Initial commit

This is the initial import of the originally scanned code
from AMD.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>

161 files changed, 312728 insertions, 0 deletions

diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..152c324
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,80 @@
+LIBNAME=bin/libumr.a
+BINNAME=bin/umr
+
+CFLAGS += -Wall -W -O2 -g3 -Isrc/ -DPIC -fPIC
+
+REV=$(shell git rev-parse HEAD | cut -b1-12)
+VER_MAJOR=1
+VER_MINOR=0
+CFLAGS+=-DUMR_BUILD_REV=\"${REV}\" -DUMR_BUILD_VER=\"${VER_MAJOR}.${VER_MINOR}\"
+
+
+PREFIX ?= /usr/local/
+
+#library objects (ASICs blocks)
+LIBOBJS=\
+src/lib/asic/bonaire.o src/lib/asic/carrizo.o src/lib/asic/fiji.o \
+src/lib/asic/hainan.o src/lib/asic/kaveri.o src/lib/asic/oland.o \
+src/lib/asic/pitcairn.o src/lib/asic/polaris10.o src/lib/asic/polaris11.o \
+src/lib/asic/polaris12.o src/lib/asic/stoney.o src/lib/asic/tahiti.o \
+src/lib/asic/tonga.o src/lib/asic/topaz.o src/lib/asic/verde.o \
+\
+src/lib/bitfield_print.o src/lib/close_asic.o src/lib/create_asic_helper.o \
+src/lib/discover_by_did.o src/lib/discover_by_name.o src/lib/discover.o src/lib/dump_ib.o \
+src/lib/find_reg.o src/lib/grab_frame.o src/lib/mmio.o src/lib/query_drm.o \
+src/lib/read_sgpr.o src/lib/read_vram.o src/lib/ring_decode.o src/lib/scan_config.o \
+src/lib/wave_status.o \
+\
+src/lib/ip/bif30.o src/lib/ip/bif41.o src/lib/ip/bif50.o src/lib/ip/bif51.o \
+\
+src/lib/ip/dce100.o src/lib/ip/dce110.o src/lib/ip/dce112.o src/lib/ip/dce60.o \
+src/lib/ip/dce80.o \
+\
+src/lib/ip/gfx60.o src/lib/ip/gfx70.o src/lib/ip/gfx72.o src/lib/ip/gfx80.o \
+src/lib/ip/gfx81.o \
+\
+src/lib/ip/gmc60.o src/lib/ip/gmc70.o src/lib/ip/gmc71.o src/lib/ip/gmc81.o \
+src/lib/ip/gmc82.o \
+\
+src/lib/ip/oss10.o src/lib/ip/oss20.o src/lib/ip/oss30.o \
+\
+src/lib/ip/smu60.o src/lib/ip/smu700.o src/lib/ip/smu701.o src/lib/ip/smu710.o \
+src/lib/ip/smu711.o src/lib/ip/smu712.o src/lib/ip/smu713.o src/lib/ip/smu80.o \
+\
+src/lib/ip/uvd40.o src/lib/ip/uvd42.o src/lib/ip/uvd5.o src/lib/ip/uvd6.o \
+\
+src/lib/ip/vce1.o src/lib/ip/vce2.o src/lib/ip/vce3.o
+
+
+#application objects
+APPOBJS=src/app/main.o src/app/print.o src/app/print_config.o \
+src/app/ring_read.o src/app/scan.o src/app/scan_log.o \
+src/app/top.o src/app/umr_lookup.o src/app/set_bit.o src/app/set_reg.o src/app/print_waves.o \
+src/app/enum.o
+
+${BINNAME}: ${LIBNAME} ${APPOBJS}
+	${CC} ${CFLAGS} ${APPOBJS} ${LIBNAME} -lpciaccess -lncurses -o $@
+
+${LIBOBJS}: src/umr.h
+${APPOBJS}: src/umr.h
+
+${LIBNAME}: ${LIBOBJS}
+	${AR} ${ARFLAGS} $@ $^
+
+.PHONY: install
+install: bin/umr
+	mkdir -p ${PREFIX}/bin
+	mkdir -p ${PREFIX}/share/man/man1
+	install ${BINNAME} ${PREFIX}/bin/
+	install doc/umr.1 ${PREFIX}/share/man/man1/
+
+.PHONY: installlib
+installlib: ${LIBOBJS}
+	mkdir -p ${PREFIX}/include
+	mkdir -p ${PREFIX}/lib
+	install src/*.h ${PREFIX}/include/
+	install ${LIBNAME} ${PREFIX}/lib/
+
+.PHONY: clean
+clean:
+	rm -f bin/umr ${LIBNAME} ${LIBOBJS} ${APPOBJS}
diff --git a/README b/README
new file mode 100644
index 0000000..59dbe84
--- /dev/null
+++ b/README
@@ -0,0 +1,177 @@
+UserMode Register Debugger for AMDGPU Hardware
+Copyright (c) 2017 AMD Inc.
+
+Introduction
+-------------
+
+umr is a userspace debugging and diagnostic tool for AMD GPUs using
+the AMDGPU kernel driver with limited support for driverless debugging
+(via PCI direct access).
+
+The tool allows reading/writing MMIO registers, analyzing wavefronts,
+ring contents, as well as performance tracking.  It supports hardware
+from SI based hardware onwards.
+
+The tool is open source and hosted at
+
+    : TBD
+
+Users may report bugs, feedback, and submit patches to the amd-gfx
+mailing list at:
+
+    https://lists.freedesktop.org/mailman/listinfo/amd-gfx
+
+Building
+---------
+
+To build umr you will need pciaccess and ncurses headers.  Which are
+available in both Fedora and Ubuntu (as well as other distributions).
+To build simply invoke the make command
+
+    $ make
+
+and then
+
+    $ make install
+
+To install it.  If you plan to use it as a non-root user you may
+want to add the setuid bit
+
+    $ chmod +s `which umr`
+
+NOTE:  Allowing untrusted users access to umr may lead to system
+comprimises, instability, and hardware damage.  Do not setuid this
+tool on multi-user systems.
+
+Running umr
+------------
+
+umr is a command line which parses options and commands from the
+command line supplied.  It processes arguments left to right which
+means that options specified after a command do not affect the command
+for instance
+
+    $ umr -r *.dce100.mmFOO -O bits
+
+is not the same as
+
+    $ umr -O bits -r *.dce100.mmFOO
+
+Users can get help with command options via
+
+    $ umr -h
+
+or
+    $ man umr
+
+Options can be stacked with commas.  For instance:
+
+    $ umr -O bits,follow,empty_log -ls
+
+Selecting Hardware
+-------------------
+
+On machines with more than one AMDGPU device umr can be instructed
+which to look at.  If the driver is loaded and display attached
+the --instance option can select a device.  The devices can be listed
+with the --enumerate option.  Once one is picked the number can be used
+for instance:
+
+    $ umr -i 1 -s uvd6
+
+Would scan the uvd6 block on the second AMDGPU device.
+
+If the AMDGPU driver is not loaded you can specify a device by name
+or PCI device ID for instance:
+
+    $ umr -f tahiti -s uvd4
+
+or
+
+    $ umr -f 0x6780 -s uvd4
+
+Would read the uvd4 block from the first tahiti device in the system.
+Note that the '-f' command does not support two instances of the same
+hardware.  To choose between those the --instance command needs to be
+used.
+
+
+Quick Guide
+------------
+
+To read registers you can use various commands.  To scan an entire
+IP block use the --scan command
+
+    $ umr --scan uvd6
+
+Would scan and print all of the MMIO registers for the uvd6 block (on
+the default instance 0 device).  This can be specifed multiple times
+to read multiple blocks, for instance:
+
+    $ umr --scan uvd6 --scan dce110
+
+To read a specific register the --read command can be used:
+
+    $ umr -r tahiti.uvd4.mmUVD_VCPU_CNTL
+
+Would read the mmUVD_VCPU_CNTL register of the uvd4 block.  The asic
+name can be replaced with * to simplify scripting, for instance:
+
+    $ umr -r *.uvd4.mmUVD_VCPU_CNTL
+
+With both --scan and --read the bits option can be used to decode
+bitfields.  For instance,
+
+    $ umr -O bits -s uvd6
+
+Would scan the uvd6 block and print out all of the registers and their
+bitfield decodings.
+
+Registers can be written with --write and --writebit commands.
+
+To read ring contents the --ring command can be used.  Optionally,
+ranges can be specified or by default it will read from 32 words before
+the read pointer upto the write pointer.
+
+The kernel supports a MMIO tracepoint and can be read with the
+--logscan command.  Normally, one would want to follow it so the
+typical use would be
+
+    $ umr -O bits,follow,empty_log -ls
+
+GPU Utilization
+----------------
+
+The GPU utilization can be summarize with the --top command.  It is
+an interactive mode of umr which samples various registers and
+prints out the counts.
+
+When this mode is active the frequency of sampling can be changed by
+hitting '1'.  It defaults to 100Hz but can be increased to 1000Hz.  The
+frequency of reporting can be changed with '2' from 1Hz to 10Hz.
+
+Various fields can be enabled with keys indicated at the bottom of the
+screen.  When all the desired options are enabled the 'W' (upper case)
+can be hit to write the configuration to disk.
+
+The fields can be logged to disk by hitting 'l' to toggle the logging
+on and off.  By default, it will write to ~/umr.log in comma separated
+value format.  It appends to the file so it can be toggled on and off
+as a test is instrumented.  The first column includes an uptime counter
+so it can be used to sort the output.
+
+The use_colour (also: use_color) option can be specified to colourize
+the display making seeing busy bits easier to see.
+
+Wavefront Debugging
+--------------------
+
+The status of valid wavefronts can be displayed with the --waves
+command.  The bits option enables bitfield decoding.  Normally,
+the colums would be pretty printed:
+
+    $ umr -wa | column -t
+
+Note that wave fetching is unstable if GFX PG is enabled as reading
+some of the wave related registers can lead to GPU hangs while the GFX
+block is transitioning.
diff --git a/bin/.keep b/bin/.keep
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/bin/.keep
diff --git a/doc/umr.1 b/doc/umr.1
new file mode 100644
index 0000000..97a205e
--- /dev/null
+++ b/doc/umr.1
@@ -0,0 +1,141 @@
+.TH UMR 1 "January 2017" "AMD (c) 2017" "User Manuals"
+.SH NAME
+umr \- AMDGPU Userspace Register Debugger
+.SH DESCRIPTION
+.B umr
+is a tool to read and display, as well as write to AMDGPU device
+MMIO, PCIE, SMC, and DIDT registers via userspace.  It can autodetect
+and scan AMDGPU devices (SI and up).
+.SH OPTIONS
+.IP "--instance, -i <number>"
+Pick a device instance to work with.  Defaults to the 0'th device.  The instance
+refers to a directory under
+.B /sys/kernel/debug/dri/
+where 0 is the first card probed.
+.IP "--bank, -b <se_bank> <sh_bank> <instance>"
+Select a GFX INSTANCE/SH/SE bank in decimal.  Can use 'x' to denote a broadcast selection.
+.IP "--force -f <number>"
+Force a PCIE Device ID in hex or by asic name.  This is used in case the amdgpu driver
+is not yet loaded or a display is not yet attached.
+.IP "--print, -p"
+Enable scanning and printing all registers.  Defaults to off as it can
+be very verbose.
+.IP "--config, -c"
+Print out configuation data read from kernel driver.
+.IP "--enumerate, -e"
+Enumerate all AMDGPU supported devices.
+.IP "--list-blocks -lb"
+List all blocks attached to the asic that has been detected.
+.IP "--list-regs, -lr <string>"
+List all registers in an IP block (can use '-O bits' to list bitfields)
+.IP "--lookup, -lu <address> <number>"
+Look up an MMIO register by address and bitfield decode the value specified.
+.IP "--write -w <string> <number>"
+Write a value specified in hex to a register specified with a complete
+register path in the form <
+.B asicname.ipname.regname
+>.  The value of asicname can be
+.B *
+to simplify scripting.  This command can be used multiple times to
+write to multiple registers in a single invocation.
+.IP "--writebit -wb <string> <number>"
+Write a value specified in hex to a register bitfield specified with a
+complete register path as in the
+.B --write
+command.
+.IP "--read, -r <string>"
+Read a value from a register specified by a register path to stdout.
+This command uses the same syntax as the
+.B --write
+command but also allows
+.B *
+for the regname field.
+.IP "--scan, -s <string>"
+Scan and print an IP block by name, for example,
+.B uvd5.
+Can be used multiple times in a single invocation.
+.IP "--ring, -R <string>(from:to)"
+Read the contents of a ring named by the string without the
+.B amdgpu_ring_
+prefix.  By default it will read and display the entire ring.  A
+starting and ending address can be specified in decimal or a '.' can
+be used to indicate relative to the current
+.B wptr
+pointer.  For example, "-R gfx" would read the entire gfx ring,
+"-R gfx[0:16]" would display the contents from 0 to 16 inclusively, and
+"-R gfx[.]" or "-R gfx[.:.]" would display the last 32 words relative
+to rptr.
+.IP "--logscan, -ls"
+Read and display contents of the MMIO register log.  Usually specified
+with '-O bits,follow,empty_log' to enable continual dumping of the trace
+log.
+.IP "--top, -t"
+Summarize GPU utilization.  Can select a SE block with --bank.  Relevant
+options that apply are:
+.B use_colour
+and
+.B use_pci
+.
+.IP "--waves, -wa"
+Print out information about any active CU waves.  Note that if GFX power gating
+is enabled this command may result in a GPU hang.  It's unlikely unless you're
+invoking it very rapidly.  Unlike the wave count reading in --top this command
+will operate regardless of whether GFX PG is enabled or not.  Can use
+.B bits
+to decode the wave bitfields.
+
+.IP "--option, -O <string>[,<string>,...]"
+Specify options to the tool.  Multiple options can be specified as comma
+separated strings.
+
+.B quiet
+     Disable various informative but not required (for functionality) outputs.
+
+.B risky
+     enables scanning risky ip blocks (such as GFX).  Specify twice for SMU
+     blocks.
+
+.B read_smc
+     Enable scanning of SMC registers.
+
+.B bits
+     enables displaying bitfields for scanned blocks.
+
+.B bitsfull
+     enables displaying bitfields using their entire path for scanned blocks.
+
+.B empty_log
+     Empties the MMIO log after reading it.
+
+.B follow
+     Causes the --logscan and --top commands to repeatedly produce output without
+     exiting.
+
+.B named
+     Causes --read to print out the register name with the register
+     value.
+
+.B many
+     Allows matching regname openly (used with --read) and implies
+     "named".  For instance "*.dce100.CRTC" would match any register that
+     contains the fragment "CRTC" in the name.
+
+.B use_pci
+     Enable PCI access for MMIO instead of using debugfs.  Used by the --read,
+     --scan, --top, --write, and --write-bit commands.  Does not currently
+     support multiple instances of the same GPU (PCI device ID).  Note that access
+     to non-MMIO registers might be disabled when using this flag.
+
+.B use_colour
+     Enable colour output for --top command, scales from blue, green, yellow, to red.  Also
+     accepted is 'use_color'.
+
+.SH "Notes"
+
+- The "Waves" field in the DRM section of --top only works if GFX PG has been disabled.  Otherwise,
+GPU hangs occur frequently.  When PG is enabled it will read a constant 0.
+
+.SH "Environmental Variables"
+
+.B UMR_LOGGER
+    Directory to output "umr.log" file when capturing samples with the --top command.
diff --git a/scripts/parse_bits.sh b/scripts/parse_bits.sh
new file mode 100755
index 0000000..ebaa6ae
--- /dev/null
+++ b/scripts/parse_bits.sh
@@ -0,0 +1,119 @@
+#!/bin/bash
+
+# this script generates the *_bits.i and *_regs.i files for SI through VI
+# ASICs
+
+#this is the path to the tree (not necessarily the one running on your host)
+pk=/nas/work/repos/linux/drivers/gpu/drm/amd/include/asic_reg/
+
+# parse_bits /path/to/asic_reg/foo/block /path/to/umr/file
+parse_bits() {
+regfile=$1_d.h
+bitfile=$1_sh_mask.h
+
+if [ ! -f ${regfile} ]; then printf "Cannot find reg file ${regfile}\n"; exit 1; fi
+if [ ! -f ${bitfile} ]; then printf "Cannot find bit file ${bitfile}\n"; exit 1; fi
+
+grep -E "(mm|ix)" ${regfile} | sort -u -k 3 | (while read line; do
+	reg=`echo "${line}" | awk '{ print $2; }'`
+	addr=`echo "${line}" | awk '{ print $3; }'`
+	regclean=`echo ${reg} | sed -e 's/^mm//g' | sed -e 's/^ix//g'`
+	`echo ${reg} | grep '^mm' > /dev/null`
+	if [ $? != 0 ]; then class="SMC"; else class="MMIO"; fi
+	printf "Parsing ${regclean}..."
+	if grep " ${regclean}__" ${bitfile} > /dev/null; then
+		# has bit definitions ...
+		# output reg declaration
+		printf "\t{ \"${reg}\", REG_${class}, ${addr}, &${reg}[0], sizeof(${reg})/sizeof(${reg}[0]), 0, 0 },\n" >> /tmp/bits.1
+		# now we parse out bits
+		printf "static struct umr_bitfield ${reg}[] = {\n" >> /tmp/bits.2
+		printf "has bits... hold on..."
+		grep " ${regclean}__" ${bitfile} | grep "_MASK " | grep -v "__SHIFT " | ( while read bitline; do
+			bitmask=`echo ${bitline} | awk '{ print $3; }'`
+			bitname=`echo ${bitline} | awk '{ print $2; }'`
+			bitnameclean=`echo ${bitname} | sed -e "s/^${regclean}__//" | sed -e 's/_MASK$//'`
+			bitidx=`/tmp/countbits ${bitmask}`
+			printf "\t { \"${bitnameclean}\", ${bitidx}, &umr_bitfield_default },\n" >> /tmp/bits.2
+		done; )
+		printf "};\n" >> /tmp/bits.2
+	else
+		printf "\t{ \"${reg}\", REG_${class}, ${addr}, NULL, 0, 0, 0 },\n" >> /tmp/bits.1
+	fi
+	printf "done.\n";
+done; )
+	mv -vf /tmp/bits.1 $2_regs.i
+	mv -vf /tmp/bits.2 $2_bits.i
+}
+
+if [ ! -d ${pk} ]; then
+	printf "The kernel headers were not found in [${pk}]\n"
+	exit 1
+fi
+
+rm -f /tmp/bits.1 /tmp/bits.2 /tmp/countbits*
+
+(cat <<ENDCB
+#include <stdio.h>
+int main(int argc, char **argv)
+{
+	unsigned long value, x;
+	if (sscanf(argv[1], "0x%08lx", &value)) {
+		x = 0;
+		while (!(value & 1) && x < 32) { x++; value >>= 1; }
+		printf("%lu, ", x);
+		while ((value & 1) && x < 32) { x++; value >>= 1; }
+		printf("%lu", x-1);
+	}
+	return 0;
+}
+ENDCB
+) > /tmp/countbits.c
+gcc /tmp/countbits.c -o /tmp/countbits
+
+if [ "$1" == "" ]; then
+	parse_bits ${pk}/smu/smu_6_0 src/lib/ip/smu60
+	parse_bits ${pk}/smu/smu_7_0_0 src/lib/ip/smu700
+	parse_bits ${pk}/smu/smu_7_0_1 src/lib/ip/smu701
+	parse_bits ${pk}/smu/smu_7_1_0 src/lib/ip/smu710
+	parse_bits ${pk}/smu/smu_7_1_1 src/lib/ip/smu711
+	parse_bits ${pk}/smu/smu_7_1_2 src/lib/ip/smu712
+	parse_bits ${pk}/smu/smu_7_1_3 src/lib/ip/smu713
+	parse_bits ${pk}/smu/smu_8_0 src/lib/ip/smu80
+
+	parse_bits ${pk}/oss/oss_1_0 src/lib/ip/oss10
+	parse_bits ${pk}/oss/oss_2_0 src/lib/ip/oss20
+	parse_bits ${pk}/oss/oss_3_0 src/lib/ip/oss30
+
+	parse_bits ${pk}/gmc/gmc_6_0 src/lib/ip/gmc60
+	parse_bits ${pk}/gmc/gmc_7_0 src/lib/ip/gmc70
+	parse_bits ${pk}/gmc/gmc_7_1 src/lib/ip/gmc71
+	parse_bits ${pk}/gmc/gmc_8_1 src/lib/ip/gmc81
+	parse_bits ${pk}/gmc/gmc_8_2 src/lib/ip/gmc82
+
+	parse_bits ${pk}/dce/dce_6_0 src/lib/ip/dce60
+	parse_bits ${pk}/dce/dce_8_0 src/lib/ip/dce80
+	parse_bits ${pk}/dce/dce_10_0 src/lib/ip/dce100
+	parse_bits ${pk}/dce/dce_11_0 src/lib/ip/dce110
+	parse_bits ${pk}/dce/dce_11_2 src/lib/ip/dce112
+
+	parse_bits ${pk}/gca/gfx_6_0 src/lib/ip/gfx60
+	parse_bits ${pk}/gca/gfx_7_2 src/lib/ip/gfx72
+	parse_bits ${pk}/gca/gfx_8_0 src/lib/ip/gfx80
+	parse_bits ${pk}/gca/gfx_8_1 src/lib/ip/gfx81
+
+	parse_bits ${pk}/uvd/uvd_4_0 src/lib/ip/uvd40
+	parse_bits ${pk}/uvd/uvd_4_2 src/lib/ip/uvd42
+	parse_bits ${pk}/uvd/uvd_5_0 src/lib/ip/uvd50
+	parse_bits ${pk}/uvd/uvd_6_0 src/lib/ip/uvd60
+
+	parse_bits ${pk}/vce/vce_1_0 src/lib/ip/vce10
+	parse_bits ${pk}/vce/vce_2_0 src/lib/ip/vce20
+	parse_bits ${pk}/vce/vce_3_0 src/lib/ip/vce30
+
+	parse_bits ${pk}/bif/bif_3_0 src/lib/ip/bif30
+	parse_bits ${pk}/bif/bif_4_1 src/lib/ip/bif41
+	parse_bits ${pk}/bif/bif_5_0 src/lib/ip/bif50
+	parse_bits ${pk}/bif/bif_5_1 src/lib/ip/bif51;
+else
+	parse_bits ${pk}/$1 src/lib/ip/$2
+fi
diff --git a/src/app/enum.c b/src/app/enum.c
new file mode 100644
index 0000000..b7363d6
--- /dev/null
+++ b/src/app/enum.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+
+#define MAX_DEV 16
+
+struct gpus {
+	struct umr_asic *asic;
+	struct pci_device pcopy;
+	int instance;
+};
+
+void umr_enumerate_devices(void)
+{
+	struct gpus asics[MAX_DEV];
+	struct umr_options options;
+	int devices, x, y;
+	struct pci_device_iterator *pci_iter;
+	struct pci_device *pdevice;
+	char path[128];
+	FILE *dri;
+
+	devices = 0;
+	memset(asics, 0, sizeof(asics));
+	memset(&options, 0, sizeof(options));
+	options.quiet = 1;
+
+	// scan PCI space for all AMDGPU devices...
+	pci_system_init();
+	pci_iter = pci_id_match_iterator_create(NULL);
+	if (!pci_iter) {
+		fprintf(stderr, "Cannot create PCI iterator");
+		return;
+	}
+	do {
+		x = 0;
+		do {
+			pdevice = pci_device_next(pci_iter);
+		} while (pdevice && pdevice->vendor_id != 0x1002);
+
+		if (pdevice && (asics[devices].asic = umr_discover_asic_by_did(&options, pdevice->device_id))) {
+			asics[devices].instance = -1;
+			asics[devices].asic->pci.pdevice = &asics[devices].pcopy;
+			asics[devices++].pcopy = *pdevice;
+			x = 1;
+		}
+	} while (pdevice && devices < MAX_DEV);
+
+	// now try to match devices against instances
+	for (y = 0; y < MAX_DEV; y++) {
+		snprintf(path, sizeof(path)-1, "/sys/kernel/debug/dri/%d/name", y);
+		dri = fopen(path, "r");
+		if (dri) {
+			unsigned dummy, domain, dev, bus, func;
+			int ok = 0;
+			if (fscanf(dri, "amdgpu %04x:%02u:%02u.%01u pci:%04x:%02u:%02u.%01u",
+				&dummy, &dummy, &dummy, &dummy,
+				&domain, &bus, &dev, &func) == 8) {
+				ok = 1;
+			}
+			// try a second time (for kernels > 4.7)
+			if (!ok) {
+				fseek(dri, 0, SEEK_SET);
+				if (fscanf(dri, "amdgpu dev=%04x:%02u:%02u.%01u master=pci:%04x:%02u:%02u.%01u",
+					&dummy, &dummy, &dummy, &dummy,
+					&domain, &bus, &dev, &func) == 8) {
+					ok = 1;
+				}
+			}
+			fclose(dri);
+
+			if (ok) {
+				for (x = 0; x < devices; x++) {
+					if (
+					    asics[x].pcopy.domain == domain &&
+					    asics[x].pcopy.bus == bus &&
+					    asics[x].pcopy.dev == dev &&
+					    asics[x].pcopy.func == func) {
+						asics[x].instance = y;
+						asics[x].asic->instance = y;
+						umr_scan_config(asics[x].asic);
+					}
+
+				}
+			}
+		}
+	}
+
+	for (x = 0; x < devices; x++) {
+		printf("gpu #%d => %s (instance: %d)\n", x, asics[x].asic->asicname, asics[x].instance);
+		if (asics[x].instance != -1)
+			umr_print_config(asics[x].asic);
+		umr_close_asic(asics[x].asic);
+	}
+
+}
diff --git a/src/app/main.c b/src/app/main.c
new file mode 100644
index 0000000..427a39e
--- /dev/null
+++ b/src/app/main.c
@@ -0,0 +1,365 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <signal.h>
+#include <time.h>
+
+static int quit;
+
+void sigint(int signo)
+{
+	if (signo == SIGINT)
+		quit = 1;
+}
+
+struct umr_options options;
+
+static struct umr_asic *get_asic(void)
+{
+	struct umr_asic *asic;
+	asic = umr_discover_asic(&options);
+	if (!asic) {
+		printf("ASIC not found (instance=%d, did=%08lx)\n", options.instance, (unsigned long)options.forcedid);
+		exit(EXIT_FAILURE);
+	}
+	return asic;
+}
+
+static void parse_options(char *str)
+{
+	char option[64], *p;
+
+	while (*str) {
+		p = &option[0];
+		while (*str && *str != ',' && p != &option[sizeof(option)-1])
+			*p++ = *str++;
+		*p = 0;
+		if (*str == ',')
+			++str;
+		if (!strcmp(option, "risky")) {
+			options.risky++;
+		} else if (!strcmp(option, "named")) {
+			options.named = 1;
+		} else if (!strcmp(option, "many")) {
+			options.named = 1;
+			options.many = 1;
+		} else if (!strcmp(option, "bits")) {
+			options.bitfields = 1;
+		} else if (!strcmp(option, "empty_log")) {
+			options.empty_log = 1;
+		} else if (!strcmp(option, "follow")) {
+			options.follow = 1;
+		} else if (!strcmp(option, "use_pci")) {
+			options.use_pci = 1;
+		} else if (!strcmp(option, "use_colour") || !strcmp(option, "use_color")) {
+			options.use_colour = 1;
+		} else if (!strcmp(option, "bitsfull")) {
+			options.bitfields = 1;
+			options.bitfields_full = 1;
+		} else if (!strcmp(option, "read_smc")) {
+			options.read_smc = 1;
+		} else if (!strcmp(option, "quiet")) {
+			options.quiet = 1;
+		} else {
+			printf("error: Unknown option [%s]\n", option);
+			exit(EXIT_FAILURE);
+		}
+	}
+}
+
+
+int main(int argc, char **argv)
+{
+	int i, j, k, l;
+	struct umr_asic *asic;
+	char *str, *str2, asicname[256], ipname[256], regname[256];
+	struct timespec req;
+
+	memset(&options, 0, sizeof options);
+
+	/* defaults */
+	asic = NULL;
+	options.need_scan = 1;
+	options.forcedid = -1;
+	options.scanblock = "";
+
+	for (i = 1; i < argc; i++) {
+		if (!strcmp(argv[i], "--instance") || !strcmp(argv[i], "-i")) {
+			if (i + 1 < argc) {
+				options.instance = atoi(argv[i+1]);
+				++i;
+			} else {
+				printf("--instance requires a number\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--bank") || !strcmp(argv[i], "-b")) {
+			if (!asic)
+				asic = get_asic();
+			if (i + 3 < argc) {
+				options.se_bank = argv[i+1][0] == 'x' ? 0x3FF : atoi(argv[i+1]);
+				options.sh_bank = argv[i+2][0] == 'x' ? 0x3FF : atoi(argv[i+2]);
+				options.instance_bank = argv[i+3][0] == 'x' ? 0x3FF : atoi(argv[i+3]);
+				if ((options.se_bank != 0x3FF && options.se_bank >= asic->config.gfx.max_shader_engines) ||
+				    (options.sh_bank != 0x3FF && options.sh_bank >= asic->config.gfx.max_sh_per_se)) {
+					printf("Invalid bank selection for specific ASIC\n");
+					return EXIT_FAILURE;
+				}
+				options.use_bank = 1;
+				i += 3;
+			} else {
+				printf("--bank requires three parameters\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--force") || !strcmp(argv[i], "-f")) {
+			if (i + 1 < argc) {
+				if (sscanf(argv[i+1], "0x%lx", &options.forcedid) == 0) {
+					strncpy(options.dev_name, argv[i+1], sizeof(options.dev_name) - 1);
+					options.forcedid = 0;
+					options.instance = -1;
+				}
+				++i;
+			} else {
+				printf("--force requires a number/name\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--print") || !strcmp(argv[i], "-p")) {
+			options.print = 1;
+			options.need_scan = 1;
+		} else if (!strcmp(argv[i], "--config") || !strcmp(argv[i], "-c")) {
+			if (!asic)
+				asic = get_asic();
+			umr_print_config(asic);
+		} else if (!strcmp(argv[i], "--list-blocks") || !strcmp(argv[i], "-lb")) {
+			if (!asic)
+				asic = get_asic();
+			for (j = 0; j < asic->no_blocks; j++)
+				printf("\t%s.%s\n", asic->asicname, asic->blocks[j]->ipname);
+		} else if (!strcmp(argv[i], "--list-regs") || !strcmp(argv[i], "-lr")) {
+			if (i + 1 < argc) {
+				if (!asic)
+					asic = get_asic();
+				for (j = 0; j < asic->no_blocks; j++)
+					if (!strcmp(asic->blocks[j]->ipname, argv[i+1]))
+						for (k = 0; k < asic->blocks[j]->no_regs; k++) {
+							printf("\t%s.%s.%s => 0x%05lx\n", asic->asicname, asic->blocks[j]->ipname, asic->blocks[j]->regs[k].regname, (unsigned long)asic->blocks[j]->regs[k].addr);
+							if (options.bitfields) {
+								for (l = 0; l < asic->blocks[j]->regs[k].no_bits; l++)
+									printf("\t\t%s.%s.%s.%s[%d:%d]\n", asic->asicname, asic->blocks[j]->ipname, asic->blocks[j]->regs[k].regname, asic->blocks[j]->regs[k].bits[l].regname, asic->blocks[j]->regs[k].bits[l].start, asic->blocks[j]->regs[k].bits[l].stop);
+							}
+						}
+				++i;
+			} else {
+				printf("--list-regs requires one parameter\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--lookup") || !strcmp(argv[i], "-lu")) {
+			if (i + 2 < argc) {
+				int tmp = options.bitfields;
+				if (!asic)
+					asic = get_asic();
+				options.bitfields = 1;
+				umr_lookup(asic, argv[i+1], argv[i+2]);
+				options.bitfields = tmp;
+				i += 2;
+			}
+		} else if (!strcmp(argv[i], "--write") || !strcmp(argv[i], "-w")) {
+			if (i + 2 < argc) {
+				if (!asic)
+					asic = get_asic();
+				umr_set_register(asic, argv[i+1], argv[i+2]);
+				i += 2;
+				options.need_scan = 0;
+			} else {
+				printf("--write requires two parameters\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--writebit") || !strcmp(argv[i], "-wb")) {
+			if (i + 2 < argc) {
+				if (!asic)
+					asic = get_asic();
+				umr_set_register_bit(asic, argv[i+1], argv[i+2]);
+				i += 2;
+				options.need_scan = 0;
+			} else {
+				printf("--write requires two parameters\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--waves") || !strcmp(argv[i], "-wa")) {
+			if (!asic)
+				asic = get_asic();
+			umr_print_waves(asic);
+		} else if (!strcmp(argv[i], "--scan") || !strcmp(argv[i], "-s")) {
+			if (i + 1 < argc) {
+				if (!asic)
+					asic = get_asic();
+				if (!umr_scan_asic(asic, "", argv[i+1], ""))
+					umr_print_asic(asic, argv[i+1]);
+				++i;
+				options.need_scan = 0;
+			} else {
+				printf("--scan requires one parameter\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--read") || !strcmp(argv[i], "-r")) {
+			if (i + 1 < argc) {
+				if (!asic)
+					asic = get_asic();
+				str = strstr(argv[i+1], ".");
+				str2 = strstr(str+1, ".");
+				if (str && str2) {
+					memset(asicname, 0, sizeof asicname);
+					memset(ipname, 0, sizeof ipname);
+					memset(regname, 0, sizeof regname);
+					str[0] = 0;
+					str2[0] = 0;
+					strcpy(asicname, argv[i+1]);
+					strcpy(ipname, str+1);
+					strcpy(regname, str2+1);
+				} else {
+					printf("Invalid asicname.ipname.regname syntax\n");
+					return EXIT_FAILURE;
+				}
+				umr_scan_asic(asic, asicname, ipname, regname);
+				++i;
+				options.need_scan = 0;
+			} else {
+				printf("--read requires one parameter\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--ring") || !strcmp(argv[i], "-R")) {
+			if (i + 1 < argc) {
+				if (!asic)
+					asic = get_asic();
+				umr_read_ring(asic, argv[i+1]);
+				++i;
+			} else {
+				printf("--ring requires one parameter\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--logscan") || !strcmp(argv[i], "-ls")) {
+			if (!asic)
+				asic = get_asic();
+			if (options.follow) {
+				signal(SIGINT, sigint);
+				system("echo 1 > /sys/kernel/debug/tracing/events/amdgpu/amdgpu_mm_wreg/enable");
+				system("echo 1 > /sys/kernel/debug/tracing/events/amdgpu/amdgpu_mm_rreg/enable");
+				req.tv_sec = 0;
+				req.tv_nsec = 1000000000/10; // 100ms
+				while (!quit) {
+					nanosleep(&req, NULL);
+					umr_scan_log(asic);
+				}
+				system("echo 0 > /sys/kernel/debug/tracing/events/amdgpu/amdgpu_mm_wreg/enable");
+				system("echo 0 > /sys/kernel/debug/tracing/events/amdgpu/amdgpu_mm_rreg/enable");
+			} else {
+				umr_scan_log(asic);
+			}
+		} else if (!strcmp(argv[i], "--top") || !strcmp(argv[i], "-t")) {
+			if (!asic)
+				asic = get_asic();
+			umr_top(asic);
+		} else if (!strcmp(argv[i], "--enumerate") || !strcmp(argv[i], "-e")) {
+			umr_enumerate_devices();
+			return 0;
+		} else if (!strcmp(argv[i], "--grab-frame") || !strcmp(argv[i], "-gf")) {
+			void *fb;
+			uint32_t size;
+			if (i + 1 < argc) {
+				if (!asic)
+					asic = get_asic();
+				umr_grab_framebuffer(asic, &fb, &size);
+				if (fb) {
+					FILE *out = fopen(argv[i+1], "wb");
+					printf("Saving to %s\n", argv[i+1]);
+					if (!out) { perror("Cannot open output"); return EXIT_FAILURE; }
+					fwrite(fb, 1, size, out);
+					fclose(out);
+				}
+				++i;
+			} else {
+				printf("--grab-frame requires one parameter\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--option") || !strcmp(argv[i], "-O")) {
+			if (i + 1 < argc) {
+				parse_options(argv[i+1]);
+				++i;
+			} else {
+				printf("--option requires one parameter\n");
+				return EXIT_FAILURE;
+			}
+		} else if (!strcmp(argv[i], "--help") || !strcmp(argv[i], "-h")) {
+			printf("User Mode Register debugger v%s for AMDGPU devices (build: %s), Copyright (c) 2017, AMD Inc.\n"
+"\n\t--instance, -i <number>\n\t\tSelect a device instance to investigate. (default: 0)"
+	"\n\t\tThe instance is the directory name under /sys/kernel/debug/dri/"
+	"\n\t\tof the card you want to work with.\n"
+"\n\t--bank, -b <se_bank> <sh_bank> <instance>\n\t\tSelect a GFX INSTANCE/SH/SE bank in decimal. Can use 'x' to denote broadcast.\n"
+"\n\t--force, -f <number>\n\t\tForce a PCIE DID number in hex or asic name.  Useful if amdgpu is"
+	"\n\t\tnot loaded or a display is not attached.\n"
+"\n\t--print, -p\n\t\tEnable dumping of all device registers. (default: off)\n"
+"\n\t--config, -c\n\t\tPrint out configuation data read from kernel driver.\n"
+"\n\t--enumerate, -e\n\t\tEnumerate all AMDGPU devices detected.\n"
+"\n\t--list-blocks, -lb\n\t\tList IP blocks discovered for this device.\n"
+"\n\t--list-regs, -lr <string>\n\t\tList registers for a given IP block (can use '-O bits' to list bitfields).\n"
+"\n\t--lookup, -lu <address> <value>\n\t\tLook up bit decoding of an MMIO register by address.\n"
+"\n\t--write, -w <address> <number>\n\t\tWrite a value in hex to a register specified as a register path in the"
+	"\n\t\tform <asicname.ipname.regname>.  For instance \"tonga.uvd5.mmUVD_SOFT_RESET\"."
+	"\n\t\tCan be used multiple times to set multiple registers.  You can"
+	"\n\t\tspecify * for asicname to simplify scripts.\n"
+"\n\t--writebit, -wb <string> <number>\n\t\tWrite a value in hex to a register bitfield specified as in --write but"
+	"\n\t\tthe addition of the bitfield name.  For instance: \"*.gfx80.mmRLC_PG_CNTL.PG_OVERRIDE\"\n"
+"\n\t--read, -r <string>\n\t\tRead a value from a register and print it to stdout.  This command"
+	"\n\t\tuses the same path notation as --write.  It also accepts * for regname.\n"
+"\n\t--scan, -s <string>\n\t\tScan and print an ip block by name, e.g. \"uvd5\".  Can be used multiple times.\n"
+"\n\t--ring, -R <string>([from:to])\n\t\tRead the contents of a ring named by the string without the amdgpu_ring_ prefix. "
+	"\n\t\tBy default it will read and display the entire ring.  A starting and ending "
+	"\n\t\taddress can be specified in decimal or a '.' can be used to indicate relative "
+	"\n\t\tto the current wptr pointer.  For example, \"-R gfx\" would read the entire gfx "
+	"\n\t\tring, \"-R gfx[0:16]\" would display the contents from 0 to 16 inclusively, and "
+	"\n\t\t\"-R gfx[.]\" or \"-R gfx[.:.]\" would display the last 32 words relative to rptr.\n"
+"\n\t--logscan, -ls\n\t\tRead and display contents of the MMIO register log (usually specified with"
+	"\n\t\t'-O bits,follow,empty_log' to continually dump the trace log.)\n"
+"\n\t--top, -t\n\t\tSummarize GPU utilization.  Can select a SE block with --bank.  Can use"
+	"\n\t\toptions 'use_colour' to colourize output and 'use_pci' to improve efficiency.\n"
+"\n\t--waves, -wa\n\t\tPrint out information about any active CU waves.  Can use '-O bits'"
+	"\n\t\tto see decoding of various wave fields.\n"
+"\n\t--option -O <string>[,<string>,...]\n\t\tEnable various flags: risky, bits, bitsfull, empty_log, follow, named, many,"
+	"\n\t\tuse_pci, use_colour, read_smc, quiet.\n"
+"\n\n", UMR_BUILD_VER, UMR_BUILD_REV);
+			exit(EXIT_SUCCESS);
+		}
+	}
+
+	if (!asic)
+		asic = get_asic();
+
+	if (options.need_scan && options.print)
+		umr_scan_asic(asic, "", "", "");
+
+	if (options.print)
+		umr_print_asic(asic, "");
+
+	umr_close_asic(asic);
+}
diff --git a/src/app/print.c b/src/app/print.c
new file mode 100644
index 0000000..3737d52
--- /dev/null
+++ b/src/app/print.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+
+void umr_print_asic(struct umr_asic *asic, char *ipname)
+{
+	int i, j, k;
+	uint32_t v;
+	for (i = 0; i < asic->no_blocks; i++) {
+		if (ipname[0] == 0 || !strcmp(ipname, asic->blocks[i]->ipname)) {
+			for (j = 0; j < asic->blocks[i]->no_regs; j++) {
+				if (asic->blocks[i]->regs[j].type == REG_SMC && !options.read_smc)
+					continue;
+				printf("%s.%s.%s%s%s == %s0x%08lx%s\n", asic->asicname, asic->blocks[i]->ipname, CYAN, asic->blocks[i]->regs[j].regname, RST, YELLOW, (unsigned long)asic->blocks[i]->regs[j].value, RST);
+				for (k = 0; k < asic->blocks[i]->regs[j].no_bits; k++) {
+					v = (1UL << (asic->blocks[i]->regs[j].bits[k].stop + 1 - asic->blocks[i]->regs[j].bits[k].start)) - 1;
+					v &= (asic->blocks[i]->regs[j].value >> asic->blocks[i]->regs[j].bits[k].start);
+					asic->blocks[i]->regs[j].bits[k].bitfield_print(asic, asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, asic->blocks[i]->regs[j].bits[k].regname, asic->blocks[i]->regs[j].bits[k].start, asic->blocks[i]->regs[j].bits[k].stop, v);
+				}
+			}
+		}
+	}
+}
diff --git a/src/app/print_config.c b/src/app/print_config.c
new file mode 100644
index 0000000..6a4bf5d
--- /dev/null
+++ b/src/app/print_config.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+
+#define p(x) printf("\t" #x " == %lu\n" , (unsigned long)asic->config. x)
+#define px(x) printf("\t" #x " == %08lx\n" , (unsigned long)asic->config. x)
+
+#define pp(x) printf("\tpci." #x " == %lu\n" , (unsigned long)asic->pci.pdevice-> x)
+#define ppx(x) printf("\tpci." #x " == %lx\n" , (unsigned long)asic->pci.pdevice-> x)
+
+#define M(x, y) { ""#x, y },
+
+struct {
+	char *name;
+	unsigned long mask;
+} cg_masks[] = {
+M(AMD_CG_SUPPORT_GFX_MGCG, 1UL << 0)
+M(AMD_CG_SUPPORT_GFX_MGLS, 1UL << 1)
+M(AMD_CG_SUPPORT_GFX_CGCG, 1UL << 2)
+M(AMD_CG_SUPPORT_GFX_CGLS, 1UL << 3)
+M(AMD_CG_SUPPORT_GFX_CGTS, 1UL << 4)
+M(AMD_CG_SUPPORT_GFX_CGTS_LS, 1UL << 5)
+M(AMD_CG_SUPPORT_GFX_CP_LS, 1UL << 6)
+M(AMD_CG_SUPPORT_GFX_RLC_LS, 1UL << 7)
+M(AMD_CG_SUPPORT_MC_LS, 1UL << 8)
+M(AMD_CG_SUPPORT_MC_MGCG, 1UL << 9)
+M(AMD_CG_SUPPORT_SDMA_LS, 1UL << 10)
+M(AMD_CG_SUPPORT_SDMA_MGCG, 1UL << 11)
+M(AMD_CG_SUPPORT_BIF_LS, 1UL << 12)
+M(AMD_CG_SUPPORT_UVD_MGCG, 1UL << 13)
+M(AMD_CG_SUPPORT_VCE_MGCG, 1UL << 14)
+M(AMD_CG_SUPPORT_HDP_LS, 1UL << 15)
+M(AMD_CG_SUPPORT_HDP_MGCG, 1UL << 16)
+M(AMD_CG_SUPPORT_ROM_MGCG, 1UL << 17)
+{ NULL, 0, },
+};
+
+struct {
+	char *name;
+	unsigned long mask;
+} pg_masks[] = {
+M(AMD_PG_SUPPORT_GFX_PG, 1UL << 0)
+M(AMD_PG_SUPPORT_GFX_SMG, 1UL << 1)
+M(AMD_PG_SUPPORT_GFX_DMG, 1UL << 2)
+M(AMD_PG_SUPPORT_UVD, 1UL << 3)
+M(AMD_PG_SUPPORT_VCE, 1UL << 4)
+M(AMD_PG_SUPPORT_CP, 1UL << 5)
+M(AMD_PG_SUPPORT_GDS, 1UL << 6)
+M(AMD_PG_SUPPORT_RLC_SMU_HS, 1UL << 7)
+M(AMD_PG_SUPPORT_SDMA, 1UL << 8)
+M(AMD_PG_SUPPORT_ACP, 1UL << 9)
+M(AMD_PG_SUPPORT_SAMU, 1UL << 10)
+M(AMD_PG_SUPPORT_GFX_QUICK_MG, 1UL << 11)
+M(AMD_PG_SUPPORT_GFX_PIPELINE, 1UL << 12)
+{ NULL, 0, },
+};
+
+static const struct {
+	char *name;
+	unsigned family_id;
+} family[] = {
+	{ "Sea Island", 120 },
+	{ "Kaveri", 125 },
+	{ "Volcanic Islands", 130 },
+	{ "Carrizo", 135 },
+	{ NULL, 0 },
+};
+
+void umr_print_config(struct umr_asic *asic)
+{
+	int r, x;
+
+	printf("\tumr.version == %s\n\n", UMR_BUILD_REV);
+
+	for (r = 0; asic->config.fw[r].name[0]; r++) {
+		printf("\tfw.%s == .feature==%lu .firmware==0x%08lx\n",
+			asic->config.fw[r].name,
+			(unsigned long)asic->config.fw[r].feature_version,
+			(unsigned long)asic->config.fw[r].firmware_version);
+	}
+	printf("\n");
+
+	printf("\tasic.instance == %d\n\n", asic->instance);
+	if (asic->pci.pdevice) {
+		ppx(vendor_id);
+		ppx(device_id);
+		ppx(subvendor_id);
+		ppx(subdevice_id);
+		ppx(revision);
+	}
+	printf("\n");
+
+	p(gfx.max_shader_engines);
+	p(gfx.max_tile_pipes);
+	p(gfx.max_cu_per_sh);
+	p(gfx.max_sh_per_se);
+	p(gfx.max_backends_per_se);
+	p(gfx.max_texture_channel_caches);
+	p(gfx.max_gprs);
+	p(gfx.max_gs_threads);
+	p(gfx.max_hw_contexts);
+	p(gfx.sc_prim_fifo_size_frontend);
+	p(gfx.sc_prim_fifo_size_backend);
+	p(gfx.sc_hiz_tile_fifo_size);
+	p(gfx.sc_earlyz_tile_fifo_size);
+	p(gfx.num_tile_pipes);
+	p(gfx.backend_enable_mask);
+	p(gfx.mem_max_burst_length_bytes);
+	p(gfx.mem_row_size_in_kb);
+	p(gfx.shader_engine_tile_size);
+	p(gfx.num_gpus);
+	p(gfx.multi_gpu_tile_size);
+	p(gfx.mc_arb_ramcfg);
+	p(gfx.gb_addr_config);
+	p(gfx.num_rbs);
+
+	printf("\tgfx.family = %u", asic->config.gfx.family);
+	for (x = 0; family[x].name != NULL; x++)
+		if (family[x].family_id == asic->config.gfx.family)
+			printf(", %s", family[x].name);
+	printf("\n");
+	px(gfx.rev_id);
+	px(gfx.external_rev_id);
+	px(gfx.cg_flags);
+	for (x = 0; cg_masks[x].name; x++)
+		if (asic->config.gfx.cg_flags & cg_masks[x].mask)
+			printf("\t\t%s\n", cg_masks[x].name);
+	px(gfx.pg_flags);
+	for (x = 0; pg_masks[x].name; x++)
+		if (asic->config.gfx.pg_flags & pg_masks[x].mask)
+			printf("\t\t%s\n", pg_masks[x].name);
+	printf("\n");
+}
diff --git a/src/app/print_waves.c b/src/app/print_waves.c
new file mode 100644
index 0000000..f0eeeba
--- /dev/null
+++ b/src/app/print_waves.c
@@ -0,0 +1,183 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+
+#define PP(x, y) if (col++ == 4) { col = 1; printf("\n\t"); } printf("%20s: %8u | ", #y, (unsigned)ws.x.y); 
+#define PX(x, y) if (col++ == 4) { col = 1; printf("\n\t"); } printf("%20s: %08lx | ", #y, (unsigned long)ws.x.y);
+
+#define P(x) if (col++ == 4) { col = 1; printf("\n\t"); } printf("%20s: %8u | ", #x, (unsigned)ws.x); 
+#define X(x) if (col++ == 4) { col = 1; printf("\n\t"); } printf("%20s: %08lx | ", #x, (unsigned long)ws.x);
+
+#define H(x) if (col) { printf("\n"); }; col = 0; printf("\n\n%s:\n\t", x);
+#define Hv(x, y) if (col) { printf("\n"); }; col = 0; printf("\n\n%s[%08lx]:\n\t", x, (unsigned long)y);
+
+void umr_print_waves(struct umr_asic *asic)
+{
+	uint32_t x, se, sh, cu, simd, wave, sgprs[1024], shift;
+	struct umr_wave_status ws;
+	int first = 1, col = 0;
+
+	if (asic->family <= FAMILY_CIK)
+		shift = 3;  // on SI..CIK allocations were done in 8-dword blocks
+	else
+		shift = 4;  // on VI allocations are in 16-dword blocks
+
+	for (se = 0; se < asic->config.gfx.max_shader_engines; se++)
+	for (sh = 0; sh < asic->config.gfx.max_sh_per_se; sh++)
+	for (cu = 0; cu < asic->config.gfx.max_cu_per_sh; cu++) {
+		umr_get_wave_sq_info(asic, se, sh, cu, &ws);
+		if (ws.sq_info.busy) {
+			for (simd = 0; simd < 4; simd++)
+			for (wave = 0; wave < 10; wave++) { //both simd/wave are hard coded at the moment...
+				umr_get_wave_status(asic, se, sh, cu, simd, wave, &ws);
+				if (ws.wave_status.halt || ws.wave_status.valid) {
+					// grab sgprs..
+					umr_read_sgprs(asic, &ws, &sgprs[0]);
+
+					if (!options.bitfields && first) {
+						first = 0;
+						printf("SE SH CU SIMD WAVE# WAVE_STATUS PC_HI PC_LO INST_DW0 INST_DW1 EXEC_HI EXEC_LO HW_ID GPRALLOC LDSALLOC TRAPSTS IBSTS TBA_HI TBA_LO TMA_HI TMA_LO IB_DBG0 M0\n");
+					}
+					if (!options.bitfields) {
+					printf(
+"%u %u %u %u %u " // se/sh/cu/simd/wave
+"%08lx %08lx %08lx " // wave_status pc/hi/lo
+"%08lx %08lx %08lx %08lx " // inst0/1 exec hi/lo
+"%08lx %08lx %08lx %08lx %08lx " // HW_ID GPR/LDSALLOC TRAP/IB STS
+"%08lx %08lx %08lx %08lx %08lx %08lx " // TBA_HI TBA_LO TMA_HI TMA_LO IB_DBG0 M0\n");
+"\n",
+(unsigned)se, (unsigned)sh, (unsigned)cu, (unsigned)ws.hw_id.simd_id, (unsigned)ws.hw_id.wave_id,
+(unsigned long)ws.wave_status.value, (unsigned long)ws.pc_hi, (unsigned long)ws.pc_lo,
+(unsigned long)ws.wave_inst_dw0, (unsigned long)ws.wave_inst_dw1, (unsigned long)ws.exec_hi, (unsigned long)ws.exec_lo,
+(unsigned long)ws.hw_id.value, (unsigned long)ws.gpr_alloc.value, (unsigned long)ws.lds_alloc.value, (unsigned long)ws.trapsts.value, (unsigned long)ws.ib_sts.value,
+(unsigned long)ws.tba_hi, (unsigned long)ws.tba_lo, (unsigned long)ws.tma_hi, (unsigned long)ws.tma_lo, (unsigned long)ws.ib_dbg0, (unsigned long)ws.m0
+);
+					for (x = 0; x < ((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
+						printf(">SGPRS[%u..%u] = { %08lx, %08lx, %08lx, %08lx }\n",
+							(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
+							(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
+							(unsigned long)sgprs[x],
+							(unsigned long)sgprs[x+1],
+							(unsigned long)sgprs[x+2],
+							(unsigned long)sgprs[x+3]);
+					}
+
+					if (options.bitfields) {
+						first = 0;
+						printf("\n------------------------------------------------------\nse%u.sh%u.cu%u.simd%u.wave%u\n",
+						(unsigned)se, (unsigned)sh, (unsigned)cu, (unsigned)ws.hw_id.simd_id, (unsigned)ws.hw_id.wave_id);
+
+						H("Main Registers");
+						X(pc_hi);
+						X(pc_lo);
+						X(wave_inst_dw0);
+						X(wave_inst_dw1);
+						X(exec_hi);
+						X(exec_lo);
+						X(tba_hi);
+						X(tba_lo);
+						X(tma_hi);
+						X(tma_lo);
+						X(m0);
+						X(ib_dbg0);
+
+						Hv("Wave_Status", ws.wave_status.value);
+						PP(wave_status, scc);
+						PP(wave_status, execz);
+						PP(wave_status, vccz);
+						PP(wave_status, in_tg);
+						PP(wave_status, halt);
+						PP(wave_status, valid);
+						PP(wave_status, spi_prio);
+						PP(wave_status, wave_prio);
+						PP(wave_status, trap_en);
+						PP(wave_status, ttrace_en);
+						PP(wave_status, export_rdy);
+						PP(wave_status, in_barrier);
+						PP(wave_status, trap);
+						PP(wave_status, ecc_err);
+						PP(wave_status, skip_export);
+						PP(wave_status, perf_en);
+						PP(wave_status, cond_dbg_user);
+						PP(wave_status, cond_dbg_sys);
+						PP(wave_status, data_atc);
+						PP(wave_status, inst_atc);
+						PP(wave_status, dispatch_cache_ctrl);
+						PP(wave_status, must_export);
+
+						Hv("HW_ID", ws.hw_id.value);
+						PP(hw_id, wave_id);
+						PP(hw_id, simd_id);
+						PP(hw_id, pipe_id);
+						PP(hw_id, cu_id);
+						PP(hw_id, sh_id);
+						PP(hw_id, se_id);
+						PP(hw_id, tg_id);
+						PP(hw_id, vm_id);
+						PP(hw_id, queue_id);
+						PP(hw_id, state_id);
+						PP(hw_id, me_id);
+
+						Hv("GPR_ALLOC", ws.gpr_alloc.value);
+						PP(gpr_alloc, vgpr_base);
+						PP(gpr_alloc, vgpr_size);
+						PP(gpr_alloc, sgpr_base);
+						PP(gpr_alloc, sgpr_size);
+
+						printf("\n\nSGPRS:\n");
+						for (x = 0; x < ((ws.gpr_alloc.sgpr_size + 1) << shift); x += 4)
+							printf("\t[%4u..%4u] = { %08lx, %08lx, %08lx, %08lx }\n",
+								(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x),
+								(unsigned)((ws.gpr_alloc.sgpr_base << shift) + x + 3),
+								(unsigned long)sgprs[x],
+								(unsigned long)sgprs[x+1],
+								(unsigned long)sgprs[x+2],
+								(unsigned long)sgprs[x+3]);
+
+						Hv("LDS_ALLOC", ws.lds_alloc.value);
+						PP(lds_alloc, lds_base);
+						PP(lds_alloc, lds_size);
+
+						Hv("IB_STS", ws.ib_sts.value);
+						PP(ib_sts, vm_cnt);
+						PP(ib_sts, exp_cnt);
+						PP(ib_sts, lgkm_cnt);
+						PP(ib_sts, valu_cnt);
+
+						Hv("TRAPSTS", ws.trapsts.value);
+						PP(trapsts, excp);
+						PP(trapsts, excp_cycle);
+						PP(trapsts, dp_rate);
+
+						printf("\n"); col = 0;
+					}
+
+				}
+			}
+		}
+	}
+	if (first)
+		printf("No active waves!\n");
+}
diff --git a/src/app/ring_read.c b/src/app/ring_read.c
new file mode 100644
index 0000000..52206de
--- /dev/null
+++ b/src/app/ring_read.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <inttypes.h>
+
+void umr_read_ring(struct umr_asic *asic, char *ringpath)
+{
+	char fname[128], ringname[32], from[32], to[32];
+	int fd, use_decoder, enable_decoder;
+	uint32_t wptr, rptr, drv_wptr, ringsize, start, end, value,
+		 *ring_data;
+	struct umr_ring_decoder decoder, *pdecoder, *ppdecoder;
+
+	memset(ringname, 0, sizeof ringname);
+	memset(from, 0, sizeof from);
+	memset(to, 0, sizeof to);
+	if (sscanf(ringpath, "%[a-z0-9._][%[.0-9]:%[.0-9]]", ringname, from, to) < 1) {
+		printf("Invalid ringpath\n");
+		return;
+	}
+
+	snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_ring_%s", asic->instance, ringname);
+	fd = open(fname, O_RDWR);
+	if (fd < 0) {
+		perror("Could not open ring debugfs file");
+		return;
+	}
+
+	// only decode PM4 packets on certain rings
+	memset(&decoder, 0, sizeof decoder);
+	if (!memcmp(ringname, "gfx", 3) ||
+	    !memcmp(ringname, "uvd", 3) ||
+	    !memcmp(ringname, "comp", 4)) {
+		enable_decoder = 1;
+		decoder.pm = 4;
+	} else {
+		enable_decoder = 0;
+	}
+
+	/* determine file size */
+	ringsize = lseek(fd, 0, SEEK_END) - 12;
+	lseek(fd, 0, SEEK_SET);
+
+	ring_data = calloc(1, ringsize + 12);
+	if (!ring_data) {
+		close(fd);
+		perror("Could not allocate ring data");
+		return;
+	}
+	read(fd, ring_data, ringsize + 12);
+	close(fd);
+
+	/* read pointers */
+	rptr = ring_data[0]<<2;
+	wptr = ring_data[1]<<2;
+	drv_wptr = ring_data[2]<<2;
+
+	/* default to reading entire ring */
+	if (!from[0]) {
+		start = 0;
+		end   = ringsize;
+	} else {
+		if (from[0] == '.' || !to[0] || to[0] == '.') {
+			/* start from 32 words prior to rptr up to wptr */
+			end = wptr+4;
+			if (rptr < (31*4)) {
+				start = rptr - 31*4;
+				start += ringsize;
+			} else {
+				start = rptr - 31*4;
+			}
+
+		} else {
+			sscanf(from, "%"SCNu32, &start);
+			sscanf(to, "%"SCNu32, &end);
+		}
+	}
+	end %= ringsize;
+	start %= ringsize;
+
+	/* dump data */
+	printf("\n%s.%s.rptr == %lu\n%s.%s.wptr == %lu\n%s.%s.drv_wptr == %lu\n",
+		asic->asicname, ringname, (unsigned long)rptr >> 2,
+		asic->asicname, ringname, (unsigned long)wptr >> 2,
+		asic->asicname, ringname, (unsigned long)drv_wptr >> 2);
+
+	use_decoder = 0;
+	while (start != end) {
+		value = ring_data[(start+12)>>2];
+		printf("%s.%s.ring[%4lu] == 0x%08lx   ", asic->asicname, ringname, (unsigned long)start >> 2, (unsigned long)value);
+		if (enable_decoder && start == rptr && start != wptr) {
+			use_decoder = 1;
+			decoder.pm4.cur_opcode = 0xFFFFFFFF;
+		}
+		printf(" %c%c%c ",
+			(start == rptr) ? 'r' : '.',
+			(start == wptr) ? 'w' : '.',
+			(start == drv_wptr) ? 'D' : '.');
+		if (use_decoder)
+			umr_print_decode(asic, &decoder, value);
+		printf("\n");
+		start += 4;
+		start %= ringsize;
+	}
+	free(ring_data);
+	printf("\n");
+
+	pdecoder = decoder.next_ib;
+	while (pdecoder) {
+		umr_dump_ib(asic, pdecoder);
+		ppdecoder = pdecoder->next_ib;
+		free(pdecoder);
+		pdecoder = ppdecoder;
+	}
+}
diff --git a/src/app/scan.c b/src/app/scan.c
new file mode 100644
index 0000000..436c2e0
--- /dev/null
+++ b/src/app/scan.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+
+int umr_scan_asic(struct umr_asic *asic, char *asicname, char *ipname, char *regname)
+{
+	int r, fd;
+	int i, j, k;
+	uint64_t addr, scale;
+	char buf[256];
+
+	/* scan them all in order */
+	if (!asicname[0] || !strcmp(asicname, "*") || !strcmp(asicname, asic->asicname)) {
+		for (i = 0; i < asic->no_blocks; i++) {
+			if (!ipname[0] || !strcmp(ipname, asic->blocks[i]->ipname)) {
+				if (asic->blocks[i]->grant) {
+					r = asic->blocks[i]->grant(asic);
+					if (r)
+						continue;
+				}
+				for (j = 0; j < asic->blocks[i]->no_regs; j++) {
+					if (!regname[0] || !strcmp(regname, "*") || !strcmp(regname, asic->blocks[i]->regs[j].regname) ||
+					(options.many && strstr(asic->blocks[i]->regs[j].regname, regname))) {
+						if (asic->pci.mem == NULL) {
+							switch(asic->blocks[i]->regs[j].type) {
+							case REG_MMIO: fd = asic->fd.mmio; scale = 4; break;
+							case REG_DIDT: fd = asic->fd.didt; scale = 1; break;
+							case REG_PCIE: fd = asic->fd.pcie; scale = 1; break;
+							case REG_SMC:
+								if (options.read_smc) {
+									fd = asic->fd.smc; scale = 4;
+								} else {
+									continue;
+								}
+								break;
+							default: return -1;
+							}
+
+							if (options.use_bank && asic->blocks[i]->regs[j].type == REG_MMIO)
+								addr =
+									(1ULL << 62) |
+									(((uint64_t)options.se_bank) << 24) |
+									(((uint64_t)options.sh_bank) << 34) |
+									(((uint64_t)options.instance_bank) << 44);
+							else
+								addr = 0;
+
+							if (lseek(fd, addr|(asic->blocks[i]->regs[j].addr*scale), SEEK_SET) == -1) {
+								snprintf(buf, sizeof(buf)-1, "Could not seek reading register %s.%s.%s", asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname);
+								perror(buf);
+								r = -1;
+								goto error;
+							}
+							if (read(fd, &asic->blocks[i]->regs[j].value, 4) != 4) {
+								snprintf(buf, sizeof(buf)-1, "Could not read register %s.%s.%s", asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname);
+								perror(buf);
+								r = -1;
+								goto error;
+							}
+						} else if (asic->blocks[i]->regs[j].type == REG_MMIO) {
+							asic->blocks[i]->regs[j].value = asic->pci.mem[asic->blocks[i]->regs[j].addr];
+						}
+						if (regname[0]) {
+							if (options.named)
+								printf("%s%s%s => ", CYAN, asic->blocks[i]->regs[j].regname, RST);
+							printf("%s0x%08lx%s\n", YELLOW, (unsigned long)asic->blocks[i]->regs[j].value, RST);
+							if (options.bitfields)
+								for (k = 0; k < asic->blocks[i]->regs[j].no_bits; k++) {
+									uint32_t v;
+									v = (1UL << (asic->blocks[i]->regs[j].bits[k].stop + 1 - asic->blocks[i]->regs[j].bits[k].start)) - 1;
+									v &= (asic->blocks[i]->regs[j].value >> asic->blocks[i]->regs[j].bits[k].start);
+									asic->blocks[i]->regs[j].bits[k].bitfield_print(asic, asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, asic->blocks[i]->regs[j].bits[k].regname, asic->blocks[i]->regs[j].bits[k].start, asic->blocks[i]->regs[j].bits[k].stop, v);
+								}
+						}
+					}
+				}
+				if (asic->blocks[i]->release) {
+					r = asic->blocks[i]->release(asic);
+					if (r)
+						goto error;
+				}
+			}
+		}
+	}
+
+	r = 0;
+error:
+
+	return r;
+}
diff --git a/src/app/scan_log.c b/src/app/scan_log.c
new file mode 100644
index 0000000..3401be9
--- /dev/null
+++ b/src/app/scan_log.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+
+void umr_scan_log(struct umr_asic *asic)
+{
+	char line[256], *chr;
+	FILE *f;
+	int i, j, k, found;
+	unsigned long delta, did, regno, value, write;
+
+	f = fopen("/sys/kernel/debug/tracing/trace", "r");
+	if (!f) {
+		perror("Could not open ftrace log");
+		return;
+	}
+
+	while (fgets(line, sizeof(line), f)) {
+		found = 0;
+		delta = 0;
+		write = 0;
+
+		chr = strstr(line, "amdgpu_mm_");
+		if (chr) {
+			if (sscanf(chr, "amdgpu_mm_rreg: 0x%08lx, 0x%08lx, 0x%08lx",
+				   &did, &regno, &value) != 3) {
+				write = 1;
+				if (sscanf(chr, "amdgpu_mm_wreg: 0x%08lx, 0x%08lx, 0x%08lx",
+					&did, &regno, &value) != 3)
+					continue;
+			}
+
+			if (did == asic->did) {
+				do {
+					// try to find reg in asic profile
+					for (i = 0; i < asic->no_blocks; i++)
+					for (j = 0; j < asic->blocks[i]->no_regs; j++)
+						if (asic->blocks[i]->regs[j].type == REG_MMIO &&
+						    asic->blocks[i]->regs[j].addr == regno) {
+							// bingo
+							if (write)
+								printf("%s.%s.%s +0x%04lx <= 0x%08lx\n",
+									asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname,
+									(unsigned long)delta,
+									(unsigned long)value);
+							else
+								printf("%s.%s.%s +0x%04lx => 0x%08lx\n",
+									asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname,
+									(unsigned long)delta,
+									(unsigned long)value);
+							if (options.bitfields)
+								for (k = 0; k < asic->blocks[i]->regs[j].no_bits; k++) {
+									uint32_t v;
+									v = (1UL << (asic->blocks[i]->regs[j].bits[k].stop + 1 - asic->blocks[i]->regs[j].bits[k].start)) - 1;
+									v &= (value >> asic->blocks[i]->regs[j].bits[k].start);
+									asic->blocks[i]->regs[j].bits[k].bitfield_print(asic, asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, asic->blocks[i]->regs[j].bits[k].regname, asic->blocks[i]->regs[j].bits[k].start, asic->blocks[i]->regs[j].bits[k].stop, v);
+								}
+							found = 1;
+							goto out;
+						}
+out:
+					regno -= 1;
+					delta += 1;
+				} while (!found);
+			}
+		}
+	}
+	fclose(f);
+	if (options.empty_log) {
+		f = fopen("/sys/kernel/debug/tracing/trace", "w");
+		if (f) {
+			fprintf(f, "foo\n");
+			fclose(f);
+		}
+	}
+}
+
diff --git a/src/app/set_bit.c b/src/app/set_bit.c
new file mode 100644
index 0000000..bd9ee2b
--- /dev/null
+++ b/src/app/set_bit.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <inttypes.h>
+
+/* set a register based on regpath e.g.
+ *
+ * stoney.uvd6.mmFOO.bit
+ */
+int umr_set_register_bit(struct umr_asic *asic, char *regpath, char *regvalue)
+{
+	char rpath[512];
+	int i, j, k, fd;
+	uint32_t value, mask, copy;
+	uint64_t addr, scale;
+
+	/* scan until we compare with regpath... */
+	for (i = 0; i < asic->no_blocks; i++) {
+		if (!memcmp(regpath, "*.", 2))
+			snprintf(rpath, sizeof(rpath)-1, "*.%s.", asic->blocks[i]->ipname);
+		else
+			snprintf(rpath, sizeof(rpath)-1, "%s.%s.", asic->asicname, asic->blocks[i]->ipname);
+		if (memcmp(regpath, rpath, strlen(rpath)) == 0) {
+			for (j = 0; j < asic->blocks[i]->no_regs; j++) {
+				if (asic->blocks[i]->regs[j].bits) {
+					for (k = 0; k < asic->blocks[i]->regs[j].no_bits; k++) {
+						if (!memcmp(regpath, "*.", 2))
+							snprintf(rpath, sizeof(rpath)-1, "*.%s.%s.%s", asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, asic->blocks[i]->regs[j].bits[k].regname);
+						else
+							snprintf(rpath, sizeof(rpath)-1, "%s.%s.%s.%s", asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, asic->blocks[i]->regs[j].bits[k].regname);
+						if (!strcmp(regpath, rpath)) {
+							sscanf(regvalue, "%"SCNx32, &value);
+
+							mask = (1UL<<((1+asic->blocks[i]->regs[j].bits[k].stop)-asic->blocks[i]->regs[j].bits[k].start))-1;
+							mask <<= asic->blocks[i]->regs[j].bits[k].start;
+							if (asic->pci.mem == NULL) {
+								// set this register
+								switch (asic->blocks[i]->regs[j].type){
+								case REG_MMIO: fd = asic->fd.mmio; scale = 4; break;
+								case REG_DIDT: fd = asic->fd.didt; scale = 1; break;
+								case REG_PCIE: fd = asic->fd.pcie; scale = 1; break;
+								case REG_SMC:  fd = asic->fd.smc; scale = 4; break;
+								default: return -1;
+								}
+								if (asic->blocks[i]->grant) {
+									if (asic->blocks[i]->grant(asic)) {
+										return -1;
+									}
+								}
+
+								if (options.use_bank && asic->blocks[i]->regs[j].type == REG_MMIO)
+									addr =
+										(1ULL << 62) |
+										(((uint64_t)options.se_bank) << 24) |
+										(((uint64_t)options.sh_bank) << 34) |
+										(((uint64_t)options.instance_bank) << 44);
+								else
+									addr = 0;
+
+								lseek(fd, addr | (asic->blocks[i]->regs[j].addr*scale), SEEK_SET);
+								read(fd, &copy, 4);
+
+								// read-modify-write value back
+								copy &= ~mask;
+								value = (value << asic->blocks[i]->regs[j].bits[k].start) & mask;
+								copy |= value;
+
+								lseek(fd, addr | (asic->blocks[i]->regs[j].addr<<2), SEEK_SET);
+								write(fd, &copy, 4);
+								if (!options.quiet) printf("%s <= 0x%08lx\n", regpath, (unsigned long)copy);
+
+								if (asic->blocks[i]->release) {
+									if (asic->blocks[i]->release(asic)) {
+										return -1;
+									}
+								}
+							} else if (asic->blocks[i]->regs[j].type == REG_MMIO) {
+								copy = asic->pci.mem[asic->blocks[i]->regs[j].addr] & ~mask;
+								copy |= (value << asic->blocks[i]->regs[j].bits[k].start) & mask;
+								asic->pci.mem[asic->blocks[i]->regs[j].addr] = copy;
+								if (!options.quiet) printf("%s <= 0x%08lx\n", regpath, (unsigned long)copy);
+							}
+							return 0;
+						}
+					}
+				}
+			}
+		}
+	}
+	fprintf(stderr, "Path <%s> not found on this ASIC\n", regpath);
+	return -1;
+}
+
diff --git a/src/app/set_reg.c b/src/app/set_reg.c
new file mode 100644
index 0000000..c3a44b5
--- /dev/null
+++ b/src/app/set_reg.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <inttypes.h>
+
+/* set a register based on regpath e.g.
+ *
+ * stoney.uvd6.mmFOO
+ */
+int umr_set_register(struct umr_asic *asic, char *regpath, char *regvalue)
+{
+	char rpath[512];
+	int i, j, fd;
+	uint32_t value;
+	uint64_t addr, scale;
+
+	/* scan until we compare with regpath... */
+	for (i = 0; i < asic->no_blocks; i++) {
+		if (!memcmp(regpath, "*.", 2))
+			snprintf(rpath, sizeof(rpath)-1, "*.%s.", asic->blocks[i]->ipname);
+		else
+			snprintf(rpath, sizeof(rpath)-1, "%s.%s.", asic->asicname, asic->blocks[i]->ipname);
+		if (memcmp(regpath, rpath, strlen(rpath)) == 0) {
+			for (j = 0; j < asic->blocks[i]->no_regs; j++) {
+				if (!memcmp(regpath, "*.", 2))
+					snprintf(rpath, sizeof(rpath)-1, "*.%s.%s", asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname);
+				else
+					snprintf(rpath, sizeof(rpath)-1, "%s.%s.%s", asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname);
+				if (!strcmp(regpath, rpath)) {
+					sscanf(regvalue, "%"SCNx32, &value);
+
+					if (asic->pci.mem == NULL) {
+						// set this register
+						switch (asic->blocks[i]->regs[j].type){
+						case REG_MMIO: fd = asic->fd.mmio; scale = 4; break;
+						case REG_DIDT: fd = asic->fd.didt; scale = 1; break;
+						case REG_PCIE: fd = asic->fd.pcie; scale = 1; break;
+						case REG_SMC:  fd = asic->fd.smc; scale = 4; break;
+						default: return -1;
+						}
+						
+						if (asic->blocks[i]->grant) {
+							if (asic->blocks[i]->grant(asic)) {
+								return -1;
+							}
+						}
+
+						if (options.use_bank && asic->blocks[i]->regs[j].type == REG_MMIO)
+							addr =
+								(1ULL << 62) |
+								(((uint64_t)options.se_bank) << 24) |
+								(((uint64_t)options.sh_bank) << 34) |
+								(((uint64_t)options.instance_bank) << 44);
+						else
+							addr = 0;
+
+						lseek(fd, addr | (asic->blocks[i]->regs[j].addr*scale), SEEK_SET);
+						write(fd, &value, 4);
+
+						if (asic->blocks[i]->release) {
+							if (asic->blocks[i]->release(asic)) {
+								return -1;
+							}
+						}
+					} else if (asic->blocks[i]->regs[j].type == REG_MMIO) {
+						asic->pci.mem[asic->blocks[i]->regs[j].addr] = value;
+					}
+					return 0;
+				}
+			}
+		}
+	}
+	fprintf(stderr, "Path <%s> not found on this ASIC\n", regpath);
+	return -1;
+}
diff --git a/src/app/top.c b/src/app/top.c
new file mode 100644
index 0000000..b081515
--- /dev/null
+++ b/src/app/top.c
@@ -0,0 +1,976 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <time.h>
+#include <ncurses.h>
+
+static struct {
+	int quit,
+	    wide,
+	    vram,
+	    high_precision,
+	    high_frequency,
+	    all,
+	    logger,
+	    drm;
+	struct {
+		int ta,
+		    vgt,
+		    uvd,
+		    vce,
+		    memory_hub,
+		    grbm,
+		    gfxpwr,
+		    sdma,
+		    sensors;
+	} vi;
+	char *helptext;
+	void (*handle_key)(int ch);
+} top_options;
+
+enum sensor_maps {
+	SENSOR_IDENTITY=0, // x = x
+	SENSOR_D1000,    // x = x/1000
+	SENSOR_D100,    // x = x/100
+};
+
+enum sensor_print {
+	SENSOR_MILLIVOLT=0,
+	SENSOR_MHZ,
+	SENSOR_PERCENT,
+	SENSOR_TEMP,
+};
+
+enum drm_print {
+	DRM_INFO_BYTES=0,
+	DRM_INFO_COUNT,
+};
+
+static struct umr_bitfield stat_grbm_bits[] = {
+	 { "TA_BUSY", 255, 255, &umr_bitfield_default },
+	 { "GDS_BUSY", 255, 255, &umr_bitfield_default },
+	 { "WD_BUSY_NO_DMA", 255, 255, &umr_bitfield_default },
+	 { "VGT_BUSY", 255, 255, &umr_bitfield_default },
+	 { "IA_BUSY_NO_DMA", 255, 255, &umr_bitfield_default },
+	 { "IA_BUSY", 255, 255, &umr_bitfield_default },
+	 { "SX_BUSY", 255, 255, &umr_bitfield_default },
+	 { "WD_BUSY", 255, 255, &umr_bitfield_default },
+	 { "SPI_BUSY", 255, 255, &umr_bitfield_default },
+	 { "BCI_BUSY", 255, 255, &umr_bitfield_default },
+	 { "SC_BUSY", 255, 255, &umr_bitfield_default },
+	 { "PA_BUSY", 255, 255, &umr_bitfield_default },
+	 { "DB_BUSY", 255, 255, &umr_bitfield_default },
+	 { "CP_COHERENCY_BUSY", 255, 255, &umr_bitfield_default },
+	 { "CP_BUSY", 255, 255, &umr_bitfield_default },
+	 { "CB_BUSY", 255, 255, &umr_bitfield_default },
+	 { "GUI_ACTIVE", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_grbm2_bits[] = {
+	 { "RLC_BUSY", 255, 255, &umr_bitfield_default },
+	 { "TC_BUSY", 255, 255, &umr_bitfield_default },
+	 { "CPF_BUSY", 255, 255, &umr_bitfield_default },
+	 { "CPC_BUSY", 255, 255, &umr_bitfield_default },
+	 { "CPG_BUSY", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_uvdclk_bits[] = {
+	 { "UDEC_SCLK", 255, 255, &umr_bitfield_default },
+	 { "MPEG2_SCLK", 255, 255, &umr_bitfield_default },
+	 { "IDCT_SCLK", 255, 255, &umr_bitfield_default },
+	 { "MPRD_SCLK", 255, 255, &umr_bitfield_default },
+	 { "MPC_SCLK", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_ta_bits[] = {
+	 { "IN_BUSY", 255, 255, &umr_bitfield_default },
+	 { "FG_BUSY", 255, 255, &umr_bitfield_default },
+	 { "LA_BUSY", 255, 255, &umr_bitfield_default },
+	 { "FL_BUSY", 255, 255, &umr_bitfield_default },
+	 { "TA_BUSY", 255, 255, &umr_bitfield_default },
+	 { "FA_BUSY", 255, 255, &umr_bitfield_default },
+	 { "AL_BUSY", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_vgt_bits[] = {
+	 { "VGT_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_OUT_INDX_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_OUT_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_PT_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_TE_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_VR_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_PI_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_GS_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_HS_BUSY", 255, 255, &umr_bitfield_default },
+	 { "VGT_TE11_BUSY", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_rlc_gpm_bits[] = {
+	 { "GFX_POWER_STATUS", 255, 255, &umr_bitfield_default },
+	 { "GFX_CLOCK_STATUS", 255, 255, &umr_bitfield_default },
+	 { "GFX_LS_STATUS", 255, 255, &umr_bitfield_default },
+	 { "GFX_PIPELINE_POWER_STATUS",255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_uvd_pgfsm1_bits[] = {
+	 { "UVD_PGFSM_READ_TILE1_VALUE", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+static struct umr_bitfield stat_uvd_pgfsm2_bits[] = {
+	 { "UVD_PGFSM_READ_TILE2_VALUE", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+static struct umr_bitfield stat_uvd_pgfsm3_bits[] = {
+	 { "UVD_PGFSM_READ_TILE3_VALUE", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+static struct umr_bitfield stat_uvd_pgfsm4_bits[] = {
+	 { "UVD_PGFSM_READ_TILE4_VALUE", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+static struct umr_bitfield stat_uvd_pgfsm5_bits[] = {
+	 { "UVD_PGFSM_READ_TILE5_VALUE", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+static struct umr_bitfield stat_uvd_pgfsm6_bits[] = {
+	 { "UVD_PGFSM_READ_TILE6_VALUE", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+static struct umr_bitfield stat_uvd_pgfsm7_bits[] = {
+	 { "UVD_PGFSM_READ_TILE7_VALUE", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+static struct umr_bitfield stat_mc_hub_bits[] = {
+	 { "OUTSTANDING_READ", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE", 255, 255, &umr_bitfield_default },
+//	 { "OUTSTANDING_ATOMIC", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDREQ", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDRET", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRREQ", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRRET", 255, 255, &umr_bitfield_default },
+//	 { "OUTSTANDING_HUB_ATOMIC_REQ", 255, 255, &umr_bitfield_default },
+//	 { "OUTSTANDING_HUB_ATOMIC_RET", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_READ", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_WRITE", 255, 255, &umr_bitfield_default },
+//	 { "OUTSTANDING_RPB_ATOMIC", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_READ", 255, 255, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_WRITE", 255, 255, &umr_bitfield_default },
+//	 { "OUTSTANDING_MCD_ATOMIC", 255, 255, &umr_bitfield_default },
+	 { NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_sdma_bits[] = {
+	{ "SDMA_RQ_PENDING", 255, 255, &umr_bitfield_default },
+	{ "SDMA1_RQ_PENDING", 255, 255, &umr_bitfield_default },
+	{ "SDMA_BUSY", 255, 255, &umr_bitfield_default },
+	{ "SDMA1_BUSY",255, 255, &umr_bitfield_default },
+	{ "SDMA2_BUSY", 255, 255, &umr_bitfield_default },
+	{ "SDMA3_BUSY", 255, 255, &umr_bitfield_default },
+	{ "SDMA2_RQ_PENDING", 255, 255, &umr_bitfield_default },
+	{ "SDMA3_RQ_PENDING", 255, 255, &umr_bitfield_default },
+	{ NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_srbm_status2_vce_bits[] = {
+	{ "VCE0_BUSY", 255, 255, &umr_bitfield_default },
+	{ "VCE1_BUSY", 255, 255, &umr_bitfield_default },
+	{ NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_srbm_status_uvd_bits[] = {
+	{ "UVD_BUSY", 255, 255, &umr_bitfield_default },
+	{ NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_carrizo_sensor_bits[] = {
+	{ "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), &umr_bitfield_default },
+	{ "VDD_NB", AMDGPU_PP_SENSOR_VDDNB, SENSOR_MILLIVOLT<<4, &umr_bitfield_default },
+	{ "VDD_GFX", AMDGPU_PP_SENSOR_VDDGFX, SENSOR_MILLIVOLT<<4, &umr_bitfield_default },
+	{ "UVD_VCLK", AMDGPU_PP_SENSOR_UVD_VCLK, SENSOR_D100|(SENSOR_MHZ<<4), &umr_bitfield_default },
+	{ "UVD_DCLK", AMDGPU_PP_SENSOR_UVD_DCLK, SENSOR_D100|(SENSOR_MHZ<<4), &umr_bitfield_default },
+	{ "VCE_ECCLK", AMDGPU_PP_SENSOR_VCE_ECCLK, SENSOR_D100|(SENSOR_MHZ<<4), &umr_bitfield_default },
+	{ "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, &umr_bitfield_default },
+	{ "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), &umr_bitfield_default },
+	{ NULL, 0, 0, NULL },
+};
+
+static struct umr_bitfield stat_vi_sensor_bits[] = {
+	{ "GFX_SCLK", AMDGPU_PP_SENSOR_GFX_SCLK, SENSOR_D100|(SENSOR_MHZ<<4), &umr_bitfield_default },
+	{ "GFX_MCLK", AMDGPU_PP_SENSOR_GFX_MCLK, SENSOR_D100|(SENSOR_MHZ<<4), &umr_bitfield_default },
+	{ "GPU_LOAD", AMDGPU_PP_SENSOR_GPU_LOAD, SENSOR_PERCENT<<4, &umr_bitfield_default },
+	{ "GPU_TEMP", AMDGPU_PP_SENSOR_GPU_TEMP, SENSOR_D1000|(SENSOR_TEMP<<4), &umr_bitfield_default },
+	{ NULL, 0, 0, NULL },
+};
+
+#define AMDGPU_INFO_NUM_BYTES_MOVED		0x0f
+#define AMDGPU_INFO_VRAM_USAGE			0x10
+#define AMDGPU_INFO_GTT_USAGE			0x11
+#define AMDGPU_INFO_VIS_VRAM_USAGE		0x17
+#define AMDGPU_INFO_NUM_EVICTIONS		0x18
+
+#define AMDGPU_INFO_FENCES_SIGNALED 0x80
+#define AMDGPU_INFO_FENCES_EMITTED  0x81
+#define AMDGPU_INFO_FENCES_DELTA    0x82
+#define AMDGPU_INFO_WAVES           0x83
+
+static struct umr_bitfield stat_drm_bits[] = {
+	{ "BYTES_MOVED", AMDGPU_INFO_NUM_BYTES_MOVED, DRM_INFO_BYTES, &umr_bitfield_default },
+	{ "VRAM_USAGE", AMDGPU_INFO_VRAM_USAGE, DRM_INFO_BYTES, &umr_bitfield_default },
+	{ "GTT_USAGE", AMDGPU_INFO_GTT_USAGE, DRM_INFO_BYTES, &umr_bitfield_default },
+	{ "VIS_VRAM", AMDGPU_INFO_VIS_VRAM_USAGE, DRM_INFO_BYTES, &umr_bitfield_default },
+	{ "EVICTIONS", AMDGPU_INFO_NUM_EVICTIONS, DRM_INFO_COUNT, &umr_bitfield_default },
+	{ "FENCES_SIGNALED", AMDGPU_INFO_FENCES_SIGNALED, DRM_INFO_COUNT, &umr_bitfield_default },
+	{ "FENCES_EMITTED", AMDGPU_INFO_FENCES_EMITTED, DRM_INFO_COUNT, &umr_bitfield_default },
+	{ "FENCES_DELTA", AMDGPU_INFO_FENCES_DELTA, DRM_INFO_COUNT, &umr_bitfield_default },
+	{ "WAVES", AMDGPU_INFO_WAVES, DRM_INFO_COUNT, &umr_bitfield_default },
+	{ NULL, 0, 0, NULL },
+};
+
+static FILE *logfile = NULL;
+
+
+static unsigned long last_fence_emitted, last_fence_signaled, fence_signal_count, fence_emit_count;
+static void analyze_fence_info(struct umr_asic *asic)
+{
+	char name[256];
+	unsigned long fence_emitted, fence_signaled, number;
+	FILE *f;
+
+	snprintf(name, sizeof(name)-1, "/sys/kernel/debug/dri/%d/amdgpu_fence_info", asic->instance);
+	f = fopen(name, "rb");
+	if (f) {
+		fence_emitted = fence_signaled = 0;
+		while (fgets(name, sizeof(name)-1, f)) {
+			if (sscanf(name, "Last signaled fence 0x%08lx", &number) == 1)
+				fence_signaled += number;
+			else if (sscanf(name, "Last emitted 0x%08lx", &number) == 1)
+				fence_emitted += number;
+		}
+		fence_signal_count = fence_signaled - last_fence_signaled;
+		fence_emit_count = fence_emitted - last_fence_emitted;
+		last_fence_signaled = fence_signaled;
+		last_fence_emitted = fence_emitted;
+		fclose(f);
+	}
+}
+
+static unsigned vi_count_waves(struct umr_asic *asic)
+{
+	uint32_t se, sh, cu, simd, wave, count;
+	struct umr_wave_status ws;
+
+	// don't count waves if PG is enabled because it causes GPU hangs
+	if ((asic->config.gfx.pg_flags & ~0xffffeffc) ||
+	    (asic->config.gfx.cg_flags & 0xFF))
+		return 0;
+
+	count = 0;
+	for (se = 0; se < asic->config.gfx.max_shader_engines; se++)
+	for (sh = 0; sh < asic->config.gfx.max_sh_per_se; sh++)
+	for (cu = 0; cu < asic->config.gfx.max_cu_per_sh; cu++) {
+		for (simd = 0; simd < 1; simd++)
+		for (wave = 0; wave < 10; wave++) { //both simd/wave are hard coded at the moment...
+			umr_get_wave_status(asic, se, sh, cu, simd, wave, &ws);
+			if (ws.wave_status.halt || ws.wave_status.valid)
+				++count;
+		}
+	}
+	return count;
+}
+
+static void slice(char *r, char *s)
+{
+	char *p, *q;
+	if ((p = strstr(r, s))) {
+		q = p + strlen(s);
+		do {
+			*p++ = *q;
+		} while (*q++);
+	}
+}
+
+
+static int maxstrlen = 0;
+static int grab_bits(char *name, struct umr_asic *asic, struct umr_bitfield *bits, uint32_t *addr)
+{
+	int i, j, k, l;
+
+	// try to find the register somewhere in the ASIC
+	*addr = 0;
+	for (i = 0; i < asic->no_blocks; i++) {
+		for (j = 0; j < asic->blocks[i]->no_regs; j++) {
+			if (strcmp(asic->blocks[i]->regs[j].regname, name) == 0) {
+				*addr = asic->blocks[i]->regs[j].addr<<2;
+				goto out;
+			}
+		}
+	}
+out:
+	// now map all of the bits of that register to that of the ASIC
+	if (*addr) {
+		for (k = 0; bits[k].regname; k++) {
+			for (l = 0; l < asic->blocks[i]->regs[j].no_bits; l++) {
+				if (!strcmp(bits[k].regname, asic->blocks[i]->regs[j].bits[l].regname)) {
+					// copy
+					bits[k] = asic->blocks[i]->regs[j].bits[l];
+					break;
+				}
+			}
+		}
+	}
+
+	// let's trim _BUSY out of the names since it's redundant
+	if (*addr) {
+		for (k = 0; bits[k].regname; k++) {
+			bits[k].regname = strcpy(calloc(1, strlen(bits[k].regname) + 1), bits[k].regname);
+			slice(bits[k].regname, "_BUSY");
+			slice(bits[k].regname, "_STATUS");
+			slice(bits[k].regname, "_VALUE");
+			slice(bits[k].regname, "_ACTIVE");
+			slice(bits[k].regname, "OUTSTANDING_");
+			slice(bits[k].regname, "PGFSM_READ_");
+		}
+	}
+	return (*addr == 0) ? 1 : 0;
+}
+
+static int print_j = 0;
+
+static void print_count_value(uint64_t count)
+{
+	int i, v;
+	if (options.use_colour) {
+		if (top_options.high_precision)
+			v = (count+9) / 10;
+		else
+			v = count;
+		if (v <= 10)
+			i = 1;
+		else if (v <= 20)
+			i = 2;
+		else if (v <= 35)
+			i = 3;
+		else
+			i = 4;
+		attron(COLOR_PAIR(i)|A_BOLD);
+	}
+	if (top_options.high_precision)
+		printw("%5d.%d %%", count/10, count%10);
+	else
+		printw("%5d %%  ", count);
+	if (options.use_colour)
+		attroff(COLOR_PAIR(i)|A_BOLD);
+}
+
+static char namefmt[30];
+static void print_counts(struct umr_bitfield *bits, uint64_t *counts)
+{
+	int i;
+	for (i = 0; bits[i].regname; i++) {
+		if (bits[i].start != 255) {
+			printw(namefmt, bits[i].regname);
+			print_count_value(counts[i]);
+			if ((++print_j & (top_options.wide ? 3 : 1)) != 0)
+				printw(" |");
+			else
+				printw("\n");
+		}
+	}
+}
+
+static void print_sensors(struct umr_bitfield *bits, uint64_t *counts)
+{
+	int i;
+	for (i = 0; bits[i].regname; i++) {
+		if (bits[i].start != 255) {
+			printw(namefmt, bits[i].regname);
+			switch (bits[i].stop >> 4) {
+				default:
+					printw("%5d    ", counts[i]);
+					break;
+				case SENSOR_MHZ:
+					printw("%5d MHz", counts[i]);
+					break;
+				case SENSOR_MILLIVOLT:
+					printw("%5d.%3d", counts[i]/1000, counts[i]%1000);
+					break;
+				case SENSOR_PERCENT:
+					printw("%5d %%  ", counts[i]);
+					break;
+				case SENSOR_TEMP:
+					printw("%5d C  ", counts[i]);
+					break;
+			};
+			if ((++print_j & (top_options.wide ? 3 : 1)) != 0)
+				printw(" |");
+			else
+				printw("\n");
+		}
+	}
+}
+
+static void print_drm(struct umr_bitfield *bits, uint64_t *counts)
+{
+	int i;
+
+	for (i = 0; bits[i].regname; i++) {
+		if (bits[i].start != 255) {
+			printw(namefmt, bits[i].regname);
+			switch (bits[i].stop) {
+				case DRM_INFO_COUNT:
+					printw("%5d    ", counts[i]);
+					break;
+				case DRM_INFO_BYTES:
+					if (counts[i] < 1024)
+						printw("%5d    ", (int)counts[i]);
+					else if (counts[i] < 1024*1024)
+						printw("%7.3f k", ((double)counts[i])/1024.0);
+					else if (counts[i] < 1024*1024*1024)
+						printw("%7.3f m", ((double)counts[i])/1048576.0);
+					else
+						printw("%7.3f g", ((double)counts[i])/(1024*1024*1024));
+					break;
+			}
+			if ((++print_j & (top_options.wide ? 3 : 1)) != 0)
+				printw(" |");
+			else
+				printw("\n");
+		}
+	}
+}
+
+
+static void parse_bits(struct umr_asic *asic, uint32_t addr, struct umr_bitfield *bits, uint64_t *counts, uint32_t *mask, uint32_t *cmp, uint64_t addr_mask)
+{
+	int j;
+	uint32_t value;
+
+	if (addr) {
+		if (addr_mask && asic->fd.mmio < 0) {
+			value = 0;
+		} else if (!addr_mask && asic->pci.mem) {
+			value = asic->pci.mem[addr>>2];
+		} else {
+			lseek(asic->fd.mmio, addr | addr_mask, SEEK_SET);
+			read(asic->fd.mmio, &value, 4);
+		}
+		for (j = 0; bits[j].regname; j++)
+			if (bits[j].start != 255) {
+				if (bits[j].start == bits[j].stop) {
+					counts[j] += (value & (1UL<<bits[j].start)) ? (top_options.high_frequency ? 10 : 1) : 0;
+				} else {
+					value = (value >> bits[j].start) & ((1UL << (bits[j].stop-bits[j].start)) - 1);
+					counts[j] += ((value & mask[j]) == cmp[j]) ? (top_options.high_frequency ? 10 : 1) : 0;
+				}
+			}
+	}
+}
+
+static void parse_sensors(struct umr_asic *asic, uint32_t addr, struct umr_bitfield *bits, uint64_t *counts, uint32_t *mask, uint32_t *cmp, uint64_t addr_mask)
+{
+	int j;
+	int32_t value;
+
+	(void)addr;
+	(void)mask;
+	(void)cmp;
+	(void)addr_mask;
+
+	if (asic->fd.sensors < 0)
+		return;
+
+	for (j = 0; bits[j].regname; j++) {
+		lseek(asic->fd.sensors, bits[j].start * 4, SEEK_SET);
+		read(asic->fd.sensors, &value, 4);
+		switch (bits[j].stop & 0x0F) {
+			case SENSOR_IDENTITY:	counts[j] = value; break; // identity
+			case SENSOR_D1000:	counts[j] = value/1000; break; // divide by 1000 (e.g. KHz => MHz)
+			case SENSOR_D100:	counts[j] = value/100; break; // divide by 100 (e.g. 10KHz => MHz)
+		}
+	}
+}
+
+static void parse_drm(struct umr_asic *asic, uint32_t addr, struct umr_bitfield *bits, uint64_t *counts, uint32_t *mask, uint32_t *cmp, uint64_t addr_mask)
+{
+	int j;
+
+	(void)addr;
+	(void)mask;
+	(void)cmp;
+	(void)addr_mask;
+
+	if (asic->fd.drm < 0)
+		return;
+
+	analyze_fence_info(asic);
+
+	for (j = 0; bits[j].regname; j++) {
+		if (bits[j].start == AMDGPU_INFO_FENCES_EMITTED)
+			counts[j] = fence_emit_count;
+		else if (bits[j].start == AMDGPU_INFO_FENCES_SIGNALED)
+			counts[j] = fence_signal_count;
+		else if (bits[j].start == AMDGPU_INFO_FENCES_DELTA)
+			counts[j] = last_fence_emitted - last_fence_signaled;
+		else if (bits[j].start == AMDGPU_INFO_WAVES)
+			counts[j] = vi_count_waves(asic);
+		else
+			umr_query_drm(asic, bits[j].start, &counts[j]);
+	}
+}
+
+static void grab_vram(struct umr_asic *asic)
+{
+	char name[256];
+	FILE *f;
+	unsigned long total, free, used;
+
+	snprintf(name, sizeof(name)-1, "/sys/kernel/debug/dri/%d/amdgpu_vram_mm", asic->instance);
+	f = fopen(name, "rb");
+	if (f) {
+		fseek(f, -128, SEEK_END); // skip to end of file
+		memset(name, 0, sizeof name);
+		while (fgets(name, sizeof(name)-1, f)) {
+			if (memcmp(name, "total:", 6) == 0) {
+				if (sscanf(name, "total: %lu, used %lu free %lu", &total, &used, &free) == 3)
+					printw("\nVRAM: %lu/%lu (MiB)\n", (used * 4096) / 1048576, (total * 4096) / 1048576);
+				break;
+			}
+		}
+		fclose(f);
+	}
+}
+
+static void analyze_drm_info(struct umr_asic *asic)
+{
+	char region[256], name[256], line[256];
+	unsigned long old_pid, pid, id, size, tot_vram, tot_gtt;
+	FILE *f;
+
+	snprintf(name, sizeof(name)-1, "/sys/kernel/debug/dri/%d/amdgpu_gem_info", asic->instance);
+	f = fopen(name, "rb");
+	if (f) {
+		name[0] = 0;
+		old_pid = pid = tot_vram = tot_gtt = 0;
+		while (fgets(line, sizeof(line)-1, f)) {
+			if (sscanf(line, "pid %lu command %s:", &pid, region) == 2) {
+				if (name[0]) {
+					snprintf(line, sizeof(line)-1, "%s(%5lu)", name, old_pid);
+					printw("   %-30s: %10lu KiB VRAM, %10lu KiB GTT\n", line, tot_vram>>10, tot_gtt>>10);
+				}
+				tot_vram = tot_gtt = 0;
+				old_pid = pid;
+				strcpy(name, region);
+			} else {
+				sscanf(line, "\t0x%08lx: %lu byte %s @", &id, &size, region);
+				if (!strcmp(region, "VRAM"))
+					tot_vram += size;
+				else
+					tot_gtt += size;
+			}
+		}
+		if (name[0]) {
+			snprintf(line, sizeof(line)-1, "%s(%5lu)", name, old_pid);
+			printw("   %-30s: %10lu KiB VRAM, %10lu KiB GTT\n", line, tot_vram>>10, tot_gtt>>10);
+		}
+		fclose(f);
+	}
+	f = fopen("/sys/devices/virtual/drm/ttm/memory_accounting/kernel/used_memory", "rb");
+	if (f) {
+		if (fscanf(f, "%lu", &size) == 1)
+			printw("\nDMA: %lu KiB\n", size);
+		fclose(f);
+	}
+}
+
+
+void save_options(void)
+{
+	FILE *f;
+	char path[512];
+
+	sprintf(path, "%s/.umrtop", getenv("HOME"));
+	f = fopen(path, "w");
+	if (f) {
+		fprintf(f, "%d\n", top_options.wide);
+		fprintf(f, "%d\n", top_options.vram);
+		fprintf(f, "%d\n", top_options.high_precision);
+		fprintf(f, "%d\n", top_options.high_frequency);
+		fprintf(f, "%d\n", top_options.all);
+		fprintf(f, "%d\n", top_options.drm);
+		fprintf(f, "%d\n", top_options.vi.ta);
+		fprintf(f, "%d\n", top_options.vi.vgt);
+		fprintf(f, "%d\n", top_options.vi.uvd);
+		fprintf(f, "%d\n", top_options.vi.vce);
+		fprintf(f, "%d\n", top_options.vi.gfxpwr);
+		fprintf(f, "%d\n", top_options.vi.grbm);
+		fprintf(f, "%d\n", top_options.vi.memory_hub);
+		fprintf(f, "%d\n", top_options.vi.sdma);
+		fprintf(f, "%d\n", top_options.vi.sensors);
+		fclose(f);
+	}
+}
+
+void load_options(void)
+{
+	FILE *f;
+	char path[512];
+
+	memset(&top_options, 0, sizeof(top_options));
+
+	sprintf(path, "%s/.umrtop", getenv("HOME"));
+	f = fopen(path, "r");
+	if (f) {
+		fscanf(f, "%d\n", &top_options.wide);
+		fscanf(f, "%d\n", &top_options.vram);
+		fscanf(f, "%d\n", &top_options.high_precision);
+		fscanf(f, "%d\n", &top_options.high_frequency);
+		fscanf(f, "%d\n", &top_options.all);
+		fscanf(f, "%d\n", &top_options.drm);
+		fscanf(f, "%d\n", &top_options.vi.ta);
+		fscanf(f, "%d\n", &top_options.vi.vgt);
+		fscanf(f, "%d\n", &top_options.vi.uvd);
+		fscanf(f, "%d\n", &top_options.vi.vce);
+		fscanf(f, "%d\n", &top_options.vi.gfxpwr);
+		fscanf(f, "%d\n", &top_options.vi.grbm);
+		fscanf(f, "%d\n", &top_options.vi.memory_hub);
+		fscanf(f, "%d\n", &top_options.vi.sdma);
+		fscanf(f, "%d\n", &top_options.vi.sensors);
+		fclose(f);
+	} else {
+		// add some defaults to not be so boring
+		top_options.vi.grbm = 1;
+		top_options.vi.vgt = 1;
+		top_options.vi.ta = 1;
+	}
+}
+
+static struct {
+		char *name, *tag;
+		uint64_t counts[32];
+		int *opt, is_sensor;
+		uint32_t addr, mask[32], cmp[32];
+		uint64_t addr_mask;
+		struct umr_bitfield *bits;
+} stat_counters[64];
+
+#define ENTRY(_j, _name, _bits, _opt, _tag) do { int _i = (_j); stat_counters[_i].name = _name; stat_counters[_i].bits = _bits; stat_counters[_i].opt = _opt; stat_counters[_i].tag = _tag; } while (0)
+#define ENTRY_SENSOR(_j, _name, _bits, _opt, _tag) do { int _i = (_j); stat_counters[_i].name = _name; stat_counters[_i].bits = _bits; stat_counters[_i].opt = _opt; stat_counters[_i].tag = _tag; stat_counters[_i].is_sensor = 1; } while (0)
+
+static void vi_handle_keys(int i)
+{
+	switch(i) {
+	case 't':  top_options.vi.ta ^= 1; break;
+	case 'g':  top_options.vi.vgt ^= 1; break;
+	case 'G':  top_options.vi.gfxpwr ^= 1; break;
+	case 'u':  top_options.vi.uvd ^= 1; break;
+	case 'c':  top_options.vi.vce ^= 1; break;
+	case 's':  top_options.vi.grbm ^= 1; break;
+	case 'm':  top_options.vi.memory_hub ^= 1; break;
+	case 'd':  top_options.vi.sdma ^= 1; break;
+	case 'n':  top_options.vi.sensors ^= 1; break;
+	}
+}
+
+static void top_build_vi_program(struct umr_asic *asic)
+{
+	int i, j, k;
+	char *regname;
+
+	(void)asic;
+
+	stat_counters[0].bits = &stat_grbm_bits[0];
+	stat_counters[0].opt = &top_options.vi.grbm;
+	stat_counters[0].tag = "GRBM";
+
+	stat_counters[1].opt = &top_options.vi.grbm;
+	stat_counters[1].tag = stat_counters[0].tag;
+	stat_counters[1].name = "mmGRBM_STATUS2";
+	stat_counters[1].bits = &stat_grbm2_bits[0];
+
+	i = 2;
+
+	if (asic->config.gfx.family > 110)
+		ENTRY(i++, "mmRLC_GPM_STAT", &stat_rlc_gpm_bits[0], &top_options.vi.gfxpwr, "GFX PWR");
+
+	// sensors
+	if (asic->config.gfx.family == 135) {
+		// Carrizo/Stoney family
+		ENTRY_SENSOR(i++, "GFX_SCLK", &stat_carrizo_sensor_bits[0], &top_options.vi.sensors, "Sensors");
+	} else if (asic->config.gfx.family == 130) {
+		// Volcanic Islands Family
+		ENTRY_SENSOR(i++, "GFX_SCLK", &stat_vi_sensor_bits[0], &top_options.vi.sensors, "Sensors");
+	}
+
+	// More GFX bits
+	ENTRY(i++, "mmTA_STATUS", &stat_ta_bits[0], &top_options.vi.ta, "TA");
+	ENTRY(i++, "mmVGT_CNTL_STATUS", &stat_vgt_bits[0], &top_options.vi.vgt, "VGT");
+
+	// UVD registers
+		ENTRY(i++, "mmSRBM_STATUS", &stat_srbm_status_uvd_bits[0], &top_options.vi.uvd, "UVD");
+		k = i;
+		ENTRY(i++, "mmUVD_CGC_STATUS", &stat_uvdclk_bits[0], &top_options.vi.uvd, "UVD");
+		// set PG flag for all UVD registers
+		for (; k < i; k++) {
+			stat_counters[k].addr_mask = (1ULL << 23);  // UVD requires PG lock
+		}
+
+		k = j = i;
+		ENTRY(i++, "mmUVD_PGFSM_READ_TILE1", &stat_uvd_pgfsm1_bits[0], &top_options.vi.uvd, "UVD");
+		ENTRY(i++, "mmUVD_PGFSM_READ_TILE2", &stat_uvd_pgfsm2_bits[0], &top_options.vi.uvd, "UVD");
+		ENTRY(i++, "mmUVD_PGFSM_READ_TILE3", &stat_uvd_pgfsm3_bits[0], &top_options.vi.uvd, "UVD");
+		ENTRY(i++, "mmUVD_PGFSM_READ_TILE4", &stat_uvd_pgfsm4_bits[0], &top_options.vi.uvd, "UVD");
+		ENTRY(i++, "mmUVD_PGFSM_READ_TILE5", &stat_uvd_pgfsm5_bits[0], &top_options.vi.uvd, "UVD");
+		ENTRY(i++, "mmUVD_PGFSM_READ_TILE6", &stat_uvd_pgfsm6_bits[0], &top_options.vi.uvd, "UVD");
+		ENTRY(i++, "mmUVD_PGFSM_READ_TILE7", &stat_uvd_pgfsm7_bits[0], &top_options.vi.uvd, "UVD");
+
+		// set compare/mask for UVD TILE registers
+		for (; j < i; j++) {
+			stat_counters[j].cmp[0] = 0;
+			stat_counters[j].mask[0] = 3;
+			stat_counters[j].addr_mask = (1ULL << 23);  // require PG lock
+		}
+
+	// VCE registers
+		ENTRY(i++, "mmSRBM_STATUS2", &stat_srbm_status2_vce_bits[0], &top_options.vi.vce, "VCE");
+		k = i;
+
+		// set PG flag for all VCE registers
+		for (; k < i; k++) {
+			stat_counters[k].addr_mask = (1ULL << 23);  // VCE requires PG lock
+		}
+
+	// memory hub
+		k = i;
+		ENTRY(i++, "mmMC_HUB_MISC_STATUS", &stat_mc_hub_bits[0], &top_options.vi.memory_hub, "MC HUB");
+
+	// SDMA
+		k = i;
+		ENTRY(i++, "mmSRBM_STATUS2", &stat_sdma_bits[0], &top_options.vi.sdma, "SDMA");
+
+	// which SE to read ...
+	regname = calloc(1, 64);
+	if (options.use_bank)
+		snprintf(regname, 63, "mmGRBM_STATUS_SE%d", options.se_bank);
+	else
+		snprintf(regname, 63, "mmGRBM_STATUS");
+
+	stat_counters[0].name = regname;
+
+	top_options.handle_key = vi_handle_keys;
+	top_options.helptext =
+		"(u)vd v(c)e (G)FX_PWR (s)GRBM (t)a v(g)t (m)emory_hub \n"
+		"s(d)ma se(n)sors\n";
+
+}
+
+static void toggle_logger(void)
+{
+	int i, j;
+	top_options.logger ^= 1;
+
+	if (top_options.logger) {
+		char *p, name[512];
+		if (!(p = getenv("UMR_LOGGER")))
+			p = getenv("HOME");
+		sprintf(name, "%s/umr.log", p);
+		logfile = fopen(name, "a");
+
+		fprintf(logfile, "Time (seconds),");
+		for (i = 0; stat_counters[i].name; i++)
+			if (top_options.all || *stat_counters[i].opt)
+				for (j = 0; stat_counters[i].bits[j].regname != 0; j++)
+					fprintf(logfile, "%s.%s,", stat_counters[i].tag, stat_counters[i].bits[j].regname);
+		fprintf(logfile, "\n");
+	} else {
+		if (logfile)
+			fclose(logfile);
+		logfile = NULL;
+	}
+}
+
+void umr_top(struct umr_asic *asic)
+{
+	int i, j, k;
+	struct timespec req;
+	uint32_t rep;
+	time_t tt;
+	uint64_t ts;
+	char hostname[64] = { 0 };
+
+	if (getenv("HOSTNAME")) strcpy(hostname, getenv("HOSTNAME"));
+
+	// init stats
+	memset(&stat_counters, 0, sizeof stat_counters);
+	load_options();
+
+	// select an architecture ...
+	if (asic->family <= FAMILY_VI)
+		top_build_vi_program(asic);
+
+	// add DRM info
+	for (i = 0; stat_counters[i].name; i++);
+	ENTRY(i, "DRM", &stat_drm_bits[0], &top_options.drm, "DRM");
+	stat_counters[i].is_sensor = 2;
+
+	for (i = 0; stat_counters[i].name; i++)
+		if (stat_counters[i].is_sensor == 0)
+			grab_bits(stat_counters[i].name, asic, stat_counters[i].bits, &stat_counters[i].addr);
+
+	initscr();
+	start_color();
+	cbreak();
+	nodelay(stdscr, 1);
+	noecho();
+
+	init_pair(1, COLOR_BLUE, COLOR_BLACK);
+	init_pair(2, COLOR_GREEN, COLOR_BLACK);
+	init_pair(3, COLOR_YELLOW, COLOR_BLACK);
+	init_pair(4, COLOR_RED, COLOR_BLACK);
+
+	// setup loop
+	if (top_options.high_precision)
+		rep = 1000;
+	else
+		rep = 100;
+	req.tv_sec = 0;
+	req.tv_nsec = 1000000000/rep; // 10ms
+
+	ts = 0;
+	while (!top_options.quit) {
+		for (i = 0; stat_counters[i].name; i++)
+			memset(stat_counters[i].counts, 0, sizeof(stat_counters[i].counts[0])*32);
+
+		for (i = 0; i < (int)rep / (top_options.high_frequency ? 10 : 1); i++) {
+			for (j = 0; stat_counters[j].name; j++)
+				if (top_options.all || *stat_counters[j].opt) {
+					if (stat_counters[j].is_sensor == 0)
+						parse_bits(asic, stat_counters[j].addr, stat_counters[j].bits, stat_counters[j].counts, stat_counters[j].mask, stat_counters[j].cmp, stat_counters[j].addr_mask);
+					else if (i == 0 && stat_counters[j].is_sensor == 1) // only parse sensors on first go-around per display
+						parse_sensors(asic, stat_counters[j].addr, stat_counters[j].bits, stat_counters[j].counts, stat_counters[j].mask, stat_counters[j].cmp, stat_counters[j].addr_mask);
+					else if (i == 0 && stat_counters[j].is_sensor == 2) // only parse drm on first go-around per display
+						parse_drm(asic, stat_counters[j].addr, stat_counters[j].bits, stat_counters[j].counts, stat_counters[j].mask, stat_counters[j].cmp, stat_counters[j].addr_mask);
+				}
+			nanosleep(&req, NULL);
+			ts += (req.tv_nsec / 1000000);
+		}
+		move(0, 0);
+		clear();
+
+		if ((i = wgetch(stdscr)) != ERR) {
+			switch (i) {
+			case 'q':  top_options.quit = 1; break;
+			case 'l':  toggle_logger(); break;
+			case 'a':  top_options.all ^= 1; break;
+			case 'w':  top_options.wide ^= 1; break;
+			case 'v':  top_options.vram ^= 1; break;
+			case 'W':  save_options(); break;
+			case '1':
+				top_options.high_precision ^= 1;
+				if (top_options.high_precision)
+					rep = 1000;
+				else
+					rep = 100;
+
+				req.tv_sec = 0;
+				req.tv_nsec = 1000000000/rep; // 10ms
+				break;
+			case '2':
+				top_options.high_frequency ^= 1;
+				break;
+			case 'r': top_options.drm ^= 1; break;
+			default:
+				top_options.handle_key(i);
+			}
+		}
+
+		tt = time(NULL);
+		printw("(%s[%s]) %s%s -- %s",
+			hostname, asic->asicname,
+			top_options.logger ? "(logger enabled) " : "",
+			top_options.high_frequency ?
+				(top_options.high_precision ? "(sample @ 1ms, report @ 100ms)" : "(sample @ 10ms, report @ 100ms)") :
+				(top_options.high_precision ? "(sample @ 1ms, report @ 1000ms)" : "(sample @ 10ms, report @ 1000ms)"),
+			ctime(&tt));
+
+		// figure out padding
+		for (i = maxstrlen = 0; stat_counters[i].name; i++)
+			if (top_options.all || *stat_counters[i].opt)
+				for (j = 0; stat_counters[i].bits[j].regname; j++)
+					if (stat_counters[i].bits[j].start != 255 && (k = strlen(stat_counters[i].bits[j].regname)) > maxstrlen)
+						maxstrlen = k;
+		snprintf(namefmt, sizeof(namefmt)-1, "%%%ds => ", maxstrlen + 1);
+
+		print_j = 0;
+		if (logfile != NULL) {
+			struct timespec tp;
+			clock_gettime(CLOCK_MONOTONIC, &tp);
+			fprintf(logfile, "%f,", ((double)tp.tv_sec * 1000000000.0 + tp.tv_nsec) / 1000000000.0);
+		}
+		for (i = 0; stat_counters[i].name; i++) {
+			if (top_options.all || *stat_counters[i].opt) {
+				if (logfile != NULL) {
+					for (j = 0; stat_counters[i].bits[j].regname != 0; j++) {
+						if (stat_counters[i].bits[j].start != 255)
+							fprintf(logfile, "%llu,", (unsigned long long)stat_counters[i].counts[j]);
+					}
+				}
+				if (!i || strcmp(stat_counters[i-1].tag, stat_counters[i].tag)) {
+					if (print_j & (top_options.wide ? 3 : 1))
+						printw("\n");
+					printw("\n%s Bits:\n", stat_counters[i].tag);
+					print_j = 0;
+				}
+
+				if (stat_counters[i].is_sensor == 0)
+					print_counts(stat_counters[i].bits, stat_counters[i].counts);
+				else if (stat_counters[i].is_sensor == 1)
+					print_sensors(stat_counters[i].bits, stat_counters[i].counts);
+				else if (stat_counters[i].is_sensor == 2)
+					print_drm(stat_counters[i].bits, stat_counters[i].counts);
+			}
+		}
+		if (logfile != NULL) {
+			fprintf(logfile, "\n");
+		}
+
+		if (top_options.all || top_options.vram) {
+			if (print_j & (top_options.wide ? 3 : 1))
+				printw("\n");
+			grab_vram(asic);
+			analyze_drm_info(asic);
+		}
+		if (print_j & (top_options.wide ? 3 : 1))
+			printw("\n");
+		printw("\n(a)ll (w)ide (1)high_precision (2)high_frequency (W)rite (l)ogger\n(v)ram d(r)m\n%s", top_options.helptext);
+		refresh();
+	}
+	endwin();
+}
diff --git a/src/app/umr_lookup.c b/src/app/umr_lookup.c
new file mode 100644
index 0000000..3f3402a
--- /dev/null
+++ b/src/app/umr_lookup.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <inttypes.h>
+
+void umr_lookup(struct umr_asic *asic, char *address, char *value)
+{
+	int i, j, k;
+	uint32_t regno, num;
+
+	sscanf(address, "%"SCNx32, &regno);
+	sscanf(value, "%"SCNx32, &num);
+
+	for (i = 0; i < asic->no_blocks; i++)
+	for (j = 0; j < asic->blocks[i]->no_regs; j++)
+		if (asic->blocks[i]->regs[j].type == REG_MMIO &&
+		    asic->blocks[i]->regs[j].addr == regno) {
+			printf("%s => 0x%08lx\n", asic->blocks[i]->regs[j].regname, (unsigned long)num);
+			for (k = 0; k < asic->blocks[i]->regs[j].no_bits; k++) {
+				uint32_t v;
+				v = (1UL << (asic->blocks[i]->regs[j].bits[k].stop + 1 - asic->blocks[i]->regs[j].bits[k].start)) - 1;
+				v &= (num >> asic->blocks[i]->regs[j].bits[k].start);
+				asic->blocks[i]->regs[j].bits[k].bitfield_print(asic, asic->asicname, asic->blocks[i]->ipname, asic->blocks[i]->regs[j].regname, asic->blocks[i]->regs[j].bits[k].regname, asic->blocks[i]->regs[j].bits[k].start, asic->blocks[i]->regs[j].bits[k].stop, v);
+			}
+		}
+}
+
diff --git a/src/lib/asic/bonaire.c b/src/lib/asic/bonaire.c
new file mode 100644
index 0000000..659d25e
--- /dev/null
+++ b/src/lib/asic/bonaire.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_bonaire(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("bonaire", FAMILY_CIK,
+			umr_create_uvd42(options),
+			umr_create_vce2(options),
+			umr_create_gmc70(options),
+			umr_create_dce80(options),
+			umr_create_gfx70(options),
+			umr_create_smu700(options),
+			umr_create_oss20(options),
+			umr_create_bif41(options),
+			NULL);
+}
diff --git a/src/lib/asic/carrizo.c b/src/lib/asic/carrizo.c
new file mode 100644
index 0000000..3aff309
--- /dev/null
+++ b/src/lib/asic/carrizo.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_carrizo(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("carrizo", FAMILY_VI,
+			umr_create_uvd6(options),
+			umr_create_vce3(options),
+			umr_create_gmc81(options),
+			umr_create_dce110(options),
+			umr_create_gfx80(options),
+			umr_create_smu80(options),
+			umr_create_oss30(options),
+			umr_create_bif51(options),
+			NULL);
+}
diff --git a/src/lib/asic/fiji.c b/src/lib/asic/fiji.c
new file mode 100644
index 0000000..46e452b
--- /dev/null
+++ b/src/lib/asic/fiji.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_fiji(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("fiji", FAMILY_VI,
+			umr_create_uvd6(options),
+			umr_create_vce3(options),
+			umr_create_gmc81(options),
+			umr_create_dce100(options),
+			umr_create_gfx80(options),
+			umr_create_smu713(options),
+			umr_create_oss30(options),
+			umr_create_bif50(options),
+			NULL);
+}
diff --git a/src/lib/asic/hainan.c b/src/lib/asic/hainan.c
new file mode 100644
index 0000000..ced930f
--- /dev/null
+++ b/src/lib/asic/hainan.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_hainan(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("hainan", FAMILY_SI,
+			umr_create_gmc60(options),
+			umr_create_gfx60(options),
+			umr_create_oss10(options),
+			umr_create_smu60(options),
+			umr_create_bif30(options),
+			NULL);
+}
diff --git a/src/lib/asic/kaveri.c b/src/lib/asic/kaveri.c
new file mode 100644
index 0000000..2afc061
--- /dev/null
+++ b/src/lib/asic/kaveri.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_kaveri(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("kaveri", FAMILY_CIK,
+			umr_create_uvd42(options),
+			umr_create_vce2(options),
+			umr_create_gmc70(options),
+			umr_create_dce80(options),
+			umr_create_gfx70(options),
+			umr_create_smu700(options),
+			umr_create_oss20(options),
+			umr_create_bif41(options),
+			NULL);
+}
diff --git a/src/lib/asic/oland.c b/src/lib/asic/oland.c
new file mode 100644
index 0000000..339a29e
--- /dev/null
+++ b/src/lib/asic/oland.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_oland(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("oland", FAMILY_SI,
+			umr_create_uvd40(options),
+			umr_create_vce1(options),
+			umr_create_gmc60(options),
+			umr_create_dce60(options), // technically is DCEv64...
+			umr_create_gfx60(options),
+			umr_create_oss10(options),
+			umr_create_smu60(options),
+			umr_create_bif30(options),
+			NULL);
+}
diff --git a/src/lib/asic/pitcairn.c b/src/lib/asic/pitcairn.c
new file mode 100644
index 0000000..7d07a33
--- /dev/null
+++ b/src/lib/asic/pitcairn.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_pitcairn(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("pitcairn", FAMILY_SI,
+			umr_create_uvd40(options),
+			umr_create_vce1(options),
+			umr_create_gmc60(options),
+			umr_create_dce60(options),
+			umr_create_gfx60(options),
+			umr_create_oss10(options),
+			umr_create_smu60(options),
+			umr_create_bif30(options),
+			NULL);
+}
diff --git a/src/lib/asic/polaris10.c b/src/lib/asic/polaris10.c
new file mode 100644
index 0000000..afcdc9a
--- /dev/null
+++ b/src/lib/asic/polaris10.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_polaris10(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("polaris10", FAMILY_VI,
+			umr_create_uvd6(options),
+			umr_create_vce3(options),
+			umr_create_gmc81(options),
+			umr_create_dce112(options),
+			umr_create_gfx80(options),
+			umr_create_smu713(options),
+			umr_create_oss30(options),
+			umr_create_bif51(options),
+			NULL);
+}
diff --git a/src/lib/asic/polaris11.c b/src/lib/asic/polaris11.c
new file mode 100644
index 0000000..5749651
--- /dev/null
+++ b/src/lib/asic/polaris11.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_polaris11(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("polaris11", FAMILY_VI,
+			umr_create_uvd6(options),
+			umr_create_vce3(options),
+			umr_create_gmc81(options),
+			umr_create_dce112(options),
+			umr_create_gfx80(options),
+			umr_create_smu713(options),
+			umr_create_oss30(options),
+			umr_create_bif51(options),
+			NULL);
+}
diff --git a/src/lib/asic/polaris12.c b/src/lib/asic/polaris12.c
new file mode 100644
index 0000000..0ccadb8
--- /dev/null
+++ b/src/lib/asic/polaris12.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_polaris12(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("polaris12", FAMILY_VI,
+			umr_create_uvd6(options),
+			umr_create_vce3(options),
+			umr_create_gmc81(options),
+			umr_create_dce112(options),
+			umr_create_gfx80(options),
+			umr_create_smu713(options),
+			umr_create_oss30(options),
+			umr_create_bif51(options),
+			NULL);
+}
diff --git a/src/lib/asic/stoney.c b/src/lib/asic/stoney.c
new file mode 100644
index 0000000..6cfd9a5
--- /dev/null
+++ b/src/lib/asic/stoney.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_stoney(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("stoney", FAMILY_VI,
+			umr_create_uvd6(options),
+			umr_create_vce3(options),
+			umr_create_gmc81(options),
+			umr_create_dce110(options),
+			umr_create_gfx81(options),
+			umr_create_smu80(options),
+			umr_create_oss30(options),
+			umr_create_bif51(options),
+			NULL);
+}
diff --git a/src/lib/asic/tahiti.c b/src/lib/asic/tahiti.c
new file mode 100644
index 0000000..e9ab325
--- /dev/null
+++ b/src/lib/asic/tahiti.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_tahiti(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("tahiti", FAMILY_SI,
+			umr_create_uvd40(options),
+			umr_create_vce1(options),
+			umr_create_gmc60(options),
+			umr_create_dce60(options),
+			umr_create_gfx60(options),
+			umr_create_oss10(options),
+			umr_create_smu60(options),
+			umr_create_bif30(options),
+			NULL);
+}
diff --git a/src/lib/asic/tonga.c b/src/lib/asic/tonga.c
new file mode 100644
index 0000000..d1b255f
--- /dev/null
+++ b/src/lib/asic/tonga.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_tonga(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("tonga", FAMILY_VI,
+			umr_create_uvd5(options),
+			umr_create_vce3(options),
+			umr_create_gmc81(options),
+			umr_create_dce100(options),
+			umr_create_gfx80(options),
+			umr_create_smu712(options),
+			umr_create_oss30(options),
+			umr_create_bif50(options),
+			NULL);
+}
diff --git a/src/lib/asic/topaz.c b/src/lib/asic/topaz.c
new file mode 100644
index 0000000..49868ba
--- /dev/null
+++ b/src/lib/asic/topaz.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_topaz(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("topaz", FAMILY_VI,
+			umr_create_gmc70(options),
+			umr_create_gfx80(options),
+			umr_create_oss20(options),
+			umr_create_smu711(options),
+			umr_create_bif50(options),
+			NULL);
+}
diff --git a/src/lib/asic/verde.c b/src/lib/asic/verde.c
new file mode 100644
index 0000000..706d84f
--- /dev/null
+++ b/src/lib/asic/verde.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+struct umr_asic *umr_create_verde(struct umr_options *options)
+{
+	return
+		umr_create_asic_helper("verde", FAMILY_SI,
+			umr_create_uvd40(options),
+			umr_create_vce1(options),
+			umr_create_gmc60(options),
+			umr_create_dce60(options),
+			umr_create_gfx60(options),
+			umr_create_oss10(options),
+			umr_create_smu60(options),
+			umr_create_bif30(options),
+			NULL);
+}
diff --git a/src/lib/bitfield_print.c b/src/lib/bitfield_print.c
new file mode 100644
index 0000000..f925700
--- /dev/null
+++ b/src/lib/bitfield_print.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+void umr_bitfield_default(struct umr_asic *asic, char *asicname, char *ipname, char *regname, char *bitname, int start, int stop, uint32_t value)
+{
+	char buf[256], fpath[256];
+	struct umr_options options = asic->options;
+	if (options.bitfields) {
+		snprintf(fpath, sizeof(fpath)-1, "%s.%s.%s%s%s.", asicname, ipname, CYAN, regname, RST);
+		snprintf(buf, sizeof(buf)-1, "\t%s%s%s%s[%s%d:%d%s]",
+			options.bitfields_full ? fpath : ".",
+			RED, bitname, RST,
+			BLUE, start, stop, RST);
+		printf("%-65s == %s%8lu%s (%s0x%08lx%s)\n", buf,
+			YELLOW, (unsigned long)value, RST,
+			YELLOW, (unsigned long)value, RST);
+	}
+}
+
diff --git a/src/lib/close_asic.c b/src/lib/close_asic.c
new file mode 100644
index 0000000..e1d5916
--- /dev/null
+++ b/src/lib/close_asic.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#define cond_close(x) do { if ((x) >= 0) close((x)); } while(0);
+
+void umr_close_asic(struct umr_asic *asic)
+{
+	int x;
+	if (asic) {
+		cond_close(asic->fd.mmio);
+		cond_close(asic->fd.didt);
+		cond_close(asic->fd.pcie);
+		cond_close(asic->fd.smc);
+		cond_close(asic->fd.sensors);
+		cond_close(asic->fd.wave);
+		cond_close(asic->fd.vram);
+		cond_close(asic->fd.gpr);
+		cond_close(asic->fd.drm);
+		if (asic->pci.mem != NULL) {
+			// free PCI mapping
+			pci_device_unmap_range(asic->pci.pdevice, asic->pci.mem, asic->pci.pdevice->regions[asic->pci.region].size);
+			pci_system_cleanup();
+		}
+		for (x = 0; x < asic->no_blocks; x++) {
+			free(asic->blocks[x]->regs);
+			free(asic->blocks[x]);
+		}
+		free(asic->blocks);
+		free(asic);
+	}
+}
diff --git a/src/lib/create_asic_helper.c b/src/lib/create_asic_helper.c
new file mode 100644
index 0000000..d0ee34a
--- /dev/null
+++ b/src/lib/create_asic_helper.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+#include <stdarg.h>
+
+struct umr_asic *umr_create_asic_helper(char *name, int family, ...)
+{
+	struct umr_asic *asic;
+	struct umr_ip_block *ip;
+	va_list ap;
+	int x;
+	
+	asic = calloc(1, sizeof(*asic));
+	if (!asic) {
+		return NULL;
+	}
+	asic->asicname = name;
+	asic->family   = family;
+
+	// count asics
+	va_start(ap, family);
+	ip = va_arg(ap, struct umr_ip_block *);
+	while (ip) {
+		asic->no_blocks++;
+		ip = va_arg(ap, struct umr_ip_block *);
+	}
+	va_end(ap);
+
+	asic->blocks = calloc(asic->no_blocks, sizeof(struct umr_ip_block *));
+	if (!asic->blocks) {
+		free(asic);
+		return NULL;
+	}
+
+	// copy them
+	va_start(ap, family);
+	ip = va_arg(ap, struct umr_ip_block *);
+	x  = 0;
+	while (ip) {
+		asic->blocks[x++] = ip;
+		ip = va_arg(ap, struct umr_ip_block *);
+	}
+	va_end(ap);
+
+	return asic;
+}
diff --git a/src/lib/discover.c b/src/lib/discover.c
new file mode 100644
index 0000000..b58d3cc
--- /dev/null
+++ b/src/lib/discover.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+static int is_did_match(struct umr_asic *asic, unsigned did)
+{
+	struct umr_asic *tmp;
+	int r = 0, q;
+
+	q = asic->options.quiet;
+	asic->options.quiet = 1;
+
+	tmp = umr_discover_asic_by_did(&asic->options, did);
+	if (tmp) {
+		if (!strcmp(tmp->asicname, asic->asicname)) {
+			asic->did = did;
+			r = 1;
+		}
+		umr_close_asic(tmp);
+	}
+	asic->options.quiet = q;
+	return r;
+}
+
+
+struct umr_asic *umr_discover_asic(struct umr_options *options)
+{
+	char driver[256], name[256], fname[256];
+	FILE *f;
+	unsigned did;
+	struct umr_asic *asic;
+
+	if (options->forcedid < 0) {
+		snprintf(name, sizeof(name)-1, "/sys/kernel/debug/dri/%d/name", options->instance);
+		f = fopen(name, "r");
+		if (!f) {
+			int found = 0;
+			if (!options->quiet) {
+				f = popen("lsmod | grep ^amdgpu", "r");
+				while (fgets(name, sizeof(name)-1, f)) {
+					if (strstr(name, "amdgpu"))
+						found = 1;
+				}
+				pclose(f);
+
+				perror("Cannot open DRI name under debugfs");
+				if (!found)
+					printf("ERROR: amdgpu.ko is not loaded.\n");
+				else
+					printf("ERROR: amdgpu.ko is loaded but /sys/kernel/debug/dri/%d/name is not found\n", options->instance);
+			}
+			return NULL;
+		}
+		fscanf(f, "%s %s %s\n", driver, name, driver);
+		fclose(f);
+
+		// strip off dev= for kernels > 4.7
+		if (strstr(name, "dev="))
+			memmove(name, name+4, strlen(name)-3);
+
+		snprintf(driver, sizeof(driver)-1, "/sys/bus/pci/devices/%s/device", name);
+		f = fopen(driver, "r");
+		if (!f) {
+			if (!options->quiet) perror("Cannot open PCI device name under sysfs (is a display attached?)");
+			return NULL;
+		}
+		fscanf(f, "0x%04x", &did);
+		fclose(f);
+		asic = umr_discover_asic_by_did(options, did);
+	} else {
+		if (options->dev_name[0])
+			asic = umr_discover_asic_by_name(options, options->dev_name);
+		else
+			asic = umr_discover_asic_by_did(options, options->forcedid);
+	}
+
+	if (asic) {
+		memcpy(&asic->options, options, sizeof(*options));
+		snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_regs", asic->instance);
+		asic->fd.mmio = open(fname, O_RDWR);
+		snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_regs_didt", asic->instance);
+		asic->fd.didt = open(fname, O_RDWR);
+		snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_regs_pcie", asic->instance);
+		asic->fd.pcie = open(fname, O_RDWR);
+		snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_regs_smc", asic->instance);
+		asic->fd.smc = open(fname, O_RDWR);
+		snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_sensors", asic->instance);
+		asic->fd.sensors = open(fname, O_RDWR);
+		snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_wave", asic->instance);
+		asic->fd.wave = open(fname, O_RDWR);
+		snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_vram", asic->instance);
+		asic->fd.vram = open(fname, O_RDWR);
+		snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_gpr", asic->instance);
+		asic->fd.gpr = open(fname, O_RDWR);
+		snprintf(fname, sizeof(fname)-1, "/dev/dri/card%d", asic->instance);
+		asic->fd.drm = open(fname, O_RDWR);
+		// if appending to the fd list remember to update close_asic() and discover_by_did()...
+
+		if (options->use_pci) {
+			// init PCI mapping
+			int use_region;
+			void *pcimem_v;
+			struct pci_device_iterator *pci_iter;
+			pciaddr_t pci_region_addr;
+
+			pci_system_init();
+			pci_iter = pci_id_match_iterator_create(NULL);
+			if (!pci_iter) {
+				fprintf(stderr, "Cannot create PCI iterator");
+				goto err_pci;
+			}
+			do {
+				asic->pci.pdevice = pci_device_next(pci_iter);
+			} while (asic->pci.pdevice && !(asic->pci.pdevice->vendor_id == 0x1002 && is_did_match(asic, asic->pci.pdevice->device_id)));
+
+			if (!asic->pci.pdevice) {
+				fprintf(stderr, "Could not find ASIC with DID of %04lx\n", (unsigned long)asic->did);
+				goto err_pci;
+			}
+			pci_iterator_destroy(pci_iter);
+			pci_device_probe(asic->pci.pdevice);
+
+			use_region = 6;
+			// try to detect based on ASIC family
+			if (asic->family <= FAMILY_SI) {
+				// try region 2 for SI
+				if (	asic->pci.pdevice->regions[2].is_64 == 0 &&
+					asic->pci.pdevice->regions[2].is_prefetchable == 0 &&
+					asic->pci.pdevice->regions[2].is_IO == 0) {
+						use_region = 2;
+				}
+			} else if (asic->family <= FAMILY_VI) {
+				// try region 5 for CIK..VI
+				if (	asic->pci.pdevice->regions[5].is_64 == 0 &&
+					asic->pci.pdevice->regions[5].is_prefetchable == 0 &&
+					asic->pci.pdevice->regions[5].is_IO == 0) {
+						use_region = 5;
+				}
+			}
+
+			// scan for a 256K/512K region
+			if (use_region == 6) {
+				for (use_region = 0; use_region < 6; use_region++)
+					if ((asic->family < FAMILY_NEXT && asic->pci.pdevice->regions[use_region].size == (256UL * 1024)) ||
+					    (asic->family == FAMILY_NEXT && asic->pci.pdevice->regions[use_region].size == (512UL * 1024)))
+						break;
+			}
+
+			if (use_region == 6) {
+				fprintf(stderr, "Could not find PCI region (debugfs mode might still work)\n");
+				goto err_pci;
+			}
+			asic->pci.region = use_region;
+
+			pci_region_addr = asic->pci.pdevice->regions[use_region].base_addr;
+			if (pci_device_map_range(asic->pci.pdevice, pci_region_addr, asic->pci.pdevice->regions[use_region].size, PCI_DEV_MAP_FLAG_WRITABLE, &pcimem_v)) {
+				fprintf(stderr, "Could not map PCI memory\n");
+				goto err_pci;
+			}
+			asic->pci.mem = pcimem_v;
+		}
+	}
+	return asic;
+err_pci:
+	umr_close_asic(asic);
+	return NULL;
+}
+
diff --git a/src/lib/discover_by_did.c b/src/lib/discover_by_did.c
new file mode 100644
index 0000000..2afb118
--- /dev/null
+++ b/src/lib/discover_by_did.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+static const struct {
+	uint32_t did;
+	struct umr_asic *(*create)(struct umr_options *option);
+} devices[] = {
+	{ 0x1304, &umr_create_kaveri },
+	{ 0x1305, &umr_create_kaveri },
+	{ 0x1306, &umr_create_kaveri },
+	{ 0x1307, &umr_create_kaveri },
+	{ 0x1309, &umr_create_kaveri },
+	{ 0x130A, &umr_create_kaveri },
+	{ 0x130B, &umr_create_kaveri },
+	{ 0x130C, &umr_create_kaveri },
+	{ 0x130D, &umr_create_kaveri },
+	{ 0x130E, &umr_create_kaveri },
+	{ 0x130F, &umr_create_kaveri },
+	{ 0x1310, &umr_create_kaveri },
+	{ 0x1311, &umr_create_kaveri },
+	{ 0x1312, &umr_create_kaveri },
+	{ 0x1313, &umr_create_kaveri },
+	{ 0x1315, &umr_create_kaveri },
+	{ 0x1316, &umr_create_kaveri },
+	{ 0x1317, &umr_create_kaveri },
+	{ 0x1318, &umr_create_kaveri },
+	{ 0x131B, &umr_create_kaveri },
+	{ 0x131C, &umr_create_kaveri },
+	{ 0x131D, &umr_create_kaveri },
+	{ 0x6600, &umr_create_oland },
+	{ 0x6601, &umr_create_oland },
+	{ 0x6602, &umr_create_oland },
+	{ 0x6603, &umr_create_oland },
+	{ 0x6604, &umr_create_oland },
+	{ 0x6605, &umr_create_oland },
+	{ 0x6606, &umr_create_oland },
+	{ 0x6607, &umr_create_oland },
+	{ 0x6608, &umr_create_oland },
+	{ 0x6610, &umr_create_oland },
+	{ 0x6611, &umr_create_oland },
+	{ 0x6613, &umr_create_oland },
+	{ 0x6617, &umr_create_oland },
+	{ 0x6620, &umr_create_oland },
+	{ 0x6621, &umr_create_oland },
+	{ 0x6623, &umr_create_oland },
+	{ 0x6631, &umr_create_oland },
+	{ 0x6658, &umr_create_bonaire },
+	{ 0x665F, &umr_create_bonaire },
+	{ 0x6660, &umr_create_hainan },
+	{ 0x6663, &umr_create_hainan },
+	{ 0x6664, &umr_create_hainan },
+	{ 0x6665, &umr_create_hainan },
+	{ 0x6667, &umr_create_hainan },
+	{ 0x666F, &umr_create_hainan },
+	{ 0x6780, &umr_create_tahiti },
+	{ 0x6784, &umr_create_tahiti },
+	{ 0x6788, &umr_create_tahiti },
+	{ 0x678A, &umr_create_tahiti },
+	{ 0x6790, &umr_create_tahiti },
+	{ 0x6791, &umr_create_tahiti },
+	{ 0x6792, &umr_create_tahiti },
+	{ 0x6798, &umr_create_tahiti },
+	{ 0x6799, &umr_create_tahiti },
+	{ 0x679A, &umr_create_tahiti },
+	{ 0x679B, &umr_create_tahiti },
+	{ 0x679E, &umr_create_tahiti },
+	{ 0x679F, &umr_create_tahiti },
+	{ 0x67C0, &umr_create_polaris10 },
+	{ 0x67C1, &umr_create_polaris10 },
+	{ 0x67C2, &umr_create_polaris10 },
+	{ 0x67C4, &umr_create_polaris10 },
+	{ 0x67C7, &umr_create_polaris10 },
+	{ 0x67C8, &umr_create_polaris10 },
+	{ 0x67C9, &umr_create_polaris10 },
+	{ 0x67CA, &umr_create_polaris10 },
+	{ 0x67CC, &umr_create_polaris10 },
+	{ 0x67CF, &umr_create_polaris10 },
+	{ 0x67DF, &umr_create_polaris10 },
+	{ 0x67E0, &umr_create_polaris11 },
+	{ 0x67E1, &umr_create_polaris11 },
+	{ 0x67E3, &umr_create_polaris11 },
+	{ 0x67E7, &umr_create_polaris11 },
+	{ 0x67E8, &umr_create_polaris11 },
+	{ 0x67E9, &umr_create_polaris11 },
+	{ 0x67EB, &umr_create_polaris11 },
+	{ 0x67EF, &umr_create_polaris11 },
+	{ 0x67FF, &umr_create_polaris11 },
+	{ 0x6800, &umr_create_pitcairn },
+	{ 0x6801, &umr_create_pitcairn },
+	{ 0x6802, &umr_create_pitcairn },
+	{ 0x6806, &umr_create_pitcairn },
+	{ 0x6808, &umr_create_pitcairn },
+	{ 0x6809, &umr_create_pitcairn },
+	{ 0x6810, &umr_create_pitcairn },
+	{ 0x6811, &umr_create_pitcairn },
+	{ 0x6816, &umr_create_pitcairn },
+	{ 0x6817, &umr_create_pitcairn },
+	{ 0x6818, &umr_create_pitcairn },
+	{ 0x6819, &umr_create_pitcairn },
+	{ 0x6820, &umr_create_verde },
+	{ 0x6821, &umr_create_verde },
+	{ 0x6822, &umr_create_verde },
+	{ 0x6823, &umr_create_verde },
+	{ 0x6824, &umr_create_verde },
+	{ 0x6825, &umr_create_verde },
+	{ 0x6826, &umr_create_verde },
+	{ 0x6827, &umr_create_verde },
+	{ 0x6828, &umr_create_verde },
+	{ 0x6829, &umr_create_verde },
+	{ 0x682A, &umr_create_verde },
+	{ 0x682B, &umr_create_verde },
+	{ 0x682C, &umr_create_verde },
+	{ 0x682D, &umr_create_verde },
+	{ 0x682F, &umr_create_verde },
+	{ 0x6830, &umr_create_verde },
+	{ 0x6831, &umr_create_verde },
+	{ 0x6835, &umr_create_verde },
+	{ 0x6837, &umr_create_verde },
+	{ 0x6838, &umr_create_verde },
+	{ 0x6839, &umr_create_verde },
+	{ 0x683B, &umr_create_verde },
+	{ 0x683D, &umr_create_verde },
+	{ 0x683F, &umr_create_verde },
+	{ 0x6900, &umr_create_topaz },
+	{ 0x6901, &umr_create_topaz },
+	{ 0x6902, &umr_create_topaz },
+	{ 0x6903, &umr_create_topaz },
+	{ 0x6907, &umr_create_topaz },
+	{ 0x6920, &umr_create_tonga  },
+	{ 0x6921, &umr_create_tonga  },
+	{ 0x6928, &umr_create_tonga  },
+	{ 0x6929, &umr_create_tonga  },
+	{ 0x692B, &umr_create_tonga  },
+	{ 0x692F, &umr_create_tonga  },
+	{ 0x6930, &umr_create_tonga  },
+	{ 0x6938, &umr_create_tonga  },
+	{ 0x6939, &umr_create_tonga  },
+	{ 0x6981, &umr_create_polaris12 },
+	{ 0x6985, &umr_create_polaris12 },
+	{ 0x6986, &umr_create_polaris12 },
+	{ 0x6987, &umr_create_polaris12 },
+	{ 0x698F, &umr_create_polaris12 },
+	{ 0x7300, &umr_create_fiji   },
+	{ 0x730F, &umr_create_fiji   },
+	{ 0x9870, &umr_create_carrizo },
+	{ 0x9874, &umr_create_carrizo },
+	{ 0x9875, &umr_create_carrizo },
+	{ 0x9876, &umr_create_carrizo },
+	{ 0x9877, &umr_create_carrizo },
+	{ 0x98E4, &umr_create_stoney },
+};
+
+struct umr_asic *umr_discover_asic_by_did(struct umr_options *options, long did)
+{
+	unsigned x;
+	struct umr_asic *asic;
+
+	asic = NULL;
+	for (x = 0; x < (sizeof(devices)/sizeof(devices[0])); x++)
+		if (devices[x].did == did)
+			asic = devices[x].create(options);
+
+	if (asic) {
+		asic->did = did;
+		asic->instance = options->instance;
+		umr_scan_config(asic);
+
+		// set all file handles to -1 (so a call to close_asic won't close handle 0)
+		asic->fd.mmio = -1;
+		asic->fd.didt = -1;
+		asic->fd.pcie = -1;
+		asic->fd.smc = -1;
+		asic->fd.sensors = -1;
+		asic->fd.wave = -1;
+		asic->fd.vram = -1;
+		asic->fd.gpr = -1;
+		asic->fd.drm = -1;
+	} else {
+		if (!options->quiet && !options->dev_name[0])
+			printf("ERROR: Device 0x%04lx not found in UMR device table\n", did);
+	}
+
+	return asic;
+}
+
diff --git a/src/lib/discover_by_name.c b/src/lib/discover_by_name.c
new file mode 100644
index 0000000..856948c
--- /dev/null
+++ b/src/lib/discover_by_name.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+static const struct {
+	char *name;
+	struct umr_asic *(*create)(struct umr_options *option);
+} devices[] = {
+	{ "kaveri", &umr_create_kaveri },
+	{ "oland", &umr_create_oland },
+	{ "bonaire", &umr_create_bonaire },
+	{ "hainan", &umr_create_hainan },
+	{ "tahiti", &umr_create_tahiti },
+	{ "polaris10", &umr_create_polaris10 },
+	{ "polaris11", &umr_create_polaris11 },
+	{ "polaris12", &umr_create_polaris12 },
+	{ "pitcairn", &umr_create_pitcairn },
+	{ "verde", &umr_create_verde },
+	{ "topaz", &umr_create_topaz },
+	{ "tonga", &umr_create_tonga  },
+	{ "fiji", &umr_create_fiji   },
+	{ "carrizo", &umr_create_carrizo },
+	{ "stoney", &umr_create_stoney },
+};
+
+struct umr_asic *umr_discover_asic_by_name(struct umr_options *options, char *name)
+{
+	unsigned x;
+	struct umr_asic *asic, *tmp;
+
+	asic = NULL;
+	for (x = 0; x < (sizeof(devices)/sizeof(devices[0])); x++)
+		if (!strcmp(devices[x].name, name))
+			asic = devices[x].create(options);
+
+	if (asic) {
+		asic->did = 0;
+		if (options->instance == -1) {
+			// try and discover an instance that works
+			struct umr_options tmp_opt;
+			memset(&tmp_opt, 0, sizeof(tmp_opt));
+			tmp_opt.forcedid = -1;
+			tmp_opt.quiet = 1;
+			for (x = 0; x < 10; x++) {
+				tmp_opt.instance = x;
+				tmp = umr_discover_asic(&tmp_opt);
+				if (tmp) {
+					if (!strcmp(tmp->asicname, name)) {
+						asic->instance = x;
+						umr_close_asic(tmp);
+						break;
+					}
+					umr_close_asic(tmp);
+				}
+			}
+		} else {
+			asic->instance = options->instance;
+		}
+		umr_scan_config(asic);
+	} else {
+		printf("ERROR: Device %s not found in UMR device table\n", name);
+	}
+
+	return asic;
+}
+
diff --git a/src/lib/dump_ib.c b/src/lib/dump_ib.c
new file mode 100644
index 0000000..f88ed3f
--- /dev/null
+++ b/src/lib/dump_ib.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <inttypes.h>
+
+void umr_dump_ib(struct umr_asic *asic, struct umr_ring_decoder *decoder)
+{
+	uint32_t *data = NULL, x;
+
+	printf("Dumping IB at VMID:%u 0x%llx of %u words\n",
+		(unsigned)decoder->next_ib_info.vmid,
+		(unsigned long long)decoder->next_ib_info.ib_addr,
+		(unsigned)decoder->next_ib_info.size/4);
+
+	// read IB
+	data = calloc(sizeof(*data), decoder->next_ib_info.size/sizeof(*data));
+	if (data && !umr_read_vram(asic, decoder->next_ib_info.vmid, decoder->next_ib_info.ib_addr, decoder->next_ib_info.size, data)) {
+	// dump IB
+		for (x = 0; x < decoder->next_ib_info.size/4; x++) {
+			printf("IB[%5u] = 0x%08lx ... ", (unsigned)x, (unsigned long)data[x]);
+			umr_print_decode(asic, decoder, data[x]);
+			printf("\n");
+		}
+	}
+	free(data);
+	printf("\n");
+}
diff --git a/src/lib/find_reg.c b/src/lib/find_reg.c
new file mode 100644
index 0000000..957f6a7
--- /dev/null
+++ b/src/lib/find_reg.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+uint32_t umr_find_reg(struct umr_asic *asic, char *regname)
+{
+	int i, j;
+
+	for (i = 0; i < asic->no_blocks; i++)
+		for (j = 0; j < asic->blocks[i]->no_regs; j++)
+			if (!strcmp(asic->blocks[i]->regs[j].regname, regname))
+				return asic->blocks[i]->regs[j].addr;
+	fprintf(stderr, "BUG: reg [%s] not found on asic [%s]\n", regname, asic->asicname);
+	return 0;
+}
+
+struct umr_reg *umr_find_reg_data(struct umr_asic *asic, char *regname)
+{
+	int i, j;
+
+	for (i = 0; i < asic->no_blocks; i++)
+		for (j = 0; j < asic->blocks[i]->no_regs; j++)
+			if (!strcmp(asic->blocks[i]->regs[j].regname, regname))
+				return &asic->blocks[i]->regs[j];
+	fprintf(stderr, "BUG: reg [%s] not found on asic [%s]\n", regname, asic->asicname);
+	return NULL;
+}
diff --git a/src/lib/grab_frame.c b/src/lib/grab_frame.c
new file mode 100644
index 0000000..7063ac2
--- /dev/null
+++ b/src/lib/grab_frame.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <inttypes.h>
+
+// note: this currently assumes the FB isn't panned or otherwise distorted...
+
+int umr_grab_framebuffer(struct umr_asic *asic, void **fb, uint32_t *size)
+{
+	uint32_t width, height, bpp=4, control_format, control_depth, tmp;
+	uint64_t fb_addr;
+
+	width   = umr_read_reg_by_name(asic, "mmGRPH_X_END");
+	height  = umr_read_reg_by_name(asic, "mmGRPH_Y_END");
+	tmp     = umr_read_reg_by_name(asic, "mmGRPH_PRIMARY_SURFACE_ADDRESS");
+	fb_addr = umr_bitslice_reg_by_name(asic, "mmGRPH_PRIMARY_SURFACE_ADDRESS", "GRPH_PRIMARY_SURFACE_ADDRESS", tmp);
+	fb_addr <<= 8;
+	tmp     = umr_read_reg_by_name(asic, "mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH");
+	fb_addr |= ((uint64_t)tmp) << 32;
+
+	tmp     = umr_read_reg_by_name(asic, "mmGRPH_CONTROL");
+	control_depth  = umr_bitslice_reg_by_name(asic, "mmGRPH_CONTROL", "GRPH_DEPTH", tmp);
+	control_format = umr_bitslice_reg_by_name(asic, "mmGRPH_CONTROL", "GRPH_FORMAT", tmp);
+
+	if (control_depth == 2 && control_format == 0) {
+		bpp = 4; // bytes per pixel
+	} // TODO: fill in rest of modes...
+
+	printf("Ok so this display is %u x %u with %u bytes per pixel(%u, %u) at %llx\n", width, height, bpp, control_depth, control_format, (unsigned long long)fb_addr);
+
+	*fb = calloc(width * height, bpp);
+	if (*fb) {
+		*size = width * height * bpp;
+		umr_read_vram(asic, 0xFFFF, fb_addr, *size, *fb);
+		return 0;
+	}
+	return -1;
+
+}
diff --git a/src/lib/ip/bif30.c b/src/lib/ip/bif30.c
new file mode 100644
index 0000000..39696dd
--- /dev/null
+++ b/src/lib/ip/bif30.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "bif30_bits.i"
+
+static const struct umr_reg bif30_registers[] = {
+#include "bif30_regs.i"
+};
+
+struct umr_ip_block *umr_create_bif30(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "bif30";
+	ip->no_regs = sizeof(bif30_registers)/sizeof(bif30_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(bif30_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, bif30_registers, sizeof(bif30_registers));
+	return ip;
+}
diff --git a/src/lib/ip/bif30_bits.i b/src/lib/ip/bif30_bits.i
new file mode 100644
index 0000000..28923a4
--- /dev/null
+++ b/src/lib/ip/bif30_bits.i
@@ -0,0 +1,3044 @@
+static struct umr_bitfield ixPCIEP_RESERVED[] = {
+	 { "PCIEP_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SCRATCH[] = {
+	 { "PIF_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_HW_DEBUG[] = {
+	 { "PB0_PIF_HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "PB0_PIF_HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "PB0_PIF_HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "PB0_PIF_HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "PB0_PIF_HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "PB0_PIF_HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "PB0_PIF_HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "PB0_PIF_HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "PB0_PIF_HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "PB0_PIF_HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "PB0_PIF_HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "PB0_PIF_HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "PB0_PIF_HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "PB0_PIF_HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "PB0_PIF_HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "PB0_PIF_HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_INDEX_HI[] = {
+	 { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_NUM_NAK[] = {
+	 { "RX_NUM_NAK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_NUM_NAK_GENERATED[] = {
+	 { "RX_NUM_NAK_GENERATED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_CNTL[] = {
+	 { "DA_FIFO_RESET_0", 1, 1, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_1", 5, 5, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_2", 9, 9, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_3", 13, 13, &umr_bitfield_default },
+	 { "DIVINIT_MODE", 8, 8, &umr_bitfield_default },
+	 { "EI_CYCLE_OFF_TIME", 20, 22, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_MODE", 4, 4, &umr_bitfield_default },
+	 { "EXIT_L0S_INIT_DIS", 23, 23, &umr_bitfield_default },
+	 { "EXTEND_WAIT_FOR_RAMPUP", 28, 28, &umr_bitfield_default },
+	 { "IGNORE_TxDataValid_EP_DIS", 29, 29, &umr_bitfield_default },
+	 { "LS2_EXIT_TIME", 17, 19, &umr_bitfield_default },
+	 { "PHYCMD_CR_EN_MODE", 3, 3, &umr_bitfield_default },
+	 { "PHY_CR_EN_MODE", 2, 2, &umr_bitfield_default },
+	 { "PLL_BINDING_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "RXDETECT_FIFO_RESET_MODE", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_TX_PWR_MODE", 7, 7, &umr_bitfield_default },
+	 { "RXEN_GATER", 24, 27, &umr_bitfield_default },
+	 { "SC_CALIB_DONE_CNTL", 11, 11, &umr_bitfield_default },
+	 { "SERIAL_CFG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TXGND_TIME", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PAIRING[] = {
+	 { "MULTI_PIF", 25, 25, &umr_bitfield_default },
+	 { "X16_LANE_15_0", 20, 20, &umr_bitfield_default },
+	 { "X2_LANE_1_0", 0, 0, &umr_bitfield_default },
+	 { "X2_LANE_11_10", 5, 5, &umr_bitfield_default },
+	 { "X2_LANE_13_12", 6, 6, &umr_bitfield_default },
+	 { "X2_LANE_15_14", 7, 7, &umr_bitfield_default },
+	 { "X2_LANE_3_2", 1, 1, &umr_bitfield_default },
+	 { "X2_LANE_5_4", 2, 2, &umr_bitfield_default },
+	 { "X2_LANE_7_6", 3, 3, &umr_bitfield_default },
+	 { "X2_LANE_9_8", 4, 4, &umr_bitfield_default },
+	 { "X4_LANE_11_8", 10, 10, &umr_bitfield_default },
+	 { "X4_LANE_15_12", 11, 11, &umr_bitfield_default },
+	 { "X4_LANE_3_0", 8, 8, &umr_bitfield_default },
+	 { "X4_LANE_7_4", 9, 9, &umr_bitfield_default },
+	 { "X8_LANE_15_8", 17, 17, &umr_bitfield_default },
+	 { "X8_LANE_7_0", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PWRDOWN_0[] = {
+	 { "FORCE_RXEN_IN_L0s_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_0", 10, 12, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_0", 7, 9, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_0", 29, 31, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_0", 24, 26, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_0", 4, 6, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_0", 16, 16, &umr_bitfield_default },
+	 { "TX_POWER_STATE_IN_TXS2_0", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PWRDOWN_1[] = {
+	 { "FORCE_RXEN_IN_L0s_1", 3, 3, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_1", 10, 12, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_1", 7, 9, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_1", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_1", 29, 31, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_1", 24, 26, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_1", 4, 6, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_1", 16, 16, &umr_bitfield_default },
+	 { "TX_POWER_STATE_IN_TXS2_1", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_CNTL2[] = {
+	 { "RXDETECT_OVERRIDE_EN", 7, 7, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_10", 18, 18, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_11", 19, 19, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_12", 20, 20, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_13", 21, 21, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_14", 22, 22, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_15", 23, 23, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_1", 9, 9, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_2", 10, 10, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_3", 11, 11, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_4", 12, 12, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_5", 13, 13, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_6", 14, 14, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_7", 15, 15, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_8", 16, 16, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_9", 17, 17, &umr_bitfield_default },
+	 { "RXDETECT_SAMPL_TIME", 1, 2, &umr_bitfield_default },
+	 { "RXPHYSTATUS_DELAY", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_TXPHYSTATUS[] = {
+	 { "TXPHYSTATUS_0", 0, 0, &umr_bitfield_default },
+	 { "TXPHYSTATUS_10", 10, 10, &umr_bitfield_default },
+	 { "TXPHYSTATUS_11", 11, 11, &umr_bitfield_default },
+	 { "TXPHYSTATUS_12", 12, 12, &umr_bitfield_default },
+	 { "TXPHYSTATUS_13", 13, 13, &umr_bitfield_default },
+	 { "TXPHYSTATUS_14", 14, 14, &umr_bitfield_default },
+	 { "TXPHYSTATUS_15", 15, 15, &umr_bitfield_default },
+	 { "TXPHYSTATUS_1", 1, 1, &umr_bitfield_default },
+	 { "TXPHYSTATUS_2", 2, 2, &umr_bitfield_default },
+	 { "TXPHYSTATUS_3", 3, 3, &umr_bitfield_default },
+	 { "TXPHYSTATUS_4", 4, 4, &umr_bitfield_default },
+	 { "TXPHYSTATUS_5", 5, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_6", 6, 6, &umr_bitfield_default },
+	 { "TXPHYSTATUS_7", 7, 7, &umr_bitfield_default },
+	 { "TXPHYSTATUS_8", 8, 8, &umr_bitfield_default },
+	 { "TXPHYSTATUS_9", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SC_CTL[] = {
+	 { "SC_CALIBRATION", 0, 0, &umr_bitfield_default },
+	 { "SC_ENTER_L1_FROM_L0", 5, 5, &umr_bitfield_default },
+	 { "SC_ENTER_L1_FROM_L0S", 4, 4, &umr_bitfield_default },
+	 { "SC_EXIT_L1_TO_L0", 3, 3, &umr_bitfield_default },
+	 { "SC_EXIT_L1_TO_L0S", 2, 2, &umr_bitfield_default },
+	 { "SC_LANE_0_RESUME", 16, 16, &umr_bitfield_default },
+	 { "SC_LANE_10_RESUME", 26, 26, &umr_bitfield_default },
+	 { "SC_LANE_11_RESUME", 27, 27, &umr_bitfield_default },
+	 { "SC_LANE_12_RESUME", 28, 28, &umr_bitfield_default },
+	 { "SC_LANE_13_RESUME", 29, 29, &umr_bitfield_default },
+	 { "SC_LANE_14_RESUME", 30, 30, &umr_bitfield_default },
+	 { "SC_LANE_15_RESUME", 31, 31, &umr_bitfield_default },
+	 { "SC_LANE_1_RESUME", 17, 17, &umr_bitfield_default },
+	 { "SC_LANE_2_RESUME", 18, 18, &umr_bitfield_default },
+	 { "SC_LANE_3_RESUME", 19, 19, &umr_bitfield_default },
+	 { "SC_LANE_4_RESUME", 20, 20, &umr_bitfield_default },
+	 { "SC_LANE_5_RESUME", 21, 21, &umr_bitfield_default },
+	 { "SC_LANE_6_RESUME", 22, 22, &umr_bitfield_default },
+	 { "SC_LANE_7_RESUME", 23, 23, &umr_bitfield_default },
+	 { "SC_LANE_8_RESUME", 24, 24, &umr_bitfield_default },
+	 { "SC_LANE_9_RESUME", 25, 25, &umr_bitfield_default },
+	 { "SC_PHASE_1", 8, 8, &umr_bitfield_default },
+	 { "SC_PHASE_2", 9, 9, &umr_bitfield_default },
+	 { "SC_PHASE_3", 10, 10, &umr_bitfield_default },
+	 { "SC_PHASE_4", 11, 11, &umr_bitfield_default },
+	 { "SC_PHASE_5", 12, 12, &umr_bitfield_default },
+	 { "SC_PHASE_6", 13, 13, &umr_bitfield_default },
+	 { "SC_PHASE_7", 14, 14, &umr_bitfield_default },
+	 { "SC_PHASE_8", 15, 15, &umr_bitfield_default },
+	 { "SC_RXDETECT", 1, 1, &umr_bitfield_default },
+	 { "SC_SPEED_CHANGE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PWRDOWN_2[] = {
+	 { "FORCE_RXEN_IN_L0s_2", 3, 3, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_2", 10, 12, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_2", 7, 9, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_2", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_2", 29, 31, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_2", 24, 26, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_2", 4, 6, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_2", 16, 16, &umr_bitfield_default },
+	 { "TX_POWER_STATE_IN_TXS2_2", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PWRDOWN_3[] = {
+	 { "FORCE_RXEN_IN_L0s_3", 3, 3, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_3", 10, 12, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_3", 7, 9, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_3", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_3", 29, 31, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_3", 24, 26, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_3", 4, 6, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_3", 16, 16, &umr_bitfield_default },
+	 { "TX_POWER_STATE_IN_TXS2_3", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_INT_CNTL[] = {
+	 { "CORR_ERR_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "FATAL_ERR_INT_EN", 2, 2, &umr_bitfield_default },
+	 { "LINK_BW_INT_EN", 7, 7, &umr_bitfield_default },
+	 { "MISC_ERR_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "POWER_STATE_CHG_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "QUIESCE_RCVD_INT_EN", 8, 8, &umr_bitfield_default },
+	 { "USR_DETECTED_INT_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_INT_STATUS[] = {
+	 { "CORR_ERR_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "FATAL_ERR_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "LINK_BW_INT_STATUS", 7, 7, &umr_bitfield_default },
+	 { "MISC_ERR_INT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "POWER_STATE_CHG_INT_STATUS", 6, 6, &umr_bitfield_default },
+	 { "QUIESCE_RCVD_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "USR_DETECTED_INT_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CNTL2[] = {
+	 { "MST_MEM_LS_EN", 18, 18, &umr_bitfield_default },
+	 { "MST_MEM_SD_EN", 22, 22, &umr_bitfield_default },
+	 { "REPLAY_MEM_LS_EN", 19, 19, &umr_bitfield_default },
+	 { "REPLAY_MEM_SD_EN", 23, 23, &umr_bitfield_default },
+	 { "RX_NP_MEM_WRITE_ENCODING", 24, 28, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_LS_EN", 17, 17, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_SD_EN", 21, 21, &umr_bitfield_default },
+	 { "SLV_MEM_LS_EN", 16, 16, &umr_bitfield_default },
+	 { "SLV_MEM_SD_EN", 20, 20, &umr_bitfield_default },
+	 { "TX_ARB_MST_LIMIT", 6, 10, &umr_bitfield_default },
+	 { "TX_ARB_ROUND_ROBIN_EN", 0, 0, &umr_bitfield_default },
+	 { "TX_ARB_SLV_LIMIT", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL2[] = {
+	 { "RX_IGNORE_EP_ATSTRANSREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_INVALIDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_INVCPL_UR", 5, 5, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_PAGEREQMSG_UR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMRD_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMWR_UR", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_0[] = {
+	 { "RXEN_OVERRIDE_EN_0", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_0", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_0", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_0", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_0", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_0", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_0", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_0", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_0", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_0", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_1[] = {
+	 { "RXEN_OVERRIDE_EN_1", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_1", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_1", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_1", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_1", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_1", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_1", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_1", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_1", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_1", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_2[] = {
+	 { "RXEN_OVERRIDE_EN_2", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_2", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_2", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_2", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_2", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_2", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_2", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_2", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_2", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_2", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_3[] = {
+	 { "RXEN_OVERRIDE_EN_3", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_3", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_3", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_3", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_3", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_3", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_3", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_3", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_3", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_3", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_4[] = {
+	 { "RXEN_OVERRIDE_EN_4", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_4", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_4", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_4", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_4", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_4", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_4", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_4", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_4", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_4", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_5[] = {
+	 { "RXEN_OVERRIDE_EN_5", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_5", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_5", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_5", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_5", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_5", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_5", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_5", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_5", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_5", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_6[] = {
+	 { "RXEN_OVERRIDE_EN_6", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_6", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_6", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_6", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_6", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_6", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_6", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_6", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_6", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_6", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_7[] = {
+	 { "RXEN_OVERRIDE_EN_7", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_7", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_7", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_7", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_7", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_7", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_7", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_7", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_7", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_7", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_0[] = {
+	 { "SEQ_CALIBRATION_0", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_0", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_0", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_0", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_0", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_0", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_0", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_0", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_1[] = {
+	 { "SEQ_CALIBRATION_1", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_1", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_1", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_1", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_1", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_1", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_1", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_1", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_2[] = {
+	 { "SEQ_CALIBRATION_2", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_2", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_2", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_2", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_2", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_2", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_2", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_3[] = {
+	 { "SEQ_CALIBRATION_3", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_3", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_3", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_3", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_3", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_3", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_3", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_3", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_4[] = {
+	 { "SEQ_CALIBRATION_4", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_4", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_4", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_4", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_4", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_4", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_4", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_4", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_5[] = {
+	 { "SEQ_CALIBRATION_5", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_5", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_5", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_5", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_5", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_5", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_5", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_5", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_6[] = {
+	 { "SEQ_CALIBRATION_6", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_6", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_6", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_6", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_6", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_6", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_6", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_6", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_7[] = {
+	 { "SEQ_CALIBRATION_7", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_7", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_7", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_7", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_7", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_7", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_7", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_7", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_8[] = {
+	 { "RXEN_OVERRIDE_EN_8", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_8", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_8", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_8", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_8", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_8", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_8", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_8", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_8", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_8", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_9[] = {
+	 { "RXEN_OVERRIDE_EN_9", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_9", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_9", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_9", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_9", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_9", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_9", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_9", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_9", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_9", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_10[] = {
+	 { "RXEN_OVERRIDE_EN_10", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_10", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_10", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_10", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_10", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_10", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_10", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_10", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_10", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_10", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_11[] = {
+	 { "RXEN_OVERRIDE_EN_11", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_11", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_11", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_11", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_11", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_11", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_11", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_11", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_11", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_11", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_12[] = {
+	 { "RXEN_OVERRIDE_EN_12", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_12", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_12", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_12", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_12", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_12", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_12", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_12", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_12", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_12", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_13[] = {
+	 { "RXEN_OVERRIDE_EN_13", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_13", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_13", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_13", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_13", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_13", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_13", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_13", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_13", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_13", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_14[] = {
+	 { "RXEN_OVERRIDE_EN_14", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_14", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_14", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_14", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_14", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_14", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_14", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_14", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_14", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_14", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_15[] = {
+	 { "RXEN_OVERRIDE_EN_15", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_15", 9, 9, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_15", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_15", 5, 7, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_15", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_15", 15, 17, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_EN_15", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_15", 1, 3, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_15", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_15", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_8[] = {
+	 { "SEQ_CALIBRATION_8", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_8", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_8", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_8", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_8", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_8", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_8", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_8", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_9[] = {
+	 { "SEQ_CALIBRATION_9", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_9", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_9", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_9", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_9", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_9", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_9", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_9", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_10[] = {
+	 { "SEQ_CALIBRATION_10", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_10", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_10", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_10", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_10", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_10", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_10", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_10", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_11[] = {
+	 { "SEQ_CALIBRATION_11", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_11", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_11", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_11", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_11", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_11", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_11", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_11", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_12[] = {
+	 { "SEQ_CALIBRATION_12", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_12", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_12", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_12", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_12", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_12", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_12", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_12", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_13[] = {
+	 { "SEQ_CALIBRATION_13", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_13", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_13", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_13", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_13", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_13", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_13", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_13", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_14[] = {
+	 { "SEQ_CALIBRATION_14", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_14", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_14", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_14", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_14", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_14", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_14", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_14", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_15[] = {
+	 { "SEQ_CALIBRATION_15", 0, 0, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_15", 5, 5, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_15", 4, 4, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_15", 3, 3, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_15", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PHASE_15", 8, 10, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_15", 1, 1, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_15", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_CNTL[] = {
+	 { "P_ALWAYS_USE_FAST_TXCLK", 13, 13, &umr_bitfield_default },
+	 { "P_BLK_LOCK_MODE", 12, 12, &umr_bitfield_default },
+	 { "P_ELASTDESKEW_HW_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "P_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "P_IGNORE_CRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "P_IGNORE_EDB_ERR", 6, 6, &umr_bitfield_default },
+	 { "P_IGNORE_IDL_ERR", 7, 7, &umr_bitfield_default },
+	 { "P_IGNORE_LEN_ERR", 5, 5, &umr_bitfield_default },
+	 { "P_IGNORE_TOK_ERR", 8, 8, &umr_bitfield_default },
+	 { "P_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "P_SYMALIGN_HW_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "P_SYMALIGN_MODE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_BUF_STATUS[] = {
+	 { "P_OVERFLOW_ERR", 0, 15, &umr_bitfield_default },
+	 { "P_UNDERFLOW_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_DECODER_STATUS[] = {
+	 { "P_DECODE_ERR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_MISC_STATUS[] = {
+	 { "P_DESKEW_ERR", 0, 7, &umr_bitfield_default },
+	 { "P_SYMUNLOCK_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_PORT_LANE_STATUS[] = {
+	 { "PHY_LINK_WIDTH", 1, 6, &umr_bitfield_default },
+	 { "PORT_LANE_REVERSAL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_P[] = {
+	 { "PD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "PH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_NP[] = {
+	 { "NPD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "NPH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_CPL[] = {
+	 { "CPLD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "CPLH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_ERR_CNTL[] = {
+	 { "AER_HDR_LOG_F0_TIMER_EXPIRED", 11, 11, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F1_TIMER_EXPIRED", 12, 12, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F2_TIMER_EXPIRED", 13, 13, &umr_bitfield_default },
+	 { "AER_HDR_LOG_TIMEOUT", 8, 10, &umr_bitfield_default },
+	 { "CI_NP_SLV_BUF_RD_HALT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "CI_P_SLV_BUF_RD_HALT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CI_SLV_BUF_HALT_RESET", 16, 16, &umr_bitfield_default },
+	 { "ERR_REPORTING_DIS", 0, 0, &umr_bitfield_default },
+	 { "RX_GENERATE_ECRC_ERR", 7, 7, &umr_bitfield_default },
+	 { "RX_GENERATE_LCRC_ERR", 5, 5, &umr_bitfield_default },
+	 { "STRAP_FIRST_RCVD_ERR_LOG", 1, 1, &umr_bitfield_default },
+	 { "TX_GENERATE_ECRC_ERR", 6, 6, &umr_bitfield_default },
+	 { "TX_GENERATE_LCRC_ERR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL[] = {
+	 { "RX_FC_INIT_FROM_REG", 15, 15, &umr_bitfield_default },
+	 { "RX_GEN_ONE_NAK", 14, 14, &umr_bitfield_default },
+	 { "RX_IGNORE_AT_ERR", 12, 12, &umr_bitfield_default },
+	 { "RX_IGNORE_BE_ERR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_UR", 10, 10, &umr_bitfield_default },
+	 { "RX_IGNORE_CPL_ERR", 5, 5, &umr_bitfield_default },
+	 { "RX_IGNORE_CPLPREFIX_ERR", 23, 23, &umr_bitfield_default },
+	 { "RX_IGNORE_CRC_ERR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_IGNORE_INVALIDPASID_ERR", 24, 24, &umr_bitfield_default },
+	 { "RX_IGNORE_IO_ERR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_IO_UR", 11, 11, &umr_bitfield_default },
+	 { "RX_IGNORE_LEN_MISMATCH_ERR", 7, 7, &umr_bitfield_default },
+	 { "RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default },
+	 { "RX_IGNORE_MAXPREFIX_ERR", 22, 22, &umr_bitfield_default },
+	 { "RX_IGNORE_MSG_ERR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_NOT_PASID_UR", 25, 25, &umr_bitfield_default },
+	 { "RX_IGNORE_SHORTPREFIX_ERR", 21, 21, &umr_bitfield_default },
+	 { "RX_IGNORE_TC_ERR", 9, 9, &umr_bitfield_default },
+	 { "RX_NAK_IF_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RX_PCIE_CPL_TIMEOUT_DIS", 20, 20, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT", 16, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_MODE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_EXPECTED_SEQNUM[] = {
+	 { "RX_EXPECTED_SEQNUM", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_VENDOR_SPECIFIC[] = {
+	 { "RX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+	 { "RX_VENDOR_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL3[] = {
+	 { "RX_IGNORE_RC_INVCPLPASID_UR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_PRGRESPMSG_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_TRANSMRDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_TRANSMWRPASID_UR", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT_CNTL[] = {
+	 { "GLOBAL_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GLOBAL_COUNT_RESET", 2, 2, &umr_bitfield_default },
+	 { "GLOBAL_SHADOW_WR", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_TXCLK[] = {
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_TXCLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_TXCLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_MST_R_CLK[] = {
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_MST_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_MST_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_MST_C_CLK[] = {
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_MST_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_MST_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_R_CLK[] = {
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_S_C_CLK[] = {
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_S_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_S_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_NS_C_CLK[] = {
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[] = {
+	 { "PERF0_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[] = {
+	 { "PERF1_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_TXCLK2[] = {
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_TXCLK2[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_TXCLK2[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL[] = {
+	 { "LC_16X_CLEAR_TX_PIPE", 4, 7, &umr_bitfield_default },
+	 { "LC_ASPM_TO_L1_DIS", 24, 24, &umr_bitfield_default },
+	 { "LC_DELAY_COUNT", 25, 26, &umr_bitfield_default },
+	 { "LC_DELAY_L0S_EXIT", 27, 27, &umr_bitfield_default },
+	 { "LC_DELAY_L1_EXIT", 28, 28, &umr_bitfield_default },
+	 { "LC_DONT_ENTER_L23_IN_D0", 1, 1, &umr_bitfield_default },
+	 { "LC_ESCAPE_L1L23_EN", 30, 30, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_EL_IDLE", 29, 29, &umr_bitfield_default },
+	 { "LC_FACTOR_IN_EXT_SYNC", 20, 20, &umr_bitfield_default },
+	 { "LC_GATE_RCVR_IDLE", 31, 31, &umr_bitfield_default },
+	 { "LC_INC_N_FTS_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_L0S_INACTIVITY", 8, 11, &umr_bitfield_default },
+	 { "LC_L1_IMMEDIATE_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_L1_INACTIVITY", 12, 15, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_IDLE_IN_L1L23", 18, 19, &umr_bitfield_default },
+	 { "LC_PMI_TO_L1_DIS", 16, 16, &umr_bitfield_default },
+	 { "LC_RESET_L_IDLE_COUNT_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_RESET_LINK", 3, 3, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_PM_ACK_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_WAKE_FROM_L23", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_TRAINING_CNTL[] = {
+	 { "LC_ALLOW_TX_L1_CONTROL", 28, 28, &umr_bitfield_default },
+	 { "LC_ASPM_L1_NAK_TIMER_SEL", 22, 23, &umr_bitfield_default },
+	 { "LC_AUTONOMOUS_CHANGE_OFF", 17, 17, &umr_bitfield_default },
+	 { "LC_COMPLIANCE_RECEIVE", 4, 4, &umr_bitfield_default },
+	 { "LC_DISABLE_TRAINING_BIT_ARCH", 13, 13, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_R_SPEED", 24, 24, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_TEST", 25, 25, &umr_bitfield_default },
+	 { "LC_DONT_GO_TO_L0S_IF_L1_ARMED", 11, 11, &umr_bitfield_default },
+	 { "LC_EXTEND_EQ_REQ_TIME", 30, 31, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_SKP", 16, 16, &umr_bitfield_default },
+	 { "LC_HW_LINK_DIS_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_INIT_SPD_CHG_WITH_CSR_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_L0S_L1_TRAINING_CNTL_EN", 6, 6, &umr_bitfield_default },
+	 { "LC_L1_LONG_WAKE_FIX_EN", 7, 7, &umr_bitfield_default },
+	 { "LC_LINK_DIS_BY_HW", 20, 20, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_MORE_NON_MATCHING_TS1", 5, 5, &umr_bitfield_default },
+	 { "LC_POWER_STATE", 8, 10, &umr_bitfield_default },
+	 { "LC_RESET_ASPM_L1_NAK_TIMER", 26, 26, &umr_bitfield_default },
+	 { "LC_SHORT_RCFG_TIMEOUT", 27, 27, &umr_bitfield_default },
+	 { "LC_STATIC_TX_PIPE_COUNT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_TRAINING_CNTL", 0, 3, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAP_OFF", 18, 18, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_FOM_VALID_AFTER_TRACK", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_LINK_WIDTH_CNTL[] = {
+	 { "LC_DEASSERT_TX_PDNB", 16, 16, &umr_bitfield_default },
+	 { "LC_DUAL_END_RECONFIG_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_DYN_LANES_PWR_STATE", 21, 22, &umr_bitfield_default },
+	 { "LC_DYNLINK_MST_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_EQ_REVERSAL_LOGIC_EN", 23, 23, &umr_bitfield_default },
+	 { "LC_L1_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_LINK_WIDTH", 0, 2, &umr_bitfield_default },
+	 { "LC_LINK_WIDTH_RD", 4, 6, &umr_bitfield_default },
+	 { "LC_RECONFIG_ARC_MISSING_ESCAPE", 7, 7, &umr_bitfield_default },
+	 { "LC_RECONFIG_NOW", 8, 8, &umr_bitfield_default },
+	 { "LC_RENEGOTIATE_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_RENEGOTIATION_SUPPORT", 9, 9, &umr_bitfield_default },
+	 { "LC_SHORT_RECONFIG_EN", 11, 11, &umr_bitfield_default },
+	 { "LC_UPCFG_TIMER_SEL", 15, 15, &umr_bitfield_default },
+	 { "LC_UPCFG_WAIT_FOR_RCVR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_DIS", 13, 13, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_SUPPORT", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_N_FTS_CNTL[] = {
+	 { "LC_N_FTS", 24, 31, &umr_bitfield_default },
+	 { "LC_XMIT_FTS_BEFORE_RECOVERY", 9, 9, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_LIMIT", 16, 23, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS", 0, 7, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_OVERRIDE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_SPEED_CNTL[] = {
+	 { "LC_1_OR_MORE_TS2_SPEED_ARC_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_AUTO_RECOVERY_DIS", 22, 22, &umr_bitfield_default },
+	 { "LC_CHECK_DATA_RATE", 26, 26, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_SPD_CHANGE_CNT", 16, 16, &umr_bitfield_default },
+	 { "LC_CURRENT_DATA_RATE", 13, 14, &umr_bitfield_default },
+	 { "LC_DATA_RATE_ADVERTISED", 24, 25, &umr_bitfield_default },
+	 { "LC_DELAY_COEFF_UPDATE_DIS", 31, 31, &umr_bitfield_default },
+	 { "LC_DONT_CHECK_EQTS_IN_RCFG", 30, 30, &umr_bitfield_default },
+	 { "LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS", 15, 15, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_HW_SPEED_CHANGE", 8, 8, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_SW_SPEED_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_FORCE_EN_HW_SPEED_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_FORCE_EN_SW_SPEED_CHANGE", 5, 5, &umr_bitfield_default },
+	 { "LC_GEN2_EN_STRAP", 0, 0, &umr_bitfield_default },
+	 { "LC_GEN3_EN_STRAP", 1, 1, &umr_bitfield_default },
+	 { "LC_INITIATE_LINK_SPEED_CHANGE", 9, 9, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L0s_EN", 28, 28, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L1_EN", 29, 29, &umr_bitfield_default },
+	 { "LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN", 27, 27, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN2", 18, 18, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN3", 20, 20, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN2", 19, 19, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN3", 21, 21, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPT_FAILED", 12, 12, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPTS_ALLOWED", 10, 11, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_STATUS", 23, 23, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE0[] = {
+	 { "LC_CURRENT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE1", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE2", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE1[] = {
+	 { "LC_PREV_STATE4", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE5", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE6", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE7", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE2[] = {
+	 { "LC_PREV_STATE10", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE11", 24, 29, &umr_bitfield_default },
+	 { "LC_PREV_STATE8", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE9", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE3[] = {
+	 { "LC_PREV_STATE12", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE13", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE14", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE15", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE4[] = {
+	 { "LC_PREV_STATE16", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE17", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE18", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE19", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE5[] = {
+	 { "LC_PREV_STATE20", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE21", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE22", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE23", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F0[] = {
+	 { "STRAP_F0_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F0_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F0_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F0_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F0_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F0_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F0_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F0_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F0_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F0_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F0_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F0_VC_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL2[] = {
+	 { "LC_ALLOW_PDWN_IN_L1", 17, 17, &umr_bitfield_default },
+	 { "LC_ALLOW_PDWN_IN_L23", 18, 18, &umr_bitfield_default },
+	 { "LC_ASSERT_INACTIVE_DURING_HOLD", 22, 22, &umr_bitfield_default },
+	 { "LC_BLOCK_EL_IDLE_IN_L0", 20, 20, &umr_bitfield_default },
+	 { "LC_DEASSERT_RX_EN_IN_L0S", 19, 19, &umr_bitfield_default },
+	 { "LC_DISABLE_INFERRED_ELEC_IDLE_DET", 16, 16, &umr_bitfield_default },
+	 { "LC_DISABLE_LOST_SYM_LOCK_ARCS", 26, 26, &umr_bitfield_default },
+	 { "LC_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI", 31, 31, &umr_bitfield_default },
+	 { "LC_ILLEGAL_STATE", 11, 11, &umr_bitfield_default },
+	 { "LC_ILLEGAL_STATE_RESTART_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DIS", 27, 27, &umr_bitfield_default },
+	 { "LC_LINK_UP_REVERSAL_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_BW_REDUCTION", 7, 7, &umr_bitfield_default },
+	 { "LC_MORE_TS2_EN", 8, 8, &umr_bitfield_default },
+	 { "LC_PMI_L1_WAIT_FOR_SLV_IDLE", 28, 28, &umr_bitfield_default },
+	 { "LC_PWR_DOWN_NEG_OFF_LANES", 25, 25, &umr_bitfield_default },
+	 { "LC_RCV_L0_TO_RCV_L0S_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_STATE_TIMED_OUT", 6, 6, &umr_bitfield_default },
+	 { "LC_TEST_TIMER_SEL", 29, 30, &umr_bitfield_default },
+	 { "LC_TIMED_OUT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_LANES_IN_LW_NEG", 23, 24, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_OTHER_LANES_MODE", 13, 13, &umr_bitfield_default },
+	 { "LC_X12_NEGOTIATION_DIS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_BW_CHANGE_CNTL[] = {
+	 { "LC_BW_CHANGE_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "LC_FAILED_SPEED_NEG", 5, 5, &umr_bitfield_default },
+	 { "LC_HW_INIT_SPEED_CHANGE", 1, 1, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DETECT_MODE", 10, 10, &umr_bitfield_default },
+	 { "LC_LONG_LW_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_FAILED", 9, 9, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_OTHER", 8, 8, &umr_bitfield_default },
+	 { "LC_OTHER_INIT_SPEED_CHANGE", 3, 3, &umr_bitfield_default },
+	 { "LC_RELIABILITY_SPEED_CHANGE", 4, 4, &umr_bitfield_default },
+	 { "LC_SHORT_LW_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_SW_INIT_SPEED_CHANGE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CDR_CNTL[] = {
+	 { "LC_CDR_SET_TYPE", 24, 25, &umr_bitfield_default },
+	 { "LC_CDR_TEST_OFF", 0, 11, &umr_bitfield_default },
+	 { "LC_CDR_TEST_SETS", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_LANE_CNTL[] = {
+	 { "LC_CORRUPTED_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_LANE_DIS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL3[] = {
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL", 19, 20, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED", 8, 8, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED", 6, 7, &umr_bitfield_default },
+	 { "LC_CHIP_BIF_USB_IDLE_EN", 16, 16, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT", 9, 9, &umr_bitfield_default },
+	 { "LC_COMP_TO_DETECT", 4, 4, &umr_bitfield_default },
+	 { "LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_EHP_RX_PHY_CMD", 12, 13, &umr_bitfield_default },
+	 { "LC_EHP_TX_PHY_CMD", 14, 15, &umr_bitfield_default },
+	 { "LC_ENHANCED_HOT_PLUG_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_FAST_L1_ENTRY_EXIT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_GO_TO_RECOVERY", 30, 30, &umr_bitfield_default },
+	 { "LC_HW_VOLTAGE_IF_CONTROL", 24, 25, &umr_bitfield_default },
+	 { "LC_L1_BLOCK_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_N_EIE_SEL", 31, 31, &umr_bitfield_default },
+	 { "LC_RCVD_DEEMPHASIS", 3, 3, &umr_bitfield_default },
+	 { "LC_RCVR_DET_EN_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "LC_RESET_TSX_CNT_IN_RLOCK_EN", 5, 5, &umr_bitfield_default },
+	 { "LC_RXPHYCMD_INACTIVE_EN_MODE", 22, 22, &umr_bitfield_default },
+	 { "LC_SELECT_DEEMPHASIS_CNTL", 1, 2, &umr_bitfield_default },
+	 { "LC_SELECT_DEEMPHASIS", 0, 0, &umr_bitfield_default },
+	 { "LC_VOLTAGE_TIMER_SEL", 26, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL4[] = {
+	 { "LC_8GT_SKIP_ORDER_EN", 25, 25, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ", 4, 4, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ_REQ_PHASE", 16, 16, &umr_bitfield_default },
+	 { "LC_DSC_CHECK_COEFFS_IN_RLOCK", 10, 10, &umr_bitfield_default },
+	 { "LC_EQ_SEARCH_MODE", 8, 9, &umr_bitfield_default },
+	 { "LC_EQ_WAIT_FOR_EVAL_DONE", 24, 24, &umr_bitfield_default },
+	 { "LC_EXTEND_EIEOS", 6, 6, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_IN_EQ_REQ_PHASE", 17, 17, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_VALUE", 18, 21, &umr_bitfield_default },
+	 { "LC_IGNORE_PARITY", 7, 7, &umr_bitfield_default },
+	 { "LC_PCIE_TX_FULL_SWING", 23, 23, &umr_bitfield_default },
+	 { "LC_QUIESCE_RCVD", 14, 14, &umr_bitfield_default },
+	 { "LC_REDO_EQ", 5, 5, &umr_bitfield_default },
+	 { "LC_SET_QUIESCE", 13, 13, &umr_bitfield_default },
+	 { "LC_TX_ENABLE_BEHAVIOUR", 0, 1, &umr_bitfield_default },
+	 { "LC_UNEXPECTED_COEFFS_RCVD", 15, 15, &umr_bitfield_default },
+	 { "LC_USC_DELAY_DLLPS", 22, 22, &umr_bitfield_default },
+	 { "LC_USC_EQ_NOT_REQD", 11, 11, &umr_bitfield_default },
+	 { "LC_USC_GO_TO_EQ", 12, 12, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_MORE_TS_IN_RLOCK", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL5[] = {
+	 { "LC_EQ_FS_0", 0, 5, &umr_bitfield_default },
+	 { "LC_EQ_FS_8", 6, 11, &umr_bitfield_default },
+	 { "LC_EQ_LF_0", 12, 17, &umr_bitfield_default },
+	 { "LC_EQ_LF_8", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_FORCE_COEFF[] = {
+	 { "LC_3X3_COEFF_SEARCH_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_FORCE_COEFF", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR", 13, 18, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_BEST_EQ_SETTINGS[] = {
+	 { "LC_BEST_CURSOR", 10, 15, &umr_bitfield_default },
+	 { "LC_BEST_FOM", 22, 29, &umr_bitfield_default },
+	 { "LC_BEST_POSTCURSOR", 16, 21, &umr_bitfield_default },
+	 { "LC_BEST_PRECURSOR", 4, 9, &umr_bitfield_default },
+	 { "LC_BEST_PRESET", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_FORCE_EQ_REQ_COEFF[] = {
+	 { "LC_FORCE_COEFF_IN_EQ_REQ_PHASE", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR_REQ", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR_REQ", 13, 18, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR_REQ", 1, 6, &umr_bitfield_default },
+	 { "LC_FS_OTHER_END", 19, 24, &umr_bitfield_default },
+	 { "LC_LF_OTHER_END", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_STRAP_LC[] = {
+	 { "STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_BYPASS_RCVR_DET", 11, 11, &umr_bitfield_default },
+	 { "STRAP_COMPLIANCE_DIS", 12, 12, &umr_bitfield_default },
+	 { "STRAP_FORCE_COMPLIANCE", 13, 13, &umr_bitfield_default },
+	 { "STRAP_FTS_yTSx_COUNT", 0, 1, &umr_bitfield_default },
+	 { "STRAP_LANE_NEGOTIATION", 16, 18, &umr_bitfield_default },
+	 { "STRAP_LONG_yTSx_COUNT", 2, 3, &umr_bitfield_default },
+	 { "STRAP_MED_yTSx_COUNT", 4, 5, &umr_bitfield_default },
+	 { "STRAP_REVERSE_LC_LANES", 14, 14, &umr_bitfield_default },
+	 { "STRAP_SHORT_yTSx_COUNT", 6, 7, &umr_bitfield_default },
+	 { "STRAP_SKIP_INTERVAL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_STRAP_MISC[] = {
+	 { "STRAP_E2E_PREFIX_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_EXTENDED_FMT_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "STRAP_OBFF_SUPPORTED", 3, 4, &umr_bitfield_default },
+	 { "STRAP_REVERSE_LANES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_PI[] = {
+	 { "STRAP_QUICKSIM_START", 0, 0, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_MODE", 29, 29, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_PATTERN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_I2C_BD[] = {
+	 { "STRAP_BIF_DBG_I2C_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_I2C_SLV_ADR", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_CLR[] = {
+	 { "PRBS_CHECKER_DEBUG_BUS_SELECT", 16, 19, &umr_bitfield_default },
+	 { "PRBS_CLR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_STATUS1[] = {
+	 { "PRBS_ERRSTAT", 0, 15, &umr_bitfield_default },
+	 { "PRBS_LOCKED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_STATUS2[] = {
+	 { "PRBS_BITCNT_DONE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_FREERUN[] = {
+	 { "PRBS_FREERUN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_MISC[] = {
+	 { "PRBS_8BIT_SEL", 4, 4, &umr_bitfield_default },
+	 { "PRBS_CHK_ERR_MASK", 16, 31, &umr_bitfield_default },
+	 { "PRBS_COMMA_NUM", 5, 6, &umr_bitfield_default },
+	 { "PRBS_DATA_RATE", 14, 15, &umr_bitfield_default },
+	 { "PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "PRBS_LOCK_CNT", 7, 11, &umr_bitfield_default },
+	 { "PRBS_TEST_MODE", 1, 2, &umr_bitfield_default },
+	 { "PRBS_USER_PATTERN_TOGGLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_USER_PATTERN[] = {
+	 { "PRBS_USER_PATTERN", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_LO_BITCNT[] = {
+	 { "PRBS_LO_BITCNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_HI_BITCNT[] = {
+	 { "PRBS_HI_BITCNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_0[] = {
+	 { "PRBS_ERRCNT_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_1[] = {
+	 { "PRBS_ERRCNT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_2[] = {
+	 { "PRBS_ERRCNT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_3[] = {
+	 { "PRBS_ERRCNT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_4[] = {
+	 { "PRBS_ERRCNT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_5[] = {
+	 { "PRBS_ERRCNT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_6[] = {
+	 { "PRBS_ERRCNT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_7[] = {
+	 { "PRBS_ERRCNT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_8[] = {
+	 { "PRBS_ERRCNT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_9[] = {
+	 { "PRBS_ERRCNT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_10[] = {
+	 { "PRBS_ERRCNT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_11[] = {
+	 { "PRBS_ERRCNT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_12[] = {
+	 { "PRBS_ERRCNT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_13[] = {
+	 { "PRBS_ERRCNT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_14[] = {
+	 { "PRBS_ERRCNT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_15[] = {
+	 { "PRBS_ERRCNT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_CAP[] = {
+	 { "PWR_ALLOC_SCALE", 12, 13, &umr_bitfield_default },
+	 { "TRANS_LAT_UNIT", 8, 9, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_0", 16, 23, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_LATENCY_INDICATOR[] = {
+	 { "TRANS_LAT_INDICATOR_BITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_CNTL[] = {
+	 { "SUBSTATE_STATUS", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_0[] = {
+	 { "BIOS_SCRATCH_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_1[] = {
+	 { "BIOS_SCRATCH_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_2[] = {
+	 { "BIOS_SCRATCH_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_3[] = {
+	 { "BIOS_SCRATCH_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_4[] = {
+	 { "BIOS_SCRATCH_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_5[] = {
+	 { "BIOS_SCRATCH_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_6[] = {
+	 { "BIOS_SCRATCH_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_7[] = {
+	 { "BIOS_SCRATCH_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_8[] = {
+	 { "BIOS_SCRATCH_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_9[] = {
+	 { "BIOS_SCRATCH_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_10[] = {
+	 { "BIOS_SCRATCH_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_11[] = {
+	 { "BIOS_SCRATCH_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_12[] = {
+	 { "BIOS_SCRATCH_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_13[] = {
+	 { "BIOS_SCRATCH_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_14[] = {
+	 { "BIOS_SCRATCH_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_15[] = {
+	 { "BIOS_SCRATCH_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG0[] = {
+	 { "BACKUP", 0, 15, &umr_bitfield_default },
+	 { "CFG_IDLEDET_TH", 16, 17, &umr_bitfield_default },
+	 { "DBG_RX2TXBYP_SEL", 20, 22, &umr_bitfield_default },
+	 { "DBG_RXFEBYP_EN", 23, 23, &umr_bitfield_default },
+	 { "DBG_RXPRBS_CLR", 24, 24, &umr_bitfield_default },
+	 { "DBG_RXTOGGLE_EN", 25, 25, &umr_bitfield_default },
+	 { "DBG_TX2RXLBACK_EN", 26, 26, &umr_bitfield_default },
+	 { "TXCFG_CMGOOD_RANGE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG1[] = {
+	 { "PLL_CFG_DISPCLK_DIV", 31, 31, &umr_bitfield_default },
+	 { "RXDBG_CDR_FR_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_CDR_FR_BYP_VAL", 1, 6, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_EN", 7, 7, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_VAL", 8, 13, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_EN", 14, 14, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_VAL", 15, 21, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_VAL", 23, 29, &umr_bitfield_default },
+	 { "TST_LOSPDTST_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG2[] = {
+	 { "RXDBG_D2TH_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_D2TH_BYP_VAL", 1, 7, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_EN", 8, 8, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_VAL", 9, 15, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_EN", 16, 16, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_VAL", 17, 23, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_EN", 24, 24, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_VAL", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG3[] = {
+	 { "BG_CFG_LC_REG_VREF0_SEL", 5, 6, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF1_SEL", 7, 8, &umr_bitfield_default },
+	 { "BG_CFG_RO_REG_VREF_SEL", 9, 10, &umr_bitfield_default },
+	 { "BG_DBG_ANALOG_SEL", 14, 16, &umr_bitfield_default },
+	 { "BG_DBG_IREFBYP_EN", 12, 12, &umr_bitfield_default },
+	 { "BG_DBG_VREFBYP_EN", 11, 11, &umr_bitfield_default },
+	 { "DBG_DLL_CLK_SEL", 18, 20, &umr_bitfield_default },
+	 { "DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE", 31, 31, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_VAL", 23, 26, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_EN", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_VAL", 28, 30, &umr_bitfield_default },
+	 { "PLL_DISPCLK_CMOS_SEL", 21, 21, &umr_bitfield_default },
+	 { "RXDBG_SEL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG4[] = {
+	 { "DBG_RXAPU_EXEC", 22, 25, &umr_bitfield_default },
+	 { "DBG_RXAPU_INST", 0, 15, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_EN", 18, 18, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_VAL", 16, 17, &umr_bitfield_default },
+	 { "DBG_RXDLL_VREG_REF_SEL", 26, 26, &umr_bitfield_default },
+	 { "DBG_RXRDATA_GATING_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "PWRGOOD_OVRD", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG5[] = {
+	 { "DBG_RXAPU_MODE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_ALL_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_IMPCAL_ACTIVE_SCI_UPDT", 4, 4, &umr_bitfield_default },
+	 { "IMPCAL_ACTIVE", 20, 20, &umr_bitfield_default },
+	 { "RXIMP", 16, 19, &umr_bitfield_default },
+	 { "TXNIMP", 8, 11, &umr_bitfield_default },
+	 { "TXPIMP", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG1[] = {
+	 { "DLL_LOCK_0", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_1", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_2", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_3", 15, 15, &umr_bitfield_default },
+	 { "FREQDIV_0", 18, 19, &umr_bitfield_default },
+	 { "FREQDIV_1", 22, 23, &umr_bitfield_default },
+	 { "FREQDIV_2", 26, 27, &umr_bitfield_default },
+	 { "FREQDIV_3", 30, 31, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L0T3", 2, 2, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L0T3", 1, 1, &umr_bitfield_default },
+	 { "IGNR_MODE_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "MODE_0", 16, 17, &umr_bitfield_default },
+	 { "MODE_1", 20, 21, &umr_bitfield_default },
+	 { "MODE_2", 24, 25, &umr_bitfield_default },
+	 { "MODE_3", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG2[] = {
+	 { "DLL_LOCK_4", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_5", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_6", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_7", 15, 15, &umr_bitfield_default },
+	 { "FREQDIV_4", 18, 19, &umr_bitfield_default },
+	 { "FREQDIV_5", 22, 23, &umr_bitfield_default },
+	 { "FREQDIV_6", 26, 27, &umr_bitfield_default },
+	 { "FREQDIV_7", 30, 31, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L4T7", 2, 2, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_MODE_SCI_UPDT_L4T7", 0, 0, &umr_bitfield_default },
+	 { "MODE_4", 16, 17, &umr_bitfield_default },
+	 { "MODE_5", 20, 21, &umr_bitfield_default },
+	 { "MODE_6", 24, 25, &umr_bitfield_default },
+	 { "MODE_7", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG3[] = {
+	 { "DLL_LOCK_10", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_11", 15, 15, &umr_bitfield_default },
+	 { "DLL_LOCK_8", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_9", 13, 13, &umr_bitfield_default },
+	 { "FREQDIV_10", 26, 27, &umr_bitfield_default },
+	 { "FREQDIV_11", 30, 31, &umr_bitfield_default },
+	 { "FREQDIV_8", 18, 19, &umr_bitfield_default },
+	 { "FREQDIV_9", 22, 23, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L8T11", 1, 1, &umr_bitfield_default },
+	 { "IGNR_MODE_SCI_UPDT_L8T11", 0, 0, &umr_bitfield_default },
+	 { "MODE_10", 24, 25, &umr_bitfield_default },
+	 { "MODE_11", 28, 29, &umr_bitfield_default },
+	 { "MODE_8", 16, 17, &umr_bitfield_default },
+	 { "MODE_9", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG4[] = {
+	 { "DLL_LOCK_12", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_13", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_14", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_15", 15, 15, &umr_bitfield_default },
+	 { "FREQDIV_12", 18, 19, &umr_bitfield_default },
+	 { "FREQDIV_13", 22, 23, &umr_bitfield_default },
+	 { "FREQDIV_14", 26, 27, &umr_bitfield_default },
+	 { "FREQDIV_15", 30, 31, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L12T15", 2, 2, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L12T15", 1, 1, &umr_bitfield_default },
+	 { "IGNR_MODE_SCI_UPDT_L12T15", 0, 0, &umr_bitfield_default },
+	 { "MODE_12", 16, 17, &umr_bitfield_default },
+	 { "MODE_13", 20, 21, &umr_bitfield_default },
+	 { "MODE_14", 24, 25, &umr_bitfield_default },
+	 { "MODE_15", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG0[] = {
+	 { "TXPDTERM_VAL_OVRD_VAL", 0, 15, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG1[] = {
+	 { "RXTERM_VAL_OVRD_EN", 15, 15, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_VAL", 3, 3, &umr_bitfield_default },
+	 { "TXPDTERM_VAL_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG2[] = {
+	 { "BG_PWRON_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "BG_PWRON_OVRD_VAL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_HW_DEBUG[] = {
+	 { "PB0_HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "PB0_HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "PB0_HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "PB0_HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "PB0_HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "PB0_HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "PB0_HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "PB0_HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "PB0_HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "PB0_HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "PB0_HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "PB0_HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "PB0_HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "PB0_HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "PB0_HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "PB0_HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "PB0_HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "PB0_HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "PB0_HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "PB0_HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "PB0_HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "PB0_HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "PB0_HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "PB0_HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "PB0_HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "PB0_HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "PB0_HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "PB0_HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "PB0_HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "PB0_HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "PB0_HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "PB0_HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_GLB_REG0[] = {
+	 { "STRAP_DBG_RXDLL_VREG_REF_SEL", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG0[] = {
+	 { "DFT_CLK_PER_STEP", 8, 11, &umr_bitfield_default },
+	 { "DFT_DECR_SWP_EN", 23, 23, &umr_bitfield_default },
+	 { "DFT_INCR_SWP_EN", 22, 22, &umr_bitfield_default },
+	 { "DFT_NUM_STEPS", 0, 4, &umr_bitfield_default },
+	 { "DFT_RECOVERY_TIME", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG1[] = {
+	 { "DFT_BLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DFT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "DFT_BYPASS_VALUE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG2[] = {
+	 { "DFT_LANE_EN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_DEBUG_CTRL_REG0[] = {
+	 { "DFT_PHY_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DFT_PHY_DEBUG_MODE", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO_GLB_CTRL_REG0[] = {
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 9, 9, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 10, 10, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 11, 11, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN", 20, 20, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN", 21, 21, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 12, 12, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 13, 13, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 14, 14, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN", 22, 22, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN", 23, 23, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_LUT_ENTRY_LS2", 8, 8, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 2, 2, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 3, 3, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN", 16, 16, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN", 17, 17, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 4, 4, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 5, 5, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 6, 6, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN", 18, 18, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN", 19, 19, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_LUT_ENTRY_LS2", 7, 7, &umr_bitfield_default },
+	 { "PLL_TST_LOSPDTST_SRC", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_CTRL_REG0[] = {
+	 { "PLL_DBG_RO_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_RO_LF_CNTRL_0", 4, 10, &umr_bitfield_default },
+	 { "PLL_DBG_RO_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_TST_RO_USAMPLE_EN_0", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_OVRD_REG0[] = {
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0", 0, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0", 9, 11, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_VAL_0", 15, 27, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_OVRD_REG1[] = {
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0", 22, 22, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0", 19, 21, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFDIV_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFDIV_OVRD_VAL_0", 0, 4, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_VAL_0", 6, 7, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0", 11, 11, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO0_FREQMODE", 8, 9, &umr_bitfield_default },
+	 { "PLL_RO0_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO0_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO0_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO1_FREQMODE", 8, 9, &umr_bitfield_default },
+	 { "PLL_RO1_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO1_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO1_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO2_FREQMODE", 8, 9, &umr_bitfield_default },
+	 { "PLL_RO2_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO2_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO2_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO3_FREQMODE", 8, 9, &umr_bitfield_default },
+	 { "PLL_RO3_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO3_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO3_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_CTRL_REG0[] = {
+	 { "PLL_DBG_LC_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_LC_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_TST_LC_USAMPLE_EN_0", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_OVRD_REG0[] = {
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0", 4, 6, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_VAL_0", 10, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0", 19, 27, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_VAL_0", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_OVRD_REG1[] = {
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0", 14, 17, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC0_FREQMODE", 8, 9, &umr_bitfield_default },
+	 { "PLL_LC0_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC0_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC0_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC1_FREQMODE", 8, 9, &umr_bitfield_default },
+	 { "PLL_LC1_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC1_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC1_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC2_FREQMODE", 8, 9, &umr_bitfield_default },
+	 { "PLL_LC2_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC2_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC2_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC3_FREQMODE", 8, 9, &umr_bitfield_default },
+	 { "PLL_LC3_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC3_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC3_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_XDMA_LO[] = {
+	 { "BIF_XDMA_APER_EN", 31, 31, &umr_bitfield_default },
+	 { "BIF_XDMA_LOWER_BOUND", 0, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_XDMA_HI[] = {
+	 { "BIF_XDMA_UPPER_BOUND", 0, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_FEATURES_CONTROL_MISC[] = {
+	 { "BIF_MST_CPL_EP_DIS", 3, 3, &umr_bitfield_default },
+	 { "BIF_SLV_REQ_EP_DIS", 2, 2, &umr_bitfield_default },
+	 { "IGNORE_BE_CHECK_GASKET_COMB_DIS", 8, 8, &umr_bitfield_default },
+	 { "MST_BIF_REQ_EP_DIS", 0, 0, &umr_bitfield_default },
+	 { "PLL_SWITCH_IMPCTL_CAL_DONE_DIS", 7, 7, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS", 5, 5, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS", 6, 6, &umr_bitfield_default },
+	 { "SLV_BIF_CPL_EP_DIS", 1, 1, &umr_bitfield_default },
+	 { "UR_PSN_PKT_REPORT_POISON_DIS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBUS_BACO_DUMMY[] = {
+	 { "SMBUS_BACO_DUMMY_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBF_ANA_ISO_CNTL[] = {
+	 { "BF_ANA_ISO_DIS_MASK", 0, 0, &umr_bitfield_default },
+	 { "BF_VDDC_ISO_DIS_MASK", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_PWR_STATUS[] = {
+	 { "SSA_DISP_PWR_STATUS", 1, 1, &umr_bitfield_default },
+	 { "SSA_GFX_PWR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "SSA_MC_PWR_STATUS", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX0_LOWER[] = {
+	 { "SSA_GFX0_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_GFX0_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_GFX0_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX0_UPPER[] = {
+	 { "SSA_GFX0_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX1_LOWER[] = {
+	 { "SSA_GFX1_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_GFX1_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_GFX1_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX1_UPPER[] = {
+	 { "SSA_GFX1_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX2_LOWER[] = {
+	 { "SSA_GFX2_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_GFX2_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_GFX2_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX2_UPPER[] = {
+	 { "SSA_GFX2_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX3_LOWER[] = {
+	 { "SSA_GFX3_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_GFX3_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_GFX3_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX3_UPPER[] = {
+	 { "SSA_GFX3_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_DISP_LOWER[] = {
+	 { "SSA_DISP_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_DISP_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_DISP_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_DISP_UPPER[] = {
+	 { "SSA_DISP_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_MC_LOWER[] = {
+	 { "SSA_MC_FB_STALL_EN", 29, 29, &umr_bitfield_default },
+	 { "SSA_MC_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_MC_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_MC_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_MC_UPPER[] = {
+	 { "SSA_MC_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_DEBUG_LATCH[] = {
+	 { "BIF_BACO_LATCH_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_MSIC[] = {
+	 { "BIF_XTALIN_SEL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_DEBUG[] = {
+	 { "BIF_BACO_SCANDUMP_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBACO_CNTL[] = {
+	 { "BACO_ANA_ISO_DIS", 7, 7, &umr_bitfield_default },
+	 { "BACO_BCLK_OFF", 1, 1, &umr_bitfield_default },
+	 { "BACO_EN", 0, 0, &umr_bitfield_default },
+	 { "BACO_HANG_PROTECTION_EN", 5, 5, &umr_bitfield_default },
+	 { "BACO_ISO_DIS", 2, 2, &umr_bitfield_default },
+	 { "BACO_MODE", 6, 6, &umr_bitfield_default },
+	 { "BACO_POWER_OFF", 3, 3, &umr_bitfield_default },
+	 { "BACO_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "PWRGOOD_BF", 9, 9, &umr_bitfield_default },
+	 { "PWRGOOD_DVO", 12, 12, &umr_bitfield_default },
+	 { "PWRGOOD_GPIO", 10, 10, &umr_bitfield_default },
+	 { "PWRGOOD_MEM", 11, 11, &umr_bitfield_default },
+	 { "RCU_BIF_CONFIG_DONE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEVFUNCNUM_LIST1[] = {
+	 { "DEVFUNC_ID4", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID5", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID6", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEVFUNCNUM_LIST0[] = {
+	 { "DEVFUNC_ID0", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID1", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID2", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmNEW_REFCLKB_TIMER_1[] = {
+	 { "PHY_PLL_PDWN_TIMER", 0, 9, &umr_bitfield_default },
+	 { "PLL0_PDNB_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmNEW_REFCLKB_TIMER[] = {
+	 { "REFCLK_ON", 21, 21, &umr_bitfield_default },
+	 { "REG_STOP_REFCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "STOP_REFCLK_TIMER", 1, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER3_FB_OFFSET_LO[] = {
+	 { "PEER3_FB_EN", 31, 31, &umr_bitfield_default },
+	 { "PEER3_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER3_FB_OFFSET_HI[] = {
+	 { "PEER3_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER2_FB_OFFSET_LO[] = {
+	 { "PEER2_FB_EN", 31, 31, &umr_bitfield_default },
+	 { "PEER2_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER2_FB_OFFSET_HI[] = {
+	 { "PEER2_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER1_FB_OFFSET_LO[] = {
+	 { "PEER1_FB_EN", 31, 31, &umr_bitfield_default },
+	 { "PEER1_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER1_FB_OFFSET_HI[] = {
+	 { "PEER1_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER0_FB_OFFSET_LO[] = {
+	 { "PEER0_FB_EN", 31, 31, &umr_bitfield_default },
+	 { "PEER0_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER0_FB_OFFSET_HI[] = {
+	 { "PEER0_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMPCTL_RESET[] = {
+	 { "IMP_SW_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBUS_CNTL[] = {
+	 { "BIF_ERR_RTR_BKPRESSURE_EN", 8, 8, &umr_bitfield_default },
+	 { "BIOS_ROM_DIS", 1, 1, &umr_bitfield_default },
+	 { "BIOS_ROM_WRT_EN", 0, 0, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 4, 4, &umr_bitfield_default },
+	 { "PMI_INT_DIS", 5, 5, &umr_bitfield_default },
+	 { "PMI_IO_DIS", 2, 2, &umr_bitfield_default },
+	 { "PMI_MEM_DIS", 3, 3, &umr_bitfield_default },
+	 { "RD_STALL_IO_WR", 18, 18, &umr_bitfield_default },
+	 { "SET_AZ_TC", 10, 12, &umr_bitfield_default },
+	 { "SET_MC_TC", 13, 15, &umr_bitfield_default },
+	 { "VGA_MEM_COHERENCY_DIS", 7, 7, &umr_bitfield_default },
+	 { "VGA_REG_COHERENCY_DIS", 6, 6, &umr_bitfield_default },
+	 { "ZERO_BE_RD_EN", 17, 17, &umr_bitfield_default },
+	 { "ZERO_BE_WR_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_CNTL[] = {
+	 { "CFG_VGA_RAM_EN", 0, 0, &umr_bitfield_default },
+	 { "GENMO_MONO_ADDRESS_B", 2, 2, &umr_bitfield_default },
+	 { "GRPH_ADRSEL", 3, 4, &umr_bitfield_default },
+	 { "VGA_DIS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_MEMSIZE[] = {
+	 { "CONFIG_MEMSIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_F0_BASE[] = {
+	 { "F0_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_APER_SIZE[] = {
+	 { "APER_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_REG_APER_SIZE[] = {
+	 { "REG_APER_SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SCRATCH0[] = {
+	 { "BIF_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SCRATCH1[] = {
+	 { "BIF_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RESET_EN[] = {
+	 { "BIF_COR_RESET_EN", 22, 22, &umr_bitfield_default },
+	 { "CFG_RESET_EN", 6, 6, &umr_bitfield_default },
+	 { "CFG_RESET_PULSE_WIDTH", 12, 17, &umr_bitfield_default },
+	 { "COR_RESET_EN", 3, 3, &umr_bitfield_default },
+	 { "DRV_RESET_DELAY_SEL", 18, 19, &umr_bitfield_default },
+	 { "DRV_RESET_EN", 7, 7, &umr_bitfield_default },
+	 { "FUNC0_FLR_EN", 23, 23, &umr_bitfield_default },
+	 { "FUNC0_RESET_DELAY_SEL", 26, 27, &umr_bitfield_default },
+	 { "FUNC1_FLR_EN", 24, 24, &umr_bitfield_default },
+	 { "FUNC1_RESET_DELAY_SEL", 28, 29, &umr_bitfield_default },
+	 { "FUNC2_FLR_EN", 25, 25, &umr_bitfield_default },
+	 { "FUNC2_RESET_DELAY_SEL", 30, 31, &umr_bitfield_default },
+	 { "HOT_RESET_EN", 9, 9, &umr_bitfield_default },
+	 { "LINK_DISABLE_RESET_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_DOWN_RESET_EN", 11, 11, &umr_bitfield_default },
+	 { "PHY_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "PIF_RSTB_EN", 20, 20, &umr_bitfield_default },
+	 { "PIF_STRAP_ALLVALID_EN", 21, 21, &umr_bitfield_default },
+	 { "REG_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "RESET_CFGREG_ONLY_EN", 8, 8, &umr_bitfield_default },
+	 { "SOFT_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "STY_RESET_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_CFGREGS_CNTL[] = {
+	 { "MM_CFG_FUNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "MM_WR_TO_CFG_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_CREDIT_CNTL[] = {
+	 { "BIF_AZ_RDRET_CREDIT", 16, 21, &umr_bitfield_default },
+	 { "BIF_MC_RDRET_CREDIT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_REQ_CREDIT_CNTL[] = {
+	 { "BIF_AZ_REQ_CREDIT", 20, 20, &umr_bitfield_default },
+	 { "BIF_HDP_REQ_CREDIT", 10, 14, &umr_bitfield_default },
+	 { "BIF_ROM_REQ_CREDIT", 15, 15, &umr_bitfield_default },
+	 { "BIF_SRBM_REQ_CREDIT", 0, 4, &umr_bitfield_default },
+	 { "BIF_VGA_REQ_CREDIT", 5, 8, &umr_bitfield_default },
+	 { "BIF_XDMA_REQ_CREDIT", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CNTL[] = {
+	 { "GEN_GPIO_INT_EN", 9, 12, &umr_bitfield_default },
+	 { "GEN_IH_INT_EN", 8, 8, &umr_bitfield_default },
+	 { "IH_DUMMY_RD_EN", 1, 1, &umr_bitfield_default },
+	 { "IH_DUMMY_RD_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "IH_INTR_DLY_CNTR", 4, 7, &umr_bitfield_default },
+	 { "IH_REQ_NONSNOOP_EN", 3, 3, &umr_bitfield_default },
+	 { "SELECT_INT_GPIO_OUTPUT", 13, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CNTL2[] = {
+	 { "IH_DUMMY_RD_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_CNTL[] = {
+	 { "DEBUG_BYTESEL_BLK1", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK2", 5, 5, &umr_bitfield_default },
+	 { "DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK1", 8, 12, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK2", 16, 20, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_XSP", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_MULTIBLOCKEN", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "DEBUG_PAD_SEL", 3, 3, &umr_bitfield_default },
+	 { "DEBUG_SWAP", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_SYNC_CLKSEL", 30, 31, &umr_bitfield_default },
+	 { "DEBUG_SYNC_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_MUX[] = {
+	 { "DEBUG_MUX_BLK1", 0, 5, &umr_bitfield_default },
+	 { "DEBUG_MUX_BLK2", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_OUT[] = {
+	 { "DEBUG_OUTPUT", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_CLK_PDWN_DELAY_TIMER[] = {
+	 { "TIMER", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEM_COHERENCY_FLUSH_CNTL[] = {
+	 { "HDP_MEM_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCLKREQB_PAD_CNTL[] = {
+	 { "CLKREQB_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "CLKREQB_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+	 { "CLKREQB_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "CLKREQB_PAD_WAKE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBDAT_PAD_CNTL[] = {
+	 { "SMBDAT_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "SMBDAT_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+	 { "SMBDAT_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "SMBDAT_PAD_WAKE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBCLK_PAD_CNTL[] = {
+	 { "SMBCLK_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "SMBCLK_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+	 { "SMBCLK_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "SMBCLK_PAD_WAKE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_FB_EN[] = {
+	 { "FB_READ_EN", 0, 0, &umr_bitfield_default },
+	 { "FB_WRITE_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_CNTL1[] = {
+	 { "ID_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_LIST0[] = {
+	 { "ID0", 0, 7, &umr_bitfield_default },
+	 { "ID1", 8, 15, &umr_bitfield_default },
+	 { "ID2", 16, 23, &umr_bitfield_default },
+	 { "ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_LIST1[] = {
+	 { "ID4", 0, 7, &umr_bitfield_default },
+	 { "ID5", 8, 15, &umr_bitfield_default },
+	 { "ID6", 16, 23, &umr_bitfield_default },
+	 { "ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_REG_COHERENCY_FLUSH_CNTL[] = {
+	 { "HDP_REG_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSY_DELAY_CNTR[] = {
+	 { "DELAY_CNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_CNTL2[] = {
+	 { "AUTOUPDATE_EN", 8, 8, &umr_bitfield_default },
+	 { "AUTOUPDATE_SEL", 0, 7, &umr_bitfield_default },
+	 { "ERROR_MULTIPLE_ID_MATCH", 17, 17, &umr_bitfield_default },
+	 { "HDPREG_CNTL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFMON_CNTL[] = {
+	 { "PERFCOUNTER_EN", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET0", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET1", 2, 2, &umr_bitfield_default },
+	 { "PERF_SEL0", 8, 12, &umr_bitfield_default },
+	 { "PERF_SEL1", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFCOUNTER0_RESULT[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFCOUNTER1_RESULT[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PIF_TXCLK_SWITCH_TIMER[] = {
+	 { "PLL0_ACK_TIMER", 0, 2, &umr_bitfield_default },
+	 { "PLL1_ACK_TIMER", 3, 5, &umr_bitfield_default },
+	 { "PLL_SWITCH_TIMER", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_HANG_PROTECTION_CNTL[] = {
+	 { "HANG_PROTECTION_TIMER_SEL", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_HANG_ERROR[] = {
+	 { "AUDIO_HANG_ERROR", 4, 4, &umr_bitfield_default },
+	 { "CEC_HANG_ERROR", 5, 5, &umr_bitfield_default },
+	 { "HDP_HANG_ERROR", 1, 1, &umr_bitfield_default },
+	 { "ROM_HANG_ERROR", 3, 3, &umr_bitfield_default },
+	 { "SRBM_HANG_ERROR", 0, 0, &umr_bitfield_default },
+	 { "VGA_HANG_ERROR", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCAPTURE_HOST_BUSNUM[] = {
+	 { "CHECK_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHOST_BUSNUM[] = {
+	 { "HOST_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER_REG_RANGE0[] = {
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER_REG_RANGE1[] = {
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG0[] = {
+	 { "RX_CFG_ADAPT_MODE_GEN1", 0, 9, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN2", 10, 19, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN3", 20, 29, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_RST_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG1[] = {
+	 { "RX_ADAPT_HLD_ASRT_TO_DCLK_EN", 30, 31, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN1", 24, 24, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN2", 25, 25, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN3", 26, 26, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN3", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG2[] = {
+	 { "RX_CFG_CDR_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN1", 24, 25, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN2", 26, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN3", 28, 29, &umr_bitfield_default },
+	 { "RX_DCLK_EN_ASRT_TO_ADAPT_HLD", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG3[] = {
+	 { "RX_CFG_CDR_FR_EN_GEN1", 0, 0, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN2", 1, 1, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN3", 2, 2, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG4[] = {
+	 { "RX_CFG_FOM_BER_GEN1", 0, 2, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN2", 3, 5, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN3", 6, 8, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN3", 28, 31, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN1", 9, 11, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN2", 12, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN3", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG5[] = {
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1", 0, 4, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2", 5, 9, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3", 10, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN1", 15, 15, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN2", 16, 16, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN3", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN1", 18, 18, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN2", 19, 19, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN3", 20, 20, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG6[] = {
+	 { "RX_AUX_PWRON_LUT_ENTRY_LS2", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0", 24, 24, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS2", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG7[] = {
+	 { "RX_CFG_DLL_CPI_SEL_GEN1", 18, 20, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN2", 21, 23, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN3", 24, 26, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS2", 13, 13, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_LUT_ENTRY_LS2", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3", 4, 4, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15", 7, 7, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7", 5, 5, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11", 6, 6, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L0T3", 16, 16, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L12T15", 19, 19, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L4T7", 17, 17, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L8T11", 18, 18, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L0T3", 20, 20, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L12T15", 23, 23, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L4T7", 21, 21, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L8T11", 22, 22, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_OVRD_REG0[] = {
+	 { "RX_ADAPT_FOM_OVRD_EN", 31, 31, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_VAL", 6, 7, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_VAL", 15, 15, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_EN", 18, 18, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_VAL", 17, 17, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_EN", 20, 20, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_VAL", 19, 19, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_EN", 22, 22, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_VAL", 21, 21, &umr_bitfield_default },
+	 { "RX_TERM_EN_OVRD_EN", 24, 24, &umr_bitfield_default },
+	 { "RX_TERM_EN_OVRD_VAL", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_OVRD_REG1[] = {
+	 { "RX_ADAPT_TRK_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "RX_ADAPT_TRK_OVRD_VAL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE0_CTRL_REG0[] = {
+	 { "RX_BACKUP_0", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_0", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_0", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_0", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_0", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_0", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_0", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE1_CTRL_REG0[] = {
+	 { "RX_BACKUP_1", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_1", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_1", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_1", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_1", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_1", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_1", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE2_CTRL_REG0[] = {
+	 { "RX_BACKUP_2", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_2", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_2", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_2", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_2", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_2", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_2", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE3_CTRL_REG0[] = {
+	 { "RX_BACKUP_3", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_3", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_3", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_3", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_3", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_3", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_3", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE4_CTRL_REG0[] = {
+	 { "RX_BACKUP_4", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_4", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_4", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_4", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_4", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_4", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_4", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE5_CTRL_REG0[] = {
+	 { "RX_BACKUP_5", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_5", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_5", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_5", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_5", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_5", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_5", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE6_CTRL_REG0[] = {
+	 { "RX_BACKUP_6", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_6", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_6", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_6", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_6", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_6", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_6", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE7_CTRL_REG0[] = {
+	 { "RX_BACKUP_7", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_7", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_7", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_7", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_7", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_7", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_7", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE8_CTRL_REG0[] = {
+	 { "RX_BACKUP_8", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_8", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_8", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_8", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_8", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_8", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_8", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_8", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_8", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_8", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE9_CTRL_REG0[] = {
+	 { "RX_BACKUP_9", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_9", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_9", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_9", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_9", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_9", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_9", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_9", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_9", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_9", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE10_CTRL_REG0[] = {
+	 { "RX_BACKUP_10", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_10", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_10", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_10", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_10", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_10", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_10", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_10", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_10", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_10", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE11_CTRL_REG0[] = {
+	 { "RX_BACKUP_11", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_11", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_11", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_11", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_11", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_11", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_11", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_11", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_11", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_11", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE12_CTRL_REG0[] = {
+	 { "RX_BACKUP_12", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_12", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_12", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_12", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_12", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_12", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_12", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_12", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_12", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_12", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE13_CTRL_REG0[] = {
+	 { "RX_BACKUP_13", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_13", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_13", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_13", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_13", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_13", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_13", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_13", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_13", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_13", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE14_CTRL_REG0[] = {
+	 { "RX_BACKUP_14", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_14", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_14", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_14", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_14", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_14", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_14", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_14", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_14", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_14", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE15_CTRL_REG0[] = {
+	 { "RX_BACKUP_15", 0, 7, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_15", 13, 13, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_15", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_15", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "ELECIDLEDETEN_15", 3, 3, &umr_bitfield_default },
+	 { "ENABLEFOM_15", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_15", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_15", 9, 9, &umr_bitfield_default },
+	 { "RXPRESETHINT_15", 4, 6, &umr_bitfield_default },
+	 { "RXPWR_15", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_CTRL_REG0[] = {
+	 { "TX_CFG_RPTR_RST_VAL_GEN1", 8, 10, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN2", 11, 13, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN3", 14, 16, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_DIR_VER", 22, 22, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_EN", 21, 21, &umr_bitfield_default },
+	 { "TX_DATA_CLK_GATING", 19, 19, &umr_bitfield_default },
+	 { "TX_DCLK_EN_LSX_ALWAYS_ON", 23, 23, &umr_bitfield_default },
+	 { "TX_DRV_DATA_ASRT_DLY_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_DSRT_DLY_VAL", 3, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_IN_OFF", 24, 24, &umr_bitfield_default },
+	 { "TX_PRESET_TABLE_BYPASS", 20, 20, &umr_bitfield_default },
+	 { "TX_STAGGER_CTRL", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_LANE_SKEW_CTRL[] = {
+	 { "TX_CFG_GROUPX16_EN_L0T15", 30, 30, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_10", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_11", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_12", 12, 12, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_13", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_14", 14, 14, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_15", 15, 15, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_6", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_7", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_8", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_9", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L0T1", 16, 16, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L10T11", 21, 21, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L12T13", 22, 22, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L14T15", 23, 23, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L2T3", 17, 17, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L4T5", 18, 18, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L6T7", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L8T9", 20, 20, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L0T3", 24, 24, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L12T15", 27, 27, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L4T7", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L8T11", 26, 26, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L0T7", 28, 28, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L8T15", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L0T3", 4, 4, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L12T15", 7, 7, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L4T7", 5, 5, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L8T11", 6, 6, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[] = {
+	 { "ACCEPT_ENTRY_0", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_10", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_11", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_12", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_13", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_14", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_15", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_16", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_17", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_18", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_19", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_1", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_20", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_21", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_22", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_23", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_24", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_25", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_26", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_27", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_28", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_29", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_2", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_30", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_31", 31, 31, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_3", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_4", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_5", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_6", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_7", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_8", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_9", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[] = {
+	 { "ACCEPT_ENTRY_32", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_33", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_34", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_35", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_36", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_37", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_38", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_39", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_40", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_41", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_42", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_43", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_44", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_45", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_46", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_47", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_48", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_49", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_50", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_51", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_52", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_53", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_54", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_55", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_56", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_57", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_58", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_59", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_60", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_61", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_62", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_63", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[] = {
+	 { "ACCEPT_ENTRY_64", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_65", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_66", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_67", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_68", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_69", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_70", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_71", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_72", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_73", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_74", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_75", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_76", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_77", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_78", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_79", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_80", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_81", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_82", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_83", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_84", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_85", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_86", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_87", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_88", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_89", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_90", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_91", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_92", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_93", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_94", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_95", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[] = {
+	 { "ACCEPT_ENTRY_100", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_101", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_102", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_103", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_104", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_105", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_106", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_107", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_108", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_109", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_96", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_97", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_98", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_99", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG0[] = {
+	 { "TX_CFG_DCLK_DIV_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_DCLK_DIV_OVRD_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN1_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL", 9, 12, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_OVRD_EN", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN1_OVRD_VAL", 14, 18, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_OVRD_EN", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN1_OVRD_VAL", 26, 29, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_OVRD_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG1[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_OVRD_EN", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN1_OVRD_VAL", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_OVRD_EN", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_VAL", 15, 24, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_EN", 27, 27, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_VAL", 26, 26, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_EN", 31, 31, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_VAL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG2[] = {
+	 { "TX_CFG_DRV0_EN_GEN2_OVRD_VAL", 12, 15, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL", 16, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN2_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL", 25, 29, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_EN", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_VAL", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_EN", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_EN", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_VAL", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_EN", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_WRITE_EN_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TX_WRITE_EN_OVRD_VAL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG3[] = {
+	 { "TX_CFG_DRV0_EN_GEN3_OVRD_VAL", 10, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL", 14, 17, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN3_OVRD_VAL", 18, 22, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL", 23, 27, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN2_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN3_OVRD_VAL", 28, 31, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN2_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG4[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN3_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_0", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_0", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_0", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_0", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_0", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_0", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_0", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_1", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_1", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_1", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_1", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_1", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_1", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_1", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_1", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_1", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_1", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_2", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_2", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_2", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_2", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_2", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_2", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_2", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_2", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_2", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_2", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_3", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_3", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_3", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_3", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_3", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_3", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_3", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_3", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_3", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_3", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_3", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_4", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_4", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_4", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_4", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_4", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_4", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_4", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_4", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_4", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_4", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_5", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_5", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_5", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_5", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_5", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_5", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_5", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_5", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_5", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_5", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_5", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_6", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_6", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_6", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_6", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_6", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_6", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_6", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_6", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_6", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_6", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_6", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_7", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_7", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_7", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_7", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_7", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_7", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_7", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_7", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_7", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_7", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_7", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_8", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_8", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_8", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_8", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_8", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_8", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_8", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_8", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_8", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_8", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_8", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_8", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_8", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_8", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_8", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_8", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_9", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_9", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_9", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_9", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_9", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_9", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_9", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_9", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_9", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_9", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_9", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_9", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_9", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_9", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_9", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_9", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_10", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_10", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_10", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_10", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_10", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_10", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_10", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_10", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_10", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_10", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_10", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_10", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_10", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_10", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_10", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_10", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_11", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_11", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_11", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_11", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_11", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_11", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_11", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_11", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_11", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_11", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_11", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_11", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_11", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_11", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_11", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_11", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_12", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_12", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_12", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_12", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_12", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_12", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_12", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_12", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_12", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_12", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_12", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_12", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_12", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_12", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_12", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_12", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_13", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_13", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_13", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_13", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_13", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_13", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_13", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_13", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_13", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_13", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_13", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_13", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_13", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_13", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_13", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_13", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_14", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_14", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_14", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_14", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_14", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_14", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_14", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_14", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_14", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_14", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_14", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_14", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_14", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_14", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_14", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_14", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_15", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_15", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_15", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_EN_15", 1, 1, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_VAL_15", 0, 0, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_15", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_15", 5, 5, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_15", 4, 4, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_15", 7, 7, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_15", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "COEFFICIENT_15", 10, 15, &umr_bitfield_default },
+	 { "COEFFICIENTID_15", 8, 9, &umr_bitfield_default },
+	 { "DEEMPH_15", 7, 7, &umr_bitfield_default },
+	 { "INCOHERENTCK_15", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_15", 4, 6, &umr_bitfield_default },
+	 { "TXPWR_15", 0, 2, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/bif30_regs.i b/src/lib/ip/bif30_regs.i
new file mode 100644
index 0000000..afed1e1
--- /dev/null
+++ b/src/lib/ip/bif30_regs.i
@@ -0,0 +1,386 @@
+	{ "ixPCIEP_RESERVED", REG_SMC, 0x0000, &ixPCIEP_RESERVED[0], sizeof(ixPCIEP_RESERVED)/sizeof(ixPCIEP_RESERVED[0]), 0, 0 },
+	{ "ixPB0_PIF_SCRATCH", REG_SMC, 0x0001, &ixPB0_PIF_SCRATCH[0], sizeof(ixPB0_PIF_SCRATCH)/sizeof(ixPB0_PIF_SCRATCH[0]), 0, 0 },
+	{ "ixPB0_PIF_HW_DEBUG", REG_SMC, 0x0002, &ixPB0_PIF_HW_DEBUG[0], sizeof(ixPB0_PIF_HW_DEBUG)/sizeof(ixPB0_PIF_HW_DEBUG[0]), 0, 0 },
+	{ "mmMM_INDEX_HI", REG_MMIO, 0x0006, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
+	{ "mmPCIE_INDEX", REG_MMIO, 0x000C, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
+	{ "mmPCIE_DATA", REG_MMIO, 0x000D, &mmPCIE_DATA[0], sizeof(mmPCIE_DATA)/sizeof(mmPCIE_DATA[0]), 0, 0 },
+	{ "ixPCIE_RX_NUM_NAK", REG_SMC, 0x000E, &ixPCIE_RX_NUM_NAK[0], sizeof(ixPCIE_RX_NUM_NAK)/sizeof(ixPCIE_RX_NUM_NAK[0]), 0, 0 },
+	{ "ixPCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x000F, &ixPCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 },
+	{ "ixPB0_PIF_CNTL", REG_SMC, 0x0010, &ixPB0_PIF_CNTL[0], sizeof(ixPB0_PIF_CNTL)/sizeof(ixPB0_PIF_CNTL[0]), 0, 0 },
+	{ "ixPB0_PIF_PAIRING", REG_SMC, 0x0011, &ixPB0_PIF_PAIRING[0], sizeof(ixPB0_PIF_PAIRING)/sizeof(ixPB0_PIF_PAIRING[0]), 0, 0 },
+	{ "ixPB0_PIF_PWRDOWN_0", REG_SMC, 0x0012, &ixPB0_PIF_PWRDOWN_0[0], sizeof(ixPB0_PIF_PWRDOWN_0)/sizeof(ixPB0_PIF_PWRDOWN_0[0]), 0, 0 },
+	{ "ixPB0_PIF_PWRDOWN_1", REG_SMC, 0x0013, &ixPB0_PIF_PWRDOWN_1[0], sizeof(ixPB0_PIF_PWRDOWN_1)/sizeof(ixPB0_PIF_PWRDOWN_1[0]), 0, 0 },
+	{ "ixPB0_PIF_CNTL2", REG_SMC, 0x0014, &ixPB0_PIF_CNTL2[0], sizeof(ixPB0_PIF_CNTL2)/sizeof(ixPB0_PIF_CNTL2[0]), 0, 0 },
+	{ "ixPB0_PIF_TXPHYSTATUS", REG_SMC, 0x0015, &ixPB0_PIF_TXPHYSTATUS[0], sizeof(ixPB0_PIF_TXPHYSTATUS)/sizeof(ixPB0_PIF_TXPHYSTATUS[0]), 0, 0 },
+	{ "ixPB0_PIF_SC_CTL", REG_SMC, 0x0016, &ixPB0_PIF_SC_CTL[0], sizeof(ixPB0_PIF_SC_CTL)/sizeof(ixPB0_PIF_SC_CTL[0]), 0, 0 },
+	{ "ixPB0_PIF_PWRDOWN_2", REG_SMC, 0x0017, &ixPB0_PIF_PWRDOWN_2[0], sizeof(ixPB0_PIF_PWRDOWN_2)/sizeof(ixPB0_PIF_PWRDOWN_2[0]), 0, 0 },
+	{ "ixPB0_PIF_PWRDOWN_3", REG_SMC, 0x0018, &ixPB0_PIF_PWRDOWN_3[0], sizeof(ixPB0_PIF_PWRDOWN_3)/sizeof(ixPB0_PIF_PWRDOWN_3[0]), 0, 0 },
+	{ "ixPCIE_INT_CNTL", REG_SMC, 0x001A, &ixPCIE_INT_CNTL[0], sizeof(ixPCIE_INT_CNTL)/sizeof(ixPCIE_INT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_INT_STATUS", REG_SMC, 0x001B, &ixPCIE_INT_STATUS[0], sizeof(ixPCIE_INT_STATUS)/sizeof(ixPCIE_INT_STATUS[0]), 0, 0 },
+	{ "ixPCIE_CNTL2", REG_SMC, 0x001C, &ixPCIE_CNTL2[0], sizeof(ixPCIE_CNTL2)/sizeof(ixPCIE_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL2", REG_SMC, 0x001D, &ixPCIE_RX_CNTL2[0], sizeof(ixPCIE_RX_CNTL2)/sizeof(ixPCIE_RX_CNTL2[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_0", REG_SMC, 0x0020, &ixPB0_PIF_PDNB_OVERRIDE_0[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_0)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_0[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_1", REG_SMC, 0x0021, &ixPB0_PIF_PDNB_OVERRIDE_1[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_1)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_1[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_2", REG_SMC, 0x0022, &ixPB0_PIF_PDNB_OVERRIDE_2[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_2)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_2[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_3", REG_SMC, 0x0023, &ixPB0_PIF_PDNB_OVERRIDE_3[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_3)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_3[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_4", REG_SMC, 0x0024, &ixPB0_PIF_PDNB_OVERRIDE_4[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_4)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_4[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_5", REG_SMC, 0x0025, &ixPB0_PIF_PDNB_OVERRIDE_5[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_5)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_5[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_6", REG_SMC, 0x0026, &ixPB0_PIF_PDNB_OVERRIDE_6[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_6)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_6[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_7", REG_SMC, 0x0027, &ixPB0_PIF_PDNB_OVERRIDE_7[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_7)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_7[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_0", REG_SMC, 0x0028, &ixPB0_PIF_SEQ_STATUS_0[0], sizeof(ixPB0_PIF_SEQ_STATUS_0)/sizeof(ixPB0_PIF_SEQ_STATUS_0[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_1", REG_SMC, 0x0029, &ixPB0_PIF_SEQ_STATUS_1[0], sizeof(ixPB0_PIF_SEQ_STATUS_1)/sizeof(ixPB0_PIF_SEQ_STATUS_1[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_2", REG_SMC, 0x002A, &ixPB0_PIF_SEQ_STATUS_2[0], sizeof(ixPB0_PIF_SEQ_STATUS_2)/sizeof(ixPB0_PIF_SEQ_STATUS_2[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_3", REG_SMC, 0x002B, &ixPB0_PIF_SEQ_STATUS_3[0], sizeof(ixPB0_PIF_SEQ_STATUS_3)/sizeof(ixPB0_PIF_SEQ_STATUS_3[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_4", REG_SMC, 0x002C, &ixPB0_PIF_SEQ_STATUS_4[0], sizeof(ixPB0_PIF_SEQ_STATUS_4)/sizeof(ixPB0_PIF_SEQ_STATUS_4[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_5", REG_SMC, 0x002D, &ixPB0_PIF_SEQ_STATUS_5[0], sizeof(ixPB0_PIF_SEQ_STATUS_5)/sizeof(ixPB0_PIF_SEQ_STATUS_5[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_6", REG_SMC, 0x002E, &ixPB0_PIF_SEQ_STATUS_6[0], sizeof(ixPB0_PIF_SEQ_STATUS_6)/sizeof(ixPB0_PIF_SEQ_STATUS_6[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_7", REG_SMC, 0x002F, &ixPB0_PIF_SEQ_STATUS_7[0], sizeof(ixPB0_PIF_SEQ_STATUS_7)/sizeof(ixPB0_PIF_SEQ_STATUS_7[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_8", REG_SMC, 0x0030, &ixPB0_PIF_PDNB_OVERRIDE_8[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_8)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_8[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_9", REG_SMC, 0x0031, &ixPB0_PIF_PDNB_OVERRIDE_9[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_9)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_9[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_10", REG_SMC, 0x0032, &ixPB0_PIF_PDNB_OVERRIDE_10[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_10)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_10[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_11", REG_SMC, 0x0033, &ixPB0_PIF_PDNB_OVERRIDE_11[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_11)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_11[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_12", REG_SMC, 0x0034, &ixPB0_PIF_PDNB_OVERRIDE_12[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_12)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_12[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_13", REG_SMC, 0x0035, &ixPB0_PIF_PDNB_OVERRIDE_13[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_13)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_13[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_14", REG_SMC, 0x0036, &ixPB0_PIF_PDNB_OVERRIDE_14[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_14)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_14[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_15", REG_SMC, 0x0037, &ixPB0_PIF_PDNB_OVERRIDE_15[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_15)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_15[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_8", REG_SMC, 0x0038, &ixPB0_PIF_SEQ_STATUS_8[0], sizeof(ixPB0_PIF_SEQ_STATUS_8)/sizeof(ixPB0_PIF_SEQ_STATUS_8[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_9", REG_SMC, 0x0039, &ixPB0_PIF_SEQ_STATUS_9[0], sizeof(ixPB0_PIF_SEQ_STATUS_9)/sizeof(ixPB0_PIF_SEQ_STATUS_9[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_10", REG_SMC, 0x003A, &ixPB0_PIF_SEQ_STATUS_10[0], sizeof(ixPB0_PIF_SEQ_STATUS_10)/sizeof(ixPB0_PIF_SEQ_STATUS_10[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_11", REG_SMC, 0x003B, &ixPB0_PIF_SEQ_STATUS_11[0], sizeof(ixPB0_PIF_SEQ_STATUS_11)/sizeof(ixPB0_PIF_SEQ_STATUS_11[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_12", REG_SMC, 0x003C, &ixPB0_PIF_SEQ_STATUS_12[0], sizeof(ixPB0_PIF_SEQ_STATUS_12)/sizeof(ixPB0_PIF_SEQ_STATUS_12[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_13", REG_SMC, 0x003D, &ixPB0_PIF_SEQ_STATUS_13[0], sizeof(ixPB0_PIF_SEQ_STATUS_13)/sizeof(ixPB0_PIF_SEQ_STATUS_13[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_14", REG_SMC, 0x003E, &ixPB0_PIF_SEQ_STATUS_14[0], sizeof(ixPB0_PIF_SEQ_STATUS_14)/sizeof(ixPB0_PIF_SEQ_STATUS_14[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_15", REG_SMC, 0x003F, &ixPB0_PIF_SEQ_STATUS_15[0], sizeof(ixPB0_PIF_SEQ_STATUS_15)/sizeof(ixPB0_PIF_SEQ_STATUS_15[0]), 0, 0 },
+	{ "ixPCIE_P_CNTL", REG_SMC, 0x0040, &ixPCIE_P_CNTL[0], sizeof(ixPCIE_P_CNTL)/sizeof(ixPCIE_P_CNTL[0]), 0, 0 },
+	{ "ixPCIE_P_BUF_STATUS", REG_SMC, 0x0041, &ixPCIE_P_BUF_STATUS[0], sizeof(ixPCIE_P_BUF_STATUS)/sizeof(ixPCIE_P_BUF_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_DECODER_STATUS", REG_SMC, 0x0042, &ixPCIE_P_DECODER_STATUS[0], sizeof(ixPCIE_P_DECODER_STATUS)/sizeof(ixPCIE_P_DECODER_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_MISC_STATUS", REG_SMC, 0x0043, &ixPCIE_P_MISC_STATUS[0], sizeof(ixPCIE_P_MISC_STATUS)/sizeof(ixPCIE_P_MISC_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_PORT_LANE_STATUS", REG_SMC, 0x0050, &ixPCIE_P_PORT_LANE_STATUS[0], sizeof(ixPCIE_P_PORT_LANE_STATUS)/sizeof(ixPCIE_P_PORT_LANE_STATUS[0]), 0, 0 },
+	{ "ixPCIE_FC_P", REG_SMC, 0x0060, &ixPCIE_FC_P[0], sizeof(ixPCIE_FC_P)/sizeof(ixPCIE_FC_P[0]), 0, 0 },
+	{ "ixPCIE_FC_NP", REG_SMC, 0x0061, &ixPCIE_FC_NP[0], sizeof(ixPCIE_FC_NP)/sizeof(ixPCIE_FC_NP[0]), 0, 0 },
+	{ "ixPCIE_FC_CPL", REG_SMC, 0x0062, &ixPCIE_FC_CPL[0], sizeof(ixPCIE_FC_CPL)/sizeof(ixPCIE_FC_CPL[0]), 0, 0 },
+	{ "ixPCIE_ERR_CNTL", REG_SMC, 0x006A, &ixPCIE_ERR_CNTL[0], sizeof(ixPCIE_ERR_CNTL)/sizeof(ixPCIE_ERR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL", REG_SMC, 0x0070, &ixPCIE_RX_CNTL[0], sizeof(ixPCIE_RX_CNTL)/sizeof(ixPCIE_RX_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_EXPECTED_SEQNUM", REG_SMC, 0x0071, &ixPCIE_RX_EXPECTED_SEQNUM[0], sizeof(ixPCIE_RX_EXPECTED_SEQNUM)/sizeof(ixPCIE_RX_EXPECTED_SEQNUM[0]), 0, 0 },
+	{ "ixPCIE_RX_VENDOR_SPECIFIC", REG_SMC, 0x0072, &ixPCIE_RX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_RX_VENDOR_SPECIFIC)/sizeof(ixPCIE_RX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL3", REG_SMC, 0x0074, &ixPCIE_RX_CNTL3[0], sizeof(ixPCIE_RX_CNTL3)/sizeof(ixPCIE_RX_CNTL3[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT_CNTL", REG_SMC, 0x0080, &ixPCIE_PERF_COUNT_CNTL[0], sizeof(ixPCIE_PERF_COUNT_CNTL)/sizeof(ixPCIE_PERF_COUNT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_TXCLK", REG_SMC, 0x0081, &ixPCIE_PERF_CNTL_TXCLK[0], sizeof(ixPCIE_PERF_CNTL_TXCLK)/sizeof(ixPCIE_PERF_CNTL_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x0082, &ixPCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK)/sizeof(ixPCIE_PERF_COUNT0_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x0083, &ixPCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK)/sizeof(ixPCIE_PERF_COUNT1_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x0084, &ixPCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x0085, &ixPCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x0086, &ixPCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x0087, &ixPCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x0088, &ixPCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x0089, &ixPCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x008A, &ixPCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x008B, &ixPCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x008C, &ixPCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x008D, &ixPCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x008E, &ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x008F, &ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x0090, &ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x0091, &ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x0092, &ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x0093, &ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x0094, &ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x0095, &ixPCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPCIE_PERF_CNTL_TXCLK2)/sizeof(ixPCIE_PERF_CNTL_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x0096, &ixPCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x0097, &ixPCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL", REG_SMC, 0x00A0, &ixPCIE_LC_CNTL[0], sizeof(ixPCIE_LC_CNTL)/sizeof(ixPCIE_LC_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_TRAINING_CNTL", REG_SMC, 0x00A1, &ixPCIE_LC_TRAINING_CNTL[0], sizeof(ixPCIE_LC_TRAINING_CNTL)/sizeof(ixPCIE_LC_TRAINING_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_LINK_WIDTH_CNTL", REG_SMC, 0x00A2, &ixPCIE_LC_LINK_WIDTH_CNTL[0], sizeof(ixPCIE_LC_LINK_WIDTH_CNTL)/sizeof(ixPCIE_LC_LINK_WIDTH_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_N_FTS_CNTL", REG_SMC, 0x00A3, &ixPCIE_LC_N_FTS_CNTL[0], sizeof(ixPCIE_LC_N_FTS_CNTL)/sizeof(ixPCIE_LC_N_FTS_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_SPEED_CNTL", REG_SMC, 0x00A4, &ixPCIE_LC_SPEED_CNTL[0], sizeof(ixPCIE_LC_SPEED_CNTL)/sizeof(ixPCIE_LC_SPEED_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE0", REG_SMC, 0x00A5, &ixPCIE_LC_STATE0[0], sizeof(ixPCIE_LC_STATE0)/sizeof(ixPCIE_LC_STATE0[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE1", REG_SMC, 0x00A6, &ixPCIE_LC_STATE1[0], sizeof(ixPCIE_LC_STATE1)/sizeof(ixPCIE_LC_STATE1[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE2", REG_SMC, 0x00A7, &ixPCIE_LC_STATE2[0], sizeof(ixPCIE_LC_STATE2)/sizeof(ixPCIE_LC_STATE2[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE3", REG_SMC, 0x00A8, &ixPCIE_LC_STATE3[0], sizeof(ixPCIE_LC_STATE3)/sizeof(ixPCIE_LC_STATE3[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE4", REG_SMC, 0x00A9, &ixPCIE_LC_STATE4[0], sizeof(ixPCIE_LC_STATE4)/sizeof(ixPCIE_LC_STATE4[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE5", REG_SMC, 0x00AA, &ixPCIE_LC_STATE5[0], sizeof(ixPCIE_LC_STATE5)/sizeof(ixPCIE_LC_STATE5[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F0", REG_SMC, 0x00B0, &ixPCIE_STRAP_F0[0], sizeof(ixPCIE_STRAP_F0)/sizeof(ixPCIE_STRAP_F0[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL2", REG_SMC, 0x00B1, &ixPCIE_LC_CNTL2[0], sizeof(ixPCIE_LC_CNTL2)/sizeof(ixPCIE_LC_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_LC_BW_CHANGE_CNTL", REG_SMC, 0x00B2, &ixPCIE_LC_BW_CHANGE_CNTL[0], sizeof(ixPCIE_LC_BW_CHANGE_CNTL)/sizeof(ixPCIE_LC_BW_CHANGE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_CDR_CNTL", REG_SMC, 0x00B3, &ixPCIE_LC_CDR_CNTL[0], sizeof(ixPCIE_LC_CDR_CNTL)/sizeof(ixPCIE_LC_CDR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_LANE_CNTL", REG_SMC, 0x00B4, &ixPCIE_LC_LANE_CNTL[0], sizeof(ixPCIE_LC_LANE_CNTL)/sizeof(ixPCIE_LC_LANE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL3", REG_SMC, 0x00B5, &ixPCIE_LC_CNTL3[0], sizeof(ixPCIE_LC_CNTL3)/sizeof(ixPCIE_LC_CNTL3[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL4", REG_SMC, 0x00B6, &ixPCIE_LC_CNTL4[0], sizeof(ixPCIE_LC_CNTL4)/sizeof(ixPCIE_LC_CNTL4[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL5", REG_SMC, 0x00B7, &ixPCIE_LC_CNTL5[0], sizeof(ixPCIE_LC_CNTL5)/sizeof(ixPCIE_LC_CNTL5[0]), 0, 0 },
+	{ "ixPCIE_LC_FORCE_COEFF", REG_SMC, 0x00B8, &ixPCIE_LC_FORCE_COEFF[0], sizeof(ixPCIE_LC_FORCE_COEFF)/sizeof(ixPCIE_LC_FORCE_COEFF[0]), 0, 0 },
+	{ "ixPCIE_LC_BEST_EQ_SETTINGS", REG_SMC, 0x00B9, &ixPCIE_LC_BEST_EQ_SETTINGS[0], sizeof(ixPCIE_LC_BEST_EQ_SETTINGS)/sizeof(ixPCIE_LC_BEST_EQ_SETTINGS[0]), 0, 0 },
+	{ "ixPCIE_LC_FORCE_EQ_REQ_COEFF", REG_SMC, 0x00BA, &ixPCIE_LC_FORCE_EQ_REQ_COEFF[0], sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF)/sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF[0]), 0, 0 },
+	{ "ixPCIEP_STRAP_LC", REG_SMC, 0x00C0, &ixPCIEP_STRAP_LC[0], sizeof(ixPCIEP_STRAP_LC)/sizeof(ixPCIEP_STRAP_LC[0]), 0, 0 },
+	{ "ixPCIEP_STRAP_MISC", REG_SMC, 0x00C1, &ixPCIEP_STRAP_MISC[0], sizeof(ixPCIEP_STRAP_MISC)/sizeof(ixPCIEP_STRAP_MISC[0]), 0, 0 },
+	{ "ixPCIE_STRAP_PI", REG_SMC, 0x00C2, &ixPCIE_STRAP_PI[0], sizeof(ixPCIE_STRAP_PI)/sizeof(ixPCIE_STRAP_PI[0]), 0, 0 },
+	{ "ixPCIE_STRAP_I2C_BD", REG_SMC, 0x00C4, &ixPCIE_STRAP_I2C_BD[0], sizeof(ixPCIE_STRAP_I2C_BD)/sizeof(ixPCIE_STRAP_I2C_BD[0]), 0, 0 },
+	{ "ixPCIE_PRBS_CLR", REG_SMC, 0x00C8, &ixPCIE_PRBS_CLR[0], sizeof(ixPCIE_PRBS_CLR)/sizeof(ixPCIE_PRBS_CLR[0]), 0, 0 },
+	{ "ixPCIE_PRBS_STATUS1", REG_SMC, 0x00C9, &ixPCIE_PRBS_STATUS1[0], sizeof(ixPCIE_PRBS_STATUS1)/sizeof(ixPCIE_PRBS_STATUS1[0]), 0, 0 },
+	{ "ixPCIE_PRBS_STATUS2", REG_SMC, 0x00CA, &ixPCIE_PRBS_STATUS2[0], sizeof(ixPCIE_PRBS_STATUS2)/sizeof(ixPCIE_PRBS_STATUS2[0]), 0, 0 },
+	{ "ixPCIE_PRBS_FREERUN", REG_SMC, 0x00CB, &ixPCIE_PRBS_FREERUN[0], sizeof(ixPCIE_PRBS_FREERUN)/sizeof(ixPCIE_PRBS_FREERUN[0]), 0, 0 },
+	{ "ixPCIE_PRBS_MISC", REG_SMC, 0x00CC, &ixPCIE_PRBS_MISC[0], sizeof(ixPCIE_PRBS_MISC)/sizeof(ixPCIE_PRBS_MISC[0]), 0, 0 },
+	{ "ixPCIE_PRBS_USER_PATTERN", REG_SMC, 0x00CD, &ixPCIE_PRBS_USER_PATTERN[0], sizeof(ixPCIE_PRBS_USER_PATTERN)/sizeof(ixPCIE_PRBS_USER_PATTERN[0]), 0, 0 },
+	{ "ixPCIE_PRBS_LO_BITCNT", REG_SMC, 0x00CE, &ixPCIE_PRBS_LO_BITCNT[0], sizeof(ixPCIE_PRBS_LO_BITCNT)/sizeof(ixPCIE_PRBS_LO_BITCNT[0]), 0, 0 },
+	{ "ixPCIE_PRBS_HI_BITCNT", REG_SMC, 0x00CF, &ixPCIE_PRBS_HI_BITCNT[0], sizeof(ixPCIE_PRBS_HI_BITCNT)/sizeof(ixPCIE_PRBS_HI_BITCNT[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_0", REG_SMC, 0x00D0, &ixPCIE_PRBS_ERRCNT_0[0], sizeof(ixPCIE_PRBS_ERRCNT_0)/sizeof(ixPCIE_PRBS_ERRCNT_0[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_1", REG_SMC, 0x00D1, &ixPCIE_PRBS_ERRCNT_1[0], sizeof(ixPCIE_PRBS_ERRCNT_1)/sizeof(ixPCIE_PRBS_ERRCNT_1[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_2", REG_SMC, 0x00D2, &ixPCIE_PRBS_ERRCNT_2[0], sizeof(ixPCIE_PRBS_ERRCNT_2)/sizeof(ixPCIE_PRBS_ERRCNT_2[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_3", REG_SMC, 0x00D3, &ixPCIE_PRBS_ERRCNT_3[0], sizeof(ixPCIE_PRBS_ERRCNT_3)/sizeof(ixPCIE_PRBS_ERRCNT_3[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_4", REG_SMC, 0x00D4, &ixPCIE_PRBS_ERRCNT_4[0], sizeof(ixPCIE_PRBS_ERRCNT_4)/sizeof(ixPCIE_PRBS_ERRCNT_4[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_5", REG_SMC, 0x00D5, &ixPCIE_PRBS_ERRCNT_5[0], sizeof(ixPCIE_PRBS_ERRCNT_5)/sizeof(ixPCIE_PRBS_ERRCNT_5[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_6", REG_SMC, 0x00D6, &ixPCIE_PRBS_ERRCNT_6[0], sizeof(ixPCIE_PRBS_ERRCNT_6)/sizeof(ixPCIE_PRBS_ERRCNT_6[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_7", REG_SMC, 0x00D7, &ixPCIE_PRBS_ERRCNT_7[0], sizeof(ixPCIE_PRBS_ERRCNT_7)/sizeof(ixPCIE_PRBS_ERRCNT_7[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_8", REG_SMC, 0x00D8, &ixPCIE_PRBS_ERRCNT_8[0], sizeof(ixPCIE_PRBS_ERRCNT_8)/sizeof(ixPCIE_PRBS_ERRCNT_8[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_9", REG_SMC, 0x00D9, &ixPCIE_PRBS_ERRCNT_9[0], sizeof(ixPCIE_PRBS_ERRCNT_9)/sizeof(ixPCIE_PRBS_ERRCNT_9[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_10", REG_SMC, 0x00DA, &ixPCIE_PRBS_ERRCNT_10[0], sizeof(ixPCIE_PRBS_ERRCNT_10)/sizeof(ixPCIE_PRBS_ERRCNT_10[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_11", REG_SMC, 0x00DB, &ixPCIE_PRBS_ERRCNT_11[0], sizeof(ixPCIE_PRBS_ERRCNT_11)/sizeof(ixPCIE_PRBS_ERRCNT_11[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_12", REG_SMC, 0x00DC, &ixPCIE_PRBS_ERRCNT_12[0], sizeof(ixPCIE_PRBS_ERRCNT_12)/sizeof(ixPCIE_PRBS_ERRCNT_12[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_13", REG_SMC, 0x00DD, &ixPCIE_PRBS_ERRCNT_13[0], sizeof(ixPCIE_PRBS_ERRCNT_13)/sizeof(ixPCIE_PRBS_ERRCNT_13[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_14", REG_SMC, 0x00DE, &ixPCIE_PRBS_ERRCNT_14[0], sizeof(ixPCIE_PRBS_ERRCNT_14)/sizeof(ixPCIE_PRBS_ERRCNT_14[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_15", REG_SMC, 0x00DF, &ixPCIE_PRBS_ERRCNT_15[0], sizeof(ixPCIE_PRBS_ERRCNT_15)/sizeof(ixPCIE_PRBS_ERRCNT_15[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_CAP", REG_SMC, 0x00E0, &ixPCIE_F0_DPA_CAP[0], sizeof(ixPCIE_F0_DPA_CAP)/sizeof(ixPCIE_F0_DPA_CAP[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_LATENCY_INDICATOR", REG_SMC, 0x00E4, &ixPCIE_F0_DPA_LATENCY_INDICATOR[0], sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR)/sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_CNTL", REG_SMC, 0x00E5, &ixPCIE_F0_DPA_CNTL[0], sizeof(ixPCIE_F0_DPA_CNTL)/sizeof(ixPCIE_F0_DPA_CNTL[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0", REG_SMC, 0x00E7, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1", REG_SMC, 0x00E8, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2", REG_SMC, 0x00E9, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3", REG_SMC, 0x00EA, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4", REG_SMC, 0x00EB, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5", REG_SMC, 0x00EC, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6", REG_SMC, 0x00ED, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7", REG_SMC, 0x00EE, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_0", REG_MMIO, 0x05C9, &mmBIOS_SCRATCH_0[0], sizeof(mmBIOS_SCRATCH_0)/sizeof(mmBIOS_SCRATCH_0[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_1", REG_MMIO, 0x05CA, &mmBIOS_SCRATCH_1[0], sizeof(mmBIOS_SCRATCH_1)/sizeof(mmBIOS_SCRATCH_1[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_2", REG_MMIO, 0x05CB, &mmBIOS_SCRATCH_2[0], sizeof(mmBIOS_SCRATCH_2)/sizeof(mmBIOS_SCRATCH_2[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_3", REG_MMIO, 0x05CC, &mmBIOS_SCRATCH_3[0], sizeof(mmBIOS_SCRATCH_3)/sizeof(mmBIOS_SCRATCH_3[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_4", REG_MMIO, 0x05CD, &mmBIOS_SCRATCH_4[0], sizeof(mmBIOS_SCRATCH_4)/sizeof(mmBIOS_SCRATCH_4[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_5", REG_MMIO, 0x05CE, &mmBIOS_SCRATCH_5[0], sizeof(mmBIOS_SCRATCH_5)/sizeof(mmBIOS_SCRATCH_5[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_6", REG_MMIO, 0x05CF, &mmBIOS_SCRATCH_6[0], sizeof(mmBIOS_SCRATCH_6)/sizeof(mmBIOS_SCRATCH_6[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_7", REG_MMIO, 0x05D0, &mmBIOS_SCRATCH_7[0], sizeof(mmBIOS_SCRATCH_7)/sizeof(mmBIOS_SCRATCH_7[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_8", REG_MMIO, 0x05D1, &mmBIOS_SCRATCH_8[0], sizeof(mmBIOS_SCRATCH_8)/sizeof(mmBIOS_SCRATCH_8[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_9", REG_MMIO, 0x05D2, &mmBIOS_SCRATCH_9[0], sizeof(mmBIOS_SCRATCH_9)/sizeof(mmBIOS_SCRATCH_9[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_10", REG_MMIO, 0x05D3, &mmBIOS_SCRATCH_10[0], sizeof(mmBIOS_SCRATCH_10)/sizeof(mmBIOS_SCRATCH_10[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_11", REG_MMIO, 0x05D4, &mmBIOS_SCRATCH_11[0], sizeof(mmBIOS_SCRATCH_11)/sizeof(mmBIOS_SCRATCH_11[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_12", REG_MMIO, 0x05D5, &mmBIOS_SCRATCH_12[0], sizeof(mmBIOS_SCRATCH_12)/sizeof(mmBIOS_SCRATCH_12[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_13", REG_MMIO, 0x05D6, &mmBIOS_SCRATCH_13[0], sizeof(mmBIOS_SCRATCH_13)/sizeof(mmBIOS_SCRATCH_13[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_14", REG_MMIO, 0x05D7, &mmBIOS_SCRATCH_14[0], sizeof(mmBIOS_SCRATCH_14)/sizeof(mmBIOS_SCRATCH_14[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_15", REG_MMIO, 0x05D8, &mmBIOS_SCRATCH_15[0], sizeof(mmBIOS_SCRATCH_15)/sizeof(mmBIOS_SCRATCH_15[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG0", REG_SMC, 0x10004, &ixPB0_GLB_CTRL_REG0[0], sizeof(ixPB0_GLB_CTRL_REG0)/sizeof(ixPB0_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG1", REG_SMC, 0x10008, &ixPB0_GLB_CTRL_REG1[0], sizeof(ixPB0_GLB_CTRL_REG1)/sizeof(ixPB0_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG2", REG_SMC, 0x1000C, &ixPB0_GLB_CTRL_REG2[0], sizeof(ixPB0_GLB_CTRL_REG2)/sizeof(ixPB0_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG3", REG_SMC, 0x10010, &ixPB0_GLB_CTRL_REG3[0], sizeof(ixPB0_GLB_CTRL_REG3)/sizeof(ixPB0_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG4", REG_SMC, 0x10014, &ixPB0_GLB_CTRL_REG4[0], sizeof(ixPB0_GLB_CTRL_REG4)/sizeof(ixPB0_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG5", REG_SMC, 0x10018, &ixPB0_GLB_CTRL_REG5[0], sizeof(ixPB0_GLB_CTRL_REG5)/sizeof(ixPB0_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x1001C, &ixPB0_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG1", REG_SMC, 0x10020, &ixPB0_GLB_SCI_STAT_OVRD_REG1[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG1)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG2", REG_SMC, 0x10024, &ixPB0_GLB_SCI_STAT_OVRD_REG2[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG2)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG3", REG_SMC, 0x10028, &ixPB0_GLB_SCI_STAT_OVRD_REG3[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG3)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG4", REG_SMC, 0x1002C, &ixPB0_GLB_SCI_STAT_OVRD_REG4[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG4)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG0", REG_SMC, 0x10030, &ixPB0_GLB_OVRD_REG0[0], sizeof(ixPB0_GLB_OVRD_REG0)/sizeof(ixPB0_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG1", REG_SMC, 0x10034, &ixPB0_GLB_OVRD_REG1[0], sizeof(ixPB0_GLB_OVRD_REG1)/sizeof(ixPB0_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG2", REG_SMC, 0x10038, &ixPB0_GLB_OVRD_REG2[0], sizeof(ixPB0_GLB_OVRD_REG2)/sizeof(ixPB0_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_HW_DEBUG", REG_SMC, 0x12004, &ixPB0_HW_DEBUG[0], sizeof(ixPB0_HW_DEBUG)/sizeof(ixPB0_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB0_STRAP_GLB_REG0", REG_SMC, 0x12020, &ixPB0_STRAP_GLB_REG0[0], sizeof(ixPB0_STRAP_GLB_REG0)/sizeof(ixPB0_STRAP_GLB_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_TX_REG0", REG_SMC, 0x12024, NULL, 0, 0, 0 },
+	{ "ixPB0_STRAP_RX_REG0", REG_SMC, 0x12028, NULL, 0, 0, 0 },
+	{ "ixPB0_STRAP_RX_REG1", REG_SMC, 0x1202C, NULL, 0, 0, 0 },
+	{ "ixPB0_STRAP_PLL_REG0", REG_SMC, 0x12030, NULL, 0, 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG0", REG_SMC, 0x13000, &ixPB0_DFT_JIT_INJ_REG0[0], sizeof(ixPB0_DFT_JIT_INJ_REG0)/sizeof(ixPB0_DFT_JIT_INJ_REG0[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG1", REG_SMC, 0x13004, &ixPB0_DFT_JIT_INJ_REG1[0], sizeof(ixPB0_DFT_JIT_INJ_REG1)/sizeof(ixPB0_DFT_JIT_INJ_REG1[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG2", REG_SMC, 0x13008, &ixPB0_DFT_JIT_INJ_REG2[0], sizeof(ixPB0_DFT_JIT_INJ_REG2)/sizeof(ixPB0_DFT_JIT_INJ_REG2[0]), 0, 0 },
+	{ "ixPB0_DFT_DEBUG_CTRL_REG0", REG_SMC, 0x1300C, &ixPB0_DFT_DEBUG_CTRL_REG0[0], sizeof(ixPB0_DFT_DEBUG_CTRL_REG0)/sizeof(ixPB0_DFT_DEBUG_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO_GLB_CTRL_REG0", REG_SMC, 0x14000, &ixPB0_PLL_RO_GLB_CTRL_REG0[0], sizeof(ixPB0_PLL_RO_GLB_CTRL_REG0)/sizeof(ixPB0_PLL_RO_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO_GLB_OVRD_REG0", REG_SMC, 0x14010, NULL, 0, 0, 0 },
+	{ "ixPB0_PLL_RO0_CTRL_REG0", REG_SMC, 0x14440, &ixPB0_PLL_RO0_CTRL_REG0[0], sizeof(ixPB0_PLL_RO0_CTRL_REG0)/sizeof(ixPB0_PLL_RO0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_OVRD_REG0", REG_SMC, 0x14450, &ixPB0_PLL_RO0_OVRD_REG0[0], sizeof(ixPB0_PLL_RO0_OVRD_REG0)/sizeof(ixPB0_PLL_RO0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_OVRD_REG1", REG_SMC, 0x14454, &ixPB0_PLL_RO0_OVRD_REG1[0], sizeof(ixPB0_PLL_RO0_OVRD_REG1)/sizeof(ixPB0_PLL_RO0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0", REG_SMC, 0x14460, &ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0", REG_SMC, 0x14464, &ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0", REG_SMC, 0x14468, &ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0", REG_SMC, 0x1446C, &ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_CTRL_REG0", REG_SMC, 0x14480, &ixPB0_PLL_LC0_CTRL_REG0[0], sizeof(ixPB0_PLL_LC0_CTRL_REG0)/sizeof(ixPB0_PLL_LC0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_OVRD_REG0", REG_SMC, 0x14490, &ixPB0_PLL_LC0_OVRD_REG0[0], sizeof(ixPB0_PLL_LC0_OVRD_REG0)/sizeof(ixPB0_PLL_LC0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_OVRD_REG1", REG_SMC, 0x14494, &ixPB0_PLL_LC0_OVRD_REG1[0], sizeof(ixPB0_PLL_LC0_OVRD_REG1)/sizeof(ixPB0_PLL_LC0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0", REG_SMC, 0x14500, &ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0", REG_SMC, 0x14504, &ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0", REG_SMC, 0x14508, &ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0", REG_SMC, 0x1450C, &ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "mmBIF_XDMA_LO", REG_MMIO, 0x14C0, &mmBIF_XDMA_LO[0], sizeof(mmBIF_XDMA_LO)/sizeof(mmBIF_XDMA_LO[0]), 0, 0 },
+	{ "mmBIF_XDMA_HI", REG_MMIO, 0x14C1, &mmBIF_XDMA_HI[0], sizeof(mmBIF_XDMA_HI)/sizeof(mmBIF_XDMA_HI[0]), 0, 0 },
+	{ "mmBIF_FEATURES_CONTROL_MISC", REG_MMIO, 0x14C2, &mmBIF_FEATURES_CONTROL_MISC[0], sizeof(mmBIF_FEATURES_CONTROL_MISC)/sizeof(mmBIF_FEATURES_CONTROL_MISC[0]), 0, 0 },
+	{ "mmSMBUS_BACO_DUMMY", REG_MMIO, 0x14C6, &mmSMBUS_BACO_DUMMY[0], sizeof(mmSMBUS_BACO_DUMMY)/sizeof(mmSMBUS_BACO_DUMMY[0]), 0, 0 },
+	{ "mmBF_ANA_ISO_CNTL", REG_MMIO, 0x14C7, &mmBF_ANA_ISO_CNTL[0], sizeof(mmBF_ANA_ISO_CNTL)/sizeof(mmBF_ANA_ISO_CNTL[0]), 0, 0 },
+	{ "mmBIF_SSA_PWR_STATUS", REG_MMIO, 0x14C8, &mmBIF_SSA_PWR_STATUS[0], sizeof(mmBIF_SSA_PWR_STATUS)/sizeof(mmBIF_SSA_PWR_STATUS[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX0_LOWER", REG_MMIO, 0x14CA, &mmBIF_SSA_GFX0_LOWER[0], sizeof(mmBIF_SSA_GFX0_LOWER)/sizeof(mmBIF_SSA_GFX0_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX0_UPPER", REG_MMIO, 0x14CB, &mmBIF_SSA_GFX0_UPPER[0], sizeof(mmBIF_SSA_GFX0_UPPER)/sizeof(mmBIF_SSA_GFX0_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX1_LOWER", REG_MMIO, 0x14CC, &mmBIF_SSA_GFX1_LOWER[0], sizeof(mmBIF_SSA_GFX1_LOWER)/sizeof(mmBIF_SSA_GFX1_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX1_UPPER", REG_MMIO, 0x14CD, &mmBIF_SSA_GFX1_UPPER[0], sizeof(mmBIF_SSA_GFX1_UPPER)/sizeof(mmBIF_SSA_GFX1_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX2_LOWER", REG_MMIO, 0x14CE, &mmBIF_SSA_GFX2_LOWER[0], sizeof(mmBIF_SSA_GFX2_LOWER)/sizeof(mmBIF_SSA_GFX2_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX2_UPPER", REG_MMIO, 0x14CF, &mmBIF_SSA_GFX2_UPPER[0], sizeof(mmBIF_SSA_GFX2_UPPER)/sizeof(mmBIF_SSA_GFX2_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX3_LOWER", REG_MMIO, 0x14D0, &mmBIF_SSA_GFX3_LOWER[0], sizeof(mmBIF_SSA_GFX3_LOWER)/sizeof(mmBIF_SSA_GFX3_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX3_UPPER", REG_MMIO, 0x14D1, &mmBIF_SSA_GFX3_UPPER[0], sizeof(mmBIF_SSA_GFX3_UPPER)/sizeof(mmBIF_SSA_GFX3_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_DISP_LOWER", REG_MMIO, 0x14D2, &mmBIF_SSA_DISP_LOWER[0], sizeof(mmBIF_SSA_DISP_LOWER)/sizeof(mmBIF_SSA_DISP_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_DISP_UPPER", REG_MMIO, 0x14D3, &mmBIF_SSA_DISP_UPPER[0], sizeof(mmBIF_SSA_DISP_UPPER)/sizeof(mmBIF_SSA_DISP_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_MC_LOWER", REG_MMIO, 0x14D4, &mmBIF_SSA_MC_LOWER[0], sizeof(mmBIF_SSA_MC_LOWER)/sizeof(mmBIF_SSA_MC_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_MC_UPPER", REG_MMIO, 0x14D5, &mmBIF_SSA_MC_UPPER[0], sizeof(mmBIF_SSA_MC_UPPER)/sizeof(mmBIF_SSA_MC_UPPER[0]), 0, 0 },
+	{ "mmBIF_BACO_DEBUG_LATCH", REG_MMIO, 0x14DC, &mmBIF_BACO_DEBUG_LATCH[0], sizeof(mmBIF_BACO_DEBUG_LATCH)/sizeof(mmBIF_BACO_DEBUG_LATCH[0]), 0, 0 },
+	{ "mmBIF_BACO_MSIC", REG_MMIO, 0x14DE, &mmBIF_BACO_MSIC[0], sizeof(mmBIF_BACO_MSIC)/sizeof(mmBIF_BACO_MSIC[0]), 0, 0 },
+	{ "mmBIF_BACO_DEBUG", REG_MMIO, 0x14DF, &mmBIF_BACO_DEBUG[0], sizeof(mmBIF_BACO_DEBUG)/sizeof(mmBIF_BACO_DEBUG[0]), 0, 0 },
+	{ "mmBACO_CNTL", REG_MMIO, 0x14E5, &mmBACO_CNTL[0], sizeof(mmBACO_CNTL)/sizeof(mmBACO_CNTL[0]), 0, 0 },
+	{ "mmBIF_DEVFUNCNUM_LIST1", REG_MMIO, 0x14E7, &mmBIF_DEVFUNCNUM_LIST1[0], sizeof(mmBIF_DEVFUNCNUM_LIST1)/sizeof(mmBIF_DEVFUNCNUM_LIST1[0]), 0, 0 },
+	{ "mmBIF_DEVFUNCNUM_LIST0", REG_MMIO, 0x14E8, &mmBIF_DEVFUNCNUM_LIST0[0], sizeof(mmBIF_DEVFUNCNUM_LIST0)/sizeof(mmBIF_DEVFUNCNUM_LIST0[0]), 0, 0 },
+	{ "mmNEW_REFCLKB_TIMER_1", REG_MMIO, 0x14E9, &mmNEW_REFCLKB_TIMER_1[0], sizeof(mmNEW_REFCLKB_TIMER_1)/sizeof(mmNEW_REFCLKB_TIMER_1[0]), 0, 0 },
+	{ "mmNEW_REFCLKB_TIMER", REG_MMIO, 0x14EA, &mmNEW_REFCLKB_TIMER[0], sizeof(mmNEW_REFCLKB_TIMER)/sizeof(mmNEW_REFCLKB_TIMER[0]), 0, 0 },
+	{ "mmPEER3_FB_OFFSET_LO", REG_MMIO, 0x14EC, &mmPEER3_FB_OFFSET_LO[0], sizeof(mmPEER3_FB_OFFSET_LO)/sizeof(mmPEER3_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER3_FB_OFFSET_HI", REG_MMIO, 0x14ED, &mmPEER3_FB_OFFSET_HI[0], sizeof(mmPEER3_FB_OFFSET_HI)/sizeof(mmPEER3_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER2_FB_OFFSET_LO", REG_MMIO, 0x14EE, &mmPEER2_FB_OFFSET_LO[0], sizeof(mmPEER2_FB_OFFSET_LO)/sizeof(mmPEER2_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER2_FB_OFFSET_HI", REG_MMIO, 0x14EF, &mmPEER2_FB_OFFSET_HI[0], sizeof(mmPEER2_FB_OFFSET_HI)/sizeof(mmPEER2_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER1_FB_OFFSET_LO", REG_MMIO, 0x14F0, &mmPEER1_FB_OFFSET_LO[0], sizeof(mmPEER1_FB_OFFSET_LO)/sizeof(mmPEER1_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER1_FB_OFFSET_HI", REG_MMIO, 0x14F1, &mmPEER1_FB_OFFSET_HI[0], sizeof(mmPEER1_FB_OFFSET_HI)/sizeof(mmPEER1_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER0_FB_OFFSET_LO", REG_MMIO, 0x14F2, &mmPEER0_FB_OFFSET_LO[0], sizeof(mmPEER0_FB_OFFSET_LO)/sizeof(mmPEER0_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER0_FB_OFFSET_HI", REG_MMIO, 0x14F3, &mmPEER0_FB_OFFSET_HI[0], sizeof(mmPEER0_FB_OFFSET_HI)/sizeof(mmPEER0_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmIMPCTL_RESET", REG_MMIO, 0x14F5, &mmIMPCTL_RESET[0], sizeof(mmIMPCTL_RESET)/sizeof(mmIMPCTL_RESET[0]), 0, 0 },
+	{ "mmBUS_CNTL", REG_MMIO, 0x1508, &mmBUS_CNTL[0], sizeof(mmBUS_CNTL)/sizeof(mmBUS_CNTL[0]), 0, 0 },
+	{ "mmCONFIG_CNTL", REG_MMIO, 0x1509, &mmCONFIG_CNTL[0], sizeof(mmCONFIG_CNTL)/sizeof(mmCONFIG_CNTL[0]), 0, 0 },
+	{ "mmCONFIG_MEMSIZE", REG_MMIO, 0x150A, &mmCONFIG_MEMSIZE[0], sizeof(mmCONFIG_MEMSIZE)/sizeof(mmCONFIG_MEMSIZE[0]), 0, 0 },
+	{ "mmCONFIG_F0_BASE", REG_MMIO, 0x150B, &mmCONFIG_F0_BASE[0], sizeof(mmCONFIG_F0_BASE)/sizeof(mmCONFIG_F0_BASE[0]), 0, 0 },
+	{ "mmCONFIG_APER_SIZE", REG_MMIO, 0x150C, &mmCONFIG_APER_SIZE[0], sizeof(mmCONFIG_APER_SIZE)/sizeof(mmCONFIG_APER_SIZE[0]), 0, 0 },
+	{ "mmCONFIG_REG_APER_SIZE", REG_MMIO, 0x150D, &mmCONFIG_REG_APER_SIZE[0], sizeof(mmCONFIG_REG_APER_SIZE)/sizeof(mmCONFIG_REG_APER_SIZE[0]), 0, 0 },
+	{ "mmBIF_SCRATCH0", REG_MMIO, 0x150E, &mmBIF_SCRATCH0[0], sizeof(mmBIF_SCRATCH0)/sizeof(mmBIF_SCRATCH0[0]), 0, 0 },
+	{ "mmBIF_SCRATCH1", REG_MMIO, 0x150F, &mmBIF_SCRATCH1[0], sizeof(mmBIF_SCRATCH1)/sizeof(mmBIF_SCRATCH1[0]), 0, 0 },
+	{ "mmBIF_RESET_EN", REG_MMIO, 0x1511, &mmBIF_RESET_EN[0], sizeof(mmBIF_RESET_EN)/sizeof(mmBIF_RESET_EN[0]), 0, 0 },
+	{ "mmMM_CFGREGS_CNTL", REG_MMIO, 0x1513, &mmMM_CFGREGS_CNTL[0], sizeof(mmMM_CFGREGS_CNTL)/sizeof(mmMM_CFGREGS_CNTL[0]), 0, 0 },
+	{ "mmHW_DEBUG", REG_MMIO, 0x1515, &mmHW_DEBUG[0], sizeof(mmHW_DEBUG)/sizeof(mmHW_DEBUG[0]), 0, 0 },
+	{ "mmMASTER_CREDIT_CNTL", REG_MMIO, 0x1516, &mmMASTER_CREDIT_CNTL[0], sizeof(mmMASTER_CREDIT_CNTL)/sizeof(mmMASTER_CREDIT_CNTL[0]), 0, 0 },
+	{ "mmSLAVE_REQ_CREDIT_CNTL", REG_MMIO, 0x1517, &mmSLAVE_REQ_CREDIT_CNTL[0], sizeof(mmSLAVE_REQ_CREDIT_CNTL)/sizeof(mmSLAVE_REQ_CREDIT_CNTL[0]), 0, 0 },
+	{ "mmINTERRUPT_CNTL", REG_MMIO, 0x151A, &mmINTERRUPT_CNTL[0], sizeof(mmINTERRUPT_CNTL)/sizeof(mmINTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmINTERRUPT_CNTL2", REG_MMIO, 0x151B, &mmINTERRUPT_CNTL2[0], sizeof(mmINTERRUPT_CNTL2)/sizeof(mmINTERRUPT_CNTL2[0]), 0, 0 },
+	{ "mmBIF_DEBUG_CNTL", REG_MMIO, 0x151C, &mmBIF_DEBUG_CNTL[0], sizeof(mmBIF_DEBUG_CNTL)/sizeof(mmBIF_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmBIF_DEBUG_MUX", REG_MMIO, 0x151D, &mmBIF_DEBUG_MUX[0], sizeof(mmBIF_DEBUG_MUX)/sizeof(mmBIF_DEBUG_MUX[0]), 0, 0 },
+	{ "mmBIF_DEBUG_OUT", REG_MMIO, 0x151E, &mmBIF_DEBUG_OUT[0], sizeof(mmBIF_DEBUG_OUT)/sizeof(mmBIF_DEBUG_OUT[0]), 0, 0 },
+	{ "mmBIF_CLK_PDWN_DELAY_TIMER", REG_MMIO, 0x151F, &mmBIF_CLK_PDWN_DELAY_TIMER[0], sizeof(mmBIF_CLK_PDWN_DELAY_TIMER)/sizeof(mmBIF_CLK_PDWN_DELAY_TIMER[0]), 0, 0 },
+	{ "mmHDP_MEM_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1520, &mmHDP_MEM_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmCLKREQB_PAD_CNTL", REG_MMIO, 0x1521, &mmCLKREQB_PAD_CNTL[0], sizeof(mmCLKREQB_PAD_CNTL)/sizeof(mmCLKREQB_PAD_CNTL[0]), 0, 0 },
+	{ "mmSMBDAT_PAD_CNTL", REG_MMIO, 0x1522, &mmSMBDAT_PAD_CNTL[0], sizeof(mmSMBDAT_PAD_CNTL)/sizeof(mmSMBDAT_PAD_CNTL[0]), 0, 0 },
+	{ "mmSMBCLK_PAD_CNTL", REG_MMIO, 0x1523, &mmSMBCLK_PAD_CNTL[0], sizeof(mmSMBCLK_PAD_CNTL)/sizeof(mmSMBCLK_PAD_CNTL[0]), 0, 0 },
+	{ "mmBIF_FB_EN", REG_MMIO, 0x1524, &mmBIF_FB_EN[0], sizeof(mmBIF_FB_EN)/sizeof(mmBIF_FB_EN[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_CNTL1", REG_MMIO, 0x1525, &mmBIF_BUSNUM_CNTL1[0], sizeof(mmBIF_BUSNUM_CNTL1)/sizeof(mmBIF_BUSNUM_CNTL1[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_LIST0", REG_MMIO, 0x1526, &mmBIF_BUSNUM_LIST0[0], sizeof(mmBIF_BUSNUM_LIST0)/sizeof(mmBIF_BUSNUM_LIST0[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_LIST1", REG_MMIO, 0x1527, &mmBIF_BUSNUM_LIST1[0], sizeof(mmBIF_BUSNUM_LIST1)/sizeof(mmBIF_BUSNUM_LIST1[0]), 0, 0 },
+	{ "mmHDP_REG_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1528, &mmHDP_REG_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmBIF_BUSY_DELAY_CNTR", REG_MMIO, 0x1529, &mmBIF_BUSY_DELAY_CNTR[0], sizeof(mmBIF_BUSY_DELAY_CNTR)/sizeof(mmBIF_BUSY_DELAY_CNTR[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_CNTL2", REG_MMIO, 0x152B, &mmBIF_BUSNUM_CNTL2[0], sizeof(mmBIF_BUSNUM_CNTL2)/sizeof(mmBIF_BUSNUM_CNTL2[0]), 0, 0 },
+	{ "mmBIF_PERFMON_CNTL", REG_MMIO, 0x152C, &mmBIF_PERFMON_CNTL[0], sizeof(mmBIF_PERFMON_CNTL)/sizeof(mmBIF_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmBIF_PERFCOUNTER0_RESULT", REG_MMIO, 0x152D, &mmBIF_PERFCOUNTER0_RESULT[0], sizeof(mmBIF_PERFCOUNTER0_RESULT)/sizeof(mmBIF_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmBIF_PERFCOUNTER1_RESULT", REG_MMIO, 0x152E, &mmBIF_PERFCOUNTER1_RESULT[0], sizeof(mmBIF_PERFCOUNTER1_RESULT)/sizeof(mmBIF_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmBIF_PIF_TXCLK_SWITCH_TIMER", REG_MMIO, 0x152F, &mmBIF_PIF_TXCLK_SWITCH_TIMER[0], sizeof(mmBIF_PIF_TXCLK_SWITCH_TIMER)/sizeof(mmBIF_PIF_TXCLK_SWITCH_TIMER[0]), 0, 0 },
+	{ "mmSLAVE_HANG_PROTECTION_CNTL", REG_MMIO, 0x1536, &mmSLAVE_HANG_PROTECTION_CNTL[0], sizeof(mmSLAVE_HANG_PROTECTION_CNTL)/sizeof(mmSLAVE_HANG_PROTECTION_CNTL[0]), 0, 0 },
+	{ "mmSLAVE_HANG_ERROR", REG_MMIO, 0x153B, &mmSLAVE_HANG_ERROR[0], sizeof(mmSLAVE_HANG_ERROR)/sizeof(mmSLAVE_HANG_ERROR[0]), 0, 0 },
+	{ "mmCAPTURE_HOST_BUSNUM", REG_MMIO, 0x153C, &mmCAPTURE_HOST_BUSNUM[0], sizeof(mmCAPTURE_HOST_BUSNUM)/sizeof(mmCAPTURE_HOST_BUSNUM[0]), 0, 0 },
+	{ "mmHOST_BUSNUM", REG_MMIO, 0x153D, &mmHOST_BUSNUM[0], sizeof(mmHOST_BUSNUM)/sizeof(mmHOST_BUSNUM[0]), 0, 0 },
+	{ "mmPEER_REG_RANGE0", REG_MMIO, 0x153E, &mmPEER_REG_RANGE0[0], sizeof(mmPEER_REG_RANGE0)/sizeof(mmPEER_REG_RANGE0[0]), 0, 0 },
+	{ "mmPEER_REG_RANGE1", REG_MMIO, 0x153F, &mmPEER_REG_RANGE1[0], sizeof(mmPEER_REG_RANGE1)/sizeof(mmPEER_REG_RANGE1[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG0", REG_SMC, 0x16000, &ixPB0_RX_GLB_CTRL_REG0[0], sizeof(ixPB0_RX_GLB_CTRL_REG0)/sizeof(ixPB0_RX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG1", REG_SMC, 0x16004, &ixPB0_RX_GLB_CTRL_REG1[0], sizeof(ixPB0_RX_GLB_CTRL_REG1)/sizeof(ixPB0_RX_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG2", REG_SMC, 0x16008, &ixPB0_RX_GLB_CTRL_REG2[0], sizeof(ixPB0_RX_GLB_CTRL_REG2)/sizeof(ixPB0_RX_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG3", REG_SMC, 0x1600C, &ixPB0_RX_GLB_CTRL_REG3[0], sizeof(ixPB0_RX_GLB_CTRL_REG3)/sizeof(ixPB0_RX_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG4", REG_SMC, 0x16010, &ixPB0_RX_GLB_CTRL_REG4[0], sizeof(ixPB0_RX_GLB_CTRL_REG4)/sizeof(ixPB0_RX_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG5", REG_SMC, 0x16014, &ixPB0_RX_GLB_CTRL_REG5[0], sizeof(ixPB0_RX_GLB_CTRL_REG5)/sizeof(ixPB0_RX_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG6", REG_SMC, 0x16018, &ixPB0_RX_GLB_CTRL_REG6[0], sizeof(ixPB0_RX_GLB_CTRL_REG6)/sizeof(ixPB0_RX_GLB_CTRL_REG6[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG7", REG_SMC, 0x1601C, &ixPB0_RX_GLB_CTRL_REG7[0], sizeof(ixPB0_RX_GLB_CTRL_REG7)/sizeof(ixPB0_RX_GLB_CTRL_REG7[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG8", REG_SMC, 0x16020, NULL, 0, 0, 0 },
+	{ "ixPB0_RX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x16028, &ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_OVRD_REG0", REG_SMC, 0x16030, &ixPB0_RX_GLB_OVRD_REG0[0], sizeof(ixPB0_RX_GLB_OVRD_REG0)/sizeof(ixPB0_RX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_OVRD_REG1", REG_SMC, 0x16034, &ixPB0_RX_GLB_OVRD_REG1[0], sizeof(ixPB0_RX_GLB_OVRD_REG1)/sizeof(ixPB0_RX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_RX_LANE0_CTRL_REG0", REG_SMC, 0x16440, &ixPB0_RX_LANE0_CTRL_REG0[0], sizeof(ixPB0_RX_LANE0_CTRL_REG0)/sizeof(ixPB0_RX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x16448, &ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE1_CTRL_REG0", REG_SMC, 0x16480, &ixPB0_RX_LANE1_CTRL_REG0[0], sizeof(ixPB0_RX_LANE1_CTRL_REG0)/sizeof(ixPB0_RX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x16488, &ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE2_CTRL_REG0", REG_SMC, 0x16500, &ixPB0_RX_LANE2_CTRL_REG0[0], sizeof(ixPB0_RX_LANE2_CTRL_REG0)/sizeof(ixPB0_RX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x16508, &ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE3_CTRL_REG0", REG_SMC, 0x16600, &ixPB0_RX_LANE3_CTRL_REG0[0], sizeof(ixPB0_RX_LANE3_CTRL_REG0)/sizeof(ixPB0_RX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x16608, &ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE4_CTRL_REG0", REG_SMC, 0x16800, &ixPB0_RX_LANE4_CTRL_REG0[0], sizeof(ixPB0_RX_LANE4_CTRL_REG0)/sizeof(ixPB0_RX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x16848, &ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE5_CTRL_REG0", REG_SMC, 0x16880, &ixPB0_RX_LANE5_CTRL_REG0[0], sizeof(ixPB0_RX_LANE5_CTRL_REG0)/sizeof(ixPB0_RX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x16888, &ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE6_CTRL_REG0", REG_SMC, 0x16900, &ixPB0_RX_LANE6_CTRL_REG0[0], sizeof(ixPB0_RX_LANE6_CTRL_REG0)/sizeof(ixPB0_RX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x16908, &ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE7_CTRL_REG0", REG_SMC, 0x16A00, &ixPB0_RX_LANE7_CTRL_REG0[0], sizeof(ixPB0_RX_LANE7_CTRL_REG0)/sizeof(ixPB0_RX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x16A08, &ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE8_CTRL_REG0", REG_SMC, 0x17440, &ixPB0_RX_LANE8_CTRL_REG0[0], sizeof(ixPB0_RX_LANE8_CTRL_REG0)/sizeof(ixPB0_RX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x17448, &ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE9_CTRL_REG0", REG_SMC, 0x17480, &ixPB0_RX_LANE9_CTRL_REG0[0], sizeof(ixPB0_RX_LANE9_CTRL_REG0)/sizeof(ixPB0_RX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x17488, &ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE10_CTRL_REG0", REG_SMC, 0x17500, &ixPB0_RX_LANE10_CTRL_REG0[0], sizeof(ixPB0_RX_LANE10_CTRL_REG0)/sizeof(ixPB0_RX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x17508, &ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE11_CTRL_REG0", REG_SMC, 0x17600, &ixPB0_RX_LANE11_CTRL_REG0[0], sizeof(ixPB0_RX_LANE11_CTRL_REG0)/sizeof(ixPB0_RX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x17608, &ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE12_CTRL_REG0", REG_SMC, 0x17840, &ixPB0_RX_LANE12_CTRL_REG0[0], sizeof(ixPB0_RX_LANE12_CTRL_REG0)/sizeof(ixPB0_RX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x17848, &ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE13_CTRL_REG0", REG_SMC, 0x17880, &ixPB0_RX_LANE13_CTRL_REG0[0], sizeof(ixPB0_RX_LANE13_CTRL_REG0)/sizeof(ixPB0_RX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x17888, &ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE14_CTRL_REG0", REG_SMC, 0x17900, &ixPB0_RX_LANE14_CTRL_REG0[0], sizeof(ixPB0_RX_LANE14_CTRL_REG0)/sizeof(ixPB0_RX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x17908, &ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE15_CTRL_REG0", REG_SMC, 0x17A00, &ixPB0_RX_LANE15_CTRL_REG0[0], sizeof(ixPB0_RX_LANE15_CTRL_REG0)/sizeof(ixPB0_RX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x17A08, &ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_CTRL_REG0", REG_SMC, 0x18000, &ixPB0_TX_GLB_CTRL_REG0[0], sizeof(ixPB0_TX_GLB_CTRL_REG0)/sizeof(ixPB0_TX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_LANE_SKEW_CTRL", REG_SMC, 0x18004, &ixPB0_TX_GLB_LANE_SKEW_CTRL[0], sizeof(ixPB0_TX_GLB_LANE_SKEW_CTRL)/sizeof(ixPB0_TX_GLB_LANE_SKEW_CTRL[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x18010, &ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0", REG_SMC, 0x18014, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1", REG_SMC, 0x18018, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2", REG_SMC, 0x1801C, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3", REG_SMC, 0x18020, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG0", REG_SMC, 0x18030, &ixPB0_TX_GLB_OVRD_REG0[0], sizeof(ixPB0_TX_GLB_OVRD_REG0)/sizeof(ixPB0_TX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG1", REG_SMC, 0x18034, &ixPB0_TX_GLB_OVRD_REG1[0], sizeof(ixPB0_TX_GLB_OVRD_REG1)/sizeof(ixPB0_TX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG2", REG_SMC, 0x18038, &ixPB0_TX_GLB_OVRD_REG2[0], sizeof(ixPB0_TX_GLB_OVRD_REG2)/sizeof(ixPB0_TX_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG3", REG_SMC, 0x1803C, &ixPB0_TX_GLB_OVRD_REG3[0], sizeof(ixPB0_TX_GLB_OVRD_REG3)/sizeof(ixPB0_TX_GLB_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG4", REG_SMC, 0x18040, &ixPB0_TX_GLB_OVRD_REG4[0], sizeof(ixPB0_TX_GLB_OVRD_REG4)/sizeof(ixPB0_TX_GLB_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_CTRL_REG0", REG_SMC, 0x18440, &ixPB0_TX_LANE0_CTRL_REG0[0], sizeof(ixPB0_TX_LANE0_CTRL_REG0)/sizeof(ixPB0_TX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_OVRD_REG0", REG_SMC, 0x18444, &ixPB0_TX_LANE0_OVRD_REG0[0], sizeof(ixPB0_TX_LANE0_OVRD_REG0)/sizeof(ixPB0_TX_LANE0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x18448, &ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_CTRL_REG0", REG_SMC, 0x18480, &ixPB0_TX_LANE1_CTRL_REG0[0], sizeof(ixPB0_TX_LANE1_CTRL_REG0)/sizeof(ixPB0_TX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_OVRD_REG0", REG_SMC, 0x18484, &ixPB0_TX_LANE1_OVRD_REG0[0], sizeof(ixPB0_TX_LANE1_OVRD_REG0)/sizeof(ixPB0_TX_LANE1_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x18488, &ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_CTRL_REG0", REG_SMC, 0x18500, &ixPB0_TX_LANE2_CTRL_REG0[0], sizeof(ixPB0_TX_LANE2_CTRL_REG0)/sizeof(ixPB0_TX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_OVRD_REG0", REG_SMC, 0x18504, &ixPB0_TX_LANE2_OVRD_REG0[0], sizeof(ixPB0_TX_LANE2_OVRD_REG0)/sizeof(ixPB0_TX_LANE2_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x18508, &ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_CTRL_REG0", REG_SMC, 0x18600, &ixPB0_TX_LANE3_CTRL_REG0[0], sizeof(ixPB0_TX_LANE3_CTRL_REG0)/sizeof(ixPB0_TX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_OVRD_REG0", REG_SMC, 0x18604, &ixPB0_TX_LANE3_OVRD_REG0[0], sizeof(ixPB0_TX_LANE3_OVRD_REG0)/sizeof(ixPB0_TX_LANE3_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x18608, &ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_CTRL_REG0", REG_SMC, 0x18840, &ixPB0_TX_LANE4_CTRL_REG0[0], sizeof(ixPB0_TX_LANE4_CTRL_REG0)/sizeof(ixPB0_TX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_OVRD_REG0", REG_SMC, 0x18844, &ixPB0_TX_LANE4_OVRD_REG0[0], sizeof(ixPB0_TX_LANE4_OVRD_REG0)/sizeof(ixPB0_TX_LANE4_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x18848, &ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_CTRL_REG0", REG_SMC, 0x18880, &ixPB0_TX_LANE5_CTRL_REG0[0], sizeof(ixPB0_TX_LANE5_CTRL_REG0)/sizeof(ixPB0_TX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_OVRD_REG0", REG_SMC, 0x18884, &ixPB0_TX_LANE5_OVRD_REG0[0], sizeof(ixPB0_TX_LANE5_OVRD_REG0)/sizeof(ixPB0_TX_LANE5_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x18888, &ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_CTRL_REG0", REG_SMC, 0x18900, &ixPB0_TX_LANE6_CTRL_REG0[0], sizeof(ixPB0_TX_LANE6_CTRL_REG0)/sizeof(ixPB0_TX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_OVRD_REG0", REG_SMC, 0x18904, &ixPB0_TX_LANE6_OVRD_REG0[0], sizeof(ixPB0_TX_LANE6_OVRD_REG0)/sizeof(ixPB0_TX_LANE6_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x18908, &ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_CTRL_REG0", REG_SMC, 0x18A00, &ixPB0_TX_LANE7_CTRL_REG0[0], sizeof(ixPB0_TX_LANE7_CTRL_REG0)/sizeof(ixPB0_TX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_OVRD_REG0", REG_SMC, 0x18A04, &ixPB0_TX_LANE7_OVRD_REG0[0], sizeof(ixPB0_TX_LANE7_OVRD_REG0)/sizeof(ixPB0_TX_LANE7_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x18A08, &ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_CTRL_REG0", REG_SMC, 0x19440, &ixPB0_TX_LANE8_CTRL_REG0[0], sizeof(ixPB0_TX_LANE8_CTRL_REG0)/sizeof(ixPB0_TX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_OVRD_REG0", REG_SMC, 0x19444, &ixPB0_TX_LANE8_OVRD_REG0[0], sizeof(ixPB0_TX_LANE8_OVRD_REG0)/sizeof(ixPB0_TX_LANE8_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x19448, &ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_CTRL_REG0", REG_SMC, 0x19480, &ixPB0_TX_LANE9_CTRL_REG0[0], sizeof(ixPB0_TX_LANE9_CTRL_REG0)/sizeof(ixPB0_TX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_OVRD_REG0", REG_SMC, 0x19484, &ixPB0_TX_LANE9_OVRD_REG0[0], sizeof(ixPB0_TX_LANE9_OVRD_REG0)/sizeof(ixPB0_TX_LANE9_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x19488, &ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_CTRL_REG0", REG_SMC, 0x19500, &ixPB0_TX_LANE10_CTRL_REG0[0], sizeof(ixPB0_TX_LANE10_CTRL_REG0)/sizeof(ixPB0_TX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_OVRD_REG0", REG_SMC, 0x19504, &ixPB0_TX_LANE10_OVRD_REG0[0], sizeof(ixPB0_TX_LANE10_OVRD_REG0)/sizeof(ixPB0_TX_LANE10_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x19508, &ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_CTRL_REG0", REG_SMC, 0x19600, &ixPB0_TX_LANE11_CTRL_REG0[0], sizeof(ixPB0_TX_LANE11_CTRL_REG0)/sizeof(ixPB0_TX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_OVRD_REG0", REG_SMC, 0x19604, &ixPB0_TX_LANE11_OVRD_REG0[0], sizeof(ixPB0_TX_LANE11_OVRD_REG0)/sizeof(ixPB0_TX_LANE11_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x19608, &ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_CTRL_REG0", REG_SMC, 0x19840, &ixPB0_TX_LANE12_CTRL_REG0[0], sizeof(ixPB0_TX_LANE12_CTRL_REG0)/sizeof(ixPB0_TX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_OVRD_REG0", REG_SMC, 0x19844, &ixPB0_TX_LANE12_OVRD_REG0[0], sizeof(ixPB0_TX_LANE12_OVRD_REG0)/sizeof(ixPB0_TX_LANE12_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x19848, &ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_CTRL_REG0", REG_SMC, 0x19880, &ixPB0_TX_LANE13_CTRL_REG0[0], sizeof(ixPB0_TX_LANE13_CTRL_REG0)/sizeof(ixPB0_TX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_OVRD_REG0", REG_SMC, 0x19884, &ixPB0_TX_LANE13_OVRD_REG0[0], sizeof(ixPB0_TX_LANE13_OVRD_REG0)/sizeof(ixPB0_TX_LANE13_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x19888, &ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_CTRL_REG0", REG_SMC, 0x19900, &ixPB0_TX_LANE14_CTRL_REG0[0], sizeof(ixPB0_TX_LANE14_CTRL_REG0)/sizeof(ixPB0_TX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_OVRD_REG0", REG_SMC, 0x19904, &ixPB0_TX_LANE14_OVRD_REG0[0], sizeof(ixPB0_TX_LANE14_OVRD_REG0)/sizeof(ixPB0_TX_LANE14_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x19908, &ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_CTRL_REG0", REG_SMC, 0x19A00, &ixPB0_TX_LANE15_CTRL_REG0[0], sizeof(ixPB0_TX_LANE15_CTRL_REG0)/sizeof(ixPB0_TX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_OVRD_REG0", REG_SMC, 0x19A04, &ixPB0_TX_LANE15_OVRD_REG0[0], sizeof(ixPB0_TX_LANE15_OVRD_REG0)/sizeof(ixPB0_TX_LANE15_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x19A08, &ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
diff --git a/src/lib/ip/bif41.c b/src/lib/ip/bif41.c
new file mode 100644
index 0000000..92509e2
--- /dev/null
+++ b/src/lib/ip/bif41.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "bif41_bits.i"
+
+static const struct umr_reg bif41_registers[] = {
+#include "bif41_regs.i"
+};
+
+struct umr_ip_block *umr_create_bif41(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "bif41";
+	ip->no_regs = sizeof(bif41_registers)/sizeof(bif41_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(bif41_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, bif41_registers, sizeof(bif41_registers));
+	return ip;
+}
diff --git a/src/lib/ip/bif41_bits.i b/src/lib/ip/bif41_bits.i
new file mode 100644
index 0000000..6846510
--- /dev/null
+++ b/src/lib/ip/bif41_bits.i
@@ -0,0 +1,6791 @@
+static struct umr_bitfield mmVENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_INDEX[] = {
+	 { "MM_OFFSET", 0, 30, &umr_bitfield_default },
+	 { "MM_APER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_DATA[] = {
+	 { "MM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTATUS[] = {
+	 { "INT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "CAP_LIST", 4, 4, &umr_bitfield_default },
+	 { "PCI_66_EN", 5, 5, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 7, 7, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 8, 8, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 9, 10, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 11, 11, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 12, 12, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 13, 13, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 14, 14, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_RESERVED[] = {
+	 { "PCIEP_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_SCRATCH[] = {
+	 { "PCIEP_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_PORT_CNTL[] = {
+	 { "SLV_PORT_REQ_EN", 0, 0, &umr_bitfield_default },
+	 { "CI_SNOOP_OVERRIDE", 1, 1, &umr_bitfield_default },
+	 { "HOTPLUG_MSG_EN", 2, 2, &umr_bitfield_default },
+	 { "NATIVE_PME_EN", 3, 3, &umr_bitfield_default },
+	 { "PWR_FAULT_EN", 4, 4, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 5, 5, &umr_bitfield_default },
+	 { "SEQNUM_DEBUG_MODE", 6, 6, &umr_bitfield_default },
+	 { "CI_SLV_CPL_STATIC_ALLOC_LIMIT_S", 8, 14, &umr_bitfield_default },
+	 { "CI_MAX_CPL_PAYLOAD_SIZE_MODE", 16, 17, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_CPL_PAYLOAD_SIZE", 18, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CNTL[] = {
+	 { "TX_SNR_OVERRIDE", 10, 11, &umr_bitfield_default },
+	 { "TX_RO_OVERRIDE", 12, 13, &umr_bitfield_default },
+	 { "TX_PACK_PACKET_DIS", 14, 14, &umr_bitfield_default },
+	 { "TX_FLUSH_TLP_DIS", 15, 15, &umr_bitfield_default },
+	 { "TX_CPL_PASS_P", 20, 20, &umr_bitfield_default },
+	 { "TX_NP_PASS_P", 21, 21, &umr_bitfield_default },
+	 { "TX_CLEAR_EXTRA_PM_REQS", 22, 22, &umr_bitfield_default },
+	 { "TX_FC_UPDATE_TIMEOUT_DIS", 23, 23, &umr_bitfield_default },
+	 { "TX_F0_TPH_DIS", 24, 24, &umr_bitfield_default },
+	 { "TX_F1_TPH_DIS", 25, 25, &umr_bitfield_default },
+	 { "TX_F2_TPH_DIS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REQUESTER_ID[] = {
+	 { "TX_REQUESTER_ID_FUNCTION", 0, 2, &umr_bitfield_default },
+	 { "TX_REQUESTER_ID_DEVICE", 3, 7, &umr_bitfield_default },
+	 { "TX_REQUESTER_ID_BUS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_VENDOR_SPECIFIC[] = {
+	 { "TX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REQUEST_NUM_CNTL[] = {
+	 { "TX_NUM_OUTSTANDING_NP", 24, 29, &umr_bitfield_default },
+	 { "TX_NUM_OUTSTANDING_NP_VC1_EN", 30, 30, &umr_bitfield_default },
+	 { "TX_NUM_OUTSTANDING_NP_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_SEQ[] = {
+	 { "TX_NEXT_TRANSMIT_SEQ", 0, 11, &umr_bitfield_default },
+	 { "TX_ACKD_SEQ", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REPLAY[] = {
+	 { "TX_REPLAY_NUM", 0, 2, &umr_bitfield_default },
+	 { "TX_REPLAY_TIMER_OVERWRITE", 15, 15, &umr_bitfield_default },
+	 { "TX_REPLAY_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_ACK_LATENCY_LIMIT[] = {
+	 { "TX_ACK_LATENCY_LIMIT", 0, 11, &umr_bitfield_default },
+	 { "TX_ACK_LATENCY_LIMIT_OVERWRITE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_P[] = {
+	 { "TX_CREDITS_ADVT_PD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_NP[] = {
+	 { "TX_CREDITS_ADVT_NPD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_CPL[] = {
+	 { "TX_CREDITS_ADVT_CPLD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_P[] = {
+	 { "TX_CREDITS_INIT_PD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_NP[] = {
+	 { "TX_CREDITS_INIT_NPD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_CPL[] = {
+	 { "TX_CREDITS_INIT_CPLD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_STATUS[] = {
+	 { "TX_CREDITS_ERR_PD", 0, 0, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_PH", 1, 1, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_NPD", 2, 2, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_NPH", 3, 3, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_CPLD", 4, 4, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_CPLH", 5, 5, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_PD", 16, 16, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_PH", 17, 17, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_NPD", 18, 18, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_NPH", 19, 19, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_CPLD", 20, 20, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_CPLH", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_FCU_THRESHOLD[] = {
+	 { "TX_FCU_THRESHOLD_P_VC0", 0, 2, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_NP_VC0", 4, 6, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_CPL_VC0", 8, 10, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_P_VC1", 16, 18, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_NP_VC1", 20, 22, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_CPL_VC1", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_PORT_LANE_STATUS[] = {
+	 { "PORT_LANE_REVERSAL", 0, 0, &umr_bitfield_default },
+	 { "PHY_LINK_WIDTH", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_P[] = {
+	 { "PD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "PH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_NP[] = {
+	 { "NPD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "NPH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_CPL[] = {
+	 { "CPLD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "CPLH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_ERR_CNTL[] = {
+	 { "ERR_REPORTING_DIS", 0, 0, &umr_bitfield_default },
+	 { "STRAP_FIRST_RCVD_ERR_LOG", 1, 1, &umr_bitfield_default },
+	 { "RX_DROP_ECRC_FAILURES", 2, 2, &umr_bitfield_default },
+	 { "TX_GENERATE_LCRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_GENERATE_LCRC_ERR", 5, 5, &umr_bitfield_default },
+	 { "TX_GENERATE_ECRC_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_GENERATE_ECRC_ERR", 7, 7, &umr_bitfield_default },
+	 { "AER_HDR_LOG_TIMEOUT", 8, 10, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F0_TIMER_EXPIRED", 11, 11, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F1_TIMER_EXPIRED", 12, 12, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F2_TIMER_EXPIRED", 13, 13, &umr_bitfield_default },
+	 { "CI_P_SLV_BUF_RD_HALT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CI_NP_SLV_BUF_RD_HALT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "CI_SLV_BUF_HALT_RESET", 16, 16, &umr_bitfield_default },
+	 { "SEND_ERR_MSG_IMMEDIATELY", 17, 17, &umr_bitfield_default },
+	 { "STRAP_POISONED_ADVISORY_NONFATAL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL[] = {
+	 { "RX_IGNORE_IO_ERR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_BE_ERR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_MSG_ERR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_CRC_ERR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_CPL_ERR", 5, 5, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_IGNORE_LEN_MISMATCH_ERR", 7, 7, &umr_bitfield_default },
+	 { "RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default },
+	 { "RX_IGNORE_TC_ERR", 9, 9, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_UR", 10, 10, &umr_bitfield_default },
+	 { "RX_IGNORE_IO_UR", 11, 11, &umr_bitfield_default },
+	 { "RX_IGNORE_AT_ERR", 12, 12, &umr_bitfield_default },
+	 { "RX_NAK_IF_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RX_GEN_ONE_NAK", 14, 14, &umr_bitfield_default },
+	 { "RX_FC_INIT_FROM_REG", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT", 16, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_PCIE_CPL_TIMEOUT_DIS", 20, 20, &umr_bitfield_default },
+	 { "RX_IGNORE_SHORTPREFIX_ERR", 21, 21, &umr_bitfield_default },
+	 { "RX_IGNORE_MAXPREFIX_ERR", 22, 22, &umr_bitfield_default },
+	 { "RX_IGNORE_CPLPREFIX_ERR", 23, 23, &umr_bitfield_default },
+	 { "RX_IGNORE_INVALIDPASID_ERR", 24, 24, &umr_bitfield_default },
+	 { "RX_IGNORE_NOT_PASID_UR", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_EXPECTED_SEQNUM[] = {
+	 { "RX_EXPECTED_SEQNUM", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_VENDOR_SPECIFIC[] = {
+	 { "RX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+	 { "RX_VENDOR_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL3[] = {
+	 { "RX_IGNORE_RC_TRANSMRDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_TRANSMWRPASID_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_PRGRESPMSG_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVCPLPASID_UR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_P[] = {
+	 { "RX_CREDITS_ALLOCATED_PD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_NP[] = {
+	 { "RX_CREDITS_ALLOCATED_NPD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_CPL[] = {
+	 { "RX_CREDITS_ALLOCATED_CPLD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL[] = {
+	 { "LC_DONT_ENTER_L23_IN_D0", 1, 1, &umr_bitfield_default },
+	 { "LC_RESET_L_IDLE_COUNT_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_RESET_LINK", 3, 3, &umr_bitfield_default },
+	 { "LC_16X_CLEAR_TX_PIPE", 4, 7, &umr_bitfield_default },
+	 { "LC_L0S_INACTIVITY", 8, 11, &umr_bitfield_default },
+	 { "LC_L1_INACTIVITY", 12, 15, &umr_bitfield_default },
+	 { "LC_PMI_TO_L1_DIS", 16, 16, &umr_bitfield_default },
+	 { "LC_INC_N_FTS_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_IDLE_IN_L1L23", 18, 19, &umr_bitfield_default },
+	 { "LC_FACTOR_IN_EXT_SYNC", 20, 20, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_PM_ACK_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_WAKE_FROM_L23", 22, 22, &umr_bitfield_default },
+	 { "LC_L1_IMMEDIATE_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_ASPM_TO_L1_DIS", 24, 24, &umr_bitfield_default },
+	 { "LC_DELAY_COUNT", 25, 26, &umr_bitfield_default },
+	 { "LC_DELAY_L0S_EXIT", 27, 27, &umr_bitfield_default },
+	 { "LC_DELAY_L1_EXIT", 28, 28, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_EL_IDLE", 29, 29, &umr_bitfield_default },
+	 { "LC_ESCAPE_L1L23_EN", 30, 30, &umr_bitfield_default },
+	 { "LC_GATE_RCVR_IDLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_TRAINING_CNTL[] = {
+	 { "LC_TRAINING_CNTL", 0, 3, &umr_bitfield_default },
+	 { "LC_COMPLIANCE_RECEIVE", 4, 4, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_MORE_NON_MATCHING_TS1", 5, 5, &umr_bitfield_default },
+	 { "LC_L0S_L1_TRAINING_CNTL_EN", 6, 6, &umr_bitfield_default },
+	 { "LC_L1_LONG_WAKE_FIX_EN", 7, 7, &umr_bitfield_default },
+	 { "LC_POWER_STATE", 8, 10, &umr_bitfield_default },
+	 { "LC_DONT_GO_TO_L0S_IF_L1_ARMED", 11, 11, &umr_bitfield_default },
+	 { "LC_INIT_SPD_CHG_WITH_CSR_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_DISABLE_TRAINING_BIT_ARCH", 13, 13, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_SKP", 16, 16, &umr_bitfield_default },
+	 { "LC_AUTONOMOUS_CHANGE_OFF", 17, 17, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAP_OFF", 18, 18, &umr_bitfield_default },
+	 { "LC_HW_LINK_DIS_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_LINK_DIS_BY_HW", 20, 20, &umr_bitfield_default },
+	 { "LC_STATIC_TX_PIPE_COUNT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_ASPM_L1_NAK_TIMER_SEL", 22, 23, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_R_SPEED", 24, 24, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_TEST", 25, 25, &umr_bitfield_default },
+	 { "LC_RESET_ASPM_L1_NAK_TIMER", 26, 26, &umr_bitfield_default },
+	 { "LC_SHORT_RCFG_TIMEOUT", 27, 27, &umr_bitfield_default },
+	 { "LC_ALLOW_TX_L1_CONTROL", 28, 28, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_FOM_VALID_AFTER_TRACK", 29, 29, &umr_bitfield_default },
+	 { "LC_EXTEND_EQ_REQ_TIME", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_LINK_WIDTH_CNTL[] = {
+	 { "LC_LINK_WIDTH", 0, 2, &umr_bitfield_default },
+	 { "LC_LINK_WIDTH_RD", 4, 6, &umr_bitfield_default },
+	 { "LC_RECONFIG_ARC_MISSING_ESCAPE", 7, 7, &umr_bitfield_default },
+	 { "LC_RECONFIG_NOW", 8, 8, &umr_bitfield_default },
+	 { "LC_RENEGOTIATION_SUPPORT", 9, 9, &umr_bitfield_default },
+	 { "LC_RENEGOTIATE_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_SHORT_RECONFIG_EN", 11, 11, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_SUPPORT", 12, 12, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_DIS", 13, 13, &umr_bitfield_default },
+	 { "LC_UPCFG_WAIT_FOR_RCVR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LC_UPCFG_TIMER_SEL", 15, 15, &umr_bitfield_default },
+	 { "LC_DEASSERT_TX_PDNB", 16, 16, &umr_bitfield_default },
+	 { "LC_L1_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_DYNLINK_MST_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_DUAL_END_RECONFIG_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LC_DYN_LANES_PWR_STATE", 21, 22, &umr_bitfield_default },
+	 { "LC_EQ_REVERSAL_LOGIC_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_N_FTS_CNTL[] = {
+	 { "LC_XMIT_N_FTS", 0, 7, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_OVERRIDE_EN", 8, 8, &umr_bitfield_default },
+	 { "LC_XMIT_FTS_BEFORE_RECOVERY", 9, 9, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_LIMIT", 16, 23, &umr_bitfield_default },
+	 { "LC_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_SPEED_CNTL[] = {
+	 { "LC_GEN2_EN_STRAP", 0, 0, &umr_bitfield_default },
+	 { "LC_GEN3_EN_STRAP", 1, 1, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE", 3, 4, &umr_bitfield_default },
+	 { "LC_FORCE_EN_SW_SPEED_CHANGE", 5, 5, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_SW_SPEED_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_FORCE_EN_HW_SPEED_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_HW_SPEED_CHANGE", 8, 8, &umr_bitfield_default },
+	 { "LC_INITIATE_LINK_SPEED_CHANGE", 9, 9, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPTS_ALLOWED", 10, 11, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPT_FAILED", 12, 12, &umr_bitfield_default },
+	 { "LC_CURRENT_DATA_RATE", 13, 14, &umr_bitfield_default },
+	 { "LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS", 15, 15, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_SPD_CHANGE_CNT", 16, 16, &umr_bitfield_default },
+	 { "LC_1_OR_MORE_TS2_SPEED_ARC_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN2", 18, 18, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN2", 19, 19, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN3", 20, 20, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN3", 21, 21, &umr_bitfield_default },
+	 { "LC_AUTO_RECOVERY_DIS", 22, 22, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_STATUS", 23, 23, &umr_bitfield_default },
+	 { "LC_DATA_RATE_ADVERTISED", 24, 25, &umr_bitfield_default },
+	 { "LC_CHECK_DATA_RATE", 26, 26, &umr_bitfield_default },
+	 { "LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN", 27, 27, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L0s_EN", 28, 28, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L1_EN", 29, 29, &umr_bitfield_default },
+	 { "LC_DONT_CHECK_EQTS_IN_RCFG", 30, 30, &umr_bitfield_default },
+	 { "LC_DELAY_COEFF_UPDATE_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE0[] = {
+	 { "LC_CURRENT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE1", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE2", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE1[] = {
+	 { "LC_PREV_STATE4", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE5", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE6", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE7", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE2[] = {
+	 { "LC_PREV_STATE8", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE9", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE10", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE11", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE3[] = {
+	 { "LC_PREV_STATE12", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE13", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE14", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE15", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE4[] = {
+	 { "LC_PREV_STATE16", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE17", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE18", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE19", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE5[] = {
+	 { "LC_PREV_STATE20", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE21", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE22", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE23", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL2[] = {
+	 { "LC_TIMED_OUT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_STATE_TIMED_OUT", 6, 6, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_BW_REDUCTION", 7, 7, &umr_bitfield_default },
+	 { "LC_MORE_TS2_EN", 8, 8, &umr_bitfield_default },
+	 { "LC_X12_NEGOTIATION_DIS", 9, 9, &umr_bitfield_default },
+	 { "LC_LINK_UP_REVERSAL_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_ILLEGAL_STATE", 11, 11, &umr_bitfield_default },
+	 { "LC_ILLEGAL_STATE_RESTART_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_OTHER_LANES_MODE", 13, 13, &umr_bitfield_default },
+	 { "LC_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "LC_DISABLE_INFERRED_ELEC_IDLE_DET", 16, 16, &umr_bitfield_default },
+	 { "LC_ALLOW_PDWN_IN_L1", 17, 17, &umr_bitfield_default },
+	 { "LC_ALLOW_PDWN_IN_L23", 18, 18, &umr_bitfield_default },
+	 { "LC_DEASSERT_RX_EN_IN_L0S", 19, 19, &umr_bitfield_default },
+	 { "LC_BLOCK_EL_IDLE_IN_L0", 20, 20, &umr_bitfield_default },
+	 { "LC_RCV_L0_TO_RCV_L0S_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_ASSERT_INACTIVE_DURING_HOLD", 22, 22, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_LANES_IN_LW_NEG", 23, 24, &umr_bitfield_default },
+	 { "LC_PWR_DOWN_NEG_OFF_LANES", 25, 25, &umr_bitfield_default },
+	 { "LC_DISABLE_LOST_SYM_LOCK_ARCS", 26, 26, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DIS", 27, 27, &umr_bitfield_default },
+	 { "LC_PMI_L1_WAIT_FOR_SLV_IDLE", 28, 28, &umr_bitfield_default },
+	 { "LC_TEST_TIMER_SEL", 29, 30, &umr_bitfield_default },
+	 { "LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_BW_CHANGE_CNTL[] = {
+	 { "LC_BW_CHANGE_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "LC_HW_INIT_SPEED_CHANGE", 1, 1, &umr_bitfield_default },
+	 { "LC_SW_INIT_SPEED_CHANGE", 2, 2, &umr_bitfield_default },
+	 { "LC_OTHER_INIT_SPEED_CHANGE", 3, 3, &umr_bitfield_default },
+	 { "LC_RELIABILITY_SPEED_CHANGE", 4, 4, &umr_bitfield_default },
+	 { "LC_FAILED_SPEED_NEG", 5, 5, &umr_bitfield_default },
+	 { "LC_LONG_LW_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_SHORT_LW_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_OTHER", 8, 8, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_FAILED", 9, 9, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DETECT_MODE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CDR_CNTL[] = {
+	 { "LC_CDR_TEST_OFF", 0, 11, &umr_bitfield_default },
+	 { "LC_CDR_TEST_SETS", 12, 23, &umr_bitfield_default },
+	 { "LC_CDR_SET_TYPE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_LANE_CNTL[] = {
+	 { "LC_CORRUPTED_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_LANE_DIS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL3[] = {
+	 { "LC_SELECT_DEEMPHASIS", 0, 0, &umr_bitfield_default },
+	 { "LC_SELECT_DEEMPHASIS_CNTL", 1, 2, &umr_bitfield_default },
+	 { "LC_RCVD_DEEMPHASIS", 3, 3, &umr_bitfield_default },
+	 { "LC_COMP_TO_DETECT", 4, 4, &umr_bitfield_default },
+	 { "LC_RESET_TSX_CNT_IN_RLOCK_EN", 5, 5, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED", 6, 7, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED", 8, 8, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT", 9, 9, &umr_bitfield_default },
+	 { "LC_ENHANCED_HOT_PLUG_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_RCVR_DET_EN_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "LC_EHP_RX_PHY_CMD", 12, 13, &umr_bitfield_default },
+	 { "LC_EHP_TX_PHY_CMD", 14, 15, &umr_bitfield_default },
+	 { "LC_CHIP_BIF_USB_IDLE_EN", 16, 16, &umr_bitfield_default },
+	 { "LC_L1_BLOCK_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL", 19, 20, &umr_bitfield_default },
+	 { "LC_FAST_L1_ENTRY_EXIT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_RXPHYCMD_INACTIVE_EN_MODE", 22, 22, &umr_bitfield_default },
+	 { "LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_HW_VOLTAGE_IF_CONTROL", 24, 25, &umr_bitfield_default },
+	 { "LC_VOLTAGE_TIMER_SEL", 26, 29, &umr_bitfield_default },
+	 { "LC_GO_TO_RECOVERY", 30, 30, &umr_bitfield_default },
+	 { "LC_N_EIE_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL4[] = {
+	 { "LC_TX_ENABLE_BEHAVIOUR", 0, 1, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ", 4, 4, &umr_bitfield_default },
+	 { "LC_REDO_EQ", 5, 5, &umr_bitfield_default },
+	 { "LC_EXTEND_EIEOS", 6, 6, &umr_bitfield_default },
+	 { "LC_IGNORE_PARITY", 7, 7, &umr_bitfield_default },
+	 { "LC_EQ_SEARCH_MODE", 8, 9, &umr_bitfield_default },
+	 { "LC_DSC_CHECK_COEFFS_IN_RLOCK", 10, 10, &umr_bitfield_default },
+	 { "LC_USC_EQ_NOT_REQD", 11, 11, &umr_bitfield_default },
+	 { "LC_USC_GO_TO_EQ", 12, 12, &umr_bitfield_default },
+	 { "LC_SET_QUIESCE", 13, 13, &umr_bitfield_default },
+	 { "LC_QUIESCE_RCVD", 14, 14, &umr_bitfield_default },
+	 { "LC_UNEXPECTED_COEFFS_RCVD", 15, 15, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ_REQ_PHASE", 16, 16, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_IN_EQ_REQ_PHASE", 17, 17, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_VALUE", 18, 21, &umr_bitfield_default },
+	 { "LC_USC_DELAY_DLLPS", 22, 22, &umr_bitfield_default },
+	 { "LC_PCIE_TX_FULL_SWING", 23, 23, &umr_bitfield_default },
+	 { "LC_EQ_WAIT_FOR_EVAL_DONE", 24, 24, &umr_bitfield_default },
+	 { "LC_8GT_SKIP_ORDER_EN", 25, 25, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_MORE_TS_IN_RLOCK", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL5[] = {
+	 { "LC_EQ_FS_0", 0, 5, &umr_bitfield_default },
+	 { "LC_EQ_FS_8", 6, 11, &umr_bitfield_default },
+	 { "LC_EQ_LF_0", 12, 17, &umr_bitfield_default },
+	 { "LC_EQ_LF_8", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_FORCE_COEFF[] = {
+	 { "LC_FORCE_COEFF", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR", 1, 6, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR", 13, 18, &umr_bitfield_default },
+	 { "LC_3X3_COEFF_SEARCH_EN", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_BEST_EQ_SETTINGS[] = {
+	 { "LC_BEST_PRESET", 0, 3, &umr_bitfield_default },
+	 { "LC_BEST_PRECURSOR", 4, 9, &umr_bitfield_default },
+	 { "LC_BEST_CURSOR", 10, 15, &umr_bitfield_default },
+	 { "LC_BEST_POSTCURSOR", 16, 21, &umr_bitfield_default },
+	 { "LC_BEST_FOM", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_FORCE_EQ_REQ_COEFF[] = {
+	 { "LC_FORCE_COEFF_IN_EQ_REQ_PHASE", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR_REQ", 1, 6, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR_REQ", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR_REQ", 13, 18, &umr_bitfield_default },
+	 { "LC_FS_OTHER_END", 19, 24, &umr_bitfield_default },
+	 { "LC_LF_OTHER_END", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_STRAP_LC[] = {
+	 { "STRAP_FTS_yTSx_COUNT", 0, 1, &umr_bitfield_default },
+	 { "STRAP_LONG_yTSx_COUNT", 2, 3, &umr_bitfield_default },
+	 { "STRAP_MED_yTSx_COUNT", 4, 5, &umr_bitfield_default },
+	 { "STRAP_SHORT_yTSx_COUNT", 6, 7, &umr_bitfield_default },
+	 { "STRAP_SKIP_INTERVAL", 8, 10, &umr_bitfield_default },
+	 { "STRAP_BYPASS_RCVR_DET", 11, 11, &umr_bitfield_default },
+	 { "STRAP_COMPLIANCE_DIS", 12, 12, &umr_bitfield_default },
+	 { "STRAP_FORCE_COMPLIANCE", 13, 13, &umr_bitfield_default },
+	 { "STRAP_REVERSE_LC_LANES", 14, 14, &umr_bitfield_default },
+	 { "STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_LANE_NEGOTIATION", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_STRAP_MISC[] = {
+	 { "STRAP_REVERSE_LANES", 0, 0, &umr_bitfield_default },
+	 { "STRAP_E2E_PREFIX_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_EXTENDED_FMT_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "STRAP_OBFF_SUPPORTED", 3, 4, &umr_bitfield_default },
+	 { "STRAP_LTR_SUPPORTED", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_BCH_ECC_CNTL[] = {
+	 { "STRAP_BCH_ECC_EN", 0, 0, &umr_bitfield_default },
+	 { "BCH_ECC_ERROR_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "BCH_ECC_ERROR_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SCRATCH[] = {
+	 { "PIF_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_HW_DEBUG[] = {
+	 { "PB0_PIF_HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "PB0_PIF_HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "PB0_PIF_HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "PB0_PIF_HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "PB0_PIF_HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "PB0_PIF_HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "PB0_PIF_HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "PB0_PIF_HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "PB0_PIF_HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "PB0_PIF_HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "PB0_PIF_HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "PB0_PIF_HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "PB0_PIF_HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "PB0_PIF_HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "PB0_PIF_HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "PB0_PIF_HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PRG6[] = {
+	 { "PRG_SPEEDCHANGE_STEP4_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PRG7[] = {
+	 { "PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_CNTL[] = {
+	 { "SERIAL_CFG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_0", 1, 1, &umr_bitfield_default },
+	 { "PHY_CR_EN_MODE", 2, 2, &umr_bitfield_default },
+	 { "PHYCMD_CR_EN_MODE", 3, 3, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_MODE", 4, 4, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_1", 5, 5, &umr_bitfield_default },
+	 { "RXDETECT_FIFO_RESET_MODE", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_TX_PWR_MODE", 7, 7, &umr_bitfield_default },
+	 { "DIVINIT_MODE", 8, 8, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_2", 9, 9, &umr_bitfield_default },
+	 { "PLL_BINDING_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "SC_CALIB_DONE_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DIVINIT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_3", 13, 13, &umr_bitfield_default },
+	 { "PLL0_IN_GEN3_MODE", 14, 14, &umr_bitfield_default },
+	 { "FORCE_TxFreqEquZeroinDTM_EN", 15, 15, &umr_bitfield_default },
+	 { "TXGND_TIME", 16, 16, &umr_bitfield_default },
+	 { "LS2_EXIT_TIME", 17, 19, &umr_bitfield_default },
+	 { "EI_CYCLE_OFF_TIME", 20, 22, &umr_bitfield_default },
+	 { "EXIT_L0S_INIT_DIS", 23, 23, &umr_bitfield_default },
+	 { "RXEN_GATER", 24, 27, &umr_bitfield_default },
+	 { "EXTEND_WAIT_FOR_RAMPUP", 28, 28, &umr_bitfield_default },
+	 { "IGNORE_TxDataValid_EP_DIS", 29, 29, &umr_bitfield_default },
+	 { "PHYRESPONSEMODE_ON_RXDET_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PAIRING[] = {
+	 { "X2_LANE_1_0", 0, 0, &umr_bitfield_default },
+	 { "X2_LANE_3_2", 1, 1, &umr_bitfield_default },
+	 { "X2_LANE_5_4", 2, 2, &umr_bitfield_default },
+	 { "X2_LANE_7_6", 3, 3, &umr_bitfield_default },
+	 { "X2_LANE_9_8", 4, 4, &umr_bitfield_default },
+	 { "X2_LANE_11_10", 5, 5, &umr_bitfield_default },
+	 { "X2_LANE_13_12", 6, 6, &umr_bitfield_default },
+	 { "X2_LANE_15_14", 7, 7, &umr_bitfield_default },
+	 { "X4_LANE_3_0", 8, 8, &umr_bitfield_default },
+	 { "X4_LANE_7_4", 9, 9, &umr_bitfield_default },
+	 { "X4_LANE_11_8", 10, 10, &umr_bitfield_default },
+	 { "X4_LANE_15_12", 11, 11, &umr_bitfield_default },
+	 { "X8_LANE_7_0", 16, 16, &umr_bitfield_default },
+	 { "X8_LANE_15_8", 17, 17, &umr_bitfield_default },
+	 { "X16_LANE_15_0", 20, 20, &umr_bitfield_default },
+	 { "MULTI_PIF", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PWRDOWN_0[] = {
+	 { "TX_POWER_STATE_IN_TXS2_0", 0, 2, &umr_bitfield_default },
+	 { "FORCE_RXEN_IN_L0s_0", 3, 3, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_0", 4, 6, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_0", 7, 9, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_0", 10, 12, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_0", 16, 16, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_0", 24, 26, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_0", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PWRDOWN_1[] = {
+	 { "TX_POWER_STATE_IN_TXS2_1", 0, 2, &umr_bitfield_default },
+	 { "FORCE_RXEN_IN_L0s_1", 3, 3, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_1", 4, 6, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_1", 7, 9, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_1", 10, 12, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_1", 16, 16, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_1", 24, 26, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_1", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_1", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_CNTL2[] = {
+	 { "RXDETECT_PRG_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDETECT_SAMPL_TIME", 1, 2, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_PRG_EN", 3, 3, &umr_bitfield_default },
+	 { "LS2_EXIT_TIME_PRG_EN", 4, 4, &umr_bitfield_default },
+	 { "SERVICE2_STEP4_DELAY_PRG_EN", 5, 5, &umr_bitfield_default },
+	 { "SERVICE3_STEP4_DELAY_PRG_EN", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_EN", 7, 7, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_1", 9, 9, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_2", 10, 10, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_3", 11, 11, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_4", 12, 12, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_5", 13, 13, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_6", 14, 14, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_7", 15, 15, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_8", 16, 16, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_9", 17, 17, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_10", 18, 18, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_11", 19, 19, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_12", 20, 20, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_13", 21, 21, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_14", 22, 22, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_15", 23, 23, &umr_bitfield_default },
+	 { "RXPHYSTATUS_DELAY", 24, 26, &umr_bitfield_default },
+	 { "RX_STAGGERING_MODE", 27, 27, &umr_bitfield_default },
+	 { "SPEEDCHANGE_STEP2_DELAY_PRG_EN", 28, 28, &umr_bitfield_default },
+	 { "RX_STAGGERING_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "PLL1_ALWAYS_ON_EN", 30, 30, &umr_bitfield_default },
+	 { "SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_TXPHYSTATUS[] = {
+	 { "TXPHYSTATUS_0", 0, 0, &umr_bitfield_default },
+	 { "TXPHYSTATUS_1", 1, 1, &umr_bitfield_default },
+	 { "TXPHYSTATUS_2", 2, 2, &umr_bitfield_default },
+	 { "TXPHYSTATUS_3", 3, 3, &umr_bitfield_default },
+	 { "TXPHYSTATUS_4", 4, 4, &umr_bitfield_default },
+	 { "TXPHYSTATUS_5", 5, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_6", 6, 6, &umr_bitfield_default },
+	 { "TXPHYSTATUS_7", 7, 7, &umr_bitfield_default },
+	 { "TXPHYSTATUS_8", 8, 8, &umr_bitfield_default },
+	 { "TXPHYSTATUS_9", 9, 9, &umr_bitfield_default },
+	 { "TXPHYSTATUS_10", 10, 10, &umr_bitfield_default },
+	 { "TXPHYSTATUS_11", 11, 11, &umr_bitfield_default },
+	 { "TXPHYSTATUS_12", 12, 12, &umr_bitfield_default },
+	 { "TXPHYSTATUS_13", 13, 13, &umr_bitfield_default },
+	 { "TXPHYSTATUS_14", 14, 14, &umr_bitfield_default },
+	 { "TXPHYSTATUS_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SC_CTL[] = {
+	 { "SC_CALIBRATION", 0, 0, &umr_bitfield_default },
+	 { "SC_RXDETECT", 1, 1, &umr_bitfield_default },
+	 { "SC_EXIT_L1_TO_L0S", 2, 2, &umr_bitfield_default },
+	 { "SC_EXIT_L1_TO_L0", 3, 3, &umr_bitfield_default },
+	 { "SC_ENTER_L1_FROM_L0S", 4, 4, &umr_bitfield_default },
+	 { "SC_ENTER_L1_FROM_L0", 5, 5, &umr_bitfield_default },
+	 { "SC_SPEED_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "SC_PHASE_1", 8, 8, &umr_bitfield_default },
+	 { "SC_PHASE_2", 9, 9, &umr_bitfield_default },
+	 { "SC_PHASE_3", 10, 10, &umr_bitfield_default },
+	 { "SC_PHASE_4", 11, 11, &umr_bitfield_default },
+	 { "SC_PHASE_5", 12, 12, &umr_bitfield_default },
+	 { "SC_PHASE_6", 13, 13, &umr_bitfield_default },
+	 { "SC_PHASE_7", 14, 14, &umr_bitfield_default },
+	 { "SC_PHASE_8", 15, 15, &umr_bitfield_default },
+	 { "SC_LANE_0_RESUME", 16, 16, &umr_bitfield_default },
+	 { "SC_LANE_1_RESUME", 17, 17, &umr_bitfield_default },
+	 { "SC_LANE_2_RESUME", 18, 18, &umr_bitfield_default },
+	 { "SC_LANE_3_RESUME", 19, 19, &umr_bitfield_default },
+	 { "SC_LANE_4_RESUME", 20, 20, &umr_bitfield_default },
+	 { "SC_LANE_5_RESUME", 21, 21, &umr_bitfield_default },
+	 { "SC_LANE_6_RESUME", 22, 22, &umr_bitfield_default },
+	 { "SC_LANE_7_RESUME", 23, 23, &umr_bitfield_default },
+	 { "SC_LANE_8_RESUME", 24, 24, &umr_bitfield_default },
+	 { "SC_LANE_9_RESUME", 25, 25, &umr_bitfield_default },
+	 { "SC_LANE_10_RESUME", 26, 26, &umr_bitfield_default },
+	 { "SC_LANE_11_RESUME", 27, 27, &umr_bitfield_default },
+	 { "SC_LANE_12_RESUME", 28, 28, &umr_bitfield_default },
+	 { "SC_LANE_13_RESUME", 29, 29, &umr_bitfield_default },
+	 { "SC_LANE_14_RESUME", 30, 30, &umr_bitfield_default },
+	 { "SC_LANE_15_RESUME", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PWRDOWN_2[] = {
+	 { "TX_POWER_STATE_IN_TXS2_2", 0, 2, &umr_bitfield_default },
+	 { "FORCE_RXEN_IN_L0s_2", 3, 3, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_2", 4, 6, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_2", 7, 9, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_2", 10, 12, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_2", 16, 16, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_2", 24, 26, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_2", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_2", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PWRDOWN_3[] = {
+	 { "TX_POWER_STATE_IN_TXS2_3", 0, 2, &umr_bitfield_default },
+	 { "FORCE_RXEN_IN_L0s_3", 3, 3, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_3", 4, 6, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_3", 7, 9, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_3", 10, 12, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_3", 16, 16, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_3", 24, 26, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_3", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_3", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SC_CTL2[] = {
+	 { "SERIAL_CFG_PERLANE_DISABLE_0", 0, 0, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_1", 1, 1, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_2", 2, 2, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_3", 3, 3, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_4", 4, 4, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_5", 5, 5, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_6", 6, 6, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_7", 7, 7, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_8", 8, 8, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_9", 9, 9, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_10", 10, 10, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_11", 11, 11, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_12", 12, 12, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_13", 13, 13, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_14", 14, 14, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PRG0[] = {
+	 { "PRG_RXDETECT_SAMPL_TIME", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PRG1[] = {
+	 { "PRG_PLL_RAMP_UP_TIME", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PRG2[] = {
+	 { "PRG_SERVICE2_STEP4_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PRG3[] = {
+	 { "PRG_SERVICE3_STEP4_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PRG4[] = {
+	 { "PRG_SPEEDCHANGE_STEP2_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PRG5[] = {
+	 { "PRG_LS2_EXIT_TIME", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_0[] = {
+	 { "TX_PDNB_OVERRIDE_EN_0", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_0", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_0", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_0", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_0", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_0", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_0", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_0", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_0", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_0", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_1[] = {
+	 { "TX_PDNB_OVERRIDE_EN_1", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_1", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_1", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_1", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_1", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_1", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_1", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_1", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_1", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_1", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_2[] = {
+	 { "TX_PDNB_OVERRIDE_EN_2", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_2", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_2", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_2", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_2", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_2", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_2", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_2", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_2", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_2", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_3[] = {
+	 { "TX_PDNB_OVERRIDE_EN_3", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_3", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_3", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_3", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_3", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_3", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_3", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_3", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_3", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_3", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_4[] = {
+	 { "TX_PDNB_OVERRIDE_EN_4", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_4", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_4", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_4", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_4", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_4", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_4", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_4", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_4", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_4", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_5[] = {
+	 { "TX_PDNB_OVERRIDE_EN_5", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_5", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_5", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_5", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_5", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_5", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_5", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_5", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_5", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_5", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_6[] = {
+	 { "TX_PDNB_OVERRIDE_EN_6", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_6", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_6", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_6", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_6", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_6", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_6", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_6", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_6", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_6", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_7[] = {
+	 { "TX_PDNB_OVERRIDE_EN_7", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_7", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_7", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_7", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_7", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_7", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_7", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_7", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_7", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_7", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_0[] = {
+	 { "SEQ_CALIBRATION_0", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_0", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_0", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_0", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_0", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_0", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_0", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_0", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_1[] = {
+	 { "SEQ_CALIBRATION_1", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_1", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_1", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_1", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_1", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_1", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_1", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_1", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_2[] = {
+	 { "SEQ_CALIBRATION_2", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_2", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_2", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_2", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_2", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_2", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_2", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_3[] = {
+	 { "SEQ_CALIBRATION_3", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_3", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_3", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_3", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_3", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_3", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_3", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_3", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_4[] = {
+	 { "SEQ_CALIBRATION_4", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_4", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_4", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_4", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_4", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_4", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_4", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_4", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_5[] = {
+	 { "SEQ_CALIBRATION_5", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_5", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_5", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_5", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_5", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_5", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_5", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_5", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_6[] = {
+	 { "SEQ_CALIBRATION_6", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_6", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_6", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_6", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_6", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_6", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_6", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_6", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_7[] = {
+	 { "SEQ_CALIBRATION_7", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_7", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_7", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_7", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_7", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_7", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_7", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_7", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_8[] = {
+	 { "TX_PDNB_OVERRIDE_EN_8", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_8", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_8", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_8", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_8", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_8", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_8", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_8", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_8", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_8", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_9[] = {
+	 { "TX_PDNB_OVERRIDE_EN_9", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_9", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_9", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_9", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_9", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_9", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_9", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_9", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_9", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_9", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_10[] = {
+	 { "TX_PDNB_OVERRIDE_EN_10", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_10", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_10", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_10", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_10", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_10", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_10", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_10", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_10", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_10", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_11[] = {
+	 { "TX_PDNB_OVERRIDE_EN_11", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_11", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_11", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_11", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_11", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_11", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_11", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_11", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_11", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_11", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_12[] = {
+	 { "TX_PDNB_OVERRIDE_EN_12", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_12", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_12", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_12", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_12", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_12", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_12", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_12", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_12", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_12", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_13[] = {
+	 { "TX_PDNB_OVERRIDE_EN_13", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_13", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_13", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_13", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_13", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_13", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_13", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_13", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_13", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_13", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_14[] = {
+	 { "TX_PDNB_OVERRIDE_EN_14", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_14", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_14", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_14", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_14", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_14", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_14", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_14", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_14", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_14", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_PDNB_OVERRIDE_15[] = {
+	 { "TX_PDNB_OVERRIDE_EN_15", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_15", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_15", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_15", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_15", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_15", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_15", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_15", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_15", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_15", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_8[] = {
+	 { "SEQ_CALIBRATION_8", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_8", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_8", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_8", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_8", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_8", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_8", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_8", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_9[] = {
+	 { "SEQ_CALIBRATION_9", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_9", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_9", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_9", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_9", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_9", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_9", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_9", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_10[] = {
+	 { "SEQ_CALIBRATION_10", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_10", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_10", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_10", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_10", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_10", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_10", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_10", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_11[] = {
+	 { "SEQ_CALIBRATION_11", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_11", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_11", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_11", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_11", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_11", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_11", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_11", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_12[] = {
+	 { "SEQ_CALIBRATION_12", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_12", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_12", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_12", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_12", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_12", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_12", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_12", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_13[] = {
+	 { "SEQ_CALIBRATION_13", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_13", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_13", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_13", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_13", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_13", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_13", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_13", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_14[] = {
+	 { "SEQ_CALIBRATION_14", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_14", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_14", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_14", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_14", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_14", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_14", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_14", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SEQ_STATUS_15[] = {
+	 { "SEQ_CALIBRATION_15", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_15", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_15", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_15", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_15", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_15", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_15", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_15", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVENDOR_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+	 { "LENGTH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG0[] = {
+	 { "BACKUP", 0, 15, &umr_bitfield_default },
+	 { "CFG_IDLEDET_TH", 16, 17, &umr_bitfield_default },
+	 { "DBG_RX2TXBYP_SEL", 20, 22, &umr_bitfield_default },
+	 { "DBG_RXFEBYP_EN", 23, 23, &umr_bitfield_default },
+	 { "DBG_RXPRBS_CLR", 24, 24, &umr_bitfield_default },
+	 { "DBG_RXTOGGLE_EN", 25, 25, &umr_bitfield_default },
+	 { "DBG_TX2RXLBACK_EN", 26, 26, &umr_bitfield_default },
+	 { "TXCFG_CMGOOD_RANGE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG1[] = {
+	 { "RXDBG_CDR_FR_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_CDR_FR_BYP_VAL", 1, 6, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_EN", 7, 7, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_VAL", 8, 13, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_EN", 14, 14, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_VAL", 15, 21, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_VAL", 23, 29, &umr_bitfield_default },
+	 { "TST_LOSPDTST_EN", 30, 30, &umr_bitfield_default },
+	 { "PLL_CFG_DISPCLK_DIV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG2[] = {
+	 { "RXDBG_D2TH_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_D2TH_BYP_VAL", 1, 7, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_EN", 8, 8, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_VAL", 9, 15, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_EN", 16, 16, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_VAL", 17, 23, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_EN", 24, 24, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_VAL", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG3[] = {
+	 { "RXDBG_SEL", 0, 4, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF0_SEL", 5, 6, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF1_SEL", 7, 8, &umr_bitfield_default },
+	 { "BG_CFG_RO_REG_VREF_SEL", 9, 10, &umr_bitfield_default },
+	 { "BG_DBG_VREFBYP_EN", 11, 11, &umr_bitfield_default },
+	 { "BG_DBG_IREFBYP_EN", 12, 12, &umr_bitfield_default },
+	 { "BG_DBG_ANALOG_SEL", 14, 16, &umr_bitfield_default },
+	 { "DBG_DLL_CLK_SEL", 18, 20, &umr_bitfield_default },
+	 { "PLL_DISPCLK_CMOS_SEL", 21, 21, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_VAL", 23, 26, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_EN", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_VAL", 28, 30, &umr_bitfield_default },
+	 { "DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG4[] = {
+	 { "DBG_RXAPU_INST", 0, 15, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_VAL", 16, 17, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_EN", 18, 18, &umr_bitfield_default },
+	 { "DBG_RXAPU_EXEC", 22, 25, &umr_bitfield_default },
+	 { "DBG_RXDLL_VREG_REF_SEL", 26, 26, &umr_bitfield_default },
+	 { "PWRGOOD_OVRD", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXRDATA_GATING_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG5[] = {
+	 { "DBG_RXAPU_MODE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_ALL_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_IMPCAL_ACTIVE_SCI_UPDT", 4, 4, &umr_bitfield_default },
+	 { "TXNIMP", 8, 11, &umr_bitfield_default },
+	 { "TXPIMP", 12, 15, &umr_bitfield_default },
+	 { "RXIMP", 16, 19, &umr_bitfield_default },
+	 { "IMPCAL_ACTIVE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG1[] = {
+	 { "IGNR_MODE_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L0T3", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L0T3", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_0", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_1", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_2", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_3", 15, 15, &umr_bitfield_default },
+	 { "MODE_0", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_0", 18, 19, &umr_bitfield_default },
+	 { "MODE_1", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_1", 22, 23, &umr_bitfield_default },
+	 { "MODE_2", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_2", 26, 27, &umr_bitfield_default },
+	 { "MODE_3", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG2[] = {
+	 { "IGNR_MODE_SCI_UPDT_L4T7", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L4T7", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_4", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_5", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_6", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_7", 15, 15, &umr_bitfield_default },
+	 { "MODE_4", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_4", 18, 19, &umr_bitfield_default },
+	 { "MODE_5", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_5", 22, 23, &umr_bitfield_default },
+	 { "MODE_6", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_6", 26, 27, &umr_bitfield_default },
+	 { "MODE_7", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_7", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG3[] = {
+	 { "IGNR_MODE_SCI_UPDT_L8T11", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L8T11", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_8", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_9", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_10", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_11", 15, 15, &umr_bitfield_default },
+	 { "MODE_8", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_8", 18, 19, &umr_bitfield_default },
+	 { "MODE_9", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_9", 22, 23, &umr_bitfield_default },
+	 { "MODE_10", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_10", 26, 27, &umr_bitfield_default },
+	 { "MODE_11", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_11", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG4[] = {
+	 { "IGNR_MODE_SCI_UPDT_L12T15", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L12T15", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L12T15", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_12", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_13", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_14", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_15", 15, 15, &umr_bitfield_default },
+	 { "MODE_12", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_12", 18, 19, &umr_bitfield_default },
+	 { "MODE_13", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_13", 22, 23, &umr_bitfield_default },
+	 { "MODE_14", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_14", 26, 27, &umr_bitfield_default },
+	 { "MODE_15", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG0[] = {
+	 { "TXPDTERM_VAL_OVRD_VAL", 0, 15, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG1[] = {
+	 { "TXPDTERM_VAL_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_VAL", 3, 3, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_EN", 15, 15, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG2[] = {
+	 { "BG_PWRON_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "BG_PWRON_OVRD_VAL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_HW_DEBUG[] = {
+	 { "PB0_HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "PB0_HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "PB0_HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "PB0_HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "PB0_HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "PB0_HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "PB0_HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "PB0_HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "PB0_HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "PB0_HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "PB0_HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "PB0_HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "PB0_HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "PB0_HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "PB0_HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "PB0_HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "PB0_HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "PB0_HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "PB0_HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "PB0_HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "PB0_HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "PB0_HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "PB0_HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "PB0_HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "PB0_HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "PB0_HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "PB0_HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "PB0_HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "PB0_HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "PB0_HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "PB0_HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "PB0_HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_GLB_REG0[] = {
+	 { "STRAP_QUICK_SIM_START", 1, 1, &umr_bitfield_default },
+	 { "STRAP_DFT_RXBSCAN_EN_VAL", 2, 2, &umr_bitfield_default },
+	 { "STRAP_DFT_CALIB_BYPASS", 3, 3, &umr_bitfield_default },
+	 { "STRAP_CFG_IDLEDET_TH", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL", 7, 11, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_OVR_PWRSF", 12, 12, &umr_bitfield_default },
+	 { "STRAP_RX_TRK_MODE_0_", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PWRGOOD_OVRD", 14, 14, &umr_bitfield_default },
+	 { "STRAP_DBG_RXDLL_VREG_REF_SEL", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_LC_VCO_TUNE", 16, 19, &umr_bitfield_default },
+	 { "STRAP_DBG_RXRDATA_GATING_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "STRAP_DBG_RXPI_OFFSET_BYP_VAL", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_TX_REG0[] = {
+	 { "STRAP_TX_CFG_DRV0_EN", 1, 4, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV0_TAP_SEL", 5, 8, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV1_EN", 9, 13, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV1_TAP_SEL", 14, 18, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV2_EN", 19, 22, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV2_TAP_SEL", 23, 26, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRVX_EN", 27, 27, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRVX_TAP_SEL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_RX_TRK_MODE_1_", 29, 29, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_SWING_BOOST_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_RX_REG0[] = {
+	 { "STRAP_RX_CFG_TH_LOOP_GAIN", 1, 4, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_DLL_FLOCK_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "STRAP_DBG_RXPI_OFFSET_BYP_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_LC_REG_VREF0_SEL", 8, 9, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_LC_REG_VREF1_SEL", 10, 11, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_CDR_TIME", 12, 15, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_FOM_TIME", 16, 19, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_TIME", 20, 23, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_OC_TIME", 24, 27, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_RPTR_RST_VAL", 28, 30, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_TERM_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_RX_REG1[] = {
+	 { "STRAP_RX_CFG_CDR_PI_STPSZ", 1, 1, &umr_bitfield_default },
+	 { "STRAP_TX_DEEMPH_PRSHT_STNG", 2, 4, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_RO_REG_VREF_SEL", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_POLE_BYP_DIS", 7, 7, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_POLE_BYP_VAL", 8, 10, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_CDR_PH_GAIN", 11, 14, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_ADAPT_MODE", 15, 24, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_DFE_TIME", 25, 28, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_LOOP_GAIN", 29, 30, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_SHUNT_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_PLL_REG0[] = {
+	 { "STRAP_PLL_CFG_LC_BW_CNTRL", 1, 3, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_LC_LF_CNTRL", 4, 12, &umr_bitfield_default },
+	 { "STRAP_TX_RXDET_X1_SSF", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_RO_BW_CNTRL", 16, 23, &umr_bitfield_default },
+	 { "STRAP_PLL_STRAP_SEL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_PIN_REG0[] = {
+	 { "STRAP_TX_DEEMPH_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_TX_FULL_SWING", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG0[] = {
+	 { "DFT_NUM_STEPS", 0, 5, &umr_bitfield_default },
+	 { "DFT_DISABLE_ERR", 7, 7, &umr_bitfield_default },
+	 { "DFT_CLK_PER_STEP", 8, 11, &umr_bitfield_default },
+	 { "DFT_MODE_CDR_EN", 20, 20, &umr_bitfield_default },
+	 { "DFT_EN_RECOVERY", 21, 21, &umr_bitfield_default },
+	 { "DFT_INCR_SWP_EN", 22, 22, &umr_bitfield_default },
+	 { "DFT_DECR_SWP_EN", 23, 23, &umr_bitfield_default },
+	 { "DFT_RECOVERY_TIME", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG1[] = {
+	 { "DFT_BYPASS_VALUE", 0, 7, &umr_bitfield_default },
+	 { "DFT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "DFT_BLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DFT_NUM_OF_TESTS", 17, 19, &umr_bitfield_default },
+	 { "DFT_CHECK_TIME", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG2[] = {
+	 { "DFT_LANE_EN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_DEBUG_CTRL_REG0[] = {
+	 { "DFT_PHY_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DFT_PHY_DEBUG_MODE", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_STAT_REG0[] = {
+	 { "DFT_STAT_DECR", 0, 7, &umr_bitfield_default },
+	 { "DFT_STAT_INCR", 8, 15, &umr_bitfield_default },
+	 { "DFT_STAT_FINISHED", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO_GLB_CTRL_REG0[] = {
+	 { "PLL_TST_LOSPDTST_SRC", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 2, 2, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 3, 3, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 4, 4, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 5, 5, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 6, 6, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_LUT_ENTRY_LS2", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_LUT_ENTRY_LS2", 8, 8, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 9, 9, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 10, 10, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 11, 11, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 12, 12, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 13, 13, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 14, 14, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN", 16, 16, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN", 17, 17, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN", 18, 18, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN", 19, 19, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN", 20, 20, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN", 21, 21, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN", 22, 22, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_CTRL_REG0[] = {
+	 { "PLL_DBG_RO_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_RO_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_DBG_RO_LF_CNTRL_0", 4, 10, &umr_bitfield_default },
+	 { "PLL_TST_RO_USAMPLE_EN_0", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_OVRD_REG0[] = {
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0", 0, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0", 9, 11, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_VAL_0", 15, 27, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0", 30, 30, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_OVRD_REG1[] = {
+	 { "PLL_CFG_RO_REFDIV_OVRD_VAL_0", 0, 4, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFDIV_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_VAL_0", 6, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0", 11, 11, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0", 19, 21, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO0_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO0_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO0_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO0_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO1_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO1_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO1_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO1_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO2_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO2_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO2_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO2_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO3_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO3_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO3_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO3_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_CTRL_REG0[] = {
+	 { "PLL_DBG_LC_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_LC_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_TST_LC_USAMPLE_EN_0", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_OVRD_REG0[] = {
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0", 4, 6, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_VAL_0", 10, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0", 19, 27, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_VAL_0", 29, 30, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_OVRD_REG1[] = {
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0", 14, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC0_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC0_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC0_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_LC0_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC1_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC1_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC1_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_LC1_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC2_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC2_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC2_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_LC2_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC3_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC3_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC3_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_LC3_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG0[] = {
+	 { "RX_CFG_ADAPT_MODE_GEN1", 0, 9, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN2", 10, 19, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN3", 20, 29, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_RST_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG1[] = {
+	 { "RX_CFG_CDR_FR_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN1", 24, 24, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN2", 25, 25, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN3", 26, 26, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_ASRT_TO_DCLK_EN", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG2[] = {
+	 { "RX_CFG_CDR_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN1", 24, 25, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN2", 26, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN3", 28, 29, &umr_bitfield_default },
+	 { "RX_DCLK_EN_ASRT_TO_ADAPT_HLD", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG3[] = {
+	 { "RX_CFG_CDR_FR_EN_GEN1", 0, 0, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN2", 1, 1, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN3", 2, 2, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG4[] = {
+	 { "RX_CFG_FOM_BER_GEN1", 0, 2, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN2", 3, 5, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN3", 6, 8, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN1", 9, 11, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN2", 12, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN3", 15, 17, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG5[] = {
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1", 0, 4, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2", 5, 9, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3", 10, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN1", 15, 15, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN2", 16, 16, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN3", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN1", 18, 18, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN2", 19, 19, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN3", 20, 20, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0", 30, 30, &umr_bitfield_default },
+	 { "RX_ADAPT_AUX_PWRON_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG6[] = {
+	 { "RX_CFG_LEQ_TIME_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0", 24, 24, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS2", 26, 26, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_LUT_ENTRY_LS2", 27, 27, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG7[] = {
+	 { "RX_CFG_TH_LOOP_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS2", 13, 13, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_LUT_ENTRY_LS2", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN1", 18, 20, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN2", 21, 23, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN3", 24, 26, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN3", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG8[] = {
+	 { "RX_DLL_LOCK_TIME", 0, 1, &umr_bitfield_default },
+	 { "RX_DLL_SPEEDCHANGE_RESET_TIME", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_RXPWR_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3", 4, 4, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7", 5, 5, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11", 6, 6, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15", 7, 7, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L0T3", 16, 16, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L4T7", 17, 17, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L8T11", 18, 18, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L12T15", 19, 19, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L0T3", 20, 20, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L4T7", 21, 21, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L8T11", 22, 22, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L12T15", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_OVRD_REG0[] = {
+	 { "RX_ADAPT_HLD_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_VAL", 6, 7, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_VAL", 15, 15, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_VAL", 17, 17, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_EN", 18, 18, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_VAL", 19, 19, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_EN", 20, 20, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_VAL", 21, 21, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_EN", 22, 22, &umr_bitfield_default },
+	 { "RX_TERM_EN_OVRD_VAL", 23, 23, &umr_bitfield_default },
+	 { "RX_TERM_EN_OVRD_EN", 24, 24, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_OVRD_REG1[] = {
+	 { "RX_ADAPT_TRK_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_TRK_OVRD_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE0_CTRL_REG0[] = {
+	 { "RX_BACKUP_0", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_0", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_0", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_0", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_0", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_0", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE1_CTRL_REG0[] = {
+	 { "RX_BACKUP_1", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_1", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_1", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_1", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_1", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_1", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_1", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE2_CTRL_REG0[] = {
+	 { "RX_BACKUP_2", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_2", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_2", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_2", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_2", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_2", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_2", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE3_CTRL_REG0[] = {
+	 { "RX_BACKUP_3", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_3", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_3", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_3", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_3", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_3", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_3", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE4_CTRL_REG0[] = {
+	 { "RX_BACKUP_4", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_4", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_4", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_4", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_4", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_4", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_4", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE5_CTRL_REG0[] = {
+	 { "RX_BACKUP_5", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_5", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_5", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_5", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_5", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_5", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_5", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE6_CTRL_REG0[] = {
+	 { "RX_BACKUP_6", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_6", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_6", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_6", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_6", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_6", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_6", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE7_CTRL_REG0[] = {
+	 { "RX_BACKUP_7", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_7", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_7", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_7", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_7", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_7", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_7", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE8_CTRL_REG0[] = {
+	 { "RX_BACKUP_8", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_8", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_8", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_8", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_8", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_8", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_8", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_8", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_8", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_8", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE9_CTRL_REG0[] = {
+	 { "RX_BACKUP_9", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_9", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_9", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_9", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_9", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_9", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_9", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_9", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_9", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_9", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE10_CTRL_REG0[] = {
+	 { "RX_BACKUP_10", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_10", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_10", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_10", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_10", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_10", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_10", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_10", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_10", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_10", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE11_CTRL_REG0[] = {
+	 { "RX_BACKUP_11", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_11", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_11", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_11", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_11", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_11", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_11", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_11", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_11", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_11", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE12_CTRL_REG0[] = {
+	 { "RX_BACKUP_12", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_12", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_12", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_12", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_12", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_12", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_12", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_12", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_12", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_12", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE13_CTRL_REG0[] = {
+	 { "RX_BACKUP_13", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_13", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_13", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_13", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_13", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_13", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_13", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_13", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_13", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_13", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE14_CTRL_REG0[] = {
+	 { "RX_BACKUP_14", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_14", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_14", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_14", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_14", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_14", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_14", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_14", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_14", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_14", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE15_CTRL_REG0[] = {
+	 { "RX_BACKUP_15", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_15", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_15", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_15", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_15", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_15", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_15", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_15", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_15", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_15", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_CTRL_REG0[] = {
+	 { "TX_DRV_DATA_ASRT_DLY_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_DSRT_DLY_VAL", 3, 5, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN1", 8, 10, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN2", 11, 13, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN3", 14, 16, &umr_bitfield_default },
+	 { "TX_STAGGER_CTRL", 17, 18, &umr_bitfield_default },
+	 { "TX_DATA_CLK_GATING", 19, 19, &umr_bitfield_default },
+	 { "TX_PRESET_TABLE_BYPASS", 20, 20, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_EN", 21, 21, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_DIR_VER", 22, 22, &umr_bitfield_default },
+	 { "TX_DCLK_EN_LSX_ALWAYS_ON", 23, 23, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_IN_OFF", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_LANE_SKEW_CTRL[] = {
+	 { "TX_CFG_GROUPX1_EN_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_6", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_7", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_8", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_9", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_10", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_11", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_12", 12, 12, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_13", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_14", 14, 14, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_15", 15, 15, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L0T1", 16, 16, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L2T3", 17, 17, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L4T5", 18, 18, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L6T7", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L8T9", 20, 20, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L10T11", 21, 21, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L12T13", 22, 22, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L14T15", 23, 23, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L0T3", 24, 24, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L4T7", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L8T11", 26, 26, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L12T15", 27, 27, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L0T7", 28, 28, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L8T15", 29, 29, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_L0T15", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_TXPWR_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L0T3", 4, 4, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L4T7", 5, 5, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L8T11", 6, 6, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L12T15", 7, 7, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[] = {
+	 { "ACCEPT_ENTRY_0", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_1", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_2", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_3", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_4", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_5", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_6", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_7", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_8", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_9", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_10", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_11", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_12", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_13", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_14", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_15", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_16", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_17", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_18", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_19", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_20", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_21", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_22", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_23", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_24", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_25", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_26", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_27", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_28", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_29", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_30", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_31", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[] = {
+	 { "ACCEPT_ENTRY_32", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_33", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_34", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_35", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_36", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_37", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_38", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_39", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_40", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_41", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_42", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_43", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_44", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_45", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_46", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_47", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_48", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_49", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_50", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_51", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_52", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_53", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_54", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_55", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_56", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_57", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_58", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_59", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_60", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_61", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_62", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_63", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[] = {
+	 { "ACCEPT_ENTRY_64", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_65", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_66", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_67", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_68", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_69", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_70", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_71", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_72", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_73", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_74", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_75", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_76", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_77", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_78", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_79", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_80", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_81", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_82", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_83", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_84", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_85", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_86", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_87", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_88", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_89", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_90", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_91", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_92", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_93", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_94", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_95", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[] = {
+	 { "ACCEPT_ENTRY_96", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_97", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_98", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_99", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_100", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_101", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_102", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_103", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_104", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_105", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_106", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_107", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_108", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_109", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG0[] = {
+	 { "TX_CFG_DCLK_DIV_OVRD_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_CFG_DCLK_DIV_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN1_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL", 9, 12, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_OVRD_EN", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN1_OVRD_VAL", 14, 18, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_OVRD_EN", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN1_OVRD_VAL", 26, 29, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_OVRD_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG1[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_OVRD_EN", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN1_OVRD_VAL", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_OVRD_EN", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_VAL", 15, 24, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_VAL", 26, 26, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_EN", 27, 27, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG2[] = {
+	 { "TX_WRITE_EN_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "TX_WRITE_EN_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_EN", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_VAL", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_EN", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_EN", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_VAL", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_EN", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN2_OVRD_VAL", 12, 15, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL", 16, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN2_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG3[] = {
+	 { "TX_CFG_DRV2_EN_GEN2_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN2_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN3_OVRD_VAL", 10, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL", 14, 17, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN3_OVRD_VAL", 18, 22, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL", 23, 27, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN3_OVRD_VAL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG4[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN3_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_0", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_0", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_0", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_0", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_0", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_0", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_0", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_1", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_1", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_1", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_1", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_1", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_1", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_1", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_1", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_1", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_2", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_2", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_2", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_2", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_2", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_2", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_2", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_2", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_2", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_2", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_3", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_3", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_3", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_3", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_3", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_3", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_3", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_3", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_3", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_3", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_4", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_4", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_4", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_4", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_4", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_4", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_4", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_4", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_4", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_4", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_5", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_5", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_5", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_5", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_5", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_5", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_5", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_5", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_5", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_5", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_5", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_6", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_6", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_6", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_6", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_6", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_6", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_6", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_6", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_6", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_6", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_6", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_7", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_7", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_7", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_7", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_7", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_7", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_7", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_7", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_7", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_7", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_7", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_8", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_8", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_8", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_8", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_8", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_8", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_8", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_8", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_8", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_8", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_8", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_8", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_8", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_8", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_8", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_8", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_9", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_9", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_9", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_9", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_9", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_9", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_9", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_9", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_9", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_9", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_9", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_9", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_9", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_9", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_9", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_9", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_10", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_10", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_10", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_10", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_10", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_10", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_10", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_10", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_10", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_10", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_10", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_10", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_10", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_10", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_10", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_10", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_11", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_11", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_11", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_11", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_11", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_11", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_11", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_11", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_11", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_11", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_11", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_11", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_11", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_11", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_11", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_11", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_12", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_12", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_12", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_12", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_12", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_12", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_12", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_12", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_12", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_12", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_12", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_12", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_12", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_12", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_12", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_12", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_13", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_13", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_13", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_13", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_13", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_13", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_13", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_13", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_13", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_13", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_13", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_13", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_13", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_13", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_13", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_13", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_14", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_14", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_14", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_14", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_14", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_14", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_14", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_14", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_14", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_14", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_14", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_14", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_14", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_14", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_14", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_14", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_15", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_15", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_15", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_15", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_15", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_15", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_15", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_15", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_15", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_15", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_15", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_15", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_15", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_15", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_15", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_15", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmADAPTER_ID_W[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_CAP[] = {
+	 { "VERSION", 0, 2, &umr_bitfield_default },
+	 { "PME_CLOCK", 3, 3, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 5, 5, &umr_bitfield_default },
+	 { "AUX_CURRENT", 6, 8, &umr_bitfield_default },
+	 { "D1_SUPPORT", 9, 9, &umr_bitfield_default },
+	 { "D2_SUPPORT", 10, 10, &umr_bitfield_default },
+	 { "PME_SUPPORT", 11, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RESERVED[] = {
+	 { "PCIE_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_SCRATCH[] = {
+	 { "PCIE_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_NUM_NAK[] = {
+	 { "RX_NUM_NAK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_NUM_NAK_GENERATED[] = {
+	 { "RX_NUM_NAK_GENERATED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CNTL[] = {
+	 { "HWINIT_WR_LOCK", 0, 0, &umr_bitfield_default },
+	 { "LC_HOT_PLUG_DELAY_SEL", 1, 3, &umr_bitfield_default },
+	 { "UR_ERR_REPORT_DIS", 7, 7, &umr_bitfield_default },
+	 { "PCIE_MALFORM_ATOMIC_OPS", 8, 8, &umr_bitfield_default },
+	 { "PCIE_HT_NP_MEM_WRITE", 9, 9, &umr_bitfield_default },
+	 { "RX_SB_ADJ_PAYLOAD_SIZE", 10, 12, &umr_bitfield_default },
+	 { "RX_RCB_ATS_UC_DIS", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_REORDER_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_RCB_INVALID_SIZE_DIS", 17, 17, &umr_bitfield_default },
+	 { "RX_RCB_UNEXP_CPL_DIS", 18, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_TEST_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_RCB_CHANNEL_ORDERING", 20, 20, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_ATTR_DIS", 21, 21, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_FUNCNUM_DIS", 22, 22, &umr_bitfield_default },
+	 { "RX_ATS_TRAN_CPL_SPLIT_DIS", 23, 23, &umr_bitfield_default },
+	 { "TX_CPL_DEBUG", 24, 29, &umr_bitfield_default },
+	 { "RX_IGNORE_LTR_MSG_UR", 30, 30, &umr_bitfield_default },
+	 { "RX_CPL_POSTED_REQ_ORD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CONFIG_CNTL[] = {
+	 { "DYN_CLK_LATENCY", 0, 3, &umr_bitfield_default },
+	 { "CI_MAX_PAYLOAD_SIZE_MODE", 16, 16, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_PAYLOAD_SIZE", 17, 19, &umr_bitfield_default },
+	 { "CI_MAX_READ_REQUEST_SIZE_MODE", 20, 20, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_READ_REQUEST_SIZE", 21, 23, &umr_bitfield_default },
+	 { "CI_MAX_READ_SAFE_MODE", 24, 24, &umr_bitfield_default },
+	 { "CI_EXTENDED_TAG_EN_OVERRIDE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_DEBUG_CNTL[] = {
+	 { "DEBUG_PORT_EN", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_SELECT", 8, 8, &umr_bitfield_default },
+	 { "DEBUG_LANE_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_INT_CNTL[] = {
+	 { "CORR_ERR_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_INT_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED_INT_EN", 3, 3, &umr_bitfield_default },
+	 { "MISC_ERR_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "POWER_STATE_CHG_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "LINK_BW_INT_EN", 7, 7, &umr_bitfield_default },
+	 { "QUIESCE_RCVD_INT_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_INT_STATUS[] = {
+	 { "CORR_ERR_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED_INT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "MISC_ERR_INT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "POWER_STATE_CHG_INT_STATUS", 6, 6, &umr_bitfield_default },
+	 { "LINK_BW_INT_STATUS", 7, 7, &umr_bitfield_default },
+	 { "QUIESCE_RCVD_INT_STATUS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CNTL2[] = {
+	 { "TX_ARB_ROUND_ROBIN_EN", 0, 0, &umr_bitfield_default },
+	 { "TX_ARB_SLV_LIMIT", 1, 5, &umr_bitfield_default },
+	 { "TX_ARB_MST_LIMIT", 6, 10, &umr_bitfield_default },
+	 { "TX_BLOCK_TLP_ON_PM_DIS", 11, 11, &umr_bitfield_default },
+	 { "SLV_MEM_LS_EN", 16, 16, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_LS_EN", 17, 17, &umr_bitfield_default },
+	 { "MST_MEM_LS_EN", 18, 18, &umr_bitfield_default },
+	 { "REPLAY_MEM_LS_EN", 19, 19, &umr_bitfield_default },
+	 { "SLV_MEM_SD_EN", 20, 20, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_SD_EN", 21, 21, &umr_bitfield_default },
+	 { "MST_MEM_SD_EN", 22, 22, &umr_bitfield_default },
+	 { "REPLAY_MEM_SD_EN", 23, 23, &umr_bitfield_default },
+	 { "RX_NP_MEM_WRITE_ENCODING", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL2[] = {
+	 { "RX_IGNORE_EP_INVALIDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMRD_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMWR_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ATSTRANSREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_PAGEREQMSG_UR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_INVCPL_UR", 5, 5, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_SCALE", 9, 11, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_MAX_COUNT", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_F0_ATTR_CNTL[] = {
+	 { "TX_F0_IDO_OVERRIDE_P", 0, 1, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_NP", 2, 3, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_CPL", 4, 5, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_P", 6, 7, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_NP", 8, 9, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_P", 10, 11, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_NP", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_F1_F2_ATTR_CNTL[] = {
+	 { "TX_F1_IDO_OVERRIDE_P", 0, 1, &umr_bitfield_default },
+	 { "TX_F1_IDO_OVERRIDE_NP", 2, 3, &umr_bitfield_default },
+	 { "TX_F1_IDO_OVERRIDE_CPL", 4, 5, &umr_bitfield_default },
+	 { "TX_F1_RO_OVERRIDE_P", 6, 7, &umr_bitfield_default },
+	 { "TX_F1_RO_OVERRIDE_NP", 8, 9, &umr_bitfield_default },
+	 { "TX_F1_SNR_OVERRIDE_P", 10, 11, &umr_bitfield_default },
+	 { "TX_F1_SNR_OVERRIDE_NP", 12, 13, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_P", 16, 17, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_NP", 18, 19, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_CPL", 20, 21, &umr_bitfield_default },
+	 { "TX_F2_RO_OVERRIDE_P", 22, 23, &umr_bitfield_default },
+	 { "TX_F2_RO_OVERRIDE_NP", 24, 25, &umr_bitfield_default },
+	 { "TX_F2_SNR_OVERRIDE_P", 26, 27, &umr_bitfield_default },
+	 { "TX_F2_SNR_OVERRIDE_NP", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CI_CNTL[] = {
+	 { "CI_SLAVE_SPLIT_MODE", 2, 2, &umr_bitfield_default },
+	 { "CI_SLAVE_GEN_USR_DIS", 3, 3, &umr_bitfield_default },
+	 { "CI_MST_CMPL_DUMMY_DATA", 4, 4, &umr_bitfield_default },
+	 { "CI_SLV_RC_RD_REQ_SIZE", 6, 7, &umr_bitfield_default },
+	 { "CI_SLV_ORDERING_DIS", 8, 8, &umr_bitfield_default },
+	 { "CI_RC_ORDERING_DIS", 9, 9, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_DIS", 10, 10, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_MODE", 11, 11, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_SOR", 12, 12, &umr_bitfield_default },
+	 { "CI_MST_IGNORE_PAGE_ALIGNED_REQUEST", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_BUS_CNTL[] = {
+	 { "PMI_INT_DIS", 6, 6, &umr_bitfield_default },
+	 { "IMMEDIATE_PMI_DIS", 7, 7, &umr_bitfield_default },
+	 { "TRUE_PM_STATUS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE6[] = {
+	 { "LC_PREV_STATE24", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE25", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE26", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE27", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE7[] = {
+	 { "LC_PREV_STATE28", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE29", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE30", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE31", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE8[] = {
+	 { "LC_PREV_STATE32", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE33", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE34", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE35", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE9[] = {
+	 { "LC_PREV_STATE36", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE37", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE38", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE39", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE10[] = {
+	 { "LC_PREV_STATE40", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE41", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE42", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE43", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE11[] = {
+	 { "LC_PREV_STATE44", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE45", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE46", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE47", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATUS1[] = {
+	 { "LC_REVERSE_RCVR", 0, 0, &umr_bitfield_default },
+	 { "LC_REVERSE_XMIT", 1, 1, &umr_bitfield_default },
+	 { "LC_OPERATING_LINK_WIDTH", 2, 4, &umr_bitfield_default },
+	 { "LC_DETECTED_LINK_WIDTH", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATUS2[] = {
+	 { "LC_TOTAL_INACTIVE_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_TURN_ON_LANE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WPR_CNTL[] = {
+	 { "WPR_RESET_HOT_RST_EN", 0, 0, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DWN_EN", 1, 1, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DIS_EN", 2, 2, &umr_bitfield_default },
+	 { "WPR_RESET_COR_EN", 3, 3, &umr_bitfield_default },
+	 { "WPR_RESET_REG_EN", 4, 4, &umr_bitfield_default },
+	 { "WPR_RESET_STY_EN", 5, 5, &umr_bitfield_default },
+	 { "WPR_RESET_PHY_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP0[] = {
+	 { "RX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP1[] = {
+	 { "RX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP2[] = {
+	 { "RX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP3[] = {
+	 { "RX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP0[] = {
+	 { "TX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP1[] = {
+	 { "TX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP2[] = {
+	 { "TX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP3[] = {
+	 { "TX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_I2C_REG_ADDR_EXPAND[] = {
+	 { "I2C_REG_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_I2C_REG_DATA[] = {
+	 { "I2C_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CFG_CNTL[] = {
+	 { "CFG_EN_DEC_TO_HIDDEN_REG", 0, 0, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG", 1, 1, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_CNTL[] = {
+	 { "P_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "P_SYMALIGN_MODE", 1, 1, &umr_bitfield_default },
+	 { "P_SYMALIGN_HW_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "P_ELASTDESKEW_HW_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "P_IGNORE_CRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "P_IGNORE_LEN_ERR", 5, 5, &umr_bitfield_default },
+	 { "P_IGNORE_EDB_ERR", 6, 6, &umr_bitfield_default },
+	 { "P_IGNORE_IDL_ERR", 7, 7, &umr_bitfield_default },
+	 { "P_IGNORE_TOK_ERR", 8, 8, &umr_bitfield_default },
+	 { "P_BLK_LOCK_MODE", 12, 12, &umr_bitfield_default },
+	 { "P_ALWAYS_USE_FAST_TXCLK", 13, 13, &umr_bitfield_default },
+	 { "P_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "DLP_IGNORE_IN_L1_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_BUF_STATUS[] = {
+	 { "P_OVERFLOW_ERR", 0, 15, &umr_bitfield_default },
+	 { "P_UNDERFLOW_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_DECODER_STATUS[] = {
+	 { "P_DECODE_ERR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_MISC_STATUS[] = {
+	 { "P_DESKEW_ERR", 0, 7, &umr_bitfield_default },
+	 { "P_SYMUNLOCK_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_RCV_L0S_FTS_DET[] = {
+	 { "P_RCV_L0S_FTS_DET_MIN", 0, 7, &umr_bitfield_default },
+	 { "P_RCV_L0S_FTS_DET_MAX", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LTR_CNTL[] = {
+	 { "LTR_PRIV_S_SHORT_VALUE", 0, 2, &umr_bitfield_default },
+	 { "LTR_PRIV_S_LONG_VALUE", 3, 5, &umr_bitfield_default },
+	 { "LTR_PRIV_S_REQUIREMENT", 6, 6, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_SHORT_VALUE", 7, 9, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_LONG_VALUE", 10, 12, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_REQUIREMENT", 13, 13, &umr_bitfield_default },
+	 { "LTR_PRIV_MSG_DIS_IN_PM_NON_D0", 14, 14, &umr_bitfield_default },
+	 { "LTR_PRIV_RST_LTR_IN_DL_DOWN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_OBFF_CNTL[] = {
+	 { "TX_OBFF_PRIV_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_SIMPLE_MODE_EN", 1, 1, &umr_bitfield_default },
+	 { "TX_OBFF_HOSTMEM_TO_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "TX_OBFF_SLVCPL_TO_ACTIVE", 3, 3, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_MAX_PULSE_WIDTH", 4, 7, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH", 8, 11, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_SAMPLING_PERIOD", 12, 15, &umr_bitfield_default },
+	 { "TX_OBFF_INTR_TO_ACTIVE", 16, 16, &umr_bitfield_default },
+	 { "TX_OBFF_ERR_TO_ACTIVE", 17, 17, &umr_bitfield_default },
+	 { "TX_OBFF_ANY_MSG_TO_ACTIVE", 18, 18, &umr_bitfield_default },
+	 { "TX_OBFF_PENDING_REQ_TO_ACTIVE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT_CNTL[] = {
+	 { "GLOBAL_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GLOBAL_SHADOW_WR", 1, 1, &umr_bitfield_default },
+	 { "GLOBAL_COUNT_RESET", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_TXCLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_TXCLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_TXCLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_MST_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_MST_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_MST_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_MST_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_MST_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_MST_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_S_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_S_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_S_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_NS_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[] = {
+	 { "PERF0_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[] = {
+	 { "PERF1_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_TXCLK2[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_TXCLK2[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_TXCLK2[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F0[] = {
+	 { "STRAP_F0_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F0_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F0_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F0_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F0_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F0_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F0_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F0_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F0_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F0_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F0_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F0_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F0_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F0_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+	 { "STRAP_F0_MC_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F1[] = {
+	 { "STRAP_F1_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F1_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F1_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F1_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F1_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F1_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F1_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F1_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F1_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F1_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F1_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F1_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F1_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F1_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F1_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F1_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F1_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F2[] = {
+	 { "STRAP_F2_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F2_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F2_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F2_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F2_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F2_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F2_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F2_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F2_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F2_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F2_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F2_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F2_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F2_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F2_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F2_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F2_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F7[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_MISC[] = {
+	 { "STRAP_LINK_CONFIG", 0, 3, &umr_bitfield_default },
+	 { "STRAP_TL_ALT_BUF_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_MAX_PASID_WIDTH", 8, 12, &umr_bitfield_default },
+	 { "STRAP_PASID_EXE_PERMISSION_SUPPORTED", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PASID_PRIV_MODE_SUPPORTED", 14, 14, &umr_bitfield_default },
+	 { "STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED", 15, 15, &umr_bitfield_default },
+	 { "STRAP_CLK_PM_EN", 24, 24, &umr_bitfield_default },
+	 { "STRAP_ECN1P1_EN", 25, 25, &umr_bitfield_default },
+	 { "STRAP_EXT_VC_COUNT", 26, 26, &umr_bitfield_default },
+	 { "STRAP_REVERSE_ALL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_MST_ADR64_EN", 29, 29, &umr_bitfield_default },
+	 { "STRAP_FLR_EN", 30, 30, &umr_bitfield_default },
+	 { "STRAP_INTERNAL_ERR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_MISC2[] = {
+	 { "STRAP_GEN2_COMPLIANCE", 1, 1, &umr_bitfield_default },
+	 { "STRAP_MSTCPL_TIMEOUT_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_GEN3_COMPLIANCE", 3, 3, &umr_bitfield_default },
+	 { "STRAP_TPH_SUPPORTED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_PI[] = {
+	 { "STRAP_QUICKSIM_START", 0, 0, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_PATTERN", 28, 28, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_MODE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_I2C_BD[] = {
+	 { "STRAP_BIF_I2C_SLV_ADR", 0, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_DBG_I2C_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_CLR[] = {
+	 { "PRBS_CLR", 0, 15, &umr_bitfield_default },
+	 { "PRBS_CHECKER_DEBUG_BUS_SELECT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_STATUS1[] = {
+	 { "PRBS_ERRSTAT", 0, 15, &umr_bitfield_default },
+	 { "PRBS_LOCKED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_STATUS2[] = {
+	 { "PRBS_BITCNT_DONE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_FREERUN[] = {
+	 { "PRBS_FREERUN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_MISC[] = {
+	 { "PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "PRBS_TEST_MODE", 1, 2, &umr_bitfield_default },
+	 { "PRBS_USER_PATTERN_TOGGLE", 3, 3, &umr_bitfield_default },
+	 { "PRBS_8BIT_SEL", 4, 4, &umr_bitfield_default },
+	 { "PRBS_COMMA_NUM", 5, 6, &umr_bitfield_default },
+	 { "PRBS_LOCK_CNT", 7, 11, &umr_bitfield_default },
+	 { "PRBS_DATA_RATE", 14, 15, &umr_bitfield_default },
+	 { "PRBS_CHK_ERR_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_USER_PATTERN[] = {
+	 { "PRBS_USER_PATTERN", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_LO_BITCNT[] = {
+	 { "PRBS_LO_BITCNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_HI_BITCNT[] = {
+	 { "PRBS_HI_BITCNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_0[] = {
+	 { "PRBS_ERRCNT_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_1[] = {
+	 { "PRBS_ERRCNT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_2[] = {
+	 { "PRBS_ERRCNT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_3[] = {
+	 { "PRBS_ERRCNT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_4[] = {
+	 { "PRBS_ERRCNT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_5[] = {
+	 { "PRBS_ERRCNT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_6[] = {
+	 { "PRBS_ERRCNT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_7[] = {
+	 { "PRBS_ERRCNT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_8[] = {
+	 { "PRBS_ERRCNT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_9[] = {
+	 { "PRBS_ERRCNT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_10[] = {
+	 { "PRBS_ERRCNT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_11[] = {
+	 { "PRBS_ERRCNT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_12[] = {
+	 { "PRBS_ERRCNT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_13[] = {
+	 { "PRBS_ERRCNT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_14[] = {
+	 { "PRBS_ERRCNT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_15[] = {
+	 { "PRBS_ERRCNT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_CAP[] = {
+	 { "TRANS_LAT_UNIT", 8, 9, &umr_bitfield_default },
+	 { "PWR_ALLOC_SCALE", 12, 13, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_0", 16, 23, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_LATENCY_INDICATOR[] = {
+	 { "TRANS_LAT_INDICATOR_BITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_CNTL[] = {
+	 { "SUBSTATE_STATUS", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_CNTL[] = {
+	 { "CP_RB0_WPTR", 0, 0, &umr_bitfield_default },
+	 { "CP_RB1_WPTR", 1, 1, &umr_bitfield_default },
+	 { "CP_RB2_WPTR", 2, 2, &umr_bitfield_default },
+	 { "UVD_RBC_RB_WPTR", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR", 5, 5, &umr_bitfield_default },
+	 { "CP_DMA_ME_COMMAND", 6, 6, &umr_bitfield_default },
+	 { "CP_DMA_PFP_COMMAND", 7, 7, &umr_bitfield_default },
+	 { "SAM_SAB_RBI_WPTR", 8, 8, &umr_bitfield_default },
+	 { "SAM_SAB_RBO_WPTR", 9, 9, &umr_bitfield_default },
+	 { "VCE_OUT_RB_WPTR", 10, 10, &umr_bitfield_default },
+	 { "VCE_RB_WPTR2", 11, 11, &umr_bitfield_default },
+	 { "VCE_RB_WPTR", 12, 12, &umr_bitfield_default },
+	 { "HOST_DOORBELL", 13, 13, &umr_bitfield_default },
+	 { "SELFRING_DOORBELL", 14, 14, &umr_bitfield_default },
+	 { "DISPLAY", 16, 16, &umr_bitfield_default },
+	 { "IGNORE_MC_DISABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_0[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_1[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_2[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_3[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_3[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_4[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_4[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_5[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_5[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_6[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_6[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_7[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_7[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_REQ[] = {
+	 { "FLUSH_REQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_GARLIC_FLUSH_REQ[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_GARLIC_FLUSH_DONE[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_RB0_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_RB1_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_RB2_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_UVD_RBC_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SDMA0_GFX_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SDMA1_GFX_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_DMA_ME_COMMAND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_DMA_PFP_COMMAND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SAM_SAB_RBI_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SAM_SAB_RBO_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_VCE_OUT_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_VCE_RB_WPTR2[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_VCE_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_SOFTRST_CNTL[] = {
+	 { "REG_RST_rstTimer", 0, 15, &umr_bitfield_default },
+	 { "REG_RST_softRstPropEn", 30, 30, &umr_bitfield_default },
+	 { "SoftRstReg", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[] = {
+	 { "CLIENT0_RFE_RFEWDBIF_rst", 0, 0, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWDBIF_rst", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MASTER_SOFTRST_TRIGGER[] = {
+	 { "BU_rst", 0, 0, &umr_bitfield_default },
+	 { "RWREG_RFEWDBIF_rst", 1, 1, &umr_bitfield_default },
+	 { "BX_rst", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PWDN_COMMAND[] = {
+	 { "REG_BU_pw_cmd", 0, 0, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWDBIF_pw_cmd", 1, 1, &umr_bitfield_default },
+	 { "REG_BX_pw_cmd", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PWDN_STATUS[] = {
+	 { "BU_REG_pw_status", 0, 0, &umr_bitfield_default },
+	 { "RWREG_RFEWDBIF_REG_pw_status", 1, 1, &umr_bitfield_default },
+	 { "BX_REG_pw_status", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_BU_CMDSTATUS[] = {
+	 { "REG_BU_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_BU_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_BU_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "BU_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS[] = {
+	 { "REG_RWREG_RFEWDBIF_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWDBIF_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWDBIF_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "RWREG_RFEWDBIF_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_BX_CMDSTATUS[] = {
+	 { "REG_BX_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_BX_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_BX_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "BX_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_TMOUT_STATUS[] = {
+	 { "MstTmoutStatus", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MMCFG_CNTL[] = {
+	 { "CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN", 0, 0, &umr_bitfield_default },
+	 { "CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL", 1, 3, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN", 4, 4, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_SMPLCNTL[] = {
+	 { "FORCE_DONE", 0, 0, &umr_bitfield_default },
+	 { "RxPDNB", 1, 1, &umr_bitfield_default },
+	 { "TxPDNB_pd", 2, 2, &umr_bitfield_default },
+	 { "TxPDNB_pu", 3, 3, &umr_bitfield_default },
+	 { "SAMPLE_PERIOD", 8, 12, &umr_bitfield_default },
+	 { "EXTEND_SAMPLES", 13, 13, &umr_bitfield_default },
+	 { "FORCE_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SETUP_TIME", 15, 19, &umr_bitfield_default },
+	 { "LOWER_SAMPLE_THRESH", 20, 25, &umr_bitfield_default },
+	 { "UPPER_SAMPLE_THRESH", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_RXCNTL[] = {
+	 { "RX_ADJUST", 0, 2, &umr_bitfield_default },
+	 { "RX_BIAS_HIGH", 3, 3, &umr_bitfield_default },
+	 { "CONT_AFTER_RX_DECT", 4, 4, &umr_bitfield_default },
+	 { "SUSPEND", 6, 6, &umr_bitfield_default },
+	 { "FORCE_RST", 7, 7, &umr_bitfield_default },
+	 { "LOWER_RX_ADJ_THRESH", 8, 11, &umr_bitfield_default },
+	 { "LOWER_RX_ADJ", 12, 12, &umr_bitfield_default },
+	 { "UPPER_RX_ADJ_THRESH", 13, 16, &umr_bitfield_default },
+	 { "UPPER_RX_ADJ", 17, 17, &umr_bitfield_default },
+	 { "RX_IMP_LOCKED", 18, 18, &umr_bitfield_default },
+	 { "RX_IMP_READBACK_SEL", 19, 19, &umr_bitfield_default },
+	 { "RX_IMP_READBACK", 20, 23, &umr_bitfield_default },
+	 { "RX_CMP_AMBIG", 28, 28, &umr_bitfield_default },
+	 { "CAL_DONE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_TXCNTL_pd[] = {
+	 { "TX_ADJUST_pd", 0, 2, &umr_bitfield_default },
+	 { "TX_BIAS_HIGH_pd", 3, 3, &umr_bitfield_default },
+	 { "LOWER_TX_ADJ_THRESH_pd", 8, 11, &umr_bitfield_default },
+	 { "LOWER_TX_ADJ_pd", 12, 12, &umr_bitfield_default },
+	 { "UPPER_TX_ADJ_THRESH_pd", 13, 16, &umr_bitfield_default },
+	 { "UPPER_TX_ADJ_pd", 17, 17, &umr_bitfield_default },
+	 { "TX_IMP_LOCKED_pd", 18, 18, &umr_bitfield_default },
+	 { "TX_IMP_READBACK_SEL_pd", 19, 19, &umr_bitfield_default },
+	 { "TX_IMP_READBACK_pd", 20, 23, &umr_bitfield_default },
+	 { "TX_CMP_AMBIG_pd", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_TXCNTL_pu[] = {
+	 { "TX_ADJUST_pu", 0, 2, &umr_bitfield_default },
+	 { "TX_BIAS_HIGH_pu", 3, 3, &umr_bitfield_default },
+	 { "LOWER_TX_ADJ_THRESH_pu", 8, 11, &umr_bitfield_default },
+	 { "LOWER_TX_ADJ_pu", 12, 12, &umr_bitfield_default },
+	 { "UPPER_TX_ADJ_THRESH_pu", 13, 16, &umr_bitfield_default },
+	 { "UPPER_TX_ADJ_pu", 17, 17, &umr_bitfield_default },
+	 { "TX_IMP_LOCKED_pu", 18, 18, &umr_bitfield_default },
+	 { "TX_IMP_READBACK_SEL_pu", 19, 19, &umr_bitfield_default },
+	 { "TX_IMP_READBACK_pu", 20, 23, &umr_bitfield_default },
+	 { "TX_CMP_AMBIG_pu", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD[] = {
+	 { "UPDATE_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_CC_RFE_IMP_OVERRIDECNTL[] = {
+	 { "STRAP_PLL_RX_IMPVAL", 1, 4, &umr_bitfield_default },
+	 { "STRAP_PLL_RX_IMPVAL_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_PLL_TX_IMPVAL_PD", 6, 9, &umr_bitfield_default },
+	 { "STRAP_PLL_TX_IMPVAL_EN_PD", 10, 10, &umr_bitfield_default },
+	 { "STRAP_PLL_TX_IMPVAL_PU", 11, 14, &umr_bitfield_default },
+	 { "STRAP_PLL_TX_IMPVAL_EN_PU", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_IMP_DBG_ANALOG_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_IMPRST_CNTL[] = {
+	 { "REG_RST_impEn", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_WARMRST_CNTL[] = {
+	 { "REG_RST_warmRstRfeEn", 0, 0, &umr_bitfield_default },
+	 { "REG_RST_warmRstImpEn", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_MSIC[] = {
+	 { "BIF_XTALIN_SEL", 0, 0, &umr_bitfield_default },
+	 { "BACO_LINK_RST_SEL", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PIF_TXCLK_SWITCH_TIMER[] = {
+	 { "PLL0_ACK_TIMER", 0, 2, &umr_bitfield_default },
+	 { "PLL1_ACK_TIMER", 3, 5, &umr_bitfield_default },
+	 { "PLL_SWITCH_TIMER", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RESET_EN[] = {
+	 { "SOFT_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "PHY_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "COR_RESET_EN", 3, 3, &umr_bitfield_default },
+	 { "REG_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "STY_RESET_EN", 5, 5, &umr_bitfield_default },
+	 { "CFG_RESET_EN", 6, 6, &umr_bitfield_default },
+	 { "DRV_RESET_EN", 7, 7, &umr_bitfield_default },
+	 { "RESET_CFGREG_ONLY_EN", 8, 8, &umr_bitfield_default },
+	 { "HOT_RESET_EN", 9, 9, &umr_bitfield_default },
+	 { "LINK_DISABLE_RESET_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_DOWN_RESET_EN", 11, 11, &umr_bitfield_default },
+	 { "CFG_RESET_PULSE_WIDTH", 12, 17, &umr_bitfield_default },
+	 { "DRV_RESET_DELAY_SEL", 18, 19, &umr_bitfield_default },
+	 { "PIF_RSTB_EN", 20, 20, &umr_bitfield_default },
+	 { "PIF_STRAP_ALLVALID_EN", 21, 21, &umr_bitfield_default },
+	 { "BIF_COR_RESET_EN", 22, 22, &umr_bitfield_default },
+	 { "FUNC0_FLR_EN", 23, 23, &umr_bitfield_default },
+	 { "FUNC1_FLR_EN", 24, 24, &umr_bitfield_default },
+	 { "FUNC2_FLR_EN", 25, 25, &umr_bitfield_default },
+	 { "FUNC0_RESET_DELAY_SEL", 26, 27, &umr_bitfield_default },
+	 { "FUNC1_RESET_DELAY_SEL", 28, 29, &umr_bitfield_default },
+	 { "FUNC2_RESET_DELAY_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_CLK_PDWN_DELAY_TIMER[] = {
+	 { "TIMER", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmNEW_REFCLKB_TIMER_1[] = {
+	 { "PHY_PLL_PDWN_TIMER", 0, 9, &umr_bitfield_default },
+	 { "PLL0_PDNB_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmNEW_REFCLKB_TIMER[] = {
+	 { "REG_STOP_REFCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "STOP_REFCLK_TIMER", 1, 20, &umr_bitfield_default },
+	 { "REFCLK_ON", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RESET_CNTL[] = {
+	 { "STRAP_EN", 0, 0, &umr_bitfield_default },
+	 { "RST_DONE", 1, 1, &umr_bitfield_default },
+	 { "LINK_TRAIN_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_ALL_VALID", 3, 3, &umr_bitfield_default },
+	 { "RECAP_STRAP_WARMRST", 8, 8, &umr_bitfield_default },
+	 { "HOLD_LKTRN_WARMRST_DIS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLNCNT_CONTROL[] = {
+	 { "LNCNT_ACC_MODE", 0, 0, &umr_bitfield_default },
+	 { "LNCNT_REF_TIMEBASE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_LNCNT_RESET[] = {
+	 { "RESET_LNCNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_CLOCKS_BITS[] = {
+	 { "OBFF_XSL_FORCE_REFCLK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_CNTL_MISC[] = {
+	 { "ADAPT_pif0_bu_reg_accessMode", 0, 0, &umr_bitfield_default },
+	 { "ADAPT_pif1_bu_reg_accessMode", 1, 1, &umr_bitfield_default },
+	 { "ADAPT_pwreg_bu_reg_accessMode", 2, 2, &umr_bitfield_default },
+	 { "ADAPT_pciecore0_bu_reg_accessMode", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_XDMA_LO[] = {
+	 { "BIF_XDMA_LOWER_BOUND", 0, 28, &umr_bitfield_default },
+	 { "BIF_XDMA_APER_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_XDMA_HI[] = {
+	 { "BIF_XDMA_UPPER_BOUND", 0, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_FEATURES_CONTROL_MISC[] = {
+	 { "MST_BIF_REQ_EP_DIS", 0, 0, &umr_bitfield_default },
+	 { "SLV_BIF_CPL_EP_DIS", 1, 1, &umr_bitfield_default },
+	 { "BIF_SLV_REQ_EP_DIS", 2, 2, &umr_bitfield_default },
+	 { "BIF_MST_CPL_EP_DIS", 3, 3, &umr_bitfield_default },
+	 { "UR_PSN_PKT_REPORT_POISON_DIS", 4, 4, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS", 5, 5, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS", 6, 6, &umr_bitfield_default },
+	 { "PLL_SWITCH_IMPCTL_CAL_DONE_DIS", 7, 7, &umr_bitfield_default },
+	 { "IGNORE_BE_CHECK_GASKET_COMB_DIS", 8, 8, &umr_bitfield_default },
+	 { "MC_BIF_REQ_ID_ROUTING_DIS", 9, 9, &umr_bitfield_default },
+	 { "AZ_BIF_REQ_ID_ROUTING_DIS", 10, 10, &umr_bitfield_default },
+	 { "ATC_PRG_RESP_PASID_UR_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_CNTL[] = {
+	 { "SELF_RING_DIS", 0, 0, &umr_bitfield_default },
+	 { "TRANS_CHECK_DIS", 1, 1, &umr_bitfield_default },
+	 { "UNTRANS_LBACK_EN", 2, 2, &umr_bitfield_default },
+	 { "NON_CONSECUTIVE_BE_ZERO_DIS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SLVARB_MODE[] = {
+	 { "SLVARB_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBUS_BACO_DUMMY[] = {
+	 { "SMBUS_BACO_DUMMY_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBF_ANA_ISO_CNTL[] = {
+	 { "BF_ANA_ISO_DIS_MASK", 0, 0, &umr_bitfield_default },
+	 { "BF_VDDC_ISO_DIS_MASK", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_PWR_STATUS[] = {
+	 { "SSA_GFX_PWR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "SSA_DISP_PWR_STATUS", 1, 1, &umr_bitfield_default },
+	 { "SSA_MC_PWR_STATUS", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX0_LOWER[] = {
+	 { "SSA_GFX0_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_GFX0_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_GFX0_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX0_UPPER[] = {
+	 { "SSA_GFX0_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX1_LOWER[] = {
+	 { "SSA_GFX1_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_GFX1_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_GFX1_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX1_UPPER[] = {
+	 { "SSA_GFX1_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX2_LOWER[] = {
+	 { "SSA_GFX2_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_GFX2_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_GFX2_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX2_UPPER[] = {
+	 { "SSA_GFX2_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX3_LOWER[] = {
+	 { "SSA_GFX3_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_GFX3_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_GFX3_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_GFX3_UPPER[] = {
+	 { "SSA_GFX3_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_DISP_LOWER[] = {
+	 { "SSA_DISP_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_DISP_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_DISP_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_DISP_UPPER[] = {
+	 { "SSA_DISP_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_MC_LOWER[] = {
+	 { "SSA_MC_LOWER", 2, 17, &umr_bitfield_default },
+	 { "SSA_MC_FB_STALL_EN", 29, 29, &umr_bitfield_default },
+	 { "SSA_MC_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "SSA_MC_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SSA_MC_UPPER[] = {
+	 { "SSA_MC_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBACO_CNTL_MISC[] = {
+	 { "BIF_ROM_REQ_DIS", 0, 0, &umr_bitfield_default },
+	 { "BIF_AZ_REQ_DIS", 1, 1, &umr_bitfield_default },
+	 { "BACO_LINK_RST_WIDTH_SEL", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_DEBUG_LATCH[] = {
+	 { "BIF_BACO_LATCH_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_DEBUG[] = {
+	 { "BIF_BACO_SCANDUMP_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMEM_TYPE_CNTL[] = {
+	 { "BF_MEM_PHY_G5_G3", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBACO_CNTL[] = {
+	 { "BACO_EN", 0, 0, &umr_bitfield_default },
+	 { "BACO_BCLK_OFF", 1, 1, &umr_bitfield_default },
+	 { "BACO_ISO_DIS", 2, 2, &umr_bitfield_default },
+	 { "BACO_POWER_OFF", 3, 3, &umr_bitfield_default },
+	 { "BACO_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "BACO_HANG_PROTECTION_EN", 5, 5, &umr_bitfield_default },
+	 { "BACO_MODE", 6, 6, &umr_bitfield_default },
+	 { "BACO_ANA_ISO_DIS", 7, 7, &umr_bitfield_default },
+	 { "RCU_BIF_CONFIG_DONE", 8, 8, &umr_bitfield_default },
+	 { "PWRGOOD_BF", 9, 9, &umr_bitfield_default },
+	 { "PWRGOOD_GPIO", 10, 10, &umr_bitfield_default },
+	 { "PWRGOOD_MEM", 11, 11, &umr_bitfield_default },
+	 { "PWRGOOD_DVO", 12, 12, &umr_bitfield_default },
+	 { "PWRGOOD_IDSC", 13, 13, &umr_bitfield_default },
+	 { "BACO_POWER_OFF_DRAM", 16, 16, &umr_bitfield_default },
+	 { "BACO_BF_MEM_PHY_ISO_CNTRL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEVFUNCNUM_LIST1[] = {
+	 { "DEVFUNC_ID4", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID5", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID6", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEVFUNCNUM_LIST0[] = {
+	 { "DEVFUNC_ID0", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID1", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID2", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDBG_BYPASS_SRBM_ACCESS[] = {
+	 { "DBG_BYPASS_SRBM_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "DBG_APER_AD", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER3_FB_OFFSET_LO[] = {
+	 { "PEER3_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER3_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER3_FB_OFFSET_HI[] = {
+	 { "PEER3_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER2_FB_OFFSET_LO[] = {
+	 { "PEER2_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER2_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER2_FB_OFFSET_HI[] = {
+	 { "PEER2_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER1_FB_OFFSET_LO[] = {
+	 { "PEER1_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER1_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER1_FB_OFFSET_HI[] = {
+	 { "PEER1_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER0_FB_OFFSET_LO[] = {
+	 { "PEER0_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER0_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER0_FB_OFFSET_HI[] = {
+	 { "PEER0_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMPCTL_RESET[] = {
+	 { "IMP_SW_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBUS_SLV_CNTL[] = {
+	 { "SMB_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "SMB_SLV_ADR", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBUS_SLV_CNTL1[] = {
+	 { "SMB_TIMEOUT_THRESHOLD", 0, 21, &umr_bitfield_default },
+	 { "SMB_XTALIN_FREQUENCY_SEL", 24, 24, &umr_bitfield_default },
+	 { "SMB_TIMEOUT_DIS", 25, 25, &umr_bitfield_default },
+	 { "SMB_DAT_HOLD_TIME_MARGIN", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBUS_CNTL[] = {
+	 { "BIOS_ROM_WRT_EN", 0, 0, &umr_bitfield_default },
+	 { "BIOS_ROM_DIS", 1, 1, &umr_bitfield_default },
+	 { "PMI_IO_DIS", 2, 2, &umr_bitfield_default },
+	 { "PMI_MEM_DIS", 3, 3, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 4, 4, &umr_bitfield_default },
+	 { "PMI_INT_DIS", 5, 5, &umr_bitfield_default },
+	 { "VGA_REG_COHERENCY_DIS", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_COHERENCY_DIS", 7, 7, &umr_bitfield_default },
+	 { "BIF_ERR_RTR_BKPRESSURE_EN", 8, 8, &umr_bitfield_default },
+	 { "SET_AZ_TC", 10, 12, &umr_bitfield_default },
+	 { "SET_MC_TC", 13, 15, &umr_bitfield_default },
+	 { "ZERO_BE_WR_EN", 16, 16, &umr_bitfield_default },
+	 { "ZERO_BE_RD_EN", 17, 17, &umr_bitfield_default },
+	 { "RD_STALL_IO_WR", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_CNTL[] = {
+	 { "CFG_VGA_RAM_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_DIS", 1, 1, &umr_bitfield_default },
+	 { "GENMO_MONO_ADDRESS_B", 2, 2, &umr_bitfield_default },
+	 { "GRPH_ADRSEL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_MEMSIZE[] = {
+	 { "CONFIG_MEMSIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_F0_BASE[] = {
+	 { "F0_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_APER_SIZE[] = {
+	 { "APER_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_REG_APER_SIZE[] = {
+	 { "REG_APER_SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SCRATCH0[] = {
+	 { "BIF_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SCRATCH1[] = {
+	 { "BIF_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_CFGREGS_CNTL[] = {
+	 { "MM_CFG_FUNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "MM_WR_TO_CFG_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBX_RESET_EN[] = {
+	 { "COR_RESET_EN", 0, 0, &umr_bitfield_default },
+	 { "REG_RESET_EN", 1, 1, &umr_bitfield_default },
+	 { "STY_RESET_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_CREDIT_CNTL[] = {
+	 { "BIF_MC_RDRET_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "BIF_AZ_RDRET_CREDIT", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_REQ_CREDIT_CNTL[] = {
+	 { "BIF_SRBM_REQ_CREDIT", 0, 4, &umr_bitfield_default },
+	 { "BIF_VGA_REQ_CREDIT", 5, 8, &umr_bitfield_default },
+	 { "BIF_HDP_REQ_CREDIT", 10, 14, &umr_bitfield_default },
+	 { "BIF_ROM_REQ_CREDIT", 15, 15, &umr_bitfield_default },
+	 { "BIF_AZ_REQ_CREDIT", 20, 20, &umr_bitfield_default },
+	 { "BIF_XDMA_REQ_CREDIT", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBX_RESET_CNTL[] = {
+	 { "LINK_TRAIN_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CNTL[] = {
+	 { "IH_DUMMY_RD_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "IH_DUMMY_RD_EN", 1, 1, &umr_bitfield_default },
+	 { "IH_REQ_NONSNOOP_EN", 3, 3, &umr_bitfield_default },
+	 { "IH_INTR_DLY_CNTR", 4, 7, &umr_bitfield_default },
+	 { "GEN_IH_INT_EN", 8, 8, &umr_bitfield_default },
+	 { "GEN_GPIO_INT_EN", 9, 12, &umr_bitfield_default },
+	 { "SELECT_INT_GPIO_OUTPUT", 13, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CNTL2[] = {
+	 { "IH_DUMMY_RD_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_CNTL[] = {
+	 { "DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_MULTIBLOCKEN", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "DEBUG_PAD_SEL", 3, 3, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK1", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK2", 5, 5, &umr_bitfield_default },
+	 { "DEBUG_SYNC_EN", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_SWAP", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK1", 8, 12, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK2", 16, 20, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_XSP", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_SYNC_CLKSEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_MUX[] = {
+	 { "DEBUG_MUX_BLK1", 0, 5, &umr_bitfield_default },
+	 { "DEBUG_MUX_BLK2", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_OUT[] = {
+	 { "DEBUG_OUTPUT", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEM_COHERENCY_FLUSH_CNTL[] = {
+	 { "HDP_MEM_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCLKREQB_PAD_CNTL[] = {
+	 { "CLKREQB_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "CLKREQB_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "CLKREQB_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "CLKREQB_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBDAT_PAD_CNTL[] = {
+	 { "SMBDAT_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "SMBDAT_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "SMBDAT_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "SMBDAT_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBCLK_PAD_CNTL[] = {
+	 { "SMBCLK_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "SMBCLK_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "SMBCLK_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "SMBCLK_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_FB_EN[] = {
+	 { "FB_READ_EN", 0, 0, &umr_bitfield_default },
+	 { "FB_WRITE_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_CNTL1[] = {
+	 { "ID_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_LIST0[] = {
+	 { "ID0", 0, 7, &umr_bitfield_default },
+	 { "ID1", 8, 15, &umr_bitfield_default },
+	 { "ID2", 16, 23, &umr_bitfield_default },
+	 { "ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_LIST1[] = {
+	 { "ID4", 0, 7, &umr_bitfield_default },
+	 { "ID5", 8, 15, &umr_bitfield_default },
+	 { "ID6", 16, 23, &umr_bitfield_default },
+	 { "ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_REG_COHERENCY_FLUSH_CNTL[] = {
+	 { "HDP_REG_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSY_DELAY_CNTR[] = {
+	 { "DELAY_CNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_CNTL2[] = {
+	 { "AUTOUPDATE_SEL", 0, 7, &umr_bitfield_default },
+	 { "AUTOUPDATE_EN", 8, 8, &umr_bitfield_default },
+	 { "HDPREG_CNTL", 16, 16, &umr_bitfield_default },
+	 { "ERROR_MULTIPLE_ID_MATCH", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFMON_CNTL[] = {
+	 { "PERFCOUNTER_EN", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET0", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET1", 2, 2, &umr_bitfield_default },
+	 { "PERF_SEL0", 8, 12, &umr_bitfield_default },
+	 { "PERF_SEL1", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFCOUNTER0_RESULT[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFCOUNTER1_RESULT[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_HANG_PROTECTION_CNTL[] = {
+	 { "HANG_PROTECTION_TIMER_SEL", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_HDP_FLUSH_REQ[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_HDP_FLUSH_DONE[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_HANG_ERROR[] = {
+	 { "SRBM_HANG_ERROR", 0, 0, &umr_bitfield_default },
+	 { "HDP_HANG_ERROR", 1, 1, &umr_bitfield_default },
+	 { "VGA_HANG_ERROR", 2, 2, &umr_bitfield_default },
+	 { "ROM_HANG_ERROR", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_HANG_ERROR", 4, 4, &umr_bitfield_default },
+	 { "CEC_HANG_ERROR", 5, 5, &umr_bitfield_default },
+	 { "XDMA_HANG_ERROR", 7, 7, &umr_bitfield_default },
+	 { "DOORBELL_HANG_ERROR", 8, 8, &umr_bitfield_default },
+	 { "GARLIC_HANG_ERROR", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCAPTURE_HOST_BUSNUM[] = {
+	 { "CHECK_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHOST_BUSNUM[] = {
+	 { "HOST_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER_REG_RANGE0[] = {
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER_REG_RANGE1[] = {
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CAP[] = {
+	 { "VERSION", 0, 3, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 4, 7, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 8, 8, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 9, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_STATUS[] = {
+	 { "CORR_ERR", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED", 3, 3, &umr_bitfield_default },
+	 { "AUX_PWR", 4, 4, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "INITIATE_FLR", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "LINK_TRAINING", 11, 11, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 12, 12, &umr_bitfield_default },
+	 { "DL_ACTIVE", 13, 13, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_CLASS[] = {
+	 { "BASE_CLASS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSUB_CLASS[] = {
+	 { "SUB_CLASS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_STATUS2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SCRATCH[] = {
+	 { "PIF_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_HW_DEBUG[] = {
+	 { "PB1_PIF_HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "PB1_PIF_HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "PB1_PIF_HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "PB1_PIF_HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "PB1_PIF_HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "PB1_PIF_HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "PB1_PIF_HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "PB1_PIF_HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "PB1_PIF_HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "PB1_PIF_HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "PB1_PIF_HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "PB1_PIF_HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "PB1_PIF_HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "PB1_PIF_HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "PB1_PIF_HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "PB1_PIF_HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PRG6[] = {
+	 { "PRG_SPEEDCHANGE_STEP4_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PRG7[] = {
+	 { "PRG_SPEEDCHANGE_STEP4_FIRSTGEN3_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_CNTL[] = {
+	 { "SERIAL_CFG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_0", 1, 1, &umr_bitfield_default },
+	 { "PHY_CR_EN_MODE", 2, 2, &umr_bitfield_default },
+	 { "PHYCMD_CR_EN_MODE", 3, 3, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_MODE", 4, 4, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_1", 5, 5, &umr_bitfield_default },
+	 { "RXDETECT_FIFO_RESET_MODE", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_TX_PWR_MODE", 7, 7, &umr_bitfield_default },
+	 { "DIVINIT_MODE", 8, 8, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_2", 9, 9, &umr_bitfield_default },
+	 { "PLL_BINDING_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "SC_CALIB_DONE_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DIVINIT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DA_FIFO_RESET_3", 13, 13, &umr_bitfield_default },
+	 { "PLL0_IN_GEN3_MODE", 14, 14, &umr_bitfield_default },
+	 { "FORCE_TxFreqEquZeroinDTM_EN", 15, 15, &umr_bitfield_default },
+	 { "TXGND_TIME", 16, 16, &umr_bitfield_default },
+	 { "LS2_EXIT_TIME", 17, 19, &umr_bitfield_default },
+	 { "EI_CYCLE_OFF_TIME", 20, 22, &umr_bitfield_default },
+	 { "EXIT_L0S_INIT_DIS", 23, 23, &umr_bitfield_default },
+	 { "RXEN_GATER", 24, 27, &umr_bitfield_default },
+	 { "EXTEND_WAIT_FOR_RAMPUP", 28, 28, &umr_bitfield_default },
+	 { "IGNORE_TxDataValid_EP_DIS", 29, 29, &umr_bitfield_default },
+	 { "PHYRESPONSEMODE_ON_RXDET_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PAIRING[] = {
+	 { "X2_LANE_1_0", 0, 0, &umr_bitfield_default },
+	 { "X2_LANE_3_2", 1, 1, &umr_bitfield_default },
+	 { "X2_LANE_5_4", 2, 2, &umr_bitfield_default },
+	 { "X2_LANE_7_6", 3, 3, &umr_bitfield_default },
+	 { "X2_LANE_9_8", 4, 4, &umr_bitfield_default },
+	 { "X2_LANE_11_10", 5, 5, &umr_bitfield_default },
+	 { "X2_LANE_13_12", 6, 6, &umr_bitfield_default },
+	 { "X2_LANE_15_14", 7, 7, &umr_bitfield_default },
+	 { "X4_LANE_3_0", 8, 8, &umr_bitfield_default },
+	 { "X4_LANE_7_4", 9, 9, &umr_bitfield_default },
+	 { "X4_LANE_11_8", 10, 10, &umr_bitfield_default },
+	 { "X4_LANE_15_12", 11, 11, &umr_bitfield_default },
+	 { "X8_LANE_7_0", 16, 16, &umr_bitfield_default },
+	 { "X8_LANE_15_8", 17, 17, &umr_bitfield_default },
+	 { "X16_LANE_15_0", 20, 20, &umr_bitfield_default },
+	 { "MULTI_PIF", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PWRDOWN_0[] = {
+	 { "TX_POWER_STATE_IN_TXS2_0", 0, 2, &umr_bitfield_default },
+	 { "FORCE_RXEN_IN_L0s_0", 3, 3, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_0", 4, 6, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_0", 7, 9, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_0", 10, 12, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_0", 16, 16, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_0", 24, 26, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_0", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PWRDOWN_1[] = {
+	 { "TX_POWER_STATE_IN_TXS2_1", 0, 2, &umr_bitfield_default },
+	 { "FORCE_RXEN_IN_L0s_1", 3, 3, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_1", 4, 6, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_1", 7, 9, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_1", 10, 12, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_1", 16, 16, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_1", 24, 26, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_1", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_1", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_CNTL2[] = {
+	 { "RXDETECT_PRG_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDETECT_SAMPL_TIME", 1, 2, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_PRG_EN", 3, 3, &umr_bitfield_default },
+	 { "LS2_EXIT_TIME_PRG_EN", 4, 4, &umr_bitfield_default },
+	 { "SERVICE2_STEP4_DELAY_PRG_EN", 5, 5, &umr_bitfield_default },
+	 { "SERVICE3_STEP4_DELAY_PRG_EN", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_EN", 7, 7, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_1", 9, 9, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_2", 10, 10, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_3", 11, 11, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_4", 12, 12, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_5", 13, 13, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_6", 14, 14, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_7", 15, 15, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_8", 16, 16, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_9", 17, 17, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_10", 18, 18, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_11", 19, 19, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_12", 20, 20, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_13", 21, 21, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_14", 22, 22, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_15", 23, 23, &umr_bitfield_default },
+	 { "RXPHYSTATUS_DELAY", 24, 26, &umr_bitfield_default },
+	 { "RX_STAGGERING_MODE", 27, 27, &umr_bitfield_default },
+	 { "SPEEDCHANGE_STEP2_DELAY_PRG_EN", 28, 28, &umr_bitfield_default },
+	 { "RX_STAGGERING_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "PLL1_ALWAYS_ON_EN", 30, 30, &umr_bitfield_default },
+	 { "SPEEDCHANGE_STEP4_DELAY_FORCE_LONG_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_TXPHYSTATUS[] = {
+	 { "TXPHYSTATUS_0", 0, 0, &umr_bitfield_default },
+	 { "TXPHYSTATUS_1", 1, 1, &umr_bitfield_default },
+	 { "TXPHYSTATUS_2", 2, 2, &umr_bitfield_default },
+	 { "TXPHYSTATUS_3", 3, 3, &umr_bitfield_default },
+	 { "TXPHYSTATUS_4", 4, 4, &umr_bitfield_default },
+	 { "TXPHYSTATUS_5", 5, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_6", 6, 6, &umr_bitfield_default },
+	 { "TXPHYSTATUS_7", 7, 7, &umr_bitfield_default },
+	 { "TXPHYSTATUS_8", 8, 8, &umr_bitfield_default },
+	 { "TXPHYSTATUS_9", 9, 9, &umr_bitfield_default },
+	 { "TXPHYSTATUS_10", 10, 10, &umr_bitfield_default },
+	 { "TXPHYSTATUS_11", 11, 11, &umr_bitfield_default },
+	 { "TXPHYSTATUS_12", 12, 12, &umr_bitfield_default },
+	 { "TXPHYSTATUS_13", 13, 13, &umr_bitfield_default },
+	 { "TXPHYSTATUS_14", 14, 14, &umr_bitfield_default },
+	 { "TXPHYSTATUS_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SC_CTL[] = {
+	 { "SC_CALIBRATION", 0, 0, &umr_bitfield_default },
+	 { "SC_RXDETECT", 1, 1, &umr_bitfield_default },
+	 { "SC_EXIT_L1_TO_L0S", 2, 2, &umr_bitfield_default },
+	 { "SC_EXIT_L1_TO_L0", 3, 3, &umr_bitfield_default },
+	 { "SC_ENTER_L1_FROM_L0S", 4, 4, &umr_bitfield_default },
+	 { "SC_ENTER_L1_FROM_L0", 5, 5, &umr_bitfield_default },
+	 { "SC_SPEED_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "SC_PHASE_1", 8, 8, &umr_bitfield_default },
+	 { "SC_PHASE_2", 9, 9, &umr_bitfield_default },
+	 { "SC_PHASE_3", 10, 10, &umr_bitfield_default },
+	 { "SC_PHASE_4", 11, 11, &umr_bitfield_default },
+	 { "SC_PHASE_5", 12, 12, &umr_bitfield_default },
+	 { "SC_PHASE_6", 13, 13, &umr_bitfield_default },
+	 { "SC_PHASE_7", 14, 14, &umr_bitfield_default },
+	 { "SC_PHASE_8", 15, 15, &umr_bitfield_default },
+	 { "SC_LANE_0_RESUME", 16, 16, &umr_bitfield_default },
+	 { "SC_LANE_1_RESUME", 17, 17, &umr_bitfield_default },
+	 { "SC_LANE_2_RESUME", 18, 18, &umr_bitfield_default },
+	 { "SC_LANE_3_RESUME", 19, 19, &umr_bitfield_default },
+	 { "SC_LANE_4_RESUME", 20, 20, &umr_bitfield_default },
+	 { "SC_LANE_5_RESUME", 21, 21, &umr_bitfield_default },
+	 { "SC_LANE_6_RESUME", 22, 22, &umr_bitfield_default },
+	 { "SC_LANE_7_RESUME", 23, 23, &umr_bitfield_default },
+	 { "SC_LANE_8_RESUME", 24, 24, &umr_bitfield_default },
+	 { "SC_LANE_9_RESUME", 25, 25, &umr_bitfield_default },
+	 { "SC_LANE_10_RESUME", 26, 26, &umr_bitfield_default },
+	 { "SC_LANE_11_RESUME", 27, 27, &umr_bitfield_default },
+	 { "SC_LANE_12_RESUME", 28, 28, &umr_bitfield_default },
+	 { "SC_LANE_13_RESUME", 29, 29, &umr_bitfield_default },
+	 { "SC_LANE_14_RESUME", 30, 30, &umr_bitfield_default },
+	 { "SC_LANE_15_RESUME", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PWRDOWN_2[] = {
+	 { "TX_POWER_STATE_IN_TXS2_2", 0, 2, &umr_bitfield_default },
+	 { "FORCE_RXEN_IN_L0s_2", 3, 3, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_2", 4, 6, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_2", 7, 9, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_2", 10, 12, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_2", 16, 16, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_2", 24, 26, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_2", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_2", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PWRDOWN_3[] = {
+	 { "TX_POWER_STATE_IN_TXS2_3", 0, 2, &umr_bitfield_default },
+	 { "FORCE_RXEN_IN_L0s_3", 3, 3, &umr_bitfield_default },
+	 { "RX_POWER_STATE_IN_RXS2_3", 4, 6, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_TXS2_3", 7, 9, &umr_bitfield_default },
+	 { "PLL_POWER_STATE_IN_OFF_3", 10, 12, &umr_bitfield_default },
+	 { "TX2P5CLK_CLOCK_GATING_EN_3", 16, 16, &umr_bitfield_default },
+	 { "PLL_RAMP_UP_TIME_3", 24, 26, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_EN_3", 28, 28, &umr_bitfield_default },
+	 { "PLLPWR_OVERRIDE_VAL_3", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SC_CTL2[] = {
+	 { "SERIAL_CFG_PERLANE_DISABLE_0", 0, 0, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_1", 1, 1, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_2", 2, 2, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_3", 3, 3, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_4", 4, 4, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_5", 5, 5, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_6", 6, 6, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_7", 7, 7, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_8", 8, 8, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_9", 9, 9, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_10", 10, 10, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_11", 11, 11, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_12", 12, 12, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_13", 13, 13, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_14", 14, 14, &umr_bitfield_default },
+	 { "SERIAL_CFG_PERLANE_DISABLE_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PRG0[] = {
+	 { "PRG_RXDETECT_SAMPL_TIME", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PRG1[] = {
+	 { "PRG_PLL_RAMP_UP_TIME", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PRG2[] = {
+	 { "PRG_SERVICE2_STEP4_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PRG3[] = {
+	 { "PRG_SERVICE3_STEP4_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PRG4[] = {
+	 { "PRG_SPEEDCHANGE_STEP2_DELAY", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PRG5[] = {
+	 { "PRG_LS2_EXIT_TIME", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_0[] = {
+	 { "TX_PDNB_OVERRIDE_EN_0", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_0", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_0", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_0", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_0", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_0", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_0", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_0", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_0", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_0", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_1[] = {
+	 { "TX_PDNB_OVERRIDE_EN_1", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_1", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_1", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_1", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_1", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_1", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_1", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_1", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_1", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_1", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_2[] = {
+	 { "TX_PDNB_OVERRIDE_EN_2", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_2", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_2", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_2", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_2", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_2", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_2", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_2", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_2", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_2", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_3[] = {
+	 { "TX_PDNB_OVERRIDE_EN_3", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_3", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_3", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_3", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_3", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_3", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_3", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_3", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_3", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_3", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_4[] = {
+	 { "TX_PDNB_OVERRIDE_EN_4", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_4", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_4", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_4", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_4", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_4", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_4", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_4", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_4", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_4", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_5[] = {
+	 { "TX_PDNB_OVERRIDE_EN_5", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_5", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_5", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_5", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_5", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_5", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_5", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_5", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_5", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_5", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_6[] = {
+	 { "TX_PDNB_OVERRIDE_EN_6", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_6", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_6", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_6", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_6", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_6", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_6", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_6", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_6", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_6", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_7[] = {
+	 { "TX_PDNB_OVERRIDE_EN_7", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_7", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_7", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_7", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_7", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_7", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_7", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_7", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_7", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_7", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_0[] = {
+	 { "SEQ_CALIBRATION_0", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_0", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_0", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_0", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_0", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_0", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_0", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_0", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_1[] = {
+	 { "SEQ_CALIBRATION_1", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_1", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_1", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_1", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_1", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_1", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_1", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_1", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_2[] = {
+	 { "SEQ_CALIBRATION_2", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_2", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_2", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_2", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_2", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_2", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_2", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_3[] = {
+	 { "SEQ_CALIBRATION_3", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_3", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_3", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_3", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_3", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_3", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_3", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_3", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_4[] = {
+	 { "SEQ_CALIBRATION_4", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_4", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_4", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_4", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_4", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_4", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_4", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_4", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_5[] = {
+	 { "SEQ_CALIBRATION_5", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_5", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_5", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_5", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_5", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_5", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_5", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_5", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_6[] = {
+	 { "SEQ_CALIBRATION_6", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_6", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_6", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_6", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_6", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_6", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_6", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_6", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_7[] = {
+	 { "SEQ_CALIBRATION_7", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_7", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_7", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_7", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_7", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_7", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_7", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_7", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_8[] = {
+	 { "TX_PDNB_OVERRIDE_EN_8", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_8", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_8", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_8", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_8", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_8", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_8", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_8", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_8", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_8", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_9[] = {
+	 { "TX_PDNB_OVERRIDE_EN_9", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_9", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_9", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_9", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_9", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_9", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_9", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_9", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_9", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_9", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_10[] = {
+	 { "TX_PDNB_OVERRIDE_EN_10", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_10", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_10", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_10", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_10", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_10", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_10", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_10", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_10", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_10", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_11[] = {
+	 { "TX_PDNB_OVERRIDE_EN_11", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_11", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_11", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_11", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_11", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_11", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_11", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_11", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_11", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_11", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_12[] = {
+	 { "TX_PDNB_OVERRIDE_EN_12", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_12", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_12", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_12", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_12", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_12", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_12", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_12", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_12", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_12", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_13[] = {
+	 { "TX_PDNB_OVERRIDE_EN_13", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_13", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_13", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_13", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_13", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_13", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_13", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_13", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_13", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_13", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_14[] = {
+	 { "TX_PDNB_OVERRIDE_EN_14", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_14", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_14", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_14", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_14", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_14", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_14", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_14", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_14", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_14", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_PDNB_OVERRIDE_15[] = {
+	 { "TX_PDNB_OVERRIDE_EN_15", 0, 0, &umr_bitfield_default },
+	 { "TX_PDNB_OVERRIDE_VAL_15", 1, 3, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_EN_15", 4, 4, &umr_bitfield_default },
+	 { "RX_PDNB_OVERRIDE_VAL_15", 5, 7, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_EN_15", 8, 8, &umr_bitfield_default },
+	 { "RXEN_OVERRIDE_VAL_15", 9, 9, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_EN_15", 10, 10, &umr_bitfield_default },
+	 { "TXPWR_OVERRIDE_VAL_15", 11, 13, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_EN_15", 14, 14, &umr_bitfield_default },
+	 { "RXPWR_OVERRIDE_VAL_15", 15, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_8[] = {
+	 { "SEQ_CALIBRATION_8", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_8", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_8", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_8", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_8", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_8", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_8", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_8", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_9[] = {
+	 { "SEQ_CALIBRATION_9", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_9", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_9", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_9", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_9", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_9", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_9", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_9", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_10[] = {
+	 { "SEQ_CALIBRATION_10", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_10", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_10", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_10", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_10", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_10", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_10", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_10", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_11[] = {
+	 { "SEQ_CALIBRATION_11", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_11", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_11", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_11", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_11", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_11", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_11", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_11", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_12[] = {
+	 { "SEQ_CALIBRATION_12", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_12", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_12", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_12", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_12", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_12", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_12", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_12", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_13[] = {
+	 { "SEQ_CALIBRATION_13", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_13", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_13", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_13", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_13", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_13", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_13", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_13", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_14[] = {
+	 { "SEQ_CALIBRATION_14", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_14", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_14", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_14", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_14", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_14", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_14", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_14", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SEQ_STATUS_15[] = {
+	 { "SEQ_CALIBRATION_15", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RXDETECT_15", 1, 1, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0S_15", 2, 2, &umr_bitfield_default },
+	 { "SEQ_EXIT_L1_TO_L0_15", 3, 3, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0S_15", 4, 4, &umr_bitfield_default },
+	 { "SEQ_ENTER_L1_FROM_L0_15", 5, 5, &umr_bitfield_default },
+	 { "SEQ_SPEED_CHANGE_15", 6, 6, &umr_bitfield_default },
+	 { "SEQ_PHASE_15", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 0, 0, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 1, 1, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 2, 2, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 3, 3, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 4, 4, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG0[] = {
+	 { "BACKUP", 0, 15, &umr_bitfield_default },
+	 { "CFG_IDLEDET_TH", 16, 17, &umr_bitfield_default },
+	 { "DBG_RX2TXBYP_SEL", 20, 22, &umr_bitfield_default },
+	 { "DBG_RXFEBYP_EN", 23, 23, &umr_bitfield_default },
+	 { "DBG_RXPRBS_CLR", 24, 24, &umr_bitfield_default },
+	 { "DBG_RXTOGGLE_EN", 25, 25, &umr_bitfield_default },
+	 { "DBG_TX2RXLBACK_EN", 26, 26, &umr_bitfield_default },
+	 { "TXCFG_CMGOOD_RANGE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG1[] = {
+	 { "RXDBG_CDR_FR_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_CDR_FR_BYP_VAL", 1, 6, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_EN", 7, 7, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_VAL", 8, 13, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_EN", 14, 14, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_VAL", 15, 21, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_VAL", 23, 29, &umr_bitfield_default },
+	 { "TST_LOSPDTST_EN", 30, 30, &umr_bitfield_default },
+	 { "PLL_CFG_DISPCLK_DIV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG2[] = {
+	 { "RXDBG_D2TH_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_D2TH_BYP_VAL", 1, 7, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_EN", 8, 8, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_VAL", 9, 15, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_EN", 16, 16, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_VAL", 17, 23, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_EN", 24, 24, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_VAL", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG3[] = {
+	 { "RXDBG_SEL", 0, 4, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF0_SEL", 5, 6, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF1_SEL", 7, 8, &umr_bitfield_default },
+	 { "BG_CFG_RO_REG_VREF_SEL", 9, 10, &umr_bitfield_default },
+	 { "BG_DBG_VREFBYP_EN", 11, 11, &umr_bitfield_default },
+	 { "BG_DBG_IREFBYP_EN", 12, 12, &umr_bitfield_default },
+	 { "BG_DBG_ANALOG_SEL", 14, 16, &umr_bitfield_default },
+	 { "DBG_DLL_CLK_SEL", 18, 20, &umr_bitfield_default },
+	 { "PLL_DISPCLK_CMOS_SEL", 21, 21, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_VAL", 23, 26, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_EN", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_VAL", 28, 30, &umr_bitfield_default },
+	 { "DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG4[] = {
+	 { "DBG_RXAPU_INST", 0, 15, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_VAL", 16, 17, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_EN", 18, 18, &umr_bitfield_default },
+	 { "DBG_RXAPU_EXEC", 22, 25, &umr_bitfield_default },
+	 { "DBG_RXDLL_VREG_REF_SEL", 26, 26, &umr_bitfield_default },
+	 { "PWRGOOD_OVRD", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXRDATA_GATING_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG5[] = {
+	 { "DBG_RXAPU_MODE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_ALL_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_ALL_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_IMPCAL_ACTIVE_SCI_UPDT", 4, 4, &umr_bitfield_default },
+	 { "TXNIMP", 8, 11, &umr_bitfield_default },
+	 { "TXPIMP", 12, 15, &umr_bitfield_default },
+	 { "RXIMP", 16, 19, &umr_bitfield_default },
+	 { "IMPCAL_ACTIVE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG1[] = {
+	 { "IGNR_MODE_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L0T3", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L0T3", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_0", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_1", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_2", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_3", 15, 15, &umr_bitfield_default },
+	 { "MODE_0", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_0", 18, 19, &umr_bitfield_default },
+	 { "MODE_1", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_1", 22, 23, &umr_bitfield_default },
+	 { "MODE_2", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_2", 26, 27, &umr_bitfield_default },
+	 { "MODE_3", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG2[] = {
+	 { "IGNR_MODE_SCI_UPDT_L4T7", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L4T7", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_4", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_5", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_6", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_7", 15, 15, &umr_bitfield_default },
+	 { "MODE_4", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_4", 18, 19, &umr_bitfield_default },
+	 { "MODE_5", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_5", 22, 23, &umr_bitfield_default },
+	 { "MODE_6", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_6", 26, 27, &umr_bitfield_default },
+	 { "MODE_7", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_7", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG3[] = {
+	 { "IGNR_MODE_SCI_UPDT_L8T11", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L8T11", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_8", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_9", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_10", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_11", 15, 15, &umr_bitfield_default },
+	 { "MODE_8", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_8", 18, 19, &umr_bitfield_default },
+	 { "MODE_9", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_9", 22, 23, &umr_bitfield_default },
+	 { "MODE_10", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_10", 26, 27, &umr_bitfield_default },
+	 { "MODE_11", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_11", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG4[] = {
+	 { "IGNR_MODE_SCI_UPDT_L12T15", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_SCI_UPDT_L12T15", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_SCI_UPDT_L12T15", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_12", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_13", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_14", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_15", 15, 15, &umr_bitfield_default },
+	 { "MODE_12", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_12", 18, 19, &umr_bitfield_default },
+	 { "MODE_13", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_13", 22, 23, &umr_bitfield_default },
+	 { "MODE_14", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_14", 26, 27, &umr_bitfield_default },
+	 { "MODE_15", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_OVRD_REG0[] = {
+	 { "TXPDTERM_VAL_OVRD_VAL", 0, 15, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_OVRD_REG1[] = {
+	 { "TXPDTERM_VAL_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_VAL", 3, 3, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_EN", 15, 15, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_OVRD_REG2[] = {
+	 { "BG_PWRON_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "BG_PWRON_OVRD_VAL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_HW_DEBUG[] = {
+	 { "PB1_HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "PB1_HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "PB1_HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "PB1_HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "PB1_HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "PB1_HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "PB1_HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "PB1_HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "PB1_HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "PB1_HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "PB1_HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "PB1_HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "PB1_HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "PB1_HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "PB1_HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "PB1_HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "PB1_HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "PB1_HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "PB1_HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "PB1_HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "PB1_HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "PB1_HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "PB1_HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "PB1_HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "PB1_HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "PB1_HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "PB1_HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "PB1_HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "PB1_HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "PB1_HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "PB1_HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "PB1_HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_GLB_REG0[] = {
+	 { "STRAP_QUICK_SIM_START", 1, 1, &umr_bitfield_default },
+	 { "STRAP_DFT_RXBSCAN_EN_VAL", 2, 2, &umr_bitfield_default },
+	 { "STRAP_DFT_CALIB_BYPASS", 3, 3, &umr_bitfield_default },
+	 { "STRAP_CFG_IDLEDET_TH", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL", 7, 11, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_OVR_PWRSF", 12, 12, &umr_bitfield_default },
+	 { "STRAP_RX_TRK_MODE_0_", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PWRGOOD_OVRD", 14, 14, &umr_bitfield_default },
+	 { "STRAP_DBG_RXDLL_VREG_REF_SEL", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_LC_VCO_TUNE", 16, 19, &umr_bitfield_default },
+	 { "STRAP_DBG_RXRDATA_GATING_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "STRAP_DBG_RXPI_OFFSET_BYP_VAL", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_TX_REG0[] = {
+	 { "STRAP_TX_CFG_DRV0_EN", 1, 4, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV0_TAP_SEL", 5, 8, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV1_EN", 9, 13, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV1_TAP_SEL", 14, 18, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV2_EN", 19, 22, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV2_TAP_SEL", 23, 26, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRVX_EN", 27, 27, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRVX_TAP_SEL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_RX_TRK_MODE_1_", 29, 29, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_SWING_BOOST_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_RX_REG0[] = {
+	 { "STRAP_RX_CFG_TH_LOOP_GAIN", 1, 4, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_DLL_FLOCK_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "STRAP_DBG_RXPI_OFFSET_BYP_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_LC_REG_VREF0_SEL", 8, 9, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_LC_REG_VREF1_SEL", 10, 11, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_CDR_TIME", 12, 15, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_FOM_TIME", 16, 19, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_TIME", 20, 23, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_OC_TIME", 24, 27, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_RPTR_RST_VAL", 28, 30, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_TERM_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_RX_REG1[] = {
+	 { "STRAP_RX_CFG_CDR_PI_STPSZ", 1, 1, &umr_bitfield_default },
+	 { "STRAP_TX_DEEMPH_PRSHT_STNG", 2, 4, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_RO_REG_VREF_SEL", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_POLE_BYP_DIS", 7, 7, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_POLE_BYP_VAL", 8, 10, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_CDR_PH_GAIN", 11, 14, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_ADAPT_MODE", 15, 24, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_DFE_TIME", 25, 28, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_LOOP_GAIN", 29, 30, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_SHUNT_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_PLL_REG0[] = {
+	 { "STRAP_PLL_CFG_LC_BW_CNTRL", 1, 3, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_LC_LF_CNTRL", 4, 12, &umr_bitfield_default },
+	 { "STRAP_TX_RXDET_X1_SSF", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_RO_BW_CNTRL", 16, 23, &umr_bitfield_default },
+	 { "STRAP_PLL_STRAP_SEL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_PIN_REG0[] = {
+	 { "STRAP_TX_DEEMPH_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_TX_FULL_SWING", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_JIT_INJ_REG0[] = {
+	 { "DFT_NUM_STEPS", 0, 5, &umr_bitfield_default },
+	 { "DFT_DISABLE_ERR", 7, 7, &umr_bitfield_default },
+	 { "DFT_CLK_PER_STEP", 8, 11, &umr_bitfield_default },
+	 { "DFT_MODE_CDR_EN", 20, 20, &umr_bitfield_default },
+	 { "DFT_EN_RECOVERY", 21, 21, &umr_bitfield_default },
+	 { "DFT_INCR_SWP_EN", 22, 22, &umr_bitfield_default },
+	 { "DFT_DECR_SWP_EN", 23, 23, &umr_bitfield_default },
+	 { "DFT_RECOVERY_TIME", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_JIT_INJ_REG1[] = {
+	 { "DFT_BYPASS_VALUE", 0, 7, &umr_bitfield_default },
+	 { "DFT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "DFT_BLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DFT_NUM_OF_TESTS", 17, 19, &umr_bitfield_default },
+	 { "DFT_CHECK_TIME", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_JIT_INJ_REG2[] = {
+	 { "DFT_LANE_EN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_DEBUG_CTRL_REG0[] = {
+	 { "DFT_PHY_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DFT_PHY_DEBUG_MODE", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_JIT_INJ_STAT_REG0[] = {
+	 { "DFT_STAT_DECR", 0, 7, &umr_bitfield_default },
+	 { "DFT_STAT_INCR", 8, 15, &umr_bitfield_default },
+	 { "DFT_STAT_FINISHED", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO_GLB_CTRL_REG0[] = {
+	 { "PLL_TST_LOSPDTST_SRC", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 2, 2, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 3, 3, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 4, 4, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 5, 5, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 6, 6, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_LUT_ENTRY_LS2", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_LUT_ENTRY_LS2", 8, 8, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 9, 9, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 10, 10, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 11, 11, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 12, 12, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 13, 13, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 14, 14, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_LEFT_EN_GATING_EN", 16, 16, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_RIGHT_EN_GATING_EN", 17, 17, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_LEFT_EN_GATING_EN", 18, 18, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_RIGHT_EN_GATING_EN", 19, 19, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_LEFT_EN_GATING_EN", 20, 20, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_RIGHT_EN_GATING_EN", 21, 21, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_LEFT_EN_GATING_EN", 22, 22, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_RIGHT_EN_GATING_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO0_CTRL_REG0[] = {
+	 { "PLL_DBG_RO_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_RO_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_DBG_RO_LF_CNTRL_0", 4, 10, &umr_bitfield_default },
+	 { "PLL_TST_RO_USAMPLE_EN_0", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO0_OVRD_REG0[] = {
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0", 0, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0", 9, 11, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_VAL_0", 15, 27, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0", 30, 30, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO0_OVRD_REG1[] = {
+	 { "PLL_CFG_RO_REFDIV_OVRD_VAL_0", 0, 4, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFDIV_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_VAL_0", 6, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0", 11, 11, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0", 19, 21, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO0_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO0_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO0_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO0_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO1_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO1_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO1_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO1_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO2_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO2_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO2_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO2_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO3_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO3_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO3_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO3_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC0_CTRL_REG0[] = {
+	 { "PLL_DBG_LC_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_LC_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_TST_LC_USAMPLE_EN_0", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC0_OVRD_REG0[] = {
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0", 4, 6, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_VAL_0", 10, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0", 19, 27, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_VAL_0", 29, 30, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC0_OVRD_REG1[] = {
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0", 14, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC0_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC0_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC0_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_LC0_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC1_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC1_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC1_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_LC1_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC2_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC2_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC2_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_LC2_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC3_IGNR_PLLPWR_SCI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC3_IGNR_FREQMODE_SCI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_LC3_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_LC3_FREQMODE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG0[] = {
+	 { "RX_CFG_ADAPT_MODE_GEN1", 0, 9, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN2", 10, 19, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN3", 20, 29, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_RST_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG1[] = {
+	 { "RX_CFG_CDR_FR_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN1", 24, 24, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN2", 25, 25, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN3", 26, 26, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_ASRT_TO_DCLK_EN", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG2[] = {
+	 { "RX_CFG_CDR_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN1", 24, 25, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN2", 26, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN3", 28, 29, &umr_bitfield_default },
+	 { "RX_DCLK_EN_ASRT_TO_ADAPT_HLD", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG3[] = {
+	 { "RX_CFG_CDR_FR_EN_GEN1", 0, 0, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN2", 1, 1, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN3", 2, 2, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG4[] = {
+	 { "RX_CFG_FOM_BER_GEN1", 0, 2, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN2", 3, 5, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN3", 6, 8, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN1", 9, 11, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN2", 12, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN3", 15, 17, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG5[] = {
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1", 0, 4, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2", 5, 9, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3", 10, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN1", 15, 15, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN2", 16, 16, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN3", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN1", 18, 18, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN2", 19, 19, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN3", 20, 20, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_FORCE_DLL_RST_RXPWR_LS2OFF_TO_LS0", 30, 30, &umr_bitfield_default },
+	 { "RX_ADAPT_AUX_PWRON_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG6[] = {
+	 { "RX_CFG_LEQ_TIME_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0", 24, 24, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS2", 26, 26, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_LUT_ENTRY_LS2", 27, 27, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG7[] = {
+	 { "RX_CFG_TH_LOOP_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS2", 13, 13, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_LUT_ENTRY_LS2", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN1", 18, 20, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN2", 21, 23, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN3", 24, 26, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN3", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG8[] = {
+	 { "RX_DLL_LOCK_TIME", 0, 1, &umr_bitfield_default },
+	 { "RX_DLL_SPEEDCHANGE_RESET_TIME", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_RXPWR_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_RXPWR_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L0T3", 4, 4, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L4T7", 5, 5, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L8T11", 6, 6, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_SCI_UPDT_L12T15", 7, 7, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_RXPRESETHINT_SCI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_SCI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L0T3", 16, 16, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L4T7", 17, 17, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L8T11", 18, 18, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_SCI_UPDT_L12T15", 19, 19, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L0T3", 20, 20, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L4T7", 21, 21, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L8T11", 22, 22, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_SCI_UPDT_L12T15", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_OVRD_REG0[] = {
+	 { "RX_ADAPT_HLD_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_VAL", 6, 7, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_VAL", 15, 15, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_VAL", 17, 17, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_EN", 18, 18, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_VAL", 19, 19, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_EN", 20, 20, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_VAL", 21, 21, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_EN", 22, 22, &umr_bitfield_default },
+	 { "RX_TERM_EN_OVRD_VAL", 23, 23, &umr_bitfield_default },
+	 { "RX_TERM_EN_OVRD_EN", 24, 24, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_OVRD_REG1[] = {
+	 { "RX_ADAPT_TRK_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_TRK_OVRD_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE0_CTRL_REG0[] = {
+	 { "RX_BACKUP_0", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_0", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_0", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_0", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_0", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_0", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE1_CTRL_REG0[] = {
+	 { "RX_BACKUP_1", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_1", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_1", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_1", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_1", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_1", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_1", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE2_CTRL_REG0[] = {
+	 { "RX_BACKUP_2", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_2", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_2", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_2", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_2", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_2", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_2", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE3_CTRL_REG0[] = {
+	 { "RX_BACKUP_3", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_3", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_3", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_3", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_3", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_3", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_3", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE4_CTRL_REG0[] = {
+	 { "RX_BACKUP_4", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_4", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_4", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_4", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_4", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_4", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_4", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE5_CTRL_REG0[] = {
+	 { "RX_BACKUP_5", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_5", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_5", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_5", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_5", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_5", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_5", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE6_CTRL_REG0[] = {
+	 { "RX_BACKUP_6", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_6", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_6", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_6", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_6", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_6", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_6", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE7_CTRL_REG0[] = {
+	 { "RX_BACKUP_7", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_7", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_7", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_7", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_7", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_7", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_7", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE8_CTRL_REG0[] = {
+	 { "RX_BACKUP_8", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_8", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_8", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_8", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_8", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_8", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_8", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_8", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_8", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_8", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE9_CTRL_REG0[] = {
+	 { "RX_BACKUP_9", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_9", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_9", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_9", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_9", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_9", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_9", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_9", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_9", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_9", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE10_CTRL_REG0[] = {
+	 { "RX_BACKUP_10", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_10", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_10", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_10", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_10", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_10", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_10", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_10", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_10", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_10", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE11_CTRL_REG0[] = {
+	 { "RX_BACKUP_11", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_11", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_11", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_11", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_11", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_11", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_11", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_11", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_11", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_11", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE12_CTRL_REG0[] = {
+	 { "RX_BACKUP_12", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_12", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_12", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_12", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_12", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_12", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_12", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_12", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_12", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_12", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE13_CTRL_REG0[] = {
+	 { "RX_BACKUP_13", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_13", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_13", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_13", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_13", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_13", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_13", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_13", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_13", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_13", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE14_CTRL_REG0[] = {
+	 { "RX_BACKUP_14", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_14", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_14", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_14", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_14", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_14", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_14", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_14", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_14", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_14", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE15_CTRL_REG0[] = {
+	 { "RX_BACKUP_15", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_15", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_15", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_15", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_15", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_15", 3, 3, &umr_bitfield_default },
+	 { "RXPRESETHINT_15", 4, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_15", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_15", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_15", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_CTRL_REG0[] = {
+	 { "TX_DRV_DATA_ASRT_DLY_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_DSRT_DLY_VAL", 3, 5, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN1", 8, 10, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN2", 11, 13, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN3", 14, 16, &umr_bitfield_default },
+	 { "TX_STAGGER_CTRL", 17, 18, &umr_bitfield_default },
+	 { "TX_DATA_CLK_GATING", 19, 19, &umr_bitfield_default },
+	 { "TX_PRESET_TABLE_BYPASS", 20, 20, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_EN", 21, 21, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_DIR_VER", 22, 22, &umr_bitfield_default },
+	 { "TX_DCLK_EN_LSX_ALWAYS_ON", 23, 23, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_IN_OFF", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_LANE_SKEW_CTRL[] = {
+	 { "TX_CFG_GROUPX1_EN_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_6", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_7", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_8", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_9", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_10", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_11", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_12", 12, 12, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_13", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_14", 14, 14, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_15", 15, 15, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L0T1", 16, 16, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L2T3", 17, 17, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L4T5", 18, 18, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L6T7", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L8T9", 20, 20, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L10T11", 21, 21, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L12T13", 22, 22, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L14T15", 23, 23, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L0T3", 24, 24, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L4T7", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L8T11", 26, 26, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L12T15", 27, 27, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L0T7", 28, 28, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L8T15", 29, 29, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_L0T15", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_TXPWR_SCI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_TXPWR_SCI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L0T3", 4, 4, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L4T7", 5, 5, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L8T11", 6, 6, &umr_bitfield_default },
+	 { "IGNR_INCOHERENTCK_SCI_UPDT_L12T15", 7, 7, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_SCI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_SCI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0[] = {
+	 { "ACCEPT_ENTRY_0", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_1", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_2", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_3", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_4", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_5", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_6", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_7", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_8", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_9", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_10", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_11", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_12", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_13", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_14", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_15", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_16", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_17", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_18", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_19", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_20", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_21", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_22", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_23", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_24", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_25", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_26", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_27", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_28", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_29", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_30", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_31", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1[] = {
+	 { "ACCEPT_ENTRY_32", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_33", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_34", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_35", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_36", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_37", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_38", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_39", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_40", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_41", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_42", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_43", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_44", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_45", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_46", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_47", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_48", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_49", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_50", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_51", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_52", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_53", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_54", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_55", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_56", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_57", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_58", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_59", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_60", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_61", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_62", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_63", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2[] = {
+	 { "ACCEPT_ENTRY_64", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_65", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_66", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_67", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_68", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_69", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_70", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_71", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_72", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_73", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_74", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_75", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_76", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_77", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_78", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_79", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_80", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_81", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_82", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_83", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_84", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_85", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_86", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_87", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_88", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_89", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_90", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_91", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_92", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_93", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_94", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_95", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3[] = {
+	 { "ACCEPT_ENTRY_96", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_97", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_98", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_99", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_100", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_101", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_102", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_103", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_104", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_105", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_106", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_107", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_108", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_109", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG0[] = {
+	 { "TX_CFG_DCLK_DIV_OVRD_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_CFG_DCLK_DIV_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN1_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL", 9, 12, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_OVRD_EN", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN1_OVRD_VAL", 14, 18, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_OVRD_EN", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN1_OVRD_VAL", 26, 29, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_OVRD_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG1[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_OVRD_EN", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN1_OVRD_VAL", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_OVRD_EN", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_VAL", 15, 24, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_VAL", 26, 26, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_EN", 27, 27, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG2[] = {
+	 { "TX_WRITE_EN_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "TX_WRITE_EN_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_EN", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_VAL", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_EN", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_EN", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_VAL", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_EN", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN2_OVRD_VAL", 12, 15, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL", 16, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN2_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG3[] = {
+	 { "TX_CFG_DRV2_EN_GEN2_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN2_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN3_OVRD_VAL", 10, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL", 14, 17, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN3_OVRD_VAL", 18, 22, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL", 23, 27, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN3_OVRD_VAL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG4[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN3_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE0_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_0", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_0", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE0_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_0", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_0", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_0", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_0", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_0", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE1_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_1", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_1", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE1_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_1", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_1", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_1", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_1", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_1", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_1", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_1", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE2_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_2", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_2", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE2_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_2", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_2", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_2", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_2", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_2", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_2", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_2", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_2", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE3_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_3", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_3", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_3", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE3_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_3", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_3", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_3", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_3", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_3", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_3", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_3", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE4_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_4", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_4", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_4", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE4_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_4", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_4", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_4", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_4", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_4", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_4", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_4", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE5_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_5", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_5", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_5", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE5_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_5", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_5", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_5", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_5", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_5", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_5", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_5", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_5", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE6_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_6", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_6", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_6", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE6_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_6", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_6", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_6", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_6", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_6", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_6", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_6", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_6", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE7_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_7", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_7", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_7", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE7_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_7", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_7", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_7", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_7", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_7", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_7", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_7", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_7", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE8_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_8", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_8", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_8", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE8_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_8", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_8", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_8", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_8", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_8", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_8", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_8", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_8", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_8", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_8", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_8", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_8", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_8", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE9_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_9", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_9", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_9", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE9_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_9", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_9", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_9", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_9", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_9", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_9", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_9", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_9", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_9", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_9", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_9", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_9", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_9", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE10_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_10", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_10", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_10", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE10_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_10", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_10", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_10", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_10", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_10", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_10", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_10", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_10", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_10", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_10", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_10", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_10", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_10", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE11_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_11", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_11", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_11", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE11_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_11", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_11", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_11", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_11", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_11", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_11", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_11", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_11", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_11", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_11", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_11", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_11", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_11", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE12_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_12", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_12", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_12", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE12_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_12", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_12", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_12", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_12", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_12", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_12", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_12", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_12", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_12", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_12", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_12", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_12", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_12", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE13_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_13", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_13", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_13", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE13_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_13", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_13", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_13", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_13", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_13", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_13", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_13", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_13", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_13", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_13", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_13", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_13", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_13", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE14_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_14", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_14", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_14", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE14_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_14", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_14", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_14", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_14", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_14", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_14", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_14", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_14", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_14", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_14", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_14", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_14", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_14", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE15_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_15", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_15", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_15", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE15_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_15", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_15", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_15", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_15", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_15", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_15", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_15", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_15", 0, 2, &umr_bitfield_default },
+	 { "INCOHERENTCK_15", 3, 3, &umr_bitfield_default },
+	 { "TXMARG_15", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_15", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_15", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_15", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_SNOOP_REG[] = {
+	 { "REG_SNOOP_ARBITER", 0, 0, &umr_bitfield_default },
+	 { "REG_SNOOP_ALLMASTER", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLATENCY[] = {
+	 { "LATENCY_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHEADER[] = {
+	 { "HEADER_TYPE", 0, 6, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIST[] = {
+	 { "BIST_COMP", 0, 3, &umr_bitfield_default },
+	 { "BIST_STRT", 6, 6, &umr_bitfield_default },
+	 { "BIST_CAP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_1[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_2[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_0[] = {
+	 { "BIOS_SCRATCH_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_1[] = {
+	 { "BIOS_SCRATCH_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_2[] = {
+	 { "BIOS_SCRATCH_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_3[] = {
+	 { "BIOS_SCRATCH_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_4[] = {
+	 { "BIOS_SCRATCH_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_5[] = {
+	 { "BIOS_SCRATCH_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_6[] = {
+	 { "BIOS_SCRATCH_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_7[] = {
+	 { "BIOS_SCRATCH_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_8[] = {
+	 { "BIOS_SCRATCH_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_9[] = {
+	 { "BIOS_SCRATCH_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_10[] = {
+	 { "BIOS_SCRATCH_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_11[] = {
+	 { "BIOS_SCRATCH_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_12[] = {
+	 { "BIOS_SCRATCH_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_13[] = {
+	 { "BIOS_SCRATCH_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_14[] = {
+	 { "BIOS_SCRATCH_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_15[] = {
+	 { "BIOS_SCRATCH_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_INDEX_HI[] = {
+	 { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_4[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_5[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR1_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR1_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR2_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR2_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR3_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR3_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR4_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR4_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR5_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR5_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR6_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR6_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_6[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_DATA_SELECT[] = {
+	 { "DATA_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_DATA[] = {
+	 { "BASE_POWER", 0, 7, &umr_bitfield_default },
+	 { "DATA_SCALE", 8, 9, &umr_bitfield_default },
+	 { "PM_SUB_STATE", 10, 12, &umr_bitfield_default },
+	 { "PM_STATE", 13, 14, &umr_bitfield_default },
+	 { "TYPE", 15, 17, &umr_bitfield_default },
+	 { "POWER_RAIL", 18, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_CAP[] = {
+	 { "SYSTEM_ALLOCATED", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_CAP[] = {
+	 { "SUBSTATE_MAX", 0, 4, &umr_bitfield_default },
+	 { "TRANS_LAT_UNIT", 8, 9, &umr_bitfield_default },
+	 { "PWR_ALLOC_SCALE", 12, 13, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_0", 16, 23, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_LATENCY_INDICATOR[] = {
+	 { "TRANS_LAT_INDICATOR_BITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_STATUS[] = {
+	 { "SUBSTATE_STATUS", 0, 4, &umr_bitfield_default },
+	 { "SUBSTATE_CNTL_ENABLED", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_CNTL[] = {
+	 { "SUBSTATE_CNTL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_CNTL[] = {
+	 { "STU", 0, 4, &umr_bitfield_default },
+	 { "ATC_ENABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_CAP[] = {
+	 { "INVALIDATE_Q_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "PAGE_ALIGNED_REQUEST", 5, 5, &umr_bitfield_default },
+	 { "GLOBAL_INVALIDATE_SUPPORTED", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmADAPTER_ID[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_STATUS[] = {
+	 { "RESPONSE_FAILURE", 0, 0, &umr_bitfield_default },
+	 { "UNEXPECTED_PAGE_REQ_GRP_INDEX", 1, 1, &umr_bitfield_default },
+	 { "STOPPED", 8, 8, &umr_bitfield_default },
+	 { "PRG_RESPONSE_PASID_REQUIRED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_CNTL[] = {
+	 { "PRI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRI_RESET", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[] = {
+	 { "OUTSTAND_PAGE_REQ_CAPACITY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[] = {
+	 { "OUTSTAND_PAGE_REQ_ALLOC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_CNTL[] = {
+	 { "PASID_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PASID_EXE_PERMISSION_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "PASID_PRIV_MODE_SUPPORTED_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_CAP[] = {
+	 { "PASID_EXE_PERMISSION_SUPPORTED", 1, 1, &umr_bitfield_default },
+	 { "PASID_PRIV_MODE_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "MAX_PASID_WIDTH", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_CAP[] = {
+	 { "TPH_REQR_NO_ST_MODE_SUPPORTED", 0, 0, &umr_bitfield_default },
+	 { "TPH_REQR_INT_VEC_MODE_SUPPORTED", 1, 1, &umr_bitfield_default },
+	 { "TPH_REQR_DEV_SPC_MODE_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "TPH_REQR_EXTND_TPH_REQR_SUPPORED", 8, 8, &umr_bitfield_default },
+	 { "TPH_REQR_ST_TABLE_LOCATION", 9, 10, &umr_bitfield_default },
+	 { "TPH_REQR_ST_TABLE_SIZE", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_CNTL[] = {
+	 { "TPH_REQR_ST_MODE_SEL", 0, 2, &umr_bitfield_default },
+	 { "TPH_REQR_EN", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ENABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_WIN_SIZE_REQ", 8, 13, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmROM_BASE_ADDR[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_INDEX_2[] = {
+	 { "PCIE_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LTR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LTR_CAP[] = {
+	 { "LTR_MAX_S_LATENCY_VALUE", 0, 9, &umr_bitfield_default },
+	 { "LTR_MAX_S_LATENCY_SCALE", 10, 12, &umr_bitfield_default },
+	 { "LTR_MAX_NS_LATENCY_VALUE", 16, 25, &umr_bitfield_default },
+	 { "LTR_MAX_NS_LATENCY_SCALE", 26, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DATA_2[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_INDEX[] = {
+	 { "PCIE_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAX_LATENCY[] = {
+	 { "MAX_LAT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMIN_GRANT[] = {
+	 { "MIN_GNT", 0, 7, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/bif41_regs.i b/src/lib/ip/bif41_regs.i
new file mode 100644
index 0000000..b013afc
--- /dev/null
+++ b/src/lib/ip/bif41_regs.i
@@ -0,0 +1,874 @@
+	{ "mmVENDOR_ID", REG_MMIO, 0x0, &mmVENDOR_ID[0], sizeof(mmVENDOR_ID)/sizeof(mmVENDOR_ID[0]), 0, 0 },
+	{ "mmMM_INDEX", REG_MMIO, 0x0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
+	{ "mmMM_DATA", REG_MMIO, 0x1, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
+	{ "mmSTATUS", REG_MMIO, 0x1, &mmSTATUS[0], sizeof(mmSTATUS)/sizeof(mmSTATUS[0]), 0, 0 },
+	{ "ixPCIEP_RESERVED", REG_SMC, 0x10010000, &ixPCIEP_RESERVED[0], sizeof(ixPCIEP_RESERVED)/sizeof(ixPCIEP_RESERVED[0]), 0, 0 },
+	{ "ixPCIEP_SCRATCH", REG_SMC, 0x10010001, &ixPCIEP_SCRATCH[0], sizeof(ixPCIEP_SCRATCH)/sizeof(ixPCIEP_SCRATCH[0]), 0, 0 },
+	{ "ixPCIEP_HW_DEBUG", REG_SMC, 0x10010002, &ixPCIEP_HW_DEBUG[0], sizeof(ixPCIEP_HW_DEBUG)/sizeof(ixPCIEP_HW_DEBUG[0]), 0, 0 },
+	{ "ixPCIEP_PORT_CNTL", REG_SMC, 0x10010010, &ixPCIEP_PORT_CNTL[0], sizeof(ixPCIEP_PORT_CNTL)/sizeof(ixPCIEP_PORT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_CNTL", REG_SMC, 0x10010020, &ixPCIE_TX_CNTL[0], sizeof(ixPCIE_TX_CNTL)/sizeof(ixPCIE_TX_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_REQUESTER_ID", REG_SMC, 0x10010021, &ixPCIE_TX_REQUESTER_ID[0], sizeof(ixPCIE_TX_REQUESTER_ID)/sizeof(ixPCIE_TX_REQUESTER_ID[0]), 0, 0 },
+	{ "ixPCIE_TX_VENDOR_SPECIFIC", REG_SMC, 0x10010022, &ixPCIE_TX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_TX_VENDOR_SPECIFIC)/sizeof(ixPCIE_TX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "ixPCIE_TX_REQUEST_NUM_CNTL", REG_SMC, 0x10010023, &ixPCIE_TX_REQUEST_NUM_CNTL[0], sizeof(ixPCIE_TX_REQUEST_NUM_CNTL)/sizeof(ixPCIE_TX_REQUEST_NUM_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_SEQ", REG_SMC, 0x10010024, &ixPCIE_TX_SEQ[0], sizeof(ixPCIE_TX_SEQ)/sizeof(ixPCIE_TX_SEQ[0]), 0, 0 },
+	{ "ixPCIE_TX_REPLAY", REG_SMC, 0x10010025, &ixPCIE_TX_REPLAY[0], sizeof(ixPCIE_TX_REPLAY)/sizeof(ixPCIE_TX_REPLAY[0]), 0, 0 },
+	{ "ixPCIE_TX_ACK_LATENCY_LIMIT", REG_SMC, 0x10010026, &ixPCIE_TX_ACK_LATENCY_LIMIT[0], sizeof(ixPCIE_TX_ACK_LATENCY_LIMIT)/sizeof(ixPCIE_TX_ACK_LATENCY_LIMIT[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_P", REG_SMC, 0x10010030, &ixPCIE_TX_CREDITS_ADVT_P[0], sizeof(ixPCIE_TX_CREDITS_ADVT_P)/sizeof(ixPCIE_TX_CREDITS_ADVT_P[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_NP", REG_SMC, 0x10010031, &ixPCIE_TX_CREDITS_ADVT_NP[0], sizeof(ixPCIE_TX_CREDITS_ADVT_NP)/sizeof(ixPCIE_TX_CREDITS_ADVT_NP[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_CPL", REG_SMC, 0x10010032, &ixPCIE_TX_CREDITS_ADVT_CPL[0], sizeof(ixPCIE_TX_CREDITS_ADVT_CPL)/sizeof(ixPCIE_TX_CREDITS_ADVT_CPL[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_P", REG_SMC, 0x10010033, &ixPCIE_TX_CREDITS_INIT_P[0], sizeof(ixPCIE_TX_CREDITS_INIT_P)/sizeof(ixPCIE_TX_CREDITS_INIT_P[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_NP", REG_SMC, 0x10010034, &ixPCIE_TX_CREDITS_INIT_NP[0], sizeof(ixPCIE_TX_CREDITS_INIT_NP)/sizeof(ixPCIE_TX_CREDITS_INIT_NP[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_CPL", REG_SMC, 0x10010035, &ixPCIE_TX_CREDITS_INIT_CPL[0], sizeof(ixPCIE_TX_CREDITS_INIT_CPL)/sizeof(ixPCIE_TX_CREDITS_INIT_CPL[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_STATUS", REG_SMC, 0x10010036, &ixPCIE_TX_CREDITS_STATUS[0], sizeof(ixPCIE_TX_CREDITS_STATUS)/sizeof(ixPCIE_TX_CREDITS_STATUS[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_FCU_THRESHOLD", REG_SMC, 0x10010037, &ixPCIE_TX_CREDITS_FCU_THRESHOLD[0], sizeof(ixPCIE_TX_CREDITS_FCU_THRESHOLD)/sizeof(ixPCIE_TX_CREDITS_FCU_THRESHOLD[0]), 0, 0 },
+	{ "ixPCIE_P_PORT_LANE_STATUS", REG_SMC, 0x10010050, &ixPCIE_P_PORT_LANE_STATUS[0], sizeof(ixPCIE_P_PORT_LANE_STATUS)/sizeof(ixPCIE_P_PORT_LANE_STATUS[0]), 0, 0 },
+	{ "ixPCIE_FC_P", REG_SMC, 0x10010060, &ixPCIE_FC_P[0], sizeof(ixPCIE_FC_P)/sizeof(ixPCIE_FC_P[0]), 0, 0 },
+	{ "ixPCIE_FC_NP", REG_SMC, 0x10010061, &ixPCIE_FC_NP[0], sizeof(ixPCIE_FC_NP)/sizeof(ixPCIE_FC_NP[0]), 0, 0 },
+	{ "ixPCIE_FC_CPL", REG_SMC, 0x10010062, &ixPCIE_FC_CPL[0], sizeof(ixPCIE_FC_CPL)/sizeof(ixPCIE_FC_CPL[0]), 0, 0 },
+	{ "ixPCIE_ERR_CNTL", REG_SMC, 0x1001006a, &ixPCIE_ERR_CNTL[0], sizeof(ixPCIE_ERR_CNTL)/sizeof(ixPCIE_ERR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL", REG_SMC, 0x10010070, &ixPCIE_RX_CNTL[0], sizeof(ixPCIE_RX_CNTL)/sizeof(ixPCIE_RX_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_EXPECTED_SEQNUM", REG_SMC, 0x10010071, &ixPCIE_RX_EXPECTED_SEQNUM[0], sizeof(ixPCIE_RX_EXPECTED_SEQNUM)/sizeof(ixPCIE_RX_EXPECTED_SEQNUM[0]), 0, 0 },
+	{ "ixPCIE_RX_VENDOR_SPECIFIC", REG_SMC, 0x10010072, &ixPCIE_RX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_RX_VENDOR_SPECIFIC)/sizeof(ixPCIE_RX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL3", REG_SMC, 0x10010074, &ixPCIE_RX_CNTL3[0], sizeof(ixPCIE_RX_CNTL3)/sizeof(ixPCIE_RX_CNTL3[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_P", REG_SMC, 0x10010080, &ixPCIE_RX_CREDITS_ALLOCATED_P[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_P)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_P[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_NP", REG_SMC, 0x10010081, &ixPCIE_RX_CREDITS_ALLOCATED_NP[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_NP)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_NP[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_CPL", REG_SMC, 0x10010082, &ixPCIE_RX_CREDITS_ALLOCATED_CPL[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_CPL)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_CPL[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL", REG_SMC, 0x100100a0, &ixPCIE_LC_CNTL[0], sizeof(ixPCIE_LC_CNTL)/sizeof(ixPCIE_LC_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_TRAINING_CNTL", REG_SMC, 0x100100a1, &ixPCIE_LC_TRAINING_CNTL[0], sizeof(ixPCIE_LC_TRAINING_CNTL)/sizeof(ixPCIE_LC_TRAINING_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_LINK_WIDTH_CNTL", REG_SMC, 0x100100a2, &ixPCIE_LC_LINK_WIDTH_CNTL[0], sizeof(ixPCIE_LC_LINK_WIDTH_CNTL)/sizeof(ixPCIE_LC_LINK_WIDTH_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_N_FTS_CNTL", REG_SMC, 0x100100a3, &ixPCIE_LC_N_FTS_CNTL[0], sizeof(ixPCIE_LC_N_FTS_CNTL)/sizeof(ixPCIE_LC_N_FTS_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_SPEED_CNTL", REG_SMC, 0x100100a4, &ixPCIE_LC_SPEED_CNTL[0], sizeof(ixPCIE_LC_SPEED_CNTL)/sizeof(ixPCIE_LC_SPEED_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE0", REG_SMC, 0x100100a5, &ixPCIE_LC_STATE0[0], sizeof(ixPCIE_LC_STATE0)/sizeof(ixPCIE_LC_STATE0[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE1", REG_SMC, 0x100100a6, &ixPCIE_LC_STATE1[0], sizeof(ixPCIE_LC_STATE1)/sizeof(ixPCIE_LC_STATE1[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE2", REG_SMC, 0x100100a7, &ixPCIE_LC_STATE2[0], sizeof(ixPCIE_LC_STATE2)/sizeof(ixPCIE_LC_STATE2[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE3", REG_SMC, 0x100100a8, &ixPCIE_LC_STATE3[0], sizeof(ixPCIE_LC_STATE3)/sizeof(ixPCIE_LC_STATE3[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE4", REG_SMC, 0x100100a9, &ixPCIE_LC_STATE4[0], sizeof(ixPCIE_LC_STATE4)/sizeof(ixPCIE_LC_STATE4[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE5", REG_SMC, 0x100100aa, &ixPCIE_LC_STATE5[0], sizeof(ixPCIE_LC_STATE5)/sizeof(ixPCIE_LC_STATE5[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL2", REG_SMC, 0x100100b1, &ixPCIE_LC_CNTL2[0], sizeof(ixPCIE_LC_CNTL2)/sizeof(ixPCIE_LC_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_LC_BW_CHANGE_CNTL", REG_SMC, 0x100100b2, &ixPCIE_LC_BW_CHANGE_CNTL[0], sizeof(ixPCIE_LC_BW_CHANGE_CNTL)/sizeof(ixPCIE_LC_BW_CHANGE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_CDR_CNTL", REG_SMC, 0x100100b3, &ixPCIE_LC_CDR_CNTL[0], sizeof(ixPCIE_LC_CDR_CNTL)/sizeof(ixPCIE_LC_CDR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_LANE_CNTL", REG_SMC, 0x100100b4, &ixPCIE_LC_LANE_CNTL[0], sizeof(ixPCIE_LC_LANE_CNTL)/sizeof(ixPCIE_LC_LANE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL3", REG_SMC, 0x100100b5, &ixPCIE_LC_CNTL3[0], sizeof(ixPCIE_LC_CNTL3)/sizeof(ixPCIE_LC_CNTL3[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL4", REG_SMC, 0x100100b6, &ixPCIE_LC_CNTL4[0], sizeof(ixPCIE_LC_CNTL4)/sizeof(ixPCIE_LC_CNTL4[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL5", REG_SMC, 0x100100b7, &ixPCIE_LC_CNTL5[0], sizeof(ixPCIE_LC_CNTL5)/sizeof(ixPCIE_LC_CNTL5[0]), 0, 0 },
+	{ "ixPCIE_LC_FORCE_COEFF", REG_SMC, 0x100100b8, &ixPCIE_LC_FORCE_COEFF[0], sizeof(ixPCIE_LC_FORCE_COEFF)/sizeof(ixPCIE_LC_FORCE_COEFF[0]), 0, 0 },
+	{ "ixPCIE_LC_BEST_EQ_SETTINGS", REG_SMC, 0x100100b9, &ixPCIE_LC_BEST_EQ_SETTINGS[0], sizeof(ixPCIE_LC_BEST_EQ_SETTINGS)/sizeof(ixPCIE_LC_BEST_EQ_SETTINGS[0]), 0, 0 },
+	{ "ixPCIE_LC_FORCE_EQ_REQ_COEFF", REG_SMC, 0x100100ba, &ixPCIE_LC_FORCE_EQ_REQ_COEFF[0], sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF)/sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF[0]), 0, 0 },
+	{ "ixPCIEP_STRAP_LC", REG_SMC, 0x100100c0, &ixPCIEP_STRAP_LC[0], sizeof(ixPCIEP_STRAP_LC)/sizeof(ixPCIEP_STRAP_LC[0]), 0, 0 },
+	{ "ixPCIEP_STRAP_MISC", REG_SMC, 0x100100c1, &ixPCIEP_STRAP_MISC[0], sizeof(ixPCIEP_STRAP_MISC)/sizeof(ixPCIEP_STRAP_MISC[0]), 0, 0 },
+	{ "ixPCIEP_BCH_ECC_CNTL", REG_SMC, 0x100100d0, &ixPCIEP_BCH_ECC_CNTL[0], sizeof(ixPCIEP_BCH_ECC_CNTL)/sizeof(ixPCIEP_BCH_ECC_CNTL[0]), 0, 0 },
+	{ "ixPB0_PIF_SCRATCH", REG_SMC, 0x1100001, &ixPB0_PIF_SCRATCH[0], sizeof(ixPB0_PIF_SCRATCH)/sizeof(ixPB0_PIF_SCRATCH[0]), 0, 0 },
+	{ "ixPB0_PIF_HW_DEBUG", REG_SMC, 0x1100002, &ixPB0_PIF_HW_DEBUG[0], sizeof(ixPB0_PIF_HW_DEBUG)/sizeof(ixPB0_PIF_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB0_PIF_PRG6", REG_SMC, 0x1100003, &ixPB0_PIF_PRG6[0], sizeof(ixPB0_PIF_PRG6)/sizeof(ixPB0_PIF_PRG6[0]), 0, 0 },
+	{ "ixPB0_PIF_PRG7", REG_SMC, 0x1100004, &ixPB0_PIF_PRG7[0], sizeof(ixPB0_PIF_PRG7)/sizeof(ixPB0_PIF_PRG7[0]), 0, 0 },
+	{ "ixPB0_PIF_CNTL", REG_SMC, 0x1100010, &ixPB0_PIF_CNTL[0], sizeof(ixPB0_PIF_CNTL)/sizeof(ixPB0_PIF_CNTL[0]), 0, 0 },
+	{ "ixPB0_PIF_PAIRING", REG_SMC, 0x1100011, &ixPB0_PIF_PAIRING[0], sizeof(ixPB0_PIF_PAIRING)/sizeof(ixPB0_PIF_PAIRING[0]), 0, 0 },
+	{ "ixPB0_PIF_PWRDOWN_0", REG_SMC, 0x1100012, &ixPB0_PIF_PWRDOWN_0[0], sizeof(ixPB0_PIF_PWRDOWN_0)/sizeof(ixPB0_PIF_PWRDOWN_0[0]), 0, 0 },
+	{ "ixPB0_PIF_PWRDOWN_1", REG_SMC, 0x1100013, &ixPB0_PIF_PWRDOWN_1[0], sizeof(ixPB0_PIF_PWRDOWN_1)/sizeof(ixPB0_PIF_PWRDOWN_1[0]), 0, 0 },
+	{ "ixPB0_PIF_CNTL2", REG_SMC, 0x1100014, &ixPB0_PIF_CNTL2[0], sizeof(ixPB0_PIF_CNTL2)/sizeof(ixPB0_PIF_CNTL2[0]), 0, 0 },
+	{ "ixPB0_PIF_TXPHYSTATUS", REG_SMC, 0x1100015, &ixPB0_PIF_TXPHYSTATUS[0], sizeof(ixPB0_PIF_TXPHYSTATUS)/sizeof(ixPB0_PIF_TXPHYSTATUS[0]), 0, 0 },
+	{ "ixPB0_PIF_SC_CTL", REG_SMC, 0x1100016, &ixPB0_PIF_SC_CTL[0], sizeof(ixPB0_PIF_SC_CTL)/sizeof(ixPB0_PIF_SC_CTL[0]), 0, 0 },
+	{ "ixPB0_PIF_PWRDOWN_2", REG_SMC, 0x1100017, &ixPB0_PIF_PWRDOWN_2[0], sizeof(ixPB0_PIF_PWRDOWN_2)/sizeof(ixPB0_PIF_PWRDOWN_2[0]), 0, 0 },
+	{ "ixPB0_PIF_PWRDOWN_3", REG_SMC, 0x1100018, &ixPB0_PIF_PWRDOWN_3[0], sizeof(ixPB0_PIF_PWRDOWN_3)/sizeof(ixPB0_PIF_PWRDOWN_3[0]), 0, 0 },
+	{ "ixPB0_PIF_SC_CTL2", REG_SMC, 0x1100019, &ixPB0_PIF_SC_CTL2[0], sizeof(ixPB0_PIF_SC_CTL2)/sizeof(ixPB0_PIF_SC_CTL2[0]), 0, 0 },
+	{ "ixPB0_PIF_PRG0", REG_SMC, 0x110001a, &ixPB0_PIF_PRG0[0], sizeof(ixPB0_PIF_PRG0)/sizeof(ixPB0_PIF_PRG0[0]), 0, 0 },
+	{ "ixPB0_PIF_PRG1", REG_SMC, 0x110001b, &ixPB0_PIF_PRG1[0], sizeof(ixPB0_PIF_PRG1)/sizeof(ixPB0_PIF_PRG1[0]), 0, 0 },
+	{ "ixPB0_PIF_PRG2", REG_SMC, 0x110001c, &ixPB0_PIF_PRG2[0], sizeof(ixPB0_PIF_PRG2)/sizeof(ixPB0_PIF_PRG2[0]), 0, 0 },
+	{ "ixPB0_PIF_PRG3", REG_SMC, 0x110001d, &ixPB0_PIF_PRG3[0], sizeof(ixPB0_PIF_PRG3)/sizeof(ixPB0_PIF_PRG3[0]), 0, 0 },
+	{ "ixPB0_PIF_PRG4", REG_SMC, 0x110001e, &ixPB0_PIF_PRG4[0], sizeof(ixPB0_PIF_PRG4)/sizeof(ixPB0_PIF_PRG4[0]), 0, 0 },
+	{ "ixPB0_PIF_PRG5", REG_SMC, 0x110001f, &ixPB0_PIF_PRG5[0], sizeof(ixPB0_PIF_PRG5)/sizeof(ixPB0_PIF_PRG5[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_0", REG_SMC, 0x1100020, &ixPB0_PIF_PDNB_OVERRIDE_0[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_0)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_0[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_1", REG_SMC, 0x1100021, &ixPB0_PIF_PDNB_OVERRIDE_1[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_1)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_1[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_2", REG_SMC, 0x1100022, &ixPB0_PIF_PDNB_OVERRIDE_2[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_2)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_2[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_3", REG_SMC, 0x1100023, &ixPB0_PIF_PDNB_OVERRIDE_3[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_3)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_3[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_4", REG_SMC, 0x1100024, &ixPB0_PIF_PDNB_OVERRIDE_4[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_4)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_4[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_5", REG_SMC, 0x1100025, &ixPB0_PIF_PDNB_OVERRIDE_5[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_5)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_5[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_6", REG_SMC, 0x1100026, &ixPB0_PIF_PDNB_OVERRIDE_6[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_6)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_6[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_7", REG_SMC, 0x1100027, &ixPB0_PIF_PDNB_OVERRIDE_7[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_7)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_7[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_0", REG_SMC, 0x1100028, &ixPB0_PIF_SEQ_STATUS_0[0], sizeof(ixPB0_PIF_SEQ_STATUS_0)/sizeof(ixPB0_PIF_SEQ_STATUS_0[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_1", REG_SMC, 0x1100029, &ixPB0_PIF_SEQ_STATUS_1[0], sizeof(ixPB0_PIF_SEQ_STATUS_1)/sizeof(ixPB0_PIF_SEQ_STATUS_1[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_2", REG_SMC, 0x110002a, &ixPB0_PIF_SEQ_STATUS_2[0], sizeof(ixPB0_PIF_SEQ_STATUS_2)/sizeof(ixPB0_PIF_SEQ_STATUS_2[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_3", REG_SMC, 0x110002b, &ixPB0_PIF_SEQ_STATUS_3[0], sizeof(ixPB0_PIF_SEQ_STATUS_3)/sizeof(ixPB0_PIF_SEQ_STATUS_3[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_4", REG_SMC, 0x110002c, &ixPB0_PIF_SEQ_STATUS_4[0], sizeof(ixPB0_PIF_SEQ_STATUS_4)/sizeof(ixPB0_PIF_SEQ_STATUS_4[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_5", REG_SMC, 0x110002d, &ixPB0_PIF_SEQ_STATUS_5[0], sizeof(ixPB0_PIF_SEQ_STATUS_5)/sizeof(ixPB0_PIF_SEQ_STATUS_5[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_6", REG_SMC, 0x110002e, &ixPB0_PIF_SEQ_STATUS_6[0], sizeof(ixPB0_PIF_SEQ_STATUS_6)/sizeof(ixPB0_PIF_SEQ_STATUS_6[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_7", REG_SMC, 0x110002f, &ixPB0_PIF_SEQ_STATUS_7[0], sizeof(ixPB0_PIF_SEQ_STATUS_7)/sizeof(ixPB0_PIF_SEQ_STATUS_7[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_8", REG_SMC, 0x1100030, &ixPB0_PIF_PDNB_OVERRIDE_8[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_8)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_8[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_9", REG_SMC, 0x1100031, &ixPB0_PIF_PDNB_OVERRIDE_9[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_9)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_9[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_10", REG_SMC, 0x1100032, &ixPB0_PIF_PDNB_OVERRIDE_10[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_10)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_10[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_11", REG_SMC, 0x1100033, &ixPB0_PIF_PDNB_OVERRIDE_11[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_11)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_11[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_12", REG_SMC, 0x1100034, &ixPB0_PIF_PDNB_OVERRIDE_12[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_12)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_12[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_13", REG_SMC, 0x1100035, &ixPB0_PIF_PDNB_OVERRIDE_13[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_13)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_13[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_14", REG_SMC, 0x1100036, &ixPB0_PIF_PDNB_OVERRIDE_14[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_14)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_14[0]), 0, 0 },
+	{ "ixPB0_PIF_PDNB_OVERRIDE_15", REG_SMC, 0x1100037, &ixPB0_PIF_PDNB_OVERRIDE_15[0], sizeof(ixPB0_PIF_PDNB_OVERRIDE_15)/sizeof(ixPB0_PIF_PDNB_OVERRIDE_15[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_8", REG_SMC, 0x1100038, &ixPB0_PIF_SEQ_STATUS_8[0], sizeof(ixPB0_PIF_SEQ_STATUS_8)/sizeof(ixPB0_PIF_SEQ_STATUS_8[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_9", REG_SMC, 0x1100039, &ixPB0_PIF_SEQ_STATUS_9[0], sizeof(ixPB0_PIF_SEQ_STATUS_9)/sizeof(ixPB0_PIF_SEQ_STATUS_9[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_10", REG_SMC, 0x110003a, &ixPB0_PIF_SEQ_STATUS_10[0], sizeof(ixPB0_PIF_SEQ_STATUS_10)/sizeof(ixPB0_PIF_SEQ_STATUS_10[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_11", REG_SMC, 0x110003b, &ixPB0_PIF_SEQ_STATUS_11[0], sizeof(ixPB0_PIF_SEQ_STATUS_11)/sizeof(ixPB0_PIF_SEQ_STATUS_11[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_12", REG_SMC, 0x110003c, &ixPB0_PIF_SEQ_STATUS_12[0], sizeof(ixPB0_PIF_SEQ_STATUS_12)/sizeof(ixPB0_PIF_SEQ_STATUS_12[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_13", REG_SMC, 0x110003d, &ixPB0_PIF_SEQ_STATUS_13[0], sizeof(ixPB0_PIF_SEQ_STATUS_13)/sizeof(ixPB0_PIF_SEQ_STATUS_13[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_14", REG_SMC, 0x110003e, &ixPB0_PIF_SEQ_STATUS_14[0], sizeof(ixPB0_PIF_SEQ_STATUS_14)/sizeof(ixPB0_PIF_SEQ_STATUS_14[0]), 0, 0 },
+	{ "ixPB0_PIF_SEQ_STATUS_15", REG_SMC, 0x110003f, &ixPB0_PIF_SEQ_STATUS_15[0], sizeof(ixPB0_PIF_SEQ_STATUS_15)/sizeof(ixPB0_PIF_SEQ_STATUS_15[0]), 0, 0 },
+	{ "mmVENDOR_CAP_LIST", REG_MMIO, 0x12, &mmVENDOR_CAP_LIST[0], sizeof(mmVENDOR_CAP_LIST)/sizeof(mmVENDOR_CAP_LIST[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG0", REG_SMC, 0x1200004, &ixPB0_GLB_CTRL_REG0[0], sizeof(ixPB0_GLB_CTRL_REG0)/sizeof(ixPB0_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG1", REG_SMC, 0x1200008, &ixPB0_GLB_CTRL_REG1[0], sizeof(ixPB0_GLB_CTRL_REG1)/sizeof(ixPB0_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG2", REG_SMC, 0x120000c, &ixPB0_GLB_CTRL_REG2[0], sizeof(ixPB0_GLB_CTRL_REG2)/sizeof(ixPB0_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG3", REG_SMC, 0x1200010, &ixPB0_GLB_CTRL_REG3[0], sizeof(ixPB0_GLB_CTRL_REG3)/sizeof(ixPB0_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG4", REG_SMC, 0x1200014, &ixPB0_GLB_CTRL_REG4[0], sizeof(ixPB0_GLB_CTRL_REG4)/sizeof(ixPB0_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG5", REG_SMC, 0x1200018, &ixPB0_GLB_CTRL_REG5[0], sizeof(ixPB0_GLB_CTRL_REG5)/sizeof(ixPB0_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x120001c, &ixPB0_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG1", REG_SMC, 0x1200020, &ixPB0_GLB_SCI_STAT_OVRD_REG1[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG1)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG2", REG_SMC, 0x1200024, &ixPB0_GLB_SCI_STAT_OVRD_REG2[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG2)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG3", REG_SMC, 0x1200028, &ixPB0_GLB_SCI_STAT_OVRD_REG3[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG3)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG4", REG_SMC, 0x120002c, &ixPB0_GLB_SCI_STAT_OVRD_REG4[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG4)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG0", REG_SMC, 0x1200030, &ixPB0_GLB_OVRD_REG0[0], sizeof(ixPB0_GLB_OVRD_REG0)/sizeof(ixPB0_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG1", REG_SMC, 0x1200034, &ixPB0_GLB_OVRD_REG1[0], sizeof(ixPB0_GLB_OVRD_REG1)/sizeof(ixPB0_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG2", REG_SMC, 0x1200038, &ixPB0_GLB_OVRD_REG2[0], sizeof(ixPB0_GLB_OVRD_REG2)/sizeof(ixPB0_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_HW_DEBUG", REG_SMC, 0x1202004, &ixPB0_HW_DEBUG[0], sizeof(ixPB0_HW_DEBUG)/sizeof(ixPB0_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB0_STRAP_GLB_REG0", REG_SMC, 0x1202020, &ixPB0_STRAP_GLB_REG0[0], sizeof(ixPB0_STRAP_GLB_REG0)/sizeof(ixPB0_STRAP_GLB_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_TX_REG0", REG_SMC, 0x1202024, &ixPB0_STRAP_TX_REG0[0], sizeof(ixPB0_STRAP_TX_REG0)/sizeof(ixPB0_STRAP_TX_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_RX_REG0", REG_SMC, 0x1202028, &ixPB0_STRAP_RX_REG0[0], sizeof(ixPB0_STRAP_RX_REG0)/sizeof(ixPB0_STRAP_RX_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_RX_REG1", REG_SMC, 0x120202c, &ixPB0_STRAP_RX_REG1[0], sizeof(ixPB0_STRAP_RX_REG1)/sizeof(ixPB0_STRAP_RX_REG1[0]), 0, 0 },
+	{ "ixPB0_STRAP_PLL_REG0", REG_SMC, 0x1202030, &ixPB0_STRAP_PLL_REG0[0], sizeof(ixPB0_STRAP_PLL_REG0)/sizeof(ixPB0_STRAP_PLL_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_PIN_REG0", REG_SMC, 0x1202034, &ixPB0_STRAP_PIN_REG0[0], sizeof(ixPB0_STRAP_PIN_REG0)/sizeof(ixPB0_STRAP_PIN_REG0[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG0", REG_SMC, 0x1203000, &ixPB0_DFT_JIT_INJ_REG0[0], sizeof(ixPB0_DFT_JIT_INJ_REG0)/sizeof(ixPB0_DFT_JIT_INJ_REG0[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG1", REG_SMC, 0x1203004, &ixPB0_DFT_JIT_INJ_REG1[0], sizeof(ixPB0_DFT_JIT_INJ_REG1)/sizeof(ixPB0_DFT_JIT_INJ_REG1[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG2", REG_SMC, 0x1203008, &ixPB0_DFT_JIT_INJ_REG2[0], sizeof(ixPB0_DFT_JIT_INJ_REG2)/sizeof(ixPB0_DFT_JIT_INJ_REG2[0]), 0, 0 },
+	{ "ixPB0_DFT_DEBUG_CTRL_REG0", REG_SMC, 0x120300c, &ixPB0_DFT_DEBUG_CTRL_REG0[0], sizeof(ixPB0_DFT_DEBUG_CTRL_REG0)/sizeof(ixPB0_DFT_DEBUG_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_STAT_REG0", REG_SMC, 0x1203010, &ixPB0_DFT_JIT_INJ_STAT_REG0[0], sizeof(ixPB0_DFT_JIT_INJ_STAT_REG0)/sizeof(ixPB0_DFT_JIT_INJ_STAT_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO_GLB_CTRL_REG0", REG_SMC, 0x1204000, &ixPB0_PLL_RO_GLB_CTRL_REG0[0], sizeof(ixPB0_PLL_RO_GLB_CTRL_REG0)/sizeof(ixPB0_PLL_RO_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO_GLB_OVRD_REG0", REG_SMC, 0x1204010, NULL, 0, 0, 0 },
+	{ "ixPB0_PLL_RO0_CTRL_REG0", REG_SMC, 0x1204440, &ixPB0_PLL_RO0_CTRL_REG0[0], sizeof(ixPB0_PLL_RO0_CTRL_REG0)/sizeof(ixPB0_PLL_RO0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_OVRD_REG0", REG_SMC, 0x1204450, &ixPB0_PLL_RO0_OVRD_REG0[0], sizeof(ixPB0_PLL_RO0_OVRD_REG0)/sizeof(ixPB0_PLL_RO0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_OVRD_REG1", REG_SMC, 0x1204454, &ixPB0_PLL_RO0_OVRD_REG1[0], sizeof(ixPB0_PLL_RO0_OVRD_REG1)/sizeof(ixPB0_PLL_RO0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204460, &ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204464, &ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204468, &ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0", REG_SMC, 0x120446c, &ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_CTRL_REG0", REG_SMC, 0x1204480, &ixPB0_PLL_LC0_CTRL_REG0[0], sizeof(ixPB0_PLL_LC0_CTRL_REG0)/sizeof(ixPB0_PLL_LC0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_OVRD_REG0", REG_SMC, 0x1204490, &ixPB0_PLL_LC0_OVRD_REG0[0], sizeof(ixPB0_PLL_LC0_OVRD_REG0)/sizeof(ixPB0_PLL_LC0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_OVRD_REG1", REG_SMC, 0x1204494, &ixPB0_PLL_LC0_OVRD_REG1[0], sizeof(ixPB0_PLL_LC0_OVRD_REG1)/sizeof(ixPB0_PLL_LC0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204500, &ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204504, &ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204508, &ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0", REG_SMC, 0x120450c, &ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG0", REG_SMC, 0x1206000, &ixPB0_RX_GLB_CTRL_REG0[0], sizeof(ixPB0_RX_GLB_CTRL_REG0)/sizeof(ixPB0_RX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG1", REG_SMC, 0x1206004, &ixPB0_RX_GLB_CTRL_REG1[0], sizeof(ixPB0_RX_GLB_CTRL_REG1)/sizeof(ixPB0_RX_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG2", REG_SMC, 0x1206008, &ixPB0_RX_GLB_CTRL_REG2[0], sizeof(ixPB0_RX_GLB_CTRL_REG2)/sizeof(ixPB0_RX_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG3", REG_SMC, 0x120600c, &ixPB0_RX_GLB_CTRL_REG3[0], sizeof(ixPB0_RX_GLB_CTRL_REG3)/sizeof(ixPB0_RX_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG4", REG_SMC, 0x1206010, &ixPB0_RX_GLB_CTRL_REG4[0], sizeof(ixPB0_RX_GLB_CTRL_REG4)/sizeof(ixPB0_RX_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG5", REG_SMC, 0x1206014, &ixPB0_RX_GLB_CTRL_REG5[0], sizeof(ixPB0_RX_GLB_CTRL_REG5)/sizeof(ixPB0_RX_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG6", REG_SMC, 0x1206018, &ixPB0_RX_GLB_CTRL_REG6[0], sizeof(ixPB0_RX_GLB_CTRL_REG6)/sizeof(ixPB0_RX_GLB_CTRL_REG6[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG7", REG_SMC, 0x120601c, &ixPB0_RX_GLB_CTRL_REG7[0], sizeof(ixPB0_RX_GLB_CTRL_REG7)/sizeof(ixPB0_RX_GLB_CTRL_REG7[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG8", REG_SMC, 0x1206020, &ixPB0_RX_GLB_CTRL_REG8[0], sizeof(ixPB0_RX_GLB_CTRL_REG8)/sizeof(ixPB0_RX_GLB_CTRL_REG8[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206028, &ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_OVRD_REG0", REG_SMC, 0x1206030, &ixPB0_RX_GLB_OVRD_REG0[0], sizeof(ixPB0_RX_GLB_OVRD_REG0)/sizeof(ixPB0_RX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_OVRD_REG1", REG_SMC, 0x1206034, &ixPB0_RX_GLB_OVRD_REG1[0], sizeof(ixPB0_RX_GLB_OVRD_REG1)/sizeof(ixPB0_RX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_RX_LANE0_CTRL_REG0", REG_SMC, 0x1206440, &ixPB0_RX_LANE0_CTRL_REG0[0], sizeof(ixPB0_RX_LANE0_CTRL_REG0)/sizeof(ixPB0_RX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206448, &ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE1_CTRL_REG0", REG_SMC, 0x1206480, &ixPB0_RX_LANE1_CTRL_REG0[0], sizeof(ixPB0_RX_LANE1_CTRL_REG0)/sizeof(ixPB0_RX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206488, &ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE2_CTRL_REG0", REG_SMC, 0x1206500, &ixPB0_RX_LANE2_CTRL_REG0[0], sizeof(ixPB0_RX_LANE2_CTRL_REG0)/sizeof(ixPB0_RX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206508, &ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE3_CTRL_REG0", REG_SMC, 0x1206600, &ixPB0_RX_LANE3_CTRL_REG0[0], sizeof(ixPB0_RX_LANE3_CTRL_REG0)/sizeof(ixPB0_RX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206608, &ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE4_CTRL_REG0", REG_SMC, 0x1206800, &ixPB0_RX_LANE4_CTRL_REG0[0], sizeof(ixPB0_RX_LANE4_CTRL_REG0)/sizeof(ixPB0_RX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206848, &ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE5_CTRL_REG0", REG_SMC, 0x1206880, &ixPB0_RX_LANE5_CTRL_REG0[0], sizeof(ixPB0_RX_LANE5_CTRL_REG0)/sizeof(ixPB0_RX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206888, &ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE6_CTRL_REG0", REG_SMC, 0x1206900, &ixPB0_RX_LANE6_CTRL_REG0[0], sizeof(ixPB0_RX_LANE6_CTRL_REG0)/sizeof(ixPB0_RX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206908, &ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE7_CTRL_REG0", REG_SMC, 0x1206a00, &ixPB0_RX_LANE7_CTRL_REG0[0], sizeof(ixPB0_RX_LANE7_CTRL_REG0)/sizeof(ixPB0_RX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206a08, &ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE8_CTRL_REG0", REG_SMC, 0x1207440, &ixPB0_RX_LANE8_CTRL_REG0[0], sizeof(ixPB0_RX_LANE8_CTRL_REG0)/sizeof(ixPB0_RX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207448, &ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE9_CTRL_REG0", REG_SMC, 0x1207480, &ixPB0_RX_LANE9_CTRL_REG0[0], sizeof(ixPB0_RX_LANE9_CTRL_REG0)/sizeof(ixPB0_RX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207488, &ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE10_CTRL_REG0", REG_SMC, 0x1207500, &ixPB0_RX_LANE10_CTRL_REG0[0], sizeof(ixPB0_RX_LANE10_CTRL_REG0)/sizeof(ixPB0_RX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207508, &ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE11_CTRL_REG0", REG_SMC, 0x1207600, &ixPB0_RX_LANE11_CTRL_REG0[0], sizeof(ixPB0_RX_LANE11_CTRL_REG0)/sizeof(ixPB0_RX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207608, &ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE12_CTRL_REG0", REG_SMC, 0x1207840, &ixPB0_RX_LANE12_CTRL_REG0[0], sizeof(ixPB0_RX_LANE12_CTRL_REG0)/sizeof(ixPB0_RX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207848, &ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE13_CTRL_REG0", REG_SMC, 0x1207880, &ixPB0_RX_LANE13_CTRL_REG0[0], sizeof(ixPB0_RX_LANE13_CTRL_REG0)/sizeof(ixPB0_RX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207888, &ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE14_CTRL_REG0", REG_SMC, 0x1207900, &ixPB0_RX_LANE14_CTRL_REG0[0], sizeof(ixPB0_RX_LANE14_CTRL_REG0)/sizeof(ixPB0_RX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207908, &ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE15_CTRL_REG0", REG_SMC, 0x1207a00, &ixPB0_RX_LANE15_CTRL_REG0[0], sizeof(ixPB0_RX_LANE15_CTRL_REG0)/sizeof(ixPB0_RX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207a08, &ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_CTRL_REG0", REG_SMC, 0x1208000, &ixPB0_TX_GLB_CTRL_REG0[0], sizeof(ixPB0_TX_GLB_CTRL_REG0)/sizeof(ixPB0_TX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_LANE_SKEW_CTRL", REG_SMC, 0x1208004, &ixPB0_TX_GLB_LANE_SKEW_CTRL[0], sizeof(ixPB0_TX_GLB_LANE_SKEW_CTRL)/sizeof(ixPB0_TX_GLB_LANE_SKEW_CTRL[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208010, &ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0", REG_SMC, 0x1208014, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1", REG_SMC, 0x1208018, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2", REG_SMC, 0x120801c, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3", REG_SMC, 0x1208020, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG0", REG_SMC, 0x1208030, &ixPB0_TX_GLB_OVRD_REG0[0], sizeof(ixPB0_TX_GLB_OVRD_REG0)/sizeof(ixPB0_TX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG1", REG_SMC, 0x1208034, &ixPB0_TX_GLB_OVRD_REG1[0], sizeof(ixPB0_TX_GLB_OVRD_REG1)/sizeof(ixPB0_TX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG2", REG_SMC, 0x1208038, &ixPB0_TX_GLB_OVRD_REG2[0], sizeof(ixPB0_TX_GLB_OVRD_REG2)/sizeof(ixPB0_TX_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG3", REG_SMC, 0x120803c, &ixPB0_TX_GLB_OVRD_REG3[0], sizeof(ixPB0_TX_GLB_OVRD_REG3)/sizeof(ixPB0_TX_GLB_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG4", REG_SMC, 0x1208040, &ixPB0_TX_GLB_OVRD_REG4[0], sizeof(ixPB0_TX_GLB_OVRD_REG4)/sizeof(ixPB0_TX_GLB_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_CTRL_REG0", REG_SMC, 0x1208440, &ixPB0_TX_LANE0_CTRL_REG0[0], sizeof(ixPB0_TX_LANE0_CTRL_REG0)/sizeof(ixPB0_TX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_OVRD_REG0", REG_SMC, 0x1208444, &ixPB0_TX_LANE0_OVRD_REG0[0], sizeof(ixPB0_TX_LANE0_OVRD_REG0)/sizeof(ixPB0_TX_LANE0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208448, &ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_CTRL_REG0", REG_SMC, 0x1208480, &ixPB0_TX_LANE1_CTRL_REG0[0], sizeof(ixPB0_TX_LANE1_CTRL_REG0)/sizeof(ixPB0_TX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_OVRD_REG0", REG_SMC, 0x1208484, &ixPB0_TX_LANE1_OVRD_REG0[0], sizeof(ixPB0_TX_LANE1_OVRD_REG0)/sizeof(ixPB0_TX_LANE1_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208488, &ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_CTRL_REG0", REG_SMC, 0x1208500, &ixPB0_TX_LANE2_CTRL_REG0[0], sizeof(ixPB0_TX_LANE2_CTRL_REG0)/sizeof(ixPB0_TX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_OVRD_REG0", REG_SMC, 0x1208504, &ixPB0_TX_LANE2_OVRD_REG0[0], sizeof(ixPB0_TX_LANE2_OVRD_REG0)/sizeof(ixPB0_TX_LANE2_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208508, &ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_CTRL_REG0", REG_SMC, 0x1208600, &ixPB0_TX_LANE3_CTRL_REG0[0], sizeof(ixPB0_TX_LANE3_CTRL_REG0)/sizeof(ixPB0_TX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_OVRD_REG0", REG_SMC, 0x1208604, &ixPB0_TX_LANE3_OVRD_REG0[0], sizeof(ixPB0_TX_LANE3_OVRD_REG0)/sizeof(ixPB0_TX_LANE3_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208608, &ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_CTRL_REG0", REG_SMC, 0x1208840, &ixPB0_TX_LANE4_CTRL_REG0[0], sizeof(ixPB0_TX_LANE4_CTRL_REG0)/sizeof(ixPB0_TX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_OVRD_REG0", REG_SMC, 0x1208844, &ixPB0_TX_LANE4_OVRD_REG0[0], sizeof(ixPB0_TX_LANE4_OVRD_REG0)/sizeof(ixPB0_TX_LANE4_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208848, &ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_CTRL_REG0", REG_SMC, 0x1208880, &ixPB0_TX_LANE5_CTRL_REG0[0], sizeof(ixPB0_TX_LANE5_CTRL_REG0)/sizeof(ixPB0_TX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_OVRD_REG0", REG_SMC, 0x1208884, &ixPB0_TX_LANE5_OVRD_REG0[0], sizeof(ixPB0_TX_LANE5_OVRD_REG0)/sizeof(ixPB0_TX_LANE5_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208888, &ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_CTRL_REG0", REG_SMC, 0x1208900, &ixPB0_TX_LANE6_CTRL_REG0[0], sizeof(ixPB0_TX_LANE6_CTRL_REG0)/sizeof(ixPB0_TX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_OVRD_REG0", REG_SMC, 0x1208904, &ixPB0_TX_LANE6_OVRD_REG0[0], sizeof(ixPB0_TX_LANE6_OVRD_REG0)/sizeof(ixPB0_TX_LANE6_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208908, &ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_CTRL_REG0", REG_SMC, 0x1208a00, &ixPB0_TX_LANE7_CTRL_REG0[0], sizeof(ixPB0_TX_LANE7_CTRL_REG0)/sizeof(ixPB0_TX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_OVRD_REG0", REG_SMC, 0x1208a04, &ixPB0_TX_LANE7_OVRD_REG0[0], sizeof(ixPB0_TX_LANE7_OVRD_REG0)/sizeof(ixPB0_TX_LANE7_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208a08, &ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_CTRL_REG0", REG_SMC, 0x1209440, &ixPB0_TX_LANE8_CTRL_REG0[0], sizeof(ixPB0_TX_LANE8_CTRL_REG0)/sizeof(ixPB0_TX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_OVRD_REG0", REG_SMC, 0x1209444, &ixPB0_TX_LANE8_OVRD_REG0[0], sizeof(ixPB0_TX_LANE8_OVRD_REG0)/sizeof(ixPB0_TX_LANE8_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209448, &ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_CTRL_REG0", REG_SMC, 0x1209480, &ixPB0_TX_LANE9_CTRL_REG0[0], sizeof(ixPB0_TX_LANE9_CTRL_REG0)/sizeof(ixPB0_TX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_OVRD_REG0", REG_SMC, 0x1209484, &ixPB0_TX_LANE9_OVRD_REG0[0], sizeof(ixPB0_TX_LANE9_OVRD_REG0)/sizeof(ixPB0_TX_LANE9_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209488, &ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_CTRL_REG0", REG_SMC, 0x1209500, &ixPB0_TX_LANE10_CTRL_REG0[0], sizeof(ixPB0_TX_LANE10_CTRL_REG0)/sizeof(ixPB0_TX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_OVRD_REG0", REG_SMC, 0x1209504, &ixPB0_TX_LANE10_OVRD_REG0[0], sizeof(ixPB0_TX_LANE10_OVRD_REG0)/sizeof(ixPB0_TX_LANE10_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209508, &ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_CTRL_REG0", REG_SMC, 0x1209600, &ixPB0_TX_LANE11_CTRL_REG0[0], sizeof(ixPB0_TX_LANE11_CTRL_REG0)/sizeof(ixPB0_TX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_OVRD_REG0", REG_SMC, 0x1209604, &ixPB0_TX_LANE11_OVRD_REG0[0], sizeof(ixPB0_TX_LANE11_OVRD_REG0)/sizeof(ixPB0_TX_LANE11_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209608, &ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_CTRL_REG0", REG_SMC, 0x1209840, &ixPB0_TX_LANE12_CTRL_REG0[0], sizeof(ixPB0_TX_LANE12_CTRL_REG0)/sizeof(ixPB0_TX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_OVRD_REG0", REG_SMC, 0x1209844, &ixPB0_TX_LANE12_OVRD_REG0[0], sizeof(ixPB0_TX_LANE12_OVRD_REG0)/sizeof(ixPB0_TX_LANE12_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209848, &ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_CTRL_REG0", REG_SMC, 0x1209880, &ixPB0_TX_LANE13_CTRL_REG0[0], sizeof(ixPB0_TX_LANE13_CTRL_REG0)/sizeof(ixPB0_TX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_OVRD_REG0", REG_SMC, 0x1209884, &ixPB0_TX_LANE13_OVRD_REG0[0], sizeof(ixPB0_TX_LANE13_OVRD_REG0)/sizeof(ixPB0_TX_LANE13_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209888, &ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_CTRL_REG0", REG_SMC, 0x1209900, &ixPB0_TX_LANE14_CTRL_REG0[0], sizeof(ixPB0_TX_LANE14_CTRL_REG0)/sizeof(ixPB0_TX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_OVRD_REG0", REG_SMC, 0x1209904, &ixPB0_TX_LANE14_OVRD_REG0[0], sizeof(ixPB0_TX_LANE14_OVRD_REG0)/sizeof(ixPB0_TX_LANE14_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209908, &ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_CTRL_REG0", REG_SMC, 0x1209a00, &ixPB0_TX_LANE15_CTRL_REG0[0], sizeof(ixPB0_TX_LANE15_CTRL_REG0)/sizeof(ixPB0_TX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_OVRD_REG0", REG_SMC, 0x1209a04, &ixPB0_TX_LANE15_OVRD_REG0[0], sizeof(ixPB0_TX_LANE15_OVRD_REG0)/sizeof(ixPB0_TX_LANE15_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209a08, &ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "mmADAPTER_ID_W", REG_MMIO, 0x13, &mmADAPTER_ID_W[0], sizeof(mmADAPTER_ID_W)/sizeof(mmADAPTER_ID_W[0]), 0, 0 },
+	{ "mmPMI_CAP_LIST", REG_MMIO, 0x14, &mmPMI_CAP_LIST[0], sizeof(mmPMI_CAP_LIST)/sizeof(mmPMI_CAP_LIST[0]), 0, 0 },
+	{ "mmPMI_CAP", REG_MMIO, 0x14, &mmPMI_CAP[0], sizeof(mmPMI_CAP)/sizeof(mmPMI_CAP[0]), 0, 0 },
+	{ "ixPCIE_RESERVED", REG_SMC, 0x1400000, &ixPCIE_RESERVED[0], sizeof(ixPCIE_RESERVED)/sizeof(ixPCIE_RESERVED[0]), 0, 0 },
+	{ "ixPCIE_SCRATCH", REG_SMC, 0x1400001, &ixPCIE_SCRATCH[0], sizeof(ixPCIE_SCRATCH)/sizeof(ixPCIE_SCRATCH[0]), 0, 0 },
+	{ "ixPCIE_HW_DEBUG", REG_SMC, 0x1400002, &ixPCIE_HW_DEBUG[0], sizeof(ixPCIE_HW_DEBUG)/sizeof(ixPCIE_HW_DEBUG[0]), 0, 0 },
+	{ "ixPCIE_RX_NUM_NAK", REG_SMC, 0x140000e, &ixPCIE_RX_NUM_NAK[0], sizeof(ixPCIE_RX_NUM_NAK)/sizeof(ixPCIE_RX_NUM_NAK[0]), 0, 0 },
+	{ "ixPCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x140000f, &ixPCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 },
+	{ "ixPCIE_CNTL", REG_SMC, 0x1400010, &ixPCIE_CNTL[0], sizeof(ixPCIE_CNTL)/sizeof(ixPCIE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_CONFIG_CNTL", REG_SMC, 0x1400011, &ixPCIE_CONFIG_CNTL[0], sizeof(ixPCIE_CONFIG_CNTL)/sizeof(ixPCIE_CONFIG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_DEBUG_CNTL", REG_SMC, 0x1400012, &ixPCIE_DEBUG_CNTL[0], sizeof(ixPCIE_DEBUG_CNTL)/sizeof(ixPCIE_DEBUG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_INT_CNTL", REG_SMC, 0x140001a, &ixPCIE_INT_CNTL[0], sizeof(ixPCIE_INT_CNTL)/sizeof(ixPCIE_INT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_INT_STATUS", REG_SMC, 0x140001b, &ixPCIE_INT_STATUS[0], sizeof(ixPCIE_INT_STATUS)/sizeof(ixPCIE_INT_STATUS[0]), 0, 0 },
+	{ "ixPCIE_CNTL2", REG_SMC, 0x140001c, &ixPCIE_CNTL2[0], sizeof(ixPCIE_CNTL2)/sizeof(ixPCIE_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL2", REG_SMC, 0x140001d, &ixPCIE_RX_CNTL2[0], sizeof(ixPCIE_RX_CNTL2)/sizeof(ixPCIE_RX_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_TX_F0_ATTR_CNTL", REG_SMC, 0x140001e, &ixPCIE_TX_F0_ATTR_CNTL[0], sizeof(ixPCIE_TX_F0_ATTR_CNTL)/sizeof(ixPCIE_TX_F0_ATTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_F1_F2_ATTR_CNTL", REG_SMC, 0x140001f, &ixPCIE_TX_F1_F2_ATTR_CNTL[0], sizeof(ixPCIE_TX_F1_F2_ATTR_CNTL)/sizeof(ixPCIE_TX_F1_F2_ATTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_CI_CNTL", REG_SMC, 0x1400020, &ixPCIE_CI_CNTL[0], sizeof(ixPCIE_CI_CNTL)/sizeof(ixPCIE_CI_CNTL[0]), 0, 0 },
+	{ "ixPCIE_BUS_CNTL", REG_SMC, 0x1400021, &ixPCIE_BUS_CNTL[0], sizeof(ixPCIE_BUS_CNTL)/sizeof(ixPCIE_BUS_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE6", REG_SMC, 0x1400022, &ixPCIE_LC_STATE6[0], sizeof(ixPCIE_LC_STATE6)/sizeof(ixPCIE_LC_STATE6[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE7", REG_SMC, 0x1400023, &ixPCIE_LC_STATE7[0], sizeof(ixPCIE_LC_STATE7)/sizeof(ixPCIE_LC_STATE7[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE8", REG_SMC, 0x1400024, &ixPCIE_LC_STATE8[0], sizeof(ixPCIE_LC_STATE8)/sizeof(ixPCIE_LC_STATE8[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE9", REG_SMC, 0x1400025, &ixPCIE_LC_STATE9[0], sizeof(ixPCIE_LC_STATE9)/sizeof(ixPCIE_LC_STATE9[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE10", REG_SMC, 0x1400026, &ixPCIE_LC_STATE10[0], sizeof(ixPCIE_LC_STATE10)/sizeof(ixPCIE_LC_STATE10[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE11", REG_SMC, 0x1400027, &ixPCIE_LC_STATE11[0], sizeof(ixPCIE_LC_STATE11)/sizeof(ixPCIE_LC_STATE11[0]), 0, 0 },
+	{ "ixPCIE_LC_STATUS1", REG_SMC, 0x1400028, &ixPCIE_LC_STATUS1[0], sizeof(ixPCIE_LC_STATUS1)/sizeof(ixPCIE_LC_STATUS1[0]), 0, 0 },
+	{ "ixPCIE_LC_STATUS2", REG_SMC, 0x1400029, &ixPCIE_LC_STATUS2[0], sizeof(ixPCIE_LC_STATUS2)/sizeof(ixPCIE_LC_STATUS2[0]), 0, 0 },
+	{ "ixPCIE_WPR_CNTL", REG_SMC, 0x1400030, &ixPCIE_WPR_CNTL[0], sizeof(ixPCIE_WPR_CNTL)/sizeof(ixPCIE_WPR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP0", REG_SMC, 0x1400031, &ixPCIE_RX_LAST_TLP0[0], sizeof(ixPCIE_RX_LAST_TLP0)/sizeof(ixPCIE_RX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP1", REG_SMC, 0x1400032, &ixPCIE_RX_LAST_TLP1[0], sizeof(ixPCIE_RX_LAST_TLP1)/sizeof(ixPCIE_RX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP2", REG_SMC, 0x1400033, &ixPCIE_RX_LAST_TLP2[0], sizeof(ixPCIE_RX_LAST_TLP2)/sizeof(ixPCIE_RX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP3", REG_SMC, 0x1400034, &ixPCIE_RX_LAST_TLP3[0], sizeof(ixPCIE_RX_LAST_TLP3)/sizeof(ixPCIE_RX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP0", REG_SMC, 0x1400035, &ixPCIE_TX_LAST_TLP0[0], sizeof(ixPCIE_TX_LAST_TLP0)/sizeof(ixPCIE_TX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP1", REG_SMC, 0x1400036, &ixPCIE_TX_LAST_TLP1[0], sizeof(ixPCIE_TX_LAST_TLP1)/sizeof(ixPCIE_TX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP2", REG_SMC, 0x1400037, &ixPCIE_TX_LAST_TLP2[0], sizeof(ixPCIE_TX_LAST_TLP2)/sizeof(ixPCIE_TX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP3", REG_SMC, 0x1400038, &ixPCIE_TX_LAST_TLP3[0], sizeof(ixPCIE_TX_LAST_TLP3)/sizeof(ixPCIE_TX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPCIE_I2C_REG_ADDR_EXPAND", REG_SMC, 0x140003a, &ixPCIE_I2C_REG_ADDR_EXPAND[0], sizeof(ixPCIE_I2C_REG_ADDR_EXPAND)/sizeof(ixPCIE_I2C_REG_ADDR_EXPAND[0]), 0, 0 },
+	{ "ixPCIE_I2C_REG_DATA", REG_SMC, 0x140003b, &ixPCIE_I2C_REG_DATA[0], sizeof(ixPCIE_I2C_REG_DATA)/sizeof(ixPCIE_I2C_REG_DATA[0]), 0, 0 },
+	{ "ixPCIE_CFG_CNTL", REG_SMC, 0x140003c, &ixPCIE_CFG_CNTL[0], sizeof(ixPCIE_CFG_CNTL)/sizeof(ixPCIE_CFG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_P_CNTL", REG_SMC, 0x1400040, &ixPCIE_P_CNTL[0], sizeof(ixPCIE_P_CNTL)/sizeof(ixPCIE_P_CNTL[0]), 0, 0 },
+	{ "ixPCIE_P_BUF_STATUS", REG_SMC, 0x1400041, &ixPCIE_P_BUF_STATUS[0], sizeof(ixPCIE_P_BUF_STATUS)/sizeof(ixPCIE_P_BUF_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_DECODER_STATUS", REG_SMC, 0x1400042, &ixPCIE_P_DECODER_STATUS[0], sizeof(ixPCIE_P_DECODER_STATUS)/sizeof(ixPCIE_P_DECODER_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_MISC_STATUS", REG_SMC, 0x1400043, &ixPCIE_P_MISC_STATUS[0], sizeof(ixPCIE_P_MISC_STATUS)/sizeof(ixPCIE_P_MISC_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_RCV_L0S_FTS_DET", REG_SMC, 0x1400050, &ixPCIE_P_RCV_L0S_FTS_DET[0], sizeof(ixPCIE_P_RCV_L0S_FTS_DET)/sizeof(ixPCIE_P_RCV_L0S_FTS_DET[0]), 0, 0 },
+	{ "ixPCIE_TX_LTR_CNTL", REG_SMC, 0x1400060, &ixPCIE_TX_LTR_CNTL[0], sizeof(ixPCIE_TX_LTR_CNTL)/sizeof(ixPCIE_TX_LTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_OBFF_CNTL", REG_SMC, 0x1400061, &ixPCIE_OBFF_CNTL[0], sizeof(ixPCIE_OBFF_CNTL)/sizeof(ixPCIE_OBFF_CNTL[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT_CNTL", REG_SMC, 0x1400080, &ixPCIE_PERF_COUNT_CNTL[0], sizeof(ixPCIE_PERF_COUNT_CNTL)/sizeof(ixPCIE_PERF_COUNT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_TXCLK", REG_SMC, 0x1400081, &ixPCIE_PERF_CNTL_TXCLK[0], sizeof(ixPCIE_PERF_CNTL_TXCLK)/sizeof(ixPCIE_PERF_CNTL_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x1400082, &ixPCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK)/sizeof(ixPCIE_PERF_COUNT0_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x1400083, &ixPCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK)/sizeof(ixPCIE_PERF_COUNT1_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x1400084, &ixPCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x1400085, &ixPCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x1400086, &ixPCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x1400087, &ixPCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x1400088, &ixPCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x1400089, &ixPCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x140008a, &ixPCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x140008b, &ixPCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x140008c, &ixPCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x140008d, &ixPCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x140008e, &ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x140008f, &ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x1400090, &ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x1400091, &ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x1400092, &ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x1400093, &ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x1400094, &ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x1400095, &ixPCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPCIE_PERF_CNTL_TXCLK2)/sizeof(ixPCIE_PERF_CNTL_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x1400096, &ixPCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x1400097, &ixPCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F0", REG_SMC, 0x14000b0, &ixPCIE_STRAP_F0[0], sizeof(ixPCIE_STRAP_F0)/sizeof(ixPCIE_STRAP_F0[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F1", REG_SMC, 0x14000b1, &ixPCIE_STRAP_F1[0], sizeof(ixPCIE_STRAP_F1)/sizeof(ixPCIE_STRAP_F1[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F2", REG_SMC, 0x14000b2, &ixPCIE_STRAP_F2[0], sizeof(ixPCIE_STRAP_F2)/sizeof(ixPCIE_STRAP_F2[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F3", REG_SMC, 0x14000b3, &ixPCIE_STRAP_F3[0], sizeof(ixPCIE_STRAP_F3)/sizeof(ixPCIE_STRAP_F3[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F4", REG_SMC, 0x14000b4, &ixPCIE_STRAP_F4[0], sizeof(ixPCIE_STRAP_F4)/sizeof(ixPCIE_STRAP_F4[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F5", REG_SMC, 0x14000b5, &ixPCIE_STRAP_F5[0], sizeof(ixPCIE_STRAP_F5)/sizeof(ixPCIE_STRAP_F5[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F6", REG_SMC, 0x14000b6, &ixPCIE_STRAP_F6[0], sizeof(ixPCIE_STRAP_F6)/sizeof(ixPCIE_STRAP_F6[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F7", REG_SMC, 0x14000b7, &ixPCIE_STRAP_F7[0], sizeof(ixPCIE_STRAP_F7)/sizeof(ixPCIE_STRAP_F7[0]), 0, 0 },
+	{ "ixPCIE_STRAP_MISC", REG_SMC, 0x14000c0, &ixPCIE_STRAP_MISC[0], sizeof(ixPCIE_STRAP_MISC)/sizeof(ixPCIE_STRAP_MISC[0]), 0, 0 },
+	{ "ixPCIE_STRAP_MISC2", REG_SMC, 0x14000c1, &ixPCIE_STRAP_MISC2[0], sizeof(ixPCIE_STRAP_MISC2)/sizeof(ixPCIE_STRAP_MISC2[0]), 0, 0 },
+	{ "ixPCIE_STRAP_PI", REG_SMC, 0x14000c2, &ixPCIE_STRAP_PI[0], sizeof(ixPCIE_STRAP_PI)/sizeof(ixPCIE_STRAP_PI[0]), 0, 0 },
+	{ "ixPCIE_STRAP_I2C_BD", REG_SMC, 0x14000c4, &ixPCIE_STRAP_I2C_BD[0], sizeof(ixPCIE_STRAP_I2C_BD)/sizeof(ixPCIE_STRAP_I2C_BD[0]), 0, 0 },
+	{ "ixPCIE_PRBS_CLR", REG_SMC, 0x14000c8, &ixPCIE_PRBS_CLR[0], sizeof(ixPCIE_PRBS_CLR)/sizeof(ixPCIE_PRBS_CLR[0]), 0, 0 },
+	{ "ixPCIE_PRBS_STATUS1", REG_SMC, 0x14000c9, &ixPCIE_PRBS_STATUS1[0], sizeof(ixPCIE_PRBS_STATUS1)/sizeof(ixPCIE_PRBS_STATUS1[0]), 0, 0 },
+	{ "ixPCIE_PRBS_STATUS2", REG_SMC, 0x14000ca, &ixPCIE_PRBS_STATUS2[0], sizeof(ixPCIE_PRBS_STATUS2)/sizeof(ixPCIE_PRBS_STATUS2[0]), 0, 0 },
+	{ "ixPCIE_PRBS_FREERUN", REG_SMC, 0x14000cb, &ixPCIE_PRBS_FREERUN[0], sizeof(ixPCIE_PRBS_FREERUN)/sizeof(ixPCIE_PRBS_FREERUN[0]), 0, 0 },
+	{ "ixPCIE_PRBS_MISC", REG_SMC, 0x14000cc, &ixPCIE_PRBS_MISC[0], sizeof(ixPCIE_PRBS_MISC)/sizeof(ixPCIE_PRBS_MISC[0]), 0, 0 },
+	{ "ixPCIE_PRBS_USER_PATTERN", REG_SMC, 0x14000cd, &ixPCIE_PRBS_USER_PATTERN[0], sizeof(ixPCIE_PRBS_USER_PATTERN)/sizeof(ixPCIE_PRBS_USER_PATTERN[0]), 0, 0 },
+	{ "ixPCIE_PRBS_LO_BITCNT", REG_SMC, 0x14000ce, &ixPCIE_PRBS_LO_BITCNT[0], sizeof(ixPCIE_PRBS_LO_BITCNT)/sizeof(ixPCIE_PRBS_LO_BITCNT[0]), 0, 0 },
+	{ "ixPCIE_PRBS_HI_BITCNT", REG_SMC, 0x14000cf, &ixPCIE_PRBS_HI_BITCNT[0], sizeof(ixPCIE_PRBS_HI_BITCNT)/sizeof(ixPCIE_PRBS_HI_BITCNT[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_0", REG_SMC, 0x14000d0, &ixPCIE_PRBS_ERRCNT_0[0], sizeof(ixPCIE_PRBS_ERRCNT_0)/sizeof(ixPCIE_PRBS_ERRCNT_0[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_1", REG_SMC, 0x14000d1, &ixPCIE_PRBS_ERRCNT_1[0], sizeof(ixPCIE_PRBS_ERRCNT_1)/sizeof(ixPCIE_PRBS_ERRCNT_1[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_2", REG_SMC, 0x14000d2, &ixPCIE_PRBS_ERRCNT_2[0], sizeof(ixPCIE_PRBS_ERRCNT_2)/sizeof(ixPCIE_PRBS_ERRCNT_2[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_3", REG_SMC, 0x14000d3, &ixPCIE_PRBS_ERRCNT_3[0], sizeof(ixPCIE_PRBS_ERRCNT_3)/sizeof(ixPCIE_PRBS_ERRCNT_3[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_4", REG_SMC, 0x14000d4, &ixPCIE_PRBS_ERRCNT_4[0], sizeof(ixPCIE_PRBS_ERRCNT_4)/sizeof(ixPCIE_PRBS_ERRCNT_4[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_5", REG_SMC, 0x14000d5, &ixPCIE_PRBS_ERRCNT_5[0], sizeof(ixPCIE_PRBS_ERRCNT_5)/sizeof(ixPCIE_PRBS_ERRCNT_5[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_6", REG_SMC, 0x14000d6, &ixPCIE_PRBS_ERRCNT_6[0], sizeof(ixPCIE_PRBS_ERRCNT_6)/sizeof(ixPCIE_PRBS_ERRCNT_6[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_7", REG_SMC, 0x14000d7, &ixPCIE_PRBS_ERRCNT_7[0], sizeof(ixPCIE_PRBS_ERRCNT_7)/sizeof(ixPCIE_PRBS_ERRCNT_7[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_8", REG_SMC, 0x14000d8, &ixPCIE_PRBS_ERRCNT_8[0], sizeof(ixPCIE_PRBS_ERRCNT_8)/sizeof(ixPCIE_PRBS_ERRCNT_8[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_9", REG_SMC, 0x14000d9, &ixPCIE_PRBS_ERRCNT_9[0], sizeof(ixPCIE_PRBS_ERRCNT_9)/sizeof(ixPCIE_PRBS_ERRCNT_9[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_10", REG_SMC, 0x14000da, &ixPCIE_PRBS_ERRCNT_10[0], sizeof(ixPCIE_PRBS_ERRCNT_10)/sizeof(ixPCIE_PRBS_ERRCNT_10[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_11", REG_SMC, 0x14000db, &ixPCIE_PRBS_ERRCNT_11[0], sizeof(ixPCIE_PRBS_ERRCNT_11)/sizeof(ixPCIE_PRBS_ERRCNT_11[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_12", REG_SMC, 0x14000dc, &ixPCIE_PRBS_ERRCNT_12[0], sizeof(ixPCIE_PRBS_ERRCNT_12)/sizeof(ixPCIE_PRBS_ERRCNT_12[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_13", REG_SMC, 0x14000dd, &ixPCIE_PRBS_ERRCNT_13[0], sizeof(ixPCIE_PRBS_ERRCNT_13)/sizeof(ixPCIE_PRBS_ERRCNT_13[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_14", REG_SMC, 0x14000de, &ixPCIE_PRBS_ERRCNT_14[0], sizeof(ixPCIE_PRBS_ERRCNT_14)/sizeof(ixPCIE_PRBS_ERRCNT_14[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_15", REG_SMC, 0x14000df, &ixPCIE_PRBS_ERRCNT_15[0], sizeof(ixPCIE_PRBS_ERRCNT_15)/sizeof(ixPCIE_PRBS_ERRCNT_15[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_CAP", REG_SMC, 0x14000e0, &ixPCIE_F0_DPA_CAP[0], sizeof(ixPCIE_F0_DPA_CAP)/sizeof(ixPCIE_F0_DPA_CAP[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_LATENCY_INDICATOR", REG_SMC, 0x14000e4, &ixPCIE_F0_DPA_LATENCY_INDICATOR[0], sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR)/sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_CNTL", REG_SMC, 0x14000e5, &ixPCIE_F0_DPA_CNTL[0], sizeof(ixPCIE_F0_DPA_CNTL)/sizeof(ixPCIE_F0_DPA_CNTL[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0", REG_SMC, 0x14000e7, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1", REG_SMC, 0x14000e8, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2", REG_SMC, 0x14000e9, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3", REG_SMC, 0x14000ea, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4", REG_SMC, 0x14000eb, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5", REG_SMC, 0x14000ec, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6", REG_SMC, 0x14000ed, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7", REG_SMC, 0x14000ee, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_CNTL", REG_MMIO, 0x1401, &mmGARLIC_FLUSH_CNTL[0], sizeof(mmGARLIC_FLUSH_CNTL)/sizeof(mmGARLIC_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_0", REG_MMIO, 0x1402, &mmGARLIC_FLUSH_ADDR_START_0[0], sizeof(mmGARLIC_FLUSH_ADDR_START_0)/sizeof(mmGARLIC_FLUSH_ADDR_START_0[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_0", REG_MMIO, 0x1403, &mmGARLIC_FLUSH_ADDR_END_0[0], sizeof(mmGARLIC_FLUSH_ADDR_END_0)/sizeof(mmGARLIC_FLUSH_ADDR_END_0[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_1", REG_MMIO, 0x1404, &mmGARLIC_FLUSH_ADDR_START_1[0], sizeof(mmGARLIC_FLUSH_ADDR_START_1)/sizeof(mmGARLIC_FLUSH_ADDR_START_1[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_1", REG_MMIO, 0x1405, &mmGARLIC_FLUSH_ADDR_END_1[0], sizeof(mmGARLIC_FLUSH_ADDR_END_1)/sizeof(mmGARLIC_FLUSH_ADDR_END_1[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_2", REG_MMIO, 0x1406, &mmGARLIC_FLUSH_ADDR_START_2[0], sizeof(mmGARLIC_FLUSH_ADDR_START_2)/sizeof(mmGARLIC_FLUSH_ADDR_START_2[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_2", REG_MMIO, 0x1407, &mmGARLIC_FLUSH_ADDR_END_2[0], sizeof(mmGARLIC_FLUSH_ADDR_END_2)/sizeof(mmGARLIC_FLUSH_ADDR_END_2[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_3", REG_MMIO, 0x1408, &mmGARLIC_FLUSH_ADDR_START_3[0], sizeof(mmGARLIC_FLUSH_ADDR_START_3)/sizeof(mmGARLIC_FLUSH_ADDR_START_3[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_3", REG_MMIO, 0x1409, &mmGARLIC_FLUSH_ADDR_END_3[0], sizeof(mmGARLIC_FLUSH_ADDR_END_3)/sizeof(mmGARLIC_FLUSH_ADDR_END_3[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_4", REG_MMIO, 0x140a, &mmGARLIC_FLUSH_ADDR_START_4[0], sizeof(mmGARLIC_FLUSH_ADDR_START_4)/sizeof(mmGARLIC_FLUSH_ADDR_START_4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_4", REG_MMIO, 0x140b, &mmGARLIC_FLUSH_ADDR_END_4[0], sizeof(mmGARLIC_FLUSH_ADDR_END_4)/sizeof(mmGARLIC_FLUSH_ADDR_END_4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_5", REG_MMIO, 0x140c, &mmGARLIC_FLUSH_ADDR_START_5[0], sizeof(mmGARLIC_FLUSH_ADDR_START_5)/sizeof(mmGARLIC_FLUSH_ADDR_START_5[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_5", REG_MMIO, 0x140d, &mmGARLIC_FLUSH_ADDR_END_5[0], sizeof(mmGARLIC_FLUSH_ADDR_END_5)/sizeof(mmGARLIC_FLUSH_ADDR_END_5[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_6", REG_MMIO, 0x140e, &mmGARLIC_FLUSH_ADDR_START_6[0], sizeof(mmGARLIC_FLUSH_ADDR_START_6)/sizeof(mmGARLIC_FLUSH_ADDR_START_6[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_6", REG_MMIO, 0x140f, &mmGARLIC_FLUSH_ADDR_END_6[0], sizeof(mmGARLIC_FLUSH_ADDR_END_6)/sizeof(mmGARLIC_FLUSH_ADDR_END_6[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_7", REG_MMIO, 0x1410, &mmGARLIC_FLUSH_ADDR_START_7[0], sizeof(mmGARLIC_FLUSH_ADDR_START_7)/sizeof(mmGARLIC_FLUSH_ADDR_START_7[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_7", REG_MMIO, 0x1411, &mmGARLIC_FLUSH_ADDR_END_7[0], sizeof(mmGARLIC_FLUSH_ADDR_END_7)/sizeof(mmGARLIC_FLUSH_ADDR_END_7[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_REQ", REG_MMIO, 0x1412, &mmGARLIC_FLUSH_REQ[0], sizeof(mmGARLIC_FLUSH_REQ)/sizeof(mmGARLIC_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_GARLIC_FLUSH_REQ", REG_MMIO, 0x1413, &mmGPU_GARLIC_FLUSH_REQ[0], sizeof(mmGPU_GARLIC_FLUSH_REQ)/sizeof(mmGPU_GARLIC_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_GARLIC_FLUSH_DONE", REG_MMIO, 0x1414, &mmGPU_GARLIC_FLUSH_DONE[0], sizeof(mmGPU_GARLIC_FLUSH_DONE)/sizeof(mmGPU_GARLIC_FLUSH_DONE[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_RB0_WPTR", REG_MMIO, 0x1415, &mmGARLIC_COHE_CP_RB0_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB0_WPTR)/sizeof(mmGARLIC_COHE_CP_RB0_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_RB1_WPTR", REG_MMIO, 0x1416, &mmGARLIC_COHE_CP_RB1_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB1_WPTR)/sizeof(mmGARLIC_COHE_CP_RB1_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_RB2_WPTR", REG_MMIO, 0x1417, &mmGARLIC_COHE_CP_RB2_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB2_WPTR)/sizeof(mmGARLIC_COHE_CP_RB2_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_UVD_RBC_RB_WPTR", REG_MMIO, 0x1418, &mmGARLIC_COHE_UVD_RBC_RB_WPTR[0], sizeof(mmGARLIC_COHE_UVD_RBC_RB_WPTR)/sizeof(mmGARLIC_COHE_UVD_RBC_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SDMA0_GFX_RB_WPTR", REG_MMIO, 0x1419, &mmGARLIC_COHE_SDMA0_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA0_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA0_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SDMA1_GFX_RB_WPTR", REG_MMIO, 0x141a, &mmGARLIC_COHE_SDMA1_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA1_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA1_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_DMA_ME_COMMAND", REG_MMIO, 0x141b, &mmGARLIC_COHE_CP_DMA_ME_COMMAND[0], sizeof(mmGARLIC_COHE_CP_DMA_ME_COMMAND)/sizeof(mmGARLIC_COHE_CP_DMA_ME_COMMAND[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_DMA_PFP_COMMAND", REG_MMIO, 0x141c, &mmGARLIC_COHE_CP_DMA_PFP_COMMAND[0], sizeof(mmGARLIC_COHE_CP_DMA_PFP_COMMAND)/sizeof(mmGARLIC_COHE_CP_DMA_PFP_COMMAND[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SAM_SAB_RBI_WPTR", REG_MMIO, 0x141d, &mmGARLIC_COHE_SAM_SAB_RBI_WPTR[0], sizeof(mmGARLIC_COHE_SAM_SAB_RBI_WPTR)/sizeof(mmGARLIC_COHE_SAM_SAB_RBI_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SAM_SAB_RBO_WPTR", REG_MMIO, 0x141e, &mmGARLIC_COHE_SAM_SAB_RBO_WPTR[0], sizeof(mmGARLIC_COHE_SAM_SAB_RBO_WPTR)/sizeof(mmGARLIC_COHE_SAM_SAB_RBO_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_VCE_OUT_RB_WPTR", REG_MMIO, 0x141f, &mmGARLIC_COHE_VCE_OUT_RB_WPTR[0], sizeof(mmGARLIC_COHE_VCE_OUT_RB_WPTR)/sizeof(mmGARLIC_COHE_VCE_OUT_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_VCE_RB_WPTR2", REG_MMIO, 0x1420, &mmGARLIC_COHE_VCE_RB_WPTR2[0], sizeof(mmGARLIC_COHE_VCE_RB_WPTR2)/sizeof(mmGARLIC_COHE_VCE_RB_WPTR2[0]), 0, 0 },
+	{ "mmGARLIC_COHE_VCE_RB_WPTR", REG_MMIO, 0x1421, &mmGARLIC_COHE_VCE_RB_WPTR[0], sizeof(mmGARLIC_COHE_VCE_RB_WPTR)/sizeof(mmGARLIC_COHE_VCE_RB_WPTR[0]), 0, 0 },
+	{ "mmBIF_RFE_SOFTRST_CNTL", REG_MMIO, 0x1441, &mmBIF_RFE_SOFTRST_CNTL[0], sizeof(mmBIF_RFE_SOFTRST_CNTL)/sizeof(mmBIF_RFE_SOFTRST_CNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_CLIENT_SOFTRST_TRIGGER", REG_MMIO, 0x1442, &mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[0], sizeof(mmBIF_RFE_CLIENT_SOFTRST_TRIGGER)/sizeof(mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[0]), 0, 0 },
+	{ "mmBIF_RFE_MASTER_SOFTRST_TRIGGER", REG_MMIO, 0x1443, &mmBIF_RFE_MASTER_SOFTRST_TRIGGER[0], sizeof(mmBIF_RFE_MASTER_SOFTRST_TRIGGER)/sizeof(mmBIF_RFE_MASTER_SOFTRST_TRIGGER[0]), 0, 0 },
+	{ "mmBIF_PWDN_COMMAND", REG_MMIO, 0x1444, &mmBIF_PWDN_COMMAND[0], sizeof(mmBIF_PWDN_COMMAND)/sizeof(mmBIF_PWDN_COMMAND[0]), 0, 0 },
+	{ "mmBIF_PWDN_STATUS", REG_MMIO, 0x1445, &mmBIF_PWDN_STATUS[0], sizeof(mmBIF_PWDN_STATUS)/sizeof(mmBIF_PWDN_STATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_BU_CMDSTATUS", REG_MMIO, 0x1446, &mmBIF_RFE_MST_BU_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_BU_CMDSTATUS)/sizeof(mmBIF_RFE_MST_BU_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS", REG_MMIO, 0x1447, &mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS)/sizeof(mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_BX_CMDSTATUS", REG_MMIO, 0x1448, &mmBIF_RFE_MST_BX_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_BX_CMDSTATUS)/sizeof(mmBIF_RFE_MST_BX_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_TMOUT_STATUS", REG_MMIO, 0x144b, &mmBIF_RFE_MST_TMOUT_STATUS[0], sizeof(mmBIF_RFE_MST_TMOUT_STATUS)/sizeof(mmBIF_RFE_MST_TMOUT_STATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MMCFG_CNTL", REG_MMIO, 0x144c, &mmBIF_RFE_MMCFG_CNTL[0], sizeof(mmBIF_RFE_MMCFG_CNTL)/sizeof(mmBIF_RFE_MMCFG_CNTL[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_SMPLCNTL", REG_MMIO, 0x1450, &mmBIF_IMPCTL_SMPLCNTL[0], sizeof(mmBIF_IMPCTL_SMPLCNTL)/sizeof(mmBIF_IMPCTL_SMPLCNTL[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_RXCNTL", REG_MMIO, 0x1451, &mmBIF_IMPCTL_RXCNTL[0], sizeof(mmBIF_IMPCTL_RXCNTL)/sizeof(mmBIF_IMPCTL_RXCNTL[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_TXCNTL_pd", REG_MMIO, 0x1452, &mmBIF_IMPCTL_TXCNTL_pd[0], sizeof(mmBIF_IMPCTL_TXCNTL_pd)/sizeof(mmBIF_IMPCTL_TXCNTL_pd[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_TXCNTL_pu", REG_MMIO, 0x1453, &mmBIF_IMPCTL_TXCNTL_pu[0], sizeof(mmBIF_IMPCTL_TXCNTL_pu)/sizeof(mmBIF_IMPCTL_TXCNTL_pu[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD", REG_MMIO, 0x1454, &mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD[0], sizeof(mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD)/sizeof(mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD[0]), 0, 0 },
+	{ "mmBIF_CC_RFE_IMP_OVERRIDECNTL", REG_MMIO, 0x1455, &mmBIF_CC_RFE_IMP_OVERRIDECNTL[0], sizeof(mmBIF_CC_RFE_IMP_OVERRIDECNTL)/sizeof(mmBIF_CC_RFE_IMP_OVERRIDECNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_IMPRST_CNTL", REG_MMIO, 0x1458, &mmBIF_RFE_IMPRST_CNTL[0], sizeof(mmBIF_RFE_IMPRST_CNTL)/sizeof(mmBIF_RFE_IMPRST_CNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_WARMRST_CNTL", REG_MMIO, 0x1459, &mmBIF_RFE_WARMRST_CNTL[0], sizeof(mmBIF_RFE_WARMRST_CNTL)/sizeof(mmBIF_RFE_WARMRST_CNTL[0]), 0, 0 },
+	{ "mmBIF_BACO_MSIC", REG_MMIO, 0x1480, &mmBIF_BACO_MSIC[0], sizeof(mmBIF_BACO_MSIC)/sizeof(mmBIF_BACO_MSIC[0]), 0, 0 },
+	{ "mmBIF_PIF_TXCLK_SWITCH_TIMER", REG_MMIO, 0x1481, &mmBIF_PIF_TXCLK_SWITCH_TIMER[0], sizeof(mmBIF_PIF_TXCLK_SWITCH_TIMER)/sizeof(mmBIF_PIF_TXCLK_SWITCH_TIMER[0]), 0, 0 },
+	{ "mmBIF_RESET_EN", REG_MMIO, 0x1482, &mmBIF_RESET_EN[0], sizeof(mmBIF_RESET_EN)/sizeof(mmBIF_RESET_EN[0]), 0, 0 },
+	{ "mmBIF_CLK_PDWN_DELAY_TIMER", REG_MMIO, 0x1483, &mmBIF_CLK_PDWN_DELAY_TIMER[0], sizeof(mmBIF_CLK_PDWN_DELAY_TIMER)/sizeof(mmBIF_CLK_PDWN_DELAY_TIMER[0]), 0, 0 },
+	{ "mmNEW_REFCLKB_TIMER_1", REG_MMIO, 0x1484, &mmNEW_REFCLKB_TIMER_1[0], sizeof(mmNEW_REFCLKB_TIMER_1)/sizeof(mmNEW_REFCLKB_TIMER_1[0]), 0, 0 },
+	{ "mmNEW_REFCLKB_TIMER", REG_MMIO, 0x1485, &mmNEW_REFCLKB_TIMER[0], sizeof(mmNEW_REFCLKB_TIMER)/sizeof(mmNEW_REFCLKB_TIMER[0]), 0, 0 },
+	{ "mmBIF_RESET_CNTL", REG_MMIO, 0x1486, &mmBIF_RESET_CNTL[0], sizeof(mmBIF_RESET_CNTL)/sizeof(mmBIF_RESET_CNTL[0]), 0, 0 },
+	{ "mmLNCNT_CONTROL", REG_MMIO, 0x1487, &mmLNCNT_CONTROL[0], sizeof(mmLNCNT_CONTROL)/sizeof(mmLNCNT_CONTROL[0]), 0, 0 },
+	{ "mmBIF_LNCNT_RESET", REG_MMIO, 0x1488, &mmBIF_LNCNT_RESET[0], sizeof(mmBIF_LNCNT_RESET)/sizeof(mmBIF_LNCNT_RESET[0]), 0, 0 },
+	{ "mmBIF_CLOCKS_BITS", REG_MMIO, 0x1489, &mmBIF_CLOCKS_BITS[0], sizeof(mmBIF_CLOCKS_BITS)/sizeof(mmBIF_CLOCKS_BITS[0]), 0, 0 },
+	{ "mmBIF_RFE_CNTL_MISC", REG_MMIO, 0x148c, &mmBIF_RFE_CNTL_MISC[0], sizeof(mmBIF_RFE_CNTL_MISC)/sizeof(mmBIF_RFE_CNTL_MISC[0]), 0, 0 },
+	{ "mmBIF_XDMA_LO", REG_MMIO, 0x14c0, &mmBIF_XDMA_LO[0], sizeof(mmBIF_XDMA_LO)/sizeof(mmBIF_XDMA_LO[0]), 0, 0 },
+	{ "mmBIF_XDMA_HI", REG_MMIO, 0x14c1, &mmBIF_XDMA_HI[0], sizeof(mmBIF_XDMA_HI)/sizeof(mmBIF_XDMA_HI[0]), 0, 0 },
+	{ "mmBIF_FEATURES_CONTROL_MISC", REG_MMIO, 0x14c2, &mmBIF_FEATURES_CONTROL_MISC[0], sizeof(mmBIF_FEATURES_CONTROL_MISC)/sizeof(mmBIF_FEATURES_CONTROL_MISC[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_CNTL", REG_MMIO, 0x14c3, &mmBIF_DOORBELL_CNTL[0], sizeof(mmBIF_DOORBELL_CNTL)/sizeof(mmBIF_DOORBELL_CNTL[0]), 0, 0 },
+	{ "mmBIF_SLVARB_MODE", REG_MMIO, 0x14c4, &mmBIF_SLVARB_MODE[0], sizeof(mmBIF_SLVARB_MODE)/sizeof(mmBIF_SLVARB_MODE[0]), 0, 0 },
+	{ "mmSMBUS_BACO_DUMMY", REG_MMIO, 0x14c6, &mmSMBUS_BACO_DUMMY[0], sizeof(mmSMBUS_BACO_DUMMY)/sizeof(mmSMBUS_BACO_DUMMY[0]), 0, 0 },
+	{ "mmBF_ANA_ISO_CNTL", REG_MMIO, 0x14c7, &mmBF_ANA_ISO_CNTL[0], sizeof(mmBF_ANA_ISO_CNTL)/sizeof(mmBF_ANA_ISO_CNTL[0]), 0, 0 },
+	{ "mmBIF_SSA_PWR_STATUS", REG_MMIO, 0x14c8, &mmBIF_SSA_PWR_STATUS[0], sizeof(mmBIF_SSA_PWR_STATUS)/sizeof(mmBIF_SSA_PWR_STATUS[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX0_LOWER", REG_MMIO, 0x14ca, &mmBIF_SSA_GFX0_LOWER[0], sizeof(mmBIF_SSA_GFX0_LOWER)/sizeof(mmBIF_SSA_GFX0_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX0_UPPER", REG_MMIO, 0x14cb, &mmBIF_SSA_GFX0_UPPER[0], sizeof(mmBIF_SSA_GFX0_UPPER)/sizeof(mmBIF_SSA_GFX0_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX1_LOWER", REG_MMIO, 0x14cc, &mmBIF_SSA_GFX1_LOWER[0], sizeof(mmBIF_SSA_GFX1_LOWER)/sizeof(mmBIF_SSA_GFX1_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX1_UPPER", REG_MMIO, 0x14cd, &mmBIF_SSA_GFX1_UPPER[0], sizeof(mmBIF_SSA_GFX1_UPPER)/sizeof(mmBIF_SSA_GFX1_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX2_LOWER", REG_MMIO, 0x14ce, &mmBIF_SSA_GFX2_LOWER[0], sizeof(mmBIF_SSA_GFX2_LOWER)/sizeof(mmBIF_SSA_GFX2_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX2_UPPER", REG_MMIO, 0x14cf, &mmBIF_SSA_GFX2_UPPER[0], sizeof(mmBIF_SSA_GFX2_UPPER)/sizeof(mmBIF_SSA_GFX2_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX3_LOWER", REG_MMIO, 0x14d0, &mmBIF_SSA_GFX3_LOWER[0], sizeof(mmBIF_SSA_GFX3_LOWER)/sizeof(mmBIF_SSA_GFX3_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_GFX3_UPPER", REG_MMIO, 0x14d1, &mmBIF_SSA_GFX3_UPPER[0], sizeof(mmBIF_SSA_GFX3_UPPER)/sizeof(mmBIF_SSA_GFX3_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_DISP_LOWER", REG_MMIO, 0x14d2, &mmBIF_SSA_DISP_LOWER[0], sizeof(mmBIF_SSA_DISP_LOWER)/sizeof(mmBIF_SSA_DISP_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_DISP_UPPER", REG_MMIO, 0x14d3, &mmBIF_SSA_DISP_UPPER[0], sizeof(mmBIF_SSA_DISP_UPPER)/sizeof(mmBIF_SSA_DISP_UPPER[0]), 0, 0 },
+	{ "mmBIF_SSA_MC_LOWER", REG_MMIO, 0x14d4, &mmBIF_SSA_MC_LOWER[0], sizeof(mmBIF_SSA_MC_LOWER)/sizeof(mmBIF_SSA_MC_LOWER[0]), 0, 0 },
+	{ "mmBIF_SSA_MC_UPPER", REG_MMIO, 0x14d5, &mmBIF_SSA_MC_UPPER[0], sizeof(mmBIF_SSA_MC_UPPER)/sizeof(mmBIF_SSA_MC_UPPER[0]), 0, 0 },
+	{ "mmBACO_CNTL_MISC", REG_MMIO, 0x14db, &mmBACO_CNTL_MISC[0], sizeof(mmBACO_CNTL_MISC)/sizeof(mmBACO_CNTL_MISC[0]), 0, 0 },
+	{ "mmBIF_BACO_DEBUG_LATCH", REG_MMIO, 0x14dc, &mmBIF_BACO_DEBUG_LATCH[0], sizeof(mmBIF_BACO_DEBUG_LATCH)/sizeof(mmBIF_BACO_DEBUG_LATCH[0]), 0, 0 },
+	{ "mmBIF_BACO_DEBUG", REG_MMIO, 0x14df, &mmBIF_BACO_DEBUG[0], sizeof(mmBIF_BACO_DEBUG)/sizeof(mmBIF_BACO_DEBUG[0]), 0, 0 },
+	{ "mmMEM_TYPE_CNTL", REG_MMIO, 0x14e4, &mmMEM_TYPE_CNTL[0], sizeof(mmMEM_TYPE_CNTL)/sizeof(mmMEM_TYPE_CNTL[0]), 0, 0 },
+	{ "mmBACO_CNTL", REG_MMIO, 0x14e5, &mmBACO_CNTL[0], sizeof(mmBACO_CNTL)/sizeof(mmBACO_CNTL[0]), 0, 0 },
+	{ "mmBIF_DEVFUNCNUM_LIST1", REG_MMIO, 0x14e7, &mmBIF_DEVFUNCNUM_LIST1[0], sizeof(mmBIF_DEVFUNCNUM_LIST1)/sizeof(mmBIF_DEVFUNCNUM_LIST1[0]), 0, 0 },
+	{ "mmBIF_DEVFUNCNUM_LIST0", REG_MMIO, 0x14e8, &mmBIF_DEVFUNCNUM_LIST0[0], sizeof(mmBIF_DEVFUNCNUM_LIST0)/sizeof(mmBIF_DEVFUNCNUM_LIST0[0]), 0, 0 },
+	{ "mmDBG_BYPASS_SRBM_ACCESS", REG_MMIO, 0x14eb, &mmDBG_BYPASS_SRBM_ACCESS[0], sizeof(mmDBG_BYPASS_SRBM_ACCESS)/sizeof(mmDBG_BYPASS_SRBM_ACCESS[0]), 0, 0 },
+	{ "mmPEER3_FB_OFFSET_LO", REG_MMIO, 0x14ec, &mmPEER3_FB_OFFSET_LO[0], sizeof(mmPEER3_FB_OFFSET_LO)/sizeof(mmPEER3_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER3_FB_OFFSET_HI", REG_MMIO, 0x14ed, &mmPEER3_FB_OFFSET_HI[0], sizeof(mmPEER3_FB_OFFSET_HI)/sizeof(mmPEER3_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER2_FB_OFFSET_LO", REG_MMIO, 0x14ee, &mmPEER2_FB_OFFSET_LO[0], sizeof(mmPEER2_FB_OFFSET_LO)/sizeof(mmPEER2_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER2_FB_OFFSET_HI", REG_MMIO, 0x14ef, &mmPEER2_FB_OFFSET_HI[0], sizeof(mmPEER2_FB_OFFSET_HI)/sizeof(mmPEER2_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER1_FB_OFFSET_LO", REG_MMIO, 0x14f0, &mmPEER1_FB_OFFSET_LO[0], sizeof(mmPEER1_FB_OFFSET_LO)/sizeof(mmPEER1_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER1_FB_OFFSET_HI", REG_MMIO, 0x14f1, &mmPEER1_FB_OFFSET_HI[0], sizeof(mmPEER1_FB_OFFSET_HI)/sizeof(mmPEER1_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER0_FB_OFFSET_LO", REG_MMIO, 0x14f2, &mmPEER0_FB_OFFSET_LO[0], sizeof(mmPEER0_FB_OFFSET_LO)/sizeof(mmPEER0_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER0_FB_OFFSET_HI", REG_MMIO, 0x14f3, &mmPEER0_FB_OFFSET_HI[0], sizeof(mmPEER0_FB_OFFSET_HI)/sizeof(mmPEER0_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmIMPCTL_RESET", REG_MMIO, 0x14f5, &mmIMPCTL_RESET[0], sizeof(mmIMPCTL_RESET)/sizeof(mmIMPCTL_RESET[0]), 0, 0 },
+	{ "mmSMBUS_SLV_CNTL", REG_MMIO, 0x14fd, &mmSMBUS_SLV_CNTL[0], sizeof(mmSMBUS_SLV_CNTL)/sizeof(mmSMBUS_SLV_CNTL[0]), 0, 0 },
+	{ "mmSMBUS_SLV_CNTL1", REG_MMIO, 0x14fe, &mmSMBUS_SLV_CNTL1[0], sizeof(mmSMBUS_SLV_CNTL1)/sizeof(mmSMBUS_SLV_CNTL1[0]), 0, 0 },
+	{ "mmPMI_STATUS_CNTL", REG_MMIO, 0x15, &mmPMI_STATUS_CNTL[0], sizeof(mmPMI_STATUS_CNTL)/sizeof(mmPMI_STATUS_CNTL[0]), 0, 0 },
+	{ "mmBUS_CNTL", REG_MMIO, 0x1508, &mmBUS_CNTL[0], sizeof(mmBUS_CNTL)/sizeof(mmBUS_CNTL[0]), 0, 0 },
+	{ "mmCONFIG_CNTL", REG_MMIO, 0x1509, &mmCONFIG_CNTL[0], sizeof(mmCONFIG_CNTL)/sizeof(mmCONFIG_CNTL[0]), 0, 0 },
+	{ "mmCONFIG_MEMSIZE", REG_MMIO, 0x150a, &mmCONFIG_MEMSIZE[0], sizeof(mmCONFIG_MEMSIZE)/sizeof(mmCONFIG_MEMSIZE[0]), 0, 0 },
+	{ "mmCONFIG_F0_BASE", REG_MMIO, 0x150b, &mmCONFIG_F0_BASE[0], sizeof(mmCONFIG_F0_BASE)/sizeof(mmCONFIG_F0_BASE[0]), 0, 0 },
+	{ "mmCONFIG_APER_SIZE", REG_MMIO, 0x150c, &mmCONFIG_APER_SIZE[0], sizeof(mmCONFIG_APER_SIZE)/sizeof(mmCONFIG_APER_SIZE[0]), 0, 0 },
+	{ "mmCONFIG_REG_APER_SIZE", REG_MMIO, 0x150d, &mmCONFIG_REG_APER_SIZE[0], sizeof(mmCONFIG_REG_APER_SIZE)/sizeof(mmCONFIG_REG_APER_SIZE[0]), 0, 0 },
+	{ "mmBIF_SCRATCH0", REG_MMIO, 0x150e, &mmBIF_SCRATCH0[0], sizeof(mmBIF_SCRATCH0)/sizeof(mmBIF_SCRATCH0[0]), 0, 0 },
+	{ "mmBIF_SCRATCH1", REG_MMIO, 0x150f, &mmBIF_SCRATCH1[0], sizeof(mmBIF_SCRATCH1)/sizeof(mmBIF_SCRATCH1[0]), 0, 0 },
+	{ "mmMM_CFGREGS_CNTL", REG_MMIO, 0x1513, &mmMM_CFGREGS_CNTL[0], sizeof(mmMM_CFGREGS_CNTL)/sizeof(mmMM_CFGREGS_CNTL[0]), 0, 0 },
+	{ "mmBX_RESET_EN", REG_MMIO, 0x1514, &mmBX_RESET_EN[0], sizeof(mmBX_RESET_EN)/sizeof(mmBX_RESET_EN[0]), 0, 0 },
+	{ "mmHW_DEBUG", REG_MMIO, 0x1515, &mmHW_DEBUG[0], sizeof(mmHW_DEBUG)/sizeof(mmHW_DEBUG[0]), 0, 0 },
+	{ "mmMASTER_CREDIT_CNTL", REG_MMIO, 0x1516, &mmMASTER_CREDIT_CNTL[0], sizeof(mmMASTER_CREDIT_CNTL)/sizeof(mmMASTER_CREDIT_CNTL[0]), 0, 0 },
+	{ "mmSLAVE_REQ_CREDIT_CNTL", REG_MMIO, 0x1517, &mmSLAVE_REQ_CREDIT_CNTL[0], sizeof(mmSLAVE_REQ_CREDIT_CNTL)/sizeof(mmSLAVE_REQ_CREDIT_CNTL[0]), 0, 0 },
+	{ "mmBX_RESET_CNTL", REG_MMIO, 0x1518, &mmBX_RESET_CNTL[0], sizeof(mmBX_RESET_CNTL)/sizeof(mmBX_RESET_CNTL[0]), 0, 0 },
+	{ "mmINTERRUPT_CNTL", REG_MMIO, 0x151a, &mmINTERRUPT_CNTL[0], sizeof(mmINTERRUPT_CNTL)/sizeof(mmINTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmINTERRUPT_CNTL2", REG_MMIO, 0x151b, &mmINTERRUPT_CNTL2[0], sizeof(mmINTERRUPT_CNTL2)/sizeof(mmINTERRUPT_CNTL2[0]), 0, 0 },
+	{ "mmBIF_DEBUG_CNTL", REG_MMIO, 0x151c, &mmBIF_DEBUG_CNTL[0], sizeof(mmBIF_DEBUG_CNTL)/sizeof(mmBIF_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmBIF_DEBUG_MUX", REG_MMIO, 0x151d, &mmBIF_DEBUG_MUX[0], sizeof(mmBIF_DEBUG_MUX)/sizeof(mmBIF_DEBUG_MUX[0]), 0, 0 },
+	{ "mmBIF_DEBUG_OUT", REG_MMIO, 0x151e, &mmBIF_DEBUG_OUT[0], sizeof(mmBIF_DEBUG_OUT)/sizeof(mmBIF_DEBUG_OUT[0]), 0, 0 },
+	{ "mmHDP_MEM_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1520, &mmHDP_MEM_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmCLKREQB_PAD_CNTL", REG_MMIO, 0x1521, &mmCLKREQB_PAD_CNTL[0], sizeof(mmCLKREQB_PAD_CNTL)/sizeof(mmCLKREQB_PAD_CNTL[0]), 0, 0 },
+	{ "mmSMBDAT_PAD_CNTL", REG_MMIO, 0x1522, &mmSMBDAT_PAD_CNTL[0], sizeof(mmSMBDAT_PAD_CNTL)/sizeof(mmSMBDAT_PAD_CNTL[0]), 0, 0 },
+	{ "mmSMBCLK_PAD_CNTL", REG_MMIO, 0x1523, &mmSMBCLK_PAD_CNTL[0], sizeof(mmSMBCLK_PAD_CNTL)/sizeof(mmSMBCLK_PAD_CNTL[0]), 0, 0 },
+	{ "mmBIF_FB_EN", REG_MMIO, 0x1524, &mmBIF_FB_EN[0], sizeof(mmBIF_FB_EN)/sizeof(mmBIF_FB_EN[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_CNTL1", REG_MMIO, 0x1525, &mmBIF_BUSNUM_CNTL1[0], sizeof(mmBIF_BUSNUM_CNTL1)/sizeof(mmBIF_BUSNUM_CNTL1[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_LIST0", REG_MMIO, 0x1526, &mmBIF_BUSNUM_LIST0[0], sizeof(mmBIF_BUSNUM_LIST0)/sizeof(mmBIF_BUSNUM_LIST0[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_LIST1", REG_MMIO, 0x1527, &mmBIF_BUSNUM_LIST1[0], sizeof(mmBIF_BUSNUM_LIST1)/sizeof(mmBIF_BUSNUM_LIST1[0]), 0, 0 },
+	{ "mmHDP_REG_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1528, &mmHDP_REG_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmBIF_BUSY_DELAY_CNTR", REG_MMIO, 0x1529, &mmBIF_BUSY_DELAY_CNTR[0], sizeof(mmBIF_BUSY_DELAY_CNTR)/sizeof(mmBIF_BUSY_DELAY_CNTR[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_CNTL2", REG_MMIO, 0x152b, &mmBIF_BUSNUM_CNTL2[0], sizeof(mmBIF_BUSNUM_CNTL2)/sizeof(mmBIF_BUSNUM_CNTL2[0]), 0, 0 },
+	{ "mmBIF_PERFMON_CNTL", REG_MMIO, 0x152c, &mmBIF_PERFMON_CNTL[0], sizeof(mmBIF_PERFMON_CNTL)/sizeof(mmBIF_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmBIF_PERFCOUNTER0_RESULT", REG_MMIO, 0x152d, &mmBIF_PERFCOUNTER0_RESULT[0], sizeof(mmBIF_PERFCOUNTER0_RESULT)/sizeof(mmBIF_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmBIF_PERFCOUNTER1_RESULT", REG_MMIO, 0x152e, &mmBIF_PERFCOUNTER1_RESULT[0], sizeof(mmBIF_PERFCOUNTER1_RESULT)/sizeof(mmBIF_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmSLAVE_HANG_PROTECTION_CNTL", REG_MMIO, 0x1536, &mmSLAVE_HANG_PROTECTION_CNTL[0], sizeof(mmSLAVE_HANG_PROTECTION_CNTL)/sizeof(mmSLAVE_HANG_PROTECTION_CNTL[0]), 0, 0 },
+	{ "mmGPU_HDP_FLUSH_REQ", REG_MMIO, 0x1537, &mmGPU_HDP_FLUSH_REQ[0], sizeof(mmGPU_HDP_FLUSH_REQ)/sizeof(mmGPU_HDP_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_HDP_FLUSH_DONE", REG_MMIO, 0x1538, &mmGPU_HDP_FLUSH_DONE[0], sizeof(mmGPU_HDP_FLUSH_DONE)/sizeof(mmGPU_HDP_FLUSH_DONE[0]), 0, 0 },
+	{ "mmSLAVE_HANG_ERROR", REG_MMIO, 0x153b, &mmSLAVE_HANG_ERROR[0], sizeof(mmSLAVE_HANG_ERROR)/sizeof(mmSLAVE_HANG_ERROR[0]), 0, 0 },
+	{ "mmCAPTURE_HOST_BUSNUM", REG_MMIO, 0x153c, &mmCAPTURE_HOST_BUSNUM[0], sizeof(mmCAPTURE_HOST_BUSNUM)/sizeof(mmCAPTURE_HOST_BUSNUM[0]), 0, 0 },
+	{ "mmHOST_BUSNUM", REG_MMIO, 0x153d, &mmHOST_BUSNUM[0], sizeof(mmHOST_BUSNUM)/sizeof(mmHOST_BUSNUM[0]), 0, 0 },
+	{ "mmPEER_REG_RANGE0", REG_MMIO, 0x153e, &mmPEER_REG_RANGE0[0], sizeof(mmPEER_REG_RANGE0)/sizeof(mmPEER_REG_RANGE0[0]), 0, 0 },
+	{ "mmPEER_REG_RANGE1", REG_MMIO, 0x153f, &mmPEER_REG_RANGE1[0], sizeof(mmPEER_REG_RANGE1)/sizeof(mmPEER_REG_RANGE1[0]), 0, 0 },
+	{ "mmPCIE_CAP_LIST", REG_MMIO, 0x16, &mmPCIE_CAP_LIST[0], sizeof(mmPCIE_CAP_LIST)/sizeof(mmPCIE_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_CAP", REG_MMIO, 0x16, &mmPCIE_CAP[0], sizeof(mmPCIE_CAP)/sizeof(mmPCIE_CAP[0]), 0, 0 },
+	{ "mmDEVICE_CAP", REG_MMIO, 0x17, &mmDEVICE_CAP[0], sizeof(mmDEVICE_CAP)/sizeof(mmDEVICE_CAP[0]), 0, 0 },
+	{ "mmDEVICE_STATUS", REG_MMIO, 0x18, &mmDEVICE_STATUS[0], sizeof(mmDEVICE_STATUS)/sizeof(mmDEVICE_STATUS[0]), 0, 0 },
+	{ "mmDEVICE_CNTL", REG_MMIO, 0x18, &mmDEVICE_CNTL[0], sizeof(mmDEVICE_CNTL)/sizeof(mmDEVICE_CNTL[0]), 0, 0 },
+	{ "mmLINK_CAP", REG_MMIO, 0x19, &mmLINK_CAP[0], sizeof(mmLINK_CAP)/sizeof(mmLINK_CAP[0]), 0, 0 },
+	{ "mmLINK_STATUS", REG_MMIO, 0x1a, &mmLINK_STATUS[0], sizeof(mmLINK_STATUS)/sizeof(mmLINK_STATUS[0]), 0, 0 },
+	{ "mmLINK_CNTL", REG_MMIO, 0x1a, &mmLINK_CNTL[0], sizeof(mmLINK_CNTL)/sizeof(mmLINK_CNTL[0]), 0, 0 },
+	{ "mmDEVICE_CAP2", REG_MMIO, 0x1f, &mmDEVICE_CAP2[0], sizeof(mmDEVICE_CAP2)/sizeof(mmDEVICE_CAP2[0]), 0, 0 },
+	{ "mmPROG_INTERFACE", REG_MMIO, 0x2, &mmPROG_INTERFACE[0], sizeof(mmPROG_INTERFACE)/sizeof(mmPROG_INTERFACE[0]), 0, 0 },
+	{ "mmREVISION_ID", REG_MMIO, 0x2, &mmREVISION_ID[0], sizeof(mmREVISION_ID)/sizeof(mmREVISION_ID[0]), 0, 0 },
+	{ "mmBASE_CLASS", REG_MMIO, 0x2, &mmBASE_CLASS[0], sizeof(mmBASE_CLASS)/sizeof(mmBASE_CLASS[0]), 0, 0 },
+	{ "mmSUB_CLASS", REG_MMIO, 0x2, &mmSUB_CLASS[0], sizeof(mmSUB_CLASS)/sizeof(mmSUB_CLASS[0]), 0, 0 },
+	{ "mmDEVICE_STATUS2", REG_MMIO, 0x20, &mmDEVICE_STATUS2[0], sizeof(mmDEVICE_STATUS2)/sizeof(mmDEVICE_STATUS2[0]), 0, 0 },
+	{ "mmDEVICE_CNTL2", REG_MMIO, 0x20, &mmDEVICE_CNTL2[0], sizeof(mmDEVICE_CNTL2)/sizeof(mmDEVICE_CNTL2[0]), 0, 0 },
+	{ "mmLINK_CAP2", REG_MMIO, 0x21, &mmLINK_CAP2[0], sizeof(mmLINK_CAP2)/sizeof(mmLINK_CAP2[0]), 0, 0 },
+	{ "ixPB1_PIF_SCRATCH", REG_SMC, 0x2100001, &ixPB1_PIF_SCRATCH[0], sizeof(ixPB1_PIF_SCRATCH)/sizeof(ixPB1_PIF_SCRATCH[0]), 0, 0 },
+	{ "ixPB1_PIF_HW_DEBUG", REG_SMC, 0x2100002, &ixPB1_PIF_HW_DEBUG[0], sizeof(ixPB1_PIF_HW_DEBUG)/sizeof(ixPB1_PIF_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB1_PIF_PRG6", REG_SMC, 0x2100003, &ixPB1_PIF_PRG6[0], sizeof(ixPB1_PIF_PRG6)/sizeof(ixPB1_PIF_PRG6[0]), 0, 0 },
+	{ "ixPB1_PIF_PRG7", REG_SMC, 0x2100004, &ixPB1_PIF_PRG7[0], sizeof(ixPB1_PIF_PRG7)/sizeof(ixPB1_PIF_PRG7[0]), 0, 0 },
+	{ "ixPB1_PIF_CNTL", REG_SMC, 0x2100010, &ixPB1_PIF_CNTL[0], sizeof(ixPB1_PIF_CNTL)/sizeof(ixPB1_PIF_CNTL[0]), 0, 0 },
+	{ "ixPB1_PIF_PAIRING", REG_SMC, 0x2100011, &ixPB1_PIF_PAIRING[0], sizeof(ixPB1_PIF_PAIRING)/sizeof(ixPB1_PIF_PAIRING[0]), 0, 0 },
+	{ "ixPB1_PIF_PWRDOWN_0", REG_SMC, 0x2100012, &ixPB1_PIF_PWRDOWN_0[0], sizeof(ixPB1_PIF_PWRDOWN_0)/sizeof(ixPB1_PIF_PWRDOWN_0[0]), 0, 0 },
+	{ "ixPB1_PIF_PWRDOWN_1", REG_SMC, 0x2100013, &ixPB1_PIF_PWRDOWN_1[0], sizeof(ixPB1_PIF_PWRDOWN_1)/sizeof(ixPB1_PIF_PWRDOWN_1[0]), 0, 0 },
+	{ "ixPB1_PIF_CNTL2", REG_SMC, 0x2100014, &ixPB1_PIF_CNTL2[0], sizeof(ixPB1_PIF_CNTL2)/sizeof(ixPB1_PIF_CNTL2[0]), 0, 0 },
+	{ "ixPB1_PIF_TXPHYSTATUS", REG_SMC, 0x2100015, &ixPB1_PIF_TXPHYSTATUS[0], sizeof(ixPB1_PIF_TXPHYSTATUS)/sizeof(ixPB1_PIF_TXPHYSTATUS[0]), 0, 0 },
+	{ "ixPB1_PIF_SC_CTL", REG_SMC, 0x2100016, &ixPB1_PIF_SC_CTL[0], sizeof(ixPB1_PIF_SC_CTL)/sizeof(ixPB1_PIF_SC_CTL[0]), 0, 0 },
+	{ "ixPB1_PIF_PWRDOWN_2", REG_SMC, 0x2100017, &ixPB1_PIF_PWRDOWN_2[0], sizeof(ixPB1_PIF_PWRDOWN_2)/sizeof(ixPB1_PIF_PWRDOWN_2[0]), 0, 0 },
+	{ "ixPB1_PIF_PWRDOWN_3", REG_SMC, 0x2100018, &ixPB1_PIF_PWRDOWN_3[0], sizeof(ixPB1_PIF_PWRDOWN_3)/sizeof(ixPB1_PIF_PWRDOWN_3[0]), 0, 0 },
+	{ "ixPB1_PIF_SC_CTL2", REG_SMC, 0x2100019, &ixPB1_PIF_SC_CTL2[0], sizeof(ixPB1_PIF_SC_CTL2)/sizeof(ixPB1_PIF_SC_CTL2[0]), 0, 0 },
+	{ "ixPB1_PIF_PRG0", REG_SMC, 0x210001a, &ixPB1_PIF_PRG0[0], sizeof(ixPB1_PIF_PRG0)/sizeof(ixPB1_PIF_PRG0[0]), 0, 0 },
+	{ "ixPB1_PIF_PRG1", REG_SMC, 0x210001b, &ixPB1_PIF_PRG1[0], sizeof(ixPB1_PIF_PRG1)/sizeof(ixPB1_PIF_PRG1[0]), 0, 0 },
+	{ "ixPB1_PIF_PRG2", REG_SMC, 0x210001c, &ixPB1_PIF_PRG2[0], sizeof(ixPB1_PIF_PRG2)/sizeof(ixPB1_PIF_PRG2[0]), 0, 0 },
+	{ "ixPB1_PIF_PRG3", REG_SMC, 0x210001d, &ixPB1_PIF_PRG3[0], sizeof(ixPB1_PIF_PRG3)/sizeof(ixPB1_PIF_PRG3[0]), 0, 0 },
+	{ "ixPB1_PIF_PRG4", REG_SMC, 0x210001e, &ixPB1_PIF_PRG4[0], sizeof(ixPB1_PIF_PRG4)/sizeof(ixPB1_PIF_PRG4[0]), 0, 0 },
+	{ "ixPB1_PIF_PRG5", REG_SMC, 0x210001f, &ixPB1_PIF_PRG5[0], sizeof(ixPB1_PIF_PRG5)/sizeof(ixPB1_PIF_PRG5[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_0", REG_SMC, 0x2100020, &ixPB1_PIF_PDNB_OVERRIDE_0[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_0)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_0[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_1", REG_SMC, 0x2100021, &ixPB1_PIF_PDNB_OVERRIDE_1[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_1)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_1[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_2", REG_SMC, 0x2100022, &ixPB1_PIF_PDNB_OVERRIDE_2[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_2)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_2[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_3", REG_SMC, 0x2100023, &ixPB1_PIF_PDNB_OVERRIDE_3[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_3)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_3[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_4", REG_SMC, 0x2100024, &ixPB1_PIF_PDNB_OVERRIDE_4[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_4)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_4[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_5", REG_SMC, 0x2100025, &ixPB1_PIF_PDNB_OVERRIDE_5[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_5)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_5[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_6", REG_SMC, 0x2100026, &ixPB1_PIF_PDNB_OVERRIDE_6[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_6)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_6[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_7", REG_SMC, 0x2100027, &ixPB1_PIF_PDNB_OVERRIDE_7[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_7)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_7[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_0", REG_SMC, 0x2100028, &ixPB1_PIF_SEQ_STATUS_0[0], sizeof(ixPB1_PIF_SEQ_STATUS_0)/sizeof(ixPB1_PIF_SEQ_STATUS_0[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_1", REG_SMC, 0x2100029, &ixPB1_PIF_SEQ_STATUS_1[0], sizeof(ixPB1_PIF_SEQ_STATUS_1)/sizeof(ixPB1_PIF_SEQ_STATUS_1[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_2", REG_SMC, 0x210002a, &ixPB1_PIF_SEQ_STATUS_2[0], sizeof(ixPB1_PIF_SEQ_STATUS_2)/sizeof(ixPB1_PIF_SEQ_STATUS_2[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_3", REG_SMC, 0x210002b, &ixPB1_PIF_SEQ_STATUS_3[0], sizeof(ixPB1_PIF_SEQ_STATUS_3)/sizeof(ixPB1_PIF_SEQ_STATUS_3[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_4", REG_SMC, 0x210002c, &ixPB1_PIF_SEQ_STATUS_4[0], sizeof(ixPB1_PIF_SEQ_STATUS_4)/sizeof(ixPB1_PIF_SEQ_STATUS_4[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_5", REG_SMC, 0x210002d, &ixPB1_PIF_SEQ_STATUS_5[0], sizeof(ixPB1_PIF_SEQ_STATUS_5)/sizeof(ixPB1_PIF_SEQ_STATUS_5[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_6", REG_SMC, 0x210002e, &ixPB1_PIF_SEQ_STATUS_6[0], sizeof(ixPB1_PIF_SEQ_STATUS_6)/sizeof(ixPB1_PIF_SEQ_STATUS_6[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_7", REG_SMC, 0x210002f, &ixPB1_PIF_SEQ_STATUS_7[0], sizeof(ixPB1_PIF_SEQ_STATUS_7)/sizeof(ixPB1_PIF_SEQ_STATUS_7[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_8", REG_SMC, 0x2100030, &ixPB1_PIF_PDNB_OVERRIDE_8[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_8)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_8[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_9", REG_SMC, 0x2100031, &ixPB1_PIF_PDNB_OVERRIDE_9[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_9)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_9[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_10", REG_SMC, 0x2100032, &ixPB1_PIF_PDNB_OVERRIDE_10[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_10)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_10[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_11", REG_SMC, 0x2100033, &ixPB1_PIF_PDNB_OVERRIDE_11[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_11)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_11[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_12", REG_SMC, 0x2100034, &ixPB1_PIF_PDNB_OVERRIDE_12[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_12)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_12[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_13", REG_SMC, 0x2100035, &ixPB1_PIF_PDNB_OVERRIDE_13[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_13)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_13[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_14", REG_SMC, 0x2100036, &ixPB1_PIF_PDNB_OVERRIDE_14[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_14)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_14[0]), 0, 0 },
+	{ "ixPB1_PIF_PDNB_OVERRIDE_15", REG_SMC, 0x2100037, &ixPB1_PIF_PDNB_OVERRIDE_15[0], sizeof(ixPB1_PIF_PDNB_OVERRIDE_15)/sizeof(ixPB1_PIF_PDNB_OVERRIDE_15[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_8", REG_SMC, 0x2100038, &ixPB1_PIF_SEQ_STATUS_8[0], sizeof(ixPB1_PIF_SEQ_STATUS_8)/sizeof(ixPB1_PIF_SEQ_STATUS_8[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_9", REG_SMC, 0x2100039, &ixPB1_PIF_SEQ_STATUS_9[0], sizeof(ixPB1_PIF_SEQ_STATUS_9)/sizeof(ixPB1_PIF_SEQ_STATUS_9[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_10", REG_SMC, 0x210003a, &ixPB1_PIF_SEQ_STATUS_10[0], sizeof(ixPB1_PIF_SEQ_STATUS_10)/sizeof(ixPB1_PIF_SEQ_STATUS_10[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_11", REG_SMC, 0x210003b, &ixPB1_PIF_SEQ_STATUS_11[0], sizeof(ixPB1_PIF_SEQ_STATUS_11)/sizeof(ixPB1_PIF_SEQ_STATUS_11[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_12", REG_SMC, 0x210003c, &ixPB1_PIF_SEQ_STATUS_12[0], sizeof(ixPB1_PIF_SEQ_STATUS_12)/sizeof(ixPB1_PIF_SEQ_STATUS_12[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_13", REG_SMC, 0x210003d, &ixPB1_PIF_SEQ_STATUS_13[0], sizeof(ixPB1_PIF_SEQ_STATUS_13)/sizeof(ixPB1_PIF_SEQ_STATUS_13[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_14", REG_SMC, 0x210003e, &ixPB1_PIF_SEQ_STATUS_14[0], sizeof(ixPB1_PIF_SEQ_STATUS_14)/sizeof(ixPB1_PIF_SEQ_STATUS_14[0]), 0, 0 },
+	{ "ixPB1_PIF_SEQ_STATUS_15", REG_SMC, 0x210003f, &ixPB1_PIF_SEQ_STATUS_15[0], sizeof(ixPB1_PIF_SEQ_STATUS_15)/sizeof(ixPB1_PIF_SEQ_STATUS_15[0]), 0, 0 },
+	{ "mmLINK_STATUS2", REG_MMIO, 0x22, &mmLINK_STATUS2[0], sizeof(mmLINK_STATUS2)/sizeof(mmLINK_STATUS2[0]), 0, 0 },
+	{ "mmLINK_CNTL2", REG_MMIO, 0x22, &mmLINK_CNTL2[0], sizeof(mmLINK_CNTL2)/sizeof(mmLINK_CNTL2[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG0", REG_SMC, 0x2200004, &ixPB1_GLB_CTRL_REG0[0], sizeof(ixPB1_GLB_CTRL_REG0)/sizeof(ixPB1_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG1", REG_SMC, 0x2200008, &ixPB1_GLB_CTRL_REG1[0], sizeof(ixPB1_GLB_CTRL_REG1)/sizeof(ixPB1_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG2", REG_SMC, 0x220000c, &ixPB1_GLB_CTRL_REG2[0], sizeof(ixPB1_GLB_CTRL_REG2)/sizeof(ixPB1_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG3", REG_SMC, 0x2200010, &ixPB1_GLB_CTRL_REG3[0], sizeof(ixPB1_GLB_CTRL_REG3)/sizeof(ixPB1_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG4", REG_SMC, 0x2200014, &ixPB1_GLB_CTRL_REG4[0], sizeof(ixPB1_GLB_CTRL_REG4)/sizeof(ixPB1_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG5", REG_SMC, 0x2200018, &ixPB1_GLB_CTRL_REG5[0], sizeof(ixPB1_GLB_CTRL_REG5)/sizeof(ixPB1_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x220001c, &ixPB1_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG1", REG_SMC, 0x2200020, &ixPB1_GLB_SCI_STAT_OVRD_REG1[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG1)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG2", REG_SMC, 0x2200024, &ixPB1_GLB_SCI_STAT_OVRD_REG2[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG2)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG3", REG_SMC, 0x2200028, &ixPB1_GLB_SCI_STAT_OVRD_REG3[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG3)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG4", REG_SMC, 0x220002c, &ixPB1_GLB_SCI_STAT_OVRD_REG4[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG4)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB1_GLB_OVRD_REG0", REG_SMC, 0x2200030, &ixPB1_GLB_OVRD_REG0[0], sizeof(ixPB1_GLB_OVRD_REG0)/sizeof(ixPB1_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_GLB_OVRD_REG1", REG_SMC, 0x2200034, &ixPB1_GLB_OVRD_REG1[0], sizeof(ixPB1_GLB_OVRD_REG1)/sizeof(ixPB1_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_GLB_OVRD_REG2", REG_SMC, 0x2200038, &ixPB1_GLB_OVRD_REG2[0], sizeof(ixPB1_GLB_OVRD_REG2)/sizeof(ixPB1_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB1_HW_DEBUG", REG_SMC, 0x2202004, &ixPB1_HW_DEBUG[0], sizeof(ixPB1_HW_DEBUG)/sizeof(ixPB1_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB1_STRAP_GLB_REG0", REG_SMC, 0x2202020, &ixPB1_STRAP_GLB_REG0[0], sizeof(ixPB1_STRAP_GLB_REG0)/sizeof(ixPB1_STRAP_GLB_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_TX_REG0", REG_SMC, 0x2202024, &ixPB1_STRAP_TX_REG0[0], sizeof(ixPB1_STRAP_TX_REG0)/sizeof(ixPB1_STRAP_TX_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_RX_REG0", REG_SMC, 0x2202028, &ixPB1_STRAP_RX_REG0[0], sizeof(ixPB1_STRAP_RX_REG0)/sizeof(ixPB1_STRAP_RX_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_RX_REG1", REG_SMC, 0x220202c, &ixPB1_STRAP_RX_REG1[0], sizeof(ixPB1_STRAP_RX_REG1)/sizeof(ixPB1_STRAP_RX_REG1[0]), 0, 0 },
+	{ "ixPB1_STRAP_PLL_REG0", REG_SMC, 0x2202030, &ixPB1_STRAP_PLL_REG0[0], sizeof(ixPB1_STRAP_PLL_REG0)/sizeof(ixPB1_STRAP_PLL_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_PIN_REG0", REG_SMC, 0x2202034, &ixPB1_STRAP_PIN_REG0[0], sizeof(ixPB1_STRAP_PIN_REG0)/sizeof(ixPB1_STRAP_PIN_REG0[0]), 0, 0 },
+	{ "ixPB1_DFT_JIT_INJ_REG0", REG_SMC, 0x2203000, &ixPB1_DFT_JIT_INJ_REG0[0], sizeof(ixPB1_DFT_JIT_INJ_REG0)/sizeof(ixPB1_DFT_JIT_INJ_REG0[0]), 0, 0 },
+	{ "ixPB1_DFT_JIT_INJ_REG1", REG_SMC, 0x2203004, &ixPB1_DFT_JIT_INJ_REG1[0], sizeof(ixPB1_DFT_JIT_INJ_REG1)/sizeof(ixPB1_DFT_JIT_INJ_REG1[0]), 0, 0 },
+	{ "ixPB1_DFT_JIT_INJ_REG2", REG_SMC, 0x2203008, &ixPB1_DFT_JIT_INJ_REG2[0], sizeof(ixPB1_DFT_JIT_INJ_REG2)/sizeof(ixPB1_DFT_JIT_INJ_REG2[0]), 0, 0 },
+	{ "ixPB1_DFT_DEBUG_CTRL_REG0", REG_SMC, 0x220300c, &ixPB1_DFT_DEBUG_CTRL_REG0[0], sizeof(ixPB1_DFT_DEBUG_CTRL_REG0)/sizeof(ixPB1_DFT_DEBUG_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_DFT_JIT_INJ_STAT_REG0", REG_SMC, 0x2203010, &ixPB1_DFT_JIT_INJ_STAT_REG0[0], sizeof(ixPB1_DFT_JIT_INJ_STAT_REG0)/sizeof(ixPB1_DFT_JIT_INJ_STAT_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO_GLB_CTRL_REG0", REG_SMC, 0x2204000, &ixPB1_PLL_RO_GLB_CTRL_REG0[0], sizeof(ixPB1_PLL_RO_GLB_CTRL_REG0)/sizeof(ixPB1_PLL_RO_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO_GLB_OVRD_REG0", REG_SMC, 0x2204010, NULL, 0, 0, 0 },
+	{ "ixPB1_PLL_RO0_CTRL_REG0", REG_SMC, 0x2204440, &ixPB1_PLL_RO0_CTRL_REG0[0], sizeof(ixPB1_PLL_RO0_CTRL_REG0)/sizeof(ixPB1_PLL_RO0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO0_OVRD_REG0", REG_SMC, 0x2204450, &ixPB1_PLL_RO0_OVRD_REG0[0], sizeof(ixPB1_PLL_RO0_OVRD_REG0)/sizeof(ixPB1_PLL_RO0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO0_OVRD_REG1", REG_SMC, 0x2204454, &ixPB1_PLL_RO0_OVRD_REG1[0], sizeof(ixPB1_PLL_RO0_OVRD_REG1)/sizeof(ixPB1_PLL_RO0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204460, &ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204464, &ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204468, &ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0", REG_SMC, 0x220446c, &ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC0_CTRL_REG0", REG_SMC, 0x2204480, &ixPB1_PLL_LC0_CTRL_REG0[0], sizeof(ixPB1_PLL_LC0_CTRL_REG0)/sizeof(ixPB1_PLL_LC0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC0_OVRD_REG0", REG_SMC, 0x2204490, &ixPB1_PLL_LC0_OVRD_REG0[0], sizeof(ixPB1_PLL_LC0_OVRD_REG0)/sizeof(ixPB1_PLL_LC0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC0_OVRD_REG1", REG_SMC, 0x2204494, &ixPB1_PLL_LC0_OVRD_REG1[0], sizeof(ixPB1_PLL_LC0_OVRD_REG1)/sizeof(ixPB1_PLL_LC0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204500, &ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204504, &ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204508, &ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0", REG_SMC, 0x220450c, &ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG0", REG_SMC, 0x2206000, &ixPB1_RX_GLB_CTRL_REG0[0], sizeof(ixPB1_RX_GLB_CTRL_REG0)/sizeof(ixPB1_RX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG1", REG_SMC, 0x2206004, &ixPB1_RX_GLB_CTRL_REG1[0], sizeof(ixPB1_RX_GLB_CTRL_REG1)/sizeof(ixPB1_RX_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG2", REG_SMC, 0x2206008, &ixPB1_RX_GLB_CTRL_REG2[0], sizeof(ixPB1_RX_GLB_CTRL_REG2)/sizeof(ixPB1_RX_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG3", REG_SMC, 0x220600c, &ixPB1_RX_GLB_CTRL_REG3[0], sizeof(ixPB1_RX_GLB_CTRL_REG3)/sizeof(ixPB1_RX_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG4", REG_SMC, 0x2206010, &ixPB1_RX_GLB_CTRL_REG4[0], sizeof(ixPB1_RX_GLB_CTRL_REG4)/sizeof(ixPB1_RX_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG5", REG_SMC, 0x2206014, &ixPB1_RX_GLB_CTRL_REG5[0], sizeof(ixPB1_RX_GLB_CTRL_REG5)/sizeof(ixPB1_RX_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG6", REG_SMC, 0x2206018, &ixPB1_RX_GLB_CTRL_REG6[0], sizeof(ixPB1_RX_GLB_CTRL_REG6)/sizeof(ixPB1_RX_GLB_CTRL_REG6[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG7", REG_SMC, 0x220601c, &ixPB1_RX_GLB_CTRL_REG7[0], sizeof(ixPB1_RX_GLB_CTRL_REG7)/sizeof(ixPB1_RX_GLB_CTRL_REG7[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG8", REG_SMC, 0x2206020, &ixPB1_RX_GLB_CTRL_REG8[0], sizeof(ixPB1_RX_GLB_CTRL_REG8)/sizeof(ixPB1_RX_GLB_CTRL_REG8[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206028, &ixPB1_RX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_OVRD_REG0", REG_SMC, 0x2206030, &ixPB1_RX_GLB_OVRD_REG0[0], sizeof(ixPB1_RX_GLB_OVRD_REG0)/sizeof(ixPB1_RX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_OVRD_REG1", REG_SMC, 0x2206034, &ixPB1_RX_GLB_OVRD_REG1[0], sizeof(ixPB1_RX_GLB_OVRD_REG1)/sizeof(ixPB1_RX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_RX_LANE0_CTRL_REG0", REG_SMC, 0x2206440, &ixPB1_RX_LANE0_CTRL_REG0[0], sizeof(ixPB1_RX_LANE0_CTRL_REG0)/sizeof(ixPB1_RX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206448, &ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE1_CTRL_REG0", REG_SMC, 0x2206480, &ixPB1_RX_LANE1_CTRL_REG0[0], sizeof(ixPB1_RX_LANE1_CTRL_REG0)/sizeof(ixPB1_RX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206488, &ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE2_CTRL_REG0", REG_SMC, 0x2206500, &ixPB1_RX_LANE2_CTRL_REG0[0], sizeof(ixPB1_RX_LANE2_CTRL_REG0)/sizeof(ixPB1_RX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206508, &ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE3_CTRL_REG0", REG_SMC, 0x2206600, &ixPB1_RX_LANE3_CTRL_REG0[0], sizeof(ixPB1_RX_LANE3_CTRL_REG0)/sizeof(ixPB1_RX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206608, &ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE4_CTRL_REG0", REG_SMC, 0x2206800, &ixPB1_RX_LANE4_CTRL_REG0[0], sizeof(ixPB1_RX_LANE4_CTRL_REG0)/sizeof(ixPB1_RX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206848, &ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE5_CTRL_REG0", REG_SMC, 0x2206880, &ixPB1_RX_LANE5_CTRL_REG0[0], sizeof(ixPB1_RX_LANE5_CTRL_REG0)/sizeof(ixPB1_RX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206888, &ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE6_CTRL_REG0", REG_SMC, 0x2206900, &ixPB1_RX_LANE6_CTRL_REG0[0], sizeof(ixPB1_RX_LANE6_CTRL_REG0)/sizeof(ixPB1_RX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206908, &ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE7_CTRL_REG0", REG_SMC, 0x2206a00, &ixPB1_RX_LANE7_CTRL_REG0[0], sizeof(ixPB1_RX_LANE7_CTRL_REG0)/sizeof(ixPB1_RX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206a08, &ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE8_CTRL_REG0", REG_SMC, 0x2207440, &ixPB1_RX_LANE8_CTRL_REG0[0], sizeof(ixPB1_RX_LANE8_CTRL_REG0)/sizeof(ixPB1_RX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207448, &ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE9_CTRL_REG0", REG_SMC, 0x2207480, &ixPB1_RX_LANE9_CTRL_REG0[0], sizeof(ixPB1_RX_LANE9_CTRL_REG0)/sizeof(ixPB1_RX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207488, &ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE10_CTRL_REG0", REG_SMC, 0x2207500, &ixPB1_RX_LANE10_CTRL_REG0[0], sizeof(ixPB1_RX_LANE10_CTRL_REG0)/sizeof(ixPB1_RX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207508, &ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE11_CTRL_REG0", REG_SMC, 0x2207600, &ixPB1_RX_LANE11_CTRL_REG0[0], sizeof(ixPB1_RX_LANE11_CTRL_REG0)/sizeof(ixPB1_RX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207608, &ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE12_CTRL_REG0", REG_SMC, 0x2207840, &ixPB1_RX_LANE12_CTRL_REG0[0], sizeof(ixPB1_RX_LANE12_CTRL_REG0)/sizeof(ixPB1_RX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207848, &ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE13_CTRL_REG0", REG_SMC, 0x2207880, &ixPB1_RX_LANE13_CTRL_REG0[0], sizeof(ixPB1_RX_LANE13_CTRL_REG0)/sizeof(ixPB1_RX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207888, &ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE14_CTRL_REG0", REG_SMC, 0x2207900, &ixPB1_RX_LANE14_CTRL_REG0[0], sizeof(ixPB1_RX_LANE14_CTRL_REG0)/sizeof(ixPB1_RX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207908, &ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE15_CTRL_REG0", REG_SMC, 0x2207a00, &ixPB1_RX_LANE15_CTRL_REG0[0], sizeof(ixPB1_RX_LANE15_CTRL_REG0)/sizeof(ixPB1_RX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207a08, &ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_CTRL_REG0", REG_SMC, 0x2208000, &ixPB1_TX_GLB_CTRL_REG0[0], sizeof(ixPB1_TX_GLB_CTRL_REG0)/sizeof(ixPB1_TX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_LANE_SKEW_CTRL", REG_SMC, 0x2208004, &ixPB1_TX_GLB_LANE_SKEW_CTRL[0], sizeof(ixPB1_TX_GLB_LANE_SKEW_CTRL)/sizeof(ixPB1_TX_GLB_LANE_SKEW_CTRL[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208010, &ixPB1_TX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0", REG_SMC, 0x2208014, &ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0], sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0)/sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1", REG_SMC, 0x2208018, &ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0], sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1)/sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2", REG_SMC, 0x220801c, &ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0], sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2)/sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3", REG_SMC, 0x2208020, &ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0], sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3)/sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG0", REG_SMC, 0x2208030, &ixPB1_TX_GLB_OVRD_REG0[0], sizeof(ixPB1_TX_GLB_OVRD_REG0)/sizeof(ixPB1_TX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG1", REG_SMC, 0x2208034, &ixPB1_TX_GLB_OVRD_REG1[0], sizeof(ixPB1_TX_GLB_OVRD_REG1)/sizeof(ixPB1_TX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG2", REG_SMC, 0x2208038, &ixPB1_TX_GLB_OVRD_REG2[0], sizeof(ixPB1_TX_GLB_OVRD_REG2)/sizeof(ixPB1_TX_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG3", REG_SMC, 0x220803c, &ixPB1_TX_GLB_OVRD_REG3[0], sizeof(ixPB1_TX_GLB_OVRD_REG3)/sizeof(ixPB1_TX_GLB_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG4", REG_SMC, 0x2208040, &ixPB1_TX_GLB_OVRD_REG4[0], sizeof(ixPB1_TX_GLB_OVRD_REG4)/sizeof(ixPB1_TX_GLB_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB1_TX_LANE0_CTRL_REG0", REG_SMC, 0x2208440, &ixPB1_TX_LANE0_CTRL_REG0[0], sizeof(ixPB1_TX_LANE0_CTRL_REG0)/sizeof(ixPB1_TX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE0_OVRD_REG0", REG_SMC, 0x2208444, &ixPB1_TX_LANE0_OVRD_REG0[0], sizeof(ixPB1_TX_LANE0_OVRD_REG0)/sizeof(ixPB1_TX_LANE0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208448, &ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE1_CTRL_REG0", REG_SMC, 0x2208480, &ixPB1_TX_LANE1_CTRL_REG0[0], sizeof(ixPB1_TX_LANE1_CTRL_REG0)/sizeof(ixPB1_TX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE1_OVRD_REG0", REG_SMC, 0x2208484, &ixPB1_TX_LANE1_OVRD_REG0[0], sizeof(ixPB1_TX_LANE1_OVRD_REG0)/sizeof(ixPB1_TX_LANE1_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208488, &ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE2_CTRL_REG0", REG_SMC, 0x2208500, &ixPB1_TX_LANE2_CTRL_REG0[0], sizeof(ixPB1_TX_LANE2_CTRL_REG0)/sizeof(ixPB1_TX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE2_OVRD_REG0", REG_SMC, 0x2208504, &ixPB1_TX_LANE2_OVRD_REG0[0], sizeof(ixPB1_TX_LANE2_OVRD_REG0)/sizeof(ixPB1_TX_LANE2_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208508, &ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE3_CTRL_REG0", REG_SMC, 0x2208600, &ixPB1_TX_LANE3_CTRL_REG0[0], sizeof(ixPB1_TX_LANE3_CTRL_REG0)/sizeof(ixPB1_TX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE3_OVRD_REG0", REG_SMC, 0x2208604, &ixPB1_TX_LANE3_OVRD_REG0[0], sizeof(ixPB1_TX_LANE3_OVRD_REG0)/sizeof(ixPB1_TX_LANE3_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208608, &ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE4_CTRL_REG0", REG_SMC, 0x2208840, &ixPB1_TX_LANE4_CTRL_REG0[0], sizeof(ixPB1_TX_LANE4_CTRL_REG0)/sizeof(ixPB1_TX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE4_OVRD_REG0", REG_SMC, 0x2208844, &ixPB1_TX_LANE4_OVRD_REG0[0], sizeof(ixPB1_TX_LANE4_OVRD_REG0)/sizeof(ixPB1_TX_LANE4_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208848, &ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE5_CTRL_REG0", REG_SMC, 0x2208880, &ixPB1_TX_LANE5_CTRL_REG0[0], sizeof(ixPB1_TX_LANE5_CTRL_REG0)/sizeof(ixPB1_TX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE5_OVRD_REG0", REG_SMC, 0x2208884, &ixPB1_TX_LANE5_OVRD_REG0[0], sizeof(ixPB1_TX_LANE5_OVRD_REG0)/sizeof(ixPB1_TX_LANE5_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208888, &ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE6_CTRL_REG0", REG_SMC, 0x2208900, &ixPB1_TX_LANE6_CTRL_REG0[0], sizeof(ixPB1_TX_LANE6_CTRL_REG0)/sizeof(ixPB1_TX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE6_OVRD_REG0", REG_SMC, 0x2208904, &ixPB1_TX_LANE6_OVRD_REG0[0], sizeof(ixPB1_TX_LANE6_OVRD_REG0)/sizeof(ixPB1_TX_LANE6_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208908, &ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE7_CTRL_REG0", REG_SMC, 0x2208a00, &ixPB1_TX_LANE7_CTRL_REG0[0], sizeof(ixPB1_TX_LANE7_CTRL_REG0)/sizeof(ixPB1_TX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE7_OVRD_REG0", REG_SMC, 0x2208a04, &ixPB1_TX_LANE7_OVRD_REG0[0], sizeof(ixPB1_TX_LANE7_OVRD_REG0)/sizeof(ixPB1_TX_LANE7_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208a08, &ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE8_CTRL_REG0", REG_SMC, 0x2209440, &ixPB1_TX_LANE8_CTRL_REG0[0], sizeof(ixPB1_TX_LANE8_CTRL_REG0)/sizeof(ixPB1_TX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE8_OVRD_REG0", REG_SMC, 0x2209444, &ixPB1_TX_LANE8_OVRD_REG0[0], sizeof(ixPB1_TX_LANE8_OVRD_REG0)/sizeof(ixPB1_TX_LANE8_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209448, &ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE9_CTRL_REG0", REG_SMC, 0x2209480, &ixPB1_TX_LANE9_CTRL_REG0[0], sizeof(ixPB1_TX_LANE9_CTRL_REG0)/sizeof(ixPB1_TX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE9_OVRD_REG0", REG_SMC, 0x2209484, &ixPB1_TX_LANE9_OVRD_REG0[0], sizeof(ixPB1_TX_LANE9_OVRD_REG0)/sizeof(ixPB1_TX_LANE9_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209488, &ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE10_CTRL_REG0", REG_SMC, 0x2209500, &ixPB1_TX_LANE10_CTRL_REG0[0], sizeof(ixPB1_TX_LANE10_CTRL_REG0)/sizeof(ixPB1_TX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE10_OVRD_REG0", REG_SMC, 0x2209504, &ixPB1_TX_LANE10_OVRD_REG0[0], sizeof(ixPB1_TX_LANE10_OVRD_REG0)/sizeof(ixPB1_TX_LANE10_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209508, &ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE11_CTRL_REG0", REG_SMC, 0x2209600, &ixPB1_TX_LANE11_CTRL_REG0[0], sizeof(ixPB1_TX_LANE11_CTRL_REG0)/sizeof(ixPB1_TX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE11_OVRD_REG0", REG_SMC, 0x2209604, &ixPB1_TX_LANE11_OVRD_REG0[0], sizeof(ixPB1_TX_LANE11_OVRD_REG0)/sizeof(ixPB1_TX_LANE11_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209608, &ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE12_CTRL_REG0", REG_SMC, 0x2209840, &ixPB1_TX_LANE12_CTRL_REG0[0], sizeof(ixPB1_TX_LANE12_CTRL_REG0)/sizeof(ixPB1_TX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE12_OVRD_REG0", REG_SMC, 0x2209844, &ixPB1_TX_LANE12_OVRD_REG0[0], sizeof(ixPB1_TX_LANE12_OVRD_REG0)/sizeof(ixPB1_TX_LANE12_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209848, &ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE13_CTRL_REG0", REG_SMC, 0x2209880, &ixPB1_TX_LANE13_CTRL_REG0[0], sizeof(ixPB1_TX_LANE13_CTRL_REG0)/sizeof(ixPB1_TX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE13_OVRD_REG0", REG_SMC, 0x2209884, &ixPB1_TX_LANE13_OVRD_REG0[0], sizeof(ixPB1_TX_LANE13_OVRD_REG0)/sizeof(ixPB1_TX_LANE13_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209888, &ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE14_CTRL_REG0", REG_SMC, 0x2209900, &ixPB1_TX_LANE14_CTRL_REG0[0], sizeof(ixPB1_TX_LANE14_CTRL_REG0)/sizeof(ixPB1_TX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE14_OVRD_REG0", REG_SMC, 0x2209904, &ixPB1_TX_LANE14_OVRD_REG0[0], sizeof(ixPB1_TX_LANE14_OVRD_REG0)/sizeof(ixPB1_TX_LANE14_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209908, &ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE15_CTRL_REG0", REG_SMC, 0x2209a00, &ixPB1_TX_LANE15_CTRL_REG0[0], sizeof(ixPB1_TX_LANE15_CTRL_REG0)/sizeof(ixPB1_TX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE15_OVRD_REG0", REG_SMC, 0x2209a04, &ixPB1_TX_LANE15_OVRD_REG0[0], sizeof(ixPB1_TX_LANE15_OVRD_REG0)/sizeof(ixPB1_TX_LANE15_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209a08, &ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "mmBIF_RFE_SNOOP_REG", REG_MMIO, 0x27, &mmBIF_RFE_SNOOP_REG[0], sizeof(mmBIF_RFE_SNOOP_REG)/sizeof(mmBIF_RFE_SNOOP_REG[0]), 0, 0 },
+	{ "mmMSI_CAP_LIST", REG_MMIO, 0x28, &mmMSI_CAP_LIST[0], sizeof(mmMSI_CAP_LIST)/sizeof(mmMSI_CAP_LIST[0]), 0, 0 },
+	{ "mmMSI_MSG_ADDR_LO", REG_MMIO, 0x29, &mmMSI_MSG_ADDR_LO[0], sizeof(mmMSI_MSG_ADDR_LO)/sizeof(mmMSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "mmMSI_MSG_ADDR_HI", REG_MMIO, 0x2a, &mmMSI_MSG_ADDR_HI[0], sizeof(mmMSI_MSG_ADDR_HI)/sizeof(mmMSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "mmMSI_MSG_DATA", REG_MMIO, 0x2a, &mmMSI_MSG_DATA[0], sizeof(mmMSI_MSG_DATA)/sizeof(mmMSI_MSG_DATA[0]), 0, 0 },
+	{ "mmMSI_MSG_DATA_64", REG_MMIO, 0x2b, &mmMSI_MSG_DATA_64[0], sizeof(mmMSI_MSG_DATA_64)/sizeof(mmMSI_MSG_DATA_64[0]), 0, 0 },
+	{ "mmCACHE_LINE", REG_MMIO, 0x3, &mmCACHE_LINE[0], sizeof(mmCACHE_LINE)/sizeof(mmCACHE_LINE[0]), 0, 0 },
+	{ "mmLATENCY", REG_MMIO, 0x3, &mmLATENCY[0], sizeof(mmLATENCY)/sizeof(mmLATENCY[0]), 0, 0 },
+	{ "mmHEADER", REG_MMIO, 0x3, &mmHEADER[0], sizeof(mmHEADER)/sizeof(mmHEADER[0]), 0, 0 },
+	{ "mmBIST", REG_MMIO, 0x3, &mmBIST[0], sizeof(mmBIST)/sizeof(mmBIST[0]), 0, 0 },
+	{ "mmBASE_ADDR_1", REG_MMIO, 0x4, &mmBASE_ADDR_1[0], sizeof(mmBASE_ADDR_1)/sizeof(mmBASE_ADDR_1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_MMIO, 0x40, &mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR", REG_MMIO, 0x41, &mmPCIE_VENDOR_SPECIFIC_HDR[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC1", REG_MMIO, 0x42, &mmPCIE_VENDOR_SPECIFIC1[0], sizeof(mmPCIE_VENDOR_SPECIFIC1)/sizeof(mmPCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC2", REG_MMIO, 0x43, &mmPCIE_VENDOR_SPECIFIC2[0], sizeof(mmPCIE_VENDOR_SPECIFIC2)/sizeof(mmPCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "mmPCIE_VC_ENH_CAP_LIST", REG_MMIO, 0x44, &mmPCIE_VC_ENH_CAP_LIST[0], sizeof(mmPCIE_VC_ENH_CAP_LIST)/sizeof(mmPCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CAP_REG1", REG_MMIO, 0x45, &mmPCIE_PORT_VC_CAP_REG1[0], sizeof(mmPCIE_PORT_VC_CAP_REG1)/sizeof(mmPCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CAP_REG2", REG_MMIO, 0x46, &mmPCIE_PORT_VC_CAP_REG2[0], sizeof(mmPCIE_PORT_VC_CAP_REG2)/sizeof(mmPCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_STATUS", REG_MMIO, 0x47, &mmPCIE_PORT_VC_STATUS[0], sizeof(mmPCIE_PORT_VC_STATUS)/sizeof(mmPCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CNTL", REG_MMIO, 0x47, &mmPCIE_PORT_VC_CNTL[0], sizeof(mmPCIE_PORT_VC_CNTL)/sizeof(mmPCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_CAP", REG_MMIO, 0x48, &mmPCIE_VC0_RESOURCE_CAP[0], sizeof(mmPCIE_VC0_RESOURCE_CAP)/sizeof(mmPCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_CNTL", REG_MMIO, 0x49, &mmPCIE_VC0_RESOURCE_CNTL[0], sizeof(mmPCIE_VC0_RESOURCE_CNTL)/sizeof(mmPCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_STATUS", REG_MMIO, 0x4a, &mmPCIE_VC0_RESOURCE_STATUS[0], sizeof(mmPCIE_VC0_RESOURCE_STATUS)/sizeof(mmPCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_CAP", REG_MMIO, 0x4b, &mmPCIE_VC1_RESOURCE_CAP[0], sizeof(mmPCIE_VC1_RESOURCE_CAP)/sizeof(mmPCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_CNTL", REG_MMIO, 0x4c, &mmPCIE_VC1_RESOURCE_CNTL[0], sizeof(mmPCIE_VC1_RESOURCE_CNTL)/sizeof(mmPCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_STATUS", REG_MMIO, 0x4d, &mmPCIE_VC1_RESOURCE_STATUS[0], sizeof(mmPCIE_VC1_RESOURCE_STATUS)/sizeof(mmPCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "mmBASE_ADDR_2", REG_MMIO, 0x5, &mmBASE_ADDR_2[0], sizeof(mmBASE_ADDR_2)/sizeof(mmBASE_ADDR_2[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_MMIO, 0x50, &mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_DW1", REG_MMIO, 0x51, &mmPCIE_DEV_SERIAL_NUM_DW1[0], sizeof(mmPCIE_DEV_SERIAL_NUM_DW1)/sizeof(mmPCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_DW2", REG_MMIO, 0x52, &mmPCIE_DEV_SERIAL_NUM_DW2[0], sizeof(mmPCIE_DEV_SERIAL_NUM_DW2)/sizeof(mmPCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_MMIO, 0x54, &mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_STATUS", REG_MMIO, 0x55, &mmPCIE_UNCORR_ERR_STATUS[0], sizeof(mmPCIE_UNCORR_ERR_STATUS)/sizeof(mmPCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_MASK", REG_MMIO, 0x56, &mmPCIE_UNCORR_ERR_MASK[0], sizeof(mmPCIE_UNCORR_ERR_MASK)/sizeof(mmPCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_SEVERITY", REG_MMIO, 0x57, &mmPCIE_UNCORR_ERR_SEVERITY[0], sizeof(mmPCIE_UNCORR_ERR_SEVERITY)/sizeof(mmPCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "mmPCIE_CORR_ERR_STATUS", REG_MMIO, 0x58, &mmPCIE_CORR_ERR_STATUS[0], sizeof(mmPCIE_CORR_ERR_STATUS)/sizeof(mmPCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_CORR_ERR_MASK", REG_MMIO, 0x59, &mmPCIE_CORR_ERR_MASK[0], sizeof(mmPCIE_CORR_ERR_MASK)/sizeof(mmPCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "mmPCIE_ADV_ERR_CAP_CNTL", REG_MMIO, 0x5a, &mmPCIE_ADV_ERR_CAP_CNTL[0], sizeof(mmPCIE_ADV_ERR_CAP_CNTL)/sizeof(mmPCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG0", REG_MMIO, 0x5b, &mmPCIE_HDR_LOG0[0], sizeof(mmPCIE_HDR_LOG0)/sizeof(mmPCIE_HDR_LOG0[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG1", REG_MMIO, 0x5c, &mmPCIE_HDR_LOG1[0], sizeof(mmPCIE_HDR_LOG1)/sizeof(mmPCIE_HDR_LOG1[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_0", REG_MMIO, 0x5c9, &mmBIOS_SCRATCH_0[0], sizeof(mmBIOS_SCRATCH_0)/sizeof(mmBIOS_SCRATCH_0[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_1", REG_MMIO, 0x5ca, &mmBIOS_SCRATCH_1[0], sizeof(mmBIOS_SCRATCH_1)/sizeof(mmBIOS_SCRATCH_1[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_2", REG_MMIO, 0x5cb, &mmBIOS_SCRATCH_2[0], sizeof(mmBIOS_SCRATCH_2)/sizeof(mmBIOS_SCRATCH_2[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_3", REG_MMIO, 0x5cc, &mmBIOS_SCRATCH_3[0], sizeof(mmBIOS_SCRATCH_3)/sizeof(mmBIOS_SCRATCH_3[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_4", REG_MMIO, 0x5cd, &mmBIOS_SCRATCH_4[0], sizeof(mmBIOS_SCRATCH_4)/sizeof(mmBIOS_SCRATCH_4[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_5", REG_MMIO, 0x5ce, &mmBIOS_SCRATCH_5[0], sizeof(mmBIOS_SCRATCH_5)/sizeof(mmBIOS_SCRATCH_5[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_6", REG_MMIO, 0x5cf, &mmBIOS_SCRATCH_6[0], sizeof(mmBIOS_SCRATCH_6)/sizeof(mmBIOS_SCRATCH_6[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG2", REG_MMIO, 0x5d, &mmPCIE_HDR_LOG2[0], sizeof(mmPCIE_HDR_LOG2)/sizeof(mmPCIE_HDR_LOG2[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_7", REG_MMIO, 0x5d0, &mmBIOS_SCRATCH_7[0], sizeof(mmBIOS_SCRATCH_7)/sizeof(mmBIOS_SCRATCH_7[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_8", REG_MMIO, 0x5d1, &mmBIOS_SCRATCH_8[0], sizeof(mmBIOS_SCRATCH_8)/sizeof(mmBIOS_SCRATCH_8[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_9", REG_MMIO, 0x5d2, &mmBIOS_SCRATCH_9[0], sizeof(mmBIOS_SCRATCH_9)/sizeof(mmBIOS_SCRATCH_9[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_10", REG_MMIO, 0x5d3, &mmBIOS_SCRATCH_10[0], sizeof(mmBIOS_SCRATCH_10)/sizeof(mmBIOS_SCRATCH_10[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_11", REG_MMIO, 0x5d4, &mmBIOS_SCRATCH_11[0], sizeof(mmBIOS_SCRATCH_11)/sizeof(mmBIOS_SCRATCH_11[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_12", REG_MMIO, 0x5d5, &mmBIOS_SCRATCH_12[0], sizeof(mmBIOS_SCRATCH_12)/sizeof(mmBIOS_SCRATCH_12[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_13", REG_MMIO, 0x5d6, &mmBIOS_SCRATCH_13[0], sizeof(mmBIOS_SCRATCH_13)/sizeof(mmBIOS_SCRATCH_13[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_14", REG_MMIO, 0x5d7, &mmBIOS_SCRATCH_14[0], sizeof(mmBIOS_SCRATCH_14)/sizeof(mmBIOS_SCRATCH_14[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_15", REG_MMIO, 0x5d8, &mmBIOS_SCRATCH_15[0], sizeof(mmBIOS_SCRATCH_15)/sizeof(mmBIOS_SCRATCH_15[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG3", REG_MMIO, 0x5e, &mmPCIE_HDR_LOG3[0], sizeof(mmPCIE_HDR_LOG3)/sizeof(mmPCIE_HDR_LOG3[0]), 0, 0 },
+	{ "mmMM_INDEX_HI", REG_MMIO, 0x6, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG0", REG_MMIO, 0x62, &mmPCIE_TLP_PREFIX_LOG0[0], sizeof(mmPCIE_TLP_PREFIX_LOG0)/sizeof(mmPCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG1", REG_MMIO, 0x63, &mmPCIE_TLP_PREFIX_LOG1[0], sizeof(mmPCIE_TLP_PREFIX_LOG1)/sizeof(mmPCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG2", REG_MMIO, 0x64, &mmPCIE_TLP_PREFIX_LOG2[0], sizeof(mmPCIE_TLP_PREFIX_LOG2)/sizeof(mmPCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG3", REG_MMIO, 0x65, &mmPCIE_TLP_PREFIX_LOG3[0], sizeof(mmPCIE_TLP_PREFIX_LOG3)/sizeof(mmPCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "mmBASE_ADDR_4", REG_MMIO, 0x7, &mmBASE_ADDR_4[0], sizeof(mmBASE_ADDR_4)/sizeof(mmBASE_ADDR_4[0]), 0, 0 },
+	{ "mmBASE_ADDR_5", REG_MMIO, 0x8, &mmBASE_ADDR_5[0], sizeof(mmBASE_ADDR_5)/sizeof(mmBASE_ADDR_5[0]), 0, 0 },
+	{ "mmPCIE_BAR_ENH_CAP_LIST", REG_MMIO, 0x80, &mmPCIE_BAR_ENH_CAP_LIST[0], sizeof(mmPCIE_BAR_ENH_CAP_LIST)/sizeof(mmPCIE_BAR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_BAR1_CAP", REG_MMIO, 0x81, &mmPCIE_BAR1_CAP[0], sizeof(mmPCIE_BAR1_CAP)/sizeof(mmPCIE_BAR1_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR1_CNTL", REG_MMIO, 0x82, &mmPCIE_BAR1_CNTL[0], sizeof(mmPCIE_BAR1_CNTL)/sizeof(mmPCIE_BAR1_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR2_CAP", REG_MMIO, 0x83, &mmPCIE_BAR2_CAP[0], sizeof(mmPCIE_BAR2_CAP)/sizeof(mmPCIE_BAR2_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR2_CNTL", REG_MMIO, 0x84, &mmPCIE_BAR2_CNTL[0], sizeof(mmPCIE_BAR2_CNTL)/sizeof(mmPCIE_BAR2_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR3_CAP", REG_MMIO, 0x85, &mmPCIE_BAR3_CAP[0], sizeof(mmPCIE_BAR3_CAP)/sizeof(mmPCIE_BAR3_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR3_CNTL", REG_MMIO, 0x86, &mmPCIE_BAR3_CNTL[0], sizeof(mmPCIE_BAR3_CNTL)/sizeof(mmPCIE_BAR3_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR4_CAP", REG_MMIO, 0x87, &mmPCIE_BAR4_CAP[0], sizeof(mmPCIE_BAR4_CAP)/sizeof(mmPCIE_BAR4_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR4_CNTL", REG_MMIO, 0x88, &mmPCIE_BAR4_CNTL[0], sizeof(mmPCIE_BAR4_CNTL)/sizeof(mmPCIE_BAR4_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR5_CAP", REG_MMIO, 0x89, &mmPCIE_BAR5_CAP[0], sizeof(mmPCIE_BAR5_CAP)/sizeof(mmPCIE_BAR5_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR5_CNTL", REG_MMIO, 0x8a, &mmPCIE_BAR5_CNTL[0], sizeof(mmPCIE_BAR5_CNTL)/sizeof(mmPCIE_BAR5_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR6_CAP", REG_MMIO, 0x8b, &mmPCIE_BAR6_CAP[0], sizeof(mmPCIE_BAR6_CAP)/sizeof(mmPCIE_BAR6_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR6_CNTL", REG_MMIO, 0x8c, &mmPCIE_BAR6_CNTL[0], sizeof(mmPCIE_BAR6_CNTL)/sizeof(mmPCIE_BAR6_CNTL[0]), 0, 0 },
+	{ "mmBASE_ADDR_6", REG_MMIO, 0x9, &mmBASE_ADDR_6[0], sizeof(mmBASE_ADDR_6)/sizeof(mmBASE_ADDR_6[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_ENH_CAP_LIST", REG_MMIO, 0x90, &mmPCIE_PWR_BUDGET_ENH_CAP_LIST[0], sizeof(mmPCIE_PWR_BUDGET_ENH_CAP_LIST)/sizeof(mmPCIE_PWR_BUDGET_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_DATA_SELECT", REG_MMIO, 0x91, &mmPCIE_PWR_BUDGET_DATA_SELECT[0], sizeof(mmPCIE_PWR_BUDGET_DATA_SELECT)/sizeof(mmPCIE_PWR_BUDGET_DATA_SELECT[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_DATA", REG_MMIO, 0x92, &mmPCIE_PWR_BUDGET_DATA[0], sizeof(mmPCIE_PWR_BUDGET_DATA)/sizeof(mmPCIE_PWR_BUDGET_DATA[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_CAP", REG_MMIO, 0x93, &mmPCIE_PWR_BUDGET_CAP[0], sizeof(mmPCIE_PWR_BUDGET_CAP)/sizeof(mmPCIE_PWR_BUDGET_CAP[0]), 0, 0 },
+	{ "mmPCIE_DPA_ENH_CAP_LIST", REG_MMIO, 0x94, &mmPCIE_DPA_ENH_CAP_LIST[0], sizeof(mmPCIE_DPA_ENH_CAP_LIST)/sizeof(mmPCIE_DPA_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_DPA_CAP", REG_MMIO, 0x95, &mmPCIE_DPA_CAP[0], sizeof(mmPCIE_DPA_CAP)/sizeof(mmPCIE_DPA_CAP[0]), 0, 0 },
+	{ "mmPCIE_DPA_LATENCY_INDICATOR", REG_MMIO, 0x96, &mmPCIE_DPA_LATENCY_INDICATOR[0], sizeof(mmPCIE_DPA_LATENCY_INDICATOR)/sizeof(mmPCIE_DPA_LATENCY_INDICATOR[0]), 0, 0 },
+	{ "mmPCIE_DPA_STATUS", REG_MMIO, 0x97, &mmPCIE_DPA_STATUS[0], sizeof(mmPCIE_DPA_STATUS)/sizeof(mmPCIE_DPA_STATUS[0]), 0, 0 },
+	{ "mmPCIE_DPA_CNTL", REG_MMIO, 0x97, &mmPCIE_DPA_CNTL[0], sizeof(mmPCIE_DPA_CNTL)/sizeof(mmPCIE_DPA_CNTL[0]), 0, 0 },
+	{ "mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0", REG_MMIO, 0x98, &mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 },
+	{ "mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4", REG_MMIO, 0x99, &mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 },
+	{ "mmPCIE_SECONDARY_ENH_CAP_LIST", REG_MMIO, 0x9c, &mmPCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(mmPCIE_SECONDARY_ENH_CAP_LIST)/sizeof(mmPCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_LINK_CNTL3", REG_MMIO, 0x9d, &mmPCIE_LINK_CNTL3[0], sizeof(mmPCIE_LINK_CNTL3)/sizeof(mmPCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "mmPCIE_LANE_ERROR_STATUS", REG_MMIO, 0x9e, &mmPCIE_LANE_ERROR_STATUS[0], sizeof(mmPCIE_LANE_ERROR_STATUS)/sizeof(mmPCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_LANE_0_EQUALIZATION_CNTL", REG_MMIO, 0x9f, &mmPCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_2_EQUALIZATION_CNTL", REG_MMIO, 0xa0, &mmPCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_4_EQUALIZATION_CNTL", REG_MMIO, 0xa1, &mmPCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_6_EQUALIZATION_CNTL", REG_MMIO, 0xa2, &mmPCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_8_EQUALIZATION_CNTL", REG_MMIO, 0xa3, &mmPCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_10_EQUALIZATION_CNTL", REG_MMIO, 0xa4, &mmPCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_12_EQUALIZATION_CNTL", REG_MMIO, 0xa5, &mmPCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_14_EQUALIZATION_CNTL", REG_MMIO, 0xa6, &mmPCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ACS_ENH_CAP_LIST", REG_MMIO, 0xa8, &mmPCIE_ACS_ENH_CAP_LIST[0], sizeof(mmPCIE_ACS_ENH_CAP_LIST)/sizeof(mmPCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_ACS_CNTL", REG_MMIO, 0xa9, &mmPCIE_ACS_CNTL[0], sizeof(mmPCIE_ACS_CNTL)/sizeof(mmPCIE_ACS_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ACS_CAP", REG_MMIO, 0xa9, &mmPCIE_ACS_CAP[0], sizeof(mmPCIE_ACS_CAP)/sizeof(mmPCIE_ACS_CAP[0]), 0, 0 },
+	{ "mmPCIE_ATS_ENH_CAP_LIST", REG_MMIO, 0xac, &mmPCIE_ATS_ENH_CAP_LIST[0], sizeof(mmPCIE_ATS_ENH_CAP_LIST)/sizeof(mmPCIE_ATS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_ATS_CNTL", REG_MMIO, 0xad, &mmPCIE_ATS_CNTL[0], sizeof(mmPCIE_ATS_CNTL)/sizeof(mmPCIE_ATS_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ATS_CAP", REG_MMIO, 0xad, &mmPCIE_ATS_CAP[0], sizeof(mmPCIE_ATS_CAP)/sizeof(mmPCIE_ATS_CAP[0]), 0, 0 },
+	{ "mmADAPTER_ID", REG_MMIO, 0xb, &mmADAPTER_ID[0], sizeof(mmADAPTER_ID)/sizeof(mmADAPTER_ID[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_ENH_CAP_LIST", REG_MMIO, 0xb0, &mmPCIE_PAGE_REQ_ENH_CAP_LIST[0], sizeof(mmPCIE_PAGE_REQ_ENH_CAP_LIST)/sizeof(mmPCIE_PAGE_REQ_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_STATUS", REG_MMIO, 0xb1, &mmPCIE_PAGE_REQ_STATUS[0], sizeof(mmPCIE_PAGE_REQ_STATUS)/sizeof(mmPCIE_PAGE_REQ_STATUS[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_CNTL", REG_MMIO, 0xb1, &mmPCIE_PAGE_REQ_CNTL[0], sizeof(mmPCIE_PAGE_REQ_CNTL)/sizeof(mmPCIE_PAGE_REQ_CNTL[0]), 0, 0 },
+	{ "mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY", REG_MMIO, 0xb2, &mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[0], sizeof(mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY)/sizeof(mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[0]), 0, 0 },
+	{ "mmPCIE_OUTSTAND_PAGE_REQ_ALLOC", REG_MMIO, 0xb3, &mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[0], sizeof(mmPCIE_OUTSTAND_PAGE_REQ_ALLOC)/sizeof(mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[0]), 0, 0 },
+	{ "mmPCIE_PASID_ENH_CAP_LIST", REG_MMIO, 0xb4, &mmPCIE_PASID_ENH_CAP_LIST[0], sizeof(mmPCIE_PASID_ENH_CAP_LIST)/sizeof(mmPCIE_PASID_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PASID_CNTL", REG_MMIO, 0xb5, &mmPCIE_PASID_CNTL[0], sizeof(mmPCIE_PASID_CNTL)/sizeof(mmPCIE_PASID_CNTL[0]), 0, 0 },
+	{ "mmPCIE_PASID_CAP", REG_MMIO, 0xb5, &mmPCIE_PASID_CAP[0], sizeof(mmPCIE_PASID_CAP)/sizeof(mmPCIE_PASID_CAP[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_ENH_CAP_LIST", REG_MMIO, 0xb8, &mmPCIE_TPH_REQR_ENH_CAP_LIST[0], sizeof(mmPCIE_TPH_REQR_ENH_CAP_LIST)/sizeof(mmPCIE_TPH_REQR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_CAP", REG_MMIO, 0xb9, &mmPCIE_TPH_REQR_CAP[0], sizeof(mmPCIE_TPH_REQR_CAP)/sizeof(mmPCIE_TPH_REQR_CAP[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_CNTL", REG_MMIO, 0xba, &mmPCIE_TPH_REQR_CNTL[0], sizeof(mmPCIE_TPH_REQR_CNTL)/sizeof(mmPCIE_TPH_REQR_CNTL[0]), 0, 0 },
+	{ "mmPCIE_MC_ENH_CAP_LIST", REG_MMIO, 0xbc, &mmPCIE_MC_ENH_CAP_LIST[0], sizeof(mmPCIE_MC_ENH_CAP_LIST)/sizeof(mmPCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_MC_CNTL", REG_MMIO, 0xbd, &mmPCIE_MC_CNTL[0], sizeof(mmPCIE_MC_CNTL)/sizeof(mmPCIE_MC_CNTL[0]), 0, 0 },
+	{ "mmPCIE_MC_CAP", REG_MMIO, 0xbd, &mmPCIE_MC_CAP[0], sizeof(mmPCIE_MC_CAP)/sizeof(mmPCIE_MC_CAP[0]), 0, 0 },
+	{ "mmPCIE_MC_ADDR0", REG_MMIO, 0xbe, &mmPCIE_MC_ADDR0[0], sizeof(mmPCIE_MC_ADDR0)/sizeof(mmPCIE_MC_ADDR0[0]), 0, 0 },
+	{ "mmPCIE_MC_ADDR1", REG_MMIO, 0xbf, &mmPCIE_MC_ADDR1[0], sizeof(mmPCIE_MC_ADDR1)/sizeof(mmPCIE_MC_ADDR1[0]), 0, 0 },
+	{ "mmROM_BASE_ADDR", REG_MMIO, 0xc, &mmROM_BASE_ADDR[0], sizeof(mmROM_BASE_ADDR)/sizeof(mmROM_BASE_ADDR[0]), 0, 0 },
+	{ "mmPCIE_INDEX_2", REG_MMIO, 0xc, &mmPCIE_INDEX_2[0], sizeof(mmPCIE_INDEX_2)/sizeof(mmPCIE_INDEX_2[0]), 0, 0 },
+	{ "mmPCIE_MC_RCV0", REG_MMIO, 0xc0, &mmPCIE_MC_RCV0[0], sizeof(mmPCIE_MC_RCV0)/sizeof(mmPCIE_MC_RCV0[0]), 0, 0 },
+	{ "mmPCIE_MC_RCV1", REG_MMIO, 0xc1, &mmPCIE_MC_RCV1[0], sizeof(mmPCIE_MC_RCV1)/sizeof(mmPCIE_MC_RCV1[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_ALL0", REG_MMIO, 0xc2, &mmPCIE_MC_BLOCK_ALL0[0], sizeof(mmPCIE_MC_BLOCK_ALL0)/sizeof(mmPCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_ALL1", REG_MMIO, 0xc3, &mmPCIE_MC_BLOCK_ALL1[0], sizeof(mmPCIE_MC_BLOCK_ALL1)/sizeof(mmPCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_UNTRANSLATED_0", REG_MMIO, 0xc4, &mmPCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_UNTRANSLATED_1", REG_MMIO, 0xc5, &mmPCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "mmPCIE_LTR_ENH_CAP_LIST", REG_MMIO, 0xc8, &mmPCIE_LTR_ENH_CAP_LIST[0], sizeof(mmPCIE_LTR_ENH_CAP_LIST)/sizeof(mmPCIE_LTR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_LTR_CAP", REG_MMIO, 0xc9, &mmPCIE_LTR_CAP[0], sizeof(mmPCIE_LTR_CAP)/sizeof(mmPCIE_LTR_CAP[0]), 0, 0 },
+	{ "mmPCIE_DATA_2", REG_MMIO, 0xd, &mmPCIE_DATA_2[0], sizeof(mmPCIE_DATA_2)/sizeof(mmPCIE_DATA_2[0]), 0, 0 },
+	{ "mmCAP_PTR", REG_MMIO, 0xd, &mmCAP_PTR[0], sizeof(mmCAP_PTR)/sizeof(mmCAP_PTR[0]), 0, 0 },
+	{ "mmPCIE_INDEX", REG_MMIO, 0xe, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
+	{ "mmINTERRUPT_LINE", REG_MMIO, 0xf, &mmINTERRUPT_LINE[0], sizeof(mmINTERRUPT_LINE)/sizeof(mmINTERRUPT_LINE[0]), 0, 0 },
+	{ "mmINTERRUPT_PIN", REG_MMIO, 0xf, &mmINTERRUPT_PIN[0], sizeof(mmINTERRUPT_PIN)/sizeof(mmINTERRUPT_PIN[0]), 0, 0 },
+	{ "mmMAX_LATENCY", REG_MMIO, 0xf, &mmMAX_LATENCY[0], sizeof(mmMAX_LATENCY)/sizeof(mmMAX_LATENCY[0]), 0, 0 },
+	{ "mmMIN_GRANT", REG_MMIO, 0xf, &mmMIN_GRANT[0], sizeof(mmMIN_GRANT)/sizeof(mmMIN_GRANT[0]), 0, 0 },
diff --git a/src/lib/ip/bif50.c b/src/lib/ip/bif50.c
new file mode 100644
index 0000000..af6dc49
--- /dev/null
+++ b/src/lib/ip/bif50.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "bif50_bits.i"
+
+static const struct umr_reg bif50_registers[] = {
+#include "bif50_regs.i"
+};
+
+struct umr_ip_block *umr_create_bif50(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "bif50";
+	ip->no_regs = sizeof(bif50_registers)/sizeof(bif50_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(bif50_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, bif50_registers, sizeof(bif50_registers));
+	return ip;
+}
diff --git a/src/lib/ip/bif50_bits.i b/src/lib/ip/bif50_bits.i
new file mode 100644
index 0000000..c1b91e9
--- /dev/null
+++ b/src/lib/ip/bif50_bits.i
@@ -0,0 +1,7720 @@
+static struct umr_bitfield mmVENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_INDEX[] = {
+	 { "MM_OFFSET", 0, 30, &umr_bitfield_default },
+	 { "MM_APER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_DATA[] = {
+	 { "MM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTATUS[] = {
+	 { "INT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "CAP_LIST", 4, 4, &umr_bitfield_default },
+	 { "PCI_66_EN", 5, 5, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 7, 7, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 8, 8, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 9, 10, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 11, 11, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 12, 12, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 13, 13, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 14, 14, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_RESERVED[] = {
+	 { "PCIEP_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_SCRATCH[] = {
+	 { "PCIEP_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_PORT_CNTL[] = {
+	 { "SLV_PORT_REQ_EN", 0, 0, &umr_bitfield_default },
+	 { "CI_SNOOP_OVERRIDE", 1, 1, &umr_bitfield_default },
+	 { "HOTPLUG_MSG_EN", 2, 2, &umr_bitfield_default },
+	 { "NATIVE_PME_EN", 3, 3, &umr_bitfield_default },
+	 { "PWR_FAULT_EN", 4, 4, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 5, 5, &umr_bitfield_default },
+	 { "SEQNUM_DEBUG_MODE", 6, 6, &umr_bitfield_default },
+	 { "CI_SLV_CPL_STATIC_ALLOC_LIMIT_S", 8, 14, &umr_bitfield_default },
+	 { "CI_MAX_CPL_PAYLOAD_SIZE_MODE", 16, 17, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_CPL_PAYLOAD_SIZE", 18, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CNTL[] = {
+	 { "TX_SNR_OVERRIDE", 10, 11, &umr_bitfield_default },
+	 { "TX_RO_OVERRIDE", 12, 13, &umr_bitfield_default },
+	 { "TX_PACK_PACKET_DIS", 14, 14, &umr_bitfield_default },
+	 { "TX_FLUSH_TLP_DIS", 15, 15, &umr_bitfield_default },
+	 { "TX_CPL_PASS_P", 20, 20, &umr_bitfield_default },
+	 { "TX_NP_PASS_P", 21, 21, &umr_bitfield_default },
+	 { "TX_CLEAR_EXTRA_PM_REQS", 22, 22, &umr_bitfield_default },
+	 { "TX_FC_UPDATE_TIMEOUT_DIS", 23, 23, &umr_bitfield_default },
+	 { "TX_F0_TPH_DIS", 24, 24, &umr_bitfield_default },
+	 { "TX_F1_TPH_DIS", 25, 25, &umr_bitfield_default },
+	 { "TX_F2_TPH_DIS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REQUESTER_ID[] = {
+	 { "TX_REQUESTER_ID_FUNCTION", 0, 2, &umr_bitfield_default },
+	 { "TX_REQUESTER_ID_DEVICE", 3, 7, &umr_bitfield_default },
+	 { "TX_REQUESTER_ID_BUS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_VENDOR_SPECIFIC[] = {
+	 { "TX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REQUEST_NUM_CNTL[] = {
+	 { "TX_NUM_OUTSTANDING_NP", 24, 29, &umr_bitfield_default },
+	 { "TX_NUM_OUTSTANDING_NP_VC1_EN", 30, 30, &umr_bitfield_default },
+	 { "TX_NUM_OUTSTANDING_NP_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_SEQ[] = {
+	 { "TX_NEXT_TRANSMIT_SEQ", 0, 11, &umr_bitfield_default },
+	 { "TX_ACKD_SEQ", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REPLAY[] = {
+	 { "TX_REPLAY_NUM", 0, 2, &umr_bitfield_default },
+	 { "TX_REPLAY_TIMER_OVERWRITE", 15, 15, &umr_bitfield_default },
+	 { "TX_REPLAY_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_ACK_LATENCY_LIMIT[] = {
+	 { "TX_ACK_LATENCY_LIMIT", 0, 11, &umr_bitfield_default },
+	 { "TX_ACK_LATENCY_LIMIT_OVERWRITE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_P[] = {
+	 { "TX_CREDITS_ADVT_PD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_NP[] = {
+	 { "TX_CREDITS_ADVT_NPD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_CPL[] = {
+	 { "TX_CREDITS_ADVT_CPLD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_P[] = {
+	 { "TX_CREDITS_INIT_PD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_NP[] = {
+	 { "TX_CREDITS_INIT_NPD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_CPL[] = {
+	 { "TX_CREDITS_INIT_CPLD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_STATUS[] = {
+	 { "TX_CREDITS_ERR_PD", 0, 0, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_PH", 1, 1, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_NPD", 2, 2, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_NPH", 3, 3, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_CPLD", 4, 4, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_CPLH", 5, 5, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_PD", 16, 16, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_PH", 17, 17, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_NPD", 18, 18, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_NPH", 19, 19, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_CPLD", 20, 20, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_CPLH", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_FCU_THRESHOLD[] = {
+	 { "TX_FCU_THRESHOLD_P_VC0", 0, 2, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_NP_VC0", 4, 6, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_CPL_VC0", 8, 10, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_P_VC1", 16, 18, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_NP_VC1", 20, 22, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_CPL_VC1", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_PORT_LANE_STATUS[] = {
+	 { "PORT_LANE_REVERSAL", 0, 0, &umr_bitfield_default },
+	 { "PHY_LINK_WIDTH", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_P[] = {
+	 { "PD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "PH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_NP[] = {
+	 { "NPD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "NPH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_CPL[] = {
+	 { "CPLD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "CPLH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_ERR_CNTL[] = {
+	 { "ERR_REPORTING_DIS", 0, 0, &umr_bitfield_default },
+	 { "STRAP_FIRST_RCVD_ERR_LOG", 1, 1, &umr_bitfield_default },
+	 { "RX_DROP_ECRC_FAILURES", 2, 2, &umr_bitfield_default },
+	 { "TX_GENERATE_LCRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_GENERATE_LCRC_ERR", 5, 5, &umr_bitfield_default },
+	 { "TX_GENERATE_ECRC_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_GENERATE_ECRC_ERR", 7, 7, &umr_bitfield_default },
+	 { "AER_HDR_LOG_TIMEOUT", 8, 10, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F0_TIMER_EXPIRED", 11, 11, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F1_TIMER_EXPIRED", 12, 12, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F2_TIMER_EXPIRED", 13, 13, &umr_bitfield_default },
+	 { "CI_P_SLV_BUF_RD_HALT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CI_NP_SLV_BUF_RD_HALT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "CI_SLV_BUF_HALT_RESET", 16, 16, &umr_bitfield_default },
+	 { "SEND_ERR_MSG_IMMEDIATELY", 17, 17, &umr_bitfield_default },
+	 { "STRAP_POISONED_ADVISORY_NONFATAL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL[] = {
+	 { "RX_IGNORE_IO_ERR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_BE_ERR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_MSG_ERR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_CRC_ERR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_CPL_ERR", 5, 5, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_IGNORE_LEN_MISMATCH_ERR", 7, 7, &umr_bitfield_default },
+	 { "RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default },
+	 { "RX_IGNORE_TC_ERR", 9, 9, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_UR", 10, 10, &umr_bitfield_default },
+	 { "RX_IGNORE_IO_UR", 11, 11, &umr_bitfield_default },
+	 { "RX_IGNORE_AT_ERR", 12, 12, &umr_bitfield_default },
+	 { "RX_NAK_IF_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RX_GEN_ONE_NAK", 14, 14, &umr_bitfield_default },
+	 { "RX_FC_INIT_FROM_REG", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT", 16, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_PCIE_CPL_TIMEOUT_DIS", 20, 20, &umr_bitfield_default },
+	 { "RX_IGNORE_SHORTPREFIX_ERR", 21, 21, &umr_bitfield_default },
+	 { "RX_IGNORE_MAXPREFIX_ERR", 22, 22, &umr_bitfield_default },
+	 { "RX_IGNORE_CPLPREFIX_ERR", 23, 23, &umr_bitfield_default },
+	 { "RX_IGNORE_INVALIDPASID_ERR", 24, 24, &umr_bitfield_default },
+	 { "RX_IGNORE_NOT_PASID_UR", 25, 25, &umr_bitfield_default },
+	 { "RX_TPH_DIS", 26, 26, &umr_bitfield_default },
+	 { "RX_RCB_FLR_TIMEOUT_DIS", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_EXPECTED_SEQNUM[] = {
+	 { "RX_EXPECTED_SEQNUM", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_VENDOR_SPECIFIC[] = {
+	 { "RX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+	 { "RX_VENDOR_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL3[] = {
+	 { "RX_IGNORE_RC_TRANSMRDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_TRANSMWRPASID_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_PRGRESPMSG_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVCPLPASID_UR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_P[] = {
+	 { "RX_CREDITS_ALLOCATED_PD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_NP[] = {
+	 { "RX_CREDITS_ALLOCATED_NPD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_CPL[] = {
+	 { "RX_CREDITS_ALLOCATED_CPLD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_ERROR_INJECT_PHYSICAL[] = {
+	 { "ERROR_INJECT_PL_LANE_ERR", 0, 1, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_FRAMING_ERR", 2, 3, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_BAD_PARITY_IN_SKP", 4, 5, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_BAD_LFSR_IN_SKP", 6, 7, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_LOOPBACK_UFLOW", 8, 9, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_LOOPBACK_OFLOW", 10, 11, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_DESKEW_ERR", 12, 13, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_8B10B_DISPARITY_ERR", 14, 15, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_8B10B_DECODE_ERR", 16, 17, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_SKP_OS_ERROR", 18, 19, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_INV_OS_IDENTIFIER", 20, 21, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_BAD_SYNC_HEADER", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_ERROR_INJECT_TRANSACTION[] = {
+	 { "ERROR_INJECT_TL_FLOW_CTL_ERR", 0, 1, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER", 2, 3, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_BAD_DLLP", 4, 5, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_BAD_TLP", 6, 7, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_UNSUPPORTED_REQ", 8, 9, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_ECRC_ERROR", 10, 11, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_MALFORMED_TLP", 12, 13, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_UNEXPECTED_CMPLT", 14, 15, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_COMPLETER_ABORT", 16, 17, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_COMPLETION_TIMEOUT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_SRIOV_PRIV_CTRL[] = {
+	 { "RX_SRIOV_VF_MAPPING_MODE", 0, 1, &umr_bitfield_default },
+	 { "SRIOV_SAVE_VFS_ON_VFENABLE_CLR", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL[] = {
+	 { "LC_DONT_ENTER_L23_IN_D0", 1, 1, &umr_bitfield_default },
+	 { "LC_RESET_L_IDLE_COUNT_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_RESET_LINK", 3, 3, &umr_bitfield_default },
+	 { "LC_16X_CLEAR_TX_PIPE", 4, 7, &umr_bitfield_default },
+	 { "LC_L0S_INACTIVITY", 8, 11, &umr_bitfield_default },
+	 { "LC_L1_INACTIVITY", 12, 15, &umr_bitfield_default },
+	 { "LC_PMI_TO_L1_DIS", 16, 16, &umr_bitfield_default },
+	 { "LC_INC_N_FTS_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_IDLE_IN_L1L23", 18, 19, &umr_bitfield_default },
+	 { "LC_FACTOR_IN_EXT_SYNC", 20, 20, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_PM_ACK_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_WAKE_FROM_L23", 22, 22, &umr_bitfield_default },
+	 { "LC_L1_IMMEDIATE_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_ASPM_TO_L1_DIS", 24, 24, &umr_bitfield_default },
+	 { "LC_DELAY_COUNT", 25, 26, &umr_bitfield_default },
+	 { "LC_DELAY_L0S_EXIT", 27, 27, &umr_bitfield_default },
+	 { "LC_DELAY_L1_EXIT", 28, 28, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_EL_IDLE", 29, 29, &umr_bitfield_default },
+	 { "LC_ESCAPE_L1L23_EN", 30, 30, &umr_bitfield_default },
+	 { "LC_GATE_RCVR_IDLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_TRAINING_CNTL[] = {
+	 { "LC_TRAINING_CNTL", 0, 3, &umr_bitfield_default },
+	 { "LC_COMPLIANCE_RECEIVE", 4, 4, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_MORE_NON_MATCHING_TS1", 5, 5, &umr_bitfield_default },
+	 { "LC_L0S_L1_TRAINING_CNTL_EN", 6, 6, &umr_bitfield_default },
+	 { "LC_L1_LONG_WAKE_FIX_EN", 7, 7, &umr_bitfield_default },
+	 { "LC_POWER_STATE", 8, 10, &umr_bitfield_default },
+	 { "LC_DONT_GO_TO_L0S_IF_L1_ARMED", 11, 11, &umr_bitfield_default },
+	 { "LC_INIT_SPD_CHG_WITH_CSR_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_DISABLE_TRAINING_BIT_ARCH", 13, 13, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_SETS_IN_RCFG", 14, 14, &umr_bitfield_default },
+	 { "LC_HOT_RESET_QUICK_EXIT_EN", 15, 15, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_SKP", 16, 16, &umr_bitfield_default },
+	 { "LC_AUTONOMOUS_CHANGE_OFF", 17, 17, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAP_OFF", 18, 18, &umr_bitfield_default },
+	 { "LC_HW_LINK_DIS_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_LINK_DIS_BY_HW", 20, 20, &umr_bitfield_default },
+	 { "LC_STATIC_TX_PIPE_COUNT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_ASPM_L1_NAK_TIMER_SEL", 22, 23, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_R_SPEED", 24, 24, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_TEST", 25, 25, &umr_bitfield_default },
+	 { "LC_RESET_ASPM_L1_NAK_TIMER", 26, 26, &umr_bitfield_default },
+	 { "LC_SHORT_RCFG_TIMEOUT", 27, 27, &umr_bitfield_default },
+	 { "LC_ALLOW_TX_L1_CONTROL", 28, 28, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_FOM_VALID_AFTER_TRACK", 29, 29, &umr_bitfield_default },
+	 { "LC_EXTEND_EQ_REQ_TIME", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_LINK_WIDTH_CNTL[] = {
+	 { "LC_LINK_WIDTH", 0, 2, &umr_bitfield_default },
+	 { "LC_LINK_WIDTH_RD", 4, 6, &umr_bitfield_default },
+	 { "LC_RECONFIG_ARC_MISSING_ESCAPE", 7, 7, &umr_bitfield_default },
+	 { "LC_RECONFIG_NOW", 8, 8, &umr_bitfield_default },
+	 { "LC_RENEGOTIATION_SUPPORT", 9, 9, &umr_bitfield_default },
+	 { "LC_RENEGOTIATE_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_SHORT_RECONFIG_EN", 11, 11, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_SUPPORT", 12, 12, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_DIS", 13, 13, &umr_bitfield_default },
+	 { "LC_UPCFG_WAIT_FOR_RCVR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LC_UPCFG_TIMER_SEL", 15, 15, &umr_bitfield_default },
+	 { "LC_DEASSERT_TX_PDNB", 16, 16, &umr_bitfield_default },
+	 { "LC_L1_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_DYNLINK_MST_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_DUAL_END_RECONFIG_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LC_DYN_LANES_PWR_STATE", 21, 22, &umr_bitfield_default },
+	 { "LC_EQ_REVERSAL_LOGIC_EN", 23, 23, &umr_bitfield_default },
+	 { "LC_MULT_REVERSE_ATTEMP_EN", 24, 24, &umr_bitfield_default },
+	 { "LC_RESET_TSX_CNT_IN_RCONFIG_EN", 25, 25, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_L_IDLE_IN_R_IDLE", 26, 26, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT", 27, 27, &umr_bitfield_default },
+	 { "LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE", 28, 28, &umr_bitfield_default },
+	 { "LC_BYPASS_RXL0S_ON_SHORT_EI", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_N_FTS_CNTL[] = {
+	 { "LC_XMIT_N_FTS", 0, 7, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_OVERRIDE_EN", 8, 8, &umr_bitfield_default },
+	 { "LC_XMIT_FTS_BEFORE_RECOVERY", 9, 9, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_LIMIT", 16, 23, &umr_bitfield_default },
+	 { "LC_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_SPEED_CNTL[] = {
+	 { "LC_GEN2_EN_STRAP", 0, 0, &umr_bitfield_default },
+	 { "LC_GEN3_EN_STRAP", 1, 1, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE", 3, 4, &umr_bitfield_default },
+	 { "LC_FORCE_EN_SW_SPEED_CHANGE", 5, 5, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_SW_SPEED_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_FORCE_EN_HW_SPEED_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_HW_SPEED_CHANGE", 8, 8, &umr_bitfield_default },
+	 { "LC_INITIATE_LINK_SPEED_CHANGE", 9, 9, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPTS_ALLOWED", 10, 11, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPT_FAILED", 12, 12, &umr_bitfield_default },
+	 { "LC_CURRENT_DATA_RATE", 13, 14, &umr_bitfield_default },
+	 { "LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS", 15, 15, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_SPD_CHANGE_CNT", 16, 16, &umr_bitfield_default },
+	 { "LC_1_OR_MORE_TS2_SPEED_ARC_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN2", 18, 18, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN2", 19, 19, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN3", 20, 20, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN3", 21, 21, &umr_bitfield_default },
+	 { "LC_AUTO_RECOVERY_DIS", 22, 22, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_STATUS", 23, 23, &umr_bitfield_default },
+	 { "LC_DATA_RATE_ADVERTISED", 24, 25, &umr_bitfield_default },
+	 { "LC_CHECK_DATA_RATE", 26, 26, &umr_bitfield_default },
+	 { "LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN", 27, 27, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L0s_EN", 28, 28, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L1_EN", 29, 29, &umr_bitfield_default },
+	 { "LC_DONT_CHECK_EQTS_IN_RCFG", 30, 30, &umr_bitfield_default },
+	 { "LC_DELAY_COEFF_UPDATE_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE0[] = {
+	 { "LC_CURRENT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE1", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE2", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE1[] = {
+	 { "LC_PREV_STATE4", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE5", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE6", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE7", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE2[] = {
+	 { "LC_PREV_STATE8", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE9", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE10", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE11", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE3[] = {
+	 { "LC_PREV_STATE12", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE13", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE14", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE15", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE4[] = {
+	 { "LC_PREV_STATE16", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE17", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE18", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE19", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE5[] = {
+	 { "LC_PREV_STATE20", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE21", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE22", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE23", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL2[] = {
+	 { "LC_TIMED_OUT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_STATE_TIMED_OUT", 6, 6, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_BW_REDUCTION", 7, 7, &umr_bitfield_default },
+	 { "LC_MORE_TS2_EN", 8, 8, &umr_bitfield_default },
+	 { "LC_X12_NEGOTIATION_DIS", 9, 9, &umr_bitfield_default },
+	 { "LC_LINK_UP_REVERSAL_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_ILLEGAL_STATE", 11, 11, &umr_bitfield_default },
+	 { "LC_ILLEGAL_STATE_RESTART_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_OTHER_LANES_MODE", 13, 13, &umr_bitfield_default },
+	 { "LC_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "LC_DISABLE_INFERRED_ELEC_IDLE_DET", 16, 16, &umr_bitfield_default },
+	 { "LC_ALLOW_PDWN_IN_L1", 17, 17, &umr_bitfield_default },
+	 { "LC_ALLOW_PDWN_IN_L23", 18, 18, &umr_bitfield_default },
+	 { "LC_DEASSERT_RX_EN_IN_L0S", 19, 19, &umr_bitfield_default },
+	 { "LC_BLOCK_EL_IDLE_IN_L0", 20, 20, &umr_bitfield_default },
+	 { "LC_RCV_L0_TO_RCV_L0S_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_ASSERT_INACTIVE_DURING_HOLD", 22, 22, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_LANES_IN_LW_NEG", 23, 24, &umr_bitfield_default },
+	 { "LC_PWR_DOWN_NEG_OFF_LANES", 25, 25, &umr_bitfield_default },
+	 { "LC_DISABLE_LOST_SYM_LOCK_ARCS", 26, 26, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DIS", 27, 27, &umr_bitfield_default },
+	 { "LC_PMI_L1_WAIT_FOR_SLV_IDLE", 28, 28, &umr_bitfield_default },
+	 { "LC_TEST_TIMER_SEL", 29, 30, &umr_bitfield_default },
+	 { "LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_BW_CHANGE_CNTL[] = {
+	 { "LC_BW_CHANGE_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "LC_HW_INIT_SPEED_CHANGE", 1, 1, &umr_bitfield_default },
+	 { "LC_SW_INIT_SPEED_CHANGE", 2, 2, &umr_bitfield_default },
+	 { "LC_OTHER_INIT_SPEED_CHANGE", 3, 3, &umr_bitfield_default },
+	 { "LC_RELIABILITY_SPEED_CHANGE", 4, 4, &umr_bitfield_default },
+	 { "LC_FAILED_SPEED_NEG", 5, 5, &umr_bitfield_default },
+	 { "LC_LONG_LW_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_SHORT_LW_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_OTHER", 8, 8, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_FAILED", 9, 9, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DETECT_MODE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CDR_CNTL[] = {
+	 { "LC_CDR_TEST_OFF", 0, 11, &umr_bitfield_default },
+	 { "LC_CDR_TEST_SETS", 12, 23, &umr_bitfield_default },
+	 { "LC_CDR_SET_TYPE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_LANE_CNTL[] = {
+	 { "LC_CORRUPTED_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_LANE_DIS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL3[] = {
+	 { "LC_SELECT_DEEMPHASIS", 0, 0, &umr_bitfield_default },
+	 { "LC_SELECT_DEEMPHASIS_CNTL", 1, 2, &umr_bitfield_default },
+	 { "LC_RCVD_DEEMPHASIS", 3, 3, &umr_bitfield_default },
+	 { "LC_COMP_TO_DETECT", 4, 4, &umr_bitfield_default },
+	 { "LC_RESET_TSX_CNT_IN_RLOCK_EN", 5, 5, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED", 6, 7, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED", 8, 8, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT", 9, 9, &umr_bitfield_default },
+	 { "LC_ENHANCED_HOT_PLUG_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_RCVR_DET_EN_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "LC_EHP_RX_PHY_CMD", 12, 13, &umr_bitfield_default },
+	 { "LC_EHP_TX_PHY_CMD", 14, 15, &umr_bitfield_default },
+	 { "LC_CHIP_BIF_USB_IDLE_EN", 16, 16, &umr_bitfield_default },
+	 { "LC_L1_BLOCK_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL", 19, 20, &umr_bitfield_default },
+	 { "LC_FAST_L1_ENTRY_EXIT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_RXPHYCMD_INACTIVE_EN_MODE", 22, 22, &umr_bitfield_default },
+	 { "LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_HW_VOLTAGE_IF_CONTROL", 24, 25, &umr_bitfield_default },
+	 { "LC_VOLTAGE_TIMER_SEL", 26, 29, &umr_bitfield_default },
+	 { "LC_GO_TO_RECOVERY", 30, 30, &umr_bitfield_default },
+	 { "LC_N_EIE_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL4[] = {
+	 { "LC_TX_ENABLE_BEHAVIOUR", 0, 1, &umr_bitfield_default },
+	 { "LC_DIS_CONTIG_END_SET_CHECK", 2, 2, &umr_bitfield_default },
+	 { "LC_DIS_ASPM_L1_IN_SPEED_CHANGE", 3, 3, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ", 4, 4, &umr_bitfield_default },
+	 { "LC_REDO_EQ", 5, 5, &umr_bitfield_default },
+	 { "LC_EXTEND_EIEOS", 6, 6, &umr_bitfield_default },
+	 { "LC_IGNORE_PARITY", 7, 7, &umr_bitfield_default },
+	 { "LC_EQ_SEARCH_MODE", 8, 9, &umr_bitfield_default },
+	 { "LC_DSC_CHECK_COEFFS_IN_RLOCK", 10, 10, &umr_bitfield_default },
+	 { "LC_USC_EQ_NOT_REQD", 11, 11, &umr_bitfield_default },
+	 { "LC_USC_GO_TO_EQ", 12, 12, &umr_bitfield_default },
+	 { "LC_SET_QUIESCE", 13, 13, &umr_bitfield_default },
+	 { "LC_QUIESCE_RCVD", 14, 14, &umr_bitfield_default },
+	 { "LC_UNEXPECTED_COEFFS_RCVD", 15, 15, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ_REQ_PHASE", 16, 16, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_IN_EQ_REQ_PHASE", 17, 17, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_VALUE", 18, 21, &umr_bitfield_default },
+	 { "LC_USC_DELAY_DLLPS", 22, 22, &umr_bitfield_default },
+	 { "LC_PCIE_TX_FULL_SWING", 23, 23, &umr_bitfield_default },
+	 { "LC_EQ_WAIT_FOR_EVAL_DONE", 24, 24, &umr_bitfield_default },
+	 { "LC_8GT_SKIP_ORDER_EN", 25, 25, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_MORE_TS_IN_RLOCK", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL5[] = {
+	 { "LC_EQ_FS_0", 0, 5, &umr_bitfield_default },
+	 { "LC_EQ_FS_8", 6, 11, &umr_bitfield_default },
+	 { "LC_EQ_LF_0", 12, 17, &umr_bitfield_default },
+	 { "LC_EQ_LF_8", 18, 23, &umr_bitfield_default },
+	 { "LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_FORCE_COEFF[] = {
+	 { "LC_FORCE_COEFF", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR", 1, 6, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR", 13, 18, &umr_bitfield_default },
+	 { "LC_3X3_COEFF_SEARCH_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_PRESET_10_EN", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_BEST_EQ_SETTINGS[] = {
+	 { "LC_BEST_PRESET", 0, 3, &umr_bitfield_default },
+	 { "LC_BEST_PRECURSOR", 4, 9, &umr_bitfield_default },
+	 { "LC_BEST_CURSOR", 10, 15, &umr_bitfield_default },
+	 { "LC_BEST_POSTCURSOR", 16, 21, &umr_bitfield_default },
+	 { "LC_BEST_FOM", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_FORCE_EQ_REQ_COEFF[] = {
+	 { "LC_FORCE_COEFF_IN_EQ_REQ_PHASE", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR_REQ", 1, 6, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR_REQ", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR_REQ", 13, 18, &umr_bitfield_default },
+	 { "LC_FS_OTHER_END", 19, 24, &umr_bitfield_default },
+	 { "LC_LF_OTHER_END", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL6[] = {
+	 { "LC_SPC_MODE_2P5GT", 0, 0, &umr_bitfield_default },
+	 { "LC_SPC_MODE_5GT", 2, 2, &umr_bitfield_default },
+	 { "LC_SPC_MODE_8GT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_STRAP_LC[] = {
+	 { "STRAP_FTS_yTSx_COUNT", 0, 1, &umr_bitfield_default },
+	 { "STRAP_LONG_yTSx_COUNT", 2, 3, &umr_bitfield_default },
+	 { "STRAP_MED_yTSx_COUNT", 4, 5, &umr_bitfield_default },
+	 { "STRAP_SHORT_yTSx_COUNT", 6, 7, &umr_bitfield_default },
+	 { "STRAP_SKIP_INTERVAL", 8, 10, &umr_bitfield_default },
+	 { "STRAP_BYPASS_RCVR_DET", 11, 11, &umr_bitfield_default },
+	 { "STRAP_COMPLIANCE_DIS", 12, 12, &umr_bitfield_default },
+	 { "STRAP_FORCE_COMPLIANCE", 13, 13, &umr_bitfield_default },
+	 { "STRAP_REVERSE_LC_LANES", 14, 14, &umr_bitfield_default },
+	 { "STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_LANE_NEGOTIATION", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_STRAP_MISC[] = {
+	 { "STRAP_REVERSE_LANES", 0, 0, &umr_bitfield_default },
+	 { "STRAP_E2E_PREFIX_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_EXTENDED_FMT_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "STRAP_OBFF_SUPPORTED", 3, 4, &umr_bitfield_default },
+	 { "STRAP_LTR_SUPPORTED", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_BCH_ECC_CNTL[] = {
+	 { "STRAP_BCH_ECC_EN", 0, 0, &umr_bitfield_default },
+	 { "BCH_ECC_ERROR_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "BCH_ECC_ERROR_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_HPGI_PRIVATE[] = {
+	 { "PRESENCE_DETECT_CHANGED_PRIVATE", 3, 3, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE_PRIVATE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_HPGI[] = {
+	 { "REG_HPGI_ASSERT_TO_SMI_EN", 0, 0, &umr_bitfield_default },
+	 { "REG_HPGI_ASSERT_TO_SCI_EN", 1, 1, &umr_bitfield_default },
+	 { "REG_HPGI_DEASSERT_TO_SMI_EN", 2, 2, &umr_bitfield_default },
+	 { "REG_HPGI_DEASSERT_TO_SCI_EN", 3, 3, &umr_bitfield_default },
+	 { "REG_HPGI_HOOK", 7, 7, &umr_bitfield_default },
+	 { "HPGI_REG_ASSERT_TO_SMI_STATUS", 8, 8, &umr_bitfield_default },
+	 { "HPGI_REG_ASSERT_TO_SCI_STATUS", 9, 9, &umr_bitfield_default },
+	 { "HPGI_REG_DEASSERT_TO_SMI_STATUS", 10, 10, &umr_bitfield_default },
+	 { "HPGI_REG_DEASSERT_TO_SCI_STATUS", 11, 11, &umr_bitfield_default },
+	 { "HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS", 15, 15, &umr_bitfield_default },
+	 { "REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW[] = {
+	 { "VF_EN", 0, 0, &umr_bitfield_default },
+	 { "VF_NUM", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC[] = {
+	 { "CMD_CONTROL", 0, 7, &umr_bitfield_default },
+	 { "FCN_ID", 8, 15, &umr_bitfield_default },
+	 { "NXT_FCN_ID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS[] = {
+	 { "CMD_STATUS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL[] = {
+	 { "SOFT_PF_FLR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION[] = {
+	 { "RESET_NOTIFICATION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS[] = {
+	 { "VM_INIT_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT[] = {
+	 { "CNTXT_SIZE", 0, 6, &umr_bitfield_default },
+	 { "LOC", 7, 7, &umr_bitfield_default },
+	 { "CNTXT_OFFSET", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB[] = {
+	 { "TOTAL_FB_CONSUMED", 0, 15, &umr_bitfield_default },
+	 { "TOTAL_FB_AVAILABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS[] = {
+	 { "VM_BUSY_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS[] = {
+	 { "GPU_INFO_OFFSET", 8, 15, &umr_bitfield_default },
+	 { "AUTO_SCH_OFFSET", 16, 23, &umr_bitfield_default },
+	 { "DISP_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_SCRATCH[] = {
+	 { "PIF_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_STRAP_0[] = {
+	 { "STRAP_TX_RDY_XTND_DIS", 1, 1, &umr_bitfield_default },
+	 { "STRAP_RX_RDY_XTND_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_TX_STATUS_XTND_DIS", 3, 3, &umr_bitfield_default },
+	 { "STRAP_RX_STATUS_XTND_DIS", 4, 4, &umr_bitfield_default },
+	 { "STRAP_FORCE_OWN_MSTR", 5, 5, &umr_bitfield_default },
+	 { "STRAP_PIF_CDR_EN_MODE", 6, 7, &umr_bitfield_default },
+	 { "STRAP_RX_EI_FILTER", 8, 9, &umr_bitfield_default },
+	 { "STRAP_RX_DIS_HLD_EIE_IN_PS1", 10, 10, &umr_bitfield_default },
+	 { "STRAP_RX_DIS_HLD_EIE_IN_PS2", 11, 11, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_12", 12, 12, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_13", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_14", 14, 14, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_15", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_16", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_CTRL[] = {
+	 { "PIF_PLL_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "DTM_FORCE_FREQDIV_X1", 1, 1, &umr_bitfield_default },
+	 { "PIF_PLL_HNDSHK_EARLY_ABORT", 2, 2, &umr_bitfield_default },
+	 { "PIF_PLL_PWRDN_EARLY_EXIT", 3, 3, &umr_bitfield_default },
+	 { "PHY_RST_PWROK_VDD", 4, 4, &umr_bitfield_default },
+	 { "PIF_PLL_STATUS", 6, 7, &umr_bitfield_default },
+	 { "PIF_PLL_DEGRADE_OFF_VOTE", 8, 8, &umr_bitfield_default },
+	 { "PIF_PLL_UNUSED_OFF_VOTE", 9, 9, &umr_bitfield_default },
+	 { "PIF_PLL_DEGRADE_S2_VOTE", 10, 10, &umr_bitfield_default },
+	 { "PIF_PG_EXIT_MODE", 11, 11, &umr_bitfield_default },
+	 { "PIF_DEGRADE_PWR_PLL_MODE", 12, 12, &umr_bitfield_default },
+	 { "PIF_LANEUNUSED_AFFECT_GANG", 13, 13, &umr_bitfield_default },
+	 { "PIF_PG_ABORT_DISABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_TX_CTRL[] = {
+	 { "TXPWR_IN_S2", 0, 2, &umr_bitfield_default },
+	 { "TXPWR_IN_SPDCHNG", 3, 5, &umr_bitfield_default },
+	 { "TXPWR_IN_OFF", 6, 8, &umr_bitfield_default },
+	 { "TXPWR_IN_DEGRADE", 9, 11, &umr_bitfield_default },
+	 { "TXPWR_IN_UNUSED", 12, 14, &umr_bitfield_default },
+	 { "TXPWR_IN_INIT", 15, 17, &umr_bitfield_default },
+	 { "TXPWR_IN_PLL_OFF", 18, 20, &umr_bitfield_default },
+	 { "TXPWR_IN_DEGRADE_MODE", 21, 21, &umr_bitfield_default },
+	 { "TXPWR_IN_UNUSED_MODE", 22, 22, &umr_bitfield_default },
+	 { "TXPWR_GATING_IN_L1", 23, 23, &umr_bitfield_default },
+	 { "TXPWR_GATING_IN_UNUSED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_TX_CTRL2[] = {
+	 { "TX_RDY_DASRT_COUNT", 0, 2, &umr_bitfield_default },
+	 { "TX_STATUS_DASRT_COUNT", 3, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_DELAY", 6, 8, &umr_bitfield_default },
+	 { "TX_L1_PG_PHY_STATUS_MODE", 9, 9, &umr_bitfield_default },
+	 { "TX_OFF_PG_PHY_STATUS_MODE", 10, 10, &umr_bitfield_default },
+	 { "TX_HIGH_IMP_STAG_MP", 16, 16, &umr_bitfield_default },
+	 { "TX_HIGH_IMP_STAG_MODE", 17, 18, &umr_bitfield_default },
+	 { "TX_FORCE_DATA_VALID", 21, 21, &umr_bitfield_default },
+	 { "TX_L0_TO_HIZ_DLY", 22, 24, &umr_bitfield_default },
+	 { "TX_FIFO_INIT_UPCONFIG", 25, 25, &umr_bitfield_default },
+	 { "TX_HIZ_TO_L0_DLY", 26, 28, &umr_bitfield_default },
+	 { "TX_LINKSPEED_ACK_IN_S2", 29, 29, &umr_bitfield_default },
+	 { "TX_DELAY_FIFO_INIT_IN_S1", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_RX_CTRL[] = {
+	 { "RXPWR_IN_S2", 0, 2, &umr_bitfield_default },
+	 { "RXPWR_IN_SPDCHNG", 3, 5, &umr_bitfield_default },
+	 { "RXPWR_IN_OFF", 6, 8, &umr_bitfield_default },
+	 { "RXPWR_IN_DEGRADE", 9, 11, &umr_bitfield_default },
+	 { "RXPWR_IN_UNUSED", 12, 14, &umr_bitfield_default },
+	 { "RXPWR_IN_INIT", 15, 17, &umr_bitfield_default },
+	 { "RXPWR_IN_PLL_OFF", 18, 20, &umr_bitfield_default },
+	 { "RXPWR_IN_DEGRADE_MODE", 21, 21, &umr_bitfield_default },
+	 { "RXPWR_IN_UNUSED_MODE", 22, 22, &umr_bitfield_default },
+	 { "RXPWR_GATING_IN_L1", 23, 23, &umr_bitfield_default },
+	 { "RXPWR_GATING_IN_UNUSED", 24, 24, &umr_bitfield_default },
+	 { "RX_HLD_EIE_COUNT", 25, 25, &umr_bitfield_default },
+	 { "RX_EI_DET_IN_PS2_DEGRADE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_RX_CTRL2[] = {
+	 { "RX_RDY_DASRT_COUNT", 0, 2, &umr_bitfield_default },
+	 { "RX_STATUS_DASRT_COUNT", 3, 5, &umr_bitfield_default },
+	 { "RXPHYSTATUS_DELAY", 6, 8, &umr_bitfield_default },
+	 { "RX_L1_PG_PHY_STATUS_MODE", 9, 9, &umr_bitfield_default },
+	 { "RX_OFF_PG_PHY_STATUS_MODE", 10, 10, &umr_bitfield_default },
+	 { "FORCE_CDREN_IN_L0S", 16, 16, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_MODE", 17, 18, &umr_bitfield_default },
+	 { "EI_DET_ON_TIME", 19, 20, &umr_bitfield_default },
+	 { "EI_DET_OFF_TIME", 21, 23, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_DIS_IN_PS1", 24, 24, &umr_bitfield_default },
+	 { "RX_CDR_XTND_MODE", 25, 26, &umr_bitfield_default },
+	 { "RX_L0S_TO_L0_DETECT_EI", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_GLB_OVRD[] = {
+	 { "RXDETECT_OVERRIDE_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_1", 1, 1, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_3", 3, 3, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_5", 5, 5, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_6", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_7", 7, 7, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_GLB_OVRD2[] = {
+	 { "X2_LANE_1_0_OVRD", 0, 0, &umr_bitfield_default },
+	 { "X2_LANE_3_2_OVRD", 1, 1, &umr_bitfield_default },
+	 { "X2_LANE_5_4_OVRD", 2, 2, &umr_bitfield_default },
+	 { "X2_LANE_7_6_OVRD", 3, 3, &umr_bitfield_default },
+	 { "X2_LANE_9_8_OVRD", 4, 4, &umr_bitfield_default },
+	 { "X2_LANE_11_10_OVRD", 5, 5, &umr_bitfield_default },
+	 { "X2_LANE_13_12_OVRD", 6, 6, &umr_bitfield_default },
+	 { "X2_LANE_15_14_OVRD", 7, 7, &umr_bitfield_default },
+	 { "X4_LANE_3_0_OVRD", 8, 8, &umr_bitfield_default },
+	 { "X4_LANE_7_4_OVRD", 9, 9, &umr_bitfield_default },
+	 { "X4_LANE_11_8_OVRD", 10, 10, &umr_bitfield_default },
+	 { "X4_LANE_15_12_OVRD", 11, 11, &umr_bitfield_default },
+	 { "X8_LANE_7_0_OVRD", 16, 16, &umr_bitfield_default },
+	 { "X8_LANE_15_8_OVRD", 17, 17, &umr_bitfield_default },
+	 { "X16_LANE_15_0_OVRD", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_BIF_CMD_STATUS[] = {
+	 { "TXPHYSTATUS_0", 0, 0, &umr_bitfield_default },
+	 { "TXPHYSTATUS_1", 1, 1, &umr_bitfield_default },
+	 { "TXPHYSTATUS_2", 2, 2, &umr_bitfield_default },
+	 { "TXPHYSTATUS_3", 3, 3, &umr_bitfield_default },
+	 { "TXPHYSTATUS_4", 4, 4, &umr_bitfield_default },
+	 { "TXPHYSTATUS_5", 5, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_6", 6, 6, &umr_bitfield_default },
+	 { "TXPHYSTATUS_7", 7, 7, &umr_bitfield_default },
+	 { "RXPHYSTATUS_0", 8, 8, &umr_bitfield_default },
+	 { "RXPHYSTATUS_1", 9, 9, &umr_bitfield_default },
+	 { "RXPHYSTATUS_2", 10, 10, &umr_bitfield_default },
+	 { "RXPHYSTATUS_3", 11, 11, &umr_bitfield_default },
+	 { "RXPHYSTATUS_4", 12, 12, &umr_bitfield_default },
+	 { "RXPHYSTATUS_5", 13, 13, &umr_bitfield_default },
+	 { "RXPHYSTATUS_6", 14, 14, &umr_bitfield_default },
+	 { "RXPHYSTATUS_7", 15, 15, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_0", 16, 16, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_1", 17, 17, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_2", 18, 18, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_3", 19, 19, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_4", 20, 20, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_5", 21, 21, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_6", 22, 22, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_7", 23, 23, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_0", 24, 24, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_1", 25, 25, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_2", 26, 26, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_3", 27, 27, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_4", 28, 28, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_5", 29, 29, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_6", 30, 30, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_CMD_BUS_CTRL[] = {
+	 { "CMD_BUS_SCHL_MODE", 0, 1, &umr_bitfield_default },
+	 { "CMD_BUS_STAG_MODE", 2, 3, &umr_bitfield_default },
+	 { "CMD_BUS_STAG_DIS", 4, 4, &umr_bitfield_default },
+	 { "CMD_BUS_SCH_REQ_MODE", 5, 6, &umr_bitfield_default },
+	 { "CMD_BUS_IGNR_PEND_PWR", 7, 7, &umr_bitfield_default },
+	 { "SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES", 8, 8, &umr_bitfield_default },
+	 { "CMD_BUS_IGNR_PWR_NOT_ON", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_CMD_BUS_GLB_OVRD[] = {
+	 { "TXMARG_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "DEEMPH_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "PLLFREQ_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TXMARG", 3, 5, &umr_bitfield_default },
+	 { "DEEMPH", 6, 6, &umr_bitfield_default },
+	 { "PLLFREQ", 7, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_PIF_OVRD", 9, 9, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_0", 16, 16, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_1", 17, 17, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_2", 18, 18, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_3", 19, 19, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_4", 20, 20, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_5", 21, 21, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_6", 22, 22, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_7", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE0_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_0", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_0", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_0", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_0", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_0", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_0", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_0", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_0", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE0_OVRD2[] = {
+	 { "GANGMODE_0", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_0", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_0", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_0", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_0", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_0", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_0", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_0", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_0", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_0", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_0", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_0", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE1_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_1", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_1", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_1", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_1", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_1", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_1", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_1", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_1", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_1", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_1", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_1", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_1", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE1_OVRD2[] = {
+	 { "GANGMODE_1", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_1", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_1", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_1", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_1", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_1", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_1", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_1", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_1", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_1", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_1", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE2_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_2", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_2", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_2", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_2", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_2", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_2", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_2", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_2", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_2", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_2", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_2", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_2", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_2", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE2_OVRD2[] = {
+	 { "GANGMODE_2", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_2", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_2", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_2", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_2", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_2", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_2", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_2", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_2", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_2", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_2", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_2", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE3_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_3", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_3", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_3", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_3", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_3", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_3", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_3", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_3", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_3", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_3", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_3", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_3", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_3", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE3_OVRD2[] = {
+	 { "GANGMODE_3", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_3", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_3", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_3", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_3", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_3", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_3", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_3", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_3", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_3", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_3", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_3", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE4_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_4", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_4", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_4", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_4", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_4", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_4", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_4", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_4", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_4", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_4", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_4", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_4", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE4_OVRD2[] = {
+	 { "GANGMODE_4", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_4", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_4", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_4", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_4", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_4", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_4", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_4", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_4", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_4", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_4", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_4", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE5_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_5", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_5", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_5", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_5", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_5", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_5", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_5", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_5", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_5", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_5", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_5", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_5", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_5", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE5_OVRD2[] = {
+	 { "GANGMODE_5", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_5", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_5", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_5", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_5", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_5", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_5", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_5", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_5", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_5", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_5", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_5", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE6_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_6", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_6", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_6", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_6", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_6", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_6", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_6", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_6", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_6", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_6", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_6", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_6", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_6", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE6_OVRD2[] = {
+	 { "GANGMODE_6", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_6", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_6", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_6", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_6", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_6", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_6", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_6", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_6", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_6", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_6", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_6", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE7_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_7", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_7", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_7", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_7", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_7", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_7", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_7", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_7", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_7", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_7", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_7", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_7", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_7", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PIF_LANE7_OVRD2[] = {
+	 { "GANGMODE_7", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_7", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_7", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_7", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_7", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_7", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_7", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_7", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_7", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_7", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_7", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_7", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB[] = {
+	 { "FB_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "FB_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT[] = {
+	 { "GPU_IDLE_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0[] = {
+	 { "LOWER", 0, 15, &umr_bitfield_default },
+	 { "UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1[] = {
+	 { "LOWER", 0, 15, &umr_bitfield_default },
+	 { "UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2[] = {
+	 { "LOWER", 0, 15, &umr_bitfield_default },
+	 { "UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVENDOR_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+	 { "LENGTH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3[] = {
+	 { "LOWER", 0, 15, &umr_bitfield_default },
+	 { "UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG0[] = {
+	 { "BACKUP", 0, 15, &umr_bitfield_default },
+	 { "CFG_IDLEDET_TH", 16, 17, &umr_bitfield_default },
+	 { "DBG_RX2TXBYP_SEL", 20, 22, &umr_bitfield_default },
+	 { "DBG_RXFEBYP_EN", 23, 23, &umr_bitfield_default },
+	 { "DBG_RXPRBS_CLR", 24, 24, &umr_bitfield_default },
+	 { "DBG_RXTOGGLE_EN", 25, 25, &umr_bitfield_default },
+	 { "DBG_TX2RXLBACK_EN", 26, 26, &umr_bitfield_default },
+	 { "TXCFG_CMGOOD_RANGE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG1[] = {
+	 { "RXDBG_CDR_FR_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_CDR_FR_BYP_VAL", 1, 6, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_EN", 7, 7, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_VAL", 8, 13, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_EN", 14, 14, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_VAL", 15, 21, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_VAL", 23, 29, &umr_bitfield_default },
+	 { "TST_LOSPDTST_EN", 30, 30, &umr_bitfield_default },
+	 { "PLL_CFG_DISPCLK_DIV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG2[] = {
+	 { "RXDBG_D2TH_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_D2TH_BYP_VAL", 1, 7, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_EN", 8, 8, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_VAL", 9, 15, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_EN", 16, 16, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_VAL", 17, 23, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_EN", 24, 24, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_VAL", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG3[] = {
+	 { "RXDBG_SEL", 0, 4, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF0_SEL", 5, 6, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF1_SEL", 7, 8, &umr_bitfield_default },
+	 { "BG_CFG_RO_REG_VREF_SEL", 9, 10, &umr_bitfield_default },
+	 { "BG_DBG_VREFBYP_EN", 11, 11, &umr_bitfield_default },
+	 { "BG_DBG_IREFBYP_EN", 12, 12, &umr_bitfield_default },
+	 { "BG_DBG_ANALOG_SEL", 14, 16, &umr_bitfield_default },
+	 { "DBG_DLL_CLK_SEL", 18, 20, &umr_bitfield_default },
+	 { "PLL_DISPCLK_CMOS_SEL", 21, 21, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_VAL", 23, 26, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_EN", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_VAL", 28, 30, &umr_bitfield_default },
+	 { "DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG4[] = {
+	 { "DBG_RXAPU_INST", 0, 15, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_VAL", 16, 17, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_EN", 18, 18, &umr_bitfield_default },
+	 { "DBG_RXAPU_EXEC", 22, 25, &umr_bitfield_default },
+	 { "DBG_RXDLL_VREG_REF_SEL", 26, 26, &umr_bitfield_default },
+	 { "PWRGOOD_OVRD", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXRDATA_GATING_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_CTRL_REG5[] = {
+	 { "DBG_RXAPU_MODE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_ALL_CBI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_ALL_CBI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_ALL_CBI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_ALL_CBI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_IMPCAL_ACTIVE_CBI_UPDT", 4, 4, &umr_bitfield_default },
+	 { "TXNIMP", 8, 11, &umr_bitfield_default },
+	 { "TXPIMP", 12, 15, &umr_bitfield_default },
+	 { "RXIMP", 16, 19, &umr_bitfield_default },
+	 { "IMPCAL_ACTIVE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG1[] = {
+	 { "IGNR_LINKSPEED_CBI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_CBI_UPDT_L0T3", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_CBI_UPDT_L0T3", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_0", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_1", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_2", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_3", 15, 15, &umr_bitfield_default },
+	 { "LINKSPEED_0", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_0", 18, 19, &umr_bitfield_default },
+	 { "LINKSPEED_1", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_1", 22, 23, &umr_bitfield_default },
+	 { "LINKSPEED_2", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_2", 26, 27, &umr_bitfield_default },
+	 { "LINKSPEED_3", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG2[] = {
+	 { "IGNR_LINKSPEED_CBI_UPDT_L4T7", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_CBI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_CBI_UPDT_L4T7", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_4", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_5", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_6", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_7", 15, 15, &umr_bitfield_default },
+	 { "LINKSPEED_4", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_4", 18, 19, &umr_bitfield_default },
+	 { "LINKSPEED_5", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_5", 22, 23, &umr_bitfield_default },
+	 { "LINKSPEED_6", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_6", 26, 27, &umr_bitfield_default },
+	 { "LINKSPEED_7", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_7", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG3[] = {
+	 { "IGNR_LINKSPEED_CBI_UPDT_L8T11", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_CBI_UPDT_L8T11", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_CBI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_8", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_9", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_10", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_11", 15, 15, &umr_bitfield_default },
+	 { "LINKSPEED_8", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_8", 18, 19, &umr_bitfield_default },
+	 { "LINKSPEED_9", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_9", 22, 23, &umr_bitfield_default },
+	 { "LINKSPEED_10", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_10", 26, 27, &umr_bitfield_default },
+	 { "LINKSPEED_11", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_11", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_SCI_STAT_OVRD_REG4[] = {
+	 { "IGNR_LINKSPEED_CBI_UPDT_L12T15", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_CBI_UPDT_L12T15", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_CBI_UPDT_L12T15", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_12", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_13", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_14", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_15", 15, 15, &umr_bitfield_default },
+	 { "LINKSPEED_12", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_12", 18, 19, &umr_bitfield_default },
+	 { "LINKSPEED_13", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_13", 22, 23, &umr_bitfield_default },
+	 { "LINKSPEED_14", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_14", 26, 27, &umr_bitfield_default },
+	 { "LINKSPEED_15", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG0[] = {
+	 { "TXPDTERM_VAL_OVRD_VAL", 0, 15, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG1[] = {
+	 { "TXPDTERM_VAL_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_VAL", 3, 3, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_EN", 15, 15, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_GLB_OVRD_REG2[] = {
+	 { "BG_PWRON_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "BG_PWRON_OVRD_VAL", 1, 1, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_OVRD_VAL", 3, 3, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_OVRD_EN", 4, 4, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_OVRD_VAL", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_GLB_REG0[] = {
+	 { "STRAP_QUICK_SIM_START", 1, 1, &umr_bitfield_default },
+	 { "STRAP_DFT_RXBSCAN_EN_VAL", 2, 2, &umr_bitfield_default },
+	 { "STRAP_DFT_CALIB_BYPASS", 3, 3, &umr_bitfield_default },
+	 { "STRAP_FORCE_LC_PLL_ON", 4, 4, &umr_bitfield_default },
+	 { "STRAP_CFG_IDLEDET_TH", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL", 7, 11, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_OVR_PWRSF", 12, 12, &umr_bitfield_default },
+	 { "STRAP_RX_TRK_MODE_0_", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PWRGOOD_OVRD", 14, 14, &umr_bitfield_default },
+	 { "STRAP_DBG_RXDLL_VREG_REF_SEL", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_LC_VCO_TUNE", 16, 19, &umr_bitfield_default },
+	 { "STRAP_DBG_RXRDATA_GATING_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "STRAP_DBG_RXPI_OFFSET_BYP_VAL", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_TX_REG0[] = {
+	 { "STRAP_TX_CFG_DRV0_EN", 1, 4, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV0_TAP_SEL", 5, 8, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV1_EN", 9, 13, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV1_TAP_SEL", 14, 18, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV2_EN", 19, 22, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV2_TAP_SEL", 23, 26, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRVX_EN", 27, 27, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRVX_TAP_SEL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_RX_TRK_MODE_1_", 29, 29, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_SWING_BOOST_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_RX_REG0[] = {
+	 { "STRAP_RX_CFG_TH_LOOP_GAIN", 1, 4, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_DLL_FLOCK_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "STRAP_DBG_RXPI_OFFSET_BYP_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_LC_REG_VREF0_SEL", 8, 9, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_LC_REG_VREF1_SEL", 10, 11, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_CDR_TIME", 12, 15, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_FOM_TIME", 16, 19, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_TIME", 20, 23, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_OC_TIME", 24, 27, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_RPTR_RST_VAL", 28, 30, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_TERM_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_RX_REG1[] = {
+	 { "STRAP_RX_CFG_CDR_PI_STPSZ", 1, 1, &umr_bitfield_default },
+	 { "STRAP_TX_DEEMPH_PRSHT_STNG", 2, 4, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_RO_REG_VREF_SEL", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_POLE_BYP_DIS", 7, 7, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_POLE_BYP_VAL", 8, 10, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_CDR_PH_GAIN", 11, 14, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_ADAPT_MODE", 15, 24, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_DFE_TIME", 25, 28, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_LOOP_GAIN", 29, 30, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_SHUNT_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_PLL_REG0[] = {
+	 { "STRAP_PLL_CFG_LC_BW_CNTRL", 1, 3, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_LC_LF_CNTRL", 4, 12, &umr_bitfield_default },
+	 { "STRAP_TX_RXDET_X1_SSF", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_RO_BW_CNTRL", 16, 23, &umr_bitfield_default },
+	 { "STRAP_PLL_STRAP_SEL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_PIN_REG0[] = {
+	 { "STRAP_TX_DEEMPH_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_TX_FULL_SWING", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_GLB_REG1[] = {
+	 { "STRAP_RX_ADAPT_RST_MODE", 1, 2, &umr_bitfield_default },
+	 { "STRAP_RX_L0_ENTRY_MODE", 3, 4, &umr_bitfield_default },
+	 { "STRAP_RX_EI_FILTER", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_ADAPT_RST_SUB_ENTRY", 7, 7, &umr_bitfield_default },
+	 { "STRAP_RX_PS0_RDY_GEN_MODE", 8, 9, &umr_bitfield_default },
+	 { "STRAP_RX_DLL_RESET_IN_SPDCHG", 10, 10, &umr_bitfield_default },
+	 { "STRAP_RX_ADAPT_TIME_OUT", 11, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_STRAP_GLB_REG2[] = {
+	 { "STRAP_BPHYC_PLL_RAMP_UP_TIME", 2, 4, &umr_bitfield_default },
+	 { "STRAP_IMPCAL_SETTLE_TIME", 5, 6, &umr_bitfield_default },
+	 { "STRAP_BG_SETTLE_TIME", 7, 8, &umr_bitfield_default },
+	 { "STRAP_TX_CMDET_TIME", 9, 10, &umr_bitfield_default },
+	 { "STRAP_TX_STARTUP_TIME", 11, 12, &umr_bitfield_default },
+	 { "STRAP_B_PCB_DIS0", 28, 28, &umr_bitfield_default },
+	 { "STRAP_B_PCB_DIS1", 29, 29, &umr_bitfield_default },
+	 { "STRAP_B_PCB_DRV_STR", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG0[] = {
+	 { "DFT_NUM_STEPS", 0, 5, &umr_bitfield_default },
+	 { "DFT_DISABLE_ERR", 7, 7, &umr_bitfield_default },
+	 { "DFT_CLK_PER_STEP", 8, 11, &umr_bitfield_default },
+	 { "DFT_MODE_CDR_EN", 20, 20, &umr_bitfield_default },
+	 { "DFT_EN_RECOVERY", 21, 21, &umr_bitfield_default },
+	 { "DFT_INCR_SWP_EN", 22, 22, &umr_bitfield_default },
+	 { "DFT_DECR_SWP_EN", 23, 23, &umr_bitfield_default },
+	 { "DFT_RECOVERY_TIME", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG1[] = {
+	 { "DFT_BYPASS_VALUE", 0, 7, &umr_bitfield_default },
+	 { "DFT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "DFT_BLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DFT_NUM_OF_TESTS", 17, 19, &umr_bitfield_default },
+	 { "DFT_CHECK_TIME", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_REG2[] = {
+	 { "DFT_LANE_EN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_DEBUG_CTRL_REG0[] = {
+	 { "DFT_PHY_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DFT_PHY_DEBUG_MODE", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_DFT_JIT_INJ_STAT_REG0[] = {
+	 { "DFT_STAT_DECR", 0, 7, &umr_bitfield_default },
+	 { "DFT_STAT_INCR", 8, 15, &umr_bitfield_default },
+	 { "DFT_STAT_FINISHED", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO_GLB_CTRL_REG0[] = {
+	 { "PLL_TST_LOSPDTST_SRC", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 2, 2, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 3, 3, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 4, 4, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 5, 5, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 6, 6, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_LUT_ENTRY_LS2", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_LUT_ENTRY_LS2", 8, 8, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 9, 9, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 10, 10, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 11, 11, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 12, 12, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 13, 13, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 14, 14, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_GATING_EN", 15, 15, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_GATING_EN", 16, 16, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_GATING_EN", 17, 17, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_GATING_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_CTRL_REG0[] = {
+	 { "PLL_DBG_RO_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_RO_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_DBG_RO_LF_CNTRL_0", 4, 10, &umr_bitfield_default },
+	 { "PLL_TST_RO_USAMPLE_EN_0", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_OVRD_REG0[] = {
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0", 0, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0", 9, 11, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_VAL_0", 15, 27, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0", 30, 30, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_OVRD_REG1[] = {
+	 { "PLL_CFG_RO_REFDIV_OVRD_VAL_0", 0, 4, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFDIV_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_VAL_0", 6, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0", 11, 11, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0", 19, 21, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO0_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO0_IGNR_PLLFREQ_CBI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO0_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO0_PLLFREQ", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO1_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO1_IGNR_PLLFREQ_CBI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO1_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO1_PLLFREQ", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO2_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO2_IGNR_PLLFREQ_CBI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO2_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO2_PLLFREQ", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO3_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO3_IGNR_PLLFREQ_CBI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO3_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO3_PLLFREQ", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_CTRL_REG0[] = {
+	 { "PLL_DBG_LC_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_LC_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_TST_LC_USAMPLE_EN_0", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_OVRD_REG0[] = {
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0", 4, 6, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_VAL_0", 10, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0", 19, 27, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_VAL_0", 29, 30, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_OVRD_REG1[] = {
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0", 14, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC0_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC0_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC1_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC1_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC2_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC2_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC3_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC3_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG0[] = {
+	 { "RX_CFG_ADAPT_MODE_GEN1", 0, 9, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN2", 10, 19, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN3", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG1[] = {
+	 { "RX_CFG_CDR_FR_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN1", 24, 24, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN2", 25, 25, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN3", 26, 26, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_ASRT_TO_DCLK_EN", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG2[] = {
+	 { "RX_CFG_CDR_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN1", 24, 25, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN2", 26, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN3", 28, 29, &umr_bitfield_default },
+	 { "RX_DCLK_EN_ASRT_TO_ADAPT_HLD", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG3[] = {
+	 { "RX_CFG_CDR_FR_EN_GEN1", 0, 0, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN2", 1, 1, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN3", 2, 2, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_MODE_GEN1", 3, 4, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_MODE_GEN2", 5, 6, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_MODE_GEN3", 7, 8, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_SUB_MODE", 9, 11, &umr_bitfield_default },
+	 { "RX_L0_ENTRY_MODE_GEN1", 12, 13, &umr_bitfield_default },
+	 { "RX_L0_ENTRY_MODE_GEN2", 14, 15, &umr_bitfield_default },
+	 { "RX_L0_ENTRY_MODE_GEN3", 16, 17, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG4[] = {
+	 { "RX_CFG_FOM_BER_GEN1", 0, 2, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN2", 3, 5, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN3", 6, 8, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN1", 9, 11, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN2", 12, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN3", 15, 17, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG5[] = {
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1", 0, 4, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2", 5, 9, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3", 10, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN1", 15, 15, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN2", 16, 16, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN3", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN1", 18, 18, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN2", 19, 19, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN3", 20, 20, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_AUX_PWRON_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG6[] = {
+	 { "RX_CFG_LEQ_TIME_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0", 24, 24, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS2", 26, 26, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_LUT_ENTRY_LS2", 27, 27, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS", 28, 28, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_L1_DLL_OFF", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG7[] = {
+	 { "RX_CFG_TH_LOOP_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS2", 13, 13, &umr_bitfield_default },
+	 { "RX_DCLK_EN_AFTER_DLL_LOCK", 14, 14, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_LUT_ENTRY_PS3", 16, 16, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_LUT_ENTRY_PS2", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN1", 18, 20, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN2", 21, 23, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN3", 24, 26, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN3", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_CTRL_REG8[] = {
+	 { "RX_DLL_LOCK_TIME", 0, 1, &umr_bitfield_default },
+	 { "RX_DLL_SPEEDCHANGE_RESET_TIME", 2, 3, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_IN_RAMPDOWN", 4, 4, &umr_bitfield_default },
+	 { "RX_FSM_L0S_IF_RX_RDY", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_RXPWR_CBI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_RXPWR_CBI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_RXPWR_CBI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_RXPWR_CBI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3", 4, 4, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7", 5, 5, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11", 6, 6, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15", 7, 7, &umr_bitfield_default },
+	 { "IGNR_REQUESTTRK_CBI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_REQUESTTRK_CBI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_REQUESTTRK_CBI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_REQUESTTRK_CBI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_CBI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_CBI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_CBI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_CBI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_CBI_UPDT_L0T3", 16, 16, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_CBI_UPDT_L4T7", 17, 17, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_CBI_UPDT_L8T11", 18, 18, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_CBI_UPDT_L12T15", 19, 19, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_CBI_UPDT_L0T3", 20, 20, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_CBI_UPDT_L4T7", 21, 21, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_CBI_UPDT_L8T11", 22, 22, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_CBI_UPDT_L12T15", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_OVRD_REG0[] = {
+	 { "RX_ADAPT_HLD_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_VAL", 6, 7, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_VAL", 15, 15, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_VAL", 17, 17, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_EN", 18, 18, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_VAL", 19, 19, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_EN", 20, 20, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_VAL", 21, 21, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_EN", 22, 22, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_GLB_OVRD_REG1[] = {
+	 { "RX_ADAPT_TRK_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_TRK_OVRD_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE0_CTRL_REG0[] = {
+	 { "RX_BACKUP_0", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_0", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_0", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_0", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_0", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_0", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_0", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_0", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE1_CTRL_REG0[] = {
+	 { "RX_BACKUP_1", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_1", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_1", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_1", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_1", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_1", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_1", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_1", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_1", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE2_CTRL_REG0[] = {
+	 { "RX_BACKUP_2", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_2", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_2", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_2", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_2", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_2", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_2", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_2", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_2", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE3_CTRL_REG0[] = {
+	 { "RX_BACKUP_3", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_3", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_3", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_3", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_3", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_3", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_3", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_3", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_3", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE4_CTRL_REG0[] = {
+	 { "RX_BACKUP_4", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_4", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_4", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_4", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_4", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_4", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_4", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_4", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_4", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE5_CTRL_REG0[] = {
+	 { "RX_BACKUP_5", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_5", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_5", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_5", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_5", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_5", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_5", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_5", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_5", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE6_CTRL_REG0[] = {
+	 { "RX_BACKUP_6", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_6", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_6", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_6", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_6", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_6", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_6", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_6", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_6", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE7_CTRL_REG0[] = {
+	 { "RX_BACKUP_7", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_7", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_7", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_7", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_7", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_7", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_7", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_7", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_7", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE8_CTRL_REG0[] = {
+	 { "RX_BACKUP_8", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_8", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_8", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_8", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_8", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_8", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_8", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_8", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_8", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_8", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_8", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_8", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE9_CTRL_REG0[] = {
+	 { "RX_BACKUP_9", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_9", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_9", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_9", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_9", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_9", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_9", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_9", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_9", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_9", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_9", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_9", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE10_CTRL_REG0[] = {
+	 { "RX_BACKUP_10", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_10", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_10", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_10", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_10", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_10", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_10", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_10", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_10", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_10", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_10", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_10", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE11_CTRL_REG0[] = {
+	 { "RX_BACKUP_11", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_11", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_11", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_11", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_11", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_11", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_11", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_11", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_11", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_11", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_11", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_11", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE12_CTRL_REG0[] = {
+	 { "RX_BACKUP_12", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_12", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_12", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_12", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_12", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_12", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_12", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_12", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_12", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_12", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_12", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_12", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE13_CTRL_REG0[] = {
+	 { "RX_BACKUP_13", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_13", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_13", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_13", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_13", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_13", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_13", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_13", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_13", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_13", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_13", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_13", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE14_CTRL_REG0[] = {
+	 { "RX_BACKUP_14", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_14", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_14", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_14", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_14", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_14", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_14", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_14", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_14", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_14", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_14", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_14", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE15_CTRL_REG0[] = {
+	 { "RX_BACKUP_15", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_15", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_15", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_15", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_15", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_15", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_15", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_15", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_15", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_15", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_15", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_15", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_CTRL_REG0[] = {
+	 { "TX_DRV_DATA_ASRT_DLY_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_DSRT_DLY_VAL", 3, 5, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN1", 8, 10, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN2", 11, 13, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN3", 14, 16, &umr_bitfield_default },
+	 { "TX_STAGGER_CTRL", 17, 18, &umr_bitfield_default },
+	 { "TX_DATA_CLK_GATING", 19, 19, &umr_bitfield_default },
+	 { "TX_PRESET_TABLE_BYPASS", 20, 20, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_EN", 21, 21, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_DIR_VER", 22, 22, &umr_bitfield_default },
+	 { "TX_DCLK_EN_LSX_ALWAYS_ON", 23, 23, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_IN_PS4", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_LANE_SKEW_CTRL[] = {
+	 { "TX_CFG_GROUPX1_EN_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_6", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_7", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_8", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_9", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_10", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_11", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_12", 12, 12, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_13", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_14", 14, 14, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_15", 15, 15, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L0T1", 16, 16, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L2T3", 17, 17, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L4T5", 18, 18, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L6T7", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L8T9", 20, 20, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L10T11", 21, 21, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L12T13", 22, 22, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L14T15", 23, 23, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L0T3", 24, 24, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L4T7", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L8T11", 26, 26, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L12T15", 27, 27, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L0T7", 28, 28, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L8T15", 29, 29, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_L0T15", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_TXPWR_CBI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_TXPWR_CBI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_TXPWR_CBI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_TXPWR_CBI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_CBI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_CBI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_CBI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_CBI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_CBI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_CBI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_CBI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_CBI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[] = {
+	 { "ACCEPT_ENTRY_0", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_1", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_2", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_3", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_4", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_5", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_6", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_7", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_8", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_9", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_10", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_11", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_12", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_13", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_14", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_15", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_16", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_17", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_18", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_19", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_20", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_21", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_22", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_23", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_24", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_25", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_26", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_27", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_28", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_29", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_30", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_31", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[] = {
+	 { "ACCEPT_ENTRY_32", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_33", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_34", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_35", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_36", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_37", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_38", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_39", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_40", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_41", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_42", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_43", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_44", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_45", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_46", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_47", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_48", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_49", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_50", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_51", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_52", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_53", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_54", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_55", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_56", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_57", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_58", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_59", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_60", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_61", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_62", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_63", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[] = {
+	 { "ACCEPT_ENTRY_64", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_65", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_66", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_67", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_68", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_69", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_70", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_71", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_72", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_73", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_74", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_75", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_76", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_77", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_78", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_79", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_80", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_81", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_82", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_83", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_84", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_85", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_86", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_87", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_88", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_89", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_90", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_91", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_92", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_93", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_94", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_95", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[] = {
+	 { "ACCEPT_ENTRY_96", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_97", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_98", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_99", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_100", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_101", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_102", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_103", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_104", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_105", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_106", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_107", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_108", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_109", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG0[] = {
+	 { "TX_CFG_DCLK_DIV_OVRD_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_CFG_DCLK_DIV_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN1_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL", 9, 12, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_OVRD_EN", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN1_OVRD_VAL", 14, 18, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_OVRD_EN", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN1_OVRD_VAL", 26, 29, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_OVRD_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG1[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_OVRD_EN", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN1_OVRD_VAL", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_OVRD_EN", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_VAL", 15, 24, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_VAL", 26, 26, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_EN", 27, 27, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG2[] = {
+	 { "TX_WRITE_EN_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "TX_WRITE_EN_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_EN", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_VAL", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_EN", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_EN", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_VAL", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_EN", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN2_OVRD_VAL", 12, 15, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL", 16, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN2_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG3[] = {
+	 { "TX_CFG_DRV2_EN_GEN2_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN2_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN3_OVRD_VAL", 10, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL", 14, 17, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN3_OVRD_VAL", 18, 22, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL", 23, 27, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN3_OVRD_VAL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_GLB_OVRD_REG4[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN3_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_0", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_0", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_0", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_0", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_0", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_0", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_1", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_1", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_1", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_1", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_1", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_1", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_1", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_1", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_2", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_2", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_2", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_2", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_2", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_2", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_2", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_2", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_2", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_3", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_3", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_3", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_3", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_3", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_3", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_3", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_3", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_3", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_4", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_4", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_4", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_4", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_4", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_4", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_4", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_4", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_4", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_5", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_5", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_5", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_5", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_5", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_5", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_5", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_5", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_5", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_5", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_6", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_6", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_6", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_6", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_6", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_6", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_6", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_6", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_6", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_6", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_7", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_7", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_7", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_7", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_7", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_7", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_7", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_7", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_7", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_7", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_8", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_8", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_8", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_8", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_8", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_8", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_8", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_8", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_8", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_8", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_8", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_8", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_8", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_8", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_8", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_9", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_9", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_9", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_9", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_9", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_9", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_9", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_9", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_9", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_9", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_9", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_9", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_9", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_9", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_9", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_10", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_10", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_10", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_10", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_10", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_10", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_10", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_10", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_10", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_10", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_10", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_10", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_10", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_10", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_10", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_11", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_11", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_11", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_11", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_11", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_11", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_11", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_11", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_11", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_11", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_11", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_11", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_11", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_11", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_11", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_12", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_12", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_12", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_12", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_12", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_12", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_12", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_12", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_12", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_12", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_12", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_12", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_12", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_12", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_12", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_13", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_13", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_13", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_13", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_13", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_13", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_13", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_13", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_13", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_13", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_13", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_13", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_13", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_13", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_13", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_14", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_14", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_14", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_14", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_14", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_14", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_14", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_14", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_14", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_14", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_14", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_14", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_14", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_14", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_14", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_15", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_15", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_15", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_15", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_15", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_15", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_15", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_15", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_15", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_15", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_15", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_15", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_15", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_15", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_15", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4[] = {
+	 { "LOWER", 0, 15, &umr_bitfield_default },
+	 { "UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5[] = {
+	 { "LOWER", 0, 15, &umr_bitfield_default },
+	 { "UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmADAPTER_ID_W[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WRAP_SCRATCH1[] = {
+	 { "PCIE_WRAP_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WRAP_SCRATCH2[] = {
+	 { "PCIE_WRAP_SCRATCH2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WRAP_REG_TARG_MISC[] = {
+	 { "CLKEN_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WRAP_DTM_MISC[] = {
+	 { "DTM_BULKPHY_FREQDIV_OVERRIDE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WRAP_TURNAROUND_DAISYCHAIN[] = {
+	 { "END_BIFCORE_REGISTER_DAISYCHAIN", 0, 0, &umr_bitfield_default },
+	 { "END_WRAPPER_REGISTER_DAISYCHAIN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WRAP_MISC[] = {
+	 { "STRAP_BIF_HOLD_TRAINING_STICKY", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_QUICKSIM_START", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WRAP_PIF_MISC[] = {
+	 { "DTM_PIF_DELAY_FI", 0, 2, &umr_bitfield_default },
+	 { "DTM_PIF_DELAY_DI", 4, 6, &umr_bitfield_default },
+	 { "DTM_PIF_ATSEL_FI", 7, 7, &umr_bitfield_default },
+	 { "DTM_PIF_ATSEL_DI", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RXDET_OVERRIDE[] = {
+	 { "RxDetOvrVal", 0, 15, &umr_bitfield_default },
+	 { "RxDetOvrEn", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixREG_ADAPT_pciecore0_CONTROL[] = {
+	 { "ACCESS_MODE_pciecore0", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixREG_ADAPT_pwregt_CONTROL[] = {
+	 { "ACCESS_MODE_pwregt", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixREG_ADAPT_pwregr_CONTROL[] = {
+	 { "ACCESS_MODE_pwregr", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixREG_ADAPT_pif0_CONTROL[] = {
+	 { "ACCESS_MODE_pif0", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_CAP[] = {
+	 { "VERSION", 0, 2, &umr_bitfield_default },
+	 { "PME_CLOCK", 3, 3, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 5, 5, &umr_bitfield_default },
+	 { "AUX_CURRENT", 6, 8, &umr_bitfield_default },
+	 { "D1_SUPPORT", 9, 9, &umr_bitfield_default },
+	 { "D2_SUPPORT", 10, 10, &umr_bitfield_default },
+	 { "PME_SUPPORT", 11, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RESERVED[] = {
+	 { "PCIE_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_SCRATCH[] = {
+	 { "PCIE_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_NUM_NAK[] = {
+	 { "RX_NUM_NAK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_NUM_NAK_GENERATED[] = {
+	 { "RX_NUM_NAK_GENERATED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CNTL[] = {
+	 { "HWINIT_WR_LOCK", 0, 0, &umr_bitfield_default },
+	 { "LC_HOT_PLUG_DELAY_SEL", 1, 3, &umr_bitfield_default },
+	 { "UR_ERR_REPORT_DIS", 7, 7, &umr_bitfield_default },
+	 { "PCIE_MALFORM_ATOMIC_OPS", 8, 8, &umr_bitfield_default },
+	 { "PCIE_HT_NP_MEM_WRITE", 9, 9, &umr_bitfield_default },
+	 { "RX_SB_ADJ_PAYLOAD_SIZE", 10, 12, &umr_bitfield_default },
+	 { "RX_RCB_ATS_UC_DIS", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_REORDER_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_RCB_INVALID_SIZE_DIS", 17, 17, &umr_bitfield_default },
+	 { "RX_RCB_UNEXP_CPL_DIS", 18, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_TEST_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_PREFIX_DIS", 20, 20, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_ATTR_DIS", 21, 21, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_FUNCNUM_DIS", 22, 22, &umr_bitfield_default },
+	 { "RX_ATS_TRAN_CPL_SPLIT_DIS", 23, 23, &umr_bitfield_default },
+	 { "TX_CPL_DEBUG", 24, 29, &umr_bitfield_default },
+	 { "RX_IGNORE_LTR_MSG_UR", 30, 30, &umr_bitfield_default },
+	 { "RX_CPL_POSTED_REQ_ORD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CONFIG_CNTL[] = {
+	 { "DYN_CLK_LATENCY", 0, 3, &umr_bitfield_default },
+	 { "CI_MAX_PAYLOAD_SIZE_MODE", 16, 16, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_PAYLOAD_SIZE", 17, 19, &umr_bitfield_default },
+	 { "CI_MAX_READ_REQUEST_SIZE_MODE", 20, 20, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_READ_REQUEST_SIZE", 21, 23, &umr_bitfield_default },
+	 { "CI_MAX_READ_SAFE_MODE", 24, 24, &umr_bitfield_default },
+	 { "CI_EXTENDED_TAG_EN_OVERRIDE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_DEBUG_CNTL[] = {
+	 { "DEBUG_PORT_EN", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_SELECT", 8, 8, &umr_bitfield_default },
+	 { "DEBUG_LANE_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_INT_CNTL[] = {
+	 { "CORR_ERR_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_INT_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED_INT_EN", 3, 3, &umr_bitfield_default },
+	 { "MISC_ERR_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "POWER_STATE_CHG_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "LINK_BW_INT_EN", 7, 7, &umr_bitfield_default },
+	 { "QUIESCE_RCVD_INT_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_INT_STATUS[] = {
+	 { "CORR_ERR_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED_INT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "MISC_ERR_INT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "POWER_STATE_CHG_INT_STATUS", 6, 6, &umr_bitfield_default },
+	 { "LINK_BW_INT_STATUS", 7, 7, &umr_bitfield_default },
+	 { "QUIESCE_RCVD_INT_STATUS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CNTL2[] = {
+	 { "TX_ARB_ROUND_ROBIN_EN", 0, 0, &umr_bitfield_default },
+	 { "TX_ARB_SLV_LIMIT", 1, 5, &umr_bitfield_default },
+	 { "TX_ARB_MST_LIMIT", 6, 10, &umr_bitfield_default },
+	 { "TX_BLOCK_TLP_ON_PM_DIS", 11, 11, &umr_bitfield_default },
+	 { "TX_NP_MEM_WRITE_SWP_ENCODING", 12, 12, &umr_bitfield_default },
+	 { "TX_ATOMIC_OPS_DISABLE", 13, 13, &umr_bitfield_default },
+	 { "TX_ATOMIC_ORDERING_DIS", 14, 14, &umr_bitfield_default },
+	 { "SLV_MEM_LS_EN", 16, 16, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_LS_EN", 17, 17, &umr_bitfield_default },
+	 { "MST_MEM_LS_EN", 18, 18, &umr_bitfield_default },
+	 { "REPLAY_MEM_LS_EN", 19, 19, &umr_bitfield_default },
+	 { "SLV_MEM_SD_EN", 20, 20, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_SD_EN", 21, 21, &umr_bitfield_default },
+	 { "MST_MEM_SD_EN", 22, 22, &umr_bitfield_default },
+	 { "REPLAY_MEM_SD_EN", 23, 23, &umr_bitfield_default },
+	 { "RX_NP_MEM_WRITE_ENCODING", 24, 28, &umr_bitfield_default },
+	 { "SLV_MEM_DS_EN", 29, 29, &umr_bitfield_default },
+	 { "MST_MEM_DS_EN", 30, 30, &umr_bitfield_default },
+	 { "REPLAY_MEM_DS_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL2[] = {
+	 { "RX_IGNORE_EP_INVALIDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMRD_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMWR_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ATSTRANSREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_PAGEREQMSG_UR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_INVCPL_UR", 5, 5, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_SCALE", 9, 11, &umr_bitfield_default },
+	 { "SLVCPL_MEM_LS_EN", 12, 12, &umr_bitfield_default },
+	 { "SLVCPL_MEM_SD_EN", 13, 13, &umr_bitfield_default },
+	 { "SLVCPL_MEM_DS_EN", 14, 14, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_MAX_COUNT", 16, 25, &umr_bitfield_default },
+	 { "FLR_EXTEND_MODE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_F0_ATTR_CNTL[] = {
+	 { "TX_F0_IDO_OVERRIDE_P", 0, 1, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_NP", 2, 3, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_CPL", 4, 5, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_P", 6, 7, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_NP", 8, 9, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_P", 10, 11, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_NP", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_F1_F2_ATTR_CNTL[] = {
+	 { "TX_F1_IDO_OVERRIDE_P", 0, 1, &umr_bitfield_default },
+	 { "TX_F1_IDO_OVERRIDE_NP", 2, 3, &umr_bitfield_default },
+	 { "TX_F1_IDO_OVERRIDE_CPL", 4, 5, &umr_bitfield_default },
+	 { "TX_F1_RO_OVERRIDE_P", 6, 7, &umr_bitfield_default },
+	 { "TX_F1_RO_OVERRIDE_NP", 8, 9, &umr_bitfield_default },
+	 { "TX_F1_SNR_OVERRIDE_P", 10, 11, &umr_bitfield_default },
+	 { "TX_F1_SNR_OVERRIDE_NP", 12, 13, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_P", 16, 17, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_NP", 18, 19, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_CPL", 20, 21, &umr_bitfield_default },
+	 { "TX_F2_RO_OVERRIDE_P", 22, 23, &umr_bitfield_default },
+	 { "TX_F2_RO_OVERRIDE_NP", 24, 25, &umr_bitfield_default },
+	 { "TX_F2_SNR_OVERRIDE_P", 26, 27, &umr_bitfield_default },
+	 { "TX_F2_SNR_OVERRIDE_NP", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CI_CNTL[] = {
+	 { "CI_SLAVE_SPLIT_MODE", 2, 2, &umr_bitfield_default },
+	 { "CI_SLAVE_GEN_USR_DIS", 3, 3, &umr_bitfield_default },
+	 { "CI_MST_CMPL_DUMMY_DATA", 4, 4, &umr_bitfield_default },
+	 { "CI_SLV_RC_RD_REQ_SIZE", 6, 7, &umr_bitfield_default },
+	 { "CI_SLV_ORDERING_DIS", 8, 8, &umr_bitfield_default },
+	 { "CI_RC_ORDERING_DIS", 9, 9, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_DIS", 10, 10, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_MODE", 11, 11, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_SOR", 12, 12, &umr_bitfield_default },
+	 { "CI_MST_IGNORE_PAGE_ALIGNED_REQUEST", 13, 13, &umr_bitfield_default },
+	 { "CI_MST_ATOMIC_ADDR_HASH", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_BUS_CNTL[] = {
+	 { "PMI_INT_DIS", 6, 6, &umr_bitfield_default },
+	 { "IMMEDIATE_PMI_DIS", 7, 7, &umr_bitfield_default },
+	 { "TRUE_PM_STATUS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE6[] = {
+	 { "LC_PREV_STATE24", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE25", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE26", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE27", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE7[] = {
+	 { "LC_PREV_STATE28", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE29", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE30", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE31", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE8[] = {
+	 { "LC_PREV_STATE32", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE33", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE34", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE35", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE9[] = {
+	 { "LC_PREV_STATE36", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE37", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE38", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE39", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE10[] = {
+	 { "LC_PREV_STATE40", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE41", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE42", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE43", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE11[] = {
+	 { "LC_PREV_STATE44", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE45", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE46", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE47", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATUS1[] = {
+	 { "LC_REVERSE_RCVR", 0, 0, &umr_bitfield_default },
+	 { "LC_REVERSE_XMIT", 1, 1, &umr_bitfield_default },
+	 { "LC_OPERATING_LINK_WIDTH", 2, 4, &umr_bitfield_default },
+	 { "LC_DETECTED_LINK_WIDTH", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATUS2[] = {
+	 { "LC_TOTAL_INACTIVE_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_TURN_ON_LANE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WPR_CNTL[] = {
+	 { "WPR_RESET_HOT_RST_EN", 0, 0, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DWN_EN", 1, 1, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DIS_EN", 2, 2, &umr_bitfield_default },
+	 { "WPR_RESET_COR_EN", 3, 3, &umr_bitfield_default },
+	 { "WPR_RESET_REG_EN", 4, 4, &umr_bitfield_default },
+	 { "WPR_RESET_STY_EN", 5, 5, &umr_bitfield_default },
+	 { "WPR_RESET_PHY_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP0[] = {
+	 { "RX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP1[] = {
+	 { "RX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP2[] = {
+	 { "RX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP3[] = {
+	 { "RX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP0[] = {
+	 { "TX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP1[] = {
+	 { "TX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP2[] = {
+	 { "TX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP3[] = {
+	 { "TX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_I2C_REG_ADDR_EXPAND[] = {
+	 { "I2C_REG_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_I2C_REG_DATA[] = {
+	 { "I2C_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CFG_CNTL[] = {
+	 { "CFG_EN_DEC_TO_HIDDEN_REG", 0, 0, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG", 1, 1, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_PM_CNTL[] = {
+	 { "LC_L1_POWER_GATING_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_CNTL[] = {
+	 { "P_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "P_SYMALIGN_MODE", 1, 1, &umr_bitfield_default },
+	 { "P_SYMALIGN_HW_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "P_ELASTDESKEW_HW_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "P_IGNORE_CRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "P_IGNORE_LEN_ERR", 5, 5, &umr_bitfield_default },
+	 { "P_IGNORE_EDB_ERR", 6, 6, &umr_bitfield_default },
+	 { "P_IGNORE_IDL_ERR", 7, 7, &umr_bitfield_default },
+	 { "P_IGNORE_TOK_ERR", 8, 8, &umr_bitfield_default },
+	 { "P_BLK_LOCK_MODE", 12, 12, &umr_bitfield_default },
+	 { "P_ALWAYS_USE_FAST_TXCLK", 13, 13, &umr_bitfield_default },
+	 { "P_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "DLP_IGNORE_IN_L1_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_BUF_STATUS[] = {
+	 { "P_OVERFLOW_ERR", 0, 15, &umr_bitfield_default },
+	 { "P_UNDERFLOW_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_DECODER_STATUS[] = {
+	 { "P_DECODE_ERR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_MISC_STATUS[] = {
+	 { "P_DESKEW_ERR", 0, 7, &umr_bitfield_default },
+	 { "P_SYMUNLOCK_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_RCV_L0S_FTS_DET[] = {
+	 { "P_RCV_L0S_FTS_DET_MIN", 0, 7, &umr_bitfield_default },
+	 { "P_RCV_L0S_FTS_DET_MAX", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LTR_CNTL[] = {
+	 { "LTR_PRIV_S_SHORT_VALUE", 0, 2, &umr_bitfield_default },
+	 { "LTR_PRIV_S_LONG_VALUE", 3, 5, &umr_bitfield_default },
+	 { "LTR_PRIV_S_REQUIREMENT", 6, 6, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_SHORT_VALUE", 7, 9, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_LONG_VALUE", 10, 12, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_REQUIREMENT", 13, 13, &umr_bitfield_default },
+	 { "LTR_PRIV_MSG_DIS_IN_PM_NON_D0", 14, 14, &umr_bitfield_default },
+	 { "LTR_PRIV_RST_LTR_IN_DL_DOWN", 15, 15, &umr_bitfield_default },
+	 { "TX_CHK_FC_FOR_L1", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_OBFF_CNTL[] = {
+	 { "TX_OBFF_PRIV_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_SIMPLE_MODE_EN", 1, 1, &umr_bitfield_default },
+	 { "TX_OBFF_HOSTMEM_TO_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "TX_OBFF_SLVCPL_TO_ACTIVE", 3, 3, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_MAX_PULSE_WIDTH", 4, 7, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH", 8, 11, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_SAMPLING_PERIOD", 12, 15, &umr_bitfield_default },
+	 { "TX_OBFF_INTR_TO_ACTIVE", 16, 16, &umr_bitfield_default },
+	 { "TX_OBFF_ERR_TO_ACTIVE", 17, 17, &umr_bitfield_default },
+	 { "TX_OBFF_ANY_MSG_TO_ACTIVE", 18, 18, &umr_bitfield_default },
+	 { "TX_OBFF_ACCEPT_IN_NOND0", 19, 19, &umr_bitfield_default },
+	 { "TX_OBFF_PENDING_REQ_TO_ACTIVE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_IDLE_STATUS[] = {
+	 { "PCIE_ALL_IDLE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "TX_TXDL_IDLE_STATUS", 1, 1, &umr_bitfield_default },
+	 { "TX_RBUF_IDLE_STATUS", 2, 2, &umr_bitfield_default },
+	 { "TX_RCVD_FC_CREDITS_IDLE", 3, 3, &umr_bitfield_default },
+	 { "TX_RPL_CREDITS_IDLE", 4, 4, &umr_bitfield_default },
+	 { "TX_PBUF_IDLE", 5, 5, &umr_bitfield_default },
+	 { "TX_NPBUF_IDLE", 6, 6, &umr_bitfield_default },
+	 { "TX_CPLBUF_IDLE", 7, 7, &umr_bitfield_default },
+	 { "TX_MSGBUF_IDLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT_CNTL[] = {
+	 { "GLOBAL_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GLOBAL_SHADOW_WR", 1, 1, &umr_bitfield_default },
+	 { "GLOBAL_COUNT_RESET", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_TXCLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_TXCLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_TXCLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_MST_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_MST_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_MST_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_MST_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_MST_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_MST_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_S_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_S_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_S_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_NS_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[] = {
+	 { "PERF0_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[] = {
+	 { "PERF1_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_TXCLK2[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_TXCLK2[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_TXCLK2[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F0[] = {
+	 { "STRAP_F0_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F0_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F0_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F0_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F0_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F0_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F0_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F0_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F0_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F0_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F0_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F0_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F0_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F0_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+	 { "STRAP_F0_MC_EN", 17, 17, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_EN", 18, 18, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_64BIT_EN", 19, 19, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_ROUTING_EN", 20, 20, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_MULTI_CAP", 21, 23, &umr_bitfield_default },
+	 { "STRAP_F0_VFn_MSI_MULTI_CAP", 24, 26, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_PERVECTOR_MASK_CAP", 27, 27, &umr_bitfield_default },
+	 { "STRAP_F0_NO_RO_ENABLED_P2P_PASSING", 28, 28, &umr_bitfield_default },
+	 { "STRAP_F0_ARI_EN", 29, 29, &umr_bitfield_default },
+	 { "STRAP_F0_SRIOV_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F1[] = {
+	 { "STRAP_F1_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F1_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F1_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F1_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F1_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F1_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F1_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F1_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F1_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F1_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F1_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F1_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F1_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F1_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F1_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F1_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+	 { "STRAP_F1_ATOMIC_EN", 18, 18, &umr_bitfield_default },
+	 { "STRAP_F1_ATOMIC_64BIT_EN", 19, 19, &umr_bitfield_default },
+	 { "STRAP_F1_ATOMIC_ROUTING_EN", 20, 20, &umr_bitfield_default },
+	 { "STRAP_F1_MSI_MULTI_CAP", 21, 23, &umr_bitfield_default },
+	 { "STRAP_F1_MSI_PERVECTOR_MASK_CAP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F2[] = {
+	 { "STRAP_F2_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F2_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F2_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F2_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F2_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F2_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F2_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F2_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F2_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F2_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F2_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F2_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F2_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F2_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F2_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F2_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+	 { "STRAP_F2_ATOMIC_EN", 18, 18, &umr_bitfield_default },
+	 { "STRAP_F2_ATOMIC_64BIT_EN", 19, 19, &umr_bitfield_default },
+	 { "STRAP_F2_ATOMIC_ROUTING_EN", 20, 20, &umr_bitfield_default },
+	 { "STRAP_F2_MSI_MULTI_CAP", 21, 23, &umr_bitfield_default },
+	 { "STRAP_F2_MSI_PERVECTOR_MASK_CAP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_MSIX[] = {
+	 { "STRAP_F0_MSIX_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F0_MSIX_TABLE_BIR", 1, 3, &umr_bitfield_default },
+	 { "STRAP_F0_MSIX_TABLE_OFFSET", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_MISC[] = {
+	 { "STRAP_TL_ALT_BUF_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_MAX_PASID_WIDTH", 8, 12, &umr_bitfield_default },
+	 { "STRAP_PASID_EXE_PERMISSION_SUPPORTED", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PASID_PRIV_MODE_SUPPORTED", 14, 14, &umr_bitfield_default },
+	 { "STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED", 15, 15, &umr_bitfield_default },
+	 { "STRAP_CLK_PM_EN", 24, 24, &umr_bitfield_default },
+	 { "STRAP_ECN1P1_EN", 25, 25, &umr_bitfield_default },
+	 { "STRAP_EXT_VC_COUNT", 26, 26, &umr_bitfield_default },
+	 { "STRAP_REVERSE_ALL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_MST_ADR64_EN", 29, 29, &umr_bitfield_default },
+	 { "STRAP_FLR_EN", 30, 30, &umr_bitfield_default },
+	 { "STRAP_INTERNAL_ERR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_MISC2[] = {
+	 { "STRAP_GEN2_COMPLIANCE", 1, 1, &umr_bitfield_default },
+	 { "STRAP_MSTCPL_TIMEOUT_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_GEN3_COMPLIANCE", 3, 3, &umr_bitfield_default },
+	 { "STRAP_TPH_SUPPORTED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_PI[] = {
+	 { "STRAP_QUICKSIM_START", 0, 0, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_PATTERN", 28, 28, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_MODE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_I2C_BD[] = {
+	 { "STRAP_BIF_I2C_SLV_ADR", 0, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_DBG_I2C_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_CLR[] = {
+	 { "PRBS_CLR", 0, 15, &umr_bitfield_default },
+	 { "PRBS_CHECKER_DEBUG_BUS_SELECT", 16, 19, &umr_bitfield_default },
+	 { "PRBS_POLARITY_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_STATUS1[] = {
+	 { "PRBS_ERRSTAT", 0, 15, &umr_bitfield_default },
+	 { "PRBS_LOCKED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_STATUS2[] = {
+	 { "PRBS_BITCNT_DONE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_FREERUN[] = {
+	 { "PRBS_FREERUN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_MISC[] = {
+	 { "PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "PRBS_TEST_MODE", 1, 3, &umr_bitfield_default },
+	 { "PRBS_USER_PATTERN_TOGGLE", 4, 4, &umr_bitfield_default },
+	 { "PRBS_8BIT_SEL", 5, 5, &umr_bitfield_default },
+	 { "PRBS_COMMA_NUM", 6, 7, &umr_bitfield_default },
+	 { "PRBS_LOCK_CNT", 8, 12, &umr_bitfield_default },
+	 { "PRBS_DATA_RATE", 14, 15, &umr_bitfield_default },
+	 { "PRBS_CHK_ERR_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_USER_PATTERN[] = {
+	 { "PRBS_USER_PATTERN", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_LO_BITCNT[] = {
+	 { "PRBS_LO_BITCNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_HI_BITCNT[] = {
+	 { "PRBS_HI_BITCNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_0[] = {
+	 { "PRBS_ERRCNT_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_1[] = {
+	 { "PRBS_ERRCNT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_2[] = {
+	 { "PRBS_ERRCNT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_3[] = {
+	 { "PRBS_ERRCNT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_4[] = {
+	 { "PRBS_ERRCNT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_5[] = {
+	 { "PRBS_ERRCNT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_6[] = {
+	 { "PRBS_ERRCNT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_7[] = {
+	 { "PRBS_ERRCNT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_8[] = {
+	 { "PRBS_ERRCNT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_9[] = {
+	 { "PRBS_ERRCNT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_10[] = {
+	 { "PRBS_ERRCNT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_11[] = {
+	 { "PRBS_ERRCNT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_12[] = {
+	 { "PRBS_ERRCNT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_13[] = {
+	 { "PRBS_ERRCNT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_14[] = {
+	 { "PRBS_ERRCNT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_15[] = {
+	 { "PRBS_ERRCNT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_CAP[] = {
+	 { "TRANS_LAT_UNIT", 8, 9, &umr_bitfield_default },
+	 { "PWR_ALLOC_SCALE", 12, 13, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_0", 16, 23, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_LATENCY_INDICATOR[] = {
+	 { "TRANS_LAT_INDICATOR_BITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_CNTL[] = {
+	 { "SUBSTATE_STATUS", 0, 4, &umr_bitfield_default },
+	 { "DPA_COMPLIANCE_MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSWRST_COMMAND_1[] = {
+	 { "SWITCHCLK", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1", 5, 5, &umr_bitfield_default },
+	 { "RESETLC", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1", 25, 25, &umr_bitfield_default },
+	 { "TOGGLESTRAP", 28, 28, &umr_bitfield_default },
+	 { "CMDCFGEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_CONTROL[] = {
+	 { "LoopbackSelect", 1, 4, &umr_bitfield_default },
+	 { "PRBSPCIeLbSelect", 5, 5, &umr_bitfield_default },
+	 { "LoopbackHalfRate", 6, 7, &umr_bitfield_default },
+	 { "LoopbackFifoPtr", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PCIETXMUX0[] = {
+	 { "TXLANE0", 0, 7, &umr_bitfield_default },
+	 { "TXLANE1", 8, 15, &umr_bitfield_default },
+	 { "TXLANE2", 16, 23, &umr_bitfield_default },
+	 { "TXLANE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PCIETXMUX1[] = {
+	 { "TXLANE4", 0, 7, &umr_bitfield_default },
+	 { "TXLANE5", 8, 15, &umr_bitfield_default },
+	 { "TXLANE6", 16, 23, &umr_bitfield_default },
+	 { "TXLANE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PCIETXMUX2[] = {
+	 { "TXLANE8", 0, 7, &umr_bitfield_default },
+	 { "TXLANE9", 8, 15, &umr_bitfield_default },
+	 { "TXLANE10", 16, 23, &umr_bitfield_default },
+	 { "TXLANE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PCIETXMUX3[] = {
+	 { "TXLANE12", 0, 7, &umr_bitfield_default },
+	 { "TXLANE13", 8, 15, &umr_bitfield_default },
+	 { "TXLANE14", 16, 23, &umr_bitfield_default },
+	 { "TXLANE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PCIERXMUX0[] = {
+	 { "RXLANE0", 0, 7, &umr_bitfield_default },
+	 { "RXLANE1", 8, 15, &umr_bitfield_default },
+	 { "RXLANE2", 16, 23, &umr_bitfield_default },
+	 { "RXLANE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PCIERXMUX1[] = {
+	 { "RXLANE4", 0, 7, &umr_bitfield_default },
+	 { "RXLANE5", 8, 15, &umr_bitfield_default },
+	 { "RXLANE6", 16, 23, &umr_bitfield_default },
+	 { "RXLANE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PCIERXMUX2[] = {
+	 { "RXLANE8", 0, 7, &umr_bitfield_default },
+	 { "RXLANE9", 8, 15, &umr_bitfield_default },
+	 { "RXLANE10", 16, 23, &umr_bitfield_default },
+	 { "RXLANE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PCIERXMUX3[] = {
+	 { "RXLANE12", 0, 7, &umr_bitfield_default },
+	 { "RXLANE13", 8, 15, &umr_bitfield_default },
+	 { "RXLANE14", 16, 23, &umr_bitfield_default },
+	 { "RXLANE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_LANEENABLE[] = {
+	 { "LANE_enable", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_PRBSCONTROL[] = {
+	 { "PRBSPCIeSelect", 0, 15, &umr_bitfield_default },
+	 { "LMLaneDegrade0", 28, 28, &umr_bitfield_default },
+	 { "LMLaneDegrade1", 29, 29, &umr_bitfield_default },
+	 { "LMLaneDegrade2", 30, 30, &umr_bitfield_default },
+	 { "LMLaneDegrade3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_POWERCONTROL[] = {
+	 { "LMTxPhyCmd0", 0, 2, &umr_bitfield_default },
+	 { "LMRxPhyCmd0", 3, 5, &umr_bitfield_default },
+	 { "LMLinkSpeed0", 6, 7, &umr_bitfield_default },
+	 { "LMTxPhyCmd1", 8, 10, &umr_bitfield_default },
+	 { "LMRxPhyCmd1", 11, 13, &umr_bitfield_default },
+	 { "LMLinkSpeed1", 14, 15, &umr_bitfield_default },
+	 { "LMTxPhyCmd2", 16, 18, &umr_bitfield_default },
+	 { "LMRxPhyCmd2", 19, 21, &umr_bitfield_default },
+	 { "LMLinkSpeed2", 22, 23, &umr_bitfield_default },
+	 { "LMTxPhyCmd3", 24, 26, &umr_bitfield_default },
+	 { "LMRxPhyCmd3", 27, 29, &umr_bitfield_default },
+	 { "LMLinkSpeed3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_POWERCONTROL1[] = {
+	 { "LMTxEn0", 0, 0, &umr_bitfield_default },
+	 { "LMTxClkEn0", 1, 1, &umr_bitfield_default },
+	 { "LMTxMargin0", 2, 4, &umr_bitfield_default },
+	 { "LMSkipBit0", 5, 5, &umr_bitfield_default },
+	 { "LMLaneUnused0", 6, 6, &umr_bitfield_default },
+	 { "LMTxMarginEn0", 7, 7, &umr_bitfield_default },
+	 { "LMDeemph0", 8, 8, &umr_bitfield_default },
+	 { "LMTxEn1", 9, 9, &umr_bitfield_default },
+	 { "LMTxClkEn1", 10, 10, &umr_bitfield_default },
+	 { "LMTxMargin1", 11, 13, &umr_bitfield_default },
+	 { "LMSkipBit1", 14, 14, &umr_bitfield_default },
+	 { "LMLaneUnused1", 15, 15, &umr_bitfield_default },
+	 { "LMTxMarginEn1", 16, 16, &umr_bitfield_default },
+	 { "LMDeemph1", 17, 17, &umr_bitfield_default },
+	 { "LMTxEn2", 18, 18, &umr_bitfield_default },
+	 { "LMTxClkEn2", 19, 19, &umr_bitfield_default },
+	 { "LMTxMargin2", 20, 22, &umr_bitfield_default },
+	 { "LMSkipBit2", 23, 23, &umr_bitfield_default },
+	 { "LMLaneUnused2", 24, 24, &umr_bitfield_default },
+	 { "LMTxMarginEn2", 25, 25, &umr_bitfield_default },
+	 { "LMDeemph2", 26, 26, &umr_bitfield_default },
+	 { "TxCoeffID0", 27, 28, &umr_bitfield_default },
+	 { "TxCoeffID1", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_POWERCONTROL2[] = {
+	 { "LMTxEn3", 0, 0, &umr_bitfield_default },
+	 { "LMTxClkEn3", 1, 1, &umr_bitfield_default },
+	 { "LMTxMargin3", 2, 4, &umr_bitfield_default },
+	 { "LMSkipBit3", 5, 5, &umr_bitfield_default },
+	 { "LMLaneUnused3", 6, 6, &umr_bitfield_default },
+	 { "LMTxMarginEn3", 7, 7, &umr_bitfield_default },
+	 { "LMDeemph3", 8, 8, &umr_bitfield_default },
+	 { "TxCoeffID2", 9, 10, &umr_bitfield_default },
+	 { "TxCoeffID3", 11, 12, &umr_bitfield_default },
+	 { "TxCoeff0", 13, 18, &umr_bitfield_default },
+	 { "TxCoeff1", 19, 24, &umr_bitfield_default },
+	 { "TxCoeff2", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_POWERCONTROL3[] = {
+	 { "TxCoeff3", 0, 5, &umr_bitfield_default },
+	 { "RxEqCtl0", 6, 11, &umr_bitfield_default },
+	 { "RxEqCtl1", 12, 17, &umr_bitfield_default },
+	 { "RxEqCtl2", 18, 23, &umr_bitfield_default },
+	 { "RxEqCtl3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLM_POWERCONTROL4[] = {
+	 { "LinkNum0", 0, 2, &umr_bitfield_default },
+	 { "LinkNum1", 3, 5, &umr_bitfield_default },
+	 { "LinkNum2", 6, 8, &umr_bitfield_default },
+	 { "LinkNum3", 9, 11, &umr_bitfield_default },
+	 { "LaneNum0", 12, 15, &umr_bitfield_default },
+	 { "LaneNum1", 16, 19, &umr_bitfield_default },
+	 { "LaneNum2", 20, 23, &umr_bitfield_default },
+	 { "LaneNum3", 24, 27, &umr_bitfield_default },
+	 { "SpcMode0", 28, 28, &umr_bitfield_default },
+	 { "SpcMode1", 29, 29, &umr_bitfield_default },
+	 { "SpcMode2", 30, 30, &umr_bitfield_default },
+	 { "SpcMode3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_CNTL[] = {
+	 { "CP_RB0_WPTR", 0, 0, &umr_bitfield_default },
+	 { "CP_RB1_WPTR", 1, 1, &umr_bitfield_default },
+	 { "CP_RB2_WPTR", 2, 2, &umr_bitfield_default },
+	 { "UVD_RBC_RB_WPTR", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR", 5, 5, &umr_bitfield_default },
+	 { "CP_DMA_ME_COMMAND", 6, 6, &umr_bitfield_default },
+	 { "CP_DMA_PFP_COMMAND", 7, 7, &umr_bitfield_default },
+	 { "SAM_SAB_RBI_WPTR", 8, 8, &umr_bitfield_default },
+	 { "SAM_SAB_RBO_WPTR", 9, 9, &umr_bitfield_default },
+	 { "VCE_OUT_RB_WPTR", 10, 10, &umr_bitfield_default },
+	 { "VCE_RB_WPTR2", 11, 11, &umr_bitfield_default },
+	 { "VCE_RB_WPTR", 12, 12, &umr_bitfield_default },
+	 { "HOST_DOORBELL", 13, 13, &umr_bitfield_default },
+	 { "SELFRING_DOORBELL", 14, 14, &umr_bitfield_default },
+	 { "CP_DMA_PIO_COMMAND", 15, 15, &umr_bitfield_default },
+	 { "DISPLAY", 16, 16, &umr_bitfield_default },
+	 { "SDMA2_GFX_RB_WPTR", 17, 17, &umr_bitfield_default },
+	 { "SDMA3_GFX_RB_WPTR", 18, 18, &umr_bitfield_default },
+	 { "IGNORE_MC_DISABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_0[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_1[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_2[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_3[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_3[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_4[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_4[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_5[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_5[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_6[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_6[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_7[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_7[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_REQ[] = {
+	 { "FLUSH_REQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_GARLIC_FLUSH_REQ[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+	 { "SDMA2", 12, 12, &umr_bitfield_default },
+	 { "SDMA3", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_GARLIC_FLUSH_DONE[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+	 { "SDMA2", 12, 12, &umr_bitfield_default },
+	 { "SDMA3", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPU_IDLE_LATENCY[] = {
+	 { "GPU_IDLE_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MMIO_MAP_RANGE0[] = {
+	 { "MMIO_MAP_RANGE0_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE0_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MMIO_MAP_RANGE1[] = {
+	 { "MMIO_MAP_RANGE1_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE1_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MMIO_MAP_RANGE2[] = {
+	 { "MMIO_MAP_RANGE2_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE2_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MMIO_MAP_RANGE3[] = {
+	 { "MMIO_MAP_RANGE3_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE3_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MMIO_MAP_RANGE4[] = {
+	 { "MMIO_MAP_RANGE4_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE4_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MMIO_MAP_RANGE5[] = {
+	 { "MMIO_MAP_RANGE5_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE5_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_GPU_IDLE_LATENCY[] = {
+	 { "GPU_IDLE_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_MMIO_MAP_RANGE0[] = {
+	 { "MMIO_MAP_RANGE0_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE0_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_MMIO_MAP_RANGE1[] = {
+	 { "MMIO_MAP_RANGE1_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE1_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_MMIO_MAP_RANGE2[] = {
+	 { "MMIO_MAP_RANGE2_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE2_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_MMIO_MAP_RANGE3[] = {
+	 { "MMIO_MAP_RANGE3_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE3_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_MMIO_MAP_RANGE4[] = {
+	 { "MMIO_MAP_RANGE4_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE4_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_MMIO_MAP_RANGE5[] = {
+	 { "MMIO_MAP_RANGE5_LOWER", 0, 15, &umr_bitfield_default },
+	 { "MMIO_MAP_RANGE5_UPPER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREMAP_HDP_MEM_FLUSH_CNTL[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREMAP_HDP_REG_FLUSH_CNTL[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX0_LOWER[] = {
+	 { "VDDGFX_GFX0_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX0_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX0_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX0_UPPER[] = {
+	 { "VDDGFX_GFX0_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX1_LOWER[] = {
+	 { "VDDGFX_GFX1_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX1_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX1_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX1_UPPER[] = {
+	 { "VDDGFX_GFX1_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX2_LOWER[] = {
+	 { "VDDGFX_GFX2_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX2_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX2_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX2_UPPER[] = {
+	 { "VDDGFX_GFX2_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX3_LOWER[] = {
+	 { "VDDGFX_GFX3_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX3_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX3_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX3_UPPER[] = {
+	 { "VDDGFX_GFX3_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX4_LOWER[] = {
+	 { "VDDGFX_GFX4_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX4_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX4_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX4_UPPER[] = {
+	 { "VDDGFX_GFX4_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX5_LOWER[] = {
+	 { "VDDGFX_GFX5_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX5_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX5_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX5_UPPER[] = {
+	 { "VDDGFX_GFX5_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV1_LOWER[] = {
+	 { "VDDGFX_RSV1_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV1_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV1_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV1_UPPER[] = {
+	 { "VDDGFX_RSV1_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV2_LOWER[] = {
+	 { "VDDGFX_RSV2_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV2_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV2_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV2_UPPER[] = {
+	 { "VDDGFX_RSV2_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV3_LOWER[] = {
+	 { "VDDGFX_RSV3_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV3_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV3_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV3_UPPER[] = {
+	 { "VDDGFX_RSV3_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV4_LOWER[] = {
+	 { "VDDGFX_RSV4_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV4_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV4_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV4_UPPER[] = {
+	 { "VDDGFX_RSV4_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_FB_CMP[] = {
+	 { "VDDGFX_FB_HDP_CMP_EN", 0, 0, &umr_bitfield_default },
+	 { "VDDGFX_FB_HDP_STALL_EN", 1, 1, &umr_bitfield_default },
+	 { "VDDGFX_FB_XDMA_CMP_EN", 2, 2, &umr_bitfield_default },
+	 { "VDDGFX_FB_XDMA_STALL_EN", 3, 3, &umr_bitfield_default },
+	 { "VDDGFX_FB_VGA_CMP_EN", 4, 4, &umr_bitfield_default },
+	 { "VDDGFX_FB_VGA_STALL_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SMU_INDEX[] = {
+	 { "BIF_SMU_INDEX", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SMU_DATA[] = {
+	 { "BIF_SMU_DATA", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_SOFTRST_CNTL[] = {
+	 { "REG_RST_rstTimer", 0, 15, &umr_bitfield_default },
+	 { "REG_RST_softRstPropEn", 30, 30, &umr_bitfield_default },
+	 { "SoftRstReg", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[] = {
+	 { "CLIENT0_RFE_RFEWDBIF_rst", 0, 0, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWDBIF_rst", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MASTER_SOFTRST_TRIGGER[] = {
+	 { "BU_rst", 0, 0, &umr_bitfield_default },
+	 { "RWREG_RFEWDBIF_rst", 1, 1, &umr_bitfield_default },
+	 { "SMBUS_rst", 2, 2, &umr_bitfield_default },
+	 { "BX_rst", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PWDN_COMMAND[] = {
+	 { "REG_BU_pw_cmd", 0, 0, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWDBIF_pw_cmd", 1, 1, &umr_bitfield_default },
+	 { "REG_SMBUS_pw_cmd", 2, 2, &umr_bitfield_default },
+	 { "REG_BX_pw_cmd", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PWDN_STATUS[] = {
+	 { "BU_REG_pw_status", 0, 0, &umr_bitfield_default },
+	 { "RWREG_RFEWDBIF_REG_pw_status", 1, 1, &umr_bitfield_default },
+	 { "SMBUS_REG_pw_status", 2, 2, &umr_bitfield_default },
+	 { "BX_REG_pw_status", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_BU_CMDSTATUS[] = {
+	 { "REG_BU_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_BU_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_BU_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "BU_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS[] = {
+	 { "REG_RWREG_RFEWDBIF_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWDBIF_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWDBIF_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "RWREG_RFEWDBIF_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_SMBUS_CMDSTATUS[] = {
+	 { "REG_SMBUS_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_SMBUS_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_SMBUS_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "SMBUS_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_BX_CMDSTATUS[] = {
+	 { "REG_BX_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_BX_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_BX_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "BX_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_TMOUT_STATUS[] = {
+	 { "MstTmoutStatus", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MMCFG_CNTL[] = {
+	 { "CLIENT0_RFE_RFEWDBIF_MM_WR_TO_CFG_EN", 0, 0, &umr_bitfield_default },
+	 { "CLIENT0_RFE_RFEWDBIF_MM_CFG_FUNC_SEL", 1, 3, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWDBIF_MM_WR_TO_CFG_EN", 4, 4, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWDBIF_MM_CFG_FUNC_SEL", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_SMPLCNTL[] = {
+	 { "FORCE_DONE", 0, 0, &umr_bitfield_default },
+	 { "RxPDNB", 1, 1, &umr_bitfield_default },
+	 { "TxPDNB_pd", 2, 2, &umr_bitfield_default },
+	 { "TxPDNB_pu", 3, 3, &umr_bitfield_default },
+	 { "SAMPLE_PERIOD", 8, 12, &umr_bitfield_default },
+	 { "EXTEND_SAMPLES", 13, 13, &umr_bitfield_default },
+	 { "FORCE_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SETUP_TIME", 15, 19, &umr_bitfield_default },
+	 { "LOWER_SAMPLE_THRESH", 20, 25, &umr_bitfield_default },
+	 { "UPPER_SAMPLE_THRESH", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_RXCNTL[] = {
+	 { "RX_ADJUST", 0, 2, &umr_bitfield_default },
+	 { "RX_BIAS_HIGH", 3, 3, &umr_bitfield_default },
+	 { "CONT_AFTER_RX_DECT", 4, 4, &umr_bitfield_default },
+	 { "SUSPEND", 6, 6, &umr_bitfield_default },
+	 { "FORCE_RST", 7, 7, &umr_bitfield_default },
+	 { "LOWER_RX_ADJ_THRESH", 8, 11, &umr_bitfield_default },
+	 { "LOWER_RX_ADJ", 12, 12, &umr_bitfield_default },
+	 { "UPPER_RX_ADJ_THRESH", 13, 16, &umr_bitfield_default },
+	 { "UPPER_RX_ADJ", 17, 17, &umr_bitfield_default },
+	 { "RX_IMP_LOCKED", 18, 18, &umr_bitfield_default },
+	 { "RX_IMP_READBACK_SEL", 19, 19, &umr_bitfield_default },
+	 { "RX_IMP_READBACK", 20, 23, &umr_bitfield_default },
+	 { "RX_CMP_AMBIG", 28, 28, &umr_bitfield_default },
+	 { "CAL_DONE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_TXCNTL_pd[] = {
+	 { "TX_ADJUST_pd", 0, 2, &umr_bitfield_default },
+	 { "TX_BIAS_HIGH_pd", 3, 3, &umr_bitfield_default },
+	 { "LOWER_TX_ADJ_THRESH_pd", 8, 11, &umr_bitfield_default },
+	 { "LOWER_TX_ADJ_pd", 12, 12, &umr_bitfield_default },
+	 { "UPPER_TX_ADJ_THRESH_pd", 13, 16, &umr_bitfield_default },
+	 { "UPPER_TX_ADJ_pd", 17, 17, &umr_bitfield_default },
+	 { "TX_IMP_LOCKED_pd", 18, 18, &umr_bitfield_default },
+	 { "TX_IMP_READBACK_SEL_pd", 19, 19, &umr_bitfield_default },
+	 { "TX_IMP_READBACK_pd", 20, 23, &umr_bitfield_default },
+	 { "TX_CMP_AMBIG_pd", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_TXCNTL_pu[] = {
+	 { "TX_ADJUST_pu", 0, 2, &umr_bitfield_default },
+	 { "TX_BIAS_HIGH_pu", 3, 3, &umr_bitfield_default },
+	 { "LOWER_TX_ADJ_THRESH_pu", 8, 11, &umr_bitfield_default },
+	 { "LOWER_TX_ADJ_pu", 12, 12, &umr_bitfield_default },
+	 { "UPPER_TX_ADJ_THRESH_pu", 13, 16, &umr_bitfield_default },
+	 { "UPPER_TX_ADJ_pu", 17, 17, &umr_bitfield_default },
+	 { "TX_IMP_LOCKED_pu", 18, 18, &umr_bitfield_default },
+	 { "TX_IMP_READBACK_SEL_pu", 19, 19, &umr_bitfield_default },
+	 { "TX_IMP_READBACK_pu", 20, 23, &umr_bitfield_default },
+	 { "TX_CMP_AMBIG_pu", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD[] = {
+	 { "UPDATE_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_CC_RFE_IMP_OVERRIDECNTL[] = {
+	 { "STRAP_PLL_RX_IMPVAL", 1, 4, &umr_bitfield_default },
+	 { "STRAP_PLL_RX_IMPVAL_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_PLL_TX_IMPVAL_PD", 6, 9, &umr_bitfield_default },
+	 { "STRAP_PLL_TX_IMPVAL_EN_PD", 10, 10, &umr_bitfield_default },
+	 { "STRAP_PLL_TX_IMPVAL_PU", 11, 14, &umr_bitfield_default },
+	 { "STRAP_PLL_TX_IMPVAL_EN_PU", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_IMP_DBG_ANALOG_EN", 16, 16, &umr_bitfield_default },
+	 { "STRAP_PLL_IMP_IGNORE_QUICKSIM", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_IMPRST_CNTL[] = {
+	 { "REG_RST_impEn", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_WARMRST_CNTL[] = {
+	 { "REG_RST_warmRstRfeEn", 0, 0, &umr_bitfield_default },
+	 { "REG_RST_warmRstImpEn", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_COMMAND_STATUS[] = {
+	 { "RECONFIGURE", 0, 0, &umr_bitfield_default },
+	 { "ATOMIC_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESET_COMPLETE", 16, 16, &umr_bitfield_default },
+	 { "WAIT_STATE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_GENERAL_CONTROL[] = {
+	 { "RECONFIGURE_EN", 0, 0, &umr_bitfield_default },
+	 { "ATOMIC_RESET_EN", 1, 1, &umr_bitfield_default },
+	 { "RESET_PERIOD", 2, 4, &umr_bitfield_default },
+	 { "WAIT_LINKUP", 8, 8, &umr_bitfield_default },
+	 { "FORCE_REGIDLE", 9, 9, &umr_bitfield_default },
+	 { "BLOCK_ON_IDLE", 10, 10, &umr_bitfield_default },
+	 { "CONFIG_XFER_MODE", 12, 12, &umr_bitfield_default },
+	 { "MUXSEL_XFER_MODE", 13, 13, &umr_bitfield_default },
+	 { "HLDTRAIN_XFER_MODE", 14, 14, &umr_bitfield_default },
+	 { "BYPASS_HOLD", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_PIF_HOLD", 17, 17, &umr_bitfield_default },
+	 { "EP_COMPLT_CHK_EN", 28, 28, &umr_bitfield_default },
+	 { "EP_COMPLT_WAIT_TMR", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_COMMAND_0[] = {
+	 { "BIF_STRAPREG_RESET", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESET", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESET", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESET", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESET", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESET", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESET", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESET", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_COMMAND_1[] = {
+	 { "SWITCHCLK", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1", 5, 5, &umr_bitfield_default },
+	 { "RESETLC", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1", 25, 25, &umr_bitfield_default },
+	 { "TOGGLESTRAP", 28, 28, &umr_bitfield_default },
+	 { "CMDCFGEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_CONTROL_0[] = {
+	 { "BIF_STRAPREG_RESETRCEN", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESETRCEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESETRCEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESETRCEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESETRCEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESETRCEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESETRCEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESETRCEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_CONTROL_1[] = {
+	 { "SWITCHCLK_RCEN", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG_RCEN", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX_RCEN", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS_RCEN", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0_RCEN", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1_RCEN", 5, 5, &umr_bitfield_default },
+	 { "RESETLC_RCEN", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0_RCEN", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1_RCEN", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR_RCEN", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR_RCEN", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM_RCEN", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0_RCEN", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1_RCEN", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0_RCEN", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1_RCEN", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0_RCEN", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1_RCEN", 25, 25, &umr_bitfield_default },
+	 { "STRAPVLD_RCEN", 28, 28, &umr_bitfield_default },
+	 { "CMDCFG_RCEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_CONTROL_2[] = {
+	 { "BIF_STRAPREG_RESETATEN", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESETATEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESETATEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESETATEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESETATEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESETATEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESETATEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESETATEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_CONTROL_3[] = {
+	 { "SWITCHCLK_ATEN", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG_ATEN", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX_ATEN", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS_ATEN", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0_ATEN", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1_ATEN", 5, 5, &umr_bitfield_default },
+	 { "RESETLC_ATEN", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0_ATEN", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1_ATEN", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR_ATEN", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR_ATEN", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM_ATEN", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0_ATEN", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1_ATEN", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0_ATEN", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1_ATEN", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0_ATEN", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1_ATEN", 25, 25, &umr_bitfield_default },
+	 { "STRAPVLD_ATEN", 28, 28, &umr_bitfield_default },
+	 { "CMDCFG_ATEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_CONTROL_4[] = {
+	 { "BIF_STRAPREG_WRRESETEN", 14, 14, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_WRRESETEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_WRRESETEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_WRRESETEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_WRRESETEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_WRRESETEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_WRRESETEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_WRRESETEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_CONTROL_5[] = {
+	 { "WRSWITCHCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "WRRESETPCFG_EN", 1, 1, &umr_bitfield_default },
+	 { "WRRESETLANEMUX_EN", 2, 2, &umr_bitfield_default },
+	 { "WRRESETWRAPREGS_EN", 3, 3, &umr_bitfield_default },
+	 { "WRRESETSRBM0_EN", 4, 4, &umr_bitfield_default },
+	 { "WRRESETSRBM1_EN", 5, 5, &umr_bitfield_default },
+	 { "WRRESETLC_EN", 6, 6, &umr_bitfield_default },
+	 { "WRSYNCIDLEPIF0_EN", 8, 8, &umr_bitfield_default },
+	 { "WRSYNCIDLEPIF1_EN", 9, 9, &umr_bitfield_default },
+	 { "WRRESETMNTR_EN", 13, 13, &umr_bitfield_default },
+	 { "WRRESETHLTR_EN", 14, 14, &umr_bitfield_default },
+	 { "WRRESETCPM_EN", 15, 15, &umr_bitfield_default },
+	 { "WRRESETPIF0_EN", 16, 16, &umr_bitfield_default },
+	 { "WRRESETPIF1_EN", 17, 17, &umr_bitfield_default },
+	 { "WRRESETIMPARB0_EN", 20, 20, &umr_bitfield_default },
+	 { "WRRESETIMPARB1_EN", 21, 21, &umr_bitfield_default },
+	 { "WRRESETPHY0_EN", 24, 24, &umr_bitfield_default },
+	 { "WRRESETPHY1_EN", 25, 25, &umr_bitfield_default },
+	 { "WRSTRAPVLD_EN", 28, 28, &umr_bitfield_default },
+	 { "WRCMDCFG_EN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_CONTROL_6[] = {
+	 { "WARMRESET_EN", 0, 0, &umr_bitfield_default },
+	 { "CONNECTWITHWRAPREGS_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_EP_COMMAND_0[] = {
+	 { "EP_CFG_RESET_ONLY", 0, 0, &umr_bitfield_default },
+	 { "EP_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "EP_DRV_RESET", 2, 2, &umr_bitfield_default },
+	 { "EP_HOT_RESET", 8, 8, &umr_bitfield_default },
+	 { "EP_LNKDWN_RESET", 9, 9, &umr_bitfield_default },
+	 { "EP_LNKDIS_RESET", 10, 10, &umr_bitfield_default },
+	 { "EP_FLR0_RESET", 16, 16, &umr_bitfield_default },
+	 { "EP_FLR1_RESET", 17, 17, &umr_bitfield_default },
+	 { "EP_FLR2_RESET", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSWRST_EP_CONTROL_0[] = {
+	 { "EP_CFG_RESET_ONLY_EN", 0, 0, &umr_bitfield_default },
+	 { "EP_SOFT_RESET_EN", 1, 1, &umr_bitfield_default },
+	 { "EP_DRV_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "EP_HOT_RESET_EN", 8, 8, &umr_bitfield_default },
+	 { "EP_LNKDWN_RESET_EN", 9, 9, &umr_bitfield_default },
+	 { "EP_LNKDIS_RESET_EN", 10, 10, &umr_bitfield_default },
+	 { "EP_FLR0_RESET_EN", 16, 16, &umr_bitfield_default },
+	 { "EP_FLR1_RESET_EN", 17, 17, &umr_bitfield_default },
+	 { "EP_FLR2_RESET_EN", 18, 18, &umr_bitfield_default },
+	 { "EP_CFG_WR_RESET_EN", 19, 19, &umr_bitfield_default },
+	 { "EP_FLR_DISABLE_CFG_RST", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPM_CONTROL[] = {
+	 { "LCLK_DYN_GATE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TXCLK_DYN_GATE_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "TXCLK_PIF_GATE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "TXCLK_GSKT_GATE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "TXCLK_LCNT_GATE_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "TXCLK_REGS_GATE_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "TXCLK_PRBS_GATE_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "REFCLK_REGS_GATE_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "LCLK_DYN_GATE_LATENCY", 9, 9, &umr_bitfield_default },
+	 { "TXCLK_DYN_GATE_LATENCY", 10, 10, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_LATENCY", 11, 11, &umr_bitfield_default },
+	 { "TXCLK_REGS_GATE_LATENCY", 12, 12, &umr_bitfield_default },
+	 { "REFCLK_REGS_GATE_LATENCY", 13, 13, &umr_bitfield_default },
+	 { "LCLK_GATE_TXCLK_FREE", 14, 14, &umr_bitfield_default },
+	 { "RCVR_DET_CLK_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_PLL_PDN", 16, 16, &umr_bitfield_default },
+	 { "FAST_TXCLK_LATENCY", 17, 19, &umr_bitfield_default },
+	 { "MASTER_PCIE_PLL_SELECT", 20, 20, &umr_bitfield_default },
+	 { "MASTER_PCIE_PLL_AUTO", 21, 21, &umr_bitfield_default },
+	 { "REFCLK_XSTCLK_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "REFCLK_XSTCLK_LATENCY", 23, 23, &umr_bitfield_default },
+	 { "SPARE_REGS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGSKT_CONTROL[] = {
+	 { "GSKT_TxFifoBypass", 0, 0, &umr_bitfield_default },
+	 { "GSKT_TxFifoDelay", 1, 1, &umr_bitfield_default },
+	 { "GSKT_TxFifoDelay2", 2, 2, &umr_bitfield_default },
+	 { "GSKT_SpareRegs", 3, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_XDMA_LO[] = {
+	 { "BIF_XDMA_LOWER_BOUND", 0, 28, &umr_bitfield_default },
+	 { "BIF_XDMA_APER_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_XDMA_HI[] = {
+	 { "BIF_XDMA_UPPER_BOUND", 0, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_FEATURES_CONTROL_MISC[] = {
+	 { "MST_BIF_REQ_EP_DIS", 0, 0, &umr_bitfield_default },
+	 { "SLV_BIF_CPL_EP_DIS", 1, 1, &umr_bitfield_default },
+	 { "BIF_SLV_REQ_EP_DIS", 2, 2, &umr_bitfield_default },
+	 { "BIF_MST_CPL_EP_DIS", 3, 3, &umr_bitfield_default },
+	 { "UR_PSN_PKT_REPORT_POISON_DIS", 4, 4, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS", 5, 5, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS", 6, 6, &umr_bitfield_default },
+	 { "PLL_SWITCH_IMPCTL_CAL_DONE_DIS", 7, 7, &umr_bitfield_default },
+	 { "IGNORE_BE_CHECK_GASKET_COMB_DIS", 8, 8, &umr_bitfield_default },
+	 { "MC_BIF_REQ_ID_ROUTING_DIS", 9, 9, &umr_bitfield_default },
+	 { "AZ_BIF_REQ_ID_ROUTING_DIS", 10, 10, &umr_bitfield_default },
+	 { "ATC_PRG_RESP_PASID_UR_EN", 11, 11, &umr_bitfield_default },
+	 { "BIF_RB_SET_OVERFLOW_EN", 12, 12, &umr_bitfield_default },
+	 { "ATOMIC_ERR_INT_DIS", 13, 13, &umr_bitfield_default },
+	 { "BME_HDL_NONVIR_EN", 15, 15, &umr_bitfield_default },
+	 { "INIT_PFFLR_CRS_RET_DIS", 16, 16, &umr_bitfield_default },
+	 { "FLR_MST_PEND_CHK_DIS", 17, 17, &umr_bitfield_default },
+	 { "FLR_SLV_PEND_CHK_DIS", 18, 18, &umr_bitfield_default },
+	 { "SOFT_PF_FLR_UR_CFG_EN", 19, 19, &umr_bitfield_default },
+	 { "FLR_OSTD_UR_DIS", 20, 20, &umr_bitfield_default },
+	 { "FLR_OSTD_HDL_DIS", 21, 21, &umr_bitfield_default },
+	 { "FLR_NEWREQ_HDL_DIS", 22, 22, &umr_bitfield_default },
+	 { "FLR_CRS_CFG_DIS", 23, 23, &umr_bitfield_default },
+	 { "DUMMY_TRANS_CPL_RET_DIS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_CNTL[] = {
+	 { "SELF_RING_DIS", 0, 0, &umr_bitfield_default },
+	 { "TRANS_CHECK_DIS", 1, 1, &umr_bitfield_default },
+	 { "UNTRANS_LBACK_EN", 2, 2, &umr_bitfield_default },
+	 { "NON_CONSECUTIVE_BE_ZERO_DIS", 3, 3, &umr_bitfield_default },
+	 { "DOORBELL_MONITOR_EN", 4, 4, &umr_bitfield_default },
+	 { "DOORBELL_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default },
+	 { "DOORBELL_INTERRUPT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DB_MNTR_INTGEN_DIS", 24, 24, &umr_bitfield_default },
+	 { "DB_MNTR_INTGEN_MODE_0", 25, 25, &umr_bitfield_default },
+	 { "DB_MNTR_INTGEN_MODE_1", 26, 26, &umr_bitfield_default },
+	 { "DB_MNTR_INTGEN_MODE_2", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SLVARB_MODE[] = {
+	 { "SLVARB_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_CLK_CTRL[] = {
+	 { "BIF_XSTCLK_READY", 0, 0, &umr_bitfield_default },
+	 { "BACO_XSTCLK_SWITCH_BYPASS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_INDEX[] = {
+	 { "MAILBOX_INDEX", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBF_ANA_ISO_CNTL[] = {
+	 { "BF_ANA_ISO_DIS_MASK", 0, 0, &umr_bitfield_default },
+	 { "BF_VDDC_ISO_DIS_MASK", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW0[] = {
+	 { "MSGBUF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW1[] = {
+	 { "MSGBUF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW2[] = {
+	 { "MSGBUF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_MSGBUF_TRN_DW3[] = {
+	 { "MSGBUF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW0[] = {
+	 { "MSGBUF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW1[] = {
+	 { "MSGBUF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW2[] = {
+	 { "MSGBUF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_MSGBUF_RCV_DW3[] = {
+	 { "MSGBUF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_CONTROL[] = {
+	 { "TRN_MSG_VALID", 0, 0, &umr_bitfield_default },
+	 { "TRN_MSG_ACK", 1, 1, &umr_bitfield_default },
+	 { "RCV_MSG_VALID", 8, 8, &umr_bitfield_default },
+	 { "RCV_MSG_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAILBOX_INT_CNTL[] = {
+	 { "VALID_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "ACK_INT_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VIRT_RESET_REQ[] = {
+	 { "VIRT_RESET_REQ_VF", 0, 15, &umr_bitfield_default },
+	 { "VIRT_RESET_REQ_SOFTPF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INIT_STATUS[] = {
+	 { "VM_INIT_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_RESET_NOTIFICATION[] = {
+	 { "RESET_NOTIFICATION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_VM_INIT_STATUS[] = {
+	 { "VM_INIT_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_GPUIOV_FB_TOTAL_FB_INFO[] = {
+	 { "TOTAL_FB_AVAILABLE", 0, 15, &umr_bitfield_default },
+	 { "TOTAL_FB_CONSUMED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBACO_CNTL_MISC[] = {
+	 { "BIF_ROM_REQ_DIS", 0, 0, &umr_bitfield_default },
+	 { "BIF_AZ_REQ_DIS", 1, 1, &umr_bitfield_default },
+	 { "BACO_LINK_RST_WIDTH_SEL", 2, 3, &umr_bitfield_default },
+	 { "BACO_REFCLK_SEL", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_DEBUG_LATCH[] = {
+	 { "BIF_BACO_LATCH_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_DEBUG[] = {
+	 { "BIF_BACO_SCANDUMP_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMEM_TYPE_CNTL[] = {
+	 { "BF_MEM_PHY_G5_G3", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBACO_CNTL[] = {
+	 { "BACO_EN", 0, 0, &umr_bitfield_default },
+	 { "BACO_BCLK_OFF", 1, 1, &umr_bitfield_default },
+	 { "BACO_ISO_DIS", 2, 2, &umr_bitfield_default },
+	 { "BACO_POWER_OFF", 3, 3, &umr_bitfield_default },
+	 { "BACO_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "BACO_HANG_PROTECTION_EN", 5, 5, &umr_bitfield_default },
+	 { "BACO_MODE", 6, 6, &umr_bitfield_default },
+	 { "BACO_ANA_ISO_DIS", 7, 7, &umr_bitfield_default },
+	 { "RCU_BIF_CONFIG_DONE", 8, 8, &umr_bitfield_default },
+	 { "PWRGOOD_BF", 9, 9, &umr_bitfield_default },
+	 { "PWRGOOD_GPIO", 10, 10, &umr_bitfield_default },
+	 { "PWRGOOD_MEM", 11, 11, &umr_bitfield_default },
+	 { "PWRGOOD_DVO", 12, 12, &umr_bitfield_default },
+	 { "PWRGOOD_IDSC", 13, 13, &umr_bitfield_default },
+	 { "BACO_POWER_OFF_DRAM", 16, 16, &umr_bitfield_default },
+	 { "BACO_BF_MEM_PHY_ISO_CNTRL", 17, 17, &umr_bitfield_default },
+	 { "BACO_BIF_SCLK_SWITCH", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEVFUNCNUM_LIST1[] = {
+	 { "DEVFUNC_ID4", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID5", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID6", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEVFUNCNUM_LIST0[] = {
+	 { "DEVFUNC_ID0", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID1", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID2", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SLV_TRANS_PENDING[] = {
+	 { "BIF_SLV_TRANS_PENDING", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MST_TRANS_PENDING[] = {
+	 { "BIF_MST_TRANS_PENDING", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDBG_SMB_BYPASS_SRBM_ACCESS[] = {
+	 { "DBG_SMB_BYPASS_SRBM_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER3_FB_OFFSET_LO[] = {
+	 { "PEER3_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER3_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER3_FB_OFFSET_HI[] = {
+	 { "PEER3_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER2_FB_OFFSET_LO[] = {
+	 { "PEER2_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER2_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER2_FB_OFFSET_HI[] = {
+	 { "PEER2_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER1_FB_OFFSET_LO[] = {
+	 { "PEER1_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER1_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER1_FB_OFFSET_HI[] = {
+	 { "PEER1_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER0_FB_OFFSET_LO[] = {
+	 { "PEER0_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER0_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER0_FB_OFFSET_HI[] = {
+	 { "PEER0_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMPCTL_RESET[] = {
+	 { "IMP_SW_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_BIF_VDDGFX_PWR_STATUS[] = {
+	 { "VDDGFX_GFX_PWR_OFF", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_GBLAPER1_LOWER[] = {
+	 { "DOORBELL_GBLAPER1_LOWER", 2, 11, &umr_bitfield_default },
+	 { "DOORBELL_GBLAPER1_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_GBLAPER1_UPPER[] = {
+	 { "DOORBELL_GBLAPER1_UPPER", 2, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_GBLAPER2_LOWER[] = {
+	 { "DOORBELL_GBLAPER2_LOWER", 2, 11, &umr_bitfield_default },
+	 { "DOORBELL_GBLAPER2_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_GBLAPER2_UPPER[] = {
+	 { "DOORBELL_GBLAPER2_UPPER", 2, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MM_INDACCESS_CNTL[] = {
+	 { "MM_INDACCESS_DIS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_HOLD_TRAINING_A[] = {
+	 { "HOLD_TRAINING_A", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_APER_EN[] = {
+	 { "BIF_DOORBELL_APER_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_RESERVED[] = {
+	 { "CONFIG_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_IOV_FUNC_IDENTIFIER[] = {
+	 { "FUNC_IDENTIFIER", 0, 0, &umr_bitfield_default },
+	 { "IOV_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBUS_CNTL[] = {
+	 { "BIOS_ROM_WRT_EN", 0, 0, &umr_bitfield_default },
+	 { "BIOS_ROM_DIS", 1, 1, &umr_bitfield_default },
+	 { "PMI_IO_DIS", 2, 2, &umr_bitfield_default },
+	 { "PMI_MEM_DIS", 3, 3, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 4, 4, &umr_bitfield_default },
+	 { "PMI_INT_DIS", 5, 5, &umr_bitfield_default },
+	 { "VGA_REG_COHERENCY_DIS", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_COHERENCY_DIS", 7, 7, &umr_bitfield_default },
+	 { "BIF_ERR_RTR_BKPRESSURE_EN", 8, 8, &umr_bitfield_default },
+	 { "SET_AZ_TC", 10, 12, &umr_bitfield_default },
+	 { "SET_MC_TC", 13, 15, &umr_bitfield_default },
+	 { "ZERO_BE_WR_EN", 16, 16, &umr_bitfield_default },
+	 { "ZERO_BE_RD_EN", 17, 17, &umr_bitfield_default },
+	 { "RD_STALL_IO_WR", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLNCNT_CONTROL[] = {
+	 { "CFG_LNC_WINDOW_EN0", 0, 0, &umr_bitfield_default },
+	 { "CFG_LNC_BW_CNT_EN1", 1, 1, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_CNT_EN2", 2, 2, &umr_bitfield_default },
+	 { "CFG_LNC_OVRD_EN3", 3, 3, &umr_bitfield_default },
+	 { "CFG_LNC_OVRD_VAL4", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCFG_LNC_WINDOW[] = {
+	 { "CFG_LNC_WINDOW0", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLNCNT_QUAN_THRD[] = {
+	 { "CFG_LNC_BW_QUAN_THRD0", 0, 2, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_QUAN_THRD4", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLNCNT_WEIGHT[] = {
+	 { "CFG_LNC_BW_WEIGHT0", 0, 15, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_WEIGHT16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLNC_TOTAL_WACC[] = {
+	 { "LNC_TOTAL_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLNC_BW_WACC[] = {
+	 { "LNC_BW_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLNC_CMN_WACC[] = {
+	 { "LNC_CMN_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_CNTL[] = {
+	 { "CFG_VGA_RAM_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_DIS", 1, 1, &umr_bitfield_default },
+	 { "GENMO_MONO_ADDRESS_B", 2, 2, &umr_bitfield_default },
+	 { "GRPH_ADRSEL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_MEMSIZE[] = {
+	 { "CONFIG_MEMSIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_F0_BASE[] = {
+	 { "F0_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_APER_SIZE[] = {
+	 { "APER_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_REG_APER_SIZE[] = {
+	 { "REG_APER_SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SCRATCH0[] = {
+	 { "BIF_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SCRATCH1[] = {
+	 { "BIF_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RLC_INTR_CNTL[] = {
+	 { "RLC_HVCMD_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "RLC_VM_IDLE_INTERRUPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BME_STATUS[] = {
+	 { "DMA_ON_BME_LOW", 0, 0, &umr_bitfield_default },
+	 { "CLEAR_DMA_ON_BME_LOW", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_ATOMIC_ERR_LOG[] = {
+	 { "UR_ATOMIC_OPCODE", 0, 0, &umr_bitfield_default },
+	 { "UR_ATOMIC_REQEN_LOW", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_UR_ATOMIC_OPCODE", 16, 16, &umr_bitfield_default },
+	 { "CLEAR_UR_ATOMIC_REQEN_LOW", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_CFGREGS_CNTL[] = {
+	 { "MM_CFG_FUNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "MM_WR_TO_CFG_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBX_RESET_EN[] = {
+	 { "COR_RESET_EN", 0, 0, &umr_bitfield_default },
+	 { "REG_RESET_EN", 1, 1, &umr_bitfield_default },
+	 { "STY_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "FLR_TWICE_EN", 8, 8, &umr_bitfield_default },
+	 { "FLR_TIMER_SEL", 9, 10, &umr_bitfield_default },
+	 { "DB_APER_RESET_EN", 15, 15, &umr_bitfield_default },
+	 { "RESET_ON_VFENABLE_LOW_EN", 16, 16, &umr_bitfield_default },
+	 { "PF_FLR_NEWHDL_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_CREDIT_CNTL[] = {
+	 { "BIF_MC_RDRET_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "BIF_AZ_RDRET_CREDIT", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_REQ_CREDIT_CNTL[] = {
+	 { "BIF_SRBM_REQ_CREDIT", 0, 4, &umr_bitfield_default },
+	 { "BIF_VGA_REQ_CREDIT", 5, 8, &umr_bitfield_default },
+	 { "BIF_HDP_REQ_CREDIT", 10, 14, &umr_bitfield_default },
+	 { "BIF_ROM_REQ_CREDIT", 15, 15, &umr_bitfield_default },
+	 { "BIF_AZ_REQ_CREDIT", 20, 20, &umr_bitfield_default },
+	 { "BIF_XDMA_REQ_CREDIT", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBX_RESET_CNTL[] = {
+	 { "LINK_TRAIN_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CNTL[] = {
+	 { "IH_DUMMY_RD_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "IH_DUMMY_RD_EN", 1, 1, &umr_bitfield_default },
+	 { "IH_REQ_NONSNOOP_EN", 3, 3, &umr_bitfield_default },
+	 { "IH_INTR_DLY_CNTR", 4, 7, &umr_bitfield_default },
+	 { "GEN_IH_INT_EN", 8, 8, &umr_bitfield_default },
+	 { "GEN_GPIO_INT_EN", 9, 12, &umr_bitfield_default },
+	 { "SELECT_INT_GPIO_OUTPUT", 13, 14, &umr_bitfield_default },
+	 { "BIF_RB_REQ_NONSNOOP_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CNTL2[] = {
+	 { "IH_DUMMY_RD_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_CNTL[] = {
+	 { "DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_MULTIBLOCKEN", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "DEBUG_PAD_SEL", 3, 3, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK1", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK2", 5, 5, &umr_bitfield_default },
+	 { "DEBUG_SYNC_EN", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_SWAP", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK1", 8, 12, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK2", 16, 20, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_XSP", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_SYNC_CLKSEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_MUX[] = {
+	 { "DEBUG_MUX_BLK1", 0, 5, &umr_bitfield_default },
+	 { "DEBUG_MUX_BLK2", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_OUT[] = {
+	 { "DEBUG_OUTPUT", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEM_COHERENCY_FLUSH_CNTL[] = {
+	 { "HDP_MEM_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCLKREQB_PAD_CNTL[] = {
+	 { "CLKREQB_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "CLKREQB_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "CLKREQB_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "CLKREQB_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+	 { "CLKREQB_PAD_Y", 13, 13, &umr_bitfield_default },
+	 { "CLKREQB_PERF_COUNTER_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCLKREQB_PERF_COUNTER[] = {
+	 { "CLKREQB_PERF_COUNTER_LOWER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_FB_EN[] = {
+	 { "FB_READ_EN", 0, 0, &umr_bitfield_default },
+	 { "FB_WRITE_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_CNTL1[] = {
+	 { "ID_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_LIST0[] = {
+	 { "ID0", 0, 7, &umr_bitfield_default },
+	 { "ID1", 8, 15, &umr_bitfield_default },
+	 { "ID2", 16, 23, &umr_bitfield_default },
+	 { "ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_LIST1[] = {
+	 { "ID4", 0, 7, &umr_bitfield_default },
+	 { "ID5", 8, 15, &umr_bitfield_default },
+	 { "ID6", 16, 23, &umr_bitfield_default },
+	 { "ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_REG_COHERENCY_FLUSH_CNTL[] = {
+	 { "HDP_REG_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSY_DELAY_CNTR[] = {
+	 { "DELAY_CNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_CNTL2[] = {
+	 { "AUTOUPDATE_SEL", 0, 7, &umr_bitfield_default },
+	 { "AUTOUPDATE_EN", 8, 8, &umr_bitfield_default },
+	 { "HDPREG_CNTL", 16, 16, &umr_bitfield_default },
+	 { "ERROR_MULTIPLE_ID_MATCH", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFMON_CNTL[] = {
+	 { "PERFCOUNTER_EN", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET0", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET1", 2, 2, &umr_bitfield_default },
+	 { "PERF_SEL0", 8, 12, &umr_bitfield_default },
+	 { "PERF_SEL1", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFCOUNTER0_RESULT[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFCOUNTER1_RESULT[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_TIMER", 9, 13, &umr_bitfield_default },
+	 { "BIF_RB_TRAN", 17, 17, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_RPTR[] = {
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_WPTR[] = {
+	 { "BIF_RB_OVERFLOW", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_WPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_WPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_HANG_PROTECTION_CNTL[] = {
+	 { "HANG_PROTECTION_TIMER_SEL", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_HDP_FLUSH_REQ[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_HDP_FLUSH_DONE[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_HANG_ERROR[] = {
+	 { "SRBM_HANG_ERROR", 0, 0, &umr_bitfield_default },
+	 { "HDP_HANG_ERROR", 1, 1, &umr_bitfield_default },
+	 { "VGA_HANG_ERROR", 2, 2, &umr_bitfield_default },
+	 { "ROM_HANG_ERROR", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_HANG_ERROR", 4, 4, &umr_bitfield_default },
+	 { "CEC_HANG_ERROR", 5, 5, &umr_bitfield_default },
+	 { "XDMA_HANG_ERROR", 7, 7, &umr_bitfield_default },
+	 { "DOORBELL_HANG_ERROR", 8, 8, &umr_bitfield_default },
+	 { "GARLIC_HANG_ERROR", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCAPTURE_HOST_BUSNUM[] = {
+	 { "CHECK_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHOST_BUSNUM[] = {
+	 { "HOST_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER_REG_RANGE0[] = {
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER_REG_RANGE1[] = {
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CAP[] = {
+	 { "VERSION", 0, 3, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 4, 7, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 8, 8, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 9, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_STATUS[] = {
+	 { "CORR_ERR", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED", 3, 3, &umr_bitfield_default },
+	 { "AUX_PWR", 4, 4, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "INITIATE_FLR", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "LINK_TRAINING", 11, 11, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 12, 12, &umr_bitfield_default },
+	 { "DL_ACTIVE", 13, 13, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_CLASS[] = {
+	 { "BASE_CLASS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSUB_CLASS[] = {
+	 { "SUB_CLASS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_STATUS2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_SCRATCH[] = {
+	 { "PIF_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_STRAP_0[] = {
+	 { "STRAP_TX_RDY_XTND_DIS", 1, 1, &umr_bitfield_default },
+	 { "STRAP_RX_RDY_XTND_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_TX_STATUS_XTND_DIS", 3, 3, &umr_bitfield_default },
+	 { "STRAP_RX_STATUS_XTND_DIS", 4, 4, &umr_bitfield_default },
+	 { "STRAP_FORCE_OWN_MSTR", 5, 5, &umr_bitfield_default },
+	 { "STRAP_PIF_CDR_EN_MODE", 6, 7, &umr_bitfield_default },
+	 { "STRAP_RX_EI_FILTER", 8, 9, &umr_bitfield_default },
+	 { "STRAP_RX_DIS_HLD_EIE_IN_PS1", 10, 10, &umr_bitfield_default },
+	 { "STRAP_RX_DIS_HLD_EIE_IN_PS2", 11, 11, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_12", 12, 12, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_13", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_14", 14, 14, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_15", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_16", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_CTRL[] = {
+	 { "PIF_PLL_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "DTM_FORCE_FREQDIV_X1", 1, 1, &umr_bitfield_default },
+	 { "PIF_PLL_HNDSHK_EARLY_ABORT", 2, 2, &umr_bitfield_default },
+	 { "PIF_PLL_PWRDN_EARLY_EXIT", 3, 3, &umr_bitfield_default },
+	 { "PHY_RST_PWROK_VDD", 4, 4, &umr_bitfield_default },
+	 { "PIF_PLL_STATUS", 6, 7, &umr_bitfield_default },
+	 { "PIF_PLL_DEGRADE_OFF_VOTE", 8, 8, &umr_bitfield_default },
+	 { "PIF_PLL_UNUSED_OFF_VOTE", 9, 9, &umr_bitfield_default },
+	 { "PIF_PLL_DEGRADE_S2_VOTE", 10, 10, &umr_bitfield_default },
+	 { "PIF_PG_EXIT_MODE", 11, 11, &umr_bitfield_default },
+	 { "PIF_DEGRADE_PWR_PLL_MODE", 12, 12, &umr_bitfield_default },
+	 { "PIF_LANEUNUSED_AFFECT_GANG", 13, 13, &umr_bitfield_default },
+	 { "PIF_PG_ABORT_DISABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_TX_CTRL[] = {
+	 { "TXPWR_IN_S2", 0, 2, &umr_bitfield_default },
+	 { "TXPWR_IN_SPDCHNG", 3, 5, &umr_bitfield_default },
+	 { "TXPWR_IN_OFF", 6, 8, &umr_bitfield_default },
+	 { "TXPWR_IN_DEGRADE", 9, 11, &umr_bitfield_default },
+	 { "TXPWR_IN_UNUSED", 12, 14, &umr_bitfield_default },
+	 { "TXPWR_IN_INIT", 15, 17, &umr_bitfield_default },
+	 { "TXPWR_IN_PLL_OFF", 18, 20, &umr_bitfield_default },
+	 { "TXPWR_IN_DEGRADE_MODE", 21, 21, &umr_bitfield_default },
+	 { "TXPWR_IN_UNUSED_MODE", 22, 22, &umr_bitfield_default },
+	 { "TXPWR_GATING_IN_L1", 23, 23, &umr_bitfield_default },
+	 { "TXPWR_GATING_IN_UNUSED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_TX_CTRL2[] = {
+	 { "TX_RDY_DASRT_COUNT", 0, 2, &umr_bitfield_default },
+	 { "TX_STATUS_DASRT_COUNT", 3, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_DELAY", 6, 8, &umr_bitfield_default },
+	 { "TX_L1_PG_PHY_STATUS_MODE", 9, 9, &umr_bitfield_default },
+	 { "TX_OFF_PG_PHY_STATUS_MODE", 10, 10, &umr_bitfield_default },
+	 { "TX_HIGH_IMP_STAG_MP", 16, 16, &umr_bitfield_default },
+	 { "TX_HIGH_IMP_STAG_MODE", 17, 18, &umr_bitfield_default },
+	 { "TX_FORCE_DATA_VALID", 21, 21, &umr_bitfield_default },
+	 { "TX_L0_TO_HIZ_DLY", 22, 24, &umr_bitfield_default },
+	 { "TX_FIFO_INIT_UPCONFIG", 25, 25, &umr_bitfield_default },
+	 { "TX_HIZ_TO_L0_DLY", 26, 28, &umr_bitfield_default },
+	 { "TX_LINKSPEED_ACK_IN_S2", 29, 29, &umr_bitfield_default },
+	 { "TX_DELAY_FIFO_INIT_IN_S1", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_RX_CTRL[] = {
+	 { "RXPWR_IN_S2", 0, 2, &umr_bitfield_default },
+	 { "RXPWR_IN_SPDCHNG", 3, 5, &umr_bitfield_default },
+	 { "RXPWR_IN_OFF", 6, 8, &umr_bitfield_default },
+	 { "RXPWR_IN_DEGRADE", 9, 11, &umr_bitfield_default },
+	 { "RXPWR_IN_UNUSED", 12, 14, &umr_bitfield_default },
+	 { "RXPWR_IN_INIT", 15, 17, &umr_bitfield_default },
+	 { "RXPWR_IN_PLL_OFF", 18, 20, &umr_bitfield_default },
+	 { "RXPWR_IN_DEGRADE_MODE", 21, 21, &umr_bitfield_default },
+	 { "RXPWR_IN_UNUSED_MODE", 22, 22, &umr_bitfield_default },
+	 { "RXPWR_GATING_IN_L1", 23, 23, &umr_bitfield_default },
+	 { "RXPWR_GATING_IN_UNUSED", 24, 24, &umr_bitfield_default },
+	 { "RX_HLD_EIE_COUNT", 25, 25, &umr_bitfield_default },
+	 { "RX_EI_DET_IN_PS2_DEGRADE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_RX_CTRL2[] = {
+	 { "RX_RDY_DASRT_COUNT", 0, 2, &umr_bitfield_default },
+	 { "RX_STATUS_DASRT_COUNT", 3, 5, &umr_bitfield_default },
+	 { "RXPHYSTATUS_DELAY", 6, 8, &umr_bitfield_default },
+	 { "RX_L1_PG_PHY_STATUS_MODE", 9, 9, &umr_bitfield_default },
+	 { "RX_OFF_PG_PHY_STATUS_MODE", 10, 10, &umr_bitfield_default },
+	 { "FORCE_CDREN_IN_L0S", 16, 16, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_MODE", 17, 18, &umr_bitfield_default },
+	 { "EI_DET_ON_TIME", 19, 20, &umr_bitfield_default },
+	 { "EI_DET_OFF_TIME", 21, 23, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_DIS_IN_PS1", 24, 24, &umr_bitfield_default },
+	 { "RX_CDR_XTND_MODE", 25, 26, &umr_bitfield_default },
+	 { "RX_L0S_TO_L0_DETECT_EI", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_GLB_OVRD[] = {
+	 { "RXDETECT_OVERRIDE_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_1", 1, 1, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_3", 3, 3, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_5", 5, 5, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_6", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_7", 7, 7, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_GLB_OVRD2[] = {
+	 { "X2_LANE_1_0_OVRD", 0, 0, &umr_bitfield_default },
+	 { "X2_LANE_3_2_OVRD", 1, 1, &umr_bitfield_default },
+	 { "X2_LANE_5_4_OVRD", 2, 2, &umr_bitfield_default },
+	 { "X2_LANE_7_6_OVRD", 3, 3, &umr_bitfield_default },
+	 { "X2_LANE_9_8_OVRD", 4, 4, &umr_bitfield_default },
+	 { "X2_LANE_11_10_OVRD", 5, 5, &umr_bitfield_default },
+	 { "X2_LANE_13_12_OVRD", 6, 6, &umr_bitfield_default },
+	 { "X2_LANE_15_14_OVRD", 7, 7, &umr_bitfield_default },
+	 { "X4_LANE_3_0_OVRD", 8, 8, &umr_bitfield_default },
+	 { "X4_LANE_7_4_OVRD", 9, 9, &umr_bitfield_default },
+	 { "X4_LANE_11_8_OVRD", 10, 10, &umr_bitfield_default },
+	 { "X4_LANE_15_12_OVRD", 11, 11, &umr_bitfield_default },
+	 { "X8_LANE_7_0_OVRD", 16, 16, &umr_bitfield_default },
+	 { "X8_LANE_15_8_OVRD", 17, 17, &umr_bitfield_default },
+	 { "X16_LANE_15_0_OVRD", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_BIF_CMD_STATUS[] = {
+	 { "TXPHYSTATUS_0", 0, 0, &umr_bitfield_default },
+	 { "TXPHYSTATUS_1", 1, 1, &umr_bitfield_default },
+	 { "TXPHYSTATUS_2", 2, 2, &umr_bitfield_default },
+	 { "TXPHYSTATUS_3", 3, 3, &umr_bitfield_default },
+	 { "TXPHYSTATUS_4", 4, 4, &umr_bitfield_default },
+	 { "TXPHYSTATUS_5", 5, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_6", 6, 6, &umr_bitfield_default },
+	 { "TXPHYSTATUS_7", 7, 7, &umr_bitfield_default },
+	 { "RXPHYSTATUS_0", 8, 8, &umr_bitfield_default },
+	 { "RXPHYSTATUS_1", 9, 9, &umr_bitfield_default },
+	 { "RXPHYSTATUS_2", 10, 10, &umr_bitfield_default },
+	 { "RXPHYSTATUS_3", 11, 11, &umr_bitfield_default },
+	 { "RXPHYSTATUS_4", 12, 12, &umr_bitfield_default },
+	 { "RXPHYSTATUS_5", 13, 13, &umr_bitfield_default },
+	 { "RXPHYSTATUS_6", 14, 14, &umr_bitfield_default },
+	 { "RXPHYSTATUS_7", 15, 15, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_0", 16, 16, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_1", 17, 17, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_2", 18, 18, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_3", 19, 19, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_4", 20, 20, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_5", 21, 21, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_6", 22, 22, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_7", 23, 23, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_0", 24, 24, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_1", 25, 25, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_2", 26, 26, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_3", 27, 27, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_4", 28, 28, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_5", 29, 29, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_6", 30, 30, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_CMD_BUS_CTRL[] = {
+	 { "CMD_BUS_SCHL_MODE", 0, 1, &umr_bitfield_default },
+	 { "CMD_BUS_STAG_MODE", 2, 3, &umr_bitfield_default },
+	 { "CMD_BUS_STAG_DIS", 4, 4, &umr_bitfield_default },
+	 { "CMD_BUS_SCH_REQ_MODE", 5, 6, &umr_bitfield_default },
+	 { "CMD_BUS_IGNR_PEND_PWR", 7, 7, &umr_bitfield_default },
+	 { "SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES", 8, 8, &umr_bitfield_default },
+	 { "CMD_BUS_IGNR_PWR_NOT_ON", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_CMD_BUS_GLB_OVRD[] = {
+	 { "TXMARG_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "DEEMPH_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "PLLFREQ_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TXMARG", 3, 5, &umr_bitfield_default },
+	 { "DEEMPH", 6, 6, &umr_bitfield_default },
+	 { "PLLFREQ", 7, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_PIF_OVRD", 9, 9, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_0", 16, 16, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_1", 17, 17, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_2", 18, 18, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_3", 19, 19, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_4", 20, 20, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_5", 21, 21, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_6", 22, 22, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_7", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE0_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_0", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_0", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_0", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_0", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_0", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_0", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_0", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_0", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE0_OVRD2[] = {
+	 { "GANGMODE_0", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_0", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_0", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_0", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_0", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_0", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_0", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_0", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_0", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_0", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_0", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_0", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE1_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_1", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_1", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_1", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_1", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_1", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_1", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_1", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_1", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_1", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_1", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_1", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_1", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE1_OVRD2[] = {
+	 { "GANGMODE_1", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_1", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_1", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_1", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_1", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_1", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_1", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_1", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_1", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_1", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_1", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE2_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_2", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_2", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_2", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_2", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_2", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_2", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_2", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_2", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_2", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_2", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_2", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_2", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_2", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE2_OVRD2[] = {
+	 { "GANGMODE_2", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_2", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_2", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_2", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_2", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_2", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_2", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_2", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_2", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_2", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_2", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_2", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE3_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_3", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_3", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_3", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_3", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_3", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_3", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_3", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_3", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_3", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_3", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_3", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_3", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_3", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE3_OVRD2[] = {
+	 { "GANGMODE_3", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_3", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_3", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_3", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_3", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_3", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_3", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_3", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_3", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_3", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_3", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_3", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE4_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_4", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_4", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_4", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_4", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_4", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_4", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_4", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_4", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_4", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_4", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_4", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_4", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE4_OVRD2[] = {
+	 { "GANGMODE_4", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_4", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_4", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_4", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_4", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_4", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_4", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_4", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_4", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_4", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_4", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_4", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE5_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_5", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_5", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_5", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_5", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_5", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_5", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_5", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_5", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_5", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_5", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_5", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_5", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_5", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE5_OVRD2[] = {
+	 { "GANGMODE_5", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_5", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_5", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_5", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_5", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_5", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_5", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_5", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_5", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_5", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_5", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_5", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE6_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_6", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_6", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_6", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_6", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_6", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_6", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_6", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_6", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_6", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_6", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_6", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_6", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_6", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE6_OVRD2[] = {
+	 { "GANGMODE_6", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_6", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_6", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_6", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_6", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_6", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_6", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_6", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_6", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_6", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_6", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_6", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE7_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_7", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_7", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_7", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_7", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_7", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_7", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_7", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_7", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_7", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_7", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_7", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_7", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_7", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PIF_LANE7_OVRD2[] = {
+	 { "GANGMODE_7", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_7", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_7", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_7", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_7", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_7", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_7", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_7", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_7", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_7", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_7", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_7", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 0, 0, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 1, 1, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 2, 2, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 3, 3, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 4, 4, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG0[] = {
+	 { "BACKUP", 0, 15, &umr_bitfield_default },
+	 { "CFG_IDLEDET_TH", 16, 17, &umr_bitfield_default },
+	 { "DBG_RX2TXBYP_SEL", 20, 22, &umr_bitfield_default },
+	 { "DBG_RXFEBYP_EN", 23, 23, &umr_bitfield_default },
+	 { "DBG_RXPRBS_CLR", 24, 24, &umr_bitfield_default },
+	 { "DBG_RXTOGGLE_EN", 25, 25, &umr_bitfield_default },
+	 { "DBG_TX2RXLBACK_EN", 26, 26, &umr_bitfield_default },
+	 { "TXCFG_CMGOOD_RANGE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG1[] = {
+	 { "RXDBG_CDR_FR_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_CDR_FR_BYP_VAL", 1, 6, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_EN", 7, 7, &umr_bitfield_default },
+	 { "RXDBG_CDR_PH_BYP_VAL", 8, 13, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_EN", 14, 14, &umr_bitfield_default },
+	 { "RXDBG_D0TH_BYP_VAL", 15, 21, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "RXDBG_D1TH_BYP_VAL", 23, 29, &umr_bitfield_default },
+	 { "TST_LOSPDTST_EN", 30, 30, &umr_bitfield_default },
+	 { "PLL_CFG_DISPCLK_DIV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG2[] = {
+	 { "RXDBG_D2TH_BYP_EN", 0, 0, &umr_bitfield_default },
+	 { "RXDBG_D2TH_BYP_VAL", 1, 7, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_EN", 8, 8, &umr_bitfield_default },
+	 { "RXDBG_D3TH_BYP_VAL", 9, 15, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_EN", 16, 16, &umr_bitfield_default },
+	 { "RXDBG_DXTH_BYP_VAL", 17, 23, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_EN", 24, 24, &umr_bitfield_default },
+	 { "RXDBG_ETH_BYP_VAL", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG3[] = {
+	 { "RXDBG_SEL", 0, 4, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF0_SEL", 5, 6, &umr_bitfield_default },
+	 { "BG_CFG_LC_REG_VREF1_SEL", 7, 8, &umr_bitfield_default },
+	 { "BG_CFG_RO_REG_VREF_SEL", 9, 10, &umr_bitfield_default },
+	 { "BG_DBG_VREFBYP_EN", 11, 11, &umr_bitfield_default },
+	 { "BG_DBG_IREFBYP_EN", 12, 12, &umr_bitfield_default },
+	 { "BG_DBG_ANALOG_SEL", 14, 16, &umr_bitfield_default },
+	 { "DBG_DLL_CLK_SEL", 18, 20, &umr_bitfield_default },
+	 { "PLL_DISPCLK_CMOS_SEL", 21, 21, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_EN", 22, 22, &umr_bitfield_default },
+	 { "DBG_RXPI_OFFSET_BYP_VAL", 23, 26, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_EN", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXSWAPDX_BYP_VAL", 28, 30, &umr_bitfield_default },
+	 { "DBG_RXLEQ_DCATTN_BYP_OVR_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG4[] = {
+	 { "DBG_RXAPU_INST", 0, 15, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_VAL", 16, 17, &umr_bitfield_default },
+	 { "DBG_RXDFEMUX_BYP_EN", 18, 18, &umr_bitfield_default },
+	 { "DBG_RXAPU_EXEC", 22, 25, &umr_bitfield_default },
+	 { "DBG_RXDLL_VREG_REF_SEL", 26, 26, &umr_bitfield_default },
+	 { "PWRGOOD_OVRD", 27, 27, &umr_bitfield_default },
+	 { "DBG_RXRDATA_GATING_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_CTRL_REG5[] = {
+	 { "DBG_RXAPU_MODE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_ALL_CBI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_ALL_CBI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_ALL_CBI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_ALL_CBI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_IMPCAL_ACTIVE_CBI_UPDT", 4, 4, &umr_bitfield_default },
+	 { "TXNIMP", 8, 11, &umr_bitfield_default },
+	 { "TXPIMP", 12, 15, &umr_bitfield_default },
+	 { "RXIMP", 16, 19, &umr_bitfield_default },
+	 { "IMPCAL_ACTIVE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG1[] = {
+	 { "IGNR_LINKSPEED_CBI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_CBI_UPDT_L0T3", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_CBI_UPDT_L0T3", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_0", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_1", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_2", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_3", 15, 15, &umr_bitfield_default },
+	 { "LINKSPEED_0", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_0", 18, 19, &umr_bitfield_default },
+	 { "LINKSPEED_1", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_1", 22, 23, &umr_bitfield_default },
+	 { "LINKSPEED_2", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_2", 26, 27, &umr_bitfield_default },
+	 { "LINKSPEED_3", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG2[] = {
+	 { "IGNR_LINKSPEED_CBI_UPDT_L4T7", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_CBI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_CBI_UPDT_L4T7", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_4", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_5", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_6", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_7", 15, 15, &umr_bitfield_default },
+	 { "LINKSPEED_4", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_4", 18, 19, &umr_bitfield_default },
+	 { "LINKSPEED_5", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_5", 22, 23, &umr_bitfield_default },
+	 { "LINKSPEED_6", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_6", 26, 27, &umr_bitfield_default },
+	 { "LINKSPEED_7", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_7", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG3[] = {
+	 { "IGNR_LINKSPEED_CBI_UPDT_L8T11", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_CBI_UPDT_L8T11", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_CBI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_8", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_9", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_10", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_11", 15, 15, &umr_bitfield_default },
+	 { "LINKSPEED_8", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_8", 18, 19, &umr_bitfield_default },
+	 { "LINKSPEED_9", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_9", 22, 23, &umr_bitfield_default },
+	 { "LINKSPEED_10", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_10", 26, 27, &umr_bitfield_default },
+	 { "LINKSPEED_11", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_11", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_SCI_STAT_OVRD_REG4[] = {
+	 { "IGNR_LINKSPEED_CBI_UPDT_L12T15", 0, 0, &umr_bitfield_default },
+	 { "IGNR_FREQDIV_CBI_UPDT_L12T15", 1, 1, &umr_bitfield_default },
+	 { "IGNR_DLL_LOCK_CBI_UPDT_L12T15", 2, 2, &umr_bitfield_default },
+	 { "DLL_LOCK_12", 12, 12, &umr_bitfield_default },
+	 { "DLL_LOCK_13", 13, 13, &umr_bitfield_default },
+	 { "DLL_LOCK_14", 14, 14, &umr_bitfield_default },
+	 { "DLL_LOCK_15", 15, 15, &umr_bitfield_default },
+	 { "LINKSPEED_12", 16, 17, &umr_bitfield_default },
+	 { "FREQDIV_12", 18, 19, &umr_bitfield_default },
+	 { "LINKSPEED_13", 20, 21, &umr_bitfield_default },
+	 { "FREQDIV_13", 22, 23, &umr_bitfield_default },
+	 { "LINKSPEED_14", 24, 25, &umr_bitfield_default },
+	 { "FREQDIV_14", 26, 27, &umr_bitfield_default },
+	 { "LINKSPEED_15", 28, 29, &umr_bitfield_default },
+	 { "FREQDIV_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_OVRD_REG0[] = {
+	 { "TXPDTERM_VAL_OVRD_VAL", 0, 15, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_OVRD_REG1[] = {
+	 { "TXPDTERM_VAL_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "TXPUTERM_VAL_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TST_LOSPDTST_RST_OVRD_VAL", 3, 3, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_EN", 15, 15, &umr_bitfield_default },
+	 { "RXTERM_VAL_OVRD_VAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_GLB_OVRD_REG2[] = {
+	 { "BG_PWRON_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "BG_PWRON_OVRD_VAL", 1, 1, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_OVRD_VAL", 3, 3, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_OVRD_EN", 4, 4, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_OVRD_VAL", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_GLB_REG0[] = {
+	 { "STRAP_QUICK_SIM_START", 1, 1, &umr_bitfield_default },
+	 { "STRAP_DFT_RXBSCAN_EN_VAL", 2, 2, &umr_bitfield_default },
+	 { "STRAP_DFT_CALIB_BYPASS", 3, 3, &umr_bitfield_default },
+	 { "STRAP_FORCE_LC_PLL_ON", 4, 4, &umr_bitfield_default },
+	 { "STRAP_CFG_IDLEDET_TH", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_DCATTN_BYP_VAL", 7, 11, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_OVR_PWRSF", 12, 12, &umr_bitfield_default },
+	 { "STRAP_RX_TRK_MODE_0_", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PWRGOOD_OVRD", 14, 14, &umr_bitfield_default },
+	 { "STRAP_DBG_RXDLL_VREG_REF_SEL", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_LC_VCO_TUNE", 16, 19, &umr_bitfield_default },
+	 { "STRAP_DBG_RXRDATA_GATING_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "STRAP_DBG_RXPI_OFFSET_BYP_VAL", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_TX_REG0[] = {
+	 { "STRAP_TX_CFG_DRV0_EN", 1, 4, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV0_TAP_SEL", 5, 8, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV1_EN", 9, 13, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV1_TAP_SEL", 14, 18, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV2_EN", 19, 22, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRV2_TAP_SEL", 23, 26, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRVX_EN", 27, 27, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_DRVX_TAP_SEL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_RX_TRK_MODE_1_", 29, 29, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_SWING_BOOST_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_RX_REG0[] = {
+	 { "STRAP_RX_CFG_TH_LOOP_GAIN", 1, 4, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_DLL_FLOCK_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "STRAP_DBG_RXPI_OFFSET_BYP_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_DCATTN_BYP_DIS", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_LC_REG_VREF0_SEL", 8, 9, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_LC_REG_VREF1_SEL", 10, 11, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_CDR_TIME", 12, 15, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_FOM_TIME", 16, 19, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_TIME", 20, 23, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_OC_TIME", 24, 27, &umr_bitfield_default },
+	 { "STRAP_TX_CFG_RPTR_RST_VAL", 28, 30, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_TERM_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_RX_REG1[] = {
+	 { "STRAP_RX_CFG_CDR_PI_STPSZ", 1, 1, &umr_bitfield_default },
+	 { "STRAP_TX_DEEMPH_PRSHT_STNG", 2, 4, &umr_bitfield_default },
+	 { "STRAP_BG_CFG_RO_REG_VREF_SEL", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_POLE_BYP_DIS", 7, 7, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_POLE_BYP_VAL", 8, 10, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_CDR_PH_GAIN", 11, 14, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_ADAPT_MODE", 15, 24, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_DFE_TIME", 25, 28, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_LOOP_GAIN", 29, 30, &umr_bitfield_default },
+	 { "STRAP_RX_CFG_LEQ_SHUNT_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_PLL_REG0[] = {
+	 { "STRAP_PLL_CFG_LC_BW_CNTRL", 1, 3, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_LC_LF_CNTRL", 4, 12, &umr_bitfield_default },
+	 { "STRAP_TX_RXDET_X1_SSF", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_RO_VTOI_BIAS_CNTRL_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PLL_CFG_RO_BW_CNTRL", 16, 23, &umr_bitfield_default },
+	 { "STRAP_PLL_STRAP_SEL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_PIN_REG0[] = {
+	 { "STRAP_TX_DEEMPH_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_TX_FULL_SWING", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_GLB_REG1[] = {
+	 { "STRAP_RX_ADAPT_RST_MODE", 1, 2, &umr_bitfield_default },
+	 { "STRAP_RX_L0_ENTRY_MODE", 3, 4, &umr_bitfield_default },
+	 { "STRAP_RX_EI_FILTER", 5, 6, &umr_bitfield_default },
+	 { "STRAP_RX_ADAPT_RST_SUB_ENTRY", 7, 7, &umr_bitfield_default },
+	 { "STRAP_RX_PS0_RDY_GEN_MODE", 8, 9, &umr_bitfield_default },
+	 { "STRAP_RX_DLL_RESET_IN_SPDCHG", 10, 10, &umr_bitfield_default },
+	 { "STRAP_RX_ADAPT_TIME_OUT", 11, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_STRAP_GLB_REG2[] = {
+	 { "STRAP_BPHYC_PLL_RAMP_UP_TIME", 2, 4, &umr_bitfield_default },
+	 { "STRAP_IMPCAL_SETTLE_TIME", 5, 6, &umr_bitfield_default },
+	 { "STRAP_BG_SETTLE_TIME", 7, 8, &umr_bitfield_default },
+	 { "STRAP_TX_CMDET_TIME", 9, 10, &umr_bitfield_default },
+	 { "STRAP_TX_STARTUP_TIME", 11, 12, &umr_bitfield_default },
+	 { "STRAP_B_PCB_DIS0", 28, 28, &umr_bitfield_default },
+	 { "STRAP_B_PCB_DIS1", 29, 29, &umr_bitfield_default },
+	 { "STRAP_B_PCB_DRV_STR", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_JIT_INJ_REG0[] = {
+	 { "DFT_NUM_STEPS", 0, 5, &umr_bitfield_default },
+	 { "DFT_DISABLE_ERR", 7, 7, &umr_bitfield_default },
+	 { "DFT_CLK_PER_STEP", 8, 11, &umr_bitfield_default },
+	 { "DFT_MODE_CDR_EN", 20, 20, &umr_bitfield_default },
+	 { "DFT_EN_RECOVERY", 21, 21, &umr_bitfield_default },
+	 { "DFT_INCR_SWP_EN", 22, 22, &umr_bitfield_default },
+	 { "DFT_DECR_SWP_EN", 23, 23, &umr_bitfield_default },
+	 { "DFT_RECOVERY_TIME", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_JIT_INJ_REG1[] = {
+	 { "DFT_BYPASS_VALUE", 0, 7, &umr_bitfield_default },
+	 { "DFT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "DFT_BLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DFT_NUM_OF_TESTS", 17, 19, &umr_bitfield_default },
+	 { "DFT_CHECK_TIME", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_JIT_INJ_REG2[] = {
+	 { "DFT_LANE_EN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_DEBUG_CTRL_REG0[] = {
+	 { "DFT_PHY_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DFT_PHY_DEBUG_MODE", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_DFT_JIT_INJ_STAT_REG0[] = {
+	 { "DFT_STAT_DECR", 0, 7, &umr_bitfield_default },
+	 { "DFT_STAT_INCR", 8, 15, &umr_bitfield_default },
+	 { "DFT_STAT_FINISHED", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO_GLB_CTRL_REG0[] = {
+	 { "PLL_TST_LOSPDTST_SRC", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 2, 2, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 3, 3, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 4, 4, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 5, 5, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 6, 6, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_LUT_ENTRY_LS2", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_LUT_ENTRY_LS2", 8, 8, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS0", 9, 9, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS1", 10, 10, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_LUT_ENTRY_LS2", 11, 11, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS0", 12, 12, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS1", 13, 13, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_LUT_ENTRY_LS2", 14, 14, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_GATING_EN", 15, 15, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_GATING_EN", 16, 16, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_GATING_EN", 17, 17, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_GATING_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO0_CTRL_REG0[] = {
+	 { "PLL_DBG_RO_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_RO_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_RO_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_DBG_RO_LF_CNTRL_0", 4, 10, &umr_bitfield_default },
+	 { "PLL_TST_RO_USAMPLE_EN_0", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO0_OVRD_REG0[] = {
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_VAL_0", 0, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_BW_CNTRL_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_VAL_0", 9, 11, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_DIV_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_CFG_RO_CORECLK_EN_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_VAL_0", 15, 27, &umr_bitfield_default },
+	 { "PLL_CFG_RO_FBDIV_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_VAL_0", 30, 30, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VTOI_BIAS_CNTRL_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO0_OVRD_REG1[] = {
+	 { "PLL_CFG_RO_REFDIV_OVRD_VAL_0", 0, 4, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFDIV_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_VAL_0", 6, 7, &umr_bitfield_default },
+	 { "PLL_CFG_RO_VCO_MODE_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_VAL_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_LEFT_EN_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_VAL_0", 11, 11, &umr_bitfield_default },
+	 { "PLL_RO_HSCLK_RIGHT_EN_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_VAL_0", 13, 13, &umr_bitfield_default },
+	 { "PLL_RO_PWRON_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_VAL_0", 19, 21, &umr_bitfield_default },
+	 { "PLL_CFG_RO_REFCLK_SRC_OVRD_EN_0", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO0_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO0_IGNR_PLLFREQ_CBI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO0_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO0_PLLFREQ", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO1_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO1_IGNR_PLLFREQ_CBI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO1_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO1_PLLFREQ", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO2_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO2_IGNR_PLLFREQ_CBI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO2_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO2_PLLFREQ", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_RO3_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_RO3_IGNR_PLLFREQ_CBI_UPDT", 1, 1, &umr_bitfield_default },
+	 { "PLL_RO3_PLLPWR", 4, 6, &umr_bitfield_default },
+	 { "PLL_RO3_PLLFREQ", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC0_CTRL_REG0[] = {
+	 { "PLL_DBG_LC_ANALOG_SEL_0", 0, 1, &umr_bitfield_default },
+	 { "PLL_DBG_LC_EXT_RESET_EN_0", 2, 2, &umr_bitfield_default },
+	 { "PLL_DBG_LC_VCTL_ADC_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_TST_LC_USAMPLE_EN_0", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC0_OVRD_REG0[] = {
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_BW_CNTRL_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_VAL_0", 4, 6, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_DIV_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_CFG_LC_CORECLK_EN_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_VAL_0", 10, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_FBDIV_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_VAL_0", 19, 27, &umr_bitfield_default },
+	 { "PLL_CFG_LC_LF_CNTRL_OVRD_EN_0", 28, 28, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_VAL_0", 29, 30, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFDIV_OVRD_EN_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC0_OVRD_REG1[] = {
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_VAL_0", 0, 2, &umr_bitfield_default },
+	 { "PLL_CFG_LC_REFCLK_SRC_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_LEFT_EN_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "PLL_LC_HSCLK_RIGHT_EN_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_VAL_0", 8, 8, &umr_bitfield_default },
+	 { "PLL_LC_PWRON_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_VAL_0", 14, 17, &umr_bitfield_default },
+	 { "PLL_CFG_LC_VCO_TUNE_OVRD_EN_0", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC0_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC0_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC1_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC1_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC2_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC2_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0[] = {
+	 { "PLL_LC3_IGNR_PLLPWR_CBI_UPDT", 0, 0, &umr_bitfield_default },
+	 { "PLL_LC3_PLLPWR", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG0[] = {
+	 { "RX_CFG_ADAPT_MODE_GEN1", 0, 9, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN2", 10, 19, &umr_bitfield_default },
+	 { "RX_CFG_ADAPT_MODE_GEN3", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG1[] = {
+	 { "RX_CFG_CDR_FR_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PH_GAIN_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN1", 24, 24, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN2", 25, 25, &umr_bitfield_default },
+	 { "RX_CFG_CDR_PI_STPSZ_GEN3", 26, 26, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_EN_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_ASRT_TO_DCLK_EN", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG2[] = {
+	 { "RX_CFG_CDR_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_CDR_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN1", 24, 25, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN2", 26, 27, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_LOOP_GAIN_GEN3", 28, 29, &umr_bitfield_default },
+	 { "RX_DCLK_EN_ASRT_TO_ADAPT_HLD", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG3[] = {
+	 { "RX_CFG_CDR_FR_EN_GEN1", 0, 0, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN2", 1, 1, &umr_bitfield_default },
+	 { "RX_CFG_CDR_FR_EN_GEN3", 2, 2, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_MODE_GEN1", 3, 4, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_MODE_GEN2", 5, 6, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_MODE_GEN3", 7, 8, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_SUB_MODE", 9, 11, &umr_bitfield_default },
+	 { "RX_L0_ENTRY_MODE_GEN1", 12, 13, &umr_bitfield_default },
+	 { "RX_L0_ENTRY_MODE_GEN2", 14, 15, &umr_bitfield_default },
+	 { "RX_L0_ENTRY_MODE_GEN3", 16, 17, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_DFE_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG4[] = {
+	 { "RX_CFG_FOM_BER_GEN1", 0, 2, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN2", 3, 5, &umr_bitfield_default },
+	 { "RX_CFG_FOM_BER_GEN3", 6, 8, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN1", 9, 11, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN2", 12, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_VAL_GEN3", 15, 17, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN1", 20, 23, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN2", 24, 27, &umr_bitfield_default },
+	 { "RX_CFG_FOM_TIME_GEN3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG5[] = {
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN1", 0, 4, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN2", 5, 9, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_DCATTN_BYP_VAL_GEN3", 10, 14, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN1", 15, 15, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN2", 16, 16, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_POLE_BYP_EN_GEN3", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN1", 18, 18, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN2", 19, 19, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_SHUNT_EN_GEN3", 20, 20, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_TERM_MODE_GEN3", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_AUX_PWRON_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG6[] = {
+	 { "RX_CFG_LEQ_TIME_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_LEQ_TIME_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN1", 12, 15, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN2", 16, 19, &umr_bitfield_default },
+	 { "RX_CFG_OC_TIME_GEN3", 20, 23, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS0_CDR_EN_0", 24, 24, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_LUT_ENTRY_LS2", 26, 26, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_LUT_ENTRY_LS2", 27, 27, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_L0S_EARLY_EXIT_DIS", 28, 28, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_L1_DLL_OFF", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG7[] = {
+	 { "RX_CFG_TH_LOOP_GAIN_GEN1", 0, 3, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN2", 4, 7, &umr_bitfield_default },
+	 { "RX_CFG_TH_LOOP_GAIN_GEN3", 8, 11, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS0_CDR_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_DCLK_EN_LUT_ENTRY_LS2", 13, 13, &umr_bitfield_default },
+	 { "RX_DCLK_EN_AFTER_DLL_LOCK", 14, 14, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_LUT_ENTRY_PS3", 16, 16, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_LUT_ENTRY_PS2", 17, 17, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN1", 18, 20, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN2", 21, 23, &umr_bitfield_default },
+	 { "RX_CFG_DLL_CPI_SEL_GEN3", 24, 26, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN1", 27, 27, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN2", 28, 28, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FLOCK_DISABLE_GEN3", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_CTRL_REG8[] = {
+	 { "RX_DLL_LOCK_TIME", 0, 1, &umr_bitfield_default },
+	 { "RX_DLL_SPEEDCHANGE_RESET_TIME", 2, 3, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_IN_RAMPDOWN", 4, 4, &umr_bitfield_default },
+	 { "RX_FSM_L0S_IF_RX_RDY", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_RXPWR_CBI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_RXPWR_CBI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_RXPWR_CBI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_RXPWR_CBI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_CBI_UPDT_L0T3", 4, 4, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_CBI_UPDT_L4T7", 5, 5, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_CBI_UPDT_L8T11", 6, 6, &umr_bitfield_default },
+	 { "IGNR_ELECIDLEDETEN_CBI_UPDT_L12T15", 7, 7, &umr_bitfield_default },
+	 { "IGNR_REQUESTTRK_CBI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_REQUESTTRK_CBI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_REQUESTTRK_CBI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_REQUESTTRK_CBI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_CBI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_CBI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_CBI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_ENABLEFOM_CBI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_CBI_UPDT_L0T3", 16, 16, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_CBI_UPDT_L4T7", 17, 17, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_CBI_UPDT_L8T11", 18, 18, &umr_bitfield_default },
+	 { "IGNR_REQUESTFOM_CBI_UPDT_L12T15", 19, 19, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_CBI_UPDT_L0T3", 20, 20, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_CBI_UPDT_L4T7", 21, 21, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_CBI_UPDT_L8T11", 22, 22, &umr_bitfield_default },
+	 { "IGNR_RESPONSEMODE_CBI_UPDT_L12T15", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_OVRD_REG0[] = {
+	 { "RX_ADAPT_HLD_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_HLD_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "RX_ADAPT_RST_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_VAL", 6, 7, &umr_bitfield_default },
+	 { "RX_CFG_DCLK_DIV_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "RX_CFG_DLL_FREQ_MODE_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "RX_CFG_PLLCLK_SEL_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "RX_CFG_RCLK_DIV_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_VAL", 15, 15, &umr_bitfield_default },
+	 { "RX_DCLK_EN_OVRD_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_VAL", 17, 17, &umr_bitfield_default },
+	 { "RX_DLL_PWRON_OVRD_EN", 18, 18, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_VAL", 19, 19, &umr_bitfield_default },
+	 { "RX_FRONTEND_PWRON_OVRD_EN", 20, 20, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_VAL", 21, 21, &umr_bitfield_default },
+	 { "RX_IDLEDET_PWRON_OVRD_EN", 22, 22, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "RX_AUX_PWRON_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "RX_ADAPT_FOM_OVRD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_GLB_OVRD_REG1[] = {
+	 { "RX_ADAPT_TRK_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "RX_ADAPT_TRK_OVRD_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE0_CTRL_REG0[] = {
+	 { "RX_BACKUP_0", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_0", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_0", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_0", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_0", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_0", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_0", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_0", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_0", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE1_CTRL_REG0[] = {
+	 { "RX_BACKUP_1", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_1", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_1", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_1", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_1", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_1", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_1", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_1", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_1", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE2_CTRL_REG0[] = {
+	 { "RX_BACKUP_2", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_2", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_2", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_2", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_2", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_2", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_2", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_2", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_2", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE3_CTRL_REG0[] = {
+	 { "RX_BACKUP_3", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_3", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_3", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_3", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_3", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_3", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_3", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_3", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_3", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE4_CTRL_REG0[] = {
+	 { "RX_BACKUP_4", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_4", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_4", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_4", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_4", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_4", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_4", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_4", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_4", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE5_CTRL_REG0[] = {
+	 { "RX_BACKUP_5", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_5", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_5", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_5", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_5", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_5", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_5", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_5", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_5", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE6_CTRL_REG0[] = {
+	 { "RX_BACKUP_6", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_6", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_6", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_6", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_6", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_6", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_6", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_6", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_6", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE7_CTRL_REG0[] = {
+	 { "RX_BACKUP_7", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_7", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_7", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_7", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_7", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_7", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_7", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_7", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_7", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE8_CTRL_REG0[] = {
+	 { "RX_BACKUP_8", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_8", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_8", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_8", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_8", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_8", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_8", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_8", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_8", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_8", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_8", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_8", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE9_CTRL_REG0[] = {
+	 { "RX_BACKUP_9", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_9", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_9", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_9", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_9", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_9", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_9", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_9", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_9", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_9", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_9", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_9", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE10_CTRL_REG0[] = {
+	 { "RX_BACKUP_10", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_10", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_10", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_10", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_10", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_10", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_10", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_10", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_10", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_10", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_10", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_10", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE11_CTRL_REG0[] = {
+	 { "RX_BACKUP_11", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_11", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_11", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_11", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_11", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_11", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_11", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_11", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_11", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_11", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_11", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_11", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE12_CTRL_REG0[] = {
+	 { "RX_BACKUP_12", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_12", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_12", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_12", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_12", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_12", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_12", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_12", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_12", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_12", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_12", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_12", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE13_CTRL_REG0[] = {
+	 { "RX_BACKUP_13", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_13", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_13", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_13", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_13", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_13", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_13", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_13", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_13", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_13", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_13", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_13", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE14_CTRL_REG0[] = {
+	 { "RX_BACKUP_14", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_14", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_14", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_14", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_14", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_14", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_14", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_14", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_14", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_14", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_14", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_14", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE15_CTRL_REG0[] = {
+	 { "RX_BACKUP_15", 0, 7, &umr_bitfield_default },
+	 { "RX_DBG_ANALOG_SEL_15", 10, 11, &umr_bitfield_default },
+	 { "RX_TST_BSCAN_EN_15", 12, 12, &umr_bitfield_default },
+	 { "RX_CFG_OVR_PWRSF_15", 13, 13, &umr_bitfield_default },
+	 { "RX_TERM_EN_15", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "RXPWR_15", 0, 2, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_15", 3, 3, &umr_bitfield_default },
+	 { "REQUESTTRK_15", 6, 6, &umr_bitfield_default },
+	 { "ENABLEFOM_15", 7, 7, &umr_bitfield_default },
+	 { "REQUESTFOM_15", 8, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_15", 9, 9, &umr_bitfield_default },
+	 { "RXEYEFOM_15", 10, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_CTRL_REG0[] = {
+	 { "TX_DRV_DATA_ASRT_DLY_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_DSRT_DLY_VAL", 3, 5, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN1", 8, 10, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN2", 11, 13, &umr_bitfield_default },
+	 { "TX_CFG_RPTR_RST_VAL_GEN3", 14, 16, &umr_bitfield_default },
+	 { "TX_STAGGER_CTRL", 17, 18, &umr_bitfield_default },
+	 { "TX_DATA_CLK_GATING", 19, 19, &umr_bitfield_default },
+	 { "TX_PRESET_TABLE_BYPASS", 20, 20, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_EN", 21, 21, &umr_bitfield_default },
+	 { "TX_COEFF_ROUND_DIR_VER", 22, 22, &umr_bitfield_default },
+	 { "TX_DCLK_EN_LSX_ALWAYS_ON", 23, 23, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_IN_PS4", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_LANE_SKEW_CTRL[] = {
+	 { "TX_CFG_GROUPX1_EN_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_6", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_7", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_8", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_9", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_10", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_11", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_12", 12, 12, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_13", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_14", 14, 14, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_15", 15, 15, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L0T1", 16, 16, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L2T3", 17, 17, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L4T5", 18, 18, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L6T7", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L8T9", 20, 20, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L10T11", 21, 21, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L12T13", 22, 22, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_L14T15", 23, 23, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L0T3", 24, 24, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L4T7", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L8T11", 26, 26, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_L12T15", 27, 27, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L0T7", 28, 28, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_L8T15", 29, 29, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_L0T15", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_SCI_STAT_OVRD_REG0[] = {
+	 { "IGNR_TXPWR_CBI_UPDT_L0T3", 0, 0, &umr_bitfield_default },
+	 { "IGNR_TXPWR_CBI_UPDT_L4T7", 1, 1, &umr_bitfield_default },
+	 { "IGNR_TXPWR_CBI_UPDT_L8T11", 2, 2, &umr_bitfield_default },
+	 { "IGNR_TXPWR_CBI_UPDT_L12T15", 3, 3, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_CBI_UPDT_L0T3", 8, 8, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_CBI_UPDT_L4T7", 9, 9, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_CBI_UPDT_L8T11", 10, 10, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENTID_CBI_UPDT_L12T15", 11, 11, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_CBI_UPDT_L0T3", 12, 12, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_CBI_UPDT_L4T7", 13, 13, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_CBI_UPDT_L8T11", 14, 14, &umr_bitfield_default },
+	 { "IGNR_COEFFICIENT_CBI_UPDT_L12T15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0[] = {
+	 { "ACCEPT_ENTRY_0", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_1", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_2", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_3", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_4", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_5", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_6", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_7", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_8", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_9", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_10", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_11", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_12", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_13", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_14", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_15", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_16", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_17", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_18", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_19", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_20", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_21", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_22", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_23", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_24", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_25", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_26", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_27", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_28", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_29", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_30", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_31", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1[] = {
+	 { "ACCEPT_ENTRY_32", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_33", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_34", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_35", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_36", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_37", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_38", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_39", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_40", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_41", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_42", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_43", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_44", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_45", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_46", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_47", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_48", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_49", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_50", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_51", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_52", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_53", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_54", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_55", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_56", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_57", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_58", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_59", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_60", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_61", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_62", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_63", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2[] = {
+	 { "ACCEPT_ENTRY_64", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_65", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_66", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_67", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_68", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_69", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_70", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_71", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_72", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_73", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_74", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_75", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_76", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_77", 13, 13, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_78", 14, 14, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_79", 15, 15, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_80", 16, 16, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_81", 17, 17, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_82", 18, 18, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_83", 19, 19, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_84", 20, 20, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_85", 21, 21, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_86", 22, 22, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_87", 23, 23, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_88", 24, 24, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_89", 25, 25, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_90", 26, 26, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_91", 27, 27, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_92", 28, 28, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_93", 29, 29, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_94", 30, 30, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_95", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3[] = {
+	 { "ACCEPT_ENTRY_96", 0, 0, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_97", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_98", 2, 2, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_99", 3, 3, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_100", 4, 4, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_101", 5, 5, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_102", 6, 6, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_103", 7, 7, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_104", 8, 8, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_105", 9, 9, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_106", 10, 10, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_107", 11, 11, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_108", 12, 12, &umr_bitfield_default },
+	 { "ACCEPT_ENTRY_109", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG0[] = {
+	 { "TX_CFG_DCLK_DIV_OVRD_VAL", 0, 2, &umr_bitfield_default },
+	 { "TX_CFG_DCLK_DIV_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN1_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN1_OVRD_VAL", 9, 12, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_OVRD_EN", 13, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN1_OVRD_VAL", 14, 18, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_OVRD_EN", 19, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN1_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN1_OVRD_VAL", 26, 29, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_OVRD_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG1[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN1_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_OVRD_EN", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN1_OVRD_VAL", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_OVRD_EN", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN1_OVRD_VAL", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_OVRD_EN", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_PLLCLK_SEL_OVRD_EN", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_VAL", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_TCLK_DIV_OVRD_EN", 12, 12, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_VAL", 13, 13, &umr_bitfield_default },
+	 { "TX_CMDET_EN_OVRD_EN", 14, 14, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_VAL", 15, 24, &umr_bitfield_default },
+	 { "TX_DATA_IN_OVRD_EN", 25, 25, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_VAL", 26, 26, &umr_bitfield_default },
+	 { "TX_RPTR_RSTN_OVRD_EN", 27, 27, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_VAL", 28, 28, &umr_bitfield_default },
+	 { "TX_RXDET_EN_OVRD_EN", 29, 29, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_VAL", 30, 30, &umr_bitfield_default },
+	 { "TX_WPTR_RSTN_OVRD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG2[] = {
+	 { "TX_WRITE_EN_OVRD_VAL", 0, 0, &umr_bitfield_default },
+	 { "TX_WRITE_EN_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_VAL", 2, 2, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX1_EN_OVRD_EN", 3, 3, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX2_EN_OVRD_EN", 5, 5, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_VAL", 6, 6, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX4_EN_OVRD_EN", 7, 7, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX8_EN_OVRD_EN", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_VAL", 10, 10, &umr_bitfield_default },
+	 { "TX_CFG_GROUPX16_EN_OVRD_EN", 11, 11, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN2_OVRD_VAL", 12, 15, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN2_OVRD_VAL", 16, 19, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN2_OVRD_VAL", 20, 24, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN2_OVRD_VAL", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG3[] = {
+	 { "TX_CFG_DRV2_EN_GEN2_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_TAP_SEL_GEN2_OVRD_VAL", 4, 7, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN2_OVRD_VAL", 8, 8, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN2_OVRD_VAL", 9, 9, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_EN_GEN3_OVRD_VAL", 10, 13, &umr_bitfield_default },
+	 { "TX_CFG_DRV0_TAP_SEL_GEN3_OVRD_VAL", 14, 17, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_EN_GEN3_OVRD_VAL", 18, 22, &umr_bitfield_default },
+	 { "TX_CFG_DRV1_TAP_SEL_GEN3_OVRD_VAL", 23, 27, &umr_bitfield_default },
+	 { "TX_CFG_DRV2_EN_GEN3_OVRD_VAL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_GLB_OVRD_REG4[] = {
+	 { "TX_CFG_DRV2_TAP_SEL_GEN3_OVRD_VAL", 0, 3, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_EN_GEN3_OVRD_VAL", 4, 4, &umr_bitfield_default },
+	 { "TX_CFG_DRVX_TAP_SEL_GEN3_OVRD_VAL", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE0_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_0", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_0", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_0", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE0_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_0", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_0", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_0", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_0", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_0", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_0", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_0", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE1_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_1", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_1", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_1", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE1_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_1", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_1", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_1", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_1", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_1", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_1", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_1", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE2_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_2", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_2", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE2_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_2", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_2", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_2", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_2", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_2", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_2", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_2", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE3_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_3", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_3", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_3", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE3_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_3", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_3", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_3", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_3", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_3", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_3", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_3", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE4_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_4", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_4", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_4", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE4_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_4", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_4", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_4", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_4", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_4", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_4", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_4", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE5_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_5", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_5", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_5", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE5_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_5", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_5", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_5", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_5", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_5", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_5", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_5", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_5", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE6_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_6", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_6", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_6", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE6_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_6", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_6", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_6", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_6", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_6", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_6", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_6", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_6", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE7_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_7", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_7", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_7", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE7_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_7", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_7", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_7", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_7", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_7", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_7", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_7", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_7", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE8_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_8", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_8", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_8", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE8_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_8", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_8", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_8", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_8", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_8", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_8", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_8", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_8", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_8", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_8", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_8", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_8", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_8", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE9_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_9", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_9", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_9", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE9_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_9", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_9", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_9", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_9", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_9", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_9", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_9", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_9", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_9", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_9", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_9", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_9", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_9", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE10_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_10", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_10", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_10", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE10_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_10", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_10", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_10", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_10", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_10", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_10", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_10", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_10", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_10", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_10", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_10", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_10", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_10", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE11_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_11", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_11", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_11", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE11_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_11", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_11", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_11", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_11", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_11", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_11", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_11", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_11", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_11", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_11", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_11", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_11", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_11", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE12_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_12", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_12", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_12", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE12_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_12", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_12", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_12", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_12", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_12", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_12", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_12", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_12", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_12", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_12", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_12", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_12", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_12", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE13_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_13", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_13", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_13", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE13_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_13", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_13", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_13", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_13", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_13", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_13", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_13", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_13", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_13", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_13", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_13", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_13", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_13", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE14_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_14", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_14", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_14", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE14_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_14", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_14", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_14", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_14", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_14", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_14", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_14", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_14", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_14", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_14", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_14", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_14", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_14", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE15_CTRL_REG0[] = {
+	 { "TX_CFG_DISPCLK_MODE_15", 0, 0, &umr_bitfield_default },
+	 { "TX_CFG_INV_DATA_15", 1, 1, &umr_bitfield_default },
+	 { "TX_CFG_SWING_BOOST_EN_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DBG_PRBS_EN_15", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE15_OVRD_REG0[] = {
+	 { "TX_DCLK_EN_OVRD_VAL_15", 0, 0, &umr_bitfield_default },
+	 { "TX_DCLK_EN_OVRD_EN_15", 1, 1, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_VAL_15", 2, 2, &umr_bitfield_default },
+	 { "TX_DRV_DATA_EN_OVRD_EN_15", 3, 3, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_VAL_15", 4, 4, &umr_bitfield_default },
+	 { "TX_DRV_PWRON_OVRD_EN_15", 5, 5, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_VAL_15", 6, 6, &umr_bitfield_default },
+	 { "TX_FRONTEND_PWRON_OVRD_EN_15", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0[] = {
+	 { "TXPWR_15", 0, 2, &umr_bitfield_default },
+	 { "TXMARG_15", 4, 6, &umr_bitfield_default },
+	 { "DEEMPH_15", 7, 7, &umr_bitfield_default },
+	 { "COEFFICIENTID_15", 8, 9, &umr_bitfield_default },
+	 { "COEFFICIENT_15", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_SNOOP_REG[] = {
+	 { "REG_SNOOP_ARBITER", 0, 0, &umr_bitfield_default },
+	 { "REG_SNOOP_ALLMASTER", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MASK[] = {
+	 { "MSI_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_PENDING[] = {
+	 { "MSI_PENDING", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_PENDING_64[] = {
+	 { "MSI_PENDING_64", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLATENCY[] = {
+	 { "LATENCY_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHEADER[] = {
+	 { "HEADER_TYPE", 0, 6, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIST[] = {
+	 { "BIST_COMP", 0, 3, &umr_bitfield_default },
+	 { "BIST_STRT", 6, 6, &umr_bitfield_default },
+	 { "BIST_CAP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSIX_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSIX_TABLE[] = {
+	 { "MSIX_TABLE_BIR", 0, 2, &umr_bitfield_default },
+	 { "MSIX_TABLE_OFFSET", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSIX_PBA[] = {
+	 { "MSIX_PBA_BIR", 0, 2, &umr_bitfield_default },
+	 { "MSIX_PBA_OFFSET", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_1[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_2[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_0[] = {
+	 { "BIOS_SCRATCH_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_1[] = {
+	 { "BIOS_SCRATCH_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_2[] = {
+	 { "BIOS_SCRATCH_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_3[] = {
+	 { "BIOS_SCRATCH_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_4[] = {
+	 { "BIOS_SCRATCH_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_5[] = {
+	 { "BIOS_SCRATCH_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_6[] = {
+	 { "BIOS_SCRATCH_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_7[] = {
+	 { "BIOS_SCRATCH_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_8[] = {
+	 { "BIOS_SCRATCH_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_9[] = {
+	 { "BIOS_SCRATCH_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_10[] = {
+	 { "BIOS_SCRATCH_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_11[] = {
+	 { "BIOS_SCRATCH_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_12[] = {
+	 { "BIOS_SCRATCH_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_13[] = {
+	 { "BIOS_SCRATCH_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_14[] = {
+	 { "BIOS_SCRATCH_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_15[] = {
+	 { "BIOS_SCRATCH_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_INDEX_HI[] = {
+	 { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT0_ADDR_LO[] = {
+	 { "MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT0_ADDR_HI[] = {
+	 { "MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT0_MSG_DATA[] = {
+	 { "MSG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT0_CONTROL[] = {
+	 { "MASK_BIT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT1_ADDR_LO[] = {
+	 { "MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT1_ADDR_HI[] = {
+	 { "MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT1_MSG_DATA[] = {
+	 { "MSG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT1_CONTROL[] = {
+	 { "MASK_BIT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT2_ADDR_LO[] = {
+	 { "MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT2_ADDR_HI[] = {
+	 { "MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT2_MSG_DATA[] = {
+	 { "MSG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT2_CONTROL[] = {
+	 { "MASK_BIT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT3_ADDR_LO[] = {
+	 { "MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT3_ADDR_HI[] = {
+	 { "MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT3_MSG_DATA[] = {
+	 { "MSG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_VECT3_CONTROL[] = {
+	 { "MASK_BIT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIEMSIX_PBA[] = {
+	 { "MSIX_PENDING_BITS", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_4[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_5[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR1_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR1_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR2_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR2_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR3_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR3_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR4_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR4_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR5_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR5_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR6_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR6_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_6[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_DATA_SELECT[] = {
+	 { "DATA_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_DATA[] = {
+	 { "BASE_POWER", 0, 7, &umr_bitfield_default },
+	 { "DATA_SCALE", 8, 9, &umr_bitfield_default },
+	 { "PM_SUB_STATE", 10, 12, &umr_bitfield_default },
+	 { "PM_STATE", 13, 14, &umr_bitfield_default },
+	 { "TYPE", 15, 17, &umr_bitfield_default },
+	 { "POWER_RAIL", 18, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_CAP[] = {
+	 { "SYSTEM_ALLOCATED", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_CAP[] = {
+	 { "SUBSTATE_MAX", 0, 4, &umr_bitfield_default },
+	 { "TRANS_LAT_UNIT", 8, 9, &umr_bitfield_default },
+	 { "PWR_ALLOC_SCALE", 12, 13, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_0", 16, 23, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_LATENCY_INDICATOR[] = {
+	 { "TRANS_LAT_INDICATOR_BITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_STATUS[] = {
+	 { "SUBSTATE_STATUS", 0, 4, &umr_bitfield_default },
+	 { "SUBSTATE_CNTL_ENABLED", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_CNTL[] = {
+	 { "SUBSTATE_CNTL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_CNTL[] = {
+	 { "STU", 0, 4, &umr_bitfield_default },
+	 { "ATC_ENABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_CAP[] = {
+	 { "INVALIDATE_Q_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "PAGE_ALIGNED_REQUEST", 5, 5, &umr_bitfield_default },
+	 { "GLOBAL_INVALIDATE_SUPPORTED", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmADAPTER_ID[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_STATUS[] = {
+	 { "RESPONSE_FAILURE", 0, 0, &umr_bitfield_default },
+	 { "UNEXPECTED_PAGE_REQ_GRP_INDEX", 1, 1, &umr_bitfield_default },
+	 { "STOPPED", 8, 8, &umr_bitfield_default },
+	 { "PRG_RESPONSE_PASID_REQUIRED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_CNTL[] = {
+	 { "PRI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRI_RESET", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[] = {
+	 { "OUTSTAND_PAGE_REQ_CAPACITY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[] = {
+	 { "OUTSTAND_PAGE_REQ_ALLOC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_CNTL[] = {
+	 { "PASID_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PASID_EXE_PERMISSION_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "PASID_PRIV_MODE_SUPPORTED_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_CAP[] = {
+	 { "PASID_EXE_PERMISSION_SUPPORTED", 1, 1, &umr_bitfield_default },
+	 { "PASID_PRIV_MODE_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "MAX_PASID_WIDTH", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_CAP[] = {
+	 { "TPH_REQR_NO_ST_MODE_SUPPORTED", 0, 0, &umr_bitfield_default },
+	 { "TPH_REQR_INT_VEC_MODE_SUPPORTED", 1, 1, &umr_bitfield_default },
+	 { "TPH_REQR_DEV_SPC_MODE_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "TPH_REQR_EXTND_TPH_REQR_SUPPORED", 8, 8, &umr_bitfield_default },
+	 { "TPH_REQR_ST_TABLE_LOCATION", 9, 10, &umr_bitfield_default },
+	 { "TPH_REQR_ST_TABLE_SIZE", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_CNTL[] = {
+	 { "TPH_REQR_ST_MODE_SEL", 0, 2, &umr_bitfield_default },
+	 { "TPH_REQR_EN", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ENABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_WIN_SIZE_REQ", 8, 13, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmROM_BASE_ADDR[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_INDEX_2[] = {
+	 { "PCIE_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LTR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LTR_CAP[] = {
+	 { "LTR_MAX_S_LATENCY_VALUE", 0, 9, &umr_bitfield_default },
+	 { "LTR_MAX_S_LATENCY_SCALE", 10, 12, &umr_bitfield_default },
+	 { "LTR_MAX_NS_LATENCY_VALUE", 16, 25, &umr_bitfield_default },
+	 { "LTR_MAX_NS_LATENCY_SCALE", 26, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ARI_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ARI_CNTL[] = {
+	 { "ARI_MFVC_FUNC_GROUPS_EN", 0, 0, &umr_bitfield_default },
+	 { "ARI_ACS_FUNC_GROUPS_EN", 1, 1, &umr_bitfield_default },
+	 { "ARI_FUNCTION_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ARI_CAP[] = {
+	 { "ARI_MFVC_FUNC_GROUPS_CAP", 0, 0, &umr_bitfield_default },
+	 { "ARI_ACS_FUNC_GROUPS_CAP", 1, 1, &umr_bitfield_default },
+	 { "ARI_NEXT_FUNC_NUM", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_CAP[] = {
+	 { "SRIOV_VF_MIGRATION_CAP", 0, 0, &umr_bitfield_default },
+	 { "SRIOV_ARI_CAP_HIERARCHY_PRESERVED", 1, 1, &umr_bitfield_default },
+	 { "SRIOV_VF_MIGRATION_INTR_MSG_NUM", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_CONTROL[] = {
+	 { "SRIOV_VF_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SRIOV_VF_MIGRATION_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "SRIOV_VF_MIGRATION_INTR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "SRIOV_VF_MSE", 3, 3, &umr_bitfield_default },
+	 { "SRIOV_ARI_CAP_HIERARCHY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_STATUS[] = {
+	 { "SRIOV_VF_MIGRATION_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_INITIAL_VFS[] = {
+	 { "SRIOV_INITIAL_VFS", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_TOTAL_VFS[] = {
+	 { "SRIOV_TOTAL_VFS", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DATA_2[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_FUNC_DEP_LINK[] = {
+	 { "SRIOV_FUNC_DEP_LINK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_NUM_VFS[] = {
+	 { "SRIOV_NUM_VFS", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_FIRST_VF_OFFSET[] = {
+	 { "SRIOV_FIRST_VF_OFFSET", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_STRIDE[] = {
+	 { "SRIOV_VF_STRIDE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_DEVICE_ID[] = {
+	 { "SRIOV_VF_DEVICE_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE[] = {
+	 { "SRIOV_SUPPORTED_PAGE_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_SYSTEM_PAGE_SIZE[] = {
+	 { "SRIOV_SYSTEM_PAGE_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_BASE_ADDR_0[] = {
+	 { "VF_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_BASE_ADDR_1[] = {
+	 { "VF_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_BASE_ADDR_2[] = {
+	 { "VF_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_BASE_ADDR_3[] = {
+	 { "VF_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_BASE_ADDR_4[] = {
+	 { "VF_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_BASE_ADDR_5[] = {
+	 { "VF_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET[] = {
+	 { "SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_INDEX[] = {
+	 { "PCIE_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAX_LATENCY[] = {
+	 { "MAX_LAT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMIN_GRANT[] = {
+	 { "MIN_GNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_EFUSE[] = {
+	 { "PCIE_EFUSE_VALID", 1, 1, &umr_bitfield_default },
+	 { "PPHY_EFUSE_VALID", 2, 2, &umr_bitfield_default },
+	 { "SPARE_5_3_EFUSE0", 3, 5, &umr_bitfield_default },
+	 { "ISTRAP_ARBEN0", 6, 6, &umr_bitfield_default },
+	 { "SPARE_26_7_EFUSE0", 7, 26, &umr_bitfield_default },
+	 { "CHIP_BIF_MODE", 27, 27, &umr_bitfield_default },
+	 { "SPARE_31_28_EFUSE0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_EFUSE2[] = {
+	 { "SPARE_31_1_EFUSE2", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_EFUSE3[] = {
+	 { "STRAP_CEC_ID", 1, 16, &umr_bitfield_default },
+	 { "STRAP_BIF_KILL_GEN3", 17, 17, &umr_bitfield_default },
+	 { "SPARE_14_PCIEFUSE3", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_EFUSE4[] = {
+	 { "CC_WRITE_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "SPARE_3_PCIEFUSE4", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_F0_DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "STRAP_BIF_F0_MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "STRAP_BIF_F0_MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+	 { "STRAP_BIF_ATI_REV_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_EFUSE5[] = {
+	 { "STRAP_AZALIA_DID", 1, 16, &umr_bitfield_default },
+	 { "SPARE_16_PCIEFUSE5", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_EFUSE6[] = {
+	 { "STRAP_BIF_F0_SUPPORTED_PAGE_SIZES", 1, 16, &umr_bitfield_default },
+	 { "SPARE_15_PCIEFUSE6", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_EFUSE7[] = {
+	 { "STRAP_BIF_F0_SRIOV_VF_DEVICE_ID", 1, 16, &umr_bitfield_default },
+	 { "SPARE_15_PCIEFUSE7", 17, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/bif50_regs.i b/src/lib/ip/bif50_regs.i
new file mode 100644
index 0000000..fc0d738
--- /dev/null
+++ b/src/lib/ip/bif50_regs.i
@@ -0,0 +1,1021 @@
+	{ "mmVENDOR_ID", REG_MMIO, 0x0, &mmVENDOR_ID[0], sizeof(mmVENDOR_ID)/sizeof(mmVENDOR_ID[0]), 0, 0 },
+	{ "mmMM_INDEX", REG_MMIO, 0x0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
+	{ "mmMM_DATA", REG_MMIO, 0x1, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
+	{ "mmSTATUS", REG_MMIO, 0x1, &mmSTATUS[0], sizeof(mmSTATUS)/sizeof(mmSTATUS[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV", REG_MMIO, 0x100, &mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV[0], sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV)/sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV[0]), 0, 0 },
+	{ "ixPCIEP_RESERVED", REG_SMC, 0x10010000, &ixPCIEP_RESERVED[0], sizeof(ixPCIEP_RESERVED)/sizeof(ixPCIEP_RESERVED[0]), 0, 0 },
+	{ "ixPCIEP_SCRATCH", REG_SMC, 0x10010001, &ixPCIEP_SCRATCH[0], sizeof(ixPCIEP_SCRATCH)/sizeof(ixPCIEP_SCRATCH[0]), 0, 0 },
+	{ "ixPCIEP_HW_DEBUG", REG_SMC, 0x10010002, &ixPCIEP_HW_DEBUG[0], sizeof(ixPCIEP_HW_DEBUG)/sizeof(ixPCIEP_HW_DEBUG[0]), 0, 0 },
+	{ "ixPCIEP_PORT_CNTL", REG_SMC, 0x10010010, &ixPCIEP_PORT_CNTL[0], sizeof(ixPCIEP_PORT_CNTL)/sizeof(ixPCIEP_PORT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_CNTL", REG_SMC, 0x10010020, &ixPCIE_TX_CNTL[0], sizeof(ixPCIE_TX_CNTL)/sizeof(ixPCIE_TX_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_REQUESTER_ID", REG_SMC, 0x10010021, &ixPCIE_TX_REQUESTER_ID[0], sizeof(ixPCIE_TX_REQUESTER_ID)/sizeof(ixPCIE_TX_REQUESTER_ID[0]), 0, 0 },
+	{ "ixPCIE_TX_VENDOR_SPECIFIC", REG_SMC, 0x10010022, &ixPCIE_TX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_TX_VENDOR_SPECIFIC)/sizeof(ixPCIE_TX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "ixPCIE_TX_REQUEST_NUM_CNTL", REG_SMC, 0x10010023, &ixPCIE_TX_REQUEST_NUM_CNTL[0], sizeof(ixPCIE_TX_REQUEST_NUM_CNTL)/sizeof(ixPCIE_TX_REQUEST_NUM_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_SEQ", REG_SMC, 0x10010024, &ixPCIE_TX_SEQ[0], sizeof(ixPCIE_TX_SEQ)/sizeof(ixPCIE_TX_SEQ[0]), 0, 0 },
+	{ "ixPCIE_TX_REPLAY", REG_SMC, 0x10010025, &ixPCIE_TX_REPLAY[0], sizeof(ixPCIE_TX_REPLAY)/sizeof(ixPCIE_TX_REPLAY[0]), 0, 0 },
+	{ "ixPCIE_TX_ACK_LATENCY_LIMIT", REG_SMC, 0x10010026, &ixPCIE_TX_ACK_LATENCY_LIMIT[0], sizeof(ixPCIE_TX_ACK_LATENCY_LIMIT)/sizeof(ixPCIE_TX_ACK_LATENCY_LIMIT[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_P", REG_SMC, 0x10010030, &ixPCIE_TX_CREDITS_ADVT_P[0], sizeof(ixPCIE_TX_CREDITS_ADVT_P)/sizeof(ixPCIE_TX_CREDITS_ADVT_P[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_NP", REG_SMC, 0x10010031, &ixPCIE_TX_CREDITS_ADVT_NP[0], sizeof(ixPCIE_TX_CREDITS_ADVT_NP)/sizeof(ixPCIE_TX_CREDITS_ADVT_NP[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_CPL", REG_SMC, 0x10010032, &ixPCIE_TX_CREDITS_ADVT_CPL[0], sizeof(ixPCIE_TX_CREDITS_ADVT_CPL)/sizeof(ixPCIE_TX_CREDITS_ADVT_CPL[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_P", REG_SMC, 0x10010033, &ixPCIE_TX_CREDITS_INIT_P[0], sizeof(ixPCIE_TX_CREDITS_INIT_P)/sizeof(ixPCIE_TX_CREDITS_INIT_P[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_NP", REG_SMC, 0x10010034, &ixPCIE_TX_CREDITS_INIT_NP[0], sizeof(ixPCIE_TX_CREDITS_INIT_NP)/sizeof(ixPCIE_TX_CREDITS_INIT_NP[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_CPL", REG_SMC, 0x10010035, &ixPCIE_TX_CREDITS_INIT_CPL[0], sizeof(ixPCIE_TX_CREDITS_INIT_CPL)/sizeof(ixPCIE_TX_CREDITS_INIT_CPL[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_STATUS", REG_SMC, 0x10010036, &ixPCIE_TX_CREDITS_STATUS[0], sizeof(ixPCIE_TX_CREDITS_STATUS)/sizeof(ixPCIE_TX_CREDITS_STATUS[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_FCU_THRESHOLD", REG_SMC, 0x10010037, &ixPCIE_TX_CREDITS_FCU_THRESHOLD[0], sizeof(ixPCIE_TX_CREDITS_FCU_THRESHOLD)/sizeof(ixPCIE_TX_CREDITS_FCU_THRESHOLD[0]), 0, 0 },
+	{ "ixPCIE_P_PORT_LANE_STATUS", REG_SMC, 0x10010050, &ixPCIE_P_PORT_LANE_STATUS[0], sizeof(ixPCIE_P_PORT_LANE_STATUS)/sizeof(ixPCIE_P_PORT_LANE_STATUS[0]), 0, 0 },
+	{ "ixPCIE_FC_P", REG_SMC, 0x10010060, &ixPCIE_FC_P[0], sizeof(ixPCIE_FC_P)/sizeof(ixPCIE_FC_P[0]), 0, 0 },
+	{ "ixPCIE_FC_NP", REG_SMC, 0x10010061, &ixPCIE_FC_NP[0], sizeof(ixPCIE_FC_NP)/sizeof(ixPCIE_FC_NP[0]), 0, 0 },
+	{ "ixPCIE_FC_CPL", REG_SMC, 0x10010062, &ixPCIE_FC_CPL[0], sizeof(ixPCIE_FC_CPL)/sizeof(ixPCIE_FC_CPL[0]), 0, 0 },
+	{ "ixPCIE_ERR_CNTL", REG_SMC, 0x1001006a, &ixPCIE_ERR_CNTL[0], sizeof(ixPCIE_ERR_CNTL)/sizeof(ixPCIE_ERR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL", REG_SMC, 0x10010070, &ixPCIE_RX_CNTL[0], sizeof(ixPCIE_RX_CNTL)/sizeof(ixPCIE_RX_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_EXPECTED_SEQNUM", REG_SMC, 0x10010071, &ixPCIE_RX_EXPECTED_SEQNUM[0], sizeof(ixPCIE_RX_EXPECTED_SEQNUM)/sizeof(ixPCIE_RX_EXPECTED_SEQNUM[0]), 0, 0 },
+	{ "ixPCIE_RX_VENDOR_SPECIFIC", REG_SMC, 0x10010072, &ixPCIE_RX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_RX_VENDOR_SPECIFIC)/sizeof(ixPCIE_RX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL3", REG_SMC, 0x10010074, &ixPCIE_RX_CNTL3[0], sizeof(ixPCIE_RX_CNTL3)/sizeof(ixPCIE_RX_CNTL3[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_P", REG_SMC, 0x10010080, &ixPCIE_RX_CREDITS_ALLOCATED_P[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_P)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_P[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_NP", REG_SMC, 0x10010081, &ixPCIE_RX_CREDITS_ALLOCATED_NP[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_NP)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_NP[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_CPL", REG_SMC, 0x10010082, &ixPCIE_RX_CREDITS_ALLOCATED_CPL[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_CPL)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_CPL[0]), 0, 0 },
+	{ "ixPCIEP_ERROR_INJECT_PHYSICAL", REG_SMC, 0x10010083, &ixPCIEP_ERROR_INJECT_PHYSICAL[0], sizeof(ixPCIEP_ERROR_INJECT_PHYSICAL)/sizeof(ixPCIEP_ERROR_INJECT_PHYSICAL[0]), 0, 0 },
+	{ "ixPCIEP_ERROR_INJECT_TRANSACTION", REG_SMC, 0x10010084, &ixPCIEP_ERROR_INJECT_TRANSACTION[0], sizeof(ixPCIEP_ERROR_INJECT_TRANSACTION)/sizeof(ixPCIEP_ERROR_INJECT_TRANSACTION[0]), 0, 0 },
+	{ "ixPCIEP_SRIOV_PRIV_CTRL", REG_SMC, 0x10010085, &ixPCIEP_SRIOV_PRIV_CTRL[0], sizeof(ixPCIEP_SRIOV_PRIV_CTRL)/sizeof(ixPCIEP_SRIOV_PRIV_CTRL[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL", REG_SMC, 0x100100a0, &ixPCIE_LC_CNTL[0], sizeof(ixPCIE_LC_CNTL)/sizeof(ixPCIE_LC_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_TRAINING_CNTL", REG_SMC, 0x100100a1, &ixPCIE_LC_TRAINING_CNTL[0], sizeof(ixPCIE_LC_TRAINING_CNTL)/sizeof(ixPCIE_LC_TRAINING_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_LINK_WIDTH_CNTL", REG_SMC, 0x100100a2, &ixPCIE_LC_LINK_WIDTH_CNTL[0], sizeof(ixPCIE_LC_LINK_WIDTH_CNTL)/sizeof(ixPCIE_LC_LINK_WIDTH_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_N_FTS_CNTL", REG_SMC, 0x100100a3, &ixPCIE_LC_N_FTS_CNTL[0], sizeof(ixPCIE_LC_N_FTS_CNTL)/sizeof(ixPCIE_LC_N_FTS_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_SPEED_CNTL", REG_SMC, 0x100100a4, &ixPCIE_LC_SPEED_CNTL[0], sizeof(ixPCIE_LC_SPEED_CNTL)/sizeof(ixPCIE_LC_SPEED_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE0", REG_SMC, 0x100100a5, &ixPCIE_LC_STATE0[0], sizeof(ixPCIE_LC_STATE0)/sizeof(ixPCIE_LC_STATE0[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE1", REG_SMC, 0x100100a6, &ixPCIE_LC_STATE1[0], sizeof(ixPCIE_LC_STATE1)/sizeof(ixPCIE_LC_STATE1[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE2", REG_SMC, 0x100100a7, &ixPCIE_LC_STATE2[0], sizeof(ixPCIE_LC_STATE2)/sizeof(ixPCIE_LC_STATE2[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE3", REG_SMC, 0x100100a8, &ixPCIE_LC_STATE3[0], sizeof(ixPCIE_LC_STATE3)/sizeof(ixPCIE_LC_STATE3[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE4", REG_SMC, 0x100100a9, &ixPCIE_LC_STATE4[0], sizeof(ixPCIE_LC_STATE4)/sizeof(ixPCIE_LC_STATE4[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE5", REG_SMC, 0x100100aa, &ixPCIE_LC_STATE5[0], sizeof(ixPCIE_LC_STATE5)/sizeof(ixPCIE_LC_STATE5[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL2", REG_SMC, 0x100100b1, &ixPCIE_LC_CNTL2[0], sizeof(ixPCIE_LC_CNTL2)/sizeof(ixPCIE_LC_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_LC_BW_CHANGE_CNTL", REG_SMC, 0x100100b2, &ixPCIE_LC_BW_CHANGE_CNTL[0], sizeof(ixPCIE_LC_BW_CHANGE_CNTL)/sizeof(ixPCIE_LC_BW_CHANGE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_CDR_CNTL", REG_SMC, 0x100100b3, &ixPCIE_LC_CDR_CNTL[0], sizeof(ixPCIE_LC_CDR_CNTL)/sizeof(ixPCIE_LC_CDR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_LANE_CNTL", REG_SMC, 0x100100b4, &ixPCIE_LC_LANE_CNTL[0], sizeof(ixPCIE_LC_LANE_CNTL)/sizeof(ixPCIE_LC_LANE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL3", REG_SMC, 0x100100b5, &ixPCIE_LC_CNTL3[0], sizeof(ixPCIE_LC_CNTL3)/sizeof(ixPCIE_LC_CNTL3[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL4", REG_SMC, 0x100100b6, &ixPCIE_LC_CNTL4[0], sizeof(ixPCIE_LC_CNTL4)/sizeof(ixPCIE_LC_CNTL4[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL5", REG_SMC, 0x100100b7, &ixPCIE_LC_CNTL5[0], sizeof(ixPCIE_LC_CNTL5)/sizeof(ixPCIE_LC_CNTL5[0]), 0, 0 },
+	{ "ixPCIE_LC_FORCE_COEFF", REG_SMC, 0x100100b8, &ixPCIE_LC_FORCE_COEFF[0], sizeof(ixPCIE_LC_FORCE_COEFF)/sizeof(ixPCIE_LC_FORCE_COEFF[0]), 0, 0 },
+	{ "ixPCIE_LC_BEST_EQ_SETTINGS", REG_SMC, 0x100100b9, &ixPCIE_LC_BEST_EQ_SETTINGS[0], sizeof(ixPCIE_LC_BEST_EQ_SETTINGS)/sizeof(ixPCIE_LC_BEST_EQ_SETTINGS[0]), 0, 0 },
+	{ "ixPCIE_LC_FORCE_EQ_REQ_COEFF", REG_SMC, 0x100100ba, &ixPCIE_LC_FORCE_EQ_REQ_COEFF[0], sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF)/sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL6", REG_SMC, 0x100100bb, &ixPCIE_LC_CNTL6[0], sizeof(ixPCIE_LC_CNTL6)/sizeof(ixPCIE_LC_CNTL6[0]), 0, 0 },
+	{ "ixPCIEP_STRAP_LC", REG_SMC, 0x100100c0, &ixPCIEP_STRAP_LC[0], sizeof(ixPCIEP_STRAP_LC)/sizeof(ixPCIEP_STRAP_LC[0]), 0, 0 },
+	{ "ixPCIEP_STRAP_MISC", REG_SMC, 0x100100c1, &ixPCIEP_STRAP_MISC[0], sizeof(ixPCIEP_STRAP_MISC)/sizeof(ixPCIEP_STRAP_MISC[0]), 0, 0 },
+	{ "ixPCIEP_BCH_ECC_CNTL", REG_SMC, 0x100100d0, &ixPCIEP_BCH_ECC_CNTL[0], sizeof(ixPCIEP_BCH_ECC_CNTL)/sizeof(ixPCIEP_BCH_ECC_CNTL[0]), 0, 0 },
+	{ "ixPCIEP_HPGI_PRIVATE", REG_SMC, 0x100100d2, &ixPCIEP_HPGI_PRIVATE[0], sizeof(ixPCIEP_HPGI_PRIVATE)/sizeof(ixPCIEP_HPGI_PRIVATE[0]), 0, 0 },
+	{ "ixPCIEP_HPGI", REG_SMC, 0x100100da, &ixPCIEP_HPGI[0], sizeof(ixPCIEP_HPGI)/sizeof(ixPCIEP_HPGI[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV", REG_MMIO, 0x101, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW", REG_MMIO, 0x102, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC", REG_MMIO, 0x103, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_CTRL_N_FUNC[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS", REG_MMIO, 0x104, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CMD_STATUS[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL", REG_MMIO, 0x105, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION", REG_MMIO, 0x106, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_NOTIFICATION[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS", REG_MMIO, 0x107, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_INIT_STATUS[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT", REG_MMIO, 0x108, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB", REG_MMIO, 0x109, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS", REG_MMIO, 0x10a, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VM_BUSY_STATUS[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS", REG_MMIO, 0x10b, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB", REG_MMIO, 0x10c, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB", REG_MMIO, 0x10d, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB", REG_MMIO, 0x10e, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB", REG_MMIO, 0x10f, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB", REG_MMIO, 0x110, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB[0]), 0, 0 },
+	{ "ixPB0_PIF_SCRATCH", REG_SMC, 0x1100001, &ixPB0_PIF_SCRATCH[0], sizeof(ixPB0_PIF_SCRATCH)/sizeof(ixPB0_PIF_SCRATCH[0]), 0, 0 },
+	{ "ixPB0_PIF_HW_DEBUG", REG_SMC, 0x1100002, &ixPB0_PIF_HW_DEBUG[0], sizeof(ixPB0_PIF_HW_DEBUG)/sizeof(ixPB0_PIF_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB0_PIF_STRAP_0", REG_SMC, 0x1100003, &ixPB0_PIF_STRAP_0[0], sizeof(ixPB0_PIF_STRAP_0)/sizeof(ixPB0_PIF_STRAP_0[0]), 0, 0 },
+	{ "ixPB0_PIF_CTRL", REG_SMC, 0x1100004, &ixPB0_PIF_CTRL[0], sizeof(ixPB0_PIF_CTRL)/sizeof(ixPB0_PIF_CTRL[0]), 0, 0 },
+	{ "ixPB0_PIF_TX_CTRL", REG_SMC, 0x1100008, &ixPB0_PIF_TX_CTRL[0], sizeof(ixPB0_PIF_TX_CTRL)/sizeof(ixPB0_PIF_TX_CTRL[0]), 0, 0 },
+	{ "ixPB0_PIF_TX_CTRL2", REG_SMC, 0x1100009, &ixPB0_PIF_TX_CTRL2[0], sizeof(ixPB0_PIF_TX_CTRL2)/sizeof(ixPB0_PIF_TX_CTRL2[0]), 0, 0 },
+	{ "ixPB0_PIF_RX_CTRL", REG_SMC, 0x110000a, &ixPB0_PIF_RX_CTRL[0], sizeof(ixPB0_PIF_RX_CTRL)/sizeof(ixPB0_PIF_RX_CTRL[0]), 0, 0 },
+	{ "ixPB0_PIF_RX_CTRL2", REG_SMC, 0x110000b, &ixPB0_PIF_RX_CTRL2[0], sizeof(ixPB0_PIF_RX_CTRL2)/sizeof(ixPB0_PIF_RX_CTRL2[0]), 0, 0 },
+	{ "ixPB0_PIF_GLB_OVRD", REG_SMC, 0x110000c, &ixPB0_PIF_GLB_OVRD[0], sizeof(ixPB0_PIF_GLB_OVRD)/sizeof(ixPB0_PIF_GLB_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_GLB_OVRD2", REG_SMC, 0x110000d, &ixPB0_PIF_GLB_OVRD2[0], sizeof(ixPB0_PIF_GLB_OVRD2)/sizeof(ixPB0_PIF_GLB_OVRD2[0]), 0, 0 },
+	{ "ixPB0_PIF_BIF_CMD_STATUS", REG_SMC, 0x1100010, &ixPB0_PIF_BIF_CMD_STATUS[0], sizeof(ixPB0_PIF_BIF_CMD_STATUS)/sizeof(ixPB0_PIF_BIF_CMD_STATUS[0]), 0, 0 },
+	{ "ixPB0_PIF_CMD_BUS_CTRL", REG_SMC, 0x1100011, &ixPB0_PIF_CMD_BUS_CTRL[0], sizeof(ixPB0_PIF_CMD_BUS_CTRL)/sizeof(ixPB0_PIF_CMD_BUS_CTRL[0]), 0, 0 },
+	{ "ixPB0_PIF_CMD_BUS_GLB_OVRD", REG_SMC, 0x1100013, &ixPB0_PIF_CMD_BUS_GLB_OVRD[0], sizeof(ixPB0_PIF_CMD_BUS_GLB_OVRD)/sizeof(ixPB0_PIF_CMD_BUS_GLB_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE0_OVRD", REG_SMC, 0x1100014, &ixPB0_PIF_LANE0_OVRD[0], sizeof(ixPB0_PIF_LANE0_OVRD)/sizeof(ixPB0_PIF_LANE0_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE0_OVRD2", REG_SMC, 0x1100015, &ixPB0_PIF_LANE0_OVRD2[0], sizeof(ixPB0_PIF_LANE0_OVRD2)/sizeof(ixPB0_PIF_LANE0_OVRD2[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE1_OVRD", REG_SMC, 0x1100016, &ixPB0_PIF_LANE1_OVRD[0], sizeof(ixPB0_PIF_LANE1_OVRD)/sizeof(ixPB0_PIF_LANE1_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE1_OVRD2", REG_SMC, 0x1100017, &ixPB0_PIF_LANE1_OVRD2[0], sizeof(ixPB0_PIF_LANE1_OVRD2)/sizeof(ixPB0_PIF_LANE1_OVRD2[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE2_OVRD", REG_SMC, 0x1100018, &ixPB0_PIF_LANE2_OVRD[0], sizeof(ixPB0_PIF_LANE2_OVRD)/sizeof(ixPB0_PIF_LANE2_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE2_OVRD2", REG_SMC, 0x1100019, &ixPB0_PIF_LANE2_OVRD2[0], sizeof(ixPB0_PIF_LANE2_OVRD2)/sizeof(ixPB0_PIF_LANE2_OVRD2[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE3_OVRD", REG_SMC, 0x110001a, &ixPB0_PIF_LANE3_OVRD[0], sizeof(ixPB0_PIF_LANE3_OVRD)/sizeof(ixPB0_PIF_LANE3_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE3_OVRD2", REG_SMC, 0x110001b, &ixPB0_PIF_LANE3_OVRD2[0], sizeof(ixPB0_PIF_LANE3_OVRD2)/sizeof(ixPB0_PIF_LANE3_OVRD2[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE4_OVRD", REG_SMC, 0x110001c, &ixPB0_PIF_LANE4_OVRD[0], sizeof(ixPB0_PIF_LANE4_OVRD)/sizeof(ixPB0_PIF_LANE4_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE4_OVRD2", REG_SMC, 0x110001d, &ixPB0_PIF_LANE4_OVRD2[0], sizeof(ixPB0_PIF_LANE4_OVRD2)/sizeof(ixPB0_PIF_LANE4_OVRD2[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE5_OVRD", REG_SMC, 0x110001e, &ixPB0_PIF_LANE5_OVRD[0], sizeof(ixPB0_PIF_LANE5_OVRD)/sizeof(ixPB0_PIF_LANE5_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE5_OVRD2", REG_SMC, 0x110001f, &ixPB0_PIF_LANE5_OVRD2[0], sizeof(ixPB0_PIF_LANE5_OVRD2)/sizeof(ixPB0_PIF_LANE5_OVRD2[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE6_OVRD", REG_SMC, 0x1100020, &ixPB0_PIF_LANE6_OVRD[0], sizeof(ixPB0_PIF_LANE6_OVRD)/sizeof(ixPB0_PIF_LANE6_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE6_OVRD2", REG_SMC, 0x1100021, &ixPB0_PIF_LANE6_OVRD2[0], sizeof(ixPB0_PIF_LANE6_OVRD2)/sizeof(ixPB0_PIF_LANE6_OVRD2[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE7_OVRD", REG_SMC, 0x1100022, &ixPB0_PIF_LANE7_OVRD[0], sizeof(ixPB0_PIF_LANE7_OVRD)/sizeof(ixPB0_PIF_LANE7_OVRD[0]), 0, 0 },
+	{ "ixPB0_PIF_LANE7_OVRD2", REG_SMC, 0x1100023, &ixPB0_PIF_LANE7_OVRD2[0], sizeof(ixPB0_PIF_LANE7_OVRD2)/sizeof(ixPB0_PIF_LANE7_OVRD2[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB", REG_MMIO, 0x111, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB", REG_MMIO, 0x112, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB", REG_MMIO, 0x113, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB", REG_MMIO, 0x114, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB", REG_MMIO, 0x115, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB", REG_MMIO, 0x116, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB", REG_MMIO, 0x117, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB", REG_MMIO, 0x118, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB", REG_MMIO, 0x119, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB", REG_MMIO, 0x11a, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB", REG_MMIO, 0x11b, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT", REG_MMIO, 0x11c, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GPU_IDLE_LAT[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0", REG_MMIO, 0x11d, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE0[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1", REG_MMIO, 0x11e, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2", REG_MMIO, 0x11f, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE2[0]), 0, 0 },
+	{ "mmVENDOR_CAP_LIST", REG_MMIO, 0x12, &mmVENDOR_CAP_LIST[0], sizeof(mmVENDOR_CAP_LIST)/sizeof(mmVENDOR_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3", REG_MMIO, 0x120, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE3[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG0", REG_SMC, 0x1200004, &ixPB0_GLB_CTRL_REG0[0], sizeof(ixPB0_GLB_CTRL_REG0)/sizeof(ixPB0_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG1", REG_SMC, 0x1200008, &ixPB0_GLB_CTRL_REG1[0], sizeof(ixPB0_GLB_CTRL_REG1)/sizeof(ixPB0_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG2", REG_SMC, 0x120000c, &ixPB0_GLB_CTRL_REG2[0], sizeof(ixPB0_GLB_CTRL_REG2)/sizeof(ixPB0_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG3", REG_SMC, 0x1200010, &ixPB0_GLB_CTRL_REG3[0], sizeof(ixPB0_GLB_CTRL_REG3)/sizeof(ixPB0_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG4", REG_SMC, 0x1200014, &ixPB0_GLB_CTRL_REG4[0], sizeof(ixPB0_GLB_CTRL_REG4)/sizeof(ixPB0_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB0_GLB_CTRL_REG5", REG_SMC, 0x1200018, &ixPB0_GLB_CTRL_REG5[0], sizeof(ixPB0_GLB_CTRL_REG5)/sizeof(ixPB0_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x120001c, &ixPB0_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG1", REG_SMC, 0x1200020, &ixPB0_GLB_SCI_STAT_OVRD_REG1[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG1)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG2", REG_SMC, 0x1200024, &ixPB0_GLB_SCI_STAT_OVRD_REG2[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG2)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG3", REG_SMC, 0x1200028, &ixPB0_GLB_SCI_STAT_OVRD_REG3[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG3)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB0_GLB_SCI_STAT_OVRD_REG4", REG_SMC, 0x120002c, &ixPB0_GLB_SCI_STAT_OVRD_REG4[0], sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG4)/sizeof(ixPB0_GLB_SCI_STAT_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG0", REG_SMC, 0x1200030, &ixPB0_GLB_OVRD_REG0[0], sizeof(ixPB0_GLB_OVRD_REG0)/sizeof(ixPB0_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG1", REG_SMC, 0x1200034, &ixPB0_GLB_OVRD_REG1[0], sizeof(ixPB0_GLB_OVRD_REG1)/sizeof(ixPB0_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_GLB_OVRD_REG2", REG_SMC, 0x1200038, &ixPB0_GLB_OVRD_REG2[0], sizeof(ixPB0_GLB_OVRD_REG2)/sizeof(ixPB0_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_HW_DEBUG", REG_SMC, 0x1202004, &ixPB0_HW_DEBUG[0], sizeof(ixPB0_HW_DEBUG)/sizeof(ixPB0_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB0_STRAP_GLB_REG0", REG_SMC, 0x1202020, &ixPB0_STRAP_GLB_REG0[0], sizeof(ixPB0_STRAP_GLB_REG0)/sizeof(ixPB0_STRAP_GLB_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_TX_REG0", REG_SMC, 0x1202024, &ixPB0_STRAP_TX_REG0[0], sizeof(ixPB0_STRAP_TX_REG0)/sizeof(ixPB0_STRAP_TX_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_RX_REG0", REG_SMC, 0x1202028, &ixPB0_STRAP_RX_REG0[0], sizeof(ixPB0_STRAP_RX_REG0)/sizeof(ixPB0_STRAP_RX_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_RX_REG1", REG_SMC, 0x120202c, &ixPB0_STRAP_RX_REG1[0], sizeof(ixPB0_STRAP_RX_REG1)/sizeof(ixPB0_STRAP_RX_REG1[0]), 0, 0 },
+	{ "ixPB0_STRAP_PLL_REG0", REG_SMC, 0x1202030, &ixPB0_STRAP_PLL_REG0[0], sizeof(ixPB0_STRAP_PLL_REG0)/sizeof(ixPB0_STRAP_PLL_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_PIN_REG0", REG_SMC, 0x1202034, &ixPB0_STRAP_PIN_REG0[0], sizeof(ixPB0_STRAP_PIN_REG0)/sizeof(ixPB0_STRAP_PIN_REG0[0]), 0, 0 },
+	{ "ixPB0_STRAP_GLB_REG1", REG_SMC, 0x1202038, &ixPB0_STRAP_GLB_REG1[0], sizeof(ixPB0_STRAP_GLB_REG1)/sizeof(ixPB0_STRAP_GLB_REG1[0]), 0, 0 },
+	{ "ixPB0_STRAP_GLB_REG2", REG_SMC, 0x120203c, &ixPB0_STRAP_GLB_REG2[0], sizeof(ixPB0_STRAP_GLB_REG2)/sizeof(ixPB0_STRAP_GLB_REG2[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG0", REG_SMC, 0x1203000, &ixPB0_DFT_JIT_INJ_REG0[0], sizeof(ixPB0_DFT_JIT_INJ_REG0)/sizeof(ixPB0_DFT_JIT_INJ_REG0[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG1", REG_SMC, 0x1203004, &ixPB0_DFT_JIT_INJ_REG1[0], sizeof(ixPB0_DFT_JIT_INJ_REG1)/sizeof(ixPB0_DFT_JIT_INJ_REG1[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_REG2", REG_SMC, 0x1203008, &ixPB0_DFT_JIT_INJ_REG2[0], sizeof(ixPB0_DFT_JIT_INJ_REG2)/sizeof(ixPB0_DFT_JIT_INJ_REG2[0]), 0, 0 },
+	{ "ixPB0_DFT_DEBUG_CTRL_REG0", REG_SMC, 0x120300c, &ixPB0_DFT_DEBUG_CTRL_REG0[0], sizeof(ixPB0_DFT_DEBUG_CTRL_REG0)/sizeof(ixPB0_DFT_DEBUG_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_DFT_JIT_INJ_STAT_REG0", REG_SMC, 0x1203010, &ixPB0_DFT_JIT_INJ_STAT_REG0[0], sizeof(ixPB0_DFT_JIT_INJ_STAT_REG0)/sizeof(ixPB0_DFT_JIT_INJ_STAT_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO_GLB_CTRL_REG0", REG_SMC, 0x1204000, &ixPB0_PLL_RO_GLB_CTRL_REG0[0], sizeof(ixPB0_PLL_RO_GLB_CTRL_REG0)/sizeof(ixPB0_PLL_RO_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO_GLB_OVRD_REG0", REG_SMC, 0x1204010, NULL, 0, 0, 0 },
+	{ "ixPB0_PLL_RO0_CTRL_REG0", REG_SMC, 0x1204440, &ixPB0_PLL_RO0_CTRL_REG0[0], sizeof(ixPB0_PLL_RO0_CTRL_REG0)/sizeof(ixPB0_PLL_RO0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_OVRD_REG0", REG_SMC, 0x1204450, &ixPB0_PLL_RO0_OVRD_REG0[0], sizeof(ixPB0_PLL_RO0_OVRD_REG0)/sizeof(ixPB0_PLL_RO0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_OVRD_REG1", REG_SMC, 0x1204454, &ixPB0_PLL_RO0_OVRD_REG1[0], sizeof(ixPB0_PLL_RO0_OVRD_REG1)/sizeof(ixPB0_PLL_RO0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204460, &ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204464, &ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204468, &ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0", REG_SMC, 0x120446c, &ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_CTRL_REG0", REG_SMC, 0x1204480, &ixPB0_PLL_LC0_CTRL_REG0[0], sizeof(ixPB0_PLL_LC0_CTRL_REG0)/sizeof(ixPB0_PLL_LC0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_OVRD_REG0", REG_SMC, 0x1204490, &ixPB0_PLL_LC0_OVRD_REG0[0], sizeof(ixPB0_PLL_LC0_OVRD_REG0)/sizeof(ixPB0_PLL_LC0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_OVRD_REG1", REG_SMC, 0x1204494, &ixPB0_PLL_LC0_OVRD_REG1[0], sizeof(ixPB0_PLL_LC0_OVRD_REG1)/sizeof(ixPB0_PLL_LC0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204500, &ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204504, &ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0", REG_SMC, 0x1204508, &ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0", REG_SMC, 0x120450c, &ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG0", REG_SMC, 0x1206000, &ixPB0_RX_GLB_CTRL_REG0[0], sizeof(ixPB0_RX_GLB_CTRL_REG0)/sizeof(ixPB0_RX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG1", REG_SMC, 0x1206004, &ixPB0_RX_GLB_CTRL_REG1[0], sizeof(ixPB0_RX_GLB_CTRL_REG1)/sizeof(ixPB0_RX_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG2", REG_SMC, 0x1206008, &ixPB0_RX_GLB_CTRL_REG2[0], sizeof(ixPB0_RX_GLB_CTRL_REG2)/sizeof(ixPB0_RX_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG3", REG_SMC, 0x120600c, &ixPB0_RX_GLB_CTRL_REG3[0], sizeof(ixPB0_RX_GLB_CTRL_REG3)/sizeof(ixPB0_RX_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG4", REG_SMC, 0x1206010, &ixPB0_RX_GLB_CTRL_REG4[0], sizeof(ixPB0_RX_GLB_CTRL_REG4)/sizeof(ixPB0_RX_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG5", REG_SMC, 0x1206014, &ixPB0_RX_GLB_CTRL_REG5[0], sizeof(ixPB0_RX_GLB_CTRL_REG5)/sizeof(ixPB0_RX_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG6", REG_SMC, 0x1206018, &ixPB0_RX_GLB_CTRL_REG6[0], sizeof(ixPB0_RX_GLB_CTRL_REG6)/sizeof(ixPB0_RX_GLB_CTRL_REG6[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG7", REG_SMC, 0x120601c, &ixPB0_RX_GLB_CTRL_REG7[0], sizeof(ixPB0_RX_GLB_CTRL_REG7)/sizeof(ixPB0_RX_GLB_CTRL_REG7[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_CTRL_REG8", REG_SMC, 0x1206020, &ixPB0_RX_GLB_CTRL_REG8[0], sizeof(ixPB0_RX_GLB_CTRL_REG8)/sizeof(ixPB0_RX_GLB_CTRL_REG8[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206028, &ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_OVRD_REG0", REG_SMC, 0x1206030, &ixPB0_RX_GLB_OVRD_REG0[0], sizeof(ixPB0_RX_GLB_OVRD_REG0)/sizeof(ixPB0_RX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_GLB_OVRD_REG1", REG_SMC, 0x1206034, &ixPB0_RX_GLB_OVRD_REG1[0], sizeof(ixPB0_RX_GLB_OVRD_REG1)/sizeof(ixPB0_RX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_RX_LANE0_CTRL_REG0", REG_SMC, 0x1206440, &ixPB0_RX_LANE0_CTRL_REG0[0], sizeof(ixPB0_RX_LANE0_CTRL_REG0)/sizeof(ixPB0_RX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206448, &ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE1_CTRL_REG0", REG_SMC, 0x1206480, &ixPB0_RX_LANE1_CTRL_REG0[0], sizeof(ixPB0_RX_LANE1_CTRL_REG0)/sizeof(ixPB0_RX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206488, &ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE2_CTRL_REG0", REG_SMC, 0x1206500, &ixPB0_RX_LANE2_CTRL_REG0[0], sizeof(ixPB0_RX_LANE2_CTRL_REG0)/sizeof(ixPB0_RX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206508, &ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE3_CTRL_REG0", REG_SMC, 0x1206600, &ixPB0_RX_LANE3_CTRL_REG0[0], sizeof(ixPB0_RX_LANE3_CTRL_REG0)/sizeof(ixPB0_RX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206608, &ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE4_CTRL_REG0", REG_SMC, 0x1206800, &ixPB0_RX_LANE4_CTRL_REG0[0], sizeof(ixPB0_RX_LANE4_CTRL_REG0)/sizeof(ixPB0_RX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206848, &ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE5_CTRL_REG0", REG_SMC, 0x1206880, &ixPB0_RX_LANE5_CTRL_REG0[0], sizeof(ixPB0_RX_LANE5_CTRL_REG0)/sizeof(ixPB0_RX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206888, &ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE6_CTRL_REG0", REG_SMC, 0x1206900, &ixPB0_RX_LANE6_CTRL_REG0[0], sizeof(ixPB0_RX_LANE6_CTRL_REG0)/sizeof(ixPB0_RX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206908, &ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE7_CTRL_REG0", REG_SMC, 0x1206a00, &ixPB0_RX_LANE7_CTRL_REG0[0], sizeof(ixPB0_RX_LANE7_CTRL_REG0)/sizeof(ixPB0_RX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x1206a08, &ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE8_CTRL_REG0", REG_SMC, 0x1207440, &ixPB0_RX_LANE8_CTRL_REG0[0], sizeof(ixPB0_RX_LANE8_CTRL_REG0)/sizeof(ixPB0_RX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207448, &ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE9_CTRL_REG0", REG_SMC, 0x1207480, &ixPB0_RX_LANE9_CTRL_REG0[0], sizeof(ixPB0_RX_LANE9_CTRL_REG0)/sizeof(ixPB0_RX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207488, &ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE10_CTRL_REG0", REG_SMC, 0x1207500, &ixPB0_RX_LANE10_CTRL_REG0[0], sizeof(ixPB0_RX_LANE10_CTRL_REG0)/sizeof(ixPB0_RX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207508, &ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE11_CTRL_REG0", REG_SMC, 0x1207600, &ixPB0_RX_LANE11_CTRL_REG0[0], sizeof(ixPB0_RX_LANE11_CTRL_REG0)/sizeof(ixPB0_RX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207608, &ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE12_CTRL_REG0", REG_SMC, 0x1207840, &ixPB0_RX_LANE12_CTRL_REG0[0], sizeof(ixPB0_RX_LANE12_CTRL_REG0)/sizeof(ixPB0_RX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207848, &ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE13_CTRL_REG0", REG_SMC, 0x1207880, &ixPB0_RX_LANE13_CTRL_REG0[0], sizeof(ixPB0_RX_LANE13_CTRL_REG0)/sizeof(ixPB0_RX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207888, &ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE14_CTRL_REG0", REG_SMC, 0x1207900, &ixPB0_RX_LANE14_CTRL_REG0[0], sizeof(ixPB0_RX_LANE14_CTRL_REG0)/sizeof(ixPB0_RX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207908, &ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE15_CTRL_REG0", REG_SMC, 0x1207a00, &ixPB0_RX_LANE15_CTRL_REG0[0], sizeof(ixPB0_RX_LANE15_CTRL_REG0)/sizeof(ixPB0_RX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x1207a08, &ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_CTRL_REG0", REG_SMC, 0x1208000, &ixPB0_TX_GLB_CTRL_REG0[0], sizeof(ixPB0_TX_GLB_CTRL_REG0)/sizeof(ixPB0_TX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_LANE_SKEW_CTRL", REG_SMC, 0x1208004, &ixPB0_TX_GLB_LANE_SKEW_CTRL[0], sizeof(ixPB0_TX_GLB_LANE_SKEW_CTRL)/sizeof(ixPB0_TX_GLB_LANE_SKEW_CTRL[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208010, &ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0", REG_SMC, 0x1208014, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1", REG_SMC, 0x1208018, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2", REG_SMC, 0x120801c, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3", REG_SMC, 0x1208020, &ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0], sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3)/sizeof(ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG0", REG_SMC, 0x1208030, &ixPB0_TX_GLB_OVRD_REG0[0], sizeof(ixPB0_TX_GLB_OVRD_REG0)/sizeof(ixPB0_TX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG1", REG_SMC, 0x1208034, &ixPB0_TX_GLB_OVRD_REG1[0], sizeof(ixPB0_TX_GLB_OVRD_REG1)/sizeof(ixPB0_TX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG2", REG_SMC, 0x1208038, &ixPB0_TX_GLB_OVRD_REG2[0], sizeof(ixPB0_TX_GLB_OVRD_REG2)/sizeof(ixPB0_TX_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG3", REG_SMC, 0x120803c, &ixPB0_TX_GLB_OVRD_REG3[0], sizeof(ixPB0_TX_GLB_OVRD_REG3)/sizeof(ixPB0_TX_GLB_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB0_TX_GLB_OVRD_REG4", REG_SMC, 0x1208040, &ixPB0_TX_GLB_OVRD_REG4[0], sizeof(ixPB0_TX_GLB_OVRD_REG4)/sizeof(ixPB0_TX_GLB_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_CTRL_REG0", REG_SMC, 0x1208440, &ixPB0_TX_LANE0_CTRL_REG0[0], sizeof(ixPB0_TX_LANE0_CTRL_REG0)/sizeof(ixPB0_TX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_OVRD_REG0", REG_SMC, 0x1208444, &ixPB0_TX_LANE0_OVRD_REG0[0], sizeof(ixPB0_TX_LANE0_OVRD_REG0)/sizeof(ixPB0_TX_LANE0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208448, &ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_CTRL_REG0", REG_SMC, 0x1208480, &ixPB0_TX_LANE1_CTRL_REG0[0], sizeof(ixPB0_TX_LANE1_CTRL_REG0)/sizeof(ixPB0_TX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_OVRD_REG0", REG_SMC, 0x1208484, &ixPB0_TX_LANE1_OVRD_REG0[0], sizeof(ixPB0_TX_LANE1_OVRD_REG0)/sizeof(ixPB0_TX_LANE1_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208488, &ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_CTRL_REG0", REG_SMC, 0x1208500, &ixPB0_TX_LANE2_CTRL_REG0[0], sizeof(ixPB0_TX_LANE2_CTRL_REG0)/sizeof(ixPB0_TX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_OVRD_REG0", REG_SMC, 0x1208504, &ixPB0_TX_LANE2_OVRD_REG0[0], sizeof(ixPB0_TX_LANE2_OVRD_REG0)/sizeof(ixPB0_TX_LANE2_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208508, &ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_CTRL_REG0", REG_SMC, 0x1208600, &ixPB0_TX_LANE3_CTRL_REG0[0], sizeof(ixPB0_TX_LANE3_CTRL_REG0)/sizeof(ixPB0_TX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_OVRD_REG0", REG_SMC, 0x1208604, &ixPB0_TX_LANE3_OVRD_REG0[0], sizeof(ixPB0_TX_LANE3_OVRD_REG0)/sizeof(ixPB0_TX_LANE3_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208608, &ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_CTRL_REG0", REG_SMC, 0x1208840, &ixPB0_TX_LANE4_CTRL_REG0[0], sizeof(ixPB0_TX_LANE4_CTRL_REG0)/sizeof(ixPB0_TX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_OVRD_REG0", REG_SMC, 0x1208844, &ixPB0_TX_LANE4_OVRD_REG0[0], sizeof(ixPB0_TX_LANE4_OVRD_REG0)/sizeof(ixPB0_TX_LANE4_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208848, &ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_CTRL_REG0", REG_SMC, 0x1208880, &ixPB0_TX_LANE5_CTRL_REG0[0], sizeof(ixPB0_TX_LANE5_CTRL_REG0)/sizeof(ixPB0_TX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_OVRD_REG0", REG_SMC, 0x1208884, &ixPB0_TX_LANE5_OVRD_REG0[0], sizeof(ixPB0_TX_LANE5_OVRD_REG0)/sizeof(ixPB0_TX_LANE5_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208888, &ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_CTRL_REG0", REG_SMC, 0x1208900, &ixPB0_TX_LANE6_CTRL_REG0[0], sizeof(ixPB0_TX_LANE6_CTRL_REG0)/sizeof(ixPB0_TX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_OVRD_REG0", REG_SMC, 0x1208904, &ixPB0_TX_LANE6_OVRD_REG0[0], sizeof(ixPB0_TX_LANE6_OVRD_REG0)/sizeof(ixPB0_TX_LANE6_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208908, &ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_CTRL_REG0", REG_SMC, 0x1208a00, &ixPB0_TX_LANE7_CTRL_REG0[0], sizeof(ixPB0_TX_LANE7_CTRL_REG0)/sizeof(ixPB0_TX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_OVRD_REG0", REG_SMC, 0x1208a04, &ixPB0_TX_LANE7_OVRD_REG0[0], sizeof(ixPB0_TX_LANE7_OVRD_REG0)/sizeof(ixPB0_TX_LANE7_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x1208a08, &ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_CTRL_REG0", REG_SMC, 0x1209440, &ixPB0_TX_LANE8_CTRL_REG0[0], sizeof(ixPB0_TX_LANE8_CTRL_REG0)/sizeof(ixPB0_TX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_OVRD_REG0", REG_SMC, 0x1209444, &ixPB0_TX_LANE8_OVRD_REG0[0], sizeof(ixPB0_TX_LANE8_OVRD_REG0)/sizeof(ixPB0_TX_LANE8_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209448, &ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_CTRL_REG0", REG_SMC, 0x1209480, &ixPB0_TX_LANE9_CTRL_REG0[0], sizeof(ixPB0_TX_LANE9_CTRL_REG0)/sizeof(ixPB0_TX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_OVRD_REG0", REG_SMC, 0x1209484, &ixPB0_TX_LANE9_OVRD_REG0[0], sizeof(ixPB0_TX_LANE9_OVRD_REG0)/sizeof(ixPB0_TX_LANE9_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209488, &ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_CTRL_REG0", REG_SMC, 0x1209500, &ixPB0_TX_LANE10_CTRL_REG0[0], sizeof(ixPB0_TX_LANE10_CTRL_REG0)/sizeof(ixPB0_TX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_OVRD_REG0", REG_SMC, 0x1209504, &ixPB0_TX_LANE10_OVRD_REG0[0], sizeof(ixPB0_TX_LANE10_OVRD_REG0)/sizeof(ixPB0_TX_LANE10_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209508, &ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_CTRL_REG0", REG_SMC, 0x1209600, &ixPB0_TX_LANE11_CTRL_REG0[0], sizeof(ixPB0_TX_LANE11_CTRL_REG0)/sizeof(ixPB0_TX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_OVRD_REG0", REG_SMC, 0x1209604, &ixPB0_TX_LANE11_OVRD_REG0[0], sizeof(ixPB0_TX_LANE11_OVRD_REG0)/sizeof(ixPB0_TX_LANE11_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209608, &ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_CTRL_REG0", REG_SMC, 0x1209840, &ixPB0_TX_LANE12_CTRL_REG0[0], sizeof(ixPB0_TX_LANE12_CTRL_REG0)/sizeof(ixPB0_TX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_OVRD_REG0", REG_SMC, 0x1209844, &ixPB0_TX_LANE12_OVRD_REG0[0], sizeof(ixPB0_TX_LANE12_OVRD_REG0)/sizeof(ixPB0_TX_LANE12_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209848, &ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_CTRL_REG0", REG_SMC, 0x1209880, &ixPB0_TX_LANE13_CTRL_REG0[0], sizeof(ixPB0_TX_LANE13_CTRL_REG0)/sizeof(ixPB0_TX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_OVRD_REG0", REG_SMC, 0x1209884, &ixPB0_TX_LANE13_OVRD_REG0[0], sizeof(ixPB0_TX_LANE13_OVRD_REG0)/sizeof(ixPB0_TX_LANE13_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209888, &ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_CTRL_REG0", REG_SMC, 0x1209900, &ixPB0_TX_LANE14_CTRL_REG0[0], sizeof(ixPB0_TX_LANE14_CTRL_REG0)/sizeof(ixPB0_TX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_OVRD_REG0", REG_SMC, 0x1209904, &ixPB0_TX_LANE14_OVRD_REG0[0], sizeof(ixPB0_TX_LANE14_OVRD_REG0)/sizeof(ixPB0_TX_LANE14_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209908, &ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_CTRL_REG0", REG_SMC, 0x1209a00, &ixPB0_TX_LANE15_CTRL_REG0[0], sizeof(ixPB0_TX_LANE15_CTRL_REG0)/sizeof(ixPB0_TX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_OVRD_REG0", REG_SMC, 0x1209a04, &ixPB0_TX_LANE15_OVRD_REG0[0], sizeof(ixPB0_TX_LANE15_OVRD_REG0)/sizeof(ixPB0_TX_LANE15_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x1209a08, &ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4", REG_MMIO, 0x121, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE4[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5", REG_MMIO, 0x122, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_MMIO_MAP_RANGE5[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0", REG_MMIO, 0x124, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_0[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1", REG_MMIO, 0x125, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2", REG_MMIO, 0x126, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_2[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3", REG_MMIO, 0x127, &mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH_3[0]), 0, 0 },
+	{ "mmADAPTER_ID_W", REG_MMIO, 0x13, &mmADAPTER_ID_W[0], sizeof(mmADAPTER_ID_W)/sizeof(mmADAPTER_ID_W[0]), 0, 0 },
+	{ "ixPCIE_WRAP_SCRATCH1", REG_SMC, 0x1308001, &ixPCIE_WRAP_SCRATCH1[0], sizeof(ixPCIE_WRAP_SCRATCH1)/sizeof(ixPCIE_WRAP_SCRATCH1[0]), 0, 0 },
+	{ "ixPCIE_WRAP_SCRATCH2", REG_SMC, 0x1308002, &ixPCIE_WRAP_SCRATCH2[0], sizeof(ixPCIE_WRAP_SCRATCH2)/sizeof(ixPCIE_WRAP_SCRATCH2[0]), 0, 0 },
+	{ "ixPCIE_WRAP_REG_TARG_MISC", REG_SMC, 0x1308005, &ixPCIE_WRAP_REG_TARG_MISC[0], sizeof(ixPCIE_WRAP_REG_TARG_MISC)/sizeof(ixPCIE_WRAP_REG_TARG_MISC[0]), 0, 0 },
+	{ "ixPCIE_WRAP_DTM_MISC", REG_SMC, 0x1308006, &ixPCIE_WRAP_DTM_MISC[0], sizeof(ixPCIE_WRAP_DTM_MISC)/sizeof(ixPCIE_WRAP_DTM_MISC[0]), 0, 0 },
+	{ "ixPCIE_WRAP_TURNAROUND_DAISYCHAIN", REG_SMC, 0x1308007, &ixPCIE_WRAP_TURNAROUND_DAISYCHAIN[0], sizeof(ixPCIE_WRAP_TURNAROUND_DAISYCHAIN)/sizeof(ixPCIE_WRAP_TURNAROUND_DAISYCHAIN[0]), 0, 0 },
+	{ "ixPCIE_WRAP_MISC", REG_SMC, 0x1308008, &ixPCIE_WRAP_MISC[0], sizeof(ixPCIE_WRAP_MISC)/sizeof(ixPCIE_WRAP_MISC[0]), 0, 0 },
+	{ "ixPCIE_WRAP_PIF_MISC", REG_SMC, 0x1308009, &ixPCIE_WRAP_PIF_MISC[0], sizeof(ixPCIE_WRAP_PIF_MISC)/sizeof(ixPCIE_WRAP_PIF_MISC[0]), 0, 0 },
+	{ "ixPCIE_RXDET_OVERRIDE", REG_SMC, 0x130800a, &ixPCIE_RXDET_OVERRIDE[0], sizeof(ixPCIE_RXDET_OVERRIDE)/sizeof(ixPCIE_RXDET_OVERRIDE[0]), 0, 0 },
+	{ "ixREG_ADAPT_pciecore0_CONTROL", REG_SMC, 0x1308090, &ixREG_ADAPT_pciecore0_CONTROL[0], sizeof(ixREG_ADAPT_pciecore0_CONTROL)/sizeof(ixREG_ADAPT_pciecore0_CONTROL[0]), 0, 0 },
+	{ "ixREG_ADAPT_pwregt_CONTROL", REG_SMC, 0x1308096, &ixREG_ADAPT_pwregt_CONTROL[0], sizeof(ixREG_ADAPT_pwregt_CONTROL)/sizeof(ixREG_ADAPT_pwregt_CONTROL[0]), 0, 0 },
+	{ "ixREG_ADAPT_pwregr_CONTROL", REG_SMC, 0x1308097, &ixREG_ADAPT_pwregr_CONTROL[0], sizeof(ixREG_ADAPT_pwregr_CONTROL)/sizeof(ixREG_ADAPT_pwregr_CONTROL[0]), 0, 0 },
+	{ "ixREG_ADAPT_pif0_CONTROL", REG_SMC, 0x1308098, &ixREG_ADAPT_pif0_CONTROL[0], sizeof(ixREG_ADAPT_pif0_CONTROL)/sizeof(ixREG_ADAPT_pif0_CONTROL[0]), 0, 0 },
+	{ "mmPMI_CAP_LIST", REG_MMIO, 0x14, &mmPMI_CAP_LIST[0], sizeof(mmPMI_CAP_LIST)/sizeof(mmPMI_CAP_LIST[0]), 0, 0 },
+	{ "mmPMI_CAP", REG_MMIO, 0x14, &mmPMI_CAP[0], sizeof(mmPMI_CAP)/sizeof(mmPMI_CAP[0]), 0, 0 },
+	{ "ixPCIE_RESERVED", REG_SMC, 0x1400000, &ixPCIE_RESERVED[0], sizeof(ixPCIE_RESERVED)/sizeof(ixPCIE_RESERVED[0]), 0, 0 },
+	{ "ixPCIE_SCRATCH", REG_SMC, 0x1400001, &ixPCIE_SCRATCH[0], sizeof(ixPCIE_SCRATCH)/sizeof(ixPCIE_SCRATCH[0]), 0, 0 },
+	{ "ixPCIE_HW_DEBUG", REG_SMC, 0x1400002, &ixPCIE_HW_DEBUG[0], sizeof(ixPCIE_HW_DEBUG)/sizeof(ixPCIE_HW_DEBUG[0]), 0, 0 },
+	{ "ixPCIE_RX_NUM_NAK", REG_SMC, 0x140000e, &ixPCIE_RX_NUM_NAK[0], sizeof(ixPCIE_RX_NUM_NAK)/sizeof(ixPCIE_RX_NUM_NAK[0]), 0, 0 },
+	{ "ixPCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x140000f, &ixPCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 },
+	{ "ixPCIE_CNTL", REG_SMC, 0x1400010, &ixPCIE_CNTL[0], sizeof(ixPCIE_CNTL)/sizeof(ixPCIE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_CONFIG_CNTL", REG_SMC, 0x1400011, &ixPCIE_CONFIG_CNTL[0], sizeof(ixPCIE_CONFIG_CNTL)/sizeof(ixPCIE_CONFIG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_DEBUG_CNTL", REG_SMC, 0x1400012, &ixPCIE_DEBUG_CNTL[0], sizeof(ixPCIE_DEBUG_CNTL)/sizeof(ixPCIE_DEBUG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_INT_CNTL", REG_SMC, 0x140001a, &ixPCIE_INT_CNTL[0], sizeof(ixPCIE_INT_CNTL)/sizeof(ixPCIE_INT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_INT_STATUS", REG_SMC, 0x140001b, &ixPCIE_INT_STATUS[0], sizeof(ixPCIE_INT_STATUS)/sizeof(ixPCIE_INT_STATUS[0]), 0, 0 },
+	{ "ixPCIE_CNTL2", REG_SMC, 0x140001c, &ixPCIE_CNTL2[0], sizeof(ixPCIE_CNTL2)/sizeof(ixPCIE_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL2", REG_SMC, 0x140001d, &ixPCIE_RX_CNTL2[0], sizeof(ixPCIE_RX_CNTL2)/sizeof(ixPCIE_RX_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_TX_F0_ATTR_CNTL", REG_SMC, 0x140001e, &ixPCIE_TX_F0_ATTR_CNTL[0], sizeof(ixPCIE_TX_F0_ATTR_CNTL)/sizeof(ixPCIE_TX_F0_ATTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_F1_F2_ATTR_CNTL", REG_SMC, 0x140001f, &ixPCIE_TX_F1_F2_ATTR_CNTL[0], sizeof(ixPCIE_TX_F1_F2_ATTR_CNTL)/sizeof(ixPCIE_TX_F1_F2_ATTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_CI_CNTL", REG_SMC, 0x1400020, &ixPCIE_CI_CNTL[0], sizeof(ixPCIE_CI_CNTL)/sizeof(ixPCIE_CI_CNTL[0]), 0, 0 },
+	{ "ixPCIE_BUS_CNTL", REG_SMC, 0x1400021, &ixPCIE_BUS_CNTL[0], sizeof(ixPCIE_BUS_CNTL)/sizeof(ixPCIE_BUS_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE6", REG_SMC, 0x1400022, &ixPCIE_LC_STATE6[0], sizeof(ixPCIE_LC_STATE6)/sizeof(ixPCIE_LC_STATE6[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE7", REG_SMC, 0x1400023, &ixPCIE_LC_STATE7[0], sizeof(ixPCIE_LC_STATE7)/sizeof(ixPCIE_LC_STATE7[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE8", REG_SMC, 0x1400024, &ixPCIE_LC_STATE8[0], sizeof(ixPCIE_LC_STATE8)/sizeof(ixPCIE_LC_STATE8[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE9", REG_SMC, 0x1400025, &ixPCIE_LC_STATE9[0], sizeof(ixPCIE_LC_STATE9)/sizeof(ixPCIE_LC_STATE9[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE10", REG_SMC, 0x1400026, &ixPCIE_LC_STATE10[0], sizeof(ixPCIE_LC_STATE10)/sizeof(ixPCIE_LC_STATE10[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE11", REG_SMC, 0x1400027, &ixPCIE_LC_STATE11[0], sizeof(ixPCIE_LC_STATE11)/sizeof(ixPCIE_LC_STATE11[0]), 0, 0 },
+	{ "ixPCIE_LC_STATUS1", REG_SMC, 0x1400028, &ixPCIE_LC_STATUS1[0], sizeof(ixPCIE_LC_STATUS1)/sizeof(ixPCIE_LC_STATUS1[0]), 0, 0 },
+	{ "ixPCIE_LC_STATUS2", REG_SMC, 0x1400029, &ixPCIE_LC_STATUS2[0], sizeof(ixPCIE_LC_STATUS2)/sizeof(ixPCIE_LC_STATUS2[0]), 0, 0 },
+	{ "ixPCIE_WPR_CNTL", REG_SMC, 0x1400030, &ixPCIE_WPR_CNTL[0], sizeof(ixPCIE_WPR_CNTL)/sizeof(ixPCIE_WPR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP0", REG_SMC, 0x1400031, &ixPCIE_RX_LAST_TLP0[0], sizeof(ixPCIE_RX_LAST_TLP0)/sizeof(ixPCIE_RX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP1", REG_SMC, 0x1400032, &ixPCIE_RX_LAST_TLP1[0], sizeof(ixPCIE_RX_LAST_TLP1)/sizeof(ixPCIE_RX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP2", REG_SMC, 0x1400033, &ixPCIE_RX_LAST_TLP2[0], sizeof(ixPCIE_RX_LAST_TLP2)/sizeof(ixPCIE_RX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP3", REG_SMC, 0x1400034, &ixPCIE_RX_LAST_TLP3[0], sizeof(ixPCIE_RX_LAST_TLP3)/sizeof(ixPCIE_RX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP0", REG_SMC, 0x1400035, &ixPCIE_TX_LAST_TLP0[0], sizeof(ixPCIE_TX_LAST_TLP0)/sizeof(ixPCIE_TX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP1", REG_SMC, 0x1400036, &ixPCIE_TX_LAST_TLP1[0], sizeof(ixPCIE_TX_LAST_TLP1)/sizeof(ixPCIE_TX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP2", REG_SMC, 0x1400037, &ixPCIE_TX_LAST_TLP2[0], sizeof(ixPCIE_TX_LAST_TLP2)/sizeof(ixPCIE_TX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP3", REG_SMC, 0x1400038, &ixPCIE_TX_LAST_TLP3[0], sizeof(ixPCIE_TX_LAST_TLP3)/sizeof(ixPCIE_TX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPCIE_I2C_REG_ADDR_EXPAND", REG_SMC, 0x140003a, &ixPCIE_I2C_REG_ADDR_EXPAND[0], sizeof(ixPCIE_I2C_REG_ADDR_EXPAND)/sizeof(ixPCIE_I2C_REG_ADDR_EXPAND[0]), 0, 0 },
+	{ "ixPCIE_I2C_REG_DATA", REG_SMC, 0x140003b, &ixPCIE_I2C_REG_DATA[0], sizeof(ixPCIE_I2C_REG_DATA)/sizeof(ixPCIE_I2C_REG_DATA[0]), 0, 0 },
+	{ "ixPCIE_CFG_CNTL", REG_SMC, 0x140003c, &ixPCIE_CFG_CNTL[0], sizeof(ixPCIE_CFG_CNTL)/sizeof(ixPCIE_CFG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_PM_CNTL", REG_SMC, 0x140003d, &ixPCIE_LC_PM_CNTL[0], sizeof(ixPCIE_LC_PM_CNTL)/sizeof(ixPCIE_LC_PM_CNTL[0]), 0, 0 },
+	{ "ixPCIE_P_CNTL", REG_SMC, 0x1400040, &ixPCIE_P_CNTL[0], sizeof(ixPCIE_P_CNTL)/sizeof(ixPCIE_P_CNTL[0]), 0, 0 },
+	{ "ixPCIE_P_BUF_STATUS", REG_SMC, 0x1400041, &ixPCIE_P_BUF_STATUS[0], sizeof(ixPCIE_P_BUF_STATUS)/sizeof(ixPCIE_P_BUF_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_DECODER_STATUS", REG_SMC, 0x1400042, &ixPCIE_P_DECODER_STATUS[0], sizeof(ixPCIE_P_DECODER_STATUS)/sizeof(ixPCIE_P_DECODER_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_MISC_STATUS", REG_SMC, 0x1400043, &ixPCIE_P_MISC_STATUS[0], sizeof(ixPCIE_P_MISC_STATUS)/sizeof(ixPCIE_P_MISC_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_RCV_L0S_FTS_DET", REG_SMC, 0x1400050, &ixPCIE_P_RCV_L0S_FTS_DET[0], sizeof(ixPCIE_P_RCV_L0S_FTS_DET)/sizeof(ixPCIE_P_RCV_L0S_FTS_DET[0]), 0, 0 },
+	{ "ixPCIE_TX_LTR_CNTL", REG_SMC, 0x1400060, &ixPCIE_TX_LTR_CNTL[0], sizeof(ixPCIE_TX_LTR_CNTL)/sizeof(ixPCIE_TX_LTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_OBFF_CNTL", REG_SMC, 0x1400061, &ixPCIE_OBFF_CNTL[0], sizeof(ixPCIE_OBFF_CNTL)/sizeof(ixPCIE_OBFF_CNTL[0]), 0, 0 },
+	{ "ixPCIE_IDLE_STATUS", REG_SMC, 0x1400062, &ixPCIE_IDLE_STATUS[0], sizeof(ixPCIE_IDLE_STATUS)/sizeof(ixPCIE_IDLE_STATUS[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT_CNTL", REG_SMC, 0x1400080, &ixPCIE_PERF_COUNT_CNTL[0], sizeof(ixPCIE_PERF_COUNT_CNTL)/sizeof(ixPCIE_PERF_COUNT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_TXCLK", REG_SMC, 0x1400081, &ixPCIE_PERF_CNTL_TXCLK[0], sizeof(ixPCIE_PERF_CNTL_TXCLK)/sizeof(ixPCIE_PERF_CNTL_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x1400082, &ixPCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK)/sizeof(ixPCIE_PERF_COUNT0_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x1400083, &ixPCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK)/sizeof(ixPCIE_PERF_COUNT1_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x1400084, &ixPCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x1400085, &ixPCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x1400086, &ixPCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x1400087, &ixPCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x1400088, &ixPCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x1400089, &ixPCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x140008a, &ixPCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x140008b, &ixPCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x140008c, &ixPCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x140008d, &ixPCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x140008e, &ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x140008f, &ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x1400090, &ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x1400091, &ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x1400092, &ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x1400093, &ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x1400094, &ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x1400095, &ixPCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPCIE_PERF_CNTL_TXCLK2)/sizeof(ixPCIE_PERF_CNTL_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x1400096, &ixPCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x1400097, &ixPCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F0", REG_SMC, 0x14000b0, &ixPCIE_STRAP_F0[0], sizeof(ixPCIE_STRAP_F0)/sizeof(ixPCIE_STRAP_F0[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F1", REG_SMC, 0x14000b1, &ixPCIE_STRAP_F1[0], sizeof(ixPCIE_STRAP_F1)/sizeof(ixPCIE_STRAP_F1[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F2", REG_SMC, 0x14000b2, &ixPCIE_STRAP_F2[0], sizeof(ixPCIE_STRAP_F2)/sizeof(ixPCIE_STRAP_F2[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F3", REG_SMC, 0x14000b3, &ixPCIE_STRAP_F3[0], sizeof(ixPCIE_STRAP_F3)/sizeof(ixPCIE_STRAP_F3[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F4", REG_SMC, 0x14000b4, &ixPCIE_STRAP_F4[0], sizeof(ixPCIE_STRAP_F4)/sizeof(ixPCIE_STRAP_F4[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F5", REG_SMC, 0x14000b5, &ixPCIE_STRAP_F5[0], sizeof(ixPCIE_STRAP_F5)/sizeof(ixPCIE_STRAP_F5[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F6", REG_SMC, 0x14000b6, &ixPCIE_STRAP_F6[0], sizeof(ixPCIE_STRAP_F6)/sizeof(ixPCIE_STRAP_F6[0]), 0, 0 },
+	{ "ixPCIE_STRAP_MSIX", REG_SMC, 0x14000b7, &ixPCIE_STRAP_MSIX[0], sizeof(ixPCIE_STRAP_MSIX)/sizeof(ixPCIE_STRAP_MSIX[0]), 0, 0 },
+	{ "ixPCIE_STRAP_MISC", REG_SMC, 0x14000c0, &ixPCIE_STRAP_MISC[0], sizeof(ixPCIE_STRAP_MISC)/sizeof(ixPCIE_STRAP_MISC[0]), 0, 0 },
+	{ "ixPCIE_STRAP_MISC2", REG_SMC, 0x14000c1, &ixPCIE_STRAP_MISC2[0], sizeof(ixPCIE_STRAP_MISC2)/sizeof(ixPCIE_STRAP_MISC2[0]), 0, 0 },
+	{ "ixPCIE_STRAP_PI", REG_SMC, 0x14000c2, &ixPCIE_STRAP_PI[0], sizeof(ixPCIE_STRAP_PI)/sizeof(ixPCIE_STRAP_PI[0]), 0, 0 },
+	{ "ixPCIE_STRAP_I2C_BD", REG_SMC, 0x14000c4, &ixPCIE_STRAP_I2C_BD[0], sizeof(ixPCIE_STRAP_I2C_BD)/sizeof(ixPCIE_STRAP_I2C_BD[0]), 0, 0 },
+	{ "ixPCIE_PRBS_CLR", REG_SMC, 0x14000c8, &ixPCIE_PRBS_CLR[0], sizeof(ixPCIE_PRBS_CLR)/sizeof(ixPCIE_PRBS_CLR[0]), 0, 0 },
+	{ "ixPCIE_PRBS_STATUS1", REG_SMC, 0x14000c9, &ixPCIE_PRBS_STATUS1[0], sizeof(ixPCIE_PRBS_STATUS1)/sizeof(ixPCIE_PRBS_STATUS1[0]), 0, 0 },
+	{ "ixPCIE_PRBS_STATUS2", REG_SMC, 0x14000ca, &ixPCIE_PRBS_STATUS2[0], sizeof(ixPCIE_PRBS_STATUS2)/sizeof(ixPCIE_PRBS_STATUS2[0]), 0, 0 },
+	{ "ixPCIE_PRBS_FREERUN", REG_SMC, 0x14000cb, &ixPCIE_PRBS_FREERUN[0], sizeof(ixPCIE_PRBS_FREERUN)/sizeof(ixPCIE_PRBS_FREERUN[0]), 0, 0 },
+	{ "ixPCIE_PRBS_MISC", REG_SMC, 0x14000cc, &ixPCIE_PRBS_MISC[0], sizeof(ixPCIE_PRBS_MISC)/sizeof(ixPCIE_PRBS_MISC[0]), 0, 0 },
+	{ "ixPCIE_PRBS_USER_PATTERN", REG_SMC, 0x14000cd, &ixPCIE_PRBS_USER_PATTERN[0], sizeof(ixPCIE_PRBS_USER_PATTERN)/sizeof(ixPCIE_PRBS_USER_PATTERN[0]), 0, 0 },
+	{ "ixPCIE_PRBS_LO_BITCNT", REG_SMC, 0x14000ce, &ixPCIE_PRBS_LO_BITCNT[0], sizeof(ixPCIE_PRBS_LO_BITCNT)/sizeof(ixPCIE_PRBS_LO_BITCNT[0]), 0, 0 },
+	{ "ixPCIE_PRBS_HI_BITCNT", REG_SMC, 0x14000cf, &ixPCIE_PRBS_HI_BITCNT[0], sizeof(ixPCIE_PRBS_HI_BITCNT)/sizeof(ixPCIE_PRBS_HI_BITCNT[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_0", REG_SMC, 0x14000d0, &ixPCIE_PRBS_ERRCNT_0[0], sizeof(ixPCIE_PRBS_ERRCNT_0)/sizeof(ixPCIE_PRBS_ERRCNT_0[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_1", REG_SMC, 0x14000d1, &ixPCIE_PRBS_ERRCNT_1[0], sizeof(ixPCIE_PRBS_ERRCNT_1)/sizeof(ixPCIE_PRBS_ERRCNT_1[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_2", REG_SMC, 0x14000d2, &ixPCIE_PRBS_ERRCNT_2[0], sizeof(ixPCIE_PRBS_ERRCNT_2)/sizeof(ixPCIE_PRBS_ERRCNT_2[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_3", REG_SMC, 0x14000d3, &ixPCIE_PRBS_ERRCNT_3[0], sizeof(ixPCIE_PRBS_ERRCNT_3)/sizeof(ixPCIE_PRBS_ERRCNT_3[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_4", REG_SMC, 0x14000d4, &ixPCIE_PRBS_ERRCNT_4[0], sizeof(ixPCIE_PRBS_ERRCNT_4)/sizeof(ixPCIE_PRBS_ERRCNT_4[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_5", REG_SMC, 0x14000d5, &ixPCIE_PRBS_ERRCNT_5[0], sizeof(ixPCIE_PRBS_ERRCNT_5)/sizeof(ixPCIE_PRBS_ERRCNT_5[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_6", REG_SMC, 0x14000d6, &ixPCIE_PRBS_ERRCNT_6[0], sizeof(ixPCIE_PRBS_ERRCNT_6)/sizeof(ixPCIE_PRBS_ERRCNT_6[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_7", REG_SMC, 0x14000d7, &ixPCIE_PRBS_ERRCNT_7[0], sizeof(ixPCIE_PRBS_ERRCNT_7)/sizeof(ixPCIE_PRBS_ERRCNT_7[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_8", REG_SMC, 0x14000d8, &ixPCIE_PRBS_ERRCNT_8[0], sizeof(ixPCIE_PRBS_ERRCNT_8)/sizeof(ixPCIE_PRBS_ERRCNT_8[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_9", REG_SMC, 0x14000d9, &ixPCIE_PRBS_ERRCNT_9[0], sizeof(ixPCIE_PRBS_ERRCNT_9)/sizeof(ixPCIE_PRBS_ERRCNT_9[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_10", REG_SMC, 0x14000da, &ixPCIE_PRBS_ERRCNT_10[0], sizeof(ixPCIE_PRBS_ERRCNT_10)/sizeof(ixPCIE_PRBS_ERRCNT_10[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_11", REG_SMC, 0x14000db, &ixPCIE_PRBS_ERRCNT_11[0], sizeof(ixPCIE_PRBS_ERRCNT_11)/sizeof(ixPCIE_PRBS_ERRCNT_11[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_12", REG_SMC, 0x14000dc, &ixPCIE_PRBS_ERRCNT_12[0], sizeof(ixPCIE_PRBS_ERRCNT_12)/sizeof(ixPCIE_PRBS_ERRCNT_12[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_13", REG_SMC, 0x14000dd, &ixPCIE_PRBS_ERRCNT_13[0], sizeof(ixPCIE_PRBS_ERRCNT_13)/sizeof(ixPCIE_PRBS_ERRCNT_13[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_14", REG_SMC, 0x14000de, &ixPCIE_PRBS_ERRCNT_14[0], sizeof(ixPCIE_PRBS_ERRCNT_14)/sizeof(ixPCIE_PRBS_ERRCNT_14[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_15", REG_SMC, 0x14000df, &ixPCIE_PRBS_ERRCNT_15[0], sizeof(ixPCIE_PRBS_ERRCNT_15)/sizeof(ixPCIE_PRBS_ERRCNT_15[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_CAP", REG_SMC, 0x14000e0, &ixPCIE_F0_DPA_CAP[0], sizeof(ixPCIE_F0_DPA_CAP)/sizeof(ixPCIE_F0_DPA_CAP[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_LATENCY_INDICATOR", REG_SMC, 0x14000e4, &ixPCIE_F0_DPA_LATENCY_INDICATOR[0], sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR)/sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_CNTL", REG_SMC, 0x14000e5, &ixPCIE_F0_DPA_CNTL[0], sizeof(ixPCIE_F0_DPA_CNTL)/sizeof(ixPCIE_F0_DPA_CNTL[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0", REG_SMC, 0x14000e7, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1", REG_SMC, 0x14000e8, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2", REG_SMC, 0x14000e9, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3", REG_SMC, 0x14000ea, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4", REG_SMC, 0x14000eb, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5", REG_SMC, 0x14000ec, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6", REG_SMC, 0x14000ed, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7", REG_SMC, 0x14000ee, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0]), 0, 0 },
+	{ "ixSWRST_COMMAND_1", REG_SMC, 0x1400103, &ixSWRST_COMMAND_1[0], sizeof(ixSWRST_COMMAND_1)/sizeof(ixSWRST_COMMAND_1[0]), 0, 0 },
+	{ "ixLM_CONTROL", REG_SMC, 0x1400120, &ixLM_CONTROL[0], sizeof(ixLM_CONTROL)/sizeof(ixLM_CONTROL[0]), 0, 0 },
+	{ "ixLM_PCIETXMUX0", REG_SMC, 0x1400121, &ixLM_PCIETXMUX0[0], sizeof(ixLM_PCIETXMUX0)/sizeof(ixLM_PCIETXMUX0[0]), 0, 0 },
+	{ "ixLM_PCIETXMUX1", REG_SMC, 0x1400122, &ixLM_PCIETXMUX1[0], sizeof(ixLM_PCIETXMUX1)/sizeof(ixLM_PCIETXMUX1[0]), 0, 0 },
+	{ "ixLM_PCIETXMUX2", REG_SMC, 0x1400123, &ixLM_PCIETXMUX2[0], sizeof(ixLM_PCIETXMUX2)/sizeof(ixLM_PCIETXMUX2[0]), 0, 0 },
+	{ "ixLM_PCIETXMUX3", REG_SMC, 0x1400124, &ixLM_PCIETXMUX3[0], sizeof(ixLM_PCIETXMUX3)/sizeof(ixLM_PCIETXMUX3[0]), 0, 0 },
+	{ "ixLM_PCIERXMUX0", REG_SMC, 0x1400125, &ixLM_PCIERXMUX0[0], sizeof(ixLM_PCIERXMUX0)/sizeof(ixLM_PCIERXMUX0[0]), 0, 0 },
+	{ "ixLM_PCIERXMUX1", REG_SMC, 0x1400126, &ixLM_PCIERXMUX1[0], sizeof(ixLM_PCIERXMUX1)/sizeof(ixLM_PCIERXMUX1[0]), 0, 0 },
+	{ "ixLM_PCIERXMUX2", REG_SMC, 0x1400127, &ixLM_PCIERXMUX2[0], sizeof(ixLM_PCIERXMUX2)/sizeof(ixLM_PCIERXMUX2[0]), 0, 0 },
+	{ "ixLM_PCIERXMUX3", REG_SMC, 0x1400128, &ixLM_PCIERXMUX3[0], sizeof(ixLM_PCIERXMUX3)/sizeof(ixLM_PCIERXMUX3[0]), 0, 0 },
+	{ "ixLM_LANEENABLE", REG_SMC, 0x1400129, &ixLM_LANEENABLE[0], sizeof(ixLM_LANEENABLE)/sizeof(ixLM_LANEENABLE[0]), 0, 0 },
+	{ "ixLM_PRBSCONTROL", REG_SMC, 0x140012a, &ixLM_PRBSCONTROL[0], sizeof(ixLM_PRBSCONTROL)/sizeof(ixLM_PRBSCONTROL[0]), 0, 0 },
+	{ "ixLM_POWERCONTROL", REG_SMC, 0x140012b, &ixLM_POWERCONTROL[0], sizeof(ixLM_POWERCONTROL)/sizeof(ixLM_POWERCONTROL[0]), 0, 0 },
+	{ "ixLM_POWERCONTROL1", REG_SMC, 0x140012c, &ixLM_POWERCONTROL1[0], sizeof(ixLM_POWERCONTROL1)/sizeof(ixLM_POWERCONTROL1[0]), 0, 0 },
+	{ "ixLM_POWERCONTROL2", REG_SMC, 0x140012d, &ixLM_POWERCONTROL2[0], sizeof(ixLM_POWERCONTROL2)/sizeof(ixLM_POWERCONTROL2[0]), 0, 0 },
+	{ "ixLM_POWERCONTROL3", REG_SMC, 0x140012e, &ixLM_POWERCONTROL3[0], sizeof(ixLM_POWERCONTROL3)/sizeof(ixLM_POWERCONTROL3[0]), 0, 0 },
+	{ "ixLM_POWERCONTROL4", REG_SMC, 0x140012f, &ixLM_POWERCONTROL4[0], sizeof(ixLM_POWERCONTROL4)/sizeof(ixLM_POWERCONTROL4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_CNTL", REG_MMIO, 0x1401, &mmGARLIC_FLUSH_CNTL[0], sizeof(mmGARLIC_FLUSH_CNTL)/sizeof(mmGARLIC_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_0", REG_MMIO, 0x1402, &mmGARLIC_FLUSH_ADDR_START_0[0], sizeof(mmGARLIC_FLUSH_ADDR_START_0)/sizeof(mmGARLIC_FLUSH_ADDR_START_0[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_0", REG_MMIO, 0x1403, &mmGARLIC_FLUSH_ADDR_END_0[0], sizeof(mmGARLIC_FLUSH_ADDR_END_0)/sizeof(mmGARLIC_FLUSH_ADDR_END_0[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_1", REG_MMIO, 0x1404, &mmGARLIC_FLUSH_ADDR_START_1[0], sizeof(mmGARLIC_FLUSH_ADDR_START_1)/sizeof(mmGARLIC_FLUSH_ADDR_START_1[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_1", REG_MMIO, 0x1405, &mmGARLIC_FLUSH_ADDR_END_1[0], sizeof(mmGARLIC_FLUSH_ADDR_END_1)/sizeof(mmGARLIC_FLUSH_ADDR_END_1[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_2", REG_MMIO, 0x1406, &mmGARLIC_FLUSH_ADDR_START_2[0], sizeof(mmGARLIC_FLUSH_ADDR_START_2)/sizeof(mmGARLIC_FLUSH_ADDR_START_2[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_2", REG_MMIO, 0x1407, &mmGARLIC_FLUSH_ADDR_END_2[0], sizeof(mmGARLIC_FLUSH_ADDR_END_2)/sizeof(mmGARLIC_FLUSH_ADDR_END_2[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_3", REG_MMIO, 0x1408, &mmGARLIC_FLUSH_ADDR_START_3[0], sizeof(mmGARLIC_FLUSH_ADDR_START_3)/sizeof(mmGARLIC_FLUSH_ADDR_START_3[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_3", REG_MMIO, 0x1409, &mmGARLIC_FLUSH_ADDR_END_3[0], sizeof(mmGARLIC_FLUSH_ADDR_END_3)/sizeof(mmGARLIC_FLUSH_ADDR_END_3[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_4", REG_MMIO, 0x140a, &mmGARLIC_FLUSH_ADDR_START_4[0], sizeof(mmGARLIC_FLUSH_ADDR_START_4)/sizeof(mmGARLIC_FLUSH_ADDR_START_4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_4", REG_MMIO, 0x140b, &mmGARLIC_FLUSH_ADDR_END_4[0], sizeof(mmGARLIC_FLUSH_ADDR_END_4)/sizeof(mmGARLIC_FLUSH_ADDR_END_4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_5", REG_MMIO, 0x140c, &mmGARLIC_FLUSH_ADDR_START_5[0], sizeof(mmGARLIC_FLUSH_ADDR_START_5)/sizeof(mmGARLIC_FLUSH_ADDR_START_5[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_5", REG_MMIO, 0x140d, &mmGARLIC_FLUSH_ADDR_END_5[0], sizeof(mmGARLIC_FLUSH_ADDR_END_5)/sizeof(mmGARLIC_FLUSH_ADDR_END_5[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_6", REG_MMIO, 0x140e, &mmGARLIC_FLUSH_ADDR_START_6[0], sizeof(mmGARLIC_FLUSH_ADDR_START_6)/sizeof(mmGARLIC_FLUSH_ADDR_START_6[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_6", REG_MMIO, 0x140f, &mmGARLIC_FLUSH_ADDR_END_6[0], sizeof(mmGARLIC_FLUSH_ADDR_END_6)/sizeof(mmGARLIC_FLUSH_ADDR_END_6[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_7", REG_MMIO, 0x1410, &mmGARLIC_FLUSH_ADDR_START_7[0], sizeof(mmGARLIC_FLUSH_ADDR_START_7)/sizeof(mmGARLIC_FLUSH_ADDR_START_7[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_7", REG_MMIO, 0x1411, &mmGARLIC_FLUSH_ADDR_END_7[0], sizeof(mmGARLIC_FLUSH_ADDR_END_7)/sizeof(mmGARLIC_FLUSH_ADDR_END_7[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_REQ", REG_MMIO, 0x1412, &mmGARLIC_FLUSH_REQ[0], sizeof(mmGARLIC_FLUSH_REQ)/sizeof(mmGARLIC_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_GARLIC_FLUSH_REQ", REG_MMIO, 0x1413, &mmGPU_GARLIC_FLUSH_REQ[0], sizeof(mmGPU_GARLIC_FLUSH_REQ)/sizeof(mmGPU_GARLIC_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_GARLIC_FLUSH_DONE", REG_MMIO, 0x1414, &mmGPU_GARLIC_FLUSH_DONE[0], sizeof(mmGPU_GARLIC_FLUSH_DONE)/sizeof(mmGPU_GARLIC_FLUSH_DONE[0]), 0, 0 },
+	{ "mmBIF_GPU_IDLE_LATENCY", REG_MMIO, 0x1415, &mmBIF_GPU_IDLE_LATENCY[0], sizeof(mmBIF_GPU_IDLE_LATENCY)/sizeof(mmBIF_GPU_IDLE_LATENCY[0]), 0, 0 },
+	{ "mmBIF_MMIO_MAP_RANGE0", REG_MMIO, 0x1416, &mmBIF_MMIO_MAP_RANGE0[0], sizeof(mmBIF_MMIO_MAP_RANGE0)/sizeof(mmBIF_MMIO_MAP_RANGE0[0]), 0, 0 },
+	{ "mmBIF_MMIO_MAP_RANGE1", REG_MMIO, 0x1417, &mmBIF_MMIO_MAP_RANGE1[0], sizeof(mmBIF_MMIO_MAP_RANGE1)/sizeof(mmBIF_MMIO_MAP_RANGE1[0]), 0, 0 },
+	{ "mmBIF_MMIO_MAP_RANGE2", REG_MMIO, 0x1418, &mmBIF_MMIO_MAP_RANGE2[0], sizeof(mmBIF_MMIO_MAP_RANGE2)/sizeof(mmBIF_MMIO_MAP_RANGE2[0]), 0, 0 },
+	{ "mmBIF_MMIO_MAP_RANGE3", REG_MMIO, 0x1419, &mmBIF_MMIO_MAP_RANGE3[0], sizeof(mmBIF_MMIO_MAP_RANGE3)/sizeof(mmBIF_MMIO_MAP_RANGE3[0]), 0, 0 },
+	{ "mmBIF_MMIO_MAP_RANGE4", REG_MMIO, 0x141a, &mmBIF_MMIO_MAP_RANGE4[0], sizeof(mmBIF_MMIO_MAP_RANGE4)/sizeof(mmBIF_MMIO_MAP_RANGE4[0]), 0, 0 },
+	{ "mmBIF_MMIO_MAP_RANGE5", REG_MMIO, 0x141b, &mmBIF_MMIO_MAP_RANGE5[0], sizeof(mmBIF_MMIO_MAP_RANGE5)/sizeof(mmBIF_MMIO_MAP_RANGE5[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_GPU_IDLE_LATENCY", REG_MMIO, 0x141c, &mmBIF_GPUIOV_GPU_IDLE_LATENCY[0], sizeof(mmBIF_GPUIOV_GPU_IDLE_LATENCY)/sizeof(mmBIF_GPUIOV_GPU_IDLE_LATENCY[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_MMIO_MAP_RANGE0", REG_MMIO, 0x141d, &mmBIF_GPUIOV_MMIO_MAP_RANGE0[0], sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE0)/sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE0[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_MMIO_MAP_RANGE1", REG_MMIO, 0x141e, &mmBIF_GPUIOV_MMIO_MAP_RANGE1[0], sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE1)/sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE1[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_MMIO_MAP_RANGE2", REG_MMIO, 0x141f, &mmBIF_GPUIOV_MMIO_MAP_RANGE2[0], sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE2)/sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE2[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_MMIO_MAP_RANGE3", REG_MMIO, 0x1420, &mmBIF_GPUIOV_MMIO_MAP_RANGE3[0], sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE3)/sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE3[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_MMIO_MAP_RANGE4", REG_MMIO, 0x1421, &mmBIF_GPUIOV_MMIO_MAP_RANGE4[0], sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE4)/sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE4[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_MMIO_MAP_RANGE5", REG_MMIO, 0x1422, &mmBIF_GPUIOV_MMIO_MAP_RANGE5[0], sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE5)/sizeof(mmBIF_GPUIOV_MMIO_MAP_RANGE5[0]), 0, 0 },
+	{ "mmREMAP_HDP_MEM_FLUSH_CNTL", REG_MMIO, 0x1426, &mmREMAP_HDP_MEM_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL)/sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmREMAP_HDP_REG_FLUSH_CNTL", REG_MMIO, 0x1427, &mmREMAP_HDP_REG_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_REG_FLUSH_CNTL)/sizeof(mmREMAP_HDP_REG_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX0_LOWER", REG_MMIO, 0x1428, &mmBIF_VDDGFX_GFX0_LOWER[0], sizeof(mmBIF_VDDGFX_GFX0_LOWER)/sizeof(mmBIF_VDDGFX_GFX0_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX0_UPPER", REG_MMIO, 0x1429, &mmBIF_VDDGFX_GFX0_UPPER[0], sizeof(mmBIF_VDDGFX_GFX0_UPPER)/sizeof(mmBIF_VDDGFX_GFX0_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX1_LOWER", REG_MMIO, 0x142a, &mmBIF_VDDGFX_GFX1_LOWER[0], sizeof(mmBIF_VDDGFX_GFX1_LOWER)/sizeof(mmBIF_VDDGFX_GFX1_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX1_UPPER", REG_MMIO, 0x142b, &mmBIF_VDDGFX_GFX1_UPPER[0], sizeof(mmBIF_VDDGFX_GFX1_UPPER)/sizeof(mmBIF_VDDGFX_GFX1_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX2_LOWER", REG_MMIO, 0x142c, &mmBIF_VDDGFX_GFX2_LOWER[0], sizeof(mmBIF_VDDGFX_GFX2_LOWER)/sizeof(mmBIF_VDDGFX_GFX2_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX2_UPPER", REG_MMIO, 0x142d, &mmBIF_VDDGFX_GFX2_UPPER[0], sizeof(mmBIF_VDDGFX_GFX2_UPPER)/sizeof(mmBIF_VDDGFX_GFX2_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX3_LOWER", REG_MMIO, 0x142e, &mmBIF_VDDGFX_GFX3_LOWER[0], sizeof(mmBIF_VDDGFX_GFX3_LOWER)/sizeof(mmBIF_VDDGFX_GFX3_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX3_UPPER", REG_MMIO, 0x142f, &mmBIF_VDDGFX_GFX3_UPPER[0], sizeof(mmBIF_VDDGFX_GFX3_UPPER)/sizeof(mmBIF_VDDGFX_GFX3_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX4_LOWER", REG_MMIO, 0x1430, &mmBIF_VDDGFX_GFX4_LOWER[0], sizeof(mmBIF_VDDGFX_GFX4_LOWER)/sizeof(mmBIF_VDDGFX_GFX4_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX4_UPPER", REG_MMIO, 0x1431, &mmBIF_VDDGFX_GFX4_UPPER[0], sizeof(mmBIF_VDDGFX_GFX4_UPPER)/sizeof(mmBIF_VDDGFX_GFX4_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX5_LOWER", REG_MMIO, 0x1432, &mmBIF_VDDGFX_GFX5_LOWER[0], sizeof(mmBIF_VDDGFX_GFX5_LOWER)/sizeof(mmBIF_VDDGFX_GFX5_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX5_UPPER", REG_MMIO, 0x1433, &mmBIF_VDDGFX_GFX5_UPPER[0], sizeof(mmBIF_VDDGFX_GFX5_UPPER)/sizeof(mmBIF_VDDGFX_GFX5_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV1_LOWER", REG_MMIO, 0x1434, &mmBIF_VDDGFX_RSV1_LOWER[0], sizeof(mmBIF_VDDGFX_RSV1_LOWER)/sizeof(mmBIF_VDDGFX_RSV1_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV1_UPPER", REG_MMIO, 0x1435, &mmBIF_VDDGFX_RSV1_UPPER[0], sizeof(mmBIF_VDDGFX_RSV1_UPPER)/sizeof(mmBIF_VDDGFX_RSV1_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV2_LOWER", REG_MMIO, 0x1436, &mmBIF_VDDGFX_RSV2_LOWER[0], sizeof(mmBIF_VDDGFX_RSV2_LOWER)/sizeof(mmBIF_VDDGFX_RSV2_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV2_UPPER", REG_MMIO, 0x1437, &mmBIF_VDDGFX_RSV2_UPPER[0], sizeof(mmBIF_VDDGFX_RSV2_UPPER)/sizeof(mmBIF_VDDGFX_RSV2_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV3_LOWER", REG_MMIO, 0x1438, &mmBIF_VDDGFX_RSV3_LOWER[0], sizeof(mmBIF_VDDGFX_RSV3_LOWER)/sizeof(mmBIF_VDDGFX_RSV3_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV3_UPPER", REG_MMIO, 0x1439, &mmBIF_VDDGFX_RSV3_UPPER[0], sizeof(mmBIF_VDDGFX_RSV3_UPPER)/sizeof(mmBIF_VDDGFX_RSV3_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV4_LOWER", REG_MMIO, 0x143a, &mmBIF_VDDGFX_RSV4_LOWER[0], sizeof(mmBIF_VDDGFX_RSV4_LOWER)/sizeof(mmBIF_VDDGFX_RSV4_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV4_UPPER", REG_MMIO, 0x143b, &mmBIF_VDDGFX_RSV4_UPPER[0], sizeof(mmBIF_VDDGFX_RSV4_UPPER)/sizeof(mmBIF_VDDGFX_RSV4_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_FB_CMP", REG_MMIO, 0x143c, &mmBIF_VDDGFX_FB_CMP[0], sizeof(mmBIF_VDDGFX_FB_CMP)/sizeof(mmBIF_VDDGFX_FB_CMP[0]), 0, 0 },
+	{ "mmBIF_SMU_INDEX", REG_MMIO, 0x143d, &mmBIF_SMU_INDEX[0], sizeof(mmBIF_SMU_INDEX)/sizeof(mmBIF_SMU_INDEX[0]), 0, 0 },
+	{ "mmBIF_SMU_DATA", REG_MMIO, 0x143e, &mmBIF_SMU_DATA[0], sizeof(mmBIF_SMU_DATA)/sizeof(mmBIF_SMU_DATA[0]), 0, 0 },
+	{ "mmBIF_RFE_SOFTRST_CNTL", REG_MMIO, 0x1441, &mmBIF_RFE_SOFTRST_CNTL[0], sizeof(mmBIF_RFE_SOFTRST_CNTL)/sizeof(mmBIF_RFE_SOFTRST_CNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_CLIENT_SOFTRST_TRIGGER", REG_MMIO, 0x1442, &mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[0], sizeof(mmBIF_RFE_CLIENT_SOFTRST_TRIGGER)/sizeof(mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[0]), 0, 0 },
+	{ "mmBIF_RFE_MASTER_SOFTRST_TRIGGER", REG_MMIO, 0x1443, &mmBIF_RFE_MASTER_SOFTRST_TRIGGER[0], sizeof(mmBIF_RFE_MASTER_SOFTRST_TRIGGER)/sizeof(mmBIF_RFE_MASTER_SOFTRST_TRIGGER[0]), 0, 0 },
+	{ "mmBIF_PWDN_COMMAND", REG_MMIO, 0x1444, &mmBIF_PWDN_COMMAND[0], sizeof(mmBIF_PWDN_COMMAND)/sizeof(mmBIF_PWDN_COMMAND[0]), 0, 0 },
+	{ "mmBIF_PWDN_STATUS", REG_MMIO, 0x1445, &mmBIF_PWDN_STATUS[0], sizeof(mmBIF_PWDN_STATUS)/sizeof(mmBIF_PWDN_STATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_BU_CMDSTATUS", REG_MMIO, 0x1446, &mmBIF_RFE_MST_BU_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_BU_CMDSTATUS)/sizeof(mmBIF_RFE_MST_BU_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS", REG_MMIO, 0x1447, &mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS)/sizeof(mmBIF_RFE_MST_RWREG_RFEWDBIF_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_SMBUS_CMDSTATUS", REG_MMIO, 0x1448, &mmBIF_RFE_MST_SMBUS_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_SMBUS_CMDSTATUS)/sizeof(mmBIF_RFE_MST_SMBUS_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_BX_CMDSTATUS", REG_MMIO, 0x1449, &mmBIF_RFE_MST_BX_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_BX_CMDSTATUS)/sizeof(mmBIF_RFE_MST_BX_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_TMOUT_STATUS", REG_MMIO, 0x144b, &mmBIF_RFE_MST_TMOUT_STATUS[0], sizeof(mmBIF_RFE_MST_TMOUT_STATUS)/sizeof(mmBIF_RFE_MST_TMOUT_STATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MMCFG_CNTL", REG_MMIO, 0x144c, &mmBIF_RFE_MMCFG_CNTL[0], sizeof(mmBIF_RFE_MMCFG_CNTL)/sizeof(mmBIF_RFE_MMCFG_CNTL[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_SMPLCNTL", REG_MMIO, 0x1450, &mmBIF_IMPCTL_SMPLCNTL[0], sizeof(mmBIF_IMPCTL_SMPLCNTL)/sizeof(mmBIF_IMPCTL_SMPLCNTL[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_RXCNTL", REG_MMIO, 0x1451, &mmBIF_IMPCTL_RXCNTL[0], sizeof(mmBIF_IMPCTL_RXCNTL)/sizeof(mmBIF_IMPCTL_RXCNTL[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_TXCNTL_pd", REG_MMIO, 0x1452, &mmBIF_IMPCTL_TXCNTL_pd[0], sizeof(mmBIF_IMPCTL_TXCNTL_pd)/sizeof(mmBIF_IMPCTL_TXCNTL_pd[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_TXCNTL_pu", REG_MMIO, 0x1453, &mmBIF_IMPCTL_TXCNTL_pu[0], sizeof(mmBIF_IMPCTL_TXCNTL_pu)/sizeof(mmBIF_IMPCTL_TXCNTL_pu[0]), 0, 0 },
+	{ "mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD", REG_MMIO, 0x1454, &mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD[0], sizeof(mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD)/sizeof(mmBIF_IMPCTL_CONTINUOUS_CALIBRATION_PERIOD[0]), 0, 0 },
+	{ "mmBIF_CC_RFE_IMP_OVERRIDECNTL", REG_MMIO, 0x1455, &mmBIF_CC_RFE_IMP_OVERRIDECNTL[0], sizeof(mmBIF_CC_RFE_IMP_OVERRIDECNTL)/sizeof(mmBIF_CC_RFE_IMP_OVERRIDECNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_IMPRST_CNTL", REG_MMIO, 0x1458, &mmBIF_RFE_IMPRST_CNTL[0], sizeof(mmBIF_RFE_IMPRST_CNTL)/sizeof(mmBIF_RFE_IMPRST_CNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_WARMRST_CNTL", REG_MMIO, 0x1459, &mmBIF_RFE_WARMRST_CNTL[0], sizeof(mmBIF_RFE_WARMRST_CNTL)/sizeof(mmBIF_RFE_WARMRST_CNTL[0]), 0, 0 },
+	{ "mmSWRST_COMMAND_STATUS", REG_MMIO, 0x14a0, &mmSWRST_COMMAND_STATUS[0], sizeof(mmSWRST_COMMAND_STATUS)/sizeof(mmSWRST_COMMAND_STATUS[0]), 0, 0 },
+	{ "mmSWRST_GENERAL_CONTROL", REG_MMIO, 0x14a1, &mmSWRST_GENERAL_CONTROL[0], sizeof(mmSWRST_GENERAL_CONTROL)/sizeof(mmSWRST_GENERAL_CONTROL[0]), 0, 0 },
+	{ "mmSWRST_COMMAND_0", REG_MMIO, 0x14a2, &mmSWRST_COMMAND_0[0], sizeof(mmSWRST_COMMAND_0)/sizeof(mmSWRST_COMMAND_0[0]), 0, 0 },
+	{ "mmSWRST_COMMAND_1", REG_MMIO, 0x14a3, &mmSWRST_COMMAND_1[0], sizeof(mmSWRST_COMMAND_1)/sizeof(mmSWRST_COMMAND_1[0]), 0, 0 },
+	{ "mmSWRST_CONTROL_0", REG_MMIO, 0x14a4, &mmSWRST_CONTROL_0[0], sizeof(mmSWRST_CONTROL_0)/sizeof(mmSWRST_CONTROL_0[0]), 0, 0 },
+	{ "mmSWRST_CONTROL_1", REG_MMIO, 0x14a5, &mmSWRST_CONTROL_1[0], sizeof(mmSWRST_CONTROL_1)/sizeof(mmSWRST_CONTROL_1[0]), 0, 0 },
+	{ "mmSWRST_CONTROL_2", REG_MMIO, 0x14a6, &mmSWRST_CONTROL_2[0], sizeof(mmSWRST_CONTROL_2)/sizeof(mmSWRST_CONTROL_2[0]), 0, 0 },
+	{ "mmSWRST_CONTROL_3", REG_MMIO, 0x14a7, &mmSWRST_CONTROL_3[0], sizeof(mmSWRST_CONTROL_3)/sizeof(mmSWRST_CONTROL_3[0]), 0, 0 },
+	{ "mmSWRST_CONTROL_4", REG_MMIO, 0x14a8, &mmSWRST_CONTROL_4[0], sizeof(mmSWRST_CONTROL_4)/sizeof(mmSWRST_CONTROL_4[0]), 0, 0 },
+	{ "mmSWRST_CONTROL_5", REG_MMIO, 0x14a9, &mmSWRST_CONTROL_5[0], sizeof(mmSWRST_CONTROL_5)/sizeof(mmSWRST_CONTROL_5[0]), 0, 0 },
+	{ "mmSWRST_CONTROL_6", REG_MMIO, 0x14aa, &mmSWRST_CONTROL_6[0], sizeof(mmSWRST_CONTROL_6)/sizeof(mmSWRST_CONTROL_6[0]), 0, 0 },
+	{ "mmSWRST_EP_COMMAND_0", REG_MMIO, 0x14ab, &mmSWRST_EP_COMMAND_0[0], sizeof(mmSWRST_EP_COMMAND_0)/sizeof(mmSWRST_EP_COMMAND_0[0]), 0, 0 },
+	{ "mmSWRST_EP_CONTROL_0", REG_MMIO, 0x14ac, &mmSWRST_EP_CONTROL_0[0], sizeof(mmSWRST_EP_CONTROL_0)/sizeof(mmSWRST_EP_CONTROL_0[0]), 0, 0 },
+	{ "mmCPM_CONTROL", REG_MMIO, 0x14b8, &mmCPM_CONTROL[0], sizeof(mmCPM_CONTROL)/sizeof(mmCPM_CONTROL[0]), 0, 0 },
+	{ "mmGSKT_CONTROL", REG_MMIO, 0x14bf, &mmGSKT_CONTROL[0], sizeof(mmGSKT_CONTROL)/sizeof(mmGSKT_CONTROL[0]), 0, 0 },
+	{ "mmBIF_XDMA_LO", REG_MMIO, 0x14c0, &mmBIF_XDMA_LO[0], sizeof(mmBIF_XDMA_LO)/sizeof(mmBIF_XDMA_LO[0]), 0, 0 },
+	{ "mmBIF_XDMA_HI", REG_MMIO, 0x14c1, &mmBIF_XDMA_HI[0], sizeof(mmBIF_XDMA_HI)/sizeof(mmBIF_XDMA_HI[0]), 0, 0 },
+	{ "mmBIF_FEATURES_CONTROL_MISC", REG_MMIO, 0x14c2, &mmBIF_FEATURES_CONTROL_MISC[0], sizeof(mmBIF_FEATURES_CONTROL_MISC)/sizeof(mmBIF_FEATURES_CONTROL_MISC[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_CNTL", REG_MMIO, 0x14c3, &mmBIF_DOORBELL_CNTL[0], sizeof(mmBIF_DOORBELL_CNTL)/sizeof(mmBIF_DOORBELL_CNTL[0]), 0, 0 },
+	{ "mmBIF_SLVARB_MODE", REG_MMIO, 0x14c4, &mmBIF_SLVARB_MODE[0], sizeof(mmBIF_SLVARB_MODE)/sizeof(mmBIF_SLVARB_MODE[0]), 0, 0 },
+	{ "mmBIF_CLK_CTRL", REG_MMIO, 0x14c5, &mmBIF_CLK_CTRL[0], sizeof(mmBIF_CLK_CTRL)/sizeof(mmBIF_CLK_CTRL[0]), 0, 0 },
+	{ "mmMAILBOX_INDEX", REG_MMIO, 0x14c6, &mmMAILBOX_INDEX[0], sizeof(mmMAILBOX_INDEX)/sizeof(mmMAILBOX_INDEX[0]), 0, 0 },
+	{ "mmBF_ANA_ISO_CNTL", REG_MMIO, 0x14c7, &mmBF_ANA_ISO_CNTL[0], sizeof(mmBF_ANA_ISO_CNTL)/sizeof(mmBF_ANA_ISO_CNTL[0]), 0, 0 },
+	{ "mmMAILBOX_MSGBUF_TRN_DW0", REG_MMIO, 0x14c8, &mmMAILBOX_MSGBUF_TRN_DW0[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW0)/sizeof(mmMAILBOX_MSGBUF_TRN_DW0[0]), 0, 0 },
+	{ "mmMAILBOX_MSGBUF_TRN_DW1", REG_MMIO, 0x14c9, &mmMAILBOX_MSGBUF_TRN_DW1[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW1)/sizeof(mmMAILBOX_MSGBUF_TRN_DW1[0]), 0, 0 },
+	{ "mmMAILBOX_MSGBUF_TRN_DW2", REG_MMIO, 0x14ca, &mmMAILBOX_MSGBUF_TRN_DW2[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW2)/sizeof(mmMAILBOX_MSGBUF_TRN_DW2[0]), 0, 0 },
+	{ "mmMAILBOX_MSGBUF_TRN_DW3", REG_MMIO, 0x14cb, &mmMAILBOX_MSGBUF_TRN_DW3[0], sizeof(mmMAILBOX_MSGBUF_TRN_DW3)/sizeof(mmMAILBOX_MSGBUF_TRN_DW3[0]), 0, 0 },
+	{ "mmMAILBOX_MSGBUF_RCV_DW0", REG_MMIO, 0x14cc, &mmMAILBOX_MSGBUF_RCV_DW0[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW0)/sizeof(mmMAILBOX_MSGBUF_RCV_DW0[0]), 0, 0 },
+	{ "mmMAILBOX_MSGBUF_RCV_DW1", REG_MMIO, 0x14cd, &mmMAILBOX_MSGBUF_RCV_DW1[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW1)/sizeof(mmMAILBOX_MSGBUF_RCV_DW1[0]), 0, 0 },
+	{ "mmMAILBOX_MSGBUF_RCV_DW2", REG_MMIO, 0x14ce, &mmMAILBOX_MSGBUF_RCV_DW2[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW2)/sizeof(mmMAILBOX_MSGBUF_RCV_DW2[0]), 0, 0 },
+	{ "mmMAILBOX_MSGBUF_RCV_DW3", REG_MMIO, 0x14cf, &mmMAILBOX_MSGBUF_RCV_DW3[0], sizeof(mmMAILBOX_MSGBUF_RCV_DW3)/sizeof(mmMAILBOX_MSGBUF_RCV_DW3[0]), 0, 0 },
+	{ "mmMAILBOX_CONTROL", REG_MMIO, 0x14d0, &mmMAILBOX_CONTROL[0], sizeof(mmMAILBOX_CONTROL)/sizeof(mmMAILBOX_CONTROL[0]), 0, 0 },
+	{ "mmMAILBOX_INT_CNTL", REG_MMIO, 0x14d1, &mmMAILBOX_INT_CNTL[0], sizeof(mmMAILBOX_INT_CNTL)/sizeof(mmMAILBOX_INT_CNTL[0]), 0, 0 },
+	{ "mmBIF_VIRT_RESET_REQ", REG_MMIO, 0x14d2, &mmBIF_VIRT_RESET_REQ[0], sizeof(mmBIF_VIRT_RESET_REQ)/sizeof(mmBIF_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmVM_INIT_STATUS", REG_MMIO, 0x14d3, &mmVM_INIT_STATUS[0], sizeof(mmVM_INIT_STATUS)/sizeof(mmVM_INIT_STATUS[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_RESET_NOTIFICATION", REG_MMIO, 0x14d5, &mmBIF_GPUIOV_RESET_NOTIFICATION[0], sizeof(mmBIF_GPUIOV_RESET_NOTIFICATION)/sizeof(mmBIF_GPUIOV_RESET_NOTIFICATION[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_VM_INIT_STATUS", REG_MMIO, 0x14d6, &mmBIF_GPUIOV_VM_INIT_STATUS[0], sizeof(mmBIF_GPUIOV_VM_INIT_STATUS)/sizeof(mmBIF_GPUIOV_VM_INIT_STATUS[0]), 0, 0 },
+	{ "mmBIF_GPUIOV_FB_TOTAL_FB_INFO", REG_MMIO, 0x14d8, &mmBIF_GPUIOV_FB_TOTAL_FB_INFO[0], sizeof(mmBIF_GPUIOV_FB_TOTAL_FB_INFO)/sizeof(mmBIF_GPUIOV_FB_TOTAL_FB_INFO[0]), 0, 0 },
+	{ "mmBACO_CNTL_MISC", REG_MMIO, 0x14db, &mmBACO_CNTL_MISC[0], sizeof(mmBACO_CNTL_MISC)/sizeof(mmBACO_CNTL_MISC[0]), 0, 0 },
+	{ "mmBIF_BACO_DEBUG_LATCH", REG_MMIO, 0x14dc, &mmBIF_BACO_DEBUG_LATCH[0], sizeof(mmBIF_BACO_DEBUG_LATCH)/sizeof(mmBIF_BACO_DEBUG_LATCH[0]), 0, 0 },
+	{ "mmBIF_BACO_DEBUG", REG_MMIO, 0x14df, &mmBIF_BACO_DEBUG[0], sizeof(mmBIF_BACO_DEBUG)/sizeof(mmBIF_BACO_DEBUG[0]), 0, 0 },
+	{ "mmMEM_TYPE_CNTL", REG_MMIO, 0x14e4, &mmMEM_TYPE_CNTL[0], sizeof(mmMEM_TYPE_CNTL)/sizeof(mmMEM_TYPE_CNTL[0]), 0, 0 },
+	{ "mmBACO_CNTL", REG_MMIO, 0x14e5, &mmBACO_CNTL[0], sizeof(mmBACO_CNTL)/sizeof(mmBACO_CNTL[0]), 0, 0 },
+	{ "mmBIF_DEVFUNCNUM_LIST1", REG_MMIO, 0x14e7, &mmBIF_DEVFUNCNUM_LIST1[0], sizeof(mmBIF_DEVFUNCNUM_LIST1)/sizeof(mmBIF_DEVFUNCNUM_LIST1[0]), 0, 0 },
+	{ "mmBIF_DEVFUNCNUM_LIST0", REG_MMIO, 0x14e8, &mmBIF_DEVFUNCNUM_LIST0[0], sizeof(mmBIF_DEVFUNCNUM_LIST0)/sizeof(mmBIF_DEVFUNCNUM_LIST0[0]), 0, 0 },
+	{ "mmBIF_SLV_TRANS_PENDING", REG_MMIO, 0x14e9, &mmBIF_SLV_TRANS_PENDING[0], sizeof(mmBIF_SLV_TRANS_PENDING)/sizeof(mmBIF_SLV_TRANS_PENDING[0]), 0, 0 },
+	{ "mmBIF_MST_TRANS_PENDING", REG_MMIO, 0x14ea, &mmBIF_MST_TRANS_PENDING[0], sizeof(mmBIF_MST_TRANS_PENDING)/sizeof(mmBIF_MST_TRANS_PENDING[0]), 0, 0 },
+	{ "mmDBG_SMB_BYPASS_SRBM_ACCESS", REG_MMIO, 0x14eb, &mmDBG_SMB_BYPASS_SRBM_ACCESS[0], sizeof(mmDBG_SMB_BYPASS_SRBM_ACCESS)/sizeof(mmDBG_SMB_BYPASS_SRBM_ACCESS[0]), 0, 0 },
+	{ "mmPEER3_FB_OFFSET_LO", REG_MMIO, 0x14ec, &mmPEER3_FB_OFFSET_LO[0], sizeof(mmPEER3_FB_OFFSET_LO)/sizeof(mmPEER3_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER3_FB_OFFSET_HI", REG_MMIO, 0x14ed, &mmPEER3_FB_OFFSET_HI[0], sizeof(mmPEER3_FB_OFFSET_HI)/sizeof(mmPEER3_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER2_FB_OFFSET_LO", REG_MMIO, 0x14ee, &mmPEER2_FB_OFFSET_LO[0], sizeof(mmPEER2_FB_OFFSET_LO)/sizeof(mmPEER2_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER2_FB_OFFSET_HI", REG_MMIO, 0x14ef, &mmPEER2_FB_OFFSET_HI[0], sizeof(mmPEER2_FB_OFFSET_HI)/sizeof(mmPEER2_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER1_FB_OFFSET_LO", REG_MMIO, 0x14f0, &mmPEER1_FB_OFFSET_LO[0], sizeof(mmPEER1_FB_OFFSET_LO)/sizeof(mmPEER1_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER1_FB_OFFSET_HI", REG_MMIO, 0x14f1, &mmPEER1_FB_OFFSET_HI[0], sizeof(mmPEER1_FB_OFFSET_HI)/sizeof(mmPEER1_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER0_FB_OFFSET_LO", REG_MMIO, 0x14f2, &mmPEER0_FB_OFFSET_LO[0], sizeof(mmPEER0_FB_OFFSET_LO)/sizeof(mmPEER0_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER0_FB_OFFSET_HI", REG_MMIO, 0x14f3, &mmPEER0_FB_OFFSET_HI[0], sizeof(mmPEER0_FB_OFFSET_HI)/sizeof(mmPEER0_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmIMPCTL_RESET", REG_MMIO, 0x14f5, &mmIMPCTL_RESET[0], sizeof(mmIMPCTL_RESET)/sizeof(mmIMPCTL_RESET[0]), 0, 0 },
+	{ "mmSMU_BIF_VDDGFX_PWR_STATUS", REG_MMIO, 0x14f8, &mmSMU_BIF_VDDGFX_PWR_STATUS[0], sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS)/sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_GBLAPER1_LOWER", REG_MMIO, 0x14fc, &mmBIF_DOORBELL_GBLAPER1_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_GBLAPER1_UPPER", REG_MMIO, 0x14fd, &mmBIF_DOORBELL_GBLAPER1_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_GBLAPER2_LOWER", REG_MMIO, 0x14fe, &mmBIF_DOORBELL_GBLAPER2_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_GBLAPER2_UPPER", REG_MMIO, 0x14ff, &mmBIF_DOORBELL_GBLAPER2_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER[0]), 0, 0 },
+	{ "mmPMI_STATUS_CNTL", REG_MMIO, 0x15, &mmPMI_STATUS_CNTL[0], sizeof(mmPMI_STATUS_CNTL)/sizeof(mmPMI_STATUS_CNTL[0]), 0, 0 },
+	{ "mmBIF_MM_INDACCESS_CNTL", REG_MMIO, 0x1500, &mmBIF_MM_INDACCESS_CNTL[0], sizeof(mmBIF_MM_INDACCESS_CNTL)/sizeof(mmBIF_MM_INDACCESS_CNTL[0]), 0, 0 },
+	{ "ixPCIE_HOLD_TRAINING_A", REG_SMC, 0x1500820, &ixPCIE_HOLD_TRAINING_A[0], sizeof(ixPCIE_HOLD_TRAINING_A)/sizeof(ixPCIE_HOLD_TRAINING_A[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_APER_EN", REG_MMIO, 0x1501, &mmBIF_DOORBELL_APER_EN[0], sizeof(mmBIF_DOORBELL_APER_EN)/sizeof(mmBIF_DOORBELL_APER_EN[0]), 0, 0 },
+	{ "mmCONFIG_RESERVED", REG_MMIO, 0x1502, &mmCONFIG_RESERVED[0], sizeof(mmCONFIG_RESERVED)/sizeof(mmCONFIG_RESERVED[0]), 0, 0 },
+	{ "mmBIF_IOV_FUNC_IDENTIFIER", REG_MMIO, 0x1503, &mmBIF_IOV_FUNC_IDENTIFIER[0], sizeof(mmBIF_IOV_FUNC_IDENTIFIER)/sizeof(mmBIF_IOV_FUNC_IDENTIFIER[0]), 0, 0 },
+	{ "mmBUS_CNTL", REG_MMIO, 0x1508, &mmBUS_CNTL[0], sizeof(mmBUS_CNTL)/sizeof(mmBUS_CNTL[0]), 0, 0 },
+	{ "ixLNCNT_CONTROL", REG_SMC, 0x1508030, &ixLNCNT_CONTROL[0], sizeof(ixLNCNT_CONTROL)/sizeof(ixLNCNT_CONTROL[0]), 0, 0 },
+	{ "ixCFG_LNC_WINDOW", REG_SMC, 0x1508031, &ixCFG_LNC_WINDOW[0], sizeof(ixCFG_LNC_WINDOW)/sizeof(ixCFG_LNC_WINDOW[0]), 0, 0 },
+	{ "ixLNCNT_QUAN_THRD", REG_SMC, 0x1508032, &ixLNCNT_QUAN_THRD[0], sizeof(ixLNCNT_QUAN_THRD)/sizeof(ixLNCNT_QUAN_THRD[0]), 0, 0 },
+	{ "ixLNCNT_WEIGHT", REG_SMC, 0x1508033, &ixLNCNT_WEIGHT[0], sizeof(ixLNCNT_WEIGHT)/sizeof(ixLNCNT_WEIGHT[0]), 0, 0 },
+	{ "ixLNC_TOTAL_WACC", REG_SMC, 0x1508034, &ixLNC_TOTAL_WACC[0], sizeof(ixLNC_TOTAL_WACC)/sizeof(ixLNC_TOTAL_WACC[0]), 0, 0 },
+	{ "ixLNC_BW_WACC", REG_SMC, 0x1508035, &ixLNC_BW_WACC[0], sizeof(ixLNC_BW_WACC)/sizeof(ixLNC_BW_WACC[0]), 0, 0 },
+	{ "ixLNC_CMN_WACC", REG_SMC, 0x1508036, &ixLNC_CMN_WACC[0], sizeof(ixLNC_CMN_WACC)/sizeof(ixLNC_CMN_WACC[0]), 0, 0 },
+	{ "mmCONFIG_CNTL", REG_MMIO, 0x1509, &mmCONFIG_CNTL[0], sizeof(mmCONFIG_CNTL)/sizeof(mmCONFIG_CNTL[0]), 0, 0 },
+	{ "mmCONFIG_MEMSIZE", REG_MMIO, 0x150a, &mmCONFIG_MEMSIZE[0], sizeof(mmCONFIG_MEMSIZE)/sizeof(mmCONFIG_MEMSIZE[0]), 0, 0 },
+	{ "mmCONFIG_F0_BASE", REG_MMIO, 0x150b, &mmCONFIG_F0_BASE[0], sizeof(mmCONFIG_F0_BASE)/sizeof(mmCONFIG_F0_BASE[0]), 0, 0 },
+	{ "mmCONFIG_APER_SIZE", REG_MMIO, 0x150c, &mmCONFIG_APER_SIZE[0], sizeof(mmCONFIG_APER_SIZE)/sizeof(mmCONFIG_APER_SIZE[0]), 0, 0 },
+	{ "mmCONFIG_REG_APER_SIZE", REG_MMIO, 0x150d, &mmCONFIG_REG_APER_SIZE[0], sizeof(mmCONFIG_REG_APER_SIZE)/sizeof(mmCONFIG_REG_APER_SIZE[0]), 0, 0 },
+	{ "mmBIF_SCRATCH0", REG_MMIO, 0x150e, &mmBIF_SCRATCH0[0], sizeof(mmBIF_SCRATCH0)/sizeof(mmBIF_SCRATCH0[0]), 0, 0 },
+	{ "mmBIF_SCRATCH1", REG_MMIO, 0x150f, &mmBIF_SCRATCH1[0], sizeof(mmBIF_SCRATCH1)/sizeof(mmBIF_SCRATCH1[0]), 0, 0 },
+	{ "mmBIF_RLC_INTR_CNTL", REG_MMIO, 0x1510, &mmBIF_RLC_INTR_CNTL[0], sizeof(mmBIF_RLC_INTR_CNTL)/sizeof(mmBIF_RLC_INTR_CNTL[0]), 0, 0 },
+	{ "mmBIF_BME_STATUS", REG_MMIO, 0x1511, &mmBIF_BME_STATUS[0], sizeof(mmBIF_BME_STATUS)/sizeof(mmBIF_BME_STATUS[0]), 0, 0 },
+	{ "mmBIF_ATOMIC_ERR_LOG", REG_MMIO, 0x1512, &mmBIF_ATOMIC_ERR_LOG[0], sizeof(mmBIF_ATOMIC_ERR_LOG)/sizeof(mmBIF_ATOMIC_ERR_LOG[0]), 0, 0 },
+	{ "mmMM_CFGREGS_CNTL", REG_MMIO, 0x1513, &mmMM_CFGREGS_CNTL[0], sizeof(mmMM_CFGREGS_CNTL)/sizeof(mmMM_CFGREGS_CNTL[0]), 0, 0 },
+	{ "mmBX_RESET_EN", REG_MMIO, 0x1514, &mmBX_RESET_EN[0], sizeof(mmBX_RESET_EN)/sizeof(mmBX_RESET_EN[0]), 0, 0 },
+	{ "mmHW_DEBUG", REG_MMIO, 0x1515, &mmHW_DEBUG[0], sizeof(mmHW_DEBUG)/sizeof(mmHW_DEBUG[0]), 0, 0 },
+	{ "mmMASTER_CREDIT_CNTL", REG_MMIO, 0x1516, &mmMASTER_CREDIT_CNTL[0], sizeof(mmMASTER_CREDIT_CNTL)/sizeof(mmMASTER_CREDIT_CNTL[0]), 0, 0 },
+	{ "mmSLAVE_REQ_CREDIT_CNTL", REG_MMIO, 0x1517, &mmSLAVE_REQ_CREDIT_CNTL[0], sizeof(mmSLAVE_REQ_CREDIT_CNTL)/sizeof(mmSLAVE_REQ_CREDIT_CNTL[0]), 0, 0 },
+	{ "mmBX_RESET_CNTL", REG_MMIO, 0x1518, &mmBX_RESET_CNTL[0], sizeof(mmBX_RESET_CNTL)/sizeof(mmBX_RESET_CNTL[0]), 0, 0 },
+	{ "mmINTERRUPT_CNTL", REG_MMIO, 0x151a, &mmINTERRUPT_CNTL[0], sizeof(mmINTERRUPT_CNTL)/sizeof(mmINTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmINTERRUPT_CNTL2", REG_MMIO, 0x151b, &mmINTERRUPT_CNTL2[0], sizeof(mmINTERRUPT_CNTL2)/sizeof(mmINTERRUPT_CNTL2[0]), 0, 0 },
+	{ "mmBIF_DEBUG_CNTL", REG_MMIO, 0x151c, &mmBIF_DEBUG_CNTL[0], sizeof(mmBIF_DEBUG_CNTL)/sizeof(mmBIF_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmBIF_DEBUG_MUX", REG_MMIO, 0x151d, &mmBIF_DEBUG_MUX[0], sizeof(mmBIF_DEBUG_MUX)/sizeof(mmBIF_DEBUG_MUX[0]), 0, 0 },
+	{ "mmBIF_DEBUG_OUT", REG_MMIO, 0x151e, &mmBIF_DEBUG_OUT[0], sizeof(mmBIF_DEBUG_OUT)/sizeof(mmBIF_DEBUG_OUT[0]), 0, 0 },
+	{ "mmHDP_MEM_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1520, &mmHDP_MEM_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmCLKREQB_PAD_CNTL", REG_MMIO, 0x1521, &mmCLKREQB_PAD_CNTL[0], sizeof(mmCLKREQB_PAD_CNTL)/sizeof(mmCLKREQB_PAD_CNTL[0]), 0, 0 },
+	{ "mmCLKREQB_PERF_COUNTER", REG_MMIO, 0x1522, &mmCLKREQB_PERF_COUNTER[0], sizeof(mmCLKREQB_PERF_COUNTER)/sizeof(mmCLKREQB_PERF_COUNTER[0]), 0, 0 },
+	{ "mmBIF_FB_EN", REG_MMIO, 0x1524, &mmBIF_FB_EN[0], sizeof(mmBIF_FB_EN)/sizeof(mmBIF_FB_EN[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_CNTL1", REG_MMIO, 0x1525, &mmBIF_BUSNUM_CNTL1[0], sizeof(mmBIF_BUSNUM_CNTL1)/sizeof(mmBIF_BUSNUM_CNTL1[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_LIST0", REG_MMIO, 0x1526, &mmBIF_BUSNUM_LIST0[0], sizeof(mmBIF_BUSNUM_LIST0)/sizeof(mmBIF_BUSNUM_LIST0[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_LIST1", REG_MMIO, 0x1527, &mmBIF_BUSNUM_LIST1[0], sizeof(mmBIF_BUSNUM_LIST1)/sizeof(mmBIF_BUSNUM_LIST1[0]), 0, 0 },
+	{ "mmHDP_REG_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1528, &mmHDP_REG_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmBIF_BUSY_DELAY_CNTR", REG_MMIO, 0x1529, &mmBIF_BUSY_DELAY_CNTR[0], sizeof(mmBIF_BUSY_DELAY_CNTR)/sizeof(mmBIF_BUSY_DELAY_CNTR[0]), 0, 0 },
+	{ "mmCC_BIF_BX_STRAP2", REG_MMIO, 0x152A, NULL, 0, 0, 0 },
+	{ "mmBIF_BUSNUM_CNTL2", REG_MMIO, 0x152b, &mmBIF_BUSNUM_CNTL2[0], sizeof(mmBIF_BUSNUM_CNTL2)/sizeof(mmBIF_BUSNUM_CNTL2[0]), 0, 0 },
+	{ "mmBIF_PERFMON_CNTL", REG_MMIO, 0x152c, &mmBIF_PERFMON_CNTL[0], sizeof(mmBIF_PERFMON_CNTL)/sizeof(mmBIF_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmBIF_PERFCOUNTER0_RESULT", REG_MMIO, 0x152d, &mmBIF_PERFCOUNTER0_RESULT[0], sizeof(mmBIF_PERFCOUNTER0_RESULT)/sizeof(mmBIF_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmBIF_PERFCOUNTER1_RESULT", REG_MMIO, 0x152e, &mmBIF_PERFCOUNTER1_RESULT[0], sizeof(mmBIF_PERFCOUNTER1_RESULT)/sizeof(mmBIF_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmBIF_RB_CNTL", REG_MMIO, 0x1530, &mmBIF_RB_CNTL[0], sizeof(mmBIF_RB_CNTL)/sizeof(mmBIF_RB_CNTL[0]), 0, 0 },
+	{ "mmBIF_RB_BASE", REG_MMIO, 0x1531, &mmBIF_RB_BASE[0], sizeof(mmBIF_RB_BASE)/sizeof(mmBIF_RB_BASE[0]), 0, 0 },
+	{ "mmBIF_RB_RPTR", REG_MMIO, 0x1532, &mmBIF_RB_RPTR[0], sizeof(mmBIF_RB_RPTR)/sizeof(mmBIF_RB_RPTR[0]), 0, 0 },
+	{ "mmBIF_RB_WPTR", REG_MMIO, 0x1533, &mmBIF_RB_WPTR[0], sizeof(mmBIF_RB_WPTR)/sizeof(mmBIF_RB_WPTR[0]), 0, 0 },
+	{ "mmBIF_RB_WPTR_ADDR_HI", REG_MMIO, 0x1534, &mmBIF_RB_WPTR_ADDR_HI[0], sizeof(mmBIF_RB_WPTR_ADDR_HI)/sizeof(mmBIF_RB_WPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmBIF_RB_WPTR_ADDR_LO", REG_MMIO, 0x1535, &mmBIF_RB_WPTR_ADDR_LO[0], sizeof(mmBIF_RB_WPTR_ADDR_LO)/sizeof(mmBIF_RB_WPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSLAVE_HANG_PROTECTION_CNTL", REG_MMIO, 0x1536, &mmSLAVE_HANG_PROTECTION_CNTL[0], sizeof(mmSLAVE_HANG_PROTECTION_CNTL)/sizeof(mmSLAVE_HANG_PROTECTION_CNTL[0]), 0, 0 },
+	{ "mmGPU_HDP_FLUSH_REQ", REG_MMIO, 0x1537, &mmGPU_HDP_FLUSH_REQ[0], sizeof(mmGPU_HDP_FLUSH_REQ)/sizeof(mmGPU_HDP_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_HDP_FLUSH_DONE", REG_MMIO, 0x1538, &mmGPU_HDP_FLUSH_DONE[0], sizeof(mmGPU_HDP_FLUSH_DONE)/sizeof(mmGPU_HDP_FLUSH_DONE[0]), 0, 0 },
+	{ "mmSLAVE_HANG_ERROR", REG_MMIO, 0x153b, &mmSLAVE_HANG_ERROR[0], sizeof(mmSLAVE_HANG_ERROR)/sizeof(mmSLAVE_HANG_ERROR[0]), 0, 0 },
+	{ "mmCAPTURE_HOST_BUSNUM", REG_MMIO, 0x153c, &mmCAPTURE_HOST_BUSNUM[0], sizeof(mmCAPTURE_HOST_BUSNUM)/sizeof(mmCAPTURE_HOST_BUSNUM[0]), 0, 0 },
+	{ "mmHOST_BUSNUM", REG_MMIO, 0x153d, &mmHOST_BUSNUM[0], sizeof(mmHOST_BUSNUM)/sizeof(mmHOST_BUSNUM[0]), 0, 0 },
+	{ "mmPEER_REG_RANGE0", REG_MMIO, 0x153e, &mmPEER_REG_RANGE0[0], sizeof(mmPEER_REG_RANGE0)/sizeof(mmPEER_REG_RANGE0[0]), 0, 0 },
+	{ "mmPEER_REG_RANGE1", REG_MMIO, 0x153f, &mmPEER_REG_RANGE1[0], sizeof(mmPEER_REG_RANGE1)/sizeof(mmPEER_REG_RANGE1[0]), 0, 0 },
+	{ "mmPCIE_CAP_LIST", REG_MMIO, 0x16, &mmPCIE_CAP_LIST[0], sizeof(mmPCIE_CAP_LIST)/sizeof(mmPCIE_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_CAP", REG_MMIO, 0x16, &mmPCIE_CAP[0], sizeof(mmPCIE_CAP)/sizeof(mmPCIE_CAP[0]), 0, 0 },
+	{ "mmDEVICE_CAP", REG_MMIO, 0x17, &mmDEVICE_CAP[0], sizeof(mmDEVICE_CAP)/sizeof(mmDEVICE_CAP[0]), 0, 0 },
+	{ "mmDEVICE_STATUS", REG_MMIO, 0x18, &mmDEVICE_STATUS[0], sizeof(mmDEVICE_STATUS)/sizeof(mmDEVICE_STATUS[0]), 0, 0 },
+	{ "mmDEVICE_CNTL", REG_MMIO, 0x18, &mmDEVICE_CNTL[0], sizeof(mmDEVICE_CNTL)/sizeof(mmDEVICE_CNTL[0]), 0, 0 },
+	{ "mmLINK_CAP", REG_MMIO, 0x19, &mmLINK_CAP[0], sizeof(mmLINK_CAP)/sizeof(mmLINK_CAP[0]), 0, 0 },
+	{ "mmLINK_STATUS", REG_MMIO, 0x1a, &mmLINK_STATUS[0], sizeof(mmLINK_STATUS)/sizeof(mmLINK_STATUS[0]), 0, 0 },
+	{ "mmLINK_CNTL", REG_MMIO, 0x1a, &mmLINK_CNTL[0], sizeof(mmLINK_CNTL)/sizeof(mmLINK_CNTL[0]), 0, 0 },
+	{ "mmDEVICE_CAP2", REG_MMIO, 0x1f, &mmDEVICE_CAP2[0], sizeof(mmDEVICE_CAP2)/sizeof(mmDEVICE_CAP2[0]), 0, 0 },
+	{ "mmPROG_INTERFACE", REG_MMIO, 0x2, &mmPROG_INTERFACE[0], sizeof(mmPROG_INTERFACE)/sizeof(mmPROG_INTERFACE[0]), 0, 0 },
+	{ "mmREVISION_ID", REG_MMIO, 0x2, &mmREVISION_ID[0], sizeof(mmREVISION_ID)/sizeof(mmREVISION_ID[0]), 0, 0 },
+	{ "mmBASE_CLASS", REG_MMIO, 0x2, &mmBASE_CLASS[0], sizeof(mmBASE_CLASS)/sizeof(mmBASE_CLASS[0]), 0, 0 },
+	{ "mmSUB_CLASS", REG_MMIO, 0x2, &mmSUB_CLASS[0], sizeof(mmSUB_CLASS)/sizeof(mmSUB_CLASS[0]), 0, 0 },
+	{ "mmDEVICE_STATUS2", REG_MMIO, 0x20, &mmDEVICE_STATUS2[0], sizeof(mmDEVICE_STATUS2)/sizeof(mmDEVICE_STATUS2[0]), 0, 0 },
+	{ "mmDEVICE_CNTL2", REG_MMIO, 0x20, &mmDEVICE_CNTL2[0], sizeof(mmDEVICE_CNTL2)/sizeof(mmDEVICE_CNTL2[0]), 0, 0 },
+	{ "mmLINK_CAP2", REG_MMIO, 0x21, &mmLINK_CAP2[0], sizeof(mmLINK_CAP2)/sizeof(mmLINK_CAP2[0]), 0, 0 },
+	{ "ixPB1_PIF_SCRATCH", REG_SMC, 0x2100001, &ixPB1_PIF_SCRATCH[0], sizeof(ixPB1_PIF_SCRATCH)/sizeof(ixPB1_PIF_SCRATCH[0]), 0, 0 },
+	{ "ixPB1_PIF_HW_DEBUG", REG_SMC, 0x2100002, &ixPB1_PIF_HW_DEBUG[0], sizeof(ixPB1_PIF_HW_DEBUG)/sizeof(ixPB1_PIF_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB1_PIF_STRAP_0", REG_SMC, 0x2100003, &ixPB1_PIF_STRAP_0[0], sizeof(ixPB1_PIF_STRAP_0)/sizeof(ixPB1_PIF_STRAP_0[0]), 0, 0 },
+	{ "ixPB1_PIF_CTRL", REG_SMC, 0x2100004, &ixPB1_PIF_CTRL[0], sizeof(ixPB1_PIF_CTRL)/sizeof(ixPB1_PIF_CTRL[0]), 0, 0 },
+	{ "ixPB1_PIF_TX_CTRL", REG_SMC, 0x2100008, &ixPB1_PIF_TX_CTRL[0], sizeof(ixPB1_PIF_TX_CTRL)/sizeof(ixPB1_PIF_TX_CTRL[0]), 0, 0 },
+	{ "ixPB1_PIF_TX_CTRL2", REG_SMC, 0x2100009, &ixPB1_PIF_TX_CTRL2[0], sizeof(ixPB1_PIF_TX_CTRL2)/sizeof(ixPB1_PIF_TX_CTRL2[0]), 0, 0 },
+	{ "ixPB1_PIF_RX_CTRL", REG_SMC, 0x210000a, &ixPB1_PIF_RX_CTRL[0], sizeof(ixPB1_PIF_RX_CTRL)/sizeof(ixPB1_PIF_RX_CTRL[0]), 0, 0 },
+	{ "ixPB1_PIF_RX_CTRL2", REG_SMC, 0x210000b, &ixPB1_PIF_RX_CTRL2[0], sizeof(ixPB1_PIF_RX_CTRL2)/sizeof(ixPB1_PIF_RX_CTRL2[0]), 0, 0 },
+	{ "ixPB1_PIF_GLB_OVRD", REG_SMC, 0x210000c, &ixPB1_PIF_GLB_OVRD[0], sizeof(ixPB1_PIF_GLB_OVRD)/sizeof(ixPB1_PIF_GLB_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_GLB_OVRD2", REG_SMC, 0x210000d, &ixPB1_PIF_GLB_OVRD2[0], sizeof(ixPB1_PIF_GLB_OVRD2)/sizeof(ixPB1_PIF_GLB_OVRD2[0]), 0, 0 },
+	{ "ixPB1_PIF_BIF_CMD_STATUS", REG_SMC, 0x2100010, &ixPB1_PIF_BIF_CMD_STATUS[0], sizeof(ixPB1_PIF_BIF_CMD_STATUS)/sizeof(ixPB1_PIF_BIF_CMD_STATUS[0]), 0, 0 },
+	{ "ixPB1_PIF_CMD_BUS_CTRL", REG_SMC, 0x2100011, &ixPB1_PIF_CMD_BUS_CTRL[0], sizeof(ixPB1_PIF_CMD_BUS_CTRL)/sizeof(ixPB1_PIF_CMD_BUS_CTRL[0]), 0, 0 },
+	{ "ixPB1_PIF_CMD_BUS_GLB_OVRD", REG_SMC, 0x2100013, &ixPB1_PIF_CMD_BUS_GLB_OVRD[0], sizeof(ixPB1_PIF_CMD_BUS_GLB_OVRD)/sizeof(ixPB1_PIF_CMD_BUS_GLB_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE0_OVRD", REG_SMC, 0x2100014, &ixPB1_PIF_LANE0_OVRD[0], sizeof(ixPB1_PIF_LANE0_OVRD)/sizeof(ixPB1_PIF_LANE0_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE0_OVRD2", REG_SMC, 0x2100015, &ixPB1_PIF_LANE0_OVRD2[0], sizeof(ixPB1_PIF_LANE0_OVRD2)/sizeof(ixPB1_PIF_LANE0_OVRD2[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE1_OVRD", REG_SMC, 0x2100016, &ixPB1_PIF_LANE1_OVRD[0], sizeof(ixPB1_PIF_LANE1_OVRD)/sizeof(ixPB1_PIF_LANE1_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE1_OVRD2", REG_SMC, 0x2100017, &ixPB1_PIF_LANE1_OVRD2[0], sizeof(ixPB1_PIF_LANE1_OVRD2)/sizeof(ixPB1_PIF_LANE1_OVRD2[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE2_OVRD", REG_SMC, 0x2100018, &ixPB1_PIF_LANE2_OVRD[0], sizeof(ixPB1_PIF_LANE2_OVRD)/sizeof(ixPB1_PIF_LANE2_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE2_OVRD2", REG_SMC, 0x2100019, &ixPB1_PIF_LANE2_OVRD2[0], sizeof(ixPB1_PIF_LANE2_OVRD2)/sizeof(ixPB1_PIF_LANE2_OVRD2[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE3_OVRD", REG_SMC, 0x210001a, &ixPB1_PIF_LANE3_OVRD[0], sizeof(ixPB1_PIF_LANE3_OVRD)/sizeof(ixPB1_PIF_LANE3_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE3_OVRD2", REG_SMC, 0x210001b, &ixPB1_PIF_LANE3_OVRD2[0], sizeof(ixPB1_PIF_LANE3_OVRD2)/sizeof(ixPB1_PIF_LANE3_OVRD2[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE4_OVRD", REG_SMC, 0x210001c, &ixPB1_PIF_LANE4_OVRD[0], sizeof(ixPB1_PIF_LANE4_OVRD)/sizeof(ixPB1_PIF_LANE4_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE4_OVRD2", REG_SMC, 0x210001d, &ixPB1_PIF_LANE4_OVRD2[0], sizeof(ixPB1_PIF_LANE4_OVRD2)/sizeof(ixPB1_PIF_LANE4_OVRD2[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE5_OVRD", REG_SMC, 0x210001e, &ixPB1_PIF_LANE5_OVRD[0], sizeof(ixPB1_PIF_LANE5_OVRD)/sizeof(ixPB1_PIF_LANE5_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE5_OVRD2", REG_SMC, 0x210001f, &ixPB1_PIF_LANE5_OVRD2[0], sizeof(ixPB1_PIF_LANE5_OVRD2)/sizeof(ixPB1_PIF_LANE5_OVRD2[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE6_OVRD", REG_SMC, 0x2100020, &ixPB1_PIF_LANE6_OVRD[0], sizeof(ixPB1_PIF_LANE6_OVRD)/sizeof(ixPB1_PIF_LANE6_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE6_OVRD2", REG_SMC, 0x2100021, &ixPB1_PIF_LANE6_OVRD2[0], sizeof(ixPB1_PIF_LANE6_OVRD2)/sizeof(ixPB1_PIF_LANE6_OVRD2[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE7_OVRD", REG_SMC, 0x2100022, &ixPB1_PIF_LANE7_OVRD[0], sizeof(ixPB1_PIF_LANE7_OVRD)/sizeof(ixPB1_PIF_LANE7_OVRD[0]), 0, 0 },
+	{ "ixPB1_PIF_LANE7_OVRD2", REG_SMC, 0x2100023, &ixPB1_PIF_LANE7_OVRD2[0], sizeof(ixPB1_PIF_LANE7_OVRD2)/sizeof(ixPB1_PIF_LANE7_OVRD2[0]), 0, 0 },
+	{ "mmLINK_STATUS2", REG_MMIO, 0x22, &mmLINK_STATUS2[0], sizeof(mmLINK_STATUS2)/sizeof(mmLINK_STATUS2[0]), 0, 0 },
+	{ "mmLINK_CNTL2", REG_MMIO, 0x22, &mmLINK_CNTL2[0], sizeof(mmLINK_CNTL2)/sizeof(mmLINK_CNTL2[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG0", REG_SMC, 0x2200004, &ixPB1_GLB_CTRL_REG0[0], sizeof(ixPB1_GLB_CTRL_REG0)/sizeof(ixPB1_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG1", REG_SMC, 0x2200008, &ixPB1_GLB_CTRL_REG1[0], sizeof(ixPB1_GLB_CTRL_REG1)/sizeof(ixPB1_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG2", REG_SMC, 0x220000c, &ixPB1_GLB_CTRL_REG2[0], sizeof(ixPB1_GLB_CTRL_REG2)/sizeof(ixPB1_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG3", REG_SMC, 0x2200010, &ixPB1_GLB_CTRL_REG3[0], sizeof(ixPB1_GLB_CTRL_REG3)/sizeof(ixPB1_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG4", REG_SMC, 0x2200014, &ixPB1_GLB_CTRL_REG4[0], sizeof(ixPB1_GLB_CTRL_REG4)/sizeof(ixPB1_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB1_GLB_CTRL_REG5", REG_SMC, 0x2200018, &ixPB1_GLB_CTRL_REG5[0], sizeof(ixPB1_GLB_CTRL_REG5)/sizeof(ixPB1_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x220001c, &ixPB1_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG1", REG_SMC, 0x2200020, &ixPB1_GLB_SCI_STAT_OVRD_REG1[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG1)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG2", REG_SMC, 0x2200024, &ixPB1_GLB_SCI_STAT_OVRD_REG2[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG2)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG3", REG_SMC, 0x2200028, &ixPB1_GLB_SCI_STAT_OVRD_REG3[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG3)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB1_GLB_SCI_STAT_OVRD_REG4", REG_SMC, 0x220002c, &ixPB1_GLB_SCI_STAT_OVRD_REG4[0], sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG4)/sizeof(ixPB1_GLB_SCI_STAT_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB1_GLB_OVRD_REG0", REG_SMC, 0x2200030, &ixPB1_GLB_OVRD_REG0[0], sizeof(ixPB1_GLB_OVRD_REG0)/sizeof(ixPB1_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_GLB_OVRD_REG1", REG_SMC, 0x2200034, &ixPB1_GLB_OVRD_REG1[0], sizeof(ixPB1_GLB_OVRD_REG1)/sizeof(ixPB1_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_GLB_OVRD_REG2", REG_SMC, 0x2200038, &ixPB1_GLB_OVRD_REG2[0], sizeof(ixPB1_GLB_OVRD_REG2)/sizeof(ixPB1_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB1_HW_DEBUG", REG_SMC, 0x2202004, &ixPB1_HW_DEBUG[0], sizeof(ixPB1_HW_DEBUG)/sizeof(ixPB1_HW_DEBUG[0]), 0, 0 },
+	{ "ixPB1_STRAP_GLB_REG0", REG_SMC, 0x2202020, &ixPB1_STRAP_GLB_REG0[0], sizeof(ixPB1_STRAP_GLB_REG0)/sizeof(ixPB1_STRAP_GLB_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_TX_REG0", REG_SMC, 0x2202024, &ixPB1_STRAP_TX_REG0[0], sizeof(ixPB1_STRAP_TX_REG0)/sizeof(ixPB1_STRAP_TX_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_RX_REG0", REG_SMC, 0x2202028, &ixPB1_STRAP_RX_REG0[0], sizeof(ixPB1_STRAP_RX_REG0)/sizeof(ixPB1_STRAP_RX_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_RX_REG1", REG_SMC, 0x220202c, &ixPB1_STRAP_RX_REG1[0], sizeof(ixPB1_STRAP_RX_REG1)/sizeof(ixPB1_STRAP_RX_REG1[0]), 0, 0 },
+	{ "ixPB1_STRAP_PLL_REG0", REG_SMC, 0x2202030, &ixPB1_STRAP_PLL_REG0[0], sizeof(ixPB1_STRAP_PLL_REG0)/sizeof(ixPB1_STRAP_PLL_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_PIN_REG0", REG_SMC, 0x2202034, &ixPB1_STRAP_PIN_REG0[0], sizeof(ixPB1_STRAP_PIN_REG0)/sizeof(ixPB1_STRAP_PIN_REG0[0]), 0, 0 },
+	{ "ixPB1_STRAP_GLB_REG1", REG_SMC, 0x2202038, &ixPB1_STRAP_GLB_REG1[0], sizeof(ixPB1_STRAP_GLB_REG1)/sizeof(ixPB1_STRAP_GLB_REG1[0]), 0, 0 },
+	{ "ixPB1_STRAP_GLB_REG2", REG_SMC, 0x220203c, &ixPB1_STRAP_GLB_REG2[0], sizeof(ixPB1_STRAP_GLB_REG2)/sizeof(ixPB1_STRAP_GLB_REG2[0]), 0, 0 },
+	{ "ixPB1_DFT_JIT_INJ_REG0", REG_SMC, 0x2203000, &ixPB1_DFT_JIT_INJ_REG0[0], sizeof(ixPB1_DFT_JIT_INJ_REG0)/sizeof(ixPB1_DFT_JIT_INJ_REG0[0]), 0, 0 },
+	{ "ixPB1_DFT_JIT_INJ_REG1", REG_SMC, 0x2203004, &ixPB1_DFT_JIT_INJ_REG1[0], sizeof(ixPB1_DFT_JIT_INJ_REG1)/sizeof(ixPB1_DFT_JIT_INJ_REG1[0]), 0, 0 },
+	{ "ixPB1_DFT_JIT_INJ_REG2", REG_SMC, 0x2203008, &ixPB1_DFT_JIT_INJ_REG2[0], sizeof(ixPB1_DFT_JIT_INJ_REG2)/sizeof(ixPB1_DFT_JIT_INJ_REG2[0]), 0, 0 },
+	{ "ixPB1_DFT_DEBUG_CTRL_REG0", REG_SMC, 0x220300c, &ixPB1_DFT_DEBUG_CTRL_REG0[0], sizeof(ixPB1_DFT_DEBUG_CTRL_REG0)/sizeof(ixPB1_DFT_DEBUG_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_DFT_JIT_INJ_STAT_REG0", REG_SMC, 0x2203010, &ixPB1_DFT_JIT_INJ_STAT_REG0[0], sizeof(ixPB1_DFT_JIT_INJ_STAT_REG0)/sizeof(ixPB1_DFT_JIT_INJ_STAT_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO_GLB_CTRL_REG0", REG_SMC, 0x2204000, &ixPB1_PLL_RO_GLB_CTRL_REG0[0], sizeof(ixPB1_PLL_RO_GLB_CTRL_REG0)/sizeof(ixPB1_PLL_RO_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO_GLB_OVRD_REG0", REG_SMC, 0x2204010, NULL, 0, 0, 0 },
+	{ "ixPB1_PLL_RO0_CTRL_REG0", REG_SMC, 0x2204440, &ixPB1_PLL_RO0_CTRL_REG0[0], sizeof(ixPB1_PLL_RO0_CTRL_REG0)/sizeof(ixPB1_PLL_RO0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO0_OVRD_REG0", REG_SMC, 0x2204450, &ixPB1_PLL_RO0_OVRD_REG0[0], sizeof(ixPB1_PLL_RO0_OVRD_REG0)/sizeof(ixPB1_PLL_RO0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO0_OVRD_REG1", REG_SMC, 0x2204454, &ixPB1_PLL_RO0_OVRD_REG1[0], sizeof(ixPB1_PLL_RO0_OVRD_REG1)/sizeof(ixPB1_PLL_RO0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204460, &ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204464, &ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204468, &ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0", REG_SMC, 0x220446c, &ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC0_CTRL_REG0", REG_SMC, 0x2204480, &ixPB1_PLL_LC0_CTRL_REG0[0], sizeof(ixPB1_PLL_LC0_CTRL_REG0)/sizeof(ixPB1_PLL_LC0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC0_OVRD_REG0", REG_SMC, 0x2204490, &ixPB1_PLL_LC0_OVRD_REG0[0], sizeof(ixPB1_PLL_LC0_OVRD_REG0)/sizeof(ixPB1_PLL_LC0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC0_OVRD_REG1", REG_SMC, 0x2204494, &ixPB1_PLL_LC0_OVRD_REG1[0], sizeof(ixPB1_PLL_LC0_OVRD_REG1)/sizeof(ixPB1_PLL_LC0_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204500, &ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204504, &ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0", REG_SMC, 0x2204508, &ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0", REG_SMC, 0x220450c, &ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG0", REG_SMC, 0x2206000, &ixPB1_RX_GLB_CTRL_REG0[0], sizeof(ixPB1_RX_GLB_CTRL_REG0)/sizeof(ixPB1_RX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG1", REG_SMC, 0x2206004, &ixPB1_RX_GLB_CTRL_REG1[0], sizeof(ixPB1_RX_GLB_CTRL_REG1)/sizeof(ixPB1_RX_GLB_CTRL_REG1[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG2", REG_SMC, 0x2206008, &ixPB1_RX_GLB_CTRL_REG2[0], sizeof(ixPB1_RX_GLB_CTRL_REG2)/sizeof(ixPB1_RX_GLB_CTRL_REG2[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG3", REG_SMC, 0x220600c, &ixPB1_RX_GLB_CTRL_REG3[0], sizeof(ixPB1_RX_GLB_CTRL_REG3)/sizeof(ixPB1_RX_GLB_CTRL_REG3[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG4", REG_SMC, 0x2206010, &ixPB1_RX_GLB_CTRL_REG4[0], sizeof(ixPB1_RX_GLB_CTRL_REG4)/sizeof(ixPB1_RX_GLB_CTRL_REG4[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG5", REG_SMC, 0x2206014, &ixPB1_RX_GLB_CTRL_REG5[0], sizeof(ixPB1_RX_GLB_CTRL_REG5)/sizeof(ixPB1_RX_GLB_CTRL_REG5[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG6", REG_SMC, 0x2206018, &ixPB1_RX_GLB_CTRL_REG6[0], sizeof(ixPB1_RX_GLB_CTRL_REG6)/sizeof(ixPB1_RX_GLB_CTRL_REG6[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG7", REG_SMC, 0x220601c, &ixPB1_RX_GLB_CTRL_REG7[0], sizeof(ixPB1_RX_GLB_CTRL_REG7)/sizeof(ixPB1_RX_GLB_CTRL_REG7[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_CTRL_REG8", REG_SMC, 0x2206020, &ixPB1_RX_GLB_CTRL_REG8[0], sizeof(ixPB1_RX_GLB_CTRL_REG8)/sizeof(ixPB1_RX_GLB_CTRL_REG8[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206028, &ixPB1_RX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_OVRD_REG0", REG_SMC, 0x2206030, &ixPB1_RX_GLB_OVRD_REG0[0], sizeof(ixPB1_RX_GLB_OVRD_REG0)/sizeof(ixPB1_RX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_GLB_OVRD_REG1", REG_SMC, 0x2206034, &ixPB1_RX_GLB_OVRD_REG1[0], sizeof(ixPB1_RX_GLB_OVRD_REG1)/sizeof(ixPB1_RX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_RX_LANE0_CTRL_REG0", REG_SMC, 0x2206440, &ixPB1_RX_LANE0_CTRL_REG0[0], sizeof(ixPB1_RX_LANE0_CTRL_REG0)/sizeof(ixPB1_RX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206448, &ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE1_CTRL_REG0", REG_SMC, 0x2206480, &ixPB1_RX_LANE1_CTRL_REG0[0], sizeof(ixPB1_RX_LANE1_CTRL_REG0)/sizeof(ixPB1_RX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206488, &ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE2_CTRL_REG0", REG_SMC, 0x2206500, &ixPB1_RX_LANE2_CTRL_REG0[0], sizeof(ixPB1_RX_LANE2_CTRL_REG0)/sizeof(ixPB1_RX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206508, &ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE3_CTRL_REG0", REG_SMC, 0x2206600, &ixPB1_RX_LANE3_CTRL_REG0[0], sizeof(ixPB1_RX_LANE3_CTRL_REG0)/sizeof(ixPB1_RX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206608, &ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE4_CTRL_REG0", REG_SMC, 0x2206800, &ixPB1_RX_LANE4_CTRL_REG0[0], sizeof(ixPB1_RX_LANE4_CTRL_REG0)/sizeof(ixPB1_RX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206848, &ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE5_CTRL_REG0", REG_SMC, 0x2206880, &ixPB1_RX_LANE5_CTRL_REG0[0], sizeof(ixPB1_RX_LANE5_CTRL_REG0)/sizeof(ixPB1_RX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206888, &ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE6_CTRL_REG0", REG_SMC, 0x2206900, &ixPB1_RX_LANE6_CTRL_REG0[0], sizeof(ixPB1_RX_LANE6_CTRL_REG0)/sizeof(ixPB1_RX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206908, &ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE7_CTRL_REG0", REG_SMC, 0x2206a00, &ixPB1_RX_LANE7_CTRL_REG0[0], sizeof(ixPB1_RX_LANE7_CTRL_REG0)/sizeof(ixPB1_RX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x2206a08, &ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE8_CTRL_REG0", REG_SMC, 0x2207440, &ixPB1_RX_LANE8_CTRL_REG0[0], sizeof(ixPB1_RX_LANE8_CTRL_REG0)/sizeof(ixPB1_RX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207448, &ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE9_CTRL_REG0", REG_SMC, 0x2207480, &ixPB1_RX_LANE9_CTRL_REG0[0], sizeof(ixPB1_RX_LANE9_CTRL_REG0)/sizeof(ixPB1_RX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207488, &ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE10_CTRL_REG0", REG_SMC, 0x2207500, &ixPB1_RX_LANE10_CTRL_REG0[0], sizeof(ixPB1_RX_LANE10_CTRL_REG0)/sizeof(ixPB1_RX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207508, &ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE11_CTRL_REG0", REG_SMC, 0x2207600, &ixPB1_RX_LANE11_CTRL_REG0[0], sizeof(ixPB1_RX_LANE11_CTRL_REG0)/sizeof(ixPB1_RX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207608, &ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE12_CTRL_REG0", REG_SMC, 0x2207840, &ixPB1_RX_LANE12_CTRL_REG0[0], sizeof(ixPB1_RX_LANE12_CTRL_REG0)/sizeof(ixPB1_RX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207848, &ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE13_CTRL_REG0", REG_SMC, 0x2207880, &ixPB1_RX_LANE13_CTRL_REG0[0], sizeof(ixPB1_RX_LANE13_CTRL_REG0)/sizeof(ixPB1_RX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207888, &ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE14_CTRL_REG0", REG_SMC, 0x2207900, &ixPB1_RX_LANE14_CTRL_REG0[0], sizeof(ixPB1_RX_LANE14_CTRL_REG0)/sizeof(ixPB1_RX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207908, &ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE15_CTRL_REG0", REG_SMC, 0x2207a00, &ixPB1_RX_LANE15_CTRL_REG0[0], sizeof(ixPB1_RX_LANE15_CTRL_REG0)/sizeof(ixPB1_RX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x2207a08, &ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_CTRL_REG0", REG_SMC, 0x2208000, &ixPB1_TX_GLB_CTRL_REG0[0], sizeof(ixPB1_TX_GLB_CTRL_REG0)/sizeof(ixPB1_TX_GLB_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_LANE_SKEW_CTRL", REG_SMC, 0x2208004, &ixPB1_TX_GLB_LANE_SKEW_CTRL[0], sizeof(ixPB1_TX_GLB_LANE_SKEW_CTRL)/sizeof(ixPB1_TX_GLB_LANE_SKEW_CTRL[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208010, &ixPB1_TX_GLB_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_GLB_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_GLB_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0", REG_SMC, 0x2208014, &ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0], sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0)/sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1", REG_SMC, 0x2208018, &ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0], sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1)/sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2", REG_SMC, 0x220801c, &ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0], sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2)/sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3", REG_SMC, 0x2208020, &ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0], sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3)/sizeof(ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG0", REG_SMC, 0x2208030, &ixPB1_TX_GLB_OVRD_REG0[0], sizeof(ixPB1_TX_GLB_OVRD_REG0)/sizeof(ixPB1_TX_GLB_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG1", REG_SMC, 0x2208034, &ixPB1_TX_GLB_OVRD_REG1[0], sizeof(ixPB1_TX_GLB_OVRD_REG1)/sizeof(ixPB1_TX_GLB_OVRD_REG1[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG2", REG_SMC, 0x2208038, &ixPB1_TX_GLB_OVRD_REG2[0], sizeof(ixPB1_TX_GLB_OVRD_REG2)/sizeof(ixPB1_TX_GLB_OVRD_REG2[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG3", REG_SMC, 0x220803c, &ixPB1_TX_GLB_OVRD_REG3[0], sizeof(ixPB1_TX_GLB_OVRD_REG3)/sizeof(ixPB1_TX_GLB_OVRD_REG3[0]), 0, 0 },
+	{ "ixPB1_TX_GLB_OVRD_REG4", REG_SMC, 0x2208040, &ixPB1_TX_GLB_OVRD_REG4[0], sizeof(ixPB1_TX_GLB_OVRD_REG4)/sizeof(ixPB1_TX_GLB_OVRD_REG4[0]), 0, 0 },
+	{ "ixPB1_TX_LANE0_CTRL_REG0", REG_SMC, 0x2208440, &ixPB1_TX_LANE0_CTRL_REG0[0], sizeof(ixPB1_TX_LANE0_CTRL_REG0)/sizeof(ixPB1_TX_LANE0_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE0_OVRD_REG0", REG_SMC, 0x2208444, &ixPB1_TX_LANE0_OVRD_REG0[0], sizeof(ixPB1_TX_LANE0_OVRD_REG0)/sizeof(ixPB1_TX_LANE0_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208448, &ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE1_CTRL_REG0", REG_SMC, 0x2208480, &ixPB1_TX_LANE1_CTRL_REG0[0], sizeof(ixPB1_TX_LANE1_CTRL_REG0)/sizeof(ixPB1_TX_LANE1_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE1_OVRD_REG0", REG_SMC, 0x2208484, &ixPB1_TX_LANE1_OVRD_REG0[0], sizeof(ixPB1_TX_LANE1_OVRD_REG0)/sizeof(ixPB1_TX_LANE1_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208488, &ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE2_CTRL_REG0", REG_SMC, 0x2208500, &ixPB1_TX_LANE2_CTRL_REG0[0], sizeof(ixPB1_TX_LANE2_CTRL_REG0)/sizeof(ixPB1_TX_LANE2_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE2_OVRD_REG0", REG_SMC, 0x2208504, &ixPB1_TX_LANE2_OVRD_REG0[0], sizeof(ixPB1_TX_LANE2_OVRD_REG0)/sizeof(ixPB1_TX_LANE2_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208508, &ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE3_CTRL_REG0", REG_SMC, 0x2208600, &ixPB1_TX_LANE3_CTRL_REG0[0], sizeof(ixPB1_TX_LANE3_CTRL_REG0)/sizeof(ixPB1_TX_LANE3_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE3_OVRD_REG0", REG_SMC, 0x2208604, &ixPB1_TX_LANE3_OVRD_REG0[0], sizeof(ixPB1_TX_LANE3_OVRD_REG0)/sizeof(ixPB1_TX_LANE3_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208608, &ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE4_CTRL_REG0", REG_SMC, 0x2208840, &ixPB1_TX_LANE4_CTRL_REG0[0], sizeof(ixPB1_TX_LANE4_CTRL_REG0)/sizeof(ixPB1_TX_LANE4_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE4_OVRD_REG0", REG_SMC, 0x2208844, &ixPB1_TX_LANE4_OVRD_REG0[0], sizeof(ixPB1_TX_LANE4_OVRD_REG0)/sizeof(ixPB1_TX_LANE4_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208848, &ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE5_CTRL_REG0", REG_SMC, 0x2208880, &ixPB1_TX_LANE5_CTRL_REG0[0], sizeof(ixPB1_TX_LANE5_CTRL_REG0)/sizeof(ixPB1_TX_LANE5_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE5_OVRD_REG0", REG_SMC, 0x2208884, &ixPB1_TX_LANE5_OVRD_REG0[0], sizeof(ixPB1_TX_LANE5_OVRD_REG0)/sizeof(ixPB1_TX_LANE5_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208888, &ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE6_CTRL_REG0", REG_SMC, 0x2208900, &ixPB1_TX_LANE6_CTRL_REG0[0], sizeof(ixPB1_TX_LANE6_CTRL_REG0)/sizeof(ixPB1_TX_LANE6_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE6_OVRD_REG0", REG_SMC, 0x2208904, &ixPB1_TX_LANE6_OVRD_REG0[0], sizeof(ixPB1_TX_LANE6_OVRD_REG0)/sizeof(ixPB1_TX_LANE6_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208908, &ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE7_CTRL_REG0", REG_SMC, 0x2208a00, &ixPB1_TX_LANE7_CTRL_REG0[0], sizeof(ixPB1_TX_LANE7_CTRL_REG0)/sizeof(ixPB1_TX_LANE7_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE7_OVRD_REG0", REG_SMC, 0x2208a04, &ixPB1_TX_LANE7_OVRD_REG0[0], sizeof(ixPB1_TX_LANE7_OVRD_REG0)/sizeof(ixPB1_TX_LANE7_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0", REG_SMC, 0x2208a08, &ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE8_CTRL_REG0", REG_SMC, 0x2209440, &ixPB1_TX_LANE8_CTRL_REG0[0], sizeof(ixPB1_TX_LANE8_CTRL_REG0)/sizeof(ixPB1_TX_LANE8_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE8_OVRD_REG0", REG_SMC, 0x2209444, &ixPB1_TX_LANE8_OVRD_REG0[0], sizeof(ixPB1_TX_LANE8_OVRD_REG0)/sizeof(ixPB1_TX_LANE8_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209448, &ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE9_CTRL_REG0", REG_SMC, 0x2209480, &ixPB1_TX_LANE9_CTRL_REG0[0], sizeof(ixPB1_TX_LANE9_CTRL_REG0)/sizeof(ixPB1_TX_LANE9_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE9_OVRD_REG0", REG_SMC, 0x2209484, &ixPB1_TX_LANE9_OVRD_REG0[0], sizeof(ixPB1_TX_LANE9_OVRD_REG0)/sizeof(ixPB1_TX_LANE9_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209488, &ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE10_CTRL_REG0", REG_SMC, 0x2209500, &ixPB1_TX_LANE10_CTRL_REG0[0], sizeof(ixPB1_TX_LANE10_CTRL_REG0)/sizeof(ixPB1_TX_LANE10_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE10_OVRD_REG0", REG_SMC, 0x2209504, &ixPB1_TX_LANE10_OVRD_REG0[0], sizeof(ixPB1_TX_LANE10_OVRD_REG0)/sizeof(ixPB1_TX_LANE10_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209508, &ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE11_CTRL_REG0", REG_SMC, 0x2209600, &ixPB1_TX_LANE11_CTRL_REG0[0], sizeof(ixPB1_TX_LANE11_CTRL_REG0)/sizeof(ixPB1_TX_LANE11_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE11_OVRD_REG0", REG_SMC, 0x2209604, &ixPB1_TX_LANE11_OVRD_REG0[0], sizeof(ixPB1_TX_LANE11_OVRD_REG0)/sizeof(ixPB1_TX_LANE11_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209608, &ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE12_CTRL_REG0", REG_SMC, 0x2209840, &ixPB1_TX_LANE12_CTRL_REG0[0], sizeof(ixPB1_TX_LANE12_CTRL_REG0)/sizeof(ixPB1_TX_LANE12_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE12_OVRD_REG0", REG_SMC, 0x2209844, &ixPB1_TX_LANE12_OVRD_REG0[0], sizeof(ixPB1_TX_LANE12_OVRD_REG0)/sizeof(ixPB1_TX_LANE12_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209848, &ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE13_CTRL_REG0", REG_SMC, 0x2209880, &ixPB1_TX_LANE13_CTRL_REG0[0], sizeof(ixPB1_TX_LANE13_CTRL_REG0)/sizeof(ixPB1_TX_LANE13_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE13_OVRD_REG0", REG_SMC, 0x2209884, &ixPB1_TX_LANE13_OVRD_REG0[0], sizeof(ixPB1_TX_LANE13_OVRD_REG0)/sizeof(ixPB1_TX_LANE13_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209888, &ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE14_CTRL_REG0", REG_SMC, 0x2209900, &ixPB1_TX_LANE14_CTRL_REG0[0], sizeof(ixPB1_TX_LANE14_CTRL_REG0)/sizeof(ixPB1_TX_LANE14_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE14_OVRD_REG0", REG_SMC, 0x2209904, &ixPB1_TX_LANE14_OVRD_REG0[0], sizeof(ixPB1_TX_LANE14_OVRD_REG0)/sizeof(ixPB1_TX_LANE14_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209908, &ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE15_CTRL_REG0", REG_SMC, 0x2209a00, &ixPB1_TX_LANE15_CTRL_REG0[0], sizeof(ixPB1_TX_LANE15_CTRL_REG0)/sizeof(ixPB1_TX_LANE15_CTRL_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE15_OVRD_REG0", REG_SMC, 0x2209a04, &ixPB1_TX_LANE15_OVRD_REG0[0], sizeof(ixPB1_TX_LANE15_OVRD_REG0)/sizeof(ixPB1_TX_LANE15_OVRD_REG0[0]), 0, 0 },
+	{ "ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0", REG_SMC, 0x2209a08, &ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0[0], sizeof(ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0)/sizeof(ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0[0]), 0, 0 },
+	{ "mmBIF_RFE_SNOOP_REG", REG_MMIO, 0x27, &mmBIF_RFE_SNOOP_REG[0], sizeof(mmBIF_RFE_SNOOP_REG)/sizeof(mmBIF_RFE_SNOOP_REG[0]), 0, 0 },
+	{ "mmMSI_CAP_LIST", REG_MMIO, 0x28, &mmMSI_CAP_LIST[0], sizeof(mmMSI_CAP_LIST)/sizeof(mmMSI_CAP_LIST[0]), 0, 0 },
+	{ "mmMSI_MSG_ADDR_LO", REG_MMIO, 0x29, &mmMSI_MSG_ADDR_LO[0], sizeof(mmMSI_MSG_ADDR_LO)/sizeof(mmMSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "mmMSI_MSG_ADDR_HI", REG_MMIO, 0x2a, &mmMSI_MSG_ADDR_HI[0], sizeof(mmMSI_MSG_ADDR_HI)/sizeof(mmMSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "mmMSI_MSG_DATA", REG_MMIO, 0x2a, &mmMSI_MSG_DATA[0], sizeof(mmMSI_MSG_DATA)/sizeof(mmMSI_MSG_DATA[0]), 0, 0 },
+	{ "mmMSI_MSG_DATA_64", REG_MMIO, 0x2b, &mmMSI_MSG_DATA_64[0], sizeof(mmMSI_MSG_DATA_64)/sizeof(mmMSI_MSG_DATA_64[0]), 0, 0 },
+	{ "mmMSI_MASK", REG_MMIO, 0x2b, &mmMSI_MASK[0], sizeof(mmMSI_MASK)/sizeof(mmMSI_MASK[0]), 0, 0 },
+	{ "mmMSI_PENDING", REG_MMIO, 0x2c, &mmMSI_PENDING[0], sizeof(mmMSI_PENDING)/sizeof(mmMSI_PENDING[0]), 0, 0 },
+	{ "mmMSI_PENDING_64", REG_MMIO, 0x2d, &mmMSI_PENDING_64[0], sizeof(mmMSI_PENDING_64)/sizeof(mmMSI_PENDING_64[0]), 0, 0 },
+	{ "mmCACHE_LINE", REG_MMIO, 0x3, &mmCACHE_LINE[0], sizeof(mmCACHE_LINE)/sizeof(mmCACHE_LINE[0]), 0, 0 },
+	{ "mmLATENCY", REG_MMIO, 0x3, &mmLATENCY[0], sizeof(mmLATENCY)/sizeof(mmLATENCY[0]), 0, 0 },
+	{ "mmHEADER", REG_MMIO, 0x3, &mmHEADER[0], sizeof(mmHEADER)/sizeof(mmHEADER[0]), 0, 0 },
+	{ "mmBIST", REG_MMIO, 0x3, &mmBIST[0], sizeof(mmBIST)/sizeof(mmBIST[0]), 0, 0 },
+	{ "mmMSIX_CAP_LIST", REG_MMIO, 0x30, &mmMSIX_CAP_LIST[0], sizeof(mmMSIX_CAP_LIST)/sizeof(mmMSIX_CAP_LIST[0]), 0, 0 },
+	{ "mmMSIX_TABLE", REG_MMIO, 0x31, &mmMSIX_TABLE[0], sizeof(mmMSIX_TABLE)/sizeof(mmMSIX_TABLE[0]), 0, 0 },
+	{ "mmMSIX_PBA", REG_MMIO, 0x32, &mmMSIX_PBA[0], sizeof(mmMSIX_PBA)/sizeof(mmMSIX_PBA[0]), 0, 0 },
+	{ "mmBASE_ADDR_1", REG_MMIO, 0x4, &mmBASE_ADDR_1[0], sizeof(mmBASE_ADDR_1)/sizeof(mmBASE_ADDR_1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_MMIO, 0x40, &mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR", REG_MMIO, 0x41, &mmPCIE_VENDOR_SPECIFIC_HDR[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC1", REG_MMIO, 0x42, &mmPCIE_VENDOR_SPECIFIC1[0], sizeof(mmPCIE_VENDOR_SPECIFIC1)/sizeof(mmPCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC2", REG_MMIO, 0x43, &mmPCIE_VENDOR_SPECIFIC2[0], sizeof(mmPCIE_VENDOR_SPECIFIC2)/sizeof(mmPCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "mmPCIE_VC_ENH_CAP_LIST", REG_MMIO, 0x44, &mmPCIE_VC_ENH_CAP_LIST[0], sizeof(mmPCIE_VC_ENH_CAP_LIST)/sizeof(mmPCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CAP_REG1", REG_MMIO, 0x45, &mmPCIE_PORT_VC_CAP_REG1[0], sizeof(mmPCIE_PORT_VC_CAP_REG1)/sizeof(mmPCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CAP_REG2", REG_MMIO, 0x46, &mmPCIE_PORT_VC_CAP_REG2[0], sizeof(mmPCIE_PORT_VC_CAP_REG2)/sizeof(mmPCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_STATUS", REG_MMIO, 0x47, &mmPCIE_PORT_VC_STATUS[0], sizeof(mmPCIE_PORT_VC_STATUS)/sizeof(mmPCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CNTL", REG_MMIO, 0x47, &mmPCIE_PORT_VC_CNTL[0], sizeof(mmPCIE_PORT_VC_CNTL)/sizeof(mmPCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_CAP", REG_MMIO, 0x48, &mmPCIE_VC0_RESOURCE_CAP[0], sizeof(mmPCIE_VC0_RESOURCE_CAP)/sizeof(mmPCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_CNTL", REG_MMIO, 0x49, &mmPCIE_VC0_RESOURCE_CNTL[0], sizeof(mmPCIE_VC0_RESOURCE_CNTL)/sizeof(mmPCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_STATUS", REG_MMIO, 0x4a, &mmPCIE_VC0_RESOURCE_STATUS[0], sizeof(mmPCIE_VC0_RESOURCE_STATUS)/sizeof(mmPCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_CAP", REG_MMIO, 0x4b, &mmPCIE_VC1_RESOURCE_CAP[0], sizeof(mmPCIE_VC1_RESOURCE_CAP)/sizeof(mmPCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_CNTL", REG_MMIO, 0x4c, &mmPCIE_VC1_RESOURCE_CNTL[0], sizeof(mmPCIE_VC1_RESOURCE_CNTL)/sizeof(mmPCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_STATUS", REG_MMIO, 0x4d, &mmPCIE_VC1_RESOURCE_STATUS[0], sizeof(mmPCIE_VC1_RESOURCE_STATUS)/sizeof(mmPCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "mmBASE_ADDR_2", REG_MMIO, 0x5, &mmBASE_ADDR_2[0], sizeof(mmBASE_ADDR_2)/sizeof(mmBASE_ADDR_2[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_MMIO, 0x50, &mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_DW1", REG_MMIO, 0x51, &mmPCIE_DEV_SERIAL_NUM_DW1[0], sizeof(mmPCIE_DEV_SERIAL_NUM_DW1)/sizeof(mmPCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_DW2", REG_MMIO, 0x52, &mmPCIE_DEV_SERIAL_NUM_DW2[0], sizeof(mmPCIE_DEV_SERIAL_NUM_DW2)/sizeof(mmPCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_MMIO, 0x54, &mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_STATUS", REG_MMIO, 0x55, &mmPCIE_UNCORR_ERR_STATUS[0], sizeof(mmPCIE_UNCORR_ERR_STATUS)/sizeof(mmPCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_MASK", REG_MMIO, 0x56, &mmPCIE_UNCORR_ERR_MASK[0], sizeof(mmPCIE_UNCORR_ERR_MASK)/sizeof(mmPCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_SEVERITY", REG_MMIO, 0x57, &mmPCIE_UNCORR_ERR_SEVERITY[0], sizeof(mmPCIE_UNCORR_ERR_SEVERITY)/sizeof(mmPCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "mmPCIE_CORR_ERR_STATUS", REG_MMIO, 0x58, &mmPCIE_CORR_ERR_STATUS[0], sizeof(mmPCIE_CORR_ERR_STATUS)/sizeof(mmPCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_CORR_ERR_MASK", REG_MMIO, 0x59, &mmPCIE_CORR_ERR_MASK[0], sizeof(mmPCIE_CORR_ERR_MASK)/sizeof(mmPCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "mmPCIE_ADV_ERR_CAP_CNTL", REG_MMIO, 0x5a, &mmPCIE_ADV_ERR_CAP_CNTL[0], sizeof(mmPCIE_ADV_ERR_CAP_CNTL)/sizeof(mmPCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG0", REG_MMIO, 0x5b, &mmPCIE_HDR_LOG0[0], sizeof(mmPCIE_HDR_LOG0)/sizeof(mmPCIE_HDR_LOG0[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG1", REG_MMIO, 0x5c, &mmPCIE_HDR_LOG1[0], sizeof(mmPCIE_HDR_LOG1)/sizeof(mmPCIE_HDR_LOG1[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_0", REG_MMIO, 0x5c9, &mmBIOS_SCRATCH_0[0], sizeof(mmBIOS_SCRATCH_0)/sizeof(mmBIOS_SCRATCH_0[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_1", REG_MMIO, 0x5ca, &mmBIOS_SCRATCH_1[0], sizeof(mmBIOS_SCRATCH_1)/sizeof(mmBIOS_SCRATCH_1[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_2", REG_MMIO, 0x5cb, &mmBIOS_SCRATCH_2[0], sizeof(mmBIOS_SCRATCH_2)/sizeof(mmBIOS_SCRATCH_2[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_3", REG_MMIO, 0x5cc, &mmBIOS_SCRATCH_3[0], sizeof(mmBIOS_SCRATCH_3)/sizeof(mmBIOS_SCRATCH_3[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_4", REG_MMIO, 0x5cd, &mmBIOS_SCRATCH_4[0], sizeof(mmBIOS_SCRATCH_4)/sizeof(mmBIOS_SCRATCH_4[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_5", REG_MMIO, 0x5ce, &mmBIOS_SCRATCH_5[0], sizeof(mmBIOS_SCRATCH_5)/sizeof(mmBIOS_SCRATCH_5[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_6", REG_MMIO, 0x5cf, &mmBIOS_SCRATCH_6[0], sizeof(mmBIOS_SCRATCH_6)/sizeof(mmBIOS_SCRATCH_6[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG2", REG_MMIO, 0x5d, &mmPCIE_HDR_LOG2[0], sizeof(mmPCIE_HDR_LOG2)/sizeof(mmPCIE_HDR_LOG2[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_7", REG_MMIO, 0x5d0, &mmBIOS_SCRATCH_7[0], sizeof(mmBIOS_SCRATCH_7)/sizeof(mmBIOS_SCRATCH_7[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_8", REG_MMIO, 0x5d1, &mmBIOS_SCRATCH_8[0], sizeof(mmBIOS_SCRATCH_8)/sizeof(mmBIOS_SCRATCH_8[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_9", REG_MMIO, 0x5d2, &mmBIOS_SCRATCH_9[0], sizeof(mmBIOS_SCRATCH_9)/sizeof(mmBIOS_SCRATCH_9[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_10", REG_MMIO, 0x5d3, &mmBIOS_SCRATCH_10[0], sizeof(mmBIOS_SCRATCH_10)/sizeof(mmBIOS_SCRATCH_10[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_11", REG_MMIO, 0x5d4, &mmBIOS_SCRATCH_11[0], sizeof(mmBIOS_SCRATCH_11)/sizeof(mmBIOS_SCRATCH_11[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_12", REG_MMIO, 0x5d5, &mmBIOS_SCRATCH_12[0], sizeof(mmBIOS_SCRATCH_12)/sizeof(mmBIOS_SCRATCH_12[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_13", REG_MMIO, 0x5d6, &mmBIOS_SCRATCH_13[0], sizeof(mmBIOS_SCRATCH_13)/sizeof(mmBIOS_SCRATCH_13[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_14", REG_MMIO, 0x5d7, &mmBIOS_SCRATCH_14[0], sizeof(mmBIOS_SCRATCH_14)/sizeof(mmBIOS_SCRATCH_14[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_15", REG_MMIO, 0x5d8, &mmBIOS_SCRATCH_15[0], sizeof(mmBIOS_SCRATCH_15)/sizeof(mmBIOS_SCRATCH_15[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG3", REG_MMIO, 0x5e, &mmPCIE_HDR_LOG3[0], sizeof(mmPCIE_HDR_LOG3)/sizeof(mmPCIE_HDR_LOG3[0]), 0, 0 },
+	{ "mmMM_INDEX_HI", REG_MMIO, 0x6, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT0_ADDR_LO", REG_MMIO, 0x6000, &mmPCIEMSIX_VECT0_ADDR_LO[0], sizeof(mmPCIEMSIX_VECT0_ADDR_LO)/sizeof(mmPCIEMSIX_VECT0_ADDR_LO[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT0_ADDR_HI", REG_MMIO, 0x6001, &mmPCIEMSIX_VECT0_ADDR_HI[0], sizeof(mmPCIEMSIX_VECT0_ADDR_HI)/sizeof(mmPCIEMSIX_VECT0_ADDR_HI[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT0_MSG_DATA", REG_MMIO, 0x6002, &mmPCIEMSIX_VECT0_MSG_DATA[0], sizeof(mmPCIEMSIX_VECT0_MSG_DATA)/sizeof(mmPCIEMSIX_VECT0_MSG_DATA[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT0_CONTROL", REG_MMIO, 0x6003, &mmPCIEMSIX_VECT0_CONTROL[0], sizeof(mmPCIEMSIX_VECT0_CONTROL)/sizeof(mmPCIEMSIX_VECT0_CONTROL[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT1_ADDR_LO", REG_MMIO, 0x6004, &mmPCIEMSIX_VECT1_ADDR_LO[0], sizeof(mmPCIEMSIX_VECT1_ADDR_LO)/sizeof(mmPCIEMSIX_VECT1_ADDR_LO[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT1_ADDR_HI", REG_MMIO, 0x6005, &mmPCIEMSIX_VECT1_ADDR_HI[0], sizeof(mmPCIEMSIX_VECT1_ADDR_HI)/sizeof(mmPCIEMSIX_VECT1_ADDR_HI[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT1_MSG_DATA", REG_MMIO, 0x6006, &mmPCIEMSIX_VECT1_MSG_DATA[0], sizeof(mmPCIEMSIX_VECT1_MSG_DATA)/sizeof(mmPCIEMSIX_VECT1_MSG_DATA[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT1_CONTROL", REG_MMIO, 0x6007, &mmPCIEMSIX_VECT1_CONTROL[0], sizeof(mmPCIEMSIX_VECT1_CONTROL)/sizeof(mmPCIEMSIX_VECT1_CONTROL[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT2_ADDR_LO", REG_MMIO, 0x6008, &mmPCIEMSIX_VECT2_ADDR_LO[0], sizeof(mmPCIEMSIX_VECT2_ADDR_LO)/sizeof(mmPCIEMSIX_VECT2_ADDR_LO[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT2_ADDR_HI", REG_MMIO, 0x6009, &mmPCIEMSIX_VECT2_ADDR_HI[0], sizeof(mmPCIEMSIX_VECT2_ADDR_HI)/sizeof(mmPCIEMSIX_VECT2_ADDR_HI[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT2_MSG_DATA", REG_MMIO, 0x600a, &mmPCIEMSIX_VECT2_MSG_DATA[0], sizeof(mmPCIEMSIX_VECT2_MSG_DATA)/sizeof(mmPCIEMSIX_VECT2_MSG_DATA[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT2_CONTROL", REG_MMIO, 0x600b, &mmPCIEMSIX_VECT2_CONTROL[0], sizeof(mmPCIEMSIX_VECT2_CONTROL)/sizeof(mmPCIEMSIX_VECT2_CONTROL[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT3_ADDR_LO", REG_MMIO, 0x600c, &mmPCIEMSIX_VECT3_ADDR_LO[0], sizeof(mmPCIEMSIX_VECT3_ADDR_LO)/sizeof(mmPCIEMSIX_VECT3_ADDR_LO[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT3_ADDR_HI", REG_MMIO, 0x600d, &mmPCIEMSIX_VECT3_ADDR_HI[0], sizeof(mmPCIEMSIX_VECT3_ADDR_HI)/sizeof(mmPCIEMSIX_VECT3_ADDR_HI[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT3_MSG_DATA", REG_MMIO, 0x600e, &mmPCIEMSIX_VECT3_MSG_DATA[0], sizeof(mmPCIEMSIX_VECT3_MSG_DATA)/sizeof(mmPCIEMSIX_VECT3_MSG_DATA[0]), 0, 0 },
+	{ "mmPCIEMSIX_VECT3_CONTROL", REG_MMIO, 0x600f, &mmPCIEMSIX_VECT3_CONTROL[0], sizeof(mmPCIEMSIX_VECT3_CONTROL)/sizeof(mmPCIEMSIX_VECT3_CONTROL[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG0", REG_MMIO, 0x62, &mmPCIE_TLP_PREFIX_LOG0[0], sizeof(mmPCIE_TLP_PREFIX_LOG0)/sizeof(mmPCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "mmPCIEMSIX_PBA", REG_MMIO, 0x6200, &mmPCIEMSIX_PBA[0], sizeof(mmPCIEMSIX_PBA)/sizeof(mmPCIEMSIX_PBA[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG1", REG_MMIO, 0x63, &mmPCIE_TLP_PREFIX_LOG1[0], sizeof(mmPCIE_TLP_PREFIX_LOG1)/sizeof(mmPCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG2", REG_MMIO, 0x64, &mmPCIE_TLP_PREFIX_LOG2[0], sizeof(mmPCIE_TLP_PREFIX_LOG2)/sizeof(mmPCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG3", REG_MMIO, 0x65, &mmPCIE_TLP_PREFIX_LOG3[0], sizeof(mmPCIE_TLP_PREFIX_LOG3)/sizeof(mmPCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "mmBASE_ADDR_4", REG_MMIO, 0x7, &mmBASE_ADDR_4[0], sizeof(mmBASE_ADDR_4)/sizeof(mmBASE_ADDR_4[0]), 0, 0 },
+	{ "mmBASE_ADDR_5", REG_MMIO, 0x8, &mmBASE_ADDR_5[0], sizeof(mmBASE_ADDR_5)/sizeof(mmBASE_ADDR_5[0]), 0, 0 },
+	{ "mmPCIE_BAR_ENH_CAP_LIST", REG_MMIO, 0x80, &mmPCIE_BAR_ENH_CAP_LIST[0], sizeof(mmPCIE_BAR_ENH_CAP_LIST)/sizeof(mmPCIE_BAR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_BAR1_CAP", REG_MMIO, 0x81, &mmPCIE_BAR1_CAP[0], sizeof(mmPCIE_BAR1_CAP)/sizeof(mmPCIE_BAR1_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR1_CNTL", REG_MMIO, 0x82, &mmPCIE_BAR1_CNTL[0], sizeof(mmPCIE_BAR1_CNTL)/sizeof(mmPCIE_BAR1_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR2_CAP", REG_MMIO, 0x83, &mmPCIE_BAR2_CAP[0], sizeof(mmPCIE_BAR2_CAP)/sizeof(mmPCIE_BAR2_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR2_CNTL", REG_MMIO, 0x84, &mmPCIE_BAR2_CNTL[0], sizeof(mmPCIE_BAR2_CNTL)/sizeof(mmPCIE_BAR2_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR3_CAP", REG_MMIO, 0x85, &mmPCIE_BAR3_CAP[0], sizeof(mmPCIE_BAR3_CAP)/sizeof(mmPCIE_BAR3_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR3_CNTL", REG_MMIO, 0x86, &mmPCIE_BAR3_CNTL[0], sizeof(mmPCIE_BAR3_CNTL)/sizeof(mmPCIE_BAR3_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR4_CAP", REG_MMIO, 0x87, &mmPCIE_BAR4_CAP[0], sizeof(mmPCIE_BAR4_CAP)/sizeof(mmPCIE_BAR4_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR4_CNTL", REG_MMIO, 0x88, &mmPCIE_BAR4_CNTL[0], sizeof(mmPCIE_BAR4_CNTL)/sizeof(mmPCIE_BAR4_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR5_CAP", REG_MMIO, 0x89, &mmPCIE_BAR5_CAP[0], sizeof(mmPCIE_BAR5_CAP)/sizeof(mmPCIE_BAR5_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR5_CNTL", REG_MMIO, 0x8a, &mmPCIE_BAR5_CNTL[0], sizeof(mmPCIE_BAR5_CNTL)/sizeof(mmPCIE_BAR5_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR6_CAP", REG_MMIO, 0x8b, &mmPCIE_BAR6_CAP[0], sizeof(mmPCIE_BAR6_CAP)/sizeof(mmPCIE_BAR6_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR6_CNTL", REG_MMIO, 0x8c, &mmPCIE_BAR6_CNTL[0], sizeof(mmPCIE_BAR6_CNTL)/sizeof(mmPCIE_BAR6_CNTL[0]), 0, 0 },
+	{ "mmBASE_ADDR_6", REG_MMIO, 0x9, &mmBASE_ADDR_6[0], sizeof(mmBASE_ADDR_6)/sizeof(mmBASE_ADDR_6[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_ENH_CAP_LIST", REG_MMIO, 0x90, &mmPCIE_PWR_BUDGET_ENH_CAP_LIST[0], sizeof(mmPCIE_PWR_BUDGET_ENH_CAP_LIST)/sizeof(mmPCIE_PWR_BUDGET_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_DATA_SELECT", REG_MMIO, 0x91, &mmPCIE_PWR_BUDGET_DATA_SELECT[0], sizeof(mmPCIE_PWR_BUDGET_DATA_SELECT)/sizeof(mmPCIE_PWR_BUDGET_DATA_SELECT[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_DATA", REG_MMIO, 0x92, &mmPCIE_PWR_BUDGET_DATA[0], sizeof(mmPCIE_PWR_BUDGET_DATA)/sizeof(mmPCIE_PWR_BUDGET_DATA[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_CAP", REG_MMIO, 0x93, &mmPCIE_PWR_BUDGET_CAP[0], sizeof(mmPCIE_PWR_BUDGET_CAP)/sizeof(mmPCIE_PWR_BUDGET_CAP[0]), 0, 0 },
+	{ "mmPCIE_DPA_ENH_CAP_LIST", REG_MMIO, 0x94, &mmPCIE_DPA_ENH_CAP_LIST[0], sizeof(mmPCIE_DPA_ENH_CAP_LIST)/sizeof(mmPCIE_DPA_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_DPA_CAP", REG_MMIO, 0x95, &mmPCIE_DPA_CAP[0], sizeof(mmPCIE_DPA_CAP)/sizeof(mmPCIE_DPA_CAP[0]), 0, 0 },
+	{ "mmPCIE_DPA_LATENCY_INDICATOR", REG_MMIO, 0x96, &mmPCIE_DPA_LATENCY_INDICATOR[0], sizeof(mmPCIE_DPA_LATENCY_INDICATOR)/sizeof(mmPCIE_DPA_LATENCY_INDICATOR[0]), 0, 0 },
+	{ "mmPCIE_DPA_STATUS", REG_MMIO, 0x97, &mmPCIE_DPA_STATUS[0], sizeof(mmPCIE_DPA_STATUS)/sizeof(mmPCIE_DPA_STATUS[0]), 0, 0 },
+	{ "mmPCIE_DPA_CNTL", REG_MMIO, 0x97, &mmPCIE_DPA_CNTL[0], sizeof(mmPCIE_DPA_CNTL)/sizeof(mmPCIE_DPA_CNTL[0]), 0, 0 },
+	{ "mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0", REG_MMIO, 0x98, &mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 },
+	{ "mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4", REG_MMIO, 0x99, &mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 },
+	{ "mmPCIE_SECONDARY_ENH_CAP_LIST", REG_MMIO, 0x9c, &mmPCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(mmPCIE_SECONDARY_ENH_CAP_LIST)/sizeof(mmPCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_LINK_CNTL3", REG_MMIO, 0x9d, &mmPCIE_LINK_CNTL3[0], sizeof(mmPCIE_LINK_CNTL3)/sizeof(mmPCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "mmPCIE_LANE_ERROR_STATUS", REG_MMIO, 0x9e, &mmPCIE_LANE_ERROR_STATUS[0], sizeof(mmPCIE_LANE_ERROR_STATUS)/sizeof(mmPCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_LANE_0_EQUALIZATION_CNTL", REG_MMIO, 0x9f, &mmPCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_2_EQUALIZATION_CNTL", REG_MMIO, 0xa0, &mmPCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_4_EQUALIZATION_CNTL", REG_MMIO, 0xa1, &mmPCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_6_EQUALIZATION_CNTL", REG_MMIO, 0xa2, &mmPCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_8_EQUALIZATION_CNTL", REG_MMIO, 0xa3, &mmPCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_10_EQUALIZATION_CNTL", REG_MMIO, 0xa4, &mmPCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_12_EQUALIZATION_CNTL", REG_MMIO, 0xa5, &mmPCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_14_EQUALIZATION_CNTL", REG_MMIO, 0xa6, &mmPCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ACS_ENH_CAP_LIST", REG_MMIO, 0xa8, &mmPCIE_ACS_ENH_CAP_LIST[0], sizeof(mmPCIE_ACS_ENH_CAP_LIST)/sizeof(mmPCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_ACS_CNTL", REG_MMIO, 0xa9, &mmPCIE_ACS_CNTL[0], sizeof(mmPCIE_ACS_CNTL)/sizeof(mmPCIE_ACS_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ACS_CAP", REG_MMIO, 0xa9, &mmPCIE_ACS_CAP[0], sizeof(mmPCIE_ACS_CAP)/sizeof(mmPCIE_ACS_CAP[0]), 0, 0 },
+	{ "mmPCIE_ATS_ENH_CAP_LIST", REG_MMIO, 0xac, &mmPCIE_ATS_ENH_CAP_LIST[0], sizeof(mmPCIE_ATS_ENH_CAP_LIST)/sizeof(mmPCIE_ATS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_ATS_CNTL", REG_MMIO, 0xad, &mmPCIE_ATS_CNTL[0], sizeof(mmPCIE_ATS_CNTL)/sizeof(mmPCIE_ATS_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ATS_CAP", REG_MMIO, 0xad, &mmPCIE_ATS_CAP[0], sizeof(mmPCIE_ATS_CAP)/sizeof(mmPCIE_ATS_CAP[0]), 0, 0 },
+	{ "mmADAPTER_ID", REG_MMIO, 0xb, &mmADAPTER_ID[0], sizeof(mmADAPTER_ID)/sizeof(mmADAPTER_ID[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_ENH_CAP_LIST", REG_MMIO, 0xb0, &mmPCIE_PAGE_REQ_ENH_CAP_LIST[0], sizeof(mmPCIE_PAGE_REQ_ENH_CAP_LIST)/sizeof(mmPCIE_PAGE_REQ_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_STATUS", REG_MMIO, 0xb1, &mmPCIE_PAGE_REQ_STATUS[0], sizeof(mmPCIE_PAGE_REQ_STATUS)/sizeof(mmPCIE_PAGE_REQ_STATUS[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_CNTL", REG_MMIO, 0xb1, &mmPCIE_PAGE_REQ_CNTL[0], sizeof(mmPCIE_PAGE_REQ_CNTL)/sizeof(mmPCIE_PAGE_REQ_CNTL[0]), 0, 0 },
+	{ "mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY", REG_MMIO, 0xb2, &mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[0], sizeof(mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY)/sizeof(mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[0]), 0, 0 },
+	{ "mmPCIE_OUTSTAND_PAGE_REQ_ALLOC", REG_MMIO, 0xb3, &mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[0], sizeof(mmPCIE_OUTSTAND_PAGE_REQ_ALLOC)/sizeof(mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[0]), 0, 0 },
+	{ "mmPCIE_PASID_ENH_CAP_LIST", REG_MMIO, 0xb4, &mmPCIE_PASID_ENH_CAP_LIST[0], sizeof(mmPCIE_PASID_ENH_CAP_LIST)/sizeof(mmPCIE_PASID_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PASID_CNTL", REG_MMIO, 0xb5, &mmPCIE_PASID_CNTL[0], sizeof(mmPCIE_PASID_CNTL)/sizeof(mmPCIE_PASID_CNTL[0]), 0, 0 },
+	{ "mmPCIE_PASID_CAP", REG_MMIO, 0xb5, &mmPCIE_PASID_CAP[0], sizeof(mmPCIE_PASID_CAP)/sizeof(mmPCIE_PASID_CAP[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_ENH_CAP_LIST", REG_MMIO, 0xb8, &mmPCIE_TPH_REQR_ENH_CAP_LIST[0], sizeof(mmPCIE_TPH_REQR_ENH_CAP_LIST)/sizeof(mmPCIE_TPH_REQR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_CAP", REG_MMIO, 0xb9, &mmPCIE_TPH_REQR_CAP[0], sizeof(mmPCIE_TPH_REQR_CAP)/sizeof(mmPCIE_TPH_REQR_CAP[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_CNTL", REG_MMIO, 0xba, &mmPCIE_TPH_REQR_CNTL[0], sizeof(mmPCIE_TPH_REQR_CNTL)/sizeof(mmPCIE_TPH_REQR_CNTL[0]), 0, 0 },
+	{ "mmPCIE_MC_ENH_CAP_LIST", REG_MMIO, 0xbc, &mmPCIE_MC_ENH_CAP_LIST[0], sizeof(mmPCIE_MC_ENH_CAP_LIST)/sizeof(mmPCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_MC_CNTL", REG_MMIO, 0xbd, &mmPCIE_MC_CNTL[0], sizeof(mmPCIE_MC_CNTL)/sizeof(mmPCIE_MC_CNTL[0]), 0, 0 },
+	{ "mmPCIE_MC_CAP", REG_MMIO, 0xbd, &mmPCIE_MC_CAP[0], sizeof(mmPCIE_MC_CAP)/sizeof(mmPCIE_MC_CAP[0]), 0, 0 },
+	{ "mmPCIE_MC_ADDR0", REG_MMIO, 0xbe, &mmPCIE_MC_ADDR0[0], sizeof(mmPCIE_MC_ADDR0)/sizeof(mmPCIE_MC_ADDR0[0]), 0, 0 },
+	{ "mmPCIE_MC_ADDR1", REG_MMIO, 0xbf, &mmPCIE_MC_ADDR1[0], sizeof(mmPCIE_MC_ADDR1)/sizeof(mmPCIE_MC_ADDR1[0]), 0, 0 },
+	{ "mmROM_BASE_ADDR", REG_MMIO, 0xc, &mmROM_BASE_ADDR[0], sizeof(mmROM_BASE_ADDR)/sizeof(mmROM_BASE_ADDR[0]), 0, 0 },
+	{ "mmPCIE_INDEX_2", REG_MMIO, 0xc, &mmPCIE_INDEX_2[0], sizeof(mmPCIE_INDEX_2)/sizeof(mmPCIE_INDEX_2[0]), 0, 0 },
+	{ "mmPCIE_MC_RCV0", REG_MMIO, 0xc0, &mmPCIE_MC_RCV0[0], sizeof(mmPCIE_MC_RCV0)/sizeof(mmPCIE_MC_RCV0[0]), 0, 0 },
+	{ "mmPCIE_MC_RCV1", REG_MMIO, 0xc1, &mmPCIE_MC_RCV1[0], sizeof(mmPCIE_MC_RCV1)/sizeof(mmPCIE_MC_RCV1[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_ALL0", REG_MMIO, 0xc2, &mmPCIE_MC_BLOCK_ALL0[0], sizeof(mmPCIE_MC_BLOCK_ALL0)/sizeof(mmPCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_ALL1", REG_MMIO, 0xc3, &mmPCIE_MC_BLOCK_ALL1[0], sizeof(mmPCIE_MC_BLOCK_ALL1)/sizeof(mmPCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_UNTRANSLATED_0", REG_MMIO, 0xc4, &mmPCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_UNTRANSLATED_1", REG_MMIO, 0xc5, &mmPCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "mmPCIE_LTR_ENH_CAP_LIST", REG_MMIO, 0xc8, &mmPCIE_LTR_ENH_CAP_LIST[0], sizeof(mmPCIE_LTR_ENH_CAP_LIST)/sizeof(mmPCIE_LTR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_LTR_CAP", REG_MMIO, 0xc9, &mmPCIE_LTR_CAP[0], sizeof(mmPCIE_LTR_CAP)/sizeof(mmPCIE_LTR_CAP[0]), 0, 0 },
+	{ "mmPCIE_ARI_ENH_CAP_LIST", REG_MMIO, 0xca, &mmPCIE_ARI_ENH_CAP_LIST[0], sizeof(mmPCIE_ARI_ENH_CAP_LIST)/sizeof(mmPCIE_ARI_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_ARI_CNTL", REG_MMIO, 0xcb, &mmPCIE_ARI_CNTL[0], sizeof(mmPCIE_ARI_CNTL)/sizeof(mmPCIE_ARI_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ARI_CAP", REG_MMIO, 0xcb, &mmPCIE_ARI_CAP[0], sizeof(mmPCIE_ARI_CAP)/sizeof(mmPCIE_ARI_CAP[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_ENH_CAP_LIST", REG_MMIO, 0xcc, &mmPCIE_SRIOV_ENH_CAP_LIST[0], sizeof(mmPCIE_SRIOV_ENH_CAP_LIST)/sizeof(mmPCIE_SRIOV_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_CAP", REG_MMIO, 0xcd, &mmPCIE_SRIOV_CAP[0], sizeof(mmPCIE_SRIOV_CAP)/sizeof(mmPCIE_SRIOV_CAP[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_CONTROL", REG_MMIO, 0xce, &mmPCIE_SRIOV_CONTROL[0], sizeof(mmPCIE_SRIOV_CONTROL)/sizeof(mmPCIE_SRIOV_CONTROL[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_STATUS", REG_MMIO, 0xce, &mmPCIE_SRIOV_STATUS[0], sizeof(mmPCIE_SRIOV_STATUS)/sizeof(mmPCIE_SRIOV_STATUS[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_INITIAL_VFS", REG_MMIO, 0xcf, &mmPCIE_SRIOV_INITIAL_VFS[0], sizeof(mmPCIE_SRIOV_INITIAL_VFS)/sizeof(mmPCIE_SRIOV_INITIAL_VFS[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_TOTAL_VFS", REG_MMIO, 0xcf, &mmPCIE_SRIOV_TOTAL_VFS[0], sizeof(mmPCIE_SRIOV_TOTAL_VFS)/sizeof(mmPCIE_SRIOV_TOTAL_VFS[0]), 0, 0 },
+	{ "mmPCIE_DATA_2", REG_MMIO, 0xd, &mmPCIE_DATA_2[0], sizeof(mmPCIE_DATA_2)/sizeof(mmPCIE_DATA_2[0]), 0, 0 },
+	{ "mmCAP_PTR", REG_MMIO, 0xd, &mmCAP_PTR[0], sizeof(mmCAP_PTR)/sizeof(mmCAP_PTR[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_FUNC_DEP_LINK", REG_MMIO, 0xd0, &mmPCIE_SRIOV_FUNC_DEP_LINK[0], sizeof(mmPCIE_SRIOV_FUNC_DEP_LINK)/sizeof(mmPCIE_SRIOV_FUNC_DEP_LINK[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_NUM_VFS", REG_MMIO, 0xd0, &mmPCIE_SRIOV_NUM_VFS[0], sizeof(mmPCIE_SRIOV_NUM_VFS)/sizeof(mmPCIE_SRIOV_NUM_VFS[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_FIRST_VF_OFFSET", REG_MMIO, 0xd1, &mmPCIE_SRIOV_FIRST_VF_OFFSET[0], sizeof(mmPCIE_SRIOV_FIRST_VF_OFFSET)/sizeof(mmPCIE_SRIOV_FIRST_VF_OFFSET[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_STRIDE", REG_MMIO, 0xd1, &mmPCIE_SRIOV_VF_STRIDE[0], sizeof(mmPCIE_SRIOV_VF_STRIDE)/sizeof(mmPCIE_SRIOV_VF_STRIDE[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_DEVICE_ID", REG_MMIO, 0xd2, &mmPCIE_SRIOV_VF_DEVICE_ID[0], sizeof(mmPCIE_SRIOV_VF_DEVICE_ID)/sizeof(mmPCIE_SRIOV_VF_DEVICE_ID[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE", REG_MMIO, 0xd3, &mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE[0], sizeof(mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE)/sizeof(mmPCIE_SRIOV_SUPPORTED_PAGE_SIZE[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_SYSTEM_PAGE_SIZE", REG_MMIO, 0xd4, &mmPCIE_SRIOV_SYSTEM_PAGE_SIZE[0], sizeof(mmPCIE_SRIOV_SYSTEM_PAGE_SIZE)/sizeof(mmPCIE_SRIOV_SYSTEM_PAGE_SIZE[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_BASE_ADDR_0", REG_MMIO, 0xd5, &mmPCIE_SRIOV_VF_BASE_ADDR_0[0], sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_0)/sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_0[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_BASE_ADDR_1", REG_MMIO, 0xd6, &mmPCIE_SRIOV_VF_BASE_ADDR_1[0], sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_1)/sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_1[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_BASE_ADDR_2", REG_MMIO, 0xd7, &mmPCIE_SRIOV_VF_BASE_ADDR_2[0], sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_2)/sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_2[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_BASE_ADDR_3", REG_MMIO, 0xd8, &mmPCIE_SRIOV_VF_BASE_ADDR_3[0], sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_3)/sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_3[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_BASE_ADDR_4", REG_MMIO, 0xd9, &mmPCIE_SRIOV_VF_BASE_ADDR_4[0], sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_4)/sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_4[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_BASE_ADDR_5", REG_MMIO, 0xda, &mmPCIE_SRIOV_VF_BASE_ADDR_5[0], sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_5)/sizeof(mmPCIE_SRIOV_VF_BASE_ADDR_5[0]), 0, 0 },
+	{ "mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET", REG_MMIO, 0xdb, &mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET[0], sizeof(mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET)/sizeof(mmPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET[0]), 0, 0 },
+	{ "mmPCIE_INDEX", REG_MMIO, 0xe, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
+	{ "mmINTERRUPT_LINE", REG_MMIO, 0xf, &mmINTERRUPT_LINE[0], sizeof(mmINTERRUPT_LINE)/sizeof(mmINTERRUPT_LINE[0]), 0, 0 },
+	{ "mmINTERRUPT_PIN", REG_MMIO, 0xf, &mmINTERRUPT_PIN[0], sizeof(mmINTERRUPT_PIN)/sizeof(mmINTERRUPT_PIN[0]), 0, 0 },
+	{ "mmMAX_LATENCY", REG_MMIO, 0xf, &mmMAX_LATENCY[0], sizeof(mmMAX_LATENCY)/sizeof(mmMAX_LATENCY[0]), 0, 0 },
+	{ "mmMIN_GRANT", REG_MMIO, 0xf, &mmMIN_GRANT[0], sizeof(mmMIN_GRANT)/sizeof(mmMIN_GRANT[0]), 0, 0 },
+	{ "mmPCIE_EFUSE", REG_MMIO, 0xfc0, &mmPCIE_EFUSE[0], sizeof(mmPCIE_EFUSE)/sizeof(mmPCIE_EFUSE[0]), 0, 0 },
+	{ "mmPCIE_EFUSE2", REG_MMIO, 0xfc1, &mmPCIE_EFUSE2[0], sizeof(mmPCIE_EFUSE2)/sizeof(mmPCIE_EFUSE2[0]), 0, 0 },
+	{ "mmPCIE_EFUSE3", REG_MMIO, 0xfc2, &mmPCIE_EFUSE3[0], sizeof(mmPCIE_EFUSE3)/sizeof(mmPCIE_EFUSE3[0]), 0, 0 },
+	{ "mmPCIE_EFUSE4", REG_MMIO, 0xfc3, &mmPCIE_EFUSE4[0], sizeof(mmPCIE_EFUSE4)/sizeof(mmPCIE_EFUSE4[0]), 0, 0 },
+	{ "mmPCIE_EFUSE5", REG_MMIO, 0xfc4, &mmPCIE_EFUSE5[0], sizeof(mmPCIE_EFUSE5)/sizeof(mmPCIE_EFUSE5[0]), 0, 0 },
+	{ "mmPCIE_EFUSE6", REG_MMIO, 0xfc5, &mmPCIE_EFUSE6[0], sizeof(mmPCIE_EFUSE6)/sizeof(mmPCIE_EFUSE6[0]), 0, 0 },
+	{ "mmPCIE_EFUSE7", REG_MMIO, 0xfc6, &mmPCIE_EFUSE7[0], sizeof(mmPCIE_EFUSE7)/sizeof(mmPCIE_EFUSE7[0]), 0, 0 },
diff --git a/src/lib/ip/bif51.c b/src/lib/ip/bif51.c
new file mode 100644
index 0000000..3ee2301
--- /dev/null
+++ b/src/lib/ip/bif51.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "bif51_bits.i"
+
+static const struct umr_reg bif51_registers[] = {
+#include "bif51_regs.i"
+};
+
+struct umr_ip_block *umr_create_bif51(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "bif51";
+	ip->no_regs = sizeof(bif51_registers)/sizeof(bif51_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(bif51_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, bif51_registers, sizeof(bif51_registers));
+	return ip;
+}
diff --git a/src/lib/ip/bif51_bits.i b/src/lib/ip/bif51_bits.i
new file mode 100644
index 0000000..c82e6a9
--- /dev/null
+++ b/src/lib/ip/bif51_bits.i
@@ -0,0 +1,17831 @@
+static struct umr_bitfield ixD2F1_PCIEP_RESERVED[] = {
+	 { "PCIEP_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_INDEX[] = {
+	 { "MM_OFFSET", 0, 30, &umr_bitfield_default },
+	 { "MM_APER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_SCRATCH[] = {
+	 { "PCIEP_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_DATA[] = {
+	 { "MM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTATUS[] = {
+	 { "INT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "CAP_LIST", 4, 4, &umr_bitfield_default },
+	 { "PCI_66_EN", 5, 5, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 7, 7, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 8, 8, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 9, 10, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 11, 11, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 12, 12, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 13, 13, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 14, 14, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_PORT_CNTL[] = {
+	 { "SLV_PORT_REQ_EN", 0, 0, &umr_bitfield_default },
+	 { "CI_SNOOP_OVERRIDE", 1, 1, &umr_bitfield_default },
+	 { "HOTPLUG_MSG_EN", 2, 2, &umr_bitfield_default },
+	 { "NATIVE_PME_EN", 3, 3, &umr_bitfield_default },
+	 { "PWR_FAULT_EN", 4, 4, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 5, 5, &umr_bitfield_default },
+	 { "SEQNUM_DEBUG_MODE", 6, 6, &umr_bitfield_default },
+	 { "CI_SLV_CPL_STATIC_ALLOC_LIMIT_S", 8, 14, &umr_bitfield_default },
+	 { "CI_MAX_CPL_PAYLOAD_SIZE_MODE", 16, 17, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_CPL_PAYLOAD_SIZE", 18, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_RESERVED[] = {
+	 { "PCIEP_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_SCRATCH[] = {
+	 { "PCIEP_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_PORT_CNTL[] = {
+	 { "SLV_PORT_REQ_EN", 0, 0, &umr_bitfield_default },
+	 { "CI_SNOOP_OVERRIDE", 1, 1, &umr_bitfield_default },
+	 { "HOTPLUG_MSG_EN", 2, 2, &umr_bitfield_default },
+	 { "NATIVE_PME_EN", 3, 3, &umr_bitfield_default },
+	 { "PWR_FAULT_EN", 4, 4, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 5, 5, &umr_bitfield_default },
+	 { "SEQNUM_DEBUG_MODE", 6, 6, &umr_bitfield_default },
+	 { "CI_SLV_CPL_STATIC_ALLOC_LIMIT_S", 8, 14, &umr_bitfield_default },
+	 { "CI_MAX_CPL_PAYLOAD_SIZE_MODE", 16, 17, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_CPL_PAYLOAD_SIZE", 18, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CNTL[] = {
+	 { "TX_SNR_OVERRIDE", 10, 11, &umr_bitfield_default },
+	 { "TX_RO_OVERRIDE", 12, 13, &umr_bitfield_default },
+	 { "TX_PACK_PACKET_DIS", 14, 14, &umr_bitfield_default },
+	 { "TX_FLUSH_TLP_DIS", 15, 15, &umr_bitfield_default },
+	 { "TX_CPL_PASS_P", 20, 20, &umr_bitfield_default },
+	 { "TX_NP_PASS_P", 21, 21, &umr_bitfield_default },
+	 { "TX_CLEAR_EXTRA_PM_REQS", 22, 22, &umr_bitfield_default },
+	 { "TX_FC_UPDATE_TIMEOUT_DIS", 23, 23, &umr_bitfield_default },
+	 { "TX_F0_TPH_DIS", 24, 24, &umr_bitfield_default },
+	 { "TX_F1_TPH_DIS", 25, 25, &umr_bitfield_default },
+	 { "TX_F2_TPH_DIS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REQUESTER_ID[] = {
+	 { "TX_REQUESTER_ID_FUNCTION", 0, 2, &umr_bitfield_default },
+	 { "TX_REQUESTER_ID_DEVICE", 3, 7, &umr_bitfield_default },
+	 { "TX_REQUESTER_ID_BUS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_VENDOR_SPECIFIC[] = {
+	 { "TX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REQUEST_NUM_CNTL[] = {
+	 { "TX_NUM_OUTSTANDING_NP", 24, 29, &umr_bitfield_default },
+	 { "TX_NUM_OUTSTANDING_NP_VC1_EN", 30, 30, &umr_bitfield_default },
+	 { "TX_NUM_OUTSTANDING_NP_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_SEQ[] = {
+	 { "TX_NEXT_TRANSMIT_SEQ", 0, 11, &umr_bitfield_default },
+	 { "TX_ACKD_SEQ", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_REPLAY[] = {
+	 { "TX_REPLAY_NUM", 0, 2, &umr_bitfield_default },
+	 { "TX_REPLAY_TIMER_OVERWRITE", 15, 15, &umr_bitfield_default },
+	 { "TX_REPLAY_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_ACK_LATENCY_LIMIT[] = {
+	 { "TX_ACK_LATENCY_LIMIT", 0, 11, &umr_bitfield_default },
+	 { "TX_ACK_LATENCY_LIMIT_OVERWRITE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_P[] = {
+	 { "TX_CREDITS_ADVT_PD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_NP[] = {
+	 { "TX_CREDITS_ADVT_NPD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_ADVT_CPL[] = {
+	 { "TX_CREDITS_ADVT_CPLD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_P[] = {
+	 { "TX_CREDITS_INIT_PD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_NP[] = {
+	 { "TX_CREDITS_INIT_NPD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_INIT_CPL[] = {
+	 { "TX_CREDITS_INIT_CPLD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_STATUS[] = {
+	 { "TX_CREDITS_ERR_PD", 0, 0, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_PH", 1, 1, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_NPD", 2, 2, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_NPH", 3, 3, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_CPLD", 4, 4, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_CPLH", 5, 5, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_PD", 16, 16, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_PH", 17, 17, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_NPD", 18, 18, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_NPH", 19, 19, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_CPLD", 20, 20, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_CPLH", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_CREDITS_FCU_THRESHOLD[] = {
+	 { "TX_FCU_THRESHOLD_P_VC0", 0, 2, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_NP_VC0", 4, 6, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_CPL_VC0", 8, 10, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_P_VC1", 16, 18, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_NP_VC1", 20, 22, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_CPL_VC1", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_PORT_LANE_STATUS[] = {
+	 { "PORT_LANE_REVERSAL", 0, 0, &umr_bitfield_default },
+	 { "PHY_LINK_WIDTH", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_P[] = {
+	 { "PD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "PH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_NP[] = {
+	 { "NPD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "NPH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_FC_CPL[] = {
+	 { "CPLD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "CPLH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_ERR_CNTL[] = {
+	 { "ERR_REPORTING_DIS", 0, 0, &umr_bitfield_default },
+	 { "STRAP_FIRST_RCVD_ERR_LOG", 1, 1, &umr_bitfield_default },
+	 { "RX_DROP_ECRC_FAILURES", 2, 2, &umr_bitfield_default },
+	 { "TX_GENERATE_LCRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_GENERATE_LCRC_ERR", 5, 5, &umr_bitfield_default },
+	 { "TX_GENERATE_ECRC_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_GENERATE_ECRC_ERR", 7, 7, &umr_bitfield_default },
+	 { "AER_HDR_LOG_TIMEOUT", 8, 10, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F0_TIMER_EXPIRED", 11, 11, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F1_TIMER_EXPIRED", 12, 12, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F2_TIMER_EXPIRED", 13, 13, &umr_bitfield_default },
+	 { "CI_P_SLV_BUF_RD_HALT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CI_NP_SLV_BUF_RD_HALT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "CI_SLV_BUF_HALT_RESET", 16, 16, &umr_bitfield_default },
+	 { "SEND_ERR_MSG_IMMEDIATELY", 17, 17, &umr_bitfield_default },
+	 { "STRAP_POISONED_ADVISORY_NONFATAL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL[] = {
+	 { "RX_IGNORE_IO_ERR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_BE_ERR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_MSG_ERR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_CRC_ERR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_CPL_ERR", 5, 5, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_IGNORE_LEN_MISMATCH_ERR", 7, 7, &umr_bitfield_default },
+	 { "RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default },
+	 { "RX_IGNORE_TC_ERR", 9, 9, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_UR", 10, 10, &umr_bitfield_default },
+	 { "RX_IGNORE_IO_UR", 11, 11, &umr_bitfield_default },
+	 { "RX_IGNORE_AT_ERR", 12, 12, &umr_bitfield_default },
+	 { "RX_NAK_IF_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RX_GEN_ONE_NAK", 14, 14, &umr_bitfield_default },
+	 { "RX_FC_INIT_FROM_REG", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT", 16, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_PCIE_CPL_TIMEOUT_DIS", 20, 20, &umr_bitfield_default },
+	 { "RX_IGNORE_SHORTPREFIX_ERR", 21, 21, &umr_bitfield_default },
+	 { "RX_IGNORE_MAXPREFIX_ERR", 22, 22, &umr_bitfield_default },
+	 { "RX_IGNORE_CPLPREFIX_ERR", 23, 23, &umr_bitfield_default },
+	 { "RX_IGNORE_INVALIDPASID_ERR", 24, 24, &umr_bitfield_default },
+	 { "RX_IGNORE_NOT_PASID_UR", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_EXPECTED_SEQNUM[] = {
+	 { "RX_EXPECTED_SEQNUM", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_VENDOR_SPECIFIC[] = {
+	 { "RX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+	 { "RX_VENDOR_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL3[] = {
+	 { "RX_IGNORE_RC_TRANSMRDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_TRANSMWRPASID_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_PRGRESPMSG_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVCPLPASID_UR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_P[] = {
+	 { "RX_CREDITS_ALLOCATED_PD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_NP[] = {
+	 { "RX_CREDITS_ALLOCATED_NPD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CREDITS_ALLOCATED_CPL[] = {
+	 { "RX_CREDITS_ALLOCATED_CPLD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL[] = {
+	 { "LC_DONT_ENTER_L23_IN_D0", 1, 1, &umr_bitfield_default },
+	 { "LC_RESET_L_IDLE_COUNT_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_RESET_LINK", 3, 3, &umr_bitfield_default },
+	 { "LC_16X_CLEAR_TX_PIPE", 4, 7, &umr_bitfield_default },
+	 { "LC_L0S_INACTIVITY", 8, 11, &umr_bitfield_default },
+	 { "LC_L1_INACTIVITY", 12, 15, &umr_bitfield_default },
+	 { "LC_PMI_TO_L1_DIS", 16, 16, &umr_bitfield_default },
+	 { "LC_INC_N_FTS_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_IDLE_IN_L1L23", 18, 19, &umr_bitfield_default },
+	 { "LC_FACTOR_IN_EXT_SYNC", 20, 20, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_PM_ACK_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_WAKE_FROM_L23", 22, 22, &umr_bitfield_default },
+	 { "LC_L1_IMMEDIATE_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_ASPM_TO_L1_DIS", 24, 24, &umr_bitfield_default },
+	 { "LC_DELAY_COUNT", 25, 26, &umr_bitfield_default },
+	 { "LC_DELAY_L0S_EXIT", 27, 27, &umr_bitfield_default },
+	 { "LC_DELAY_L1_EXIT", 28, 28, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_EL_IDLE", 29, 29, &umr_bitfield_default },
+	 { "LC_ESCAPE_L1L23_EN", 30, 30, &umr_bitfield_default },
+	 { "LC_GATE_RCVR_IDLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_TRAINING_CNTL[] = {
+	 { "LC_TRAINING_CNTL", 0, 3, &umr_bitfield_default },
+	 { "LC_COMPLIANCE_RECEIVE", 4, 4, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_MORE_NON_MATCHING_TS1", 5, 5, &umr_bitfield_default },
+	 { "LC_L0S_L1_TRAINING_CNTL_EN", 6, 6, &umr_bitfield_default },
+	 { "LC_L1_LONG_WAKE_FIX_EN", 7, 7, &umr_bitfield_default },
+	 { "LC_POWER_STATE", 8, 10, &umr_bitfield_default },
+	 { "LC_DONT_GO_TO_L0S_IF_L1_ARMED", 11, 11, &umr_bitfield_default },
+	 { "LC_INIT_SPD_CHG_WITH_CSR_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_DISABLE_TRAINING_BIT_ARCH", 13, 13, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_SKP", 16, 16, &umr_bitfield_default },
+	 { "LC_AUTONOMOUS_CHANGE_OFF", 17, 17, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAP_OFF", 18, 18, &umr_bitfield_default },
+	 { "LC_HW_LINK_DIS_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_LINK_DIS_BY_HW", 20, 20, &umr_bitfield_default },
+	 { "LC_STATIC_TX_PIPE_COUNT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_ASPM_L1_NAK_TIMER_SEL", 22, 23, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_R_SPEED", 24, 24, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_TEST", 25, 25, &umr_bitfield_default },
+	 { "LC_RESET_ASPM_L1_NAK_TIMER", 26, 26, &umr_bitfield_default },
+	 { "LC_SHORT_RCFG_TIMEOUT", 27, 27, &umr_bitfield_default },
+	 { "LC_ALLOW_TX_L1_CONTROL", 28, 28, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_FOM_VALID_AFTER_TRACK", 29, 29, &umr_bitfield_default },
+	 { "LC_EXTEND_EQ_REQ_TIME", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_LINK_WIDTH_CNTL[] = {
+	 { "LC_LINK_WIDTH", 0, 2, &umr_bitfield_default },
+	 { "LC_LINK_WIDTH_RD", 4, 6, &umr_bitfield_default },
+	 { "LC_RECONFIG_ARC_MISSING_ESCAPE", 7, 7, &umr_bitfield_default },
+	 { "LC_RECONFIG_NOW", 8, 8, &umr_bitfield_default },
+	 { "LC_RENEGOTIATION_SUPPORT", 9, 9, &umr_bitfield_default },
+	 { "LC_RENEGOTIATE_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_SHORT_RECONFIG_EN", 11, 11, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_SUPPORT", 12, 12, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_DIS", 13, 13, &umr_bitfield_default },
+	 { "LC_UPCFG_WAIT_FOR_RCVR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LC_UPCFG_TIMER_SEL", 15, 15, &umr_bitfield_default },
+	 { "LC_DEASSERT_TX_PDNB", 16, 16, &umr_bitfield_default },
+	 { "LC_L1_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_DYNLINK_MST_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_DUAL_END_RECONFIG_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LC_DYN_LANES_PWR_STATE", 21, 22, &umr_bitfield_default },
+	 { "LC_EQ_REVERSAL_LOGIC_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_N_FTS_CNTL[] = {
+	 { "LC_XMIT_N_FTS", 0, 7, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_OVERRIDE_EN", 8, 8, &umr_bitfield_default },
+	 { "LC_XMIT_FTS_BEFORE_RECOVERY", 9, 9, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_LIMIT", 16, 23, &umr_bitfield_default },
+	 { "LC_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_SPEED_CNTL[] = {
+	 { "LC_GEN2_EN_STRAP", 0, 0, &umr_bitfield_default },
+	 { "LC_GEN3_EN_STRAP", 1, 1, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE", 3, 4, &umr_bitfield_default },
+	 { "LC_FORCE_EN_SW_SPEED_CHANGE", 5, 5, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_SW_SPEED_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_FORCE_EN_HW_SPEED_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_HW_SPEED_CHANGE", 8, 8, &umr_bitfield_default },
+	 { "LC_INITIATE_LINK_SPEED_CHANGE", 9, 9, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPTS_ALLOWED", 10, 11, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPT_FAILED", 12, 12, &umr_bitfield_default },
+	 { "LC_CURRENT_DATA_RATE", 13, 14, &umr_bitfield_default },
+	 { "LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS", 15, 15, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_SPD_CHANGE_CNT", 16, 16, &umr_bitfield_default },
+	 { "LC_1_OR_MORE_TS2_SPEED_ARC_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN2", 18, 18, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN2", 19, 19, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN3", 20, 20, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN3", 21, 21, &umr_bitfield_default },
+	 { "LC_AUTO_RECOVERY_DIS", 22, 22, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_STATUS", 23, 23, &umr_bitfield_default },
+	 { "LC_DATA_RATE_ADVERTISED", 24, 25, &umr_bitfield_default },
+	 { "LC_CHECK_DATA_RATE", 26, 26, &umr_bitfield_default },
+	 { "LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN", 27, 27, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L0s_EN", 28, 28, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L1_EN", 29, 29, &umr_bitfield_default },
+	 { "LC_DONT_CHECK_EQTS_IN_RCFG", 30, 30, &umr_bitfield_default },
+	 { "LC_DELAY_COEFF_UPDATE_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE0[] = {
+	 { "LC_CURRENT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE1", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE2", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE1[] = {
+	 { "LC_PREV_STATE4", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE5", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE6", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE7", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE2[] = {
+	 { "LC_PREV_STATE8", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE9", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE10", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE11", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE3[] = {
+	 { "LC_PREV_STATE12", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE13", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE14", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE15", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE4[] = {
+	 { "LC_PREV_STATE16", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE17", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE18", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE19", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE5[] = {
+	 { "LC_PREV_STATE20", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE21", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE22", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE23", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL2[] = {
+	 { "LC_TIMED_OUT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_STATE_TIMED_OUT", 6, 6, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_BW_REDUCTION", 7, 7, &umr_bitfield_default },
+	 { "LC_MORE_TS2_EN", 8, 8, &umr_bitfield_default },
+	 { "LC_X12_NEGOTIATION_DIS", 9, 9, &umr_bitfield_default },
+	 { "LC_LINK_UP_REVERSAL_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_ILLEGAL_STATE", 11, 11, &umr_bitfield_default },
+	 { "LC_ILLEGAL_STATE_RESTART_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_OTHER_LANES_MODE", 13, 13, &umr_bitfield_default },
+	 { "LC_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "LC_DISABLE_INFERRED_ELEC_IDLE_DET", 16, 16, &umr_bitfield_default },
+	 { "LC_ALLOW_PDWN_IN_L1", 17, 17, &umr_bitfield_default },
+	 { "LC_ALLOW_PDWN_IN_L23", 18, 18, &umr_bitfield_default },
+	 { "LC_DEASSERT_RX_EN_IN_L0S", 19, 19, &umr_bitfield_default },
+	 { "LC_BLOCK_EL_IDLE_IN_L0", 20, 20, &umr_bitfield_default },
+	 { "LC_RCV_L0_TO_RCV_L0S_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_ASSERT_INACTIVE_DURING_HOLD", 22, 22, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_LANES_IN_LW_NEG", 23, 24, &umr_bitfield_default },
+	 { "LC_PWR_DOWN_NEG_OFF_LANES", 25, 25, &umr_bitfield_default },
+	 { "LC_DISABLE_LOST_SYM_LOCK_ARCS", 26, 26, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DIS", 27, 27, &umr_bitfield_default },
+	 { "LC_PMI_L1_WAIT_FOR_SLV_IDLE", 28, 28, &umr_bitfield_default },
+	 { "LC_TEST_TIMER_SEL", 29, 30, &umr_bitfield_default },
+	 { "LC_ENABLE_INFERRED_ELEC_IDLE_FOR_PI", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_BW_CHANGE_CNTL[] = {
+	 { "LC_BW_CHANGE_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "LC_HW_INIT_SPEED_CHANGE", 1, 1, &umr_bitfield_default },
+	 { "LC_SW_INIT_SPEED_CHANGE", 2, 2, &umr_bitfield_default },
+	 { "LC_OTHER_INIT_SPEED_CHANGE", 3, 3, &umr_bitfield_default },
+	 { "LC_RELIABILITY_SPEED_CHANGE", 4, 4, &umr_bitfield_default },
+	 { "LC_FAILED_SPEED_NEG", 5, 5, &umr_bitfield_default },
+	 { "LC_LONG_LW_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_SHORT_LW_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_OTHER", 8, 8, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_FAILED", 9, 9, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DETECT_MODE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CDR_CNTL[] = {
+	 { "LC_CDR_TEST_OFF", 0, 11, &umr_bitfield_default },
+	 { "LC_CDR_TEST_SETS", 12, 23, &umr_bitfield_default },
+	 { "LC_CDR_SET_TYPE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_LANE_CNTL[] = {
+	 { "LC_CORRUPTED_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_LANE_DIS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL3[] = {
+	 { "LC_SELECT_DEEMPHASIS", 0, 0, &umr_bitfield_default },
+	 { "LC_SELECT_DEEMPHASIS_CNTL", 1, 2, &umr_bitfield_default },
+	 { "LC_RCVD_DEEMPHASIS", 3, 3, &umr_bitfield_default },
+	 { "LC_COMP_TO_DETECT", 4, 4, &umr_bitfield_default },
+	 { "LC_RESET_TSX_CNT_IN_RLOCK_EN", 5, 5, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED", 6, 7, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED", 8, 8, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT", 9, 9, &umr_bitfield_default },
+	 { "LC_ENHANCED_HOT_PLUG_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_RCVR_DET_EN_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "LC_EHP_RX_PHY_CMD", 12, 13, &umr_bitfield_default },
+	 { "LC_EHP_TX_PHY_CMD", 14, 15, &umr_bitfield_default },
+	 { "LC_CHIP_BIF_USB_IDLE_EN", 16, 16, &umr_bitfield_default },
+	 { "LC_L1_BLOCK_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL", 19, 20, &umr_bitfield_default },
+	 { "LC_FAST_L1_ENTRY_EXIT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_RXPHYCMD_INACTIVE_EN_MODE", 22, 22, &umr_bitfield_default },
+	 { "LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_HW_VOLTAGE_IF_CONTROL", 24, 25, &umr_bitfield_default },
+	 { "LC_VOLTAGE_TIMER_SEL", 26, 29, &umr_bitfield_default },
+	 { "LC_GO_TO_RECOVERY", 30, 30, &umr_bitfield_default },
+	 { "LC_N_EIE_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL4[] = {
+	 { "LC_TX_ENABLE_BEHAVIOUR", 0, 1, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ", 4, 4, &umr_bitfield_default },
+	 { "LC_REDO_EQ", 5, 5, &umr_bitfield_default },
+	 { "LC_EXTEND_EIEOS", 6, 6, &umr_bitfield_default },
+	 { "LC_IGNORE_PARITY", 7, 7, &umr_bitfield_default },
+	 { "LC_EQ_SEARCH_MODE", 8, 9, &umr_bitfield_default },
+	 { "LC_DSC_CHECK_COEFFS_IN_RLOCK", 10, 10, &umr_bitfield_default },
+	 { "LC_USC_EQ_NOT_REQD", 11, 11, &umr_bitfield_default },
+	 { "LC_USC_GO_TO_EQ", 12, 12, &umr_bitfield_default },
+	 { "LC_SET_QUIESCE", 13, 13, &umr_bitfield_default },
+	 { "LC_QUIESCE_RCVD", 14, 14, &umr_bitfield_default },
+	 { "LC_UNEXPECTED_COEFFS_RCVD", 15, 15, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ_REQ_PHASE", 16, 16, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_IN_EQ_REQ_PHASE", 17, 17, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_VALUE", 18, 21, &umr_bitfield_default },
+	 { "LC_USC_DELAY_DLLPS", 22, 22, &umr_bitfield_default },
+	 { "LC_PCIE_TX_FULL_SWING", 23, 23, &umr_bitfield_default },
+	 { "LC_EQ_WAIT_FOR_EVAL_DONE", 24, 24, &umr_bitfield_default },
+	 { "LC_8GT_SKIP_ORDER_EN", 25, 25, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_MORE_TS_IN_RLOCK", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_CNTL5[] = {
+	 { "LC_EQ_FS_0", 0, 5, &umr_bitfield_default },
+	 { "LC_EQ_FS_8", 6, 11, &umr_bitfield_default },
+	 { "LC_EQ_LF_0", 12, 17, &umr_bitfield_default },
+	 { "LC_EQ_LF_8", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_FORCE_COEFF[] = {
+	 { "LC_FORCE_COEFF", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR", 1, 6, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR", 13, 18, &umr_bitfield_default },
+	 { "LC_3X3_COEFF_SEARCH_EN", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_BEST_EQ_SETTINGS[] = {
+	 { "LC_BEST_PRESET", 0, 3, &umr_bitfield_default },
+	 { "LC_BEST_PRECURSOR", 4, 9, &umr_bitfield_default },
+	 { "LC_BEST_CURSOR", 10, 15, &umr_bitfield_default },
+	 { "LC_BEST_POSTCURSOR", 16, 21, &umr_bitfield_default },
+	 { "LC_BEST_FOM", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_FORCE_EQ_REQ_COEFF[] = {
+	 { "LC_FORCE_COEFF_IN_EQ_REQ_PHASE", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR_REQ", 1, 6, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR_REQ", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR_REQ", 13, 18, &umr_bitfield_default },
+	 { "LC_FS_OTHER_END", 19, 24, &umr_bitfield_default },
+	 { "LC_LF_OTHER_END", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_STRAP_LC[] = {
+	 { "STRAP_FTS_yTSx_COUNT", 0, 1, &umr_bitfield_default },
+	 { "STRAP_LONG_yTSx_COUNT", 2, 3, &umr_bitfield_default },
+	 { "STRAP_MED_yTSx_COUNT", 4, 5, &umr_bitfield_default },
+	 { "STRAP_SHORT_yTSx_COUNT", 6, 7, &umr_bitfield_default },
+	 { "STRAP_SKIP_INTERVAL", 8, 10, &umr_bitfield_default },
+	 { "STRAP_BYPASS_RCVR_DET", 11, 11, &umr_bitfield_default },
+	 { "STRAP_COMPLIANCE_DIS", 12, 12, &umr_bitfield_default },
+	 { "STRAP_FORCE_COMPLIANCE", 13, 13, &umr_bitfield_default },
+	 { "STRAP_REVERSE_LC_LANES", 14, 14, &umr_bitfield_default },
+	 { "STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_LANE_NEGOTIATION", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_STRAP_MISC[] = {
+	 { "STRAP_REVERSE_LANES", 0, 0, &umr_bitfield_default },
+	 { "STRAP_E2E_PREFIX_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_EXTENDED_FMT_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "STRAP_OBFF_SUPPORTED", 3, 4, &umr_bitfield_default },
+	 { "STRAP_LTR_SUPPORTED", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIEP_BCH_ECC_CNTL[] = {
+	 { "STRAP_BCH_ECC_EN", 0, 0, &umr_bitfield_default },
+	 { "BCH_ECC_ERROR_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "BCH_ECC_ERROR_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_SOFTRST_CNTL[] = {
+	 { "REG_RST_rstTimer", 0, 15, &umr_bitfield_default },
+	 { "REG_RST_softRstPropEn", 30, 30, &umr_bitfield_default },
+	 { "SoftRstReg", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_CLIENT_SOFTRST_TRIGGER[] = {
+	 { "CLIENT0_RFE_RFEWRC_rst", 0, 0, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWRC_rst", 1, 1, &umr_bitfield_default },
+	 { "CLIENT2_RFE_RFEWRC_rst", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_MASTER_SOFTRST_TRIGGER[] = {
+	 { "PCIEW0_rst", 0, 0, &umr_bitfield_default },
+	 { "PCIEW1_rst", 1, 1, &umr_bitfield_default },
+	 { "RWREG_RFEWRC_rst", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_PWDN_COMMAND[] = {
+	 { "REG_PCIEW0_pw_cmd", 0, 0, &umr_bitfield_default },
+	 { "REG_PCIEW1_pw_cmd", 1, 1, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWRC_pw_cmd", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_PWDN_STATUS[] = {
+	 { "PCIEW0_REG_pw_status", 0, 0, &umr_bitfield_default },
+	 { "PCIEW1_REG_pw_status", 1, 1, &umr_bitfield_default },
+	 { "RWREG_RFEWRC_REG_pw_status", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_MST_PCIEW0_CMDSTATUS[] = {
+	 { "REG_PCIEW0_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_PCIEW0_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_PCIEW0_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "PCIEW0_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_MST_PCIEW1_CMDSTATUS[] = {
+	 { "REG_PCIEW1_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_PCIEW1_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_PCIEW1_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "PCIEW1_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_MST_RWREG_RFEWRC_CMDSTATUS[] = {
+	 { "REG_RWREG_RFEWRC_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWRC_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWRC_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "RWREG_RFEWRC_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_MST_TMOUT_STATUS[] = {
+	 { "MstTmoutStatus", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_IMPARBH_CONTROL[] = {
+	 { "REG_IMPA_throttleTimer", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_IMPARBH_STATUS[] = {
+	 { "IMPAH_REG_calDone", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_IMPRST_CNTL[] = {
+	 { "REG_RST_impEn", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRFE_WARMRST_CNTL[] = {
+	 { "REG_RST_warmRstRfeEn", 0, 0, &umr_bitfield_default },
+	 { "REG_RST_warmRstImpEn", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMM_INDEX_IND[] = {
+	 { "MM_OFFSET", 0, 30, &umr_bitfield_default },
+	 { "MM_APER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMM_DATA_IND[] = {
+	 { "MM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMM_INDEX_HI_IND[] = {
+	 { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_0_IND[] = {
+	 { "BIOS_SCRATCH_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_1_IND[] = {
+	 { "BIOS_SCRATCH_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_2_IND[] = {
+	 { "BIOS_SCRATCH_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_3_IND[] = {
+	 { "BIOS_SCRATCH_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_4_IND[] = {
+	 { "BIOS_SCRATCH_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_5_IND[] = {
+	 { "BIOS_SCRATCH_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_6_IND[] = {
+	 { "BIOS_SCRATCH_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_7_IND[] = {
+	 { "BIOS_SCRATCH_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_8_IND[] = {
+	 { "BIOS_SCRATCH_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_9_IND[] = {
+	 { "BIOS_SCRATCH_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_10_IND[] = {
+	 { "BIOS_SCRATCH_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_11_IND[] = {
+	 { "BIOS_SCRATCH_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_12_IND[] = {
+	 { "BIOS_SCRATCH_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_13_IND[] = {
+	 { "BIOS_SCRATCH_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_14_IND[] = {
+	 { "BIOS_SCRATCH_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIOS_SCRATCH_15_IND[] = {
+	 { "BIOS_SCRATCH_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_FLUSH_CNTL_IND[] = {
+	 { "CP_RB0_WPTR", 0, 0, &umr_bitfield_default },
+	 { "CP_RB1_WPTR", 1, 1, &umr_bitfield_default },
+	 { "CP_RB2_WPTR", 2, 2, &umr_bitfield_default },
+	 { "UVD_RBC_RB_WPTR", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR", 5, 5, &umr_bitfield_default },
+	 { "CP_DMA_ME_COMMAND", 6, 6, &umr_bitfield_default },
+	 { "CP_DMA_PFP_COMMAND", 7, 7, &umr_bitfield_default },
+	 { "SAM_SAB_RBI_WPTR", 8, 8, &umr_bitfield_default },
+	 { "SAM_SAB_RBO_WPTR", 9, 9, &umr_bitfield_default },
+	 { "VCE_OUT_RB_WPTR", 10, 10, &umr_bitfield_default },
+	 { "VCE_RB_WPTR2", 11, 11, &umr_bitfield_default },
+	 { "VCE_RB_WPTR", 12, 12, &umr_bitfield_default },
+	 { "HOST_DOORBELL", 13, 13, &umr_bitfield_default },
+	 { "SELFRING_DOORBELL", 14, 14, &umr_bitfield_default },
+	 { "CP_DMA_PIO_COMMAND", 15, 15, &umr_bitfield_default },
+	 { "DISPLAY", 16, 16, &umr_bitfield_default },
+	 { "SDMA2_GFX_RB_WPTR", 17, 17, &umr_bitfield_default },
+	 { "SDMA3_GFX_RB_WPTR", 18, 18, &umr_bitfield_default },
+	 { "IGNORE_MC_DISABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_FLUSH_REQ_IND[] = {
+	 { "FLUSH_REQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGPU_GARLIC_FLUSH_REQ_IND[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+	 { "SDMA2", 12, 12, &umr_bitfield_default },
+	 { "SDMA3", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGPU_GARLIC_FLUSH_DONE_IND[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+	 { "SDMA2", 12, 12, &umr_bitfield_default },
+	 { "SDMA3", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_CP_RB0_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_CP_RB1_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_CP_RB2_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_VCE_RB_WPTR2_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_VCE_RB_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixREMAP_HDP_MEM_FLUSH_CNTL_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixREMAP_HDP_REG_FLUSH_CNTL_IND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX0_LOWER_IND[] = {
+	 { "VDDGFX_GFX0_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX0_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX0_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX0_UPPER_IND[] = {
+	 { "VDDGFX_GFX0_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX1_LOWER_IND[] = {
+	 { "VDDGFX_GFX1_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX1_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX1_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX1_UPPER_IND[] = {
+	 { "VDDGFX_GFX1_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX2_LOWER_IND[] = {
+	 { "VDDGFX_GFX2_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX2_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX2_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX2_UPPER_IND[] = {
+	 { "VDDGFX_GFX2_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX3_LOWER_IND[] = {
+	 { "VDDGFX_GFX3_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX3_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX3_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX3_UPPER_IND[] = {
+	 { "VDDGFX_GFX3_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX4_LOWER_IND[] = {
+	 { "VDDGFX_GFX4_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX4_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX4_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX4_UPPER_IND[] = {
+	 { "VDDGFX_GFX4_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX5_LOWER_IND[] = {
+	 { "VDDGFX_GFX5_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX5_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX5_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_GFX5_UPPER_IND[] = {
+	 { "VDDGFX_GFX5_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_RSV1_LOWER_IND[] = {
+	 { "VDDGFX_RSV1_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV1_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV1_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_RSV1_UPPER_IND[] = {
+	 { "VDDGFX_RSV1_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_RSV2_LOWER_IND[] = {
+	 { "VDDGFX_RSV2_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV2_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV2_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_RSV2_UPPER_IND[] = {
+	 { "VDDGFX_RSV2_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_RSV3_LOWER_IND[] = {
+	 { "VDDGFX_RSV3_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV3_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV3_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_RSV3_UPPER_IND[] = {
+	 { "VDDGFX_RSV3_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_RSV4_LOWER_IND[] = {
+	 { "VDDGFX_RSV4_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV4_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV4_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_RSV4_UPPER_IND[] = {
+	 { "VDDGFX_RSV4_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_VDDGFX_FB_CMP_IND[] = {
+	 { "VDDGFX_FB_HDP_CMP_EN", 0, 0, &umr_bitfield_default },
+	 { "VDDGFX_FB_HDP_STALL_EN", 1, 1, &umr_bitfield_default },
+	 { "VDDGFX_FB_XDMA_CMP_EN", 2, 2, &umr_bitfield_default },
+	 { "VDDGFX_FB_XDMA_STALL_EN", 3, 3, &umr_bitfield_default },
+	 { "VDDGFX_FB_VGA_CMP_EN", 4, 4, &umr_bitfield_default },
+	 { "VDDGFX_FB_VGA_STALL_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_SMU_INDEX_IND[] = {
+	 { "BIF_SMU_INDEX", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_SMU_DATA_IND[] = {
+	 { "BIF_SMU_DATA", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_XDMA_LO_IND[] = {
+	 { "BIF_XDMA_LOWER_BOUND", 0, 28, &umr_bitfield_default },
+	 { "BIF_XDMA_APER_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_XDMA_HI_IND[] = {
+	 { "BIF_XDMA_UPPER_BOUND", 0, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_FEATURES_CONTROL_MISC_IND[] = {
+	 { "MST_BIF_REQ_EP_DIS", 0, 0, &umr_bitfield_default },
+	 { "SLV_BIF_CPL_EP_DIS", 1, 1, &umr_bitfield_default },
+	 { "BIF_SLV_REQ_EP_DIS", 2, 2, &umr_bitfield_default },
+	 { "BIF_MST_CPL_EP_DIS", 3, 3, &umr_bitfield_default },
+	 { "UR_PSN_PKT_REPORT_POISON_DIS", 4, 4, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS", 5, 5, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS", 6, 6, &umr_bitfield_default },
+	 { "PLL_SWITCH_IMPCTL_CAL_DONE_DIS", 7, 7, &umr_bitfield_default },
+	 { "IGNORE_BE_CHECK_GASKET_COMB_DIS", 8, 8, &umr_bitfield_default },
+	 { "MC_BIF_REQ_ID_ROUTING_DIS", 9, 9, &umr_bitfield_default },
+	 { "AZ_BIF_REQ_ID_ROUTING_DIS", 10, 10, &umr_bitfield_default },
+	 { "ATC_PRG_RESP_PASID_UR_EN", 11, 11, &umr_bitfield_default },
+	 { "BIF_RB_SET_OVERFLOW_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DOORBELL_CNTL_IND[] = {
+	 { "SELF_RING_DIS", 0, 0, &umr_bitfield_default },
+	 { "TRANS_CHECK_DIS", 1, 1, &umr_bitfield_default },
+	 { "UNTRANS_LBACK_EN", 2, 2, &umr_bitfield_default },
+	 { "NON_CONSECUTIVE_BE_ZERO_DIS", 3, 3, &umr_bitfield_default },
+	 { "DOORBELL_MONITOR_EN", 4, 4, &umr_bitfield_default },
+	 { "DOORBELL_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default },
+	 { "DOORBELL_INTERRUPT_CLEAR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_SLVARB_MODE_IND[] = {
+	 { "SLVARB_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMBUS_BACO_DUMMY_IND[] = {
+	 { "SMBUS_BACO_DUMMY_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBF_ANA_ISO_CNTL_IND[] = {
+	 { "BF_ANA_ISO_DIS_MASK", 0, 0, &umr_bitfield_default },
+	 { "BF_VDDC_ISO_DIS_MASK", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBACO_CNTL_MISC_IND[] = {
+	 { "BIF_ROM_REQ_DIS", 0, 0, &umr_bitfield_default },
+	 { "BIF_AZ_REQ_DIS", 1, 1, &umr_bitfield_default },
+	 { "BACO_LINK_RST_WIDTH_SEL", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_BACO_DEBUG_LATCH_IND[] = {
+	 { "BIF_BACO_LATCH_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_BACO_DEBUG_IND[] = {
+	 { "BIF_BACO_SCANDUMP_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMEM_TYPE_CNTL_IND[] = {
+	 { "BF_MEM_PHY_G5_G3", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBACO_CNTL_IND[] = {
+	 { "BACO_EN", 0, 0, &umr_bitfield_default },
+	 { "BACO_BCLK_OFF", 1, 1, &umr_bitfield_default },
+	 { "BACO_ISO_DIS", 2, 2, &umr_bitfield_default },
+	 { "BACO_POWER_OFF", 3, 3, &umr_bitfield_default },
+	 { "BACO_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "BACO_HANG_PROTECTION_EN", 5, 5, &umr_bitfield_default },
+	 { "BACO_MODE", 6, 6, &umr_bitfield_default },
+	 { "BACO_ANA_ISO_DIS", 7, 7, &umr_bitfield_default },
+	 { "RCU_BIF_CONFIG_DONE", 8, 8, &umr_bitfield_default },
+	 { "PWRGOOD_BF", 9, 9, &umr_bitfield_default },
+	 { "PWRGOOD_GPIO", 10, 10, &umr_bitfield_default },
+	 { "PWRGOOD_MEM", 11, 11, &umr_bitfield_default },
+	 { "PWRGOOD_DVO", 12, 12, &umr_bitfield_default },
+	 { "PWRGOOD_IDSC", 13, 13, &umr_bitfield_default },
+	 { "BACO_POWER_OFF_DRAM", 16, 16, &umr_bitfield_default },
+	 { "BACO_BF_MEM_PHY_ISO_CNTRL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DEVFUNCNUM_LIST1_IND[] = {
+	 { "DEVFUNC_ID4", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID5", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID6", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DEVFUNCNUM_LIST0_IND[] = {
+	 { "DEVFUNC_ID0", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID1", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID2", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDBG_BYPASS_SRBM_ACCESS_IND[] = {
+	 { "DBG_BYPASS_SRBM_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "DBG_APER_AD", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER3_FB_OFFSET_LO_IND[] = {
+	 { "PEER3_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER3_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER3_FB_OFFSET_HI_IND[] = {
+	 { "PEER3_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER2_FB_OFFSET_LO_IND[] = {
+	 { "PEER2_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER2_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER2_FB_OFFSET_HI_IND[] = {
+	 { "PEER2_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER1_FB_OFFSET_LO_IND[] = {
+	 { "PEER1_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER1_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER1_FB_OFFSET_HI_IND[] = {
+	 { "PEER1_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER0_FB_OFFSET_LO_IND[] = {
+	 { "PEER0_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER0_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER0_FB_OFFSET_HI_IND[] = {
+	 { "PEER0_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIMPCTL_RESET_IND[] = {
+	 { "IMP_SW_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_BIF_VDDGFX_PWR_STATUS_IND[] = {
+	 { "VDDGFX_GFX_PWR_OFF", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DOORBELL_GBLAPER1_LOWER_IND[] = {
+	 { "DOORBELL_GBLAPER1_LOWER", 2, 11, &umr_bitfield_default },
+	 { "DOORBELL_GBLAPER1_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DOORBELL_GBLAPER1_UPPER_IND[] = {
+	 { "DOORBELL_GBLAPER1_UPPER", 2, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DOORBELL_GBLAPER2_LOWER_IND[] = {
+	 { "DOORBELL_GBLAPER2_LOWER", 2, 11, &umr_bitfield_default },
+	 { "DOORBELL_GBLAPER2_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DOORBELL_GBLAPER2_UPPER_IND[] = {
+	 { "DOORBELL_GBLAPER2_UPPER", 2, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_MM_INDACCESS_CNTL_IND[] = {
+	 { "MM_INDACCESS_DIS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBUS_CNTL_IND[] = {
+	 { "BIOS_ROM_WRT_EN", 0, 0, &umr_bitfield_default },
+	 { "BIOS_ROM_DIS", 1, 1, &umr_bitfield_default },
+	 { "PMI_IO_DIS", 2, 2, &umr_bitfield_default },
+	 { "PMI_MEM_DIS", 3, 3, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 4, 4, &umr_bitfield_default },
+	 { "PMI_INT_DIS", 5, 5, &umr_bitfield_default },
+	 { "VGA_REG_COHERENCY_DIS", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_COHERENCY_DIS", 7, 7, &umr_bitfield_default },
+	 { "BIF_ERR_RTR_BKPRESSURE_EN", 8, 8, &umr_bitfield_default },
+	 { "SET_AZ_TC", 10, 12, &umr_bitfield_default },
+	 { "SET_MC_TC", 13, 15, &umr_bitfield_default },
+	 { "ZERO_BE_WR_EN", 16, 16, &umr_bitfield_default },
+	 { "ZERO_BE_RD_EN", 17, 17, &umr_bitfield_default },
+	 { "RD_STALL_IO_WR", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCONFIG_CNTL_IND[] = {
+	 { "CFG_VGA_RAM_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_DIS", 1, 1, &umr_bitfield_default },
+	 { "GENMO_MONO_ADDRESS_B", 2, 2, &umr_bitfield_default },
+	 { "GRPH_ADRSEL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCONFIG_MEMSIZE_IND[] = {
+	 { "CONFIG_MEMSIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCONFIG_F0_BASE_IND[] = {
+	 { "F0_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCONFIG_APER_SIZE_IND[] = {
+	 { "APER_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCONFIG_REG_APER_SIZE_IND[] = {
+	 { "REG_APER_SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_SCRATCH0_IND[] = {
+	 { "BIF_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_SCRATCH1_IND[] = {
+	 { "BIF_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMM_CFGREGS_CNTL_IND[] = {
+	 { "MM_CFG_FUNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "MM_WR_TO_CFG_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBX_RESET_EN_IND[] = {
+	 { "COR_RESET_EN", 0, 0, &umr_bitfield_default },
+	 { "REG_RESET_EN", 1, 1, &umr_bitfield_default },
+	 { "STY_RESET_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHW_DEBUG_IND[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMASTER_CREDIT_CNTL_IND[] = {
+	 { "BIF_MC_RDRET_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "BIF_AZ_RDRET_CREDIT", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSLAVE_REQ_CREDIT_CNTL_IND[] = {
+	 { "BIF_SRBM_REQ_CREDIT", 0, 4, &umr_bitfield_default },
+	 { "BIF_VGA_REQ_CREDIT", 5, 8, &umr_bitfield_default },
+	 { "BIF_HDP_REQ_CREDIT", 10, 14, &umr_bitfield_default },
+	 { "BIF_ROM_REQ_CREDIT", 15, 15, &umr_bitfield_default },
+	 { "BIF_AZ_REQ_CREDIT", 20, 20, &umr_bitfield_default },
+	 { "BIF_XDMA_REQ_CREDIT", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBX_RESET_CNTL_IND[] = {
+	 { "LINK_TRAIN_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixINTERRUPT_CNTL_IND[] = {
+	 { "IH_DUMMY_RD_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "IH_DUMMY_RD_EN", 1, 1, &umr_bitfield_default },
+	 { "IH_REQ_NONSNOOP_EN", 3, 3, &umr_bitfield_default },
+	 { "IH_INTR_DLY_CNTR", 4, 7, &umr_bitfield_default },
+	 { "GEN_IH_INT_EN", 8, 8, &umr_bitfield_default },
+	 { "GEN_GPIO_INT_EN", 9, 12, &umr_bitfield_default },
+	 { "SELECT_INT_GPIO_OUTPUT", 13, 14, &umr_bitfield_default },
+	 { "BIF_RB_REQ_NONSNOOP_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixINTERRUPT_CNTL2_IND[] = {
+	 { "IH_DUMMY_RD_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DEBUG_CNTL_IND[] = {
+	 { "DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_MULTIBLOCKEN", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "DEBUG_PAD_SEL", 3, 3, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK1", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK2", 5, 5, &umr_bitfield_default },
+	 { "DEBUG_SYNC_EN", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_SWAP", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK1", 8, 12, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK2", 16, 20, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_XSP", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_SYNC_CLKSEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DEBUG_MUX_IND[] = {
+	 { "DEBUG_MUX_BLK1", 0, 5, &umr_bitfield_default },
+	 { "DEBUG_MUX_BLK2", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_DEBUG_OUT_IND[] = {
+	 { "DEBUG_OUTPUT", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND[] = {
+	 { "HDP_MEM_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLKREQB_PAD_CNTL_IND[] = {
+	 { "CLKREQB_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "CLKREQB_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "CLKREQB_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "CLKREQB_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMBDAT_PAD_CNTL_IND[] = {
+	 { "SMBDAT_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "SMBDAT_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "SMBDAT_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "SMBDAT_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMBCLK_PAD_CNTL_IND[] = {
+	 { "SMBCLK_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "SMBCLK_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "SMBCLK_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "SMBCLK_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_FB_EN_IND[] = {
+	 { "FB_READ_EN", 0, 0, &umr_bitfield_default },
+	 { "FB_WRITE_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_BUSNUM_CNTL1_IND[] = {
+	 { "ID_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_BUSNUM_LIST0_IND[] = {
+	 { "ID0", 0, 7, &umr_bitfield_default },
+	 { "ID1", 8, 15, &umr_bitfield_default },
+	 { "ID2", 16, 23, &umr_bitfield_default },
+	 { "ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_BUSNUM_LIST1_IND[] = {
+	 { "ID4", 0, 7, &umr_bitfield_default },
+	 { "ID5", 8, 15, &umr_bitfield_default },
+	 { "ID6", 16, 23, &umr_bitfield_default },
+	 { "ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHDP_REG_COHERENCY_FLUSH_CNTL_IND[] = {
+	 { "HDP_REG_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_BUSY_DELAY_CNTR_IND[] = {
+	 { "DELAY_CNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_BUSNUM_CNTL2_IND[] = {
+	 { "AUTOUPDATE_SEL", 0, 7, &umr_bitfield_default },
+	 { "AUTOUPDATE_EN", 8, 8, &umr_bitfield_default },
+	 { "HDPREG_CNTL", 16, 16, &umr_bitfield_default },
+	 { "ERROR_MULTIPLE_ID_MATCH", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_PERFMON_CNTL_IND[] = {
+	 { "PERFCOUNTER_EN", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET0", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET1", 2, 2, &umr_bitfield_default },
+	 { "PERF_SEL0", 8, 12, &umr_bitfield_default },
+	 { "PERF_SEL1", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_PERFCOUNTER0_RESULT_IND[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_PERFCOUNTER1_RESULT_IND[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RB_CNTL_IND[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_TIMER", 9, 13, &umr_bitfield_default },
+	 { "BIF_RB_TRAN", 17, 17, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RB_BASE_IND[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RB_RPTR_IND[] = {
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RB_WPTR_IND[] = {
+	 { "BIF_RB_OVERFLOW", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RB_WPTR_ADDR_HI_IND[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RB_WPTR_ADDR_LO_IND[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSLAVE_HANG_PROTECTION_CNTL_IND[] = {
+	 { "HANG_PROTECTION_TIMER_SEL", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGPU_HDP_FLUSH_REQ_IND[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGPU_HDP_FLUSH_DONE_IND[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSLAVE_HANG_ERROR_IND[] = {
+	 { "SRBM_HANG_ERROR", 0, 0, &umr_bitfield_default },
+	 { "HDP_HANG_ERROR", 1, 1, &umr_bitfield_default },
+	 { "VGA_HANG_ERROR", 2, 2, &umr_bitfield_default },
+	 { "ROM_HANG_ERROR", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_HANG_ERROR", 4, 4, &umr_bitfield_default },
+	 { "CEC_HANG_ERROR", 5, 5, &umr_bitfield_default },
+	 { "XDMA_HANG_ERROR", 7, 7, &umr_bitfield_default },
+	 { "DOORBELL_HANG_ERROR", 8, 8, &umr_bitfield_default },
+	 { "GARLIC_HANG_ERROR", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCAPTURE_HOST_BUSNUM_IND[] = {
+	 { "CHECK_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHOST_BUSNUM_IND[] = {
+	 { "HOST_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER_REG_RANGE0_IND[] = {
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPEER_REG_RANGE1_IND[] = {
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_SCRATCH[] = {
+	 { "PIF_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_STRAP_0[] = {
+	 { "STRAP_TX_RDY_XTND_DIS", 1, 1, &umr_bitfield_default },
+	 { "STRAP_RX_RDY_XTND_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_TX_STATUS_XTND_DIS", 3, 3, &umr_bitfield_default },
+	 { "STRAP_RX_STATUS_XTND_DIS", 4, 4, &umr_bitfield_default },
+	 { "STRAP_FORCE_OWN_MSTR", 5, 5, &umr_bitfield_default },
+	 { "STRAP_PIF_CDR_EN_MODE", 6, 7, &umr_bitfield_default },
+	 { "STRAP_RX_EI_FILTER", 8, 9, &umr_bitfield_default },
+	 { "STRAP_RX_DIS_HLD_EIE_IN_PS1", 10, 10, &umr_bitfield_default },
+	 { "STRAP_RX_DIS_HLD_EIE_IN_PS2", 11, 11, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_12", 12, 12, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_13", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_14", 14, 14, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_15", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_16", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_CTRL[] = {
+	 { "PIF_PLL_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "DTM_FORCE_FREQDIV_X1", 1, 1, &umr_bitfield_default },
+	 { "PIF_PLL_HNDSHK_EARLY_ABORT", 2, 2, &umr_bitfield_default },
+	 { "PIF_PLL_PWRDN_EARLY_EXIT", 3, 3, &umr_bitfield_default },
+	 { "PHY_RST_PWROK_VDD", 4, 4, &umr_bitfield_default },
+	 { "PIF_PLL_STATUS", 6, 7, &umr_bitfield_default },
+	 { "PIF_PLL_DEGRADE_OFF_VOTE", 8, 8, &umr_bitfield_default },
+	 { "PIF_PLL_UNUSED_OFF_VOTE", 9, 9, &umr_bitfield_default },
+	 { "PIF_PLL_DEGRADE_S2_VOTE", 10, 10, &umr_bitfield_default },
+	 { "PIF_PG_EXIT_MODE", 11, 11, &umr_bitfield_default },
+	 { "PIF_DEGRADE_PWR_PLL_MODE", 12, 12, &umr_bitfield_default },
+	 { "PIF_LANEUNUSED_AFFECT_GANG", 13, 13, &umr_bitfield_default },
+	 { "PIF_PG_ABORT_DISABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_TX_CTRL[] = {
+	 { "TXPWR_IN_S2", 0, 2, &umr_bitfield_default },
+	 { "TXPWR_IN_SPDCHNG", 3, 5, &umr_bitfield_default },
+	 { "TXPWR_IN_OFF", 6, 8, &umr_bitfield_default },
+	 { "TXPWR_IN_DEGRADE", 9, 11, &umr_bitfield_default },
+	 { "TXPWR_IN_UNUSED", 12, 14, &umr_bitfield_default },
+	 { "TXPWR_IN_INIT", 15, 17, &umr_bitfield_default },
+	 { "TXPWR_IN_PLL_OFF", 18, 20, &umr_bitfield_default },
+	 { "TXPWR_IN_DEGRADE_MODE", 21, 21, &umr_bitfield_default },
+	 { "TXPWR_IN_UNUSED_MODE", 22, 22, &umr_bitfield_default },
+	 { "TXPWR_GATING_IN_L1", 23, 23, &umr_bitfield_default },
+	 { "TXPWR_GATING_IN_UNUSED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_TX_CTRL2[] = {
+	 { "TX_RDY_DASRT_COUNT", 0, 2, &umr_bitfield_default },
+	 { "TX_STATUS_DASRT_COUNT", 3, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_DELAY", 6, 8, &umr_bitfield_default },
+	 { "TX_L1_PG_PHY_STATUS_MODE", 9, 9, &umr_bitfield_default },
+	 { "TX_OFF_PG_PHY_STATUS_MODE", 10, 10, &umr_bitfield_default },
+	 { "TX_HIGH_IMP_STAG_MP", 16, 16, &umr_bitfield_default },
+	 { "TX_HIGH_IMP_STAG_MODE", 17, 18, &umr_bitfield_default },
+	 { "TX_FORCE_DATA_VALID", 21, 21, &umr_bitfield_default },
+	 { "TX_L0_TO_HIZ_DLY", 22, 24, &umr_bitfield_default },
+	 { "TX_FIFO_INIT_UPCONFIG", 25, 25, &umr_bitfield_default },
+	 { "TX_HIZ_TO_L0_DLY", 26, 28, &umr_bitfield_default },
+	 { "TX_LINKSPEED_ACK_IN_S2", 29, 29, &umr_bitfield_default },
+	 { "TX_DELAY_FIFO_INIT_IN_S1", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_RX_CTRL[] = {
+	 { "RXPWR_IN_S2", 0, 2, &umr_bitfield_default },
+	 { "RXPWR_IN_SPDCHNG", 3, 5, &umr_bitfield_default },
+	 { "RXPWR_IN_OFF", 6, 8, &umr_bitfield_default },
+	 { "RXPWR_IN_DEGRADE", 9, 11, &umr_bitfield_default },
+	 { "RXPWR_IN_UNUSED", 12, 14, &umr_bitfield_default },
+	 { "RXPWR_IN_INIT", 15, 17, &umr_bitfield_default },
+	 { "RXPWR_IN_PLL_OFF", 18, 20, &umr_bitfield_default },
+	 { "RXPWR_IN_DEGRADE_MODE", 21, 21, &umr_bitfield_default },
+	 { "RXPWR_IN_UNUSED_MODE", 22, 22, &umr_bitfield_default },
+	 { "RXPWR_GATING_IN_L1", 23, 23, &umr_bitfield_default },
+	 { "RXPWR_GATING_IN_UNUSED", 24, 24, &umr_bitfield_default },
+	 { "RX_HLD_EIE_COUNT", 25, 25, &umr_bitfield_default },
+	 { "RX_EI_DET_IN_PS2_DEGRADE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_RX_CTRL2[] = {
+	 { "RX_RDY_DASRT_COUNT", 0, 2, &umr_bitfield_default },
+	 { "RX_STATUS_DASRT_COUNT", 3, 5, &umr_bitfield_default },
+	 { "RXPHYSTATUS_DELAY", 6, 8, &umr_bitfield_default },
+	 { "RX_L1_PG_PHY_STATUS_MODE", 9, 9, &umr_bitfield_default },
+	 { "RX_OFF_PG_PHY_STATUS_MODE", 10, 10, &umr_bitfield_default },
+	 { "FORCE_CDREN_IN_L0S", 16, 16, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_MODE", 17, 18, &umr_bitfield_default },
+	 { "EI_DET_ON_TIME", 19, 20, &umr_bitfield_default },
+	 { "EI_DET_OFF_TIME", 21, 23, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_DIS_IN_PS1", 24, 24, &umr_bitfield_default },
+	 { "RX_CDR_XTND_MODE", 25, 26, &umr_bitfield_default },
+	 { "RX_L0S_TO_L0_DETECT_EI", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_GLB_OVRD[] = {
+	 { "RXDETECT_OVERRIDE_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_1", 1, 1, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_3", 3, 3, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_5", 5, 5, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_6", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_7", 7, 7, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_GLB_OVRD2[] = {
+	 { "X2_LANE_1_0_OVRD", 0, 0, &umr_bitfield_default },
+	 { "X2_LANE_3_2_OVRD", 1, 1, &umr_bitfield_default },
+	 { "X2_LANE_5_4_OVRD", 2, 2, &umr_bitfield_default },
+	 { "X2_LANE_7_6_OVRD", 3, 3, &umr_bitfield_default },
+	 { "X2_LANE_9_8_OVRD", 4, 4, &umr_bitfield_default },
+	 { "X2_LANE_11_10_OVRD", 5, 5, &umr_bitfield_default },
+	 { "X2_LANE_13_12_OVRD", 6, 6, &umr_bitfield_default },
+	 { "X2_LANE_15_14_OVRD", 7, 7, &umr_bitfield_default },
+	 { "X4_LANE_3_0_OVRD", 8, 8, &umr_bitfield_default },
+	 { "X4_LANE_7_4_OVRD", 9, 9, &umr_bitfield_default },
+	 { "X4_LANE_11_8_OVRD", 10, 10, &umr_bitfield_default },
+	 { "X4_LANE_15_12_OVRD", 11, 11, &umr_bitfield_default },
+	 { "X8_LANE_7_0_OVRD", 16, 16, &umr_bitfield_default },
+	 { "X8_LANE_15_8_OVRD", 17, 17, &umr_bitfield_default },
+	 { "X16_LANE_15_0_OVRD", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_BIF_CMD_STATUS[] = {
+	 { "TXPHYSTATUS_0", 0, 0, &umr_bitfield_default },
+	 { "TXPHYSTATUS_1", 1, 1, &umr_bitfield_default },
+	 { "TXPHYSTATUS_2", 2, 2, &umr_bitfield_default },
+	 { "TXPHYSTATUS_3", 3, 3, &umr_bitfield_default },
+	 { "TXPHYSTATUS_4", 4, 4, &umr_bitfield_default },
+	 { "TXPHYSTATUS_5", 5, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_6", 6, 6, &umr_bitfield_default },
+	 { "TXPHYSTATUS_7", 7, 7, &umr_bitfield_default },
+	 { "RXPHYSTATUS_0", 8, 8, &umr_bitfield_default },
+	 { "RXPHYSTATUS_1", 9, 9, &umr_bitfield_default },
+	 { "RXPHYSTATUS_2", 10, 10, &umr_bitfield_default },
+	 { "RXPHYSTATUS_3", 11, 11, &umr_bitfield_default },
+	 { "RXPHYSTATUS_4", 12, 12, &umr_bitfield_default },
+	 { "RXPHYSTATUS_5", 13, 13, &umr_bitfield_default },
+	 { "RXPHYSTATUS_6", 14, 14, &umr_bitfield_default },
+	 { "RXPHYSTATUS_7", 15, 15, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_0", 16, 16, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_1", 17, 17, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_2", 18, 18, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_3", 19, 19, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_4", 20, 20, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_5", 21, 21, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_6", 22, 22, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_7", 23, 23, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_0", 24, 24, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_1", 25, 25, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_2", 26, 26, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_3", 27, 27, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_4", 28, 28, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_5", 29, 29, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_6", 30, 30, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_CMD_BUS_CTRL[] = {
+	 { "CMD_BUS_SCHL_MODE", 0, 1, &umr_bitfield_default },
+	 { "CMD_BUS_STAG_MODE", 2, 3, &umr_bitfield_default },
+	 { "CMD_BUS_STAG_DIS", 4, 4, &umr_bitfield_default },
+	 { "CMD_BUS_SCH_REQ_MODE", 5, 6, &umr_bitfield_default },
+	 { "CMD_BUS_IGNR_PEND_PWR", 7, 7, &umr_bitfield_default },
+	 { "SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES", 8, 8, &umr_bitfield_default },
+	 { "CMD_BUS_IGNR_PWR_NOT_ON", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_CMD_BUS_GLB_OVRD[] = {
+	 { "TXMARG_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "DEEMPH_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "PLLFREQ_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TXMARG", 3, 5, &umr_bitfield_default },
+	 { "DEEMPH", 6, 6, &umr_bitfield_default },
+	 { "PLLFREQ", 7, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_PIF_OVRD", 9, 9, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_0", 16, 16, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_1", 17, 17, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_2", 18, 18, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_3", 19, 19, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_4", 20, 20, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_5", 21, 21, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_6", 22, 22, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_7", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE0_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_0", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_0", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_0", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_0", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_0", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_0", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_0", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_0", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE0_OVRD2[] = {
+	 { "GANGMODE_0", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_0", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_0", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_0", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_0", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_0", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_0", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_0", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_0", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_0", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_0", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_0", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE1_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_1", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_1", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_1", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_1", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_1", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_1", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_1", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_1", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_1", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_1", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_1", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_1", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE1_OVRD2[] = {
+	 { "GANGMODE_1", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_1", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_1", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_1", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_1", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_1", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_1", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_1", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_1", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_1", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_1", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE2_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_2", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_2", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_2", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_2", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_2", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_2", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_2", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_2", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_2", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_2", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_2", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_2", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_2", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE2_OVRD2[] = {
+	 { "GANGMODE_2", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_2", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_2", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_2", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_2", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_2", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_2", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_2", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_2", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_2", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_2", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_2", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE3_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_3", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_3", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_3", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_3", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_3", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_3", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_3", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_3", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_3", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_3", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_3", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_3", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_3", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE3_OVRD2[] = {
+	 { "GANGMODE_3", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_3", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_3", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_3", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_3", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_3", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_3", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_3", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_3", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_3", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_3", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_3", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE4_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_4", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_4", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_4", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_4", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_4", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_4", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_4", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_4", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_4", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_4", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_4", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_4", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE4_OVRD2[] = {
+	 { "GANGMODE_4", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_4", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_4", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_4", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_4", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_4", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_4", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_4", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_4", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_4", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_4", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_4", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE5_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_5", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_5", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_5", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_5", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_5", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_5", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_5", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_5", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_5", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_5", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_5", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_5", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_5", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE5_OVRD2[] = {
+	 { "GANGMODE_5", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_5", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_5", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_5", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_5", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_5", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_5", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_5", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_5", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_5", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_5", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_5", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE6_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_6", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_6", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_6", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_6", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_6", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_6", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_6", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_6", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_6", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_6", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_6", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_6", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_6", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE6_OVRD2[] = {
+	 { "GANGMODE_6", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_6", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_6", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_6", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_6", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_6", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_6", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_6", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_6", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_6", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_6", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_6", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE7_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_7", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_7", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_7", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_7", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_7", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_7", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_7", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_7", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_7", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_7", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_7", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_7", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_7", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PIF0_LANE7_OVRD2[] = {
+	 { "GANGMODE_7", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_7", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_7", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_7", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_7", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_7", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_7", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_7", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_7", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_7", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_7", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_7", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_SCRATCH[] = {
+	 { "PIF_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_STRAP_0[] = {
+	 { "STRAP_TX_RDY_XTND_DIS", 1, 1, &umr_bitfield_default },
+	 { "STRAP_RX_RDY_XTND_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_TX_STATUS_XTND_DIS", 3, 3, &umr_bitfield_default },
+	 { "STRAP_RX_STATUS_XTND_DIS", 4, 4, &umr_bitfield_default },
+	 { "STRAP_FORCE_OWN_MSTR", 5, 5, &umr_bitfield_default },
+	 { "STRAP_PIF_CDR_EN_MODE", 6, 7, &umr_bitfield_default },
+	 { "STRAP_RX_EI_FILTER", 8, 9, &umr_bitfield_default },
+	 { "STRAP_RX_DIS_HLD_EIE_IN_PS1", 10, 10, &umr_bitfield_default },
+	 { "STRAP_RX_DIS_HLD_EIE_IN_PS2", 11, 11, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_12", 12, 12, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_13", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_14", 14, 14, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_15", 15, 15, &umr_bitfield_default },
+	 { "STRAP_PIF_BIT_16", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_CTRL[] = {
+	 { "PIF_PLL_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "DTM_FORCE_FREQDIV_X1", 1, 1, &umr_bitfield_default },
+	 { "PIF_PLL_HNDSHK_EARLY_ABORT", 2, 2, &umr_bitfield_default },
+	 { "PIF_PLL_PWRDN_EARLY_EXIT", 3, 3, &umr_bitfield_default },
+	 { "PHY_RST_PWROK_VDD", 4, 4, &umr_bitfield_default },
+	 { "PIF_PLL_STATUS", 6, 7, &umr_bitfield_default },
+	 { "PIF_PLL_DEGRADE_OFF_VOTE", 8, 8, &umr_bitfield_default },
+	 { "PIF_PLL_UNUSED_OFF_VOTE", 9, 9, &umr_bitfield_default },
+	 { "PIF_PLL_DEGRADE_S2_VOTE", 10, 10, &umr_bitfield_default },
+	 { "PIF_PG_EXIT_MODE", 11, 11, &umr_bitfield_default },
+	 { "PIF_DEGRADE_PWR_PLL_MODE", 12, 12, &umr_bitfield_default },
+	 { "PIF_LANEUNUSED_AFFECT_GANG", 13, 13, &umr_bitfield_default },
+	 { "PIF_PG_ABORT_DISABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_TX_CTRL[] = {
+	 { "TXPWR_IN_S2", 0, 2, &umr_bitfield_default },
+	 { "TXPWR_IN_SPDCHNG", 3, 5, &umr_bitfield_default },
+	 { "TXPWR_IN_OFF", 6, 8, &umr_bitfield_default },
+	 { "TXPWR_IN_DEGRADE", 9, 11, &umr_bitfield_default },
+	 { "TXPWR_IN_UNUSED", 12, 14, &umr_bitfield_default },
+	 { "TXPWR_IN_INIT", 15, 17, &umr_bitfield_default },
+	 { "TXPWR_IN_PLL_OFF", 18, 20, &umr_bitfield_default },
+	 { "TXPWR_IN_DEGRADE_MODE", 21, 21, &umr_bitfield_default },
+	 { "TXPWR_IN_UNUSED_MODE", 22, 22, &umr_bitfield_default },
+	 { "TXPWR_GATING_IN_L1", 23, 23, &umr_bitfield_default },
+	 { "TXPWR_GATING_IN_UNUSED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_TX_CTRL2[] = {
+	 { "TX_RDY_DASRT_COUNT", 0, 2, &umr_bitfield_default },
+	 { "TX_STATUS_DASRT_COUNT", 3, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_DELAY", 6, 8, &umr_bitfield_default },
+	 { "TX_L1_PG_PHY_STATUS_MODE", 9, 9, &umr_bitfield_default },
+	 { "TX_OFF_PG_PHY_STATUS_MODE", 10, 10, &umr_bitfield_default },
+	 { "TX_HIGH_IMP_STAG_MP", 16, 16, &umr_bitfield_default },
+	 { "TX_HIGH_IMP_STAG_MODE", 17, 18, &umr_bitfield_default },
+	 { "TX_FORCE_DATA_VALID", 21, 21, &umr_bitfield_default },
+	 { "TX_L0_TO_HIZ_DLY", 22, 24, &umr_bitfield_default },
+	 { "TX_FIFO_INIT_UPCONFIG", 25, 25, &umr_bitfield_default },
+	 { "TX_HIZ_TO_L0_DLY", 26, 28, &umr_bitfield_default },
+	 { "TX_LINKSPEED_ACK_IN_S2", 29, 29, &umr_bitfield_default },
+	 { "TX_DELAY_FIFO_INIT_IN_S1", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_RX_CTRL[] = {
+	 { "RXPWR_IN_S2", 0, 2, &umr_bitfield_default },
+	 { "RXPWR_IN_SPDCHNG", 3, 5, &umr_bitfield_default },
+	 { "RXPWR_IN_OFF", 6, 8, &umr_bitfield_default },
+	 { "RXPWR_IN_DEGRADE", 9, 11, &umr_bitfield_default },
+	 { "RXPWR_IN_UNUSED", 12, 14, &umr_bitfield_default },
+	 { "RXPWR_IN_INIT", 15, 17, &umr_bitfield_default },
+	 { "RXPWR_IN_PLL_OFF", 18, 20, &umr_bitfield_default },
+	 { "RXPWR_IN_DEGRADE_MODE", 21, 21, &umr_bitfield_default },
+	 { "RXPWR_IN_UNUSED_MODE", 22, 22, &umr_bitfield_default },
+	 { "RXPWR_GATING_IN_L1", 23, 23, &umr_bitfield_default },
+	 { "RXPWR_GATING_IN_UNUSED", 24, 24, &umr_bitfield_default },
+	 { "RX_HLD_EIE_COUNT", 25, 25, &umr_bitfield_default },
+	 { "RX_EI_DET_IN_PS2_DEGRADE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_RX_CTRL2[] = {
+	 { "RX_RDY_DASRT_COUNT", 0, 2, &umr_bitfield_default },
+	 { "RX_STATUS_DASRT_COUNT", 3, 5, &umr_bitfield_default },
+	 { "RXPHYSTATUS_DELAY", 6, 8, &umr_bitfield_default },
+	 { "RX_L1_PG_PHY_STATUS_MODE", 9, 9, &umr_bitfield_default },
+	 { "RX_OFF_PG_PHY_STATUS_MODE", 10, 10, &umr_bitfield_default },
+	 { "FORCE_CDREN_IN_L0S", 16, 16, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_MODE", 17, 18, &umr_bitfield_default },
+	 { "EI_DET_ON_TIME", 19, 20, &umr_bitfield_default },
+	 { "EI_DET_OFF_TIME", 21, 23, &umr_bitfield_default },
+	 { "EI_DET_CYCLE_DIS_IN_PS1", 24, 24, &umr_bitfield_default },
+	 { "RX_CDR_XTND_MODE", 25, 26, &umr_bitfield_default },
+	 { "RX_L0S_TO_L0_DETECT_EI", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_GLB_OVRD[] = {
+	 { "RXDETECT_OVERRIDE_VAL_0", 0, 0, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_1", 1, 1, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_2", 2, 2, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_3", 3, 3, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_4", 4, 4, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_5", 5, 5, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_6", 6, 6, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_VAL_7", 7, 7, &umr_bitfield_default },
+	 { "RXDETECT_OVERRIDE_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_GLB_OVRD2[] = {
+	 { "X2_LANE_1_0_OVRD", 0, 0, &umr_bitfield_default },
+	 { "X2_LANE_3_2_OVRD", 1, 1, &umr_bitfield_default },
+	 { "X2_LANE_5_4_OVRD", 2, 2, &umr_bitfield_default },
+	 { "X2_LANE_7_6_OVRD", 3, 3, &umr_bitfield_default },
+	 { "X2_LANE_9_8_OVRD", 4, 4, &umr_bitfield_default },
+	 { "X2_LANE_11_10_OVRD", 5, 5, &umr_bitfield_default },
+	 { "X2_LANE_13_12_OVRD", 6, 6, &umr_bitfield_default },
+	 { "X2_LANE_15_14_OVRD", 7, 7, &umr_bitfield_default },
+	 { "X4_LANE_3_0_OVRD", 8, 8, &umr_bitfield_default },
+	 { "X4_LANE_7_4_OVRD", 9, 9, &umr_bitfield_default },
+	 { "X4_LANE_11_8_OVRD", 10, 10, &umr_bitfield_default },
+	 { "X4_LANE_15_12_OVRD", 11, 11, &umr_bitfield_default },
+	 { "X8_LANE_7_0_OVRD", 16, 16, &umr_bitfield_default },
+	 { "X8_LANE_15_8_OVRD", 17, 17, &umr_bitfield_default },
+	 { "X16_LANE_15_0_OVRD", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_BIF_CMD_STATUS[] = {
+	 { "TXPHYSTATUS_0", 0, 0, &umr_bitfield_default },
+	 { "TXPHYSTATUS_1", 1, 1, &umr_bitfield_default },
+	 { "TXPHYSTATUS_2", 2, 2, &umr_bitfield_default },
+	 { "TXPHYSTATUS_3", 3, 3, &umr_bitfield_default },
+	 { "TXPHYSTATUS_4", 4, 4, &umr_bitfield_default },
+	 { "TXPHYSTATUS_5", 5, 5, &umr_bitfield_default },
+	 { "TXPHYSTATUS_6", 6, 6, &umr_bitfield_default },
+	 { "TXPHYSTATUS_7", 7, 7, &umr_bitfield_default },
+	 { "RXPHYSTATUS_0", 8, 8, &umr_bitfield_default },
+	 { "RXPHYSTATUS_1", 9, 9, &umr_bitfield_default },
+	 { "RXPHYSTATUS_2", 10, 10, &umr_bitfield_default },
+	 { "RXPHYSTATUS_3", 11, 11, &umr_bitfield_default },
+	 { "RXPHYSTATUS_4", 12, 12, &umr_bitfield_default },
+	 { "RXPHYSTATUS_5", 13, 13, &umr_bitfield_default },
+	 { "RXPHYSTATUS_6", 14, 14, &umr_bitfield_default },
+	 { "RXPHYSTATUS_7", 15, 15, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_0", 16, 16, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_1", 17, 17, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_2", 18, 18, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_3", 19, 19, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_4", 20, 20, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_5", 21, 21, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_6", 22, 22, &umr_bitfield_default },
+	 { "BPHY_CORE_TX_RDY_7", 23, 23, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_0", 24, 24, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_1", 25, 25, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_2", 26, 26, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_3", 27, 27, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_4", 28, 28, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_5", 29, 29, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_6", 30, 30, &umr_bitfield_default },
+	 { "BPHY_CORE_RX_RDY_7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_CMD_BUS_CTRL[] = {
+	 { "CMD_BUS_SCHL_MODE", 0, 1, &umr_bitfield_default },
+	 { "CMD_BUS_STAG_MODE", 2, 3, &umr_bitfield_default },
+	 { "CMD_BUS_STAG_DIS", 4, 4, &umr_bitfield_default },
+	 { "CMD_BUS_SCH_REQ_MODE", 5, 6, &umr_bitfield_default },
+	 { "CMD_BUS_IGNR_PEND_PWR", 7, 7, &umr_bitfield_default },
+	 { "SEND_GANGED_MODE_UPDATE_FOR_OFFPG_LANES", 8, 8, &umr_bitfield_default },
+	 { "CMD_BUS_IGNR_PWR_NOT_ON", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_CMD_BUS_GLB_OVRD[] = {
+	 { "TXMARG_OVRD_EN", 0, 0, &umr_bitfield_default },
+	 { "DEEMPH_OVRD_EN", 1, 1, &umr_bitfield_default },
+	 { "PLLFREQ_OVRD_EN", 2, 2, &umr_bitfield_default },
+	 { "TXMARG", 3, 5, &umr_bitfield_default },
+	 { "DEEMPH", 6, 6, &umr_bitfield_default },
+	 { "PLLFREQ", 7, 8, &umr_bitfield_default },
+	 { "RESPONSEMODE_PIF_OVRD", 9, 9, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_0", 16, 16, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_1", 17, 17, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_2", 18, 18, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_3", 19, 19, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_4", 20, 20, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_5", 21, 21, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_6", 22, 22, &umr_bitfield_default },
+	 { "CMD_BUS_LANE_DIS_7", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE0_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_0", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_0", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_0", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_0", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_0", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_0", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_0", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_0", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_0", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_0", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_0", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_0", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_0", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_0", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_0", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_0", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_0", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_0", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE0_OVRD2[] = {
+	 { "GANGMODE_0", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_0", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_0", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_0", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_0", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_0", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_0", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_0", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_0", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_0", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_0", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_0", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_0", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_0", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_0", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_0", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE1_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_1", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_1", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_1", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_1", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_1", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_1", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_1", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_1", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_1", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_1", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_1", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_1", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_1", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_1", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_1", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_1", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_1", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE1_OVRD2[] = {
+	 { "GANGMODE_1", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_1", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_1", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_1", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_1", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_1", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_1", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_1", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_1", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_1", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_1", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_1", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_1", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_1", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_1", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE2_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_2", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_2", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_2", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_2", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_2", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_2", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_2", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_2", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_2", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_2", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_2", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_2", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_2", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_2", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_2", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_2", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_2", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_2", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE2_OVRD2[] = {
+	 { "GANGMODE_2", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_2", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_2", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_2", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_2", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_2", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_2", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_2", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_2", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_2", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_2", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_2", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_2", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_2", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_2", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_2", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE3_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_3", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_3", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_3", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_3", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_3", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_3", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_3", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_3", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_3", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_3", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_3", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_3", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_3", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_3", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_3", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_3", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_3", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_3", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE3_OVRD2[] = {
+	 { "GANGMODE_3", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_3", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_3", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_3", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_3", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_3", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_3", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_3", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_3", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_3", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_3", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_3", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_3", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_3", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_3", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_3", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE4_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_4", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_4", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_4", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_4", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_4", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_4", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_4", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_4", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_4", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_4", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_4", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_4", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_4", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_4", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_4", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_4", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_4", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_4", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE4_OVRD2[] = {
+	 { "GANGMODE_4", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_4", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_4", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_4", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_4", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_4", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_4", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_4", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_4", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_4", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_4", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_4", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_4", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_4", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_4", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_4", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE5_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_5", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_5", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_5", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_5", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_5", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_5", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_5", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_5", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_5", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_5", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_5", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_5", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_5", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_5", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_5", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_5", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_5", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_5", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE5_OVRD2[] = {
+	 { "GANGMODE_5", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_5", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_5", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_5", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_5", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_5", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_5", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_5", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_5", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_5", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_5", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_5", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_5", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_5", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_5", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_5", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE6_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_6", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_6", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_6", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_6", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_6", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_6", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_6", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_6", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_6", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_6", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_6", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_6", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_6", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_6", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_6", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_6", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_6", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_6", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE6_OVRD2[] = {
+	 { "GANGMODE_6", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_6", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_6", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_6", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_6", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_6", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_6", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_6", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_6", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_6", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_6", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_6", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_6", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_6", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_6", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_6", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE7_OVRD[] = {
+	 { "GANGMODE_OVRD_EN_7", 0, 0, &umr_bitfield_default },
+	 { "FREQDIV_OVRD_EN_7", 1, 1, &umr_bitfield_default },
+	 { "LINKSPEED_OVRD_EN_7", 2, 2, &umr_bitfield_default },
+	 { "TWOSYMENABLE_OVRD_EN_7", 3, 3, &umr_bitfield_default },
+	 { "TXPWR_OVRD_EN_7", 4, 4, &umr_bitfield_default },
+	 { "TXPGENABLE_OVRD_EN_7", 5, 5, &umr_bitfield_default },
+	 { "RXPWR_OVRD_EN_7", 6, 6, &umr_bitfield_default },
+	 { "RXPGENABLE_OVRD_EN_7", 7, 7, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_OVRD_EN_7", 8, 8, &umr_bitfield_default },
+	 { "ENABLEFOM_OVRD_EN_7", 9, 9, &umr_bitfield_default },
+	 { "REQUESTFOM_OVRD_EN_7", 10, 10, &umr_bitfield_default },
+	 { "RESPONSEMODE_OVRD_EN_7", 11, 11, &umr_bitfield_default },
+	 { "REQUESTTRK_OVRD_EN_7", 12, 12, &umr_bitfield_default },
+	 { "REQUESTTRN_OVRD_EN_7", 13, 13, &umr_bitfield_default },
+	 { "COEFFICIENTID_OVRD_EN_7", 14, 14, &umr_bitfield_default },
+	 { "COEFFICIENT_OVRD_EN_7", 15, 15, &umr_bitfield_default },
+	 { "CDREN_OVRD_EN_7", 16, 16, &umr_bitfield_default },
+	 { "CDREN_OVRD_VAL_7", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PIF0_LANE7_OVRD2[] = {
+	 { "GANGMODE_7", 0, 2, &umr_bitfield_default },
+	 { "FREQDIV_7", 3, 4, &umr_bitfield_default },
+	 { "LINKSPEED_7", 5, 6, &umr_bitfield_default },
+	 { "TWOSYMENABLE_7", 7, 7, &umr_bitfield_default },
+	 { "TXPWR_7", 8, 10, &umr_bitfield_default },
+	 { "TXPGENABLE_7", 11, 12, &umr_bitfield_default },
+	 { "RXPWR_7", 13, 15, &umr_bitfield_default },
+	 { "RXPGENABLE_7", 16, 17, &umr_bitfield_default },
+	 { "ELECIDLEDETEN_7", 18, 18, &umr_bitfield_default },
+	 { "ENABLEFOM_7", 19, 19, &umr_bitfield_default },
+	 { "REQUESTFOM_7", 20, 20, &umr_bitfield_default },
+	 { "RESPONSEMODE_7", 21, 21, &umr_bitfield_default },
+	 { "REQUESTTRK_7", 22, 22, &umr_bitfield_default },
+	 { "REQUESTTRN_7", 23, 23, &umr_bitfield_default },
+	 { "COEFFICIENTID_7", 24, 25, &umr_bitfield_default },
+	 { "COEFFICIENT_7", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVENDOR_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+	 { "LENGTH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_LANE0[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_LANE0[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_LANE0[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_LANE0[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_LANE0[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_LANE0[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_LANE1[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_LANE1[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_LANE1[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_LANE1[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_LANE1[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_LANE1[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_LANE2[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_LANE2[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_LANE2[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_LANE2[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_LANE2[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_LANE2[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_LANE3[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_LANE3[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_LANE3[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_LANE3[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_LANE3[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_LANE3[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_LANE4[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_LANE4[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_LANE4[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_LANE4[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_LANE4[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_LANE4[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_LANE5[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_LANE5[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_LANE5[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_LANE5[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_LANE5[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_LANE5[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_LANE6[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_LANE6[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_LANE6[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_LANE6[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_LANE6[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_LANE6[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_LANE7[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_LANE7[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_LANE7[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_LANE7[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_LANE7[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_LANE7[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_LANE0[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_LANE0[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_LANE0[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_LANE1[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_LANE1[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_LANE1[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_LANE2[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_LANE2[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_LANE2[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_LANE3[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_LANE3[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_LANE3[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_LANE4[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_LANE4[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_LANE4[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_LANE5[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_LANE5[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_LANE5[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_LANE6[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_LANE6[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_LANE6[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_LANE7[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_LANE7[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_LANE7[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt[] = {
+	 { "BgRcFiltShortTimer", 0, 2, &umr_bitfield_default },
+	 { "BgRcFiltShortForce", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl[] = {
+	 { "VcoRange", 0, 7, &umr_bitfield_default },
+	 { "VcoRangeBin", 8, 10, &umr_bitfield_default },
+	 { "LpfRes", 12, 13, &umr_bitfield_default },
+	 { "CpiDac3_0", 14, 17, &umr_bitfield_default },
+	 { "CpiDac7_4", 18, 21, &umr_bitfield_default },
+	 { "FastLockTimer", 22, 25, &umr_bitfield_default },
+	 { "FastLock", 26, 26, &umr_bitfield_default },
+	 { "ClearLockDetect", 28, 28, &umr_bitfield_default },
+	 { "PllLocked", 29, 29, &umr_bitfield_default },
+	 { "ManaregRampTimer", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1[] = {
+	 { "PllMeasCtl", 0, 10, &umr_bitfield_default },
+	 { "PllTp", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2[] = {
+	 { "PLC_MeasOut", 0, 17, &umr_bitfield_default },
+	 { "PLC_Tpo", 18, 18, &umr_bitfield_default },
+	 { "PllDsmObsSel", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode[] = {
+	 { "FullRateClkEn", 12, 12, &umr_bitfield_default },
+	 { "FullRateClkEnOvrd", 13, 13, &umr_bitfield_default },
+	 { "HalfRateClkEn", 16, 16, &umr_bitfield_default },
+	 { "HalfRateClkEnOvrd", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[] = {
+	 { "LCTankI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[] = {
+	 { "PllControlUpdate", 0, 0, &umr_bitfield_default },
+	 { "MeasCycleCnt", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3[] = {
+	 { "FinalFbCnt", 0, 13, &umr_bitfield_default },
+	 { "CalDone", 15, 15, &umr_bitfield_default },
+	 { "ManCalRdyNext", 16, 16, &umr_bitfield_default },
+	 { "CalFail", 17, 19, &umr_bitfield_default },
+	 { "ADCRefIn", 20, 25, &umr_bitfield_default },
+	 { "PLC_AdcOut", 26, 26, &umr_bitfield_default },
+	 { "StartCntEn", 27, 27, &umr_bitfield_default },
+	 { "ContinueCal", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4[] = {
+	 { "AltDiv", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5[] = {
+	 { "VregCtl7_0", 0, 7, &umr_bitfield_default },
+	 { "VregCtl11_8", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn[] = {
+	 { "PllPowerDownEn", 0, 2, &umr_bitfield_default },
+	 { "PllPowerDownOvrd", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt[] = {
+	 { "BgRcFiltShortTimer", 0, 2, &umr_bitfield_default },
+	 { "BgRcFiltShortForce", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl[] = {
+	 { "VcoRange", 0, 7, &umr_bitfield_default },
+	 { "LpfRes", 10, 13, &umr_bitfield_default },
+	 { "CpiDac", 14, 21, &umr_bitfield_default },
+	 { "FastLockTimer", 22, 25, &umr_bitfield_default },
+	 { "FastLock", 26, 26, &umr_bitfield_default },
+	 { "ClearLockDetect", 28, 28, &umr_bitfield_default },
+	 { "PllLocked", 29, 29, &umr_bitfield_default },
+	 { "ManaregRampTimer", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1[] = {
+	 { "PllMeasCtl", 0, 10, &umr_bitfield_default },
+	 { "PllTp", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2[] = {
+	 { "PLL_MeasOut", 0, 17, &umr_bitfield_default },
+	 { "PLL_Tpo", 18, 18, &umr_bitfield_default },
+	 { "PllDsmObsSel", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode[] = {
+	 { "PllClkFreq", 0, 6, &umr_bitfield_default },
+	 { "PllFreqModeOvrd", 7, 7, &umr_bitfield_default },
+	 { "Clk2CtlrEn", 8, 8, &umr_bitfield_default },
+	 { "Clk2CtlrEnOvrd", 9, 9, &umr_bitfield_default },
+	 { "Clk2CtlrRate", 10, 10, &umr_bitfield_default },
+	 { "Clk2CtlrRateOvrd", 11, 11, &umr_bitfield_default },
+	 { "FullRateClkEn", 12, 12, &umr_bitfield_default },
+	 { "FullRateClkEnOvrd", 13, 13, &umr_bitfield_default },
+	 { "HalfRateClkEn", 16, 16, &umr_bitfield_default },
+	 { "HalfRateClkEnOvrd", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[] = {
+	 { "PllControlUpdate", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3[] = {
+	 { "AutoTrigRoCal", 0, 0, &umr_bitfield_default },
+	 { "ManTrigRoCal", 1, 1, &umr_bitfield_default },
+	 { "ContinueCal", 2, 2, &umr_bitfield_default },
+	 { "CalDone", 3, 3, &umr_bitfield_default },
+	 { "ManCalRdyNext", 4, 4, &umr_bitfield_default },
+	 { "CalFail", 5, 6, &umr_bitfield_default },
+	 { "ADCRefIn", 20, 25, &umr_bitfield_default },
+	 { "PLL_AdcOut", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess[] = {
+	 { "PhyFuseValid", 0, 0, &umr_bitfield_default },
+	 { "FuseProcRefAdj", 1, 4, &umr_bitfield_default },
+	 { "FuseProcPllSpare", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4[] = {
+	 { "AltDiv", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5[] = {
+	 { "VregCtl7_0", 0, 7, &umr_bitfield_default },
+	 { "VregCtl11_8", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn[] = {
+	 { "PllPowerDownEn", 0, 2, &umr_bitfield_default },
+	 { "PllPowerDownOvrd", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_FUSE1[] = {
+	 { "fuse1_valid", 0, 0, &umr_bitfield_default },
+	 { "fuse1_ei_det_thresh_sel", 1, 2, &umr_bitfield_default },
+	 { "fuse1_dll_flock_disable", 3, 3, &umr_bitfield_default },
+	 { "fuse1_cdr_ph_gain_gen12", 4, 7, &umr_bitfield_default },
+	 { "fuse1_cdr_pi_stpsz_gen12", 8, 8, &umr_bitfield_default },
+	 { "fuse1_ron_ctl", 9, 10, &umr_bitfield_default },
+	 { "fuse1_rtt_ctl", 11, 12, &umr_bitfield_default },
+	 { "fuse1_rxdetect_samp_time", 18, 19, &umr_bitfield_default },
+	 { "fuse1_spare", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_FUSE2[] = {
+	 { "fuse2_valid", 0, 0, &umr_bitfield_default },
+	 { "fuse2_spare", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_FUSE3[] = {
+	 { "fuse3_valid", 0, 0, &umr_bitfield_default },
+	 { "fuse3_dll_cpi_sel", 1, 3, &umr_bitfield_default },
+	 { "fuse3_ron_override_val", 4, 9, &umr_bitfield_default },
+	 { "fuse3_rtt_override_val", 10, 15, &umr_bitfield_default },
+	 { "fuse3_lcpll_bw_adj", 16, 19, &umr_bitfield_default },
+	 { "fuse3_lcpll_ref_adj", 20, 23, &umr_bitfield_default },
+	 { "fuse3_ropll_ref_adj", 24, 27, &umr_bitfield_default },
+	 { "fuse3_refresh_cal_en", 28, 28, &umr_bitfield_default },
+	 { "fuse3_spare", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_ELECIDLE[] = {
+	 { "ei_det_dis_ps0", 0, 0, &umr_bitfield_default },
+	 { "ei_det_initiate_ofc_cal", 1, 1, &umr_bitfield_default },
+	 { "ei_det_dac_test_ofc_sel", 2, 2, &umr_bitfield_default },
+	 { "ei_det_dac_test_code", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_DFX[] = {
+	 { "nelb_en", 0, 0, &umr_bitfield_default },
+	 { "prbs_seed", 1, 10, &umr_bitfield_default },
+	 { "force_cdr_en", 11, 11, &umr_bitfield_default },
+	 { "ovrd_pll_on", 13, 13, &umr_bitfield_default },
+	 { "ovrd_clk_en", 15, 15, &umr_bitfield_default },
+	 { "dsm_sel", 17, 22, &umr_bitfield_default },
+	 { "dsm_en", 24, 27, &umr_bitfield_default },
+	 { "hold_rdy_response", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM[] = {
+	 { "tx_margin_nom", 0, 7, &umr_bitfield_default },
+	 { "deemph_gen1_nom", 8, 15, &umr_bitfield_default },
+	 { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default },
+	 { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_SELDEEMPH35[] = {
+	 { "deemph_3pt5db_1", 0, 7, &umr_bitfield_default },
+	 { "deemph_3pt5db_2", 8, 15, &umr_bitfield_default },
+	 { "deemph_3pt5db_3", 16, 23, &umr_bitfield_default },
+	 { "deemph_3pt5db_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_SELDEEMPH60[] = {
+	 { "deemph_6db_1", 0, 7, &umr_bitfield_default },
+	 { "deemph_6db_2", 8, 15, &umr_bitfield_default },
+	 { "deemph_6db_3", 16, 23, &umr_bitfield_default },
+	 { "deemph_6db_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT[] = {
+	 { "pgdelay", 0, 3, &umr_bitfield_default },
+	 { "pgmask", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_ADAPTCTL1[] = {
+	 { "adapt_cfg_fom_ber", 0, 2, &umr_bitfield_default },
+	 { "adapt_cfg_oc_time", 4, 7, &umr_bitfield_default },
+	 { "adapt_cfg_cdr_time", 9, 12, &umr_bitfield_default },
+	 { "adapt_cfg_leq_time", 14, 17, &umr_bitfield_default },
+	 { "adapt_cfg_dfe_time", 19, 22, &umr_bitfield_default },
+	 { "adapt_cfg_fom_time", 25, 28, &umr_bitfield_default },
+	 { "adapt_cfg_dfe_alg_sel", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_ADAPTCTL2[] = {
+	 { "adapt_cfg_leq_loop_gain", 0, 1, &umr_bitfield_default },
+	 { "adapt_cfg_ofc_loop_gain", 3, 6, &umr_bitfield_default },
+	 { "adapt_cfg_fom_loop_gain", 8, 11, &umr_bitfield_default },
+	 { "adapt_cfg_dfe_ref_loop_gain", 13, 16, &umr_bitfield_default },
+	 { "adapt_cfg_dfe_tap_loop_gain", 18, 21, &umr_bitfield_default },
+	 { "adapt_cfg_pi_off_range_rt", 23, 25, &umr_bitfield_default },
+	 { "adapt_cfg_pi_off_range_lt", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_val", 0, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_val", 6, 10, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_val", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_val", 17, 19, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_val", 22, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[] = {
+	 { "adapt_cfg_gen12_dfe_tp2_byp_val", 0, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_val", 8, 11, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_val", 13, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[] = {
+	 { "adapt_dbg_doff_byp_val", 0, 8, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_val", 11, 19, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_val", 22, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[] = {
+	 { "adapt_dbg_gen3_dfe_tp1_byp_val", 0, 5, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_val", 7, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1[] = {
+	 { "adapt_dbg_apu_mode", 0, 2, &umr_bitfield_default },
+	 { "adapt_dbg_apu_exec", 6, 8, &umr_bitfield_default },
+	 { "adapt_dbg_apu_inst", 10, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_LNCNTRL[] = {
+	 { "clkgate_dis", 5, 5, &umr_bitfield_default },
+	 { "dll_lock_time_sel", 6, 7, &umr_bitfield_default },
+	 { "cdr_lock_time_sel", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG[] = {
+	 { "test_single_leg_sel", 0, 4, &umr_bitfield_default },
+	 { "test_single_leg_en", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG[] = {
+	 { "rx2tx_bypass_sel", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_CDR_PHCTL[] = {
+	 { "cdr_pi_stpsz_gen3", 0, 0, &umr_bitfield_default },
+	 { "cdr_ph_gain_gen3", 7, 10, &umr_bitfield_default },
+	 { "cdr_ph_byp_val", 13, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_COM_COMMON_CDR_FRCTL[] = {
+	 { "cdr_fr_en", 0, 0, &umr_bitfield_default },
+	 { "cdr_fr_gain_gen12", 2, 5, &umr_bitfield_default },
+	 { "cdr_fr_gain_gen3", 7, 10, &umr_bitfield_default },
+	 { "cdr_fr_byp_val", 12, 20, &umr_bitfield_default },
+	 { "cdr_fr_limit", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RX_CTL_BROADCAST[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DLL_CTL_BROADCAST[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DFX_BROADCAST[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_DEEMPH_BROADCAST[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_TXCNTRL_BROADCAST[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_LANE0[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_LANE0[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_LANE0[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_LANE0[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_LANE0[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_LANE0[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_LANE1[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_LANE1[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_LANE1[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_LANE1[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_LANE1[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_LANE1[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_LANE2[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_LANE2[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_LANE2[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_LANE2[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_LANE2[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_LANE2[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_LANE3[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_LANE3[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_LANE3[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_LANE3[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_LANE3[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_LANE3[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_LANE4[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_LANE4[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_LANE4[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_LANE4[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_LANE4[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_LANE4[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_LANE5[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_LANE5[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_LANE5[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_LANE5[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_LANE5[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_LANE5[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_LANE6[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_LANE6[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_LANE6[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_LANE6[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_LANE6[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_LANE6[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_LANE7[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_LANE7[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_LANE7[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_LANE7[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_LANE7[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_LANE7[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_LANE0[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_LANE0[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_LANE0[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_LANE1[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_LANE1[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_LANE1[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_LANE2[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_LANE2[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_LANE2[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_LANE3[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_LANE3[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_LANE3[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_LANE4[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_LANE4[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_LANE4[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_LANE5[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_LANE5[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_LANE5[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_LANE6[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_LANE6[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_LANE6[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_LANE7[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_LANE7[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_LANE7[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt[] = {
+	 { "BgRcFiltShortTimer", 0, 2, &umr_bitfield_default },
+	 { "BgRcFiltShortForce", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl[] = {
+	 { "VcoRange", 0, 7, &umr_bitfield_default },
+	 { "VcoRangeBin", 8, 10, &umr_bitfield_default },
+	 { "LpfRes", 12, 13, &umr_bitfield_default },
+	 { "CpiDac3_0", 14, 17, &umr_bitfield_default },
+	 { "CpiDac7_4", 18, 21, &umr_bitfield_default },
+	 { "FastLockTimer", 22, 25, &umr_bitfield_default },
+	 { "FastLock", 26, 26, &umr_bitfield_default },
+	 { "ClearLockDetect", 28, 28, &umr_bitfield_default },
+	 { "PllLocked", 29, 29, &umr_bitfield_default },
+	 { "ManaregRampTimer", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1[] = {
+	 { "PllMeasCtl", 0, 10, &umr_bitfield_default },
+	 { "PllTp", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2[] = {
+	 { "PLC_MeasOut", 0, 17, &umr_bitfield_default },
+	 { "PLC_Tpo", 18, 18, &umr_bitfield_default },
+	 { "PllDsmObsSel", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode[] = {
+	 { "FullRateClkEn", 12, 12, &umr_bitfield_default },
+	 { "FullRateClkEnOvrd", 13, 13, &umr_bitfield_default },
+	 { "HalfRateClkEn", 16, 16, &umr_bitfield_default },
+	 { "HalfRateClkEnOvrd", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[] = {
+	 { "LCTankI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[] = {
+	 { "PllControlUpdate", 0, 0, &umr_bitfield_default },
+	 { "MeasCycleCnt", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3[] = {
+	 { "FinalFbCnt", 0, 13, &umr_bitfield_default },
+	 { "CalDone", 15, 15, &umr_bitfield_default },
+	 { "ManCalRdyNext", 16, 16, &umr_bitfield_default },
+	 { "CalFail", 17, 19, &umr_bitfield_default },
+	 { "ADCRefIn", 20, 25, &umr_bitfield_default },
+	 { "PLC_AdcOut", 26, 26, &umr_bitfield_default },
+	 { "StartCntEn", 27, 27, &umr_bitfield_default },
+	 { "ContinueCal", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4[] = {
+	 { "AltDiv", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5[] = {
+	 { "VregCtl7_0", 0, 7, &umr_bitfield_default },
+	 { "VregCtl11_8", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn[] = {
+	 { "PllPowerDownEn", 0, 2, &umr_bitfield_default },
+	 { "PllPowerDownOvrd", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt[] = {
+	 { "BgRcFiltShortTimer", 0, 2, &umr_bitfield_default },
+	 { "BgRcFiltShortForce", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl[] = {
+	 { "VcoRange", 0, 7, &umr_bitfield_default },
+	 { "LpfRes", 10, 13, &umr_bitfield_default },
+	 { "CpiDac", 14, 21, &umr_bitfield_default },
+	 { "FastLockTimer", 22, 25, &umr_bitfield_default },
+	 { "FastLock", 26, 26, &umr_bitfield_default },
+	 { "ClearLockDetect", 28, 28, &umr_bitfield_default },
+	 { "PllLocked", 29, 29, &umr_bitfield_default },
+	 { "ManaregRampTimer", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1[] = {
+	 { "PllMeasCtl", 0, 10, &umr_bitfield_default },
+	 { "PllTp", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2[] = {
+	 { "PLL_MeasOut", 0, 17, &umr_bitfield_default },
+	 { "PLL_Tpo", 18, 18, &umr_bitfield_default },
+	 { "PllDsmObsSel", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode[] = {
+	 { "PllClkFreq", 0, 6, &umr_bitfield_default },
+	 { "PllFreqModeOvrd", 7, 7, &umr_bitfield_default },
+	 { "Clk2CtlrEn", 8, 8, &umr_bitfield_default },
+	 { "Clk2CtlrEnOvrd", 9, 9, &umr_bitfield_default },
+	 { "Clk2CtlrRate", 10, 10, &umr_bitfield_default },
+	 { "Clk2CtlrRateOvrd", 11, 11, &umr_bitfield_default },
+	 { "FullRateClkEn", 12, 12, &umr_bitfield_default },
+	 { "FullRateClkEnOvrd", 13, 13, &umr_bitfield_default },
+	 { "HalfRateClkEn", 16, 16, &umr_bitfield_default },
+	 { "HalfRateClkEnOvrd", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[] = {
+	 { "PllControlUpdate", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3[] = {
+	 { "AutoTrigRoCal", 0, 0, &umr_bitfield_default },
+	 { "ManTrigRoCal", 1, 1, &umr_bitfield_default },
+	 { "ContinueCal", 2, 2, &umr_bitfield_default },
+	 { "CalDone", 3, 3, &umr_bitfield_default },
+	 { "ManCalRdyNext", 4, 4, &umr_bitfield_default },
+	 { "CalFail", 5, 6, &umr_bitfield_default },
+	 { "ADCRefIn", 20, 25, &umr_bitfield_default },
+	 { "PLL_AdcOut", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess[] = {
+	 { "PhyFuseValid", 0, 0, &umr_bitfield_default },
+	 { "FuseProcRefAdj", 1, 4, &umr_bitfield_default },
+	 { "FuseProcPllSpare", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4[] = {
+	 { "AltDiv", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5[] = {
+	 { "VregCtl7_0", 0, 7, &umr_bitfield_default },
+	 { "VregCtl11_8", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn[] = {
+	 { "PllPowerDownEn", 0, 2, &umr_bitfield_default },
+	 { "PllPowerDownOvrd", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_FUSE1[] = {
+	 { "fuse1_valid", 0, 0, &umr_bitfield_default },
+	 { "fuse1_ei_det_thresh_sel", 1, 2, &umr_bitfield_default },
+	 { "fuse1_dll_flock_disable", 3, 3, &umr_bitfield_default },
+	 { "fuse1_cdr_ph_gain_gen12", 4, 7, &umr_bitfield_default },
+	 { "fuse1_cdr_pi_stpsz_gen12", 8, 8, &umr_bitfield_default },
+	 { "fuse1_ron_ctl", 9, 10, &umr_bitfield_default },
+	 { "fuse1_rtt_ctl", 11, 12, &umr_bitfield_default },
+	 { "fuse1_rxdetect_samp_time", 18, 19, &umr_bitfield_default },
+	 { "fuse1_spare", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_FUSE2[] = {
+	 { "fuse2_valid", 0, 0, &umr_bitfield_default },
+	 { "fuse2_spare", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_FUSE3[] = {
+	 { "fuse3_valid", 0, 0, &umr_bitfield_default },
+	 { "fuse3_dll_cpi_sel", 1, 3, &umr_bitfield_default },
+	 { "fuse3_ron_override_val", 4, 9, &umr_bitfield_default },
+	 { "fuse3_rtt_override_val", 10, 15, &umr_bitfield_default },
+	 { "fuse3_lcpll_bw_adj", 16, 19, &umr_bitfield_default },
+	 { "fuse3_lcpll_ref_adj", 20, 23, &umr_bitfield_default },
+	 { "fuse3_ropll_ref_adj", 24, 27, &umr_bitfield_default },
+	 { "fuse3_refresh_cal_en", 28, 28, &umr_bitfield_default },
+	 { "fuse3_spare", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_ELECIDLE[] = {
+	 { "ei_det_dis_ps0", 0, 0, &umr_bitfield_default },
+	 { "ei_det_initiate_ofc_cal", 1, 1, &umr_bitfield_default },
+	 { "ei_det_dac_test_ofc_sel", 2, 2, &umr_bitfield_default },
+	 { "ei_det_dac_test_code", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_DFX[] = {
+	 { "nelb_en", 0, 0, &umr_bitfield_default },
+	 { "prbs_seed", 1, 10, &umr_bitfield_default },
+	 { "force_cdr_en", 11, 11, &umr_bitfield_default },
+	 { "ovrd_pll_on", 13, 13, &umr_bitfield_default },
+	 { "ovrd_clk_en", 15, 15, &umr_bitfield_default },
+	 { "dsm_sel", 17, 22, &umr_bitfield_default },
+	 { "dsm_en", 24, 27, &umr_bitfield_default },
+	 { "hold_rdy_response", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM[] = {
+	 { "tx_margin_nom", 0, 7, &umr_bitfield_default },
+	 { "deemph_gen1_nom", 8, 15, &umr_bitfield_default },
+	 { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default },
+	 { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_SELDEEMPH35[] = {
+	 { "deemph_3pt5db_1", 0, 7, &umr_bitfield_default },
+	 { "deemph_3pt5db_2", 8, 15, &umr_bitfield_default },
+	 { "deemph_3pt5db_3", 16, 23, &umr_bitfield_default },
+	 { "deemph_3pt5db_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_SELDEEMPH60[] = {
+	 { "deemph_6db_1", 0, 7, &umr_bitfield_default },
+	 { "deemph_6db_2", 8, 15, &umr_bitfield_default },
+	 { "deemph_6db_3", 16, 23, &umr_bitfield_default },
+	 { "deemph_6db_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT[] = {
+	 { "pgdelay", 0, 3, &umr_bitfield_default },
+	 { "pgmask", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_ADAPTCTL1[] = {
+	 { "adapt_cfg_fom_ber", 0, 2, &umr_bitfield_default },
+	 { "adapt_cfg_oc_time", 4, 7, &umr_bitfield_default },
+	 { "adapt_cfg_cdr_time", 9, 12, &umr_bitfield_default },
+	 { "adapt_cfg_leq_time", 14, 17, &umr_bitfield_default },
+	 { "adapt_cfg_dfe_time", 19, 22, &umr_bitfield_default },
+	 { "adapt_cfg_fom_time", 25, 28, &umr_bitfield_default },
+	 { "adapt_cfg_dfe_alg_sel", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_ADAPTCTL2[] = {
+	 { "adapt_cfg_leq_loop_gain", 0, 1, &umr_bitfield_default },
+	 { "adapt_cfg_ofc_loop_gain", 3, 6, &umr_bitfield_default },
+	 { "adapt_cfg_fom_loop_gain", 8, 11, &umr_bitfield_default },
+	 { "adapt_cfg_dfe_ref_loop_gain", 13, 16, &umr_bitfield_default },
+	 { "adapt_cfg_dfe_tap_loop_gain", 18, 21, &umr_bitfield_default },
+	 { "adapt_cfg_pi_off_range_rt", 23, 25, &umr_bitfield_default },
+	 { "adapt_cfg_pi_off_range_lt", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_val", 0, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_val", 6, 10, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_val", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_val", 17, 19, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_val", 22, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[] = {
+	 { "adapt_cfg_gen12_dfe_tp2_byp_val", 0, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_val", 8, 11, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_val", 13, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[] = {
+	 { "adapt_dbg_doff_byp_val", 0, 8, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_val", 11, 19, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_val", 22, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[] = {
+	 { "adapt_dbg_gen3_dfe_tp1_byp_val", 0, 5, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_val", 7, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1[] = {
+	 { "adapt_dbg_apu_mode", 0, 2, &umr_bitfield_default },
+	 { "adapt_dbg_apu_exec", 6, 8, &umr_bitfield_default },
+	 { "adapt_dbg_apu_inst", 10, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_LNCNTRL[] = {
+	 { "clkgate_dis", 5, 5, &umr_bitfield_default },
+	 { "dll_lock_time_sel", 6, 7, &umr_bitfield_default },
+	 { "cdr_lock_time_sel", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG[] = {
+	 { "test_single_leg_sel", 0, 4, &umr_bitfield_default },
+	 { "test_single_leg_en", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG[] = {
+	 { "rx2tx_bypass_sel", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_CDR_PHCTL[] = {
+	 { "cdr_pi_stpsz_gen3", 0, 0, &umr_bitfield_default },
+	 { "cdr_ph_gain_gen3", 7, 10, &umr_bitfield_default },
+	 { "cdr_ph_byp_val", 13, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_COM_COMMON_CDR_FRCTL[] = {
+	 { "cdr_fr_en", 0, 0, &umr_bitfield_default },
+	 { "cdr_fr_gain_gen12", 2, 5, &umr_bitfield_default },
+	 { "cdr_fr_gain_gen3", 7, 10, &umr_bitfield_default },
+	 { "cdr_fr_byp_val", 12, 20, &umr_bitfield_default },
+	 { "cdr_fr_limit", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[] = {
+	 { "rx_pwr", 0, 2, &umr_bitfield_default },
+	 { "rx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "eidet_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RX_CTL_BROADCAST[] = {
+	 { "rx_dfr_dis", 0, 0, &umr_bitfield_default },
+	 { "rx_dac_vdc", 1, 8, &umr_bitfield_default },
+	 { "rx_term_mode", 11, 12, &umr_bitfield_default },
+	 { "rx_vdc_dac_tri", 13, 13, &umr_bitfield_default },
+	 { "rx_vdc_dac_fixed_polarity", 14, 14, &umr_bitfield_default },
+	 { "rx_dfr_data_sign", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DLL_CTL_BROADCAST[] = {
+	 { "dll_dbg_clk_sel", 0, 2, &umr_bitfield_default },
+	 { "dll_dbg_vreg_ref_sel", 4, 4, &umr_bitfield_default },
+	 { "dll_analog_obs_en", 5, 5, &umr_bitfield_default },
+	 { "dll_surge_ctrl", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST[] = {
+	 { "prbs_clr", 0, 0, &umr_bitfield_default },
+	 { "prbs_err", 1, 1, &umr_bitfield_default },
+	 { "rx_dfr_force", 4, 4, &umr_bitfield_default },
+	 { "rx_force_leq_en", 5, 5, &umr_bitfield_default },
+	 { "rx_byp_ac_cap", 6, 6, &umr_bitfield_default },
+	 { "rx_byp_res", 7, 7, &umr_bitfield_default },
+	 { "rx_raw_pin_gate", 8, 8, &umr_bitfield_default },
+	 { "rx_force_short_vdc_out", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[] = {
+	 { "ei_det_async_ei", 0, 0, &umr_bitfield_default },
+	 { "ei_det_ofc_comp_out", 1, 1, &umr_bitfield_default },
+	 { "ei_det_ofc_out_of_bounds", 2, 2, &umr_bitfield_default },
+	 { "ei_det_thresh_adj", 3, 8, &umr_bitfield_default },
+	 { "ei_det_dac_test_en", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST[] = {
+	 { "adapt_cfg_mode", 0, 9, &umr_bitfield_default },
+	 { "adapt_cfg_track_sel", 13, 15, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_save_off", 17, 17, &umr_bitfield_default },
+	 { "adapt_cfg_pwr_down_time_sel", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST[] = {
+	 { "rx_fom_valid", 0, 0, &umr_bitfield_default },
+	 { "rx_eye_fom", 1, 8, &umr_bitfield_default },
+	 { "enable_fom", 11, 11, &umr_bitfield_default },
+	 { "request_fom", 12, 12, &umr_bitfield_default },
+	 { "request_trk", 13, 13, &umr_bitfield_default },
+	 { "request_trn", 14, 14, &umr_bitfield_default },
+	 { "response_mode", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[] = {
+	 { "adapt_cfg_gen12_leq_dcattn_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_dcattn_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_leq_pole_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_leq_pole_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp1_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_dfe_tp2_byp_en", 5, 5, &umr_bitfield_default },
+	 { "adapt_cfg_gen12_pi_off_byp_en", 6, 6, &umr_bitfield_default },
+	 { "adapt_cfg_gen3_pi_off_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST[] = {
+	 { "adapt_dbg_doff_byp_en", 0, 0, &umr_bitfield_default },
+	 { "adapt_dbg_xoff_byp_en", 1, 1, &umr_bitfield_default },
+	 { "adapt_dbg_eoff_byp_en", 2, 2, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp1_byp_en", 3, 3, &umr_bitfield_default },
+	 { "adapt_dbg_gen3_dfe_tp2_byp_en", 4, 4, &umr_bitfield_default },
+	 { "adapt_dbg_leq_dcattn_byp_ovr_disable", 5, 5, &umr_bitfield_default },
+	 { "cdr_ph_byp_en", 6, 6, &umr_bitfield_default },
+	 { "cdr_fr_byp_en", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST[] = {
+	 { "adapt_dbg_bus_sel", 0, 3, &umr_bitfield_default },
+	 { "adapt_dbg_bus_out", 6, 16, &umr_bitfield_default },
+	 { "adapt_dbg_force_rst", 19, 19, &umr_bitfield_default },
+	 { "adapt_dbg_force_en", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DFX_BROADCAST[] = {
+	 { "obs_en", 0, 0, &umr_bitfield_default },
+	 { "obs_sel", 2, 2, &umr_bitfield_default },
+	 { "felb_en", 4, 4, &umr_bitfield_default },
+	 { "prbs_en", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_DEEMPH_BROADCAST[] = {
+	 { "gen3_coeff_cm1", 0, 7, &umr_bitfield_default },
+	 { "gen3_coeff_c0", 8, 13, &umr_bitfield_default },
+	 { "gen3_coeff_cp1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph35_sel", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[] = {
+	 { "ron_comp_binary", 0, 4, &umr_bitfield_default },
+	 { "ron_comp_valid", 6, 6, &umr_bitfield_default },
+	 { "too_many_allocated", 8, 8, &umr_bitfield_default },
+	 { "alloc_error", 10, 10, &umr_bitfield_default },
+	 { "first_allocation_done", 12, 12, &umr_bitfield_default },
+	 { "total_legs_allocated", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_TXCNTRL_BROADCAST[] = {
+	 { "rxdetect_response", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[] = {
+	 { "twosym_en", 0, 0, &umr_bitfield_default },
+	 { "link_speed", 1, 2, &umr_bitfield_default },
+	 { "freq_div2", 3, 3, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmADAPTER_ID_W[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_BACO_MSIC_IND[] = {
+	 { "BIF_XTALIN_SEL", 0, 0, &umr_bitfield_default },
+	 { "BACO_LINK_RST_SEL", 1, 2, &umr_bitfield_default },
+	 { "ACPI_BACO_MUX_DIS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_PIF_TXCLK_SWITCH_TIMER_IND[] = {
+	 { "PLL0_ACK_TIMER", 0, 2, &umr_bitfield_default },
+	 { "PLL1_ACK_TIMER", 3, 5, &umr_bitfield_default },
+	 { "PLL_SWITCH_TIMER", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RESET_EN_IND[] = {
+	 { "SOFT_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "PHY_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "COR_RESET_EN", 3, 3, &umr_bitfield_default },
+	 { "REG_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "STY_RESET_EN", 5, 5, &umr_bitfield_default },
+	 { "CFG_RESET_EN", 6, 6, &umr_bitfield_default },
+	 { "DRV_RESET_EN", 7, 7, &umr_bitfield_default },
+	 { "RESET_CFGREG_ONLY_EN", 8, 8, &umr_bitfield_default },
+	 { "HOT_RESET_EN", 9, 9, &umr_bitfield_default },
+	 { "LINK_DISABLE_RESET_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_DOWN_RESET_EN", 11, 11, &umr_bitfield_default },
+	 { "CFG_RESET_PULSE_WIDTH", 12, 17, &umr_bitfield_default },
+	 { "DRV_RESET_DELAY_SEL", 18, 19, &umr_bitfield_default },
+	 { "PIF_RSTB_EN", 20, 20, &umr_bitfield_default },
+	 { "PIF_STRAP_ALLVALID_EN", 21, 21, &umr_bitfield_default },
+	 { "BIF_COR_RESET_EN", 22, 22, &umr_bitfield_default },
+	 { "FUNC0_FLR_EN", 23, 23, &umr_bitfield_default },
+	 { "FUNC1_FLR_EN", 24, 24, &umr_bitfield_default },
+	 { "FUNC2_FLR_EN", 25, 25, &umr_bitfield_default },
+	 { "FUNC0_RESET_DELAY_SEL", 26, 27, &umr_bitfield_default },
+	 { "FUNC1_RESET_DELAY_SEL", 28, 29, &umr_bitfield_default },
+	 { "FUNC2_RESET_DELAY_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_CLK_PDWN_DELAY_TIMER_IND[] = {
+	 { "TIMER", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixNEW_REFCLKB_TIMER_1_IND[] = {
+	 { "PHY_PLL_PDWN_TIMER", 0, 9, &umr_bitfield_default },
+	 { "PLL0_PDNB_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixNEW_REFCLKB_TIMER_IND[] = {
+	 { "REG_STOP_REFCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "STOP_REFCLK_TIMER", 1, 20, &umr_bitfield_default },
+	 { "REFCLK_ON", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RESET_CNTL_IND[] = {
+	 { "STRAP_EN", 0, 0, &umr_bitfield_default },
+	 { "RST_DONE", 1, 1, &umr_bitfield_default },
+	 { "LINK_TRAIN_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_ALL_VALID", 3, 3, &umr_bitfield_default },
+	 { "RECAP_STRAP_WARMRST", 8, 8, &umr_bitfield_default },
+	 { "HOLD_LKTRN_WARMRST_DIS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLNCNT_CONTROL_IND[] = {
+	 { "LNCNT_ACC_MODE", 0, 0, &umr_bitfield_default },
+	 { "LNCNT_REF_TIMEBASE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_LNCNT_RESET_IND[] = {
+	 { "RESET_LNCNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_CLOCKS_BITS_IND[] = {
+	 { "OBFF_XSL_FORCE_REFCLK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_MEM_PG_CNTL_IND[] = {
+	 { "BIF_MEM_SD_EN", 0, 0, &umr_bitfield_default },
+	 { "BIF_MEM_SD_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBIF_RFE_CNTL_MISC_IND[] = {
+	 { "ADAPT_pif0_bu_reg_accessMode", 0, 0, &umr_bitfield_default },
+	 { "ADAPT_pif1_bu_reg_accessMode", 1, 1, &umr_bitfield_default },
+	 { "ADAPT_pwreg_bu_reg_accessMode", 2, 2, &umr_bitfield_default },
+	 { "ADAPT_pciecore0_bu_reg_accessMode", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_WRAP_SCRATCH1[] = {
+	 { "PCIE_WRAP_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_WRAP_SCRATCH2[] = {
+	 { "PCIE_WRAP_SCRATCH2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC[] = {
+	 { "CLKEN_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_WRAP_DTM_MISC[] = {
+	 { "DTM_BULKPHY_FREQDIV_OVERRIDE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[] = {
+	 { "END_BIFCORE_REGISTER_DAISYCHAIN", 0, 0, &umr_bitfield_default },
+	 { "END_WRAPPER_REGISTER_DAISYCHAIN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_WRAP_MISC[] = {
+	 { "HOLD_TRAINING_STICKY", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_QUICKSIM_START", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_WRAP_PIF_MISC[] = {
+	 { "DTM_PIF_DELAY_FI", 0, 2, &umr_bitfield_default },
+	 { "DTM_PIF_DELAY_DI", 4, 6, &umr_bitfield_default },
+	 { "DTM_PIF_ATSEL_FI", 7, 7, &umr_bitfield_default },
+	 { "DTM_PIF_ATSEL_DI", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_RXDET_OVERRIDE[] = {
+	 { "RxDetOvrVal", 0, 7, &umr_bitfield_default },
+	 { "RxDetOvrEn", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_IMPCTL_CNTL_PIF0[] = {
+	 { "ArbEn0", 0, 0, &umr_bitfield_default },
+	 { "QuickSimOverRide0", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL[] = {
+	 { "ACCESS_MODE_pciecore0", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL[] = {
+	 { "ACCESS_MODE_pwregt", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL[] = {
+	 { "ACCESS_MODE_pwregr", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_REG_ADAPT_pif0_CONTROL[] = {
+	 { "ACCESS_MODE_pif0", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIOSTIMER_CMD[] = {
+	 { "Microseconds", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIOSTIMER_CNTL[] = {
+	 { "ClockRate", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIOSTIMER_DEBUG[] = {
+	 { "Microseconds_compare", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DELAYLINE_COMMAND[] = {
+	 { "CFG_DPC_modeCharz", 0, 0, &umr_bitfield_default },
+	 { "CFG_DPC_modeMaintainLock", 1, 1, &umr_bitfield_default },
+	 { "CFG_DPC_modeWidePhase", 2, 2, &umr_bitfield_default },
+	 { "CFG_DPC_modeOverrideDelay", 3, 3, &umr_bitfield_default },
+	 { "CFG_DPC_delayOverride", 8, 15, &umr_bitfield_default },
+	 { "CFG_DPC_cmdIdle", 16, 16, &umr_bitfield_default },
+	 { "CFG_DPC_cmdStart", 17, 17, &umr_bitfield_default },
+	 { "CFG_DPC_cmdRestart", 18, 18, &umr_bitfield_default },
+	 { "CFG_DPC_Enable", 20, 20, &umr_bitfield_default },
+	 { "CFG_DPC_FastCkStable", 21, 21, &umr_bitfield_default },
+	 { "CFG_DPC_spare", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DELAYLINE_STATUS[] = {
+	 { "DPC_CFG_controllerIdle", 0, 0, &umr_bitfield_default },
+	 { "DPC_CFG_commandComplete", 1, 1, &umr_bitfield_default },
+	 { "DPC_CFG_phaseLocked", 2, 2, &umr_bitfield_default },
+	 { "DPC_CFG_posAlignmentVld", 3, 3, &umr_bitfield_default },
+	 { "DPC_CFG_negAlignmentVld", 4, 4, &umr_bitfield_default },
+	 { "DPC_CFG_posDelayValue", 8, 15, &umr_bitfield_default },
+	 { "DPC_CFG_negDelayValue", 16, 23, &umr_bitfield_default },
+	 { "DPC_CFG_freqRatio", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DTM_RX_BP_CNTL[] = {
+	 { "rxElasBP_Cntl", 0, 7, &umr_bitfield_default },
+	 { "Dbg_Cntl", 16, 19, &umr_bitfield_default },
+	 { "rxElasBP_SlideValue", 20, 23, &umr_bitfield_default },
+	 { "td_hold_training_override", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DTM_CNTL[] = {
+	 { "Dtm_Dummy0", 0, 0, &umr_bitfield_default },
+	 { "Dtm_Dummy1", 1, 1, &umr_bitfield_default },
+	 { "Determinism_En_DTM", 2, 2, &umr_bitfield_default },
+	 { "Dtm_Dummy2", 3, 3, &umr_bitfield_default },
+	 { "Dtm_Dummy3", 4, 4, &umr_bitfield_default },
+	 { "Dtm_Dummy4", 5, 5, &umr_bitfield_default },
+	 { "Dtm_Dummy5", 6, 6, &umr_bitfield_default },
+	 { "Dtm_Dummy6", 7, 7, &umr_bitfield_default },
+	 { "TxClk1x_Cntl", 8, 9, &umr_bitfield_default },
+	 { "TxClkGskt_Cntl", 10, 11, &umr_bitfield_default },
+	 { "refClk_Cntl", 12, 13, &umr_bitfield_default },
+	 { "dtmClk_Sel_Timer", 14, 15, &umr_bitfield_default },
+	 { "Dtm_Dummy7", 16, 16, &umr_bitfield_default },
+	 { "Dtm_Dummy8", 17, 17, &umr_bitfield_default },
+	 { "Dtm_Dummy9", 18, 18, &umr_bitfield_default },
+	 { "Dtm_Dummy10", 19, 19, &umr_bitfield_default },
+	 { "Dtm_Dummy11", 20, 20, &umr_bitfield_default },
+	 { "Dtm_Dummy12", 21, 21, &umr_bitfield_default },
+	 { "rxElasWidth_Cntl", 22, 23, &umr_bitfield_default },
+	 { "Dtm_Dummy13", 24, 24, &umr_bitfield_default },
+	 { "Dtm_Dummy14", 25, 25, &umr_bitfield_default },
+	 { "Dtm_Dummy15", 26, 26, &umr_bitfield_default },
+	 { "Dtm_Dummy16", 27, 27, &umr_bitfield_default },
+	 { "Dtm_Dummy17", 28, 28, &umr_bitfield_default },
+	 { "Warm_RstTimer", 29, 30, &umr_bitfield_default },
+	 { "Dtm_Dummy18", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DTM_CNTL_LEGACY[] = {
+	 { "Dtm_Dummy19", 0, 0, &umr_bitfield_default },
+	 { "fifoInit_one_dropout", 1, 1, &umr_bitfield_default },
+	 { "Dtm_Clk_2sym", 2, 2, &umr_bitfield_default },
+	 { "Dtm_GsktClk_2sym", 3, 3, &umr_bitfield_default },
+	 { "Dtm_hardRst_slide", 4, 5, &umr_bitfield_default },
+	 { "Dtm_earlyRst_slide", 6, 7, &umr_bitfield_default },
+	 { "Dtm_txPhyStsOk_slide", 8, 9, &umr_bitfield_default },
+	 { "Dtm_Sti_TXCLK_Period", 12, 15, &umr_bitfield_default },
+	 { "Dtm_Sti_TXCLK_Send", 16, 19, &umr_bitfield_default },
+	 { "Dtm_Sti_TXCLK_Rcv", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DTM_STI_LCLK_CTRL[] = {
+	 { "Dtm_Sti_LCLK_Period", 0, 8, &umr_bitfield_default },
+	 { "Dtm_Sti_LCLK_Send", 9, 17, &umr_bitfield_default },
+	 { "Dtm_Sti_LCLK_Rcv", 18, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[] = {
+	 { "DentistGate_startTime_DI_clk10x", 0, 7, &umr_bitfield_default },
+	 { "DentistGate_dropoutTime_DI_clk10x", 8, 15, &umr_bitfield_default },
+	 { "DentistGate_stopTime_DI_clk10x", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[] = {
+	 { "DentistGate_startTime_DI_clkGskt", 0, 7, &umr_bitfield_default },
+	 { "DentistGate_dropoutTime_DI_clkGskt", 8, 15, &umr_bitfield_default },
+	 { "DentistGate_stopTime_DI_clkGskt", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[] = {
+	 { "DentistGate_startTime_FI_clk10x", 0, 7, &umr_bitfield_default },
+	 { "DentistGate_dropoutTime_FI_clk10x", 8, 15, &umr_bitfield_default },
+	 { "DentistGate_stopTime_FI_clk10x", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[] = {
+	 { "DentistGate_startTime_FI_clkGskt", 0, 7, &umr_bitfield_default },
+	 { "DentistGate_dropoutTime_FI_clkGskt", 8, 15, &umr_bitfield_default },
+	 { "DentistGate_stopTime_FI_clkGskt", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_WRAP_SCRATCH1[] = {
+	 { "PCIE_WRAP_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_WRAP_SCRATCH2[] = {
+	 { "PCIE_WRAP_SCRATCH2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC[] = {
+	 { "CLKEN_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_WRAP_DTM_MISC[] = {
+	 { "DTM_BULKPHY_FREQDIV_OVERRIDE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[] = {
+	 { "END_BIFCORE_REGISTER_DAISYCHAIN", 0, 0, &umr_bitfield_default },
+	 { "END_WRAPPER_REGISTER_DAISYCHAIN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_WRAP_MISC[] = {
+	 { "HOLD_TRAINING_STICKY", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_QUICKSIM_START", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_WRAP_PIF_MISC[] = {
+	 { "DTM_PIF_DELAY_FI", 0, 2, &umr_bitfield_default },
+	 { "DTM_PIF_DELAY_DI", 4, 6, &umr_bitfield_default },
+	 { "DTM_PIF_ATSEL_FI", 7, 7, &umr_bitfield_default },
+	 { "DTM_PIF_ATSEL_DI", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_RXDET_OVERRIDE[] = {
+	 { "RxDetOvrVal", 0, 7, &umr_bitfield_default },
+	 { "RxDetOvrEn", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_IMPCTL_CNTL_PIF0[] = {
+	 { "ArbEn0", 0, 0, &umr_bitfield_default },
+	 { "QuickSimOverRide0", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL[] = {
+	 { "ACCESS_MODE_pciecore0", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL[] = {
+	 { "ACCESS_MODE_pwregt", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL[] = {
+	 { "ACCESS_MODE_pwregr", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_REG_ADAPT_pif0_CONTROL[] = {
+	 { "ACCESS_MODE_pif0", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIOSTIMER_CMD[] = {
+	 { "Microseconds", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIOSTIMER_CNTL[] = {
+	 { "ClockRate", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIOSTIMER_DEBUG[] = {
+	 { "Microseconds_compare", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DELAYLINE_COMMAND[] = {
+	 { "CFG_DPC_modeCharz", 0, 0, &umr_bitfield_default },
+	 { "CFG_DPC_modeMaintainLock", 1, 1, &umr_bitfield_default },
+	 { "CFG_DPC_modeWidePhase", 2, 2, &umr_bitfield_default },
+	 { "CFG_DPC_modeOverrideDelay", 3, 3, &umr_bitfield_default },
+	 { "CFG_DPC_delayOverride", 8, 15, &umr_bitfield_default },
+	 { "CFG_DPC_cmdIdle", 16, 16, &umr_bitfield_default },
+	 { "CFG_DPC_cmdStart", 17, 17, &umr_bitfield_default },
+	 { "CFG_DPC_cmdRestart", 18, 18, &umr_bitfield_default },
+	 { "CFG_DPC_Enable", 20, 20, &umr_bitfield_default },
+	 { "CFG_DPC_FastCkStable", 21, 21, &umr_bitfield_default },
+	 { "CFG_DPC_spare", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DELAYLINE_STATUS[] = {
+	 { "DPC_CFG_controllerIdle", 0, 0, &umr_bitfield_default },
+	 { "DPC_CFG_commandComplete", 1, 1, &umr_bitfield_default },
+	 { "DPC_CFG_phaseLocked", 2, 2, &umr_bitfield_default },
+	 { "DPC_CFG_posAlignmentVld", 3, 3, &umr_bitfield_default },
+	 { "DPC_CFG_negAlignmentVld", 4, 4, &umr_bitfield_default },
+	 { "DPC_CFG_posDelayValue", 8, 15, &umr_bitfield_default },
+	 { "DPC_CFG_negDelayValue", 16, 23, &umr_bitfield_default },
+	 { "DPC_CFG_freqRatio", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DTM_RX_BP_CNTL[] = {
+	 { "rxElasBP_Cntl", 0, 7, &umr_bitfield_default },
+	 { "Dbg_Cntl", 16, 19, &umr_bitfield_default },
+	 { "rxElasBP_SlideValue", 20, 23, &umr_bitfield_default },
+	 { "td_hold_training_override", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DTM_CNTL[] = {
+	 { "Dtm_Dummy0", 0, 0, &umr_bitfield_default },
+	 { "Dtm_Dummy1", 1, 1, &umr_bitfield_default },
+	 { "Determinism_En_DTM", 2, 2, &umr_bitfield_default },
+	 { "Dtm_Dummy2", 3, 3, &umr_bitfield_default },
+	 { "Dtm_Dummy3", 4, 4, &umr_bitfield_default },
+	 { "Dtm_Dummy4", 5, 5, &umr_bitfield_default },
+	 { "Dtm_Dummy5", 6, 6, &umr_bitfield_default },
+	 { "Dtm_Dummy6", 7, 7, &umr_bitfield_default },
+	 { "TxClk1x_Cntl", 8, 9, &umr_bitfield_default },
+	 { "TxClkGskt_Cntl", 10, 11, &umr_bitfield_default },
+	 { "refClk_Cntl", 12, 13, &umr_bitfield_default },
+	 { "dtmClk_Sel_Timer", 14, 15, &umr_bitfield_default },
+	 { "Dtm_Dummy7", 16, 16, &umr_bitfield_default },
+	 { "Dtm_Dummy8", 17, 17, &umr_bitfield_default },
+	 { "Dtm_Dummy9", 18, 18, &umr_bitfield_default },
+	 { "Dtm_Dummy10", 19, 19, &umr_bitfield_default },
+	 { "Dtm_Dummy11", 20, 20, &umr_bitfield_default },
+	 { "Dtm_Dummy12", 21, 21, &umr_bitfield_default },
+	 { "rxElasWidth_Cntl", 22, 23, &umr_bitfield_default },
+	 { "Dtm_Dummy13", 24, 24, &umr_bitfield_default },
+	 { "Dtm_Dummy14", 25, 25, &umr_bitfield_default },
+	 { "Dtm_Dummy15", 26, 26, &umr_bitfield_default },
+	 { "Dtm_Dummy16", 27, 27, &umr_bitfield_default },
+	 { "Dtm_Dummy17", 28, 28, &umr_bitfield_default },
+	 { "Warm_RstTimer", 29, 30, &umr_bitfield_default },
+	 { "Dtm_Dummy18", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DTM_CNTL_LEGACY[] = {
+	 { "Dtm_Dummy19", 0, 0, &umr_bitfield_default },
+	 { "fifoInit_one_dropout", 1, 1, &umr_bitfield_default },
+	 { "Dtm_Clk_2sym", 2, 2, &umr_bitfield_default },
+	 { "Dtm_GsktClk_2sym", 3, 3, &umr_bitfield_default },
+	 { "Dtm_hardRst_slide", 4, 5, &umr_bitfield_default },
+	 { "Dtm_earlyRst_slide", 6, 7, &umr_bitfield_default },
+	 { "Dtm_txPhyStsOk_slide", 8, 9, &umr_bitfield_default },
+	 { "Dtm_Sti_TXCLK_Period", 12, 15, &umr_bitfield_default },
+	 { "Dtm_Sti_TXCLK_Send", 16, 19, &umr_bitfield_default },
+	 { "Dtm_Sti_TXCLK_Rcv", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DTM_STI_LCLK_CTRL[] = {
+	 { "Dtm_Sti_LCLK_Period", 0, 8, &umr_bitfield_default },
+	 { "Dtm_Sti_LCLK_Send", 9, 17, &umr_bitfield_default },
+	 { "Dtm_Sti_LCLK_Rcv", 18, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[] = {
+	 { "DentistGate_startTime_DI_clk10x", 0, 7, &umr_bitfield_default },
+	 { "DentistGate_dropoutTime_DI_clk10x", 8, 15, &umr_bitfield_default },
+	 { "DentistGate_stopTime_DI_clk10x", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[] = {
+	 { "DentistGate_startTime_DI_clkGskt", 0, 7, &umr_bitfield_default },
+	 { "DentistGate_dropoutTime_DI_clkGskt", 8, 15, &umr_bitfield_default },
+	 { "DentistGate_stopTime_DI_clkGskt", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[] = {
+	 { "DentistGate_startTime_FI_clk10x", 0, 7, &umr_bitfield_default },
+	 { "DentistGate_dropoutTime_FI_clk10x", 8, 15, &umr_bitfield_default },
+	 { "DentistGate_stopTime_FI_clk10x", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[] = {
+	 { "DentistGate_startTime_FI_clkGskt", 0, 7, &umr_bitfield_default },
+	 { "DentistGate_dropoutTime_FI_clkGskt", 8, 15, &umr_bitfield_default },
+	 { "DentistGate_stopTime_FI_clkGskt", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_CAP[] = {
+	 { "VERSION", 0, 2, &umr_bitfield_default },
+	 { "PME_CLOCK", 3, 3, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 5, 5, &umr_bitfield_default },
+	 { "AUX_CURRENT", 6, 8, &umr_bitfield_default },
+	 { "D1_SUPPORT", 9, 9, &umr_bitfield_default },
+	 { "D2_SUPPORT", 10, 10, &umr_bitfield_default },
+	 { "PME_SUPPORT", 11, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_RESERVED[] = {
+	 { "PCIE_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RESERVED[] = {
+	 { "PCIE_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_SCRATCH[] = {
+	 { "PCIE_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_SCRATCH[] = {
+	 { "PCIE_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_RX_NUM_NAK[] = {
+	 { "RX_NUM_NAK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_NUM_NAK[] = {
+	 { "RX_NUM_NAK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED[] = {
+	 { "RX_NUM_NAK_GENERATED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_NUM_NAK_GENERATED[] = {
+	 { "RX_NUM_NAK_GENERATED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_CNTL[] = {
+	 { "HWINIT_WR_LOCK", 0, 0, &umr_bitfield_default },
+	 { "LC_HOT_PLUG_DELAY_SEL", 1, 3, &umr_bitfield_default },
+	 { "UR_ERR_REPORT_DIS", 7, 7, &umr_bitfield_default },
+	 { "PCIE_MALFORM_ATOMIC_OPS", 8, 8, &umr_bitfield_default },
+	 { "PCIE_HT_NP_MEM_WRITE", 9, 9, &umr_bitfield_default },
+	 { "RX_SB_ADJ_PAYLOAD_SIZE", 10, 12, &umr_bitfield_default },
+	 { "RX_RCB_ATS_UC_DIS", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_REORDER_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_RCB_INVALID_SIZE_DIS", 17, 17, &umr_bitfield_default },
+	 { "RX_RCB_UNEXP_CPL_DIS", 18, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_TEST_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_PREFIX_DIS", 20, 20, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_ATTR_DIS", 21, 21, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_FUNCNUM_DIS", 22, 22, &umr_bitfield_default },
+	 { "RX_ATS_TRAN_CPL_SPLIT_DIS", 23, 23, &umr_bitfield_default },
+	 { "TX_CPL_DEBUG", 24, 29, &umr_bitfield_default },
+	 { "RX_IGNORE_LTR_MSG_UR", 30, 30, &umr_bitfield_default },
+	 { "RX_CPL_POSTED_REQ_ORD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CNTL[] = {
+	 { "HWINIT_WR_LOCK", 0, 0, &umr_bitfield_default },
+	 { "LC_HOT_PLUG_DELAY_SEL", 1, 3, &umr_bitfield_default },
+	 { "UR_ERR_REPORT_DIS", 7, 7, &umr_bitfield_default },
+	 { "PCIE_MALFORM_ATOMIC_OPS", 8, 8, &umr_bitfield_default },
+	 { "PCIE_HT_NP_MEM_WRITE", 9, 9, &umr_bitfield_default },
+	 { "RX_SB_ADJ_PAYLOAD_SIZE", 10, 12, &umr_bitfield_default },
+	 { "RX_RCB_ATS_UC_DIS", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_REORDER_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_RCB_INVALID_SIZE_DIS", 17, 17, &umr_bitfield_default },
+	 { "RX_RCB_UNEXP_CPL_DIS", 18, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_TEST_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_RCB_CHANNEL_ORDERING", 20, 20, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_ATTR_DIS", 21, 21, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_FUNCNUM_DIS", 22, 22, &umr_bitfield_default },
+	 { "RX_ATS_TRAN_CPL_SPLIT_DIS", 23, 23, &umr_bitfield_default },
+	 { "TX_CPL_DEBUG", 24, 29, &umr_bitfield_default },
+	 { "RX_IGNORE_LTR_MSG_UR", 30, 30, &umr_bitfield_default },
+	 { "RX_CPL_POSTED_REQ_ORD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_CONFIG_CNTL[] = {
+	 { "DYN_CLK_LATENCY", 0, 3, &umr_bitfield_default },
+	 { "CI_MAX_PAYLOAD_SIZE_MODE", 16, 16, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_PAYLOAD_SIZE", 17, 19, &umr_bitfield_default },
+	 { "CI_MAX_READ_REQUEST_SIZE_MODE", 20, 20, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_READ_REQUEST_SIZE", 21, 23, &umr_bitfield_default },
+	 { "CI_MAX_READ_SAFE_MODE", 24, 24, &umr_bitfield_default },
+	 { "CI_EXTENDED_TAG_EN_OVERRIDE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CONFIG_CNTL[] = {
+	 { "DYN_CLK_LATENCY", 0, 3, &umr_bitfield_default },
+	 { "CI_MAX_PAYLOAD_SIZE_MODE", 16, 16, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_PAYLOAD_SIZE", 17, 19, &umr_bitfield_default },
+	 { "CI_MAX_READ_REQUEST_SIZE_MODE", 20, 20, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_READ_REQUEST_SIZE", 21, 23, &umr_bitfield_default },
+	 { "CI_MAX_READ_SAFE_MODE", 24, 24, &umr_bitfield_default },
+	 { "CI_EXTENDED_TAG_EN_OVERRIDE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_DEBUG_CNTL[] = {
+	 { "DEBUG_PORT_EN", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_SELECT", 8, 8, &umr_bitfield_default },
+	 { "DEBUG_LANE_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_DEBUG_CNTL[] = {
+	 { "DEBUG_PORT_EN", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_SELECT", 8, 8, &umr_bitfield_default },
+	 { "DEBUG_LANE_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_INT_CNTL[] = {
+	 { "CORR_ERR_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_INT_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED_INT_EN", 3, 3, &umr_bitfield_default },
+	 { "MISC_ERR_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "POWER_STATE_CHG_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "LINK_BW_INT_EN", 7, 7, &umr_bitfield_default },
+	 { "QUIESCE_RCVD_INT_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_INT_STATUS[] = {
+	 { "CORR_ERR_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED_INT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "MISC_ERR_INT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "POWER_STATE_CHG_INT_STATUS", 6, 6, &umr_bitfield_default },
+	 { "LINK_BW_INT_STATUS", 7, 7, &umr_bitfield_default },
+	 { "QUIESCE_RCVD_INT_STATUS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_CNTL2[] = {
+	 { "TX_ARB_ROUND_ROBIN_EN", 0, 0, &umr_bitfield_default },
+	 { "TX_ARB_SLV_LIMIT", 1, 5, &umr_bitfield_default },
+	 { "TX_ARB_MST_LIMIT", 6, 10, &umr_bitfield_default },
+	 { "TX_BLOCK_TLP_ON_PM_DIS", 11, 11, &umr_bitfield_default },
+	 { "TX_NP_MEM_WRITE_SWP_ENCODING", 12, 12, &umr_bitfield_default },
+	 { "TX_ATOMIC_OPS_DISABLE", 13, 13, &umr_bitfield_default },
+	 { "TX_ATOMIC_ORDERING_DIS", 14, 14, &umr_bitfield_default },
+	 { "SLV_MEM_LS_EN", 16, 16, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_LS_EN", 17, 17, &umr_bitfield_default },
+	 { "MST_MEM_LS_EN", 18, 18, &umr_bitfield_default },
+	 { "REPLAY_MEM_LS_EN", 19, 19, &umr_bitfield_default },
+	 { "SLV_MEM_SD_EN", 20, 20, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_SD_EN", 21, 21, &umr_bitfield_default },
+	 { "MST_MEM_SD_EN", 22, 22, &umr_bitfield_default },
+	 { "REPLAY_MEM_SD_EN", 23, 23, &umr_bitfield_default },
+	 { "RX_NP_MEM_WRITE_ENCODING", 24, 28, &umr_bitfield_default },
+	 { "SLV_MEM_DS_EN", 29, 29, &umr_bitfield_default },
+	 { "MST_MEM_DS_EN", 30, 30, &umr_bitfield_default },
+	 { "REPLAY_MEM_DS_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CNTL2[] = {
+	 { "TX_ARB_ROUND_ROBIN_EN", 0, 0, &umr_bitfield_default },
+	 { "TX_ARB_SLV_LIMIT", 1, 5, &umr_bitfield_default },
+	 { "TX_ARB_MST_LIMIT", 6, 10, &umr_bitfield_default },
+	 { "TX_BLOCK_TLP_ON_PM_DIS", 11, 11, &umr_bitfield_default },
+	 { "SLV_MEM_LS_EN", 16, 16, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_LS_EN", 17, 17, &umr_bitfield_default },
+	 { "MST_MEM_LS_EN", 18, 18, &umr_bitfield_default },
+	 { "REPLAY_MEM_LS_EN", 19, 19, &umr_bitfield_default },
+	 { "SLV_MEM_SD_EN", 20, 20, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_SD_EN", 21, 21, &umr_bitfield_default },
+	 { "MST_MEM_SD_EN", 22, 22, &umr_bitfield_default },
+	 { "REPLAY_MEM_SD_EN", 23, 23, &umr_bitfield_default },
+	 { "RX_NP_MEM_WRITE_ENCODING", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_RX_CNTL2[] = {
+	 { "RX_IGNORE_EP_INVALIDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMRD_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMWR_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ATSTRANSREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_PAGEREQMSG_UR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_INVCPL_UR", 5, 5, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_SCALE", 9, 11, &umr_bitfield_default },
+	 { "SLVCPL_MEM_LS_EN", 12, 12, &umr_bitfield_default },
+	 { "SLVCPL_MEM_SD_EN", 13, 13, &umr_bitfield_default },
+	 { "SLVCPL_MEM_DS_EN", 14, 14, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_MAX_COUNT", 16, 25, &umr_bitfield_default },
+	 { "FLR_EXTEND_MODE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_CNTL2[] = {
+	 { "RX_IGNORE_EP_INVALIDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMRD_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMWR_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ATSTRANSREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_PAGEREQMSG_UR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_INVCPL_UR", 5, 5, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_SCALE", 9, 11, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_MAX_COUNT", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL[] = {
+	 { "TX_F0_IDO_OVERRIDE_P", 0, 1, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_NP", 2, 3, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_CPL", 4, 5, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_P", 6, 7, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_NP", 8, 9, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_P", 10, 11, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_NP", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_F0_ATTR_CNTL[] = {
+	 { "TX_F0_IDO_OVERRIDE_P", 0, 1, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_NP", 2, 3, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_CPL", 4, 5, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_P", 6, 7, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_NP", 8, 9, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_P", 10, 11, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_NP", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_F1_F2_ATTR_CNTL[] = {
+	 { "TX_F1_IDO_OVERRIDE_P", 0, 1, &umr_bitfield_default },
+	 { "TX_F1_IDO_OVERRIDE_NP", 2, 3, &umr_bitfield_default },
+	 { "TX_F1_IDO_OVERRIDE_CPL", 4, 5, &umr_bitfield_default },
+	 { "TX_F1_RO_OVERRIDE_P", 6, 7, &umr_bitfield_default },
+	 { "TX_F1_RO_OVERRIDE_NP", 8, 9, &umr_bitfield_default },
+	 { "TX_F1_SNR_OVERRIDE_P", 10, 11, &umr_bitfield_default },
+	 { "TX_F1_SNR_OVERRIDE_NP", 12, 13, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_P", 16, 17, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_NP", 18, 19, &umr_bitfield_default },
+	 { "TX_F2_IDO_OVERRIDE_CPL", 20, 21, &umr_bitfield_default },
+	 { "TX_F2_RO_OVERRIDE_P", 22, 23, &umr_bitfield_default },
+	 { "TX_F2_RO_OVERRIDE_NP", 24, 25, &umr_bitfield_default },
+	 { "TX_F2_SNR_OVERRIDE_P", 26, 27, &umr_bitfield_default },
+	 { "TX_F2_SNR_OVERRIDE_NP", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_CI_CNTL[] = {
+	 { "CI_SLAVE_SPLIT_MODE", 2, 2, &umr_bitfield_default },
+	 { "CI_SLAVE_GEN_USR_DIS", 3, 3, &umr_bitfield_default },
+	 { "CI_MST_CMPL_DUMMY_DATA", 4, 4, &umr_bitfield_default },
+	 { "CI_SLV_RC_RD_REQ_SIZE", 6, 7, &umr_bitfield_default },
+	 { "CI_SLV_ORDERING_DIS", 8, 8, &umr_bitfield_default },
+	 { "CI_RC_ORDERING_DIS", 9, 9, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_DIS", 10, 10, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_MODE", 11, 11, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_SOR", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CI_CNTL[] = {
+	 { "CI_SLAVE_SPLIT_MODE", 2, 2, &umr_bitfield_default },
+	 { "CI_SLAVE_GEN_USR_DIS", 3, 3, &umr_bitfield_default },
+	 { "CI_MST_CMPL_DUMMY_DATA", 4, 4, &umr_bitfield_default },
+	 { "CI_SLV_RC_RD_REQ_SIZE", 6, 7, &umr_bitfield_default },
+	 { "CI_SLV_ORDERING_DIS", 8, 8, &umr_bitfield_default },
+	 { "CI_RC_ORDERING_DIS", 9, 9, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_DIS", 10, 10, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_MODE", 11, 11, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_SOR", 12, 12, &umr_bitfield_default },
+	 { "CI_MST_IGNORE_PAGE_ALIGNED_REQUEST", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_BUS_CNTL[] = {
+	 { "PMI_INT_DIS", 6, 6, &umr_bitfield_default },
+	 { "IMMEDIATE_PMI_DIS", 7, 7, &umr_bitfield_default },
+	 { "TRUE_PM_STATUS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_BUS_CNTL[] = {
+	 { "PMI_INT_DIS", 6, 6, &umr_bitfield_default },
+	 { "IMMEDIATE_PMI_DIS", 7, 7, &umr_bitfield_default },
+	 { "TRUE_PM_STATUS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_STATE6[] = {
+	 { "LC_PREV_STATE24", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE25", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE26", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE27", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE6[] = {
+	 { "LC_PREV_STATE24", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE25", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE26", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE27", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_STATE7[] = {
+	 { "LC_PREV_STATE28", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE29", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE30", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE31", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE7[] = {
+	 { "LC_PREV_STATE28", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE29", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE30", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE31", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_STATE8[] = {
+	 { "LC_PREV_STATE32", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE33", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE34", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE35", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE8[] = {
+	 { "LC_PREV_STATE32", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE33", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE34", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE35", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_STATE9[] = {
+	 { "LC_PREV_STATE36", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE37", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE38", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE39", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE9[] = {
+	 { "LC_PREV_STATE36", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE37", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE38", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE39", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_STATE10[] = {
+	 { "LC_PREV_STATE40", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE41", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE42", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE43", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE10[] = {
+	 { "LC_PREV_STATE40", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE41", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE42", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE43", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_STATE11[] = {
+	 { "LC_PREV_STATE44", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE45", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE46", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE47", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATE11[] = {
+	 { "LC_PREV_STATE44", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE45", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE46", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE47", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_STATUS1[] = {
+	 { "LC_REVERSE_RCVR", 0, 0, &umr_bitfield_default },
+	 { "LC_REVERSE_XMIT", 1, 1, &umr_bitfield_default },
+	 { "LC_OPERATING_LINK_WIDTH", 2, 4, &umr_bitfield_default },
+	 { "LC_DETECTED_LINK_WIDTH", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATUS1[] = {
+	 { "LC_REVERSE_RCVR", 0, 0, &umr_bitfield_default },
+	 { "LC_REVERSE_XMIT", 1, 1, &umr_bitfield_default },
+	 { "LC_OPERATING_LINK_WIDTH", 2, 4, &umr_bitfield_default },
+	 { "LC_DETECTED_LINK_WIDTH", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_STATUS2[] = {
+	 { "LC_TOTAL_INACTIVE_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_TURN_ON_LANE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_LC_STATUS2[] = {
+	 { "LC_TOTAL_INACTIVE_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_TURN_ON_LANE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_WPR_CNTL[] = {
+	 { "WPR_RESET_HOT_RST_EN", 0, 0, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DWN_EN", 1, 1, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DIS_EN", 2, 2, &umr_bitfield_default },
+	 { "WPR_RESET_COR_EN", 3, 3, &umr_bitfield_default },
+	 { "WPR_RESET_REG_EN", 4, 4, &umr_bitfield_default },
+	 { "WPR_RESET_STY_EN", 5, 5, &umr_bitfield_default },
+	 { "WPR_RESET_PHY_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_WPR_CNTL[] = {
+	 { "WPR_RESET_HOT_RST_EN", 0, 0, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DWN_EN", 1, 1, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DIS_EN", 2, 2, &umr_bitfield_default },
+	 { "WPR_RESET_COR_EN", 3, 3, &umr_bitfield_default },
+	 { "WPR_RESET_REG_EN", 4, 4, &umr_bitfield_default },
+	 { "WPR_RESET_STY_EN", 5, 5, &umr_bitfield_default },
+	 { "WPR_RESET_PHY_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_RX_LAST_TLP0[] = {
+	 { "RX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP0[] = {
+	 { "RX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_RX_LAST_TLP1[] = {
+	 { "RX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP1[] = {
+	 { "RX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_RX_LAST_TLP2[] = {
+	 { "RX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP2[] = {
+	 { "RX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_RX_LAST_TLP3[] = {
+	 { "RX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_RX_LAST_TLP3[] = {
+	 { "RX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_TX_LAST_TLP0[] = {
+	 { "TX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP0[] = {
+	 { "TX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_TX_LAST_TLP1[] = {
+	 { "TX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP1[] = {
+	 { "TX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_TX_LAST_TLP2[] = {
+	 { "TX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP2[] = {
+	 { "TX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_TX_LAST_TLP3[] = {
+	 { "TX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LAST_TLP3[] = {
+	 { "TX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND[] = {
+	 { "I2C_REG_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_I2C_REG_ADDR_EXPAND[] = {
+	 { "I2C_REG_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_I2C_REG_DATA[] = {
+	 { "I2C_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_I2C_REG_DATA[] = {
+	 { "I2C_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_CFG_CNTL[] = {
+	 { "CFG_EN_DEC_TO_HIDDEN_REG", 0, 0, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG", 1, 1, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_CFG_CNTL[] = {
+	 { "CFG_EN_DEC_TO_HIDDEN_REG", 0, 0, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG", 1, 1, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_LC_PM_CNTL[] = {
+	 { "LC_L1_POWER_GATING_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_P_CNTL[] = {
+	 { "P_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "P_SYMALIGN_MODE", 1, 1, &umr_bitfield_default },
+	 { "P_SYMALIGN_HW_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "P_ELASTDESKEW_HW_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "P_IGNORE_CRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "P_IGNORE_LEN_ERR", 5, 5, &umr_bitfield_default },
+	 { "P_IGNORE_EDB_ERR", 6, 6, &umr_bitfield_default },
+	 { "P_IGNORE_IDL_ERR", 7, 7, &umr_bitfield_default },
+	 { "P_IGNORE_TOK_ERR", 8, 8, &umr_bitfield_default },
+	 { "P_BLK_LOCK_MODE", 12, 12, &umr_bitfield_default },
+	 { "P_ALWAYS_USE_FAST_TXCLK", 13, 13, &umr_bitfield_default },
+	 { "P_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "DLP_IGNORE_IN_L1_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_CNTL[] = {
+	 { "P_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "P_SYMALIGN_MODE", 1, 1, &umr_bitfield_default },
+	 { "P_SYMALIGN_HW_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "P_ELASTDESKEW_HW_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "P_IGNORE_CRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "P_IGNORE_LEN_ERR", 5, 5, &umr_bitfield_default },
+	 { "P_IGNORE_EDB_ERR", 6, 6, &umr_bitfield_default },
+	 { "P_IGNORE_IDL_ERR", 7, 7, &umr_bitfield_default },
+	 { "P_IGNORE_TOK_ERR", 8, 8, &umr_bitfield_default },
+	 { "P_BLK_LOCK_MODE", 12, 12, &umr_bitfield_default },
+	 { "P_ALWAYS_USE_FAST_TXCLK", 13, 13, &umr_bitfield_default },
+	 { "P_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "DLP_IGNORE_IN_L1_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_P_BUF_STATUS[] = {
+	 { "P_OVERFLOW_ERR", 0, 15, &umr_bitfield_default },
+	 { "P_UNDERFLOW_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_BUF_STATUS[] = {
+	 { "P_OVERFLOW_ERR", 0, 15, &umr_bitfield_default },
+	 { "P_UNDERFLOW_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_P_DECODER_STATUS[] = {
+	 { "P_DECODE_ERR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_DECODER_STATUS[] = {
+	 { "P_DECODE_ERR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_P_MISC_STATUS[] = {
+	 { "P_DESKEW_ERR", 0, 7, &umr_bitfield_default },
+	 { "P_SYMUNLOCK_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_MISC_STATUS[] = {
+	 { "P_DESKEW_ERR", 0, 7, &umr_bitfield_default },
+	 { "P_SYMUNLOCK_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET[] = {
+	 { "P_RCV_L0S_FTS_DET_MIN", 0, 7, &umr_bitfield_default },
+	 { "P_RCV_L0S_FTS_DET_MAX", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_P_RCV_L0S_FTS_DET[] = {
+	 { "P_RCV_L0S_FTS_DET_MIN", 0, 7, &umr_bitfield_default },
+	 { "P_RCV_L0S_FTS_DET_MAX", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_TX_LTR_CNTL[] = {
+	 { "LTR_PRIV_S_SHORT_VALUE", 0, 2, &umr_bitfield_default },
+	 { "LTR_PRIV_S_LONG_VALUE", 3, 5, &umr_bitfield_default },
+	 { "LTR_PRIV_S_REQUIREMENT", 6, 6, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_SHORT_VALUE", 7, 9, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_LONG_VALUE", 10, 12, &umr_bitfield_default },
+	 { "LTR_PRIV_NS_REQUIREMENT", 13, 13, &umr_bitfield_default },
+	 { "LTR_PRIV_MSG_DIS_IN_PM_NON_D0", 14, 14, &umr_bitfield_default },
+	 { "LTR_PRIV_RST_LTR_IN_DL_DOWN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_OBFF_CNTL[] = {
+	 { "TX_OBFF_PRIV_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_SIMPLE_MODE_EN", 1, 1, &umr_bitfield_default },
+	 { "TX_OBFF_HOSTMEM_TO_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "TX_OBFF_SLVCPL_TO_ACTIVE", 3, 3, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_MAX_PULSE_WIDTH", 4, 7, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH", 8, 11, &umr_bitfield_default },
+	 { "TX_OBFF_WAKE_SAMPLING_PERIOD", 12, 15, &umr_bitfield_default },
+	 { "TX_OBFF_INTR_TO_ACTIVE", 16, 16, &umr_bitfield_default },
+	 { "TX_OBFF_ERR_TO_ACTIVE", 17, 17, &umr_bitfield_default },
+	 { "TX_OBFF_ANY_MSG_TO_ACTIVE", 18, 18, &umr_bitfield_default },
+	 { "TX_OBFF_PENDING_REQ_TO_ACTIVE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT_CNTL[] = {
+	 { "GLOBAL_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GLOBAL_SHADOW_WR", 1, 1, &umr_bitfield_default },
+	 { "GLOBAL_COUNT_RESET", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT_CNTL[] = {
+	 { "GLOBAL_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GLOBAL_SHADOW_WR", 1, 1, &umr_bitfield_default },
+	 { "GLOBAL_COUNT_RESET", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_TXCLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_TXCLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_TXCLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_MST_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_MST_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_MST_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_MST_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_MST_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_MST_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_S_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_S_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_S_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_SLV_NS_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[] = {
+	 { "PERF0_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[] = {
+	 { "PERF0_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[] = {
+	 { "PERF1_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[] = {
+	 { "PERF1_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_CNTL_TXCLK2[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT0_TXCLK2[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PERF_COUNT1_TXCLK2[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_STRAP_F0[] = {
+	 { "STRAP_F0_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F0_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F0_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F0_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F0_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F0_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F0_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F0_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F0_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F0_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F0_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F0_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F0_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F0_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+	 { "STRAP_F0_MC_EN", 17, 17, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_EN", 18, 18, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_64BIT_EN", 19, 19, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_ROUTING_EN", 20, 20, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_MULTI_CAP", 21, 23, &umr_bitfield_default },
+	 { "STRAP_F0_VFn_MSI_MULTI_CAP", 24, 26, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_PERVECTOR_MASK_CAP", 27, 27, &umr_bitfield_default },
+	 { "STRAP_F0_NO_RO_ENABLED_P2P_PASSING", 28, 28, &umr_bitfield_default },
+	 { "STRAP_F0_ARI_EN", 29, 29, &umr_bitfield_default },
+	 { "STRAP_F0_SRIOV_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F0[] = {
+	 { "STRAP_F0_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F0_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F0_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F0_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F0_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F0_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F0_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F0_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F0_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F0_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F0_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F0_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F0_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F0_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+	 { "STRAP_F0_MC_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F1[] = {
+	 { "STRAP_F1_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F1_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F1_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F1_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F1_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F1_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F1_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F1_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F1_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F1_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F1_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F1_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F1_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F1_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F1_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F1_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F1_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F2[] = {
+	 { "STRAP_F2_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F2_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F2_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F2_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F2_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F2_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F2_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F2_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F2_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F2_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F2_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F2_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F2_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F2_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F2_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F2_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F2_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_F7[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_STRAP_MISC[] = {
+	 { "STRAP_TL_ALT_BUF_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_CLK_PM_EN", 24, 24, &umr_bitfield_default },
+	 { "STRAP_ECN1P1_EN", 25, 25, &umr_bitfield_default },
+	 { "STRAP_EXT_VC_COUNT", 26, 26, &umr_bitfield_default },
+	 { "STRAP_REVERSE_ALL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_MST_ADR64_EN", 29, 29, &umr_bitfield_default },
+	 { "STRAP_FLR_EN", 30, 30, &umr_bitfield_default },
+	 { "STRAP_INTERNAL_ERR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_MISC[] = {
+	 { "STRAP_LINK_CONFIG", 0, 3, &umr_bitfield_default },
+	 { "STRAP_TL_ALT_BUF_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_MAX_PASID_WIDTH", 8, 12, &umr_bitfield_default },
+	 { "STRAP_PASID_EXE_PERMISSION_SUPPORTED", 13, 13, &umr_bitfield_default },
+	 { "STRAP_PASID_PRIV_MODE_SUPPORTED", 14, 14, &umr_bitfield_default },
+	 { "STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED", 15, 15, &umr_bitfield_default },
+	 { "STRAP_CLK_PM_EN", 24, 24, &umr_bitfield_default },
+	 { "STRAP_ECN1P1_EN", 25, 25, &umr_bitfield_default },
+	 { "STRAP_EXT_VC_COUNT", 26, 26, &umr_bitfield_default },
+	 { "STRAP_REVERSE_ALL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_MST_ADR64_EN", 29, 29, &umr_bitfield_default },
+	 { "STRAP_FLR_EN", 30, 30, &umr_bitfield_default },
+	 { "STRAP_INTERNAL_ERR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_STRAP_MISC2[] = {
+	 { "STRAP_LINK_BW_NOTIFICATION_CAP_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_GEN2_COMPLIANCE", 1, 1, &umr_bitfield_default },
+	 { "STRAP_MSTCPL_TIMEOUT_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_GEN3_COMPLIANCE", 3, 3, &umr_bitfield_default },
+	 { "STRAP_TPH_SUPPORTED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_MISC2[] = {
+	 { "STRAP_GEN2_COMPLIANCE", 1, 1, &umr_bitfield_default },
+	 { "STRAP_MSTCPL_TIMEOUT_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_GEN3_COMPLIANCE", 3, 3, &umr_bitfield_default },
+	 { "STRAP_TPH_SUPPORTED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_STRAP_PI[] = {
+	 { "STRAP_QUICKSIM_START", 0, 0, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_PATTERN", 28, 28, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_MODE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_PI[] = {
+	 { "STRAP_QUICKSIM_START", 0, 0, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_PATTERN", 28, 28, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_MODE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_STRAP_I2C_BD[] = {
+	 { "STRAP_BIF_I2C_SLV_ADR", 0, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_DBG_I2C_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_STRAP_I2C_BD[] = {
+	 { "STRAP_BIF_I2C_SLV_ADR", 0, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_DBG_I2C_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_CLR[] = {
+	 { "PRBS_CLR", 0, 15, &umr_bitfield_default },
+	 { "PRBS_CHECKER_DEBUG_BUS_SELECT", 16, 19, &umr_bitfield_default },
+	 { "PRBS_POLARITY_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_CLR[] = {
+	 { "PRBS_CLR", 0, 15, &umr_bitfield_default },
+	 { "PRBS_CHECKER_DEBUG_BUS_SELECT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_STATUS1[] = {
+	 { "PRBS_ERRSTAT", 0, 15, &umr_bitfield_default },
+	 { "PRBS_LOCKED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_STATUS1[] = {
+	 { "PRBS_ERRSTAT", 0, 15, &umr_bitfield_default },
+	 { "PRBS_LOCKED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_STATUS2[] = {
+	 { "PRBS_BITCNT_DONE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_STATUS2[] = {
+	 { "PRBS_BITCNT_DONE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_FREERUN[] = {
+	 { "PRBS_FREERUN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_FREERUN[] = {
+	 { "PRBS_FREERUN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_MISC[] = {
+	 { "PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "PRBS_TEST_MODE", 1, 3, &umr_bitfield_default },
+	 { "PRBS_USER_PATTERN_TOGGLE", 4, 4, &umr_bitfield_default },
+	 { "PRBS_8BIT_SEL", 5, 5, &umr_bitfield_default },
+	 { "PRBS_COMMA_NUM", 6, 7, &umr_bitfield_default },
+	 { "PRBS_LOCK_CNT", 8, 12, &umr_bitfield_default },
+	 { "PRBS_DATA_RATE", 14, 15, &umr_bitfield_default },
+	 { "PRBS_CHK_ERR_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_MISC[] = {
+	 { "PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "PRBS_TEST_MODE", 1, 2, &umr_bitfield_default },
+	 { "PRBS_USER_PATTERN_TOGGLE", 3, 3, &umr_bitfield_default },
+	 { "PRBS_8BIT_SEL", 4, 4, &umr_bitfield_default },
+	 { "PRBS_COMMA_NUM", 5, 6, &umr_bitfield_default },
+	 { "PRBS_LOCK_CNT", 7, 11, &umr_bitfield_default },
+	 { "PRBS_DATA_RATE", 14, 15, &umr_bitfield_default },
+	 { "PRBS_CHK_ERR_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_USER_PATTERN[] = {
+	 { "PRBS_USER_PATTERN", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_USER_PATTERN[] = {
+	 { "PRBS_USER_PATTERN", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_LO_BITCNT[] = {
+	 { "PRBS_LO_BITCNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_LO_BITCNT[] = {
+	 { "PRBS_LO_BITCNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_HI_BITCNT[] = {
+	 { "PRBS_HI_BITCNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_HI_BITCNT[] = {
+	 { "PRBS_HI_BITCNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_0[] = {
+	 { "PRBS_ERRCNT_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_0[] = {
+	 { "PRBS_ERRCNT_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_1[] = {
+	 { "PRBS_ERRCNT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_1[] = {
+	 { "PRBS_ERRCNT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_2[] = {
+	 { "PRBS_ERRCNT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_2[] = {
+	 { "PRBS_ERRCNT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_3[] = {
+	 { "PRBS_ERRCNT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_3[] = {
+	 { "PRBS_ERRCNT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_4[] = {
+	 { "PRBS_ERRCNT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_4[] = {
+	 { "PRBS_ERRCNT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_5[] = {
+	 { "PRBS_ERRCNT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_5[] = {
+	 { "PRBS_ERRCNT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_6[] = {
+	 { "PRBS_ERRCNT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_6[] = {
+	 { "PRBS_ERRCNT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_7[] = {
+	 { "PRBS_ERRCNT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_7[] = {
+	 { "PRBS_ERRCNT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_8[] = {
+	 { "PRBS_ERRCNT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_8[] = {
+	 { "PRBS_ERRCNT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_9[] = {
+	 { "PRBS_ERRCNT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_9[] = {
+	 { "PRBS_ERRCNT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_10[] = {
+	 { "PRBS_ERRCNT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_10[] = {
+	 { "PRBS_ERRCNT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_11[] = {
+	 { "PRBS_ERRCNT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_11[] = {
+	 { "PRBS_ERRCNT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_12[] = {
+	 { "PRBS_ERRCNT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_12[] = {
+	 { "PRBS_ERRCNT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_13[] = {
+	 { "PRBS_ERRCNT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_13[] = {
+	 { "PRBS_ERRCNT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_14[] = {
+	 { "PRBS_ERRCNT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_14[] = {
+	 { "PRBS_ERRCNT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_PCIE_PRBS_ERRCNT_15[] = {
+	 { "PRBS_ERRCNT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PRBS_ERRCNT_15[] = {
+	 { "PRBS_ERRCNT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_CAP[] = {
+	 { "TRANS_LAT_UNIT", 8, 9, &umr_bitfield_default },
+	 { "PWR_ALLOC_SCALE", 12, 13, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_0", 16, 23, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_LATENCY_INDICATOR[] = {
+	 { "TRANS_LAT_INDICATOR_BITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_CNTL[] = {
+	 { "SUBSTATE_STATUS", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_COMMAND_STATUS[] = {
+	 { "RECONFIGURE", 0, 0, &umr_bitfield_default },
+	 { "ATOMIC_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESET_COMPLETE", 16, 16, &umr_bitfield_default },
+	 { "WAIT_STATE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_GENERAL_CONTROL[] = {
+	 { "RECONFIGURE_EN", 0, 0, &umr_bitfield_default },
+	 { "ATOMIC_RESET_EN", 1, 1, &umr_bitfield_default },
+	 { "RESET_PERIOD", 2, 4, &umr_bitfield_default },
+	 { "WAIT_LINKUP", 8, 8, &umr_bitfield_default },
+	 { "FORCE_REGIDLE", 9, 9, &umr_bitfield_default },
+	 { "BLOCK_ON_IDLE", 10, 10, &umr_bitfield_default },
+	 { "CONFIG_XFER_MODE", 12, 12, &umr_bitfield_default },
+	 { "MUXSEL_XFER_MODE", 13, 13, &umr_bitfield_default },
+	 { "HLDTRAIN_XFER_MODE", 14, 14, &umr_bitfield_default },
+	 { "BYPASS_HOLD", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_PIF_HOLD", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_COMMAND_0[] = {
+	 { "BIF_STRAPREG_RESET", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESET", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESET", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESET", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESET", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESET", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESET", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESET", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_COMMAND_1[] = {
+	 { "SWITCHCLK", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1", 5, 5, &umr_bitfield_default },
+	 { "RESETLC", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1", 25, 25, &umr_bitfield_default },
+	 { "TOGGLESTRAP", 28, 28, &umr_bitfield_default },
+	 { "CMDCFGEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_CONTROL_0[] = {
+	 { "BIF_STRAPREG_RESETRCEN", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESETRCEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESETRCEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESETRCEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESETRCEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESETRCEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESETRCEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESETRCEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_CONTROL_1[] = {
+	 { "SWITCHCLK_RCEN", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG_RCEN", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX_RCEN", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS_RCEN", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0_RCEN", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1_RCEN", 5, 5, &umr_bitfield_default },
+	 { "RESETLC_RCEN", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0_RCEN", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1_RCEN", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR_RCEN", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR_RCEN", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM_RCEN", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0_RCEN", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1_RCEN", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0_RCEN", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1_RCEN", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0_RCEN", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1_RCEN", 25, 25, &umr_bitfield_default },
+	 { "STRAPVLD_RCEN", 28, 28, &umr_bitfield_default },
+	 { "CMDCFG_RCEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_CONTROL_2[] = {
+	 { "BIF_STRAPREG_RESETATEN", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESETATEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESETATEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESETATEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESETATEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESETATEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESETATEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESETATEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_CONTROL_3[] = {
+	 { "SWITCHCLK_ATEN", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG_ATEN", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX_ATEN", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS_ATEN", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0_ATEN", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1_ATEN", 5, 5, &umr_bitfield_default },
+	 { "RESETLC_ATEN", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0_ATEN", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1_ATEN", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR_ATEN", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR_ATEN", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM_ATEN", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0_ATEN", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1_ATEN", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0_ATEN", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1_ATEN", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0_ATEN", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1_ATEN", 25, 25, &umr_bitfield_default },
+	 { "STRAPVLD_ATEN", 28, 28, &umr_bitfield_default },
+	 { "CMDCFG_ATEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_CONTROL_4[] = {
+	 { "BIF_STRAPREG_WRRESETEN", 14, 14, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_WRRESETEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_WRRESETEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_WRRESETEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_WRRESETEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_WRRESETEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_WRRESETEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_WRRESETEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_CONTROL_5[] = {
+	 { "WRSWITCHCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "WRRESETPCFG_EN", 1, 1, &umr_bitfield_default },
+	 { "WRRESETLANEMUX_EN", 2, 2, &umr_bitfield_default },
+	 { "WRRESETWRAPREGS_EN", 3, 3, &umr_bitfield_default },
+	 { "WRRESETSRBM0_EN", 4, 4, &umr_bitfield_default },
+	 { "WRRESETSRBM1_EN", 5, 5, &umr_bitfield_default },
+	 { "WRRESETLC_EN", 6, 6, &umr_bitfield_default },
+	 { "WRSYNCIDLEPIF0_EN", 8, 8, &umr_bitfield_default },
+	 { "WRSYNCIDLEPIF1_EN", 9, 9, &umr_bitfield_default },
+	 { "WRRESETMNTR_EN", 13, 13, &umr_bitfield_default },
+	 { "WRRESETHLTR_EN", 14, 14, &umr_bitfield_default },
+	 { "WRRESETCPM_EN", 15, 15, &umr_bitfield_default },
+	 { "WRRESETPIF0_EN", 16, 16, &umr_bitfield_default },
+	 { "WRRESETPIF1_EN", 17, 17, &umr_bitfield_default },
+	 { "WRRESETIMPARB0_EN", 20, 20, &umr_bitfield_default },
+	 { "WRRESETIMPARB1_EN", 21, 21, &umr_bitfield_default },
+	 { "WRRESETPHY0_EN", 24, 24, &umr_bitfield_default },
+	 { "WRRESETPHY1_EN", 25, 25, &umr_bitfield_default },
+	 { "WRSTRAPVLD_EN", 28, 28, &umr_bitfield_default },
+	 { "WRCMDCFG_EN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_SWRST_CONTROL_6[] = {
+	 { "WARMRESET_EN", 0, 0, &umr_bitfield_default },
+	 { "CONNECTWITHWRAPREGS_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_CPM_CONTROL[] = {
+	 { "LCLK_DYN_GATE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TXCLK_DYN_GATE_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "TXCLK_PIF_GATE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "TXCLK_GSKT_GATE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "TXCLK_LCNT_GATE_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "TXCLK_REGS_GATE_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "TXCLK_PRBS_GATE_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "REFCLK_REGS_GATE_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "LCLK_DYN_GATE_LATENCY", 9, 9, &umr_bitfield_default },
+	 { "TXCLK_DYN_GATE_LATENCY", 10, 10, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_LATENCY", 11, 11, &umr_bitfield_default },
+	 { "TXCLK_REGS_GATE_LATENCY", 12, 12, &umr_bitfield_default },
+	 { "REFCLK_REGS_GATE_LATENCY", 13, 13, &umr_bitfield_default },
+	 { "LCLK_GATE_TXCLK_FREE", 14, 14, &umr_bitfield_default },
+	 { "RCVR_DET_CLK_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_PLL_PDN", 16, 16, &umr_bitfield_default },
+	 { "FAST_TXCLK_LATENCY", 17, 19, &umr_bitfield_default },
+	 { "MASTER_PCIE_PLL_SELECT", 20, 20, &umr_bitfield_default },
+	 { "MASTER_PCIE_PLL_AUTO", 21, 21, &umr_bitfield_default },
+	 { "REFCLK_XSTCLK_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "REFCLK_XSTCLK_LATENCY", 23, 23, &umr_bitfield_default },
+	 { "SPARE_REGS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_CONTROL[] = {
+	 { "LoopbackSelect", 1, 4, &umr_bitfield_default },
+	 { "PRBSPCIeLbSelect", 5, 5, &umr_bitfield_default },
+	 { "LoopbackHalfRate", 6, 7, &umr_bitfield_default },
+	 { "LoopbackFifoPtr", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PCIETXMUX0[] = {
+	 { "TXLANE0", 0, 7, &umr_bitfield_default },
+	 { "TXLANE1", 8, 15, &umr_bitfield_default },
+	 { "TXLANE2", 16, 23, &umr_bitfield_default },
+	 { "TXLANE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PCIETXMUX1[] = {
+	 { "TXLANE4", 0, 7, &umr_bitfield_default },
+	 { "TXLANE5", 8, 15, &umr_bitfield_default },
+	 { "TXLANE6", 16, 23, &umr_bitfield_default },
+	 { "TXLANE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PCIETXMUX2[] = {
+	 { "TXLANE8", 0, 7, &umr_bitfield_default },
+	 { "TXLANE9", 8, 15, &umr_bitfield_default },
+	 { "TXLANE10", 16, 23, &umr_bitfield_default },
+	 { "TXLANE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PCIETXMUX3[] = {
+	 { "TXLANE12", 0, 7, &umr_bitfield_default },
+	 { "TXLANE13", 8, 15, &umr_bitfield_default },
+	 { "TXLANE14", 16, 23, &umr_bitfield_default },
+	 { "TXLANE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PCIERXMUX0[] = {
+	 { "RXLANE0", 0, 7, &umr_bitfield_default },
+	 { "RXLANE1", 8, 15, &umr_bitfield_default },
+	 { "RXLANE2", 16, 23, &umr_bitfield_default },
+	 { "RXLANE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PCIERXMUX1[] = {
+	 { "RXLANE4", 0, 7, &umr_bitfield_default },
+	 { "RXLANE5", 8, 15, &umr_bitfield_default },
+	 { "RXLANE6", 16, 23, &umr_bitfield_default },
+	 { "RXLANE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PCIERXMUX2[] = {
+	 { "RXLANE8", 0, 7, &umr_bitfield_default },
+	 { "RXLANE9", 8, 15, &umr_bitfield_default },
+	 { "RXLANE10", 16, 23, &umr_bitfield_default },
+	 { "RXLANE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PCIERXMUX3[] = {
+	 { "RXLANE12", 0, 7, &umr_bitfield_default },
+	 { "RXLANE13", 8, 15, &umr_bitfield_default },
+	 { "RXLANE14", 16, 23, &umr_bitfield_default },
+	 { "RXLANE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_LANEENABLE[] = {
+	 { "LANE_enable", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_PRBSCONTROL[] = {
+	 { "PRBSPCIeSelect", 0, 15, &umr_bitfield_default },
+	 { "LMLaneDegrade0", 28, 28, &umr_bitfield_default },
+	 { "LMLaneDegrade1", 29, 29, &umr_bitfield_default },
+	 { "LMLaneDegrade2", 30, 30, &umr_bitfield_default },
+	 { "LMLaneDegrade3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_POWERCONTROL[] = {
+	 { "LMTxPhyCmd0", 0, 2, &umr_bitfield_default },
+	 { "LMRxPhyCmd0", 3, 5, &umr_bitfield_default },
+	 { "LMLinkSpeed0", 6, 7, &umr_bitfield_default },
+	 { "LMTxPhyCmd1", 8, 10, &umr_bitfield_default },
+	 { "LMRxPhyCmd1", 11, 13, &umr_bitfield_default },
+	 { "LMLinkSpeed1", 14, 15, &umr_bitfield_default },
+	 { "LMTxPhyCmd2", 16, 18, &umr_bitfield_default },
+	 { "LMRxPhyCmd2", 19, 21, &umr_bitfield_default },
+	 { "LMLinkSpeed2", 22, 23, &umr_bitfield_default },
+	 { "LMTxPhyCmd3", 24, 26, &umr_bitfield_default },
+	 { "LMRxPhyCmd3", 27, 29, &umr_bitfield_default },
+	 { "LMLinkSpeed3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_POWERCONTROL1[] = {
+	 { "LMTxEn0", 0, 0, &umr_bitfield_default },
+	 { "LMTxClkEn0", 1, 1, &umr_bitfield_default },
+	 { "LMTxMargin0", 2, 4, &umr_bitfield_default },
+	 { "LMSkipBit0", 5, 5, &umr_bitfield_default },
+	 { "LMLaneUnused0", 6, 6, &umr_bitfield_default },
+	 { "LMTxMarginEn0", 7, 7, &umr_bitfield_default },
+	 { "LMDeemph0", 8, 8, &umr_bitfield_default },
+	 { "LMTxEn1", 9, 9, &umr_bitfield_default },
+	 { "LMTxClkEn1", 10, 10, &umr_bitfield_default },
+	 { "LMTxMargin1", 11, 13, &umr_bitfield_default },
+	 { "LMSkipBit1", 14, 14, &umr_bitfield_default },
+	 { "LMLaneUnused1", 15, 15, &umr_bitfield_default },
+	 { "LMTxMarginEn1", 16, 16, &umr_bitfield_default },
+	 { "LMDeemph1", 17, 17, &umr_bitfield_default },
+	 { "LMTxEn2", 18, 18, &umr_bitfield_default },
+	 { "LMTxClkEn2", 19, 19, &umr_bitfield_default },
+	 { "LMTxMargin2", 20, 22, &umr_bitfield_default },
+	 { "LMSkipBit2", 23, 23, &umr_bitfield_default },
+	 { "LMLaneUnused2", 24, 24, &umr_bitfield_default },
+	 { "LMTxMarginEn2", 25, 25, &umr_bitfield_default },
+	 { "LMDeemph2", 26, 26, &umr_bitfield_default },
+	 { "TxCoeffID0", 27, 28, &umr_bitfield_default },
+	 { "TxCoeffID1", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_POWERCONTROL2[] = {
+	 { "LMTxEn3", 0, 0, &umr_bitfield_default },
+	 { "LMTxClkEn3", 1, 1, &umr_bitfield_default },
+	 { "LMTxMargin3", 2, 4, &umr_bitfield_default },
+	 { "LMSkipBit3", 5, 5, &umr_bitfield_default },
+	 { "LMLaneUnused3", 6, 6, &umr_bitfield_default },
+	 { "LMTxMarginEn3", 7, 7, &umr_bitfield_default },
+	 { "LMDeemph3", 8, 8, &umr_bitfield_default },
+	 { "TxCoeffID2", 9, 10, &umr_bitfield_default },
+	 { "TxCoeffID3", 11, 12, &umr_bitfield_default },
+	 { "TxCoeff0", 13, 18, &umr_bitfield_default },
+	 { "TxCoeff1", 19, 24, &umr_bitfield_default },
+	 { "TxCoeff2", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_POWERCONTROL3[] = {
+	 { "TxCoeff3", 0, 5, &umr_bitfield_default },
+	 { "RxEqCtl0", 6, 11, &umr_bitfield_default },
+	 { "RxEqCtl1", 12, 17, &umr_bitfield_default },
+	 { "RxEqCtl2", 18, 23, &umr_bitfield_default },
+	 { "RxEqCtl3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_BIF_LM_POWERCONTROL4[] = {
+	 { "LinkNum0", 0, 2, &umr_bitfield_default },
+	 { "LinkNum1", 3, 5, &umr_bitfield_default },
+	 { "LinkNum2", 6, 8, &umr_bitfield_default },
+	 { "LinkNum3", 9, 11, &umr_bitfield_default },
+	 { "LaneNum0", 12, 15, &umr_bitfield_default },
+	 { "LaneNum1", 16, 19, &umr_bitfield_default },
+	 { "LaneNum2", 20, 23, &umr_bitfield_default },
+	 { "LaneNum3", 24, 27, &umr_bitfield_default },
+	 { "SpcMode0", 28, 28, &umr_bitfield_default },
+	 { "SpcMode1", 29, 29, &umr_bitfield_default },
+	 { "SpcMode2", 30, 30, &umr_bitfield_default },
+	 { "SpcMode3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_CNTL[] = {
+	 { "CP_RB0_WPTR", 0, 0, &umr_bitfield_default },
+	 { "CP_RB1_WPTR", 1, 1, &umr_bitfield_default },
+	 { "CP_RB2_WPTR", 2, 2, &umr_bitfield_default },
+	 { "UVD_RBC_RB_WPTR", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR", 5, 5, &umr_bitfield_default },
+	 { "CP_DMA_ME_COMMAND", 6, 6, &umr_bitfield_default },
+	 { "CP_DMA_PFP_COMMAND", 7, 7, &umr_bitfield_default },
+	 { "SAM_SAB_RBI_WPTR", 8, 8, &umr_bitfield_default },
+	 { "SAM_SAB_RBO_WPTR", 9, 9, &umr_bitfield_default },
+	 { "VCE_OUT_RB_WPTR", 10, 10, &umr_bitfield_default },
+	 { "VCE_RB_WPTR2", 11, 11, &umr_bitfield_default },
+	 { "VCE_RB_WPTR", 12, 12, &umr_bitfield_default },
+	 { "HOST_DOORBELL", 13, 13, &umr_bitfield_default },
+	 { "SELFRING_DOORBELL", 14, 14, &umr_bitfield_default },
+	 { "CP_DMA_PIO_COMMAND", 15, 15, &umr_bitfield_default },
+	 { "DISPLAY", 16, 16, &umr_bitfield_default },
+	 { "SDMA2_GFX_RB_WPTR", 17, 17, &umr_bitfield_default },
+	 { "SDMA3_GFX_RB_WPTR", 18, 18, &umr_bitfield_default },
+	 { "IGNORE_MC_DISABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_0[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_1[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_2[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_3[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_3[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_4[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_4[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_5[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_5[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_6[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_6[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_START_7[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MODE", 1, 1, &umr_bitfield_default },
+	 { "ADDR_START", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_RESERVED[] = {
+	 { "PCIE_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_SCRATCH[] = {
+	 { "PCIE_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_RX_NUM_NAK[] = {
+	 { "RX_NUM_NAK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED[] = {
+	 { "RX_NUM_NAK_GENERATED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_CNTL[] = {
+	 { "HWINIT_WR_LOCK", 0, 0, &umr_bitfield_default },
+	 { "LC_HOT_PLUG_DELAY_SEL", 1, 3, &umr_bitfield_default },
+	 { "UR_ERR_REPORT_DIS", 7, 7, &umr_bitfield_default },
+	 { "PCIE_MALFORM_ATOMIC_OPS", 8, 8, &umr_bitfield_default },
+	 { "PCIE_HT_NP_MEM_WRITE", 9, 9, &umr_bitfield_default },
+	 { "RX_SB_ADJ_PAYLOAD_SIZE", 10, 12, &umr_bitfield_default },
+	 { "RX_RCB_ATS_UC_DIS", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_REORDER_EN", 16, 16, &umr_bitfield_default },
+	 { "RX_RCB_INVALID_SIZE_DIS", 17, 17, &umr_bitfield_default },
+	 { "RX_RCB_UNEXP_CPL_DIS", 18, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_TEST_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_PREFIX_DIS", 20, 20, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_ATTR_DIS", 21, 21, &umr_bitfield_default },
+	 { "RX_RCB_WRONG_FUNCNUM_DIS", 22, 22, &umr_bitfield_default },
+	 { "RX_ATS_TRAN_CPL_SPLIT_DIS", 23, 23, &umr_bitfield_default },
+	 { "TX_CPL_DEBUG", 24, 29, &umr_bitfield_default },
+	 { "RX_IGNORE_LTR_MSG_UR", 30, 30, &umr_bitfield_default },
+	 { "RX_CPL_POSTED_REQ_ORD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_CONFIG_CNTL[] = {
+	 { "DYN_CLK_LATENCY", 0, 3, &umr_bitfield_default },
+	 { "CI_MAX_PAYLOAD_SIZE_MODE", 16, 16, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_PAYLOAD_SIZE", 17, 19, &umr_bitfield_default },
+	 { "CI_MAX_READ_REQUEST_SIZE_MODE", 20, 20, &umr_bitfield_default },
+	 { "CI_PRIV_MAX_READ_REQUEST_SIZE", 21, 23, &umr_bitfield_default },
+	 { "CI_MAX_READ_SAFE_MODE", 24, 24, &umr_bitfield_default },
+	 { "CI_EXTENDED_TAG_EN_OVERRIDE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_DEBUG_CNTL[] = {
+	 { "DEBUG_PORT_EN", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_SELECT", 8, 8, &umr_bitfield_default },
+	 { "DEBUG_LANE_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_CNTL2[] = {
+	 { "TX_ARB_ROUND_ROBIN_EN", 0, 0, &umr_bitfield_default },
+	 { "TX_ARB_SLV_LIMIT", 1, 5, &umr_bitfield_default },
+	 { "TX_ARB_MST_LIMIT", 6, 10, &umr_bitfield_default },
+	 { "TX_BLOCK_TLP_ON_PM_DIS", 11, 11, &umr_bitfield_default },
+	 { "TX_NP_MEM_WRITE_SWP_ENCODING", 12, 12, &umr_bitfield_default },
+	 { "TX_ATOMIC_OPS_DISABLE", 13, 13, &umr_bitfield_default },
+	 { "TX_ATOMIC_ORDERING_DIS", 14, 14, &umr_bitfield_default },
+	 { "SLV_MEM_LS_EN", 16, 16, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_LS_EN", 17, 17, &umr_bitfield_default },
+	 { "MST_MEM_LS_EN", 18, 18, &umr_bitfield_default },
+	 { "REPLAY_MEM_LS_EN", 19, 19, &umr_bitfield_default },
+	 { "SLV_MEM_SD_EN", 20, 20, &umr_bitfield_default },
+	 { "SLV_MEM_AGGRESSIVE_SD_EN", 21, 21, &umr_bitfield_default },
+	 { "MST_MEM_SD_EN", 22, 22, &umr_bitfield_default },
+	 { "REPLAY_MEM_SD_EN", 23, 23, &umr_bitfield_default },
+	 { "RX_NP_MEM_WRITE_ENCODING", 24, 28, &umr_bitfield_default },
+	 { "SLV_MEM_DS_EN", 29, 29, &umr_bitfield_default },
+	 { "MST_MEM_DS_EN", 30, 30, &umr_bitfield_default },
+	 { "REPLAY_MEM_DS_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_RX_CNTL2[] = {
+	 { "RX_IGNORE_EP_INVALIDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMRD_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_TRANSMWR_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ATSTRANSREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_PAGEREQMSG_UR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_INVCPL_UR", 5, 5, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_EN", 8, 8, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_SCALE", 9, 11, &umr_bitfield_default },
+	 { "SLVCPL_MEM_LS_EN", 12, 12, &umr_bitfield_default },
+	 { "SLVCPL_MEM_SD_EN", 13, 13, &umr_bitfield_default },
+	 { "SLVCPL_MEM_DS_EN", 14, 14, &umr_bitfield_default },
+	 { "RX_RCB_LATENCY_MAX_COUNT", 16, 25, &umr_bitfield_default },
+	 { "FLR_EXTEND_MODE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL[] = {
+	 { "TX_F0_IDO_OVERRIDE_P", 0, 1, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_NP", 2, 3, &umr_bitfield_default },
+	 { "TX_F0_IDO_OVERRIDE_CPL", 4, 5, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_P", 6, 7, &umr_bitfield_default },
+	 { "TX_F0_RO_OVERRIDE_NP", 8, 9, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_P", 10, 11, &umr_bitfield_default },
+	 { "TX_F0_SNR_OVERRIDE_NP", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_CI_CNTL[] = {
+	 { "CI_SLAVE_SPLIT_MODE", 2, 2, &umr_bitfield_default },
+	 { "CI_SLAVE_GEN_USR_DIS", 3, 3, &umr_bitfield_default },
+	 { "CI_MST_CMPL_DUMMY_DATA", 4, 4, &umr_bitfield_default },
+	 { "CI_SLV_RC_RD_REQ_SIZE", 6, 7, &umr_bitfield_default },
+	 { "CI_SLV_ORDERING_DIS", 8, 8, &umr_bitfield_default },
+	 { "CI_RC_ORDERING_DIS", 9, 9, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_DIS", 10, 10, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_MODE", 11, 11, &umr_bitfield_default },
+	 { "CI_SLV_CPL_ALLOC_SOR", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_BUS_CNTL[] = {
+	 { "PMI_INT_DIS", 6, 6, &umr_bitfield_default },
+	 { "IMMEDIATE_PMI_DIS", 7, 7, &umr_bitfield_default },
+	 { "TRUE_PM_STATUS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_STATE6[] = {
+	 { "LC_PREV_STATE24", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE25", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE26", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE27", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_STATE7[] = {
+	 { "LC_PREV_STATE28", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE29", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE30", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE31", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_STATE8[] = {
+	 { "LC_PREV_STATE32", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE33", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE34", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE35", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_STATE9[] = {
+	 { "LC_PREV_STATE36", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE37", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE38", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE39", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_STATE10[] = {
+	 { "LC_PREV_STATE40", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE41", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE42", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE43", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_STATE11[] = {
+	 { "LC_PREV_STATE44", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE45", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE46", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE47", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_STATUS1[] = {
+	 { "LC_REVERSE_RCVR", 0, 0, &umr_bitfield_default },
+	 { "LC_REVERSE_XMIT", 1, 1, &umr_bitfield_default },
+	 { "LC_OPERATING_LINK_WIDTH", 2, 4, &umr_bitfield_default },
+	 { "LC_DETECTED_LINK_WIDTH", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_STATUS2[] = {
+	 { "LC_TOTAL_INACTIVE_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_TURN_ON_LANE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_WPR_CNTL[] = {
+	 { "WPR_RESET_HOT_RST_EN", 0, 0, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DWN_EN", 1, 1, &umr_bitfield_default },
+	 { "WPR_RESET_LNK_DIS_EN", 2, 2, &umr_bitfield_default },
+	 { "WPR_RESET_COR_EN", 3, 3, &umr_bitfield_default },
+	 { "WPR_RESET_REG_EN", 4, 4, &umr_bitfield_default },
+	 { "WPR_RESET_STY_EN", 5, 5, &umr_bitfield_default },
+	 { "WPR_RESET_PHY_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_RX_LAST_TLP0[] = {
+	 { "RX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_RX_LAST_TLP1[] = {
+	 { "RX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_RX_LAST_TLP2[] = {
+	 { "RX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_RX_LAST_TLP3[] = {
+	 { "RX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_TX_LAST_TLP0[] = {
+	 { "TX_LAST_TLP0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_TX_LAST_TLP1[] = {
+	 { "TX_LAST_TLP1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_TX_LAST_TLP2[] = {
+	 { "TX_LAST_TLP2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_TX_LAST_TLP3[] = {
+	 { "TX_LAST_TLP3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND[] = {
+	 { "I2C_REG_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_I2C_REG_DATA[] = {
+	 { "I2C_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_CFG_CNTL[] = {
+	 { "CFG_EN_DEC_TO_HIDDEN_REG", 0, 0, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN2_HIDDEN_REG", 1, 1, &umr_bitfield_default },
+	 { "CFG_EN_DEC_TO_GEN3_HIDDEN_REG", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_LC_PM_CNTL[] = {
+	 { "LC_L1_POWER_GATING_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_P_CNTL[] = {
+	 { "P_PWRDN_EN", 0, 0, &umr_bitfield_default },
+	 { "P_SYMALIGN_MODE", 1, 1, &umr_bitfield_default },
+	 { "P_SYMALIGN_HW_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "P_ELASTDESKEW_HW_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "P_IGNORE_CRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "P_IGNORE_LEN_ERR", 5, 5, &umr_bitfield_default },
+	 { "P_IGNORE_EDB_ERR", 6, 6, &umr_bitfield_default },
+	 { "P_IGNORE_IDL_ERR", 7, 7, &umr_bitfield_default },
+	 { "P_IGNORE_TOK_ERR", 8, 8, &umr_bitfield_default },
+	 { "P_BLK_LOCK_MODE", 12, 12, &umr_bitfield_default },
+	 { "P_ALWAYS_USE_FAST_TXCLK", 13, 13, &umr_bitfield_default },
+	 { "P_ELEC_IDLE_MODE", 14, 15, &umr_bitfield_default },
+	 { "DLP_IGNORE_IN_L1_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_P_BUF_STATUS[] = {
+	 { "P_OVERFLOW_ERR", 0, 15, &umr_bitfield_default },
+	 { "P_UNDERFLOW_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_P_DECODER_STATUS[] = {
+	 { "P_DECODE_ERR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_P_MISC_STATUS[] = {
+	 { "P_DESKEW_ERR", 0, 7, &umr_bitfield_default },
+	 { "P_SYMUNLOCK_ERR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET[] = {
+	 { "P_RCV_L0S_FTS_DET_MIN", 0, 7, &umr_bitfield_default },
+	 { "P_RCV_L0S_FTS_DET_MAX", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT_CNTL[] = {
+	 { "GLOBAL_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GLOBAL_SHADOW_WR", 1, 1, &umr_bitfield_default },
+	 { "GLOBAL_COUNT_RESET", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[] = {
+	 { "PERF0_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF0_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[] = {
+	 { "PERF1_PORT_SEL_TXCLK", 0, 3, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_R_CLK", 4, 7, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_MST_C_CLK", 8, 11, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_R_CLK", 12, 15, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_S_C_CLK", 16, 19, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_SLV_NS_C_CLK", 20, 23, &umr_bitfield_default },
+	 { "PERF1_PORT_SEL_TXCLK2", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2[] = {
+	 { "EVENT0_SEL", 0, 7, &umr_bitfield_default },
+	 { "EVENT1_SEL", 8, 15, &umr_bitfield_default },
+	 { "COUNTER0_UPPER", 16, 23, &umr_bitfield_default },
+	 { "COUNTER1_UPPER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2[] = {
+	 { "COUNTER0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2[] = {
+	 { "COUNTER1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_STRAP_F0[] = {
+	 { "STRAP_F0_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_F0_LEGACY_DEVICE_TYPE_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_F0_VC_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_F0_DSN_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_F0_AER_EN", 5, 5, &umr_bitfield_default },
+	 { "STRAP_F0_ACS_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_F0_BAR_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_F0_PWR_EN", 8, 8, &umr_bitfield_default },
+	 { "STRAP_F0_DPA_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_F0_ATS_EN", 10, 10, &umr_bitfield_default },
+	 { "STRAP_F0_PAGE_REQ_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_F0_PASID_EN", 12, 12, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_CHECK_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_F0_ECRC_GEN_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_F0_CPL_ABORT_ERR_EN", 15, 15, &umr_bitfield_default },
+	 { "STRAP_F0_POISONED_ADVISORY_NONFATAL", 16, 16, &umr_bitfield_default },
+	 { "STRAP_F0_MC_EN", 17, 17, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_EN", 18, 18, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_64BIT_EN", 19, 19, &umr_bitfield_default },
+	 { "STRAP_F0_ATOMIC_ROUTING_EN", 20, 20, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_MULTI_CAP", 21, 23, &umr_bitfield_default },
+	 { "STRAP_F0_VFn_MSI_MULTI_CAP", 24, 26, &umr_bitfield_default },
+	 { "STRAP_F0_MSI_PERVECTOR_MASK_CAP", 27, 27, &umr_bitfield_default },
+	 { "STRAP_F0_NO_RO_ENABLED_P2P_PASSING", 28, 28, &umr_bitfield_default },
+	 { "STRAP_F0_ARI_EN", 29, 29, &umr_bitfield_default },
+	 { "STRAP_F0_SRIOV_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_STRAP_MISC[] = {
+	 { "STRAP_TL_ALT_BUF_EN", 4, 4, &umr_bitfield_default },
+	 { "STRAP_CLK_PM_EN", 24, 24, &umr_bitfield_default },
+	 { "STRAP_ECN1P1_EN", 25, 25, &umr_bitfield_default },
+	 { "STRAP_EXT_VC_COUNT", 26, 26, &umr_bitfield_default },
+	 { "STRAP_REVERSE_ALL", 28, 28, &umr_bitfield_default },
+	 { "STRAP_MST_ADR64_EN", 29, 29, &umr_bitfield_default },
+	 { "STRAP_FLR_EN", 30, 30, &umr_bitfield_default },
+	 { "STRAP_INTERNAL_ERR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_STRAP_MISC2[] = {
+	 { "STRAP_LINK_BW_NOTIFICATION_CAP_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_GEN2_COMPLIANCE", 1, 1, &umr_bitfield_default },
+	 { "STRAP_MSTCPL_TIMEOUT_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_GEN3_COMPLIANCE", 3, 3, &umr_bitfield_default },
+	 { "STRAP_TPH_SUPPORTED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_STRAP_PI[] = {
+	 { "STRAP_QUICKSIM_START", 0, 0, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_PATTERN", 28, 28, &umr_bitfield_default },
+	 { "STRAP_TEST_TOGGLE_MODE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_STRAP_I2C_BD[] = {
+	 { "STRAP_BIF_I2C_SLV_ADR", 0, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_DBG_I2C_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_CLR[] = {
+	 { "PRBS_CLR", 0, 15, &umr_bitfield_default },
+	 { "PRBS_CHECKER_DEBUG_BUS_SELECT", 16, 19, &umr_bitfield_default },
+	 { "PRBS_POLARITY_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_STATUS1[] = {
+	 { "PRBS_ERRSTAT", 0, 15, &umr_bitfield_default },
+	 { "PRBS_LOCKED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_STATUS2[] = {
+	 { "PRBS_BITCNT_DONE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_FREERUN[] = {
+	 { "PRBS_FREERUN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_MISC[] = {
+	 { "PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "PRBS_TEST_MODE", 1, 3, &umr_bitfield_default },
+	 { "PRBS_USER_PATTERN_TOGGLE", 4, 4, &umr_bitfield_default },
+	 { "PRBS_8BIT_SEL", 5, 5, &umr_bitfield_default },
+	 { "PRBS_COMMA_NUM", 6, 7, &umr_bitfield_default },
+	 { "PRBS_LOCK_CNT", 8, 12, &umr_bitfield_default },
+	 { "PRBS_DATA_RATE", 14, 15, &umr_bitfield_default },
+	 { "PRBS_CHK_ERR_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_USER_PATTERN[] = {
+	 { "PRBS_USER_PATTERN", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_LO_BITCNT[] = {
+	 { "PRBS_LO_BITCNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_HI_BITCNT[] = {
+	 { "PRBS_HI_BITCNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_0[] = {
+	 { "PRBS_ERRCNT_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_1[] = {
+	 { "PRBS_ERRCNT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_2[] = {
+	 { "PRBS_ERRCNT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_3[] = {
+	 { "PRBS_ERRCNT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_4[] = {
+	 { "PRBS_ERRCNT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_5[] = {
+	 { "PRBS_ERRCNT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_6[] = {
+	 { "PRBS_ERRCNT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_7[] = {
+	 { "PRBS_ERRCNT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_8[] = {
+	 { "PRBS_ERRCNT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_9[] = {
+	 { "PRBS_ERRCNT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_10[] = {
+	 { "PRBS_ERRCNT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_11[] = {
+	 { "PRBS_ERRCNT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_12[] = {
+	 { "PRBS_ERRCNT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_13[] = {
+	 { "PRBS_ERRCNT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_14[] = {
+	 { "PRBS_ERRCNT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_PCIE_PRBS_ERRCNT_15[] = {
+	 { "PRBS_ERRCNT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_COMMAND_STATUS[] = {
+	 { "RECONFIGURE", 0, 0, &umr_bitfield_default },
+	 { "ATOMIC_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESET_COMPLETE", 16, 16, &umr_bitfield_default },
+	 { "WAIT_STATE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_GENERAL_CONTROL[] = {
+	 { "RECONFIGURE_EN", 0, 0, &umr_bitfield_default },
+	 { "ATOMIC_RESET_EN", 1, 1, &umr_bitfield_default },
+	 { "RESET_PERIOD", 2, 4, &umr_bitfield_default },
+	 { "WAIT_LINKUP", 8, 8, &umr_bitfield_default },
+	 { "FORCE_REGIDLE", 9, 9, &umr_bitfield_default },
+	 { "BLOCK_ON_IDLE", 10, 10, &umr_bitfield_default },
+	 { "CONFIG_XFER_MODE", 12, 12, &umr_bitfield_default },
+	 { "MUXSEL_XFER_MODE", 13, 13, &umr_bitfield_default },
+	 { "HLDTRAIN_XFER_MODE", 14, 14, &umr_bitfield_default },
+	 { "BYPASS_HOLD", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_PIF_HOLD", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_COMMAND_0[] = {
+	 { "BIF_STRAPREG_RESET", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESET", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESET", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESET", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESET", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESET", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESET", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESET", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_COMMAND_1[] = {
+	 { "SWITCHCLK", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1", 5, 5, &umr_bitfield_default },
+	 { "RESETLC", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1", 25, 25, &umr_bitfield_default },
+	 { "TOGGLESTRAP", 28, 28, &umr_bitfield_default },
+	 { "CMDCFGEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_CONTROL_0[] = {
+	 { "BIF_STRAPREG_RESETRCEN", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESETRCEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESETRCEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESETRCEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESETRCEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESETRCEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESETRCEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESETRCEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_CONTROL_1[] = {
+	 { "SWITCHCLK_RCEN", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG_RCEN", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX_RCEN", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS_RCEN", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0_RCEN", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1_RCEN", 5, 5, &umr_bitfield_default },
+	 { "RESETLC_RCEN", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0_RCEN", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1_RCEN", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR_RCEN", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR_RCEN", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM_RCEN", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0_RCEN", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1_RCEN", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0_RCEN", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1_RCEN", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0_RCEN", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1_RCEN", 25, 25, &umr_bitfield_default },
+	 { "STRAPVLD_RCEN", 28, 28, &umr_bitfield_default },
+	 { "CMDCFG_RCEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_CONTROL_2[] = {
+	 { "BIF_STRAPREG_RESETATEN", 15, 15, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_RESETATEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_RESETATEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_RESETATEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_RESETATEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_RESETATEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_RESETATEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_RESETATEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_CONTROL_3[] = {
+	 { "SWITCHCLK_ATEN", 0, 0, &umr_bitfield_default },
+	 { "RESETPCFG_ATEN", 1, 1, &umr_bitfield_default },
+	 { "RESETLANEMUX_ATEN", 2, 2, &umr_bitfield_default },
+	 { "RESETWRAPREGS_ATEN", 3, 3, &umr_bitfield_default },
+	 { "RESETSRBM0_ATEN", 4, 4, &umr_bitfield_default },
+	 { "RESETSRBM1_ATEN", 5, 5, &umr_bitfield_default },
+	 { "RESETLC_ATEN", 6, 6, &umr_bitfield_default },
+	 { "SYNCIDLEPIF0_ATEN", 8, 8, &umr_bitfield_default },
+	 { "SYNCIDLEPIF1_ATEN", 9, 9, &umr_bitfield_default },
+	 { "RESETMNTR_ATEN", 13, 13, &umr_bitfield_default },
+	 { "RESETHLTR_ATEN", 14, 14, &umr_bitfield_default },
+	 { "RESETCPM_ATEN", 15, 15, &umr_bitfield_default },
+	 { "RESETPIF0_ATEN", 16, 16, &umr_bitfield_default },
+	 { "RESETPIF1_ATEN", 17, 17, &umr_bitfield_default },
+	 { "RESETIMPARB0_ATEN", 20, 20, &umr_bitfield_default },
+	 { "RESETIMPARB1_ATEN", 21, 21, &umr_bitfield_default },
+	 { "RESETPHY0_ATEN", 24, 24, &umr_bitfield_default },
+	 { "RESETPHY1_ATEN", 25, 25, &umr_bitfield_default },
+	 { "STRAPVLD_ATEN", 28, 28, &umr_bitfield_default },
+	 { "CMDCFG_ATEN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_CONTROL_4[] = {
+	 { "BIF_STRAPREG_WRRESETEN", 14, 14, &umr_bitfield_default },
+	 { "BIF0_GLOBAL_WRRESETEN", 16, 16, &umr_bitfield_default },
+	 { "BIF0_CALIB_WRRESETEN", 17, 17, &umr_bitfield_default },
+	 { "BIF0_CORE_WRRESETEN", 18, 18, &umr_bitfield_default },
+	 { "BIF0_REGISTER_WRRESETEN", 19, 19, &umr_bitfield_default },
+	 { "BIF0_PHY_WRRESETEN", 20, 20, &umr_bitfield_default },
+	 { "BIF0_STICKY_WRRESETEN", 21, 21, &umr_bitfield_default },
+	 { "BIF0_CONFIG_WRRESETEN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_CONTROL_5[] = {
+	 { "WRSWITCHCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "WRRESETPCFG_EN", 1, 1, &umr_bitfield_default },
+	 { "WRRESETLANEMUX_EN", 2, 2, &umr_bitfield_default },
+	 { "WRRESETWRAPREGS_EN", 3, 3, &umr_bitfield_default },
+	 { "WRRESETSRBM0_EN", 4, 4, &umr_bitfield_default },
+	 { "WRRESETSRBM1_EN", 5, 5, &umr_bitfield_default },
+	 { "WRRESETLC_EN", 6, 6, &umr_bitfield_default },
+	 { "WRSYNCIDLEPIF0_EN", 8, 8, &umr_bitfield_default },
+	 { "WRSYNCIDLEPIF1_EN", 9, 9, &umr_bitfield_default },
+	 { "WRRESETMNTR_EN", 13, 13, &umr_bitfield_default },
+	 { "WRRESETHLTR_EN", 14, 14, &umr_bitfield_default },
+	 { "WRRESETCPM_EN", 15, 15, &umr_bitfield_default },
+	 { "WRRESETPIF0_EN", 16, 16, &umr_bitfield_default },
+	 { "WRRESETPIF1_EN", 17, 17, &umr_bitfield_default },
+	 { "WRRESETIMPARB0_EN", 20, 20, &umr_bitfield_default },
+	 { "WRRESETIMPARB1_EN", 21, 21, &umr_bitfield_default },
+	 { "WRRESETPHY0_EN", 24, 24, &umr_bitfield_default },
+	 { "WRRESETPHY1_EN", 25, 25, &umr_bitfield_default },
+	 { "WRSTRAPVLD_EN", 28, 28, &umr_bitfield_default },
+	 { "WRCMDCFG_EN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_SWRST_CONTROL_6[] = {
+	 { "WARMRESET_EN", 0, 0, &umr_bitfield_default },
+	 { "CONNECTWITHWRAPREGS_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_CPM_CONTROL[] = {
+	 { "LCLK_DYN_GATE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TXCLK_DYN_GATE_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "TXCLK_PIF_GATE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "TXCLK_GSKT_GATE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "TXCLK_LCNT_GATE_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "TXCLK_REGS_GATE_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "TXCLK_PRBS_GATE_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "REFCLK_REGS_GATE_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "LCLK_DYN_GATE_LATENCY", 9, 9, &umr_bitfield_default },
+	 { "TXCLK_DYN_GATE_LATENCY", 10, 10, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_LATENCY", 11, 11, &umr_bitfield_default },
+	 { "TXCLK_REGS_GATE_LATENCY", 12, 12, &umr_bitfield_default },
+	 { "REFCLK_REGS_GATE_LATENCY", 13, 13, &umr_bitfield_default },
+	 { "LCLK_GATE_TXCLK_FREE", 14, 14, &umr_bitfield_default },
+	 { "RCVR_DET_CLK_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "TXCLK_PERM_GATE_PLL_PDN", 16, 16, &umr_bitfield_default },
+	 { "FAST_TXCLK_LATENCY", 17, 19, &umr_bitfield_default },
+	 { "MASTER_PCIE_PLL_SELECT", 20, 20, &umr_bitfield_default },
+	 { "MASTER_PCIE_PLL_AUTO", 21, 21, &umr_bitfield_default },
+	 { "REFCLK_XSTCLK_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "REFCLK_XSTCLK_LATENCY", 23, 23, &umr_bitfield_default },
+	 { "SPARE_REGS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_CONTROL[] = {
+	 { "LoopbackSelect", 1, 4, &umr_bitfield_default },
+	 { "PRBSPCIeLbSelect", 5, 5, &umr_bitfield_default },
+	 { "LoopbackHalfRate", 6, 7, &umr_bitfield_default },
+	 { "LoopbackFifoPtr", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PCIETXMUX0[] = {
+	 { "TXLANE0", 0, 7, &umr_bitfield_default },
+	 { "TXLANE1", 8, 15, &umr_bitfield_default },
+	 { "TXLANE2", 16, 23, &umr_bitfield_default },
+	 { "TXLANE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PCIETXMUX1[] = {
+	 { "TXLANE4", 0, 7, &umr_bitfield_default },
+	 { "TXLANE5", 8, 15, &umr_bitfield_default },
+	 { "TXLANE6", 16, 23, &umr_bitfield_default },
+	 { "TXLANE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PCIETXMUX2[] = {
+	 { "TXLANE8", 0, 7, &umr_bitfield_default },
+	 { "TXLANE9", 8, 15, &umr_bitfield_default },
+	 { "TXLANE10", 16, 23, &umr_bitfield_default },
+	 { "TXLANE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PCIETXMUX3[] = {
+	 { "TXLANE12", 0, 7, &umr_bitfield_default },
+	 { "TXLANE13", 8, 15, &umr_bitfield_default },
+	 { "TXLANE14", 16, 23, &umr_bitfield_default },
+	 { "TXLANE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PCIERXMUX0[] = {
+	 { "RXLANE0", 0, 7, &umr_bitfield_default },
+	 { "RXLANE1", 8, 15, &umr_bitfield_default },
+	 { "RXLANE2", 16, 23, &umr_bitfield_default },
+	 { "RXLANE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PCIERXMUX1[] = {
+	 { "RXLANE4", 0, 7, &umr_bitfield_default },
+	 { "RXLANE5", 8, 15, &umr_bitfield_default },
+	 { "RXLANE6", 16, 23, &umr_bitfield_default },
+	 { "RXLANE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PCIERXMUX2[] = {
+	 { "RXLANE8", 0, 7, &umr_bitfield_default },
+	 { "RXLANE9", 8, 15, &umr_bitfield_default },
+	 { "RXLANE10", 16, 23, &umr_bitfield_default },
+	 { "RXLANE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PCIERXMUX3[] = {
+	 { "RXLANE12", 0, 7, &umr_bitfield_default },
+	 { "RXLANE13", 8, 15, &umr_bitfield_default },
+	 { "RXLANE14", 16, 23, &umr_bitfield_default },
+	 { "RXLANE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_LANEENABLE[] = {
+	 { "LANE_enable", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_PRBSCONTROL[] = {
+	 { "PRBSPCIeSelect", 0, 15, &umr_bitfield_default },
+	 { "LMLaneDegrade0", 28, 28, &umr_bitfield_default },
+	 { "LMLaneDegrade1", 29, 29, &umr_bitfield_default },
+	 { "LMLaneDegrade2", 30, 30, &umr_bitfield_default },
+	 { "LMLaneDegrade3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_POWERCONTROL[] = {
+	 { "LMTxPhyCmd0", 0, 2, &umr_bitfield_default },
+	 { "LMRxPhyCmd0", 3, 5, &umr_bitfield_default },
+	 { "LMLinkSpeed0", 6, 7, &umr_bitfield_default },
+	 { "LMTxPhyCmd1", 8, 10, &umr_bitfield_default },
+	 { "LMRxPhyCmd1", 11, 13, &umr_bitfield_default },
+	 { "LMLinkSpeed1", 14, 15, &umr_bitfield_default },
+	 { "LMTxPhyCmd2", 16, 18, &umr_bitfield_default },
+	 { "LMRxPhyCmd2", 19, 21, &umr_bitfield_default },
+	 { "LMLinkSpeed2", 22, 23, &umr_bitfield_default },
+	 { "LMTxPhyCmd3", 24, 26, &umr_bitfield_default },
+	 { "LMRxPhyCmd3", 27, 29, &umr_bitfield_default },
+	 { "LMLinkSpeed3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_POWERCONTROL1[] = {
+	 { "LMTxEn0", 0, 0, &umr_bitfield_default },
+	 { "LMTxClkEn0", 1, 1, &umr_bitfield_default },
+	 { "LMTxMargin0", 2, 4, &umr_bitfield_default },
+	 { "LMSkipBit0", 5, 5, &umr_bitfield_default },
+	 { "LMLaneUnused0", 6, 6, &umr_bitfield_default },
+	 { "LMTxMarginEn0", 7, 7, &umr_bitfield_default },
+	 { "LMDeemph0", 8, 8, &umr_bitfield_default },
+	 { "LMTxEn1", 9, 9, &umr_bitfield_default },
+	 { "LMTxClkEn1", 10, 10, &umr_bitfield_default },
+	 { "LMTxMargin1", 11, 13, &umr_bitfield_default },
+	 { "LMSkipBit1", 14, 14, &umr_bitfield_default },
+	 { "LMLaneUnused1", 15, 15, &umr_bitfield_default },
+	 { "LMTxMarginEn1", 16, 16, &umr_bitfield_default },
+	 { "LMDeemph1", 17, 17, &umr_bitfield_default },
+	 { "LMTxEn2", 18, 18, &umr_bitfield_default },
+	 { "LMTxClkEn2", 19, 19, &umr_bitfield_default },
+	 { "LMTxMargin2", 20, 22, &umr_bitfield_default },
+	 { "LMSkipBit2", 23, 23, &umr_bitfield_default },
+	 { "LMLaneUnused2", 24, 24, &umr_bitfield_default },
+	 { "LMTxMarginEn2", 25, 25, &umr_bitfield_default },
+	 { "LMDeemph2", 26, 26, &umr_bitfield_default },
+	 { "TxCoeffID0", 27, 28, &umr_bitfield_default },
+	 { "TxCoeffID1", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_POWERCONTROL2[] = {
+	 { "LMTxEn3", 0, 0, &umr_bitfield_default },
+	 { "LMTxClkEn3", 1, 1, &umr_bitfield_default },
+	 { "LMTxMargin3", 2, 4, &umr_bitfield_default },
+	 { "LMSkipBit3", 5, 5, &umr_bitfield_default },
+	 { "LMLaneUnused3", 6, 6, &umr_bitfield_default },
+	 { "LMTxMarginEn3", 7, 7, &umr_bitfield_default },
+	 { "LMDeemph3", 8, 8, &umr_bitfield_default },
+	 { "TxCoeffID2", 9, 10, &umr_bitfield_default },
+	 { "TxCoeffID3", 11, 12, &umr_bitfield_default },
+	 { "TxCoeff0", 13, 18, &umr_bitfield_default },
+	 { "TxCoeff1", 19, 24, &umr_bitfield_default },
+	 { "TxCoeff2", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_POWERCONTROL3[] = {
+	 { "TxCoeff3", 0, 5, &umr_bitfield_default },
+	 { "RxEqCtl0", 6, 11, &umr_bitfield_default },
+	 { "RxEqCtl1", 12, 17, &umr_bitfield_default },
+	 { "RxEqCtl2", 18, 23, &umr_bitfield_default },
+	 { "RxEqCtl3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_BIF_LM_POWERCONTROL4[] = {
+	 { "LinkNum0", 0, 2, &umr_bitfield_default },
+	 { "LinkNum1", 3, 5, &umr_bitfield_default },
+	 { "LinkNum2", 6, 8, &umr_bitfield_default },
+	 { "LinkNum3", 9, 11, &umr_bitfield_default },
+	 { "LaneNum0", 12, 15, &umr_bitfield_default },
+	 { "LaneNum1", 16, 19, &umr_bitfield_default },
+	 { "LaneNum2", 20, 23, &umr_bitfield_default },
+	 { "LaneNum3", 24, 27, &umr_bitfield_default },
+	 { "SpcMode0", 28, 28, &umr_bitfield_default },
+	 { "SpcMode1", 29, 29, &umr_bitfield_default },
+	 { "SpcMode2", 30, 30, &umr_bitfield_default },
+	 { "SpcMode3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_ADDR_END_7[] = {
+	 { "ADDR_END", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_FLUSH_REQ[] = {
+	 { "FLUSH_REQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_GARLIC_FLUSH_REQ[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+	 { "SDMA2", 12, 12, &umr_bitfield_default },
+	 { "SDMA3", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_GARLIC_FLUSH_DONE[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+	 { "SDMA2", 12, 12, &umr_bitfield_default },
+	 { "SDMA3", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_RB0_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_RB1_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_RB2_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_UVD_RBC_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SDMA0_GFX_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SDMA1_GFX_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_DMA_ME_COMMAND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_DMA_PFP_COMMAND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SAM_SAB_RBI_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SAM_SAB_RBO_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_VCE_OUT_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_VCE_RB_WPTR2[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_VCE_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SDMA2_GFX_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_SDMA3_GFX_RB_WPTR[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_CP_DMA_PIO_COMMAND[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGARLIC_COHE_GARLIC_FLUSH_REQ[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREMAP_HDP_MEM_FLUSH_CNTL[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREMAP_HDP_REG_FLUSH_CNTL[] = {
+	 { "ADDRESS", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX0_LOWER[] = {
+	 { "VDDGFX_GFX0_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX0_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX0_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX0_UPPER[] = {
+	 { "VDDGFX_GFX0_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX1_LOWER[] = {
+	 { "VDDGFX_GFX1_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX1_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX1_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX1_UPPER[] = {
+	 { "VDDGFX_GFX1_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX2_LOWER[] = {
+	 { "VDDGFX_GFX2_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX2_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX2_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX2_UPPER[] = {
+	 { "VDDGFX_GFX2_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX3_LOWER[] = {
+	 { "VDDGFX_GFX3_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX3_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX3_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX3_UPPER[] = {
+	 { "VDDGFX_GFX3_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX4_LOWER[] = {
+	 { "VDDGFX_GFX4_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX4_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX4_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX4_UPPER[] = {
+	 { "VDDGFX_GFX4_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX5_LOWER[] = {
+	 { "VDDGFX_GFX5_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_GFX5_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_GFX5_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_GFX5_UPPER[] = {
+	 { "VDDGFX_GFX5_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV1_LOWER[] = {
+	 { "VDDGFX_RSV1_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV1_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV1_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV1_UPPER[] = {
+	 { "VDDGFX_RSV1_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV2_LOWER[] = {
+	 { "VDDGFX_RSV2_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV2_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV2_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV2_UPPER[] = {
+	 { "VDDGFX_RSV2_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV3_LOWER[] = {
+	 { "VDDGFX_RSV3_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV3_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV3_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV3_UPPER[] = {
+	 { "VDDGFX_RSV3_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV4_LOWER[] = {
+	 { "VDDGFX_RSV4_REG_LOWER", 2, 17, &umr_bitfield_default },
+	 { "VDDGFX_RSV4_REG_CMP_EN", 30, 30, &umr_bitfield_default },
+	 { "VDDGFX_RSV4_REG_STALL_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_RSV4_UPPER[] = {
+	 { "VDDGFX_RSV4_REG_UPPER", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_VDDGFX_FB_CMP[] = {
+	 { "VDDGFX_FB_HDP_CMP_EN", 0, 0, &umr_bitfield_default },
+	 { "VDDGFX_FB_HDP_STALL_EN", 1, 1, &umr_bitfield_default },
+	 { "VDDGFX_FB_XDMA_CMP_EN", 2, 2, &umr_bitfield_default },
+	 { "VDDGFX_FB_XDMA_STALL_EN", 3, 3, &umr_bitfield_default },
+	 { "VDDGFX_FB_VGA_CMP_EN", 4, 4, &umr_bitfield_default },
+	 { "VDDGFX_FB_VGA_STALL_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SMU_INDEX[] = {
+	 { "BIF_SMU_INDEX", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SMU_DATA[] = {
+	 { "BIF_SMU_DATA", 2, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_SOFTRST_CNTL[] = {
+	 { "REG_RST_rstTimer", 0, 15, &umr_bitfield_default },
+	 { "REG_RST_softRstPropEn", 30, 30, &umr_bitfield_default },
+	 { "SoftRstReg", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[] = {
+	 { "CLIENT0_RFE_RFEWGBIF_rst", 0, 0, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWGBIF_rst", 1, 1, &umr_bitfield_default },
+	 { "CLIENT2_RFE_RFEWGBIF_rst", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MASTER_SOFTRST_TRIGGER[] = {
+	 { "FBU_rst", 0, 0, &umr_bitfield_default },
+	 { "RWREG_RFEWGBIF_rst", 1, 1, &umr_bitfield_default },
+	 { "BX_rst", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PWDN_COMMAND[] = {
+	 { "REG_FBU_pw_cmd", 0, 0, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWGBIF_pw_cmd", 1, 1, &umr_bitfield_default },
+	 { "REG_BX_pw_cmd", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PWDN_STATUS[] = {
+	 { "FBU_REG_pw_status", 0, 0, &umr_bitfield_default },
+	 { "RWREG_RFEWGBIF_REG_pw_status", 1, 1, &umr_bitfield_default },
+	 { "BX_REG_pw_status", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_FBU_CMDSTATUS[] = {
+	 { "REG_FBU_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_FBU_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_FBU_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "FBU_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS[] = {
+	 { "REG_RWREG_RFEWGBIF_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWGBIF_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_RWREG_RFEWGBIF_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "RWREG_RFEWGBIF_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_BX_CMDSTATUS[] = {
+	 { "REG_BX_clkGate_timer", 0, 7, &umr_bitfield_default },
+	 { "REG_BX_clkSetup_timer", 8, 11, &umr_bitfield_default },
+	 { "REG_BX_timeout_timer", 16, 23, &umr_bitfield_default },
+	 { "BX_RFE_mstTimeout", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MST_TMOUT_STATUS[] = {
+	 { "MstTmoutStatus", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_MMCFG_CNTL[] = {
+	 { "CLIENT1_RFE_RFEWGBIF_MM_WR_TO_CFG_EN", 0, 0, &umr_bitfield_default },
+	 { "CLIENT1_RFE_RFEWGBIF_MM_CFG_FUNC_SEL", 1, 3, &umr_bitfield_default },
+	 { "CLIENT2_RFE_RFEWGBIF_MM_WR_TO_CFG_EN", 4, 4, &umr_bitfield_default },
+	 { "CLIENT2_RFE_RFEWGBIF_MM_CFG_FUNC_SEL", 5, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_WARMRST_CNTL[] = {
+	 { "REG_RST_warmRstRfeEn", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_MSIC[] = {
+	 { "BIF_XTALIN_SEL", 0, 0, &umr_bitfield_default },
+	 { "BACO_LINK_RST_SEL", 1, 2, &umr_bitfield_default },
+	 { "ACPI_BACO_MUX_DIS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PIF_TXCLK_SWITCH_TIMER[] = {
+	 { "PLL0_ACK_TIMER", 0, 2, &umr_bitfield_default },
+	 { "PLL1_ACK_TIMER", 3, 5, &umr_bitfield_default },
+	 { "PLL_SWITCH_TIMER", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RESET_EN[] = {
+	 { "SOFT_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "PHY_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "COR_RESET_EN", 3, 3, &umr_bitfield_default },
+	 { "REG_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "STY_RESET_EN", 5, 5, &umr_bitfield_default },
+	 { "CFG_RESET_EN", 6, 6, &umr_bitfield_default },
+	 { "DRV_RESET_EN", 7, 7, &umr_bitfield_default },
+	 { "RESET_CFGREG_ONLY_EN", 8, 8, &umr_bitfield_default },
+	 { "HOT_RESET_EN", 9, 9, &umr_bitfield_default },
+	 { "LINK_DISABLE_RESET_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_DOWN_RESET_EN", 11, 11, &umr_bitfield_default },
+	 { "CFG_RESET_PULSE_WIDTH", 12, 17, &umr_bitfield_default },
+	 { "DRV_RESET_DELAY_SEL", 18, 19, &umr_bitfield_default },
+	 { "PIF_RSTB_EN", 20, 20, &umr_bitfield_default },
+	 { "PIF_STRAP_ALLVALID_EN", 21, 21, &umr_bitfield_default },
+	 { "BIF_COR_RESET_EN", 22, 22, &umr_bitfield_default },
+	 { "FUNC0_FLR_EN", 23, 23, &umr_bitfield_default },
+	 { "FUNC1_FLR_EN", 24, 24, &umr_bitfield_default },
+	 { "FUNC2_FLR_EN", 25, 25, &umr_bitfield_default },
+	 { "FUNC0_RESET_DELAY_SEL", 26, 27, &umr_bitfield_default },
+	 { "FUNC1_RESET_DELAY_SEL", 28, 29, &umr_bitfield_default },
+	 { "FUNC2_RESET_DELAY_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_CLK_PDWN_DELAY_TIMER[] = {
+	 { "TIMER", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmNEW_REFCLKB_TIMER_1[] = {
+	 { "PHY_PLL_PDWN_TIMER", 0, 9, &umr_bitfield_default },
+	 { "PLL0_PDNB_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmNEW_REFCLKB_TIMER[] = {
+	 { "REG_STOP_REFCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "STOP_REFCLK_TIMER", 1, 20, &umr_bitfield_default },
+	 { "REFCLK_ON", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RESET_CNTL[] = {
+	 { "STRAP_EN", 0, 0, &umr_bitfield_default },
+	 { "RST_DONE", 1, 1, &umr_bitfield_default },
+	 { "LINK_TRAIN_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_ALL_VALID", 3, 3, &umr_bitfield_default },
+	 { "RECAP_STRAP_WARMRST", 8, 8, &umr_bitfield_default },
+	 { "HOLD_LKTRN_WARMRST_DIS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLNCNT_CONTROL[] = {
+	 { "LNCNT_ACC_MODE", 0, 0, &umr_bitfield_default },
+	 { "LNCNT_REF_TIMEBASE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_LNCNT_RESET[] = {
+	 { "RESET_LNCNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_CLOCKS_BITS[] = {
+	 { "OBFF_XSL_FORCE_REFCLK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MEM_PG_CNTL[] = {
+	 { "BIF_MEM_SD_EN", 0, 0, &umr_bitfield_default },
+	 { "BIF_MEM_SD_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_CNTL_MISC[] = {
+	 { "ADAPT_pif0_bu_reg_accessMode", 0, 0, &umr_bitfield_default },
+	 { "ADAPT_pif1_bu_reg_accessMode", 1, 1, &umr_bitfield_default },
+	 { "ADAPT_pwreg_bu_reg_accessMode", 2, 2, &umr_bitfield_default },
+	 { "ADAPT_pciecore0_bu_reg_accessMode", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_XDMA_LO[] = {
+	 { "BIF_XDMA_LOWER_BOUND", 0, 28, &umr_bitfield_default },
+	 { "BIF_XDMA_APER_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_XDMA_HI[] = {
+	 { "BIF_XDMA_UPPER_BOUND", 0, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_FEATURES_CONTROL_MISC[] = {
+	 { "MST_BIF_REQ_EP_DIS", 0, 0, &umr_bitfield_default },
+	 { "SLV_BIF_CPL_EP_DIS", 1, 1, &umr_bitfield_default },
+	 { "BIF_SLV_REQ_EP_DIS", 2, 2, &umr_bitfield_default },
+	 { "BIF_MST_CPL_EP_DIS", 3, 3, &umr_bitfield_default },
+	 { "UR_PSN_PKT_REPORT_POISON_DIS", 4, 4, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS", 5, 5, &umr_bitfield_default },
+	 { "POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS", 6, 6, &umr_bitfield_default },
+	 { "PLL_SWITCH_IMPCTL_CAL_DONE_DIS", 7, 7, &umr_bitfield_default },
+	 { "IGNORE_BE_CHECK_GASKET_COMB_DIS", 8, 8, &umr_bitfield_default },
+	 { "MC_BIF_REQ_ID_ROUTING_DIS", 9, 9, &umr_bitfield_default },
+	 { "AZ_BIF_REQ_ID_ROUTING_DIS", 10, 10, &umr_bitfield_default },
+	 { "ATC_PRG_RESP_PASID_UR_EN", 11, 11, &umr_bitfield_default },
+	 { "BIF_RB_SET_OVERFLOW_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_CNTL[] = {
+	 { "SELF_RING_DIS", 0, 0, &umr_bitfield_default },
+	 { "TRANS_CHECK_DIS", 1, 1, &umr_bitfield_default },
+	 { "UNTRANS_LBACK_EN", 2, 2, &umr_bitfield_default },
+	 { "NON_CONSECUTIVE_BE_ZERO_DIS", 3, 3, &umr_bitfield_default },
+	 { "DOORBELL_MONITOR_EN", 4, 4, &umr_bitfield_default },
+	 { "DOORBELL_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default },
+	 { "DOORBELL_INTERRUPT_CLEAR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SLVARB_MODE[] = {
+	 { "SLVARB_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBUS_BACO_DUMMY[] = {
+	 { "SMBUS_BACO_DUMMY_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBF_ANA_ISO_CNTL[] = {
+	 { "BF_ANA_ISO_DIS_MASK", 0, 0, &umr_bitfield_default },
+	 { "BF_VDDC_ISO_DIS_MASK", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBACO_CNTL_MISC[] = {
+	 { "BIF_ROM_REQ_DIS", 0, 0, &umr_bitfield_default },
+	 { "BIF_AZ_REQ_DIS", 1, 1, &umr_bitfield_default },
+	 { "BACO_LINK_RST_WIDTH_SEL", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_DEBUG_LATCH[] = {
+	 { "BIF_BACO_LATCH_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BACO_DEBUG[] = {
+	 { "BIF_BACO_SCANDUMP_FLG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMEM_TYPE_CNTL[] = {
+	 { "BF_MEM_PHY_G5_G3", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBACO_CNTL[] = {
+	 { "BACO_EN", 0, 0, &umr_bitfield_default },
+	 { "BACO_BCLK_OFF", 1, 1, &umr_bitfield_default },
+	 { "BACO_ISO_DIS", 2, 2, &umr_bitfield_default },
+	 { "BACO_POWER_OFF", 3, 3, &umr_bitfield_default },
+	 { "BACO_RESET_EN", 4, 4, &umr_bitfield_default },
+	 { "BACO_HANG_PROTECTION_EN", 5, 5, &umr_bitfield_default },
+	 { "BACO_MODE", 6, 6, &umr_bitfield_default },
+	 { "BACO_ANA_ISO_DIS", 7, 7, &umr_bitfield_default },
+	 { "RCU_BIF_CONFIG_DONE", 8, 8, &umr_bitfield_default },
+	 { "PWRGOOD_BF", 9, 9, &umr_bitfield_default },
+	 { "PWRGOOD_GPIO", 10, 10, &umr_bitfield_default },
+	 { "PWRGOOD_MEM", 11, 11, &umr_bitfield_default },
+	 { "PWRGOOD_DVO", 12, 12, &umr_bitfield_default },
+	 { "PWRGOOD_IDSC", 13, 13, &umr_bitfield_default },
+	 { "BACO_POWER_OFF_DRAM", 16, 16, &umr_bitfield_default },
+	 { "BACO_BF_MEM_PHY_ISO_CNTRL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEVFUNCNUM_LIST1[] = {
+	 { "DEVFUNC_ID4", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID5", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID6", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEVFUNCNUM_LIST0[] = {
+	 { "DEVFUNC_ID0", 0, 7, &umr_bitfield_default },
+	 { "DEVFUNC_ID1", 8, 15, &umr_bitfield_default },
+	 { "DEVFUNC_ID2", 16, 23, &umr_bitfield_default },
+	 { "DEVFUNC_ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDBG_BYPASS_SRBM_ACCESS[] = {
+	 { "DBG_BYPASS_SRBM_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "DBG_APER_AD", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER3_FB_OFFSET_LO[] = {
+	 { "PEER3_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER3_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER3_FB_OFFSET_HI[] = {
+	 { "PEER3_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER2_FB_OFFSET_LO[] = {
+	 { "PEER2_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER2_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER2_FB_OFFSET_HI[] = {
+	 { "PEER2_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER1_FB_OFFSET_LO[] = {
+	 { "PEER1_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER1_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER1_FB_OFFSET_HI[] = {
+	 { "PEER1_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER0_FB_OFFSET_LO[] = {
+	 { "PEER0_FB_OFFSET_LO", 0, 19, &umr_bitfield_default },
+	 { "PEER0_FB_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER0_FB_OFFSET_HI[] = {
+	 { "PEER0_FB_OFFSET_HI", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMPCTL_RESET[] = {
+	 { "IMP_SW_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_BIF_VDDGFX_PWR_STATUS[] = {
+	 { "VDDGFX_GFX_PWR_OFF", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_GBLAPER1_LOWER[] = {
+	 { "DOORBELL_GBLAPER1_LOWER", 2, 11, &umr_bitfield_default },
+	 { "DOORBELL_GBLAPER1_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_GBLAPER1_UPPER[] = {
+	 { "DOORBELL_GBLAPER1_UPPER", 2, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_GBLAPER2_LOWER[] = {
+	 { "DOORBELL_GBLAPER2_LOWER", 2, 11, &umr_bitfield_default },
+	 { "DOORBELL_GBLAPER2_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DOORBELL_GBLAPER2_UPPER[] = {
+	 { "DOORBELL_GBLAPER2_UPPER", 2, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_MM_INDACCESS_CNTL[] = {
+	 { "MM_INDACCESS_DIS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1[] = {
+	 { "STRAP_BIF_AER_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_ECN1P1_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_GEN2_COMPLIANCE", 3, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_EN_DEC_TO_HIDDEN_REG", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_FORCE_MASTER_TIMEOUT_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_TPH_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_MULTI_FUNC_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_2VC_EN", 21, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_ARI_EN", 23, 23, &umr_bitfield_default },
+	 { "STRAP_BIF_TL_ALT_BUF_EN", 28, 28, &umr_bitfield_default },
+	 { "STRAP_BIF_LTR_SUPPORTED", 29, 29, &umr_bitfield_default },
+	 { "STRAP_BIF_OBFF_SUPPORTED", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_PI_CNTL[] = {
+	 { "STRAP_BIF_PI_HW_DEBUG", 3, 12, &umr_bitfield_default },
+	 { "STRAP_PI_PRBS_CLK_ADJ", 13, 14, &umr_bitfield_default },
+	 { "STRAP_RXP_HW_DEBUG", 15, 20, &umr_bitfield_default },
+	 { "STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE[] = {
+	 { "STRAP_BIF_ALWAYS_USE_FAST_TXCLK", 1, 1, &umr_bitfield_default },
+	 { "STRAP_PLL_CMP_FREQ_MODE", 2, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FORCE_GEN2_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE[] = {
+	 { "STRAP_BIF_FORCE_GEN3_MODE", 10, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_GEN3_COMPLIANCE", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_ECRC_GEN_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_ECRC_CHECK_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL", 15, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE[] = {
+	 { "STRAP_BIF_RX_IGNORE_IO_ERR", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_BE_ERR", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_MSG_ERR", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_CFG_ERR", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_CPL_ERR", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_EP_ERR", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_TC_ERR", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_AT_ERR", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_ERR_REPORTING_DIS", 16, 16, &umr_bitfield_default },
+	 { "STRAP_BIF_CPL_ABORT_ERR_EN", 17, 17, &umr_bitfield_default },
+	 { "STRAP_BIF_INTERNAL_ERR_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_TEST_DFT[] = {
+	 { "STRAP_BIF_FORCE_CDR_MODE", 26, 26, &umr_bitfield_default },
+	 { "STRAP_BIF_TX_TEST_ALL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_INT_CNTL[] = {
+	 { "INT_LINKAUTONOMOUSBWINT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_ACS[] = {
+	 { "STRAP_BIF_ACS_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_ACS_SOURCE_VALIDATION", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_ACS_TRANSLATION_BLOCKING", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2[] = {
+	 { "STRAP_BIF_KILL_GEN3", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_STRAP_F0_ATOMIC_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_MSI_MULTI_CAP", 4, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_SSID[] = {
+	 { "STRAP_BIF_SUBSYS_VEN_ID", 0, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_SUBSYS_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL[] = {
+	 { "STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT", 0, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT", 3, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET", 6, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_LINK_CONFIG[] = {
+	 { "STRAP_BIF_LINK_CONFIG", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_HOLD_TRAINING_A[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_ASPM_A[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_MISC_PORT_A[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_PORT_IS_SB_A[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_HOLD_TRAINING_B[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_ASPM_B[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_MISC_PORT_B[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_PORT_IS_SB_B[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_HOLD_TRAINING_C[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_ASPM_C[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_MISC_PORT_C[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_PORT_IS_SB_C[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_HOLD_TRAINING_D[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_ASPM_D[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_MISC_PORT_D[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_PORT_IS_SB_D[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_HOLD_TRAINING_E[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_ASPM_E[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_MISC_PORT_E[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_PORT_IS_SB_E[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBUS_CNTL[] = {
+	 { "BIOS_ROM_WRT_EN", 0, 0, &umr_bitfield_default },
+	 { "BIOS_ROM_DIS", 1, 1, &umr_bitfield_default },
+	 { "PMI_IO_DIS", 2, 2, &umr_bitfield_default },
+	 { "PMI_MEM_DIS", 3, 3, &umr_bitfield_default },
+	 { "PMI_BM_DIS", 4, 4, &umr_bitfield_default },
+	 { "PMI_INT_DIS", 5, 5, &umr_bitfield_default },
+	 { "VGA_REG_COHERENCY_DIS", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_COHERENCY_DIS", 7, 7, &umr_bitfield_default },
+	 { "BIF_ERR_RTR_BKPRESSURE_EN", 8, 8, &umr_bitfield_default },
+	 { "SET_AZ_TC", 10, 12, &umr_bitfield_default },
+	 { "SET_MC_TC", 13, 15, &umr_bitfield_default },
+	 { "ZERO_BE_WR_EN", 16, 16, &umr_bitfield_default },
+	 { "ZERO_BE_RD_EN", 17, 17, &umr_bitfield_default },
+	 { "RD_STALL_IO_WR", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_LNCNT_CONTROL[] = {
+	 { "CFG_LNC_WINDOW_EN0", 0, 0, &umr_bitfield_default },
+	 { "CFG_LNC_BW_CNT_EN1", 1, 1, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_CNT_EN2", 2, 2, &umr_bitfield_default },
+	 { "CFG_LNC_OVRD_EN3", 3, 3, &umr_bitfield_default },
+	 { "CFG_LNC_OVRD_VAL4", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_CFG_LNC_WINDOW[] = {
+	 { "CFG_LNC_WINDOW0", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_LNCNT_QUAN_THRD[] = {
+	 { "CFG_LNC_BW_QUAN_THRD0", 0, 2, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_QUAN_THRD4", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_LNCNT_WEIGHT[] = {
+	 { "CFG_LNC_BW_WEIGHT0", 0, 15, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_WEIGHT16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_LNC_TOTAL_WACC[] = {
+	 { "LNC_TOTAL_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_LNC_BW_WACC[] = {
+	 { "LNC_BW_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_LNC_CMN_WACC[] = {
+	 { "LNC_CMN_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_CNTL[] = {
+	 { "CFG_VGA_RAM_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_DIS", 1, 1, &umr_bitfield_default },
+	 { "GENMO_MONO_ADDRESS_B", 2, 2, &umr_bitfield_default },
+	 { "GRPH_ADRSEL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_MEMSIZE[] = {
+	 { "CONFIG_MEMSIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_F0_BASE[] = {
+	 { "F0_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_APER_SIZE[] = {
+	 { "APER_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCONFIG_REG_APER_SIZE[] = {
+	 { "REG_APER_SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SCRATCH0[] = {
+	 { "BIF_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_SCRATCH1[] = {
+	 { "BIF_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_EFUSE[] = {
+	 { "PCIE_EFUSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_EFUSE2[] = {
+	 { "PCIE_EFUSE2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_EFUSE3[] = {
+	 { "PCIE_EFUSE3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_EFUSE4[] = {
+	 { "PCIE_EFUSE4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_EFUSE5[] = {
+	 { "PCIE_EFUSE5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_EFUSE6[] = {
+	 { "PCIE_EFUSE6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX80_WRP_PCIE_EFUSE7[] = {
+	 { "PCIE_EFUSE7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1[] = {
+	 { "STRAP_BIF_AER_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_ECN1P1_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_GEN2_COMPLIANCE", 3, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_EN_DEC_TO_HIDDEN_REG", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_FORCE_MASTER_TIMEOUT_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_TPH_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_MULTI_FUNC_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_2VC_EN", 21, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_ARI_EN", 23, 23, &umr_bitfield_default },
+	 { "STRAP_BIF_TL_ALT_BUF_EN", 28, 28, &umr_bitfield_default },
+	 { "STRAP_BIF_LTR_SUPPORTED", 29, 29, &umr_bitfield_default },
+	 { "STRAP_BIF_OBFF_SUPPORTED", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_PI_CNTL[] = {
+	 { "STRAP_BIF_PI_HW_DEBUG", 3, 12, &umr_bitfield_default },
+	 { "STRAP_PI_PRBS_CLK_ADJ", 13, 14, &umr_bitfield_default },
+	 { "STRAP_RXP_HW_DEBUG", 15, 20, &umr_bitfield_default },
+	 { "STRAP_PI_PREP_ELASTDESKEW_FOR_PRBS", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE[] = {
+	 { "STRAP_BIF_ALWAYS_USE_FAST_TXCLK", 1, 1, &umr_bitfield_default },
+	 { "STRAP_PLL_CMP_FREQ_MODE", 2, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FORCE_GEN2_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE[] = {
+	 { "STRAP_BIF_FORCE_GEN3_MODE", 10, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_GEN3_COMPLIANCE", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_ECRC_GEN_EN", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_ECRC_CHECK_EN", 14, 14, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL", 15, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE[] = {
+	 { "STRAP_BIF_RX_IGNORE_IO_ERR", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_BE_ERR", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_MSG_ERR", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_CFG_ERR", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_CPL_ERR", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_EP_ERR", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_LEN_MISMATCH_ERR", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_TC_ERR", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_RX_IGNORE_AT_ERR", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_ERR_REPORTING_DIS", 16, 16, &umr_bitfield_default },
+	 { "STRAP_BIF_CPL_ABORT_ERR_EN", 17, 17, &umr_bitfield_default },
+	 { "STRAP_BIF_INTERNAL_ERR_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_TEST_DFT[] = {
+	 { "STRAP_BIF_FORCE_CDR_MODE", 26, 26, &umr_bitfield_default },
+	 { "STRAP_BIF_TX_TEST_ALL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_INT_CNTL[] = {
+	 { "INT_LINKAUTONOMOUSBWINT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_ACS[] = {
+	 { "STRAP_BIF_ACS_EN", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_ACS_SOURCE_VALIDATION", 1, 1, &umr_bitfield_default },
+	 { "STRAP_BIF_ACS_TRANSLATION_BLOCKING", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2[] = {
+	 { "STRAP_BIF_KILL_GEN3", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_STRAP_F0_ATOMIC_EN", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_STRAP_F0_ATOMIC_ROUTING_EN", 3, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_MSI_MULTI_CAP", 4, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_STRAP_F0_NO_RO_ENABLED_P2P_PASSING", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_ENABLE_LEGACY_DEBUG_BUS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_SSID[] = {
+	 { "STRAP_BIF_SUBSYS_VEN_ID", 0, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_SUBSYS_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL[] = {
+	 { "STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT", 0, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT", 3, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET", 6, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_LINK_CONFIG[] = {
+	 { "STRAP_BIF_LINK_CONFIG", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_HOLD_TRAINING_A[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_ASPM_A[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_MISC_PORT_A[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_PORT_IS_SB_A[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_HOLD_TRAINING_B[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_ASPM_B[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_MISC_PORT_B[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_PORT_IS_SB_B[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_HOLD_TRAINING_C[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_ASPM_C[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_MISC_PORT_C[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_PORT_IS_SB_C[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_HOLD_TRAINING_D[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_ASPM_D[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_MISC_PORT_D[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_PORT_IS_SB_D[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_HOLD_TRAINING_E[] = {
+	 { "HOLD_TRAINING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E[] = {
+	 { "STRAP_BIF_AUTO_RC_SPEED_NEGOTIATION_DIS", 2, 2, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_TARGET_LINK_SPEED_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_BYPASS_EQ_REQ_PHASE", 8, 8, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_SEARCH_MODE", 9, 10, &umr_bitfield_default },
+	 { "STRAP_BIF_TARGET_LINK_SPEED", 12, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_FS", 16, 21, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_EQ_LF", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_ASPM_E[] = {
+	 { "STRAP_BIF_PM_SUPPORT", 14, 15, &umr_bitfield_default },
+	 { "STRAP_BIF_L1_EXIT_LATENCY", 16, 18, &umr_bitfield_default },
+	 { "STRAP_BIF_L0S_EXIT_LATENCY", 19, 21, &umr_bitfield_default },
+	 { "STRAP_ENABLE_SIGNAL_EXIT_L1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E[] = {
+	 { "STRAP_BIF_DE_EMPHASIS_SEL", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 11, 11, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_2P5GT", 12, 12, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_5GT", 13, 13, &umr_bitfield_default },
+	 { "STRAP_BIF_LC_SPC_MODE_8GT", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_MISC_PORT_E[] = {
+	 { "STRAP_BIF_POISONED_ADVISORY_NONFATAL", 0, 0, &umr_bitfield_default },
+	 { "STRAP_BIF_MAX_PAYLOAD_SUPPORT", 1, 3, &umr_bitfield_default },
+	 { "STRAP_BIF_FIRST_RCVD_ERR_LOG", 4, 4, &umr_bitfield_default },
+	 { "STRAP_BIF_EXTENDED_FMT_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "STRAP_BIF_E2E_PREFIX_EN", 6, 6, &umr_bitfield_default },
+	 { "STRAP_BIF_BCH_ECC_EN", 7, 7, &umr_bitfield_default },
+	 { "STRAP_BIF_MC_ECRC_REGEN_SUPP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E[] = {
+	 { "STRAP_BIF_LC_ENHANCED_HOT_PLUG_EN", 9, 9, &umr_bitfield_default },
+	 { "STRAP_BIF_INITIAL_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_PORT_IS_SB_E[] = {
+	 { "PORT_IS_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_CFGREGS_CNTL[] = {
+	 { "MM_CFG_FUNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "MM_WR_TO_CFG_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBX_RESET_EN[] = {
+	 { "COR_RESET_EN", 0, 0, &umr_bitfield_default },
+	 { "REG_RESET_EN", 1, 1, &umr_bitfield_default },
+	 { "STY_RESET_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+	 { "HW_16_DEBUG", 16, 16, &umr_bitfield_default },
+	 { "HW_17_DEBUG", 17, 17, &umr_bitfield_default },
+	 { "HW_18_DEBUG", 18, 18, &umr_bitfield_default },
+	 { "HW_19_DEBUG", 19, 19, &umr_bitfield_default },
+	 { "HW_20_DEBUG", 20, 20, &umr_bitfield_default },
+	 { "HW_21_DEBUG", 21, 21, &umr_bitfield_default },
+	 { "HW_22_DEBUG", 22, 22, &umr_bitfield_default },
+	 { "HW_23_DEBUG", 23, 23, &umr_bitfield_default },
+	 { "HW_24_DEBUG", 24, 24, &umr_bitfield_default },
+	 { "HW_25_DEBUG", 25, 25, &umr_bitfield_default },
+	 { "HW_26_DEBUG", 26, 26, &umr_bitfield_default },
+	 { "HW_27_DEBUG", 27, 27, &umr_bitfield_default },
+	 { "HW_28_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "HW_29_DEBUG", 29, 29, &umr_bitfield_default },
+	 { "HW_30_DEBUG", 30, 30, &umr_bitfield_default },
+	 { "HW_31_DEBUG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_CREDIT_CNTL[] = {
+	 { "BIF_MC_RDRET_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "BIF_AZ_RDRET_CREDIT", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_REQ_CREDIT_CNTL[] = {
+	 { "BIF_SRBM_REQ_CREDIT", 0, 4, &umr_bitfield_default },
+	 { "BIF_VGA_REQ_CREDIT", 5, 8, &umr_bitfield_default },
+	 { "BIF_HDP_REQ_CREDIT", 10, 14, &umr_bitfield_default },
+	 { "BIF_ROM_REQ_CREDIT", 15, 15, &umr_bitfield_default },
+	 { "BIF_AZ_REQ_CREDIT", 20, 20, &umr_bitfield_default },
+	 { "BIF_XDMA_REQ_CREDIT", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBX_RESET_CNTL[] = {
+	 { "LINK_TRAIN_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_LNCNT_CONTROL[] = {
+	 { "CFG_LNC_WINDOW_EN0", 0, 0, &umr_bitfield_default },
+	 { "CFG_LNC_BW_CNT_EN1", 1, 1, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_CNT_EN2", 2, 2, &umr_bitfield_default },
+	 { "CFG_LNC_OVRD_EN3", 3, 3, &umr_bitfield_default },
+	 { "CFG_LNC_OVRD_VAL4", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_CFG_LNC_WINDOW[] = {
+	 { "CFG_LNC_WINDOW0", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_LNCNT_QUAN_THRD[] = {
+	 { "CFG_LNC_BW_QUAN_THRD0", 0, 2, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_QUAN_THRD4", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_LNCNT_WEIGHT[] = {
+	 { "CFG_LNC_BW_WEIGHT0", 0, 15, &umr_bitfield_default },
+	 { "CFG_LNC_CMN_WEIGHT16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_LNC_TOTAL_WACC[] = {
+	 { "LNC_TOTAL_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_LNC_BW_WACC[] = {
+	 { "LNC_BW_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_LNC_CMN_WACC[] = {
+	 { "LNC_CMN_WACC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CNTL[] = {
+	 { "IH_DUMMY_RD_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "IH_DUMMY_RD_EN", 1, 1, &umr_bitfield_default },
+	 { "IH_REQ_NONSNOOP_EN", 3, 3, &umr_bitfield_default },
+	 { "IH_INTR_DLY_CNTR", 4, 7, &umr_bitfield_default },
+	 { "GEN_IH_INT_EN", 8, 8, &umr_bitfield_default },
+	 { "GEN_GPIO_INT_EN", 9, 12, &umr_bitfield_default },
+	 { "SELECT_INT_GPIO_OUTPUT", 13, 14, &umr_bitfield_default },
+	 { "BIF_RB_REQ_NONSNOOP_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CNTL2[] = {
+	 { "IH_DUMMY_RD_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_CNTL[] = {
+	 { "DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_MULTIBLOCKEN", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "DEBUG_PAD_SEL", 3, 3, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK1", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_BYTESEL_BLK2", 5, 5, &umr_bitfield_default },
+	 { "DEBUG_SYNC_EN", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_SWAP", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK1", 8, 12, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_BLK2", 16, 20, &umr_bitfield_default },
+	 { "DEBUG_IDSEL_XSP", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_SYNC_CLKSEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_MUX[] = {
+	 { "DEBUG_MUX_BLK1", 0, 5, &umr_bitfield_default },
+	 { "DEBUG_MUX_BLK2", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_DEBUG_OUT[] = {
+	 { "DEBUG_OUTPUT", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_EFUSE[] = {
+	 { "PCIE_EFUSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_EFUSE2[] = {
+	 { "PCIE_EFUSE2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_EFUSE3[] = {
+	 { "PCIE_EFUSE3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_EFUSE4[] = {
+	 { "PCIE_EFUSE4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_EFUSE5[] = {
+	 { "PCIE_EFUSE5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_EFUSE6[] = {
+	 { "PCIE_EFUSE6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPSX81_WRP_PCIE_EFUSE7[] = {
+	 { "PCIE_EFUSE7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEM_COHERENCY_FLUSH_CNTL[] = {
+	 { "HDP_MEM_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCLKREQB_PAD_CNTL[] = {
+	 { "CLKREQB_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "CLKREQB_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "CLKREQB_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "CLKREQB_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "CLKREQB_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBDAT_PAD_CNTL[] = {
+	 { "SMBDAT_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "SMBDAT_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "SMBDAT_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "SMBDAT_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "SMBDAT_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMBCLK_PAD_CNTL[] = {
+	 { "SMBCLK_PAD_A", 0, 0, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SEL", 1, 1, &umr_bitfield_default },
+	 { "SMBCLK_PAD_MODE", 2, 2, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SPARE", 3, 4, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN0", 5, 5, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN1", 6, 6, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN2", 7, 7, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SN3", 8, 8, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SLEWN", 9, 9, &umr_bitfield_default },
+	 { "SMBCLK_PAD_WAKE", 10, 10, &umr_bitfield_default },
+	 { "SMBCLK_PAD_SCHMEN", 11, 11, &umr_bitfield_default },
+	 { "SMBCLK_PAD_CNTL_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_FB_EN[] = {
+	 { "FB_READ_EN", 0, 0, &umr_bitfield_default },
+	 { "FB_WRITE_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_CNTL1[] = {
+	 { "ID_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_LIST0[] = {
+	 { "ID0", 0, 7, &umr_bitfield_default },
+	 { "ID1", 8, 15, &umr_bitfield_default },
+	 { "ID2", 16, 23, &umr_bitfield_default },
+	 { "ID3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_LIST1[] = {
+	 { "ID4", 0, 7, &umr_bitfield_default },
+	 { "ID5", 8, 15, &umr_bitfield_default },
+	 { "ID6", 16, 23, &umr_bitfield_default },
+	 { "ID7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_REG_COHERENCY_FLUSH_CNTL[] = {
+	 { "HDP_REG_FLUSH_ADDR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSY_DELAY_CNTR[] = {
+	 { "DELAY_CNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_BUSNUM_CNTL2[] = {
+	 { "AUTOUPDATE_SEL", 0, 7, &umr_bitfield_default },
+	 { "AUTOUPDATE_EN", 8, 8, &umr_bitfield_default },
+	 { "HDPREG_CNTL", 16, 16, &umr_bitfield_default },
+	 { "ERROR_MULTIPLE_ID_MATCH", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFMON_CNTL[] = {
+	 { "PERFCOUNTER_EN", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET0", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESET1", 2, 2, &umr_bitfield_default },
+	 { "PERF_SEL0", 8, 12, &umr_bitfield_default },
+	 { "PERF_SEL1", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFCOUNTER0_RESULT[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_PERFCOUNTER1_RESULT[] = {
+	 { "PERFCOUNTER_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_TIMER", 9, 13, &umr_bitfield_default },
+	 { "BIF_RB_TRAN", 17, 17, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_RPTR[] = {
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_WPTR[] = {
+	 { "BIF_RB_OVERFLOW", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_WPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RB_WPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_HANG_PROTECTION_CNTL[] = {
+	 { "HANG_PROTECTION_TIMER_SEL", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_HDP_FLUSH_REQ[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_HDP_FLUSH_DONE[] = {
+	 { "CP0", 0, 0, &umr_bitfield_default },
+	 { "CP1", 1, 1, &umr_bitfield_default },
+	 { "CP2", 2, 2, &umr_bitfield_default },
+	 { "CP3", 3, 3, &umr_bitfield_default },
+	 { "CP4", 4, 4, &umr_bitfield_default },
+	 { "CP5", 5, 5, &umr_bitfield_default },
+	 { "CP6", 6, 6, &umr_bitfield_default },
+	 { "CP7", 7, 7, &umr_bitfield_default },
+	 { "CP8", 8, 8, &umr_bitfield_default },
+	 { "CP9", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_HANG_ERROR[] = {
+	 { "SRBM_HANG_ERROR", 0, 0, &umr_bitfield_default },
+	 { "HDP_HANG_ERROR", 1, 1, &umr_bitfield_default },
+	 { "VGA_HANG_ERROR", 2, 2, &umr_bitfield_default },
+	 { "ROM_HANG_ERROR", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_HANG_ERROR", 4, 4, &umr_bitfield_default },
+	 { "CEC_HANG_ERROR", 5, 5, &umr_bitfield_default },
+	 { "XDMA_HANG_ERROR", 7, 7, &umr_bitfield_default },
+	 { "DOORBELL_HANG_ERROR", 8, 8, &umr_bitfield_default },
+	 { "GARLIC_HANG_ERROR", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCAPTURE_HOST_BUSNUM[] = {
+	 { "CHECK_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHOST_BUSNUM[] = {
+	 { "HOST_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER_REG_RANGE0[] = {
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPEER_REG_RANGE1[] = {
+	 { "START_ADDR", 0, 15, &umr_bitfield_default },
+	 { "END_ADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CAP[] = {
+	 { "VERSION", 0, 3, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 4, 7, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 8, 8, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 9, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_STATUS[] = {
+	 { "CORR_ERR", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR", 2, 2, &umr_bitfield_default },
+	 { "USR_DETECTED", 3, 3, &umr_bitfield_default },
+	 { "AUX_PWR", 4, 4, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "INITIATE_FLR", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "LINK_TRAINING", 11, 11, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 12, 12, &umr_bitfield_default },
+	 { "DL_ACTIVE", 13, 13, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_HW_DEBUG[] = {
+	 { "HW_00_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "HW_01_DEBUG", 1, 1, &umr_bitfield_default },
+	 { "HW_02_DEBUG", 2, 2, &umr_bitfield_default },
+	 { "HW_03_DEBUG", 3, 3, &umr_bitfield_default },
+	 { "HW_04_DEBUG", 4, 4, &umr_bitfield_default },
+	 { "HW_05_DEBUG", 5, 5, &umr_bitfield_default },
+	 { "HW_06_DEBUG", 6, 6, &umr_bitfield_default },
+	 { "HW_07_DEBUG", 7, 7, &umr_bitfield_default },
+	 { "HW_08_DEBUG", 8, 8, &umr_bitfield_default },
+	 { "HW_09_DEBUG", 9, 9, &umr_bitfield_default },
+	 { "HW_10_DEBUG", 10, 10, &umr_bitfield_default },
+	 { "HW_11_DEBUG", 11, 11, &umr_bitfield_default },
+	 { "HW_12_DEBUG", 12, 12, &umr_bitfield_default },
+	 { "HW_13_DEBUG", 13, 13, &umr_bitfield_default },
+	 { "HW_14_DEBUG", 14, 14, &umr_bitfield_default },
+	 { "HW_15_DEBUG", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_CLASS[] = {
+	 { "BASE_CLASS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSUB_CLASS[] = {
+	 { "SUB_CLASS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CNTL[] = {
+	 { "TX_SNR_OVERRIDE", 10, 11, &umr_bitfield_default },
+	 { "TX_RO_OVERRIDE", 12, 13, &umr_bitfield_default },
+	 { "TX_PACK_PACKET_DIS", 14, 14, &umr_bitfield_default },
+	 { "TX_FLUSH_TLP_DIS", 15, 15, &umr_bitfield_default },
+	 { "TX_CPL_PASS_P", 20, 20, &umr_bitfield_default },
+	 { "TX_NP_PASS_P", 21, 21, &umr_bitfield_default },
+	 { "TX_CLEAR_EXTRA_PM_REQS", 22, 22, &umr_bitfield_default },
+	 { "TX_FC_UPDATE_TIMEOUT_DIS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_STATUS2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_REQUESTER_ID[] = {
+	 { "TX_REQUESTER_ID_FUNCTION", 0, 2, &umr_bitfield_default },
+	 { "TX_REQUESTER_ID_DEVICE", 3, 7, &umr_bitfield_default },
+	 { "TX_REQUESTER_ID_BUS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_VENDOR_SPECIFIC[] = {
+	 { "TX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 0, 0, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 1, 1, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 2, 2, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 3, 3, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 4, 4, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_REQUEST_NUM_CNTL[] = {
+	 { "TX_NUM_OUTSTANDING_NP", 24, 29, &umr_bitfield_default },
+	 { "TX_NUM_OUTSTANDING_NP_VC1_EN", 30, 30, &umr_bitfield_default },
+	 { "TX_NUM_OUTSTANDING_NP_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_SEQ[] = {
+	 { "TX_NEXT_TRANSMIT_SEQ", 0, 11, &umr_bitfield_default },
+	 { "TX_ACKD_SEQ", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_REPLAY[] = {
+	 { "TX_REPLAY_NUM", 0, 2, &umr_bitfield_default },
+	 { "TX_REPLAY_TIMER_OVERWRITE", 15, 15, &umr_bitfield_default },
+	 { "TX_REPLAY_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT[] = {
+	 { "TX_ACK_LATENCY_LIMIT", 0, 11, &umr_bitfield_default },
+	 { "TX_ACK_LATENCY_LIMIT_OVERWRITE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIF_RFE_SNOOP_REG[] = {
+	 { "REG_SNOOP_ARBITER", 0, 0, &umr_bitfield_default },
+	 { "REG_SNOOP_ALLMASTER", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmC_PCIE_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLATENCY[] = {
+	 { "LATENCY_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHEADER[] = {
+	 { "HEADER_TYPE", 0, 6, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIST[] = {
+	 { "BIST_COMP", 0, 3, &umr_bitfield_default },
+	 { "BIST_STRT", 6, 6, &umr_bitfield_default },
+	 { "BIST_CAP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CREDITS_ADVT_P[] = {
+	 { "TX_CREDITS_ADVT_PD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F2_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CREDITS_ADVT_NP[] = {
+	 { "TX_CREDITS_ADVT_NPD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CREDITS_ADVT_CPL[] = {
+	 { "TX_CREDITS_ADVT_CPLD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_ADVT_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CREDITS_INIT_P[] = {
+	 { "TX_CREDITS_INIT_PD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CREDITS_INIT_NP[] = {
+	 { "TX_CREDITS_INIT_NPD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmNB_GBIF_INDEX[] = {
+	 { "NB_GBIF_IND_ADDR", 0, 31, &umr_bitfield_default },
+	 { "NB_GBIF_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CREDITS_INIT_CPL[] = {
+	 { "TX_CREDITS_INIT_CPLD", 0, 11, &umr_bitfield_default },
+	 { "TX_CREDITS_INIT_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmNB_GBIF_DATA[] = {
+	 { "NB_GBIF_DATA", 0, 31, &umr_bitfield_default },
+	 { "NB_GBIF_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CREDITS_STATUS[] = {
+	 { "TX_CREDITS_ERR_PD", 0, 0, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_PH", 1, 1, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_NPD", 2, 2, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_NPH", 3, 3, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_CPLD", 4, 4, &umr_bitfield_default },
+	 { "TX_CREDITS_ERR_CPLH", 5, 5, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_PD", 16, 16, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_PH", 17, 17, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_NPD", 18, 18, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_NPH", 19, 19, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_CPLD", 20, 20, &umr_bitfield_default },
+	 { "TX_CREDITS_CUR_STATUS_CPLH", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD[] = {
+	 { "TX_FCU_THRESHOLD_P_VC0", 0, 2, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_NP_VC0", 4, 6, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_CPL_VC0", 8, 10, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_P_VC1", 16, 18, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_NP_VC1", 20, 22, &umr_bitfield_default },
+	 { "TX_FCU_THRESHOLD_CPL_VC1", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmC_PCIE_P_INDEX[] = {
+	 { "PCIE_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmC_PCIE_P_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_1[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F3_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_2[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_P_PORT_LANE_STATUS[] = {
+	 { "PORT_LANE_REVERSAL", 0, 0, &umr_bitfield_default },
+	 { "PHY_LINK_WIDTH", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F4_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_0[] = {
+	 { "BIOS_SCRATCH_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_1[] = {
+	 { "BIOS_SCRATCH_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_2[] = {
+	 { "BIOS_SCRATCH_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_3[] = {
+	 { "BIOS_SCRATCH_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_4[] = {
+	 { "BIOS_SCRATCH_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_5[] = {
+	 { "BIOS_SCRATCH_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_6[] = {
+	 { "BIOS_SCRATCH_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_7[] = {
+	 { "BIOS_SCRATCH_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_8[] = {
+	 { "BIOS_SCRATCH_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_9[] = {
+	 { "BIOS_SCRATCH_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_10[] = {
+	 { "BIOS_SCRATCH_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_11[] = {
+	 { "BIOS_SCRATCH_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_12[] = {
+	 { "BIOS_SCRATCH_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_13[] = {
+	 { "BIOS_SCRATCH_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_14[] = {
+	 { "BIOS_SCRATCH_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBIOS_SCRATCH_15[] = {
+	 { "BIOS_SCRATCH_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMM_INDEX_HI[] = {
+	 { "MM_OFFSET_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_FC_P[] = {
+	 { "PD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "PH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F5_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_FC_NP[] = {
+	 { "NPD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "NPH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_FC_CPL[] = {
+	 { "CPLD_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "CPLH_CREDITS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_ERR_CNTL[] = {
+	 { "ERR_REPORTING_DIS", 0, 0, &umr_bitfield_default },
+	 { "STRAP_FIRST_RCVD_ERR_LOG", 1, 1, &umr_bitfield_default },
+	 { "RX_DROP_ECRC_FAILURES", 2, 2, &umr_bitfield_default },
+	 { "TX_GENERATE_LCRC_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_GENERATE_LCRC_ERR", 5, 5, &umr_bitfield_default },
+	 { "TX_GENERATE_ECRC_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_GENERATE_ECRC_ERR", 7, 7, &umr_bitfield_default },
+	 { "AER_HDR_LOG_TIMEOUT", 8, 10, &umr_bitfield_default },
+	 { "AER_HDR_LOG_F0_TIMER_EXPIRED", 11, 11, &umr_bitfield_default },
+	 { "CI_P_SLV_BUF_RD_HALT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CI_NP_SLV_BUF_RD_HALT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "CI_SLV_BUF_HALT_RESET", 16, 16, &umr_bitfield_default },
+	 { "SEND_ERR_MSG_IMMEDIATELY", 17, 17, &umr_bitfield_default },
+	 { "STRAP_POISONED_ADVISORY_NONFATAL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_4[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_RX_CNTL[] = {
+	 { "RX_IGNORE_IO_ERR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_BE_ERR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_MSG_ERR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_CRC_ERR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_ERR", 4, 4, &umr_bitfield_default },
+	 { "RX_IGNORE_CPL_ERR", 5, 5, &umr_bitfield_default },
+	 { "RX_IGNORE_EP_ERR", 6, 6, &umr_bitfield_default },
+	 { "RX_IGNORE_LEN_MISMATCH_ERR", 7, 7, &umr_bitfield_default },
+	 { "RX_IGNORE_MAX_PAYLOAD_ERR", 8, 8, &umr_bitfield_default },
+	 { "RX_IGNORE_TC_ERR", 9, 9, &umr_bitfield_default },
+	 { "RX_IGNORE_CFG_UR", 10, 10, &umr_bitfield_default },
+	 { "RX_IGNORE_IO_UR", 11, 11, &umr_bitfield_default },
+	 { "RX_IGNORE_AT_ERR", 12, 12, &umr_bitfield_default },
+	 { "RX_NAK_IF_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "RX_GEN_ONE_NAK", 14, 14, &umr_bitfield_default },
+	 { "RX_FC_INIT_FROM_REG", 15, 15, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT", 16, 18, &umr_bitfield_default },
+	 { "RX_RCB_CPL_TIMEOUT_MODE", 19, 19, &umr_bitfield_default },
+	 { "RX_PCIE_CPL_TIMEOUT_DIS", 20, 20, &umr_bitfield_default },
+	 { "RX_IGNORE_SHORTPREFIX_ERR", 21, 21, &umr_bitfield_default },
+	 { "RX_IGNORE_MAXPREFIX_ERR", 22, 22, &umr_bitfield_default },
+	 { "RX_IGNORE_CPLPREFIX_ERR", 23, 23, &umr_bitfield_default },
+	 { "RX_IGNORE_INVALIDPASID_ERR", 24, 24, &umr_bitfield_default },
+	 { "RX_IGNORE_NOT_PASID_UR", 25, 25, &umr_bitfield_default },
+	 { "RX_TPH_DIS", 26, 26, &umr_bitfield_default },
+	 { "RX_RCB_FLR_TIMEOUT_DIS", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F1_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_RX_EXPECTED_SEQNUM[] = {
+	 { "RX_EXPECTED_SEQNUM", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_RX_VENDOR_SPECIFIC[] = {
+	 { "RX_VENDOR_DATA", 0, 23, &umr_bitfield_default },
+	 { "RX_VENDOR_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_RX_CNTL3[] = {
+	 { "RX_IGNORE_RC_TRANSMRDPASID_UR", 0, 0, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_TRANSMWRPASID_UR", 1, 1, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_PRGRESPMSG_UR", 2, 2, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVREQ_UR", 3, 3, &umr_bitfield_default },
+	 { "RX_IGNORE_RC_INVCPLPASID_UR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_5[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P[] = {
+	 { "RX_CREDITS_ALLOCATED_PD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_PH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F2_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP[] = {
+	 { "RX_CREDITS_ALLOCATED_NPD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_NPH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR1_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL[] = {
+	 { "RX_CREDITS_ALLOCATED_CPLD", 0, 11, &umr_bitfield_default },
+	 { "RX_CREDITS_ALLOCATED_CPLH", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR1_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL[] = {
+	 { "ERROR_INJECT_PL_LANE_ERR", 0, 1, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_FRAMING_ERR", 2, 3, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_BAD_PARITY_IN_SKP", 4, 5, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_BAD_LFSR_IN_SKP", 6, 7, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_LOOPBACK_UFLOW", 8, 9, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_LOOPBACK_OFLOW", 10, 11, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_DESKEW_ERR", 12, 13, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_8B10B_DISPARITY_ERR", 14, 15, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_8B10B_DECODE_ERR", 16, 17, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_SKP_OS_ERROR", 18, 19, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_INV_OS_IDENTIFIER", 20, 21, &umr_bitfield_default },
+	 { "ERROR_INJECT_PL_BAD_SYNC_HEADER", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR2_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION[] = {
+	 { "ERROR_INJECT_TL_FLOW_CTL_ERR", 0, 1, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_REPLAY_NUM_ROLLOVER", 2, 3, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_BAD_DLLP", 4, 5, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_BAD_TLP", 6, 7, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_UNSUPPORTED_REQ", 8, 9, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_ECRC_ERROR", 10, 11, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_MALFORMED_TLP", 12, 13, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_UNEXPECTED_CMPLT", 14, 15, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_COMPLETER_ABORT", 16, 17, &umr_bitfield_default },
+	 { "ERROR_INJECT_TL_COMPLETION_TIMEOUT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR2_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR3_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR3_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR4_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR4_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR5_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR5_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR6_CAP[] = {
+	 { "BAR_SIZE_SUPPORTED", 4, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_BAR6_CNTL[] = {
+	 { "BAR_INDEX", 0, 2, &umr_bitfield_default },
+	 { "BAR_TOTAL_NUM", 5, 7, &umr_bitfield_default },
+	 { "BAR_SIZE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBASE_ADDR_6[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F3_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_DATA_SELECT[] = {
+	 { "DATA_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_DATA[] = {
+	 { "BASE_POWER", 0, 7, &umr_bitfield_default },
+	 { "DATA_SCALE", 8, 9, &umr_bitfield_default },
+	 { "PM_SUB_STATE", 10, 12, &umr_bitfield_default },
+	 { "PM_STATE", 13, 14, &umr_bitfield_default },
+	 { "TYPE", 15, 17, &umr_bitfield_default },
+	 { "POWER_RAIL", 18, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PWR_BUDGET_CAP[] = {
+	 { "SYSTEM_ALLOCATED", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_CAP[] = {
+	 { "SUBSTATE_MAX", 0, 4, &umr_bitfield_default },
+	 { "TRANS_LAT_UNIT", 8, 9, &umr_bitfield_default },
+	 { "PWR_ALLOC_SCALE", 12, 13, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_0", 16, 23, &umr_bitfield_default },
+	 { "TRANS_LAT_VAL_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_LATENCY_INDICATOR[] = {
+	 { "TRANS_LAT_INDICATOR_BITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_STATUS[] = {
+	 { "SUBSTATE_STATUS", 0, 4, &umr_bitfield_default },
+	 { "SUBSTATE_CNTL_ENABLED", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_CNTL[] = {
+	 { "SUBSTATE_CNTL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[] = {
+	 { "SUBSTATE_PWR_ALLOC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_CNTL[] = {
+	 { "LC_DONT_ENTER_L23_IN_D0", 1, 1, &umr_bitfield_default },
+	 { "LC_RESET_L_IDLE_COUNT_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_RESET_LINK", 3, 3, &umr_bitfield_default },
+	 { "LC_16X_CLEAR_TX_PIPE", 4, 7, &umr_bitfield_default },
+	 { "LC_L0S_INACTIVITY", 8, 11, &umr_bitfield_default },
+	 { "LC_L1_INACTIVITY", 12, 15, &umr_bitfield_default },
+	 { "LC_PMI_TO_L1_DIS", 16, 16, &umr_bitfield_default },
+	 { "LC_INC_N_FTS_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_IDLE_IN_L1L23", 18, 19, &umr_bitfield_default },
+	 { "LC_FACTOR_IN_EXT_SYNC", 20, 20, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_PM_ACK_DIS", 21, 21, &umr_bitfield_default },
+	 { "LC_WAKE_FROM_L23", 22, 22, &umr_bitfield_default },
+	 { "LC_L1_IMMEDIATE_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_ASPM_TO_L1_DIS", 24, 24, &umr_bitfield_default },
+	 { "LC_DELAY_COUNT", 25, 26, &umr_bitfield_default },
+	 { "LC_DELAY_L0S_EXIT", 27, 27, &umr_bitfield_default },
+	 { "LC_DELAY_L1_EXIT", 28, 28, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_EL_IDLE", 29, 29, &umr_bitfield_default },
+	 { "LC_ESCAPE_L1L23_EN", 30, 30, &umr_bitfield_default },
+	 { "LC_GATE_RCVR_IDLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F4_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_TRAINING_CNTL[] = {
+	 { "LC_TRAINING_CNTL", 0, 3, &umr_bitfield_default },
+	 { "LC_COMPLIANCE_RECEIVE", 4, 4, &umr_bitfield_default },
+	 { "LC_LOOK_FOR_MORE_NON_MATCHING_TS1", 5, 5, &umr_bitfield_default },
+	 { "LC_L0S_L1_TRAINING_CNTL_EN", 6, 6, &umr_bitfield_default },
+	 { "LC_L1_LONG_WAKE_FIX_EN", 7, 7, &umr_bitfield_default },
+	 { "LC_POWER_STATE", 8, 10, &umr_bitfield_default },
+	 { "LC_DONT_GO_TO_L0S_IF_L1_ARMED", 11, 11, &umr_bitfield_default },
+	 { "LC_INIT_SPD_CHG_WITH_CSR_EN", 12, 12, &umr_bitfield_default },
+	 { "LC_DISABLE_TRAINING_BIT_ARCH", 13, 13, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_SETS_IN_RCFG", 14, 14, &umr_bitfield_default },
+	 { "LC_HOT_RESET_QUICK_EXIT_EN", 15, 15, &umr_bitfield_default },
+	 { "LC_EXTEND_WAIT_FOR_SKP", 16, 16, &umr_bitfield_default },
+	 { "LC_AUTONOMOUS_CHANGE_OFF", 17, 17, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAP_OFF", 18, 18, &umr_bitfield_default },
+	 { "LC_HW_LINK_DIS_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_LINK_DIS_BY_HW", 20, 20, &umr_bitfield_default },
+	 { "LC_STATIC_TX_PIPE_COUNT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_ASPM_L1_NAK_TIMER_SEL", 22, 23, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_R_SPEED", 24, 24, &umr_bitfield_default },
+	 { "LC_DONT_DEASSERT_RX_EN_IN_TEST", 25, 25, &umr_bitfield_default },
+	 { "LC_RESET_ASPM_L1_NAK_TIMER", 26, 26, &umr_bitfield_default },
+	 { "LC_SHORT_RCFG_TIMEOUT", 27, 27, &umr_bitfield_default },
+	 { "LC_ALLOW_TX_L1_CONTROL", 28, 28, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_FOM_VALID_AFTER_TRACK", 29, 29, &umr_bitfield_default },
+	 { "LC_EXTEND_EQ_REQ_TIME", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_LINK_WIDTH_CNTL[] = {
+	 { "LC_LINK_WIDTH", 0, 2, &umr_bitfield_default },
+	 { "LC_LINK_WIDTH_RD", 4, 6, &umr_bitfield_default },
+	 { "LC_RECONFIG_ARC_MISSING_ESCAPE", 7, 7, &umr_bitfield_default },
+	 { "LC_RECONFIG_NOW", 8, 8, &umr_bitfield_default },
+	 { "LC_RENEGOTIATION_SUPPORT", 9, 9, &umr_bitfield_default },
+	 { "LC_RENEGOTIATE_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_SHORT_RECONFIG_EN", 11, 11, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_SUPPORT", 12, 12, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_DIS", 13, 13, &umr_bitfield_default },
+	 { "LC_UPCFG_WAIT_FOR_RCVR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LC_UPCFG_TIMER_SEL", 15, 15, &umr_bitfield_default },
+	 { "LC_DEASSERT_TX_PDNB", 16, 16, &umr_bitfield_default },
+	 { "LC_L1_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_DYNLINK_MST_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_DUAL_END_RECONFIG_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_UPCONFIGURE_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LC_DYN_LANES_PWR_STATE", 21, 22, &umr_bitfield_default },
+	 { "LC_EQ_REVERSAL_LOGIC_EN", 23, 23, &umr_bitfield_default },
+	 { "LC_MULT_REVERSE_ATTEMP_EN", 24, 24, &umr_bitfield_default },
+	 { "LC_RESET_TSX_CNT_IN_RCONFIG_EN", 25, 25, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_L_IDLE_IN_R_IDLE", 26, 26, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_NON_EI_ON_RXL0S_EXIT", 27, 27, &umr_bitfield_default },
+	 { "LC_HOLD_EI_FOR_RSPEED_CMD_CHANGE", 28, 28, &umr_bitfield_default },
+	 { "LC_BYPASS_RXL0S_ON_SHORT_EI", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_N_FTS_CNTL[] = {
+	 { "LC_XMIT_N_FTS", 0, 7, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_OVERRIDE_EN", 8, 8, &umr_bitfield_default },
+	 { "LC_XMIT_FTS_BEFORE_RECOVERY", 9, 9, &umr_bitfield_default },
+	 { "LC_XMIT_N_FTS_LIMIT", 16, 23, &umr_bitfield_default },
+	 { "LC_N_FTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_SPEED_CNTL[] = {
+	 { "LC_GEN2_EN_STRAP", 0, 0, &umr_bitfield_default },
+	 { "LC_GEN3_EN_STRAP", 1, 1, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE_EN", 2, 2, &umr_bitfield_default },
+	 { "LC_TARGET_LINK_SPEED_OVERRIDE", 3, 4, &umr_bitfield_default },
+	 { "LC_FORCE_EN_SW_SPEED_CHANGE", 5, 5, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_SW_SPEED_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_FORCE_EN_HW_SPEED_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_FORCE_DIS_HW_SPEED_CHANGE", 8, 8, &umr_bitfield_default },
+	 { "LC_INITIATE_LINK_SPEED_CHANGE", 9, 9, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPTS_ALLOWED", 10, 11, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_ATTEMPT_FAILED", 12, 12, &umr_bitfield_default },
+	 { "LC_CURRENT_DATA_RATE", 13, 14, &umr_bitfield_default },
+	 { "LC_DONT_CLR_TARGET_SPD_CHANGE_STATUS", 15, 15, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_SPD_CHANGE_CNT", 16, 16, &umr_bitfield_default },
+	 { "LC_1_OR_MORE_TS2_SPEED_ARC_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN2", 18, 18, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN2", 19, 19, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_EVER_SENT_GEN3", 20, 20, &umr_bitfield_default },
+	 { "LC_OTHER_SIDE_SUPPORTS_GEN3", 21, 21, &umr_bitfield_default },
+	 { "LC_AUTO_RECOVERY_DIS", 22, 22, &umr_bitfield_default },
+	 { "LC_SPEED_CHANGE_STATUS", 23, 23, &umr_bitfield_default },
+	 { "LC_DATA_RATE_ADVERTISED", 24, 25, &umr_bitfield_default },
+	 { "LC_CHECK_DATA_RATE", 26, 26, &umr_bitfield_default },
+	 { "LC_MULT_UPSTREAM_AUTO_SPD_CHNG_EN", 27, 27, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L0s_EN", 28, 28, &umr_bitfield_default },
+	 { "LC_INIT_SPEED_NEG_IN_L1_EN", 29, 29, &umr_bitfield_default },
+	 { "LC_DONT_CHECK_EQTS_IN_RCFG", 30, 30, &umr_bitfield_default },
+	 { "LC_DELAY_COEFF_UPDATE_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_STATE0[] = {
+	 { "LC_CURRENT_STATE", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE1", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE2", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_STATE1[] = {
+	 { "LC_PREV_STATE4", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE5", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE6", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE7", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_STATE2[] = {
+	 { "LC_PREV_STATE8", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE9", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE10", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE11", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_STATE3[] = {
+	 { "LC_PREV_STATE12", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE13", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE14", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE15", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_STATE4[] = {
+	 { "LC_PREV_STATE16", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE17", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE18", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE19", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_STATE5[] = {
+	 { "LC_PREV_STATE20", 0, 5, &umr_bitfield_default },
+	 { "LC_PREV_STATE21", 8, 13, &umr_bitfield_default },
+	 { "LC_PREV_STATE22", 16, 21, &umr_bitfield_default },
+	 { "LC_PREV_STATE23", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_CNTL[] = {
+	 { "STU", 0, 4, &umr_bitfield_default },
+	 { "ATC_ENABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_ATS_CAP[] = {
+	 { "INVALIDATE_Q_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "PAGE_ALIGNED_REQUEST", 5, 5, &umr_bitfield_default },
+	 { "GLOBAL_INVALIDATE_SUPPORTED", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmADAPTER_ID[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_VENDOR_ID[] = {
+	 { "VENDOR_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_COMMAND[] = {
+	 { "IO_ACCESS_EN", 0, 0, &umr_bitfield_default },
+	 { "MEM_ACCESS_EN", 1, 1, &umr_bitfield_default },
+	 { "BUS_MASTER_EN", 2, 2, &umr_bitfield_default },
+	 { "SPECIAL_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "MEM_WRITE_INVALIDATE_EN", 4, 4, &umr_bitfield_default },
+	 { "PAL_SNOOP_EN", 5, 5, &umr_bitfield_default },
+	 { "PARITY_ERROR_RESPONSE", 6, 6, &umr_bitfield_default },
+	 { "AD_STEPPING", 7, 7, &umr_bitfield_default },
+	 { "SERR_EN", 8, 8, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 9, 9, &umr_bitfield_default },
+	 { "INT_DIS", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_STATUS[] = {
+	 { "INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "SIGNALED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PROG_INTERFACE[] = {
+	 { "PROG_INTERFACE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_REVISION_ID[] = {
+	 { "MINOR_REV_ID", 0, 3, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_BASE_CLASS[] = {
+	 { "BASE_CLASS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SUB_CLASS[] = {
+	 { "SUB_CLASS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_CACHE_LINE[] = {
+	 { "CACHE_LINE_SIZE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_LATENCY[] = {
+	 { "LATENCY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_HEADER[] = {
+	 { "HEADER_TYPE", 16, 22, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_BIST[] = {
+	 { "BIST_COMP", 24, 27, &umr_bitfield_default },
+	 { "BIST_STRT", 30, 30, &umr_bitfield_default },
+	 { "BIST_CAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SUB_BUS_NUMBER_LATENCY[] = {
+	 { "PRIMARY_BUS", 0, 7, &umr_bitfield_default },
+	 { "SECONDARY_BUS", 8, 15, &umr_bitfield_default },
+	 { "SUB_BUS_NUM", 16, 23, &umr_bitfield_default },
+	 { "SECONDARY_LATENCY_TIMER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SECONDARY_STATUS[] = {
+	 { "CAP_LIST", 20, 20, &umr_bitfield_default },
+	 { "PCI_66_EN", 21, 21, &umr_bitfield_default },
+	 { "FAST_BACK_CAPABLE", 23, 23, &umr_bitfield_default },
+	 { "MASTER_DATA_PARITY_ERROR", 24, 24, &umr_bitfield_default },
+	 { "DEVSEL_TIMING", 25, 26, &umr_bitfield_default },
+	 { "SIGNAL_TARGET_ABORT", 27, 27, &umr_bitfield_default },
+	 { "RECEIVED_TARGET_ABORT", 28, 28, &umr_bitfield_default },
+	 { "RECEIVED_MASTER_ABORT", 29, 29, &umr_bitfield_default },
+	 { "RECEIVED_SYSTEM_ERROR", 30, 30, &umr_bitfield_default },
+	 { "PARITY_ERROR_DETECTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_IO_BASE_LIMIT[] = {
+	 { "IO_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "IO_BASE", 4, 7, &umr_bitfield_default },
+	 { "IO_LIMIT_TYPE", 8, 11, &umr_bitfield_default },
+	 { "IO_LIMIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MEM_BASE_LIMIT[] = {
+	 { "MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PREF_BASE_LIMIT[] = {
+	 { "PREF_MEM_BASE_TYPE", 0, 3, &umr_bitfield_default },
+	 { "PREF_MEM_BASE_31_20", 4, 15, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_TYPE", 16, 19, &umr_bitfield_default },
+	 { "PREF_MEM_LIMIT_31_20", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PREF_BASE_UPPER[] = {
+	 { "PREF_BASE_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PREF_LIMIT_UPPER[] = {
+	 { "PREF_LIMIT_UPPER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_IO_BASE_LIMIT_HI[] = {
+	 { "IO_BASE_31_16", 0, 15, &umr_bitfield_default },
+	 { "IO_LIMIT_31_16", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_CAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_IRQ_BRIDGE_CNTL[] = {
+	 { "PARITY_RESPONSE_EN", 16, 16, &umr_bitfield_default },
+	 { "SERR_EN", 17, 17, &umr_bitfield_default },
+	 { "ISA_EN", 18, 18, &umr_bitfield_default },
+	 { "VGA_EN", 19, 19, &umr_bitfield_default },
+	 { "VGA_DEC", 20, 20, &umr_bitfield_default },
+	 { "MASTER_ABORT_MODE", 21, 21, &umr_bitfield_default },
+	 { "SECONDARY_BUS_RESET", 22, 22, &umr_bitfield_default },
+	 { "FAST_B2B_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_INTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_INTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_EXT_BRIDGE_CNTL[] = {
+	 { "IO_PORT_80_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PMI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PMI_CAP[] = {
+	 { "VERSION", 16, 18, &umr_bitfield_default },
+	 { "PME_CLOCK", 19, 19, &umr_bitfield_default },
+	 { "DEV_SPECIFIC_INIT", 21, 21, &umr_bitfield_default },
+	 { "AUX_CURRENT", 22, 24, &umr_bitfield_default },
+	 { "D1_SUPPORT", 25, 25, &umr_bitfield_default },
+	 { "D2_SUPPORT", 26, 26, &umr_bitfield_default },
+	 { "PME_SUPPORT", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PMI_STATUS_CNTL[] = {
+	 { "POWER_STATE", 0, 1, &umr_bitfield_default },
+	 { "NO_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "PME_EN", 8, 8, &umr_bitfield_default },
+	 { "DATA_SELECT", 9, 12, &umr_bitfield_default },
+	 { "DATA_SCALE", 13, 14, &umr_bitfield_default },
+	 { "PME_STATUS", 15, 15, &umr_bitfield_default },
+	 { "B2_B3_SUPPORT", 22, 22, &umr_bitfield_default },
+	 { "BUS_PWR_EN", 23, 23, &umr_bitfield_default },
+	 { "PMI_DATA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_CAP[] = {
+	 { "VERSION", 16, 19, &umr_bitfield_default },
+	 { "DEVICE_TYPE", 20, 23, &umr_bitfield_default },
+	 { "SLOT_IMPLEMENTED", 24, 24, &umr_bitfield_default },
+	 { "INT_MESSAGE_NUM", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_DEVICE_CAP[] = {
+	 { "MAX_PAYLOAD_SUPPORT", 0, 2, &umr_bitfield_default },
+	 { "PHANTOM_FUNC", 3, 4, &umr_bitfield_default },
+	 { "EXTENDED_TAG", 5, 5, &umr_bitfield_default },
+	 { "L0S_ACCEPTABLE_LATENCY", 6, 8, &umr_bitfield_default },
+	 { "L1_ACCEPTABLE_LATENCY", 9, 11, &umr_bitfield_default },
+	 { "ROLE_BASED_ERR_REPORTING", 15, 15, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_LIMIT", 18, 25, &umr_bitfield_default },
+	 { "CAPTURED_SLOT_POWER_SCALE", 26, 27, &umr_bitfield_default },
+	 { "FLR_CAPABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_DEVICE_STATUS[] = {
+	 { "CORR_ERR", 16, 16, &umr_bitfield_default },
+	 { "NON_FATAL_ERR", 17, 17, &umr_bitfield_default },
+	 { "FATAL_ERR", 18, 18, &umr_bitfield_default },
+	 { "USR_DETECTED", 19, 19, &umr_bitfield_default },
+	 { "AUX_PWR", 20, 20, &umr_bitfield_default },
+	 { "TRANSACTIONS_PEND", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_DEVICE_CNTL[] = {
+	 { "CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "NON_FATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "USR_REPORT_EN", 3, 3, &umr_bitfield_default },
+	 { "RELAXED_ORD_EN", 4, 4, &umr_bitfield_default },
+	 { "MAX_PAYLOAD_SIZE", 5, 7, &umr_bitfield_default },
+	 { "EXTENDED_TAG_EN", 8, 8, &umr_bitfield_default },
+	 { "PHANTOM_FUNC_EN", 9, 9, &umr_bitfield_default },
+	 { "AUX_POWER_PM_EN", 10, 10, &umr_bitfield_default },
+	 { "NO_SNOOP_EN", 11, 11, &umr_bitfield_default },
+	 { "MAX_READ_REQUEST_SIZE", 12, 14, &umr_bitfield_default },
+	 { "BRIDGE_CFG_RETRY_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_LINK_CAP[] = {
+	 { "LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "LINK_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PM_SUPPORT", 10, 11, &umr_bitfield_default },
+	 { "L0S_EXIT_LATENCY", 12, 14, &umr_bitfield_default },
+	 { "L1_EXIT_LATENCY", 15, 17, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT", 18, 18, &umr_bitfield_default },
+	 { "SURPRISE_DOWN_ERR_REPORTING", 19, 19, &umr_bitfield_default },
+	 { "DL_ACTIVE_REPORTING_CAPABLE", 20, 20, &umr_bitfield_default },
+	 { "LINK_BW_NOTIFICATION_CAP", 21, 21, &umr_bitfield_default },
+	 { "ASPM_OPTIONALITY_COMPLIANCE", 22, 22, &umr_bitfield_default },
+	 { "PORT_NUMBER", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_LINK_STATUS[] = {
+	 { "CURRENT_LINK_SPEED", 16, 19, &umr_bitfield_default },
+	 { "NEGOTIATED_LINK_WIDTH", 20, 25, &umr_bitfield_default },
+	 { "LINK_TRAINING", 27, 27, &umr_bitfield_default },
+	 { "SLOT_CLOCK_CFG", 28, 28, &umr_bitfield_default },
+	 { "DL_ACTIVE", 29, 29, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_LINK_CNTL[] = {
+	 { "PM_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "READ_CPL_BOUNDARY", 3, 3, &umr_bitfield_default },
+	 { "LINK_DIS", 4, 4, &umr_bitfield_default },
+	 { "RETRAIN_LINK", 5, 5, &umr_bitfield_default },
+	 { "COMMON_CLOCK_CFG", 6, 6, &umr_bitfield_default },
+	 { "EXTENDED_SYNC", 7, 7, &umr_bitfield_default },
+	 { "CLOCK_POWER_MANAGEMENT_EN", 8, 8, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_WIDTH_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "LINK_BW_MANAGEMENT_INT_EN", 10, 10, &umr_bitfield_default },
+	 { "LINK_AUTONOMOUS_BW_INT_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SLOT_CAP[] = {
+	 { "ATTN_BUTTON_PRESENT", 0, 0, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_PRESENT", 3, 3, &umr_bitfield_default },
+	 { "PWR_INDICATOR_PRESENT", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_SURPRISE", 5, 5, &umr_bitfield_default },
+	 { "HOTPLUG_CAPABLE", 6, 6, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_VALUE", 7, 14, &umr_bitfield_default },
+	 { "SLOT_PWR_LIMIT_SCALE", 15, 16, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_PRESENT", 17, 17, &umr_bitfield_default },
+	 { "NO_COMMAND_COMPLETED_SUPPORTED", 18, 18, &umr_bitfield_default },
+	 { "PHYSICAL_SLOT_NUM", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SLOT_STATUS[] = {
+	 { "ATTN_BUTTON_PRESSED", 16, 16, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED", 17, 17, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED", 18, 18, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED", 19, 19, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED", 20, 20, &umr_bitfield_default },
+	 { "MRL_SENSOR_STATE", 21, 21, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE", 22, 22, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_STATUS", 23, 23, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SLOT_CNTL[] = {
+	 { "ATTN_BUTTON_PRESSED_EN", 0, 0, &umr_bitfield_default },
+	 { "PWR_FAULT_DETECTED_EN", 1, 1, &umr_bitfield_default },
+	 { "MRL_SENSOR_CHANGED_EN", 2, 2, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_CHANGED_EN", 3, 3, &umr_bitfield_default },
+	 { "COMMAND_COMPLETED_INTR_EN", 4, 4, &umr_bitfield_default },
+	 { "HOTPLUG_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "ATTN_INDICATOR_CNTL", 6, 7, &umr_bitfield_default },
+	 { "PWR_INDICATOR_CNTL", 8, 9, &umr_bitfield_default },
+	 { "PWR_CONTROLLER_CNTL", 10, 10, &umr_bitfield_default },
+	 { "ELECTROMECH_INTERLOCK_CNTL", 11, 11, &umr_bitfield_default },
+	 { "DL_STATE_CHANGED_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_ROOT_CNTL[] = {
+	 { "SERR_ON_CORR_ERR_EN", 0, 0, &umr_bitfield_default },
+	 { "SERR_ON_NONFATAL_ERR_EN", 1, 1, &umr_bitfield_default },
+	 { "SERR_ON_FATAL_ERR_EN", 2, 2, &umr_bitfield_default },
+	 { "PM_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+	 { "CRS_SOFTWARE_VISIBILITY_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_ROOT_CAP[] = {
+	 { "CRS_SOFTWARE_VISIBILITY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_ROOT_STATUS[] = {
+	 { "PME_REQUESTOR_ID", 0, 15, &umr_bitfield_default },
+	 { "PME_STATUS", 16, 16, &umr_bitfield_default },
+	 { "PME_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_DEVICE_CAP2[] = {
+	 { "CPL_TIMEOUT_RANGE_SUPPORTED", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS_SUPPORTED", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_SUPPORTED", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_ROUTING_SUPPORTED", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_32CMPLT_SUPPORTED", 7, 7, &umr_bitfield_default },
+	 { "ATOMICOP_64CMPLT_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "CAS128_CMPLT_SUPPORTED", 9, 9, &umr_bitfield_default },
+	 { "NO_RO_ENABLED_P2P_PASSING", 10, 10, &umr_bitfield_default },
+	 { "LTR_SUPPORTED", 11, 11, &umr_bitfield_default },
+	 { "TPH_CPLR_SUPPORTED", 12, 13, &umr_bitfield_default },
+	 { "OBFF_SUPPORTED", 18, 19, &umr_bitfield_default },
+	 { "EXTENDED_FMT_FIELD_SUPPORTED", 20, 20, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_SUPPORTED", 21, 21, &umr_bitfield_default },
+	 { "MAX_END_END_TLP_PREFIXES", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_DEVICE_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_DEVICE_CNTL2[] = {
+	 { "CPL_TIMEOUT_VALUE", 0, 3, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "ARI_FORWARDING_EN", 5, 5, &umr_bitfield_default },
+	 { "ATOMICOP_REQUEST_EN", 6, 6, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKING", 7, 7, &umr_bitfield_default },
+	 { "IDO_REQUEST_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "IDO_COMPLETION_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "LTR_EN", 10, 10, &umr_bitfield_default },
+	 { "OBFF_EN", 13, 14, &umr_bitfield_default },
+	 { "END_END_TLP_PREFIX_BLOCKING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_LINK_CAP2[] = {
+	 { "SUPPORTED_LINK_SPEED", 1, 7, &umr_bitfield_default },
+	 { "CROSSLINK_SUPPORTED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_LINK_STATUS2[] = {
+	 { "CUR_DEEMPHASIS_LEVEL", 16, 16, &umr_bitfield_default },
+	 { "EQUALIZATION_COMPLETE", 17, 17, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE1_SUCCESS", 18, 18, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE2_SUCCESS", 19, 19, &umr_bitfield_default },
+	 { "EQUALIZATION_PHASE3_SUCCESS", 20, 20, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQUEST", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_LINK_CNTL2[] = {
+	 { "TARGET_LINK_SPEED", 0, 3, &umr_bitfield_default },
+	 { "ENTER_COMPLIANCE", 4, 4, &umr_bitfield_default },
+	 { "HW_AUTONOMOUS_SPEED_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SELECTABLE_DEEMPHASIS", 6, 6, &umr_bitfield_default },
+	 { "XMIT_MARGIN", 7, 9, &umr_bitfield_default },
+	 { "ENTER_MOD_COMPLIANCE", 10, 10, &umr_bitfield_default },
+	 { "COMPLIANCE_SOS", 11, 11, &umr_bitfield_default },
+	 { "COMPLIANCE_DEEMPHASIS", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SLOT_CAP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SLOT_STATUS2[] = {
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SLOT_CNTL2[] = {
+	 { "RESERVED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_MSG_ADDR_LO[] = {
+	 { "MSI_MSG_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_MSG_ADDR_HI[] = {
+	 { "MSI_MSG_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_MSG_DATA[] = {
+	 { "MSI_DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_MSG_DATA_64[] = {
+	 { "MSI_DATA_64", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SSID_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_SSID_CAP[] = {
+	 { "SUBSYSTEM_VENDOR_ID", 0, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_MAP_CAP_LIST[] = {
+	 { "CAP_ID", 0, 7, &umr_bitfield_default },
+	 { "NEXT_PTR", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_MAP_CAP[] = {
+	 { "EN", 16, 16, &umr_bitfield_default },
+	 { "FIXD", 17, 17, &umr_bitfield_default },
+	 { "CAP_TYPE", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_MAP_ADDR_LO[] = {
+	 { "MSI_MAP_ADDR_LO", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_MSI_MAP_ADDR_HI[] = {
+	 { "MSI_MAP_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_PORT_INDEX[] = {
+	 { "PCIE_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_PORT_DATA[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VENDOR_SPECIFIC_HDR[] = {
+	 { "VSEC_ID", 0, 15, &umr_bitfield_default },
+	 { "VSEC_REV", 16, 19, &umr_bitfield_default },
+	 { "VSEC_LENGTH", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VENDOR_SPECIFIC1[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VENDOR_SPECIFIC2[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_PORT_VC_CAP_REG1[] = {
+	 { "EXT_VC_COUNT", 0, 2, &umr_bitfield_default },
+	 { "LOW_PRIORITY_EXT_VC_COUNT", 4, 6, &umr_bitfield_default },
+	 { "REF_CLK", 8, 9, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_ENTRY_SIZE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_PORT_VC_CAP_REG2[] = {
+	 { "VC_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "VC_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_PORT_VC_STATUS[] = {
+	 { "VC_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_PORT_VC_CNTL[] = {
+	 { "LOAD_VC_ARB_TABLE", 0, 0, &umr_bitfield_default },
+	 { "VC_ARB_SELECT", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VC0_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VC0_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VC0_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VC1_RESOURCE_CAP[] = {
+	 { "PORT_ARB_CAP", 0, 7, &umr_bitfield_default },
+	 { "REJECT_SNOOP_TRANS", 15, 15, &umr_bitfield_default },
+	 { "MAX_TIME_SLOTS", 16, 21, &umr_bitfield_default },
+	 { "PORT_ARB_TABLE_OFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VC1_RESOURCE_CNTL[] = {
+	 { "TC_VC_MAP_TC0", 0, 0, &umr_bitfield_default },
+	 { "TC_VC_MAP_TC1_7", 1, 7, &umr_bitfield_default },
+	 { "LOAD_PORT_ARB_TABLE", 16, 16, &umr_bitfield_default },
+	 { "PORT_ARB_SELECT", 17, 19, &umr_bitfield_default },
+	 { "VC_ID", 24, 26, &umr_bitfield_default },
+	 { "VC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_VC1_RESOURCE_STATUS[] = {
+	 { "PORT_ARB_TABLE_STATUS", 16, 16, &umr_bitfield_default },
+	 { "VC_NEGOTIATION_PENDING", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_DEV_SERIAL_NUM_DW1[] = {
+	 { "SERIAL_NUMBER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_DEV_SERIAL_NUM_DW2[] = {
+	 { "SERIAL_NUMBER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_UNCORR_ERR_STATUS[] = {
+	 { "DLP_ERR_STATUS", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_STATUS", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_STATUS", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_STATUS", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_STATUS", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_STATUS", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_STATUS", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_STATUS", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_STATUS", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_STATUS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_UNCORR_ERR_MASK[] = {
+	 { "DLP_ERR_MASK", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_MASK", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_MASK", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_MASK", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_MASK", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_MASK", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_MASK", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_MASK", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_MASK", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_MASK", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_MASK", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_MASK", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_MASK", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_UNCORR_ERR_SEVERITY[] = {
+	 { "DLP_ERR_SEVERITY", 4, 4, &umr_bitfield_default },
+	 { "SURPDN_ERR_SEVERITY", 5, 5, &umr_bitfield_default },
+	 { "PSN_ERR_SEVERITY", 12, 12, &umr_bitfield_default },
+	 { "FC_ERR_SEVERITY", 13, 13, &umr_bitfield_default },
+	 { "CPL_TIMEOUT_SEVERITY", 14, 14, &umr_bitfield_default },
+	 { "CPL_ABORT_ERR_SEVERITY", 15, 15, &umr_bitfield_default },
+	 { "UNEXP_CPL_SEVERITY", 16, 16, &umr_bitfield_default },
+	 { "RCV_OVFL_SEVERITY", 17, 17, &umr_bitfield_default },
+	 { "MAL_TLP_SEVERITY", 18, 18, &umr_bitfield_default },
+	 { "ECRC_ERR_SEVERITY", 19, 19, &umr_bitfield_default },
+	 { "UNSUPP_REQ_ERR_SEVERITY", 20, 20, &umr_bitfield_default },
+	 { "ACS_VIOLATION_SEVERITY", 21, 21, &umr_bitfield_default },
+	 { "UNCORR_INT_ERR_SEVERITY", 22, 22, &umr_bitfield_default },
+	 { "MC_BLOCKED_TLP_SEVERITY", 23, 23, &umr_bitfield_default },
+	 { "ATOMICOP_EGRESS_BLOCKED_SEVERITY", 24, 24, &umr_bitfield_default },
+	 { "TLP_PREFIX_BLOCKED_ERR_SEVERITY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_CORR_ERR_STATUS[] = {
+	 { "RCV_ERR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_STATUS", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_STATUS", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_STATUS", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_STATUS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_CORR_ERR_MASK[] = {
+	 { "RCV_ERR_MASK", 0, 0, &umr_bitfield_default },
+	 { "BAD_TLP_MASK", 6, 6, &umr_bitfield_default },
+	 { "BAD_DLLP_MASK", 7, 7, &umr_bitfield_default },
+	 { "REPLAY_NUM_ROLLOVER_MASK", 8, 8, &umr_bitfield_default },
+	 { "REPLAY_TIMER_TIMEOUT_MASK", 12, 12, &umr_bitfield_default },
+	 { "ADVISORY_NONFATAL_ERR_MASK", 13, 13, &umr_bitfield_default },
+	 { "CORR_INT_ERR_MASK", 14, 14, &umr_bitfield_default },
+	 { "HDR_LOG_OVFL_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_ADV_ERR_CAP_CNTL[] = {
+	 { "FIRST_ERR_PTR", 0, 4, &umr_bitfield_default },
+	 { "ECRC_GEN_CAP", 5, 5, &umr_bitfield_default },
+	 { "ECRC_GEN_EN", 6, 6, &umr_bitfield_default },
+	 { "ECRC_CHECK_CAP", 7, 7, &umr_bitfield_default },
+	 { "ECRC_CHECK_EN", 8, 8, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_CAP", 9, 9, &umr_bitfield_default },
+	 { "MULTI_HDR_RECD_EN", 10, 10, &umr_bitfield_default },
+	 { "TLP_PREFIX_LOG_PRESENT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_HDR_LOG0[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_HDR_LOG1[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_HDR_LOG2[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_HDR_LOG3[] = {
+	 { "TLP_HDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_ROOT_ERR_CMD[] = {
+	 { "CORR_ERR_REP_EN", 0, 0, &umr_bitfield_default },
+	 { "NONFATAL_ERR_REP_EN", 1, 1, &umr_bitfield_default },
+	 { "FATAL_ERR_REP_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_ROOT_ERR_STATUS[] = {
+	 { "ERR_CORR_RCVD", 0, 0, &umr_bitfield_default },
+	 { "MULT_ERR_CORR_RCVD", 1, 1, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_RCVD", 2, 2, &umr_bitfield_default },
+	 { "MULT_ERR_FATAL_NONFATAL_RCVD", 3, 3, &umr_bitfield_default },
+	 { "FIRST_UNCORRECTABLE_FATAL", 4, 4, &umr_bitfield_default },
+	 { "NONFATAL_ERROR_MSG_RCVD", 5, 5, &umr_bitfield_default },
+	 { "FATAL_ERROR_MSG_RCVD", 6, 6, &umr_bitfield_default },
+	 { "ADV_ERR_INT_MSG_NUM", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_ERR_SRC_ID[] = {
+	 { "ERR_CORR_SRC_ID", 0, 15, &umr_bitfield_default },
+	 { "ERR_FATAL_NONFATAL_SRC_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_TLP_PREFIX_LOG0[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_TLP_PREFIX_LOG1[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_TLP_PREFIX_LOG2[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_TLP_PREFIX_LOG3[] = {
+	 { "TLP_PREFIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LINK_CNTL3[] = {
+	 { "PERFORM_EQUALIZATION", 0, 0, &umr_bitfield_default },
+	 { "LINK_EQUALIZATION_REQ_INT_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_ERROR_STATUS[] = {
+	 { "LANE_ERROR_STATUS_BITS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL[] = {
+	 { "DOWNSTREAM_PORT_TX_PRESET", 0, 3, &umr_bitfield_default },
+	 { "DOWNSTREAM_PORT_RX_PRESET_HINT", 4, 6, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_TX_PRESET", 8, 11, &umr_bitfield_default },
+	 { "UPSTREAM_PORT_RX_PRESET_HINT", 12, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_ACS_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_ACS_CNTL[] = {
+	 { "SOURCE_VALIDATION_EN", 16, 16, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING_EN", 17, 17, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT_EN", 18, 18, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT_EN", 19, 19, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING_EN", 20, 20, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL_EN", 21, 21, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_ACS_CAP[] = {
+	 { "SOURCE_VALIDATION", 0, 0, &umr_bitfield_default },
+	 { "TRANSLATION_BLOCKING", 1, 1, &umr_bitfield_default },
+	 { "P2P_REQUEST_REDIRECT", 2, 2, &umr_bitfield_default },
+	 { "P2P_COMPLETION_REDIRECT", 3, 3, &umr_bitfield_default },
+	 { "UPSTREAM_FORWARDING", 4, 4, &umr_bitfield_default },
+	 { "P2P_EGRESS_CONTROL", 5, 5, &umr_bitfield_default },
+	 { "DIRECT_TRANSLATED_P2P", 6, 6, &umr_bitfield_default },
+	 { "EGRESS_CONTROL_VECTOR_SIZE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 16, 21, &umr_bitfield_default },
+	 { "MC_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_OVERLAY_BAR0[] = {
+	 { "MC_OVERLAY_SIZE", 0, 5, &umr_bitfield_default },
+	 { "MC_OVERLAY_BAR_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD3F5_PCIE_MC_OVERLAY_BAR1[] = {
+	 { "MC_OVERLAY_BAR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_STATUS[] = {
+	 { "RESPONSE_FAILURE", 0, 0, &umr_bitfield_default },
+	 { "UNEXPECTED_PAGE_REQ_GRP_INDEX", 1, 1, &umr_bitfield_default },
+	 { "STOPPED", 8, 8, &umr_bitfield_default },
+	 { "PRG_RESPONSE_PASID_REQUIRED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PAGE_REQ_CNTL[] = {
+	 { "PRI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRI_RESET", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[] = {
+	 { "OUTSTAND_PAGE_REQ_CAPACITY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_BW_CHANGE_CNTL[] = {
+	 { "LC_BW_CHANGE_INT_EN", 0, 0, &umr_bitfield_default },
+	 { "LC_HW_INIT_SPEED_CHANGE", 1, 1, &umr_bitfield_default },
+	 { "LC_SW_INIT_SPEED_CHANGE", 2, 2, &umr_bitfield_default },
+	 { "LC_OTHER_INIT_SPEED_CHANGE", 3, 3, &umr_bitfield_default },
+	 { "LC_RELIABILITY_SPEED_CHANGE", 4, 4, &umr_bitfield_default },
+	 { "LC_FAILED_SPEED_NEG", 5, 5, &umr_bitfield_default },
+	 { "LC_LONG_LW_CHANGE", 6, 6, &umr_bitfield_default },
+	 { "LC_SHORT_LW_CHANGE", 7, 7, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_OTHER", 8, 8, &umr_bitfield_default },
+	 { "LC_LW_CHANGE_FAILED", 9, 9, &umr_bitfield_default },
+	 { "LC_LINK_BW_NOTIFICATION_DETECT_MODE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[] = {
+	 { "OUTSTAND_PAGE_REQ_ALLOC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_CDR_CNTL[] = {
+	 { "LC_CDR_TEST_OFF", 0, 11, &umr_bitfield_default },
+	 { "LC_CDR_TEST_SETS", 12, 23, &umr_bitfield_default },
+	 { "LC_CDR_SET_TYPE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_LANE_CNTL[] = {
+	 { "LC_CORRUPTED_LANES", 0, 15, &umr_bitfield_default },
+	 { "LC_LANE_DIS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_CNTL3[] = {
+	 { "LC_SELECT_DEEMPHASIS", 0, 0, &umr_bitfield_default },
+	 { "LC_SELECT_DEEMPHASIS_CNTL", 1, 2, &umr_bitfield_default },
+	 { "LC_RCVD_DEEMPHASIS", 3, 3, &umr_bitfield_default },
+	 { "LC_COMP_TO_DETECT", 4, 4, &umr_bitfield_default },
+	 { "LC_RESET_TSX_CNT_IN_RLOCK_EN", 5, 5, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPTS_ALLOWED", 6, 7, &umr_bitfield_default },
+	 { "LC_AUTO_SPEED_CHANGE_ATTEMPT_FAILED", 8, 8, &umr_bitfield_default },
+	 { "LC_CLR_FAILED_AUTO_SPD_CHANGE_CNT", 9, 9, &umr_bitfield_default },
+	 { "LC_ENHANCED_HOT_PLUG_EN", 10, 10, &umr_bitfield_default },
+	 { "LC_RCVR_DET_EN_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "LC_EHP_RX_PHY_CMD", 12, 13, &umr_bitfield_default },
+	 { "LC_EHP_TX_PHY_CMD", 14, 15, &umr_bitfield_default },
+	 { "LC_CHIP_BIF_USB_IDLE_EN", 16, 16, &umr_bitfield_default },
+	 { "LC_L1_BLOCK_RECONFIG_EN", 17, 17, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_EN", 18, 18, &umr_bitfield_default },
+	 { "LC_AUTO_DISABLE_SPEED_SUPPORT_MAX_FAIL_SEL", 19, 20, &umr_bitfield_default },
+	 { "LC_FAST_L1_ENTRY_EXIT_EN", 21, 21, &umr_bitfield_default },
+	 { "LC_RXPHYCMD_INACTIVE_EN_MODE", 22, 22, &umr_bitfield_default },
+	 { "LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK", 23, 23, &umr_bitfield_default },
+	 { "LC_HW_VOLTAGE_IF_CONTROL", 24, 25, &umr_bitfield_default },
+	 { "LC_VOLTAGE_TIMER_SEL", 26, 29, &umr_bitfield_default },
+	 { "LC_GO_TO_RECOVERY", 30, 30, &umr_bitfield_default },
+	 { "LC_N_EIE_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_CNTL[] = {
+	 { "PASID_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PASID_EXE_PERMISSION_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "PASID_PRIV_MODE_SUPPORTED_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_PASID_CAP[] = {
+	 { "PASID_EXE_PERMISSION_SUPPORTED", 1, 1, &umr_bitfield_default },
+	 { "PASID_PRIV_MODE_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "MAX_PASID_WIDTH", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_CNTL4[] = {
+	 { "LC_TX_ENABLE_BEHAVIOUR", 0, 1, &umr_bitfield_default },
+	 { "LC_DIS_CONTIG_END_SET_CHECK", 2, 2, &umr_bitfield_default },
+	 { "LC_DIS_ASPM_L1_IN_SPEED_CHANGE", 3, 3, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ", 4, 4, &umr_bitfield_default },
+	 { "LC_REDO_EQ", 5, 5, &umr_bitfield_default },
+	 { "LC_EXTEND_EIEOS", 6, 6, &umr_bitfield_default },
+	 { "LC_IGNORE_PARITY", 7, 7, &umr_bitfield_default },
+	 { "LC_EQ_SEARCH_MODE", 8, 9, &umr_bitfield_default },
+	 { "LC_DSC_CHECK_COEFFS_IN_RLOCK", 10, 10, &umr_bitfield_default },
+	 { "LC_USC_EQ_NOT_REQD", 11, 11, &umr_bitfield_default },
+	 { "LC_USC_GO_TO_EQ", 12, 12, &umr_bitfield_default },
+	 { "LC_SET_QUIESCE", 13, 13, &umr_bitfield_default },
+	 { "LC_QUIESCE_RCVD", 14, 14, &umr_bitfield_default },
+	 { "LC_UNEXPECTED_COEFFS_RCVD", 15, 15, &umr_bitfield_default },
+	 { "LC_BYPASS_EQ_REQ_PHASE", 16, 16, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_IN_EQ_REQ_PHASE", 17, 17, &umr_bitfield_default },
+	 { "LC_FORCE_PRESET_VALUE", 18, 21, &umr_bitfield_default },
+	 { "LC_USC_DELAY_DLLPS", 22, 22, &umr_bitfield_default },
+	 { "LC_PCIE_TX_FULL_SWING", 23, 23, &umr_bitfield_default },
+	 { "LC_EQ_WAIT_FOR_EVAL_DONE", 24, 24, &umr_bitfield_default },
+	 { "LC_8GT_SKIP_ORDER_EN", 25, 25, &umr_bitfield_default },
+	 { "LC_WAIT_FOR_MORE_TS_IN_RLOCK", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_CNTL5[] = {
+	 { "LC_EQ_FS_0", 0, 5, &umr_bitfield_default },
+	 { "LC_EQ_FS_8", 6, 11, &umr_bitfield_default },
+	 { "LC_EQ_LF_0", 12, 17, &umr_bitfield_default },
+	 { "LC_EQ_LF_8", 18, 23, &umr_bitfield_default },
+	 { "LC_DSC_EQ_FS_LF_INVALID_TO_PRESETS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_FORCE_COEFF[] = {
+	 { "LC_FORCE_COEFF", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR", 1, 6, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR", 13, 18, &umr_bitfield_default },
+	 { "LC_3X3_COEFF_SEARCH_EN", 19, 19, &umr_bitfield_default },
+	 { "LC_PRESET_10_EN", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_BEST_EQ_SETTINGS[] = {
+	 { "LC_BEST_PRESET", 0, 3, &umr_bitfield_default },
+	 { "LC_BEST_PRECURSOR", 4, 9, &umr_bitfield_default },
+	 { "LC_BEST_CURSOR", 10, 15, &umr_bitfield_default },
+	 { "LC_BEST_POSTCURSOR", 16, 21, &umr_bitfield_default },
+	 { "LC_BEST_FOM", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_CAP[] = {
+	 { "TPH_REQR_NO_ST_MODE_SUPPORTED", 0, 0, &umr_bitfield_default },
+	 { "TPH_REQR_INT_VEC_MODE_SUPPORTED", 1, 1, &umr_bitfield_default },
+	 { "TPH_REQR_DEV_SPC_MODE_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "TPH_REQR_EXTND_TPH_REQR_SUPPORED", 8, 8, &umr_bitfield_default },
+	 { "TPH_REQR_ST_TABLE_LOCATION", 9, 10, &umr_bitfield_default },
+	 { "TPH_REQR_ST_TABLE_SIZE", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF[] = {
+	 { "LC_FORCE_COEFF_IN_EQ_REQ_PHASE", 0, 0, &umr_bitfield_default },
+	 { "LC_FORCE_PRE_CURSOR_REQ", 1, 6, &umr_bitfield_default },
+	 { "LC_FORCE_CURSOR_REQ", 7, 12, &umr_bitfield_default },
+	 { "LC_FORCE_POST_CURSOR_REQ", 13, 18, &umr_bitfield_default },
+	 { "LC_FS_OTHER_END", 19, 24, &umr_bitfield_default },
+	 { "LC_LF_OTHER_END", 25, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_TPH_REQR_CNTL[] = {
+	 { "TPH_REQR_ST_MODE_SEL", 0, 2, &umr_bitfield_default },
+	 { "TPH_REQR_EN", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIE_LC_CNTL6[] = {
+	 { "LC_SPC_MODE_2P5GT", 0, 0, &umr_bitfield_default },
+	 { "LC_SPC_MODE_5GT", 2, 2, &umr_bitfield_default },
+	 { "LC_SPC_MODE_8GT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_CNTL[] = {
+	 { "MC_NUM_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_ENABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_CAP[] = {
+	 { "MC_MAX_GROUP", 0, 5, &umr_bitfield_default },
+	 { "MC_WIN_SIZE_REQ", 8, 13, &umr_bitfield_default },
+	 { "MC_ECRC_REGEN_SUPP", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ADDR0[] = {
+	 { "MC_INDEX_POS", 0, 5, &umr_bitfield_default },
+	 { "MC_BASE_ADDR_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_ADDR1[] = {
+	 { "MC_BASE_ADDR_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmROM_BASE_ADDR[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_INDEX_2[] = {
+	 { "PCIE_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_STRAP_LC[] = {
+	 { "STRAP_FTS_yTSx_COUNT", 0, 1, &umr_bitfield_default },
+	 { "STRAP_LONG_yTSx_COUNT", 2, 3, &umr_bitfield_default },
+	 { "STRAP_MED_yTSx_COUNT", 4, 5, &umr_bitfield_default },
+	 { "STRAP_SHORT_yTSx_COUNT", 6, 7, &umr_bitfield_default },
+	 { "STRAP_SKIP_INTERVAL", 8, 10, &umr_bitfield_default },
+	 { "STRAP_BYPASS_RCVR_DET", 11, 11, &umr_bitfield_default },
+	 { "STRAP_COMPLIANCE_DIS", 12, 12, &umr_bitfield_default },
+	 { "STRAP_FORCE_COMPLIANCE", 13, 13, &umr_bitfield_default },
+	 { "STRAP_REVERSE_LC_LANES", 14, 14, &umr_bitfield_default },
+	 { "STRAP_AUTO_RC_SPEED_NEGOTIATION_DIS", 15, 15, &umr_bitfield_default },
+	 { "STRAP_LANE_NEGOTIATION", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_RCV0[] = {
+	 { "MC_RECEIVE_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_STRAP_MISC[] = {
+	 { "STRAP_REVERSE_LANES", 0, 0, &umr_bitfield_default },
+	 { "STRAP_E2E_PREFIX_EN", 1, 1, &umr_bitfield_default },
+	 { "STRAP_EXTENDED_FMT_SUPPORTED", 2, 2, &umr_bitfield_default },
+	 { "STRAP_OBFF_SUPPORTED", 3, 4, &umr_bitfield_default },
+	 { "STRAP_LTR_SUPPORTED", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_RCV1[] = {
+	 { "MC_RECEIVE_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_ALL0[] = {
+	 { "MC_BLOCK_ALL_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_ALL1[] = {
+	 { "MC_BLOCK_ALL_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_UNTRANSLATED_0[] = {
+	 { "MC_BLOCK_UNTRANSLATED_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_MC_BLOCK_UNTRANSLATED_1[] = {
+	 { "MC_BLOCK_UNTRANSLATED_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LTR_ENH_CAP_LIST[] = {
+	 { "CAP_ID", 0, 15, &umr_bitfield_default },
+	 { "CAP_VER", 16, 19, &umr_bitfield_default },
+	 { "NEXT_PTR", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_LTR_CAP[] = {
+	 { "LTR_MAX_S_LATENCY_VALUE", 0, 9, &umr_bitfield_default },
+	 { "LTR_MAX_S_LATENCY_SCALE", 10, 12, &umr_bitfield_default },
+	 { "LTR_MAX_NS_LATENCY_VALUE", 16, 25, &umr_bitfield_default },
+	 { "LTR_MAX_NS_LATENCY_SCALE", 26, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_DATA_2[] = {
+	 { "PCIE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCAP_PTR[] = {
+	 { "CAP_PTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_BCH_ECC_CNTL[] = {
+	 { "STRAP_BCH_ECC_EN", 0, 0, &umr_bitfield_default },
+	 { "BCH_ECC_ERROR_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "BCH_ECC_ERROR_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_HPGI_PRIVATE[] = {
+	 { "PRESENCE_DETECT_CHANGED_PRIVATE", 3, 3, &umr_bitfield_default },
+	 { "PRESENCE_DETECT_STATE_PRIVATE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixD2F1_PCIEP_HPGI[] = {
+	 { "REG_HPGI_ASSERT_TO_SMI_EN", 0, 0, &umr_bitfield_default },
+	 { "REG_HPGI_ASSERT_TO_SCI_EN", 1, 1, &umr_bitfield_default },
+	 { "REG_HPGI_DEASSERT_TO_SMI_EN", 2, 2, &umr_bitfield_default },
+	 { "REG_HPGI_DEASSERT_TO_SCI_EN", 3, 3, &umr_bitfield_default },
+	 { "REG_HPGI_HOOK", 7, 7, &umr_bitfield_default },
+	 { "HPGI_REG_ASSERT_TO_SMI_STATUS", 8, 8, &umr_bitfield_default },
+	 { "HPGI_REG_ASSERT_TO_SCI_STATUS", 9, 9, &umr_bitfield_default },
+	 { "HPGI_REG_DEASSERT_TO_SMI_STATUS", 10, 10, &umr_bitfield_default },
+	 { "HPGI_REG_DEASSERT_TO_SCI_STATUS", 11, 11, &umr_bitfield_default },
+	 { "HPGI_REG_PRESENCE_DETECT_STATE_CHANGE_STATUS", 15, 15, &umr_bitfield_default },
+	 { "REG_HPGI_PRESENCE_DETECT_STATE_CHANGE_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPCIE_INDEX[] = {
+	 { "PCIE_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_LINE[] = {
+	 { "INTERRUPT_LINE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_PIN[] = {
+	 { "INTERRUPT_PIN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMAX_LATENCY[] = {
+	 { "MAX_LAT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMIN_GRANT[] = {
+	 { "MIN_GNT", 0, 7, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/bif51_regs.i b/src/lib/ip/bif51_regs.i
new file mode 100644
index 0000000..3273295
--- /dev/null
+++ b/src/lib/ip/bif51_regs.i
@@ -0,0 +1,2886 @@
+	{ "ixD2F1_PCIEP_RESERVED", REG_SMC, 0x0, &ixD2F1_PCIEP_RESERVED[0], sizeof(ixD2F1_PCIEP_RESERVED)/sizeof(ixD2F1_PCIEP_RESERVED[0]), 0, 0 },
+	{ "mmVENDOR_ID", REG_MMIO, 0x0, &mmVENDOR_ID[0], sizeof(mmVENDOR_ID)/sizeof(mmVENDOR_ID[0]), 0, 0 },
+	{ "mmMM_INDEX", REG_MMIO, 0x0, &mmMM_INDEX[0], sizeof(mmMM_INDEX)/sizeof(mmMM_INDEX[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_SCRATCH", REG_SMC, 0x1, &ixD2F1_PCIEP_SCRATCH[0], sizeof(ixD2F1_PCIEP_SCRATCH)/sizeof(ixD2F1_PCIEP_SCRATCH[0]), 0, 0 },
+	{ "mmMM_DATA", REG_MMIO, 0x1, &mmMM_DATA[0], sizeof(mmMM_DATA)/sizeof(mmMM_DATA[0]), 0, 0 },
+	{ "mmSTATUS", REG_MMIO, 0x1, &mmSTATUS[0], sizeof(mmSTATUS)/sizeof(mmSTATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_PORT_CNTL", REG_SMC, 0x10, &ixD2F1_PCIEP_PORT_CNTL[0], sizeof(ixD2F1_PCIEP_PORT_CNTL)/sizeof(ixD2F1_PCIEP_PORT_CNTL[0]), 0, 0 },
+	{ "ixPCIEP_RESERVED", REG_SMC, 0x10010000, &ixPCIEP_RESERVED[0], sizeof(ixPCIEP_RESERVED)/sizeof(ixPCIEP_RESERVED[0]), 0, 0 },
+	{ "ixPCIEP_SCRATCH", REG_SMC, 0x10010001, &ixPCIEP_SCRATCH[0], sizeof(ixPCIEP_SCRATCH)/sizeof(ixPCIEP_SCRATCH[0]), 0, 0 },
+	{ "ixPCIEP_HW_DEBUG", REG_SMC, 0x10010002, &ixPCIEP_HW_DEBUG[0], sizeof(ixPCIEP_HW_DEBUG)/sizeof(ixPCIEP_HW_DEBUG[0]), 0, 0 },
+	{ "ixPCIEP_PORT_CNTL", REG_SMC, 0x10010010, &ixPCIEP_PORT_CNTL[0], sizeof(ixPCIEP_PORT_CNTL)/sizeof(ixPCIEP_PORT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_CNTL", REG_SMC, 0x10010020, &ixPCIE_TX_CNTL[0], sizeof(ixPCIE_TX_CNTL)/sizeof(ixPCIE_TX_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_REQUESTER_ID", REG_SMC, 0x10010021, &ixPCIE_TX_REQUESTER_ID[0], sizeof(ixPCIE_TX_REQUESTER_ID)/sizeof(ixPCIE_TX_REQUESTER_ID[0]), 0, 0 },
+	{ "ixPCIE_TX_VENDOR_SPECIFIC", REG_SMC, 0x10010022, &ixPCIE_TX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_TX_VENDOR_SPECIFIC)/sizeof(ixPCIE_TX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "ixPCIE_TX_REQUEST_NUM_CNTL", REG_SMC, 0x10010023, &ixPCIE_TX_REQUEST_NUM_CNTL[0], sizeof(ixPCIE_TX_REQUEST_NUM_CNTL)/sizeof(ixPCIE_TX_REQUEST_NUM_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_SEQ", REG_SMC, 0x10010024, &ixPCIE_TX_SEQ[0], sizeof(ixPCIE_TX_SEQ)/sizeof(ixPCIE_TX_SEQ[0]), 0, 0 },
+	{ "ixPCIE_TX_REPLAY", REG_SMC, 0x10010025, &ixPCIE_TX_REPLAY[0], sizeof(ixPCIE_TX_REPLAY)/sizeof(ixPCIE_TX_REPLAY[0]), 0, 0 },
+	{ "ixPCIE_TX_ACK_LATENCY_LIMIT", REG_SMC, 0x10010026, &ixPCIE_TX_ACK_LATENCY_LIMIT[0], sizeof(ixPCIE_TX_ACK_LATENCY_LIMIT)/sizeof(ixPCIE_TX_ACK_LATENCY_LIMIT[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_P", REG_SMC, 0x10010030, &ixPCIE_TX_CREDITS_ADVT_P[0], sizeof(ixPCIE_TX_CREDITS_ADVT_P)/sizeof(ixPCIE_TX_CREDITS_ADVT_P[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_NP", REG_SMC, 0x10010031, &ixPCIE_TX_CREDITS_ADVT_NP[0], sizeof(ixPCIE_TX_CREDITS_ADVT_NP)/sizeof(ixPCIE_TX_CREDITS_ADVT_NP[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_ADVT_CPL", REG_SMC, 0x10010032, &ixPCIE_TX_CREDITS_ADVT_CPL[0], sizeof(ixPCIE_TX_CREDITS_ADVT_CPL)/sizeof(ixPCIE_TX_CREDITS_ADVT_CPL[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_P", REG_SMC, 0x10010033, &ixPCIE_TX_CREDITS_INIT_P[0], sizeof(ixPCIE_TX_CREDITS_INIT_P)/sizeof(ixPCIE_TX_CREDITS_INIT_P[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_NP", REG_SMC, 0x10010034, &ixPCIE_TX_CREDITS_INIT_NP[0], sizeof(ixPCIE_TX_CREDITS_INIT_NP)/sizeof(ixPCIE_TX_CREDITS_INIT_NP[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_INIT_CPL", REG_SMC, 0x10010035, &ixPCIE_TX_CREDITS_INIT_CPL[0], sizeof(ixPCIE_TX_CREDITS_INIT_CPL)/sizeof(ixPCIE_TX_CREDITS_INIT_CPL[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_STATUS", REG_SMC, 0x10010036, &ixPCIE_TX_CREDITS_STATUS[0], sizeof(ixPCIE_TX_CREDITS_STATUS)/sizeof(ixPCIE_TX_CREDITS_STATUS[0]), 0, 0 },
+	{ "ixPCIE_TX_CREDITS_FCU_THRESHOLD", REG_SMC, 0x10010037, &ixPCIE_TX_CREDITS_FCU_THRESHOLD[0], sizeof(ixPCIE_TX_CREDITS_FCU_THRESHOLD)/sizeof(ixPCIE_TX_CREDITS_FCU_THRESHOLD[0]), 0, 0 },
+	{ "ixPCIE_P_PORT_LANE_STATUS", REG_SMC, 0x10010050, &ixPCIE_P_PORT_LANE_STATUS[0], sizeof(ixPCIE_P_PORT_LANE_STATUS)/sizeof(ixPCIE_P_PORT_LANE_STATUS[0]), 0, 0 },
+	{ "ixPCIE_FC_P", REG_SMC, 0x10010060, &ixPCIE_FC_P[0], sizeof(ixPCIE_FC_P)/sizeof(ixPCIE_FC_P[0]), 0, 0 },
+	{ "ixPCIE_FC_NP", REG_SMC, 0x10010061, &ixPCIE_FC_NP[0], sizeof(ixPCIE_FC_NP)/sizeof(ixPCIE_FC_NP[0]), 0, 0 },
+	{ "ixPCIE_FC_CPL", REG_SMC, 0x10010062, &ixPCIE_FC_CPL[0], sizeof(ixPCIE_FC_CPL)/sizeof(ixPCIE_FC_CPL[0]), 0, 0 },
+	{ "ixPCIE_ERR_CNTL", REG_SMC, 0x1001006a, &ixPCIE_ERR_CNTL[0], sizeof(ixPCIE_ERR_CNTL)/sizeof(ixPCIE_ERR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL", REG_SMC, 0x10010070, &ixPCIE_RX_CNTL[0], sizeof(ixPCIE_RX_CNTL)/sizeof(ixPCIE_RX_CNTL[0]), 0, 0 },
+	{ "ixPCIE_RX_EXPECTED_SEQNUM", REG_SMC, 0x10010071, &ixPCIE_RX_EXPECTED_SEQNUM[0], sizeof(ixPCIE_RX_EXPECTED_SEQNUM)/sizeof(ixPCIE_RX_EXPECTED_SEQNUM[0]), 0, 0 },
+	{ "ixPCIE_RX_VENDOR_SPECIFIC", REG_SMC, 0x10010072, &ixPCIE_RX_VENDOR_SPECIFIC[0], sizeof(ixPCIE_RX_VENDOR_SPECIFIC)/sizeof(ixPCIE_RX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL3", REG_SMC, 0x10010074, &ixPCIE_RX_CNTL3[0], sizeof(ixPCIE_RX_CNTL3)/sizeof(ixPCIE_RX_CNTL3[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_P", REG_SMC, 0x10010080, &ixPCIE_RX_CREDITS_ALLOCATED_P[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_P)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_P[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_NP", REG_SMC, 0x10010081, &ixPCIE_RX_CREDITS_ALLOCATED_NP[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_NP)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_NP[0]), 0, 0 },
+	{ "ixPCIE_RX_CREDITS_ALLOCATED_CPL", REG_SMC, 0x10010082, &ixPCIE_RX_CREDITS_ALLOCATED_CPL[0], sizeof(ixPCIE_RX_CREDITS_ALLOCATED_CPL)/sizeof(ixPCIE_RX_CREDITS_ALLOCATED_CPL[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL", REG_SMC, 0x100100a0, &ixPCIE_LC_CNTL[0], sizeof(ixPCIE_LC_CNTL)/sizeof(ixPCIE_LC_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_TRAINING_CNTL", REG_SMC, 0x100100a1, &ixPCIE_LC_TRAINING_CNTL[0], sizeof(ixPCIE_LC_TRAINING_CNTL)/sizeof(ixPCIE_LC_TRAINING_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_LINK_WIDTH_CNTL", REG_SMC, 0x100100a2, &ixPCIE_LC_LINK_WIDTH_CNTL[0], sizeof(ixPCIE_LC_LINK_WIDTH_CNTL)/sizeof(ixPCIE_LC_LINK_WIDTH_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_N_FTS_CNTL", REG_SMC, 0x100100a3, &ixPCIE_LC_N_FTS_CNTL[0], sizeof(ixPCIE_LC_N_FTS_CNTL)/sizeof(ixPCIE_LC_N_FTS_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_SPEED_CNTL", REG_SMC, 0x100100a4, &ixPCIE_LC_SPEED_CNTL[0], sizeof(ixPCIE_LC_SPEED_CNTL)/sizeof(ixPCIE_LC_SPEED_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE0", REG_SMC, 0x100100a5, &ixPCIE_LC_STATE0[0], sizeof(ixPCIE_LC_STATE0)/sizeof(ixPCIE_LC_STATE0[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE1", REG_SMC, 0x100100a6, &ixPCIE_LC_STATE1[0], sizeof(ixPCIE_LC_STATE1)/sizeof(ixPCIE_LC_STATE1[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE2", REG_SMC, 0x100100a7, &ixPCIE_LC_STATE2[0], sizeof(ixPCIE_LC_STATE2)/sizeof(ixPCIE_LC_STATE2[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE3", REG_SMC, 0x100100a8, &ixPCIE_LC_STATE3[0], sizeof(ixPCIE_LC_STATE3)/sizeof(ixPCIE_LC_STATE3[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE4", REG_SMC, 0x100100a9, &ixPCIE_LC_STATE4[0], sizeof(ixPCIE_LC_STATE4)/sizeof(ixPCIE_LC_STATE4[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE5", REG_SMC, 0x100100aa, &ixPCIE_LC_STATE5[0], sizeof(ixPCIE_LC_STATE5)/sizeof(ixPCIE_LC_STATE5[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL2", REG_SMC, 0x100100b1, &ixPCIE_LC_CNTL2[0], sizeof(ixPCIE_LC_CNTL2)/sizeof(ixPCIE_LC_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_LC_BW_CHANGE_CNTL", REG_SMC, 0x100100b2, &ixPCIE_LC_BW_CHANGE_CNTL[0], sizeof(ixPCIE_LC_BW_CHANGE_CNTL)/sizeof(ixPCIE_LC_BW_CHANGE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_CDR_CNTL", REG_SMC, 0x100100b3, &ixPCIE_LC_CDR_CNTL[0], sizeof(ixPCIE_LC_CDR_CNTL)/sizeof(ixPCIE_LC_CDR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_LANE_CNTL", REG_SMC, 0x100100b4, &ixPCIE_LC_LANE_CNTL[0], sizeof(ixPCIE_LC_LANE_CNTL)/sizeof(ixPCIE_LC_LANE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL3", REG_SMC, 0x100100b5, &ixPCIE_LC_CNTL3[0], sizeof(ixPCIE_LC_CNTL3)/sizeof(ixPCIE_LC_CNTL3[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL4", REG_SMC, 0x100100b6, &ixPCIE_LC_CNTL4[0], sizeof(ixPCIE_LC_CNTL4)/sizeof(ixPCIE_LC_CNTL4[0]), 0, 0 },
+	{ "ixPCIE_LC_CNTL5", REG_SMC, 0x100100b7, &ixPCIE_LC_CNTL5[0], sizeof(ixPCIE_LC_CNTL5)/sizeof(ixPCIE_LC_CNTL5[0]), 0, 0 },
+	{ "ixPCIE_LC_FORCE_COEFF", REG_SMC, 0x100100b8, &ixPCIE_LC_FORCE_COEFF[0], sizeof(ixPCIE_LC_FORCE_COEFF)/sizeof(ixPCIE_LC_FORCE_COEFF[0]), 0, 0 },
+	{ "ixPCIE_LC_BEST_EQ_SETTINGS", REG_SMC, 0x100100b9, &ixPCIE_LC_BEST_EQ_SETTINGS[0], sizeof(ixPCIE_LC_BEST_EQ_SETTINGS)/sizeof(ixPCIE_LC_BEST_EQ_SETTINGS[0]), 0, 0 },
+	{ "ixPCIE_LC_FORCE_EQ_REQ_COEFF", REG_SMC, 0x100100ba, &ixPCIE_LC_FORCE_EQ_REQ_COEFF[0], sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF)/sizeof(ixPCIE_LC_FORCE_EQ_REQ_COEFF[0]), 0, 0 },
+	{ "ixPCIEP_STRAP_LC", REG_SMC, 0x100100c0, &ixPCIEP_STRAP_LC[0], sizeof(ixPCIEP_STRAP_LC)/sizeof(ixPCIEP_STRAP_LC[0]), 0, 0 },
+	{ "ixPCIEP_STRAP_MISC", REG_SMC, 0x100100c1, &ixPCIEP_STRAP_MISC[0], sizeof(ixPCIEP_STRAP_MISC)/sizeof(ixPCIEP_STRAP_MISC[0]), 0, 0 },
+	{ "ixPCIEP_BCH_ECC_CNTL", REG_SMC, 0x100100d0, &ixPCIEP_BCH_ECC_CNTL[0], sizeof(ixPCIEP_BCH_ECC_CNTL)/sizeof(ixPCIEP_BCH_ECC_CNTL[0]), 0, 0 },
+	{ "ixRFE_SOFTRST_CNTL", REG_SMC, 0x1080001, &ixRFE_SOFTRST_CNTL[0], sizeof(ixRFE_SOFTRST_CNTL)/sizeof(ixRFE_SOFTRST_CNTL[0]), 0, 0 },
+	{ "ixRFE_CLIENT_SOFTRST_TRIGGER", REG_SMC, 0x1080004, &ixRFE_CLIENT_SOFTRST_TRIGGER[0], sizeof(ixRFE_CLIENT_SOFTRST_TRIGGER)/sizeof(ixRFE_CLIENT_SOFTRST_TRIGGER[0]), 0, 0 },
+	{ "ixRFE_MASTER_SOFTRST_TRIGGER", REG_SMC, 0x1080005, &ixRFE_MASTER_SOFTRST_TRIGGER[0], sizeof(ixRFE_MASTER_SOFTRST_TRIGGER)/sizeof(ixRFE_MASTER_SOFTRST_TRIGGER[0]), 0, 0 },
+	{ "ixRFE_PWDN_COMMAND", REG_SMC, 0x1080010, &ixRFE_PWDN_COMMAND[0], sizeof(ixRFE_PWDN_COMMAND)/sizeof(ixRFE_PWDN_COMMAND[0]), 0, 0 },
+	{ "ixRFE_PWDN_STATUS", REG_SMC, 0x1080011, &ixRFE_PWDN_STATUS[0], sizeof(ixRFE_PWDN_STATUS)/sizeof(ixRFE_PWDN_STATUS[0]), 0, 0 },
+	{ "ixRFE_MST_PCIEW0_CMDSTATUS", REG_SMC, 0x1080020, &ixRFE_MST_PCIEW0_CMDSTATUS[0], sizeof(ixRFE_MST_PCIEW0_CMDSTATUS)/sizeof(ixRFE_MST_PCIEW0_CMDSTATUS[0]), 0, 0 },
+	{ "ixRFE_MST_PCIEW1_CMDSTATUS", REG_SMC, 0x1080021, &ixRFE_MST_PCIEW1_CMDSTATUS[0], sizeof(ixRFE_MST_PCIEW1_CMDSTATUS)/sizeof(ixRFE_MST_PCIEW1_CMDSTATUS[0]), 0, 0 },
+	{ "ixRFE_MST_RWREG_RFEWRC_CMDSTATUS", REG_SMC, 0x1080022, &ixRFE_MST_RWREG_RFEWRC_CMDSTATUS[0], sizeof(ixRFE_MST_RWREG_RFEWRC_CMDSTATUS)/sizeof(ixRFE_MST_RWREG_RFEWRC_CMDSTATUS[0]), 0, 0 },
+	{ "ixRFE_MST_TMOUT_STATUS", REG_SMC, 0x108003f, &ixRFE_MST_TMOUT_STATUS[0], sizeof(ixRFE_MST_TMOUT_STATUS)/sizeof(ixRFE_MST_TMOUT_STATUS[0]), 0, 0 },
+	{ "ixRFE_IMPARBH_CONTROL", REG_SMC, 0x1080083, &ixRFE_IMPARBH_CONTROL[0], sizeof(ixRFE_IMPARBH_CONTROL)/sizeof(ixRFE_IMPARBH_CONTROL[0]), 0, 0 },
+	{ "ixRFE_IMPARBH_STATUS", REG_SMC, 0x1085140, &ixRFE_IMPARBH_STATUS[0], sizeof(ixRFE_IMPARBH_STATUS)/sizeof(ixRFE_IMPARBH_STATUS[0]), 0, 0 },
+	{ "ixRFE_IMPRST_CNTL", REG_SMC, 0x1085160, &ixRFE_IMPRST_CNTL[0], sizeof(ixRFE_IMPRST_CNTL)/sizeof(ixRFE_IMPRST_CNTL[0]), 0, 0 },
+	{ "ixRFE_WARMRST_CNTL", REG_SMC, 0x1085164, &ixRFE_WARMRST_CNTL[0], sizeof(ixRFE_WARMRST_CNTL)/sizeof(ixRFE_WARMRST_CNTL[0]), 0, 0 },
+	{ "ixMM_INDEX_IND", REG_SMC, 0x1090000, &ixMM_INDEX_IND[0], sizeof(ixMM_INDEX_IND)/sizeof(ixMM_INDEX_IND[0]), 0, 0 },
+	{ "ixMM_DATA_IND", REG_SMC, 0x1090001, &ixMM_DATA_IND[0], sizeof(ixMM_DATA_IND)/sizeof(ixMM_DATA_IND[0]), 0, 0 },
+	{ "ixMM_INDEX_HI_IND", REG_SMC, 0x1090006, &ixMM_INDEX_HI_IND[0], sizeof(ixMM_INDEX_HI_IND)/sizeof(ixMM_INDEX_HI_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_0_IND", REG_SMC, 0x10905c9, &ixBIOS_SCRATCH_0_IND[0], sizeof(ixBIOS_SCRATCH_0_IND)/sizeof(ixBIOS_SCRATCH_0_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_1_IND", REG_SMC, 0x10905ca, &ixBIOS_SCRATCH_1_IND[0], sizeof(ixBIOS_SCRATCH_1_IND)/sizeof(ixBIOS_SCRATCH_1_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_2_IND", REG_SMC, 0x10905cb, &ixBIOS_SCRATCH_2_IND[0], sizeof(ixBIOS_SCRATCH_2_IND)/sizeof(ixBIOS_SCRATCH_2_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_3_IND", REG_SMC, 0x10905cc, &ixBIOS_SCRATCH_3_IND[0], sizeof(ixBIOS_SCRATCH_3_IND)/sizeof(ixBIOS_SCRATCH_3_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_4_IND", REG_SMC, 0x10905cd, &ixBIOS_SCRATCH_4_IND[0], sizeof(ixBIOS_SCRATCH_4_IND)/sizeof(ixBIOS_SCRATCH_4_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_5_IND", REG_SMC, 0x10905ce, &ixBIOS_SCRATCH_5_IND[0], sizeof(ixBIOS_SCRATCH_5_IND)/sizeof(ixBIOS_SCRATCH_5_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_6_IND", REG_SMC, 0x10905cf, &ixBIOS_SCRATCH_6_IND[0], sizeof(ixBIOS_SCRATCH_6_IND)/sizeof(ixBIOS_SCRATCH_6_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_7_IND", REG_SMC, 0x10905d0, &ixBIOS_SCRATCH_7_IND[0], sizeof(ixBIOS_SCRATCH_7_IND)/sizeof(ixBIOS_SCRATCH_7_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_8_IND", REG_SMC, 0x10905d1, &ixBIOS_SCRATCH_8_IND[0], sizeof(ixBIOS_SCRATCH_8_IND)/sizeof(ixBIOS_SCRATCH_8_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_9_IND", REG_SMC, 0x10905d2, &ixBIOS_SCRATCH_9_IND[0], sizeof(ixBIOS_SCRATCH_9_IND)/sizeof(ixBIOS_SCRATCH_9_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_10_IND", REG_SMC, 0x10905d3, &ixBIOS_SCRATCH_10_IND[0], sizeof(ixBIOS_SCRATCH_10_IND)/sizeof(ixBIOS_SCRATCH_10_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_11_IND", REG_SMC, 0x10905d4, &ixBIOS_SCRATCH_11_IND[0], sizeof(ixBIOS_SCRATCH_11_IND)/sizeof(ixBIOS_SCRATCH_11_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_12_IND", REG_SMC, 0x10905d5, &ixBIOS_SCRATCH_12_IND[0], sizeof(ixBIOS_SCRATCH_12_IND)/sizeof(ixBIOS_SCRATCH_12_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_13_IND", REG_SMC, 0x10905d6, &ixBIOS_SCRATCH_13_IND[0], sizeof(ixBIOS_SCRATCH_13_IND)/sizeof(ixBIOS_SCRATCH_13_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_14_IND", REG_SMC, 0x10905d7, &ixBIOS_SCRATCH_14_IND[0], sizeof(ixBIOS_SCRATCH_14_IND)/sizeof(ixBIOS_SCRATCH_14_IND[0]), 0, 0 },
+	{ "ixBIOS_SCRATCH_15_IND", REG_SMC, 0x10905d8, &ixBIOS_SCRATCH_15_IND[0], sizeof(ixBIOS_SCRATCH_15_IND)/sizeof(ixBIOS_SCRATCH_15_IND[0]), 0, 0 },
+	{ "ixGARLIC_FLUSH_CNTL_IND", REG_SMC, 0x1091401, &ixGARLIC_FLUSH_CNTL_IND[0], sizeof(ixGARLIC_FLUSH_CNTL_IND)/sizeof(ixGARLIC_FLUSH_CNTL_IND[0]), 0, 0 },
+	{ "ixGARLIC_FLUSH_REQ_IND", REG_SMC, 0x1091412, &ixGARLIC_FLUSH_REQ_IND[0], sizeof(ixGARLIC_FLUSH_REQ_IND)/sizeof(ixGARLIC_FLUSH_REQ_IND[0]), 0, 0 },
+	{ "ixGPU_GARLIC_FLUSH_REQ_IND", REG_SMC, 0x1091413, &ixGPU_GARLIC_FLUSH_REQ_IND[0], sizeof(ixGPU_GARLIC_FLUSH_REQ_IND)/sizeof(ixGPU_GARLIC_FLUSH_REQ_IND[0]), 0, 0 },
+	{ "ixGPU_GARLIC_FLUSH_DONE_IND", REG_SMC, 0x1091414, &ixGPU_GARLIC_FLUSH_DONE_IND[0], sizeof(ixGPU_GARLIC_FLUSH_DONE_IND)/sizeof(ixGPU_GARLIC_FLUSH_DONE_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_CP_RB0_WPTR_IND", REG_SMC, 0x1091415, &ixGARLIC_COHE_CP_RB0_WPTR_IND[0], sizeof(ixGARLIC_COHE_CP_RB0_WPTR_IND)/sizeof(ixGARLIC_COHE_CP_RB0_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_CP_RB1_WPTR_IND", REG_SMC, 0x1091416, &ixGARLIC_COHE_CP_RB1_WPTR_IND[0], sizeof(ixGARLIC_COHE_CP_RB1_WPTR_IND)/sizeof(ixGARLIC_COHE_CP_RB1_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_CP_RB2_WPTR_IND", REG_SMC, 0x1091417, &ixGARLIC_COHE_CP_RB2_WPTR_IND[0], sizeof(ixGARLIC_COHE_CP_RB2_WPTR_IND)/sizeof(ixGARLIC_COHE_CP_RB2_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND", REG_SMC, 0x1091418, &ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_UVD_RBC_RB_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND", REG_SMC, 0x1091419, &ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_SDMA0_GFX_RB_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND", REG_SMC, 0x109141a, &ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_SDMA1_GFX_RB_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND", REG_SMC, 0x109141b, &ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND[0], sizeof(ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND)/sizeof(ixGARLIC_COHE_CP_DMA_ME_COMMAND_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND", REG_SMC, 0x109141c, &ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND[0], sizeof(ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND)/sizeof(ixGARLIC_COHE_CP_DMA_PFP_COMMAND_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND", REG_SMC, 0x109141d, &ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND[0], sizeof(ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND)/sizeof(ixGARLIC_COHE_SAM_SAB_RBI_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND", REG_SMC, 0x109141e, &ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND[0], sizeof(ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND)/sizeof(ixGARLIC_COHE_SAM_SAB_RBO_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND", REG_SMC, 0x109141f, &ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_VCE_OUT_RB_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_VCE_RB_WPTR2_IND", REG_SMC, 0x1091420, &ixGARLIC_COHE_VCE_RB_WPTR2_IND[0], sizeof(ixGARLIC_COHE_VCE_RB_WPTR2_IND)/sizeof(ixGARLIC_COHE_VCE_RB_WPTR2_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_VCE_RB_WPTR_IND", REG_SMC, 0x1091421, &ixGARLIC_COHE_VCE_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_VCE_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_VCE_RB_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND", REG_SMC, 0x1091422, &ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_SDMA2_GFX_RB_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND", REG_SMC, 0x1091423, &ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND[0], sizeof(ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND)/sizeof(ixGARLIC_COHE_SDMA3_GFX_RB_WPTR_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND", REG_SMC, 0x1091424, &ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND[0], sizeof(ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND)/sizeof(ixGARLIC_COHE_CP_DMA_PIO_COMMAND_IND[0]), 0, 0 },
+	{ "ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND", REG_SMC, 0x1091425, &ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND[0], sizeof(ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND)/sizeof(ixGARLIC_COHE_GARLIC_FLUSH_REQ_IND[0]), 0, 0 },
+	{ "ixREMAP_HDP_MEM_FLUSH_CNTL_IND", REG_SMC, 0x1091426, &ixREMAP_HDP_MEM_FLUSH_CNTL_IND[0], sizeof(ixREMAP_HDP_MEM_FLUSH_CNTL_IND)/sizeof(ixREMAP_HDP_MEM_FLUSH_CNTL_IND[0]), 0, 0 },
+	{ "ixREMAP_HDP_REG_FLUSH_CNTL_IND", REG_SMC, 0x1091427, &ixREMAP_HDP_REG_FLUSH_CNTL_IND[0], sizeof(ixREMAP_HDP_REG_FLUSH_CNTL_IND)/sizeof(ixREMAP_HDP_REG_FLUSH_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX0_LOWER_IND", REG_SMC, 0x1091428, &ixBIF_VDDGFX_GFX0_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX0_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX0_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX0_UPPER_IND", REG_SMC, 0x1091429, &ixBIF_VDDGFX_GFX0_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX0_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX0_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX1_LOWER_IND", REG_SMC, 0x109142a, &ixBIF_VDDGFX_GFX1_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX1_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX1_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX1_UPPER_IND", REG_SMC, 0x109142b, &ixBIF_VDDGFX_GFX1_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX1_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX1_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX2_LOWER_IND", REG_SMC, 0x109142c, &ixBIF_VDDGFX_GFX2_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX2_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX2_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX2_UPPER_IND", REG_SMC, 0x109142d, &ixBIF_VDDGFX_GFX2_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX2_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX2_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX3_LOWER_IND", REG_SMC, 0x109142e, &ixBIF_VDDGFX_GFX3_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX3_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX3_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX3_UPPER_IND", REG_SMC, 0x109142f, &ixBIF_VDDGFX_GFX3_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX3_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX3_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX4_LOWER_IND", REG_SMC, 0x1091430, &ixBIF_VDDGFX_GFX4_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX4_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX4_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX4_UPPER_IND", REG_SMC, 0x1091431, &ixBIF_VDDGFX_GFX4_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX4_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX4_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX5_LOWER_IND", REG_SMC, 0x1091432, &ixBIF_VDDGFX_GFX5_LOWER_IND[0], sizeof(ixBIF_VDDGFX_GFX5_LOWER_IND)/sizeof(ixBIF_VDDGFX_GFX5_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_GFX5_UPPER_IND", REG_SMC, 0x1091433, &ixBIF_VDDGFX_GFX5_UPPER_IND[0], sizeof(ixBIF_VDDGFX_GFX5_UPPER_IND)/sizeof(ixBIF_VDDGFX_GFX5_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_RSV1_LOWER_IND", REG_SMC, 0x1091434, &ixBIF_VDDGFX_RSV1_LOWER_IND[0], sizeof(ixBIF_VDDGFX_RSV1_LOWER_IND)/sizeof(ixBIF_VDDGFX_RSV1_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_RSV1_UPPER_IND", REG_SMC, 0x1091435, &ixBIF_VDDGFX_RSV1_UPPER_IND[0], sizeof(ixBIF_VDDGFX_RSV1_UPPER_IND)/sizeof(ixBIF_VDDGFX_RSV1_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_RSV2_LOWER_IND", REG_SMC, 0x1091436, &ixBIF_VDDGFX_RSV2_LOWER_IND[0], sizeof(ixBIF_VDDGFX_RSV2_LOWER_IND)/sizeof(ixBIF_VDDGFX_RSV2_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_RSV2_UPPER_IND", REG_SMC, 0x1091437, &ixBIF_VDDGFX_RSV2_UPPER_IND[0], sizeof(ixBIF_VDDGFX_RSV2_UPPER_IND)/sizeof(ixBIF_VDDGFX_RSV2_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_RSV3_LOWER_IND", REG_SMC, 0x1091438, &ixBIF_VDDGFX_RSV3_LOWER_IND[0], sizeof(ixBIF_VDDGFX_RSV3_LOWER_IND)/sizeof(ixBIF_VDDGFX_RSV3_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_RSV3_UPPER_IND", REG_SMC, 0x1091439, &ixBIF_VDDGFX_RSV3_UPPER_IND[0], sizeof(ixBIF_VDDGFX_RSV3_UPPER_IND)/sizeof(ixBIF_VDDGFX_RSV3_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_RSV4_LOWER_IND", REG_SMC, 0x109143a, &ixBIF_VDDGFX_RSV4_LOWER_IND[0], sizeof(ixBIF_VDDGFX_RSV4_LOWER_IND)/sizeof(ixBIF_VDDGFX_RSV4_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_RSV4_UPPER_IND", REG_SMC, 0x109143b, &ixBIF_VDDGFX_RSV4_UPPER_IND[0], sizeof(ixBIF_VDDGFX_RSV4_UPPER_IND)/sizeof(ixBIF_VDDGFX_RSV4_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_VDDGFX_FB_CMP_IND", REG_SMC, 0x109143c, &ixBIF_VDDGFX_FB_CMP_IND[0], sizeof(ixBIF_VDDGFX_FB_CMP_IND)/sizeof(ixBIF_VDDGFX_FB_CMP_IND[0]), 0, 0 },
+	{ "ixBIF_SMU_INDEX_IND", REG_SMC, 0x109143d, &ixBIF_SMU_INDEX_IND[0], sizeof(ixBIF_SMU_INDEX_IND)/sizeof(ixBIF_SMU_INDEX_IND[0]), 0, 0 },
+	{ "ixBIF_SMU_DATA_IND", REG_SMC, 0x109143e, &ixBIF_SMU_DATA_IND[0], sizeof(ixBIF_SMU_DATA_IND)/sizeof(ixBIF_SMU_DATA_IND[0]), 0, 0 },
+	{ "ixBIF_XDMA_LO_IND", REG_SMC, 0x10914c0, &ixBIF_XDMA_LO_IND[0], sizeof(ixBIF_XDMA_LO_IND)/sizeof(ixBIF_XDMA_LO_IND[0]), 0, 0 },
+	{ "ixBIF_XDMA_HI_IND", REG_SMC, 0x10914c1, &ixBIF_XDMA_HI_IND[0], sizeof(ixBIF_XDMA_HI_IND)/sizeof(ixBIF_XDMA_HI_IND[0]), 0, 0 },
+	{ "ixBIF_FEATURES_CONTROL_MISC_IND", REG_SMC, 0x10914c2, &ixBIF_FEATURES_CONTROL_MISC_IND[0], sizeof(ixBIF_FEATURES_CONTROL_MISC_IND)/sizeof(ixBIF_FEATURES_CONTROL_MISC_IND[0]), 0, 0 },
+	{ "ixBIF_DOORBELL_CNTL_IND", REG_SMC, 0x10914c3, &ixBIF_DOORBELL_CNTL_IND[0], sizeof(ixBIF_DOORBELL_CNTL_IND)/sizeof(ixBIF_DOORBELL_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_SLVARB_MODE_IND", REG_SMC, 0x10914c4, &ixBIF_SLVARB_MODE_IND[0], sizeof(ixBIF_SLVARB_MODE_IND)/sizeof(ixBIF_SLVARB_MODE_IND[0]), 0, 0 },
+	{ "ixSMBUS_BACO_DUMMY_IND", REG_SMC, 0x10914c6, &ixSMBUS_BACO_DUMMY_IND[0], sizeof(ixSMBUS_BACO_DUMMY_IND)/sizeof(ixSMBUS_BACO_DUMMY_IND[0]), 0, 0 },
+	{ "ixBF_ANA_ISO_CNTL_IND", REG_SMC, 0x10914c7, &ixBF_ANA_ISO_CNTL_IND[0], sizeof(ixBF_ANA_ISO_CNTL_IND)/sizeof(ixBF_ANA_ISO_CNTL_IND[0]), 0, 0 },
+	{ "ixBACO_CNTL_MISC_IND", REG_SMC, 0x10914db, &ixBACO_CNTL_MISC_IND[0], sizeof(ixBACO_CNTL_MISC_IND)/sizeof(ixBACO_CNTL_MISC_IND[0]), 0, 0 },
+	{ "ixBIF_BACO_DEBUG_LATCH_IND", REG_SMC, 0x10914dc, &ixBIF_BACO_DEBUG_LATCH_IND[0], sizeof(ixBIF_BACO_DEBUG_LATCH_IND)/sizeof(ixBIF_BACO_DEBUG_LATCH_IND[0]), 0, 0 },
+	{ "ixBIF_BACO_DEBUG_IND", REG_SMC, 0x10914df, &ixBIF_BACO_DEBUG_IND[0], sizeof(ixBIF_BACO_DEBUG_IND)/sizeof(ixBIF_BACO_DEBUG_IND[0]), 0, 0 },
+	{ "ixMEM_TYPE_CNTL_IND", REG_SMC, 0x10914e4, &ixMEM_TYPE_CNTL_IND[0], sizeof(ixMEM_TYPE_CNTL_IND)/sizeof(ixMEM_TYPE_CNTL_IND[0]), 0, 0 },
+	{ "ixBACO_CNTL_IND", REG_SMC, 0x10914e5, &ixBACO_CNTL_IND[0], sizeof(ixBACO_CNTL_IND)/sizeof(ixBACO_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_DEVFUNCNUM_LIST1_IND", REG_SMC, 0x10914e7, &ixBIF_DEVFUNCNUM_LIST1_IND[0], sizeof(ixBIF_DEVFUNCNUM_LIST1_IND)/sizeof(ixBIF_DEVFUNCNUM_LIST1_IND[0]), 0, 0 },
+	{ "ixBIF_DEVFUNCNUM_LIST0_IND", REG_SMC, 0x10914e8, &ixBIF_DEVFUNCNUM_LIST0_IND[0], sizeof(ixBIF_DEVFUNCNUM_LIST0_IND)/sizeof(ixBIF_DEVFUNCNUM_LIST0_IND[0]), 0, 0 },
+	{ "ixDBG_BYPASS_SRBM_ACCESS_IND", REG_SMC, 0x10914eb, &ixDBG_BYPASS_SRBM_ACCESS_IND[0], sizeof(ixDBG_BYPASS_SRBM_ACCESS_IND)/sizeof(ixDBG_BYPASS_SRBM_ACCESS_IND[0]), 0, 0 },
+	{ "ixPEER3_FB_OFFSET_LO_IND", REG_SMC, 0x10914ec, &ixPEER3_FB_OFFSET_LO_IND[0], sizeof(ixPEER3_FB_OFFSET_LO_IND)/sizeof(ixPEER3_FB_OFFSET_LO_IND[0]), 0, 0 },
+	{ "ixPEER3_FB_OFFSET_HI_IND", REG_SMC, 0x10914ed, &ixPEER3_FB_OFFSET_HI_IND[0], sizeof(ixPEER3_FB_OFFSET_HI_IND)/sizeof(ixPEER3_FB_OFFSET_HI_IND[0]), 0, 0 },
+	{ "ixPEER2_FB_OFFSET_LO_IND", REG_SMC, 0x10914ee, &ixPEER2_FB_OFFSET_LO_IND[0], sizeof(ixPEER2_FB_OFFSET_LO_IND)/sizeof(ixPEER2_FB_OFFSET_LO_IND[0]), 0, 0 },
+	{ "ixPEER2_FB_OFFSET_HI_IND", REG_SMC, 0x10914ef, &ixPEER2_FB_OFFSET_HI_IND[0], sizeof(ixPEER2_FB_OFFSET_HI_IND)/sizeof(ixPEER2_FB_OFFSET_HI_IND[0]), 0, 0 },
+	{ "ixPEER1_FB_OFFSET_LO_IND", REG_SMC, 0x10914f0, &ixPEER1_FB_OFFSET_LO_IND[0], sizeof(ixPEER1_FB_OFFSET_LO_IND)/sizeof(ixPEER1_FB_OFFSET_LO_IND[0]), 0, 0 },
+	{ "ixPEER1_FB_OFFSET_HI_IND", REG_SMC, 0x10914f1, &ixPEER1_FB_OFFSET_HI_IND[0], sizeof(ixPEER1_FB_OFFSET_HI_IND)/sizeof(ixPEER1_FB_OFFSET_HI_IND[0]), 0, 0 },
+	{ "ixPEER0_FB_OFFSET_LO_IND", REG_SMC, 0x10914f2, &ixPEER0_FB_OFFSET_LO_IND[0], sizeof(ixPEER0_FB_OFFSET_LO_IND)/sizeof(ixPEER0_FB_OFFSET_LO_IND[0]), 0, 0 },
+	{ "ixPEER0_FB_OFFSET_HI_IND", REG_SMC, 0x10914f3, &ixPEER0_FB_OFFSET_HI_IND[0], sizeof(ixPEER0_FB_OFFSET_HI_IND)/sizeof(ixPEER0_FB_OFFSET_HI_IND[0]), 0, 0 },
+	{ "ixIMPCTL_RESET_IND", REG_SMC, 0x10914f5, &ixIMPCTL_RESET_IND[0], sizeof(ixIMPCTL_RESET_IND)/sizeof(ixIMPCTL_RESET_IND[0]), 0, 0 },
+	{ "ixSMU_BIF_VDDGFX_PWR_STATUS_IND", REG_SMC, 0x10914f8, &ixSMU_BIF_VDDGFX_PWR_STATUS_IND[0], sizeof(ixSMU_BIF_VDDGFX_PWR_STATUS_IND)/sizeof(ixSMU_BIF_VDDGFX_PWR_STATUS_IND[0]), 0, 0 },
+	{ "ixBIF_DOORBELL_GBLAPER1_LOWER_IND", REG_SMC, 0x10914fc, &ixBIF_DOORBELL_GBLAPER1_LOWER_IND[0], sizeof(ixBIF_DOORBELL_GBLAPER1_LOWER_IND)/sizeof(ixBIF_DOORBELL_GBLAPER1_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_DOORBELL_GBLAPER1_UPPER_IND", REG_SMC, 0x10914fd, &ixBIF_DOORBELL_GBLAPER1_UPPER_IND[0], sizeof(ixBIF_DOORBELL_GBLAPER1_UPPER_IND)/sizeof(ixBIF_DOORBELL_GBLAPER1_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_DOORBELL_GBLAPER2_LOWER_IND", REG_SMC, 0x10914fe, &ixBIF_DOORBELL_GBLAPER2_LOWER_IND[0], sizeof(ixBIF_DOORBELL_GBLAPER2_LOWER_IND)/sizeof(ixBIF_DOORBELL_GBLAPER2_LOWER_IND[0]), 0, 0 },
+	{ "ixBIF_DOORBELL_GBLAPER2_UPPER_IND", REG_SMC, 0x10914ff, &ixBIF_DOORBELL_GBLAPER2_UPPER_IND[0], sizeof(ixBIF_DOORBELL_GBLAPER2_UPPER_IND)/sizeof(ixBIF_DOORBELL_GBLAPER2_UPPER_IND[0]), 0, 0 },
+	{ "ixBIF_MM_INDACCESS_CNTL_IND", REG_SMC, 0x1091500, &ixBIF_MM_INDACCESS_CNTL_IND[0], sizeof(ixBIF_MM_INDACCESS_CNTL_IND)/sizeof(ixBIF_MM_INDACCESS_CNTL_IND[0]), 0, 0 },
+	{ "ixBUS_CNTL_IND", REG_SMC, 0x1091508, &ixBUS_CNTL_IND[0], sizeof(ixBUS_CNTL_IND)/sizeof(ixBUS_CNTL_IND[0]), 0, 0 },
+	{ "ixCONFIG_CNTL_IND", REG_SMC, 0x1091509, &ixCONFIG_CNTL_IND[0], sizeof(ixCONFIG_CNTL_IND)/sizeof(ixCONFIG_CNTL_IND[0]), 0, 0 },
+	{ "ixCONFIG_MEMSIZE_IND", REG_SMC, 0x109150a, &ixCONFIG_MEMSIZE_IND[0], sizeof(ixCONFIG_MEMSIZE_IND)/sizeof(ixCONFIG_MEMSIZE_IND[0]), 0, 0 },
+	{ "ixCONFIG_F0_BASE_IND", REG_SMC, 0x109150b, &ixCONFIG_F0_BASE_IND[0], sizeof(ixCONFIG_F0_BASE_IND)/sizeof(ixCONFIG_F0_BASE_IND[0]), 0, 0 },
+	{ "ixCONFIG_APER_SIZE_IND", REG_SMC, 0x109150c, &ixCONFIG_APER_SIZE_IND[0], sizeof(ixCONFIG_APER_SIZE_IND)/sizeof(ixCONFIG_APER_SIZE_IND[0]), 0, 0 },
+	{ "ixCONFIG_REG_APER_SIZE_IND", REG_SMC, 0x109150d, &ixCONFIG_REG_APER_SIZE_IND[0], sizeof(ixCONFIG_REG_APER_SIZE_IND)/sizeof(ixCONFIG_REG_APER_SIZE_IND[0]), 0, 0 },
+	{ "ixBIF_SCRATCH0_IND", REG_SMC, 0x109150e, &ixBIF_SCRATCH0_IND[0], sizeof(ixBIF_SCRATCH0_IND)/sizeof(ixBIF_SCRATCH0_IND[0]), 0, 0 },
+	{ "ixBIF_SCRATCH1_IND", REG_SMC, 0x109150f, &ixBIF_SCRATCH1_IND[0], sizeof(ixBIF_SCRATCH1_IND)/sizeof(ixBIF_SCRATCH1_IND[0]), 0, 0 },
+	{ "ixMM_CFGREGS_CNTL_IND", REG_SMC, 0x1091513, &ixMM_CFGREGS_CNTL_IND[0], sizeof(ixMM_CFGREGS_CNTL_IND)/sizeof(ixMM_CFGREGS_CNTL_IND[0]), 0, 0 },
+	{ "ixBX_RESET_EN_IND", REG_SMC, 0x1091514, &ixBX_RESET_EN_IND[0], sizeof(ixBX_RESET_EN_IND)/sizeof(ixBX_RESET_EN_IND[0]), 0, 0 },
+	{ "ixHW_DEBUG_IND", REG_SMC, 0x1091515, &ixHW_DEBUG_IND[0], sizeof(ixHW_DEBUG_IND)/sizeof(ixHW_DEBUG_IND[0]), 0, 0 },
+	{ "ixMASTER_CREDIT_CNTL_IND", REG_SMC, 0x1091516, &ixMASTER_CREDIT_CNTL_IND[0], sizeof(ixMASTER_CREDIT_CNTL_IND)/sizeof(ixMASTER_CREDIT_CNTL_IND[0]), 0, 0 },
+	{ "ixSLAVE_REQ_CREDIT_CNTL_IND", REG_SMC, 0x1091517, &ixSLAVE_REQ_CREDIT_CNTL_IND[0], sizeof(ixSLAVE_REQ_CREDIT_CNTL_IND)/sizeof(ixSLAVE_REQ_CREDIT_CNTL_IND[0]), 0, 0 },
+	{ "ixBX_RESET_CNTL_IND", REG_SMC, 0x1091518, &ixBX_RESET_CNTL_IND[0], sizeof(ixBX_RESET_CNTL_IND)/sizeof(ixBX_RESET_CNTL_IND[0]), 0, 0 },
+	{ "ixINTERRUPT_CNTL_IND", REG_SMC, 0x109151a, &ixINTERRUPT_CNTL_IND[0], sizeof(ixINTERRUPT_CNTL_IND)/sizeof(ixINTERRUPT_CNTL_IND[0]), 0, 0 },
+	{ "ixINTERRUPT_CNTL2_IND", REG_SMC, 0x109151b, &ixINTERRUPT_CNTL2_IND[0], sizeof(ixINTERRUPT_CNTL2_IND)/sizeof(ixINTERRUPT_CNTL2_IND[0]), 0, 0 },
+	{ "ixBIF_DEBUG_CNTL_IND", REG_SMC, 0x109151c, &ixBIF_DEBUG_CNTL_IND[0], sizeof(ixBIF_DEBUG_CNTL_IND)/sizeof(ixBIF_DEBUG_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_DEBUG_MUX_IND", REG_SMC, 0x109151d, &ixBIF_DEBUG_MUX_IND[0], sizeof(ixBIF_DEBUG_MUX_IND)/sizeof(ixBIF_DEBUG_MUX_IND[0]), 0, 0 },
+	{ "ixBIF_DEBUG_OUT_IND", REG_SMC, 0x109151e, &ixBIF_DEBUG_OUT_IND[0], sizeof(ixBIF_DEBUG_OUT_IND)/sizeof(ixBIF_DEBUG_OUT_IND[0]), 0, 0 },
+	{ "ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND", REG_SMC, 0x1091520, &ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND[0], sizeof(ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND)/sizeof(ixHDP_MEM_COHERENCY_FLUSH_CNTL_IND[0]), 0, 0 },
+	{ "ixCLKREQB_PAD_CNTL_IND", REG_SMC, 0x1091521, &ixCLKREQB_PAD_CNTL_IND[0], sizeof(ixCLKREQB_PAD_CNTL_IND)/sizeof(ixCLKREQB_PAD_CNTL_IND[0]), 0, 0 },
+	{ "ixSMBDAT_PAD_CNTL_IND", REG_SMC, 0x1091522, &ixSMBDAT_PAD_CNTL_IND[0], sizeof(ixSMBDAT_PAD_CNTL_IND)/sizeof(ixSMBDAT_PAD_CNTL_IND[0]), 0, 0 },
+	{ "ixSMBCLK_PAD_CNTL_IND", REG_SMC, 0x1091523, &ixSMBCLK_PAD_CNTL_IND[0], sizeof(ixSMBCLK_PAD_CNTL_IND)/sizeof(ixSMBCLK_PAD_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_FB_EN_IND", REG_SMC, 0x1091524, &ixBIF_FB_EN_IND[0], sizeof(ixBIF_FB_EN_IND)/sizeof(ixBIF_FB_EN_IND[0]), 0, 0 },
+	{ "ixBIF_BUSNUM_CNTL1_IND", REG_SMC, 0x1091525, &ixBIF_BUSNUM_CNTL1_IND[0], sizeof(ixBIF_BUSNUM_CNTL1_IND)/sizeof(ixBIF_BUSNUM_CNTL1_IND[0]), 0, 0 },
+	{ "ixBIF_BUSNUM_LIST0_IND", REG_SMC, 0x1091526, &ixBIF_BUSNUM_LIST0_IND[0], sizeof(ixBIF_BUSNUM_LIST0_IND)/sizeof(ixBIF_BUSNUM_LIST0_IND[0]), 0, 0 },
+	{ "ixBIF_BUSNUM_LIST1_IND", REG_SMC, 0x1091527, &ixBIF_BUSNUM_LIST1_IND[0], sizeof(ixBIF_BUSNUM_LIST1_IND)/sizeof(ixBIF_BUSNUM_LIST1_IND[0]), 0, 0 },
+	{ "ixHDP_REG_COHERENCY_FLUSH_CNTL_IND", REG_SMC, 0x1091528, &ixHDP_REG_COHERENCY_FLUSH_CNTL_IND[0], sizeof(ixHDP_REG_COHERENCY_FLUSH_CNTL_IND)/sizeof(ixHDP_REG_COHERENCY_FLUSH_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_BUSY_DELAY_CNTR_IND", REG_SMC, 0x1091529, &ixBIF_BUSY_DELAY_CNTR_IND[0], sizeof(ixBIF_BUSY_DELAY_CNTR_IND)/sizeof(ixBIF_BUSY_DELAY_CNTR_IND[0]), 0, 0 },
+	{ "ixBIF_BUSNUM_CNTL2_IND", REG_SMC, 0x109152b, &ixBIF_BUSNUM_CNTL2_IND[0], sizeof(ixBIF_BUSNUM_CNTL2_IND)/sizeof(ixBIF_BUSNUM_CNTL2_IND[0]), 0, 0 },
+	{ "ixBIF_PERFMON_CNTL_IND", REG_SMC, 0x109152c, &ixBIF_PERFMON_CNTL_IND[0], sizeof(ixBIF_PERFMON_CNTL_IND)/sizeof(ixBIF_PERFMON_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_PERFCOUNTER0_RESULT_IND", REG_SMC, 0x109152d, &ixBIF_PERFCOUNTER0_RESULT_IND[0], sizeof(ixBIF_PERFCOUNTER0_RESULT_IND)/sizeof(ixBIF_PERFCOUNTER0_RESULT_IND[0]), 0, 0 },
+	{ "ixBIF_PERFCOUNTER1_RESULT_IND", REG_SMC, 0x109152e, &ixBIF_PERFCOUNTER1_RESULT_IND[0], sizeof(ixBIF_PERFCOUNTER1_RESULT_IND)/sizeof(ixBIF_PERFCOUNTER1_RESULT_IND[0]), 0, 0 },
+	{ "ixBIF_RB_CNTL_IND", REG_SMC, 0x1091530, &ixBIF_RB_CNTL_IND[0], sizeof(ixBIF_RB_CNTL_IND)/sizeof(ixBIF_RB_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_RB_BASE_IND", REG_SMC, 0x1091531, &ixBIF_RB_BASE_IND[0], sizeof(ixBIF_RB_BASE_IND)/sizeof(ixBIF_RB_BASE_IND[0]), 0, 0 },
+	{ "ixBIF_RB_RPTR_IND", REG_SMC, 0x1091532, &ixBIF_RB_RPTR_IND[0], sizeof(ixBIF_RB_RPTR_IND)/sizeof(ixBIF_RB_RPTR_IND[0]), 0, 0 },
+	{ "ixBIF_RB_WPTR_IND", REG_SMC, 0x1091533, &ixBIF_RB_WPTR_IND[0], sizeof(ixBIF_RB_WPTR_IND)/sizeof(ixBIF_RB_WPTR_IND[0]), 0, 0 },
+	{ "ixBIF_RB_WPTR_ADDR_HI_IND", REG_SMC, 0x1091534, &ixBIF_RB_WPTR_ADDR_HI_IND[0], sizeof(ixBIF_RB_WPTR_ADDR_HI_IND)/sizeof(ixBIF_RB_WPTR_ADDR_HI_IND[0]), 0, 0 },
+	{ "ixBIF_RB_WPTR_ADDR_LO_IND", REG_SMC, 0x1091535, &ixBIF_RB_WPTR_ADDR_LO_IND[0], sizeof(ixBIF_RB_WPTR_ADDR_LO_IND)/sizeof(ixBIF_RB_WPTR_ADDR_LO_IND[0]), 0, 0 },
+	{ "ixSLAVE_HANG_PROTECTION_CNTL_IND", REG_SMC, 0x1091536, &ixSLAVE_HANG_PROTECTION_CNTL_IND[0], sizeof(ixSLAVE_HANG_PROTECTION_CNTL_IND)/sizeof(ixSLAVE_HANG_PROTECTION_CNTL_IND[0]), 0, 0 },
+	{ "ixGPU_HDP_FLUSH_REQ_IND", REG_SMC, 0x1091537, &ixGPU_HDP_FLUSH_REQ_IND[0], sizeof(ixGPU_HDP_FLUSH_REQ_IND)/sizeof(ixGPU_HDP_FLUSH_REQ_IND[0]), 0, 0 },
+	{ "ixGPU_HDP_FLUSH_DONE_IND", REG_SMC, 0x1091538, &ixGPU_HDP_FLUSH_DONE_IND[0], sizeof(ixGPU_HDP_FLUSH_DONE_IND)/sizeof(ixGPU_HDP_FLUSH_DONE_IND[0]), 0, 0 },
+	{ "ixSLAVE_HANG_ERROR_IND", REG_SMC, 0x109153b, &ixSLAVE_HANG_ERROR_IND[0], sizeof(ixSLAVE_HANG_ERROR_IND)/sizeof(ixSLAVE_HANG_ERROR_IND[0]), 0, 0 },
+	{ "ixCAPTURE_HOST_BUSNUM_IND", REG_SMC, 0x109153c, &ixCAPTURE_HOST_BUSNUM_IND[0], sizeof(ixCAPTURE_HOST_BUSNUM_IND)/sizeof(ixCAPTURE_HOST_BUSNUM_IND[0]), 0, 0 },
+	{ "ixHOST_BUSNUM_IND", REG_SMC, 0x109153d, &ixHOST_BUSNUM_IND[0], sizeof(ixHOST_BUSNUM_IND)/sizeof(ixHOST_BUSNUM_IND[0]), 0, 0 },
+	{ "ixPEER_REG_RANGE0_IND", REG_SMC, 0x109153e, &ixPEER_REG_RANGE0_IND[0], sizeof(ixPEER_REG_RANGE0_IND)/sizeof(ixPEER_REG_RANGE0_IND[0]), 0, 0 },
+	{ "ixPEER_REG_RANGE1_IND", REG_SMC, 0x109153f, &ixPEER_REG_RANGE1_IND[0], sizeof(ixPEER_REG_RANGE1_IND)/sizeof(ixPEER_REG_RANGE1_IND[0]), 0, 0 },
+	{ "ixPSX80_PIF0_SCRATCH", REG_SMC, 0x1100001, &ixPSX80_PIF0_SCRATCH[0], sizeof(ixPSX80_PIF0_SCRATCH)/sizeof(ixPSX80_PIF0_SCRATCH[0]), 0, 0 },
+	{ "ixPSX80_PIF0_HW_DEBUG", REG_SMC, 0x1100002, &ixPSX80_PIF0_HW_DEBUG[0], sizeof(ixPSX80_PIF0_HW_DEBUG)/sizeof(ixPSX80_PIF0_HW_DEBUG[0]), 0, 0 },
+	{ "ixPSX80_PIF0_STRAP_0", REG_SMC, 0x1100003, &ixPSX80_PIF0_STRAP_0[0], sizeof(ixPSX80_PIF0_STRAP_0)/sizeof(ixPSX80_PIF0_STRAP_0[0]), 0, 0 },
+	{ "ixPSX80_PIF0_CTRL", REG_SMC, 0x1100004, &ixPSX80_PIF0_CTRL[0], sizeof(ixPSX80_PIF0_CTRL)/sizeof(ixPSX80_PIF0_CTRL[0]), 0, 0 },
+	{ "ixPSX80_PIF0_TX_CTRL", REG_SMC, 0x1100008, &ixPSX80_PIF0_TX_CTRL[0], sizeof(ixPSX80_PIF0_TX_CTRL)/sizeof(ixPSX80_PIF0_TX_CTRL[0]), 0, 0 },
+	{ "ixPSX80_PIF0_TX_CTRL2", REG_SMC, 0x1100009, &ixPSX80_PIF0_TX_CTRL2[0], sizeof(ixPSX80_PIF0_TX_CTRL2)/sizeof(ixPSX80_PIF0_TX_CTRL2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_RX_CTRL", REG_SMC, 0x110000a, &ixPSX80_PIF0_RX_CTRL[0], sizeof(ixPSX80_PIF0_RX_CTRL)/sizeof(ixPSX80_PIF0_RX_CTRL[0]), 0, 0 },
+	{ "ixPSX80_PIF0_RX_CTRL2", REG_SMC, 0x110000b, &ixPSX80_PIF0_RX_CTRL2[0], sizeof(ixPSX80_PIF0_RX_CTRL2)/sizeof(ixPSX80_PIF0_RX_CTRL2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_GLB_OVRD", REG_SMC, 0x110000c, &ixPSX80_PIF0_GLB_OVRD[0], sizeof(ixPSX80_PIF0_GLB_OVRD)/sizeof(ixPSX80_PIF0_GLB_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_GLB_OVRD2", REG_SMC, 0x110000d, &ixPSX80_PIF0_GLB_OVRD2[0], sizeof(ixPSX80_PIF0_GLB_OVRD2)/sizeof(ixPSX80_PIF0_GLB_OVRD2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_BIF_CMD_STATUS", REG_SMC, 0x1100010, &ixPSX80_PIF0_BIF_CMD_STATUS[0], sizeof(ixPSX80_PIF0_BIF_CMD_STATUS)/sizeof(ixPSX80_PIF0_BIF_CMD_STATUS[0]), 0, 0 },
+	{ "ixPSX80_PIF0_CMD_BUS_CTRL", REG_SMC, 0x1100011, &ixPSX80_PIF0_CMD_BUS_CTRL[0], sizeof(ixPSX80_PIF0_CMD_BUS_CTRL)/sizeof(ixPSX80_PIF0_CMD_BUS_CTRL[0]), 0, 0 },
+	{ "ixPSX80_PIF0_CMD_BUS_GLB_OVRD", REG_SMC, 0x1100013, &ixPSX80_PIF0_CMD_BUS_GLB_OVRD[0], sizeof(ixPSX80_PIF0_CMD_BUS_GLB_OVRD)/sizeof(ixPSX80_PIF0_CMD_BUS_GLB_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE0_OVRD", REG_SMC, 0x1100014, &ixPSX80_PIF0_LANE0_OVRD[0], sizeof(ixPSX80_PIF0_LANE0_OVRD)/sizeof(ixPSX80_PIF0_LANE0_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE0_OVRD2", REG_SMC, 0x1100015, &ixPSX80_PIF0_LANE0_OVRD2[0], sizeof(ixPSX80_PIF0_LANE0_OVRD2)/sizeof(ixPSX80_PIF0_LANE0_OVRD2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE1_OVRD", REG_SMC, 0x1100016, &ixPSX80_PIF0_LANE1_OVRD[0], sizeof(ixPSX80_PIF0_LANE1_OVRD)/sizeof(ixPSX80_PIF0_LANE1_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE1_OVRD2", REG_SMC, 0x1100017, &ixPSX80_PIF0_LANE1_OVRD2[0], sizeof(ixPSX80_PIF0_LANE1_OVRD2)/sizeof(ixPSX80_PIF0_LANE1_OVRD2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE2_OVRD", REG_SMC, 0x1100018, &ixPSX80_PIF0_LANE2_OVRD[0], sizeof(ixPSX80_PIF0_LANE2_OVRD)/sizeof(ixPSX80_PIF0_LANE2_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE2_OVRD2", REG_SMC, 0x1100019, &ixPSX80_PIF0_LANE2_OVRD2[0], sizeof(ixPSX80_PIF0_LANE2_OVRD2)/sizeof(ixPSX80_PIF0_LANE2_OVRD2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE3_OVRD", REG_SMC, 0x110001a, &ixPSX80_PIF0_LANE3_OVRD[0], sizeof(ixPSX80_PIF0_LANE3_OVRD)/sizeof(ixPSX80_PIF0_LANE3_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE3_OVRD2", REG_SMC, 0x110001b, &ixPSX80_PIF0_LANE3_OVRD2[0], sizeof(ixPSX80_PIF0_LANE3_OVRD2)/sizeof(ixPSX80_PIF0_LANE3_OVRD2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE4_OVRD", REG_SMC, 0x110001c, &ixPSX80_PIF0_LANE4_OVRD[0], sizeof(ixPSX80_PIF0_LANE4_OVRD)/sizeof(ixPSX80_PIF0_LANE4_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE4_OVRD2", REG_SMC, 0x110001d, &ixPSX80_PIF0_LANE4_OVRD2[0], sizeof(ixPSX80_PIF0_LANE4_OVRD2)/sizeof(ixPSX80_PIF0_LANE4_OVRD2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE5_OVRD", REG_SMC, 0x110001e, &ixPSX80_PIF0_LANE5_OVRD[0], sizeof(ixPSX80_PIF0_LANE5_OVRD)/sizeof(ixPSX80_PIF0_LANE5_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE5_OVRD2", REG_SMC, 0x110001f, &ixPSX80_PIF0_LANE5_OVRD2[0], sizeof(ixPSX80_PIF0_LANE5_OVRD2)/sizeof(ixPSX80_PIF0_LANE5_OVRD2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE6_OVRD", REG_SMC, 0x1100020, &ixPSX80_PIF0_LANE6_OVRD[0], sizeof(ixPSX80_PIF0_LANE6_OVRD)/sizeof(ixPSX80_PIF0_LANE6_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE6_OVRD2", REG_SMC, 0x1100021, &ixPSX80_PIF0_LANE6_OVRD2[0], sizeof(ixPSX80_PIF0_LANE6_OVRD2)/sizeof(ixPSX80_PIF0_LANE6_OVRD2[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE7_OVRD", REG_SMC, 0x1100022, &ixPSX80_PIF0_LANE7_OVRD[0], sizeof(ixPSX80_PIF0_LANE7_OVRD)/sizeof(ixPSX80_PIF0_LANE7_OVRD[0]), 0, 0 },
+	{ "ixPSX80_PIF0_LANE7_OVRD2", REG_SMC, 0x1100023, &ixPSX80_PIF0_LANE7_OVRD2[0], sizeof(ixPSX80_PIF0_LANE7_OVRD2)/sizeof(ixPSX80_PIF0_LANE7_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_SCRATCH", REG_SMC, 0x1110001, &ixPSX81_PIF0_SCRATCH[0], sizeof(ixPSX81_PIF0_SCRATCH)/sizeof(ixPSX81_PIF0_SCRATCH[0]), 0, 0 },
+	{ "ixPSX81_PIF0_HW_DEBUG", REG_SMC, 0x1110002, &ixPSX81_PIF0_HW_DEBUG[0], sizeof(ixPSX81_PIF0_HW_DEBUG)/sizeof(ixPSX81_PIF0_HW_DEBUG[0]), 0, 0 },
+	{ "ixPSX81_PIF0_STRAP_0", REG_SMC, 0x1110003, &ixPSX81_PIF0_STRAP_0[0], sizeof(ixPSX81_PIF0_STRAP_0)/sizeof(ixPSX81_PIF0_STRAP_0[0]), 0, 0 },
+	{ "ixPSX81_PIF0_CTRL", REG_SMC, 0x1110004, &ixPSX81_PIF0_CTRL[0], sizeof(ixPSX81_PIF0_CTRL)/sizeof(ixPSX81_PIF0_CTRL[0]), 0, 0 },
+	{ "ixPSX81_PIF0_TX_CTRL", REG_SMC, 0x1110008, &ixPSX81_PIF0_TX_CTRL[0], sizeof(ixPSX81_PIF0_TX_CTRL)/sizeof(ixPSX81_PIF0_TX_CTRL[0]), 0, 0 },
+	{ "ixPSX81_PIF0_TX_CTRL2", REG_SMC, 0x1110009, &ixPSX81_PIF0_TX_CTRL2[0], sizeof(ixPSX81_PIF0_TX_CTRL2)/sizeof(ixPSX81_PIF0_TX_CTRL2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_RX_CTRL", REG_SMC, 0x111000a, &ixPSX81_PIF0_RX_CTRL[0], sizeof(ixPSX81_PIF0_RX_CTRL)/sizeof(ixPSX81_PIF0_RX_CTRL[0]), 0, 0 },
+	{ "ixPSX81_PIF0_RX_CTRL2", REG_SMC, 0x111000b, &ixPSX81_PIF0_RX_CTRL2[0], sizeof(ixPSX81_PIF0_RX_CTRL2)/sizeof(ixPSX81_PIF0_RX_CTRL2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_GLB_OVRD", REG_SMC, 0x111000c, &ixPSX81_PIF0_GLB_OVRD[0], sizeof(ixPSX81_PIF0_GLB_OVRD)/sizeof(ixPSX81_PIF0_GLB_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_GLB_OVRD2", REG_SMC, 0x111000d, &ixPSX81_PIF0_GLB_OVRD2[0], sizeof(ixPSX81_PIF0_GLB_OVRD2)/sizeof(ixPSX81_PIF0_GLB_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_BIF_CMD_STATUS", REG_SMC, 0x1110010, &ixPSX81_PIF0_BIF_CMD_STATUS[0], sizeof(ixPSX81_PIF0_BIF_CMD_STATUS)/sizeof(ixPSX81_PIF0_BIF_CMD_STATUS[0]), 0, 0 },
+	{ "ixPSX81_PIF0_CMD_BUS_CTRL", REG_SMC, 0x1110011, &ixPSX81_PIF0_CMD_BUS_CTRL[0], sizeof(ixPSX81_PIF0_CMD_BUS_CTRL)/sizeof(ixPSX81_PIF0_CMD_BUS_CTRL[0]), 0, 0 },
+	{ "ixPSX81_PIF0_CMD_BUS_GLB_OVRD", REG_SMC, 0x1110013, &ixPSX81_PIF0_CMD_BUS_GLB_OVRD[0], sizeof(ixPSX81_PIF0_CMD_BUS_GLB_OVRD)/sizeof(ixPSX81_PIF0_CMD_BUS_GLB_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE0_OVRD", REG_SMC, 0x1110014, &ixPSX81_PIF0_LANE0_OVRD[0], sizeof(ixPSX81_PIF0_LANE0_OVRD)/sizeof(ixPSX81_PIF0_LANE0_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE0_OVRD2", REG_SMC, 0x1110015, &ixPSX81_PIF0_LANE0_OVRD2[0], sizeof(ixPSX81_PIF0_LANE0_OVRD2)/sizeof(ixPSX81_PIF0_LANE0_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE1_OVRD", REG_SMC, 0x1110016, &ixPSX81_PIF0_LANE1_OVRD[0], sizeof(ixPSX81_PIF0_LANE1_OVRD)/sizeof(ixPSX81_PIF0_LANE1_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE1_OVRD2", REG_SMC, 0x1110017, &ixPSX81_PIF0_LANE1_OVRD2[0], sizeof(ixPSX81_PIF0_LANE1_OVRD2)/sizeof(ixPSX81_PIF0_LANE1_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE2_OVRD", REG_SMC, 0x1110018, &ixPSX81_PIF0_LANE2_OVRD[0], sizeof(ixPSX81_PIF0_LANE2_OVRD)/sizeof(ixPSX81_PIF0_LANE2_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE2_OVRD2", REG_SMC, 0x1110019, &ixPSX81_PIF0_LANE2_OVRD2[0], sizeof(ixPSX81_PIF0_LANE2_OVRD2)/sizeof(ixPSX81_PIF0_LANE2_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE3_OVRD", REG_SMC, 0x111001a, &ixPSX81_PIF0_LANE3_OVRD[0], sizeof(ixPSX81_PIF0_LANE3_OVRD)/sizeof(ixPSX81_PIF0_LANE3_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE3_OVRD2", REG_SMC, 0x111001b, &ixPSX81_PIF0_LANE3_OVRD2[0], sizeof(ixPSX81_PIF0_LANE3_OVRD2)/sizeof(ixPSX81_PIF0_LANE3_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE4_OVRD", REG_SMC, 0x111001c, &ixPSX81_PIF0_LANE4_OVRD[0], sizeof(ixPSX81_PIF0_LANE4_OVRD)/sizeof(ixPSX81_PIF0_LANE4_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE4_OVRD2", REG_SMC, 0x111001d, &ixPSX81_PIF0_LANE4_OVRD2[0], sizeof(ixPSX81_PIF0_LANE4_OVRD2)/sizeof(ixPSX81_PIF0_LANE4_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE5_OVRD", REG_SMC, 0x111001e, &ixPSX81_PIF0_LANE5_OVRD[0], sizeof(ixPSX81_PIF0_LANE5_OVRD)/sizeof(ixPSX81_PIF0_LANE5_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE5_OVRD2", REG_SMC, 0x111001f, &ixPSX81_PIF0_LANE5_OVRD2[0], sizeof(ixPSX81_PIF0_LANE5_OVRD2)/sizeof(ixPSX81_PIF0_LANE5_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE6_OVRD", REG_SMC, 0x1110020, &ixPSX81_PIF0_LANE6_OVRD[0], sizeof(ixPSX81_PIF0_LANE6_OVRD)/sizeof(ixPSX81_PIF0_LANE6_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE6_OVRD2", REG_SMC, 0x1110021, &ixPSX81_PIF0_LANE6_OVRD2[0], sizeof(ixPSX81_PIF0_LANE6_OVRD2)/sizeof(ixPSX81_PIF0_LANE6_OVRD2[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE7_OVRD", REG_SMC, 0x1110022, &ixPSX81_PIF0_LANE7_OVRD[0], sizeof(ixPSX81_PIF0_LANE7_OVRD)/sizeof(ixPSX81_PIF0_LANE7_OVRD[0]), 0, 0 },
+	{ "ixPSX81_PIF0_LANE7_OVRD2", REG_SMC, 0x1110023, &ixPSX81_PIF0_LANE7_OVRD2[0], sizeof(ixPSX81_PIF0_LANE7_OVRD2)/sizeof(ixPSX81_PIF0_LANE7_OVRD2[0]), 0, 0 },
+	{ "mmVENDOR_CAP_LIST", REG_MMIO, 0x12, &mmVENDOR_CAP_LIST[0], sizeof(mmVENDOR_CAP_LIST)/sizeof(mmVENDOR_CAP_LIST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0", REG_SMC, 0x1200000, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0", REG_SMC, 0x1200001, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_LANE0", REG_SMC, 0x1200002, &ixPSX80_PHY0_RX_RX_CTL_LANE0[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE0)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_LANE0", REG_SMC, 0x1200003, &ixPSX80_PHY0_RX_DLL_CTL_LANE0[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE0)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_LANE0", REG_SMC, 0x1200004, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE0[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE0)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0", REG_SMC, 0x1200005, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_LANE0", REG_SMC, 0x120000a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE0[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE0)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_LANE0", REG_SMC, 0x120000b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE0[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE0)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0", REG_SMC, 0x120000c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0", REG_SMC, 0x120000d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_LANE0", REG_SMC, 0x120000e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE0[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE0)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1", REG_SMC, 0x1200100, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1", REG_SMC, 0x1200101, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_LANE1", REG_SMC, 0x1200102, &ixPSX80_PHY0_RX_RX_CTL_LANE1[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE1)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_LANE1", REG_SMC, 0x1200103, &ixPSX80_PHY0_RX_DLL_CTL_LANE1[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE1)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_LANE1", REG_SMC, 0x1200104, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE1[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE1)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1", REG_SMC, 0x1200105, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_LANE1", REG_SMC, 0x120010a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE1[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE1)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_LANE1", REG_SMC, 0x120010b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE1[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE1)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1", REG_SMC, 0x120010c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1", REG_SMC, 0x120010d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_LANE1", REG_SMC, 0x120010e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE1[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE1)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2", REG_SMC, 0x1200200, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2", REG_SMC, 0x1200201, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_LANE2", REG_SMC, 0x1200202, &ixPSX80_PHY0_RX_RX_CTL_LANE2[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE2)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_LANE2", REG_SMC, 0x1200203, &ixPSX80_PHY0_RX_DLL_CTL_LANE2[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE2)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_LANE2", REG_SMC, 0x1200204, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE2[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE2)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2", REG_SMC, 0x1200205, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_LANE2", REG_SMC, 0x120020a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE2[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE2)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_LANE2", REG_SMC, 0x120020b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE2[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE2)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2", REG_SMC, 0x120020c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2", REG_SMC, 0x120020d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_LANE2", REG_SMC, 0x120020e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE2[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE2)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3", REG_SMC, 0x1200300, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3", REG_SMC, 0x1200301, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_LANE3", REG_SMC, 0x1200302, &ixPSX80_PHY0_RX_RX_CTL_LANE3[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE3)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_LANE3", REG_SMC, 0x1200303, &ixPSX80_PHY0_RX_DLL_CTL_LANE3[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE3)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_LANE3", REG_SMC, 0x1200304, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE3[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE3)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3", REG_SMC, 0x1200305, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_LANE3", REG_SMC, 0x120030a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE3[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE3)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_LANE3", REG_SMC, 0x120030b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE3[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE3)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3", REG_SMC, 0x120030c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3", REG_SMC, 0x120030d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_LANE3", REG_SMC, 0x120030e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE3[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE3)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4", REG_SMC, 0x1200400, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4", REG_SMC, 0x1200401, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_LANE4", REG_SMC, 0x1200402, &ixPSX80_PHY0_RX_RX_CTL_LANE4[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE4)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_LANE4", REG_SMC, 0x1200403, &ixPSX80_PHY0_RX_DLL_CTL_LANE4[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE4)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_LANE4", REG_SMC, 0x1200404, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE4[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE4)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4", REG_SMC, 0x1200405, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_LANE4", REG_SMC, 0x120040a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE4[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE4)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_LANE4", REG_SMC, 0x120040b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE4[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE4)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4", REG_SMC, 0x120040c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4", REG_SMC, 0x120040d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_LANE4", REG_SMC, 0x120040e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE4[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE4)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5", REG_SMC, 0x1200500, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5", REG_SMC, 0x1200501, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_LANE5", REG_SMC, 0x1200502, &ixPSX80_PHY0_RX_RX_CTL_LANE5[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE5)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_LANE5", REG_SMC, 0x1200503, &ixPSX80_PHY0_RX_DLL_CTL_LANE5[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE5)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_LANE5", REG_SMC, 0x1200504, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE5[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE5)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5", REG_SMC, 0x1200505, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_LANE5", REG_SMC, 0x120050a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE5[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE5)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_LANE5", REG_SMC, 0x120050b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE5[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE5)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5", REG_SMC, 0x120050c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5", REG_SMC, 0x120050d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_LANE5", REG_SMC, 0x120050e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE5[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE5)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6", REG_SMC, 0x1200600, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6", REG_SMC, 0x1200601, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_LANE6", REG_SMC, 0x1200602, &ixPSX80_PHY0_RX_RX_CTL_LANE6[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE6)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_LANE6", REG_SMC, 0x1200603, &ixPSX80_PHY0_RX_DLL_CTL_LANE6[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE6)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_LANE6", REG_SMC, 0x1200604, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE6[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE6)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6", REG_SMC, 0x1200605, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_LANE6", REG_SMC, 0x120060a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE6[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE6)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_LANE6", REG_SMC, 0x120060b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE6[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE6)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6", REG_SMC, 0x120060c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6", REG_SMC, 0x120060d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_LANE6", REG_SMC, 0x120060e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE6[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE6)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7", REG_SMC, 0x1200700, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7", REG_SMC, 0x1200701, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_LANE7", REG_SMC, 0x1200702, &ixPSX80_PHY0_RX_RX_CTL_LANE7[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE7)/sizeof(ixPSX80_PHY0_RX_RX_CTL_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_LANE7", REG_SMC, 0x1200703, &ixPSX80_PHY0_RX_DLL_CTL_LANE7[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE7)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_LANE7", REG_SMC, 0x1200704, &ixPSX80_PHY0_RX_RXTEST_REGS_LANE7[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE7)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7", REG_SMC, 0x1200705, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_LANE7", REG_SMC, 0x120070a, &ixPSX80_PHY0_RX_ADAPTCTL_LANE7[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE7)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_LANE7", REG_SMC, 0x120070b, &ixPSX80_PHY0_RX_FOMCALCCTL_LANE7[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE7)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7", REG_SMC, 0x120070c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7", REG_SMC, 0x120070d, &ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_LANE7", REG_SMC, 0x120070e, &ixPSX80_PHY0_RX_ADAPTDBG1_LANE7[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE7)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0", REG_SMC, 0x1202000, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_LANE0", REG_SMC, 0x1202001, &ixPSX80_PHY0_TX_DFX_LANE0[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE0)/sizeof(ixPSX80_PHY0_TX_DFX_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_LANE0", REG_SMC, 0x1202002, &ixPSX80_PHY0_TX_DEEMPH_LANE0[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE0)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0", REG_SMC, 0x1202003, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0", REG_SMC, 0x1202004, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_LANE0", REG_SMC, 0x1202006, &ixPSX80_PHY0_TX_TXCNTRL_LANE0[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE0)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_SMC, 0x1202007, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1", REG_SMC, 0x1202100, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_LANE1", REG_SMC, 0x1202101, &ixPSX80_PHY0_TX_DFX_LANE1[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE1)/sizeof(ixPSX80_PHY0_TX_DFX_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_LANE1", REG_SMC, 0x1202102, &ixPSX80_PHY0_TX_DEEMPH_LANE1[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE1)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1", REG_SMC, 0x1202103, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1", REG_SMC, 0x1202104, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_LANE1", REG_SMC, 0x1202106, &ixPSX80_PHY0_TX_TXCNTRL_LANE1[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE1)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_SMC, 0x1202107, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2", REG_SMC, 0x1202200, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_LANE2", REG_SMC, 0x1202201, &ixPSX80_PHY0_TX_DFX_LANE2[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE2)/sizeof(ixPSX80_PHY0_TX_DFX_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_LANE2", REG_SMC, 0x1202202, &ixPSX80_PHY0_TX_DEEMPH_LANE2[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE2)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2", REG_SMC, 0x1202203, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2", REG_SMC, 0x1202204, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_LANE2", REG_SMC, 0x1202206, &ixPSX80_PHY0_TX_TXCNTRL_LANE2[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE2)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_SMC, 0x1202207, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3", REG_SMC, 0x1202300, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_LANE3", REG_SMC, 0x1202301, &ixPSX80_PHY0_TX_DFX_LANE3[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE3)/sizeof(ixPSX80_PHY0_TX_DFX_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_LANE3", REG_SMC, 0x1202302, &ixPSX80_PHY0_TX_DEEMPH_LANE3[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE3)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3", REG_SMC, 0x1202303, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3", REG_SMC, 0x1202304, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_LANE3", REG_SMC, 0x1202306, &ixPSX80_PHY0_TX_TXCNTRL_LANE3[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE3)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_SMC, 0x1202307, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4", REG_SMC, 0x1202400, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_LANE4", REG_SMC, 0x1202401, &ixPSX80_PHY0_TX_DFX_LANE4[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE4)/sizeof(ixPSX80_PHY0_TX_DFX_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_LANE4", REG_SMC, 0x1202402, &ixPSX80_PHY0_TX_DEEMPH_LANE4[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE4)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4", REG_SMC, 0x1202403, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4", REG_SMC, 0x1202404, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_LANE4", REG_SMC, 0x1202406, &ixPSX80_PHY0_TX_TXCNTRL_LANE4[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE4)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4", REG_SMC, 0x1202407, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5", REG_SMC, 0x1202500, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_LANE5", REG_SMC, 0x1202501, &ixPSX80_PHY0_TX_DFX_LANE5[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE5)/sizeof(ixPSX80_PHY0_TX_DFX_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_LANE5", REG_SMC, 0x1202502, &ixPSX80_PHY0_TX_DEEMPH_LANE5[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE5)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5", REG_SMC, 0x1202503, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5", REG_SMC, 0x1202504, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_LANE5", REG_SMC, 0x1202506, &ixPSX80_PHY0_TX_TXCNTRL_LANE5[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE5)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5", REG_SMC, 0x1202507, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6", REG_SMC, 0x1202600, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_LANE6", REG_SMC, 0x1202601, &ixPSX80_PHY0_TX_DFX_LANE6[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE6)/sizeof(ixPSX80_PHY0_TX_DFX_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_LANE6", REG_SMC, 0x1202602, &ixPSX80_PHY0_TX_DEEMPH_LANE6[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE6)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6", REG_SMC, 0x1202603, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6", REG_SMC, 0x1202604, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_LANE6", REG_SMC, 0x1202606, &ixPSX80_PHY0_TX_TXCNTRL_LANE6[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE6)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6", REG_SMC, 0x1202607, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7", REG_SMC, 0x1202700, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_LANE7", REG_SMC, 0x1202701, &ixPSX80_PHY0_TX_DFX_LANE7[0], sizeof(ixPSX80_PHY0_TX_DFX_LANE7)/sizeof(ixPSX80_PHY0_TX_DFX_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_LANE7", REG_SMC, 0x1202702, &ixPSX80_PHY0_TX_DEEMPH_LANE7[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE7)/sizeof(ixPSX80_PHY0_TX_DEEMPH_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7", REG_SMC, 0x1202703, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7", REG_SMC, 0x1202704, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_LANE7", REG_SMC, 0x1202706, &ixPSX80_PHY0_TX_TXCNTRL_LANE7[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE7)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7", REG_SMC, 0x1202707, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt", REG_SMC, 0x1204001, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllControlExt[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl", REG_SMC, 0x1204002, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllControl[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1", REG_SMC, 0x1204003, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2", REG_SMC, 0x1204004, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode", REG_SMC, 0x1204005, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllFreqMode[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl", REG_SMC, 0x1204007, &ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl", REG_SMC, 0x1204008, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3", REG_SMC, 0x1204009, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4", REG_SMC, 0x120400b, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5", REG_SMC, 0x120400c, &ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PciPllTestDebug5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn", REG_SMC, 0x1204080, &ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn[0], sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn)/sizeof(ixPSX80_PHY0_LCPLL_LCPLL_PowerDownEn[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt", REG_SMC, 0x1204101, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllControlExt[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl", REG_SMC, 0x1204102, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllControl[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1", REG_SMC, 0x1204103, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2", REG_SMC, 0x1204104, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode", REG_SMC, 0x1204105, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllFreqMode[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl", REG_SMC, 0x1204108, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3", REG_SMC, 0x1204109, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess", REG_SMC, 0x120410a, &ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciFuseProcess[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4", REG_SMC, 0x120410b, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug4[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5", REG_SMC, 0x120410c, &ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PciPllTestDebug5[0]), 0, 0 },
+	{ "ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn", REG_SMC, 0x1204180, &ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn[0], sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn)/sizeof(ixPSX80_PHY0_HTPLL_ROPLL_PowerDownEn[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_FUSE1", REG_SMC, 0x1206200, &ixPSX80_PHY0_COM_COMMON_FUSE1[0], sizeof(ixPSX80_PHY0_COM_COMMON_FUSE1)/sizeof(ixPSX80_PHY0_COM_COMMON_FUSE1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_FUSE2", REG_SMC, 0x1206201, &ixPSX80_PHY0_COM_COMMON_FUSE2[0], sizeof(ixPSX80_PHY0_COM_COMMON_FUSE2)/sizeof(ixPSX80_PHY0_COM_COMMON_FUSE2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_FUSE3", REG_SMC, 0x1206202, &ixPSX80_PHY0_COM_COMMON_FUSE3[0], sizeof(ixPSX80_PHY0_COM_COMMON_FUSE3)/sizeof(ixPSX80_PHY0_COM_COMMON_FUSE3[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_ELECIDLE", REG_SMC, 0x1206204, &ixPSX80_PHY0_COM_COMMON_ELECIDLE[0], sizeof(ixPSX80_PHY0_COM_COMMON_ELECIDLE)/sizeof(ixPSX80_PHY0_COM_COMMON_ELECIDLE[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_DFX", REG_SMC, 0x1206205, &ixPSX80_PHY0_COM_COMMON_DFX[0], sizeof(ixPSX80_PHY0_COM_COMMON_DFX)/sizeof(ixPSX80_PHY0_COM_COMMON_DFX[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM", REG_SMC, 0x1206206, &ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM[0], sizeof(ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM)/sizeof(ixPSX80_PHY0_COM_COMMON_MAR_DEEMPH_NOM[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_SELDEEMPH35", REG_SMC, 0x1206207, &ixPSX80_PHY0_COM_COMMON_SELDEEMPH35[0], sizeof(ixPSX80_PHY0_COM_COMMON_SELDEEMPH35)/sizeof(ixPSX80_PHY0_COM_COMMON_SELDEEMPH35[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_SELDEEMPH60", REG_SMC, 0x1206208, &ixPSX80_PHY0_COM_COMMON_SELDEEMPH60[0], sizeof(ixPSX80_PHY0_COM_COMMON_SELDEEMPH60)/sizeof(ixPSX80_PHY0_COM_COMMON_SELDEEMPH60[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT", REG_SMC, 0x1206209, &ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT[0], sizeof(ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT)/sizeof(ixPSX80_PHY0_COM_COMMON_LANE_PWRMGMT[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_ADAPTCTL1", REG_SMC, 0x120620a, &ixPSX80_PHY0_COM_COMMON_ADAPTCTL1[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPTCTL1)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPTCTL1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_ADAPTCTL2", REG_SMC, 0x120620b, &ixPSX80_PHY0_COM_COMMON_ADAPTCTL2[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPTCTL2)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPTCTL2[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL", REG_SMC, 0x120620c, &ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1", REG_SMC, 0x120620d, &ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL", REG_SMC, 0x120620e, &ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1", REG_SMC, 0x120620f, &ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1", REG_SMC, 0x1206210, &ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1[0], sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1)/sizeof(ixPSX80_PHY0_COM_COMMON_ADAPT_DBG1[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_LNCNTRL", REG_SMC, 0x1206211, &ixPSX80_PHY0_COM_COMMON_LNCNTRL[0], sizeof(ixPSX80_PHY0_COM_COMMON_LNCNTRL)/sizeof(ixPSX80_PHY0_COM_COMMON_LNCNTRL[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG", REG_SMC, 0x1206212, &ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG[0], sizeof(ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG)/sizeof(ixPSX80_PHY0_COM_COMMON_TXTESTDEBUG[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG", REG_SMC, 0x1206213, &ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG[0], sizeof(ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG)/sizeof(ixPSX80_PHY0_COM_COMMON_RXTESTDEBUG[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_CDR_PHCTL", REG_SMC, 0x1206214, &ixPSX80_PHY0_COM_COMMON_CDR_PHCTL[0], sizeof(ixPSX80_PHY0_COM_COMMON_CDR_PHCTL)/sizeof(ixPSX80_PHY0_COM_COMMON_CDR_PHCTL[0]), 0, 0 },
+	{ "ixPSX80_PHY0_COM_COMMON_CDR_FRCTL", REG_SMC, 0x1206215, &ixPSX80_PHY0_COM_COMMON_CDR_FRCTL[0], sizeof(ixPSX80_PHY0_COM_COMMON_CDR_FRCTL)/sizeof(ixPSX80_PHY0_COM_COMMON_CDR_FRCTL[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST", REG_SMC, 0x120fe00, &ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST", REG_SMC, 0x120fe01, &ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST)/sizeof(ixPSX80_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RX_CTL_BROADCAST", REG_SMC, 0x120fe02, &ixPSX80_PHY0_RX_RX_CTL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_RX_CTL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_RX_CTL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DLL_CTL_BROADCAST", REG_SMC, 0x120fe03, &ixPSX80_PHY0_RX_DLL_CTL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_DLL_CTL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_DLL_CTL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST", REG_SMC, 0x120fe04, &ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST)/sizeof(ixPSX80_PHY0_RX_RXTEST_REGS_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST", REG_SMC, 0x120fe05, &ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST)/sizeof(ixPSX80_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST", REG_SMC, 0x120fe0a, &ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_ADAPTCTL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST", REG_SMC, 0x120fe0b, &ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST)/sizeof(ixPSX80_PHY0_RX_FOMCALCCTL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST", REG_SMC, 0x120fe0c, &ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST)/sizeof(ixPSX80_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST", REG_SMC, 0x120fe0d, &ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST)/sizeof(ixPSX80_PHY0_RX_DBG_BYP_EN_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST", REG_SMC, 0x120fe0e, &ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST[0], sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST)/sizeof(ixPSX80_PHY0_RX_ADAPTDBG1_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST", REG_SMC, 0x120ff00, &ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DFX_BROADCAST", REG_SMC, 0x120ff01, &ixPSX80_PHY0_TX_DFX_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_DFX_BROADCAST)/sizeof(ixPSX80_PHY0_TX_DFX_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_DEEMPH_BROADCAST", REG_SMC, 0x120ff02, &ixPSX80_PHY0_TX_DEEMPH_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_DEEMPH_BROADCAST)/sizeof(ixPSX80_PHY0_TX_DEEMPH_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST", REG_SMC, 0x120ff03, &ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST)/sizeof(ixPSX80_PHY0_TX_TSTMARGDEEMPH_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST", REG_SMC, 0x120ff04, &ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST)/sizeof(ixPSX80_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_TXCNTRL_BROADCAST", REG_SMC, 0x120ff06, &ixPSX80_PHY0_TX_TXCNTRL_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_TXCNTRL_BROADCAST)/sizeof(ixPSX80_PHY0_TX_TXCNTRL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST", REG_SMC, 0x120ff07, &ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[0], sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST)/sizeof(ixPSX80_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0", REG_SMC, 0x1210000, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0", REG_SMC, 0x1210001, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_LANE0", REG_SMC, 0x1210002, &ixPSX81_PHY0_RX_RX_CTL_LANE0[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE0)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_LANE0", REG_SMC, 0x1210003, &ixPSX81_PHY0_RX_DLL_CTL_LANE0[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE0)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_LANE0", REG_SMC, 0x1210004, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE0[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE0)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0", REG_SMC, 0x1210005, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_LANE0", REG_SMC, 0x121000a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE0[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE0)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_LANE0", REG_SMC, 0x121000b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE0[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE0)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0", REG_SMC, 0x121000c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0", REG_SMC, 0x121000d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_LANE0", REG_SMC, 0x121000e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE0[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE0)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1", REG_SMC, 0x1210100, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1", REG_SMC, 0x1210101, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_LANE1", REG_SMC, 0x1210102, &ixPSX81_PHY0_RX_RX_CTL_LANE1[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE1)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_LANE1", REG_SMC, 0x1210103, &ixPSX81_PHY0_RX_DLL_CTL_LANE1[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE1)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_LANE1", REG_SMC, 0x1210104, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE1[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE1)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1", REG_SMC, 0x1210105, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_LANE1", REG_SMC, 0x121010a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE1[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE1)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_LANE1", REG_SMC, 0x121010b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE1[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE1)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1", REG_SMC, 0x121010c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1", REG_SMC, 0x121010d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_LANE1", REG_SMC, 0x121010e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE1[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE1)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2", REG_SMC, 0x1210200, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2", REG_SMC, 0x1210201, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_LANE2", REG_SMC, 0x1210202, &ixPSX81_PHY0_RX_RX_CTL_LANE2[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE2)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_LANE2", REG_SMC, 0x1210203, &ixPSX81_PHY0_RX_DLL_CTL_LANE2[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE2)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_LANE2", REG_SMC, 0x1210204, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE2[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE2)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2", REG_SMC, 0x1210205, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_LANE2", REG_SMC, 0x121020a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE2[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE2)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_LANE2", REG_SMC, 0x121020b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE2[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE2)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2", REG_SMC, 0x121020c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2", REG_SMC, 0x121020d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_LANE2", REG_SMC, 0x121020e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE2[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE2)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3", REG_SMC, 0x1210300, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3", REG_SMC, 0x1210301, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_LANE3", REG_SMC, 0x1210302, &ixPSX81_PHY0_RX_RX_CTL_LANE3[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE3)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_LANE3", REG_SMC, 0x1210303, &ixPSX81_PHY0_RX_DLL_CTL_LANE3[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE3)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_LANE3", REG_SMC, 0x1210304, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE3[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE3)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3", REG_SMC, 0x1210305, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_LANE3", REG_SMC, 0x121030a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE3[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE3)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_LANE3", REG_SMC, 0x121030b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE3[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE3)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3", REG_SMC, 0x121030c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3", REG_SMC, 0x121030d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_LANE3", REG_SMC, 0x121030e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE3[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE3)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4", REG_SMC, 0x1210400, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4", REG_SMC, 0x1210401, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_LANE4", REG_SMC, 0x1210402, &ixPSX81_PHY0_RX_RX_CTL_LANE4[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE4)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_LANE4", REG_SMC, 0x1210403, &ixPSX81_PHY0_RX_DLL_CTL_LANE4[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE4)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_LANE4", REG_SMC, 0x1210404, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE4[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE4)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4", REG_SMC, 0x1210405, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_LANE4", REG_SMC, 0x121040a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE4[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE4)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_LANE4", REG_SMC, 0x121040b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE4[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE4)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4", REG_SMC, 0x121040c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4", REG_SMC, 0x121040d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_LANE4", REG_SMC, 0x121040e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE4[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE4)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5", REG_SMC, 0x1210500, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5", REG_SMC, 0x1210501, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_LANE5", REG_SMC, 0x1210502, &ixPSX81_PHY0_RX_RX_CTL_LANE5[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE5)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_LANE5", REG_SMC, 0x1210503, &ixPSX81_PHY0_RX_DLL_CTL_LANE5[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE5)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_LANE5", REG_SMC, 0x1210504, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE5[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE5)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5", REG_SMC, 0x1210505, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_LANE5", REG_SMC, 0x121050a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE5[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE5)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_LANE5", REG_SMC, 0x121050b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE5[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE5)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5", REG_SMC, 0x121050c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5", REG_SMC, 0x121050d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_LANE5", REG_SMC, 0x121050e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE5[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE5)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6", REG_SMC, 0x1210600, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6", REG_SMC, 0x1210601, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_LANE6", REG_SMC, 0x1210602, &ixPSX81_PHY0_RX_RX_CTL_LANE6[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE6)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_LANE6", REG_SMC, 0x1210603, &ixPSX81_PHY0_RX_DLL_CTL_LANE6[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE6)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_LANE6", REG_SMC, 0x1210604, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE6[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE6)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6", REG_SMC, 0x1210605, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_LANE6", REG_SMC, 0x121060a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE6[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE6)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_LANE6", REG_SMC, 0x121060b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE6[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE6)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6", REG_SMC, 0x121060c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6", REG_SMC, 0x121060d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_LANE6", REG_SMC, 0x121060e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE6[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE6)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7", REG_SMC, 0x1210700, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7", REG_SMC, 0x1210701, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_LANE7", REG_SMC, 0x1210702, &ixPSX81_PHY0_RX_RX_CTL_LANE7[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE7)/sizeof(ixPSX81_PHY0_RX_RX_CTL_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_LANE7", REG_SMC, 0x1210703, &ixPSX81_PHY0_RX_DLL_CTL_LANE7[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE7)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_LANE7", REG_SMC, 0x1210704, &ixPSX81_PHY0_RX_RXTEST_REGS_LANE7[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE7)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7", REG_SMC, 0x1210705, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_LANE7", REG_SMC, 0x121070a, &ixPSX81_PHY0_RX_ADAPTCTL_LANE7[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE7)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_LANE7", REG_SMC, 0x121070b, &ixPSX81_PHY0_RX_FOMCALCCTL_LANE7[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE7)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7", REG_SMC, 0x121070c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7", REG_SMC, 0x121070d, &ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_LANE7", REG_SMC, 0x121070e, &ixPSX81_PHY0_RX_ADAPTDBG1_LANE7[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE7)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0", REG_SMC, 0x1212000, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_LANE0", REG_SMC, 0x1212001, &ixPSX81_PHY0_TX_DFX_LANE0[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE0)/sizeof(ixPSX81_PHY0_TX_DFX_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_LANE0", REG_SMC, 0x1212002, &ixPSX81_PHY0_TX_DEEMPH_LANE0[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE0)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0", REG_SMC, 0x1212003, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0", REG_SMC, 0x1212004, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_LANE0", REG_SMC, 0x1212006, &ixPSX81_PHY0_TX_TXCNTRL_LANE0[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE0)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_SMC, 0x1212007, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1", REG_SMC, 0x1212100, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_LANE1", REG_SMC, 0x1212101, &ixPSX81_PHY0_TX_DFX_LANE1[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE1)/sizeof(ixPSX81_PHY0_TX_DFX_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_LANE1", REG_SMC, 0x1212102, &ixPSX81_PHY0_TX_DEEMPH_LANE1[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE1)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1", REG_SMC, 0x1212103, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1", REG_SMC, 0x1212104, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_LANE1", REG_SMC, 0x1212106, &ixPSX81_PHY0_TX_TXCNTRL_LANE1[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE1)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_SMC, 0x1212107, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2", REG_SMC, 0x1212200, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_LANE2", REG_SMC, 0x1212201, &ixPSX81_PHY0_TX_DFX_LANE2[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE2)/sizeof(ixPSX81_PHY0_TX_DFX_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_LANE2", REG_SMC, 0x1212202, &ixPSX81_PHY0_TX_DEEMPH_LANE2[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE2)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2", REG_SMC, 0x1212203, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2", REG_SMC, 0x1212204, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_LANE2", REG_SMC, 0x1212206, &ixPSX81_PHY0_TX_TXCNTRL_LANE2[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE2)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_SMC, 0x1212207, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3", REG_SMC, 0x1212300, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_LANE3", REG_SMC, 0x1212301, &ixPSX81_PHY0_TX_DFX_LANE3[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE3)/sizeof(ixPSX81_PHY0_TX_DFX_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_LANE3", REG_SMC, 0x1212302, &ixPSX81_PHY0_TX_DEEMPH_LANE3[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE3)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3", REG_SMC, 0x1212303, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3", REG_SMC, 0x1212304, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_LANE3", REG_SMC, 0x1212306, &ixPSX81_PHY0_TX_TXCNTRL_LANE3[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE3)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_SMC, 0x1212307, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4", REG_SMC, 0x1212400, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_LANE4", REG_SMC, 0x1212401, &ixPSX81_PHY0_TX_DFX_LANE4[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE4)/sizeof(ixPSX81_PHY0_TX_DFX_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_LANE4", REG_SMC, 0x1212402, &ixPSX81_PHY0_TX_DEEMPH_LANE4[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE4)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4", REG_SMC, 0x1212403, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4", REG_SMC, 0x1212404, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_LANE4", REG_SMC, 0x1212406, &ixPSX81_PHY0_TX_TXCNTRL_LANE4[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE4)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4", REG_SMC, 0x1212407, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5", REG_SMC, 0x1212500, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_LANE5", REG_SMC, 0x1212501, &ixPSX81_PHY0_TX_DFX_LANE5[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE5)/sizeof(ixPSX81_PHY0_TX_DFX_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_LANE5", REG_SMC, 0x1212502, &ixPSX81_PHY0_TX_DEEMPH_LANE5[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE5)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5", REG_SMC, 0x1212503, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5", REG_SMC, 0x1212504, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_LANE5", REG_SMC, 0x1212506, &ixPSX81_PHY0_TX_TXCNTRL_LANE5[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE5)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5", REG_SMC, 0x1212507, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6", REG_SMC, 0x1212600, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_LANE6", REG_SMC, 0x1212601, &ixPSX81_PHY0_TX_DFX_LANE6[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE6)/sizeof(ixPSX81_PHY0_TX_DFX_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_LANE6", REG_SMC, 0x1212602, &ixPSX81_PHY0_TX_DEEMPH_LANE6[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE6)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6", REG_SMC, 0x1212603, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6", REG_SMC, 0x1212604, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_LANE6", REG_SMC, 0x1212606, &ixPSX81_PHY0_TX_TXCNTRL_LANE6[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE6)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6", REG_SMC, 0x1212607, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE6[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7", REG_SMC, 0x1212700, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_LANE7", REG_SMC, 0x1212701, &ixPSX81_PHY0_TX_DFX_LANE7[0], sizeof(ixPSX81_PHY0_TX_DFX_LANE7)/sizeof(ixPSX81_PHY0_TX_DFX_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_LANE7", REG_SMC, 0x1212702, &ixPSX81_PHY0_TX_DEEMPH_LANE7[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE7)/sizeof(ixPSX81_PHY0_TX_DEEMPH_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7", REG_SMC, 0x1212703, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7", REG_SMC, 0x1212704, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_LANE7", REG_SMC, 0x1212706, &ixPSX81_PHY0_TX_TXCNTRL_LANE7[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE7)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7", REG_SMC, 0x1212707, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_LANE7[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt", REG_SMC, 0x1214001, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllControlExt[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl", REG_SMC, 0x1214002, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllControl[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1", REG_SMC, 0x1214003, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2", REG_SMC, 0x1214004, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode", REG_SMC, 0x1214005, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllFreqMode[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl", REG_SMC, 0x1214007, &ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciLcVcoCtrl[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl", REG_SMC, 0x1214008, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllUpdateCtrl[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3", REG_SMC, 0x1214009, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4", REG_SMC, 0x121400b, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5", REG_SMC, 0x121400c, &ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PciPllTestDebug5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn", REG_SMC, 0x1214080, &ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn[0], sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn)/sizeof(ixPSX81_PHY0_LCPLL_LCPLL_PowerDownEn[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt", REG_SMC, 0x1214101, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllControlExt[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl", REG_SMC, 0x1214102, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllControl[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1", REG_SMC, 0x1214103, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2", REG_SMC, 0x1214104, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode", REG_SMC, 0x1214105, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllFreqMode[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl", REG_SMC, 0x1214108, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllUpdateCtrl[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3", REG_SMC, 0x1214109, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess", REG_SMC, 0x121410a, &ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciFuseProcess[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4", REG_SMC, 0x121410b, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug4[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5", REG_SMC, 0x121410c, &ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PciPllTestDebug5[0]), 0, 0 },
+	{ "ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn", REG_SMC, 0x1214180, &ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn[0], sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn)/sizeof(ixPSX81_PHY0_HTPLL_ROPLL_PowerDownEn[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_FUSE1", REG_SMC, 0x1216200, &ixPSX81_PHY0_COM_COMMON_FUSE1[0], sizeof(ixPSX81_PHY0_COM_COMMON_FUSE1)/sizeof(ixPSX81_PHY0_COM_COMMON_FUSE1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_FUSE2", REG_SMC, 0x1216201, &ixPSX81_PHY0_COM_COMMON_FUSE2[0], sizeof(ixPSX81_PHY0_COM_COMMON_FUSE2)/sizeof(ixPSX81_PHY0_COM_COMMON_FUSE2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_FUSE3", REG_SMC, 0x1216202, &ixPSX81_PHY0_COM_COMMON_FUSE3[0], sizeof(ixPSX81_PHY0_COM_COMMON_FUSE3)/sizeof(ixPSX81_PHY0_COM_COMMON_FUSE3[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_ELECIDLE", REG_SMC, 0x1216204, &ixPSX81_PHY0_COM_COMMON_ELECIDLE[0], sizeof(ixPSX81_PHY0_COM_COMMON_ELECIDLE)/sizeof(ixPSX81_PHY0_COM_COMMON_ELECIDLE[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_DFX", REG_SMC, 0x1216205, &ixPSX81_PHY0_COM_COMMON_DFX[0], sizeof(ixPSX81_PHY0_COM_COMMON_DFX)/sizeof(ixPSX81_PHY0_COM_COMMON_DFX[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM", REG_SMC, 0x1216206, &ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM[0], sizeof(ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM)/sizeof(ixPSX81_PHY0_COM_COMMON_MAR_DEEMPH_NOM[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_SELDEEMPH35", REG_SMC, 0x1216207, &ixPSX81_PHY0_COM_COMMON_SELDEEMPH35[0], sizeof(ixPSX81_PHY0_COM_COMMON_SELDEEMPH35)/sizeof(ixPSX81_PHY0_COM_COMMON_SELDEEMPH35[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_SELDEEMPH60", REG_SMC, 0x1216208, &ixPSX81_PHY0_COM_COMMON_SELDEEMPH60[0], sizeof(ixPSX81_PHY0_COM_COMMON_SELDEEMPH60)/sizeof(ixPSX81_PHY0_COM_COMMON_SELDEEMPH60[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT", REG_SMC, 0x1216209, &ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT[0], sizeof(ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT)/sizeof(ixPSX81_PHY0_COM_COMMON_LANE_PWRMGMT[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_ADAPTCTL1", REG_SMC, 0x121620a, &ixPSX81_PHY0_COM_COMMON_ADAPTCTL1[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPTCTL1)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPTCTL1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_ADAPTCTL2", REG_SMC, 0x121620b, &ixPSX81_PHY0_COM_COMMON_ADAPTCTL2[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPTCTL2)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPTCTL2[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL", REG_SMC, 0x121620c, &ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1", REG_SMC, 0x121620d, &ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_CFG_BYP_VAL1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL", REG_SMC, 0x121620e, &ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1", REG_SMC, 0x121620f, &ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG_BYP_VAL1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1", REG_SMC, 0x1216210, &ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1[0], sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1)/sizeof(ixPSX81_PHY0_COM_COMMON_ADAPT_DBG1[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_LNCNTRL", REG_SMC, 0x1216211, &ixPSX81_PHY0_COM_COMMON_LNCNTRL[0], sizeof(ixPSX81_PHY0_COM_COMMON_LNCNTRL)/sizeof(ixPSX81_PHY0_COM_COMMON_LNCNTRL[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG", REG_SMC, 0x1216212, &ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG[0], sizeof(ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG)/sizeof(ixPSX81_PHY0_COM_COMMON_TXTESTDEBUG[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG", REG_SMC, 0x1216213, &ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG[0], sizeof(ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG)/sizeof(ixPSX81_PHY0_COM_COMMON_RXTESTDEBUG[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_CDR_PHCTL", REG_SMC, 0x1216214, &ixPSX81_PHY0_COM_COMMON_CDR_PHCTL[0], sizeof(ixPSX81_PHY0_COM_COMMON_CDR_PHCTL)/sizeof(ixPSX81_PHY0_COM_COMMON_CDR_PHCTL[0]), 0, 0 },
+	{ "ixPSX81_PHY0_COM_COMMON_CDR_FRCTL", REG_SMC, 0x1216215, &ixPSX81_PHY0_COM_COMMON_CDR_FRCTL[0], sizeof(ixPSX81_PHY0_COM_COMMON_CDR_FRCTL)/sizeof(ixPSX81_PHY0_COM_COMMON_CDR_FRCTL[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST", REG_SMC, 0x121fe00, &ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_RX_CONTROL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST", REG_SMC, 0x121fe01, &ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST)/sizeof(ixPSX81_PHY0_RX_CMD_BUS_GLOBAL_FOR_RX_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RX_CTL_BROADCAST", REG_SMC, 0x121fe02, &ixPSX81_PHY0_RX_RX_CTL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_RX_CTL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_RX_CTL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DLL_CTL_BROADCAST", REG_SMC, 0x121fe03, &ixPSX81_PHY0_RX_DLL_CTL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_DLL_CTL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_DLL_CTL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST", REG_SMC, 0x121fe04, &ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST)/sizeof(ixPSX81_PHY0_RX_RXTEST_REGS_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST", REG_SMC, 0x121fe05, &ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST)/sizeof(ixPSX81_PHY0_RX_ELECIDLE_DEBUG_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST", REG_SMC, 0x121fe0a, &ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_ADAPTCTL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST", REG_SMC, 0x121fe0b, &ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST)/sizeof(ixPSX81_PHY0_RX_FOMCALCCTL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST", REG_SMC, 0x121fe0c, &ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST)/sizeof(ixPSX81_PHY0_RX_ADAPT_CFG_BYP_EN_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST", REG_SMC, 0x121fe0d, &ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST)/sizeof(ixPSX81_PHY0_RX_DBG_BYP_EN_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST", REG_SMC, 0x121fe0e, &ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST[0], sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST)/sizeof(ixPSX81_PHY0_RX_ADAPTDBG1_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST", REG_SMC, 0x121ff00, &ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_TX_CONTROL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DFX_BROADCAST", REG_SMC, 0x121ff01, &ixPSX81_PHY0_TX_DFX_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_DFX_BROADCAST)/sizeof(ixPSX81_PHY0_TX_DFX_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_DEEMPH_BROADCAST", REG_SMC, 0x121ff02, &ixPSX81_PHY0_TX_DEEMPH_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_DEEMPH_BROADCAST)/sizeof(ixPSX81_PHY0_TX_DEEMPH_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST", REG_SMC, 0x121ff03, &ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST)/sizeof(ixPSX81_PHY0_TX_TSTMARGDEEMPH_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST", REG_SMC, 0x121ff04, &ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST)/sizeof(ixPSX81_PHY0_TX_MARGDEEMPHSTATUS_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_TXCNTRL_BROADCAST", REG_SMC, 0x121ff06, &ixPSX81_PHY0_TX_TXCNTRL_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_TXCNTRL_BROADCAST)/sizeof(ixPSX81_PHY0_TX_TXCNTRL_BROADCAST[0]), 0, 0 },
+	{ "ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST", REG_SMC, 0x121ff07, &ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[0], sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST)/sizeof(ixPSX81_PHY0_TX_CMD_BUS_GLOBAL_FOR_TX_BROADCAST[0]), 0, 0 },
+	{ "mmADAPTER_ID_W", REG_MMIO, 0x13, &mmADAPTER_ID_W[0], sizeof(mmADAPTER_ID_W)/sizeof(mmADAPTER_ID_W[0]), 0, 0 },
+	{ "ixBIF_BACO_MSIC_IND", REG_SMC, 0x1301480, &ixBIF_BACO_MSIC_IND[0], sizeof(ixBIF_BACO_MSIC_IND)/sizeof(ixBIF_BACO_MSIC_IND[0]), 0, 0 },
+	{ "ixBIF_PIF_TXCLK_SWITCH_TIMER_IND", REG_SMC, 0x1301481, &ixBIF_PIF_TXCLK_SWITCH_TIMER_IND[0], sizeof(ixBIF_PIF_TXCLK_SWITCH_TIMER_IND)/sizeof(ixBIF_PIF_TXCLK_SWITCH_TIMER_IND[0]), 0, 0 },
+	{ "ixBIF_RESET_EN_IND", REG_SMC, 0x1301482, &ixBIF_RESET_EN_IND[0], sizeof(ixBIF_RESET_EN_IND)/sizeof(ixBIF_RESET_EN_IND[0]), 0, 0 },
+	{ "ixBIF_CLK_PDWN_DELAY_TIMER_IND", REG_SMC, 0x1301483, &ixBIF_CLK_PDWN_DELAY_TIMER_IND[0], sizeof(ixBIF_CLK_PDWN_DELAY_TIMER_IND)/sizeof(ixBIF_CLK_PDWN_DELAY_TIMER_IND[0]), 0, 0 },
+	{ "ixNEW_REFCLKB_TIMER_1_IND", REG_SMC, 0x1301484, &ixNEW_REFCLKB_TIMER_1_IND[0], sizeof(ixNEW_REFCLKB_TIMER_1_IND)/sizeof(ixNEW_REFCLKB_TIMER_1_IND[0]), 0, 0 },
+	{ "ixNEW_REFCLKB_TIMER_IND", REG_SMC, 0x1301485, &ixNEW_REFCLKB_TIMER_IND[0], sizeof(ixNEW_REFCLKB_TIMER_IND)/sizeof(ixNEW_REFCLKB_TIMER_IND[0]), 0, 0 },
+	{ "ixBIF_RESET_CNTL_IND", REG_SMC, 0x1301486, &ixBIF_RESET_CNTL_IND[0], sizeof(ixBIF_RESET_CNTL_IND)/sizeof(ixBIF_RESET_CNTL_IND[0]), 0, 0 },
+	{ "ixLNCNT_CONTROL_IND", REG_SMC, 0x1301487, &ixLNCNT_CONTROL_IND[0], sizeof(ixLNCNT_CONTROL_IND)/sizeof(ixLNCNT_CONTROL_IND[0]), 0, 0 },
+	{ "ixBIF_LNCNT_RESET_IND", REG_SMC, 0x1301488, &ixBIF_LNCNT_RESET_IND[0], sizeof(ixBIF_LNCNT_RESET_IND)/sizeof(ixBIF_LNCNT_RESET_IND[0]), 0, 0 },
+	{ "ixBIF_CLOCKS_BITS_IND", REG_SMC, 0x1301489, &ixBIF_CLOCKS_BITS_IND[0], sizeof(ixBIF_CLOCKS_BITS_IND)/sizeof(ixBIF_CLOCKS_BITS_IND[0]), 0, 0 },
+	{ "ixBIF_MEM_PG_CNTL_IND", REG_SMC, 0x130148a, &ixBIF_MEM_PG_CNTL_IND[0], sizeof(ixBIF_MEM_PG_CNTL_IND)/sizeof(ixBIF_MEM_PG_CNTL_IND[0]), 0, 0 },
+	{ "ixBIF_RFE_CNTL_MISC_IND", REG_SMC, 0x130148c, &ixBIF_RFE_CNTL_MISC_IND[0], sizeof(ixBIF_RFE_CNTL_MISC_IND)/sizeof(ixBIF_RFE_CNTL_MISC_IND[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_WRAP_SCRATCH1", REG_SMC, 0x1308001, &ixPSX80_WRP_PCIE_WRAP_SCRATCH1[0], sizeof(ixPSX80_WRP_PCIE_WRAP_SCRATCH1)/sizeof(ixPSX80_WRP_PCIE_WRAP_SCRATCH1[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_WRAP_SCRATCH2", REG_SMC, 0x1308002, &ixPSX80_WRP_PCIE_WRAP_SCRATCH2[0], sizeof(ixPSX80_WRP_PCIE_WRAP_SCRATCH2)/sizeof(ixPSX80_WRP_PCIE_WRAP_SCRATCH2[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC", REG_SMC, 0x1308005, &ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC[0], sizeof(ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC)/sizeof(ixPSX80_WRP_PCIE_WRAP_REG_TARG_MISC[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_WRAP_DTM_MISC", REG_SMC, 0x1308006, &ixPSX80_WRP_PCIE_WRAP_DTM_MISC[0], sizeof(ixPSX80_WRP_PCIE_WRAP_DTM_MISC)/sizeof(ixPSX80_WRP_PCIE_WRAP_DTM_MISC[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN", REG_SMC, 0x1308007, &ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[0], sizeof(ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN)/sizeof(ixPSX80_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_WRAP_MISC", REG_SMC, 0x1308008, &ixPSX80_WRP_PCIE_WRAP_MISC[0], sizeof(ixPSX80_WRP_PCIE_WRAP_MISC)/sizeof(ixPSX80_WRP_PCIE_WRAP_MISC[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_WRAP_PIF_MISC", REG_SMC, 0x1308009, &ixPSX80_WRP_PCIE_WRAP_PIF_MISC[0], sizeof(ixPSX80_WRP_PCIE_WRAP_PIF_MISC)/sizeof(ixPSX80_WRP_PCIE_WRAP_PIF_MISC[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_RXDET_OVERRIDE", REG_SMC, 0x130800a, &ixPSX80_WRP_PCIE_RXDET_OVERRIDE[0], sizeof(ixPSX80_WRP_PCIE_RXDET_OVERRIDE)/sizeof(ixPSX80_WRP_PCIE_RXDET_OVERRIDE[0]), 0, 0 },
+	{ "ixPSX80_WRP_IMPCTL_CNTL_PIF0", REG_SMC, 0x1308070, &ixPSX80_WRP_IMPCTL_CNTL_PIF0[0], sizeof(ixPSX80_WRP_IMPCTL_CNTL_PIF0)/sizeof(ixPSX80_WRP_IMPCTL_CNTL_PIF0[0]), 0, 0 },
+	{ "ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL", REG_SMC, 0x1308090, &ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL[0], sizeof(ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL)/sizeof(ixPSX80_WRP_REG_ADAPT_pciecore0_CONTROL[0]), 0, 0 },
+	{ "ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL", REG_SMC, 0x1308096, &ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL[0], sizeof(ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL)/sizeof(ixPSX80_WRP_REG_ADAPT_pwregt_CONTROL[0]), 0, 0 },
+	{ "ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL", REG_SMC, 0x1308097, &ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL[0], sizeof(ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL)/sizeof(ixPSX80_WRP_REG_ADAPT_pwregr_CONTROL[0]), 0, 0 },
+	{ "ixPSX80_WRP_REG_ADAPT_pif0_CONTROL", REG_SMC, 0x1308098, &ixPSX80_WRP_REG_ADAPT_pif0_CONTROL[0], sizeof(ixPSX80_WRP_REG_ADAPT_pif0_CONTROL)/sizeof(ixPSX80_WRP_REG_ADAPT_pif0_CONTROL[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIOSTIMER_CMD", REG_SMC, 0x13080f0, &ixPSX80_WRP_BIOSTIMER_CMD[0], sizeof(ixPSX80_WRP_BIOSTIMER_CMD)/sizeof(ixPSX80_WRP_BIOSTIMER_CMD[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIOSTIMER_CNTL", REG_SMC, 0x13080f1, &ixPSX80_WRP_BIOSTIMER_CNTL[0], sizeof(ixPSX80_WRP_BIOSTIMER_CNTL)/sizeof(ixPSX80_WRP_BIOSTIMER_CNTL[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIOSTIMER_DEBUG", REG_SMC, 0x13080f2, &ixPSX80_WRP_BIOSTIMER_DEBUG[0], sizeof(ixPSX80_WRP_BIOSTIMER_DEBUG)/sizeof(ixPSX80_WRP_BIOSTIMER_DEBUG[0]), 0, 0 },
+	{ "ixPSX80_WRP_DELAYLINE_COMMAND", REG_SMC, 0x130ffd0, &ixPSX80_WRP_DELAYLINE_COMMAND[0], sizeof(ixPSX80_WRP_DELAYLINE_COMMAND)/sizeof(ixPSX80_WRP_DELAYLINE_COMMAND[0]), 0, 0 },
+	{ "ixPSX80_WRP_DELAYLINE_STATUS", REG_SMC, 0x130ffd1, &ixPSX80_WRP_DELAYLINE_STATUS[0], sizeof(ixPSX80_WRP_DELAYLINE_STATUS)/sizeof(ixPSX80_WRP_DELAYLINE_STATUS[0]), 0, 0 },
+	{ "ixPSX80_WRP_DTM_RX_BP_CNTL", REG_SMC, 0x130ffe0, &ixPSX80_WRP_DTM_RX_BP_CNTL[0], sizeof(ixPSX80_WRP_DTM_RX_BP_CNTL)/sizeof(ixPSX80_WRP_DTM_RX_BP_CNTL[0]), 0, 0 },
+	{ "ixPSX80_WRP_DTM_CNTL", REG_SMC, 0x130ffe1, &ixPSX80_WRP_DTM_CNTL[0], sizeof(ixPSX80_WRP_DTM_CNTL)/sizeof(ixPSX80_WRP_DTM_CNTL[0]), 0, 0 },
+	{ "ixPSX80_WRP_DTM_CNTL_LEGACY", REG_SMC, 0x130ffe2, &ixPSX80_WRP_DTM_CNTL_LEGACY[0], sizeof(ixPSX80_WRP_DTM_CNTL_LEGACY)/sizeof(ixPSX80_WRP_DTM_CNTL_LEGACY[0]), 0, 0 },
+	{ "ixPSX80_WRP_DTM_STI_LCLK_CTRL", REG_SMC, 0x130ffe3, &ixPSX80_WRP_DTM_STI_LCLK_CTRL[0], sizeof(ixPSX80_WRP_DTM_STI_LCLK_CTRL)/sizeof(ixPSX80_WRP_DTM_STI_LCLK_CTRL[0]), 0, 0 },
+	{ "ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x", REG_SMC, 0x130ffe4, &ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[0], sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x)/sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[0]), 0, 0 },
+	{ "ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt", REG_SMC, 0x130ffe5, &ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[0], sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt)/sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[0]), 0, 0 },
+	{ "ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x", REG_SMC, 0x130ffe6, &ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[0], sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x)/sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[0]), 0, 0 },
+	{ "ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt", REG_SMC, 0x130ffe7, &ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[0], sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt)/sizeof(ixPSX80_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_WRAP_SCRATCH1", REG_SMC, 0x1318001, &ixPSX81_WRP_PCIE_WRAP_SCRATCH1[0], sizeof(ixPSX81_WRP_PCIE_WRAP_SCRATCH1)/sizeof(ixPSX81_WRP_PCIE_WRAP_SCRATCH1[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_WRAP_SCRATCH2", REG_SMC, 0x1318002, &ixPSX81_WRP_PCIE_WRAP_SCRATCH2[0], sizeof(ixPSX81_WRP_PCIE_WRAP_SCRATCH2)/sizeof(ixPSX81_WRP_PCIE_WRAP_SCRATCH2[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC", REG_SMC, 0x1318005, &ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC[0], sizeof(ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC)/sizeof(ixPSX81_WRP_PCIE_WRAP_REG_TARG_MISC[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_WRAP_DTM_MISC", REG_SMC, 0x1318006, &ixPSX81_WRP_PCIE_WRAP_DTM_MISC[0], sizeof(ixPSX81_WRP_PCIE_WRAP_DTM_MISC)/sizeof(ixPSX81_WRP_PCIE_WRAP_DTM_MISC[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN", REG_SMC, 0x1318007, &ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[0], sizeof(ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN)/sizeof(ixPSX81_WRP_PCIE_WRAP_TURNAROUND_DAISYCHAIN[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_WRAP_MISC", REG_SMC, 0x1318008, &ixPSX81_WRP_PCIE_WRAP_MISC[0], sizeof(ixPSX81_WRP_PCIE_WRAP_MISC)/sizeof(ixPSX81_WRP_PCIE_WRAP_MISC[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_WRAP_PIF_MISC", REG_SMC, 0x1318009, &ixPSX81_WRP_PCIE_WRAP_PIF_MISC[0], sizeof(ixPSX81_WRP_PCIE_WRAP_PIF_MISC)/sizeof(ixPSX81_WRP_PCIE_WRAP_PIF_MISC[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_RXDET_OVERRIDE", REG_SMC, 0x131800a, &ixPSX81_WRP_PCIE_RXDET_OVERRIDE[0], sizeof(ixPSX81_WRP_PCIE_RXDET_OVERRIDE)/sizeof(ixPSX81_WRP_PCIE_RXDET_OVERRIDE[0]), 0, 0 },
+	{ "ixPSX81_WRP_IMPCTL_CNTL_PIF0", REG_SMC, 0x1318070, &ixPSX81_WRP_IMPCTL_CNTL_PIF0[0], sizeof(ixPSX81_WRP_IMPCTL_CNTL_PIF0)/sizeof(ixPSX81_WRP_IMPCTL_CNTL_PIF0[0]), 0, 0 },
+	{ "ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL", REG_SMC, 0x1318090, &ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL[0], sizeof(ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL)/sizeof(ixPSX81_WRP_REG_ADAPT_pciecore0_CONTROL[0]), 0, 0 },
+	{ "ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL", REG_SMC, 0x1318096, &ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL[0], sizeof(ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL)/sizeof(ixPSX81_WRP_REG_ADAPT_pwregt_CONTROL[0]), 0, 0 },
+	{ "ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL", REG_SMC, 0x1318097, &ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL[0], sizeof(ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL)/sizeof(ixPSX81_WRP_REG_ADAPT_pwregr_CONTROL[0]), 0, 0 },
+	{ "ixPSX81_WRP_REG_ADAPT_pif0_CONTROL", REG_SMC, 0x1318098, &ixPSX81_WRP_REG_ADAPT_pif0_CONTROL[0], sizeof(ixPSX81_WRP_REG_ADAPT_pif0_CONTROL)/sizeof(ixPSX81_WRP_REG_ADAPT_pif0_CONTROL[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIOSTIMER_CMD", REG_SMC, 0x13180f0, &ixPSX81_WRP_BIOSTIMER_CMD[0], sizeof(ixPSX81_WRP_BIOSTIMER_CMD)/sizeof(ixPSX81_WRP_BIOSTIMER_CMD[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIOSTIMER_CNTL", REG_SMC, 0x13180f1, &ixPSX81_WRP_BIOSTIMER_CNTL[0], sizeof(ixPSX81_WRP_BIOSTIMER_CNTL)/sizeof(ixPSX81_WRP_BIOSTIMER_CNTL[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIOSTIMER_DEBUG", REG_SMC, 0x13180f2, &ixPSX81_WRP_BIOSTIMER_DEBUG[0], sizeof(ixPSX81_WRP_BIOSTIMER_DEBUG)/sizeof(ixPSX81_WRP_BIOSTIMER_DEBUG[0]), 0, 0 },
+	{ "ixPSX81_WRP_DELAYLINE_COMMAND", REG_SMC, 0x131ffd0, &ixPSX81_WRP_DELAYLINE_COMMAND[0], sizeof(ixPSX81_WRP_DELAYLINE_COMMAND)/sizeof(ixPSX81_WRP_DELAYLINE_COMMAND[0]), 0, 0 },
+	{ "ixPSX81_WRP_DELAYLINE_STATUS", REG_SMC, 0x131ffd1, &ixPSX81_WRP_DELAYLINE_STATUS[0], sizeof(ixPSX81_WRP_DELAYLINE_STATUS)/sizeof(ixPSX81_WRP_DELAYLINE_STATUS[0]), 0, 0 },
+	{ "ixPSX81_WRP_DTM_RX_BP_CNTL", REG_SMC, 0x131ffe0, &ixPSX81_WRP_DTM_RX_BP_CNTL[0], sizeof(ixPSX81_WRP_DTM_RX_BP_CNTL)/sizeof(ixPSX81_WRP_DTM_RX_BP_CNTL[0]), 0, 0 },
+	{ "ixPSX81_WRP_DTM_CNTL", REG_SMC, 0x131ffe1, &ixPSX81_WRP_DTM_CNTL[0], sizeof(ixPSX81_WRP_DTM_CNTL)/sizeof(ixPSX81_WRP_DTM_CNTL[0]), 0, 0 },
+	{ "ixPSX81_WRP_DTM_CNTL_LEGACY", REG_SMC, 0x131ffe2, &ixPSX81_WRP_DTM_CNTL_LEGACY[0], sizeof(ixPSX81_WRP_DTM_CNTL_LEGACY)/sizeof(ixPSX81_WRP_DTM_CNTL_LEGACY[0]), 0, 0 },
+	{ "ixPSX81_WRP_DTM_STI_LCLK_CTRL", REG_SMC, 0x131ffe3, &ixPSX81_WRP_DTM_STI_LCLK_CTRL[0], sizeof(ixPSX81_WRP_DTM_STI_LCLK_CTRL)/sizeof(ixPSX81_WRP_DTM_STI_LCLK_CTRL[0]), 0, 0 },
+	{ "ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x", REG_SMC, 0x131ffe4, &ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[0], sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x)/sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clk10x[0]), 0, 0 },
+	{ "ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt", REG_SMC, 0x131ffe5, &ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[0], sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt)/sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_DI_clkGskt[0]), 0, 0 },
+	{ "ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x", REG_SMC, 0x131ffe6, &ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[0], sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x)/sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clk10x[0]), 0, 0 },
+	{ "ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt", REG_SMC, 0x131ffe7, &ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[0], sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt)/sizeof(ixPSX81_WRP_DTM_DENTIST_GATE_TIMING_FI_clkGskt[0]), 0, 0 },
+	{ "mmPMI_CAP_LIST", REG_MMIO, 0x14, &mmPMI_CAP_LIST[0], sizeof(mmPMI_CAP_LIST)/sizeof(mmPMI_CAP_LIST[0]), 0, 0 },
+	{ "mmPMI_CAP", REG_MMIO, 0x14, &mmPMI_CAP[0], sizeof(mmPMI_CAP)/sizeof(mmPMI_CAP[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_RESERVED", REG_SMC, 0x1400000, &ixPSX80_BIF_PCIE_RESERVED[0], sizeof(ixPSX80_BIF_PCIE_RESERVED)/sizeof(ixPSX80_BIF_PCIE_RESERVED[0]), 0, 0 },
+	{ "ixPCIE_RESERVED", REG_SMC, 0x1400000, &ixPCIE_RESERVED[0], sizeof(ixPCIE_RESERVED)/sizeof(ixPCIE_RESERVED[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_SCRATCH", REG_SMC, 0x1400001, &ixPSX80_BIF_PCIE_SCRATCH[0], sizeof(ixPSX80_BIF_PCIE_SCRATCH)/sizeof(ixPSX80_BIF_PCIE_SCRATCH[0]), 0, 0 },
+	{ "ixPCIE_SCRATCH", REG_SMC, 0x1400001, &ixPCIE_SCRATCH[0], sizeof(ixPCIE_SCRATCH)/sizeof(ixPCIE_SCRATCH[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_HW_DEBUG", REG_SMC, 0x1400002, &ixPSX80_BIF_PCIE_HW_DEBUG[0], sizeof(ixPSX80_BIF_PCIE_HW_DEBUG)/sizeof(ixPSX80_BIF_PCIE_HW_DEBUG[0]), 0, 0 },
+	{ "ixPCIE_HW_DEBUG", REG_SMC, 0x1400002, &ixPCIE_HW_DEBUG[0], sizeof(ixPCIE_HW_DEBUG)/sizeof(ixPCIE_HW_DEBUG[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_RX_NUM_NAK", REG_SMC, 0x140000e, &ixPSX80_BIF_PCIE_RX_NUM_NAK[0], sizeof(ixPSX80_BIF_PCIE_RX_NUM_NAK)/sizeof(ixPSX80_BIF_PCIE_RX_NUM_NAK[0]), 0, 0 },
+	{ "ixPCIE_RX_NUM_NAK", REG_SMC, 0x140000e, &ixPCIE_RX_NUM_NAK[0], sizeof(ixPCIE_RX_NUM_NAK)/sizeof(ixPCIE_RX_NUM_NAK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x140000f, &ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPSX80_BIF_PCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 },
+	{ "ixPCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x140000f, &ixPCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_CNTL", REG_SMC, 0x1400010, &ixPSX80_BIF_PCIE_CNTL[0], sizeof(ixPSX80_BIF_PCIE_CNTL)/sizeof(ixPSX80_BIF_PCIE_CNTL[0]), 0, 0 },
+	{ "ixPCIE_CNTL", REG_SMC, 0x1400010, &ixPCIE_CNTL[0], sizeof(ixPCIE_CNTL)/sizeof(ixPCIE_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_CONFIG_CNTL", REG_SMC, 0x1400011, &ixPSX80_BIF_PCIE_CONFIG_CNTL[0], sizeof(ixPSX80_BIF_PCIE_CONFIG_CNTL)/sizeof(ixPSX80_BIF_PCIE_CONFIG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_CONFIG_CNTL", REG_SMC, 0x1400011, &ixPCIE_CONFIG_CNTL[0], sizeof(ixPCIE_CONFIG_CNTL)/sizeof(ixPCIE_CONFIG_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_DEBUG_CNTL", REG_SMC, 0x1400012, &ixPSX80_BIF_PCIE_DEBUG_CNTL[0], sizeof(ixPSX80_BIF_PCIE_DEBUG_CNTL)/sizeof(ixPSX80_BIF_PCIE_DEBUG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_DEBUG_CNTL", REG_SMC, 0x1400012, &ixPCIE_DEBUG_CNTL[0], sizeof(ixPCIE_DEBUG_CNTL)/sizeof(ixPCIE_DEBUG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_INT_CNTL", REG_SMC, 0x140001a, &ixPCIE_INT_CNTL[0], sizeof(ixPCIE_INT_CNTL)/sizeof(ixPCIE_INT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_INT_STATUS", REG_SMC, 0x140001b, &ixPCIE_INT_STATUS[0], sizeof(ixPCIE_INT_STATUS)/sizeof(ixPCIE_INT_STATUS[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_CNTL2", REG_SMC, 0x140001c, &ixPSX80_BIF_PCIE_CNTL2[0], sizeof(ixPSX80_BIF_PCIE_CNTL2)/sizeof(ixPSX80_BIF_PCIE_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_CNTL2", REG_SMC, 0x140001c, &ixPCIE_CNTL2[0], sizeof(ixPCIE_CNTL2)/sizeof(ixPCIE_CNTL2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_RX_CNTL2", REG_SMC, 0x140001d, &ixPSX80_BIF_PCIE_RX_CNTL2[0], sizeof(ixPSX80_BIF_PCIE_RX_CNTL2)/sizeof(ixPSX80_BIF_PCIE_RX_CNTL2[0]), 0, 0 },
+	{ "ixPCIE_RX_CNTL2", REG_SMC, 0x140001d, &ixPCIE_RX_CNTL2[0], sizeof(ixPCIE_RX_CNTL2)/sizeof(ixPCIE_RX_CNTL2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL", REG_SMC, 0x140001e, &ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL[0], sizeof(ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL)/sizeof(ixPSX80_BIF_PCIE_TX_F0_ATTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_F0_ATTR_CNTL", REG_SMC, 0x140001e, &ixPCIE_TX_F0_ATTR_CNTL[0], sizeof(ixPCIE_TX_F0_ATTR_CNTL)/sizeof(ixPCIE_TX_F0_ATTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_TX_F1_F2_ATTR_CNTL", REG_SMC, 0x140001f, &ixPCIE_TX_F1_F2_ATTR_CNTL[0], sizeof(ixPCIE_TX_F1_F2_ATTR_CNTL)/sizeof(ixPCIE_TX_F1_F2_ATTR_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_CI_CNTL", REG_SMC, 0x1400020, &ixPSX80_BIF_PCIE_CI_CNTL[0], sizeof(ixPSX80_BIF_PCIE_CI_CNTL)/sizeof(ixPSX80_BIF_PCIE_CI_CNTL[0]), 0, 0 },
+	{ "ixPCIE_CI_CNTL", REG_SMC, 0x1400020, &ixPCIE_CI_CNTL[0], sizeof(ixPCIE_CI_CNTL)/sizeof(ixPCIE_CI_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_BUS_CNTL", REG_SMC, 0x1400021, &ixPSX80_BIF_PCIE_BUS_CNTL[0], sizeof(ixPSX80_BIF_PCIE_BUS_CNTL)/sizeof(ixPSX80_BIF_PCIE_BUS_CNTL[0]), 0, 0 },
+	{ "ixPCIE_BUS_CNTL", REG_SMC, 0x1400021, &ixPCIE_BUS_CNTL[0], sizeof(ixPCIE_BUS_CNTL)/sizeof(ixPCIE_BUS_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_STATE6", REG_SMC, 0x1400022, &ixPSX80_BIF_PCIE_LC_STATE6[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE6)/sizeof(ixPSX80_BIF_PCIE_LC_STATE6[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE6", REG_SMC, 0x1400022, &ixPCIE_LC_STATE6[0], sizeof(ixPCIE_LC_STATE6)/sizeof(ixPCIE_LC_STATE6[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_STATE7", REG_SMC, 0x1400023, &ixPSX80_BIF_PCIE_LC_STATE7[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE7)/sizeof(ixPSX80_BIF_PCIE_LC_STATE7[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE7", REG_SMC, 0x1400023, &ixPCIE_LC_STATE7[0], sizeof(ixPCIE_LC_STATE7)/sizeof(ixPCIE_LC_STATE7[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_STATE8", REG_SMC, 0x1400024, &ixPSX80_BIF_PCIE_LC_STATE8[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE8)/sizeof(ixPSX80_BIF_PCIE_LC_STATE8[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE8", REG_SMC, 0x1400024, &ixPCIE_LC_STATE8[0], sizeof(ixPCIE_LC_STATE8)/sizeof(ixPCIE_LC_STATE8[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_STATE9", REG_SMC, 0x1400025, &ixPSX80_BIF_PCIE_LC_STATE9[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE9)/sizeof(ixPSX80_BIF_PCIE_LC_STATE9[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE9", REG_SMC, 0x1400025, &ixPCIE_LC_STATE9[0], sizeof(ixPCIE_LC_STATE9)/sizeof(ixPCIE_LC_STATE9[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_STATE10", REG_SMC, 0x1400026, &ixPSX80_BIF_PCIE_LC_STATE10[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE10)/sizeof(ixPSX80_BIF_PCIE_LC_STATE10[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE10", REG_SMC, 0x1400026, &ixPCIE_LC_STATE10[0], sizeof(ixPCIE_LC_STATE10)/sizeof(ixPCIE_LC_STATE10[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_STATE11", REG_SMC, 0x1400027, &ixPSX80_BIF_PCIE_LC_STATE11[0], sizeof(ixPSX80_BIF_PCIE_LC_STATE11)/sizeof(ixPSX80_BIF_PCIE_LC_STATE11[0]), 0, 0 },
+	{ "ixPCIE_LC_STATE11", REG_SMC, 0x1400027, &ixPCIE_LC_STATE11[0], sizeof(ixPCIE_LC_STATE11)/sizeof(ixPCIE_LC_STATE11[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_STATUS1", REG_SMC, 0x1400028, &ixPSX80_BIF_PCIE_LC_STATUS1[0], sizeof(ixPSX80_BIF_PCIE_LC_STATUS1)/sizeof(ixPSX80_BIF_PCIE_LC_STATUS1[0]), 0, 0 },
+	{ "ixPCIE_LC_STATUS1", REG_SMC, 0x1400028, &ixPCIE_LC_STATUS1[0], sizeof(ixPCIE_LC_STATUS1)/sizeof(ixPCIE_LC_STATUS1[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_STATUS2", REG_SMC, 0x1400029, &ixPSX80_BIF_PCIE_LC_STATUS2[0], sizeof(ixPSX80_BIF_PCIE_LC_STATUS2)/sizeof(ixPSX80_BIF_PCIE_LC_STATUS2[0]), 0, 0 },
+	{ "ixPCIE_LC_STATUS2", REG_SMC, 0x1400029, &ixPCIE_LC_STATUS2[0], sizeof(ixPCIE_LC_STATUS2)/sizeof(ixPCIE_LC_STATUS2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_WPR_CNTL", REG_SMC, 0x1400030, &ixPSX80_BIF_PCIE_WPR_CNTL[0], sizeof(ixPSX80_BIF_PCIE_WPR_CNTL)/sizeof(ixPSX80_BIF_PCIE_WPR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_WPR_CNTL", REG_SMC, 0x1400030, &ixPCIE_WPR_CNTL[0], sizeof(ixPCIE_WPR_CNTL)/sizeof(ixPCIE_WPR_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_RX_LAST_TLP0", REG_SMC, 0x1400031, &ixPSX80_BIF_PCIE_RX_LAST_TLP0[0], sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP0)/sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP0", REG_SMC, 0x1400031, &ixPCIE_RX_LAST_TLP0[0], sizeof(ixPCIE_RX_LAST_TLP0)/sizeof(ixPCIE_RX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_RX_LAST_TLP1", REG_SMC, 0x1400032, &ixPSX80_BIF_PCIE_RX_LAST_TLP1[0], sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP1)/sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP1", REG_SMC, 0x1400032, &ixPCIE_RX_LAST_TLP1[0], sizeof(ixPCIE_RX_LAST_TLP1)/sizeof(ixPCIE_RX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_RX_LAST_TLP2", REG_SMC, 0x1400033, &ixPSX80_BIF_PCIE_RX_LAST_TLP2[0], sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP2)/sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP2", REG_SMC, 0x1400033, &ixPCIE_RX_LAST_TLP2[0], sizeof(ixPCIE_RX_LAST_TLP2)/sizeof(ixPCIE_RX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_RX_LAST_TLP3", REG_SMC, 0x1400034, &ixPSX80_BIF_PCIE_RX_LAST_TLP3[0], sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP3)/sizeof(ixPSX80_BIF_PCIE_RX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPCIE_RX_LAST_TLP3", REG_SMC, 0x1400034, &ixPCIE_RX_LAST_TLP3[0], sizeof(ixPCIE_RX_LAST_TLP3)/sizeof(ixPCIE_RX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_TX_LAST_TLP0", REG_SMC, 0x1400035, &ixPSX80_BIF_PCIE_TX_LAST_TLP0[0], sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP0)/sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP0", REG_SMC, 0x1400035, &ixPCIE_TX_LAST_TLP0[0], sizeof(ixPCIE_TX_LAST_TLP0)/sizeof(ixPCIE_TX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_TX_LAST_TLP1", REG_SMC, 0x1400036, &ixPSX80_BIF_PCIE_TX_LAST_TLP1[0], sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP1)/sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP1", REG_SMC, 0x1400036, &ixPCIE_TX_LAST_TLP1[0], sizeof(ixPCIE_TX_LAST_TLP1)/sizeof(ixPCIE_TX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_TX_LAST_TLP2", REG_SMC, 0x1400037, &ixPSX80_BIF_PCIE_TX_LAST_TLP2[0], sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP2)/sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP2", REG_SMC, 0x1400037, &ixPCIE_TX_LAST_TLP2[0], sizeof(ixPCIE_TX_LAST_TLP2)/sizeof(ixPCIE_TX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_TX_LAST_TLP3", REG_SMC, 0x1400038, &ixPSX80_BIF_PCIE_TX_LAST_TLP3[0], sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP3)/sizeof(ixPSX80_BIF_PCIE_TX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPCIE_TX_LAST_TLP3", REG_SMC, 0x1400038, &ixPCIE_TX_LAST_TLP3[0], sizeof(ixPCIE_TX_LAST_TLP3)/sizeof(ixPCIE_TX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND", REG_SMC, 0x140003a, &ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND[0], sizeof(ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND)/sizeof(ixPSX80_BIF_PCIE_I2C_REG_ADDR_EXPAND[0]), 0, 0 },
+	{ "ixPCIE_I2C_REG_ADDR_EXPAND", REG_SMC, 0x140003a, &ixPCIE_I2C_REG_ADDR_EXPAND[0], sizeof(ixPCIE_I2C_REG_ADDR_EXPAND)/sizeof(ixPCIE_I2C_REG_ADDR_EXPAND[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_I2C_REG_DATA", REG_SMC, 0x140003b, &ixPSX80_BIF_PCIE_I2C_REG_DATA[0], sizeof(ixPSX80_BIF_PCIE_I2C_REG_DATA)/sizeof(ixPSX80_BIF_PCIE_I2C_REG_DATA[0]), 0, 0 },
+	{ "ixPCIE_I2C_REG_DATA", REG_SMC, 0x140003b, &ixPCIE_I2C_REG_DATA[0], sizeof(ixPCIE_I2C_REG_DATA)/sizeof(ixPCIE_I2C_REG_DATA[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_CFG_CNTL", REG_SMC, 0x140003c, &ixPSX80_BIF_PCIE_CFG_CNTL[0], sizeof(ixPSX80_BIF_PCIE_CFG_CNTL)/sizeof(ixPSX80_BIF_PCIE_CFG_CNTL[0]), 0, 0 },
+	{ "ixPCIE_CFG_CNTL", REG_SMC, 0x140003c, &ixPCIE_CFG_CNTL[0], sizeof(ixPCIE_CFG_CNTL)/sizeof(ixPCIE_CFG_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_LC_PM_CNTL", REG_SMC, 0x140003d, &ixPSX80_BIF_PCIE_LC_PM_CNTL[0], sizeof(ixPSX80_BIF_PCIE_LC_PM_CNTL)/sizeof(ixPSX80_BIF_PCIE_LC_PM_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_P_CNTL", REG_SMC, 0x1400040, &ixPSX80_BIF_PCIE_P_CNTL[0], sizeof(ixPSX80_BIF_PCIE_P_CNTL)/sizeof(ixPSX80_BIF_PCIE_P_CNTL[0]), 0, 0 },
+	{ "ixPCIE_P_CNTL", REG_SMC, 0x1400040, &ixPCIE_P_CNTL[0], sizeof(ixPCIE_P_CNTL)/sizeof(ixPCIE_P_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_P_BUF_STATUS", REG_SMC, 0x1400041, &ixPSX80_BIF_PCIE_P_BUF_STATUS[0], sizeof(ixPSX80_BIF_PCIE_P_BUF_STATUS)/sizeof(ixPSX80_BIF_PCIE_P_BUF_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_BUF_STATUS", REG_SMC, 0x1400041, &ixPCIE_P_BUF_STATUS[0], sizeof(ixPCIE_P_BUF_STATUS)/sizeof(ixPCIE_P_BUF_STATUS[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_P_DECODER_STATUS", REG_SMC, 0x1400042, &ixPSX80_BIF_PCIE_P_DECODER_STATUS[0], sizeof(ixPSX80_BIF_PCIE_P_DECODER_STATUS)/sizeof(ixPSX80_BIF_PCIE_P_DECODER_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_DECODER_STATUS", REG_SMC, 0x1400042, &ixPCIE_P_DECODER_STATUS[0], sizeof(ixPCIE_P_DECODER_STATUS)/sizeof(ixPCIE_P_DECODER_STATUS[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_P_MISC_STATUS", REG_SMC, 0x1400043, &ixPSX80_BIF_PCIE_P_MISC_STATUS[0], sizeof(ixPSX80_BIF_PCIE_P_MISC_STATUS)/sizeof(ixPSX80_BIF_PCIE_P_MISC_STATUS[0]), 0, 0 },
+	{ "ixPCIE_P_MISC_STATUS", REG_SMC, 0x1400043, &ixPCIE_P_MISC_STATUS[0], sizeof(ixPCIE_P_MISC_STATUS)/sizeof(ixPCIE_P_MISC_STATUS[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET", REG_SMC, 0x1400050, &ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET[0], sizeof(ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET)/sizeof(ixPSX80_BIF_PCIE_P_RCV_L0S_FTS_DET[0]), 0, 0 },
+	{ "ixPCIE_P_RCV_L0S_FTS_DET", REG_SMC, 0x1400050, &ixPCIE_P_RCV_L0S_FTS_DET[0], sizeof(ixPCIE_P_RCV_L0S_FTS_DET)/sizeof(ixPCIE_P_RCV_L0S_FTS_DET[0]), 0, 0 },
+	{ "ixPCIE_TX_LTR_CNTL", REG_SMC, 0x1400060, &ixPCIE_TX_LTR_CNTL[0], sizeof(ixPCIE_TX_LTR_CNTL)/sizeof(ixPCIE_TX_LTR_CNTL[0]), 0, 0 },
+	{ "ixPCIE_OBFF_CNTL", REG_SMC, 0x1400061, &ixPCIE_OBFF_CNTL[0], sizeof(ixPCIE_OBFF_CNTL)/sizeof(ixPCIE_OBFF_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT_CNTL", REG_SMC, 0x1400080, &ixPSX80_BIF_PCIE_PERF_COUNT_CNTL[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT_CNTL)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT_CNTL[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT_CNTL", REG_SMC, 0x1400080, &ixPCIE_PERF_COUNT_CNTL[0], sizeof(ixPCIE_PERF_COUNT_CNTL)/sizeof(ixPCIE_PERF_COUNT_CNTL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK", REG_SMC, 0x1400081, &ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_TXCLK", REG_SMC, 0x1400081, &ixPCIE_PERF_CNTL_TXCLK[0], sizeof(ixPCIE_PERF_CNTL_TXCLK)/sizeof(ixPCIE_PERF_CNTL_TXCLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x1400082, &ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x1400082, &ixPCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK)/sizeof(ixPCIE_PERF_COUNT0_TXCLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x1400083, &ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x1400083, &ixPCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK)/sizeof(ixPCIE_PERF_COUNT1_TXCLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x1400084, &ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x1400084, &ixPCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x1400085, &ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x1400085, &ixPCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x1400086, &ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x1400086, &ixPCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x1400087, &ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x1400087, &ixPCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x1400088, &ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x1400088, &ixPCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x1400089, &ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x1400089, &ixPCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x140008a, &ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x140008a, &ixPCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x140008b, &ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x140008b, &ixPCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x140008c, &ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x140008c, &ixPCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x140008d, &ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x140008d, &ixPCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x140008e, &ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x140008e, &ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x140008f, &ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x140008f, &ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x1400090, &ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x1400090, &ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x1400091, &ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x1400091, &ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x1400092, &ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x1400092, &ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x1400093, &ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x1400093, &ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x1400094, &ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x1400094, &ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x1400095, &ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2)/sizeof(ixPSX80_BIF_PCIE_PERF_CNTL_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x1400095, &ixPCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPCIE_PERF_CNTL_TXCLK2)/sizeof(ixPCIE_PERF_CNTL_TXCLK2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x1400096, &ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x1400096, &ixPCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x1400097, &ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPSX80_BIF_PCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 },
+	{ "ixPCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x1400097, &ixPCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_STRAP_F0", REG_SMC, 0x14000b0, &ixPSX80_BIF_PCIE_STRAP_F0[0], sizeof(ixPSX80_BIF_PCIE_STRAP_F0)/sizeof(ixPSX80_BIF_PCIE_STRAP_F0[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F0", REG_SMC, 0x14000b0, &ixPCIE_STRAP_F0[0], sizeof(ixPCIE_STRAP_F0)/sizeof(ixPCIE_STRAP_F0[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F1", REG_SMC, 0x14000b1, &ixPCIE_STRAP_F1[0], sizeof(ixPCIE_STRAP_F1)/sizeof(ixPCIE_STRAP_F1[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F2", REG_SMC, 0x14000b2, &ixPCIE_STRAP_F2[0], sizeof(ixPCIE_STRAP_F2)/sizeof(ixPCIE_STRAP_F2[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F3", REG_SMC, 0x14000b3, &ixPCIE_STRAP_F3[0], sizeof(ixPCIE_STRAP_F3)/sizeof(ixPCIE_STRAP_F3[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F4", REG_SMC, 0x14000b4, &ixPCIE_STRAP_F4[0], sizeof(ixPCIE_STRAP_F4)/sizeof(ixPCIE_STRAP_F4[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F5", REG_SMC, 0x14000b5, &ixPCIE_STRAP_F5[0], sizeof(ixPCIE_STRAP_F5)/sizeof(ixPCIE_STRAP_F5[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F6", REG_SMC, 0x14000b6, &ixPCIE_STRAP_F6[0], sizeof(ixPCIE_STRAP_F6)/sizeof(ixPCIE_STRAP_F6[0]), 0, 0 },
+	{ "ixPCIE_STRAP_F7", REG_SMC, 0x14000b7, &ixPCIE_STRAP_F7[0], sizeof(ixPCIE_STRAP_F7)/sizeof(ixPCIE_STRAP_F7[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_STRAP_MISC", REG_SMC, 0x14000c0, &ixPSX80_BIF_PCIE_STRAP_MISC[0], sizeof(ixPSX80_BIF_PCIE_STRAP_MISC)/sizeof(ixPSX80_BIF_PCIE_STRAP_MISC[0]), 0, 0 },
+	{ "ixPCIE_STRAP_MISC", REG_SMC, 0x14000c0, &ixPCIE_STRAP_MISC[0], sizeof(ixPCIE_STRAP_MISC)/sizeof(ixPCIE_STRAP_MISC[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_STRAP_MISC2", REG_SMC, 0x14000c1, &ixPSX80_BIF_PCIE_STRAP_MISC2[0], sizeof(ixPSX80_BIF_PCIE_STRAP_MISC2)/sizeof(ixPSX80_BIF_PCIE_STRAP_MISC2[0]), 0, 0 },
+	{ "ixPCIE_STRAP_MISC2", REG_SMC, 0x14000c1, &ixPCIE_STRAP_MISC2[0], sizeof(ixPCIE_STRAP_MISC2)/sizeof(ixPCIE_STRAP_MISC2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_STRAP_PI", REG_SMC, 0x14000c2, &ixPSX80_BIF_PCIE_STRAP_PI[0], sizeof(ixPSX80_BIF_PCIE_STRAP_PI)/sizeof(ixPSX80_BIF_PCIE_STRAP_PI[0]), 0, 0 },
+	{ "ixPCIE_STRAP_PI", REG_SMC, 0x14000c2, &ixPCIE_STRAP_PI[0], sizeof(ixPCIE_STRAP_PI)/sizeof(ixPCIE_STRAP_PI[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_STRAP_I2C_BD", REG_SMC, 0x14000c4, &ixPSX80_BIF_PCIE_STRAP_I2C_BD[0], sizeof(ixPSX80_BIF_PCIE_STRAP_I2C_BD)/sizeof(ixPSX80_BIF_PCIE_STRAP_I2C_BD[0]), 0, 0 },
+	{ "ixPCIE_STRAP_I2C_BD", REG_SMC, 0x14000c4, &ixPCIE_STRAP_I2C_BD[0], sizeof(ixPCIE_STRAP_I2C_BD)/sizeof(ixPCIE_STRAP_I2C_BD[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_CLR", REG_SMC, 0x14000c8, &ixPSX80_BIF_PCIE_PRBS_CLR[0], sizeof(ixPSX80_BIF_PCIE_PRBS_CLR)/sizeof(ixPSX80_BIF_PCIE_PRBS_CLR[0]), 0, 0 },
+	{ "ixPCIE_PRBS_CLR", REG_SMC, 0x14000c8, &ixPCIE_PRBS_CLR[0], sizeof(ixPCIE_PRBS_CLR)/sizeof(ixPCIE_PRBS_CLR[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_STATUS1", REG_SMC, 0x14000c9, &ixPSX80_BIF_PCIE_PRBS_STATUS1[0], sizeof(ixPSX80_BIF_PCIE_PRBS_STATUS1)/sizeof(ixPSX80_BIF_PCIE_PRBS_STATUS1[0]), 0, 0 },
+	{ "ixPCIE_PRBS_STATUS1", REG_SMC, 0x14000c9, &ixPCIE_PRBS_STATUS1[0], sizeof(ixPCIE_PRBS_STATUS1)/sizeof(ixPCIE_PRBS_STATUS1[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_STATUS2", REG_SMC, 0x14000ca, &ixPSX80_BIF_PCIE_PRBS_STATUS2[0], sizeof(ixPSX80_BIF_PCIE_PRBS_STATUS2)/sizeof(ixPSX80_BIF_PCIE_PRBS_STATUS2[0]), 0, 0 },
+	{ "ixPCIE_PRBS_STATUS2", REG_SMC, 0x14000ca, &ixPCIE_PRBS_STATUS2[0], sizeof(ixPCIE_PRBS_STATUS2)/sizeof(ixPCIE_PRBS_STATUS2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_FREERUN", REG_SMC, 0x14000cb, &ixPSX80_BIF_PCIE_PRBS_FREERUN[0], sizeof(ixPSX80_BIF_PCIE_PRBS_FREERUN)/sizeof(ixPSX80_BIF_PCIE_PRBS_FREERUN[0]), 0, 0 },
+	{ "ixPCIE_PRBS_FREERUN", REG_SMC, 0x14000cb, &ixPCIE_PRBS_FREERUN[0], sizeof(ixPCIE_PRBS_FREERUN)/sizeof(ixPCIE_PRBS_FREERUN[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_MISC", REG_SMC, 0x14000cc, &ixPSX80_BIF_PCIE_PRBS_MISC[0], sizeof(ixPSX80_BIF_PCIE_PRBS_MISC)/sizeof(ixPSX80_BIF_PCIE_PRBS_MISC[0]), 0, 0 },
+	{ "ixPCIE_PRBS_MISC", REG_SMC, 0x14000cc, &ixPCIE_PRBS_MISC[0], sizeof(ixPCIE_PRBS_MISC)/sizeof(ixPCIE_PRBS_MISC[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_USER_PATTERN", REG_SMC, 0x14000cd, &ixPSX80_BIF_PCIE_PRBS_USER_PATTERN[0], sizeof(ixPSX80_BIF_PCIE_PRBS_USER_PATTERN)/sizeof(ixPSX80_BIF_PCIE_PRBS_USER_PATTERN[0]), 0, 0 },
+	{ "ixPCIE_PRBS_USER_PATTERN", REG_SMC, 0x14000cd, &ixPCIE_PRBS_USER_PATTERN[0], sizeof(ixPCIE_PRBS_USER_PATTERN)/sizeof(ixPCIE_PRBS_USER_PATTERN[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_LO_BITCNT", REG_SMC, 0x14000ce, &ixPSX80_BIF_PCIE_PRBS_LO_BITCNT[0], sizeof(ixPSX80_BIF_PCIE_PRBS_LO_BITCNT)/sizeof(ixPSX80_BIF_PCIE_PRBS_LO_BITCNT[0]), 0, 0 },
+	{ "ixPCIE_PRBS_LO_BITCNT", REG_SMC, 0x14000ce, &ixPCIE_PRBS_LO_BITCNT[0], sizeof(ixPCIE_PRBS_LO_BITCNT)/sizeof(ixPCIE_PRBS_LO_BITCNT[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_HI_BITCNT", REG_SMC, 0x14000cf, &ixPSX80_BIF_PCIE_PRBS_HI_BITCNT[0], sizeof(ixPSX80_BIF_PCIE_PRBS_HI_BITCNT)/sizeof(ixPSX80_BIF_PCIE_PRBS_HI_BITCNT[0]), 0, 0 },
+	{ "ixPCIE_PRBS_HI_BITCNT", REG_SMC, 0x14000cf, &ixPCIE_PRBS_HI_BITCNT[0], sizeof(ixPCIE_PRBS_HI_BITCNT)/sizeof(ixPCIE_PRBS_HI_BITCNT[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_0", REG_SMC, 0x14000d0, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_0[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_0)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_0[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_0", REG_SMC, 0x14000d0, &ixPCIE_PRBS_ERRCNT_0[0], sizeof(ixPCIE_PRBS_ERRCNT_0)/sizeof(ixPCIE_PRBS_ERRCNT_0[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_1", REG_SMC, 0x14000d1, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_1[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_1)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_1[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_1", REG_SMC, 0x14000d1, &ixPCIE_PRBS_ERRCNT_1[0], sizeof(ixPCIE_PRBS_ERRCNT_1)/sizeof(ixPCIE_PRBS_ERRCNT_1[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_2", REG_SMC, 0x14000d2, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_2[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_2)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_2[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_2", REG_SMC, 0x14000d2, &ixPCIE_PRBS_ERRCNT_2[0], sizeof(ixPCIE_PRBS_ERRCNT_2)/sizeof(ixPCIE_PRBS_ERRCNT_2[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_3", REG_SMC, 0x14000d3, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_3[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_3)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_3[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_3", REG_SMC, 0x14000d3, &ixPCIE_PRBS_ERRCNT_3[0], sizeof(ixPCIE_PRBS_ERRCNT_3)/sizeof(ixPCIE_PRBS_ERRCNT_3[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_4", REG_SMC, 0x14000d4, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_4[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_4)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_4[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_4", REG_SMC, 0x14000d4, &ixPCIE_PRBS_ERRCNT_4[0], sizeof(ixPCIE_PRBS_ERRCNT_4)/sizeof(ixPCIE_PRBS_ERRCNT_4[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_5", REG_SMC, 0x14000d5, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_5[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_5)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_5[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_5", REG_SMC, 0x14000d5, &ixPCIE_PRBS_ERRCNT_5[0], sizeof(ixPCIE_PRBS_ERRCNT_5)/sizeof(ixPCIE_PRBS_ERRCNT_5[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_6", REG_SMC, 0x14000d6, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_6[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_6)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_6[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_6", REG_SMC, 0x14000d6, &ixPCIE_PRBS_ERRCNT_6[0], sizeof(ixPCIE_PRBS_ERRCNT_6)/sizeof(ixPCIE_PRBS_ERRCNT_6[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_7", REG_SMC, 0x14000d7, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_7[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_7)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_7[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_7", REG_SMC, 0x14000d7, &ixPCIE_PRBS_ERRCNT_7[0], sizeof(ixPCIE_PRBS_ERRCNT_7)/sizeof(ixPCIE_PRBS_ERRCNT_7[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_8", REG_SMC, 0x14000d8, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_8[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_8)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_8[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_8", REG_SMC, 0x14000d8, &ixPCIE_PRBS_ERRCNT_8[0], sizeof(ixPCIE_PRBS_ERRCNT_8)/sizeof(ixPCIE_PRBS_ERRCNT_8[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_9", REG_SMC, 0x14000d9, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_9[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_9)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_9[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_9", REG_SMC, 0x14000d9, &ixPCIE_PRBS_ERRCNT_9[0], sizeof(ixPCIE_PRBS_ERRCNT_9)/sizeof(ixPCIE_PRBS_ERRCNT_9[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_10", REG_SMC, 0x14000da, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_10[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_10)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_10[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_10", REG_SMC, 0x14000da, &ixPCIE_PRBS_ERRCNT_10[0], sizeof(ixPCIE_PRBS_ERRCNT_10)/sizeof(ixPCIE_PRBS_ERRCNT_10[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_11", REG_SMC, 0x14000db, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_11[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_11)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_11[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_11", REG_SMC, 0x14000db, &ixPCIE_PRBS_ERRCNT_11[0], sizeof(ixPCIE_PRBS_ERRCNT_11)/sizeof(ixPCIE_PRBS_ERRCNT_11[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_12", REG_SMC, 0x14000dc, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_12[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_12)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_12[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_12", REG_SMC, 0x14000dc, &ixPCIE_PRBS_ERRCNT_12[0], sizeof(ixPCIE_PRBS_ERRCNT_12)/sizeof(ixPCIE_PRBS_ERRCNT_12[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_13", REG_SMC, 0x14000dd, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_13[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_13)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_13[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_13", REG_SMC, 0x14000dd, &ixPCIE_PRBS_ERRCNT_13[0], sizeof(ixPCIE_PRBS_ERRCNT_13)/sizeof(ixPCIE_PRBS_ERRCNT_13[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_14", REG_SMC, 0x14000de, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_14[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_14)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_14[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_14", REG_SMC, 0x14000de, &ixPCIE_PRBS_ERRCNT_14[0], sizeof(ixPCIE_PRBS_ERRCNT_14)/sizeof(ixPCIE_PRBS_ERRCNT_14[0]), 0, 0 },
+	{ "ixPSX80_BIF_PCIE_PRBS_ERRCNT_15", REG_SMC, 0x14000df, &ixPSX80_BIF_PCIE_PRBS_ERRCNT_15[0], sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_15)/sizeof(ixPSX80_BIF_PCIE_PRBS_ERRCNT_15[0]), 0, 0 },
+	{ "ixPCIE_PRBS_ERRCNT_15", REG_SMC, 0x14000df, &ixPCIE_PRBS_ERRCNT_15[0], sizeof(ixPCIE_PRBS_ERRCNT_15)/sizeof(ixPCIE_PRBS_ERRCNT_15[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_CAP", REG_SMC, 0x14000e0, &ixPCIE_F0_DPA_CAP[0], sizeof(ixPCIE_F0_DPA_CAP)/sizeof(ixPCIE_F0_DPA_CAP[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_LATENCY_INDICATOR", REG_SMC, 0x14000e4, &ixPCIE_F0_DPA_LATENCY_INDICATOR[0], sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR)/sizeof(ixPCIE_F0_DPA_LATENCY_INDICATOR[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_CNTL", REG_SMC, 0x14000e5, &ixPCIE_F0_DPA_CNTL[0], sizeof(ixPCIE_F0_DPA_CNTL)/sizeof(ixPCIE_F0_DPA_CNTL[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0", REG_SMC, 0x14000e7, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1", REG_SMC, 0x14000e8, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2", REG_SMC, 0x14000e9, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3", REG_SMC, 0x14000ea, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4", REG_SMC, 0x14000eb, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5", REG_SMC, 0x14000ec, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6", REG_SMC, 0x14000ed, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6[0]), 0, 0 },
+	{ "ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7", REG_SMC, 0x14000ee, &ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0], sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7)/sizeof(ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_COMMAND_STATUS", REG_SMC, 0x1400100, &ixPSX80_BIF_SWRST_COMMAND_STATUS[0], sizeof(ixPSX80_BIF_SWRST_COMMAND_STATUS)/sizeof(ixPSX80_BIF_SWRST_COMMAND_STATUS[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_GENERAL_CONTROL", REG_SMC, 0x1400101, &ixPSX80_BIF_SWRST_GENERAL_CONTROL[0], sizeof(ixPSX80_BIF_SWRST_GENERAL_CONTROL)/sizeof(ixPSX80_BIF_SWRST_GENERAL_CONTROL[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_COMMAND_0", REG_SMC, 0x1400102, &ixPSX80_BIF_SWRST_COMMAND_0[0], sizeof(ixPSX80_BIF_SWRST_COMMAND_0)/sizeof(ixPSX80_BIF_SWRST_COMMAND_0[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_COMMAND_1", REG_SMC, 0x1400103, &ixPSX80_BIF_SWRST_COMMAND_1[0], sizeof(ixPSX80_BIF_SWRST_COMMAND_1)/sizeof(ixPSX80_BIF_SWRST_COMMAND_1[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_CONTROL_0", REG_SMC, 0x1400104, &ixPSX80_BIF_SWRST_CONTROL_0[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_0)/sizeof(ixPSX80_BIF_SWRST_CONTROL_0[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_CONTROL_1", REG_SMC, 0x1400105, &ixPSX80_BIF_SWRST_CONTROL_1[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_1)/sizeof(ixPSX80_BIF_SWRST_CONTROL_1[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_CONTROL_2", REG_SMC, 0x1400106, &ixPSX80_BIF_SWRST_CONTROL_2[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_2)/sizeof(ixPSX80_BIF_SWRST_CONTROL_2[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_CONTROL_3", REG_SMC, 0x1400107, &ixPSX80_BIF_SWRST_CONTROL_3[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_3)/sizeof(ixPSX80_BIF_SWRST_CONTROL_3[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_CONTROL_4", REG_SMC, 0x1400108, &ixPSX80_BIF_SWRST_CONTROL_4[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_4)/sizeof(ixPSX80_BIF_SWRST_CONTROL_4[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_CONTROL_5", REG_SMC, 0x1400109, &ixPSX80_BIF_SWRST_CONTROL_5[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_5)/sizeof(ixPSX80_BIF_SWRST_CONTROL_5[0]), 0, 0 },
+	{ "ixPSX80_BIF_SWRST_CONTROL_6", REG_SMC, 0x140010a, &ixPSX80_BIF_SWRST_CONTROL_6[0], sizeof(ixPSX80_BIF_SWRST_CONTROL_6)/sizeof(ixPSX80_BIF_SWRST_CONTROL_6[0]), 0, 0 },
+	{ "ixPSX80_BIF_CPM_CONTROL", REG_SMC, 0x1400118, &ixPSX80_BIF_CPM_CONTROL[0], sizeof(ixPSX80_BIF_CPM_CONTROL)/sizeof(ixPSX80_BIF_CPM_CONTROL[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_CONTROL", REG_SMC, 0x1400120, &ixPSX80_BIF_LM_CONTROL[0], sizeof(ixPSX80_BIF_LM_CONTROL)/sizeof(ixPSX80_BIF_LM_CONTROL[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PCIETXMUX0", REG_SMC, 0x1400121, &ixPSX80_BIF_LM_PCIETXMUX0[0], sizeof(ixPSX80_BIF_LM_PCIETXMUX0)/sizeof(ixPSX80_BIF_LM_PCIETXMUX0[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PCIETXMUX1", REG_SMC, 0x1400122, &ixPSX80_BIF_LM_PCIETXMUX1[0], sizeof(ixPSX80_BIF_LM_PCIETXMUX1)/sizeof(ixPSX80_BIF_LM_PCIETXMUX1[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PCIETXMUX2", REG_SMC, 0x1400123, &ixPSX80_BIF_LM_PCIETXMUX2[0], sizeof(ixPSX80_BIF_LM_PCIETXMUX2)/sizeof(ixPSX80_BIF_LM_PCIETXMUX2[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PCIETXMUX3", REG_SMC, 0x1400124, &ixPSX80_BIF_LM_PCIETXMUX3[0], sizeof(ixPSX80_BIF_LM_PCIETXMUX3)/sizeof(ixPSX80_BIF_LM_PCIETXMUX3[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PCIERXMUX0", REG_SMC, 0x1400125, &ixPSX80_BIF_LM_PCIERXMUX0[0], sizeof(ixPSX80_BIF_LM_PCIERXMUX0)/sizeof(ixPSX80_BIF_LM_PCIERXMUX0[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PCIERXMUX1", REG_SMC, 0x1400126, &ixPSX80_BIF_LM_PCIERXMUX1[0], sizeof(ixPSX80_BIF_LM_PCIERXMUX1)/sizeof(ixPSX80_BIF_LM_PCIERXMUX1[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PCIERXMUX2", REG_SMC, 0x1400127, &ixPSX80_BIF_LM_PCIERXMUX2[0], sizeof(ixPSX80_BIF_LM_PCIERXMUX2)/sizeof(ixPSX80_BIF_LM_PCIERXMUX2[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PCIERXMUX3", REG_SMC, 0x1400128, &ixPSX80_BIF_LM_PCIERXMUX3[0], sizeof(ixPSX80_BIF_LM_PCIERXMUX3)/sizeof(ixPSX80_BIF_LM_PCIERXMUX3[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_LANEENABLE", REG_SMC, 0x1400129, &ixPSX80_BIF_LM_LANEENABLE[0], sizeof(ixPSX80_BIF_LM_LANEENABLE)/sizeof(ixPSX80_BIF_LM_LANEENABLE[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_PRBSCONTROL", REG_SMC, 0x140012a, &ixPSX80_BIF_LM_PRBSCONTROL[0], sizeof(ixPSX80_BIF_LM_PRBSCONTROL)/sizeof(ixPSX80_BIF_LM_PRBSCONTROL[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_POWERCONTROL", REG_SMC, 0x140012b, &ixPSX80_BIF_LM_POWERCONTROL[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL)/sizeof(ixPSX80_BIF_LM_POWERCONTROL[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_POWERCONTROL1", REG_SMC, 0x140012c, &ixPSX80_BIF_LM_POWERCONTROL1[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL1)/sizeof(ixPSX80_BIF_LM_POWERCONTROL1[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_POWERCONTROL2", REG_SMC, 0x140012d, &ixPSX80_BIF_LM_POWERCONTROL2[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL2)/sizeof(ixPSX80_BIF_LM_POWERCONTROL2[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_POWERCONTROL3", REG_SMC, 0x140012e, &ixPSX80_BIF_LM_POWERCONTROL3[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL3)/sizeof(ixPSX80_BIF_LM_POWERCONTROL3[0]), 0, 0 },
+	{ "ixPSX80_BIF_LM_POWERCONTROL4", REG_SMC, 0x140012f, &ixPSX80_BIF_LM_POWERCONTROL4[0], sizeof(ixPSX80_BIF_LM_POWERCONTROL4)/sizeof(ixPSX80_BIF_LM_POWERCONTROL4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_CNTL", REG_MMIO, 0x1401, &mmGARLIC_FLUSH_CNTL[0], sizeof(mmGARLIC_FLUSH_CNTL)/sizeof(mmGARLIC_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_0", REG_MMIO, 0x1402, &mmGARLIC_FLUSH_ADDR_START_0[0], sizeof(mmGARLIC_FLUSH_ADDR_START_0)/sizeof(mmGARLIC_FLUSH_ADDR_START_0[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_0", REG_MMIO, 0x1403, &mmGARLIC_FLUSH_ADDR_END_0[0], sizeof(mmGARLIC_FLUSH_ADDR_END_0)/sizeof(mmGARLIC_FLUSH_ADDR_END_0[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_1", REG_MMIO, 0x1404, &mmGARLIC_FLUSH_ADDR_START_1[0], sizeof(mmGARLIC_FLUSH_ADDR_START_1)/sizeof(mmGARLIC_FLUSH_ADDR_START_1[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_1", REG_MMIO, 0x1405, &mmGARLIC_FLUSH_ADDR_END_1[0], sizeof(mmGARLIC_FLUSH_ADDR_END_1)/sizeof(mmGARLIC_FLUSH_ADDR_END_1[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_2", REG_MMIO, 0x1406, &mmGARLIC_FLUSH_ADDR_START_2[0], sizeof(mmGARLIC_FLUSH_ADDR_START_2)/sizeof(mmGARLIC_FLUSH_ADDR_START_2[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_2", REG_MMIO, 0x1407, &mmGARLIC_FLUSH_ADDR_END_2[0], sizeof(mmGARLIC_FLUSH_ADDR_END_2)/sizeof(mmGARLIC_FLUSH_ADDR_END_2[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_3", REG_MMIO, 0x1408, &mmGARLIC_FLUSH_ADDR_START_3[0], sizeof(mmGARLIC_FLUSH_ADDR_START_3)/sizeof(mmGARLIC_FLUSH_ADDR_START_3[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_3", REG_MMIO, 0x1409, &mmGARLIC_FLUSH_ADDR_END_3[0], sizeof(mmGARLIC_FLUSH_ADDR_END_3)/sizeof(mmGARLIC_FLUSH_ADDR_END_3[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_4", REG_MMIO, 0x140a, &mmGARLIC_FLUSH_ADDR_START_4[0], sizeof(mmGARLIC_FLUSH_ADDR_START_4)/sizeof(mmGARLIC_FLUSH_ADDR_START_4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_4", REG_MMIO, 0x140b, &mmGARLIC_FLUSH_ADDR_END_4[0], sizeof(mmGARLIC_FLUSH_ADDR_END_4)/sizeof(mmGARLIC_FLUSH_ADDR_END_4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_5", REG_MMIO, 0x140c, &mmGARLIC_FLUSH_ADDR_START_5[0], sizeof(mmGARLIC_FLUSH_ADDR_START_5)/sizeof(mmGARLIC_FLUSH_ADDR_START_5[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_5", REG_MMIO, 0x140d, &mmGARLIC_FLUSH_ADDR_END_5[0], sizeof(mmGARLIC_FLUSH_ADDR_END_5)/sizeof(mmGARLIC_FLUSH_ADDR_END_5[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_6", REG_MMIO, 0x140e, &mmGARLIC_FLUSH_ADDR_START_6[0], sizeof(mmGARLIC_FLUSH_ADDR_START_6)/sizeof(mmGARLIC_FLUSH_ADDR_START_6[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_6", REG_MMIO, 0x140f, &mmGARLIC_FLUSH_ADDR_END_6[0], sizeof(mmGARLIC_FLUSH_ADDR_END_6)/sizeof(mmGARLIC_FLUSH_ADDR_END_6[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_START_7", REG_MMIO, 0x1410, &mmGARLIC_FLUSH_ADDR_START_7[0], sizeof(mmGARLIC_FLUSH_ADDR_START_7)/sizeof(mmGARLIC_FLUSH_ADDR_START_7[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_RESERVED", REG_SMC, 0x1410000, &ixPSX81_BIF_PCIE_RESERVED[0], sizeof(ixPSX81_BIF_PCIE_RESERVED)/sizeof(ixPSX81_BIF_PCIE_RESERVED[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_SCRATCH", REG_SMC, 0x1410001, &ixPSX81_BIF_PCIE_SCRATCH[0], sizeof(ixPSX81_BIF_PCIE_SCRATCH)/sizeof(ixPSX81_BIF_PCIE_SCRATCH[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_HW_DEBUG", REG_SMC, 0x1410002, &ixPSX81_BIF_PCIE_HW_DEBUG[0], sizeof(ixPSX81_BIF_PCIE_HW_DEBUG)/sizeof(ixPSX81_BIF_PCIE_HW_DEBUG[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_RX_NUM_NAK", REG_SMC, 0x141000e, &ixPSX81_BIF_PCIE_RX_NUM_NAK[0], sizeof(ixPSX81_BIF_PCIE_RX_NUM_NAK)/sizeof(ixPSX81_BIF_PCIE_RX_NUM_NAK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED", REG_SMC, 0x141000f, &ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED[0], sizeof(ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED)/sizeof(ixPSX81_BIF_PCIE_RX_NUM_NAK_GENERATED[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_CNTL", REG_SMC, 0x1410010, &ixPSX81_BIF_PCIE_CNTL[0], sizeof(ixPSX81_BIF_PCIE_CNTL)/sizeof(ixPSX81_BIF_PCIE_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_CONFIG_CNTL", REG_SMC, 0x1410011, &ixPSX81_BIF_PCIE_CONFIG_CNTL[0], sizeof(ixPSX81_BIF_PCIE_CONFIG_CNTL)/sizeof(ixPSX81_BIF_PCIE_CONFIG_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_DEBUG_CNTL", REG_SMC, 0x1410012, &ixPSX81_BIF_PCIE_DEBUG_CNTL[0], sizeof(ixPSX81_BIF_PCIE_DEBUG_CNTL)/sizeof(ixPSX81_BIF_PCIE_DEBUG_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_CNTL2", REG_SMC, 0x141001c, &ixPSX81_BIF_PCIE_CNTL2[0], sizeof(ixPSX81_BIF_PCIE_CNTL2)/sizeof(ixPSX81_BIF_PCIE_CNTL2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_RX_CNTL2", REG_SMC, 0x141001d, &ixPSX81_BIF_PCIE_RX_CNTL2[0], sizeof(ixPSX81_BIF_PCIE_RX_CNTL2)/sizeof(ixPSX81_BIF_PCIE_RX_CNTL2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL", REG_SMC, 0x141001e, &ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL[0], sizeof(ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL)/sizeof(ixPSX81_BIF_PCIE_TX_F0_ATTR_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_CI_CNTL", REG_SMC, 0x1410020, &ixPSX81_BIF_PCIE_CI_CNTL[0], sizeof(ixPSX81_BIF_PCIE_CI_CNTL)/sizeof(ixPSX81_BIF_PCIE_CI_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_BUS_CNTL", REG_SMC, 0x1410021, &ixPSX81_BIF_PCIE_BUS_CNTL[0], sizeof(ixPSX81_BIF_PCIE_BUS_CNTL)/sizeof(ixPSX81_BIF_PCIE_BUS_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_STATE6", REG_SMC, 0x1410022, &ixPSX81_BIF_PCIE_LC_STATE6[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE6)/sizeof(ixPSX81_BIF_PCIE_LC_STATE6[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_STATE7", REG_SMC, 0x1410023, &ixPSX81_BIF_PCIE_LC_STATE7[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE7)/sizeof(ixPSX81_BIF_PCIE_LC_STATE7[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_STATE8", REG_SMC, 0x1410024, &ixPSX81_BIF_PCIE_LC_STATE8[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE8)/sizeof(ixPSX81_BIF_PCIE_LC_STATE8[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_STATE9", REG_SMC, 0x1410025, &ixPSX81_BIF_PCIE_LC_STATE9[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE9)/sizeof(ixPSX81_BIF_PCIE_LC_STATE9[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_STATE10", REG_SMC, 0x1410026, &ixPSX81_BIF_PCIE_LC_STATE10[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE10)/sizeof(ixPSX81_BIF_PCIE_LC_STATE10[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_STATE11", REG_SMC, 0x1410027, &ixPSX81_BIF_PCIE_LC_STATE11[0], sizeof(ixPSX81_BIF_PCIE_LC_STATE11)/sizeof(ixPSX81_BIF_PCIE_LC_STATE11[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_STATUS1", REG_SMC, 0x1410028, &ixPSX81_BIF_PCIE_LC_STATUS1[0], sizeof(ixPSX81_BIF_PCIE_LC_STATUS1)/sizeof(ixPSX81_BIF_PCIE_LC_STATUS1[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_STATUS2", REG_SMC, 0x1410029, &ixPSX81_BIF_PCIE_LC_STATUS2[0], sizeof(ixPSX81_BIF_PCIE_LC_STATUS2)/sizeof(ixPSX81_BIF_PCIE_LC_STATUS2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_WPR_CNTL", REG_SMC, 0x1410030, &ixPSX81_BIF_PCIE_WPR_CNTL[0], sizeof(ixPSX81_BIF_PCIE_WPR_CNTL)/sizeof(ixPSX81_BIF_PCIE_WPR_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_RX_LAST_TLP0", REG_SMC, 0x1410031, &ixPSX81_BIF_PCIE_RX_LAST_TLP0[0], sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP0)/sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_RX_LAST_TLP1", REG_SMC, 0x1410032, &ixPSX81_BIF_PCIE_RX_LAST_TLP1[0], sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP1)/sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_RX_LAST_TLP2", REG_SMC, 0x1410033, &ixPSX81_BIF_PCIE_RX_LAST_TLP2[0], sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP2)/sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_RX_LAST_TLP3", REG_SMC, 0x1410034, &ixPSX81_BIF_PCIE_RX_LAST_TLP3[0], sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP3)/sizeof(ixPSX81_BIF_PCIE_RX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_TX_LAST_TLP0", REG_SMC, 0x1410035, &ixPSX81_BIF_PCIE_TX_LAST_TLP0[0], sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP0)/sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP0[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_TX_LAST_TLP1", REG_SMC, 0x1410036, &ixPSX81_BIF_PCIE_TX_LAST_TLP1[0], sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP1)/sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP1[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_TX_LAST_TLP2", REG_SMC, 0x1410037, &ixPSX81_BIF_PCIE_TX_LAST_TLP2[0], sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP2)/sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_TX_LAST_TLP3", REG_SMC, 0x1410038, &ixPSX81_BIF_PCIE_TX_LAST_TLP3[0], sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP3)/sizeof(ixPSX81_BIF_PCIE_TX_LAST_TLP3[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND", REG_SMC, 0x141003a, &ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND[0], sizeof(ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND)/sizeof(ixPSX81_BIF_PCIE_I2C_REG_ADDR_EXPAND[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_I2C_REG_DATA", REG_SMC, 0x141003b, &ixPSX81_BIF_PCIE_I2C_REG_DATA[0], sizeof(ixPSX81_BIF_PCIE_I2C_REG_DATA)/sizeof(ixPSX81_BIF_PCIE_I2C_REG_DATA[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_CFG_CNTL", REG_SMC, 0x141003c, &ixPSX81_BIF_PCIE_CFG_CNTL[0], sizeof(ixPSX81_BIF_PCIE_CFG_CNTL)/sizeof(ixPSX81_BIF_PCIE_CFG_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_LC_PM_CNTL", REG_SMC, 0x141003d, &ixPSX81_BIF_PCIE_LC_PM_CNTL[0], sizeof(ixPSX81_BIF_PCIE_LC_PM_CNTL)/sizeof(ixPSX81_BIF_PCIE_LC_PM_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_P_CNTL", REG_SMC, 0x1410040, &ixPSX81_BIF_PCIE_P_CNTL[0], sizeof(ixPSX81_BIF_PCIE_P_CNTL)/sizeof(ixPSX81_BIF_PCIE_P_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_P_BUF_STATUS", REG_SMC, 0x1410041, &ixPSX81_BIF_PCIE_P_BUF_STATUS[0], sizeof(ixPSX81_BIF_PCIE_P_BUF_STATUS)/sizeof(ixPSX81_BIF_PCIE_P_BUF_STATUS[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_P_DECODER_STATUS", REG_SMC, 0x1410042, &ixPSX81_BIF_PCIE_P_DECODER_STATUS[0], sizeof(ixPSX81_BIF_PCIE_P_DECODER_STATUS)/sizeof(ixPSX81_BIF_PCIE_P_DECODER_STATUS[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_P_MISC_STATUS", REG_SMC, 0x1410043, &ixPSX81_BIF_PCIE_P_MISC_STATUS[0], sizeof(ixPSX81_BIF_PCIE_P_MISC_STATUS)/sizeof(ixPSX81_BIF_PCIE_P_MISC_STATUS[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET", REG_SMC, 0x1410050, &ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET[0], sizeof(ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET)/sizeof(ixPSX81_BIF_PCIE_P_RCV_L0S_FTS_DET[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT_CNTL", REG_SMC, 0x1410080, &ixPSX81_BIF_PCIE_PERF_COUNT_CNTL[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT_CNTL)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT_CNTL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK", REG_SMC, 0x1410081, &ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK", REG_SMC, 0x1410082, &ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK", REG_SMC, 0x1410083, &ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK", REG_SMC, 0x1410084, &ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_MST_R_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK", REG_SMC, 0x1410085, &ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_MST_R_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK", REG_SMC, 0x1410086, &ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_MST_R_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK", REG_SMC, 0x1410087, &ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_MST_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK", REG_SMC, 0x1410088, &ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_MST_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK", REG_SMC, 0x1410089, &ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_MST_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK", REG_SMC, 0x141008a, &ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK", REG_SMC, 0x141008b, &ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK", REG_SMC, 0x141008c, &ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_R_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK", REG_SMC, 0x141008d, &ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK", REG_SMC, 0x141008e, &ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK", REG_SMC, 0x141008f, &ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_S_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK", REG_SMC, 0x1410090, &ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK", REG_SMC, 0x1410091, &ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK", REG_SMC, 0x1410092, &ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_SLV_NS_C_CLK[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL", REG_SMC, 0x1410093, &ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_EVENT0_PORT_SEL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL", REG_SMC, 0x1410094, &ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_EVENT1_PORT_SEL[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2", REG_SMC, 0x1410095, &ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2[0], sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2)/sizeof(ixPSX81_BIF_PCIE_PERF_CNTL_TXCLK2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2", REG_SMC, 0x1410096, &ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT0_TXCLK2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2", REG_SMC, 0x1410097, &ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2[0], sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2)/sizeof(ixPSX81_BIF_PCIE_PERF_COUNT1_TXCLK2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_STRAP_F0", REG_SMC, 0x14100b0, &ixPSX81_BIF_PCIE_STRAP_F0[0], sizeof(ixPSX81_BIF_PCIE_STRAP_F0)/sizeof(ixPSX81_BIF_PCIE_STRAP_F0[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_STRAP_MISC", REG_SMC, 0x14100c0, &ixPSX81_BIF_PCIE_STRAP_MISC[0], sizeof(ixPSX81_BIF_PCIE_STRAP_MISC)/sizeof(ixPSX81_BIF_PCIE_STRAP_MISC[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_STRAP_MISC2", REG_SMC, 0x14100c1, &ixPSX81_BIF_PCIE_STRAP_MISC2[0], sizeof(ixPSX81_BIF_PCIE_STRAP_MISC2)/sizeof(ixPSX81_BIF_PCIE_STRAP_MISC2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_STRAP_PI", REG_SMC, 0x14100c2, &ixPSX81_BIF_PCIE_STRAP_PI[0], sizeof(ixPSX81_BIF_PCIE_STRAP_PI)/sizeof(ixPSX81_BIF_PCIE_STRAP_PI[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_STRAP_I2C_BD", REG_SMC, 0x14100c4, &ixPSX81_BIF_PCIE_STRAP_I2C_BD[0], sizeof(ixPSX81_BIF_PCIE_STRAP_I2C_BD)/sizeof(ixPSX81_BIF_PCIE_STRAP_I2C_BD[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_CLR", REG_SMC, 0x14100c8, &ixPSX81_BIF_PCIE_PRBS_CLR[0], sizeof(ixPSX81_BIF_PCIE_PRBS_CLR)/sizeof(ixPSX81_BIF_PCIE_PRBS_CLR[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_STATUS1", REG_SMC, 0x14100c9, &ixPSX81_BIF_PCIE_PRBS_STATUS1[0], sizeof(ixPSX81_BIF_PCIE_PRBS_STATUS1)/sizeof(ixPSX81_BIF_PCIE_PRBS_STATUS1[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_STATUS2", REG_SMC, 0x14100ca, &ixPSX81_BIF_PCIE_PRBS_STATUS2[0], sizeof(ixPSX81_BIF_PCIE_PRBS_STATUS2)/sizeof(ixPSX81_BIF_PCIE_PRBS_STATUS2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_FREERUN", REG_SMC, 0x14100cb, &ixPSX81_BIF_PCIE_PRBS_FREERUN[0], sizeof(ixPSX81_BIF_PCIE_PRBS_FREERUN)/sizeof(ixPSX81_BIF_PCIE_PRBS_FREERUN[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_MISC", REG_SMC, 0x14100cc, &ixPSX81_BIF_PCIE_PRBS_MISC[0], sizeof(ixPSX81_BIF_PCIE_PRBS_MISC)/sizeof(ixPSX81_BIF_PCIE_PRBS_MISC[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_USER_PATTERN", REG_SMC, 0x14100cd, &ixPSX81_BIF_PCIE_PRBS_USER_PATTERN[0], sizeof(ixPSX81_BIF_PCIE_PRBS_USER_PATTERN)/sizeof(ixPSX81_BIF_PCIE_PRBS_USER_PATTERN[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_LO_BITCNT", REG_SMC, 0x14100ce, &ixPSX81_BIF_PCIE_PRBS_LO_BITCNT[0], sizeof(ixPSX81_BIF_PCIE_PRBS_LO_BITCNT)/sizeof(ixPSX81_BIF_PCIE_PRBS_LO_BITCNT[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_HI_BITCNT", REG_SMC, 0x14100cf, &ixPSX81_BIF_PCIE_PRBS_HI_BITCNT[0], sizeof(ixPSX81_BIF_PCIE_PRBS_HI_BITCNT)/sizeof(ixPSX81_BIF_PCIE_PRBS_HI_BITCNT[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_0", REG_SMC, 0x14100d0, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_0[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_0)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_0[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_1", REG_SMC, 0x14100d1, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_1[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_1)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_1[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_2", REG_SMC, 0x14100d2, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_2[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_2)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_2[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_3", REG_SMC, 0x14100d3, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_3[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_3)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_3[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_4", REG_SMC, 0x14100d4, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_4[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_4)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_4[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_5", REG_SMC, 0x14100d5, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_5[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_5)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_5[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_6", REG_SMC, 0x14100d6, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_6[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_6)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_6[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_7", REG_SMC, 0x14100d7, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_7[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_7)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_7[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_8", REG_SMC, 0x14100d8, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_8[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_8)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_8[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_9", REG_SMC, 0x14100d9, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_9[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_9)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_9[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_10", REG_SMC, 0x14100da, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_10[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_10)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_10[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_11", REG_SMC, 0x14100db, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_11[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_11)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_11[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_12", REG_SMC, 0x14100dc, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_12[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_12)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_12[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_13", REG_SMC, 0x14100dd, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_13[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_13)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_13[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_14", REG_SMC, 0x14100de, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_14[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_14)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_14[0]), 0, 0 },
+	{ "ixPSX81_BIF_PCIE_PRBS_ERRCNT_15", REG_SMC, 0x14100df, &ixPSX81_BIF_PCIE_PRBS_ERRCNT_15[0], sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_15)/sizeof(ixPSX81_BIF_PCIE_PRBS_ERRCNT_15[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_COMMAND_STATUS", REG_SMC, 0x1410100, &ixPSX81_BIF_SWRST_COMMAND_STATUS[0], sizeof(ixPSX81_BIF_SWRST_COMMAND_STATUS)/sizeof(ixPSX81_BIF_SWRST_COMMAND_STATUS[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_GENERAL_CONTROL", REG_SMC, 0x1410101, &ixPSX81_BIF_SWRST_GENERAL_CONTROL[0], sizeof(ixPSX81_BIF_SWRST_GENERAL_CONTROL)/sizeof(ixPSX81_BIF_SWRST_GENERAL_CONTROL[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_COMMAND_0", REG_SMC, 0x1410102, &ixPSX81_BIF_SWRST_COMMAND_0[0], sizeof(ixPSX81_BIF_SWRST_COMMAND_0)/sizeof(ixPSX81_BIF_SWRST_COMMAND_0[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_COMMAND_1", REG_SMC, 0x1410103, &ixPSX81_BIF_SWRST_COMMAND_1[0], sizeof(ixPSX81_BIF_SWRST_COMMAND_1)/sizeof(ixPSX81_BIF_SWRST_COMMAND_1[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_CONTROL_0", REG_SMC, 0x1410104, &ixPSX81_BIF_SWRST_CONTROL_0[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_0)/sizeof(ixPSX81_BIF_SWRST_CONTROL_0[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_CONTROL_1", REG_SMC, 0x1410105, &ixPSX81_BIF_SWRST_CONTROL_1[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_1)/sizeof(ixPSX81_BIF_SWRST_CONTROL_1[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_CONTROL_2", REG_SMC, 0x1410106, &ixPSX81_BIF_SWRST_CONTROL_2[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_2)/sizeof(ixPSX81_BIF_SWRST_CONTROL_2[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_CONTROL_3", REG_SMC, 0x1410107, &ixPSX81_BIF_SWRST_CONTROL_3[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_3)/sizeof(ixPSX81_BIF_SWRST_CONTROL_3[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_CONTROL_4", REG_SMC, 0x1410108, &ixPSX81_BIF_SWRST_CONTROL_4[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_4)/sizeof(ixPSX81_BIF_SWRST_CONTROL_4[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_CONTROL_5", REG_SMC, 0x1410109, &ixPSX81_BIF_SWRST_CONTROL_5[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_5)/sizeof(ixPSX81_BIF_SWRST_CONTROL_5[0]), 0, 0 },
+	{ "ixPSX81_BIF_SWRST_CONTROL_6", REG_SMC, 0x141010a, &ixPSX81_BIF_SWRST_CONTROL_6[0], sizeof(ixPSX81_BIF_SWRST_CONTROL_6)/sizeof(ixPSX81_BIF_SWRST_CONTROL_6[0]), 0, 0 },
+	{ "ixPSX81_BIF_CPM_CONTROL", REG_SMC, 0x1410118, &ixPSX81_BIF_CPM_CONTROL[0], sizeof(ixPSX81_BIF_CPM_CONTROL)/sizeof(ixPSX81_BIF_CPM_CONTROL[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_CONTROL", REG_SMC, 0x1410120, &ixPSX81_BIF_LM_CONTROL[0], sizeof(ixPSX81_BIF_LM_CONTROL)/sizeof(ixPSX81_BIF_LM_CONTROL[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PCIETXMUX0", REG_SMC, 0x1410121, &ixPSX81_BIF_LM_PCIETXMUX0[0], sizeof(ixPSX81_BIF_LM_PCIETXMUX0)/sizeof(ixPSX81_BIF_LM_PCIETXMUX0[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PCIETXMUX1", REG_SMC, 0x1410122, &ixPSX81_BIF_LM_PCIETXMUX1[0], sizeof(ixPSX81_BIF_LM_PCIETXMUX1)/sizeof(ixPSX81_BIF_LM_PCIETXMUX1[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PCIETXMUX2", REG_SMC, 0x1410123, &ixPSX81_BIF_LM_PCIETXMUX2[0], sizeof(ixPSX81_BIF_LM_PCIETXMUX2)/sizeof(ixPSX81_BIF_LM_PCIETXMUX2[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PCIETXMUX3", REG_SMC, 0x1410124, &ixPSX81_BIF_LM_PCIETXMUX3[0], sizeof(ixPSX81_BIF_LM_PCIETXMUX3)/sizeof(ixPSX81_BIF_LM_PCIETXMUX3[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PCIERXMUX0", REG_SMC, 0x1410125, &ixPSX81_BIF_LM_PCIERXMUX0[0], sizeof(ixPSX81_BIF_LM_PCIERXMUX0)/sizeof(ixPSX81_BIF_LM_PCIERXMUX0[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PCIERXMUX1", REG_SMC, 0x1410126, &ixPSX81_BIF_LM_PCIERXMUX1[0], sizeof(ixPSX81_BIF_LM_PCIERXMUX1)/sizeof(ixPSX81_BIF_LM_PCIERXMUX1[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PCIERXMUX2", REG_SMC, 0x1410127, &ixPSX81_BIF_LM_PCIERXMUX2[0], sizeof(ixPSX81_BIF_LM_PCIERXMUX2)/sizeof(ixPSX81_BIF_LM_PCIERXMUX2[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PCIERXMUX3", REG_SMC, 0x1410128, &ixPSX81_BIF_LM_PCIERXMUX3[0], sizeof(ixPSX81_BIF_LM_PCIERXMUX3)/sizeof(ixPSX81_BIF_LM_PCIERXMUX3[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_LANEENABLE", REG_SMC, 0x1410129, &ixPSX81_BIF_LM_LANEENABLE[0], sizeof(ixPSX81_BIF_LM_LANEENABLE)/sizeof(ixPSX81_BIF_LM_LANEENABLE[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_PRBSCONTROL", REG_SMC, 0x141012a, &ixPSX81_BIF_LM_PRBSCONTROL[0], sizeof(ixPSX81_BIF_LM_PRBSCONTROL)/sizeof(ixPSX81_BIF_LM_PRBSCONTROL[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_POWERCONTROL", REG_SMC, 0x141012b, &ixPSX81_BIF_LM_POWERCONTROL[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL)/sizeof(ixPSX81_BIF_LM_POWERCONTROL[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_POWERCONTROL1", REG_SMC, 0x141012c, &ixPSX81_BIF_LM_POWERCONTROL1[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL1)/sizeof(ixPSX81_BIF_LM_POWERCONTROL1[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_POWERCONTROL2", REG_SMC, 0x141012d, &ixPSX81_BIF_LM_POWERCONTROL2[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL2)/sizeof(ixPSX81_BIF_LM_POWERCONTROL2[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_POWERCONTROL3", REG_SMC, 0x141012e, &ixPSX81_BIF_LM_POWERCONTROL3[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL3)/sizeof(ixPSX81_BIF_LM_POWERCONTROL3[0]), 0, 0 },
+	{ "ixPSX81_BIF_LM_POWERCONTROL4", REG_SMC, 0x141012f, &ixPSX81_BIF_LM_POWERCONTROL4[0], sizeof(ixPSX81_BIF_LM_POWERCONTROL4)/sizeof(ixPSX81_BIF_LM_POWERCONTROL4[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_ADDR_END_7", REG_MMIO, 0x1411, &mmGARLIC_FLUSH_ADDR_END_7[0], sizeof(mmGARLIC_FLUSH_ADDR_END_7)/sizeof(mmGARLIC_FLUSH_ADDR_END_7[0]), 0, 0 },
+	{ "mmGARLIC_FLUSH_REQ", REG_MMIO, 0x1412, &mmGARLIC_FLUSH_REQ[0], sizeof(mmGARLIC_FLUSH_REQ)/sizeof(mmGARLIC_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_GARLIC_FLUSH_REQ", REG_MMIO, 0x1413, &mmGPU_GARLIC_FLUSH_REQ[0], sizeof(mmGPU_GARLIC_FLUSH_REQ)/sizeof(mmGPU_GARLIC_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_GARLIC_FLUSH_DONE", REG_MMIO, 0x1414, &mmGPU_GARLIC_FLUSH_DONE[0], sizeof(mmGPU_GARLIC_FLUSH_DONE)/sizeof(mmGPU_GARLIC_FLUSH_DONE[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_RB0_WPTR", REG_MMIO, 0x1415, &mmGARLIC_COHE_CP_RB0_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB0_WPTR)/sizeof(mmGARLIC_COHE_CP_RB0_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_RB1_WPTR", REG_MMIO, 0x1416, &mmGARLIC_COHE_CP_RB1_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB1_WPTR)/sizeof(mmGARLIC_COHE_CP_RB1_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_RB2_WPTR", REG_MMIO, 0x1417, &mmGARLIC_COHE_CP_RB2_WPTR[0], sizeof(mmGARLIC_COHE_CP_RB2_WPTR)/sizeof(mmGARLIC_COHE_CP_RB2_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_UVD_RBC_RB_WPTR", REG_MMIO, 0x1418, &mmGARLIC_COHE_UVD_RBC_RB_WPTR[0], sizeof(mmGARLIC_COHE_UVD_RBC_RB_WPTR)/sizeof(mmGARLIC_COHE_UVD_RBC_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SDMA0_GFX_RB_WPTR", REG_MMIO, 0x1419, &mmGARLIC_COHE_SDMA0_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA0_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA0_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SDMA1_GFX_RB_WPTR", REG_MMIO, 0x141a, &mmGARLIC_COHE_SDMA1_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA1_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA1_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_DMA_ME_COMMAND", REG_MMIO, 0x141b, &mmGARLIC_COHE_CP_DMA_ME_COMMAND[0], sizeof(mmGARLIC_COHE_CP_DMA_ME_COMMAND)/sizeof(mmGARLIC_COHE_CP_DMA_ME_COMMAND[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_DMA_PFP_COMMAND", REG_MMIO, 0x141c, &mmGARLIC_COHE_CP_DMA_PFP_COMMAND[0], sizeof(mmGARLIC_COHE_CP_DMA_PFP_COMMAND)/sizeof(mmGARLIC_COHE_CP_DMA_PFP_COMMAND[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SAM_SAB_RBI_WPTR", REG_MMIO, 0x141d, &mmGARLIC_COHE_SAM_SAB_RBI_WPTR[0], sizeof(mmGARLIC_COHE_SAM_SAB_RBI_WPTR)/sizeof(mmGARLIC_COHE_SAM_SAB_RBI_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SAM_SAB_RBO_WPTR", REG_MMIO, 0x141e, &mmGARLIC_COHE_SAM_SAB_RBO_WPTR[0], sizeof(mmGARLIC_COHE_SAM_SAB_RBO_WPTR)/sizeof(mmGARLIC_COHE_SAM_SAB_RBO_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_VCE_OUT_RB_WPTR", REG_MMIO, 0x141f, &mmGARLIC_COHE_VCE_OUT_RB_WPTR[0], sizeof(mmGARLIC_COHE_VCE_OUT_RB_WPTR)/sizeof(mmGARLIC_COHE_VCE_OUT_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_VCE_RB_WPTR2", REG_MMIO, 0x1420, &mmGARLIC_COHE_VCE_RB_WPTR2[0], sizeof(mmGARLIC_COHE_VCE_RB_WPTR2)/sizeof(mmGARLIC_COHE_VCE_RB_WPTR2[0]), 0, 0 },
+	{ "mmGARLIC_COHE_VCE_RB_WPTR", REG_MMIO, 0x1421, &mmGARLIC_COHE_VCE_RB_WPTR[0], sizeof(mmGARLIC_COHE_VCE_RB_WPTR)/sizeof(mmGARLIC_COHE_VCE_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SDMA2_GFX_RB_WPTR", REG_MMIO, 0x1422, &mmGARLIC_COHE_SDMA2_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA2_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA2_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_SDMA3_GFX_RB_WPTR", REG_MMIO, 0x1423, &mmGARLIC_COHE_SDMA3_GFX_RB_WPTR[0], sizeof(mmGARLIC_COHE_SDMA3_GFX_RB_WPTR)/sizeof(mmGARLIC_COHE_SDMA3_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmGARLIC_COHE_CP_DMA_PIO_COMMAND", REG_MMIO, 0x1424, &mmGARLIC_COHE_CP_DMA_PIO_COMMAND[0], sizeof(mmGARLIC_COHE_CP_DMA_PIO_COMMAND)/sizeof(mmGARLIC_COHE_CP_DMA_PIO_COMMAND[0]), 0, 0 },
+	{ "mmGARLIC_COHE_GARLIC_FLUSH_REQ", REG_MMIO, 0x1425, &mmGARLIC_COHE_GARLIC_FLUSH_REQ[0], sizeof(mmGARLIC_COHE_GARLIC_FLUSH_REQ)/sizeof(mmGARLIC_COHE_GARLIC_FLUSH_REQ[0]), 0, 0 },
+	{ "mmREMAP_HDP_MEM_FLUSH_CNTL", REG_MMIO, 0x1426, &mmREMAP_HDP_MEM_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL)/sizeof(mmREMAP_HDP_MEM_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmREMAP_HDP_REG_FLUSH_CNTL", REG_MMIO, 0x1427, &mmREMAP_HDP_REG_FLUSH_CNTL[0], sizeof(mmREMAP_HDP_REG_FLUSH_CNTL)/sizeof(mmREMAP_HDP_REG_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX0_LOWER", REG_MMIO, 0x1428, &mmBIF_VDDGFX_GFX0_LOWER[0], sizeof(mmBIF_VDDGFX_GFX0_LOWER)/sizeof(mmBIF_VDDGFX_GFX0_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX0_UPPER", REG_MMIO, 0x1429, &mmBIF_VDDGFX_GFX0_UPPER[0], sizeof(mmBIF_VDDGFX_GFX0_UPPER)/sizeof(mmBIF_VDDGFX_GFX0_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX1_LOWER", REG_MMIO, 0x142a, &mmBIF_VDDGFX_GFX1_LOWER[0], sizeof(mmBIF_VDDGFX_GFX1_LOWER)/sizeof(mmBIF_VDDGFX_GFX1_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX1_UPPER", REG_MMIO, 0x142b, &mmBIF_VDDGFX_GFX1_UPPER[0], sizeof(mmBIF_VDDGFX_GFX1_UPPER)/sizeof(mmBIF_VDDGFX_GFX1_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX2_LOWER", REG_MMIO, 0x142c, &mmBIF_VDDGFX_GFX2_LOWER[0], sizeof(mmBIF_VDDGFX_GFX2_LOWER)/sizeof(mmBIF_VDDGFX_GFX2_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX2_UPPER", REG_MMIO, 0x142d, &mmBIF_VDDGFX_GFX2_UPPER[0], sizeof(mmBIF_VDDGFX_GFX2_UPPER)/sizeof(mmBIF_VDDGFX_GFX2_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX3_LOWER", REG_MMIO, 0x142e, &mmBIF_VDDGFX_GFX3_LOWER[0], sizeof(mmBIF_VDDGFX_GFX3_LOWER)/sizeof(mmBIF_VDDGFX_GFX3_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX3_UPPER", REG_MMIO, 0x142f, &mmBIF_VDDGFX_GFX3_UPPER[0], sizeof(mmBIF_VDDGFX_GFX3_UPPER)/sizeof(mmBIF_VDDGFX_GFX3_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX4_LOWER", REG_MMIO, 0x1430, &mmBIF_VDDGFX_GFX4_LOWER[0], sizeof(mmBIF_VDDGFX_GFX4_LOWER)/sizeof(mmBIF_VDDGFX_GFX4_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX4_UPPER", REG_MMIO, 0x1431, &mmBIF_VDDGFX_GFX4_UPPER[0], sizeof(mmBIF_VDDGFX_GFX4_UPPER)/sizeof(mmBIF_VDDGFX_GFX4_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX5_LOWER", REG_MMIO, 0x1432, &mmBIF_VDDGFX_GFX5_LOWER[0], sizeof(mmBIF_VDDGFX_GFX5_LOWER)/sizeof(mmBIF_VDDGFX_GFX5_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_GFX5_UPPER", REG_MMIO, 0x1433, &mmBIF_VDDGFX_GFX5_UPPER[0], sizeof(mmBIF_VDDGFX_GFX5_UPPER)/sizeof(mmBIF_VDDGFX_GFX5_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV1_LOWER", REG_MMIO, 0x1434, &mmBIF_VDDGFX_RSV1_LOWER[0], sizeof(mmBIF_VDDGFX_RSV1_LOWER)/sizeof(mmBIF_VDDGFX_RSV1_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV1_UPPER", REG_MMIO, 0x1435, &mmBIF_VDDGFX_RSV1_UPPER[0], sizeof(mmBIF_VDDGFX_RSV1_UPPER)/sizeof(mmBIF_VDDGFX_RSV1_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV2_LOWER", REG_MMIO, 0x1436, &mmBIF_VDDGFX_RSV2_LOWER[0], sizeof(mmBIF_VDDGFX_RSV2_LOWER)/sizeof(mmBIF_VDDGFX_RSV2_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV2_UPPER", REG_MMIO, 0x1437, &mmBIF_VDDGFX_RSV2_UPPER[0], sizeof(mmBIF_VDDGFX_RSV2_UPPER)/sizeof(mmBIF_VDDGFX_RSV2_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV3_LOWER", REG_MMIO, 0x1438, &mmBIF_VDDGFX_RSV3_LOWER[0], sizeof(mmBIF_VDDGFX_RSV3_LOWER)/sizeof(mmBIF_VDDGFX_RSV3_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV3_UPPER", REG_MMIO, 0x1439, &mmBIF_VDDGFX_RSV3_UPPER[0], sizeof(mmBIF_VDDGFX_RSV3_UPPER)/sizeof(mmBIF_VDDGFX_RSV3_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV4_LOWER", REG_MMIO, 0x143a, &mmBIF_VDDGFX_RSV4_LOWER[0], sizeof(mmBIF_VDDGFX_RSV4_LOWER)/sizeof(mmBIF_VDDGFX_RSV4_LOWER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_RSV4_UPPER", REG_MMIO, 0x143b, &mmBIF_VDDGFX_RSV4_UPPER[0], sizeof(mmBIF_VDDGFX_RSV4_UPPER)/sizeof(mmBIF_VDDGFX_RSV4_UPPER[0]), 0, 0 },
+	{ "mmBIF_VDDGFX_FB_CMP", REG_MMIO, 0x143c, &mmBIF_VDDGFX_FB_CMP[0], sizeof(mmBIF_VDDGFX_FB_CMP)/sizeof(mmBIF_VDDGFX_FB_CMP[0]), 0, 0 },
+	{ "mmBIF_SMU_INDEX", REG_MMIO, 0x143d, &mmBIF_SMU_INDEX[0], sizeof(mmBIF_SMU_INDEX)/sizeof(mmBIF_SMU_INDEX[0]), 0, 0 },
+	{ "mmBIF_SMU_DATA", REG_MMIO, 0x143e, &mmBIF_SMU_DATA[0], sizeof(mmBIF_SMU_DATA)/sizeof(mmBIF_SMU_DATA[0]), 0, 0 },
+	{ "mmBIF_RFE_SOFTRST_CNTL", REG_MMIO, 0x1441, &mmBIF_RFE_SOFTRST_CNTL[0], sizeof(mmBIF_RFE_SOFTRST_CNTL)/sizeof(mmBIF_RFE_SOFTRST_CNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_CLIENT_SOFTRST_TRIGGER", REG_MMIO, 0x1442, &mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[0], sizeof(mmBIF_RFE_CLIENT_SOFTRST_TRIGGER)/sizeof(mmBIF_RFE_CLIENT_SOFTRST_TRIGGER[0]), 0, 0 },
+	{ "mmBIF_RFE_MASTER_SOFTRST_TRIGGER", REG_MMIO, 0x1443, &mmBIF_RFE_MASTER_SOFTRST_TRIGGER[0], sizeof(mmBIF_RFE_MASTER_SOFTRST_TRIGGER)/sizeof(mmBIF_RFE_MASTER_SOFTRST_TRIGGER[0]), 0, 0 },
+	{ "mmBIF_PWDN_COMMAND", REG_MMIO, 0x1444, &mmBIF_PWDN_COMMAND[0], sizeof(mmBIF_PWDN_COMMAND)/sizeof(mmBIF_PWDN_COMMAND[0]), 0, 0 },
+	{ "mmBIF_PWDN_STATUS", REG_MMIO, 0x1445, &mmBIF_PWDN_STATUS[0], sizeof(mmBIF_PWDN_STATUS)/sizeof(mmBIF_PWDN_STATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_FBU_CMDSTATUS", REG_MMIO, 0x1446, &mmBIF_RFE_MST_FBU_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_FBU_CMDSTATUS)/sizeof(mmBIF_RFE_MST_FBU_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS", REG_MMIO, 0x1447, &mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS)/sizeof(mmBIF_RFE_MST_RWREG_RFEWGBIF_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_BX_CMDSTATUS", REG_MMIO, 0x1448, &mmBIF_RFE_MST_BX_CMDSTATUS[0], sizeof(mmBIF_RFE_MST_BX_CMDSTATUS)/sizeof(mmBIF_RFE_MST_BX_CMDSTATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MST_TMOUT_STATUS", REG_MMIO, 0x144b, &mmBIF_RFE_MST_TMOUT_STATUS[0], sizeof(mmBIF_RFE_MST_TMOUT_STATUS)/sizeof(mmBIF_RFE_MST_TMOUT_STATUS[0]), 0, 0 },
+	{ "mmBIF_RFE_MMCFG_CNTL", REG_MMIO, 0x144c, &mmBIF_RFE_MMCFG_CNTL[0], sizeof(mmBIF_RFE_MMCFG_CNTL)/sizeof(mmBIF_RFE_MMCFG_CNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_WARMRST_CNTL", REG_MMIO, 0x1459, &mmBIF_RFE_WARMRST_CNTL[0], sizeof(mmBIF_RFE_WARMRST_CNTL)/sizeof(mmBIF_RFE_WARMRST_CNTL[0]), 0, 0 },
+	{ "mmBIF_BACO_MSIC", REG_MMIO, 0x1480, &mmBIF_BACO_MSIC[0], sizeof(mmBIF_BACO_MSIC)/sizeof(mmBIF_BACO_MSIC[0]), 0, 0 },
+	{ "mmBIF_PIF_TXCLK_SWITCH_TIMER", REG_MMIO, 0x1481, &mmBIF_PIF_TXCLK_SWITCH_TIMER[0], sizeof(mmBIF_PIF_TXCLK_SWITCH_TIMER)/sizeof(mmBIF_PIF_TXCLK_SWITCH_TIMER[0]), 0, 0 },
+	{ "mmBIF_RESET_EN", REG_MMIO, 0x1482, &mmBIF_RESET_EN[0], sizeof(mmBIF_RESET_EN)/sizeof(mmBIF_RESET_EN[0]), 0, 0 },
+	{ "mmBIF_CLK_PDWN_DELAY_TIMER", REG_MMIO, 0x1483, &mmBIF_CLK_PDWN_DELAY_TIMER[0], sizeof(mmBIF_CLK_PDWN_DELAY_TIMER)/sizeof(mmBIF_CLK_PDWN_DELAY_TIMER[0]), 0, 0 },
+	{ "mmNEW_REFCLKB_TIMER_1", REG_MMIO, 0x1484, &mmNEW_REFCLKB_TIMER_1[0], sizeof(mmNEW_REFCLKB_TIMER_1)/sizeof(mmNEW_REFCLKB_TIMER_1[0]), 0, 0 },
+	{ "mmNEW_REFCLKB_TIMER", REG_MMIO, 0x1485, &mmNEW_REFCLKB_TIMER[0], sizeof(mmNEW_REFCLKB_TIMER)/sizeof(mmNEW_REFCLKB_TIMER[0]), 0, 0 },
+	{ "mmBIF_RESET_CNTL", REG_MMIO, 0x1486, &mmBIF_RESET_CNTL[0], sizeof(mmBIF_RESET_CNTL)/sizeof(mmBIF_RESET_CNTL[0]), 0, 0 },
+	{ "mmLNCNT_CONTROL", REG_MMIO, 0x1487, &mmLNCNT_CONTROL[0], sizeof(mmLNCNT_CONTROL)/sizeof(mmLNCNT_CONTROL[0]), 0, 0 },
+	{ "mmBIF_LNCNT_RESET", REG_MMIO, 0x1488, &mmBIF_LNCNT_RESET[0], sizeof(mmBIF_LNCNT_RESET)/sizeof(mmBIF_LNCNT_RESET[0]), 0, 0 },
+	{ "mmBIF_CLOCKS_BITS", REG_MMIO, 0x1489, &mmBIF_CLOCKS_BITS[0], sizeof(mmBIF_CLOCKS_BITS)/sizeof(mmBIF_CLOCKS_BITS[0]), 0, 0 },
+	{ "mmBIF_MEM_PG_CNTL", REG_MMIO, 0x148a, &mmBIF_MEM_PG_CNTL[0], sizeof(mmBIF_MEM_PG_CNTL)/sizeof(mmBIF_MEM_PG_CNTL[0]), 0, 0 },
+	{ "mmBIF_RFE_CNTL_MISC", REG_MMIO, 0x148c, &mmBIF_RFE_CNTL_MISC[0], sizeof(mmBIF_RFE_CNTL_MISC)/sizeof(mmBIF_RFE_CNTL_MISC[0]), 0, 0 },
+	{ "mmBIF_XDMA_LO", REG_MMIO, 0x14c0, &mmBIF_XDMA_LO[0], sizeof(mmBIF_XDMA_LO)/sizeof(mmBIF_XDMA_LO[0]), 0, 0 },
+	{ "mmBIF_XDMA_HI", REG_MMIO, 0x14c1, &mmBIF_XDMA_HI[0], sizeof(mmBIF_XDMA_HI)/sizeof(mmBIF_XDMA_HI[0]), 0, 0 },
+	{ "mmBIF_FEATURES_CONTROL_MISC", REG_MMIO, 0x14c2, &mmBIF_FEATURES_CONTROL_MISC[0], sizeof(mmBIF_FEATURES_CONTROL_MISC)/sizeof(mmBIF_FEATURES_CONTROL_MISC[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_CNTL", REG_MMIO, 0x14c3, &mmBIF_DOORBELL_CNTL[0], sizeof(mmBIF_DOORBELL_CNTL)/sizeof(mmBIF_DOORBELL_CNTL[0]), 0, 0 },
+	{ "mmBIF_SLVARB_MODE", REG_MMIO, 0x14c4, &mmBIF_SLVARB_MODE[0], sizeof(mmBIF_SLVARB_MODE)/sizeof(mmBIF_SLVARB_MODE[0]), 0, 0 },
+	{ "mmSMBUS_BACO_DUMMY", REG_MMIO, 0x14c6, &mmSMBUS_BACO_DUMMY[0], sizeof(mmSMBUS_BACO_DUMMY)/sizeof(mmSMBUS_BACO_DUMMY[0]), 0, 0 },
+	{ "mmBF_ANA_ISO_CNTL", REG_MMIO, 0x14c7, &mmBF_ANA_ISO_CNTL[0], sizeof(mmBF_ANA_ISO_CNTL)/sizeof(mmBF_ANA_ISO_CNTL[0]), 0, 0 },
+	{ "mmBACO_CNTL_MISC", REG_MMIO, 0x14db, &mmBACO_CNTL_MISC[0], sizeof(mmBACO_CNTL_MISC)/sizeof(mmBACO_CNTL_MISC[0]), 0, 0 },
+	{ "mmBIF_BACO_DEBUG_LATCH", REG_MMIO, 0x14dc, &mmBIF_BACO_DEBUG_LATCH[0], sizeof(mmBIF_BACO_DEBUG_LATCH)/sizeof(mmBIF_BACO_DEBUG_LATCH[0]), 0, 0 },
+	{ "mmBIF_BACO_DEBUG", REG_MMIO, 0x14df, &mmBIF_BACO_DEBUG[0], sizeof(mmBIF_BACO_DEBUG)/sizeof(mmBIF_BACO_DEBUG[0]), 0, 0 },
+	{ "mmMEM_TYPE_CNTL", REG_MMIO, 0x14e4, &mmMEM_TYPE_CNTL[0], sizeof(mmMEM_TYPE_CNTL)/sizeof(mmMEM_TYPE_CNTL[0]), 0, 0 },
+	{ "mmBACO_CNTL", REG_MMIO, 0x14e5, &mmBACO_CNTL[0], sizeof(mmBACO_CNTL)/sizeof(mmBACO_CNTL[0]), 0, 0 },
+	{ "mmBIF_DEVFUNCNUM_LIST1", REG_MMIO, 0x14e7, &mmBIF_DEVFUNCNUM_LIST1[0], sizeof(mmBIF_DEVFUNCNUM_LIST1)/sizeof(mmBIF_DEVFUNCNUM_LIST1[0]), 0, 0 },
+	{ "mmBIF_DEVFUNCNUM_LIST0", REG_MMIO, 0x14e8, &mmBIF_DEVFUNCNUM_LIST0[0], sizeof(mmBIF_DEVFUNCNUM_LIST0)/sizeof(mmBIF_DEVFUNCNUM_LIST0[0]), 0, 0 },
+	{ "mmDBG_BYPASS_SRBM_ACCESS", REG_MMIO, 0x14eb, &mmDBG_BYPASS_SRBM_ACCESS[0], sizeof(mmDBG_BYPASS_SRBM_ACCESS)/sizeof(mmDBG_BYPASS_SRBM_ACCESS[0]), 0, 0 },
+	{ "mmPEER3_FB_OFFSET_LO", REG_MMIO, 0x14ec, &mmPEER3_FB_OFFSET_LO[0], sizeof(mmPEER3_FB_OFFSET_LO)/sizeof(mmPEER3_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER3_FB_OFFSET_HI", REG_MMIO, 0x14ed, &mmPEER3_FB_OFFSET_HI[0], sizeof(mmPEER3_FB_OFFSET_HI)/sizeof(mmPEER3_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER2_FB_OFFSET_LO", REG_MMIO, 0x14ee, &mmPEER2_FB_OFFSET_LO[0], sizeof(mmPEER2_FB_OFFSET_LO)/sizeof(mmPEER2_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER2_FB_OFFSET_HI", REG_MMIO, 0x14ef, &mmPEER2_FB_OFFSET_HI[0], sizeof(mmPEER2_FB_OFFSET_HI)/sizeof(mmPEER2_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER1_FB_OFFSET_LO", REG_MMIO, 0x14f0, &mmPEER1_FB_OFFSET_LO[0], sizeof(mmPEER1_FB_OFFSET_LO)/sizeof(mmPEER1_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER1_FB_OFFSET_HI", REG_MMIO, 0x14f1, &mmPEER1_FB_OFFSET_HI[0], sizeof(mmPEER1_FB_OFFSET_HI)/sizeof(mmPEER1_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmPEER0_FB_OFFSET_LO", REG_MMIO, 0x14f2, &mmPEER0_FB_OFFSET_LO[0], sizeof(mmPEER0_FB_OFFSET_LO)/sizeof(mmPEER0_FB_OFFSET_LO[0]), 0, 0 },
+	{ "mmPEER0_FB_OFFSET_HI", REG_MMIO, 0x14f3, &mmPEER0_FB_OFFSET_HI[0], sizeof(mmPEER0_FB_OFFSET_HI)/sizeof(mmPEER0_FB_OFFSET_HI[0]), 0, 0 },
+	{ "mmIMPCTL_RESET", REG_MMIO, 0x14f5, &mmIMPCTL_RESET[0], sizeof(mmIMPCTL_RESET)/sizeof(mmIMPCTL_RESET[0]), 0, 0 },
+	{ "mmSMU_BIF_VDDGFX_PWR_STATUS", REG_MMIO, 0x14f8, &mmSMU_BIF_VDDGFX_PWR_STATUS[0], sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS)/sizeof(mmSMU_BIF_VDDGFX_PWR_STATUS[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_GBLAPER1_LOWER", REG_MMIO, 0x14fc, &mmBIF_DOORBELL_GBLAPER1_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER1_LOWER[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_GBLAPER1_UPPER", REG_MMIO, 0x14fd, &mmBIF_DOORBELL_GBLAPER1_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER1_UPPER[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_GBLAPER2_LOWER", REG_MMIO, 0x14fe, &mmBIF_DOORBELL_GBLAPER2_LOWER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER)/sizeof(mmBIF_DOORBELL_GBLAPER2_LOWER[0]), 0, 0 },
+	{ "mmBIF_DOORBELL_GBLAPER2_UPPER", REG_MMIO, 0x14ff, &mmBIF_DOORBELL_GBLAPER2_UPPER[0], sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER)/sizeof(mmBIF_DOORBELL_GBLAPER2_UPPER[0]), 0, 0 },
+	{ "mmPMI_STATUS_CNTL", REG_MMIO, 0x15, &mmPMI_STATUS_CNTL[0], sizeof(mmPMI_STATUS_CNTL)/sizeof(mmPMI_STATUS_CNTL[0]), 0, 0 },
+	{ "mmBIF_MM_INDACCESS_CNTL", REG_MMIO, 0x1500, &mmBIF_MM_INDACCESS_CNTL[0], sizeof(mmBIF_MM_INDACCESS_CNTL)/sizeof(mmBIF_MM_INDACCESS_CNTL[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1", REG_SMC, 0x1500000, &ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1[0], sizeof(ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1)/sizeof(ixPSX80_WRP_BIF_STRAP_FEATURE_EN_1[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_PI_CNTL", REG_SMC, 0x1500001, &ixPSX80_WRP_BIF_STRAP_PI_CNTL[0], sizeof(ixPSX80_WRP_BIF_STRAP_PI_CNTL)/sizeof(ixPSX80_WRP_BIF_STRAP_PI_CNTL[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE", REG_SMC, 0x1500002, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_CORE[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE", REG_SMC, 0x1500003, &ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_CORE[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE", REG_SMC, 0x1500004, &ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE[0], sizeof(ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE)/sizeof(ixPSX80_WRP_BIF_STRAP_ERROR_IGNORE[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_TEST_DFT", REG_SMC, 0x1500005, &ixPSX80_WRP_BIF_STRAP_TEST_DFT[0], sizeof(ixPSX80_WRP_BIF_STRAP_TEST_DFT)/sizeof(ixPSX80_WRP_BIF_STRAP_TEST_DFT[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_ID", REG_SMC, 0x1500006, NULL, 0, 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_REV_ID", REG_SMC, 0x1500007, NULL, 0, 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_I2C_CNTL", REG_SMC, 0x1500008, NULL, 0, 0, 0 },
+	{ "ixPSX80_WRP_BIF_INT_CNTL", REG_SMC, 0x1500009, &ixPSX80_WRP_BIF_INT_CNTL[0], sizeof(ixPSX80_WRP_BIF_INT_CNTL)/sizeof(ixPSX80_WRP_BIF_INT_CNTL[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_ACS", REG_SMC, 0x150000a, &ixPSX80_WRP_BIF_STRAP_ACS[0], sizeof(ixPSX80_WRP_BIF_STRAP_ACS)/sizeof(ixPSX80_WRP_BIF_STRAP_ACS[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_PM", REG_SMC, 0x150000b, NULL, 0, 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2", REG_SMC, 0x150000c, &ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2[0], sizeof(ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2)/sizeof(ixPSX80_WRP_BIF_STRAP_FEATURE_EN_2[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_SERIAL_NUM", REG_SMC, 0x1500045, NULL, 0, 0, 0 },
+	{ "ixPSX80_WRP_BIF_SSID", REG_SMC, 0x1500046, &ixPSX80_WRP_BIF_SSID[0], sizeof(ixPSX80_WRP_BIF_SSID)/sizeof(ixPSX80_WRP_BIF_SSID[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL", REG_SMC, 0x1500050, &ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL[0], sizeof(ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL)/sizeof(ixPSX80_WRP_BIF_LANE_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_LINK_CONFIG", REG_SMC, 0x1500080, &ixPSX80_WRP_PCIE_LINK_CONFIG[0], sizeof(ixPSX80_WRP_PCIE_LINK_CONFIG)/sizeof(ixPSX80_WRP_PCIE_LINK_CONFIG[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_HOLD_TRAINING_A", REG_SMC, 0x1500800, &ixPSX80_WRP_PCIE_HOLD_TRAINING_A[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_A)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_A[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A", REG_SMC, 0x1500801, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_A[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_ASPM_A", REG_SMC, 0x1500802, &ixPSX80_WRP_BIF_STRAP_ASPM_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_A)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_A[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A", REG_SMC, 0x1500803, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_A[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_MISC_PORT_A", REG_SMC, 0x1500804, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_A)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_A[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A", REG_SMC, 0x1500805, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_A[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_PORT_IS_SB_A", REG_SMC, 0x1500813, &ixPSX80_WRP_PCIE_PORT_IS_SB_A[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_A)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_A[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_HOLD_TRAINING_B", REG_SMC, 0x1500900, &ixPSX80_WRP_PCIE_HOLD_TRAINING_B[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_B)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_B[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B", REG_SMC, 0x1500901, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_B[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_ASPM_B", REG_SMC, 0x1500902, &ixPSX80_WRP_BIF_STRAP_ASPM_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_B)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_B[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B", REG_SMC, 0x1500903, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_B[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_MISC_PORT_B", REG_SMC, 0x1500904, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_B)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_B[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B", REG_SMC, 0x1500905, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_B[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_PORT_IS_SB_B", REG_SMC, 0x1500913, &ixPSX80_WRP_PCIE_PORT_IS_SB_B[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_B)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_B[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_HOLD_TRAINING_C", REG_SMC, 0x1500a00, &ixPSX80_WRP_PCIE_HOLD_TRAINING_C[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_C)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_C[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C", REG_SMC, 0x1500a01, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_C[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_ASPM_C", REG_SMC, 0x1500a02, &ixPSX80_WRP_BIF_STRAP_ASPM_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_C)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_C[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C", REG_SMC, 0x1500a03, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_C[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_MISC_PORT_C", REG_SMC, 0x1500a04, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_C)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_C[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C", REG_SMC, 0x1500a05, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_C[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_PORT_IS_SB_C", REG_SMC, 0x1500a13, &ixPSX80_WRP_PCIE_PORT_IS_SB_C[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_C)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_C[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_HOLD_TRAINING_D", REG_SMC, 0x1500b00, &ixPSX80_WRP_PCIE_HOLD_TRAINING_D[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_D)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_D[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D", REG_SMC, 0x1500b01, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_D[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_ASPM_D", REG_SMC, 0x1500b02, &ixPSX80_WRP_BIF_STRAP_ASPM_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_D)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_D[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D", REG_SMC, 0x1500b03, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_D[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_MISC_PORT_D", REG_SMC, 0x1500b04, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_D)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_D[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D", REG_SMC, 0x1500b05, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_D[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_PORT_IS_SB_D", REG_SMC, 0x1500b13, &ixPSX80_WRP_PCIE_PORT_IS_SB_D[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_D)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_D[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_HOLD_TRAINING_E", REG_SMC, 0x1500c00, &ixPSX80_WRP_PCIE_HOLD_TRAINING_E[0], sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_E)/sizeof(ixPSX80_WRP_PCIE_HOLD_TRAINING_E[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E", REG_SMC, 0x1500c01, &ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_SPEED_PORT_E[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_ASPM_E", REG_SMC, 0x1500c02, &ixPSX80_WRP_BIF_STRAP_ASPM_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_E)/sizeof(ixPSX80_WRP_BIF_STRAP_ASPM_E[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E", REG_SMC, 0x1500c03, &ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E)/sizeof(ixPSX80_WRP_BIF_STRAP_LC_MISC_PORT_E[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_MISC_PORT_E", REG_SMC, 0x1500c04, &ixPSX80_WRP_BIF_STRAP_MISC_PORT_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_E)/sizeof(ixPSX80_WRP_BIF_STRAP_MISC_PORT_E[0]), 0, 0 },
+	{ "ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E", REG_SMC, 0x1500c05, &ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E[0], sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E)/sizeof(ixPSX80_WRP_BIF_STRAP_LINK_TRAINING_E[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_PORT_IS_SB_E", REG_SMC, 0x1500c13, &ixPSX80_WRP_PCIE_PORT_IS_SB_E[0], sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_E)/sizeof(ixPSX80_WRP_PCIE_PORT_IS_SB_E[0]), 0, 0 },
+	{ "mmBUS_CNTL", REG_MMIO, 0x1508, &mmBUS_CNTL[0], sizeof(mmBUS_CNTL)/sizeof(mmBUS_CNTL[0]), 0, 0 },
+	{ "ixPSX80_WRP_LNCNT_CONTROL", REG_SMC, 0x1508030, &ixPSX80_WRP_LNCNT_CONTROL[0], sizeof(ixPSX80_WRP_LNCNT_CONTROL)/sizeof(ixPSX80_WRP_LNCNT_CONTROL[0]), 0, 0 },
+	{ "ixPSX80_WRP_CFG_LNC_WINDOW", REG_SMC, 0x1508031, &ixPSX80_WRP_CFG_LNC_WINDOW[0], sizeof(ixPSX80_WRP_CFG_LNC_WINDOW)/sizeof(ixPSX80_WRP_CFG_LNC_WINDOW[0]), 0, 0 },
+	{ "ixPSX80_WRP_LNCNT_QUAN_THRD", REG_SMC, 0x1508032, &ixPSX80_WRP_LNCNT_QUAN_THRD[0], sizeof(ixPSX80_WRP_LNCNT_QUAN_THRD)/sizeof(ixPSX80_WRP_LNCNT_QUAN_THRD[0]), 0, 0 },
+	{ "ixPSX80_WRP_LNCNT_WEIGHT", REG_SMC, 0x1508033, &ixPSX80_WRP_LNCNT_WEIGHT[0], sizeof(ixPSX80_WRP_LNCNT_WEIGHT)/sizeof(ixPSX80_WRP_LNCNT_WEIGHT[0]), 0, 0 },
+	{ "ixPSX80_WRP_LNC_TOTAL_WACC", REG_SMC, 0x1508034, &ixPSX80_WRP_LNC_TOTAL_WACC[0], sizeof(ixPSX80_WRP_LNC_TOTAL_WACC)/sizeof(ixPSX80_WRP_LNC_TOTAL_WACC[0]), 0, 0 },
+	{ "ixPSX80_WRP_LNC_BW_WACC", REG_SMC, 0x1508035, &ixPSX80_WRP_LNC_BW_WACC[0], sizeof(ixPSX80_WRP_LNC_BW_WACC)/sizeof(ixPSX80_WRP_LNC_BW_WACC[0]), 0, 0 },
+	{ "ixPSX80_WRP_LNC_CMN_WACC", REG_SMC, 0x1508036, &ixPSX80_WRP_LNC_CMN_WACC[0], sizeof(ixPSX80_WRP_LNC_CMN_WACC)/sizeof(ixPSX80_WRP_LNC_CMN_WACC[0]), 0, 0 },
+	{ "mmCONFIG_CNTL", REG_MMIO, 0x1509, &mmCONFIG_CNTL[0], sizeof(mmCONFIG_CNTL)/sizeof(mmCONFIG_CNTL[0]), 0, 0 },
+	{ "mmCONFIG_MEMSIZE", REG_MMIO, 0x150a, &mmCONFIG_MEMSIZE[0], sizeof(mmCONFIG_MEMSIZE)/sizeof(mmCONFIG_MEMSIZE[0]), 0, 0 },
+	{ "mmCONFIG_F0_BASE", REG_MMIO, 0x150b, &mmCONFIG_F0_BASE[0], sizeof(mmCONFIG_F0_BASE)/sizeof(mmCONFIG_F0_BASE[0]), 0, 0 },
+	{ "mmCONFIG_APER_SIZE", REG_MMIO, 0x150c, &mmCONFIG_APER_SIZE[0], sizeof(mmCONFIG_APER_SIZE)/sizeof(mmCONFIG_APER_SIZE[0]), 0, 0 },
+	{ "mmCONFIG_REG_APER_SIZE", REG_MMIO, 0x150d, &mmCONFIG_REG_APER_SIZE[0], sizeof(mmCONFIG_REG_APER_SIZE)/sizeof(mmCONFIG_REG_APER_SIZE[0]), 0, 0 },
+	{ "mmBIF_SCRATCH0", REG_MMIO, 0x150e, &mmBIF_SCRATCH0[0], sizeof(mmBIF_SCRATCH0)/sizeof(mmBIF_SCRATCH0[0]), 0, 0 },
+	{ "mmBIF_SCRATCH1", REG_MMIO, 0x150f, &mmBIF_SCRATCH1[0], sizeof(mmBIF_SCRATCH1)/sizeof(mmBIF_SCRATCH1[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_EFUSE", REG_SMC, 0x150fff0, &ixPSX80_WRP_PCIE_EFUSE[0], sizeof(ixPSX80_WRP_PCIE_EFUSE)/sizeof(ixPSX80_WRP_PCIE_EFUSE[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_EFUSE2", REG_SMC, 0x150fff1, &ixPSX80_WRP_PCIE_EFUSE2[0], sizeof(ixPSX80_WRP_PCIE_EFUSE2)/sizeof(ixPSX80_WRP_PCIE_EFUSE2[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_EFUSE3", REG_SMC, 0x150fff2, &ixPSX80_WRP_PCIE_EFUSE3[0], sizeof(ixPSX80_WRP_PCIE_EFUSE3)/sizeof(ixPSX80_WRP_PCIE_EFUSE3[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_EFUSE4", REG_SMC, 0x150fff3, &ixPSX80_WRP_PCIE_EFUSE4[0], sizeof(ixPSX80_WRP_PCIE_EFUSE4)/sizeof(ixPSX80_WRP_PCIE_EFUSE4[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_EFUSE5", REG_SMC, 0x150fff4, &ixPSX80_WRP_PCIE_EFUSE5[0], sizeof(ixPSX80_WRP_PCIE_EFUSE5)/sizeof(ixPSX80_WRP_PCIE_EFUSE5[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_EFUSE6", REG_SMC, 0x150fff5, &ixPSX80_WRP_PCIE_EFUSE6[0], sizeof(ixPSX80_WRP_PCIE_EFUSE6)/sizeof(ixPSX80_WRP_PCIE_EFUSE6[0]), 0, 0 },
+	{ "ixPSX80_WRP_PCIE_EFUSE7", REG_SMC, 0x150fff6, &ixPSX80_WRP_PCIE_EFUSE7[0], sizeof(ixPSX80_WRP_PCIE_EFUSE7)/sizeof(ixPSX80_WRP_PCIE_EFUSE7[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1", REG_SMC, 0x1510000, &ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1[0], sizeof(ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1)/sizeof(ixPSX81_WRP_BIF_STRAP_FEATURE_EN_1[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_PI_CNTL", REG_SMC, 0x1510001, &ixPSX81_WRP_BIF_STRAP_PI_CNTL[0], sizeof(ixPSX81_WRP_BIF_STRAP_PI_CNTL)/sizeof(ixPSX81_WRP_BIF_STRAP_PI_CNTL[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE", REG_SMC, 0x1510002, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_CORE[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE", REG_SMC, 0x1510003, &ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_CORE[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE", REG_SMC, 0x1510004, &ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE[0], sizeof(ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE)/sizeof(ixPSX81_WRP_BIF_STRAP_ERROR_IGNORE[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_TEST_DFT", REG_SMC, 0x1510005, &ixPSX81_WRP_BIF_STRAP_TEST_DFT[0], sizeof(ixPSX81_WRP_BIF_STRAP_TEST_DFT)/sizeof(ixPSX81_WRP_BIF_STRAP_TEST_DFT[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_ID", REG_SMC, 0x1510006, NULL, 0, 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_REV_ID", REG_SMC, 0x1510007, NULL, 0, 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_I2C_CNTL", REG_SMC, 0x1510008, NULL, 0, 0, 0 },
+	{ "ixPSX81_WRP_BIF_INT_CNTL", REG_SMC, 0x1510009, &ixPSX81_WRP_BIF_INT_CNTL[0], sizeof(ixPSX81_WRP_BIF_INT_CNTL)/sizeof(ixPSX81_WRP_BIF_INT_CNTL[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_ACS", REG_SMC, 0x151000a, &ixPSX81_WRP_BIF_STRAP_ACS[0], sizeof(ixPSX81_WRP_BIF_STRAP_ACS)/sizeof(ixPSX81_WRP_BIF_STRAP_ACS[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_PM", REG_SMC, 0x151000b, NULL, 0, 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2", REG_SMC, 0x151000c, &ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2[0], sizeof(ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2)/sizeof(ixPSX81_WRP_BIF_STRAP_FEATURE_EN_2[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_SERIAL_NUM", REG_SMC, 0x1510045, NULL, 0, 0, 0 },
+	{ "ixPSX81_WRP_BIF_SSID", REG_SMC, 0x1510046, &ixPSX81_WRP_BIF_SSID[0], sizeof(ixPSX81_WRP_BIF_SSID)/sizeof(ixPSX81_WRP_BIF_SSID[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL", REG_SMC, 0x1510050, &ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL[0], sizeof(ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL)/sizeof(ixPSX81_WRP_BIF_LANE_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_LINK_CONFIG", REG_SMC, 0x1510080, &ixPSX81_WRP_PCIE_LINK_CONFIG[0], sizeof(ixPSX81_WRP_PCIE_LINK_CONFIG)/sizeof(ixPSX81_WRP_PCIE_LINK_CONFIG[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_HOLD_TRAINING_A", REG_SMC, 0x1510800, &ixPSX81_WRP_PCIE_HOLD_TRAINING_A[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_A)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_A[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A", REG_SMC, 0x1510801, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_A[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_ASPM_A", REG_SMC, 0x1510802, &ixPSX81_WRP_BIF_STRAP_ASPM_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_A)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_A[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A", REG_SMC, 0x1510803, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_A[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_MISC_PORT_A", REG_SMC, 0x1510804, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_A)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_A[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A", REG_SMC, 0x1510805, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_A[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_PORT_IS_SB_A", REG_SMC, 0x1510813, &ixPSX81_WRP_PCIE_PORT_IS_SB_A[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_A)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_A[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_HOLD_TRAINING_B", REG_SMC, 0x1510900, &ixPSX81_WRP_PCIE_HOLD_TRAINING_B[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_B)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_B[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B", REG_SMC, 0x1510901, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_B[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_ASPM_B", REG_SMC, 0x1510902, &ixPSX81_WRP_BIF_STRAP_ASPM_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_B)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_B[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B", REG_SMC, 0x1510903, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_B[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_MISC_PORT_B", REG_SMC, 0x1510904, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_B)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_B[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B", REG_SMC, 0x1510905, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_B[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_PORT_IS_SB_B", REG_SMC, 0x1510913, &ixPSX81_WRP_PCIE_PORT_IS_SB_B[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_B)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_B[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_HOLD_TRAINING_C", REG_SMC, 0x1510a00, &ixPSX81_WRP_PCIE_HOLD_TRAINING_C[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_C)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_C[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C", REG_SMC, 0x1510a01, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_C[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_ASPM_C", REG_SMC, 0x1510a02, &ixPSX81_WRP_BIF_STRAP_ASPM_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_C)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_C[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C", REG_SMC, 0x1510a03, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_C[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_MISC_PORT_C", REG_SMC, 0x1510a04, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_C)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_C[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C", REG_SMC, 0x1510a05, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_C[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_PORT_IS_SB_C", REG_SMC, 0x1510a13, &ixPSX81_WRP_PCIE_PORT_IS_SB_C[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_C)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_C[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_HOLD_TRAINING_D", REG_SMC, 0x1510b00, &ixPSX81_WRP_PCIE_HOLD_TRAINING_D[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_D)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_D[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D", REG_SMC, 0x1510b01, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_D[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_ASPM_D", REG_SMC, 0x1510b02, &ixPSX81_WRP_BIF_STRAP_ASPM_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_D)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_D[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D", REG_SMC, 0x1510b03, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_D[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_MISC_PORT_D", REG_SMC, 0x1510b04, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_D)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_D[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D", REG_SMC, 0x1510b05, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_D[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_PORT_IS_SB_D", REG_SMC, 0x1510b13, &ixPSX81_WRP_PCIE_PORT_IS_SB_D[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_D)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_D[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_HOLD_TRAINING_E", REG_SMC, 0x1510c00, &ixPSX81_WRP_PCIE_HOLD_TRAINING_E[0], sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_E)/sizeof(ixPSX81_WRP_PCIE_HOLD_TRAINING_E[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E", REG_SMC, 0x1510c01, &ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_SPEED_PORT_E[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_ASPM_E", REG_SMC, 0x1510c02, &ixPSX81_WRP_BIF_STRAP_ASPM_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_E)/sizeof(ixPSX81_WRP_BIF_STRAP_ASPM_E[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E", REG_SMC, 0x1510c03, &ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E)/sizeof(ixPSX81_WRP_BIF_STRAP_LC_MISC_PORT_E[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_MISC_PORT_E", REG_SMC, 0x1510c04, &ixPSX81_WRP_BIF_STRAP_MISC_PORT_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_E)/sizeof(ixPSX81_WRP_BIF_STRAP_MISC_PORT_E[0]), 0, 0 },
+	{ "ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E", REG_SMC, 0x1510c05, &ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E[0], sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E)/sizeof(ixPSX81_WRP_BIF_STRAP_LINK_TRAINING_E[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_PORT_IS_SB_E", REG_SMC, 0x1510c13, &ixPSX81_WRP_PCIE_PORT_IS_SB_E[0], sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_E)/sizeof(ixPSX81_WRP_PCIE_PORT_IS_SB_E[0]), 0, 0 },
+	{ "mmMM_CFGREGS_CNTL", REG_MMIO, 0x1513, &mmMM_CFGREGS_CNTL[0], sizeof(mmMM_CFGREGS_CNTL)/sizeof(mmMM_CFGREGS_CNTL[0]), 0, 0 },
+	{ "mmBX_RESET_EN", REG_MMIO, 0x1514, &mmBX_RESET_EN[0], sizeof(mmBX_RESET_EN)/sizeof(mmBX_RESET_EN[0]), 0, 0 },
+	{ "mmHW_DEBUG", REG_MMIO, 0x1515, &mmHW_DEBUG[0], sizeof(mmHW_DEBUG)/sizeof(mmHW_DEBUG[0]), 0, 0 },
+	{ "mmMASTER_CREDIT_CNTL", REG_MMIO, 0x1516, &mmMASTER_CREDIT_CNTL[0], sizeof(mmMASTER_CREDIT_CNTL)/sizeof(mmMASTER_CREDIT_CNTL[0]), 0, 0 },
+	{ "mmSLAVE_REQ_CREDIT_CNTL", REG_MMIO, 0x1517, &mmSLAVE_REQ_CREDIT_CNTL[0], sizeof(mmSLAVE_REQ_CREDIT_CNTL)/sizeof(mmSLAVE_REQ_CREDIT_CNTL[0]), 0, 0 },
+	{ "mmBX_RESET_CNTL", REG_MMIO, 0x1518, &mmBX_RESET_CNTL[0], sizeof(mmBX_RESET_CNTL)/sizeof(mmBX_RESET_CNTL[0]), 0, 0 },
+	{ "ixPSX81_WRP_LNCNT_CONTROL", REG_SMC, 0x1518030, &ixPSX81_WRP_LNCNT_CONTROL[0], sizeof(ixPSX81_WRP_LNCNT_CONTROL)/sizeof(ixPSX81_WRP_LNCNT_CONTROL[0]), 0, 0 },
+	{ "ixPSX81_WRP_CFG_LNC_WINDOW", REG_SMC, 0x1518031, &ixPSX81_WRP_CFG_LNC_WINDOW[0], sizeof(ixPSX81_WRP_CFG_LNC_WINDOW)/sizeof(ixPSX81_WRP_CFG_LNC_WINDOW[0]), 0, 0 },
+	{ "ixPSX81_WRP_LNCNT_QUAN_THRD", REG_SMC, 0x1518032, &ixPSX81_WRP_LNCNT_QUAN_THRD[0], sizeof(ixPSX81_WRP_LNCNT_QUAN_THRD)/sizeof(ixPSX81_WRP_LNCNT_QUAN_THRD[0]), 0, 0 },
+	{ "ixPSX81_WRP_LNCNT_WEIGHT", REG_SMC, 0x1518033, &ixPSX81_WRP_LNCNT_WEIGHT[0], sizeof(ixPSX81_WRP_LNCNT_WEIGHT)/sizeof(ixPSX81_WRP_LNCNT_WEIGHT[0]), 0, 0 },
+	{ "ixPSX81_WRP_LNC_TOTAL_WACC", REG_SMC, 0x1518034, &ixPSX81_WRP_LNC_TOTAL_WACC[0], sizeof(ixPSX81_WRP_LNC_TOTAL_WACC)/sizeof(ixPSX81_WRP_LNC_TOTAL_WACC[0]), 0, 0 },
+	{ "ixPSX81_WRP_LNC_BW_WACC", REG_SMC, 0x1518035, &ixPSX81_WRP_LNC_BW_WACC[0], sizeof(ixPSX81_WRP_LNC_BW_WACC)/sizeof(ixPSX81_WRP_LNC_BW_WACC[0]), 0, 0 },
+	{ "ixPSX81_WRP_LNC_CMN_WACC", REG_SMC, 0x1518036, &ixPSX81_WRP_LNC_CMN_WACC[0], sizeof(ixPSX81_WRP_LNC_CMN_WACC)/sizeof(ixPSX81_WRP_LNC_CMN_WACC[0]), 0, 0 },
+	{ "mmINTERRUPT_CNTL", REG_MMIO, 0x151a, &mmINTERRUPT_CNTL[0], sizeof(mmINTERRUPT_CNTL)/sizeof(mmINTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmINTERRUPT_CNTL2", REG_MMIO, 0x151b, &mmINTERRUPT_CNTL2[0], sizeof(mmINTERRUPT_CNTL2)/sizeof(mmINTERRUPT_CNTL2[0]), 0, 0 },
+	{ "mmBIF_DEBUG_CNTL", REG_MMIO, 0x151c, &mmBIF_DEBUG_CNTL[0], sizeof(mmBIF_DEBUG_CNTL)/sizeof(mmBIF_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmBIF_DEBUG_MUX", REG_MMIO, 0x151d, &mmBIF_DEBUG_MUX[0], sizeof(mmBIF_DEBUG_MUX)/sizeof(mmBIF_DEBUG_MUX[0]), 0, 0 },
+	{ "mmBIF_DEBUG_OUT", REG_MMIO, 0x151e, &mmBIF_DEBUG_OUT[0], sizeof(mmBIF_DEBUG_OUT)/sizeof(mmBIF_DEBUG_OUT[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_EFUSE", REG_SMC, 0x151fff0, &ixPSX81_WRP_PCIE_EFUSE[0], sizeof(ixPSX81_WRP_PCIE_EFUSE)/sizeof(ixPSX81_WRP_PCIE_EFUSE[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_EFUSE2", REG_SMC, 0x151fff1, &ixPSX81_WRP_PCIE_EFUSE2[0], sizeof(ixPSX81_WRP_PCIE_EFUSE2)/sizeof(ixPSX81_WRP_PCIE_EFUSE2[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_EFUSE3", REG_SMC, 0x151fff2, &ixPSX81_WRP_PCIE_EFUSE3[0], sizeof(ixPSX81_WRP_PCIE_EFUSE3)/sizeof(ixPSX81_WRP_PCIE_EFUSE3[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_EFUSE4", REG_SMC, 0x151fff3, &ixPSX81_WRP_PCIE_EFUSE4[0], sizeof(ixPSX81_WRP_PCIE_EFUSE4)/sizeof(ixPSX81_WRP_PCIE_EFUSE4[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_EFUSE5", REG_SMC, 0x151fff4, &ixPSX81_WRP_PCIE_EFUSE5[0], sizeof(ixPSX81_WRP_PCIE_EFUSE5)/sizeof(ixPSX81_WRP_PCIE_EFUSE5[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_EFUSE6", REG_SMC, 0x151fff5, &ixPSX81_WRP_PCIE_EFUSE6[0], sizeof(ixPSX81_WRP_PCIE_EFUSE6)/sizeof(ixPSX81_WRP_PCIE_EFUSE6[0]), 0, 0 },
+	{ "ixPSX81_WRP_PCIE_EFUSE7", REG_SMC, 0x151fff6, &ixPSX81_WRP_PCIE_EFUSE7[0], sizeof(ixPSX81_WRP_PCIE_EFUSE7)/sizeof(ixPSX81_WRP_PCIE_EFUSE7[0]), 0, 0 },
+	{ "mmHDP_MEM_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1520, &mmHDP_MEM_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_MEM_COHERENCY_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmCLKREQB_PAD_CNTL", REG_MMIO, 0x1521, &mmCLKREQB_PAD_CNTL[0], sizeof(mmCLKREQB_PAD_CNTL)/sizeof(mmCLKREQB_PAD_CNTL[0]), 0, 0 },
+	{ "mmSMBDAT_PAD_CNTL", REG_MMIO, 0x1522, &mmSMBDAT_PAD_CNTL[0], sizeof(mmSMBDAT_PAD_CNTL)/sizeof(mmSMBDAT_PAD_CNTL[0]), 0, 0 },
+	{ "mmSMBCLK_PAD_CNTL", REG_MMIO, 0x1523, &mmSMBCLK_PAD_CNTL[0], sizeof(mmSMBCLK_PAD_CNTL)/sizeof(mmSMBCLK_PAD_CNTL[0]), 0, 0 },
+	{ "mmBIF_FB_EN", REG_MMIO, 0x1524, &mmBIF_FB_EN[0], sizeof(mmBIF_FB_EN)/sizeof(mmBIF_FB_EN[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_CNTL1", REG_MMIO, 0x1525, &mmBIF_BUSNUM_CNTL1[0], sizeof(mmBIF_BUSNUM_CNTL1)/sizeof(mmBIF_BUSNUM_CNTL1[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_LIST0", REG_MMIO, 0x1526, &mmBIF_BUSNUM_LIST0[0], sizeof(mmBIF_BUSNUM_LIST0)/sizeof(mmBIF_BUSNUM_LIST0[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_LIST1", REG_MMIO, 0x1527, &mmBIF_BUSNUM_LIST1[0], sizeof(mmBIF_BUSNUM_LIST1)/sizeof(mmBIF_BUSNUM_LIST1[0]), 0, 0 },
+	{ "mmHDP_REG_COHERENCY_FLUSH_CNTL", REG_MMIO, 0x1528, &mmHDP_REG_COHERENCY_FLUSH_CNTL[0], sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL)/sizeof(mmHDP_REG_COHERENCY_FLUSH_CNTL[0]), 0, 0 },
+	{ "mmBIF_BUSY_DELAY_CNTR", REG_MMIO, 0x1529, &mmBIF_BUSY_DELAY_CNTR[0], sizeof(mmBIF_BUSY_DELAY_CNTR)/sizeof(mmBIF_BUSY_DELAY_CNTR[0]), 0, 0 },
+	{ "mmBIF_BUSNUM_CNTL2", REG_MMIO, 0x152b, &mmBIF_BUSNUM_CNTL2[0], sizeof(mmBIF_BUSNUM_CNTL2)/sizeof(mmBIF_BUSNUM_CNTL2[0]), 0, 0 },
+	{ "mmBIF_PERFMON_CNTL", REG_MMIO, 0x152c, &mmBIF_PERFMON_CNTL[0], sizeof(mmBIF_PERFMON_CNTL)/sizeof(mmBIF_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmBIF_PERFCOUNTER0_RESULT", REG_MMIO, 0x152d, &mmBIF_PERFCOUNTER0_RESULT[0], sizeof(mmBIF_PERFCOUNTER0_RESULT)/sizeof(mmBIF_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmBIF_PERFCOUNTER1_RESULT", REG_MMIO, 0x152e, &mmBIF_PERFCOUNTER1_RESULT[0], sizeof(mmBIF_PERFCOUNTER1_RESULT)/sizeof(mmBIF_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmBIF_RB_CNTL", REG_MMIO, 0x1530, &mmBIF_RB_CNTL[0], sizeof(mmBIF_RB_CNTL)/sizeof(mmBIF_RB_CNTL[0]), 0, 0 },
+	{ "mmBIF_RB_BASE", REG_MMIO, 0x1531, &mmBIF_RB_BASE[0], sizeof(mmBIF_RB_BASE)/sizeof(mmBIF_RB_BASE[0]), 0, 0 },
+	{ "mmBIF_RB_RPTR", REG_MMIO, 0x1532, &mmBIF_RB_RPTR[0], sizeof(mmBIF_RB_RPTR)/sizeof(mmBIF_RB_RPTR[0]), 0, 0 },
+	{ "mmBIF_RB_WPTR", REG_MMIO, 0x1533, &mmBIF_RB_WPTR[0], sizeof(mmBIF_RB_WPTR)/sizeof(mmBIF_RB_WPTR[0]), 0, 0 },
+	{ "mmBIF_RB_WPTR_ADDR_HI", REG_MMIO, 0x1534, &mmBIF_RB_WPTR_ADDR_HI[0], sizeof(mmBIF_RB_WPTR_ADDR_HI)/sizeof(mmBIF_RB_WPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmBIF_RB_WPTR_ADDR_LO", REG_MMIO, 0x1535, &mmBIF_RB_WPTR_ADDR_LO[0], sizeof(mmBIF_RB_WPTR_ADDR_LO)/sizeof(mmBIF_RB_WPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSLAVE_HANG_PROTECTION_CNTL", REG_MMIO, 0x1536, &mmSLAVE_HANG_PROTECTION_CNTL[0], sizeof(mmSLAVE_HANG_PROTECTION_CNTL)/sizeof(mmSLAVE_HANG_PROTECTION_CNTL[0]), 0, 0 },
+	{ "mmGPU_HDP_FLUSH_REQ", REG_MMIO, 0x1537, &mmGPU_HDP_FLUSH_REQ[0], sizeof(mmGPU_HDP_FLUSH_REQ)/sizeof(mmGPU_HDP_FLUSH_REQ[0]), 0, 0 },
+	{ "mmGPU_HDP_FLUSH_DONE", REG_MMIO, 0x1538, &mmGPU_HDP_FLUSH_DONE[0], sizeof(mmGPU_HDP_FLUSH_DONE)/sizeof(mmGPU_HDP_FLUSH_DONE[0]), 0, 0 },
+	{ "mmSLAVE_HANG_ERROR", REG_MMIO, 0x153b, &mmSLAVE_HANG_ERROR[0], sizeof(mmSLAVE_HANG_ERROR)/sizeof(mmSLAVE_HANG_ERROR[0]), 0, 0 },
+	{ "mmCAPTURE_HOST_BUSNUM", REG_MMIO, 0x153c, &mmCAPTURE_HOST_BUSNUM[0], sizeof(mmCAPTURE_HOST_BUSNUM)/sizeof(mmCAPTURE_HOST_BUSNUM[0]), 0, 0 },
+	{ "mmHOST_BUSNUM", REG_MMIO, 0x153d, &mmHOST_BUSNUM[0], sizeof(mmHOST_BUSNUM)/sizeof(mmHOST_BUSNUM[0]), 0, 0 },
+	{ "mmPEER_REG_RANGE0", REG_MMIO, 0x153e, &mmPEER_REG_RANGE0[0], sizeof(mmPEER_REG_RANGE0)/sizeof(mmPEER_REG_RANGE0[0]), 0, 0 },
+	{ "mmPEER_REG_RANGE1", REG_MMIO, 0x153f, &mmPEER_REG_RANGE1[0], sizeof(mmPEER_REG_RANGE1)/sizeof(mmPEER_REG_RANGE1[0]), 0, 0 },
+	{ "mmPCIE_CAP_LIST", REG_MMIO, 0x16, &mmPCIE_CAP_LIST[0], sizeof(mmPCIE_CAP_LIST)/sizeof(mmPCIE_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_CAP", REG_MMIO, 0x16, &mmPCIE_CAP[0], sizeof(mmPCIE_CAP)/sizeof(mmPCIE_CAP[0]), 0, 0 },
+	{ "mmDEVICE_CAP", REG_MMIO, 0x17, &mmDEVICE_CAP[0], sizeof(mmDEVICE_CAP)/sizeof(mmDEVICE_CAP[0]), 0, 0 },
+	{ "mmDEVICE_STATUS", REG_MMIO, 0x18, &mmDEVICE_STATUS[0], sizeof(mmDEVICE_STATUS)/sizeof(mmDEVICE_STATUS[0]), 0, 0 },
+	{ "mmDEVICE_CNTL", REG_MMIO, 0x18, &mmDEVICE_CNTL[0], sizeof(mmDEVICE_CNTL)/sizeof(mmDEVICE_CNTL[0]), 0, 0 },
+	{ "mmLINK_CAP", REG_MMIO, 0x19, &mmLINK_CAP[0], sizeof(mmLINK_CAP)/sizeof(mmLINK_CAP[0]), 0, 0 },
+	{ "mmLINK_STATUS", REG_MMIO, 0x1a, &mmLINK_STATUS[0], sizeof(mmLINK_STATUS)/sizeof(mmLINK_STATUS[0]), 0, 0 },
+	{ "mmLINK_CNTL", REG_MMIO, 0x1a, &mmLINK_CNTL[0], sizeof(mmLINK_CNTL)/sizeof(mmLINK_CNTL[0]), 0, 0 },
+	{ "mmDEVICE_CAP2", REG_MMIO, 0x1f, &mmDEVICE_CAP2[0], sizeof(mmDEVICE_CAP2)/sizeof(mmDEVICE_CAP2[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_HW_DEBUG", REG_SMC, 0x2, &ixD2F1_PCIEP_HW_DEBUG[0], sizeof(ixD2F1_PCIEP_HW_DEBUG)/sizeof(ixD2F1_PCIEP_HW_DEBUG[0]), 0, 0 },
+	{ "mmPROG_INTERFACE", REG_MMIO, 0x2, &mmPROG_INTERFACE[0], sizeof(mmPROG_INTERFACE)/sizeof(mmPROG_INTERFACE[0]), 0, 0 },
+	{ "mmREVISION_ID", REG_MMIO, 0x2, &mmREVISION_ID[0], sizeof(mmREVISION_ID)/sizeof(mmREVISION_ID[0]), 0, 0 },
+	{ "mmBASE_CLASS", REG_MMIO, 0x2, &mmBASE_CLASS[0], sizeof(mmBASE_CLASS)/sizeof(mmBASE_CLASS[0]), 0, 0 },
+	{ "mmSUB_CLASS", REG_MMIO, 0x2, &mmSUB_CLASS[0], sizeof(mmSUB_CLASS)/sizeof(mmSUB_CLASS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CNTL", REG_SMC, 0x20, &ixD2F1_PCIE_TX_CNTL[0], sizeof(ixD2F1_PCIE_TX_CNTL)/sizeof(ixD2F1_PCIE_TX_CNTL[0]), 0, 0 },
+	{ "mmDEVICE_STATUS2", REG_MMIO, 0x20, &mmDEVICE_STATUS2[0], sizeof(mmDEVICE_STATUS2)/sizeof(mmDEVICE_STATUS2[0]), 0, 0 },
+	{ "mmDEVICE_CNTL2", REG_MMIO, 0x20, &mmDEVICE_CNTL2[0], sizeof(mmDEVICE_CNTL2)/sizeof(mmDEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD2F1_VENDOR_ID", REG_SMC, 0x2000000, &ixD2F1_VENDOR_ID[0], sizeof(ixD2F1_VENDOR_ID)/sizeof(ixD2F1_VENDOR_ID[0]), 0, 0 },
+	{ "ixD2F1_COMMAND", REG_SMC, 0x2000001, &ixD2F1_COMMAND[0], sizeof(ixD2F1_COMMAND)/sizeof(ixD2F1_COMMAND[0]), 0, 0 },
+	{ "ixD2F1_STATUS", REG_SMC, 0x2000001, &ixD2F1_STATUS[0], sizeof(ixD2F1_STATUS)/sizeof(ixD2F1_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PROG_INTERFACE", REG_SMC, 0x2000002, &ixD2F1_PROG_INTERFACE[0], sizeof(ixD2F1_PROG_INTERFACE)/sizeof(ixD2F1_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD2F1_REVISION_ID", REG_SMC, 0x2000002, &ixD2F1_REVISION_ID[0], sizeof(ixD2F1_REVISION_ID)/sizeof(ixD2F1_REVISION_ID[0]), 0, 0 },
+	{ "ixD2F1_BASE_CLASS", REG_SMC, 0x2000002, &ixD2F1_BASE_CLASS[0], sizeof(ixD2F1_BASE_CLASS)/sizeof(ixD2F1_BASE_CLASS[0]), 0, 0 },
+	{ "ixD2F1_SUB_CLASS", REG_SMC, 0x2000002, &ixD2F1_SUB_CLASS[0], sizeof(ixD2F1_SUB_CLASS)/sizeof(ixD2F1_SUB_CLASS[0]), 0, 0 },
+	{ "ixD2F1_CACHE_LINE", REG_SMC, 0x2000003, &ixD2F1_CACHE_LINE[0], sizeof(ixD2F1_CACHE_LINE)/sizeof(ixD2F1_CACHE_LINE[0]), 0, 0 },
+	{ "ixD2F1_LATENCY", REG_SMC, 0x2000003, &ixD2F1_LATENCY[0], sizeof(ixD2F1_LATENCY)/sizeof(ixD2F1_LATENCY[0]), 0, 0 },
+	{ "ixD2F1_HEADER", REG_SMC, 0x2000003, &ixD2F1_HEADER[0], sizeof(ixD2F1_HEADER)/sizeof(ixD2F1_HEADER[0]), 0, 0 },
+	{ "ixD2F1_BIST", REG_SMC, 0x2000003, &ixD2F1_BIST[0], sizeof(ixD2F1_BIST)/sizeof(ixD2F1_BIST[0]), 0, 0 },
+	{ "ixD2F1_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x2000006, &ixD2F1_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F1_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F1_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD2F1_SECONDARY_STATUS", REG_SMC, 0x2000007, &ixD2F1_SECONDARY_STATUS[0], sizeof(ixD2F1_SECONDARY_STATUS)/sizeof(ixD2F1_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD2F1_IO_BASE_LIMIT", REG_SMC, 0x2000007, &ixD2F1_IO_BASE_LIMIT[0], sizeof(ixD2F1_IO_BASE_LIMIT)/sizeof(ixD2F1_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F1_MEM_BASE_LIMIT", REG_SMC, 0x2000008, &ixD2F1_MEM_BASE_LIMIT[0], sizeof(ixD2F1_MEM_BASE_LIMIT)/sizeof(ixD2F1_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F1_PREF_BASE_LIMIT", REG_SMC, 0x2000009, &ixD2F1_PREF_BASE_LIMIT[0], sizeof(ixD2F1_PREF_BASE_LIMIT)/sizeof(ixD2F1_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F1_PREF_BASE_UPPER", REG_SMC, 0x200000a, &ixD2F1_PREF_BASE_UPPER[0], sizeof(ixD2F1_PREF_BASE_UPPER)/sizeof(ixD2F1_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD2F1_PREF_LIMIT_UPPER", REG_SMC, 0x200000b, &ixD2F1_PREF_LIMIT_UPPER[0], sizeof(ixD2F1_PREF_LIMIT_UPPER)/sizeof(ixD2F1_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD2F1_IO_BASE_LIMIT_HI", REG_SMC, 0x200000c, &ixD2F1_IO_BASE_LIMIT_HI[0], sizeof(ixD2F1_IO_BASE_LIMIT_HI)/sizeof(ixD2F1_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD2F1_CAP_PTR", REG_SMC, 0x200000d, &ixD2F1_CAP_PTR[0], sizeof(ixD2F1_CAP_PTR)/sizeof(ixD2F1_CAP_PTR[0]), 0, 0 },
+	{ "ixD2F1_IRQ_BRIDGE_CNTL", REG_SMC, 0x200000f, &ixD2F1_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F1_IRQ_BRIDGE_CNTL)/sizeof(ixD2F1_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F1_INTERRUPT_LINE", REG_SMC, 0x200000f, &ixD2F1_INTERRUPT_LINE[0], sizeof(ixD2F1_INTERRUPT_LINE)/sizeof(ixD2F1_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD2F1_INTERRUPT_PIN", REG_SMC, 0x200000f, &ixD2F1_INTERRUPT_PIN[0], sizeof(ixD2F1_INTERRUPT_PIN)/sizeof(ixD2F1_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD2F1_EXT_BRIDGE_CNTL", REG_SMC, 0x2000010, &ixD2F1_EXT_BRIDGE_CNTL[0], sizeof(ixD2F1_EXT_BRIDGE_CNTL)/sizeof(ixD2F1_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PMI_CAP_LIST", REG_SMC, 0x2000014, &ixD2F1_PMI_CAP_LIST[0], sizeof(ixD2F1_PMI_CAP_LIST)/sizeof(ixD2F1_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PMI_CAP", REG_SMC, 0x2000014, &ixD2F1_PMI_CAP[0], sizeof(ixD2F1_PMI_CAP)/sizeof(ixD2F1_PMI_CAP[0]), 0, 0 },
+	{ "ixD2F1_PMI_STATUS_CNTL", REG_SMC, 0x2000015, &ixD2F1_PMI_STATUS_CNTL[0], sizeof(ixD2F1_PMI_STATUS_CNTL)/sizeof(ixD2F1_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_CAP_LIST", REG_SMC, 0x2000016, &ixD2F1_PCIE_CAP_LIST[0], sizeof(ixD2F1_PCIE_CAP_LIST)/sizeof(ixD2F1_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_CAP", REG_SMC, 0x2000016, &ixD2F1_PCIE_CAP[0], sizeof(ixD2F1_PCIE_CAP)/sizeof(ixD2F1_PCIE_CAP[0]), 0, 0 },
+	{ "ixD2F1_DEVICE_CAP", REG_SMC, 0x2000017, &ixD2F1_DEVICE_CAP[0], sizeof(ixD2F1_DEVICE_CAP)/sizeof(ixD2F1_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD2F1_DEVICE_STATUS", REG_SMC, 0x2000018, &ixD2F1_DEVICE_STATUS[0], sizeof(ixD2F1_DEVICE_STATUS)/sizeof(ixD2F1_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD2F1_DEVICE_CNTL", REG_SMC, 0x2000018, &ixD2F1_DEVICE_CNTL[0], sizeof(ixD2F1_DEVICE_CNTL)/sizeof(ixD2F1_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD2F1_LINK_CAP", REG_SMC, 0x2000019, &ixD2F1_LINK_CAP[0], sizeof(ixD2F1_LINK_CAP)/sizeof(ixD2F1_LINK_CAP[0]), 0, 0 },
+	{ "ixD2F1_LINK_STATUS", REG_SMC, 0x200001a, &ixD2F1_LINK_STATUS[0], sizeof(ixD2F1_LINK_STATUS)/sizeof(ixD2F1_LINK_STATUS[0]), 0, 0 },
+	{ "ixD2F1_LINK_CNTL", REG_SMC, 0x200001a, &ixD2F1_LINK_CNTL[0], sizeof(ixD2F1_LINK_CNTL)/sizeof(ixD2F1_LINK_CNTL[0]), 0, 0 },
+	{ "ixD2F1_SLOT_CAP", REG_SMC, 0x200001b, &ixD2F1_SLOT_CAP[0], sizeof(ixD2F1_SLOT_CAP)/sizeof(ixD2F1_SLOT_CAP[0]), 0, 0 },
+	{ "ixD2F1_SLOT_STATUS", REG_SMC, 0x200001c, &ixD2F1_SLOT_STATUS[0], sizeof(ixD2F1_SLOT_STATUS)/sizeof(ixD2F1_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD2F1_SLOT_CNTL", REG_SMC, 0x200001c, &ixD2F1_SLOT_CNTL[0], sizeof(ixD2F1_SLOT_CNTL)/sizeof(ixD2F1_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD2F1_ROOT_CNTL", REG_SMC, 0x200001d, &ixD2F1_ROOT_CNTL[0], sizeof(ixD2F1_ROOT_CNTL)/sizeof(ixD2F1_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD2F1_ROOT_CAP", REG_SMC, 0x200001d, &ixD2F1_ROOT_CAP[0], sizeof(ixD2F1_ROOT_CAP)/sizeof(ixD2F1_ROOT_CAP[0]), 0, 0 },
+	{ "ixD2F1_ROOT_STATUS", REG_SMC, 0x200001e, &ixD2F1_ROOT_STATUS[0], sizeof(ixD2F1_ROOT_STATUS)/sizeof(ixD2F1_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD2F1_DEVICE_CAP2", REG_SMC, 0x200001f, &ixD2F1_DEVICE_CAP2[0], sizeof(ixD2F1_DEVICE_CAP2)/sizeof(ixD2F1_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD2F1_DEVICE_STATUS2", REG_SMC, 0x2000020, &ixD2F1_DEVICE_STATUS2[0], sizeof(ixD2F1_DEVICE_STATUS2)/sizeof(ixD2F1_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD2F1_DEVICE_CNTL2", REG_SMC, 0x2000020, &ixD2F1_DEVICE_CNTL2[0], sizeof(ixD2F1_DEVICE_CNTL2)/sizeof(ixD2F1_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD2F1_LINK_CAP2", REG_SMC, 0x2000021, &ixD2F1_LINK_CAP2[0], sizeof(ixD2F1_LINK_CAP2)/sizeof(ixD2F1_LINK_CAP2[0]), 0, 0 },
+	{ "ixD2F1_LINK_STATUS2", REG_SMC, 0x2000022, &ixD2F1_LINK_STATUS2[0], sizeof(ixD2F1_LINK_STATUS2)/sizeof(ixD2F1_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD2F1_LINK_CNTL2", REG_SMC, 0x2000022, &ixD2F1_LINK_CNTL2[0], sizeof(ixD2F1_LINK_CNTL2)/sizeof(ixD2F1_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD2F1_SLOT_CAP2", REG_SMC, 0x2000023, &ixD2F1_SLOT_CAP2[0], sizeof(ixD2F1_SLOT_CAP2)/sizeof(ixD2F1_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD2F1_SLOT_STATUS2", REG_SMC, 0x2000024, &ixD2F1_SLOT_STATUS2[0], sizeof(ixD2F1_SLOT_STATUS2)/sizeof(ixD2F1_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD2F1_SLOT_CNTL2", REG_SMC, 0x2000024, &ixD2F1_SLOT_CNTL2[0], sizeof(ixD2F1_SLOT_CNTL2)/sizeof(ixD2F1_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD2F1_MSI_CAP_LIST", REG_SMC, 0x2000028, &ixD2F1_MSI_CAP_LIST[0], sizeof(ixD2F1_MSI_CAP_LIST)/sizeof(ixD2F1_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_MSI_MSG_ADDR_LO", REG_SMC, 0x2000029, &ixD2F1_MSI_MSG_ADDR_LO[0], sizeof(ixD2F1_MSI_MSG_ADDR_LO)/sizeof(ixD2F1_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F1_MSI_MSG_ADDR_HI", REG_SMC, 0x200002a, &ixD2F1_MSI_MSG_ADDR_HI[0], sizeof(ixD2F1_MSI_MSG_ADDR_HI)/sizeof(ixD2F1_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F1_MSI_MSG_DATA", REG_SMC, 0x200002a, &ixD2F1_MSI_MSG_DATA[0], sizeof(ixD2F1_MSI_MSG_DATA)/sizeof(ixD2F1_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD2F1_MSI_MSG_DATA_64", REG_SMC, 0x200002b, &ixD2F1_MSI_MSG_DATA_64[0], sizeof(ixD2F1_MSI_MSG_DATA_64)/sizeof(ixD2F1_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD2F1_SSID_CAP_LIST", REG_SMC, 0x2000030, &ixD2F1_SSID_CAP_LIST[0], sizeof(ixD2F1_SSID_CAP_LIST)/sizeof(ixD2F1_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_SSID_CAP", REG_SMC, 0x2000031, &ixD2F1_SSID_CAP[0], sizeof(ixD2F1_SSID_CAP)/sizeof(ixD2F1_SSID_CAP[0]), 0, 0 },
+	{ "ixD2F1_MSI_MAP_CAP_LIST", REG_SMC, 0x2000032, &ixD2F1_MSI_MAP_CAP_LIST[0], sizeof(ixD2F1_MSI_MAP_CAP_LIST)/sizeof(ixD2F1_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_MSI_MAP_CAP", REG_SMC, 0x2000032, &ixD2F1_MSI_MAP_CAP[0], sizeof(ixD2F1_MSI_MAP_CAP)/sizeof(ixD2F1_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD2F1_MSI_MAP_ADDR_LO", REG_SMC, 0x2000033, &ixD2F1_MSI_MAP_ADDR_LO[0], sizeof(ixD2F1_MSI_MAP_ADDR_LO)/sizeof(ixD2F1_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F1_MSI_MAP_ADDR_HI", REG_SMC, 0x2000034, &ixD2F1_MSI_MAP_ADDR_HI[0], sizeof(ixD2F1_MSI_MAP_ADDR_HI)/sizeof(ixD2F1_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F1_PCIE_PORT_INDEX", REG_SMC, 0x2000038, &ixD2F1_PCIE_PORT_INDEX[0], sizeof(ixD2F1_PCIE_PORT_INDEX)/sizeof(ixD2F1_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD2F1_PCIE_PORT_DATA", REG_SMC, 0x2000039, &ixD2F1_PCIE_PORT_DATA[0], sizeof(ixD2F1_PCIE_PORT_DATA)/sizeof(ixD2F1_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x2000040, &ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x2000041, &ixD2F1_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x2000042, &ixD2F1_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x2000043, &ixD2F1_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F1_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x2000044, &ixD2F1_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x2000045, &ixD2F1_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F1_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F1_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x2000046, &ixD2F1_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F1_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F1_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD2F1_PCIE_PORT_VC_STATUS", REG_SMC, 0x2000047, &ixD2F1_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F1_PCIE_PORT_VC_STATUS)/sizeof(ixD2F1_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_PORT_VC_CNTL", REG_SMC, 0x2000047, &ixD2F1_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F1_PCIE_PORT_VC_CNTL)/sizeof(ixD2F1_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x2000048, &ixD2F1_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F1_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F1_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x2000049, &ixD2F1_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F1_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F1_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x200004a, &ixD2F1_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F1_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F1_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x200004b, &ixD2F1_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F1_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F1_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x200004c, &ixD2F1_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F1_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F1_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x200004d, &ixD2F1_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F1_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F1_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x2000050, &ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x2000051, &ixD2F1_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x2000052, &ixD2F1_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F1_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x2000054, &ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x2000055, &ixD2F1_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F1_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F1_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x2000056, &ixD2F1_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F1_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F1_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F1_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x2000057, &ixD2F1_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F1_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F1_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD2F1_PCIE_CORR_ERR_STATUS", REG_SMC, 0x2000058, &ixD2F1_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F1_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F1_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_CORR_ERR_MASK", REG_SMC, 0x2000059, &ixD2F1_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F1_PCIE_CORR_ERR_MASK)/sizeof(ixD2F1_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x200005a, &ixD2F1_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F1_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F1_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_HDR_LOG0", REG_SMC, 0x200005b, &ixD2F1_PCIE_HDR_LOG0[0], sizeof(ixD2F1_PCIE_HDR_LOG0)/sizeof(ixD2F1_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD2F1_PCIE_HDR_LOG1", REG_SMC, 0x200005c, &ixD2F1_PCIE_HDR_LOG1[0], sizeof(ixD2F1_PCIE_HDR_LOG1)/sizeof(ixD2F1_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_HDR_LOG2", REG_SMC, 0x200005d, &ixD2F1_PCIE_HDR_LOG2[0], sizeof(ixD2F1_PCIE_HDR_LOG2)/sizeof(ixD2F1_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD2F1_PCIE_HDR_LOG3", REG_SMC, 0x200005e, &ixD2F1_PCIE_HDR_LOG3[0], sizeof(ixD2F1_PCIE_HDR_LOG3)/sizeof(ixD2F1_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ROOT_ERR_CMD", REG_SMC, 0x200005f, &ixD2F1_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F1_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F1_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x2000060, &ixD2F1_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F1_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F1_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ERR_SRC_ID", REG_SMC, 0x2000061, &ixD2F1_PCIE_ERR_SRC_ID[0], sizeof(ixD2F1_PCIE_ERR_SRC_ID)/sizeof(ixD2F1_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x2000062, &ixD2F1_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x2000063, &ixD2F1_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x2000064, &ixD2F1_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x2000065, &ixD2F1_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F1_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x200009c, &ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LINK_CNTL3", REG_SMC, 0x200009d, &ixD2F1_PCIE_LINK_CNTL3[0], sizeof(ixD2F1_PCIE_LINK_CNTL3)/sizeof(ixD2F1_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x200009e, &ixD2F1_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F1_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F1_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x200009f, &ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x20000a0, &ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x20000a1, &ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x20000a2, &ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x20000a3, &ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x20000a4, &ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x20000a5, &ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x20000a6, &ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F1_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x20000a8, &ixD2F1_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ACS_CNTL", REG_SMC, 0x20000a9, &ixD2F1_PCIE_ACS_CNTL[0], sizeof(ixD2F1_PCIE_ACS_CNTL)/sizeof(ixD2F1_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ACS_CAP", REG_SMC, 0x20000a9, &ixD2F1_PCIE_ACS_CAP[0], sizeof(ixD2F1_PCIE_ACS_CAP)/sizeof(ixD2F1_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x20000bc, &ixD2F1_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F1_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F1_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_CNTL", REG_SMC, 0x20000bd, &ixD2F1_PCIE_MC_CNTL[0], sizeof(ixD2F1_PCIE_MC_CNTL)/sizeof(ixD2F1_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_CAP", REG_SMC, 0x20000bd, &ixD2F1_PCIE_MC_CAP[0], sizeof(ixD2F1_PCIE_MC_CAP)/sizeof(ixD2F1_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_ADDR0", REG_SMC, 0x20000be, &ixD2F1_PCIE_MC_ADDR0[0], sizeof(ixD2F1_PCIE_MC_ADDR0)/sizeof(ixD2F1_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_ADDR1", REG_SMC, 0x20000bf, &ixD2F1_PCIE_MC_ADDR1[0], sizeof(ixD2F1_PCIE_MC_ADDR1)/sizeof(ixD2F1_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_RCV0", REG_SMC, 0x20000c0, &ixD2F1_PCIE_MC_RCV0[0], sizeof(ixD2F1_PCIE_MC_RCV0)/sizeof(ixD2F1_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_RCV1", REG_SMC, 0x20000c1, &ixD2F1_PCIE_MC_RCV1[0], sizeof(ixD2F1_PCIE_MC_RCV1)/sizeof(ixD2F1_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x20000c2, &ixD2F1_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F1_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F1_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x20000c3, &ixD2F1_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F1_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F1_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x20000c4, &ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x20000c5, &ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F1_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x20000c6, &ixD2F1_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F1_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F1_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD2F1_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x20000c7, &ixD2F1_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F1_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F1_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_REQUESTER_ID", REG_SMC, 0x21, &ixD2F1_PCIE_TX_REQUESTER_ID[0], sizeof(ixD2F1_PCIE_TX_REQUESTER_ID)/sizeof(ixD2F1_PCIE_TX_REQUESTER_ID[0]), 0, 0 },
+	{ "mmLINK_CAP2", REG_MMIO, 0x21, &mmLINK_CAP2[0], sizeof(mmLINK_CAP2)/sizeof(mmLINK_CAP2[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_VENDOR_SPECIFIC", REG_SMC, 0x22, &ixD2F1_PCIE_TX_VENDOR_SPECIFIC[0], sizeof(ixD2F1_PCIE_TX_VENDOR_SPECIFIC)/sizeof(ixD2F1_PCIE_TX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "mmLINK_STATUS2", REG_MMIO, 0x22, &mmLINK_STATUS2[0], sizeof(mmLINK_STATUS2)/sizeof(mmLINK_STATUS2[0]), 0, 0 },
+	{ "mmLINK_CNTL2", REG_MMIO, 0x22, &mmLINK_CNTL2[0], sizeof(mmLINK_CNTL2)/sizeof(mmLINK_CNTL2[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_REQUEST_NUM_CNTL", REG_SMC, 0x23, &ixD2F1_PCIE_TX_REQUEST_NUM_CNTL[0], sizeof(ixD2F1_PCIE_TX_REQUEST_NUM_CNTL)/sizeof(ixD2F1_PCIE_TX_REQUEST_NUM_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_SEQ", REG_SMC, 0x24, &ixD2F1_PCIE_TX_SEQ[0], sizeof(ixD2F1_PCIE_TX_SEQ)/sizeof(ixD2F1_PCIE_TX_SEQ[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_REPLAY", REG_SMC, 0x25, &ixD2F1_PCIE_TX_REPLAY[0], sizeof(ixD2F1_PCIE_TX_REPLAY)/sizeof(ixD2F1_PCIE_TX_REPLAY[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT", REG_SMC, 0x26, &ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT[0], sizeof(ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT)/sizeof(ixD2F1_PCIE_TX_ACK_LATENCY_LIMIT[0]), 0, 0 },
+	{ "mmBIF_RFE_SNOOP_REG", REG_MMIO, 0x27, &mmBIF_RFE_SNOOP_REG[0], sizeof(mmBIF_RFE_SNOOP_REG)/sizeof(mmBIF_RFE_SNOOP_REG[0]), 0, 0 },
+	{ "mmPCIE_WRAPPER0_C_PCIE_INDEX", REG_MMIO, 0x28, NULL, 0, 0, 0 },
+	{ "mmMSI_CAP_LIST", REG_MMIO, 0x28, &mmMSI_CAP_LIST[0], sizeof(mmMSI_CAP_LIST)/sizeof(mmMSI_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_WRAPPER0_C_PCIE_DATA", REG_MMIO, 0x29, NULL, 0, 0, 0 },
+	{ "mmMSI_MSG_ADDR_LO", REG_MMIO, 0x29, &mmMSI_MSG_ADDR_LO[0], sizeof(mmMSI_MSG_ADDR_LO)/sizeof(mmMSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "mmC_PCIE_DATA", REG_MMIO, 0x29, &mmC_PCIE_DATA[0], sizeof(mmC_PCIE_DATA)/sizeof(mmC_PCIE_DATA[0]), 0, 0 },
+	{ "mmMSI_MSG_ADDR_HI", REG_MMIO, 0x2a, &mmMSI_MSG_ADDR_HI[0], sizeof(mmMSI_MSG_ADDR_HI)/sizeof(mmMSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "mmMSI_MSG_DATA", REG_MMIO, 0x2a, &mmMSI_MSG_DATA[0], sizeof(mmMSI_MSG_DATA)/sizeof(mmMSI_MSG_DATA[0]), 0, 0 },
+	{ "mmMSI_MSG_DATA_64", REG_MMIO, 0x2b, &mmMSI_MSG_DATA_64[0], sizeof(mmMSI_MSG_DATA_64)/sizeof(mmMSI_MSG_DATA_64[0]), 0, 0 },
+	{ "mmCACHE_LINE", REG_MMIO, 0x3, &mmCACHE_LINE[0], sizeof(mmCACHE_LINE)/sizeof(mmCACHE_LINE[0]), 0, 0 },
+	{ "mmLATENCY", REG_MMIO, 0x3, &mmLATENCY[0], sizeof(mmLATENCY)/sizeof(mmLATENCY[0]), 0, 0 },
+	{ "mmHEADER", REG_MMIO, 0x3, &mmHEADER[0], sizeof(mmHEADER)/sizeof(mmHEADER[0]), 0, 0 },
+	{ "mmBIST", REG_MMIO, 0x3, &mmBIST[0], sizeof(mmBIST)/sizeof(mmBIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CREDITS_ADVT_P", REG_SMC, 0x30, &ixD2F1_PCIE_TX_CREDITS_ADVT_P[0], sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_P)/sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_P[0]), 0, 0 },
+	{ "ixD2F2_VENDOR_ID", REG_SMC, 0x3000000, &ixD2F2_VENDOR_ID[0], sizeof(ixD2F2_VENDOR_ID)/sizeof(ixD2F2_VENDOR_ID[0]), 0, 0 },
+	{ "ixD2F2_COMMAND", REG_SMC, 0x3000001, &ixD2F2_COMMAND[0], sizeof(ixD2F2_COMMAND)/sizeof(ixD2F2_COMMAND[0]), 0, 0 },
+	{ "ixD2F2_STATUS", REG_SMC, 0x3000001, &ixD2F2_STATUS[0], sizeof(ixD2F2_STATUS)/sizeof(ixD2F2_STATUS[0]), 0, 0 },
+	{ "ixD2F2_PROG_INTERFACE", REG_SMC, 0x3000002, &ixD2F2_PROG_INTERFACE[0], sizeof(ixD2F2_PROG_INTERFACE)/sizeof(ixD2F2_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD2F2_REVISION_ID", REG_SMC, 0x3000002, &ixD2F2_REVISION_ID[0], sizeof(ixD2F2_REVISION_ID)/sizeof(ixD2F2_REVISION_ID[0]), 0, 0 },
+	{ "ixD2F2_BASE_CLASS", REG_SMC, 0x3000002, &ixD2F2_BASE_CLASS[0], sizeof(ixD2F2_BASE_CLASS)/sizeof(ixD2F2_BASE_CLASS[0]), 0, 0 },
+	{ "ixD2F2_SUB_CLASS", REG_SMC, 0x3000002, &ixD2F2_SUB_CLASS[0], sizeof(ixD2F2_SUB_CLASS)/sizeof(ixD2F2_SUB_CLASS[0]), 0, 0 },
+	{ "ixD2F2_CACHE_LINE", REG_SMC, 0x3000003, &ixD2F2_CACHE_LINE[0], sizeof(ixD2F2_CACHE_LINE)/sizeof(ixD2F2_CACHE_LINE[0]), 0, 0 },
+	{ "ixD2F2_LATENCY", REG_SMC, 0x3000003, &ixD2F2_LATENCY[0], sizeof(ixD2F2_LATENCY)/sizeof(ixD2F2_LATENCY[0]), 0, 0 },
+	{ "ixD2F2_HEADER", REG_SMC, 0x3000003, &ixD2F2_HEADER[0], sizeof(ixD2F2_HEADER)/sizeof(ixD2F2_HEADER[0]), 0, 0 },
+	{ "ixD2F2_BIST", REG_SMC, 0x3000003, &ixD2F2_BIST[0], sizeof(ixD2F2_BIST)/sizeof(ixD2F2_BIST[0]), 0, 0 },
+	{ "ixD2F2_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x3000006, &ixD2F2_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F2_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F2_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD2F2_SECONDARY_STATUS", REG_SMC, 0x3000007, &ixD2F2_SECONDARY_STATUS[0], sizeof(ixD2F2_SECONDARY_STATUS)/sizeof(ixD2F2_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD2F2_IO_BASE_LIMIT", REG_SMC, 0x3000007, &ixD2F2_IO_BASE_LIMIT[0], sizeof(ixD2F2_IO_BASE_LIMIT)/sizeof(ixD2F2_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F2_MEM_BASE_LIMIT", REG_SMC, 0x3000008, &ixD2F2_MEM_BASE_LIMIT[0], sizeof(ixD2F2_MEM_BASE_LIMIT)/sizeof(ixD2F2_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F2_PREF_BASE_LIMIT", REG_SMC, 0x3000009, &ixD2F2_PREF_BASE_LIMIT[0], sizeof(ixD2F2_PREF_BASE_LIMIT)/sizeof(ixD2F2_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F2_PREF_BASE_UPPER", REG_SMC, 0x300000a, &ixD2F2_PREF_BASE_UPPER[0], sizeof(ixD2F2_PREF_BASE_UPPER)/sizeof(ixD2F2_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD2F2_PREF_LIMIT_UPPER", REG_SMC, 0x300000b, &ixD2F2_PREF_LIMIT_UPPER[0], sizeof(ixD2F2_PREF_LIMIT_UPPER)/sizeof(ixD2F2_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD2F2_IO_BASE_LIMIT_HI", REG_SMC, 0x300000c, &ixD2F2_IO_BASE_LIMIT_HI[0], sizeof(ixD2F2_IO_BASE_LIMIT_HI)/sizeof(ixD2F2_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD2F2_CAP_PTR", REG_SMC, 0x300000d, &ixD2F2_CAP_PTR[0], sizeof(ixD2F2_CAP_PTR)/sizeof(ixD2F2_CAP_PTR[0]), 0, 0 },
+	{ "ixD2F2_IRQ_BRIDGE_CNTL", REG_SMC, 0x300000f, &ixD2F2_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F2_IRQ_BRIDGE_CNTL)/sizeof(ixD2F2_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F2_INTERRUPT_LINE", REG_SMC, 0x300000f, &ixD2F2_INTERRUPT_LINE[0], sizeof(ixD2F2_INTERRUPT_LINE)/sizeof(ixD2F2_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD2F2_INTERRUPT_PIN", REG_SMC, 0x300000f, &ixD2F2_INTERRUPT_PIN[0], sizeof(ixD2F2_INTERRUPT_PIN)/sizeof(ixD2F2_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD2F2_EXT_BRIDGE_CNTL", REG_SMC, 0x3000010, &ixD2F2_EXT_BRIDGE_CNTL[0], sizeof(ixD2F2_EXT_BRIDGE_CNTL)/sizeof(ixD2F2_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PMI_CAP_LIST", REG_SMC, 0x3000014, &ixD2F2_PMI_CAP_LIST[0], sizeof(ixD2F2_PMI_CAP_LIST)/sizeof(ixD2F2_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PMI_CAP", REG_SMC, 0x3000014, &ixD2F2_PMI_CAP[0], sizeof(ixD2F2_PMI_CAP)/sizeof(ixD2F2_PMI_CAP[0]), 0, 0 },
+	{ "ixD2F2_PMI_STATUS_CNTL", REG_SMC, 0x3000015, &ixD2F2_PMI_STATUS_CNTL[0], sizeof(ixD2F2_PMI_STATUS_CNTL)/sizeof(ixD2F2_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_CAP_LIST", REG_SMC, 0x3000016, &ixD2F2_PCIE_CAP_LIST[0], sizeof(ixD2F2_PCIE_CAP_LIST)/sizeof(ixD2F2_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PCIE_CAP", REG_SMC, 0x3000016, &ixD2F2_PCIE_CAP[0], sizeof(ixD2F2_PCIE_CAP)/sizeof(ixD2F2_PCIE_CAP[0]), 0, 0 },
+	{ "ixD2F2_DEVICE_CAP", REG_SMC, 0x3000017, &ixD2F2_DEVICE_CAP[0], sizeof(ixD2F2_DEVICE_CAP)/sizeof(ixD2F2_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD2F2_DEVICE_STATUS", REG_SMC, 0x3000018, &ixD2F2_DEVICE_STATUS[0], sizeof(ixD2F2_DEVICE_STATUS)/sizeof(ixD2F2_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD2F2_DEVICE_CNTL", REG_SMC, 0x3000018, &ixD2F2_DEVICE_CNTL[0], sizeof(ixD2F2_DEVICE_CNTL)/sizeof(ixD2F2_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD2F2_LINK_CAP", REG_SMC, 0x3000019, &ixD2F2_LINK_CAP[0], sizeof(ixD2F2_LINK_CAP)/sizeof(ixD2F2_LINK_CAP[0]), 0, 0 },
+	{ "ixD2F2_LINK_STATUS", REG_SMC, 0x300001a, &ixD2F2_LINK_STATUS[0], sizeof(ixD2F2_LINK_STATUS)/sizeof(ixD2F2_LINK_STATUS[0]), 0, 0 },
+	{ "ixD2F2_LINK_CNTL", REG_SMC, 0x300001a, &ixD2F2_LINK_CNTL[0], sizeof(ixD2F2_LINK_CNTL)/sizeof(ixD2F2_LINK_CNTL[0]), 0, 0 },
+	{ "ixD2F2_SLOT_CAP", REG_SMC, 0x300001b, &ixD2F2_SLOT_CAP[0], sizeof(ixD2F2_SLOT_CAP)/sizeof(ixD2F2_SLOT_CAP[0]), 0, 0 },
+	{ "ixD2F2_SLOT_STATUS", REG_SMC, 0x300001c, &ixD2F2_SLOT_STATUS[0], sizeof(ixD2F2_SLOT_STATUS)/sizeof(ixD2F2_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD2F2_SLOT_CNTL", REG_SMC, 0x300001c, &ixD2F2_SLOT_CNTL[0], sizeof(ixD2F2_SLOT_CNTL)/sizeof(ixD2F2_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD2F2_ROOT_CNTL", REG_SMC, 0x300001d, &ixD2F2_ROOT_CNTL[0], sizeof(ixD2F2_ROOT_CNTL)/sizeof(ixD2F2_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD2F2_ROOT_CAP", REG_SMC, 0x300001d, &ixD2F2_ROOT_CAP[0], sizeof(ixD2F2_ROOT_CAP)/sizeof(ixD2F2_ROOT_CAP[0]), 0, 0 },
+	{ "ixD2F2_ROOT_STATUS", REG_SMC, 0x300001e, &ixD2F2_ROOT_STATUS[0], sizeof(ixD2F2_ROOT_STATUS)/sizeof(ixD2F2_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD2F2_DEVICE_CAP2", REG_SMC, 0x300001f, &ixD2F2_DEVICE_CAP2[0], sizeof(ixD2F2_DEVICE_CAP2)/sizeof(ixD2F2_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD2F2_DEVICE_STATUS2", REG_SMC, 0x3000020, &ixD2F2_DEVICE_STATUS2[0], sizeof(ixD2F2_DEVICE_STATUS2)/sizeof(ixD2F2_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD2F2_DEVICE_CNTL2", REG_SMC, 0x3000020, &ixD2F2_DEVICE_CNTL2[0], sizeof(ixD2F2_DEVICE_CNTL2)/sizeof(ixD2F2_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD2F2_LINK_CAP2", REG_SMC, 0x3000021, &ixD2F2_LINK_CAP2[0], sizeof(ixD2F2_LINK_CAP2)/sizeof(ixD2F2_LINK_CAP2[0]), 0, 0 },
+	{ "ixD2F2_LINK_STATUS2", REG_SMC, 0x3000022, &ixD2F2_LINK_STATUS2[0], sizeof(ixD2F2_LINK_STATUS2)/sizeof(ixD2F2_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD2F2_LINK_CNTL2", REG_SMC, 0x3000022, &ixD2F2_LINK_CNTL2[0], sizeof(ixD2F2_LINK_CNTL2)/sizeof(ixD2F2_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD2F2_SLOT_CAP2", REG_SMC, 0x3000023, &ixD2F2_SLOT_CAP2[0], sizeof(ixD2F2_SLOT_CAP2)/sizeof(ixD2F2_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD2F2_SLOT_STATUS2", REG_SMC, 0x3000024, &ixD2F2_SLOT_STATUS2[0], sizeof(ixD2F2_SLOT_STATUS2)/sizeof(ixD2F2_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD2F2_SLOT_CNTL2", REG_SMC, 0x3000024, &ixD2F2_SLOT_CNTL2[0], sizeof(ixD2F2_SLOT_CNTL2)/sizeof(ixD2F2_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD2F2_MSI_CAP_LIST", REG_SMC, 0x3000028, &ixD2F2_MSI_CAP_LIST[0], sizeof(ixD2F2_MSI_CAP_LIST)/sizeof(ixD2F2_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_MSI_MSG_ADDR_LO", REG_SMC, 0x3000029, &ixD2F2_MSI_MSG_ADDR_LO[0], sizeof(ixD2F2_MSI_MSG_ADDR_LO)/sizeof(ixD2F2_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F2_MSI_MSG_ADDR_HI", REG_SMC, 0x300002a, &ixD2F2_MSI_MSG_ADDR_HI[0], sizeof(ixD2F2_MSI_MSG_ADDR_HI)/sizeof(ixD2F2_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F2_MSI_MSG_DATA", REG_SMC, 0x300002a, &ixD2F2_MSI_MSG_DATA[0], sizeof(ixD2F2_MSI_MSG_DATA)/sizeof(ixD2F2_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD2F2_MSI_MSG_DATA_64", REG_SMC, 0x300002b, &ixD2F2_MSI_MSG_DATA_64[0], sizeof(ixD2F2_MSI_MSG_DATA_64)/sizeof(ixD2F2_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD2F2_SSID_CAP_LIST", REG_SMC, 0x3000030, &ixD2F2_SSID_CAP_LIST[0], sizeof(ixD2F2_SSID_CAP_LIST)/sizeof(ixD2F2_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_SSID_CAP", REG_SMC, 0x3000031, &ixD2F2_SSID_CAP[0], sizeof(ixD2F2_SSID_CAP)/sizeof(ixD2F2_SSID_CAP[0]), 0, 0 },
+	{ "ixD2F2_MSI_MAP_CAP_LIST", REG_SMC, 0x3000032, &ixD2F2_MSI_MAP_CAP_LIST[0], sizeof(ixD2F2_MSI_MAP_CAP_LIST)/sizeof(ixD2F2_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_MSI_MAP_CAP", REG_SMC, 0x3000032, &ixD2F2_MSI_MAP_CAP[0], sizeof(ixD2F2_MSI_MAP_CAP)/sizeof(ixD2F2_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD2F2_MSI_MAP_ADDR_LO", REG_SMC, 0x3000033, &ixD2F2_MSI_MAP_ADDR_LO[0], sizeof(ixD2F2_MSI_MAP_ADDR_LO)/sizeof(ixD2F2_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F2_MSI_MAP_ADDR_HI", REG_SMC, 0x3000034, &ixD2F2_MSI_MAP_ADDR_HI[0], sizeof(ixD2F2_MSI_MAP_ADDR_HI)/sizeof(ixD2F2_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F2_PCIE_PORT_INDEX", REG_SMC, 0x3000038, &ixD2F2_PCIE_PORT_INDEX[0], sizeof(ixD2F2_PCIE_PORT_INDEX)/sizeof(ixD2F2_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD2F2_PCIE_PORT_DATA", REG_SMC, 0x3000039, &ixD2F2_PCIE_PORT_DATA[0], sizeof(ixD2F2_PCIE_PORT_DATA)/sizeof(ixD2F2_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x3000040, &ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x3000041, &ixD2F2_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x3000042, &ixD2F2_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x3000043, &ixD2F2_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F2_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x3000044, &ixD2F2_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x3000045, &ixD2F2_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F2_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F2_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x3000046, &ixD2F2_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F2_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F2_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD2F2_PCIE_PORT_VC_STATUS", REG_SMC, 0x3000047, &ixD2F2_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F2_PCIE_PORT_VC_STATUS)/sizeof(ixD2F2_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD2F2_PCIE_PORT_VC_CNTL", REG_SMC, 0x3000047, &ixD2F2_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F2_PCIE_PORT_VC_CNTL)/sizeof(ixD2F2_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x3000048, &ixD2F2_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F2_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F2_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x3000049, &ixD2F2_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F2_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F2_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x300004a, &ixD2F2_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F2_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F2_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x300004b, &ixD2F2_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F2_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F2_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x300004c, &ixD2F2_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F2_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F2_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x300004d, &ixD2F2_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F2_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F2_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x3000050, &ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x3000051, &ixD2F2_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x3000052, &ixD2F2_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F2_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x3000054, &ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x3000055, &ixD2F2_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F2_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F2_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F2_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x3000056, &ixD2F2_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F2_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F2_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F2_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x3000057, &ixD2F2_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F2_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F2_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD2F2_PCIE_CORR_ERR_STATUS", REG_SMC, 0x3000058, &ixD2F2_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F2_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F2_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F2_PCIE_CORR_ERR_MASK", REG_SMC, 0x3000059, &ixD2F2_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F2_PCIE_CORR_ERR_MASK)/sizeof(ixD2F2_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F2_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x300005a, &ixD2F2_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F2_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F2_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_HDR_LOG0", REG_SMC, 0x300005b, &ixD2F2_PCIE_HDR_LOG0[0], sizeof(ixD2F2_PCIE_HDR_LOG0)/sizeof(ixD2F2_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD2F2_PCIE_HDR_LOG1", REG_SMC, 0x300005c, &ixD2F2_PCIE_HDR_LOG1[0], sizeof(ixD2F2_PCIE_HDR_LOG1)/sizeof(ixD2F2_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_HDR_LOG2", REG_SMC, 0x300005d, &ixD2F2_PCIE_HDR_LOG2[0], sizeof(ixD2F2_PCIE_HDR_LOG2)/sizeof(ixD2F2_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD2F2_PCIE_HDR_LOG3", REG_SMC, 0x300005e, &ixD2F2_PCIE_HDR_LOG3[0], sizeof(ixD2F2_PCIE_HDR_LOG3)/sizeof(ixD2F2_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD2F2_PCIE_ROOT_ERR_CMD", REG_SMC, 0x300005f, &ixD2F2_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F2_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F2_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD2F2_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x3000060, &ixD2F2_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F2_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F2_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F2_PCIE_ERR_SRC_ID", REG_SMC, 0x3000061, &ixD2F2_PCIE_ERR_SRC_ID[0], sizeof(ixD2F2_PCIE_ERR_SRC_ID)/sizeof(ixD2F2_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD2F2_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x3000062, &ixD2F2_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD2F2_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x3000063, &ixD2F2_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x3000064, &ixD2F2_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD2F2_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x3000065, &ixD2F2_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F2_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x300009c, &ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LINK_CNTL3", REG_SMC, 0x300009d, &ixD2F2_PCIE_LINK_CNTL3[0], sizeof(ixD2F2_PCIE_LINK_CNTL3)/sizeof(ixD2F2_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x300009e, &ixD2F2_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F2_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F2_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x300009f, &ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x30000a0, &ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x30000a1, &ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x30000a2, &ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x30000a3, &ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x30000a4, &ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x30000a5, &ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x30000a6, &ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F2_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x30000a8, &ixD2F2_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PCIE_ACS_CNTL", REG_SMC, 0x30000a9, &ixD2F2_PCIE_ACS_CNTL[0], sizeof(ixD2F2_PCIE_ACS_CNTL)/sizeof(ixD2F2_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_ACS_CAP", REG_SMC, 0x30000a9, &ixD2F2_PCIE_ACS_CAP[0], sizeof(ixD2F2_PCIE_ACS_CAP)/sizeof(ixD2F2_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x30000bc, &ixD2F2_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F2_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F2_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_CNTL", REG_SMC, 0x30000bd, &ixD2F2_PCIE_MC_CNTL[0], sizeof(ixD2F2_PCIE_MC_CNTL)/sizeof(ixD2F2_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_CAP", REG_SMC, 0x30000bd, &ixD2F2_PCIE_MC_CAP[0], sizeof(ixD2F2_PCIE_MC_CAP)/sizeof(ixD2F2_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_ADDR0", REG_SMC, 0x30000be, &ixD2F2_PCIE_MC_ADDR0[0], sizeof(ixD2F2_PCIE_MC_ADDR0)/sizeof(ixD2F2_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_ADDR1", REG_SMC, 0x30000bf, &ixD2F2_PCIE_MC_ADDR1[0], sizeof(ixD2F2_PCIE_MC_ADDR1)/sizeof(ixD2F2_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_RCV0", REG_SMC, 0x30000c0, &ixD2F2_PCIE_MC_RCV0[0], sizeof(ixD2F2_PCIE_MC_RCV0)/sizeof(ixD2F2_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_RCV1", REG_SMC, 0x30000c1, &ixD2F2_PCIE_MC_RCV1[0], sizeof(ixD2F2_PCIE_MC_RCV1)/sizeof(ixD2F2_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x30000c2, &ixD2F2_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F2_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F2_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x30000c3, &ixD2F2_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F2_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F2_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x30000c4, &ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x30000c5, &ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F2_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x30000c6, &ixD2F2_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F2_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F2_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD2F2_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x30000c7, &ixD2F2_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F2_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F2_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CREDITS_ADVT_NP", REG_SMC, 0x31, &ixD2F1_PCIE_TX_CREDITS_ADVT_NP[0], sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_NP)/sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_NP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CREDITS_ADVT_CPL", REG_SMC, 0x32, &ixD2F1_PCIE_TX_CREDITS_ADVT_CPL[0], sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_CPL)/sizeof(ixD2F1_PCIE_TX_CREDITS_ADVT_CPL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CREDITS_INIT_P", REG_SMC, 0x33, &ixD2F1_PCIE_TX_CREDITS_INIT_P[0], sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_P)/sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_P[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CREDITS_INIT_NP", REG_SMC, 0x34, &ixD2F1_PCIE_TX_CREDITS_INIT_NP[0], sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_NP)/sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_NP[0]), 0, 0 },
+	{ "mmNB_GBIF_INDEX", REG_MMIO, 0x34, &mmNB_GBIF_INDEX[0], sizeof(mmNB_GBIF_INDEX)/sizeof(mmNB_GBIF_INDEX[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CREDITS_INIT_CPL", REG_SMC, 0x35, &ixD2F1_PCIE_TX_CREDITS_INIT_CPL[0], sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_CPL)/sizeof(ixD2F1_PCIE_TX_CREDITS_INIT_CPL[0]), 0, 0 },
+	{ "mmNB_GBIF_DATA", REG_MMIO, 0x35, &mmNB_GBIF_DATA[0], sizeof(mmNB_GBIF_DATA)/sizeof(mmNB_GBIF_DATA[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CREDITS_STATUS", REG_SMC, 0x36, &ixD2F1_PCIE_TX_CREDITS_STATUS[0], sizeof(ixD2F1_PCIE_TX_CREDITS_STATUS)/sizeof(ixD2F1_PCIE_TX_CREDITS_STATUS[0]), 0, 0 },
+	{ "ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD", REG_SMC, 0x37, &ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD[0], sizeof(ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD)/sizeof(ixD2F1_PCIE_TX_CREDITS_FCU_THRESHOLD[0]), 0, 0 },
+	{ "mmPCIE_WRAPPER1_C_PCIE_INDEX", REG_MMIO, 0x38, NULL, 0, 0, 0 },
+	{ "mmC_PCIE_P_INDEX", REG_MMIO, 0x38, &mmC_PCIE_P_INDEX[0], sizeof(mmC_PCIE_P_INDEX)/sizeof(mmC_PCIE_P_INDEX[0]), 0, 0 },
+	{ "mmPCIE_WRAPPER1_C_PCIE_DATA", REG_MMIO, 0x39, NULL, 0, 0, 0 },
+	{ "mmC_PCIE_P_DATA", REG_MMIO, 0x39, &mmC_PCIE_P_DATA[0], sizeof(mmC_PCIE_P_DATA)/sizeof(mmC_PCIE_P_DATA[0]), 0, 0 },
+	{ "mmRFE_SNOOP_RST", REG_MMIO, 0x3c, NULL, 0, 0, 0 },
+	{ "mmBASE_ADDR_1", REG_MMIO, 0x4, &mmBASE_ADDR_1[0], sizeof(mmBASE_ADDR_1)/sizeof(mmBASE_ADDR_1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_MMIO, 0x40, &mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(mmPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_VENDOR_ID", REG_SMC, 0x4000000, &ixD2F3_VENDOR_ID[0], sizeof(ixD2F3_VENDOR_ID)/sizeof(ixD2F3_VENDOR_ID[0]), 0, 0 },
+	{ "ixD2F3_COMMAND", REG_SMC, 0x4000001, &ixD2F3_COMMAND[0], sizeof(ixD2F3_COMMAND)/sizeof(ixD2F3_COMMAND[0]), 0, 0 },
+	{ "ixD2F3_STATUS", REG_SMC, 0x4000001, &ixD2F3_STATUS[0], sizeof(ixD2F3_STATUS)/sizeof(ixD2F3_STATUS[0]), 0, 0 },
+	{ "ixD2F3_PROG_INTERFACE", REG_SMC, 0x4000002, &ixD2F3_PROG_INTERFACE[0], sizeof(ixD2F3_PROG_INTERFACE)/sizeof(ixD2F3_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD2F3_REVISION_ID", REG_SMC, 0x4000002, &ixD2F3_REVISION_ID[0], sizeof(ixD2F3_REVISION_ID)/sizeof(ixD2F3_REVISION_ID[0]), 0, 0 },
+	{ "ixD2F3_BASE_CLASS", REG_SMC, 0x4000002, &ixD2F3_BASE_CLASS[0], sizeof(ixD2F3_BASE_CLASS)/sizeof(ixD2F3_BASE_CLASS[0]), 0, 0 },
+	{ "ixD2F3_SUB_CLASS", REG_SMC, 0x4000002, &ixD2F3_SUB_CLASS[0], sizeof(ixD2F3_SUB_CLASS)/sizeof(ixD2F3_SUB_CLASS[0]), 0, 0 },
+	{ "ixD2F3_CACHE_LINE", REG_SMC, 0x4000003, &ixD2F3_CACHE_LINE[0], sizeof(ixD2F3_CACHE_LINE)/sizeof(ixD2F3_CACHE_LINE[0]), 0, 0 },
+	{ "ixD2F3_LATENCY", REG_SMC, 0x4000003, &ixD2F3_LATENCY[0], sizeof(ixD2F3_LATENCY)/sizeof(ixD2F3_LATENCY[0]), 0, 0 },
+	{ "ixD2F3_HEADER", REG_SMC, 0x4000003, &ixD2F3_HEADER[0], sizeof(ixD2F3_HEADER)/sizeof(ixD2F3_HEADER[0]), 0, 0 },
+	{ "ixD2F3_BIST", REG_SMC, 0x4000003, &ixD2F3_BIST[0], sizeof(ixD2F3_BIST)/sizeof(ixD2F3_BIST[0]), 0, 0 },
+	{ "ixD2F3_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x4000006, &ixD2F3_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F3_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F3_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD2F3_SECONDARY_STATUS", REG_SMC, 0x4000007, &ixD2F3_SECONDARY_STATUS[0], sizeof(ixD2F3_SECONDARY_STATUS)/sizeof(ixD2F3_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD2F3_IO_BASE_LIMIT", REG_SMC, 0x4000007, &ixD2F3_IO_BASE_LIMIT[0], sizeof(ixD2F3_IO_BASE_LIMIT)/sizeof(ixD2F3_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F3_MEM_BASE_LIMIT", REG_SMC, 0x4000008, &ixD2F3_MEM_BASE_LIMIT[0], sizeof(ixD2F3_MEM_BASE_LIMIT)/sizeof(ixD2F3_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F3_PREF_BASE_LIMIT", REG_SMC, 0x4000009, &ixD2F3_PREF_BASE_LIMIT[0], sizeof(ixD2F3_PREF_BASE_LIMIT)/sizeof(ixD2F3_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F3_PREF_BASE_UPPER", REG_SMC, 0x400000a, &ixD2F3_PREF_BASE_UPPER[0], sizeof(ixD2F3_PREF_BASE_UPPER)/sizeof(ixD2F3_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD2F3_PREF_LIMIT_UPPER", REG_SMC, 0x400000b, &ixD2F3_PREF_LIMIT_UPPER[0], sizeof(ixD2F3_PREF_LIMIT_UPPER)/sizeof(ixD2F3_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD2F3_IO_BASE_LIMIT_HI", REG_SMC, 0x400000c, &ixD2F3_IO_BASE_LIMIT_HI[0], sizeof(ixD2F3_IO_BASE_LIMIT_HI)/sizeof(ixD2F3_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD2F3_CAP_PTR", REG_SMC, 0x400000d, &ixD2F3_CAP_PTR[0], sizeof(ixD2F3_CAP_PTR)/sizeof(ixD2F3_CAP_PTR[0]), 0, 0 },
+	{ "ixD2F3_IRQ_BRIDGE_CNTL", REG_SMC, 0x400000f, &ixD2F3_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F3_IRQ_BRIDGE_CNTL)/sizeof(ixD2F3_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F3_INTERRUPT_LINE", REG_SMC, 0x400000f, &ixD2F3_INTERRUPT_LINE[0], sizeof(ixD2F3_INTERRUPT_LINE)/sizeof(ixD2F3_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD2F3_INTERRUPT_PIN", REG_SMC, 0x400000f, &ixD2F3_INTERRUPT_PIN[0], sizeof(ixD2F3_INTERRUPT_PIN)/sizeof(ixD2F3_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD2F3_EXT_BRIDGE_CNTL", REG_SMC, 0x4000010, &ixD2F3_EXT_BRIDGE_CNTL[0], sizeof(ixD2F3_EXT_BRIDGE_CNTL)/sizeof(ixD2F3_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PMI_CAP_LIST", REG_SMC, 0x4000014, &ixD2F3_PMI_CAP_LIST[0], sizeof(ixD2F3_PMI_CAP_LIST)/sizeof(ixD2F3_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PMI_CAP", REG_SMC, 0x4000014, &ixD2F3_PMI_CAP[0], sizeof(ixD2F3_PMI_CAP)/sizeof(ixD2F3_PMI_CAP[0]), 0, 0 },
+	{ "ixD2F3_PMI_STATUS_CNTL", REG_SMC, 0x4000015, &ixD2F3_PMI_STATUS_CNTL[0], sizeof(ixD2F3_PMI_STATUS_CNTL)/sizeof(ixD2F3_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_CAP_LIST", REG_SMC, 0x4000016, &ixD2F3_PCIE_CAP_LIST[0], sizeof(ixD2F3_PCIE_CAP_LIST)/sizeof(ixD2F3_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PCIE_CAP", REG_SMC, 0x4000016, &ixD2F3_PCIE_CAP[0], sizeof(ixD2F3_PCIE_CAP)/sizeof(ixD2F3_PCIE_CAP[0]), 0, 0 },
+	{ "ixD2F3_DEVICE_CAP", REG_SMC, 0x4000017, &ixD2F3_DEVICE_CAP[0], sizeof(ixD2F3_DEVICE_CAP)/sizeof(ixD2F3_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD2F3_DEVICE_STATUS", REG_SMC, 0x4000018, &ixD2F3_DEVICE_STATUS[0], sizeof(ixD2F3_DEVICE_STATUS)/sizeof(ixD2F3_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD2F3_DEVICE_CNTL", REG_SMC, 0x4000018, &ixD2F3_DEVICE_CNTL[0], sizeof(ixD2F3_DEVICE_CNTL)/sizeof(ixD2F3_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD2F3_LINK_CAP", REG_SMC, 0x4000019, &ixD2F3_LINK_CAP[0], sizeof(ixD2F3_LINK_CAP)/sizeof(ixD2F3_LINK_CAP[0]), 0, 0 },
+	{ "ixD2F3_LINK_STATUS", REG_SMC, 0x400001a, &ixD2F3_LINK_STATUS[0], sizeof(ixD2F3_LINK_STATUS)/sizeof(ixD2F3_LINK_STATUS[0]), 0, 0 },
+	{ "ixD2F3_LINK_CNTL", REG_SMC, 0x400001a, &ixD2F3_LINK_CNTL[0], sizeof(ixD2F3_LINK_CNTL)/sizeof(ixD2F3_LINK_CNTL[0]), 0, 0 },
+	{ "ixD2F3_SLOT_CAP", REG_SMC, 0x400001b, &ixD2F3_SLOT_CAP[0], sizeof(ixD2F3_SLOT_CAP)/sizeof(ixD2F3_SLOT_CAP[0]), 0, 0 },
+	{ "ixD2F3_SLOT_STATUS", REG_SMC, 0x400001c, &ixD2F3_SLOT_STATUS[0], sizeof(ixD2F3_SLOT_STATUS)/sizeof(ixD2F3_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD2F3_SLOT_CNTL", REG_SMC, 0x400001c, &ixD2F3_SLOT_CNTL[0], sizeof(ixD2F3_SLOT_CNTL)/sizeof(ixD2F3_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD2F3_ROOT_CNTL", REG_SMC, 0x400001d, &ixD2F3_ROOT_CNTL[0], sizeof(ixD2F3_ROOT_CNTL)/sizeof(ixD2F3_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD2F3_ROOT_CAP", REG_SMC, 0x400001d, &ixD2F3_ROOT_CAP[0], sizeof(ixD2F3_ROOT_CAP)/sizeof(ixD2F3_ROOT_CAP[0]), 0, 0 },
+	{ "ixD2F3_ROOT_STATUS", REG_SMC, 0x400001e, &ixD2F3_ROOT_STATUS[0], sizeof(ixD2F3_ROOT_STATUS)/sizeof(ixD2F3_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD2F3_DEVICE_CAP2", REG_SMC, 0x400001f, &ixD2F3_DEVICE_CAP2[0], sizeof(ixD2F3_DEVICE_CAP2)/sizeof(ixD2F3_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD2F3_DEVICE_STATUS2", REG_SMC, 0x4000020, &ixD2F3_DEVICE_STATUS2[0], sizeof(ixD2F3_DEVICE_STATUS2)/sizeof(ixD2F3_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD2F3_DEVICE_CNTL2", REG_SMC, 0x4000020, &ixD2F3_DEVICE_CNTL2[0], sizeof(ixD2F3_DEVICE_CNTL2)/sizeof(ixD2F3_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD2F3_LINK_CAP2", REG_SMC, 0x4000021, &ixD2F3_LINK_CAP2[0], sizeof(ixD2F3_LINK_CAP2)/sizeof(ixD2F3_LINK_CAP2[0]), 0, 0 },
+	{ "ixD2F3_LINK_STATUS2", REG_SMC, 0x4000022, &ixD2F3_LINK_STATUS2[0], sizeof(ixD2F3_LINK_STATUS2)/sizeof(ixD2F3_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD2F3_LINK_CNTL2", REG_SMC, 0x4000022, &ixD2F3_LINK_CNTL2[0], sizeof(ixD2F3_LINK_CNTL2)/sizeof(ixD2F3_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD2F3_SLOT_CAP2", REG_SMC, 0x4000023, &ixD2F3_SLOT_CAP2[0], sizeof(ixD2F3_SLOT_CAP2)/sizeof(ixD2F3_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD2F3_SLOT_STATUS2", REG_SMC, 0x4000024, &ixD2F3_SLOT_STATUS2[0], sizeof(ixD2F3_SLOT_STATUS2)/sizeof(ixD2F3_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD2F3_SLOT_CNTL2", REG_SMC, 0x4000024, &ixD2F3_SLOT_CNTL2[0], sizeof(ixD2F3_SLOT_CNTL2)/sizeof(ixD2F3_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD2F3_MSI_CAP_LIST", REG_SMC, 0x4000028, &ixD2F3_MSI_CAP_LIST[0], sizeof(ixD2F3_MSI_CAP_LIST)/sizeof(ixD2F3_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_MSI_MSG_ADDR_LO", REG_SMC, 0x4000029, &ixD2F3_MSI_MSG_ADDR_LO[0], sizeof(ixD2F3_MSI_MSG_ADDR_LO)/sizeof(ixD2F3_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F3_MSI_MSG_ADDR_HI", REG_SMC, 0x400002a, &ixD2F3_MSI_MSG_ADDR_HI[0], sizeof(ixD2F3_MSI_MSG_ADDR_HI)/sizeof(ixD2F3_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F3_MSI_MSG_DATA", REG_SMC, 0x400002a, &ixD2F3_MSI_MSG_DATA[0], sizeof(ixD2F3_MSI_MSG_DATA)/sizeof(ixD2F3_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD2F3_MSI_MSG_DATA_64", REG_SMC, 0x400002b, &ixD2F3_MSI_MSG_DATA_64[0], sizeof(ixD2F3_MSI_MSG_DATA_64)/sizeof(ixD2F3_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD2F3_SSID_CAP_LIST", REG_SMC, 0x4000030, &ixD2F3_SSID_CAP_LIST[0], sizeof(ixD2F3_SSID_CAP_LIST)/sizeof(ixD2F3_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_SSID_CAP", REG_SMC, 0x4000031, &ixD2F3_SSID_CAP[0], sizeof(ixD2F3_SSID_CAP)/sizeof(ixD2F3_SSID_CAP[0]), 0, 0 },
+	{ "ixD2F3_MSI_MAP_CAP_LIST", REG_SMC, 0x4000032, &ixD2F3_MSI_MAP_CAP_LIST[0], sizeof(ixD2F3_MSI_MAP_CAP_LIST)/sizeof(ixD2F3_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_MSI_MAP_CAP", REG_SMC, 0x4000032, &ixD2F3_MSI_MAP_CAP[0], sizeof(ixD2F3_MSI_MAP_CAP)/sizeof(ixD2F3_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD2F3_MSI_MAP_ADDR_LO", REG_SMC, 0x4000033, &ixD2F3_MSI_MAP_ADDR_LO[0], sizeof(ixD2F3_MSI_MAP_ADDR_LO)/sizeof(ixD2F3_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F3_MSI_MAP_ADDR_HI", REG_SMC, 0x4000034, &ixD2F3_MSI_MAP_ADDR_HI[0], sizeof(ixD2F3_MSI_MAP_ADDR_HI)/sizeof(ixD2F3_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F3_PCIE_PORT_INDEX", REG_SMC, 0x4000038, &ixD2F3_PCIE_PORT_INDEX[0], sizeof(ixD2F3_PCIE_PORT_INDEX)/sizeof(ixD2F3_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD2F3_PCIE_PORT_DATA", REG_SMC, 0x4000039, &ixD2F3_PCIE_PORT_DATA[0], sizeof(ixD2F3_PCIE_PORT_DATA)/sizeof(ixD2F3_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x4000040, &ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x4000041, &ixD2F3_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x4000042, &ixD2F3_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x4000043, &ixD2F3_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F3_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x4000044, &ixD2F3_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x4000045, &ixD2F3_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F3_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F3_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x4000046, &ixD2F3_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F3_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F3_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD2F3_PCIE_PORT_VC_STATUS", REG_SMC, 0x4000047, &ixD2F3_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F3_PCIE_PORT_VC_STATUS)/sizeof(ixD2F3_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD2F3_PCIE_PORT_VC_CNTL", REG_SMC, 0x4000047, &ixD2F3_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F3_PCIE_PORT_VC_CNTL)/sizeof(ixD2F3_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x4000048, &ixD2F3_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F3_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F3_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x4000049, &ixD2F3_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F3_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F3_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x400004a, &ixD2F3_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F3_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F3_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x400004b, &ixD2F3_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F3_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F3_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x400004c, &ixD2F3_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F3_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F3_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x400004d, &ixD2F3_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F3_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F3_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x4000050, &ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x4000051, &ixD2F3_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x4000052, &ixD2F3_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F3_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x4000054, &ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x4000055, &ixD2F3_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F3_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F3_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F3_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x4000056, &ixD2F3_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F3_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F3_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F3_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x4000057, &ixD2F3_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F3_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F3_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD2F3_PCIE_CORR_ERR_STATUS", REG_SMC, 0x4000058, &ixD2F3_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F3_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F3_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F3_PCIE_CORR_ERR_MASK", REG_SMC, 0x4000059, &ixD2F3_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F3_PCIE_CORR_ERR_MASK)/sizeof(ixD2F3_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F3_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x400005a, &ixD2F3_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F3_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F3_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_HDR_LOG0", REG_SMC, 0x400005b, &ixD2F3_PCIE_HDR_LOG0[0], sizeof(ixD2F3_PCIE_HDR_LOG0)/sizeof(ixD2F3_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD2F3_PCIE_HDR_LOG1", REG_SMC, 0x400005c, &ixD2F3_PCIE_HDR_LOG1[0], sizeof(ixD2F3_PCIE_HDR_LOG1)/sizeof(ixD2F3_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_HDR_LOG2", REG_SMC, 0x400005d, &ixD2F3_PCIE_HDR_LOG2[0], sizeof(ixD2F3_PCIE_HDR_LOG2)/sizeof(ixD2F3_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD2F3_PCIE_HDR_LOG3", REG_SMC, 0x400005e, &ixD2F3_PCIE_HDR_LOG3[0], sizeof(ixD2F3_PCIE_HDR_LOG3)/sizeof(ixD2F3_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD2F3_PCIE_ROOT_ERR_CMD", REG_SMC, 0x400005f, &ixD2F3_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F3_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F3_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD2F3_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x4000060, &ixD2F3_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F3_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F3_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F3_PCIE_ERR_SRC_ID", REG_SMC, 0x4000061, &ixD2F3_PCIE_ERR_SRC_ID[0], sizeof(ixD2F3_PCIE_ERR_SRC_ID)/sizeof(ixD2F3_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD2F3_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x4000062, &ixD2F3_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD2F3_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x4000063, &ixD2F3_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x4000064, &ixD2F3_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD2F3_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x4000065, &ixD2F3_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F3_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x400009c, &ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LINK_CNTL3", REG_SMC, 0x400009d, &ixD2F3_PCIE_LINK_CNTL3[0], sizeof(ixD2F3_PCIE_LINK_CNTL3)/sizeof(ixD2F3_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x400009e, &ixD2F3_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F3_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F3_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x400009f, &ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x40000a0, &ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x40000a1, &ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x40000a2, &ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x40000a3, &ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x40000a4, &ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x40000a5, &ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x40000a6, &ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F3_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x40000a8, &ixD2F3_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PCIE_ACS_CNTL", REG_SMC, 0x40000a9, &ixD2F3_PCIE_ACS_CNTL[0], sizeof(ixD2F3_PCIE_ACS_CNTL)/sizeof(ixD2F3_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_ACS_CAP", REG_SMC, 0x40000a9, &ixD2F3_PCIE_ACS_CAP[0], sizeof(ixD2F3_PCIE_ACS_CAP)/sizeof(ixD2F3_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x40000bc, &ixD2F3_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F3_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F3_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_CNTL", REG_SMC, 0x40000bd, &ixD2F3_PCIE_MC_CNTL[0], sizeof(ixD2F3_PCIE_MC_CNTL)/sizeof(ixD2F3_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_CAP", REG_SMC, 0x40000bd, &ixD2F3_PCIE_MC_CAP[0], sizeof(ixD2F3_PCIE_MC_CAP)/sizeof(ixD2F3_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_ADDR0", REG_SMC, 0x40000be, &ixD2F3_PCIE_MC_ADDR0[0], sizeof(ixD2F3_PCIE_MC_ADDR0)/sizeof(ixD2F3_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_ADDR1", REG_SMC, 0x40000bf, &ixD2F3_PCIE_MC_ADDR1[0], sizeof(ixD2F3_PCIE_MC_ADDR1)/sizeof(ixD2F3_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_RCV0", REG_SMC, 0x40000c0, &ixD2F3_PCIE_MC_RCV0[0], sizeof(ixD2F3_PCIE_MC_RCV0)/sizeof(ixD2F3_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_RCV1", REG_SMC, 0x40000c1, &ixD2F3_PCIE_MC_RCV1[0], sizeof(ixD2F3_PCIE_MC_RCV1)/sizeof(ixD2F3_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x40000c2, &ixD2F3_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F3_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F3_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x40000c3, &ixD2F3_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F3_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F3_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x40000c4, &ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x40000c5, &ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F3_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x40000c6, &ixD2F3_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F3_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F3_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD2F3_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x40000c7, &ixD2F3_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F3_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F3_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC_HDR", REG_MMIO, 0x41, &mmPCIE_VENDOR_SPECIFIC_HDR[0], sizeof(mmPCIE_VENDOR_SPECIFIC_HDR)/sizeof(mmPCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC1", REG_MMIO, 0x42, &mmPCIE_VENDOR_SPECIFIC1[0], sizeof(mmPCIE_VENDOR_SPECIFIC1)/sizeof(mmPCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "mmPCIE_VENDOR_SPECIFIC2", REG_MMIO, 0x43, &mmPCIE_VENDOR_SPECIFIC2[0], sizeof(mmPCIE_VENDOR_SPECIFIC2)/sizeof(mmPCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "mmPCIE_VC_ENH_CAP_LIST", REG_MMIO, 0x44, &mmPCIE_VC_ENH_CAP_LIST[0], sizeof(mmPCIE_VC_ENH_CAP_LIST)/sizeof(mmPCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CAP_REG1", REG_MMIO, 0x45, &mmPCIE_PORT_VC_CAP_REG1[0], sizeof(mmPCIE_PORT_VC_CAP_REG1)/sizeof(mmPCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CAP_REG2", REG_MMIO, 0x46, &mmPCIE_PORT_VC_CAP_REG2[0], sizeof(mmPCIE_PORT_VC_CAP_REG2)/sizeof(mmPCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_STATUS", REG_MMIO, 0x47, &mmPCIE_PORT_VC_STATUS[0], sizeof(mmPCIE_PORT_VC_STATUS)/sizeof(mmPCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "mmPCIE_PORT_VC_CNTL", REG_MMIO, 0x47, &mmPCIE_PORT_VC_CNTL[0], sizeof(mmPCIE_PORT_VC_CNTL)/sizeof(mmPCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_CAP", REG_MMIO, 0x48, &mmPCIE_VC0_RESOURCE_CAP[0], sizeof(mmPCIE_VC0_RESOURCE_CAP)/sizeof(mmPCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_CNTL", REG_MMIO, 0x49, &mmPCIE_VC0_RESOURCE_CNTL[0], sizeof(mmPCIE_VC0_RESOURCE_CNTL)/sizeof(mmPCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC0_RESOURCE_STATUS", REG_MMIO, 0x4a, &mmPCIE_VC0_RESOURCE_STATUS[0], sizeof(mmPCIE_VC0_RESOURCE_STATUS)/sizeof(mmPCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_CAP", REG_MMIO, 0x4b, &mmPCIE_VC1_RESOURCE_CAP[0], sizeof(mmPCIE_VC1_RESOURCE_CAP)/sizeof(mmPCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_CNTL", REG_MMIO, 0x4c, &mmPCIE_VC1_RESOURCE_CNTL[0], sizeof(mmPCIE_VC1_RESOURCE_CNTL)/sizeof(mmPCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmPCIE_VC1_RESOURCE_STATUS", REG_MMIO, 0x4d, &mmPCIE_VC1_RESOURCE_STATUS[0], sizeof(mmPCIE_VC1_RESOURCE_STATUS)/sizeof(mmPCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "mmBASE_ADDR_2", REG_MMIO, 0x5, &mmBASE_ADDR_2[0], sizeof(mmBASE_ADDR_2)/sizeof(mmBASE_ADDR_2[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_MMIO, 0x50, &mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(mmPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_P_PORT_LANE_STATUS", REG_SMC, 0x50, &ixD2F1_PCIE_P_PORT_LANE_STATUS[0], sizeof(ixD2F1_PCIE_P_PORT_LANE_STATUS)/sizeof(ixD2F1_PCIE_P_PORT_LANE_STATUS[0]), 0, 0 },
+	{ "ixD2F4_VENDOR_ID", REG_SMC, 0x5000000, &ixD2F4_VENDOR_ID[0], sizeof(ixD2F4_VENDOR_ID)/sizeof(ixD2F4_VENDOR_ID[0]), 0, 0 },
+	{ "ixD2F4_COMMAND", REG_SMC, 0x5000001, &ixD2F4_COMMAND[0], sizeof(ixD2F4_COMMAND)/sizeof(ixD2F4_COMMAND[0]), 0, 0 },
+	{ "ixD2F4_STATUS", REG_SMC, 0x5000001, &ixD2F4_STATUS[0], sizeof(ixD2F4_STATUS)/sizeof(ixD2F4_STATUS[0]), 0, 0 },
+	{ "ixD2F4_PROG_INTERFACE", REG_SMC, 0x5000002, &ixD2F4_PROG_INTERFACE[0], sizeof(ixD2F4_PROG_INTERFACE)/sizeof(ixD2F4_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD2F4_REVISION_ID", REG_SMC, 0x5000002, &ixD2F4_REVISION_ID[0], sizeof(ixD2F4_REVISION_ID)/sizeof(ixD2F4_REVISION_ID[0]), 0, 0 },
+	{ "ixD2F4_BASE_CLASS", REG_SMC, 0x5000002, &ixD2F4_BASE_CLASS[0], sizeof(ixD2F4_BASE_CLASS)/sizeof(ixD2F4_BASE_CLASS[0]), 0, 0 },
+	{ "ixD2F4_SUB_CLASS", REG_SMC, 0x5000002, &ixD2F4_SUB_CLASS[0], sizeof(ixD2F4_SUB_CLASS)/sizeof(ixD2F4_SUB_CLASS[0]), 0, 0 },
+	{ "ixD2F4_CACHE_LINE", REG_SMC, 0x5000003, &ixD2F4_CACHE_LINE[0], sizeof(ixD2F4_CACHE_LINE)/sizeof(ixD2F4_CACHE_LINE[0]), 0, 0 },
+	{ "ixD2F4_LATENCY", REG_SMC, 0x5000003, &ixD2F4_LATENCY[0], sizeof(ixD2F4_LATENCY)/sizeof(ixD2F4_LATENCY[0]), 0, 0 },
+	{ "ixD2F4_HEADER", REG_SMC, 0x5000003, &ixD2F4_HEADER[0], sizeof(ixD2F4_HEADER)/sizeof(ixD2F4_HEADER[0]), 0, 0 },
+	{ "ixD2F4_BIST", REG_SMC, 0x5000003, &ixD2F4_BIST[0], sizeof(ixD2F4_BIST)/sizeof(ixD2F4_BIST[0]), 0, 0 },
+	{ "ixD2F4_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x5000006, &ixD2F4_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F4_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F4_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD2F4_SECONDARY_STATUS", REG_SMC, 0x5000007, &ixD2F4_SECONDARY_STATUS[0], sizeof(ixD2F4_SECONDARY_STATUS)/sizeof(ixD2F4_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD2F4_IO_BASE_LIMIT", REG_SMC, 0x5000007, &ixD2F4_IO_BASE_LIMIT[0], sizeof(ixD2F4_IO_BASE_LIMIT)/sizeof(ixD2F4_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F4_MEM_BASE_LIMIT", REG_SMC, 0x5000008, &ixD2F4_MEM_BASE_LIMIT[0], sizeof(ixD2F4_MEM_BASE_LIMIT)/sizeof(ixD2F4_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F4_PREF_BASE_LIMIT", REG_SMC, 0x5000009, &ixD2F4_PREF_BASE_LIMIT[0], sizeof(ixD2F4_PREF_BASE_LIMIT)/sizeof(ixD2F4_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F4_PREF_BASE_UPPER", REG_SMC, 0x500000a, &ixD2F4_PREF_BASE_UPPER[0], sizeof(ixD2F4_PREF_BASE_UPPER)/sizeof(ixD2F4_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD2F4_PREF_LIMIT_UPPER", REG_SMC, 0x500000b, &ixD2F4_PREF_LIMIT_UPPER[0], sizeof(ixD2F4_PREF_LIMIT_UPPER)/sizeof(ixD2F4_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD2F4_IO_BASE_LIMIT_HI", REG_SMC, 0x500000c, &ixD2F4_IO_BASE_LIMIT_HI[0], sizeof(ixD2F4_IO_BASE_LIMIT_HI)/sizeof(ixD2F4_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD2F4_CAP_PTR", REG_SMC, 0x500000d, &ixD2F4_CAP_PTR[0], sizeof(ixD2F4_CAP_PTR)/sizeof(ixD2F4_CAP_PTR[0]), 0, 0 },
+	{ "ixD2F4_IRQ_BRIDGE_CNTL", REG_SMC, 0x500000f, &ixD2F4_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F4_IRQ_BRIDGE_CNTL)/sizeof(ixD2F4_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F4_INTERRUPT_LINE", REG_SMC, 0x500000f, &ixD2F4_INTERRUPT_LINE[0], sizeof(ixD2F4_INTERRUPT_LINE)/sizeof(ixD2F4_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD2F4_INTERRUPT_PIN", REG_SMC, 0x500000f, &ixD2F4_INTERRUPT_PIN[0], sizeof(ixD2F4_INTERRUPT_PIN)/sizeof(ixD2F4_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD2F4_EXT_BRIDGE_CNTL", REG_SMC, 0x5000010, &ixD2F4_EXT_BRIDGE_CNTL[0], sizeof(ixD2F4_EXT_BRIDGE_CNTL)/sizeof(ixD2F4_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PMI_CAP_LIST", REG_SMC, 0x5000014, &ixD2F4_PMI_CAP_LIST[0], sizeof(ixD2F4_PMI_CAP_LIST)/sizeof(ixD2F4_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PMI_CAP", REG_SMC, 0x5000014, &ixD2F4_PMI_CAP[0], sizeof(ixD2F4_PMI_CAP)/sizeof(ixD2F4_PMI_CAP[0]), 0, 0 },
+	{ "ixD2F4_PMI_STATUS_CNTL", REG_SMC, 0x5000015, &ixD2F4_PMI_STATUS_CNTL[0], sizeof(ixD2F4_PMI_STATUS_CNTL)/sizeof(ixD2F4_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_CAP_LIST", REG_SMC, 0x5000016, &ixD2F4_PCIE_CAP_LIST[0], sizeof(ixD2F4_PCIE_CAP_LIST)/sizeof(ixD2F4_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PCIE_CAP", REG_SMC, 0x5000016, &ixD2F4_PCIE_CAP[0], sizeof(ixD2F4_PCIE_CAP)/sizeof(ixD2F4_PCIE_CAP[0]), 0, 0 },
+	{ "ixD2F4_DEVICE_CAP", REG_SMC, 0x5000017, &ixD2F4_DEVICE_CAP[0], sizeof(ixD2F4_DEVICE_CAP)/sizeof(ixD2F4_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD2F4_DEVICE_STATUS", REG_SMC, 0x5000018, &ixD2F4_DEVICE_STATUS[0], sizeof(ixD2F4_DEVICE_STATUS)/sizeof(ixD2F4_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD2F4_DEVICE_CNTL", REG_SMC, 0x5000018, &ixD2F4_DEVICE_CNTL[0], sizeof(ixD2F4_DEVICE_CNTL)/sizeof(ixD2F4_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD2F4_LINK_CAP", REG_SMC, 0x5000019, &ixD2F4_LINK_CAP[0], sizeof(ixD2F4_LINK_CAP)/sizeof(ixD2F4_LINK_CAP[0]), 0, 0 },
+	{ "ixD2F4_LINK_STATUS", REG_SMC, 0x500001a, &ixD2F4_LINK_STATUS[0], sizeof(ixD2F4_LINK_STATUS)/sizeof(ixD2F4_LINK_STATUS[0]), 0, 0 },
+	{ "ixD2F4_LINK_CNTL", REG_SMC, 0x500001a, &ixD2F4_LINK_CNTL[0], sizeof(ixD2F4_LINK_CNTL)/sizeof(ixD2F4_LINK_CNTL[0]), 0, 0 },
+	{ "ixD2F4_SLOT_CAP", REG_SMC, 0x500001b, &ixD2F4_SLOT_CAP[0], sizeof(ixD2F4_SLOT_CAP)/sizeof(ixD2F4_SLOT_CAP[0]), 0, 0 },
+	{ "ixD2F4_SLOT_STATUS", REG_SMC, 0x500001c, &ixD2F4_SLOT_STATUS[0], sizeof(ixD2F4_SLOT_STATUS)/sizeof(ixD2F4_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD2F4_SLOT_CNTL", REG_SMC, 0x500001c, &ixD2F4_SLOT_CNTL[0], sizeof(ixD2F4_SLOT_CNTL)/sizeof(ixD2F4_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD2F4_ROOT_CNTL", REG_SMC, 0x500001d, &ixD2F4_ROOT_CNTL[0], sizeof(ixD2F4_ROOT_CNTL)/sizeof(ixD2F4_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD2F4_ROOT_CAP", REG_SMC, 0x500001d, &ixD2F4_ROOT_CAP[0], sizeof(ixD2F4_ROOT_CAP)/sizeof(ixD2F4_ROOT_CAP[0]), 0, 0 },
+	{ "ixD2F4_ROOT_STATUS", REG_SMC, 0x500001e, &ixD2F4_ROOT_STATUS[0], sizeof(ixD2F4_ROOT_STATUS)/sizeof(ixD2F4_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD2F4_DEVICE_CAP2", REG_SMC, 0x500001f, &ixD2F4_DEVICE_CAP2[0], sizeof(ixD2F4_DEVICE_CAP2)/sizeof(ixD2F4_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD2F4_DEVICE_STATUS2", REG_SMC, 0x5000020, &ixD2F4_DEVICE_STATUS2[0], sizeof(ixD2F4_DEVICE_STATUS2)/sizeof(ixD2F4_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD2F4_DEVICE_CNTL2", REG_SMC, 0x5000020, &ixD2F4_DEVICE_CNTL2[0], sizeof(ixD2F4_DEVICE_CNTL2)/sizeof(ixD2F4_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD2F4_LINK_CAP2", REG_SMC, 0x5000021, &ixD2F4_LINK_CAP2[0], sizeof(ixD2F4_LINK_CAP2)/sizeof(ixD2F4_LINK_CAP2[0]), 0, 0 },
+	{ "ixD2F4_LINK_STATUS2", REG_SMC, 0x5000022, &ixD2F4_LINK_STATUS2[0], sizeof(ixD2F4_LINK_STATUS2)/sizeof(ixD2F4_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD2F4_LINK_CNTL2", REG_SMC, 0x5000022, &ixD2F4_LINK_CNTL2[0], sizeof(ixD2F4_LINK_CNTL2)/sizeof(ixD2F4_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD2F4_SLOT_CAP2", REG_SMC, 0x5000023, &ixD2F4_SLOT_CAP2[0], sizeof(ixD2F4_SLOT_CAP2)/sizeof(ixD2F4_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD2F4_SLOT_STATUS2", REG_SMC, 0x5000024, &ixD2F4_SLOT_STATUS2[0], sizeof(ixD2F4_SLOT_STATUS2)/sizeof(ixD2F4_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD2F4_SLOT_CNTL2", REG_SMC, 0x5000024, &ixD2F4_SLOT_CNTL2[0], sizeof(ixD2F4_SLOT_CNTL2)/sizeof(ixD2F4_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD2F4_MSI_CAP_LIST", REG_SMC, 0x5000028, &ixD2F4_MSI_CAP_LIST[0], sizeof(ixD2F4_MSI_CAP_LIST)/sizeof(ixD2F4_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_MSI_MSG_ADDR_LO", REG_SMC, 0x5000029, &ixD2F4_MSI_MSG_ADDR_LO[0], sizeof(ixD2F4_MSI_MSG_ADDR_LO)/sizeof(ixD2F4_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F4_MSI_MSG_ADDR_HI", REG_SMC, 0x500002a, &ixD2F4_MSI_MSG_ADDR_HI[0], sizeof(ixD2F4_MSI_MSG_ADDR_HI)/sizeof(ixD2F4_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F4_MSI_MSG_DATA", REG_SMC, 0x500002a, &ixD2F4_MSI_MSG_DATA[0], sizeof(ixD2F4_MSI_MSG_DATA)/sizeof(ixD2F4_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD2F4_MSI_MSG_DATA_64", REG_SMC, 0x500002b, &ixD2F4_MSI_MSG_DATA_64[0], sizeof(ixD2F4_MSI_MSG_DATA_64)/sizeof(ixD2F4_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD2F4_SSID_CAP_LIST", REG_SMC, 0x5000030, &ixD2F4_SSID_CAP_LIST[0], sizeof(ixD2F4_SSID_CAP_LIST)/sizeof(ixD2F4_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_SSID_CAP", REG_SMC, 0x5000031, &ixD2F4_SSID_CAP[0], sizeof(ixD2F4_SSID_CAP)/sizeof(ixD2F4_SSID_CAP[0]), 0, 0 },
+	{ "ixD2F4_MSI_MAP_CAP_LIST", REG_SMC, 0x5000032, &ixD2F4_MSI_MAP_CAP_LIST[0], sizeof(ixD2F4_MSI_MAP_CAP_LIST)/sizeof(ixD2F4_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_MSI_MAP_CAP", REG_SMC, 0x5000032, &ixD2F4_MSI_MAP_CAP[0], sizeof(ixD2F4_MSI_MAP_CAP)/sizeof(ixD2F4_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD2F4_MSI_MAP_ADDR_LO", REG_SMC, 0x5000033, &ixD2F4_MSI_MAP_ADDR_LO[0], sizeof(ixD2F4_MSI_MAP_ADDR_LO)/sizeof(ixD2F4_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F4_MSI_MAP_ADDR_HI", REG_SMC, 0x5000034, &ixD2F4_MSI_MAP_ADDR_HI[0], sizeof(ixD2F4_MSI_MAP_ADDR_HI)/sizeof(ixD2F4_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F4_PCIE_PORT_INDEX", REG_SMC, 0x5000038, &ixD2F4_PCIE_PORT_INDEX[0], sizeof(ixD2F4_PCIE_PORT_INDEX)/sizeof(ixD2F4_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD2F4_PCIE_PORT_DATA", REG_SMC, 0x5000039, &ixD2F4_PCIE_PORT_DATA[0], sizeof(ixD2F4_PCIE_PORT_DATA)/sizeof(ixD2F4_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x5000040, &ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x5000041, &ixD2F4_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x5000042, &ixD2F4_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x5000043, &ixD2F4_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F4_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x5000044, &ixD2F4_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x5000045, &ixD2F4_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F4_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F4_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x5000046, &ixD2F4_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F4_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F4_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD2F4_PCIE_PORT_VC_STATUS", REG_SMC, 0x5000047, &ixD2F4_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F4_PCIE_PORT_VC_STATUS)/sizeof(ixD2F4_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD2F4_PCIE_PORT_VC_CNTL", REG_SMC, 0x5000047, &ixD2F4_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F4_PCIE_PORT_VC_CNTL)/sizeof(ixD2F4_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x5000048, &ixD2F4_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F4_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F4_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x5000049, &ixD2F4_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F4_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F4_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x500004a, &ixD2F4_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F4_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F4_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x500004b, &ixD2F4_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F4_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F4_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x500004c, &ixD2F4_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F4_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F4_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x500004d, &ixD2F4_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F4_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F4_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x5000050, &ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x5000051, &ixD2F4_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x5000052, &ixD2F4_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F4_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x5000054, &ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x5000055, &ixD2F4_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F4_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F4_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F4_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x5000056, &ixD2F4_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F4_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F4_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F4_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x5000057, &ixD2F4_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F4_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F4_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD2F4_PCIE_CORR_ERR_STATUS", REG_SMC, 0x5000058, &ixD2F4_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F4_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F4_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F4_PCIE_CORR_ERR_MASK", REG_SMC, 0x5000059, &ixD2F4_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F4_PCIE_CORR_ERR_MASK)/sizeof(ixD2F4_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F4_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x500005a, &ixD2F4_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F4_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F4_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_HDR_LOG0", REG_SMC, 0x500005b, &ixD2F4_PCIE_HDR_LOG0[0], sizeof(ixD2F4_PCIE_HDR_LOG0)/sizeof(ixD2F4_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD2F4_PCIE_HDR_LOG1", REG_SMC, 0x500005c, &ixD2F4_PCIE_HDR_LOG1[0], sizeof(ixD2F4_PCIE_HDR_LOG1)/sizeof(ixD2F4_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_HDR_LOG2", REG_SMC, 0x500005d, &ixD2F4_PCIE_HDR_LOG2[0], sizeof(ixD2F4_PCIE_HDR_LOG2)/sizeof(ixD2F4_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD2F4_PCIE_HDR_LOG3", REG_SMC, 0x500005e, &ixD2F4_PCIE_HDR_LOG3[0], sizeof(ixD2F4_PCIE_HDR_LOG3)/sizeof(ixD2F4_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD2F4_PCIE_ROOT_ERR_CMD", REG_SMC, 0x500005f, &ixD2F4_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F4_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F4_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD2F4_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x5000060, &ixD2F4_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F4_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F4_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F4_PCIE_ERR_SRC_ID", REG_SMC, 0x5000061, &ixD2F4_PCIE_ERR_SRC_ID[0], sizeof(ixD2F4_PCIE_ERR_SRC_ID)/sizeof(ixD2F4_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD2F4_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x5000062, &ixD2F4_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD2F4_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x5000063, &ixD2F4_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x5000064, &ixD2F4_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD2F4_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x5000065, &ixD2F4_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F4_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x500009c, &ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LINK_CNTL3", REG_SMC, 0x500009d, &ixD2F4_PCIE_LINK_CNTL3[0], sizeof(ixD2F4_PCIE_LINK_CNTL3)/sizeof(ixD2F4_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x500009e, &ixD2F4_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F4_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F4_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x500009f, &ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x50000a0, &ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x50000a1, &ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x50000a2, &ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x50000a3, &ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x50000a4, &ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x50000a5, &ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x50000a6, &ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F4_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x50000a8, &ixD2F4_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PCIE_ACS_CNTL", REG_SMC, 0x50000a9, &ixD2F4_PCIE_ACS_CNTL[0], sizeof(ixD2F4_PCIE_ACS_CNTL)/sizeof(ixD2F4_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_ACS_CAP", REG_SMC, 0x50000a9, &ixD2F4_PCIE_ACS_CAP[0], sizeof(ixD2F4_PCIE_ACS_CAP)/sizeof(ixD2F4_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x50000bc, &ixD2F4_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F4_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F4_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_CNTL", REG_SMC, 0x50000bd, &ixD2F4_PCIE_MC_CNTL[0], sizeof(ixD2F4_PCIE_MC_CNTL)/sizeof(ixD2F4_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_CAP", REG_SMC, 0x50000bd, &ixD2F4_PCIE_MC_CAP[0], sizeof(ixD2F4_PCIE_MC_CAP)/sizeof(ixD2F4_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_ADDR0", REG_SMC, 0x50000be, &ixD2F4_PCIE_MC_ADDR0[0], sizeof(ixD2F4_PCIE_MC_ADDR0)/sizeof(ixD2F4_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_ADDR1", REG_SMC, 0x50000bf, &ixD2F4_PCIE_MC_ADDR1[0], sizeof(ixD2F4_PCIE_MC_ADDR1)/sizeof(ixD2F4_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_RCV0", REG_SMC, 0x50000c0, &ixD2F4_PCIE_MC_RCV0[0], sizeof(ixD2F4_PCIE_MC_RCV0)/sizeof(ixD2F4_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_RCV1", REG_SMC, 0x50000c1, &ixD2F4_PCIE_MC_RCV1[0], sizeof(ixD2F4_PCIE_MC_RCV1)/sizeof(ixD2F4_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x50000c2, &ixD2F4_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F4_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F4_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x50000c3, &ixD2F4_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F4_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F4_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x50000c4, &ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x50000c5, &ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F4_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x50000c6, &ixD2F4_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F4_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F4_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD2F4_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x50000c7, &ixD2F4_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F4_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F4_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_DW1", REG_MMIO, 0x51, &mmPCIE_DEV_SERIAL_NUM_DW1[0], sizeof(mmPCIE_DEV_SERIAL_NUM_DW1)/sizeof(mmPCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "mmPCIE_DEV_SERIAL_NUM_DW2", REG_MMIO, 0x52, &mmPCIE_DEV_SERIAL_NUM_DW2[0], sizeof(mmPCIE_DEV_SERIAL_NUM_DW2)/sizeof(mmPCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_MMIO, 0x54, &mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(mmPCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_STATUS", REG_MMIO, 0x55, &mmPCIE_UNCORR_ERR_STATUS[0], sizeof(mmPCIE_UNCORR_ERR_STATUS)/sizeof(mmPCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_MASK", REG_MMIO, 0x56, &mmPCIE_UNCORR_ERR_MASK[0], sizeof(mmPCIE_UNCORR_ERR_MASK)/sizeof(mmPCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "mmPCIE_UNCORR_ERR_SEVERITY", REG_MMIO, 0x57, &mmPCIE_UNCORR_ERR_SEVERITY[0], sizeof(mmPCIE_UNCORR_ERR_SEVERITY)/sizeof(mmPCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "mmPCIE_CORR_ERR_STATUS", REG_MMIO, 0x58, &mmPCIE_CORR_ERR_STATUS[0], sizeof(mmPCIE_CORR_ERR_STATUS)/sizeof(mmPCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_CORR_ERR_MASK", REG_MMIO, 0x59, &mmPCIE_CORR_ERR_MASK[0], sizeof(mmPCIE_CORR_ERR_MASK)/sizeof(mmPCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "mmPCIE_ADV_ERR_CAP_CNTL", REG_MMIO, 0x5a, &mmPCIE_ADV_ERR_CAP_CNTL[0], sizeof(mmPCIE_ADV_ERR_CAP_CNTL)/sizeof(mmPCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG0", REG_MMIO, 0x5b, &mmPCIE_HDR_LOG0[0], sizeof(mmPCIE_HDR_LOG0)/sizeof(mmPCIE_HDR_LOG0[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG1", REG_MMIO, 0x5c, &mmPCIE_HDR_LOG1[0], sizeof(mmPCIE_HDR_LOG1)/sizeof(mmPCIE_HDR_LOG1[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_0", REG_MMIO, 0x5c9, &mmBIOS_SCRATCH_0[0], sizeof(mmBIOS_SCRATCH_0)/sizeof(mmBIOS_SCRATCH_0[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_1", REG_MMIO, 0x5ca, &mmBIOS_SCRATCH_1[0], sizeof(mmBIOS_SCRATCH_1)/sizeof(mmBIOS_SCRATCH_1[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_2", REG_MMIO, 0x5cb, &mmBIOS_SCRATCH_2[0], sizeof(mmBIOS_SCRATCH_2)/sizeof(mmBIOS_SCRATCH_2[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_3", REG_MMIO, 0x5cc, &mmBIOS_SCRATCH_3[0], sizeof(mmBIOS_SCRATCH_3)/sizeof(mmBIOS_SCRATCH_3[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_4", REG_MMIO, 0x5cd, &mmBIOS_SCRATCH_4[0], sizeof(mmBIOS_SCRATCH_4)/sizeof(mmBIOS_SCRATCH_4[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_5", REG_MMIO, 0x5ce, &mmBIOS_SCRATCH_5[0], sizeof(mmBIOS_SCRATCH_5)/sizeof(mmBIOS_SCRATCH_5[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_6", REG_MMIO, 0x5cf, &mmBIOS_SCRATCH_6[0], sizeof(mmBIOS_SCRATCH_6)/sizeof(mmBIOS_SCRATCH_6[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG2", REG_MMIO, 0x5d, &mmPCIE_HDR_LOG2[0], sizeof(mmPCIE_HDR_LOG2)/sizeof(mmPCIE_HDR_LOG2[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_7", REG_MMIO, 0x5d0, &mmBIOS_SCRATCH_7[0], sizeof(mmBIOS_SCRATCH_7)/sizeof(mmBIOS_SCRATCH_7[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_8", REG_MMIO, 0x5d1, &mmBIOS_SCRATCH_8[0], sizeof(mmBIOS_SCRATCH_8)/sizeof(mmBIOS_SCRATCH_8[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_9", REG_MMIO, 0x5d2, &mmBIOS_SCRATCH_9[0], sizeof(mmBIOS_SCRATCH_9)/sizeof(mmBIOS_SCRATCH_9[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_10", REG_MMIO, 0x5d3, &mmBIOS_SCRATCH_10[0], sizeof(mmBIOS_SCRATCH_10)/sizeof(mmBIOS_SCRATCH_10[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_11", REG_MMIO, 0x5d4, &mmBIOS_SCRATCH_11[0], sizeof(mmBIOS_SCRATCH_11)/sizeof(mmBIOS_SCRATCH_11[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_12", REG_MMIO, 0x5d5, &mmBIOS_SCRATCH_12[0], sizeof(mmBIOS_SCRATCH_12)/sizeof(mmBIOS_SCRATCH_12[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_13", REG_MMIO, 0x5d6, &mmBIOS_SCRATCH_13[0], sizeof(mmBIOS_SCRATCH_13)/sizeof(mmBIOS_SCRATCH_13[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_14", REG_MMIO, 0x5d7, &mmBIOS_SCRATCH_14[0], sizeof(mmBIOS_SCRATCH_14)/sizeof(mmBIOS_SCRATCH_14[0]), 0, 0 },
+	{ "mmBIOS_SCRATCH_15", REG_MMIO, 0x5d8, &mmBIOS_SCRATCH_15[0], sizeof(mmBIOS_SCRATCH_15)/sizeof(mmBIOS_SCRATCH_15[0]), 0, 0 },
+	{ "mmPCIE_HDR_LOG3", REG_MMIO, 0x5e, &mmPCIE_HDR_LOG3[0], sizeof(mmPCIE_HDR_LOG3)/sizeof(mmPCIE_HDR_LOG3[0]), 0, 0 },
+	{ "mmMM_INDEX_HI", REG_MMIO, 0x6, &mmMM_INDEX_HI[0], sizeof(mmMM_INDEX_HI)/sizeof(mmMM_INDEX_HI[0]), 0, 0 },
+	{ "ixD2F1_PCIE_FC_P", REG_SMC, 0x60, &ixD2F1_PCIE_FC_P[0], sizeof(ixD2F1_PCIE_FC_P)/sizeof(ixD2F1_PCIE_FC_P[0]), 0, 0 },
+	{ "ixD2F5_VENDOR_ID", REG_SMC, 0x6000000, &ixD2F5_VENDOR_ID[0], sizeof(ixD2F5_VENDOR_ID)/sizeof(ixD2F5_VENDOR_ID[0]), 0, 0 },
+	{ "ixD2F5_COMMAND", REG_SMC, 0x6000001, &ixD2F5_COMMAND[0], sizeof(ixD2F5_COMMAND)/sizeof(ixD2F5_COMMAND[0]), 0, 0 },
+	{ "ixD2F5_STATUS", REG_SMC, 0x6000001, &ixD2F5_STATUS[0], sizeof(ixD2F5_STATUS)/sizeof(ixD2F5_STATUS[0]), 0, 0 },
+	{ "ixD2F5_PROG_INTERFACE", REG_SMC, 0x6000002, &ixD2F5_PROG_INTERFACE[0], sizeof(ixD2F5_PROG_INTERFACE)/sizeof(ixD2F5_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD2F5_REVISION_ID", REG_SMC, 0x6000002, &ixD2F5_REVISION_ID[0], sizeof(ixD2F5_REVISION_ID)/sizeof(ixD2F5_REVISION_ID[0]), 0, 0 },
+	{ "ixD2F5_BASE_CLASS", REG_SMC, 0x6000002, &ixD2F5_BASE_CLASS[0], sizeof(ixD2F5_BASE_CLASS)/sizeof(ixD2F5_BASE_CLASS[0]), 0, 0 },
+	{ "ixD2F5_SUB_CLASS", REG_SMC, 0x6000002, &ixD2F5_SUB_CLASS[0], sizeof(ixD2F5_SUB_CLASS)/sizeof(ixD2F5_SUB_CLASS[0]), 0, 0 },
+	{ "ixD2F5_CACHE_LINE", REG_SMC, 0x6000003, &ixD2F5_CACHE_LINE[0], sizeof(ixD2F5_CACHE_LINE)/sizeof(ixD2F5_CACHE_LINE[0]), 0, 0 },
+	{ "ixD2F5_LATENCY", REG_SMC, 0x6000003, &ixD2F5_LATENCY[0], sizeof(ixD2F5_LATENCY)/sizeof(ixD2F5_LATENCY[0]), 0, 0 },
+	{ "ixD2F5_HEADER", REG_SMC, 0x6000003, &ixD2F5_HEADER[0], sizeof(ixD2F5_HEADER)/sizeof(ixD2F5_HEADER[0]), 0, 0 },
+	{ "ixD2F5_BIST", REG_SMC, 0x6000003, &ixD2F5_BIST[0], sizeof(ixD2F5_BIST)/sizeof(ixD2F5_BIST[0]), 0, 0 },
+	{ "ixD2F5_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x6000006, &ixD2F5_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD2F5_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD2F5_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD2F5_SECONDARY_STATUS", REG_SMC, 0x6000007, &ixD2F5_SECONDARY_STATUS[0], sizeof(ixD2F5_SECONDARY_STATUS)/sizeof(ixD2F5_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD2F5_IO_BASE_LIMIT", REG_SMC, 0x6000007, &ixD2F5_IO_BASE_LIMIT[0], sizeof(ixD2F5_IO_BASE_LIMIT)/sizeof(ixD2F5_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F5_MEM_BASE_LIMIT", REG_SMC, 0x6000008, &ixD2F5_MEM_BASE_LIMIT[0], sizeof(ixD2F5_MEM_BASE_LIMIT)/sizeof(ixD2F5_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F5_PREF_BASE_LIMIT", REG_SMC, 0x6000009, &ixD2F5_PREF_BASE_LIMIT[0], sizeof(ixD2F5_PREF_BASE_LIMIT)/sizeof(ixD2F5_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD2F5_PREF_BASE_UPPER", REG_SMC, 0x600000a, &ixD2F5_PREF_BASE_UPPER[0], sizeof(ixD2F5_PREF_BASE_UPPER)/sizeof(ixD2F5_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD2F5_PREF_LIMIT_UPPER", REG_SMC, 0x600000b, &ixD2F5_PREF_LIMIT_UPPER[0], sizeof(ixD2F5_PREF_LIMIT_UPPER)/sizeof(ixD2F5_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD2F5_IO_BASE_LIMIT_HI", REG_SMC, 0x600000c, &ixD2F5_IO_BASE_LIMIT_HI[0], sizeof(ixD2F5_IO_BASE_LIMIT_HI)/sizeof(ixD2F5_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD2F5_CAP_PTR", REG_SMC, 0x600000d, &ixD2F5_CAP_PTR[0], sizeof(ixD2F5_CAP_PTR)/sizeof(ixD2F5_CAP_PTR[0]), 0, 0 },
+	{ "ixD2F5_IRQ_BRIDGE_CNTL", REG_SMC, 0x600000f, &ixD2F5_IRQ_BRIDGE_CNTL[0], sizeof(ixD2F5_IRQ_BRIDGE_CNTL)/sizeof(ixD2F5_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F5_INTERRUPT_LINE", REG_SMC, 0x600000f, &ixD2F5_INTERRUPT_LINE[0], sizeof(ixD2F5_INTERRUPT_LINE)/sizeof(ixD2F5_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD2F5_INTERRUPT_PIN", REG_SMC, 0x600000f, &ixD2F5_INTERRUPT_PIN[0], sizeof(ixD2F5_INTERRUPT_PIN)/sizeof(ixD2F5_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD2F5_EXT_BRIDGE_CNTL", REG_SMC, 0x6000010, &ixD2F5_EXT_BRIDGE_CNTL[0], sizeof(ixD2F5_EXT_BRIDGE_CNTL)/sizeof(ixD2F5_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PMI_CAP_LIST", REG_SMC, 0x6000014, &ixD2F5_PMI_CAP_LIST[0], sizeof(ixD2F5_PMI_CAP_LIST)/sizeof(ixD2F5_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PMI_CAP", REG_SMC, 0x6000014, &ixD2F5_PMI_CAP[0], sizeof(ixD2F5_PMI_CAP)/sizeof(ixD2F5_PMI_CAP[0]), 0, 0 },
+	{ "ixD2F5_PMI_STATUS_CNTL", REG_SMC, 0x6000015, &ixD2F5_PMI_STATUS_CNTL[0], sizeof(ixD2F5_PMI_STATUS_CNTL)/sizeof(ixD2F5_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_CAP_LIST", REG_SMC, 0x6000016, &ixD2F5_PCIE_CAP_LIST[0], sizeof(ixD2F5_PCIE_CAP_LIST)/sizeof(ixD2F5_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PCIE_CAP", REG_SMC, 0x6000016, &ixD2F5_PCIE_CAP[0], sizeof(ixD2F5_PCIE_CAP)/sizeof(ixD2F5_PCIE_CAP[0]), 0, 0 },
+	{ "ixD2F5_DEVICE_CAP", REG_SMC, 0x6000017, &ixD2F5_DEVICE_CAP[0], sizeof(ixD2F5_DEVICE_CAP)/sizeof(ixD2F5_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD2F5_DEVICE_STATUS", REG_SMC, 0x6000018, &ixD2F5_DEVICE_STATUS[0], sizeof(ixD2F5_DEVICE_STATUS)/sizeof(ixD2F5_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD2F5_DEVICE_CNTL", REG_SMC, 0x6000018, &ixD2F5_DEVICE_CNTL[0], sizeof(ixD2F5_DEVICE_CNTL)/sizeof(ixD2F5_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD2F5_LINK_CAP", REG_SMC, 0x6000019, &ixD2F5_LINK_CAP[0], sizeof(ixD2F5_LINK_CAP)/sizeof(ixD2F5_LINK_CAP[0]), 0, 0 },
+	{ "ixD2F5_LINK_STATUS", REG_SMC, 0x600001a, &ixD2F5_LINK_STATUS[0], sizeof(ixD2F5_LINK_STATUS)/sizeof(ixD2F5_LINK_STATUS[0]), 0, 0 },
+	{ "ixD2F5_LINK_CNTL", REG_SMC, 0x600001a, &ixD2F5_LINK_CNTL[0], sizeof(ixD2F5_LINK_CNTL)/sizeof(ixD2F5_LINK_CNTL[0]), 0, 0 },
+	{ "ixD2F5_SLOT_CAP", REG_SMC, 0x600001b, &ixD2F5_SLOT_CAP[0], sizeof(ixD2F5_SLOT_CAP)/sizeof(ixD2F5_SLOT_CAP[0]), 0, 0 },
+	{ "ixD2F5_SLOT_STATUS", REG_SMC, 0x600001c, &ixD2F5_SLOT_STATUS[0], sizeof(ixD2F5_SLOT_STATUS)/sizeof(ixD2F5_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD2F5_SLOT_CNTL", REG_SMC, 0x600001c, &ixD2F5_SLOT_CNTL[0], sizeof(ixD2F5_SLOT_CNTL)/sizeof(ixD2F5_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD2F5_ROOT_CNTL", REG_SMC, 0x600001d, &ixD2F5_ROOT_CNTL[0], sizeof(ixD2F5_ROOT_CNTL)/sizeof(ixD2F5_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD2F5_ROOT_CAP", REG_SMC, 0x600001d, &ixD2F5_ROOT_CAP[0], sizeof(ixD2F5_ROOT_CAP)/sizeof(ixD2F5_ROOT_CAP[0]), 0, 0 },
+	{ "ixD2F5_ROOT_STATUS", REG_SMC, 0x600001e, &ixD2F5_ROOT_STATUS[0], sizeof(ixD2F5_ROOT_STATUS)/sizeof(ixD2F5_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD2F5_DEVICE_CAP2", REG_SMC, 0x600001f, &ixD2F5_DEVICE_CAP2[0], sizeof(ixD2F5_DEVICE_CAP2)/sizeof(ixD2F5_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD2F5_DEVICE_STATUS2", REG_SMC, 0x6000020, &ixD2F5_DEVICE_STATUS2[0], sizeof(ixD2F5_DEVICE_STATUS2)/sizeof(ixD2F5_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD2F5_DEVICE_CNTL2", REG_SMC, 0x6000020, &ixD2F5_DEVICE_CNTL2[0], sizeof(ixD2F5_DEVICE_CNTL2)/sizeof(ixD2F5_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD2F5_LINK_CAP2", REG_SMC, 0x6000021, &ixD2F5_LINK_CAP2[0], sizeof(ixD2F5_LINK_CAP2)/sizeof(ixD2F5_LINK_CAP2[0]), 0, 0 },
+	{ "ixD2F5_LINK_STATUS2", REG_SMC, 0x6000022, &ixD2F5_LINK_STATUS2[0], sizeof(ixD2F5_LINK_STATUS2)/sizeof(ixD2F5_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD2F5_LINK_CNTL2", REG_SMC, 0x6000022, &ixD2F5_LINK_CNTL2[0], sizeof(ixD2F5_LINK_CNTL2)/sizeof(ixD2F5_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD2F5_SLOT_CAP2", REG_SMC, 0x6000023, &ixD2F5_SLOT_CAP2[0], sizeof(ixD2F5_SLOT_CAP2)/sizeof(ixD2F5_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD2F5_SLOT_STATUS2", REG_SMC, 0x6000024, &ixD2F5_SLOT_STATUS2[0], sizeof(ixD2F5_SLOT_STATUS2)/sizeof(ixD2F5_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD2F5_SLOT_CNTL2", REG_SMC, 0x6000024, &ixD2F5_SLOT_CNTL2[0], sizeof(ixD2F5_SLOT_CNTL2)/sizeof(ixD2F5_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD2F5_MSI_CAP_LIST", REG_SMC, 0x6000028, &ixD2F5_MSI_CAP_LIST[0], sizeof(ixD2F5_MSI_CAP_LIST)/sizeof(ixD2F5_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_MSI_MSG_ADDR_LO", REG_SMC, 0x6000029, &ixD2F5_MSI_MSG_ADDR_LO[0], sizeof(ixD2F5_MSI_MSG_ADDR_LO)/sizeof(ixD2F5_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F5_MSI_MSG_ADDR_HI", REG_SMC, 0x600002a, &ixD2F5_MSI_MSG_ADDR_HI[0], sizeof(ixD2F5_MSI_MSG_ADDR_HI)/sizeof(ixD2F5_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F5_MSI_MSG_DATA", REG_SMC, 0x600002a, &ixD2F5_MSI_MSG_DATA[0], sizeof(ixD2F5_MSI_MSG_DATA)/sizeof(ixD2F5_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD2F5_MSI_MSG_DATA_64", REG_SMC, 0x600002b, &ixD2F5_MSI_MSG_DATA_64[0], sizeof(ixD2F5_MSI_MSG_DATA_64)/sizeof(ixD2F5_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD2F5_SSID_CAP_LIST", REG_SMC, 0x6000030, &ixD2F5_SSID_CAP_LIST[0], sizeof(ixD2F5_SSID_CAP_LIST)/sizeof(ixD2F5_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_SSID_CAP", REG_SMC, 0x6000031, &ixD2F5_SSID_CAP[0], sizeof(ixD2F5_SSID_CAP)/sizeof(ixD2F5_SSID_CAP[0]), 0, 0 },
+	{ "ixD2F5_MSI_MAP_CAP_LIST", REG_SMC, 0x6000032, &ixD2F5_MSI_MAP_CAP_LIST[0], sizeof(ixD2F5_MSI_MAP_CAP_LIST)/sizeof(ixD2F5_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_MSI_MAP_CAP", REG_SMC, 0x6000032, &ixD2F5_MSI_MAP_CAP[0], sizeof(ixD2F5_MSI_MAP_CAP)/sizeof(ixD2F5_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD2F5_MSI_MAP_ADDR_LO", REG_SMC, 0x6000033, &ixD2F5_MSI_MAP_ADDR_LO[0], sizeof(ixD2F5_MSI_MAP_ADDR_LO)/sizeof(ixD2F5_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD2F5_MSI_MAP_ADDR_HI", REG_SMC, 0x6000034, &ixD2F5_MSI_MAP_ADDR_HI[0], sizeof(ixD2F5_MSI_MAP_ADDR_HI)/sizeof(ixD2F5_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD2F5_PCIE_PORT_INDEX", REG_SMC, 0x6000038, &ixD2F5_PCIE_PORT_INDEX[0], sizeof(ixD2F5_PCIE_PORT_INDEX)/sizeof(ixD2F5_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD2F5_PCIE_PORT_DATA", REG_SMC, 0x6000039, &ixD2F5_PCIE_PORT_DATA[0], sizeof(ixD2F5_PCIE_PORT_DATA)/sizeof(ixD2F5_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x6000040, &ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x6000041, &ixD2F5_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x6000042, &ixD2F5_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x6000043, &ixD2F5_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD2F5_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x6000044, &ixD2F5_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x6000045, &ixD2F5_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD2F5_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD2F5_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x6000046, &ixD2F5_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD2F5_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD2F5_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD2F5_PCIE_PORT_VC_STATUS", REG_SMC, 0x6000047, &ixD2F5_PCIE_PORT_VC_STATUS[0], sizeof(ixD2F5_PCIE_PORT_VC_STATUS)/sizeof(ixD2F5_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD2F5_PCIE_PORT_VC_CNTL", REG_SMC, 0x6000047, &ixD2F5_PCIE_PORT_VC_CNTL[0], sizeof(ixD2F5_PCIE_PORT_VC_CNTL)/sizeof(ixD2F5_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x6000048, &ixD2F5_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD2F5_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD2F5_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x6000049, &ixD2F5_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD2F5_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD2F5_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x600004a, &ixD2F5_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD2F5_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD2F5_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x600004b, &ixD2F5_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD2F5_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD2F5_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x600004c, &ixD2F5_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD2F5_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD2F5_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x600004d, &ixD2F5_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD2F5_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD2F5_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x6000050, &ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x6000051, &ixD2F5_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x6000052, &ixD2F5_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD2F5_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x6000054, &ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x6000055, &ixD2F5_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD2F5_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD2F5_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F5_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x6000056, &ixD2F5_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD2F5_PCIE_UNCORR_ERR_MASK)/sizeof(ixD2F5_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F5_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x6000057, &ixD2F5_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD2F5_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD2F5_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD2F5_PCIE_CORR_ERR_STATUS", REG_SMC, 0x6000058, &ixD2F5_PCIE_CORR_ERR_STATUS[0], sizeof(ixD2F5_PCIE_CORR_ERR_STATUS)/sizeof(ixD2F5_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F5_PCIE_CORR_ERR_MASK", REG_SMC, 0x6000059, &ixD2F5_PCIE_CORR_ERR_MASK[0], sizeof(ixD2F5_PCIE_CORR_ERR_MASK)/sizeof(ixD2F5_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD2F5_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x600005a, &ixD2F5_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD2F5_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD2F5_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_HDR_LOG0", REG_SMC, 0x600005b, &ixD2F5_PCIE_HDR_LOG0[0], sizeof(ixD2F5_PCIE_HDR_LOG0)/sizeof(ixD2F5_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD2F5_PCIE_HDR_LOG1", REG_SMC, 0x600005c, &ixD2F5_PCIE_HDR_LOG1[0], sizeof(ixD2F5_PCIE_HDR_LOG1)/sizeof(ixD2F5_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_HDR_LOG2", REG_SMC, 0x600005d, &ixD2F5_PCIE_HDR_LOG2[0], sizeof(ixD2F5_PCIE_HDR_LOG2)/sizeof(ixD2F5_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD2F5_PCIE_HDR_LOG3", REG_SMC, 0x600005e, &ixD2F5_PCIE_HDR_LOG3[0], sizeof(ixD2F5_PCIE_HDR_LOG3)/sizeof(ixD2F5_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD2F5_PCIE_ROOT_ERR_CMD", REG_SMC, 0x600005f, &ixD2F5_PCIE_ROOT_ERR_CMD[0], sizeof(ixD2F5_PCIE_ROOT_ERR_CMD)/sizeof(ixD2F5_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD2F5_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x6000060, &ixD2F5_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD2F5_PCIE_ROOT_ERR_STATUS)/sizeof(ixD2F5_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD2F5_PCIE_ERR_SRC_ID", REG_SMC, 0x6000061, &ixD2F5_PCIE_ERR_SRC_ID[0], sizeof(ixD2F5_PCIE_ERR_SRC_ID)/sizeof(ixD2F5_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD2F5_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x6000062, &ixD2F5_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD2F5_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x6000063, &ixD2F5_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x6000064, &ixD2F5_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD2F5_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x6000065, &ixD2F5_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD2F5_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x600009c, &ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LINK_CNTL3", REG_SMC, 0x600009d, &ixD2F5_PCIE_LINK_CNTL3[0], sizeof(ixD2F5_PCIE_LINK_CNTL3)/sizeof(ixD2F5_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x600009e, &ixD2F5_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD2F5_PCIE_LANE_ERROR_STATUS)/sizeof(ixD2F5_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x600009f, &ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x60000a0, &ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x60000a1, &ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x60000a2, &ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x60000a3, &ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x60000a4, &ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x60000a5, &ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x60000a6, &ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD2F5_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x60000a8, &ixD2F5_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PCIE_ACS_CNTL", REG_SMC, 0x60000a9, &ixD2F5_PCIE_ACS_CNTL[0], sizeof(ixD2F5_PCIE_ACS_CNTL)/sizeof(ixD2F5_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_ACS_CAP", REG_SMC, 0x60000a9, &ixD2F5_PCIE_ACS_CAP[0], sizeof(ixD2F5_PCIE_ACS_CAP)/sizeof(ixD2F5_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x60000bc, &ixD2F5_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD2F5_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD2F5_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_CNTL", REG_SMC, 0x60000bd, &ixD2F5_PCIE_MC_CNTL[0], sizeof(ixD2F5_PCIE_MC_CNTL)/sizeof(ixD2F5_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_CAP", REG_SMC, 0x60000bd, &ixD2F5_PCIE_MC_CAP[0], sizeof(ixD2F5_PCIE_MC_CAP)/sizeof(ixD2F5_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_ADDR0", REG_SMC, 0x60000be, &ixD2F5_PCIE_MC_ADDR0[0], sizeof(ixD2F5_PCIE_MC_ADDR0)/sizeof(ixD2F5_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_ADDR1", REG_SMC, 0x60000bf, &ixD2F5_PCIE_MC_ADDR1[0], sizeof(ixD2F5_PCIE_MC_ADDR1)/sizeof(ixD2F5_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_RCV0", REG_SMC, 0x60000c0, &ixD2F5_PCIE_MC_RCV0[0], sizeof(ixD2F5_PCIE_MC_RCV0)/sizeof(ixD2F5_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_RCV1", REG_SMC, 0x60000c1, &ixD2F5_PCIE_MC_RCV1[0], sizeof(ixD2F5_PCIE_MC_RCV1)/sizeof(ixD2F5_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x60000c2, &ixD2F5_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD2F5_PCIE_MC_BLOCK_ALL0)/sizeof(ixD2F5_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x60000c3, &ixD2F5_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD2F5_PCIE_MC_BLOCK_ALL1)/sizeof(ixD2F5_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x60000c4, &ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x60000c5, &ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD2F5_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x60000c6, &ixD2F5_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD2F5_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD2F5_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD2F5_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x60000c7, &ixD2F5_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD2F5_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD2F5_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_FC_NP", REG_SMC, 0x61, &ixD2F1_PCIE_FC_NP[0], sizeof(ixD2F1_PCIE_FC_NP)/sizeof(ixD2F1_PCIE_FC_NP[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG0", REG_MMIO, 0x62, &mmPCIE_TLP_PREFIX_LOG0[0], sizeof(mmPCIE_TLP_PREFIX_LOG0)/sizeof(mmPCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD2F1_PCIE_FC_CPL", REG_SMC, 0x62, &ixD2F1_PCIE_FC_CPL[0], sizeof(ixD2F1_PCIE_FC_CPL)/sizeof(ixD2F1_PCIE_FC_CPL[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG1", REG_MMIO, 0x63, &mmPCIE_TLP_PREFIX_LOG1[0], sizeof(mmPCIE_TLP_PREFIX_LOG1)/sizeof(mmPCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG2", REG_MMIO, 0x64, &mmPCIE_TLP_PREFIX_LOG2[0], sizeof(mmPCIE_TLP_PREFIX_LOG2)/sizeof(mmPCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "mmPCIE_TLP_PREFIX_LOG3", REG_MMIO, 0x65, &mmPCIE_TLP_PREFIX_LOG3[0], sizeof(mmPCIE_TLP_PREFIX_LOG3)/sizeof(mmPCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD2F1_PCIE_ERR_CNTL", REG_SMC, 0x6a, &ixD2F1_PCIE_ERR_CNTL[0], sizeof(ixD2F1_PCIE_ERR_CNTL)/sizeof(ixD2F1_PCIE_ERR_CNTL[0]), 0, 0 },
+	{ "mmBASE_ADDR_4", REG_MMIO, 0x7, &mmBASE_ADDR_4[0], sizeof(mmBASE_ADDR_4)/sizeof(mmBASE_ADDR_4[0]), 0, 0 },
+	{ "ixD2F1_PCIE_RX_CNTL", REG_SMC, 0x70, &ixD2F1_PCIE_RX_CNTL[0], sizeof(ixD2F1_PCIE_RX_CNTL)/sizeof(ixD2F1_PCIE_RX_CNTL[0]), 0, 0 },
+	{ "ixD3F1_VENDOR_ID", REG_SMC, 0x7000000, &ixD3F1_VENDOR_ID[0], sizeof(ixD3F1_VENDOR_ID)/sizeof(ixD3F1_VENDOR_ID[0]), 0, 0 },
+	{ "ixD3F1_COMMAND", REG_SMC, 0x7000001, &ixD3F1_COMMAND[0], sizeof(ixD3F1_COMMAND)/sizeof(ixD3F1_COMMAND[0]), 0, 0 },
+	{ "ixD3F1_STATUS", REG_SMC, 0x7000001, &ixD3F1_STATUS[0], sizeof(ixD3F1_STATUS)/sizeof(ixD3F1_STATUS[0]), 0, 0 },
+	{ "ixD3F1_PROG_INTERFACE", REG_SMC, 0x7000002, &ixD3F1_PROG_INTERFACE[0], sizeof(ixD3F1_PROG_INTERFACE)/sizeof(ixD3F1_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD3F1_REVISION_ID", REG_SMC, 0x7000002, &ixD3F1_REVISION_ID[0], sizeof(ixD3F1_REVISION_ID)/sizeof(ixD3F1_REVISION_ID[0]), 0, 0 },
+	{ "ixD3F1_BASE_CLASS", REG_SMC, 0x7000002, &ixD3F1_BASE_CLASS[0], sizeof(ixD3F1_BASE_CLASS)/sizeof(ixD3F1_BASE_CLASS[0]), 0, 0 },
+	{ "ixD3F1_SUB_CLASS", REG_SMC, 0x7000002, &ixD3F1_SUB_CLASS[0], sizeof(ixD3F1_SUB_CLASS)/sizeof(ixD3F1_SUB_CLASS[0]), 0, 0 },
+	{ "ixD3F1_CACHE_LINE", REG_SMC, 0x7000003, &ixD3F1_CACHE_LINE[0], sizeof(ixD3F1_CACHE_LINE)/sizeof(ixD3F1_CACHE_LINE[0]), 0, 0 },
+	{ "ixD3F1_LATENCY", REG_SMC, 0x7000003, &ixD3F1_LATENCY[0], sizeof(ixD3F1_LATENCY)/sizeof(ixD3F1_LATENCY[0]), 0, 0 },
+	{ "ixD3F1_HEADER", REG_SMC, 0x7000003, &ixD3F1_HEADER[0], sizeof(ixD3F1_HEADER)/sizeof(ixD3F1_HEADER[0]), 0, 0 },
+	{ "ixD3F1_BIST", REG_SMC, 0x7000003, &ixD3F1_BIST[0], sizeof(ixD3F1_BIST)/sizeof(ixD3F1_BIST[0]), 0, 0 },
+	{ "ixD3F1_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x7000006, &ixD3F1_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F1_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F1_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD3F1_SECONDARY_STATUS", REG_SMC, 0x7000007, &ixD3F1_SECONDARY_STATUS[0], sizeof(ixD3F1_SECONDARY_STATUS)/sizeof(ixD3F1_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD3F1_IO_BASE_LIMIT", REG_SMC, 0x7000007, &ixD3F1_IO_BASE_LIMIT[0], sizeof(ixD3F1_IO_BASE_LIMIT)/sizeof(ixD3F1_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F1_MEM_BASE_LIMIT", REG_SMC, 0x7000008, &ixD3F1_MEM_BASE_LIMIT[0], sizeof(ixD3F1_MEM_BASE_LIMIT)/sizeof(ixD3F1_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F1_PREF_BASE_LIMIT", REG_SMC, 0x7000009, &ixD3F1_PREF_BASE_LIMIT[0], sizeof(ixD3F1_PREF_BASE_LIMIT)/sizeof(ixD3F1_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F1_PREF_BASE_UPPER", REG_SMC, 0x700000a, &ixD3F1_PREF_BASE_UPPER[0], sizeof(ixD3F1_PREF_BASE_UPPER)/sizeof(ixD3F1_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD3F1_PREF_LIMIT_UPPER", REG_SMC, 0x700000b, &ixD3F1_PREF_LIMIT_UPPER[0], sizeof(ixD3F1_PREF_LIMIT_UPPER)/sizeof(ixD3F1_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD3F1_IO_BASE_LIMIT_HI", REG_SMC, 0x700000c, &ixD3F1_IO_BASE_LIMIT_HI[0], sizeof(ixD3F1_IO_BASE_LIMIT_HI)/sizeof(ixD3F1_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD3F1_CAP_PTR", REG_SMC, 0x700000d, &ixD3F1_CAP_PTR[0], sizeof(ixD3F1_CAP_PTR)/sizeof(ixD3F1_CAP_PTR[0]), 0, 0 },
+	{ "ixD3F1_IRQ_BRIDGE_CNTL", REG_SMC, 0x700000f, &ixD3F1_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F1_IRQ_BRIDGE_CNTL)/sizeof(ixD3F1_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F1_INTERRUPT_LINE", REG_SMC, 0x700000f, &ixD3F1_INTERRUPT_LINE[0], sizeof(ixD3F1_INTERRUPT_LINE)/sizeof(ixD3F1_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD3F1_INTERRUPT_PIN", REG_SMC, 0x700000f, &ixD3F1_INTERRUPT_PIN[0], sizeof(ixD3F1_INTERRUPT_PIN)/sizeof(ixD3F1_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD3F1_EXT_BRIDGE_CNTL", REG_SMC, 0x7000010, &ixD3F1_EXT_BRIDGE_CNTL[0], sizeof(ixD3F1_EXT_BRIDGE_CNTL)/sizeof(ixD3F1_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PMI_CAP_LIST", REG_SMC, 0x7000014, &ixD3F1_PMI_CAP_LIST[0], sizeof(ixD3F1_PMI_CAP_LIST)/sizeof(ixD3F1_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PMI_CAP", REG_SMC, 0x7000014, &ixD3F1_PMI_CAP[0], sizeof(ixD3F1_PMI_CAP)/sizeof(ixD3F1_PMI_CAP[0]), 0, 0 },
+	{ "ixD3F1_PMI_STATUS_CNTL", REG_SMC, 0x7000015, &ixD3F1_PMI_STATUS_CNTL[0], sizeof(ixD3F1_PMI_STATUS_CNTL)/sizeof(ixD3F1_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_CAP_LIST", REG_SMC, 0x7000016, &ixD3F1_PCIE_CAP_LIST[0], sizeof(ixD3F1_PCIE_CAP_LIST)/sizeof(ixD3F1_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PCIE_CAP", REG_SMC, 0x7000016, &ixD3F1_PCIE_CAP[0], sizeof(ixD3F1_PCIE_CAP)/sizeof(ixD3F1_PCIE_CAP[0]), 0, 0 },
+	{ "ixD3F1_DEVICE_CAP", REG_SMC, 0x7000017, &ixD3F1_DEVICE_CAP[0], sizeof(ixD3F1_DEVICE_CAP)/sizeof(ixD3F1_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD3F1_DEVICE_STATUS", REG_SMC, 0x7000018, &ixD3F1_DEVICE_STATUS[0], sizeof(ixD3F1_DEVICE_STATUS)/sizeof(ixD3F1_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD3F1_DEVICE_CNTL", REG_SMC, 0x7000018, &ixD3F1_DEVICE_CNTL[0], sizeof(ixD3F1_DEVICE_CNTL)/sizeof(ixD3F1_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD3F1_LINK_CAP", REG_SMC, 0x7000019, &ixD3F1_LINK_CAP[0], sizeof(ixD3F1_LINK_CAP)/sizeof(ixD3F1_LINK_CAP[0]), 0, 0 },
+	{ "ixD3F1_LINK_STATUS", REG_SMC, 0x700001a, &ixD3F1_LINK_STATUS[0], sizeof(ixD3F1_LINK_STATUS)/sizeof(ixD3F1_LINK_STATUS[0]), 0, 0 },
+	{ "ixD3F1_LINK_CNTL", REG_SMC, 0x700001a, &ixD3F1_LINK_CNTL[0], sizeof(ixD3F1_LINK_CNTL)/sizeof(ixD3F1_LINK_CNTL[0]), 0, 0 },
+	{ "ixD3F1_SLOT_CAP", REG_SMC, 0x700001b, &ixD3F1_SLOT_CAP[0], sizeof(ixD3F1_SLOT_CAP)/sizeof(ixD3F1_SLOT_CAP[0]), 0, 0 },
+	{ "ixD3F1_SLOT_STATUS", REG_SMC, 0x700001c, &ixD3F1_SLOT_STATUS[0], sizeof(ixD3F1_SLOT_STATUS)/sizeof(ixD3F1_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD3F1_SLOT_CNTL", REG_SMC, 0x700001c, &ixD3F1_SLOT_CNTL[0], sizeof(ixD3F1_SLOT_CNTL)/sizeof(ixD3F1_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD3F1_ROOT_CNTL", REG_SMC, 0x700001d, &ixD3F1_ROOT_CNTL[0], sizeof(ixD3F1_ROOT_CNTL)/sizeof(ixD3F1_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD3F1_ROOT_CAP", REG_SMC, 0x700001d, &ixD3F1_ROOT_CAP[0], sizeof(ixD3F1_ROOT_CAP)/sizeof(ixD3F1_ROOT_CAP[0]), 0, 0 },
+	{ "ixD3F1_ROOT_STATUS", REG_SMC, 0x700001e, &ixD3F1_ROOT_STATUS[0], sizeof(ixD3F1_ROOT_STATUS)/sizeof(ixD3F1_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD3F1_DEVICE_CAP2", REG_SMC, 0x700001f, &ixD3F1_DEVICE_CAP2[0], sizeof(ixD3F1_DEVICE_CAP2)/sizeof(ixD3F1_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD3F1_DEVICE_STATUS2", REG_SMC, 0x7000020, &ixD3F1_DEVICE_STATUS2[0], sizeof(ixD3F1_DEVICE_STATUS2)/sizeof(ixD3F1_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD3F1_DEVICE_CNTL2", REG_SMC, 0x7000020, &ixD3F1_DEVICE_CNTL2[0], sizeof(ixD3F1_DEVICE_CNTL2)/sizeof(ixD3F1_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD3F1_LINK_CAP2", REG_SMC, 0x7000021, &ixD3F1_LINK_CAP2[0], sizeof(ixD3F1_LINK_CAP2)/sizeof(ixD3F1_LINK_CAP2[0]), 0, 0 },
+	{ "ixD3F1_LINK_STATUS2", REG_SMC, 0x7000022, &ixD3F1_LINK_STATUS2[0], sizeof(ixD3F1_LINK_STATUS2)/sizeof(ixD3F1_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD3F1_LINK_CNTL2", REG_SMC, 0x7000022, &ixD3F1_LINK_CNTL2[0], sizeof(ixD3F1_LINK_CNTL2)/sizeof(ixD3F1_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD3F1_SLOT_CAP2", REG_SMC, 0x7000023, &ixD3F1_SLOT_CAP2[0], sizeof(ixD3F1_SLOT_CAP2)/sizeof(ixD3F1_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD3F1_SLOT_STATUS2", REG_SMC, 0x7000024, &ixD3F1_SLOT_STATUS2[0], sizeof(ixD3F1_SLOT_STATUS2)/sizeof(ixD3F1_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD3F1_SLOT_CNTL2", REG_SMC, 0x7000024, &ixD3F1_SLOT_CNTL2[0], sizeof(ixD3F1_SLOT_CNTL2)/sizeof(ixD3F1_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD3F1_MSI_CAP_LIST", REG_SMC, 0x7000028, &ixD3F1_MSI_CAP_LIST[0], sizeof(ixD3F1_MSI_CAP_LIST)/sizeof(ixD3F1_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_MSI_MSG_ADDR_LO", REG_SMC, 0x7000029, &ixD3F1_MSI_MSG_ADDR_LO[0], sizeof(ixD3F1_MSI_MSG_ADDR_LO)/sizeof(ixD3F1_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F1_MSI_MSG_ADDR_HI", REG_SMC, 0x700002a, &ixD3F1_MSI_MSG_ADDR_HI[0], sizeof(ixD3F1_MSI_MSG_ADDR_HI)/sizeof(ixD3F1_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F1_MSI_MSG_DATA", REG_SMC, 0x700002a, &ixD3F1_MSI_MSG_DATA[0], sizeof(ixD3F1_MSI_MSG_DATA)/sizeof(ixD3F1_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD3F1_MSI_MSG_DATA_64", REG_SMC, 0x700002b, &ixD3F1_MSI_MSG_DATA_64[0], sizeof(ixD3F1_MSI_MSG_DATA_64)/sizeof(ixD3F1_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD3F1_SSID_CAP_LIST", REG_SMC, 0x7000030, &ixD3F1_SSID_CAP_LIST[0], sizeof(ixD3F1_SSID_CAP_LIST)/sizeof(ixD3F1_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_SSID_CAP", REG_SMC, 0x7000031, &ixD3F1_SSID_CAP[0], sizeof(ixD3F1_SSID_CAP)/sizeof(ixD3F1_SSID_CAP[0]), 0, 0 },
+	{ "ixD3F1_MSI_MAP_CAP_LIST", REG_SMC, 0x7000032, &ixD3F1_MSI_MAP_CAP_LIST[0], sizeof(ixD3F1_MSI_MAP_CAP_LIST)/sizeof(ixD3F1_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_MSI_MAP_CAP", REG_SMC, 0x7000032, &ixD3F1_MSI_MAP_CAP[0], sizeof(ixD3F1_MSI_MAP_CAP)/sizeof(ixD3F1_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD3F1_MSI_MAP_ADDR_LO", REG_SMC, 0x7000033, &ixD3F1_MSI_MAP_ADDR_LO[0], sizeof(ixD3F1_MSI_MAP_ADDR_LO)/sizeof(ixD3F1_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F1_MSI_MAP_ADDR_HI", REG_SMC, 0x7000034, &ixD3F1_MSI_MAP_ADDR_HI[0], sizeof(ixD3F1_MSI_MAP_ADDR_HI)/sizeof(ixD3F1_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F1_PCIE_PORT_INDEX", REG_SMC, 0x7000038, &ixD3F1_PCIE_PORT_INDEX[0], sizeof(ixD3F1_PCIE_PORT_INDEX)/sizeof(ixD3F1_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD3F1_PCIE_PORT_DATA", REG_SMC, 0x7000039, &ixD3F1_PCIE_PORT_DATA[0], sizeof(ixD3F1_PCIE_PORT_DATA)/sizeof(ixD3F1_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x7000040, &ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x7000041, &ixD3F1_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x7000042, &ixD3F1_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x7000043, &ixD3F1_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F1_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x7000044, &ixD3F1_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x7000045, &ixD3F1_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F1_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F1_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x7000046, &ixD3F1_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F1_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F1_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD3F1_PCIE_PORT_VC_STATUS", REG_SMC, 0x7000047, &ixD3F1_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F1_PCIE_PORT_VC_STATUS)/sizeof(ixD3F1_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD3F1_PCIE_PORT_VC_CNTL", REG_SMC, 0x7000047, &ixD3F1_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F1_PCIE_PORT_VC_CNTL)/sizeof(ixD3F1_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x7000048, &ixD3F1_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F1_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F1_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x7000049, &ixD3F1_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F1_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F1_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x700004a, &ixD3F1_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F1_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F1_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x700004b, &ixD3F1_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F1_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F1_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x700004c, &ixD3F1_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F1_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F1_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x700004d, &ixD3F1_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F1_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F1_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x7000050, &ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x7000051, &ixD3F1_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x7000052, &ixD3F1_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F1_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x7000054, &ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x7000055, &ixD3F1_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F1_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F1_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F1_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x7000056, &ixD3F1_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F1_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F1_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F1_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x7000057, &ixD3F1_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F1_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F1_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD3F1_PCIE_CORR_ERR_STATUS", REG_SMC, 0x7000058, &ixD3F1_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F1_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F1_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F1_PCIE_CORR_ERR_MASK", REG_SMC, 0x7000059, &ixD3F1_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F1_PCIE_CORR_ERR_MASK)/sizeof(ixD3F1_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F1_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x700005a, &ixD3F1_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F1_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F1_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_HDR_LOG0", REG_SMC, 0x700005b, &ixD3F1_PCIE_HDR_LOG0[0], sizeof(ixD3F1_PCIE_HDR_LOG0)/sizeof(ixD3F1_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD3F1_PCIE_HDR_LOG1", REG_SMC, 0x700005c, &ixD3F1_PCIE_HDR_LOG1[0], sizeof(ixD3F1_PCIE_HDR_LOG1)/sizeof(ixD3F1_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_HDR_LOG2", REG_SMC, 0x700005d, &ixD3F1_PCIE_HDR_LOG2[0], sizeof(ixD3F1_PCIE_HDR_LOG2)/sizeof(ixD3F1_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD3F1_PCIE_HDR_LOG3", REG_SMC, 0x700005e, &ixD3F1_PCIE_HDR_LOG3[0], sizeof(ixD3F1_PCIE_HDR_LOG3)/sizeof(ixD3F1_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD3F1_PCIE_ROOT_ERR_CMD", REG_SMC, 0x700005f, &ixD3F1_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F1_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F1_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD3F1_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x7000060, &ixD3F1_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F1_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F1_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F1_PCIE_ERR_SRC_ID", REG_SMC, 0x7000061, &ixD3F1_PCIE_ERR_SRC_ID[0], sizeof(ixD3F1_PCIE_ERR_SRC_ID)/sizeof(ixD3F1_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD3F1_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x7000062, &ixD3F1_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD3F1_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x7000063, &ixD3F1_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x7000064, &ixD3F1_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD3F1_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x7000065, &ixD3F1_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F1_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x700009c, &ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LINK_CNTL3", REG_SMC, 0x700009d, &ixD3F1_PCIE_LINK_CNTL3[0], sizeof(ixD3F1_PCIE_LINK_CNTL3)/sizeof(ixD3F1_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x700009e, &ixD3F1_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F1_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F1_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x700009f, &ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x70000a0, &ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x70000a1, &ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x70000a2, &ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x70000a3, &ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x70000a4, &ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x70000a5, &ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x70000a6, &ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F1_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x70000a8, &ixD3F1_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PCIE_ACS_CNTL", REG_SMC, 0x70000a9, &ixD3F1_PCIE_ACS_CNTL[0], sizeof(ixD3F1_PCIE_ACS_CNTL)/sizeof(ixD3F1_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_ACS_CAP", REG_SMC, 0x70000a9, &ixD3F1_PCIE_ACS_CAP[0], sizeof(ixD3F1_PCIE_ACS_CAP)/sizeof(ixD3F1_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x70000bc, &ixD3F1_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F1_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F1_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_CNTL", REG_SMC, 0x70000bd, &ixD3F1_PCIE_MC_CNTL[0], sizeof(ixD3F1_PCIE_MC_CNTL)/sizeof(ixD3F1_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_CAP", REG_SMC, 0x70000bd, &ixD3F1_PCIE_MC_CAP[0], sizeof(ixD3F1_PCIE_MC_CAP)/sizeof(ixD3F1_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_ADDR0", REG_SMC, 0x70000be, &ixD3F1_PCIE_MC_ADDR0[0], sizeof(ixD3F1_PCIE_MC_ADDR0)/sizeof(ixD3F1_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_ADDR1", REG_SMC, 0x70000bf, &ixD3F1_PCIE_MC_ADDR1[0], sizeof(ixD3F1_PCIE_MC_ADDR1)/sizeof(ixD3F1_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_RCV0", REG_SMC, 0x70000c0, &ixD3F1_PCIE_MC_RCV0[0], sizeof(ixD3F1_PCIE_MC_RCV0)/sizeof(ixD3F1_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_RCV1", REG_SMC, 0x70000c1, &ixD3F1_PCIE_MC_RCV1[0], sizeof(ixD3F1_PCIE_MC_RCV1)/sizeof(ixD3F1_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x70000c2, &ixD3F1_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F1_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F1_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x70000c3, &ixD3F1_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F1_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F1_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x70000c4, &ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x70000c5, &ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F1_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x70000c6, &ixD3F1_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F1_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F1_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD3F1_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x70000c7, &ixD3F1_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F1_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F1_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_RX_EXPECTED_SEQNUM", REG_SMC, 0x71, &ixD2F1_PCIE_RX_EXPECTED_SEQNUM[0], sizeof(ixD2F1_PCIE_RX_EXPECTED_SEQNUM)/sizeof(ixD2F1_PCIE_RX_EXPECTED_SEQNUM[0]), 0, 0 },
+	{ "ixD2F1_PCIE_RX_VENDOR_SPECIFIC", REG_SMC, 0x72, &ixD2F1_PCIE_RX_VENDOR_SPECIFIC[0], sizeof(ixD2F1_PCIE_RX_VENDOR_SPECIFIC)/sizeof(ixD2F1_PCIE_RX_VENDOR_SPECIFIC[0]), 0, 0 },
+	{ "ixD2F1_PCIE_RX_CNTL3", REG_SMC, 0x74, &ixD2F1_PCIE_RX_CNTL3[0], sizeof(ixD2F1_PCIE_RX_CNTL3)/sizeof(ixD2F1_PCIE_RX_CNTL3[0]), 0, 0 },
+	{ "mmBASE_ADDR_5", REG_MMIO, 0x8, &mmBASE_ADDR_5[0], sizeof(mmBASE_ADDR_5)/sizeof(mmBASE_ADDR_5[0]), 0, 0 },
+	{ "ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P", REG_SMC, 0x80, &ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P[0], sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P)/sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_P[0]), 0, 0 },
+	{ "mmPCIE_BAR_ENH_CAP_LIST", REG_MMIO, 0x80, &mmPCIE_BAR_ENH_CAP_LIST[0], sizeof(mmPCIE_BAR_ENH_CAP_LIST)/sizeof(mmPCIE_BAR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_VENDOR_ID", REG_SMC, 0x8000000, &ixD3F2_VENDOR_ID[0], sizeof(ixD3F2_VENDOR_ID)/sizeof(ixD3F2_VENDOR_ID[0]), 0, 0 },
+	{ "ixD3F2_COMMAND", REG_SMC, 0x8000001, &ixD3F2_COMMAND[0], sizeof(ixD3F2_COMMAND)/sizeof(ixD3F2_COMMAND[0]), 0, 0 },
+	{ "ixD3F2_STATUS", REG_SMC, 0x8000001, &ixD3F2_STATUS[0], sizeof(ixD3F2_STATUS)/sizeof(ixD3F2_STATUS[0]), 0, 0 },
+	{ "ixD3F2_PROG_INTERFACE", REG_SMC, 0x8000002, &ixD3F2_PROG_INTERFACE[0], sizeof(ixD3F2_PROG_INTERFACE)/sizeof(ixD3F2_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD3F2_REVISION_ID", REG_SMC, 0x8000002, &ixD3F2_REVISION_ID[0], sizeof(ixD3F2_REVISION_ID)/sizeof(ixD3F2_REVISION_ID[0]), 0, 0 },
+	{ "ixD3F2_BASE_CLASS", REG_SMC, 0x8000002, &ixD3F2_BASE_CLASS[0], sizeof(ixD3F2_BASE_CLASS)/sizeof(ixD3F2_BASE_CLASS[0]), 0, 0 },
+	{ "ixD3F2_SUB_CLASS", REG_SMC, 0x8000002, &ixD3F2_SUB_CLASS[0], sizeof(ixD3F2_SUB_CLASS)/sizeof(ixD3F2_SUB_CLASS[0]), 0, 0 },
+	{ "ixD3F2_CACHE_LINE", REG_SMC, 0x8000003, &ixD3F2_CACHE_LINE[0], sizeof(ixD3F2_CACHE_LINE)/sizeof(ixD3F2_CACHE_LINE[0]), 0, 0 },
+	{ "ixD3F2_LATENCY", REG_SMC, 0x8000003, &ixD3F2_LATENCY[0], sizeof(ixD3F2_LATENCY)/sizeof(ixD3F2_LATENCY[0]), 0, 0 },
+	{ "ixD3F2_HEADER", REG_SMC, 0x8000003, &ixD3F2_HEADER[0], sizeof(ixD3F2_HEADER)/sizeof(ixD3F2_HEADER[0]), 0, 0 },
+	{ "ixD3F2_BIST", REG_SMC, 0x8000003, &ixD3F2_BIST[0], sizeof(ixD3F2_BIST)/sizeof(ixD3F2_BIST[0]), 0, 0 },
+	{ "ixD3F2_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x8000006, &ixD3F2_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F2_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F2_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD3F2_SECONDARY_STATUS", REG_SMC, 0x8000007, &ixD3F2_SECONDARY_STATUS[0], sizeof(ixD3F2_SECONDARY_STATUS)/sizeof(ixD3F2_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD3F2_IO_BASE_LIMIT", REG_SMC, 0x8000007, &ixD3F2_IO_BASE_LIMIT[0], sizeof(ixD3F2_IO_BASE_LIMIT)/sizeof(ixD3F2_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F2_MEM_BASE_LIMIT", REG_SMC, 0x8000008, &ixD3F2_MEM_BASE_LIMIT[0], sizeof(ixD3F2_MEM_BASE_LIMIT)/sizeof(ixD3F2_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F2_PREF_BASE_LIMIT", REG_SMC, 0x8000009, &ixD3F2_PREF_BASE_LIMIT[0], sizeof(ixD3F2_PREF_BASE_LIMIT)/sizeof(ixD3F2_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F2_PREF_BASE_UPPER", REG_SMC, 0x800000a, &ixD3F2_PREF_BASE_UPPER[0], sizeof(ixD3F2_PREF_BASE_UPPER)/sizeof(ixD3F2_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD3F2_PREF_LIMIT_UPPER", REG_SMC, 0x800000b, &ixD3F2_PREF_LIMIT_UPPER[0], sizeof(ixD3F2_PREF_LIMIT_UPPER)/sizeof(ixD3F2_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD3F2_IO_BASE_LIMIT_HI", REG_SMC, 0x800000c, &ixD3F2_IO_BASE_LIMIT_HI[0], sizeof(ixD3F2_IO_BASE_LIMIT_HI)/sizeof(ixD3F2_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD3F2_CAP_PTR", REG_SMC, 0x800000d, &ixD3F2_CAP_PTR[0], sizeof(ixD3F2_CAP_PTR)/sizeof(ixD3F2_CAP_PTR[0]), 0, 0 },
+	{ "ixD3F2_IRQ_BRIDGE_CNTL", REG_SMC, 0x800000f, &ixD3F2_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F2_IRQ_BRIDGE_CNTL)/sizeof(ixD3F2_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F2_INTERRUPT_LINE", REG_SMC, 0x800000f, &ixD3F2_INTERRUPT_LINE[0], sizeof(ixD3F2_INTERRUPT_LINE)/sizeof(ixD3F2_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD3F2_INTERRUPT_PIN", REG_SMC, 0x800000f, &ixD3F2_INTERRUPT_PIN[0], sizeof(ixD3F2_INTERRUPT_PIN)/sizeof(ixD3F2_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD3F2_EXT_BRIDGE_CNTL", REG_SMC, 0x8000010, &ixD3F2_EXT_BRIDGE_CNTL[0], sizeof(ixD3F2_EXT_BRIDGE_CNTL)/sizeof(ixD3F2_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PMI_CAP_LIST", REG_SMC, 0x8000014, &ixD3F2_PMI_CAP_LIST[0], sizeof(ixD3F2_PMI_CAP_LIST)/sizeof(ixD3F2_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PMI_CAP", REG_SMC, 0x8000014, &ixD3F2_PMI_CAP[0], sizeof(ixD3F2_PMI_CAP)/sizeof(ixD3F2_PMI_CAP[0]), 0, 0 },
+	{ "ixD3F2_PMI_STATUS_CNTL", REG_SMC, 0x8000015, &ixD3F2_PMI_STATUS_CNTL[0], sizeof(ixD3F2_PMI_STATUS_CNTL)/sizeof(ixD3F2_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_CAP_LIST", REG_SMC, 0x8000016, &ixD3F2_PCIE_CAP_LIST[0], sizeof(ixD3F2_PCIE_CAP_LIST)/sizeof(ixD3F2_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PCIE_CAP", REG_SMC, 0x8000016, &ixD3F2_PCIE_CAP[0], sizeof(ixD3F2_PCIE_CAP)/sizeof(ixD3F2_PCIE_CAP[0]), 0, 0 },
+	{ "ixD3F2_DEVICE_CAP", REG_SMC, 0x8000017, &ixD3F2_DEVICE_CAP[0], sizeof(ixD3F2_DEVICE_CAP)/sizeof(ixD3F2_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD3F2_DEVICE_STATUS", REG_SMC, 0x8000018, &ixD3F2_DEVICE_STATUS[0], sizeof(ixD3F2_DEVICE_STATUS)/sizeof(ixD3F2_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD3F2_DEVICE_CNTL", REG_SMC, 0x8000018, &ixD3F2_DEVICE_CNTL[0], sizeof(ixD3F2_DEVICE_CNTL)/sizeof(ixD3F2_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD3F2_LINK_CAP", REG_SMC, 0x8000019, &ixD3F2_LINK_CAP[0], sizeof(ixD3F2_LINK_CAP)/sizeof(ixD3F2_LINK_CAP[0]), 0, 0 },
+	{ "ixD3F2_LINK_STATUS", REG_SMC, 0x800001a, &ixD3F2_LINK_STATUS[0], sizeof(ixD3F2_LINK_STATUS)/sizeof(ixD3F2_LINK_STATUS[0]), 0, 0 },
+	{ "ixD3F2_LINK_CNTL", REG_SMC, 0x800001a, &ixD3F2_LINK_CNTL[0], sizeof(ixD3F2_LINK_CNTL)/sizeof(ixD3F2_LINK_CNTL[0]), 0, 0 },
+	{ "ixD3F2_SLOT_CAP", REG_SMC, 0x800001b, &ixD3F2_SLOT_CAP[0], sizeof(ixD3F2_SLOT_CAP)/sizeof(ixD3F2_SLOT_CAP[0]), 0, 0 },
+	{ "ixD3F2_SLOT_STATUS", REG_SMC, 0x800001c, &ixD3F2_SLOT_STATUS[0], sizeof(ixD3F2_SLOT_STATUS)/sizeof(ixD3F2_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD3F2_SLOT_CNTL", REG_SMC, 0x800001c, &ixD3F2_SLOT_CNTL[0], sizeof(ixD3F2_SLOT_CNTL)/sizeof(ixD3F2_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD3F2_ROOT_CNTL", REG_SMC, 0x800001d, &ixD3F2_ROOT_CNTL[0], sizeof(ixD3F2_ROOT_CNTL)/sizeof(ixD3F2_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD3F2_ROOT_CAP", REG_SMC, 0x800001d, &ixD3F2_ROOT_CAP[0], sizeof(ixD3F2_ROOT_CAP)/sizeof(ixD3F2_ROOT_CAP[0]), 0, 0 },
+	{ "ixD3F2_ROOT_STATUS", REG_SMC, 0x800001e, &ixD3F2_ROOT_STATUS[0], sizeof(ixD3F2_ROOT_STATUS)/sizeof(ixD3F2_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD3F2_DEVICE_CAP2", REG_SMC, 0x800001f, &ixD3F2_DEVICE_CAP2[0], sizeof(ixD3F2_DEVICE_CAP2)/sizeof(ixD3F2_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD3F2_DEVICE_STATUS2", REG_SMC, 0x8000020, &ixD3F2_DEVICE_STATUS2[0], sizeof(ixD3F2_DEVICE_STATUS2)/sizeof(ixD3F2_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD3F2_DEVICE_CNTL2", REG_SMC, 0x8000020, &ixD3F2_DEVICE_CNTL2[0], sizeof(ixD3F2_DEVICE_CNTL2)/sizeof(ixD3F2_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD3F2_LINK_CAP2", REG_SMC, 0x8000021, &ixD3F2_LINK_CAP2[0], sizeof(ixD3F2_LINK_CAP2)/sizeof(ixD3F2_LINK_CAP2[0]), 0, 0 },
+	{ "ixD3F2_LINK_STATUS2", REG_SMC, 0x8000022, &ixD3F2_LINK_STATUS2[0], sizeof(ixD3F2_LINK_STATUS2)/sizeof(ixD3F2_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD3F2_LINK_CNTL2", REG_SMC, 0x8000022, &ixD3F2_LINK_CNTL2[0], sizeof(ixD3F2_LINK_CNTL2)/sizeof(ixD3F2_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD3F2_SLOT_CAP2", REG_SMC, 0x8000023, &ixD3F2_SLOT_CAP2[0], sizeof(ixD3F2_SLOT_CAP2)/sizeof(ixD3F2_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD3F2_SLOT_STATUS2", REG_SMC, 0x8000024, &ixD3F2_SLOT_STATUS2[0], sizeof(ixD3F2_SLOT_STATUS2)/sizeof(ixD3F2_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD3F2_SLOT_CNTL2", REG_SMC, 0x8000024, &ixD3F2_SLOT_CNTL2[0], sizeof(ixD3F2_SLOT_CNTL2)/sizeof(ixD3F2_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD3F2_MSI_CAP_LIST", REG_SMC, 0x8000028, &ixD3F2_MSI_CAP_LIST[0], sizeof(ixD3F2_MSI_CAP_LIST)/sizeof(ixD3F2_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_MSI_MSG_ADDR_LO", REG_SMC, 0x8000029, &ixD3F2_MSI_MSG_ADDR_LO[0], sizeof(ixD3F2_MSI_MSG_ADDR_LO)/sizeof(ixD3F2_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F2_MSI_MSG_ADDR_HI", REG_SMC, 0x800002a, &ixD3F2_MSI_MSG_ADDR_HI[0], sizeof(ixD3F2_MSI_MSG_ADDR_HI)/sizeof(ixD3F2_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F2_MSI_MSG_DATA", REG_SMC, 0x800002a, &ixD3F2_MSI_MSG_DATA[0], sizeof(ixD3F2_MSI_MSG_DATA)/sizeof(ixD3F2_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD3F2_MSI_MSG_DATA_64", REG_SMC, 0x800002b, &ixD3F2_MSI_MSG_DATA_64[0], sizeof(ixD3F2_MSI_MSG_DATA_64)/sizeof(ixD3F2_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD3F2_SSID_CAP_LIST", REG_SMC, 0x8000030, &ixD3F2_SSID_CAP_LIST[0], sizeof(ixD3F2_SSID_CAP_LIST)/sizeof(ixD3F2_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_SSID_CAP", REG_SMC, 0x8000031, &ixD3F2_SSID_CAP[0], sizeof(ixD3F2_SSID_CAP)/sizeof(ixD3F2_SSID_CAP[0]), 0, 0 },
+	{ "ixD3F2_MSI_MAP_CAP_LIST", REG_SMC, 0x8000032, &ixD3F2_MSI_MAP_CAP_LIST[0], sizeof(ixD3F2_MSI_MAP_CAP_LIST)/sizeof(ixD3F2_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_MSI_MAP_CAP", REG_SMC, 0x8000032, &ixD3F2_MSI_MAP_CAP[0], sizeof(ixD3F2_MSI_MAP_CAP)/sizeof(ixD3F2_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD3F2_MSI_MAP_ADDR_LO", REG_SMC, 0x8000033, &ixD3F2_MSI_MAP_ADDR_LO[0], sizeof(ixD3F2_MSI_MAP_ADDR_LO)/sizeof(ixD3F2_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F2_MSI_MAP_ADDR_HI", REG_SMC, 0x8000034, &ixD3F2_MSI_MAP_ADDR_HI[0], sizeof(ixD3F2_MSI_MAP_ADDR_HI)/sizeof(ixD3F2_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F2_PCIE_PORT_INDEX", REG_SMC, 0x8000038, &ixD3F2_PCIE_PORT_INDEX[0], sizeof(ixD3F2_PCIE_PORT_INDEX)/sizeof(ixD3F2_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD3F2_PCIE_PORT_DATA", REG_SMC, 0x8000039, &ixD3F2_PCIE_PORT_DATA[0], sizeof(ixD3F2_PCIE_PORT_DATA)/sizeof(ixD3F2_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x8000040, &ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x8000041, &ixD3F2_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x8000042, &ixD3F2_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x8000043, &ixD3F2_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F2_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x8000044, &ixD3F2_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x8000045, &ixD3F2_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F2_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F2_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x8000046, &ixD3F2_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F2_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F2_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD3F2_PCIE_PORT_VC_STATUS", REG_SMC, 0x8000047, &ixD3F2_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F2_PCIE_PORT_VC_STATUS)/sizeof(ixD3F2_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD3F2_PCIE_PORT_VC_CNTL", REG_SMC, 0x8000047, &ixD3F2_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F2_PCIE_PORT_VC_CNTL)/sizeof(ixD3F2_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x8000048, &ixD3F2_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F2_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F2_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x8000049, &ixD3F2_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F2_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F2_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x800004a, &ixD3F2_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F2_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F2_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x800004b, &ixD3F2_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F2_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F2_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x800004c, &ixD3F2_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F2_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F2_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x800004d, &ixD3F2_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F2_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F2_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x8000050, &ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x8000051, &ixD3F2_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x8000052, &ixD3F2_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F2_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x8000054, &ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x8000055, &ixD3F2_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F2_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F2_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F2_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x8000056, &ixD3F2_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F2_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F2_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F2_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x8000057, &ixD3F2_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F2_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F2_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD3F2_PCIE_CORR_ERR_STATUS", REG_SMC, 0x8000058, &ixD3F2_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F2_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F2_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F2_PCIE_CORR_ERR_MASK", REG_SMC, 0x8000059, &ixD3F2_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F2_PCIE_CORR_ERR_MASK)/sizeof(ixD3F2_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F2_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x800005a, &ixD3F2_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F2_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F2_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_HDR_LOG0", REG_SMC, 0x800005b, &ixD3F2_PCIE_HDR_LOG0[0], sizeof(ixD3F2_PCIE_HDR_LOG0)/sizeof(ixD3F2_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD3F2_PCIE_HDR_LOG1", REG_SMC, 0x800005c, &ixD3F2_PCIE_HDR_LOG1[0], sizeof(ixD3F2_PCIE_HDR_LOG1)/sizeof(ixD3F2_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_HDR_LOG2", REG_SMC, 0x800005d, &ixD3F2_PCIE_HDR_LOG2[0], sizeof(ixD3F2_PCIE_HDR_LOG2)/sizeof(ixD3F2_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD3F2_PCIE_HDR_LOG3", REG_SMC, 0x800005e, &ixD3F2_PCIE_HDR_LOG3[0], sizeof(ixD3F2_PCIE_HDR_LOG3)/sizeof(ixD3F2_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD3F2_PCIE_ROOT_ERR_CMD", REG_SMC, 0x800005f, &ixD3F2_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F2_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F2_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD3F2_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x8000060, &ixD3F2_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F2_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F2_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F2_PCIE_ERR_SRC_ID", REG_SMC, 0x8000061, &ixD3F2_PCIE_ERR_SRC_ID[0], sizeof(ixD3F2_PCIE_ERR_SRC_ID)/sizeof(ixD3F2_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD3F2_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x8000062, &ixD3F2_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD3F2_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x8000063, &ixD3F2_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x8000064, &ixD3F2_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD3F2_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x8000065, &ixD3F2_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F2_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x800009c, &ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LINK_CNTL3", REG_SMC, 0x800009d, &ixD3F2_PCIE_LINK_CNTL3[0], sizeof(ixD3F2_PCIE_LINK_CNTL3)/sizeof(ixD3F2_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x800009e, &ixD3F2_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F2_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F2_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x800009f, &ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x80000a0, &ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x80000a1, &ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x80000a2, &ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x80000a3, &ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x80000a4, &ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x80000a5, &ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x80000a6, &ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F2_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x80000a8, &ixD3F2_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PCIE_ACS_CNTL", REG_SMC, 0x80000a9, &ixD3F2_PCIE_ACS_CNTL[0], sizeof(ixD3F2_PCIE_ACS_CNTL)/sizeof(ixD3F2_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_ACS_CAP", REG_SMC, 0x80000a9, &ixD3F2_PCIE_ACS_CAP[0], sizeof(ixD3F2_PCIE_ACS_CAP)/sizeof(ixD3F2_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x80000bc, &ixD3F2_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F2_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F2_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_CNTL", REG_SMC, 0x80000bd, &ixD3F2_PCIE_MC_CNTL[0], sizeof(ixD3F2_PCIE_MC_CNTL)/sizeof(ixD3F2_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_CAP", REG_SMC, 0x80000bd, &ixD3F2_PCIE_MC_CAP[0], sizeof(ixD3F2_PCIE_MC_CAP)/sizeof(ixD3F2_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_ADDR0", REG_SMC, 0x80000be, &ixD3F2_PCIE_MC_ADDR0[0], sizeof(ixD3F2_PCIE_MC_ADDR0)/sizeof(ixD3F2_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_ADDR1", REG_SMC, 0x80000bf, &ixD3F2_PCIE_MC_ADDR1[0], sizeof(ixD3F2_PCIE_MC_ADDR1)/sizeof(ixD3F2_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_RCV0", REG_SMC, 0x80000c0, &ixD3F2_PCIE_MC_RCV0[0], sizeof(ixD3F2_PCIE_MC_RCV0)/sizeof(ixD3F2_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_RCV1", REG_SMC, 0x80000c1, &ixD3F2_PCIE_MC_RCV1[0], sizeof(ixD3F2_PCIE_MC_RCV1)/sizeof(ixD3F2_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x80000c2, &ixD3F2_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F2_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F2_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x80000c3, &ixD3F2_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F2_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F2_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x80000c4, &ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x80000c5, &ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F2_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x80000c6, &ixD3F2_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F2_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F2_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD3F2_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x80000c7, &ixD3F2_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F2_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F2_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP", REG_SMC, 0x81, &ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP[0], sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP)/sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_NP[0]), 0, 0 },
+	{ "mmPCIE_BAR1_CAP", REG_MMIO, 0x81, &mmPCIE_BAR1_CAP[0], sizeof(mmPCIE_BAR1_CAP)/sizeof(mmPCIE_BAR1_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL", REG_SMC, 0x82, &ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL[0], sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL)/sizeof(ixD2F1_PCIE_RX_CREDITS_ALLOCATED_CPL[0]), 0, 0 },
+	{ "mmPCIE_BAR1_CNTL", REG_MMIO, 0x82, &mmPCIE_BAR1_CNTL[0], sizeof(mmPCIE_BAR1_CNTL)/sizeof(mmPCIE_BAR1_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL", REG_SMC, 0x83, &ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL[0], sizeof(ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL)/sizeof(ixD2F1_PCIEP_ERROR_INJECT_PHYSICAL[0]), 0, 0 },
+	{ "mmPCIE_BAR2_CAP", REG_MMIO, 0x83, &mmPCIE_BAR2_CAP[0], sizeof(mmPCIE_BAR2_CAP)/sizeof(mmPCIE_BAR2_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION", REG_SMC, 0x84, &ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION[0], sizeof(ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION)/sizeof(ixD2F1_PCIEP_ERROR_INJECT_TRANSACTION[0]), 0, 0 },
+	{ "mmPCIE_BAR2_CNTL", REG_MMIO, 0x84, &mmPCIE_BAR2_CNTL[0], sizeof(mmPCIE_BAR2_CNTL)/sizeof(mmPCIE_BAR2_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR3_CAP", REG_MMIO, 0x85, &mmPCIE_BAR3_CAP[0], sizeof(mmPCIE_BAR3_CAP)/sizeof(mmPCIE_BAR3_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR3_CNTL", REG_MMIO, 0x86, &mmPCIE_BAR3_CNTL[0], sizeof(mmPCIE_BAR3_CNTL)/sizeof(mmPCIE_BAR3_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR4_CAP", REG_MMIO, 0x87, &mmPCIE_BAR4_CAP[0], sizeof(mmPCIE_BAR4_CAP)/sizeof(mmPCIE_BAR4_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR4_CNTL", REG_MMIO, 0x88, &mmPCIE_BAR4_CNTL[0], sizeof(mmPCIE_BAR4_CNTL)/sizeof(mmPCIE_BAR4_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR5_CAP", REG_MMIO, 0x89, &mmPCIE_BAR5_CAP[0], sizeof(mmPCIE_BAR5_CAP)/sizeof(mmPCIE_BAR5_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR5_CNTL", REG_MMIO, 0x8a, &mmPCIE_BAR5_CNTL[0], sizeof(mmPCIE_BAR5_CNTL)/sizeof(mmPCIE_BAR5_CNTL[0]), 0, 0 },
+	{ "mmPCIE_BAR6_CAP", REG_MMIO, 0x8b, &mmPCIE_BAR6_CAP[0], sizeof(mmPCIE_BAR6_CAP)/sizeof(mmPCIE_BAR6_CAP[0]), 0, 0 },
+	{ "mmPCIE_BAR6_CNTL", REG_MMIO, 0x8c, &mmPCIE_BAR6_CNTL[0], sizeof(mmPCIE_BAR6_CNTL)/sizeof(mmPCIE_BAR6_CNTL[0]), 0, 0 },
+	{ "mmBASE_ADDR_6", REG_MMIO, 0x9, &mmBASE_ADDR_6[0], sizeof(mmBASE_ADDR_6)/sizeof(mmBASE_ADDR_6[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_ENH_CAP_LIST", REG_MMIO, 0x90, &mmPCIE_PWR_BUDGET_ENH_CAP_LIST[0], sizeof(mmPCIE_PWR_BUDGET_ENH_CAP_LIST)/sizeof(mmPCIE_PWR_BUDGET_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_VENDOR_ID", REG_SMC, 0x9000000, &ixD3F3_VENDOR_ID[0], sizeof(ixD3F3_VENDOR_ID)/sizeof(ixD3F3_VENDOR_ID[0]), 0, 0 },
+	{ "ixD3F3_COMMAND", REG_SMC, 0x9000001, &ixD3F3_COMMAND[0], sizeof(ixD3F3_COMMAND)/sizeof(ixD3F3_COMMAND[0]), 0, 0 },
+	{ "ixD3F3_STATUS", REG_SMC, 0x9000001, &ixD3F3_STATUS[0], sizeof(ixD3F3_STATUS)/sizeof(ixD3F3_STATUS[0]), 0, 0 },
+	{ "ixD3F3_PROG_INTERFACE", REG_SMC, 0x9000002, &ixD3F3_PROG_INTERFACE[0], sizeof(ixD3F3_PROG_INTERFACE)/sizeof(ixD3F3_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD3F3_REVISION_ID", REG_SMC, 0x9000002, &ixD3F3_REVISION_ID[0], sizeof(ixD3F3_REVISION_ID)/sizeof(ixD3F3_REVISION_ID[0]), 0, 0 },
+	{ "ixD3F3_BASE_CLASS", REG_SMC, 0x9000002, &ixD3F3_BASE_CLASS[0], sizeof(ixD3F3_BASE_CLASS)/sizeof(ixD3F3_BASE_CLASS[0]), 0, 0 },
+	{ "ixD3F3_SUB_CLASS", REG_SMC, 0x9000002, &ixD3F3_SUB_CLASS[0], sizeof(ixD3F3_SUB_CLASS)/sizeof(ixD3F3_SUB_CLASS[0]), 0, 0 },
+	{ "ixD3F3_CACHE_LINE", REG_SMC, 0x9000003, &ixD3F3_CACHE_LINE[0], sizeof(ixD3F3_CACHE_LINE)/sizeof(ixD3F3_CACHE_LINE[0]), 0, 0 },
+	{ "ixD3F3_LATENCY", REG_SMC, 0x9000003, &ixD3F3_LATENCY[0], sizeof(ixD3F3_LATENCY)/sizeof(ixD3F3_LATENCY[0]), 0, 0 },
+	{ "ixD3F3_HEADER", REG_SMC, 0x9000003, &ixD3F3_HEADER[0], sizeof(ixD3F3_HEADER)/sizeof(ixD3F3_HEADER[0]), 0, 0 },
+	{ "ixD3F3_BIST", REG_SMC, 0x9000003, &ixD3F3_BIST[0], sizeof(ixD3F3_BIST)/sizeof(ixD3F3_BIST[0]), 0, 0 },
+	{ "ixD3F3_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0x9000006, &ixD3F3_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F3_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F3_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD3F3_SECONDARY_STATUS", REG_SMC, 0x9000007, &ixD3F3_SECONDARY_STATUS[0], sizeof(ixD3F3_SECONDARY_STATUS)/sizeof(ixD3F3_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD3F3_IO_BASE_LIMIT", REG_SMC, 0x9000007, &ixD3F3_IO_BASE_LIMIT[0], sizeof(ixD3F3_IO_BASE_LIMIT)/sizeof(ixD3F3_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F3_MEM_BASE_LIMIT", REG_SMC, 0x9000008, &ixD3F3_MEM_BASE_LIMIT[0], sizeof(ixD3F3_MEM_BASE_LIMIT)/sizeof(ixD3F3_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F3_PREF_BASE_LIMIT", REG_SMC, 0x9000009, &ixD3F3_PREF_BASE_LIMIT[0], sizeof(ixD3F3_PREF_BASE_LIMIT)/sizeof(ixD3F3_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F3_PREF_BASE_UPPER", REG_SMC, 0x900000a, &ixD3F3_PREF_BASE_UPPER[0], sizeof(ixD3F3_PREF_BASE_UPPER)/sizeof(ixD3F3_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD3F3_PREF_LIMIT_UPPER", REG_SMC, 0x900000b, &ixD3F3_PREF_LIMIT_UPPER[0], sizeof(ixD3F3_PREF_LIMIT_UPPER)/sizeof(ixD3F3_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD3F3_IO_BASE_LIMIT_HI", REG_SMC, 0x900000c, &ixD3F3_IO_BASE_LIMIT_HI[0], sizeof(ixD3F3_IO_BASE_LIMIT_HI)/sizeof(ixD3F3_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD3F3_CAP_PTR", REG_SMC, 0x900000d, &ixD3F3_CAP_PTR[0], sizeof(ixD3F3_CAP_PTR)/sizeof(ixD3F3_CAP_PTR[0]), 0, 0 },
+	{ "ixD3F3_IRQ_BRIDGE_CNTL", REG_SMC, 0x900000f, &ixD3F3_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F3_IRQ_BRIDGE_CNTL)/sizeof(ixD3F3_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F3_INTERRUPT_LINE", REG_SMC, 0x900000f, &ixD3F3_INTERRUPT_LINE[0], sizeof(ixD3F3_INTERRUPT_LINE)/sizeof(ixD3F3_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD3F3_INTERRUPT_PIN", REG_SMC, 0x900000f, &ixD3F3_INTERRUPT_PIN[0], sizeof(ixD3F3_INTERRUPT_PIN)/sizeof(ixD3F3_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD3F3_EXT_BRIDGE_CNTL", REG_SMC, 0x9000010, &ixD3F3_EXT_BRIDGE_CNTL[0], sizeof(ixD3F3_EXT_BRIDGE_CNTL)/sizeof(ixD3F3_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PMI_CAP_LIST", REG_SMC, 0x9000014, &ixD3F3_PMI_CAP_LIST[0], sizeof(ixD3F3_PMI_CAP_LIST)/sizeof(ixD3F3_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PMI_CAP", REG_SMC, 0x9000014, &ixD3F3_PMI_CAP[0], sizeof(ixD3F3_PMI_CAP)/sizeof(ixD3F3_PMI_CAP[0]), 0, 0 },
+	{ "ixD3F3_PMI_STATUS_CNTL", REG_SMC, 0x9000015, &ixD3F3_PMI_STATUS_CNTL[0], sizeof(ixD3F3_PMI_STATUS_CNTL)/sizeof(ixD3F3_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_CAP_LIST", REG_SMC, 0x9000016, &ixD3F3_PCIE_CAP_LIST[0], sizeof(ixD3F3_PCIE_CAP_LIST)/sizeof(ixD3F3_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PCIE_CAP", REG_SMC, 0x9000016, &ixD3F3_PCIE_CAP[0], sizeof(ixD3F3_PCIE_CAP)/sizeof(ixD3F3_PCIE_CAP[0]), 0, 0 },
+	{ "ixD3F3_DEVICE_CAP", REG_SMC, 0x9000017, &ixD3F3_DEVICE_CAP[0], sizeof(ixD3F3_DEVICE_CAP)/sizeof(ixD3F3_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD3F3_DEVICE_STATUS", REG_SMC, 0x9000018, &ixD3F3_DEVICE_STATUS[0], sizeof(ixD3F3_DEVICE_STATUS)/sizeof(ixD3F3_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD3F3_DEVICE_CNTL", REG_SMC, 0x9000018, &ixD3F3_DEVICE_CNTL[0], sizeof(ixD3F3_DEVICE_CNTL)/sizeof(ixD3F3_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD3F3_LINK_CAP", REG_SMC, 0x9000019, &ixD3F3_LINK_CAP[0], sizeof(ixD3F3_LINK_CAP)/sizeof(ixD3F3_LINK_CAP[0]), 0, 0 },
+	{ "ixD3F3_LINK_STATUS", REG_SMC, 0x900001a, &ixD3F3_LINK_STATUS[0], sizeof(ixD3F3_LINK_STATUS)/sizeof(ixD3F3_LINK_STATUS[0]), 0, 0 },
+	{ "ixD3F3_LINK_CNTL", REG_SMC, 0x900001a, &ixD3F3_LINK_CNTL[0], sizeof(ixD3F3_LINK_CNTL)/sizeof(ixD3F3_LINK_CNTL[0]), 0, 0 },
+	{ "ixD3F3_SLOT_CAP", REG_SMC, 0x900001b, &ixD3F3_SLOT_CAP[0], sizeof(ixD3F3_SLOT_CAP)/sizeof(ixD3F3_SLOT_CAP[0]), 0, 0 },
+	{ "ixD3F3_SLOT_STATUS", REG_SMC, 0x900001c, &ixD3F3_SLOT_STATUS[0], sizeof(ixD3F3_SLOT_STATUS)/sizeof(ixD3F3_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD3F3_SLOT_CNTL", REG_SMC, 0x900001c, &ixD3F3_SLOT_CNTL[0], sizeof(ixD3F3_SLOT_CNTL)/sizeof(ixD3F3_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD3F3_ROOT_CNTL", REG_SMC, 0x900001d, &ixD3F3_ROOT_CNTL[0], sizeof(ixD3F3_ROOT_CNTL)/sizeof(ixD3F3_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD3F3_ROOT_CAP", REG_SMC, 0x900001d, &ixD3F3_ROOT_CAP[0], sizeof(ixD3F3_ROOT_CAP)/sizeof(ixD3F3_ROOT_CAP[0]), 0, 0 },
+	{ "ixD3F3_ROOT_STATUS", REG_SMC, 0x900001e, &ixD3F3_ROOT_STATUS[0], sizeof(ixD3F3_ROOT_STATUS)/sizeof(ixD3F3_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD3F3_DEVICE_CAP2", REG_SMC, 0x900001f, &ixD3F3_DEVICE_CAP2[0], sizeof(ixD3F3_DEVICE_CAP2)/sizeof(ixD3F3_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD3F3_DEVICE_STATUS2", REG_SMC, 0x9000020, &ixD3F3_DEVICE_STATUS2[0], sizeof(ixD3F3_DEVICE_STATUS2)/sizeof(ixD3F3_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD3F3_DEVICE_CNTL2", REG_SMC, 0x9000020, &ixD3F3_DEVICE_CNTL2[0], sizeof(ixD3F3_DEVICE_CNTL2)/sizeof(ixD3F3_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD3F3_LINK_CAP2", REG_SMC, 0x9000021, &ixD3F3_LINK_CAP2[0], sizeof(ixD3F3_LINK_CAP2)/sizeof(ixD3F3_LINK_CAP2[0]), 0, 0 },
+	{ "ixD3F3_LINK_STATUS2", REG_SMC, 0x9000022, &ixD3F3_LINK_STATUS2[0], sizeof(ixD3F3_LINK_STATUS2)/sizeof(ixD3F3_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD3F3_LINK_CNTL2", REG_SMC, 0x9000022, &ixD3F3_LINK_CNTL2[0], sizeof(ixD3F3_LINK_CNTL2)/sizeof(ixD3F3_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD3F3_SLOT_CAP2", REG_SMC, 0x9000023, &ixD3F3_SLOT_CAP2[0], sizeof(ixD3F3_SLOT_CAP2)/sizeof(ixD3F3_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD3F3_SLOT_STATUS2", REG_SMC, 0x9000024, &ixD3F3_SLOT_STATUS2[0], sizeof(ixD3F3_SLOT_STATUS2)/sizeof(ixD3F3_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD3F3_SLOT_CNTL2", REG_SMC, 0x9000024, &ixD3F3_SLOT_CNTL2[0], sizeof(ixD3F3_SLOT_CNTL2)/sizeof(ixD3F3_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD3F3_MSI_CAP_LIST", REG_SMC, 0x9000028, &ixD3F3_MSI_CAP_LIST[0], sizeof(ixD3F3_MSI_CAP_LIST)/sizeof(ixD3F3_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_MSI_MSG_ADDR_LO", REG_SMC, 0x9000029, &ixD3F3_MSI_MSG_ADDR_LO[0], sizeof(ixD3F3_MSI_MSG_ADDR_LO)/sizeof(ixD3F3_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F3_MSI_MSG_ADDR_HI", REG_SMC, 0x900002a, &ixD3F3_MSI_MSG_ADDR_HI[0], sizeof(ixD3F3_MSI_MSG_ADDR_HI)/sizeof(ixD3F3_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F3_MSI_MSG_DATA", REG_SMC, 0x900002a, &ixD3F3_MSI_MSG_DATA[0], sizeof(ixD3F3_MSI_MSG_DATA)/sizeof(ixD3F3_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD3F3_MSI_MSG_DATA_64", REG_SMC, 0x900002b, &ixD3F3_MSI_MSG_DATA_64[0], sizeof(ixD3F3_MSI_MSG_DATA_64)/sizeof(ixD3F3_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD3F3_SSID_CAP_LIST", REG_SMC, 0x9000030, &ixD3F3_SSID_CAP_LIST[0], sizeof(ixD3F3_SSID_CAP_LIST)/sizeof(ixD3F3_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_SSID_CAP", REG_SMC, 0x9000031, &ixD3F3_SSID_CAP[0], sizeof(ixD3F3_SSID_CAP)/sizeof(ixD3F3_SSID_CAP[0]), 0, 0 },
+	{ "ixD3F3_MSI_MAP_CAP_LIST", REG_SMC, 0x9000032, &ixD3F3_MSI_MAP_CAP_LIST[0], sizeof(ixD3F3_MSI_MAP_CAP_LIST)/sizeof(ixD3F3_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_MSI_MAP_CAP", REG_SMC, 0x9000032, &ixD3F3_MSI_MAP_CAP[0], sizeof(ixD3F3_MSI_MAP_CAP)/sizeof(ixD3F3_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD3F3_MSI_MAP_ADDR_LO", REG_SMC, 0x9000033, &ixD3F3_MSI_MAP_ADDR_LO[0], sizeof(ixD3F3_MSI_MAP_ADDR_LO)/sizeof(ixD3F3_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F3_MSI_MAP_ADDR_HI", REG_SMC, 0x9000034, &ixD3F3_MSI_MAP_ADDR_HI[0], sizeof(ixD3F3_MSI_MAP_ADDR_HI)/sizeof(ixD3F3_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F3_PCIE_PORT_INDEX", REG_SMC, 0x9000038, &ixD3F3_PCIE_PORT_INDEX[0], sizeof(ixD3F3_PCIE_PORT_INDEX)/sizeof(ixD3F3_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD3F3_PCIE_PORT_DATA", REG_SMC, 0x9000039, &ixD3F3_PCIE_PORT_DATA[0], sizeof(ixD3F3_PCIE_PORT_DATA)/sizeof(ixD3F3_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0x9000040, &ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0x9000041, &ixD3F3_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0x9000042, &ixD3F3_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0x9000043, &ixD3F3_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F3_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0x9000044, &ixD3F3_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0x9000045, &ixD3F3_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F3_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F3_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0x9000046, &ixD3F3_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F3_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F3_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD3F3_PCIE_PORT_VC_STATUS", REG_SMC, 0x9000047, &ixD3F3_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F3_PCIE_PORT_VC_STATUS)/sizeof(ixD3F3_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD3F3_PCIE_PORT_VC_CNTL", REG_SMC, 0x9000047, &ixD3F3_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F3_PCIE_PORT_VC_CNTL)/sizeof(ixD3F3_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0x9000048, &ixD3F3_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F3_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F3_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0x9000049, &ixD3F3_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F3_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F3_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0x900004a, &ixD3F3_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F3_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F3_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0x900004b, &ixD3F3_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F3_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F3_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0x900004c, &ixD3F3_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F3_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F3_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0x900004d, &ixD3F3_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F3_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F3_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0x9000050, &ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0x9000051, &ixD3F3_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0x9000052, &ixD3F3_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F3_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0x9000054, &ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0x9000055, &ixD3F3_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F3_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F3_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F3_PCIE_UNCORR_ERR_MASK", REG_SMC, 0x9000056, &ixD3F3_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F3_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F3_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F3_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0x9000057, &ixD3F3_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F3_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F3_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD3F3_PCIE_CORR_ERR_STATUS", REG_SMC, 0x9000058, &ixD3F3_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F3_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F3_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F3_PCIE_CORR_ERR_MASK", REG_SMC, 0x9000059, &ixD3F3_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F3_PCIE_CORR_ERR_MASK)/sizeof(ixD3F3_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F3_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0x900005a, &ixD3F3_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F3_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F3_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_HDR_LOG0", REG_SMC, 0x900005b, &ixD3F3_PCIE_HDR_LOG0[0], sizeof(ixD3F3_PCIE_HDR_LOG0)/sizeof(ixD3F3_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD3F3_PCIE_HDR_LOG1", REG_SMC, 0x900005c, &ixD3F3_PCIE_HDR_LOG1[0], sizeof(ixD3F3_PCIE_HDR_LOG1)/sizeof(ixD3F3_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_HDR_LOG2", REG_SMC, 0x900005d, &ixD3F3_PCIE_HDR_LOG2[0], sizeof(ixD3F3_PCIE_HDR_LOG2)/sizeof(ixD3F3_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD3F3_PCIE_HDR_LOG3", REG_SMC, 0x900005e, &ixD3F3_PCIE_HDR_LOG3[0], sizeof(ixD3F3_PCIE_HDR_LOG3)/sizeof(ixD3F3_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD3F3_PCIE_ROOT_ERR_CMD", REG_SMC, 0x900005f, &ixD3F3_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F3_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F3_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD3F3_PCIE_ROOT_ERR_STATUS", REG_SMC, 0x9000060, &ixD3F3_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F3_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F3_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F3_PCIE_ERR_SRC_ID", REG_SMC, 0x9000061, &ixD3F3_PCIE_ERR_SRC_ID[0], sizeof(ixD3F3_PCIE_ERR_SRC_ID)/sizeof(ixD3F3_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD3F3_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0x9000062, &ixD3F3_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD3F3_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0x9000063, &ixD3F3_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0x9000064, &ixD3F3_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD3F3_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0x9000065, &ixD3F3_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F3_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0x900009c, &ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LINK_CNTL3", REG_SMC, 0x900009d, &ixD3F3_PCIE_LINK_CNTL3[0], sizeof(ixD3F3_PCIE_LINK_CNTL3)/sizeof(ixD3F3_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_ERROR_STATUS", REG_SMC, 0x900009e, &ixD3F3_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F3_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F3_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0x900009f, &ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0x90000a0, &ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0x90000a1, &ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0x90000a2, &ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0x90000a3, &ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0x90000a4, &ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0x90000a5, &ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0x90000a6, &ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F3_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0x90000a8, &ixD3F3_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PCIE_ACS_CNTL", REG_SMC, 0x90000a9, &ixD3F3_PCIE_ACS_CNTL[0], sizeof(ixD3F3_PCIE_ACS_CNTL)/sizeof(ixD3F3_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_ACS_CAP", REG_SMC, 0x90000a9, &ixD3F3_PCIE_ACS_CAP[0], sizeof(ixD3F3_PCIE_ACS_CAP)/sizeof(ixD3F3_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0x90000bc, &ixD3F3_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F3_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F3_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_CNTL", REG_SMC, 0x90000bd, &ixD3F3_PCIE_MC_CNTL[0], sizeof(ixD3F3_PCIE_MC_CNTL)/sizeof(ixD3F3_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_CAP", REG_SMC, 0x90000bd, &ixD3F3_PCIE_MC_CAP[0], sizeof(ixD3F3_PCIE_MC_CAP)/sizeof(ixD3F3_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_ADDR0", REG_SMC, 0x90000be, &ixD3F3_PCIE_MC_ADDR0[0], sizeof(ixD3F3_PCIE_MC_ADDR0)/sizeof(ixD3F3_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_ADDR1", REG_SMC, 0x90000bf, &ixD3F3_PCIE_MC_ADDR1[0], sizeof(ixD3F3_PCIE_MC_ADDR1)/sizeof(ixD3F3_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_RCV0", REG_SMC, 0x90000c0, &ixD3F3_PCIE_MC_RCV0[0], sizeof(ixD3F3_PCIE_MC_RCV0)/sizeof(ixD3F3_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_RCV1", REG_SMC, 0x90000c1, &ixD3F3_PCIE_MC_RCV1[0], sizeof(ixD3F3_PCIE_MC_RCV1)/sizeof(ixD3F3_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_BLOCK_ALL0", REG_SMC, 0x90000c2, &ixD3F3_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F3_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F3_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_BLOCK_ALL1", REG_SMC, 0x90000c3, &ixD3F3_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F3_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F3_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0x90000c4, &ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0x90000c5, &ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F3_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0x90000c6, &ixD3F3_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F3_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F3_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD3F3_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0x90000c7, &ixD3F3_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F3_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F3_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_DATA_SELECT", REG_MMIO, 0x91, &mmPCIE_PWR_BUDGET_DATA_SELECT[0], sizeof(mmPCIE_PWR_BUDGET_DATA_SELECT)/sizeof(mmPCIE_PWR_BUDGET_DATA_SELECT[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_DATA", REG_MMIO, 0x92, &mmPCIE_PWR_BUDGET_DATA[0], sizeof(mmPCIE_PWR_BUDGET_DATA)/sizeof(mmPCIE_PWR_BUDGET_DATA[0]), 0, 0 },
+	{ "mmPCIE_PWR_BUDGET_CAP", REG_MMIO, 0x93, &mmPCIE_PWR_BUDGET_CAP[0], sizeof(mmPCIE_PWR_BUDGET_CAP)/sizeof(mmPCIE_PWR_BUDGET_CAP[0]), 0, 0 },
+	{ "mmPCIE_DPA_ENH_CAP_LIST", REG_MMIO, 0x94, &mmPCIE_DPA_ENH_CAP_LIST[0], sizeof(mmPCIE_DPA_ENH_CAP_LIST)/sizeof(mmPCIE_DPA_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_DPA_CAP", REG_MMIO, 0x95, &mmPCIE_DPA_CAP[0], sizeof(mmPCIE_DPA_CAP)/sizeof(mmPCIE_DPA_CAP[0]), 0, 0 },
+	{ "mmPCIE_DPA_LATENCY_INDICATOR", REG_MMIO, 0x96, &mmPCIE_DPA_LATENCY_INDICATOR[0], sizeof(mmPCIE_DPA_LATENCY_INDICATOR)/sizeof(mmPCIE_DPA_LATENCY_INDICATOR[0]), 0, 0 },
+	{ "mmPCIE_DPA_STATUS", REG_MMIO, 0x97, &mmPCIE_DPA_STATUS[0], sizeof(mmPCIE_DPA_STATUS)/sizeof(mmPCIE_DPA_STATUS[0]), 0, 0 },
+	{ "mmPCIE_DPA_CNTL", REG_MMIO, 0x97, &mmPCIE_DPA_CNTL[0], sizeof(mmPCIE_DPA_CNTL)/sizeof(mmPCIE_DPA_CNTL[0]), 0, 0 },
+	{ "mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0", REG_MMIO, 0x98, &mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[0], sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0)/sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_0[0]), 0, 0 },
+	{ "mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4", REG_MMIO, 0x99, &mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[0], sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4)/sizeof(mmPCIE_DPA_SUBSTATE_PWR_ALLOC_4[0]), 0, 0 },
+	{ "mmPCIE_SECONDARY_ENH_CAP_LIST", REG_MMIO, 0x9c, &mmPCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(mmPCIE_SECONDARY_ENH_CAP_LIST)/sizeof(mmPCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_LINK_CNTL3", REG_MMIO, 0x9d, &mmPCIE_LINK_CNTL3[0], sizeof(mmPCIE_LINK_CNTL3)/sizeof(mmPCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "mmPCIE_LANE_ERROR_STATUS", REG_MMIO, 0x9e, &mmPCIE_LANE_ERROR_STATUS[0], sizeof(mmPCIE_LANE_ERROR_STATUS)/sizeof(mmPCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "mmPCIE_LANE_0_EQUALIZATION_CNTL", REG_MMIO, 0x9f, &mmPCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_2_EQUALIZATION_CNTL", REG_MMIO, 0xa0, &mmPCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_CNTL", REG_SMC, 0xa0, &ixD2F1_PCIE_LC_CNTL[0], sizeof(ixD2F1_PCIE_LC_CNTL)/sizeof(ixD2F1_PCIE_LC_CNTL[0]), 0, 0 },
+	{ "ixD3F4_VENDOR_ID", REG_SMC, 0xa000000, &ixD3F4_VENDOR_ID[0], sizeof(ixD3F4_VENDOR_ID)/sizeof(ixD3F4_VENDOR_ID[0]), 0, 0 },
+	{ "ixD3F4_COMMAND", REG_SMC, 0xa000001, &ixD3F4_COMMAND[0], sizeof(ixD3F4_COMMAND)/sizeof(ixD3F4_COMMAND[0]), 0, 0 },
+	{ "ixD3F4_STATUS", REG_SMC, 0xa000001, &ixD3F4_STATUS[0], sizeof(ixD3F4_STATUS)/sizeof(ixD3F4_STATUS[0]), 0, 0 },
+	{ "ixD3F4_PROG_INTERFACE", REG_SMC, 0xa000002, &ixD3F4_PROG_INTERFACE[0], sizeof(ixD3F4_PROG_INTERFACE)/sizeof(ixD3F4_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD3F4_REVISION_ID", REG_SMC, 0xa000002, &ixD3F4_REVISION_ID[0], sizeof(ixD3F4_REVISION_ID)/sizeof(ixD3F4_REVISION_ID[0]), 0, 0 },
+	{ "ixD3F4_BASE_CLASS", REG_SMC, 0xa000002, &ixD3F4_BASE_CLASS[0], sizeof(ixD3F4_BASE_CLASS)/sizeof(ixD3F4_BASE_CLASS[0]), 0, 0 },
+	{ "ixD3F4_SUB_CLASS", REG_SMC, 0xa000002, &ixD3F4_SUB_CLASS[0], sizeof(ixD3F4_SUB_CLASS)/sizeof(ixD3F4_SUB_CLASS[0]), 0, 0 },
+	{ "ixD3F4_CACHE_LINE", REG_SMC, 0xa000003, &ixD3F4_CACHE_LINE[0], sizeof(ixD3F4_CACHE_LINE)/sizeof(ixD3F4_CACHE_LINE[0]), 0, 0 },
+	{ "ixD3F4_LATENCY", REG_SMC, 0xa000003, &ixD3F4_LATENCY[0], sizeof(ixD3F4_LATENCY)/sizeof(ixD3F4_LATENCY[0]), 0, 0 },
+	{ "ixD3F4_HEADER", REG_SMC, 0xa000003, &ixD3F4_HEADER[0], sizeof(ixD3F4_HEADER)/sizeof(ixD3F4_HEADER[0]), 0, 0 },
+	{ "ixD3F4_BIST", REG_SMC, 0xa000003, &ixD3F4_BIST[0], sizeof(ixD3F4_BIST)/sizeof(ixD3F4_BIST[0]), 0, 0 },
+	{ "ixD3F4_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0xa000006, &ixD3F4_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F4_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F4_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD3F4_SECONDARY_STATUS", REG_SMC, 0xa000007, &ixD3F4_SECONDARY_STATUS[0], sizeof(ixD3F4_SECONDARY_STATUS)/sizeof(ixD3F4_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD3F4_IO_BASE_LIMIT", REG_SMC, 0xa000007, &ixD3F4_IO_BASE_LIMIT[0], sizeof(ixD3F4_IO_BASE_LIMIT)/sizeof(ixD3F4_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F4_MEM_BASE_LIMIT", REG_SMC, 0xa000008, &ixD3F4_MEM_BASE_LIMIT[0], sizeof(ixD3F4_MEM_BASE_LIMIT)/sizeof(ixD3F4_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F4_PREF_BASE_LIMIT", REG_SMC, 0xa000009, &ixD3F4_PREF_BASE_LIMIT[0], sizeof(ixD3F4_PREF_BASE_LIMIT)/sizeof(ixD3F4_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F4_PREF_BASE_UPPER", REG_SMC, 0xa00000a, &ixD3F4_PREF_BASE_UPPER[0], sizeof(ixD3F4_PREF_BASE_UPPER)/sizeof(ixD3F4_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD3F4_PREF_LIMIT_UPPER", REG_SMC, 0xa00000b, &ixD3F4_PREF_LIMIT_UPPER[0], sizeof(ixD3F4_PREF_LIMIT_UPPER)/sizeof(ixD3F4_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD3F4_IO_BASE_LIMIT_HI", REG_SMC, 0xa00000c, &ixD3F4_IO_BASE_LIMIT_HI[0], sizeof(ixD3F4_IO_BASE_LIMIT_HI)/sizeof(ixD3F4_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD3F4_CAP_PTR", REG_SMC, 0xa00000d, &ixD3F4_CAP_PTR[0], sizeof(ixD3F4_CAP_PTR)/sizeof(ixD3F4_CAP_PTR[0]), 0, 0 },
+	{ "ixD3F4_IRQ_BRIDGE_CNTL", REG_SMC, 0xa00000f, &ixD3F4_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F4_IRQ_BRIDGE_CNTL)/sizeof(ixD3F4_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F4_INTERRUPT_LINE", REG_SMC, 0xa00000f, &ixD3F4_INTERRUPT_LINE[0], sizeof(ixD3F4_INTERRUPT_LINE)/sizeof(ixD3F4_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD3F4_INTERRUPT_PIN", REG_SMC, 0xa00000f, &ixD3F4_INTERRUPT_PIN[0], sizeof(ixD3F4_INTERRUPT_PIN)/sizeof(ixD3F4_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD3F4_EXT_BRIDGE_CNTL", REG_SMC, 0xa000010, &ixD3F4_EXT_BRIDGE_CNTL[0], sizeof(ixD3F4_EXT_BRIDGE_CNTL)/sizeof(ixD3F4_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PMI_CAP_LIST", REG_SMC, 0xa000014, &ixD3F4_PMI_CAP_LIST[0], sizeof(ixD3F4_PMI_CAP_LIST)/sizeof(ixD3F4_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PMI_CAP", REG_SMC, 0xa000014, &ixD3F4_PMI_CAP[0], sizeof(ixD3F4_PMI_CAP)/sizeof(ixD3F4_PMI_CAP[0]), 0, 0 },
+	{ "ixD3F4_PMI_STATUS_CNTL", REG_SMC, 0xa000015, &ixD3F4_PMI_STATUS_CNTL[0], sizeof(ixD3F4_PMI_STATUS_CNTL)/sizeof(ixD3F4_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_CAP_LIST", REG_SMC, 0xa000016, &ixD3F4_PCIE_CAP_LIST[0], sizeof(ixD3F4_PCIE_CAP_LIST)/sizeof(ixD3F4_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PCIE_CAP", REG_SMC, 0xa000016, &ixD3F4_PCIE_CAP[0], sizeof(ixD3F4_PCIE_CAP)/sizeof(ixD3F4_PCIE_CAP[0]), 0, 0 },
+	{ "ixD3F4_DEVICE_CAP", REG_SMC, 0xa000017, &ixD3F4_DEVICE_CAP[0], sizeof(ixD3F4_DEVICE_CAP)/sizeof(ixD3F4_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD3F4_DEVICE_STATUS", REG_SMC, 0xa000018, &ixD3F4_DEVICE_STATUS[0], sizeof(ixD3F4_DEVICE_STATUS)/sizeof(ixD3F4_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD3F4_DEVICE_CNTL", REG_SMC, 0xa000018, &ixD3F4_DEVICE_CNTL[0], sizeof(ixD3F4_DEVICE_CNTL)/sizeof(ixD3F4_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD3F4_LINK_CAP", REG_SMC, 0xa000019, &ixD3F4_LINK_CAP[0], sizeof(ixD3F4_LINK_CAP)/sizeof(ixD3F4_LINK_CAP[0]), 0, 0 },
+	{ "ixD3F4_LINK_STATUS", REG_SMC, 0xa00001a, &ixD3F4_LINK_STATUS[0], sizeof(ixD3F4_LINK_STATUS)/sizeof(ixD3F4_LINK_STATUS[0]), 0, 0 },
+	{ "ixD3F4_LINK_CNTL", REG_SMC, 0xa00001a, &ixD3F4_LINK_CNTL[0], sizeof(ixD3F4_LINK_CNTL)/sizeof(ixD3F4_LINK_CNTL[0]), 0, 0 },
+	{ "ixD3F4_SLOT_CAP", REG_SMC, 0xa00001b, &ixD3F4_SLOT_CAP[0], sizeof(ixD3F4_SLOT_CAP)/sizeof(ixD3F4_SLOT_CAP[0]), 0, 0 },
+	{ "ixD3F4_SLOT_STATUS", REG_SMC, 0xa00001c, &ixD3F4_SLOT_STATUS[0], sizeof(ixD3F4_SLOT_STATUS)/sizeof(ixD3F4_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD3F4_SLOT_CNTL", REG_SMC, 0xa00001c, &ixD3F4_SLOT_CNTL[0], sizeof(ixD3F4_SLOT_CNTL)/sizeof(ixD3F4_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD3F4_ROOT_CNTL", REG_SMC, 0xa00001d, &ixD3F4_ROOT_CNTL[0], sizeof(ixD3F4_ROOT_CNTL)/sizeof(ixD3F4_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD3F4_ROOT_CAP", REG_SMC, 0xa00001d, &ixD3F4_ROOT_CAP[0], sizeof(ixD3F4_ROOT_CAP)/sizeof(ixD3F4_ROOT_CAP[0]), 0, 0 },
+	{ "ixD3F4_ROOT_STATUS", REG_SMC, 0xa00001e, &ixD3F4_ROOT_STATUS[0], sizeof(ixD3F4_ROOT_STATUS)/sizeof(ixD3F4_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD3F4_DEVICE_CAP2", REG_SMC, 0xa00001f, &ixD3F4_DEVICE_CAP2[0], sizeof(ixD3F4_DEVICE_CAP2)/sizeof(ixD3F4_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD3F4_DEVICE_STATUS2", REG_SMC, 0xa000020, &ixD3F4_DEVICE_STATUS2[0], sizeof(ixD3F4_DEVICE_STATUS2)/sizeof(ixD3F4_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD3F4_DEVICE_CNTL2", REG_SMC, 0xa000020, &ixD3F4_DEVICE_CNTL2[0], sizeof(ixD3F4_DEVICE_CNTL2)/sizeof(ixD3F4_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD3F4_LINK_CAP2", REG_SMC, 0xa000021, &ixD3F4_LINK_CAP2[0], sizeof(ixD3F4_LINK_CAP2)/sizeof(ixD3F4_LINK_CAP2[0]), 0, 0 },
+	{ "ixD3F4_LINK_STATUS2", REG_SMC, 0xa000022, &ixD3F4_LINK_STATUS2[0], sizeof(ixD3F4_LINK_STATUS2)/sizeof(ixD3F4_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD3F4_LINK_CNTL2", REG_SMC, 0xa000022, &ixD3F4_LINK_CNTL2[0], sizeof(ixD3F4_LINK_CNTL2)/sizeof(ixD3F4_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD3F4_SLOT_CAP2", REG_SMC, 0xa000023, &ixD3F4_SLOT_CAP2[0], sizeof(ixD3F4_SLOT_CAP2)/sizeof(ixD3F4_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD3F4_SLOT_STATUS2", REG_SMC, 0xa000024, &ixD3F4_SLOT_STATUS2[0], sizeof(ixD3F4_SLOT_STATUS2)/sizeof(ixD3F4_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD3F4_SLOT_CNTL2", REG_SMC, 0xa000024, &ixD3F4_SLOT_CNTL2[0], sizeof(ixD3F4_SLOT_CNTL2)/sizeof(ixD3F4_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD3F4_MSI_CAP_LIST", REG_SMC, 0xa000028, &ixD3F4_MSI_CAP_LIST[0], sizeof(ixD3F4_MSI_CAP_LIST)/sizeof(ixD3F4_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_MSI_MSG_ADDR_LO", REG_SMC, 0xa000029, &ixD3F4_MSI_MSG_ADDR_LO[0], sizeof(ixD3F4_MSI_MSG_ADDR_LO)/sizeof(ixD3F4_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F4_MSI_MSG_ADDR_HI", REG_SMC, 0xa00002a, &ixD3F4_MSI_MSG_ADDR_HI[0], sizeof(ixD3F4_MSI_MSG_ADDR_HI)/sizeof(ixD3F4_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F4_MSI_MSG_DATA", REG_SMC, 0xa00002a, &ixD3F4_MSI_MSG_DATA[0], sizeof(ixD3F4_MSI_MSG_DATA)/sizeof(ixD3F4_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD3F4_MSI_MSG_DATA_64", REG_SMC, 0xa00002b, &ixD3F4_MSI_MSG_DATA_64[0], sizeof(ixD3F4_MSI_MSG_DATA_64)/sizeof(ixD3F4_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD3F4_SSID_CAP_LIST", REG_SMC, 0xa000030, &ixD3F4_SSID_CAP_LIST[0], sizeof(ixD3F4_SSID_CAP_LIST)/sizeof(ixD3F4_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_SSID_CAP", REG_SMC, 0xa000031, &ixD3F4_SSID_CAP[0], sizeof(ixD3F4_SSID_CAP)/sizeof(ixD3F4_SSID_CAP[0]), 0, 0 },
+	{ "ixD3F4_MSI_MAP_CAP_LIST", REG_SMC, 0xa000032, &ixD3F4_MSI_MAP_CAP_LIST[0], sizeof(ixD3F4_MSI_MAP_CAP_LIST)/sizeof(ixD3F4_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_MSI_MAP_CAP", REG_SMC, 0xa000032, &ixD3F4_MSI_MAP_CAP[0], sizeof(ixD3F4_MSI_MAP_CAP)/sizeof(ixD3F4_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD3F4_MSI_MAP_ADDR_LO", REG_SMC, 0xa000033, &ixD3F4_MSI_MAP_ADDR_LO[0], sizeof(ixD3F4_MSI_MAP_ADDR_LO)/sizeof(ixD3F4_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F4_MSI_MAP_ADDR_HI", REG_SMC, 0xa000034, &ixD3F4_MSI_MAP_ADDR_HI[0], sizeof(ixD3F4_MSI_MAP_ADDR_HI)/sizeof(ixD3F4_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F4_PCIE_PORT_INDEX", REG_SMC, 0xa000038, &ixD3F4_PCIE_PORT_INDEX[0], sizeof(ixD3F4_PCIE_PORT_INDEX)/sizeof(ixD3F4_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD3F4_PCIE_PORT_DATA", REG_SMC, 0xa000039, &ixD3F4_PCIE_PORT_DATA[0], sizeof(ixD3F4_PCIE_PORT_DATA)/sizeof(ixD3F4_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0xa000040, &ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0xa000041, &ixD3F4_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0xa000042, &ixD3F4_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0xa000043, &ixD3F4_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F4_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0xa000044, &ixD3F4_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0xa000045, &ixD3F4_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F4_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F4_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0xa000046, &ixD3F4_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F4_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F4_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD3F4_PCIE_PORT_VC_STATUS", REG_SMC, 0xa000047, &ixD3F4_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F4_PCIE_PORT_VC_STATUS)/sizeof(ixD3F4_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD3F4_PCIE_PORT_VC_CNTL", REG_SMC, 0xa000047, &ixD3F4_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F4_PCIE_PORT_VC_CNTL)/sizeof(ixD3F4_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0xa000048, &ixD3F4_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F4_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F4_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0xa000049, &ixD3F4_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F4_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F4_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0xa00004a, &ixD3F4_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F4_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F4_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0xa00004b, &ixD3F4_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F4_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F4_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0xa00004c, &ixD3F4_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F4_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F4_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0xa00004d, &ixD3F4_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F4_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F4_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0xa000050, &ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0xa000051, &ixD3F4_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0xa000052, &ixD3F4_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F4_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0xa000054, &ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0xa000055, &ixD3F4_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F4_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F4_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F4_PCIE_UNCORR_ERR_MASK", REG_SMC, 0xa000056, &ixD3F4_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F4_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F4_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F4_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0xa000057, &ixD3F4_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F4_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F4_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD3F4_PCIE_CORR_ERR_STATUS", REG_SMC, 0xa000058, &ixD3F4_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F4_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F4_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F4_PCIE_CORR_ERR_MASK", REG_SMC, 0xa000059, &ixD3F4_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F4_PCIE_CORR_ERR_MASK)/sizeof(ixD3F4_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F4_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0xa00005a, &ixD3F4_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F4_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F4_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_HDR_LOG0", REG_SMC, 0xa00005b, &ixD3F4_PCIE_HDR_LOG0[0], sizeof(ixD3F4_PCIE_HDR_LOG0)/sizeof(ixD3F4_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD3F4_PCIE_HDR_LOG1", REG_SMC, 0xa00005c, &ixD3F4_PCIE_HDR_LOG1[0], sizeof(ixD3F4_PCIE_HDR_LOG1)/sizeof(ixD3F4_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_HDR_LOG2", REG_SMC, 0xa00005d, &ixD3F4_PCIE_HDR_LOG2[0], sizeof(ixD3F4_PCIE_HDR_LOG2)/sizeof(ixD3F4_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD3F4_PCIE_HDR_LOG3", REG_SMC, 0xa00005e, &ixD3F4_PCIE_HDR_LOG3[0], sizeof(ixD3F4_PCIE_HDR_LOG3)/sizeof(ixD3F4_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD3F4_PCIE_ROOT_ERR_CMD", REG_SMC, 0xa00005f, &ixD3F4_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F4_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F4_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD3F4_PCIE_ROOT_ERR_STATUS", REG_SMC, 0xa000060, &ixD3F4_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F4_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F4_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F4_PCIE_ERR_SRC_ID", REG_SMC, 0xa000061, &ixD3F4_PCIE_ERR_SRC_ID[0], sizeof(ixD3F4_PCIE_ERR_SRC_ID)/sizeof(ixD3F4_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD3F4_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0xa000062, &ixD3F4_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD3F4_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0xa000063, &ixD3F4_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0xa000064, &ixD3F4_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD3F4_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0xa000065, &ixD3F4_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F4_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0xa00009c, &ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LINK_CNTL3", REG_SMC, 0xa00009d, &ixD3F4_PCIE_LINK_CNTL3[0], sizeof(ixD3F4_PCIE_LINK_CNTL3)/sizeof(ixD3F4_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_ERROR_STATUS", REG_SMC, 0xa00009e, &ixD3F4_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F4_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F4_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0xa00009f, &ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0xa0000a0, &ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0xa0000a1, &ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0xa0000a2, &ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0xa0000a3, &ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0xa0000a4, &ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0xa0000a5, &ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0xa0000a6, &ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F4_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0xa0000a8, &ixD3F4_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PCIE_ACS_CNTL", REG_SMC, 0xa0000a9, &ixD3F4_PCIE_ACS_CNTL[0], sizeof(ixD3F4_PCIE_ACS_CNTL)/sizeof(ixD3F4_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_ACS_CAP", REG_SMC, 0xa0000a9, &ixD3F4_PCIE_ACS_CAP[0], sizeof(ixD3F4_PCIE_ACS_CAP)/sizeof(ixD3F4_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0xa0000bc, &ixD3F4_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F4_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F4_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_CNTL", REG_SMC, 0xa0000bd, &ixD3F4_PCIE_MC_CNTL[0], sizeof(ixD3F4_PCIE_MC_CNTL)/sizeof(ixD3F4_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_CAP", REG_SMC, 0xa0000bd, &ixD3F4_PCIE_MC_CAP[0], sizeof(ixD3F4_PCIE_MC_CAP)/sizeof(ixD3F4_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_ADDR0", REG_SMC, 0xa0000be, &ixD3F4_PCIE_MC_ADDR0[0], sizeof(ixD3F4_PCIE_MC_ADDR0)/sizeof(ixD3F4_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_ADDR1", REG_SMC, 0xa0000bf, &ixD3F4_PCIE_MC_ADDR1[0], sizeof(ixD3F4_PCIE_MC_ADDR1)/sizeof(ixD3F4_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_RCV0", REG_SMC, 0xa0000c0, &ixD3F4_PCIE_MC_RCV0[0], sizeof(ixD3F4_PCIE_MC_RCV0)/sizeof(ixD3F4_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_RCV1", REG_SMC, 0xa0000c1, &ixD3F4_PCIE_MC_RCV1[0], sizeof(ixD3F4_PCIE_MC_RCV1)/sizeof(ixD3F4_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_BLOCK_ALL0", REG_SMC, 0xa0000c2, &ixD3F4_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F4_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F4_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_BLOCK_ALL1", REG_SMC, 0xa0000c3, &ixD3F4_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F4_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F4_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0xa0000c4, &ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0xa0000c5, &ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F4_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0xa0000c6, &ixD3F4_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F4_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F4_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD3F4_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0xa0000c7, &ixD3F4_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F4_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F4_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "mmPCIE_LANE_4_EQUALIZATION_CNTL", REG_MMIO, 0xa1, &mmPCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_TRAINING_CNTL", REG_SMC, 0xa1, &ixD2F1_PCIE_LC_TRAINING_CNTL[0], sizeof(ixD2F1_PCIE_LC_TRAINING_CNTL)/sizeof(ixD2F1_PCIE_LC_TRAINING_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_6_EQUALIZATION_CNTL", REG_MMIO, 0xa2, &mmPCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_LINK_WIDTH_CNTL", REG_SMC, 0xa2, &ixD2F1_PCIE_LC_LINK_WIDTH_CNTL[0], sizeof(ixD2F1_PCIE_LC_LINK_WIDTH_CNTL)/sizeof(ixD2F1_PCIE_LC_LINK_WIDTH_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_8_EQUALIZATION_CNTL", REG_MMIO, 0xa3, &mmPCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_N_FTS_CNTL", REG_SMC, 0xa3, &ixD2F1_PCIE_LC_N_FTS_CNTL[0], sizeof(ixD2F1_PCIE_LC_N_FTS_CNTL)/sizeof(ixD2F1_PCIE_LC_N_FTS_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_10_EQUALIZATION_CNTL", REG_MMIO, 0xa4, &mmPCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_SPEED_CNTL", REG_SMC, 0xa4, &ixD2F1_PCIE_LC_SPEED_CNTL[0], sizeof(ixD2F1_PCIE_LC_SPEED_CNTL)/sizeof(ixD2F1_PCIE_LC_SPEED_CNTL[0]), 0, 0 },
+	{ "mmPCIE_LANE_12_EQUALIZATION_CNTL", REG_MMIO, 0xa5, &mmPCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_STATE0", REG_SMC, 0xa5, &ixD2F1_PCIE_LC_STATE0[0], sizeof(ixD2F1_PCIE_LC_STATE0)/sizeof(ixD2F1_PCIE_LC_STATE0[0]), 0, 0 },
+	{ "mmPCIE_LANE_14_EQUALIZATION_CNTL", REG_MMIO, 0xa6, &mmPCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(mmPCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(mmPCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_STATE1", REG_SMC, 0xa6, &ixD2F1_PCIE_LC_STATE1[0], sizeof(ixD2F1_PCIE_LC_STATE1)/sizeof(ixD2F1_PCIE_LC_STATE1[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_STATE2", REG_SMC, 0xa7, &ixD2F1_PCIE_LC_STATE2[0], sizeof(ixD2F1_PCIE_LC_STATE2)/sizeof(ixD2F1_PCIE_LC_STATE2[0]), 0, 0 },
+	{ "mmPCIE_ACS_ENH_CAP_LIST", REG_MMIO, 0xa8, &mmPCIE_ACS_ENH_CAP_LIST[0], sizeof(mmPCIE_ACS_ENH_CAP_LIST)/sizeof(mmPCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_STATE3", REG_SMC, 0xa8, &ixD2F1_PCIE_LC_STATE3[0], sizeof(ixD2F1_PCIE_LC_STATE3)/sizeof(ixD2F1_PCIE_LC_STATE3[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_STATE4", REG_SMC, 0xa9, &ixD2F1_PCIE_LC_STATE4[0], sizeof(ixD2F1_PCIE_LC_STATE4)/sizeof(ixD2F1_PCIE_LC_STATE4[0]), 0, 0 },
+	{ "mmPCIE_ACS_CNTL", REG_MMIO, 0xa9, &mmPCIE_ACS_CNTL[0], sizeof(mmPCIE_ACS_CNTL)/sizeof(mmPCIE_ACS_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ACS_CAP", REG_MMIO, 0xa9, &mmPCIE_ACS_CAP[0], sizeof(mmPCIE_ACS_CAP)/sizeof(mmPCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_STATE5", REG_SMC, 0xaa, &ixD2F1_PCIE_LC_STATE5[0], sizeof(ixD2F1_PCIE_LC_STATE5)/sizeof(ixD2F1_PCIE_LC_STATE5[0]), 0, 0 },
+	{ "mmPCIE_ATS_ENH_CAP_LIST", REG_MMIO, 0xac, &mmPCIE_ATS_ENH_CAP_LIST[0], sizeof(mmPCIE_ATS_ENH_CAP_LIST)/sizeof(mmPCIE_ATS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_ATS_CNTL", REG_MMIO, 0xad, &mmPCIE_ATS_CNTL[0], sizeof(mmPCIE_ATS_CNTL)/sizeof(mmPCIE_ATS_CNTL[0]), 0, 0 },
+	{ "mmPCIE_ATS_CAP", REG_MMIO, 0xad, &mmPCIE_ATS_CAP[0], sizeof(mmPCIE_ATS_CAP)/sizeof(mmPCIE_ATS_CAP[0]), 0, 0 },
+	{ "mmADAPTER_ID", REG_MMIO, 0xb, &mmADAPTER_ID[0], sizeof(mmADAPTER_ID)/sizeof(mmADAPTER_ID[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_ENH_CAP_LIST", REG_MMIO, 0xb0, &mmPCIE_PAGE_REQ_ENH_CAP_LIST[0], sizeof(mmPCIE_PAGE_REQ_ENH_CAP_LIST)/sizeof(mmPCIE_PAGE_REQ_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_VENDOR_ID", REG_SMC, 0xb000000, &ixD3F5_VENDOR_ID[0], sizeof(ixD3F5_VENDOR_ID)/sizeof(ixD3F5_VENDOR_ID[0]), 0, 0 },
+	{ "ixD3F5_COMMAND", REG_SMC, 0xb000001, &ixD3F5_COMMAND[0], sizeof(ixD3F5_COMMAND)/sizeof(ixD3F5_COMMAND[0]), 0, 0 },
+	{ "ixD3F5_STATUS", REG_SMC, 0xb000001, &ixD3F5_STATUS[0], sizeof(ixD3F5_STATUS)/sizeof(ixD3F5_STATUS[0]), 0, 0 },
+	{ "ixD3F5_PROG_INTERFACE", REG_SMC, 0xb000002, &ixD3F5_PROG_INTERFACE[0], sizeof(ixD3F5_PROG_INTERFACE)/sizeof(ixD3F5_PROG_INTERFACE[0]), 0, 0 },
+	{ "ixD3F5_REVISION_ID", REG_SMC, 0xb000002, &ixD3F5_REVISION_ID[0], sizeof(ixD3F5_REVISION_ID)/sizeof(ixD3F5_REVISION_ID[0]), 0, 0 },
+	{ "ixD3F5_BASE_CLASS", REG_SMC, 0xb000002, &ixD3F5_BASE_CLASS[0], sizeof(ixD3F5_BASE_CLASS)/sizeof(ixD3F5_BASE_CLASS[0]), 0, 0 },
+	{ "ixD3F5_SUB_CLASS", REG_SMC, 0xb000002, &ixD3F5_SUB_CLASS[0], sizeof(ixD3F5_SUB_CLASS)/sizeof(ixD3F5_SUB_CLASS[0]), 0, 0 },
+	{ "ixD3F5_CACHE_LINE", REG_SMC, 0xb000003, &ixD3F5_CACHE_LINE[0], sizeof(ixD3F5_CACHE_LINE)/sizeof(ixD3F5_CACHE_LINE[0]), 0, 0 },
+	{ "ixD3F5_LATENCY", REG_SMC, 0xb000003, &ixD3F5_LATENCY[0], sizeof(ixD3F5_LATENCY)/sizeof(ixD3F5_LATENCY[0]), 0, 0 },
+	{ "ixD3F5_HEADER", REG_SMC, 0xb000003, &ixD3F5_HEADER[0], sizeof(ixD3F5_HEADER)/sizeof(ixD3F5_HEADER[0]), 0, 0 },
+	{ "ixD3F5_BIST", REG_SMC, 0xb000003, &ixD3F5_BIST[0], sizeof(ixD3F5_BIST)/sizeof(ixD3F5_BIST[0]), 0, 0 },
+	{ "ixD3F5_SUB_BUS_NUMBER_LATENCY", REG_SMC, 0xb000006, &ixD3F5_SUB_BUS_NUMBER_LATENCY[0], sizeof(ixD3F5_SUB_BUS_NUMBER_LATENCY)/sizeof(ixD3F5_SUB_BUS_NUMBER_LATENCY[0]), 0, 0 },
+	{ "ixD3F5_SECONDARY_STATUS", REG_SMC, 0xb000007, &ixD3F5_SECONDARY_STATUS[0], sizeof(ixD3F5_SECONDARY_STATUS)/sizeof(ixD3F5_SECONDARY_STATUS[0]), 0, 0 },
+	{ "ixD3F5_IO_BASE_LIMIT", REG_SMC, 0xb000007, &ixD3F5_IO_BASE_LIMIT[0], sizeof(ixD3F5_IO_BASE_LIMIT)/sizeof(ixD3F5_IO_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F5_MEM_BASE_LIMIT", REG_SMC, 0xb000008, &ixD3F5_MEM_BASE_LIMIT[0], sizeof(ixD3F5_MEM_BASE_LIMIT)/sizeof(ixD3F5_MEM_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F5_PREF_BASE_LIMIT", REG_SMC, 0xb000009, &ixD3F5_PREF_BASE_LIMIT[0], sizeof(ixD3F5_PREF_BASE_LIMIT)/sizeof(ixD3F5_PREF_BASE_LIMIT[0]), 0, 0 },
+	{ "ixD3F5_PREF_BASE_UPPER", REG_SMC, 0xb00000a, &ixD3F5_PREF_BASE_UPPER[0], sizeof(ixD3F5_PREF_BASE_UPPER)/sizeof(ixD3F5_PREF_BASE_UPPER[0]), 0, 0 },
+	{ "ixD3F5_PREF_LIMIT_UPPER", REG_SMC, 0xb00000b, &ixD3F5_PREF_LIMIT_UPPER[0], sizeof(ixD3F5_PREF_LIMIT_UPPER)/sizeof(ixD3F5_PREF_LIMIT_UPPER[0]), 0, 0 },
+	{ "ixD3F5_IO_BASE_LIMIT_HI", REG_SMC, 0xb00000c, &ixD3F5_IO_BASE_LIMIT_HI[0], sizeof(ixD3F5_IO_BASE_LIMIT_HI)/sizeof(ixD3F5_IO_BASE_LIMIT_HI[0]), 0, 0 },
+	{ "ixD3F5_CAP_PTR", REG_SMC, 0xb00000d, &ixD3F5_CAP_PTR[0], sizeof(ixD3F5_CAP_PTR)/sizeof(ixD3F5_CAP_PTR[0]), 0, 0 },
+	{ "ixD3F5_IRQ_BRIDGE_CNTL", REG_SMC, 0xb00000f, &ixD3F5_IRQ_BRIDGE_CNTL[0], sizeof(ixD3F5_IRQ_BRIDGE_CNTL)/sizeof(ixD3F5_IRQ_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F5_INTERRUPT_LINE", REG_SMC, 0xb00000f, &ixD3F5_INTERRUPT_LINE[0], sizeof(ixD3F5_INTERRUPT_LINE)/sizeof(ixD3F5_INTERRUPT_LINE[0]), 0, 0 },
+	{ "ixD3F5_INTERRUPT_PIN", REG_SMC, 0xb00000f, &ixD3F5_INTERRUPT_PIN[0], sizeof(ixD3F5_INTERRUPT_PIN)/sizeof(ixD3F5_INTERRUPT_PIN[0]), 0, 0 },
+	{ "ixD3F5_EXT_BRIDGE_CNTL", REG_SMC, 0xb000010, &ixD3F5_EXT_BRIDGE_CNTL[0], sizeof(ixD3F5_EXT_BRIDGE_CNTL)/sizeof(ixD3F5_EXT_BRIDGE_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PMI_CAP_LIST", REG_SMC, 0xb000014, &ixD3F5_PMI_CAP_LIST[0], sizeof(ixD3F5_PMI_CAP_LIST)/sizeof(ixD3F5_PMI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PMI_CAP", REG_SMC, 0xb000014, &ixD3F5_PMI_CAP[0], sizeof(ixD3F5_PMI_CAP)/sizeof(ixD3F5_PMI_CAP[0]), 0, 0 },
+	{ "ixD3F5_PMI_STATUS_CNTL", REG_SMC, 0xb000015, &ixD3F5_PMI_STATUS_CNTL[0], sizeof(ixD3F5_PMI_STATUS_CNTL)/sizeof(ixD3F5_PMI_STATUS_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_CAP_LIST", REG_SMC, 0xb000016, &ixD3F5_PCIE_CAP_LIST[0], sizeof(ixD3F5_PCIE_CAP_LIST)/sizeof(ixD3F5_PCIE_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PCIE_CAP", REG_SMC, 0xb000016, &ixD3F5_PCIE_CAP[0], sizeof(ixD3F5_PCIE_CAP)/sizeof(ixD3F5_PCIE_CAP[0]), 0, 0 },
+	{ "ixD3F5_DEVICE_CAP", REG_SMC, 0xb000017, &ixD3F5_DEVICE_CAP[0], sizeof(ixD3F5_DEVICE_CAP)/sizeof(ixD3F5_DEVICE_CAP[0]), 0, 0 },
+	{ "ixD3F5_DEVICE_STATUS", REG_SMC, 0xb000018, &ixD3F5_DEVICE_STATUS[0], sizeof(ixD3F5_DEVICE_STATUS)/sizeof(ixD3F5_DEVICE_STATUS[0]), 0, 0 },
+	{ "ixD3F5_DEVICE_CNTL", REG_SMC, 0xb000018, &ixD3F5_DEVICE_CNTL[0], sizeof(ixD3F5_DEVICE_CNTL)/sizeof(ixD3F5_DEVICE_CNTL[0]), 0, 0 },
+	{ "ixD3F5_LINK_CAP", REG_SMC, 0xb000019, &ixD3F5_LINK_CAP[0], sizeof(ixD3F5_LINK_CAP)/sizeof(ixD3F5_LINK_CAP[0]), 0, 0 },
+	{ "ixD3F5_LINK_STATUS", REG_SMC, 0xb00001a, &ixD3F5_LINK_STATUS[0], sizeof(ixD3F5_LINK_STATUS)/sizeof(ixD3F5_LINK_STATUS[0]), 0, 0 },
+	{ "ixD3F5_LINK_CNTL", REG_SMC, 0xb00001a, &ixD3F5_LINK_CNTL[0], sizeof(ixD3F5_LINK_CNTL)/sizeof(ixD3F5_LINK_CNTL[0]), 0, 0 },
+	{ "ixD3F5_SLOT_CAP", REG_SMC, 0xb00001b, &ixD3F5_SLOT_CAP[0], sizeof(ixD3F5_SLOT_CAP)/sizeof(ixD3F5_SLOT_CAP[0]), 0, 0 },
+	{ "ixD3F5_SLOT_STATUS", REG_SMC, 0xb00001c, &ixD3F5_SLOT_STATUS[0], sizeof(ixD3F5_SLOT_STATUS)/sizeof(ixD3F5_SLOT_STATUS[0]), 0, 0 },
+	{ "ixD3F5_SLOT_CNTL", REG_SMC, 0xb00001c, &ixD3F5_SLOT_CNTL[0], sizeof(ixD3F5_SLOT_CNTL)/sizeof(ixD3F5_SLOT_CNTL[0]), 0, 0 },
+	{ "ixD3F5_ROOT_CNTL", REG_SMC, 0xb00001d, &ixD3F5_ROOT_CNTL[0], sizeof(ixD3F5_ROOT_CNTL)/sizeof(ixD3F5_ROOT_CNTL[0]), 0, 0 },
+	{ "ixD3F5_ROOT_CAP", REG_SMC, 0xb00001d, &ixD3F5_ROOT_CAP[0], sizeof(ixD3F5_ROOT_CAP)/sizeof(ixD3F5_ROOT_CAP[0]), 0, 0 },
+	{ "ixD3F5_ROOT_STATUS", REG_SMC, 0xb00001e, &ixD3F5_ROOT_STATUS[0], sizeof(ixD3F5_ROOT_STATUS)/sizeof(ixD3F5_ROOT_STATUS[0]), 0, 0 },
+	{ "ixD3F5_DEVICE_CAP2", REG_SMC, 0xb00001f, &ixD3F5_DEVICE_CAP2[0], sizeof(ixD3F5_DEVICE_CAP2)/sizeof(ixD3F5_DEVICE_CAP2[0]), 0, 0 },
+	{ "ixD3F5_DEVICE_STATUS2", REG_SMC, 0xb000020, &ixD3F5_DEVICE_STATUS2[0], sizeof(ixD3F5_DEVICE_STATUS2)/sizeof(ixD3F5_DEVICE_STATUS2[0]), 0, 0 },
+	{ "ixD3F5_DEVICE_CNTL2", REG_SMC, 0xb000020, &ixD3F5_DEVICE_CNTL2[0], sizeof(ixD3F5_DEVICE_CNTL2)/sizeof(ixD3F5_DEVICE_CNTL2[0]), 0, 0 },
+	{ "ixD3F5_LINK_CAP2", REG_SMC, 0xb000021, &ixD3F5_LINK_CAP2[0], sizeof(ixD3F5_LINK_CAP2)/sizeof(ixD3F5_LINK_CAP2[0]), 0, 0 },
+	{ "ixD3F5_LINK_STATUS2", REG_SMC, 0xb000022, &ixD3F5_LINK_STATUS2[0], sizeof(ixD3F5_LINK_STATUS2)/sizeof(ixD3F5_LINK_STATUS2[0]), 0, 0 },
+	{ "ixD3F5_LINK_CNTL2", REG_SMC, 0xb000022, &ixD3F5_LINK_CNTL2[0], sizeof(ixD3F5_LINK_CNTL2)/sizeof(ixD3F5_LINK_CNTL2[0]), 0, 0 },
+	{ "ixD3F5_SLOT_CAP2", REG_SMC, 0xb000023, &ixD3F5_SLOT_CAP2[0], sizeof(ixD3F5_SLOT_CAP2)/sizeof(ixD3F5_SLOT_CAP2[0]), 0, 0 },
+	{ "ixD3F5_SLOT_STATUS2", REG_SMC, 0xb000024, &ixD3F5_SLOT_STATUS2[0], sizeof(ixD3F5_SLOT_STATUS2)/sizeof(ixD3F5_SLOT_STATUS2[0]), 0, 0 },
+	{ "ixD3F5_SLOT_CNTL2", REG_SMC, 0xb000024, &ixD3F5_SLOT_CNTL2[0], sizeof(ixD3F5_SLOT_CNTL2)/sizeof(ixD3F5_SLOT_CNTL2[0]), 0, 0 },
+	{ "ixD3F5_MSI_CAP_LIST", REG_SMC, 0xb000028, &ixD3F5_MSI_CAP_LIST[0], sizeof(ixD3F5_MSI_CAP_LIST)/sizeof(ixD3F5_MSI_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_MSI_MSG_ADDR_LO", REG_SMC, 0xb000029, &ixD3F5_MSI_MSG_ADDR_LO[0], sizeof(ixD3F5_MSI_MSG_ADDR_LO)/sizeof(ixD3F5_MSI_MSG_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F5_MSI_MSG_ADDR_HI", REG_SMC, 0xb00002a, &ixD3F5_MSI_MSG_ADDR_HI[0], sizeof(ixD3F5_MSI_MSG_ADDR_HI)/sizeof(ixD3F5_MSI_MSG_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F5_MSI_MSG_DATA", REG_SMC, 0xb00002a, &ixD3F5_MSI_MSG_DATA[0], sizeof(ixD3F5_MSI_MSG_DATA)/sizeof(ixD3F5_MSI_MSG_DATA[0]), 0, 0 },
+	{ "ixD3F5_MSI_MSG_DATA_64", REG_SMC, 0xb00002b, &ixD3F5_MSI_MSG_DATA_64[0], sizeof(ixD3F5_MSI_MSG_DATA_64)/sizeof(ixD3F5_MSI_MSG_DATA_64[0]), 0, 0 },
+	{ "ixD3F5_SSID_CAP_LIST", REG_SMC, 0xb000030, &ixD3F5_SSID_CAP_LIST[0], sizeof(ixD3F5_SSID_CAP_LIST)/sizeof(ixD3F5_SSID_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_SSID_CAP", REG_SMC, 0xb000031, &ixD3F5_SSID_CAP[0], sizeof(ixD3F5_SSID_CAP)/sizeof(ixD3F5_SSID_CAP[0]), 0, 0 },
+	{ "ixD3F5_MSI_MAP_CAP_LIST", REG_SMC, 0xb000032, &ixD3F5_MSI_MAP_CAP_LIST[0], sizeof(ixD3F5_MSI_MAP_CAP_LIST)/sizeof(ixD3F5_MSI_MAP_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_MSI_MAP_CAP", REG_SMC, 0xb000032, &ixD3F5_MSI_MAP_CAP[0], sizeof(ixD3F5_MSI_MAP_CAP)/sizeof(ixD3F5_MSI_MAP_CAP[0]), 0, 0 },
+	{ "ixD3F5_MSI_MAP_ADDR_LO", REG_SMC, 0xb000033, &ixD3F5_MSI_MAP_ADDR_LO[0], sizeof(ixD3F5_MSI_MAP_ADDR_LO)/sizeof(ixD3F5_MSI_MAP_ADDR_LO[0]), 0, 0 },
+	{ "ixD3F5_MSI_MAP_ADDR_HI", REG_SMC, 0xb000034, &ixD3F5_MSI_MAP_ADDR_HI[0], sizeof(ixD3F5_MSI_MAP_ADDR_HI)/sizeof(ixD3F5_MSI_MAP_ADDR_HI[0]), 0, 0 },
+	{ "ixD3F5_PCIE_PORT_INDEX", REG_SMC, 0xb000038, &ixD3F5_PCIE_PORT_INDEX[0], sizeof(ixD3F5_PCIE_PORT_INDEX)/sizeof(ixD3F5_PCIE_PORT_INDEX[0]), 0, 0 },
+	{ "ixD3F5_PCIE_PORT_DATA", REG_SMC, 0xb000039, &ixD3F5_PCIE_PORT_DATA[0], sizeof(ixD3F5_PCIE_PORT_DATA)/sizeof(ixD3F5_PCIE_PORT_DATA[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST", REG_SMC, 0xb000040, &ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VENDOR_SPECIFIC_HDR", REG_SMC, 0xb000041, &ixD3F5_PCIE_VENDOR_SPECIFIC_HDR[0], sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC_HDR)/sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC_HDR[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VENDOR_SPECIFIC1", REG_SMC, 0xb000042, &ixD3F5_PCIE_VENDOR_SPECIFIC1[0], sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC1)/sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VENDOR_SPECIFIC2", REG_SMC, 0xb000043, &ixD3F5_PCIE_VENDOR_SPECIFIC2[0], sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC2)/sizeof(ixD3F5_PCIE_VENDOR_SPECIFIC2[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VC_ENH_CAP_LIST", REG_SMC, 0xb000044, &ixD3F5_PCIE_VC_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_VC_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_VC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PCIE_PORT_VC_CAP_REG1", REG_SMC, 0xb000045, &ixD3F5_PCIE_PORT_VC_CAP_REG1[0], sizeof(ixD3F5_PCIE_PORT_VC_CAP_REG1)/sizeof(ixD3F5_PCIE_PORT_VC_CAP_REG1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_PORT_VC_CAP_REG2", REG_SMC, 0xb000046, &ixD3F5_PCIE_PORT_VC_CAP_REG2[0], sizeof(ixD3F5_PCIE_PORT_VC_CAP_REG2)/sizeof(ixD3F5_PCIE_PORT_VC_CAP_REG2[0]), 0, 0 },
+	{ "ixD3F5_PCIE_PORT_VC_STATUS", REG_SMC, 0xb000047, &ixD3F5_PCIE_PORT_VC_STATUS[0], sizeof(ixD3F5_PCIE_PORT_VC_STATUS)/sizeof(ixD3F5_PCIE_PORT_VC_STATUS[0]), 0, 0 },
+	{ "ixD3F5_PCIE_PORT_VC_CNTL", REG_SMC, 0xb000047, &ixD3F5_PCIE_PORT_VC_CNTL[0], sizeof(ixD3F5_PCIE_PORT_VC_CNTL)/sizeof(ixD3F5_PCIE_PORT_VC_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VC0_RESOURCE_CAP", REG_SMC, 0xb000048, &ixD3F5_PCIE_VC0_RESOURCE_CAP[0], sizeof(ixD3F5_PCIE_VC0_RESOURCE_CAP)/sizeof(ixD3F5_PCIE_VC0_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VC0_RESOURCE_CNTL", REG_SMC, 0xb000049, &ixD3F5_PCIE_VC0_RESOURCE_CNTL[0], sizeof(ixD3F5_PCIE_VC0_RESOURCE_CNTL)/sizeof(ixD3F5_PCIE_VC0_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VC0_RESOURCE_STATUS", REG_SMC, 0xb00004a, &ixD3F5_PCIE_VC0_RESOURCE_STATUS[0], sizeof(ixD3F5_PCIE_VC0_RESOURCE_STATUS)/sizeof(ixD3F5_PCIE_VC0_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VC1_RESOURCE_CAP", REG_SMC, 0xb00004b, &ixD3F5_PCIE_VC1_RESOURCE_CAP[0], sizeof(ixD3F5_PCIE_VC1_RESOURCE_CAP)/sizeof(ixD3F5_PCIE_VC1_RESOURCE_CAP[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VC1_RESOURCE_CNTL", REG_SMC, 0xb00004c, &ixD3F5_PCIE_VC1_RESOURCE_CNTL[0], sizeof(ixD3F5_PCIE_VC1_RESOURCE_CNTL)/sizeof(ixD3F5_PCIE_VC1_RESOURCE_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_VC1_RESOURCE_STATUS", REG_SMC, 0xb00004d, &ixD3F5_PCIE_VC1_RESOURCE_STATUS[0], sizeof(ixD3F5_PCIE_VC1_RESOURCE_STATUS)/sizeof(ixD3F5_PCIE_VC1_RESOURCE_STATUS[0]), 0, 0 },
+	{ "ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST", REG_SMC, 0xb000050, &ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PCIE_DEV_SERIAL_NUM_DW1", REG_SMC, 0xb000051, &ixD3F5_PCIE_DEV_SERIAL_NUM_DW1[0], sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_DW1)/sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_DW1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_DEV_SERIAL_NUM_DW2", REG_SMC, 0xb000052, &ixD3F5_PCIE_DEV_SERIAL_NUM_DW2[0], sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_DW2)/sizeof(ixD3F5_PCIE_DEV_SERIAL_NUM_DW2[0]), 0, 0 },
+	{ "ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST", REG_SMC, 0xb000054, &ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PCIE_UNCORR_ERR_STATUS", REG_SMC, 0xb000055, &ixD3F5_PCIE_UNCORR_ERR_STATUS[0], sizeof(ixD3F5_PCIE_UNCORR_ERR_STATUS)/sizeof(ixD3F5_PCIE_UNCORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F5_PCIE_UNCORR_ERR_MASK", REG_SMC, 0xb000056, &ixD3F5_PCIE_UNCORR_ERR_MASK[0], sizeof(ixD3F5_PCIE_UNCORR_ERR_MASK)/sizeof(ixD3F5_PCIE_UNCORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F5_PCIE_UNCORR_ERR_SEVERITY", REG_SMC, 0xb000057, &ixD3F5_PCIE_UNCORR_ERR_SEVERITY[0], sizeof(ixD3F5_PCIE_UNCORR_ERR_SEVERITY)/sizeof(ixD3F5_PCIE_UNCORR_ERR_SEVERITY[0]), 0, 0 },
+	{ "ixD3F5_PCIE_CORR_ERR_STATUS", REG_SMC, 0xb000058, &ixD3F5_PCIE_CORR_ERR_STATUS[0], sizeof(ixD3F5_PCIE_CORR_ERR_STATUS)/sizeof(ixD3F5_PCIE_CORR_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F5_PCIE_CORR_ERR_MASK", REG_SMC, 0xb000059, &ixD3F5_PCIE_CORR_ERR_MASK[0], sizeof(ixD3F5_PCIE_CORR_ERR_MASK)/sizeof(ixD3F5_PCIE_CORR_ERR_MASK[0]), 0, 0 },
+	{ "ixD3F5_PCIE_ADV_ERR_CAP_CNTL", REG_SMC, 0xb00005a, &ixD3F5_PCIE_ADV_ERR_CAP_CNTL[0], sizeof(ixD3F5_PCIE_ADV_ERR_CAP_CNTL)/sizeof(ixD3F5_PCIE_ADV_ERR_CAP_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_HDR_LOG0", REG_SMC, 0xb00005b, &ixD3F5_PCIE_HDR_LOG0[0], sizeof(ixD3F5_PCIE_HDR_LOG0)/sizeof(ixD3F5_PCIE_HDR_LOG0[0]), 0, 0 },
+	{ "ixD3F5_PCIE_HDR_LOG1", REG_SMC, 0xb00005c, &ixD3F5_PCIE_HDR_LOG1[0], sizeof(ixD3F5_PCIE_HDR_LOG1)/sizeof(ixD3F5_PCIE_HDR_LOG1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_HDR_LOG2", REG_SMC, 0xb00005d, &ixD3F5_PCIE_HDR_LOG2[0], sizeof(ixD3F5_PCIE_HDR_LOG2)/sizeof(ixD3F5_PCIE_HDR_LOG2[0]), 0, 0 },
+	{ "ixD3F5_PCIE_HDR_LOG3", REG_SMC, 0xb00005e, &ixD3F5_PCIE_HDR_LOG3[0], sizeof(ixD3F5_PCIE_HDR_LOG3)/sizeof(ixD3F5_PCIE_HDR_LOG3[0]), 0, 0 },
+	{ "ixD3F5_PCIE_ROOT_ERR_CMD", REG_SMC, 0xb00005f, &ixD3F5_PCIE_ROOT_ERR_CMD[0], sizeof(ixD3F5_PCIE_ROOT_ERR_CMD)/sizeof(ixD3F5_PCIE_ROOT_ERR_CMD[0]), 0, 0 },
+	{ "ixD3F5_PCIE_ROOT_ERR_STATUS", REG_SMC, 0xb000060, &ixD3F5_PCIE_ROOT_ERR_STATUS[0], sizeof(ixD3F5_PCIE_ROOT_ERR_STATUS)/sizeof(ixD3F5_PCIE_ROOT_ERR_STATUS[0]), 0, 0 },
+	{ "ixD3F5_PCIE_ERR_SRC_ID", REG_SMC, 0xb000061, &ixD3F5_PCIE_ERR_SRC_ID[0], sizeof(ixD3F5_PCIE_ERR_SRC_ID)/sizeof(ixD3F5_PCIE_ERR_SRC_ID[0]), 0, 0 },
+	{ "ixD3F5_PCIE_TLP_PREFIX_LOG0", REG_SMC, 0xb000062, &ixD3F5_PCIE_TLP_PREFIX_LOG0[0], sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG0)/sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG0[0]), 0, 0 },
+	{ "ixD3F5_PCIE_TLP_PREFIX_LOG1", REG_SMC, 0xb000063, &ixD3F5_PCIE_TLP_PREFIX_LOG1[0], sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG1)/sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_TLP_PREFIX_LOG2", REG_SMC, 0xb000064, &ixD3F5_PCIE_TLP_PREFIX_LOG2[0], sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG2)/sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG2[0]), 0, 0 },
+	{ "ixD3F5_PCIE_TLP_PREFIX_LOG3", REG_SMC, 0xb000065, &ixD3F5_PCIE_TLP_PREFIX_LOG3[0], sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG3)/sizeof(ixD3F5_PCIE_TLP_PREFIX_LOG3[0]), 0, 0 },
+	{ "ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST", REG_SMC, 0xb00009c, &ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_SECONDARY_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LINK_CNTL3", REG_SMC, 0xb00009d, &ixD3F5_PCIE_LINK_CNTL3[0], sizeof(ixD3F5_PCIE_LINK_CNTL3)/sizeof(ixD3F5_PCIE_LINK_CNTL3[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_ERROR_STATUS", REG_SMC, 0xb00009e, &ixD3F5_PCIE_LANE_ERROR_STATUS[0], sizeof(ixD3F5_PCIE_LANE_ERROR_STATUS)/sizeof(ixD3F5_PCIE_LANE_ERROR_STATUS[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL", REG_SMC, 0xb00009f, &ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_0_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL", REG_SMC, 0xb0000a0, &ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_2_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL", REG_SMC, 0xb0000a1, &ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_4_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL", REG_SMC, 0xb0000a2, &ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_6_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL", REG_SMC, 0xb0000a3, &ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_8_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL", REG_SMC, 0xb0000a4, &ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_10_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL", REG_SMC, 0xb0000a5, &ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_12_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL", REG_SMC, 0xb0000a6, &ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL[0], sizeof(ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL)/sizeof(ixD3F5_PCIE_LANE_14_EQUALIZATION_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_ACS_ENH_CAP_LIST", REG_SMC, 0xb0000a8, &ixD3F5_PCIE_ACS_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_ACS_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_ACS_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PCIE_ACS_CNTL", REG_SMC, 0xb0000a9, &ixD3F5_PCIE_ACS_CNTL[0], sizeof(ixD3F5_PCIE_ACS_CNTL)/sizeof(ixD3F5_PCIE_ACS_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_ACS_CAP", REG_SMC, 0xb0000a9, &ixD3F5_PCIE_ACS_CAP[0], sizeof(ixD3F5_PCIE_ACS_CAP)/sizeof(ixD3F5_PCIE_ACS_CAP[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_ENH_CAP_LIST", REG_SMC, 0xb0000bc, &ixD3F5_PCIE_MC_ENH_CAP_LIST[0], sizeof(ixD3F5_PCIE_MC_ENH_CAP_LIST)/sizeof(ixD3F5_PCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_CNTL", REG_SMC, 0xb0000bd, &ixD3F5_PCIE_MC_CNTL[0], sizeof(ixD3F5_PCIE_MC_CNTL)/sizeof(ixD3F5_PCIE_MC_CNTL[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_CAP", REG_SMC, 0xb0000bd, &ixD3F5_PCIE_MC_CAP[0], sizeof(ixD3F5_PCIE_MC_CAP)/sizeof(ixD3F5_PCIE_MC_CAP[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_ADDR0", REG_SMC, 0xb0000be, &ixD3F5_PCIE_MC_ADDR0[0], sizeof(ixD3F5_PCIE_MC_ADDR0)/sizeof(ixD3F5_PCIE_MC_ADDR0[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_ADDR1", REG_SMC, 0xb0000bf, &ixD3F5_PCIE_MC_ADDR1[0], sizeof(ixD3F5_PCIE_MC_ADDR1)/sizeof(ixD3F5_PCIE_MC_ADDR1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_RCV0", REG_SMC, 0xb0000c0, &ixD3F5_PCIE_MC_RCV0[0], sizeof(ixD3F5_PCIE_MC_RCV0)/sizeof(ixD3F5_PCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_RCV1", REG_SMC, 0xb0000c1, &ixD3F5_PCIE_MC_RCV1[0], sizeof(ixD3F5_PCIE_MC_RCV1)/sizeof(ixD3F5_PCIE_MC_RCV1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_BLOCK_ALL0", REG_SMC, 0xb0000c2, &ixD3F5_PCIE_MC_BLOCK_ALL0[0], sizeof(ixD3F5_PCIE_MC_BLOCK_ALL0)/sizeof(ixD3F5_PCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_BLOCK_ALL1", REG_SMC, 0xb0000c3, &ixD3F5_PCIE_MC_BLOCK_ALL1[0], sizeof(ixD3F5_PCIE_MC_BLOCK_ALL1)/sizeof(ixD3F5_PCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0", REG_SMC, 0xb0000c4, &ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1", REG_SMC, 0xb0000c5, &ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(ixD3F5_PCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_OVERLAY_BAR0", REG_SMC, 0xb0000c6, &ixD3F5_PCIE_MC_OVERLAY_BAR0[0], sizeof(ixD3F5_PCIE_MC_OVERLAY_BAR0)/sizeof(ixD3F5_PCIE_MC_OVERLAY_BAR0[0]), 0, 0 },
+	{ "ixD3F5_PCIE_MC_OVERLAY_BAR1", REG_SMC, 0xb0000c7, &ixD3F5_PCIE_MC_OVERLAY_BAR1[0], sizeof(ixD3F5_PCIE_MC_OVERLAY_BAR1)/sizeof(ixD3F5_PCIE_MC_OVERLAY_BAR1[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_STATUS", REG_MMIO, 0xb1, &mmPCIE_PAGE_REQ_STATUS[0], sizeof(mmPCIE_PAGE_REQ_STATUS)/sizeof(mmPCIE_PAGE_REQ_STATUS[0]), 0, 0 },
+	{ "mmPCIE_PAGE_REQ_CNTL", REG_MMIO, 0xb1, &mmPCIE_PAGE_REQ_CNTL[0], sizeof(mmPCIE_PAGE_REQ_CNTL)/sizeof(mmPCIE_PAGE_REQ_CNTL[0]), 0, 0 },
+	{ "mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY", REG_MMIO, 0xb2, &mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[0], sizeof(mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY)/sizeof(mmPCIE_OUTSTAND_PAGE_REQ_CAPACITY[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_BW_CHANGE_CNTL", REG_SMC, 0xb2, &ixD2F1_PCIE_LC_BW_CHANGE_CNTL[0], sizeof(ixD2F1_PCIE_LC_BW_CHANGE_CNTL)/sizeof(ixD2F1_PCIE_LC_BW_CHANGE_CNTL[0]), 0, 0 },
+	{ "mmPCIE_OUTSTAND_PAGE_REQ_ALLOC", REG_MMIO, 0xb3, &mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[0], sizeof(mmPCIE_OUTSTAND_PAGE_REQ_ALLOC)/sizeof(mmPCIE_OUTSTAND_PAGE_REQ_ALLOC[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_CDR_CNTL", REG_SMC, 0xb3, &ixD2F1_PCIE_LC_CDR_CNTL[0], sizeof(ixD2F1_PCIE_LC_CDR_CNTL)/sizeof(ixD2F1_PCIE_LC_CDR_CNTL[0]), 0, 0 },
+	{ "mmPCIE_PASID_ENH_CAP_LIST", REG_MMIO, 0xb4, &mmPCIE_PASID_ENH_CAP_LIST[0], sizeof(mmPCIE_PASID_ENH_CAP_LIST)/sizeof(mmPCIE_PASID_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_LANE_CNTL", REG_SMC, 0xb4, &ixD2F1_PCIE_LC_LANE_CNTL[0], sizeof(ixD2F1_PCIE_LC_LANE_CNTL)/sizeof(ixD2F1_PCIE_LC_LANE_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_CNTL3", REG_SMC, 0xb5, &ixD2F1_PCIE_LC_CNTL3[0], sizeof(ixD2F1_PCIE_LC_CNTL3)/sizeof(ixD2F1_PCIE_LC_CNTL3[0]), 0, 0 },
+	{ "mmPCIE_PASID_CNTL", REG_MMIO, 0xb5, &mmPCIE_PASID_CNTL[0], sizeof(mmPCIE_PASID_CNTL)/sizeof(mmPCIE_PASID_CNTL[0]), 0, 0 },
+	{ "mmPCIE_PASID_CAP", REG_MMIO, 0xb5, &mmPCIE_PASID_CAP[0], sizeof(mmPCIE_PASID_CAP)/sizeof(mmPCIE_PASID_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_CNTL4", REG_SMC, 0xb6, &ixD2F1_PCIE_LC_CNTL4[0], sizeof(ixD2F1_PCIE_LC_CNTL4)/sizeof(ixD2F1_PCIE_LC_CNTL4[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_CNTL5", REG_SMC, 0xb7, &ixD2F1_PCIE_LC_CNTL5[0], sizeof(ixD2F1_PCIE_LC_CNTL5)/sizeof(ixD2F1_PCIE_LC_CNTL5[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_ENH_CAP_LIST", REG_MMIO, 0xb8, &mmPCIE_TPH_REQR_ENH_CAP_LIST[0], sizeof(mmPCIE_TPH_REQR_ENH_CAP_LIST)/sizeof(mmPCIE_TPH_REQR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_FORCE_COEFF", REG_SMC, 0xb8, &ixD2F1_PCIE_LC_FORCE_COEFF[0], sizeof(ixD2F1_PCIE_LC_FORCE_COEFF)/sizeof(ixD2F1_PCIE_LC_FORCE_COEFF[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_BEST_EQ_SETTINGS", REG_SMC, 0xb9, &ixD2F1_PCIE_LC_BEST_EQ_SETTINGS[0], sizeof(ixD2F1_PCIE_LC_BEST_EQ_SETTINGS)/sizeof(ixD2F1_PCIE_LC_BEST_EQ_SETTINGS[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_CAP", REG_MMIO, 0xb9, &mmPCIE_TPH_REQR_CAP[0], sizeof(mmPCIE_TPH_REQR_CAP)/sizeof(mmPCIE_TPH_REQR_CAP[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF", REG_SMC, 0xba, &ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF[0], sizeof(ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF)/sizeof(ixD2F1_PCIE_LC_FORCE_EQ_REQ_COEFF[0]), 0, 0 },
+	{ "mmPCIE_TPH_REQR_CNTL", REG_MMIO, 0xba, &mmPCIE_TPH_REQR_CNTL[0], sizeof(mmPCIE_TPH_REQR_CNTL)/sizeof(mmPCIE_TPH_REQR_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIE_LC_CNTL6", REG_SMC, 0xbb, &ixD2F1_PCIE_LC_CNTL6[0], sizeof(ixD2F1_PCIE_LC_CNTL6)/sizeof(ixD2F1_PCIE_LC_CNTL6[0]), 0, 0 },
+	{ "mmPCIE_MC_ENH_CAP_LIST", REG_MMIO, 0xbc, &mmPCIE_MC_ENH_CAP_LIST[0], sizeof(mmPCIE_MC_ENH_CAP_LIST)/sizeof(mmPCIE_MC_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_MC_CNTL", REG_MMIO, 0xbd, &mmPCIE_MC_CNTL[0], sizeof(mmPCIE_MC_CNTL)/sizeof(mmPCIE_MC_CNTL[0]), 0, 0 },
+	{ "mmPCIE_MC_CAP", REG_MMIO, 0xbd, &mmPCIE_MC_CAP[0], sizeof(mmPCIE_MC_CAP)/sizeof(mmPCIE_MC_CAP[0]), 0, 0 },
+	{ "mmPCIE_MC_ADDR0", REG_MMIO, 0xbe, &mmPCIE_MC_ADDR0[0], sizeof(mmPCIE_MC_ADDR0)/sizeof(mmPCIE_MC_ADDR0[0]), 0, 0 },
+	{ "mmPCIE_MC_ADDR1", REG_MMIO, 0xbf, &mmPCIE_MC_ADDR1[0], sizeof(mmPCIE_MC_ADDR1)/sizeof(mmPCIE_MC_ADDR1[0]), 0, 0 },
+	{ "mmROM_BASE_ADDR", REG_MMIO, 0xc, &mmROM_BASE_ADDR[0], sizeof(mmROM_BASE_ADDR)/sizeof(mmROM_BASE_ADDR[0]), 0, 0 },
+	{ "mmPCIE_INDEX_2", REG_MMIO, 0xc, &mmPCIE_INDEX_2[0], sizeof(mmPCIE_INDEX_2)/sizeof(mmPCIE_INDEX_2[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_STRAP_LC", REG_SMC, 0xc0, &ixD2F1_PCIEP_STRAP_LC[0], sizeof(ixD2F1_PCIEP_STRAP_LC)/sizeof(ixD2F1_PCIEP_STRAP_LC[0]), 0, 0 },
+	{ "mmPCIE_MC_RCV0", REG_MMIO, 0xc0, &mmPCIE_MC_RCV0[0], sizeof(mmPCIE_MC_RCV0)/sizeof(mmPCIE_MC_RCV0[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_STRAP_MISC", REG_SMC, 0xc1, &ixD2F1_PCIEP_STRAP_MISC[0], sizeof(ixD2F1_PCIEP_STRAP_MISC)/sizeof(ixD2F1_PCIEP_STRAP_MISC[0]), 0, 0 },
+	{ "mmPCIE_MC_RCV1", REG_MMIO, 0xc1, &mmPCIE_MC_RCV1[0], sizeof(mmPCIE_MC_RCV1)/sizeof(mmPCIE_MC_RCV1[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_ALL0", REG_MMIO, 0xc2, &mmPCIE_MC_BLOCK_ALL0[0], sizeof(mmPCIE_MC_BLOCK_ALL0)/sizeof(mmPCIE_MC_BLOCK_ALL0[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_ALL1", REG_MMIO, 0xc3, &mmPCIE_MC_BLOCK_ALL1[0], sizeof(mmPCIE_MC_BLOCK_ALL1)/sizeof(mmPCIE_MC_BLOCK_ALL1[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_UNTRANSLATED_0", REG_MMIO, 0xc4, &mmPCIE_MC_BLOCK_UNTRANSLATED_0[0], sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_0)/sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_0[0]), 0, 0 },
+	{ "mmPCIE_MC_BLOCK_UNTRANSLATED_1", REG_MMIO, 0xc5, &mmPCIE_MC_BLOCK_UNTRANSLATED_1[0], sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_1)/sizeof(mmPCIE_MC_BLOCK_UNTRANSLATED_1[0]), 0, 0 },
+	{ "mmPCIE_LTR_ENH_CAP_LIST", REG_MMIO, 0xc8, &mmPCIE_LTR_ENH_CAP_LIST[0], sizeof(mmPCIE_LTR_ENH_CAP_LIST)/sizeof(mmPCIE_LTR_ENH_CAP_LIST[0]), 0, 0 },
+	{ "mmPCIE_LTR_CAP", REG_MMIO, 0xc9, &mmPCIE_LTR_CAP[0], sizeof(mmPCIE_LTR_CAP)/sizeof(mmPCIE_LTR_CAP[0]), 0, 0 },
+	{ "mmPCIE_DATA_2", REG_MMIO, 0xd, &mmPCIE_DATA_2[0], sizeof(mmPCIE_DATA_2)/sizeof(mmPCIE_DATA_2[0]), 0, 0 },
+	{ "mmCAP_PTR", REG_MMIO, 0xd, &mmCAP_PTR[0], sizeof(mmCAP_PTR)/sizeof(mmCAP_PTR[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_BCH_ECC_CNTL", REG_SMC, 0xd0, &ixD2F1_PCIEP_BCH_ECC_CNTL[0], sizeof(ixD2F1_PCIEP_BCH_ECC_CNTL)/sizeof(ixD2F1_PCIEP_BCH_ECC_CNTL[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_HPGI_PRIVATE", REG_SMC, 0xd2, &ixD2F1_PCIEP_HPGI_PRIVATE[0], sizeof(ixD2F1_PCIEP_HPGI_PRIVATE)/sizeof(ixD2F1_PCIEP_HPGI_PRIVATE[0]), 0, 0 },
+	{ "ixD2F1_PCIEP_HPGI", REG_SMC, 0xda, &ixD2F1_PCIEP_HPGI[0], sizeof(ixD2F1_PCIEP_HPGI)/sizeof(ixD2F1_PCIEP_HPGI[0]), 0, 0 },
+	{ "mmPCIE_INDEX", REG_MMIO, 0xe, &mmPCIE_INDEX[0], sizeof(mmPCIE_INDEX)/sizeof(mmPCIE_INDEX[0]), 0, 0 },
+	{ "mmINTERRUPT_LINE", REG_MMIO, 0xf, &mmINTERRUPT_LINE[0], sizeof(mmINTERRUPT_LINE)/sizeof(mmINTERRUPT_LINE[0]), 0, 0 },
+	{ "mmINTERRUPT_PIN", REG_MMIO, 0xf, &mmINTERRUPT_PIN[0], sizeof(mmINTERRUPT_PIN)/sizeof(mmINTERRUPT_PIN[0]), 0, 0 },
+	{ "mmMAX_LATENCY", REG_MMIO, 0xf, &mmMAX_LATENCY[0], sizeof(mmMAX_LATENCY)/sizeof(mmMAX_LATENCY[0]), 0, 0 },
+	{ "mmMIN_GRANT", REG_MMIO, 0xf, &mmMIN_GRANT[0], sizeof(mmMIN_GRANT)/sizeof(mmMIN_GRANT[0]), 0, 0 },
diff --git a/src/lib/ip/dce100.c b/src/lib/ip/dce100.c
new file mode 100644
index 0000000..a1c8063
--- /dev/null
+++ b/src/lib/ip/dce100.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "dce100_bits.i"
+
+static const struct umr_reg dce100_registers[] = {
+#include "dce100_regs.i"
+};
+
+struct umr_ip_block *umr_create_dce100(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "dce100";
+	ip->no_regs = sizeof(dce100_registers)/sizeof(dce100_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(dce100_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, dce100_registers, sizeof(dce100_registers));
+	return ip;
+}
diff --git a/src/lib/ip/dce100_bits.i b/src/lib/ip/dce100_bits.i
new file mode 100644
index 0000000..55c3a60
--- /dev/null
+++ b/src/lib/ip/dce100_bits.i
@@ -0,0 +1,13320 @@
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[] = {
+	 { "AZALIA_INPUT_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[] = {
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL0[] = {
+	 { "INPUT_CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_FIFO_SIZE_CONTROL[] = {
+	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
+	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
+	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL0[] = {
+	 { "CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_CAPABILITIES[] = {
+	 { "SIXTY_FOUR_BIT_ADDRESS_SUPPORTED", 0, 0, &umr_bitfield_default },
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+	 { "NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED", 3, 7, &umr_bitfield_default },
+	 { "NUMBER_OF_INPUT_STREAMS_SUPPORTED", 8, 11, &umr_bitfield_default },
+	 { "NUMBER_OF_OUTPUT_STREAMS_SUPPORTED", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG_ID[] = {
+	 { "DCIO_DEBUG_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG_ID[] = {
+	 { "FMT_DEBUG_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR00[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ00[] = {
+	 { "SEQ_RST0B", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RST1B", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[] = {
+	 { "PRODUCT_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_LATENCY_COUNTER_CONTROL[] = {
+	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL1[] = {
+	 { "INPUT_CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_PAYLOAD_CAPABILITY[] = {
+	 { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL1[] = {
+	 { "CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR0[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1[] = {
+	 { "DCO_DCIO_MVP_DVOCNTL_A0_REG", 0, 1, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_MASK_REG", 2, 3, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_EN_REG", 4, 5, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_A0", 6, 7, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_SEL0", 8, 9, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_EN", 10, 11, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCLK_C", 12, 12, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0_REG", 13, 13, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0_PREMUX", 14, 14, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0", 15, 15, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN_REG", 16, 16, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_HSYNC_TRISTATE", 17, 17, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_CLK_TRISTATE", 18, 18, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN_PREMUX", 19, 19, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN", 20, 20, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_MUX", 21, 21, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_MASK_REG", 22, 22, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_VSYNC_TRISTATE", 24, 24, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_RATE_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_SEL0_PREMUX", 26, 26, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_SEL0", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG0[] = {
+	 { "FMT_DEBUG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR01[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ01[] = {
+	 { "SEQ_DOT8", 0, 0, &umr_bitfield_default },
+	 { "SEQ_SHIFT2", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PCLKBY2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_SHIFT4", 4, 4, &umr_bitfield_default },
+	 { "SEQ_MAXBW", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_LOWER_BASE_ADDRESS[] = {
+	 { "CORB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "CORB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION11[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_A[] = {
+	 { "DP_AUX_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG10[] = {
+	 { "DCIO_DIGC_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR10[] = {
+	 { "ATTR_GRPH_MODE", 0, 0, &umr_bitfield_default },
+	 { "ATTR_MONO_EN", 1, 1, &umr_bitfield_default },
+	 { "ATTR_LGRPH_EN", 2, 2, &umr_bitfield_default },
+	 { "ATTR_BLINK_EN", 3, 3, &umr_bitfield_default },
+	 { "ATTR_PANTOPONLY", 5, 5, &umr_bitfield_default },
+	 { "ATTR_PCLKBY2", 6, 6, &umr_bitfield_default },
+	 { "ATTR_CSEL_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT10[] = {
+	 { "V_SYNC_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPREFCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "DPREFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DPREFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREFCLK_CNTL[] = {
+	 { "REFCLK_CLOCK_EN", 0, 0, &umr_bitfield_default },
+	 { "REFCLK_SRC_SEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREFCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "REFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_CLK_FORCE_CONTROL[] = {
+	 { "DPDBG_CLK_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "DPDBG_CLK_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_PERFMON_CNTL2[] = {
+	 { "DCCG_PERF_DSICLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERF_REFCLK_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_UPPER_BASE_ADDRESS[] = {
+	 { "CORB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION12[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_B[] = {
+	 { "DP_AUX_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG11[] = {
+	 { "DCIO_DIGD_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR11[] = {
+	 { "ATTR_OVSC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT11[] = {
+	 { "V_SYNC_END", 0, 3, &umr_bitfield_default },
+	 { "V_INTR_CLR", 4, 4, &umr_bitfield_default },
+	 { "V_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "SEL5_REFRESH_CYC", 6, 6, &umr_bitfield_default },
+	 { "C0T7_WR_ONLY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CBUS_WRCMD_DELAY[] = {
+	 { "CBUS_PLL_WRCMD_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DEBUG_CNTL[] = {
+	 { "DCCG_DS_DEBUG_COUNT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_VALUE", 4, 12, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT_SRC_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DTO_INCR[] = {
+	 { "DCCG_DS_DTO_INCR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DTO_MODULO[] = {
+	 { "DCCG_DS_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_CNTL[] = {
+	 { "DCCG_DS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DS_HW_CAL_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DCCG_DS_ENABLED_STATUS", 9, 9, &umr_bitfield_default },
+	 { "DCCG_DS_XTALIN_RATE_DIV", 16, 17, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_REMOVE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DCCG_DS_DELAY_XTAL_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_HW_CAL_INTERVAL[] = {
+	 { "DCCG_DS_HW_CAL_INTERVAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPREFCLK_CNTL[] = {
+	 { "DPREFCLK_SRC_SEL", 0, 2, &umr_bitfield_default },
+	 { "UNB_DB_CLK_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEM_WRITE_PAGE_ADDR[] = {
+	 { "VGA_MEM_WRITE_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
+	 { "VGA_MEM_WRITE_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_WRITE_POINTER[] = {
+	 { "CORB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_READ_POINTER[] = {
+	 { "CORB_READ_POINTER", 0, 7, &umr_bitfield_default },
+	 { "CORB_READ_POINTER_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_C[] = {
+	 { "DP_AUX_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG12[] = {
+	 { "DCIO_DIGE_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR12[] = {
+	 { "ATTR_MAP_EN", 0, 3, &umr_bitfield_default },
+	 { "ATTR_VSMUX", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT12[] = {
+	 { "V_DISP_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CNTL[] = {
+	 { "DCCG_GTC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_INCR[] = {
+	 { "DCCG_GTC_DTO_INCR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_MODULO[] = {
+	 { "DCCG_GTC_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CURRENT[] = {
+	 { "DCCG_GTC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENTIST_DISPCLK_CNTL[] = {
+	 { "DENTIST_DISPCLK_WDIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_RDIVIDER", 8, 14, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_MODE", 15, 16, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHGTOG", 17, 17, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_DONETOG", 18, 18, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_DONE", 19, 19, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHG_DONE", 20, 20, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHGTOG", 21, 21, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_DONETOG", 22, 22, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_WDIVIDER", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CLK_ENABLE[] = {
+	 { "DACA_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DACB_CLK_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CLK_ENABLE[] = {
+	 { "DVO_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_WRITE[] = {
+	 { "AVSYNC_COUNTER_WRVALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_CONTROL[] = {
+	 { "AVSYNC_COUNTER_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_SMU_INTERRUPT_CNTL[] = {
+	 { "DMCU_SMU_STATIC_SCREEN_INT", 0, 0, &umr_bitfield_default },
+	 { "DMCU_SMU_STATIC_SCREEN_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_CONTROL[] = {
+	 { "DISPLAY0_FORCE_VBI", 0, 0, &umr_bitfield_default },
+	 { "DISPLAY1_FORCE_VBI", 1, 1, &umr_bitfield_default },
+	 { "DISPLAY2_FORCE_VBI", 2, 2, &umr_bitfield_default },
+	 { "DISPLAY3_FORCE_VBI", 3, 3, &umr_bitfield_default },
+	 { "DISPLAY4_FORCE_VBI", 4, 4, &umr_bitfield_default },
+	 { "DISPLAY5_FORCE_VBI", 5, 5, &umr_bitfield_default },
+	 { "DISPLAY_V0_FORCE_VBI", 6, 6, &umr_bitfield_default },
+	 { "SMU_DC_INT_CLEAR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_INTERRUPT_CONTROL[] = {
+	 { "DC_SMU_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DC_SMU_INT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DC_SMU_INT_EVENT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_READ[] = {
+	 { "AVSYNC_COUNTER_RDVALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEM_READ_PAGE_ADDR[] = {
+	 { "VGA_MEM_READ_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
+	 { "VGA_MEM_READ_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION14[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_D[] = {
+	 { "DP_AUX_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG13[] = {
+	 { "DCIO_DIGF_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_STATUS[] = {
+	 { "CORB_MEMORY_ERROR_INDICATION", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_SIZE[] = {
+	 { "CORB_SIZE", 0, 1, &umr_bitfield_default },
+	 { "CORB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR13[] = {
+	 { "ATTR_PPAN", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT13[] = {
+	 { "DISP_PITCH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMILLISECOND_TIME_BASE_DIV[] = {
+	 { "MILLISECOND_TIME_BASE_DIV", 0, 16, &umr_bitfield_default },
+	 { "MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_FREQ_CHANGE_CNTL[] = {
+	 { "DISPCLK_STEP_DELAY", 0, 13, &umr_bitfield_default },
+	 { "DISPCLK_STEP_SIZE", 16, 19, &umr_bitfield_default },
+	 { "DISPCLK_FREQ_RAMP_DONE", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_MAX_ERRDET_CYCLES", 25, 27, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_RESET", 28, 28, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_STATE", 29, 29, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_OVR_EN", 30, 30, &umr_bitfield_default },
+	 { "DISPCLK_CHG_FWD_CORR_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_MEM_GLOBAL_PWR_REQ_CNTL[] = {
+	 { "DC_MEM_GLOBAL_PWR_REQ_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_PERFMON_CNTL[] = {
+	 { "DCCG_PERF_DISPCLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERF_DPREFCLK_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK1_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK2_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERF_RUN", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_VSYNC", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_HSYNC", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERF_CRTC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCCG_PERF_XTALIN_PULSE_DIV", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL[] = {
+	 { "DISPCLK_DCCG_GATE_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_R_DCCG_GATE_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "SCLK_GATE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "DPREFCLK_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "DACACLK_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "DACBCLK_GATE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DVOACLK_GATE_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "DPDBG_CLK_GATE_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "DPREFCLK_R_DCCG_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "PCLK_TV_GATE_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "AOMCLK0_GATE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "AOMCLK1_GATE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "AOMCLK2_GATE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_R_DCCG_RAMP_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "AUDIO_DTO2_CLK_GATE_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "DPREFCLK_GTC_GATE_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "UNB_DB_CLK_GATE_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "REFCLK_GATE_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "REFCLK_R_DIG_GATE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "DSICLK_GATE_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "BYTECLK_GATE_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "ESCCLK_GATE_DISABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "DISPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DISPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_DISPCLK_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_SCLK_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CAC_STATUS[] = {
+	 { "CAC_STATUS_RDDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK1_RESYNC_CNTL[] = {
+	 { "PIXCLK1_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL1", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK2_RESYNC_CNTL[] = {
+	 { "PIXCLK2_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL2", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK0_RESYNC_CNTL[] = {
+	 { "PIXCLK0_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL0", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMICROSECOND_TIME_BASE_DIV[] = {
+	 { "MICROSECOND_TIME_BASE_DIV", 0, 6, &umr_bitfield_default },
+	 { "XTAL_REF_DIV", 8, 14, &umr_bitfield_default },
+	 { "XTAL_REF_SEL", 16, 16, &umr_bitfield_default },
+	 { "XTAL_REF_CLOCK_SOURCE_SEL", 17, 17, &umr_bitfield_default },
+	 { "MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DISP_CNTL_REG[] = {
+	 { "ALLOW_SR_ON_TRANS_REQ", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_LOWER_BASE_ADDRESS[] = {
+	 { "RIRB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "RIRB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION15[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_E[] = {
+	 { "DP_AUX_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG14[] = {
+	 { "DCIO_DIGG_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR14[] = {
+	 { "ATTR_CSEL1", 0, 1, &umr_bitfield_default },
+	 { "ATTR_CSEL2", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT14[] = {
+	 { "UNDRLN_LOC", 0, 4, &umr_bitfield_default },
+	 { "ADDR_CNT_BY4", 5, 5, &umr_bitfield_default },
+	 { "DOUBLE_WORD", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC0_PIXEL_RATE_CNTL[] = {
+	 { "CRTC0_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO0_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC0_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC0_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_PHASE[] = {
+	 { "DP_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_MODULO[] = {
+	 { "DP_DTO0_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC1_PIXEL_RATE_CNTL[] = {
+	 { "CRTC1_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO1_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO1_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_PHASE[] = {
+	 { "DP_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_MODULO[] = {
+	 { "DP_DTO1_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC2_PIXEL_RATE_CNTL[] = {
+	 { "CRTC2_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO2_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO2_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_PHASE[] = {
+	 { "DP_DTO2_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_MODULO[] = {
+	 { "DP_DTO2_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC3_PIXEL_RATE_CNTL[] = {
+	 { "CRTC3_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO3_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO3_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_PHASE[] = {
+	 { "DP_DTO3_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_MODULO[] = {
+	 { "DP_DTO3_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_UPPER_BASE_ADDRESS[] = {
+	 { "RIRB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION16[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_F[] = {
+	 { "DP_AUX_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG15[] = {
+	 { "DCIO_DEBUG15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT15[] = {
+	 { "V_BLANK_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC4_PIXEL_RATE_CNTL[] = {
+	 { "CRTC4_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO4_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO4_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_PHASE[] = {
+	 { "DP_DTO4_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_MODULO[] = {
+	 { "DP_DTO4_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC5_PIXEL_RATE_CNTL[] = {
+	 { "CRTC5_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO5_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO5_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_PHASE[] = {
+	 { "DP_DTO5_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_MODULO[] = {
+	 { "DP_DTO5_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_SOFT_RESET[] = {
+	 { "REFCLK_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "PCIE_REFCLK_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SOFT_RESET_DVO", 2, 2, &umr_bitfield_default },
+	 { "DVO_ENABLE_RST", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_DTO2_CLK_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DPREFCLK_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "AMCLK0_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "AMCLK1_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "P0PLL_CFG_IF_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "P1PLL_CFG_IF_SOFT_RESET", 15, 15, &umr_bitfield_default },
+	 { "P2PLL_CFG_IF_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "A0PLL_CFG_IF_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "A1PLL_CFG_IF_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "C0PLL_CFG_IF_SOFT_RESET", 19, 19, &umr_bitfield_default },
+	 { "C1PLL_CFG_IF_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "C2PLL_CFG_IF_SOFT_RESET", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRESPONSE_INTERRUPT_COUNT[] = {
+	 { "N_RESPONSE_INTERRUPT_COUNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_WRITE_POINTER[] = {
+	 { "RIRB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
+	 { "RIRB_WRITE_POINTER_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_G[] = {
+	 { "DP_AUX_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG16[] = {
+	 { "DCIO_DEBUG16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT16[] = {
+	 { "V_BLANK_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKA_CLOCK_ENABLE[] = {
+	 { "SYMCLKA_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_CTRL[] = {
+	 { "RESET_UC", 0, 0, &umr_bitfield_default },
+	 { "IGNORE_PWRMGT", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_IRQ_TO_UC", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_XIRQ_TO_UC", 3, 3, &umr_bitfield_default },
+	 { "DMCU_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_STATUS[] = {
+	 { "UC_IN_RESET", 0, 0, &umr_bitfield_default },
+	 { "UC_IN_WAIT_MODE", 1, 1, &umr_bitfield_default },
+	 { "UC_IN_STOP_MODE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PC_START_ADDR[] = {
+	 { "PC_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "PC_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_START_ADDR[] = {
+	 { "FW_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_END_ADDR[] = {
+	 { "FW_END_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_END_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_ISR_START_ADDR[] = {
+	 { "FW_ISR_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_ISR_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_HI[] = {
+	 { "FW_CHECKSUM_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_LO[] = {
+	 { "FW_CHECKSUM_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_RAM_ACCESS_CTRL[] = {
+	 { "ERAM_WR_ADDR_AUTO_INC", 0, 0, &umr_bitfield_default },
+	 { "ERAM_RD_ADDR_AUTO_INC", 1, 1, &umr_bitfield_default },
+	 { "IRAM_WR_ADDR_AUTO_INC", 2, 2, &umr_bitfield_default },
+	 { "IRAM_RD_ADDR_AUTO_INC", 3, 3, &umr_bitfield_default },
+	 { "ERAM_HOST_ACCESS_EN", 4, 4, &umr_bitfield_default },
+	 { "IRAM_HOST_ACCESS_EN", 5, 5, &umr_bitfield_default },
+	 { "UC_RST_RELEASE_DELAY_CNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_CTRL[] = {
+	 { "ERAM_WR_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_WR_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_WR_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_DATA[] = {
+	 { "ERAM_WR_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_CTRL[] = {
+	 { "ERAM_RD_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_RD_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_RD_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_DATA[] = {
+	 { "ERAM_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_CTRL[] = {
+	 { "IRAM_WR_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_DATA[] = {
+	 { "IRAM_WR_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_CTRL[] = {
+	 { "IRAM_RD_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKB_CLOCK_ENABLE[] = {
+	 { "SYMCLKB_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_DATA[] = {
+	 { "IRAM_RD_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_EVENT_TRIGGER[] = {
+	 { "GEN_SW_INT_TO_UC", 0, 0, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CODE", 16, 22, &umr_bitfield_default },
+	 { "GEN_UC_INTERNAL_INT_TO_HOST", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_INTERNAL_INT_STATUS[] = {
+	 { "UC_INT_IRQ_N_PIN", 0, 0, &umr_bitfield_default },
+	 { "UC_INT_XIRQ_N_PIN", 1, 1, &umr_bitfield_default },
+	 { "UC_INT_SOFTWARE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "UC_INT_ILLEGAL_OPCODE_TRAP", 3, 3, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_4", 4, 4, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_3", 5, 5, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_2", 6, 6, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_1", 7, 7, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "UC_INT_REAL_TIME_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5", 10, 10, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_3", 11, 11, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_2", 12, 12, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_1", 13, 13, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE", 14, 14, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_OVERFLOW", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_SS_INTERRUPT_CNTL_STATUS[] = {
+	 { "STATIC_SCREEN1_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_STATUS", 21, 21, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_STATUS[] = {
+	 { "ABM1_HG_READY_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "SCP_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "VBLANK1_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "VBLANK2_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "VBLANK3_INT_CLEAR", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_OCCURRED", 27, 27, &umr_bitfield_default },
+	 { "VBLANK4_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_OCCURRED", 28, 28, &umr_bitfield_default },
+	 { "VBLANK5_INT_CLEAR", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_OCCURRED", 29, 29, &umr_bitfield_default },
+	 { "VBLANK6_INT_CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_HOST_EN_MASK[] = {
+	 { "ABM1_HG_READY_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "SCP_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK[] = {
+	 { "ABM1_HG_READY_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_TO_UC_EN", 29, 29, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_TO_UC_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[] = {
+	 { "ABM1_HG_READY_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_XIRQ_IRQ_SEL", 29, 29, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_XIRQ_IRQ_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DMCU_SCRATCH[] = {
+	 { "DMCU_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INT_CNT[] = {
+	 { "DMCU_ABM1_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default },
+	 { "DMCU_ABM1_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default },
+	 { "DMCU_ABM1_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[] = {
+	 { "DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS", 0, 1, &umr_bitfield_default },
+	 { "DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_CLK_GATING_CNTL[] = {
+	 { "UC_IRAM_RD_DELAY", 0, 2, &umr_bitfield_default },
+	 { "UC_ERAM_RD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "UC_RBBM_RD_CLK_GATING_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG1[] = {
+	 { "MASTER_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG2[] = {
+	 { "MASTER_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG3[] = {
+	 { "MASTER_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CMD_REG[] = {
+	 { "MASTER_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKC_CLOCK_ENABLE[] = {
+	 { "SYMCLKC_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CNTL_REG[] = {
+	 { "MASTER_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG1[] = {
+	 { "SLAVE_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG2[] = {
+	 { "SLAVE_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG3[] = {
+	 { "SLAVE_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CMD_REG[] = {
+	 { "SLAVE_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CNTL_REG[] = {
+	 { "SLAVE_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "COMM_PORT_MSG_TO_HOST_IN_PROGRESS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_INDEX[] = {
+	 { "DMCU_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMCU_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_DATA[] = {
+	 { "DMCU_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_AMBIENT_LIGHT_LEVEL[] = {
+	 { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_USER_LEVEL[] = {
+	 { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_TARGET_ABM_LEVEL[] = {
+	 { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_CURRENT_ABM_LEVEL[] = {
+	 { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_FINAL_DUTY_CYCLE[] = {
+	 { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_MINIMUM_DUTY_CYCLE[] = {
+	 { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_ABM_CNTL[] = {
+	 { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[] = {
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKD_CLOCK_ENABLE[] = {
+	 { "SYMCLKD_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_GRP2_REG_LOCK[] = {
+	 { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5[] = {
+	 { "DCFEV_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_STATUS1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED", 28, 28, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_CNTL[] = {
+	 { "ABM1_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default },
+	 { "ABM1_BLANK_MODE_SUPPORT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_IPCSC_COEFF_SEL[] = {
+	 { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_0[] = {
+	 { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_1[] = {
+	 { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_2[] = {
+	 { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_3[] = {
+	 { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_4[] = {
+	 { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_12[] = {
+	 { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKE_CLOCK_ENABLE[] = {
+	 { "SYMCLKE_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_34[] = {
+	 { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default },
+	 { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default },
+	 { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_CNTL_MISC[] = {
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default },
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS5[] = {
+	 { "DCFEV_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[] = {
+	 { "DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_DEBUG_MISC[] = {
+	 { "ABM1_HG_FORCE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_FORCE_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "ABM1_BL_FORCE_INTERRUPT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HGLS_REG_READ_PROGRESS[] = {
+	 { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_MISC_CTRL[] = {
+	 { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default },
+	 { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default },
+	 { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default },
+	 { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default },
+	 { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default },
+	 { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SUM_OF_LUMA[] = {
+	 { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_PIXEL_COUNT[] = {
+	 { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKF_CLOCK_ENABLE[] = {
+	 { "SYMCLKF_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_OVR_SCAN_BIN[] = {
+	 { "ABM1_LS_OVR_SCAN_BIN", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_SAMPLE_RATE[] = {
+	 { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SAMPLE_RATE[] = {
+	 { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = {
+	 { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_1[] = {
+	 { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_2[] = {
+	 { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_3[] = {
+	 { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_4[] = {
+	 { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_5[] = {
+	 { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_6[] = {
+	 { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_7[] = {
+	 { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_8[] = {
+	 { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_9[] = {
+	 { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_10[] = {
+	 { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_11[] = {
+	 { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_12[] = {
+	 { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_13[] = {
+	 { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_14[] = {
+	 { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_15[] = {
+	 { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_16[] = {
+	 { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_17[] = {
+	 { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_18[] = {
+	 { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_19[] = {
+	 { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_20[] = {
+	 { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_21[] = {
+	 { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_22[] = {
+	 { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_23[] = {
+	 { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_24[] = {
+	 { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[] = {
+	 { "DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_MASK", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_MASK", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_MASK", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_MASK", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_MASK", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_MASK", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_MASK", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_MASK", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_MASK", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_MASK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKD_CNTL[] = {
+	 { "DVOACLKD_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKD_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKD_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKD_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKD_IN_PHASE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKC_MVP_CNTL[] = {
+	 { "DVOACLKC_MVP_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_IN_PHASE", 18, 18, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_SKEW_PHASE_OVERRIDE", 20, 20, &umr_bitfield_default },
+	 { "MVP_CLK_A_SRC_SEL", 24, 25, &umr_bitfield_default },
+	 { "MVP_CLK_B_SRC_SEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_OVERSCAN_PIXEL_VALUE[] = {
+	 { "ABM1_OVERSCAN_R_PIXEL_VALUE", 0, 9, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_G_PIXEL_VALUE", 10, 19, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_B_PIXEL_VALUE", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_BL_MASTER_LOCK[] = {
+	 { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_INDEX[] = {
+	 { "ABM_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "ABM_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_DATA[] = {
+	 { "ABM_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKC_CNTL[] = {
+	 { "DVOACLKC_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKC_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKC_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKC_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKC_IN_PHASE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_ENABLE[] = {
+	 { "DVO_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DVO_PIXEL_WIDTH", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SOURCE_SELECT[] = {
+	 { "DVO_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DVO_STEREOSYNC_SELECT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_OUTPUT[] = {
+	 { "DVO_OUTPUT_ENABLE_MODE", 0, 1, &umr_bitfield_default },
+	 { "DVO_CLOCK_MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CONTROL[] = {
+	 { "DVO_RATE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "DVO_SDRCLK_SEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_DVPDATA_WIDTH", 4, 5, &umr_bitfield_default },
+	 { "DVO_DUAL_CHANNEL_EN", 8, 8, &umr_bitfield_default },
+	 { "DVO_RESET_FIFO", 16, 16, &umr_bitfield_default },
+	 { "DVO_SYNC_PHASE", 17, 17, &umr_bitfield_default },
+	 { "DVO_INVERT_DVOCLK", 18, 18, &umr_bitfield_default },
+	 { "DVO_HSYNC_POLARITY", 20, 20, &umr_bitfield_default },
+	 { "DVO_VSYNC_POLARITY", 21, 21, &umr_bitfield_default },
+	 { "DVO_DE_POLARITY", 22, 22, &umr_bitfield_default },
+	 { "DVO_COLOR_FORMAT", 24, 25, &umr_bitfield_default },
+	 { "DVO_CTL3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC_EN[] = {
+	 { "DVO_CRC2_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_MASK[] = {
+	 { "DVO_CRC2_SIG_MASK", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_RESULT[] = {
+	 { "DVO_CRC2_SIG_RESULT", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_FIFO_ERROR_STATUS[] = {
+	 { "DVO_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DVO_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DVO_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DVO_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DVO_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DVO_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DVO_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_TEST_DEBUG_INDEX[] = {
+	 { "DVO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DVO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_TEST_DEBUG_DATA[] = {
+	 { "DVO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_ENABLE[] = {
+	 { "DAC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_POINTER_SKEW", 2, 3, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR", 4, 4, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR_ACK", 5, 5, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_TVOUT_SIM", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SOURCE_SELECT[] = {
+	 { "DAC_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DAC_TV_SELECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_EN[] = {
+	 { "DAC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_CONT_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_CONTROL[] = {
+	 { "DAC_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_ONLY_BLANKB", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB_MASK[] = {
+	 { "DAC_CRC_SIG_BLUE_MASK", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN_MASK", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED_MASK", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL_MASK[] = {
+	 { "DAC_CRC_SIG_CONTROL_MASK", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO_SOURCE[] = {
+	 { "DCCG_AUDIO_DTO0_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_SOURCE_SEL", 12, 13, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_CLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_USE_512FBR_DTO", 20, 20, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO0_USE_512FBR_DTO", 24, 24, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO1_USE_512FBR_DTO", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB[] = {
+	 { "DAC_CRC_SIG_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL[] = {
+	 { "DAC_CRC_SIG_CONTROL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SYNC_TRISTATE_CONTROL[] = {
+	 { "DAC_HSYNCA_TRISTATE", 0, 0, &umr_bitfield_default },
+	 { "DAC_VSYNCA_TRISTATE", 8, 8, &umr_bitfield_default },
+	 { "DAC_SYNCA_TRISTATE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_STEREOSYNC_SELECT[] = {
+	 { "DAC_STEREOSYNC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL[] = {
+	 { "DAC_AUTODETECT_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_FRAME_TIME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CHECK_MASK", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL2[] = {
+	 { "DAC_AUTODETECT_POWERUP_COUNTER", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_TESTMODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL3[] = {
+	 { "DAC_AUTODET_COMPARATOR_IN_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODET_COMPARATOR_OUT_DELAY", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_STATUS[] = {
+	 { "DAC_AUTODETECT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CONNECT", 4, 4, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_RED_SENSE", 8, 9, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_GREEN_SENSE", 16, 17, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_BLUE_SENSE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_INT_CONTROL[] = {
+	 { "DAC_AUTODETECT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_INT_ENABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_OUTPUT_CNTL[] = {
+	 { "DAC_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_SEL", 8, 10, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_ON_BLANKB_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_DATA[] = {
+	 { "DAC_FORCE_DATA", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_POWERDOWN[] = {
+	 { "DAC_POWERDOWN", 0, 0, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_BLUE", 8, 8, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_GREEN", 16, 16, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_RED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CONTROL[] = {
+	 { "DAC_DFORCE_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_TV_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DAC_ZSCALE_SHIFT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_ENABLE[] = {
+	 { "DAC_COMP_DDET_REF_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMP_SDET_REF_EN", 8, 8, &umr_bitfield_default },
+	 { "DAC_R_ASYNC_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DAC_G_ASYNC_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "DAC_B_ASYNC_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_OUTPUT[] = {
+	 { "DAC_COMPARATOR_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_BLUE", 1, 1, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_GREEN", 2, 2, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_RED", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_PWR_CNTL[] = {
+	 { "DAC_BG_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_PWRCNTL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_PHASE[] = {
+	 { "DCCG_AUDIO_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_DFT_CONFIG[] = {
+	 { "DAC_DFT_CONFIG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FIFO_STATUS[] = {
+	 { "DAC_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DAC_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DAC_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DAC_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DAC_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DAC_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_TEST_DEBUG_INDEX[] = {
+	 { "DAC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DAC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_TEST_DEBUG_DATA[] = {
+	 { "DAC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK1_SEL[] = {
+	 { "DCDEBUG_BUS_CLK1_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK2_SEL[] = {
+	 { "DCDEBUG_BUS_CLK2_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK3_SEL[] = {
+	 { "DCDEBUG_BUS_CLK3_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK4_SEL[] = {
+	 { "DCDEBUG_BUS_CLK4_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK5_SEL[] = {
+	 { "DCDEBUG_BUS_CLK5_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_PIN_OVERRIDE[] = {
+	 { "DCDEBUG_OUT_OVERRIDE1_PIN_SEL", 0, 4, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL", 5, 9, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_EN", 12, 12, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_PIN_SEL", 15, 19, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL", 20, 24, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_CNTL[] = {
+	 { "DCDEBUG_BLOCK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_24BIT_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCDEBUG_CLK_SEL", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_DATA[] = {
+	 { "DCDEBUG_OUT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_MODULE[] = {
+	 { "DCCG_AUDIO_DTO0_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_CONTROL[] = {
+	 { "DC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_STATUS_RESET", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC_SELECT", 8, 10, &umr_bitfield_default },
+	 { "DC_I2C_TRANSACTION_COUNT", 20, 21, &umr_bitfield_default },
+	 { "DC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_ARBITRATION[] = {
+	 { "DC_I2C_SW_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "DC_I2C_NO_QUEUED_SW_GO", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_HW_XFER", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_SW_XFER", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_USE_I2C_REG_REQ", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_USING_I2C_REG", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_USE_I2C_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_DONE_USING_I2C_REG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_INTERRUPT_CONTROL[] = {
+	 { "DC_I2C_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_MASK", 10, 10, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_INT", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_ACK", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_MASK", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_INT", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_ACK", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_MASK", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_INT", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_ACK", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_INT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_ACK", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_MASK", 26, 26, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_INT", 27, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_ACK", 28, 28, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_MASK", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_SW_STATUS[] = {
+	 { "DC_I2C_SW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_ABORTED", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_SW_TIMEOUT", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_SW_INTERRUPTED", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_SW_BUFFER_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_SW_STOPPED_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK2", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK3", 15, 15, &umr_bitfield_default },
+	 { "DC_I2C_SW_REQ", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_HW_STATUS[] = {
+	 { "DC_I2C_DDC1_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_HW_STATUS[] = {
+	 { "DC_I2C_DDC2_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_HW_STATUS[] = {
+	 { "DC_I2C_DDC3_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_HW_STATUS[] = {
+	 { "DC_I2C_DDC4_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_HW_STATUS[] = {
+	 { "DC_I2C_DDC5_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_HW_STATUS[] = {
+	 { "DC_I2C_DDC6_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SPEED[] = {
+	 { "DC_I2C_DDC1_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SETUP[] = {
+	 { "DC_I2C_DDC1_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_PHASE[] = {
+	 { "DCCG_AUDIO_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SPEED[] = {
+	 { "DC_I2C_DDC2_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SETUP[] = {
+	 { "DC_I2C_DDC2_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SPEED[] = {
+	 { "DC_I2C_DDC3_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SETUP[] = {
+	 { "DC_I2C_DDC3_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SPEED[] = {
+	 { "DC_I2C_DDC4_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SETUP[] = {
+	 { "DC_I2C_DDC4_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SPEED[] = {
+	 { "DC_I2C_DDC5_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SETUP[] = {
+	 { "DC_I2C_DDC5_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SPEED[] = {
+	 { "DC_I2C_DDC6_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SETUP[] = {
+	 { "DC_I2C_DDC6_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION0[] = {
+	 { "DC_I2C_RW0", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK0", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP0", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT0", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION1[] = {
+	 { "DC_I2C_RW1", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK1", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START1", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION2[] = {
+	 { "DC_I2C_RW2", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK2", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START2", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP2", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION3[] = {
+	 { "DC_I2C_RW3", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK3", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START3", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP3", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT3", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DATA[] = {
+	 { "DC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_INDEX", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_HW_STATUS[] = {
+	 { "DC_I2C_DDCVGA_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_MODULE[] = {
+	 { "DCCG_AUDIO_DTO1_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SPEED[] = {
+	 { "DC_I2C_DDCVGA_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SETUP[] = {
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_EDID_DETECT_CTRL[] = {
+	 { "DC_I2C_EDID_DETECT_WAIT_TIME", 0, 15, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID", 20, 23, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_SEND_RESET", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_READ_REQUEST_INTERRUPT[] = {
+	 { "DC_I2C_DDC1_READ_REQUEST_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_INT", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_ACK", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_MASK", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_INT", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_ACK", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_INT", 9, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_ACK", 10, 10, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_MASK", 11, 11, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_INT", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_ACK", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_MASK", 15, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_INT", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_ACK", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_MASK", 19, 19, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_INT", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_ACK", 22, 22, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_MASK", 23, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_INT", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_ACK", 26, 26, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_MASK", 27, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC_READ_REQUEST_ACK_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC_READ_REQUEST_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_CONTROL[] = {
+	 { "GENERIC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_INTERRUPT_CONTROL[] = {
+	 { "GENERIC_I2C_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_INT", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_ACK", 10, 10, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_MASK", 11, 11, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_STATUS[] = {
+	 { "GENERIC_I2C_STATUS", 0, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_ABORTED", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOPPED_ON_NACK", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_NACK", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SPEED[] = {
+	 { "GENERIC_I2C_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SETUP[] = {
+	 { "GENERIC_I2C_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "GENERIC_I2C_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_TRANSACTION[] = {
+	 { "GENERIC_I2C_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "GENERIC_I2C_ACK_ON_READ", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_START", 12, 12, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP", 13, 13, &umr_bitfield_default },
+	 { "GENERIC_I2C_COUNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_DATA[] = {
+	 { "GENERIC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX", 16, 19, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_SELECTION[] = {
+	 { "GENERIC_I2C_SCL_PIN_SEL", 0, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_PIN_SEL", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_DEBUG[] = {
+	 { "GENERIC_I2C_SCL_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_INPUT", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_EN", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_OUTPUT", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_INPUT", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_H[] = {
+	 { "DP_AUX_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_CONTROL[] = {
+	 { "RESPONSE_INTERRUPT_CONTROL", 0, 0, &umr_bitfield_default },
+	 { "RIRB_DMA_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "RESPONSE_OVERRUN_INTERRUPT_CONTROL", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_STATUS[] = {
+	 { "RESPONSE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "RESPONSE_OVERRUN_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_SIZE[] = {
+	 { "RIRB_SIZE", 0, 1, &umr_bitfield_default },
+	 { "RIRB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT17[] = {
+	 { "RA0_AS_A13B", 0, 0, &umr_bitfield_default },
+	 { "RA1_AS_A14B", 1, 1, &umr_bitfield_default },
+	 { "VCOUNT_BY2", 2, 2, &umr_bitfield_default },
+	 { "ADDR_CNT_BY2", 3, 3, &umr_bitfield_default },
+	 { "WRAP_A15TOA0", 5, 5, &umr_bitfield_default },
+	 { "BYTE_MODE", 6, 6, &umr_bitfield_default },
+	 { "CRTC_SYNC_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFCOUNTER_CNTL[] = {
+	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
+	 { "PERFCOUNTER_INC_MODE", 12, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_HW_CNTL_SEL", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_RUNEN_MODE", 15, 15, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTOFF_SEL", 16, 20, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTOFF_START_DIS", 21, 21, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESTART_EN", 22, 22, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT_EN", 23, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_OFF_MASK", 24, 24, &umr_bitfield_default },
+	 { "PERFCOUNTER_ACTIVE", 25, 25, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT_TYPE", 26, 26, &umr_bitfield_default },
+	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 27, 27, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED0[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_REF_DIV[] = {
+	 { "PLL_REF_DIV", 0, 9, &umr_bitfield_default },
+	 { "PLL_CALIBRATION_REF_DIV", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED1[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_FB_DIV[] = {
+	 { "PLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "PLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PLL_FB_DIV", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED2[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_POST_DIV[] = {
+	 { "PLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "PLL_POST_DIV1P5_DISPCLK", 7, 7, &umr_bitfield_default },
+	 { "PLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "PLL_POST_DIV1P5_DPREFCLK", 15, 15, &umr_bitfield_default },
+	 { "PLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED3[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_SS_AMOUNT_DSFRAC[] = {
+	 { "PLL_SS_AMOUNT_DSFRAC", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED4[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_SS_CNTL[] = {
+	 { "PLL_SS_AMOUNT_FBDIV", 0, 7, &umr_bitfield_default },
+	 { "PLL_SS_AMOUNT_NFRAC_SLIP", 8, 11, &umr_bitfield_default },
+	 { "PLL_SS_EN", 12, 12, &umr_bitfield_default },
+	 { "PLL_SS_MODE", 13, 13, &umr_bitfield_default },
+	 { "PLL_SS_STEP_SIZE_DSFRAC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED5[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_DS_CNTL[] = {
+	 { "PLL_DS_FRAC", 0, 15, &umr_bitfield_default },
+	 { "PLL_DS_ORDER", 16, 17, &umr_bitfield_default },
+	 { "PLL_DS_MODE", 18, 18, &umr_bitfield_default },
+	 { "PLL_DS_PRBS_EN", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED6[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_IDCLK_CNTL[] = {
+	 { "PLL_LTDP_IDCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "PLL_LTDP_IDCLK_DIFF_EN", 1, 1, &umr_bitfield_default },
+	 { "PLL_TMDP_IDCLK_EN", 2, 2, &umr_bitfield_default },
+	 { "PLL_TMDP_IDCLK_DIFF_EN", 3, 3, &umr_bitfield_default },
+	 { "PLL_IDCLK_EN", 4, 4, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV_RESET", 8, 8, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV_SELECT", 12, 12, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV", 16, 19, &umr_bitfield_default },
+	 { "PLL_CUR_LTDP", 20, 21, &umr_bitfield_default },
+	 { "PLL_CUR_PREDRV", 22, 23, &umr_bitfield_default },
+	 { "PLL_CUR_TMDP", 24, 25, &umr_bitfield_default },
+	 { "PLL_CML_A_DRVSTR", 26, 27, &umr_bitfield_default },
+	 { "PLL_CML_B_DRVSTR", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED7[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_CNTL[] = {
+	 { "PLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "PLL_POWER_DOWN", 1, 1, &umr_bitfield_default },
+	 { "PLL_BYPASS_CAL", 2, 2, &umr_bitfield_default },
+	 { "PLL_POST_DIV_SRC", 3, 3, &umr_bitfield_default },
+	 { "PLL_VCOREF", 4, 5, &umr_bitfield_default },
+	 { "PLL_PCIE_REFCLK_SEL", 6, 6, &umr_bitfield_default },
+	 { "PLL_ANTIGLITCH_RESETB", 7, 7, &umr_bitfield_default },
+	 { "PLL_CALREF", 8, 9, &umr_bitfield_default },
+	 { "PLL_CAL_BYPASS_REFDIV", 10, 10, &umr_bitfield_default },
+	 { "PLL_REFCLK_SEL", 11, 12, &umr_bitfield_default },
+	 { "PLL_ANTI_GLITCH_RESET", 13, 13, &umr_bitfield_default },
+	 { "PLL_XOCLK_DRV_R_EN", 14, 14, &umr_bitfield_default },
+	 { "PLL_REF_DIV_SRC", 16, 18, &umr_bitfield_default },
+	 { "PLL_LOCK_FREQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "PLL_CALIB_DONE", 20, 20, &umr_bitfield_default },
+	 { "PLL_LOCKED", 21, 21, &umr_bitfield_default },
+	 { "PLL_REFCLK_RECV_EN", 22, 22, &umr_bitfield_default },
+	 { "PLL_REFCLK_RECV_SEL", 23, 23, &umr_bitfield_default },
+	 { "PLL_TIMING_MODE_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PLL_DIG_SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED8[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_ANALOG[] = {
+	 { "PLL_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "PLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "PLL_CP", 8, 11, &umr_bitfield_default },
+	 { "PLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "PLL_VREG_FB_TRIM", 21, 23, &umr_bitfield_default },
+	 { "PLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED9[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_VREG_CNTL[] = {
+	 { "PLL_VREG_CNTL", 0, 19, &umr_bitfield_default },
+	 { "PLL_BG_VREG_BIAS", 20, 21, &umr_bitfield_default },
+	 { "PLL_VREF_SEL", 26, 26, &umr_bitfield_default },
+	 { "PLL_VREG_BIAS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED10[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UNLOCK_DETECT_CNTL[] = {
+	 { "PLL_UNLOCK_DETECT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PLL_UNLOCK_DET_RES100_SELECT", 1, 1, &umr_bitfield_default },
+	 { "PLL_UNLOCK_STICKY_STATUS", 2, 2, &umr_bitfield_default },
+	 { "PLL_UNLOCK_DET_COUNT", 4, 6, &umr_bitfield_default },
+	 { "PLL_UNLOCKED_STICKY_RST_TEST", 7, 7, &umr_bitfield_default },
+	 { "PLL_UNLOCKED_STICKY_TEST_READBACK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED11[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_DEBUG_CNTL[] = {
+	 { "PLL_DEBUG_SIGNALS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PLL_DEBUG_MUXOUT_SEL", 4, 7, &umr_bitfield_default },
+	 { "PLL_DEBUG_CLK_SEL", 8, 12, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_CNTL", 16, 23, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_READBACK", 24, 26, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED12[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UPDATE_LOCK[] = {
+	 { "PLL_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED13[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UPDATE_CNTL[] = {
+	 { "PLL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "PLL_UPDATE_POINT", 8, 8, &umr_bitfield_default },
+	 { "PLL_AUTO_RESET_DISABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED14[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED15[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFCOUNTER_STATE[] = {
+	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED16[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_XOR_LOCK[] = {
+	 { "PLL_XOR_LOCK", 0, 0, &umr_bitfield_default },
+	 { "PLL_XOR_LOCK_READBACK", 1, 1, &umr_bitfield_default },
+	 { "PLL_SPARE", 8, 13, &umr_bitfield_default },
+	 { "PLL_LOCK_COUNT_SEL", 16, 19, &umr_bitfield_default },
+	 { "PLL_LOCK_DETECTOR_RESOLUTION_FREF", 20, 22, &umr_bitfield_default },
+	 { "PLL_LOCK_DETECTOR_RESOLUTION_FFB", 23, 25, &umr_bitfield_default },
+	 { "PLL_LOCK_DETECTOR_OPAMP_BIAS", 26, 27, &umr_bitfield_default },
+	 { "PLL_FAST_LOCK_MODE_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED17[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_ANALOG_CNTL[] = {
+	 { "PLL_ANALOG_TEST_EN", 0, 0, &umr_bitfield_default },
+	 { "PLL_ANALOG_MUX_CNTL", 1, 4, &umr_bitfield_default },
+	 { "PLL_ANALOGOUT_MUX_CNTL", 5, 8, &umr_bitfield_default },
+	 { "PLL_REGREF_TRIM", 9, 13, &umr_bitfield_default },
+	 { "PLL_CALIB_FBDIV", 14, 16, &umr_bitfield_default },
+	 { "PLL_CALIB_FASTCAL", 17, 17, &umr_bitfield_default },
+	 { "PLL_TEST_SSAMP_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED18[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_REF_DIV[] = {
+	 { "VGA25_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED19[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_REF_DIV[] = {
+	 { "VGA28_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED20[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_REF_DIV[] = {
+	 { "VGA41_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED21[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_FB_DIV[] = {
+	 { "VGA25_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA25_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA25_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED22[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_FB_DIV[] = {
+	 { "VGA28_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA28_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA28_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED23[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_FB_DIV[] = {
+	 { "VGA41_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA41_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA41_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED24[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_POST_DIV[] = {
+	 { "VGA25_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA25_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA25_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED25[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_POST_DIV[] = {
+	 { "VGA28_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA28_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA28_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED26[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_POST_DIV[] = {
+	 { "VGA41_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA41_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA41_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED27[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_ANALOG[] = {
+	 { "VGA25_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA25_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA25_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA25_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA25_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED28[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_ANALOG[] = {
+	 { "VGA28_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA28_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA28_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA28_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA28_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED29[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_ANALOG[] = {
+	 { "VGA41_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA41_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA41_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA41_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA41_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED30[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPPLL_BG_CNTL[] = {
+	 { "DISPPLL_BG_PDN", 0, 0, &umr_bitfield_default },
+	 { "DISPPLL_BG_ADJ", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED31[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_DIV_UPDATE_DEBUG[] = {
+	 { "PLL_REF_DIV_CHANGED", 0, 0, &umr_bitfield_default },
+	 { "PLL_FB_DIV_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "PLL_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "PLL_UPDATE_CURRENT_STATE", 3, 4, &umr_bitfield_default },
+	 { "PLL_UPDATE_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "PLL_UPDATE_REQ", 6, 6, &umr_bitfield_default },
+	 { "PLL_UPDATE_ACK", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CVALUE_INT_MISC[] = {
+	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
+	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED32[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_STATUS_DEBUG[] = {
+	 { "PLL_DEBUG_BUS", 0, 15, &umr_bitfield_default },
+	 { "PLL_UNLOCK", 16, 16, &umr_bitfield_default },
+	 { "PLL_CAL_RESULT", 17, 20, &umr_bitfield_default },
+	 { "PLL_POWERGOOD_ISO_ENB", 24, 24, &umr_bitfield_default },
+	 { "PLL_POWERGOOD_S", 25, 25, &umr_bitfield_default },
+	 { "PLL_POWERGOOD_V", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[] = {
+	 { "SUBSYSTEM_ID_BYTE1", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED33[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_DEBUG_MUX_CNTL[] = {
+	 { "DEBUG_BUS_MUX_SEL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[] = {
+	 { "SUBSYSTEM_ID_BYTE2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED34[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_SPARE0[] = {
+	 { "PLL_SPARE0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[] = {
+	 { "SUBSYSTEM_ID_BYTE3", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED35[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_SPARE1[] = {
+	 { "PLL_SPARE1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED36[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED37[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED38[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED39[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED40[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED41[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
+	 { "PERFMON_RUN_ENABLE_SEL", 2, 7, &umr_bitfield_default },
+	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CVALUE_LOW[] = {
+	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_HI[] = {
+	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
+	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_LOW[] = {
+	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_TEST_DEBUG_INDEX[] = {
+	 { "PERFMON_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "PERFMON_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_TEST_DEBUG_DATA[] = {
+	 { "PERFMON_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_INDEX[] = {
+	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_DATA[] = {
+	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CNTL2[] = {
+	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
+	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
+	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_INDEX[] = {
+	 { "DCCG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCCG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_DATA[] = {
+	 { "DCCG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_CLK_SEL[] = {
+	 { "DCCG_TEST_CLK_GENERICA_SEL", 0, 8, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICA_INV", 12, 12, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_SEL", 16, 24, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_INV", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_CLOCK_GATING[] = {
+	 { "ENABLE_CLOCK_GATING", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO[] = {
+	 { "AZALIA_AUDIO_DTO_PHASE", 0, 15, &umr_bitfield_default },
+	 { "AZALIA_AUDIO_DTO_MODULE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO_CONTROL[] = {
+	 { "AZALIA_AUDIO_FORCE_DTO", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_SCLK_CONTROL[] = {
+	 { "AUDIO_SCLK_CONTROL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_UNDERFLOW_FILLER_SAMPLE[] = {
+	 { "AZALIA_UNDERFLOW_FILLER_SAMPLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_DATA_DMA_CONTROL[] = {
+	 { "DATA_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+	 { "INPUT_DATA_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default },
+	 { "DATA_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "INPUT_DATA_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default },
+	 { "AZALIA_IOC_GENERATION_METHOD", 16, 16, &umr_bitfield_default },
+	 { "AZALIA_UNDERFLOW_CONTROL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_BDL_DMA_CONTROL[] = {
+	 { "BDL_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+	 { "INPUT_BDL_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default },
+	 { "BDL_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "INPUT_BDL_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_RIRB_AND_DP_CONTROL[] = {
+	 { "RIRB_NON_SNOOP", 0, 0, &umr_bitfield_default },
+	 { "DP_DMA_NON_SNOOP", 4, 4, &umr_bitfield_default },
+	 { "DP_UPDATE_FREQ_DIVIDER", 5, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CORB_DMA_CONTROL[] = {
+	 { "CORB_DMA_NON_SNOOP", 0, 0, &umr_bitfield_default },
+	 { "CORB_DMA_ISOCHRONOUS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[] = {
+	 { "APPLICATION_POSITION_IN_CYCLIC_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CYCLIC_BUFFER_SYNC[] = {
+	 { "CYCLIC_BUFFER_SYNC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_GLOBAL_CAPABILITIES[] = {
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+	 { "OUTSTRMPAY", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[] = {
+	 { "LATENCY_HIDING_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "SYS_MEM_ACTIVE_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "INPUT_LATENCY_HIDING_LEVEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_PAYLOAD_CAPABILITY[] = {
+	 { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+	 { "INSTRMPAY", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_DEBUG[] = {
+	 { "CONTROLLER_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL0[] = {
+	 { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL1[] = {
+	 { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL2[] = {
+	 { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL3[] = {
+	 { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_RESULT[] = {
+	 { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[] = {
+	 { "IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD", 0, 27, &umr_bitfield_default },
+	 { "IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_I[] = {
+	 { "DP_AUX_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT18[] = {
+	 { "LINE_CMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL0[] = {
+	 { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL1[] = {
+	 { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL2[] = {
+	 { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL3[] = {
+	 { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_RESULT[] = {
+	 { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL0[] = {
+	 { "CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL1[] = {
+	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL2[] = {
+	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL3[] = {
+	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_RESULT[] = {
+	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL0[] = {
+	 { "CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL1[] = {
+	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL2[] = {
+	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL3[] = {
+	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_RESULT[] = {
+	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_MEM_PWR_CTRL[] = {
+	 { "AZ_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "AZ_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "AZ_MEM_PWR_MODE_SEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_MEM_PWR_STATUS[] = {
+	 { "AZ_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_PG_DEBUG_CONFIG[] = {
+	 { "DCI_PG_DBG_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_INDEX[] = {
+	 { "AZ_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZ_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_DATA[] = {
+	 { "AZ_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[] = {
+	 { "HBR_CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "COMPRESSED_CHANNEL_COUNT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[] = {
+	 { "RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[] = {
+	 { "PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[] = {
+	 { "INPUT_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
+	 { "INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_DEBUG[] = {
+	 { "DISABLE_FORMAT_COMPARISON", 0, 5, &umr_bitfield_default },
+	 { "CODEC_DEBUG", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET0[] = {
+	 { "GTC_GROUP_OFFSET0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET1[] = {
+	 { "GTC_GROUP_OFFSET1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET2[] = {
+	 { "GTC_GROUP_OFFSET2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET3[] = {
+	 { "GTC_GROUP_OFFSET3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET4[] = {
+	 { "GTC_GROUP_OFFSET4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET5[] = {
+	 { "GTC_GROUP_OFFSET5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET6[] = {
+	 { "GTC_GROUP_OFFSET6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH0[] = {
+	 { "DCO_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH1[] = {
+	 { "DCO_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH2[] = {
+	 { "DCO_SCRATCH2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH3[] = {
+	 { "DCO_SCRATCH3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH4[] = {
+	 { "DCO_SCRATCH4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH5[] = {
+	 { "DCO_SCRATCH5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH6[] = {
+	 { "DCO_SCRATCH6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH7[] = {
+	 { "DCO_SCRATCH7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCE_VCE_CONTROL[] = {
+	 { "DC_VCE_VIDEO_PIPE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DC_VCE_AUDIO_STREAM_SELECT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS[] = {
+	 { "SCL_DISP1_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D1BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D1_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D1_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC1_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC1_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC1_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGA_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD1_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX1_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX1_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DACA_AUTODETECT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DACB_AUTODETECT_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_HW_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DMCU_UC_INTERNAL_INT", 26, 26, &umr_bitfield_default },
+	 { "DMCU_SCP_INT", 27, 27, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT", 28, 28, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT", 29, 29, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE[] = {
+	 { "SCL_DISP2_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D2BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D2_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D2_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC2_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC2_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC2_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGB_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD2_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX2_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX2_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "LB_D1_VLINE2_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "LB_D2_VLINE2_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "LB_D3_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE2[] = {
+	 { "SCL_DISP3_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D3BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D3_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D3_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC3_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC3_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC3_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGC_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD3_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX3_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX3_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "LB_D4_VLINE2_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "LB_D5_VLINE2_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "LB_D6_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE3[] = {
+	 { "SCL_DISP4_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D4BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D4_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D4_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC4_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC4_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC4_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGD_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD4_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX4_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX4_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "BUFMGR_IHIF_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "WBSCL_HOST_CONFLICT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "WBSCL_DATA_OVERFLOW_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE4", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE4[] = {
+	 { "SCL_DISP5_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D5BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D5_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D5_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC5_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC5_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC5_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGE_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD5_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX5_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX5_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE5", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE5[] = {
+	 { "SCL_DISP6_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D6BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D6_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D6_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC6_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC6_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC6_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC6_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC6_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGF_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD6_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX6_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX6_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT0", 25, 25, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT1", 26, 26, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT2", 27, 27, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE6", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE6[] = {
+	 { "DCRX_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "BUFMGR_CWB0_IHIF_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "BUFMGR_CWB1_IHIF_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGG_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "AUX1_GTC_SYNC_ERROR_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX2_GTC_SYNC_ERROR_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "AUX3_GTC_SYNC_ERROR_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "AUX4_GTC_SYNC_ERROR_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "AUX5_GTC_SYNC_ERROR_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "AUX6_GTC_SYNC_ERROR_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE7[] = {
+	 { "DCCG_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER0_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INTERRUPT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE8", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE8[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INTERRUPT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE9", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE9[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INTERRUPT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_STATUS[] = {
+	 { "I2C_MEM_PWR_STATE", 0, 0, &umr_bitfield_default },
+	 { "TVOUT_MEM_PWR_STATE", 1, 1, &umr_bitfield_default },
+	 { "MVP_MEM_PWR_STATE", 2, 2, &umr_bitfield_default },
+	 { "DPA_MEM_PWR_STATE", 3, 3, &umr_bitfield_default },
+	 { "DPB_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "DPC_MEM_PWR_STATE", 5, 5, &umr_bitfield_default },
+	 { "DPD_MEM_PWR_STATE", 6, 6, &umr_bitfield_default },
+	 { "DPE_MEM_PWR_STATE", 7, 7, &umr_bitfield_default },
+	 { "DPF_MEM_PWR_STATE", 8, 8, &umr_bitfield_default },
+	 { "DPG_MEM_PWR_STATE", 9, 9, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_CTRL[] = {
+	 { "I2C_LIGHT_SLEEP_FORCE", 0, 0, &umr_bitfield_default },
+	 { "I2C_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default },
+	 { "TVOUT_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "MVP_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DPA_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DPB_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DPC_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DPD_LIGHT_SLEEP_DIS", 7, 7, &umr_bitfield_default },
+	 { "DPE_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DPF_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
+	 { "DPG_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_FORCE", 14, 15, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_DIS", 19, 19, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_FORCE", 23, 24, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_DIS", 25, 25, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_FORCE", 26, 27, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_DIS", 28, 28, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_FORCE", 29, 30, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_CTRL2[] = {
+	 { "HDMI_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL[] = {
+	 { "DCO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCO_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_G_ABM_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_G_DVO_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_DACA_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_DACB_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "REFCLK_R_DCO_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGA_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGB_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGC_GATE_DIS", 26, 26, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGD_GATE_DIS", 27, 27, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGE_GATE_DIS", 28, 28, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGF_GATE_DIS", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGG_GATE_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_RAMP_CNTL[] = {
+	 { "REFCLK_R_DCO_RAMP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCO_RAMP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_G_ABM_RAMP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_G_DVO_RAMP_DIS", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_DACA_RAMP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_DACB_RAMP_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT0_RAMP_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT1_RAMP_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT2_RAMP_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT3_RAMP_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT4_RAMP_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT5_RAMP_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGA_RAMP_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGB_RAMP_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGC_RAMP_DIS", 26, 26, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGD_RAMP_DIS", 27, 27, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGE_RAMP_DIS", 28, 28, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGF_RAMP_DIS", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGG_RAMP_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_CNTL[] = {
+	 { "DPDBG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DPDBG_INPUT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DPDBG_SYMCLK_ON", 4, 4, &umr_bitfield_default },
+	 { "DPDBG_ERROR_DETECTION_MODE", 8, 8, &umr_bitfield_default },
+	 { "DPDBG_LINE_LENGTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_INTERRUPT[] = {
+	 { "DPDBG_FIFO_OVERFLOW_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_TYPE", 1, 1, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_POWER_MANAGEMENT_CNTL[] = {
+	 { "PM_ASSERT_RESET", 0, 0, &umr_bitfield_default },
+	 { "PM_ALL_BUSY_OFF", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_STEREOSYNC_SEL[] = {
+	 { "GENERICA_STEREOSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "GENERICB_STEREOSYNC_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_TEST_DEBUG_INDEX[] = {
+	 { "DCO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_TEST_DEBUG_DATA[] = {
+	 { "DCO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SOFT_RESET[] = {
+	 { "DACA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "I2S0_SPDIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "I2S1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "SPDIF1_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DB_CLK_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "FMT0_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "FMT1_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FMT2_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "FMT3_SOFT_RESET", 19, 19, &umr_bitfield_default },
+	 { "FMT4_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "FMT5_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "MVP_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "ABM_SOFT_RESET", 25, 25, &umr_bitfield_default },
+	 { "DVO_SOFT_RESET", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_SOFT_RESET[] = {
+	 { "DIGA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DIGA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DIGB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DIGB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIGC_FE_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DIGC_BE_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DIGD_FE_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DIGD_BE_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DIGE_FE_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "DIGE_BE_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "DIGF_FE_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "DIGF_BE_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "DIGG_FE_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "DIGG_BE_SOFT_RESET", 25, 25, &umr_bitfield_default },
+	 { "DPDBG_SOFT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_INT_STATUS[] = {
+	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_INT_CONTROL[] = {
+	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_CONTROL[] = {
+	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[] = {
+	 { "IMMEDIATE_RESPONSE_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_J[] = {
+	 { "DP_AUX_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_STATUS[] = {
+	 { "IMMEDIATE_COMMAND_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IMMEDIATE_RESULT_VALID", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_K[] = {
+	 { "DP_AUX_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_ENABLE[] = {
+	 { "GRPH_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_CONTROL[] = {
+	 { "GRPH_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "GRPH_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "GRPH_Z", 4, 5, &umr_bitfield_default },
+	 { "GRPH_BANK_WIDTH", 6, 7, &umr_bitfield_default },
+	 { "GRPH_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "GRPH_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "GRPH_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT", 18, 19, &umr_bitfield_default },
+	 { "GRPH_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "GRPH_PIPE_CONFIG", 24, 28, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE", 29, 30, &umr_bitfield_default },
+	 { "GRPH_COLOR_EXPANSION_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_LUT_10BIT_BYPASS[] = {
+	 { "GRPH_LUT_10BIT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SWAP_CNTL[] = {
+	 { "GRPH_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "GRPH_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "GRPH_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+	 { "GRPH_ALPHA_CROSSBAR", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PRIMARY_SURFACE_ADDRESS[] = {
+	 { "GRPH_PRIMARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SECONDARY_SURFACE_ADDRESS[] = {
+	 { "GRPH_SECONDARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PITCH[] = {
+	 { "GRPH_PITCH", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_OFFSET_X[] = {
+	 { "GRPH_SURFACE_OFFSET_X", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_OFFSET_Y[] = {
+	 { "GRPH_SURFACE_OFFSET_Y", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_X_START[] = {
+	 { "GRPH_X_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_Y_START[] = {
+	 { "GRPH_Y_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_X_END[] = {
+	 { "GRPH_X_END", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_Y_END[] = {
+	 { "GRPH_Y_END", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_CONTROL[] = {
+	 { "GRPH_INPUT_GAMMA_MODE", 0, 1, &umr_bitfield_default },
+	 { "OVL_INPUT_GAMMA_MODE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_UPDATE[] = {
+	 { "GRPH_MODE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "GRPH_MODE_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_TAKEN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_SURFACE_XDMA_PENDING_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "GRPH_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SURFACE_IGNORE_UPDATE_LOCK", 20, 20, &umr_bitfield_default },
+	 { "GRPH_MODE_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_FLIP_CONTROL[] = {
+	 { "GRPH_SURFACE_UPDATE_H_RETRACE_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_XDMA_SUPER_AA_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_ADDRESS_INUSE[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_DFQ_CONTROL[] = {
+	 { "GRPH_DFQ_RESET", 0, 0, &umr_bitfield_default },
+	 { "GRPH_DFQ_SIZE", 4, 6, &umr_bitfield_default },
+	 { "GRPH_DFQ_MIN_FREE_ENTRIES", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_DFQ_STATUS[] = {
+	 { "GRPH_PRIMARY_DFQ_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_DFQ_NUM_ENTRIES", 4, 7, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_INTERRUPT_STATUS[] = {
+	 { "GRPH_PFLIP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_INTERRUPT_CONTROL[] = {
+	 { "GRPH_PFLIP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_SURFACE_ADDRESS[] = {
+	 { "GRPH_COMPRESS_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_PITCH[] = {
+	 { "GRPH_COMPRESS_PITCH", 6, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_ENABLE[] = {
+	 { "OVL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OVLSCL_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_CONTROL1[] = {
+	 { "OVL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "OVL_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "OVL_Z", 4, 5, &umr_bitfield_default },
+	 { "OVL_BANK_WIDTH", 6, 7, &umr_bitfield_default },
+	 { "OVL_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "OVL_BANK_HEIGHT", 11, 12, &umr_bitfield_default },
+	 { "OVL_TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "OVL_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OVL_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "OVL_MACRO_TILE_ASPECT", 18, 19, &umr_bitfield_default },
+	 { "OVL_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "OVL_COLOR_EXPANSION_MODE", 24, 24, &umr_bitfield_default },
+	 { "OVL_PIPE_CONFIG", 25, 29, &umr_bitfield_default },
+	 { "OVL_MICRO_TILE_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_CONTROL2[] = {
+	 { "OVL_HALF_RESOLUTION_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SWAP_CNTL[] = {
+	 { "OVL_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "OVL_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "OVL_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "OVL_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+	 { "OVL_ALPHA_CROSSBAR", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_ADDRESS[] = {
+	 { "OVL_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OVL_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_PITCH[] = {
+	 { "OVL_PITCH", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_ADDRESS_HIGH[] = {
+	 { "OVL_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_OFFSET_X[] = {
+	 { "OVL_SURFACE_OFFSET_X", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_OFFSET_Y[] = {
+	 { "OVL_SURFACE_OFFSET_Y", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_START[] = {
+	 { "OVL_Y_START", 0, 13, &umr_bitfield_default },
+	 { "OVL_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_END[] = {
+	 { "OVL_Y_END", 0, 14, &umr_bitfield_default },
+	 { "OVL_X_END", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_UPDATE[] = {
+	 { "OVL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "OVL_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "OVL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "OVL_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_ADDRESS_INUSE[] = {
+	 { "OVL_SURFACE_ADDRESS_INUSE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_DFQ_CONTROL[] = {
+	 { "OVL_DFQ_RESET", 0, 0, &umr_bitfield_default },
+	 { "OVL_DFQ_SIZE", 4, 6, &umr_bitfield_default },
+	 { "OVL_DFQ_MIN_FREE_ENTRIES", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_DFQ_STATUS[] = {
+	 { "OVL_DFQ_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "OVL_SECONDARY_DFQ_NUM_ENTRIES", 4, 7, &umr_bitfield_default },
+	 { "OVL_DFQ_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "OVL_DFQ_RESET_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_ADDRESS_HIGH_INUSE[] = {
+	 { "OVL_SURFACE_ADDRESS_HIGH_INUSE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVLSCL_EDGE_PIXEL_CNTL[] = {
+	 { "OVLSCL_BLACK_COLOR_BCB", 0, 9, &umr_bitfield_default },
+	 { "OVLSCL_BLACK_COLOR_GY", 10, 19, &umr_bitfield_default },
+	 { "OVLSCL_BLACK_COLOR_RCR", 20, 29, &umr_bitfield_default },
+	 { "OVLSCL_EDGE_PIXEL_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_GRPH_CONTROL[] = {
+	 { "GRPH_PRESCALE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_R_SIGN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_G_SIGN", 2, 2, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_B_SIGN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_BYPASS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_R[] = {
+	 { "GRPH_PRESCALE_BIAS_R", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_G[] = {
+	 { "GRPH_PRESCALE_BIAS_G", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_B[] = {
+	 { "GRPH_PRESCALE_BIAS_B", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_OVL_CONTROL[] = {
+	 { "OVL_PRESCALE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "OVL_PRESCALE_CB_SIGN", 1, 1, &umr_bitfield_default },
+	 { "OVL_PRESCALE_Y_SIGN", 2, 2, &umr_bitfield_default },
+	 { "OVL_PRESCALE_CR_SIGN", 3, 3, &umr_bitfield_default },
+	 { "OVL_PRESCALE_BYPASS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_OVL_CB[] = {
+	 { "OVL_PRESCALE_BIAS_CB", 0, 15, &umr_bitfield_default },
+	 { "OVL_PRESCALE_SCALE_CB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_OVL_Y[] = {
+	 { "OVL_PRESCALE_BIAS_Y", 0, 15, &umr_bitfield_default },
+	 { "OVL_PRESCALE_SCALE_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_OVL_CR[] = {
+	 { "OVL_PRESCALE_BIAS_CR", 0, 15, &umr_bitfield_default },
+	 { "OVL_PRESCALE_SCALE_CR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_CONTROL[] = {
+	 { "INPUT_CSC_GRPH_MODE", 0, 1, &umr_bitfield_default },
+	 { "INPUT_CSC_OVL_MODE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12[] = {
+	 { "INPUT_CSC_C11", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14[] = {
+	 { "INPUT_CSC_C13", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22[] = {
+	 { "INPUT_CSC_C21", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24[] = {
+	 { "INPUT_CSC_C23", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32[] = {
+	 { "INPUT_CSC_C31", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34[] = {
+	 { "INPUT_CSC_C33", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_CONTROL[] = {
+	 { "OUTPUT_CSC_GRPH_MODE", 0, 2, &umr_bitfield_default },
+	 { "OUTPUT_CSC_OVL_MODE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12[] = {
+	 { "OUTPUT_CSC_C11", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14[] = {
+	 { "OUTPUT_CSC_C13", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22[] = {
+	 { "OUTPUT_CSC_C21", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24[] = {
+	 { "OUTPUT_CSC_C23", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32[] = {
+	 { "OUTPUT_CSC_C31", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34[] = {
+	 { "OUTPUT_CSC_C33", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXA_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXA_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXA_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXA_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXA_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXA_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXB_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXB_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXB_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXB_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXB_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXB_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CONTROL[] = {
+	 { "DENORM_MODE", 0, 2, &umr_bitfield_default },
+	 { "DENORM_14BIT_OUT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_ROUND_CONTROL[] = {
+	 { "OUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_R_CR[] = {
+	 { "OUT_CLAMP_MAX_R_CR", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_R_CR", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_CONTROL[] = {
+	 { "KEY_SELECT", 0, 0, &umr_bitfield_default },
+	 { "KEY_MODE", 1, 2, &umr_bitfield_default },
+	 { "GRPH_OVL_HALF_BLEND", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_ALPHA[] = {
+	 { "KEY_ALPHA_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_ALPHA_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_RED[] = {
+	 { "KEY_RED_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_RED_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_GREEN[] = {
+	 { "KEY_GREEN_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_GREEN_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_BLUE[] = {
+	 { "KEY_BLUE_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_BLUE_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEGAMMA_CONTROL[] = {
+	 { "GRPH_DEGAMMA_MODE", 0, 1, &umr_bitfield_default },
+	 { "OVL_DEGAMMA_MODE", 4, 5, &umr_bitfield_default },
+	 { "CURSOR2_DEGAMMA_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_DEGAMMA_MODE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_CONTROL[] = {
+	 { "GRPH_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default },
+	 { "OVL_GAMUT_REMAP_MODE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C11_C12[] = {
+	 { "GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C13_C14[] = {
+	 { "GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C21_C22[] = {
+	 { "GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C23_C24[] = {
+	 { "GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C31_C32[] = {
+	 { "GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C33_C34[] = {
+	 { "GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_SPATIAL_DITHER_CNTL[] = {
+	 { "DCP_SPATIAL_DITHER_EN", 0, 0, &umr_bitfield_default },
+	 { "DCP_SPATIAL_DITHER_MODE", 4, 5, &umr_bitfield_default },
+	 { "DCP_SPATIAL_DITHER_DEPTH", 6, 7, &umr_bitfield_default },
+	 { "DCP_FRAME_RANDOM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DCP_RGB_RANDOM_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "DCP_HIGHPASS_RANDOM_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_RANDOM_SEEDS[] = {
+	 { "DCP_RAND_R_SEED", 0, 7, &umr_bitfield_default },
+	 { "DCP_RAND_G_SEED", 8, 15, &umr_bitfield_default },
+	 { "DCP_RAND_B_SEED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_FP_CONVERTED_FIELD[] = {
+	 { "DCP_FP_CONVERTED_FIELD_DATA", 0, 17, &umr_bitfield_default },
+	 { "DCP_FP_CONVERTED_FIELD_INDEX", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_CONTROL[] = {
+	 { "CURSOR_EN", 0, 0, &umr_bitfield_default },
+	 { "CUR_INV_TRANS_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_2X_MAGNIFY", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_FORCE_MC_ON", 20, 20, &umr_bitfield_default },
+	 { "CURSOR_URGENT_CONTROL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS[] = {
+	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SIZE[] = {
+	 { "CURSOR_HEIGHT", 0, 6, &umr_bitfield_default },
+	 { "CURSOR_WIDTH", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS_HIGH[] = {
+	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_POSITION[] = {
+	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
+	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_HOT_SPOT[] = {
+	 { "CURSOR_HOT_SPOT_Y", 0, 6, &umr_bitfield_default },
+	 { "CURSOR_HOT_SPOT_X", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR1[] = {
+	 { "CUR_COLOR1_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR1_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR1_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR2[] = {
+	 { "CUR_COLOR2_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR2_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR2_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_UPDATE[] = {
+	 { "CURSOR_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_STEREO_MODE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_MODE[] = {
+	 { "DC_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
+	 { "DC_LUT_ERROR", 16, 16, &umr_bitfield_default },
+	 { "DC_LUT_ERROR_RST", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_INDEX[] = {
+	 { "DC_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_SEQ_COLOR[] = {
+	 { "DC_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_PWL_DATA[] = {
+	 { "DC_LUT_BASE", 0, 15, &umr_bitfield_default },
+	 { "DC_LUT_DELTA", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_30_COLOR[] = {
+	 { "DC_LUT_COLOR_10_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_VGA_ACCESS_ENABLE[] = {
+	 { "DC_LUT_VGA_ACCESS_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WRITE_EN_MASK[] = {
+	 { "DC_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_AUTOFILL[] = {
+	 { "DC_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
+	 { "DC_LUT_AUTOFILL_DONE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_CONTROL[] = {
+	 { "DC_LUT_INC_B", 0, 3, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_SIGNED_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FLOAT_POINT_EN", 5, 5, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FORMAT", 6, 7, &umr_bitfield_default },
+	 { "DC_LUT_INC_G", 8, 11, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_SIGNED_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FLOAT_POINT_EN", 13, 13, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FORMAT", 14, 15, &umr_bitfield_default },
+	 { "DC_LUT_INC_R", 16, 19, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_SIGNED_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FLOAT_POINT_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FORMAT", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_BLUE[] = {
+	 { "DC_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_GREEN[] = {
+	 { "DC_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_RED[] = {
+	 { "DC_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_BLUE[] = {
+	 { "DC_LUT_WHITE_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_GREEN[] = {
+	 { "DC_LUT_WHITE_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_RED[] = {
+	 { "DC_LUT_WHITE_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_CONTROL[] = {
+	 { "DCP_CRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCP_CRC_SOURCE_SEL", 2, 4, &umr_bitfield_default },
+	 { "DCP_CRC_LINE_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_MASK[] = {
+	 { "DCP_CRC_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_CURRENT[] = {
+	 { "DCP_CRC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_LAST[] = {
+	 { "DCP_CRC_LAST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG[] = {
+	 { "DCP_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_FLIP_RATE_CNTL[] = {
+	 { "GRPH_FLIP_RATE", 0, 2, &umr_bitfield_default },
+	 { "GRPH_FLIP_RATE_ENABLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_GSL_CONTROL[] = {
+	 { "DCP_GSL0_EN", 0, 0, &umr_bitfield_default },
+	 { "DCP_GSL1_EN", 1, 1, &umr_bitfield_default },
+	 { "DCP_GSL2_EN", 2, 2, &umr_bitfield_default },
+	 { "DCP_GSL_MODE", 8, 9, &umr_bitfield_default },
+	 { "DCP_GSL_HSYNC_FLIP_FORCE_DELAY", 12, 15, &umr_bitfield_default },
+	 { "DCP_GSL_MASTER_EN", 16, 16, &umr_bitfield_default },
+	 { "DCP_GSL_XDMA_GROUP", 17, 18, &umr_bitfield_default },
+	 { "DCP_GSL_XDMA_GROUP_UNDERFLOW_EN", 19, 19, &umr_bitfield_default },
+	 { "DCP_GSL_SYNC_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "DCP_GSL_DELAY_SURFACE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
+	 { "DCP_GSL_HSYNC_FLIP_CHECK_DELAY", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[] = {
+	 { "DCP_LB_GAP_BETWEEN_CHUNK_20BPP", 0, 3, &umr_bitfield_default },
+	 { "DCP_LB_GAP_BETWEEN_CHUNK_30BPP", 4, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SECONDARY_SURFACE_ADDRESS[] = {
+	 { "OVL_SECONDARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OVL_SECONDARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_STEREOSYNC_FLIP[] = {
+	 { "OVL_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "OVL_STEREOSYNC_FLIP_MODE", 8, 9, &umr_bitfield_default },
+	 { "OVL_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "OVL_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "OVL_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "OVL_SECONDARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_TEST_DEBUG_INDEX[] = {
+	 { "DCP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_TEST_DEBUG_DATA[] = {
+	 { "DCP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_STEREOSYNC_FLIP[] = {
+	 { "GRPH_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_FLIP_MODE", 8, 9, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG2[] = {
+	 { "DCP_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_REQUEST_FILTER_CNTL[] = {
+	 { "CUR_REQUEST_FILTER_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_STEREO_CONTROL[] = {
+	 { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_STEREO_OFFSET_YNX", 1, 1, &umr_bitfield_default },
+	 { "CURSOR_PRIMARY_OFFSET", 4, 13, &umr_bitfield_default },
+	 { "CURSOR_SECONDARY_OFFSET", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_G_Y[] = {
+	 { "OUT_CLAMP_MAX_G_Y", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_G_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_B_CB[] = {
+	 { "OUT_CLAMP_MAX_B_CB", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_B_CB", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHW_ROTATION[] = {
+	 { "GRPH_ROTATION_ANGLE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[] = {
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE", 1, 1, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT", 4, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CONTROL[] = {
+	 { "GRPH_REGAMMA_MODE", 0, 2, &umr_bitfield_default },
+	 { "OVL_REGAMMA_MODE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_INDEX[] = {
+	 { "REGAMMA_LUT_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_DATA[] = {
+	 { "REGAMMA_LUT_DATA", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_WRITE_EN_MASK[] = {
+	 { "REGAMMA_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_START_CNTL[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_SLOPE_CNTL[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_END_CNTL1[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_END_CNTL2[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_0_1[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_2_3[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_4_5[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_6_7[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_8_9[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_10_11[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_12_13[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_14_15[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_START_CNTL[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_SLOPE_CNTL[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_END_CNTL1[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_END_CNTL2[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_0_1[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_2_3[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_4_5[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_6_7[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_8_9[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_10_11[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_12_13[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_14_15[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmALPHA_CONTROL[] = {
+	 { "ALPHA_ROUND_TRUNC_MODE", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_ALPHA_BLND_ENA", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[] = {
+	 { "GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[] = {
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT", 0, 19, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK", 25, 25, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK", 26, 26, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT", 28, 28, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK", 29, 29, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DATA_FORMAT[] = {
+	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "PIXEL_EXPAN_MODE", 2, 2, &umr_bitfield_default },
+	 { "INTERLEAVE_EN", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_REDUCE_MODE", 4, 4, &umr_bitfield_default },
+	 { "DYNAMIC_PIXEL_DEPTH", 5, 5, &umr_bitfield_default },
+	 { "PREFETCH", 12, 12, &umr_bitfield_default },
+	 { "REQUEST_MODE", 24, 24, &umr_bitfield_default },
+	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_MEMORY_CTRL[] = {
+	 { "LB_MEMORY_SIZE", 0, 11, &umr_bitfield_default },
+	 { "LB_NUM_PARTITIONS", 16, 19, &umr_bitfield_default },
+	 { "LB_MEMORY_CONFIG", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_MEMORY_SIZE_STATUS[] = {
+	 { "LB_MEMORY_SIZE_STATUS", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DESKTOP_HEIGHT[] = {
+	 { "DESKTOP_HEIGHT", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE_START_END[] = {
+	 { "VLINE_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE2_START_END[] = {
+	 { "VLINE2_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE2_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE2_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_V_COUNTER[] = {
+	 { "V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_SNAPSHOT_V_COUNTER[] = {
+	 { "SNAPSHOT_V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_INTERRUPT_MASK[] = {
+	 { "VBLANK_INTERRUPT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_MASK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE_STATUS[] = {
+	 { "VLINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE2_STATUS[] = {
+	 { "VLINE2_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE2_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VBLANK_STATUS[] = {
+	 { "VBLANK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VBLANK_ACK", 4, 4, &umr_bitfield_default },
+	 { "VBLANK_STAT", 12, 12, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_SYNC_RESET_SEL[] = {
+	 { "LB_SYNC_RESET_SEL", 0, 1, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_SEL2", 4, 4, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LB_SYNC_DURATION", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_R_CR[] = {
+	 { "LB_BLACK_KEYER_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_G_Y[] = {
+	 { "LB_BLACK_KEYER_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_B_CB[] = {
+	 { "LB_BLACK_KEYER_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_CTRL[] = {
+	 { "LB_KEYER_COLOR_EN", 0, 0, &umr_bitfield_default },
+	 { "LB_KEYER_COLOR_REP_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_R_CR[] = {
+	 { "LB_KEYER_COLOR_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_G_Y[] = {
+	 { "LB_KEYER_COLOR_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_B_CB[] = {
+	 { "LB_KEYER_COLOR_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_R_CR[] = {
+	 { "LB_KEYER_COLOR_REP_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_G_Y[] = {
+	 { "LB_KEYER_COLOR_REP_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_B_CB[] = {
+	 { "LB_KEYER_COLOR_REP_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_LEVEL_STATUS[] = {
+	 { "REQ_FIFO_LEVEL", 0, 5, &umr_bitfield_default },
+	 { "REQ_FIFO_FULL_CNTL", 10, 15, &umr_bitfield_default },
+	 { "DATA_BUFFER_LEVEL", 16, 27, &umr_bitfield_default },
+	 { "DATA_FIFO_FULL_CNTL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_URGENCY_CTRL[] = {
+	 { "LB_BUFFER_URGENCY_MARK_ON", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_MARK_OFF", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_URGENCY_STATUS[] = {
+	 { "LB_BUFFER_URGENCY_LEVEL", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_STAT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_STATUS[] = {
+	 { "LB_BUFFER_EMPTY_MARGIN", 0, 3, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_STAT", 4, 4, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_ACK", 12, 12, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_STAT", 16, 16, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_ACK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_NO_OUTSTANDING_REQ_STATUS[] = {
+	 { "LB_NO_OUTSTANDING_REQ_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_AFR_FLIP_MODE[] = {
+	 { "MVP_AFR_FLIP_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_AFR_FLIP_FIFO_CNTL[] = {
+	 { "MVP_AFR_FLIP_FIFO_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET", 4, 4, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FLIP_LINE_NUM_INSERT[] = {
+	 { "MVP_FLIP_LINE_NUM_INSERT_MODE", 0, 1, &umr_bitfield_default },
+	 { "MVP_FLIP_LINE_NUM_INSERT", 8, 22, &umr_bitfield_default },
+	 { "MVP_FLIP_LINE_NUM_OFFSET", 24, 29, &umr_bitfield_default },
+	 { "MVP_FLIP_AUTO_ENABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_MVP_LB_CONTROL[] = {
+	 { "MVP_SWAP_LOCK_IN_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_SEL", 8, 8, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_IN_CAP", 28, 28, &umr_bitfield_default },
+	 { "DC_MVP_SPARE_FLOPS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG[] = {
+	 { "LB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG2[] = {
+	 { "LB_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG3[] = {
+	 { "LB_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_TEST_DEBUG_INDEX[] = {
+	 { "LB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "LB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_TEST_DEBUG_DATA[] = {
+	 { "LB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_L[] = {
+	 { "DP_AUX_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_CLOCK_CONTROL[] = {
+	 { "DISPCLK_R_DCFE_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "DISPCLK_G_DCP_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_SCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "DCFE_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DCFE_CLOCK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_SOFT_RESET[] = {
+	 { "DCP_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_DBG_CONFIG[] = {
+	 { "DCFE_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE_DBG_SEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_ARBITRATION_CONTROL1[] = {
+	 { "PIXEL_DURATION", 0, 15, &umr_bitfield_default },
+	 { "BASE_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_ARBITRATION_CONTROL2[] = {
+	 { "TIME_WEIGHT", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_WATERMARK_MASK_CONTROL[] = {
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK", 0, 1, &umr_bitfield_default },
+	 { "URGENCY_WATERMARK_MASK", 8, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_URGENCY_CONTROL[] = {
+	 { "URGENCY_LOW_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_HIGH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_DPM_CONTROL[] = {
+	 { "DPM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCLK_CHANGE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCLK_CHANGE_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK_MASK", 12, 13, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_STUTTER_CONTROL[] = {
+	 { "STUTTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON", 11, 11, &umr_bitfield_default },
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[] = {
+	 { "NB_PSTATE_CHANGE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_FORCE_ON", 9, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_ALLOW_FOR_URGENT", 10, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[] = {
+	 { "STUTTER_ENABLE_NONLPTCH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR_NONLPTCH", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON_NONLPTCH", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA_NONLPTCH", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC_NONLPTCH", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON_NONLPTCH", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_TEST_DEBUG_INDEX[] = {
+	 { "DPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_TEST_DEBUG_DATA[] = {
+	 { "DPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_REPEATER_PROGRAM[] = {
+	 { "REG_DPG_DMIFRC_REPEATER", 0, 2, &umr_bitfield_default },
+	 { "REG_DMIFRC_DPG_REPEATER", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_A[] = {
+	 { "DPG_HW_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_B[] = {
+	 { "DPG_HW_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_11[] = {
+	 { "DPG_HW_DEBUG_11", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_SELECT[] = {
+	 { "SCL_C_RAM_TAP_PAIR_IDX", 0, 3, &umr_bitfield_default },
+	 { "SCL_C_RAM_PHASE", 8, 11, &umr_bitfield_default },
+	 { "SCL_C_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_TAP_DATA[] = {
+	 { "SCL_C_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
+	 { "SCL_C_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE[] = {
+	 { "SCL_MODE", 0, 1, &umr_bitfield_default },
+	 { "SCL_PSCL_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TAP_CONTROL[] = {
+	 { "SCL_V_NUM_OF_TAPS", 0, 2, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_CONTROL[] = {
+	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_EARLY_EOL_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_BYPASS_CONTROL[] = {
+	 { "SCL_BYPASS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MANUAL_REPLICATE_CONTROL[] = {
+	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
+	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_AUTOMATIC_MODE_CONTROL[] = {
+	 { "SCL_V_CALC_AUTO_RATIO_EN", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_CALC_AUTO_RATIO_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_CONTROL[] = {
+	 { "SCL_H_FILTER_PICK_NEAREST", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_SCALE_RATIO[] = {
+	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_INIT[] = {
+	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_CONTROL[] = {
+	 { "SCL_V_FILTER_PICK_NEAREST", 0, 0, &umr_bitfield_default },
+	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_SCALE_RATIO[] = {
+	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_INIT[] = {
+	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_INIT_BOT[] = {
+	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_ROUND_OFFSET[] = {
+	 { "SCL_ROUND_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
+	 { "SCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_UPDATE[] = {
+	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "SCL_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "SCL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "SCL_COEF_UPDATE_COMPLETE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_F_SHARP_CONTROL[] = {
+	 { "SCL_HF_SHARP_SCALE_FACTOR", 0, 2, &umr_bitfield_default },
+	 { "SCL_HF_SHARP_EN", 4, 4, &umr_bitfield_default },
+	 { "SCL_VF_SHARP_SCALE_FACTOR", 8, 10, &umr_bitfield_default },
+	 { "SCL_VF_SHARP_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_ALU_CONTROL[] = {
+	 { "SCL_ALU_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_CONFLICT_STATUS[] = {
+	 { "SCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_START_SECONDARY[] = {
+	 { "VIEWPORT_Y_START_SECONDARY", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_START[] = {
+	 { "VIEWPORT_Y_START", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_SIZE[] = {
+	 { "VIEWPORT_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_LEFT_RIGHT[] = {
+	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_TOP_BOTTOM[] = {
+	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET1[] = {
+	 { "SCL_MODE_CHANGE", 0, 0, &umr_bitfield_default },
+	 { "SCL_MODE_CHANGE_ACK", 4, 4, &umr_bitfield_default },
+	 { "SCL_ALU_H_SCALE_RATIO", 7, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET2[] = {
+	 { "SCL_ALU_V_SCALE_RATIO", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET3[] = {
+	 { "SCL_ALU_SOURCE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "SCL_ALU_SOURCE_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_MASK[] = {
+	 { "SCL_MODE_CHANGE_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_DEBUG2[] = {
+	 { "SCL_DEBUG_REQ_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_DEBUG_EOF_MODE", 1, 2, &umr_bitfield_default },
+	 { "SCL_DEBUG2", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_DEBUG[] = {
+	 { "SCL_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TEST_DEBUG_INDEX[] = {
+	 { "SCL_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SCL_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TEST_DEBUG_DATA[] = {
+	 { "SCL_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_CONTROL[] = {
+	 { "BLND_GLOBAL_GAIN", 0, 7, &umr_bitfield_default },
+	 { "BLND_MODE", 8, 9, &umr_bitfield_default },
+	 { "BLND_STEREO_TYPE", 10, 11, &umr_bitfield_default },
+	 { "BLND_STEREO_POLARITY", 12, 12, &umr_bitfield_default },
+	 { "BLND_FEEDTHROUGH_EN", 13, 13, &umr_bitfield_default },
+	 { "BLND_ALPHA_MODE", 16, 17, &umr_bitfield_default },
+	 { "BLND_MULTIPLIED_MODE", 20, 20, &umr_bitfield_default },
+	 { "BLND_GLOBAL_ALPHA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSM_CONTROL2[] = {
+	 { "SM_MODE", 0, 2, &umr_bitfield_default },
+	 { "SM_FRAME_ALTERNATE", 4, 4, &umr_bitfield_default },
+	 { "SM_FIELD_ALTERNATE", 5, 5, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
+	 { "SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_CONTROL2[] = {
+	 { "PTI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PTI_NEW_PIXEL_GAP", 4, 5, &umr_bitfield_default },
+	 { "BLND_NEW_PIXEL_MODE", 6, 6, &umr_bitfield_default },
+	 { "BLND_SUPERAA_DEGAMMA_EN", 7, 7, &umr_bitfield_default },
+	 { "BLND_SUPERAA_REGAMMA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_UPDATE[] = {
+	 { "BLND_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "BLND_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "BLND_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_UNDERFLOW_INTERRUPT[] = {
+	 { "BLND_UNDERFLOW_INT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_PIPE_INDEX", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_V_UPDATE_LOCK[] = {
+	 { "BLND_DCP_GRPH_V_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BLND_DCP_GRPH_SURF_V_UPDATE_LOCK", 1, 1, &umr_bitfield_default },
+	 { "BLND_DCP_OVL_V_UPDATE_LOCK", 8, 8, &umr_bitfield_default },
+	 { "BLND_DCP_CUR_V_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "BLND_DCP_CUR2_V_UPDATE_LOCK", 24, 24, &umr_bitfield_default },
+	 { "BLND_SCL_V_UPDATE_LOCK", 28, 28, &umr_bitfield_default },
+	 { "BLND_BLND_V_UPDATE_LOCK", 29, 29, &umr_bitfield_default },
+	 { "BLND_V_UPDATE_LOCK_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_DEBUG[] = {
+	 { "BLND_CNV_MUX_SELECT", 0, 0, &umr_bitfield_default },
+	 { "BLND_DEBUG", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_TEST_DEBUG_INDEX[] = {
+	 { "BLND_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "BLND_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_TEST_DEBUG_DATA[] = {
+	 { "BLND_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_REG_UPDATE_STATUS[] = {
+	 { "DCP_BLNDC_GRPH_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
+	 { "DCP_BLNDC_GRPH_SURF_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_SURF_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
+	 { "DCP_BLNDC_OVL_UPDATE_PENDING", 4, 4, &umr_bitfield_default },
+	 { "DCP_BLNDO_OVL_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
+	 { "DCP_BLNDC_CUR_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
+	 { "DCP_BLNDO_CUR_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
+	 { "SCL_BLNDC_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "SCL_BLNDO_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
+	 { "BLND_BLNDC_UPDATE_PENDING", 10, 10, &umr_bitfield_default },
+	 { "BLND_BLNDO_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_3D_STRUCTURE_CONTROL[] = {
+	 { "CRTC_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_EN_DB", 4, 4, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_VSYNC_GAP[] = {
+	 { "CRTC_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_WINDOW[] = {
+	 { "CRTC_GSL_WINDOW_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_GSL_WINDOW_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_CONTROL[] = {
+	 { "CRTC_GSL_CHECK_LINE_NUM", 0, 13, &umr_bitfield_default },
+	 { "CRTC_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DCFE_CLOCK_CONTROL[] = {
+	 { "CRTC_DISPCLK_R_DCFE_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_DISPCLK_G_DCP_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_DISPCLK_G_SCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "CRTC_DCFE_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "CRTC_DCFE_CLOCK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_BLANK_EARLY_NUM[] = {
+	 { "CRTC_H_BLANK_EARLY_NUM", 0, 9, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_EARLY_NUM_DIS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_DBG_SEL[] = {
+	 { "DCFE_DBG_SEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_CTRL[] = {
+	 { "DCP_LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DCP_LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_FORCE", 21, 22, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_FORCE", 27, 28, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_DIS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_TOTAL[] = {
+	 { "CRTC_H_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_BLANK_START_END[] = {
+	 { "CRTC_H_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_A[] = {
+	 { "CRTC_H_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_A_CNTL[] = {
+	 { "CRTC_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_B[] = {
+	 { "CRTC_H_SYNC_B_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_B_CNTL[] = {
+	 { "CRTC_H_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_B_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VBI_END[] = {
+	 { "CRTC_VBI_V_END", 0, 13, &umr_bitfield_default },
+	 { "CRTC_VBI_H_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL[] = {
+	 { "CRTC_V_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_MIN[] = {
+	 { "CRTC_V_TOTAL_MIN", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_MAX[] = {
+	 { "CRTC_V_TOTAL_MAX", 0, 13, &umr_bitfield_default },
+	 { "CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_CONTROL[] = {
+	 { "CRTC_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_TOTAL_MAX_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_ON_EVENT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_TO_MASTER_VSYNC", 12, 12, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK_EN", 15, 15, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_INT_STATUS[] = {
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VSYNC_NOM_INT_STATUS[] = {
+	 { "CRTC_VSYNC_NOM", 0, 0, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_BLANK_START_END[] = {
+	 { "CRTC_V_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_A[] = {
+	 { "CRTC_V_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_A_CNTL[] = {
+	 { "CRTC_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_B[] = {
+	 { "CRTC_V_SYNC_B_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_B_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_B_CNTL[] = {
+	 { "CRTC_V_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DTMTEST_CNTL[] = {
+	 { "CRTC_DTMTEST_CRTC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_CLK_DIV", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DTMTEST_STATUS_POSITION[] = {
+	 { "CRTC_DTMTEST_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGA_CNTL[] = {
+	 { "CRTC_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGA_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGA_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGB_CNTL[] = {
+	 { "CRTC_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGB_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGB_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FORCE_COUNT_NOW_CNTL[] = {
+	 { "CRTC_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FLOW_CONTROL[] = {
+	 { "CRTC_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_FORCE_NEXT_EYE[] = {
+	 { "CRTC_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_AVSYNC_COUNTER[] = {
+	 { "CRTC_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CONTROL[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SYNC_RESET_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
+	 { "CRTC_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
+	 { "CRTC_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_HBLANK_EARLY_CONTROL", 20, 22, &umr_bitfield_default },
+	 { "CRTC_DISP_READ_REQUEST_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SOF_PULL_EN", 29, 29, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LOCK_SNAPSHOT", 30, 30, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_VSYNC_N_HSYNC_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_CONTROL[] = {
+	 { "CRTC_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERLACE_CONTROL[] = {
+	 { "CRTC_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERLACE_STATUS[] = {
+	 { "CRTC_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FIELD_INDICATION_CONTROL[] = {
+	 { "CRTC_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_PIXEL_DATA_READBACK0[] = {
+	 { "CRTC_PIXEL_DATA_BLUE_CB", 0, 11, &umr_bitfield_default },
+	 { "CRTC_PIXEL_DATA_GREEN_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_PIXEL_DATA_READBACK1[] = {
+	 { "CRTC_PIXEL_DATA_RED_CR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS[] = {
+	 { "CRTC_V_BLANK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A", 2, 2, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "CRTC_V_START_LINE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_H_BLANK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_POSITION[] = {
+	 { "CRTC_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_NOM_VERT_POSITION[] = {
+	 { "CRTC_VERT_COUNT_NOM", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_FRAME_COUNT[] = {
+	 { "CRTC_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_VF_COUNT[] = {
+	 { "CRTC_VF_COUNT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_HV_COUNT[] = {
+	 { "CRTC_HV_COUNT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_COUNT_CONTROL[] = {
+	 { "CRTC_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_COUNT_RESET[] = {
+	 { "CRTC_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
+	 { "CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERT_SYNC_CONTROL[] = {
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "CRTC_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_STATUS[] = {
+	 { "CRTC_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
+	 { "CRTC_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_CONTROL[] = {
+	 { "CRTC_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 13, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT_POLARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
+	 { "CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
+	 { "CRTC_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
+	 { "CRTC_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
+	 { "CRTC_STEREO_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_STATUS[] = {
+	 { "CRTC_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_CONTROL[] = {
+	 { "CRTC_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_POSITION[] = {
+	 { "CRTC_SNAPSHOT_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_FRAME[] = {
+	 { "CRTC_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_START_LINE_CONTROL[] = {
+	 { "CRTC_PROGRESSIVE_START_LINE_EARLY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_START_LINE_EARLY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_ADVANCED_START_LINE_POSITION", 12, 19, &umr_bitfield_default },
+	 { "CRTC_LEGACY_REQUESTOR_EN", 20, 20, &umr_bitfield_default },
+	 { "CRTC_PREFETCH_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERRUPT_CONTROL[] = {
+	 { "CRTC_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_MSK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_TYPE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_UPDATE_LOCK[] = {
+	 { "CRTC_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DOUBLE_BUFFER_CONTROL[] = {
+	 { "CRTC_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CRTC_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VGA_PARAMETER_CAPTURE_MODE[] = {
+	 { "CRTC_VGA_PARAMETER_CAPTURE_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_CTRL2[] = {
+	 { "DCP_LUT_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_MODE_SEL", 2, 3, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_MODE_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_MODE_SEL", 6, 7, &umr_bitfield_default },
+	 { "LB_ALPHA_MEM_PWR_MODE_SEL", 8, 9, &umr_bitfield_default },
+	 { "LB_MEM_PWR_MODE_SEL", 10, 11, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_MODE_SEL", 14, 15, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
+	 { "OVLSCL_MEM_PWR_FORCE", 19, 19, &umr_bitfield_default },
+	 { "OVLSCL_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_FORCE", 21, 22, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_STATUS[] = {
+	 { "DCP_LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "OVLSCL_MEM_PWR_STATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_CONTROL[] = {
+	 { "CRTC_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_PARAMETERS[] = {
+	 { "CRTC_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_COLOR[] = {
+	 { "CRTC_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_UPDATE_LOCK[] = {
+	 { "MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "GSL_CONTROL_MASTER_UPDATE_LOCK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_UPDATE_MODE[] = {
+	 { "MASTER_UPDATE_MODE", 0, 2, &umr_bitfield_default },
+	 { "MASTER_UPDATE_INTERLACED_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_INBAND_CNTL_INSERT[] = {
+	 { "CRTC_MVP_INBAND_OUT_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[] = {
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_STATUS[] = {
+	 { "CRTC_FLIP_NOW_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FLIP_NOW_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MASTER_EN[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_ALLOW_STOP_OFF_V_CNT[] = {
+	 { "CRTC_ALLOW_STOP_OFF_V_CNT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_UPDATE_INT_STATUS[] = {
+	 { "CRTC_V_UPDATE_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_DEBUG_INDEX[] = {
+	 { "CRTC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_DEBUG_DATA[] = {
+	 { "CRTC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_OVERSCAN_COLOR[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE", 0, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN", 10, 19, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_OVERSCAN_COLOR_EXT[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_DATA_COLOR[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_DATA_COLOR_EXT[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLACK_COLOR[] = {
+	 { "CRTC_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLACK_COLOR_EXT[] = {
+	 { "CRTC_BLACK_COLOR_B_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT0_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT0_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT1_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_LINE_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT1_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT2_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_LINE_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT2_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC_CNTL[] = {
+	 { "CRTC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "CRTC_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_CRC0_SELECT", 20, 22, &umr_bitfield_default },
+	 { "CRTC_CRC1_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_DATA_RG[] = {
+	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_DATA_B[] = {
+	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_DATA_RG[] = {
+	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_DATA_B[] = {
+	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW", 5, 6, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE", 9, 9, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY", 12, 12, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY", 13, 13, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INTERLACE_MODE", 14, 14, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE", 24, 26, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_WINDOW_START[] = {
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_START_X", 0, 13, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_START_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_WINDOW_END[] = {
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_END_X", 0, 13, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_END_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE", 20, 20, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INT_TYPE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATIC_SCREEN_CONTROL[] = {
+	 { "CRTC_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
+	 { "CRTC_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SS_STATUS", 25, 25, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_R[] = {
+	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_G[] = {
+	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_B[] = {
+	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEST_DEBUG_INDEX[] = {
+	 { "FMT_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FMT_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEST_DEBUG_DATA[] = {
+	 { "FMT_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DYNAMIC_EXP_CNTL[] = {
+	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CONTROL[] = {
+	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "FMT_STEREOSYNC_OVR_POL", 4, 4, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
+	 { "FMT_PIXEL_ENCODING", 16, 16, &umr_bitfield_default },
+	 { "FMT_SUBSAMPLING_MODE", 17, 17, &umr_bitfield_default },
+	 { "FMT_SUBSAMPLING_ORDER", 18, 18, &umr_bitfield_default },
+	 { "FMT_SRC_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_FORCE_OUTPUT_CNTL[] = {
+	 { "FMT_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA_SEL_COLOR", 8, 10, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA_SEL_SLOT", 12, 15, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA_ON_BLANKB_ONLY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_FORCE_DATA_0_1[] = {
+	 { "FMT_FORCE_DATA0", 0, 15, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_FORCE_DATA_2_3[] = {
+	 { "FMT_FORCE_DATA2", 0, 15, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_BIT_DEPTH_CONTROL[] = {
+	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
+	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
+	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
+	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
+	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
+	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_R_SEED[] = {
+	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_G_SEED[] = {
+	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_B_SEED[] = {
+	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT", 0, 0, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_CNTL[] = {
+	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_CNTL[] = {
+	 { "FMT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_DTMTEST_CRC_EN", 1, 1, &umr_bitfield_default },
+	 { "FMT_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "FMT_CRC_ONLY_BLANKB", 8, 8, &umr_bitfield_default },
+	 { "FMT_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "FMT_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "FMT_CRC_EVEN_ODD_PIX_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FMT_CRC_EVEN_ODD_PIX_SELECT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_RED_GREEN_MASK[] = {
+	 { "FMT_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_BLUE_CONTROL_MASK[] = {
+	 { "FMT_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_RED_GREEN[] = {
+	 { "FMT_CRC_SIG_RED", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_BLUE_CONTROL[] = {
+	 { "FMT_CRC_SIG_BLUE", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_CONTROL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DEBUG_CNTL[] = {
+	 { "FMT_DEBUG_COLOR_SELECT", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMA_POSITION_LOWER_BASE_ADDRESS[] = {
+	 { "DMA_POSITION_BUFFER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS", 1, 6, &umr_bitfield_default },
+	 { "DMA_POSITION_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_M[] = {
+	 { "DP_AUX_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMA_POSITION_UPPER_BASE_ADDRESS[] = {
+	 { "DMA_POSITION_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_N[] = {
+	 { "DP_AUX_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_O[] = {
+	 { "DP_AUX_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1E[] = {
+	 { "GRPH_DEC_RD1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_P[] = {
+	 { "DP_AUX_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1F[] = {
+	 { "GRPH_DEC_RD0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_WORSTCASE_LATENCY_COUNT[] = {
+	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL2[] = {
+	 { "INPUT_CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL2[] = {
+	 { "CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMIF_DEBUG02_CORE0[] = {
+	 { "DB_DATA", 0, 15, &umr_bitfield_default },
+	 { "MC_RDRET_COUNT_EN", 16, 16, &umr_bitfield_default },
+	 { "MC_RDRET_COUNTER", 17, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR1[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_CONTROL[] = {
+	 { "CONTROLLER_RESET", 0, 0, &umr_bitfield_default },
+	 { "FLUSH_CONTROL", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_UNSOLICITED_RESPONSE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG2[] = {
+	 { "DCIO_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG1[] = {
+	 { "FMT_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR02[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ02[] = {
+	 { "SEQ_MAP0_EN", 0, 0, &umr_bitfield_default },
+	 { "SEQ_MAP1_EN", 1, 1, &umr_bitfield_default },
+	 { "SEQ_MAP2_EN", 2, 2, &umr_bitfield_default },
+	 { "SEQ_MAP3_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
+	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
+	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
+	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
+	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
+	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
+	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
+	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
+	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_Q[] = {
+	 { "DP_AUX_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
+	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
+	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT22[] = {
+	 { "GRPH_LATCH_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+	 { "STREAM_TYPE_R", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
+	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
+	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
+	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
+	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
+	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
+	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[] = {
+	 { "CC", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[] = {
+	 { "KEEPALIVE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
+	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CNTL[] = {
+	 { "FBC_GRPH_COMP_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_SRC_SEL", 1, 3, &umr_bitfield_default },
+	 { "FBC_COHERENCY_MODE", 16, 17, &umr_bitfield_default },
+	 { "FBC_SOFT_COMPRESS_EN", 25, 25, &umr_bitfield_default },
+	 { "FBC_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_MASK[] = {
+	 { "FBC_IDLE_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_FORCE_CLEAR_MASK[] = {
+	 { "FBC_IDLE_FORCE_CLEAR_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_START_STOP_DELAY[] = {
+	 { "FBC_DECOMP_START_DELAY", 0, 4, &umr_bitfield_default },
+	 { "FBC_DECOMP_STOP_DELAY", 7, 7, &umr_bitfield_default },
+	 { "FBC_COMP_START_DELAY", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_CNTL[] = {
+	 { "FBC_MIN_COMPRESSION", 0, 3, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO08_EN", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO16_EN", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB04_EN", 18, 18, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB08_EN", 19, 19, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB16_EN", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_MODE[] = {
+	 { "FBC_RLE_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_DPCM4_RGB_EN", 8, 8, &umr_bitfield_default },
+	 { "FBC_DPCM8_RGB_EN", 9, 9, &umr_bitfield_default },
+	 { "FBC_DPCM4_YUV_EN", 10, 10, &umr_bitfield_default },
+	 { "FBC_DPCM8_YUV_EN", 11, 11, &umr_bitfield_default },
+	 { "FBC_IND_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG0[] = {
+	 { "FBC_PERF_MUX0", 0, 7, &umr_bitfield_default },
+	 { "FBC_PERF_MUX1", 8, 15, &umr_bitfield_default },
+	 { "FBC_COMP_WAKE_DIS", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG0", 17, 23, &umr_bitfield_default },
+	 { "FBC_DEBUG_MUX", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG1[] = {
+	 { "FBC_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG2[] = {
+	 { "FBC_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT0[] = {
+	 { "FBC_IND_LUT0", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT1[] = {
+	 { "FBC_IND_LUT1", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT2[] = {
+	 { "FBC_IND_LUT2", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT3[] = {
+	 { "FBC_IND_LUT3", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT4[] = {
+	 { "FBC_IND_LUT4", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT5[] = {
+	 { "FBC_IND_LUT5", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT6[] = {
+	 { "FBC_IND_LUT6", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT7[] = {
+	 { "FBC_IND_LUT7", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT8[] = {
+	 { "FBC_IND_LUT8", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT9[] = {
+	 { "FBC_IND_LUT9", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT10[] = {
+	 { "FBC_IND_LUT10", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT11[] = {
+	 { "FBC_IND_LUT11", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT12[] = {
+	 { "FBC_IND_LUT12", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT13[] = {
+	 { "FBC_IND_LUT13", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT14[] = {
+	 { "FBC_IND_LUT14", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT15[] = {
+	 { "FBC_IND_LUT15", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_01[] = {
+	 { "FBC_CSM_REGION_OFFSET_0", 0, 9, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_23[] = {
+	 { "FBC_CSM_REGION_OFFSET_2", 0, 9, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_3", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CLIENT_REGION_MASK[] = {
+	 { "FBC_MEMORY_REGION_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_COMP[] = {
+	 { "FBC_COMP_SWAP", 0, 1, &umr_bitfield_default },
+	 { "FBC_COMP_RSIZE", 3, 3, &umr_bitfield_default },
+	 { "FBC_COMP_BUSY_HYSTERESIS", 4, 7, &umr_bitfield_default },
+	 { "FBC_COMP_CLK_CNTL", 8, 9, &umr_bitfield_default },
+	 { "FBC_COMP_PRIVILEGED_ACCESS_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "FBC_COMP_ADDRESS_TRANSLATION_ENABLE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR[] = {
+	 { "FBC_DEBUG_CSR_ADDR", 0, 9, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_WR_DATA", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_RD_DATA", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA[] = {
+	 { "FBC_DEBUG_CSR_RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA[] = {
+	 { "FBC_DEBUG_CSR_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_RDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_WDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_MISC[] = {
+	 { "FBC_DECOMPRESS_ERROR", 0, 1, &umr_bitfield_default },
+	 { "FBC_STOP_ON_ERROR", 2, 2, &umr_bitfield_default },
+	 { "FBC_INVALIDATE_ON_ERROR", 3, 3, &umr_bitfield_default },
+	 { "FBC_ERROR_PIXEL", 4, 7, &umr_bitfield_default },
+	 { "FBC_DIVIDE_X", 8, 9, &umr_bitfield_default },
+	 { "FBC_DIVIDE_Y", 10, 10, &umr_bitfield_default },
+	 { "FBC_RSM_WRITE_VALUE", 11, 11, &umr_bitfield_default },
+	 { "FBC_RSM_UNCOMP_DATA_IMMEDIATELY", 12, 12, &umr_bitfield_default },
+	 { "FBC_DECOMPRESS_ERROR_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "FBC_RESET_AT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FBC_RESET_AT_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "FBC_SLOW_REQ_INTERVAL", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_STATUS[] = {
+	 { "FBC_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_INDEX[] = {
+	 { "FBC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FBC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_DATA[] = {
+	 { "FBC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL1[] = {
+	 { "MVP_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_MIXER_MODE", 4, 6, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK", 9, 9, &umr_bitfield_default },
+	 { "MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE", 10, 10, &umr_bitfield_default },
+	 { "MVP_RATE_CONTROL", 12, 12, &umr_bitfield_default },
+	 { "MVP_CHANNEL_CONTROL", 16, 16, &umr_bitfield_default },
+	 { "MVP_GPU_CHAIN_LOCATION", 20, 21, &umr_bitfield_default },
+	 { "MVP_DISABLE_MSB_EXPAND", 24, 24, &umr_bitfield_default },
+	 { "MVP_30BPP_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_A", 30, 30, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_B", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL2[] = {
+	 { "MVP_MUX_DE_DVOCNTL0_SEL", 0, 0, &umr_bitfield_default },
+	 { "MVP_MUX_DE_DVOCNTL2_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_MUXA_CLK_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MUXB_CLK_SEL", 12, 12, &umr_bitfield_default },
+	 { "MVP_DVOCNTL_MUX", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_OUT_EN", 24, 24, &umr_bitfield_default },
+	 { "MVP_SWAP_AB_IN_DC_DDR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_CONTROL[] = {
+	 { "MVP_STOP_SLAVE_WM", 0, 7, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_WM", 8, 15, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_CNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_STATUS[] = {
+	 { "MVP_FIFO_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_ACK", 16, 16, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW", 20, 20, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_ACK", 28, 28, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_MASK", 30, 30, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_SLAVE_STATUS[] = {
+	 { "MVP_SLAVE_PIXELS_PER_LINE_RCVED", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINES_PER_FRAME_RCVED", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_INBAND_CNTL_CAP[] = {
+	 { "MVP_IGNOR_INBAND_CNTL", 0, 0, &umr_bitfield_default },
+	 { "MVP_PASSING_INBAND_CNTL_EN", 4, 4, &umr_bitfield_default },
+	 { "MVP_INBAND_CNTL_CHAR_CAP", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_BLACK_KEYER[] = {
+	 { "MVP_BLACK_KEYER_R", 0, 9, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_G", 10, 19, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_B", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_CNTL[] = {
+	 { "MVP_CRC_BLUE_MASK", 0, 7, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_MASK", 8, 15, &umr_bitfield_default },
+	 { "MVP_CRC_RED_MASK", 16, 23, &umr_bitfield_default },
+	 { "MVP_CRC_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_CRC_CONT_EN", 29, 29, &umr_bitfield_default },
+	 { "MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_BLUE_GREEN[] = {
+	 { "MVP_CRC_BLUE_RESULT", 0, 15, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_RESULT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_RED[] = {
+	 { "MVP_CRC_RED_RESULT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL3[] = {
+	 { "MVP_RESET_IN_BETWEEN_FRAMES", 0, 0, &umr_bitfield_default },
+	 { "MVP_DDR_SC_AB_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_DDR_SC_B_START_MODE", 8, 8, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_CASCADE_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_48BIT_EN", 24, 24, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_CAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL1[] = {
+	 { "MVP_SLAVE_PIXEL_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINE_ERROR_CNT", 16, 28, &umr_bitfield_default },
+	 { "MVP_SLAVE_DATA_CHK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL2[] = {
+	 { "MVP_SLAVE_FRAME_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_FRAME_ERROR_CNT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_INDEX[] = {
+	 { "MVP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MVP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_DATA[] = {
+	 { "MVP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_DEBUG[] = {
+	 { "MVP_SWAP_LOCK_IN_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_EN", 1, 1, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_IN_SEL", 2, 2, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_SEL", 3, 3, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP", 4, 4, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP", 5, 5, &umr_bitfield_default },
+	 { "MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR", 6, 6, &umr_bitfield_default },
+	 { "MVP_DIS_READ_POINTER_RESET_DELAY", 7, 7, &umr_bitfield_default },
+	 { "MVP_DEBUG_BITS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_CONFIG[] = {
+	 { "PIPE0_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_ENABLE[] = {
+	 { "PIPE0_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_STATUS[] = {
+	 { "PIPE0_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE0_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE0_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_CONFIG[] = {
+	 { "PIPE1_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_ENABLE[] = {
+	 { "PIPE1_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_STATUS[] = {
+	 { "PIPE1_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE1_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE1_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE1_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE1_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_CONFIG[] = {
+	 { "PIPE2_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_ENABLE[] = {
+	 { "PIPE2_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_STATUS[] = {
+	 { "PIPE2_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE2_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE2_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE2_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE2_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_CONFIG[] = {
+	 { "PIPE3_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_ENABLE[] = {
+	 { "PIPE3_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_STATUS[] = {
+	 { "PIPE3_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE3_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE3_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE3_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE3_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_CONFIG[] = {
+	 { "PIPE4_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_ENABLE[] = {
+	 { "PIPE4_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_STATUS[] = {
+	 { "PIPE4_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE4_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE4_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE4_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE4_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_CONFIG[] = {
+	 { "PIPE5_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_ENABLE[] = {
+	 { "PIPE5_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_STATUS[] = {
+	 { "PIPE5_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE5_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE5_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE5_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE5_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_IP_REQUEST_CNTL[] = {
+	 { "IP_REQUEST_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_CONFIG_REG[] = {
+	 { "PGFSM_CONFIG_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_WRITE_REG[] = {
+	 { "PGFSM_WRITE_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGCNTL_STATUS_REG[] = {
+	 { "SWREQ_RWOP_BUSY", 0, 0, &umr_bitfield_default },
+	 { "SWREQ_RWOP_FORCE", 1, 1, &umr_bitfield_default },
+	 { "IPREQ_IGNORE_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DCPG_ECO_DEBUG", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_INDEX[] = {
+	 { "DCPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_DATA[] = {
+	 { "DCPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_CONTROL[] = {
+	 { "DMIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_GROUP_REQUESTS_IN_CHUNK", 2, 2, &umr_bitfield_default },
+	 { "DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT", 4, 4, &umr_bitfield_default },
+	 { "DMIF_REQ_BURST_SIZE", 8, 10, &umr_bitfield_default },
+	 { "DMIF_UNDERFLOW_RECOVERY_EN", 11, 11, &umr_bitfield_default },
+	 { "DMIF_FORCE_TOTAL_REQ_BURST_SIZE", 12, 15, &umr_bitfield_default },
+	 { "DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS", 16, 21, &umr_bitfield_default },
+	 { "DMIF_DELAY_ARBITRATION", 24, 28, &umr_bitfield_default },
+	 { "DMIF_CHUNK_BUFF_MARGIN", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS[] = {
+	 { "DMIF_MC_SEND_ON_IDLE", 0, 7, &umr_bitfield_default },
+	 { "DMIF_CLEAR_MC_SEND_ON_IDLE", 8, 15, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_URGENT_ONLY", 17, 17, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT", 20, 22, &umr_bitfield_default },
+	 { "DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT", 24, 26, &umr_bitfield_default },
+	 { "DMIF_UNDERFLOW", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_HW_DEBUG[] = {
+	 { "DMIF_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ARBITRATION_CONTROL[] = {
+	 { "DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "PIPE_SWITCH_EFFICIENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[] = {
+	 { "PORTID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CUMULATIVE_LATENCY_COUNT[] = {
+	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL3[] = {
+	 { "INPUT_CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL3[] = {
+	 { "CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTATE_CHANGE_STATUS[] = {
+	 { "STATE_CHANGE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR2[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG3[] = {
+	 { "DCIO_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG2[] = {
+	 { "FMT_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR03[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ03[] = {
+	 { "SEQ_FONT_B1", 0, 0, &umr_bitfield_default },
+	 { "SEQ_FONT_B2", 1, 1, &umr_bitfield_default },
+	 { "SEQ_FONT_A1", 2, 2, &umr_bitfield_default },
+	 { "SEQ_FONT_A2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_FONT_B0", 4, 4, &umr_bitfield_default },
+	 { "SEQ_FONT_A0", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_P_VMID[] = {
+	 { "P_VMID_PIPE0", 0, 3, &umr_bitfield_default },
+	 { "P_VMID_PIPE1", 4, 7, &umr_bitfield_default },
+	 { "P_VMID_PIPE2", 8, 11, &umr_bitfield_default },
+	 { "P_VMID_PIPE3", 12, 15, &umr_bitfield_default },
+	 { "P_VMID_PIPE4", 16, 19, &umr_bitfield_default },
+	 { "P_VMID_PIPE5", 20, 23, &umr_bitfield_default },
+	 { "P_VMID_PIPE6", 24, 27, &umr_bitfield_default },
+	 { "P_VMID_PIPE7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_INDEX[] = {
+	 { "DMIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_DATA[] = {
+	 { "DMIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CALC[] = {
+	 { "ADDR_CONFIG_PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ADDR_CONFIG_ROW_SIZE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS2[] = {
+	 { "DMIF_PIPE0_DISPCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DMIF_PIPE1_DISPCLK_STATUS", 1, 1, &umr_bitfield_default },
+	 { "DMIF_PIPE2_DISPCLK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DMIF_PIPE3_DISPCLK_STATUS", 3, 3, &umr_bitfield_default },
+	 { "DMIF_PIPE4_DISPCLK_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DMIF_PIPE5_DISPCLK_STATUS", 5, 5, &umr_bitfield_default },
+	 { "DMIF_CHUNK_TRACKER_SCLK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DMIF_FBC_TRACKER_SCLK_STATUS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLOW_POWER_TILING_CONTROL[] = {
+	 { "LOW_POWER_TILING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_MODE", 3, 4, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_PIPES", 5, 7, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_BANKS", 8, 10, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE", 11, 11, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROW_SIZE", 12, 14, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROWS_PER_CHAN", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_CONTROL[] = {
+	 { "MCIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "ADDRESS_TRANSLATION_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "PRIVILEGED_ACCESS_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MCIF_SLOW_REQ_INTERVAL", 12, 15, &umr_bitfield_default },
+	 { "LOW_READ_URG_LEVEL", 16, 23, &umr_bitfield_default },
+	 { "MC_CLEAN_DEASSERT_LATENCY", 24, 29, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_URGENT_ONLY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WRITE_COMBINE_CONTROL[] = {
+	 { "MCIF_WRITE_COMBINE_TIMEOUT", 0, 7, &umr_bitfield_default },
+	 { "VIP_WRITE_COMBINE_TIMEOUT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_INDEX[] = {
+	 { "MCIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MCIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_DATA[] = {
+	 { "MCIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_VMID[] = {
+	 { "MCIF_WR_VMID", 0, 3, &umr_bitfield_default },
+	 { "VIP_WR_VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_MEM_CONTROL[] = {
+	 { "MCIFMEM_CACHE_MODE_DIS", 0, 0, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_MODE", 4, 5, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_SIZE", 8, 15, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_PIPE", 16, 18, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_TYPE", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
+	 { "DC_PIPE_DIS", 1, 6, &umr_bitfield_default },
+	 { "MCIF_WB_URG_OVRD", 8, 8, &umr_bitfield_default },
+	 { "MCIF_WB_URG_LVL", 9, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DC_INTERFACE_NACK_STATUS[] = {
+	 { "DMIF_RDRET_NACK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DMIF_RDRET_NACK_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_TIMEOUT[] = {
+	 { "RBBMIF_TIMEOUT_DELAY", 0, 19, &umr_bitfield_default },
+	 { "RBBMIF_ACK_HOLD", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_STATUS[] = {
+	 { "RBBMIF_TIMEOUT_CLIENTS_DEC", 0, 14, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_OP", 28, 28, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_RDWR_STATUS", 29, 29, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_ACK", 30, 30, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_MASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_TIMEOUT_DIS[] = {
+	 { "CLIENT0_TIMEOUT_DIS", 0, 0, &umr_bitfield_default },
+	 { "CLIENT1_TIMEOUT_DIS", 1, 1, &umr_bitfield_default },
+	 { "CLIENT2_TIMEOUT_DIS", 2, 2, &umr_bitfield_default },
+	 { "CLIENT3_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "CLIENT4_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "CLIENT5_TIMEOUT_DIS", 5, 5, &umr_bitfield_default },
+	 { "CLIENT6_TIMEOUT_DIS", 6, 6, &umr_bitfield_default },
+	 { "CLIENT7_TIMEOUT_DIS", 7, 7, &umr_bitfield_default },
+	 { "CLIENT8_TIMEOUT_DIS", 8, 8, &umr_bitfield_default },
+	 { "CLIENT9_TIMEOUT_DIS", 9, 9, &umr_bitfield_default },
+	 { "CLIENT10_TIMEOUT_DIS", 10, 10, &umr_bitfield_default },
+	 { "CLIENT11_TIMEOUT_DIS", 11, 11, &umr_bitfield_default },
+	 { "CLIENT12_TIMEOUT_DIS", 12, 12, &umr_bitfield_default },
+	 { "CLIENT13_TIMEOUT_DIS", 13, 13, &umr_bitfield_default },
+	 { "CLIENT14_TIMEOUT_DIS", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATUS[] = {
+	 { "DMIF_RDREQ_MEM1_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM2_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_STATE", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_STATE", 8, 8, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_STATE", 9, 10, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_STATE", 11, 11, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_STATE", 22, 22, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_STATE", 26, 27, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_STATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATUS2[] = {
+	 { "DMIF1_ASYNC_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_STATE", 5, 6, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_STATE", 7, 8, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_STATE", 9, 9, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_STATE", 14, 14, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_PWR_STATE", 15, 16, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_STATE", 17, 18, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_STATE", 19, 19, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_STATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_CLK_CNTL[] = {
+	 { "DCI_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCI_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_M_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "SCLK_G_STREAM_AZ_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "SCLK_R_AZ_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_FBC_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_VGA_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "DISPCLK_G_VIP_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "VPCLK_POL", 14, 14, &umr_bitfield_default },
+	 { "DISPCLK_G_DMCU_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "SCLK_G_DMIF_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "SCLK_G_DMIFTRK_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "SCLK_G_CNTL_AZ_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIFV_L_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIFV_C_GATE_DIS", 26, 26, &umr_bitfield_default },
+	 { "DCI_PG_TEST_CLK_SEL", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL[] = {
+	 { "DMIF_RDREQ_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_FORCE", 3, 3, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_FORCE", 5, 5, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_FORCE", 7, 7, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_FORCE", 12, 12, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_FORCE", 14, 15, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_DIS", 19, 19, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_FORCE", 23, 24, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_DIS", 25, 25, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_FORCE", 26, 27, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_DIS", 28, 28, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_FORCE", 29, 29, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL2[] = {
+	 { "DMIF0_ASYNC_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_DIS", 7, 7, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_FORCE", 14, 14, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_DIS", 15, 15, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_FORCE", 19, 20, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_DIS", 21, 21, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_FORCE", 22, 22, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_FORCE", 27, 28, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_DIS", 29, 29, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_FORCE", 30, 30, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL3[] = {
+	 { "DMIF4_ASYNC_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_DIS", 7, 7, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_FORCE", 14, 14, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_DIS", 15, 15, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM_PWR_MODE_SEL", 16, 17, &umr_bitfield_default },
+	 { "DMIF_ASYNC_MEM_PWR_MODE_SEL", 18, 19, &umr_bitfield_default },
+	 { "DMIF_DATA_MEM_PWR_MODE_SEL", 20, 21, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_MODE_SEL", 22, 22, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_MODE_SEL", 23, 24, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_MODE_SEL", 25, 26, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_MODE_SEL", 27, 28, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_MODE_SEL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_INDEX[] = {
+	 { "DCI_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCI_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_DATA[] = {
+	 { "DCI_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_DEBUG_CONFIG[] = {
+	 { "DCI_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCI_DBG_BLOCK_SEL", 4, 7, &umr_bitfield_default },
+	 { "DCI_DBG_CLOCK_SEL", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_STATUS_FLAG[] = {
+	 { "RBBMIF_STATE", 0, 2, &umr_bitfield_default },
+	 { "RBBMIF_ACK_TIMEOUT", 3, 3, &umr_bitfield_default },
+	 { "RBBMIF_READ_TIMEOUT", 4, 4, &umr_bitfield_default },
+	 { "RBBMIF_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
+	 { "RBBMIF_FIFO_FULL", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_SOFT_RESET[] = {
+	 { "VGA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "VIP_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "MCIF_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "FBC_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "DMIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DMIF1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DMIF2_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DMIF3_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "DMIF4_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DMIF5_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DCFEV0_L_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "DCFEV0_C_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "DMIFARB_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "MCIF_DWB_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "MCIF_CWB0_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "MCIF_CWB1_SOFT_RESET", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_URG_OVERRIDE[] = {
+	 { "DMIF_URG_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "DMIF_URG_OVERRIDE_LEVEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE6_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE7_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE6_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE7_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
+	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
+	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[] = {
+	 { "CONNECTION_LIST_ENTRY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
+	 { "MISC", 0, 3, &umr_bitfield_default },
+	 { "COLOR", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
+	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
+	 { "LOCATION", 0, 5, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[] = {
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 8, 8, &umr_bitfield_default },
+	 { "DP_CONNECTION", 9, 9, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[] = {
+	 { "LFE_PLAYBACK_LEVEL", 0, 1, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 3, 6, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[] = {
+	 { "DESCRIPTOR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "FORMAT_CODE", 3, 6, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[] = {
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[] = {
+	 { "MULTICHANNEL23_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[] = {
+	 { "MULTICHANNEL45_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[] = {
+	 { "MULTICHANNEL67_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[] = {
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[] = {
+	 { "SINK_INFO_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[] = {
+	 { "SINK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
+	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
+	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
+	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
+	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[] = {
+	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
+	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
+	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
+	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
+	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
+	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
+	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
+	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MC_PCIE_CLIENT_CONFIG[] = {
+	 { "XDMA_MC_PCIE_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING1[] = {
+	 { "XDMA_LOCAL_ARRAY_MODE", 0, 3, &umr_bitfield_default },
+	 { "XDMA_LOCAL_TILE_SPLIT", 4, 6, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_WIDTH", 8, 9, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MACRO_TILE_ASPECT", 12, 13, &umr_bitfield_default },
+	 { "XDMA_LOCAL_NUM_BANKS", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING2[] = {
+	 { "XDMA_LOCAL_PIPE_INTERLEAVE_SIZE", 0, 2, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MICRO_TILE_MODE", 20, 22, &umr_bitfield_default },
+	 { "XDMA_LOCAL_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_INTERRUPT[] = {
+	 { "XDMA_MSTR_MEM_URGENT_STAT", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_MASK", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_ACK", 10, 10, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_STAT", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_MASK", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_ACK", 18, 18, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_STAT", 20, 20, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_MASK", 21, 21, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_ACK", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_CLOCK_GATING_CNTL[] = {
+	 { "XDMA_SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "XDMA_SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "XDMA_SCLK_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "XDMA_SCLK_REG_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1", 18, 18, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4", 21, 21, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5", 22, 22, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SDYN_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MSTAT_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SSTAT_GATE_DIS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MEM_POWER_CNTL[] = {
+	 { "XDMA_MEM_CORE_IDLE_STATE", 0, 1, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_IDLE_STATE", 2, 3, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_PCIE_STATE", 19, 20, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_PCIE_TRANS", 21, 21, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_RD_STATE", 22, 23, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_RD_TRANS", 25, 25, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_WR_STATE", 26, 27, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_WR_TRANS", 28, 28, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_BIF_STATE", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_BIF_TRANS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_BIF_STATUS[] = {
+	 { "XDMA_IF_BIF_ERROR_STATUS", 0, 3, &umr_bitfield_default },
+	 { "XDMA_IF_BIF_ERROR_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PERF_MEAS_STATUS[] = {
+	 { "XDMA_PERF_MEAS_STATUS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_STATUS[] = {
+	 { "XDMA_MC_PCIEWR_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_DATA[] = {
+	 { "XDMA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CNTL[] = {
+	 { "XDMA_MSTR_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_READY", 14, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_DEBUG_MODE", 18, 18, &umr_bitfield_default },
+	 { "XDMA_MSTR_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "XDMA_MSTR_BIF_STALL_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_STATUS[] = {
+	 { "XDMA_MSTR_VCOUNT_CURRENT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_WRITE_LINE_CURRENT", 16, 27, &umr_bitfield_default },
+	 { "XDMA_MSTR_STATUS_SELECT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
+	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[] = {
+	 { "CONNECTION_LIST_LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_PITCH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_PITCH", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CMD_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_CMD_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_CMD_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_CMD_STALL_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PCIE_NACK_STATUS[] = {
+	 { "XDMA_MSTR_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_NACK_STATUS[] = {
+	 { "XDMA_MSTR_MEM_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_VSYNC_GSL_CHECK[] = {
+	 { "XDMA_MSTR_VSYNC_GSL_CHECK_SEL", 0, 2, &umr_bitfield_default },
+	 { "XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT", 8, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_RBBMIF_RDWR_CNTL[] = {
+	 { "XDMA_RBBMIF_RDWR_DELAY", 0, 2, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_TIMEOUT_DELAY", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_CONTROL[] = {
+	 { "XDMA_PG_CONTROL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_WDATA[] = {
+	 { "XDMA_PG_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_STATUS[] = {
+	 { "XDMA_SERDES_RDATA", 0, 23, &umr_bitfield_default },
+	 { "XDMA_PGFSM_READ_READY", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SERDES_BUSY", 25, 25, &umr_bitfield_default },
+	 { "XDMA_SERDES_SMU_POWER_STATUS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_AON_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_AON_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_AON_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+	 { "XDMA_DEBUG_SEL", 9, 9, &umr_bitfield_default },
+	 { "XDMA_DEBUG_OUT_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_AON_TEST_DEBUG_DATA[] = {
+	 { "XDMA_AON_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[] = {
+	 { "PORTID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CUMULATIVE_REQUEST_COUNT[] = {
+	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL4[] = {
+	 { "INPUT_CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL4[] = {
+	 { "CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR3[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_STATUS[] = {
+	 { "FLUSH_STATUS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG4[] = {
+	 { "DCIO_DEBUG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR04[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ04[] = {
+	 { "SEQ_256K", 1, 1, &umr_bitfield_default },
+	 { "SEQ_ODDEVEN", 2, 2, &umr_bitfield_default },
+	 { "SEQ_CHAIN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
+	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PIPE_CNTL[] = {
+	 { "XDMA_MSTR_CACHE_LINES", 0, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_READ_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FRAME_MODE", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_INVALIDATE", 11, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_CHANNEL_ID", 12, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_FLIP_MODE", 15, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_MIN", 16, 23, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_ACTIVE", 24, 24, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FLUSHING", 25, 25, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FLIP_PENDING", 26, 26, &umr_bitfield_default },
+	 { "XDMA_MSTR_VSYNC_GSL_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "XDMA_MSTR_SUPERAA_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "XDMA_MSTR_HSYNC_GSL_GROUP", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_GSL_GROUP_MASTER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_READ_COMMAND[] = {
+	 { "XDMA_MSTR_REQUEST_SIZE", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_PREFETCH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CHANNEL_DIM[] = {
+	 { "XDMA_MSTR_CHANNEL_WIDTH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CHANNEL_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_HEIGHT[] = {
+	 { "XDMA_MSTR_ACTIVE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_FRAME_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_CACHE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_CACHE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE[] = {
+	 { "XDMA_MSTR_CACHE_PITCH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_TLB_PG_STATE", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_TLB_PG_TRANS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CHANNEL_START[] = {
+	 { "XDMA_MSTR_CHANNEL_START_X", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CHANNEL_START_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_STATUS[] = {
+	 { "XDMA_MSTR_PERFMEAS_DATA", 0, 23, &umr_bitfield_default },
+	 { "XDMA_MSTR_PERFMEAS_INDEX", 24, 26, &umr_bitfield_default },
+	 { "XDMA_MSTR_PERFMEAS_INDEX_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_CNTL[] = {
+	 { "XDMA_MSTR_CACHE_BW_MEAS_ITER", 0, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_BW_SEGID_SEL", 12, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_BW_COUNTER_RST", 17, 17, &umr_bitfield_default },
+	 { "XDMA_MSTR_LT_MEAS_ITER", 19, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_LT_COUNTER_RST", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
+	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
+	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CNTL[] = {
+	 { "XDMA_SLV_READ_LINES", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_READY", 9, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "XDMA_SLV_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SLV_REQ_MAXED_OUT", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SLV_WB_BURST_RESET", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_ENABLE[] = {
+	 { "GRPH_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_CONTROL[] = {
+	 { "GRPH_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "GRPH_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "GRPH_Z", 4, 5, &umr_bitfield_default },
+	 { "GRPH_BANK_WIDTH", 6, 7, &umr_bitfield_default },
+	 { "GRPH_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "GRPH_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "GRPH_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT", 18, 19, &umr_bitfield_default },
+	 { "GRPH_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "GRPH_PIPE_CONFIG", 24, 28, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE", 29, 30, &umr_bitfield_default },
+	 { "GRPH_COLOR_EXPANSION_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_CONTROL_EXP[] = {
+	 { "VIDEO_FORMAT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SWAP_CNTL[] = {
+	 { "GRPH_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "GRPH_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "GRPH_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_PRIMARY_DFQ_ENABLE_L", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_PRIMARY_DFQ_ENABLE_C", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_L", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_PRIMARY_BOTTOM_DFQ_ENABLE_C", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_SECONDARY_DFQ_ENABLE_L", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_SECONDARY_DFQ_ENABLE_C", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_SLV_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_L", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_SECONDARY_BOTTOM_DFQ_ENABLE_C", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PITCH_L[] = {
+	 { "GRPH_PITCH_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PITCH_C[] = {
+	 { "GRPH_PITCH_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_X_L[] = {
+	 { "GRPH_SURFACE_OFFSET_X_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_X_C[] = {
+	 { "GRPH_SURFACE_OFFSET_X_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_Y_L[] = {
+	 { "GRPH_SURFACE_OFFSET_Y_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_Y_C[] = {
+	 { "GRPH_SURFACE_OFFSET_Y_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_START_L[] = {
+	 { "GRPH_X_START_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_START_C[] = {
+	 { "GRPH_X_START_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_START_L[] = {
+	 { "GRPH_Y_START_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_START_C[] = {
+	 { "GRPH_Y_START_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_SLS_PITCH[] = {
+	 { "XDMA_SLV_SLS_PITCH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_SLS_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_END_L[] = {
+	 { "GRPH_X_END_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_END_C[] = {
+	 { "GRPH_X_END_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_END_L[] = {
+	 { "GRPH_Y_END_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_END_C[] = {
+	 { "GRPH_Y_END_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_UPDATE[] = {
+	 { "GRPH_MODE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "GRPH_MODE_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_TAKEN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SURFACE_IGNORE_UPDATE_LOCK", 20, 20, &umr_bitfield_default },
+	 { "GRPH_MODE_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_DFQ_CONTROL[] = {
+	 { "GRPH_DFQ_RESET", 0, 0, &umr_bitfield_default },
+	 { "GRPH_DFQ_SIZE", 4, 6, &umr_bitfield_default },
+	 { "GRPH_DFQ_MIN_FREE_ENTRIES", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_DFQ_STATUS[] = {
+	 { "GRPH_PRIMARY_DFQ_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_DFQ_NUM_ENTRIES", 4, 7, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_INTERRUPT_STATUS[] = {
+	 { "GRPH_PFLIP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_INTERRUPT_CONTROL[] = {
+	 { "GRPH_PFLIP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_STEREOSYNC_FLIP[] = {
+	 { "GRPH_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_FLIP_MODE", 4, 5, &umr_bitfield_default },
+	 { "GRPH_STACK_INTERLACE_FLIP_EN", 8, 8, &umr_bitfield_default },
+	 { "GRPH_STACK_INTERLACE_FLIP_MODE", 12, 13, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_PENDING", 18, 18, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_PENDING", 19, 19, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_FLIP_RATE_CNTL[] = {
+	 { "GRPH_FLIP_RATE", 0, 2, &umr_bitfield_default },
+	 { "GRPH_FLIP_RATE_ENABLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_URGENT_CNTL[] = {
+	 { "XDMA_SLV_READ_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_CONTROL[] = {
+	 { "UNP_CRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "UNP_CRC_SOURCE_SEL", 2, 4, &umr_bitfield_default },
+	 { "UNP_CRC_LINE_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_MASK[] = {
+	 { "UNP_CRC_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_CURRENT[] = {
+	 { "UNP_CRC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_LAST[] = {
+	 { "UNP_CRC_LAST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[] = {
+	 { "UNP_LB_GAP_BETWEEN_CHUNK", 4, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_HW_ROTATION[] = {
+	 { "ROTATION_ANGLE", 0, 2, &umr_bitfield_default },
+	 { "PIXEL_DROP", 4, 4, &umr_bitfield_default },
+	 { "BUFFER_MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DEBUG[] = {
+	 { "UNP_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DEBUG2[] = {
+	 { "UNP_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_TEST_DEBUG_INDEX[] = {
+	 { "UNP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "UNP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_TEST_DEBUG_DATA[] = {
+	 { "UNP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DATA_FORMAT[] = {
+	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "PIXEL_EXPAN_MODE", 2, 2, &umr_bitfield_default },
+	 { "INTERLEAVE_EN", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_REDUCE_MODE", 4, 4, &umr_bitfield_default },
+	 { "DYNAMIC_PIXEL_DEPTH", 5, 5, &umr_bitfield_default },
+	 { "DITHER_EN", 6, 6, &umr_bitfield_default },
+	 { "DOWNSCALE_PREFETCH_EN", 7, 7, &umr_bitfield_default },
+	 { "PREFETCH", 12, 12, &umr_bitfield_default },
+	 { "REQUEST_MODE", 24, 24, &umr_bitfield_default },
+	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_MEMORY_CTRL[] = {
+	 { "LB_MEMORY_SIZE", 0, 11, &umr_bitfield_default },
+	 { "LB_NUM_PARTITIONS", 16, 19, &umr_bitfield_default },
+	 { "LB_MEMORY_CONFIG", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_MEMORY_SIZE_STATUS[] = {
+	 { "LB_MEMORY_SIZE_STATUS", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DESKTOP_HEIGHT[] = {
+	 { "DESKTOP_HEIGHT", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WRITE_URGENT_CNTL[] = {
+	 { "XDMA_SLV_WRITE_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_STALL_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE_START_END[] = {
+	 { "VLINE_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE2_START_END[] = {
+	 { "VLINE2_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE2_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE2_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_V_COUNTER[] = {
+	 { "V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SNAPSHOT_V_COUNTER[] = {
+	 { "SNAPSHOT_V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_V_COUNTER_CHROMA[] = {
+	 { "V_COUNTER_CHROMA", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SNAPSHOT_V_COUNTER_CHROMA[] = {
+	 { "SNAPSHOT_V_COUNTER_CHROMA", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_INTERRUPT_MASK[] = {
+	 { "VBLANK_INTERRUPT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_MASK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE_STATUS[] = {
+	 { "VLINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE2_STATUS[] = {
+	 { "VLINE2_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE2_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VBLANK_STATUS[] = {
+	 { "VBLANK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VBLANK_ACK", 4, 4, &umr_bitfield_default },
+	 { "VBLANK_STAT", 12, 12, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SYNC_RESET_SEL[] = {
+	 { "LB_SYNC_RESET_SEL", 0, 1, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_SEL2", 4, 4, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LB_SYNC_DURATION", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_R_CR[] = {
+	 { "LB_BLACK_KEYER_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_G_Y[] = {
+	 { "LB_BLACK_KEYER_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_B_CB[] = {
+	 { "LB_BLACK_KEYER_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_CTRL[] = {
+	 { "LB_KEYER_COLOR_EN", 0, 0, &umr_bitfield_default },
+	 { "LB_KEYER_COLOR_REP_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_R_CR[] = {
+	 { "LB_KEYER_COLOR_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WB_RATE_CNTL[] = {
+	 { "XDMA_SLV_WB_BURST_SIZE", 0, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_WB_BURST_PERIOD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_G_Y[] = {
+	 { "LB_KEYER_COLOR_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_B_CB[] = {
+	 { "LB_KEYER_COLOR_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_R_CR[] = {
+	 { "LB_KEYER_COLOR_REP_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_G_Y[] = {
+	 { "LB_KEYER_COLOR_REP_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_B_CB[] = {
+	 { "LB_KEYER_COLOR_REP_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_LEVEL_STATUS[] = {
+	 { "REQ_FIFO_LEVEL", 0, 5, &umr_bitfield_default },
+	 { "REQ_FIFO_FULL_CNTL", 10, 15, &umr_bitfield_default },
+	 { "DATA_BUFFER_LEVEL", 16, 27, &umr_bitfield_default },
+	 { "DATA_FIFO_FULL_CNTL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_URGENCY_CTRL[] = {
+	 { "LB_BUFFER_URGENCY_MARK_ON", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_MARK_OFF", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_URGENCY_STATUS[] = {
+	 { "LB_BUFFER_URGENCY_LEVEL", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_STAT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_STATUS[] = {
+	 { "LB_BUFFER_EMPTY_MARGIN", 0, 3, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_STAT", 4, 4, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_ACK", 12, 12, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_STAT", 16, 16, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_ACK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_NO_OUTSTANDING_REQ_STATUS[] = {
+	 { "LB_NO_OUTSTANDING_REQ_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG[] = {
+	 { "LB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG2[] = {
+	 { "LB_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG3[] = {
+	 { "LB_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_MINMAX[] = {
+	 { "XDMA_SLV_READ_LATENCY_MIN", 0, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_TEST_DEBUG_INDEX[] = {
+	 { "LB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "LB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_TEST_DEBUG_DATA[] = {
+	 { "LB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_AVE[] = {
+	 { "XDMA_SLV_READ_LATENCY_ACC", 0, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_COUNT", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_COEF_RAM_SELECT[] = {
+	 { "SCL_C_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default },
+	 { "SCL_C_RAM_PHASE", 8, 14, &umr_bitfield_default },
+	 { "SCL_C_RAM_FILTER_TYPE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_COEF_RAM_TAP_DATA[] = {
+	 { "SCL_C_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
+	 { "SCL_C_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE[] = {
+	 { "SCL_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_PSCL_EN", 4, 4, &umr_bitfield_default },
+	 { "SCL_INTERLACE_SOURCE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TAP_CONTROL[] = {
+	 { "SCL_V_NUM_OF_TAPS", 0, 2, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS", 4, 6, &umr_bitfield_default },
+	 { "SCL_V_NUM_OF_TAPS_C", 8, 10, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS_C", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_CONTROL[] = {
+	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_EARLY_EOL_MODE", 4, 4, &umr_bitfield_default },
+	 { "SCL_TOTAL_PHASE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MANUAL_REPLICATE_CONTROL[] = {
+	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
+	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_AUTOMATIC_MODE_CONTROL[] = {
+	 { "SCL_V_CALC_AUTO_RATIO_EN", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_CALC_AUTO_RATIO_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_CONTROL[] = {
+	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_SCALE_RATIO[] = {
+	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT[] = {
+	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_SCALE_RATIO_C[] = {
+	 { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT_C[] = {
+	 { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_CONTROL[] = {
+	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_SCALE_RATIO[] = {
+	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT[] = {
+	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_BOT[] = {
+	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_PCIE_NACK_STATUS[] = {
+	 { "XDMA_SLV_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_SCALE_RATIO_C[] = {
+	 { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_C[] = {
+	 { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_C", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_BOT_C[] = {
+	 { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT_C", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_ROUND_OFFSET[] = {
+	 { "SCL_ROUND_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
+	 { "SCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_UPDATE[] = {
+	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "SCL_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "SCL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "SCL_COEF_UPDATE_COMPLETE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_ALU_CONTROL[] = {
+	 { "SCL_ALU_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START[] = {
+	 { "VIEWPORT_Y_START", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_SECONDARY[] = {
+	 { "VIEWPORT_Y_START_SECONDARY", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_SIZE[] = {
+	 { "VIEWPORT_HEIGHT", 0, 12, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_C[] = {
+	 { "VIEWPORT_Y_START_C", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_C", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_SECONDARY_C[] = {
+	 { "VIEWPORT_Y_START_SECONDARY_C", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY_C", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_SIZE_C[] = {
+	 { "VIEWPORT_HEIGHT_C", 0, 12, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH_C", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[] = {
+	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[] = {
+	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET1[] = {
+	 { "SCL_MODE_CHANGE", 0, 0, &umr_bitfield_default },
+	 { "SCL_MODE_CHANGE_ACK", 4, 4, &umr_bitfield_default },
+	 { "SCL_ALU_H_SCALE_RATIO", 7, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET2[] = {
+	 { "SCL_ALU_V_SCALE_RATIO", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_NACK_STATUS[] = {
+	 { "XDMA_SLV_MEM_NACK_TAG", 0, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK", 16, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK_CLR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET3[] = {
+	 { "SCL_ALU_SOURCE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "SCL_ALU_SOURCE_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_MASK[] = {
+	 { "SCL_MODE_CHANGE_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_DEBUG2[] = {
+	 { "SCL_DEBUG_REQ_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_DEBUG_EOF_MODE", 1, 2, &umr_bitfield_default },
+	 { "SCL_DEBUG2", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_DEBUG[] = {
+	 { "SCL_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TEST_DEBUG_INDEX[] = {
+	 { "SCL_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SCL_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TEST_DEBUG_DATA[] = {
+	 { "SCL_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_RDRET_BUF_STATUS[] = {
+	 { "XDMA_SLV_RDRET_FREE_ENTRIES", 0, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_BUF_SIZE", 12, 21, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_PG_STATE", 22, 23, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_PG_TRANS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_UPDATE[] = {
+	 { "COL_MAN_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "COL_MAN_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "COL_MAN_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "COL_MAN_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_INPUT_CSC_CONTROL[] = {
+	 { "INPUT_CSC_MODE", 0, 1, &umr_bitfield_default },
+	 { "INPUT_CSC_INPUT_TYPE", 2, 3, &umr_bitfield_default },
+	 { "INPUT_CSC_CONVERSION_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12_A[] = {
+	 { "INPUT_CSC_C11_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14_A[] = {
+	 { "INPUT_CSC_C13_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22_A[] = {
+	 { "INPUT_CSC_C21_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24_A[] = {
+	 { "INPUT_CSC_C23_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32_A[] = {
+	 { "INPUT_CSC_C31_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34_A[] = {
+	 { "INPUT_CSC_C33_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12_B[] = {
+	 { "INPUT_CSC_C11_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14_B[] = {
+	 { "INPUT_CSC_C13_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22_B[] = {
+	 { "INPUT_CSC_C21_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24_B[] = {
+	 { "INPUT_CSC_C23_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_TIMER[] = {
+	 { "XDMA_SLV_READ_LATENCY_TIMER", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32_B[] = {
+	 { "INPUT_CSC_C31_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34_B[] = {
+	 { "INPUT_CSC_C33_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_CONTROL[] = {
+	 { "PRESCALE_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_R[] = {
+	 { "PRESCALE_BIAS_R", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_G[] = {
+	 { "PRESCALE_BIAS_G", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_B[] = {
+	 { "PRESCALE_BIAS_B", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_OUTPUT_CSC_CONTROL[] = {
+	 { "OUTPUT_CSC_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12_A[] = {
+	 { "OUTPUT_CSC_C11_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14_A[] = {
+	 { "OUTPUT_CSC_C13_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22_A[] = {
+	 { "OUTPUT_CSC_C21_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24_A[] = {
+	 { "OUTPUT_CSC_C23_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32_A[] = {
+	 { "OUTPUT_CSC_C31_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34_A[] = {
+	 { "OUTPUT_CSC_C33_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12_B[] = {
+	 { "OUTPUT_CSC_C11_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14_B[] = {
+	 { "OUTPUT_CSC_C13_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22_B[] = {
+	 { "OUTPUT_CSC_C21_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_FLIP_PENDING[] = {
+	 { "XDMA_SLV_FLIP_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24_B[] = {
+	 { "OUTPUT_CSC_C23_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32_B[] = {
+	 { "OUTPUT_CSC_C31_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34_B[] = {
+	 { "OUTPUT_CSC_C33_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_CONTROL[] = {
+	 { "DENORM_FACTOR", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_R_CR[] = {
+	 { "RANGE_CLAMP_MAX_R_CR", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_R_CR", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_G_Y[] = {
+	 { "RANGE_CLAMP_MAX_G_Y", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_G_Y", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_B_CB[] = {
+	 { "RANGE_CLAMP_MAX_B_CB", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_B_CB", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_FP_CONVERTED_FIELD[] = {
+	 { "COL_MAN_FP_CONVERTED_FIELD_DATA", 0, 17, &umr_bitfield_default },
+	 { "COL_MAN_FP_CONVERTED_FIELD_INDEX", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CONTROL[] = {
+	 { "GAMMA_CORR_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_INDEX[] = {
+	 { "GAMMA_CORR_LUT_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_DATA[] = {
+	 { "GAMMA_CORR_LUT_DATA", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_WRITE_EN_MASK[] = {
+	 { "GAMMA_CORR_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_START_CNTL[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_SLOPE_CNTL[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_END_CNTL1[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_END_CNTL2[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_0_1[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_2_3[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_4_5[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_6_7[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_8_9[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_10_11[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_12_13[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_14_15[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_START_CNTL[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_SLOPE_CNTL[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_END_CNTL1[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_END_CNTL2[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_0_1[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_2_3[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_4_5[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_6_7[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_8_9[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_10_11[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_12_13[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_14_15[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_TEST_DEBUG_INDEX[] = {
+	 { "COL_MAN_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "COL_MAN_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_TEST_DEBUG_DATA[] = {
+	 { "COL_MAN_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_DEBUG_CONTROL[] = {
+	 { "COL_MAN_GLOBAL_PASSTHROUGH_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_CLOCK_CONTROL[] = {
+	 { "DISPCLK_R_DCFEV_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "DISPCLK_G_UNP_GATE_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_SCLV_GATE_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_COL_MAN_GATE_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "DISPCLK_G_PSCLV_GATE_DISABLE", 13, 13, &umr_bitfield_default },
+	 { "DISPCLK_G_CRTC_GATE_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DCFEV_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DCFEV_CLOCK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_SOFT_RESET[] = {
+	 { "UNP_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "UNP_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCLV_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCLV_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "PSCLV_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "COL_MAN_SOFT_RESET", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_CLOCK_CONTROL[] = {
+	 { "DMIFV_SCLK_G_DMIFTRK_GATE_DIS", 3, 3, &umr_bitfield_default },
+	 { "DMIFV_DISPCLK_G_DMIFVL_GATE_DIS", 4, 4, &umr_bitfield_default },
+	 { "DMIFV_DISPCLK_G_DMIFVC_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIFV_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DMIFV_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DMIFV_BUFFER_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DBG_CONFIG[] = {
+	 { "DCFEV_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_DBG_SEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_MEM_PWR_CTRL[] = {
+	 { "DMIFV_MEM_PWR_SEL", 0, 1, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_0_FORCE", 2, 2, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_1_FORCE", 3, 3, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_2_FORCE", 4, 4, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_3_FORCE", 5, 5, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_4_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_0_FORCE", 7, 7, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_1_FORCE", 8, 8, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_2_FORCE", 9, 9, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_3_FORCE", 10, 10, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_4_FORCE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_MEM_PWR_STATUS[] = {
+	 { "DMIFV_MEM_PWR_LUMA_0_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_1_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_2_STATE", 4, 5, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_3_STATE", 6, 7, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_4_STATE", 8, 9, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_0_STATE", 10, 11, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_1_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_2_STATE", 14, 15, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_3_STATE", 16, 17, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_4_STATE", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CHANNEL_CNTL[] = {
+	 { "XDMA_SLV_CHANNEL_WEIGHT", 0, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_STOP_TRANSFER", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_CHANNEL_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_CHANNEL_ACTIVE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICA[] = {
+	 { "GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICA_SEL", 7, 11, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_REFDIV_CLK_SEL", 12, 14, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_SEL", 16, 18, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 22, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICB[] = {
+	 { "GENERICB_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICB_SEL", 8, 11, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_REFDIV_CLK_SEL", 12, 14, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_SEL", 16, 18, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 22, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PAD_EXTERN_SIG[] = {
+	 { "DC_PAD_EXTERN_SIG_SEL", 0, 3, &umr_bitfield_default },
+	 { "MVP_PIXEL_SRC_STATUS", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_REF_CLK_CNTL[] = {
+	 { "HSYNCA_OUTPUT_SEL", 0, 1, &umr_bitfield_default },
+	 { "GENLK_CLK_OUTPUT_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DEBUG[] = {
+	 { "DC_GPIO_VIP_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_MACRO_DEBUG", 8, 9, &umr_bitfield_default },
+	 { "DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DEBUG_BUS_FLOP_EN", 17, 17, &umr_bitfield_default },
+	 { "DPRX_LOOPBACK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYA_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYA_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYB_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYB_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYC_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYC_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYD_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYD_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYE_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYE_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYF_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYF_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYG_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYG_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_WRCMD_DELAY[] = {
+	 { "UNIPHY_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DAC_DELAY", 4, 7, &umr_bitfield_default },
+	 { "DPHY_DELAY", 8, 11, &umr_bitfield_default },
+	 { "DCRXPHY_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PINSTRAPS[] = {
+	 { "DC_PINSTRAPS_BIF_CEC_DIS", 10, 10, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_SMS_EN_HARD", 13, 13, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_AUDIO", 14, 15, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_CCBYPASS", 16, 16, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_CONNECTIVITY", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DVODATA_CONFIG[] = {
+	 { "VIP_MUX_EN", 19, 19, &umr_bitfield_default },
+	 { "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default },
+	 { "DVO_ALTER_MAPPING_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_CNTL[] = {
+	 { "LVTMA_PWRSEQ_EN", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_TARGET_STATE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN", 8, 8, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_OVRD", 9, 9, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_POL", 10, 10, &umr_bitfield_default },
+	 { "LVTMA_DIGON", 16, 16, &umr_bitfield_default },
+	 { "LVTMA_DIGON_OVRD", 17, 17, &umr_bitfield_default },
+	 { "LVTMA_DIGON_POL", 18, 18, &umr_bitfield_default },
+	 { "LVTMA_BLON", 24, 24, &umr_bitfield_default },
+	 { "LVTMA_BLON_OVRD", 25, 25, &umr_bitfield_default },
+	 { "LVTMA_BLON_POL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_STATE[] = {
+	 { "LVTMA_PWRSEQ_TARGET_STATE_R", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DIGON", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_SYNCEN", 2, 2, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_BLON", 3, 3, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DONE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_STATE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_REF_DIV[] = {
+	 { "LVTMA_PWRSEQ_REF_DIV", 0, 11, &umr_bitfield_default },
+	 { "BL_PWM_REF_DIV", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY1[] = {
+	 { "LVTMA_PWRUP_DELAY1", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY2", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY1", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY2[] = {
+	 { "LVTMA_PWRDN_MIN_LENGTH", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY3", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY3", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_VARY_BL_OVERRIDE_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL[] = {
+	 { "BL_ACTIVE_INT_FRAC_CNT", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_FRACTIONAL_EN", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL2[] = {
+	 { "BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE", 0, 15, &umr_bitfield_default },
+	 { "DBG_BL_PWM_INPUT_REFCLK_SELECT", 28, 29, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_BL_OUT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_PERIOD_CNTL[] = {
+	 { "BL_PWM_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_PERIOD_BITCNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_GRP1_REG_LOCK[] = {
+	 { "BL_PWM_GRP1_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_GENLK_PAD_CNTL[] = {
+	 { "DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_SWAPLOCK_PAD_CNTL[] = {
+	 { "DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL0_CNTL[] = {
+	 { "DCIO_GSL0_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL0_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL0_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL1_CNTL[] = {
+	 { "DCIO_GSL1_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL1_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL1_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL2_CNTL[] = {
+	 { "DCIO_GSL2_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL2_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL2_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_P_FLIP[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_P_FLIP", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_P_FLIP", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_P_FLIP", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_P_FLIP", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_P_FLIP", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_P_FLIP", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ[] = {
+	 { "DC_GPU_TIMER_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ_CNTL[] = {
+	 { "DC_GPU_TIMER_READ_SELECT", 0, 5, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM", 11, 13, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM", 14, 16, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM", 17, 19, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM", 20, 22, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_CLOCK_CNTL[] = {
+	 { "DCIO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCIO_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_R_DCIO_RAMP_DIS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DEBUG[] = {
+	 { "DCIO_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_DCFE_EXT_VSYNC_CNTL[] = {
+	 { "DCO_DCFE0_EXT_VSYNC_MUX", 0, 2, &umr_bitfield_default },
+	 { "DCO_DCFE1_EXT_VSYNC_MUX", 4, 6, &umr_bitfield_default },
+	 { "DCO_DCFE2_EXT_VSYNC_MUX", 8, 10, &umr_bitfield_default },
+	 { "DCO_DCFE3_EXT_VSYNC_MUX", 12, 14, &umr_bitfield_default },
+	 { "DCO_DCFE4_EXT_VSYNC_MUX", 16, 18, &umr_bitfield_default },
+	 { "DCO_DCFE5_EXT_VSYNC_MUX", 20, 22, &umr_bitfield_default },
+	 { "DCO_SWAPLOCKB_EXT_VSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DCO_GENERICB_EXT_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+	 { "DCO_CRTC_MANUAL_FLOW_CONTROL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_INDEX[] = {
+	 { "DCIO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCIO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_DATA[] = {
+	 { "DCIO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDBG_OUT_CNTL[] = {
+	 { "DBG_OUT_PIN_EN", 0, 0, &umr_bitfield_default },
+	 { "DBG_OUT_PIN_SEL", 4, 4, &umr_bitfield_default },
+	 { "DBG_OUT_12BIT_SEL", 8, 9, &umr_bitfield_default },
+	 { "DBG_OUT_TEST_DATA", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DEBUG_CONFIG[] = {
+	 { "DCIO_DBG_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SOFT_RESET[] = {
+	 { "UNIPHYA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DSYNCA_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHYB_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "DSYNCB_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "UNIPHYC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DSYNCC_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "UNIPHYD_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DSYNCD_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "UNIPHYE_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DSYNCE_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "UNIPHYF_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "DSYNCF_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "UNIPHYG_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DSYNCG_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DACA_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "DCRXPHY_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "DPHY_SOFT_RESET", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DPHY_SEL[] = {
+	 { "DPHY_LANE0_SEL", 0, 1, &umr_bitfield_default },
+	 { "DPHY_LANE1_SEL", 2, 3, &umr_bitfield_default },
+	 { "DPHY_LANE2_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_LANE3_SEL", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKA[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKA", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKA", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKA", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKA", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKA", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKA", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKB[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKB", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKB", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKB", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKB", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKB", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PERIOD[] = {
+	 { "UNIPHY_IMPCAL_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXP_IMPCAL[] = {
+	 { "AUXP_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXN_IMPCAL[] = {
+	 { "AUXN_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+	 { "AUX_IMPCAL_INTERVAL", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_AB[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKA", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKB", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKC[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKC", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKC", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKC", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKC", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKC", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKC", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKD[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKD", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKD", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKD", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKD", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKD", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKD", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_CD[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_CD[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKC", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKD", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKE[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKE", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKE", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKE", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKE", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKE", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKF[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKF", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKF", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKF", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKF", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKF", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKF", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_EF[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_EF[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKE", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKF", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_MASK[] = {
+	 { "DC_GPIO_GENERICA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_PD_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_MASK", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_PD_DIS", 13, 13, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_RECV", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_A[] = {
+	 { "DC_GPIO_GENERICA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_A", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_A", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_A", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_A", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_EN[] = {
+	 { "DC_GPIO_GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_Y[] = {
+	 { "DC_GPIO_GENERICA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_Y", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_Y", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_Y", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_Y", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_MASK[] = {
+	 { "DC_GPIO_DVODATA_MASK", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_MASK", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_MASK", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_MASK", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_A[] = {
+	 { "DC_GPIO_DVODATA_A", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_A", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_A", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_A", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_EN[] = {
+	 { "DC_GPIO_DVODATA_EN", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_EN", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_EN", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_EN", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_Y[] = {
+	 { "DC_GPIO_DVODATA_Y", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_Y", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_Y", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_Y", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_MASK[] = {
+	 { "DC_GPIO_DDC1CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD1_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX1_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC1_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_A[] = {
+	 { "DC_GPIO_DDC1CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_EN[] = {
+	 { "DC_GPIO_DDC1CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_Y[] = {
+	 { "DC_GPIO_DDC1CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_MASK[] = {
+	 { "DC_GPIO_DDC2CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD2_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX2_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC2_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_A[] = {
+	 { "DC_GPIO_DDC2CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_EN[] = {
+	 { "DC_GPIO_DDC2CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_Y[] = {
+	 { "DC_GPIO_DDC2CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_MASK[] = {
+	 { "DC_GPIO_DDC3CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD3_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX3_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC3_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_A[] = {
+	 { "DC_GPIO_DDC3CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_EN[] = {
+	 { "DC_GPIO_DDC3CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_Y[] = {
+	 { "DC_GPIO_DDC3CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_MASK[] = {
+	 { "DC_GPIO_DDC4CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD4_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX4_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC4_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_A[] = {
+	 { "DC_GPIO_DDC4CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_EN[] = {
+	 { "DC_GPIO_DDC4CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_Y[] = {
+	 { "DC_GPIO_DDC4CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_MASK[] = {
+	 { "DC_GPIO_DDC5CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD5_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX5_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC5_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_A[] = {
+	 { "DC_GPIO_DDC5CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_EN[] = {
+	 { "DC_GPIO_DDC5CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_Y[] = {
+	 { "DC_GPIO_DDC5CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_MASK[] = {
+	 { "DC_GPIO_DDC6CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD6_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX6_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC6_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_A[] = {
+	 { "DC_GPIO_DDC6CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_EN[] = {
+	 { "DC_GPIO_DDC6CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_Y[] = {
+	 { "DC_GPIO_DDC6CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_MASK[] = {
+	 { "DC_GPIO_DDCVGACLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PADVGA_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUXVGA_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDCVGA_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_A[] = {
+	 { "DC_GPIO_DDCVGACLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_EN[] = {
+	 { "DC_GPIO_DDCVGACLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_Y[] = {
+	 { "DC_GPIO_DDCVGACLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_MASK[] = {
+	 { "DC_GPIO_HSYNCA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_CRTC_HSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_CRTC_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_A[] = {
+	 { "DC_GPIO_HSYNCA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_EN[] = {
+	 { "DC_GPIO_HSYNCA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_Y[] = {
+	 { "DC_GPIO_HSYNCA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_MASK[] = {
+	 { "DC_GPIO_GENLK_CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PU_EN", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PU_EN", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PU_EN", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PU_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_A[] = {
+	 { "DC_GPIO_GENLK_CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_A", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_EN[] = {
+	 { "DC_GPIO_GENLK_CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_Y[] = {
+	 { "DC_GPIO_GENLK_CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_Y", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_MASK[] = {
+	 { "DC_GPIO_HPD1_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_MASK", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_PD_DIS", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_RX_SEL", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_RECV", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_A[] = {
+	 { "DC_GPIO_HPD1_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_A", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_A", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_EN[] = {
+	 { "DC_GPIO_HPD1_EN", 0, 0, &umr_bitfield_default },
+	 { "HPD1_SCHMEN_PI", 1, 1, &umr_bitfield_default },
+	 { "HPD1_SLEWNCORE", 2, 2, &umr_bitfield_default },
+	 { "RX_HPD_SCHMEN_PI", 3, 3, &umr_bitfield_default },
+	 { "RX_HPD_SLEWNCORE", 4, 4, &umr_bitfield_default },
+	 { "HPD1_SEL0", 6, 6, &umr_bitfield_default },
+	 { "RX_HPD_SEL0", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_EN", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_Y[] = {
+	 { "DC_GPIO_HPD1_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_Y", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_Y", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_Y", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_MASK[] = {
+	 { "DC_GPIO_BLON_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_PD_DIS", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_RECV", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_A[] = {
+	 { "DC_GPIO_BLON_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_A", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_EN[] = {
+	 { "DC_GPIO_BLON_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VARY_BL_GENERICA_EN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_Y[] = {
+	 { "DC_GPIO_BLON_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_1[] = {
+	 { "GENLK_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GENLK_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "RX_HPD_STRENGTH_SN", 8, 11, &umr_bitfield_default },
+	 { "RX_HPD_STRENGTH_SP", 12, 15, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SN", 24, 27, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SP", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_2[] = {
+	 { "STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "EXT_RESET_DRVSTRENGTH", 8, 10, &umr_bitfield_default },
+	 { "REF_27_DRVSTRENGTH", 12, 14, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SN", 16, 19, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SP", 20, 23, &umr_bitfield_default },
+	 { "REF_27_SRC_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHY_AUX_CNTL[] = {
+	 { "AUXSLAVE_PAD_SLEWN", 0, 0, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_WAKE", 1, 1, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_RXSEL", 2, 2, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_MODE", 3, 3, &umr_bitfield_default },
+	 { "DDCSLAVE_DATA_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DDCSLAVE_DATA_EN", 5, 5, &umr_bitfield_default },
+	 { "DDCSLAVE_CLK_PD_EN", 6, 6, &umr_bitfield_default },
+	 { "DDCSLAVE_CLK_EN", 7, 7, &umr_bitfield_default },
+	 { "AUX_PAD_SLEWN", 12, 12, &umr_bitfield_default },
+	 { "AUXSLAVE_CLK_PD_EN", 13, 13, &umr_bitfield_default },
+	 { "AUX_PAD_WAKE", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD_RXSEL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_A[] = {
+	 { "DC_GPIO_SCL_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_A", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_EN[] = {
+	 { "DC_GPIO_SCL_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_Y[] = {
+	 { "DC_GPIO_SCL_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_Y", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_STRENGTH[] = {
+	 { "I2C_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "I2C_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_STRENGTH_CONTROL[] = {
+	 { "DVO_SP", 0, 3, &umr_bitfield_default },
+	 { "DVO_SN", 4, 7, &umr_bitfield_default },
+	 { "DVOCLK_SP", 8, 11, &umr_bitfield_default },
+	 { "DVOCLK_SN", 12, 15, &umr_bitfield_default },
+	 { "DVO_DRVSTRENGTH", 16, 18, &umr_bitfield_default },
+	 { "DVOCLK_DRVSTRENGTH", 20, 22, &umr_bitfield_default },
+	 { "FLDO_VITNE_DRVSTRENGTH", 24, 26, &umr_bitfield_default },
+	 { "DVO_LSB_VMODE", 28, 28, &umr_bitfield_default },
+	 { "DVO_MSB_VMODE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_VREF_CONTROL[] = {
+	 { "DVO_VREFPON", 0, 0, &umr_bitfield_default },
+	 { "DVO_VREFSEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_VREFCAL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SKEW_ADJUST[] = {
+	 { "DVO_SKEW_ADJUST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED0[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED1[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_MACRO_CNTL[] = {
+	 { "BPHYC_DAC_WHITE_LEVEL", 0, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_WHITE_FINE_CONTROL", 8, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_BANDGAP_ADJUSTMENT", 16, 21, &umr_bitfield_default },
+	 { "BPHYC_DAC_ANALOG_MONITOR", 24, 27, &umr_bitfield_default },
+	 { "BPHYC_DAC_COREMON", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_AUTO_CALIB_CONTROL[] = {
+	 { "BPHYC_DAC_CAL_INITB", 0, 0, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_EN", 1, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_DACADJ_EN", 2, 2, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_WAIT_ADJUST", 4, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_MASK", 20, 22, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_COMPLETE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED2[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED3[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED0[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL1[] = {
+	 { "UNIPHY_PREMPH_STR0", 0, 2, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR1", 4, 6, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR2", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR3", 12, 14, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR4", 16, 18, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS0", 20, 21, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS1", 22, 23, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS2", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS3", 26, 27, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS4", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED1[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL2[] = {
+	 { "UNIPHY_PREMPH0_PC", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH1_PC", 4, 5, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH2_PC", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH3_PC", 12, 13, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH4_PC", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_SEL", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_RT0_CPSEL", 21, 22, &umr_bitfield_default },
+	 { "UNIPHY_RT1_CPSEL", 23, 24, &umr_bitfield_default },
+	 { "UNIPHY_RT2_CPSEL", 25, 26, &umr_bitfield_default },
+	 { "UNIPHY_RT3_CPSEL", 27, 28, &umr_bitfield_default },
+	 { "UNIPHY_RT4_CPSEL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED2[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL3[] = {
+	 { "UNIPHY_PREMPH_PW_CLK", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_PW_DAT", 2, 3, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_CS_CLK", 4, 7, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_CS_DAT", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR_CLK", 12, 15, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR_DAT", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_PESEL0", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_PESEL1", 21, 21, &umr_bitfield_default },
+	 { "UNIPHY_PESEL2", 22, 22, &umr_bitfield_default },
+	 { "UNIPHY_PESEL3", 23, 23, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS_ADJ", 24, 28, &umr_bitfield_default },
+	 { "UNIPHY_LVDS_PULLDWN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED3[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL4[] = {
+	 { "UNIPHY_TX_NVS_CLK", 0, 4, &umr_bitfield_default },
+	 { "UNIPHY_TX_NVS_DAT", 5, 9, &umr_bitfield_default },
+	 { "UNIPHY_TX_PVS_CLK", 12, 16, &umr_bitfield_default },
+	 { "UNIPHY_TX_PVS_DAT", 17, 21, &umr_bitfield_default },
+	 { "UNIPHY_TX_OP_CLK", 24, 26, &umr_bitfield_default },
+	 { "UNIPHY_TX_OP_DAT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED4[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_POWER_CONTROL[] = {
+	 { "UNIPHY_BGPDN", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_RST_LOGIC", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_BIASREF_SEL", 2, 3, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ1P00", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ1P25", 12, 15, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ0P45", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED5[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_FBDIV[] = {
+	 { "UNIPHY_PLL_FBDIV_FRACTION", 2, 15, &umr_bitfield_default },
+	 { "UNIPHY_PLL_FBDIV", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED6[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_CONTROL1[] = {
+	 { "UNIPHY_PLL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PLL_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_PLL_EXT_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "UNIPHY_PLL_CLK_EN", 3, 3, &umr_bitfield_default },
+	 { "UNIPHY_PLL_CLKPH_EN", 4, 7, &umr_bitfield_default },
+	 { "UNIPHY_PLL_LF_CNTL", 8, 14, &umr_bitfield_default },
+	 { "UNIPHY_PLL_BW_CNTL", 16, 23, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_BYPCLK_SRC", 24, 24, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_BYPCLK_EN", 25, 25, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL_ADC_EN", 26, 26, &umr_bitfield_default },
+	 { "UNIPHY_VCO_MODE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED7[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_CONTROL2[] = {
+	 { "UNIPHY_PLL_DISPCLK_MODE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_DPLLSEL", 2, 3, &umr_bitfield_default },
+	 { "UNIPHY_IDCLK_SEL", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_IPCIE_REFCLK_SEL", 5, 5, &umr_bitfield_default },
+	 { "UNIPHY_IXTALIN_SEL", 6, 6, &umr_bitfield_default },
+	 { "UNIPHY_PLL_REFCLK_SRC", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_PCIEREF_CLK_EN", 11, 11, &umr_bitfield_default },
+	 { "UNIPHY_IDCLK_EN", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CLKINV", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_PLL_VTOI_BIAS_CNTL", 16, 16, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS", 19, 19, &umr_bitfield_default },
+	 { "UNIPHY_PDIVFRAC_SEL", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_PLL_REFDIV", 24, 28, &umr_bitfield_default },
+	 { "UNIPHY_PDIV_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED8[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_SS_STEP_SIZE[] = {
+	 { "UNIPHY_PLL_SS_STEP_SIZE", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED9[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_SS_CNTL[] = {
+	 { "UNIPHY_PLL_SS_STEP_NUM", 0, 11, &umr_bitfield_default },
+	 { "UNIPHY_PLL_DSMOD_EN", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_PLL_SS_EN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED10[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_DATA_SYNCHRONIZATION[] = {
+	 { "UNIPHY_DSYNSEL", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_DSYN_LEVEL", 4, 5, &umr_bitfield_default },
+	 { "UNIPHY_DSYN_ERROR", 6, 6, &umr_bitfield_default },
+	 { "UNIPHY_SOURCE_SELECT", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_DUAL_LINK_PHASE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED11[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_REG_TEST_OUTPUT[] = {
+	 { "UNIPHY_TEST_CNTL", 0, 4, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL", 5, 8, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_SSAMP_EN", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_UNLOCK_CLR", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_RESET", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_SEL", 16, 16, &umr_bitfield_default },
+	 { "UNIPHY_TEST_VCTL_EN", 17, 17, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_ERROR", 20, 24, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL_ADC", 25, 27, &umr_bitfield_default },
+	 { "OA_PLL_TEST_UNLOCK_RAW", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_PLL_INTRESET", 29, 29, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_UNLOCK_STICKY", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED12[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_ANG_BIST_CNTL[] = {
+	 { "UNIPHY_TEST_RX_EN", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_ANG_BIST_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_RX_BIAS", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_ANG_BIST_ERROR", 16, 20, &umr_bitfield_default },
+	 { "UNIPHY_PRESETB", 24, 24, &umr_bitfield_default },
+	 { "UNIPHY_BIST_EN", 25, 25, &umr_bitfield_default },
+	 { "UNIPHY_CLK_CH_EN4_DFT", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED13[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_REG_TEST_OUTPUT2[] = {
+	 { "UNIPHY_TX", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED14[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG0[] = {
+	 { "ITXA_IMPCAL_EN", 0, 0, &umr_bitfield_default },
+	 { "ICALRA_MODE", 1, 1, &umr_bitfield_default },
+	 { "ITXA_OVERRIDE_PG", 2, 10, &umr_bitfield_default },
+	 { "ITXA_OVERRIDE_NG", 11, 19, &umr_bitfield_default },
+	 { "ITXA_TPC_SEL", 20, 20, &umr_bitfield_default },
+	 { "ITXA_PCALEN", 21, 21, &umr_bitfield_default },
+	 { "ITXA_DPPC_PWN", 22, 22, &umr_bitfield_default },
+	 { "ITXA_OVERRIDE_EN", 23, 23, &umr_bitfield_default },
+	 { "ITXA_TPC_CNTL", 24, 25, &umr_bitfield_default },
+	 { "ITXA_VSCALEN", 26, 26, &umr_bitfield_default },
+	 { "ITXA_IOCNTL_TSTSEL", 27, 30, &umr_bitfield_default },
+	 { "ITXA_IMPVSCALEN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED15[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG1[] = {
+	 { "ITXA_BIAS_ICC_TST", 0, 4, &umr_bitfield_default },
+	 { "ITXA_BIAS_IPLL100_ADJ", 5, 8, &umr_bitfield_default },
+	 { "ITXA_BIAS_IPLL50_ADJ", 9, 12, &umr_bitfield_default },
+	 { "ITXA_BIAS_ICC_ADJ", 13, 16, &umr_bitfield_default },
+	 { "ITXA_BIAS_ICC_PDN", 17, 17, &umr_bitfield_default },
+	 { "ITXA_IOCNTL", 18, 27, &umr_bitfield_default },
+	 { "ITXA_BIAS_PLLREFSEL", 28, 28, &umr_bitfield_default },
+	 { "ITX_EDPSEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED16[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG2[] = {
+	 { "ITXA_IMPCALN_PDN", 0, 0, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_OFFSET_EN", 1, 1, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_OFFSET", 2, 5, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_OVERRIDE", 7, 13, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_SET", 14, 14, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_PDN", 16, 16, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_OFFSET_EN", 17, 17, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_OFFSET", 18, 21, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_OVERRIDE_EN", 22, 22, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_OVERRIDE", 23, 29, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_SET", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED17[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG3[] = {
+	 { "ITXA_IMPCALVS_PDN", 0, 0, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_OFFSET_EN", 1, 1, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_OFFSET", 2, 5, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_OVERRIDE", 7, 13, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_SET", 14, 14, &umr_bitfield_default },
+	 { "ITXA_PREM_ADJ", 15, 19, &umr_bitfield_default },
+	 { "OTXA_RES_NCAL", 20, 24, &umr_bitfield_default },
+	 { "OTXA_RES_PCAL", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED18[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG4[] = {
+	 { "RESERVED", 0, 21, &umr_bitfield_default },
+	 { "OTXA_IOCNTL_NF", 22, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED19[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG5[] = {
+	 { "OTXA0_IOFSM_TIMEOUT", 0, 0, &umr_bitfield_default },
+	 { "OTXA0_RESCAL_DONE", 1, 1, &umr_bitfield_default },
+	 { "OTXA1_IOFSM_TIMEOUT", 2, 2, &umr_bitfield_default },
+	 { "OTXA1_RESCAL_DONE", 3, 3, &umr_bitfield_default },
+	 { "OTXA2_IOFSM_TIMEOUT", 4, 4, &umr_bitfield_default },
+	 { "OTXA2_RESCAL_DONE", 5, 5, &umr_bitfield_default },
+	 { "OTXA3_IOFSM_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "OTXA3_RESCAL_DONE", 7, 7, &umr_bitfield_default },
+	 { "OTXA_IMPCALN", 8, 16, &umr_bitfield_default },
+	 { "OTXA_IMPCALN_DONE", 17, 17, &umr_bitfield_default },
+	 { "OTXA_IMPCALN_ERROR", 18, 18, &umr_bitfield_default },
+	 { "OTXA_IMPCALP", 19, 22, &umr_bitfield_default },
+	 { "OTXA_IMPCALP_DONE", 23, 23, &umr_bitfield_default },
+	 { "OTXA_IMPCALP_ERROR", 24, 24, &umr_bitfield_default },
+	 { "OTXA_IMPCALVS", 25, 29, &umr_bitfield_default },
+	 { "OTXA_IMPCALVS_DONE", 30, 30, &umr_bitfield_default },
+	 { "OTXA_IMPCALVS_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED20[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG6[] = {
+	 { "IRXA_OS_ADJ", 0, 0, &umr_bitfield_default },
+	 { "IRXA_OS_POLB", 1, 1, &umr_bitfield_default },
+	 { "IRXA_BIST_SEL", 2, 2, &umr_bitfield_default },
+	 { "IRXA_SENADJ", 3, 6, &umr_bitfield_default },
+	 { "IRXA_CPSEL", 7, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKA", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED21[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TPG_CONTROL[] = {
+	 { "UNIPHY_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHY_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHY_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED22[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TPG_SEED[] = {
+	 { "UNIPHY_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED23[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_DEBUG[] = {
+	 { "DEBUG0", 12, 21, &umr_bitfield_default },
+	 { "DEBUG1", 22, 24, &umr_bitfield_default },
+	 { "DBG_SEL", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED24[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED25[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED26[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED27[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED28[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED29[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED30[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED31[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_CNTL[] = {
+	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
+	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
+	 { "DIG_START", 10, 10, &umr_bitfield_default },
+	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
+	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
+	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_OUTPUT_CRC_CNTL[] = {
+	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
+	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_OUTPUT_CRC_RESULT[] = {
+	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_CLOCK_PATTERN[] = {
+	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_PATTERN[] = {
+	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
+	 { "LVDS_TEST_CLOCK_DATA", 2, 2, &umr_bitfield_default },
+	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
+	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
+	 { "LVDS_EYE_PATTERN", 8, 8, &umr_bitfield_default },
+	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_RANDOM_PATTERN_SEED[] = {
+	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
+	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FIFO_STATUS[] = {
+	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
+	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_DISPCLK_SWITCH_CNTL[] = {
+	 { "DIG_DISPCLK_SWITCH_POINT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_DISPCLK_SWITCH_STATUS[] = {
+	 { "DIG_DISPCLK_SWITCH_ALLOWED", 0, 0, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT", 4, 4, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_CONTROL[] = {
+	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
+	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
+	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
+	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
+	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_STATUS[] = {
+	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
+	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
+	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_AUDIO_PACKET_CONTROL[] = {
+	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
+	 { "HDMI_AUDIO_SEND_MAX_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_PACKET_CONTROL[] = {
+	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
+	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
+	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
+	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_VBI_PACKET_CONTROL[] = {
+	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
+	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_INFOFRAME_CONTROL0[] = {
+	 { "HDMI_AVI_INFO_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_AVI_INFO_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_INFOFRAME_CONTROL1[] = {
+	 { "HDMI_AVI_INFO_LINE", 0, 5, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GENERIC_PACKET_CONTROL0[] = {
+	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GC[] = {
+	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
+	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
+	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
+	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL2[] = {
+	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
+	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
+	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_0[] = {
+	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
+	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_1[] = {
+	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_2[] = {
+	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_3[] = {
+	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_4[] = {
+	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_0[] = {
+	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_1[] = {
+	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_2[] = {
+	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_3[] = {
+	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO0[] = {
+	 { "AFMT_AVI_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_S", 8, 9, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_B", 10, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_A", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Y", 13, 14, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PB1_RSVD", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_R", 16, 19, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_M", 20, 21, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_C", 22, 23, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_SC", 24, 25, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Q", 26, 27, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_EC", 28, 30, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_ITC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO1[] = {
+	 { "AFMT_AVI_INFO_VIC", 0, 6, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PB4_RSVD", 7, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PR", 8, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_CN", 12, 13, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_YQ", 14, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO2[] = {
+	 { "AFMT_AVI_INFO_BOTTOM", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_LEFT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO3[] = {
+	 { "AFMT_AVI_INFO_RIGHT", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_VERSION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO0[] = {
+	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO1[] = {
+	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_HDR[] = {
+	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_0[] = {
+	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_1[] = {
+	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_2[] = {
+	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_3[] = {
+	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_4[] = {
+	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_5[] = {
+	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_6[] = {
+	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_7[] = {
+	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GENERIC_PACKET_CONTROL1[] = {
+	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_32_0[] = {
+	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_32_1[] = {
+	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_44_0[] = {
+	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_44_1[] = {
+	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_48_0[] = {
+	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_48_1[] = {
+	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_STATUS_0[] = {
+	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_STATUS_1[] = {
+	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO0[] = {
+	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO1[] = {
+	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_0[] = {
+	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
+	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
+	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
+	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
+	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_1[] = {
+	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_CONTROL[] = {
+	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL0[] = {
+	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
+	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL1[] = {
+	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL2[] = {
+	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL3[] = {
+	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_2[] = {
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_RESULT[] = {
+	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_STATUS[] = {
+	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL[] = {
+	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
+	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
+	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
+	 { "AFMT_BLANK_TEST_DATA_ON_ENC_ENB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_VBI_PACKET_CONTROL[] = {
+	 { "AFMT_GENERIC0_UPDATE", 2, 2, &umr_bitfield_default },
+	 { "AFMT_GENERIC2_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "AFMT_GENERIC_INDEX", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_INFOFRAME_CONTROL0[] = {
+	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_SRC_CONTROL[] = {
+	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_DBG_DTO_CNTL[] = {
+	 { "AFMT_AUDIO_DTO_FS_DIV_SEL", 0, 2, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_BASE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_MULTI", 12, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_DIV", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_BE_CNTL[] = {
+	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
+	 { "DIG_RB_SWITCH_EN", 2, 2, &umr_bitfield_default },
+	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
+	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
+	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_BE_EN_CNTL[] = {
+	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CNTL[] = {
+	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CONTROL_CHAR[] = {
+	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CONTROL0_FEEDBACK[] = {
+	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
+	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_STEREOSYNC_CTL_SEL[] = {
+	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_SYNC_CHAR_PATTERN_0_1[] = {
+	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
+	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_SYNC_CHAR_PATTERN_2_3[] = {
+	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
+	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_DEBUG[] = {
+	 { "TMDS_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_DEBUG_HSYNC", 8, 8, &umr_bitfield_default },
+	 { "TMDS_DEBUG_HSYNC_EN", 9, 9, &umr_bitfield_default },
+	 { "TMDS_DEBUG_VSYNC", 16, 16, &umr_bitfield_default },
+	 { "TMDS_DEBUG_VSYNC_EN", 17, 17, &umr_bitfield_default },
+	 { "TMDS_DEBUG_DE", 24, 24, &umr_bitfield_default },
+	 { "TMDS_DEBUG_DE_EN", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL_BITS[] = {
+	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
+	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
+	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
+	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_DCBALANCER_CONTROL[] = {
+	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_SYNC_DCBAL_EN", 4, 6, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL0_1_GEN_CNTL[] = {
+	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
+	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
+	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
+	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
+	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
+	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
+	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
+	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL2_3_GEN_CNTL[] = {
+	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
+	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
+	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
+	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
+	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
+	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
+	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVDS_DATA_CNTL[] = {
+	 { "LVDS_24BIT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LVDS_24BIT_FORMAT", 4, 4, &umr_bitfield_default },
+	 { "LVDS_2ND_CHAN_DE", 8, 8, &umr_bitfield_default },
+	 { "LVDS_2ND_CHAN_VS", 9, 9, &umr_bitfield_default },
+	 { "LVDS_2ND_CHAN_HS", 10, 10, &umr_bitfield_default },
+	 { "LVDS_2ND_LINK_CNTL_BITS", 12, 14, &umr_bitfield_default },
+	 { "LVDS_FP_POL", 16, 16, &umr_bitfield_default },
+	 { "LVDS_LP_POL", 17, 17, &umr_bitfield_default },
+	 { "LVDS_DTMG_POL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_LANE_ENABLE[] = {
+	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
+	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
+	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
+	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_DEBUG_INDEX[] = {
+	 { "DIG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DIG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_DEBUG_DATA[] = {
+	 { "DIG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_TEST_DEBUG_INDEX[] = {
+	 { "DIG_FE_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DIG_FE_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_TEST_DEBUG_DATA[] = {
+	 { "DIG_FE_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_LINK_CNTL[] = {
+	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
+	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_PIXEL_FORMAT[] = {
+	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
+	 { "DP_DYN_RANGE", 8, 8, &umr_bitfield_default },
+	 { "DP_YCBCR_RANGE", 16, 16, &umr_bitfield_default },
+	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_COLORIMETRY[] = {
+	 { "DP_MSA_MISC0_OVERRIDE", 0, 7, &umr_bitfield_default },
+	 { "DP_MSA_MISC0_OVERRIDE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_CONFIG[] = {
+	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_STREAM_CNTL[] = {
+	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
+	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
+	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_STEER_FIFO[] = {
+	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
+	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
+	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_MISC[] = {
+	 { "DP_MSA_MISC1", 3, 6, &umr_bitfield_default },
+	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
+	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
+	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_TIMING[] = {
+	 { "DP_VID_TIMING_MODE", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
+	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_N[] = {
+	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_M[] = {
+	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_LINK_FRAMING_CNTL[] = {
+	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
+	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_HBR2_EYE_PATTERN[] = {
+	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_MSA_VBID[] = {
+	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
+	 { "DP_VID_MSA_TOP_FIELD_MODE", 16, 16, &umr_bitfield_default },
+	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_INTERRUPT_CNTL[] = {
+	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CNTL[] = {
+	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
+	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_TRAINING_PATTERN_SEL[] = {
+	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM0[] = {
+	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
+	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM1[] = {
+	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
+	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM2[] = {
+	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_8B10B_CNTL[] = {
+	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
+	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
+	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_PRBS_CNTL[] = {
+	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SCRAM_CNTL[] = {
+	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
+	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_EN[] = {
+	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_CNTL[] = {
+	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_RESULT[] = {
+	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_MST_CNTL[] = {
+	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_MST_STATUS[] = {
+	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_FAST_TRAINING[] = {
+	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_FAST_TRAINING_STATUS[] = {
+	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_V_TIMING_OVERRIDE1[] = {
+	 { "DP_MSA_V_TIMING_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "DP_MSA_V_TOTAL_OVERRIDE", 4, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_V_TIMING_OVERRIDE2[] = {
+	 { "DP_MSA_V_BLANK_START_OVERRIDE", 0, 13, &umr_bitfield_default },
+	 { "DP_MSA_V_BLANK_END_OVERRIDE", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_CNTL[] = {
+	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "DP_SEC_AVI_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_CNTL1[] = {
+	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING1[] = {
+	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
+	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING2[] = {
+	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
+	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING3[] = {
+	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
+	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING4[] = {
+	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
+	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
+	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_N[] = {
+	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_N_READBACK[] = {
+	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_M[] = {
+	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_M_READBACK[] = {
+	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_TIMESTAMP[] = {
+	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_PACKET_CNTL[] = {
+	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
+	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
+	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_RATE_CNTL[] = {
+	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
+	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_RATE_UPDATE[] = {
+	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT0[] = {
+	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT1[] = {
+	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT2[] = {
+	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT_UPDATE[] = {
+	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
+	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_LINK_TIMING[] = {
+	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
+	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_MISC_CNTL[] = {
+	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
+	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
+	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
+	 { "DP_MSE_OUTPUT_DPDBG_DATA", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_TEST_DEBUG_INDEX[] = {
+	 { "DP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_TEST_DEBUG_DATA[] = {
+	 { "DP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_FE_TEST_DEBUG_INDEX[] = {
+	 { "DP_FE_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DP_FE_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_FE_TEST_DEBUG_DATA[] = {
+	 { "DP_FE_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL5[] = {
+	 { "INPUT_CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL5[] = {
+	 { "CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_STREAM_DEBUG[] = {
+	 { "STREAM_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR4[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG5[] = {
+	 { "DCIO_DEBUG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR05[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT05[] = {
+	 { "H_SYNC_END", 0, 4, &umr_bitfield_default },
+	 { "H_SYNC_SKEW", 5, 6, &umr_bitfield_default },
+	 { "H_BLANK_END_B5", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
+	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
+	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
+	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
+	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
+	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
+	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED0[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED1[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED2[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED3[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED4[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED5[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED6[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED7[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED8[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED9[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED10[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED11[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED12[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED13[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED14[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED15[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED16[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED17[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED18[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED19[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED20[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED21[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED22[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED23[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED24[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED25[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED26[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED27[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED28[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED29[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED30[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED31[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED32[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED33[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED34[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED35[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED36[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED37[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED38[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED39[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED40[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED41[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED42[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED43[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED44[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED45[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED46[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED47[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED48[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED49[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED50[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED51[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED52[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED53[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED54[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED55[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED56[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED57[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED58[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED59[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED60[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED61[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED62[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED63[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED64[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED65[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED66[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED67[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED68[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED69[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED70[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED71[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED72[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED73[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED74[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED75[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED76[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED77[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED78[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED79[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED80[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED81[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED82[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED83[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED84[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED85[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED86[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED87[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED88[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED89[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED90[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED91[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED92[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED93[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED94[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED95[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED96[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED97[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED98[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED99[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED100[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED101[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED102[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED103[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED104[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED105[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED106[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED107[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED108[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED109[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED110[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED111[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED112[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED113[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED114[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED115[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED116[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED117[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED118[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED119[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED120[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED121[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED122[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED123[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED124[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED125[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED126[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED127[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED128[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED129[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED130[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED131[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED132[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED133[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED134[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED135[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED136[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED137[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED138[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED139[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED140[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED141[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED142[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED143[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED144[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED145[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED146[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED147[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED148[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED149[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED150[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED151[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED152[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED153[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED154[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED155[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED156[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED157[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED158[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED159[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED160[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED161[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED162[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED163[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED164[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED165[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED166[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED167[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED168[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED169[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED170[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED171[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED172[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED173[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED174[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED175[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED176[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED177[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED178[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED179[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED180[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED181[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED182[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED183[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED184[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED185[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED186[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED187[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED188[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED189[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED190[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED191[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED192[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED193[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED194[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED195[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED196[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED197[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED198[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED199[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED200[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED201[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED202[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED203[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED204[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED205[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED206[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED207[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED208[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED209[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED210[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED211[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED212[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED213[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED214[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED215[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED216[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED217[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED218[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED219[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED220[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED221[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED222[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED223[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED224[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED225[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED226[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED227[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED228[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED229[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED230[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED231[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED232[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED233[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED234[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED235[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED236[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED237[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED238[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED239[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED240[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED241[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED242[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED243[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED244[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED245[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED246[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED247[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED248[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED249[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED250[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED251[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED252[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED253[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED254[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED255[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED256[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED257[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED258[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED259[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED260[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED261[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED262[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED263[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED264[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED265[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED266[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED267[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED268[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED269[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED270[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED271[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED272[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED273[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED274[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED275[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED276[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED277[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED278[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED279[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED280[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED281[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED282[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED283[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED284[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED285[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED286[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED287[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED288[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED289[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED290[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED291[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED292[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED293[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED294[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED295[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED296[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED297[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED298[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED299[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED300[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED301[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED302[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED303[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED304[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED305[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED306[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED307[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED308[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED309[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED310[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED311[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED312[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED313[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED314[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED315[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED316[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED317[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED318[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED319[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED320[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED321[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED322[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED323[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED324[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED325[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED326[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED327[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED328[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED329[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED330[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED331[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED332[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED333[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED334[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED335[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED336[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED337[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED338[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED339[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED340[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED341[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED342[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED343[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED344[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED345[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED346[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED347[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED348[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED349[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED350[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED351[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED352[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED353[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED354[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED355[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED356[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED357[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED358[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED359[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED360[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED361[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED362[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED363[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED364[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED365[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED366[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED367[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED368[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED369[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED370[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED371[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED372[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED373[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED374[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED375[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED376[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED377[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED378[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED379[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_CONTROL[] = {
+	 { "AUX_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
+	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
+	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
+	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
+	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
+	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
+	 { "SPARE_0", 30, 30, &umr_bitfield_default },
+	 { "SPARE_1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_CONTROL[] = {
+	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
+	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
+	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_ARB_CONTROL[] = {
+	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
+	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_INTERRUPT_CONTROL[] = {
+	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_STATUS[] = {
+	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_STATUS[] = {
+	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_DATA[] = {
+	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
+	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_DATA[] = {
+	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_REF_CONTROL[] = {
+	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
+	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_CONTROL[] = {
+	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
+	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
+	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL0[] = {
+	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
+	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
+	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
+	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
+	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
+	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL1[] = {
+	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_STATUS[] = {
+	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_STATUS[] = {
+	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
+	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_CONTROL[] = {
+	 { "AUX_GTC_SYNC_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_IMPCAL_EN", 4, 4, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_IMPCAL_INTERVAL", 8, 11, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_PERIOD", 12, 15, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_MAINT_PERIOD", 16, 18, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_BLOCK_REQ", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_INTERVAL_RESET_WINDOW", 22, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT", 24, 25, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_ERROR_CONTROL[] = {
+	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
+	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_CONTROLLER_STATUS[] = {
+	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_STATUS[] = {
+	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
+	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_DATA[] = {
+	 { "AUX_GTC_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_GTC_INDEX", 16, 21, &umr_bitfield_default },
+	 { "AUX_GTC_INDEX_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[] = {
+	 { "AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE", 4, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_TEST_DEBUG_INDEX[] = {
+	 { "AUX_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AUX_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_TEST_DEBUG_DATA[] = {
+	 { "AUX_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED0[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED1[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED2[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED3[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED4[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED5[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED6[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED7[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED8[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED9[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED10[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED11[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED12[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED13[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED14[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED15[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED16[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED17[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED18[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED19[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED20[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED21[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED22[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED23[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED24[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED25[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED26[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED27[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED28[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED29[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED30[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED31[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED32[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED33[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED34[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED35[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED36[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED37[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED38[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED39[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED40[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED41[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED42[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED43[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED44[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED45[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED46[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED47[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED48[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED49[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED50[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED51[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED52[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED53[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED54[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED55[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED56[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED57[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED58[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED59[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED60[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED61[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED62[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED63[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_ENABLE[] = {
+	 { "WB_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_EC_CONFIG[] = {
+	 { "DISPCLK_R_WB_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_G_WB_GATE_DIS", 1, 1, &umr_bitfield_default },
+	 { "DISPCLK_G_WBSCL_GATE_DIS", 2, 2, &umr_bitfield_default },
+	 { "DISPCLK_R_WB_RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DISPCLK_G_WB_RAMP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DISPCLK_G_WBSCL_RAMP_DIS", 5, 5, &umr_bitfield_default },
+	 { "WB_LB_LS_DIS", 6, 6, &umr_bitfield_default },
+	 { "WB_LB_SD_DIS", 7, 7, &umr_bitfield_default },
+	 { "WB_LUT_LS_DIS", 8, 8, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_MODE_SEL", 9, 10, &umr_bitfield_default },
+	 { "WB_TEST_CLK_SEL", 12, 15, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_STATE", 19, 20, &umr_bitfield_default },
+	 { "WB_RAM_PW_SAVE_MODE", 23, 23, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
+	 { "LUT_MEM_PWR_STATE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_MODE[] = {
+	 { "CNV_FRAME_CAPTURE_RATE", 8, 9, &umr_bitfield_default },
+	 { "CNV_WINDOW_CROP_EN", 12, 12, &umr_bitfield_default },
+	 { "CNV_STEREO_TYPE", 13, 14, &umr_bitfield_default },
+	 { "CNV_INTERLACED_MODE", 15, 15, &umr_bitfield_default },
+	 { "CNV_EYE_SELECTION", 16, 17, &umr_bitfield_default },
+	 { "CNV_STEREO_POLARITY", 18, 18, &umr_bitfield_default },
+	 { "CNV_INTERLACED_FIELD_ORDER", 19, 19, &umr_bitfield_default },
+	 { "CNV_STEREO_SPLIT", 20, 20, &umr_bitfield_default },
+	 { "CNV_NEW_CONTENT", 24, 24, &umr_bitfield_default },
+	 { "CNV_FRAME_CAPTURE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_WINDOW_START[] = {
+	 { "CNV_WINDOW_START_X", 0, 11, &umr_bitfield_default },
+	 { "CNV_WINDOW_START_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_WINDOW_SIZE[] = {
+	 { "CNV_WINDOW_WIDTH", 0, 11, &umr_bitfield_default },
+	 { "CNV_WINDOW_HEIGHT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_UPDATE[] = {
+	 { "CNV_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CNV_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "CNV_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_SOURCE_SIZE[] = {
+	 { "CNV_SOURCE_WIDTH", 0, 14, &umr_bitfield_default },
+	 { "CNV_SOURCE_HEIGHT", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CONTROL[] = {
+	 { "CNV_CSC_BYPASS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C11_C12[] = {
+	 { "CNV_CSC_C11", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C12", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C13_C14[] = {
+	 { "CNV_CSC_C13", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C14", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C21_C22[] = {
+	 { "CNV_CSC_C21", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C22", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C23_C24[] = {
+	 { "CNV_CSC_C23", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C24", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C31_C32[] = {
+	 { "CNV_CSC_C31", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C32", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C33_C34[] = {
+	 { "CNV_CSC_C33", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C34", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_R[] = {
+	 { "CNV_CSC_ROUND_OFFSET_R", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_G[] = {
+	 { "CNV_CSC_ROUND_OFFSET_G", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_B[] = {
+	 { "CNV_CSC_ROUND_OFFSET_B", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_R[] = {
+	 { "CNV_CSC_CLAMP_UPPER_R", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_G[] = {
+	 { "CNV_CSC_CLAMP_UPPER_G", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_B[] = {
+	 { "CNV_CSC_CLAMP_UPPER_B", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CNTL[] = {
+	 { "CNV_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_RED[] = {
+	 { "CNV_TEST_CRC_RED_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_GREEN[] = {
+	 { "CNV_TEST_CRC_GREEN_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_BLUE[] = {
+	 { "CNV_TEST_CRC_BLUE_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_DEBUG_CTRL[] = {
+	 { "WB_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_DEBUG_SEL", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_DBG_MODE[] = {
+	 { "WB_DBG_MODE_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_DBG_DIN_FMT", 1, 1, &umr_bitfield_default },
+	 { "WB_DBG_36MODE", 2, 2, &umr_bitfield_default },
+	 { "WB_DBG_CMAP", 3, 3, &umr_bitfield_default },
+	 { "WB_DBG_PXLRATE_ERROR", 8, 8, &umr_bitfield_default },
+	 { "WB_DBG_SOURCE_WIDTH", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_HW_DEBUG[] = {
+	 { "WB_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_INPUT_SELECT[] = {
+	 { "CNV_INPUT_SRC_SELECT", 0, 1, &umr_bitfield_default },
+	 { "CNV_INPUT_PIPE_SELECT", 2, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_DEBUG_INDEX[] = {
+	 { "CNV_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CNV_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_DEBUG_DATA[] = {
+	 { "CNV_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_SOFT_RESET[] = {
+	 { "WB_SOFT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED0[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED1[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED2[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED3[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED4[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED5[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED6[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED7[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED8[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED9[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED10[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED11[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[] = {
+	 { "OUTSTRMPAY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_STREAM_PAYLOAD_CAPABILITY[] = {
+	 { "INSTRMPAY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL6[] = {
+	 { "INPUT_CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL6[] = {
+	 { "CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR5[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG6[] = {
+	 { "DCIO_DEBUG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR06[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT06[] = {
+	 { "V_TOTAL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
+	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
+	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
+	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
+	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
+	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
+	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
+	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
+	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
+	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
+	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
+	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_ENABLE_STATUS[] = {
+	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
+	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
+	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
+	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL7[] = {
+	 { "INPUT_CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL7[] = {
+	 { "CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR6[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMDS_DEBUG10[] = {
+	 { "DBG_DIG_TMDS10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG7[] = {
+	 { "DCIO_DEBUG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR07[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT07[] = {
+	 { "V_TOTAL_B8", 0, 0, &umr_bitfield_default },
+	 { "V_DISP_END_B8", 1, 1, &umr_bitfield_default },
+	 { "V_SYNC_START_B8", 2, 2, &umr_bitfield_default },
+	 { "V_BLANK_START_B8", 3, 3, &umr_bitfield_default },
+	 { "LINE_CMP_B8", 4, 4, &umr_bitfield_default },
+	 { "V_TOTAL_B9", 5, 5, &umr_bitfield_default },
+	 { "V_DISP_END_B9", 6, 6, &umr_bitfield_default },
+	 { "V_SYNC_START_B9", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
+	 { "MISC", 0, 3, &umr_bitfield_default },
+	 { "COLOR", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
+	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
+	 { "LOCATION", 0, 5, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[] = {
+	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[] = {
+	 { "MULTICHANNEL2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL2_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL2_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[] = {
+	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[] = {
+	 { "MULTICHANNEL6_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL6_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL6_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
+	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
+	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
+	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
+	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
+	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
+	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
+	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
+	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[] = {
+	 { "CHANNEL_STATUS_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[] = {
+	 { "CHANNEL_STATUS_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGADCC_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CONTROL[] = {
+	 { "STREAM_0_INTERRUPT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_INTERRUPT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_INTERRUPT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_INTERRUPT_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_INTERRUPT_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_INTERRUPT_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_INTERRUPT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_INTERRUPT_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_INTERRUPT_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_INTERRUPT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_INTERRUPT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_INTERRUPT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_INTERRUPT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_INTERRUPT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "CONTROLLER_INTERRUPT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GLOBAL_INTERRUPT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMDS_DEBUG11[] = {
+	 { "DBG_DIG_TMDS11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG8[] = {
+	 { "DCIO_DEBUG8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR08[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT08[] = {
+	 { "ROW_SCAN_START", 0, 4, &umr_bitfield_default },
+	 { "BYTE_PAN", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWALL_CLOCK_COUNTER_ALIAS[] = {
+	 { "WALL_CLOCK_COUNTER_ALIAS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
+	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
+	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF02_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR8[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_STATUS[] = {
+	 { "STREAM_0_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_INTERRUPT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_INTERRUPT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_INTERRUPT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_INTERRUPT_STATUS", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_INTERRUPT_STATUS", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_INTERRUPT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_INTERRUPT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_INTERRUPT_STATUS", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_INTERRUPT_STATUS", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_INTERRUPT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_INTERRUPT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_INTERRUPT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_INTERRUPT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "CONTROLLER_INTERRUPT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GLOBAL_INTERRUPT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMDS_DEBUG12[] = {
+	 { "DBG_LVDS_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG9[] = {
+	 { "DCIO_DEBUG9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR09[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT09[] = {
+	 { "MAX_ROW_SCAN", 0, 4, &umr_bitfield_default },
+	 { "V_BLANK_START_B9", 5, 5, &umr_bitfield_default },
+	 { "LINE_CMP_B9", 6, 6, &umr_bitfield_default },
+	 { "DOUBLE_CHAR_HEIGHT", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[] = {
+	 { "PRESENTATION_TIME_OFFSET_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMIF_DEBUG02_CORE1[] = {
+	 { "DB_DATA", 0, 15, &umr_bitfield_default },
+	 { "MC_RDRET_COUNT_EN", 16, 16, &umr_bitfield_default },
+	 { "MC_RDRET_COUNTER", 17, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR9[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMDS_DEBUG13[] = {
+	 { "DBG_LVDS_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGA[] = {
+	 { "DCIO_DEBUGA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0A[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0A[] = {
+	 { "CURSOR_START", 0, 4, &umr_bitfield_default },
+	 { "CURSOR_DISABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF04_DBG_DCCIF_E[] = {
+	 { "DBG_DCCIF_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR10[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION6[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGB[] = {
+	 { "DCIO_DEBUGB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0B[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0B[] = {
+	 { "CURSOR_END", 0, 4, &umr_bitfield_default },
+	 { "CURSOR_SKEW", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
+	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF05_DBG_DCCIF_F[] = {
+	 { "DBG_DCCIF_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWALL_CLOCK_COUNTER[] = {
+	 { "WALL_CLOCK_COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION7[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_12[] = {
+	 { "IDEC_MVP_DATA_A_H", 0, 0, &umr_bitfield_default },
+	 { "IDEC_MVP_DATA_A", 1, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGC[] = {
+	 { "DCIO_DEBUGC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0C[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0C[] = {
+	 { "DISP_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_RENDER_CONTROL[] = {
+	 { "VGA_BLINK_RATE", 0, 4, &umr_bitfield_default },
+	 { "VGA_BLINK_MODE", 5, 6, &umr_bitfield_default },
+	 { "VGA_CURSOR_BLINK_INVERT", 7, 7, &umr_bitfield_default },
+	 { "VGA_EXTD_ADDR_COUNT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_VSTATUS_CNTL", 16, 17, &umr_bitfield_default },
+	 { "VGA_LOCK_8DOT", 24, 24, &umr_bitfield_default },
+	 { "VGAREG_LINECMP_COMPATIBILITY_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SEQUENCER_RESET_CONTROL[] = {
+	 { "D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 0, 0, &umr_bitfield_default },
+	 { "D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 1, 1, &umr_bitfield_default },
+	 { "D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 2, 2, &umr_bitfield_default },
+	 { "D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 3, 3, &umr_bitfield_default },
+	 { "D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 4, 4, &umr_bitfield_default },
+	 { "D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 5, 5, &umr_bitfield_default },
+	 { "D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 8, 8, &umr_bitfield_default },
+	 { "D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 9, 9, &umr_bitfield_default },
+	 { "D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 10, 10, &umr_bitfield_default },
+	 { "D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 11, 11, &umr_bitfield_default },
+	 { "D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 12, 12, &umr_bitfield_default },
+	 { "D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 13, 13, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT", 17, 17, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INDEX_SELECT", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MODE_CONTROL[] = {
+	 { "VGA_ATI_LINEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_LUT_PALETTE_UPDATE_MODE", 4, 5, &umr_bitfield_default },
+	 { "VGA_128K_APERTURE_PAGING", 8, 8, &umr_bitfield_default },
+	 { "VGA_TEXT_132_COLUMNS_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SURFACE_PITCH_SELECT[] = {
+	 { "VGA_SURFACE_PITCH_SELECT", 0, 1, &umr_bitfield_default },
+	 { "VGA_SURFACE_HEIGHT_SELECT", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_INDEX[] = {
+	 { "VGA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "VGA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF1_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF1_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_DATA[] = {
+	 { "VGA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF2_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF2_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS_HIGH[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HDP_CONTROL[] = {
+	 { "VGA_MEM_PAGE_SELECT_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_MEMORY_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "VGA_RBBM_LOCK_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RESET_CONTROL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_CACHE_CONTROL[] = {
+	 { "VGA_WRITE_THROUGH_CACHE_DIS", 0, 0, &umr_bitfield_default },
+	 { "VGA_READ_CACHE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_READ_BUFFER_INVALIDATE", 16, 16, &umr_bitfield_default },
+	 { "VGA_DCCIF_W256ONLY", 20, 20, &umr_bitfield_default },
+	 { "VGA_DCCIF_WC_TIMEOUT", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD1VGA_CONTROL[] = {
+	 { "D1VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D1VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D1VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D1VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D1VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD2VGA_CONTROL[] = {
+	 { "D2VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D2VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D2VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D2VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D2VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HW_DEBUG[] = {
+	 { "VGA_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
+	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR12[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION8[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_13[] = {
+	 { "IDED_MVP_DATA_B_H", 0, 0, &umr_bitfield_default },
+	 { "IDED_MVP_DATA_B", 1, 24, &umr_bitfield_default },
+	 { "IDED_START_READ_B", 25, 25, &umr_bitfield_default },
+	 { "IDED_READ_FIFO_ENTRY_DE_B", 26, 26, &umr_bitfield_default },
+	 { "IDED_WRITE_ADD_B", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGD[] = {
+	 { "DCIO_DEBUGD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0D[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0D[] = {
+	 { "DISP_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS[] = {
+	 { "VGA_MEM_ACCESS_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_STATUS", 1, 1, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_CONTROL[] = {
+	 { "VGA_MEM_ACCESS_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_MASK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS_CLEAR[] = {
+	 { "VGA_MEM_ACCESS_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_STATUS[] = {
+	 { "VGA_MEM_ACCESS_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MAIN_CONTROL[] = {
+	 { "VGA_CRTC_TIMEOUT", 0, 1, &umr_bitfield_default },
+	 { "VGA_RENDER_TIMEOUT_COUNT", 3, 4, &umr_bitfield_default },
+	 { "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION", 5, 7, &umr_bitfield_default },
+	 { "VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT", 8, 9, &umr_bitfield_default },
+	 { "VGA_MC_WRITE_CLEAN_WAIT_DELAY", 12, 15, &umr_bitfield_default },
+	 { "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT", 16, 17, &umr_bitfield_default },
+	 { "VGA_READBACK_CRT_INTR_SOURCE_SELECT", 24, 25, &umr_bitfield_default },
+	 { "VGA_READBACK_SENSE_SWITCH_SELECT", 26, 26, &umr_bitfield_default },
+	 { "VGA_READ_URGENT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "VGA_WRITES_URGENT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "VGA_EXTERNAL_DAC_SENSE", 29, 29, &umr_bitfield_default },
+	 { "VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_CONTROL[] = {
+	 { "VGA_TEST_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_START", 8, 8, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DONE", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DISPBUF_SELECT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_INDEX[] = {
+	 { "VGA_DEBUG_READBACK_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_DATA[] = {
+	 { "VGA_DEBUG_READBACK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
+	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTREAM_SYNCHRONIZATION[] = {
+	 { "STREAM_0_SYNCHRONIZATION", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_SYNCHRONIZATION", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_SYNCHRONIZATION", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_SYNCHRONIZATION", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_SYNCHRONIZATION", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_SYNCHRONIZATION", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_SYNCHRONIZATION", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_SYNCHRONIZATION", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_SYNCHRONIZATION", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_SYNCHRONIZATION", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_SYNCHRONIZATION", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_SYNCHRONIZATION", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_SYNCHRONIZATION", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_SYNCHRONIZATION", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_SYNCHRONIZATION", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_SYNCHRONIZATION", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR13[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION9[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_14[] = {
+	 { "IDEE_READ_ADD", 0, 2, &umr_bitfield_default },
+	 { "IDEE_WRITE_ADD_A", 3, 5, &umr_bitfield_default },
+	 { "IDEE_WRITE_ADD_B", 6, 8, &umr_bitfield_default },
+	 { "IDEE_START_READ", 9, 9, &umr_bitfield_default },
+	 { "IDEE_START_READ_B", 10, 10, &umr_bitfield_default },
+	 { "IDEE_START_INCR_WR_A", 11, 11, &umr_bitfield_default },
+	 { "IDEE_START_INCR_WR_B", 12, 12, &umr_bitfield_default },
+	 { "IDEE_WRITE2FIFO", 13, 13, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENTRY_DE", 14, 14, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENTRY_DE_B", 15, 15, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_DE", 16, 16, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_DE_B", 17, 17, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "IDEE_CRTC1_CNTL_CAPTURE_START_A", 19, 19, &umr_bitfield_default },
+	 { "IDEE_CRC_PHASE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGE[] = {
+	 { "DCIO_DIGA_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0E[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0E[] = {
+	 { "CURSOR_LOC_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_DATA[] = {
+	 { "VCRTC_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_IDX[] = {
+	 { "VCRTC_IDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_WT[] = {
+	 { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENS1[] = {
+	 { "NO_DISPLAY", 0, 0, &umr_bitfield_default },
+	 { "VGA_VSTATUS", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_READ_BACK", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION10[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_15[] = {
+	 { "IDEF_MVP_ASYNC_FIFO_WEN", 0, 0, &umr_bitfield_default },
+	 { "IDEF_MVP_ASYNC_FIFO_WDATA", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGF[] = {
+	 { "DCIO_DIGB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0F[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0F[] = {
+	 { "CURSOR_LOC_LO", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_WT[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENENB[] = {
+	 { "BLK_IO_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENS0[] = {
+	 { "SENSE_SWITCH", 4, 4, &umr_bitfield_default },
+	 { "CRT_INTR", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_R_INDEX[] = {
+	 { "DAC_R_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEQ8_DATA[] = {
+	 { "SEQ_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MASK[] = {
+	 { "DAC_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_W_INDEX[] = {
+	 { "DAC_W_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_RD[] = {
+	 { "VSYNC_SEL_R", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH8_DATA[] = {
+	 { "GRPH_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH8_IDX[] = {
+	 { "GRPH_IDX", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_RD[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD3VGA_CONTROL[] = {
+	 { "D3VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D3VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D3VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D3VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D3VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD4VGA_CONTROL[] = {
+	 { "D4VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D4VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D4VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D4VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D4VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD5VGA_CONTROL[] = {
+	 { "D5VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D5VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D5VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D5VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D5VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD6VGA_CONTROL[] = {
+	 { "D6VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D6VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D6VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D6VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D6VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SOURCE_SELECT[] = {
+	 { "VGA_SOURCE_SEL_A", 0, 2, &umr_bitfield_default },
+	 { "VGA_SOURCE_SEL_B", 8, 10, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/dce100_regs.i b/src/lib/ip/dce100_regs.i
new file mode 100644
index 0000000..f750603
--- /dev/null
+++ b/src/lib/ip/dce100_regs.i
@@ -0,0 +1,7263 @@
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID", REG_SMC, 0x0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG", REG_SMC, 0x0, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG", REG_SMC, 0x0, &ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL0", REG_SMC, 0x0, &ixAZALIA_INPUT_CRC0_CHANNEL0[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL0)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL0[0]), 0, 0 },
+	{ "ixAZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0, &ixAZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL0", REG_SMC, 0x0, &ixAZALIA_CRC0_CHANNEL0[0], sizeof(ixAZALIA_CRC0_CHANNEL0)/sizeof(ixAZALIA_CRC0_CHANNEL0[0]), 0, 0 },
+	{ "mmGLOBAL_CAPABILITIES", REG_MMIO, 0x0, &mmGLOBAL_CAPABILITIES[0], sizeof(mmGLOBAL_CAPABILITIES)/sizeof(mmGLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "ixDCIO_DEBUG_ID", REG_SMC, 0x0, &ixDCIO_DEBUG_ID[0], sizeof(ixDCIO_DEBUG_ID)/sizeof(ixDCIO_DEBUG_ID[0]), 0, 0 },
+	{ "ixFMT_DEBUG_ID", REG_SMC, 0x0, &ixFMT_DEBUG_ID[0], sizeof(ixFMT_DEBUG_ID)/sizeof(ixFMT_DEBUG_ID[0]), 0, 0 },
+	{ "ixATTR00", REG_SMC, 0x0, &ixATTR00[0], sizeof(ixATTR00)/sizeof(ixATTR00[0]), 0, 0 },
+	{ "ixSEQ00", REG_SMC, 0x0, &ixSEQ00[0], sizeof(ixSEQ00)/sizeof(ixSEQ00[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x1, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x1, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID", REG_SMC, 0x1, &ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0]), 0, 0 },
+	{ "ixAZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x1, &ixAZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL1", REG_SMC, 0x1, &ixAZALIA_INPUT_CRC0_CHANNEL1[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL1)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL1[0]), 0, 0 },
+	{ "mmOUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x1, &mmOUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmOUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmOUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmINPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x1, &mmINPUT_PAYLOAD_CAPABILITY[0], sizeof(mmINPUT_PAYLOAD_CAPABILITY)/sizeof(mmINPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL1", REG_SMC, 0x1, &ixAZALIA_CRC0_CHANNEL1[0], sizeof(ixAZALIA_CRC0_CHANNEL1)/sizeof(ixAZALIA_CRC0_CHANNEL1[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR0", REG_SMC, 0x1, &ixAUDIO_DESCRIPTOR0[0], sizeof(ixAUDIO_DESCRIPTOR0)/sizeof(ixAUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1", REG_SMC, 0x1, &ixDCIO_DEBUG1[0], sizeof(ixDCIO_DEBUG1)/sizeof(ixDCIO_DEBUG1[0]), 0, 0 },
+	{ "ixFMT_DEBUG0", REG_SMC, 0x1, &ixFMT_DEBUG0[0], sizeof(ixFMT_DEBUG0)/sizeof(ixFMT_DEBUG0[0]), 0, 0 },
+	{ "ixATTR01", REG_SMC, 0x1, &ixATTR01[0], sizeof(ixATTR01)/sizeof(ixATTR01[0]), 0, 0 },
+	{ "ixSEQ01", REG_SMC, 0x1, &ixSEQ01[0], sizeof(ixSEQ01)/sizeof(ixSEQ01[0]), 0, 0 },
+	{ "mmCORB_LOWER_BASE_ADDRESS", REG_MMIO, 0x10, &mmCORB_LOWER_BASE_ADDRESS[0], sizeof(mmCORB_LOWER_BASE_ADDRESS)/sizeof(mmCORB_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION11", REG_SMC, 0x10, &ixSINK_DESCRIPTION11[0], sizeof(ixSINK_DESCRIPTION11)/sizeof(ixSINK_DESCRIPTION11[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_A", REG_SMC, 0x10, &ixDP_AUX_DEBUG_A[0], sizeof(ixDP_AUX_DEBUG_A)/sizeof(ixDP_AUX_DEBUG_A[0]), 0, 0 },
+	{ "ixDCIO_DEBUG10", REG_SMC, 0x10, &ixDCIO_DEBUG10[0], sizeof(ixDCIO_DEBUG10)/sizeof(ixDCIO_DEBUG10[0]), 0, 0 },
+	{ "ixATTR10", REG_SMC, 0x10, &ixATTR10[0], sizeof(ixATTR10)/sizeof(ixATTR10[0]), 0, 0 },
+	{ "ixCRT10", REG_SMC, 0x10, &ixCRT10[0], sizeof(ixCRT10)/sizeof(ixCRT10[0]), 0, 0 },
+	{ "mmDPREFCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x108, &mmDPREFCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDPREFCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDPREFCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmREFCLK_CNTL", REG_MMIO, 0x109, &mmREFCLK_CNTL[0], sizeof(mmREFCLK_CNTL)/sizeof(mmREFCLK_CNTL[0]), 0, 0 },
+	{ "mmREFCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x10b, &mmREFCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmREFCLK_CGTT_BLK_CTRL_REG)/sizeof(mmREFCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmDPDBG_CLK_FORCE_CONTROL", REG_MMIO, 0x10d, &mmDPDBG_CLK_FORCE_CONTROL[0], sizeof(mmDPDBG_CLK_FORCE_CONTROL)/sizeof(mmDPDBG_CLK_FORCE_CONTROL[0]), 0, 0 },
+	{ "mmDCCG_PERFMON_CNTL2", REG_MMIO, 0x10e, &mmDCCG_PERFMON_CNTL2[0], sizeof(mmDCCG_PERFMON_CNTL2)/sizeof(mmDCCG_PERFMON_CNTL2[0]), 0, 0 },
+	{ "mmCORB_UPPER_BASE_ADDRESS", REG_MMIO, 0x11, &mmCORB_UPPER_BASE_ADDRESS[0], sizeof(mmCORB_UPPER_BASE_ADDRESS)/sizeof(mmCORB_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION12", REG_SMC, 0x11, &ixSINK_DESCRIPTION12[0], sizeof(ixSINK_DESCRIPTION12)/sizeof(ixSINK_DESCRIPTION12[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_B", REG_SMC, 0x11, &ixDP_AUX_DEBUG_B[0], sizeof(ixDP_AUX_DEBUG_B)/sizeof(ixDP_AUX_DEBUG_B[0]), 0, 0 },
+	{ "ixDCIO_DEBUG11", REG_SMC, 0x11, &ixDCIO_DEBUG11[0], sizeof(ixDCIO_DEBUG11)/sizeof(ixDCIO_DEBUG11[0]), 0, 0 },
+	{ "ixATTR11", REG_SMC, 0x11, &ixATTR11[0], sizeof(ixATTR11)/sizeof(ixATTR11[0]), 0, 0 },
+	{ "ixCRT11", REG_SMC, 0x11, &ixCRT11[0], sizeof(ixCRT11)/sizeof(ixCRT11[0]), 0, 0 },
+	{ "mmDCCG_CBUS_WRCMD_DELAY", REG_MMIO, 0x110, &mmDCCG_CBUS_WRCMD_DELAY[0], sizeof(mmDCCG_CBUS_WRCMD_DELAY)/sizeof(mmDCCG_CBUS_WRCMD_DELAY[0]), 0, 0 },
+	{ "mmDCCG_DS_DEBUG_CNTL", REG_MMIO, 0x112, &mmDCCG_DS_DEBUG_CNTL[0], sizeof(mmDCCG_DS_DEBUG_CNTL)/sizeof(mmDCCG_DS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DS_DTO_INCR", REG_MMIO, 0x113, &mmDCCG_DS_DTO_INCR[0], sizeof(mmDCCG_DS_DTO_INCR)/sizeof(mmDCCG_DS_DTO_INCR[0]), 0, 0 },
+	{ "mmDCCG_DS_DTO_MODULO", REG_MMIO, 0x114, &mmDCCG_DS_DTO_MODULO[0], sizeof(mmDCCG_DS_DTO_MODULO)/sizeof(mmDCCG_DS_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_DS_CNTL", REG_MMIO, 0x115, &mmDCCG_DS_CNTL[0], sizeof(mmDCCG_DS_CNTL)/sizeof(mmDCCG_DS_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DS_HW_CAL_INTERVAL", REG_MMIO, 0x116, &mmDCCG_DS_HW_CAL_INTERVAL[0], sizeof(mmDCCG_DS_HW_CAL_INTERVAL)/sizeof(mmDCCG_DS_HW_CAL_INTERVAL[0]), 0, 0 },
+	{ "mmDPREFCLK_CNTL", REG_MMIO, 0x118, &mmDPREFCLK_CNTL[0], sizeof(mmDPREFCLK_CNTL)/sizeof(mmDPREFCLK_CNTL[0]), 0, 0 },
+	{ "mmVGA_MEM_WRITE_PAGE_ADDR", REG_MMIO, 0x12, &mmVGA_MEM_WRITE_PAGE_ADDR[0], sizeof(mmVGA_MEM_WRITE_PAGE_ADDR)/sizeof(mmVGA_MEM_WRITE_PAGE_ADDR[0]), 0, 0 },
+	{ "mmCORB_WRITE_POINTER", REG_MMIO, 0x12, &mmCORB_WRITE_POINTER[0], sizeof(mmCORB_WRITE_POINTER)/sizeof(mmCORB_WRITE_POINTER[0]), 0, 0 },
+	{ "mmCORB_READ_POINTER", REG_MMIO, 0x12, &mmCORB_READ_POINTER[0], sizeof(mmCORB_READ_POINTER)/sizeof(mmCORB_READ_POINTER[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_C", REG_SMC, 0x12, &ixDP_AUX_DEBUG_C[0], sizeof(ixDP_AUX_DEBUG_C)/sizeof(ixDP_AUX_DEBUG_C[0]), 0, 0 },
+	{ "ixDCIO_DEBUG12", REG_SMC, 0x12, &ixDCIO_DEBUG12[0], sizeof(ixDCIO_DEBUG12)/sizeof(ixDCIO_DEBUG12[0]), 0, 0 },
+	{ "ixATTR12", REG_SMC, 0x12, &ixATTR12[0], sizeof(ixATTR12)/sizeof(ixATTR12[0]), 0, 0 },
+	{ "ixCRT12", REG_SMC, 0x12, &ixCRT12[0], sizeof(ixCRT12)/sizeof(ixCRT12[0]), 0, 0 },
+	{ "mmDCCG_GTC_CNTL", REG_MMIO, 0x120, &mmDCCG_GTC_CNTL[0], sizeof(mmDCCG_GTC_CNTL)/sizeof(mmDCCG_GTC_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_INCR", REG_MMIO, 0x121, &mmDCCG_GTC_DTO_INCR[0], sizeof(mmDCCG_GTC_DTO_INCR)/sizeof(mmDCCG_GTC_DTO_INCR[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_MODULO", REG_MMIO, 0x122, &mmDCCG_GTC_DTO_MODULO[0], sizeof(mmDCCG_GTC_DTO_MODULO)/sizeof(mmDCCG_GTC_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_GTC_CURRENT", REG_MMIO, 0x123, &mmDCCG_GTC_CURRENT[0], sizeof(mmDCCG_GTC_CURRENT)/sizeof(mmDCCG_GTC_CURRENT[0]), 0, 0 },
+	{ "mmDENTIST_DISPCLK_CNTL", REG_MMIO, 0x124, &mmDENTIST_DISPCLK_CNTL[0], sizeof(mmDENTIST_DISPCLK_CNTL)/sizeof(mmDENTIST_DISPCLK_CNTL[0]), 0, 0 },
+	{ "mmDAC_CLK_ENABLE", REG_MMIO, 0x128, &mmDAC_CLK_ENABLE[0], sizeof(mmDAC_CLK_ENABLE)/sizeof(mmDAC_CLK_ENABLE[0]), 0, 0 },
+	{ "mmDVO_CLK_ENABLE", REG_MMIO, 0x129, &mmDVO_CLK_ENABLE[0], sizeof(mmDVO_CLK_ENABLE)/sizeof(mmDVO_CLK_ENABLE[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_WRITE", REG_MMIO, 0x12a, &mmAVSYNC_COUNTER_WRITE[0], sizeof(mmAVSYNC_COUNTER_WRITE)/sizeof(mmAVSYNC_COUNTER_WRITE[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_CONTROL", REG_MMIO, 0x12b, &mmAVSYNC_COUNTER_CONTROL[0], sizeof(mmAVSYNC_COUNTER_CONTROL)/sizeof(mmAVSYNC_COUNTER_CONTROL[0]), 0, 0 },
+	{ "mmDMCU_SMU_INTERRUPT_CNTL", REG_MMIO, 0x12c, &mmDMCU_SMU_INTERRUPT_CNTL[0], sizeof(mmDMCU_SMU_INTERRUPT_CNTL)/sizeof(mmDMCU_SMU_INTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmSMU_CONTROL", REG_MMIO, 0x12d, &mmSMU_CONTROL[0], sizeof(mmSMU_CONTROL)/sizeof(mmSMU_CONTROL[0]), 0, 0 },
+	{ "mmSMU_INTERRUPT_CONTROL", REG_MMIO, 0x12e, &mmSMU_INTERRUPT_CONTROL[0], sizeof(mmSMU_INTERRUPT_CONTROL)/sizeof(mmSMU_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_READ", REG_MMIO, 0x12f, &mmAVSYNC_COUNTER_READ[0], sizeof(mmAVSYNC_COUNTER_READ)/sizeof(mmAVSYNC_COUNTER_READ[0]), 0, 0 },
+	{ "mmVGA_MEM_READ_PAGE_ADDR", REG_MMIO, 0x13, &mmVGA_MEM_READ_PAGE_ADDR[0], sizeof(mmVGA_MEM_READ_PAGE_ADDR)/sizeof(mmVGA_MEM_READ_PAGE_ADDR[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION14", REG_SMC, 0x13, &ixSINK_DESCRIPTION14[0], sizeof(ixSINK_DESCRIPTION14)/sizeof(ixSINK_DESCRIPTION14[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_D", REG_SMC, 0x13, &ixDP_AUX_DEBUG_D[0], sizeof(ixDP_AUX_DEBUG_D)/sizeof(ixDP_AUX_DEBUG_D[0]), 0, 0 },
+	{ "ixDCIO_DEBUG13", REG_SMC, 0x13, &ixDCIO_DEBUG13[0], sizeof(ixDCIO_DEBUG13)/sizeof(ixDCIO_DEBUG13[0]), 0, 0 },
+	{ "mmCORB_STATUS", REG_MMIO, 0x13, &mmCORB_STATUS[0], sizeof(mmCORB_STATUS)/sizeof(mmCORB_STATUS[0]), 0, 0 },
+	{ "mmCORB_SIZE", REG_MMIO, 0x13, &mmCORB_SIZE[0], sizeof(mmCORB_SIZE)/sizeof(mmCORB_SIZE[0]), 0, 0 },
+	{ "ixATTR13", REG_SMC, 0x13, &ixATTR13[0], sizeof(ixATTR13)/sizeof(ixATTR13[0]), 0, 0 },
+	{ "ixCRT13", REG_SMC, 0x13, &ixCRT13[0], sizeof(ixCRT13)/sizeof(ixCRT13[0]), 0, 0 },
+	{ "mmMILLISECOND_TIME_BASE_DIV", REG_MMIO, 0x130, &mmMILLISECOND_TIME_BASE_DIV[0], sizeof(mmMILLISECOND_TIME_BASE_DIV)/sizeof(mmMILLISECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDISPCLK_FREQ_CHANGE_CNTL", REG_MMIO, 0x131, &mmDISPCLK_FREQ_CHANGE_CNTL[0], sizeof(mmDISPCLK_FREQ_CHANGE_CNTL)/sizeof(mmDISPCLK_FREQ_CHANGE_CNTL[0]), 0, 0 },
+	{ "mmDC_MEM_GLOBAL_PWR_REQ_CNTL", REG_MMIO, 0x132, &mmDC_MEM_GLOBAL_PWR_REQ_CNTL[0], sizeof(mmDC_MEM_GLOBAL_PWR_REQ_CNTL)/sizeof(mmDC_MEM_GLOBAL_PWR_REQ_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PERFMON_CNTL", REG_MMIO, 0x133, &mmDCCG_PERFMON_CNTL[0], sizeof(mmDCCG_PERFMON_CNTL)/sizeof(mmDCCG_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GATE_DISABLE_CNTL", REG_MMIO, 0x134, &mmDCCG_GATE_DISABLE_CNTL[0], sizeof(mmDCCG_GATE_DISABLE_CNTL)/sizeof(mmDCCG_GATE_DISABLE_CNTL[0]), 0, 0 },
+	{ "mmDISPCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x135, &mmDISPCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmSCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x136, &mmSCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmDCCG_CAC_STATUS", REG_MMIO, 0x137, &mmDCCG_CAC_STATUS[0], sizeof(mmDCCG_CAC_STATUS)/sizeof(mmDCCG_CAC_STATUS[0]), 0, 0 },
+	{ "mmPIXCLK1_RESYNC_CNTL", REG_MMIO, 0x138, &mmPIXCLK1_RESYNC_CNTL[0], sizeof(mmPIXCLK1_RESYNC_CNTL)/sizeof(mmPIXCLK1_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPIXCLK2_RESYNC_CNTL", REG_MMIO, 0x139, &mmPIXCLK2_RESYNC_CNTL[0], sizeof(mmPIXCLK2_RESYNC_CNTL)/sizeof(mmPIXCLK2_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPIXCLK0_RESYNC_CNTL", REG_MMIO, 0x13a, &mmPIXCLK0_RESYNC_CNTL[0], sizeof(mmPIXCLK0_RESYNC_CNTL)/sizeof(mmPIXCLK0_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmMICROSECOND_TIME_BASE_DIV", REG_MMIO, 0x13b, &mmMICROSECOND_TIME_BASE_DIV[0], sizeof(mmMICROSECOND_TIME_BASE_DIV)/sizeof(mmMICROSECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDCCG_DISP_CNTL_REG", REG_MMIO, 0x13f, &mmDCCG_DISP_CNTL_REG[0], sizeof(mmDCCG_DISP_CNTL_REG)/sizeof(mmDCCG_DISP_CNTL_REG[0]), 0, 0 },
+	{ "mmRIRB_LOWER_BASE_ADDRESS", REG_MMIO, 0x14, &mmRIRB_LOWER_BASE_ADDRESS[0], sizeof(mmRIRB_LOWER_BASE_ADDRESS)/sizeof(mmRIRB_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION15", REG_SMC, 0x14, &ixSINK_DESCRIPTION15[0], sizeof(ixSINK_DESCRIPTION15)/sizeof(ixSINK_DESCRIPTION15[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_E", REG_SMC, 0x14, &ixDP_AUX_DEBUG_E[0], sizeof(ixDP_AUX_DEBUG_E)/sizeof(ixDP_AUX_DEBUG_E[0]), 0, 0 },
+	{ "ixDCIO_DEBUG14", REG_SMC, 0x14, &ixDCIO_DEBUG14[0], sizeof(ixDCIO_DEBUG14)/sizeof(ixDCIO_DEBUG14[0]), 0, 0 },
+	{ "ixATTR14", REG_SMC, 0x14, &ixATTR14[0], sizeof(ixATTR14)/sizeof(ixATTR14[0]), 0, 0 },
+	{ "ixCRT14", REG_SMC, 0x14, &ixCRT14[0], sizeof(ixCRT14)/sizeof(ixCRT14[0]), 0, 0 },
+	{ "mmCRTC0_PIXEL_RATE_CNTL", REG_MMIO, 0x140, &mmCRTC0_PIXEL_RATE_CNTL[0], sizeof(mmCRTC0_PIXEL_RATE_CNTL)/sizeof(mmCRTC0_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO0_PHASE", REG_MMIO, 0x141, &mmDP_DTO0_PHASE[0], sizeof(mmDP_DTO0_PHASE)/sizeof(mmDP_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO0_MODULO", REG_MMIO, 0x142, &mmDP_DTO0_MODULO[0], sizeof(mmDP_DTO0_MODULO)/sizeof(mmDP_DTO0_MODULO[0]), 0, 0 },
+	{ "mmCRTC1_PIXEL_RATE_CNTL", REG_MMIO, 0x144, &mmCRTC1_PIXEL_RATE_CNTL[0], sizeof(mmCRTC1_PIXEL_RATE_CNTL)/sizeof(mmCRTC1_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO1_PHASE", REG_MMIO, 0x145, &mmDP_DTO1_PHASE[0], sizeof(mmDP_DTO1_PHASE)/sizeof(mmDP_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO1_MODULO", REG_MMIO, 0x146, &mmDP_DTO1_MODULO[0], sizeof(mmDP_DTO1_MODULO)/sizeof(mmDP_DTO1_MODULO[0]), 0, 0 },
+	{ "mmCRTC2_PIXEL_RATE_CNTL", REG_MMIO, 0x148, &mmCRTC2_PIXEL_RATE_CNTL[0], sizeof(mmCRTC2_PIXEL_RATE_CNTL)/sizeof(mmCRTC2_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO2_PHASE", REG_MMIO, 0x149, &mmDP_DTO2_PHASE[0], sizeof(mmDP_DTO2_PHASE)/sizeof(mmDP_DTO2_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO2_MODULO", REG_MMIO, 0x14a, &mmDP_DTO2_MODULO[0], sizeof(mmDP_DTO2_MODULO)/sizeof(mmDP_DTO2_MODULO[0]), 0, 0 },
+	{ "mmCRTC3_PIXEL_RATE_CNTL", REG_MMIO, 0x14c, &mmCRTC3_PIXEL_RATE_CNTL[0], sizeof(mmCRTC3_PIXEL_RATE_CNTL)/sizeof(mmCRTC3_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO3_PHASE", REG_MMIO, 0x14d, &mmDP_DTO3_PHASE[0], sizeof(mmDP_DTO3_PHASE)/sizeof(mmDP_DTO3_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO3_MODULO", REG_MMIO, 0x14e, &mmDP_DTO3_MODULO[0], sizeof(mmDP_DTO3_MODULO)/sizeof(mmDP_DTO3_MODULO[0]), 0, 0 },
+	{ "mmRIRB_UPPER_BASE_ADDRESS", REG_MMIO, 0x15, &mmRIRB_UPPER_BASE_ADDRESS[0], sizeof(mmRIRB_UPPER_BASE_ADDRESS)/sizeof(mmRIRB_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION16", REG_SMC, 0x15, &ixSINK_DESCRIPTION16[0], sizeof(ixSINK_DESCRIPTION16)/sizeof(ixSINK_DESCRIPTION16[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_F", REG_SMC, 0x15, &ixDP_AUX_DEBUG_F[0], sizeof(ixDP_AUX_DEBUG_F)/sizeof(ixDP_AUX_DEBUG_F[0]), 0, 0 },
+	{ "ixDCIO_DEBUG15", REG_SMC, 0x15, &ixDCIO_DEBUG15[0], sizeof(ixDCIO_DEBUG15)/sizeof(ixDCIO_DEBUG15[0]), 0, 0 },
+	{ "ixCRT15", REG_SMC, 0x15, &ixCRT15[0], sizeof(ixCRT15)/sizeof(ixCRT15[0]), 0, 0 },
+	{ "mmCRTC4_PIXEL_RATE_CNTL", REG_MMIO, 0x150, &mmCRTC4_PIXEL_RATE_CNTL[0], sizeof(mmCRTC4_PIXEL_RATE_CNTL)/sizeof(mmCRTC4_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO4_PHASE", REG_MMIO, 0x151, &mmDP_DTO4_PHASE[0], sizeof(mmDP_DTO4_PHASE)/sizeof(mmDP_DTO4_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO4_MODULO", REG_MMIO, 0x152, &mmDP_DTO4_MODULO[0], sizeof(mmDP_DTO4_MODULO)/sizeof(mmDP_DTO4_MODULO[0]), 0, 0 },
+	{ "mmCRTC5_PIXEL_RATE_CNTL", REG_MMIO, 0x154, &mmCRTC5_PIXEL_RATE_CNTL[0], sizeof(mmCRTC5_PIXEL_RATE_CNTL)/sizeof(mmCRTC5_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO5_PHASE", REG_MMIO, 0x155, &mmDP_DTO5_PHASE[0], sizeof(mmDP_DTO5_PHASE)/sizeof(mmDP_DTO5_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO5_MODULO", REG_MMIO, 0x156, &mmDP_DTO5_MODULO[0], sizeof(mmDP_DTO5_MODULO)/sizeof(mmDP_DTO5_MODULO[0]), 0, 0 },
+	{ "mmDCCG_SOFT_RESET", REG_MMIO, 0x15f, &mmDCCG_SOFT_RESET[0], sizeof(mmDCCG_SOFT_RESET)/sizeof(mmDCCG_SOFT_RESET[0]), 0, 0 },
+	{ "mmRESPONSE_INTERRUPT_COUNT", REG_MMIO, 0x16, &mmRESPONSE_INTERRUPT_COUNT[0], sizeof(mmRESPONSE_INTERRUPT_COUNT)/sizeof(mmRESPONSE_INTERRUPT_COUNT[0]), 0, 0 },
+	{ "mmRIRB_WRITE_POINTER", REG_MMIO, 0x16, &mmRIRB_WRITE_POINTER[0], sizeof(mmRIRB_WRITE_POINTER)/sizeof(mmRIRB_WRITE_POINTER[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_G", REG_SMC, 0x16, &ixDP_AUX_DEBUG_G[0], sizeof(ixDP_AUX_DEBUG_G)/sizeof(ixDP_AUX_DEBUG_G[0]), 0, 0 },
+	{ "ixDCIO_DEBUG16", REG_SMC, 0x16, &ixDCIO_DEBUG16[0], sizeof(ixDCIO_DEBUG16)/sizeof(ixDCIO_DEBUG16[0]), 0, 0 },
+	{ "ixCRT16", REG_SMC, 0x16, &ixCRT16[0], sizeof(ixCRT16)/sizeof(ixCRT16[0]), 0, 0 },
+	{ "mmSYMCLKA_CLOCK_ENABLE", REG_MMIO, 0x160, &mmSYMCLKA_CLOCK_ENABLE[0], sizeof(mmSYMCLKA_CLOCK_ENABLE)/sizeof(mmSYMCLKA_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_CTRL", REG_MMIO, 0x1600, &mmDMCU_CTRL[0], sizeof(mmDMCU_CTRL)/sizeof(mmDMCU_CTRL[0]), 0, 0 },
+	{ "mmDMCU_STATUS", REG_MMIO, 0x1601, &mmDMCU_STATUS[0], sizeof(mmDMCU_STATUS)/sizeof(mmDMCU_STATUS[0]), 0, 0 },
+	{ "mmDMCU_PC_START_ADDR", REG_MMIO, 0x1602, &mmDMCU_PC_START_ADDR[0], sizeof(mmDMCU_PC_START_ADDR)/sizeof(mmDMCU_PC_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_START_ADDR", REG_MMIO, 0x1603, &mmDMCU_FW_START_ADDR[0], sizeof(mmDMCU_FW_START_ADDR)/sizeof(mmDMCU_FW_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_END_ADDR", REG_MMIO, 0x1604, &mmDMCU_FW_END_ADDR[0], sizeof(mmDMCU_FW_END_ADDR)/sizeof(mmDMCU_FW_END_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_ISR_START_ADDR", REG_MMIO, 0x1605, &mmDMCU_FW_ISR_START_ADDR[0], sizeof(mmDMCU_FW_ISR_START_ADDR)/sizeof(mmDMCU_FW_ISR_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_HI", REG_MMIO, 0x1606, &mmDMCU_FW_CS_HI[0], sizeof(mmDMCU_FW_CS_HI)/sizeof(mmDMCU_FW_CS_HI[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_LO", REG_MMIO, 0x1607, &mmDMCU_FW_CS_LO[0], sizeof(mmDMCU_FW_CS_LO)/sizeof(mmDMCU_FW_CS_LO[0]), 0, 0 },
+	{ "mmDMCU_RAM_ACCESS_CTRL", REG_MMIO, 0x1608, &mmDMCU_RAM_ACCESS_CTRL[0], sizeof(mmDMCU_RAM_ACCESS_CTRL)/sizeof(mmDMCU_RAM_ACCESS_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_CTRL", REG_MMIO, 0x1609, &mmDMCU_ERAM_WR_CTRL[0], sizeof(mmDMCU_ERAM_WR_CTRL)/sizeof(mmDMCU_ERAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_DATA", REG_MMIO, 0x160a, &mmDMCU_ERAM_WR_DATA[0], sizeof(mmDMCU_ERAM_WR_DATA)/sizeof(mmDMCU_ERAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_CTRL", REG_MMIO, 0x160b, &mmDMCU_ERAM_RD_CTRL[0], sizeof(mmDMCU_ERAM_RD_CTRL)/sizeof(mmDMCU_ERAM_RD_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_DATA", REG_MMIO, 0x160c, &mmDMCU_ERAM_RD_DATA[0], sizeof(mmDMCU_ERAM_RD_DATA)/sizeof(mmDMCU_ERAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_CTRL", REG_MMIO, 0x160d, &mmDMCU_IRAM_WR_CTRL[0], sizeof(mmDMCU_IRAM_WR_CTRL)/sizeof(mmDMCU_IRAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_DATA", REG_MMIO, 0x160e, &mmDMCU_IRAM_WR_DATA[0], sizeof(mmDMCU_IRAM_WR_DATA)/sizeof(mmDMCU_IRAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_CTRL", REG_MMIO, 0x160f, &mmDMCU_IRAM_RD_CTRL[0], sizeof(mmDMCU_IRAM_RD_CTRL)/sizeof(mmDMCU_IRAM_RD_CTRL[0]), 0, 0 },
+	{ "mmSYMCLKB_CLOCK_ENABLE", REG_MMIO, 0x161, &mmSYMCLKB_CLOCK_ENABLE[0], sizeof(mmSYMCLKB_CLOCK_ENABLE)/sizeof(mmSYMCLKB_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_DATA", REG_MMIO, 0x1610, &mmDMCU_IRAM_RD_DATA[0], sizeof(mmDMCU_IRAM_RD_DATA)/sizeof(mmDMCU_IRAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_EVENT_TRIGGER", REG_MMIO, 0x1611, &mmDMCU_EVENT_TRIGGER[0], sizeof(mmDMCU_EVENT_TRIGGER)/sizeof(mmDMCU_EVENT_TRIGGER[0]), 0, 0 },
+	{ "mmDMCU_UC_INTERNAL_INT_STATUS", REG_MMIO, 0x1612, &mmDMCU_UC_INTERNAL_INT_STATUS[0], sizeof(mmDMCU_UC_INTERNAL_INT_STATUS)/sizeof(mmDMCU_UC_INTERNAL_INT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_SS_INTERRUPT_CNTL_STATUS", REG_MMIO, 0x1613, &mmDMCU_SS_INTERRUPT_CNTL_STATUS[0], sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS)/sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_STATUS", REG_MMIO, 0x1614, &mmDMCU_INTERRUPT_STATUS[0], sizeof(mmDMCU_INTERRUPT_STATUS)/sizeof(mmDMCU_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_HOST_EN_MASK", REG_MMIO, 0x1615, &mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_EN_MASK", REG_MMIO, 0x1616, &mmDMCU_INTERRUPT_TO_UC_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL", REG_MMIO, 0x1617, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0]), 0, 0 },
+	{ "mmDC_DMCU_SCRATCH", REG_MMIO, 0x1618, &mmDC_DMCU_SCRATCH[0], sizeof(mmDC_DMCU_SCRATCH)/sizeof(mmDC_DMCU_SCRATCH[0]), 0, 0 },
+	{ "mmDMCU_INT_CNT", REG_MMIO, 0x1619, &mmDMCU_INT_CNT[0], sizeof(mmDMCU_INT_CNT)/sizeof(mmDMCU_INT_CNT[0]), 0, 0 },
+	{ "mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS", REG_MMIO, 0x161a, &mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0], sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS)/sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0]), 0, 0 },
+	{ "mmDMCU_UC_CLK_GATING_CNTL", REG_MMIO, 0x161b, &mmDMCU_UC_CLK_GATING_CNTL[0], sizeof(mmDMCU_UC_CLK_GATING_CNTL)/sizeof(mmDMCU_UC_CLK_GATING_CNTL[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG1", REG_MMIO, 0x161c, &mmMASTER_COMM_DATA_REG1[0], sizeof(mmMASTER_COMM_DATA_REG1)/sizeof(mmMASTER_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG2", REG_MMIO, 0x161d, &mmMASTER_COMM_DATA_REG2[0], sizeof(mmMASTER_COMM_DATA_REG2)/sizeof(mmMASTER_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG3", REG_MMIO, 0x161e, &mmMASTER_COMM_DATA_REG3[0], sizeof(mmMASTER_COMM_DATA_REG3)/sizeof(mmMASTER_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmMASTER_COMM_CMD_REG", REG_MMIO, 0x161f, &mmMASTER_COMM_CMD_REG[0], sizeof(mmMASTER_COMM_CMD_REG)/sizeof(mmMASTER_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSYMCLKC_CLOCK_ENABLE", REG_MMIO, 0x162, &mmSYMCLKC_CLOCK_ENABLE[0], sizeof(mmSYMCLKC_CLOCK_ENABLE)/sizeof(mmSYMCLKC_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmMASTER_COMM_CNTL_REG", REG_MMIO, 0x1620, &mmMASTER_COMM_CNTL_REG[0], sizeof(mmMASTER_COMM_CNTL_REG)/sizeof(mmMASTER_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG1", REG_MMIO, 0x1621, &mmSLAVE_COMM_DATA_REG1[0], sizeof(mmSLAVE_COMM_DATA_REG1)/sizeof(mmSLAVE_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG2", REG_MMIO, 0x1622, &mmSLAVE_COMM_DATA_REG2[0], sizeof(mmSLAVE_COMM_DATA_REG2)/sizeof(mmSLAVE_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG3", REG_MMIO, 0x1623, &mmSLAVE_COMM_DATA_REG3[0], sizeof(mmSLAVE_COMM_DATA_REG3)/sizeof(mmSLAVE_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CMD_REG", REG_MMIO, 0x1624, &mmSLAVE_COMM_CMD_REG[0], sizeof(mmSLAVE_COMM_CMD_REG)/sizeof(mmSLAVE_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CNTL_REG", REG_MMIO, 0x1625, &mmSLAVE_COMM_CNTL_REG[0], sizeof(mmSLAVE_COMM_CNTL_REG)/sizeof(mmSLAVE_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_INDEX", REG_MMIO, 0x1626, &mmDMCU_TEST_DEBUG_INDEX[0], sizeof(mmDMCU_TEST_DEBUG_INDEX)/sizeof(mmDMCU_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_DATA", REG_MMIO, 0x1627, &mmDMCU_TEST_DEBUG_DATA[0], sizeof(mmDMCU_TEST_DEBUG_DATA)/sizeof(mmDMCU_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBL1_PWM_AMBIENT_LIGHT_LEVEL", REG_MMIO, 0x1628, &mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0], sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL)/sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_USER_LEVEL", REG_MMIO, 0x1629, &mmBL1_PWM_USER_LEVEL[0], sizeof(mmBL1_PWM_USER_LEVEL)/sizeof(mmBL1_PWM_USER_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_TARGET_ABM_LEVEL", REG_MMIO, 0x162a, &mmBL1_PWM_TARGET_ABM_LEVEL[0], sizeof(mmBL1_PWM_TARGET_ABM_LEVEL)/sizeof(mmBL1_PWM_TARGET_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_CURRENT_ABM_LEVEL", REG_MMIO, 0x162b, &mmBL1_PWM_CURRENT_ABM_LEVEL[0], sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL)/sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_FINAL_DUTY_CYCLE", REG_MMIO, 0x162c, &mmBL1_PWM_FINAL_DUTY_CYCLE[0], sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE)/sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_MINIMUM_DUTY_CYCLE", REG_MMIO, 0x162d, &mmBL1_PWM_MINIMUM_DUTY_CYCLE[0], sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE)/sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_ABM_CNTL", REG_MMIO, 0x162e, &mmBL1_PWM_ABM_CNTL[0], sizeof(mmBL1_PWM_ABM_CNTL)/sizeof(mmBL1_PWM_ABM_CNTL[0]), 0, 0 },
+	{ "mmBL1_PWM_BL_UPDATE_SAMPLE_RATE", REG_MMIO, 0x162f, &mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0], sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE)/sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmSYMCLKD_CLOCK_ENABLE", REG_MMIO, 0x163, &mmSYMCLKD_CLOCK_ENABLE[0], sizeof(mmSYMCLKD_CLOCK_ENABLE)/sizeof(mmSYMCLKD_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmBL1_PWM_GRP2_REG_LOCK", REG_MMIO, 0x1630, &mmBL1_PWM_GRP2_REG_LOCK[0], sizeof(mmBL1_PWM_GRP2_REG_LOCK)/sizeof(mmBL1_PWM_GRP2_REG_LOCK[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5", REG_MMIO, 0x1633, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK5[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_STATUS1", REG_MMIO, 0x1634, &mmDMCU_DPRX_INTERRUPT_STATUS1[0], sizeof(mmDMCU_DPRX_INTERRUPT_STATUS1)/sizeof(mmDMCU_DPRX_INTERRUPT_STATUS1[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x1635, &mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x1636, &mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 },
+	{ "mmDC_ABM1_CNTL", REG_MMIO, 0x1638, &mmDC_ABM1_CNTL[0], sizeof(mmDC_ABM1_CNTL)/sizeof(mmDC_ABM1_CNTL[0]), 0, 0 },
+	{ "mmDC_ABM1_IPCSC_COEFF_SEL", REG_MMIO, 0x1639, &mmDC_ABM1_IPCSC_COEFF_SEL[0], sizeof(mmDC_ABM1_IPCSC_COEFF_SEL)/sizeof(mmDC_ABM1_IPCSC_COEFF_SEL[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_0", REG_MMIO, 0x163a, &mmDC_ABM1_ACE_OFFSET_SLOPE_0[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_1", REG_MMIO, 0x163b, &mmDC_ABM1_ACE_OFFSET_SLOPE_1[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_2", REG_MMIO, 0x163c, &mmDC_ABM1_ACE_OFFSET_SLOPE_2[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_3", REG_MMIO, 0x163d, &mmDC_ABM1_ACE_OFFSET_SLOPE_3[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_4", REG_MMIO, 0x163e, &mmDC_ABM1_ACE_OFFSET_SLOPE_4[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_12", REG_MMIO, 0x163f, &mmDC_ABM1_ACE_THRES_12[0], sizeof(mmDC_ABM1_ACE_THRES_12)/sizeof(mmDC_ABM1_ACE_THRES_12[0]), 0, 0 },
+	{ "mmSYMCLKE_CLOCK_ENABLE", REG_MMIO, 0x164, &mmSYMCLKE_CLOCK_ENABLE[0], sizeof(mmSYMCLKE_CLOCK_ENABLE)/sizeof(mmSYMCLKE_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_34", REG_MMIO, 0x1640, &mmDC_ABM1_ACE_THRES_34[0], sizeof(mmDC_ABM1_ACE_THRES_34)/sizeof(mmDC_ABM1_ACE_THRES_34[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_CNTL_MISC", REG_MMIO, 0x1641, &mmDC_ABM1_ACE_CNTL_MISC[0], sizeof(mmDC_ABM1_ACE_CNTL_MISC)/sizeof(mmDC_ABM1_ACE_CNTL_MISC[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS5", REG_MMIO, 0x1642, &mmDMCU_PERFMON_INTERRUPT_STATUS5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS5)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5", REG_MMIO, 0x1643, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS1", REG_MMIO, 0x1644, &mmDMCU_PERFMON_INTERRUPT_STATUS1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS2", REG_MMIO, 0x1645, &mmDMCU_PERFMON_INTERRUPT_STATUS2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS3", REG_MMIO, 0x1646, &mmDMCU_PERFMON_INTERRUPT_STATUS3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS4", REG_MMIO, 0x1647, &mmDMCU_PERFMON_INTERRUPT_STATUS4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4[0]), 0, 0 },
+	{ "mmDC_ABM1_DEBUG_MISC", REG_MMIO, 0x1649, &mmDC_ABM1_DEBUG_MISC[0], sizeof(mmDC_ABM1_DEBUG_MISC)/sizeof(mmDC_ABM1_DEBUG_MISC[0]), 0, 0 },
+	{ "mmDC_ABM1_HGLS_REG_READ_PROGRESS", REG_MMIO, 0x164a, &mmDC_ABM1_HGLS_REG_READ_PROGRESS[0], sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS)/sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_MISC_CTRL", REG_MMIO, 0x164b, &mmDC_ABM1_HG_MISC_CTRL[0], sizeof(mmDC_ABM1_HG_MISC_CTRL)/sizeof(mmDC_ABM1_HG_MISC_CTRL[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SUM_OF_LUMA", REG_MMIO, 0x164c, &mmDC_ABM1_LS_SUM_OF_LUMA[0], sizeof(mmDC_ABM1_LS_SUM_OF_LUMA)/sizeof(mmDC_ABM1_LS_SUM_OF_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_LUMA", REG_MMIO, 0x164d, &mmDC_ABM1_LS_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA", REG_MMIO, 0x164e, &mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_PIXEL_COUNT", REG_MMIO, 0x164f, &mmDC_ABM1_LS_PIXEL_COUNT[0], sizeof(mmDC_ABM1_LS_PIXEL_COUNT)/sizeof(mmDC_ABM1_LS_PIXEL_COUNT[0]), 0, 0 },
+	{ "mmSYMCLKF_CLOCK_ENABLE", REG_MMIO, 0x165, &mmSYMCLKF_CLOCK_ENABLE[0], sizeof(mmSYMCLKF_CLOCK_ENABLE)/sizeof(mmSYMCLKF_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_OVR_SCAN_BIN", REG_MMIO, 0x1650, &mmDC_ABM1_LS_OVR_SCAN_BIN[0], sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN)/sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES", REG_MMIO, 0x1651, &mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0], sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES)/sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT", REG_MMIO, 0x1652, &mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT", REG_MMIO, 0x1653, &mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_SAMPLE_RATE", REG_MMIO, 0x1654, &mmDC_ABM1_HG_SAMPLE_RATE[0], sizeof(mmDC_ABM1_HG_SAMPLE_RATE)/sizeof(mmDC_ABM1_HG_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SAMPLE_RATE", REG_MMIO, 0x1655, &mmDC_ABM1_LS_SAMPLE_RATE[0], sizeof(mmDC_ABM1_LS_SAMPLE_RATE)/sizeof(mmDC_ABM1_LS_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG", REG_MMIO, 0x1656, &mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0], sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG)/sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX", REG_MMIO, 0x1657, &mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX", REG_MMIO, 0x1658, &mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX", REG_MMIO, 0x1659, &mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX", REG_MMIO, 0x165a, &mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_1", REG_MMIO, 0x165b, &mmDC_ABM1_HG_RESULT_1[0], sizeof(mmDC_ABM1_HG_RESULT_1)/sizeof(mmDC_ABM1_HG_RESULT_1[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_2", REG_MMIO, 0x165c, &mmDC_ABM1_HG_RESULT_2[0], sizeof(mmDC_ABM1_HG_RESULT_2)/sizeof(mmDC_ABM1_HG_RESULT_2[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_3", REG_MMIO, 0x165d, &mmDC_ABM1_HG_RESULT_3[0], sizeof(mmDC_ABM1_HG_RESULT_3)/sizeof(mmDC_ABM1_HG_RESULT_3[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_4", REG_MMIO, 0x165e, &mmDC_ABM1_HG_RESULT_4[0], sizeof(mmDC_ABM1_HG_RESULT_4)/sizeof(mmDC_ABM1_HG_RESULT_4[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_5", REG_MMIO, 0x165f, &mmDC_ABM1_HG_RESULT_5[0], sizeof(mmDC_ABM1_HG_RESULT_5)/sizeof(mmDC_ABM1_HG_RESULT_5[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_6", REG_MMIO, 0x1660, &mmDC_ABM1_HG_RESULT_6[0], sizeof(mmDC_ABM1_HG_RESULT_6)/sizeof(mmDC_ABM1_HG_RESULT_6[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_7", REG_MMIO, 0x1661, &mmDC_ABM1_HG_RESULT_7[0], sizeof(mmDC_ABM1_HG_RESULT_7)/sizeof(mmDC_ABM1_HG_RESULT_7[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_8", REG_MMIO, 0x1662, &mmDC_ABM1_HG_RESULT_8[0], sizeof(mmDC_ABM1_HG_RESULT_8)/sizeof(mmDC_ABM1_HG_RESULT_8[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_9", REG_MMIO, 0x1663, &mmDC_ABM1_HG_RESULT_9[0], sizeof(mmDC_ABM1_HG_RESULT_9)/sizeof(mmDC_ABM1_HG_RESULT_9[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_10", REG_MMIO, 0x1664, &mmDC_ABM1_HG_RESULT_10[0], sizeof(mmDC_ABM1_HG_RESULT_10)/sizeof(mmDC_ABM1_HG_RESULT_10[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_11", REG_MMIO, 0x1665, &mmDC_ABM1_HG_RESULT_11[0], sizeof(mmDC_ABM1_HG_RESULT_11)/sizeof(mmDC_ABM1_HG_RESULT_11[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_12", REG_MMIO, 0x1666, &mmDC_ABM1_HG_RESULT_12[0], sizeof(mmDC_ABM1_HG_RESULT_12)/sizeof(mmDC_ABM1_HG_RESULT_12[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_13", REG_MMIO, 0x1667, &mmDC_ABM1_HG_RESULT_13[0], sizeof(mmDC_ABM1_HG_RESULT_13)/sizeof(mmDC_ABM1_HG_RESULT_13[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_14", REG_MMIO, 0x1668, &mmDC_ABM1_HG_RESULT_14[0], sizeof(mmDC_ABM1_HG_RESULT_14)/sizeof(mmDC_ABM1_HG_RESULT_14[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_15", REG_MMIO, 0x1669, &mmDC_ABM1_HG_RESULT_15[0], sizeof(mmDC_ABM1_HG_RESULT_15)/sizeof(mmDC_ABM1_HG_RESULT_15[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_16", REG_MMIO, 0x166a, &mmDC_ABM1_HG_RESULT_16[0], sizeof(mmDC_ABM1_HG_RESULT_16)/sizeof(mmDC_ABM1_HG_RESULT_16[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_17", REG_MMIO, 0x166b, &mmDC_ABM1_HG_RESULT_17[0], sizeof(mmDC_ABM1_HG_RESULT_17)/sizeof(mmDC_ABM1_HG_RESULT_17[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_18", REG_MMIO, 0x166c, &mmDC_ABM1_HG_RESULT_18[0], sizeof(mmDC_ABM1_HG_RESULT_18)/sizeof(mmDC_ABM1_HG_RESULT_18[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_19", REG_MMIO, 0x166d, &mmDC_ABM1_HG_RESULT_19[0], sizeof(mmDC_ABM1_HG_RESULT_19)/sizeof(mmDC_ABM1_HG_RESULT_19[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_20", REG_MMIO, 0x166e, &mmDC_ABM1_HG_RESULT_20[0], sizeof(mmDC_ABM1_HG_RESULT_20)/sizeof(mmDC_ABM1_HG_RESULT_20[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_21", REG_MMIO, 0x166f, &mmDC_ABM1_HG_RESULT_21[0], sizeof(mmDC_ABM1_HG_RESULT_21)/sizeof(mmDC_ABM1_HG_RESULT_21[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_22", REG_MMIO, 0x1670, &mmDC_ABM1_HG_RESULT_22[0], sizeof(mmDC_ABM1_HG_RESULT_22)/sizeof(mmDC_ABM1_HG_RESULT_22[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_23", REG_MMIO, 0x1671, &mmDC_ABM1_HG_RESULT_23[0], sizeof(mmDC_ABM1_HG_RESULT_23)/sizeof(mmDC_ABM1_HG_RESULT_23[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_24", REG_MMIO, 0x1672, &mmDC_ABM1_HG_RESULT_24[0], sizeof(mmDC_ABM1_HG_RESULT_24)/sizeof(mmDC_ABM1_HG_RESULT_24[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5", REG_MMIO, 0x1673, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x1674, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2", REG_MMIO, 0x1675, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3", REG_MMIO, 0x1676, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4", REG_MMIO, 0x1677, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x1678, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2", REG_MMIO, 0x1679, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3", REG_MMIO, 0x167a, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4", REG_MMIO, 0x167b, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1", REG_MMIO, 0x167c, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2", REG_MMIO, 0x167d, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3", REG_MMIO, 0x167e, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4", REG_MMIO, 0x167f, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4[0]), 0, 0 },
+	{ "mmDVOACLKD_CNTL", REG_MMIO, 0x168, &mmDVOACLKD_CNTL[0], sizeof(mmDVOACLKD_CNTL)/sizeof(mmDVOACLKD_CNTL[0]), 0, 0 },
+	{ "mmDVOACLKC_MVP_CNTL", REG_MMIO, 0x169, &mmDVOACLKC_MVP_CNTL[0], sizeof(mmDVOACLKC_MVP_CNTL)/sizeof(mmDVOACLKC_MVP_CNTL[0]), 0, 0 },
+	{ "mmDC_ABM1_OVERSCAN_PIXEL_VALUE", REG_MMIO, 0x169b, &mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0], sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE)/sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0]), 0, 0 },
+	{ "mmDC_ABM1_BL_MASTER_LOCK", REG_MMIO, 0x169c, &mmDC_ABM1_BL_MASTER_LOCK[0], sizeof(mmDC_ABM1_BL_MASTER_LOCK)/sizeof(mmDC_ABM1_BL_MASTER_LOCK[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_INDEX", REG_MMIO, 0x169e, &mmABM_TEST_DEBUG_INDEX[0], sizeof(mmABM_TEST_DEBUG_INDEX)/sizeof(mmABM_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_DATA", REG_MMIO, 0x169f, &mmABM_TEST_DEBUG_DATA[0], sizeof(mmABM_TEST_DEBUG_DATA)/sizeof(mmABM_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDVOACLKC_CNTL", REG_MMIO, 0x16a, &mmDVOACLKC_CNTL[0], sizeof(mmDVOACLKC_CNTL)/sizeof(mmDVOACLKC_CNTL[0]), 0, 0 },
+	{ "mmDVO_ENABLE", REG_MMIO, 0x16a0, &mmDVO_ENABLE[0], sizeof(mmDVO_ENABLE)/sizeof(mmDVO_ENABLE[0]), 0, 0 },
+	{ "mmDVO_SOURCE_SELECT", REG_MMIO, 0x16a1, &mmDVO_SOURCE_SELECT[0], sizeof(mmDVO_SOURCE_SELECT)/sizeof(mmDVO_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDVO_OUTPUT", REG_MMIO, 0x16a2, &mmDVO_OUTPUT[0], sizeof(mmDVO_OUTPUT)/sizeof(mmDVO_OUTPUT[0]), 0, 0 },
+	{ "mmDVO_CONTROL", REG_MMIO, 0x16a3, &mmDVO_CONTROL[0], sizeof(mmDVO_CONTROL)/sizeof(mmDVO_CONTROL[0]), 0, 0 },
+	{ "mmDVO_CRC_EN", REG_MMIO, 0x16a4, &mmDVO_CRC_EN[0], sizeof(mmDVO_CRC_EN)/sizeof(mmDVO_CRC_EN[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_MASK", REG_MMIO, 0x16a5, &mmDVO_CRC2_SIG_MASK[0], sizeof(mmDVO_CRC2_SIG_MASK)/sizeof(mmDVO_CRC2_SIG_MASK[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_RESULT", REG_MMIO, 0x16a6, &mmDVO_CRC2_SIG_RESULT[0], sizeof(mmDVO_CRC2_SIG_RESULT)/sizeof(mmDVO_CRC2_SIG_RESULT[0]), 0, 0 },
+	{ "mmDVO_FIFO_ERROR_STATUS", REG_MMIO, 0x16a7, &mmDVO_FIFO_ERROR_STATUS[0], sizeof(mmDVO_FIFO_ERROR_STATUS)/sizeof(mmDVO_FIFO_ERROR_STATUS[0]), 0, 0 },
+	{ "mmDVO_TEST_DEBUG_INDEX", REG_MMIO, 0x16a8, &mmDVO_TEST_DEBUG_INDEX[0], sizeof(mmDVO_TEST_DEBUG_INDEX)/sizeof(mmDVO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDVO_TEST_DEBUG_DATA", REG_MMIO, 0x16a9, &mmDVO_TEST_DEBUG_DATA[0], sizeof(mmDVO_TEST_DEBUG_DATA)/sizeof(mmDVO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDAC_ENABLE", REG_MMIO, 0x16aa, &mmDAC_ENABLE[0], sizeof(mmDAC_ENABLE)/sizeof(mmDAC_ENABLE[0]), 0, 0 },
+	{ "mmDAC_SOURCE_SELECT", REG_MMIO, 0x16ab, &mmDAC_SOURCE_SELECT[0], sizeof(mmDAC_SOURCE_SELECT)/sizeof(mmDAC_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDAC_CRC_EN", REG_MMIO, 0x16ac, &mmDAC_CRC_EN[0], sizeof(mmDAC_CRC_EN)/sizeof(mmDAC_CRC_EN[0]), 0, 0 },
+	{ "mmDAC_CRC_CONTROL", REG_MMIO, 0x16ad, &mmDAC_CRC_CONTROL[0], sizeof(mmDAC_CRC_CONTROL)/sizeof(mmDAC_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB_MASK", REG_MMIO, 0x16ae, &mmDAC_CRC_SIG_RGB_MASK[0], sizeof(mmDAC_CRC_SIG_RGB_MASK)/sizeof(mmDAC_CRC_SIG_RGB_MASK[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL_MASK", REG_MMIO, 0x16af, &mmDAC_CRC_SIG_CONTROL_MASK[0], sizeof(mmDAC_CRC_SIG_CONTROL_MASK)/sizeof(mmDAC_CRC_SIG_CONTROL_MASK[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO_SOURCE", REG_MMIO, 0x16b, &mmDCCG_AUDIO_DTO_SOURCE[0], sizeof(mmDCCG_AUDIO_DTO_SOURCE)/sizeof(mmDCCG_AUDIO_DTO_SOURCE[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB", REG_MMIO, 0x16b0, &mmDAC_CRC_SIG_RGB[0], sizeof(mmDAC_CRC_SIG_RGB)/sizeof(mmDAC_CRC_SIG_RGB[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL", REG_MMIO, 0x16b1, &mmDAC_CRC_SIG_CONTROL[0], sizeof(mmDAC_CRC_SIG_CONTROL)/sizeof(mmDAC_CRC_SIG_CONTROL[0]), 0, 0 },
+	{ "mmDAC_SYNC_TRISTATE_CONTROL", REG_MMIO, 0x16b2, &mmDAC_SYNC_TRISTATE_CONTROL[0], sizeof(mmDAC_SYNC_TRISTATE_CONTROL)/sizeof(mmDAC_SYNC_TRISTATE_CONTROL[0]), 0, 0 },
+	{ "mmDAC_STEREOSYNC_SELECT", REG_MMIO, 0x16b3, &mmDAC_STEREOSYNC_SELECT[0], sizeof(mmDAC_STEREOSYNC_SELECT)/sizeof(mmDAC_STEREOSYNC_SELECT[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL", REG_MMIO, 0x16b4, &mmDAC_AUTODETECT_CONTROL[0], sizeof(mmDAC_AUTODETECT_CONTROL)/sizeof(mmDAC_AUTODETECT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL2", REG_MMIO, 0x16b5, &mmDAC_AUTODETECT_CONTROL2[0], sizeof(mmDAC_AUTODETECT_CONTROL2)/sizeof(mmDAC_AUTODETECT_CONTROL2[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL3", REG_MMIO, 0x16b6, &mmDAC_AUTODETECT_CONTROL3[0], sizeof(mmDAC_AUTODETECT_CONTROL3)/sizeof(mmDAC_AUTODETECT_CONTROL3[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_STATUS", REG_MMIO, 0x16b7, &mmDAC_AUTODETECT_STATUS[0], sizeof(mmDAC_AUTODETECT_STATUS)/sizeof(mmDAC_AUTODETECT_STATUS[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_INT_CONTROL", REG_MMIO, 0x16b8, &mmDAC_AUTODETECT_INT_CONTROL[0], sizeof(mmDAC_AUTODETECT_INT_CONTROL)/sizeof(mmDAC_AUTODETECT_INT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_FORCE_OUTPUT_CNTL", REG_MMIO, 0x16b9, &mmDAC_FORCE_OUTPUT_CNTL[0], sizeof(mmDAC_FORCE_OUTPUT_CNTL)/sizeof(mmDAC_FORCE_OUTPUT_CNTL[0]), 0, 0 },
+	{ "mmDAC_FORCE_DATA", REG_MMIO, 0x16ba, &mmDAC_FORCE_DATA[0], sizeof(mmDAC_FORCE_DATA)/sizeof(mmDAC_FORCE_DATA[0]), 0, 0 },
+	{ "mmDAC_POWERDOWN", REG_MMIO, 0x16bb, &mmDAC_POWERDOWN[0], sizeof(mmDAC_POWERDOWN)/sizeof(mmDAC_POWERDOWN[0]), 0, 0 },
+	{ "mmDAC_CONTROL", REG_MMIO, 0x16bc, &mmDAC_CONTROL[0], sizeof(mmDAC_CONTROL)/sizeof(mmDAC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_ENABLE", REG_MMIO, 0x16bd, &mmDAC_COMPARATOR_ENABLE[0], sizeof(mmDAC_COMPARATOR_ENABLE)/sizeof(mmDAC_COMPARATOR_ENABLE[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_OUTPUT", REG_MMIO, 0x16be, &mmDAC_COMPARATOR_OUTPUT[0], sizeof(mmDAC_COMPARATOR_OUTPUT)/sizeof(mmDAC_COMPARATOR_OUTPUT[0]), 0, 0 },
+	{ "mmDAC_PWR_CNTL", REG_MMIO, 0x16bf, &mmDAC_PWR_CNTL[0], sizeof(mmDAC_PWR_CNTL)/sizeof(mmDAC_PWR_CNTL[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_PHASE", REG_MMIO, 0x16c, &mmDCCG_AUDIO_DTO0_PHASE[0], sizeof(mmDCCG_AUDIO_DTO0_PHASE)/sizeof(mmDCCG_AUDIO_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDAC_DFT_CONFIG", REG_MMIO, 0x16c0, &mmDAC_DFT_CONFIG[0], sizeof(mmDAC_DFT_CONFIG)/sizeof(mmDAC_DFT_CONFIG[0]), 0, 0 },
+	{ "mmDAC_FIFO_STATUS", REG_MMIO, 0x16c1, &mmDAC_FIFO_STATUS[0], sizeof(mmDAC_FIFO_STATUS)/sizeof(mmDAC_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDAC_TEST_DEBUG_INDEX", REG_MMIO, 0x16c2, &mmDAC_TEST_DEBUG_INDEX[0], sizeof(mmDAC_TEST_DEBUG_INDEX)/sizeof(mmDAC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDAC_TEST_DEBUG_DATA", REG_MMIO, 0x16c3, &mmDAC_TEST_DEBUG_DATA[0], sizeof(mmDAC_TEST_DEBUG_DATA)/sizeof(mmDAC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK1_SEL", REG_MMIO, 0x16c4, &mmDCDEBUG_BUS_CLK1_SEL[0], sizeof(mmDCDEBUG_BUS_CLK1_SEL)/sizeof(mmDCDEBUG_BUS_CLK1_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK2_SEL", REG_MMIO, 0x16c5, &mmDCDEBUG_BUS_CLK2_SEL[0], sizeof(mmDCDEBUG_BUS_CLK2_SEL)/sizeof(mmDCDEBUG_BUS_CLK2_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK3_SEL", REG_MMIO, 0x16c6, &mmDCDEBUG_BUS_CLK3_SEL[0], sizeof(mmDCDEBUG_BUS_CLK3_SEL)/sizeof(mmDCDEBUG_BUS_CLK3_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK4_SEL", REG_MMIO, 0x16c7, &mmDCDEBUG_BUS_CLK4_SEL[0], sizeof(mmDCDEBUG_BUS_CLK4_SEL)/sizeof(mmDCDEBUG_BUS_CLK4_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK5_SEL", REG_MMIO, 0x16c8, &mmDCDEBUG_BUS_CLK5_SEL[0], sizeof(mmDCDEBUG_BUS_CLK5_SEL)/sizeof(mmDCDEBUG_BUS_CLK5_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_PIN_OVERRIDE", REG_MMIO, 0x16c9, &mmDCDEBUG_OUT_PIN_OVERRIDE[0], sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE)/sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_CNTL", REG_MMIO, 0x16ca, &mmDCDEBUG_OUT_CNTL[0], sizeof(mmDCDEBUG_OUT_CNTL)/sizeof(mmDCDEBUG_OUT_CNTL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_DATA", REG_MMIO, 0x16cb, &mmDCDEBUG_OUT_DATA[0], sizeof(mmDCDEBUG_OUT_DATA)/sizeof(mmDCDEBUG_OUT_DATA[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_MODULE", REG_MMIO, 0x16d, &mmDCCG_AUDIO_DTO0_MODULE[0], sizeof(mmDCCG_AUDIO_DTO0_MODULE)/sizeof(mmDCCG_AUDIO_DTO0_MODULE[0]), 0, 0 },
+	{ "mmDC_I2C_CONTROL", REG_MMIO, 0x16d4, &mmDC_I2C_CONTROL[0], sizeof(mmDC_I2C_CONTROL)/sizeof(mmDC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_ARBITRATION", REG_MMIO, 0x16d5, &mmDC_I2C_ARBITRATION[0], sizeof(mmDC_I2C_ARBITRATION)/sizeof(mmDC_I2C_ARBITRATION[0]), 0, 0 },
+	{ "mmDC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x16d6, &mmDC_I2C_INTERRUPT_CONTROL[0], sizeof(mmDC_I2C_INTERRUPT_CONTROL)/sizeof(mmDC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_SW_STATUS", REG_MMIO, 0x16d7, &mmDC_I2C_SW_STATUS[0], sizeof(mmDC_I2C_SW_STATUS)/sizeof(mmDC_I2C_SW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_HW_STATUS", REG_MMIO, 0x16d8, &mmDC_I2C_DDC1_HW_STATUS[0], sizeof(mmDC_I2C_DDC1_HW_STATUS)/sizeof(mmDC_I2C_DDC1_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_HW_STATUS", REG_MMIO, 0x16d9, &mmDC_I2C_DDC2_HW_STATUS[0], sizeof(mmDC_I2C_DDC2_HW_STATUS)/sizeof(mmDC_I2C_DDC2_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_HW_STATUS", REG_MMIO, 0x16da, &mmDC_I2C_DDC3_HW_STATUS[0], sizeof(mmDC_I2C_DDC3_HW_STATUS)/sizeof(mmDC_I2C_DDC3_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_HW_STATUS", REG_MMIO, 0x16db, &mmDC_I2C_DDC4_HW_STATUS[0], sizeof(mmDC_I2C_DDC4_HW_STATUS)/sizeof(mmDC_I2C_DDC4_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_HW_STATUS", REG_MMIO, 0x16dc, &mmDC_I2C_DDC5_HW_STATUS[0], sizeof(mmDC_I2C_DDC5_HW_STATUS)/sizeof(mmDC_I2C_DDC5_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_HW_STATUS", REG_MMIO, 0x16dd, &mmDC_I2C_DDC6_HW_STATUS[0], sizeof(mmDC_I2C_DDC6_HW_STATUS)/sizeof(mmDC_I2C_DDC6_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SPEED", REG_MMIO, 0x16de, &mmDC_I2C_DDC1_SPEED[0], sizeof(mmDC_I2C_DDC1_SPEED)/sizeof(mmDC_I2C_DDC1_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SETUP", REG_MMIO, 0x16df, &mmDC_I2C_DDC1_SETUP[0], sizeof(mmDC_I2C_DDC1_SETUP)/sizeof(mmDC_I2C_DDC1_SETUP[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_PHASE", REG_MMIO, 0x16e, &mmDCCG_AUDIO_DTO1_PHASE[0], sizeof(mmDCCG_AUDIO_DTO1_PHASE)/sizeof(mmDCCG_AUDIO_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SPEED", REG_MMIO, 0x16e0, &mmDC_I2C_DDC2_SPEED[0], sizeof(mmDC_I2C_DDC2_SPEED)/sizeof(mmDC_I2C_DDC2_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SETUP", REG_MMIO, 0x16e1, &mmDC_I2C_DDC2_SETUP[0], sizeof(mmDC_I2C_DDC2_SETUP)/sizeof(mmDC_I2C_DDC2_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SPEED", REG_MMIO, 0x16e2, &mmDC_I2C_DDC3_SPEED[0], sizeof(mmDC_I2C_DDC3_SPEED)/sizeof(mmDC_I2C_DDC3_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SETUP", REG_MMIO, 0x16e3, &mmDC_I2C_DDC3_SETUP[0], sizeof(mmDC_I2C_DDC3_SETUP)/sizeof(mmDC_I2C_DDC3_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SPEED", REG_MMIO, 0x16e4, &mmDC_I2C_DDC4_SPEED[0], sizeof(mmDC_I2C_DDC4_SPEED)/sizeof(mmDC_I2C_DDC4_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SETUP", REG_MMIO, 0x16e5, &mmDC_I2C_DDC4_SETUP[0], sizeof(mmDC_I2C_DDC4_SETUP)/sizeof(mmDC_I2C_DDC4_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SPEED", REG_MMIO, 0x16e6, &mmDC_I2C_DDC5_SPEED[0], sizeof(mmDC_I2C_DDC5_SPEED)/sizeof(mmDC_I2C_DDC5_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SETUP", REG_MMIO, 0x16e7, &mmDC_I2C_DDC5_SETUP[0], sizeof(mmDC_I2C_DDC5_SETUP)/sizeof(mmDC_I2C_DDC5_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SPEED", REG_MMIO, 0x16e8, &mmDC_I2C_DDC6_SPEED[0], sizeof(mmDC_I2C_DDC6_SPEED)/sizeof(mmDC_I2C_DDC6_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SETUP", REG_MMIO, 0x16e9, &mmDC_I2C_DDC6_SETUP[0], sizeof(mmDC_I2C_DDC6_SETUP)/sizeof(mmDC_I2C_DDC6_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION0", REG_MMIO, 0x16ea, &mmDC_I2C_TRANSACTION0[0], sizeof(mmDC_I2C_TRANSACTION0)/sizeof(mmDC_I2C_TRANSACTION0[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION1", REG_MMIO, 0x16eb, &mmDC_I2C_TRANSACTION1[0], sizeof(mmDC_I2C_TRANSACTION1)/sizeof(mmDC_I2C_TRANSACTION1[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION2", REG_MMIO, 0x16ec, &mmDC_I2C_TRANSACTION2[0], sizeof(mmDC_I2C_TRANSACTION2)/sizeof(mmDC_I2C_TRANSACTION2[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION3", REG_MMIO, 0x16ed, &mmDC_I2C_TRANSACTION3[0], sizeof(mmDC_I2C_TRANSACTION3)/sizeof(mmDC_I2C_TRANSACTION3[0]), 0, 0 },
+	{ "mmDC_I2C_DATA", REG_MMIO, 0x16ee, &mmDC_I2C_DATA[0], sizeof(mmDC_I2C_DATA)/sizeof(mmDC_I2C_DATA[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_HW_STATUS", REG_MMIO, 0x16ef, &mmDC_I2C_DDCVGA_HW_STATUS[0], sizeof(mmDC_I2C_DDCVGA_HW_STATUS)/sizeof(mmDC_I2C_DDCVGA_HW_STATUS[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_MODULE", REG_MMIO, 0x16f, &mmDCCG_AUDIO_DTO1_MODULE[0], sizeof(mmDCCG_AUDIO_DTO1_MODULE)/sizeof(mmDCCG_AUDIO_DTO1_MODULE[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SPEED", REG_MMIO, 0x16f0, &mmDC_I2C_DDCVGA_SPEED[0], sizeof(mmDC_I2C_DDCVGA_SPEED)/sizeof(mmDC_I2C_DDCVGA_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SETUP", REG_MMIO, 0x16f1, &mmDC_I2C_DDCVGA_SETUP[0], sizeof(mmDC_I2C_DDCVGA_SETUP)/sizeof(mmDC_I2C_DDCVGA_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_EDID_DETECT_CTRL", REG_MMIO, 0x16f2, &mmDC_I2C_EDID_DETECT_CTRL[0], sizeof(mmDC_I2C_EDID_DETECT_CTRL)/sizeof(mmDC_I2C_EDID_DETECT_CTRL[0]), 0, 0 },
+	{ "mmDC_I2C_READ_REQUEST_INTERRUPT", REG_MMIO, 0x16f3, &mmDC_I2C_READ_REQUEST_INTERRUPT[0], sizeof(mmDC_I2C_READ_REQUEST_INTERRUPT)/sizeof(mmDC_I2C_READ_REQUEST_INTERRUPT[0]), 0, 0 },
+	{ "mmGENERIC_I2C_CONTROL", REG_MMIO, 0x16f4, &mmGENERIC_I2C_CONTROL[0], sizeof(mmGENERIC_I2C_CONTROL)/sizeof(mmGENERIC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x16f5, &mmGENERIC_I2C_INTERRUPT_CONTROL[0], sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL)/sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_STATUS", REG_MMIO, 0x16f6, &mmGENERIC_I2C_STATUS[0], sizeof(mmGENERIC_I2C_STATUS)/sizeof(mmGENERIC_I2C_STATUS[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SPEED", REG_MMIO, 0x16f7, &mmGENERIC_I2C_SPEED[0], sizeof(mmGENERIC_I2C_SPEED)/sizeof(mmGENERIC_I2C_SPEED[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SETUP", REG_MMIO, 0x16f8, &mmGENERIC_I2C_SETUP[0], sizeof(mmGENERIC_I2C_SETUP)/sizeof(mmGENERIC_I2C_SETUP[0]), 0, 0 },
+	{ "mmGENERIC_I2C_TRANSACTION", REG_MMIO, 0x16f9, &mmGENERIC_I2C_TRANSACTION[0], sizeof(mmGENERIC_I2C_TRANSACTION)/sizeof(mmGENERIC_I2C_TRANSACTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_DATA", REG_MMIO, 0x16fa, &mmGENERIC_I2C_DATA[0], sizeof(mmGENERIC_I2C_DATA)/sizeof(mmGENERIC_I2C_DATA[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_SELECTION", REG_MMIO, 0x16fb, &mmGENERIC_I2C_PIN_SELECTION[0], sizeof(mmGENERIC_I2C_PIN_SELECTION)/sizeof(mmGENERIC_I2C_PIN_SELECTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_DEBUG", REG_MMIO, 0x16fc, &mmGENERIC_I2C_PIN_DEBUG[0], sizeof(mmGENERIC_I2C_PIN_DEBUG)/sizeof(mmGENERIC_I2C_PIN_DEBUG[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_H", REG_SMC, 0x17, &ixDP_AUX_DEBUG_H[0], sizeof(ixDP_AUX_DEBUG_H)/sizeof(ixDP_AUX_DEBUG_H[0]), 0, 0 },
+	{ "mmRIRB_CONTROL", REG_MMIO, 0x17, &mmRIRB_CONTROL[0], sizeof(mmRIRB_CONTROL)/sizeof(mmRIRB_CONTROL[0]), 0, 0 },
+	{ "mmRIRB_STATUS", REG_MMIO, 0x17, &mmRIRB_STATUS[0], sizeof(mmRIRB_STATUS)/sizeof(mmRIRB_STATUS[0]), 0, 0 },
+	{ "mmRIRB_SIZE", REG_MMIO, 0x17, &mmRIRB_SIZE[0], sizeof(mmRIRB_SIZE)/sizeof(mmRIRB_SIZE[0]), 0, 0 },
+	{ "ixCRT17", REG_SMC, 0x17, &ixCRT17[0], sizeof(ixCRT17)/sizeof(ixCRT17[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFCOUNTER_CNTL", REG_MMIO, 0x170, NULL, 0, 0, 0 },
+	{ "mmPERFCOUNTER_CNTL", REG_MMIO, 0x170, &mmPERFCOUNTER_CNTL[0], sizeof(mmPERFCOUNTER_CNTL)/sizeof(mmPERFCOUNTER_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1700, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1700, &mmPLL_MACRO_CNTL_RESERVED0[0], sizeof(mmPLL_MACRO_CNTL_RESERVED0)/sizeof(mmPLL_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_REF_DIV", REG_MMIO, 0x1700, NULL, 0, 0, 0 },
+	{ "mmPLL_REF_DIV", REG_MMIO, 0x1700, &mmPLL_REF_DIV[0], sizeof(mmPLL_REF_DIV)/sizeof(mmPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1701, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1701, &mmPLL_MACRO_CNTL_RESERVED1[0], sizeof(mmPLL_MACRO_CNTL_RESERVED1)/sizeof(mmPLL_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_FB_DIV", REG_MMIO, 0x1701, NULL, 0, 0, 0 },
+	{ "mmPLL_FB_DIV", REG_MMIO, 0x1701, &mmPLL_FB_DIV[0], sizeof(mmPLL_FB_DIV)/sizeof(mmPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1702, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1702, &mmPLL_MACRO_CNTL_RESERVED2[0], sizeof(mmPLL_MACRO_CNTL_RESERVED2)/sizeof(mmPLL_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_POST_DIV", REG_MMIO, 0x1702, NULL, 0, 0, 0 },
+	{ "mmPLL_POST_DIV", REG_MMIO, 0x1702, &mmPLL_POST_DIV[0], sizeof(mmPLL_POST_DIV)/sizeof(mmPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1703, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1703, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1703, &mmPLL_MACRO_CNTL_RESERVED3[0], sizeof(mmPLL_MACRO_CNTL_RESERVED3)/sizeof(mmPLL_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmPLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1703, &mmPLL_SS_AMOUNT_DSFRAC[0], sizeof(mmPLL_SS_AMOUNT_DSFRAC)/sizeof(mmPLL_SS_AMOUNT_DSFRAC[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1704, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1704, &mmPLL_MACRO_CNTL_RESERVED4[0], sizeof(mmPLL_MACRO_CNTL_RESERVED4)/sizeof(mmPLL_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_SS_CNTL", REG_MMIO, 0x1704, NULL, 0, 0, 0 },
+	{ "mmPLL_SS_CNTL", REG_MMIO, 0x1704, &mmPLL_SS_CNTL[0], sizeof(mmPLL_SS_CNTL)/sizeof(mmPLL_SS_CNTL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_SMC, 0x1705, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1705, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1705, &mmPLL_MACRO_CNTL_RESERVED5[0], sizeof(mmPLL_MACRO_CNTL_RESERVED5)/sizeof(mmPLL_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_DS_CNTL", REG_MMIO, 0x1705, NULL, 0, 0, 0 },
+	{ "mmPLL_DS_CNTL", REG_MMIO, 0x1705, &mmPLL_DS_CNTL[0], sizeof(mmPLL_DS_CNTL)/sizeof(mmPLL_DS_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1706, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_IDCLK_CNTL", REG_MMIO, 0x1706, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1706, &mmPLL_MACRO_CNTL_RESERVED6[0], sizeof(mmPLL_MACRO_CNTL_RESERVED6)/sizeof(mmPLL_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmPLL_IDCLK_CNTL", REG_MMIO, 0x1706, &mmPLL_IDCLK_CNTL[0], sizeof(mmPLL_IDCLK_CNTL)/sizeof(mmPLL_IDCLK_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1707, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1707, &mmPLL_MACRO_CNTL_RESERVED7[0], sizeof(mmPLL_MACRO_CNTL_RESERVED7)/sizeof(mmPLL_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_CNTL", REG_MMIO, 0x1707, NULL, 0, 0, 0 },
+	{ "mmPLL_CNTL", REG_MMIO, 0x1707, &mmPLL_CNTL[0], sizeof(mmPLL_CNTL)/sizeof(mmPLL_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1708, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1708, &mmPLL_MACRO_CNTL_RESERVED8[0], sizeof(mmPLL_MACRO_CNTL_RESERVED8)/sizeof(mmPLL_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_ANALOG", REG_MMIO, 0x1708, NULL, 0, 0, 0 },
+	{ "mmPLL_ANALOG", REG_MMIO, 0x1708, &mmPLL_ANALOG[0], sizeof(mmPLL_ANALOG)/sizeof(mmPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1709, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1709, &mmPLL_MACRO_CNTL_RESERVED9[0], sizeof(mmPLL_MACRO_CNTL_RESERVED9)/sizeof(mmPLL_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmPLL_VREG_CNTL", REG_MMIO, 0x1709, &mmPLL_VREG_CNTL[0], sizeof(mmPLL_VREG_CNTL)/sizeof(mmPLL_VREG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x170a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x170a, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x170a, &mmPLL_MACRO_CNTL_RESERVED10[0], sizeof(mmPLL_MACRO_CNTL_RESERVED10)/sizeof(mmPLL_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmPLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x170a, &mmPLL_UNLOCK_DETECT_CNTL[0], sizeof(mmPLL_UNLOCK_DETECT_CNTL)/sizeof(mmPLL_UNLOCK_DETECT_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x170b, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x170b, &mmPLL_MACRO_CNTL_RESERVED11[0], sizeof(mmPLL_MACRO_CNTL_RESERVED11)/sizeof(mmPLL_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmPLL_DEBUG_CNTL", REG_MMIO, 0x170b, &mmPLL_DEBUG_CNTL[0], sizeof(mmPLL_DEBUG_CNTL)/sizeof(mmPLL_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x170c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_UPDATE_LOCK", REG_MMIO, 0x170c, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x170c, &mmPLL_MACRO_CNTL_RESERVED12[0], sizeof(mmPLL_MACRO_CNTL_RESERVED12)/sizeof(mmPLL_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmPLL_UPDATE_LOCK", REG_MMIO, 0x170c, &mmPLL_UPDATE_LOCK[0], sizeof(mmPLL_UPDATE_LOCK)/sizeof(mmPLL_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x170d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_UPDATE_CNTL", REG_MMIO, 0x170d, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x170d, &mmPLL_MACRO_CNTL_RESERVED13[0], sizeof(mmPLL_MACRO_CNTL_RESERVED13)/sizeof(mmPLL_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmPLL_UPDATE_CNTL", REG_MMIO, 0x170d, &mmPLL_UPDATE_CNTL[0], sizeof(mmPLL_UPDATE_CNTL)/sizeof(mmPLL_UPDATE_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x170e, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x170e, &mmPLL_MACRO_CNTL_RESERVED14[0], sizeof(mmPLL_MACRO_CNTL_RESERVED14)/sizeof(mmPLL_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x170f, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x170f, &mmPLL_MACRO_CNTL_RESERVED15[0], sizeof(mmPLL_MACRO_CNTL_RESERVED15)/sizeof(mmPLL_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFCOUNTER_STATE", REG_MMIO, 0x171, NULL, 0, 0, 0 },
+	{ "mmPERFCOUNTER_STATE", REG_MMIO, 0x171, &mmPERFCOUNTER_STATE[0], sizeof(mmPERFCOUNTER_STATE)/sizeof(mmPERFCOUNTER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1710, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1710, &mmPLL_MACRO_CNTL_RESERVED16[0], sizeof(mmPLL_MACRO_CNTL_RESERVED16)/sizeof(mmPLL_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_XOR_LOCK", REG_MMIO, 0x1710, NULL, 0, 0, 0 },
+	{ "mmPLL_XOR_LOCK", REG_MMIO, 0x1710, &mmPLL_XOR_LOCK[0], sizeof(mmPLL_XOR_LOCK)/sizeof(mmPLL_XOR_LOCK[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1711, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_ANALOG_CNTL", REG_MMIO, 0x1711, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1711, &mmPLL_MACRO_CNTL_RESERVED17[0], sizeof(mmPLL_MACRO_CNTL_RESERVED17)/sizeof(mmPLL_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmPLL_ANALOG_CNTL", REG_MMIO, 0x1711, &mmPLL_ANALOG_CNTL[0], sizeof(mmPLL_ANALOG_CNTL)/sizeof(mmPLL_ANALOG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1712, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA25_PPLL_REF_DIV", REG_MMIO, 0x1712, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1712, &mmPLL_MACRO_CNTL_RESERVED18[0], sizeof(mmPLL_MACRO_CNTL_RESERVED18)/sizeof(mmPLL_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmVGA25_PPLL_REF_DIV", REG_MMIO, 0x1712, &mmVGA25_PPLL_REF_DIV[0], sizeof(mmVGA25_PPLL_REF_DIV)/sizeof(mmVGA25_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1713, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA28_PPLL_REF_DIV", REG_MMIO, 0x1713, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1713, &mmPLL_MACRO_CNTL_RESERVED19[0], sizeof(mmPLL_MACRO_CNTL_RESERVED19)/sizeof(mmPLL_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmVGA28_PPLL_REF_DIV", REG_MMIO, 0x1713, &mmVGA28_PPLL_REF_DIV[0], sizeof(mmVGA28_PPLL_REF_DIV)/sizeof(mmVGA28_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1714, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA41_PPLL_REF_DIV", REG_MMIO, 0x1714, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1714, &mmPLL_MACRO_CNTL_RESERVED20[0], sizeof(mmPLL_MACRO_CNTL_RESERVED20)/sizeof(mmPLL_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmVGA41_PPLL_REF_DIV", REG_MMIO, 0x1714, &mmVGA41_PPLL_REF_DIV[0], sizeof(mmVGA41_PPLL_REF_DIV)/sizeof(mmVGA41_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1715, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA25_PPLL_FB_DIV", REG_MMIO, 0x1715, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1715, &mmPLL_MACRO_CNTL_RESERVED21[0], sizeof(mmPLL_MACRO_CNTL_RESERVED21)/sizeof(mmPLL_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmVGA25_PPLL_FB_DIV", REG_MMIO, 0x1715, &mmVGA25_PPLL_FB_DIV[0], sizeof(mmVGA25_PPLL_FB_DIV)/sizeof(mmVGA25_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1716, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA28_PPLL_FB_DIV", REG_MMIO, 0x1716, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1716, &mmPLL_MACRO_CNTL_RESERVED22[0], sizeof(mmPLL_MACRO_CNTL_RESERVED22)/sizeof(mmPLL_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmVGA28_PPLL_FB_DIV", REG_MMIO, 0x1716, &mmVGA28_PPLL_FB_DIV[0], sizeof(mmVGA28_PPLL_FB_DIV)/sizeof(mmVGA28_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1717, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA41_PPLL_FB_DIV", REG_MMIO, 0x1717, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1717, &mmPLL_MACRO_CNTL_RESERVED23[0], sizeof(mmPLL_MACRO_CNTL_RESERVED23)/sizeof(mmPLL_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmVGA41_PPLL_FB_DIV", REG_MMIO, 0x1717, &mmVGA41_PPLL_FB_DIV[0], sizeof(mmVGA41_PPLL_FB_DIV)/sizeof(mmVGA41_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1718, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA25_PPLL_POST_DIV", REG_MMIO, 0x1718, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1718, &mmPLL_MACRO_CNTL_RESERVED24[0], sizeof(mmPLL_MACRO_CNTL_RESERVED24)/sizeof(mmPLL_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmVGA25_PPLL_POST_DIV", REG_MMIO, 0x1718, &mmVGA25_PPLL_POST_DIV[0], sizeof(mmVGA25_PPLL_POST_DIV)/sizeof(mmVGA25_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1719, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA28_PPLL_POST_DIV", REG_MMIO, 0x1719, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1719, &mmPLL_MACRO_CNTL_RESERVED25[0], sizeof(mmPLL_MACRO_CNTL_RESERVED25)/sizeof(mmPLL_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmVGA28_PPLL_POST_DIV", REG_MMIO, 0x1719, &mmVGA28_PPLL_POST_DIV[0], sizeof(mmVGA28_PPLL_POST_DIV)/sizeof(mmVGA28_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x171a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA41_PPLL_POST_DIV", REG_MMIO, 0x171a, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x171a, &mmPLL_MACRO_CNTL_RESERVED26[0], sizeof(mmPLL_MACRO_CNTL_RESERVED26)/sizeof(mmPLL_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmVGA41_PPLL_POST_DIV", REG_MMIO, 0x171a, &mmVGA41_PPLL_POST_DIV[0], sizeof(mmVGA41_PPLL_POST_DIV)/sizeof(mmVGA41_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x171b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA25_PPLL_ANALOG", REG_MMIO, 0x171b, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x171b, &mmPLL_MACRO_CNTL_RESERVED27[0], sizeof(mmPLL_MACRO_CNTL_RESERVED27)/sizeof(mmPLL_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmVGA25_PPLL_ANALOG", REG_MMIO, 0x171b, &mmVGA25_PPLL_ANALOG[0], sizeof(mmVGA25_PPLL_ANALOG)/sizeof(mmVGA25_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x171c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA28_PPLL_ANALOG", REG_MMIO, 0x171c, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x171c, &mmPLL_MACRO_CNTL_RESERVED28[0], sizeof(mmPLL_MACRO_CNTL_RESERVED28)/sizeof(mmPLL_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmVGA28_PPLL_ANALOG", REG_MMIO, 0x171c, &mmVGA28_PPLL_ANALOG[0], sizeof(mmVGA28_PPLL_ANALOG)/sizeof(mmVGA28_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x171d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA41_PPLL_ANALOG", REG_MMIO, 0x171d, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x171d, &mmPLL_MACRO_CNTL_RESERVED29[0], sizeof(mmPLL_MACRO_CNTL_RESERVED29)/sizeof(mmPLL_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmVGA41_PPLL_ANALOG", REG_MMIO, 0x171d, &mmVGA41_PPLL_ANALOG[0], sizeof(mmVGA41_PPLL_ANALOG)/sizeof(mmVGA41_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x171e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_DISPPLL_BG_CNTL", REG_MMIO, 0x171e, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x171e, &mmPLL_MACRO_CNTL_RESERVED30[0], sizeof(mmPLL_MACRO_CNTL_RESERVED30)/sizeof(mmPLL_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDISPPLL_BG_CNTL", REG_MMIO, 0x171e, &mmDISPPLL_BG_CNTL[0], sizeof(mmDISPPLL_BG_CNTL)/sizeof(mmDISPPLL_BG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x171f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x171f, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x171f, &mmPLL_MACRO_CNTL_RESERVED31[0], sizeof(mmPLL_MACRO_CNTL_RESERVED31)/sizeof(mmPLL_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmPPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x171f, &mmPPLL_DIV_UPDATE_DEBUG[0], sizeof(mmPPLL_DIV_UPDATE_DEBUG)/sizeof(mmPPLL_DIV_UPDATE_DEBUG[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x172, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CVALUE_INT_MISC", REG_MMIO, 0x172, &mmPERFMON_CVALUE_INT_MISC[0], sizeof(mmPERFMON_CVALUE_INT_MISC)/sizeof(mmPERFMON_CVALUE_INT_MISC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_SMC, 0x1720, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1720, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_STATUS_DEBUG", REG_MMIO, 0x1720, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1720, &mmPLL_MACRO_CNTL_RESERVED32[0], sizeof(mmPLL_MACRO_CNTL_RESERVED32)/sizeof(mmPLL_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmPPLL_STATUS_DEBUG", REG_MMIO, 0x1720, &mmPPLL_STATUS_DEBUG[0], sizeof(mmPPLL_STATUS_DEBUG)/sizeof(mmPPLL_STATUS_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2", REG_SMC, 0x1721, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1721, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1721, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1721, &mmPLL_MACRO_CNTL_RESERVED33[0], sizeof(mmPLL_MACRO_CNTL_RESERVED33)/sizeof(mmPLL_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmPPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1721, &mmPPLL_DEBUG_MUX_CNTL[0], sizeof(mmPPLL_DEBUG_MUX_CNTL)/sizeof(mmPPLL_DEBUG_MUX_CNTL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3", REG_SMC, 0x1722, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1722, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1722, &mmPLL_MACRO_CNTL_RESERVED34[0], sizeof(mmPLL_MACRO_CNTL_RESERVED34)/sizeof(mmPLL_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_SPARE0", REG_MMIO, 0x1722, NULL, 0, 0, 0 },
+	{ "mmPPLL_SPARE0", REG_MMIO, 0x1722, &mmPPLL_SPARE0[0], sizeof(mmPPLL_SPARE0)/sizeof(mmPPLL_SPARE0[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4", REG_SMC, 0x1723, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1723, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1723, &mmPLL_MACRO_CNTL_RESERVED35[0], sizeof(mmPLL_MACRO_CNTL_RESERVED35)/sizeof(mmPLL_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_SPARE1", REG_MMIO, 0x1723, NULL, 0, 0, 0 },
+	{ "mmPPLL_SPARE1", REG_MMIO, 0x1723, &mmPPLL_SPARE1[0], sizeof(mmPPLL_SPARE1)/sizeof(mmPPLL_SPARE1[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1724, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1724, &mmPLL_MACRO_CNTL_RESERVED36[0], sizeof(mmPLL_MACRO_CNTL_RESERVED36)/sizeof(mmPLL_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1725, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1725, &mmPLL_MACRO_CNTL_RESERVED37[0], sizeof(mmPLL_MACRO_CNTL_RESERVED37)/sizeof(mmPLL_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1726, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1726, &mmPLL_MACRO_CNTL_RESERVED38[0], sizeof(mmPLL_MACRO_CNTL_RESERVED38)/sizeof(mmPLL_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1727, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1727, &mmPLL_MACRO_CNTL_RESERVED39[0], sizeof(mmPLL_MACRO_CNTL_RESERVED39)/sizeof(mmPLL_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1728, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1728, &mmPLL_MACRO_CNTL_RESERVED40[0], sizeof(mmPLL_MACRO_CNTL_RESERVED40)/sizeof(mmPLL_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1729, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1729, &mmPLL_MACRO_CNTL_RESERVED41[0], sizeof(mmPLL_MACRO_CNTL_RESERVED41)/sizeof(mmPLL_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x172a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_REF_DIV", REG_MMIO, 0x172a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x172b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_FB_DIV", REG_MMIO, 0x172b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x172c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_POST_DIV", REG_MMIO, 0x172c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x172d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x172d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x172e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_SS_CNTL", REG_MMIO, 0x172e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x172f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_DS_CNTL", REG_MMIO, 0x172f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CNTL", REG_MMIO, 0x173, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CNTL", REG_MMIO, 0x173, &mmPERFMON_CNTL[0], sizeof(mmPERFMON_CNTL)/sizeof(mmPERFMON_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1730, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_IDCLK_CNTL", REG_MMIO, 0x1730, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1731, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_CNTL", REG_MMIO, 0x1731, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1732, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_ANALOG", REG_MMIO, 0x1732, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1733, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_VREG_CNTL", REG_MMIO, 0x1733, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x1734, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x1734, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x1735, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_DEBUG_CNTL", REG_MMIO, 0x1735, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x1736, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_UPDATE_LOCK", REG_MMIO, 0x1736, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x1737, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_UPDATE_CNTL", REG_MMIO, 0x1737, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x1738, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x1739, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x173a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_XOR_LOCK", REG_MMIO, 0x173a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x173b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_ANALOG_CNTL", REG_MMIO, 0x173b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x173c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA25_PPLL_REF_DIV", REG_MMIO, 0x173c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x173d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA28_PPLL_REF_DIV", REG_MMIO, 0x173d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x173e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA41_PPLL_REF_DIV", REG_MMIO, 0x173e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x173f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA25_PPLL_FB_DIV", REG_MMIO, 0x173f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CVALUE_LOW", REG_MMIO, 0x174, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CVALUE_LOW", REG_MMIO, 0x174, &mmPERFMON_CVALUE_LOW[0], sizeof(mmPERFMON_CVALUE_LOW)/sizeof(mmPERFMON_CVALUE_LOW[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1740, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA28_PPLL_FB_DIV", REG_MMIO, 0x1740, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1741, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA41_PPLL_FB_DIV", REG_MMIO, 0x1741, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1742, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA25_PPLL_POST_DIV", REG_MMIO, 0x1742, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1743, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA28_PPLL_POST_DIV", REG_MMIO, 0x1743, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x1744, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA41_PPLL_POST_DIV", REG_MMIO, 0x1744, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x1745, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA25_PPLL_ANALOG", REG_MMIO, 0x1745, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x1746, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA28_PPLL_ANALOG", REG_MMIO, 0x1746, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x1747, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA41_PPLL_ANALOG", REG_MMIO, 0x1747, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x1748, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_DISPPLL_BG_CNTL", REG_MMIO, 0x1748, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x1749, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x1749, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x174a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_STATUS_DEBUG", REG_MMIO, 0x174a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x174b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x174b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x174c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_SPARE0", REG_MMIO, 0x174c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x174d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_SPARE1", REG_MMIO, 0x174d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x174e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x174f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_HI", REG_MMIO, 0x175, NULL, 0, 0, 0 },
+	{ "mmPERFMON_HI", REG_MMIO, 0x175, &mmPERFMON_HI[0], sizeof(mmPERFMON_HI)/sizeof(mmPERFMON_HI[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1750, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1751, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1752, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1753, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1754, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_REF_DIV", REG_MMIO, 0x1754, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1755, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_FB_DIV", REG_MMIO, 0x1755, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1756, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_POST_DIV", REG_MMIO, 0x1756, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1757, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1757, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1758, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_SS_CNTL", REG_MMIO, 0x1758, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1759, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_DS_CNTL", REG_MMIO, 0x1759, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x175a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_IDCLK_CNTL", REG_MMIO, 0x175a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x175b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_CNTL", REG_MMIO, 0x175b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x175c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_ANALOG", REG_MMIO, 0x175c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x175d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_VREG_CNTL", REG_MMIO, 0x175d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x175e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x175e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x175f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_DEBUG_CNTL", REG_MMIO, 0x175f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_LOW", REG_MMIO, 0x176, NULL, 0, 0, 0 },
+	{ "mmPERFMON_LOW", REG_MMIO, 0x176, &mmPERFMON_LOW[0], sizeof(mmPERFMON_LOW)/sizeof(mmPERFMON_LOW[0]), 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x1760, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_UPDATE_LOCK", REG_MMIO, 0x1760, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x1761, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_UPDATE_CNTL", REG_MMIO, 0x1761, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x1762, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x1763, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1764, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_XOR_LOCK", REG_MMIO, 0x1764, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1765, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_ANALOG_CNTL", REG_MMIO, 0x1765, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1766, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA25_PPLL_REF_DIV", REG_MMIO, 0x1766, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1767, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA28_PPLL_REF_DIV", REG_MMIO, 0x1767, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1768, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA41_PPLL_REF_DIV", REG_MMIO, 0x1768, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1769, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA25_PPLL_FB_DIV", REG_MMIO, 0x1769, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x176a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA28_PPLL_FB_DIV", REG_MMIO, 0x176a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x176b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA41_PPLL_FB_DIV", REG_MMIO, 0x176b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x176c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA25_PPLL_POST_DIV", REG_MMIO, 0x176c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x176d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA28_PPLL_POST_DIV", REG_MMIO, 0x176d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x176e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA41_PPLL_POST_DIV", REG_MMIO, 0x176e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x176f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA25_PPLL_ANALOG", REG_MMIO, 0x176f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x177, NULL, 0, 0, 0 },
+	{ "mmPERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x177, &mmPERFMON_TEST_DEBUG_INDEX[0], sizeof(mmPERFMON_TEST_DEBUG_INDEX)/sizeof(mmPERFMON_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_SMC, 0x1770, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x1770, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA28_PPLL_ANALOG", REG_MMIO, 0x1770, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x1771, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA41_PPLL_ANALOG", REG_MMIO, 0x1771, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x1772, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_DISPPLL_BG_CNTL", REG_MMIO, 0x1772, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x1773, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x1773, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1774, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_STATUS_DEBUG", REG_MMIO, 0x1774, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1775, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1775, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1776, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_SPARE0", REG_MMIO, 0x1776, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1777, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_SPARE1", REG_MMIO, 0x1777, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1778, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1779, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x177a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x177b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x177c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x177d, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x178, NULL, 0, 0, 0 },
+	{ "mmPERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x178, &mmPERFMON_TEST_DEBUG_DATA[0], sizeof(mmPERFMON_TEST_DEBUG_DATA)/sizeof(mmPERFMON_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZF0STREAM0_AZALIA_STREAM_INDEX", REG_MMIO, 0x1780, NULL, 0, 0, 0 },
+	{ "mmAZALIA_STREAM_INDEX", REG_MMIO, 0x1780, &mmAZALIA_STREAM_INDEX[0], sizeof(mmAZALIA_STREAM_INDEX)/sizeof(mmAZALIA_STREAM_INDEX[0]), 0, 0 },
+	{ "mmAZF0STREAM0_AZALIA_STREAM_DATA", REG_MMIO, 0x1781, NULL, 0, 0, 0 },
+	{ "mmAZALIA_STREAM_DATA", REG_MMIO, 0x1781, &mmAZALIA_STREAM_DATA[0], sizeof(mmAZALIA_STREAM_DATA)/sizeof(mmAZALIA_STREAM_DATA[0]), 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_INDEX", REG_MMIO, 0x1782, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_DATA", REG_MMIO, 0x1783, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_INDEX", REG_MMIO, 0x1784, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_DATA", REG_MMIO, 0x1785, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_INDEX", REG_MMIO, 0x1786, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_DATA", REG_MMIO, 0x1787, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_INDEX", REG_MMIO, 0x1788, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_DATA", REG_MMIO, 0x1789, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_INDEX", REG_MMIO, 0x178a, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_DATA", REG_MMIO, 0x178b, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM6_AZALIA_STREAM_INDEX", REG_MMIO, 0x178c, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM6_AZALIA_STREAM_DATA", REG_MMIO, 0x178d, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM7_AZALIA_STREAM_INDEX", REG_MMIO, 0x178e, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM7_AZALIA_STREAM_DATA", REG_MMIO, 0x178f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CNTL2", REG_MMIO, 0x17a, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CNTL2", REG_MMIO, 0x17a, &mmPERFMON_CNTL2[0], sizeof(mmPERFMON_CNTL2)/sizeof(mmPERFMON_CNTL2[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17a8, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17a8, &mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17a9, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17a9, &mmAZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17ac, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17ad, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b0, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b1, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b4, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b5, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b8, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b9, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17bc, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17bd, NULL, 0, 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_INDEX", REG_MMIO, 0x17c, &mmDCCG_TEST_DEBUG_INDEX[0], sizeof(mmDCCG_TEST_DEBUG_INDEX)/sizeof(mmDCCG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17c0, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17c1, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17c4, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17c5, NULL, 0, 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_DATA", REG_MMIO, 0x17d, &mmDCCG_TEST_DEBUG_DATA[0], sizeof(mmDCCG_TEST_DEBUG_DATA)/sizeof(mmDCCG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCCG_TEST_CLK_SEL", REG_MMIO, 0x17e, &mmDCCG_TEST_CLK_SEL[0], sizeof(mmDCCG_TEST_CLK_SEL)/sizeof(mmDCCG_TEST_CLK_SEL[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_CLOCK_GATING", REG_MMIO, 0x17e4, &mmAZALIA_CONTROLLER_CLOCK_GATING[0], sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING)/sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO", REG_MMIO, 0x17e5, &mmAZALIA_AUDIO_DTO[0], sizeof(mmAZALIA_AUDIO_DTO)/sizeof(mmAZALIA_AUDIO_DTO[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO_CONTROL", REG_MMIO, 0x17e6, &mmAZALIA_AUDIO_DTO_CONTROL[0], sizeof(mmAZALIA_AUDIO_DTO_CONTROL)/sizeof(mmAZALIA_AUDIO_DTO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_SCLK_CONTROL", REG_MMIO, 0x17e7, &mmAZALIA_SCLK_CONTROL[0], sizeof(mmAZALIA_SCLK_CONTROL)/sizeof(mmAZALIA_SCLK_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_UNDERFLOW_FILLER_SAMPLE", REG_MMIO, 0x17e8, &mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0], sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE)/sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0]), 0, 0 },
+	{ "mmAZALIA_DATA_DMA_CONTROL", REG_MMIO, 0x17e9, &mmAZALIA_DATA_DMA_CONTROL[0], sizeof(mmAZALIA_DATA_DMA_CONTROL)/sizeof(mmAZALIA_DATA_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_BDL_DMA_CONTROL", REG_MMIO, 0x17ea, &mmAZALIA_BDL_DMA_CONTROL[0], sizeof(mmAZALIA_BDL_DMA_CONTROL)/sizeof(mmAZALIA_BDL_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_RIRB_AND_DP_CONTROL", REG_MMIO, 0x17eb, &mmAZALIA_RIRB_AND_DP_CONTROL[0], sizeof(mmAZALIA_RIRB_AND_DP_CONTROL)/sizeof(mmAZALIA_RIRB_AND_DP_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_CORB_DMA_CONTROL", REG_MMIO, 0x17ec, &mmAZALIA_CORB_DMA_CONTROL[0], sizeof(mmAZALIA_CORB_DMA_CONTROL)/sizeof(mmAZALIA_CORB_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER", REG_MMIO, 0x17f3, &mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0], sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER)/sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0]), 0, 0 },
+	{ "mmAZALIA_CYCLIC_BUFFER_SYNC", REG_MMIO, 0x17f4, &mmAZALIA_CYCLIC_BUFFER_SYNC[0], sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC)/sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC[0]), 0, 0 },
+	{ "mmAZALIA_GLOBAL_CAPABILITIES", REG_MMIO, 0x17f5, &mmAZALIA_GLOBAL_CAPABILITIES[0], sizeof(mmAZALIA_GLOBAL_CAPABILITIES)/sizeof(mmAZALIA_GLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x17f6, &mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL", REG_MMIO, 0x17f7, &mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0], sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL)/sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x17f8, &mmAZALIA_INPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_INPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_INPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_DEBUG", REG_MMIO, 0x17f9, &mmAZALIA_CONTROLLER_DEBUG[0], sizeof(mmAZALIA_CONTROLLER_DEBUG)/sizeof(mmAZALIA_CONTROLLER_DEBUG[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL0", REG_MMIO, 0x17fb, &mmAZALIA_INPUT_CRC0_CONTROL0[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL0)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL1", REG_MMIO, 0x17fc, &mmAZALIA_INPUT_CRC0_CONTROL1[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL1)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL2", REG_MMIO, 0x17fd, &mmAZALIA_INPUT_CRC0_CONTROL2[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL2)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL3", REG_MMIO, 0x17fe, &mmAZALIA_INPUT_CRC0_CONTROL3[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL3)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET", REG_SMC, 0x17ff, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_RESULT", REG_MMIO, 0x17ff, &mmAZALIA_INPUT_CRC0_RESULT[0], sizeof(mmAZALIA_INPUT_CRC0_RESULT)/sizeof(mmAZALIA_INPUT_CRC0_RESULT[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_I", REG_SMC, 0x18, &ixDP_AUX_DEBUG_I[0], sizeof(ixDP_AUX_DEBUG_I)/sizeof(ixDP_AUX_DEBUG_I[0]), 0, 0 },
+	{ "ixCRT18", REG_SMC, 0x18, &ixCRT18[0], sizeof(ixCRT18)/sizeof(ixCRT18[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL0", REG_MMIO, 0x1800, &mmAZALIA_INPUT_CRC1_CONTROL0[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL0)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL1", REG_MMIO, 0x1801, &mmAZALIA_INPUT_CRC1_CONTROL1[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL1)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL2", REG_MMIO, 0x1802, &mmAZALIA_INPUT_CRC1_CONTROL2[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL2)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL3", REG_MMIO, 0x1803, &mmAZALIA_INPUT_CRC1_CONTROL3[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL3)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_RESULT", REG_MMIO, 0x1804, &mmAZALIA_INPUT_CRC1_RESULT[0], sizeof(mmAZALIA_INPUT_CRC1_RESULT)/sizeof(mmAZALIA_INPUT_CRC1_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL0", REG_MMIO, 0x1805, &mmAZALIA_CRC0_CONTROL0[0], sizeof(mmAZALIA_CRC0_CONTROL0)/sizeof(mmAZALIA_CRC0_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL1", REG_MMIO, 0x1806, &mmAZALIA_CRC0_CONTROL1[0], sizeof(mmAZALIA_CRC0_CONTROL1)/sizeof(mmAZALIA_CRC0_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL2", REG_MMIO, 0x1807, &mmAZALIA_CRC0_CONTROL2[0], sizeof(mmAZALIA_CRC0_CONTROL2)/sizeof(mmAZALIA_CRC0_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL3", REG_MMIO, 0x1808, &mmAZALIA_CRC0_CONTROL3[0], sizeof(mmAZALIA_CRC0_CONTROL3)/sizeof(mmAZALIA_CRC0_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_RESULT", REG_MMIO, 0x1809, &mmAZALIA_CRC0_RESULT[0], sizeof(mmAZALIA_CRC0_RESULT)/sizeof(mmAZALIA_CRC0_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL0", REG_MMIO, 0x180a, &mmAZALIA_CRC1_CONTROL0[0], sizeof(mmAZALIA_CRC1_CONTROL0)/sizeof(mmAZALIA_CRC1_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL1", REG_MMIO, 0x180b, &mmAZALIA_CRC1_CONTROL1[0], sizeof(mmAZALIA_CRC1_CONTROL1)/sizeof(mmAZALIA_CRC1_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL2", REG_MMIO, 0x180c, &mmAZALIA_CRC1_CONTROL2[0], sizeof(mmAZALIA_CRC1_CONTROL2)/sizeof(mmAZALIA_CRC1_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL3", REG_MMIO, 0x180d, &mmAZALIA_CRC1_CONTROL3[0], sizeof(mmAZALIA_CRC1_CONTROL3)/sizeof(mmAZALIA_CRC1_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_RESULT", REG_MMIO, 0x180e, &mmAZALIA_CRC1_RESULT[0], sizeof(mmAZALIA_CRC1_RESULT)/sizeof(mmAZALIA_CRC1_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_MEM_PWR_CTRL", REG_MMIO, 0x1810, &mmAZALIA_MEM_PWR_CTRL[0], sizeof(mmAZALIA_MEM_PWR_CTRL)/sizeof(mmAZALIA_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmAZALIA_MEM_PWR_STATUS", REG_MMIO, 0x1811, &mmAZALIA_MEM_PWR_STATUS[0], sizeof(mmAZALIA_MEM_PWR_STATUS)/sizeof(mmAZALIA_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCI_PG_DEBUG_CONFIG", REG_MMIO, 0x1812, &mmDCI_PG_DEBUG_CONFIG[0], sizeof(mmDCI_PG_DEBUG_CONFIG)/sizeof(mmDCI_PG_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_INDEX", REG_MMIO, 0x181f, &mmAZ_TEST_DEBUG_INDEX[0], sizeof(mmAZ_TEST_DEBUG_INDEX)/sizeof(mmAZ_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_DATA", REG_MMIO, 0x1820, &mmAZ_TEST_DEBUG_DATA[0], sizeof(mmAZ_TEST_DEBUG_DATA)/sizeof(mmAZ_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_MMIO, 0x1828, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID", REG_MMIO, 0x1829, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL", REG_MMIO, 0x182a, &mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL)/sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL", REG_MMIO, 0x182b, &mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL)/sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_MMIO, 0x182c, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_MMIO, 0x182d, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_MMIO, 0x182e, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_MMIO, 0x182f, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_MMIO, 0x1830, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET", REG_MMIO, 0x1831, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_MMIO, 0x1832, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_MMIO, 0x1833, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY", REG_MMIO, 0x1834, &mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0]), 0, 0 },
+	{ "mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY", REG_MMIO, 0x1835, &mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_DEBUG", REG_MMIO, 0x1836, &mmAZALIA_F0_CODEC_DEBUG[0], sizeof(mmAZALIA_F0_CODEC_DEBUG)/sizeof(mmAZALIA_F0_CODEC_DEBUG[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET0", REG_MMIO, 0x1837, &mmAZALIA_F0_GTC_GROUP_OFFSET0[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET1", REG_MMIO, 0x1838, &mmAZALIA_F0_GTC_GROUP_OFFSET1[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET2", REG_MMIO, 0x1839, &mmAZALIA_F0_GTC_GROUP_OFFSET2[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET3", REG_MMIO, 0x183a, &mmAZALIA_F0_GTC_GROUP_OFFSET3[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET4", REG_MMIO, 0x183b, &mmAZALIA_F0_GTC_GROUP_OFFSET4[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET5", REG_MMIO, 0x183c, &mmAZALIA_F0_GTC_GROUP_OFFSET5[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET6", REG_MMIO, 0x183d, &mmAZALIA_F0_GTC_GROUP_OFFSET6[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6[0]), 0, 0 },
+	{ "mmDCO_SCRATCH0", REG_MMIO, 0x184e, &mmDCO_SCRATCH0[0], sizeof(mmDCO_SCRATCH0)/sizeof(mmDCO_SCRATCH0[0]), 0, 0 },
+	{ "mmDCO_SCRATCH1", REG_MMIO, 0x184f, &mmDCO_SCRATCH1[0], sizeof(mmDCO_SCRATCH1)/sizeof(mmDCO_SCRATCH1[0]), 0, 0 },
+	{ "mmDCO_SCRATCH2", REG_MMIO, 0x1850, &mmDCO_SCRATCH2[0], sizeof(mmDCO_SCRATCH2)/sizeof(mmDCO_SCRATCH2[0]), 0, 0 },
+	{ "mmDCO_SCRATCH3", REG_MMIO, 0x1851, &mmDCO_SCRATCH3[0], sizeof(mmDCO_SCRATCH3)/sizeof(mmDCO_SCRATCH3[0]), 0, 0 },
+	{ "mmDCO_SCRATCH4", REG_MMIO, 0x1852, &mmDCO_SCRATCH4[0], sizeof(mmDCO_SCRATCH4)/sizeof(mmDCO_SCRATCH4[0]), 0, 0 },
+	{ "mmDCO_SCRATCH5", REG_MMIO, 0x1853, &mmDCO_SCRATCH5[0], sizeof(mmDCO_SCRATCH5)/sizeof(mmDCO_SCRATCH5[0]), 0, 0 },
+	{ "mmDCO_SCRATCH6", REG_MMIO, 0x1854, &mmDCO_SCRATCH6[0], sizeof(mmDCO_SCRATCH6)/sizeof(mmDCO_SCRATCH6[0]), 0, 0 },
+	{ "mmDCO_SCRATCH7", REG_MMIO, 0x1855, &mmDCO_SCRATCH7[0], sizeof(mmDCO_SCRATCH7)/sizeof(mmDCO_SCRATCH7[0]), 0, 0 },
+	{ "mmDCE_VCE_CONTROL", REG_MMIO, 0x1856, &mmDCE_VCE_CONTROL[0], sizeof(mmDCE_VCE_CONTROL)/sizeof(mmDCE_VCE_CONTROL[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS", REG_MMIO, 0x1857, &mmDISP_INTERRUPT_STATUS[0], sizeof(mmDISP_INTERRUPT_STATUS)/sizeof(mmDISP_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE", REG_MMIO, 0x1858, &mmDISP_INTERRUPT_STATUS_CONTINUE[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE2", REG_MMIO, 0x1859, &mmDISP_INTERRUPT_STATUS_CONTINUE2[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE3", REG_MMIO, 0x185a, &mmDISP_INTERRUPT_STATUS_CONTINUE3[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE4", REG_MMIO, 0x185b, &mmDISP_INTERRUPT_STATUS_CONTINUE4[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE5", REG_MMIO, 0x185c, &mmDISP_INTERRUPT_STATUS_CONTINUE5[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE6", REG_MMIO, 0x185d, &mmDISP_INTERRUPT_STATUS_CONTINUE6[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE7", REG_MMIO, 0x185e, &mmDISP_INTERRUPT_STATUS_CONTINUE7[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE8", REG_MMIO, 0x185f, &mmDISP_INTERRUPT_STATUS_CONTINUE8[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE9", REG_MMIO, 0x1860, &mmDISP_INTERRUPT_STATUS_CONTINUE9[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_STATUS", REG_MMIO, 0x1861, &mmDCO_MEM_PWR_STATUS[0], sizeof(mmDCO_MEM_PWR_STATUS)/sizeof(mmDCO_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_CTRL", REG_MMIO, 0x1862, &mmDCO_MEM_PWR_CTRL[0], sizeof(mmDCO_MEM_PWR_CTRL)/sizeof(mmDCO_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_CTRL2", REG_MMIO, 0x1863, &mmDCO_MEM_PWR_CTRL2[0], sizeof(mmDCO_MEM_PWR_CTRL2)/sizeof(mmDCO_MEM_PWR_CTRL2[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL", REG_MMIO, 0x1864, &mmDCO_CLK_CNTL[0], sizeof(mmDCO_CLK_CNTL)/sizeof(mmDCO_CLK_CNTL[0]), 0, 0 },
+	{ "mmDCO_CLK_RAMP_CNTL", REG_MMIO, 0x1865, &mmDCO_CLK_RAMP_CNTL[0], sizeof(mmDCO_CLK_RAMP_CNTL)/sizeof(mmDCO_CLK_RAMP_CNTL[0]), 0, 0 },
+	{ "mmDPDBG_CNTL", REG_MMIO, 0x1866, &mmDPDBG_CNTL[0], sizeof(mmDPDBG_CNTL)/sizeof(mmDPDBG_CNTL[0]), 0, 0 },
+	{ "mmDPDBG_INTERRUPT", REG_MMIO, 0x1867, &mmDPDBG_INTERRUPT[0], sizeof(mmDPDBG_INTERRUPT)/sizeof(mmDPDBG_INTERRUPT[0]), 0, 0 },
+	{ "mmDCO_POWER_MANAGEMENT_CNTL", REG_MMIO, 0x1868, &mmDCO_POWER_MANAGEMENT_CNTL[0], sizeof(mmDCO_POWER_MANAGEMENT_CNTL)/sizeof(mmDCO_POWER_MANAGEMENT_CNTL[0]), 0, 0 },
+	{ "mmDCO_STEREOSYNC_SEL", REG_MMIO, 0x186e, &mmDCO_STEREOSYNC_SEL[0], sizeof(mmDCO_STEREOSYNC_SEL)/sizeof(mmDCO_STEREOSYNC_SEL[0]), 0, 0 },
+	{ "mmDCO_TEST_DEBUG_INDEX", REG_MMIO, 0x186f, &mmDCO_TEST_DEBUG_INDEX[0], sizeof(mmDCO_TEST_DEBUG_INDEX)/sizeof(mmDCO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCO_TEST_DEBUG_DATA", REG_MMIO, 0x1870, &mmDCO_TEST_DEBUG_DATA[0], sizeof(mmDCO_TEST_DEBUG_DATA)/sizeof(mmDCO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCO_SOFT_RESET", REG_MMIO, 0x1871, &mmDCO_SOFT_RESET[0], sizeof(mmDCO_SOFT_RESET)/sizeof(mmDCO_SOFT_RESET[0]), 0, 0 },
+	{ "mmDIG_SOFT_RESET", REG_MMIO, 0x1872, &mmDIG_SOFT_RESET[0], sizeof(mmDIG_SOFT_RESET)/sizeof(mmDIG_SOFT_RESET[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_INT_STATUS", REG_MMIO, 0x1898, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_INT_STATUS", REG_MMIO, 0x1898, &mmDC_HPD_INT_STATUS[0], sizeof(mmDC_HPD_INT_STATUS)/sizeof(mmDC_HPD_INT_STATUS[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_INT_CONTROL", REG_MMIO, 0x1899, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_INT_CONTROL", REG_MMIO, 0x1899, &mmDC_HPD_INT_CONTROL[0], sizeof(mmDC_HPD_INT_CONTROL)/sizeof(mmDC_HPD_INT_CONTROL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_CONTROL", REG_MMIO, 0x189a, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_CONTROL", REG_MMIO, 0x189a, &mmDC_HPD_CONTROL[0], sizeof(mmDC_HPD_CONTROL)/sizeof(mmDC_HPD_CONTROL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x189b, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x189b, &mmDC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x189c, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x189c, &mmDC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmHPD1_DC_HPD_INT_STATUS", REG_MMIO, 0x18a0, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_INT_CONTROL", REG_MMIO, 0x18a1, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_CONTROL", REG_MMIO, 0x18a2, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18a3, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18a4, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_INT_STATUS", REG_MMIO, 0x18a8, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_INT_CONTROL", REG_MMIO, 0x18a9, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_CONTROL", REG_MMIO, 0x18aa, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18ab, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18ac, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_INT_STATUS", REG_MMIO, 0x18b0, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_INT_CONTROL", REG_MMIO, 0x18b1, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_CONTROL", REG_MMIO, 0x18b2, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18b3, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18b4, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_INT_STATUS", REG_MMIO, 0x18b8, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_INT_CONTROL", REG_MMIO, 0x18b9, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_CONTROL", REG_MMIO, 0x18ba, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18bb, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18bc, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_INT_STATUS", REG_MMIO, 0x18c0, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_INT_CONTROL", REG_MMIO, 0x18c1, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_CONTROL", REG_MMIO, 0x18c2, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18c3, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18c4, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFCOUNTER_CNTL", REG_MMIO, 0x18c8, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFCOUNTER_STATE", REG_MMIO, 0x18c9, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x18ca, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CNTL", REG_MMIO, 0x18cb, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CVALUE_LOW", REG_MMIO, 0x18cc, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_HI", REG_MMIO, 0x18cd, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_LOW", REG_MMIO, 0x18ce, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x18cf, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x18d0, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CNTL2", REG_MMIO, 0x18d2, NULL, 0, 0, 0 },
+	{ "mmIMMEDIATE_RESPONSE_INPUT_INTERFACE", REG_MMIO, 0x19, &mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0], sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE)/sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_J", REG_SMC, 0x19, &ixDP_AUX_DEBUG_J[0], sizeof(ixDP_AUX_DEBUG_J)/sizeof(ixDP_AUX_DEBUG_J[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_STATUS", REG_MMIO, 0x1a, &mmIMMEDIATE_COMMAND_STATUS[0], sizeof(mmIMMEDIATE_COMMAND_STATUS)/sizeof(mmIMMEDIATE_COMMAND_STATUS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_K", REG_SMC, 0x1a, &ixDP_AUX_DEBUG_K[0], sizeof(ixDP_AUX_DEBUG_K)/sizeof(ixDP_AUX_DEBUG_K[0]), 0, 0 },
+	{ "mmDCP0_GRPH_ENABLE", REG_MMIO, 0x1a00, NULL, 0, 0, 0 },
+	{ "mmGRPH_ENABLE", REG_MMIO, 0x1a00, &mmGRPH_ENABLE[0], sizeof(mmGRPH_ENABLE)/sizeof(mmGRPH_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_CONTROL", REG_MMIO, 0x1a01, NULL, 0, 0, 0 },
+	{ "mmGRPH_CONTROL", REG_MMIO, 0x1a01, &mmGRPH_CONTROL[0], sizeof(mmGRPH_CONTROL)/sizeof(mmGRPH_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1a02, NULL, 0, 0, 0 },
+	{ "mmGRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1a02, &mmGRPH_LUT_10BIT_BYPASS[0], sizeof(mmGRPH_LUT_10BIT_BYPASS)/sizeof(mmGRPH_LUT_10BIT_BYPASS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SWAP_CNTL", REG_MMIO, 0x1a03, NULL, 0, 0, 0 },
+	{ "mmGRPH_SWAP_CNTL", REG_MMIO, 0x1a03, &mmGRPH_SWAP_CNTL[0], sizeof(mmGRPH_SWAP_CNTL)/sizeof(mmGRPH_SWAP_CNTL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1a04, NULL, 0, 0, 0 },
+	{ "mmGRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1a04, &mmGRPH_PRIMARY_SURFACE_ADDRESS[0], sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS)/sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a05, NULL, 0, 0, 0 },
+	{ "mmGRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a05, &mmGRPH_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS)/sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PITCH", REG_MMIO, 0x1a06, NULL, 0, 0, 0 },
+	{ "mmGRPH_PITCH", REG_MMIO, 0x1a06, &mmGRPH_PITCH[0], sizeof(mmGRPH_PITCH)/sizeof(mmGRPH_PITCH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a07, NULL, 0, 0, 0 },
+	{ "mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a07, &mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a08, NULL, 0, 0, 0 },
+	{ "mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a08, &mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1a09, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1a09, &mmGRPH_SURFACE_OFFSET_X[0], sizeof(mmGRPH_SURFACE_OFFSET_X)/sizeof(mmGRPH_SURFACE_OFFSET_X[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1a0a, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1a0a, &mmGRPH_SURFACE_OFFSET_Y[0], sizeof(mmGRPH_SURFACE_OFFSET_Y)/sizeof(mmGRPH_SURFACE_OFFSET_Y[0]), 0, 0 },
+	{ "mmDCP0_GRPH_X_START", REG_MMIO, 0x1a0b, NULL, 0, 0, 0 },
+	{ "mmGRPH_X_START", REG_MMIO, 0x1a0b, &mmGRPH_X_START[0], sizeof(mmGRPH_X_START)/sizeof(mmGRPH_X_START[0]), 0, 0 },
+	{ "mmDCP0_GRPH_Y_START", REG_MMIO, 0x1a0c, NULL, 0, 0, 0 },
+	{ "mmGRPH_Y_START", REG_MMIO, 0x1a0c, &mmGRPH_Y_START[0], sizeof(mmGRPH_Y_START)/sizeof(mmGRPH_Y_START[0]), 0, 0 },
+	{ "mmDCP0_GRPH_X_END", REG_MMIO, 0x1a0d, NULL, 0, 0, 0 },
+	{ "mmGRPH_X_END", REG_MMIO, 0x1a0d, &mmGRPH_X_END[0], sizeof(mmGRPH_X_END)/sizeof(mmGRPH_X_END[0]), 0, 0 },
+	{ "mmDCP0_GRPH_Y_END", REG_MMIO, 0x1a0e, NULL, 0, 0, 0 },
+	{ "mmGRPH_Y_END", REG_MMIO, 0x1a0e, &mmGRPH_Y_END[0], sizeof(mmGRPH_Y_END)/sizeof(mmGRPH_Y_END[0]), 0, 0 },
+	{ "mmDCP0_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1a10, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_CONTROL", REG_MMIO, 0x1a10, &mmINPUT_GAMMA_CONTROL[0], sizeof(mmINPUT_GAMMA_CONTROL)/sizeof(mmINPUT_GAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_UPDATE", REG_MMIO, 0x1a11, NULL, 0, 0, 0 },
+	{ "mmGRPH_UPDATE", REG_MMIO, 0x1a11, &mmGRPH_UPDATE[0], sizeof(mmGRPH_UPDATE)/sizeof(mmGRPH_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_CONTROL", REG_MMIO, 0x1a12, NULL, 0, 0, 0 },
+	{ "mmGRPH_FLIP_CONTROL", REG_MMIO, 0x1a12, &mmGRPH_FLIP_CONTROL[0], sizeof(mmGRPH_FLIP_CONTROL)/sizeof(mmGRPH_FLIP_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a13, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a13, &mmGRPH_SURFACE_ADDRESS_INUSE[0], sizeof(mmGRPH_SURFACE_ADDRESS_INUSE)/sizeof(mmGRPH_SURFACE_ADDRESS_INUSE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_CONTROL", REG_MMIO, 0x1a14, NULL, 0, 0, 0 },
+	{ "mmGRPH_DFQ_CONTROL", REG_MMIO, 0x1a14, &mmGRPH_DFQ_CONTROL[0], sizeof(mmGRPH_DFQ_CONTROL)/sizeof(mmGRPH_DFQ_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_STATUS", REG_MMIO, 0x1a15, NULL, 0, 0, 0 },
+	{ "mmGRPH_DFQ_STATUS", REG_MMIO, 0x1a15, &mmGRPH_DFQ_STATUS[0], sizeof(mmGRPH_DFQ_STATUS)/sizeof(mmGRPH_DFQ_STATUS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1a16, NULL, 0, 0, 0 },
+	{ "mmGRPH_INTERRUPT_STATUS", REG_MMIO, 0x1a16, &mmGRPH_INTERRUPT_STATUS[0], sizeof(mmGRPH_INTERRUPT_STATUS)/sizeof(mmGRPH_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1a17, NULL, 0, 0, 0 },
+	{ "mmGRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1a17, &mmGRPH_INTERRUPT_CONTROL[0], sizeof(mmGRPH_INTERRUPT_CONTROL)/sizeof(mmGRPH_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a18, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a18, &mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[0], sizeof(mmGRPH_SURFACE_ADDRESS_HIGH_INUSE)/sizeof(mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1a19, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1a19, &mmGRPH_COMPRESS_SURFACE_ADDRESS[0], sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS)/sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1a1a, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_PITCH", REG_MMIO, 0x1a1a, &mmGRPH_COMPRESS_PITCH[0], sizeof(mmGRPH_COMPRESS_PITCH)/sizeof(mmGRPH_COMPRESS_PITCH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a1b, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a1b, &mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_OVL_ENABLE", REG_MMIO, 0x1a1c, NULL, 0, 0, 0 },
+	{ "mmOVL_ENABLE", REG_MMIO, 0x1a1c, &mmOVL_ENABLE[0], sizeof(mmOVL_ENABLE)/sizeof(mmOVL_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_OVL_CONTROL1", REG_MMIO, 0x1a1d, NULL, 0, 0, 0 },
+	{ "mmOVL_CONTROL1", REG_MMIO, 0x1a1d, &mmOVL_CONTROL1[0], sizeof(mmOVL_CONTROL1)/sizeof(mmOVL_CONTROL1[0]), 0, 0 },
+	{ "mmDCP0_OVL_CONTROL2", REG_MMIO, 0x1a1e, NULL, 0, 0, 0 },
+	{ "mmOVL_CONTROL2", REG_MMIO, 0x1a1e, &mmOVL_CONTROL2[0], sizeof(mmOVL_CONTROL2)/sizeof(mmOVL_CONTROL2[0]), 0, 0 },
+	{ "mmDCP0_OVL_SWAP_CNTL", REG_MMIO, 0x1a1f, NULL, 0, 0, 0 },
+	{ "mmOVL_SWAP_CNTL", REG_MMIO, 0x1a1f, &mmOVL_SWAP_CNTL[0], sizeof(mmOVL_SWAP_CNTL)/sizeof(mmOVL_SWAP_CNTL[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS", REG_MMIO, 0x1a20, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_ADDRESS", REG_MMIO, 0x1a20, &mmOVL_SURFACE_ADDRESS[0], sizeof(mmOVL_SURFACE_ADDRESS)/sizeof(mmOVL_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_OVL_PITCH", REG_MMIO, 0x1a21, NULL, 0, 0, 0 },
+	{ "mmOVL_PITCH", REG_MMIO, 0x1a21, &mmOVL_PITCH[0], sizeof(mmOVL_PITCH)/sizeof(mmOVL_PITCH[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a22, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a22, &mmOVL_SURFACE_ADDRESS_HIGH[0], sizeof(mmOVL_SURFACE_ADDRESS_HIGH)/sizeof(mmOVL_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x1a23, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_OFFSET_X", REG_MMIO, 0x1a23, &mmOVL_SURFACE_OFFSET_X[0], sizeof(mmOVL_SURFACE_OFFSET_X)/sizeof(mmOVL_SURFACE_OFFSET_X[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1a24, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1a24, &mmOVL_SURFACE_OFFSET_Y[0], sizeof(mmOVL_SURFACE_OFFSET_Y)/sizeof(mmOVL_SURFACE_OFFSET_Y[0]), 0, 0 },
+	{ "mmDCP0_OVL_START", REG_MMIO, 0x1a25, NULL, 0, 0, 0 },
+	{ "mmOVL_START", REG_MMIO, 0x1a25, &mmOVL_START[0], sizeof(mmOVL_START)/sizeof(mmOVL_START[0]), 0, 0 },
+	{ "mmDCP0_OVL_END", REG_MMIO, 0x1a26, NULL, 0, 0, 0 },
+	{ "mmOVL_END", REG_MMIO, 0x1a26, &mmOVL_END[0], sizeof(mmOVL_END)/sizeof(mmOVL_END[0]), 0, 0 },
+	{ "mmDCP0_OVL_UPDATE", REG_MMIO, 0x1a27, NULL, 0, 0, 0 },
+	{ "mmOVL_UPDATE", REG_MMIO, 0x1a27, &mmOVL_UPDATE[0], sizeof(mmOVL_UPDATE)/sizeof(mmOVL_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a28, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a28, &mmOVL_SURFACE_ADDRESS_INUSE[0], sizeof(mmOVL_SURFACE_ADDRESS_INUSE)/sizeof(mmOVL_SURFACE_ADDRESS_INUSE[0]), 0, 0 },
+	{ "mmDCP0_OVL_DFQ_CONTROL", REG_MMIO, 0x1a29, NULL, 0, 0, 0 },
+	{ "mmOVL_DFQ_CONTROL", REG_MMIO, 0x1a29, &mmOVL_DFQ_CONTROL[0], sizeof(mmOVL_DFQ_CONTROL)/sizeof(mmOVL_DFQ_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OVL_DFQ_STATUS", REG_MMIO, 0x1a2a, NULL, 0, 0, 0 },
+	{ "mmOVL_DFQ_STATUS", REG_MMIO, 0x1a2a, &mmOVL_DFQ_STATUS[0], sizeof(mmOVL_DFQ_STATUS)/sizeof(mmOVL_DFQ_STATUS[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a2b, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a2b, &mmOVL_SURFACE_ADDRESS_HIGH_INUSE[0], sizeof(mmOVL_SURFACE_ADDRESS_HIGH_INUSE)/sizeof(mmOVL_SURFACE_ADDRESS_HIGH_INUSE[0]), 0, 0 },
+	{ "mmDCP0_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1a2c, NULL, 0, 0, 0 },
+	{ "mmOVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1a2c, &mmOVLSCL_EDGE_PIXEL_CNTL[0], sizeof(mmOVLSCL_EDGE_PIXEL_CNTL)/sizeof(mmOVLSCL_EDGE_PIXEL_CNTL[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1a2d, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_GRPH_CONTROL", REG_MMIO, 0x1a2d, &mmPRESCALE_GRPH_CONTROL[0], sizeof(mmPRESCALE_GRPH_CONTROL)/sizeof(mmPRESCALE_GRPH_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1a2e, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1a2e, &mmPRESCALE_VALUES_GRPH_R[0], sizeof(mmPRESCALE_VALUES_GRPH_R)/sizeof(mmPRESCALE_VALUES_GRPH_R[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1a2f, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1a2f, &mmPRESCALE_VALUES_GRPH_G[0], sizeof(mmPRESCALE_VALUES_GRPH_G)/sizeof(mmPRESCALE_VALUES_GRPH_G[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1a30, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1a30, &mmPRESCALE_VALUES_GRPH_B[0], sizeof(mmPRESCALE_VALUES_GRPH_B)/sizeof(mmPRESCALE_VALUES_GRPH_B[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_OVL_CONTROL", REG_MMIO, 0x1a31, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_OVL_CONTROL", REG_MMIO, 0x1a31, &mmPRESCALE_OVL_CONTROL[0], sizeof(mmPRESCALE_OVL_CONTROL)/sizeof(mmPRESCALE_OVL_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1a32, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1a32, &mmPRESCALE_VALUES_OVL_CB[0], sizeof(mmPRESCALE_VALUES_OVL_CB)/sizeof(mmPRESCALE_VALUES_OVL_CB[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1a33, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1a33, &mmPRESCALE_VALUES_OVL_Y[0], sizeof(mmPRESCALE_VALUES_OVL_Y)/sizeof(mmPRESCALE_VALUES_OVL_Y[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1a34, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1a34, &mmPRESCALE_VALUES_OVL_CR[0], sizeof(mmPRESCALE_VALUES_OVL_CR)/sizeof(mmPRESCALE_VALUES_OVL_CR[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_CONTROL", REG_MMIO, 0x1a35, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_CONTROL", REG_MMIO, 0x1a35, &mmINPUT_CSC_CONTROL[0], sizeof(mmINPUT_CSC_CONTROL)/sizeof(mmINPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C11_C12", REG_MMIO, 0x1a36, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C11_C12", REG_MMIO, 0x1a36, &mmINPUT_CSC_C11_C12[0], sizeof(mmINPUT_CSC_C11_C12)/sizeof(mmINPUT_CSC_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C13_C14", REG_MMIO, 0x1a37, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C13_C14", REG_MMIO, 0x1a37, &mmINPUT_CSC_C13_C14[0], sizeof(mmINPUT_CSC_C13_C14)/sizeof(mmINPUT_CSC_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C21_C22", REG_MMIO, 0x1a38, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C21_C22", REG_MMIO, 0x1a38, &mmINPUT_CSC_C21_C22[0], sizeof(mmINPUT_CSC_C21_C22)/sizeof(mmINPUT_CSC_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C23_C24", REG_MMIO, 0x1a39, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C23_C24", REG_MMIO, 0x1a39, &mmINPUT_CSC_C23_C24[0], sizeof(mmINPUT_CSC_C23_C24)/sizeof(mmINPUT_CSC_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C31_C32", REG_MMIO, 0x1a3a, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C31_C32", REG_MMIO, 0x1a3a, &mmINPUT_CSC_C31_C32[0], sizeof(mmINPUT_CSC_C31_C32)/sizeof(mmINPUT_CSC_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C33_C34", REG_MMIO, 0x1a3b, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C33_C34", REG_MMIO, 0x1a3b, &mmINPUT_CSC_C33_C34[0], sizeof(mmINPUT_CSC_C33_C34)/sizeof(mmINPUT_CSC_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1a3c, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_CONTROL", REG_MMIO, 0x1a3c, &mmOUTPUT_CSC_CONTROL[0], sizeof(mmOUTPUT_CSC_CONTROL)/sizeof(mmOUTPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1a3d, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12", REG_MMIO, 0x1a3d, &mmOUTPUT_CSC_C11_C12[0], sizeof(mmOUTPUT_CSC_C11_C12)/sizeof(mmOUTPUT_CSC_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1a3e, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14", REG_MMIO, 0x1a3e, &mmOUTPUT_CSC_C13_C14[0], sizeof(mmOUTPUT_CSC_C13_C14)/sizeof(mmOUTPUT_CSC_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1a3f, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22", REG_MMIO, 0x1a3f, &mmOUTPUT_CSC_C21_C22[0], sizeof(mmOUTPUT_CSC_C21_C22)/sizeof(mmOUTPUT_CSC_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1a40, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24", REG_MMIO, 0x1a40, &mmOUTPUT_CSC_C23_C24[0], sizeof(mmOUTPUT_CSC_C23_C24)/sizeof(mmOUTPUT_CSC_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1a41, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32", REG_MMIO, 0x1a41, &mmOUTPUT_CSC_C31_C32[0], sizeof(mmOUTPUT_CSC_C31_C32)/sizeof(mmOUTPUT_CSC_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1a42, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34", REG_MMIO, 0x1a42, &mmOUTPUT_CSC_C33_C34[0], sizeof(mmOUTPUT_CSC_C33_C34)/sizeof(mmOUTPUT_CSC_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1a43, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1a43, &mmCOMM_MATRIXA_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXA_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXA_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1a44, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1a44, &mmCOMM_MATRIXA_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXA_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXA_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1a45, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1a45, &mmCOMM_MATRIXA_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXA_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXA_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1a46, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1a46, &mmCOMM_MATRIXA_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXA_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXA_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1a47, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1a47, &mmCOMM_MATRIXA_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXA_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXA_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1a48, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1a48, &mmCOMM_MATRIXA_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXA_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXA_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1a49, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1a49, &mmCOMM_MATRIXB_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXB_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXB_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1a4a, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1a4a, &mmCOMM_MATRIXB_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXB_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXB_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1a4b, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1a4b, &mmCOMM_MATRIXB_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXB_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXB_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1a4c, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1a4c, &mmCOMM_MATRIXB_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXB_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXB_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1a4d, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1a4d, &mmCOMM_MATRIXB_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXB_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXB_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1a4e, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1a4e, &mmCOMM_MATRIXB_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXB_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXB_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DENORM_CONTROL", REG_MMIO, 0x1a50, NULL, 0, 0, 0 },
+	{ "mmDENORM_CONTROL", REG_MMIO, 0x1a50, &mmDENORM_CONTROL[0], sizeof(mmDENORM_CONTROL)/sizeof(mmDENORM_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_ROUND_CONTROL", REG_MMIO, 0x1a51, NULL, 0, 0, 0 },
+	{ "mmOUT_ROUND_CONTROL", REG_MMIO, 0x1a51, &mmOUT_ROUND_CONTROL[0], sizeof(mmOUT_ROUND_CONTROL)/sizeof(mmOUT_ROUND_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1a52, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1a52, &mmOUT_CLAMP_CONTROL_R_CR[0], sizeof(mmOUT_CLAMP_CONTROL_R_CR)/sizeof(mmOUT_CLAMP_CONTROL_R_CR[0]), 0, 0 },
+	{ "mmDCP0_KEY_CONTROL", REG_MMIO, 0x1a53, NULL, 0, 0, 0 },
+	{ "mmKEY_CONTROL", REG_MMIO, 0x1a53, &mmKEY_CONTROL[0], sizeof(mmKEY_CONTROL)/sizeof(mmKEY_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_ALPHA", REG_MMIO, 0x1a54, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_ALPHA", REG_MMIO, 0x1a54, &mmKEY_RANGE_ALPHA[0], sizeof(mmKEY_RANGE_ALPHA)/sizeof(mmKEY_RANGE_ALPHA[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_RED", REG_MMIO, 0x1a55, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_RED", REG_MMIO, 0x1a55, &mmKEY_RANGE_RED[0], sizeof(mmKEY_RANGE_RED)/sizeof(mmKEY_RANGE_RED[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_GREEN", REG_MMIO, 0x1a56, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_GREEN", REG_MMIO, 0x1a56, &mmKEY_RANGE_GREEN[0], sizeof(mmKEY_RANGE_GREEN)/sizeof(mmKEY_RANGE_GREEN[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_BLUE", REG_MMIO, 0x1a57, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_BLUE", REG_MMIO, 0x1a57, &mmKEY_RANGE_BLUE[0], sizeof(mmKEY_RANGE_BLUE)/sizeof(mmKEY_RANGE_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DEGAMMA_CONTROL", REG_MMIO, 0x1a58, NULL, 0, 0, 0 },
+	{ "mmDEGAMMA_CONTROL", REG_MMIO, 0x1a58, &mmDEGAMMA_CONTROL[0], sizeof(mmDEGAMMA_CONTROL)/sizeof(mmDEGAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1a59, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_CONTROL", REG_MMIO, 0x1a59, &mmGAMUT_REMAP_CONTROL[0], sizeof(mmGAMUT_REMAP_CONTROL)/sizeof(mmGAMUT_REMAP_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1a5a, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C11_C12", REG_MMIO, 0x1a5a, &mmGAMUT_REMAP_C11_C12[0], sizeof(mmGAMUT_REMAP_C11_C12)/sizeof(mmGAMUT_REMAP_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1a5b, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C13_C14", REG_MMIO, 0x1a5b, &mmGAMUT_REMAP_C13_C14[0], sizeof(mmGAMUT_REMAP_C13_C14)/sizeof(mmGAMUT_REMAP_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1a5c, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C21_C22", REG_MMIO, 0x1a5c, &mmGAMUT_REMAP_C21_C22[0], sizeof(mmGAMUT_REMAP_C21_C22)/sizeof(mmGAMUT_REMAP_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1a5d, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C23_C24", REG_MMIO, 0x1a5d, &mmGAMUT_REMAP_C23_C24[0], sizeof(mmGAMUT_REMAP_C23_C24)/sizeof(mmGAMUT_REMAP_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1a5e, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C31_C32", REG_MMIO, 0x1a5e, &mmGAMUT_REMAP_C31_C32[0], sizeof(mmGAMUT_REMAP_C31_C32)/sizeof(mmGAMUT_REMAP_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1a5f, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C33_C34", REG_MMIO, 0x1a5f, &mmGAMUT_REMAP_C33_C34[0], sizeof(mmGAMUT_REMAP_C33_C34)/sizeof(mmGAMUT_REMAP_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1a60, NULL, 0, 0, 0 },
+	{ "mmDCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1a60, &mmDCP_SPATIAL_DITHER_CNTL[0], sizeof(mmDCP_SPATIAL_DITHER_CNTL)/sizeof(mmDCP_SPATIAL_DITHER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_DCP_RANDOM_SEEDS", REG_MMIO, 0x1a61, NULL, 0, 0, 0 },
+	{ "mmDCP_RANDOM_SEEDS", REG_MMIO, 0x1a61, &mmDCP_RANDOM_SEEDS[0], sizeof(mmDCP_RANDOM_SEEDS)/sizeof(mmDCP_RANDOM_SEEDS[0]), 0, 0 },
+	{ "mmDCP0_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1a65, NULL, 0, 0, 0 },
+	{ "mmDCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1a65, &mmDCP_FP_CONVERTED_FIELD[0], sizeof(mmDCP_FP_CONVERTED_FIELD)/sizeof(mmDCP_FP_CONVERTED_FIELD[0]), 0, 0 },
+	{ "mmDCP0_CUR_CONTROL", REG_MMIO, 0x1a66, NULL, 0, 0, 0 },
+	{ "mmCUR_CONTROL", REG_MMIO, 0x1a66, &mmCUR_CONTROL[0], sizeof(mmCUR_CONTROL)/sizeof(mmCUR_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1a67, NULL, 0, 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS", REG_MMIO, 0x1a67, &mmCUR_SURFACE_ADDRESS[0], sizeof(mmCUR_SURFACE_ADDRESS)/sizeof(mmCUR_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_CUR_SIZE", REG_MMIO, 0x1a68, NULL, 0, 0, 0 },
+	{ "mmCUR_SIZE", REG_MMIO, 0x1a68, &mmCUR_SIZE[0], sizeof(mmCUR_SIZE)/sizeof(mmCUR_SIZE[0]), 0, 0 },
+	{ "mmDCP0_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a69, NULL, 0, 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a69, &mmCUR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCUR_SURFACE_ADDRESS_HIGH)/sizeof(mmCUR_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_CUR_POSITION", REG_MMIO, 0x1a6a, NULL, 0, 0, 0 },
+	{ "mmCUR_POSITION", REG_MMIO, 0x1a6a, &mmCUR_POSITION[0], sizeof(mmCUR_POSITION)/sizeof(mmCUR_POSITION[0]), 0, 0 },
+	{ "mmDCP0_CUR_HOT_SPOT", REG_MMIO, 0x1a6b, NULL, 0, 0, 0 },
+	{ "mmCUR_HOT_SPOT", REG_MMIO, 0x1a6b, &mmCUR_HOT_SPOT[0], sizeof(mmCUR_HOT_SPOT)/sizeof(mmCUR_HOT_SPOT[0]), 0, 0 },
+	{ "mmDCP0_CUR_COLOR1", REG_MMIO, 0x1a6c, NULL, 0, 0, 0 },
+	{ "mmCUR_COLOR1", REG_MMIO, 0x1a6c, &mmCUR_COLOR1[0], sizeof(mmCUR_COLOR1)/sizeof(mmCUR_COLOR1[0]), 0, 0 },
+	{ "mmDCP0_CUR_COLOR2", REG_MMIO, 0x1a6d, NULL, 0, 0, 0 },
+	{ "mmCUR_COLOR2", REG_MMIO, 0x1a6d, &mmCUR_COLOR2[0], sizeof(mmCUR_COLOR2)/sizeof(mmCUR_COLOR2[0]), 0, 0 },
+	{ "mmDCP0_CUR_UPDATE", REG_MMIO, 0x1a6e, NULL, 0, 0, 0 },
+	{ "mmCUR_UPDATE", REG_MMIO, 0x1a6e, &mmCUR_UPDATE[0], sizeof(mmCUR_UPDATE)/sizeof(mmCUR_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_RW_MODE", REG_MMIO, 0x1a78, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_RW_MODE", REG_MMIO, 0x1a78, &mmDC_LUT_RW_MODE[0], sizeof(mmDC_LUT_RW_MODE)/sizeof(mmDC_LUT_RW_MODE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_RW_INDEX", REG_MMIO, 0x1a79, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_RW_INDEX", REG_MMIO, 0x1a79, &mmDC_LUT_RW_INDEX[0], sizeof(mmDC_LUT_RW_INDEX)/sizeof(mmDC_LUT_RW_INDEX[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1a7a, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_SEQ_COLOR", REG_MMIO, 0x1a7a, &mmDC_LUT_SEQ_COLOR[0], sizeof(mmDC_LUT_SEQ_COLOR)/sizeof(mmDC_LUT_SEQ_COLOR[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_PWL_DATA", REG_MMIO, 0x1a7b, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_PWL_DATA", REG_MMIO, 0x1a7b, &mmDC_LUT_PWL_DATA[0], sizeof(mmDC_LUT_PWL_DATA)/sizeof(mmDC_LUT_PWL_DATA[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_30_COLOR", REG_MMIO, 0x1a7c, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_30_COLOR", REG_MMIO, 0x1a7c, &mmDC_LUT_30_COLOR[0], sizeof(mmDC_LUT_30_COLOR)/sizeof(mmDC_LUT_30_COLOR[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1a7d, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1a7d, &mmDC_LUT_VGA_ACCESS_ENABLE[0], sizeof(mmDC_LUT_VGA_ACCESS_ENABLE)/sizeof(mmDC_LUT_VGA_ACCESS_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1a7e, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1a7e, &mmDC_LUT_WRITE_EN_MASK[0], sizeof(mmDC_LUT_WRITE_EN_MASK)/sizeof(mmDC_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_AUTOFILL", REG_MMIO, 0x1a7f, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_AUTOFILL", REG_MMIO, 0x1a7f, &mmDC_LUT_AUTOFILL[0], sizeof(mmDC_LUT_AUTOFILL)/sizeof(mmDC_LUT_AUTOFILL[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_CONTROL", REG_MMIO, 0x1a80, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_CONTROL", REG_MMIO, 0x1a80, &mmDC_LUT_CONTROL[0], sizeof(mmDC_LUT_CONTROL)/sizeof(mmDC_LUT_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1a81, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1a81, &mmDC_LUT_BLACK_OFFSET_BLUE[0], sizeof(mmDC_LUT_BLACK_OFFSET_BLUE)/sizeof(mmDC_LUT_BLACK_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1a82, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1a82, &mmDC_LUT_BLACK_OFFSET_GREEN[0], sizeof(mmDC_LUT_BLACK_OFFSET_GREEN)/sizeof(mmDC_LUT_BLACK_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1a83, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1a83, &mmDC_LUT_BLACK_OFFSET_RED[0], sizeof(mmDC_LUT_BLACK_OFFSET_RED)/sizeof(mmDC_LUT_BLACK_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1a84, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1a84, &mmDC_LUT_WHITE_OFFSET_BLUE[0], sizeof(mmDC_LUT_WHITE_OFFSET_BLUE)/sizeof(mmDC_LUT_WHITE_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1a85, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1a85, &mmDC_LUT_WHITE_OFFSET_GREEN[0], sizeof(mmDC_LUT_WHITE_OFFSET_GREEN)/sizeof(mmDC_LUT_WHITE_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1a86, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1a86, &mmDC_LUT_WHITE_OFFSET_RED[0], sizeof(mmDC_LUT_WHITE_OFFSET_RED)/sizeof(mmDC_LUT_WHITE_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CONTROL", REG_MMIO, 0x1a87, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_CONTROL", REG_MMIO, 0x1a87, &mmDCP_CRC_CONTROL[0], sizeof(mmDCP_CRC_CONTROL)/sizeof(mmDCP_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_MASK", REG_MMIO, 0x1a88, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_MASK", REG_MMIO, 0x1a88, &mmDCP_CRC_MASK[0], sizeof(mmDCP_CRC_MASK)/sizeof(mmDCP_CRC_MASK[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CURRENT", REG_MMIO, 0x1a89, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_CURRENT", REG_MMIO, 0x1a89, &mmDCP_CRC_CURRENT[0], sizeof(mmDCP_CRC_CURRENT)/sizeof(mmDCP_CRC_CURRENT[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_LAST", REG_MMIO, 0x1a8b, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_LAST", REG_MMIO, 0x1a8b, &mmDCP_CRC_LAST[0], sizeof(mmDCP_CRC_LAST)/sizeof(mmDCP_CRC_LAST[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG", REG_MMIO, 0x1a8d, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG", REG_MMIO, 0x1a8d, &mmDCP_DEBUG[0], sizeof(mmDCP_DEBUG)/sizeof(mmDCP_DEBUG[0]), 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1a8e, NULL, 0, 0, 0 },
+	{ "mmGRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1a8e, &mmGRPH_FLIP_RATE_CNTL[0], sizeof(mmGRPH_FLIP_RATE_CNTL)/sizeof(mmGRPH_FLIP_RATE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_DCP_GSL_CONTROL", REG_MMIO, 0x1a90, NULL, 0, 0, 0 },
+	{ "mmDCP_GSL_CONTROL", REG_MMIO, 0x1a90, &mmDCP_GSL_CONTROL[0], sizeof(mmDCP_GSL_CONTROL)/sizeof(mmDCP_GSL_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1a91, NULL, 0, 0, 0 },
+	{ "mmDCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1a91, &mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[0], sizeof(mmDCP_LB_DATA_GAP_BETWEEN_CHUNK)/sizeof(mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[0]), 0, 0 },
+	{ "mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a92, NULL, 0, 0, 0 },
+	{ "mmOVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a92, &mmOVL_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmOVL_SECONDARY_SURFACE_ADDRESS)/sizeof(mmOVL_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x1a93, NULL, 0, 0, 0 },
+	{ "mmOVL_STEREOSYNC_FLIP", REG_MMIO, 0x1a93, &mmOVL_STEREOSYNC_FLIP[0], sizeof(mmOVL_STEREOSYNC_FLIP)/sizeof(mmOVL_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a94, NULL, 0, 0, 0 },
+	{ "mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a94, &mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1a95, NULL, 0, 0, 0 },
+	{ "mmDCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1a95, &mmDCP_TEST_DEBUG_INDEX[0], sizeof(mmDCP_TEST_DEBUG_INDEX)/sizeof(mmDCP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1a96, NULL, 0, 0, 0 },
+	{ "mmDCP_TEST_DEBUG_DATA", REG_MMIO, 0x1a96, &mmDCP_TEST_DEBUG_DATA[0], sizeof(mmDCP_TEST_DEBUG_DATA)/sizeof(mmDCP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCP0_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1a97, NULL, 0, 0, 0 },
+	{ "mmGRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1a97, &mmGRPH_STEREOSYNC_FLIP[0], sizeof(mmGRPH_STEREOSYNC_FLIP)/sizeof(mmGRPH_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG2", REG_MMIO, 0x1a98, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG2", REG_MMIO, 0x1a98, &mmDCP_DEBUG2[0], sizeof(mmDCP_DEBUG2)/sizeof(mmDCP_DEBUG2[0]), 0, 0 },
+	{ "mmDCP0_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1a99, NULL, 0, 0, 0 },
+	{ "mmCUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1a99, &mmCUR_REQUEST_FILTER_CNTL[0], sizeof(mmCUR_REQUEST_FILTER_CNTL)/sizeof(mmCUR_REQUEST_FILTER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_CUR_STEREO_CONTROL", REG_MMIO, 0x1a9a, NULL, 0, 0, 0 },
+	{ "mmCUR_STEREO_CONTROL", REG_MMIO, 0x1a9a, &mmCUR_STEREO_CONTROL[0], sizeof(mmCUR_STEREO_CONTROL)/sizeof(mmCUR_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1a9c, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1a9c, &mmOUT_CLAMP_CONTROL_G_Y[0], sizeof(mmOUT_CLAMP_CONTROL_G_Y)/sizeof(mmOUT_CLAMP_CONTROL_G_Y[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1a9d, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1a9d, &mmOUT_CLAMP_CONTROL_B_CB[0], sizeof(mmOUT_CLAMP_CONTROL_B_CB)/sizeof(mmOUT_CLAMP_CONTROL_B_CB[0]), 0, 0 },
+	{ "mmDCP0_HW_ROTATION", REG_MMIO, 0x1a9e, NULL, 0, 0, 0 },
+	{ "mmHW_ROTATION", REG_MMIO, 0x1a9e, &mmHW_ROTATION[0], sizeof(mmHW_ROTATION)/sizeof(mmHW_ROTATION[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1a9f, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1a9f, &mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[0], sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL)/sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CONTROL", REG_MMIO, 0x1aa0, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CONTROL", REG_MMIO, 0x1aa0, &mmREGAMMA_CONTROL[0], sizeof(mmREGAMMA_CONTROL)/sizeof(mmREGAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_INDEX", REG_MMIO, 0x1aa1, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_INDEX", REG_MMIO, 0x1aa1, &mmREGAMMA_LUT_INDEX[0], sizeof(mmREGAMMA_LUT_INDEX)/sizeof(mmREGAMMA_LUT_INDEX[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_DATA", REG_MMIO, 0x1aa2, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_DATA", REG_MMIO, 0x1aa2, &mmREGAMMA_LUT_DATA[0], sizeof(mmREGAMMA_LUT_DATA)/sizeof(mmREGAMMA_LUT_DATA[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1aa3, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1aa3, &mmREGAMMA_LUT_WRITE_EN_MASK[0], sizeof(mmREGAMMA_LUT_WRITE_EN_MASK)/sizeof(mmREGAMMA_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1aa4, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1aa4, &mmREGAMMA_CNTLA_START_CNTL[0], sizeof(mmREGAMMA_CNTLA_START_CNTL)/sizeof(mmREGAMMA_CNTLA_START_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1aa5, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1aa5, &mmREGAMMA_CNTLA_SLOPE_CNTL[0], sizeof(mmREGAMMA_CNTLA_SLOPE_CNTL)/sizeof(mmREGAMMA_CNTLA_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1aa6, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1aa6, &mmREGAMMA_CNTLA_END_CNTL1[0], sizeof(mmREGAMMA_CNTLA_END_CNTL1)/sizeof(mmREGAMMA_CNTLA_END_CNTL1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1aa7, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1aa7, &mmREGAMMA_CNTLA_END_CNTL2[0], sizeof(mmREGAMMA_CNTLA_END_CNTL2)/sizeof(mmREGAMMA_CNTLA_END_CNTL2[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1aa8, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1aa8, &mmREGAMMA_CNTLA_REGION_0_1[0], sizeof(mmREGAMMA_CNTLA_REGION_0_1)/sizeof(mmREGAMMA_CNTLA_REGION_0_1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1aa9, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1aa9, &mmREGAMMA_CNTLA_REGION_2_3[0], sizeof(mmREGAMMA_CNTLA_REGION_2_3)/sizeof(mmREGAMMA_CNTLA_REGION_2_3[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1aaa, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1aaa, &mmREGAMMA_CNTLA_REGION_4_5[0], sizeof(mmREGAMMA_CNTLA_REGION_4_5)/sizeof(mmREGAMMA_CNTLA_REGION_4_5[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1aab, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1aab, &mmREGAMMA_CNTLA_REGION_6_7[0], sizeof(mmREGAMMA_CNTLA_REGION_6_7)/sizeof(mmREGAMMA_CNTLA_REGION_6_7[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1aac, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1aac, &mmREGAMMA_CNTLA_REGION_8_9[0], sizeof(mmREGAMMA_CNTLA_REGION_8_9)/sizeof(mmREGAMMA_CNTLA_REGION_8_9[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1aad, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1aad, &mmREGAMMA_CNTLA_REGION_10_11[0], sizeof(mmREGAMMA_CNTLA_REGION_10_11)/sizeof(mmREGAMMA_CNTLA_REGION_10_11[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1aae, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1aae, &mmREGAMMA_CNTLA_REGION_12_13[0], sizeof(mmREGAMMA_CNTLA_REGION_12_13)/sizeof(mmREGAMMA_CNTLA_REGION_12_13[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1aaf, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1aaf, &mmREGAMMA_CNTLA_REGION_14_15[0], sizeof(mmREGAMMA_CNTLA_REGION_14_15)/sizeof(mmREGAMMA_CNTLA_REGION_14_15[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1ab0, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1ab0, &mmREGAMMA_CNTLB_START_CNTL[0], sizeof(mmREGAMMA_CNTLB_START_CNTL)/sizeof(mmREGAMMA_CNTLB_START_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1ab1, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1ab1, &mmREGAMMA_CNTLB_SLOPE_CNTL[0], sizeof(mmREGAMMA_CNTLB_SLOPE_CNTL)/sizeof(mmREGAMMA_CNTLB_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1ab2, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1ab2, &mmREGAMMA_CNTLB_END_CNTL1[0], sizeof(mmREGAMMA_CNTLB_END_CNTL1)/sizeof(mmREGAMMA_CNTLB_END_CNTL1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1ab3, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1ab3, &mmREGAMMA_CNTLB_END_CNTL2[0], sizeof(mmREGAMMA_CNTLB_END_CNTL2)/sizeof(mmREGAMMA_CNTLB_END_CNTL2[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1ab4, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1ab4, &mmREGAMMA_CNTLB_REGION_0_1[0], sizeof(mmREGAMMA_CNTLB_REGION_0_1)/sizeof(mmREGAMMA_CNTLB_REGION_0_1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1ab5, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1ab5, &mmREGAMMA_CNTLB_REGION_2_3[0], sizeof(mmREGAMMA_CNTLB_REGION_2_3)/sizeof(mmREGAMMA_CNTLB_REGION_2_3[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1ab6, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1ab6, &mmREGAMMA_CNTLB_REGION_4_5[0], sizeof(mmREGAMMA_CNTLB_REGION_4_5)/sizeof(mmREGAMMA_CNTLB_REGION_4_5[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1ab7, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1ab7, &mmREGAMMA_CNTLB_REGION_6_7[0], sizeof(mmREGAMMA_CNTLB_REGION_6_7)/sizeof(mmREGAMMA_CNTLB_REGION_6_7[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1ab8, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1ab8, &mmREGAMMA_CNTLB_REGION_8_9[0], sizeof(mmREGAMMA_CNTLB_REGION_8_9)/sizeof(mmREGAMMA_CNTLB_REGION_8_9[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1ab9, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1ab9, &mmREGAMMA_CNTLB_REGION_10_11[0], sizeof(mmREGAMMA_CNTLB_REGION_10_11)/sizeof(mmREGAMMA_CNTLB_REGION_10_11[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1aba, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1aba, &mmREGAMMA_CNTLB_REGION_12_13[0], sizeof(mmREGAMMA_CNTLB_REGION_12_13)/sizeof(mmREGAMMA_CNTLB_REGION_12_13[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1abb, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1abb, &mmREGAMMA_CNTLB_REGION_14_15[0], sizeof(mmREGAMMA_CNTLB_REGION_14_15)/sizeof(mmREGAMMA_CNTLB_REGION_14_15[0]), 0, 0 },
+	{ "mmDCP0_ALPHA_CONTROL", REG_MMIO, 0x1abc, NULL, 0, 0, 0 },
+	{ "mmALPHA_CONTROL", REG_MMIO, 0x1abc, &mmALPHA_CONTROL[0], sizeof(mmALPHA_CONTROL)/sizeof(mmALPHA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1abd, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1abd, &mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[0], sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS)/sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1abe, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1abe, &mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1abf, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1abf, &mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[0], sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS)/sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_DATA_FORMAT", REG_MMIO, 0x1ac0, NULL, 0, 0, 0 },
+	{ "mmLB_DATA_FORMAT", REG_MMIO, 0x1ac0, &mmLB_DATA_FORMAT[0], sizeof(mmLB_DATA_FORMAT)/sizeof(mmLB_DATA_FORMAT[0]), 0, 0 },
+	{ "mmLB0_LB_MEMORY_CTRL", REG_MMIO, 0x1ac1, NULL, 0, 0, 0 },
+	{ "mmLB_MEMORY_CTRL", REG_MMIO, 0x1ac1, &mmLB_MEMORY_CTRL[0], sizeof(mmLB_MEMORY_CTRL)/sizeof(mmLB_MEMORY_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ac2, NULL, 0, 0, 0 },
+	{ "mmLB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ac2, &mmLB_MEMORY_SIZE_STATUS[0], sizeof(mmLB_MEMORY_SIZE_STATUS)/sizeof(mmLB_MEMORY_SIZE_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1ac3, NULL, 0, 0, 0 },
+	{ "mmLB_DESKTOP_HEIGHT", REG_MMIO, 0x1ac3, &mmLB_DESKTOP_HEIGHT[0], sizeof(mmLB_DESKTOP_HEIGHT)/sizeof(mmLB_DESKTOP_HEIGHT[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE_START_END", REG_MMIO, 0x1ac4, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE_START_END", REG_MMIO, 0x1ac4, &mmLB_VLINE_START_END[0], sizeof(mmLB_VLINE_START_END)/sizeof(mmLB_VLINE_START_END[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE2_START_END", REG_MMIO, 0x1ac5, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE2_START_END", REG_MMIO, 0x1ac5, &mmLB_VLINE2_START_END[0], sizeof(mmLB_VLINE2_START_END)/sizeof(mmLB_VLINE2_START_END[0]), 0, 0 },
+	{ "mmLB0_LB_V_COUNTER", REG_MMIO, 0x1ac6, NULL, 0, 0, 0 },
+	{ "mmLB_V_COUNTER", REG_MMIO, 0x1ac6, &mmLB_V_COUNTER[0], sizeof(mmLB_V_COUNTER)/sizeof(mmLB_V_COUNTER[0]), 0, 0 },
+	{ "mmLB0_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ac7, NULL, 0, 0, 0 },
+	{ "mmLB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ac7, &mmLB_SNAPSHOT_V_COUNTER[0], sizeof(mmLB_SNAPSHOT_V_COUNTER)/sizeof(mmLB_SNAPSHOT_V_COUNTER[0]), 0, 0 },
+	{ "mmLB0_LB_INTERRUPT_MASK", REG_MMIO, 0x1ac8, NULL, 0, 0, 0 },
+	{ "mmLB_INTERRUPT_MASK", REG_MMIO, 0x1ac8, &mmLB_INTERRUPT_MASK[0], sizeof(mmLB_INTERRUPT_MASK)/sizeof(mmLB_INTERRUPT_MASK[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE_STATUS", REG_MMIO, 0x1ac9, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE_STATUS", REG_MMIO, 0x1ac9, &mmLB_VLINE_STATUS[0], sizeof(mmLB_VLINE_STATUS)/sizeof(mmLB_VLINE_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE2_STATUS", REG_MMIO, 0x1aca, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE2_STATUS", REG_MMIO, 0x1aca, &mmLB_VLINE2_STATUS[0], sizeof(mmLB_VLINE2_STATUS)/sizeof(mmLB_VLINE2_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_VBLANK_STATUS", REG_MMIO, 0x1acb, NULL, 0, 0, 0 },
+	{ "mmLB_VBLANK_STATUS", REG_MMIO, 0x1acb, &mmLB_VBLANK_STATUS[0], sizeof(mmLB_VBLANK_STATUS)/sizeof(mmLB_VBLANK_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_SYNC_RESET_SEL", REG_MMIO, 0x1acc, NULL, 0, 0, 0 },
+	{ "mmLB_SYNC_RESET_SEL", REG_MMIO, 0x1acc, &mmLB_SYNC_RESET_SEL[0], sizeof(mmLB_SYNC_RESET_SEL)/sizeof(mmLB_SYNC_RESET_SEL[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1acd, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_R_CR", REG_MMIO, 0x1acd, &mmLB_BLACK_KEYER_R_CR[0], sizeof(mmLB_BLACK_KEYER_R_CR)/sizeof(mmLB_BLACK_KEYER_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ace, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ace, &mmLB_BLACK_KEYER_G_Y[0], sizeof(mmLB_BLACK_KEYER_G_Y)/sizeof(mmLB_BLACK_KEYER_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1acf, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_B_CB", REG_MMIO, 0x1acf, &mmLB_BLACK_KEYER_B_CB[0], sizeof(mmLB_BLACK_KEYER_B_CB)/sizeof(mmLB_BLACK_KEYER_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ad0, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ad0, &mmLB_KEYER_COLOR_CTRL[0], sizeof(mmLB_KEYER_COLOR_CTRL)/sizeof(mmLB_KEYER_COLOR_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ad1, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ad1, &mmLB_KEYER_COLOR_R_CR[0], sizeof(mmLB_KEYER_COLOR_R_CR)/sizeof(mmLB_KEYER_COLOR_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ad2, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ad2, &mmLB_KEYER_COLOR_G_Y[0], sizeof(mmLB_KEYER_COLOR_G_Y)/sizeof(mmLB_KEYER_COLOR_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ad3, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ad3, &mmLB_KEYER_COLOR_B_CB[0], sizeof(mmLB_KEYER_COLOR_B_CB)/sizeof(mmLB_KEYER_COLOR_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ad4, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ad4, &mmLB_KEYER_COLOR_REP_R_CR[0], sizeof(mmLB_KEYER_COLOR_REP_R_CR)/sizeof(mmLB_KEYER_COLOR_REP_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ad5, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ad5, &mmLB_KEYER_COLOR_REP_G_Y[0], sizeof(mmLB_KEYER_COLOR_REP_G_Y)/sizeof(mmLB_KEYER_COLOR_REP_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ad6, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ad6, &mmLB_KEYER_COLOR_REP_B_CB[0], sizeof(mmLB_KEYER_COLOR_REP_B_CB)/sizeof(mmLB_KEYER_COLOR_REP_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ad7, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ad7, &mmLB_BUFFER_LEVEL_STATUS[0], sizeof(mmLB_BUFFER_LEVEL_STATUS)/sizeof(mmLB_BUFFER_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ad8, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ad8, &mmLB_BUFFER_URGENCY_CTRL[0], sizeof(mmLB_BUFFER_URGENCY_CTRL)/sizeof(mmLB_BUFFER_URGENCY_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ad9, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ad9, &mmLB_BUFFER_URGENCY_STATUS[0], sizeof(mmLB_BUFFER_URGENCY_STATUS)/sizeof(mmLB_BUFFER_URGENCY_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_STATUS", REG_MMIO, 0x1ada, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_STATUS", REG_MMIO, 0x1ada, &mmLB_BUFFER_STATUS[0], sizeof(mmLB_BUFFER_STATUS)/sizeof(mmLB_BUFFER_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1adc, NULL, 0, 0, 0 },
+	{ "mmLB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1adc, &mmLB_NO_OUTSTANDING_REQ_STATUS[0], sizeof(mmLB_NO_OUTSTANDING_REQ_STATUS)/sizeof(mmLB_NO_OUTSTANDING_REQ_STATUS[0]), 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ae0, NULL, 0, 0, 0 },
+	{ "mmMVP_AFR_FLIP_MODE", REG_MMIO, 0x1ae0, &mmMVP_AFR_FLIP_MODE[0], sizeof(mmMVP_AFR_FLIP_MODE)/sizeof(mmMVP_AFR_FLIP_MODE[0]), 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ae1, NULL, 0, 0, 0 },
+	{ "mmMVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ae1, &mmMVP_AFR_FLIP_FIFO_CNTL[0], sizeof(mmMVP_AFR_FLIP_FIFO_CNTL)/sizeof(mmMVP_AFR_FLIP_FIFO_CNTL[0]), 0, 0 },
+	{ "mmLB0_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ae2, NULL, 0, 0, 0 },
+	{ "mmMVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ae2, &mmMVP_FLIP_LINE_NUM_INSERT[0], sizeof(mmMVP_FLIP_LINE_NUM_INSERT)/sizeof(mmMVP_FLIP_LINE_NUM_INSERT[0]), 0, 0 },
+	{ "mmLB0_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ae3, NULL, 0, 0, 0 },
+	{ "mmDC_MVP_LB_CONTROL", REG_MMIO, 0x1ae3, &mmDC_MVP_LB_CONTROL[0], sizeof(mmDC_MVP_LB_CONTROL)/sizeof(mmDC_MVP_LB_CONTROL[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG", REG_MMIO, 0x1ae4, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG", REG_MMIO, 0x1ae4, &mmLB_DEBUG[0], sizeof(mmLB_DEBUG)/sizeof(mmLB_DEBUG[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG2", REG_MMIO, 0x1ae5, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG2", REG_MMIO, 0x1ae5, &mmLB_DEBUG2[0], sizeof(mmLB_DEBUG2)/sizeof(mmLB_DEBUG2[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG3", REG_MMIO, 0x1ae6, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG3", REG_MMIO, 0x1ae6, &mmLB_DEBUG3[0], sizeof(mmLB_DEBUG3)/sizeof(mmLB_DEBUG3[0]), 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1afe, NULL, 0, 0, 0 },
+	{ "mmLB_TEST_DEBUG_INDEX", REG_MMIO, 0x1afe, &mmLB_TEST_DEBUG_INDEX[0], sizeof(mmLB_TEST_DEBUG_INDEX)/sizeof(mmLB_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1aff, NULL, 0, 0, 0 },
+	{ "mmLB_TEST_DEBUG_DATA", REG_MMIO, 0x1aff, &mmLB_TEST_DEBUG_DATA[0], sizeof(mmLB_TEST_DEBUG_DATA)/sizeof(mmLB_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_L", REG_SMC, 0x1b, &ixDP_AUX_DEBUG_L[0], sizeof(ixDP_AUX_DEBUG_L)/sizeof(ixDP_AUX_DEBUG_L[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1b00, NULL, 0, 0, 0 },
+	{ "mmDCFE_CLOCK_CONTROL", REG_MMIO, 0x1b00, &mmDCFE_CLOCK_CONTROL[0], sizeof(mmDCFE_CLOCK_CONTROL)/sizeof(mmDCFE_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_SOFT_RESET", REG_MMIO, 0x1b01, NULL, 0, 0, 0 },
+	{ "mmDCFE_SOFT_RESET", REG_MMIO, 0x1b01, &mmDCFE_SOFT_RESET[0], sizeof(mmDCFE_SOFT_RESET)/sizeof(mmDCFE_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_DBG_CONFIG", REG_MMIO, 0x1b02, NULL, 0, 0, 0 },
+	{ "mmDCFE_DBG_CONFIG", REG_MMIO, 0x1b02, &mmDCFE_DBG_CONFIG[0], sizeof(mmDCFE_DBG_CONFIG)/sizeof(mmDCFE_DBG_CONFIG[0]), 0, 0 },
+	{ "mmDC_PERFMON3_PERFCOUNTER_CNTL", REG_MMIO, 0x1b24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFCOUNTER_STATE", REG_MMIO, 0x1b25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1b26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CNTL", REG_MMIO, 0x1b27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CVALUE_LOW", REG_MMIO, 0x1b28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_HI", REG_MMIO, 0x1b29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_LOW", REG_MMIO, 0x1b2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1b2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1b2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CNTL2", REG_MMIO, 0x1b2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1b30, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1b30, &mmDPG_PIPE_ARBITRATION_CONTROL1[0], sizeof(mmDPG_PIPE_ARBITRATION_CONTROL1)/sizeof(mmDPG_PIPE_ARBITRATION_CONTROL1[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1b31, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1b31, &mmDPG_PIPE_ARBITRATION_CONTROL2[0], sizeof(mmDPG_PIPE_ARBITRATION_CONTROL2)/sizeof(mmDPG_PIPE_ARBITRATION_CONTROL2[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1b32, NULL, 0, 0, 0 },
+	{ "mmDPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1b32, &mmDPG_WATERMARK_MASK_CONTROL[0], sizeof(mmDPG_WATERMARK_MASK_CONTROL)/sizeof(mmDPG_WATERMARK_MASK_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1b33, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1b33, &mmDPG_PIPE_URGENCY_CONTROL[0], sizeof(mmDPG_PIPE_URGENCY_CONTROL)/sizeof(mmDPG_PIPE_URGENCY_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1b34, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1b34, &mmDPG_PIPE_DPM_CONTROL[0], sizeof(mmDPG_PIPE_DPM_CONTROL)/sizeof(mmDPG_PIPE_DPM_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1b35, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1b35, &mmDPG_PIPE_STUTTER_CONTROL[0], sizeof(mmDPG_PIPE_STUTTER_CONTROL)/sizeof(mmDPG_PIPE_STUTTER_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1b36, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1b36, &mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[0], sizeof(mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL)/sizeof(mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1b37, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1b37, &mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[0], sizeof(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)/sizeof(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1b38, NULL, 0, 0, 0 },
+	{ "mmDPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1b38, &mmDPG_TEST_DEBUG_INDEX[0], sizeof(mmDPG_TEST_DEBUG_INDEX)/sizeof(mmDPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1b39, NULL, 0, 0, 0 },
+	{ "mmDPG_TEST_DEBUG_DATA", REG_MMIO, 0x1b39, &mmDPG_TEST_DEBUG_DATA[0], sizeof(mmDPG_TEST_DEBUG_DATA)/sizeof(mmDPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1b3a, NULL, 0, 0, 0 },
+	{ "mmDPG_REPEATER_PROGRAM", REG_MMIO, 0x1b3a, &mmDPG_REPEATER_PROGRAM[0], sizeof(mmDPG_REPEATER_PROGRAM)/sizeof(mmDPG_REPEATER_PROGRAM[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_A", REG_MMIO, 0x1b3b, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_A", REG_MMIO, 0x1b3b, &mmDPG_HW_DEBUG_A[0], sizeof(mmDPG_HW_DEBUG_A)/sizeof(mmDPG_HW_DEBUG_A[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_B", REG_MMIO, 0x1b3c, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_B", REG_MMIO, 0x1b3c, &mmDPG_HW_DEBUG_B[0], sizeof(mmDPG_HW_DEBUG_B)/sizeof(mmDPG_HW_DEBUG_B[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_11", REG_MMIO, 0x1b3d, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_11", REG_MMIO, 0x1b3d, &mmDPG_HW_DEBUG_11[0], sizeof(mmDPG_HW_DEBUG_11)/sizeof(mmDPG_HW_DEBUG_11[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1b40, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_SELECT", REG_MMIO, 0x1b40, &mmSCL_COEF_RAM_SELECT[0], sizeof(mmSCL_COEF_RAM_SELECT)/sizeof(mmSCL_COEF_RAM_SELECT[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1b41, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1b41, &mmSCL_COEF_RAM_TAP_DATA[0], sizeof(mmSCL_COEF_RAM_TAP_DATA)/sizeof(mmSCL_COEF_RAM_TAP_DATA[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE", REG_MMIO, 0x1b42, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE", REG_MMIO, 0x1b42, &mmSCL_MODE[0], sizeof(mmSCL_MODE)/sizeof(mmSCL_MODE[0]), 0, 0 },
+	{ "mmSCL0_SCL_TAP_CONTROL", REG_MMIO, 0x1b43, NULL, 0, 0, 0 },
+	{ "mmSCL_TAP_CONTROL", REG_MMIO, 0x1b43, &mmSCL_TAP_CONTROL[0], sizeof(mmSCL_TAP_CONTROL)/sizeof(mmSCL_TAP_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_CONTROL", REG_MMIO, 0x1b44, NULL, 0, 0, 0 },
+	{ "mmSCL_CONTROL", REG_MMIO, 0x1b44, &mmSCL_CONTROL[0], sizeof(mmSCL_CONTROL)/sizeof(mmSCL_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_BYPASS_CONTROL", REG_MMIO, 0x1b45, NULL, 0, 0, 0 },
+	{ "mmSCL_BYPASS_CONTROL", REG_MMIO, 0x1b45, &mmSCL_BYPASS_CONTROL[0], sizeof(mmSCL_BYPASS_CONTROL)/sizeof(mmSCL_BYPASS_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1b46, NULL, 0, 0, 0 },
+	{ "mmSCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1b46, &mmSCL_MANUAL_REPLICATE_CONTROL[0], sizeof(mmSCL_MANUAL_REPLICATE_CONTROL)/sizeof(mmSCL_MANUAL_REPLICATE_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1b47, NULL, 0, 0, 0 },
+	{ "mmSCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1b47, &mmSCL_AUTOMATIC_MODE_CONTROL[0], sizeof(mmSCL_AUTOMATIC_MODE_CONTROL)/sizeof(mmSCL_AUTOMATIC_MODE_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1b48, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1b48, &mmSCL_HORZ_FILTER_CONTROL[0], sizeof(mmSCL_HORZ_FILTER_CONTROL)/sizeof(mmSCL_HORZ_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1b49, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1b49, &mmSCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmSCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmSCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1b4a, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_INIT", REG_MMIO, 0x1b4a, &mmSCL_HORZ_FILTER_INIT[0], sizeof(mmSCL_HORZ_FILTER_INIT)/sizeof(mmSCL_HORZ_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1b4b, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1b4b, &mmSCL_VERT_FILTER_CONTROL[0], sizeof(mmSCL_VERT_FILTER_CONTROL)/sizeof(mmSCL_VERT_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1b4c, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1b4c, &mmSCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmSCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmSCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1b4d, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_INIT", REG_MMIO, 0x1b4d, &mmSCL_VERT_FILTER_INIT[0], sizeof(mmSCL_VERT_FILTER_INIT)/sizeof(mmSCL_VERT_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1b4e, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1b4e, &mmSCL_VERT_FILTER_INIT_BOT[0], sizeof(mmSCL_VERT_FILTER_INIT_BOT)/sizeof(mmSCL_VERT_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmSCL0_SCL_ROUND_OFFSET", REG_MMIO, 0x1b4f, NULL, 0, 0, 0 },
+	{ "mmSCL_ROUND_OFFSET", REG_MMIO, 0x1b4f, &mmSCL_ROUND_OFFSET[0], sizeof(mmSCL_ROUND_OFFSET)/sizeof(mmSCL_ROUND_OFFSET[0]), 0, 0 },
+	{ "mmSCL0_SCL_UPDATE", REG_MMIO, 0x1b51, NULL, 0, 0, 0 },
+	{ "mmSCL_UPDATE", REG_MMIO, 0x1b51, &mmSCL_UPDATE[0], sizeof(mmSCL_UPDATE)/sizeof(mmSCL_UPDATE[0]), 0, 0 },
+	{ "mmSCL0_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1b53, NULL, 0, 0, 0 },
+	{ "mmSCL_F_SHARP_CONTROL", REG_MMIO, 0x1b53, &mmSCL_F_SHARP_CONTROL[0], sizeof(mmSCL_F_SHARP_CONTROL)/sizeof(mmSCL_F_SHARP_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_ALU_CONTROL", REG_MMIO, 0x1b54, NULL, 0, 0, 0 },
+	{ "mmSCL_ALU_CONTROL", REG_MMIO, 0x1b54, &mmSCL_ALU_CONTROL[0], sizeof(mmSCL_ALU_CONTROL)/sizeof(mmSCL_ALU_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1b55, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1b55, &mmSCL_COEF_RAM_CONFLICT_STATUS[0], sizeof(mmSCL_COEF_RAM_CONFLICT_STATUS)/sizeof(mmSCL_COEF_RAM_CONFLICT_STATUS[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1b5b, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_START_SECONDARY", REG_MMIO, 0x1b5b, &mmVIEWPORT_START_SECONDARY[0], sizeof(mmVIEWPORT_START_SECONDARY)/sizeof(mmVIEWPORT_START_SECONDARY[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_START", REG_MMIO, 0x1b5c, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_START", REG_MMIO, 0x1b5c, &mmVIEWPORT_START[0], sizeof(mmVIEWPORT_START)/sizeof(mmVIEWPORT_START[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_SIZE", REG_MMIO, 0x1b5d, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_SIZE", REG_MMIO, 0x1b5d, &mmVIEWPORT_SIZE[0], sizeof(mmVIEWPORT_SIZE)/sizeof(mmVIEWPORT_SIZE[0]), 0, 0 },
+	{ "mmSCL0_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1b5e, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1b5e, &mmEXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmEXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmEXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 },
+	{ "mmSCL0_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1b5f, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1b5f, &mmEXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmEXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmEXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1b60, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET1", REG_MMIO, 0x1b60, &mmSCL_MODE_CHANGE_DET1[0], sizeof(mmSCL_MODE_CHANGE_DET1)/sizeof(mmSCL_MODE_CHANGE_DET1[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1b61, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET2", REG_MMIO, 0x1b61, &mmSCL_MODE_CHANGE_DET2[0], sizeof(mmSCL_MODE_CHANGE_DET2)/sizeof(mmSCL_MODE_CHANGE_DET2[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1b62, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET3", REG_MMIO, 0x1b62, &mmSCL_MODE_CHANGE_DET3[0], sizeof(mmSCL_MODE_CHANGE_DET3)/sizeof(mmSCL_MODE_CHANGE_DET3[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1b63, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_MASK", REG_MMIO, 0x1b63, &mmSCL_MODE_CHANGE_MASK[0], sizeof(mmSCL_MODE_CHANGE_MASK)/sizeof(mmSCL_MODE_CHANGE_MASK[0]), 0, 0 },
+	{ "mmSCL0_SCL_DEBUG2", REG_MMIO, 0x1b69, NULL, 0, 0, 0 },
+	{ "mmSCL_DEBUG2", REG_MMIO, 0x1b69, &mmSCL_DEBUG2[0], sizeof(mmSCL_DEBUG2)/sizeof(mmSCL_DEBUG2[0]), 0, 0 },
+	{ "mmSCL0_SCL_DEBUG", REG_MMIO, 0x1b6a, NULL, 0, 0, 0 },
+	{ "mmSCL_DEBUG", REG_MMIO, 0x1b6a, &mmSCL_DEBUG[0], sizeof(mmSCL_DEBUG)/sizeof(mmSCL_DEBUG[0]), 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1b6b, NULL, 0, 0, 0 },
+	{ "mmSCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1b6b, &mmSCL_TEST_DEBUG_INDEX[0], sizeof(mmSCL_TEST_DEBUG_INDEX)/sizeof(mmSCL_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1b6c, NULL, 0, 0, 0 },
+	{ "mmSCL_TEST_DEBUG_DATA", REG_MMIO, 0x1b6c, &mmSCL_TEST_DEBUG_DATA[0], sizeof(mmSCL_TEST_DEBUG_DATA)/sizeof(mmSCL_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLND0_BLND_CONTROL", REG_MMIO, 0x1b6d, NULL, 0, 0, 0 },
+	{ "mmBLND_CONTROL", REG_MMIO, 0x1b6d, &mmBLND_CONTROL[0], sizeof(mmBLND_CONTROL)/sizeof(mmBLND_CONTROL[0]), 0, 0 },
+	{ "mmBLND0_SM_CONTROL2", REG_MMIO, 0x1b6e, NULL, 0, 0, 0 },
+	{ "mmSM_CONTROL2", REG_MMIO, 0x1b6e, &mmSM_CONTROL2[0], sizeof(mmSM_CONTROL2)/sizeof(mmSM_CONTROL2[0]), 0, 0 },
+	{ "mmBLND0_BLND_CONTROL2", REG_MMIO, 0x1b6f, NULL, 0, 0, 0 },
+	{ "mmBLND_CONTROL2", REG_MMIO, 0x1b6f, &mmBLND_CONTROL2[0], sizeof(mmBLND_CONTROL2)/sizeof(mmBLND_CONTROL2[0]), 0, 0 },
+	{ "mmBLND0_BLND_UPDATE", REG_MMIO, 0x1b70, NULL, 0, 0, 0 },
+	{ "mmBLND_UPDATE", REG_MMIO, 0x1b70, &mmBLND_UPDATE[0], sizeof(mmBLND_UPDATE)/sizeof(mmBLND_UPDATE[0]), 0, 0 },
+	{ "mmBLND0_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1b71, NULL, 0, 0, 0 },
+	{ "mmBLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1b71, &mmBLND_UNDERFLOW_INTERRUPT[0], sizeof(mmBLND_UNDERFLOW_INTERRUPT)/sizeof(mmBLND_UNDERFLOW_INTERRUPT[0]), 0, 0 },
+	{ "mmBLND0_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1b73, NULL, 0, 0, 0 },
+	{ "mmBLND_V_UPDATE_LOCK", REG_MMIO, 0x1b73, &mmBLND_V_UPDATE_LOCK[0], sizeof(mmBLND_V_UPDATE_LOCK)/sizeof(mmBLND_V_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmBLND0_BLND_DEBUG", REG_MMIO, 0x1b74, NULL, 0, 0, 0 },
+	{ "mmBLND_DEBUG", REG_MMIO, 0x1b74, &mmBLND_DEBUG[0], sizeof(mmBLND_DEBUG)/sizeof(mmBLND_DEBUG[0]), 0, 0 },
+	{ "mmBLND0_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1b75, NULL, 0, 0, 0 },
+	{ "mmBLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1b75, &mmBLND_TEST_DEBUG_INDEX[0], sizeof(mmBLND_TEST_DEBUG_INDEX)/sizeof(mmBLND_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmBLND0_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1b76, NULL, 0, 0, 0 },
+	{ "mmBLND_TEST_DEBUG_DATA", REG_MMIO, 0x1b76, &mmBLND_TEST_DEBUG_DATA[0], sizeof(mmBLND_TEST_DEBUG_DATA)/sizeof(mmBLND_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLND0_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1b77, NULL, 0, 0, 0 },
+	{ "mmBLND_REG_UPDATE_STATUS", REG_MMIO, 0x1b77, &mmBLND_REG_UPDATE_STATUS[0], sizeof(mmBLND_REG_UPDATE_STATUS)/sizeof(mmBLND_REG_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b78, NULL, 0, 0, 0 },
+	{ "mmCRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b78, &mmCRTC_3D_STRUCTURE_CONTROL[0], sizeof(mmCRTC_3D_STRUCTURE_CONTROL)/sizeof(mmCRTC_3D_STRUCTURE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1b79, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1b79, &mmCRTC_GSL_VSYNC_GAP[0], sizeof(mmCRTC_GSL_VSYNC_GAP)/sizeof(mmCRTC_GSL_VSYNC_GAP[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_WINDOW", REG_MMIO, 0x1b7a, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_WINDOW", REG_MMIO, 0x1b7a, &mmCRTC_GSL_WINDOW[0], sizeof(mmCRTC_GSL_WINDOW)/sizeof(mmCRTC_GSL_WINDOW[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_CONTROL", REG_MMIO, 0x1b7b, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_CONTROL", REG_MMIO, 0x1b7b, &mmCRTC_GSL_CONTROL[0], sizeof(mmCRTC_GSL_CONTROL)/sizeof(mmCRTC_GSL_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1b7c, NULL, 0, 0, 0 },
+	{ "mmCRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1b7c, &mmCRTC_DCFE_CLOCK_CONTROL[0], sizeof(mmCRTC_DCFE_CLOCK_CONTROL)/sizeof(mmCRTC_DCFE_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1b7d, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1b7d, &mmCRTC_H_BLANK_EARLY_NUM[0], sizeof(mmCRTC_H_BLANK_EARLY_NUM)/sizeof(mmCRTC_H_BLANK_EARLY_NUM[0]), 0, 0 },
+	{ "mmCRTC0_DCFE_DBG_SEL", REG_MMIO, 0x1b7e, NULL, 0, 0, 0 },
+	{ "mmDCFE_DBG_SEL", REG_MMIO, 0x1b7e, &mmDCFE_DBG_SEL[0], sizeof(mmDCFE_DBG_SEL)/sizeof(mmDCFE_DBG_SEL[0]), 0, 0 },
+	{ "mmCRTC0_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1b7f, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_CTRL", REG_MMIO, 0x1b7f, &mmDCFE_MEM_PWR_CTRL[0], sizeof(mmDCFE_MEM_PWR_CTRL)/sizeof(mmDCFE_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_TOTAL", REG_MMIO, 0x1b80, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_TOTAL", REG_MMIO, 0x1b80, &mmCRTC_H_TOTAL[0], sizeof(mmCRTC_H_TOTAL)/sizeof(mmCRTC_H_TOTAL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_START_END", REG_MMIO, 0x1b81, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_BLANK_START_END", REG_MMIO, 0x1b81, &mmCRTC_H_BLANK_START_END[0], sizeof(mmCRTC_H_BLANK_START_END)/sizeof(mmCRTC_H_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A", REG_MMIO, 0x1b82, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_A", REG_MMIO, 0x1b82, &mmCRTC_H_SYNC_A[0], sizeof(mmCRTC_H_SYNC_A)/sizeof(mmCRTC_H_SYNC_A[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1b83, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1b83, &mmCRTC_H_SYNC_A_CNTL[0], sizeof(mmCRTC_H_SYNC_A_CNTL)/sizeof(mmCRTC_H_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B", REG_MMIO, 0x1b84, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_B", REG_MMIO, 0x1b84, &mmCRTC_H_SYNC_B[0], sizeof(mmCRTC_H_SYNC_B)/sizeof(mmCRTC_H_SYNC_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1b85, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1b85, &mmCRTC_H_SYNC_B_CNTL[0], sizeof(mmCRTC_H_SYNC_B_CNTL)/sizeof(mmCRTC_H_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VBI_END", REG_MMIO, 0x1b86, NULL, 0, 0, 0 },
+	{ "mmCRTC_VBI_END", REG_MMIO, 0x1b86, &mmCRTC_VBI_END[0], sizeof(mmCRTC_VBI_END)/sizeof(mmCRTC_VBI_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL", REG_MMIO, 0x1b87, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL", REG_MMIO, 0x1b87, &mmCRTC_V_TOTAL[0], sizeof(mmCRTC_V_TOTAL)/sizeof(mmCRTC_V_TOTAL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1b88, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_MIN", REG_MMIO, 0x1b88, &mmCRTC_V_TOTAL_MIN[0], sizeof(mmCRTC_V_TOTAL_MIN)/sizeof(mmCRTC_V_TOTAL_MIN[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1b89, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_MAX", REG_MMIO, 0x1b89, &mmCRTC_V_TOTAL_MAX[0], sizeof(mmCRTC_V_TOTAL_MAX)/sizeof(mmCRTC_V_TOTAL_MAX[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1b8a, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1b8a, &mmCRTC_V_TOTAL_CONTROL[0], sizeof(mmCRTC_V_TOTAL_CONTROL)/sizeof(mmCRTC_V_TOTAL_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b8b, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b8b, &mmCRTC_V_TOTAL_INT_STATUS[0], sizeof(mmCRTC_V_TOTAL_INT_STATUS)/sizeof(mmCRTC_V_TOTAL_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b8c, NULL, 0, 0, 0 },
+	{ "mmCRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b8c, &mmCRTC_VSYNC_NOM_INT_STATUS[0], sizeof(mmCRTC_VSYNC_NOM_INT_STATUS)/sizeof(mmCRTC_VSYNC_NOM_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_BLANK_START_END", REG_MMIO, 0x1b8d, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_BLANK_START_END", REG_MMIO, 0x1b8d, &mmCRTC_V_BLANK_START_END[0], sizeof(mmCRTC_V_BLANK_START_END)/sizeof(mmCRTC_V_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A", REG_MMIO, 0x1b8e, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_A", REG_MMIO, 0x1b8e, &mmCRTC_V_SYNC_A[0], sizeof(mmCRTC_V_SYNC_A)/sizeof(mmCRTC_V_SYNC_A[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1b8f, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1b8f, &mmCRTC_V_SYNC_A_CNTL[0], sizeof(mmCRTC_V_SYNC_A_CNTL)/sizeof(mmCRTC_V_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B", REG_MMIO, 0x1b90, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_B", REG_MMIO, 0x1b90, &mmCRTC_V_SYNC_B[0], sizeof(mmCRTC_V_SYNC_B)/sizeof(mmCRTC_V_SYNC_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1b91, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1b91, &mmCRTC_V_SYNC_B_CNTL[0], sizeof(mmCRTC_V_SYNC_B_CNTL)/sizeof(mmCRTC_V_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1b92, NULL, 0, 0, 0 },
+	{ "mmCRTC_DTMTEST_CNTL", REG_MMIO, 0x1b92, &mmCRTC_DTMTEST_CNTL[0], sizeof(mmCRTC_DTMTEST_CNTL)/sizeof(mmCRTC_DTMTEST_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1b93, NULL, 0, 0, 0 },
+	{ "mmCRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1b93, &mmCRTC_DTMTEST_STATUS_POSITION[0], sizeof(mmCRTC_DTMTEST_STATUS_POSITION)/sizeof(mmCRTC_DTMTEST_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_CNTL", REG_MMIO, 0x1b94, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGA_CNTL", REG_MMIO, 0x1b94, &mmCRTC_TRIGA_CNTL[0], sizeof(mmCRTC_TRIGA_CNTL)/sizeof(mmCRTC_TRIGA_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b95, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b95, &mmCRTC_TRIGA_MANUAL_TRIG[0], sizeof(mmCRTC_TRIGA_MANUAL_TRIG)/sizeof(mmCRTC_TRIGA_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_CNTL", REG_MMIO, 0x1b96, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGB_CNTL", REG_MMIO, 0x1b96, &mmCRTC_TRIGB_CNTL[0], sizeof(mmCRTC_TRIGB_CNTL)/sizeof(mmCRTC_TRIGB_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b97, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b97, &mmCRTC_TRIGB_MANUAL_TRIG[0], sizeof(mmCRTC_TRIGB_MANUAL_TRIG)/sizeof(mmCRTC_TRIGB_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b98, NULL, 0, 0, 0 },
+	{ "mmCRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b98, &mmCRTC_FORCE_COUNT_NOW_CNTL[0], sizeof(mmCRTC_FORCE_COUNT_NOW_CNTL)/sizeof(mmCRTC_FORCE_COUNT_NOW_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FLOW_CONTROL", REG_MMIO, 0x1b99, NULL, 0, 0, 0 },
+	{ "mmCRTC_FLOW_CONTROL", REG_MMIO, 0x1b99, &mmCRTC_FLOW_CONTROL[0], sizeof(mmCRTC_FLOW_CONTROL)/sizeof(mmCRTC_FLOW_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b9a, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b9a, &mmCRTC_STEREO_FORCE_NEXT_EYE[0], sizeof(mmCRTC_STEREO_FORCE_NEXT_EYE)/sizeof(mmCRTC_STEREO_FORCE_NEXT_EYE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1b9b, NULL, 0, 0, 0 },
+	{ "mmCRTC_AVSYNC_COUNTER", REG_MMIO, 0x1b9b, &mmCRTC_AVSYNC_COUNTER[0], sizeof(mmCRTC_AVSYNC_COUNTER)/sizeof(mmCRTC_AVSYNC_COUNTER[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CONTROL", REG_MMIO, 0x1b9c, NULL, 0, 0, 0 },
+	{ "mmCRTC_CONTROL", REG_MMIO, 0x1b9c, &mmCRTC_CONTROL[0], sizeof(mmCRTC_CONTROL)/sizeof(mmCRTC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_CONTROL", REG_MMIO, 0x1b9d, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_CONTROL", REG_MMIO, 0x1b9d, &mmCRTC_BLANK_CONTROL[0], sizeof(mmCRTC_BLANK_CONTROL)/sizeof(mmCRTC_BLANK_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1b9e, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERLACE_CONTROL", REG_MMIO, 0x1b9e, &mmCRTC_INTERLACE_CONTROL[0], sizeof(mmCRTC_INTERLACE_CONTROL)/sizeof(mmCRTC_INTERLACE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1b9f, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERLACE_STATUS", REG_MMIO, 0x1b9f, &mmCRTC_INTERLACE_STATUS[0], sizeof(mmCRTC_INTERLACE_STATUS)/sizeof(mmCRTC_INTERLACE_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ba0, NULL, 0, 0, 0 },
+	{ "mmCRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ba0, &mmCRTC_FIELD_INDICATION_CONTROL[0], sizeof(mmCRTC_FIELD_INDICATION_CONTROL)/sizeof(mmCRTC_FIELD_INDICATION_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ba1, NULL, 0, 0, 0 },
+	{ "mmCRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ba1, &mmCRTC_PIXEL_DATA_READBACK0[0], sizeof(mmCRTC_PIXEL_DATA_READBACK0)/sizeof(mmCRTC_PIXEL_DATA_READBACK0[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ba2, NULL, 0, 0, 0 },
+	{ "mmCRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ba2, &mmCRTC_PIXEL_DATA_READBACK1[0], sizeof(mmCRTC_PIXEL_DATA_READBACK1)/sizeof(mmCRTC_PIXEL_DATA_READBACK1[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS", REG_MMIO, 0x1ba3, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS", REG_MMIO, 0x1ba3, &mmCRTC_STATUS[0], sizeof(mmCRTC_STATUS)/sizeof(mmCRTC_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_POSITION", REG_MMIO, 0x1ba4, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_POSITION", REG_MMIO, 0x1ba4, &mmCRTC_STATUS_POSITION[0], sizeof(mmCRTC_STATUS_POSITION)/sizeof(mmCRTC_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ba5, NULL, 0, 0, 0 },
+	{ "mmCRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ba5, &mmCRTC_NOM_VERT_POSITION[0], sizeof(mmCRTC_NOM_VERT_POSITION)/sizeof(mmCRTC_NOM_VERT_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ba6, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ba6, &mmCRTC_STATUS_FRAME_COUNT[0], sizeof(mmCRTC_STATUS_FRAME_COUNT)/sizeof(mmCRTC_STATUS_FRAME_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ba7, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ba7, &mmCRTC_STATUS_VF_COUNT[0], sizeof(mmCRTC_STATUS_VF_COUNT)/sizeof(mmCRTC_STATUS_VF_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ba8, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ba8, &mmCRTC_STATUS_HV_COUNT[0], sizeof(mmCRTC_STATUS_HV_COUNT)/sizeof(mmCRTC_STATUS_HV_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_CONTROL", REG_MMIO, 0x1ba9, NULL, 0, 0, 0 },
+	{ "mmCRTC_COUNT_CONTROL", REG_MMIO, 0x1ba9, &mmCRTC_COUNT_CONTROL[0], sizeof(mmCRTC_COUNT_CONTROL)/sizeof(mmCRTC_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_RESET", REG_MMIO, 0x1baa, NULL, 0, 0, 0 },
+	{ "mmCRTC_COUNT_RESET", REG_MMIO, 0x1baa, &mmCRTC_COUNT_RESET[0], sizeof(mmCRTC_COUNT_RESET)/sizeof(mmCRTC_COUNT_RESET[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bab, NULL, 0, 0, 0 },
+	{ "mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bab, &mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1bac, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1bac, &mmCRTC_VERT_SYNC_CONTROL[0], sizeof(mmCRTC_VERT_SYNC_CONTROL)/sizeof(mmCRTC_VERT_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_STATUS", REG_MMIO, 0x1bad, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_STATUS", REG_MMIO, 0x1bad, &mmCRTC_STEREO_STATUS[0], sizeof(mmCRTC_STEREO_STATUS)/sizeof(mmCRTC_STEREO_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_CONTROL", REG_MMIO, 0x1bae, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_CONTROL", REG_MMIO, 0x1bae, &mmCRTC_STEREO_CONTROL[0], sizeof(mmCRTC_STEREO_CONTROL)/sizeof(mmCRTC_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1baf, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1baf, &mmCRTC_SNAPSHOT_STATUS[0], sizeof(mmCRTC_SNAPSHOT_STATUS)/sizeof(mmCRTC_SNAPSHOT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1bb0, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1bb0, &mmCRTC_SNAPSHOT_CONTROL[0], sizeof(mmCRTC_SNAPSHOT_CONTROL)/sizeof(mmCRTC_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1bb1, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1bb1, &mmCRTC_SNAPSHOT_POSITION[0], sizeof(mmCRTC_SNAPSHOT_POSITION)/sizeof(mmCRTC_SNAPSHOT_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1bb2, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1bb2, &mmCRTC_SNAPSHOT_FRAME[0], sizeof(mmCRTC_SNAPSHOT_FRAME)/sizeof(mmCRTC_SNAPSHOT_FRAME[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1bb3, NULL, 0, 0, 0 },
+	{ "mmCRTC_START_LINE_CONTROL", REG_MMIO, 0x1bb3, &mmCRTC_START_LINE_CONTROL[0], sizeof(mmCRTC_START_LINE_CONTROL)/sizeof(mmCRTC_START_LINE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1bb4, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1bb4, &mmCRTC_INTERRUPT_CONTROL[0], sizeof(mmCRTC_INTERRUPT_CONTROL)/sizeof(mmCRTC_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_UPDATE_LOCK", REG_MMIO, 0x1bb5, NULL, 0, 0, 0 },
+	{ "mmCRTC_UPDATE_LOCK", REG_MMIO, 0x1bb5, &mmCRTC_UPDATE_LOCK[0], sizeof(mmCRTC_UPDATE_LOCK)/sizeof(mmCRTC_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bb6, NULL, 0, 0, 0 },
+	{ "mmCRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bb6, &mmCRTC_DOUBLE_BUFFER_CONTROL[0], sizeof(mmCRTC_DOUBLE_BUFFER_CONTROL)/sizeof(mmCRTC_DOUBLE_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1bb7, NULL, 0, 0, 0 },
+	{ "mmCRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1bb7, &mmCRTC_VGA_PARAMETER_CAPTURE_MODE[0], sizeof(mmCRTC_VGA_PARAMETER_CAPTURE_MODE)/sizeof(mmCRTC_VGA_PARAMETER_CAPTURE_MODE[0]), 0, 0 },
+	{ "mmCRTC0_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1bb8, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1bb8, &mmDCFE_MEM_PWR_CTRL2[0], sizeof(mmDCFE_MEM_PWR_CTRL2)/sizeof(mmDCFE_MEM_PWR_CTRL2[0]), 0, 0 },
+	{ "mmCRTC0_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1bb9, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_STATUS", REG_MMIO, 0x1bb9, &mmDCFE_MEM_PWR_STATUS[0], sizeof(mmDCFE_MEM_PWR_STATUS)/sizeof(mmDCFE_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bba, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bba, &mmCRTC_TEST_PATTERN_CONTROL[0], sizeof(mmCRTC_TEST_PATTERN_CONTROL)/sizeof(mmCRTC_TEST_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bbb, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bbb, &mmCRTC_TEST_PATTERN_PARAMETERS[0], sizeof(mmCRTC_TEST_PATTERN_PARAMETERS)/sizeof(mmCRTC_TEST_PATTERN_PARAMETERS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1bbc, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1bbc, &mmCRTC_TEST_PATTERN_COLOR[0], sizeof(mmCRTC_TEST_PATTERN_COLOR)/sizeof(mmCRTC_TEST_PATTERN_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_MASTER_UPDATE_LOCK", REG_MMIO, 0x1bbd, NULL, 0, 0, 0 },
+	{ "mmMASTER_UPDATE_LOCK", REG_MMIO, 0x1bbd, &mmMASTER_UPDATE_LOCK[0], sizeof(mmMASTER_UPDATE_LOCK)/sizeof(mmMASTER_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTC0_MASTER_UPDATE_MODE", REG_MMIO, 0x1bbe, NULL, 0, 0, 0 },
+	{ "mmMASTER_UPDATE_MODE", REG_MMIO, 0x1bbe, &mmMASTER_UPDATE_MODE[0], sizeof(mmMASTER_UPDATE_MODE)/sizeof(mmMASTER_UPDATE_MODE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1bbf, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1bbf, &mmCRTC_MVP_INBAND_CNTL_INSERT[0], sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT)/sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1bc0, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1bc0, &mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[0], sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER)/sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_STATUS", REG_MMIO, 0x1bc1, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_STATUS", REG_MMIO, 0x1bc1, &mmCRTC_MVP_STATUS[0], sizeof(mmCRTC_MVP_STATUS)/sizeof(mmCRTC_MVP_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_EN", REG_MMIO, 0x1bc2, NULL, 0, 0, 0 },
+	{ "mmCRTC_MASTER_EN", REG_MMIO, 0x1bc2, &mmCRTC_MASTER_EN[0], sizeof(mmCRTC_MASTER_EN)/sizeof(mmCRTC_MASTER_EN[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1bc3, NULL, 0, 0, 0 },
+	{ "mmCRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1bc3, &mmCRTC_ALLOW_STOP_OFF_V_CNT[0], sizeof(mmCRTC_ALLOW_STOP_OFF_V_CNT)/sizeof(mmCRTC_ALLOW_STOP_OFF_V_CNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1bc4, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1bc4, &mmCRTC_V_UPDATE_INT_STATUS[0], sizeof(mmCRTC_V_UPDATE_INT_STATUS)/sizeof(mmCRTC_V_UPDATE_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1bc6, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1bc6, &mmCRTC_TEST_DEBUG_INDEX[0], sizeof(mmCRTC_TEST_DEBUG_INDEX)/sizeof(mmCRTC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1bc7, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1bc7, &mmCRTC_TEST_DEBUG_DATA[0], sizeof(mmCRTC_TEST_DEBUG_DATA)/sizeof(mmCRTC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1bc8, NULL, 0, 0, 0 },
+	{ "mmCRTC_OVERSCAN_COLOR", REG_MMIO, 0x1bc8, &mmCRTC_OVERSCAN_COLOR[0], sizeof(mmCRTC_OVERSCAN_COLOR)/sizeof(mmCRTC_OVERSCAN_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1bc9, NULL, 0, 0, 0 },
+	{ "mmCRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1bc9, &mmCRTC_OVERSCAN_COLOR_EXT[0], sizeof(mmCRTC_OVERSCAN_COLOR_EXT)/sizeof(mmCRTC_OVERSCAN_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1bca, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1bca, &mmCRTC_BLANK_DATA_COLOR[0], sizeof(mmCRTC_BLANK_DATA_COLOR)/sizeof(mmCRTC_BLANK_DATA_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1bcb, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1bcb, &mmCRTC_BLANK_DATA_COLOR_EXT[0], sizeof(mmCRTC_BLANK_DATA_COLOR_EXT)/sizeof(mmCRTC_BLANK_DATA_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR", REG_MMIO, 0x1bcc, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLACK_COLOR", REG_MMIO, 0x1bcc, &mmCRTC_BLACK_COLOR[0], sizeof(mmCRTC_BLACK_COLOR)/sizeof(mmCRTC_BLACK_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1bcd, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1bcd, &mmCRTC_BLACK_COLOR_EXT[0], sizeof(mmCRTC_BLACK_COLOR_EXT)/sizeof(mmCRTC_BLACK_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1bce, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1bce, &mmCRTC_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1bcf, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1bcf, &mmCRTC_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1bd0, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1bd0, &mmCRTC_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1bd1, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1bd1, &mmCRTC_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1bd2, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1bd2, &mmCRTC_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bd3, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bd3, &mmCRTC_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC_CNTL", REG_MMIO, 0x1bd4, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC_CNTL", REG_MMIO, 0x1bd4, &mmCRTC_CRC_CNTL[0], sizeof(mmCRTC_CRC_CNTL)/sizeof(mmCRTC_CRC_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bd5, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bd5, &mmCRTC_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWA_X_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bd6, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bd6, &mmCRTC_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bd7, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bd7, &mmCRTC_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWB_X_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bd8, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bd8, &mmCRTC_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1bd9, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_DATA_RG", REG_MMIO, 0x1bd9, &mmCRTC_CRC0_DATA_RG[0], sizeof(mmCRTC_CRC0_DATA_RG)/sizeof(mmCRTC_CRC0_DATA_RG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_DATA_B", REG_MMIO, 0x1bda, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_DATA_B", REG_MMIO, 0x1bda, &mmCRTC_CRC0_DATA_B[0], sizeof(mmCRTC_CRC0_DATA_B)/sizeof(mmCRTC_CRC0_DATA_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bdb, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bdb, &mmCRTC_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWA_X_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bdc, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bdc, &mmCRTC_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bdd, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bdd, &mmCRTC_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWB_X_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bde, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bde, &mmCRTC_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1bdf, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_DATA_RG", REG_MMIO, 0x1bdf, &mmCRTC_CRC1_DATA_RG[0], sizeof(mmCRTC_CRC1_DATA_RG)/sizeof(mmCRTC_CRC1_DATA_RG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_DATA_B", REG_MMIO, 0x1be0, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_DATA_B", REG_MMIO, 0x1be0, &mmCRTC_CRC1_DATA_B[0], sizeof(mmCRTC_CRC1_DATA_B)/sizeof(mmCRTC_CRC1_DATA_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1be1, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1be1, &mmCRTC_EXT_TIMING_SYNC_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1be2, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1be2, &mmCRTC_EXT_TIMING_SYNC_WINDOW_START[0], sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_START)/sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_START[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1be3, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1be3, &mmCRTC_EXT_TIMING_SYNC_WINDOW_END[0], sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_END)/sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1be4, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1be4, &mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1be5, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1be5, &mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1be6, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1be6, &mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1be7, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1be7, &mmCRTC_STATIC_SCREEN_CONTROL[0], sizeof(mmCRTC_STATIC_SCREEN_CONTROL)/sizeof(mmCRTC_STATIC_SCREEN_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1be8, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1be8, &mmFMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT_CLAMP_COMPONENT_R)/sizeof(mmFMT_CLAMP_COMPONENT_R[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1be9, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1be9, &mmFMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT_CLAMP_COMPONENT_G)/sizeof(mmFMT_CLAMP_COMPONENT_G[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1bea, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1bea, &mmFMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT_CLAMP_COMPONENT_B)/sizeof(mmFMT_CLAMP_COMPONENT_B[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1beb, NULL, 0, 0, 0 },
+	{ "mmFMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1beb, &mmFMT_TEST_DEBUG_INDEX[0], sizeof(mmFMT_TEST_DEBUG_INDEX)/sizeof(mmFMT_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1bec, NULL, 0, 0, 0 },
+	{ "mmFMT_TEST_DEBUG_DATA", REG_MMIO, 0x1bec, &mmFMT_TEST_DEBUG_DATA[0], sizeof(mmFMT_TEST_DEBUG_DATA)/sizeof(mmFMT_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmFMT0_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1bed, NULL, 0, 0, 0 },
+	{ "mmFMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1bed, &mmFMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT_DYNAMIC_EXP_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CONTROL", REG_MMIO, 0x1bee, NULL, 0, 0, 0 },
+	{ "mmFMT_CONTROL", REG_MMIO, 0x1bee, &mmFMT_CONTROL[0], sizeof(mmFMT_CONTROL)/sizeof(mmFMT_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1bef, NULL, 0, 0, 0 },
+	{ "mmFMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1bef, &mmFMT_FORCE_OUTPUT_CNTL[0], sizeof(mmFMT_FORCE_OUTPUT_CNTL)/sizeof(mmFMT_FORCE_OUTPUT_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_FORCE_DATA_0_1", REG_MMIO, 0x1bf0, NULL, 0, 0, 0 },
+	{ "mmFMT_FORCE_DATA_0_1", REG_MMIO, 0x1bf0, &mmFMT_FORCE_DATA_0_1[0], sizeof(mmFMT_FORCE_DATA_0_1)/sizeof(mmFMT_FORCE_DATA_0_1[0]), 0, 0 },
+	{ "mmFMT0_FMT_FORCE_DATA_2_3", REG_MMIO, 0x1bf1, NULL, 0, 0, 0 },
+	{ "mmFMT_FORCE_DATA_2_3", REG_MMIO, 0x1bf1, &mmFMT_FORCE_DATA_2_3[0], sizeof(mmFMT_FORCE_DATA_2_3)/sizeof(mmFMT_FORCE_DATA_2_3[0]), 0, 0 },
+	{ "mmFMT0_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1bf2, NULL, 0, 0, 0 },
+	{ "mmFMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1bf2, &mmFMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT_BIT_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1bf3, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1bf3, &mmFMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT_DITHER_RAND_R_SEED)/sizeof(mmFMT_DITHER_RAND_R_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1bf4, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1bf4, &mmFMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT_DITHER_RAND_G_SEED)/sizeof(mmFMT_DITHER_RAND_G_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1bf5, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1bf5, &mmFMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT_DITHER_RAND_B_SEED)/sizeof(mmFMT_DITHER_RAND_B_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1bf6, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1bf6, &mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[0], sizeof(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL)/sizeof(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1bf7, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1bf7, &mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[0], sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX)/sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1bf8, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1bf8, &mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[0], sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX)/sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_CNTL", REG_MMIO, 0x1bf9, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_CNTL", REG_MMIO, 0x1bf9, &mmFMT_CLAMP_CNTL[0], sizeof(mmFMT_CLAMP_CNTL)/sizeof(mmFMT_CLAMP_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_CNTL", REG_MMIO, 0x1bfa, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_CNTL", REG_MMIO, 0x1bfa, &mmFMT_CRC_CNTL[0], sizeof(mmFMT_CRC_CNTL)/sizeof(mmFMT_CRC_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfb, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfb, &mmFMT_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmFMT_CRC_SIG_RED_GREEN_MASK)/sizeof(mmFMT_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfc, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfc, &mmFMT_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmFMT_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmFMT_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1bfd, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1bfd, &mmFMT_CRC_SIG_RED_GREEN[0], sizeof(mmFMT_CRC_SIG_RED_GREEN)/sizeof(mmFMT_CRC_SIG_RED_GREEN[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1bfe, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1bfe, &mmFMT_CRC_SIG_BLUE_CONTROL[0], sizeof(mmFMT_CRC_SIG_BLUE_CONTROL)/sizeof(mmFMT_CRC_SIG_BLUE_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_DEBUG_CNTL", REG_MMIO, 0x1bff, NULL, 0, 0, 0 },
+	{ "mmFMT_DEBUG_CNTL", REG_MMIO, 0x1bff, &mmFMT_DEBUG_CNTL[0], sizeof(mmFMT_DEBUG_CNTL)/sizeof(mmFMT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDMA_POSITION_LOWER_BASE_ADDRESS", REG_MMIO, 0x1c, &mmDMA_POSITION_LOWER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_M", REG_SMC, 0x1c, &ixDP_AUX_DEBUG_M[0], sizeof(ixDP_AUX_DEBUG_M)/sizeof(ixDP_AUX_DEBUG_M[0]), 0, 0 },
+	{ "mmDCP1_GRPH_ENABLE", REG_MMIO, 0x1c00, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_CONTROL", REG_MMIO, 0x1c01, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1c02, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SWAP_CNTL", REG_MMIO, 0x1c03, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1c04, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1c05, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PITCH", REG_MMIO, 0x1c06, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c07, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c08, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1c09, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1c0a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_START", REG_MMIO, 0x1c0b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_START", REG_MMIO, 0x1c0c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_END", REG_MMIO, 0x1c0d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_END", REG_MMIO, 0x1c0e, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1c10, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_UPDATE", REG_MMIO, 0x1c11, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_CONTROL", REG_MMIO, 0x1c12, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1c13, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_CONTROL", REG_MMIO, 0x1c14, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_STATUS", REG_MMIO, 0x1c15, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1c16, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1c17, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1c18, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1c19, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1c1a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c1b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_ENABLE", REG_MMIO, 0x1c1c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_CONTROL1", REG_MMIO, 0x1c1d, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_CONTROL2", REG_MMIO, 0x1c1e, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SWAP_CNTL", REG_MMIO, 0x1c1f, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS", REG_MMIO, 0x1c20, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_PITCH", REG_MMIO, 0x1c21, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c22, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x1c23, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1c24, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_START", REG_MMIO, 0x1c25, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_END", REG_MMIO, 0x1c26, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_UPDATE", REG_MMIO, 0x1c27, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1c28, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_DFQ_CONTROL", REG_MMIO, 0x1c29, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_DFQ_STATUS", REG_MMIO, 0x1c2a, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1c2b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1c2c, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1c2d, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1c2e, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1c2f, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1c30, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_OVL_CONTROL", REG_MMIO, 0x1c31, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1c32, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1c33, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1c34, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_CONTROL", REG_MMIO, 0x1c35, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C11_C12", REG_MMIO, 0x1c36, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C13_C14", REG_MMIO, 0x1c37, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C21_C22", REG_MMIO, 0x1c38, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C23_C24", REG_MMIO, 0x1c39, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C31_C32", REG_MMIO, 0x1c3a, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C33_C34", REG_MMIO, 0x1c3b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1c3c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1c3d, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1c3e, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1c3f, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1c40, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1c41, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1c42, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1c43, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1c44, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1c45, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1c46, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1c47, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1c48, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1c49, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1c4a, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1c4b, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1c4c, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1c4d, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1c4e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DENORM_CONTROL", REG_MMIO, 0x1c50, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_ROUND_CONTROL", REG_MMIO, 0x1c51, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1c52, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_CONTROL", REG_MMIO, 0x1c53, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_ALPHA", REG_MMIO, 0x1c54, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_RED", REG_MMIO, 0x1c55, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_GREEN", REG_MMIO, 0x1c56, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_BLUE", REG_MMIO, 0x1c57, NULL, 0, 0, 0 },
+	{ "mmDCP1_DEGAMMA_CONTROL", REG_MMIO, 0x1c58, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1c59, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1c5a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1c5b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1c5c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1c5d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1c5e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1c5f, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1c60, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_RANDOM_SEEDS", REG_MMIO, 0x1c61, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1c65, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_CONTROL", REG_MMIO, 0x1c66, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1c67, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SIZE", REG_MMIO, 0x1c68, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c69, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_POSITION", REG_MMIO, 0x1c6a, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_HOT_SPOT", REG_MMIO, 0x1c6b, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR1", REG_MMIO, 0x1c6c, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR2", REG_MMIO, 0x1c6d, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_UPDATE", REG_MMIO, 0x1c6e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_MODE", REG_MMIO, 0x1c78, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_INDEX", REG_MMIO, 0x1c79, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1c7a, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_PWL_DATA", REG_MMIO, 0x1c7b, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_30_COLOR", REG_MMIO, 0x1c7c, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1c7d, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1c7e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_AUTOFILL", REG_MMIO, 0x1c7f, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_CONTROL", REG_MMIO, 0x1c80, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1c81, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1c82, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1c83, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1c84, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1c85, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1c86, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CONTROL", REG_MMIO, 0x1c87, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_MASK", REG_MMIO, 0x1c88, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CURRENT", REG_MMIO, 0x1c89, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_LAST", REG_MMIO, 0x1c8b, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG", REG_MMIO, 0x1c8d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1c8e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_GSL_CONTROL", REG_MMIO, 0x1c90, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1c91, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1c92, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x1c93, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c94, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1c95, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1c96, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1c97, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG2", REG_MMIO, 0x1c98, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1c99, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_STEREO_CONTROL", REG_MMIO, 0x1c9a, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1c9c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1c9d, NULL, 0, 0, 0 },
+	{ "mmDCP1_HW_ROTATION", REG_MMIO, 0x1c9e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1c9f, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CONTROL", REG_MMIO, 0x1ca0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_INDEX", REG_MMIO, 0x1ca1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_DATA", REG_MMIO, 0x1ca2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1ca3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1ca4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1ca5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1ca6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1ca7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1ca8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1ca9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1caa, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1cab, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1cac, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1cad, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1cae, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1caf, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1cb0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1cb1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1cb2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1cb3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1cb4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1cb5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1cb6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1cb7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1cb8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1cb9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1cba, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1cbb, NULL, 0, 0, 0 },
+	{ "mmDCP1_ALPHA_CONTROL", REG_MMIO, 0x1cbc, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1cbd, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1cbe, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1cbf, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DATA_FORMAT", REG_MMIO, 0x1cc0, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_MEMORY_CTRL", REG_MMIO, 0x1cc1, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1cc2, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1cc3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE_START_END", REG_MMIO, 0x1cc4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE2_START_END", REG_MMIO, 0x1cc5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_V_COUNTER", REG_MMIO, 0x1cc6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1cc7, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_INTERRUPT_MASK", REG_MMIO, 0x1cc8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE_STATUS", REG_MMIO, 0x1cc9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE2_STATUS", REG_MMIO, 0x1cca, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VBLANK_STATUS", REG_MMIO, 0x1ccb, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SYNC_RESET_SEL", REG_MMIO, 0x1ccc, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1ccd, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1cce, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1ccf, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1cd0, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1cd1, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1cd2, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1cd3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1cd4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1cd5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1cd6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1cd7, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1cd8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1cd9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_STATUS", REG_MMIO, 0x1cda, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1cdc, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ce0, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ce1, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ce2, NULL, 0, 0, 0 },
+	{ "mmLB1_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ce3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG", REG_MMIO, 0x1ce4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG2", REG_MMIO, 0x1ce5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG3", REG_MMIO, 0x1ce6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1cfe, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1cff, NULL, 0, 0, 0 },
+	{ "mmDMA_POSITION_UPPER_BASE_ADDRESS", REG_MMIO, 0x1d, &mmDMA_POSITION_UPPER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_N", REG_SMC, 0x1d, &ixDP_AUX_DEBUG_N[0], sizeof(ixDP_AUX_DEBUG_N)/sizeof(ixDP_AUX_DEBUG_N[0]), 0, 0 },
+	{ "mmDCFE1_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1d00, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_SOFT_RESET", REG_MMIO, 0x1d01, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_DBG_CONFIG", REG_MMIO, 0x1d02, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFCOUNTER_CNTL", REG_MMIO, 0x1d24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFCOUNTER_STATE", REG_MMIO, 0x1d25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1d26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CNTL", REG_MMIO, 0x1d27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CVALUE_LOW", REG_MMIO, 0x1d28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_HI", REG_MMIO, 0x1d29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_LOW", REG_MMIO, 0x1d2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1d2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1d2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CNTL2", REG_MMIO, 0x1d2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1d30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1d31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1d32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1d33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1d34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1d35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1d36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1d37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1d38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1d39, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1d3a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_A", REG_MMIO, 0x1d3b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_B", REG_MMIO, 0x1d3c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_11", REG_MMIO, 0x1d3d, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1d40, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1d41, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE", REG_MMIO, 0x1d42, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TAP_CONTROL", REG_MMIO, 0x1d43, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_CONTROL", REG_MMIO, 0x1d44, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_BYPASS_CONTROL", REG_MMIO, 0x1d45, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1d46, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1d47, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1d48, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1d49, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1d4a, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1d4b, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1d4c, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1d4d, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1d4e, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ROUND_OFFSET", REG_MMIO, 0x1d4f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_UPDATE", REG_MMIO, 0x1d51, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1d53, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ALU_CONTROL", REG_MMIO, 0x1d54, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1d55, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1d5b, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_START", REG_MMIO, 0x1d5c, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_SIZE", REG_MMIO, 0x1d5d, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1d5e, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1d5f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1d60, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1d61, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1d62, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1d63, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG2", REG_MMIO, 0x1d69, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG", REG_MMIO, 0x1d6a, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1d6b, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1d6c, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_CONTROL", REG_MMIO, 0x1d6d, NULL, 0, 0, 0 },
+	{ "mmBLND1_SM_CONTROL2", REG_MMIO, 0x1d6e, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_CONTROL2", REG_MMIO, 0x1d6f, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_UPDATE", REG_MMIO, 0x1d70, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1d71, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1d73, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_DEBUG", REG_MMIO, 0x1d74, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1d75, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1d76, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1d77, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1d78, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1d79, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_WINDOW", REG_MMIO, 0x1d7a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_CONTROL", REG_MMIO, 0x1d7b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1d7c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1d7d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_DCFE_DBG_SEL", REG_MMIO, 0x1d7e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1d7f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_TOTAL", REG_MMIO, 0x1d80, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_START_END", REG_MMIO, 0x1d81, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A", REG_MMIO, 0x1d82, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1d83, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B", REG_MMIO, 0x1d84, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1d85, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VBI_END", REG_MMIO, 0x1d86, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL", REG_MMIO, 0x1d87, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1d88, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1d89, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1d8a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1d8b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1d8c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_BLANK_START_END", REG_MMIO, 0x1d8d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A", REG_MMIO, 0x1d8e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1d8f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B", REG_MMIO, 0x1d90, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1d91, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1d92, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1d93, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_CNTL", REG_MMIO, 0x1d94, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1d95, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_CNTL", REG_MMIO, 0x1d96, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1d97, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1d98, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FLOW_CONTROL", REG_MMIO, 0x1d99, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1d9a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1d9b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CONTROL", REG_MMIO, 0x1d9c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_CONTROL", REG_MMIO, 0x1d9d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1d9e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1d9f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1da0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1da1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1da2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS", REG_MMIO, 0x1da3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_POSITION", REG_MMIO, 0x1da4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1da5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1da6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1da7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1da8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_CONTROL", REG_MMIO, 0x1da9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_RESET", REG_MMIO, 0x1daa, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1dab, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1dac, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_STATUS", REG_MMIO, 0x1dad, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_CONTROL", REG_MMIO, 0x1dae, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1daf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1db0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1db1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1db2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1db3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1db4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_UPDATE_LOCK", REG_MMIO, 0x1db5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1db6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1db7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1db8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1db9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1dba, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1dbb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1dbc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_MASTER_UPDATE_LOCK", REG_MMIO, 0x1dbd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_MASTER_UPDATE_MODE", REG_MMIO, 0x1dbe, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1dbf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1dc0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_STATUS", REG_MMIO, 0x1dc1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_EN", REG_MMIO, 0x1dc2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1dc3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1dc4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1dc6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1dc7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1dc8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1dc9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1dca, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1dcb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR", REG_MMIO, 0x1dcc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1dcd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1dce, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1dcf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1dd0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1dd1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1dd2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1dd3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC_CNTL", REG_MMIO, 0x1dd4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1dd5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1dd6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1dd7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1dd8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1dd9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_DATA_B", REG_MMIO, 0x1dda, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1ddb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1ddc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1ddd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1dde, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1ddf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_DATA_B", REG_MMIO, 0x1de0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1de1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1de2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1de3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1de4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1de5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1de6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1de7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1de8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1de9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1dea, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1deb, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1dec, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1ded, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CONTROL", REG_MMIO, 0x1dee, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1def, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_DATA_0_1", REG_MMIO, 0x1df0, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_DATA_2_3", REG_MMIO, 0x1df1, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1df2, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1df3, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1df4, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1df5, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1df6, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1df7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1df8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_CNTL", REG_MMIO, 0x1df9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_CNTL", REG_MMIO, 0x1dfa, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1dfb, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1dfc, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1dfd, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1dfe, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DEBUG_CNTL", REG_MMIO, 0x1dff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX_DEBUG_O", REG_SMC, 0x1e, &ixDP_AUX_DEBUG_O[0], sizeof(ixDP_AUX_DEBUG_O)/sizeof(ixDP_AUX_DEBUG_O[0]), 0, 0 },
+	{ "ixCRT1E", REG_SMC, 0x1e, &ixCRT1E[0], sizeof(ixCRT1E)/sizeof(ixCRT1E[0]), 0, 0 },
+	{ "mmDCP2_GRPH_ENABLE", REG_MMIO, 0x1e00, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_CONTROL", REG_MMIO, 0x1e01, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1e02, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SWAP_CNTL", REG_MMIO, 0x1e03, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1e04, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1e05, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PITCH", REG_MMIO, 0x1e06, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e07, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e08, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1e09, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1e0a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_START", REG_MMIO, 0x1e0b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_START", REG_MMIO, 0x1e0c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_END", REG_MMIO, 0x1e0d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_END", REG_MMIO, 0x1e0e, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1e10, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_UPDATE", REG_MMIO, 0x1e11, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_CONTROL", REG_MMIO, 0x1e12, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1e13, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_CONTROL", REG_MMIO, 0x1e14, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_STATUS", REG_MMIO, 0x1e15, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1e16, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1e17, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1e18, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1e19, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1e1a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e1b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_ENABLE", REG_MMIO, 0x1e1c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_CONTROL1", REG_MMIO, 0x1e1d, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_CONTROL2", REG_MMIO, 0x1e1e, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SWAP_CNTL", REG_MMIO, 0x1e1f, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS", REG_MMIO, 0x1e20, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_PITCH", REG_MMIO, 0x1e21, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e22, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x1e23, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1e24, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_START", REG_MMIO, 0x1e25, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_END", REG_MMIO, 0x1e26, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_UPDATE", REG_MMIO, 0x1e27, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1e28, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_DFQ_CONTROL", REG_MMIO, 0x1e29, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_DFQ_STATUS", REG_MMIO, 0x1e2a, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1e2b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1e2c, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1e2d, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1e2e, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1e2f, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1e30, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_OVL_CONTROL", REG_MMIO, 0x1e31, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1e32, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1e33, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1e34, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_CONTROL", REG_MMIO, 0x1e35, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C11_C12", REG_MMIO, 0x1e36, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C13_C14", REG_MMIO, 0x1e37, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C21_C22", REG_MMIO, 0x1e38, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C23_C24", REG_MMIO, 0x1e39, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C31_C32", REG_MMIO, 0x1e3a, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C33_C34", REG_MMIO, 0x1e3b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1e3c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1e3d, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1e3e, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1e3f, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1e40, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1e41, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1e42, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1e43, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1e44, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1e45, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1e46, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1e47, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1e48, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1e49, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1e4a, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1e4b, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1e4c, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1e4d, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1e4e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DENORM_CONTROL", REG_MMIO, 0x1e50, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_ROUND_CONTROL", REG_MMIO, 0x1e51, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1e52, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_CONTROL", REG_MMIO, 0x1e53, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_ALPHA", REG_MMIO, 0x1e54, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_RED", REG_MMIO, 0x1e55, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_GREEN", REG_MMIO, 0x1e56, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_BLUE", REG_MMIO, 0x1e57, NULL, 0, 0, 0 },
+	{ "mmDCP2_DEGAMMA_CONTROL", REG_MMIO, 0x1e58, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1e59, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1e5a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1e5b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1e5c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1e5d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1e5e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1e5f, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1e60, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_RANDOM_SEEDS", REG_MMIO, 0x1e61, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1e65, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_CONTROL", REG_MMIO, 0x1e66, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1e67, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SIZE", REG_MMIO, 0x1e68, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e69, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_POSITION", REG_MMIO, 0x1e6a, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_HOT_SPOT", REG_MMIO, 0x1e6b, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR1", REG_MMIO, 0x1e6c, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR2", REG_MMIO, 0x1e6d, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_UPDATE", REG_MMIO, 0x1e6e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_MODE", REG_MMIO, 0x1e78, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_INDEX", REG_MMIO, 0x1e79, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1e7a, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_PWL_DATA", REG_MMIO, 0x1e7b, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_30_COLOR", REG_MMIO, 0x1e7c, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1e7d, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1e7e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_AUTOFILL", REG_MMIO, 0x1e7f, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_CONTROL", REG_MMIO, 0x1e80, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1e81, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1e82, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1e83, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1e84, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1e85, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1e86, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CONTROL", REG_MMIO, 0x1e87, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_MASK", REG_MMIO, 0x1e88, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CURRENT", REG_MMIO, 0x1e89, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_LAST", REG_MMIO, 0x1e8b, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG", REG_MMIO, 0x1e8d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1e8e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_GSL_CONTROL", REG_MMIO, 0x1e90, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1e91, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1e92, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x1e93, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e94, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1e95, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1e96, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1e97, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG2", REG_MMIO, 0x1e98, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1e99, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_STEREO_CONTROL", REG_MMIO, 0x1e9a, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1e9c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1e9d, NULL, 0, 0, 0 },
+	{ "mmDCP2_HW_ROTATION", REG_MMIO, 0x1e9e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1e9f, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CONTROL", REG_MMIO, 0x1ea0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_INDEX", REG_MMIO, 0x1ea1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_DATA", REG_MMIO, 0x1ea2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1ea3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1ea4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1ea5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1ea6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1ea7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1ea8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1ea9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1eaa, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1eab, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1eac, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1ead, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1eae, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1eaf, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1eb0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1eb1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1eb2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1eb3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1eb4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1eb5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1eb6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1eb7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1eb8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1eb9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1eba, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1ebb, NULL, 0, 0, 0 },
+	{ "mmDCP2_ALPHA_CONTROL", REG_MMIO, 0x1ebc, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1ebd, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1ebe, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1ebf, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DATA_FORMAT", REG_MMIO, 0x1ec0, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_MEMORY_CTRL", REG_MMIO, 0x1ec1, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ec2, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1ec3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE_START_END", REG_MMIO, 0x1ec4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE2_START_END", REG_MMIO, 0x1ec5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_V_COUNTER", REG_MMIO, 0x1ec6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ec7, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_INTERRUPT_MASK", REG_MMIO, 0x1ec8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE_STATUS", REG_MMIO, 0x1ec9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE2_STATUS", REG_MMIO, 0x1eca, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VBLANK_STATUS", REG_MMIO, 0x1ecb, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SYNC_RESET_SEL", REG_MMIO, 0x1ecc, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1ecd, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ece, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1ecf, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ed0, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ed1, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ed2, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ed3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ed4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ed5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ed6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ed7, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ed8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ed9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_STATUS", REG_MMIO, 0x1eda, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1edc, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ee0, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ee1, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ee2, NULL, 0, 0, 0 },
+	{ "mmLB2_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ee3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG", REG_MMIO, 0x1ee4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG2", REG_MMIO, 0x1ee5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG3", REG_MMIO, 0x1ee6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1efe, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1eff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX_DEBUG_P", REG_SMC, 0x1f, &ixDP_AUX_DEBUG_P[0], sizeof(ixDP_AUX_DEBUG_P)/sizeof(ixDP_AUX_DEBUG_P[0]), 0, 0 },
+	{ "ixCRT1F", REG_SMC, 0x1f, &ixCRT1F[0], sizeof(ixCRT1F)/sizeof(ixCRT1F[0]), 0, 0 },
+	{ "mmDCFE2_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1f00, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_SOFT_RESET", REG_MMIO, 0x1f01, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_DBG_CONFIG", REG_MMIO, 0x1f02, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0x1f04, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_SMC, 0x1f05, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x1f0a, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_SMC, 0x1f0b, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_SMC, 0x1f0f, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmDC_PERFMON5_PERFCOUNTER_CNTL", REG_MMIO, 0x1f24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFCOUNTER_STATE", REG_MMIO, 0x1f25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1f26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CNTL", REG_MMIO, 0x1f27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CVALUE_LOW", REG_MMIO, 0x1f28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_HI", REG_MMIO, 0x1f29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_LOW", REG_MMIO, 0x1f2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1f2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1f2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CNTL2", REG_MMIO, 0x1f2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1f30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1f31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1f32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1f33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1f34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1f35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1f36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1f37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1f38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1f39, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1f3a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_A", REG_MMIO, 0x1f3b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_B", REG_MMIO, 0x1f3c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_11", REG_MMIO, 0x1f3d, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1f40, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1f41, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE", REG_MMIO, 0x1f42, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TAP_CONTROL", REG_MMIO, 0x1f43, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_CONTROL", REG_MMIO, 0x1f44, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_BYPASS_CONTROL", REG_MMIO, 0x1f45, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1f46, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1f47, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1f48, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1f49, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1f4a, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1f4b, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1f4c, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1f4d, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1f4e, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ROUND_OFFSET", REG_MMIO, 0x1f4f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_UPDATE", REG_MMIO, 0x1f51, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1f53, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ALU_CONTROL", REG_MMIO, 0x1f54, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1f55, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1f5b, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_START", REG_MMIO, 0x1f5c, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_SIZE", REG_MMIO, 0x1f5d, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1f5e, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1f5f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1f60, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1f61, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1f62, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1f63, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG2", REG_MMIO, 0x1f69, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG", REG_MMIO, 0x1f6a, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1f6b, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1f6c, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_CONTROL", REG_MMIO, 0x1f6d, NULL, 0, 0, 0 },
+	{ "mmBLND2_SM_CONTROL2", REG_MMIO, 0x1f6e, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_CONTROL2", REG_MMIO, 0x1f6f, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_UPDATE", REG_MMIO, 0x1f70, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1f71, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1f73, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_DEBUG", REG_MMIO, 0x1f74, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1f75, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1f76, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1f77, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1f78, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1f79, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_WINDOW", REG_MMIO, 0x1f7a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_CONTROL", REG_MMIO, 0x1f7b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1f7c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1f7d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_DCFE_DBG_SEL", REG_MMIO, 0x1f7e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1f7f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_TOTAL", REG_MMIO, 0x1f80, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_START_END", REG_MMIO, 0x1f81, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A", REG_MMIO, 0x1f82, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1f83, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B", REG_MMIO, 0x1f84, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1f85, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VBI_END", REG_MMIO, 0x1f86, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL", REG_MMIO, 0x1f87, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1f88, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1f89, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1f8a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1f8b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1f8c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_BLANK_START_END", REG_MMIO, 0x1f8d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A", REG_MMIO, 0x1f8e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1f8f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B", REG_MMIO, 0x1f90, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1f91, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1f92, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1f93, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_CNTL", REG_MMIO, 0x1f94, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1f95, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_CNTL", REG_MMIO, 0x1f96, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1f97, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1f98, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FLOW_CONTROL", REG_MMIO, 0x1f99, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1f9a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1f9b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CONTROL", REG_MMIO, 0x1f9c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_CONTROL", REG_MMIO, 0x1f9d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1f9e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1f9f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1fa0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1fa1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1fa2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS", REG_MMIO, 0x1fa3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_POSITION", REG_MMIO, 0x1fa4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1fa5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1fa6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1fa7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1fa8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_CONTROL", REG_MMIO, 0x1fa9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_RESET", REG_MMIO, 0x1faa, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1fab, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1fac, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_STATUS", REG_MMIO, 0x1fad, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_CONTROL", REG_MMIO, 0x1fae, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1faf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1fb0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1fb1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1fb2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1fb3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1fb4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_UPDATE_LOCK", REG_MMIO, 0x1fb5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1fb6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1fb7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1fb8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1fb9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1fba, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1fbb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1fbc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_MASTER_UPDATE_LOCK", REG_MMIO, 0x1fbd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_MASTER_UPDATE_MODE", REG_MMIO, 0x1fbe, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1fbf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1fc0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_STATUS", REG_MMIO, 0x1fc1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_EN", REG_MMIO, 0x1fc2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1fc3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1fc4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1fc6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1fc7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1fc8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1fc9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1fca, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1fcb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR", REG_MMIO, 0x1fcc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1fcd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1fce, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1fcf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1fd0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1fd1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1fd2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1fd3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC_CNTL", REG_MMIO, 0x1fd4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1fd5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1fd6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1fd7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1fd8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1fd9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_DATA_B", REG_MMIO, 0x1fda, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1fdb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1fdc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1fdd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1fde, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1fdf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_DATA_B", REG_MMIO, 0x1fe0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1fe1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1fe2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1fe3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1fe4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1fe5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1fe6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1fe7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1fe8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1fe9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1fea, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1feb, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1fec, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1fed, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CONTROL", REG_MMIO, 0x1fee, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1fef, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_DATA_0_1", REG_MMIO, 0x1ff0, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_DATA_2_3", REG_MMIO, 0x1ff1, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1ff2, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1ff3, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1ff4, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1ff5, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1ff6, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1ff7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1ff8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_CNTL", REG_MMIO, 0x1ff9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_CNTL", REG_MMIO, 0x1ffa, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1ffb, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1ffc, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1ffd, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1ffe, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DEBUG_CNTL", REG_MMIO, 0x1fff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN", REG_SMC, 0x2, &ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0]), 0, 0 },
+	{ "ixAZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x2, &ixAZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL2", REG_SMC, 0x2, &ixAZALIA_INPUT_CRC0_CHANNEL2[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL2)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL2[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL2", REG_SMC, 0x2, &ixAZALIA_CRC0_CHANNEL2[0], sizeof(ixAZALIA_CRC0_CHANNEL2)/sizeof(ixAZALIA_CRC0_CHANNEL2[0]), 0, 0 },
+	{ "ixDMIF_DEBUG02_CORE0", REG_SMC, 0x2, &ixDMIF_DEBUG02_CORE0[0], sizeof(ixDMIF_DEBUG02_CORE0)/sizeof(ixDMIF_DEBUG02_CORE0[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR1", REG_SMC, 0x2, &ixAUDIO_DESCRIPTOR1[0], sizeof(ixAUDIO_DESCRIPTOR1)/sizeof(ixAUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "mmGLOBAL_CONTROL", REG_MMIO, 0x2, &mmGLOBAL_CONTROL[0], sizeof(mmGLOBAL_CONTROL)/sizeof(mmGLOBAL_CONTROL[0]), 0, 0 },
+	{ "ixDCIO_DEBUG2", REG_SMC, 0x2, &ixDCIO_DEBUG2[0], sizeof(ixDCIO_DEBUG2)/sizeof(ixDCIO_DEBUG2[0]), 0, 0 },
+	{ "ixFMT_DEBUG1", REG_SMC, 0x2, &ixFMT_DEBUG1[0], sizeof(ixFMT_DEBUG1)/sizeof(ixFMT_DEBUG1[0]), 0, 0 },
+	{ "ixATTR02", REG_SMC, 0x2, &ixATTR02[0], sizeof(ixATTR02)/sizeof(ixATTR02[0]), 0, 0 },
+	{ "ixSEQ02", REG_SMC, 0x2, &ixSEQ02[0], sizeof(ixSEQ02)/sizeof(ixSEQ02[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x20, &ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x20, &ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x20, &mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_Q", REG_SMC, 0x20, &ixDP_AUX_DEBUG_Q[0], sizeof(ixDP_AUX_DEBUG_Q)/sizeof(ixDP_AUX_DEBUG_Q[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x21, &mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x21, &ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x21, &ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x22, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x22, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x22, &mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 },
+	{ "ixCRT22", REG_SMC, 0x22, &ixCRT22[0], sizeof(ixCRT22)/sizeof(ixCRT22[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2200, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x23, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x23, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x23, &mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x24, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x24, &ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x24, &mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x24, &mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x25, &ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x26, &mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x27, &mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x2706, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x270d, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2", REG_SMC, 0x270e, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x2724, &ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3", REG_SMC, 0x273e, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x2770, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x2771, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x28, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "mmFBC_CNTL", REG_MMIO, 0x280, &mmFBC_CNTL[0], sizeof(mmFBC_CNTL)/sizeof(mmFBC_CNTL[0]), 0, 0 },
+	{ "mmFBC_IDLE_MASK", REG_MMIO, 0x281, &mmFBC_IDLE_MASK[0], sizeof(mmFBC_IDLE_MASK)/sizeof(mmFBC_IDLE_MASK[0]), 0, 0 },
+	{ "mmFBC_IDLE_FORCE_CLEAR_MASK", REG_MMIO, 0x282, &mmFBC_IDLE_FORCE_CLEAR_MASK[0], sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK)/sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK[0]), 0, 0 },
+	{ "mmFBC_START_STOP_DELAY", REG_MMIO, 0x283, &mmFBC_START_STOP_DELAY[0], sizeof(mmFBC_START_STOP_DELAY)/sizeof(mmFBC_START_STOP_DELAY[0]), 0, 0 },
+	{ "mmFBC_COMP_CNTL", REG_MMIO, 0x284, &mmFBC_COMP_CNTL[0], sizeof(mmFBC_COMP_CNTL)/sizeof(mmFBC_COMP_CNTL[0]), 0, 0 },
+	{ "mmFBC_COMP_MODE", REG_MMIO, 0x285, &mmFBC_COMP_MODE[0], sizeof(mmFBC_COMP_MODE)/sizeof(mmFBC_COMP_MODE[0]), 0, 0 },
+	{ "mmFBC_DEBUG0", REG_MMIO, 0x286, &mmFBC_DEBUG0[0], sizeof(mmFBC_DEBUG0)/sizeof(mmFBC_DEBUG0[0]), 0, 0 },
+	{ "mmFBC_DEBUG1", REG_MMIO, 0x287, &mmFBC_DEBUG1[0], sizeof(mmFBC_DEBUG1)/sizeof(mmFBC_DEBUG1[0]), 0, 0 },
+	{ "mmFBC_DEBUG2", REG_MMIO, 0x288, &mmFBC_DEBUG2[0], sizeof(mmFBC_DEBUG2)/sizeof(mmFBC_DEBUG2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT0", REG_MMIO, 0x289, &mmFBC_IND_LUT0[0], sizeof(mmFBC_IND_LUT0)/sizeof(mmFBC_IND_LUT0[0]), 0, 0 },
+	{ "mmFBC_IND_LUT1", REG_MMIO, 0x28a, &mmFBC_IND_LUT1[0], sizeof(mmFBC_IND_LUT1)/sizeof(mmFBC_IND_LUT1[0]), 0, 0 },
+	{ "mmFBC_IND_LUT2", REG_MMIO, 0x28b, &mmFBC_IND_LUT2[0], sizeof(mmFBC_IND_LUT2)/sizeof(mmFBC_IND_LUT2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT3", REG_MMIO, 0x28c, &mmFBC_IND_LUT3[0], sizeof(mmFBC_IND_LUT3)/sizeof(mmFBC_IND_LUT3[0]), 0, 0 },
+	{ "mmFBC_IND_LUT4", REG_MMIO, 0x28d, &mmFBC_IND_LUT4[0], sizeof(mmFBC_IND_LUT4)/sizeof(mmFBC_IND_LUT4[0]), 0, 0 },
+	{ "mmFBC_IND_LUT5", REG_MMIO, 0x28e, &mmFBC_IND_LUT5[0], sizeof(mmFBC_IND_LUT5)/sizeof(mmFBC_IND_LUT5[0]), 0, 0 },
+	{ "mmFBC_IND_LUT6", REG_MMIO, 0x28f, &mmFBC_IND_LUT6[0], sizeof(mmFBC_IND_LUT6)/sizeof(mmFBC_IND_LUT6[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x29, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "mmFBC_IND_LUT7", REG_MMIO, 0x290, &mmFBC_IND_LUT7[0], sizeof(mmFBC_IND_LUT7)/sizeof(mmFBC_IND_LUT7[0]), 0, 0 },
+	{ "mmFBC_IND_LUT8", REG_MMIO, 0x291, &mmFBC_IND_LUT8[0], sizeof(mmFBC_IND_LUT8)/sizeof(mmFBC_IND_LUT8[0]), 0, 0 },
+	{ "mmFBC_IND_LUT9", REG_MMIO, 0x292, &mmFBC_IND_LUT9[0], sizeof(mmFBC_IND_LUT9)/sizeof(mmFBC_IND_LUT9[0]), 0, 0 },
+	{ "mmFBC_IND_LUT10", REG_MMIO, 0x293, &mmFBC_IND_LUT10[0], sizeof(mmFBC_IND_LUT10)/sizeof(mmFBC_IND_LUT10[0]), 0, 0 },
+	{ "mmFBC_IND_LUT11", REG_MMIO, 0x294, &mmFBC_IND_LUT11[0], sizeof(mmFBC_IND_LUT11)/sizeof(mmFBC_IND_LUT11[0]), 0, 0 },
+	{ "mmFBC_IND_LUT12", REG_MMIO, 0x295, &mmFBC_IND_LUT12[0], sizeof(mmFBC_IND_LUT12)/sizeof(mmFBC_IND_LUT12[0]), 0, 0 },
+	{ "mmFBC_IND_LUT13", REG_MMIO, 0x296, &mmFBC_IND_LUT13[0], sizeof(mmFBC_IND_LUT13)/sizeof(mmFBC_IND_LUT13[0]), 0, 0 },
+	{ "mmFBC_IND_LUT14", REG_MMIO, 0x297, &mmFBC_IND_LUT14[0], sizeof(mmFBC_IND_LUT14)/sizeof(mmFBC_IND_LUT14[0]), 0, 0 },
+	{ "mmFBC_IND_LUT15", REG_MMIO, 0x298, &mmFBC_IND_LUT15[0], sizeof(mmFBC_IND_LUT15)/sizeof(mmFBC_IND_LUT15[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_01", REG_MMIO, 0x299, &mmFBC_CSM_REGION_OFFSET_01[0], sizeof(mmFBC_CSM_REGION_OFFSET_01)/sizeof(mmFBC_CSM_REGION_OFFSET_01[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_23", REG_MMIO, 0x29a, &mmFBC_CSM_REGION_OFFSET_23[0], sizeof(mmFBC_CSM_REGION_OFFSET_23)/sizeof(mmFBC_CSM_REGION_OFFSET_23[0]), 0, 0 },
+	{ "mmFBC_CLIENT_REGION_MASK", REG_MMIO, 0x29b, &mmFBC_CLIENT_REGION_MASK[0], sizeof(mmFBC_CLIENT_REGION_MASK)/sizeof(mmFBC_CLIENT_REGION_MASK[0]), 0, 0 },
+	{ "mmFBC_DEBUG_COMP", REG_MMIO, 0x29c, &mmFBC_DEBUG_COMP[0], sizeof(mmFBC_DEBUG_COMP)/sizeof(mmFBC_DEBUG_COMP[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR", REG_MMIO, 0x29d, &mmFBC_DEBUG_CSR[0], sizeof(mmFBC_DEBUG_CSR)/sizeof(mmFBC_DEBUG_CSR[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA", REG_MMIO, 0x29e, &mmFBC_DEBUG_CSR_RDATA[0], sizeof(mmFBC_DEBUG_CSR_RDATA)/sizeof(mmFBC_DEBUG_CSR_RDATA[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA", REG_MMIO, 0x29f, &mmFBC_DEBUG_CSR_WDATA[0], sizeof(mmFBC_DEBUG_CSR_WDATA)/sizeof(mmFBC_DEBUG_CSR_WDATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x2a, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA_HI", REG_MMIO, 0x2a0, &mmFBC_DEBUG_CSR_RDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_RDATA_HI)/sizeof(mmFBC_DEBUG_CSR_RDATA_HI[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA_HI", REG_MMIO, 0x2a1, &mmFBC_DEBUG_CSR_WDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_WDATA_HI)/sizeof(mmFBC_DEBUG_CSR_WDATA_HI[0]), 0, 0 },
+	{ "mmFBC_MISC", REG_MMIO, 0x2a2, &mmFBC_MISC[0], sizeof(mmFBC_MISC)/sizeof(mmFBC_MISC[0]), 0, 0 },
+	{ "mmFBC_STATUS", REG_MMIO, 0x2a3, &mmFBC_STATUS[0], sizeof(mmFBC_STATUS)/sizeof(mmFBC_STATUS[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_INDEX", REG_MMIO, 0x2a4, &mmFBC_TEST_DEBUG_INDEX[0], sizeof(mmFBC_TEST_DEBUG_INDEX)/sizeof(mmFBC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_DATA", REG_MMIO, 0x2a5, &mmFBC_TEST_DEBUG_DATA[0], sizeof(mmFBC_TEST_DEBUG_DATA)/sizeof(mmFBC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMVP_CONTROL1", REG_MMIO, 0x2ac, &mmMVP_CONTROL1[0], sizeof(mmMVP_CONTROL1)/sizeof(mmMVP_CONTROL1[0]), 0, 0 },
+	{ "mmMVP_CONTROL2", REG_MMIO, 0x2ad, &mmMVP_CONTROL2[0], sizeof(mmMVP_CONTROL2)/sizeof(mmMVP_CONTROL2[0]), 0, 0 },
+	{ "mmMVP_FIFO_CONTROL", REG_MMIO, 0x2ae, &mmMVP_FIFO_CONTROL[0], sizeof(mmMVP_FIFO_CONTROL)/sizeof(mmMVP_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmMVP_FIFO_STATUS", REG_MMIO, 0x2af, &mmMVP_FIFO_STATUS[0], sizeof(mmMVP_FIFO_STATUS)/sizeof(mmMVP_FIFO_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x2b, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "mmMVP_SLAVE_STATUS", REG_MMIO, 0x2b0, &mmMVP_SLAVE_STATUS[0], sizeof(mmMVP_SLAVE_STATUS)/sizeof(mmMVP_SLAVE_STATUS[0]), 0, 0 },
+	{ "mmMVP_INBAND_CNTL_CAP", REG_MMIO, 0x2b1, &mmMVP_INBAND_CNTL_CAP[0], sizeof(mmMVP_INBAND_CNTL_CAP)/sizeof(mmMVP_INBAND_CNTL_CAP[0]), 0, 0 },
+	{ "mmMVP_BLACK_KEYER", REG_MMIO, 0x2b2, &mmMVP_BLACK_KEYER[0], sizeof(mmMVP_BLACK_KEYER)/sizeof(mmMVP_BLACK_KEYER[0]), 0, 0 },
+	{ "mmMVP_CRC_CNTL", REG_MMIO, 0x2b3, &mmMVP_CRC_CNTL[0], sizeof(mmMVP_CRC_CNTL)/sizeof(mmMVP_CRC_CNTL[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_BLUE_GREEN", REG_MMIO, 0x2b4, &mmMVP_CRC_RESULT_BLUE_GREEN[0], sizeof(mmMVP_CRC_RESULT_BLUE_GREEN)/sizeof(mmMVP_CRC_RESULT_BLUE_GREEN[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_RED", REG_MMIO, 0x2b5, &mmMVP_CRC_RESULT_RED[0], sizeof(mmMVP_CRC_RESULT_RED)/sizeof(mmMVP_CRC_RESULT_RED[0]), 0, 0 },
+	{ "mmMVP_CONTROL3", REG_MMIO, 0x2b6, &mmMVP_CONTROL3[0], sizeof(mmMVP_CONTROL3)/sizeof(mmMVP_CONTROL3[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL1", REG_MMIO, 0x2b7, &mmMVP_RECEIVE_CNT_CNTL1[0], sizeof(mmMVP_RECEIVE_CNT_CNTL1)/sizeof(mmMVP_RECEIVE_CNT_CNTL1[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL2", REG_MMIO, 0x2b8, &mmMVP_RECEIVE_CNT_CNTL2[0], sizeof(mmMVP_RECEIVE_CNT_CNTL2)/sizeof(mmMVP_RECEIVE_CNT_CNTL2[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_INDEX", REG_MMIO, 0x2b9, &mmMVP_TEST_DEBUG_INDEX[0], sizeof(mmMVP_TEST_DEBUG_INDEX)/sizeof(mmMVP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_DATA", REG_MMIO, 0x2ba, &mmMVP_TEST_DEBUG_DATA[0], sizeof(mmMVP_TEST_DEBUG_DATA)/sizeof(mmMVP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMVP_DEBUG", REG_MMIO, 0x2bb, &mmMVP_DEBUG[0], sizeof(mmMVP_DEBUG)/sizeof(mmMVP_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x2c, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "mmPIPE0_PG_CONFIG", REG_MMIO, 0x2c0, &mmPIPE0_PG_CONFIG[0], sizeof(mmPIPE0_PG_CONFIG)/sizeof(mmPIPE0_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE0_PG_ENABLE", REG_MMIO, 0x2c1, &mmPIPE0_PG_ENABLE[0], sizeof(mmPIPE0_PG_ENABLE)/sizeof(mmPIPE0_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE0_PG_STATUS", REG_MMIO, 0x2c2, &mmPIPE0_PG_STATUS[0], sizeof(mmPIPE0_PG_STATUS)/sizeof(mmPIPE0_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE1_PG_CONFIG", REG_MMIO, 0x2c3, &mmPIPE1_PG_CONFIG[0], sizeof(mmPIPE1_PG_CONFIG)/sizeof(mmPIPE1_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE1_PG_ENABLE", REG_MMIO, 0x2c4, &mmPIPE1_PG_ENABLE[0], sizeof(mmPIPE1_PG_ENABLE)/sizeof(mmPIPE1_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE1_PG_STATUS", REG_MMIO, 0x2c5, &mmPIPE1_PG_STATUS[0], sizeof(mmPIPE1_PG_STATUS)/sizeof(mmPIPE1_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE2_PG_CONFIG", REG_MMIO, 0x2c6, &mmPIPE2_PG_CONFIG[0], sizeof(mmPIPE2_PG_CONFIG)/sizeof(mmPIPE2_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE2_PG_ENABLE", REG_MMIO, 0x2c7, &mmPIPE2_PG_ENABLE[0], sizeof(mmPIPE2_PG_ENABLE)/sizeof(mmPIPE2_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE2_PG_STATUS", REG_MMIO, 0x2c8, &mmPIPE2_PG_STATUS[0], sizeof(mmPIPE2_PG_STATUS)/sizeof(mmPIPE2_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE3_PG_CONFIG", REG_MMIO, 0x2c9, &mmPIPE3_PG_CONFIG[0], sizeof(mmPIPE3_PG_CONFIG)/sizeof(mmPIPE3_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE3_PG_ENABLE", REG_MMIO, 0x2ca, &mmPIPE3_PG_ENABLE[0], sizeof(mmPIPE3_PG_ENABLE)/sizeof(mmPIPE3_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE3_PG_STATUS", REG_MMIO, 0x2cb, &mmPIPE3_PG_STATUS[0], sizeof(mmPIPE3_PG_STATUS)/sizeof(mmPIPE3_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE4_PG_CONFIG", REG_MMIO, 0x2cc, &mmPIPE4_PG_CONFIG[0], sizeof(mmPIPE4_PG_CONFIG)/sizeof(mmPIPE4_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE4_PG_ENABLE", REG_MMIO, 0x2cd, &mmPIPE4_PG_ENABLE[0], sizeof(mmPIPE4_PG_ENABLE)/sizeof(mmPIPE4_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE4_PG_STATUS", REG_MMIO, 0x2ce, &mmPIPE4_PG_STATUS[0], sizeof(mmPIPE4_PG_STATUS)/sizeof(mmPIPE4_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE5_PG_CONFIG", REG_MMIO, 0x2cf, &mmPIPE5_PG_CONFIG[0], sizeof(mmPIPE5_PG_CONFIG)/sizeof(mmPIPE5_PG_CONFIG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x2d, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "mmPIPE5_PG_ENABLE", REG_MMIO, 0x2d0, &mmPIPE5_PG_ENABLE[0], sizeof(mmPIPE5_PG_ENABLE)/sizeof(mmPIPE5_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE5_PG_STATUS", REG_MMIO, 0x2d1, &mmPIPE5_PG_STATUS[0], sizeof(mmPIPE5_PG_STATUS)/sizeof(mmPIPE5_PG_STATUS[0]), 0, 0 },
+	{ "mmDC_IP_REQUEST_CNTL", REG_MMIO, 0x2d2, &mmDC_IP_REQUEST_CNTL[0], sizeof(mmDC_IP_REQUEST_CNTL)/sizeof(mmDC_IP_REQUEST_CNTL[0]), 0, 0 },
+	{ "mmDC_PGFSM_CONFIG_REG", REG_MMIO, 0x2d3, &mmDC_PGFSM_CONFIG_REG[0], sizeof(mmDC_PGFSM_CONFIG_REG)/sizeof(mmDC_PGFSM_CONFIG_REG[0]), 0, 0 },
+	{ "mmDC_PGFSM_WRITE_REG", REG_MMIO, 0x2d4, &mmDC_PGFSM_WRITE_REG[0], sizeof(mmDC_PGFSM_WRITE_REG)/sizeof(mmDC_PGFSM_WRITE_REG[0]), 0, 0 },
+	{ "mmDC_PGCNTL_STATUS_REG", REG_MMIO, 0x2d5, &mmDC_PGCNTL_STATUS_REG[0], sizeof(mmDC_PGCNTL_STATUS_REG)/sizeof(mmDC_PGCNTL_STATUS_REG[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_INDEX", REG_MMIO, 0x2d6, &mmDCPG_TEST_DEBUG_INDEX[0], sizeof(mmDCPG_TEST_DEBUG_INDEX)/sizeof(mmDCPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_DATA", REG_MMIO, 0x2d7, &mmDCPG_TEST_DEBUG_DATA[0], sizeof(mmDCPG_TEST_DEBUG_DATA)/sizeof(mmDCPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x2e, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x2f, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x2f09, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x2f0a, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x2f0b, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CONFIG", REG_MMIO, 0x2f5, &mmDMIF_ADDR_CONFIG[0], sizeof(mmDMIF_ADDR_CONFIG)/sizeof(mmDMIF_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmDMIF_CONTROL", REG_MMIO, 0x2f6, &mmDMIF_CONTROL[0], sizeof(mmDMIF_CONTROL)/sizeof(mmDMIF_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_STATUS", REG_MMIO, 0x2f7, &mmDMIF_STATUS[0], sizeof(mmDMIF_STATUS)/sizeof(mmDMIF_STATUS[0]), 0, 0 },
+	{ "mmDMIF_HW_DEBUG", REG_MMIO, 0x2f8, &mmDMIF_HW_DEBUG[0], sizeof(mmDMIF_HW_DEBUG)/sizeof(mmDMIF_HW_DEBUG[0]), 0, 0 },
+	{ "mmDMIF_ARBITRATION_CONTROL", REG_MMIO, 0x2f9, &mmDMIF_ARBITRATION_CONTROL[0], sizeof(mmDMIF_ARBITRATION_CONTROL)/sizeof(mmDMIF_ARBITRATION_CONTROL[0]), 0, 0 },
+	{ "mmPIPE0_ARBITRATION_CONTROL3", REG_MMIO, 0x2fa, &mmPIPE0_ARBITRATION_CONTROL3[0], sizeof(mmPIPE0_ARBITRATION_CONTROL3)/sizeof(mmPIPE0_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE1_ARBITRATION_CONTROL3", REG_MMIO, 0x2fb, &mmPIPE1_ARBITRATION_CONTROL3[0], sizeof(mmPIPE1_ARBITRATION_CONTROL3)/sizeof(mmPIPE1_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE2_ARBITRATION_CONTROL3", REG_MMIO, 0x2fc, &mmPIPE2_ARBITRATION_CONTROL3[0], sizeof(mmPIPE2_ARBITRATION_CONTROL3)/sizeof(mmPIPE2_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE3_ARBITRATION_CONTROL3", REG_MMIO, 0x2fd, &mmPIPE3_ARBITRATION_CONTROL3[0], sizeof(mmPIPE3_ARBITRATION_CONTROL3)/sizeof(mmPIPE3_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE4_ARBITRATION_CONTROL3", REG_MMIO, 0x2fe, &mmPIPE4_ARBITRATION_CONTROL3[0], sizeof(mmPIPE4_ARBITRATION_CONTROL3)/sizeof(mmPIPE4_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE5_ARBITRATION_CONTROL3", REG_MMIO, 0x2ff, &mmPIPE5_ARBITRATION_CONTROL3[0], sizeof(mmPIPE5_ARBITRATION_CONTROL3)/sizeof(mmPIPE5_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x3, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x3, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0", REG_SMC, 0x3, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0]), 0, 0 },
+	{ "ixAZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x3, &ixAZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL3", REG_SMC, 0x3, &ixAZALIA_INPUT_CRC0_CHANNEL3[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL3)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL3[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL3", REG_SMC, 0x3, &ixAZALIA_CRC0_CHANNEL3[0], sizeof(ixAZALIA_CRC0_CHANNEL3)/sizeof(ixAZALIA_CRC0_CHANNEL3[0]), 0, 0 },
+	{ "mmSTATE_CHANGE_STATUS", REG_MMIO, 0x3, &mmSTATE_CHANGE_STATUS[0], sizeof(mmSTATE_CHANGE_STATUS)/sizeof(mmSTATE_CHANGE_STATUS[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR2", REG_SMC, 0x3, &ixAUDIO_DESCRIPTOR2[0], sizeof(ixAUDIO_DESCRIPTOR2)/sizeof(ixAUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "ixDCIO_DEBUG3", REG_SMC, 0x3, &ixDCIO_DEBUG3[0], sizeof(ixDCIO_DEBUG3)/sizeof(ixDCIO_DEBUG3[0]), 0, 0 },
+	{ "ixFMT_DEBUG2", REG_SMC, 0x3, &ixFMT_DEBUG2[0], sizeof(ixFMT_DEBUG2)/sizeof(ixFMT_DEBUG2[0]), 0, 0 },
+	{ "ixATTR03", REG_SMC, 0x3, &ixATTR03[0], sizeof(ixATTR03)/sizeof(ixATTR03[0]), 0, 0 },
+	{ "ixSEQ03", REG_SMC, 0x3, &ixSEQ03[0], sizeof(ixSEQ03)/sizeof(ixSEQ03[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x30, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "mmDMIF_P_VMID", REG_MMIO, 0x300, &mmDMIF_P_VMID[0], sizeof(mmDMIF_P_VMID)/sizeof(mmDMIF_P_VMID[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_INDEX", REG_MMIO, 0x301, &mmDMIF_TEST_DEBUG_INDEX[0], sizeof(mmDMIF_TEST_DEBUG_INDEX)/sizeof(mmDMIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_DATA", REG_MMIO, 0x302, &mmDMIF_TEST_DEBUG_DATA[0], sizeof(mmDMIF_TEST_DEBUG_DATA)/sizeof(mmDMIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CALC", REG_MMIO, 0x303, &mmDMIF_ADDR_CALC[0], sizeof(mmDMIF_ADDR_CALC)/sizeof(mmDMIF_ADDR_CALC[0]), 0, 0 },
+	{ "mmDMIF_STATUS2", REG_MMIO, 0x304, &mmDMIF_STATUS2[0], sizeof(mmDMIF_STATUS2)/sizeof(mmDMIF_STATUS2[0]), 0, 0 },
+	{ "mmPIPE0_MAX_REQUESTS", REG_MMIO, 0x305, &mmPIPE0_MAX_REQUESTS[0], sizeof(mmPIPE0_MAX_REQUESTS)/sizeof(mmPIPE0_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE1_MAX_REQUESTS", REG_MMIO, 0x306, &mmPIPE1_MAX_REQUESTS[0], sizeof(mmPIPE1_MAX_REQUESTS)/sizeof(mmPIPE1_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE2_MAX_REQUESTS", REG_MMIO, 0x307, &mmPIPE2_MAX_REQUESTS[0], sizeof(mmPIPE2_MAX_REQUESTS)/sizeof(mmPIPE2_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE3_MAX_REQUESTS", REG_MMIO, 0x308, &mmPIPE3_MAX_REQUESTS[0], sizeof(mmPIPE3_MAX_REQUESTS)/sizeof(mmPIPE3_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE4_MAX_REQUESTS", REG_MMIO, 0x309, &mmPIPE4_MAX_REQUESTS[0], sizeof(mmPIPE4_MAX_REQUESTS)/sizeof(mmPIPE4_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE5_MAX_REQUESTS", REG_MMIO, 0x30a, &mmPIPE5_MAX_REQUESTS[0], sizeof(mmPIPE5_MAX_REQUESTS)/sizeof(mmPIPE5_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmLOW_POWER_TILING_CONTROL", REG_MMIO, 0x30b, &mmLOW_POWER_TILING_CONTROL[0], sizeof(mmLOW_POWER_TILING_CONTROL)/sizeof(mmLOW_POWER_TILING_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_CONTROL", REG_MMIO, 0x30c, &mmMCIF_CONTROL[0], sizeof(mmMCIF_CONTROL)/sizeof(mmMCIF_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WRITE_COMBINE_CONTROL", REG_MMIO, 0x30d, &mmMCIF_WRITE_COMBINE_CONTROL[0], sizeof(mmMCIF_WRITE_COMBINE_CONTROL)/sizeof(mmMCIF_WRITE_COMBINE_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_INDEX", REG_MMIO, 0x30e, &mmMCIF_TEST_DEBUG_INDEX[0], sizeof(mmMCIF_TEST_DEBUG_INDEX)/sizeof(mmMCIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_DATA", REG_MMIO, 0x30f, &mmMCIF_TEST_DEBUG_DATA[0], sizeof(mmMCIF_TEST_DEBUG_DATA)/sizeof(mmMCIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x31, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "mmMCIF_VMID", REG_MMIO, 0x310, &mmMCIF_VMID[0], sizeof(mmMCIF_VMID)/sizeof(mmMCIF_VMID[0]), 0, 0 },
+	{ "mmMCIF_MEM_CONTROL", REG_MMIO, 0x311, &mmMCIF_MEM_CONTROL[0], sizeof(mmMCIF_MEM_CONTROL)/sizeof(mmMCIF_MEM_CONTROL[0]), 0, 0 },
+	{ "mmCC_DC_PIPE_DIS", REG_MMIO, 0x312, &mmCC_DC_PIPE_DIS[0], sizeof(mmCC_DC_PIPE_DIS)/sizeof(mmCC_DC_PIPE_DIS[0]), 0, 0 },
+	{ "mmMC_DC_INTERFACE_NACK_STATUS", REG_MMIO, 0x313, &mmMC_DC_INTERFACE_NACK_STATUS[0], sizeof(mmMC_DC_INTERFACE_NACK_STATUS)/sizeof(mmMC_DC_INTERFACE_NACK_STATUS[0]), 0, 0 },
+	{ "mmRBBMIF_TIMEOUT", REG_MMIO, 0x314, &mmRBBMIF_TIMEOUT[0], sizeof(mmRBBMIF_TIMEOUT)/sizeof(mmRBBMIF_TIMEOUT[0]), 0, 0 },
+	{ "mmRBBMIF_STATUS", REG_MMIO, 0x315, &mmRBBMIF_STATUS[0], sizeof(mmRBBMIF_STATUS)/sizeof(mmRBBMIF_STATUS[0]), 0, 0 },
+	{ "mmRBBMIF_TIMEOUT_DIS", REG_MMIO, 0x316, &mmRBBMIF_TIMEOUT_DIS[0], sizeof(mmRBBMIF_TIMEOUT_DIS)/sizeof(mmRBBMIF_TIMEOUT_DIS[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATUS", REG_MMIO, 0x317, &mmDCI_MEM_PWR_STATUS[0], sizeof(mmDCI_MEM_PWR_STATUS)/sizeof(mmDCI_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATUS2", REG_MMIO, 0x318, &mmDCI_MEM_PWR_STATUS2[0], sizeof(mmDCI_MEM_PWR_STATUS2)/sizeof(mmDCI_MEM_PWR_STATUS2[0]), 0, 0 },
+	{ "mmDCI_CLK_CNTL", REG_MMIO, 0x319, &mmDCI_CLK_CNTL[0], sizeof(mmDCI_CLK_CNTL)/sizeof(mmDCI_CLK_CNTL[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL", REG_MMIO, 0x31b, &mmDCI_MEM_PWR_CNTL[0], sizeof(mmDCI_MEM_PWR_CNTL)/sizeof(mmDCI_MEM_PWR_CNTL[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL2", REG_MMIO, 0x31c, &mmDCI_MEM_PWR_CNTL2[0], sizeof(mmDCI_MEM_PWR_CNTL2)/sizeof(mmDCI_MEM_PWR_CNTL2[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL3", REG_MMIO, 0x31d, &mmDCI_MEM_PWR_CNTL3[0], sizeof(mmDCI_MEM_PWR_CNTL3)/sizeof(mmDCI_MEM_PWR_CNTL3[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_INDEX", REG_MMIO, 0x31e, &mmDCI_TEST_DEBUG_INDEX[0], sizeof(mmDCI_TEST_DEBUG_INDEX)/sizeof(mmDCI_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_DATA", REG_MMIO, 0x31f, &mmDCI_TEST_DEBUG_DATA[0], sizeof(mmDCI_TEST_DEBUG_DATA)/sizeof(mmDCI_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x32, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "mmDCI_DEBUG_CONFIG", REG_MMIO, 0x320, &mmDCI_DEBUG_CONFIG[0], sizeof(mmDCI_DEBUG_CONFIG)/sizeof(mmDCI_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE0_DMIF_BUFFER_CONTROL", REG_MMIO, 0x321, &mmPIPE0_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE0_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE0_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE1_DMIF_BUFFER_CONTROL", REG_MMIO, 0x322, &mmPIPE1_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE1_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE1_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE2_DMIF_BUFFER_CONTROL", REG_MMIO, 0x323, &mmPIPE2_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE2_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE2_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE3_DMIF_BUFFER_CONTROL", REG_MMIO, 0x324, &mmPIPE3_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE3_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE3_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE4_DMIF_BUFFER_CONTROL", REG_MMIO, 0x325, &mmPIPE4_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE4_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE4_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE5_DMIF_BUFFER_CONTROL", REG_MMIO, 0x326, &mmPIPE5_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE5_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE5_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmRBBMIF_STATUS_FLAG", REG_MMIO, 0x327, &mmRBBMIF_STATUS_FLAG[0], sizeof(mmRBBMIF_STATUS_FLAG)/sizeof(mmRBBMIF_STATUS_FLAG[0]), 0, 0 },
+	{ "mmDCI_SOFT_RESET", REG_MMIO, 0x328, &mmDCI_SOFT_RESET[0], sizeof(mmDCI_SOFT_RESET)/sizeof(mmDCI_SOFT_RESET[0]), 0, 0 },
+	{ "mmDMIF_URG_OVERRIDE", REG_MMIO, 0x329, &mmDMIF_URG_OVERRIDE[0], sizeof(mmDMIF_URG_OVERRIDE)/sizeof(mmDMIF_URG_OVERRIDE[0]), 0, 0 },
+	{ "mmPIPE6_ARBITRATION_CONTROL3", REG_MMIO, 0x32a, &mmPIPE6_ARBITRATION_CONTROL3[0], sizeof(mmPIPE6_ARBITRATION_CONTROL3)/sizeof(mmPIPE6_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE7_ARBITRATION_CONTROL3", REG_MMIO, 0x32b, &mmPIPE7_ARBITRATION_CONTROL3[0], sizeof(mmPIPE7_ARBITRATION_CONTROL3)/sizeof(mmPIPE7_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE6_MAX_REQUESTS", REG_MMIO, 0x32c, &mmPIPE6_MAX_REQUESTS[0], sizeof(mmPIPE6_MAX_REQUESTS)/sizeof(mmPIPE6_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE7_MAX_REQUESTS", REG_MMIO, 0x32d, &mmPIPE7_MAX_REQUESTS[0], sizeof(mmPIPE7_MAX_REQUESTS)/sizeof(mmPIPE7_MAX_REQUESTS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x33, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x34, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x35, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x36, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x36, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 },
+	{ "mmDC_PERFMON1_PERFCOUNTER_CNTL", REG_MMIO, 0x364, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFCOUNTER_STATE", REG_MMIO, 0x365, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x366, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CNTL", REG_MMIO, 0x367, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CVALUE_LOW", REG_MMIO, 0x368, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_HI", REG_MMIO, 0x369, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_LOW", REG_MMIO, 0x36a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x36b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x36c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CNTL2", REG_MMIO, 0x36e, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x37, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x37, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY", REG_SMC, 0x3702, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x3707, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x3708, &ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x3709, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x371c, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x371d, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x371e, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x371f, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION", REG_SMC, 0x3770, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x3771, &ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO", REG_SMC, 0x3772, &ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE", REG_SMC, 0x3777, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE", REG_SMC, 0x3778, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE", REG_SMC, 0x3779, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE", REG_SMC, 0x377a, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC", REG_SMC, 0x377b, &ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_HBR", REG_SMC, 0x377c, &ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX", REG_SMC, 0x3780, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA", REG_SMC, 0x3781, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x3785, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x3786, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x3787, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x3788, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x3789, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x378a, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x378b, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x378c, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x378d, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x378e, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x378f, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x3790, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x3791, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x3792, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x3793, &ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x3797, &ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x3798, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x3799, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x379a, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x379b, &ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x379c, &ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x379d, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x379e, &ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x38, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x38, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x3a, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x3b, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x3c, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x3d, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x3e, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 },
+	{ "mmXDMA_MC_PCIE_CLIENT_CONFIG", REG_MMIO, 0x3e0, &mmXDMA_MC_PCIE_CLIENT_CONFIG[0], sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG)/sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING1", REG_MMIO, 0x3e1, &mmXDMA_LOCAL_SURFACE_TILING1[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING1)/sizeof(mmXDMA_LOCAL_SURFACE_TILING1[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING2", REG_MMIO, 0x3e2, &mmXDMA_LOCAL_SURFACE_TILING2[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING2)/sizeof(mmXDMA_LOCAL_SURFACE_TILING2[0]), 0, 0 },
+	{ "mmXDMA_INTERRUPT", REG_MMIO, 0x3e3, &mmXDMA_INTERRUPT[0], sizeof(mmXDMA_INTERRUPT)/sizeof(mmXDMA_INTERRUPT[0]), 0, 0 },
+	{ "mmXDMA_CLOCK_GATING_CNTL", REG_MMIO, 0x3e4, &mmXDMA_CLOCK_GATING_CNTL[0], sizeof(mmXDMA_CLOCK_GATING_CNTL)/sizeof(mmXDMA_CLOCK_GATING_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MEM_POWER_CNTL", REG_MMIO, 0x3e6, &mmXDMA_MEM_POWER_CNTL[0], sizeof(mmXDMA_MEM_POWER_CNTL)/sizeof(mmXDMA_MEM_POWER_CNTL[0]), 0, 0 },
+	{ "mmXDMA_IF_BIF_STATUS", REG_MMIO, 0x3e7, &mmXDMA_IF_BIF_STATUS[0], sizeof(mmXDMA_IF_BIF_STATUS)/sizeof(mmXDMA_IF_BIF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_PERF_MEAS_STATUS", REG_MMIO, 0x3e8, &mmXDMA_PERF_MEAS_STATUS[0], sizeof(mmXDMA_PERF_MEAS_STATUS)/sizeof(mmXDMA_PERF_MEAS_STATUS[0]), 0, 0 },
+	{ "mmXDMA_IF_STATUS", REG_MMIO, 0x3e9, &mmXDMA_IF_STATUS[0], sizeof(mmXDMA_IF_STATUS)/sizeof(mmXDMA_IF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_INDEX", REG_MMIO, 0x3ea, &mmXDMA_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_TEST_DEBUG_INDEX)/sizeof(mmXDMA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_DATA", REG_MMIO, 0x3eb, &mmXDMA_TEST_DEBUG_DATA[0], sizeof(mmXDMA_TEST_DEBUG_DATA)/sizeof(mmXDMA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CNTL", REG_MMIO, 0x3ec, &mmXDMA_MSTR_CNTL[0], sizeof(mmXDMA_MSTR_CNTL)/sizeof(mmXDMA_MSTR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_STATUS", REG_MMIO, 0x3ed, &mmXDMA_MSTR_STATUS[0], sizeof(mmXDMA_MSTR_STATUS)/sizeof(mmXDMA_MSTR_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_CLIENT_CONFIG", REG_MMIO, 0x3ee, &mmXDMA_MSTR_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", REG_MMIO, 0x3ef, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x3f, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", REG_MMIO, 0x3f0, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x3f09, &ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x3f0c, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH", REG_SMC, 0x3f0e, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_PITCH", REG_MMIO, 0x3f1, &mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CMD_URGENT_CNTL", REG_MMIO, 0x3f2, &mmXDMA_MSTR_CMD_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL)/sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_URGENT_CNTL", REG_MMIO, 0x3f3, &mmXDMA_MSTR_MEM_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL)/sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PCIE_NACK_STATUS", REG_MMIO, 0x3f5, &mmXDMA_MSTR_PCIE_NACK_STATUS[0], sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS)/sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_NACK_STATUS", REG_MMIO, 0x3f6, &mmXDMA_MSTR_MEM_NACK_STATUS[0], sizeof(mmXDMA_MSTR_MEM_NACK_STATUS)/sizeof(mmXDMA_MSTR_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_VSYNC_GSL_CHECK", REG_MMIO, 0x3f7, &mmXDMA_MSTR_VSYNC_GSL_CHECK[0], sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK)/sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK[0]), 0, 0 },
+	{ "mmXDMA_RBBMIF_RDWR_CNTL", REG_MMIO, 0x3f8, &mmXDMA_RBBMIF_RDWR_CNTL[0], sizeof(mmXDMA_RBBMIF_RDWR_CNTL)/sizeof(mmXDMA_RBBMIF_RDWR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_PG_CONTROL", REG_MMIO, 0x3f9, &mmXDMA_PG_CONTROL[0], sizeof(mmXDMA_PG_CONTROL)/sizeof(mmXDMA_PG_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_PG_WDATA", REG_MMIO, 0x3fa, &mmXDMA_PG_WDATA[0], sizeof(mmXDMA_PG_WDATA)/sizeof(mmXDMA_PG_WDATA[0]), 0, 0 },
+	{ "mmXDMA_PG_STATUS", REG_MMIO, 0x3fb, &mmXDMA_PG_STATUS[0], sizeof(mmXDMA_PG_STATUS)/sizeof(mmXDMA_PG_STATUS[0]), 0, 0 },
+	{ "mmXDMA_AON_TEST_DEBUG_INDEX", REG_MMIO, 0x3fc, &mmXDMA_AON_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_AON_TEST_DEBUG_INDEX)/sizeof(mmXDMA_AON_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_AON_TEST_DEBUG_DATA", REG_MMIO, 0x3fd, &mmXDMA_AON_TEST_DEBUG_DATA[0], sizeof(mmXDMA_AON_TEST_DEBUG_DATA)/sizeof(mmXDMA_AON_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x4, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x4, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1", REG_SMC, 0x4, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0]), 0, 0 },
+	{ "ixAZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x4, &ixAZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL4", REG_SMC, 0x4, &ixAZALIA_INPUT_CRC0_CHANNEL4[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL4)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL4[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL4", REG_SMC, 0x4, &ixAZALIA_CRC0_CHANNEL4[0], sizeof(ixAZALIA_CRC0_CHANNEL4)/sizeof(ixAZALIA_CRC0_CHANNEL4[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR3", REG_SMC, 0x4, &ixAUDIO_DESCRIPTOR3[0], sizeof(ixAUDIO_DESCRIPTOR3)/sizeof(ixAUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "mmGLOBAL_STATUS", REG_MMIO, 0x4, &mmGLOBAL_STATUS[0], sizeof(mmGLOBAL_STATUS)/sizeof(mmGLOBAL_STATUS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG4", REG_SMC, 0x4, &ixDCIO_DEBUG4[0], sizeof(ixDCIO_DEBUG4)/sizeof(ixDCIO_DEBUG4[0]), 0, 0 },
+	{ "ixATTR04", REG_SMC, 0x4, &ixATTR04[0], sizeof(ixATTR04)/sizeof(ixATTR04[0]), 0, 0 },
+	{ "ixSEQ04", REG_SMC, 0x4, &ixSEQ04[0], sizeof(ixSEQ04)/sizeof(ixSEQ04[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x40, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, &mmXDMA_MSTR_PIPE_CNTL[0], sizeof(mmXDMA_MSTR_PIPE_CNTL)/sizeof(mmXDMA_MSTR_PIPE_CNTL[0]), 0, 0 },
+	{ "mmDCP3_GRPH_ENABLE", REG_MMIO, 0x4000, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_CONTROL", REG_MMIO, 0x4001, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4002, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SWAP_CNTL", REG_MMIO, 0x4003, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4004, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4005, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PITCH", REG_MMIO, 0x4006, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4007, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4008, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4009, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x400a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_START", REG_MMIO, 0x400b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_START", REG_MMIO, 0x400c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_END", REG_MMIO, 0x400d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_END", REG_MMIO, 0x400e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, &mmXDMA_MSTR_READ_COMMAND[0], sizeof(mmXDMA_MSTR_READ_COMMAND)/sizeof(mmXDMA_MSTR_READ_COMMAND[0]), 0, 0 },
+	{ "mmDCP3_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4010, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_UPDATE", REG_MMIO, 0x4011, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_CONTROL", REG_MMIO, 0x4012, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4013, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_CONTROL", REG_MMIO, 0x4014, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_STATUS", REG_MMIO, 0x4015, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4016, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4017, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4018, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4019, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_PITCH", REG_MMIO, 0x401a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x401b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_ENABLE", REG_MMIO, 0x401c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_CONTROL1", REG_MMIO, 0x401d, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_CONTROL2", REG_MMIO, 0x401e, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SWAP_CNTL", REG_MMIO, 0x401f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, &mmXDMA_MSTR_CHANNEL_DIM[0], sizeof(mmXDMA_MSTR_CHANNEL_DIM)/sizeof(mmXDMA_MSTR_CHANNEL_DIM[0]), 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4020, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_PITCH", REG_MMIO, 0x4021, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4022, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4023, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4024, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_START", REG_MMIO, 0x4025, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_END", REG_MMIO, 0x4026, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_UPDATE", REG_MMIO, 0x4027, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4028, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_DFQ_CONTROL", REG_MMIO, 0x4029, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_DFQ_STATUS", REG_MMIO, 0x402a, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x402b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x402c, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x402d, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x402e, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x402f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT", REG_MMIO, 0x403, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_HEIGHT", REG_MMIO, 0x403, &mmXDMA_MSTR_HEIGHT[0], sizeof(mmXDMA_MSTR_HEIGHT)/sizeof(mmXDMA_MSTR_HEIGHT[0]), 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4030, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4031, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4032, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4033, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4034, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_CONTROL", REG_MMIO, 0x4035, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C11_C12", REG_MMIO, 0x4036, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C13_C14", REG_MMIO, 0x4037, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C21_C22", REG_MMIO, 0x4038, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C23_C24", REG_MMIO, 0x4039, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C31_C32", REG_MMIO, 0x403a, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C33_C34", REG_MMIO, 0x403b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_CONTROL", REG_MMIO, 0x403c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C11_C12", REG_MMIO, 0x403d, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C13_C14", REG_MMIO, 0x403e, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C21_C22", REG_MMIO, 0x403f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, &mmXDMA_MSTR_REMOTE_SURFACE_BASE[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE[0]), 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4040, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4041, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4042, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4043, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4044, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4045, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4046, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4047, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4048, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4049, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x404a, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x404b, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x404c, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x404d, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x404e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, &mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DENORM_CONTROL", REG_MMIO, 0x4050, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_ROUND_CONTROL", REG_MMIO, 0x4051, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4052, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_CONTROL", REG_MMIO, 0x4053, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_ALPHA", REG_MMIO, 0x4054, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_RED", REG_MMIO, 0x4055, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_GREEN", REG_MMIO, 0x4056, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_BLUE", REG_MMIO, 0x4057, NULL, 0, 0, 0 },
+	{ "mmDCP3_DEGAMMA_CONTROL", REG_MMIO, 0x4058, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4059, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C11_C12", REG_MMIO, 0x405a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C13_C14", REG_MMIO, 0x405b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C21_C22", REG_MMIO, 0x405c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C23_C24", REG_MMIO, 0x405d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C31_C32", REG_MMIO, 0x405e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C33_C34", REG_MMIO, 0x405f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmDCP3_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4060, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_RANDOM_SEEDS", REG_MMIO, 0x4061, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4065, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_CONTROL", REG_MMIO, 0x4066, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4067, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SIZE", REG_MMIO, 0x4068, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4069, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_POSITION", REG_MMIO, 0x406a, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_HOT_SPOT", REG_MMIO, 0x406b, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR1", REG_MMIO, 0x406c, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR2", REG_MMIO, 0x406d, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_UPDATE", REG_MMIO, 0x406e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_MODE", REG_MMIO, 0x4078, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_INDEX", REG_MMIO, 0x4079, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_SEQ_COLOR", REG_MMIO, 0x407a, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_PWL_DATA", REG_MMIO, 0x407b, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_30_COLOR", REG_MMIO, 0x407c, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x407d, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x407e, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_AUTOFILL", REG_MMIO, 0x407f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, &mmXDMA_MSTR_CACHE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR[0]), 0, 0 },
+	{ "mmDCP3_DC_LUT_CONTROL", REG_MMIO, 0x4080, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4081, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4082, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4083, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4084, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4085, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4086, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CONTROL", REG_MMIO, 0x4087, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_MASK", REG_MMIO, 0x4088, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CURRENT", REG_MMIO, 0x4089, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_LAST", REG_MMIO, 0x408b, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG", REG_MMIO, 0x408d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x408e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, &mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DCP_GSL_CONTROL", REG_MMIO, 0x4090, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4091, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4092, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4093, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4094, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4095, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4096, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4097, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG2", REG_MMIO, 0x4098, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4099, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_STEREO_CONTROL", REG_MMIO, 0x409a, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x409c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x409d, NULL, 0, 0, 0 },
+	{ "mmDCP3_HW_ROTATION", REG_MMIO, 0x409e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x409f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE", REG_MMIO, 0x40a, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE", REG_MMIO, 0x40a, &mmXDMA_MSTR_CACHE[0], sizeof(mmXDMA_MSTR_CACHE)/sizeof(mmXDMA_MSTR_CACHE[0]), 0, 0 },
+	{ "mmDCP3_REGAMMA_CONTROL", REG_MMIO, 0x40a0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_INDEX", REG_MMIO, 0x40a1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_DATA", REG_MMIO, 0x40a2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x40a3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x40a4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x40a5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x40a6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x40a7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x40a8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x40a9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x40aa, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x40ab, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x40ac, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x40ad, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x40ae, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x40af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, &mmXDMA_MSTR_CHANNEL_START[0], sizeof(mmXDMA_MSTR_CHANNEL_START)/sizeof(mmXDMA_MSTR_CHANNEL_START[0]), 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x40b0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x40b1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x40b2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x40b3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x40b4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x40b5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x40b6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x40b7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x40b8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x40b9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x40ba, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x40bb, NULL, 0, 0, 0 },
+	{ "mmDCP3_ALPHA_CONTROL", REG_MMIO, 0x40bc, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x40bd, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x40be, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x40bf, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DATA_FORMAT", REG_MMIO, 0x40c0, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_MEMORY_CTRL", REG_MMIO, 0x40c1, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x40c2, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DESKTOP_HEIGHT", REG_MMIO, 0x40c3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE_START_END", REG_MMIO, 0x40c4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE2_START_END", REG_MMIO, 0x40c5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_V_COUNTER", REG_MMIO, 0x40c6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x40c7, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_INTERRUPT_MASK", REG_MMIO, 0x40c8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE_STATUS", REG_MMIO, 0x40c9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE2_STATUS", REG_MMIO, 0x40ca, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VBLANK_STATUS", REG_MMIO, 0x40cb, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SYNC_RESET_SEL", REG_MMIO, 0x40cc, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x40cd, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x40ce, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x40cf, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x40d0, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x40d1, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x40d2, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x40d3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x40d4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x40d5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x40d6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x40d7, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x40d8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x40d9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_STATUS", REG_MMIO, 0x40da, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x40dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, &mmXDMA_MSTR_PERFMEAS_STATUS[0], sizeof(mmXDMA_MSTR_PERFMEAS_STATUS)/sizeof(mmXDMA_MSTR_PERFMEAS_STATUS[0]), 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_MODE", REG_MMIO, 0x40e0, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x40e1, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x40e2, NULL, 0, 0, 0 },
+	{ "mmLB3_DC_MVP_LB_CONTROL", REG_MMIO, 0x40e3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG", REG_MMIO, 0x40e4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG2", REG_MMIO, 0x40e5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG3", REG_MMIO, 0x40e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, &mmXDMA_MSTR_PERFMEAS_CNTL[0], sizeof(mmXDMA_MSTR_PERFMEAS_CNTL)/sizeof(mmXDMA_MSTR_PERFMEAS_CNTL[0]), 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x40fe, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_DATA", REG_MMIO, 0x40ff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x41, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x410, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4100, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_SOFT_RESET", REG_MMIO, 0x4101, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_DBG_CONFIG", REG_MMIO, 0x4102, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x411, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x412, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFCOUNTER_CNTL", REG_MMIO, 0x4124, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFCOUNTER_STATE", REG_MMIO, 0x4125, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4126, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CNTL", REG_MMIO, 0x4127, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CVALUE_LOW", REG_MMIO, 0x4128, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_HI", REG_MMIO, 0x4129, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_LOW", REG_MMIO, 0x412a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x412b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x412c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CNTL2", REG_MMIO, 0x412e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT", REG_MMIO, 0x413, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4130, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4131, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4132, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4133, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4134, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4135, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4136, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4137, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4138, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4139, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_REPEATER_PROGRAM", REG_MMIO, 0x413a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_A", REG_MMIO, 0x413b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_B", REG_MMIO, 0x413c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_11", REG_MMIO, 0x413d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x414, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4140, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4141, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE", REG_MMIO, 0x4142, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TAP_CONTROL", REG_MMIO, 0x4143, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_CONTROL", REG_MMIO, 0x4144, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_BYPASS_CONTROL", REG_MMIO, 0x4145, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4146, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4147, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4148, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4149, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x414a, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x414b, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x414c, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT", REG_MMIO, 0x414d, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x414e, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ROUND_OFFSET", REG_MMIO, 0x414f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x415, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_UPDATE", REG_MMIO, 0x4151, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4153, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ALU_CONTROL", REG_MMIO, 0x4154, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4155, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_START_SECONDARY", REG_MMIO, 0x415b, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_START", REG_MMIO, 0x415c, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_SIZE", REG_MMIO, 0x415d, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x415e, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x415f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x416, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4160, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4161, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4162, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4163, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG2", REG_MMIO, 0x4169, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG", REG_MMIO, 0x416a, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x416b, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x416c, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_CONTROL", REG_MMIO, 0x416d, NULL, 0, 0, 0 },
+	{ "mmBLND3_SM_CONTROL2", REG_MMIO, 0x416e, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_CONTROL2", REG_MMIO, 0x416f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x417, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_UPDATE", REG_MMIO, 0x4170, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4171, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4173, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_DEBUG", REG_MMIO, 0x4174, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4175, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4176, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4177, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4178, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4179, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_WINDOW", REG_MMIO, 0x417a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_CONTROL", REG_MMIO, 0x417b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x417c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x417d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_DCFE_DBG_SEL", REG_MMIO, 0x417e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x417f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x418, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_TOTAL", REG_MMIO, 0x4180, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_START_END", REG_MMIO, 0x4181, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A", REG_MMIO, 0x4182, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4183, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B", REG_MMIO, 0x4184, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4185, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VBI_END", REG_MMIO, 0x4186, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL", REG_MMIO, 0x4187, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4188, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4189, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x418a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x418b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x418c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_BLANK_START_END", REG_MMIO, 0x418d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A", REG_MMIO, 0x418e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x418f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x419, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B", REG_MMIO, 0x4190, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4191, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4192, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4193, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_CNTL", REG_MMIO, 0x4194, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4195, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_CNTL", REG_MMIO, 0x4196, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4197, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4198, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FLOW_CONTROL", REG_MMIO, 0x4199, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x419a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x419b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CONTROL", REG_MMIO, 0x419c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_CONTROL", REG_MMIO, 0x419d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x419e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_STATUS", REG_MMIO, 0x419f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE", REG_MMIO, 0x41a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x41a0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x41a1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x41a2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS", REG_MMIO, 0x41a3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_POSITION", REG_MMIO, 0x41a4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x41a5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x41a6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x41a7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x41a8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_CONTROL", REG_MMIO, 0x41a9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_RESET", REG_MMIO, 0x41aa, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x41ab, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x41ac, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_STATUS", REG_MMIO, 0x41ad, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_CONTROL", REG_MMIO, 0x41ae, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x41af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x41b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x41b0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x41b1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x41b2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_START_LINE_CONTROL", REG_MMIO, 0x41b3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x41b4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_UPDATE_LOCK", REG_MMIO, 0x41b5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x41b6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x41b7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x41b8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x41b9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x41ba, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x41bb, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x41bc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_MASTER_UPDATE_LOCK", REG_MMIO, 0x41bd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_MASTER_UPDATE_MODE", REG_MMIO, 0x41be, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x41bf, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x41c0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_STATUS", REG_MMIO, 0x41c1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_EN", REG_MMIO, 0x41c2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x41c3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x41c4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x41c6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x41c7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x41c8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x41c9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x41ca, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x41cb, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR", REG_MMIO, 0x41cc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x41cd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x41ce, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x41cf, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x41d0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x41d1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x41d2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x41d3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC_CNTL", REG_MMIO, 0x41d4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x41d5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x41d6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x41d7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x41d8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_DATA_RG", REG_MMIO, 0x41d9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_DATA_B", REG_MMIO, 0x41da, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x41db, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x41dc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x41dd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x41de, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_DATA_RG", REG_MMIO, 0x41df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x41e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_DATA_B", REG_MMIO, 0x41e0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x41e1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x41e2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x41e3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x41e4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x41e5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x41e6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x41e7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x41e8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x41e9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x41ea, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x41eb, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x41ec, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x41ed, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CONTROL", REG_MMIO, 0x41ee, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x41ef, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x41f, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_DATA_0_1", REG_MMIO, 0x41f0, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_DATA_2_3", REG_MMIO, 0x41f1, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x41f2, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x41f3, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x41f4, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x41f5, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x41f6, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x41f7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x41f8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_CNTL", REG_MMIO, 0x41f9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_CNTL", REG_MMIO, 0x41fa, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x41fb, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x41fc, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x41fd, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x41fe, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DEBUG_CNTL", REG_MMIO, 0x41ff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x42, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x420, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_ENABLE", REG_MMIO, 0x4200, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_CONTROL", REG_MMIO, 0x4201, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4202, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SWAP_CNTL", REG_MMIO, 0x4203, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4204, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4205, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PITCH", REG_MMIO, 0x4206, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4207, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4208, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4209, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x420a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_START", REG_MMIO, 0x420b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_START", REG_MMIO, 0x420c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_END", REG_MMIO, 0x420d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_END", REG_MMIO, 0x420e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x421, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4210, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_UPDATE", REG_MMIO, 0x4211, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_CONTROL", REG_MMIO, 0x4212, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4213, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_CONTROL", REG_MMIO, 0x4214, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_STATUS", REG_MMIO, 0x4215, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4216, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4217, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4218, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4219, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_PITCH", REG_MMIO, 0x421a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x421b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_ENABLE", REG_MMIO, 0x421c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_CONTROL1", REG_MMIO, 0x421d, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_CONTROL2", REG_MMIO, 0x421e, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SWAP_CNTL", REG_MMIO, 0x421f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x422, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4220, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_PITCH", REG_MMIO, 0x4221, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4222, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4223, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4224, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_START", REG_MMIO, 0x4225, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_END", REG_MMIO, 0x4226, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_UPDATE", REG_MMIO, 0x4227, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4228, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_DFQ_CONTROL", REG_MMIO, 0x4229, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_DFQ_STATUS", REG_MMIO, 0x422a, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x422b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x422c, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x422d, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x422e, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x422f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT", REG_MMIO, 0x423, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4230, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4231, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4232, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4233, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4234, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_CONTROL", REG_MMIO, 0x4235, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C11_C12", REG_MMIO, 0x4236, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C13_C14", REG_MMIO, 0x4237, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C21_C22", REG_MMIO, 0x4238, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C23_C24", REG_MMIO, 0x4239, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C31_C32", REG_MMIO, 0x423a, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C33_C34", REG_MMIO, 0x423b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_CONTROL", REG_MMIO, 0x423c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C11_C12", REG_MMIO, 0x423d, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C13_C14", REG_MMIO, 0x423e, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C21_C22", REG_MMIO, 0x423f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x424, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4240, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4241, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4242, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4243, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4244, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4245, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4246, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4247, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4248, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4249, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x424a, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x424b, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x424c, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x424d, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x424e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x425, NULL, 0, 0, 0 },
+	{ "mmDCP4_DENORM_CONTROL", REG_MMIO, 0x4250, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_ROUND_CONTROL", REG_MMIO, 0x4251, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4252, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_CONTROL", REG_MMIO, 0x4253, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_ALPHA", REG_MMIO, 0x4254, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_RED", REG_MMIO, 0x4255, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_GREEN", REG_MMIO, 0x4256, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_BLUE", REG_MMIO, 0x4257, NULL, 0, 0, 0 },
+	{ "mmDCP4_DEGAMMA_CONTROL", REG_MMIO, 0x4258, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4259, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C11_C12", REG_MMIO, 0x425a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C13_C14", REG_MMIO, 0x425b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C21_C22", REG_MMIO, 0x425c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C23_C24", REG_MMIO, 0x425d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C31_C32", REG_MMIO, 0x425e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C33_C34", REG_MMIO, 0x425f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x426, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4260, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_RANDOM_SEEDS", REG_MMIO, 0x4261, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4265, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_CONTROL", REG_MMIO, 0x4266, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4267, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SIZE", REG_MMIO, 0x4268, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4269, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_POSITION", REG_MMIO, 0x426a, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_HOT_SPOT", REG_MMIO, 0x426b, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR1", REG_MMIO, 0x426c, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR2", REG_MMIO, 0x426d, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_UPDATE", REG_MMIO, 0x426e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x427, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_MODE", REG_MMIO, 0x4278, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_INDEX", REG_MMIO, 0x4279, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_SEQ_COLOR", REG_MMIO, 0x427a, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_PWL_DATA", REG_MMIO, 0x427b, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_30_COLOR", REG_MMIO, 0x427c, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x427d, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x427e, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_AUTOFILL", REG_MMIO, 0x427f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x428, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_CONTROL", REG_MMIO, 0x4280, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4281, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4282, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4283, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4284, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4285, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4286, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CONTROL", REG_MMIO, 0x4287, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_MASK", REG_MMIO, 0x4288, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CURRENT", REG_MMIO, 0x4289, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_LAST", REG_MMIO, 0x428b, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG", REG_MMIO, 0x428d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x428e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x429, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_GSL_CONTROL", REG_MMIO, 0x4290, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4291, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4292, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4293, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4294, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4295, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4296, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4297, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG2", REG_MMIO, 0x4298, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4299, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_STEREO_CONTROL", REG_MMIO, 0x429a, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x429c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x429d, NULL, 0, 0, 0 },
+	{ "mmDCP4_HW_ROTATION", REG_MMIO, 0x429e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x429f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE", REG_MMIO, 0x42a, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CONTROL", REG_MMIO, 0x42a0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_INDEX", REG_MMIO, 0x42a1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_DATA", REG_MMIO, 0x42a2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x42a3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x42a4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x42a5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x42a6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x42a7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x42a8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x42a9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x42aa, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x42ab, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x42ac, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x42ad, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x42ae, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x42af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x42b, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x42b0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x42b1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x42b2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x42b3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x42b4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x42b5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x42b6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x42b7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x42b8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x42b9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x42ba, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x42bb, NULL, 0, 0, 0 },
+	{ "mmDCP4_ALPHA_CONTROL", REG_MMIO, 0x42bc, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x42bd, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x42be, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x42bf, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DATA_FORMAT", REG_MMIO, 0x42c0, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_MEMORY_CTRL", REG_MMIO, 0x42c1, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x42c2, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DESKTOP_HEIGHT", REG_MMIO, 0x42c3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE_START_END", REG_MMIO, 0x42c4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE2_START_END", REG_MMIO, 0x42c5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_V_COUNTER", REG_MMIO, 0x42c6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x42c7, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_INTERRUPT_MASK", REG_MMIO, 0x42c8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE_STATUS", REG_MMIO, 0x42c9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE2_STATUS", REG_MMIO, 0x42ca, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VBLANK_STATUS", REG_MMIO, 0x42cb, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SYNC_RESET_SEL", REG_MMIO, 0x42cc, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x42cd, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x42ce, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x42cf, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x42d0, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x42d1, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x42d2, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x42d3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x42d4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x42d5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x42d6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x42d7, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x42d8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x42d9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_STATUS", REG_MMIO, 0x42da, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x42dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x42e, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_MODE", REG_MMIO, 0x42e0, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x42e1, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x42e2, NULL, 0, 0, 0 },
+	{ "mmLB4_DC_MVP_LB_CONTROL", REG_MMIO, 0x42e3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG", REG_MMIO, 0x42e4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG2", REG_MMIO, 0x42e5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG3", REG_MMIO, 0x42e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x42f, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x42fe, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_DATA", REG_MMIO, 0x42ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x430, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4300, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_SOFT_RESET", REG_MMIO, 0x4301, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_DBG_CONFIG", REG_MMIO, 0x4302, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x431, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x432, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFCOUNTER_CNTL", REG_MMIO, 0x4324, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFCOUNTER_STATE", REG_MMIO, 0x4325, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4326, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CNTL", REG_MMIO, 0x4327, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CVALUE_LOW", REG_MMIO, 0x4328, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_HI", REG_MMIO, 0x4329, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_LOW", REG_MMIO, 0x432a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x432b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x432c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CNTL2", REG_MMIO, 0x432e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT", REG_MMIO, 0x433, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4330, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4331, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4332, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4333, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4334, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4335, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4336, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4337, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4338, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4339, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_REPEATER_PROGRAM", REG_MMIO, 0x433a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_A", REG_MMIO, 0x433b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_B", REG_MMIO, 0x433c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_11", REG_MMIO, 0x433d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x434, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4340, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4341, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE", REG_MMIO, 0x4342, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TAP_CONTROL", REG_MMIO, 0x4343, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_CONTROL", REG_MMIO, 0x4344, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_BYPASS_CONTROL", REG_MMIO, 0x4345, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4346, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4347, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4348, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4349, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x434a, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x434b, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x434c, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT", REG_MMIO, 0x434d, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x434e, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ROUND_OFFSET", REG_MMIO, 0x434f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x435, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_UPDATE", REG_MMIO, 0x4351, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4353, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ALU_CONTROL", REG_MMIO, 0x4354, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4355, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_START_SECONDARY", REG_MMIO, 0x435b, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_START", REG_MMIO, 0x435c, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_SIZE", REG_MMIO, 0x435d, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x435e, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x435f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x436, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4360, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4361, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4362, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4363, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG2", REG_MMIO, 0x4369, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG", REG_MMIO, 0x436a, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x436b, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x436c, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_CONTROL", REG_MMIO, 0x436d, NULL, 0, 0, 0 },
+	{ "mmBLND4_SM_CONTROL2", REG_MMIO, 0x436e, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_CONTROL2", REG_MMIO, 0x436f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x437, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_UPDATE", REG_MMIO, 0x4370, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4371, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4373, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_DEBUG", REG_MMIO, 0x4374, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4375, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4376, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4377, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4378, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4379, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_WINDOW", REG_MMIO, 0x437a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_CONTROL", REG_MMIO, 0x437b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x437c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x437d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_DCFE_DBG_SEL", REG_MMIO, 0x437e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x437f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x438, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_TOTAL", REG_MMIO, 0x4380, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_START_END", REG_MMIO, 0x4381, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A", REG_MMIO, 0x4382, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4383, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B", REG_MMIO, 0x4384, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4385, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VBI_END", REG_MMIO, 0x4386, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL", REG_MMIO, 0x4387, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4388, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4389, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x438a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x438b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x438c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_BLANK_START_END", REG_MMIO, 0x438d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A", REG_MMIO, 0x438e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x438f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x439, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B", REG_MMIO, 0x4390, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4391, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4392, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4393, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_CNTL", REG_MMIO, 0x4394, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4395, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_CNTL", REG_MMIO, 0x4396, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4397, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4398, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FLOW_CONTROL", REG_MMIO, 0x4399, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x439a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x439b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CONTROL", REG_MMIO, 0x439c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_CONTROL", REG_MMIO, 0x439d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x439e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_STATUS", REG_MMIO, 0x439f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE", REG_MMIO, 0x43a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x43a0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x43a1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x43a2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS", REG_MMIO, 0x43a3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_POSITION", REG_MMIO, 0x43a4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x43a5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x43a6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x43a7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x43a8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_CONTROL", REG_MMIO, 0x43a9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_RESET", REG_MMIO, 0x43aa, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x43ab, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x43ac, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_STATUS", REG_MMIO, 0x43ad, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_CONTROL", REG_MMIO, 0x43ae, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x43af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x43b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x43b0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x43b1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x43b2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_START_LINE_CONTROL", REG_MMIO, 0x43b3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x43b4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_UPDATE_LOCK", REG_MMIO, 0x43b5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x43b6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x43b7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x43b8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x43b9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x43ba, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x43bb, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x43bc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_MASTER_UPDATE_LOCK", REG_MMIO, 0x43bd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_MASTER_UPDATE_MODE", REG_MMIO, 0x43be, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x43bf, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x43c0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_STATUS", REG_MMIO, 0x43c1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_EN", REG_MMIO, 0x43c2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x43c3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x43c4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x43c6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x43c7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x43c8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x43c9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x43ca, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x43cb, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR", REG_MMIO, 0x43cc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x43cd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x43ce, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x43cf, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x43d0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x43d1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x43d2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x43d3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC_CNTL", REG_MMIO, 0x43d4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x43d5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x43d6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x43d7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x43d8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_DATA_RG", REG_MMIO, 0x43d9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_DATA_B", REG_MMIO, 0x43da, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x43db, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x43dc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x43dd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x43de, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_DATA_RG", REG_MMIO, 0x43df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x43e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_DATA_B", REG_MMIO, 0x43e0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x43e1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x43e2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x43e3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x43e4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x43e5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x43e6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x43e7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x43e8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x43e9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x43ea, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x43eb, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x43ec, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x43ed, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CONTROL", REG_MMIO, 0x43ee, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x43ef, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x43f, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_DATA_0_1", REG_MMIO, 0x43f0, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_DATA_2_3", REG_MMIO, 0x43f1, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x43f2, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x43f3, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x43f4, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x43f5, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x43f6, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x43f7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x43f8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_CNTL", REG_MMIO, 0x43f9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_CNTL", REG_MMIO, 0x43fa, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x43fb, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x43fc, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x43fd, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x43fe, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DEBUG_CNTL", REG_MMIO, 0x43ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x440, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_ENABLE", REG_MMIO, 0x4400, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_CONTROL", REG_MMIO, 0x4401, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4402, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SWAP_CNTL", REG_MMIO, 0x4403, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4404, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4405, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PITCH", REG_MMIO, 0x4406, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4407, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4408, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4409, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x440a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_START", REG_MMIO, 0x440b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_START", REG_MMIO, 0x440c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_END", REG_MMIO, 0x440d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_END", REG_MMIO, 0x440e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x441, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4410, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_UPDATE", REG_MMIO, 0x4411, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_CONTROL", REG_MMIO, 0x4412, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4413, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_CONTROL", REG_MMIO, 0x4414, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_STATUS", REG_MMIO, 0x4415, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4416, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4417, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4418, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4419, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_PITCH", REG_MMIO, 0x441a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x441b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_ENABLE", REG_MMIO, 0x441c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_CONTROL1", REG_MMIO, 0x441d, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_CONTROL2", REG_MMIO, 0x441e, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SWAP_CNTL", REG_MMIO, 0x441f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x442, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4420, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_PITCH", REG_MMIO, 0x4421, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4422, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4423, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4424, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_START", REG_MMIO, 0x4425, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_END", REG_MMIO, 0x4426, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_UPDATE", REG_MMIO, 0x4427, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4428, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_DFQ_CONTROL", REG_MMIO, 0x4429, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_DFQ_STATUS", REG_MMIO, 0x442a, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x442b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x442c, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x442d, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x442e, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x442f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT", REG_MMIO, 0x443, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4430, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4431, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4432, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4433, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4434, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_CONTROL", REG_MMIO, 0x4435, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C11_C12", REG_MMIO, 0x4436, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C13_C14", REG_MMIO, 0x4437, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C21_C22", REG_MMIO, 0x4438, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C23_C24", REG_MMIO, 0x4439, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C31_C32", REG_MMIO, 0x443a, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C33_C34", REG_MMIO, 0x443b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_CONTROL", REG_MMIO, 0x443c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C11_C12", REG_MMIO, 0x443d, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C13_C14", REG_MMIO, 0x443e, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C21_C22", REG_MMIO, 0x443f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x444, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4440, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4441, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4442, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4443, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4444, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4445, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4446, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4447, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4448, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4449, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x444a, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x444b, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x444c, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x444d, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x444e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x445, NULL, 0, 0, 0 },
+	{ "mmDCP5_DENORM_CONTROL", REG_MMIO, 0x4450, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_ROUND_CONTROL", REG_MMIO, 0x4451, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4452, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_CONTROL", REG_MMIO, 0x4453, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_ALPHA", REG_MMIO, 0x4454, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_RED", REG_MMIO, 0x4455, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_GREEN", REG_MMIO, 0x4456, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_BLUE", REG_MMIO, 0x4457, NULL, 0, 0, 0 },
+	{ "mmDCP5_DEGAMMA_CONTROL", REG_MMIO, 0x4458, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4459, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C11_C12", REG_MMIO, 0x445a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C13_C14", REG_MMIO, 0x445b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C21_C22", REG_MMIO, 0x445c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C23_C24", REG_MMIO, 0x445d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C31_C32", REG_MMIO, 0x445e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C33_C34", REG_MMIO, 0x445f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x446, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4460, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_RANDOM_SEEDS", REG_MMIO, 0x4461, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4465, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_CONTROL", REG_MMIO, 0x4466, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4467, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SIZE", REG_MMIO, 0x4468, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4469, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_POSITION", REG_MMIO, 0x446a, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_HOT_SPOT", REG_MMIO, 0x446b, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR1", REG_MMIO, 0x446c, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR2", REG_MMIO, 0x446d, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_UPDATE", REG_MMIO, 0x446e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x447, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_MODE", REG_MMIO, 0x4478, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_INDEX", REG_MMIO, 0x4479, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_SEQ_COLOR", REG_MMIO, 0x447a, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_PWL_DATA", REG_MMIO, 0x447b, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_30_COLOR", REG_MMIO, 0x447c, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x447d, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x447e, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_AUTOFILL", REG_MMIO, 0x447f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x448, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_CONTROL", REG_MMIO, 0x4480, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4481, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4482, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4483, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4484, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4485, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4486, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CONTROL", REG_MMIO, 0x4487, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_MASK", REG_MMIO, 0x4488, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CURRENT", REG_MMIO, 0x4489, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_LAST", REG_MMIO, 0x448b, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG", REG_MMIO, 0x448d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x448e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x449, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_GSL_CONTROL", REG_MMIO, 0x4490, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4491, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4492, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4493, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4494, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4495, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4496, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4497, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG2", REG_MMIO, 0x4498, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4499, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_STEREO_CONTROL", REG_MMIO, 0x449a, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x449c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x449d, NULL, 0, 0, 0 },
+	{ "mmDCP5_HW_ROTATION", REG_MMIO, 0x449e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x449f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE", REG_MMIO, 0x44a, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CONTROL", REG_MMIO, 0x44a0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_INDEX", REG_MMIO, 0x44a1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_DATA", REG_MMIO, 0x44a2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x44a3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x44a4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x44a5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x44a6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x44a7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x44a8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x44a9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x44aa, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x44ab, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x44ac, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x44ad, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x44ae, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x44af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x44b, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x44b0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x44b1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x44b2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x44b3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x44b4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x44b5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x44b6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x44b7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x44b8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x44b9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x44ba, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x44bb, NULL, 0, 0, 0 },
+	{ "mmDCP5_ALPHA_CONTROL", REG_MMIO, 0x44bc, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x44bd, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x44be, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x44bf, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DATA_FORMAT", REG_MMIO, 0x44c0, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_MEMORY_CTRL", REG_MMIO, 0x44c1, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x44c2, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DESKTOP_HEIGHT", REG_MMIO, 0x44c3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE_START_END", REG_MMIO, 0x44c4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE2_START_END", REG_MMIO, 0x44c5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_V_COUNTER", REG_MMIO, 0x44c6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x44c7, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_INTERRUPT_MASK", REG_MMIO, 0x44c8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE_STATUS", REG_MMIO, 0x44c9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE2_STATUS", REG_MMIO, 0x44ca, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VBLANK_STATUS", REG_MMIO, 0x44cb, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SYNC_RESET_SEL", REG_MMIO, 0x44cc, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x44cd, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x44ce, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x44cf, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x44d0, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x44d1, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x44d2, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x44d3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x44d4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x44d5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x44d6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x44d7, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x44d8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x44d9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_STATUS", REG_MMIO, 0x44da, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x44dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x44e, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_MODE", REG_MMIO, 0x44e0, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x44e1, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x44e2, NULL, 0, 0, 0 },
+	{ "mmLB5_DC_MVP_LB_CONTROL", REG_MMIO, 0x44e3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG", REG_MMIO, 0x44e4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG2", REG_MMIO, 0x44e5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG3", REG_MMIO, 0x44e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x44f, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x44fe, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_DATA", REG_MMIO, 0x44ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x450, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4500, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_SOFT_RESET", REG_MMIO, 0x4501, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_DBG_CONFIG", REG_MMIO, 0x4502, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x451, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x452, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFCOUNTER_CNTL", REG_MMIO, 0x4524, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFCOUNTER_STATE", REG_MMIO, 0x4525, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4526, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CNTL", REG_MMIO, 0x4527, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CVALUE_LOW", REG_MMIO, 0x4528, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_HI", REG_MMIO, 0x4529, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_LOW", REG_MMIO, 0x452a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x452b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x452c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CNTL2", REG_MMIO, 0x452e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT", REG_MMIO, 0x453, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4530, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4531, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4532, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4533, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4534, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4535, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4536, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4537, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4538, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4539, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_REPEATER_PROGRAM", REG_MMIO, 0x453a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_A", REG_MMIO, 0x453b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_B", REG_MMIO, 0x453c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_11", REG_MMIO, 0x453d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x454, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4540, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4541, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE", REG_MMIO, 0x4542, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TAP_CONTROL", REG_MMIO, 0x4543, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_CONTROL", REG_MMIO, 0x4544, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_BYPASS_CONTROL", REG_MMIO, 0x4545, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4546, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4547, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4548, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4549, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x454a, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x454b, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x454c, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT", REG_MMIO, 0x454d, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x454e, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ROUND_OFFSET", REG_MMIO, 0x454f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x455, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_UPDATE", REG_MMIO, 0x4551, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4553, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ALU_CONTROL", REG_MMIO, 0x4554, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4555, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_START_SECONDARY", REG_MMIO, 0x455b, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_START", REG_MMIO, 0x455c, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_SIZE", REG_MMIO, 0x455d, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x455e, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x455f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x456, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4560, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4561, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4562, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4563, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG2", REG_MMIO, 0x4569, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG", REG_MMIO, 0x456a, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x456b, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x456c, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_CONTROL", REG_MMIO, 0x456d, NULL, 0, 0, 0 },
+	{ "mmBLND5_SM_CONTROL2", REG_MMIO, 0x456e, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_CONTROL2", REG_MMIO, 0x456f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x457, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_UPDATE", REG_MMIO, 0x4570, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4571, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4573, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_DEBUG", REG_MMIO, 0x4574, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4575, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4576, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4577, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4578, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4579, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_WINDOW", REG_MMIO, 0x457a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_CONTROL", REG_MMIO, 0x457b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x457c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x457d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_DCFE_DBG_SEL", REG_MMIO, 0x457e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x457f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x458, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_TOTAL", REG_MMIO, 0x4580, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_START_END", REG_MMIO, 0x4581, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A", REG_MMIO, 0x4582, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4583, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B", REG_MMIO, 0x4584, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4585, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VBI_END", REG_MMIO, 0x4586, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL", REG_MMIO, 0x4587, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4588, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4589, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x458a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x458b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x458c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_BLANK_START_END", REG_MMIO, 0x458d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A", REG_MMIO, 0x458e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x458f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x459, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B", REG_MMIO, 0x4590, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4591, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4592, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4593, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_CNTL", REG_MMIO, 0x4594, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4595, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_CNTL", REG_MMIO, 0x4596, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4597, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4598, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FLOW_CONTROL", REG_MMIO, 0x4599, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x459a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x459b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CONTROL", REG_MMIO, 0x459c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_CONTROL", REG_MMIO, 0x459d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x459e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_STATUS", REG_MMIO, 0x459f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE", REG_MMIO, 0x45a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x45a0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x45a1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x45a2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS", REG_MMIO, 0x45a3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_POSITION", REG_MMIO, 0x45a4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x45a5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x45a6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x45a7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x45a8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_CONTROL", REG_MMIO, 0x45a9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_RESET", REG_MMIO, 0x45aa, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x45ab, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x45ac, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_STATUS", REG_MMIO, 0x45ad, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_CONTROL", REG_MMIO, 0x45ae, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x45af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x45b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x45b0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x45b1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x45b2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_START_LINE_CONTROL", REG_MMIO, 0x45b3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x45b4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_UPDATE_LOCK", REG_MMIO, 0x45b5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x45b6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x45b7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x45b8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x45b9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x45ba, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x45bb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x45bc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_MASTER_UPDATE_LOCK", REG_MMIO, 0x45bd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_MASTER_UPDATE_MODE", REG_MMIO, 0x45be, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x45bf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x45c0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_STATUS", REG_MMIO, 0x45c1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_EN", REG_MMIO, 0x45c2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x45c3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x45c4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x45c6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x45c7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x45c8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x45c9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x45ca, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x45cb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR", REG_MMIO, 0x45cc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x45cd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x45ce, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x45cf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x45d0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x45d1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x45d2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x45d3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC_CNTL", REG_MMIO, 0x45d4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x45d5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x45d6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x45d7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x45d8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_DATA_RG", REG_MMIO, 0x45d9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_DATA_B", REG_MMIO, 0x45da, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x45db, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x45dc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x45dd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x45de, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_DATA_RG", REG_MMIO, 0x45df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x45e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_DATA_B", REG_MMIO, 0x45e0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x45e1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x45e2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x45e3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x45e4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x45e5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x45e6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x45e7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x45e8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x45e9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x45ea, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x45eb, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x45ec, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x45ed, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CONTROL", REG_MMIO, 0x45ee, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x45ef, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x45f, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_DATA_0_1", REG_MMIO, 0x45f0, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_DATA_2_3", REG_MMIO, 0x45f1, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x45f2, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x45f3, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x45f4, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x45f5, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x45f6, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x45f7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x45f8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_CNTL", REG_MMIO, 0x45f9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_CNTL", REG_MMIO, 0x45fa, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x45fb, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x45fc, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x45fd, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x45fe, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DEBUG_CNTL", REG_MMIO, 0x45ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CNTL", REG_MMIO, 0x460, &mmXDMA_SLV_CNTL[0], sizeof(mmXDMA_SLV_CNTL)/sizeof(mmXDMA_SLV_CNTL[0]), 0, 0 },
+	{ "mmUNP_GRPH_ENABLE", REG_MMIO, 0x4600, &mmUNP_GRPH_ENABLE[0], sizeof(mmUNP_GRPH_ENABLE)/sizeof(mmUNP_GRPH_ENABLE[0]), 0, 0 },
+	{ "mmUNP_GRPH_CONTROL", REG_MMIO, 0x4601, &mmUNP_GRPH_CONTROL[0], sizeof(mmUNP_GRPH_CONTROL)/sizeof(mmUNP_GRPH_CONTROL[0]), 0, 0 },
+	{ "mmUNP_GRPH_CONTROL_EXP", REG_MMIO, 0x4603, &mmUNP_GRPH_CONTROL_EXP[0], sizeof(mmUNP_GRPH_CONTROL_EXP)/sizeof(mmUNP_GRPH_CONTROL_EXP[0]), 0, 0 },
+	{ "mmUNP_GRPH_SWAP_CNTL", REG_MMIO, 0x4605, &mmUNP_GRPH_SWAP_CNTL[0], sizeof(mmUNP_GRPH_SWAP_CNTL)/sizeof(mmUNP_GRPH_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L", REG_MMIO, 0x4606, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x4607, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4608, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4609, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x460a, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x460b, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x460c, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x460d, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L", REG_MMIO, 0x460e, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x460f, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_CLIENT_CONFIG", REG_MMIO, 0x461, &mmXDMA_SLV_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4610, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4611, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x4612, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x4613, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4614, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4615, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_PITCH_L", REG_MMIO, 0x4616, &mmUNP_GRPH_PITCH_L[0], sizeof(mmUNP_GRPH_PITCH_L)/sizeof(mmUNP_GRPH_PITCH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PITCH_C", REG_MMIO, 0x4617, &mmUNP_GRPH_PITCH_C[0], sizeof(mmUNP_GRPH_PITCH_C)/sizeof(mmUNP_GRPH_PITCH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_X_L", REG_MMIO, 0x4618, &mmUNP_GRPH_SURFACE_OFFSET_X_L[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_L)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_X_C", REG_MMIO, 0x4619, &mmUNP_GRPH_SURFACE_OFFSET_X_C[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_C)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_Y_L", REG_MMIO, 0x461a, &mmUNP_GRPH_SURFACE_OFFSET_Y_L[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_L)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_Y_C", REG_MMIO, 0x461b, &mmUNP_GRPH_SURFACE_OFFSET_Y_C[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_C)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_X_START_L", REG_MMIO, 0x461c, &mmUNP_GRPH_X_START_L[0], sizeof(mmUNP_GRPH_X_START_L)/sizeof(mmUNP_GRPH_X_START_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_X_START_C", REG_MMIO, 0x461d, &mmUNP_GRPH_X_START_C[0], sizeof(mmUNP_GRPH_X_START_C)/sizeof(mmUNP_GRPH_X_START_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_Y_START_L", REG_MMIO, 0x461e, &mmUNP_GRPH_Y_START_L[0], sizeof(mmUNP_GRPH_Y_START_L)/sizeof(mmUNP_GRPH_Y_START_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_Y_START_C", REG_MMIO, 0x461f, &mmUNP_GRPH_Y_START_C[0], sizeof(mmUNP_GRPH_Y_START_C)/sizeof(mmUNP_GRPH_Y_START_C[0]), 0, 0 },
+	{ "mmXDMA_SLV_SLS_PITCH", REG_MMIO, 0x462, &mmXDMA_SLV_SLS_PITCH[0], sizeof(mmXDMA_SLV_SLS_PITCH)/sizeof(mmXDMA_SLV_SLS_PITCH[0]), 0, 0 },
+	{ "mmUNP_GRPH_X_END_L", REG_MMIO, 0x4620, &mmUNP_GRPH_X_END_L[0], sizeof(mmUNP_GRPH_X_END_L)/sizeof(mmUNP_GRPH_X_END_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_X_END_C", REG_MMIO, 0x4621, &mmUNP_GRPH_X_END_C[0], sizeof(mmUNP_GRPH_X_END_C)/sizeof(mmUNP_GRPH_X_END_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_Y_END_L", REG_MMIO, 0x4622, &mmUNP_GRPH_Y_END_L[0], sizeof(mmUNP_GRPH_Y_END_L)/sizeof(mmUNP_GRPH_Y_END_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_Y_END_C", REG_MMIO, 0x4623, &mmUNP_GRPH_Y_END_C[0], sizeof(mmUNP_GRPH_Y_END_C)/sizeof(mmUNP_GRPH_Y_END_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_UPDATE", REG_MMIO, 0x4624, &mmUNP_GRPH_UPDATE[0], sizeof(mmUNP_GRPH_UPDATE)/sizeof(mmUNP_GRPH_UPDATE[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L", REG_MMIO, 0x4625, &mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C", REG_MMIO, 0x4626, &mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L", REG_MMIO, 0x4627, &mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C", REG_MMIO, 0x4628, &mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_DFQ_CONTROL", REG_MMIO, 0x4629, &mmUNP_GRPH_DFQ_CONTROL[0], sizeof(mmUNP_GRPH_DFQ_CONTROL)/sizeof(mmUNP_GRPH_DFQ_CONTROL[0]), 0, 0 },
+	{ "mmUNP_GRPH_DFQ_STATUS", REG_MMIO, 0x462a, &mmUNP_GRPH_DFQ_STATUS[0], sizeof(mmUNP_GRPH_DFQ_STATUS)/sizeof(mmUNP_GRPH_DFQ_STATUS[0]), 0, 0 },
+	{ "mmUNP_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x462b, &mmUNP_GRPH_INTERRUPT_STATUS[0], sizeof(mmUNP_GRPH_INTERRUPT_STATUS)/sizeof(mmUNP_GRPH_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmUNP_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x462c, &mmUNP_GRPH_INTERRUPT_CONTROL[0], sizeof(mmUNP_GRPH_INTERRUPT_CONTROL)/sizeof(mmUNP_GRPH_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmUNP_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x462e, &mmUNP_GRPH_STEREOSYNC_FLIP[0], sizeof(mmUNP_GRPH_STEREOSYNC_FLIP)/sizeof(mmUNP_GRPH_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmUNP_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x462f, &mmUNP_GRPH_FLIP_RATE_CNTL[0], sizeof(mmUNP_GRPH_FLIP_RATE_CNTL)/sizeof(mmUNP_GRPH_FLIP_RATE_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_URGENT_CNTL", REG_MMIO, 0x463, &mmXDMA_SLV_READ_URGENT_CNTL[0], sizeof(mmXDMA_SLV_READ_URGENT_CNTL)/sizeof(mmXDMA_SLV_READ_URGENT_CNTL[0]), 0, 0 },
+	{ "mmUNP_CRC_CONTROL", REG_MMIO, 0x4630, &mmUNP_CRC_CONTROL[0], sizeof(mmUNP_CRC_CONTROL)/sizeof(mmUNP_CRC_CONTROL[0]), 0, 0 },
+	{ "mmUNP_CRC_MASK", REG_MMIO, 0x4631, &mmUNP_CRC_MASK[0], sizeof(mmUNP_CRC_MASK)/sizeof(mmUNP_CRC_MASK[0]), 0, 0 },
+	{ "mmUNP_CRC_CURRENT", REG_MMIO, 0x4632, &mmUNP_CRC_CURRENT[0], sizeof(mmUNP_CRC_CURRENT)/sizeof(mmUNP_CRC_CURRENT[0]), 0, 0 },
+	{ "mmUNP_CRC_LAST", REG_MMIO, 0x4633, &mmUNP_CRC_LAST[0], sizeof(mmUNP_CRC_LAST)/sizeof(mmUNP_CRC_LAST[0]), 0, 0 },
+	{ "mmUNP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4634, &mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[0], sizeof(mmUNP_LB_DATA_GAP_BETWEEN_CHUNK)/sizeof(mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[0]), 0, 0 },
+	{ "mmUNP_HW_ROTATION", REG_MMIO, 0x4635, &mmUNP_HW_ROTATION[0], sizeof(mmUNP_HW_ROTATION)/sizeof(mmUNP_HW_ROTATION[0]), 0, 0 },
+	{ "mmUNP_DEBUG", REG_MMIO, 0x4636, &mmUNP_DEBUG[0], sizeof(mmUNP_DEBUG)/sizeof(mmUNP_DEBUG[0]), 0, 0 },
+	{ "mmUNP_DEBUG2", REG_MMIO, 0x4637, &mmUNP_DEBUG2[0], sizeof(mmUNP_DEBUG2)/sizeof(mmUNP_DEBUG2[0]), 0, 0 },
+	{ "mmUNP_TEST_DEBUG_INDEX", REG_MMIO, 0x4638, &mmUNP_TEST_DEBUG_INDEX[0], sizeof(mmUNP_TEST_DEBUG_INDEX)/sizeof(mmUNP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmUNP_TEST_DEBUG_DATA", REG_MMIO, 0x4639, &mmUNP_TEST_DEBUG_DATA[0], sizeof(mmUNP_TEST_DEBUG_DATA)/sizeof(mmUNP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmLBV_DATA_FORMAT", REG_MMIO, 0x463c, &mmLBV_DATA_FORMAT[0], sizeof(mmLBV_DATA_FORMAT)/sizeof(mmLBV_DATA_FORMAT[0]), 0, 0 },
+	{ "mmLBV_MEMORY_CTRL", REG_MMIO, 0x463d, &mmLBV_MEMORY_CTRL[0], sizeof(mmLBV_MEMORY_CTRL)/sizeof(mmLBV_MEMORY_CTRL[0]), 0, 0 },
+	{ "mmLBV_MEMORY_SIZE_STATUS", REG_MMIO, 0x463e, &mmLBV_MEMORY_SIZE_STATUS[0], sizeof(mmLBV_MEMORY_SIZE_STATUS)/sizeof(mmLBV_MEMORY_SIZE_STATUS[0]), 0, 0 },
+	{ "mmLBV_DESKTOP_HEIGHT", REG_MMIO, 0x463f, &mmLBV_DESKTOP_HEIGHT[0], sizeof(mmLBV_DESKTOP_HEIGHT)/sizeof(mmLBV_DESKTOP_HEIGHT[0]), 0, 0 },
+	{ "mmXDMA_SLV_WRITE_URGENT_CNTL", REG_MMIO, 0x464, &mmXDMA_SLV_WRITE_URGENT_CNTL[0], sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL)/sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL[0]), 0, 0 },
+	{ "mmLBV_VLINE_START_END", REG_MMIO, 0x4640, &mmLBV_VLINE_START_END[0], sizeof(mmLBV_VLINE_START_END)/sizeof(mmLBV_VLINE_START_END[0]), 0, 0 },
+	{ "mmLBV_VLINE2_START_END", REG_MMIO, 0x4641, &mmLBV_VLINE2_START_END[0], sizeof(mmLBV_VLINE2_START_END)/sizeof(mmLBV_VLINE2_START_END[0]), 0, 0 },
+	{ "mmLBV_V_COUNTER", REG_MMIO, 0x4642, &mmLBV_V_COUNTER[0], sizeof(mmLBV_V_COUNTER)/sizeof(mmLBV_V_COUNTER[0]), 0, 0 },
+	{ "mmLBV_SNAPSHOT_V_COUNTER", REG_MMIO, 0x4643, &mmLBV_SNAPSHOT_V_COUNTER[0], sizeof(mmLBV_SNAPSHOT_V_COUNTER)/sizeof(mmLBV_SNAPSHOT_V_COUNTER[0]), 0, 0 },
+	{ "mmLBV_V_COUNTER_CHROMA", REG_MMIO, 0x4644, &mmLBV_V_COUNTER_CHROMA[0], sizeof(mmLBV_V_COUNTER_CHROMA)/sizeof(mmLBV_V_COUNTER_CHROMA[0]), 0, 0 },
+	{ "mmLBV_SNAPSHOT_V_COUNTER_CHROMA", REG_MMIO, 0x4645, &mmLBV_SNAPSHOT_V_COUNTER_CHROMA[0], sizeof(mmLBV_SNAPSHOT_V_COUNTER_CHROMA)/sizeof(mmLBV_SNAPSHOT_V_COUNTER_CHROMA[0]), 0, 0 },
+	{ "mmLBV_INTERRUPT_MASK", REG_MMIO, 0x4646, &mmLBV_INTERRUPT_MASK[0], sizeof(mmLBV_INTERRUPT_MASK)/sizeof(mmLBV_INTERRUPT_MASK[0]), 0, 0 },
+	{ "mmLBV_VLINE_STATUS", REG_MMIO, 0x4647, &mmLBV_VLINE_STATUS[0], sizeof(mmLBV_VLINE_STATUS)/sizeof(mmLBV_VLINE_STATUS[0]), 0, 0 },
+	{ "mmLBV_VLINE2_STATUS", REG_MMIO, 0x4648, &mmLBV_VLINE2_STATUS[0], sizeof(mmLBV_VLINE2_STATUS)/sizeof(mmLBV_VLINE2_STATUS[0]), 0, 0 },
+	{ "mmLBV_VBLANK_STATUS", REG_MMIO, 0x4649, &mmLBV_VBLANK_STATUS[0], sizeof(mmLBV_VBLANK_STATUS)/sizeof(mmLBV_VBLANK_STATUS[0]), 0, 0 },
+	{ "mmLBV_SYNC_RESET_SEL", REG_MMIO, 0x464a, &mmLBV_SYNC_RESET_SEL[0], sizeof(mmLBV_SYNC_RESET_SEL)/sizeof(mmLBV_SYNC_RESET_SEL[0]), 0, 0 },
+	{ "mmLBV_BLACK_KEYER_R_CR", REG_MMIO, 0x464b, &mmLBV_BLACK_KEYER_R_CR[0], sizeof(mmLBV_BLACK_KEYER_R_CR)/sizeof(mmLBV_BLACK_KEYER_R_CR[0]), 0, 0 },
+	{ "mmLBV_BLACK_KEYER_G_Y", REG_MMIO, 0x464c, &mmLBV_BLACK_KEYER_G_Y[0], sizeof(mmLBV_BLACK_KEYER_G_Y)/sizeof(mmLBV_BLACK_KEYER_G_Y[0]), 0, 0 },
+	{ "mmLBV_BLACK_KEYER_B_CB", REG_MMIO, 0x464d, &mmLBV_BLACK_KEYER_B_CB[0], sizeof(mmLBV_BLACK_KEYER_B_CB)/sizeof(mmLBV_BLACK_KEYER_B_CB[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_CTRL", REG_MMIO, 0x464e, &mmLBV_KEYER_COLOR_CTRL[0], sizeof(mmLBV_KEYER_COLOR_CTRL)/sizeof(mmLBV_KEYER_COLOR_CTRL[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_R_CR", REG_MMIO, 0x464f, &mmLBV_KEYER_COLOR_R_CR[0], sizeof(mmLBV_KEYER_COLOR_R_CR)/sizeof(mmLBV_KEYER_COLOR_R_CR[0]), 0, 0 },
+	{ "mmXDMA_SLV_WB_RATE_CNTL", REG_MMIO, 0x465, &mmXDMA_SLV_WB_RATE_CNTL[0], sizeof(mmXDMA_SLV_WB_RATE_CNTL)/sizeof(mmXDMA_SLV_WB_RATE_CNTL[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_G_Y", REG_MMIO, 0x4650, &mmLBV_KEYER_COLOR_G_Y[0], sizeof(mmLBV_KEYER_COLOR_G_Y)/sizeof(mmLBV_KEYER_COLOR_G_Y[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_B_CB", REG_MMIO, 0x4651, &mmLBV_KEYER_COLOR_B_CB[0], sizeof(mmLBV_KEYER_COLOR_B_CB)/sizeof(mmLBV_KEYER_COLOR_B_CB[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x4652, &mmLBV_KEYER_COLOR_REP_R_CR[0], sizeof(mmLBV_KEYER_COLOR_REP_R_CR)/sizeof(mmLBV_KEYER_COLOR_REP_R_CR[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x4653, &mmLBV_KEYER_COLOR_REP_G_Y[0], sizeof(mmLBV_KEYER_COLOR_REP_G_Y)/sizeof(mmLBV_KEYER_COLOR_REP_G_Y[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x4654, &mmLBV_KEYER_COLOR_REP_B_CB[0], sizeof(mmLBV_KEYER_COLOR_REP_B_CB)/sizeof(mmLBV_KEYER_COLOR_REP_B_CB[0]), 0, 0 },
+	{ "mmLBV_BUFFER_LEVEL_STATUS", REG_MMIO, 0x4655, &mmLBV_BUFFER_LEVEL_STATUS[0], sizeof(mmLBV_BUFFER_LEVEL_STATUS)/sizeof(mmLBV_BUFFER_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmLBV_BUFFER_URGENCY_CTRL", REG_MMIO, 0x4656, &mmLBV_BUFFER_URGENCY_CTRL[0], sizeof(mmLBV_BUFFER_URGENCY_CTRL)/sizeof(mmLBV_BUFFER_URGENCY_CTRL[0]), 0, 0 },
+	{ "mmLBV_BUFFER_URGENCY_STATUS", REG_MMIO, 0x4657, &mmLBV_BUFFER_URGENCY_STATUS[0], sizeof(mmLBV_BUFFER_URGENCY_STATUS)/sizeof(mmLBV_BUFFER_URGENCY_STATUS[0]), 0, 0 },
+	{ "mmLBV_BUFFER_STATUS", REG_MMIO, 0x4658, &mmLBV_BUFFER_STATUS[0], sizeof(mmLBV_BUFFER_STATUS)/sizeof(mmLBV_BUFFER_STATUS[0]), 0, 0 },
+	{ "mmLBV_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x4659, &mmLBV_NO_OUTSTANDING_REQ_STATUS[0], sizeof(mmLBV_NO_OUTSTANDING_REQ_STATUS)/sizeof(mmLBV_NO_OUTSTANDING_REQ_STATUS[0]), 0, 0 },
+	{ "mmLBV_DEBUG", REG_MMIO, 0x465a, &mmLBV_DEBUG[0], sizeof(mmLBV_DEBUG)/sizeof(mmLBV_DEBUG[0]), 0, 0 },
+	{ "mmLBV_DEBUG2", REG_MMIO, 0x465b, &mmLBV_DEBUG2[0], sizeof(mmLBV_DEBUG2)/sizeof(mmLBV_DEBUG2[0]), 0, 0 },
+	{ "mmLBV_DEBUG3", REG_MMIO, 0x465c, &mmLBV_DEBUG3[0], sizeof(mmLBV_DEBUG3)/sizeof(mmLBV_DEBUG3[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_MINMAX", REG_MMIO, 0x466, &mmXDMA_SLV_READ_LATENCY_MINMAX[0], sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX)/sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX[0]), 0, 0 },
+	{ "mmLBV_TEST_DEBUG_INDEX", REG_MMIO, 0x4666, &mmLBV_TEST_DEBUG_INDEX[0], sizeof(mmLBV_TEST_DEBUG_INDEX)/sizeof(mmLBV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmLBV_TEST_DEBUG_DATA", REG_MMIO, 0x4667, &mmLBV_TEST_DEBUG_DATA[0], sizeof(mmLBV_TEST_DEBUG_DATA)/sizeof(mmLBV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_AVE", REG_MMIO, 0x467, &mmXDMA_SLV_READ_LATENCY_AVE[0], sizeof(mmXDMA_SLV_READ_LATENCY_AVE)/sizeof(mmXDMA_SLV_READ_LATENCY_AVE[0]), 0, 0 },
+	{ "mmSCLV_COEF_RAM_SELECT", REG_MMIO, 0x4670, &mmSCLV_COEF_RAM_SELECT[0], sizeof(mmSCLV_COEF_RAM_SELECT)/sizeof(mmSCLV_COEF_RAM_SELECT[0]), 0, 0 },
+	{ "mmSCLV_COEF_RAM_TAP_DATA", REG_MMIO, 0x4671, &mmSCLV_COEF_RAM_TAP_DATA[0], sizeof(mmSCLV_COEF_RAM_TAP_DATA)/sizeof(mmSCLV_COEF_RAM_TAP_DATA[0]), 0, 0 },
+	{ "mmSCLV_MODE", REG_MMIO, 0x4672, &mmSCLV_MODE[0], sizeof(mmSCLV_MODE)/sizeof(mmSCLV_MODE[0]), 0, 0 },
+	{ "mmSCLV_TAP_CONTROL", REG_MMIO, 0x4673, &mmSCLV_TAP_CONTROL[0], sizeof(mmSCLV_TAP_CONTROL)/sizeof(mmSCLV_TAP_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_CONTROL", REG_MMIO, 0x4674, &mmSCLV_CONTROL[0], sizeof(mmSCLV_CONTROL)/sizeof(mmSCLV_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4675, &mmSCLV_MANUAL_REPLICATE_CONTROL[0], sizeof(mmSCLV_MANUAL_REPLICATE_CONTROL)/sizeof(mmSCLV_MANUAL_REPLICATE_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4676, &mmSCLV_AUTOMATIC_MODE_CONTROL[0], sizeof(mmSCLV_AUTOMATIC_MODE_CONTROL)/sizeof(mmSCLV_AUTOMATIC_MODE_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_CONTROL", REG_MMIO, 0x4677, &mmSCLV_HORZ_FILTER_CONTROL[0], sizeof(mmSCLV_HORZ_FILTER_CONTROL)/sizeof(mmSCLV_HORZ_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4678, &mmSCLV_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO)/sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT", REG_MMIO, 0x4679, &mmSCLV_HORZ_FILTER_INIT[0], sizeof(mmSCLV_HORZ_FILTER_INIT)/sizeof(mmSCLV_HORZ_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x467a, &mmSCLV_HORZ_FILTER_SCALE_RATIO_C[0], sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO_C)/sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO_C[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT_C", REG_MMIO, 0x467b, &mmSCLV_HORZ_FILTER_INIT_C[0], sizeof(mmSCLV_HORZ_FILTER_INIT_C)/sizeof(mmSCLV_HORZ_FILTER_INIT_C[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_CONTROL", REG_MMIO, 0x467c, &mmSCLV_VERT_FILTER_CONTROL[0], sizeof(mmSCLV_VERT_FILTER_CONTROL)/sizeof(mmSCLV_VERT_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x467d, &mmSCLV_VERT_FILTER_SCALE_RATIO[0], sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO)/sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT", REG_MMIO, 0x467e, &mmSCLV_VERT_FILTER_INIT[0], sizeof(mmSCLV_VERT_FILTER_INIT)/sizeof(mmSCLV_VERT_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_BOT", REG_MMIO, 0x467f, &mmSCLV_VERT_FILTER_INIT_BOT[0], sizeof(mmSCLV_VERT_FILTER_INIT_BOT)/sizeof(mmSCLV_VERT_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmXDMA_SLV_PCIE_NACK_STATUS", REG_MMIO, 0x468, &mmXDMA_SLV_PCIE_NACK_STATUS[0], sizeof(mmXDMA_SLV_PCIE_NACK_STATUS)/sizeof(mmXDMA_SLV_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x4680, &mmSCLV_VERT_FILTER_SCALE_RATIO_C[0], sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO_C)/sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO_C[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_C", REG_MMIO, 0x4681, &mmSCLV_VERT_FILTER_INIT_C[0], sizeof(mmSCLV_VERT_FILTER_INIT_C)/sizeof(mmSCLV_VERT_FILTER_INIT_C[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x4682, &mmSCLV_VERT_FILTER_INIT_BOT_C[0], sizeof(mmSCLV_VERT_FILTER_INIT_BOT_C)/sizeof(mmSCLV_VERT_FILTER_INIT_BOT_C[0]), 0, 0 },
+	{ "mmSCLV_ROUND_OFFSET", REG_MMIO, 0x4683, &mmSCLV_ROUND_OFFSET[0], sizeof(mmSCLV_ROUND_OFFSET)/sizeof(mmSCLV_ROUND_OFFSET[0]), 0, 0 },
+	{ "mmSCLV_UPDATE", REG_MMIO, 0x4684, &mmSCLV_UPDATE[0], sizeof(mmSCLV_UPDATE)/sizeof(mmSCLV_UPDATE[0]), 0, 0 },
+	{ "mmSCLV_ALU_CONTROL", REG_MMIO, 0x4685, &mmSCLV_ALU_CONTROL[0], sizeof(mmSCLV_ALU_CONTROL)/sizeof(mmSCLV_ALU_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_START", REG_MMIO, 0x4686, &mmSCLV_VIEWPORT_START[0], sizeof(mmSCLV_VIEWPORT_START)/sizeof(mmSCLV_VIEWPORT_START[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_SECONDARY", REG_MMIO, 0x4687, &mmSCLV_VIEWPORT_START_SECONDARY[0], sizeof(mmSCLV_VIEWPORT_START_SECONDARY)/sizeof(mmSCLV_VIEWPORT_START_SECONDARY[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_SIZE", REG_MMIO, 0x4688, &mmSCLV_VIEWPORT_SIZE[0], sizeof(mmSCLV_VIEWPORT_SIZE)/sizeof(mmSCLV_VIEWPORT_SIZE[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_C", REG_MMIO, 0x4689, &mmSCLV_VIEWPORT_START_C[0], sizeof(mmSCLV_VIEWPORT_START_C)/sizeof(mmSCLV_VIEWPORT_START_C[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_SECONDARY_C", REG_MMIO, 0x468a, &mmSCLV_VIEWPORT_START_SECONDARY_C[0], sizeof(mmSCLV_VIEWPORT_START_SECONDARY_C)/sizeof(mmSCLV_VIEWPORT_START_SECONDARY_C[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_SIZE_C", REG_MMIO, 0x468b, &mmSCLV_VIEWPORT_SIZE_C[0], sizeof(mmSCLV_VIEWPORT_SIZE_C)/sizeof(mmSCLV_VIEWPORT_SIZE_C[0]), 0, 0 },
+	{ "mmSCLV_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x468c, &mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmSCLV_EXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 },
+	{ "mmSCLV_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x468d, &mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmSCLV_EXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET1", REG_MMIO, 0x468e, &mmSCLV_MODE_CHANGE_DET1[0], sizeof(mmSCLV_MODE_CHANGE_DET1)/sizeof(mmSCLV_MODE_CHANGE_DET1[0]), 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET2", REG_MMIO, 0x468f, &mmSCLV_MODE_CHANGE_DET2[0], sizeof(mmSCLV_MODE_CHANGE_DET2)/sizeof(mmSCLV_MODE_CHANGE_DET2[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_NACK_STATUS", REG_MMIO, 0x469, &mmXDMA_SLV_MEM_NACK_STATUS[0], sizeof(mmXDMA_SLV_MEM_NACK_STATUS)/sizeof(mmXDMA_SLV_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET3", REG_MMIO, 0x4690, &mmSCLV_MODE_CHANGE_DET3[0], sizeof(mmSCLV_MODE_CHANGE_DET3)/sizeof(mmSCLV_MODE_CHANGE_DET3[0]), 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_MASK", REG_MMIO, 0x4691, &mmSCLV_MODE_CHANGE_MASK[0], sizeof(mmSCLV_MODE_CHANGE_MASK)/sizeof(mmSCLV_MODE_CHANGE_MASK[0]), 0, 0 },
+	{ "mmSCLV_DEBUG2", REG_MMIO, 0x4692, &mmSCLV_DEBUG2[0], sizeof(mmSCLV_DEBUG2)/sizeof(mmSCLV_DEBUG2[0]), 0, 0 },
+	{ "mmSCLV_DEBUG", REG_MMIO, 0x4693, &mmSCLV_DEBUG[0], sizeof(mmSCLV_DEBUG)/sizeof(mmSCLV_DEBUG[0]), 0, 0 },
+	{ "mmSCLV_TEST_DEBUG_INDEX", REG_MMIO, 0x4694, &mmSCLV_TEST_DEBUG_INDEX[0], sizeof(mmSCLV_TEST_DEBUG_INDEX)/sizeof(mmSCLV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmSCLV_TEST_DEBUG_DATA", REG_MMIO, 0x4695, &mmSCLV_TEST_DEBUG_DATA[0], sizeof(mmSCLV_TEST_DEBUG_DATA)/sizeof(mmSCLV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_SLV_RDRET_BUF_STATUS", REG_MMIO, 0x46a, &mmXDMA_SLV_RDRET_BUF_STATUS[0], sizeof(mmXDMA_SLV_RDRET_BUF_STATUS)/sizeof(mmXDMA_SLV_RDRET_BUF_STATUS[0]), 0, 0 },
+	{ "mmCOL_MAN_UPDATE", REG_MMIO, 0x46a4, &mmCOL_MAN_UPDATE[0], sizeof(mmCOL_MAN_UPDATE)/sizeof(mmCOL_MAN_UPDATE[0]), 0, 0 },
+	{ "mmCOL_MAN_INPUT_CSC_CONTROL", REG_MMIO, 0x46a5, &mmCOL_MAN_INPUT_CSC_CONTROL[0], sizeof(mmCOL_MAN_INPUT_CSC_CONTROL)/sizeof(mmCOL_MAN_INPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmINPUT_CSC_C11_C12_A", REG_MMIO, 0x46a6, &mmINPUT_CSC_C11_C12_A[0], sizeof(mmINPUT_CSC_C11_C12_A)/sizeof(mmINPUT_CSC_C11_C12_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C13_C14_A", REG_MMIO, 0x46a7, &mmINPUT_CSC_C13_C14_A[0], sizeof(mmINPUT_CSC_C13_C14_A)/sizeof(mmINPUT_CSC_C13_C14_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C21_C22_A", REG_MMIO, 0x46a8, &mmINPUT_CSC_C21_C22_A[0], sizeof(mmINPUT_CSC_C21_C22_A)/sizeof(mmINPUT_CSC_C21_C22_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C23_C24_A", REG_MMIO, 0x46a9, &mmINPUT_CSC_C23_C24_A[0], sizeof(mmINPUT_CSC_C23_C24_A)/sizeof(mmINPUT_CSC_C23_C24_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C31_C32_A", REG_MMIO, 0x46aa, &mmINPUT_CSC_C31_C32_A[0], sizeof(mmINPUT_CSC_C31_C32_A)/sizeof(mmINPUT_CSC_C31_C32_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C33_C34_A", REG_MMIO, 0x46ab, &mmINPUT_CSC_C33_C34_A[0], sizeof(mmINPUT_CSC_C33_C34_A)/sizeof(mmINPUT_CSC_C33_C34_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C11_C12_B", REG_MMIO, 0x46ac, &mmINPUT_CSC_C11_C12_B[0], sizeof(mmINPUT_CSC_C11_C12_B)/sizeof(mmINPUT_CSC_C11_C12_B[0]), 0, 0 },
+	{ "mmINPUT_CSC_C13_C14_B", REG_MMIO, 0x46ad, &mmINPUT_CSC_C13_C14_B[0], sizeof(mmINPUT_CSC_C13_C14_B)/sizeof(mmINPUT_CSC_C13_C14_B[0]), 0, 0 },
+	{ "mmINPUT_CSC_C21_C22_B", REG_MMIO, 0x46ae, &mmINPUT_CSC_C21_C22_B[0], sizeof(mmINPUT_CSC_C21_C22_B)/sizeof(mmINPUT_CSC_C21_C22_B[0]), 0, 0 },
+	{ "mmINPUT_CSC_C23_C24_B", REG_MMIO, 0x46af, &mmINPUT_CSC_C23_C24_B[0], sizeof(mmINPUT_CSC_C23_C24_B)/sizeof(mmINPUT_CSC_C23_C24_B[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_TIMER", REG_MMIO, 0x46b, &mmXDMA_SLV_READ_LATENCY_TIMER[0], sizeof(mmXDMA_SLV_READ_LATENCY_TIMER)/sizeof(mmXDMA_SLV_READ_LATENCY_TIMER[0]), 0, 0 },
+	{ "mmINPUT_CSC_C31_C32_B", REG_MMIO, 0x46b0, &mmINPUT_CSC_C31_C32_B[0], sizeof(mmINPUT_CSC_C31_C32_B)/sizeof(mmINPUT_CSC_C31_C32_B[0]), 0, 0 },
+	{ "mmINPUT_CSC_C33_C34_B", REG_MMIO, 0x46b1, &mmINPUT_CSC_C33_C34_B[0], sizeof(mmINPUT_CSC_C33_C34_B)/sizeof(mmINPUT_CSC_C33_C34_B[0]), 0, 0 },
+	{ "mmPRESCALE_CONTROL", REG_MMIO, 0x46b2, &mmPRESCALE_CONTROL[0], sizeof(mmPRESCALE_CONTROL)/sizeof(mmPRESCALE_CONTROL[0]), 0, 0 },
+	{ "mmPRESCALE_VALUES_R", REG_MMIO, 0x46b3, &mmPRESCALE_VALUES_R[0], sizeof(mmPRESCALE_VALUES_R)/sizeof(mmPRESCALE_VALUES_R[0]), 0, 0 },
+	{ "mmPRESCALE_VALUES_G", REG_MMIO, 0x46b4, &mmPRESCALE_VALUES_G[0], sizeof(mmPRESCALE_VALUES_G)/sizeof(mmPRESCALE_VALUES_G[0]), 0, 0 },
+	{ "mmPRESCALE_VALUES_B", REG_MMIO, 0x46b5, &mmPRESCALE_VALUES_B[0], sizeof(mmPRESCALE_VALUES_B)/sizeof(mmPRESCALE_VALUES_B[0]), 0, 0 },
+	{ "mmCOL_MAN_OUTPUT_CSC_CONTROL", REG_MMIO, 0x46b6, &mmCOL_MAN_OUTPUT_CSC_CONTROL[0], sizeof(mmCOL_MAN_OUTPUT_CSC_CONTROL)/sizeof(mmCOL_MAN_OUTPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12_A", REG_MMIO, 0x46b7, &mmOUTPUT_CSC_C11_C12_A[0], sizeof(mmOUTPUT_CSC_C11_C12_A)/sizeof(mmOUTPUT_CSC_C11_C12_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14_A", REG_MMIO, 0x46b8, &mmOUTPUT_CSC_C13_C14_A[0], sizeof(mmOUTPUT_CSC_C13_C14_A)/sizeof(mmOUTPUT_CSC_C13_C14_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22_A", REG_MMIO, 0x46b9, &mmOUTPUT_CSC_C21_C22_A[0], sizeof(mmOUTPUT_CSC_C21_C22_A)/sizeof(mmOUTPUT_CSC_C21_C22_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24_A", REG_MMIO, 0x46ba, &mmOUTPUT_CSC_C23_C24_A[0], sizeof(mmOUTPUT_CSC_C23_C24_A)/sizeof(mmOUTPUT_CSC_C23_C24_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32_A", REG_MMIO, 0x46bb, &mmOUTPUT_CSC_C31_C32_A[0], sizeof(mmOUTPUT_CSC_C31_C32_A)/sizeof(mmOUTPUT_CSC_C31_C32_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34_A", REG_MMIO, 0x46bc, &mmOUTPUT_CSC_C33_C34_A[0], sizeof(mmOUTPUT_CSC_C33_C34_A)/sizeof(mmOUTPUT_CSC_C33_C34_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12_B", REG_MMIO, 0x46bd, &mmOUTPUT_CSC_C11_C12_B[0], sizeof(mmOUTPUT_CSC_C11_C12_B)/sizeof(mmOUTPUT_CSC_C11_C12_B[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14_B", REG_MMIO, 0x46be, &mmOUTPUT_CSC_C13_C14_B[0], sizeof(mmOUTPUT_CSC_C13_C14_B)/sizeof(mmOUTPUT_CSC_C13_C14_B[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22_B", REG_MMIO, 0x46bf, &mmOUTPUT_CSC_C21_C22_B[0], sizeof(mmOUTPUT_CSC_C21_C22_B)/sizeof(mmOUTPUT_CSC_C21_C22_B[0]), 0, 0 },
+	{ "mmXDMA_SLV_FLIP_PENDING", REG_MMIO, 0x46c, &mmXDMA_SLV_FLIP_PENDING[0], sizeof(mmXDMA_SLV_FLIP_PENDING)/sizeof(mmXDMA_SLV_FLIP_PENDING[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24_B", REG_MMIO, 0x46c0, &mmOUTPUT_CSC_C23_C24_B[0], sizeof(mmOUTPUT_CSC_C23_C24_B)/sizeof(mmOUTPUT_CSC_C23_C24_B[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32_B", REG_MMIO, 0x46c1, &mmOUTPUT_CSC_C31_C32_B[0], sizeof(mmOUTPUT_CSC_C31_C32_B)/sizeof(mmOUTPUT_CSC_C31_C32_B[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34_B", REG_MMIO, 0x46c2, &mmOUTPUT_CSC_C33_C34_B[0], sizeof(mmOUTPUT_CSC_C33_C34_B)/sizeof(mmOUTPUT_CSC_C33_C34_B[0]), 0, 0 },
+	{ "mmDENORM_CLAMP_CONTROL", REG_MMIO, 0x46c3, &mmDENORM_CLAMP_CONTROL[0], sizeof(mmDENORM_CLAMP_CONTROL)/sizeof(mmDENORM_CLAMP_CONTROL[0]), 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_R_CR", REG_MMIO, 0x46c4, &mmDENORM_CLAMP_RANGE_R_CR[0], sizeof(mmDENORM_CLAMP_RANGE_R_CR)/sizeof(mmDENORM_CLAMP_RANGE_R_CR[0]), 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_G_Y", REG_MMIO, 0x46c5, &mmDENORM_CLAMP_RANGE_G_Y[0], sizeof(mmDENORM_CLAMP_RANGE_G_Y)/sizeof(mmDENORM_CLAMP_RANGE_G_Y[0]), 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_B_CB", REG_MMIO, 0x46c6, &mmDENORM_CLAMP_RANGE_B_CB[0], sizeof(mmDENORM_CLAMP_RANGE_B_CB)/sizeof(mmDENORM_CLAMP_RANGE_B_CB[0]), 0, 0 },
+	{ "mmCOL_MAN_FP_CONVERTED_FIELD", REG_MMIO, 0x46c7, &mmCOL_MAN_FP_CONVERTED_FIELD[0], sizeof(mmCOL_MAN_FP_CONVERTED_FIELD)/sizeof(mmCOL_MAN_FP_CONVERTED_FIELD[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CONTROL", REG_MMIO, 0x46c8, &mmGAMMA_CORR_CONTROL[0], sizeof(mmGAMMA_CORR_CONTROL)/sizeof(mmGAMMA_CORR_CONTROL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_LUT_INDEX", REG_MMIO, 0x46c9, &mmGAMMA_CORR_LUT_INDEX[0], sizeof(mmGAMMA_CORR_LUT_INDEX)/sizeof(mmGAMMA_CORR_LUT_INDEX[0]), 0, 0 },
+	{ "mmGAMMA_CORR_LUT_DATA", REG_MMIO, 0x46ca, &mmGAMMA_CORR_LUT_DATA[0], sizeof(mmGAMMA_CORR_LUT_DATA)/sizeof(mmGAMMA_CORR_LUT_DATA[0]), 0, 0 },
+	{ "mmGAMMA_CORR_LUT_WRITE_EN_MASK", REG_MMIO, 0x46cb, &mmGAMMA_CORR_LUT_WRITE_EN_MASK[0], sizeof(mmGAMMA_CORR_LUT_WRITE_EN_MASK)/sizeof(mmGAMMA_CORR_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_START_CNTL", REG_MMIO, 0x46cc, &mmGAMMA_CORR_CNTLA_START_CNTL[0], sizeof(mmGAMMA_CORR_CNTLA_START_CNTL)/sizeof(mmGAMMA_CORR_CNTLA_START_CNTL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_SLOPE_CNTL", REG_MMIO, 0x46cd, &mmGAMMA_CORR_CNTLA_SLOPE_CNTL[0], sizeof(mmGAMMA_CORR_CNTLA_SLOPE_CNTL)/sizeof(mmGAMMA_CORR_CNTLA_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_END_CNTL1", REG_MMIO, 0x46ce, &mmGAMMA_CORR_CNTLA_END_CNTL1[0], sizeof(mmGAMMA_CORR_CNTLA_END_CNTL1)/sizeof(mmGAMMA_CORR_CNTLA_END_CNTL1[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_END_CNTL2", REG_MMIO, 0x46cf, &mmGAMMA_CORR_CNTLA_END_CNTL2[0], sizeof(mmGAMMA_CORR_CNTLA_END_CNTL2)/sizeof(mmGAMMA_CORR_CNTLA_END_CNTL2[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_0_1", REG_MMIO, 0x46d0, &mmGAMMA_CORR_CNTLA_REGION_0_1[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_0_1)/sizeof(mmGAMMA_CORR_CNTLA_REGION_0_1[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_2_3", REG_MMIO, 0x46d1, &mmGAMMA_CORR_CNTLA_REGION_2_3[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_2_3)/sizeof(mmGAMMA_CORR_CNTLA_REGION_2_3[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_4_5", REG_MMIO, 0x46d2, &mmGAMMA_CORR_CNTLA_REGION_4_5[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_4_5)/sizeof(mmGAMMA_CORR_CNTLA_REGION_4_5[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_6_7", REG_MMIO, 0x46d3, &mmGAMMA_CORR_CNTLA_REGION_6_7[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_6_7)/sizeof(mmGAMMA_CORR_CNTLA_REGION_6_7[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_8_9", REG_MMIO, 0x46d4, &mmGAMMA_CORR_CNTLA_REGION_8_9[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_8_9)/sizeof(mmGAMMA_CORR_CNTLA_REGION_8_9[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_10_11", REG_MMIO, 0x46d5, &mmGAMMA_CORR_CNTLA_REGION_10_11[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_10_11)/sizeof(mmGAMMA_CORR_CNTLA_REGION_10_11[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_12_13", REG_MMIO, 0x46d6, &mmGAMMA_CORR_CNTLA_REGION_12_13[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_12_13)/sizeof(mmGAMMA_CORR_CNTLA_REGION_12_13[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_14_15", REG_MMIO, 0x46d7, &mmGAMMA_CORR_CNTLA_REGION_14_15[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_14_15)/sizeof(mmGAMMA_CORR_CNTLA_REGION_14_15[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_START_CNTL", REG_MMIO, 0x46d8, &mmGAMMA_CORR_CNTLB_START_CNTL[0], sizeof(mmGAMMA_CORR_CNTLB_START_CNTL)/sizeof(mmGAMMA_CORR_CNTLB_START_CNTL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_SLOPE_CNTL", REG_MMIO, 0x46d9, &mmGAMMA_CORR_CNTLB_SLOPE_CNTL[0], sizeof(mmGAMMA_CORR_CNTLB_SLOPE_CNTL)/sizeof(mmGAMMA_CORR_CNTLB_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_END_CNTL1", REG_MMIO, 0x46da, &mmGAMMA_CORR_CNTLB_END_CNTL1[0], sizeof(mmGAMMA_CORR_CNTLB_END_CNTL1)/sizeof(mmGAMMA_CORR_CNTLB_END_CNTL1[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_END_CNTL2", REG_MMIO, 0x46db, &mmGAMMA_CORR_CNTLB_END_CNTL2[0], sizeof(mmGAMMA_CORR_CNTLB_END_CNTL2)/sizeof(mmGAMMA_CORR_CNTLB_END_CNTL2[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_0_1", REG_MMIO, 0x46dc, &mmGAMMA_CORR_CNTLB_REGION_0_1[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_0_1)/sizeof(mmGAMMA_CORR_CNTLB_REGION_0_1[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_2_3", REG_MMIO, 0x46dd, &mmGAMMA_CORR_CNTLB_REGION_2_3[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_2_3)/sizeof(mmGAMMA_CORR_CNTLB_REGION_2_3[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_4_5", REG_MMIO, 0x46de, &mmGAMMA_CORR_CNTLB_REGION_4_5[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_4_5)/sizeof(mmGAMMA_CORR_CNTLB_REGION_4_5[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_6_7", REG_MMIO, 0x46df, &mmGAMMA_CORR_CNTLB_REGION_6_7[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_6_7)/sizeof(mmGAMMA_CORR_CNTLB_REGION_6_7[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_8_9", REG_MMIO, 0x46e0, &mmGAMMA_CORR_CNTLB_REGION_8_9[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_8_9)/sizeof(mmGAMMA_CORR_CNTLB_REGION_8_9[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_10_11", REG_MMIO, 0x46e1, &mmGAMMA_CORR_CNTLB_REGION_10_11[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_10_11)/sizeof(mmGAMMA_CORR_CNTLB_REGION_10_11[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_12_13", REG_MMIO, 0x46e2, &mmGAMMA_CORR_CNTLB_REGION_12_13[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_12_13)/sizeof(mmGAMMA_CORR_CNTLB_REGION_12_13[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_14_15", REG_MMIO, 0x46e3, &mmGAMMA_CORR_CNTLB_REGION_14_15[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_14_15)/sizeof(mmGAMMA_CORR_CNTLB_REGION_14_15[0]), 0, 0 },
+	{ "mmCOL_MAN_TEST_DEBUG_INDEX", REG_MMIO, 0x46e4, &mmCOL_MAN_TEST_DEBUG_INDEX[0], sizeof(mmCOL_MAN_TEST_DEBUG_INDEX)/sizeof(mmCOL_MAN_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCOL_MAN_TEST_DEBUG_DATA", REG_MMIO, 0x46e5, &mmCOL_MAN_TEST_DEBUG_DATA[0], sizeof(mmCOL_MAN_TEST_DEBUG_DATA)/sizeof(mmCOL_MAN_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmCOL_MAN_DEBUG_CONTROL", REG_MMIO, 0x46e6, &mmCOL_MAN_DEBUG_CONTROL[0], sizeof(mmCOL_MAN_DEBUG_CONTROL)/sizeof(mmCOL_MAN_DEBUG_CONTROL[0]), 0, 0 },
+	{ "mmDCFEV_CLOCK_CONTROL", REG_MMIO, 0x46f4, &mmDCFEV_CLOCK_CONTROL[0], sizeof(mmDCFEV_CLOCK_CONTROL)/sizeof(mmDCFEV_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFEV_SOFT_RESET", REG_MMIO, 0x46f5, &mmDCFEV_SOFT_RESET[0], sizeof(mmDCFEV_SOFT_RESET)/sizeof(mmDCFEV_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFEV_DMIFV_CLOCK_CONTROL", REG_MMIO, 0x46f6, &mmDCFEV_DMIFV_CLOCK_CONTROL[0], sizeof(mmDCFEV_DMIFV_CLOCK_CONTROL)/sizeof(mmDCFEV_DMIFV_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFEV_DBG_CONFIG", REG_MMIO, 0x46f7, &mmDCFEV_DBG_CONFIG[0], sizeof(mmDCFEV_DBG_CONFIG)/sizeof(mmDCFEV_DBG_CONFIG[0]), 0, 0 },
+	{ "mmDCFEV_DMIFV_MEM_PWR_CTRL", REG_MMIO, 0x46f8, &mmDCFEV_DMIFV_MEM_PWR_CTRL[0], sizeof(mmDCFEV_DMIFV_MEM_PWR_CTRL)/sizeof(mmDCFEV_DMIFV_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCFEV_DMIFV_MEM_PWR_STATUS", REG_MMIO, 0x46f9, &mmDCFEV_DMIFV_MEM_PWR_STATUS[0], sizeof(mmDCFEV_DMIFV_MEM_PWR_STATUS)/sizeof(mmDCFEV_DMIFV_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, &mmXDMA_SLV_CHANNEL_CNTL[0], sizeof(mmXDMA_SLV_CHANNEL_CNTL)/sizeof(mmXDMA_SLV_CHANNEL_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, &mmXDMA_SLV_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, &mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDC_PERFMON9_PERFCOUNTER_CNTL", REG_MMIO, 0x4724, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFCOUNTER_STATE", REG_MMIO, 0x4725, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4726, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CNTL", REG_MMIO, 0x4727, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CVALUE_LOW", REG_MMIO, 0x4728, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_HI", REG_MMIO, 0x4729, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_LOW", REG_MMIO, 0x472a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x472b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x472c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CNTL2", REG_MMIO, 0x472e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4730, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4731, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4732, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4733, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4734, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4735, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4736, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4737, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4738, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4739, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_REPEATER_PROGRAM", REG_MMIO, 0x473a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_HW_DEBUG_A", REG_MMIO, 0x473b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_HW_DEBUG_B", REG_MMIO, 0x473c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG6_DPG_HW_DEBUG_11", REG_MMIO, 0x473d, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_CONTROL", REG_MMIO, 0x476d, NULL, 0, 0, 0 },
+	{ "mmBLND6_SM_CONTROL2", REG_MMIO, 0x476e, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_CONTROL2", REG_MMIO, 0x476f, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_UPDATE", REG_MMIO, 0x4770, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4771, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4773, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_DEBUG", REG_MMIO, 0x4774, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4775, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4776, NULL, 0, 0, 0 },
+	{ "mmBLND6_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4777, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4778, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4779, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_GSL_WINDOW", REG_MMIO, 0x477a, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_GSL_CONTROL", REG_MMIO, 0x477b, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x477c, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x477d, NULL, 0, 0, 0 },
+	{ "mmCRTC6_DCFE_DBG_SEL", REG_MMIO, 0x477e, NULL, 0, 0, 0 },
+	{ "mmCRTC6_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x477f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x478, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_H_TOTAL", REG_MMIO, 0x4780, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_H_BLANK_START_END", REG_MMIO, 0x4781, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_H_SYNC_A", REG_MMIO, 0x4782, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4783, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_H_SYNC_B", REG_MMIO, 0x4784, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4785, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VBI_END", REG_MMIO, 0x4786, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_TOTAL", REG_MMIO, 0x4787, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4788, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4789, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x478a, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x478b, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x478c, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_BLANK_START_END", REG_MMIO, 0x478d, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_SYNC_A", REG_MMIO, 0x478e, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x478f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x479, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_SYNC_B", REG_MMIO, 0x4790, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4791, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4792, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4793, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TRIGA_CNTL", REG_MMIO, 0x4794, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4795, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TRIGB_CNTL", REG_MMIO, 0x4796, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4797, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4798, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_FLOW_CONTROL", REG_MMIO, 0x4799, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x479a, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x479b, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CONTROL", REG_MMIO, 0x479c, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_BLANK_CONTROL", REG_MMIO, 0x479d, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x479e, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_INTERLACE_STATUS", REG_MMIO, 0x479f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x47a, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x47a0, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x47a1, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x47a2, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STATUS", REG_MMIO, 0x47a3, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STATUS_POSITION", REG_MMIO, 0x47a4, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x47a5, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x47a6, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x47a7, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x47a8, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_COUNT_CONTROL", REG_MMIO, 0x47a9, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_COUNT_RESET", REG_MMIO, 0x47aa, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x47ab, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x47ac, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STEREO_STATUS", REG_MMIO, 0x47ad, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STEREO_CONTROL", REG_MMIO, 0x47ae, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x47af, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x47b0, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x47b1, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x47b2, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_START_LINE_CONTROL", REG_MMIO, 0x47b3, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x47b4, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_UPDATE_LOCK", REG_MMIO, 0x47b5, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x47b6, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x47b7, NULL, 0, 0, 0 },
+	{ "mmCRTC6_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x47b8, NULL, 0, 0, 0 },
+	{ "mmCRTC6_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x47b9, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x47ba, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x47bb, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x47bc, NULL, 0, 0, 0 },
+	{ "mmCRTC6_MASTER_UPDATE_LOCK", REG_MMIO, 0x47bd, NULL, 0, 0, 0 },
+	{ "mmCRTC6_MASTER_UPDATE_MODE", REG_MMIO, 0x47be, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x47bf, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x47c0, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_MVP_STATUS", REG_MMIO, 0x47c1, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_MASTER_EN", REG_MMIO, 0x47c2, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x47c3, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x47c4, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x47c6, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x47c7, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x47c8, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x47c9, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x47ca, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x47cb, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_BLACK_COLOR", REG_MMIO, 0x47cc, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x47cd, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x47ce, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x47cf, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x47d0, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x47d1, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x47d2, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x47d3, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC_CNTL", REG_MMIO, 0x47d4, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x47d5, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x47d6, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x47d7, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x47d8, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC0_DATA_RG", REG_MMIO, 0x47d9, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC0_DATA_B", REG_MMIO, 0x47da, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x47db, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x47dc, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x47dd, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x47de, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC1_DATA_RG", REG_MMIO, 0x47df, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_CRC1_DATA_B", REG_MMIO, 0x47e0, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x47e1, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x47e2, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x47e3, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x47e4, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x47e5, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x47e6, NULL, 0, 0, 0 },
+	{ "mmCRTC6_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x47e7, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x480, NULL, 0, 0, 0 },
+	{ "mmDC_GENERICA", REG_MMIO, 0x4800, &mmDC_GENERICA[0], sizeof(mmDC_GENERICA)/sizeof(mmDC_GENERICA[0]), 0, 0 },
+	{ "mmDC_GENERICB", REG_MMIO, 0x4801, &mmDC_GENERICB[0], sizeof(mmDC_GENERICB)/sizeof(mmDC_GENERICB[0]), 0, 0 },
+	{ "mmDC_PAD_EXTERN_SIG", REG_MMIO, 0x4802, &mmDC_PAD_EXTERN_SIG[0], sizeof(mmDC_PAD_EXTERN_SIG)/sizeof(mmDC_PAD_EXTERN_SIG[0]), 0, 0 },
+	{ "mmDC_REF_CLK_CNTL", REG_MMIO, 0x4803, &mmDC_REF_CLK_CNTL[0], sizeof(mmDC_REF_CLK_CNTL)/sizeof(mmDC_REF_CLK_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_DEBUG", REG_MMIO, 0x4804, &mmDC_GPIO_DEBUG[0], sizeof(mmDC_GPIO_DEBUG)/sizeof(mmDC_GPIO_DEBUG[0]), 0, 0 },
+	{ "mmUNIPHYA_LINK_CNTL", REG_MMIO, 0x4805, &mmUNIPHYA_LINK_CNTL[0], sizeof(mmUNIPHYA_LINK_CNTL)/sizeof(mmUNIPHYA_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYA_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4806, &mmUNIPHYA_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYA_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYA_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYB_LINK_CNTL", REG_MMIO, 0x4807, &mmUNIPHYB_LINK_CNTL[0], sizeof(mmUNIPHYB_LINK_CNTL)/sizeof(mmUNIPHYB_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYB_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4808, &mmUNIPHYB_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYB_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYB_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYC_LINK_CNTL", REG_MMIO, 0x4809, &mmUNIPHYC_LINK_CNTL[0], sizeof(mmUNIPHYC_LINK_CNTL)/sizeof(mmUNIPHYC_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYC_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480a, &mmUNIPHYC_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYC_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYC_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYD_LINK_CNTL", REG_MMIO, 0x480b, &mmUNIPHYD_LINK_CNTL[0], sizeof(mmUNIPHYD_LINK_CNTL)/sizeof(mmUNIPHYD_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYD_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480c, &mmUNIPHYD_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYD_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYD_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYE_LINK_CNTL", REG_MMIO, 0x480d, &mmUNIPHYE_LINK_CNTL[0], sizeof(mmUNIPHYE_LINK_CNTL)/sizeof(mmUNIPHYE_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYE_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480e, &mmUNIPHYE_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYE_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYE_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYF_LINK_CNTL", REG_MMIO, 0x480f, &mmUNIPHYF_LINK_CNTL[0], sizeof(mmUNIPHYF_LINK_CNTL)/sizeof(mmUNIPHYF_LINK_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x481, NULL, 0, 0, 0 },
+	{ "mmUNIPHYF_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4810, &mmUNIPHYF_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYF_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYF_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYG_LINK_CNTL", REG_MMIO, 0x4811, &mmUNIPHYG_LINK_CNTL[0], sizeof(mmUNIPHYG_LINK_CNTL)/sizeof(mmUNIPHYG_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYG_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4812, &mmUNIPHYG_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmDCIO_WRCMD_DELAY", REG_MMIO, 0x4816, &mmDCIO_WRCMD_DELAY[0], sizeof(mmDCIO_WRCMD_DELAY)/sizeof(mmDCIO_WRCMD_DELAY[0]), 0, 0 },
+	{ "mmDC_PINSTRAPS", REG_MMIO, 0x4818, &mmDC_PINSTRAPS[0], sizeof(mmDC_PINSTRAPS)/sizeof(mmDC_PINSTRAPS[0]), 0, 0 },
+	{ "mmDC_DVODATA_CONFIG", REG_MMIO, 0x481a, &mmDC_DVODATA_CONFIG[0], sizeof(mmDC_DVODATA_CONFIG)/sizeof(mmDC_DVODATA_CONFIG[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_CNTL", REG_MMIO, 0x481b, &mmLVTMA_PWRSEQ_CNTL[0], sizeof(mmLVTMA_PWRSEQ_CNTL)/sizeof(mmLVTMA_PWRSEQ_CNTL[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_STATE", REG_MMIO, 0x481c, &mmLVTMA_PWRSEQ_STATE[0], sizeof(mmLVTMA_PWRSEQ_STATE)/sizeof(mmLVTMA_PWRSEQ_STATE[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_REF_DIV", REG_MMIO, 0x481d, &mmLVTMA_PWRSEQ_REF_DIV[0], sizeof(mmLVTMA_PWRSEQ_REF_DIV)/sizeof(mmLVTMA_PWRSEQ_REF_DIV[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY1", REG_MMIO, 0x481e, &mmLVTMA_PWRSEQ_DELAY1[0], sizeof(mmLVTMA_PWRSEQ_DELAY1)/sizeof(mmLVTMA_PWRSEQ_DELAY1[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY2", REG_MMIO, 0x481f, &mmLVTMA_PWRSEQ_DELAY2[0], sizeof(mmLVTMA_PWRSEQ_DELAY2)/sizeof(mmLVTMA_PWRSEQ_DELAY2[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x482, NULL, 0, 0, 0 },
+	{ "mmBL_PWM_CNTL", REG_MMIO, 0x4820, &mmBL_PWM_CNTL[0], sizeof(mmBL_PWM_CNTL)/sizeof(mmBL_PWM_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_CNTL2", REG_MMIO, 0x4821, &mmBL_PWM_CNTL2[0], sizeof(mmBL_PWM_CNTL2)/sizeof(mmBL_PWM_CNTL2[0]), 0, 0 },
+	{ "mmBL_PWM_PERIOD_CNTL", REG_MMIO, 0x4822, &mmBL_PWM_PERIOD_CNTL[0], sizeof(mmBL_PWM_PERIOD_CNTL)/sizeof(mmBL_PWM_PERIOD_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_GRP1_REG_LOCK", REG_MMIO, 0x4823, &mmBL_PWM_GRP1_REG_LOCK[0], sizeof(mmBL_PWM_GRP1_REG_LOCK)/sizeof(mmBL_PWM_GRP1_REG_LOCK[0]), 0, 0 },
+	{ "mmDCIO_GSL_GENLK_PAD_CNTL", REG_MMIO, 0x4824, &mmDCIO_GSL_GENLK_PAD_CNTL[0], sizeof(mmDCIO_GSL_GENLK_PAD_CNTL)/sizeof(mmDCIO_GSL_GENLK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL_SWAPLOCK_PAD_CNTL", REG_MMIO, 0x4825, &mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0], sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL)/sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL0_CNTL", REG_MMIO, 0x4826, &mmDCIO_GSL0_CNTL[0], sizeof(mmDCIO_GSL0_CNTL)/sizeof(mmDCIO_GSL0_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL1_CNTL", REG_MMIO, 0x4827, &mmDCIO_GSL1_CNTL[0], sizeof(mmDCIO_GSL1_CNTL)/sizeof(mmDCIO_GSL1_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL2_CNTL", REG_MMIO, 0x4828, &mmDCIO_GSL2_CNTL[0], sizeof(mmDCIO_GSL2_CNTL)/sizeof(mmDCIO_GSL2_CNTL[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_V_UPDATE", REG_MMIO, 0x4829, &mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0], sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE)/sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_P_FLIP", REG_MMIO, 0x482a, &mmDC_GPU_TIMER_START_POSITION_P_FLIP[0], sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP)/sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ", REG_MMIO, 0x482b, &mmDC_GPU_TIMER_READ[0], sizeof(mmDC_GPU_TIMER_READ)/sizeof(mmDC_GPU_TIMER_READ[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ_CNTL", REG_MMIO, 0x482c, &mmDC_GPU_TIMER_READ_CNTL[0], sizeof(mmDC_GPU_TIMER_READ_CNTL)/sizeof(mmDC_GPU_TIMER_READ_CNTL[0]), 0, 0 },
+	{ "mmDCIO_CLOCK_CNTL", REG_MMIO, 0x482d, &mmDCIO_CLOCK_CNTL[0], sizeof(mmDCIO_CLOCK_CNTL)/sizeof(mmDCIO_CLOCK_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DEBUG", REG_MMIO, 0x482f, &mmDCIO_DEBUG[0], sizeof(mmDCIO_DEBUG)/sizeof(mmDCIO_DEBUG[0]), 0, 0 },
+	{ "mmDCO_DCFE_EXT_VSYNC_CNTL", REG_MMIO, 0x4830, &mmDCO_DCFE_EXT_VSYNC_CNTL[0], sizeof(mmDCO_DCFE_EXT_VSYNC_CNTL)/sizeof(mmDCO_DCFE_EXT_VSYNC_CNTL[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_INDEX", REG_MMIO, 0x4831, &mmDCIO_TEST_DEBUG_INDEX[0], sizeof(mmDCIO_TEST_DEBUG_INDEX)/sizeof(mmDCIO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_DATA", REG_MMIO, 0x4832, &mmDCIO_TEST_DEBUG_DATA[0], sizeof(mmDCIO_TEST_DEBUG_DATA)/sizeof(mmDCIO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDBG_OUT_CNTL", REG_MMIO, 0x4834, &mmDBG_OUT_CNTL[0], sizeof(mmDBG_OUT_CNTL)/sizeof(mmDBG_OUT_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DEBUG_CONFIG", REG_MMIO, 0x4835, &mmDCIO_DEBUG_CONFIG[0], sizeof(mmDCIO_DEBUG_CONFIG)/sizeof(mmDCIO_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmDCIO_SOFT_RESET", REG_MMIO, 0x4836, &mmDCIO_SOFT_RESET[0], sizeof(mmDCIO_SOFT_RESET)/sizeof(mmDCIO_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCIO_DPHY_SEL", REG_MMIO, 0x4837, &mmDCIO_DPHY_SEL[0], sizeof(mmDCIO_DPHY_SEL)/sizeof(mmDCIO_DPHY_SEL[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKA", REG_MMIO, 0x4838, &mmUNIPHY_IMPCAL_LINKA[0], sizeof(mmUNIPHY_IMPCAL_LINKA)/sizeof(mmUNIPHY_IMPCAL_LINKA[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKB", REG_MMIO, 0x4839, &mmUNIPHY_IMPCAL_LINKB[0], sizeof(mmUNIPHY_IMPCAL_LINKB)/sizeof(mmUNIPHY_IMPCAL_LINKB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PERIOD", REG_MMIO, 0x483a, &mmUNIPHY_IMPCAL_PERIOD[0], sizeof(mmUNIPHY_IMPCAL_PERIOD)/sizeof(mmUNIPHY_IMPCAL_PERIOD[0]), 0, 0 },
+	{ "mmAUXP_IMPCAL", REG_MMIO, 0x483b, &mmAUXP_IMPCAL[0], sizeof(mmAUXP_IMPCAL)/sizeof(mmAUXP_IMPCAL[0]), 0, 0 },
+	{ "mmAUXN_IMPCAL", REG_MMIO, 0x483c, &mmAUXN_IMPCAL[0], sizeof(mmAUXN_IMPCAL)/sizeof(mmAUXN_IMPCAL[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL", REG_MMIO, 0x483d, &mmDCIO_IMPCAL_CNTL[0], sizeof(mmDCIO_IMPCAL_CNTL)/sizeof(mmDCIO_IMPCAL_CNTL[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_AB", REG_MMIO, 0x483e, &mmUNIPHY_IMPCAL_PSW_AB[0], sizeof(mmUNIPHY_IMPCAL_PSW_AB)/sizeof(mmUNIPHY_IMPCAL_PSW_AB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKC", REG_MMIO, 0x483f, &mmUNIPHY_IMPCAL_LINKC[0], sizeof(mmUNIPHY_IMPCAL_LINKC)/sizeof(mmUNIPHY_IMPCAL_LINKC[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKD", REG_MMIO, 0x4840, &mmUNIPHY_IMPCAL_LINKD[0], sizeof(mmUNIPHY_IMPCAL_LINKD)/sizeof(mmUNIPHY_IMPCAL_LINKD[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_CD", REG_MMIO, 0x4841, &mmDCIO_IMPCAL_CNTL_CD[0], sizeof(mmDCIO_IMPCAL_CNTL_CD)/sizeof(mmDCIO_IMPCAL_CNTL_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_CD", REG_MMIO, 0x4842, &mmUNIPHY_IMPCAL_PSW_CD[0], sizeof(mmUNIPHY_IMPCAL_PSW_CD)/sizeof(mmUNIPHY_IMPCAL_PSW_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKE", REG_MMIO, 0x4843, &mmUNIPHY_IMPCAL_LINKE[0], sizeof(mmUNIPHY_IMPCAL_LINKE)/sizeof(mmUNIPHY_IMPCAL_LINKE[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKF", REG_MMIO, 0x4844, &mmUNIPHY_IMPCAL_LINKF[0], sizeof(mmUNIPHY_IMPCAL_LINKF)/sizeof(mmUNIPHY_IMPCAL_LINKF[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_EF", REG_MMIO, 0x4845, &mmDCIO_IMPCAL_CNTL_EF[0], sizeof(mmDCIO_IMPCAL_CNTL_EF)/sizeof(mmDCIO_IMPCAL_CNTL_EF[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_EF", REG_MMIO, 0x4846, &mmUNIPHY_IMPCAL_PSW_EF[0], sizeof(mmUNIPHY_IMPCAL_PSW_EF)/sizeof(mmUNIPHY_IMPCAL_PSW_EF[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_MASK", REG_MMIO, 0x4860, &mmDC_GPIO_GENERIC_MASK[0], sizeof(mmDC_GPIO_GENERIC_MASK)/sizeof(mmDC_GPIO_GENERIC_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_A", REG_MMIO, 0x4861, &mmDC_GPIO_GENERIC_A[0], sizeof(mmDC_GPIO_GENERIC_A)/sizeof(mmDC_GPIO_GENERIC_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_EN", REG_MMIO, 0x4862, &mmDC_GPIO_GENERIC_EN[0], sizeof(mmDC_GPIO_GENERIC_EN)/sizeof(mmDC_GPIO_GENERIC_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_Y", REG_MMIO, 0x4863, &mmDC_GPIO_GENERIC_Y[0], sizeof(mmDC_GPIO_GENERIC_Y)/sizeof(mmDC_GPIO_GENERIC_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_MASK", REG_MMIO, 0x4864, &mmDC_GPIO_DVODATA_MASK[0], sizeof(mmDC_GPIO_DVODATA_MASK)/sizeof(mmDC_GPIO_DVODATA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_A", REG_MMIO, 0x4865, &mmDC_GPIO_DVODATA_A[0], sizeof(mmDC_GPIO_DVODATA_A)/sizeof(mmDC_GPIO_DVODATA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_EN", REG_MMIO, 0x4866, &mmDC_GPIO_DVODATA_EN[0], sizeof(mmDC_GPIO_DVODATA_EN)/sizeof(mmDC_GPIO_DVODATA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_Y", REG_MMIO, 0x4867, &mmDC_GPIO_DVODATA_Y[0], sizeof(mmDC_GPIO_DVODATA_Y)/sizeof(mmDC_GPIO_DVODATA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_MASK", REG_MMIO, 0x4868, &mmDC_GPIO_DDC1_MASK[0], sizeof(mmDC_GPIO_DDC1_MASK)/sizeof(mmDC_GPIO_DDC1_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_A", REG_MMIO, 0x4869, &mmDC_GPIO_DDC1_A[0], sizeof(mmDC_GPIO_DDC1_A)/sizeof(mmDC_GPIO_DDC1_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_EN", REG_MMIO, 0x486a, &mmDC_GPIO_DDC1_EN[0], sizeof(mmDC_GPIO_DDC1_EN)/sizeof(mmDC_GPIO_DDC1_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_Y", REG_MMIO, 0x486b, &mmDC_GPIO_DDC1_Y[0], sizeof(mmDC_GPIO_DDC1_Y)/sizeof(mmDC_GPIO_DDC1_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_MASK", REG_MMIO, 0x486c, &mmDC_GPIO_DDC2_MASK[0], sizeof(mmDC_GPIO_DDC2_MASK)/sizeof(mmDC_GPIO_DDC2_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_A", REG_MMIO, 0x486d, &mmDC_GPIO_DDC2_A[0], sizeof(mmDC_GPIO_DDC2_A)/sizeof(mmDC_GPIO_DDC2_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_EN", REG_MMIO, 0x486e, &mmDC_GPIO_DDC2_EN[0], sizeof(mmDC_GPIO_DDC2_EN)/sizeof(mmDC_GPIO_DDC2_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_Y", REG_MMIO, 0x486f, &mmDC_GPIO_DDC2_Y[0], sizeof(mmDC_GPIO_DDC2_Y)/sizeof(mmDC_GPIO_DDC2_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_MASK", REG_MMIO, 0x4870, &mmDC_GPIO_DDC3_MASK[0], sizeof(mmDC_GPIO_DDC3_MASK)/sizeof(mmDC_GPIO_DDC3_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_A", REG_MMIO, 0x4871, &mmDC_GPIO_DDC3_A[0], sizeof(mmDC_GPIO_DDC3_A)/sizeof(mmDC_GPIO_DDC3_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_EN", REG_MMIO, 0x4872, &mmDC_GPIO_DDC3_EN[0], sizeof(mmDC_GPIO_DDC3_EN)/sizeof(mmDC_GPIO_DDC3_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_Y", REG_MMIO, 0x4873, &mmDC_GPIO_DDC3_Y[0], sizeof(mmDC_GPIO_DDC3_Y)/sizeof(mmDC_GPIO_DDC3_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_MASK", REG_MMIO, 0x4874, &mmDC_GPIO_DDC4_MASK[0], sizeof(mmDC_GPIO_DDC4_MASK)/sizeof(mmDC_GPIO_DDC4_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_A", REG_MMIO, 0x4875, &mmDC_GPIO_DDC4_A[0], sizeof(mmDC_GPIO_DDC4_A)/sizeof(mmDC_GPIO_DDC4_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_EN", REG_MMIO, 0x4876, &mmDC_GPIO_DDC4_EN[0], sizeof(mmDC_GPIO_DDC4_EN)/sizeof(mmDC_GPIO_DDC4_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_Y", REG_MMIO, 0x4877, &mmDC_GPIO_DDC4_Y[0], sizeof(mmDC_GPIO_DDC4_Y)/sizeof(mmDC_GPIO_DDC4_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_MASK", REG_MMIO, 0x4878, &mmDC_GPIO_DDC5_MASK[0], sizeof(mmDC_GPIO_DDC5_MASK)/sizeof(mmDC_GPIO_DDC5_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_A", REG_MMIO, 0x4879, &mmDC_GPIO_DDC5_A[0], sizeof(mmDC_GPIO_DDC5_A)/sizeof(mmDC_GPIO_DDC5_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_EN", REG_MMIO, 0x487a, &mmDC_GPIO_DDC5_EN[0], sizeof(mmDC_GPIO_DDC5_EN)/sizeof(mmDC_GPIO_DDC5_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_Y", REG_MMIO, 0x487b, &mmDC_GPIO_DDC5_Y[0], sizeof(mmDC_GPIO_DDC5_Y)/sizeof(mmDC_GPIO_DDC5_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_MASK", REG_MMIO, 0x487c, &mmDC_GPIO_DDC6_MASK[0], sizeof(mmDC_GPIO_DDC6_MASK)/sizeof(mmDC_GPIO_DDC6_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_A", REG_MMIO, 0x487d, &mmDC_GPIO_DDC6_A[0], sizeof(mmDC_GPIO_DDC6_A)/sizeof(mmDC_GPIO_DDC6_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_EN", REG_MMIO, 0x487e, &mmDC_GPIO_DDC6_EN[0], sizeof(mmDC_GPIO_DDC6_EN)/sizeof(mmDC_GPIO_DDC6_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_Y", REG_MMIO, 0x487f, &mmDC_GPIO_DDC6_Y[0], sizeof(mmDC_GPIO_DDC6_Y)/sizeof(mmDC_GPIO_DDC6_Y[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x488, NULL, 0, 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_MASK", REG_MMIO, 0x4880, &mmDC_GPIO_DDCVGA_MASK[0], sizeof(mmDC_GPIO_DDCVGA_MASK)/sizeof(mmDC_GPIO_DDCVGA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_A", REG_MMIO, 0x4881, &mmDC_GPIO_DDCVGA_A[0], sizeof(mmDC_GPIO_DDCVGA_A)/sizeof(mmDC_GPIO_DDCVGA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_EN", REG_MMIO, 0x4882, &mmDC_GPIO_DDCVGA_EN[0], sizeof(mmDC_GPIO_DDCVGA_EN)/sizeof(mmDC_GPIO_DDCVGA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_Y", REG_MMIO, 0x4883, &mmDC_GPIO_DDCVGA_Y[0], sizeof(mmDC_GPIO_DDCVGA_Y)/sizeof(mmDC_GPIO_DDCVGA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_MASK", REG_MMIO, 0x4884, &mmDC_GPIO_SYNCA_MASK[0], sizeof(mmDC_GPIO_SYNCA_MASK)/sizeof(mmDC_GPIO_SYNCA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_A", REG_MMIO, 0x4885, &mmDC_GPIO_SYNCA_A[0], sizeof(mmDC_GPIO_SYNCA_A)/sizeof(mmDC_GPIO_SYNCA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_EN", REG_MMIO, 0x4886, &mmDC_GPIO_SYNCA_EN[0], sizeof(mmDC_GPIO_SYNCA_EN)/sizeof(mmDC_GPIO_SYNCA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_Y", REG_MMIO, 0x4887, &mmDC_GPIO_SYNCA_Y[0], sizeof(mmDC_GPIO_SYNCA_Y)/sizeof(mmDC_GPIO_SYNCA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_MASK", REG_MMIO, 0x4888, &mmDC_GPIO_GENLK_MASK[0], sizeof(mmDC_GPIO_GENLK_MASK)/sizeof(mmDC_GPIO_GENLK_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_A", REG_MMIO, 0x4889, &mmDC_GPIO_GENLK_A[0], sizeof(mmDC_GPIO_GENLK_A)/sizeof(mmDC_GPIO_GENLK_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_EN", REG_MMIO, 0x488a, &mmDC_GPIO_GENLK_EN[0], sizeof(mmDC_GPIO_GENLK_EN)/sizeof(mmDC_GPIO_GENLK_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_Y", REG_MMIO, 0x488b, &mmDC_GPIO_GENLK_Y[0], sizeof(mmDC_GPIO_GENLK_Y)/sizeof(mmDC_GPIO_GENLK_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_MASK", REG_MMIO, 0x488c, &mmDC_GPIO_HPD_MASK[0], sizeof(mmDC_GPIO_HPD_MASK)/sizeof(mmDC_GPIO_HPD_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_A", REG_MMIO, 0x488d, &mmDC_GPIO_HPD_A[0], sizeof(mmDC_GPIO_HPD_A)/sizeof(mmDC_GPIO_HPD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_EN", REG_MMIO, 0x488e, &mmDC_GPIO_HPD_EN[0], sizeof(mmDC_GPIO_HPD_EN)/sizeof(mmDC_GPIO_HPD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_Y", REG_MMIO, 0x488f, &mmDC_GPIO_HPD_Y[0], sizeof(mmDC_GPIO_HPD_Y)/sizeof(mmDC_GPIO_HPD_Y[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x489, NULL, 0, 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_MASK", REG_MMIO, 0x4890, &mmDC_GPIO_PWRSEQ_MASK[0], sizeof(mmDC_GPIO_PWRSEQ_MASK)/sizeof(mmDC_GPIO_PWRSEQ_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_A", REG_MMIO, 0x4891, &mmDC_GPIO_PWRSEQ_A[0], sizeof(mmDC_GPIO_PWRSEQ_A)/sizeof(mmDC_GPIO_PWRSEQ_A[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_EN", REG_MMIO, 0x4892, &mmDC_GPIO_PWRSEQ_EN[0], sizeof(mmDC_GPIO_PWRSEQ_EN)/sizeof(mmDC_GPIO_PWRSEQ_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_Y", REG_MMIO, 0x4893, &mmDC_GPIO_PWRSEQ_Y[0], sizeof(mmDC_GPIO_PWRSEQ_Y)/sizeof(mmDC_GPIO_PWRSEQ_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_1", REG_MMIO, 0x4894, &mmDC_GPIO_PAD_STRENGTH_1[0], sizeof(mmDC_GPIO_PAD_STRENGTH_1)/sizeof(mmDC_GPIO_PAD_STRENGTH_1[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_2", REG_MMIO, 0x4895, &mmDC_GPIO_PAD_STRENGTH_2[0], sizeof(mmDC_GPIO_PAD_STRENGTH_2)/sizeof(mmDC_GPIO_PAD_STRENGTH_2[0]), 0, 0 },
+	{ "mmPHY_AUX_CNTL", REG_MMIO, 0x4897, &mmPHY_AUX_CNTL[0], sizeof(mmPHY_AUX_CNTL)/sizeof(mmPHY_AUX_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_A", REG_MMIO, 0x4899, &mmDC_GPIO_I2CPAD_A[0], sizeof(mmDC_GPIO_I2CPAD_A)/sizeof(mmDC_GPIO_I2CPAD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_EN", REG_MMIO, 0x489a, &mmDC_GPIO_I2CPAD_EN[0], sizeof(mmDC_GPIO_I2CPAD_EN)/sizeof(mmDC_GPIO_I2CPAD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_Y", REG_MMIO, 0x489b, &mmDC_GPIO_I2CPAD_Y[0], sizeof(mmDC_GPIO_I2CPAD_Y)/sizeof(mmDC_GPIO_I2CPAD_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_STRENGTH", REG_MMIO, 0x489c, &mmDC_GPIO_I2CPAD_STRENGTH[0], sizeof(mmDC_GPIO_I2CPAD_STRENGTH)/sizeof(mmDC_GPIO_I2CPAD_STRENGTH[0]), 0, 0 },
+	{ "mmDVO_STRENGTH_CONTROL", REG_MMIO, 0x489d, &mmDVO_STRENGTH_CONTROL[0], sizeof(mmDVO_STRENGTH_CONTROL)/sizeof(mmDVO_STRENGTH_CONTROL[0]), 0, 0 },
+	{ "mmDVO_VREF_CONTROL", REG_MMIO, 0x489e, &mmDVO_VREF_CONTROL[0], sizeof(mmDVO_VREF_CONTROL)/sizeof(mmDVO_VREF_CONTROL[0]), 0, 0 },
+	{ "mmDVO_SKEW_ADJUST", REG_MMIO, 0x489f, &mmDVO_SKEW_ADJUST[0], sizeof(mmDVO_SKEW_ADJUST)/sizeof(mmDVO_SKEW_ADJUST[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x48a, NULL, 0, 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48b8, &mmDAC_MACRO_CNTL_RESERVED0[0], sizeof(mmDAC_MACRO_CNTL_RESERVED0)/sizeof(mmDAC_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48b9, &mmDAC_MACRO_CNTL_RESERVED1[0], sizeof(mmDAC_MACRO_CNTL_RESERVED1)/sizeof(mmDAC_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmBPHYC_DAC_MACRO_CNTL", REG_MMIO, 0x48b9, &mmBPHYC_DAC_MACRO_CNTL[0], sizeof(mmBPHYC_DAC_MACRO_CNTL)/sizeof(mmBPHYC_DAC_MACRO_CNTL[0]), 0, 0 },
+	{ "mmBPHYC_DAC_AUTO_CALIB_CONTROL", REG_MMIO, 0x48ba, &mmBPHYC_DAC_AUTO_CALIB_CONTROL[0], sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL)/sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48ba, &mmDAC_MACRO_CNTL_RESERVED2[0], sizeof(mmDAC_MACRO_CNTL_RESERVED2)/sizeof(mmDAC_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48bb, &mmDAC_MACRO_CNTL_RESERVED3[0], sizeof(mmDAC_MACRO_CNTL_RESERVED3)/sizeof(mmDAC_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48c0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1", REG_MMIO, 0x48c0, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48c0, &mmUNIPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED0)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL1", REG_MMIO, 0x48c0, &mmUNIPHY_TX_CONTROL1[0], sizeof(mmUNIPHY_TX_CONTROL1)/sizeof(mmUNIPHY_TX_CONTROL1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48c1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2", REG_MMIO, 0x48c1, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48c1, &mmUNIPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED1)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL2", REG_MMIO, 0x48c1, &mmUNIPHY_TX_CONTROL2[0], sizeof(mmUNIPHY_TX_CONTROL2)/sizeof(mmUNIPHY_TX_CONTROL2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48c2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3", REG_MMIO, 0x48c2, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48c2, &mmUNIPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED2)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL3", REG_MMIO, 0x48c2, &mmUNIPHY_TX_CONTROL3[0], sizeof(mmUNIPHY_TX_CONTROL3)/sizeof(mmUNIPHY_TX_CONTROL3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48c3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4", REG_MMIO, 0x48c3, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48c3, &mmUNIPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED3)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL4", REG_MMIO, 0x48c3, &mmUNIPHY_TX_CONTROL4[0], sizeof(mmUNIPHY_TX_CONTROL4)/sizeof(mmUNIPHY_TX_CONTROL4[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x48c4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL", REG_MMIO, 0x48c4, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x48c4, &mmUNIPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED4)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmUNIPHY_POWER_CONTROL", REG_MMIO, 0x48c4, &mmUNIPHY_POWER_CONTROL[0], sizeof(mmUNIPHY_POWER_CONTROL)/sizeof(mmUNIPHY_POWER_CONTROL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x48c5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV", REG_MMIO, 0x48c5, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x48c5, &mmUNIPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED5)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_FBDIV", REG_MMIO, 0x48c5, &mmUNIPHY_PLL_FBDIV[0], sizeof(mmUNIPHY_PLL_FBDIV)/sizeof(mmUNIPHY_PLL_FBDIV[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x48c6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x48c6, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x48c6, &mmUNIPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED6)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_CONTROL1", REG_MMIO, 0x48c6, &mmUNIPHY_PLL_CONTROL1[0], sizeof(mmUNIPHY_PLL_CONTROL1)/sizeof(mmUNIPHY_PLL_CONTROL1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x48c7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x48c7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x48c7, &mmUNIPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED7)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_CONTROL2", REG_MMIO, 0x48c7, &mmUNIPHY_PLL_CONTROL2[0], sizeof(mmUNIPHY_PLL_CONTROL2)/sizeof(mmUNIPHY_PLL_CONTROL2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x48c8, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x48c8, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x48c8, &mmUNIPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED8)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x48c8, &mmUNIPHY_PLL_SS_STEP_SIZE[0], sizeof(mmUNIPHY_PLL_SS_STEP_SIZE)/sizeof(mmUNIPHY_PLL_SS_STEP_SIZE[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x48c9, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x48c9, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x48c9, &mmUNIPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED9)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_SS_CNTL", REG_MMIO, 0x48c9, &mmUNIPHY_PLL_SS_CNTL[0], sizeof(mmUNIPHY_PLL_SS_CNTL)/sizeof(mmUNIPHY_PLL_SS_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x48ca, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x48ca, &mmUNIPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED10)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmUNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x48ca, &mmUNIPHY_DATA_SYNCHRONIZATION[0], sizeof(mmUNIPHY_DATA_SYNCHRONIZATION)/sizeof(mmUNIPHY_DATA_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x48cb, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x48cb, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x48cb, &mmUNIPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED11)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmUNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x48cb, &mmUNIPHY_REG_TEST_OUTPUT[0], sizeof(mmUNIPHY_REG_TEST_OUTPUT)/sizeof(mmUNIPHY_REG_TEST_OUTPUT[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x48cc, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x48cc, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x48cc, &mmUNIPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED12)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmUNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x48cc, &mmUNIPHY_ANG_BIST_CNTL[0], sizeof(mmUNIPHY_ANG_BIST_CNTL)/sizeof(mmUNIPHY_ANG_BIST_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x48cd, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x48cd, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x48cd, &mmUNIPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED13)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmUNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x48cd, &mmUNIPHY_REG_TEST_OUTPUT2[0], sizeof(mmUNIPHY_REG_TEST_OUTPUT2)/sizeof(mmUNIPHY_REG_TEST_OUTPUT2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x48ce, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0", REG_MMIO, 0x48ce, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x48ce, &mmUNIPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED14)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG0", REG_MMIO, 0x48ce, &mmUNIPHY_TMDP_REG0[0], sizeof(mmUNIPHY_TMDP_REG0)/sizeof(mmUNIPHY_TMDP_REG0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x48cf, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1", REG_MMIO, 0x48cf, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x48cf, &mmUNIPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED15)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG1", REG_MMIO, 0x48cf, &mmUNIPHY_TMDP_REG1[0], sizeof(mmUNIPHY_TMDP_REG1)/sizeof(mmUNIPHY_TMDP_REG1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x48d0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2", REG_MMIO, 0x48d0, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x48d0, &mmUNIPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED16)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG2", REG_MMIO, 0x48d0, &mmUNIPHY_TMDP_REG2[0], sizeof(mmUNIPHY_TMDP_REG2)/sizeof(mmUNIPHY_TMDP_REG2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x48d1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3", REG_MMIO, 0x48d1, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x48d1, &mmUNIPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED17)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG3", REG_MMIO, 0x48d1, &mmUNIPHY_TMDP_REG3[0], sizeof(mmUNIPHY_TMDP_REG3)/sizeof(mmUNIPHY_TMDP_REG3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x48d2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4", REG_MMIO, 0x48d2, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x48d2, &mmUNIPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED18)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG4", REG_MMIO, 0x48d2, &mmUNIPHY_TMDP_REG4[0], sizeof(mmUNIPHY_TMDP_REG4)/sizeof(mmUNIPHY_TMDP_REG4[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x48d3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5", REG_MMIO, 0x48d3, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x48d3, &mmUNIPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED19)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG5", REG_MMIO, 0x48d3, &mmUNIPHY_TMDP_REG5[0], sizeof(mmUNIPHY_TMDP_REG5)/sizeof(mmUNIPHY_TMDP_REG5[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x48d4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6", REG_MMIO, 0x48d4, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x48d4, &mmUNIPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED20)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG6", REG_MMIO, 0x48d4, &mmUNIPHY_TMDP_REG6[0], sizeof(mmUNIPHY_TMDP_REG6)/sizeof(mmUNIPHY_TMDP_REG6[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x48d5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL", REG_MMIO, 0x48d5, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x48d5, &mmUNIPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED21)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmUNIPHY_TPG_CONTROL", REG_MMIO, 0x48d5, &mmUNIPHY_TPG_CONTROL[0], sizeof(mmUNIPHY_TPG_CONTROL)/sizeof(mmUNIPHY_TPG_CONTROL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x48d6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED", REG_MMIO, 0x48d6, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x48d6, &mmUNIPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED22)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmUNIPHY_TPG_SEED", REG_MMIO, 0x48d6, &mmUNIPHY_TPG_SEED[0], sizeof(mmUNIPHY_TPG_SEED)/sizeof(mmUNIPHY_TPG_SEED[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x48d7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x48d7, &mmUNIPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED23)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_DEBUG", REG_MMIO, 0x48d7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_DEBUG", REG_MMIO, 0x48d7, &mmUNIPHY_DEBUG[0], sizeof(mmUNIPHY_DEBUG)/sizeof(mmUNIPHY_DEBUG[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x48d8, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x48d8, &mmUNIPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED24)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x48d9, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x48d9, &mmUNIPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED25)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x48da, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x48da, &mmUNIPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED26)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x48db, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x48db, &mmUNIPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED27)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x48dc, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x48dc, &mmUNIPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED28)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x48dd, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x48dd, &mmUNIPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED29)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x48de, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x48de, &mmUNIPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED30)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x48df, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x48df, &mmUNIPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED31)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48e0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1", REG_MMIO, 0x48e0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48e1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2", REG_MMIO, 0x48e1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48e2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3", REG_MMIO, 0x48e2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48e3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4", REG_MMIO, 0x48e3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x48e4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL", REG_MMIO, 0x48e4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x48e5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV", REG_MMIO, 0x48e5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x48e6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x48e6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x48e7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x48e7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x48e8, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x48e8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x48e9, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x48e9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x48ea, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x48eb, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x48eb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x48ec, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x48ec, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x48ed, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x48ed, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x48ee, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0", REG_MMIO, 0x48ee, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x48ef, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1", REG_MMIO, 0x48ef, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x48f0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2", REG_MMIO, 0x48f0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x48f1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3", REG_MMIO, 0x48f1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x48f2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4", REG_MMIO, 0x48f2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x48f3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5", REG_MMIO, 0x48f3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x48f4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6", REG_MMIO, 0x48f4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x48f5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL", REG_MMIO, 0x48f5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x48f6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED", REG_MMIO, 0x48f6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x48f7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_DEBUG", REG_MMIO, 0x48f7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x48f8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x48f9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x48fa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x48fb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x48fc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x48fd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x48fe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x48ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x490, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4900, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4900, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4901, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4901, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4902, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4902, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4903, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4903, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4904, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4904, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4905, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4905, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4906, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4906, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4907, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4907, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4908, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4908, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4909, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4909, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x490a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x490b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x490b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x490c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x490c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x490d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x490d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x490e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0", REG_MMIO, 0x490e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x490f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1", REG_MMIO, 0x490f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x491, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4910, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2", REG_MMIO, 0x4910, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4911, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3", REG_MMIO, 0x4911, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4912, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4", REG_MMIO, 0x4912, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4913, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5", REG_MMIO, 0x4913, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4914, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6", REG_MMIO, 0x4914, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4915, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4915, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4916, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED", REG_MMIO, 0x4916, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4917, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_DEBUG", REG_MMIO, 0x4917, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4918, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4919, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x491a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x491b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x491c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x491d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x491e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x491f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x492, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4920, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4920, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4921, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4921, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4922, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4922, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4923, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4923, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4924, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4924, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4925, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4925, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4926, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4926, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4927, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4927, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4929, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4929, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x492a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x492b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x492b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x492c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x492c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x492d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x492d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x492e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0", REG_MMIO, 0x492e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x492f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1", REG_MMIO, 0x492f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4930, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2", REG_MMIO, 0x4930, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4931, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3", REG_MMIO, 0x4931, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4932, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4", REG_MMIO, 0x4932, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4933, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5", REG_MMIO, 0x4933, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4934, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6", REG_MMIO, 0x4934, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4935, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4935, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4936, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED", REG_MMIO, 0x4936, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4937, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_DEBUG", REG_MMIO, 0x4937, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4938, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4939, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x493a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x493b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x493c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x493d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x493e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x493f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4940, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4940, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4941, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4941, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4942, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4942, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4943, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4943, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4944, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4944, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4945, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4945, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4946, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4946, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4947, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4947, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4948, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4948, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4949, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4949, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x494a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x494b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x494b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x494c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x494c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x494d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x494d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x494e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0", REG_MMIO, 0x494e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x494f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1", REG_MMIO, 0x494f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4950, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2", REG_MMIO, 0x4950, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4951, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3", REG_MMIO, 0x4951, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4952, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4", REG_MMIO, 0x4952, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4953, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5", REG_MMIO, 0x4953, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4954, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6", REG_MMIO, 0x4954, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4955, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4955, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4956, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED", REG_MMIO, 0x4956, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4957, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_DEBUG", REG_MMIO, 0x4957, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4958, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4959, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x495a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x495b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x495c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x495d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x495e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x495f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4960, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4960, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4961, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4961, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4962, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4962, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4963, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4963, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4964, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4964, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4965, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4965, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4966, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4966, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4967, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4967, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4968, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4968, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4969, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4969, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x496a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x496b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x496b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x496c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x496c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x496d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x496d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x496e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0", REG_MMIO, 0x496e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x496f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1", REG_MMIO, 0x496f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4970, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2", REG_MMIO, 0x4970, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4971, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3", REG_MMIO, 0x4971, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4972, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4", REG_MMIO, 0x4972, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4973, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5", REG_MMIO, 0x4973, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4974, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6", REG_MMIO, 0x4974, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4975, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4975, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4976, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED", REG_MMIO, 0x4976, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4977, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_DEBUG", REG_MMIO, 0x4977, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4978, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4979, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x497a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x497b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x497c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x497d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x497e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x497f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x498, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4980, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4980, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4981, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4981, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4982, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4982, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4983, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4983, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4984, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4984, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4985, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4985, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4986, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4986, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4987, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4987, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4988, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4988, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4989, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4989, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x498a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x498b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x498b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x498c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x498c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x498d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x498d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x498e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0", REG_MMIO, 0x498e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x498f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1", REG_MMIO, 0x498f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x499, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4990, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2", REG_MMIO, 0x4990, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4991, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3", REG_MMIO, 0x4991, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4992, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4", REG_MMIO, 0x4992, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4993, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5", REG_MMIO, 0x4993, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4994, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6", REG_MMIO, 0x4994, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4995, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4995, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4996, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED", REG_MMIO, 0x4996, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4997, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_DEBUG", REG_MMIO, 0x4997, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4998, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4999, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x499a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x499b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x499c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x499d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x499e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x499f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x49a, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_FE_CNTL", REG_MMIO, 0x4a00, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_CNTL", REG_MMIO, 0x4a00, &mmDIG_FE_CNTL[0], sizeof(mmDIG_FE_CNTL)/sizeof(mmDIG_FE_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4a01, NULL, 0, 0, 0 },
+	{ "mmDIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4a01, &mmDIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG_OUTPUT_CRC_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4a02, NULL, 0, 0, 0 },
+	{ "mmDIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4a02, &mmDIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG_OUTPUT_CRC_RESULT[0]), 0, 0 },
+	{ "mmDIG0_DIG_CLOCK_PATTERN", REG_MMIO, 0x4a03, NULL, 0, 0, 0 },
+	{ "mmDIG_CLOCK_PATTERN", REG_MMIO, 0x4a03, &mmDIG_CLOCK_PATTERN[0], sizeof(mmDIG_CLOCK_PATTERN)/sizeof(mmDIG_CLOCK_PATTERN[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_PATTERN", REG_MMIO, 0x4a04, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_PATTERN", REG_MMIO, 0x4a04, &mmDIG_TEST_PATTERN[0], sizeof(mmDIG_TEST_PATTERN)/sizeof(mmDIG_TEST_PATTERN[0]), 0, 0 },
+	{ "mmDIG0_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4a05, NULL, 0, 0, 0 },
+	{ "mmDIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4a05, &mmDIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG_RANDOM_PATTERN_SEED[0]), 0, 0 },
+	{ "mmDIG0_DIG_FIFO_STATUS", REG_MMIO, 0x4a06, NULL, 0, 0, 0 },
+	{ "mmDIG_FIFO_STATUS", REG_MMIO, 0x4a06, &mmDIG_FIFO_STATUS[0], sizeof(mmDIG_FIFO_STATUS)/sizeof(mmDIG_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4a07, NULL, 0, 0, 0 },
+	{ "mmDIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4a07, &mmDIG_DISPCLK_SWITCH_CNTL[0], sizeof(mmDIG_DISPCLK_SWITCH_CNTL)/sizeof(mmDIG_DISPCLK_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4a08, NULL, 0, 0, 0 },
+	{ "mmDIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4a08, &mmDIG_DISPCLK_SWITCH_STATUS[0], sizeof(mmDIG_DISPCLK_SWITCH_STATUS)/sizeof(mmDIG_DISPCLK_SWITCH_STATUS[0]), 0, 0 },
+	{ "mmDIG0_HDMI_CONTROL", REG_MMIO, 0x4a09, NULL, 0, 0, 0 },
+	{ "mmHDMI_CONTROL", REG_MMIO, 0x4a09, &mmHDMI_CONTROL[0], sizeof(mmHDMI_CONTROL)/sizeof(mmHDMI_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_STATUS", REG_MMIO, 0x4a0a, NULL, 0, 0, 0 },
+	{ "mmHDMI_STATUS", REG_MMIO, 0x4a0a, &mmHDMI_STATUS[0], sizeof(mmHDMI_STATUS)/sizeof(mmHDMI_STATUS[0]), 0, 0 },
+	{ "mmDIG0_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a0b, NULL, 0, 0, 0 },
+	{ "mmHDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a0b, &mmHDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmHDMI_AUDIO_PACKET_CONTROL)/sizeof(mmHDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4a0c, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4a0c, &mmHDMI_ACR_PACKET_CONTROL[0], sizeof(mmHDMI_ACR_PACKET_CONTROL)/sizeof(mmHDMI_ACR_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4a0d, NULL, 0, 0, 0 },
+	{ "mmHDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4a0d, &mmHDMI_VBI_PACKET_CONTROL[0], sizeof(mmHDMI_VBI_PACKET_CONTROL)/sizeof(mmHDMI_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4a0e, NULL, 0, 0, 0 },
+	{ "mmHDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4a0e, &mmHDMI_INFOFRAME_CONTROL0[0], sizeof(mmHDMI_INFOFRAME_CONTROL0)/sizeof(mmHDMI_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4a0f, NULL, 0, 0, 0 },
+	{ "mmHDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4a0f, &mmHDMI_INFOFRAME_CONTROL1[0], sizeof(mmHDMI_INFOFRAME_CONTROL1)/sizeof(mmHDMI_INFOFRAME_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4a10, NULL, 0, 0, 0 },
+	{ "mmHDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4a10, &mmHDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmHDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmHDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4a11, NULL, 0, 0, 0 },
+	{ "mmAFMT_INTERRUPT_STATUS", REG_MMIO, 0x4a11, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_GC", REG_MMIO, 0x4a13, NULL, 0, 0, 0 },
+	{ "mmHDMI_GC", REG_MMIO, 0x4a13, &mmHDMI_GC[0], sizeof(mmHDMI_GC)/sizeof(mmHDMI_GC[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4a14, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4a14, &mmAFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_0", REG_MMIO, 0x4a15, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_0", REG_MMIO, 0x4a15, &mmAFMT_ISRC1_0[0], sizeof(mmAFMT_ISRC1_0)/sizeof(mmAFMT_ISRC1_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_1", REG_MMIO, 0x4a16, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_1", REG_MMIO, 0x4a16, &mmAFMT_ISRC1_1[0], sizeof(mmAFMT_ISRC1_1)/sizeof(mmAFMT_ISRC1_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_2", REG_MMIO, 0x4a17, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_2", REG_MMIO, 0x4a17, &mmAFMT_ISRC1_2[0], sizeof(mmAFMT_ISRC1_2)/sizeof(mmAFMT_ISRC1_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_3", REG_MMIO, 0x4a18, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_3", REG_MMIO, 0x4a18, &mmAFMT_ISRC1_3[0], sizeof(mmAFMT_ISRC1_3)/sizeof(mmAFMT_ISRC1_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_4", REG_MMIO, 0x4a19, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_4", REG_MMIO, 0x4a19, &mmAFMT_ISRC1_4[0], sizeof(mmAFMT_ISRC1_4)/sizeof(mmAFMT_ISRC1_4[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_0", REG_MMIO, 0x4a1a, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_0", REG_MMIO, 0x4a1a, &mmAFMT_ISRC2_0[0], sizeof(mmAFMT_ISRC2_0)/sizeof(mmAFMT_ISRC2_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_1", REG_MMIO, 0x4a1b, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_1", REG_MMIO, 0x4a1b, &mmAFMT_ISRC2_1[0], sizeof(mmAFMT_ISRC2_1)/sizeof(mmAFMT_ISRC2_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_2", REG_MMIO, 0x4a1c, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_2", REG_MMIO, 0x4a1c, &mmAFMT_ISRC2_2[0], sizeof(mmAFMT_ISRC2_2)/sizeof(mmAFMT_ISRC2_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_3", REG_MMIO, 0x4a1d, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_3", REG_MMIO, 0x4a1d, &mmAFMT_ISRC2_3[0], sizeof(mmAFMT_ISRC2_3)/sizeof(mmAFMT_ISRC2_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO0", REG_MMIO, 0x4a1e, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO0", REG_MMIO, 0x4a1e, &mmAFMT_AVI_INFO0[0], sizeof(mmAFMT_AVI_INFO0)/sizeof(mmAFMT_AVI_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO1", REG_MMIO, 0x4a1f, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO1", REG_MMIO, 0x4a1f, &mmAFMT_AVI_INFO1[0], sizeof(mmAFMT_AVI_INFO1)/sizeof(mmAFMT_AVI_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO2", REG_MMIO, 0x4a20, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO2", REG_MMIO, 0x4a20, &mmAFMT_AVI_INFO2[0], sizeof(mmAFMT_AVI_INFO2)/sizeof(mmAFMT_AVI_INFO2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO3", REG_MMIO, 0x4a21, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO3", REG_MMIO, 0x4a21, &mmAFMT_AVI_INFO3[0], sizeof(mmAFMT_AVI_INFO3)/sizeof(mmAFMT_AVI_INFO3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_MPEG_INFO0", REG_MMIO, 0x4a22, NULL, 0, 0, 0 },
+	{ "mmAFMT_MPEG_INFO0", REG_MMIO, 0x4a22, &mmAFMT_MPEG_INFO0[0], sizeof(mmAFMT_MPEG_INFO0)/sizeof(mmAFMT_MPEG_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_MPEG_INFO1", REG_MMIO, 0x4a23, NULL, 0, 0, 0 },
+	{ "mmAFMT_MPEG_INFO1", REG_MMIO, 0x4a23, &mmAFMT_MPEG_INFO1[0], sizeof(mmAFMT_MPEG_INFO1)/sizeof(mmAFMT_MPEG_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_HDR", REG_MMIO, 0x4a24, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_HDR", REG_MMIO, 0x4a24, &mmAFMT_GENERIC_HDR[0], sizeof(mmAFMT_GENERIC_HDR)/sizeof(mmAFMT_GENERIC_HDR[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_0", REG_MMIO, 0x4a25, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_0", REG_MMIO, 0x4a25, &mmAFMT_GENERIC_0[0], sizeof(mmAFMT_GENERIC_0)/sizeof(mmAFMT_GENERIC_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_1", REG_MMIO, 0x4a26, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_1", REG_MMIO, 0x4a26, &mmAFMT_GENERIC_1[0], sizeof(mmAFMT_GENERIC_1)/sizeof(mmAFMT_GENERIC_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_2", REG_MMIO, 0x4a27, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_2", REG_MMIO, 0x4a27, &mmAFMT_GENERIC_2[0], sizeof(mmAFMT_GENERIC_2)/sizeof(mmAFMT_GENERIC_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_3", REG_MMIO, 0x4a28, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_3", REG_MMIO, 0x4a28, &mmAFMT_GENERIC_3[0], sizeof(mmAFMT_GENERIC_3)/sizeof(mmAFMT_GENERIC_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_4", REG_MMIO, 0x4a29, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_4", REG_MMIO, 0x4a29, &mmAFMT_GENERIC_4[0], sizeof(mmAFMT_GENERIC_4)/sizeof(mmAFMT_GENERIC_4[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_5", REG_MMIO, 0x4a2a, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_5", REG_MMIO, 0x4a2a, &mmAFMT_GENERIC_5[0], sizeof(mmAFMT_GENERIC_5)/sizeof(mmAFMT_GENERIC_5[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_6", REG_MMIO, 0x4a2b, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_6", REG_MMIO, 0x4a2b, &mmAFMT_GENERIC_6[0], sizeof(mmAFMT_GENERIC_6)/sizeof(mmAFMT_GENERIC_6[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_7", REG_MMIO, 0x4a2c, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_7", REG_MMIO, 0x4a2c, &mmAFMT_GENERIC_7[0], sizeof(mmAFMT_GENERIC_7)/sizeof(mmAFMT_GENERIC_7[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4a2d, NULL, 0, 0, 0 },
+	{ "mmHDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4a2d, &mmHDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmHDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmHDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_0", REG_MMIO, 0x4a2e, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_32_0", REG_MMIO, 0x4a2e, &mmHDMI_ACR_32_0[0], sizeof(mmHDMI_ACR_32_0)/sizeof(mmHDMI_ACR_32_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_1", REG_MMIO, 0x4a2f, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_32_1", REG_MMIO, 0x4a2f, &mmHDMI_ACR_32_1[0], sizeof(mmHDMI_ACR_32_1)/sizeof(mmHDMI_ACR_32_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_0", REG_MMIO, 0x4a30, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_44_0", REG_MMIO, 0x4a30, &mmHDMI_ACR_44_0[0], sizeof(mmHDMI_ACR_44_0)/sizeof(mmHDMI_ACR_44_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_1", REG_MMIO, 0x4a31, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_44_1", REG_MMIO, 0x4a31, &mmHDMI_ACR_44_1[0], sizeof(mmHDMI_ACR_44_1)/sizeof(mmHDMI_ACR_44_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_0", REG_MMIO, 0x4a32, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_48_0", REG_MMIO, 0x4a32, &mmHDMI_ACR_48_0[0], sizeof(mmHDMI_ACR_48_0)/sizeof(mmHDMI_ACR_48_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_1", REG_MMIO, 0x4a33, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_48_1", REG_MMIO, 0x4a33, &mmHDMI_ACR_48_1[0], sizeof(mmHDMI_ACR_48_1)/sizeof(mmHDMI_ACR_48_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_0", REG_MMIO, 0x4a34, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_STATUS_0", REG_MMIO, 0x4a34, &mmHDMI_ACR_STATUS_0[0], sizeof(mmHDMI_ACR_STATUS_0)/sizeof(mmHDMI_ACR_STATUS_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_1", REG_MMIO, 0x4a35, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_STATUS_1", REG_MMIO, 0x4a35, &mmHDMI_ACR_STATUS_1[0], sizeof(mmHDMI_ACR_STATUS_1)/sizeof(mmHDMI_ACR_STATUS_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_INFO0", REG_MMIO, 0x4a36, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO0", REG_MMIO, 0x4a36, &mmAFMT_AUDIO_INFO0[0], sizeof(mmAFMT_AUDIO_INFO0)/sizeof(mmAFMT_AUDIO_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_INFO1", REG_MMIO, 0x4a37, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO1", REG_MMIO, 0x4a37, &mmAFMT_AUDIO_INFO1[0], sizeof(mmAFMT_AUDIO_INFO1)/sizeof(mmAFMT_AUDIO_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_0", REG_MMIO, 0x4a38, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_0", REG_MMIO, 0x4a38, &mmAFMT_60958_0[0], sizeof(mmAFMT_60958_0)/sizeof(mmAFMT_60958_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_1", REG_MMIO, 0x4a39, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_1", REG_MMIO, 0x4a39, &mmAFMT_60958_1[0], sizeof(mmAFMT_60958_1)/sizeof(mmAFMT_60958_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4a3a, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4a3a, &mmAFMT_AUDIO_CRC_CONTROL[0], sizeof(mmAFMT_AUDIO_CRC_CONTROL)/sizeof(mmAFMT_AUDIO_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4a3b, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL0", REG_MMIO, 0x4a3b, &mmAFMT_RAMP_CONTROL0[0], sizeof(mmAFMT_RAMP_CONTROL0)/sizeof(mmAFMT_RAMP_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4a3c, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL1", REG_MMIO, 0x4a3c, &mmAFMT_RAMP_CONTROL1[0], sizeof(mmAFMT_RAMP_CONTROL1)/sizeof(mmAFMT_RAMP_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4a3d, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL2", REG_MMIO, 0x4a3d, &mmAFMT_RAMP_CONTROL2[0], sizeof(mmAFMT_RAMP_CONTROL2)/sizeof(mmAFMT_RAMP_CONTROL2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4a3e, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL3", REG_MMIO, 0x4a3e, &mmAFMT_RAMP_CONTROL3[0], sizeof(mmAFMT_RAMP_CONTROL3)/sizeof(mmAFMT_RAMP_CONTROL3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_2", REG_MMIO, 0x4a3f, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_2", REG_MMIO, 0x4a3f, &mmAFMT_60958_2[0], sizeof(mmAFMT_60958_2)/sizeof(mmAFMT_60958_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4a40, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4a40, &mmAFMT_AUDIO_CRC_RESULT[0], sizeof(mmAFMT_AUDIO_CRC_RESULT)/sizeof(mmAFMT_AUDIO_CRC_RESULT[0]), 0, 0 },
+	{ "mmDIG0_AFMT_STATUS", REG_MMIO, 0x4a41, NULL, 0, 0, 0 },
+	{ "mmAFMT_STATUS", REG_MMIO, 0x4a41, &mmAFMT_STATUS[0], sizeof(mmAFMT_STATUS)/sizeof(mmAFMT_STATUS[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a42, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a42, &mmAFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4a43, NULL, 0, 0, 0 },
+	{ "mmAFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4a43, &mmAFMT_VBI_PACKET_CONTROL[0], sizeof(mmAFMT_VBI_PACKET_CONTROL)/sizeof(mmAFMT_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4a44, NULL, 0, 0, 0 },
+	{ "mmAFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4a44, &mmAFMT_INFOFRAME_CONTROL0[0], sizeof(mmAFMT_INFOFRAME_CONTROL0)/sizeof(mmAFMT_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4a45, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4a45, &mmAFMT_AUDIO_SRC_CONTROL[0], sizeof(mmAFMT_AUDIO_SRC_CONTROL)/sizeof(mmAFMT_AUDIO_SRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4a46, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4a46, &mmAFMT_AUDIO_DBG_DTO_CNTL[0], sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL)/sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_CNTL", REG_MMIO, 0x4a47, NULL, 0, 0, 0 },
+	{ "mmDIG_BE_CNTL", REG_MMIO, 0x4a47, &mmDIG_BE_CNTL[0], sizeof(mmDIG_BE_CNTL)/sizeof(mmDIG_BE_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_EN_CNTL", REG_MMIO, 0x4a48, NULL, 0, 0, 0 },
+	{ "mmDIG_BE_EN_CNTL", REG_MMIO, 0x4a48, &mmDIG_BE_EN_CNTL[0], sizeof(mmDIG_BE_EN_CNTL)/sizeof(mmDIG_BE_EN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CNTL", REG_MMIO, 0x4a6b, NULL, 0, 0, 0 },
+	{ "mmTMDS_CNTL", REG_MMIO, 0x4a6b, &mmTMDS_CNTL[0], sizeof(mmTMDS_CNTL)/sizeof(mmTMDS_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL_CHAR", REG_MMIO, 0x4a6c, NULL, 0, 0, 0 },
+	{ "mmTMDS_CONTROL_CHAR", REG_MMIO, 0x4a6c, &mmTMDS_CONTROL_CHAR[0], sizeof(mmTMDS_CONTROL_CHAR)/sizeof(mmTMDS_CONTROL_CHAR[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4a6d, NULL, 0, 0, 0 },
+	{ "mmTMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4a6d, &mmTMDS_CONTROL0_FEEDBACK[0], sizeof(mmTMDS_CONTROL0_FEEDBACK)/sizeof(mmTMDS_CONTROL0_FEEDBACK[0]), 0, 0 },
+	{ "mmDIG0_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4a6e, NULL, 0, 0, 0 },
+	{ "mmTMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4a6e, &mmTMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmTMDS_STEREOSYNC_CTL_SEL)/sizeof(mmTMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4a6f, NULL, 0, 0, 0 },
+	{ "mmTMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4a6f, &mmTMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmTMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmTMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4a70, NULL, 0, 0, 0 },
+	{ "mmTMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4a70, &mmTMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmTMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmTMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 },
+	{ "mmDIG0_TMDS_DEBUG", REG_MMIO, 0x4a71, NULL, 0, 0, 0 },
+	{ "mmTMDS_DEBUG", REG_MMIO, 0x4a71, &mmTMDS_DEBUG[0], sizeof(mmTMDS_DEBUG)/sizeof(mmTMDS_DEBUG[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL_BITS", REG_MMIO, 0x4a72, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL_BITS", REG_MMIO, 0x4a72, &mmTMDS_CTL_BITS[0], sizeof(mmTMDS_CTL_BITS)/sizeof(mmTMDS_CTL_BITS[0]), 0, 0 },
+	{ "mmDIG0_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4a73, NULL, 0, 0, 0 },
+	{ "mmTMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4a73, &mmTMDS_DCBALANCER_CONTROL[0], sizeof(mmTMDS_DCBALANCER_CONTROL)/sizeof(mmTMDS_DCBALANCER_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4a75, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4a75, &mmTMDS_CTL0_1_GEN_CNTL[0], sizeof(mmTMDS_CTL0_1_GEN_CNTL)/sizeof(mmTMDS_CTL0_1_GEN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4a76, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4a76, &mmTMDS_CTL2_3_GEN_CNTL[0], sizeof(mmTMDS_CTL2_3_GEN_CNTL)/sizeof(mmTMDS_CTL2_3_GEN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_LVDS_DATA_CNTL", REG_MMIO, 0x4a78, NULL, 0, 0, 0 },
+	{ "mmLVDS_DATA_CNTL", REG_MMIO, 0x4a78, &mmLVDS_DATA_CNTL[0], sizeof(mmLVDS_DATA_CNTL)/sizeof(mmLVDS_DATA_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_LANE_ENABLE", REG_MMIO, 0x4a79, NULL, 0, 0, 0 },
+	{ "mmDIG_LANE_ENABLE", REG_MMIO, 0x4a79, &mmDIG_LANE_ENABLE[0], sizeof(mmDIG_LANE_ENABLE)/sizeof(mmDIG_LANE_ENABLE[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7a, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7a, &mmDIG_TEST_DEBUG_INDEX[0], sizeof(mmDIG_TEST_DEBUG_INDEX)/sizeof(mmDIG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4a7b, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_DEBUG_DATA", REG_MMIO, 0x4a7b, &mmDIG_TEST_DEBUG_DATA[0], sizeof(mmDIG_TEST_DEBUG_DATA)/sizeof(mmDIG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDIG0_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7c, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7c, &mmDIG_FE_TEST_DEBUG_INDEX[0], sizeof(mmDIG_FE_TEST_DEBUG_INDEX)/sizeof(mmDIG_FE_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDIG0_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4a7d, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4a7d, &mmDIG_FE_TEST_DEBUG_DATA[0], sizeof(mmDIG_FE_TEST_DEBUG_DATA)/sizeof(mmDIG_FE_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP0_DP_LINK_CNTL", REG_MMIO, 0x4aa0, NULL, 0, 0, 0 },
+	{ "mmDP_LINK_CNTL", REG_MMIO, 0x4aa0, &mmDP_LINK_CNTL[0], sizeof(mmDP_LINK_CNTL)/sizeof(mmDP_LINK_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_PIXEL_FORMAT", REG_MMIO, 0x4aa1, NULL, 0, 0, 0 },
+	{ "mmDP_PIXEL_FORMAT", REG_MMIO, 0x4aa1, &mmDP_PIXEL_FORMAT[0], sizeof(mmDP_PIXEL_FORMAT)/sizeof(mmDP_PIXEL_FORMAT[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_COLORIMETRY", REG_MMIO, 0x4aa2, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_COLORIMETRY", REG_MMIO, 0x4aa2, &mmDP_MSA_COLORIMETRY[0], sizeof(mmDP_MSA_COLORIMETRY)/sizeof(mmDP_MSA_COLORIMETRY[0]), 0, 0 },
+	{ "mmDP0_DP_CONFIG", REG_MMIO, 0x4aa3, NULL, 0, 0, 0 },
+	{ "mmDP_CONFIG", REG_MMIO, 0x4aa3, &mmDP_CONFIG[0], sizeof(mmDP_CONFIG)/sizeof(mmDP_CONFIG[0]), 0, 0 },
+	{ "mmDP0_DP_VID_STREAM_CNTL", REG_MMIO, 0x4aa4, NULL, 0, 0, 0 },
+	{ "mmDP_VID_STREAM_CNTL", REG_MMIO, 0x4aa4, &mmDP_VID_STREAM_CNTL[0], sizeof(mmDP_VID_STREAM_CNTL)/sizeof(mmDP_VID_STREAM_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_STEER_FIFO", REG_MMIO, 0x4aa5, NULL, 0, 0, 0 },
+	{ "mmDP_STEER_FIFO", REG_MMIO, 0x4aa5, &mmDP_STEER_FIFO[0], sizeof(mmDP_STEER_FIFO)/sizeof(mmDP_STEER_FIFO[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_MISC", REG_MMIO, 0x4aa6, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_MISC", REG_MMIO, 0x4aa6, &mmDP_MSA_MISC[0], sizeof(mmDP_MSA_MISC)/sizeof(mmDP_MSA_MISC[0]), 0, 0 },
+	{ "mmDP0_DP_VID_TIMING", REG_MMIO, 0x4aa8, NULL, 0, 0, 0 },
+	{ "mmDP_VID_TIMING", REG_MMIO, 0x4aa8, &mmDP_VID_TIMING[0], sizeof(mmDP_VID_TIMING)/sizeof(mmDP_VID_TIMING[0]), 0, 0 },
+	{ "mmDP0_DP_VID_N", REG_MMIO, 0x4aa9, NULL, 0, 0, 0 },
+	{ "mmDP_VID_N", REG_MMIO, 0x4aa9, &mmDP_VID_N[0], sizeof(mmDP_VID_N)/sizeof(mmDP_VID_N[0]), 0, 0 },
+	{ "mmDP0_DP_VID_M", REG_MMIO, 0x4aaa, NULL, 0, 0, 0 },
+	{ "mmDP_VID_M", REG_MMIO, 0x4aaa, &mmDP_VID_M[0], sizeof(mmDP_VID_M)/sizeof(mmDP_VID_M[0]), 0, 0 },
+	{ "mmDP0_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4aab, NULL, 0, 0, 0 },
+	{ "mmDP_LINK_FRAMING_CNTL", REG_MMIO, 0x4aab, &mmDP_LINK_FRAMING_CNTL[0], sizeof(mmDP_LINK_FRAMING_CNTL)/sizeof(mmDP_LINK_FRAMING_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4aac, NULL, 0, 0, 0 },
+	{ "mmDP_HBR2_EYE_PATTERN", REG_MMIO, 0x4aac, &mmDP_HBR2_EYE_PATTERN[0], sizeof(mmDP_HBR2_EYE_PATTERN)/sizeof(mmDP_HBR2_EYE_PATTERN[0]), 0, 0 },
+	{ "mmDP0_DP_VID_MSA_VBID", REG_MMIO, 0x4aad, NULL, 0, 0, 0 },
+	{ "mmDP_VID_MSA_VBID", REG_MMIO, 0x4aad, &mmDP_VID_MSA_VBID[0], sizeof(mmDP_VID_MSA_VBID)/sizeof(mmDP_VID_MSA_VBID[0]), 0, 0 },
+	{ "mmDP0_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4aae, NULL, 0, 0, 0 },
+	{ "mmDP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4aae, &mmDP_VID_INTERRUPT_CNTL[0], sizeof(mmDP_VID_INTERRUPT_CNTL)/sizeof(mmDP_VID_INTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CNTL", REG_MMIO, 0x4aaf, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CNTL", REG_MMIO, 0x4aaf, &mmDP_DPHY_CNTL[0], sizeof(mmDP_DPHY_CNTL)/sizeof(mmDP_DPHY_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4ab0, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4ab0, &mmDP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM0", REG_MMIO, 0x4ab1, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM0", REG_MMIO, 0x4ab1, &mmDP_DPHY_SYM0[0], sizeof(mmDP_DPHY_SYM0)/sizeof(mmDP_DPHY_SYM0[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM1", REG_MMIO, 0x4ab2, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM1", REG_MMIO, 0x4ab2, &mmDP_DPHY_SYM1[0], sizeof(mmDP_DPHY_SYM1)/sizeof(mmDP_DPHY_SYM1[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM2", REG_MMIO, 0x4ab3, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM2", REG_MMIO, 0x4ab3, &mmDP_DPHY_SYM2[0], sizeof(mmDP_DPHY_SYM2)/sizeof(mmDP_DPHY_SYM2[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4ab4, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_8B10B_CNTL", REG_MMIO, 0x4ab4, &mmDP_DPHY_8B10B_CNTL[0], sizeof(mmDP_DPHY_8B10B_CNTL)/sizeof(mmDP_DPHY_8B10B_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4ab5, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_PRBS_CNTL", REG_MMIO, 0x4ab5, &mmDP_DPHY_PRBS_CNTL[0], sizeof(mmDP_DPHY_PRBS_CNTL)/sizeof(mmDP_DPHY_PRBS_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4ab6, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4ab6, &mmDP_DPHY_SCRAM_CNTL[0], sizeof(mmDP_DPHY_SCRAM_CNTL)/sizeof(mmDP_DPHY_SCRAM_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_EN", REG_MMIO, 0x4ab7, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_EN", REG_MMIO, 0x4ab7, &mmDP_DPHY_CRC_EN[0], sizeof(mmDP_DPHY_CRC_EN)/sizeof(mmDP_DPHY_CRC_EN[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4ab8, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_CNTL", REG_MMIO, 0x4ab8, &mmDP_DPHY_CRC_CNTL[0], sizeof(mmDP_DPHY_CRC_CNTL)/sizeof(mmDP_DPHY_CRC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4ab9, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_RESULT", REG_MMIO, 0x4ab9, &mmDP_DPHY_CRC_RESULT[0], sizeof(mmDP_DPHY_CRC_RESULT)/sizeof(mmDP_DPHY_CRC_RESULT[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4aba, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4aba, &mmDP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP_DPHY_CRC_MST_CNTL)/sizeof(mmDP_DPHY_CRC_MST_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4abb, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4abb, &mmDP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP_DPHY_CRC_MST_STATUS)/sizeof(mmDP_DPHY_CRC_MST_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4abc, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_FAST_TRAINING", REG_MMIO, 0x4abc, &mmDP_DPHY_FAST_TRAINING[0], sizeof(mmDP_DPHY_FAST_TRAINING)/sizeof(mmDP_DPHY_FAST_TRAINING[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4abd, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4abd, &mmDP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4abe, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4abe, &mmDP_MSA_V_TIMING_OVERRIDE1[0], sizeof(mmDP_MSA_V_TIMING_OVERRIDE1)/sizeof(mmDP_MSA_V_TIMING_OVERRIDE1[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4abf, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4abf, &mmDP_MSA_V_TIMING_OVERRIDE2[0], sizeof(mmDP_MSA_V_TIMING_OVERRIDE2)/sizeof(mmDP_MSA_V_TIMING_OVERRIDE2[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL", REG_MMIO, 0x4ac3, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_CNTL", REG_MMIO, 0x4ac3, &mmDP_SEC_CNTL[0], sizeof(mmDP_SEC_CNTL)/sizeof(mmDP_SEC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL1", REG_MMIO, 0x4ac4, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_CNTL1", REG_MMIO, 0x4ac4, &mmDP_SEC_CNTL1[0], sizeof(mmDP_SEC_CNTL1)/sizeof(mmDP_SEC_CNTL1[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING1", REG_MMIO, 0x4ac5, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING1", REG_MMIO, 0x4ac5, &mmDP_SEC_FRAMING1[0], sizeof(mmDP_SEC_FRAMING1)/sizeof(mmDP_SEC_FRAMING1[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING2", REG_MMIO, 0x4ac6, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING2", REG_MMIO, 0x4ac6, &mmDP_SEC_FRAMING2[0], sizeof(mmDP_SEC_FRAMING2)/sizeof(mmDP_SEC_FRAMING2[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING3", REG_MMIO, 0x4ac7, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING3", REG_MMIO, 0x4ac7, &mmDP_SEC_FRAMING3[0], sizeof(mmDP_SEC_FRAMING3)/sizeof(mmDP_SEC_FRAMING3[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING4", REG_MMIO, 0x4ac8, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING4", REG_MMIO, 0x4ac8, &mmDP_SEC_FRAMING4[0], sizeof(mmDP_SEC_FRAMING4)/sizeof(mmDP_SEC_FRAMING4[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N", REG_MMIO, 0x4ac9, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_N", REG_MMIO, 0x4ac9, &mmDP_SEC_AUD_N[0], sizeof(mmDP_SEC_AUD_N)/sizeof(mmDP_SEC_AUD_N[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4aca, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_N_READBACK", REG_MMIO, 0x4aca, &mmDP_SEC_AUD_N_READBACK[0], sizeof(mmDP_SEC_AUD_N_READBACK)/sizeof(mmDP_SEC_AUD_N_READBACK[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M", REG_MMIO, 0x4acb, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_M", REG_MMIO, 0x4acb, &mmDP_SEC_AUD_M[0], sizeof(mmDP_SEC_AUD_M)/sizeof(mmDP_SEC_AUD_M[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4acc, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_M_READBACK", REG_MMIO, 0x4acc, &mmDP_SEC_AUD_M_READBACK[0], sizeof(mmDP_SEC_AUD_M_READBACK)/sizeof(mmDP_SEC_AUD_M_READBACK[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_TIMESTAMP", REG_MMIO, 0x4acd, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_TIMESTAMP", REG_MMIO, 0x4acd, &mmDP_SEC_TIMESTAMP[0], sizeof(mmDP_SEC_TIMESTAMP)/sizeof(mmDP_SEC_TIMESTAMP[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4ace, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_PACKET_CNTL", REG_MMIO, 0x4ace, &mmDP_SEC_PACKET_CNTL[0], sizeof(mmDP_SEC_PACKET_CNTL)/sizeof(mmDP_SEC_PACKET_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_CNTL", REG_MMIO, 0x4acf, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_RATE_CNTL", REG_MMIO, 0x4acf, &mmDP_MSE_RATE_CNTL[0], sizeof(mmDP_MSE_RATE_CNTL)/sizeof(mmDP_MSE_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4ad1, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_RATE_UPDATE", REG_MMIO, 0x4ad1, &mmDP_MSE_RATE_UPDATE[0], sizeof(mmDP_MSE_RATE_UPDATE)/sizeof(mmDP_MSE_RATE_UPDATE[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT0", REG_MMIO, 0x4ad2, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT0", REG_MMIO, 0x4ad2, &mmDP_MSE_SAT0[0], sizeof(mmDP_MSE_SAT0)/sizeof(mmDP_MSE_SAT0[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT1", REG_MMIO, 0x4ad3, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT1", REG_MMIO, 0x4ad3, &mmDP_MSE_SAT1[0], sizeof(mmDP_MSE_SAT1)/sizeof(mmDP_MSE_SAT1[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT2", REG_MMIO, 0x4ad4, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT2", REG_MMIO, 0x4ad4, &mmDP_MSE_SAT2[0], sizeof(mmDP_MSE_SAT2)/sizeof(mmDP_MSE_SAT2[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4ad5, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT_UPDATE", REG_MMIO, 0x4ad5, &mmDP_MSE_SAT_UPDATE[0], sizeof(mmDP_MSE_SAT_UPDATE)/sizeof(mmDP_MSE_SAT_UPDATE[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_LINK_TIMING", REG_MMIO, 0x4ad6, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_LINK_TIMING", REG_MMIO, 0x4ad6, &mmDP_MSE_LINK_TIMING[0], sizeof(mmDP_MSE_LINK_TIMING)/sizeof(mmDP_MSE_LINK_TIMING[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_MISC_CNTL", REG_MMIO, 0x4ad7, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_MISC_CNTL", REG_MMIO, 0x4ad7, &mmDP_MSE_MISC_CNTL[0], sizeof(mmDP_MSE_MISC_CNTL)/sizeof(mmDP_MSE_MISC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ad8, NULL, 0, 0, 0 },
+	{ "mmDP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ad8, &mmDP_TEST_DEBUG_INDEX[0], sizeof(mmDP_TEST_DEBUG_INDEX)/sizeof(mmDP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4ad9, NULL, 0, 0, 0 },
+	{ "mmDP_TEST_DEBUG_DATA", REG_MMIO, 0x4ad9, &mmDP_TEST_DEBUG_DATA[0], sizeof(mmDP_TEST_DEBUG_DATA)/sizeof(mmDP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP0_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4ada, NULL, 0, 0, 0 },
+	{ "mmDP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4ada, &mmDP_FE_TEST_DEBUG_INDEX[0], sizeof(mmDP_FE_TEST_DEBUG_INDEX)/sizeof(mmDP_FE_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP0_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4adb, NULL, 0, 0, 0 },
+	{ "mmDP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4adb, &mmDP_FE_TEST_DEBUG_DATA[0], sizeof(mmDP_FE_TEST_DEBUG_DATA)/sizeof(mmDP_FE_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDIG1_DIG_FE_CNTL", REG_MMIO, 0x4b00, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4b01, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4b02, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_CLOCK_PATTERN", REG_MMIO, 0x4b03, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_PATTERN", REG_MMIO, 0x4b04, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4b05, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FIFO_STATUS", REG_MMIO, 0x4b06, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4b07, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4b08, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_CONTROL", REG_MMIO, 0x4b09, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_STATUS", REG_MMIO, 0x4b0a, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4b0b, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4b0c, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4b0d, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4b0e, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4b0f, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4b10, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4b11, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GC", REG_MMIO, 0x4b13, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4b14, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_0", REG_MMIO, 0x4b15, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_1", REG_MMIO, 0x4b16, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_2", REG_MMIO, 0x4b17, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_3", REG_MMIO, 0x4b18, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_4", REG_MMIO, 0x4b19, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_0", REG_MMIO, 0x4b1a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_1", REG_MMIO, 0x4b1b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_2", REG_MMIO, 0x4b1c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_3", REG_MMIO, 0x4b1d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO0", REG_MMIO, 0x4b1e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO1", REG_MMIO, 0x4b1f, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO2", REG_MMIO, 0x4b20, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO3", REG_MMIO, 0x4b21, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO0", REG_MMIO, 0x4b22, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO1", REG_MMIO, 0x4b23, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_HDR", REG_MMIO, 0x4b24, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_0", REG_MMIO, 0x4b25, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_1", REG_MMIO, 0x4b26, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_2", REG_MMIO, 0x4b27, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_3", REG_MMIO, 0x4b28, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_4", REG_MMIO, 0x4b29, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_5", REG_MMIO, 0x4b2a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_6", REG_MMIO, 0x4b2b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_7", REG_MMIO, 0x4b2c, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4b2d, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_0", REG_MMIO, 0x4b2e, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_1", REG_MMIO, 0x4b2f, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_0", REG_MMIO, 0x4b30, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_1", REG_MMIO, 0x4b31, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_0", REG_MMIO, 0x4b32, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_1", REG_MMIO, 0x4b33, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_0", REG_MMIO, 0x4b34, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_1", REG_MMIO, 0x4b35, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO0", REG_MMIO, 0x4b36, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO1", REG_MMIO, 0x4b37, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_0", REG_MMIO, 0x4b38, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_1", REG_MMIO, 0x4b39, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4b3a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4b3b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4b3c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4b3d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4b3e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_2", REG_MMIO, 0x4b3f, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4b40, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_STATUS", REG_MMIO, 0x4b41, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4b42, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4b43, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4b44, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4b45, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4b46, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_CNTL", REG_MMIO, 0x4b47, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_EN_CNTL", REG_MMIO, 0x4b48, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CNTL", REG_MMIO, 0x4b6b, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL_CHAR", REG_MMIO, 0x4b6c, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4b6d, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4b6e, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4b6f, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4b70, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DEBUG", REG_MMIO, 0x4b71, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL_BITS", REG_MMIO, 0x4b72, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4b73, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4b75, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4b76, NULL, 0, 0, 0 },
+	{ "mmDIG1_LVDS_DATA_CNTL", REG_MMIO, 0x4b78, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_LANE_ENABLE", REG_MMIO, 0x4b79, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4b7a, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4b7b, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4b7c, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4b7d, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_CNTL", REG_MMIO, 0x4ba0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_PIXEL_FORMAT", REG_MMIO, 0x4ba1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ba2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_CONFIG", REG_MMIO, 0x4ba3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ba4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_STEER_FIFO", REG_MMIO, 0x4ba5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_MISC", REG_MMIO, 0x4ba6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_TIMING", REG_MMIO, 0x4ba8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_N", REG_MMIO, 0x4ba9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_M", REG_MMIO, 0x4baa, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4bab, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4bac, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_MSA_VBID", REG_MMIO, 0x4bad, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4bae, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CNTL", REG_MMIO, 0x4baf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4bb0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM0", REG_MMIO, 0x4bb1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM1", REG_MMIO, 0x4bb2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM2", REG_MMIO, 0x4bb3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4bb4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4bb5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4bb6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_EN", REG_MMIO, 0x4bb7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4bb8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4bb9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4bba, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4bbb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4bbc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4bbd, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4bbe, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4bbf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL", REG_MMIO, 0x4bc3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL1", REG_MMIO, 0x4bc4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING1", REG_MMIO, 0x4bc5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING2", REG_MMIO, 0x4bc6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING3", REG_MMIO, 0x4bc7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING4", REG_MMIO, 0x4bc8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N", REG_MMIO, 0x4bc9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4bca, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M", REG_MMIO, 0x4bcb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4bcc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_TIMESTAMP", REG_MMIO, 0x4bcd, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4bce, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_CNTL", REG_MMIO, 0x4bcf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4bd1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT0", REG_MMIO, 0x4bd2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT1", REG_MMIO, 0x4bd3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT2", REG_MMIO, 0x4bd4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4bd5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_LINK_TIMING", REG_MMIO, 0x4bd6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_MISC_CNTL", REG_MMIO, 0x4bd7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4bd8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4bd9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4bda, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4bdb, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_CNTL", REG_MMIO, 0x4c00, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4c01, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4c02, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_CLOCK_PATTERN", REG_MMIO, 0x4c03, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_PATTERN", REG_MMIO, 0x4c04, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4c05, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FIFO_STATUS", REG_MMIO, 0x4c06, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4c07, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4c08, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_CONTROL", REG_MMIO, 0x4c09, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_STATUS", REG_MMIO, 0x4c0a, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4c0b, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4c0c, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4c0d, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4c0e, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4c0f, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4c10, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4c11, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GC", REG_MMIO, 0x4c13, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4c14, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_0", REG_MMIO, 0x4c15, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_1", REG_MMIO, 0x4c16, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_2", REG_MMIO, 0x4c17, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_3", REG_MMIO, 0x4c18, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_4", REG_MMIO, 0x4c19, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_0", REG_MMIO, 0x4c1a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_1", REG_MMIO, 0x4c1b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_2", REG_MMIO, 0x4c1c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_3", REG_MMIO, 0x4c1d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO0", REG_MMIO, 0x4c1e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO1", REG_MMIO, 0x4c1f, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO2", REG_MMIO, 0x4c20, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO3", REG_MMIO, 0x4c21, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO0", REG_MMIO, 0x4c22, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO1", REG_MMIO, 0x4c23, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_HDR", REG_MMIO, 0x4c24, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_0", REG_MMIO, 0x4c25, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_1", REG_MMIO, 0x4c26, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_2", REG_MMIO, 0x4c27, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_3", REG_MMIO, 0x4c28, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_4", REG_MMIO, 0x4c29, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_5", REG_MMIO, 0x4c2a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_6", REG_MMIO, 0x4c2b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_7", REG_MMIO, 0x4c2c, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4c2d, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_0", REG_MMIO, 0x4c2e, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_1", REG_MMIO, 0x4c2f, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_0", REG_MMIO, 0x4c30, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_1", REG_MMIO, 0x4c31, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_0", REG_MMIO, 0x4c32, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_1", REG_MMIO, 0x4c33, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_0", REG_MMIO, 0x4c34, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_1", REG_MMIO, 0x4c35, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO0", REG_MMIO, 0x4c36, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO1", REG_MMIO, 0x4c37, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_0", REG_MMIO, 0x4c38, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_1", REG_MMIO, 0x4c39, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4c3a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4c3b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4c3c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4c3d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4c3e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_2", REG_MMIO, 0x4c3f, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4c40, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_STATUS", REG_MMIO, 0x4c41, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4c42, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4c43, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4c44, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4c45, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4c46, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_CNTL", REG_MMIO, 0x4c47, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_EN_CNTL", REG_MMIO, 0x4c48, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CNTL", REG_MMIO, 0x4c6b, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL_CHAR", REG_MMIO, 0x4c6c, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4c6d, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4c6e, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4c6f, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4c70, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DEBUG", REG_MMIO, 0x4c71, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL_BITS", REG_MMIO, 0x4c72, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4c73, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4c75, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4c76, NULL, 0, 0, 0 },
+	{ "mmDIG2_LVDS_DATA_CNTL", REG_MMIO, 0x4c78, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_LANE_ENABLE", REG_MMIO, 0x4c79, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4c7a, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4c7b, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4c7c, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4c7d, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_CNTL", REG_MMIO, 0x4ca0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_PIXEL_FORMAT", REG_MMIO, 0x4ca1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ca2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_CONFIG", REG_MMIO, 0x4ca3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ca4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_STEER_FIFO", REG_MMIO, 0x4ca5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_MISC", REG_MMIO, 0x4ca6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_TIMING", REG_MMIO, 0x4ca8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_N", REG_MMIO, 0x4ca9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_M", REG_MMIO, 0x4caa, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4cab, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4cac, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_MSA_VBID", REG_MMIO, 0x4cad, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4cae, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CNTL", REG_MMIO, 0x4caf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4cb0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM0", REG_MMIO, 0x4cb1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM1", REG_MMIO, 0x4cb2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM2", REG_MMIO, 0x4cb3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4cb4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4cb5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4cb6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_EN", REG_MMIO, 0x4cb7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4cb8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4cb9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4cba, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4cbb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4cbc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4cbd, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4cbe, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4cbf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL", REG_MMIO, 0x4cc3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL1", REG_MMIO, 0x4cc4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING1", REG_MMIO, 0x4cc5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING2", REG_MMIO, 0x4cc6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING3", REG_MMIO, 0x4cc7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING4", REG_MMIO, 0x4cc8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N", REG_MMIO, 0x4cc9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4cca, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M", REG_MMIO, 0x4ccb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4ccc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_TIMESTAMP", REG_MMIO, 0x4ccd, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4cce, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_CNTL", REG_MMIO, 0x4ccf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4cd1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT0", REG_MMIO, 0x4cd2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT1", REG_MMIO, 0x4cd3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT2", REG_MMIO, 0x4cd4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4cd5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_LINK_TIMING", REG_MMIO, 0x4cd6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_MISC_CNTL", REG_MMIO, 0x4cd7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4cd8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4cd9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4cda, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4cdb, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_CNTL", REG_MMIO, 0x4d00, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4d01, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4d02, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_CLOCK_PATTERN", REG_MMIO, 0x4d03, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_PATTERN", REG_MMIO, 0x4d04, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4d05, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FIFO_STATUS", REG_MMIO, 0x4d06, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4d07, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4d08, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_CONTROL", REG_MMIO, 0x4d09, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_STATUS", REG_MMIO, 0x4d0a, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4d0b, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4d0c, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4d0d, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4d0e, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4d0f, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4d10, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4d11, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GC", REG_MMIO, 0x4d13, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4d14, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_0", REG_MMIO, 0x4d15, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_1", REG_MMIO, 0x4d16, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_2", REG_MMIO, 0x4d17, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_3", REG_MMIO, 0x4d18, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_4", REG_MMIO, 0x4d19, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_0", REG_MMIO, 0x4d1a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_1", REG_MMIO, 0x4d1b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_2", REG_MMIO, 0x4d1c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_3", REG_MMIO, 0x4d1d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO0", REG_MMIO, 0x4d1e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO1", REG_MMIO, 0x4d1f, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO2", REG_MMIO, 0x4d20, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO3", REG_MMIO, 0x4d21, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO0", REG_MMIO, 0x4d22, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO1", REG_MMIO, 0x4d23, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_HDR", REG_MMIO, 0x4d24, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_0", REG_MMIO, 0x4d25, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_1", REG_MMIO, 0x4d26, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_2", REG_MMIO, 0x4d27, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_3", REG_MMIO, 0x4d28, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_4", REG_MMIO, 0x4d29, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_5", REG_MMIO, 0x4d2a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_6", REG_MMIO, 0x4d2b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_7", REG_MMIO, 0x4d2c, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4d2d, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_0", REG_MMIO, 0x4d2e, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_1", REG_MMIO, 0x4d2f, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_0", REG_MMIO, 0x4d30, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_1", REG_MMIO, 0x4d31, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_0", REG_MMIO, 0x4d32, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_1", REG_MMIO, 0x4d33, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_0", REG_MMIO, 0x4d34, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_1", REG_MMIO, 0x4d35, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO0", REG_MMIO, 0x4d36, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO1", REG_MMIO, 0x4d37, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_0", REG_MMIO, 0x4d38, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_1", REG_MMIO, 0x4d39, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4d3a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4d3b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4d3c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4d3d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4d3e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_2", REG_MMIO, 0x4d3f, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4d40, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_STATUS", REG_MMIO, 0x4d41, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4d42, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4d43, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4d44, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4d45, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4d46, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_CNTL", REG_MMIO, 0x4d47, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_EN_CNTL", REG_MMIO, 0x4d48, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CNTL", REG_MMIO, 0x4d6b, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL_CHAR", REG_MMIO, 0x4d6c, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4d6d, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4d6e, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4d6f, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4d70, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DEBUG", REG_MMIO, 0x4d71, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL_BITS", REG_MMIO, 0x4d72, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4d73, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4d75, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4d76, NULL, 0, 0, 0 },
+	{ "mmDIG3_LVDS_DATA_CNTL", REG_MMIO, 0x4d78, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_LANE_ENABLE", REG_MMIO, 0x4d79, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4d7a, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4d7b, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4d7c, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4d7d, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_CNTL", REG_MMIO, 0x4da0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_PIXEL_FORMAT", REG_MMIO, 0x4da1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_COLORIMETRY", REG_MMIO, 0x4da2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_CONFIG", REG_MMIO, 0x4da3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_STREAM_CNTL", REG_MMIO, 0x4da4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_STEER_FIFO", REG_MMIO, 0x4da5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_MISC", REG_MMIO, 0x4da6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_TIMING", REG_MMIO, 0x4da8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_N", REG_MMIO, 0x4da9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_M", REG_MMIO, 0x4daa, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4dab, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4dac, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_MSA_VBID", REG_MMIO, 0x4dad, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4dae, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CNTL", REG_MMIO, 0x4daf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4db0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM0", REG_MMIO, 0x4db1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM1", REG_MMIO, 0x4db2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM2", REG_MMIO, 0x4db3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4db4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4db5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4db6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_EN", REG_MMIO, 0x4db7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4db8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4db9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4dba, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4dbb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4dbc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4dbd, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4dbe, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4dbf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL", REG_MMIO, 0x4dc3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL1", REG_MMIO, 0x4dc4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING1", REG_MMIO, 0x4dc5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING2", REG_MMIO, 0x4dc6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING3", REG_MMIO, 0x4dc7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING4", REG_MMIO, 0x4dc8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N", REG_MMIO, 0x4dc9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4dca, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M", REG_MMIO, 0x4dcb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4dcc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_TIMESTAMP", REG_MMIO, 0x4dcd, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4dce, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_CNTL", REG_MMIO, 0x4dcf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4dd1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT0", REG_MMIO, 0x4dd2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT1", REG_MMIO, 0x4dd3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT2", REG_MMIO, 0x4dd4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4dd5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_LINK_TIMING", REG_MMIO, 0x4dd6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_MISC_CNTL", REG_MMIO, 0x4dd7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4dd8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4dd9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4dda, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4ddb, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_CNTL", REG_MMIO, 0x4e00, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4e01, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4e02, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_CLOCK_PATTERN", REG_MMIO, 0x4e03, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_PATTERN", REG_MMIO, 0x4e04, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4e05, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FIFO_STATUS", REG_MMIO, 0x4e06, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4e07, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4e08, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_CONTROL", REG_MMIO, 0x4e09, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_STATUS", REG_MMIO, 0x4e0a, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4e0b, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4e0c, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4e0d, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4e0e, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4e0f, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4e10, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4e11, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GC", REG_MMIO, 0x4e13, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4e14, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_0", REG_MMIO, 0x4e15, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_1", REG_MMIO, 0x4e16, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_2", REG_MMIO, 0x4e17, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_3", REG_MMIO, 0x4e18, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_4", REG_MMIO, 0x4e19, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_0", REG_MMIO, 0x4e1a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_1", REG_MMIO, 0x4e1b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_2", REG_MMIO, 0x4e1c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_3", REG_MMIO, 0x4e1d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO0", REG_MMIO, 0x4e1e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO1", REG_MMIO, 0x4e1f, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO2", REG_MMIO, 0x4e20, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO3", REG_MMIO, 0x4e21, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO0", REG_MMIO, 0x4e22, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO1", REG_MMIO, 0x4e23, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_HDR", REG_MMIO, 0x4e24, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_0", REG_MMIO, 0x4e25, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_1", REG_MMIO, 0x4e26, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_2", REG_MMIO, 0x4e27, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_3", REG_MMIO, 0x4e28, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_4", REG_MMIO, 0x4e29, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_5", REG_MMIO, 0x4e2a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_6", REG_MMIO, 0x4e2b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_7", REG_MMIO, 0x4e2c, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4e2d, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_0", REG_MMIO, 0x4e2e, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_1", REG_MMIO, 0x4e2f, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_0", REG_MMIO, 0x4e30, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_1", REG_MMIO, 0x4e31, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_0", REG_MMIO, 0x4e32, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_1", REG_MMIO, 0x4e33, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_0", REG_MMIO, 0x4e34, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_1", REG_MMIO, 0x4e35, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO0", REG_MMIO, 0x4e36, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO1", REG_MMIO, 0x4e37, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_0", REG_MMIO, 0x4e38, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_1", REG_MMIO, 0x4e39, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4e3a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4e3b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4e3c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4e3d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4e3e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_2", REG_MMIO, 0x4e3f, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4e40, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_STATUS", REG_MMIO, 0x4e41, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4e42, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4e43, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4e44, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4e45, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4e46, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_CNTL", REG_MMIO, 0x4e47, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_EN_CNTL", REG_MMIO, 0x4e48, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CNTL", REG_MMIO, 0x4e6b, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL_CHAR", REG_MMIO, 0x4e6c, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4e6d, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4e6e, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4e6f, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4e70, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DEBUG", REG_MMIO, 0x4e71, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL_BITS", REG_MMIO, 0x4e72, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4e73, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4e75, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4e76, NULL, 0, 0, 0 },
+	{ "mmDIG4_LVDS_DATA_CNTL", REG_MMIO, 0x4e78, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_LANE_ENABLE", REG_MMIO, 0x4e79, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4e7a, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4e7b, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4e7c, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4e7d, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_CNTL", REG_MMIO, 0x4ea0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_PIXEL_FORMAT", REG_MMIO, 0x4ea1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ea2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_CONFIG", REG_MMIO, 0x4ea3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ea4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_STEER_FIFO", REG_MMIO, 0x4ea5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_MISC", REG_MMIO, 0x4ea6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_TIMING", REG_MMIO, 0x4ea8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_N", REG_MMIO, 0x4ea9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_M", REG_MMIO, 0x4eaa, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4eab, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4eac, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_MSA_VBID", REG_MMIO, 0x4ead, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4eae, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CNTL", REG_MMIO, 0x4eaf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4eb0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM0", REG_MMIO, 0x4eb1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM1", REG_MMIO, 0x4eb2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM2", REG_MMIO, 0x4eb3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4eb4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4eb5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4eb6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_EN", REG_MMIO, 0x4eb7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4eb8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4eb9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4eba, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4ebb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4ebc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4ebd, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4ebe, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4ebf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL", REG_MMIO, 0x4ec3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL1", REG_MMIO, 0x4ec4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING1", REG_MMIO, 0x4ec5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING2", REG_MMIO, 0x4ec6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING3", REG_MMIO, 0x4ec7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING4", REG_MMIO, 0x4ec8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N", REG_MMIO, 0x4ec9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4eca, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M", REG_MMIO, 0x4ecb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4ecc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_TIMESTAMP", REG_MMIO, 0x4ecd, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4ece, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_CNTL", REG_MMIO, 0x4ecf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4ed1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT0", REG_MMIO, 0x4ed2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT1", REG_MMIO, 0x4ed3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT2", REG_MMIO, 0x4ed4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4ed5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_LINK_TIMING", REG_MMIO, 0x4ed6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_MISC_CNTL", REG_MMIO, 0x4ed7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ed8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4ed9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4eda, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4edb, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_CNTL", REG_MMIO, 0x4f00, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4f01, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4f02, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_CLOCK_PATTERN", REG_MMIO, 0x4f03, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_PATTERN", REG_MMIO, 0x4f04, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4f05, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FIFO_STATUS", REG_MMIO, 0x4f06, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4f07, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4f08, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_CONTROL", REG_MMIO, 0x4f09, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_STATUS", REG_MMIO, 0x4f0a, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4f0b, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4f0c, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4f0d, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4f0e, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4f0f, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4f10, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4f11, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GC", REG_MMIO, 0x4f13, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4f14, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_0", REG_MMIO, 0x4f15, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_1", REG_MMIO, 0x4f16, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_2", REG_MMIO, 0x4f17, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_3", REG_MMIO, 0x4f18, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_4", REG_MMIO, 0x4f19, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_0", REG_MMIO, 0x4f1a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_1", REG_MMIO, 0x4f1b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_2", REG_MMIO, 0x4f1c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_3", REG_MMIO, 0x4f1d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO0", REG_MMIO, 0x4f1e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO1", REG_MMIO, 0x4f1f, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO2", REG_MMIO, 0x4f20, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO3", REG_MMIO, 0x4f21, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO0", REG_MMIO, 0x4f22, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO1", REG_MMIO, 0x4f23, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_HDR", REG_MMIO, 0x4f24, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_0", REG_MMIO, 0x4f25, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_1", REG_MMIO, 0x4f26, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_2", REG_MMIO, 0x4f27, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_3", REG_MMIO, 0x4f28, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_4", REG_MMIO, 0x4f29, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_5", REG_MMIO, 0x4f2a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_6", REG_MMIO, 0x4f2b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_7", REG_MMIO, 0x4f2c, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4f2d, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_0", REG_MMIO, 0x4f2e, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_1", REG_MMIO, 0x4f2f, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_0", REG_MMIO, 0x4f30, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_1", REG_MMIO, 0x4f31, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_0", REG_MMIO, 0x4f32, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_1", REG_MMIO, 0x4f33, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_0", REG_MMIO, 0x4f34, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_1", REG_MMIO, 0x4f35, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO0", REG_MMIO, 0x4f36, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO1", REG_MMIO, 0x4f37, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_0", REG_MMIO, 0x4f38, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_1", REG_MMIO, 0x4f39, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4f3a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4f3b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4f3c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4f3d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4f3e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_2", REG_MMIO, 0x4f3f, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4f40, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_STATUS", REG_MMIO, 0x4f41, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4f42, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4f43, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4f44, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4f45, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4f46, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_CNTL", REG_MMIO, 0x4f47, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_EN_CNTL", REG_MMIO, 0x4f48, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CNTL", REG_MMIO, 0x4f6b, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL_CHAR", REG_MMIO, 0x4f6c, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4f6d, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4f6e, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4f6f, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4f70, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DEBUG", REG_MMIO, 0x4f71, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL_BITS", REG_MMIO, 0x4f72, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4f73, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4f75, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4f76, NULL, 0, 0, 0 },
+	{ "mmDIG5_LVDS_DATA_CNTL", REG_MMIO, 0x4f78, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_LANE_ENABLE", REG_MMIO, 0x4f79, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4f7a, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4f7b, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4f7c, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4f7d, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_CNTL", REG_MMIO, 0x4fa0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_PIXEL_FORMAT", REG_MMIO, 0x4fa1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_COLORIMETRY", REG_MMIO, 0x4fa2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_CONFIG", REG_MMIO, 0x4fa3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_STREAM_CNTL", REG_MMIO, 0x4fa4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_STEER_FIFO", REG_MMIO, 0x4fa5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_MISC", REG_MMIO, 0x4fa6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_TIMING", REG_MMIO, 0x4fa8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_N", REG_MMIO, 0x4fa9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_M", REG_MMIO, 0x4faa, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4fab, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4fac, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_MSA_VBID", REG_MMIO, 0x4fad, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4fae, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CNTL", REG_MMIO, 0x4faf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4fb0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM0", REG_MMIO, 0x4fb1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM1", REG_MMIO, 0x4fb2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM2", REG_MMIO, 0x4fb3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4fb4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4fb5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4fb6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_EN", REG_MMIO, 0x4fb7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4fb8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4fb9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4fba, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4fbb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4fbc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4fbd, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4fbe, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4fbf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL", REG_MMIO, 0x4fc3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL1", REG_MMIO, 0x4fc4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING1", REG_MMIO, 0x4fc5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING2", REG_MMIO, 0x4fc6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING3", REG_MMIO, 0x4fc7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING4", REG_MMIO, 0x4fc8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N", REG_MMIO, 0x4fc9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4fca, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M", REG_MMIO, 0x4fcb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4fcc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_TIMESTAMP", REG_MMIO, 0x4fcd, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4fce, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_CNTL", REG_MMIO, 0x4fcf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4fd1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT0", REG_MMIO, 0x4fd2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT1", REG_MMIO, 0x4fd3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT2", REG_MMIO, 0x4fd4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4fd5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_LINK_TIMING", REG_MMIO, 0x4fd6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_MISC_CNTL", REG_MMIO, 0x4fd7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4fd8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4fd9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4fda, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4fdb, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x5, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x5, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL5", REG_SMC, 0x5, &ixAZALIA_INPUT_CRC0_CHANNEL5[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL5)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL5[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL5", REG_SMC, 0x5, &ixAZALIA_CRC0_CHANNEL5[0], sizeof(ixAZALIA_CRC0_CHANNEL5)/sizeof(ixAZALIA_CRC0_CHANNEL5[0]), 0, 0 },
+	{ "ixAZALIA_STREAM_DEBUG", REG_SMC, 0x5, &ixAZALIA_STREAM_DEBUG[0], sizeof(ixAZALIA_STREAM_DEBUG)/sizeof(ixAZALIA_STREAM_DEBUG[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR4", REG_SMC, 0x5, &ixAUDIO_DESCRIPTOR4[0], sizeof(ixAUDIO_DESCRIPTOR4)/sizeof(ixAUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "ixDCIO_DEBUG5", REG_SMC, 0x5, &ixDCIO_DEBUG5[0], sizeof(ixDCIO_DEBUG5)/sizeof(ixDCIO_DEBUG5[0]), 0, 0 },
+	{ "ixATTR05", REG_SMC, 0x5, &ixATTR05[0], sizeof(ixATTR05)/sizeof(ixATTR05[0]), 0, 0 },
+	{ "ixCRT05", REG_SMC, 0x5, &ixCRT05[0], sizeof(ixCRT05)/sizeof(ixCRT05[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x53, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x54, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x54, &ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 },
+	{ "mmDIG6_DIG_FE_CNTL", REG_MMIO, 0x5400, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x5401, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x5402, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_CLOCK_PATTERN", REG_MMIO, 0x5403, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_PATTERN", REG_MMIO, 0x5404, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x5405, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FIFO_STATUS", REG_MMIO, 0x5406, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x5407, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x5408, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_CONTROL", REG_MMIO, 0x5409, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_STATUS", REG_MMIO, 0x540a, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x540b, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x540c, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x540d, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x540e, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x540f, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x5410, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x5411, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GC", REG_MMIO, 0x5413, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x5414, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_0", REG_MMIO, 0x5415, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_1", REG_MMIO, 0x5416, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_2", REG_MMIO, 0x5417, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_3", REG_MMIO, 0x5418, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_4", REG_MMIO, 0x5419, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_0", REG_MMIO, 0x541a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_1", REG_MMIO, 0x541b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_2", REG_MMIO, 0x541c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_3", REG_MMIO, 0x541d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO0", REG_MMIO, 0x541e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO1", REG_MMIO, 0x541f, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO2", REG_MMIO, 0x5420, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO3", REG_MMIO, 0x5421, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_MPEG_INFO0", REG_MMIO, 0x5422, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_MPEG_INFO1", REG_MMIO, 0x5423, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_HDR", REG_MMIO, 0x5424, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_0", REG_MMIO, 0x5425, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_1", REG_MMIO, 0x5426, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_2", REG_MMIO, 0x5427, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_3", REG_MMIO, 0x5428, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_4", REG_MMIO, 0x5429, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_5", REG_MMIO, 0x542a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_6", REG_MMIO, 0x542b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_7", REG_MMIO, 0x542c, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x542d, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_32_0", REG_MMIO, 0x542e, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_32_1", REG_MMIO, 0x542f, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_44_0", REG_MMIO, 0x5430, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_44_1", REG_MMIO, 0x5431, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_48_0", REG_MMIO, 0x5432, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_48_1", REG_MMIO, 0x5433, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_STATUS_0", REG_MMIO, 0x5434, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_STATUS_1", REG_MMIO, 0x5435, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_INFO0", REG_MMIO, 0x5436, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_INFO1", REG_MMIO, 0x5437, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_0", REG_MMIO, 0x5438, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_1", REG_MMIO, 0x5439, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x543a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL0", REG_MMIO, 0x543b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL1", REG_MMIO, 0x543c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL2", REG_MMIO, 0x543d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL3", REG_MMIO, 0x543e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_2", REG_MMIO, 0x543f, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x5440, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_STATUS", REG_MMIO, 0x5441, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x5442, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x5443, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x5444, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x5445, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x5446, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_BE_CNTL", REG_MMIO, 0x5447, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_BE_EN_CNTL", REG_MMIO, 0x5448, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CNTL", REG_MMIO, 0x546b, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CONTROL_CHAR", REG_MMIO, 0x546c, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x546d, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x546e, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x546f, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x5470, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_DEBUG", REG_MMIO, 0x5471, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL_BITS", REG_MMIO, 0x5472, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x5473, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x5475, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x5476, NULL, 0, 0, 0 },
+	{ "mmDIG6_LVDS_DATA_CNTL", REG_MMIO, 0x5478, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_LANE_ENABLE", REG_MMIO, 0x5479, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x547a, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x547b, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x547c, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x547d, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_LINK_CNTL", REG_MMIO, 0x54a0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_PIXEL_FORMAT", REG_MMIO, 0x54a1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_COLORIMETRY", REG_MMIO, 0x54a2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_CONFIG", REG_MMIO, 0x54a3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_STREAM_CNTL", REG_MMIO, 0x54a4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_STEER_FIFO", REG_MMIO, 0x54a5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_MISC", REG_MMIO, 0x54a6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_TIMING", REG_MMIO, 0x54a8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_N", REG_MMIO, 0x54a9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_M", REG_MMIO, 0x54aa, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x54ab, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x54ac, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_MSA_VBID", REG_MMIO, 0x54ad, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x54ae, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CNTL", REG_MMIO, 0x54af, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x54b0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM0", REG_MMIO, 0x54b1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM1", REG_MMIO, 0x54b2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM2", REG_MMIO, 0x54b3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x54b4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x54b5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x54b6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_EN", REG_MMIO, 0x54b7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_CNTL", REG_MMIO, 0x54b8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_RESULT", REG_MMIO, 0x54b9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x54ba, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x54bb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x54bc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x54bd, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x54be, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x54bf, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_CNTL", REG_MMIO, 0x54c3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_CNTL1", REG_MMIO, 0x54c4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING1", REG_MMIO, 0x54c5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING2", REG_MMIO, 0x54c6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING3", REG_MMIO, 0x54c7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING4", REG_MMIO, 0x54c8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_N", REG_MMIO, 0x54c9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x54ca, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_M", REG_MMIO, 0x54cb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x54cc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_TIMESTAMP", REG_MMIO, 0x54cd, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_PACKET_CNTL", REG_MMIO, 0x54ce, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_RATE_CNTL", REG_MMIO, 0x54cf, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_RATE_UPDATE", REG_MMIO, 0x54d1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT0", REG_MMIO, 0x54d2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT1", REG_MMIO, 0x54d3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT2", REG_MMIO, 0x54d4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT_UPDATE", REG_MMIO, 0x54d5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_LINK_TIMING", REG_MMIO, 0x54d6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_MISC_CNTL", REG_MMIO, 0x54d7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x54d8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_TEST_DEBUG_DATA", REG_MMIO, 0x54d9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x54da, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x54db, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x55, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x55, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x56, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x56, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x57, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x58, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x59, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "mmDC_PERFMON10_PERFCOUNTER_CNTL", REG_MMIO, 0x59a0, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFCOUNTER_STATE", REG_MMIO, 0x59a1, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x59a2, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CNTL", REG_MMIO, 0x59a3, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CVALUE_LOW", REG_MMIO, 0x59a4, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_HI", REG_MMIO, 0x59a5, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_LOW", REG_MMIO, 0x59a6, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x59a7, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x59a8, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CNTL2", REG_MMIO, 0x59aa, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM8_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c0, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM8_AZALIA_STREAM_DATA", REG_MMIO, 0x59c1, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM9_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c2, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM9_AZALIA_STREAM_DATA", REG_MMIO, 0x59c3, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM10_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c4, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM10_AZALIA_STREAM_DATA", REG_MMIO, 0x59c5, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM11_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c6, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM11_AZALIA_STREAM_DATA", REG_MMIO, 0x59c7, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM12_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c8, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM12_AZALIA_STREAM_DATA", REG_MMIO, 0x59c9, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM13_AZALIA_STREAM_INDEX", REG_MMIO, 0x59ca, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM13_AZALIA_STREAM_DATA", REG_MMIO, 0x59cb, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM14_AZALIA_STREAM_INDEX", REG_MMIO, 0x59cc, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM14_AZALIA_STREAM_DATA", REG_MMIO, 0x59cd, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM15_AZALIA_STREAM_INDEX", REG_MMIO, 0x59ce, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM15_AZALIA_STREAM_DATA", REG_MMIO, 0x59cf, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d4, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d4, &mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 },
+	{ "mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d5, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d5, &mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 },
+	{ "mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d8, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d9, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59dc, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59dd, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e0, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e1, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e4, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e5, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e8, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e9, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59ec, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59ed, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59f0, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59f1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x5a, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5a84, &mmDCRX_PHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED0)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5a85, &mmDCRX_PHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED1)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5a86, &mmDCRX_PHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED2)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5a87, &mmDCRX_PHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED3)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5a88, &mmDCRX_PHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED4)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5a89, &mmDCRX_PHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED5)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5a8a, &mmDCRX_PHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED6)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5a8b, &mmDCRX_PHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED7)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5a8c, &mmDCRX_PHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED8)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5a8d, &mmDCRX_PHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED9)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5a8e, &mmDCRX_PHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED10)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5a8f, &mmDCRX_PHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED11)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x5a90, &mmDCRX_PHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED12)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x5a91, &mmDCRX_PHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED13)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x5a92, &mmDCRX_PHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED14)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x5a93, &mmDCRX_PHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED15)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x5a94, &mmDCRX_PHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED16)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x5a95, &mmDCRX_PHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED17)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x5a96, &mmDCRX_PHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED18)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x5a97, &mmDCRX_PHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED19)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x5a98, &mmDCRX_PHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED20)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x5a99, &mmDCRX_PHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED21)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x5a9a, &mmDCRX_PHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED22)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x5a9b, &mmDCRX_PHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED23)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x5a9c, &mmDCRX_PHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED24)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x5a9d, &mmDCRX_PHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED25)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x5a9e, &mmDCRX_PHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED26)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x5a9f, &mmDCRX_PHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED27)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x5aa0, &mmDCRX_PHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED28)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x5aa1, &mmDCRX_PHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED29)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x5aa2, &mmDCRX_PHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED30)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x5aa3, &mmDCRX_PHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED31)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x5aa4, &mmDCRX_PHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED32)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x5aa5, &mmDCRX_PHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED33)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x5aa6, &mmDCRX_PHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED34)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x5aa7, &mmDCRX_PHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED35)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x5aa8, &mmDCRX_PHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED36)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x5aa9, &mmDCRX_PHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED37)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x5aaa, &mmDCRX_PHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED38)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x5aab, &mmDCRX_PHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED39)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x5aac, &mmDCRX_PHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED40)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x5aad, &mmDCRX_PHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED41)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x5aae, &mmDCRX_PHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED42)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED42[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x5aaf, &mmDCRX_PHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED43)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED43[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x5ab0, &mmDCRX_PHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED44)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED44[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x5ab1, &mmDCRX_PHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED45)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED45[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x5ab2, &mmDCRX_PHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED46)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED46[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x5ab3, &mmDCRX_PHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED47)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED47[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x5ab4, &mmDCRX_PHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED48)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED48[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x5ab5, &mmDCRX_PHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED49)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED49[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x5ab6, &mmDCRX_PHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED50)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED50[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x5ab7, &mmDCRX_PHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED51)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED51[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x5ab8, &mmDCRX_PHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED52)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED52[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x5ab9, &mmDCRX_PHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED53)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED53[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x5aba, &mmDCRX_PHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED54)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED54[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x5abb, &mmDCRX_PHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED55)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED55[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x5abc, &mmDCRX_PHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED56)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED56[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x5abd, &mmDCRX_PHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED57)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED57[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x5abe, &mmDCRX_PHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED58)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED58[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x5abf, &mmDCRX_PHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED59)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED59[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x5ac0, &mmDCRX_PHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED60)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED60[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x5ac1, &mmDCRX_PHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED61)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED61[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x5ac2, &mmDCRX_PHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED62)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED62[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x5ac3, &mmDCRX_PHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED63)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED63[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x5ac4, &mmDCRX_PHY_MACRO_CNTL_RESERVED64[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED64)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED64[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x5ac5, &mmDCRX_PHY_MACRO_CNTL_RESERVED65[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED65)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED65[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x5ac6, &mmDCRX_PHY_MACRO_CNTL_RESERVED66[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED66)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED66[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x5ac7, &mmDCRX_PHY_MACRO_CNTL_RESERVED67[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED67)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED67[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x5ac8, &mmDCRX_PHY_MACRO_CNTL_RESERVED68[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED68)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED68[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x5ac9, &mmDCRX_PHY_MACRO_CNTL_RESERVED69[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED69)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED69[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x5aca, &mmDCRX_PHY_MACRO_CNTL_RESERVED70[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED70)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED70[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x5acb, &mmDCRX_PHY_MACRO_CNTL_RESERVED71[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED71)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED71[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x5acc, &mmDCRX_PHY_MACRO_CNTL_RESERVED72[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED72)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED72[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x5acd, &mmDCRX_PHY_MACRO_CNTL_RESERVED73[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED73)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED73[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x5ace, &mmDCRX_PHY_MACRO_CNTL_RESERVED74[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED74)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED74[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x5acf, &mmDCRX_PHY_MACRO_CNTL_RESERVED75[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED75)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED75[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x5ad0, &mmDCRX_PHY_MACRO_CNTL_RESERVED76[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED76)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED76[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x5ad1, &mmDCRX_PHY_MACRO_CNTL_RESERVED77[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED77)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED77[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x5ad2, &mmDCRX_PHY_MACRO_CNTL_RESERVED78[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED78)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED78[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x5ad3, &mmDCRX_PHY_MACRO_CNTL_RESERVED79[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED79)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED79[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x5ad4, &mmDCRX_PHY_MACRO_CNTL_RESERVED80[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED80)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED80[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x5ad5, &mmDCRX_PHY_MACRO_CNTL_RESERVED81[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED81)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED81[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x5ad6, &mmDCRX_PHY_MACRO_CNTL_RESERVED82[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED82)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED82[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x5ad7, &mmDCRX_PHY_MACRO_CNTL_RESERVED83[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED83)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED83[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x5ad8, &mmDCRX_PHY_MACRO_CNTL_RESERVED84[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED84)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED84[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x5ad9, &mmDCRX_PHY_MACRO_CNTL_RESERVED85[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED85)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED85[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x5ada, &mmDCRX_PHY_MACRO_CNTL_RESERVED86[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED86)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED86[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x5adb, &mmDCRX_PHY_MACRO_CNTL_RESERVED87[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED87)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED87[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x5adc, &mmDCRX_PHY_MACRO_CNTL_RESERVED88[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED88)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED88[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x5add, &mmDCRX_PHY_MACRO_CNTL_RESERVED89[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED89)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED89[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x5ade, &mmDCRX_PHY_MACRO_CNTL_RESERVED90[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED90)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED90[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x5adf, &mmDCRX_PHY_MACRO_CNTL_RESERVED91[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED91)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED91[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x5ae0, &mmDCRX_PHY_MACRO_CNTL_RESERVED92[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED92)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED92[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x5ae1, &mmDCRX_PHY_MACRO_CNTL_RESERVED93[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED93)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED93[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x5ae2, &mmDCRX_PHY_MACRO_CNTL_RESERVED94[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED94)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED94[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x5ae3, &mmDCRX_PHY_MACRO_CNTL_RESERVED95[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED95)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED95[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x5ae4, &mmDCRX_PHY_MACRO_CNTL_RESERVED96[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED96)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED96[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x5ae5, &mmDCRX_PHY_MACRO_CNTL_RESERVED97[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED97)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED97[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x5ae6, &mmDCRX_PHY_MACRO_CNTL_RESERVED98[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED98)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED98[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x5ae7, &mmDCRX_PHY_MACRO_CNTL_RESERVED99[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED99)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED99[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x5ae8, &mmDCRX_PHY_MACRO_CNTL_RESERVED100[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED100)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED100[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x5ae9, &mmDCRX_PHY_MACRO_CNTL_RESERVED101[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED101)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED101[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x5aea, &mmDCRX_PHY_MACRO_CNTL_RESERVED102[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED102)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED102[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x5aeb, &mmDCRX_PHY_MACRO_CNTL_RESERVED103[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED103)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED103[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x5aec, &mmDCRX_PHY_MACRO_CNTL_RESERVED104[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED104)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED104[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x5aed, &mmDCRX_PHY_MACRO_CNTL_RESERVED105[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED105)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED105[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x5aee, &mmDCRX_PHY_MACRO_CNTL_RESERVED106[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED106)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED106[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x5aef, &mmDCRX_PHY_MACRO_CNTL_RESERVED107[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED107)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED107[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x5af0, &mmDCRX_PHY_MACRO_CNTL_RESERVED108[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED108)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED108[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x5af1, &mmDCRX_PHY_MACRO_CNTL_RESERVED109[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED109)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED109[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x5af2, &mmDCRX_PHY_MACRO_CNTL_RESERVED110[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED110)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED110[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x5af3, &mmDCRX_PHY_MACRO_CNTL_RESERVED111[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED111)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED111[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x5af4, &mmDCRX_PHY_MACRO_CNTL_RESERVED112[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED112)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED112[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x5af5, &mmDCRX_PHY_MACRO_CNTL_RESERVED113[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED113)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED113[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x5af6, &mmDCRX_PHY_MACRO_CNTL_RESERVED114[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED114)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED114[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x5af7, &mmDCRX_PHY_MACRO_CNTL_RESERVED115[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED115)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED115[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x5af8, &mmDCRX_PHY_MACRO_CNTL_RESERVED116[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED116)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED116[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x5af9, &mmDCRX_PHY_MACRO_CNTL_RESERVED117[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED117)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED117[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x5afa, &mmDCRX_PHY_MACRO_CNTL_RESERVED118[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED118)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED118[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x5afb, &mmDCRX_PHY_MACRO_CNTL_RESERVED119[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED119)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED119[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x5afc, &mmDCRX_PHY_MACRO_CNTL_RESERVED120[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED120)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED120[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x5afd, &mmDCRX_PHY_MACRO_CNTL_RESERVED121[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED121)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED121[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x5afe, &mmDCRX_PHY_MACRO_CNTL_RESERVED122[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED122)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED122[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x5aff, &mmDCRX_PHY_MACRO_CNTL_RESERVED123[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED123)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED123[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x5b, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x5b00, &mmDCRX_PHY_MACRO_CNTL_RESERVED124[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED124)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED124[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x5b01, &mmDCRX_PHY_MACRO_CNTL_RESERVED125[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED125)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED125[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x5b02, &mmDCRX_PHY_MACRO_CNTL_RESERVED126[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED126)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED126[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x5b03, &mmDCRX_PHY_MACRO_CNTL_RESERVED127[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED127)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED127[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x5b04, &mmDCRX_PHY_MACRO_CNTL_RESERVED128[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED128)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED128[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x5b05, &mmDCRX_PHY_MACRO_CNTL_RESERVED129[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED129)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED129[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x5b06, &mmDCRX_PHY_MACRO_CNTL_RESERVED130[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED130)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED130[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x5b07, &mmDCRX_PHY_MACRO_CNTL_RESERVED131[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED131)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED131[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x5b08, &mmDCRX_PHY_MACRO_CNTL_RESERVED132[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED132)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED132[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x5b09, &mmDCRX_PHY_MACRO_CNTL_RESERVED133[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED133)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED133[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x5b0a, &mmDCRX_PHY_MACRO_CNTL_RESERVED134[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED134)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED134[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x5b0b, &mmDCRX_PHY_MACRO_CNTL_RESERVED135[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED135)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED135[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x5b0c, &mmDCRX_PHY_MACRO_CNTL_RESERVED136[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED136)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED136[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x5b0d, &mmDCRX_PHY_MACRO_CNTL_RESERVED137[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED137)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED137[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x5b0e, &mmDCRX_PHY_MACRO_CNTL_RESERVED138[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED138)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED138[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x5b0f, &mmDCRX_PHY_MACRO_CNTL_RESERVED139[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED139)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED139[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x5b10, &mmDCRX_PHY_MACRO_CNTL_RESERVED140[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED140)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED140[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x5b11, &mmDCRX_PHY_MACRO_CNTL_RESERVED141[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED141)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED141[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x5b12, &mmDCRX_PHY_MACRO_CNTL_RESERVED142[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED142)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED142[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x5b13, &mmDCRX_PHY_MACRO_CNTL_RESERVED143[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED143)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED143[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x5b14, &mmDCRX_PHY_MACRO_CNTL_RESERVED144[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED144)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED144[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x5b15, &mmDCRX_PHY_MACRO_CNTL_RESERVED145[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED145)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED145[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x5b16, &mmDCRX_PHY_MACRO_CNTL_RESERVED146[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED146)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED146[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x5b17, &mmDCRX_PHY_MACRO_CNTL_RESERVED147[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED147)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED147[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x5b18, &mmDCRX_PHY_MACRO_CNTL_RESERVED148[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED148)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED148[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x5b19, &mmDCRX_PHY_MACRO_CNTL_RESERVED149[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED149)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED149[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x5b1a, &mmDCRX_PHY_MACRO_CNTL_RESERVED150[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED150)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED150[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x5b1b, &mmDCRX_PHY_MACRO_CNTL_RESERVED151[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED151)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED151[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x5b1c, &mmDCRX_PHY_MACRO_CNTL_RESERVED152[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED152)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED152[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x5b1d, &mmDCRX_PHY_MACRO_CNTL_RESERVED153[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED153)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED153[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x5b1e, &mmDCRX_PHY_MACRO_CNTL_RESERVED154[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED154)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED154[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x5b1f, &mmDCRX_PHY_MACRO_CNTL_RESERVED155[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED155)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED155[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x5b20, &mmDCRX_PHY_MACRO_CNTL_RESERVED156[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED156)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED156[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x5b21, &mmDCRX_PHY_MACRO_CNTL_RESERVED157[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED157)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED157[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x5b22, &mmDCRX_PHY_MACRO_CNTL_RESERVED158[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED158)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED158[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x5b23, &mmDCRX_PHY_MACRO_CNTL_RESERVED159[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED159)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED159[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED160", REG_MMIO, 0x5b24, &mmDCRX_PHY_MACRO_CNTL_RESERVED160[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED160)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED160[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED161", REG_MMIO, 0x5b25, &mmDCRX_PHY_MACRO_CNTL_RESERVED161[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED161)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED161[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED162", REG_MMIO, 0x5b26, &mmDCRX_PHY_MACRO_CNTL_RESERVED162[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED162)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED162[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED163", REG_MMIO, 0x5b27, &mmDCRX_PHY_MACRO_CNTL_RESERVED163[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED163)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED163[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED164", REG_MMIO, 0x5b28, &mmDCRX_PHY_MACRO_CNTL_RESERVED164[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED164)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED164[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED165", REG_MMIO, 0x5b29, &mmDCRX_PHY_MACRO_CNTL_RESERVED165[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED165)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED165[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED166", REG_MMIO, 0x5b2a, &mmDCRX_PHY_MACRO_CNTL_RESERVED166[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED166)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED166[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED167", REG_MMIO, 0x5b2b, &mmDCRX_PHY_MACRO_CNTL_RESERVED167[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED167)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED167[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED168", REG_MMIO, 0x5b2c, &mmDCRX_PHY_MACRO_CNTL_RESERVED168[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED168)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED168[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED169", REG_MMIO, 0x5b2d, &mmDCRX_PHY_MACRO_CNTL_RESERVED169[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED169)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED169[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED170", REG_MMIO, 0x5b2e, &mmDCRX_PHY_MACRO_CNTL_RESERVED170[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED170)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED170[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED171", REG_MMIO, 0x5b2f, &mmDCRX_PHY_MACRO_CNTL_RESERVED171[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED171)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED171[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED172", REG_MMIO, 0x5b30, &mmDCRX_PHY_MACRO_CNTL_RESERVED172[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED172)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED172[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED173", REG_MMIO, 0x5b31, &mmDCRX_PHY_MACRO_CNTL_RESERVED173[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED173)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED173[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED174", REG_MMIO, 0x5b32, &mmDCRX_PHY_MACRO_CNTL_RESERVED174[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED174)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED174[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED175", REG_MMIO, 0x5b33, &mmDCRX_PHY_MACRO_CNTL_RESERVED175[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED175)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED175[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED176", REG_MMIO, 0x5b34, &mmDCRX_PHY_MACRO_CNTL_RESERVED176[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED176)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED176[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED177", REG_MMIO, 0x5b35, &mmDCRX_PHY_MACRO_CNTL_RESERVED177[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED177)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED177[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED178", REG_MMIO, 0x5b36, &mmDCRX_PHY_MACRO_CNTL_RESERVED178[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED178)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED178[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED179", REG_MMIO, 0x5b37, &mmDCRX_PHY_MACRO_CNTL_RESERVED179[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED179)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED179[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED180", REG_MMIO, 0x5b38, &mmDCRX_PHY_MACRO_CNTL_RESERVED180[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED180)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED180[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED181", REG_MMIO, 0x5b39, &mmDCRX_PHY_MACRO_CNTL_RESERVED181[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED181)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED181[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED182", REG_MMIO, 0x5b3a, &mmDCRX_PHY_MACRO_CNTL_RESERVED182[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED182)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED182[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED183", REG_MMIO, 0x5b3b, &mmDCRX_PHY_MACRO_CNTL_RESERVED183[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED183)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED183[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED184", REG_MMIO, 0x5b3c, &mmDCRX_PHY_MACRO_CNTL_RESERVED184[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED184)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED184[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED185", REG_MMIO, 0x5b3d, &mmDCRX_PHY_MACRO_CNTL_RESERVED185[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED185)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED185[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED186", REG_MMIO, 0x5b3e, &mmDCRX_PHY_MACRO_CNTL_RESERVED186[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED186)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED186[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED187", REG_MMIO, 0x5b3f, &mmDCRX_PHY_MACRO_CNTL_RESERVED187[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED187)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED187[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED188", REG_MMIO, 0x5b40, &mmDCRX_PHY_MACRO_CNTL_RESERVED188[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED188)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED188[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED189", REG_MMIO, 0x5b41, &mmDCRX_PHY_MACRO_CNTL_RESERVED189[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED189)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED189[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED190", REG_MMIO, 0x5b42, &mmDCRX_PHY_MACRO_CNTL_RESERVED190[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED190)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED190[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED191", REG_MMIO, 0x5b43, &mmDCRX_PHY_MACRO_CNTL_RESERVED191[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED191)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED191[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED192", REG_MMIO, 0x5b44, &mmDCRX_PHY_MACRO_CNTL_RESERVED192[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED192)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED192[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED193", REG_MMIO, 0x5b45, &mmDCRX_PHY_MACRO_CNTL_RESERVED193[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED193)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED193[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED194", REG_MMIO, 0x5b46, &mmDCRX_PHY_MACRO_CNTL_RESERVED194[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED194)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED194[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED195", REG_MMIO, 0x5b47, &mmDCRX_PHY_MACRO_CNTL_RESERVED195[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED195)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED195[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED196", REG_MMIO, 0x5b48, &mmDCRX_PHY_MACRO_CNTL_RESERVED196[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED196)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED196[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED197", REG_MMIO, 0x5b49, &mmDCRX_PHY_MACRO_CNTL_RESERVED197[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED197)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED197[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED198", REG_MMIO, 0x5b4a, &mmDCRX_PHY_MACRO_CNTL_RESERVED198[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED198)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED198[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED199", REG_MMIO, 0x5b4b, &mmDCRX_PHY_MACRO_CNTL_RESERVED199[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED199)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED199[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED200", REG_MMIO, 0x5b4c, &mmDCRX_PHY_MACRO_CNTL_RESERVED200[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED200)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED200[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED201", REG_MMIO, 0x5b4d, &mmDCRX_PHY_MACRO_CNTL_RESERVED201[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED201)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED201[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED202", REG_MMIO, 0x5b4e, &mmDCRX_PHY_MACRO_CNTL_RESERVED202[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED202)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED202[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED203", REG_MMIO, 0x5b4f, &mmDCRX_PHY_MACRO_CNTL_RESERVED203[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED203)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED203[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED204", REG_MMIO, 0x5b50, &mmDCRX_PHY_MACRO_CNTL_RESERVED204[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED204)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED204[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED205", REG_MMIO, 0x5b51, &mmDCRX_PHY_MACRO_CNTL_RESERVED205[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED205)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED205[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED206", REG_MMIO, 0x5b52, &mmDCRX_PHY_MACRO_CNTL_RESERVED206[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED206)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED206[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED207", REG_MMIO, 0x5b53, &mmDCRX_PHY_MACRO_CNTL_RESERVED207[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED207)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED207[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED208", REG_MMIO, 0x5b54, &mmDCRX_PHY_MACRO_CNTL_RESERVED208[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED208)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED208[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED209", REG_MMIO, 0x5b55, &mmDCRX_PHY_MACRO_CNTL_RESERVED209[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED209)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED209[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED210", REG_MMIO, 0x5b56, &mmDCRX_PHY_MACRO_CNTL_RESERVED210[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED210)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED210[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED211", REG_MMIO, 0x5b57, &mmDCRX_PHY_MACRO_CNTL_RESERVED211[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED211)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED211[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED212", REG_MMIO, 0x5b58, &mmDCRX_PHY_MACRO_CNTL_RESERVED212[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED212)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED212[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED213", REG_MMIO, 0x5b59, &mmDCRX_PHY_MACRO_CNTL_RESERVED213[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED213)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED213[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED214", REG_MMIO, 0x5b5a, &mmDCRX_PHY_MACRO_CNTL_RESERVED214[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED214)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED214[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED215", REG_MMIO, 0x5b5b, &mmDCRX_PHY_MACRO_CNTL_RESERVED215[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED215)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED215[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED216", REG_MMIO, 0x5b5c, &mmDCRX_PHY_MACRO_CNTL_RESERVED216[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED216)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED216[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED217", REG_MMIO, 0x5b5d, &mmDCRX_PHY_MACRO_CNTL_RESERVED217[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED217)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED217[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED218", REG_MMIO, 0x5b5e, &mmDCRX_PHY_MACRO_CNTL_RESERVED218[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED218)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED218[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED219", REG_MMIO, 0x5b5f, &mmDCRX_PHY_MACRO_CNTL_RESERVED219[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED219)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED219[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED220", REG_MMIO, 0x5b60, &mmDCRX_PHY_MACRO_CNTL_RESERVED220[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED220)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED220[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED221", REG_MMIO, 0x5b61, &mmDCRX_PHY_MACRO_CNTL_RESERVED221[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED221)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED221[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED222", REG_MMIO, 0x5b62, &mmDCRX_PHY_MACRO_CNTL_RESERVED222[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED222)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED222[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED223", REG_MMIO, 0x5b63, &mmDCRX_PHY_MACRO_CNTL_RESERVED223[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED223)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED223[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED224", REG_MMIO, 0x5b64, &mmDCRX_PHY_MACRO_CNTL_RESERVED224[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED224)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED224[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED225", REG_MMIO, 0x5b65, &mmDCRX_PHY_MACRO_CNTL_RESERVED225[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED225)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED225[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED226", REG_MMIO, 0x5b66, &mmDCRX_PHY_MACRO_CNTL_RESERVED226[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED226)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED226[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED227", REG_MMIO, 0x5b67, &mmDCRX_PHY_MACRO_CNTL_RESERVED227[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED227)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED227[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED228", REG_MMIO, 0x5b68, &mmDCRX_PHY_MACRO_CNTL_RESERVED228[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED228)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED228[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED229", REG_MMIO, 0x5b69, &mmDCRX_PHY_MACRO_CNTL_RESERVED229[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED229)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED229[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED230", REG_MMIO, 0x5b6a, &mmDCRX_PHY_MACRO_CNTL_RESERVED230[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED230)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED230[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED231", REG_MMIO, 0x5b6b, &mmDCRX_PHY_MACRO_CNTL_RESERVED231[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED231)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED231[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED232", REG_MMIO, 0x5b6c, &mmDCRX_PHY_MACRO_CNTL_RESERVED232[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED232)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED232[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED233", REG_MMIO, 0x5b6d, &mmDCRX_PHY_MACRO_CNTL_RESERVED233[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED233)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED233[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED234", REG_MMIO, 0x5b6e, &mmDCRX_PHY_MACRO_CNTL_RESERVED234[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED234)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED234[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED235", REG_MMIO, 0x5b6f, &mmDCRX_PHY_MACRO_CNTL_RESERVED235[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED235)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED235[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED236", REG_MMIO, 0x5b70, &mmDCRX_PHY_MACRO_CNTL_RESERVED236[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED236)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED236[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED237", REG_MMIO, 0x5b71, &mmDCRX_PHY_MACRO_CNTL_RESERVED237[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED237)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED237[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED238", REG_MMIO, 0x5b72, &mmDCRX_PHY_MACRO_CNTL_RESERVED238[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED238)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED238[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED239", REG_MMIO, 0x5b73, &mmDCRX_PHY_MACRO_CNTL_RESERVED239[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED239)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED239[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED240", REG_MMIO, 0x5b74, &mmDCRX_PHY_MACRO_CNTL_RESERVED240[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED240)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED240[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED241", REG_MMIO, 0x5b75, &mmDCRX_PHY_MACRO_CNTL_RESERVED241[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED241)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED241[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED242", REG_MMIO, 0x5b76, &mmDCRX_PHY_MACRO_CNTL_RESERVED242[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED242)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED242[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED243", REG_MMIO, 0x5b77, &mmDCRX_PHY_MACRO_CNTL_RESERVED243[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED243)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED243[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED244", REG_MMIO, 0x5b78, &mmDCRX_PHY_MACRO_CNTL_RESERVED244[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED244)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED244[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED245", REG_MMIO, 0x5b79, &mmDCRX_PHY_MACRO_CNTL_RESERVED245[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED245)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED245[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED246", REG_MMIO, 0x5b7a, &mmDCRX_PHY_MACRO_CNTL_RESERVED246[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED246)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED246[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED247", REG_MMIO, 0x5b7b, &mmDCRX_PHY_MACRO_CNTL_RESERVED247[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED247)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED247[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED248", REG_MMIO, 0x5b7c, &mmDCRX_PHY_MACRO_CNTL_RESERVED248[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED248)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED248[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED249", REG_MMIO, 0x5b7d, &mmDCRX_PHY_MACRO_CNTL_RESERVED249[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED249)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED249[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED250", REG_MMIO, 0x5b7e, &mmDCRX_PHY_MACRO_CNTL_RESERVED250[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED250)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED250[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED251", REG_MMIO, 0x5b7f, &mmDCRX_PHY_MACRO_CNTL_RESERVED251[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED251)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED251[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED252", REG_MMIO, 0x5b80, &mmDCRX_PHY_MACRO_CNTL_RESERVED252[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED252)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED252[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED253", REG_MMIO, 0x5b81, &mmDCRX_PHY_MACRO_CNTL_RESERVED253[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED253)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED253[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED254", REG_MMIO, 0x5b82, &mmDCRX_PHY_MACRO_CNTL_RESERVED254[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED254)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED254[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED255", REG_MMIO, 0x5b83, &mmDCRX_PHY_MACRO_CNTL_RESERVED255[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED255)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED255[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED256", REG_MMIO, 0x5b84, &mmDCRX_PHY_MACRO_CNTL_RESERVED256[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED256)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED256[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED257", REG_MMIO, 0x5b85, &mmDCRX_PHY_MACRO_CNTL_RESERVED257[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED257)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED257[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED258", REG_MMIO, 0x5b86, &mmDCRX_PHY_MACRO_CNTL_RESERVED258[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED258)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED258[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED259", REG_MMIO, 0x5b87, &mmDCRX_PHY_MACRO_CNTL_RESERVED259[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED259)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED259[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED260", REG_MMIO, 0x5b88, &mmDCRX_PHY_MACRO_CNTL_RESERVED260[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED260)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED260[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED261", REG_MMIO, 0x5b89, &mmDCRX_PHY_MACRO_CNTL_RESERVED261[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED261)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED261[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED262", REG_MMIO, 0x5b8a, &mmDCRX_PHY_MACRO_CNTL_RESERVED262[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED262)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED262[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED263", REG_MMIO, 0x5b8b, &mmDCRX_PHY_MACRO_CNTL_RESERVED263[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED263)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED263[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED264", REG_MMIO, 0x5b8c, &mmDCRX_PHY_MACRO_CNTL_RESERVED264[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED264)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED264[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED265", REG_MMIO, 0x5b8d, &mmDCRX_PHY_MACRO_CNTL_RESERVED265[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED265)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED265[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED266", REG_MMIO, 0x5b8e, &mmDCRX_PHY_MACRO_CNTL_RESERVED266[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED266)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED266[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED267", REG_MMIO, 0x5b8f, &mmDCRX_PHY_MACRO_CNTL_RESERVED267[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED267)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED267[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED268", REG_MMIO, 0x5b90, &mmDCRX_PHY_MACRO_CNTL_RESERVED268[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED268)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED268[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED269", REG_MMIO, 0x5b91, &mmDCRX_PHY_MACRO_CNTL_RESERVED269[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED269)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED269[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED270", REG_MMIO, 0x5b92, &mmDCRX_PHY_MACRO_CNTL_RESERVED270[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED270)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED270[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED271", REG_MMIO, 0x5b93, &mmDCRX_PHY_MACRO_CNTL_RESERVED271[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED271)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED271[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED272", REG_MMIO, 0x5b94, &mmDCRX_PHY_MACRO_CNTL_RESERVED272[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED272)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED272[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED273", REG_MMIO, 0x5b95, &mmDCRX_PHY_MACRO_CNTL_RESERVED273[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED273)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED273[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED274", REG_MMIO, 0x5b96, &mmDCRX_PHY_MACRO_CNTL_RESERVED274[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED274)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED274[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED275", REG_MMIO, 0x5b97, &mmDCRX_PHY_MACRO_CNTL_RESERVED275[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED275)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED275[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED276", REG_MMIO, 0x5b98, &mmDCRX_PHY_MACRO_CNTL_RESERVED276[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED276)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED276[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED277", REG_MMIO, 0x5b99, &mmDCRX_PHY_MACRO_CNTL_RESERVED277[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED277)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED277[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED278", REG_MMIO, 0x5b9a, &mmDCRX_PHY_MACRO_CNTL_RESERVED278[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED278)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED278[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED279", REG_MMIO, 0x5b9b, &mmDCRX_PHY_MACRO_CNTL_RESERVED279[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED279)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED279[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED280", REG_MMIO, 0x5b9c, &mmDCRX_PHY_MACRO_CNTL_RESERVED280[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED280)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED280[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED281", REG_MMIO, 0x5b9d, &mmDCRX_PHY_MACRO_CNTL_RESERVED281[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED281)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED281[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED282", REG_MMIO, 0x5b9e, &mmDCRX_PHY_MACRO_CNTL_RESERVED282[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED282)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED282[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED283", REG_MMIO, 0x5b9f, &mmDCRX_PHY_MACRO_CNTL_RESERVED283[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED283)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED283[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED284", REG_MMIO, 0x5ba0, &mmDCRX_PHY_MACRO_CNTL_RESERVED284[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED284)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED284[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED285", REG_MMIO, 0x5ba1, &mmDCRX_PHY_MACRO_CNTL_RESERVED285[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED285)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED285[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED286", REG_MMIO, 0x5ba2, &mmDCRX_PHY_MACRO_CNTL_RESERVED286[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED286)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED286[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED287", REG_MMIO, 0x5ba3, &mmDCRX_PHY_MACRO_CNTL_RESERVED287[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED287)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED287[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED288", REG_MMIO, 0x5ba4, &mmDCRX_PHY_MACRO_CNTL_RESERVED288[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED288)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED288[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED289", REG_MMIO, 0x5ba5, &mmDCRX_PHY_MACRO_CNTL_RESERVED289[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED289)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED289[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED290", REG_MMIO, 0x5ba6, &mmDCRX_PHY_MACRO_CNTL_RESERVED290[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED290)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED290[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED291", REG_MMIO, 0x5ba7, &mmDCRX_PHY_MACRO_CNTL_RESERVED291[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED291)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED291[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED292", REG_MMIO, 0x5ba8, &mmDCRX_PHY_MACRO_CNTL_RESERVED292[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED292)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED292[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED293", REG_MMIO, 0x5ba9, &mmDCRX_PHY_MACRO_CNTL_RESERVED293[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED293)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED293[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED294", REG_MMIO, 0x5baa, &mmDCRX_PHY_MACRO_CNTL_RESERVED294[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED294)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED294[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED295", REG_MMIO, 0x5bab, &mmDCRX_PHY_MACRO_CNTL_RESERVED295[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED295)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED295[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED296", REG_MMIO, 0x5bac, &mmDCRX_PHY_MACRO_CNTL_RESERVED296[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED296)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED296[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED297", REG_MMIO, 0x5bad, &mmDCRX_PHY_MACRO_CNTL_RESERVED297[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED297)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED297[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED298", REG_MMIO, 0x5bae, &mmDCRX_PHY_MACRO_CNTL_RESERVED298[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED298)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED298[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED299", REG_MMIO, 0x5baf, &mmDCRX_PHY_MACRO_CNTL_RESERVED299[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED299)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED299[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED300", REG_MMIO, 0x5bb0, &mmDCRX_PHY_MACRO_CNTL_RESERVED300[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED300)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED300[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED301", REG_MMIO, 0x5bb1, &mmDCRX_PHY_MACRO_CNTL_RESERVED301[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED301)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED301[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED302", REG_MMIO, 0x5bb2, &mmDCRX_PHY_MACRO_CNTL_RESERVED302[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED302)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED302[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED303", REG_MMIO, 0x5bb3, &mmDCRX_PHY_MACRO_CNTL_RESERVED303[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED303)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED303[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED304", REG_MMIO, 0x5bb4, &mmDCRX_PHY_MACRO_CNTL_RESERVED304[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED304)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED304[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED305", REG_MMIO, 0x5bb5, &mmDCRX_PHY_MACRO_CNTL_RESERVED305[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED305)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED305[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED306", REG_MMIO, 0x5bb6, &mmDCRX_PHY_MACRO_CNTL_RESERVED306[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED306)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED306[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED307", REG_MMIO, 0x5bb7, &mmDCRX_PHY_MACRO_CNTL_RESERVED307[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED307)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED307[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED308", REG_MMIO, 0x5bb8, &mmDCRX_PHY_MACRO_CNTL_RESERVED308[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED308)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED308[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED309", REG_MMIO, 0x5bb9, &mmDCRX_PHY_MACRO_CNTL_RESERVED309[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED309)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED309[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED310", REG_MMIO, 0x5bba, &mmDCRX_PHY_MACRO_CNTL_RESERVED310[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED310)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED310[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED311", REG_MMIO, 0x5bbb, &mmDCRX_PHY_MACRO_CNTL_RESERVED311[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED311)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED311[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED312", REG_MMIO, 0x5bbc, &mmDCRX_PHY_MACRO_CNTL_RESERVED312[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED312)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED312[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED313", REG_MMIO, 0x5bbd, &mmDCRX_PHY_MACRO_CNTL_RESERVED313[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED313)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED313[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED314", REG_MMIO, 0x5bbe, &mmDCRX_PHY_MACRO_CNTL_RESERVED314[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED314)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED314[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED315", REG_MMIO, 0x5bbf, &mmDCRX_PHY_MACRO_CNTL_RESERVED315[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED315)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED315[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED316", REG_MMIO, 0x5bc0, &mmDCRX_PHY_MACRO_CNTL_RESERVED316[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED316)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED316[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED317", REG_MMIO, 0x5bc1, &mmDCRX_PHY_MACRO_CNTL_RESERVED317[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED317)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED317[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED318", REG_MMIO, 0x5bc2, &mmDCRX_PHY_MACRO_CNTL_RESERVED318[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED318)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED318[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED319", REG_MMIO, 0x5bc3, &mmDCRX_PHY_MACRO_CNTL_RESERVED319[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED319)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED319[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED320", REG_MMIO, 0x5bc4, &mmDCRX_PHY_MACRO_CNTL_RESERVED320[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED320)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED320[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED321", REG_MMIO, 0x5bc5, &mmDCRX_PHY_MACRO_CNTL_RESERVED321[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED321)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED321[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED322", REG_MMIO, 0x5bc6, &mmDCRX_PHY_MACRO_CNTL_RESERVED322[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED322)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED322[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED323", REG_MMIO, 0x5bc7, &mmDCRX_PHY_MACRO_CNTL_RESERVED323[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED323)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED323[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED324", REG_MMIO, 0x5bc8, &mmDCRX_PHY_MACRO_CNTL_RESERVED324[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED324)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED324[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED325", REG_MMIO, 0x5bc9, &mmDCRX_PHY_MACRO_CNTL_RESERVED325[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED325)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED325[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED326", REG_MMIO, 0x5bca, &mmDCRX_PHY_MACRO_CNTL_RESERVED326[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED326)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED326[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED327", REG_MMIO, 0x5bcb, &mmDCRX_PHY_MACRO_CNTL_RESERVED327[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED327)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED327[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED328", REG_MMIO, 0x5bcc, &mmDCRX_PHY_MACRO_CNTL_RESERVED328[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED328)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED328[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED329", REG_MMIO, 0x5bcd, &mmDCRX_PHY_MACRO_CNTL_RESERVED329[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED329)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED329[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED330", REG_MMIO, 0x5bce, &mmDCRX_PHY_MACRO_CNTL_RESERVED330[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED330)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED330[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED331", REG_MMIO, 0x5bcf, &mmDCRX_PHY_MACRO_CNTL_RESERVED331[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED331)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED331[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED332", REG_MMIO, 0x5bd0, &mmDCRX_PHY_MACRO_CNTL_RESERVED332[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED332)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED332[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED333", REG_MMIO, 0x5bd1, &mmDCRX_PHY_MACRO_CNTL_RESERVED333[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED333)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED333[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED334", REG_MMIO, 0x5bd2, &mmDCRX_PHY_MACRO_CNTL_RESERVED334[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED334)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED334[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED335", REG_MMIO, 0x5bd3, &mmDCRX_PHY_MACRO_CNTL_RESERVED335[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED335)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED335[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED336", REG_MMIO, 0x5bd4, &mmDCRX_PHY_MACRO_CNTL_RESERVED336[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED336)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED336[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED337", REG_MMIO, 0x5bd5, &mmDCRX_PHY_MACRO_CNTL_RESERVED337[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED337)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED337[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED338", REG_MMIO, 0x5bd6, &mmDCRX_PHY_MACRO_CNTL_RESERVED338[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED338)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED338[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED339", REG_MMIO, 0x5bd7, &mmDCRX_PHY_MACRO_CNTL_RESERVED339[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED339)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED339[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED340", REG_MMIO, 0x5bd8, &mmDCRX_PHY_MACRO_CNTL_RESERVED340[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED340)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED340[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED341", REG_MMIO, 0x5bd9, &mmDCRX_PHY_MACRO_CNTL_RESERVED341[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED341)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED341[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED342", REG_MMIO, 0x5bda, &mmDCRX_PHY_MACRO_CNTL_RESERVED342[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED342)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED342[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED343", REG_MMIO, 0x5bdb, &mmDCRX_PHY_MACRO_CNTL_RESERVED343[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED343)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED343[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED344", REG_MMIO, 0x5bdc, &mmDCRX_PHY_MACRO_CNTL_RESERVED344[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED344)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED344[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED345", REG_MMIO, 0x5bdd, &mmDCRX_PHY_MACRO_CNTL_RESERVED345[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED345)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED345[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED346", REG_MMIO, 0x5bde, &mmDCRX_PHY_MACRO_CNTL_RESERVED346[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED346)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED346[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED347", REG_MMIO, 0x5bdf, &mmDCRX_PHY_MACRO_CNTL_RESERVED347[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED347)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED347[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED348", REG_MMIO, 0x5be0, &mmDCRX_PHY_MACRO_CNTL_RESERVED348[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED348)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED348[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED349", REG_MMIO, 0x5be1, &mmDCRX_PHY_MACRO_CNTL_RESERVED349[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED349)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED349[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED350", REG_MMIO, 0x5be2, &mmDCRX_PHY_MACRO_CNTL_RESERVED350[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED350)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED350[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED351", REG_MMIO, 0x5be3, &mmDCRX_PHY_MACRO_CNTL_RESERVED351[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED351)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED351[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED352", REG_MMIO, 0x5be4, &mmDCRX_PHY_MACRO_CNTL_RESERVED352[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED352)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED352[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED353", REG_MMIO, 0x5be5, &mmDCRX_PHY_MACRO_CNTL_RESERVED353[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED353)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED353[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED354", REG_MMIO, 0x5be6, &mmDCRX_PHY_MACRO_CNTL_RESERVED354[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED354)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED354[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED355", REG_MMIO, 0x5be7, &mmDCRX_PHY_MACRO_CNTL_RESERVED355[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED355)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED355[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED356", REG_MMIO, 0x5be8, &mmDCRX_PHY_MACRO_CNTL_RESERVED356[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED356)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED356[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED357", REG_MMIO, 0x5be9, &mmDCRX_PHY_MACRO_CNTL_RESERVED357[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED357)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED357[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED358", REG_MMIO, 0x5bea, &mmDCRX_PHY_MACRO_CNTL_RESERVED358[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED358)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED358[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED359", REG_MMIO, 0x5beb, &mmDCRX_PHY_MACRO_CNTL_RESERVED359[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED359)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED359[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED360", REG_MMIO, 0x5bec, &mmDCRX_PHY_MACRO_CNTL_RESERVED360[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED360)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED360[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED361", REG_MMIO, 0x5bed, &mmDCRX_PHY_MACRO_CNTL_RESERVED361[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED361)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED361[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED362", REG_MMIO, 0x5bee, &mmDCRX_PHY_MACRO_CNTL_RESERVED362[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED362)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED362[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED363", REG_MMIO, 0x5bef, &mmDCRX_PHY_MACRO_CNTL_RESERVED363[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED363)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED363[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED364", REG_MMIO, 0x5bf0, &mmDCRX_PHY_MACRO_CNTL_RESERVED364[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED364)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED364[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED365", REG_MMIO, 0x5bf1, &mmDCRX_PHY_MACRO_CNTL_RESERVED365[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED365)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED365[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED366", REG_MMIO, 0x5bf2, &mmDCRX_PHY_MACRO_CNTL_RESERVED366[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED366)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED366[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED367", REG_MMIO, 0x5bf3, &mmDCRX_PHY_MACRO_CNTL_RESERVED367[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED367)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED367[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED368", REG_MMIO, 0x5bf4, &mmDCRX_PHY_MACRO_CNTL_RESERVED368[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED368)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED368[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED369", REG_MMIO, 0x5bf5, &mmDCRX_PHY_MACRO_CNTL_RESERVED369[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED369)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED369[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED370", REG_MMIO, 0x5bf6, &mmDCRX_PHY_MACRO_CNTL_RESERVED370[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED370)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED370[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED371", REG_MMIO, 0x5bf7, &mmDCRX_PHY_MACRO_CNTL_RESERVED371[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED371)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED371[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED372", REG_MMIO, 0x5bf8, &mmDCRX_PHY_MACRO_CNTL_RESERVED372[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED372)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED372[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED373", REG_MMIO, 0x5bf9, &mmDCRX_PHY_MACRO_CNTL_RESERVED373[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED373)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED373[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED374", REG_MMIO, 0x5bfa, &mmDCRX_PHY_MACRO_CNTL_RESERVED374[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED374)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED374[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED375", REG_MMIO, 0x5bfb, &mmDCRX_PHY_MACRO_CNTL_RESERVED375[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED375)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED375[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED376", REG_MMIO, 0x5bfc, &mmDCRX_PHY_MACRO_CNTL_RESERVED376[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED376)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED376[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED377", REG_MMIO, 0x5bfd, &mmDCRX_PHY_MACRO_CNTL_RESERVED377[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED377)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED377[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED378", REG_MMIO, 0x5bfe, &mmDCRX_PHY_MACRO_CNTL_RESERVED378[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED378)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED378[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED379", REG_MMIO, 0x5bff, &mmDCRX_PHY_MACRO_CNTL_RESERVED379[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED379)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED379[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x5c, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_CONTROL", REG_MMIO, 0x5c00, NULL, 0, 0, 0 },
+	{ "mmAUX_CONTROL", REG_MMIO, 0x5c00, &mmAUX_CONTROL[0], sizeof(mmAUX_CONTROL)/sizeof(mmAUX_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_CONTROL", REG_MMIO, 0x5c01, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_CONTROL", REG_MMIO, 0x5c01, &mmAUX_SW_CONTROL[0], sizeof(mmAUX_SW_CONTROL)/sizeof(mmAUX_SW_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_ARB_CONTROL", REG_MMIO, 0x5c02, NULL, 0, 0, 0 },
+	{ "mmAUX_ARB_CONTROL", REG_MMIO, 0x5c02, &mmAUX_ARB_CONTROL[0], sizeof(mmAUX_ARB_CONTROL)/sizeof(mmAUX_ARB_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c03, NULL, 0, 0, 0 },
+	{ "mmAUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c03, &mmAUX_INTERRUPT_CONTROL[0], sizeof(mmAUX_INTERRUPT_CONTROL)/sizeof(mmAUX_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_STATUS", REG_MMIO, 0x5c04, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_STATUS", REG_MMIO, 0x5c04, &mmAUX_SW_STATUS[0], sizeof(mmAUX_SW_STATUS)/sizeof(mmAUX_SW_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_LS_STATUS", REG_MMIO, 0x5c05, NULL, 0, 0, 0 },
+	{ "mmAUX_LS_STATUS", REG_MMIO, 0x5c05, &mmAUX_LS_STATUS[0], sizeof(mmAUX_LS_STATUS)/sizeof(mmAUX_LS_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_DATA", REG_MMIO, 0x5c06, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_DATA", REG_MMIO, 0x5c06, &mmAUX_SW_DATA[0], sizeof(mmAUX_SW_DATA)/sizeof(mmAUX_SW_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_LS_DATA", REG_MMIO, 0x5c07, NULL, 0, 0, 0 },
+	{ "mmAUX_LS_DATA", REG_MMIO, 0x5c07, &mmAUX_LS_DATA[0], sizeof(mmAUX_LS_DATA)/sizeof(mmAUX_LS_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c08, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c08, &mmAUX_DPHY_TX_REF_CONTROL[0], sizeof(mmAUX_DPHY_TX_REF_CONTROL)/sizeof(mmAUX_DPHY_TX_REF_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c09, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c09, &mmAUX_DPHY_TX_CONTROL[0], sizeof(mmAUX_DPHY_TX_CONTROL)/sizeof(mmAUX_DPHY_TX_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c0a, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c0a, &mmAUX_DPHY_RX_CONTROL0[0], sizeof(mmAUX_DPHY_RX_CONTROL0)/sizeof(mmAUX_DPHY_RX_CONTROL0[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c0b, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c0b, &mmAUX_DPHY_RX_CONTROL1[0], sizeof(mmAUX_DPHY_RX_CONTROL1)/sizeof(mmAUX_DPHY_RX_CONTROL1[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c0c, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_STATUS", REG_MMIO, 0x5c0c, &mmAUX_DPHY_TX_STATUS[0], sizeof(mmAUX_DPHY_TX_STATUS)/sizeof(mmAUX_DPHY_TX_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c0d, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_STATUS", REG_MMIO, 0x5c0d, &mmAUX_DPHY_RX_STATUS[0], sizeof(mmAUX_DPHY_RX_STATUS)/sizeof(mmAUX_DPHY_RX_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c0e, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c0e, &mmAUX_GTC_SYNC_CONTROL[0], sizeof(mmAUX_GTC_SYNC_CONTROL)/sizeof(mmAUX_GTC_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c0f, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c0f, &mmAUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmAUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmAUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c10, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c10, &mmAUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmAUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmAUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c11, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c11, &mmAUX_GTC_SYNC_STATUS[0], sizeof(mmAUX_GTC_SYNC_STATUS)/sizeof(mmAUX_GTC_SYNC_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c12, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_DATA", REG_MMIO, 0x5c12, &mmAUX_GTC_SYNC_DATA[0], sizeof(mmAUX_GTC_SYNC_DATA)/sizeof(mmAUX_GTC_SYNC_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c13, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c13, &mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[0], sizeof(mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE)/sizeof(mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c14, NULL, 0, 0, 0 },
+	{ "mmAUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c14, &mmAUX_TEST_DEBUG_INDEX[0], sizeof(mmAUX_TEST_DEBUG_INDEX)/sizeof(mmAUX_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c15, NULL, 0, 0, 0 },
+	{ "mmAUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c15, &mmAUX_TEST_DEBUG_DATA[0], sizeof(mmAUX_TEST_DEBUG_DATA)/sizeof(mmAUX_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP_AUX1_AUX_CONTROL", REG_MMIO, 0x5c1c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_CONTROL", REG_MMIO, 0x5c1d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_ARB_CONTROL", REG_MMIO, 0x5c1e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c1f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_STATUS", REG_MMIO, 0x5c20, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_STATUS", REG_MMIO, 0x5c21, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_DATA", REG_MMIO, 0x5c22, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_DATA", REG_MMIO, 0x5c23, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c24, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c25, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c26, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c27, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c28, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c29, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c2a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c2b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c2c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c2d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c2e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c2f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c30, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c31, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_CONTROL", REG_MMIO, 0x5c38, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_CONTROL", REG_MMIO, 0x5c39, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_ARB_CONTROL", REG_MMIO, 0x5c3a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c3b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_STATUS", REG_MMIO, 0x5c3c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_STATUS", REG_MMIO, 0x5c3d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_DATA", REG_MMIO, 0x5c3e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_DATA", REG_MMIO, 0x5c3f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c40, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c41, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c42, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c43, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c44, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c45, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c46, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c47, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c48, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c49, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c4a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c4b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c4c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c4d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_CONTROL", REG_MMIO, 0x5c54, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_CONTROL", REG_MMIO, 0x5c55, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_ARB_CONTROL", REG_MMIO, 0x5c56, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c57, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_STATUS", REG_MMIO, 0x5c58, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_STATUS", REG_MMIO, 0x5c59, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_DATA", REG_MMIO, 0x5c5a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_DATA", REG_MMIO, 0x5c5b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c5c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c5d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c5e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c5f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c60, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c61, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c62, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c63, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c64, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c65, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c66, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c67, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c68, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c69, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_CONTROL", REG_MMIO, 0x5c70, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_CONTROL", REG_MMIO, 0x5c71, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_ARB_CONTROL", REG_MMIO, 0x5c72, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c73, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_STATUS", REG_MMIO, 0x5c74, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_STATUS", REG_MMIO, 0x5c75, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_DATA", REG_MMIO, 0x5c76, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_DATA", REG_MMIO, 0x5c77, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c78, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c79, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c7a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c7b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c7c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c7d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c7e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c7f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c80, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c81, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c82, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c83, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c84, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c85, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_CONTROL", REG_MMIO, 0x5c8c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_CONTROL", REG_MMIO, 0x5c8d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_ARB_CONTROL", REG_MMIO, 0x5c8e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c8f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_STATUS", REG_MMIO, 0x5c90, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_STATUS", REG_MMIO, 0x5c91, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_DATA", REG_MMIO, 0x5c92, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_DATA", REG_MMIO, 0x5c93, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c94, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c95, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c96, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c97, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c98, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c99, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c9a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c9b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c9c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c9d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c9e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c9f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5ca0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5ca1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x5d, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5d98, &mmDPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED0)/sizeof(mmDPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5d99, &mmDPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED1)/sizeof(mmDPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5d9a, &mmDPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED2)/sizeof(mmDPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5d9b, &mmDPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED3)/sizeof(mmDPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5d9c, &mmDPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED4)/sizeof(mmDPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5d9d, &mmDPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED5)/sizeof(mmDPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5d9e, &mmDPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED6)/sizeof(mmDPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5d9f, &mmDPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED7)/sizeof(mmDPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5da0, &mmDPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED8)/sizeof(mmDPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5da1, &mmDPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED9)/sizeof(mmDPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5da2, &mmDPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED10)/sizeof(mmDPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5da3, &mmDPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED11)/sizeof(mmDPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x5da4, &mmDPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED12)/sizeof(mmDPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x5da5, &mmDPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED13)/sizeof(mmDPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x5da6, &mmDPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED14)/sizeof(mmDPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x5da7, &mmDPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED15)/sizeof(mmDPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x5da8, &mmDPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED16)/sizeof(mmDPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x5da9, &mmDPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED17)/sizeof(mmDPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x5daa, &mmDPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED18)/sizeof(mmDPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x5dab, &mmDPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED19)/sizeof(mmDPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x5dac, &mmDPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED20)/sizeof(mmDPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x5dad, &mmDPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED21)/sizeof(mmDPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x5dae, &mmDPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED22)/sizeof(mmDPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x5daf, &mmDPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED23)/sizeof(mmDPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x5db0, &mmDPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED24)/sizeof(mmDPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x5db1, &mmDPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED25)/sizeof(mmDPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x5db2, &mmDPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED26)/sizeof(mmDPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x5db3, &mmDPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED27)/sizeof(mmDPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x5db4, &mmDPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED28)/sizeof(mmDPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x5db5, &mmDPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED29)/sizeof(mmDPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x5db6, &mmDPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED30)/sizeof(mmDPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x5db7, &mmDPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED31)/sizeof(mmDPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x5db8, &mmDPHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED32)/sizeof(mmDPHY_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x5db9, &mmDPHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED33)/sizeof(mmDPHY_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x5dba, &mmDPHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED34)/sizeof(mmDPHY_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x5dbb, &mmDPHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED35)/sizeof(mmDPHY_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x5dbc, &mmDPHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED36)/sizeof(mmDPHY_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x5dbd, &mmDPHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED37)/sizeof(mmDPHY_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x5dbe, &mmDPHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED38)/sizeof(mmDPHY_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x5dbf, &mmDPHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED39)/sizeof(mmDPHY_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x5dc0, &mmDPHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED40)/sizeof(mmDPHY_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x5dc1, &mmDPHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED41)/sizeof(mmDPHY_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x5dc2, &mmDPHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED42)/sizeof(mmDPHY_MACRO_CNTL_RESERVED42[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x5dc3, &mmDPHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED43)/sizeof(mmDPHY_MACRO_CNTL_RESERVED43[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x5dc4, &mmDPHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED44)/sizeof(mmDPHY_MACRO_CNTL_RESERVED44[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x5dc5, &mmDPHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED45)/sizeof(mmDPHY_MACRO_CNTL_RESERVED45[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x5dc6, &mmDPHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED46)/sizeof(mmDPHY_MACRO_CNTL_RESERVED46[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x5dc7, &mmDPHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED47)/sizeof(mmDPHY_MACRO_CNTL_RESERVED47[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x5dc8, &mmDPHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED48)/sizeof(mmDPHY_MACRO_CNTL_RESERVED48[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x5dc9, &mmDPHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED49)/sizeof(mmDPHY_MACRO_CNTL_RESERVED49[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x5dca, &mmDPHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED50)/sizeof(mmDPHY_MACRO_CNTL_RESERVED50[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x5dcb, &mmDPHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED51)/sizeof(mmDPHY_MACRO_CNTL_RESERVED51[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x5dcc, &mmDPHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED52)/sizeof(mmDPHY_MACRO_CNTL_RESERVED52[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x5dcd, &mmDPHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED53)/sizeof(mmDPHY_MACRO_CNTL_RESERVED53[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x5dce, &mmDPHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED54)/sizeof(mmDPHY_MACRO_CNTL_RESERVED54[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x5dcf, &mmDPHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED55)/sizeof(mmDPHY_MACRO_CNTL_RESERVED55[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x5dd0, &mmDPHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED56)/sizeof(mmDPHY_MACRO_CNTL_RESERVED56[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x5dd1, &mmDPHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED57)/sizeof(mmDPHY_MACRO_CNTL_RESERVED57[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x5dd2, &mmDPHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED58)/sizeof(mmDPHY_MACRO_CNTL_RESERVED58[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x5dd3, &mmDPHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED59)/sizeof(mmDPHY_MACRO_CNTL_RESERVED59[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x5dd4, &mmDPHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED60)/sizeof(mmDPHY_MACRO_CNTL_RESERVED60[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x5dd5, &mmDPHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED61)/sizeof(mmDPHY_MACRO_CNTL_RESERVED61[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x5dd6, &mmDPHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED62)/sizeof(mmDPHY_MACRO_CNTL_RESERVED62[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x5dd7, &mmDPHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED63)/sizeof(mmDPHY_MACRO_CNTL_RESERVED63[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x5e, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "mmWB_ENABLE", REG_MMIO, 0x5e18, &mmWB_ENABLE[0], sizeof(mmWB_ENABLE)/sizeof(mmWB_ENABLE[0]), 0, 0 },
+	{ "mmWB_EC_CONFIG", REG_MMIO, 0x5e19, &mmWB_EC_CONFIG[0], sizeof(mmWB_EC_CONFIG)/sizeof(mmWB_EC_CONFIG[0]), 0, 0 },
+	{ "mmCNV_MODE", REG_MMIO, 0x5e1a, &mmCNV_MODE[0], sizeof(mmCNV_MODE)/sizeof(mmCNV_MODE[0]), 0, 0 },
+	{ "mmCNV_WINDOW_START", REG_MMIO, 0x5e1b, &mmCNV_WINDOW_START[0], sizeof(mmCNV_WINDOW_START)/sizeof(mmCNV_WINDOW_START[0]), 0, 0 },
+	{ "mmCNV_WINDOW_SIZE", REG_MMIO, 0x5e1c, &mmCNV_WINDOW_SIZE[0], sizeof(mmCNV_WINDOW_SIZE)/sizeof(mmCNV_WINDOW_SIZE[0]), 0, 0 },
+	{ "mmCNV_UPDATE", REG_MMIO, 0x5e1d, &mmCNV_UPDATE[0], sizeof(mmCNV_UPDATE)/sizeof(mmCNV_UPDATE[0]), 0, 0 },
+	{ "mmCNV_SOURCE_SIZE", REG_MMIO, 0x5e1e, &mmCNV_SOURCE_SIZE[0], sizeof(mmCNV_SOURCE_SIZE)/sizeof(mmCNV_SOURCE_SIZE[0]), 0, 0 },
+	{ "mmCNV_CSC_CONTROL", REG_MMIO, 0x5e1f, &mmCNV_CSC_CONTROL[0], sizeof(mmCNV_CSC_CONTROL)/sizeof(mmCNV_CSC_CONTROL[0]), 0, 0 },
+	{ "mmCNV_CSC_C11_C12", REG_MMIO, 0x5e20, &mmCNV_CSC_C11_C12[0], sizeof(mmCNV_CSC_C11_C12)/sizeof(mmCNV_CSC_C11_C12[0]), 0, 0 },
+	{ "mmCNV_CSC_C13_C14", REG_MMIO, 0x5e21, &mmCNV_CSC_C13_C14[0], sizeof(mmCNV_CSC_C13_C14)/sizeof(mmCNV_CSC_C13_C14[0]), 0, 0 },
+	{ "mmCNV_CSC_C21_C22", REG_MMIO, 0x5e22, &mmCNV_CSC_C21_C22[0], sizeof(mmCNV_CSC_C21_C22)/sizeof(mmCNV_CSC_C21_C22[0]), 0, 0 },
+	{ "mmCNV_CSC_C23_C24", REG_MMIO, 0x5e23, &mmCNV_CSC_C23_C24[0], sizeof(mmCNV_CSC_C23_C24)/sizeof(mmCNV_CSC_C23_C24[0]), 0, 0 },
+	{ "mmCNV_CSC_C31_C32", REG_MMIO, 0x5e24, &mmCNV_CSC_C31_C32[0], sizeof(mmCNV_CSC_C31_C32)/sizeof(mmCNV_CSC_C31_C32[0]), 0, 0 },
+	{ "mmCNV_CSC_C33_C34", REG_MMIO, 0x5e25, &mmCNV_CSC_C33_C34[0], sizeof(mmCNV_CSC_C33_C34)/sizeof(mmCNV_CSC_C33_C34[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_R", REG_MMIO, 0x5e26, &mmCNV_CSC_ROUND_OFFSET_R[0], sizeof(mmCNV_CSC_ROUND_OFFSET_R)/sizeof(mmCNV_CSC_ROUND_OFFSET_R[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_G", REG_MMIO, 0x5e27, &mmCNV_CSC_ROUND_OFFSET_G[0], sizeof(mmCNV_CSC_ROUND_OFFSET_G)/sizeof(mmCNV_CSC_ROUND_OFFSET_G[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_B", REG_MMIO, 0x5e28, &mmCNV_CSC_ROUND_OFFSET_B[0], sizeof(mmCNV_CSC_ROUND_OFFSET_B)/sizeof(mmCNV_CSC_ROUND_OFFSET_B[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_R", REG_MMIO, 0x5e29, &mmCNV_CSC_CLAMP_R[0], sizeof(mmCNV_CSC_CLAMP_R)/sizeof(mmCNV_CSC_CLAMP_R[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_G", REG_MMIO, 0x5e2a, &mmCNV_CSC_CLAMP_G[0], sizeof(mmCNV_CSC_CLAMP_G)/sizeof(mmCNV_CSC_CLAMP_G[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_B", REG_MMIO, 0x5e2b, &mmCNV_CSC_CLAMP_B[0], sizeof(mmCNV_CSC_CLAMP_B)/sizeof(mmCNV_CSC_CLAMP_B[0]), 0, 0 },
+	{ "mmCNV_TEST_CNTL", REG_MMIO, 0x5e2c, &mmCNV_TEST_CNTL[0], sizeof(mmCNV_TEST_CNTL)/sizeof(mmCNV_TEST_CNTL[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_RED", REG_MMIO, 0x5e2d, &mmCNV_TEST_CRC_RED[0], sizeof(mmCNV_TEST_CRC_RED)/sizeof(mmCNV_TEST_CRC_RED[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_GREEN", REG_MMIO, 0x5e2e, &mmCNV_TEST_CRC_GREEN[0], sizeof(mmCNV_TEST_CRC_GREEN)/sizeof(mmCNV_TEST_CRC_GREEN[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_BLUE", REG_MMIO, 0x5e2f, &mmCNV_TEST_CRC_BLUE[0], sizeof(mmCNV_TEST_CRC_BLUE)/sizeof(mmCNV_TEST_CRC_BLUE[0]), 0, 0 },
+	{ "mmWB_DEBUG_CTRL", REG_MMIO, 0x5e30, &mmWB_DEBUG_CTRL[0], sizeof(mmWB_DEBUG_CTRL)/sizeof(mmWB_DEBUG_CTRL[0]), 0, 0 },
+	{ "mmWB_DBG_MODE", REG_MMIO, 0x5e31, &mmWB_DBG_MODE[0], sizeof(mmWB_DBG_MODE)/sizeof(mmWB_DBG_MODE[0]), 0, 0 },
+	{ "mmWB_HW_DEBUG", REG_MMIO, 0x5e32, &mmWB_HW_DEBUG[0], sizeof(mmWB_HW_DEBUG)/sizeof(mmWB_HW_DEBUG[0]), 0, 0 },
+	{ "mmCNV_INPUT_SELECT", REG_MMIO, 0x5e33, &mmCNV_INPUT_SELECT[0], sizeof(mmCNV_INPUT_SELECT)/sizeof(mmCNV_INPUT_SELECT[0]), 0, 0 },
+	{ "mmCNV_TEST_DEBUG_INDEX", REG_MMIO, 0x5e34, &mmCNV_TEST_DEBUG_INDEX[0], sizeof(mmCNV_TEST_DEBUG_INDEX)/sizeof(mmCNV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCNV_TEST_DEBUG_DATA", REG_MMIO, 0x5e35, &mmCNV_TEST_DEBUG_DATA[0], sizeof(mmCNV_TEST_DEBUG_DATA)/sizeof(mmCNV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmWB_SOFT_RESET", REG_MMIO, 0x5e36, &mmWB_SOFT_RESET[0], sizeof(mmWB_SOFT_RESET)/sizeof(mmWB_SOFT_RESET[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x5f, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "mmDC_PERFMON11_PERFCOUNTER_CNTL", REG_MMIO, 0x5f68, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFCOUNTER_STATE", REG_MMIO, 0x5f69, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x5f6a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CNTL", REG_MMIO, 0x5f6b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CVALUE_LOW", REG_MMIO, 0x5f6c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_HI", REG_MMIO, 0x5f6d, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_LOW", REG_MMIO, 0x5f6e, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x5f6f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x5f70, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CNTL2", REG_MMIO, 0x5f72, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fd0, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fd0, &mmCPLL_MACRO_CNTL_RESERVED0[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED0)/sizeof(mmCPLL_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fd1, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fd1, &mmCPLL_MACRO_CNTL_RESERVED1[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED1)/sizeof(mmCPLL_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fd2, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fd2, &mmCPLL_MACRO_CNTL_RESERVED2[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED2)/sizeof(mmCPLL_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fd3, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fd3, &mmCPLL_MACRO_CNTL_RESERVED3[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED3)/sizeof(mmCPLL_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fd4, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fd4, &mmCPLL_MACRO_CNTL_RESERVED4[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED4)/sizeof(mmCPLL_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fd5, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fd5, &mmCPLL_MACRO_CNTL_RESERVED5[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED5)/sizeof(mmCPLL_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fd6, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fd6, &mmCPLL_MACRO_CNTL_RESERVED6[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED6)/sizeof(mmCPLL_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fd7, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fd7, &mmCPLL_MACRO_CNTL_RESERVED7[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED7)/sizeof(mmCPLL_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fd8, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fd8, &mmCPLL_MACRO_CNTL_RESERVED8[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED8)/sizeof(mmCPLL_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fd9, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fd9, &mmCPLL_MACRO_CNTL_RESERVED9[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED9)/sizeof(mmCPLL_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fda, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fda, &mmCPLL_MACRO_CNTL_RESERVED10[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED10)/sizeof(mmCPLL_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fdb, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fdb, &mmCPLL_MACRO_CNTL_RESERVED11[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED11)/sizeof(mmCPLL_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fdc, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fdd, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fde, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fdf, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fe0, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fe1, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fe2, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fe3, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fe4, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fe5, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fe6, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fe7, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fe8, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fe9, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fea, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5feb, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fec, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fed, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fee, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fef, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5ff0, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5ff1, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5ff2, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5ff3, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5ff4, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5ff5, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5ff6, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5ff7, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5ff8, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5ff9, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5ffa, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5ffb, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5ffc, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5ffd, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5ffe, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_PAYLOAD_CAPABILITY", REG_MMIO, 0x6, &mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[0], sizeof(mmOUTPUT_STREAM_PAYLOAD_CAPABILITY)/sizeof(mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmINPUT_STREAM_PAYLOAD_CAPABILITY", REG_MMIO, 0x6, &mmINPUT_STREAM_PAYLOAD_CAPABILITY[0], sizeof(mmINPUT_STREAM_PAYLOAD_CAPABILITY)/sizeof(mmINPUT_STREAM_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL6", REG_SMC, 0x6, &ixAZALIA_INPUT_CRC0_CHANNEL6[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL6)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL6[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL6", REG_SMC, 0x6, &ixAZALIA_CRC0_CHANNEL6[0], sizeof(ixAZALIA_CRC0_CHANNEL6)/sizeof(ixAZALIA_CRC0_CHANNEL6[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR5", REG_SMC, 0x6, &ixAUDIO_DESCRIPTOR5[0], sizeof(ixAUDIO_DESCRIPTOR5)/sizeof(ixAUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "ixDCIO_DEBUG6", REG_SMC, 0x6, &ixDCIO_DEBUG6[0], sizeof(ixDCIO_DEBUG6)/sizeof(ixDCIO_DEBUG6[0]), 0, 0 },
+	{ "ixATTR06", REG_SMC, 0x6, &ixATTR06[0], sizeof(ixATTR06)/sizeof(ixATTR06[0]), 0, 0 },
+	{ "ixCRT06", REG_SMC, 0x6, &ixCRT06[0], sizeof(ixCRT06)/sizeof(ixCRT06[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x60, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x61, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x62, &ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x6200, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x63, &ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x64, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x64, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x65, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x65, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x66, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x66, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x67, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x67, &ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x6706, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x670d, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x68, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x68, &ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x69, &ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x6a, &ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x6b, &ixAZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x6c, &ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x6d, &ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x6e, &ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x6f09, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6f0a, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x6f0b, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x7, &ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL7", REG_SMC, 0x7, &ixAZALIA_INPUT_CRC0_CHANNEL7[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL7)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL7[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL7", REG_SMC, 0x7, &ixAZALIA_CRC0_CHANNEL7[0], sizeof(ixAZALIA_CRC0_CHANNEL7)/sizeof(ixAZALIA_CRC0_CHANNEL7[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR6", REG_SMC, 0x7, &ixAUDIO_DESCRIPTOR6[0], sizeof(ixAUDIO_DESCRIPTOR6)/sizeof(ixAUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "ixTMDS_DEBUG10", REG_SMC, 0x7, &ixTMDS_DEBUG10[0], sizeof(ixTMDS_DEBUG10)/sizeof(ixTMDS_DEBUG10[0]), 0, 0 },
+	{ "ixDCIO_DEBUG7", REG_SMC, 0x7, &ixDCIO_DEBUG7[0], sizeof(ixDCIO_DEBUG7)/sizeof(ixDCIO_DEBUG7[0]), 0, 0 },
+	{ "ixATTR07", REG_SMC, 0x7, &ixATTR07[0], sizeof(ixATTR07)/sizeof(ixATTR07[0]), 0, 0 },
+	{ "ixCRT07", REG_SMC, 0x7, &ixCRT07[0], sizeof(ixCRT07)/sizeof(ixCRT07[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x7707, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x7708, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x7709, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x771c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x771d, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x771e, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x771f, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x7771, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE", REG_SMC, 0x7777, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE", REG_SMC, 0x7778, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE", REG_SMC, 0x7779, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE", REG_SMC, 0x777a, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR", REG_SMC, 0x777c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x7785, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x7786, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x7787, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x7788, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x7798, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x7799, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x779a, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x779b, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x779c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L", REG_SMC, 0x779d, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H", REG_SMC, 0x779e, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[0]), 0, 0 },
+	{ "ixVGADCC_DBG_DCCIF_C", REG_SMC, 0x7e, &ixVGADCC_DBG_DCCIF_C[0], sizeof(ixVGADCC_DBG_DCCIF_C)/sizeof(ixVGADCC_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x7f09, &ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x7f0c, &ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x8, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "mmINTERRUPT_CONTROL", REG_MMIO, 0x8, &mmINTERRUPT_CONTROL[0], sizeof(mmINTERRUPT_CONTROL)/sizeof(mmINTERRUPT_CONTROL[0]), 0, 0 },
+	{ "ixTMDS_DEBUG11", REG_SMC, 0x8, &ixTMDS_DEBUG11[0], sizeof(ixTMDS_DEBUG11)/sizeof(ixTMDS_DEBUG11[0]), 0, 0 },
+	{ "ixDCIO_DEBUG8", REG_SMC, 0x8, &ixDCIO_DEBUG8[0], sizeof(ixDCIO_DEBUG8)/sizeof(ixDCIO_DEBUG8[0]), 0, 0 },
+	{ "ixATTR08", REG_SMC, 0x8, &ixATTR08[0], sizeof(ixATTR08)/sizeof(ixATTR08[0]), 0, 0 },
+	{ "ixCRT08", REG_SMC, 0x8, &ixCRT08[0], sizeof(ixCRT08)/sizeof(ixCRT08[0]), 0, 0 },
+	{ "mmWALL_CLOCK_COUNTER_ALIAS", REG_MMIO, 0x80c, &mmWALL_CLOCK_COUNTER_ALIAS[0], sizeof(mmWALL_CLOCK_COUNTER_ALIAS)/sizeof(mmWALL_CLOCK_COUNTER_ALIAS[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x821, &mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x9, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 },
+	{ "ixIDDCCIF02_DBG_DCCIF_C", REG_SMC, 0x9, &ixIDDCCIF02_DBG_DCCIF_C[0], sizeof(ixIDDCCIF02_DBG_DCCIF_C)/sizeof(ixIDDCCIF02_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR8", REG_SMC, 0x9, &ixAUDIO_DESCRIPTOR8[0], sizeof(ixAUDIO_DESCRIPTOR8)/sizeof(ixAUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "mmINTERRUPT_STATUS", REG_MMIO, 0x9, &mmINTERRUPT_STATUS[0], sizeof(mmINTERRUPT_STATUS)/sizeof(mmINTERRUPT_STATUS[0]), 0, 0 },
+	{ "ixTMDS_DEBUG12", REG_SMC, 0x9, &ixTMDS_DEBUG12[0], sizeof(ixTMDS_DEBUG12)/sizeof(ixTMDS_DEBUG12[0]), 0, 0 },
+	{ "ixDCIO_DEBUG9", REG_SMC, 0x9, &ixDCIO_DEBUG9[0], sizeof(ixDCIO_DEBUG9)/sizeof(ixDCIO_DEBUG9[0]), 0, 0 },
+	{ "ixATTR09", REG_SMC, 0x9, &ixATTR09[0], sizeof(ixATTR09)/sizeof(ixATTR09[0]), 0, 0 },
+	{ "ixCRT09", REG_SMC, 0x9, &ixCRT09[0], sizeof(ixCRT09)/sizeof(ixCRT09[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG", REG_SMC, 0xa, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[0]), 0, 0 },
+	{ "ixDMIF_DEBUG02_CORE1", REG_SMC, 0xa, &ixDMIF_DEBUG02_CORE1[0], sizeof(ixDMIF_DEBUG02_CORE1)/sizeof(ixDMIF_DEBUG02_CORE1[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR9", REG_SMC, 0xa, &ixAUDIO_DESCRIPTOR9[0], sizeof(ixAUDIO_DESCRIPTOR9)/sizeof(ixAUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "ixTMDS_DEBUG13", REG_SMC, 0xa, &ixTMDS_DEBUG13[0], sizeof(ixTMDS_DEBUG13)/sizeof(ixTMDS_DEBUG13[0]), 0, 0 },
+	{ "ixDCIO_DEBUGA", REG_SMC, 0xa, &ixDCIO_DEBUGA[0], sizeof(ixDCIO_DEBUGA)/sizeof(ixDCIO_DEBUGA[0]), 0, 0 },
+	{ "ixATTR0A", REG_SMC, 0xa, &ixATTR0A[0], sizeof(ixATTR0A)/sizeof(ixATTR0A[0]), 0, 0 },
+	{ "ixCRT0A", REG_SMC, 0xa, &ixCRT0A[0], sizeof(ixCRT0A)/sizeof(ixCRT0A[0]), 0, 0 },
+	{ "ixIDDCCIF04_DBG_DCCIF_E", REG_SMC, 0xb, &ixIDDCCIF04_DBG_DCCIF_E[0], sizeof(ixIDDCCIF04_DBG_DCCIF_E)/sizeof(ixIDDCCIF04_DBG_DCCIF_E[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR10", REG_SMC, 0xb, &ixAUDIO_DESCRIPTOR10[0], sizeof(ixAUDIO_DESCRIPTOR10)/sizeof(ixAUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION6", REG_SMC, 0xb, &ixSINK_DESCRIPTION6[0], sizeof(ixSINK_DESCRIPTION6)/sizeof(ixSINK_DESCRIPTION6[0]), 0, 0 },
+	{ "ixDCIO_DEBUGB", REG_SMC, 0xb, &ixDCIO_DEBUGB[0], sizeof(ixDCIO_DEBUGB)/sizeof(ixDCIO_DEBUGB[0]), 0, 0 },
+	{ "ixATTR0B", REG_SMC, 0xb, &ixATTR0B[0], sizeof(ixATTR0B)/sizeof(ixATTR0B[0]), 0, 0 },
+	{ "ixCRT0B", REG_SMC, 0xb, &ixCRT0B[0], sizeof(ixCRT0B)/sizeof(ixCRT0B[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0xc, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 },
+	{ "ixIDDCCIF05_DBG_DCCIF_F", REG_SMC, 0xc, &ixIDDCCIF05_DBG_DCCIF_F[0], sizeof(ixIDDCCIF05_DBG_DCCIF_F)/sizeof(ixIDDCCIF05_DBG_DCCIF_F[0]), 0, 0 },
+	{ "mmWALL_CLOCK_COUNTER", REG_MMIO, 0xc, &mmWALL_CLOCK_COUNTER[0], sizeof(mmWALL_CLOCK_COUNTER)/sizeof(mmWALL_CLOCK_COUNTER[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION7", REG_SMC, 0xc, &ixSINK_DESCRIPTION7[0], sizeof(ixSINK_DESCRIPTION7)/sizeof(ixSINK_DESCRIPTION7[0]), 0, 0 },
+	{ "ixMVP_DEBUG_12", REG_SMC, 0xc, &ixMVP_DEBUG_12[0], sizeof(ixMVP_DEBUG_12)/sizeof(ixMVP_DEBUG_12[0]), 0, 0 },
+	{ "ixDCIO_DEBUGC", REG_SMC, 0xc, &ixDCIO_DEBUGC[0], sizeof(ixDCIO_DEBUGC)/sizeof(ixDCIO_DEBUGC[0]), 0, 0 },
+	{ "ixATTR0C", REG_SMC, 0xc, &ixATTR0C[0], sizeof(ixATTR0C)/sizeof(ixATTR0C[0]), 0, 0 },
+	{ "ixCRT0C", REG_SMC, 0xc, &ixCRT0C[0], sizeof(ixCRT0C)/sizeof(ixCRT0C[0]), 0, 0 },
+	{ "mmVGA_RENDER_CONTROL", REG_MMIO, 0xc0, &mmVGA_RENDER_CONTROL[0], sizeof(mmVGA_RENDER_CONTROL)/sizeof(mmVGA_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SEQUENCER_RESET_CONTROL", REG_MMIO, 0xc1, &mmVGA_SEQUENCER_RESET_CONTROL[0], sizeof(mmVGA_SEQUENCER_RESET_CONTROL)/sizeof(mmVGA_SEQUENCER_RESET_CONTROL[0]), 0, 0 },
+	{ "mmVGA_MODE_CONTROL", REG_MMIO, 0xc2, &mmVGA_MODE_CONTROL[0], sizeof(mmVGA_MODE_CONTROL)/sizeof(mmVGA_MODE_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SURFACE_PITCH_SELECT", REG_MMIO, 0xc3, &mmVGA_SURFACE_PITCH_SELECT[0], sizeof(mmVGA_SURFACE_PITCH_SELECT)/sizeof(mmVGA_SURFACE_PITCH_SELECT[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS", REG_MMIO, 0xc4, &mmVGA_MEMORY_BASE_ADDRESS[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS)/sizeof(mmVGA_MEMORY_BASE_ADDRESS[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_INDEX", REG_MMIO, 0xc5, &mmVGA_TEST_DEBUG_INDEX[0], sizeof(mmVGA_TEST_DEBUG_INDEX)/sizeof(mmVGA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmVGA_DISPBUF1_SURFACE_ADDR", REG_MMIO, 0xc6, &mmVGA_DISPBUF1_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF1_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF1_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_DATA", REG_MMIO, 0xc7, &mmVGA_TEST_DEBUG_DATA[0], sizeof(mmVGA_TEST_DEBUG_DATA)/sizeof(mmVGA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGA_DISPBUF2_SURFACE_ADDR", REG_MMIO, 0xc8, &mmVGA_DISPBUF2_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF2_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF2_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS_HIGH", REG_MMIO, 0xc9, &mmVGA_MEMORY_BASE_ADDRESS_HIGH[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH)/sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmVGA_HDP_CONTROL", REG_MMIO, 0xca, &mmVGA_HDP_CONTROL[0], sizeof(mmVGA_HDP_CONTROL)/sizeof(mmVGA_HDP_CONTROL[0]), 0, 0 },
+	{ "mmVGA_CACHE_CONTROL", REG_MMIO, 0xcb, &mmVGA_CACHE_CONTROL[0], sizeof(mmVGA_CACHE_CONTROL)/sizeof(mmVGA_CACHE_CONTROL[0]), 0, 0 },
+	{ "mmD1VGA_CONTROL", REG_MMIO, 0xcc, &mmD1VGA_CONTROL[0], sizeof(mmD1VGA_CONTROL)/sizeof(mmD1VGA_CONTROL[0]), 0, 0 },
+	{ "mmD2VGA_CONTROL", REG_MMIO, 0xce, &mmD2VGA_CONTROL[0], sizeof(mmD2VGA_CONTROL)/sizeof(mmD2VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_HW_DEBUG", REG_MMIO, 0xcf, &mmVGA_HW_DEBUG[0], sizeof(mmVGA_HW_DEBUG)/sizeof(mmVGA_HW_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0xd, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR12", REG_SMC, 0xd, &ixAUDIO_DESCRIPTOR12[0], sizeof(ixAUDIO_DESCRIPTOR12)/sizeof(ixAUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION8", REG_SMC, 0xd, &ixSINK_DESCRIPTION8[0], sizeof(ixSINK_DESCRIPTION8)/sizeof(ixSINK_DESCRIPTION8[0]), 0, 0 },
+	{ "ixMVP_DEBUG_13", REG_SMC, 0xd, &ixMVP_DEBUG_13[0], sizeof(ixMVP_DEBUG_13)/sizeof(ixMVP_DEBUG_13[0]), 0, 0 },
+	{ "ixDCIO_DEBUGD", REG_SMC, 0xd, &ixDCIO_DEBUGD[0], sizeof(ixDCIO_DEBUGD)/sizeof(ixDCIO_DEBUGD[0]), 0, 0 },
+	{ "ixATTR0D", REG_SMC, 0xd, &ixATTR0D[0], sizeof(ixATTR0D)/sizeof(ixATTR0D[0]), 0, 0 },
+	{ "ixCRT0D", REG_SMC, 0xd, &ixCRT0D[0], sizeof(ixCRT0D)/sizeof(ixCRT0D[0]), 0, 0 },
+	{ "mmVGA_STATUS", REG_MMIO, 0xd0, &mmVGA_STATUS[0], sizeof(mmVGA_STATUS)/sizeof(mmVGA_STATUS[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_CONTROL", REG_MMIO, 0xd1, &mmVGA_INTERRUPT_CONTROL[0], sizeof(mmVGA_INTERRUPT_CONTROL)/sizeof(mmVGA_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmVGA_STATUS_CLEAR", REG_MMIO, 0xd2, &mmVGA_STATUS_CLEAR[0], sizeof(mmVGA_STATUS_CLEAR)/sizeof(mmVGA_STATUS_CLEAR[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_STATUS", REG_MMIO, 0xd3, &mmVGA_INTERRUPT_STATUS[0], sizeof(mmVGA_INTERRUPT_STATUS)/sizeof(mmVGA_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmVGA_MAIN_CONTROL", REG_MMIO, 0xd4, &mmVGA_MAIN_CONTROL[0], sizeof(mmVGA_MAIN_CONTROL)/sizeof(mmVGA_MAIN_CONTROL[0]), 0, 0 },
+	{ "mmVGA_TEST_CONTROL", REG_MMIO, 0xd5, &mmVGA_TEST_CONTROL[0], sizeof(mmVGA_TEST_CONTROL)/sizeof(mmVGA_TEST_CONTROL[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_INDEX", REG_MMIO, 0xd6, &mmVGA_DEBUG_READBACK_INDEX[0], sizeof(mmVGA_DEBUG_READBACK_INDEX)/sizeof(mmVGA_DEBUG_READBACK_INDEX[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_DATA", REG_MMIO, 0xd7, &mmVGA_DEBUG_READBACK_DATA[0], sizeof(mmVGA_DEBUG_READBACK_DATA)/sizeof(mmVGA_DEBUG_READBACK_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0xe, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 },
+	{ "mmSTREAM_SYNCHRONIZATION", REG_MMIO, 0xe, &mmSTREAM_SYNCHRONIZATION[0], sizeof(mmSTREAM_SYNCHRONIZATION)/sizeof(mmSTREAM_SYNCHRONIZATION[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR13", REG_SMC, 0xe, &ixAUDIO_DESCRIPTOR13[0], sizeof(ixAUDIO_DESCRIPTOR13)/sizeof(ixAUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION9", REG_SMC, 0xe, &ixSINK_DESCRIPTION9[0], sizeof(ixSINK_DESCRIPTION9)/sizeof(ixSINK_DESCRIPTION9[0]), 0, 0 },
+	{ "ixMVP_DEBUG_14", REG_SMC, 0xe, &ixMVP_DEBUG_14[0], sizeof(ixMVP_DEBUG_14)/sizeof(ixMVP_DEBUG_14[0]), 0, 0 },
+	{ "ixDCIO_DEBUGE", REG_SMC, 0xe, &ixDCIO_DEBUGE[0], sizeof(ixDCIO_DEBUGE)/sizeof(ixDCIO_DEBUGE[0]), 0, 0 },
+	{ "ixATTR0E", REG_SMC, 0xe, &ixATTR0E[0], sizeof(ixATTR0E)/sizeof(ixATTR0E[0]), 0, 0 },
+	{ "ixCRT0E", REG_SMC, 0xe, &ixCRT0E[0], sizeof(ixCRT0E)/sizeof(ixCRT0E[0]), 0, 0 },
+	{ "mmVGA0_CRTC8_DATA", REG_MMIO, 0xed, NULL, 0, 0, 0 },
+	{ "mmVGA0_CRTC8_IDX", REG_MMIO, 0xed, NULL, 0, 0, 0 },
+	{ "mmCRTC8_DATA", REG_MMIO, 0xed, &mmCRTC8_DATA[0], sizeof(mmCRTC8_DATA)/sizeof(mmCRTC8_DATA[0]), 0, 0 },
+	{ "mmCRTC8_IDX", REG_MMIO, 0xed, &mmCRTC8_IDX[0], sizeof(mmCRTC8_IDX)/sizeof(mmCRTC8_IDX[0]), 0, 0 },
+	{ "mmVGA0_GENFC_WT", REG_MMIO, 0xee, NULL, 0, 0, 0 },
+	{ "mmVGA0_GENS1", REG_MMIO, 0xee, NULL, 0, 0, 0 },
+	{ "mmGENFC_WT", REG_MMIO, 0xee, &mmGENFC_WT[0], sizeof(mmGENFC_WT)/sizeof(mmGENFC_WT[0]), 0, 0 },
+	{ "mmGENS1", REG_MMIO, 0xee, &mmGENS1[0], sizeof(mmGENS1)/sizeof(mmGENS1[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION10", REG_SMC, 0xf, &ixSINK_DESCRIPTION10[0], sizeof(ixSINK_DESCRIPTION10)/sizeof(ixSINK_DESCRIPTION10[0]), 0, 0 },
+	{ "ixMVP_DEBUG_15", REG_SMC, 0xf, &ixMVP_DEBUG_15[0], sizeof(ixMVP_DEBUG_15)/sizeof(ixMVP_DEBUG_15[0]), 0, 0 },
+	{ "ixDCIO_DEBUGF", REG_SMC, 0xf, &ixDCIO_DEBUGF[0], sizeof(ixDCIO_DEBUGF)/sizeof(ixDCIO_DEBUGF[0]), 0, 0 },
+	{ "ixATTR0F", REG_SMC, 0xf, &ixATTR0F[0], sizeof(ixATTR0F)/sizeof(ixATTR0F[0]), 0, 0 },
+	{ "ixCRT0F", REG_SMC, 0xf, &ixCRT0F[0], sizeof(ixCRT0F)/sizeof(ixCRT0F[0]), 0, 0 },
+	{ "mmGENMO_WT", REG_MMIO, 0xf0, &mmGENMO_WT[0], sizeof(mmGENMO_WT)/sizeof(mmGENMO_WT[0]), 0, 0 },
+	{ "mmGENENB", REG_MMIO, 0xf0, &mmGENENB[0], sizeof(mmGENENB)/sizeof(mmGENENB[0]), 0, 0 },
+	{ "mmGENS0", REG_MMIO, 0xf0, &mmGENS0[0], sizeof(mmGENS0)/sizeof(mmGENS0[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_SMC, 0xf00, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID", REG_SMC, 0xf02, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0xf04, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "mmDAC_R_INDEX", REG_MMIO, 0xf1, &mmDAC_R_INDEX[0], sizeof(mmDAC_R_INDEX)/sizeof(mmDAC_R_INDEX[0]), 0, 0 },
+	{ "mmSEQ8_DATA", REG_MMIO, 0xf1, &mmSEQ8_DATA[0], sizeof(mmSEQ8_DATA)/sizeof(mmSEQ8_DATA[0]), 0, 0 },
+	{ "mmDAC_MASK", REG_MMIO, 0xf1, &mmDAC_MASK[0], sizeof(mmDAC_MASK)/sizeof(mmDAC_MASK[0]), 0, 0 },
+	{ "mmDAC_W_INDEX", REG_MMIO, 0xf2, &mmDAC_W_INDEX[0], sizeof(mmDAC_W_INDEX)/sizeof(mmDAC_W_INDEX[0]), 0, 0 },
+	{ "mmGENFC_RD", REG_MMIO, 0xf2, &mmGENFC_RD[0], sizeof(mmGENFC_RD)/sizeof(mmGENFC_RD[0]), 0, 0 },
+	{ "mmGRPH8_DATA", REG_MMIO, 0xf3, &mmGRPH8_DATA[0], sizeof(mmGRPH8_DATA)/sizeof(mmGRPH8_DATA[0]), 0, 0 },
+	{ "mmGRPH8_IDX", REG_MMIO, 0xf3, &mmGRPH8_IDX[0], sizeof(mmGRPH8_IDX)/sizeof(mmGRPH8_IDX[0]), 0, 0 },
+	{ "mmGENMO_RD", REG_MMIO, 0xf3, &mmGENMO_RD[0], sizeof(mmGENMO_RD)/sizeof(mmGENMO_RD[0]), 0, 0 },
+	{ "mmVGA1_CRTC8_DATA", REG_MMIO, 0xf5, NULL, 0, 0, 0 },
+	{ "mmVGA1_CRTC8_IDX", REG_MMIO, 0xf5, NULL, 0, 0, 0 },
+	{ "mmVGA1_GENFC_WT", REG_MMIO, 0xf6, NULL, 0, 0, 0 },
+	{ "mmVGA1_GENS1", REG_MMIO, 0xf6, NULL, 0, 0, 0 },
+	{ "mmD3VGA_CONTROL", REG_MMIO, 0xf8, &mmD3VGA_CONTROL[0], sizeof(mmD3VGA_CONTROL)/sizeof(mmD3VGA_CONTROL[0]), 0, 0 },
+	{ "mmD4VGA_CONTROL", REG_MMIO, 0xf9, &mmD4VGA_CONTROL[0], sizeof(mmD4VGA_CONTROL)/sizeof(mmD4VGA_CONTROL[0]), 0, 0 },
+	{ "mmD5VGA_CONTROL", REG_MMIO, 0xfa, &mmD5VGA_CONTROL[0], sizeof(mmD5VGA_CONTROL)/sizeof(mmD5VGA_CONTROL[0]), 0, 0 },
+	{ "mmD6VGA_CONTROL", REG_MMIO, 0xfb, &mmD6VGA_CONTROL[0], sizeof(mmD6VGA_CONTROL)/sizeof(mmD6VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SOURCE_SELECT", REG_MMIO, 0xfc, &mmVGA_SOURCE_SELECT[0], sizeof(mmVGA_SOURCE_SELECT)/sizeof(mmVGA_SOURCE_SELECT[0]), 0, 0 },
diff --git a/src/lib/ip/dce110.c b/src/lib/ip/dce110.c
new file mode 100644
index 0000000..9db4da8
--- /dev/null
+++ b/src/lib/ip/dce110.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "dce110_bits.i"
+
+static const struct umr_reg dce110_registers[] = {
+#include "dce110_regs.i"
+};
+
+struct umr_ip_block *umr_create_dce110(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "dce110";
+	ip->no_regs = sizeof(dce110_registers)/sizeof(dce110_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(dce110_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, dce110_registers, sizeof(dce110_registers));
+	return ip;
+}
diff --git a/src/lib/ip/dce110_bits.i b/src/lib/ip/dce110_bits.i
new file mode 100644
index 0000000..45d7eca
--- /dev/null
+++ b/src/lib/ip/dce110_bits.i
@@ -0,0 +1,14116 @@
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[] = {
+	 { "AZALIA_INPUT_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[] = {
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL0[] = {
+	 { "INPUT_CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_FIFO_SIZE_CONTROL[] = {
+	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
+	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
+	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL0[] = {
+	 { "CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_CAPABILITIES[] = {
+	 { "SIXTY_FOUR_BIT_ADDRESS_SUPPORTED", 0, 0, &umr_bitfield_default },
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+	 { "NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED", 3, 7, &umr_bitfield_default },
+	 { "NUMBER_OF_INPUT_STREAMS_SUPPORTED", 8, 11, &umr_bitfield_default },
+	 { "NUMBER_OF_OUTPUT_STREAMS_SUPPORTED", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG_ID[] = {
+	 { "DCIO_DEBUG_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG_ID[] = {
+	 { "FMT_DEBUG_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR00[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ00[] = {
+	 { "SEQ_RST0B", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RST1B", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[] = {
+	 { "PRODUCT_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_LATENCY_COUNTER_CONTROL[] = {
+	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL1[] = {
+	 { "INPUT_CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_PAYLOAD_CAPABILITY[] = {
+	 { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL1[] = {
+	 { "CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR0[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1[] = {
+	 { "DCO_DCIO_MVP_DVOCNTL_A0_REG", 0, 1, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_MASK_REG", 2, 3, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_EN_REG", 4, 5, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_A0", 6, 7, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_SEL0", 8, 9, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_EN", 10, 11, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCLK_C", 12, 12, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0_REG", 13, 13, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0_PREMUX", 14, 14, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0", 15, 15, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN_REG", 16, 16, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_HSYNC_TRISTATE", 17, 17, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_CLK_TRISTATE", 18, 18, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN_PREMUX", 19, 19, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN", 20, 20, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_MUX", 21, 21, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_MASK_REG", 22, 22, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_VSYNC_TRISTATE", 24, 24, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_RATE_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_SEL0_PREMUX", 26, 26, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_SEL0", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG0[] = {
+	 { "FMT_DEBUG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR01[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ01[] = {
+	 { "SEQ_DOT8", 0, 0, &umr_bitfield_default },
+	 { "SEQ_SHIFT2", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PCLKBY2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_SHIFT4", 4, 4, &umr_bitfield_default },
+	 { "SEQ_MAXBW", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_LOWER_BASE_ADDRESS[] = {
+	 { "CORB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "CORB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION11[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_A[] = {
+	 { "DP_AUX_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG10[] = {
+	 { "DCIO_DIGC_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR10[] = {
+	 { "ATTR_GRPH_MODE", 0, 0, &umr_bitfield_default },
+	 { "ATTR_MONO_EN", 1, 1, &umr_bitfield_default },
+	 { "ATTR_LGRPH_EN", 2, 2, &umr_bitfield_default },
+	 { "ATTR_BLINK_EN", 3, 3, &umr_bitfield_default },
+	 { "ATTR_PANTOPONLY", 5, 5, &umr_bitfield_default },
+	 { "ATTR_PCLKBY2", 6, 6, &umr_bitfield_default },
+	 { "ATTR_CSEL_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT10[] = {
+	 { "V_SYNC_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV0_CRTC_PIXEL_RATE_CNTL[] = {
+	 { "DCFEV0_CRTC_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPREFCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "DPREFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DPREFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREFCLK_CNTL[] = {
+	 { "REFCLK_CLOCK_EN", 0, 0, &umr_bitfield_default },
+	 { "REFCLK_SRC_SEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREFCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "REFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_CLK_FORCE_CONTROL[] = {
+	 { "DPDBG_CLK_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "DPDBG_CLK_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_PERFMON_CNTL2[] = {
+	 { "DCCG_PERF_DSICLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERF_REFCLK_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_UPPER_BASE_ADDRESS[] = {
+	 { "CORB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION12[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_B[] = {
+	 { "DP_AUX_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG11[] = {
+	 { "DCIO_DIGD_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR11[] = {
+	 { "ATTR_OVSC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT11[] = {
+	 { "V_SYNC_END", 0, 3, &umr_bitfield_default },
+	 { "V_INTR_CLR", 4, 4, &umr_bitfield_default },
+	 { "V_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "SEL5_REFRESH_CYC", 6, 6, &umr_bitfield_default },
+	 { "C0T7_WR_ONLY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CBUS_WRCMD_DELAY[] = {
+	 { "CBUS_PLL_WRCMD_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DEBUG_CNTL[] = {
+	 { "DCCG_DS_DEBUG_COUNT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_VALUE", 4, 12, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT_SRC_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DTO_INCR[] = {
+	 { "DCCG_DS_DTO_INCR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DTO_MODULO[] = {
+	 { "DCCG_DS_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_CNTL[] = {
+	 { "DCCG_DS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DS_HW_CAL_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DCCG_DS_ENABLED_STATUS", 9, 9, &umr_bitfield_default },
+	 { "DCCG_DS_XTALIN_RATE_DIV", 16, 17, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_REMOVE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DCCG_DS_DELAY_XTAL_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_HW_CAL_INTERVAL[] = {
+	 { "DCCG_DS_HW_CAL_INTERVAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKG_CLOCK_ENABLE[] = {
+	 { "SYMCLKG_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKG_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKG_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPREFCLK_CNTL[] = {
+	 { "DPREFCLK_SRC_SEL", 0, 2, &umr_bitfield_default },
+	 { "UNB_DB_CLK_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCE_VERSION[] = {
+	 { "MAJOR_VERSION", 0, 7, &umr_bitfield_default },
+	 { "MINOR_VERSION", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEM_WRITE_PAGE_ADDR[] = {
+	 { "VGA_MEM_WRITE_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
+	 { "VGA_MEM_WRITE_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_WRITE_POINTER[] = {
+	 { "CORB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_READ_POINTER[] = {
+	 { "CORB_READ_POINTER", 0, 7, &umr_bitfield_default },
+	 { "CORB_READ_POINTER_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_C[] = {
+	 { "DP_AUX_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG12[] = {
+	 { "DCIO_DIGE_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR12[] = {
+	 { "ATTR_MAP_EN", 0, 3, &umr_bitfield_default },
+	 { "ATTR_VSMUX", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT12[] = {
+	 { "V_DISP_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CNTL[] = {
+	 { "DCCG_GTC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_INCR[] = {
+	 { "DCCG_GTC_DTO_INCR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_MODULO[] = {
+	 { "DCCG_GTC_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CURRENT[] = {
+	 { "DCCG_GTC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENTIST_DISPCLK_CNTL[] = {
+	 { "DENTIST_DISPCLK_WDIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_RDIVIDER", 8, 14, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_MODE", 15, 16, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHGTOG", 17, 17, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_DONETOG", 18, 18, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_DONE", 19, 19, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHG_DONE", 20, 20, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHGTOG", 21, 21, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_DONETOG", 22, 22, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_WDIVIDER", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CLK_ENABLE[] = {
+	 { "DACA_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DACB_CLK_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CLK_ENABLE[] = {
+	 { "DVO_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_WRITE[] = {
+	 { "AVSYNC_COUNTER_WRVALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_CONTROL[] = {
+	 { "AVSYNC_COUNTER_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_SMU_INTERRUPT_CNTL[] = {
+	 { "DMCU_SMU_STATIC_SCREEN_INT", 0, 0, &umr_bitfield_default },
+	 { "DMCU_SMU_STATIC_SCREEN_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_CONTROL[] = {
+	 { "DISPLAY0_FORCE_VBI", 0, 0, &umr_bitfield_default },
+	 { "DISPLAY1_FORCE_VBI", 1, 1, &umr_bitfield_default },
+	 { "DISPLAY2_FORCE_VBI", 2, 2, &umr_bitfield_default },
+	 { "DISPLAY3_FORCE_VBI", 3, 3, &umr_bitfield_default },
+	 { "DISPLAY4_FORCE_VBI", 4, 4, &umr_bitfield_default },
+	 { "DISPLAY5_FORCE_VBI", 5, 5, &umr_bitfield_default },
+	 { "DISPLAY_V0_FORCE_VBI", 6, 6, &umr_bitfield_default },
+	 { "SMU_DC_INT_CLEAR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_INTERRUPT_CONTROL[] = {
+	 { "DC_SMU_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DC_SMU_INT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DC_SMU_INT_EVENT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_READ[] = {
+	 { "AVSYNC_COUNTER_RDVALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEM_READ_PAGE_ADDR[] = {
+	 { "VGA_MEM_READ_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
+	 { "VGA_MEM_READ_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION14[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_D[] = {
+	 { "DP_AUX_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG13[] = {
+	 { "DCIO_DIGF_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_STATUS[] = {
+	 { "CORB_MEMORY_ERROR_INDICATION", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_SIZE[] = {
+	 { "CORB_SIZE", 0, 1, &umr_bitfield_default },
+	 { "CORB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR13[] = {
+	 { "ATTR_PPAN", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT13[] = {
+	 { "DISP_PITCH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMILLISECOND_TIME_BASE_DIV[] = {
+	 { "MILLISECOND_TIME_BASE_DIV", 0, 16, &umr_bitfield_default },
+	 { "MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_FREQ_CHANGE_CNTL[] = {
+	 { "DISPCLK_STEP_DELAY", 0, 13, &umr_bitfield_default },
+	 { "DISPCLK_STEP_SIZE", 16, 19, &umr_bitfield_default },
+	 { "DISPCLK_FREQ_RAMP_DONE", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_MAX_ERRDET_CYCLES", 25, 27, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_RESET", 28, 28, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_STATE", 29, 29, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_OVR_EN", 30, 30, &umr_bitfield_default },
+	 { "DISPCLK_CHG_FWD_CORR_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_MEM_GLOBAL_PWR_REQ_CNTL[] = {
+	 { "DC_MEM_GLOBAL_PWR_REQ_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_PERFMON_CNTL[] = {
+	 { "DCCG_PERF_DISPCLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERF_DPREFCLK_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK1_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK2_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERF_RUN", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_VSYNC", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_HSYNC", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERF_CRTC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCCG_PERF_XTALIN_PULSE_DIV", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL[] = {
+	 { "DISPCLK_DCCG_GATE_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_R_DCCG_GATE_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "SCLK_GATE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "DPREFCLK_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "DACACLK_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "DACBCLK_GATE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DVOACLK_GATE_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "DPDBG_CLK_GATE_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "DPREFCLK_R_DCCG_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "AOMCLK0_GATE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "AOMCLK1_GATE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "AOMCLK2_GATE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "AUDIO_DTO2_CLK_GATE_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "DPREFCLK_GTC_GATE_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "UNB_DB_CLK_GATE_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "REFCLK_GATE_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "REFCLK_R_DIG_GATE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "DSICLK_GATE_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "BYTECLK_GATE_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "ESCCLK_GATE_DISABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "DISPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DISPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_SCLK_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CAC_STATUS[] = {
+	 { "CAC_STATUS_RDDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK1_RESYNC_CNTL[] = {
+	 { "PIXCLK1_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL1", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK2_RESYNC_CNTL[] = {
+	 { "PIXCLK2_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL2", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK0_RESYNC_CNTL[] = {
+	 { "PIXCLK0_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL0", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMICROSECOND_TIME_BASE_DIV[] = {
+	 { "MICROSECOND_TIME_BASE_DIV", 0, 6, &umr_bitfield_default },
+	 { "XTAL_REF_DIV", 8, 14, &umr_bitfield_default },
+	 { "XTAL_REF_SEL", 16, 16, &umr_bitfield_default },
+	 { "XTAL_REF_CLOCK_SOURCE_SEL", 17, 17, &umr_bitfield_default },
+	 { "MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL2[] = {
+	 { "SYMCLKA_FE_GATE_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_GATE_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "SYMCLKC_FE_GATE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "SYMCLKD_FE_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "SYMCLKE_FE_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_GATE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SYMCLKG_FE_GATE_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "SYMCLKLPA_FE_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SYMCLKLPB_FE_GATE_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "SYMCLKA_GATE_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "SYMCLKB_GATE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "SYMCLKC_GATE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "SYMCLKD_GATE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "SYMCLKE_GATE_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "SYMCLKF_GATE_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "SYMCLKG_GATE_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "SYMCLKLPA_GATE_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "SYMCLKLPB_GATE_DISABLE", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "SYMCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SYMCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHYPLL_PIXCLK_CNTL[] = {
+	 { "PHYPLL_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL_PHYPLL_PIXCLK", 4, 5, &umr_bitfield_default },
+	 { "PIXEL_RATE_PHYPLL_SEL", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DISP_CNTL_REG[] = {
+	 { "ALLOW_SR_ON_TRANS_REQ", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_LOWER_BASE_ADDRESS[] = {
+	 { "RIRB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "RIRB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION15[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_E[] = {
+	 { "DP_AUX_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG14[] = {
+	 { "DCIO_DIGG_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR14[] = {
+	 { "ATTR_CSEL1", 0, 1, &umr_bitfield_default },
+	 { "ATTR_CSEL2", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT14[] = {
+	 { "UNDRLN_LOC", 0, 4, &umr_bitfield_default },
+	 { "ADDR_CNT_BY4", 5, 5, &umr_bitfield_default },
+	 { "DOUBLE_WORD", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC0_PIXEL_RATE_CNTL[] = {
+	 { "CRTC0_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO0_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC0_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC0_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_PHASE[] = {
+	 { "DP_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_MODULO[] = {
+	 { "DP_DTO0_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC1_PIXEL_RATE_CNTL[] = {
+	 { "CRTC1_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO1_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO1_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_PHASE[] = {
+	 { "DP_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_MODULO[] = {
+	 { "DP_DTO1_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC2_PIXEL_RATE_CNTL[] = {
+	 { "CRTC2_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO2_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO2_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_PHASE[] = {
+	 { "DP_DTO2_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_MODULO[] = {
+	 { "DP_DTO2_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC3_PIXEL_RATE_CNTL[] = {
+	 { "CRTC3_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO3_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO3_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_PHASE[] = {
+	 { "DP_DTO3_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_MODULO[] = {
+	 { "DP_DTO3_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_UPPER_BASE_ADDRESS[] = {
+	 { "RIRB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION16[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_F[] = {
+	 { "DP_AUX_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG15[] = {
+	 { "DCIO_DEBUG15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT15[] = {
+	 { "V_BLANK_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC4_PIXEL_RATE_CNTL[] = {
+	 { "CRTC4_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO4_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO4_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_PHASE[] = {
+	 { "DP_DTO4_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_MODULO[] = {
+	 { "DP_DTO4_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC5_PIXEL_RATE_CNTL[] = {
+	 { "CRTC5_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO5_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO5_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_PHASE[] = {
+	 { "DP_DTO5_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_MODULO[] = {
+	 { "DP_DTO5_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_SOFT_RESET[] = {
+	 { "REFCLK_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "PCIE_REFCLK_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SOFT_RESET_DVO", 2, 2, &umr_bitfield_default },
+	 { "DVO_ENABLE_RST", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_DTO2_CLK_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DPREFCLK_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "AMCLK0_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "AMCLK1_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "P0PLL_CFG_IF_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "P1PLL_CFG_IF_SOFT_RESET", 15, 15, &umr_bitfield_default },
+	 { "P2PLL_CFG_IF_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "A0PLL_CFG_IF_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "A1PLL_CFG_IF_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "C0PLL_CFG_IF_SOFT_RESET", 19, 19, &umr_bitfield_default },
+	 { "C1PLL_CFG_IF_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "C2PLL_CFG_IF_SOFT_RESET", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRESPONSE_INTERRUPT_COUNT[] = {
+	 { "N_RESPONSE_INTERRUPT_COUNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_WRITE_POINTER[] = {
+	 { "RIRB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
+	 { "RIRB_WRITE_POINTER_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_G[] = {
+	 { "DP_AUX_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG16[] = {
+	 { "DCIO_DEBUG16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT16[] = {
+	 { "V_BLANK_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKA_CLOCK_ENABLE[] = {
+	 { "SYMCLKA_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_CTRL[] = {
+	 { "RESET_UC", 0, 0, &umr_bitfield_default },
+	 { "IGNORE_PWRMGT", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_IRQ_TO_UC", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_XIRQ_TO_UC", 3, 3, &umr_bitfield_default },
+	 { "DMCU_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DMCU_DYN_CLK_GATING_EN", 8, 8, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_STATUS[] = {
+	 { "UC_IN_RESET", 0, 0, &umr_bitfield_default },
+	 { "UC_IN_WAIT_MODE", 1, 1, &umr_bitfield_default },
+	 { "UC_IN_STOP_MODE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PC_START_ADDR[] = {
+	 { "PC_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "PC_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_START_ADDR[] = {
+	 { "FW_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_END_ADDR[] = {
+	 { "FW_END_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_END_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_ISR_START_ADDR[] = {
+	 { "FW_ISR_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_ISR_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_HI[] = {
+	 { "FW_CHECKSUM_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_LO[] = {
+	 { "FW_CHECKSUM_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_RAM_ACCESS_CTRL[] = {
+	 { "ERAM_WR_ADDR_AUTO_INC", 0, 0, &umr_bitfield_default },
+	 { "ERAM_RD_ADDR_AUTO_INC", 1, 1, &umr_bitfield_default },
+	 { "IRAM_WR_ADDR_AUTO_INC", 2, 2, &umr_bitfield_default },
+	 { "IRAM_RD_ADDR_AUTO_INC", 3, 3, &umr_bitfield_default },
+	 { "ERAM_HOST_ACCESS_EN", 4, 4, &umr_bitfield_default },
+	 { "IRAM_HOST_ACCESS_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_CTRL[] = {
+	 { "ERAM_WR_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_WR_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_WR_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_DATA[] = {
+	 { "ERAM_WR_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_CTRL[] = {
+	 { "ERAM_RD_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_RD_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_RD_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_DATA[] = {
+	 { "ERAM_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_CTRL[] = {
+	 { "IRAM_WR_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_DATA[] = {
+	 { "IRAM_WR_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_CTRL[] = {
+	 { "IRAM_RD_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKB_CLOCK_ENABLE[] = {
+	 { "SYMCLKB_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_DATA[] = {
+	 { "IRAM_RD_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_EVENT_TRIGGER[] = {
+	 { "GEN_SW_INT_TO_UC", 0, 0, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CODE", 16, 22, &umr_bitfield_default },
+	 { "GEN_UC_INTERNAL_INT_TO_HOST", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_INTERNAL_INT_STATUS[] = {
+	 { "UC_INT_IRQ_N_PIN", 0, 0, &umr_bitfield_default },
+	 { "UC_INT_XIRQ_N_PIN", 1, 1, &umr_bitfield_default },
+	 { "UC_INT_SOFTWARE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "UC_INT_ILLEGAL_OPCODE_TRAP", 3, 3, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_4", 4, 4, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_3", 5, 5, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_2", 6, 6, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_1", 7, 7, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "UC_INT_REAL_TIME_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5", 10, 10, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_3", 11, 11, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_2", 12, 12, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_1", 13, 13, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE", 14, 14, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_OVERFLOW", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_SS_INTERRUPT_CNTL_STATUS[] = {
+	 { "STATIC_SCREEN1_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_STATUS", 21, 21, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_STATUS[] = {
+	 { "ABM1_HG_READY_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "SCP_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "VBLANK1_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "VBLANK2_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "VBLANK3_INT_CLEAR", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_OCCURRED", 27, 27, &umr_bitfield_default },
+	 { "VBLANK4_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_OCCURRED", 28, 28, &umr_bitfield_default },
+	 { "VBLANK5_INT_CLEAR", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_OCCURRED", 29, 29, &umr_bitfield_default },
+	 { "VBLANK6_INT_CLEAR", 29, 29, &umr_bitfield_default },
+	 { "DCFEV0_VBLANK_INT_OCCURRED", 30, 30, &umr_bitfield_default },
+	 { "DCFEV0_VBLANK_INT_CLEAR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_HOST_EN_MASK[] = {
+	 { "ABM1_HG_READY_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "SCP_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_MASK", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK[] = {
+	 { "ABM1_HG_READY_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_TO_UC_EN", 29, 29, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_TO_UC_EN", 30, 30, &umr_bitfield_default },
+	 { "DCFEV0_VBLANK_INT_TO_UC_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[] = {
+	 { "ABM1_HG_READY_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_XIRQ_IRQ_SEL", 29, 29, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_XIRQ_IRQ_SEL", 30, 30, &umr_bitfield_default },
+	 { "DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DMCU_SCRATCH[] = {
+	 { "DMCU_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INT_CNT[] = {
+	 { "DMCU_ABM1_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default },
+	 { "DMCU_ABM1_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default },
+	 { "DMCU_ABM1_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[] = {
+	 { "DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS", 0, 1, &umr_bitfield_default },
+	 { "DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_CLK_GATING_CNTL[] = {
+	 { "UC_IRAM_RD_DELAY", 0, 2, &umr_bitfield_default },
+	 { "UC_ERAM_RD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "UC_RBBM_RD_CLK_GATING_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG1[] = {
+	 { "MASTER_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG2[] = {
+	 { "MASTER_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG3[] = {
+	 { "MASTER_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CMD_REG[] = {
+	 { "MASTER_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKC_CLOCK_ENABLE[] = {
+	 { "SYMCLKC_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CNTL_REG[] = {
+	 { "MASTER_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG1[] = {
+	 { "SLAVE_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG2[] = {
+	 { "SLAVE_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG3[] = {
+	 { "SLAVE_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CMD_REG[] = {
+	 { "SLAVE_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CNTL_REG[] = {
+	 { "SLAVE_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "COMM_PORT_MSG_TO_HOST_IN_PROGRESS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_INDEX[] = {
+	 { "DMCU_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMCU_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_DATA[] = {
+	 { "DMCU_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_AMBIENT_LIGHT_LEVEL[] = {
+	 { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_USER_LEVEL[] = {
+	 { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_TARGET_ABM_LEVEL[] = {
+	 { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_CURRENT_ABM_LEVEL[] = {
+	 { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_FINAL_DUTY_CYCLE[] = {
+	 { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_MINIMUM_DUTY_CYCLE[] = {
+	 { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_ABM_CNTL[] = {
+	 { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[] = {
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKD_CLOCK_ENABLE[] = {
+	 { "SYMCLKD_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_GRP2_REG_LOCK[] = {
+	 { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[] = {
+	 { "DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[] = {
+	 { "DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_STATUS1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED", 28, 28, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_CNTL[] = {
+	 { "ABM1_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default },
+	 { "ABM1_BLANK_MODE_SUPPORT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_IPCSC_COEFF_SEL[] = {
+	 { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_0[] = {
+	 { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_1[] = {
+	 { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_2[] = {
+	 { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_3[] = {
+	 { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_4[] = {
+	 { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_12[] = {
+	 { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKE_CLOCK_ENABLE[] = {
+	 { "SYMCLKE_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_34[] = {
+	 { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default },
+	 { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default },
+	 { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_CNTL_MISC[] = {
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default },
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS5[] = {
+	 { "DCFEV_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[] = {
+	 { "DCFEV_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_DEBUG_MISC[] = {
+	 { "ABM1_HG_FORCE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_FORCE_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "ABM1_BL_FORCE_INTERRUPT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HGLS_REG_READ_PROGRESS[] = {
+	 { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_MISC_CTRL[] = {
+	 { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default },
+	 { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default },
+	 { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default },
+	 { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default },
+	 { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default },
+	 { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SUM_OF_LUMA[] = {
+	 { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_PIXEL_COUNT[] = {
+	 { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKF_CLOCK_ENABLE[] = {
+	 { "SYMCLKF_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_OVR_SCAN_BIN[] = {
+	 { "ABM1_LS_OVR_SCAN_BIN", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_SAMPLE_RATE[] = {
+	 { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SAMPLE_RATE[] = {
+	 { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = {
+	 { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_1[] = {
+	 { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_2[] = {
+	 { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_3[] = {
+	 { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_4[] = {
+	 { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_5[] = {
+	 { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_6[] = {
+	 { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_7[] = {
+	 { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_8[] = {
+	 { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_9[] = {
+	 { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_10[] = {
+	 { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_11[] = {
+	 { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_12[] = {
+	 { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_13[] = {
+	 { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_14[] = {
+	 { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_15[] = {
+	 { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_16[] = {
+	 { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_17[] = {
+	 { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_18[] = {
+	 { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_19[] = {
+	 { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_20[] = {
+	 { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_21[] = {
+	 { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_22[] = {
+	 { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_23[] = {
+	 { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_24[] = {
+	 { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[] = {
+	 { "DCFEV_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFEV_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_OVERSCAN_PIXEL_VALUE[] = {
+	 { "ABM1_OVERSCAN_R_PIXEL_VALUE", 0, 9, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_G_PIXEL_VALUE", 10, 19, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_B_PIXEL_VALUE", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_BL_MASTER_LOCK[] = {
+	 { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_INDEX[] = {
+	 { "ABM_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "ABM_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_DATA[] = {
+	 { "ABM_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_ENABLE[] = {
+	 { "DVO_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DVO_PIXEL_WIDTH", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SOURCE_SELECT[] = {
+	 { "DVO_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DVO_STEREOSYNC_SELECT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_OUTPUT[] = {
+	 { "DVO_OUTPUT_ENABLE_MODE", 0, 1, &umr_bitfield_default },
+	 { "DVO_CLOCK_MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CONTROL[] = {
+	 { "DVO_RATE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "DVO_SDRCLK_SEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_DVPDATA_WIDTH", 4, 5, &umr_bitfield_default },
+	 { "DVO_DUAL_CHANNEL_EN", 8, 8, &umr_bitfield_default },
+	 { "DVO_RESET_FIFO", 16, 16, &umr_bitfield_default },
+	 { "DVO_SYNC_PHASE", 17, 17, &umr_bitfield_default },
+	 { "DVO_INVERT_DVOCLK", 18, 18, &umr_bitfield_default },
+	 { "DVO_HSYNC_POLARITY", 20, 20, &umr_bitfield_default },
+	 { "DVO_VSYNC_POLARITY", 21, 21, &umr_bitfield_default },
+	 { "DVO_DE_POLARITY", 22, 22, &umr_bitfield_default },
+	 { "DVO_COLOR_FORMAT", 24, 25, &umr_bitfield_default },
+	 { "DVO_CTL3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC_EN[] = {
+	 { "DVO_CRC2_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_MASK[] = {
+	 { "DVO_CRC2_SIG_MASK", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_RESULT[] = {
+	 { "DVO_CRC2_SIG_RESULT", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_FIFO_ERROR_STATUS[] = {
+	 { "DVO_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DVO_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DVO_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DVO_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DVO_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DVO_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DVO_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_TEST_DEBUG_INDEX[] = {
+	 { "DVO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DVO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_TEST_DEBUG_DATA[] = {
+	 { "DVO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_ENABLE[] = {
+	 { "DAC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_POINTER_SKEW", 2, 3, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR", 4, 4, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR_ACK", 5, 5, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_TVOUT_SIM", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SOURCE_SELECT[] = {
+	 { "DAC_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DAC_TV_SELECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_EN[] = {
+	 { "DAC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_CONT_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_CONTROL[] = {
+	 { "DAC_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_ONLY_BLANKB", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB_MASK[] = {
+	 { "DAC_CRC_SIG_BLUE_MASK", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN_MASK", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED_MASK", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL_MASK[] = {
+	 { "DAC_CRC_SIG_CONTROL_MASK", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO_SOURCE[] = {
+	 { "DCCG_AUDIO_DTO0_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_SOURCE_SEL", 12, 13, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_CLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_USE_512FBR_DTO", 20, 20, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO0_USE_512FBR_DTO", 24, 24, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO1_USE_512FBR_DTO", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB[] = {
+	 { "DAC_CRC_SIG_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL[] = {
+	 { "DAC_CRC_SIG_CONTROL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SYNC_TRISTATE_CONTROL[] = {
+	 { "DAC_HSYNCA_TRISTATE", 0, 0, &umr_bitfield_default },
+	 { "DAC_VSYNCA_TRISTATE", 8, 8, &umr_bitfield_default },
+	 { "DAC_SYNCA_TRISTATE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_STEREOSYNC_SELECT[] = {
+	 { "DAC_STEREOSYNC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL[] = {
+	 { "DAC_AUTODETECT_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_FRAME_TIME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CHECK_MASK", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL2[] = {
+	 { "DAC_AUTODETECT_POWERUP_COUNTER", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_TESTMODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL3[] = {
+	 { "DAC_AUTODET_COMPARATOR_IN_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODET_COMPARATOR_OUT_DELAY", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_STATUS[] = {
+	 { "DAC_AUTODETECT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CONNECT", 4, 4, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_RED_SENSE", 8, 9, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_GREEN_SENSE", 16, 17, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_BLUE_SENSE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_INT_CONTROL[] = {
+	 { "DAC_AUTODETECT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_INT_ENABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_OUTPUT_CNTL[] = {
+	 { "DAC_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_SEL", 8, 10, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_ON_BLANKB_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_DATA[] = {
+	 { "DAC_FORCE_DATA", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_POWERDOWN[] = {
+	 { "DAC_POWERDOWN", 0, 0, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_BLUE", 8, 8, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_GREEN", 16, 16, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_RED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CONTROL[] = {
+	 { "DAC_DFORCE_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_TV_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DAC_ZSCALE_SHIFT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_ENABLE[] = {
+	 { "DAC_COMP_DDET_REF_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMP_SDET_REF_EN", 8, 8, &umr_bitfield_default },
+	 { "DAC_R_ASYNC_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DAC_G_ASYNC_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "DAC_B_ASYNC_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_OUTPUT[] = {
+	 { "DAC_COMPARATOR_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_BLUE", 1, 1, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_GREEN", 2, 2, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_RED", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_PWR_CNTL[] = {
+	 { "DAC_BG_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_PWRCNTL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_PHASE[] = {
+	 { "DCCG_AUDIO_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_DFT_CONFIG[] = {
+	 { "DAC_DFT_CONFIG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FIFO_STATUS[] = {
+	 { "DAC_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DAC_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DAC_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DAC_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DAC_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DAC_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_TEST_DEBUG_INDEX[] = {
+	 { "DAC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DAC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_TEST_DEBUG_DATA[] = {
+	 { "DAC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK1_SEL[] = {
+	 { "DCDEBUG_BUS_CLK1_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK2_SEL[] = {
+	 { "DCDEBUG_BUS_CLK2_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK3_SEL[] = {
+	 { "DCDEBUG_BUS_CLK3_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK4_SEL[] = {
+	 { "DCDEBUG_BUS_CLK4_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK5_SEL[] = {
+	 { "DCDEBUG_BUS_CLK5_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_PIN_OVERRIDE[] = {
+	 { "DCDEBUG_OUT_OVERRIDE1_PIN_SEL", 0, 4, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL", 5, 9, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_EN", 12, 12, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_PIN_SEL", 15, 19, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL", 20, 24, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_CNTL[] = {
+	 { "DCDEBUG_BLOCK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_24BIT_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCDEBUG_CLK_SEL", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_DATA[] = {
+	 { "DCDEBUG_OUT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_MODULE[] = {
+	 { "DCCG_AUDIO_DTO0_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_CONTROL[] = {
+	 { "DC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_STATUS_RESET", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC_SELECT", 8, 10, &umr_bitfield_default },
+	 { "DC_I2C_TRANSACTION_COUNT", 20, 21, &umr_bitfield_default },
+	 { "DC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_ARBITRATION[] = {
+	 { "DC_I2C_SW_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "DC_I2C_NO_QUEUED_SW_GO", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_HW_XFER", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_SW_XFER", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_USE_I2C_REG_REQ", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_USING_I2C_REG", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_USE_I2C_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_DONE_USING_I2C_REG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_INTERRUPT_CONTROL[] = {
+	 { "DC_I2C_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_MASK", 10, 10, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_INT", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_ACK", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_MASK", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_INT", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_ACK", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_MASK", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_INT", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_ACK", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_INT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_ACK", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_MASK", 26, 26, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_INT", 27, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_ACK", 28, 28, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_MASK", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_SW_STATUS[] = {
+	 { "DC_I2C_SW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_ABORTED", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_SW_TIMEOUT", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_SW_INTERRUPTED", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_SW_BUFFER_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_SW_STOPPED_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK2", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK3", 15, 15, &umr_bitfield_default },
+	 { "DC_I2C_SW_REQ", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_HW_STATUS[] = {
+	 { "DC_I2C_DDC1_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_HW_STATUS[] = {
+	 { "DC_I2C_DDC2_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_HW_STATUS[] = {
+	 { "DC_I2C_DDC3_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_HW_STATUS[] = {
+	 { "DC_I2C_DDC4_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_HW_STATUS[] = {
+	 { "DC_I2C_DDC5_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_HW_STATUS[] = {
+	 { "DC_I2C_DDC6_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SPEED[] = {
+	 { "DC_I2C_DDC1_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SETUP[] = {
+	 { "DC_I2C_DDC1_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_PHASE[] = {
+	 { "DCCG_AUDIO_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SPEED[] = {
+	 { "DC_I2C_DDC2_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SETUP[] = {
+	 { "DC_I2C_DDC2_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SPEED[] = {
+	 { "DC_I2C_DDC3_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SETUP[] = {
+	 { "DC_I2C_DDC3_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SPEED[] = {
+	 { "DC_I2C_DDC4_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SETUP[] = {
+	 { "DC_I2C_DDC4_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SPEED[] = {
+	 { "DC_I2C_DDC5_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SETUP[] = {
+	 { "DC_I2C_DDC5_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SPEED[] = {
+	 { "DC_I2C_DDC6_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SETUP[] = {
+	 { "DC_I2C_DDC6_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION0[] = {
+	 { "DC_I2C_RW0", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK0", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP0", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT0", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION1[] = {
+	 { "DC_I2C_RW1", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK1", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START1", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION2[] = {
+	 { "DC_I2C_RW2", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK2", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START2", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP2", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION3[] = {
+	 { "DC_I2C_RW3", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK3", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START3", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP3", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT3", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DATA[] = {
+	 { "DC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_INDEX", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_HW_STATUS[] = {
+	 { "DC_I2C_DDCVGA_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_MODULE[] = {
+	 { "DCCG_AUDIO_DTO1_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SPEED[] = {
+	 { "DC_I2C_DDCVGA_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SETUP[] = {
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_EDID_DETECT_CTRL[] = {
+	 { "DC_I2C_EDID_DETECT_WAIT_TIME", 0, 15, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID", 20, 23, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_SEND_RESET", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_READ_REQUEST_INTERRUPT[] = {
+	 { "DC_I2C_DDC1_READ_REQUEST_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_INT", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_ACK", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_MASK", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_INT", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_ACK", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_INT", 9, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_ACK", 10, 10, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_MASK", 11, 11, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_INT", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_ACK", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_MASK", 15, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_INT", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_ACK", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_MASK", 19, 19, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_INT", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_ACK", 22, 22, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_MASK", 23, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_INT", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_ACK", 26, 26, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_MASK", 27, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC_READ_REQUEST_ACK_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC_READ_REQUEST_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_CONTROL[] = {
+	 { "GENERIC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_INTERRUPT_CONTROL[] = {
+	 { "GENERIC_I2C_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_INT", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_ACK", 10, 10, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_MASK", 11, 11, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_STATUS[] = {
+	 { "GENERIC_I2C_STATUS", 0, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_ABORTED", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOPPED_ON_NACK", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_NACK", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SPEED[] = {
+	 { "GENERIC_I2C_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SETUP[] = {
+	 { "GENERIC_I2C_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "GENERIC_I2C_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_TRANSACTION[] = {
+	 { "GENERIC_I2C_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "GENERIC_I2C_ACK_ON_READ", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_START", 12, 12, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP", 13, 13, &umr_bitfield_default },
+	 { "GENERIC_I2C_COUNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_DATA[] = {
+	 { "GENERIC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX", 16, 19, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_SELECTION[] = {
+	 { "GENERIC_I2C_SCL_PIN_SEL", 0, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_PIN_SEL", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_DEBUG[] = {
+	 { "GENERIC_I2C_SCL_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_INPUT", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_EN", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_OUTPUT", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_INPUT", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_H[] = {
+	 { "DP_AUX_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG17[] = {
+	 { "DCIO_DEBUG17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_STATUS[] = {
+	 { "RESPONSE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "RESPONSE_OVERRUN_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_SIZE[] = {
+	 { "RIRB_SIZE", 0, 1, &umr_bitfield_default },
+	 { "RIRB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT17[] = {
+	 { "RA0_AS_A13B", 0, 0, &umr_bitfield_default },
+	 { "RA1_AS_A14B", 1, 1, &umr_bitfield_default },
+	 { "VCOUNT_BY2", 2, 2, &umr_bitfield_default },
+	 { "ADDR_CNT_BY2", 3, 3, &umr_bitfield_default },
+	 { "WRAP_A15TOA0", 5, 5, &umr_bitfield_default },
+	 { "BYTE_MODE", 6, 6, &umr_bitfield_default },
+	 { "CRTC_SYNC_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFCOUNTER_CNTL[] = {
+	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
+	 { "PERFCOUNTER_INC_MODE", 12, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_HW_CNTL_SEL", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_RUNEN_MODE", 15, 15, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTOFF_SEL", 16, 20, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTOFF_START_DIS", 21, 21, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESTART_EN", 22, 22, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT_EN", 23, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_OFF_MASK", 24, 24, &umr_bitfield_default },
+	 { "PERFCOUNTER_ACTIVE", 25, 25, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT_TYPE", 26, 26, &umr_bitfield_default },
+	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 27, 27, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED0[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_REF_DIV[] = {
+	 { "PLL_REF_DIV", 0, 9, &umr_bitfield_default },
+	 { "PLL_CALIBRATION_REF_DIV", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED1[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_FB_DIV[] = {
+	 { "PLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "PLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PLL_FB_DIV", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED2[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_POST_DIV[] = {
+	 { "PLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "PLL_POST_DIV1P5_DISPCLK", 7, 7, &umr_bitfield_default },
+	 { "PLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "PLL_POST_DIV1P5_DPREFCLK", 15, 15, &umr_bitfield_default },
+	 { "PLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED3[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_SS_AMOUNT_DSFRAC[] = {
+	 { "PLL_SS_AMOUNT_DSFRAC", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED4[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_SS_CNTL[] = {
+	 { "PLL_SS_AMOUNT_FBDIV", 0, 7, &umr_bitfield_default },
+	 { "PLL_SS_AMOUNT_NFRAC_SLIP", 8, 11, &umr_bitfield_default },
+	 { "PLL_SS_EN", 12, 12, &umr_bitfield_default },
+	 { "PLL_SS_MODE", 13, 13, &umr_bitfield_default },
+	 { "PLL_SS_STEP_SIZE_DSFRAC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED5[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_DS_CNTL[] = {
+	 { "PLL_DS_FRAC", 0, 15, &umr_bitfield_default },
+	 { "PLL_DS_ORDER", 16, 17, &umr_bitfield_default },
+	 { "PLL_DS_MODE", 18, 18, &umr_bitfield_default },
+	 { "PLL_DS_PRBS_EN", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED6[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_IDCLK_CNTL[] = {
+	 { "PLL_LTDP_IDCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "PLL_LTDP_IDCLK_DIFF_EN", 1, 1, &umr_bitfield_default },
+	 { "PLL_TMDP_IDCLK_EN", 2, 2, &umr_bitfield_default },
+	 { "PLL_TMDP_IDCLK_DIFF_EN", 3, 3, &umr_bitfield_default },
+	 { "PLL_IDCLK_EN", 4, 4, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV_RESET", 8, 8, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV_SELECT", 12, 12, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV", 16, 19, &umr_bitfield_default },
+	 { "PLL_CUR_LTDP", 20, 21, &umr_bitfield_default },
+	 { "PLL_CUR_PREDRV", 22, 23, &umr_bitfield_default },
+	 { "PLL_CUR_TMDP", 24, 25, &umr_bitfield_default },
+	 { "PLL_CML_A_DRVSTR", 26, 27, &umr_bitfield_default },
+	 { "PLL_CML_B_DRVSTR", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED7[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_CNTL[] = {
+	 { "PLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "PLL_POWER_DOWN", 1, 1, &umr_bitfield_default },
+	 { "PLL_BYPASS_CAL", 2, 2, &umr_bitfield_default },
+	 { "PLL_POST_DIV_SRC", 3, 3, &umr_bitfield_default },
+	 { "PLL_VCOREF", 4, 5, &umr_bitfield_default },
+	 { "PLL_PCIE_REFCLK_SEL", 6, 6, &umr_bitfield_default },
+	 { "PLL_ANTIGLITCH_RESETB", 7, 7, &umr_bitfield_default },
+	 { "PLL_CALREF", 8, 9, &umr_bitfield_default },
+	 { "PLL_CAL_BYPASS_REFDIV", 10, 10, &umr_bitfield_default },
+	 { "PLL_REFCLK_SEL", 11, 12, &umr_bitfield_default },
+	 { "PLL_ANTI_GLITCH_RESET", 13, 13, &umr_bitfield_default },
+	 { "PLL_XOCLK_DRV_R_EN", 14, 14, &umr_bitfield_default },
+	 { "PLL_REF_DIV_SRC", 16, 18, &umr_bitfield_default },
+	 { "PLL_LOCK_FREQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "PLL_CALIB_DONE", 20, 20, &umr_bitfield_default },
+	 { "PLL_LOCKED", 21, 21, &umr_bitfield_default },
+	 { "PLL_REFCLK_RECV_EN", 22, 22, &umr_bitfield_default },
+	 { "PLL_REFCLK_RECV_SEL", 23, 23, &umr_bitfield_default },
+	 { "PLL_TIMING_MODE_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PLL_DIG_SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED8[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_ANALOG[] = {
+	 { "PLL_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "PLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "PLL_CP", 8, 11, &umr_bitfield_default },
+	 { "PLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "PLL_VREG_FB_TRIM", 21, 23, &umr_bitfield_default },
+	 { "PLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED9[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_VREG_CNTL[] = {
+	 { "PLL_VREG_CNTL", 0, 19, &umr_bitfield_default },
+	 { "PLL_BG_VREG_BIAS", 20, 21, &umr_bitfield_default },
+	 { "PLL_VREF_SEL", 26, 26, &umr_bitfield_default },
+	 { "PLL_VREG_BIAS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED10[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UNLOCK_DETECT_CNTL[] = {
+	 { "PLL_UNLOCK_DETECT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PLL_UNLOCK_DET_RES100_SELECT", 1, 1, &umr_bitfield_default },
+	 { "PLL_UNLOCK_STICKY_STATUS", 2, 2, &umr_bitfield_default },
+	 { "PLL_UNLOCK_DET_COUNT", 4, 6, &umr_bitfield_default },
+	 { "PLL_UNLOCKED_STICKY_RST_TEST", 7, 7, &umr_bitfield_default },
+	 { "PLL_UNLOCKED_STICKY_TEST_READBACK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED11[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_DEBUG_CNTL[] = {
+	 { "PLL_DEBUG_SIGNALS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PLL_DEBUG_MUXOUT_SEL", 4, 7, &umr_bitfield_default },
+	 { "PLL_DEBUG_CLK_SEL", 8, 12, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_CNTL", 16, 23, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_READBACK", 24, 26, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED12[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UPDATE_LOCK[] = {
+	 { "PLL_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED13[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UPDATE_CNTL[] = {
+	 { "PLL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "PLL_UPDATE_POINT", 8, 8, &umr_bitfield_default },
+	 { "PLL_AUTO_RESET_DISABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED14[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED15[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFCOUNTER_STATE[] = {
+	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED16[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_XOR_LOCK[] = {
+	 { "PLL_XOR_LOCK", 0, 0, &umr_bitfield_default },
+	 { "PLL_XOR_LOCK_READBACK", 1, 1, &umr_bitfield_default },
+	 { "PLL_SPARE", 8, 13, &umr_bitfield_default },
+	 { "PLL_LOCK_COUNT_SEL", 16, 19, &umr_bitfield_default },
+	 { "PLL_LOCK_DETECTOR_RESOLUTION_FREF", 20, 22, &umr_bitfield_default },
+	 { "PLL_LOCK_DETECTOR_RESOLUTION_FFB", 23, 25, &umr_bitfield_default },
+	 { "PLL_LOCK_DETECTOR_OPAMP_BIAS", 26, 27, &umr_bitfield_default },
+	 { "PLL_FAST_LOCK_MODE_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED17[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_ANALOG_CNTL[] = {
+	 { "PLL_ANALOG_TEST_EN", 0, 0, &umr_bitfield_default },
+	 { "PLL_ANALOG_MUX_CNTL", 1, 4, &umr_bitfield_default },
+	 { "PLL_ANALOGOUT_MUX_CNTL", 5, 8, &umr_bitfield_default },
+	 { "PLL_REGREF_TRIM", 9, 13, &umr_bitfield_default },
+	 { "PLL_CALIB_FBDIV", 14, 16, &umr_bitfield_default },
+	 { "PLL_CALIB_FASTCAL", 17, 17, &umr_bitfield_default },
+	 { "PLL_TEST_SSAMP_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED18[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_REF_DIV[] = {
+	 { "VGA25_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED19[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_REF_DIV[] = {
+	 { "VGA28_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED20[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_REF_DIV[] = {
+	 { "VGA41_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED21[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_FB_DIV[] = {
+	 { "VGA25_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA25_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA25_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED22[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_FB_DIV[] = {
+	 { "VGA28_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA28_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA28_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED23[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_FB_DIV[] = {
+	 { "VGA41_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA41_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA41_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED24[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_POST_DIV[] = {
+	 { "VGA25_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA25_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA25_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED25[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_POST_DIV[] = {
+	 { "VGA28_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA28_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA28_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED26[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_POST_DIV[] = {
+	 { "VGA41_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA41_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA41_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED27[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_ANALOG[] = {
+	 { "VGA25_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA25_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA25_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA25_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA25_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED28[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_ANALOG[] = {
+	 { "VGA28_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA28_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA28_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA28_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA28_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED29[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_ANALOG[] = {
+	 { "VGA41_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA41_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA41_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA41_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA41_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED30[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPPLL_BG_CNTL[] = {
+	 { "DISPPLL_BG_PDN", 0, 0, &umr_bitfield_default },
+	 { "DISPPLL_BG_ADJ", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED31[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_DIV_UPDATE_DEBUG[] = {
+	 { "PLL_REF_DIV_CHANGED", 0, 0, &umr_bitfield_default },
+	 { "PLL_FB_DIV_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "PLL_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "PLL_UPDATE_CURRENT_STATE", 3, 4, &umr_bitfield_default },
+	 { "PLL_UPDATE_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "PLL_UPDATE_REQ", 6, 6, &umr_bitfield_default },
+	 { "PLL_UPDATE_ACK", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CVALUE_INT_MISC[] = {
+	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
+	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED32[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_STATUS_DEBUG[] = {
+	 { "PLL_DEBUG_BUS", 0, 15, &umr_bitfield_default },
+	 { "PLL_UNLOCK", 16, 16, &umr_bitfield_default },
+	 { "PLL_CAL_RESULT", 17, 20, &umr_bitfield_default },
+	 { "PLL_POWERGOOD_ISO_ENB", 24, 24, &umr_bitfield_default },
+	 { "PLL_POWERGOOD_S", 25, 25, &umr_bitfield_default },
+	 { "PLL_POWERGOOD_V", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[] = {
+	 { "SUBSYSTEM_ID_BYTE1", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED33[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_DEBUG_MUX_CNTL[] = {
+	 { "DEBUG_BUS_MUX_SEL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[] = {
+	 { "SUBSYSTEM_ID_BYTE2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED34[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_SPARE0[] = {
+	 { "PLL_SPARE0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[] = {
+	 { "SUBSYSTEM_ID_BYTE3", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED35[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_SPARE1[] = {
+	 { "PLL_SPARE1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED36[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED37[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED38[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED39[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED40[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED41[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
+	 { "PERFMON_RUN_ENABLE_SEL", 2, 7, &umr_bitfield_default },
+	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CVALUE_LOW[] = {
+	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_HI[] = {
+	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
+	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_LOW[] = {
+	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_TEST_DEBUG_INDEX[] = {
+	 { "PERFMON_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "PERFMON_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_TEST_DEBUG_DATA[] = {
+	 { "PERFMON_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_INDEX[] = {
+	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_DATA[] = {
+	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CNTL2[] = {
+	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
+	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
+	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
+	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_INDEX[] = {
+	 { "DCCG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCCG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_DATA[] = {
+	 { "DCCG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_CLK_SEL[] = {
+	 { "DCCG_TEST_CLK_GENERICA_SEL", 0, 8, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICA_INV", 12, 12, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_SEL", 16, 24, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_INV", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_CLOCK_GATING[] = {
+	 { "ENABLE_CLOCK_GATING", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO[] = {
+	 { "AZALIA_AUDIO_DTO_PHASE", 0, 15, &umr_bitfield_default },
+	 { "AZALIA_AUDIO_DTO_MODULE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO_CONTROL[] = {
+	 { "AZALIA_AUDIO_FORCE_DTO", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_SCLK_CONTROL[] = {
+	 { "AUDIO_SCLK_CONTROL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_UNDERFLOW_FILLER_SAMPLE[] = {
+	 { "AZALIA_UNDERFLOW_FILLER_SAMPLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_DATA_DMA_CONTROL[] = {
+	 { "DATA_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+	 { "INPUT_DATA_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default },
+	 { "DATA_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "INPUT_DATA_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default },
+	 { "AZALIA_IOC_GENERATION_METHOD", 16, 16, &umr_bitfield_default },
+	 { "AZALIA_UNDERFLOW_CONTROL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_BDL_DMA_CONTROL[] = {
+	 { "BDL_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+	 { "INPUT_BDL_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default },
+	 { "BDL_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "INPUT_BDL_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_RIRB_AND_DP_CONTROL[] = {
+	 { "RIRB_NON_SNOOP", 0, 0, &umr_bitfield_default },
+	 { "DP_DMA_NON_SNOOP", 4, 4, &umr_bitfield_default },
+	 { "DP_UPDATE_FREQ_DIVIDER", 5, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CORB_DMA_CONTROL[] = {
+	 { "CORB_DMA_NON_SNOOP", 0, 0, &umr_bitfield_default },
+	 { "CORB_DMA_ISOCHRONOUS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[] = {
+	 { "APPLICATION_POSITION_IN_CYCLIC_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CYCLIC_BUFFER_SYNC[] = {
+	 { "CYCLIC_BUFFER_SYNC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_GLOBAL_CAPABILITIES[] = {
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+	 { "OUTSTRMPAY", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[] = {
+	 { "LATENCY_HIDING_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "SYS_MEM_ACTIVE_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "INPUT_LATENCY_HIDING_LEVEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_PAYLOAD_CAPABILITY[] = {
+	 { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+	 { "INSTRMPAY", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_DEBUG[] = {
+	 { "CONTROLLER_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL0[] = {
+	 { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL1[] = {
+	 { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL2[] = {
+	 { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL3[] = {
+	 { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_RESULT[] = {
+	 { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[] = {
+	 { "IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD", 0, 27, &umr_bitfield_default },
+	 { "IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_I[] = {
+	 { "DP_AUX_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG18[] = {
+	 { "DCIO_DEBUG18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT18[] = {
+	 { "LINE_CMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL0[] = {
+	 { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL1[] = {
+	 { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL2[] = {
+	 { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL3[] = {
+	 { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_RESULT[] = {
+	 { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL0[] = {
+	 { "CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL1[] = {
+	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL2[] = {
+	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL3[] = {
+	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_RESULT[] = {
+	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL0[] = {
+	 { "CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL1[] = {
+	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL2[] = {
+	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL3[] = {
+	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_RESULT[] = {
+	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_MEM_PWR_CTRL[] = {
+	 { "AZ_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "AZ_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "AZ_MEM_PWR_MODE_SEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_MEM_PWR_STATUS[] = {
+	 { "AZ_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_PG_DEBUG_CONFIG[] = {
+	 { "DCI_PG_DBG_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_INDEX[] = {
+	 { "AZ_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZ_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_DATA[] = {
+	 { "AZ_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[] = {
+	 { "HBR_CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "COMPRESSED_CHANNEL_COUNT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[] = {
+	 { "RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[] = {
+	 { "PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[] = {
+	 { "INPUT_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
+	 { "INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_DEBUG[] = {
+	 { "DISABLE_FORMAT_COMPARISON", 0, 5, &umr_bitfield_default },
+	 { "CODEC_DEBUG", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET0[] = {
+	 { "GTC_GROUP_OFFSET0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET1[] = {
+	 { "GTC_GROUP_OFFSET1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET2[] = {
+	 { "GTC_GROUP_OFFSET2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET3[] = {
+	 { "GTC_GROUP_OFFSET3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET4[] = {
+	 { "GTC_GROUP_OFFSET4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET5[] = {
+	 { "GTC_GROUP_OFFSET5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET6[] = {
+	 { "GTC_GROUP_OFFSET6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH0[] = {
+	 { "DCO_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH1[] = {
+	 { "DCO_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH2[] = {
+	 { "DCO_SCRATCH2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH3[] = {
+	 { "DCO_SCRATCH3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH4[] = {
+	 { "DCO_SCRATCH4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH5[] = {
+	 { "DCO_SCRATCH5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH6[] = {
+	 { "DCO_SCRATCH6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH7[] = {
+	 { "DCO_SCRATCH7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCE_VCE_CONTROL[] = {
+	 { "DC_VCE_VIDEO_PIPE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DC_VCE_AUDIO_STREAM_SELECT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS[] = {
+	 { "SCL_DISP1_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D1BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D1_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D1_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC1_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC1_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC1_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGA_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD1_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX1_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX1_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DACA_AUTODETECT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DACB_AUTODETECT_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_HW_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DMCU_UC_INTERNAL_INT", 26, 26, &umr_bitfield_default },
+	 { "DMCU_SCP_INT", 27, 27, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT", 28, 28, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT", 29, 29, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE[] = {
+	 { "SCL_DISP2_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D2BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D2_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D2_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC2_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC2_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC2_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGB_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD2_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX2_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX2_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "LB_D1_VLINE2_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "LB_D2_VLINE2_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "LB_D3_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE2[] = {
+	 { "SCL_DISP3_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D3BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D3_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D3_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC3_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC3_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC3_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGC_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD3_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX3_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX3_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "LB_D4_VLINE2_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "LB_D5_VLINE2_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "LB_D6_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE3[] = {
+	 { "SCL_DISP4_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D4BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D4_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D4_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC4_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC4_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC4_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGD_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD4_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX4_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX4_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "BUFMGR_IHIF_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "WBSCL_HOST_CONFLICT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "WBSCL_DATA_OVERFLOW_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE4", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE4[] = {
+	 { "SCL_DISP5_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D5BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D5_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D5_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC5_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC5_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC5_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGE_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD5_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX5_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX5_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE5", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE5[] = {
+	 { "SCL_DISP6_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D6BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D6_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D6_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC6_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC6_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC6_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC6_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC6_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGF_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD6_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX6_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX6_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT0", 25, 25, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT1", 26, 26, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT2", 27, 27, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE6", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE6[] = {
+	 { "DCRX_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "BUFMGR_CWB0_IHIF_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "BUFMGR_CWB1_IHIF_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGG_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "AUX1_GTC_SYNC_ERROR_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX2_GTC_SYNC_ERROR_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "AUX3_GTC_SYNC_ERROR_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "AUX4_GTC_SYNC_ERROR_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "AUX5_GTC_SYNC_ERROR_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "AUX6_GTC_SYNC_ERROR_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE7[] = {
+	 { "DCCG_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER0_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INTERRUPT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE8", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE8[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INTERRUPT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE9", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE9[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE10", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_STATUS[] = {
+	 { "I2C_MEM_PWR_STATE", 0, 0, &umr_bitfield_default },
+	 { "MVP_MEM_PWR_STATE", 2, 2, &umr_bitfield_default },
+	 { "DPA_MEM_PWR_STATE", 3, 3, &umr_bitfield_default },
+	 { "DPB_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "DPC_MEM_PWR_STATE", 5, 5, &umr_bitfield_default },
+	 { "DPD_MEM_PWR_STATE", 6, 6, &umr_bitfield_default },
+	 { "DPE_MEM_PWR_STATE", 7, 7, &umr_bitfield_default },
+	 { "DPF_MEM_PWR_STATE", 8, 8, &umr_bitfield_default },
+	 { "DPG_MEM_PWR_STATE", 9, 9, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_CTRL[] = {
+	 { "I2C_LIGHT_SLEEP_FORCE", 0, 0, &umr_bitfield_default },
+	 { "I2C_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default },
+	 { "MVP_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DPA_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DPB_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DPC_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DPD_LIGHT_SLEEP_DIS", 7, 7, &umr_bitfield_default },
+	 { "DPE_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DPF_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
+	 { "DPG_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_FORCE", 14, 15, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_DIS", 19, 19, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_FORCE", 23, 24, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_DIS", 25, 25, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_FORCE", 26, 27, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_DIS", 28, 28, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_FORCE", 29, 30, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_CTRL2[] = {
+	 { "HDMI_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
+	 { "DPLPA_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "DPLPB_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HDMILP0_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
+	 { "HDMILP0_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
+	 { "HDMILP1_MEM_PWR_FORCE", 19, 20, &umr_bitfield_default },
+	 { "HDMILP1_MEM_PWR_DIS", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL[] = {
+	 { "DISPCLK_R_DCO_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_G_ABM_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_G_DVO_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_DACA_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_DACB_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "REFCLK_R_DCO_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGLPA_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGLPB_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGA_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGB_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGC_GATE_DIS", 26, 26, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGD_GATE_DIS", 27, 27, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGE_GATE_DIS", 28, 28, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGF_GATE_DIS", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGG_GATE_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_CNTL[] = {
+	 { "DPDBG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DPDBG_INPUT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DPDBG_SYMCLK_ON", 4, 4, &umr_bitfield_default },
+	 { "DPDBG_ERROR_DETECTION_MODE", 8, 8, &umr_bitfield_default },
+	 { "DPDBG_LINE_LENGTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_INTERRUPT[] = {
+	 { "DPDBG_FIFO_OVERFLOW_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_TYPE", 1, 1, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_POWER_MANAGEMENT_CNTL[] = {
+	 { "PM_ASSERT_RESET", 0, 0, &umr_bitfield_default },
+	 { "PM_ALL_BUSY_OFF", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_SOFT_RESET_2[] = {
+	 { "DIGLPA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DIGLPA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DIGLPB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DIGLPB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_STEREOSYNC_SEL[] = {
+	 { "GENERICA_STEREOSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "GENERICB_STEREOSYNC_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_TEST_DEBUG_INDEX[] = {
+	 { "DCO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_TEST_DEBUG_DATA[] = {
+	 { "DCO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SOFT_RESET[] = {
+	 { "DACA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "I2S0_SPDIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "I2S1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "SPDIF1_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DB_CLK_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "FMT0_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "FMT1_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FMT2_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "FMT3_SOFT_RESET", 19, 19, &umr_bitfield_default },
+	 { "FMT4_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "FMT5_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "MVP_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "ABM_SOFT_RESET", 25, 25, &umr_bitfield_default },
+	 { "DVO_SOFT_RESET", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_SOFT_RESET[] = {
+	 { "DIGA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DIGA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DIGB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DIGB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIGC_FE_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DIGC_BE_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DIGD_FE_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DIGD_BE_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DIGE_FE_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "DIGE_BE_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "DIGF_FE_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "DIGF_BE_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "DIGG_FE_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "DIGG_BE_SOFT_RESET", 25, 25, &umr_bitfield_default },
+	 { "DPDBG_SOFT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_STATUS1[] = {
+	 { "DPLPA_MEM_PWR_STATE", 0, 0, &umr_bitfield_default },
+	 { "DPLPB_MEM_PWR_STATE", 1, 1, &umr_bitfield_default },
+	 { "HDMILP0_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "HDMILP1_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE10[] = {
+	 { "DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL2[] = {
+	 { "DCO_TEST_CLK_SEL", 0, 6, &umr_bitfield_default },
+	 { "SCLK_G_AFMTA_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "SCLK_G_AFMTB_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "SCLK_G_AFMTC_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "SCLK_G_AFMTD_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "SCLK_G_AFMTE_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "SCLK_G_AFMTF_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "SCLK_G_AFMTG_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "SCLK_G_AFMTLPA_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "SCLK_G_AFMTLPB_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "SYMCLKA_FE_G_AFMT_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "SYMCLKB_FE_G_AFMT_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "SYMCLKC_FE_G_AFMT_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "SYMCLKD_FE_G_AFMT_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "SYMCLKE_FE_G_AFMT_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "SYMCLKF_FE_G_AFMT_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "SYMCLKG_FE_G_AFMT_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "SYMCLKLPA_FE_G_AFMT_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "SYMCLKLPB_FE_G_AFMT_GATE_DIS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL3[] = {
+	 { "SYMCLKA_FE_G_TMDS_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_G_TMDS_GATE_DIS", 1, 1, &umr_bitfield_default },
+	 { "SYMCLKC_FE_G_TMDS_GATE_DIS", 2, 2, &umr_bitfield_default },
+	 { "SYMCLKD_FE_G_TMDS_GATE_DIS", 3, 3, &umr_bitfield_default },
+	 { "SYMCLKE_FE_G_TMDS_GATE_DIS", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_G_TMDS_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "SYMCLKG_FE_G_TMDS_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "SYMCLKLPA_FE_G_TMDS_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "SYMCLKLPB_FE_G_TMDS_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "SYMCLKA_G_TMDS_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "SYMCLKB_G_TMDS_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "SYMCLKC_G_TMDS_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "SYMCLKD_G_TMDS_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "SYMCLKE_G_TMDS_GATE_DIS", 14, 14, &umr_bitfield_default },
+	 { "SYMCLKF_G_TMDS_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "SYMCLKG_G_TMDS_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "SYMCLKLPA_G_TMDS_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "SYMCLKLPB_G_TMDS_GATE_DIS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_INT_STATUS[] = {
+	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_INT_CONTROL[] = {
+	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_CONTROL[] = {
+	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[] = {
+	 { "IMMEDIATE_RESPONSE_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_J[] = {
+	 { "DP_AUX_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG19[] = {
+	 { "DCIO_DIGLPA_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_STATUS[] = {
+	 { "IMMEDIATE_COMMAND_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IMMEDIATE_RESULT_VALID", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_K[] = {
+	 { "DP_AUX_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1A[] = {
+	 { "DCIO_DIGLPB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_ENABLE[] = {
+	 { "GRPH_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_KEYER_ALPHA_SEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_CONTROL[] = {
+	 { "GRPH_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "GRPH_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "GRPH_Z", 4, 5, &umr_bitfield_default },
+	 { "GRPH_BANK_WIDTH", 6, 7, &umr_bitfield_default },
+	 { "GRPH_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "GRPH_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "GRPH_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT", 18, 19, &umr_bitfield_default },
+	 { "GRPH_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "GRPH_PIPE_CONFIG", 24, 28, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE", 29, 30, &umr_bitfield_default },
+	 { "GRPH_COLOR_EXPANSION_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_LUT_10BIT_BYPASS[] = {
+	 { "GRPH_LUT_10BIT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SWAP_CNTL[] = {
+	 { "GRPH_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "GRPH_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "GRPH_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+	 { "GRPH_ALPHA_CROSSBAR", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PRIMARY_SURFACE_ADDRESS[] = {
+	 { "GRPH_PRIMARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SECONDARY_SURFACE_ADDRESS[] = {
+	 { "GRPH_SECONDARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PITCH[] = {
+	 { "GRPH_PITCH", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_OFFSET_X[] = {
+	 { "GRPH_SURFACE_OFFSET_X", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_OFFSET_Y[] = {
+	 { "GRPH_SURFACE_OFFSET_Y", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_X_START[] = {
+	 { "GRPH_X_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_Y_START[] = {
+	 { "GRPH_Y_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_X_END[] = {
+	 { "GRPH_X_END", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_Y_END[] = {
+	 { "GRPH_Y_END", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_COUNTER_CONTROL[] = {
+	 { "GRPH_SURFACE_COUNTER_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SURFACE_COUNTER_EVENT_SELECT", 1, 4, &umr_bitfield_default },
+	 { "GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_CONTROL[] = {
+	 { "GRPH_INPUT_GAMMA_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_UPDATE[] = {
+	 { "GRPH_MODE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "GRPH_MODE_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_TAKEN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_SURFACE_XDMA_PENDING_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "GRPH_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SURFACE_IGNORE_UPDATE_LOCK", 20, 20, &umr_bitfield_default },
+	 { "GRPH_MODE_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_FLIP_CONTROL[] = {
+	 { "GRPH_SURFACE_UPDATE_H_RETRACE_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_XDMA_SUPER_AA_EN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_IMMEDIATE_EN", 4, 4, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING_MODE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_ADDRESS_INUSE[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_DFQ_CONTROL[] = {
+	 { "GRPH_DFQ_RESET", 0, 0, &umr_bitfield_default },
+	 { "GRPH_DFQ_SIZE", 4, 6, &umr_bitfield_default },
+	 { "GRPH_DFQ_MIN_FREE_ENTRIES", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_DFQ_STATUS[] = {
+	 { "GRPH_PRIMARY_DFQ_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_DFQ_NUM_ENTRIES", 4, 7, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_INTERRUPT_STATUS[] = {
+	 { "GRPH_PFLIP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_INTERRUPT_CONTROL[] = {
+	 { "GRPH_PFLIP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_SURFACE_ADDRESS[] = {
+	 { "GRPH_COMPRESS_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_PITCH[] = {
+	 { "GRPH_COMPRESS_PITCH", 6, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT[] = {
+	 { "GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_COUNTER_OUTPUT[] = {
+	 { "GRPH_SURFACE_COUNTER_MIN", 0, 15, &umr_bitfield_default },
+	 { "GRPH_SURFACE_COUNTER_MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_GRPH_CONTROL[] = {
+	 { "GRPH_PRESCALE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_R_SIGN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_G_SIGN", 2, 2, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_B_SIGN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_BYPASS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_R[] = {
+	 { "GRPH_PRESCALE_BIAS_R", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_G[] = {
+	 { "GRPH_PRESCALE_BIAS_G", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_B[] = {
+	 { "GRPH_PRESCALE_BIAS_B", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_CONTROL[] = {
+	 { "INPUT_CSC_GRPH_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12[] = {
+	 { "INPUT_CSC_C11", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14[] = {
+	 { "INPUT_CSC_C13", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22[] = {
+	 { "INPUT_CSC_C21", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24[] = {
+	 { "INPUT_CSC_C23", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32[] = {
+	 { "INPUT_CSC_C31", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34[] = {
+	 { "INPUT_CSC_C33", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_CONTROL[] = {
+	 { "OUTPUT_CSC_GRPH_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12[] = {
+	 { "OUTPUT_CSC_C11", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14[] = {
+	 { "OUTPUT_CSC_C13", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22[] = {
+	 { "OUTPUT_CSC_C21", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24[] = {
+	 { "OUTPUT_CSC_C23", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32[] = {
+	 { "OUTPUT_CSC_C31", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34[] = {
+	 { "OUTPUT_CSC_C33", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXA_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXA_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXA_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXA_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXA_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXA_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXB_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXB_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXB_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXB_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXB_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXB_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CONTROL[] = {
+	 { "DENORM_MODE", 0, 2, &umr_bitfield_default },
+	 { "DENORM_14BIT_OUT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_ROUND_CONTROL[] = {
+	 { "OUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_R_CR[] = {
+	 { "OUT_CLAMP_MAX_R_CR", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_R_CR", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_CONTROL[] = {
+	 { "KEY_MODE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_ALPHA[] = {
+	 { "KEY_ALPHA_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_ALPHA_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_RED[] = {
+	 { "KEY_RED_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_RED_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_GREEN[] = {
+	 { "KEY_GREEN_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_GREEN_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_BLUE[] = {
+	 { "KEY_BLUE_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_BLUE_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEGAMMA_CONTROL[] = {
+	 { "GRPH_DEGAMMA_MODE", 0, 1, &umr_bitfield_default },
+	 { "CURSOR2_DEGAMMA_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_DEGAMMA_MODE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_CONTROL[] = {
+	 { "GRPH_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C11_C12[] = {
+	 { "GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C13_C14[] = {
+	 { "GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C21_C22[] = {
+	 { "GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C23_C24[] = {
+	 { "GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C31_C32[] = {
+	 { "GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C33_C34[] = {
+	 { "GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_SPATIAL_DITHER_CNTL[] = {
+	 { "DCP_SPATIAL_DITHER_EN", 0, 0, &umr_bitfield_default },
+	 { "DCP_SPATIAL_DITHER_MODE", 4, 5, &umr_bitfield_default },
+	 { "DCP_SPATIAL_DITHER_DEPTH", 6, 7, &umr_bitfield_default },
+	 { "DCP_FRAME_RANDOM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DCP_RGB_RANDOM_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "DCP_HIGHPASS_RANDOM_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_FP_CONVERTED_FIELD[] = {
+	 { "DCP_FP_CONVERTED_FIELD_DATA", 0, 17, &umr_bitfield_default },
+	 { "DCP_FP_CONVERTED_FIELD_INDEX", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_CONTROL[] = {
+	 { "CURSOR_EN", 0, 0, &umr_bitfield_default },
+	 { "CUR_INV_TRANS_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_2X_MAGNIFY", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_FORCE_MC_ON", 20, 20, &umr_bitfield_default },
+	 { "CURSOR_URGENT_CONTROL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS[] = {
+	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SIZE[] = {
+	 { "CURSOR_HEIGHT", 0, 6, &umr_bitfield_default },
+	 { "CURSOR_WIDTH", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS_HIGH[] = {
+	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_POSITION[] = {
+	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
+	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_HOT_SPOT[] = {
+	 { "CURSOR_HOT_SPOT_Y", 0, 6, &umr_bitfield_default },
+	 { "CURSOR_HOT_SPOT_X", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR1[] = {
+	 { "CUR_COLOR1_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR1_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR1_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR2[] = {
+	 { "CUR_COLOR2_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR2_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR2_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_UPDATE[] = {
+	 { "CURSOR_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_STEREO_MODE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_MODE[] = {
+	 { "DC_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
+	 { "DC_LUT_ERROR", 16, 16, &umr_bitfield_default },
+	 { "DC_LUT_ERROR_RST", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_INDEX[] = {
+	 { "DC_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_SEQ_COLOR[] = {
+	 { "DC_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_PWL_DATA[] = {
+	 { "DC_LUT_BASE", 0, 15, &umr_bitfield_default },
+	 { "DC_LUT_DELTA", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_30_COLOR[] = {
+	 { "DC_LUT_COLOR_10_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_VGA_ACCESS_ENABLE[] = {
+	 { "DC_LUT_VGA_ACCESS_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WRITE_EN_MASK[] = {
+	 { "DC_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_AUTOFILL[] = {
+	 { "DC_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
+	 { "DC_LUT_AUTOFILL_DONE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_CONTROL[] = {
+	 { "DC_LUT_INC_B", 0, 3, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_SIGNED_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FLOAT_POINT_EN", 5, 5, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FORMAT", 6, 7, &umr_bitfield_default },
+	 { "DC_LUT_INC_G", 8, 11, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_SIGNED_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FLOAT_POINT_EN", 13, 13, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FORMAT", 14, 15, &umr_bitfield_default },
+	 { "DC_LUT_INC_R", 16, 19, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_SIGNED_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FLOAT_POINT_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FORMAT", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_BLUE[] = {
+	 { "DC_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_GREEN[] = {
+	 { "DC_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_RED[] = {
+	 { "DC_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_BLUE[] = {
+	 { "DC_LUT_WHITE_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_GREEN[] = {
+	 { "DC_LUT_WHITE_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_RED[] = {
+	 { "DC_LUT_WHITE_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_CONTROL[] = {
+	 { "DCP_CRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCP_CRC_SOURCE_SEL", 2, 4, &umr_bitfield_default },
+	 { "DCP_CRC_LINE_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_MASK[] = {
+	 { "DCP_CRC_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_CURRENT[] = {
+	 { "DCP_CRC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_CONTROL[] = {
+	 { "DVMM_USE_SINGLE_PTE", 0, 0, &umr_bitfield_default },
+	 { "DVMM_PAGE_WIDTH", 1, 4, &umr_bitfield_default },
+	 { "DVMM_PAGE_HEIGHT", 5, 8, &umr_bitfield_default },
+	 { "DVMM_MIN_PTE_BEFORE_FLIP", 9, 18, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE0", 20, 20, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE1", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_LAST[] = {
+	 { "DCP_CRC_LAST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_ARB_CONTROL[] = {
+	 { "DVMM_PTE_REQ_PER_CHUNK", 0, 5, &umr_bitfield_default },
+	 { "DVMM_MAX_PTE_REQ_OUTSTANDING", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG[] = {
+	 { "DCP_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_FLIP_RATE_CNTL[] = {
+	 { "GRPH_FLIP_RATE", 0, 2, &umr_bitfield_default },
+	 { "GRPH_FLIP_RATE_ENABLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_GSL_CONTROL[] = {
+	 { "DCP_GSL0_EN", 0, 0, &umr_bitfield_default },
+	 { "DCP_GSL1_EN", 1, 1, &umr_bitfield_default },
+	 { "DCP_GSL2_EN", 2, 2, &umr_bitfield_default },
+	 { "DCP_GSL_HSYNC_FLIP_FORCE_DELAY", 12, 15, &umr_bitfield_default },
+	 { "DCP_GSL_MASTER_EN", 16, 16, &umr_bitfield_default },
+	 { "DCP_GSL_XDMA_GROUP", 17, 18, &umr_bitfield_default },
+	 { "DCP_GSL_XDMA_GROUP_UNDERFLOW_EN", 19, 19, &umr_bitfield_default },
+	 { "DCP_GSL_SYNC_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "DCP_GSL_DELAY_SURFACE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
+	 { "DCP_GSL_HSYNC_FLIP_CHECK_DELAY", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[] = {
+	 { "DCP_LB_GAP_BETWEEN_CHUNK_20BPP", 0, 3, &umr_bitfield_default },
+	 { "DCP_LB_GAP_BETWEEN_CHUNK_30BPP", 4, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG_SG[] = {
+	 { "DCP_DEBUG_SG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DVMM_DEBUG[] = {
+	 { "DCP_DVMM_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG_SG2[] = {
+	 { "DCP_DEBUG_SG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_TEST_DEBUG_INDEX[] = {
+	 { "DCP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_TEST_DEBUG_DATA[] = {
+	 { "DCP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_STEREOSYNC_FLIP[] = {
+	 { "GRPH_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_FLIP_MODE", 8, 9, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG2[] = {
+	 { "DCP_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_REQUEST_FILTER_CNTL[] = {
+	 { "CUR_REQUEST_FILTER_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_STEREO_CONTROL[] = {
+	 { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_STEREO_OFFSET_YNX", 1, 1, &umr_bitfield_default },
+	 { "CURSOR_PRIMARY_OFFSET", 4, 13, &umr_bitfield_default },
+	 { "CURSOR_SECONDARY_OFFSET", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_G_Y[] = {
+	 { "OUT_CLAMP_MAX_G_Y", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_G_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_B_CB[] = {
+	 { "OUT_CLAMP_MAX_B_CB", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_B_CB", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHW_ROTATION[] = {
+	 { "GRPH_ROTATION_ANGLE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[] = {
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE", 1, 1, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT", 4, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CONTROL[] = {
+	 { "GRPH_REGAMMA_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_INDEX[] = {
+	 { "REGAMMA_LUT_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_DATA[] = {
+	 { "REGAMMA_LUT_DATA", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_WRITE_EN_MASK[] = {
+	 { "REGAMMA_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_START_CNTL[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_SLOPE_CNTL[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_END_CNTL1[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_END_CNTL2[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_0_1[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_2_3[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_4_5[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_6_7[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_8_9[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_10_11[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_12_13[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_14_15[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_START_CNTL[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_SLOPE_CNTL[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_END_CNTL1[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_END_CNTL2[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_0_1[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_2_3[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_4_5[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_6_7[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_8_9[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_10_11[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_12_13[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_14_15[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmALPHA_CONTROL[] = {
+	 { "ALPHA_ROUND_TRUNC_MODE", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_ALPHA_BLND_ENA", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[] = {
+	 { "GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[] = {
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT", 0, 19, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK", 25, 25, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK", 26, 26, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT", 28, 28, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK", 29, 29, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DATA_FORMAT[] = {
+	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "PIXEL_EXPAN_MODE", 2, 2, &umr_bitfield_default },
+	 { "INTERLEAVE_EN", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_REDUCE_MODE", 4, 4, &umr_bitfield_default },
+	 { "DYNAMIC_PIXEL_DEPTH", 5, 5, &umr_bitfield_default },
+	 { "PREFETCH", 12, 12, &umr_bitfield_default },
+	 { "REQUEST_MODE", 24, 24, &umr_bitfield_default },
+	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_MEMORY_CTRL[] = {
+	 { "LB_MEMORY_SIZE", 0, 11, &umr_bitfield_default },
+	 { "LB_NUM_PARTITIONS", 16, 19, &umr_bitfield_default },
+	 { "LB_MEMORY_CONFIG", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_MEMORY_SIZE_STATUS[] = {
+	 { "LB_MEMORY_SIZE_STATUS", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DESKTOP_HEIGHT[] = {
+	 { "DESKTOP_HEIGHT", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE_START_END[] = {
+	 { "VLINE_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE2_START_END[] = {
+	 { "VLINE2_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE2_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE2_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_V_COUNTER[] = {
+	 { "V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_SNAPSHOT_V_COUNTER[] = {
+	 { "SNAPSHOT_V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_INTERRUPT_MASK[] = {
+	 { "VBLANK_INTERRUPT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_MASK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE_STATUS[] = {
+	 { "VLINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE2_STATUS[] = {
+	 { "VLINE2_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE2_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VBLANK_STATUS[] = {
+	 { "VBLANK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VBLANK_ACK", 4, 4, &umr_bitfield_default },
+	 { "VBLANK_STAT", 12, 12, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_SYNC_RESET_SEL[] = {
+	 { "LB_SYNC_RESET_SEL", 0, 1, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_SEL2", 4, 4, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LB_SYNC_DURATION", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_R_CR[] = {
+	 { "LB_BLACK_KEYER_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_G_Y[] = {
+	 { "LB_BLACK_KEYER_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_B_CB[] = {
+	 { "LB_BLACK_KEYER_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_CTRL[] = {
+	 { "LB_KEYER_COLOR_EN", 0, 0, &umr_bitfield_default },
+	 { "LB_KEYER_COLOR_REP_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_R_CR[] = {
+	 { "LB_KEYER_COLOR_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_G_Y[] = {
+	 { "LB_KEYER_COLOR_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_B_CB[] = {
+	 { "LB_KEYER_COLOR_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_R_CR[] = {
+	 { "LB_KEYER_COLOR_REP_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_G_Y[] = {
+	 { "LB_KEYER_COLOR_REP_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_B_CB[] = {
+	 { "LB_KEYER_COLOR_REP_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_LEVEL_STATUS[] = {
+	 { "REQ_FIFO_LEVEL", 0, 5, &umr_bitfield_default },
+	 { "REQ_FIFO_FULL_CNTL", 10, 15, &umr_bitfield_default },
+	 { "DATA_BUFFER_LEVEL", 16, 27, &umr_bitfield_default },
+	 { "DATA_FIFO_FULL_CNTL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_URGENCY_CTRL[] = {
+	 { "LB_BUFFER_URGENCY_MARK_ON", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_MARK_OFF", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_URGENCY_STATUS[] = {
+	 { "LB_BUFFER_URGENCY_LEVEL", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_STAT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_STATUS[] = {
+	 { "LB_BUFFER_EMPTY_MARGIN", 0, 3, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_STAT", 4, 4, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_ACK", 12, 12, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_STAT", 16, 16, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_ACK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_NO_OUTSTANDING_REQ_STATUS[] = {
+	 { "LB_NO_OUTSTANDING_REQ_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_AFR_FLIP_MODE[] = {
+	 { "MVP_AFR_FLIP_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_AFR_FLIP_FIFO_CNTL[] = {
+	 { "MVP_AFR_FLIP_FIFO_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET", 4, 4, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FLIP_LINE_NUM_INSERT[] = {
+	 { "MVP_FLIP_LINE_NUM_INSERT_MODE", 0, 1, &umr_bitfield_default },
+	 { "MVP_FLIP_LINE_NUM_INSERT", 8, 22, &umr_bitfield_default },
+	 { "MVP_FLIP_LINE_NUM_OFFSET", 24, 29, &umr_bitfield_default },
+	 { "MVP_FLIP_AUTO_ENABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_MVP_LB_CONTROL[] = {
+	 { "MVP_SWAP_LOCK_IN_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_SEL", 8, 8, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_IN_CAP", 28, 28, &umr_bitfield_default },
+	 { "DC_MVP_SPARE_FLOPS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG[] = {
+	 { "LB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG2[] = {
+	 { "LB_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG3[] = {
+	 { "LB_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_TEST_DEBUG_INDEX[] = {
+	 { "LB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "LB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_TEST_DEBUG_DATA[] = {
+	 { "LB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_L[] = {
+	 { "DP_AUX_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1B[] = {
+	 { "DCIO_DEBUGHPD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_CLOCK_CONTROL[] = {
+	 { "DISPCLK_R_DCFE_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "DISPCLK_G_DCP_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_SCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "DISPCLK_G_PSCL_GATE_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DISPCLK_G_DCP_LOW_POWER_GATE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "DCFE_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DCFE_CLOCK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_SOFT_RESET[] = {
+	 { "DCP_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "PSCL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DCP_LOW_POWER_SOFT_RESET", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_DBG_CONFIG[] = {
+	 { "DCFE_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE_DBG_SEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_CTRL[] = {
+	 { "DCP_LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DCP_LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_FORCE", 21, 22, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_FORCE", 27, 28, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_DIS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_CTRL2[] = {
+	 { "DCP_LUT_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_MODE_SEL", 2, 3, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_MODE_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_MODE_SEL", 6, 7, &umr_bitfield_default },
+	 { "LB_ALPHA_MEM_PWR_MODE_SEL", 8, 9, &umr_bitfield_default },
+	 { "LB_MEM_PWR_MODE_SEL", 10, 11, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_MODE_SEL", 14, 15, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_FORCE", 21, 22, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_STATUS[] = {
+	 { "DCP_LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MISC[] = {
+	 { "DCFE_DPG_ALLOW_SR_ECO_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_ARBITRATION_CONTROL1[] = {
+	 { "PIXEL_DURATION", 0, 15, &umr_bitfield_default },
+	 { "BASE_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_ARBITRATION_CONTROL2[] = {
+	 { "TIME_WEIGHT", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_WATERMARK_MASK_CONTROL[] = {
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK", 0, 1, &umr_bitfield_default },
+	 { "URGENCY_WATERMARK_MASK", 8, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 16, 17, &umr_bitfield_default },
+	 { "DISABLE_FLIP_URGENT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_URGENCY_CONTROL[] = {
+	 { "URGENCY_LOW_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_HIGH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_DPM_CONTROL[] = {
+	 { "DPM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCLK_CHANGE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCLK_CHANGE_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK_MASK", 12, 13, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_STUTTER_CONTROL[] = {
+	 { "STUTTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON", 11, 11, &umr_bitfield_default },
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[] = {
+	 { "NB_PSTATE_CHANGE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_FORCE_ON", 9, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_ALLOW_FOR_URGENT", 10, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[] = {
+	 { "STUTTER_ENABLE_NONLPTCH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR_NONLPTCH", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON_NONLPTCH", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA_NONLPTCH", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC_NONLPTCH", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON_NONLPTCH", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_TEST_DEBUG_INDEX[] = {
+	 { "DPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_TEST_DEBUG_DATA[] = {
+	 { "DPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_REPEATER_PROGRAM[] = {
+	 { "REG_DPG_DMIFRC_REPEATER", 0, 2, &umr_bitfield_default },
+	 { "REG_DMIFRC_DPG_REPEATER", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_A[] = {
+	 { "DPG_HW_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_B[] = {
+	 { "DPG_HW_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_11[] = {
+	 { "DPG_HW_DEBUG_11", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_CHK_PRE_PROC_CNTL[] = {
+	 { "DPG_DISABLE_DMIF_BUF_CHK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_SELECT[] = {
+	 { "SCL_C_RAM_TAP_PAIR_IDX", 0, 3, &umr_bitfield_default },
+	 { "SCL_C_RAM_PHASE", 8, 11, &umr_bitfield_default },
+	 { "SCL_C_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_TAP_DATA[] = {
+	 { "SCL_C_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
+	 { "SCL_C_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE[] = {
+	 { "SCL_MODE", 0, 1, &umr_bitfield_default },
+	 { "SCL_PSCL_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TAP_CONTROL[] = {
+	 { "SCL_V_NUM_OF_TAPS", 0, 2, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_CONTROL[] = {
+	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_EARLY_EOL_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_BYPASS_CONTROL[] = {
+	 { "SCL_BYPASS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MANUAL_REPLICATE_CONTROL[] = {
+	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
+	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_AUTOMATIC_MODE_CONTROL[] = {
+	 { "SCL_V_CALC_AUTO_RATIO_EN", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_CALC_AUTO_RATIO_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_CONTROL[] = {
+	 { "SCL_H_FILTER_PICK_NEAREST", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_SCALE_RATIO[] = {
+	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_INIT[] = {
+	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_CONTROL[] = {
+	 { "SCL_V_FILTER_PICK_NEAREST", 0, 0, &umr_bitfield_default },
+	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_SCALE_RATIO[] = {
+	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_INIT[] = {
+	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_INIT_BOT[] = {
+	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_ROUND_OFFSET[] = {
+	 { "SCL_ROUND_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
+	 { "SCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_UPDATE[] = {
+	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "SCL_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "SCL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "SCL_COEF_UPDATE_COMPLETE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_F_SHARP_CONTROL[] = {
+	 { "SCL_HF_SHARP_SCALE_FACTOR", 0, 2, &umr_bitfield_default },
+	 { "SCL_HF_SHARP_EN", 4, 4, &umr_bitfield_default },
+	 { "SCL_VF_SHARP_SCALE_FACTOR", 8, 10, &umr_bitfield_default },
+	 { "SCL_VF_SHARP_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_ALU_CONTROL[] = {
+	 { "SCL_ALU_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_CONFLICT_STATUS[] = {
+	 { "SCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_START_SECONDARY[] = {
+	 { "VIEWPORT_Y_START_SECONDARY", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_START[] = {
+	 { "VIEWPORT_Y_START", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_SIZE[] = {
+	 { "VIEWPORT_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_LEFT_RIGHT[] = {
+	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_TOP_BOTTOM[] = {
+	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET1[] = {
+	 { "SCL_MODE_CHANGE", 0, 0, &umr_bitfield_default },
+	 { "SCL_MODE_CHANGE_ACK", 4, 4, &umr_bitfield_default },
+	 { "SCL_ALU_H_SCALE_RATIO", 7, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET2[] = {
+	 { "SCL_ALU_V_SCALE_RATIO", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET3[] = {
+	 { "SCL_ALU_SOURCE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "SCL_ALU_SOURCE_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_MASK[] = {
+	 { "SCL_MODE_CHANGE_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_DEBUG2[] = {
+	 { "SCL_DEBUG_REQ_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_DEBUG_EOF_MODE", 1, 2, &umr_bitfield_default },
+	 { "SCL_DEBUG2", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_DEBUG[] = {
+	 { "SCL_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TEST_DEBUG_INDEX[] = {
+	 { "SCL_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SCL_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TEST_DEBUG_DATA[] = {
+	 { "SCL_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_CONTROL[] = {
+	 { "BLND_GLOBAL_GAIN", 0, 7, &umr_bitfield_default },
+	 { "BLND_MODE", 8, 9, &umr_bitfield_default },
+	 { "BLND_STEREO_TYPE", 10, 11, &umr_bitfield_default },
+	 { "BLND_STEREO_POLARITY", 12, 12, &umr_bitfield_default },
+	 { "BLND_FEEDTHROUGH_EN", 13, 13, &umr_bitfield_default },
+	 { "BLND_ALPHA_MODE", 16, 17, &umr_bitfield_default },
+	 { "BLND_MULTIPLIED_MODE", 20, 20, &umr_bitfield_default },
+	 { "BLND_GLOBAL_ALPHA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_SM_CONTROL2[] = {
+	 { "SM_MODE", 0, 2, &umr_bitfield_default },
+	 { "SM_FRAME_ALTERNATE", 4, 4, &umr_bitfield_default },
+	 { "SM_FIELD_ALTERNATE", 5, 5, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
+	 { "SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_CONTROL2[] = {
+	 { "PTI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PTI_NEW_PIXEL_GAP", 4, 5, &umr_bitfield_default },
+	 { "BLND_NEW_PIXEL_MODE", 6, 6, &umr_bitfield_default },
+	 { "BLND_SUPERAA_DEGAMMA_EN", 7, 7, &umr_bitfield_default },
+	 { "BLND_SUPERAA_REGAMMA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_UPDATE[] = {
+	 { "BLND_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "BLND_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "BLND_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_UNDERFLOW_INTERRUPT[] = {
+	 { "BLND_UNDERFLOW_INT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_PIPE_INDEX", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_V_UPDATE_LOCK[] = {
+	 { "BLND_DCP_GRPH_V_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BLND_DCP_GRPH_SURF_V_UPDATE_LOCK", 1, 1, &umr_bitfield_default },
+	 { "BLND_DCP_CUR_V_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "BLND_DCP_CUR2_V_UPDATE_LOCK", 24, 24, &umr_bitfield_default },
+	 { "BLND_SCL_V_UPDATE_LOCK", 28, 28, &umr_bitfield_default },
+	 { "BLND_BLND_V_UPDATE_LOCK", 29, 29, &umr_bitfield_default },
+	 { "BLND_V_UPDATE_LOCK_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_DEBUG[] = {
+	 { "BLND_CNV_MUX_SELECT", 0, 0, &umr_bitfield_default },
+	 { "BLND_DEBUG", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_TEST_DEBUG_INDEX[] = {
+	 { "BLND_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "BLND_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_TEST_DEBUG_DATA[] = {
+	 { "BLND_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_REG_UPDATE_STATUS[] = {
+	 { "DCP_BLNDC_GRPH_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
+	 { "DCP_BLNDC_GRPH_SURF_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_SURF_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
+	 { "DCP_BLNDC_CUR_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
+	 { "DCP_BLNDO_CUR_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
+	 { "SCL_BLNDC_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "SCL_BLNDO_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
+	 { "BLND_BLNDC_UPDATE_PENDING", 10, 10, &umr_bitfield_default },
+	 { "BLND_BLNDO_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_3D_STRUCTURE_CONTROL[] = {
+	 { "CRTC_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_EN_DB", 4, 4, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_VSYNC_GAP[] = {
+	 { "CRTC_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_WINDOW[] = {
+	 { "CRTC_GSL_WINDOW_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_GSL_WINDOW_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_CONTROL[] = {
+	 { "CRTC_GSL_CHECK_LINE_NUM", 0, 13, &umr_bitfield_default },
+	 { "CRTC_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_BLANK_EARLY_NUM[] = {
+	 { "CRTC_H_BLANK_EARLY_NUM", 0, 9, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_EARLY_NUM_DIS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_TOTAL[] = {
+	 { "CRTC_H_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_BLANK_START_END[] = {
+	 { "CRTC_H_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_A[] = {
+	 { "CRTC_H_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_A_CNTL[] = {
+	 { "CRTC_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_B[] = {
+	 { "CRTC_H_SYNC_B_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_B_CNTL[] = {
+	 { "CRTC_H_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_B_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VBI_END[] = {
+	 { "CRTC_VBI_V_END", 0, 13, &umr_bitfield_default },
+	 { "CRTC_VBI_H_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL[] = {
+	 { "CRTC_V_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_MIN[] = {
+	 { "CRTC_V_TOTAL_MIN", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_MAX[] = {
+	 { "CRTC_V_TOTAL_MAX", 0, 13, &umr_bitfield_default },
+	 { "CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_CONTROL[] = {
+	 { "CRTC_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_TOTAL_MAX_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_ON_EVENT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_TO_MASTER_VSYNC", 12, 12, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK_EN", 15, 15, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_INT_STATUS[] = {
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VSYNC_NOM_INT_STATUS[] = {
+	 { "CRTC_VSYNC_NOM", 0, 0, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_BLANK_START_END[] = {
+	 { "CRTC_V_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_A[] = {
+	 { "CRTC_V_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_A_CNTL[] = {
+	 { "CRTC_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_B[] = {
+	 { "CRTC_V_SYNC_B_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_B_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_B_CNTL[] = {
+	 { "CRTC_V_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DTMTEST_CNTL[] = {
+	 { "CRTC_DTMTEST_CRTC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_CLK_DIV", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DTMTEST_STATUS_POSITION[] = {
+	 { "CRTC_DTMTEST_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGA_CNTL[] = {
+	 { "CRTC_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGA_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGA_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGB_CNTL[] = {
+	 { "CRTC_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGB_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGB_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FORCE_COUNT_NOW_CNTL[] = {
+	 { "CRTC_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FLOW_CONTROL[] = {
+	 { "CRTC_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_FORCE_NEXT_EYE[] = {
+	 { "CRTC_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_AVSYNC_COUNTER[] = {
+	 { "CRTC_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CONTROL[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SYNC_RESET_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
+	 { "CRTC_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
+	 { "CRTC_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_HBLANK_EARLY_CONTROL", 20, 22, &umr_bitfield_default },
+	 { "CRTC_DISP_READ_REQUEST_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SOF_PULL_EN", 29, 29, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LOCK_SNAPSHOT", 30, 30, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_VSYNC_N_HSYNC_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_CONTROL[] = {
+	 { "CRTC_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERLACE_CONTROL[] = {
+	 { "CRTC_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERLACE_STATUS[] = {
+	 { "CRTC_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FIELD_INDICATION_CONTROL[] = {
+	 { "CRTC_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_PIXEL_DATA_READBACK0[] = {
+	 { "CRTC_PIXEL_DATA_BLUE_CB", 0, 11, &umr_bitfield_default },
+	 { "CRTC_PIXEL_DATA_GREEN_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_PIXEL_DATA_READBACK1[] = {
+	 { "CRTC_PIXEL_DATA_RED_CR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS[] = {
+	 { "CRTC_V_BLANK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A", 2, 2, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "CRTC_V_START_LINE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_H_BLANK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_POSITION[] = {
+	 { "CRTC_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_NOM_VERT_POSITION[] = {
+	 { "CRTC_VERT_COUNT_NOM", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_FRAME_COUNT[] = {
+	 { "CRTC_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_VF_COUNT[] = {
+	 { "CRTC_VF_COUNT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_HV_COUNT[] = {
+	 { "CRTC_HV_COUNT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_COUNT_CONTROL[] = {
+	 { "CRTC_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_COUNT_RESET[] = {
+	 { "CRTC_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
+	 { "CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERT_SYNC_CONTROL[] = {
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "CRTC_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_STATUS[] = {
+	 { "CRTC_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
+	 { "CRTC_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_CONTROL[] = {
+	 { "CRTC_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 13, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT_POLARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
+	 { "CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
+	 { "CRTC_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
+	 { "CRTC_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
+	 { "CRTC_STEREO_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_STATUS[] = {
+	 { "CRTC_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_CONTROL[] = {
+	 { "CRTC_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_POSITION[] = {
+	 { "CRTC_SNAPSHOT_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_FRAME[] = {
+	 { "CRTC_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_START_LINE_CONTROL[] = {
+	 { "CRTC_PROGRESSIVE_START_LINE_EARLY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_START_LINE_EARLY", 1, 1, &umr_bitfield_default },
+	 { "CRTC_PREFETCH_EN", 2, 2, &umr_bitfield_default },
+	 { "CRTC_LEGACY_REQUESTOR_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_ADVANCED_START_LINE_POSITION", 12, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERRUPT_CONTROL[] = {
+	 { "CRTC_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_MSK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_TYPE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_UPDATE_LOCK[] = {
+	 { "CRTC_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DOUBLE_BUFFER_CONTROL[] = {
+	 { "CRTC_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CRTC_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VGA_PARAMETER_CAPTURE_MODE[] = {
+	 { "CRTC_VGA_PARAMETER_CAPTURE_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_CONTROL[] = {
+	 { "CRTC_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_PARAMETERS[] = {
+	 { "CRTC_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_COLOR[] = {
+	 { "CRTC_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MASTER_UPDATE_LOCK[] = {
+	 { "MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "GSL_CONTROL_MASTER_UPDATE_LOCK", 8, 8, &umr_bitfield_default },
+	 { "UNDERFLOW_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MASTER_UPDATE_MODE[] = {
+	 { "MASTER_UPDATE_MODE", 0, 2, &umr_bitfield_default },
+	 { "MASTER_UPDATE_INTERLACED_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_INBAND_CNTL_INSERT[] = {
+	 { "CRTC_MVP_INBAND_OUT_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[] = {
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_STATUS[] = {
+	 { "CRTC_FLIP_NOW_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FLIP_NOW_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MASTER_EN[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_ALLOW_STOP_OFF_V_CNT[] = {
+	 { "CRTC_ALLOW_STOP_OFF_V_CNT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_UPDATE_INT_STATUS[] = {
+	 { "CRTC_V_UPDATE_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_DEBUG_INDEX[] = {
+	 { "CRTC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_DEBUG_DATA[] = {
+	 { "CRTC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_OVERSCAN_COLOR[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE", 0, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN", 10, 19, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_OVERSCAN_COLOR_EXT[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_DATA_COLOR[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_DATA_COLOR_EXT[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLACK_COLOR[] = {
+	 { "CRTC_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLACK_COLOR_EXT[] = {
+	 { "CRTC_BLACK_COLOR_B_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT0_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT0_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT1_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_LINE_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT1_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT2_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_LINE_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT2_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC_CNTL[] = {
+	 { "CRTC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "CRTC_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_CRC0_SELECT", 20, 22, &umr_bitfield_default },
+	 { "CRTC_CRC1_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_DATA_RG[] = {
+	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_DATA_B[] = {
+	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_DATA_RG[] = {
+	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_DATA_B[] = {
+	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATIC_SCREEN_CONTROL[] = {
+	 { "CRTC_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
+	 { "CRTC_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SS_STATUS", 25, 25, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_R[] = {
+	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_G[] = {
+	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_B[] = {
+	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEST_DEBUG_INDEX[] = {
+	 { "FMT_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FMT_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEST_DEBUG_DATA[] = {
+	 { "FMT_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DYNAMIC_EXP_CNTL[] = {
+	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CONTROL[] = {
+	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "FMT_STEREOSYNC_OVR_POL", 4, 4, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
+	 { "FMT_PIXEL_ENCODING", 16, 16, &umr_bitfield_default },
+	 { "FMT_SUBSAMPLING_MODE", 17, 17, &umr_bitfield_default },
+	 { "FMT_SUBSAMPLING_ORDER", 18, 18, &umr_bitfield_default },
+	 { "FMT_SRC_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_BIT_DEPTH_CONTROL[] = {
+	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
+	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
+	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
+	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
+	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
+	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_R_SEED[] = {
+	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_G_SEED[] = {
+	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_B_SEED[] = {
+	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT", 0, 0, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_CNTL[] = {
+	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_CNTL[] = {
+	 { "FMT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_DTMTEST_CRC_EN", 1, 1, &umr_bitfield_default },
+	 { "FMT_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "FMT_ONE_SHOT_CRC_PENDING", 5, 5, &umr_bitfield_default },
+	 { "FMT_CRC_INCLUDE_OVERSCAN", 6, 6, &umr_bitfield_default },
+	 { "FMT_CRC_ONLY_BLANKB", 8, 8, &umr_bitfield_default },
+	 { "FMT_CRC_PSR_MODE_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "FMT_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "FMT_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "FMT_CRC_EVEN_ODD_PIX_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FMT_CRC_EVEN_ODD_PIX_SELECT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_RED_GREEN_MASK[] = {
+	 { "FMT_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_BLUE_CONTROL_MASK[] = {
+	 { "FMT_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_RED_GREEN[] = {
+	 { "FMT_CRC_SIG_RED", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_BLUE_CONTROL[] = {
+	 { "FMT_CRC_SIG_BLUE", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_CONTROL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DEBUG_CNTL[] = {
+	 { "FMT_DEBUG_COLOR_SELECT", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMA_POSITION_LOWER_BASE_ADDRESS[] = {
+	 { "DMA_POSITION_BUFFER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS", 1, 6, &umr_bitfield_default },
+	 { "DMA_POSITION_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_M[] = {
+	 { "DP_AUX_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMA_POSITION_UPPER_BASE_ADDRESS[] = {
+	 { "DMA_POSITION_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_N[] = {
+	 { "DP_AUX_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_O[] = {
+	 { "DP_AUX_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1E[] = {
+	 { "GRPH_DEC_RD1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_P[] = {
+	 { "DP_AUX_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1F[] = {
+	 { "GRPH_DEC_RD0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_WORSTCASE_LATENCY_COUNT[] = {
+	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL2[] = {
+	 { "INPUT_CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL2[] = {
+	 { "CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMIF_DEBUG02_CORE0[] = {
+	 { "DB_DATA", 0, 15, &umr_bitfield_default },
+	 { "MC_RDRET_COUNT_EN", 16, 16, &umr_bitfield_default },
+	 { "MC_RDRET_COUNTER", 17, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR1[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_CONTROL[] = {
+	 { "CONTROLLER_RESET", 0, 0, &umr_bitfield_default },
+	 { "FLUSH_CONTROL", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_UNSOLICITED_RESPONSE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG2[] = {
+	 { "DCIO_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG1[] = {
+	 { "FMT_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR02[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ02[] = {
+	 { "SEQ_MAP0_EN", 0, 0, &umr_bitfield_default },
+	 { "SEQ_MAP1_EN", 1, 1, &umr_bitfield_default },
+	 { "SEQ_MAP2_EN", 2, 2, &umr_bitfield_default },
+	 { "SEQ_MAP3_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
+	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
+	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
+	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
+	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
+	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
+	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
+	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
+	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_Q[] = {
+	 { "DP_AUX_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
+	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
+	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT22[] = {
+	 { "GRPH_LATCH_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+	 { "STREAM_TYPE_R", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
+	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
+	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
+	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
+	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
+	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
+	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[] = {
+	 { "CC", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[] = {
+	 { "KEEPALIVE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
+	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CNTL[] = {
+	 { "FBC_GRPH_COMP_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_SRC_SEL", 1, 3, &umr_bitfield_default },
+	 { "FBC_COMP_CLK_GATE_EN", 8, 8, &umr_bitfield_default },
+	 { "FBC_COHERENCY_MODE", 16, 17, &umr_bitfield_default },
+	 { "FBC_SOFT_COMPRESS_EN", 25, 25, &umr_bitfield_default },
+	 { "FBC_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_MASK[] = {
+	 { "FBC_IDLE_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_FORCE_CLEAR_MASK[] = {
+	 { "FBC_IDLE_FORCE_CLEAR_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_START_STOP_DELAY[] = {
+	 { "FBC_DECOMP_START_DELAY", 0, 4, &umr_bitfield_default },
+	 { "FBC_DECOMP_STOP_DELAY", 7, 7, &umr_bitfield_default },
+	 { "FBC_COMP_START_DELAY", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_CNTL[] = {
+	 { "FBC_MIN_COMPRESSION", 0, 3, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO08_EN", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO16_EN", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB04_EN", 18, 18, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB08_EN", 19, 19, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB16_EN", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_MODE[] = {
+	 { "FBC_RLE_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_DPCM4_RGB_EN", 8, 8, &umr_bitfield_default },
+	 { "FBC_DPCM8_RGB_EN", 9, 9, &umr_bitfield_default },
+	 { "FBC_DPCM4_YUV_EN", 10, 10, &umr_bitfield_default },
+	 { "FBC_DPCM8_YUV_EN", 11, 11, &umr_bitfield_default },
+	 { "FBC_IND_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG0[] = {
+	 { "FBC_PERF_MUX0", 0, 7, &umr_bitfield_default },
+	 { "FBC_PERF_MUX1", 8, 15, &umr_bitfield_default },
+	 { "FBC_COMP_WAKE_DIS", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG0", 17, 23, &umr_bitfield_default },
+	 { "FBC_DEBUG_MUX", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG1[] = {
+	 { "FBC_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG2[] = {
+	 { "FBC_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT0[] = {
+	 { "FBC_IND_LUT0", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT1[] = {
+	 { "FBC_IND_LUT1", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT2[] = {
+	 { "FBC_IND_LUT2", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT3[] = {
+	 { "FBC_IND_LUT3", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT4[] = {
+	 { "FBC_IND_LUT4", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT5[] = {
+	 { "FBC_IND_LUT5", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT6[] = {
+	 { "FBC_IND_LUT6", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT7[] = {
+	 { "FBC_IND_LUT7", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT8[] = {
+	 { "FBC_IND_LUT8", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT9[] = {
+	 { "FBC_IND_LUT9", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT10[] = {
+	 { "FBC_IND_LUT10", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT11[] = {
+	 { "FBC_IND_LUT11", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT12[] = {
+	 { "FBC_IND_LUT12", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT13[] = {
+	 { "FBC_IND_LUT13", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT14[] = {
+	 { "FBC_IND_LUT14", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT15[] = {
+	 { "FBC_IND_LUT15", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_01[] = {
+	 { "FBC_CSM_REGION_OFFSET_0", 0, 11, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_1", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_23[] = {
+	 { "FBC_CSM_REGION_OFFSET_2", 0, 11, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_3", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CLIENT_REGION_MASK[] = {
+	 { "FBC_MEMORY_REGION_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_COMP[] = {
+	 { "FBC_COMP_SWAP", 0, 1, &umr_bitfield_default },
+	 { "FBC_COMP_RSIZE", 3, 3, &umr_bitfield_default },
+	 { "FBC_COMP_BUSY_HYSTERESIS", 4, 7, &umr_bitfield_default },
+	 { "FBC_COMP_CLK_CNTL", 8, 9, &umr_bitfield_default },
+	 { "FBC_COMP_PRIVILEGED_ACCESS_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "FBC_COMP_ADDRESS_TRANSLATION_ENABLE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR[] = {
+	 { "FBC_DEBUG_CSR_ADDR", 0, 11, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_WR_DATA", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_RD_DATA", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA[] = {
+	 { "FBC_DEBUG_CSR_RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA[] = {
+	 { "FBC_DEBUG_CSR_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_RDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_WDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_MISC[] = {
+	 { "FBC_DECOMPRESS_ERROR", 0, 1, &umr_bitfield_default },
+	 { "FBC_STOP_ON_ERROR", 2, 2, &umr_bitfield_default },
+	 { "FBC_INVALIDATE_ON_ERROR", 3, 3, &umr_bitfield_default },
+	 { "FBC_ERROR_PIXEL", 4, 7, &umr_bitfield_default },
+	 { "FBC_DIVIDE_X", 8, 9, &umr_bitfield_default },
+	 { "FBC_DIVIDE_Y", 10, 10, &umr_bitfield_default },
+	 { "FBC_RSM_WRITE_VALUE", 11, 11, &umr_bitfield_default },
+	 { "FBC_RSM_UNCOMP_DATA_IMMEDIATELY", 12, 12, &umr_bitfield_default },
+	 { "FBC_STOP_ON_HFLIP_EVENT", 13, 13, &umr_bitfield_default },
+	 { "FBC_DECOMPRESS_ERROR_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "FBC_RESET_AT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FBC_RESET_AT_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "FBC_SLOW_REQ_INTERVAL", 24, 28, &umr_bitfield_default },
+	 { "FBC_FORCE_DECOMPRESSOR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_STATUS[] = {
+	 { "FBC_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_INDEX[] = {
+	 { "FBC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FBC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_DATA[] = {
+	 { "FBC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL1[] = {
+	 { "MVP_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_MIXER_MODE", 4, 6, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK", 9, 9, &umr_bitfield_default },
+	 { "MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE", 10, 10, &umr_bitfield_default },
+	 { "MVP_RATE_CONTROL", 12, 12, &umr_bitfield_default },
+	 { "MVP_CHANNEL_CONTROL", 16, 16, &umr_bitfield_default },
+	 { "MVP_GPU_CHAIN_LOCATION", 20, 21, &umr_bitfield_default },
+	 { "MVP_DISABLE_MSB_EXPAND", 24, 24, &umr_bitfield_default },
+	 { "MVP_30BPP_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_A", 30, 30, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_B", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL2[] = {
+	 { "MVP_MUX_DE_DVOCNTL0_SEL", 0, 0, &umr_bitfield_default },
+	 { "MVP_MUX_DE_DVOCNTL2_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_MUXA_CLK_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MUXB_CLK_SEL", 12, 12, &umr_bitfield_default },
+	 { "MVP_DVOCNTL_MUX", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_OUT_EN", 24, 24, &umr_bitfield_default },
+	 { "MVP_SWAP_AB_IN_DC_DDR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_CONTROL[] = {
+	 { "MVP_STOP_SLAVE_WM", 0, 7, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_WM", 8, 15, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_CNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_STATUS[] = {
+	 { "MVP_FIFO_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_ACK", 16, 16, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW", 20, 20, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_ACK", 28, 28, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_MASK", 30, 30, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_SLAVE_STATUS[] = {
+	 { "MVP_SLAVE_PIXELS_PER_LINE_RCVED", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINES_PER_FRAME_RCVED", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_INBAND_CNTL_CAP[] = {
+	 { "MVP_IGNOR_INBAND_CNTL", 0, 0, &umr_bitfield_default },
+	 { "MVP_PASSING_INBAND_CNTL_EN", 4, 4, &umr_bitfield_default },
+	 { "MVP_INBAND_CNTL_CHAR_CAP", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_BLACK_KEYER[] = {
+	 { "MVP_BLACK_KEYER_R", 0, 9, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_G", 10, 19, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_B", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_CNTL[] = {
+	 { "MVP_CRC_BLUE_MASK", 0, 7, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_MASK", 8, 15, &umr_bitfield_default },
+	 { "MVP_CRC_RED_MASK", 16, 23, &umr_bitfield_default },
+	 { "MVP_CRC_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_CRC_CONT_EN", 29, 29, &umr_bitfield_default },
+	 { "MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_BLUE_GREEN[] = {
+	 { "MVP_CRC_BLUE_RESULT", 0, 15, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_RESULT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_RED[] = {
+	 { "MVP_CRC_RED_RESULT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL3[] = {
+	 { "MVP_RESET_IN_BETWEEN_FRAMES", 0, 0, &umr_bitfield_default },
+	 { "MVP_DDR_SC_AB_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_DDR_SC_B_START_MODE", 8, 8, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_CASCADE_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_48BIT_EN", 24, 24, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_CAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL1[] = {
+	 { "MVP_SLAVE_PIXEL_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINE_ERROR_CNT", 16, 28, &umr_bitfield_default },
+	 { "MVP_SLAVE_DATA_CHK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL2[] = {
+	 { "MVP_SLAVE_FRAME_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_FRAME_ERROR_CNT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_INDEX[] = {
+	 { "MVP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MVP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_DATA[] = {
+	 { "MVP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_DEBUG[] = {
+	 { "MVP_SWAP_LOCK_IN_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_EN", 1, 1, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_IN_SEL", 2, 2, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_SEL", 3, 3, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP", 4, 4, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP", 5, 5, &umr_bitfield_default },
+	 { "MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR", 6, 6, &umr_bitfield_default },
+	 { "MVP_DIS_READ_POINTER_RESET_DELAY", 7, 7, &umr_bitfield_default },
+	 { "MVP_DEBUG_BITS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_CONFIG[] = {
+	 { "PIPE0_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_ENABLE[] = {
+	 { "PIPE0_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_STATUS[] = {
+	 { "PIPE0_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE0_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE0_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_CONFIG[] = {
+	 { "PIPE1_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_ENABLE[] = {
+	 { "PIPE1_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_STATUS[] = {
+	 { "PIPE1_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE1_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE1_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE1_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE1_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_CONFIG[] = {
+	 { "PIPE2_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_ENABLE[] = {
+	 { "PIPE2_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_STATUS[] = {
+	 { "PIPE2_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE2_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE2_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE2_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE2_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_IP_REQUEST_CNTL[] = {
+	 { "IP_REQUEST_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_CONFIG_REG[] = {
+	 { "PGFSM_CONFIG_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_WRITE_REG[] = {
+	 { "PGFSM_WRITE_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGCNTL_STATUS_REG[] = {
+	 { "SWREQ_RWOP_BUSY", 0, 0, &umr_bitfield_default },
+	 { "SWREQ_RWOP_FORCE", 1, 1, &umr_bitfield_default },
+	 { "IPREQ_IGNORE_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DCPG_ECO_DEBUG", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_INDEX[] = {
+	 { "DCPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_DATA[] = {
+	 { "DCPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV0_PG_CONFIG[] = {
+	 { "DCFEV0_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV0_PG_ENABLE[] = {
+	 { "DCFEV0_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV0_PG_STATUS[] = {
+	 { "DCFEV0_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "DCFEV0_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "DCFEV0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "DCFEV0_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "DCFEV0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_INTERRUPT_STATUS[] = {
+	 { "DCFE0_POWER_UP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_POWER_DOWN_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE1_POWER_UP_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE1_POWER_DOWN_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE2_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE2_POWER_DOWN_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_POWER_UP_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_POWER_DOWN_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_POWER_UP_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_POWER_DOWN_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE5_POWER_UP_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE5_POWER_DOWN_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFEV0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFEV0_POWER_DOWN_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DSI_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DSI_POWER_DOWN_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_INTERRUPT_CONTROL[] = {
+	 { "DCFE0_POWER_UP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_POWER_DOWN_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_POWER_DOWN_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE1_POWER_UP_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCFE1_POWER_UP_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE1_POWER_DOWN_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCFE1_POWER_DOWN_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE2_POWER_UP_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCFE2_POWER_UP_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE2_POWER_DOWN_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCFE2_POWER_DOWN_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE3_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCFE3_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE3_POWER_DOWN_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCFE3_POWER_DOWN_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCFE4_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE4_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCFE4_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_POWER_UP_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_POWER_UP_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFEV0_POWER_UP_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCFEV0_POWER_UP_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFEV0_POWER_DOWN_INT_MASK", 26, 26, &umr_bitfield_default },
+	 { "DCFEV0_POWER_DOWN_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "DSI_POWER_UP_INT_MASK", 28, 28, &umr_bitfield_default },
+	 { "DSI_POWER_UP_INT_CLEAR", 29, 29, &umr_bitfield_default },
+	 { "DSI_POWER_DOWN_INT_MASK", 30, 30, &umr_bitfield_default },
+	 { "DSI_POWER_DOWN_INT_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_CONTROL[] = {
+	 { "DMIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_GROUP_REQUESTS_IN_CHUNK", 2, 2, &umr_bitfield_default },
+	 { "DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT", 4, 4, &umr_bitfield_default },
+	 { "DMIF_REQ_BURST_SIZE", 8, 10, &umr_bitfield_default },
+	 { "DMIF_UNDERFLOW_RECOVERY_EN", 11, 11, &umr_bitfield_default },
+	 { "DMIF_FORCE_TOTAL_REQ_BURST_SIZE", 12, 15, &umr_bitfield_default },
+	 { "DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS", 16, 21, &umr_bitfield_default },
+	 { "DMIF_DELAY_ARBITRATION", 24, 28, &umr_bitfield_default },
+	 { "DMIF_CHUNK_BUFF_MARGIN", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS[] = {
+	 { "DMIF_MC_SEND_ON_IDLE", 0, 7, &umr_bitfield_default },
+	 { "DMIF_CLEAR_MC_SEND_ON_IDLE", 8, 15, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_URGENT_ONLY", 17, 17, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT", 20, 23, &umr_bitfield_default },
+	 { "DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT", 24, 27, &umr_bitfield_default },
+	 { "DMIF_UNDERFLOW", 28, 28, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_TAP_POINT", 29, 30, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_REQ_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_HW_DEBUG[] = {
+	 { "DMIF_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ARBITRATION_CONTROL[] = {
+	 { "DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "PIPE_SWITCH_EFFICIENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[] = {
+	 { "PORTID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CUMULATIVE_LATENCY_COUNT[] = {
+	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL3[] = {
+	 { "INPUT_CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL3[] = {
+	 { "CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTATE_CHANGE_STATUS[] = {
+	 { "STATE_CHANGE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR2[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG3[] = {
+	 { "DCIO_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG2[] = {
+	 { "FMT_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR03[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ03[] = {
+	 { "SEQ_FONT_B1", 0, 0, &umr_bitfield_default },
+	 { "SEQ_FONT_B2", 1, 1, &umr_bitfield_default },
+	 { "SEQ_FONT_A1", 2, 2, &umr_bitfield_default },
+	 { "SEQ_FONT_A2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_FONT_B0", 4, 4, &umr_bitfield_default },
+	 { "SEQ_FONT_A0", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_P_VMID[] = {
+	 { "P_VMID_PIPE0", 0, 3, &umr_bitfield_default },
+	 { "P_VMID_PIPE1", 4, 7, &umr_bitfield_default },
+	 { "P_VMID_PIPE2", 8, 11, &umr_bitfield_default },
+	 { "P_VMID_PIPE3", 12, 15, &umr_bitfield_default },
+	 { "P_VMID_PIPE4", 16, 19, &umr_bitfield_default },
+	 { "P_VMID_PIPE5", 20, 23, &umr_bitfield_default },
+	 { "P_VMID_PIPE6", 24, 27, &umr_bitfield_default },
+	 { "P_VMID_PIPE7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_INDEX[] = {
+	 { "DMIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_DATA[] = {
+	 { "DMIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CALC[] = {
+	 { "ADDR_CONFIG_PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ADDR_CONFIG_ROW_SIZE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS2[] = {
+	 { "DMIF_PIPE0_DISPCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DMIF_PIPE1_DISPCLK_STATUS", 1, 1, &umr_bitfield_default },
+	 { "DMIF_PIPE2_DISPCLK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DMIF_PIPE3_DISPCLK_STATUS", 3, 3, &umr_bitfield_default },
+	 { "DMIF_PIPE4_DISPCLK_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DMIF_PIPE5_DISPCLK_STATUS", 5, 5, &umr_bitfield_default },
+	 { "DMIF_CHUNK_TRACKER_SCLK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DMIF_FBC_TRACKER_SCLK_STATUS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLOW_POWER_TILING_CONTROL[] = {
+	 { "LOW_POWER_TILING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_MODE", 3, 4, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_PIPES", 5, 7, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_BANKS", 8, 10, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE", 11, 11, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROW_SIZE", 12, 14, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROWS_PER_CHAN", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_CONTROL[] = {
+	 { "MCIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "ADDRESS_TRANSLATION_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "PRIVILEGED_ACCESS_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MCIF_SLOW_REQ_INTERVAL", 12, 15, &umr_bitfield_default },
+	 { "LOW_READ_URG_LEVEL", 16, 23, &umr_bitfield_default },
+	 { "MC_CLEAN_DEASSERT_LATENCY", 24, 29, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_URGENT_ONLY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WRITE_COMBINE_CONTROL[] = {
+	 { "MCIF_WRITE_COMBINE_TIMEOUT", 0, 7, &umr_bitfield_default },
+	 { "VIP_WRITE_COMBINE_TIMEOUT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_INDEX[] = {
+	 { "MCIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MCIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_DATA[] = {
+	 { "MCIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_VMID[] = {
+	 { "MCIF_WR_VMID", 0, 3, &umr_bitfield_default },
+	 { "VIP_WR_VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_MEM_CONTROL[] = {
+	 { "MCIFMEM_CACHE_MODE_DIS", 0, 0, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_MODE", 4, 5, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_SIZE", 8, 15, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_PIPE", 16, 18, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_TYPE", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
+	 { "DC_PIPE_DIS", 1, 6, &umr_bitfield_default },
+	 { "DC_UNDERLAY_PIPE_DIS", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DC_INTERFACE_NACK_STATUS[] = {
+	 { "DMIF_RDRET_NACK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DMIF_RDRET_NACK_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_TIMEOUT[] = {
+	 { "RBBMIF_TIMEOUT_DELAY", 0, 19, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_TO_REQ_HOLD", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_STATUS[] = {
+	 { "RBBMIF_TIMEOUT_CLIENTS_DEC", 0, 14, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_OP", 28, 28, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_RDWR_STATUS", 29, 29, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_ACK", 30, 30, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_MASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_TIMEOUT_DIS[] = {
+	 { "CLIENT0_TIMEOUT_DIS", 0, 0, &umr_bitfield_default },
+	 { "CLIENT1_TIMEOUT_DIS", 1, 1, &umr_bitfield_default },
+	 { "CLIENT2_TIMEOUT_DIS", 2, 2, &umr_bitfield_default },
+	 { "CLIENT3_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "CLIENT4_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "CLIENT5_TIMEOUT_DIS", 5, 5, &umr_bitfield_default },
+	 { "CLIENT6_TIMEOUT_DIS", 6, 6, &umr_bitfield_default },
+	 { "CLIENT7_TIMEOUT_DIS", 7, 7, &umr_bitfield_default },
+	 { "CLIENT8_TIMEOUT_DIS", 8, 8, &umr_bitfield_default },
+	 { "CLIENT9_TIMEOUT_DIS", 9, 9, &umr_bitfield_default },
+	 { "CLIENT10_TIMEOUT_DIS", 10, 10, &umr_bitfield_default },
+	 { "CLIENT11_TIMEOUT_DIS", 11, 11, &umr_bitfield_default },
+	 { "CLIENT12_TIMEOUT_DIS", 12, 12, &umr_bitfield_default },
+	 { "CLIENT13_TIMEOUT_DIS", 13, 13, &umr_bitfield_default },
+	 { "CLIENT14_TIMEOUT_DIS", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATUS[] = {
+	 { "DMIF_RDREQ_MEM1_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM2_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_STATE", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_STATE", 8, 8, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_STATE", 9, 10, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_STATE", 11, 11, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_STATE", 22, 22, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_STATE", 26, 27, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_STATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATUS2[] = {
+	 { "DMIF1_ASYNC_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_STATE", 5, 6, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_STATE", 7, 8, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_STATE", 9, 9, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_STATE", 14, 14, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_PWR_STATE", 15, 16, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_STATE", 17, 18, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_STATE", 19, 19, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_STATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_CLK_CNTL[] = {
+	 { "DCI_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCI_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_M_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "SCLK_G_STREAM_AZ_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "SCLK_R_AZ_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_FBC_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_VGA_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "DISPCLK_G_VIP_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "VPCLK_POL", 14, 14, &umr_bitfield_default },
+	 { "DISPCLK_G_DMCU_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "SCLK_G_DMIF_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "SCLK_G_DMIFTRK_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "SCLK_G_CNTL_AZ_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIFV_L_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIFV_C_GATE_DIS", 26, 26, &umr_bitfield_default },
+	 { "DCI_PG_TEST_CLK_SEL", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_CLK_RAMP_CNTL[] = {
+	 { "DISPCLK_G_MCIF_DWB_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "SCLK_G_MCIF_DWB_GATE_DIS", 1, 1, &umr_bitfield_default },
+	 { "DISPCLK_G_MCIF_CWB0_GATE_DIS", 2, 2, &umr_bitfield_default },
+	 { "SCLK_G_MCIF_CWB0_GATE_DIS", 3, 3, &umr_bitfield_default },
+	 { "DISPCLK_G_MCIF_CWB1_GATE_DIS", 4, 4, &umr_bitfield_default },
+	 { "SCLK_G_MCIF_CWB1_GATE_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL[] = {
+	 { "DMIF_RDREQ_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_FORCE", 3, 3, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_FORCE", 5, 5, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_FORCE", 7, 7, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_FORCE", 12, 12, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_FORCE", 14, 15, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_DIS", 19, 19, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_FORCE", 23, 24, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_DIS", 25, 25, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_FORCE", 26, 27, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_DIS", 28, 28, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_FORCE", 29, 29, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL2[] = {
+	 { "DMIF0_ASYNC_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_DIS", 7, 7, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_FORCE", 14, 14, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_DIS", 15, 15, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_FORCE", 19, 20, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_DIS", 21, 21, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_FORCE", 22, 22, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_FORCE", 27, 28, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_DIS", 29, 29, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_FORCE", 30, 30, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL3[] = {
+	 { "DMIF4_ASYNC_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_DIS", 7, 7, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_FORCE", 14, 14, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_DIS", 15, 15, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM_PWR_MODE_SEL", 16, 17, &umr_bitfield_default },
+	 { "DMIF_ASYNC_MEM_PWR_MODE_SEL", 18, 19, &umr_bitfield_default },
+	 { "DMIF_DATA_MEM_PWR_MODE_SEL", 20, 21, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_MODE_SEL", 22, 22, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_MODE_SEL", 23, 24, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_MODE_SEL", 25, 26, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_MODE_SEL", 27, 28, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_MODE_SEL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_INDEX[] = {
+	 { "DCI_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCI_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_DATA[] = {
+	 { "DCI_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_DEBUG_CONFIG[] = {
+	 { "DCI_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCI_DBG_BLOCK_SEL", 4, 7, &umr_bitfield_default },
+	 { "DCI_DBG_CLOCK_SEL", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_STATUS_FLAG[] = {
+	 { "RBBMIF_STATE", 0, 1, &umr_bitfield_default },
+	 { "RBBMIF_READ_TIMEOUT", 4, 4, &umr_bitfield_default },
+	 { "RBBMIF_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
+	 { "RBBMIF_FIFO_FULL", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_SOFT_RESET[] = {
+	 { "VGA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "VIP_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "MCIF_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "FBC_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "DMIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DMIF1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DMIF2_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DMIF3_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "DMIF4_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DMIF5_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DCFEV0_L_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "DCFEV0_C_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "DMIFARB_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "MCIF_DWB_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "MCIF_CWB0_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "MCIF_CWB1_SOFT_RESET", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_URG_OVERRIDE[] = {
+	 { "DMIF_URG_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "DMIF_URG_OVERRIDE_LEVEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE6_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE7_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE6_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE7_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_REG_RD_STATUS[] = {
+	 { "DVMM_REG_RD_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_REG_RD_DATA[] = {
+	 { "DVMM_REG_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_REQ[] = {
+	 { "MAX_PTEREQ_TO_ISSUE", 0, 7, &umr_bitfield_default },
+	 { "HFLIP_PTEREQ_PER_CHUNK_INT", 8, 15, &umr_bitfield_default },
+	 { "HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_CNTL[] = {
+	 { "PDE_CACHE_INVALIDATE_CNTL", 0, 1, &umr_bitfield_default },
+	 { "DEBUG_SYSTEM_ACCESS_MODE", 4, 5, &umr_bitfield_default },
+	 { "FORCE_SYSTEM_ACCESS_MODE", 7, 7, &umr_bitfield_default },
+	 { "DBG_DCE_VMID", 8, 11, &umr_bitfield_default },
+	 { "FORCE_DBG_DCE_VMID", 15, 15, &umr_bitfield_default },
+	 { "OVERRIDE_SNOOP", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_PDE_INVALIDATE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_FAULT_STATUS[] = {
+	 { "DVMM_FAULT_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_FAULT_ADDR[] = {
+	 { "DVMM_FAULT_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MISC[] = {
+	 { "MCIF_WB_URG_OVRD", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_URG_LVL", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_PGMEM_CONTROL[] = {
+	 { "DVMM_PTE0_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DVMM_PTE0_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DVMM_PTE1_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DVMM_PTE1_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "DVMM_PTE2_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "DVMM_PTE2_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "DVMM_PTE3_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "DVMM_PTE3_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "DVMM_PTE4_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "DVMM_PTE4_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "DVMM_PTE5_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "DVMM_PTE5_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+	 { "DVMM_PTE6_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
+	 { "DVMM_PTE6_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "DVMM_PTE7_MEM_PWR_FORCE", 21, 22, &umr_bitfield_default },
+	 { "DVMM_PTE7_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+	 { "DVMM_PTE_MEM_PWR_MODE_SEL", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_PGMEM_STATE[] = {
+	 { "DVMM_PIPE0_PTE_PGMEM_STATE", 0, 1, &umr_bitfield_default },
+	 { "DVMM_PIPE1_PTE_PGMEM_STATE", 2, 3, &umr_bitfield_default },
+	 { "DVMM_PIPE2_PTE_PGMEM_STATE", 4, 5, &umr_bitfield_default },
+	 { "DVMM_PIPE3_PTE_PGMEM_STATE", 6, 7, &umr_bitfield_default },
+	 { "DVMM_PIPE4_PTE_PGMEM_STATE", 8, 9, &umr_bitfield_default },
+	 { "DVMM_PIPE5_PTE_PGMEM_STATE", 10, 11, &umr_bitfield_default },
+	 { "DVMM_PIPE6_PTE_PGMEM_STATE", 12, 13, &umr_bitfield_default },
+	 { "DVMM_PIPE7_PTE_PGMEM_STATE", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
+	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
+	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[] = {
+	 { "CONNECTION_LIST_ENTRY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
+	 { "MISC", 0, 3, &umr_bitfield_default },
+	 { "COLOR", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
+	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
+	 { "LOCATION", 0, 5, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[] = {
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 8, 8, &umr_bitfield_default },
+	 { "DP_CONNECTION", 9, 9, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[] = {
+	 { "LFE_PLAYBACK_LEVEL", 0, 1, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 3, 6, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[] = {
+	 { "DESCRIPTOR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "FORMAT_CODE", 3, 6, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[] = {
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[] = {
+	 { "MULTICHANNEL23_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[] = {
+	 { "MULTICHANNEL45_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[] = {
+	 { "MULTICHANNEL67_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[] = {
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[] = {
+	 { "SINK_INFO_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[] = {
+	 { "SINK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
+	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
+	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
+	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
+	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[] = {
+	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
+	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
+	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
+	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
+	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
+	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
+	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
+	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MC_PCIE_CLIENT_CONFIG[] = {
+	 { "XDMA_MC_PCIE_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING1[] = {
+	 { "XDMA_LOCAL_ARRAY_MODE", 0, 3, &umr_bitfield_default },
+	 { "XDMA_LOCAL_TILE_SPLIT", 4, 6, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_WIDTH", 8, 9, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MACRO_TILE_ASPECT", 12, 13, &umr_bitfield_default },
+	 { "XDMA_LOCAL_NUM_BANKS", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING2[] = {
+	 { "XDMA_LOCAL_PIPE_INTERLEAVE_SIZE", 0, 2, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MICRO_TILE_MODE", 20, 22, &umr_bitfield_default },
+	 { "XDMA_LOCAL_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_INTERRUPT[] = {
+	 { "XDMA_MSTR_MEM_URGENT_STAT", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_MASK", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_ACK", 10, 10, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_STAT", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_MASK", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_ACK", 18, 18, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_STAT", 20, 20, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_MASK", 21, 21, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_ACK", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_CLOCK_GATING_CNTL[] = {
+	 { "XDMA_SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "XDMA_SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "XDMA_SCLK_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "XDMA_SCLK_REG_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1", 18, 18, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4", 21, 21, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5", 22, 22, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SDYN_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MSTAT_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SSTAT_GATE_DIS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MEM_POWER_CNTL[] = {
+	 { "XDMA_MEM_CORE_IDLE_STATE", 0, 1, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_IDLE_STATE", 2, 3, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_PCIE_STATE", 19, 20, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_PCIE_TRANS", 21, 21, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_RD_STATE", 22, 23, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_RD_TRANS", 25, 25, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_WR_STATE", 26, 27, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_WR_TRANS", 28, 28, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_BIF_STATE", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_BIF_TRANS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_BIF_STATUS[] = {
+	 { "XDMA_IF_BIF_ERROR_STATUS", 0, 3, &umr_bitfield_default },
+	 { "XDMA_IF_BIF_ERROR_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PERF_MEAS_STATUS[] = {
+	 { "XDMA_PERF_MEAS_STATUS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_STATUS[] = {
+	 { "XDMA_MC_PCIEWR_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_DATA[] = {
+	 { "XDMA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CNTL[] = {
+	 { "XDMA_MSTR_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_READY", 14, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_DEBUG_MODE", 18, 18, &umr_bitfield_default },
+	 { "XDMA_MSTR_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "XDMA_MSTR_BIF_STALL_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_STATUS[] = {
+	 { "XDMA_MSTR_VCOUNT_CURRENT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_WRITE_LINE_CURRENT", 16, 27, &umr_bitfield_default },
+	 { "XDMA_MSTR_STATUS_SELECT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
+	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[] = {
+	 { "CONNECTION_LIST_LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_PITCH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_PITCH", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CMD_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_CMD_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_CMD_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_CMD_STALL_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PCIE_NACK_STATUS[] = {
+	 { "XDMA_MSTR_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_NACK_STATUS[] = {
+	 { "XDMA_MSTR_MEM_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_VSYNC_GSL_CHECK[] = {
+	 { "XDMA_MSTR_VSYNC_GSL_CHECK_SEL", 0, 2, &umr_bitfield_default },
+	 { "XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT", 8, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_RBBMIF_RDWR_CNTL[] = {
+	 { "XDMA_RBBMIF_RDWR_DELAY", 0, 2, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_TIMEOUT_DELAY", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_CONTROL[] = {
+	 { "XDMA_PG_CONTROL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_WDATA[] = {
+	 { "XDMA_PG_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_STATUS[] = {
+	 { "XDMA_SERDES_RDATA", 0, 23, &umr_bitfield_default },
+	 { "XDMA_PGFSM_READ_READY", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SERDES_BUSY", 25, 25, &umr_bitfield_default },
+	 { "XDMA_SERDES_SMU_POWER_STATUS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_AON_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_AON_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_AON_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+	 { "XDMA_DEBUG_SEL", 9, 9, &umr_bitfield_default },
+	 { "XDMA_DEBUG_OUT_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_AON_TEST_DEBUG_DATA[] = {
+	 { "XDMA_AON_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[] = {
+	 { "PORTID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CUMULATIVE_REQUEST_COUNT[] = {
+	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL4[] = {
+	 { "INPUT_CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL4[] = {
+	 { "CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR3[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_STATUS[] = {
+	 { "FLUSH_STATUS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG4[] = {
+	 { "DCIO_DEBUG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR04[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ04[] = {
+	 { "SEQ_256K", 1, 1, &umr_bitfield_default },
+	 { "SEQ_ODDEVEN", 2, 2, &umr_bitfield_default },
+	 { "SEQ_CHAIN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
+	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PIPE_CNTL[] = {
+	 { "XDMA_MSTR_CACHE_LINES", 0, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_READ_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FRAME_MODE", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_INVALIDATE", 11, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_CHANNEL_ID", 12, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_FLIP_MODE", 15, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_MIN", 16, 23, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_ACTIVE", 24, 24, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FLUSHING", 25, 25, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FLIP_PENDING", 26, 26, &umr_bitfield_default },
+	 { "XDMA_MSTR_VSYNC_GSL_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "XDMA_MSTR_SUPERAA_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "XDMA_MSTR_HSYNC_GSL_GROUP", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_GSL_GROUP_MASTER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_READ_COMMAND[] = {
+	 { "XDMA_MSTR_REQUEST_SIZE", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_PREFETCH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CHANNEL_DIM[] = {
+	 { "XDMA_MSTR_CHANNEL_WIDTH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CHANNEL_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_HEIGHT[] = {
+	 { "XDMA_MSTR_ACTIVE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_FRAME_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_CACHE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_CACHE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE[] = {
+	 { "XDMA_MSTR_CACHE_PITCH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_TLB_PG_STATE", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_TLB_PG_TRANS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CHANNEL_START[] = {
+	 { "XDMA_MSTR_CHANNEL_START_X", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CHANNEL_START_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_STATUS[] = {
+	 { "XDMA_MSTR_PERFMEAS_DATA", 0, 23, &umr_bitfield_default },
+	 { "XDMA_MSTR_PERFMEAS_INDEX", 24, 26, &umr_bitfield_default },
+	 { "XDMA_MSTR_PERFMEAS_INDEX_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_CNTL[] = {
+	 { "XDMA_MSTR_CACHE_BW_MEAS_ITER", 0, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_BW_SEGID_SEL", 12, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_BW_COUNTER_RST", 17, 17, &umr_bitfield_default },
+	 { "XDMA_MSTR_LT_MEAS_ITER", 19, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_LT_COUNTER_RST", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
+	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
+	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CNTL[] = {
+	 { "XDMA_SLV_READ_LINES", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_READY", 9, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "XDMA_SLV_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SLV_REQ_MAXED_OUT", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SLV_WB_BURST_RESET", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_ENABLE[] = {
+	 { "GRPH_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_CONTROL[] = {
+	 { "GRPH_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "GRPH_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "GRPH_Z", 4, 5, &umr_bitfield_default },
+	 { "GRPH_BANK_WIDTH_L", 6, 7, &umr_bitfield_default },
+	 { "GRPH_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT_L", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT_L", 13, 15, &umr_bitfield_default },
+	 { "GRPH_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "GRPH_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT_L", 18, 19, &umr_bitfield_default },
+	 { "GRPH_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "GRPH_PIPE_CONFIG", 24, 28, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE_L", 29, 30, &umr_bitfield_default },
+	 { "GRPH_COLOR_EXPANSION_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_CONTROL_C[] = {
+	 { "GRPH_BANK_WIDTH_C", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT_C", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT_C", 13, 15, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT_C", 18, 19, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE_C", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_CONTROL_EXP[] = {
+	 { "VIDEO_FORMAT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DVMM_PTE_CONTROL_C[] = {
+	 { "DVMM_USE_SINGLE_PTE_C", 0, 0, &umr_bitfield_default },
+	 { "DVMM_PAGE_WIDTH_C", 1, 4, &umr_bitfield_default },
+	 { "DVMM_PAGE_HEIGHT_C", 5, 8, &umr_bitfield_default },
+	 { "DVMM_MIN_PTE_BEFORE_FLIP_C", 9, 18, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE0_C", 20, 20, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE1_C", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SWAP_CNTL[] = {
+	 { "GRPH_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "GRPH_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "GRPH_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_SLV_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PITCH_L[] = {
+	 { "GRPH_PITCH_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PITCH_C[] = {
+	 { "GRPH_PITCH_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_X_L[] = {
+	 { "GRPH_SURFACE_OFFSET_X_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_X_C[] = {
+	 { "GRPH_SURFACE_OFFSET_X_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_Y_L[] = {
+	 { "GRPH_SURFACE_OFFSET_Y_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_Y_C[] = {
+	 { "GRPH_SURFACE_OFFSET_Y_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_START_L[] = {
+	 { "GRPH_X_START_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_START_C[] = {
+	 { "GRPH_X_START_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_START_L[] = {
+	 { "GRPH_Y_START_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_START_C[] = {
+	 { "GRPH_Y_START_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_SLS_PITCH[] = {
+	 { "XDMA_SLV_SLS_PITCH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_SLS_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_END_L[] = {
+	 { "GRPH_X_END_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_END_C[] = {
+	 { "GRPH_X_END_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_END_L[] = {
+	 { "GRPH_Y_END_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_END_C[] = {
+	 { "GRPH_Y_END_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_UPDATE[] = {
+	 { "GRPH_MODE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "GRPH_MODE_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_TAKEN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SURFACE_IGNORE_UPDATE_LOCK", 20, 20, &umr_bitfield_default },
+	 { "GRPH_MODE_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DVMM_PTE_CONTROL[] = {
+	 { "DVMM_USE_SINGLE_PTE", 0, 0, &umr_bitfield_default },
+	 { "DVMM_PAGE_WIDTH", 1, 4, &umr_bitfield_default },
+	 { "DVMM_PAGE_HEIGHT", 5, 8, &umr_bitfield_default },
+	 { "DVMM_MIN_PTE_BEFORE_FLIP", 9, 18, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE0", 20, 20, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE1", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DVMM_PTE_ARB_CONTROL[] = {
+	 { "DVMM_PTE_REQ_PER_CHUNK", 0, 5, &umr_bitfield_default },
+	 { "DVMM_MAX_PTE_REQ_OUTSTANDING", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_INTERRUPT_STATUS[] = {
+	 { "GRPH_PFLIP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_INTERRUPT_CONTROL[] = {
+	 { "GRPH_PFLIP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DVMM_PTE_ARB_CONTROL_C[] = {
+	 { "DVMM_PTE_REQ_PER_CHUNK_C", 0, 5, &umr_bitfield_default },
+	 { "DVMM_MAX_PTE_REQ_OUTSTANDING_C", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_STEREOSYNC_FLIP[] = {
+	 { "GRPH_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_FLIP_MODE", 4, 5, &umr_bitfield_default },
+	 { "GRPH_STACK_INTERLACE_FLIP_EN", 8, 8, &umr_bitfield_default },
+	 { "GRPH_STACK_INTERLACE_FLIP_MODE", 12, 13, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_PENDING", 18, 18, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_PENDING", 19, 19, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_FLIP_CONTROL[] = {
+	 { "GRPH_SURFACE_UPDATE_PENDING_MODE", 0, 0, &umr_bitfield_default },
+	 { "UNP_DEBUG_SG", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_URGENT_CNTL[] = {
+	 { "XDMA_SLV_READ_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_CONTROL[] = {
+	 { "UNP_CRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "UNP_CRC_SOURCE_SEL", 2, 4, &umr_bitfield_default },
+	 { "UNP_CRC_LINE_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_MASK[] = {
+	 { "UNP_CRC_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_CURRENT[] = {
+	 { "UNP_CRC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_LAST[] = {
+	 { "UNP_CRC_LAST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[] = {
+	 { "UNP_LB_GAP_BETWEEN_CHUNK", 4, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_HW_ROTATION[] = {
+	 { "ROTATION_ANGLE", 0, 2, &umr_bitfield_default },
+	 { "PIXEL_DROP", 4, 4, &umr_bitfield_default },
+	 { "BUFFER_MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DEBUG[] = {
+	 { "UNP_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DEBUG2[] = {
+	 { "UNP_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_TEST_DEBUG_INDEX[] = {
+	 { "UNP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "UNP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_TEST_DEBUG_DATA[] = {
+	 { "UNP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT[] = {
+	 { "UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L", 0, 7, &umr_bitfield_default },
+	 { "UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DVMM_DEBUG[] = {
+	 { "UNP_L_DVMM_DEBUG", 0, 15, &umr_bitfield_default },
+	 { "UNP_C_DVMM_DEBUG", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DATA_FORMAT[] = {
+	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "PIXEL_EXPAN_MODE", 2, 2, &umr_bitfield_default },
+	 { "INTERLEAVE_EN", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_REDUCE_MODE", 4, 4, &umr_bitfield_default },
+	 { "DYNAMIC_PIXEL_DEPTH", 5, 5, &umr_bitfield_default },
+	 { "DITHER_EN", 6, 6, &umr_bitfield_default },
+	 { "DOWNSCALE_PREFETCH_EN", 7, 7, &umr_bitfield_default },
+	 { "PREFETCH", 12, 12, &umr_bitfield_default },
+	 { "REQUEST_MODE", 24, 24, &umr_bitfield_default },
+	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_MEMORY_CTRL[] = {
+	 { "LB_MEMORY_SIZE", 0, 11, &umr_bitfield_default },
+	 { "LB_NUM_PARTITIONS", 16, 19, &umr_bitfield_default },
+	 { "LB_MEMORY_CONFIG", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_MEMORY_SIZE_STATUS[] = {
+	 { "LB_MEMORY_SIZE_STATUS", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DESKTOP_HEIGHT[] = {
+	 { "DESKTOP_HEIGHT", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WRITE_URGENT_CNTL[] = {
+	 { "XDMA_SLV_WRITE_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_STALL_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE_START_END[] = {
+	 { "VLINE_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE2_START_END[] = {
+	 { "VLINE2_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE2_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE2_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_V_COUNTER[] = {
+	 { "V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SNAPSHOT_V_COUNTER[] = {
+	 { "SNAPSHOT_V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_V_COUNTER_CHROMA[] = {
+	 { "V_COUNTER_CHROMA", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SNAPSHOT_V_COUNTER_CHROMA[] = {
+	 { "SNAPSHOT_V_COUNTER_CHROMA", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_INTERRUPT_MASK[] = {
+	 { "VBLANK_INTERRUPT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_MASK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE_STATUS[] = {
+	 { "VLINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE2_STATUS[] = {
+	 { "VLINE2_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE2_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VBLANK_STATUS[] = {
+	 { "VBLANK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VBLANK_ACK", 4, 4, &umr_bitfield_default },
+	 { "VBLANK_STAT", 12, 12, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SYNC_RESET_SEL[] = {
+	 { "LB_SYNC_RESET_SEL", 0, 1, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_SEL2", 4, 4, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LB_SYNC_DURATION", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_R_CR[] = {
+	 { "LB_BLACK_KEYER_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_G_Y[] = {
+	 { "LB_BLACK_KEYER_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_B_CB[] = {
+	 { "LB_BLACK_KEYER_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_CTRL[] = {
+	 { "LB_KEYER_COLOR_EN", 0, 0, &umr_bitfield_default },
+	 { "LB_KEYER_COLOR_REP_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_R_CR[] = {
+	 { "LB_KEYER_COLOR_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WB_RATE_CNTL[] = {
+	 { "XDMA_SLV_WB_BURST_SIZE", 0, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_WB_BURST_PERIOD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_G_Y[] = {
+	 { "LB_KEYER_COLOR_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_B_CB[] = {
+	 { "LB_KEYER_COLOR_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_R_CR[] = {
+	 { "LB_KEYER_COLOR_REP_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_G_Y[] = {
+	 { "LB_KEYER_COLOR_REP_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_B_CB[] = {
+	 { "LB_KEYER_COLOR_REP_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_LEVEL_STATUS[] = {
+	 { "REQ_FIFO_LEVEL", 0, 5, &umr_bitfield_default },
+	 { "REQ_FIFO_FULL_CNTL", 10, 15, &umr_bitfield_default },
+	 { "DATA_BUFFER_LEVEL", 16, 27, &umr_bitfield_default },
+	 { "DATA_FIFO_FULL_CNTL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_URGENCY_CTRL[] = {
+	 { "LB_BUFFER_URGENCY_MARK_ON", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_MARK_OFF", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_URGENCY_STATUS[] = {
+	 { "LB_BUFFER_URGENCY_LEVEL", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_STAT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_STATUS[] = {
+	 { "LB_BUFFER_EMPTY_MARGIN", 0, 3, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_STAT", 4, 4, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_ACK", 12, 12, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_STAT", 16, 16, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_ACK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_NO_OUTSTANDING_REQ_STATUS[] = {
+	 { "LB_NO_OUTSTANDING_REQ_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG[] = {
+	 { "LB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG2[] = {
+	 { "LB_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG3[] = {
+	 { "LB_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_MINMAX[] = {
+	 { "XDMA_SLV_READ_LATENCY_MIN", 0, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_TEST_DEBUG_INDEX[] = {
+	 { "LB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "LB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_TEST_DEBUG_DATA[] = {
+	 { "LB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_AVE[] = {
+	 { "XDMA_SLV_READ_LATENCY_ACC", 0, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_COUNT", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_COEF_RAM_SELECT[] = {
+	 { "SCL_C_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default },
+	 { "SCL_C_RAM_PHASE", 8, 14, &umr_bitfield_default },
+	 { "SCL_C_RAM_FILTER_TYPE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_COEF_RAM_TAP_DATA[] = {
+	 { "SCL_C_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
+	 { "SCL_C_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE[] = {
+	 { "SCL_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_MODE_C", 1, 1, &umr_bitfield_default },
+	 { "SCL_PSCL_EN", 4, 4, &umr_bitfield_default },
+	 { "SCL_PSCL_EN_C", 5, 5, &umr_bitfield_default },
+	 { "SCL_INTERLACE_SOURCE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TAP_CONTROL[] = {
+	 { "SCL_V_NUM_OF_TAPS", 0, 2, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS", 4, 6, &umr_bitfield_default },
+	 { "SCL_V_NUM_OF_TAPS_C", 8, 10, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS_C", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_CONTROL[] = {
+	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_EARLY_EOL_MODE", 4, 4, &umr_bitfield_default },
+	 { "SCL_TOTAL_PHASE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MANUAL_REPLICATE_CONTROL[] = {
+	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
+	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_AUTOMATIC_MODE_CONTROL[] = {
+	 { "SCL_V_CALC_AUTO_RATIO_EN", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_CALC_AUTO_RATIO_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_CONTROL[] = {
+	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_SCALE_RATIO[] = {
+	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT[] = {
+	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_SCALE_RATIO_C[] = {
+	 { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT_C[] = {
+	 { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_CONTROL[] = {
+	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_SCALE_RATIO[] = {
+	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT[] = {
+	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_BOT[] = {
+	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_PCIE_NACK_STATUS[] = {
+	 { "XDMA_SLV_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_SCALE_RATIO_C[] = {
+	 { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_C[] = {
+	 { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_C", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_BOT_C[] = {
+	 { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT_C", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_ROUND_OFFSET[] = {
+	 { "SCL_ROUND_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
+	 { "SCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_UPDATE[] = {
+	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "SCL_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "SCL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "SCL_COEF_UPDATE_COMPLETE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_ALU_CONTROL[] = {
+	 { "SCL_ALU_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START[] = {
+	 { "VIEWPORT_Y_START", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_SECONDARY[] = {
+	 { "VIEWPORT_Y_START_SECONDARY", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_SIZE[] = {
+	 { "VIEWPORT_HEIGHT", 0, 12, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_C[] = {
+	 { "VIEWPORT_Y_START_C", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_C", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_SECONDARY_C[] = {
+	 { "VIEWPORT_Y_START_SECONDARY_C", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY_C", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_SIZE_C[] = {
+	 { "VIEWPORT_HEIGHT_C", 0, 12, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH_C", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[] = {
+	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[] = {
+	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET1[] = {
+	 { "SCL_MODE_CHANGE", 0, 0, &umr_bitfield_default },
+	 { "SCL_MODE_CHANGE_ACK", 4, 4, &umr_bitfield_default },
+	 { "SCL_ALU_H_SCALE_RATIO", 7, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET2[] = {
+	 { "SCL_ALU_V_SCALE_RATIO", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_NACK_STATUS[] = {
+	 { "XDMA_SLV_MEM_NACK_TAG", 0, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK", 16, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK_CLR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET3[] = {
+	 { "SCL_ALU_SOURCE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "SCL_ALU_SOURCE_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_MASK[] = {
+	 { "SCL_MODE_CHANGE_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT_BOT[] = {
+	 { "SCL_H_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT_BOT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT_BOT_C[] = {
+	 { "SCL_H_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_DEBUG2[] = {
+	 { "SCL_DEBUG_REQ_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_DEBUG_EOF_MODE", 1, 2, &umr_bitfield_default },
+	 { "SCL_DEBUG2", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_DEBUG[] = {
+	 { "SCL_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TEST_DEBUG_INDEX[] = {
+	 { "SCL_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SCL_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TEST_DEBUG_DATA[] = {
+	 { "SCL_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_RDRET_BUF_STATUS[] = {
+	 { "XDMA_SLV_RDRET_FREE_ENTRIES", 0, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_BUF_SIZE", 12, 21, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_PG_STATE", 22, 23, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_PG_TRANS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_UPDATE[] = {
+	 { "COL_MAN_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "COL_MAN_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "COL_MAN_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "COL_MAN_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_INPUT_CSC_CONTROL[] = {
+	 { "INPUT_CSC_MODE", 0, 1, &umr_bitfield_default },
+	 { "INPUT_CSC_INPUT_TYPE", 8, 9, &umr_bitfield_default },
+	 { "INPUT_CSC_CONVERSION_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12_A[] = {
+	 { "INPUT_CSC_C11_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14_A[] = {
+	 { "INPUT_CSC_C13_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22_A[] = {
+	 { "INPUT_CSC_C21_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24_A[] = {
+	 { "INPUT_CSC_C23_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32_A[] = {
+	 { "INPUT_CSC_C31_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34_A[] = {
+	 { "INPUT_CSC_C33_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12_B[] = {
+	 { "INPUT_CSC_C11_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14_B[] = {
+	 { "INPUT_CSC_C13_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22_B[] = {
+	 { "INPUT_CSC_C21_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24_B[] = {
+	 { "INPUT_CSC_C23_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_TIMER[] = {
+	 { "XDMA_SLV_READ_LATENCY_TIMER", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32_B[] = {
+	 { "INPUT_CSC_C31_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34_B[] = {
+	 { "INPUT_CSC_C33_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_CONTROL[] = {
+	 { "PRESCALE_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_R[] = {
+	 { "PRESCALE_BIAS_R", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_G[] = {
+	 { "PRESCALE_BIAS_G", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_B[] = {
+	 { "PRESCALE_BIAS_B", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_OUTPUT_CSC_CONTROL[] = {
+	 { "OUTPUT_CSC_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12_A[] = {
+	 { "OUTPUT_CSC_C11_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14_A[] = {
+	 { "OUTPUT_CSC_C13_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22_A[] = {
+	 { "OUTPUT_CSC_C21_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24_A[] = {
+	 { "OUTPUT_CSC_C23_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32_A[] = {
+	 { "OUTPUT_CSC_C31_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34_A[] = {
+	 { "OUTPUT_CSC_C33_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12_B[] = {
+	 { "OUTPUT_CSC_C11_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14_B[] = {
+	 { "OUTPUT_CSC_C13_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22_B[] = {
+	 { "OUTPUT_CSC_C21_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_FLIP_PENDING[] = {
+	 { "XDMA_SLV_FLIP_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24_B[] = {
+	 { "OUTPUT_CSC_C23_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32_B[] = {
+	 { "OUTPUT_CSC_C31_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34_B[] = {
+	 { "OUTPUT_CSC_C33_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_CONTROL[] = {
+	 { "DENORM_MODE", 0, 1, &umr_bitfield_default },
+	 { "DENORM_10BIT_OUT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_R_CR[] = {
+	 { "RANGE_CLAMP_MAX_R_CR", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_R_CR", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_G_Y[] = {
+	 { "RANGE_CLAMP_MAX_G_Y", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_G_Y", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_B_CB[] = {
+	 { "RANGE_CLAMP_MAX_B_CB", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_B_CB", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_FP_CONVERTED_FIELD[] = {
+	 { "COL_MAN_FP_CONVERTED_FIELD_DATA", 0, 17, &umr_bitfield_default },
+	 { "COL_MAN_FP_CONVERTED_FIELD_INDEX", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CONTROL[] = {
+	 { "GAMMA_CORR_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_INDEX[] = {
+	 { "GAMMA_CORR_LUT_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_DATA[] = {
+	 { "GAMMA_CORR_LUT_DATA", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_WRITE_EN_MASK[] = {
+	 { "GAMMA_CORR_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_START_CNTL[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_SLOPE_CNTL[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_END_CNTL1[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_END_CNTL2[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_0_1[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_2_3[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_4_5[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_6_7[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_8_9[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_10_11[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_12_13[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_14_15[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_START_CNTL[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_SLOPE_CNTL[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_END_CNTL1[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_END_CNTL2[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_0_1[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_2_3[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_4_5[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_6_7[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_8_9[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_10_11[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_12_13[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_14_15[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPACK_FIFO_ERROR[] = {
+	 { "PACK_FIFO_L_UNDERFLOW_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "PACK_FIFO_L_UNDERFLOW_ACK", 1, 1, &umr_bitfield_default },
+	 { "PACK_FIFO_C_UNDERFLOW_OCCURED", 8, 8, &umr_bitfield_default },
+	 { "PACK_FIFO_C_UNDERFLOW_ACK", 9, 9, &umr_bitfield_default },
+	 { "PACK_FIFO_L_OVERFLOW_OCCURED", 16, 16, &umr_bitfield_default },
+	 { "PACK_FIFO_L_OVERFLOW_ACK", 17, 17, &umr_bitfield_default },
+	 { "PACK_FIFO_C_OVERFLOW_OCCURED", 24, 24, &umr_bitfield_default },
+	 { "PACK_FIFO_C_OVERFLOW_ACK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_FIFO_ERROR[] = {
+	 { "OUTPUT_FIFO_UNDERFLOW_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "OUTPUT_FIFO_UNDERFLOW_ACK", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_FIFO_OVERFLOW_OCCURED", 8, 8, &umr_bitfield_default },
+	 { "OUTPUT_FIFO_OVERFLOW_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_AUTOFILL[] = {
+	 { "INPUT_GAMMA_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_AUTOFILL_DONE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_RW_INDEX[] = {
+	 { "INPUT_GAMMA_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_SEQ_COLOR[] = {
+	 { "INPUT_GAMMA_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_PWL_DATA[] = {
+	 { "INPUT_GAMMA_LUT_BASE", 0, 15, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_DELTA", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_30_COLOR[] = {
+	 { "INPUT_GAMMA_LUT_COLOR_10_BLUE", 0, 9, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_COLOR_10_GREEN", 10, 19, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_COLOR_10_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_INPUT_GAMMA_CONTROL1[] = {
+	 { "INPUT_GAMMA_MODE", 0, 1, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_10BIT_BYPASS_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_INPUT_GAMMA_CONTROL2[] = {
+	 { "INPUT_GAMMA_INC_B", 1, 4, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_B_SIGNED_EN", 5, 5, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_B_FORMAT", 6, 7, &umr_bitfield_default },
+	 { "INPUT_GAMMA_INC_G", 8, 11, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_G_SIGNED_EN", 12, 12, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_G_FORMAT", 13, 14, &umr_bitfield_default },
+	 { "INPUT_GAMMA_INC_R", 15, 18, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_R_SIGNED_EN", 19, 19, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_R_FORMAT", 20, 21, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_RW_MODE", 22, 22, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_WRITE_EN_MASK", 23, 25, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_BW_OFFSETS_B[] = {
+	 { "INPUT_GAMMA_BLACK_OFFSET_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_GAMMA_WHITE_OFFSET_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_BW_OFFSETS_G[] = {
+	 { "INPUT_GAMMA_BLACK_OFFSET_G", 0, 15, &umr_bitfield_default },
+	 { "INPUT_GAMMA_WHITE_OFFSET_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_BW_OFFSETS_R[] = {
+	 { "INPUT_GAMMA_BLACK_OFFSET_R", 0, 15, &umr_bitfield_default },
+	 { "INPUT_GAMMA_WHITE_OFFSET_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_DEBUG_CONTROL[] = {
+	 { "COL_MAN_GLOBAL_PASSTHROUGH_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_TEST_DEBUG_INDEX[] = {
+	 { "COL_MAN_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "COL_MAN_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_TEST_DEBUG_DATA[] = {
+	 { "COL_MAN_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_CLOCK_CONTROL[] = {
+	 { "DISPCLK_R_DCFEV_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "DISPCLK_G_UNP_GATE_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_SCLV_GATE_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_COL_MAN_GATE_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "DISPCLK_G_PSCLV_GATE_DISABLE", 13, 13, &umr_bitfield_default },
+	 { "DISPCLK_G_CRTC_GATE_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DCFEV_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DCFEV_CLOCK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_SOFT_RESET[] = {
+	 { "UNP_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "UNP_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCLV_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCLV_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "PSCLV_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "COL_MAN_SOFT_RESET", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_CLOCK_CONTROL[] = {
+	 { "DMIFV_SCLK_G_DMIFTRK_GATE_DIS", 3, 3, &umr_bitfield_default },
+	 { "DMIFV_DISPCLK_G_DMIFVL_GATE_DIS", 4, 4, &umr_bitfield_default },
+	 { "DMIFV_DISPCLK_G_DMIFVC_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIFV_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DMIFV_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DMIFV_BUFFER_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DBG_CONFIG[] = {
+	 { "DCFEV_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_DBG_SEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_MEM_PWR_CTRL[] = {
+	 { "DMIFV_MEM_PWR_SEL", 0, 1, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_0_FORCE", 2, 2, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_1_FORCE", 3, 3, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_2_FORCE", 4, 4, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_3_FORCE", 5, 5, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_4_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_0_FORCE", 7, 7, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_1_FORCE", 8, 8, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_2_FORCE", 9, 9, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_3_FORCE", 10, 10, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_4_FORCE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_MEM_PWR_STATUS[] = {
+	 { "DMIFV_MEM_PWR_LUMA_0_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_1_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_2_STATE", 4, 5, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_3_STATE", 6, 7, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_4_STATE", 8, 9, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_0_STATE", 10, 11, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_1_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_2_STATE", 14, 15, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_3_STATE", 16, 17, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_4_STATE", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_MEM_PWR_CTRL[] = {
+	 { "COL_MAN_GAMMA_CORR_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "COL_MAN_GAMMA_CORR_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "COL_MAN_INPUT_GAMMA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "SCLV_COEFF_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "SCLV_COEFF_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "LBV0_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "LBV0_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "LBV1_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "LBV1_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LBV2_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "LBV2_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_MEM_PWR_CTRL2[] = {
+	 { "COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
+	 { "COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL", 2, 3, &umr_bitfield_default },
+	 { "SCLV_COEFF_MEM_PWR_MODE_SEL", 4, 5, &umr_bitfield_default },
+	 { "LBV_MEM_PWR_MODE_SEL", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_MEM_PWR_STATUS[] = {
+	 { "COL_MAN_GAMMA_CORR_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "COL_MAN_INPUT_GAMMA_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "SCLV_COEFF_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "LBV0_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "LBV1_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "LBV2_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "LBV3_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_DEBUG[] = {
+	 { "DMIFV_DEBUG_BUS_SEL", 0, 3, &umr_bitfield_default },
+	 { "DMIFV_DEBUG_LUMA_VS_CHROMA", 4, 4, &umr_bitfield_default },
+	 { "DMIFV_DEBUG_LOWER_UPPER", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_MISC[] = {
+	 { "DCFEV_DPG_ALLOW_SR_ECO_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CHANNEL_CNTL[] = {
+	 { "XDMA_SLV_CHANNEL_WEIGHT", 0, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_STOP_TRANSFER", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_CHANNEL_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_CHANNEL_ACTIVE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_ARBITRATION_CONTROL1[] = {
+	 { "PIXEL_DURATION", 0, 15, &umr_bitfield_default },
+	 { "BASE_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_ARBITRATION_CONTROL2[] = {
+	 { "TIME_WEIGHT", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_WATERMARK_MASK_CONTROL[] = {
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK", 0, 1, &umr_bitfield_default },
+	 { "URGENCY_WATERMARK_MASK", 8, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 16, 17, &umr_bitfield_default },
+	 { "DISABLE_FLIP_URGENT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_URGENCY_CONTROL[] = {
+	 { "URGENCY_LOW_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_HIGH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_DPM_CONTROL[] = {
+	 { "DPM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCLK_CHANGE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCLK_CHANGE_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK_MASK", 12, 13, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_STUTTER_CONTROL[] = {
+	 { "STUTTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON", 11, 11, &umr_bitfield_default },
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL[] = {
+	 { "NB_PSTATE_CHANGE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_FORCE_ON", 9, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_ALLOW_FOR_URGENT", 10, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH[] = {
+	 { "STUTTER_ENABLE_NONLPTCH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR_NONLPTCH", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON_NONLPTCH", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA_NONLPTCH", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC_NONLPTCH", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON_NONLPTCH", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_REPEATER_PROGRAM[] = {
+	 { "REG_DPG_DMIFRC_REPEATER", 0, 2, &umr_bitfield_default },
+	 { "REG_DMIFRC_DPG_REPEATER", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_HW_DEBUG_A[] = {
+	 { "DPG_HW_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_HW_DEBUG_B[] = {
+	 { "DPG_HW_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_HW_DEBUG_11[] = {
+	 { "DPG_HW_DEBUG_11", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_CHK_PRE_PROC_CNTL[] = {
+	 { "DPG_DISABLE_DMIF_BUF_CHK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_ARBITRATION_CONTROL1[] = {
+	 { "PIXEL_DURATION", 0, 15, &umr_bitfield_default },
+	 { "BASE_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_ARBITRATION_CONTROL2[] = {
+	 { "TIME_WEIGHT", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_WATERMARK_MASK_CONTROL[] = {
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK", 0, 1, &umr_bitfield_default },
+	 { "URGENCY_WATERMARK_MASK", 8, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 16, 17, &umr_bitfield_default },
+	 { "DISABLE_FLIP_URGENT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_URGENCY_CONTROL[] = {
+	 { "URGENCY_LOW_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_HIGH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_DPM_CONTROL[] = {
+	 { "DPM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCLK_CHANGE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCLK_CHANGE_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK_MASK", 12, 13, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_STUTTER_CONTROL[] = {
+	 { "STUTTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON", 11, 11, &umr_bitfield_default },
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL[] = {
+	 { "NB_PSTATE_CHANGE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_FORCE_ON", 9, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_ALLOW_FOR_URGENT", 10, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH[] = {
+	 { "STUTTER_ENABLE_NONLPTCH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR_NONLPTCH", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON_NONLPTCH", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA_NONLPTCH", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC_NONLPTCH", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON_NONLPTCH", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_REPEATER_PROGRAM[] = {
+	 { "REG_DPG_DMIFRC_REPEATER", 0, 2, &umr_bitfield_default },
+	 { "REG_DMIFRC_DPG_REPEATER", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_HW_DEBUG_A[] = {
+	 { "DPG_HW_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_HW_DEBUG_B[] = {
+	 { "DPG_HW_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_HW_DEBUG_11[] = {
+	 { "DPG_HW_DEBUG_11", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_CHK_PRE_PROC_CNTL[] = {
+	 { "DPG_DISABLE_DMIF_BUF_CHK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV_TEST_DEBUG_INDEX[] = {
+	 { "DPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV_TEST_DEBUG_DATA[] = {
+	 { "DPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_CONTROL[] = {
+	 { "BLND_GLOBAL_GAIN", 0, 7, &umr_bitfield_default },
+	 { "BLND_MODE", 8, 9, &umr_bitfield_default },
+	 { "BLND_STEREO_TYPE", 10, 11, &umr_bitfield_default },
+	 { "BLND_STEREO_POLARITY", 12, 12, &umr_bitfield_default },
+	 { "BLND_FEEDTHROUGH_EN", 13, 13, &umr_bitfield_default },
+	 { "BLND_ALPHA_MODE", 16, 17, &umr_bitfield_default },
+	 { "BLND_MULTIPLIED_MODE", 20, 20, &umr_bitfield_default },
+	 { "BLND_GLOBAL_ALPHA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_SM_CONTROL2[] = {
+	 { "SM_MODE", 0, 2, &umr_bitfield_default },
+	 { "SM_FRAME_ALTERNATE", 4, 4, &umr_bitfield_default },
+	 { "SM_FIELD_ALTERNATE", 5, 5, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
+	 { "SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_CONTROL2[] = {
+	 { "PTI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PTI_NEW_PIXEL_GAP", 4, 5, &umr_bitfield_default },
+	 { "BLND_NEW_PIXEL_MODE", 6, 6, &umr_bitfield_default },
+	 { "BLND_SUPERAA_DEGAMMA_EN", 7, 7, &umr_bitfield_default },
+	 { "BLND_SUPERAA_REGAMMA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_UPDATE[] = {
+	 { "BLND_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "BLND_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "BLND_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_UNDERFLOW_INTERRUPT[] = {
+	 { "BLND_UNDERFLOW_INT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_PIPE_INDEX", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_V_UPDATE_LOCK[] = {
+	 { "BLND_DCP_GRPH_V_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BLND_DCP_GRPH_SURF_V_UPDATE_LOCK", 1, 1, &umr_bitfield_default },
+	 { "BLND_DCP_CUR_V_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "BLND_DCP_CUR2_V_UPDATE_LOCK", 24, 24, &umr_bitfield_default },
+	 { "BLND_SCL_V_UPDATE_LOCK", 28, 28, &umr_bitfield_default },
+	 { "BLND_BLND_V_UPDATE_LOCK", 29, 29, &umr_bitfield_default },
+	 { "BLND_V_UPDATE_LOCK_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_DEBUG[] = {
+	 { "BLND_CNV_MUX_SELECT", 0, 0, &umr_bitfield_default },
+	 { "BLND_DEBUG", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_TEST_DEBUG_INDEX[] = {
+	 { "BLND_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "BLND_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_TEST_DEBUG_DATA[] = {
+	 { "BLND_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_REG_UPDATE_STATUS[] = {
+	 { "DCP_BLNDC_GRPH_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
+	 { "DCP_BLNDC_GRPH_SURF_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_SURF_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
+	 { "DCP_BLNDC_CUR_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
+	 { "DCP_BLNDO_CUR_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
+	 { "SCL_BLNDC_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "SCL_BLNDO_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
+	 { "BLND_BLNDC_UPDATE_PENDING", 10, 10, &umr_bitfield_default },
+	 { "BLND_BLNDO_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_3D_STRUCTURE_CONTROL[] = {
+	 { "CRTC_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_EN_DB", 4, 4, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_GSL_VSYNC_GAP[] = {
+	 { "CRTC_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_GSL_WINDOW[] = {
+	 { "CRTC_GSL_WINDOW_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_GSL_WINDOW_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_GSL_CONTROL[] = {
+	 { "CRTC_GSL_CHECK_LINE_NUM", 0, 13, &umr_bitfield_default },
+	 { "CRTC_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_BLANK_EARLY_NUM[] = {
+	 { "CRTC_H_BLANK_EARLY_NUM", 0, 9, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_EARLY_NUM_DIS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_TOTAL[] = {
+	 { "CRTC_H_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_BLANK_START_END[] = {
+	 { "CRTC_H_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_SYNC_A[] = {
+	 { "CRTC_H_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_SYNC_A_CNTL[] = {
+	 { "CRTC_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_SYNC_B[] = {
+	 { "CRTC_H_SYNC_B_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_SYNC_B_CNTL[] = {
+	 { "CRTC_H_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_B_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VBI_END[] = {
+	 { "CRTC_VBI_V_END", 0, 13, &umr_bitfield_default },
+	 { "CRTC_VBI_H_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_TOTAL[] = {
+	 { "CRTC_V_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_TOTAL_MIN[] = {
+	 { "CRTC_V_TOTAL_MIN", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_TOTAL_MAX[] = {
+	 { "CRTC_V_TOTAL_MAX", 0, 13, &umr_bitfield_default },
+	 { "CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_TOTAL_CONTROL[] = {
+	 { "CRTC_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_TOTAL_MAX_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_ON_EVENT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_TO_MASTER_VSYNC", 12, 12, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK_EN", 15, 15, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_TOTAL_INT_STATUS[] = {
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VSYNC_NOM_INT_STATUS[] = {
+	 { "CRTC_VSYNC_NOM", 0, 0, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_BLANK_START_END[] = {
+	 { "CRTC_V_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_SYNC_A[] = {
+	 { "CRTC_V_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_SYNC_A_CNTL[] = {
+	 { "CRTC_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_SYNC_B[] = {
+	 { "CRTC_V_SYNC_B_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_B_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_SYNC_B_CNTL[] = {
+	 { "CRTC_V_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_DTMTEST_CNTL[] = {
+	 { "CRTC_DTMTEST_CRTC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_CLK_DIV", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_DTMTEST_STATUS_POSITION[] = {
+	 { "CRTC_DTMTEST_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TRIGA_CNTL[] = {
+	 { "CRTC_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGA_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TRIGA_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TRIGB_CNTL[] = {
+	 { "CRTC_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGB_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TRIGB_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_FORCE_COUNT_NOW_CNTL[] = {
+	 { "CRTC_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_FLOW_CONTROL[] = {
+	 { "CRTC_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STEREO_FORCE_NEXT_EYE[] = {
+	 { "CRTC_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_AVSYNC_COUNTER[] = {
+	 { "CRTC_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CONTROL[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SYNC_RESET_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
+	 { "CRTC_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
+	 { "CRTC_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_HBLANK_EARLY_CONTROL", 20, 22, &umr_bitfield_default },
+	 { "CRTC_DISP_READ_REQUEST_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SOF_PULL_EN", 29, 29, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LOCK_SNAPSHOT", 30, 30, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_VSYNC_N_HSYNC_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_BLANK_CONTROL[] = {
+	 { "CRTC_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_INTERLACE_CONTROL[] = {
+	 { "CRTC_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_INTERLACE_STATUS[] = {
+	 { "CRTC_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_FIELD_INDICATION_CONTROL[] = {
+	 { "CRTC_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_PIXEL_DATA_READBACK0[] = {
+	 { "CRTC_PIXEL_DATA_BLUE_CB", 0, 11, &umr_bitfield_default },
+	 { "CRTC_PIXEL_DATA_GREEN_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_PIXEL_DATA_READBACK1[] = {
+	 { "CRTC_PIXEL_DATA_RED_CR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STATUS[] = {
+	 { "CRTC_V_BLANK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A", 2, 2, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "CRTC_V_START_LINE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_H_BLANK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STATUS_POSITION[] = {
+	 { "CRTC_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_NOM_VERT_POSITION[] = {
+	 { "CRTC_VERT_COUNT_NOM", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STATUS_FRAME_COUNT[] = {
+	 { "CRTC_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STATUS_VF_COUNT[] = {
+	 { "CRTC_VF_COUNT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STATUS_HV_COUNT[] = {
+	 { "CRTC_HV_COUNT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_COUNT_CONTROL[] = {
+	 { "CRTC_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_COUNT_RESET[] = {
+	 { "CRTC_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
+	 { "CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VERT_SYNC_CONTROL[] = {
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "CRTC_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STEREO_STATUS[] = {
+	 { "CRTC_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
+	 { "CRTC_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STEREO_CONTROL[] = {
+	 { "CRTC_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 13, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT_POLARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
+	 { "CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
+	 { "CRTC_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
+	 { "CRTC_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
+	 { "CRTC_STEREO_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_SNAPSHOT_STATUS[] = {
+	 { "CRTC_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_SNAPSHOT_CONTROL[] = {
+	 { "CRTC_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_SNAPSHOT_POSITION[] = {
+	 { "CRTC_SNAPSHOT_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_SNAPSHOT_FRAME[] = {
+	 { "CRTC_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_START_LINE_CONTROL[] = {
+	 { "CRTC_PROGRESSIVE_START_LINE_EARLY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_START_LINE_EARLY", 1, 1, &umr_bitfield_default },
+	 { "CRTC_PREFETCH_EN", 2, 2, &umr_bitfield_default },
+	 { "CRTC_LEGACY_REQUESTOR_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_ADVANCED_START_LINE_POSITION", 12, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_INTERRUPT_CONTROL[] = {
+	 { "CRTC_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_MSK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_TYPE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_UPDATE_LOCK[] = {
+	 { "CRTC_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_DOUBLE_BUFFER_CONTROL[] = {
+	 { "CRTC_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CRTC_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VGA_PARAMETER_CAPTURE_MODE[] = {
+	 { "CRTC_VGA_PARAMETER_CAPTURE_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TEST_PATTERN_CONTROL[] = {
+	 { "CRTC_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TEST_PATTERN_PARAMETERS[] = {
+	 { "CRTC_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TEST_PATTERN_COLOR[] = {
+	 { "CRTC_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_MASTER_UPDATE_LOCK[] = {
+	 { "MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "GSL_CONTROL_MASTER_UPDATE_LOCK", 8, 8, &umr_bitfield_default },
+	 { "UNDERFLOW_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_MASTER_UPDATE_MODE[] = {
+	 { "MASTER_UPDATE_MODE", 0, 2, &umr_bitfield_default },
+	 { "MASTER_UPDATE_INTERLACED_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_MVP_INBAND_CNTL_INSERT[] = {
+	 { "CRTC_MVP_INBAND_OUT_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER[] = {
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_MVP_STATUS[] = {
+	 { "CRTC_FLIP_NOW_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FLIP_NOW_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_MASTER_EN[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_ALLOW_STOP_OFF_V_CNT[] = {
+	 { "CRTC_ALLOW_STOP_OFF_V_CNT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_UPDATE_INT_STATUS[] = {
+	 { "CRTC_V_UPDATE_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TEST_DEBUG_INDEX[] = {
+	 { "CRTC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TEST_DEBUG_DATA[] = {
+	 { "CRTC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_OVERSCAN_COLOR[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE", 0, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN", 10, 19, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_OVERSCAN_COLOR_EXT[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_BLANK_DATA_COLOR[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_BLANK_DATA_COLOR_EXT[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_BLACK_COLOR[] = {
+	 { "CRTC_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_BLACK_COLOR_EXT[] = {
+	 { "CRTC_BLACK_COLOR_B_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VERTICAL_INTERRUPT0_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VERTICAL_INTERRUPT0_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VERTICAL_INTERRUPT1_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_LINE_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VERTICAL_INTERRUPT1_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VERTICAL_INTERRUPT2_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_LINE_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_VERTICAL_INTERRUPT2_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC_CNTL[] = {
+	 { "CRTC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "CRTC_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_CRC0_SELECT", 20, 22, &umr_bitfield_default },
+	 { "CRTC_CRC1_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_DATA_RG[] = {
+	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_DATA_B[] = {
+	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_DATA_RG[] = {
+	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_DATA_B[] = {
+	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_STATIC_SCREEN_CONTROL[] = {
+	 { "CRTC_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
+	 { "CRTC_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SS_STATUS", 25, 25, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICA[] = {
+	 { "GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICA_SEL", 7, 11, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_REFDIV_CLK_SEL", 12, 15, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_SEL", 16, 19, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 23, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICB[] = {
+	 { "GENERICB_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICB_SEL", 8, 11, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_REFDIV_CLK_SEL", 12, 15, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_SEL", 16, 19, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 23, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PAD_EXTERN_SIG[] = {
+	 { "DC_PAD_EXTERN_SIG_SEL", 0, 3, &umr_bitfield_default },
+	 { "MVP_PIXEL_SRC_STATUS", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_REF_CLK_CNTL[] = {
+	 { "HSYNCA_OUTPUT_SEL", 0, 1, &umr_bitfield_default },
+	 { "GENLK_CLK_OUTPUT_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DEBUG[] = {
+	 { "DC_GPIO_VIP_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_MACRO_DEBUG", 8, 9, &umr_bitfield_default },
+	 { "DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DEBUG_BUS_FLOP_EN", 17, 17, &umr_bitfield_default },
+	 { "DPRX_LOOPBACK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYA_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYA_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYB_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYB_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYC_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYC_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYD_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYD_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYE_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYE_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYF_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYF_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYG_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYG_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_WRCMD_DELAY[] = {
+	 { "UNIPHY_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DAC_DELAY", 4, 7, &umr_bitfield_default },
+	 { "DPHY_DELAY", 8, 11, &umr_bitfield_default },
+	 { "DCRXPHY_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PINSTRAPS[] = {
+	 { "DC_PINSTRAPS_BIF_CEC_DIS", 10, 10, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_SMS_EN_HARD", 13, 13, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_AUDIO", 14, 15, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_CCBYPASS", 16, 16, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_CONNECTIVITY", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DVODATA_CONFIG[] = {
+	 { "VIP_MUX_EN", 19, 19, &umr_bitfield_default },
+	 { "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default },
+	 { "DVO_ALTER_MAPPING_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_CNTL[] = {
+	 { "LVTMA_PWRSEQ_EN", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_TARGET_STATE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN", 8, 8, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_OVRD", 9, 9, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_POL", 10, 10, &umr_bitfield_default },
+	 { "LVTMA_DIGON", 16, 16, &umr_bitfield_default },
+	 { "LVTMA_DIGON_OVRD", 17, 17, &umr_bitfield_default },
+	 { "LVTMA_DIGON_POL", 18, 18, &umr_bitfield_default },
+	 { "LVTMA_BLON", 24, 24, &umr_bitfield_default },
+	 { "LVTMA_BLON_OVRD", 25, 25, &umr_bitfield_default },
+	 { "LVTMA_BLON_POL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_STATE[] = {
+	 { "LVTMA_PWRSEQ_TARGET_STATE_R", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DIGON", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_SYNCEN", 2, 2, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_BLON", 3, 3, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DONE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_STATE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_REF_DIV[] = {
+	 { "LVTMA_PWRSEQ_REF_DIV", 0, 11, &umr_bitfield_default },
+	 { "BL_PWM_REF_DIV", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY1[] = {
+	 { "LVTMA_PWRUP_DELAY1", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY2", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY1", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY2[] = {
+	 { "LVTMA_PWRDN_MIN_LENGTH", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY3", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY3", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_VARY_BL_OVERRIDE_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL[] = {
+	 { "BL_ACTIVE_INT_FRAC_CNT", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_FRACTIONAL_EN", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL2[] = {
+	 { "BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE", 0, 15, &umr_bitfield_default },
+	 { "DBG_BL_PWM_INPUT_REFCLK_SELECT", 28, 29, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_BL_OUT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_PERIOD_CNTL[] = {
+	 { "BL_PWM_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_PERIOD_BITCNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_GRP1_REG_LOCK[] = {
+	 { "BL_PWM_GRP1_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_GENLK_PAD_CNTL[] = {
+	 { "DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_SWAPLOCK_PAD_CNTL[] = {
+	 { "DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL0_CNTL[] = {
+	 { "DCIO_GSL0_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL0_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL0_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL1_CNTL[] = {
+	 { "DCIO_GSL1_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL1_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL1_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL2_CNTL[] = {
+	 { "DCIO_GSL2_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL2_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL2_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_P_FLIP[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_P_FLIP", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_P_FLIP", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_P_FLIP", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_P_FLIP", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_P_FLIP", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_P_FLIP", 20, 22, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_DCFEV_P_FLIP", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ[] = {
+	 { "DC_GPU_TIMER_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ_CNTL[] = {
+	 { "DC_GPU_TIMER_READ_SELECT", 0, 5, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM", 11, 13, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM", 14, 16, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM", 17, 19, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM", 20, 22, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_CLOCK_CNTL[] = {
+	 { "DCIO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCIO_GATE_DIS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DEBUG[] = {
+	 { "DCIO_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_DCFE_EXT_VSYNC_CNTL[] = {
+	 { "DCO_DCFE0_EXT_VSYNC_MUX", 0, 2, &umr_bitfield_default },
+	 { "DCO_DCFE1_EXT_VSYNC_MUX", 4, 6, &umr_bitfield_default },
+	 { "DCO_DCFE2_EXT_VSYNC_MUX", 8, 10, &umr_bitfield_default },
+	 { "DCO_DCFE3_EXT_VSYNC_MUX", 12, 14, &umr_bitfield_default },
+	 { "DCO_DCFE4_EXT_VSYNC_MUX", 16, 18, &umr_bitfield_default },
+	 { "DCO_DCFE5_EXT_VSYNC_MUX", 20, 22, &umr_bitfield_default },
+	 { "DCO_SWAPLOCKB_EXT_VSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DCO_GENERICB_EXT_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+	 { "DCO_CRTC_MANUAL_FLOW_CONTROL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_INDEX[] = {
+	 { "DCIO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCIO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_DATA[] = {
+	 { "DCIO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDBG_OUT_CNTL[] = {
+	 { "DBG_OUT_PIN_EN", 0, 0, &umr_bitfield_default },
+	 { "DBG_OUT_PIN_SEL", 4, 4, &umr_bitfield_default },
+	 { "DBG_OUT_12BIT_SEL", 8, 9, &umr_bitfield_default },
+	 { "DBG_OUT_TEST_DATA", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DEBUG_CONFIG[] = {
+	 { "DCIO_DBG_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SOFT_RESET[] = {
+	 { "UNIPHYA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DSYNCA_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHYB_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "DSYNCB_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "UNIPHYC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DSYNCC_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "UNIPHYD_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DSYNCD_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "UNIPHYE_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DSYNCE_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "UNIPHYF_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "DSYNCF_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "UNIPHYG_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DSYNCG_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DACA_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "DCRXPHY_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "DPHY_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "UNIPHYLPA_SOFT_RESET", 28, 28, &umr_bitfield_default },
+	 { "DSYNCLPA_SOFT_RESET", 29, 29, &umr_bitfield_default },
+	 { "UNIPHYLPB_SOFT_RESET", 30, 30, &umr_bitfield_default },
+	 { "DSYNCLPB_SOFT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DPHY_SEL[] = {
+	 { "DPHY_LANE0_SEL", 0, 1, &umr_bitfield_default },
+	 { "DPHY_LANE1_SEL", 2, 3, &umr_bitfield_default },
+	 { "DPHY_LANE2_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_LANE3_SEL", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKA[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKA", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKA", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKA", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKA", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKA", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKA", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKB[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKB", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKB", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKB", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKB", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKB", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PERIOD[] = {
+	 { "UNIPHY_IMPCAL_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXP_IMPCAL[] = {
+	 { "AUXP_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXN_IMPCAL[] = {
+	 { "AUXN_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+	 { "AUX_IMPCAL_INTERVAL", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_AB[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKA", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKB", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKC[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKC", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKC", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKC", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKC", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKC", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKC", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKD[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKD", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKD", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKD", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKD", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKD", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKD", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_CD[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_CD[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKC", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKD", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKE[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKE", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKE", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKE", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKE", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKE", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKF[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKF", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKF", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKF", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKF", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKF", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKF", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_EF[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_EF[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKE", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKF", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYLPA_LINK_CNTL[] = {
+	 { "UNIPHYLP_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHYLP_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHYLP_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHYLP_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYLPB_LINK_CNTL[] = {
+	 { "UNIPHYLP_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHYLP_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHYLP_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHYLP_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYLPA_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHYLP_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHYLP_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYLPB_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHYLP_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHYLP_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_MASK[] = {
+	 { "DC_GPIO_GENERICA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_PD_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_MASK", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_PD_DIS", 13, 13, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_RECV", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_A[] = {
+	 { "DC_GPIO_GENERICA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_A", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_A", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_A", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_A", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_EN[] = {
+	 { "DC_GPIO_GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_Y[] = {
+	 { "DC_GPIO_GENERICA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_Y", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_Y", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_Y", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_Y", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_MASK[] = {
+	 { "DC_GPIO_DVODATA_MASK", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_MASK", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_MASK", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_MASK", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_A[] = {
+	 { "DC_GPIO_DVODATA_A", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_A", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_A", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_A", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_EN[] = {
+	 { "DC_GPIO_DVODATA_EN", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_EN", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_EN", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_EN", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_Y[] = {
+	 { "DC_GPIO_DVODATA_Y", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_Y", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_Y", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_Y", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_MASK[] = {
+	 { "DC_GPIO_DDC1CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD1_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX1_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC1_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_A[] = {
+	 { "DC_GPIO_DDC1CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_EN[] = {
+	 { "DC_GPIO_DDC1CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_Y[] = {
+	 { "DC_GPIO_DDC1CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_MASK[] = {
+	 { "DC_GPIO_DDC2CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD2_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX2_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC2_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_A[] = {
+	 { "DC_GPIO_DDC2CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_EN[] = {
+	 { "DC_GPIO_DDC2CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_Y[] = {
+	 { "DC_GPIO_DDC2CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_MASK[] = {
+	 { "DC_GPIO_DDC3CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD3_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX3_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC3_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_A[] = {
+	 { "DC_GPIO_DDC3CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_EN[] = {
+	 { "DC_GPIO_DDC3CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_Y[] = {
+	 { "DC_GPIO_DDC3CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_MASK[] = {
+	 { "DC_GPIO_DDC4CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD4_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX4_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC4_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_A[] = {
+	 { "DC_GPIO_DDC4CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_EN[] = {
+	 { "DC_GPIO_DDC4CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_Y[] = {
+	 { "DC_GPIO_DDC4CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_MASK[] = {
+	 { "DC_GPIO_DDC5CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD5_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX5_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC5_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_A[] = {
+	 { "DC_GPIO_DDC5CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_EN[] = {
+	 { "DC_GPIO_DDC5CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_Y[] = {
+	 { "DC_GPIO_DDC5CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_MASK[] = {
+	 { "DC_GPIO_DDC6CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD6_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX6_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC6_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_A[] = {
+	 { "DC_GPIO_DDC6CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_EN[] = {
+	 { "DC_GPIO_DDC6CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_Y[] = {
+	 { "DC_GPIO_DDC6CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_MASK[] = {
+	 { "DC_GPIO_DDCVGACLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PADVGA_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUXVGA_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDCVGA_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_A[] = {
+	 { "DC_GPIO_DDCVGACLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_EN[] = {
+	 { "DC_GPIO_DDCVGACLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_Y[] = {
+	 { "DC_GPIO_DDCVGACLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_MASK[] = {
+	 { "DC_GPIO_HSYNCA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_CRTC_HSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_CRTC_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_A[] = {
+	 { "DC_GPIO_HSYNCA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_EN[] = {
+	 { "DC_GPIO_HSYNCA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_Y[] = {
+	 { "DC_GPIO_HSYNCA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_MASK[] = {
+	 { "DC_GPIO_GENLK_CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PU_EN", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PU_EN", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PU_EN", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PU_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_A[] = {
+	 { "DC_GPIO_GENLK_CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_A", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_EN[] = {
+	 { "DC_GPIO_GENLK_CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_Y[] = {
+	 { "DC_GPIO_GENLK_CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_Y", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_MASK[] = {
+	 { "DC_GPIO_HPD1_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_MASK", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_PD_DIS", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_RX_SEL", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_RECV", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_A[] = {
+	 { "DC_GPIO_HPD1_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_A", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_A", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_EN[] = {
+	 { "DC_GPIO_HPD1_EN", 0, 0, &umr_bitfield_default },
+	 { "HPD1_SCHMEN_PI", 1, 1, &umr_bitfield_default },
+	 { "HPD1_SLEWNCORE", 2, 2, &umr_bitfield_default },
+	 { "RX_HPD_SCHMEN_PI", 3, 3, &umr_bitfield_default },
+	 { "RX_HPD_SLEWNCORE", 4, 4, &umr_bitfield_default },
+	 { "HPD12_SPARE0", 5, 5, &umr_bitfield_default },
+	 { "HPD1_SEL0", 6, 6, &umr_bitfield_default },
+	 { "RX_HPD_SEL0", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_EN", 8, 8, &umr_bitfield_default },
+	 { "HPD2_SCHMEN_PI", 9, 9, &umr_bitfield_default },
+	 { "HPD12_SPARE1", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_EN", 16, 16, &umr_bitfield_default },
+	 { "HPD3_SCHMEN_PI", 17, 17, &umr_bitfield_default },
+	 { "HPD34_SPARE0", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_EN", 20, 20, &umr_bitfield_default },
+	 { "HPD4_SCHMEN_PI", 21, 21, &umr_bitfield_default },
+	 { "HPD34_SPARE1", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_EN", 24, 24, &umr_bitfield_default },
+	 { "HPD5_SCHMEN_PI", 25, 25, &umr_bitfield_default },
+	 { "HPD56_SPARE0", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_EN", 28, 28, &umr_bitfield_default },
+	 { "HPD6_SCHMEN_PI", 29, 29, &umr_bitfield_default },
+	 { "HPD56_SPARE1", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_Y[] = {
+	 { "DC_GPIO_HPD1_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_Y", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_Y", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_Y", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_MASK[] = {
+	 { "DC_GPIO_BLON_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_PD_DIS", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_RECV", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_A[] = {
+	 { "DC_GPIO_BLON_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_A", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_EN[] = {
+	 { "DC_GPIO_BLON_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VARY_BL_GENERICA_EN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_Y[] = {
+	 { "DC_GPIO_BLON_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_1[] = {
+	 { "GENLK_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GENLK_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "RX_HPD_STRENGTH_SN", 8, 11, &umr_bitfield_default },
+	 { "RX_HPD_STRENGTH_SP", 12, 15, &umr_bitfield_default },
+	 { "TX_HPD_STRENGTH_SN", 16, 19, &umr_bitfield_default },
+	 { "TX_HPD_STRENGTH_SP", 20, 23, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SN", 24, 27, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SP", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_2[] = {
+	 { "STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "EXT_RESET_DRVSTRENGTH", 8, 10, &umr_bitfield_default },
+	 { "REF_27_DRVSTRENGTH", 12, 14, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SN", 16, 19, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SP", 20, 23, &umr_bitfield_default },
+	 { "REF_27_SRC_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHY_AUX_CNTL[] = {
+	 { "AUXSLAVE_PAD_SLEWN", 0, 0, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_WAKE", 1, 1, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_RXSEL", 2, 2, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_MODE", 3, 3, &umr_bitfield_default },
+	 { "DDCSLAVE_DATA_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DDCSLAVE_DATA_EN", 5, 5, &umr_bitfield_default },
+	 { "DDCSLAVE_CLK_PD_EN", 6, 6, &umr_bitfield_default },
+	 { "DDCSLAVE_CLK_EN", 7, 7, &umr_bitfield_default },
+	 { "AUX_PAD_SLEWN", 12, 12, &umr_bitfield_default },
+	 { "AUXSLAVE_CLK_PD_EN", 13, 13, &umr_bitfield_default },
+	 { "AUX_PAD_WAKE", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD_RXSEL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_MASK[] = {
+	 { "DC_GPIO_SCL_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SCL_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_SCL_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_PD_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_RECV", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_A[] = {
+	 { "DC_GPIO_SCL_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_A", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_EN[] = {
+	 { "DC_GPIO_SCL_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_Y[] = {
+	 { "DC_GPIO_SCL_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_Y", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_STRENGTH[] = {
+	 { "I2C_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "I2C_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_VREF_CONTROL[] = {
+	 { "DVO_VREFPON", 0, 0, &umr_bitfield_default },
+	 { "DVO_VREFSEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_VREFCAL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SKEW_ADJUST[] = {
+	 { "DVO_SKEW_ADJUST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED0[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED1[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_MACRO_CNTL[] = {
+	 { "BPHYC_DAC_WHITE_LEVEL", 0, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_WHITE_FINE_CONTROL", 8, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_BANDGAP_ADJUSTMENT", 16, 21, &umr_bitfield_default },
+	 { "BPHYC_DAC_ANALOG_MONITOR", 24, 27, &umr_bitfield_default },
+	 { "BPHYC_DAC_COREMON", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_AUTO_CALIB_CONTROL[] = {
+	 { "BPHYC_DAC_CAL_INITB", 0, 0, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_EN", 1, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_DACADJ_EN", 2, 2, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_WAIT_ADJUST", 4, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_MASK", 20, 22, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_COMPLETE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED2[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED3[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED0[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL1[] = {
+	 { "UNIPHY_PREMPH_STR0", 0, 2, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR1", 4, 6, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR2", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR3", 12, 14, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR4", 16, 18, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS0", 20, 21, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS1", 22, 23, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS2", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS3", 26, 27, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS4", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED1[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL2[] = {
+	 { "UNIPHY_PREMPH0_PC", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH1_PC", 4, 5, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH2_PC", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH3_PC", 12, 13, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH4_PC", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_SEL", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_RT0_CPSEL", 21, 22, &umr_bitfield_default },
+	 { "UNIPHY_RT1_CPSEL", 23, 24, &umr_bitfield_default },
+	 { "UNIPHY_RT2_CPSEL", 25, 26, &umr_bitfield_default },
+	 { "UNIPHY_RT3_CPSEL", 27, 28, &umr_bitfield_default },
+	 { "UNIPHY_RT4_CPSEL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED2[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL3[] = {
+	 { "UNIPHY_PREMPH_PW_CLK", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_PW_DAT", 2, 3, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_CS_CLK", 4, 7, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_CS_DAT", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR_CLK", 12, 15, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR_DAT", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_PESEL0", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_PESEL1", 21, 21, &umr_bitfield_default },
+	 { "UNIPHY_PESEL2", 22, 22, &umr_bitfield_default },
+	 { "UNIPHY_PESEL3", 23, 23, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS_ADJ", 24, 28, &umr_bitfield_default },
+	 { "UNIPHY_LVDS_PULLDWN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED3[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL4[] = {
+	 { "UNIPHY_TX_NVS_CLK", 0, 4, &umr_bitfield_default },
+	 { "UNIPHY_TX_NVS_DAT", 5, 9, &umr_bitfield_default },
+	 { "UNIPHY_TX_PVS_CLK", 12, 16, &umr_bitfield_default },
+	 { "UNIPHY_TX_PVS_DAT", 17, 21, &umr_bitfield_default },
+	 { "UNIPHY_TX_OP_CLK", 24, 26, &umr_bitfield_default },
+	 { "UNIPHY_TX_OP_DAT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED4[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_POWER_CONTROL[] = {
+	 { "UNIPHY_BGPDN", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_RST_LOGIC", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_BIASREF_SEL", 2, 3, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ1P00", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ1P25", 12, 15, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ0P45", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED5[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_FBDIV[] = {
+	 { "UNIPHY_PLL_FBDIV_FRACTION", 2, 15, &umr_bitfield_default },
+	 { "UNIPHY_PLL_FBDIV", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED6[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_CONTROL1[] = {
+	 { "UNIPHY_PLL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PLL_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_PLL_EXT_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "UNIPHY_PLL_CLK_EN", 3, 3, &umr_bitfield_default },
+	 { "UNIPHY_PLL_CLKPH_EN", 4, 7, &umr_bitfield_default },
+	 { "UNIPHY_PLL_LF_CNTL", 8, 14, &umr_bitfield_default },
+	 { "UNIPHY_PLL_BW_CNTL", 16, 23, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_BYPCLK_SRC", 24, 24, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_BYPCLK_EN", 25, 25, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL_ADC_EN", 26, 26, &umr_bitfield_default },
+	 { "UNIPHY_VCO_MODE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED7[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_CONTROL2[] = {
+	 { "UNIPHY_PLL_DISPCLK_MODE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_DPLLSEL", 2, 3, &umr_bitfield_default },
+	 { "UNIPHY_IDCLK_SEL", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_IPCIE_REFCLK_SEL", 5, 5, &umr_bitfield_default },
+	 { "UNIPHY_IXTALIN_SEL", 6, 6, &umr_bitfield_default },
+	 { "UNIPHY_PLL_REFCLK_SRC", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_PCIEREF_CLK_EN", 11, 11, &umr_bitfield_default },
+	 { "UNIPHY_IDCLK_EN", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CLKINV", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_PLL_VTOI_BIAS_CNTL", 16, 16, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS", 19, 19, &umr_bitfield_default },
+	 { "UNIPHY_PDIVFRAC_SEL", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_PLL_REFDIV", 24, 28, &umr_bitfield_default },
+	 { "UNIPHY_PDIV_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED8[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_SS_STEP_SIZE[] = {
+	 { "UNIPHY_PLL_SS_STEP_SIZE", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED9[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_SS_CNTL[] = {
+	 { "UNIPHY_PLL_SS_STEP_NUM", 0, 11, &umr_bitfield_default },
+	 { "UNIPHY_PLL_DSMOD_EN", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_PLL_SS_EN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED10[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_DATA_SYNCHRONIZATION[] = {
+	 { "UNIPHY_DSYNSEL", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_DSYN_LEVEL", 4, 5, &umr_bitfield_default },
+	 { "UNIPHY_DSYN_ERROR", 6, 6, &umr_bitfield_default },
+	 { "UNIPHY_SOURCE_SELECT", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_DUAL_LINK_PHASE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED11[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_REG_TEST_OUTPUT[] = {
+	 { "UNIPHY_TEST_CNTL", 0, 4, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL", 5, 8, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_SSAMP_EN", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_UNLOCK_CLR", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_RESET", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_SEL", 16, 16, &umr_bitfield_default },
+	 { "UNIPHY_TEST_VCTL_EN", 17, 17, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_ERROR", 20, 24, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL_ADC", 25, 27, &umr_bitfield_default },
+	 { "OA_PLL_TEST_UNLOCK_RAW", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_PLL_INTRESET", 29, 29, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_UNLOCK_STICKY", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED12[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_ANG_BIST_CNTL[] = {
+	 { "UNIPHY_TEST_RX_EN", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_ANG_BIST_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_RX_BIAS", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_ANG_BIST_ERROR", 16, 20, &umr_bitfield_default },
+	 { "UNIPHY_PRESETB", 24, 24, &umr_bitfield_default },
+	 { "UNIPHY_BIST_EN", 25, 25, &umr_bitfield_default },
+	 { "UNIPHY_CLK_CH_EN4_DFT", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED13[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_REG_TEST_OUTPUT2[] = {
+	 { "UNIPHY_TX", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED14[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG0[] = {
+	 { "ITXA_IMPCAL_EN", 0, 0, &umr_bitfield_default },
+	 { "ICALRA_MODE", 1, 1, &umr_bitfield_default },
+	 { "ITXA_OVERRIDE_PG", 2, 10, &umr_bitfield_default },
+	 { "ITXA_OVERRIDE_NG", 11, 19, &umr_bitfield_default },
+	 { "ITXA_TPC_SEL", 20, 20, &umr_bitfield_default },
+	 { "ITXA_PCALEN", 21, 21, &umr_bitfield_default },
+	 { "ITXA_DPPC_PWN", 22, 22, &umr_bitfield_default },
+	 { "ITXA_OVERRIDE_EN", 23, 23, &umr_bitfield_default },
+	 { "ITXA_TPC_CNTL", 24, 25, &umr_bitfield_default },
+	 { "ITXA_VSCALEN", 26, 26, &umr_bitfield_default },
+	 { "ITXA_IOCNTL_TSTSEL", 27, 30, &umr_bitfield_default },
+	 { "ITXA_IMPVSCALEN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED15[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG1[] = {
+	 { "ITXA_BIAS_ICC_TST", 0, 4, &umr_bitfield_default },
+	 { "ITXA_BIAS_IPLL100_ADJ", 5, 8, &umr_bitfield_default },
+	 { "ITXA_BIAS_IPLL50_ADJ", 9, 12, &umr_bitfield_default },
+	 { "ITXA_BIAS_ICC_ADJ", 13, 16, &umr_bitfield_default },
+	 { "ITXA_BIAS_ICC_PDN", 17, 17, &umr_bitfield_default },
+	 { "ITXA_IOCNTL", 18, 27, &umr_bitfield_default },
+	 { "ITXA_BIAS_PLLREFSEL", 28, 28, &umr_bitfield_default },
+	 { "ITX_EDPSEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED16[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG2[] = {
+	 { "ITXA_IMPCALN_PDN", 0, 0, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_OFFSET_EN", 1, 1, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_OFFSET", 2, 5, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_OVERRIDE", 7, 13, &umr_bitfield_default },
+	 { "ITXA_IMPCALN_SET", 14, 14, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_PDN", 16, 16, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_OFFSET_EN", 17, 17, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_OFFSET", 18, 21, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_OVERRIDE_EN", 22, 22, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_OVERRIDE", 23, 29, &umr_bitfield_default },
+	 { "ITXA_IMPCALP_SET", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED17[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG3[] = {
+	 { "ITXA_IMPCALVS_PDN", 0, 0, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_OFFSET_EN", 1, 1, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_OFFSET", 2, 5, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_OVERRIDE_EN", 6, 6, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_OVERRIDE", 7, 13, &umr_bitfield_default },
+	 { "ITXA_IMPCALVS_SET", 14, 14, &umr_bitfield_default },
+	 { "ITXA_PREM_ADJ", 15, 19, &umr_bitfield_default },
+	 { "OTXA_RES_NCAL", 20, 24, &umr_bitfield_default },
+	 { "OTXA_RES_PCAL", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED18[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG4[] = {
+	 { "RESERVED", 0, 21, &umr_bitfield_default },
+	 { "OTXA_IOCNTL_NF", 22, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED19[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG5[] = {
+	 { "OTXA0_IOFSM_TIMEOUT", 0, 0, &umr_bitfield_default },
+	 { "OTXA0_RESCAL_DONE", 1, 1, &umr_bitfield_default },
+	 { "OTXA1_IOFSM_TIMEOUT", 2, 2, &umr_bitfield_default },
+	 { "OTXA1_RESCAL_DONE", 3, 3, &umr_bitfield_default },
+	 { "OTXA2_IOFSM_TIMEOUT", 4, 4, &umr_bitfield_default },
+	 { "OTXA2_RESCAL_DONE", 5, 5, &umr_bitfield_default },
+	 { "OTXA3_IOFSM_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "OTXA3_RESCAL_DONE", 7, 7, &umr_bitfield_default },
+	 { "OTXA_IMPCALN", 8, 16, &umr_bitfield_default },
+	 { "OTXA_IMPCALN_DONE", 17, 17, &umr_bitfield_default },
+	 { "OTXA_IMPCALN_ERROR", 18, 18, &umr_bitfield_default },
+	 { "OTXA_IMPCALP", 19, 22, &umr_bitfield_default },
+	 { "OTXA_IMPCALP_DONE", 23, 23, &umr_bitfield_default },
+	 { "OTXA_IMPCALP_ERROR", 24, 24, &umr_bitfield_default },
+	 { "OTXA_IMPCALVS", 25, 29, &umr_bitfield_default },
+	 { "OTXA_IMPCALVS_DONE", 30, 30, &umr_bitfield_default },
+	 { "OTXA_IMPCALVS_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED20[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TMDP_REG6[] = {
+	 { "IRXA_OS_ADJ", 0, 0, &umr_bitfield_default },
+	 { "IRXA_OS_POLB", 1, 1, &umr_bitfield_default },
+	 { "IRXA_BIST_SEL", 2, 2, &umr_bitfield_default },
+	 { "IRXA_SENADJ", 3, 6, &umr_bitfield_default },
+	 { "IRXA_CPSEL", 7, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKA", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED21[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TPG_CONTROL[] = {
+	 { "UNIPHY_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHY_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHY_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED22[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TPG_SEED[] = {
+	 { "UNIPHY_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED23[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_DEBUG[] = {
+	 { "DEBUG0", 12, 21, &umr_bitfield_default },
+	 { "DEBUG1", 22, 24, &umr_bitfield_default },
+	 { "DBG_SEL", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED24[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED25[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED26[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED27[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED28[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED29[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED30[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED31[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_CNTL[] = {
+	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
+	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
+	 { "DIG_START", 10, 10, &umr_bitfield_default },
+	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
+	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
+	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_OUTPUT_CRC_CNTL[] = {
+	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
+	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_OUTPUT_CRC_RESULT[] = {
+	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_CLOCK_PATTERN[] = {
+	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_PATTERN[] = {
+	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
+	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
+	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
+	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_RANDOM_PATTERN_SEED[] = {
+	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
+	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FIFO_STATUS[] = {
+	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
+	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
+	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_DISPCLK_SWITCH_CNTL[] = {
+	 { "DIG_DISPCLK_SWITCH_POINT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_DISPCLK_SWITCH_STATUS[] = {
+	 { "DIG_DISPCLK_SWITCH_ALLOWED", 0, 0, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT", 4, 4, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_CONTROL[] = {
+	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
+	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
+	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
+	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
+	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
+	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_STATUS[] = {
+	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
+	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
+	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_AUDIO_PACKET_CONTROL[] = {
+	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
+	 { "HDMI_AUDIO_SEND_MAX_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_PACKET_CONTROL[] = {
+	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
+	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
+	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
+	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_VBI_PACKET_CONTROL[] = {
+	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
+	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_INFOFRAME_CONTROL0[] = {
+	 { "HDMI_AVI_INFO_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_AVI_INFO_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_INFOFRAME_CONTROL1[] = {
+	 { "HDMI_AVI_INFO_LINE", 0, 5, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GENERIC_PACKET_CONTROL0[] = {
+	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GC[] = {
+	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
+	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
+	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
+	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL2[] = {
+	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
+	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
+	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_0[] = {
+	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
+	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_1[] = {
+	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_2[] = {
+	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_3[] = {
+	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_4[] = {
+	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_0[] = {
+	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_1[] = {
+	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_2[] = {
+	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_3[] = {
+	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO0[] = {
+	 { "AFMT_AVI_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_S", 8, 9, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_B", 10, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_A", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Y", 13, 14, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PB1_RSVD", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_R", 16, 19, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_M", 20, 21, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_C", 22, 23, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_SC", 24, 25, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Q", 26, 27, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_EC", 28, 30, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_ITC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO1[] = {
+	 { "AFMT_AVI_INFO_VIC", 0, 6, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PB4_RSVD", 7, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PR", 8, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_CN", 12, 13, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_YQ", 14, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO2[] = {
+	 { "AFMT_AVI_INFO_BOTTOM", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_LEFT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO3[] = {
+	 { "AFMT_AVI_INFO_RIGHT", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_VERSION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO0[] = {
+	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO1[] = {
+	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_HDR[] = {
+	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_0[] = {
+	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_1[] = {
+	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_2[] = {
+	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_3[] = {
+	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_4[] = {
+	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_5[] = {
+	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_6[] = {
+	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_7[] = {
+	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GENERIC_PACKET_CONTROL1[] = {
+	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_32_0[] = {
+	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_32_1[] = {
+	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_44_0[] = {
+	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_44_1[] = {
+	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_48_0[] = {
+	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_48_1[] = {
+	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_STATUS_0[] = {
+	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_STATUS_1[] = {
+	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO0[] = {
+	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO1[] = {
+	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_0[] = {
+	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
+	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
+	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
+	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
+	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_1[] = {
+	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_CONTROL[] = {
+	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL0[] = {
+	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
+	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL1[] = {
+	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL2[] = {
+	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL3[] = {
+	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_2[] = {
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_RESULT[] = {
+	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_STATUS[] = {
+	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL[] = {
+	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
+	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
+	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
+	 { "AFMT_BLANK_TEST_DATA_ON_ENC_ENB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_VBI_PACKET_CONTROL[] = {
+	 { "AFMT_GENERIC0_UPDATE", 2, 2, &umr_bitfield_default },
+	 { "AFMT_GENERIC2_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "AFMT_GENERIC_INDEX", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_INFOFRAME_CONTROL0[] = {
+	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_SRC_CONTROL[] = {
+	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_DBG_DTO_CNTL[] = {
+	 { "AFMT_AUDIO_DTO_FS_DIV_SEL", 0, 2, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_BASE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_MULTI", 12, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_DIV", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_BE_CNTL[] = {
+	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
+	 { "DIG_RB_SWITCH_EN", 2, 2, &umr_bitfield_default },
+	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
+	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
+	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_BE_EN_CNTL[] = {
+	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CNTL[] = {
+	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CONTROL_CHAR[] = {
+	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CONTROL0_FEEDBACK[] = {
+	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
+	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_STEREOSYNC_CTL_SEL[] = {
+	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_SYNC_CHAR_PATTERN_0_1[] = {
+	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
+	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_SYNC_CHAR_PATTERN_2_3[] = {
+	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
+	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_DEBUG[] = {
+	 { "TMDS_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_DEBUG_HSYNC", 8, 8, &umr_bitfield_default },
+	 { "TMDS_DEBUG_HSYNC_EN", 9, 9, &umr_bitfield_default },
+	 { "TMDS_DEBUG_VSYNC", 16, 16, &umr_bitfield_default },
+	 { "TMDS_DEBUG_VSYNC_EN", 17, 17, &umr_bitfield_default },
+	 { "TMDS_DEBUG_DE", 24, 24, &umr_bitfield_default },
+	 { "TMDS_DEBUG_DE_EN", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL_BITS[] = {
+	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
+	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
+	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
+	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_DCBALANCER_CONTROL[] = {
+	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_SYNC_DCBAL_EN", 4, 6, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL0_1_GEN_CNTL[] = {
+	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
+	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
+	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
+	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
+	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
+	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
+	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
+	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL2_3_GEN_CNTL[] = {
+	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
+	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
+	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
+	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
+	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
+	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
+	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_VERSION[] = {
+	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_LANE_ENABLE[] = {
+	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
+	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
+	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
+	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_DEBUG_INDEX[] = {
+	 { "DIG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DIG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_DEBUG_DATA[] = {
+	 { "DIG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_TEST_DEBUG_INDEX[] = {
+	 { "DIG_FE_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DIG_FE_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_TEST_DEBUG_DATA[] = {
+	 { "DIG_FE_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_CNTL[] = {
+	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_LINK_CNTL[] = {
+	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
+	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_PIXEL_FORMAT[] = {
+	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
+	 { "DP_DYN_RANGE", 8, 8, &umr_bitfield_default },
+	 { "DP_YCBCR_RANGE", 16, 16, &umr_bitfield_default },
+	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_COLORIMETRY[] = {
+	 { "DP_MSA_MISC0_OVERRIDE", 0, 7, &umr_bitfield_default },
+	 { "DP_MSA_MISC0_OVERRIDE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_CONFIG[] = {
+	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_STREAM_CNTL[] = {
+	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
+	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
+	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_STEER_FIFO[] = {
+	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
+	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
+	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_MISC[] = {
+	 { "DP_MSA_MISC1", 3, 6, &umr_bitfield_default },
+	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
+	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
+	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_TIMING[] = {
+	 { "DP_VID_TIMING_MODE", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
+	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
+	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_N[] = {
+	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_M[] = {
+	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_LINK_FRAMING_CNTL[] = {
+	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
+	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_HBR2_EYE_PATTERN[] = {
+	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_MSA_VBID[] = {
+	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
+	 { "DP_VID_MSA_TOP_FIELD_MODE", 16, 16, &umr_bitfield_default },
+	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_INTERRUPT_CNTL[] = {
+	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CNTL[] = {
+	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
+	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_TRAINING_PATTERN_SEL[] = {
+	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM0[] = {
+	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
+	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM1[] = {
+	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
+	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM2[] = {
+	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_8B10B_CNTL[] = {
+	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
+	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
+	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_PRBS_CNTL[] = {
+	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SCRAM_CNTL[] = {
+	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
+	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_EN[] = {
+	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_CNTL[] = {
+	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_RESULT[] = {
+	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_MST_CNTL[] = {
+	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_MST_STATUS[] = {
+	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_FAST_TRAINING[] = {
+	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_FAST_TRAINING_STATUS[] = {
+	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_V_TIMING_OVERRIDE1[] = {
+	 { "DP_MSA_V_TIMING_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "DP_MSA_V_TOTAL_OVERRIDE", 4, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_V_TIMING_OVERRIDE2[] = {
+	 { "DP_MSA_V_BLANK_START_OVERRIDE", 0, 13, &umr_bitfield_default },
+	 { "DP_MSA_V_BLANK_END_OVERRIDE", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_CNTL[] = {
+	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "DP_SEC_AVI_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_CNTL1[] = {
+	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING1[] = {
+	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
+	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING2[] = {
+	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
+	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING3[] = {
+	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
+	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING4[] = {
+	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
+	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
+	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_N[] = {
+	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_N_READBACK[] = {
+	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_M[] = {
+	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_M_READBACK[] = {
+	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_TIMESTAMP[] = {
+	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_PACKET_CNTL[] = {
+	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
+	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
+	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_RATE_CNTL[] = {
+	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
+	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_RATE_UPDATE[] = {
+	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT0[] = {
+	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT1[] = {
+	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT2[] = {
+	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT_UPDATE[] = {
+	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
+	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_LINK_TIMING[] = {
+	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
+	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_MISC_CNTL[] = {
+	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
+	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
+	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
+	 { "DP_MSE_OUTPUT_DPDBG_DATA", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_TEST_DEBUG_INDEX[] = {
+	 { "DP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_TEST_DEBUG_DATA[] = {
+	 { "DP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_FE_TEST_DEBUG_INDEX[] = {
+	 { "DP_FE_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DP_FE_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_FE_TEST_DEBUG_DATA[] = {
+	 { "DP_FE_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_BS_SR_SWAP_CNTL[] = {
+	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
+	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
+	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_HBR2_PATTERN_CONTROL[] = {
+	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL5[] = {
+	 { "INPUT_CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL5[] = {
+	 { "CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_STREAM_DEBUG[] = {
+	 { "STREAM_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR4[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG5[] = {
+	 { "DCIO_DEBUG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR05[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT05[] = {
+	 { "H_SYNC_END", 0, 4, &umr_bitfield_default },
+	 { "H_SYNC_SKEW", 5, 6, &umr_bitfield_default },
+	 { "H_BLANK_END_B5", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
+	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
+	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
+	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
+	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
+	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
+	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED0[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED1[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED2[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED3[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED4[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED5[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED6[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED7[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED8[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED9[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED10[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED11[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED12[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED13[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED14[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED15[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED16[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED17[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED18[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED19[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED20[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED21[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED22[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED23[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED24[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED25[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED26[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED27[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED28[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED29[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED30[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED31[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED32[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED33[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED34[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED35[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED36[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED37[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED38[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED39[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED40[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED41[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED42[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED43[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED44[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED45[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED46[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED47[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED48[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED49[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED50[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED51[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED52[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED53[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED54[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED55[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED56[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED57[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED58[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED59[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED60[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED61[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED62[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED63[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED64[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED65[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED66[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED67[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED68[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED69[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED70[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED71[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED72[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED73[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED74[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED75[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED76[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED77[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED78[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED79[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED80[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED81[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED82[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED83[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED84[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED85[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED86[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED87[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED88[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED89[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED90[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED91[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED92[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED93[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED94[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED95[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED96[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED97[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED98[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED99[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED100[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED101[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED102[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED103[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED104[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED105[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED106[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED107[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED108[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED109[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED110[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED111[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED112[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED113[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED114[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED115[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED116[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED117[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED118[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED119[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED120[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED121[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED122[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED123[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED124[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED125[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED126[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED127[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED128[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED129[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED130[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED131[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED132[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED133[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED134[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED135[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED136[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED137[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED138[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED139[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED140[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED141[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED142[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED143[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED144[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED145[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED146[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED147[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED148[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED149[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED150[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED151[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED152[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED153[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED154[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED155[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED156[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED157[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED158[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED159[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED160[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED161[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED162[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED163[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED164[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED165[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED166[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED167[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED168[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED169[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED170[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED171[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED172[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED173[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED174[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED175[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED176[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED177[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED178[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED179[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED180[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED181[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED182[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED183[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED184[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED185[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED186[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED187[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED188[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED189[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED190[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED191[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED192[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED193[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED194[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED195[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED196[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED197[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED198[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED199[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED200[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED201[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED202[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED203[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED204[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED205[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED206[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED207[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED208[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED209[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED210[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED211[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED212[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED213[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED214[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED215[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED216[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED217[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED218[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED219[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED220[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED221[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED222[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED223[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED224[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED225[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED226[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED227[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED228[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED229[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED230[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED231[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED232[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED233[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED234[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED235[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED236[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED237[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED238[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED239[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED240[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED241[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED242[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED243[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED244[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED245[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED246[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED247[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED248[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED249[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED250[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED251[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED252[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED253[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED254[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED255[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED256[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED257[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED258[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED259[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED260[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED261[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED262[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED263[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED264[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED265[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED266[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED267[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED268[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED269[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED270[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED271[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED272[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED273[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED274[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED275[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED276[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED277[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED278[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED279[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED280[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED281[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED282[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED283[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED284[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED285[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED286[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED287[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED288[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED289[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED290[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED291[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED292[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED293[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED294[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED295[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED296[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED297[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED298[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED299[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED300[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED301[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED302[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED303[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED304[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED305[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED306[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED307[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED308[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED309[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED310[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED311[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED312[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED313[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED314[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED315[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED316[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED317[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED318[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED319[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED320[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED321[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED322[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED323[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED324[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED325[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED326[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED327[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED328[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED329[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED330[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED331[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED332[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED333[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED334[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED335[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED336[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED337[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED338[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED339[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED340[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED341[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED342[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED343[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED344[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED345[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED346[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED347[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED348[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED349[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED350[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED351[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED352[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED353[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED354[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED355[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED356[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED357[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED358[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED359[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED360[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED361[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED362[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED363[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED364[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED365[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED366[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED367[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED368[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED369[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED370[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED371[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED372[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED373[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED374[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED375[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED376[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED377[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED378[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED379[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_CONTROL[] = {
+	 { "AUX_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
+	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
+	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
+	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
+	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
+	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
+	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
+	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
+	 { "SPARE_0", 30, 30, &umr_bitfield_default },
+	 { "SPARE_1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_CONTROL[] = {
+	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
+	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
+	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_ARB_CONTROL[] = {
+	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
+	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_INTERRUPT_CONTROL[] = {
+	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_STATUS[] = {
+	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_STATUS[] = {
+	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_DATA[] = {
+	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
+	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_DATA[] = {
+	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_REF_CONTROL[] = {
+	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
+	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_CONTROL[] = {
+	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
+	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
+	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL0[] = {
+	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
+	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
+	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
+	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
+	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
+	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL1[] = {
+	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_STATUS[] = {
+	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_STATUS[] = {
+	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
+	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_CONTROL[] = {
+	 { "AUX_GTC_SYNC_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_IMPCAL_EN", 4, 4, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_IMPCAL_INTERVAL", 8, 11, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_PERIOD", 12, 15, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_MAINT_PERIOD", 16, 18, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_BLOCK_REQ", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_INTERVAL_RESET_WINDOW", 22, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT", 24, 25, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_ERROR_CONTROL[] = {
+	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
+	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_CONTROLLER_STATUS[] = {
+	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_STATUS[] = {
+	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
+	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_DATA[] = {
+	 { "AUX_GTC_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_GTC_INDEX", 16, 21, &umr_bitfield_default },
+	 { "AUX_GTC_INDEX_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[] = {
+	 { "AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE", 4, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_TEST_DEBUG_INDEX[] = {
+	 { "AUX_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AUX_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_TEST_DEBUG_DATA[] = {
+	 { "AUX_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED0[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED1[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED2[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED3[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED4[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED5[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED6[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED7[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED8[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED9[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED10[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED11[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED12[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED13[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED14[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED15[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED16[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED17[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED18[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED19[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED20[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED21[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED22[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED23[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED24[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED25[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED26[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED27[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED28[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED29[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED30[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED31[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED32[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED33[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED34[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED35[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED36[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED37[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED38[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED39[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED40[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED41[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED42[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED43[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED44[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED45[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED46[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED47[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED48[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED49[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED50[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED51[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED52[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED53[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED54[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED55[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED56[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED57[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED58[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED59[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED60[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED61[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED62[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED63[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_ENABLE[] = {
+	 { "WB_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_EC_CONFIG[] = {
+	 { "DISPCLK_R_WB_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_G_WB_GATE_DIS", 1, 1, &umr_bitfield_default },
+	 { "DISPCLK_G_WBSCL_GATE_DIS", 2, 2, &umr_bitfield_default },
+	 { "WB_LB_LS_DIS", 6, 6, &umr_bitfield_default },
+	 { "WB_LB_SD_DIS", 7, 7, &umr_bitfield_default },
+	 { "WB_LUT_LS_DIS", 8, 8, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_MODE_SEL", 9, 10, &umr_bitfield_default },
+	 { "WB_TEST_CLK_SEL", 12, 15, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_STATE", 19, 20, &umr_bitfield_default },
+	 { "WB_RAM_PW_SAVE_MODE", 23, 23, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
+	 { "LUT_MEM_PWR_STATE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_MODE[] = {
+	 { "CNV_FRAME_CAPTURE_RATE", 8, 9, &umr_bitfield_default },
+	 { "CNV_WINDOW_CROP_EN", 12, 12, &umr_bitfield_default },
+	 { "CNV_STEREO_TYPE", 13, 14, &umr_bitfield_default },
+	 { "CNV_INTERLACED_MODE", 15, 15, &umr_bitfield_default },
+	 { "CNV_EYE_SELECTION", 16, 17, &umr_bitfield_default },
+	 { "CNV_STEREO_POLARITY", 18, 18, &umr_bitfield_default },
+	 { "CNV_INTERLACED_FIELD_ORDER", 19, 19, &umr_bitfield_default },
+	 { "CNV_STEREO_SPLIT", 20, 20, &umr_bitfield_default },
+	 { "CNV_NEW_CONTENT", 24, 24, &umr_bitfield_default },
+	 { "CNV_FRAME_CAPTURE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_WINDOW_START[] = {
+	 { "CNV_WINDOW_START_X", 0, 11, &umr_bitfield_default },
+	 { "CNV_WINDOW_START_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_WINDOW_SIZE[] = {
+	 { "CNV_WINDOW_WIDTH", 0, 11, &umr_bitfield_default },
+	 { "CNV_WINDOW_HEIGHT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_UPDATE[] = {
+	 { "CNV_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CNV_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "CNV_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_SOURCE_SIZE[] = {
+	 { "CNV_SOURCE_WIDTH", 0, 14, &umr_bitfield_default },
+	 { "CNV_SOURCE_HEIGHT", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CONTROL[] = {
+	 { "CNV_CSC_BYPASS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C11_C12[] = {
+	 { "CNV_CSC_C11", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C12", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C13_C14[] = {
+	 { "CNV_CSC_C13", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C14", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C21_C22[] = {
+	 { "CNV_CSC_C21", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C22", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C23_C24[] = {
+	 { "CNV_CSC_C23", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C24", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C31_C32[] = {
+	 { "CNV_CSC_C31", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C32", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C33_C34[] = {
+	 { "CNV_CSC_C33", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C34", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_R[] = {
+	 { "CNV_CSC_ROUND_OFFSET_R", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_G[] = {
+	 { "CNV_CSC_ROUND_OFFSET_G", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_B[] = {
+	 { "CNV_CSC_ROUND_OFFSET_B", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_R[] = {
+	 { "CNV_CSC_CLAMP_UPPER_R", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_G[] = {
+	 { "CNV_CSC_CLAMP_UPPER_G", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_B[] = {
+	 { "CNV_CSC_CLAMP_UPPER_B", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CNTL[] = {
+	 { "CNV_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_RED[] = {
+	 { "CNV_TEST_CRC_RED_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_GREEN[] = {
+	 { "CNV_TEST_CRC_GREEN_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_BLUE[] = {
+	 { "CNV_TEST_CRC_BLUE_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_DEBUG_CTRL[] = {
+	 { "WB_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_DEBUG_SEL", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_DBG_MODE[] = {
+	 { "WB_DBG_MODE_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_DBG_DIN_FMT", 1, 1, &umr_bitfield_default },
+	 { "WB_DBG_36MODE", 2, 2, &umr_bitfield_default },
+	 { "WB_DBG_CMAP", 3, 3, &umr_bitfield_default },
+	 { "WB_DBG_PXLRATE_ERROR", 8, 8, &umr_bitfield_default },
+	 { "WB_DBG_SOURCE_WIDTH", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_HW_DEBUG[] = {
+	 { "WB_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_INPUT_SELECT[] = {
+	 { "CNV_INPUT_SRC_SELECT", 0, 1, &umr_bitfield_default },
+	 { "CNV_INPUT_PIPE_SELECT", 2, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_DEBUG_INDEX[] = {
+	 { "CNV_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CNV_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_DEBUG_DATA[] = {
+	 { "CNV_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_SOFT_RESET[] = {
+	 { "WB_SOFT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED0[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED1[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED2[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED3[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED4[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED5[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED6[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED7[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED8[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED9[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED10[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED11[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[] = {
+	 { "OUTSTRMPAY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_STREAM_PAYLOAD_CAPABILITY[] = {
+	 { "INSTRMPAY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL6[] = {
+	 { "INPUT_CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL6[] = {
+	 { "CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR5[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG6[] = {
+	 { "DCIO_DEBUG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR06[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT06[] = {
+	 { "V_TOTAL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
+	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
+	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
+	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
+	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
+	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
+	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
+	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
+	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
+	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
+	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
+	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_ENABLE_STATUS[] = {
+	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
+	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
+	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
+	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL7[] = {
+	 { "INPUT_CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL7[] = {
+	 { "CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR6[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG7[] = {
+	 { "DCIO_DEBUG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR07[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT07[] = {
+	 { "V_TOTAL_B8", 0, 0, &umr_bitfield_default },
+	 { "V_DISP_END_B8", 1, 1, &umr_bitfield_default },
+	 { "V_SYNC_START_B8", 2, 2, &umr_bitfield_default },
+	 { "V_BLANK_START_B8", 3, 3, &umr_bitfield_default },
+	 { "LINE_CMP_B8", 4, 4, &umr_bitfield_default },
+	 { "V_TOTAL_B9", 5, 5, &umr_bitfield_default },
+	 { "V_DISP_END_B9", 6, 6, &umr_bitfield_default },
+	 { "V_SYNC_START_B9", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
+	 { "MISC", 0, 3, &umr_bitfield_default },
+	 { "COLOR", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
+	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
+	 { "LOCATION", 0, 5, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[] = {
+	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[] = {
+	 { "MULTICHANNEL2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL2_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL2_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[] = {
+	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[] = {
+	 { "MULTICHANNEL6_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL6_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL6_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
+	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
+	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
+	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
+	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
+	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
+	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
+	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
+	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[] = {
+	 { "CHANNEL_STATUS_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[] = {
+	 { "CHANNEL_STATUS_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGADCC_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CONTROL[] = {
+	 { "STREAM_0_INTERRUPT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_INTERRUPT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_INTERRUPT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_INTERRUPT_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_INTERRUPT_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_INTERRUPT_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_INTERRUPT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_INTERRUPT_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_INTERRUPT_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_INTERRUPT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_INTERRUPT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_INTERRUPT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_INTERRUPT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_INTERRUPT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "CONTROLLER_INTERRUPT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GLOBAL_INTERRUPT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG8[] = {
+	 { "DCIO_DEBUG8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR08[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT08[] = {
+	 { "ROW_SCAN_START", 0, 4, &umr_bitfield_default },
+	 { "BYTE_PAN", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWALL_CLOCK_COUNTER_ALIAS[] = {
+	 { "WALL_CLOCK_COUNTER_ALIAS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
+	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
+	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF02_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR8[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_STATUS[] = {
+	 { "STREAM_0_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_INTERRUPT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_INTERRUPT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_INTERRUPT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_INTERRUPT_STATUS", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_INTERRUPT_STATUS", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_INTERRUPT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_INTERRUPT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_INTERRUPT_STATUS", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_INTERRUPT_STATUS", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_INTERRUPT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_INTERRUPT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_INTERRUPT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_INTERRUPT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "CONTROLLER_INTERRUPT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GLOBAL_INTERRUPT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG9[] = {
+	 { "DCIO_DEBUG9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR09[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT09[] = {
+	 { "MAX_ROW_SCAN", 0, 4, &umr_bitfield_default },
+	 { "V_BLANK_START_B9", 5, 5, &umr_bitfield_default },
+	 { "LINE_CMP_B9", 6, 6, &umr_bitfield_default },
+	 { "DOUBLE_CHAR_HEIGHT", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[] = {
+	 { "PRESENTATION_TIME_OFFSET_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMIF_DEBUG02_CORE1[] = {
+	 { "DB_DATA", 0, 15, &umr_bitfield_default },
+	 { "MC_RDRET_COUNT_EN", 16, 16, &umr_bitfield_default },
+	 { "MC_RDRET_COUNTER", 17, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR9[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGA[] = {
+	 { "DCIO_DEBUGA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0A[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0A[] = {
+	 { "CURSOR_START", 0, 4, &umr_bitfield_default },
+	 { "CURSOR_DISABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF04_DBG_DCCIF_E[] = {
+	 { "DBG_DCCIF_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR10[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION6[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGB[] = {
+	 { "DCIO_DEBUGB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0B[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0B[] = {
+	 { "CURSOR_END", 0, 4, &umr_bitfield_default },
+	 { "CURSOR_SKEW", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
+	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF05_DBG_DCCIF_F[] = {
+	 { "DBG_DCCIF_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWALL_CLOCK_COUNTER[] = {
+	 { "WALL_CLOCK_COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION7[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_12[] = {
+	 { "IDEC_MVP_DATA_A_H", 0, 0, &umr_bitfield_default },
+	 { "IDEC_MVP_DATA_A", 1, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGC[] = {
+	 { "DCIO_DEBUGC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0C[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0C[] = {
+	 { "DISP_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_RENDER_CONTROL[] = {
+	 { "VGA_BLINK_RATE", 0, 4, &umr_bitfield_default },
+	 { "VGA_BLINK_MODE", 5, 6, &umr_bitfield_default },
+	 { "VGA_CURSOR_BLINK_INVERT", 7, 7, &umr_bitfield_default },
+	 { "VGA_EXTD_ADDR_COUNT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_VSTATUS_CNTL", 16, 17, &umr_bitfield_default },
+	 { "VGA_LOCK_8DOT", 24, 24, &umr_bitfield_default },
+	 { "VGAREG_LINECMP_COMPATIBILITY_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SEQUENCER_RESET_CONTROL[] = {
+	 { "D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 0, 0, &umr_bitfield_default },
+	 { "D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 1, 1, &umr_bitfield_default },
+	 { "D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 2, 2, &umr_bitfield_default },
+	 { "D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 3, 3, &umr_bitfield_default },
+	 { "D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 4, 4, &umr_bitfield_default },
+	 { "D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 5, 5, &umr_bitfield_default },
+	 { "D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 8, 8, &umr_bitfield_default },
+	 { "D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 9, 9, &umr_bitfield_default },
+	 { "D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 10, 10, &umr_bitfield_default },
+	 { "D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 11, 11, &umr_bitfield_default },
+	 { "D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 12, 12, &umr_bitfield_default },
+	 { "D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 13, 13, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT", 17, 17, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INDEX_SELECT", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MODE_CONTROL[] = {
+	 { "VGA_ATI_LINEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_LUT_PALETTE_UPDATE_MODE", 4, 5, &umr_bitfield_default },
+	 { "VGA_128K_APERTURE_PAGING", 8, 8, &umr_bitfield_default },
+	 { "VGA_TEXT_132_COLUMNS_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SURFACE_PITCH_SELECT[] = {
+	 { "VGA_SURFACE_PITCH_SELECT", 0, 1, &umr_bitfield_default },
+	 { "VGA_SURFACE_HEIGHT_SELECT", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_INDEX[] = {
+	 { "VGA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "VGA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF1_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF1_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_DATA[] = {
+	 { "VGA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF2_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF2_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS_HIGH[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HDP_CONTROL[] = {
+	 { "VGA_MEM_PAGE_SELECT_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_MEMORY_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "VGA_RBBM_LOCK_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RESET_CONTROL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_CACHE_CONTROL[] = {
+	 { "VGA_WRITE_THROUGH_CACHE_DIS", 0, 0, &umr_bitfield_default },
+	 { "VGA_READ_CACHE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_READ_BUFFER_INVALIDATE", 16, 16, &umr_bitfield_default },
+	 { "VGA_DCCIF_W256ONLY", 20, 20, &umr_bitfield_default },
+	 { "VGA_DCCIF_WC_TIMEOUT", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD1VGA_CONTROL[] = {
+	 { "D1VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D1VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D1VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D1VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D1VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD2VGA_CONTROL[] = {
+	 { "D2VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D2VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D2VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D2VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D2VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HW_DEBUG[] = {
+	 { "VGA_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
+	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR12[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION8[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_13[] = {
+	 { "IDED_MVP_DATA_B_H", 0, 0, &umr_bitfield_default },
+	 { "IDED_MVP_DATA_B", 1, 24, &umr_bitfield_default },
+	 { "IDED_START_READ_B", 25, 25, &umr_bitfield_default },
+	 { "IDED_READ_FIFO_ENTRY_DE_B", 26, 26, &umr_bitfield_default },
+	 { "IDED_WRITE_ADD_B", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGD[] = {
+	 { "DCIO_DEBUGD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0D[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0D[] = {
+	 { "DISP_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS[] = {
+	 { "VGA_MEM_ACCESS_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_STATUS", 1, 1, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_CONTROL[] = {
+	 { "VGA_MEM_ACCESS_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_MASK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS_CLEAR[] = {
+	 { "VGA_MEM_ACCESS_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_STATUS[] = {
+	 { "VGA_MEM_ACCESS_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MAIN_CONTROL[] = {
+	 { "VGA_CRTC_TIMEOUT", 0, 1, &umr_bitfield_default },
+	 { "VGA_RENDER_TIMEOUT_COUNT", 3, 4, &umr_bitfield_default },
+	 { "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION", 5, 7, &umr_bitfield_default },
+	 { "VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT", 8, 9, &umr_bitfield_default },
+	 { "VGA_MC_WRITE_CLEAN_WAIT_DELAY", 12, 15, &umr_bitfield_default },
+	 { "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT", 16, 17, &umr_bitfield_default },
+	 { "VGA_READBACK_CRT_INTR_SOURCE_SELECT", 24, 25, &umr_bitfield_default },
+	 { "VGA_READBACK_SENSE_SWITCH_SELECT", 26, 26, &umr_bitfield_default },
+	 { "VGA_READ_URGENT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "VGA_WRITES_URGENT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "VGA_EXTERNAL_DAC_SENSE", 29, 29, &umr_bitfield_default },
+	 { "VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_CONTROL[] = {
+	 { "VGA_TEST_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_START", 8, 8, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DONE", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DISPBUF_SELECT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_INDEX[] = {
+	 { "VGA_DEBUG_READBACK_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_DATA[] = {
+	 { "VGA_DEBUG_READBACK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
+	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTREAM_SYNCHRONIZATION[] = {
+	 { "STREAM_0_SYNCHRONIZATION", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_SYNCHRONIZATION", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_SYNCHRONIZATION", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_SYNCHRONIZATION", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_SYNCHRONIZATION", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_SYNCHRONIZATION", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_SYNCHRONIZATION", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_SYNCHRONIZATION", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_SYNCHRONIZATION", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_SYNCHRONIZATION", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_SYNCHRONIZATION", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_SYNCHRONIZATION", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_SYNCHRONIZATION", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_SYNCHRONIZATION", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_SYNCHRONIZATION", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_SYNCHRONIZATION", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR13[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION9[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_14[] = {
+	 { "IDEE_READ_ADD", 0, 2, &umr_bitfield_default },
+	 { "IDEE_WRITE_ADD_A", 3, 5, &umr_bitfield_default },
+	 { "IDEE_WRITE_ADD_B", 6, 8, &umr_bitfield_default },
+	 { "IDEE_START_READ", 9, 9, &umr_bitfield_default },
+	 { "IDEE_START_READ_B", 10, 10, &umr_bitfield_default },
+	 { "IDEE_START_INCR_WR_A", 11, 11, &umr_bitfield_default },
+	 { "IDEE_START_INCR_WR_B", 12, 12, &umr_bitfield_default },
+	 { "IDEE_WRITE2FIFO", 13, 13, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENTRY_DE", 14, 14, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENTRY_DE_B", 15, 15, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_DE", 16, 16, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_DE_B", 17, 17, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "IDEE_CRTC1_CNTL_CAPTURE_START_A", 19, 19, &umr_bitfield_default },
+	 { "IDEE_CRC_PHASE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGE[] = {
+	 { "DCIO_DIGA_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0E[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0E[] = {
+	 { "CURSOR_LOC_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_DATA[] = {
+	 { "VCRTC_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_IDX[] = {
+	 { "VCRTC_IDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_WT[] = {
+	 { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENS1[] = {
+	 { "NO_DISPLAY", 0, 0, &umr_bitfield_default },
+	 { "VGA_VSTATUS", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_READ_BACK", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION10[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_15[] = {
+	 { "IDEF_MVP_ASYNC_FIFO_WEN", 0, 0, &umr_bitfield_default },
+	 { "IDEF_MVP_ASYNC_FIFO_WDATA", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGF[] = {
+	 { "DCIO_DIGB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0F[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0F[] = {
+	 { "CURSOR_LOC_LO", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_WT[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENENB[] = {
+	 { "BLK_IO_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENS0[] = {
+	 { "SENSE_SWITCH", 4, 4, &umr_bitfield_default },
+	 { "CRT_INTR", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_R_INDEX[] = {
+	 { "DAC_R_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEQ8_DATA[] = {
+	 { "SEQ_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MASK[] = {
+	 { "DAC_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_W_INDEX[] = {
+	 { "DAC_W_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_RD[] = {
+	 { "VSYNC_SEL_R", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH8_DATA[] = {
+	 { "GRPH_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH8_IDX[] = {
+	 { "GRPH_IDX", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_RD[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD3VGA_CONTROL[] = {
+	 { "D3VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D3VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D3VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D3VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D3VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD4VGA_CONTROL[] = {
+	 { "D4VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D4VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D4VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D4VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D4VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD5VGA_CONTROL[] = {
+	 { "D5VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D5VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D5VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D5VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D5VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD6VGA_CONTROL[] = {
+	 { "D6VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D6VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D6VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D6VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D6VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SOURCE_SELECT[] = {
+	 { "VGA_SOURCE_SEL_A", 0, 2, &umr_bitfield_default },
+	 { "VGA_SOURCE_SEL_B", 8, 10, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/dce110_regs.i b/src/lib/ip/dce110_regs.i
new file mode 100644
index 0000000..14232f7
--- /dev/null
+++ b/src/lib/ip/dce110_regs.i
@@ -0,0 +1,7565 @@
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID", REG_SMC, 0x0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG", REG_SMC, 0x0, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG", REG_SMC, 0x0, &ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL0", REG_SMC, 0x0, &ixAZALIA_INPUT_CRC0_CHANNEL0[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL0)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL0[0]), 0, 0 },
+	{ "ixAZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0, &ixAZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL0", REG_SMC, 0x0, &ixAZALIA_CRC0_CHANNEL0[0], sizeof(ixAZALIA_CRC0_CHANNEL0)/sizeof(ixAZALIA_CRC0_CHANNEL0[0]), 0, 0 },
+	{ "mmGLOBAL_CAPABILITIES", REG_MMIO, 0x0, &mmGLOBAL_CAPABILITIES[0], sizeof(mmGLOBAL_CAPABILITIES)/sizeof(mmGLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "ixDCIO_DEBUG_ID", REG_SMC, 0x0, &ixDCIO_DEBUG_ID[0], sizeof(ixDCIO_DEBUG_ID)/sizeof(ixDCIO_DEBUG_ID[0]), 0, 0 },
+	{ "ixFMT_DEBUG_ID", REG_SMC, 0x0, &ixFMT_DEBUG_ID[0], sizeof(ixFMT_DEBUG_ID)/sizeof(ixFMT_DEBUG_ID[0]), 0, 0 },
+	{ "ixATTR00", REG_SMC, 0x0, &ixATTR00[0], sizeof(ixATTR00)/sizeof(ixATTR00[0]), 0, 0 },
+	{ "ixSEQ00", REG_SMC, 0x0, &ixSEQ00[0], sizeof(ixSEQ00)/sizeof(ixSEQ00[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x1, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x1, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID", REG_SMC, 0x1, &ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0]), 0, 0 },
+	{ "ixAZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x1, &ixAZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL1", REG_SMC, 0x1, &ixAZALIA_INPUT_CRC0_CHANNEL1[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL1)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL1[0]), 0, 0 },
+	{ "mmOUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x1, &mmOUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmOUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmOUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmINPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x1, &mmINPUT_PAYLOAD_CAPABILITY[0], sizeof(mmINPUT_PAYLOAD_CAPABILITY)/sizeof(mmINPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "ixDPGV0_DEBUG00_DMIFARB", REG_SMC, 0x1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL1", REG_SMC, 0x1, &ixAZALIA_CRC0_CHANNEL1[0], sizeof(ixAZALIA_CRC0_CHANNEL1)/sizeof(ixAZALIA_CRC0_CHANNEL1[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR0", REG_SMC, 0x1, &ixAUDIO_DESCRIPTOR0[0], sizeof(ixAUDIO_DESCRIPTOR0)/sizeof(ixAUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1", REG_SMC, 0x1, &ixDCIO_DEBUG1[0], sizeof(ixDCIO_DEBUG1)/sizeof(ixDCIO_DEBUG1[0]), 0, 0 },
+	{ "ixFMT_DEBUG0", REG_SMC, 0x1, &ixFMT_DEBUG0[0], sizeof(ixFMT_DEBUG0)/sizeof(ixFMT_DEBUG0[0]), 0, 0 },
+	{ "ixATTR01", REG_SMC, 0x1, &ixATTR01[0], sizeof(ixATTR01)/sizeof(ixATTR01[0]), 0, 0 },
+	{ "ixSEQ01", REG_SMC, 0x1, &ixSEQ01[0], sizeof(ixSEQ01)/sizeof(ixSEQ01[0]), 0, 0 },
+	{ "mmCORB_LOWER_BASE_ADDRESS", REG_MMIO, 0x10, &mmCORB_LOWER_BASE_ADDRESS[0], sizeof(mmCORB_LOWER_BASE_ADDRESS)/sizeof(mmCORB_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION11", REG_SMC, 0x10, &ixSINK_DESCRIPTION11[0], sizeof(ixSINK_DESCRIPTION11)/sizeof(ixSINK_DESCRIPTION11[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_A", REG_SMC, 0x10, &ixDP_AUX_DEBUG_A[0], sizeof(ixDP_AUX_DEBUG_A)/sizeof(ixDP_AUX_DEBUG_A[0]), 0, 0 },
+	{ "ixDCIO_DEBUG10", REG_SMC, 0x10, &ixDCIO_DEBUG10[0], sizeof(ixDCIO_DEBUG10)/sizeof(ixDCIO_DEBUG10[0]), 0, 0 },
+	{ "ixATTR10", REG_SMC, 0x10, &ixATTR10[0], sizeof(ixATTR10)/sizeof(ixATTR10[0]), 0, 0 },
+	{ "ixCRT10", REG_SMC, 0x10, &ixCRT10[0], sizeof(ixCRT10)/sizeof(ixCRT10[0]), 0, 0 },
+	{ "mmDCFEV0_CRTC_PIXEL_RATE_CNTL", REG_MMIO, 0x104, &mmDCFEV0_CRTC_PIXEL_RATE_CNTL[0], sizeof(mmDCFEV0_CRTC_PIXEL_RATE_CNTL)/sizeof(mmDCFEV0_CRTC_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDPREFCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x108, &mmDPREFCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDPREFCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDPREFCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmREFCLK_CNTL", REG_MMIO, 0x109, &mmREFCLK_CNTL[0], sizeof(mmREFCLK_CNTL)/sizeof(mmREFCLK_CNTL[0]), 0, 0 },
+	{ "mmREFCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x10b, &mmREFCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmREFCLK_CGTT_BLK_CTRL_REG)/sizeof(mmREFCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmDPDBG_CLK_FORCE_CONTROL", REG_MMIO, 0x10d, &mmDPDBG_CLK_FORCE_CONTROL[0], sizeof(mmDPDBG_CLK_FORCE_CONTROL)/sizeof(mmDPDBG_CLK_FORCE_CONTROL[0]), 0, 0 },
+	{ "mmDCCG_PERFMON_CNTL2", REG_MMIO, 0x10e, &mmDCCG_PERFMON_CNTL2[0], sizeof(mmDCCG_PERFMON_CNTL2)/sizeof(mmDCCG_PERFMON_CNTL2[0]), 0, 0 },
+	{ "mmCORB_UPPER_BASE_ADDRESS", REG_MMIO, 0x11, &mmCORB_UPPER_BASE_ADDRESS[0], sizeof(mmCORB_UPPER_BASE_ADDRESS)/sizeof(mmCORB_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION12", REG_SMC, 0x11, &ixSINK_DESCRIPTION12[0], sizeof(ixSINK_DESCRIPTION12)/sizeof(ixSINK_DESCRIPTION12[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_B", REG_SMC, 0x11, &ixDP_AUX_DEBUG_B[0], sizeof(ixDP_AUX_DEBUG_B)/sizeof(ixDP_AUX_DEBUG_B[0]), 0, 0 },
+	{ "ixDCIO_DEBUG11", REG_SMC, 0x11, &ixDCIO_DEBUG11[0], sizeof(ixDCIO_DEBUG11)/sizeof(ixDCIO_DEBUG11[0]), 0, 0 },
+	{ "ixATTR11", REG_SMC, 0x11, &ixATTR11[0], sizeof(ixATTR11)/sizeof(ixATTR11[0]), 0, 0 },
+	{ "ixCRT11", REG_SMC, 0x11, &ixCRT11[0], sizeof(ixCRT11)/sizeof(ixCRT11[0]), 0, 0 },
+	{ "mmDCCG_CBUS_WRCMD_DELAY", REG_MMIO, 0x110, &mmDCCG_CBUS_WRCMD_DELAY[0], sizeof(mmDCCG_CBUS_WRCMD_DELAY)/sizeof(mmDCCG_CBUS_WRCMD_DELAY[0]), 0, 0 },
+	{ "mmDCCG_DS_DEBUG_CNTL", REG_MMIO, 0x112, &mmDCCG_DS_DEBUG_CNTL[0], sizeof(mmDCCG_DS_DEBUG_CNTL)/sizeof(mmDCCG_DS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DS_DTO_INCR", REG_MMIO, 0x113, &mmDCCG_DS_DTO_INCR[0], sizeof(mmDCCG_DS_DTO_INCR)/sizeof(mmDCCG_DS_DTO_INCR[0]), 0, 0 },
+	{ "mmDCCG_DS_DTO_MODULO", REG_MMIO, 0x114, &mmDCCG_DS_DTO_MODULO[0], sizeof(mmDCCG_DS_DTO_MODULO)/sizeof(mmDCCG_DS_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_DS_CNTL", REG_MMIO, 0x115, &mmDCCG_DS_CNTL[0], sizeof(mmDCCG_DS_CNTL)/sizeof(mmDCCG_DS_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DS_HW_CAL_INTERVAL", REG_MMIO, 0x116, &mmDCCG_DS_HW_CAL_INTERVAL[0], sizeof(mmDCCG_DS_HW_CAL_INTERVAL)/sizeof(mmDCCG_DS_HW_CAL_INTERVAL[0]), 0, 0 },
+	{ "mmSYMCLKG_CLOCK_ENABLE", REG_MMIO, 0x117, &mmSYMCLKG_CLOCK_ENABLE[0], sizeof(mmSYMCLKG_CLOCK_ENABLE)/sizeof(mmSYMCLKG_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDPREFCLK_CNTL", REG_MMIO, 0x118, &mmDPREFCLK_CNTL[0], sizeof(mmDPREFCLK_CNTL)/sizeof(mmDPREFCLK_CNTL[0]), 0, 0 },
+	{ "mmDCE_VERSION", REG_MMIO, 0x11e, &mmDCE_VERSION[0], sizeof(mmDCE_VERSION)/sizeof(mmDCE_VERSION[0]), 0, 0 },
+	{ "mmVGA_MEM_WRITE_PAGE_ADDR", REG_MMIO, 0x12, &mmVGA_MEM_WRITE_PAGE_ADDR[0], sizeof(mmVGA_MEM_WRITE_PAGE_ADDR)/sizeof(mmVGA_MEM_WRITE_PAGE_ADDR[0]), 0, 0 },
+	{ "mmCORB_WRITE_POINTER", REG_MMIO, 0x12, &mmCORB_WRITE_POINTER[0], sizeof(mmCORB_WRITE_POINTER)/sizeof(mmCORB_WRITE_POINTER[0]), 0, 0 },
+	{ "mmCORB_READ_POINTER", REG_MMIO, 0x12, &mmCORB_READ_POINTER[0], sizeof(mmCORB_READ_POINTER)/sizeof(mmCORB_READ_POINTER[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_C", REG_SMC, 0x12, &ixDP_AUX_DEBUG_C[0], sizeof(ixDP_AUX_DEBUG_C)/sizeof(ixDP_AUX_DEBUG_C[0]), 0, 0 },
+	{ "ixDCIO_DEBUG12", REG_SMC, 0x12, &ixDCIO_DEBUG12[0], sizeof(ixDCIO_DEBUG12)/sizeof(ixDCIO_DEBUG12[0]), 0, 0 },
+	{ "ixATTR12", REG_SMC, 0x12, &ixATTR12[0], sizeof(ixATTR12)/sizeof(ixATTR12[0]), 0, 0 },
+	{ "ixCRT12", REG_SMC, 0x12, &ixCRT12[0], sizeof(ixCRT12)/sizeof(ixCRT12[0]), 0, 0 },
+	{ "mmDCCG_GTC_CNTL", REG_MMIO, 0x120, &mmDCCG_GTC_CNTL[0], sizeof(mmDCCG_GTC_CNTL)/sizeof(mmDCCG_GTC_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_INCR", REG_MMIO, 0x121, &mmDCCG_GTC_DTO_INCR[0], sizeof(mmDCCG_GTC_DTO_INCR)/sizeof(mmDCCG_GTC_DTO_INCR[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_MODULO", REG_MMIO, 0x122, &mmDCCG_GTC_DTO_MODULO[0], sizeof(mmDCCG_GTC_DTO_MODULO)/sizeof(mmDCCG_GTC_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_GTC_CURRENT", REG_MMIO, 0x123, &mmDCCG_GTC_CURRENT[0], sizeof(mmDCCG_GTC_CURRENT)/sizeof(mmDCCG_GTC_CURRENT[0]), 0, 0 },
+	{ "mmDENTIST_DISPCLK_CNTL", REG_MMIO, 0x124, &mmDENTIST_DISPCLK_CNTL[0], sizeof(mmDENTIST_DISPCLK_CNTL)/sizeof(mmDENTIST_DISPCLK_CNTL[0]), 0, 0 },
+	{ "mmDAC_CLK_ENABLE", REG_MMIO, 0x128, &mmDAC_CLK_ENABLE[0], sizeof(mmDAC_CLK_ENABLE)/sizeof(mmDAC_CLK_ENABLE[0]), 0, 0 },
+	{ "mmDVO_CLK_ENABLE", REG_MMIO, 0x129, &mmDVO_CLK_ENABLE[0], sizeof(mmDVO_CLK_ENABLE)/sizeof(mmDVO_CLK_ENABLE[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_WRITE", REG_MMIO, 0x12a, &mmAVSYNC_COUNTER_WRITE[0], sizeof(mmAVSYNC_COUNTER_WRITE)/sizeof(mmAVSYNC_COUNTER_WRITE[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_CONTROL", REG_MMIO, 0x12b, &mmAVSYNC_COUNTER_CONTROL[0], sizeof(mmAVSYNC_COUNTER_CONTROL)/sizeof(mmAVSYNC_COUNTER_CONTROL[0]), 0, 0 },
+	{ "mmDMCU_SMU_INTERRUPT_CNTL", REG_MMIO, 0x12c, &mmDMCU_SMU_INTERRUPT_CNTL[0], sizeof(mmDMCU_SMU_INTERRUPT_CNTL)/sizeof(mmDMCU_SMU_INTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmSMU_CONTROL", REG_MMIO, 0x12d, &mmSMU_CONTROL[0], sizeof(mmSMU_CONTROL)/sizeof(mmSMU_CONTROL[0]), 0, 0 },
+	{ "mmSMU_INTERRUPT_CONTROL", REG_MMIO, 0x12e, &mmSMU_INTERRUPT_CONTROL[0], sizeof(mmSMU_INTERRUPT_CONTROL)/sizeof(mmSMU_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_READ", REG_MMIO, 0x12f, &mmAVSYNC_COUNTER_READ[0], sizeof(mmAVSYNC_COUNTER_READ)/sizeof(mmAVSYNC_COUNTER_READ[0]), 0, 0 },
+	{ "mmVGA_MEM_READ_PAGE_ADDR", REG_MMIO, 0x13, &mmVGA_MEM_READ_PAGE_ADDR[0], sizeof(mmVGA_MEM_READ_PAGE_ADDR)/sizeof(mmVGA_MEM_READ_PAGE_ADDR[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION14", REG_SMC, 0x13, &ixSINK_DESCRIPTION14[0], sizeof(ixSINK_DESCRIPTION14)/sizeof(ixSINK_DESCRIPTION14[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_D", REG_SMC, 0x13, &ixDP_AUX_DEBUG_D[0], sizeof(ixDP_AUX_DEBUG_D)/sizeof(ixDP_AUX_DEBUG_D[0]), 0, 0 },
+	{ "ixDCIO_DEBUG13", REG_SMC, 0x13, &ixDCIO_DEBUG13[0], sizeof(ixDCIO_DEBUG13)/sizeof(ixDCIO_DEBUG13[0]), 0, 0 },
+	{ "mmCORB_STATUS", REG_MMIO, 0x13, &mmCORB_STATUS[0], sizeof(mmCORB_STATUS)/sizeof(mmCORB_STATUS[0]), 0, 0 },
+	{ "mmCORB_SIZE", REG_MMIO, 0x13, &mmCORB_SIZE[0], sizeof(mmCORB_SIZE)/sizeof(mmCORB_SIZE[0]), 0, 0 },
+	{ "ixATTR13", REG_SMC, 0x13, &ixATTR13[0], sizeof(ixATTR13)/sizeof(ixATTR13[0]), 0, 0 },
+	{ "ixCRT13", REG_SMC, 0x13, &ixCRT13[0], sizeof(ixCRT13)/sizeof(ixCRT13[0]), 0, 0 },
+	{ "mmMILLISECOND_TIME_BASE_DIV", REG_MMIO, 0x130, &mmMILLISECOND_TIME_BASE_DIV[0], sizeof(mmMILLISECOND_TIME_BASE_DIV)/sizeof(mmMILLISECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDISPCLK_FREQ_CHANGE_CNTL", REG_MMIO, 0x131, &mmDISPCLK_FREQ_CHANGE_CNTL[0], sizeof(mmDISPCLK_FREQ_CHANGE_CNTL)/sizeof(mmDISPCLK_FREQ_CHANGE_CNTL[0]), 0, 0 },
+	{ "mmDC_MEM_GLOBAL_PWR_REQ_CNTL", REG_MMIO, 0x132, &mmDC_MEM_GLOBAL_PWR_REQ_CNTL[0], sizeof(mmDC_MEM_GLOBAL_PWR_REQ_CNTL)/sizeof(mmDC_MEM_GLOBAL_PWR_REQ_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PERFMON_CNTL", REG_MMIO, 0x133, &mmDCCG_PERFMON_CNTL[0], sizeof(mmDCCG_PERFMON_CNTL)/sizeof(mmDCCG_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GATE_DISABLE_CNTL", REG_MMIO, 0x134, &mmDCCG_GATE_DISABLE_CNTL[0], sizeof(mmDCCG_GATE_DISABLE_CNTL)/sizeof(mmDCCG_GATE_DISABLE_CNTL[0]), 0, 0 },
+	{ "mmDISPCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x135, &mmDISPCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmSCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x136, &mmSCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmDCCG_CAC_STATUS", REG_MMIO, 0x137, &mmDCCG_CAC_STATUS[0], sizeof(mmDCCG_CAC_STATUS)/sizeof(mmDCCG_CAC_STATUS[0]), 0, 0 },
+	{ "mmPIXCLK1_RESYNC_CNTL", REG_MMIO, 0x138, &mmPIXCLK1_RESYNC_CNTL[0], sizeof(mmPIXCLK1_RESYNC_CNTL)/sizeof(mmPIXCLK1_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPIXCLK2_RESYNC_CNTL", REG_MMIO, 0x139, &mmPIXCLK2_RESYNC_CNTL[0], sizeof(mmPIXCLK2_RESYNC_CNTL)/sizeof(mmPIXCLK2_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPIXCLK0_RESYNC_CNTL", REG_MMIO, 0x13a, &mmPIXCLK0_RESYNC_CNTL[0], sizeof(mmPIXCLK0_RESYNC_CNTL)/sizeof(mmPIXCLK0_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmMICROSECOND_TIME_BASE_DIV", REG_MMIO, 0x13b, &mmMICROSECOND_TIME_BASE_DIV[0], sizeof(mmMICROSECOND_TIME_BASE_DIV)/sizeof(mmMICROSECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDCCG_GATE_DISABLE_CNTL2", REG_MMIO, 0x13c, &mmDCCG_GATE_DISABLE_CNTL2[0], sizeof(mmDCCG_GATE_DISABLE_CNTL2)/sizeof(mmDCCG_GATE_DISABLE_CNTL2[0]), 0, 0 },
+	{ "mmSYMCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x13d, &mmSYMCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSYMCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSYMCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmPHYPLL_PIXCLK_CNTL", REG_MMIO, 0x13e, &mmPHYPLL_PIXCLK_CNTL[0], sizeof(mmPHYPLL_PIXCLK_CNTL)/sizeof(mmPHYPLL_PIXCLK_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DISP_CNTL_REG", REG_MMIO, 0x13f, &mmDCCG_DISP_CNTL_REG[0], sizeof(mmDCCG_DISP_CNTL_REG)/sizeof(mmDCCG_DISP_CNTL_REG[0]), 0, 0 },
+	{ "mmRIRB_LOWER_BASE_ADDRESS", REG_MMIO, 0x14, &mmRIRB_LOWER_BASE_ADDRESS[0], sizeof(mmRIRB_LOWER_BASE_ADDRESS)/sizeof(mmRIRB_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION15", REG_SMC, 0x14, &ixSINK_DESCRIPTION15[0], sizeof(ixSINK_DESCRIPTION15)/sizeof(ixSINK_DESCRIPTION15[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_E", REG_SMC, 0x14, &ixDP_AUX_DEBUG_E[0], sizeof(ixDP_AUX_DEBUG_E)/sizeof(ixDP_AUX_DEBUG_E[0]), 0, 0 },
+	{ "ixDCIO_DEBUG14", REG_SMC, 0x14, &ixDCIO_DEBUG14[0], sizeof(ixDCIO_DEBUG14)/sizeof(ixDCIO_DEBUG14[0]), 0, 0 },
+	{ "ixATTR14", REG_SMC, 0x14, &ixATTR14[0], sizeof(ixATTR14)/sizeof(ixATTR14[0]), 0, 0 },
+	{ "ixCRT14", REG_SMC, 0x14, &ixCRT14[0], sizeof(ixCRT14)/sizeof(ixCRT14[0]), 0, 0 },
+	{ "mmCRTC0_PIXEL_RATE_CNTL", REG_MMIO, 0x140, &mmCRTC0_PIXEL_RATE_CNTL[0], sizeof(mmCRTC0_PIXEL_RATE_CNTL)/sizeof(mmCRTC0_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO0_PHASE", REG_MMIO, 0x141, &mmDP_DTO0_PHASE[0], sizeof(mmDP_DTO0_PHASE)/sizeof(mmDP_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO0_MODULO", REG_MMIO, 0x142, &mmDP_DTO0_MODULO[0], sizeof(mmDP_DTO0_MODULO)/sizeof(mmDP_DTO0_MODULO[0]), 0, 0 },
+	{ "mmCRTC1_PIXEL_RATE_CNTL", REG_MMIO, 0x144, &mmCRTC1_PIXEL_RATE_CNTL[0], sizeof(mmCRTC1_PIXEL_RATE_CNTL)/sizeof(mmCRTC1_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO1_PHASE", REG_MMIO, 0x145, &mmDP_DTO1_PHASE[0], sizeof(mmDP_DTO1_PHASE)/sizeof(mmDP_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO1_MODULO", REG_MMIO, 0x146, &mmDP_DTO1_MODULO[0], sizeof(mmDP_DTO1_MODULO)/sizeof(mmDP_DTO1_MODULO[0]), 0, 0 },
+	{ "mmCRTC2_PIXEL_RATE_CNTL", REG_MMIO, 0x148, &mmCRTC2_PIXEL_RATE_CNTL[0], sizeof(mmCRTC2_PIXEL_RATE_CNTL)/sizeof(mmCRTC2_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO2_PHASE", REG_MMIO, 0x149, &mmDP_DTO2_PHASE[0], sizeof(mmDP_DTO2_PHASE)/sizeof(mmDP_DTO2_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO2_MODULO", REG_MMIO, 0x14a, &mmDP_DTO2_MODULO[0], sizeof(mmDP_DTO2_MODULO)/sizeof(mmDP_DTO2_MODULO[0]), 0, 0 },
+	{ "mmCRTC3_PIXEL_RATE_CNTL", REG_MMIO, 0x14c, &mmCRTC3_PIXEL_RATE_CNTL[0], sizeof(mmCRTC3_PIXEL_RATE_CNTL)/sizeof(mmCRTC3_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO3_PHASE", REG_MMIO, 0x14d, &mmDP_DTO3_PHASE[0], sizeof(mmDP_DTO3_PHASE)/sizeof(mmDP_DTO3_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO3_MODULO", REG_MMIO, 0x14e, &mmDP_DTO3_MODULO[0], sizeof(mmDP_DTO3_MODULO)/sizeof(mmDP_DTO3_MODULO[0]), 0, 0 },
+	{ "mmRIRB_UPPER_BASE_ADDRESS", REG_MMIO, 0x15, &mmRIRB_UPPER_BASE_ADDRESS[0], sizeof(mmRIRB_UPPER_BASE_ADDRESS)/sizeof(mmRIRB_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION16", REG_SMC, 0x15, &ixSINK_DESCRIPTION16[0], sizeof(ixSINK_DESCRIPTION16)/sizeof(ixSINK_DESCRIPTION16[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_F", REG_SMC, 0x15, &ixDP_AUX_DEBUG_F[0], sizeof(ixDP_AUX_DEBUG_F)/sizeof(ixDP_AUX_DEBUG_F[0]), 0, 0 },
+	{ "ixDCIO_DEBUG15", REG_SMC, 0x15, &ixDCIO_DEBUG15[0], sizeof(ixDCIO_DEBUG15)/sizeof(ixDCIO_DEBUG15[0]), 0, 0 },
+	{ "ixCRT15", REG_SMC, 0x15, &ixCRT15[0], sizeof(ixCRT15)/sizeof(ixCRT15[0]), 0, 0 },
+	{ "mmCRTC4_PIXEL_RATE_CNTL", REG_MMIO, 0x150, &mmCRTC4_PIXEL_RATE_CNTL[0], sizeof(mmCRTC4_PIXEL_RATE_CNTL)/sizeof(mmCRTC4_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO4_PHASE", REG_MMIO, 0x151, &mmDP_DTO4_PHASE[0], sizeof(mmDP_DTO4_PHASE)/sizeof(mmDP_DTO4_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO4_MODULO", REG_MMIO, 0x152, &mmDP_DTO4_MODULO[0], sizeof(mmDP_DTO4_MODULO)/sizeof(mmDP_DTO4_MODULO[0]), 0, 0 },
+	{ "mmCRTC5_PIXEL_RATE_CNTL", REG_MMIO, 0x154, &mmCRTC5_PIXEL_RATE_CNTL[0], sizeof(mmCRTC5_PIXEL_RATE_CNTL)/sizeof(mmCRTC5_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO5_PHASE", REG_MMIO, 0x155, &mmDP_DTO5_PHASE[0], sizeof(mmDP_DTO5_PHASE)/sizeof(mmDP_DTO5_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO5_MODULO", REG_MMIO, 0x156, &mmDP_DTO5_MODULO[0], sizeof(mmDP_DTO5_MODULO)/sizeof(mmDP_DTO5_MODULO[0]), 0, 0 },
+	{ "mmDCCG_SOFT_RESET", REG_MMIO, 0x15f, &mmDCCG_SOFT_RESET[0], sizeof(mmDCCG_SOFT_RESET)/sizeof(mmDCCG_SOFT_RESET[0]), 0, 0 },
+	{ "mmRESPONSE_INTERRUPT_COUNT", REG_MMIO, 0x16, &mmRESPONSE_INTERRUPT_COUNT[0], sizeof(mmRESPONSE_INTERRUPT_COUNT)/sizeof(mmRESPONSE_INTERRUPT_COUNT[0]), 0, 0 },
+	{ "mmRIRB_WRITE_POINTER", REG_MMIO, 0x16, &mmRIRB_WRITE_POINTER[0], sizeof(mmRIRB_WRITE_POINTER)/sizeof(mmRIRB_WRITE_POINTER[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_G", REG_SMC, 0x16, &ixDP_AUX_DEBUG_G[0], sizeof(ixDP_AUX_DEBUG_G)/sizeof(ixDP_AUX_DEBUG_G[0]), 0, 0 },
+	{ "ixDCIO_DEBUG16", REG_SMC, 0x16, &ixDCIO_DEBUG16[0], sizeof(ixDCIO_DEBUG16)/sizeof(ixDCIO_DEBUG16[0]), 0, 0 },
+	{ "ixCRT16", REG_SMC, 0x16, &ixCRT16[0], sizeof(ixCRT16)/sizeof(ixCRT16[0]), 0, 0 },
+	{ "mmSYMCLKA_CLOCK_ENABLE", REG_MMIO, 0x160, &mmSYMCLKA_CLOCK_ENABLE[0], sizeof(mmSYMCLKA_CLOCK_ENABLE)/sizeof(mmSYMCLKA_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_CTRL", REG_MMIO, 0x1600, &mmDMCU_CTRL[0], sizeof(mmDMCU_CTRL)/sizeof(mmDMCU_CTRL[0]), 0, 0 },
+	{ "mmDMCU_STATUS", REG_MMIO, 0x1601, &mmDMCU_STATUS[0], sizeof(mmDMCU_STATUS)/sizeof(mmDMCU_STATUS[0]), 0, 0 },
+	{ "mmDMCU_PC_START_ADDR", REG_MMIO, 0x1602, &mmDMCU_PC_START_ADDR[0], sizeof(mmDMCU_PC_START_ADDR)/sizeof(mmDMCU_PC_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_START_ADDR", REG_MMIO, 0x1603, &mmDMCU_FW_START_ADDR[0], sizeof(mmDMCU_FW_START_ADDR)/sizeof(mmDMCU_FW_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_END_ADDR", REG_MMIO, 0x1604, &mmDMCU_FW_END_ADDR[0], sizeof(mmDMCU_FW_END_ADDR)/sizeof(mmDMCU_FW_END_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_ISR_START_ADDR", REG_MMIO, 0x1605, &mmDMCU_FW_ISR_START_ADDR[0], sizeof(mmDMCU_FW_ISR_START_ADDR)/sizeof(mmDMCU_FW_ISR_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_HI", REG_MMIO, 0x1606, &mmDMCU_FW_CS_HI[0], sizeof(mmDMCU_FW_CS_HI)/sizeof(mmDMCU_FW_CS_HI[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_LO", REG_MMIO, 0x1607, &mmDMCU_FW_CS_LO[0], sizeof(mmDMCU_FW_CS_LO)/sizeof(mmDMCU_FW_CS_LO[0]), 0, 0 },
+	{ "mmDMCU_RAM_ACCESS_CTRL", REG_MMIO, 0x1608, &mmDMCU_RAM_ACCESS_CTRL[0], sizeof(mmDMCU_RAM_ACCESS_CTRL)/sizeof(mmDMCU_RAM_ACCESS_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_CTRL", REG_MMIO, 0x1609, &mmDMCU_ERAM_WR_CTRL[0], sizeof(mmDMCU_ERAM_WR_CTRL)/sizeof(mmDMCU_ERAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_DATA", REG_MMIO, 0x160a, &mmDMCU_ERAM_WR_DATA[0], sizeof(mmDMCU_ERAM_WR_DATA)/sizeof(mmDMCU_ERAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_CTRL", REG_MMIO, 0x160b, &mmDMCU_ERAM_RD_CTRL[0], sizeof(mmDMCU_ERAM_RD_CTRL)/sizeof(mmDMCU_ERAM_RD_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_DATA", REG_MMIO, 0x160c, &mmDMCU_ERAM_RD_DATA[0], sizeof(mmDMCU_ERAM_RD_DATA)/sizeof(mmDMCU_ERAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_CTRL", REG_MMIO, 0x160d, &mmDMCU_IRAM_WR_CTRL[0], sizeof(mmDMCU_IRAM_WR_CTRL)/sizeof(mmDMCU_IRAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_DATA", REG_MMIO, 0x160e, &mmDMCU_IRAM_WR_DATA[0], sizeof(mmDMCU_IRAM_WR_DATA)/sizeof(mmDMCU_IRAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_CTRL", REG_MMIO, 0x160f, &mmDMCU_IRAM_RD_CTRL[0], sizeof(mmDMCU_IRAM_RD_CTRL)/sizeof(mmDMCU_IRAM_RD_CTRL[0]), 0, 0 },
+	{ "mmSYMCLKB_CLOCK_ENABLE", REG_MMIO, 0x161, &mmSYMCLKB_CLOCK_ENABLE[0], sizeof(mmSYMCLKB_CLOCK_ENABLE)/sizeof(mmSYMCLKB_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_DATA", REG_MMIO, 0x1610, &mmDMCU_IRAM_RD_DATA[0], sizeof(mmDMCU_IRAM_RD_DATA)/sizeof(mmDMCU_IRAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_EVENT_TRIGGER", REG_MMIO, 0x1611, &mmDMCU_EVENT_TRIGGER[0], sizeof(mmDMCU_EVENT_TRIGGER)/sizeof(mmDMCU_EVENT_TRIGGER[0]), 0, 0 },
+	{ "mmDMCU_UC_INTERNAL_INT_STATUS", REG_MMIO, 0x1612, &mmDMCU_UC_INTERNAL_INT_STATUS[0], sizeof(mmDMCU_UC_INTERNAL_INT_STATUS)/sizeof(mmDMCU_UC_INTERNAL_INT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_SS_INTERRUPT_CNTL_STATUS", REG_MMIO, 0x1613, &mmDMCU_SS_INTERRUPT_CNTL_STATUS[0], sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS)/sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_STATUS", REG_MMIO, 0x1614, &mmDMCU_INTERRUPT_STATUS[0], sizeof(mmDMCU_INTERRUPT_STATUS)/sizeof(mmDMCU_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_HOST_EN_MASK", REG_MMIO, 0x1615, &mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_EN_MASK", REG_MMIO, 0x1616, &mmDMCU_INTERRUPT_TO_UC_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL", REG_MMIO, 0x1617, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0]), 0, 0 },
+	{ "mmDC_DMCU_SCRATCH", REG_MMIO, 0x1618, &mmDC_DMCU_SCRATCH[0], sizeof(mmDC_DMCU_SCRATCH)/sizeof(mmDC_DMCU_SCRATCH[0]), 0, 0 },
+	{ "mmDMCU_INT_CNT", REG_MMIO, 0x1619, &mmDMCU_INT_CNT[0], sizeof(mmDMCU_INT_CNT)/sizeof(mmDMCU_INT_CNT[0]), 0, 0 },
+	{ "mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS", REG_MMIO, 0x161a, &mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0], sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS)/sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0]), 0, 0 },
+	{ "mmDMCU_UC_CLK_GATING_CNTL", REG_MMIO, 0x161b, &mmDMCU_UC_CLK_GATING_CNTL[0], sizeof(mmDMCU_UC_CLK_GATING_CNTL)/sizeof(mmDMCU_UC_CLK_GATING_CNTL[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG1", REG_MMIO, 0x161c, &mmMASTER_COMM_DATA_REG1[0], sizeof(mmMASTER_COMM_DATA_REG1)/sizeof(mmMASTER_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG2", REG_MMIO, 0x161d, &mmMASTER_COMM_DATA_REG2[0], sizeof(mmMASTER_COMM_DATA_REG2)/sizeof(mmMASTER_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG3", REG_MMIO, 0x161e, &mmMASTER_COMM_DATA_REG3[0], sizeof(mmMASTER_COMM_DATA_REG3)/sizeof(mmMASTER_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmMASTER_COMM_CMD_REG", REG_MMIO, 0x161f, &mmMASTER_COMM_CMD_REG[0], sizeof(mmMASTER_COMM_CMD_REG)/sizeof(mmMASTER_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSYMCLKC_CLOCK_ENABLE", REG_MMIO, 0x162, &mmSYMCLKC_CLOCK_ENABLE[0], sizeof(mmSYMCLKC_CLOCK_ENABLE)/sizeof(mmSYMCLKC_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmMASTER_COMM_CNTL_REG", REG_MMIO, 0x1620, &mmMASTER_COMM_CNTL_REG[0], sizeof(mmMASTER_COMM_CNTL_REG)/sizeof(mmMASTER_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG1", REG_MMIO, 0x1621, &mmSLAVE_COMM_DATA_REG1[0], sizeof(mmSLAVE_COMM_DATA_REG1)/sizeof(mmSLAVE_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG2", REG_MMIO, 0x1622, &mmSLAVE_COMM_DATA_REG2[0], sizeof(mmSLAVE_COMM_DATA_REG2)/sizeof(mmSLAVE_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG3", REG_MMIO, 0x1623, &mmSLAVE_COMM_DATA_REG3[0], sizeof(mmSLAVE_COMM_DATA_REG3)/sizeof(mmSLAVE_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CMD_REG", REG_MMIO, 0x1624, &mmSLAVE_COMM_CMD_REG[0], sizeof(mmSLAVE_COMM_CMD_REG)/sizeof(mmSLAVE_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CNTL_REG", REG_MMIO, 0x1625, &mmSLAVE_COMM_CNTL_REG[0], sizeof(mmSLAVE_COMM_CNTL_REG)/sizeof(mmSLAVE_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_INDEX", REG_MMIO, 0x1626, &mmDMCU_TEST_DEBUG_INDEX[0], sizeof(mmDMCU_TEST_DEBUG_INDEX)/sizeof(mmDMCU_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_DATA", REG_MMIO, 0x1627, &mmDMCU_TEST_DEBUG_DATA[0], sizeof(mmDMCU_TEST_DEBUG_DATA)/sizeof(mmDMCU_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBL1_PWM_AMBIENT_LIGHT_LEVEL", REG_MMIO, 0x1628, &mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0], sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL)/sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_USER_LEVEL", REG_MMIO, 0x1629, &mmBL1_PWM_USER_LEVEL[0], sizeof(mmBL1_PWM_USER_LEVEL)/sizeof(mmBL1_PWM_USER_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_TARGET_ABM_LEVEL", REG_MMIO, 0x162a, &mmBL1_PWM_TARGET_ABM_LEVEL[0], sizeof(mmBL1_PWM_TARGET_ABM_LEVEL)/sizeof(mmBL1_PWM_TARGET_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_CURRENT_ABM_LEVEL", REG_MMIO, 0x162b, &mmBL1_PWM_CURRENT_ABM_LEVEL[0], sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL)/sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_FINAL_DUTY_CYCLE", REG_MMIO, 0x162c, &mmBL1_PWM_FINAL_DUTY_CYCLE[0], sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE)/sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_MINIMUM_DUTY_CYCLE", REG_MMIO, 0x162d, &mmBL1_PWM_MINIMUM_DUTY_CYCLE[0], sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE)/sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_ABM_CNTL", REG_MMIO, 0x162e, &mmBL1_PWM_ABM_CNTL[0], sizeof(mmBL1_PWM_ABM_CNTL)/sizeof(mmBL1_PWM_ABM_CNTL[0]), 0, 0 },
+	{ "mmBL1_PWM_BL_UPDATE_SAMPLE_RATE", REG_MMIO, 0x162f, &mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0], sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE)/sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmSYMCLKD_CLOCK_ENABLE", REG_MMIO, 0x163, &mmSYMCLKD_CLOCK_ENABLE[0], sizeof(mmSYMCLKD_CLOCK_ENABLE)/sizeof(mmSYMCLKD_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmBL1_PWM_GRP2_REG_LOCK", REG_MMIO, 0x1630, &mmBL1_PWM_GRP2_REG_LOCK[0], sizeof(mmBL1_PWM_GRP2_REG_LOCK)/sizeof(mmBL1_PWM_GRP2_REG_LOCK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_EN_MASK_1", REG_MMIO, 0x1631, &mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK_1)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1", REG_MMIO, 0x1632, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_STATUS1", REG_MMIO, 0x1634, &mmDMCU_DPRX_INTERRUPT_STATUS1[0], sizeof(mmDMCU_DPRX_INTERRUPT_STATUS1)/sizeof(mmDMCU_DPRX_INTERRUPT_STATUS1[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x1635, &mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x1636, &mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 },
+	{ "mmDC_ABM1_CNTL", REG_MMIO, 0x1638, &mmDC_ABM1_CNTL[0], sizeof(mmDC_ABM1_CNTL)/sizeof(mmDC_ABM1_CNTL[0]), 0, 0 },
+	{ "mmDC_ABM1_IPCSC_COEFF_SEL", REG_MMIO, 0x1639, &mmDC_ABM1_IPCSC_COEFF_SEL[0], sizeof(mmDC_ABM1_IPCSC_COEFF_SEL)/sizeof(mmDC_ABM1_IPCSC_COEFF_SEL[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_0", REG_MMIO, 0x163a, &mmDC_ABM1_ACE_OFFSET_SLOPE_0[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_1", REG_MMIO, 0x163b, &mmDC_ABM1_ACE_OFFSET_SLOPE_1[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_2", REG_MMIO, 0x163c, &mmDC_ABM1_ACE_OFFSET_SLOPE_2[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_3", REG_MMIO, 0x163d, &mmDC_ABM1_ACE_OFFSET_SLOPE_3[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_4", REG_MMIO, 0x163e, &mmDC_ABM1_ACE_OFFSET_SLOPE_4[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_12", REG_MMIO, 0x163f, &mmDC_ABM1_ACE_THRES_12[0], sizeof(mmDC_ABM1_ACE_THRES_12)/sizeof(mmDC_ABM1_ACE_THRES_12[0]), 0, 0 },
+	{ "mmSYMCLKE_CLOCK_ENABLE", REG_MMIO, 0x164, &mmSYMCLKE_CLOCK_ENABLE[0], sizeof(mmSYMCLKE_CLOCK_ENABLE)/sizeof(mmSYMCLKE_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_34", REG_MMIO, 0x1640, &mmDC_ABM1_ACE_THRES_34[0], sizeof(mmDC_ABM1_ACE_THRES_34)/sizeof(mmDC_ABM1_ACE_THRES_34[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_CNTL_MISC", REG_MMIO, 0x1641, &mmDC_ABM1_ACE_CNTL_MISC[0], sizeof(mmDC_ABM1_ACE_CNTL_MISC)/sizeof(mmDC_ABM1_ACE_CNTL_MISC[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS5", REG_MMIO, 0x1642, &mmDMCU_PERFMON_INTERRUPT_STATUS5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS5)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5", REG_MMIO, 0x1643, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS1", REG_MMIO, 0x1644, &mmDMCU_PERFMON_INTERRUPT_STATUS1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS2", REG_MMIO, 0x1645, &mmDMCU_PERFMON_INTERRUPT_STATUS2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS3", REG_MMIO, 0x1646, &mmDMCU_PERFMON_INTERRUPT_STATUS3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS4", REG_MMIO, 0x1647, &mmDMCU_PERFMON_INTERRUPT_STATUS4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4[0]), 0, 0 },
+	{ "mmDC_ABM1_DEBUG_MISC", REG_MMIO, 0x1649, &mmDC_ABM1_DEBUG_MISC[0], sizeof(mmDC_ABM1_DEBUG_MISC)/sizeof(mmDC_ABM1_DEBUG_MISC[0]), 0, 0 },
+	{ "mmDC_ABM1_HGLS_REG_READ_PROGRESS", REG_MMIO, 0x164a, &mmDC_ABM1_HGLS_REG_READ_PROGRESS[0], sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS)/sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_MISC_CTRL", REG_MMIO, 0x164b, &mmDC_ABM1_HG_MISC_CTRL[0], sizeof(mmDC_ABM1_HG_MISC_CTRL)/sizeof(mmDC_ABM1_HG_MISC_CTRL[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SUM_OF_LUMA", REG_MMIO, 0x164c, &mmDC_ABM1_LS_SUM_OF_LUMA[0], sizeof(mmDC_ABM1_LS_SUM_OF_LUMA)/sizeof(mmDC_ABM1_LS_SUM_OF_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_LUMA", REG_MMIO, 0x164d, &mmDC_ABM1_LS_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA", REG_MMIO, 0x164e, &mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_PIXEL_COUNT", REG_MMIO, 0x164f, &mmDC_ABM1_LS_PIXEL_COUNT[0], sizeof(mmDC_ABM1_LS_PIXEL_COUNT)/sizeof(mmDC_ABM1_LS_PIXEL_COUNT[0]), 0, 0 },
+	{ "mmSYMCLKF_CLOCK_ENABLE", REG_MMIO, 0x165, &mmSYMCLKF_CLOCK_ENABLE[0], sizeof(mmSYMCLKF_CLOCK_ENABLE)/sizeof(mmSYMCLKF_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_OVR_SCAN_BIN", REG_MMIO, 0x1650, &mmDC_ABM1_LS_OVR_SCAN_BIN[0], sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN)/sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES", REG_MMIO, 0x1651, &mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0], sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES)/sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT", REG_MMIO, 0x1652, &mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT", REG_MMIO, 0x1653, &mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_SAMPLE_RATE", REG_MMIO, 0x1654, &mmDC_ABM1_HG_SAMPLE_RATE[0], sizeof(mmDC_ABM1_HG_SAMPLE_RATE)/sizeof(mmDC_ABM1_HG_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SAMPLE_RATE", REG_MMIO, 0x1655, &mmDC_ABM1_LS_SAMPLE_RATE[0], sizeof(mmDC_ABM1_LS_SAMPLE_RATE)/sizeof(mmDC_ABM1_LS_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG", REG_MMIO, 0x1656, &mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0], sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG)/sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX", REG_MMIO, 0x1657, &mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX", REG_MMIO, 0x1658, &mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX", REG_MMIO, 0x1659, &mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX", REG_MMIO, 0x165a, &mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_1", REG_MMIO, 0x165b, &mmDC_ABM1_HG_RESULT_1[0], sizeof(mmDC_ABM1_HG_RESULT_1)/sizeof(mmDC_ABM1_HG_RESULT_1[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_2", REG_MMIO, 0x165c, &mmDC_ABM1_HG_RESULT_2[0], sizeof(mmDC_ABM1_HG_RESULT_2)/sizeof(mmDC_ABM1_HG_RESULT_2[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_3", REG_MMIO, 0x165d, &mmDC_ABM1_HG_RESULT_3[0], sizeof(mmDC_ABM1_HG_RESULT_3)/sizeof(mmDC_ABM1_HG_RESULT_3[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_4", REG_MMIO, 0x165e, &mmDC_ABM1_HG_RESULT_4[0], sizeof(mmDC_ABM1_HG_RESULT_4)/sizeof(mmDC_ABM1_HG_RESULT_4[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_5", REG_MMIO, 0x165f, &mmDC_ABM1_HG_RESULT_5[0], sizeof(mmDC_ABM1_HG_RESULT_5)/sizeof(mmDC_ABM1_HG_RESULT_5[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_6", REG_MMIO, 0x1660, &mmDC_ABM1_HG_RESULT_6[0], sizeof(mmDC_ABM1_HG_RESULT_6)/sizeof(mmDC_ABM1_HG_RESULT_6[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_7", REG_MMIO, 0x1661, &mmDC_ABM1_HG_RESULT_7[0], sizeof(mmDC_ABM1_HG_RESULT_7)/sizeof(mmDC_ABM1_HG_RESULT_7[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_8", REG_MMIO, 0x1662, &mmDC_ABM1_HG_RESULT_8[0], sizeof(mmDC_ABM1_HG_RESULT_8)/sizeof(mmDC_ABM1_HG_RESULT_8[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_9", REG_MMIO, 0x1663, &mmDC_ABM1_HG_RESULT_9[0], sizeof(mmDC_ABM1_HG_RESULT_9)/sizeof(mmDC_ABM1_HG_RESULT_9[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_10", REG_MMIO, 0x1664, &mmDC_ABM1_HG_RESULT_10[0], sizeof(mmDC_ABM1_HG_RESULT_10)/sizeof(mmDC_ABM1_HG_RESULT_10[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_11", REG_MMIO, 0x1665, &mmDC_ABM1_HG_RESULT_11[0], sizeof(mmDC_ABM1_HG_RESULT_11)/sizeof(mmDC_ABM1_HG_RESULT_11[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_12", REG_MMIO, 0x1666, &mmDC_ABM1_HG_RESULT_12[0], sizeof(mmDC_ABM1_HG_RESULT_12)/sizeof(mmDC_ABM1_HG_RESULT_12[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_13", REG_MMIO, 0x1667, &mmDC_ABM1_HG_RESULT_13[0], sizeof(mmDC_ABM1_HG_RESULT_13)/sizeof(mmDC_ABM1_HG_RESULT_13[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_14", REG_MMIO, 0x1668, &mmDC_ABM1_HG_RESULT_14[0], sizeof(mmDC_ABM1_HG_RESULT_14)/sizeof(mmDC_ABM1_HG_RESULT_14[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_15", REG_MMIO, 0x1669, &mmDC_ABM1_HG_RESULT_15[0], sizeof(mmDC_ABM1_HG_RESULT_15)/sizeof(mmDC_ABM1_HG_RESULT_15[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_16", REG_MMIO, 0x166a, &mmDC_ABM1_HG_RESULT_16[0], sizeof(mmDC_ABM1_HG_RESULT_16)/sizeof(mmDC_ABM1_HG_RESULT_16[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_17", REG_MMIO, 0x166b, &mmDC_ABM1_HG_RESULT_17[0], sizeof(mmDC_ABM1_HG_RESULT_17)/sizeof(mmDC_ABM1_HG_RESULT_17[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_18", REG_MMIO, 0x166c, &mmDC_ABM1_HG_RESULT_18[0], sizeof(mmDC_ABM1_HG_RESULT_18)/sizeof(mmDC_ABM1_HG_RESULT_18[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_19", REG_MMIO, 0x166d, &mmDC_ABM1_HG_RESULT_19[0], sizeof(mmDC_ABM1_HG_RESULT_19)/sizeof(mmDC_ABM1_HG_RESULT_19[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_20", REG_MMIO, 0x166e, &mmDC_ABM1_HG_RESULT_20[0], sizeof(mmDC_ABM1_HG_RESULT_20)/sizeof(mmDC_ABM1_HG_RESULT_20[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_21", REG_MMIO, 0x166f, &mmDC_ABM1_HG_RESULT_21[0], sizeof(mmDC_ABM1_HG_RESULT_21)/sizeof(mmDC_ABM1_HG_RESULT_21[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_22", REG_MMIO, 0x1670, &mmDC_ABM1_HG_RESULT_22[0], sizeof(mmDC_ABM1_HG_RESULT_22)/sizeof(mmDC_ABM1_HG_RESULT_22[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_23", REG_MMIO, 0x1671, &mmDC_ABM1_HG_RESULT_23[0], sizeof(mmDC_ABM1_HG_RESULT_23)/sizeof(mmDC_ABM1_HG_RESULT_23[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_24", REG_MMIO, 0x1672, &mmDC_ABM1_HG_RESULT_24[0], sizeof(mmDC_ABM1_HG_RESULT_24)/sizeof(mmDC_ABM1_HG_RESULT_24[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5", REG_MMIO, 0x1673, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x1674, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2", REG_MMIO, 0x1675, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3", REG_MMIO, 0x1676, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4", REG_MMIO, 0x1677, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x1678, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2", REG_MMIO, 0x1679, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3", REG_MMIO, 0x167a, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4", REG_MMIO, 0x167b, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0]), 0, 0 },
+	{ "mmDC_ABM1_OVERSCAN_PIXEL_VALUE", REG_MMIO, 0x169b, &mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0], sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE)/sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0]), 0, 0 },
+	{ "mmDC_ABM1_BL_MASTER_LOCK", REG_MMIO, 0x169c, &mmDC_ABM1_BL_MASTER_LOCK[0], sizeof(mmDC_ABM1_BL_MASTER_LOCK)/sizeof(mmDC_ABM1_BL_MASTER_LOCK[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_INDEX", REG_MMIO, 0x169e, &mmABM_TEST_DEBUG_INDEX[0], sizeof(mmABM_TEST_DEBUG_INDEX)/sizeof(mmABM_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_DATA", REG_MMIO, 0x169f, &mmABM_TEST_DEBUG_DATA[0], sizeof(mmABM_TEST_DEBUG_DATA)/sizeof(mmABM_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDVO_ENABLE", REG_MMIO, 0x16a0, &mmDVO_ENABLE[0], sizeof(mmDVO_ENABLE)/sizeof(mmDVO_ENABLE[0]), 0, 0 },
+	{ "mmDVO_SOURCE_SELECT", REG_MMIO, 0x16a1, &mmDVO_SOURCE_SELECT[0], sizeof(mmDVO_SOURCE_SELECT)/sizeof(mmDVO_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDVO_OUTPUT", REG_MMIO, 0x16a2, &mmDVO_OUTPUT[0], sizeof(mmDVO_OUTPUT)/sizeof(mmDVO_OUTPUT[0]), 0, 0 },
+	{ "mmDVO_CONTROL", REG_MMIO, 0x16a3, &mmDVO_CONTROL[0], sizeof(mmDVO_CONTROL)/sizeof(mmDVO_CONTROL[0]), 0, 0 },
+	{ "mmDVO_CRC_EN", REG_MMIO, 0x16a4, &mmDVO_CRC_EN[0], sizeof(mmDVO_CRC_EN)/sizeof(mmDVO_CRC_EN[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_MASK", REG_MMIO, 0x16a5, &mmDVO_CRC2_SIG_MASK[0], sizeof(mmDVO_CRC2_SIG_MASK)/sizeof(mmDVO_CRC2_SIG_MASK[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_RESULT", REG_MMIO, 0x16a6, &mmDVO_CRC2_SIG_RESULT[0], sizeof(mmDVO_CRC2_SIG_RESULT)/sizeof(mmDVO_CRC2_SIG_RESULT[0]), 0, 0 },
+	{ "mmDVO_FIFO_ERROR_STATUS", REG_MMIO, 0x16a7, &mmDVO_FIFO_ERROR_STATUS[0], sizeof(mmDVO_FIFO_ERROR_STATUS)/sizeof(mmDVO_FIFO_ERROR_STATUS[0]), 0, 0 },
+	{ "mmDVO_TEST_DEBUG_INDEX", REG_MMIO, 0x16a8, &mmDVO_TEST_DEBUG_INDEX[0], sizeof(mmDVO_TEST_DEBUG_INDEX)/sizeof(mmDVO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDVO_TEST_DEBUG_DATA", REG_MMIO, 0x16a9, &mmDVO_TEST_DEBUG_DATA[0], sizeof(mmDVO_TEST_DEBUG_DATA)/sizeof(mmDVO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDAC_ENABLE", REG_MMIO, 0x16aa, &mmDAC_ENABLE[0], sizeof(mmDAC_ENABLE)/sizeof(mmDAC_ENABLE[0]), 0, 0 },
+	{ "mmDAC_SOURCE_SELECT", REG_MMIO, 0x16ab, &mmDAC_SOURCE_SELECT[0], sizeof(mmDAC_SOURCE_SELECT)/sizeof(mmDAC_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDAC_CRC_EN", REG_MMIO, 0x16ac, &mmDAC_CRC_EN[0], sizeof(mmDAC_CRC_EN)/sizeof(mmDAC_CRC_EN[0]), 0, 0 },
+	{ "mmDAC_CRC_CONTROL", REG_MMIO, 0x16ad, &mmDAC_CRC_CONTROL[0], sizeof(mmDAC_CRC_CONTROL)/sizeof(mmDAC_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB_MASK", REG_MMIO, 0x16ae, &mmDAC_CRC_SIG_RGB_MASK[0], sizeof(mmDAC_CRC_SIG_RGB_MASK)/sizeof(mmDAC_CRC_SIG_RGB_MASK[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL_MASK", REG_MMIO, 0x16af, &mmDAC_CRC_SIG_CONTROL_MASK[0], sizeof(mmDAC_CRC_SIG_CONTROL_MASK)/sizeof(mmDAC_CRC_SIG_CONTROL_MASK[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO_SOURCE", REG_MMIO, 0x16b, &mmDCCG_AUDIO_DTO_SOURCE[0], sizeof(mmDCCG_AUDIO_DTO_SOURCE)/sizeof(mmDCCG_AUDIO_DTO_SOURCE[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB", REG_MMIO, 0x16b0, &mmDAC_CRC_SIG_RGB[0], sizeof(mmDAC_CRC_SIG_RGB)/sizeof(mmDAC_CRC_SIG_RGB[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL", REG_MMIO, 0x16b1, &mmDAC_CRC_SIG_CONTROL[0], sizeof(mmDAC_CRC_SIG_CONTROL)/sizeof(mmDAC_CRC_SIG_CONTROL[0]), 0, 0 },
+	{ "mmDAC_SYNC_TRISTATE_CONTROL", REG_MMIO, 0x16b2, &mmDAC_SYNC_TRISTATE_CONTROL[0], sizeof(mmDAC_SYNC_TRISTATE_CONTROL)/sizeof(mmDAC_SYNC_TRISTATE_CONTROL[0]), 0, 0 },
+	{ "mmDAC_STEREOSYNC_SELECT", REG_MMIO, 0x16b3, &mmDAC_STEREOSYNC_SELECT[0], sizeof(mmDAC_STEREOSYNC_SELECT)/sizeof(mmDAC_STEREOSYNC_SELECT[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL", REG_MMIO, 0x16b4, &mmDAC_AUTODETECT_CONTROL[0], sizeof(mmDAC_AUTODETECT_CONTROL)/sizeof(mmDAC_AUTODETECT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL2", REG_MMIO, 0x16b5, &mmDAC_AUTODETECT_CONTROL2[0], sizeof(mmDAC_AUTODETECT_CONTROL2)/sizeof(mmDAC_AUTODETECT_CONTROL2[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL3", REG_MMIO, 0x16b6, &mmDAC_AUTODETECT_CONTROL3[0], sizeof(mmDAC_AUTODETECT_CONTROL3)/sizeof(mmDAC_AUTODETECT_CONTROL3[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_STATUS", REG_MMIO, 0x16b7, &mmDAC_AUTODETECT_STATUS[0], sizeof(mmDAC_AUTODETECT_STATUS)/sizeof(mmDAC_AUTODETECT_STATUS[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_INT_CONTROL", REG_MMIO, 0x16b8, &mmDAC_AUTODETECT_INT_CONTROL[0], sizeof(mmDAC_AUTODETECT_INT_CONTROL)/sizeof(mmDAC_AUTODETECT_INT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_FORCE_OUTPUT_CNTL", REG_MMIO, 0x16b9, &mmDAC_FORCE_OUTPUT_CNTL[0], sizeof(mmDAC_FORCE_OUTPUT_CNTL)/sizeof(mmDAC_FORCE_OUTPUT_CNTL[0]), 0, 0 },
+	{ "mmDAC_FORCE_DATA", REG_MMIO, 0x16ba, &mmDAC_FORCE_DATA[0], sizeof(mmDAC_FORCE_DATA)/sizeof(mmDAC_FORCE_DATA[0]), 0, 0 },
+	{ "mmDAC_POWERDOWN", REG_MMIO, 0x16bb, &mmDAC_POWERDOWN[0], sizeof(mmDAC_POWERDOWN)/sizeof(mmDAC_POWERDOWN[0]), 0, 0 },
+	{ "mmDAC_CONTROL", REG_MMIO, 0x16bc, &mmDAC_CONTROL[0], sizeof(mmDAC_CONTROL)/sizeof(mmDAC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_ENABLE", REG_MMIO, 0x16bd, &mmDAC_COMPARATOR_ENABLE[0], sizeof(mmDAC_COMPARATOR_ENABLE)/sizeof(mmDAC_COMPARATOR_ENABLE[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_OUTPUT", REG_MMIO, 0x16be, &mmDAC_COMPARATOR_OUTPUT[0], sizeof(mmDAC_COMPARATOR_OUTPUT)/sizeof(mmDAC_COMPARATOR_OUTPUT[0]), 0, 0 },
+	{ "mmDAC_PWR_CNTL", REG_MMIO, 0x16bf, &mmDAC_PWR_CNTL[0], sizeof(mmDAC_PWR_CNTL)/sizeof(mmDAC_PWR_CNTL[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_PHASE", REG_MMIO, 0x16c, &mmDCCG_AUDIO_DTO0_PHASE[0], sizeof(mmDCCG_AUDIO_DTO0_PHASE)/sizeof(mmDCCG_AUDIO_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDAC_DFT_CONFIG", REG_MMIO, 0x16c0, &mmDAC_DFT_CONFIG[0], sizeof(mmDAC_DFT_CONFIG)/sizeof(mmDAC_DFT_CONFIG[0]), 0, 0 },
+	{ "mmDAC_FIFO_STATUS", REG_MMIO, 0x16c1, &mmDAC_FIFO_STATUS[0], sizeof(mmDAC_FIFO_STATUS)/sizeof(mmDAC_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDAC_TEST_DEBUG_INDEX", REG_MMIO, 0x16c2, &mmDAC_TEST_DEBUG_INDEX[0], sizeof(mmDAC_TEST_DEBUG_INDEX)/sizeof(mmDAC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDAC_TEST_DEBUG_DATA", REG_MMIO, 0x16c3, &mmDAC_TEST_DEBUG_DATA[0], sizeof(mmDAC_TEST_DEBUG_DATA)/sizeof(mmDAC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK1_SEL", REG_MMIO, 0x16c4, &mmDCDEBUG_BUS_CLK1_SEL[0], sizeof(mmDCDEBUG_BUS_CLK1_SEL)/sizeof(mmDCDEBUG_BUS_CLK1_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK2_SEL", REG_MMIO, 0x16c5, &mmDCDEBUG_BUS_CLK2_SEL[0], sizeof(mmDCDEBUG_BUS_CLK2_SEL)/sizeof(mmDCDEBUG_BUS_CLK2_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK3_SEL", REG_MMIO, 0x16c6, &mmDCDEBUG_BUS_CLK3_SEL[0], sizeof(mmDCDEBUG_BUS_CLK3_SEL)/sizeof(mmDCDEBUG_BUS_CLK3_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK4_SEL", REG_MMIO, 0x16c7, &mmDCDEBUG_BUS_CLK4_SEL[0], sizeof(mmDCDEBUG_BUS_CLK4_SEL)/sizeof(mmDCDEBUG_BUS_CLK4_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK5_SEL", REG_MMIO, 0x16c8, &mmDCDEBUG_BUS_CLK5_SEL[0], sizeof(mmDCDEBUG_BUS_CLK5_SEL)/sizeof(mmDCDEBUG_BUS_CLK5_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_PIN_OVERRIDE", REG_MMIO, 0x16c9, &mmDCDEBUG_OUT_PIN_OVERRIDE[0], sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE)/sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_CNTL", REG_MMIO, 0x16ca, &mmDCDEBUG_OUT_CNTL[0], sizeof(mmDCDEBUG_OUT_CNTL)/sizeof(mmDCDEBUG_OUT_CNTL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_DATA", REG_MMIO, 0x16cb, &mmDCDEBUG_OUT_DATA[0], sizeof(mmDCDEBUG_OUT_DATA)/sizeof(mmDCDEBUG_OUT_DATA[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_MODULE", REG_MMIO, 0x16d, &mmDCCG_AUDIO_DTO0_MODULE[0], sizeof(mmDCCG_AUDIO_DTO0_MODULE)/sizeof(mmDCCG_AUDIO_DTO0_MODULE[0]), 0, 0 },
+	{ "mmDC_I2C_CONTROL", REG_MMIO, 0x16d4, &mmDC_I2C_CONTROL[0], sizeof(mmDC_I2C_CONTROL)/sizeof(mmDC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_ARBITRATION", REG_MMIO, 0x16d5, &mmDC_I2C_ARBITRATION[0], sizeof(mmDC_I2C_ARBITRATION)/sizeof(mmDC_I2C_ARBITRATION[0]), 0, 0 },
+	{ "mmDC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x16d6, &mmDC_I2C_INTERRUPT_CONTROL[0], sizeof(mmDC_I2C_INTERRUPT_CONTROL)/sizeof(mmDC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_SW_STATUS", REG_MMIO, 0x16d7, &mmDC_I2C_SW_STATUS[0], sizeof(mmDC_I2C_SW_STATUS)/sizeof(mmDC_I2C_SW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_HW_STATUS", REG_MMIO, 0x16d8, &mmDC_I2C_DDC1_HW_STATUS[0], sizeof(mmDC_I2C_DDC1_HW_STATUS)/sizeof(mmDC_I2C_DDC1_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_HW_STATUS", REG_MMIO, 0x16d9, &mmDC_I2C_DDC2_HW_STATUS[0], sizeof(mmDC_I2C_DDC2_HW_STATUS)/sizeof(mmDC_I2C_DDC2_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_HW_STATUS", REG_MMIO, 0x16da, &mmDC_I2C_DDC3_HW_STATUS[0], sizeof(mmDC_I2C_DDC3_HW_STATUS)/sizeof(mmDC_I2C_DDC3_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_HW_STATUS", REG_MMIO, 0x16db, &mmDC_I2C_DDC4_HW_STATUS[0], sizeof(mmDC_I2C_DDC4_HW_STATUS)/sizeof(mmDC_I2C_DDC4_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_HW_STATUS", REG_MMIO, 0x16dc, &mmDC_I2C_DDC5_HW_STATUS[0], sizeof(mmDC_I2C_DDC5_HW_STATUS)/sizeof(mmDC_I2C_DDC5_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_HW_STATUS", REG_MMIO, 0x16dd, &mmDC_I2C_DDC6_HW_STATUS[0], sizeof(mmDC_I2C_DDC6_HW_STATUS)/sizeof(mmDC_I2C_DDC6_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SPEED", REG_MMIO, 0x16de, &mmDC_I2C_DDC1_SPEED[0], sizeof(mmDC_I2C_DDC1_SPEED)/sizeof(mmDC_I2C_DDC1_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SETUP", REG_MMIO, 0x16df, &mmDC_I2C_DDC1_SETUP[0], sizeof(mmDC_I2C_DDC1_SETUP)/sizeof(mmDC_I2C_DDC1_SETUP[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_PHASE", REG_MMIO, 0x16e, &mmDCCG_AUDIO_DTO1_PHASE[0], sizeof(mmDCCG_AUDIO_DTO1_PHASE)/sizeof(mmDCCG_AUDIO_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SPEED", REG_MMIO, 0x16e0, &mmDC_I2C_DDC2_SPEED[0], sizeof(mmDC_I2C_DDC2_SPEED)/sizeof(mmDC_I2C_DDC2_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SETUP", REG_MMIO, 0x16e1, &mmDC_I2C_DDC2_SETUP[0], sizeof(mmDC_I2C_DDC2_SETUP)/sizeof(mmDC_I2C_DDC2_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SPEED", REG_MMIO, 0x16e2, &mmDC_I2C_DDC3_SPEED[0], sizeof(mmDC_I2C_DDC3_SPEED)/sizeof(mmDC_I2C_DDC3_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SETUP", REG_MMIO, 0x16e3, &mmDC_I2C_DDC3_SETUP[0], sizeof(mmDC_I2C_DDC3_SETUP)/sizeof(mmDC_I2C_DDC3_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SPEED", REG_MMIO, 0x16e4, &mmDC_I2C_DDC4_SPEED[0], sizeof(mmDC_I2C_DDC4_SPEED)/sizeof(mmDC_I2C_DDC4_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SETUP", REG_MMIO, 0x16e5, &mmDC_I2C_DDC4_SETUP[0], sizeof(mmDC_I2C_DDC4_SETUP)/sizeof(mmDC_I2C_DDC4_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SPEED", REG_MMIO, 0x16e6, &mmDC_I2C_DDC5_SPEED[0], sizeof(mmDC_I2C_DDC5_SPEED)/sizeof(mmDC_I2C_DDC5_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SETUP", REG_MMIO, 0x16e7, &mmDC_I2C_DDC5_SETUP[0], sizeof(mmDC_I2C_DDC5_SETUP)/sizeof(mmDC_I2C_DDC5_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SPEED", REG_MMIO, 0x16e8, &mmDC_I2C_DDC6_SPEED[0], sizeof(mmDC_I2C_DDC6_SPEED)/sizeof(mmDC_I2C_DDC6_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SETUP", REG_MMIO, 0x16e9, &mmDC_I2C_DDC6_SETUP[0], sizeof(mmDC_I2C_DDC6_SETUP)/sizeof(mmDC_I2C_DDC6_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION0", REG_MMIO, 0x16ea, &mmDC_I2C_TRANSACTION0[0], sizeof(mmDC_I2C_TRANSACTION0)/sizeof(mmDC_I2C_TRANSACTION0[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION1", REG_MMIO, 0x16eb, &mmDC_I2C_TRANSACTION1[0], sizeof(mmDC_I2C_TRANSACTION1)/sizeof(mmDC_I2C_TRANSACTION1[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION2", REG_MMIO, 0x16ec, &mmDC_I2C_TRANSACTION2[0], sizeof(mmDC_I2C_TRANSACTION2)/sizeof(mmDC_I2C_TRANSACTION2[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION3", REG_MMIO, 0x16ed, &mmDC_I2C_TRANSACTION3[0], sizeof(mmDC_I2C_TRANSACTION3)/sizeof(mmDC_I2C_TRANSACTION3[0]), 0, 0 },
+	{ "mmDC_I2C_DATA", REG_MMIO, 0x16ee, &mmDC_I2C_DATA[0], sizeof(mmDC_I2C_DATA)/sizeof(mmDC_I2C_DATA[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_HW_STATUS", REG_MMIO, 0x16ef, &mmDC_I2C_DDCVGA_HW_STATUS[0], sizeof(mmDC_I2C_DDCVGA_HW_STATUS)/sizeof(mmDC_I2C_DDCVGA_HW_STATUS[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_MODULE", REG_MMIO, 0x16f, &mmDCCG_AUDIO_DTO1_MODULE[0], sizeof(mmDCCG_AUDIO_DTO1_MODULE)/sizeof(mmDCCG_AUDIO_DTO1_MODULE[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SPEED", REG_MMIO, 0x16f0, &mmDC_I2C_DDCVGA_SPEED[0], sizeof(mmDC_I2C_DDCVGA_SPEED)/sizeof(mmDC_I2C_DDCVGA_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SETUP", REG_MMIO, 0x16f1, &mmDC_I2C_DDCVGA_SETUP[0], sizeof(mmDC_I2C_DDCVGA_SETUP)/sizeof(mmDC_I2C_DDCVGA_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_EDID_DETECT_CTRL", REG_MMIO, 0x16f2, &mmDC_I2C_EDID_DETECT_CTRL[0], sizeof(mmDC_I2C_EDID_DETECT_CTRL)/sizeof(mmDC_I2C_EDID_DETECT_CTRL[0]), 0, 0 },
+	{ "mmDC_I2C_READ_REQUEST_INTERRUPT", REG_MMIO, 0x16f3, &mmDC_I2C_READ_REQUEST_INTERRUPT[0], sizeof(mmDC_I2C_READ_REQUEST_INTERRUPT)/sizeof(mmDC_I2C_READ_REQUEST_INTERRUPT[0]), 0, 0 },
+	{ "mmGENERIC_I2C_CONTROL", REG_MMIO, 0x16f4, &mmGENERIC_I2C_CONTROL[0], sizeof(mmGENERIC_I2C_CONTROL)/sizeof(mmGENERIC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x16f5, &mmGENERIC_I2C_INTERRUPT_CONTROL[0], sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL)/sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_STATUS", REG_MMIO, 0x16f6, &mmGENERIC_I2C_STATUS[0], sizeof(mmGENERIC_I2C_STATUS)/sizeof(mmGENERIC_I2C_STATUS[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SPEED", REG_MMIO, 0x16f7, &mmGENERIC_I2C_SPEED[0], sizeof(mmGENERIC_I2C_SPEED)/sizeof(mmGENERIC_I2C_SPEED[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SETUP", REG_MMIO, 0x16f8, &mmGENERIC_I2C_SETUP[0], sizeof(mmGENERIC_I2C_SETUP)/sizeof(mmGENERIC_I2C_SETUP[0]), 0, 0 },
+	{ "mmGENERIC_I2C_TRANSACTION", REG_MMIO, 0x16f9, &mmGENERIC_I2C_TRANSACTION[0], sizeof(mmGENERIC_I2C_TRANSACTION)/sizeof(mmGENERIC_I2C_TRANSACTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_DATA", REG_MMIO, 0x16fa, &mmGENERIC_I2C_DATA[0], sizeof(mmGENERIC_I2C_DATA)/sizeof(mmGENERIC_I2C_DATA[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_SELECTION", REG_MMIO, 0x16fb, &mmGENERIC_I2C_PIN_SELECTION[0], sizeof(mmGENERIC_I2C_PIN_SELECTION)/sizeof(mmGENERIC_I2C_PIN_SELECTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_DEBUG", REG_MMIO, 0x16fc, &mmGENERIC_I2C_PIN_DEBUG[0], sizeof(mmGENERIC_I2C_PIN_DEBUG)/sizeof(mmGENERIC_I2C_PIN_DEBUG[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_H", REG_SMC, 0x17, &ixDP_AUX_DEBUG_H[0], sizeof(ixDP_AUX_DEBUG_H)/sizeof(ixDP_AUX_DEBUG_H[0]), 0, 0 },
+	{ "ixDCIO_DEBUG17", REG_SMC, 0x17, &ixDCIO_DEBUG17[0], sizeof(ixDCIO_DEBUG17)/sizeof(ixDCIO_DEBUG17[0]), 0, 0 },
+	{ "mmRIRB_STATUS", REG_MMIO, 0x17, &mmRIRB_STATUS[0], sizeof(mmRIRB_STATUS)/sizeof(mmRIRB_STATUS[0]), 0, 0 },
+	{ "mmRIRB_SIZE", REG_MMIO, 0x17, &mmRIRB_SIZE[0], sizeof(mmRIRB_SIZE)/sizeof(mmRIRB_SIZE[0]), 0, 0 },
+	{ "ixCRT17", REG_SMC, 0x17, &ixCRT17[0], sizeof(ixCRT17)/sizeof(ixCRT17[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFCOUNTER_CNTL", REG_MMIO, 0x170, NULL, 0, 0, 0 },
+	{ "mmPERFCOUNTER_CNTL", REG_MMIO, 0x170, &mmPERFCOUNTER_CNTL[0], sizeof(mmPERFCOUNTER_CNTL)/sizeof(mmPERFCOUNTER_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1700, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1700, &mmPLL_MACRO_CNTL_RESERVED0[0], sizeof(mmPLL_MACRO_CNTL_RESERVED0)/sizeof(mmPLL_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_REF_DIV", REG_MMIO, 0x1700, NULL, 0, 0, 0 },
+	{ "mmPLL_REF_DIV", REG_MMIO, 0x1700, &mmPLL_REF_DIV[0], sizeof(mmPLL_REF_DIV)/sizeof(mmPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1701, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1701, &mmPLL_MACRO_CNTL_RESERVED1[0], sizeof(mmPLL_MACRO_CNTL_RESERVED1)/sizeof(mmPLL_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_FB_DIV", REG_MMIO, 0x1701, NULL, 0, 0, 0 },
+	{ "mmPLL_FB_DIV", REG_MMIO, 0x1701, &mmPLL_FB_DIV[0], sizeof(mmPLL_FB_DIV)/sizeof(mmPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1702, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1702, &mmPLL_MACRO_CNTL_RESERVED2[0], sizeof(mmPLL_MACRO_CNTL_RESERVED2)/sizeof(mmPLL_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_POST_DIV", REG_MMIO, 0x1702, NULL, 0, 0, 0 },
+	{ "mmPLL_POST_DIV", REG_MMIO, 0x1702, &mmPLL_POST_DIV[0], sizeof(mmPLL_POST_DIV)/sizeof(mmPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1703, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1703, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1703, &mmPLL_MACRO_CNTL_RESERVED3[0], sizeof(mmPLL_MACRO_CNTL_RESERVED3)/sizeof(mmPLL_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmPLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1703, &mmPLL_SS_AMOUNT_DSFRAC[0], sizeof(mmPLL_SS_AMOUNT_DSFRAC)/sizeof(mmPLL_SS_AMOUNT_DSFRAC[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1704, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1704, &mmPLL_MACRO_CNTL_RESERVED4[0], sizeof(mmPLL_MACRO_CNTL_RESERVED4)/sizeof(mmPLL_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_SS_CNTL", REG_MMIO, 0x1704, NULL, 0, 0, 0 },
+	{ "mmPLL_SS_CNTL", REG_MMIO, 0x1704, &mmPLL_SS_CNTL[0], sizeof(mmPLL_SS_CNTL)/sizeof(mmPLL_SS_CNTL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_SMC, 0x1705, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1705, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1705, &mmPLL_MACRO_CNTL_RESERVED5[0], sizeof(mmPLL_MACRO_CNTL_RESERVED5)/sizeof(mmPLL_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_DS_CNTL", REG_MMIO, 0x1705, NULL, 0, 0, 0 },
+	{ "mmPLL_DS_CNTL", REG_MMIO, 0x1705, &mmPLL_DS_CNTL[0], sizeof(mmPLL_DS_CNTL)/sizeof(mmPLL_DS_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1706, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_IDCLK_CNTL", REG_MMIO, 0x1706, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1706, &mmPLL_MACRO_CNTL_RESERVED6[0], sizeof(mmPLL_MACRO_CNTL_RESERVED6)/sizeof(mmPLL_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmPLL_IDCLK_CNTL", REG_MMIO, 0x1706, &mmPLL_IDCLK_CNTL[0], sizeof(mmPLL_IDCLK_CNTL)/sizeof(mmPLL_IDCLK_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1707, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1707, &mmPLL_MACRO_CNTL_RESERVED7[0], sizeof(mmPLL_MACRO_CNTL_RESERVED7)/sizeof(mmPLL_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_CNTL", REG_MMIO, 0x1707, NULL, 0, 0, 0 },
+	{ "mmPLL_CNTL", REG_MMIO, 0x1707, &mmPLL_CNTL[0], sizeof(mmPLL_CNTL)/sizeof(mmPLL_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1708, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1708, &mmPLL_MACRO_CNTL_RESERVED8[0], sizeof(mmPLL_MACRO_CNTL_RESERVED8)/sizeof(mmPLL_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_ANALOG", REG_MMIO, 0x1708, NULL, 0, 0, 0 },
+	{ "mmPLL_ANALOG", REG_MMIO, 0x1708, &mmPLL_ANALOG[0], sizeof(mmPLL_ANALOG)/sizeof(mmPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1709, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1709, &mmPLL_MACRO_CNTL_RESERVED9[0], sizeof(mmPLL_MACRO_CNTL_RESERVED9)/sizeof(mmPLL_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmPLL_VREG_CNTL", REG_MMIO, 0x1709, &mmPLL_VREG_CNTL[0], sizeof(mmPLL_VREG_CNTL)/sizeof(mmPLL_VREG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x170a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x170a, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x170a, &mmPLL_MACRO_CNTL_RESERVED10[0], sizeof(mmPLL_MACRO_CNTL_RESERVED10)/sizeof(mmPLL_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmPLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x170a, &mmPLL_UNLOCK_DETECT_CNTL[0], sizeof(mmPLL_UNLOCK_DETECT_CNTL)/sizeof(mmPLL_UNLOCK_DETECT_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x170b, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x170b, &mmPLL_MACRO_CNTL_RESERVED11[0], sizeof(mmPLL_MACRO_CNTL_RESERVED11)/sizeof(mmPLL_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmPLL_DEBUG_CNTL", REG_MMIO, 0x170b, &mmPLL_DEBUG_CNTL[0], sizeof(mmPLL_DEBUG_CNTL)/sizeof(mmPLL_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x170c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_UPDATE_LOCK", REG_MMIO, 0x170c, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x170c, &mmPLL_MACRO_CNTL_RESERVED12[0], sizeof(mmPLL_MACRO_CNTL_RESERVED12)/sizeof(mmPLL_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmPLL_UPDATE_LOCK", REG_MMIO, 0x170c, &mmPLL_UPDATE_LOCK[0], sizeof(mmPLL_UPDATE_LOCK)/sizeof(mmPLL_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x170d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_UPDATE_CNTL", REG_MMIO, 0x170d, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x170d, &mmPLL_MACRO_CNTL_RESERVED13[0], sizeof(mmPLL_MACRO_CNTL_RESERVED13)/sizeof(mmPLL_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmPLL_UPDATE_CNTL", REG_MMIO, 0x170d, &mmPLL_UPDATE_CNTL[0], sizeof(mmPLL_UPDATE_CNTL)/sizeof(mmPLL_UPDATE_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x170e, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x170e, &mmPLL_MACRO_CNTL_RESERVED14[0], sizeof(mmPLL_MACRO_CNTL_RESERVED14)/sizeof(mmPLL_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x170f, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x170f, &mmPLL_MACRO_CNTL_RESERVED15[0], sizeof(mmPLL_MACRO_CNTL_RESERVED15)/sizeof(mmPLL_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFCOUNTER_STATE", REG_MMIO, 0x171, NULL, 0, 0, 0 },
+	{ "mmPERFCOUNTER_STATE", REG_MMIO, 0x171, &mmPERFCOUNTER_STATE[0], sizeof(mmPERFCOUNTER_STATE)/sizeof(mmPERFCOUNTER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1710, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1710, &mmPLL_MACRO_CNTL_RESERVED16[0], sizeof(mmPLL_MACRO_CNTL_RESERVED16)/sizeof(mmPLL_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_XOR_LOCK", REG_MMIO, 0x1710, NULL, 0, 0, 0 },
+	{ "mmPLL_XOR_LOCK", REG_MMIO, 0x1710, &mmPLL_XOR_LOCK[0], sizeof(mmPLL_XOR_LOCK)/sizeof(mmPLL_XOR_LOCK[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1711, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PLL_ANALOG_CNTL", REG_MMIO, 0x1711, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1711, &mmPLL_MACRO_CNTL_RESERVED17[0], sizeof(mmPLL_MACRO_CNTL_RESERVED17)/sizeof(mmPLL_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmPLL_ANALOG_CNTL", REG_MMIO, 0x1711, &mmPLL_ANALOG_CNTL[0], sizeof(mmPLL_ANALOG_CNTL)/sizeof(mmPLL_ANALOG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1712, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA25_PPLL_REF_DIV", REG_MMIO, 0x1712, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1712, &mmPLL_MACRO_CNTL_RESERVED18[0], sizeof(mmPLL_MACRO_CNTL_RESERVED18)/sizeof(mmPLL_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmVGA25_PPLL_REF_DIV", REG_MMIO, 0x1712, &mmVGA25_PPLL_REF_DIV[0], sizeof(mmVGA25_PPLL_REF_DIV)/sizeof(mmVGA25_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1713, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA28_PPLL_REF_DIV", REG_MMIO, 0x1713, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1713, &mmPLL_MACRO_CNTL_RESERVED19[0], sizeof(mmPLL_MACRO_CNTL_RESERVED19)/sizeof(mmPLL_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmVGA28_PPLL_REF_DIV", REG_MMIO, 0x1713, &mmVGA28_PPLL_REF_DIV[0], sizeof(mmVGA28_PPLL_REF_DIV)/sizeof(mmVGA28_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1714, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA41_PPLL_REF_DIV", REG_MMIO, 0x1714, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1714, &mmPLL_MACRO_CNTL_RESERVED20[0], sizeof(mmPLL_MACRO_CNTL_RESERVED20)/sizeof(mmPLL_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmVGA41_PPLL_REF_DIV", REG_MMIO, 0x1714, &mmVGA41_PPLL_REF_DIV[0], sizeof(mmVGA41_PPLL_REF_DIV)/sizeof(mmVGA41_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1715, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA25_PPLL_FB_DIV", REG_MMIO, 0x1715, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1715, &mmPLL_MACRO_CNTL_RESERVED21[0], sizeof(mmPLL_MACRO_CNTL_RESERVED21)/sizeof(mmPLL_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmVGA25_PPLL_FB_DIV", REG_MMIO, 0x1715, &mmVGA25_PPLL_FB_DIV[0], sizeof(mmVGA25_PPLL_FB_DIV)/sizeof(mmVGA25_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1716, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA28_PPLL_FB_DIV", REG_MMIO, 0x1716, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1716, &mmPLL_MACRO_CNTL_RESERVED22[0], sizeof(mmPLL_MACRO_CNTL_RESERVED22)/sizeof(mmPLL_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmVGA28_PPLL_FB_DIV", REG_MMIO, 0x1716, &mmVGA28_PPLL_FB_DIV[0], sizeof(mmVGA28_PPLL_FB_DIV)/sizeof(mmVGA28_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1717, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA41_PPLL_FB_DIV", REG_MMIO, 0x1717, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1717, &mmPLL_MACRO_CNTL_RESERVED23[0], sizeof(mmPLL_MACRO_CNTL_RESERVED23)/sizeof(mmPLL_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmVGA41_PPLL_FB_DIV", REG_MMIO, 0x1717, &mmVGA41_PPLL_FB_DIV[0], sizeof(mmVGA41_PPLL_FB_DIV)/sizeof(mmVGA41_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1718, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA25_PPLL_POST_DIV", REG_MMIO, 0x1718, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1718, &mmPLL_MACRO_CNTL_RESERVED24[0], sizeof(mmPLL_MACRO_CNTL_RESERVED24)/sizeof(mmPLL_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmVGA25_PPLL_POST_DIV", REG_MMIO, 0x1718, &mmVGA25_PPLL_POST_DIV[0], sizeof(mmVGA25_PPLL_POST_DIV)/sizeof(mmVGA25_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1719, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA28_PPLL_POST_DIV", REG_MMIO, 0x1719, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1719, &mmPLL_MACRO_CNTL_RESERVED25[0], sizeof(mmPLL_MACRO_CNTL_RESERVED25)/sizeof(mmPLL_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmVGA28_PPLL_POST_DIV", REG_MMIO, 0x1719, &mmVGA28_PPLL_POST_DIV[0], sizeof(mmVGA28_PPLL_POST_DIV)/sizeof(mmVGA28_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x171a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA41_PPLL_POST_DIV", REG_MMIO, 0x171a, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x171a, &mmPLL_MACRO_CNTL_RESERVED26[0], sizeof(mmPLL_MACRO_CNTL_RESERVED26)/sizeof(mmPLL_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmVGA41_PPLL_POST_DIV", REG_MMIO, 0x171a, &mmVGA41_PPLL_POST_DIV[0], sizeof(mmVGA41_PPLL_POST_DIV)/sizeof(mmVGA41_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x171b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA25_PPLL_ANALOG", REG_MMIO, 0x171b, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x171b, &mmPLL_MACRO_CNTL_RESERVED27[0], sizeof(mmPLL_MACRO_CNTL_RESERVED27)/sizeof(mmPLL_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmVGA25_PPLL_ANALOG", REG_MMIO, 0x171b, &mmVGA25_PPLL_ANALOG[0], sizeof(mmVGA25_PPLL_ANALOG)/sizeof(mmVGA25_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x171c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA28_PPLL_ANALOG", REG_MMIO, 0x171c, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x171c, &mmPLL_MACRO_CNTL_RESERVED28[0], sizeof(mmPLL_MACRO_CNTL_RESERVED28)/sizeof(mmPLL_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmVGA28_PPLL_ANALOG", REG_MMIO, 0x171c, &mmVGA28_PPLL_ANALOG[0], sizeof(mmVGA28_PPLL_ANALOG)/sizeof(mmVGA28_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x171d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_VGA41_PPLL_ANALOG", REG_MMIO, 0x171d, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x171d, &mmPLL_MACRO_CNTL_RESERVED29[0], sizeof(mmPLL_MACRO_CNTL_RESERVED29)/sizeof(mmPLL_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmVGA41_PPLL_ANALOG", REG_MMIO, 0x171d, &mmVGA41_PPLL_ANALOG[0], sizeof(mmVGA41_PPLL_ANALOG)/sizeof(mmVGA41_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x171e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_DISPPLL_BG_CNTL", REG_MMIO, 0x171e, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x171e, &mmPLL_MACRO_CNTL_RESERVED30[0], sizeof(mmPLL_MACRO_CNTL_RESERVED30)/sizeof(mmPLL_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDISPPLL_BG_CNTL", REG_MMIO, 0x171e, &mmDISPPLL_BG_CNTL[0], sizeof(mmDISPPLL_BG_CNTL)/sizeof(mmDISPPLL_BG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x171f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x171f, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x171f, &mmPLL_MACRO_CNTL_RESERVED31[0], sizeof(mmPLL_MACRO_CNTL_RESERVED31)/sizeof(mmPLL_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmPPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x171f, &mmPPLL_DIV_UPDATE_DEBUG[0], sizeof(mmPPLL_DIV_UPDATE_DEBUG)/sizeof(mmPPLL_DIV_UPDATE_DEBUG[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x172, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CVALUE_INT_MISC", REG_MMIO, 0x172, &mmPERFMON_CVALUE_INT_MISC[0], sizeof(mmPERFMON_CVALUE_INT_MISC)/sizeof(mmPERFMON_CVALUE_INT_MISC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_SMC, 0x1720, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1720, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_STATUS_DEBUG", REG_MMIO, 0x1720, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1720, &mmPLL_MACRO_CNTL_RESERVED32[0], sizeof(mmPLL_MACRO_CNTL_RESERVED32)/sizeof(mmPLL_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmPPLL_STATUS_DEBUG", REG_MMIO, 0x1720, &mmPPLL_STATUS_DEBUG[0], sizeof(mmPPLL_STATUS_DEBUG)/sizeof(mmPPLL_STATUS_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2", REG_SMC, 0x1721, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1721, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1721, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1721, &mmPLL_MACRO_CNTL_RESERVED33[0], sizeof(mmPLL_MACRO_CNTL_RESERVED33)/sizeof(mmPLL_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmPPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1721, &mmPPLL_DEBUG_MUX_CNTL[0], sizeof(mmPPLL_DEBUG_MUX_CNTL)/sizeof(mmPPLL_DEBUG_MUX_CNTL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3", REG_SMC, 0x1722, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1722, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1722, &mmPLL_MACRO_CNTL_RESERVED34[0], sizeof(mmPLL_MACRO_CNTL_RESERVED34)/sizeof(mmPLL_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_SPARE0", REG_MMIO, 0x1722, NULL, 0, 0, 0 },
+	{ "mmPPLL_SPARE0", REG_MMIO, 0x1722, &mmPPLL_SPARE0[0], sizeof(mmPPLL_SPARE0)/sizeof(mmPPLL_SPARE0[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4", REG_SMC, 0x1723, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1723, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1723, &mmPLL_MACRO_CNTL_RESERVED35[0], sizeof(mmPLL_MACRO_CNTL_RESERVED35)/sizeof(mmPLL_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmBPHYC_PLL0_PPLL_SPARE1", REG_MMIO, 0x1723, NULL, 0, 0, 0 },
+	{ "mmPPLL_SPARE1", REG_MMIO, 0x1723, &mmPPLL_SPARE1[0], sizeof(mmPPLL_SPARE1)/sizeof(mmPPLL_SPARE1[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1724, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1724, &mmPLL_MACRO_CNTL_RESERVED36[0], sizeof(mmPLL_MACRO_CNTL_RESERVED36)/sizeof(mmPLL_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1725, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1725, &mmPLL_MACRO_CNTL_RESERVED37[0], sizeof(mmPLL_MACRO_CNTL_RESERVED37)/sizeof(mmPLL_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1726, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1726, &mmPLL_MACRO_CNTL_RESERVED38[0], sizeof(mmPLL_MACRO_CNTL_RESERVED38)/sizeof(mmPLL_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1727, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1727, &mmPLL_MACRO_CNTL_RESERVED39[0], sizeof(mmPLL_MACRO_CNTL_RESERVED39)/sizeof(mmPLL_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1728, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1728, &mmPLL_MACRO_CNTL_RESERVED40[0], sizeof(mmPLL_MACRO_CNTL_RESERVED40)/sizeof(mmPLL_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1729, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1729, &mmPLL_MACRO_CNTL_RESERVED41[0], sizeof(mmPLL_MACRO_CNTL_RESERVED41)/sizeof(mmPLL_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x172a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_REF_DIV", REG_MMIO, 0x172a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x172b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_FB_DIV", REG_MMIO, 0x172b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x172c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_POST_DIV", REG_MMIO, 0x172c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x172d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x172d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x172e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_SS_CNTL", REG_MMIO, 0x172e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x172f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_DS_CNTL", REG_MMIO, 0x172f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CNTL", REG_MMIO, 0x173, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CNTL", REG_MMIO, 0x173, &mmPERFMON_CNTL[0], sizeof(mmPERFMON_CNTL)/sizeof(mmPERFMON_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1730, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_IDCLK_CNTL", REG_MMIO, 0x1730, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1731, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_CNTL", REG_MMIO, 0x1731, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1732, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_ANALOG", REG_MMIO, 0x1732, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1733, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_VREG_CNTL", REG_MMIO, 0x1733, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x1734, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x1734, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x1735, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_DEBUG_CNTL", REG_MMIO, 0x1735, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x1736, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_UPDATE_LOCK", REG_MMIO, 0x1736, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x1737, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_UPDATE_CNTL", REG_MMIO, 0x1737, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x1738, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x1739, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x173a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_XOR_LOCK", REG_MMIO, 0x173a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x173b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PLL_ANALOG_CNTL", REG_MMIO, 0x173b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x173c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA25_PPLL_REF_DIV", REG_MMIO, 0x173c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x173d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA28_PPLL_REF_DIV", REG_MMIO, 0x173d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x173e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA41_PPLL_REF_DIV", REG_MMIO, 0x173e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x173f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA25_PPLL_FB_DIV", REG_MMIO, 0x173f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CVALUE_LOW", REG_MMIO, 0x174, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CVALUE_LOW", REG_MMIO, 0x174, &mmPERFMON_CVALUE_LOW[0], sizeof(mmPERFMON_CVALUE_LOW)/sizeof(mmPERFMON_CVALUE_LOW[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1740, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA28_PPLL_FB_DIV", REG_MMIO, 0x1740, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1741, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA41_PPLL_FB_DIV", REG_MMIO, 0x1741, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1742, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA25_PPLL_POST_DIV", REG_MMIO, 0x1742, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1743, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA28_PPLL_POST_DIV", REG_MMIO, 0x1743, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x1744, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA41_PPLL_POST_DIV", REG_MMIO, 0x1744, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x1745, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA25_PPLL_ANALOG", REG_MMIO, 0x1745, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x1746, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA28_PPLL_ANALOG", REG_MMIO, 0x1746, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x1747, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_VGA41_PPLL_ANALOG", REG_MMIO, 0x1747, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x1748, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_DISPPLL_BG_CNTL", REG_MMIO, 0x1748, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x1749, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x1749, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x174a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_STATUS_DEBUG", REG_MMIO, 0x174a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x174b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x174b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x174c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_SPARE0", REG_MMIO, 0x174c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x174d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL1_PPLL_SPARE1", REG_MMIO, 0x174d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x174e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x174f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_HI", REG_MMIO, 0x175, NULL, 0, 0, 0 },
+	{ "mmPERFMON_HI", REG_MMIO, 0x175, &mmPERFMON_HI[0], sizeof(mmPERFMON_HI)/sizeof(mmPERFMON_HI[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1750, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1751, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1752, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1753, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1754, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_REF_DIV", REG_MMIO, 0x1754, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1755, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_FB_DIV", REG_MMIO, 0x1755, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1756, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_POST_DIV", REG_MMIO, 0x1756, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1757, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1757, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1758, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_SS_CNTL", REG_MMIO, 0x1758, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1759, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_DS_CNTL", REG_MMIO, 0x1759, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x175a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_IDCLK_CNTL", REG_MMIO, 0x175a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x175b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_CNTL", REG_MMIO, 0x175b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x175c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_ANALOG", REG_MMIO, 0x175c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x175d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_VREG_CNTL", REG_MMIO, 0x175d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x175e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x175e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x175f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_DEBUG_CNTL", REG_MMIO, 0x175f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_LOW", REG_MMIO, 0x176, NULL, 0, 0, 0 },
+	{ "mmPERFMON_LOW", REG_MMIO, 0x176, &mmPERFMON_LOW[0], sizeof(mmPERFMON_LOW)/sizeof(mmPERFMON_LOW[0]), 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x1760, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_UPDATE_LOCK", REG_MMIO, 0x1760, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x1761, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_UPDATE_CNTL", REG_MMIO, 0x1761, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x1762, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x1763, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1764, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_XOR_LOCK", REG_MMIO, 0x1764, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1765, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PLL_ANALOG_CNTL", REG_MMIO, 0x1765, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1766, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA25_PPLL_REF_DIV", REG_MMIO, 0x1766, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1767, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA28_PPLL_REF_DIV", REG_MMIO, 0x1767, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1768, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA41_PPLL_REF_DIV", REG_MMIO, 0x1768, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1769, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA25_PPLL_FB_DIV", REG_MMIO, 0x1769, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x176a, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA28_PPLL_FB_DIV", REG_MMIO, 0x176a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x176b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA41_PPLL_FB_DIV", REG_MMIO, 0x176b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x176c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA25_PPLL_POST_DIV", REG_MMIO, 0x176c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x176d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA28_PPLL_POST_DIV", REG_MMIO, 0x176d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x176e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA41_PPLL_POST_DIV", REG_MMIO, 0x176e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x176f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA25_PPLL_ANALOG", REG_MMIO, 0x176f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x177, NULL, 0, 0, 0 },
+	{ "mmPERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x177, &mmPERFMON_TEST_DEBUG_INDEX[0], sizeof(mmPERFMON_TEST_DEBUG_INDEX)/sizeof(mmPERFMON_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_SMC, 0x1770, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x1770, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA28_PPLL_ANALOG", REG_MMIO, 0x1770, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x1771, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_VGA41_PPLL_ANALOG", REG_MMIO, 0x1771, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x1772, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_DISPPLL_BG_CNTL", REG_MMIO, 0x1772, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x1773, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x1773, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1774, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_STATUS_DEBUG", REG_MMIO, 0x1774, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1775, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1775, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1776, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_SPARE0", REG_MMIO, 0x1776, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1777, NULL, 0, 0, 0 },
+	{ "mmBPHYC_PLL2_PPLL_SPARE1", REG_MMIO, 0x1777, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1778, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1779, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x177a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x177b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x177c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x177d, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x178, NULL, 0, 0, 0 },
+	{ "mmPERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x178, &mmPERFMON_TEST_DEBUG_DATA[0], sizeof(mmPERFMON_TEST_DEBUG_DATA)/sizeof(mmPERFMON_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZF0STREAM0_AZALIA_STREAM_INDEX", REG_MMIO, 0x1780, NULL, 0, 0, 0 },
+	{ "mmAZALIA_STREAM_INDEX", REG_MMIO, 0x1780, &mmAZALIA_STREAM_INDEX[0], sizeof(mmAZALIA_STREAM_INDEX)/sizeof(mmAZALIA_STREAM_INDEX[0]), 0, 0 },
+	{ "mmAZF0STREAM0_AZALIA_STREAM_DATA", REG_MMIO, 0x1781, NULL, 0, 0, 0 },
+	{ "mmAZALIA_STREAM_DATA", REG_MMIO, 0x1781, &mmAZALIA_STREAM_DATA[0], sizeof(mmAZALIA_STREAM_DATA)/sizeof(mmAZALIA_STREAM_DATA[0]), 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_INDEX", REG_MMIO, 0x1782, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_DATA", REG_MMIO, 0x1783, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_INDEX", REG_MMIO, 0x1784, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_DATA", REG_MMIO, 0x1785, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_INDEX", REG_MMIO, 0x1786, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_DATA", REG_MMIO, 0x1787, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_INDEX", REG_MMIO, 0x1788, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_DATA", REG_MMIO, 0x1789, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_INDEX", REG_MMIO, 0x178a, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_DATA", REG_MMIO, 0x178b, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM6_AZALIA_STREAM_INDEX", REG_MMIO, 0x178c, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM6_AZALIA_STREAM_DATA", REG_MMIO, 0x178d, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM7_AZALIA_STREAM_INDEX", REG_MMIO, 0x178e, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM7_AZALIA_STREAM_DATA", REG_MMIO, 0x178f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CNTL2", REG_MMIO, 0x17a, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CNTL2", REG_MMIO, 0x17a, &mmPERFMON_CNTL2[0], sizeof(mmPERFMON_CNTL2)/sizeof(mmPERFMON_CNTL2[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17a8, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17a8, &mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17a9, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17a9, &mmAZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17ac, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17ad, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b0, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b1, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b4, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b5, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b8, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b9, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17bc, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17bd, NULL, 0, 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_INDEX", REG_MMIO, 0x17c, &mmDCCG_TEST_DEBUG_INDEX[0], sizeof(mmDCCG_TEST_DEBUG_INDEX)/sizeof(mmDCCG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17c0, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17c1, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17c4, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17c5, NULL, 0, 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_DATA", REG_MMIO, 0x17d, &mmDCCG_TEST_DEBUG_DATA[0], sizeof(mmDCCG_TEST_DEBUG_DATA)/sizeof(mmDCCG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCCG_TEST_CLK_SEL", REG_MMIO, 0x17e, &mmDCCG_TEST_CLK_SEL[0], sizeof(mmDCCG_TEST_CLK_SEL)/sizeof(mmDCCG_TEST_CLK_SEL[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_CLOCK_GATING", REG_MMIO, 0x17e4, &mmAZALIA_CONTROLLER_CLOCK_GATING[0], sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING)/sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO", REG_MMIO, 0x17e5, &mmAZALIA_AUDIO_DTO[0], sizeof(mmAZALIA_AUDIO_DTO)/sizeof(mmAZALIA_AUDIO_DTO[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO_CONTROL", REG_MMIO, 0x17e6, &mmAZALIA_AUDIO_DTO_CONTROL[0], sizeof(mmAZALIA_AUDIO_DTO_CONTROL)/sizeof(mmAZALIA_AUDIO_DTO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_SCLK_CONTROL", REG_MMIO, 0x17e7, &mmAZALIA_SCLK_CONTROL[0], sizeof(mmAZALIA_SCLK_CONTROL)/sizeof(mmAZALIA_SCLK_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_UNDERFLOW_FILLER_SAMPLE", REG_MMIO, 0x17e8, &mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0], sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE)/sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0]), 0, 0 },
+	{ "mmAZALIA_DATA_DMA_CONTROL", REG_MMIO, 0x17e9, &mmAZALIA_DATA_DMA_CONTROL[0], sizeof(mmAZALIA_DATA_DMA_CONTROL)/sizeof(mmAZALIA_DATA_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_BDL_DMA_CONTROL", REG_MMIO, 0x17ea, &mmAZALIA_BDL_DMA_CONTROL[0], sizeof(mmAZALIA_BDL_DMA_CONTROL)/sizeof(mmAZALIA_BDL_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_RIRB_AND_DP_CONTROL", REG_MMIO, 0x17eb, &mmAZALIA_RIRB_AND_DP_CONTROL[0], sizeof(mmAZALIA_RIRB_AND_DP_CONTROL)/sizeof(mmAZALIA_RIRB_AND_DP_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_CORB_DMA_CONTROL", REG_MMIO, 0x17ec, &mmAZALIA_CORB_DMA_CONTROL[0], sizeof(mmAZALIA_CORB_DMA_CONTROL)/sizeof(mmAZALIA_CORB_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER", REG_MMIO, 0x17f3, &mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0], sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER)/sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0]), 0, 0 },
+	{ "mmAZALIA_CYCLIC_BUFFER_SYNC", REG_MMIO, 0x17f4, &mmAZALIA_CYCLIC_BUFFER_SYNC[0], sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC)/sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC[0]), 0, 0 },
+	{ "mmAZALIA_GLOBAL_CAPABILITIES", REG_MMIO, 0x17f5, &mmAZALIA_GLOBAL_CAPABILITIES[0], sizeof(mmAZALIA_GLOBAL_CAPABILITIES)/sizeof(mmAZALIA_GLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x17f6, &mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL", REG_MMIO, 0x17f7, &mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0], sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL)/sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x17f8, &mmAZALIA_INPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_INPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_INPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_DEBUG", REG_MMIO, 0x17f9, &mmAZALIA_CONTROLLER_DEBUG[0], sizeof(mmAZALIA_CONTROLLER_DEBUG)/sizeof(mmAZALIA_CONTROLLER_DEBUG[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL0", REG_MMIO, 0x17fb, &mmAZALIA_INPUT_CRC0_CONTROL0[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL0)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL1", REG_MMIO, 0x17fc, &mmAZALIA_INPUT_CRC0_CONTROL1[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL1)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL2", REG_MMIO, 0x17fd, &mmAZALIA_INPUT_CRC0_CONTROL2[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL2)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL3", REG_MMIO, 0x17fe, &mmAZALIA_INPUT_CRC0_CONTROL3[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL3)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET", REG_SMC, 0x17ff, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_RESULT", REG_MMIO, 0x17ff, &mmAZALIA_INPUT_CRC0_RESULT[0], sizeof(mmAZALIA_INPUT_CRC0_RESULT)/sizeof(mmAZALIA_INPUT_CRC0_RESULT[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_I", REG_SMC, 0x18, &ixDP_AUX_DEBUG_I[0], sizeof(ixDP_AUX_DEBUG_I)/sizeof(ixDP_AUX_DEBUG_I[0]), 0, 0 },
+	{ "ixDCIO_DEBUG18", REG_SMC, 0x18, &ixDCIO_DEBUG18[0], sizeof(ixDCIO_DEBUG18)/sizeof(ixDCIO_DEBUG18[0]), 0, 0 },
+	{ "ixCRT18", REG_SMC, 0x18, &ixCRT18[0], sizeof(ixCRT18)/sizeof(ixCRT18[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL0", REG_MMIO, 0x1800, &mmAZALIA_INPUT_CRC1_CONTROL0[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL0)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL1", REG_MMIO, 0x1801, &mmAZALIA_INPUT_CRC1_CONTROL1[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL1)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL2", REG_MMIO, 0x1802, &mmAZALIA_INPUT_CRC1_CONTROL2[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL2)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL3", REG_MMIO, 0x1803, &mmAZALIA_INPUT_CRC1_CONTROL3[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL3)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_RESULT", REG_MMIO, 0x1804, &mmAZALIA_INPUT_CRC1_RESULT[0], sizeof(mmAZALIA_INPUT_CRC1_RESULT)/sizeof(mmAZALIA_INPUT_CRC1_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL0", REG_MMIO, 0x1805, &mmAZALIA_CRC0_CONTROL0[0], sizeof(mmAZALIA_CRC0_CONTROL0)/sizeof(mmAZALIA_CRC0_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL1", REG_MMIO, 0x1806, &mmAZALIA_CRC0_CONTROL1[0], sizeof(mmAZALIA_CRC0_CONTROL1)/sizeof(mmAZALIA_CRC0_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL2", REG_MMIO, 0x1807, &mmAZALIA_CRC0_CONTROL2[0], sizeof(mmAZALIA_CRC0_CONTROL2)/sizeof(mmAZALIA_CRC0_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL3", REG_MMIO, 0x1808, &mmAZALIA_CRC0_CONTROL3[0], sizeof(mmAZALIA_CRC0_CONTROL3)/sizeof(mmAZALIA_CRC0_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_RESULT", REG_MMIO, 0x1809, &mmAZALIA_CRC0_RESULT[0], sizeof(mmAZALIA_CRC0_RESULT)/sizeof(mmAZALIA_CRC0_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL0", REG_MMIO, 0x180a, &mmAZALIA_CRC1_CONTROL0[0], sizeof(mmAZALIA_CRC1_CONTROL0)/sizeof(mmAZALIA_CRC1_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL1", REG_MMIO, 0x180b, &mmAZALIA_CRC1_CONTROL1[0], sizeof(mmAZALIA_CRC1_CONTROL1)/sizeof(mmAZALIA_CRC1_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL2", REG_MMIO, 0x180c, &mmAZALIA_CRC1_CONTROL2[0], sizeof(mmAZALIA_CRC1_CONTROL2)/sizeof(mmAZALIA_CRC1_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL3", REG_MMIO, 0x180d, &mmAZALIA_CRC1_CONTROL3[0], sizeof(mmAZALIA_CRC1_CONTROL3)/sizeof(mmAZALIA_CRC1_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_RESULT", REG_MMIO, 0x180e, &mmAZALIA_CRC1_RESULT[0], sizeof(mmAZALIA_CRC1_RESULT)/sizeof(mmAZALIA_CRC1_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_MEM_PWR_CTRL", REG_MMIO, 0x1810, &mmAZALIA_MEM_PWR_CTRL[0], sizeof(mmAZALIA_MEM_PWR_CTRL)/sizeof(mmAZALIA_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmAZALIA_MEM_PWR_STATUS", REG_MMIO, 0x1811, &mmAZALIA_MEM_PWR_STATUS[0], sizeof(mmAZALIA_MEM_PWR_STATUS)/sizeof(mmAZALIA_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCI_PG_DEBUG_CONFIG", REG_MMIO, 0x1812, &mmDCI_PG_DEBUG_CONFIG[0], sizeof(mmDCI_PG_DEBUG_CONFIG)/sizeof(mmDCI_PG_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_INDEX", REG_MMIO, 0x181f, &mmAZ_TEST_DEBUG_INDEX[0], sizeof(mmAZ_TEST_DEBUG_INDEX)/sizeof(mmAZ_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_DATA", REG_MMIO, 0x1820, &mmAZ_TEST_DEBUG_DATA[0], sizeof(mmAZ_TEST_DEBUG_DATA)/sizeof(mmAZ_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_MMIO, 0x1828, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID", REG_MMIO, 0x1829, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL", REG_MMIO, 0x182a, &mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL)/sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL", REG_MMIO, 0x182b, &mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL)/sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_MMIO, 0x182c, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_MMIO, 0x182d, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_MMIO, 0x182e, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_MMIO, 0x182f, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_MMIO, 0x1830, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET", REG_MMIO, 0x1831, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_MMIO, 0x1832, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_MMIO, 0x1833, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY", REG_MMIO, 0x1834, &mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0]), 0, 0 },
+	{ "mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY", REG_MMIO, 0x1835, &mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_DEBUG", REG_MMIO, 0x1836, &mmAZALIA_F0_CODEC_DEBUG[0], sizeof(mmAZALIA_F0_CODEC_DEBUG)/sizeof(mmAZALIA_F0_CODEC_DEBUG[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET0", REG_MMIO, 0x1837, &mmAZALIA_F0_GTC_GROUP_OFFSET0[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET1", REG_MMIO, 0x1838, &mmAZALIA_F0_GTC_GROUP_OFFSET1[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET2", REG_MMIO, 0x1839, &mmAZALIA_F0_GTC_GROUP_OFFSET2[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET3", REG_MMIO, 0x183a, &mmAZALIA_F0_GTC_GROUP_OFFSET3[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET4", REG_MMIO, 0x183b, &mmAZALIA_F0_GTC_GROUP_OFFSET4[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET5", REG_MMIO, 0x183c, &mmAZALIA_F0_GTC_GROUP_OFFSET5[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET6", REG_MMIO, 0x183d, &mmAZALIA_F0_GTC_GROUP_OFFSET6[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6[0]), 0, 0 },
+	{ "mmDCO_SCRATCH0", REG_MMIO, 0x184e, &mmDCO_SCRATCH0[0], sizeof(mmDCO_SCRATCH0)/sizeof(mmDCO_SCRATCH0[0]), 0, 0 },
+	{ "mmDCO_SCRATCH1", REG_MMIO, 0x184f, &mmDCO_SCRATCH1[0], sizeof(mmDCO_SCRATCH1)/sizeof(mmDCO_SCRATCH1[0]), 0, 0 },
+	{ "mmDCO_SCRATCH2", REG_MMIO, 0x1850, &mmDCO_SCRATCH2[0], sizeof(mmDCO_SCRATCH2)/sizeof(mmDCO_SCRATCH2[0]), 0, 0 },
+	{ "mmDCO_SCRATCH3", REG_MMIO, 0x1851, &mmDCO_SCRATCH3[0], sizeof(mmDCO_SCRATCH3)/sizeof(mmDCO_SCRATCH3[0]), 0, 0 },
+	{ "mmDCO_SCRATCH4", REG_MMIO, 0x1852, &mmDCO_SCRATCH4[0], sizeof(mmDCO_SCRATCH4)/sizeof(mmDCO_SCRATCH4[0]), 0, 0 },
+	{ "mmDCO_SCRATCH5", REG_MMIO, 0x1853, &mmDCO_SCRATCH5[0], sizeof(mmDCO_SCRATCH5)/sizeof(mmDCO_SCRATCH5[0]), 0, 0 },
+	{ "mmDCO_SCRATCH6", REG_MMIO, 0x1854, &mmDCO_SCRATCH6[0], sizeof(mmDCO_SCRATCH6)/sizeof(mmDCO_SCRATCH6[0]), 0, 0 },
+	{ "mmDCO_SCRATCH7", REG_MMIO, 0x1855, &mmDCO_SCRATCH7[0], sizeof(mmDCO_SCRATCH7)/sizeof(mmDCO_SCRATCH7[0]), 0, 0 },
+	{ "mmDCE_VCE_CONTROL", REG_MMIO, 0x1856, &mmDCE_VCE_CONTROL[0], sizeof(mmDCE_VCE_CONTROL)/sizeof(mmDCE_VCE_CONTROL[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS", REG_MMIO, 0x1857, &mmDISP_INTERRUPT_STATUS[0], sizeof(mmDISP_INTERRUPT_STATUS)/sizeof(mmDISP_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE", REG_MMIO, 0x1858, &mmDISP_INTERRUPT_STATUS_CONTINUE[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE2", REG_MMIO, 0x1859, &mmDISP_INTERRUPT_STATUS_CONTINUE2[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE3", REG_MMIO, 0x185a, &mmDISP_INTERRUPT_STATUS_CONTINUE3[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE4", REG_MMIO, 0x185b, &mmDISP_INTERRUPT_STATUS_CONTINUE4[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE5", REG_MMIO, 0x185c, &mmDISP_INTERRUPT_STATUS_CONTINUE5[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE6", REG_MMIO, 0x185d, &mmDISP_INTERRUPT_STATUS_CONTINUE6[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE7", REG_MMIO, 0x185e, &mmDISP_INTERRUPT_STATUS_CONTINUE7[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE8", REG_MMIO, 0x185f, &mmDISP_INTERRUPT_STATUS_CONTINUE8[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE9", REG_MMIO, 0x1860, &mmDISP_INTERRUPT_STATUS_CONTINUE9[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_STATUS", REG_MMIO, 0x1861, &mmDCO_MEM_PWR_STATUS[0], sizeof(mmDCO_MEM_PWR_STATUS)/sizeof(mmDCO_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_CTRL", REG_MMIO, 0x1862, &mmDCO_MEM_PWR_CTRL[0], sizeof(mmDCO_MEM_PWR_CTRL)/sizeof(mmDCO_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_CTRL2", REG_MMIO, 0x1863, &mmDCO_MEM_PWR_CTRL2[0], sizeof(mmDCO_MEM_PWR_CTRL2)/sizeof(mmDCO_MEM_PWR_CTRL2[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL", REG_MMIO, 0x1864, &mmDCO_CLK_CNTL[0], sizeof(mmDCO_CLK_CNTL)/sizeof(mmDCO_CLK_CNTL[0]), 0, 0 },
+	{ "mmDPDBG_CNTL", REG_MMIO, 0x1866, &mmDPDBG_CNTL[0], sizeof(mmDPDBG_CNTL)/sizeof(mmDPDBG_CNTL[0]), 0, 0 },
+	{ "mmDPDBG_INTERRUPT", REG_MMIO, 0x1867, &mmDPDBG_INTERRUPT[0], sizeof(mmDPDBG_INTERRUPT)/sizeof(mmDPDBG_INTERRUPT[0]), 0, 0 },
+	{ "mmDCO_POWER_MANAGEMENT_CNTL", REG_MMIO, 0x1868, &mmDCO_POWER_MANAGEMENT_CNTL[0], sizeof(mmDCO_POWER_MANAGEMENT_CNTL)/sizeof(mmDCO_POWER_MANAGEMENT_CNTL[0]), 0, 0 },
+	{ "mmDIG_SOFT_RESET_2", REG_MMIO, 0x186a, &mmDIG_SOFT_RESET_2[0], sizeof(mmDIG_SOFT_RESET_2)/sizeof(mmDIG_SOFT_RESET_2[0]), 0, 0 },
+	{ "mmDCO_STEREOSYNC_SEL", REG_MMIO, 0x186e, &mmDCO_STEREOSYNC_SEL[0], sizeof(mmDCO_STEREOSYNC_SEL)/sizeof(mmDCO_STEREOSYNC_SEL[0]), 0, 0 },
+	{ "mmDCO_TEST_DEBUG_INDEX", REG_MMIO, 0x186f, &mmDCO_TEST_DEBUG_INDEX[0], sizeof(mmDCO_TEST_DEBUG_INDEX)/sizeof(mmDCO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCO_TEST_DEBUG_DATA", REG_MMIO, 0x1870, &mmDCO_TEST_DEBUG_DATA[0], sizeof(mmDCO_TEST_DEBUG_DATA)/sizeof(mmDCO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCO_SOFT_RESET", REG_MMIO, 0x1871, &mmDCO_SOFT_RESET[0], sizeof(mmDCO_SOFT_RESET)/sizeof(mmDCO_SOFT_RESET[0]), 0, 0 },
+	{ "mmDIG_SOFT_RESET", REG_MMIO, 0x1872, &mmDIG_SOFT_RESET[0], sizeof(mmDIG_SOFT_RESET)/sizeof(mmDIG_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_STATUS1", REG_MMIO, 0x1874, &mmDCO_MEM_PWR_STATUS1[0], sizeof(mmDCO_MEM_PWR_STATUS1)/sizeof(mmDCO_MEM_PWR_STATUS1[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE10", REG_MMIO, 0x1875, &mmDISP_INTERRUPT_STATUS_CONTINUE10[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE10)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE10[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL2", REG_MMIO, 0x1876, &mmDCO_CLK_CNTL2[0], sizeof(mmDCO_CLK_CNTL2)/sizeof(mmDCO_CLK_CNTL2[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL3", REG_MMIO, 0x1877, &mmDCO_CLK_CNTL3[0], sizeof(mmDCO_CLK_CNTL3)/sizeof(mmDCO_CLK_CNTL3[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_INT_STATUS", REG_MMIO, 0x1898, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_INT_STATUS", REG_MMIO, 0x1898, &mmDC_HPD_INT_STATUS[0], sizeof(mmDC_HPD_INT_STATUS)/sizeof(mmDC_HPD_INT_STATUS[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_INT_CONTROL", REG_MMIO, 0x1899, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_INT_CONTROL", REG_MMIO, 0x1899, &mmDC_HPD_INT_CONTROL[0], sizeof(mmDC_HPD_INT_CONTROL)/sizeof(mmDC_HPD_INT_CONTROL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_CONTROL", REG_MMIO, 0x189a, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_CONTROL", REG_MMIO, 0x189a, &mmDC_HPD_CONTROL[0], sizeof(mmDC_HPD_CONTROL)/sizeof(mmDC_HPD_CONTROL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x189b, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x189b, &mmDC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x189c, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x189c, &mmDC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmHPD1_DC_HPD_INT_STATUS", REG_MMIO, 0x18a0, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_INT_CONTROL", REG_MMIO, 0x18a1, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_CONTROL", REG_MMIO, 0x18a2, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18a3, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18a4, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_INT_STATUS", REG_MMIO, 0x18a8, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_INT_CONTROL", REG_MMIO, 0x18a9, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_CONTROL", REG_MMIO, 0x18aa, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18ab, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18ac, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_INT_STATUS", REG_MMIO, 0x18b0, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_INT_CONTROL", REG_MMIO, 0x18b1, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_CONTROL", REG_MMIO, 0x18b2, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18b3, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18b4, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_INT_STATUS", REG_MMIO, 0x18b8, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_INT_CONTROL", REG_MMIO, 0x18b9, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_CONTROL", REG_MMIO, 0x18ba, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18bb, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18bc, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_INT_STATUS", REG_MMIO, 0x18c0, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_INT_CONTROL", REG_MMIO, 0x18c1, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_CONTROL", REG_MMIO, 0x18c2, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18c3, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18c4, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFCOUNTER_CNTL", REG_MMIO, 0x18c8, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFCOUNTER_STATE", REG_MMIO, 0x18c9, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x18ca, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CNTL", REG_MMIO, 0x18cb, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CVALUE_LOW", REG_MMIO, 0x18cc, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_HI", REG_MMIO, 0x18cd, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_LOW", REG_MMIO, 0x18ce, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x18cf, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x18d0, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CNTL2", REG_MMIO, 0x18d2, NULL, 0, 0, 0 },
+	{ "mmIMMEDIATE_RESPONSE_INPUT_INTERFACE", REG_MMIO, 0x19, &mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0], sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE)/sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_J", REG_SMC, 0x19, &ixDP_AUX_DEBUG_J[0], sizeof(ixDP_AUX_DEBUG_J)/sizeof(ixDP_AUX_DEBUG_J[0]), 0, 0 },
+	{ "ixDCIO_DEBUG19", REG_SMC, 0x19, &ixDCIO_DEBUG19[0], sizeof(ixDCIO_DEBUG19)/sizeof(ixDCIO_DEBUG19[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_STATUS", REG_MMIO, 0x1a, &mmIMMEDIATE_COMMAND_STATUS[0], sizeof(mmIMMEDIATE_COMMAND_STATUS)/sizeof(mmIMMEDIATE_COMMAND_STATUS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_K", REG_SMC, 0x1a, &ixDP_AUX_DEBUG_K[0], sizeof(ixDP_AUX_DEBUG_K)/sizeof(ixDP_AUX_DEBUG_K[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1A", REG_SMC, 0x1a, &ixDCIO_DEBUG1A[0], sizeof(ixDCIO_DEBUG1A)/sizeof(ixDCIO_DEBUG1A[0]), 0, 0 },
+	{ "mmDCP0_GRPH_ENABLE", REG_MMIO, 0x1a00, NULL, 0, 0, 0 },
+	{ "mmGRPH_ENABLE", REG_MMIO, 0x1a00, &mmGRPH_ENABLE[0], sizeof(mmGRPH_ENABLE)/sizeof(mmGRPH_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_CONTROL", REG_MMIO, 0x1a01, NULL, 0, 0, 0 },
+	{ "mmGRPH_CONTROL", REG_MMIO, 0x1a01, &mmGRPH_CONTROL[0], sizeof(mmGRPH_CONTROL)/sizeof(mmGRPH_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1a02, NULL, 0, 0, 0 },
+	{ "mmGRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1a02, &mmGRPH_LUT_10BIT_BYPASS[0], sizeof(mmGRPH_LUT_10BIT_BYPASS)/sizeof(mmGRPH_LUT_10BIT_BYPASS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SWAP_CNTL", REG_MMIO, 0x1a03, NULL, 0, 0, 0 },
+	{ "mmGRPH_SWAP_CNTL", REG_MMIO, 0x1a03, &mmGRPH_SWAP_CNTL[0], sizeof(mmGRPH_SWAP_CNTL)/sizeof(mmGRPH_SWAP_CNTL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1a04, NULL, 0, 0, 0 },
+	{ "mmGRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1a04, &mmGRPH_PRIMARY_SURFACE_ADDRESS[0], sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS)/sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a05, NULL, 0, 0, 0 },
+	{ "mmGRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a05, &mmGRPH_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS)/sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PITCH", REG_MMIO, 0x1a06, NULL, 0, 0, 0 },
+	{ "mmGRPH_PITCH", REG_MMIO, 0x1a06, &mmGRPH_PITCH[0], sizeof(mmGRPH_PITCH)/sizeof(mmGRPH_PITCH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a07, NULL, 0, 0, 0 },
+	{ "mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a07, &mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a08, NULL, 0, 0, 0 },
+	{ "mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a08, &mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1a09, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1a09, &mmGRPH_SURFACE_OFFSET_X[0], sizeof(mmGRPH_SURFACE_OFFSET_X)/sizeof(mmGRPH_SURFACE_OFFSET_X[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1a0a, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1a0a, &mmGRPH_SURFACE_OFFSET_Y[0], sizeof(mmGRPH_SURFACE_OFFSET_Y)/sizeof(mmGRPH_SURFACE_OFFSET_Y[0]), 0, 0 },
+	{ "mmDCP0_GRPH_X_START", REG_MMIO, 0x1a0b, NULL, 0, 0, 0 },
+	{ "mmGRPH_X_START", REG_MMIO, 0x1a0b, &mmGRPH_X_START[0], sizeof(mmGRPH_X_START)/sizeof(mmGRPH_X_START[0]), 0, 0 },
+	{ "mmDCP0_GRPH_Y_START", REG_MMIO, 0x1a0c, NULL, 0, 0, 0 },
+	{ "mmGRPH_Y_START", REG_MMIO, 0x1a0c, &mmGRPH_Y_START[0], sizeof(mmGRPH_Y_START)/sizeof(mmGRPH_Y_START[0]), 0, 0 },
+	{ "mmDCP0_GRPH_X_END", REG_MMIO, 0x1a0d, NULL, 0, 0, 0 },
+	{ "mmGRPH_X_END", REG_MMIO, 0x1a0d, &mmGRPH_X_END[0], sizeof(mmGRPH_X_END)/sizeof(mmGRPH_X_END[0]), 0, 0 },
+	{ "mmDCP0_GRPH_Y_END", REG_MMIO, 0x1a0e, NULL, 0, 0, 0 },
+	{ "mmGRPH_Y_END", REG_MMIO, 0x1a0e, &mmGRPH_Y_END[0], sizeof(mmGRPH_Y_END)/sizeof(mmGRPH_Y_END[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x1a0f, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x1a0f, &mmGRPH_SURFACE_COUNTER_CONTROL[0], sizeof(mmGRPH_SURFACE_COUNTER_CONTROL)/sizeof(mmGRPH_SURFACE_COUNTER_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1a10, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_CONTROL", REG_MMIO, 0x1a10, &mmINPUT_GAMMA_CONTROL[0], sizeof(mmINPUT_GAMMA_CONTROL)/sizeof(mmINPUT_GAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_UPDATE", REG_MMIO, 0x1a11, NULL, 0, 0, 0 },
+	{ "mmGRPH_UPDATE", REG_MMIO, 0x1a11, &mmGRPH_UPDATE[0], sizeof(mmGRPH_UPDATE)/sizeof(mmGRPH_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_CONTROL", REG_MMIO, 0x1a12, NULL, 0, 0, 0 },
+	{ "mmGRPH_FLIP_CONTROL", REG_MMIO, 0x1a12, &mmGRPH_FLIP_CONTROL[0], sizeof(mmGRPH_FLIP_CONTROL)/sizeof(mmGRPH_FLIP_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a13, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a13, &mmGRPH_SURFACE_ADDRESS_INUSE[0], sizeof(mmGRPH_SURFACE_ADDRESS_INUSE)/sizeof(mmGRPH_SURFACE_ADDRESS_INUSE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_CONTROL", REG_MMIO, 0x1a14, NULL, 0, 0, 0 },
+	{ "mmGRPH_DFQ_CONTROL", REG_MMIO, 0x1a14, &mmGRPH_DFQ_CONTROL[0], sizeof(mmGRPH_DFQ_CONTROL)/sizeof(mmGRPH_DFQ_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_STATUS", REG_MMIO, 0x1a15, NULL, 0, 0, 0 },
+	{ "mmGRPH_DFQ_STATUS", REG_MMIO, 0x1a15, &mmGRPH_DFQ_STATUS[0], sizeof(mmGRPH_DFQ_STATUS)/sizeof(mmGRPH_DFQ_STATUS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1a16, NULL, 0, 0, 0 },
+	{ "mmGRPH_INTERRUPT_STATUS", REG_MMIO, 0x1a16, &mmGRPH_INTERRUPT_STATUS[0], sizeof(mmGRPH_INTERRUPT_STATUS)/sizeof(mmGRPH_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1a17, NULL, 0, 0, 0 },
+	{ "mmGRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1a17, &mmGRPH_INTERRUPT_CONTROL[0], sizeof(mmGRPH_INTERRUPT_CONTROL)/sizeof(mmGRPH_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a18, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a18, &mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[0], sizeof(mmGRPH_SURFACE_ADDRESS_HIGH_INUSE)/sizeof(mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1a19, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1a19, &mmGRPH_COMPRESS_SURFACE_ADDRESS[0], sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS)/sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1a1a, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_PITCH", REG_MMIO, 0x1a1a, &mmGRPH_COMPRESS_PITCH[0], sizeof(mmGRPH_COMPRESS_PITCH)/sizeof(mmGRPH_COMPRESS_PITCH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a1b, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a1b, &mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x1a1c, NULL, 0, 0, 0 },
+	{ "mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x1a1c, &mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT[0], sizeof(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT)/sizeof(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x1a1d, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x1a1d, &mmGRPH_SURFACE_COUNTER_OUTPUT[0], sizeof(mmGRPH_SURFACE_COUNTER_OUTPUT)/sizeof(mmGRPH_SURFACE_COUNTER_OUTPUT[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1a2d, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_GRPH_CONTROL", REG_MMIO, 0x1a2d, &mmPRESCALE_GRPH_CONTROL[0], sizeof(mmPRESCALE_GRPH_CONTROL)/sizeof(mmPRESCALE_GRPH_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1a2e, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1a2e, &mmPRESCALE_VALUES_GRPH_R[0], sizeof(mmPRESCALE_VALUES_GRPH_R)/sizeof(mmPRESCALE_VALUES_GRPH_R[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1a2f, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1a2f, &mmPRESCALE_VALUES_GRPH_G[0], sizeof(mmPRESCALE_VALUES_GRPH_G)/sizeof(mmPRESCALE_VALUES_GRPH_G[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1a30, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1a30, &mmPRESCALE_VALUES_GRPH_B[0], sizeof(mmPRESCALE_VALUES_GRPH_B)/sizeof(mmPRESCALE_VALUES_GRPH_B[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_CONTROL", REG_MMIO, 0x1a35, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_CONTROL", REG_MMIO, 0x1a35, &mmINPUT_CSC_CONTROL[0], sizeof(mmINPUT_CSC_CONTROL)/sizeof(mmINPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C11_C12", REG_MMIO, 0x1a36, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C11_C12", REG_MMIO, 0x1a36, &mmINPUT_CSC_C11_C12[0], sizeof(mmINPUT_CSC_C11_C12)/sizeof(mmINPUT_CSC_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C13_C14", REG_MMIO, 0x1a37, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C13_C14", REG_MMIO, 0x1a37, &mmINPUT_CSC_C13_C14[0], sizeof(mmINPUT_CSC_C13_C14)/sizeof(mmINPUT_CSC_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C21_C22", REG_MMIO, 0x1a38, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C21_C22", REG_MMIO, 0x1a38, &mmINPUT_CSC_C21_C22[0], sizeof(mmINPUT_CSC_C21_C22)/sizeof(mmINPUT_CSC_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C23_C24", REG_MMIO, 0x1a39, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C23_C24", REG_MMIO, 0x1a39, &mmINPUT_CSC_C23_C24[0], sizeof(mmINPUT_CSC_C23_C24)/sizeof(mmINPUT_CSC_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C31_C32", REG_MMIO, 0x1a3a, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C31_C32", REG_MMIO, 0x1a3a, &mmINPUT_CSC_C31_C32[0], sizeof(mmINPUT_CSC_C31_C32)/sizeof(mmINPUT_CSC_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C33_C34", REG_MMIO, 0x1a3b, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C33_C34", REG_MMIO, 0x1a3b, &mmINPUT_CSC_C33_C34[0], sizeof(mmINPUT_CSC_C33_C34)/sizeof(mmINPUT_CSC_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1a3c, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_CONTROL", REG_MMIO, 0x1a3c, &mmOUTPUT_CSC_CONTROL[0], sizeof(mmOUTPUT_CSC_CONTROL)/sizeof(mmOUTPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1a3d, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12", REG_MMIO, 0x1a3d, &mmOUTPUT_CSC_C11_C12[0], sizeof(mmOUTPUT_CSC_C11_C12)/sizeof(mmOUTPUT_CSC_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1a3e, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14", REG_MMIO, 0x1a3e, &mmOUTPUT_CSC_C13_C14[0], sizeof(mmOUTPUT_CSC_C13_C14)/sizeof(mmOUTPUT_CSC_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1a3f, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22", REG_MMIO, 0x1a3f, &mmOUTPUT_CSC_C21_C22[0], sizeof(mmOUTPUT_CSC_C21_C22)/sizeof(mmOUTPUT_CSC_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1a40, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24", REG_MMIO, 0x1a40, &mmOUTPUT_CSC_C23_C24[0], sizeof(mmOUTPUT_CSC_C23_C24)/sizeof(mmOUTPUT_CSC_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1a41, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32", REG_MMIO, 0x1a41, &mmOUTPUT_CSC_C31_C32[0], sizeof(mmOUTPUT_CSC_C31_C32)/sizeof(mmOUTPUT_CSC_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1a42, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34", REG_MMIO, 0x1a42, &mmOUTPUT_CSC_C33_C34[0], sizeof(mmOUTPUT_CSC_C33_C34)/sizeof(mmOUTPUT_CSC_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1a43, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1a43, &mmCOMM_MATRIXA_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXA_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXA_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1a44, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1a44, &mmCOMM_MATRIXA_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXA_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXA_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1a45, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1a45, &mmCOMM_MATRIXA_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXA_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXA_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1a46, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1a46, &mmCOMM_MATRIXA_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXA_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXA_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1a47, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1a47, &mmCOMM_MATRIXA_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXA_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXA_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1a48, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1a48, &mmCOMM_MATRIXA_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXA_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXA_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1a49, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1a49, &mmCOMM_MATRIXB_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXB_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXB_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1a4a, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1a4a, &mmCOMM_MATRIXB_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXB_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXB_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1a4b, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1a4b, &mmCOMM_MATRIXB_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXB_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXB_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1a4c, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1a4c, &mmCOMM_MATRIXB_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXB_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXB_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1a4d, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1a4d, &mmCOMM_MATRIXB_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXB_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXB_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1a4e, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1a4e, &mmCOMM_MATRIXB_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXB_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXB_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DENORM_CONTROL", REG_MMIO, 0x1a50, NULL, 0, 0, 0 },
+	{ "mmDENORM_CONTROL", REG_MMIO, 0x1a50, &mmDENORM_CONTROL[0], sizeof(mmDENORM_CONTROL)/sizeof(mmDENORM_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_ROUND_CONTROL", REG_MMIO, 0x1a51, NULL, 0, 0, 0 },
+	{ "mmOUT_ROUND_CONTROL", REG_MMIO, 0x1a51, &mmOUT_ROUND_CONTROL[0], sizeof(mmOUT_ROUND_CONTROL)/sizeof(mmOUT_ROUND_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1a52, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1a52, &mmOUT_CLAMP_CONTROL_R_CR[0], sizeof(mmOUT_CLAMP_CONTROL_R_CR)/sizeof(mmOUT_CLAMP_CONTROL_R_CR[0]), 0, 0 },
+	{ "mmDCP0_KEY_CONTROL", REG_MMIO, 0x1a53, NULL, 0, 0, 0 },
+	{ "mmKEY_CONTROL", REG_MMIO, 0x1a53, &mmKEY_CONTROL[0], sizeof(mmKEY_CONTROL)/sizeof(mmKEY_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_ALPHA", REG_MMIO, 0x1a54, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_ALPHA", REG_MMIO, 0x1a54, &mmKEY_RANGE_ALPHA[0], sizeof(mmKEY_RANGE_ALPHA)/sizeof(mmKEY_RANGE_ALPHA[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_RED", REG_MMIO, 0x1a55, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_RED", REG_MMIO, 0x1a55, &mmKEY_RANGE_RED[0], sizeof(mmKEY_RANGE_RED)/sizeof(mmKEY_RANGE_RED[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_GREEN", REG_MMIO, 0x1a56, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_GREEN", REG_MMIO, 0x1a56, &mmKEY_RANGE_GREEN[0], sizeof(mmKEY_RANGE_GREEN)/sizeof(mmKEY_RANGE_GREEN[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_BLUE", REG_MMIO, 0x1a57, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_BLUE", REG_MMIO, 0x1a57, &mmKEY_RANGE_BLUE[0], sizeof(mmKEY_RANGE_BLUE)/sizeof(mmKEY_RANGE_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DEGAMMA_CONTROL", REG_MMIO, 0x1a58, NULL, 0, 0, 0 },
+	{ "mmDEGAMMA_CONTROL", REG_MMIO, 0x1a58, &mmDEGAMMA_CONTROL[0], sizeof(mmDEGAMMA_CONTROL)/sizeof(mmDEGAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1a59, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_CONTROL", REG_MMIO, 0x1a59, &mmGAMUT_REMAP_CONTROL[0], sizeof(mmGAMUT_REMAP_CONTROL)/sizeof(mmGAMUT_REMAP_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1a5a, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C11_C12", REG_MMIO, 0x1a5a, &mmGAMUT_REMAP_C11_C12[0], sizeof(mmGAMUT_REMAP_C11_C12)/sizeof(mmGAMUT_REMAP_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1a5b, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C13_C14", REG_MMIO, 0x1a5b, &mmGAMUT_REMAP_C13_C14[0], sizeof(mmGAMUT_REMAP_C13_C14)/sizeof(mmGAMUT_REMAP_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1a5c, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C21_C22", REG_MMIO, 0x1a5c, &mmGAMUT_REMAP_C21_C22[0], sizeof(mmGAMUT_REMAP_C21_C22)/sizeof(mmGAMUT_REMAP_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1a5d, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C23_C24", REG_MMIO, 0x1a5d, &mmGAMUT_REMAP_C23_C24[0], sizeof(mmGAMUT_REMAP_C23_C24)/sizeof(mmGAMUT_REMAP_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1a5e, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C31_C32", REG_MMIO, 0x1a5e, &mmGAMUT_REMAP_C31_C32[0], sizeof(mmGAMUT_REMAP_C31_C32)/sizeof(mmGAMUT_REMAP_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1a5f, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C33_C34", REG_MMIO, 0x1a5f, &mmGAMUT_REMAP_C33_C34[0], sizeof(mmGAMUT_REMAP_C33_C34)/sizeof(mmGAMUT_REMAP_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1a60, NULL, 0, 0, 0 },
+	{ "mmDCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1a60, &mmDCP_SPATIAL_DITHER_CNTL[0], sizeof(mmDCP_SPATIAL_DITHER_CNTL)/sizeof(mmDCP_SPATIAL_DITHER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1a65, NULL, 0, 0, 0 },
+	{ "mmDCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1a65, &mmDCP_FP_CONVERTED_FIELD[0], sizeof(mmDCP_FP_CONVERTED_FIELD)/sizeof(mmDCP_FP_CONVERTED_FIELD[0]), 0, 0 },
+	{ "mmDCP0_CUR_CONTROL", REG_MMIO, 0x1a66, NULL, 0, 0, 0 },
+	{ "mmCUR_CONTROL", REG_MMIO, 0x1a66, &mmCUR_CONTROL[0], sizeof(mmCUR_CONTROL)/sizeof(mmCUR_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1a67, NULL, 0, 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS", REG_MMIO, 0x1a67, &mmCUR_SURFACE_ADDRESS[0], sizeof(mmCUR_SURFACE_ADDRESS)/sizeof(mmCUR_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_CUR_SIZE", REG_MMIO, 0x1a68, NULL, 0, 0, 0 },
+	{ "mmCUR_SIZE", REG_MMIO, 0x1a68, &mmCUR_SIZE[0], sizeof(mmCUR_SIZE)/sizeof(mmCUR_SIZE[0]), 0, 0 },
+	{ "mmDCP0_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a69, NULL, 0, 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a69, &mmCUR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCUR_SURFACE_ADDRESS_HIGH)/sizeof(mmCUR_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_CUR_POSITION", REG_MMIO, 0x1a6a, NULL, 0, 0, 0 },
+	{ "mmCUR_POSITION", REG_MMIO, 0x1a6a, &mmCUR_POSITION[0], sizeof(mmCUR_POSITION)/sizeof(mmCUR_POSITION[0]), 0, 0 },
+	{ "mmDCP0_CUR_HOT_SPOT", REG_MMIO, 0x1a6b, NULL, 0, 0, 0 },
+	{ "mmCUR_HOT_SPOT", REG_MMIO, 0x1a6b, &mmCUR_HOT_SPOT[0], sizeof(mmCUR_HOT_SPOT)/sizeof(mmCUR_HOT_SPOT[0]), 0, 0 },
+	{ "mmDCP0_CUR_COLOR1", REG_MMIO, 0x1a6c, NULL, 0, 0, 0 },
+	{ "mmCUR_COLOR1", REG_MMIO, 0x1a6c, &mmCUR_COLOR1[0], sizeof(mmCUR_COLOR1)/sizeof(mmCUR_COLOR1[0]), 0, 0 },
+	{ "mmDCP0_CUR_COLOR2", REG_MMIO, 0x1a6d, NULL, 0, 0, 0 },
+	{ "mmCUR_COLOR2", REG_MMIO, 0x1a6d, &mmCUR_COLOR2[0], sizeof(mmCUR_COLOR2)/sizeof(mmCUR_COLOR2[0]), 0, 0 },
+	{ "mmDCP0_CUR_UPDATE", REG_MMIO, 0x1a6e, NULL, 0, 0, 0 },
+	{ "mmCUR_UPDATE", REG_MMIO, 0x1a6e, &mmCUR_UPDATE[0], sizeof(mmCUR_UPDATE)/sizeof(mmCUR_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_RW_MODE", REG_MMIO, 0x1a78, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_RW_MODE", REG_MMIO, 0x1a78, &mmDC_LUT_RW_MODE[0], sizeof(mmDC_LUT_RW_MODE)/sizeof(mmDC_LUT_RW_MODE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_RW_INDEX", REG_MMIO, 0x1a79, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_RW_INDEX", REG_MMIO, 0x1a79, &mmDC_LUT_RW_INDEX[0], sizeof(mmDC_LUT_RW_INDEX)/sizeof(mmDC_LUT_RW_INDEX[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1a7a, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_SEQ_COLOR", REG_MMIO, 0x1a7a, &mmDC_LUT_SEQ_COLOR[0], sizeof(mmDC_LUT_SEQ_COLOR)/sizeof(mmDC_LUT_SEQ_COLOR[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_PWL_DATA", REG_MMIO, 0x1a7b, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_PWL_DATA", REG_MMIO, 0x1a7b, &mmDC_LUT_PWL_DATA[0], sizeof(mmDC_LUT_PWL_DATA)/sizeof(mmDC_LUT_PWL_DATA[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_30_COLOR", REG_MMIO, 0x1a7c, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_30_COLOR", REG_MMIO, 0x1a7c, &mmDC_LUT_30_COLOR[0], sizeof(mmDC_LUT_30_COLOR)/sizeof(mmDC_LUT_30_COLOR[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1a7d, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1a7d, &mmDC_LUT_VGA_ACCESS_ENABLE[0], sizeof(mmDC_LUT_VGA_ACCESS_ENABLE)/sizeof(mmDC_LUT_VGA_ACCESS_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1a7e, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1a7e, &mmDC_LUT_WRITE_EN_MASK[0], sizeof(mmDC_LUT_WRITE_EN_MASK)/sizeof(mmDC_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_AUTOFILL", REG_MMIO, 0x1a7f, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_AUTOFILL", REG_MMIO, 0x1a7f, &mmDC_LUT_AUTOFILL[0], sizeof(mmDC_LUT_AUTOFILL)/sizeof(mmDC_LUT_AUTOFILL[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_CONTROL", REG_MMIO, 0x1a80, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_CONTROL", REG_MMIO, 0x1a80, &mmDC_LUT_CONTROL[0], sizeof(mmDC_LUT_CONTROL)/sizeof(mmDC_LUT_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1a81, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1a81, &mmDC_LUT_BLACK_OFFSET_BLUE[0], sizeof(mmDC_LUT_BLACK_OFFSET_BLUE)/sizeof(mmDC_LUT_BLACK_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1a82, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1a82, &mmDC_LUT_BLACK_OFFSET_GREEN[0], sizeof(mmDC_LUT_BLACK_OFFSET_GREEN)/sizeof(mmDC_LUT_BLACK_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1a83, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1a83, &mmDC_LUT_BLACK_OFFSET_RED[0], sizeof(mmDC_LUT_BLACK_OFFSET_RED)/sizeof(mmDC_LUT_BLACK_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1a84, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1a84, &mmDC_LUT_WHITE_OFFSET_BLUE[0], sizeof(mmDC_LUT_WHITE_OFFSET_BLUE)/sizeof(mmDC_LUT_WHITE_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1a85, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1a85, &mmDC_LUT_WHITE_OFFSET_GREEN[0], sizeof(mmDC_LUT_WHITE_OFFSET_GREEN)/sizeof(mmDC_LUT_WHITE_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1a86, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1a86, &mmDC_LUT_WHITE_OFFSET_RED[0], sizeof(mmDC_LUT_WHITE_OFFSET_RED)/sizeof(mmDC_LUT_WHITE_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CONTROL", REG_MMIO, 0x1a87, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_CONTROL", REG_MMIO, 0x1a87, &mmDCP_CRC_CONTROL[0], sizeof(mmDCP_CRC_CONTROL)/sizeof(mmDCP_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_MASK", REG_MMIO, 0x1a88, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_MASK", REG_MMIO, 0x1a88, &mmDCP_CRC_MASK[0], sizeof(mmDCP_CRC_MASK)/sizeof(mmDCP_CRC_MASK[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CURRENT", REG_MMIO, 0x1a89, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_CURRENT", REG_MMIO, 0x1a89, &mmDCP_CRC_CURRENT[0], sizeof(mmDCP_CRC_CURRENT)/sizeof(mmDCP_CRC_CURRENT[0]), 0, 0 },
+	{ "mmDCP0_DVMM_PTE_CONTROL", REG_MMIO, 0x1a8a, NULL, 0, 0, 0 },
+	{ "mmDVMM_PTE_CONTROL", REG_MMIO, 0x1a8a, &mmDVMM_PTE_CONTROL[0], sizeof(mmDVMM_PTE_CONTROL)/sizeof(mmDVMM_PTE_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_LAST", REG_MMIO, 0x1a8b, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_LAST", REG_MMIO, 0x1a8b, &mmDCP_CRC_LAST[0], sizeof(mmDCP_CRC_LAST)/sizeof(mmDCP_CRC_LAST[0]), 0, 0 },
+	{ "mmDCP0_DVMM_PTE_ARB_CONTROL", REG_MMIO, 0x1a8c, NULL, 0, 0, 0 },
+	{ "mmDVMM_PTE_ARB_CONTROL", REG_MMIO, 0x1a8c, &mmDVMM_PTE_ARB_CONTROL[0], sizeof(mmDVMM_PTE_ARB_CONTROL)/sizeof(mmDVMM_PTE_ARB_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG", REG_MMIO, 0x1a8d, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG", REG_MMIO, 0x1a8d, &mmDCP_DEBUG[0], sizeof(mmDCP_DEBUG)/sizeof(mmDCP_DEBUG[0]), 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1a8e, NULL, 0, 0, 0 },
+	{ "mmGRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1a8e, &mmGRPH_FLIP_RATE_CNTL[0], sizeof(mmGRPH_FLIP_RATE_CNTL)/sizeof(mmGRPH_FLIP_RATE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_DCP_GSL_CONTROL", REG_MMIO, 0x1a90, NULL, 0, 0, 0 },
+	{ "mmDCP_GSL_CONTROL", REG_MMIO, 0x1a90, &mmDCP_GSL_CONTROL[0], sizeof(mmDCP_GSL_CONTROL)/sizeof(mmDCP_GSL_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1a91, NULL, 0, 0, 0 },
+	{ "mmDCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1a91, &mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[0], sizeof(mmDCP_LB_DATA_GAP_BETWEEN_CHUNK)/sizeof(mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG_SG", REG_MMIO, 0x1a92, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG_SG", REG_MMIO, 0x1a92, &mmDCP_DEBUG_SG[0], sizeof(mmDCP_DEBUG_SG)/sizeof(mmDCP_DEBUG_SG[0]), 0, 0 },
+	{ "mmDCP0_DCP_DVMM_DEBUG", REG_MMIO, 0x1a93, NULL, 0, 0, 0 },
+	{ "mmDCP_DVMM_DEBUG", REG_MMIO, 0x1a93, &mmDCP_DVMM_DEBUG[0], sizeof(mmDCP_DVMM_DEBUG)/sizeof(mmDCP_DVMM_DEBUG[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG_SG2", REG_MMIO, 0x1a94, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG_SG2", REG_MMIO, 0x1a94, &mmDCP_DEBUG_SG2[0], sizeof(mmDCP_DEBUG_SG2)/sizeof(mmDCP_DEBUG_SG2[0]), 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1a95, NULL, 0, 0, 0 },
+	{ "mmDCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1a95, &mmDCP_TEST_DEBUG_INDEX[0], sizeof(mmDCP_TEST_DEBUG_INDEX)/sizeof(mmDCP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1a96, NULL, 0, 0, 0 },
+	{ "mmDCP_TEST_DEBUG_DATA", REG_MMIO, 0x1a96, &mmDCP_TEST_DEBUG_DATA[0], sizeof(mmDCP_TEST_DEBUG_DATA)/sizeof(mmDCP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCP0_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1a97, NULL, 0, 0, 0 },
+	{ "mmGRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1a97, &mmGRPH_STEREOSYNC_FLIP[0], sizeof(mmGRPH_STEREOSYNC_FLIP)/sizeof(mmGRPH_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG2", REG_MMIO, 0x1a98, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG2", REG_MMIO, 0x1a98, &mmDCP_DEBUG2[0], sizeof(mmDCP_DEBUG2)/sizeof(mmDCP_DEBUG2[0]), 0, 0 },
+	{ "mmDCP0_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1a99, NULL, 0, 0, 0 },
+	{ "mmCUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1a99, &mmCUR_REQUEST_FILTER_CNTL[0], sizeof(mmCUR_REQUEST_FILTER_CNTL)/sizeof(mmCUR_REQUEST_FILTER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_CUR_STEREO_CONTROL", REG_MMIO, 0x1a9a, NULL, 0, 0, 0 },
+	{ "mmCUR_STEREO_CONTROL", REG_MMIO, 0x1a9a, &mmCUR_STEREO_CONTROL[0], sizeof(mmCUR_STEREO_CONTROL)/sizeof(mmCUR_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1a9c, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1a9c, &mmOUT_CLAMP_CONTROL_G_Y[0], sizeof(mmOUT_CLAMP_CONTROL_G_Y)/sizeof(mmOUT_CLAMP_CONTROL_G_Y[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1a9d, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1a9d, &mmOUT_CLAMP_CONTROL_B_CB[0], sizeof(mmOUT_CLAMP_CONTROL_B_CB)/sizeof(mmOUT_CLAMP_CONTROL_B_CB[0]), 0, 0 },
+	{ "mmDCP0_HW_ROTATION", REG_MMIO, 0x1a9e, NULL, 0, 0, 0 },
+	{ "mmHW_ROTATION", REG_MMIO, 0x1a9e, &mmHW_ROTATION[0], sizeof(mmHW_ROTATION)/sizeof(mmHW_ROTATION[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1a9f, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1a9f, &mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[0], sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL)/sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CONTROL", REG_MMIO, 0x1aa0, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CONTROL", REG_MMIO, 0x1aa0, &mmREGAMMA_CONTROL[0], sizeof(mmREGAMMA_CONTROL)/sizeof(mmREGAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_INDEX", REG_MMIO, 0x1aa1, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_INDEX", REG_MMIO, 0x1aa1, &mmREGAMMA_LUT_INDEX[0], sizeof(mmREGAMMA_LUT_INDEX)/sizeof(mmREGAMMA_LUT_INDEX[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_DATA", REG_MMIO, 0x1aa2, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_DATA", REG_MMIO, 0x1aa2, &mmREGAMMA_LUT_DATA[0], sizeof(mmREGAMMA_LUT_DATA)/sizeof(mmREGAMMA_LUT_DATA[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1aa3, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1aa3, &mmREGAMMA_LUT_WRITE_EN_MASK[0], sizeof(mmREGAMMA_LUT_WRITE_EN_MASK)/sizeof(mmREGAMMA_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1aa4, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1aa4, &mmREGAMMA_CNTLA_START_CNTL[0], sizeof(mmREGAMMA_CNTLA_START_CNTL)/sizeof(mmREGAMMA_CNTLA_START_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1aa5, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1aa5, &mmREGAMMA_CNTLA_SLOPE_CNTL[0], sizeof(mmREGAMMA_CNTLA_SLOPE_CNTL)/sizeof(mmREGAMMA_CNTLA_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1aa6, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1aa6, &mmREGAMMA_CNTLA_END_CNTL1[0], sizeof(mmREGAMMA_CNTLA_END_CNTL1)/sizeof(mmREGAMMA_CNTLA_END_CNTL1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1aa7, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1aa7, &mmREGAMMA_CNTLA_END_CNTL2[0], sizeof(mmREGAMMA_CNTLA_END_CNTL2)/sizeof(mmREGAMMA_CNTLA_END_CNTL2[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1aa8, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1aa8, &mmREGAMMA_CNTLA_REGION_0_1[0], sizeof(mmREGAMMA_CNTLA_REGION_0_1)/sizeof(mmREGAMMA_CNTLA_REGION_0_1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1aa9, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1aa9, &mmREGAMMA_CNTLA_REGION_2_3[0], sizeof(mmREGAMMA_CNTLA_REGION_2_3)/sizeof(mmREGAMMA_CNTLA_REGION_2_3[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1aaa, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1aaa, &mmREGAMMA_CNTLA_REGION_4_5[0], sizeof(mmREGAMMA_CNTLA_REGION_4_5)/sizeof(mmREGAMMA_CNTLA_REGION_4_5[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1aab, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1aab, &mmREGAMMA_CNTLA_REGION_6_7[0], sizeof(mmREGAMMA_CNTLA_REGION_6_7)/sizeof(mmREGAMMA_CNTLA_REGION_6_7[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1aac, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1aac, &mmREGAMMA_CNTLA_REGION_8_9[0], sizeof(mmREGAMMA_CNTLA_REGION_8_9)/sizeof(mmREGAMMA_CNTLA_REGION_8_9[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1aad, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1aad, &mmREGAMMA_CNTLA_REGION_10_11[0], sizeof(mmREGAMMA_CNTLA_REGION_10_11)/sizeof(mmREGAMMA_CNTLA_REGION_10_11[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1aae, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1aae, &mmREGAMMA_CNTLA_REGION_12_13[0], sizeof(mmREGAMMA_CNTLA_REGION_12_13)/sizeof(mmREGAMMA_CNTLA_REGION_12_13[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1aaf, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1aaf, &mmREGAMMA_CNTLA_REGION_14_15[0], sizeof(mmREGAMMA_CNTLA_REGION_14_15)/sizeof(mmREGAMMA_CNTLA_REGION_14_15[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1ab0, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1ab0, &mmREGAMMA_CNTLB_START_CNTL[0], sizeof(mmREGAMMA_CNTLB_START_CNTL)/sizeof(mmREGAMMA_CNTLB_START_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1ab1, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1ab1, &mmREGAMMA_CNTLB_SLOPE_CNTL[0], sizeof(mmREGAMMA_CNTLB_SLOPE_CNTL)/sizeof(mmREGAMMA_CNTLB_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1ab2, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1ab2, &mmREGAMMA_CNTLB_END_CNTL1[0], sizeof(mmREGAMMA_CNTLB_END_CNTL1)/sizeof(mmREGAMMA_CNTLB_END_CNTL1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1ab3, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1ab3, &mmREGAMMA_CNTLB_END_CNTL2[0], sizeof(mmREGAMMA_CNTLB_END_CNTL2)/sizeof(mmREGAMMA_CNTLB_END_CNTL2[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1ab4, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1ab4, &mmREGAMMA_CNTLB_REGION_0_1[0], sizeof(mmREGAMMA_CNTLB_REGION_0_1)/sizeof(mmREGAMMA_CNTLB_REGION_0_1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1ab5, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1ab5, &mmREGAMMA_CNTLB_REGION_2_3[0], sizeof(mmREGAMMA_CNTLB_REGION_2_3)/sizeof(mmREGAMMA_CNTLB_REGION_2_3[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1ab6, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1ab6, &mmREGAMMA_CNTLB_REGION_4_5[0], sizeof(mmREGAMMA_CNTLB_REGION_4_5)/sizeof(mmREGAMMA_CNTLB_REGION_4_5[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1ab7, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1ab7, &mmREGAMMA_CNTLB_REGION_6_7[0], sizeof(mmREGAMMA_CNTLB_REGION_6_7)/sizeof(mmREGAMMA_CNTLB_REGION_6_7[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1ab8, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1ab8, &mmREGAMMA_CNTLB_REGION_8_9[0], sizeof(mmREGAMMA_CNTLB_REGION_8_9)/sizeof(mmREGAMMA_CNTLB_REGION_8_9[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1ab9, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1ab9, &mmREGAMMA_CNTLB_REGION_10_11[0], sizeof(mmREGAMMA_CNTLB_REGION_10_11)/sizeof(mmREGAMMA_CNTLB_REGION_10_11[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1aba, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1aba, &mmREGAMMA_CNTLB_REGION_12_13[0], sizeof(mmREGAMMA_CNTLB_REGION_12_13)/sizeof(mmREGAMMA_CNTLB_REGION_12_13[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1abb, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1abb, &mmREGAMMA_CNTLB_REGION_14_15[0], sizeof(mmREGAMMA_CNTLB_REGION_14_15)/sizeof(mmREGAMMA_CNTLB_REGION_14_15[0]), 0, 0 },
+	{ "mmDCP0_ALPHA_CONTROL", REG_MMIO, 0x1abc, NULL, 0, 0, 0 },
+	{ "mmALPHA_CONTROL", REG_MMIO, 0x1abc, &mmALPHA_CONTROL[0], sizeof(mmALPHA_CONTROL)/sizeof(mmALPHA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1abd, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1abd, &mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[0], sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS)/sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1abe, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1abe, &mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1abf, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1abf, &mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[0], sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS)/sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_DATA_FORMAT", REG_MMIO, 0x1ac0, NULL, 0, 0, 0 },
+	{ "mmLB_DATA_FORMAT", REG_MMIO, 0x1ac0, &mmLB_DATA_FORMAT[0], sizeof(mmLB_DATA_FORMAT)/sizeof(mmLB_DATA_FORMAT[0]), 0, 0 },
+	{ "mmLB0_LB_MEMORY_CTRL", REG_MMIO, 0x1ac1, NULL, 0, 0, 0 },
+	{ "mmLB_MEMORY_CTRL", REG_MMIO, 0x1ac1, &mmLB_MEMORY_CTRL[0], sizeof(mmLB_MEMORY_CTRL)/sizeof(mmLB_MEMORY_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ac2, NULL, 0, 0, 0 },
+	{ "mmLB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ac2, &mmLB_MEMORY_SIZE_STATUS[0], sizeof(mmLB_MEMORY_SIZE_STATUS)/sizeof(mmLB_MEMORY_SIZE_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1ac3, NULL, 0, 0, 0 },
+	{ "mmLB_DESKTOP_HEIGHT", REG_MMIO, 0x1ac3, &mmLB_DESKTOP_HEIGHT[0], sizeof(mmLB_DESKTOP_HEIGHT)/sizeof(mmLB_DESKTOP_HEIGHT[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE_START_END", REG_MMIO, 0x1ac4, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE_START_END", REG_MMIO, 0x1ac4, &mmLB_VLINE_START_END[0], sizeof(mmLB_VLINE_START_END)/sizeof(mmLB_VLINE_START_END[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE2_START_END", REG_MMIO, 0x1ac5, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE2_START_END", REG_MMIO, 0x1ac5, &mmLB_VLINE2_START_END[0], sizeof(mmLB_VLINE2_START_END)/sizeof(mmLB_VLINE2_START_END[0]), 0, 0 },
+	{ "mmLB0_LB_V_COUNTER", REG_MMIO, 0x1ac6, NULL, 0, 0, 0 },
+	{ "mmLB_V_COUNTER", REG_MMIO, 0x1ac6, &mmLB_V_COUNTER[0], sizeof(mmLB_V_COUNTER)/sizeof(mmLB_V_COUNTER[0]), 0, 0 },
+	{ "mmLB0_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ac7, NULL, 0, 0, 0 },
+	{ "mmLB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ac7, &mmLB_SNAPSHOT_V_COUNTER[0], sizeof(mmLB_SNAPSHOT_V_COUNTER)/sizeof(mmLB_SNAPSHOT_V_COUNTER[0]), 0, 0 },
+	{ "mmLB0_LB_INTERRUPT_MASK", REG_MMIO, 0x1ac8, NULL, 0, 0, 0 },
+	{ "mmLB_INTERRUPT_MASK", REG_MMIO, 0x1ac8, &mmLB_INTERRUPT_MASK[0], sizeof(mmLB_INTERRUPT_MASK)/sizeof(mmLB_INTERRUPT_MASK[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE_STATUS", REG_MMIO, 0x1ac9, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE_STATUS", REG_MMIO, 0x1ac9, &mmLB_VLINE_STATUS[0], sizeof(mmLB_VLINE_STATUS)/sizeof(mmLB_VLINE_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE2_STATUS", REG_MMIO, 0x1aca, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE2_STATUS", REG_MMIO, 0x1aca, &mmLB_VLINE2_STATUS[0], sizeof(mmLB_VLINE2_STATUS)/sizeof(mmLB_VLINE2_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_VBLANK_STATUS", REG_MMIO, 0x1acb, NULL, 0, 0, 0 },
+	{ "mmLB_VBLANK_STATUS", REG_MMIO, 0x1acb, &mmLB_VBLANK_STATUS[0], sizeof(mmLB_VBLANK_STATUS)/sizeof(mmLB_VBLANK_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_SYNC_RESET_SEL", REG_MMIO, 0x1acc, NULL, 0, 0, 0 },
+	{ "mmLB_SYNC_RESET_SEL", REG_MMIO, 0x1acc, &mmLB_SYNC_RESET_SEL[0], sizeof(mmLB_SYNC_RESET_SEL)/sizeof(mmLB_SYNC_RESET_SEL[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1acd, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_R_CR", REG_MMIO, 0x1acd, &mmLB_BLACK_KEYER_R_CR[0], sizeof(mmLB_BLACK_KEYER_R_CR)/sizeof(mmLB_BLACK_KEYER_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ace, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ace, &mmLB_BLACK_KEYER_G_Y[0], sizeof(mmLB_BLACK_KEYER_G_Y)/sizeof(mmLB_BLACK_KEYER_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1acf, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_B_CB", REG_MMIO, 0x1acf, &mmLB_BLACK_KEYER_B_CB[0], sizeof(mmLB_BLACK_KEYER_B_CB)/sizeof(mmLB_BLACK_KEYER_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ad0, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ad0, &mmLB_KEYER_COLOR_CTRL[0], sizeof(mmLB_KEYER_COLOR_CTRL)/sizeof(mmLB_KEYER_COLOR_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ad1, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ad1, &mmLB_KEYER_COLOR_R_CR[0], sizeof(mmLB_KEYER_COLOR_R_CR)/sizeof(mmLB_KEYER_COLOR_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ad2, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ad2, &mmLB_KEYER_COLOR_G_Y[0], sizeof(mmLB_KEYER_COLOR_G_Y)/sizeof(mmLB_KEYER_COLOR_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ad3, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ad3, &mmLB_KEYER_COLOR_B_CB[0], sizeof(mmLB_KEYER_COLOR_B_CB)/sizeof(mmLB_KEYER_COLOR_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ad4, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ad4, &mmLB_KEYER_COLOR_REP_R_CR[0], sizeof(mmLB_KEYER_COLOR_REP_R_CR)/sizeof(mmLB_KEYER_COLOR_REP_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ad5, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ad5, &mmLB_KEYER_COLOR_REP_G_Y[0], sizeof(mmLB_KEYER_COLOR_REP_G_Y)/sizeof(mmLB_KEYER_COLOR_REP_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ad6, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ad6, &mmLB_KEYER_COLOR_REP_B_CB[0], sizeof(mmLB_KEYER_COLOR_REP_B_CB)/sizeof(mmLB_KEYER_COLOR_REP_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ad7, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ad7, &mmLB_BUFFER_LEVEL_STATUS[0], sizeof(mmLB_BUFFER_LEVEL_STATUS)/sizeof(mmLB_BUFFER_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ad8, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ad8, &mmLB_BUFFER_URGENCY_CTRL[0], sizeof(mmLB_BUFFER_URGENCY_CTRL)/sizeof(mmLB_BUFFER_URGENCY_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ad9, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ad9, &mmLB_BUFFER_URGENCY_STATUS[0], sizeof(mmLB_BUFFER_URGENCY_STATUS)/sizeof(mmLB_BUFFER_URGENCY_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_STATUS", REG_MMIO, 0x1ada, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_STATUS", REG_MMIO, 0x1ada, &mmLB_BUFFER_STATUS[0], sizeof(mmLB_BUFFER_STATUS)/sizeof(mmLB_BUFFER_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1adc, NULL, 0, 0, 0 },
+	{ "mmLB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1adc, &mmLB_NO_OUTSTANDING_REQ_STATUS[0], sizeof(mmLB_NO_OUTSTANDING_REQ_STATUS)/sizeof(mmLB_NO_OUTSTANDING_REQ_STATUS[0]), 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ae0, NULL, 0, 0, 0 },
+	{ "mmMVP_AFR_FLIP_MODE", REG_MMIO, 0x1ae0, &mmMVP_AFR_FLIP_MODE[0], sizeof(mmMVP_AFR_FLIP_MODE)/sizeof(mmMVP_AFR_FLIP_MODE[0]), 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ae1, NULL, 0, 0, 0 },
+	{ "mmMVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ae1, &mmMVP_AFR_FLIP_FIFO_CNTL[0], sizeof(mmMVP_AFR_FLIP_FIFO_CNTL)/sizeof(mmMVP_AFR_FLIP_FIFO_CNTL[0]), 0, 0 },
+	{ "mmLB0_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ae2, NULL, 0, 0, 0 },
+	{ "mmMVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ae2, &mmMVP_FLIP_LINE_NUM_INSERT[0], sizeof(mmMVP_FLIP_LINE_NUM_INSERT)/sizeof(mmMVP_FLIP_LINE_NUM_INSERT[0]), 0, 0 },
+	{ "mmLB0_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ae3, NULL, 0, 0, 0 },
+	{ "mmDC_MVP_LB_CONTROL", REG_MMIO, 0x1ae3, &mmDC_MVP_LB_CONTROL[0], sizeof(mmDC_MVP_LB_CONTROL)/sizeof(mmDC_MVP_LB_CONTROL[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG", REG_MMIO, 0x1ae4, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG", REG_MMIO, 0x1ae4, &mmLB_DEBUG[0], sizeof(mmLB_DEBUG)/sizeof(mmLB_DEBUG[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG2", REG_MMIO, 0x1ae5, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG2", REG_MMIO, 0x1ae5, &mmLB_DEBUG2[0], sizeof(mmLB_DEBUG2)/sizeof(mmLB_DEBUG2[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG3", REG_MMIO, 0x1ae6, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG3", REG_MMIO, 0x1ae6, &mmLB_DEBUG3[0], sizeof(mmLB_DEBUG3)/sizeof(mmLB_DEBUG3[0]), 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1afe, NULL, 0, 0, 0 },
+	{ "mmLB_TEST_DEBUG_INDEX", REG_MMIO, 0x1afe, &mmLB_TEST_DEBUG_INDEX[0], sizeof(mmLB_TEST_DEBUG_INDEX)/sizeof(mmLB_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1aff, NULL, 0, 0, 0 },
+	{ "mmLB_TEST_DEBUG_DATA", REG_MMIO, 0x1aff, &mmLB_TEST_DEBUG_DATA[0], sizeof(mmLB_TEST_DEBUG_DATA)/sizeof(mmLB_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_L", REG_SMC, 0x1b, &ixDP_AUX_DEBUG_L[0], sizeof(ixDP_AUX_DEBUG_L)/sizeof(ixDP_AUX_DEBUG_L[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1B", REG_SMC, 0x1b, &ixDCIO_DEBUG1B[0], sizeof(ixDCIO_DEBUG1B)/sizeof(ixDCIO_DEBUG1B[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1b00, NULL, 0, 0, 0 },
+	{ "mmDCFE_CLOCK_CONTROL", REG_MMIO, 0x1b00, &mmDCFE_CLOCK_CONTROL[0], sizeof(mmDCFE_CLOCK_CONTROL)/sizeof(mmDCFE_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_SOFT_RESET", REG_MMIO, 0x1b01, NULL, 0, 0, 0 },
+	{ "mmDCFE_SOFT_RESET", REG_MMIO, 0x1b01, &mmDCFE_SOFT_RESET[0], sizeof(mmDCFE_SOFT_RESET)/sizeof(mmDCFE_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_DBG_CONFIG", REG_MMIO, 0x1b02, NULL, 0, 0, 0 },
+	{ "mmDCFE_DBG_CONFIG", REG_MMIO, 0x1b02, &mmDCFE_DBG_CONFIG[0], sizeof(mmDCFE_DBG_CONFIG)/sizeof(mmDCFE_DBG_CONFIG[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1b03, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_CTRL", REG_MMIO, 0x1b03, &mmDCFE_MEM_PWR_CTRL[0], sizeof(mmDCFE_MEM_PWR_CTRL)/sizeof(mmDCFE_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1b04, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1b04, &mmDCFE_MEM_PWR_CTRL2[0], sizeof(mmDCFE_MEM_PWR_CTRL2)/sizeof(mmDCFE_MEM_PWR_CTRL2[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1b05, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_STATUS", REG_MMIO, 0x1b05, &mmDCFE_MEM_PWR_STATUS[0], sizeof(mmDCFE_MEM_PWR_STATUS)/sizeof(mmDCFE_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_MISC", REG_MMIO, 0x1b06, NULL, 0, 0, 0 },
+	{ "mmDCFE_MISC", REG_MMIO, 0x1b06, &mmDCFE_MISC[0], sizeof(mmDCFE_MISC)/sizeof(mmDCFE_MISC[0]), 0, 0 },
+	{ "mmDC_PERFMON3_PERFCOUNTER_CNTL", REG_MMIO, 0x1b24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFCOUNTER_STATE", REG_MMIO, 0x1b25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1b26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CNTL", REG_MMIO, 0x1b27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CVALUE_LOW", REG_MMIO, 0x1b28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_HI", REG_MMIO, 0x1b29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_LOW", REG_MMIO, 0x1b2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1b2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1b2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CNTL2", REG_MMIO, 0x1b2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1b30, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1b30, &mmDPG_PIPE_ARBITRATION_CONTROL1[0], sizeof(mmDPG_PIPE_ARBITRATION_CONTROL1)/sizeof(mmDPG_PIPE_ARBITRATION_CONTROL1[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1b31, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1b31, &mmDPG_PIPE_ARBITRATION_CONTROL2[0], sizeof(mmDPG_PIPE_ARBITRATION_CONTROL2)/sizeof(mmDPG_PIPE_ARBITRATION_CONTROL2[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1b32, NULL, 0, 0, 0 },
+	{ "mmDPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1b32, &mmDPG_WATERMARK_MASK_CONTROL[0], sizeof(mmDPG_WATERMARK_MASK_CONTROL)/sizeof(mmDPG_WATERMARK_MASK_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1b33, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1b33, &mmDPG_PIPE_URGENCY_CONTROL[0], sizeof(mmDPG_PIPE_URGENCY_CONTROL)/sizeof(mmDPG_PIPE_URGENCY_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1b34, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1b34, &mmDPG_PIPE_DPM_CONTROL[0], sizeof(mmDPG_PIPE_DPM_CONTROL)/sizeof(mmDPG_PIPE_DPM_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1b35, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1b35, &mmDPG_PIPE_STUTTER_CONTROL[0], sizeof(mmDPG_PIPE_STUTTER_CONTROL)/sizeof(mmDPG_PIPE_STUTTER_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1b36, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1b36, &mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[0], sizeof(mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL)/sizeof(mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1b37, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1b37, &mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[0], sizeof(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)/sizeof(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1b38, NULL, 0, 0, 0 },
+	{ "mmDPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1b38, &mmDPG_TEST_DEBUG_INDEX[0], sizeof(mmDPG_TEST_DEBUG_INDEX)/sizeof(mmDPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1b39, NULL, 0, 0, 0 },
+	{ "mmDPG_TEST_DEBUG_DATA", REG_MMIO, 0x1b39, &mmDPG_TEST_DEBUG_DATA[0], sizeof(mmDPG_TEST_DEBUG_DATA)/sizeof(mmDPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1b3a, NULL, 0, 0, 0 },
+	{ "mmDPG_REPEATER_PROGRAM", REG_MMIO, 0x1b3a, &mmDPG_REPEATER_PROGRAM[0], sizeof(mmDPG_REPEATER_PROGRAM)/sizeof(mmDPG_REPEATER_PROGRAM[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_A", REG_MMIO, 0x1b3b, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_A", REG_MMIO, 0x1b3b, &mmDPG_HW_DEBUG_A[0], sizeof(mmDPG_HW_DEBUG_A)/sizeof(mmDPG_HW_DEBUG_A[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_B", REG_MMIO, 0x1b3c, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_B", REG_MMIO, 0x1b3c, &mmDPG_HW_DEBUG_B[0], sizeof(mmDPG_HW_DEBUG_B)/sizeof(mmDPG_HW_DEBUG_B[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_11", REG_MMIO, 0x1b3d, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_11", REG_MMIO, 0x1b3d, &mmDPG_HW_DEBUG_11[0], sizeof(mmDPG_HW_DEBUG_11)/sizeof(mmDPG_HW_DEBUG_11[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x1b3e, NULL, 0, 0, 0 },
+	{ "mmDPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x1b3e, &mmDPG_CHK_PRE_PROC_CNTL[0], sizeof(mmDPG_CHK_PRE_PROC_CNTL)/sizeof(mmDPG_CHK_PRE_PROC_CNTL[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1b40, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_SELECT", REG_MMIO, 0x1b40, &mmSCL_COEF_RAM_SELECT[0], sizeof(mmSCL_COEF_RAM_SELECT)/sizeof(mmSCL_COEF_RAM_SELECT[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1b41, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1b41, &mmSCL_COEF_RAM_TAP_DATA[0], sizeof(mmSCL_COEF_RAM_TAP_DATA)/sizeof(mmSCL_COEF_RAM_TAP_DATA[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE", REG_MMIO, 0x1b42, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE", REG_MMIO, 0x1b42, &mmSCL_MODE[0], sizeof(mmSCL_MODE)/sizeof(mmSCL_MODE[0]), 0, 0 },
+	{ "mmSCL0_SCL_TAP_CONTROL", REG_MMIO, 0x1b43, NULL, 0, 0, 0 },
+	{ "mmSCL_TAP_CONTROL", REG_MMIO, 0x1b43, &mmSCL_TAP_CONTROL[0], sizeof(mmSCL_TAP_CONTROL)/sizeof(mmSCL_TAP_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_CONTROL", REG_MMIO, 0x1b44, NULL, 0, 0, 0 },
+	{ "mmSCL_CONTROL", REG_MMIO, 0x1b44, &mmSCL_CONTROL[0], sizeof(mmSCL_CONTROL)/sizeof(mmSCL_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_BYPASS_CONTROL", REG_MMIO, 0x1b45, NULL, 0, 0, 0 },
+	{ "mmSCL_BYPASS_CONTROL", REG_MMIO, 0x1b45, &mmSCL_BYPASS_CONTROL[0], sizeof(mmSCL_BYPASS_CONTROL)/sizeof(mmSCL_BYPASS_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1b46, NULL, 0, 0, 0 },
+	{ "mmSCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1b46, &mmSCL_MANUAL_REPLICATE_CONTROL[0], sizeof(mmSCL_MANUAL_REPLICATE_CONTROL)/sizeof(mmSCL_MANUAL_REPLICATE_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1b47, NULL, 0, 0, 0 },
+	{ "mmSCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1b47, &mmSCL_AUTOMATIC_MODE_CONTROL[0], sizeof(mmSCL_AUTOMATIC_MODE_CONTROL)/sizeof(mmSCL_AUTOMATIC_MODE_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1b48, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1b48, &mmSCL_HORZ_FILTER_CONTROL[0], sizeof(mmSCL_HORZ_FILTER_CONTROL)/sizeof(mmSCL_HORZ_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1b49, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1b49, &mmSCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmSCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmSCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1b4a, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_INIT", REG_MMIO, 0x1b4a, &mmSCL_HORZ_FILTER_INIT[0], sizeof(mmSCL_HORZ_FILTER_INIT)/sizeof(mmSCL_HORZ_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1b4b, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1b4b, &mmSCL_VERT_FILTER_CONTROL[0], sizeof(mmSCL_VERT_FILTER_CONTROL)/sizeof(mmSCL_VERT_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1b4c, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1b4c, &mmSCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmSCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmSCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1b4d, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_INIT", REG_MMIO, 0x1b4d, &mmSCL_VERT_FILTER_INIT[0], sizeof(mmSCL_VERT_FILTER_INIT)/sizeof(mmSCL_VERT_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1b4e, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1b4e, &mmSCL_VERT_FILTER_INIT_BOT[0], sizeof(mmSCL_VERT_FILTER_INIT_BOT)/sizeof(mmSCL_VERT_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmSCL0_SCL_ROUND_OFFSET", REG_MMIO, 0x1b4f, NULL, 0, 0, 0 },
+	{ "mmSCL_ROUND_OFFSET", REG_MMIO, 0x1b4f, &mmSCL_ROUND_OFFSET[0], sizeof(mmSCL_ROUND_OFFSET)/sizeof(mmSCL_ROUND_OFFSET[0]), 0, 0 },
+	{ "mmSCL0_SCL_UPDATE", REG_MMIO, 0x1b51, NULL, 0, 0, 0 },
+	{ "mmSCL_UPDATE", REG_MMIO, 0x1b51, &mmSCL_UPDATE[0], sizeof(mmSCL_UPDATE)/sizeof(mmSCL_UPDATE[0]), 0, 0 },
+	{ "mmSCL0_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1b53, NULL, 0, 0, 0 },
+	{ "mmSCL_F_SHARP_CONTROL", REG_MMIO, 0x1b53, &mmSCL_F_SHARP_CONTROL[0], sizeof(mmSCL_F_SHARP_CONTROL)/sizeof(mmSCL_F_SHARP_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_ALU_CONTROL", REG_MMIO, 0x1b54, NULL, 0, 0, 0 },
+	{ "mmSCL_ALU_CONTROL", REG_MMIO, 0x1b54, &mmSCL_ALU_CONTROL[0], sizeof(mmSCL_ALU_CONTROL)/sizeof(mmSCL_ALU_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1b55, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1b55, &mmSCL_COEF_RAM_CONFLICT_STATUS[0], sizeof(mmSCL_COEF_RAM_CONFLICT_STATUS)/sizeof(mmSCL_COEF_RAM_CONFLICT_STATUS[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1b5b, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_START_SECONDARY", REG_MMIO, 0x1b5b, &mmVIEWPORT_START_SECONDARY[0], sizeof(mmVIEWPORT_START_SECONDARY)/sizeof(mmVIEWPORT_START_SECONDARY[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_START", REG_MMIO, 0x1b5c, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_START", REG_MMIO, 0x1b5c, &mmVIEWPORT_START[0], sizeof(mmVIEWPORT_START)/sizeof(mmVIEWPORT_START[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_SIZE", REG_MMIO, 0x1b5d, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_SIZE", REG_MMIO, 0x1b5d, &mmVIEWPORT_SIZE[0], sizeof(mmVIEWPORT_SIZE)/sizeof(mmVIEWPORT_SIZE[0]), 0, 0 },
+	{ "mmSCL0_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1b5e, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1b5e, &mmEXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmEXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmEXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 },
+	{ "mmSCL0_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1b5f, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1b5f, &mmEXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmEXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmEXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1b60, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET1", REG_MMIO, 0x1b60, &mmSCL_MODE_CHANGE_DET1[0], sizeof(mmSCL_MODE_CHANGE_DET1)/sizeof(mmSCL_MODE_CHANGE_DET1[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1b61, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET2", REG_MMIO, 0x1b61, &mmSCL_MODE_CHANGE_DET2[0], sizeof(mmSCL_MODE_CHANGE_DET2)/sizeof(mmSCL_MODE_CHANGE_DET2[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1b62, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET3", REG_MMIO, 0x1b62, &mmSCL_MODE_CHANGE_DET3[0], sizeof(mmSCL_MODE_CHANGE_DET3)/sizeof(mmSCL_MODE_CHANGE_DET3[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1b63, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_MASK", REG_MMIO, 0x1b63, &mmSCL_MODE_CHANGE_MASK[0], sizeof(mmSCL_MODE_CHANGE_MASK)/sizeof(mmSCL_MODE_CHANGE_MASK[0]), 0, 0 },
+	{ "mmSCL0_SCL_DEBUG2", REG_MMIO, 0x1b69, NULL, 0, 0, 0 },
+	{ "mmSCL_DEBUG2", REG_MMIO, 0x1b69, &mmSCL_DEBUG2[0], sizeof(mmSCL_DEBUG2)/sizeof(mmSCL_DEBUG2[0]), 0, 0 },
+	{ "mmSCL0_SCL_DEBUG", REG_MMIO, 0x1b6a, NULL, 0, 0, 0 },
+	{ "mmSCL_DEBUG", REG_MMIO, 0x1b6a, &mmSCL_DEBUG[0], sizeof(mmSCL_DEBUG)/sizeof(mmSCL_DEBUG[0]), 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1b6b, NULL, 0, 0, 0 },
+	{ "mmSCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1b6b, &mmSCL_TEST_DEBUG_INDEX[0], sizeof(mmSCL_TEST_DEBUG_INDEX)/sizeof(mmSCL_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1b6c, NULL, 0, 0, 0 },
+	{ "mmSCL_TEST_DEBUG_DATA", REG_MMIO, 0x1b6c, &mmSCL_TEST_DEBUG_DATA[0], sizeof(mmSCL_TEST_DEBUG_DATA)/sizeof(mmSCL_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLND0_BLND_CONTROL", REG_MMIO, 0x1b6d, NULL, 0, 0, 0 },
+	{ "mmBLND_CONTROL", REG_MMIO, 0x1b6d, &mmBLND_CONTROL[0], sizeof(mmBLND_CONTROL)/sizeof(mmBLND_CONTROL[0]), 0, 0 },
+	{ "mmBLND0_BLND_SM_CONTROL2", REG_MMIO, 0x1b6e, NULL, 0, 0, 0 },
+	{ "mmBLND_SM_CONTROL2", REG_MMIO, 0x1b6e, &mmBLND_SM_CONTROL2[0], sizeof(mmBLND_SM_CONTROL2)/sizeof(mmBLND_SM_CONTROL2[0]), 0, 0 },
+	{ "mmBLND0_BLND_CONTROL2", REG_MMIO, 0x1b6f, NULL, 0, 0, 0 },
+	{ "mmBLND_CONTROL2", REG_MMIO, 0x1b6f, &mmBLND_CONTROL2[0], sizeof(mmBLND_CONTROL2)/sizeof(mmBLND_CONTROL2[0]), 0, 0 },
+	{ "mmBLND0_BLND_UPDATE", REG_MMIO, 0x1b70, NULL, 0, 0, 0 },
+	{ "mmBLND_UPDATE", REG_MMIO, 0x1b70, &mmBLND_UPDATE[0], sizeof(mmBLND_UPDATE)/sizeof(mmBLND_UPDATE[0]), 0, 0 },
+	{ "mmBLND0_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1b71, NULL, 0, 0, 0 },
+	{ "mmBLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1b71, &mmBLND_UNDERFLOW_INTERRUPT[0], sizeof(mmBLND_UNDERFLOW_INTERRUPT)/sizeof(mmBLND_UNDERFLOW_INTERRUPT[0]), 0, 0 },
+	{ "mmBLND0_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1b73, NULL, 0, 0, 0 },
+	{ "mmBLND_V_UPDATE_LOCK", REG_MMIO, 0x1b73, &mmBLND_V_UPDATE_LOCK[0], sizeof(mmBLND_V_UPDATE_LOCK)/sizeof(mmBLND_V_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmBLND0_BLND_DEBUG", REG_MMIO, 0x1b74, NULL, 0, 0, 0 },
+	{ "mmBLND_DEBUG", REG_MMIO, 0x1b74, &mmBLND_DEBUG[0], sizeof(mmBLND_DEBUG)/sizeof(mmBLND_DEBUG[0]), 0, 0 },
+	{ "mmBLND0_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1b75, NULL, 0, 0, 0 },
+	{ "mmBLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1b75, &mmBLND_TEST_DEBUG_INDEX[0], sizeof(mmBLND_TEST_DEBUG_INDEX)/sizeof(mmBLND_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmBLND0_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1b76, NULL, 0, 0, 0 },
+	{ "mmBLND_TEST_DEBUG_DATA", REG_MMIO, 0x1b76, &mmBLND_TEST_DEBUG_DATA[0], sizeof(mmBLND_TEST_DEBUG_DATA)/sizeof(mmBLND_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLND0_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1b77, NULL, 0, 0, 0 },
+	{ "mmBLND_REG_UPDATE_STATUS", REG_MMIO, 0x1b77, &mmBLND_REG_UPDATE_STATUS[0], sizeof(mmBLND_REG_UPDATE_STATUS)/sizeof(mmBLND_REG_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b78, NULL, 0, 0, 0 },
+	{ "mmCRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b78, &mmCRTC_3D_STRUCTURE_CONTROL[0], sizeof(mmCRTC_3D_STRUCTURE_CONTROL)/sizeof(mmCRTC_3D_STRUCTURE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1b79, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1b79, &mmCRTC_GSL_VSYNC_GAP[0], sizeof(mmCRTC_GSL_VSYNC_GAP)/sizeof(mmCRTC_GSL_VSYNC_GAP[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_WINDOW", REG_MMIO, 0x1b7a, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_WINDOW", REG_MMIO, 0x1b7a, &mmCRTC_GSL_WINDOW[0], sizeof(mmCRTC_GSL_WINDOW)/sizeof(mmCRTC_GSL_WINDOW[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_CONTROL", REG_MMIO, 0x1b7b, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_CONTROL", REG_MMIO, 0x1b7b, &mmCRTC_GSL_CONTROL[0], sizeof(mmCRTC_GSL_CONTROL)/sizeof(mmCRTC_GSL_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1b7d, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1b7d, &mmCRTC_H_BLANK_EARLY_NUM[0], sizeof(mmCRTC_H_BLANK_EARLY_NUM)/sizeof(mmCRTC_H_BLANK_EARLY_NUM[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_TOTAL", REG_MMIO, 0x1b80, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_TOTAL", REG_MMIO, 0x1b80, &mmCRTC_H_TOTAL[0], sizeof(mmCRTC_H_TOTAL)/sizeof(mmCRTC_H_TOTAL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_START_END", REG_MMIO, 0x1b81, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_BLANK_START_END", REG_MMIO, 0x1b81, &mmCRTC_H_BLANK_START_END[0], sizeof(mmCRTC_H_BLANK_START_END)/sizeof(mmCRTC_H_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A", REG_MMIO, 0x1b82, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_A", REG_MMIO, 0x1b82, &mmCRTC_H_SYNC_A[0], sizeof(mmCRTC_H_SYNC_A)/sizeof(mmCRTC_H_SYNC_A[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1b83, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1b83, &mmCRTC_H_SYNC_A_CNTL[0], sizeof(mmCRTC_H_SYNC_A_CNTL)/sizeof(mmCRTC_H_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B", REG_MMIO, 0x1b84, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_B", REG_MMIO, 0x1b84, &mmCRTC_H_SYNC_B[0], sizeof(mmCRTC_H_SYNC_B)/sizeof(mmCRTC_H_SYNC_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1b85, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1b85, &mmCRTC_H_SYNC_B_CNTL[0], sizeof(mmCRTC_H_SYNC_B_CNTL)/sizeof(mmCRTC_H_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VBI_END", REG_MMIO, 0x1b86, NULL, 0, 0, 0 },
+	{ "mmCRTC_VBI_END", REG_MMIO, 0x1b86, &mmCRTC_VBI_END[0], sizeof(mmCRTC_VBI_END)/sizeof(mmCRTC_VBI_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL", REG_MMIO, 0x1b87, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL", REG_MMIO, 0x1b87, &mmCRTC_V_TOTAL[0], sizeof(mmCRTC_V_TOTAL)/sizeof(mmCRTC_V_TOTAL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1b88, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_MIN", REG_MMIO, 0x1b88, &mmCRTC_V_TOTAL_MIN[0], sizeof(mmCRTC_V_TOTAL_MIN)/sizeof(mmCRTC_V_TOTAL_MIN[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1b89, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_MAX", REG_MMIO, 0x1b89, &mmCRTC_V_TOTAL_MAX[0], sizeof(mmCRTC_V_TOTAL_MAX)/sizeof(mmCRTC_V_TOTAL_MAX[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1b8a, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1b8a, &mmCRTC_V_TOTAL_CONTROL[0], sizeof(mmCRTC_V_TOTAL_CONTROL)/sizeof(mmCRTC_V_TOTAL_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b8b, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b8b, &mmCRTC_V_TOTAL_INT_STATUS[0], sizeof(mmCRTC_V_TOTAL_INT_STATUS)/sizeof(mmCRTC_V_TOTAL_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b8c, NULL, 0, 0, 0 },
+	{ "mmCRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b8c, &mmCRTC_VSYNC_NOM_INT_STATUS[0], sizeof(mmCRTC_VSYNC_NOM_INT_STATUS)/sizeof(mmCRTC_VSYNC_NOM_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_BLANK_START_END", REG_MMIO, 0x1b8d, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_BLANK_START_END", REG_MMIO, 0x1b8d, &mmCRTC_V_BLANK_START_END[0], sizeof(mmCRTC_V_BLANK_START_END)/sizeof(mmCRTC_V_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A", REG_MMIO, 0x1b8e, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_A", REG_MMIO, 0x1b8e, &mmCRTC_V_SYNC_A[0], sizeof(mmCRTC_V_SYNC_A)/sizeof(mmCRTC_V_SYNC_A[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1b8f, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1b8f, &mmCRTC_V_SYNC_A_CNTL[0], sizeof(mmCRTC_V_SYNC_A_CNTL)/sizeof(mmCRTC_V_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B", REG_MMIO, 0x1b90, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_B", REG_MMIO, 0x1b90, &mmCRTC_V_SYNC_B[0], sizeof(mmCRTC_V_SYNC_B)/sizeof(mmCRTC_V_SYNC_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1b91, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1b91, &mmCRTC_V_SYNC_B_CNTL[0], sizeof(mmCRTC_V_SYNC_B_CNTL)/sizeof(mmCRTC_V_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1b92, NULL, 0, 0, 0 },
+	{ "mmCRTC_DTMTEST_CNTL", REG_MMIO, 0x1b92, &mmCRTC_DTMTEST_CNTL[0], sizeof(mmCRTC_DTMTEST_CNTL)/sizeof(mmCRTC_DTMTEST_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1b93, NULL, 0, 0, 0 },
+	{ "mmCRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1b93, &mmCRTC_DTMTEST_STATUS_POSITION[0], sizeof(mmCRTC_DTMTEST_STATUS_POSITION)/sizeof(mmCRTC_DTMTEST_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_CNTL", REG_MMIO, 0x1b94, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGA_CNTL", REG_MMIO, 0x1b94, &mmCRTC_TRIGA_CNTL[0], sizeof(mmCRTC_TRIGA_CNTL)/sizeof(mmCRTC_TRIGA_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b95, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b95, &mmCRTC_TRIGA_MANUAL_TRIG[0], sizeof(mmCRTC_TRIGA_MANUAL_TRIG)/sizeof(mmCRTC_TRIGA_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_CNTL", REG_MMIO, 0x1b96, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGB_CNTL", REG_MMIO, 0x1b96, &mmCRTC_TRIGB_CNTL[0], sizeof(mmCRTC_TRIGB_CNTL)/sizeof(mmCRTC_TRIGB_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b97, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b97, &mmCRTC_TRIGB_MANUAL_TRIG[0], sizeof(mmCRTC_TRIGB_MANUAL_TRIG)/sizeof(mmCRTC_TRIGB_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b98, NULL, 0, 0, 0 },
+	{ "mmCRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b98, &mmCRTC_FORCE_COUNT_NOW_CNTL[0], sizeof(mmCRTC_FORCE_COUNT_NOW_CNTL)/sizeof(mmCRTC_FORCE_COUNT_NOW_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FLOW_CONTROL", REG_MMIO, 0x1b99, NULL, 0, 0, 0 },
+	{ "mmCRTC_FLOW_CONTROL", REG_MMIO, 0x1b99, &mmCRTC_FLOW_CONTROL[0], sizeof(mmCRTC_FLOW_CONTROL)/sizeof(mmCRTC_FLOW_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b9a, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b9a, &mmCRTC_STEREO_FORCE_NEXT_EYE[0], sizeof(mmCRTC_STEREO_FORCE_NEXT_EYE)/sizeof(mmCRTC_STEREO_FORCE_NEXT_EYE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1b9b, NULL, 0, 0, 0 },
+	{ "mmCRTC_AVSYNC_COUNTER", REG_MMIO, 0x1b9b, &mmCRTC_AVSYNC_COUNTER[0], sizeof(mmCRTC_AVSYNC_COUNTER)/sizeof(mmCRTC_AVSYNC_COUNTER[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CONTROL", REG_MMIO, 0x1b9c, NULL, 0, 0, 0 },
+	{ "mmCRTC_CONTROL", REG_MMIO, 0x1b9c, &mmCRTC_CONTROL[0], sizeof(mmCRTC_CONTROL)/sizeof(mmCRTC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_CONTROL", REG_MMIO, 0x1b9d, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_CONTROL", REG_MMIO, 0x1b9d, &mmCRTC_BLANK_CONTROL[0], sizeof(mmCRTC_BLANK_CONTROL)/sizeof(mmCRTC_BLANK_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1b9e, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERLACE_CONTROL", REG_MMIO, 0x1b9e, &mmCRTC_INTERLACE_CONTROL[0], sizeof(mmCRTC_INTERLACE_CONTROL)/sizeof(mmCRTC_INTERLACE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1b9f, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERLACE_STATUS", REG_MMIO, 0x1b9f, &mmCRTC_INTERLACE_STATUS[0], sizeof(mmCRTC_INTERLACE_STATUS)/sizeof(mmCRTC_INTERLACE_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ba0, NULL, 0, 0, 0 },
+	{ "mmCRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ba0, &mmCRTC_FIELD_INDICATION_CONTROL[0], sizeof(mmCRTC_FIELD_INDICATION_CONTROL)/sizeof(mmCRTC_FIELD_INDICATION_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ba1, NULL, 0, 0, 0 },
+	{ "mmCRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ba1, &mmCRTC_PIXEL_DATA_READBACK0[0], sizeof(mmCRTC_PIXEL_DATA_READBACK0)/sizeof(mmCRTC_PIXEL_DATA_READBACK0[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ba2, NULL, 0, 0, 0 },
+	{ "mmCRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ba2, &mmCRTC_PIXEL_DATA_READBACK1[0], sizeof(mmCRTC_PIXEL_DATA_READBACK1)/sizeof(mmCRTC_PIXEL_DATA_READBACK1[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS", REG_MMIO, 0x1ba3, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS", REG_MMIO, 0x1ba3, &mmCRTC_STATUS[0], sizeof(mmCRTC_STATUS)/sizeof(mmCRTC_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_POSITION", REG_MMIO, 0x1ba4, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_POSITION", REG_MMIO, 0x1ba4, &mmCRTC_STATUS_POSITION[0], sizeof(mmCRTC_STATUS_POSITION)/sizeof(mmCRTC_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ba5, NULL, 0, 0, 0 },
+	{ "mmCRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ba5, &mmCRTC_NOM_VERT_POSITION[0], sizeof(mmCRTC_NOM_VERT_POSITION)/sizeof(mmCRTC_NOM_VERT_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ba6, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ba6, &mmCRTC_STATUS_FRAME_COUNT[0], sizeof(mmCRTC_STATUS_FRAME_COUNT)/sizeof(mmCRTC_STATUS_FRAME_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ba7, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ba7, &mmCRTC_STATUS_VF_COUNT[0], sizeof(mmCRTC_STATUS_VF_COUNT)/sizeof(mmCRTC_STATUS_VF_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ba8, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ba8, &mmCRTC_STATUS_HV_COUNT[0], sizeof(mmCRTC_STATUS_HV_COUNT)/sizeof(mmCRTC_STATUS_HV_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_CONTROL", REG_MMIO, 0x1ba9, NULL, 0, 0, 0 },
+	{ "mmCRTC_COUNT_CONTROL", REG_MMIO, 0x1ba9, &mmCRTC_COUNT_CONTROL[0], sizeof(mmCRTC_COUNT_CONTROL)/sizeof(mmCRTC_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_RESET", REG_MMIO, 0x1baa, NULL, 0, 0, 0 },
+	{ "mmCRTC_COUNT_RESET", REG_MMIO, 0x1baa, &mmCRTC_COUNT_RESET[0], sizeof(mmCRTC_COUNT_RESET)/sizeof(mmCRTC_COUNT_RESET[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bab, NULL, 0, 0, 0 },
+	{ "mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bab, &mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1bac, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1bac, &mmCRTC_VERT_SYNC_CONTROL[0], sizeof(mmCRTC_VERT_SYNC_CONTROL)/sizeof(mmCRTC_VERT_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_STATUS", REG_MMIO, 0x1bad, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_STATUS", REG_MMIO, 0x1bad, &mmCRTC_STEREO_STATUS[0], sizeof(mmCRTC_STEREO_STATUS)/sizeof(mmCRTC_STEREO_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_CONTROL", REG_MMIO, 0x1bae, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_CONTROL", REG_MMIO, 0x1bae, &mmCRTC_STEREO_CONTROL[0], sizeof(mmCRTC_STEREO_CONTROL)/sizeof(mmCRTC_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1baf, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1baf, &mmCRTC_SNAPSHOT_STATUS[0], sizeof(mmCRTC_SNAPSHOT_STATUS)/sizeof(mmCRTC_SNAPSHOT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1bb0, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1bb0, &mmCRTC_SNAPSHOT_CONTROL[0], sizeof(mmCRTC_SNAPSHOT_CONTROL)/sizeof(mmCRTC_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1bb1, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1bb1, &mmCRTC_SNAPSHOT_POSITION[0], sizeof(mmCRTC_SNAPSHOT_POSITION)/sizeof(mmCRTC_SNAPSHOT_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1bb2, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1bb2, &mmCRTC_SNAPSHOT_FRAME[0], sizeof(mmCRTC_SNAPSHOT_FRAME)/sizeof(mmCRTC_SNAPSHOT_FRAME[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1bb3, NULL, 0, 0, 0 },
+	{ "mmCRTC_START_LINE_CONTROL", REG_MMIO, 0x1bb3, &mmCRTC_START_LINE_CONTROL[0], sizeof(mmCRTC_START_LINE_CONTROL)/sizeof(mmCRTC_START_LINE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1bb4, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1bb4, &mmCRTC_INTERRUPT_CONTROL[0], sizeof(mmCRTC_INTERRUPT_CONTROL)/sizeof(mmCRTC_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_UPDATE_LOCK", REG_MMIO, 0x1bb5, NULL, 0, 0, 0 },
+	{ "mmCRTC_UPDATE_LOCK", REG_MMIO, 0x1bb5, &mmCRTC_UPDATE_LOCK[0], sizeof(mmCRTC_UPDATE_LOCK)/sizeof(mmCRTC_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bb6, NULL, 0, 0, 0 },
+	{ "mmCRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bb6, &mmCRTC_DOUBLE_BUFFER_CONTROL[0], sizeof(mmCRTC_DOUBLE_BUFFER_CONTROL)/sizeof(mmCRTC_DOUBLE_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1bb7, NULL, 0, 0, 0 },
+	{ "mmCRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1bb7, &mmCRTC_VGA_PARAMETER_CAPTURE_MODE[0], sizeof(mmCRTC_VGA_PARAMETER_CAPTURE_MODE)/sizeof(mmCRTC_VGA_PARAMETER_CAPTURE_MODE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bba, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bba, &mmCRTC_TEST_PATTERN_CONTROL[0], sizeof(mmCRTC_TEST_PATTERN_CONTROL)/sizeof(mmCRTC_TEST_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bbb, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bbb, &mmCRTC_TEST_PATTERN_PARAMETERS[0], sizeof(mmCRTC_TEST_PATTERN_PARAMETERS)/sizeof(mmCRTC_TEST_PATTERN_PARAMETERS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1bbc, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1bbc, &mmCRTC_TEST_PATTERN_COLOR[0], sizeof(mmCRTC_TEST_PATTERN_COLOR)/sizeof(mmCRTC_TEST_PATTERN_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x1bbd, NULL, 0, 0, 0 },
+	{ "mmCRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x1bbd, &mmCRTC_MASTER_UPDATE_LOCK[0], sizeof(mmCRTC_MASTER_UPDATE_LOCK)/sizeof(mmCRTC_MASTER_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x1bbe, NULL, 0, 0, 0 },
+	{ "mmCRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x1bbe, &mmCRTC_MASTER_UPDATE_MODE[0], sizeof(mmCRTC_MASTER_UPDATE_MODE)/sizeof(mmCRTC_MASTER_UPDATE_MODE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1bbf, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1bbf, &mmCRTC_MVP_INBAND_CNTL_INSERT[0], sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT)/sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1bc0, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1bc0, &mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[0], sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER)/sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_STATUS", REG_MMIO, 0x1bc1, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_STATUS", REG_MMIO, 0x1bc1, &mmCRTC_MVP_STATUS[0], sizeof(mmCRTC_MVP_STATUS)/sizeof(mmCRTC_MVP_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_EN", REG_MMIO, 0x1bc2, NULL, 0, 0, 0 },
+	{ "mmCRTC_MASTER_EN", REG_MMIO, 0x1bc2, &mmCRTC_MASTER_EN[0], sizeof(mmCRTC_MASTER_EN)/sizeof(mmCRTC_MASTER_EN[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1bc3, NULL, 0, 0, 0 },
+	{ "mmCRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1bc3, &mmCRTC_ALLOW_STOP_OFF_V_CNT[0], sizeof(mmCRTC_ALLOW_STOP_OFF_V_CNT)/sizeof(mmCRTC_ALLOW_STOP_OFF_V_CNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1bc4, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1bc4, &mmCRTC_V_UPDATE_INT_STATUS[0], sizeof(mmCRTC_V_UPDATE_INT_STATUS)/sizeof(mmCRTC_V_UPDATE_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1bc6, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1bc6, &mmCRTC_TEST_DEBUG_INDEX[0], sizeof(mmCRTC_TEST_DEBUG_INDEX)/sizeof(mmCRTC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1bc7, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1bc7, &mmCRTC_TEST_DEBUG_DATA[0], sizeof(mmCRTC_TEST_DEBUG_DATA)/sizeof(mmCRTC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1bc8, NULL, 0, 0, 0 },
+	{ "mmCRTC_OVERSCAN_COLOR", REG_MMIO, 0x1bc8, &mmCRTC_OVERSCAN_COLOR[0], sizeof(mmCRTC_OVERSCAN_COLOR)/sizeof(mmCRTC_OVERSCAN_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1bc9, NULL, 0, 0, 0 },
+	{ "mmCRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1bc9, &mmCRTC_OVERSCAN_COLOR_EXT[0], sizeof(mmCRTC_OVERSCAN_COLOR_EXT)/sizeof(mmCRTC_OVERSCAN_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1bca, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1bca, &mmCRTC_BLANK_DATA_COLOR[0], sizeof(mmCRTC_BLANK_DATA_COLOR)/sizeof(mmCRTC_BLANK_DATA_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1bcb, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1bcb, &mmCRTC_BLANK_DATA_COLOR_EXT[0], sizeof(mmCRTC_BLANK_DATA_COLOR_EXT)/sizeof(mmCRTC_BLANK_DATA_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR", REG_MMIO, 0x1bcc, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLACK_COLOR", REG_MMIO, 0x1bcc, &mmCRTC_BLACK_COLOR[0], sizeof(mmCRTC_BLACK_COLOR)/sizeof(mmCRTC_BLACK_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1bcd, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1bcd, &mmCRTC_BLACK_COLOR_EXT[0], sizeof(mmCRTC_BLACK_COLOR_EXT)/sizeof(mmCRTC_BLACK_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1bce, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1bce, &mmCRTC_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1bcf, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1bcf, &mmCRTC_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1bd0, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1bd0, &mmCRTC_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1bd1, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1bd1, &mmCRTC_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1bd2, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1bd2, &mmCRTC_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bd3, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bd3, &mmCRTC_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC_CNTL", REG_MMIO, 0x1bd4, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC_CNTL", REG_MMIO, 0x1bd4, &mmCRTC_CRC_CNTL[0], sizeof(mmCRTC_CRC_CNTL)/sizeof(mmCRTC_CRC_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bd5, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bd5, &mmCRTC_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWA_X_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bd6, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bd6, &mmCRTC_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bd7, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bd7, &mmCRTC_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWB_X_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bd8, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bd8, &mmCRTC_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1bd9, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_DATA_RG", REG_MMIO, 0x1bd9, &mmCRTC_CRC0_DATA_RG[0], sizeof(mmCRTC_CRC0_DATA_RG)/sizeof(mmCRTC_CRC0_DATA_RG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_DATA_B", REG_MMIO, 0x1bda, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_DATA_B", REG_MMIO, 0x1bda, &mmCRTC_CRC0_DATA_B[0], sizeof(mmCRTC_CRC0_DATA_B)/sizeof(mmCRTC_CRC0_DATA_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bdb, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bdb, &mmCRTC_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWA_X_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bdc, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bdc, &mmCRTC_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bdd, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bdd, &mmCRTC_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWB_X_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bde, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bde, &mmCRTC_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1bdf, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_DATA_RG", REG_MMIO, 0x1bdf, &mmCRTC_CRC1_DATA_RG[0], sizeof(mmCRTC_CRC1_DATA_RG)/sizeof(mmCRTC_CRC1_DATA_RG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_DATA_B", REG_MMIO, 0x1be0, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_DATA_B", REG_MMIO, 0x1be0, &mmCRTC_CRC1_DATA_B[0], sizeof(mmCRTC_CRC1_DATA_B)/sizeof(mmCRTC_CRC1_DATA_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1be7, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1be7, &mmCRTC_STATIC_SCREEN_CONTROL[0], sizeof(mmCRTC_STATIC_SCREEN_CONTROL)/sizeof(mmCRTC_STATIC_SCREEN_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1be8, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1be8, &mmFMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT_CLAMP_COMPONENT_R)/sizeof(mmFMT_CLAMP_COMPONENT_R[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1be9, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1be9, &mmFMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT_CLAMP_COMPONENT_G)/sizeof(mmFMT_CLAMP_COMPONENT_G[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1bea, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1bea, &mmFMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT_CLAMP_COMPONENT_B)/sizeof(mmFMT_CLAMP_COMPONENT_B[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1beb, NULL, 0, 0, 0 },
+	{ "mmFMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1beb, &mmFMT_TEST_DEBUG_INDEX[0], sizeof(mmFMT_TEST_DEBUG_INDEX)/sizeof(mmFMT_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1bec, NULL, 0, 0, 0 },
+	{ "mmFMT_TEST_DEBUG_DATA", REG_MMIO, 0x1bec, &mmFMT_TEST_DEBUG_DATA[0], sizeof(mmFMT_TEST_DEBUG_DATA)/sizeof(mmFMT_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmFMT0_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1bed, NULL, 0, 0, 0 },
+	{ "mmFMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1bed, &mmFMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT_DYNAMIC_EXP_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CONTROL", REG_MMIO, 0x1bee, NULL, 0, 0, 0 },
+	{ "mmFMT_CONTROL", REG_MMIO, 0x1bee, &mmFMT_CONTROL[0], sizeof(mmFMT_CONTROL)/sizeof(mmFMT_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1bf2, NULL, 0, 0, 0 },
+	{ "mmFMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1bf2, &mmFMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT_BIT_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1bf3, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1bf3, &mmFMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT_DITHER_RAND_R_SEED)/sizeof(mmFMT_DITHER_RAND_R_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1bf4, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1bf4, &mmFMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT_DITHER_RAND_G_SEED)/sizeof(mmFMT_DITHER_RAND_G_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1bf5, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1bf5, &mmFMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT_DITHER_RAND_B_SEED)/sizeof(mmFMT_DITHER_RAND_B_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1bf6, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1bf6, &mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[0], sizeof(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL)/sizeof(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1bf7, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1bf7, &mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[0], sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX)/sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1bf8, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1bf8, &mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[0], sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX)/sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_CNTL", REG_MMIO, 0x1bf9, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_CNTL", REG_MMIO, 0x1bf9, &mmFMT_CLAMP_CNTL[0], sizeof(mmFMT_CLAMP_CNTL)/sizeof(mmFMT_CLAMP_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_CNTL", REG_MMIO, 0x1bfa, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_CNTL", REG_MMIO, 0x1bfa, &mmFMT_CRC_CNTL[0], sizeof(mmFMT_CRC_CNTL)/sizeof(mmFMT_CRC_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfb, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfb, &mmFMT_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmFMT_CRC_SIG_RED_GREEN_MASK)/sizeof(mmFMT_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfc, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfc, &mmFMT_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmFMT_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmFMT_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1bfd, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1bfd, &mmFMT_CRC_SIG_RED_GREEN[0], sizeof(mmFMT_CRC_SIG_RED_GREEN)/sizeof(mmFMT_CRC_SIG_RED_GREEN[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1bfe, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1bfe, &mmFMT_CRC_SIG_BLUE_CONTROL[0], sizeof(mmFMT_CRC_SIG_BLUE_CONTROL)/sizeof(mmFMT_CRC_SIG_BLUE_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_DEBUG_CNTL", REG_MMIO, 0x1bff, NULL, 0, 0, 0 },
+	{ "mmFMT_DEBUG_CNTL", REG_MMIO, 0x1bff, &mmFMT_DEBUG_CNTL[0], sizeof(mmFMT_DEBUG_CNTL)/sizeof(mmFMT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDMA_POSITION_LOWER_BASE_ADDRESS", REG_MMIO, 0x1c, &mmDMA_POSITION_LOWER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_M", REG_SMC, 0x1c, &ixDP_AUX_DEBUG_M[0], sizeof(ixDP_AUX_DEBUG_M)/sizeof(ixDP_AUX_DEBUG_M[0]), 0, 0 },
+	{ "mmDCP1_GRPH_ENABLE", REG_MMIO, 0x1c00, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_CONTROL", REG_MMIO, 0x1c01, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1c02, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SWAP_CNTL", REG_MMIO, 0x1c03, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1c04, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1c05, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PITCH", REG_MMIO, 0x1c06, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c07, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c08, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1c09, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1c0a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_START", REG_MMIO, 0x1c0b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_START", REG_MMIO, 0x1c0c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_END", REG_MMIO, 0x1c0d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_END", REG_MMIO, 0x1c0e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x1c0f, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1c10, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_UPDATE", REG_MMIO, 0x1c11, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_CONTROL", REG_MMIO, 0x1c12, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1c13, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_CONTROL", REG_MMIO, 0x1c14, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_STATUS", REG_MMIO, 0x1c15, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1c16, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1c17, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1c18, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1c19, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1c1a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c1b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x1c1c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x1c1d, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1c2d, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1c2e, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1c2f, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1c30, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_CONTROL", REG_MMIO, 0x1c35, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C11_C12", REG_MMIO, 0x1c36, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C13_C14", REG_MMIO, 0x1c37, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C21_C22", REG_MMIO, 0x1c38, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C23_C24", REG_MMIO, 0x1c39, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C31_C32", REG_MMIO, 0x1c3a, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C33_C34", REG_MMIO, 0x1c3b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1c3c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1c3d, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1c3e, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1c3f, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1c40, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1c41, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1c42, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1c43, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1c44, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1c45, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1c46, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1c47, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1c48, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1c49, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1c4a, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1c4b, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1c4c, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1c4d, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1c4e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DENORM_CONTROL", REG_MMIO, 0x1c50, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_ROUND_CONTROL", REG_MMIO, 0x1c51, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1c52, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_CONTROL", REG_MMIO, 0x1c53, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_ALPHA", REG_MMIO, 0x1c54, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_RED", REG_MMIO, 0x1c55, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_GREEN", REG_MMIO, 0x1c56, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_BLUE", REG_MMIO, 0x1c57, NULL, 0, 0, 0 },
+	{ "mmDCP1_DEGAMMA_CONTROL", REG_MMIO, 0x1c58, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1c59, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1c5a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1c5b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1c5c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1c5d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1c5e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1c5f, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1c60, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1c65, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_CONTROL", REG_MMIO, 0x1c66, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1c67, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SIZE", REG_MMIO, 0x1c68, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c69, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_POSITION", REG_MMIO, 0x1c6a, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_HOT_SPOT", REG_MMIO, 0x1c6b, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR1", REG_MMIO, 0x1c6c, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR2", REG_MMIO, 0x1c6d, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_UPDATE", REG_MMIO, 0x1c6e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_MODE", REG_MMIO, 0x1c78, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_INDEX", REG_MMIO, 0x1c79, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1c7a, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_PWL_DATA", REG_MMIO, 0x1c7b, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_30_COLOR", REG_MMIO, 0x1c7c, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1c7d, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1c7e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_AUTOFILL", REG_MMIO, 0x1c7f, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_CONTROL", REG_MMIO, 0x1c80, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1c81, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1c82, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1c83, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1c84, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1c85, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1c86, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CONTROL", REG_MMIO, 0x1c87, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_MASK", REG_MMIO, 0x1c88, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CURRENT", REG_MMIO, 0x1c89, NULL, 0, 0, 0 },
+	{ "mmDCP1_DVMM_PTE_CONTROL", REG_MMIO, 0x1c8a, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_LAST", REG_MMIO, 0x1c8b, NULL, 0, 0, 0 },
+	{ "mmDCP1_DVMM_PTE_ARB_CONTROL", REG_MMIO, 0x1c8c, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG", REG_MMIO, 0x1c8d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1c8e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_GSL_CONTROL", REG_MMIO, 0x1c90, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1c91, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG_SG", REG_MMIO, 0x1c92, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DVMM_DEBUG", REG_MMIO, 0x1c93, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG_SG2", REG_MMIO, 0x1c94, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1c95, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1c96, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1c97, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG2", REG_MMIO, 0x1c98, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1c99, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_STEREO_CONTROL", REG_MMIO, 0x1c9a, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1c9c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1c9d, NULL, 0, 0, 0 },
+	{ "mmDCP1_HW_ROTATION", REG_MMIO, 0x1c9e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1c9f, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CONTROL", REG_MMIO, 0x1ca0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_INDEX", REG_MMIO, 0x1ca1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_DATA", REG_MMIO, 0x1ca2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1ca3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1ca4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1ca5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1ca6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1ca7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1ca8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1ca9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1caa, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1cab, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1cac, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1cad, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1cae, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1caf, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1cb0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1cb1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1cb2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1cb3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1cb4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1cb5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1cb6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1cb7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1cb8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1cb9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1cba, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1cbb, NULL, 0, 0, 0 },
+	{ "mmDCP1_ALPHA_CONTROL", REG_MMIO, 0x1cbc, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1cbd, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1cbe, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1cbf, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DATA_FORMAT", REG_MMIO, 0x1cc0, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_MEMORY_CTRL", REG_MMIO, 0x1cc1, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1cc2, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1cc3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE_START_END", REG_MMIO, 0x1cc4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE2_START_END", REG_MMIO, 0x1cc5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_V_COUNTER", REG_MMIO, 0x1cc6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1cc7, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_INTERRUPT_MASK", REG_MMIO, 0x1cc8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE_STATUS", REG_MMIO, 0x1cc9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE2_STATUS", REG_MMIO, 0x1cca, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VBLANK_STATUS", REG_MMIO, 0x1ccb, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SYNC_RESET_SEL", REG_MMIO, 0x1ccc, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1ccd, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1cce, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1ccf, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1cd0, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1cd1, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1cd2, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1cd3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1cd4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1cd5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1cd6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1cd7, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1cd8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1cd9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_STATUS", REG_MMIO, 0x1cda, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1cdc, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ce0, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ce1, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ce2, NULL, 0, 0, 0 },
+	{ "mmLB1_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ce3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG", REG_MMIO, 0x1ce4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG2", REG_MMIO, 0x1ce5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG3", REG_MMIO, 0x1ce6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1cfe, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1cff, NULL, 0, 0, 0 },
+	{ "mmDMA_POSITION_UPPER_BASE_ADDRESS", REG_MMIO, 0x1d, &mmDMA_POSITION_UPPER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_N", REG_SMC, 0x1d, &ixDP_AUX_DEBUG_N[0], sizeof(ixDP_AUX_DEBUG_N)/sizeof(ixDP_AUX_DEBUG_N[0]), 0, 0 },
+	{ "mmDCFE1_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1d00, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_SOFT_RESET", REG_MMIO, 0x1d01, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_DBG_CONFIG", REG_MMIO, 0x1d02, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1d03, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1d04, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1d05, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_MISC", REG_MMIO, 0x1d06, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFCOUNTER_CNTL", REG_MMIO, 0x1d24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFCOUNTER_STATE", REG_MMIO, 0x1d25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1d26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CNTL", REG_MMIO, 0x1d27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CVALUE_LOW", REG_MMIO, 0x1d28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_HI", REG_MMIO, 0x1d29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_LOW", REG_MMIO, 0x1d2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1d2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1d2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CNTL2", REG_MMIO, 0x1d2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1d30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1d31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1d32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1d33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1d34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1d35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1d36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1d37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1d38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1d39, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1d3a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_A", REG_MMIO, 0x1d3b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_B", REG_MMIO, 0x1d3c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_11", REG_MMIO, 0x1d3d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x1d3e, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1d40, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1d41, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE", REG_MMIO, 0x1d42, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TAP_CONTROL", REG_MMIO, 0x1d43, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_CONTROL", REG_MMIO, 0x1d44, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_BYPASS_CONTROL", REG_MMIO, 0x1d45, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1d46, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1d47, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1d48, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1d49, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1d4a, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1d4b, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1d4c, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1d4d, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1d4e, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ROUND_OFFSET", REG_MMIO, 0x1d4f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_UPDATE", REG_MMIO, 0x1d51, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1d53, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ALU_CONTROL", REG_MMIO, 0x1d54, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1d55, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1d5b, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_START", REG_MMIO, 0x1d5c, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_SIZE", REG_MMIO, 0x1d5d, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1d5e, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1d5f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1d60, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1d61, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1d62, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1d63, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG2", REG_MMIO, 0x1d69, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG", REG_MMIO, 0x1d6a, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1d6b, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1d6c, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_CONTROL", REG_MMIO, 0x1d6d, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_SM_CONTROL2", REG_MMIO, 0x1d6e, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_CONTROL2", REG_MMIO, 0x1d6f, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_UPDATE", REG_MMIO, 0x1d70, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1d71, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1d73, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_DEBUG", REG_MMIO, 0x1d74, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1d75, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1d76, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1d77, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1d78, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1d79, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_WINDOW", REG_MMIO, 0x1d7a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_CONTROL", REG_MMIO, 0x1d7b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1d7d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_TOTAL", REG_MMIO, 0x1d80, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_START_END", REG_MMIO, 0x1d81, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A", REG_MMIO, 0x1d82, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1d83, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B", REG_MMIO, 0x1d84, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1d85, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VBI_END", REG_MMIO, 0x1d86, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL", REG_MMIO, 0x1d87, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1d88, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1d89, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1d8a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1d8b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1d8c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_BLANK_START_END", REG_MMIO, 0x1d8d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A", REG_MMIO, 0x1d8e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1d8f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B", REG_MMIO, 0x1d90, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1d91, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1d92, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1d93, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_CNTL", REG_MMIO, 0x1d94, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1d95, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_CNTL", REG_MMIO, 0x1d96, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1d97, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1d98, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FLOW_CONTROL", REG_MMIO, 0x1d99, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1d9a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1d9b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CONTROL", REG_MMIO, 0x1d9c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_CONTROL", REG_MMIO, 0x1d9d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1d9e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1d9f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1da0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1da1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1da2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS", REG_MMIO, 0x1da3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_POSITION", REG_MMIO, 0x1da4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1da5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1da6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1da7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1da8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_CONTROL", REG_MMIO, 0x1da9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_RESET", REG_MMIO, 0x1daa, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1dab, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1dac, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_STATUS", REG_MMIO, 0x1dad, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_CONTROL", REG_MMIO, 0x1dae, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1daf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1db0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1db1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1db2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1db3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1db4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_UPDATE_LOCK", REG_MMIO, 0x1db5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1db6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1db7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1dba, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1dbb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1dbc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x1dbd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x1dbe, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1dbf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1dc0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_STATUS", REG_MMIO, 0x1dc1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_EN", REG_MMIO, 0x1dc2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1dc3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1dc4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1dc6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1dc7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1dc8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1dc9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1dca, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1dcb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR", REG_MMIO, 0x1dcc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1dcd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1dce, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1dcf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1dd0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1dd1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1dd2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1dd3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC_CNTL", REG_MMIO, 0x1dd4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1dd5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1dd6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1dd7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1dd8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1dd9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_DATA_B", REG_MMIO, 0x1dda, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1ddb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1ddc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1ddd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1dde, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1ddf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_DATA_B", REG_MMIO, 0x1de0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1de7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1de8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1de9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1dea, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1deb, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1dec, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1ded, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CONTROL", REG_MMIO, 0x1dee, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1df2, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1df3, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1df4, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1df5, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1df6, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1df7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1df8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_CNTL", REG_MMIO, 0x1df9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_CNTL", REG_MMIO, 0x1dfa, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1dfb, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1dfc, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1dfd, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1dfe, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DEBUG_CNTL", REG_MMIO, 0x1dff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX_DEBUG_O", REG_SMC, 0x1e, &ixDP_AUX_DEBUG_O[0], sizeof(ixDP_AUX_DEBUG_O)/sizeof(ixDP_AUX_DEBUG_O[0]), 0, 0 },
+	{ "ixCRT1E", REG_SMC, 0x1e, &ixCRT1E[0], sizeof(ixCRT1E)/sizeof(ixCRT1E[0]), 0, 0 },
+	{ "mmDCP2_GRPH_ENABLE", REG_MMIO, 0x1e00, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_CONTROL", REG_MMIO, 0x1e01, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1e02, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SWAP_CNTL", REG_MMIO, 0x1e03, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1e04, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1e05, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PITCH", REG_MMIO, 0x1e06, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e07, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e08, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1e09, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1e0a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_START", REG_MMIO, 0x1e0b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_START", REG_MMIO, 0x1e0c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_END", REG_MMIO, 0x1e0d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_END", REG_MMIO, 0x1e0e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x1e0f, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1e10, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_UPDATE", REG_MMIO, 0x1e11, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_CONTROL", REG_MMIO, 0x1e12, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1e13, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_CONTROL", REG_MMIO, 0x1e14, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_STATUS", REG_MMIO, 0x1e15, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1e16, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1e17, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1e18, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1e19, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1e1a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e1b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x1e1c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x1e1d, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1e2d, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1e2e, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1e2f, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1e30, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_CONTROL", REG_MMIO, 0x1e35, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C11_C12", REG_MMIO, 0x1e36, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C13_C14", REG_MMIO, 0x1e37, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C21_C22", REG_MMIO, 0x1e38, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C23_C24", REG_MMIO, 0x1e39, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C31_C32", REG_MMIO, 0x1e3a, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C33_C34", REG_MMIO, 0x1e3b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1e3c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1e3d, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1e3e, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1e3f, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1e40, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1e41, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1e42, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1e43, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1e44, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1e45, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1e46, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1e47, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1e48, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1e49, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1e4a, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1e4b, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1e4c, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1e4d, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1e4e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DENORM_CONTROL", REG_MMIO, 0x1e50, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_ROUND_CONTROL", REG_MMIO, 0x1e51, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1e52, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_CONTROL", REG_MMIO, 0x1e53, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_ALPHA", REG_MMIO, 0x1e54, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_RED", REG_MMIO, 0x1e55, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_GREEN", REG_MMIO, 0x1e56, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_BLUE", REG_MMIO, 0x1e57, NULL, 0, 0, 0 },
+	{ "mmDCP2_DEGAMMA_CONTROL", REG_MMIO, 0x1e58, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1e59, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1e5a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1e5b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1e5c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1e5d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1e5e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1e5f, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1e60, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1e65, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_CONTROL", REG_MMIO, 0x1e66, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1e67, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SIZE", REG_MMIO, 0x1e68, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e69, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_POSITION", REG_MMIO, 0x1e6a, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_HOT_SPOT", REG_MMIO, 0x1e6b, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR1", REG_MMIO, 0x1e6c, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR2", REG_MMIO, 0x1e6d, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_UPDATE", REG_MMIO, 0x1e6e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_MODE", REG_MMIO, 0x1e78, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_INDEX", REG_MMIO, 0x1e79, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1e7a, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_PWL_DATA", REG_MMIO, 0x1e7b, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_30_COLOR", REG_MMIO, 0x1e7c, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1e7d, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1e7e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_AUTOFILL", REG_MMIO, 0x1e7f, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_CONTROL", REG_MMIO, 0x1e80, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1e81, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1e82, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1e83, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1e84, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1e85, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1e86, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CONTROL", REG_MMIO, 0x1e87, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_MASK", REG_MMIO, 0x1e88, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CURRENT", REG_MMIO, 0x1e89, NULL, 0, 0, 0 },
+	{ "mmDCP2_DVMM_PTE_CONTROL", REG_MMIO, 0x1e8a, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_LAST", REG_MMIO, 0x1e8b, NULL, 0, 0, 0 },
+	{ "mmDCP2_DVMM_PTE_ARB_CONTROL", REG_MMIO, 0x1e8c, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG", REG_MMIO, 0x1e8d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1e8e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_GSL_CONTROL", REG_MMIO, 0x1e90, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1e91, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG_SG", REG_MMIO, 0x1e92, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DVMM_DEBUG", REG_MMIO, 0x1e93, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG_SG2", REG_MMIO, 0x1e94, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1e95, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1e96, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1e97, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG2", REG_MMIO, 0x1e98, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1e99, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_STEREO_CONTROL", REG_MMIO, 0x1e9a, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1e9c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1e9d, NULL, 0, 0, 0 },
+	{ "mmDCP2_HW_ROTATION", REG_MMIO, 0x1e9e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1e9f, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CONTROL", REG_MMIO, 0x1ea0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_INDEX", REG_MMIO, 0x1ea1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_DATA", REG_MMIO, 0x1ea2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1ea3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1ea4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1ea5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1ea6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1ea7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1ea8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1ea9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1eaa, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1eab, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1eac, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1ead, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1eae, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1eaf, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1eb0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1eb1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1eb2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1eb3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1eb4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1eb5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1eb6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1eb7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1eb8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1eb9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1eba, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1ebb, NULL, 0, 0, 0 },
+	{ "mmDCP2_ALPHA_CONTROL", REG_MMIO, 0x1ebc, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1ebd, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1ebe, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1ebf, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DATA_FORMAT", REG_MMIO, 0x1ec0, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_MEMORY_CTRL", REG_MMIO, 0x1ec1, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ec2, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1ec3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE_START_END", REG_MMIO, 0x1ec4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE2_START_END", REG_MMIO, 0x1ec5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_V_COUNTER", REG_MMIO, 0x1ec6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ec7, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_INTERRUPT_MASK", REG_MMIO, 0x1ec8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE_STATUS", REG_MMIO, 0x1ec9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE2_STATUS", REG_MMIO, 0x1eca, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VBLANK_STATUS", REG_MMIO, 0x1ecb, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SYNC_RESET_SEL", REG_MMIO, 0x1ecc, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1ecd, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ece, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1ecf, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ed0, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ed1, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ed2, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ed3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ed4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ed5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ed6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ed7, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ed8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ed9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_STATUS", REG_MMIO, 0x1eda, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1edc, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ee0, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ee1, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ee2, NULL, 0, 0, 0 },
+	{ "mmLB2_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ee3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG", REG_MMIO, 0x1ee4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG2", REG_MMIO, 0x1ee5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG3", REG_MMIO, 0x1ee6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1efe, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1eff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX_DEBUG_P", REG_SMC, 0x1f, &ixDP_AUX_DEBUG_P[0], sizeof(ixDP_AUX_DEBUG_P)/sizeof(ixDP_AUX_DEBUG_P[0]), 0, 0 },
+	{ "ixCRT1F", REG_SMC, 0x1f, &ixCRT1F[0], sizeof(ixCRT1F)/sizeof(ixCRT1F[0]), 0, 0 },
+	{ "mmDCFE2_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1f00, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_SOFT_RESET", REG_MMIO, 0x1f01, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_DBG_CONFIG", REG_MMIO, 0x1f02, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1f03, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0x1f04, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "mmDCFE2_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1f04, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_SMC, 0x1f05, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmDCFE2_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1f05, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_MISC", REG_MMIO, 0x1f06, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x1f0a, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_SMC, 0x1f0b, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_SMC, 0x1f0f, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmDC_PERFMON5_PERFCOUNTER_CNTL", REG_MMIO, 0x1f24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFCOUNTER_STATE", REG_MMIO, 0x1f25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1f26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CNTL", REG_MMIO, 0x1f27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CVALUE_LOW", REG_MMIO, 0x1f28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_HI", REG_MMIO, 0x1f29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_LOW", REG_MMIO, 0x1f2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1f2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1f2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CNTL2", REG_MMIO, 0x1f2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1f30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1f31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1f32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1f33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1f34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1f35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1f36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1f37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1f38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1f39, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1f3a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_A", REG_MMIO, 0x1f3b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_B", REG_MMIO, 0x1f3c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_11", REG_MMIO, 0x1f3d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x1f3e, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1f40, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1f41, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE", REG_MMIO, 0x1f42, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TAP_CONTROL", REG_MMIO, 0x1f43, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_CONTROL", REG_MMIO, 0x1f44, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_BYPASS_CONTROL", REG_MMIO, 0x1f45, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1f46, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1f47, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1f48, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1f49, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1f4a, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1f4b, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1f4c, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1f4d, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1f4e, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ROUND_OFFSET", REG_MMIO, 0x1f4f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_UPDATE", REG_MMIO, 0x1f51, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1f53, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ALU_CONTROL", REG_MMIO, 0x1f54, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1f55, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1f5b, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_START", REG_MMIO, 0x1f5c, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_SIZE", REG_MMIO, 0x1f5d, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1f5e, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1f5f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1f60, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1f61, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1f62, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1f63, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG2", REG_MMIO, 0x1f69, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG", REG_MMIO, 0x1f6a, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1f6b, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1f6c, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_CONTROL", REG_MMIO, 0x1f6d, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_SM_CONTROL2", REG_MMIO, 0x1f6e, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_CONTROL2", REG_MMIO, 0x1f6f, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_UPDATE", REG_MMIO, 0x1f70, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1f71, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1f73, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_DEBUG", REG_MMIO, 0x1f74, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1f75, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1f76, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1f77, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1f78, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1f79, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_WINDOW", REG_MMIO, 0x1f7a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_CONTROL", REG_MMIO, 0x1f7b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1f7d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_TOTAL", REG_MMIO, 0x1f80, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_START_END", REG_MMIO, 0x1f81, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A", REG_MMIO, 0x1f82, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1f83, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B", REG_MMIO, 0x1f84, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1f85, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VBI_END", REG_MMIO, 0x1f86, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL", REG_MMIO, 0x1f87, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1f88, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1f89, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1f8a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1f8b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1f8c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_BLANK_START_END", REG_MMIO, 0x1f8d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A", REG_MMIO, 0x1f8e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1f8f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B", REG_MMIO, 0x1f90, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1f91, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1f92, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1f93, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_CNTL", REG_MMIO, 0x1f94, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1f95, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_CNTL", REG_MMIO, 0x1f96, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1f97, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1f98, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FLOW_CONTROL", REG_MMIO, 0x1f99, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1f9a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1f9b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CONTROL", REG_MMIO, 0x1f9c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_CONTROL", REG_MMIO, 0x1f9d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1f9e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1f9f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1fa0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1fa1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1fa2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS", REG_MMIO, 0x1fa3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_POSITION", REG_MMIO, 0x1fa4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1fa5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1fa6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1fa7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1fa8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_CONTROL", REG_MMIO, 0x1fa9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_RESET", REG_MMIO, 0x1faa, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1fab, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1fac, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_STATUS", REG_MMIO, 0x1fad, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_CONTROL", REG_MMIO, 0x1fae, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1faf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1fb0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1fb1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1fb2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1fb3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1fb4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_UPDATE_LOCK", REG_MMIO, 0x1fb5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1fb6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1fb7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1fba, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1fbb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1fbc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x1fbd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x1fbe, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1fbf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1fc0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_STATUS", REG_MMIO, 0x1fc1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_EN", REG_MMIO, 0x1fc2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1fc3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1fc4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1fc6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1fc7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1fc8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1fc9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1fca, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1fcb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR", REG_MMIO, 0x1fcc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1fcd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1fce, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1fcf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1fd0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1fd1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1fd2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1fd3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC_CNTL", REG_MMIO, 0x1fd4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1fd5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1fd6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1fd7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1fd8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1fd9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_DATA_B", REG_MMIO, 0x1fda, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1fdb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1fdc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1fdd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1fde, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1fdf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_DATA_B", REG_MMIO, 0x1fe0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1fe7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1fe8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1fe9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1fea, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1feb, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1fec, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1fed, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CONTROL", REG_MMIO, 0x1fee, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1ff2, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1ff3, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1ff4, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1ff5, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1ff6, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1ff7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1ff8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_CNTL", REG_MMIO, 0x1ff9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_CNTL", REG_MMIO, 0x1ffa, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1ffb, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1ffc, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1ffd, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1ffe, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DEBUG_CNTL", REG_MMIO, 0x1fff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN", REG_SMC, 0x2, &ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0]), 0, 0 },
+	{ "ixAZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x2, &ixAZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL2", REG_SMC, 0x2, &ixAZALIA_INPUT_CRC0_CHANNEL2[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL2)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL2[0]), 0, 0 },
+	{ "ixDPGV0_DEBUG01_DMIFARB", REG_SMC, 0x2, NULL, 0, 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL2", REG_SMC, 0x2, &ixAZALIA_CRC0_CHANNEL2[0], sizeof(ixAZALIA_CRC0_CHANNEL2)/sizeof(ixAZALIA_CRC0_CHANNEL2[0]), 0, 0 },
+	{ "ixDMIF_DEBUG02_CORE0", REG_SMC, 0x2, &ixDMIF_DEBUG02_CORE0[0], sizeof(ixDMIF_DEBUG02_CORE0)/sizeof(ixDMIF_DEBUG02_CORE0[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR1", REG_SMC, 0x2, &ixAUDIO_DESCRIPTOR1[0], sizeof(ixAUDIO_DESCRIPTOR1)/sizeof(ixAUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "mmGLOBAL_CONTROL", REG_MMIO, 0x2, &mmGLOBAL_CONTROL[0], sizeof(mmGLOBAL_CONTROL)/sizeof(mmGLOBAL_CONTROL[0]), 0, 0 },
+	{ "ixDCIO_DEBUG2", REG_SMC, 0x2, &ixDCIO_DEBUG2[0], sizeof(ixDCIO_DEBUG2)/sizeof(ixDCIO_DEBUG2[0]), 0, 0 },
+	{ "ixFMT_DEBUG1", REG_SMC, 0x2, &ixFMT_DEBUG1[0], sizeof(ixFMT_DEBUG1)/sizeof(ixFMT_DEBUG1[0]), 0, 0 },
+	{ "ixATTR02", REG_SMC, 0x2, &ixATTR02[0], sizeof(ixATTR02)/sizeof(ixATTR02[0]), 0, 0 },
+	{ "ixSEQ02", REG_SMC, 0x2, &ixSEQ02[0], sizeof(ixSEQ02)/sizeof(ixSEQ02[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x20, &ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x20, &ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x20, &mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_Q", REG_SMC, 0x20, &ixDP_AUX_DEBUG_Q[0], sizeof(ixDP_AUX_DEBUG_Q)/sizeof(ixDP_AUX_DEBUG_Q[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x21, &mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x21, &ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x21, &ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x22, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x22, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x22, &mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 },
+	{ "ixCRT22", REG_SMC, 0x22, &ixCRT22[0], sizeof(ixCRT22)/sizeof(ixCRT22[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2200, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x23, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x23, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x23, &mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x24, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x24, &ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x24, &mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x24, &mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x25, &ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x26, &mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x27, &mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x2706, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x270d, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2", REG_SMC, 0x270e, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x2724, &ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3", REG_SMC, 0x273e, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x2770, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x2771, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x28, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "mmFBC_CNTL", REG_MMIO, 0x280, &mmFBC_CNTL[0], sizeof(mmFBC_CNTL)/sizeof(mmFBC_CNTL[0]), 0, 0 },
+	{ "mmFBC_IDLE_MASK", REG_MMIO, 0x281, &mmFBC_IDLE_MASK[0], sizeof(mmFBC_IDLE_MASK)/sizeof(mmFBC_IDLE_MASK[0]), 0, 0 },
+	{ "mmFBC_IDLE_FORCE_CLEAR_MASK", REG_MMIO, 0x282, &mmFBC_IDLE_FORCE_CLEAR_MASK[0], sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK)/sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK[0]), 0, 0 },
+	{ "mmFBC_START_STOP_DELAY", REG_MMIO, 0x283, &mmFBC_START_STOP_DELAY[0], sizeof(mmFBC_START_STOP_DELAY)/sizeof(mmFBC_START_STOP_DELAY[0]), 0, 0 },
+	{ "mmFBC_COMP_CNTL", REG_MMIO, 0x284, &mmFBC_COMP_CNTL[0], sizeof(mmFBC_COMP_CNTL)/sizeof(mmFBC_COMP_CNTL[0]), 0, 0 },
+	{ "mmFBC_COMP_MODE", REG_MMIO, 0x285, &mmFBC_COMP_MODE[0], sizeof(mmFBC_COMP_MODE)/sizeof(mmFBC_COMP_MODE[0]), 0, 0 },
+	{ "mmFBC_DEBUG0", REG_MMIO, 0x286, &mmFBC_DEBUG0[0], sizeof(mmFBC_DEBUG0)/sizeof(mmFBC_DEBUG0[0]), 0, 0 },
+	{ "mmFBC_DEBUG1", REG_MMIO, 0x287, &mmFBC_DEBUG1[0], sizeof(mmFBC_DEBUG1)/sizeof(mmFBC_DEBUG1[0]), 0, 0 },
+	{ "mmFBC_DEBUG2", REG_MMIO, 0x288, &mmFBC_DEBUG2[0], sizeof(mmFBC_DEBUG2)/sizeof(mmFBC_DEBUG2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT0", REG_MMIO, 0x289, &mmFBC_IND_LUT0[0], sizeof(mmFBC_IND_LUT0)/sizeof(mmFBC_IND_LUT0[0]), 0, 0 },
+	{ "mmFBC_IND_LUT1", REG_MMIO, 0x28a, &mmFBC_IND_LUT1[0], sizeof(mmFBC_IND_LUT1)/sizeof(mmFBC_IND_LUT1[0]), 0, 0 },
+	{ "mmFBC_IND_LUT2", REG_MMIO, 0x28b, &mmFBC_IND_LUT2[0], sizeof(mmFBC_IND_LUT2)/sizeof(mmFBC_IND_LUT2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT3", REG_MMIO, 0x28c, &mmFBC_IND_LUT3[0], sizeof(mmFBC_IND_LUT3)/sizeof(mmFBC_IND_LUT3[0]), 0, 0 },
+	{ "mmFBC_IND_LUT4", REG_MMIO, 0x28d, &mmFBC_IND_LUT4[0], sizeof(mmFBC_IND_LUT4)/sizeof(mmFBC_IND_LUT4[0]), 0, 0 },
+	{ "mmFBC_IND_LUT5", REG_MMIO, 0x28e, &mmFBC_IND_LUT5[0], sizeof(mmFBC_IND_LUT5)/sizeof(mmFBC_IND_LUT5[0]), 0, 0 },
+	{ "mmFBC_IND_LUT6", REG_MMIO, 0x28f, &mmFBC_IND_LUT6[0], sizeof(mmFBC_IND_LUT6)/sizeof(mmFBC_IND_LUT6[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x29, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "mmFBC_IND_LUT7", REG_MMIO, 0x290, &mmFBC_IND_LUT7[0], sizeof(mmFBC_IND_LUT7)/sizeof(mmFBC_IND_LUT7[0]), 0, 0 },
+	{ "mmFBC_IND_LUT8", REG_MMIO, 0x291, &mmFBC_IND_LUT8[0], sizeof(mmFBC_IND_LUT8)/sizeof(mmFBC_IND_LUT8[0]), 0, 0 },
+	{ "mmFBC_IND_LUT9", REG_MMIO, 0x292, &mmFBC_IND_LUT9[0], sizeof(mmFBC_IND_LUT9)/sizeof(mmFBC_IND_LUT9[0]), 0, 0 },
+	{ "mmFBC_IND_LUT10", REG_MMIO, 0x293, &mmFBC_IND_LUT10[0], sizeof(mmFBC_IND_LUT10)/sizeof(mmFBC_IND_LUT10[0]), 0, 0 },
+	{ "mmFBC_IND_LUT11", REG_MMIO, 0x294, &mmFBC_IND_LUT11[0], sizeof(mmFBC_IND_LUT11)/sizeof(mmFBC_IND_LUT11[0]), 0, 0 },
+	{ "mmFBC_IND_LUT12", REG_MMIO, 0x295, &mmFBC_IND_LUT12[0], sizeof(mmFBC_IND_LUT12)/sizeof(mmFBC_IND_LUT12[0]), 0, 0 },
+	{ "mmFBC_IND_LUT13", REG_MMIO, 0x296, &mmFBC_IND_LUT13[0], sizeof(mmFBC_IND_LUT13)/sizeof(mmFBC_IND_LUT13[0]), 0, 0 },
+	{ "mmFBC_IND_LUT14", REG_MMIO, 0x297, &mmFBC_IND_LUT14[0], sizeof(mmFBC_IND_LUT14)/sizeof(mmFBC_IND_LUT14[0]), 0, 0 },
+	{ "mmFBC_IND_LUT15", REG_MMIO, 0x298, &mmFBC_IND_LUT15[0], sizeof(mmFBC_IND_LUT15)/sizeof(mmFBC_IND_LUT15[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_01", REG_MMIO, 0x299, &mmFBC_CSM_REGION_OFFSET_01[0], sizeof(mmFBC_CSM_REGION_OFFSET_01)/sizeof(mmFBC_CSM_REGION_OFFSET_01[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_23", REG_MMIO, 0x29a, &mmFBC_CSM_REGION_OFFSET_23[0], sizeof(mmFBC_CSM_REGION_OFFSET_23)/sizeof(mmFBC_CSM_REGION_OFFSET_23[0]), 0, 0 },
+	{ "mmFBC_CLIENT_REGION_MASK", REG_MMIO, 0x29b, &mmFBC_CLIENT_REGION_MASK[0], sizeof(mmFBC_CLIENT_REGION_MASK)/sizeof(mmFBC_CLIENT_REGION_MASK[0]), 0, 0 },
+	{ "mmFBC_DEBUG_COMP", REG_MMIO, 0x29c, &mmFBC_DEBUG_COMP[0], sizeof(mmFBC_DEBUG_COMP)/sizeof(mmFBC_DEBUG_COMP[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR", REG_MMIO, 0x29d, &mmFBC_DEBUG_CSR[0], sizeof(mmFBC_DEBUG_CSR)/sizeof(mmFBC_DEBUG_CSR[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA", REG_MMIO, 0x29e, &mmFBC_DEBUG_CSR_RDATA[0], sizeof(mmFBC_DEBUG_CSR_RDATA)/sizeof(mmFBC_DEBUG_CSR_RDATA[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA", REG_MMIO, 0x29f, &mmFBC_DEBUG_CSR_WDATA[0], sizeof(mmFBC_DEBUG_CSR_WDATA)/sizeof(mmFBC_DEBUG_CSR_WDATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x2a, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA_HI", REG_MMIO, 0x2a0, &mmFBC_DEBUG_CSR_RDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_RDATA_HI)/sizeof(mmFBC_DEBUG_CSR_RDATA_HI[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA_HI", REG_MMIO, 0x2a1, &mmFBC_DEBUG_CSR_WDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_WDATA_HI)/sizeof(mmFBC_DEBUG_CSR_WDATA_HI[0]), 0, 0 },
+	{ "mmFBC_MISC", REG_MMIO, 0x2a2, &mmFBC_MISC[0], sizeof(mmFBC_MISC)/sizeof(mmFBC_MISC[0]), 0, 0 },
+	{ "mmFBC_STATUS", REG_MMIO, 0x2a3, &mmFBC_STATUS[0], sizeof(mmFBC_STATUS)/sizeof(mmFBC_STATUS[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_INDEX", REG_MMIO, 0x2a4, &mmFBC_TEST_DEBUG_INDEX[0], sizeof(mmFBC_TEST_DEBUG_INDEX)/sizeof(mmFBC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_DATA", REG_MMIO, 0x2a5, &mmFBC_TEST_DEBUG_DATA[0], sizeof(mmFBC_TEST_DEBUG_DATA)/sizeof(mmFBC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMVP_CONTROL1", REG_MMIO, 0x2ac, &mmMVP_CONTROL1[0], sizeof(mmMVP_CONTROL1)/sizeof(mmMVP_CONTROL1[0]), 0, 0 },
+	{ "mmMVP_CONTROL2", REG_MMIO, 0x2ad, &mmMVP_CONTROL2[0], sizeof(mmMVP_CONTROL2)/sizeof(mmMVP_CONTROL2[0]), 0, 0 },
+	{ "mmMVP_FIFO_CONTROL", REG_MMIO, 0x2ae, &mmMVP_FIFO_CONTROL[0], sizeof(mmMVP_FIFO_CONTROL)/sizeof(mmMVP_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmMVP_FIFO_STATUS", REG_MMIO, 0x2af, &mmMVP_FIFO_STATUS[0], sizeof(mmMVP_FIFO_STATUS)/sizeof(mmMVP_FIFO_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x2b, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "mmMVP_SLAVE_STATUS", REG_MMIO, 0x2b0, &mmMVP_SLAVE_STATUS[0], sizeof(mmMVP_SLAVE_STATUS)/sizeof(mmMVP_SLAVE_STATUS[0]), 0, 0 },
+	{ "mmMVP_INBAND_CNTL_CAP", REG_MMIO, 0x2b1, &mmMVP_INBAND_CNTL_CAP[0], sizeof(mmMVP_INBAND_CNTL_CAP)/sizeof(mmMVP_INBAND_CNTL_CAP[0]), 0, 0 },
+	{ "mmMVP_BLACK_KEYER", REG_MMIO, 0x2b2, &mmMVP_BLACK_KEYER[0], sizeof(mmMVP_BLACK_KEYER)/sizeof(mmMVP_BLACK_KEYER[0]), 0, 0 },
+	{ "mmMVP_CRC_CNTL", REG_MMIO, 0x2b3, &mmMVP_CRC_CNTL[0], sizeof(mmMVP_CRC_CNTL)/sizeof(mmMVP_CRC_CNTL[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_BLUE_GREEN", REG_MMIO, 0x2b4, &mmMVP_CRC_RESULT_BLUE_GREEN[0], sizeof(mmMVP_CRC_RESULT_BLUE_GREEN)/sizeof(mmMVP_CRC_RESULT_BLUE_GREEN[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_RED", REG_MMIO, 0x2b5, &mmMVP_CRC_RESULT_RED[0], sizeof(mmMVP_CRC_RESULT_RED)/sizeof(mmMVP_CRC_RESULT_RED[0]), 0, 0 },
+	{ "mmMVP_CONTROL3", REG_MMIO, 0x2b6, &mmMVP_CONTROL3[0], sizeof(mmMVP_CONTROL3)/sizeof(mmMVP_CONTROL3[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL1", REG_MMIO, 0x2b7, &mmMVP_RECEIVE_CNT_CNTL1[0], sizeof(mmMVP_RECEIVE_CNT_CNTL1)/sizeof(mmMVP_RECEIVE_CNT_CNTL1[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL2", REG_MMIO, 0x2b8, &mmMVP_RECEIVE_CNT_CNTL2[0], sizeof(mmMVP_RECEIVE_CNT_CNTL2)/sizeof(mmMVP_RECEIVE_CNT_CNTL2[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_INDEX", REG_MMIO, 0x2b9, &mmMVP_TEST_DEBUG_INDEX[0], sizeof(mmMVP_TEST_DEBUG_INDEX)/sizeof(mmMVP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_DATA", REG_MMIO, 0x2ba, &mmMVP_TEST_DEBUG_DATA[0], sizeof(mmMVP_TEST_DEBUG_DATA)/sizeof(mmMVP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMVP_DEBUG", REG_MMIO, 0x2bb, &mmMVP_DEBUG[0], sizeof(mmMVP_DEBUG)/sizeof(mmMVP_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x2c, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "mmPIPE0_PG_CONFIG", REG_MMIO, 0x2c0, &mmPIPE0_PG_CONFIG[0], sizeof(mmPIPE0_PG_CONFIG)/sizeof(mmPIPE0_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE0_PG_ENABLE", REG_MMIO, 0x2c1, &mmPIPE0_PG_ENABLE[0], sizeof(mmPIPE0_PG_ENABLE)/sizeof(mmPIPE0_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE0_PG_STATUS", REG_MMIO, 0x2c2, &mmPIPE0_PG_STATUS[0], sizeof(mmPIPE0_PG_STATUS)/sizeof(mmPIPE0_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE1_PG_CONFIG", REG_MMIO, 0x2c3, &mmPIPE1_PG_CONFIG[0], sizeof(mmPIPE1_PG_CONFIG)/sizeof(mmPIPE1_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE1_PG_ENABLE", REG_MMIO, 0x2c4, &mmPIPE1_PG_ENABLE[0], sizeof(mmPIPE1_PG_ENABLE)/sizeof(mmPIPE1_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE1_PG_STATUS", REG_MMIO, 0x2c5, &mmPIPE1_PG_STATUS[0], sizeof(mmPIPE1_PG_STATUS)/sizeof(mmPIPE1_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE2_PG_CONFIG", REG_MMIO, 0x2c6, &mmPIPE2_PG_CONFIG[0], sizeof(mmPIPE2_PG_CONFIG)/sizeof(mmPIPE2_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE2_PG_ENABLE", REG_MMIO, 0x2c7, &mmPIPE2_PG_ENABLE[0], sizeof(mmPIPE2_PG_ENABLE)/sizeof(mmPIPE2_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE2_PG_STATUS", REG_MMIO, 0x2c8, &mmPIPE2_PG_STATUS[0], sizeof(mmPIPE2_PG_STATUS)/sizeof(mmPIPE2_PG_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x2d, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "mmDC_IP_REQUEST_CNTL", REG_MMIO, 0x2d2, &mmDC_IP_REQUEST_CNTL[0], sizeof(mmDC_IP_REQUEST_CNTL)/sizeof(mmDC_IP_REQUEST_CNTL[0]), 0, 0 },
+	{ "mmDC_PGFSM_CONFIG_REG", REG_MMIO, 0x2d3, &mmDC_PGFSM_CONFIG_REG[0], sizeof(mmDC_PGFSM_CONFIG_REG)/sizeof(mmDC_PGFSM_CONFIG_REG[0]), 0, 0 },
+	{ "mmDC_PGFSM_WRITE_REG", REG_MMIO, 0x2d4, &mmDC_PGFSM_WRITE_REG[0], sizeof(mmDC_PGFSM_WRITE_REG)/sizeof(mmDC_PGFSM_WRITE_REG[0]), 0, 0 },
+	{ "mmDC_PGCNTL_STATUS_REG", REG_MMIO, 0x2d5, &mmDC_PGCNTL_STATUS_REG[0], sizeof(mmDC_PGCNTL_STATUS_REG)/sizeof(mmDC_PGCNTL_STATUS_REG[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_INDEX", REG_MMIO, 0x2d6, &mmDCPG_TEST_DEBUG_INDEX[0], sizeof(mmDCPG_TEST_DEBUG_INDEX)/sizeof(mmDCPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_DATA", REG_MMIO, 0x2d7, &mmDCPG_TEST_DEBUG_DATA[0], sizeof(mmDCPG_TEST_DEBUG_DATA)/sizeof(mmDCPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCFEV0_PG_CONFIG", REG_MMIO, 0x2db, &mmDCFEV0_PG_CONFIG[0], sizeof(mmDCFEV0_PG_CONFIG)/sizeof(mmDCFEV0_PG_CONFIG[0]), 0, 0 },
+	{ "mmDCFEV0_PG_ENABLE", REG_MMIO, 0x2dc, &mmDCFEV0_PG_ENABLE[0], sizeof(mmDCFEV0_PG_ENABLE)/sizeof(mmDCFEV0_PG_ENABLE[0]), 0, 0 },
+	{ "mmDCFEV0_PG_STATUS", REG_MMIO, 0x2dd, &mmDCFEV0_PG_STATUS[0], sizeof(mmDCFEV0_PG_STATUS)/sizeof(mmDCFEV0_PG_STATUS[0]), 0, 0 },
+	{ "mmDCPG_INTERRUPT_STATUS", REG_MMIO, 0x2de, &mmDCPG_INTERRUPT_STATUS[0], sizeof(mmDCPG_INTERRUPT_STATUS)/sizeof(mmDCPG_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDCPG_INTERRUPT_CONTROL", REG_MMIO, 0x2df, &mmDCPG_INTERRUPT_CONTROL[0], sizeof(mmDCPG_INTERRUPT_CONTROL)/sizeof(mmDCPG_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x2e, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x2f, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x2f09, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x2f0a, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x2f0b, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CONFIG", REG_MMIO, 0x2f5, &mmDMIF_ADDR_CONFIG[0], sizeof(mmDMIF_ADDR_CONFIG)/sizeof(mmDMIF_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmDMIF_CONTROL", REG_MMIO, 0x2f6, &mmDMIF_CONTROL[0], sizeof(mmDMIF_CONTROL)/sizeof(mmDMIF_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_STATUS", REG_MMIO, 0x2f7, &mmDMIF_STATUS[0], sizeof(mmDMIF_STATUS)/sizeof(mmDMIF_STATUS[0]), 0, 0 },
+	{ "mmDMIF_HW_DEBUG", REG_MMIO, 0x2f8, &mmDMIF_HW_DEBUG[0], sizeof(mmDMIF_HW_DEBUG)/sizeof(mmDMIF_HW_DEBUG[0]), 0, 0 },
+	{ "mmDMIF_ARBITRATION_CONTROL", REG_MMIO, 0x2f9, &mmDMIF_ARBITRATION_CONTROL[0], sizeof(mmDMIF_ARBITRATION_CONTROL)/sizeof(mmDMIF_ARBITRATION_CONTROL[0]), 0, 0 },
+	{ "mmPIPE0_ARBITRATION_CONTROL3", REG_MMIO, 0x2fa, &mmPIPE0_ARBITRATION_CONTROL3[0], sizeof(mmPIPE0_ARBITRATION_CONTROL3)/sizeof(mmPIPE0_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE1_ARBITRATION_CONTROL3", REG_MMIO, 0x2fb, &mmPIPE1_ARBITRATION_CONTROL3[0], sizeof(mmPIPE1_ARBITRATION_CONTROL3)/sizeof(mmPIPE1_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE2_ARBITRATION_CONTROL3", REG_MMIO, 0x2fc, &mmPIPE2_ARBITRATION_CONTROL3[0], sizeof(mmPIPE2_ARBITRATION_CONTROL3)/sizeof(mmPIPE2_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE3_ARBITRATION_CONTROL3", REG_MMIO, 0x2fd, &mmPIPE3_ARBITRATION_CONTROL3[0], sizeof(mmPIPE3_ARBITRATION_CONTROL3)/sizeof(mmPIPE3_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE4_ARBITRATION_CONTROL3", REG_MMIO, 0x2fe, &mmPIPE4_ARBITRATION_CONTROL3[0], sizeof(mmPIPE4_ARBITRATION_CONTROL3)/sizeof(mmPIPE4_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE5_ARBITRATION_CONTROL3", REG_MMIO, 0x2ff, &mmPIPE5_ARBITRATION_CONTROL3[0], sizeof(mmPIPE5_ARBITRATION_CONTROL3)/sizeof(mmPIPE5_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x3, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x3, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0", REG_SMC, 0x3, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0]), 0, 0 },
+	{ "ixAZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x3, &ixAZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL3", REG_SMC, 0x3, &ixAZALIA_INPUT_CRC0_CHANNEL3[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL3)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL3[0]), 0, 0 },
+	{ "ixDPGV0_DEBUG02_DMIFARB", REG_SMC, 0x3, NULL, 0, 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL3", REG_SMC, 0x3, &ixAZALIA_CRC0_CHANNEL3[0], sizeof(ixAZALIA_CRC0_CHANNEL3)/sizeof(ixAZALIA_CRC0_CHANNEL3[0]), 0, 0 },
+	{ "mmSTATE_CHANGE_STATUS", REG_MMIO, 0x3, &mmSTATE_CHANGE_STATUS[0], sizeof(mmSTATE_CHANGE_STATUS)/sizeof(mmSTATE_CHANGE_STATUS[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR2", REG_SMC, 0x3, &ixAUDIO_DESCRIPTOR2[0], sizeof(ixAUDIO_DESCRIPTOR2)/sizeof(ixAUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "ixDCIO_DEBUG3", REG_SMC, 0x3, &ixDCIO_DEBUG3[0], sizeof(ixDCIO_DEBUG3)/sizeof(ixDCIO_DEBUG3[0]), 0, 0 },
+	{ "ixFMT_DEBUG2", REG_SMC, 0x3, &ixFMT_DEBUG2[0], sizeof(ixFMT_DEBUG2)/sizeof(ixFMT_DEBUG2[0]), 0, 0 },
+	{ "ixATTR03", REG_SMC, 0x3, &ixATTR03[0], sizeof(ixATTR03)/sizeof(ixATTR03[0]), 0, 0 },
+	{ "ixSEQ03", REG_SMC, 0x3, &ixSEQ03[0], sizeof(ixSEQ03)/sizeof(ixSEQ03[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x30, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "mmDMIF_P_VMID", REG_MMIO, 0x300, &mmDMIF_P_VMID[0], sizeof(mmDMIF_P_VMID)/sizeof(mmDMIF_P_VMID[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_INDEX", REG_MMIO, 0x301, &mmDMIF_TEST_DEBUG_INDEX[0], sizeof(mmDMIF_TEST_DEBUG_INDEX)/sizeof(mmDMIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_DATA", REG_MMIO, 0x302, &mmDMIF_TEST_DEBUG_DATA[0], sizeof(mmDMIF_TEST_DEBUG_DATA)/sizeof(mmDMIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CALC", REG_MMIO, 0x303, &mmDMIF_ADDR_CALC[0], sizeof(mmDMIF_ADDR_CALC)/sizeof(mmDMIF_ADDR_CALC[0]), 0, 0 },
+	{ "mmDMIF_STATUS2", REG_MMIO, 0x304, &mmDMIF_STATUS2[0], sizeof(mmDMIF_STATUS2)/sizeof(mmDMIF_STATUS2[0]), 0, 0 },
+	{ "mmPIPE0_MAX_REQUESTS", REG_MMIO, 0x305, &mmPIPE0_MAX_REQUESTS[0], sizeof(mmPIPE0_MAX_REQUESTS)/sizeof(mmPIPE0_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE1_MAX_REQUESTS", REG_MMIO, 0x306, &mmPIPE1_MAX_REQUESTS[0], sizeof(mmPIPE1_MAX_REQUESTS)/sizeof(mmPIPE1_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE2_MAX_REQUESTS", REG_MMIO, 0x307, &mmPIPE2_MAX_REQUESTS[0], sizeof(mmPIPE2_MAX_REQUESTS)/sizeof(mmPIPE2_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE3_MAX_REQUESTS", REG_MMIO, 0x308, &mmPIPE3_MAX_REQUESTS[0], sizeof(mmPIPE3_MAX_REQUESTS)/sizeof(mmPIPE3_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE4_MAX_REQUESTS", REG_MMIO, 0x309, &mmPIPE4_MAX_REQUESTS[0], sizeof(mmPIPE4_MAX_REQUESTS)/sizeof(mmPIPE4_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE5_MAX_REQUESTS", REG_MMIO, 0x30a, &mmPIPE5_MAX_REQUESTS[0], sizeof(mmPIPE5_MAX_REQUESTS)/sizeof(mmPIPE5_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmLOW_POWER_TILING_CONTROL", REG_MMIO, 0x30b, &mmLOW_POWER_TILING_CONTROL[0], sizeof(mmLOW_POWER_TILING_CONTROL)/sizeof(mmLOW_POWER_TILING_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_CONTROL", REG_MMIO, 0x30c, &mmMCIF_CONTROL[0], sizeof(mmMCIF_CONTROL)/sizeof(mmMCIF_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WRITE_COMBINE_CONTROL", REG_MMIO, 0x30d, &mmMCIF_WRITE_COMBINE_CONTROL[0], sizeof(mmMCIF_WRITE_COMBINE_CONTROL)/sizeof(mmMCIF_WRITE_COMBINE_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_INDEX", REG_MMIO, 0x30e, &mmMCIF_TEST_DEBUG_INDEX[0], sizeof(mmMCIF_TEST_DEBUG_INDEX)/sizeof(mmMCIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_DATA", REG_MMIO, 0x30f, &mmMCIF_TEST_DEBUG_DATA[0], sizeof(mmMCIF_TEST_DEBUG_DATA)/sizeof(mmMCIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x31, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "mmMCIF_VMID", REG_MMIO, 0x310, &mmMCIF_VMID[0], sizeof(mmMCIF_VMID)/sizeof(mmMCIF_VMID[0]), 0, 0 },
+	{ "mmMCIF_MEM_CONTROL", REG_MMIO, 0x311, &mmMCIF_MEM_CONTROL[0], sizeof(mmMCIF_MEM_CONTROL)/sizeof(mmMCIF_MEM_CONTROL[0]), 0, 0 },
+	{ "mmCC_DC_PIPE_DIS", REG_MMIO, 0x312, &mmCC_DC_PIPE_DIS[0], sizeof(mmCC_DC_PIPE_DIS)/sizeof(mmCC_DC_PIPE_DIS[0]), 0, 0 },
+	{ "mmMC_DC_INTERFACE_NACK_STATUS", REG_MMIO, 0x313, &mmMC_DC_INTERFACE_NACK_STATUS[0], sizeof(mmMC_DC_INTERFACE_NACK_STATUS)/sizeof(mmMC_DC_INTERFACE_NACK_STATUS[0]), 0, 0 },
+	{ "mmRBBMIF_TIMEOUT", REG_MMIO, 0x314, &mmRBBMIF_TIMEOUT[0], sizeof(mmRBBMIF_TIMEOUT)/sizeof(mmRBBMIF_TIMEOUT[0]), 0, 0 },
+	{ "mmRBBMIF_STATUS", REG_MMIO, 0x315, &mmRBBMIF_STATUS[0], sizeof(mmRBBMIF_STATUS)/sizeof(mmRBBMIF_STATUS[0]), 0, 0 },
+	{ "mmRBBMIF_TIMEOUT_DIS", REG_MMIO, 0x316, &mmRBBMIF_TIMEOUT_DIS[0], sizeof(mmRBBMIF_TIMEOUT_DIS)/sizeof(mmRBBMIF_TIMEOUT_DIS[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATUS", REG_MMIO, 0x317, &mmDCI_MEM_PWR_STATUS[0], sizeof(mmDCI_MEM_PWR_STATUS)/sizeof(mmDCI_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATUS2", REG_MMIO, 0x318, &mmDCI_MEM_PWR_STATUS2[0], sizeof(mmDCI_MEM_PWR_STATUS2)/sizeof(mmDCI_MEM_PWR_STATUS2[0]), 0, 0 },
+	{ "mmDCI_CLK_CNTL", REG_MMIO, 0x319, &mmDCI_CLK_CNTL[0], sizeof(mmDCI_CLK_CNTL)/sizeof(mmDCI_CLK_CNTL[0]), 0, 0 },
+	{ "mmDCI_CLK_RAMP_CNTL", REG_MMIO, 0x31a, &mmDCI_CLK_RAMP_CNTL[0], sizeof(mmDCI_CLK_RAMP_CNTL)/sizeof(mmDCI_CLK_RAMP_CNTL[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL", REG_MMIO, 0x31b, &mmDCI_MEM_PWR_CNTL[0], sizeof(mmDCI_MEM_PWR_CNTL)/sizeof(mmDCI_MEM_PWR_CNTL[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL2", REG_MMIO, 0x31c, &mmDCI_MEM_PWR_CNTL2[0], sizeof(mmDCI_MEM_PWR_CNTL2)/sizeof(mmDCI_MEM_PWR_CNTL2[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL3", REG_MMIO, 0x31d, &mmDCI_MEM_PWR_CNTL3[0], sizeof(mmDCI_MEM_PWR_CNTL3)/sizeof(mmDCI_MEM_PWR_CNTL3[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_INDEX", REG_MMIO, 0x31e, &mmDCI_TEST_DEBUG_INDEX[0], sizeof(mmDCI_TEST_DEBUG_INDEX)/sizeof(mmDCI_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_DATA", REG_MMIO, 0x31f, &mmDCI_TEST_DEBUG_DATA[0], sizeof(mmDCI_TEST_DEBUG_DATA)/sizeof(mmDCI_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x32, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "mmDCI_DEBUG_CONFIG", REG_MMIO, 0x320, &mmDCI_DEBUG_CONFIG[0], sizeof(mmDCI_DEBUG_CONFIG)/sizeof(mmDCI_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE0_DMIF_BUFFER_CONTROL", REG_MMIO, 0x321, &mmPIPE0_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE0_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE0_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE1_DMIF_BUFFER_CONTROL", REG_MMIO, 0x322, &mmPIPE1_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE1_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE1_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE2_DMIF_BUFFER_CONTROL", REG_MMIO, 0x323, &mmPIPE2_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE2_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE2_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE3_DMIF_BUFFER_CONTROL", REG_MMIO, 0x324, &mmPIPE3_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE3_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE3_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE4_DMIF_BUFFER_CONTROL", REG_MMIO, 0x325, &mmPIPE4_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE4_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE4_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE5_DMIF_BUFFER_CONTROL", REG_MMIO, 0x326, &mmPIPE5_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE5_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE5_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmRBBMIF_STATUS_FLAG", REG_MMIO, 0x327, &mmRBBMIF_STATUS_FLAG[0], sizeof(mmRBBMIF_STATUS_FLAG)/sizeof(mmRBBMIF_STATUS_FLAG[0]), 0, 0 },
+	{ "mmDCI_SOFT_RESET", REG_MMIO, 0x328, &mmDCI_SOFT_RESET[0], sizeof(mmDCI_SOFT_RESET)/sizeof(mmDCI_SOFT_RESET[0]), 0, 0 },
+	{ "mmDMIF_URG_OVERRIDE", REG_MMIO, 0x329, &mmDMIF_URG_OVERRIDE[0], sizeof(mmDMIF_URG_OVERRIDE)/sizeof(mmDMIF_URG_OVERRIDE[0]), 0, 0 },
+	{ "mmPIPE6_ARBITRATION_CONTROL3", REG_MMIO, 0x32a, &mmPIPE6_ARBITRATION_CONTROL3[0], sizeof(mmPIPE6_ARBITRATION_CONTROL3)/sizeof(mmPIPE6_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE7_ARBITRATION_CONTROL3", REG_MMIO, 0x32b, &mmPIPE7_ARBITRATION_CONTROL3[0], sizeof(mmPIPE7_ARBITRATION_CONTROL3)/sizeof(mmPIPE7_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE6_MAX_REQUESTS", REG_MMIO, 0x32c, &mmPIPE6_MAX_REQUESTS[0], sizeof(mmPIPE6_MAX_REQUESTS)/sizeof(mmPIPE6_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE7_MAX_REQUESTS", REG_MMIO, 0x32d, &mmPIPE7_MAX_REQUESTS[0], sizeof(mmPIPE7_MAX_REQUESTS)/sizeof(mmPIPE7_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmDVMM_REG_RD_STATUS", REG_MMIO, 0x32e, &mmDVMM_REG_RD_STATUS[0], sizeof(mmDVMM_REG_RD_STATUS)/sizeof(mmDVMM_REG_RD_STATUS[0]), 0, 0 },
+	{ "mmDVMM_REG_RD_DATA", REG_MMIO, 0x32f, &mmDVMM_REG_RD_DATA[0], sizeof(mmDVMM_REG_RD_DATA)/sizeof(mmDVMM_REG_RD_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x33, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 },
+	{ "mmDVMM_PTE_REQ", REG_MMIO, 0x330, &mmDVMM_PTE_REQ[0], sizeof(mmDVMM_PTE_REQ)/sizeof(mmDVMM_PTE_REQ[0]), 0, 0 },
+	{ "mmDVMM_CNTL", REG_MMIO, 0x331, &mmDVMM_CNTL[0], sizeof(mmDVMM_CNTL)/sizeof(mmDVMM_CNTL[0]), 0, 0 },
+	{ "mmDVMM_FAULT_STATUS", REG_MMIO, 0x332, &mmDVMM_FAULT_STATUS[0], sizeof(mmDVMM_FAULT_STATUS)/sizeof(mmDVMM_FAULT_STATUS[0]), 0, 0 },
+	{ "mmDVMM_FAULT_ADDR", REG_MMIO, 0x333, &mmDVMM_FAULT_ADDR[0], sizeof(mmDVMM_FAULT_ADDR)/sizeof(mmDVMM_FAULT_ADDR[0]), 0, 0 },
+	{ "mmDCI_MISC", REG_MMIO, 0x334, &mmDCI_MISC[0], sizeof(mmDCI_MISC)/sizeof(mmDCI_MISC[0]), 0, 0 },
+	{ "mmDVMM_PTE_PGMEM_CONTROL", REG_MMIO, 0x335, &mmDVMM_PTE_PGMEM_CONTROL[0], sizeof(mmDVMM_PTE_PGMEM_CONTROL)/sizeof(mmDVMM_PTE_PGMEM_CONTROL[0]), 0, 0 },
+	{ "mmDVMM_PTE_PGMEM_STATE", REG_MMIO, 0x336, &mmDVMM_PTE_PGMEM_STATE[0], sizeof(mmDVMM_PTE_PGMEM_STATE)/sizeof(mmDVMM_PTE_PGMEM_STATE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x34, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x35, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x36, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x36, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 },
+	{ "mmDC_PERFMON1_PERFCOUNTER_CNTL", REG_MMIO, 0x364, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFCOUNTER_STATE", REG_MMIO, 0x365, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x366, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CNTL", REG_MMIO, 0x367, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CVALUE_LOW", REG_MMIO, 0x368, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_HI", REG_MMIO, 0x369, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_LOW", REG_MMIO, 0x36a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x36b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x36c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CNTL2", REG_MMIO, 0x36e, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x37, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x37, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY", REG_SMC, 0x3702, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x3707, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x3708, &ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x3709, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x371c, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x371d, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x371e, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x371f, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION", REG_SMC, 0x3770, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x3771, &ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO", REG_SMC, 0x3772, &ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE", REG_SMC, 0x3777, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE", REG_SMC, 0x3778, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE", REG_SMC, 0x3779, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE", REG_SMC, 0x377a, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC", REG_SMC, 0x377b, &ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_HBR", REG_SMC, 0x377c, &ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX", REG_SMC, 0x3780, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA", REG_SMC, 0x3781, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x3785, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x3786, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x3787, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x3788, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x3789, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x378a, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x378b, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x378c, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x378d, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x378e, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x378f, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x3790, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x3791, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x3792, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x3793, &ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x3797, &ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x3798, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x3799, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x379a, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x379b, &ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x379c, &ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x379d, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x379e, &ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x38, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x38, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x3a, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x3b, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x3c, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x3d, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x3e, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 },
+	{ "mmXDMA_MC_PCIE_CLIENT_CONFIG", REG_MMIO, 0x3e0, &mmXDMA_MC_PCIE_CLIENT_CONFIG[0], sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG)/sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING1", REG_MMIO, 0x3e1, &mmXDMA_LOCAL_SURFACE_TILING1[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING1)/sizeof(mmXDMA_LOCAL_SURFACE_TILING1[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING2", REG_MMIO, 0x3e2, &mmXDMA_LOCAL_SURFACE_TILING2[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING2)/sizeof(mmXDMA_LOCAL_SURFACE_TILING2[0]), 0, 0 },
+	{ "mmXDMA_INTERRUPT", REG_MMIO, 0x3e3, &mmXDMA_INTERRUPT[0], sizeof(mmXDMA_INTERRUPT)/sizeof(mmXDMA_INTERRUPT[0]), 0, 0 },
+	{ "mmXDMA_CLOCK_GATING_CNTL", REG_MMIO, 0x3e4, &mmXDMA_CLOCK_GATING_CNTL[0], sizeof(mmXDMA_CLOCK_GATING_CNTL)/sizeof(mmXDMA_CLOCK_GATING_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MEM_POWER_CNTL", REG_MMIO, 0x3e6, &mmXDMA_MEM_POWER_CNTL[0], sizeof(mmXDMA_MEM_POWER_CNTL)/sizeof(mmXDMA_MEM_POWER_CNTL[0]), 0, 0 },
+	{ "mmXDMA_IF_BIF_STATUS", REG_MMIO, 0x3e7, &mmXDMA_IF_BIF_STATUS[0], sizeof(mmXDMA_IF_BIF_STATUS)/sizeof(mmXDMA_IF_BIF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_PERF_MEAS_STATUS", REG_MMIO, 0x3e8, &mmXDMA_PERF_MEAS_STATUS[0], sizeof(mmXDMA_PERF_MEAS_STATUS)/sizeof(mmXDMA_PERF_MEAS_STATUS[0]), 0, 0 },
+	{ "mmXDMA_IF_STATUS", REG_MMIO, 0x3e9, &mmXDMA_IF_STATUS[0], sizeof(mmXDMA_IF_STATUS)/sizeof(mmXDMA_IF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_INDEX", REG_MMIO, 0x3ea, &mmXDMA_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_TEST_DEBUG_INDEX)/sizeof(mmXDMA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_DATA", REG_MMIO, 0x3eb, &mmXDMA_TEST_DEBUG_DATA[0], sizeof(mmXDMA_TEST_DEBUG_DATA)/sizeof(mmXDMA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CNTL", REG_MMIO, 0x3ec, &mmXDMA_MSTR_CNTL[0], sizeof(mmXDMA_MSTR_CNTL)/sizeof(mmXDMA_MSTR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_STATUS", REG_MMIO, 0x3ed, &mmXDMA_MSTR_STATUS[0], sizeof(mmXDMA_MSTR_STATUS)/sizeof(mmXDMA_MSTR_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_CLIENT_CONFIG", REG_MMIO, 0x3ee, &mmXDMA_MSTR_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", REG_MMIO, 0x3ef, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x3f, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", REG_MMIO, 0x3f0, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x3f09, &ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x3f0c, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH", REG_SMC, 0x3f0e, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_PITCH", REG_MMIO, 0x3f1, &mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CMD_URGENT_CNTL", REG_MMIO, 0x3f2, &mmXDMA_MSTR_CMD_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL)/sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_URGENT_CNTL", REG_MMIO, 0x3f3, &mmXDMA_MSTR_MEM_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL)/sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PCIE_NACK_STATUS", REG_MMIO, 0x3f5, &mmXDMA_MSTR_PCIE_NACK_STATUS[0], sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS)/sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_NACK_STATUS", REG_MMIO, 0x3f6, &mmXDMA_MSTR_MEM_NACK_STATUS[0], sizeof(mmXDMA_MSTR_MEM_NACK_STATUS)/sizeof(mmXDMA_MSTR_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_VSYNC_GSL_CHECK", REG_MMIO, 0x3f7, &mmXDMA_MSTR_VSYNC_GSL_CHECK[0], sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK)/sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK[0]), 0, 0 },
+	{ "mmXDMA_RBBMIF_RDWR_CNTL", REG_MMIO, 0x3f8, &mmXDMA_RBBMIF_RDWR_CNTL[0], sizeof(mmXDMA_RBBMIF_RDWR_CNTL)/sizeof(mmXDMA_RBBMIF_RDWR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_PG_CONTROL", REG_MMIO, 0x3f9, &mmXDMA_PG_CONTROL[0], sizeof(mmXDMA_PG_CONTROL)/sizeof(mmXDMA_PG_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_PG_WDATA", REG_MMIO, 0x3fa, &mmXDMA_PG_WDATA[0], sizeof(mmXDMA_PG_WDATA)/sizeof(mmXDMA_PG_WDATA[0]), 0, 0 },
+	{ "mmXDMA_PG_STATUS", REG_MMIO, 0x3fb, &mmXDMA_PG_STATUS[0], sizeof(mmXDMA_PG_STATUS)/sizeof(mmXDMA_PG_STATUS[0]), 0, 0 },
+	{ "mmXDMA_AON_TEST_DEBUG_INDEX", REG_MMIO, 0x3fc, &mmXDMA_AON_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_AON_TEST_DEBUG_INDEX)/sizeof(mmXDMA_AON_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_AON_TEST_DEBUG_DATA", REG_MMIO, 0x3fd, &mmXDMA_AON_TEST_DEBUG_DATA[0], sizeof(mmXDMA_AON_TEST_DEBUG_DATA)/sizeof(mmXDMA_AON_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x4, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x4, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1", REG_SMC, 0x4, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0]), 0, 0 },
+	{ "ixAZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x4, &ixAZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL4", REG_SMC, 0x4, &ixAZALIA_INPUT_CRC0_CHANNEL4[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL4)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL4[0]), 0, 0 },
+	{ "ixDPGV0_DEBUG03_DMIFARB", REG_SMC, 0x4, NULL, 0, 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL4", REG_SMC, 0x4, &ixAZALIA_CRC0_CHANNEL4[0], sizeof(ixAZALIA_CRC0_CHANNEL4)/sizeof(ixAZALIA_CRC0_CHANNEL4[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR3", REG_SMC, 0x4, &ixAUDIO_DESCRIPTOR3[0], sizeof(ixAUDIO_DESCRIPTOR3)/sizeof(ixAUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "mmGLOBAL_STATUS", REG_MMIO, 0x4, &mmGLOBAL_STATUS[0], sizeof(mmGLOBAL_STATUS)/sizeof(mmGLOBAL_STATUS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG4", REG_SMC, 0x4, &ixDCIO_DEBUG4[0], sizeof(ixDCIO_DEBUG4)/sizeof(ixDCIO_DEBUG4[0]), 0, 0 },
+	{ "ixATTR04", REG_SMC, 0x4, &ixATTR04[0], sizeof(ixATTR04)/sizeof(ixATTR04[0]), 0, 0 },
+	{ "ixSEQ04", REG_SMC, 0x4, &ixSEQ04[0], sizeof(ixSEQ04)/sizeof(ixSEQ04[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x40, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, &mmXDMA_MSTR_PIPE_CNTL[0], sizeof(mmXDMA_MSTR_PIPE_CNTL)/sizeof(mmXDMA_MSTR_PIPE_CNTL[0]), 0, 0 },
+	{ "mmDCP3_GRPH_ENABLE", REG_MMIO, 0x4000, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_CONTROL", REG_MMIO, 0x4001, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4002, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SWAP_CNTL", REG_MMIO, 0x4003, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4004, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4005, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PITCH", REG_MMIO, 0x4006, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4007, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4008, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4009, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x400a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_START", REG_MMIO, 0x400b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_START", REG_MMIO, 0x400c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_END", REG_MMIO, 0x400d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_END", REG_MMIO, 0x400e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x400f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, &mmXDMA_MSTR_READ_COMMAND[0], sizeof(mmXDMA_MSTR_READ_COMMAND)/sizeof(mmXDMA_MSTR_READ_COMMAND[0]), 0, 0 },
+	{ "mmDCP3_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4010, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_UPDATE", REG_MMIO, 0x4011, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_CONTROL", REG_MMIO, 0x4012, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4013, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_CONTROL", REG_MMIO, 0x4014, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_STATUS", REG_MMIO, 0x4015, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4016, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4017, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4018, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4019, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_PITCH", REG_MMIO, 0x401a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x401b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x401c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x401d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, &mmXDMA_MSTR_CHANNEL_DIM[0], sizeof(mmXDMA_MSTR_CHANNEL_DIM)/sizeof(mmXDMA_MSTR_CHANNEL_DIM[0]), 0, 0 },
+	{ "mmDCP3_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x402d, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x402e, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x402f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT", REG_MMIO, 0x403, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_HEIGHT", REG_MMIO, 0x403, &mmXDMA_MSTR_HEIGHT[0], sizeof(mmXDMA_MSTR_HEIGHT)/sizeof(mmXDMA_MSTR_HEIGHT[0]), 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4030, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_CONTROL", REG_MMIO, 0x4035, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C11_C12", REG_MMIO, 0x4036, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C13_C14", REG_MMIO, 0x4037, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C21_C22", REG_MMIO, 0x4038, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C23_C24", REG_MMIO, 0x4039, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C31_C32", REG_MMIO, 0x403a, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C33_C34", REG_MMIO, 0x403b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_CONTROL", REG_MMIO, 0x403c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C11_C12", REG_MMIO, 0x403d, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C13_C14", REG_MMIO, 0x403e, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C21_C22", REG_MMIO, 0x403f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, &mmXDMA_MSTR_REMOTE_SURFACE_BASE[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE[0]), 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4040, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4041, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4042, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4043, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4044, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4045, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4046, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4047, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4048, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4049, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x404a, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x404b, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x404c, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x404d, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x404e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, &mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DENORM_CONTROL", REG_MMIO, 0x4050, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_ROUND_CONTROL", REG_MMIO, 0x4051, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4052, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_CONTROL", REG_MMIO, 0x4053, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_ALPHA", REG_MMIO, 0x4054, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_RED", REG_MMIO, 0x4055, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_GREEN", REG_MMIO, 0x4056, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_BLUE", REG_MMIO, 0x4057, NULL, 0, 0, 0 },
+	{ "mmDCP3_DEGAMMA_CONTROL", REG_MMIO, 0x4058, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4059, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C11_C12", REG_MMIO, 0x405a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C13_C14", REG_MMIO, 0x405b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C21_C22", REG_MMIO, 0x405c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C23_C24", REG_MMIO, 0x405d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C31_C32", REG_MMIO, 0x405e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C33_C34", REG_MMIO, 0x405f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmDCP3_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4060, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4065, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_CONTROL", REG_MMIO, 0x4066, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4067, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SIZE", REG_MMIO, 0x4068, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4069, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_POSITION", REG_MMIO, 0x406a, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_HOT_SPOT", REG_MMIO, 0x406b, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR1", REG_MMIO, 0x406c, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR2", REG_MMIO, 0x406d, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_UPDATE", REG_MMIO, 0x406e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_MODE", REG_MMIO, 0x4078, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_INDEX", REG_MMIO, 0x4079, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_SEQ_COLOR", REG_MMIO, 0x407a, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_PWL_DATA", REG_MMIO, 0x407b, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_30_COLOR", REG_MMIO, 0x407c, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x407d, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x407e, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_AUTOFILL", REG_MMIO, 0x407f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, &mmXDMA_MSTR_CACHE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR[0]), 0, 0 },
+	{ "mmDCP3_DC_LUT_CONTROL", REG_MMIO, 0x4080, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4081, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4082, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4083, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4084, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4085, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4086, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CONTROL", REG_MMIO, 0x4087, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_MASK", REG_MMIO, 0x4088, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CURRENT", REG_MMIO, 0x4089, NULL, 0, 0, 0 },
+	{ "mmDCP3_DVMM_PTE_CONTROL", REG_MMIO, 0x408a, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_LAST", REG_MMIO, 0x408b, NULL, 0, 0, 0 },
+	{ "mmDCP3_DVMM_PTE_ARB_CONTROL", REG_MMIO, 0x408c, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG", REG_MMIO, 0x408d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x408e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, &mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DCP_GSL_CONTROL", REG_MMIO, 0x4090, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4091, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG_SG", REG_MMIO, 0x4092, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DVMM_DEBUG", REG_MMIO, 0x4093, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG_SG2", REG_MMIO, 0x4094, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4095, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4096, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4097, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG2", REG_MMIO, 0x4098, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4099, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_STEREO_CONTROL", REG_MMIO, 0x409a, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x409c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x409d, NULL, 0, 0, 0 },
+	{ "mmDCP3_HW_ROTATION", REG_MMIO, 0x409e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x409f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE", REG_MMIO, 0x40a, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE", REG_MMIO, 0x40a, &mmXDMA_MSTR_CACHE[0], sizeof(mmXDMA_MSTR_CACHE)/sizeof(mmXDMA_MSTR_CACHE[0]), 0, 0 },
+	{ "mmDCP3_REGAMMA_CONTROL", REG_MMIO, 0x40a0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_INDEX", REG_MMIO, 0x40a1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_DATA", REG_MMIO, 0x40a2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x40a3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x40a4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x40a5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x40a6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x40a7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x40a8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x40a9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x40aa, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x40ab, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x40ac, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x40ad, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x40ae, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x40af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, &mmXDMA_MSTR_CHANNEL_START[0], sizeof(mmXDMA_MSTR_CHANNEL_START)/sizeof(mmXDMA_MSTR_CHANNEL_START[0]), 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x40b0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x40b1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x40b2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x40b3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x40b4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x40b5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x40b6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x40b7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x40b8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x40b9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x40ba, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x40bb, NULL, 0, 0, 0 },
+	{ "mmDCP3_ALPHA_CONTROL", REG_MMIO, 0x40bc, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x40bd, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x40be, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x40bf, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DATA_FORMAT", REG_MMIO, 0x40c0, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_MEMORY_CTRL", REG_MMIO, 0x40c1, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x40c2, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DESKTOP_HEIGHT", REG_MMIO, 0x40c3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE_START_END", REG_MMIO, 0x40c4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE2_START_END", REG_MMIO, 0x40c5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_V_COUNTER", REG_MMIO, 0x40c6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x40c7, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_INTERRUPT_MASK", REG_MMIO, 0x40c8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE_STATUS", REG_MMIO, 0x40c9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE2_STATUS", REG_MMIO, 0x40ca, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VBLANK_STATUS", REG_MMIO, 0x40cb, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SYNC_RESET_SEL", REG_MMIO, 0x40cc, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x40cd, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x40ce, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x40cf, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x40d0, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x40d1, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x40d2, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x40d3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x40d4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x40d5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x40d6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x40d7, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x40d8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x40d9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_STATUS", REG_MMIO, 0x40da, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x40dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, &mmXDMA_MSTR_PERFMEAS_STATUS[0], sizeof(mmXDMA_MSTR_PERFMEAS_STATUS)/sizeof(mmXDMA_MSTR_PERFMEAS_STATUS[0]), 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_MODE", REG_MMIO, 0x40e0, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x40e1, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x40e2, NULL, 0, 0, 0 },
+	{ "mmLB3_DC_MVP_LB_CONTROL", REG_MMIO, 0x40e3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG", REG_MMIO, 0x40e4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG2", REG_MMIO, 0x40e5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG3", REG_MMIO, 0x40e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, &mmXDMA_MSTR_PERFMEAS_CNTL[0], sizeof(mmXDMA_MSTR_PERFMEAS_CNTL)/sizeof(mmXDMA_MSTR_PERFMEAS_CNTL[0]), 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x40fe, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_DATA", REG_MMIO, 0x40ff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x41, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x410, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4100, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_SOFT_RESET", REG_MMIO, 0x4101, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_DBG_CONFIG", REG_MMIO, 0x4102, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x4103, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x4104, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x4105, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_MISC", REG_MMIO, 0x4106, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x411, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x412, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFCOUNTER_CNTL", REG_MMIO, 0x4124, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFCOUNTER_STATE", REG_MMIO, 0x4125, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4126, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CNTL", REG_MMIO, 0x4127, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CVALUE_LOW", REG_MMIO, 0x4128, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_HI", REG_MMIO, 0x4129, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_LOW", REG_MMIO, 0x412a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x412b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x412c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CNTL2", REG_MMIO, 0x412e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT", REG_MMIO, 0x413, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4130, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4131, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4132, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4133, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4134, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4135, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4136, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4137, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4138, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4139, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_REPEATER_PROGRAM", REG_MMIO, 0x413a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_A", REG_MMIO, 0x413b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_B", REG_MMIO, 0x413c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_11", REG_MMIO, 0x413d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x413e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x414, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4140, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4141, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE", REG_MMIO, 0x4142, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TAP_CONTROL", REG_MMIO, 0x4143, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_CONTROL", REG_MMIO, 0x4144, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_BYPASS_CONTROL", REG_MMIO, 0x4145, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4146, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4147, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4148, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4149, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x414a, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x414b, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x414c, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT", REG_MMIO, 0x414d, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x414e, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ROUND_OFFSET", REG_MMIO, 0x414f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x415, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_UPDATE", REG_MMIO, 0x4151, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4153, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ALU_CONTROL", REG_MMIO, 0x4154, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4155, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_START_SECONDARY", REG_MMIO, 0x415b, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_START", REG_MMIO, 0x415c, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_SIZE", REG_MMIO, 0x415d, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x415e, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x415f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x416, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4160, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4161, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4162, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4163, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG2", REG_MMIO, 0x4169, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG", REG_MMIO, 0x416a, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x416b, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x416c, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_CONTROL", REG_MMIO, 0x416d, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_SM_CONTROL2", REG_MMIO, 0x416e, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_CONTROL2", REG_MMIO, 0x416f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x417, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_UPDATE", REG_MMIO, 0x4170, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4171, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4173, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_DEBUG", REG_MMIO, 0x4174, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4175, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4176, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4177, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4178, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4179, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_WINDOW", REG_MMIO, 0x417a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_CONTROL", REG_MMIO, 0x417b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x417d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x418, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_TOTAL", REG_MMIO, 0x4180, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_START_END", REG_MMIO, 0x4181, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A", REG_MMIO, 0x4182, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4183, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B", REG_MMIO, 0x4184, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4185, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VBI_END", REG_MMIO, 0x4186, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL", REG_MMIO, 0x4187, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4188, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4189, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x418a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x418b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x418c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_BLANK_START_END", REG_MMIO, 0x418d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A", REG_MMIO, 0x418e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x418f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x419, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B", REG_MMIO, 0x4190, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4191, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4192, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4193, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_CNTL", REG_MMIO, 0x4194, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4195, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_CNTL", REG_MMIO, 0x4196, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4197, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4198, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FLOW_CONTROL", REG_MMIO, 0x4199, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x419a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x419b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CONTROL", REG_MMIO, 0x419c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_CONTROL", REG_MMIO, 0x419d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x419e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_STATUS", REG_MMIO, 0x419f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE", REG_MMIO, 0x41a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x41a0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x41a1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x41a2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS", REG_MMIO, 0x41a3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_POSITION", REG_MMIO, 0x41a4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x41a5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x41a6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x41a7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x41a8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_CONTROL", REG_MMIO, 0x41a9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_RESET", REG_MMIO, 0x41aa, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x41ab, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x41ac, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_STATUS", REG_MMIO, 0x41ad, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_CONTROL", REG_MMIO, 0x41ae, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x41af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x41b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x41b0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x41b1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x41b2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_START_LINE_CONTROL", REG_MMIO, 0x41b3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x41b4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_UPDATE_LOCK", REG_MMIO, 0x41b5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x41b6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x41b7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x41ba, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x41bb, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x41bc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x41bd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x41be, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x41bf, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x41c0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_STATUS", REG_MMIO, 0x41c1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_EN", REG_MMIO, 0x41c2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x41c3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x41c4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x41c6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x41c7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x41c8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x41c9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x41ca, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x41cb, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR", REG_MMIO, 0x41cc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x41cd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x41ce, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x41cf, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x41d0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x41d1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x41d2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x41d3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC_CNTL", REG_MMIO, 0x41d4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x41d5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x41d6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x41d7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x41d8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_DATA_RG", REG_MMIO, 0x41d9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_DATA_B", REG_MMIO, 0x41da, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x41db, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x41dc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x41dd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x41de, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_DATA_RG", REG_MMIO, 0x41df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x41e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_DATA_B", REG_MMIO, 0x41e0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x41e7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x41e8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x41e9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x41ea, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x41eb, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x41ec, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x41ed, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CONTROL", REG_MMIO, 0x41ee, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x41f, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x41f2, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x41f3, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x41f4, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x41f5, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x41f6, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x41f7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x41f8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_CNTL", REG_MMIO, 0x41f9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_CNTL", REG_MMIO, 0x41fa, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x41fb, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x41fc, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x41fd, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x41fe, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DEBUG_CNTL", REG_MMIO, 0x41ff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x42, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x420, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_ENABLE", REG_MMIO, 0x4200, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_CONTROL", REG_MMIO, 0x4201, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4202, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SWAP_CNTL", REG_MMIO, 0x4203, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4204, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4205, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PITCH", REG_MMIO, 0x4206, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4207, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4208, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4209, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x420a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_START", REG_MMIO, 0x420b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_START", REG_MMIO, 0x420c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_END", REG_MMIO, 0x420d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_END", REG_MMIO, 0x420e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x420f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x421, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4210, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_UPDATE", REG_MMIO, 0x4211, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_CONTROL", REG_MMIO, 0x4212, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4213, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_CONTROL", REG_MMIO, 0x4214, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_STATUS", REG_MMIO, 0x4215, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4216, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4217, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4218, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4219, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_PITCH", REG_MMIO, 0x421a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x421b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x421c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x421d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x422, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x422d, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x422e, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x422f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT", REG_MMIO, 0x423, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4230, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_CONTROL", REG_MMIO, 0x4235, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C11_C12", REG_MMIO, 0x4236, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C13_C14", REG_MMIO, 0x4237, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C21_C22", REG_MMIO, 0x4238, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C23_C24", REG_MMIO, 0x4239, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C31_C32", REG_MMIO, 0x423a, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C33_C34", REG_MMIO, 0x423b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_CONTROL", REG_MMIO, 0x423c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C11_C12", REG_MMIO, 0x423d, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C13_C14", REG_MMIO, 0x423e, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C21_C22", REG_MMIO, 0x423f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x424, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4240, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4241, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4242, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4243, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4244, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4245, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4246, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4247, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4248, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4249, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x424a, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x424b, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x424c, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x424d, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x424e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x425, NULL, 0, 0, 0 },
+	{ "mmDCP4_DENORM_CONTROL", REG_MMIO, 0x4250, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_ROUND_CONTROL", REG_MMIO, 0x4251, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4252, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_CONTROL", REG_MMIO, 0x4253, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_ALPHA", REG_MMIO, 0x4254, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_RED", REG_MMIO, 0x4255, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_GREEN", REG_MMIO, 0x4256, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_BLUE", REG_MMIO, 0x4257, NULL, 0, 0, 0 },
+	{ "mmDCP4_DEGAMMA_CONTROL", REG_MMIO, 0x4258, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4259, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C11_C12", REG_MMIO, 0x425a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C13_C14", REG_MMIO, 0x425b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C21_C22", REG_MMIO, 0x425c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C23_C24", REG_MMIO, 0x425d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C31_C32", REG_MMIO, 0x425e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C33_C34", REG_MMIO, 0x425f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x426, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4260, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4265, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_CONTROL", REG_MMIO, 0x4266, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4267, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SIZE", REG_MMIO, 0x4268, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4269, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_POSITION", REG_MMIO, 0x426a, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_HOT_SPOT", REG_MMIO, 0x426b, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR1", REG_MMIO, 0x426c, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR2", REG_MMIO, 0x426d, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_UPDATE", REG_MMIO, 0x426e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x427, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_MODE", REG_MMIO, 0x4278, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_INDEX", REG_MMIO, 0x4279, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_SEQ_COLOR", REG_MMIO, 0x427a, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_PWL_DATA", REG_MMIO, 0x427b, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_30_COLOR", REG_MMIO, 0x427c, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x427d, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x427e, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_AUTOFILL", REG_MMIO, 0x427f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x428, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_CONTROL", REG_MMIO, 0x4280, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4281, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4282, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4283, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4284, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4285, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4286, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CONTROL", REG_MMIO, 0x4287, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_MASK", REG_MMIO, 0x4288, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CURRENT", REG_MMIO, 0x4289, NULL, 0, 0, 0 },
+	{ "mmDCP4_DVMM_PTE_CONTROL", REG_MMIO, 0x428a, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_LAST", REG_MMIO, 0x428b, NULL, 0, 0, 0 },
+	{ "mmDCP4_DVMM_PTE_ARB_CONTROL", REG_MMIO, 0x428c, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG", REG_MMIO, 0x428d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x428e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x429, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_GSL_CONTROL", REG_MMIO, 0x4290, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4291, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG_SG", REG_MMIO, 0x4292, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DVMM_DEBUG", REG_MMIO, 0x4293, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG_SG2", REG_MMIO, 0x4294, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4295, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4296, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4297, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG2", REG_MMIO, 0x4298, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4299, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_STEREO_CONTROL", REG_MMIO, 0x429a, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x429c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x429d, NULL, 0, 0, 0 },
+	{ "mmDCP4_HW_ROTATION", REG_MMIO, 0x429e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x429f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE", REG_MMIO, 0x42a, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CONTROL", REG_MMIO, 0x42a0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_INDEX", REG_MMIO, 0x42a1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_DATA", REG_MMIO, 0x42a2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x42a3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x42a4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x42a5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x42a6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x42a7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x42a8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x42a9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x42aa, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x42ab, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x42ac, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x42ad, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x42ae, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x42af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x42b, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x42b0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x42b1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x42b2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x42b3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x42b4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x42b5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x42b6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x42b7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x42b8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x42b9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x42ba, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x42bb, NULL, 0, 0, 0 },
+	{ "mmDCP4_ALPHA_CONTROL", REG_MMIO, 0x42bc, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x42bd, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x42be, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x42bf, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DATA_FORMAT", REG_MMIO, 0x42c0, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_MEMORY_CTRL", REG_MMIO, 0x42c1, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x42c2, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DESKTOP_HEIGHT", REG_MMIO, 0x42c3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE_START_END", REG_MMIO, 0x42c4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE2_START_END", REG_MMIO, 0x42c5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_V_COUNTER", REG_MMIO, 0x42c6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x42c7, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_INTERRUPT_MASK", REG_MMIO, 0x42c8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE_STATUS", REG_MMIO, 0x42c9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE2_STATUS", REG_MMIO, 0x42ca, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VBLANK_STATUS", REG_MMIO, 0x42cb, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SYNC_RESET_SEL", REG_MMIO, 0x42cc, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x42cd, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x42ce, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x42cf, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x42d0, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x42d1, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x42d2, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x42d3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x42d4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x42d5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x42d6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x42d7, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x42d8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x42d9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_STATUS", REG_MMIO, 0x42da, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x42dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x42e, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_MODE", REG_MMIO, 0x42e0, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x42e1, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x42e2, NULL, 0, 0, 0 },
+	{ "mmLB4_DC_MVP_LB_CONTROL", REG_MMIO, 0x42e3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG", REG_MMIO, 0x42e4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG2", REG_MMIO, 0x42e5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG3", REG_MMIO, 0x42e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x42f, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x42fe, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_DATA", REG_MMIO, 0x42ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x430, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4300, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_SOFT_RESET", REG_MMIO, 0x4301, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_DBG_CONFIG", REG_MMIO, 0x4302, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x4303, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x4304, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x4305, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_MISC", REG_MMIO, 0x4306, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x431, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x432, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFCOUNTER_CNTL", REG_MMIO, 0x4324, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFCOUNTER_STATE", REG_MMIO, 0x4325, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4326, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CNTL", REG_MMIO, 0x4327, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CVALUE_LOW", REG_MMIO, 0x4328, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_HI", REG_MMIO, 0x4329, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_LOW", REG_MMIO, 0x432a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x432b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x432c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CNTL2", REG_MMIO, 0x432e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT", REG_MMIO, 0x433, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4330, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4331, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4332, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4333, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4334, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4335, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4336, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4337, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4338, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4339, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_REPEATER_PROGRAM", REG_MMIO, 0x433a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_A", REG_MMIO, 0x433b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_B", REG_MMIO, 0x433c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_11", REG_MMIO, 0x433d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x433e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x434, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4340, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4341, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE", REG_MMIO, 0x4342, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TAP_CONTROL", REG_MMIO, 0x4343, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_CONTROL", REG_MMIO, 0x4344, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_BYPASS_CONTROL", REG_MMIO, 0x4345, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4346, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4347, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4348, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4349, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x434a, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x434b, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x434c, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT", REG_MMIO, 0x434d, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x434e, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ROUND_OFFSET", REG_MMIO, 0x434f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x435, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_UPDATE", REG_MMIO, 0x4351, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4353, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ALU_CONTROL", REG_MMIO, 0x4354, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4355, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_START_SECONDARY", REG_MMIO, 0x435b, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_START", REG_MMIO, 0x435c, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_SIZE", REG_MMIO, 0x435d, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x435e, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x435f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x436, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4360, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4361, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4362, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4363, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG2", REG_MMIO, 0x4369, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG", REG_MMIO, 0x436a, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x436b, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x436c, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_CONTROL", REG_MMIO, 0x436d, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_SM_CONTROL2", REG_MMIO, 0x436e, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_CONTROL2", REG_MMIO, 0x436f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x437, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_UPDATE", REG_MMIO, 0x4370, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4371, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4373, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_DEBUG", REG_MMIO, 0x4374, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4375, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4376, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4377, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4378, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4379, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_WINDOW", REG_MMIO, 0x437a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_CONTROL", REG_MMIO, 0x437b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x437d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x438, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_TOTAL", REG_MMIO, 0x4380, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_START_END", REG_MMIO, 0x4381, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A", REG_MMIO, 0x4382, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4383, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B", REG_MMIO, 0x4384, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4385, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VBI_END", REG_MMIO, 0x4386, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL", REG_MMIO, 0x4387, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4388, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4389, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x438a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x438b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x438c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_BLANK_START_END", REG_MMIO, 0x438d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A", REG_MMIO, 0x438e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x438f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x439, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B", REG_MMIO, 0x4390, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4391, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4392, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4393, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_CNTL", REG_MMIO, 0x4394, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4395, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_CNTL", REG_MMIO, 0x4396, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4397, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4398, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FLOW_CONTROL", REG_MMIO, 0x4399, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x439a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x439b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CONTROL", REG_MMIO, 0x439c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_CONTROL", REG_MMIO, 0x439d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x439e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_STATUS", REG_MMIO, 0x439f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE", REG_MMIO, 0x43a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x43a0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x43a1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x43a2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS", REG_MMIO, 0x43a3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_POSITION", REG_MMIO, 0x43a4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x43a5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x43a6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x43a7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x43a8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_CONTROL", REG_MMIO, 0x43a9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_RESET", REG_MMIO, 0x43aa, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x43ab, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x43ac, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_STATUS", REG_MMIO, 0x43ad, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_CONTROL", REG_MMIO, 0x43ae, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x43af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x43b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x43b0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x43b1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x43b2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_START_LINE_CONTROL", REG_MMIO, 0x43b3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x43b4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_UPDATE_LOCK", REG_MMIO, 0x43b5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x43b6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x43b7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x43ba, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x43bb, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x43bc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x43bd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x43be, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x43bf, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x43c0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_STATUS", REG_MMIO, 0x43c1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_EN", REG_MMIO, 0x43c2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x43c3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x43c4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x43c6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x43c7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x43c8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x43c9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x43ca, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x43cb, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR", REG_MMIO, 0x43cc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x43cd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x43ce, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x43cf, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x43d0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x43d1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x43d2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x43d3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC_CNTL", REG_MMIO, 0x43d4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x43d5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x43d6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x43d7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x43d8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_DATA_RG", REG_MMIO, 0x43d9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_DATA_B", REG_MMIO, 0x43da, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x43db, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x43dc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x43dd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x43de, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_DATA_RG", REG_MMIO, 0x43df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x43e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_DATA_B", REG_MMIO, 0x43e0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x43e7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x43e8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x43e9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x43ea, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x43eb, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x43ec, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x43ed, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CONTROL", REG_MMIO, 0x43ee, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x43f, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x43f2, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x43f3, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x43f4, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x43f5, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x43f6, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x43f7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x43f8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_CNTL", REG_MMIO, 0x43f9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_CNTL", REG_MMIO, 0x43fa, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x43fb, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x43fc, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x43fd, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x43fe, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DEBUG_CNTL", REG_MMIO, 0x43ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x440, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_ENABLE", REG_MMIO, 0x4400, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_CONTROL", REG_MMIO, 0x4401, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4402, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SWAP_CNTL", REG_MMIO, 0x4403, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4404, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4405, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PITCH", REG_MMIO, 0x4406, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4407, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4408, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4409, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x440a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_START", REG_MMIO, 0x440b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_START", REG_MMIO, 0x440c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_END", REG_MMIO, 0x440d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_END", REG_MMIO, 0x440e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x440f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x441, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4410, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_UPDATE", REG_MMIO, 0x4411, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_CONTROL", REG_MMIO, 0x4412, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4413, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_CONTROL", REG_MMIO, 0x4414, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_STATUS", REG_MMIO, 0x4415, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4416, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4417, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4418, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4419, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_PITCH", REG_MMIO, 0x441a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x441b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x441c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x441d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x442, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x442d, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x442e, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x442f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT", REG_MMIO, 0x443, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4430, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_CONTROL", REG_MMIO, 0x4435, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C11_C12", REG_MMIO, 0x4436, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C13_C14", REG_MMIO, 0x4437, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C21_C22", REG_MMIO, 0x4438, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C23_C24", REG_MMIO, 0x4439, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C31_C32", REG_MMIO, 0x443a, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C33_C34", REG_MMIO, 0x443b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_CONTROL", REG_MMIO, 0x443c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C11_C12", REG_MMIO, 0x443d, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C13_C14", REG_MMIO, 0x443e, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C21_C22", REG_MMIO, 0x443f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x444, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4440, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4441, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4442, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4443, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4444, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4445, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4446, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4447, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4448, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4449, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x444a, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x444b, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x444c, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x444d, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x444e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x445, NULL, 0, 0, 0 },
+	{ "mmDCP5_DENORM_CONTROL", REG_MMIO, 0x4450, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_ROUND_CONTROL", REG_MMIO, 0x4451, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4452, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_CONTROL", REG_MMIO, 0x4453, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_ALPHA", REG_MMIO, 0x4454, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_RED", REG_MMIO, 0x4455, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_GREEN", REG_MMIO, 0x4456, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_BLUE", REG_MMIO, 0x4457, NULL, 0, 0, 0 },
+	{ "mmDCP5_DEGAMMA_CONTROL", REG_MMIO, 0x4458, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4459, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C11_C12", REG_MMIO, 0x445a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C13_C14", REG_MMIO, 0x445b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C21_C22", REG_MMIO, 0x445c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C23_C24", REG_MMIO, 0x445d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C31_C32", REG_MMIO, 0x445e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C33_C34", REG_MMIO, 0x445f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x446, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4460, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4465, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_CONTROL", REG_MMIO, 0x4466, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4467, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SIZE", REG_MMIO, 0x4468, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4469, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_POSITION", REG_MMIO, 0x446a, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_HOT_SPOT", REG_MMIO, 0x446b, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR1", REG_MMIO, 0x446c, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR2", REG_MMIO, 0x446d, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_UPDATE", REG_MMIO, 0x446e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x447, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_MODE", REG_MMIO, 0x4478, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_INDEX", REG_MMIO, 0x4479, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_SEQ_COLOR", REG_MMIO, 0x447a, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_PWL_DATA", REG_MMIO, 0x447b, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_30_COLOR", REG_MMIO, 0x447c, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x447d, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x447e, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_AUTOFILL", REG_MMIO, 0x447f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x448, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_CONTROL", REG_MMIO, 0x4480, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4481, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4482, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4483, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4484, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4485, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4486, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CONTROL", REG_MMIO, 0x4487, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_MASK", REG_MMIO, 0x4488, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CURRENT", REG_MMIO, 0x4489, NULL, 0, 0, 0 },
+	{ "mmDCP5_DVMM_PTE_CONTROL", REG_MMIO, 0x448a, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_LAST", REG_MMIO, 0x448b, NULL, 0, 0, 0 },
+	{ "mmDCP5_DVMM_PTE_ARB_CONTROL", REG_MMIO, 0x448c, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG", REG_MMIO, 0x448d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x448e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x449, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_GSL_CONTROL", REG_MMIO, 0x4490, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4491, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG_SG", REG_MMIO, 0x4492, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DVMM_DEBUG", REG_MMIO, 0x4493, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG_SG2", REG_MMIO, 0x4494, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4495, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4496, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4497, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG2", REG_MMIO, 0x4498, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4499, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_STEREO_CONTROL", REG_MMIO, 0x449a, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x449c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x449d, NULL, 0, 0, 0 },
+	{ "mmDCP5_HW_ROTATION", REG_MMIO, 0x449e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x449f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE", REG_MMIO, 0x44a, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CONTROL", REG_MMIO, 0x44a0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_INDEX", REG_MMIO, 0x44a1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_DATA", REG_MMIO, 0x44a2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x44a3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x44a4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x44a5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x44a6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x44a7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x44a8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x44a9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x44aa, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x44ab, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x44ac, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x44ad, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x44ae, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x44af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x44b, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x44b0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x44b1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x44b2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x44b3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x44b4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x44b5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x44b6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x44b7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x44b8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x44b9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x44ba, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x44bb, NULL, 0, 0, 0 },
+	{ "mmDCP5_ALPHA_CONTROL", REG_MMIO, 0x44bc, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x44bd, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x44be, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x44bf, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DATA_FORMAT", REG_MMIO, 0x44c0, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_MEMORY_CTRL", REG_MMIO, 0x44c1, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x44c2, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DESKTOP_HEIGHT", REG_MMIO, 0x44c3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE_START_END", REG_MMIO, 0x44c4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE2_START_END", REG_MMIO, 0x44c5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_V_COUNTER", REG_MMIO, 0x44c6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x44c7, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_INTERRUPT_MASK", REG_MMIO, 0x44c8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE_STATUS", REG_MMIO, 0x44c9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE2_STATUS", REG_MMIO, 0x44ca, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VBLANK_STATUS", REG_MMIO, 0x44cb, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SYNC_RESET_SEL", REG_MMIO, 0x44cc, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x44cd, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x44ce, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x44cf, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x44d0, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x44d1, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x44d2, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x44d3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x44d4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x44d5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x44d6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x44d7, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x44d8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x44d9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_STATUS", REG_MMIO, 0x44da, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x44dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x44e, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_MODE", REG_MMIO, 0x44e0, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x44e1, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x44e2, NULL, 0, 0, 0 },
+	{ "mmLB5_DC_MVP_LB_CONTROL", REG_MMIO, 0x44e3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG", REG_MMIO, 0x44e4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG2", REG_MMIO, 0x44e5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG3", REG_MMIO, 0x44e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x44f, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x44fe, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_DATA", REG_MMIO, 0x44ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x450, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4500, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_SOFT_RESET", REG_MMIO, 0x4501, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_DBG_CONFIG", REG_MMIO, 0x4502, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x4503, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x4504, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x4505, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_MISC", REG_MMIO, 0x4506, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x451, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x452, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFCOUNTER_CNTL", REG_MMIO, 0x4524, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFCOUNTER_STATE", REG_MMIO, 0x4525, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4526, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CNTL", REG_MMIO, 0x4527, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CVALUE_LOW", REG_MMIO, 0x4528, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_HI", REG_MMIO, 0x4529, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_LOW", REG_MMIO, 0x452a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x452b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x452c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CNTL2", REG_MMIO, 0x452e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT", REG_MMIO, 0x453, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4530, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4531, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4532, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4533, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4534, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4535, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4536, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4537, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4538, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4539, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_REPEATER_PROGRAM", REG_MMIO, 0x453a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_A", REG_MMIO, 0x453b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_B", REG_MMIO, 0x453c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_11", REG_MMIO, 0x453d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x453e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x454, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4540, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4541, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE", REG_MMIO, 0x4542, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TAP_CONTROL", REG_MMIO, 0x4543, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_CONTROL", REG_MMIO, 0x4544, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_BYPASS_CONTROL", REG_MMIO, 0x4545, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4546, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4547, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4548, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4549, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x454a, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x454b, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x454c, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT", REG_MMIO, 0x454d, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x454e, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ROUND_OFFSET", REG_MMIO, 0x454f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x455, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_UPDATE", REG_MMIO, 0x4551, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4553, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ALU_CONTROL", REG_MMIO, 0x4554, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4555, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_START_SECONDARY", REG_MMIO, 0x455b, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_START", REG_MMIO, 0x455c, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_SIZE", REG_MMIO, 0x455d, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x455e, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x455f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x456, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4560, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4561, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4562, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4563, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG2", REG_MMIO, 0x4569, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG", REG_MMIO, 0x456a, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x456b, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x456c, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_CONTROL", REG_MMIO, 0x456d, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_SM_CONTROL2", REG_MMIO, 0x456e, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_CONTROL2", REG_MMIO, 0x456f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x457, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_UPDATE", REG_MMIO, 0x4570, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4571, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4573, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_DEBUG", REG_MMIO, 0x4574, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4575, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4576, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4577, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4578, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4579, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_WINDOW", REG_MMIO, 0x457a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_CONTROL", REG_MMIO, 0x457b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x457d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x458, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_TOTAL", REG_MMIO, 0x4580, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_START_END", REG_MMIO, 0x4581, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A", REG_MMIO, 0x4582, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4583, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B", REG_MMIO, 0x4584, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4585, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VBI_END", REG_MMIO, 0x4586, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL", REG_MMIO, 0x4587, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4588, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4589, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x458a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x458b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x458c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_BLANK_START_END", REG_MMIO, 0x458d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A", REG_MMIO, 0x458e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x458f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x459, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B", REG_MMIO, 0x4590, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4591, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4592, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4593, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_CNTL", REG_MMIO, 0x4594, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4595, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_CNTL", REG_MMIO, 0x4596, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4597, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4598, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FLOW_CONTROL", REG_MMIO, 0x4599, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x459a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x459b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CONTROL", REG_MMIO, 0x459c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_CONTROL", REG_MMIO, 0x459d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x459e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_STATUS", REG_MMIO, 0x459f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE", REG_MMIO, 0x45a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x45a0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x45a1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x45a2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS", REG_MMIO, 0x45a3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_POSITION", REG_MMIO, 0x45a4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x45a5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x45a6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x45a7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x45a8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_CONTROL", REG_MMIO, 0x45a9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_RESET", REG_MMIO, 0x45aa, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x45ab, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x45ac, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_STATUS", REG_MMIO, 0x45ad, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_CONTROL", REG_MMIO, 0x45ae, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x45af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x45b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x45b0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x45b1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x45b2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_START_LINE_CONTROL", REG_MMIO, 0x45b3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x45b4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_UPDATE_LOCK", REG_MMIO, 0x45b5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x45b6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x45b7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x45ba, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x45bb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x45bc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x45bd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x45be, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x45bf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x45c0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_STATUS", REG_MMIO, 0x45c1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_EN", REG_MMIO, 0x45c2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x45c3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x45c4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x45c6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x45c7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x45c8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x45c9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x45ca, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x45cb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR", REG_MMIO, 0x45cc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x45cd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x45ce, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x45cf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x45d0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x45d1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x45d2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x45d3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC_CNTL", REG_MMIO, 0x45d4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x45d5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x45d6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x45d7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x45d8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_DATA_RG", REG_MMIO, 0x45d9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_DATA_B", REG_MMIO, 0x45da, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x45db, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x45dc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x45dd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x45de, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_DATA_RG", REG_MMIO, 0x45df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x45e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_DATA_B", REG_MMIO, 0x45e0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x45e7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x45e8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x45e9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x45ea, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x45eb, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x45ec, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x45ed, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CONTROL", REG_MMIO, 0x45ee, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x45f, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x45f2, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x45f3, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x45f4, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x45f5, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x45f6, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x45f7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x45f8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_CNTL", REG_MMIO, 0x45f9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_CNTL", REG_MMIO, 0x45fa, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x45fb, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x45fc, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x45fd, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x45fe, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DEBUG_CNTL", REG_MMIO, 0x45ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CNTL", REG_MMIO, 0x460, &mmXDMA_SLV_CNTL[0], sizeof(mmXDMA_SLV_CNTL)/sizeof(mmXDMA_SLV_CNTL[0]), 0, 0 },
+	{ "mmUNP_GRPH_ENABLE", REG_MMIO, 0x4600, &mmUNP_GRPH_ENABLE[0], sizeof(mmUNP_GRPH_ENABLE)/sizeof(mmUNP_GRPH_ENABLE[0]), 0, 0 },
+	{ "mmUNP_GRPH_CONTROL", REG_MMIO, 0x4601, &mmUNP_GRPH_CONTROL[0], sizeof(mmUNP_GRPH_CONTROL)/sizeof(mmUNP_GRPH_CONTROL[0]), 0, 0 },
+	{ "mmUNP_GRPH_CONTROL_C", REG_MMIO, 0x4602, &mmUNP_GRPH_CONTROL_C[0], sizeof(mmUNP_GRPH_CONTROL_C)/sizeof(mmUNP_GRPH_CONTROL_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_CONTROL_EXP", REG_MMIO, 0x4603, &mmUNP_GRPH_CONTROL_EXP[0], sizeof(mmUNP_GRPH_CONTROL_EXP)/sizeof(mmUNP_GRPH_CONTROL_EXP[0]), 0, 0 },
+	{ "mmUNP_DVMM_PTE_CONTROL_C", REG_MMIO, 0x4604, &mmUNP_DVMM_PTE_CONTROL_C[0], sizeof(mmUNP_DVMM_PTE_CONTROL_C)/sizeof(mmUNP_DVMM_PTE_CONTROL_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SWAP_CNTL", REG_MMIO, 0x4605, &mmUNP_GRPH_SWAP_CNTL[0], sizeof(mmUNP_GRPH_SWAP_CNTL)/sizeof(mmUNP_GRPH_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L", REG_MMIO, 0x4606, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x4607, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4608, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4609, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x460a, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x460b, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x460c, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x460d, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L", REG_MMIO, 0x460e, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x460f, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_CLIENT_CONFIG", REG_MMIO, 0x461, &mmXDMA_SLV_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4610, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4611, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x4612, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x4613, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4614, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4615, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_PITCH_L", REG_MMIO, 0x4616, &mmUNP_GRPH_PITCH_L[0], sizeof(mmUNP_GRPH_PITCH_L)/sizeof(mmUNP_GRPH_PITCH_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_PITCH_C", REG_MMIO, 0x4617, &mmUNP_GRPH_PITCH_C[0], sizeof(mmUNP_GRPH_PITCH_C)/sizeof(mmUNP_GRPH_PITCH_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_X_L", REG_MMIO, 0x4618, &mmUNP_GRPH_SURFACE_OFFSET_X_L[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_L)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_X_C", REG_MMIO, 0x4619, &mmUNP_GRPH_SURFACE_OFFSET_X_C[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_C)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_Y_L", REG_MMIO, 0x461a, &mmUNP_GRPH_SURFACE_OFFSET_Y_L[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_L)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_Y_C", REG_MMIO, 0x461b, &mmUNP_GRPH_SURFACE_OFFSET_Y_C[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_C)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_X_START_L", REG_MMIO, 0x461c, &mmUNP_GRPH_X_START_L[0], sizeof(mmUNP_GRPH_X_START_L)/sizeof(mmUNP_GRPH_X_START_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_X_START_C", REG_MMIO, 0x461d, &mmUNP_GRPH_X_START_C[0], sizeof(mmUNP_GRPH_X_START_C)/sizeof(mmUNP_GRPH_X_START_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_Y_START_L", REG_MMIO, 0x461e, &mmUNP_GRPH_Y_START_L[0], sizeof(mmUNP_GRPH_Y_START_L)/sizeof(mmUNP_GRPH_Y_START_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_Y_START_C", REG_MMIO, 0x461f, &mmUNP_GRPH_Y_START_C[0], sizeof(mmUNP_GRPH_Y_START_C)/sizeof(mmUNP_GRPH_Y_START_C[0]), 0, 0 },
+	{ "mmXDMA_SLV_SLS_PITCH", REG_MMIO, 0x462, &mmXDMA_SLV_SLS_PITCH[0], sizeof(mmXDMA_SLV_SLS_PITCH)/sizeof(mmXDMA_SLV_SLS_PITCH[0]), 0, 0 },
+	{ "mmUNP_GRPH_X_END_L", REG_MMIO, 0x4620, &mmUNP_GRPH_X_END_L[0], sizeof(mmUNP_GRPH_X_END_L)/sizeof(mmUNP_GRPH_X_END_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_X_END_C", REG_MMIO, 0x4621, &mmUNP_GRPH_X_END_C[0], sizeof(mmUNP_GRPH_X_END_C)/sizeof(mmUNP_GRPH_X_END_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_Y_END_L", REG_MMIO, 0x4622, &mmUNP_GRPH_Y_END_L[0], sizeof(mmUNP_GRPH_Y_END_L)/sizeof(mmUNP_GRPH_Y_END_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_Y_END_C", REG_MMIO, 0x4623, &mmUNP_GRPH_Y_END_C[0], sizeof(mmUNP_GRPH_Y_END_C)/sizeof(mmUNP_GRPH_Y_END_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_UPDATE", REG_MMIO, 0x4624, &mmUNP_GRPH_UPDATE[0], sizeof(mmUNP_GRPH_UPDATE)/sizeof(mmUNP_GRPH_UPDATE[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L", REG_MMIO, 0x4625, &mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C", REG_MMIO, 0x4626, &mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L", REG_MMIO, 0x4627, &mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[0]), 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C", REG_MMIO, 0x4628, &mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[0]), 0, 0 },
+	{ "mmUNP_DVMM_PTE_CONTROL", REG_MMIO, 0x4629, &mmUNP_DVMM_PTE_CONTROL[0], sizeof(mmUNP_DVMM_PTE_CONTROL)/sizeof(mmUNP_DVMM_PTE_CONTROL[0]), 0, 0 },
+	{ "mmUNP_DVMM_PTE_ARB_CONTROL", REG_MMIO, 0x462a, &mmUNP_DVMM_PTE_ARB_CONTROL[0], sizeof(mmUNP_DVMM_PTE_ARB_CONTROL)/sizeof(mmUNP_DVMM_PTE_ARB_CONTROL[0]), 0, 0 },
+	{ "mmUNP_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x462b, &mmUNP_GRPH_INTERRUPT_STATUS[0], sizeof(mmUNP_GRPH_INTERRUPT_STATUS)/sizeof(mmUNP_GRPH_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmUNP_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x462c, &mmUNP_GRPH_INTERRUPT_CONTROL[0], sizeof(mmUNP_GRPH_INTERRUPT_CONTROL)/sizeof(mmUNP_GRPH_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmUNP_DVMM_PTE_ARB_CONTROL_C", REG_MMIO, 0x462d, &mmUNP_DVMM_PTE_ARB_CONTROL_C[0], sizeof(mmUNP_DVMM_PTE_ARB_CONTROL_C)/sizeof(mmUNP_DVMM_PTE_ARB_CONTROL_C[0]), 0, 0 },
+	{ "mmUNP_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x462e, &mmUNP_GRPH_STEREOSYNC_FLIP[0], sizeof(mmUNP_GRPH_STEREOSYNC_FLIP)/sizeof(mmUNP_GRPH_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmUNP_FLIP_CONTROL", REG_MMIO, 0x462f, &mmUNP_FLIP_CONTROL[0], sizeof(mmUNP_FLIP_CONTROL)/sizeof(mmUNP_FLIP_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_URGENT_CNTL", REG_MMIO, 0x463, &mmXDMA_SLV_READ_URGENT_CNTL[0], sizeof(mmXDMA_SLV_READ_URGENT_CNTL)/sizeof(mmXDMA_SLV_READ_URGENT_CNTL[0]), 0, 0 },
+	{ "mmUNP_CRC_CONTROL", REG_MMIO, 0x4630, &mmUNP_CRC_CONTROL[0], sizeof(mmUNP_CRC_CONTROL)/sizeof(mmUNP_CRC_CONTROL[0]), 0, 0 },
+	{ "mmUNP_CRC_MASK", REG_MMIO, 0x4631, &mmUNP_CRC_MASK[0], sizeof(mmUNP_CRC_MASK)/sizeof(mmUNP_CRC_MASK[0]), 0, 0 },
+	{ "mmUNP_CRC_CURRENT", REG_MMIO, 0x4632, &mmUNP_CRC_CURRENT[0], sizeof(mmUNP_CRC_CURRENT)/sizeof(mmUNP_CRC_CURRENT[0]), 0, 0 },
+	{ "mmUNP_CRC_LAST", REG_MMIO, 0x4633, &mmUNP_CRC_LAST[0], sizeof(mmUNP_CRC_LAST)/sizeof(mmUNP_CRC_LAST[0]), 0, 0 },
+	{ "mmUNP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4634, &mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[0], sizeof(mmUNP_LB_DATA_GAP_BETWEEN_CHUNK)/sizeof(mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[0]), 0, 0 },
+	{ "mmUNP_HW_ROTATION", REG_MMIO, 0x4635, &mmUNP_HW_ROTATION[0], sizeof(mmUNP_HW_ROTATION)/sizeof(mmUNP_HW_ROTATION[0]), 0, 0 },
+	{ "mmUNP_DEBUG", REG_MMIO, 0x4636, &mmUNP_DEBUG[0], sizeof(mmUNP_DEBUG)/sizeof(mmUNP_DEBUG[0]), 0, 0 },
+	{ "mmUNP_DEBUG2", REG_MMIO, 0x4637, &mmUNP_DEBUG2[0], sizeof(mmUNP_DEBUG2)/sizeof(mmUNP_DEBUG2[0]), 0, 0 },
+	{ "mmUNP_TEST_DEBUG_INDEX", REG_MMIO, 0x4638, &mmUNP_TEST_DEBUG_INDEX[0], sizeof(mmUNP_TEST_DEBUG_INDEX)/sizeof(mmUNP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmUNP_TEST_DEBUG_DATA", REG_MMIO, 0x4639, &mmUNP_TEST_DEBUG_DATA[0], sizeof(mmUNP_TEST_DEBUG_DATA)/sizeof(mmUNP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x463a, &mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT[0], sizeof(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT)/sizeof(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT[0]), 0, 0 },
+	{ "mmUNP_DVMM_DEBUG", REG_MMIO, 0x463b, &mmUNP_DVMM_DEBUG[0], sizeof(mmUNP_DVMM_DEBUG)/sizeof(mmUNP_DVMM_DEBUG[0]), 0, 0 },
+	{ "mmLBV_DATA_FORMAT", REG_MMIO, 0x463c, &mmLBV_DATA_FORMAT[0], sizeof(mmLBV_DATA_FORMAT)/sizeof(mmLBV_DATA_FORMAT[0]), 0, 0 },
+	{ "mmLBV_MEMORY_CTRL", REG_MMIO, 0x463d, &mmLBV_MEMORY_CTRL[0], sizeof(mmLBV_MEMORY_CTRL)/sizeof(mmLBV_MEMORY_CTRL[0]), 0, 0 },
+	{ "mmLBV_MEMORY_SIZE_STATUS", REG_MMIO, 0x463e, &mmLBV_MEMORY_SIZE_STATUS[0], sizeof(mmLBV_MEMORY_SIZE_STATUS)/sizeof(mmLBV_MEMORY_SIZE_STATUS[0]), 0, 0 },
+	{ "mmLBV_DESKTOP_HEIGHT", REG_MMIO, 0x463f, &mmLBV_DESKTOP_HEIGHT[0], sizeof(mmLBV_DESKTOP_HEIGHT)/sizeof(mmLBV_DESKTOP_HEIGHT[0]), 0, 0 },
+	{ "mmXDMA_SLV_WRITE_URGENT_CNTL", REG_MMIO, 0x464, &mmXDMA_SLV_WRITE_URGENT_CNTL[0], sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL)/sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL[0]), 0, 0 },
+	{ "mmLBV_VLINE_START_END", REG_MMIO, 0x4640, &mmLBV_VLINE_START_END[0], sizeof(mmLBV_VLINE_START_END)/sizeof(mmLBV_VLINE_START_END[0]), 0, 0 },
+	{ "mmLBV_VLINE2_START_END", REG_MMIO, 0x4641, &mmLBV_VLINE2_START_END[0], sizeof(mmLBV_VLINE2_START_END)/sizeof(mmLBV_VLINE2_START_END[0]), 0, 0 },
+	{ "mmLBV_V_COUNTER", REG_MMIO, 0x4642, &mmLBV_V_COUNTER[0], sizeof(mmLBV_V_COUNTER)/sizeof(mmLBV_V_COUNTER[0]), 0, 0 },
+	{ "mmLBV_SNAPSHOT_V_COUNTER", REG_MMIO, 0x4643, &mmLBV_SNAPSHOT_V_COUNTER[0], sizeof(mmLBV_SNAPSHOT_V_COUNTER)/sizeof(mmLBV_SNAPSHOT_V_COUNTER[0]), 0, 0 },
+	{ "mmLBV_V_COUNTER_CHROMA", REG_MMIO, 0x4644, &mmLBV_V_COUNTER_CHROMA[0], sizeof(mmLBV_V_COUNTER_CHROMA)/sizeof(mmLBV_V_COUNTER_CHROMA[0]), 0, 0 },
+	{ "mmLBV_SNAPSHOT_V_COUNTER_CHROMA", REG_MMIO, 0x4645, &mmLBV_SNAPSHOT_V_COUNTER_CHROMA[0], sizeof(mmLBV_SNAPSHOT_V_COUNTER_CHROMA)/sizeof(mmLBV_SNAPSHOT_V_COUNTER_CHROMA[0]), 0, 0 },
+	{ "mmLBV_INTERRUPT_MASK", REG_MMIO, 0x4646, &mmLBV_INTERRUPT_MASK[0], sizeof(mmLBV_INTERRUPT_MASK)/sizeof(mmLBV_INTERRUPT_MASK[0]), 0, 0 },
+	{ "mmLBV_VLINE_STATUS", REG_MMIO, 0x4647, &mmLBV_VLINE_STATUS[0], sizeof(mmLBV_VLINE_STATUS)/sizeof(mmLBV_VLINE_STATUS[0]), 0, 0 },
+	{ "mmLBV_VLINE2_STATUS", REG_MMIO, 0x4648, &mmLBV_VLINE2_STATUS[0], sizeof(mmLBV_VLINE2_STATUS)/sizeof(mmLBV_VLINE2_STATUS[0]), 0, 0 },
+	{ "mmLBV_VBLANK_STATUS", REG_MMIO, 0x4649, &mmLBV_VBLANK_STATUS[0], sizeof(mmLBV_VBLANK_STATUS)/sizeof(mmLBV_VBLANK_STATUS[0]), 0, 0 },
+	{ "mmLBV_SYNC_RESET_SEL", REG_MMIO, 0x464a, &mmLBV_SYNC_RESET_SEL[0], sizeof(mmLBV_SYNC_RESET_SEL)/sizeof(mmLBV_SYNC_RESET_SEL[0]), 0, 0 },
+	{ "mmLBV_BLACK_KEYER_R_CR", REG_MMIO, 0x464b, &mmLBV_BLACK_KEYER_R_CR[0], sizeof(mmLBV_BLACK_KEYER_R_CR)/sizeof(mmLBV_BLACK_KEYER_R_CR[0]), 0, 0 },
+	{ "mmLBV_BLACK_KEYER_G_Y", REG_MMIO, 0x464c, &mmLBV_BLACK_KEYER_G_Y[0], sizeof(mmLBV_BLACK_KEYER_G_Y)/sizeof(mmLBV_BLACK_KEYER_G_Y[0]), 0, 0 },
+	{ "mmLBV_BLACK_KEYER_B_CB", REG_MMIO, 0x464d, &mmLBV_BLACK_KEYER_B_CB[0], sizeof(mmLBV_BLACK_KEYER_B_CB)/sizeof(mmLBV_BLACK_KEYER_B_CB[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_CTRL", REG_MMIO, 0x464e, &mmLBV_KEYER_COLOR_CTRL[0], sizeof(mmLBV_KEYER_COLOR_CTRL)/sizeof(mmLBV_KEYER_COLOR_CTRL[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_R_CR", REG_MMIO, 0x464f, &mmLBV_KEYER_COLOR_R_CR[0], sizeof(mmLBV_KEYER_COLOR_R_CR)/sizeof(mmLBV_KEYER_COLOR_R_CR[0]), 0, 0 },
+	{ "mmXDMA_SLV_WB_RATE_CNTL", REG_MMIO, 0x465, &mmXDMA_SLV_WB_RATE_CNTL[0], sizeof(mmXDMA_SLV_WB_RATE_CNTL)/sizeof(mmXDMA_SLV_WB_RATE_CNTL[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_G_Y", REG_MMIO, 0x4650, &mmLBV_KEYER_COLOR_G_Y[0], sizeof(mmLBV_KEYER_COLOR_G_Y)/sizeof(mmLBV_KEYER_COLOR_G_Y[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_B_CB", REG_MMIO, 0x4651, &mmLBV_KEYER_COLOR_B_CB[0], sizeof(mmLBV_KEYER_COLOR_B_CB)/sizeof(mmLBV_KEYER_COLOR_B_CB[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x4652, &mmLBV_KEYER_COLOR_REP_R_CR[0], sizeof(mmLBV_KEYER_COLOR_REP_R_CR)/sizeof(mmLBV_KEYER_COLOR_REP_R_CR[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x4653, &mmLBV_KEYER_COLOR_REP_G_Y[0], sizeof(mmLBV_KEYER_COLOR_REP_G_Y)/sizeof(mmLBV_KEYER_COLOR_REP_G_Y[0]), 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x4654, &mmLBV_KEYER_COLOR_REP_B_CB[0], sizeof(mmLBV_KEYER_COLOR_REP_B_CB)/sizeof(mmLBV_KEYER_COLOR_REP_B_CB[0]), 0, 0 },
+	{ "mmLBV_BUFFER_LEVEL_STATUS", REG_MMIO, 0x4655, &mmLBV_BUFFER_LEVEL_STATUS[0], sizeof(mmLBV_BUFFER_LEVEL_STATUS)/sizeof(mmLBV_BUFFER_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmLBV_BUFFER_URGENCY_CTRL", REG_MMIO, 0x4656, &mmLBV_BUFFER_URGENCY_CTRL[0], sizeof(mmLBV_BUFFER_URGENCY_CTRL)/sizeof(mmLBV_BUFFER_URGENCY_CTRL[0]), 0, 0 },
+	{ "mmLBV_BUFFER_URGENCY_STATUS", REG_MMIO, 0x4657, &mmLBV_BUFFER_URGENCY_STATUS[0], sizeof(mmLBV_BUFFER_URGENCY_STATUS)/sizeof(mmLBV_BUFFER_URGENCY_STATUS[0]), 0, 0 },
+	{ "mmLBV_BUFFER_STATUS", REG_MMIO, 0x4658, &mmLBV_BUFFER_STATUS[0], sizeof(mmLBV_BUFFER_STATUS)/sizeof(mmLBV_BUFFER_STATUS[0]), 0, 0 },
+	{ "mmLBV_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x4659, &mmLBV_NO_OUTSTANDING_REQ_STATUS[0], sizeof(mmLBV_NO_OUTSTANDING_REQ_STATUS)/sizeof(mmLBV_NO_OUTSTANDING_REQ_STATUS[0]), 0, 0 },
+	{ "mmLBV_DEBUG", REG_MMIO, 0x465a, &mmLBV_DEBUG[0], sizeof(mmLBV_DEBUG)/sizeof(mmLBV_DEBUG[0]), 0, 0 },
+	{ "mmLBV_DEBUG2", REG_MMIO, 0x465b, &mmLBV_DEBUG2[0], sizeof(mmLBV_DEBUG2)/sizeof(mmLBV_DEBUG2[0]), 0, 0 },
+	{ "mmLBV_DEBUG3", REG_MMIO, 0x465c, &mmLBV_DEBUG3[0], sizeof(mmLBV_DEBUG3)/sizeof(mmLBV_DEBUG3[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_MINMAX", REG_MMIO, 0x466, &mmXDMA_SLV_READ_LATENCY_MINMAX[0], sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX)/sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX[0]), 0, 0 },
+	{ "mmLBV_TEST_DEBUG_INDEX", REG_MMIO, 0x4666, &mmLBV_TEST_DEBUG_INDEX[0], sizeof(mmLBV_TEST_DEBUG_INDEX)/sizeof(mmLBV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmLBV_TEST_DEBUG_DATA", REG_MMIO, 0x4667, &mmLBV_TEST_DEBUG_DATA[0], sizeof(mmLBV_TEST_DEBUG_DATA)/sizeof(mmLBV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_AVE", REG_MMIO, 0x467, &mmXDMA_SLV_READ_LATENCY_AVE[0], sizeof(mmXDMA_SLV_READ_LATENCY_AVE)/sizeof(mmXDMA_SLV_READ_LATENCY_AVE[0]), 0, 0 },
+	{ "mmSCLV_COEF_RAM_SELECT", REG_MMIO, 0x4670, &mmSCLV_COEF_RAM_SELECT[0], sizeof(mmSCLV_COEF_RAM_SELECT)/sizeof(mmSCLV_COEF_RAM_SELECT[0]), 0, 0 },
+	{ "mmSCLV_COEF_RAM_TAP_DATA", REG_MMIO, 0x4671, &mmSCLV_COEF_RAM_TAP_DATA[0], sizeof(mmSCLV_COEF_RAM_TAP_DATA)/sizeof(mmSCLV_COEF_RAM_TAP_DATA[0]), 0, 0 },
+	{ "mmSCLV_MODE", REG_MMIO, 0x4672, &mmSCLV_MODE[0], sizeof(mmSCLV_MODE)/sizeof(mmSCLV_MODE[0]), 0, 0 },
+	{ "mmSCLV_TAP_CONTROL", REG_MMIO, 0x4673, &mmSCLV_TAP_CONTROL[0], sizeof(mmSCLV_TAP_CONTROL)/sizeof(mmSCLV_TAP_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_CONTROL", REG_MMIO, 0x4674, &mmSCLV_CONTROL[0], sizeof(mmSCLV_CONTROL)/sizeof(mmSCLV_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4675, &mmSCLV_MANUAL_REPLICATE_CONTROL[0], sizeof(mmSCLV_MANUAL_REPLICATE_CONTROL)/sizeof(mmSCLV_MANUAL_REPLICATE_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4676, &mmSCLV_AUTOMATIC_MODE_CONTROL[0], sizeof(mmSCLV_AUTOMATIC_MODE_CONTROL)/sizeof(mmSCLV_AUTOMATIC_MODE_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_CONTROL", REG_MMIO, 0x4677, &mmSCLV_HORZ_FILTER_CONTROL[0], sizeof(mmSCLV_HORZ_FILTER_CONTROL)/sizeof(mmSCLV_HORZ_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4678, &mmSCLV_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO)/sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT", REG_MMIO, 0x4679, &mmSCLV_HORZ_FILTER_INIT[0], sizeof(mmSCLV_HORZ_FILTER_INIT)/sizeof(mmSCLV_HORZ_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x467a, &mmSCLV_HORZ_FILTER_SCALE_RATIO_C[0], sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO_C)/sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO_C[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT_C", REG_MMIO, 0x467b, &mmSCLV_HORZ_FILTER_INIT_C[0], sizeof(mmSCLV_HORZ_FILTER_INIT_C)/sizeof(mmSCLV_HORZ_FILTER_INIT_C[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_CONTROL", REG_MMIO, 0x467c, &mmSCLV_VERT_FILTER_CONTROL[0], sizeof(mmSCLV_VERT_FILTER_CONTROL)/sizeof(mmSCLV_VERT_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x467d, &mmSCLV_VERT_FILTER_SCALE_RATIO[0], sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO)/sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT", REG_MMIO, 0x467e, &mmSCLV_VERT_FILTER_INIT[0], sizeof(mmSCLV_VERT_FILTER_INIT)/sizeof(mmSCLV_VERT_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_BOT", REG_MMIO, 0x467f, &mmSCLV_VERT_FILTER_INIT_BOT[0], sizeof(mmSCLV_VERT_FILTER_INIT_BOT)/sizeof(mmSCLV_VERT_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmXDMA_SLV_PCIE_NACK_STATUS", REG_MMIO, 0x468, &mmXDMA_SLV_PCIE_NACK_STATUS[0], sizeof(mmXDMA_SLV_PCIE_NACK_STATUS)/sizeof(mmXDMA_SLV_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x4680, &mmSCLV_VERT_FILTER_SCALE_RATIO_C[0], sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO_C)/sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO_C[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_C", REG_MMIO, 0x4681, &mmSCLV_VERT_FILTER_INIT_C[0], sizeof(mmSCLV_VERT_FILTER_INIT_C)/sizeof(mmSCLV_VERT_FILTER_INIT_C[0]), 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x4682, &mmSCLV_VERT_FILTER_INIT_BOT_C[0], sizeof(mmSCLV_VERT_FILTER_INIT_BOT_C)/sizeof(mmSCLV_VERT_FILTER_INIT_BOT_C[0]), 0, 0 },
+	{ "mmSCLV_ROUND_OFFSET", REG_MMIO, 0x4683, &mmSCLV_ROUND_OFFSET[0], sizeof(mmSCLV_ROUND_OFFSET)/sizeof(mmSCLV_ROUND_OFFSET[0]), 0, 0 },
+	{ "mmSCLV_UPDATE", REG_MMIO, 0x4684, &mmSCLV_UPDATE[0], sizeof(mmSCLV_UPDATE)/sizeof(mmSCLV_UPDATE[0]), 0, 0 },
+	{ "mmSCLV_ALU_CONTROL", REG_MMIO, 0x4685, &mmSCLV_ALU_CONTROL[0], sizeof(mmSCLV_ALU_CONTROL)/sizeof(mmSCLV_ALU_CONTROL[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_START", REG_MMIO, 0x4686, &mmSCLV_VIEWPORT_START[0], sizeof(mmSCLV_VIEWPORT_START)/sizeof(mmSCLV_VIEWPORT_START[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_SECONDARY", REG_MMIO, 0x4687, &mmSCLV_VIEWPORT_START_SECONDARY[0], sizeof(mmSCLV_VIEWPORT_START_SECONDARY)/sizeof(mmSCLV_VIEWPORT_START_SECONDARY[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_SIZE", REG_MMIO, 0x4688, &mmSCLV_VIEWPORT_SIZE[0], sizeof(mmSCLV_VIEWPORT_SIZE)/sizeof(mmSCLV_VIEWPORT_SIZE[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_C", REG_MMIO, 0x4689, &mmSCLV_VIEWPORT_START_C[0], sizeof(mmSCLV_VIEWPORT_START_C)/sizeof(mmSCLV_VIEWPORT_START_C[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_SECONDARY_C", REG_MMIO, 0x468a, &mmSCLV_VIEWPORT_START_SECONDARY_C[0], sizeof(mmSCLV_VIEWPORT_START_SECONDARY_C)/sizeof(mmSCLV_VIEWPORT_START_SECONDARY_C[0]), 0, 0 },
+	{ "mmSCLV_VIEWPORT_SIZE_C", REG_MMIO, 0x468b, &mmSCLV_VIEWPORT_SIZE_C[0], sizeof(mmSCLV_VIEWPORT_SIZE_C)/sizeof(mmSCLV_VIEWPORT_SIZE_C[0]), 0, 0 },
+	{ "mmSCLV_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x468c, &mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmSCLV_EXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 },
+	{ "mmSCLV_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x468d, &mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmSCLV_EXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET1", REG_MMIO, 0x468e, &mmSCLV_MODE_CHANGE_DET1[0], sizeof(mmSCLV_MODE_CHANGE_DET1)/sizeof(mmSCLV_MODE_CHANGE_DET1[0]), 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET2", REG_MMIO, 0x468f, &mmSCLV_MODE_CHANGE_DET2[0], sizeof(mmSCLV_MODE_CHANGE_DET2)/sizeof(mmSCLV_MODE_CHANGE_DET2[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_NACK_STATUS", REG_MMIO, 0x469, &mmXDMA_SLV_MEM_NACK_STATUS[0], sizeof(mmXDMA_SLV_MEM_NACK_STATUS)/sizeof(mmXDMA_SLV_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET3", REG_MMIO, 0x4690, &mmSCLV_MODE_CHANGE_DET3[0], sizeof(mmSCLV_MODE_CHANGE_DET3)/sizeof(mmSCLV_MODE_CHANGE_DET3[0]), 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_MASK", REG_MMIO, 0x4691, &mmSCLV_MODE_CHANGE_MASK[0], sizeof(mmSCLV_MODE_CHANGE_MASK)/sizeof(mmSCLV_MODE_CHANGE_MASK[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT_BOT", REG_MMIO, 0x4692, &mmSCLV_HORZ_FILTER_INIT_BOT[0], sizeof(mmSCLV_HORZ_FILTER_INIT_BOT)/sizeof(mmSCLV_HORZ_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT_BOT_C", REG_MMIO, 0x4693, &mmSCLV_HORZ_FILTER_INIT_BOT_C[0], sizeof(mmSCLV_HORZ_FILTER_INIT_BOT_C)/sizeof(mmSCLV_HORZ_FILTER_INIT_BOT_C[0]), 0, 0 },
+	{ "mmSCLV_DEBUG2", REG_MMIO, 0x4694, &mmSCLV_DEBUG2[0], sizeof(mmSCLV_DEBUG2)/sizeof(mmSCLV_DEBUG2[0]), 0, 0 },
+	{ "mmSCLV_DEBUG", REG_MMIO, 0x4695, &mmSCLV_DEBUG[0], sizeof(mmSCLV_DEBUG)/sizeof(mmSCLV_DEBUG[0]), 0, 0 },
+	{ "mmSCLV_TEST_DEBUG_INDEX", REG_MMIO, 0x4696, &mmSCLV_TEST_DEBUG_INDEX[0], sizeof(mmSCLV_TEST_DEBUG_INDEX)/sizeof(mmSCLV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmSCLV_TEST_DEBUG_DATA", REG_MMIO, 0x4697, &mmSCLV_TEST_DEBUG_DATA[0], sizeof(mmSCLV_TEST_DEBUG_DATA)/sizeof(mmSCLV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_SLV_RDRET_BUF_STATUS", REG_MMIO, 0x46a, &mmXDMA_SLV_RDRET_BUF_STATUS[0], sizeof(mmXDMA_SLV_RDRET_BUF_STATUS)/sizeof(mmXDMA_SLV_RDRET_BUF_STATUS[0]), 0, 0 },
+	{ "mmCOL_MAN_UPDATE", REG_MMIO, 0x46a4, &mmCOL_MAN_UPDATE[0], sizeof(mmCOL_MAN_UPDATE)/sizeof(mmCOL_MAN_UPDATE[0]), 0, 0 },
+	{ "mmCOL_MAN_INPUT_CSC_CONTROL", REG_MMIO, 0x46a5, &mmCOL_MAN_INPUT_CSC_CONTROL[0], sizeof(mmCOL_MAN_INPUT_CSC_CONTROL)/sizeof(mmCOL_MAN_INPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmINPUT_CSC_C11_C12_A", REG_MMIO, 0x46a6, &mmINPUT_CSC_C11_C12_A[0], sizeof(mmINPUT_CSC_C11_C12_A)/sizeof(mmINPUT_CSC_C11_C12_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C13_C14_A", REG_MMIO, 0x46a7, &mmINPUT_CSC_C13_C14_A[0], sizeof(mmINPUT_CSC_C13_C14_A)/sizeof(mmINPUT_CSC_C13_C14_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C21_C22_A", REG_MMIO, 0x46a8, &mmINPUT_CSC_C21_C22_A[0], sizeof(mmINPUT_CSC_C21_C22_A)/sizeof(mmINPUT_CSC_C21_C22_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C23_C24_A", REG_MMIO, 0x46a9, &mmINPUT_CSC_C23_C24_A[0], sizeof(mmINPUT_CSC_C23_C24_A)/sizeof(mmINPUT_CSC_C23_C24_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C31_C32_A", REG_MMIO, 0x46aa, &mmINPUT_CSC_C31_C32_A[0], sizeof(mmINPUT_CSC_C31_C32_A)/sizeof(mmINPUT_CSC_C31_C32_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C33_C34_A", REG_MMIO, 0x46ab, &mmINPUT_CSC_C33_C34_A[0], sizeof(mmINPUT_CSC_C33_C34_A)/sizeof(mmINPUT_CSC_C33_C34_A[0]), 0, 0 },
+	{ "mmINPUT_CSC_C11_C12_B", REG_MMIO, 0x46ac, &mmINPUT_CSC_C11_C12_B[0], sizeof(mmINPUT_CSC_C11_C12_B)/sizeof(mmINPUT_CSC_C11_C12_B[0]), 0, 0 },
+	{ "mmINPUT_CSC_C13_C14_B", REG_MMIO, 0x46ad, &mmINPUT_CSC_C13_C14_B[0], sizeof(mmINPUT_CSC_C13_C14_B)/sizeof(mmINPUT_CSC_C13_C14_B[0]), 0, 0 },
+	{ "mmINPUT_CSC_C21_C22_B", REG_MMIO, 0x46ae, &mmINPUT_CSC_C21_C22_B[0], sizeof(mmINPUT_CSC_C21_C22_B)/sizeof(mmINPUT_CSC_C21_C22_B[0]), 0, 0 },
+	{ "mmINPUT_CSC_C23_C24_B", REG_MMIO, 0x46af, &mmINPUT_CSC_C23_C24_B[0], sizeof(mmINPUT_CSC_C23_C24_B)/sizeof(mmINPUT_CSC_C23_C24_B[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_TIMER", REG_MMIO, 0x46b, &mmXDMA_SLV_READ_LATENCY_TIMER[0], sizeof(mmXDMA_SLV_READ_LATENCY_TIMER)/sizeof(mmXDMA_SLV_READ_LATENCY_TIMER[0]), 0, 0 },
+	{ "mmINPUT_CSC_C31_C32_B", REG_MMIO, 0x46b0, &mmINPUT_CSC_C31_C32_B[0], sizeof(mmINPUT_CSC_C31_C32_B)/sizeof(mmINPUT_CSC_C31_C32_B[0]), 0, 0 },
+	{ "mmINPUT_CSC_C33_C34_B", REG_MMIO, 0x46b1, &mmINPUT_CSC_C33_C34_B[0], sizeof(mmINPUT_CSC_C33_C34_B)/sizeof(mmINPUT_CSC_C33_C34_B[0]), 0, 0 },
+	{ "mmPRESCALE_CONTROL", REG_MMIO, 0x46b2, &mmPRESCALE_CONTROL[0], sizeof(mmPRESCALE_CONTROL)/sizeof(mmPRESCALE_CONTROL[0]), 0, 0 },
+	{ "mmPRESCALE_VALUES_R", REG_MMIO, 0x46b3, &mmPRESCALE_VALUES_R[0], sizeof(mmPRESCALE_VALUES_R)/sizeof(mmPRESCALE_VALUES_R[0]), 0, 0 },
+	{ "mmPRESCALE_VALUES_G", REG_MMIO, 0x46b4, &mmPRESCALE_VALUES_G[0], sizeof(mmPRESCALE_VALUES_G)/sizeof(mmPRESCALE_VALUES_G[0]), 0, 0 },
+	{ "mmPRESCALE_VALUES_B", REG_MMIO, 0x46b5, &mmPRESCALE_VALUES_B[0], sizeof(mmPRESCALE_VALUES_B)/sizeof(mmPRESCALE_VALUES_B[0]), 0, 0 },
+	{ "mmCOL_MAN_OUTPUT_CSC_CONTROL", REG_MMIO, 0x46b6, &mmCOL_MAN_OUTPUT_CSC_CONTROL[0], sizeof(mmCOL_MAN_OUTPUT_CSC_CONTROL)/sizeof(mmCOL_MAN_OUTPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12_A", REG_MMIO, 0x46b7, &mmOUTPUT_CSC_C11_C12_A[0], sizeof(mmOUTPUT_CSC_C11_C12_A)/sizeof(mmOUTPUT_CSC_C11_C12_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14_A", REG_MMIO, 0x46b8, &mmOUTPUT_CSC_C13_C14_A[0], sizeof(mmOUTPUT_CSC_C13_C14_A)/sizeof(mmOUTPUT_CSC_C13_C14_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22_A", REG_MMIO, 0x46b9, &mmOUTPUT_CSC_C21_C22_A[0], sizeof(mmOUTPUT_CSC_C21_C22_A)/sizeof(mmOUTPUT_CSC_C21_C22_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24_A", REG_MMIO, 0x46ba, &mmOUTPUT_CSC_C23_C24_A[0], sizeof(mmOUTPUT_CSC_C23_C24_A)/sizeof(mmOUTPUT_CSC_C23_C24_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32_A", REG_MMIO, 0x46bb, &mmOUTPUT_CSC_C31_C32_A[0], sizeof(mmOUTPUT_CSC_C31_C32_A)/sizeof(mmOUTPUT_CSC_C31_C32_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34_A", REG_MMIO, 0x46bc, &mmOUTPUT_CSC_C33_C34_A[0], sizeof(mmOUTPUT_CSC_C33_C34_A)/sizeof(mmOUTPUT_CSC_C33_C34_A[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12_B", REG_MMIO, 0x46bd, &mmOUTPUT_CSC_C11_C12_B[0], sizeof(mmOUTPUT_CSC_C11_C12_B)/sizeof(mmOUTPUT_CSC_C11_C12_B[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14_B", REG_MMIO, 0x46be, &mmOUTPUT_CSC_C13_C14_B[0], sizeof(mmOUTPUT_CSC_C13_C14_B)/sizeof(mmOUTPUT_CSC_C13_C14_B[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22_B", REG_MMIO, 0x46bf, &mmOUTPUT_CSC_C21_C22_B[0], sizeof(mmOUTPUT_CSC_C21_C22_B)/sizeof(mmOUTPUT_CSC_C21_C22_B[0]), 0, 0 },
+	{ "mmXDMA_SLV_FLIP_PENDING", REG_MMIO, 0x46c, &mmXDMA_SLV_FLIP_PENDING[0], sizeof(mmXDMA_SLV_FLIP_PENDING)/sizeof(mmXDMA_SLV_FLIP_PENDING[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24_B", REG_MMIO, 0x46c0, &mmOUTPUT_CSC_C23_C24_B[0], sizeof(mmOUTPUT_CSC_C23_C24_B)/sizeof(mmOUTPUT_CSC_C23_C24_B[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32_B", REG_MMIO, 0x46c1, &mmOUTPUT_CSC_C31_C32_B[0], sizeof(mmOUTPUT_CSC_C31_C32_B)/sizeof(mmOUTPUT_CSC_C31_C32_B[0]), 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34_B", REG_MMIO, 0x46c2, &mmOUTPUT_CSC_C33_C34_B[0], sizeof(mmOUTPUT_CSC_C33_C34_B)/sizeof(mmOUTPUT_CSC_C33_C34_B[0]), 0, 0 },
+	{ "mmDENORM_CLAMP_CONTROL", REG_MMIO, 0x46c3, &mmDENORM_CLAMP_CONTROL[0], sizeof(mmDENORM_CLAMP_CONTROL)/sizeof(mmDENORM_CLAMP_CONTROL[0]), 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_R_CR", REG_MMIO, 0x46c4, &mmDENORM_CLAMP_RANGE_R_CR[0], sizeof(mmDENORM_CLAMP_RANGE_R_CR)/sizeof(mmDENORM_CLAMP_RANGE_R_CR[0]), 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_G_Y", REG_MMIO, 0x46c5, &mmDENORM_CLAMP_RANGE_G_Y[0], sizeof(mmDENORM_CLAMP_RANGE_G_Y)/sizeof(mmDENORM_CLAMP_RANGE_G_Y[0]), 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_B_CB", REG_MMIO, 0x46c6, &mmDENORM_CLAMP_RANGE_B_CB[0], sizeof(mmDENORM_CLAMP_RANGE_B_CB)/sizeof(mmDENORM_CLAMP_RANGE_B_CB[0]), 0, 0 },
+	{ "mmCOL_MAN_FP_CONVERTED_FIELD", REG_MMIO, 0x46c7, &mmCOL_MAN_FP_CONVERTED_FIELD[0], sizeof(mmCOL_MAN_FP_CONVERTED_FIELD)/sizeof(mmCOL_MAN_FP_CONVERTED_FIELD[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CONTROL", REG_MMIO, 0x46c8, &mmGAMMA_CORR_CONTROL[0], sizeof(mmGAMMA_CORR_CONTROL)/sizeof(mmGAMMA_CORR_CONTROL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_LUT_INDEX", REG_MMIO, 0x46c9, &mmGAMMA_CORR_LUT_INDEX[0], sizeof(mmGAMMA_CORR_LUT_INDEX)/sizeof(mmGAMMA_CORR_LUT_INDEX[0]), 0, 0 },
+	{ "mmGAMMA_CORR_LUT_DATA", REG_MMIO, 0x46ca, &mmGAMMA_CORR_LUT_DATA[0], sizeof(mmGAMMA_CORR_LUT_DATA)/sizeof(mmGAMMA_CORR_LUT_DATA[0]), 0, 0 },
+	{ "mmGAMMA_CORR_LUT_WRITE_EN_MASK", REG_MMIO, 0x46cb, &mmGAMMA_CORR_LUT_WRITE_EN_MASK[0], sizeof(mmGAMMA_CORR_LUT_WRITE_EN_MASK)/sizeof(mmGAMMA_CORR_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_START_CNTL", REG_MMIO, 0x46cc, &mmGAMMA_CORR_CNTLA_START_CNTL[0], sizeof(mmGAMMA_CORR_CNTLA_START_CNTL)/sizeof(mmGAMMA_CORR_CNTLA_START_CNTL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_SLOPE_CNTL", REG_MMIO, 0x46cd, &mmGAMMA_CORR_CNTLA_SLOPE_CNTL[0], sizeof(mmGAMMA_CORR_CNTLA_SLOPE_CNTL)/sizeof(mmGAMMA_CORR_CNTLA_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_END_CNTL1", REG_MMIO, 0x46ce, &mmGAMMA_CORR_CNTLA_END_CNTL1[0], sizeof(mmGAMMA_CORR_CNTLA_END_CNTL1)/sizeof(mmGAMMA_CORR_CNTLA_END_CNTL1[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_END_CNTL2", REG_MMIO, 0x46cf, &mmGAMMA_CORR_CNTLA_END_CNTL2[0], sizeof(mmGAMMA_CORR_CNTLA_END_CNTL2)/sizeof(mmGAMMA_CORR_CNTLA_END_CNTL2[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_0_1", REG_MMIO, 0x46d0, &mmGAMMA_CORR_CNTLA_REGION_0_1[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_0_1)/sizeof(mmGAMMA_CORR_CNTLA_REGION_0_1[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_2_3", REG_MMIO, 0x46d1, &mmGAMMA_CORR_CNTLA_REGION_2_3[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_2_3)/sizeof(mmGAMMA_CORR_CNTLA_REGION_2_3[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_4_5", REG_MMIO, 0x46d2, &mmGAMMA_CORR_CNTLA_REGION_4_5[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_4_5)/sizeof(mmGAMMA_CORR_CNTLA_REGION_4_5[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_6_7", REG_MMIO, 0x46d3, &mmGAMMA_CORR_CNTLA_REGION_6_7[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_6_7)/sizeof(mmGAMMA_CORR_CNTLA_REGION_6_7[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_8_9", REG_MMIO, 0x46d4, &mmGAMMA_CORR_CNTLA_REGION_8_9[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_8_9)/sizeof(mmGAMMA_CORR_CNTLA_REGION_8_9[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_10_11", REG_MMIO, 0x46d5, &mmGAMMA_CORR_CNTLA_REGION_10_11[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_10_11)/sizeof(mmGAMMA_CORR_CNTLA_REGION_10_11[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_12_13", REG_MMIO, 0x46d6, &mmGAMMA_CORR_CNTLA_REGION_12_13[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_12_13)/sizeof(mmGAMMA_CORR_CNTLA_REGION_12_13[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_14_15", REG_MMIO, 0x46d7, &mmGAMMA_CORR_CNTLA_REGION_14_15[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_14_15)/sizeof(mmGAMMA_CORR_CNTLA_REGION_14_15[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_START_CNTL", REG_MMIO, 0x46d8, &mmGAMMA_CORR_CNTLB_START_CNTL[0], sizeof(mmGAMMA_CORR_CNTLB_START_CNTL)/sizeof(mmGAMMA_CORR_CNTLB_START_CNTL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_SLOPE_CNTL", REG_MMIO, 0x46d9, &mmGAMMA_CORR_CNTLB_SLOPE_CNTL[0], sizeof(mmGAMMA_CORR_CNTLB_SLOPE_CNTL)/sizeof(mmGAMMA_CORR_CNTLB_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_END_CNTL1", REG_MMIO, 0x46da, &mmGAMMA_CORR_CNTLB_END_CNTL1[0], sizeof(mmGAMMA_CORR_CNTLB_END_CNTL1)/sizeof(mmGAMMA_CORR_CNTLB_END_CNTL1[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_END_CNTL2", REG_MMIO, 0x46db, &mmGAMMA_CORR_CNTLB_END_CNTL2[0], sizeof(mmGAMMA_CORR_CNTLB_END_CNTL2)/sizeof(mmGAMMA_CORR_CNTLB_END_CNTL2[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_0_1", REG_MMIO, 0x46dc, &mmGAMMA_CORR_CNTLB_REGION_0_1[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_0_1)/sizeof(mmGAMMA_CORR_CNTLB_REGION_0_1[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_2_3", REG_MMIO, 0x46dd, &mmGAMMA_CORR_CNTLB_REGION_2_3[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_2_3)/sizeof(mmGAMMA_CORR_CNTLB_REGION_2_3[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_4_5", REG_MMIO, 0x46de, &mmGAMMA_CORR_CNTLB_REGION_4_5[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_4_5)/sizeof(mmGAMMA_CORR_CNTLB_REGION_4_5[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_6_7", REG_MMIO, 0x46df, &mmGAMMA_CORR_CNTLB_REGION_6_7[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_6_7)/sizeof(mmGAMMA_CORR_CNTLB_REGION_6_7[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_8_9", REG_MMIO, 0x46e0, &mmGAMMA_CORR_CNTLB_REGION_8_9[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_8_9)/sizeof(mmGAMMA_CORR_CNTLB_REGION_8_9[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_10_11", REG_MMIO, 0x46e1, &mmGAMMA_CORR_CNTLB_REGION_10_11[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_10_11)/sizeof(mmGAMMA_CORR_CNTLB_REGION_10_11[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_12_13", REG_MMIO, 0x46e2, &mmGAMMA_CORR_CNTLB_REGION_12_13[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_12_13)/sizeof(mmGAMMA_CORR_CNTLB_REGION_12_13[0]), 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_14_15", REG_MMIO, 0x46e3, &mmGAMMA_CORR_CNTLB_REGION_14_15[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_14_15)/sizeof(mmGAMMA_CORR_CNTLB_REGION_14_15[0]), 0, 0 },
+	{ "mmPACK_FIFO_ERROR", REG_MMIO, 0x46e4, &mmPACK_FIFO_ERROR[0], sizeof(mmPACK_FIFO_ERROR)/sizeof(mmPACK_FIFO_ERROR[0]), 0, 0 },
+	{ "mmOUTPUT_FIFO_ERROR", REG_MMIO, 0x46e5, &mmOUTPUT_FIFO_ERROR[0], sizeof(mmOUTPUT_FIFO_ERROR)/sizeof(mmOUTPUT_FIFO_ERROR[0]), 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_AUTOFILL", REG_MMIO, 0x46e6, &mmINPUT_GAMMA_LUT_AUTOFILL[0], sizeof(mmINPUT_GAMMA_LUT_AUTOFILL)/sizeof(mmINPUT_GAMMA_LUT_AUTOFILL[0]), 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_RW_INDEX", REG_MMIO, 0x46e7, &mmINPUT_GAMMA_LUT_RW_INDEX[0], sizeof(mmINPUT_GAMMA_LUT_RW_INDEX)/sizeof(mmINPUT_GAMMA_LUT_RW_INDEX[0]), 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_SEQ_COLOR", REG_MMIO, 0x46e8, &mmINPUT_GAMMA_LUT_SEQ_COLOR[0], sizeof(mmINPUT_GAMMA_LUT_SEQ_COLOR)/sizeof(mmINPUT_GAMMA_LUT_SEQ_COLOR[0]), 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_PWL_DATA", REG_MMIO, 0x46e9, &mmINPUT_GAMMA_LUT_PWL_DATA[0], sizeof(mmINPUT_GAMMA_LUT_PWL_DATA)/sizeof(mmINPUT_GAMMA_LUT_PWL_DATA[0]), 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_30_COLOR", REG_MMIO, 0x46ea, &mmINPUT_GAMMA_LUT_30_COLOR[0], sizeof(mmINPUT_GAMMA_LUT_30_COLOR)/sizeof(mmINPUT_GAMMA_LUT_30_COLOR[0]), 0, 0 },
+	{ "mmCOL_MAN_INPUT_GAMMA_CONTROL1", REG_MMIO, 0x46eb, &mmCOL_MAN_INPUT_GAMMA_CONTROL1[0], sizeof(mmCOL_MAN_INPUT_GAMMA_CONTROL1)/sizeof(mmCOL_MAN_INPUT_GAMMA_CONTROL1[0]), 0, 0 },
+	{ "mmCOL_MAN_INPUT_GAMMA_CONTROL2", REG_MMIO, 0x46ec, &mmCOL_MAN_INPUT_GAMMA_CONTROL2[0], sizeof(mmCOL_MAN_INPUT_GAMMA_CONTROL2)/sizeof(mmCOL_MAN_INPUT_GAMMA_CONTROL2[0]), 0, 0 },
+	{ "mmINPUT_GAMMA_BW_OFFSETS_B", REG_MMIO, 0x46ed, &mmINPUT_GAMMA_BW_OFFSETS_B[0], sizeof(mmINPUT_GAMMA_BW_OFFSETS_B)/sizeof(mmINPUT_GAMMA_BW_OFFSETS_B[0]), 0, 0 },
+	{ "mmINPUT_GAMMA_BW_OFFSETS_G", REG_MMIO, 0x46ee, &mmINPUT_GAMMA_BW_OFFSETS_G[0], sizeof(mmINPUT_GAMMA_BW_OFFSETS_G)/sizeof(mmINPUT_GAMMA_BW_OFFSETS_G[0]), 0, 0 },
+	{ "mmINPUT_GAMMA_BW_OFFSETS_R", REG_MMIO, 0x46ef, &mmINPUT_GAMMA_BW_OFFSETS_R[0], sizeof(mmINPUT_GAMMA_BW_OFFSETS_R)/sizeof(mmINPUT_GAMMA_BW_OFFSETS_R[0]), 0, 0 },
+	{ "mmCOL_MAN_DEBUG_CONTROL", REG_MMIO, 0x46f0, &mmCOL_MAN_DEBUG_CONTROL[0], sizeof(mmCOL_MAN_DEBUG_CONTROL)/sizeof(mmCOL_MAN_DEBUG_CONTROL[0]), 0, 0 },
+	{ "mmCOL_MAN_TEST_DEBUG_INDEX", REG_MMIO, 0x46f1, &mmCOL_MAN_TEST_DEBUG_INDEX[0], sizeof(mmCOL_MAN_TEST_DEBUG_INDEX)/sizeof(mmCOL_MAN_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCOL_MAN_TEST_DEBUG_DATA", REG_MMIO, 0x46f3, &mmCOL_MAN_TEST_DEBUG_DATA[0], sizeof(mmCOL_MAN_TEST_DEBUG_DATA)/sizeof(mmCOL_MAN_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCFEV_CLOCK_CONTROL", REG_MMIO, 0x46f4, &mmDCFEV_CLOCK_CONTROL[0], sizeof(mmDCFEV_CLOCK_CONTROL)/sizeof(mmDCFEV_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFEV_SOFT_RESET", REG_MMIO, 0x46f5, &mmDCFEV_SOFT_RESET[0], sizeof(mmDCFEV_SOFT_RESET)/sizeof(mmDCFEV_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFEV_DMIFV_CLOCK_CONTROL", REG_MMIO, 0x46f6, &mmDCFEV_DMIFV_CLOCK_CONTROL[0], sizeof(mmDCFEV_DMIFV_CLOCK_CONTROL)/sizeof(mmDCFEV_DMIFV_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFEV_DBG_CONFIG", REG_MMIO, 0x46f7, &mmDCFEV_DBG_CONFIG[0], sizeof(mmDCFEV_DBG_CONFIG)/sizeof(mmDCFEV_DBG_CONFIG[0]), 0, 0 },
+	{ "mmDCFEV_DMIFV_MEM_PWR_CTRL", REG_MMIO, 0x46f8, &mmDCFEV_DMIFV_MEM_PWR_CTRL[0], sizeof(mmDCFEV_DMIFV_MEM_PWR_CTRL)/sizeof(mmDCFEV_DMIFV_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCFEV_DMIFV_MEM_PWR_STATUS", REG_MMIO, 0x46f9, &mmDCFEV_DMIFV_MEM_PWR_STATUS[0], sizeof(mmDCFEV_DMIFV_MEM_PWR_STATUS)/sizeof(mmDCFEV_DMIFV_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCFEV_MEM_PWR_CTRL", REG_MMIO, 0x46fa, &mmDCFEV_MEM_PWR_CTRL[0], sizeof(mmDCFEV_MEM_PWR_CTRL)/sizeof(mmDCFEV_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCFEV_MEM_PWR_CTRL2", REG_MMIO, 0x46fb, &mmDCFEV_MEM_PWR_CTRL2[0], sizeof(mmDCFEV_MEM_PWR_CTRL2)/sizeof(mmDCFEV_MEM_PWR_CTRL2[0]), 0, 0 },
+	{ "mmDCFEV_MEM_PWR_STATUS", REG_MMIO, 0x46fc, &mmDCFEV_MEM_PWR_STATUS[0], sizeof(mmDCFEV_MEM_PWR_STATUS)/sizeof(mmDCFEV_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCFEV_DMIFV_DEBUG", REG_MMIO, 0x46fd, &mmDCFEV_DMIFV_DEBUG[0], sizeof(mmDCFEV_DMIFV_DEBUG)/sizeof(mmDCFEV_DMIFV_DEBUG[0]), 0, 0 },
+	{ "mmDCFEV_MISC", REG_MMIO, 0x46fe, &mmDCFEV_MISC[0], sizeof(mmDCFEV_MISC)/sizeof(mmDCFEV_MISC[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, &mmXDMA_SLV_CHANNEL_CNTL[0], sizeof(mmXDMA_SLV_CHANNEL_CNTL)/sizeof(mmXDMA_SLV_CHANNEL_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, &mmXDMA_SLV_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, &mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDC_PERFMON9_PERFCOUNTER_CNTL", REG_MMIO, 0x4724, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFCOUNTER_STATE", REG_MMIO, 0x4725, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4726, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CNTL", REG_MMIO, 0x4727, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CVALUE_LOW", REG_MMIO, 0x4728, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_HI", REG_MMIO, 0x4729, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_LOW", REG_MMIO, 0x472a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x472b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x472c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CNTL2", REG_MMIO, 0x472e, NULL, 0, 0, 0 },
+	{ "mmDPGV0_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4730, &mmDPGV0_PIPE_ARBITRATION_CONTROL1[0], sizeof(mmDPGV0_PIPE_ARBITRATION_CONTROL1)/sizeof(mmDPGV0_PIPE_ARBITRATION_CONTROL1[0]), 0, 0 },
+	{ "mmDPGV0_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4731, &mmDPGV0_PIPE_ARBITRATION_CONTROL2[0], sizeof(mmDPGV0_PIPE_ARBITRATION_CONTROL2)/sizeof(mmDPGV0_PIPE_ARBITRATION_CONTROL2[0]), 0, 0 },
+	{ "mmDPGV0_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4732, &mmDPGV0_WATERMARK_MASK_CONTROL[0], sizeof(mmDPGV0_WATERMARK_MASK_CONTROL)/sizeof(mmDPGV0_WATERMARK_MASK_CONTROL[0]), 0, 0 },
+	{ "mmDPGV0_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4733, &mmDPGV0_PIPE_URGENCY_CONTROL[0], sizeof(mmDPGV0_PIPE_URGENCY_CONTROL)/sizeof(mmDPGV0_PIPE_URGENCY_CONTROL[0]), 0, 0 },
+	{ "mmDPGV0_PIPE_DPM_CONTROL", REG_MMIO, 0x4734, &mmDPGV0_PIPE_DPM_CONTROL[0], sizeof(mmDPGV0_PIPE_DPM_CONTROL)/sizeof(mmDPGV0_PIPE_DPM_CONTROL[0]), 0, 0 },
+	{ "mmDPGV0_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4735, &mmDPGV0_PIPE_STUTTER_CONTROL[0], sizeof(mmDPGV0_PIPE_STUTTER_CONTROL)/sizeof(mmDPGV0_PIPE_STUTTER_CONTROL[0]), 0, 0 },
+	{ "mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4736, &mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL[0], sizeof(mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL)/sizeof(mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL[0]), 0, 0 },
+	{ "mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4737, &mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH[0], sizeof(mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH)/sizeof(mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH[0]), 0, 0 },
+	{ "mmDPGV0_REPEATER_PROGRAM", REG_MMIO, 0x4738, &mmDPGV0_REPEATER_PROGRAM[0], sizeof(mmDPGV0_REPEATER_PROGRAM)/sizeof(mmDPGV0_REPEATER_PROGRAM[0]), 0, 0 },
+	{ "mmDPGV0_HW_DEBUG_A", REG_MMIO, 0x4739, &mmDPGV0_HW_DEBUG_A[0], sizeof(mmDPGV0_HW_DEBUG_A)/sizeof(mmDPGV0_HW_DEBUG_A[0]), 0, 0 },
+	{ "mmDPGV0_HW_DEBUG_B", REG_MMIO, 0x473a, &mmDPGV0_HW_DEBUG_B[0], sizeof(mmDPGV0_HW_DEBUG_B)/sizeof(mmDPGV0_HW_DEBUG_B[0]), 0, 0 },
+	{ "mmDPGV0_HW_DEBUG_11", REG_MMIO, 0x473b, &mmDPGV0_HW_DEBUG_11[0], sizeof(mmDPGV0_HW_DEBUG_11)/sizeof(mmDPGV0_HW_DEBUG_11[0]), 0, 0 },
+	{ "mmDPGV0_CHK_PRE_PROC_CNTL", REG_MMIO, 0x473c, &mmDPGV0_CHK_PRE_PROC_CNTL[0], sizeof(mmDPGV0_CHK_PRE_PROC_CNTL)/sizeof(mmDPGV0_CHK_PRE_PROC_CNTL[0]), 0, 0 },
+	{ "mmDPGV1_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x473d, &mmDPGV1_PIPE_ARBITRATION_CONTROL1[0], sizeof(mmDPGV1_PIPE_ARBITRATION_CONTROL1)/sizeof(mmDPGV1_PIPE_ARBITRATION_CONTROL1[0]), 0, 0 },
+	{ "mmDPGV1_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x473e, &mmDPGV1_PIPE_ARBITRATION_CONTROL2[0], sizeof(mmDPGV1_PIPE_ARBITRATION_CONTROL2)/sizeof(mmDPGV1_PIPE_ARBITRATION_CONTROL2[0]), 0, 0 },
+	{ "mmDPGV1_WATERMARK_MASK_CONTROL", REG_MMIO, 0x473f, &mmDPGV1_WATERMARK_MASK_CONTROL[0], sizeof(mmDPGV1_WATERMARK_MASK_CONTROL)/sizeof(mmDPGV1_WATERMARK_MASK_CONTROL[0]), 0, 0 },
+	{ "mmDPGV1_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4740, &mmDPGV1_PIPE_URGENCY_CONTROL[0], sizeof(mmDPGV1_PIPE_URGENCY_CONTROL)/sizeof(mmDPGV1_PIPE_URGENCY_CONTROL[0]), 0, 0 },
+	{ "mmDPGV1_PIPE_DPM_CONTROL", REG_MMIO, 0x4741, &mmDPGV1_PIPE_DPM_CONTROL[0], sizeof(mmDPGV1_PIPE_DPM_CONTROL)/sizeof(mmDPGV1_PIPE_DPM_CONTROL[0]), 0, 0 },
+	{ "mmDPGV1_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4742, &mmDPGV1_PIPE_STUTTER_CONTROL[0], sizeof(mmDPGV1_PIPE_STUTTER_CONTROL)/sizeof(mmDPGV1_PIPE_STUTTER_CONTROL[0]), 0, 0 },
+	{ "mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4743, &mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL[0], sizeof(mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL)/sizeof(mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL[0]), 0, 0 },
+	{ "mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4744, &mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH[0], sizeof(mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH)/sizeof(mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH[0]), 0, 0 },
+	{ "mmDPGV1_REPEATER_PROGRAM", REG_MMIO, 0x4745, &mmDPGV1_REPEATER_PROGRAM[0], sizeof(mmDPGV1_REPEATER_PROGRAM)/sizeof(mmDPGV1_REPEATER_PROGRAM[0]), 0, 0 },
+	{ "mmDPGV1_HW_DEBUG_A", REG_MMIO, 0x4746, &mmDPGV1_HW_DEBUG_A[0], sizeof(mmDPGV1_HW_DEBUG_A)/sizeof(mmDPGV1_HW_DEBUG_A[0]), 0, 0 },
+	{ "mmDPGV1_HW_DEBUG_B", REG_MMIO, 0x4747, &mmDPGV1_HW_DEBUG_B[0], sizeof(mmDPGV1_HW_DEBUG_B)/sizeof(mmDPGV1_HW_DEBUG_B[0]), 0, 0 },
+	{ "mmDPGV1_HW_DEBUG_11", REG_MMIO, 0x4748, &mmDPGV1_HW_DEBUG_11[0], sizeof(mmDPGV1_HW_DEBUG_11)/sizeof(mmDPGV1_HW_DEBUG_11[0]), 0, 0 },
+	{ "mmDPGV1_CHK_PRE_PROC_CNTL", REG_MMIO, 0x4749, &mmDPGV1_CHK_PRE_PROC_CNTL[0], sizeof(mmDPGV1_CHK_PRE_PROC_CNTL)/sizeof(mmDPGV1_CHK_PRE_PROC_CNTL[0]), 0, 0 },
+	{ "mmDPGV_TEST_DEBUG_INDEX", REG_MMIO, 0x474e, &mmDPGV_TEST_DEBUG_INDEX[0], sizeof(mmDPGV_TEST_DEBUG_INDEX)/sizeof(mmDPGV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDPGV_TEST_DEBUG_DATA", REG_MMIO, 0x474f, &mmDPGV_TEST_DEBUG_DATA[0], sizeof(mmDPGV_TEST_DEBUG_DATA)/sizeof(mmDPGV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLNDV_CONTROL", REG_MMIO, 0x476d, &mmBLNDV_CONTROL[0], sizeof(mmBLNDV_CONTROL)/sizeof(mmBLNDV_CONTROL[0]), 0, 0 },
+	{ "mmBLNDV_SM_CONTROL2", REG_MMIO, 0x476e, &mmBLNDV_SM_CONTROL2[0], sizeof(mmBLNDV_SM_CONTROL2)/sizeof(mmBLNDV_SM_CONTROL2[0]), 0, 0 },
+	{ "mmBLNDV_CONTROL2", REG_MMIO, 0x476f, &mmBLNDV_CONTROL2[0], sizeof(mmBLNDV_CONTROL2)/sizeof(mmBLNDV_CONTROL2[0]), 0, 0 },
+	{ "mmBLNDV_UPDATE", REG_MMIO, 0x4770, &mmBLNDV_UPDATE[0], sizeof(mmBLNDV_UPDATE)/sizeof(mmBLNDV_UPDATE[0]), 0, 0 },
+	{ "mmBLNDV_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4771, &mmBLNDV_UNDERFLOW_INTERRUPT[0], sizeof(mmBLNDV_UNDERFLOW_INTERRUPT)/sizeof(mmBLNDV_UNDERFLOW_INTERRUPT[0]), 0, 0 },
+	{ "mmBLNDV_V_UPDATE_LOCK", REG_MMIO, 0x4773, &mmBLNDV_V_UPDATE_LOCK[0], sizeof(mmBLNDV_V_UPDATE_LOCK)/sizeof(mmBLNDV_V_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmBLNDV_DEBUG", REG_MMIO, 0x4774, &mmBLNDV_DEBUG[0], sizeof(mmBLNDV_DEBUG)/sizeof(mmBLNDV_DEBUG[0]), 0, 0 },
+	{ "mmBLNDV_TEST_DEBUG_INDEX", REG_MMIO, 0x4775, &mmBLNDV_TEST_DEBUG_INDEX[0], sizeof(mmBLNDV_TEST_DEBUG_INDEX)/sizeof(mmBLNDV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmBLNDV_TEST_DEBUG_DATA", REG_MMIO, 0x4776, &mmBLNDV_TEST_DEBUG_DATA[0], sizeof(mmBLNDV_TEST_DEBUG_DATA)/sizeof(mmBLNDV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLNDV_REG_UPDATE_STATUS", REG_MMIO, 0x4777, &mmBLNDV_REG_UPDATE_STATUS[0], sizeof(mmBLNDV_REG_UPDATE_STATUS)/sizeof(mmBLNDV_REG_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmCRTCV_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4778, &mmCRTCV_3D_STRUCTURE_CONTROL[0], sizeof(mmCRTCV_3D_STRUCTURE_CONTROL)/sizeof(mmCRTCV_3D_STRUCTURE_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_GSL_VSYNC_GAP", REG_MMIO, 0x4779, &mmCRTCV_GSL_VSYNC_GAP[0], sizeof(mmCRTCV_GSL_VSYNC_GAP)/sizeof(mmCRTCV_GSL_VSYNC_GAP[0]), 0, 0 },
+	{ "mmCRTCV_GSL_WINDOW", REG_MMIO, 0x477a, &mmCRTCV_GSL_WINDOW[0], sizeof(mmCRTCV_GSL_WINDOW)/sizeof(mmCRTCV_GSL_WINDOW[0]), 0, 0 },
+	{ "mmCRTCV_GSL_CONTROL", REG_MMIO, 0x477b, &mmCRTCV_GSL_CONTROL[0], sizeof(mmCRTCV_GSL_CONTROL)/sizeof(mmCRTCV_GSL_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_H_BLANK_EARLY_NUM", REG_MMIO, 0x477d, &mmCRTCV_H_BLANK_EARLY_NUM[0], sizeof(mmCRTCV_H_BLANK_EARLY_NUM)/sizeof(mmCRTCV_H_BLANK_EARLY_NUM[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x478, NULL, 0, 0, 0 },
+	{ "mmCRTCV_H_TOTAL", REG_MMIO, 0x4780, &mmCRTCV_H_TOTAL[0], sizeof(mmCRTCV_H_TOTAL)/sizeof(mmCRTCV_H_TOTAL[0]), 0, 0 },
+	{ "mmCRTCV_H_BLANK_START_END", REG_MMIO, 0x4781, &mmCRTCV_H_BLANK_START_END[0], sizeof(mmCRTCV_H_BLANK_START_END)/sizeof(mmCRTCV_H_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTCV_H_SYNC_A", REG_MMIO, 0x4782, &mmCRTCV_H_SYNC_A[0], sizeof(mmCRTCV_H_SYNC_A)/sizeof(mmCRTCV_H_SYNC_A[0]), 0, 0 },
+	{ "mmCRTCV_H_SYNC_A_CNTL", REG_MMIO, 0x4783, &mmCRTCV_H_SYNC_A_CNTL[0], sizeof(mmCRTCV_H_SYNC_A_CNTL)/sizeof(mmCRTCV_H_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTCV_H_SYNC_B", REG_MMIO, 0x4784, &mmCRTCV_H_SYNC_B[0], sizeof(mmCRTCV_H_SYNC_B)/sizeof(mmCRTCV_H_SYNC_B[0]), 0, 0 },
+	{ "mmCRTCV_H_SYNC_B_CNTL", REG_MMIO, 0x4785, &mmCRTCV_H_SYNC_B_CNTL[0], sizeof(mmCRTCV_H_SYNC_B_CNTL)/sizeof(mmCRTCV_H_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTCV_VBI_END", REG_MMIO, 0x4786, &mmCRTCV_VBI_END[0], sizeof(mmCRTCV_VBI_END)/sizeof(mmCRTCV_VBI_END[0]), 0, 0 },
+	{ "mmCRTCV_V_TOTAL", REG_MMIO, 0x4787, &mmCRTCV_V_TOTAL[0], sizeof(mmCRTCV_V_TOTAL)/sizeof(mmCRTCV_V_TOTAL[0]), 0, 0 },
+	{ "mmCRTCV_V_TOTAL_MIN", REG_MMIO, 0x4788, &mmCRTCV_V_TOTAL_MIN[0], sizeof(mmCRTCV_V_TOTAL_MIN)/sizeof(mmCRTCV_V_TOTAL_MIN[0]), 0, 0 },
+	{ "mmCRTCV_V_TOTAL_MAX", REG_MMIO, 0x4789, &mmCRTCV_V_TOTAL_MAX[0], sizeof(mmCRTCV_V_TOTAL_MAX)/sizeof(mmCRTCV_V_TOTAL_MAX[0]), 0, 0 },
+	{ "mmCRTCV_V_TOTAL_CONTROL", REG_MMIO, 0x478a, &mmCRTCV_V_TOTAL_CONTROL[0], sizeof(mmCRTCV_V_TOTAL_CONTROL)/sizeof(mmCRTCV_V_TOTAL_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_V_TOTAL_INT_STATUS", REG_MMIO, 0x478b, &mmCRTCV_V_TOTAL_INT_STATUS[0], sizeof(mmCRTCV_V_TOTAL_INT_STATUS)/sizeof(mmCRTCV_V_TOTAL_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTCV_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x478c, &mmCRTCV_VSYNC_NOM_INT_STATUS[0], sizeof(mmCRTCV_VSYNC_NOM_INT_STATUS)/sizeof(mmCRTCV_VSYNC_NOM_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTCV_V_BLANK_START_END", REG_MMIO, 0x478d, &mmCRTCV_V_BLANK_START_END[0], sizeof(mmCRTCV_V_BLANK_START_END)/sizeof(mmCRTCV_V_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTCV_V_SYNC_A", REG_MMIO, 0x478e, &mmCRTCV_V_SYNC_A[0], sizeof(mmCRTCV_V_SYNC_A)/sizeof(mmCRTCV_V_SYNC_A[0]), 0, 0 },
+	{ "mmCRTCV_V_SYNC_A_CNTL", REG_MMIO, 0x478f, &mmCRTCV_V_SYNC_A_CNTL[0], sizeof(mmCRTCV_V_SYNC_A_CNTL)/sizeof(mmCRTCV_V_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x479, NULL, 0, 0, 0 },
+	{ "mmCRTCV_V_SYNC_B", REG_MMIO, 0x4790, &mmCRTCV_V_SYNC_B[0], sizeof(mmCRTCV_V_SYNC_B)/sizeof(mmCRTCV_V_SYNC_B[0]), 0, 0 },
+	{ "mmCRTCV_V_SYNC_B_CNTL", REG_MMIO, 0x4791, &mmCRTCV_V_SYNC_B_CNTL[0], sizeof(mmCRTCV_V_SYNC_B_CNTL)/sizeof(mmCRTCV_V_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTCV_DTMTEST_CNTL", REG_MMIO, 0x4792, &mmCRTCV_DTMTEST_CNTL[0], sizeof(mmCRTCV_DTMTEST_CNTL)/sizeof(mmCRTCV_DTMTEST_CNTL[0]), 0, 0 },
+	{ "mmCRTCV_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4793, &mmCRTCV_DTMTEST_STATUS_POSITION[0], sizeof(mmCRTCV_DTMTEST_STATUS_POSITION)/sizeof(mmCRTCV_DTMTEST_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTCV_TRIGA_CNTL", REG_MMIO, 0x4794, &mmCRTCV_TRIGA_CNTL[0], sizeof(mmCRTCV_TRIGA_CNTL)/sizeof(mmCRTCV_TRIGA_CNTL[0]), 0, 0 },
+	{ "mmCRTCV_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4795, &mmCRTCV_TRIGA_MANUAL_TRIG[0], sizeof(mmCRTCV_TRIGA_MANUAL_TRIG)/sizeof(mmCRTCV_TRIGA_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTCV_TRIGB_CNTL", REG_MMIO, 0x4796, &mmCRTCV_TRIGB_CNTL[0], sizeof(mmCRTCV_TRIGB_CNTL)/sizeof(mmCRTCV_TRIGB_CNTL[0]), 0, 0 },
+	{ "mmCRTCV_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4797, &mmCRTCV_TRIGB_MANUAL_TRIG[0], sizeof(mmCRTCV_TRIGB_MANUAL_TRIG)/sizeof(mmCRTCV_TRIGB_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTCV_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4798, &mmCRTCV_FORCE_COUNT_NOW_CNTL[0], sizeof(mmCRTCV_FORCE_COUNT_NOW_CNTL)/sizeof(mmCRTCV_FORCE_COUNT_NOW_CNTL[0]), 0, 0 },
+	{ "mmCRTCV_FLOW_CONTROL", REG_MMIO, 0x4799, &mmCRTCV_FLOW_CONTROL[0], sizeof(mmCRTCV_FLOW_CONTROL)/sizeof(mmCRTCV_FLOW_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x479a, &mmCRTCV_STEREO_FORCE_NEXT_EYE[0], sizeof(mmCRTCV_STEREO_FORCE_NEXT_EYE)/sizeof(mmCRTCV_STEREO_FORCE_NEXT_EYE[0]), 0, 0 },
+	{ "mmCRTCV_AVSYNC_COUNTER", REG_MMIO, 0x479b, &mmCRTCV_AVSYNC_COUNTER[0], sizeof(mmCRTCV_AVSYNC_COUNTER)/sizeof(mmCRTCV_AVSYNC_COUNTER[0]), 0, 0 },
+	{ "mmCRTCV_CONTROL", REG_MMIO, 0x479c, &mmCRTCV_CONTROL[0], sizeof(mmCRTCV_CONTROL)/sizeof(mmCRTCV_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_BLANK_CONTROL", REG_MMIO, 0x479d, &mmCRTCV_BLANK_CONTROL[0], sizeof(mmCRTCV_BLANK_CONTROL)/sizeof(mmCRTCV_BLANK_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_INTERLACE_CONTROL", REG_MMIO, 0x479e, &mmCRTCV_INTERLACE_CONTROL[0], sizeof(mmCRTCV_INTERLACE_CONTROL)/sizeof(mmCRTCV_INTERLACE_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_INTERLACE_STATUS", REG_MMIO, 0x479f, &mmCRTCV_INTERLACE_STATUS[0], sizeof(mmCRTCV_INTERLACE_STATUS)/sizeof(mmCRTCV_INTERLACE_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x47a, NULL, 0, 0, 0 },
+	{ "mmCRTCV_FIELD_INDICATION_CONTROL", REG_MMIO, 0x47a0, &mmCRTCV_FIELD_INDICATION_CONTROL[0], sizeof(mmCRTCV_FIELD_INDICATION_CONTROL)/sizeof(mmCRTCV_FIELD_INDICATION_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_PIXEL_DATA_READBACK0", REG_MMIO, 0x47a1, &mmCRTCV_PIXEL_DATA_READBACK0[0], sizeof(mmCRTCV_PIXEL_DATA_READBACK0)/sizeof(mmCRTCV_PIXEL_DATA_READBACK0[0]), 0, 0 },
+	{ "mmCRTCV_PIXEL_DATA_READBACK1", REG_MMIO, 0x47a2, &mmCRTCV_PIXEL_DATA_READBACK1[0], sizeof(mmCRTCV_PIXEL_DATA_READBACK1)/sizeof(mmCRTCV_PIXEL_DATA_READBACK1[0]), 0, 0 },
+	{ "mmCRTCV_STATUS", REG_MMIO, 0x47a3, &mmCRTCV_STATUS[0], sizeof(mmCRTCV_STATUS)/sizeof(mmCRTCV_STATUS[0]), 0, 0 },
+	{ "mmCRTCV_STATUS_POSITION", REG_MMIO, 0x47a4, &mmCRTCV_STATUS_POSITION[0], sizeof(mmCRTCV_STATUS_POSITION)/sizeof(mmCRTCV_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTCV_NOM_VERT_POSITION", REG_MMIO, 0x47a5, &mmCRTCV_NOM_VERT_POSITION[0], sizeof(mmCRTCV_NOM_VERT_POSITION)/sizeof(mmCRTCV_NOM_VERT_POSITION[0]), 0, 0 },
+	{ "mmCRTCV_STATUS_FRAME_COUNT", REG_MMIO, 0x47a6, &mmCRTCV_STATUS_FRAME_COUNT[0], sizeof(mmCRTCV_STATUS_FRAME_COUNT)/sizeof(mmCRTCV_STATUS_FRAME_COUNT[0]), 0, 0 },
+	{ "mmCRTCV_STATUS_VF_COUNT", REG_MMIO, 0x47a7, &mmCRTCV_STATUS_VF_COUNT[0], sizeof(mmCRTCV_STATUS_VF_COUNT)/sizeof(mmCRTCV_STATUS_VF_COUNT[0]), 0, 0 },
+	{ "mmCRTCV_STATUS_HV_COUNT", REG_MMIO, 0x47a8, &mmCRTCV_STATUS_HV_COUNT[0], sizeof(mmCRTCV_STATUS_HV_COUNT)/sizeof(mmCRTCV_STATUS_HV_COUNT[0]), 0, 0 },
+	{ "mmCRTCV_COUNT_CONTROL", REG_MMIO, 0x47a9, &mmCRTCV_COUNT_CONTROL[0], sizeof(mmCRTCV_COUNT_CONTROL)/sizeof(mmCRTCV_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_COUNT_RESET", REG_MMIO, 0x47aa, &mmCRTCV_COUNT_RESET[0], sizeof(mmCRTCV_COUNT_RESET)/sizeof(mmCRTCV_COUNT_RESET[0]), 0, 0 },
+	{ "mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x47ab, &mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmCRTCV_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 },
+	{ "mmCRTCV_VERT_SYNC_CONTROL", REG_MMIO, 0x47ac, &mmCRTCV_VERT_SYNC_CONTROL[0], sizeof(mmCRTCV_VERT_SYNC_CONTROL)/sizeof(mmCRTCV_VERT_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_STEREO_STATUS", REG_MMIO, 0x47ad, &mmCRTCV_STEREO_STATUS[0], sizeof(mmCRTCV_STEREO_STATUS)/sizeof(mmCRTCV_STEREO_STATUS[0]), 0, 0 },
+	{ "mmCRTCV_STEREO_CONTROL", REG_MMIO, 0x47ae, &mmCRTCV_STEREO_CONTROL[0], sizeof(mmCRTCV_STEREO_CONTROL)/sizeof(mmCRTCV_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_SNAPSHOT_STATUS", REG_MMIO, 0x47af, &mmCRTCV_SNAPSHOT_STATUS[0], sizeof(mmCRTCV_SNAPSHOT_STATUS)/sizeof(mmCRTCV_SNAPSHOT_STATUS[0]), 0, 0 },
+	{ "mmCRTCV_SNAPSHOT_CONTROL", REG_MMIO, 0x47b0, &mmCRTCV_SNAPSHOT_CONTROL[0], sizeof(mmCRTCV_SNAPSHOT_CONTROL)/sizeof(mmCRTCV_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_SNAPSHOT_POSITION", REG_MMIO, 0x47b1, &mmCRTCV_SNAPSHOT_POSITION[0], sizeof(mmCRTCV_SNAPSHOT_POSITION)/sizeof(mmCRTCV_SNAPSHOT_POSITION[0]), 0, 0 },
+	{ "mmCRTCV_SNAPSHOT_FRAME", REG_MMIO, 0x47b2, &mmCRTCV_SNAPSHOT_FRAME[0], sizeof(mmCRTCV_SNAPSHOT_FRAME)/sizeof(mmCRTCV_SNAPSHOT_FRAME[0]), 0, 0 },
+	{ "mmCRTCV_START_LINE_CONTROL", REG_MMIO, 0x47b3, &mmCRTCV_START_LINE_CONTROL[0], sizeof(mmCRTCV_START_LINE_CONTROL)/sizeof(mmCRTCV_START_LINE_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_INTERRUPT_CONTROL", REG_MMIO, 0x47b4, &mmCRTCV_INTERRUPT_CONTROL[0], sizeof(mmCRTCV_INTERRUPT_CONTROL)/sizeof(mmCRTCV_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_UPDATE_LOCK", REG_MMIO, 0x47b5, &mmCRTCV_UPDATE_LOCK[0], sizeof(mmCRTCV_UPDATE_LOCK)/sizeof(mmCRTCV_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTCV_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x47b6, &mmCRTCV_DOUBLE_BUFFER_CONTROL[0], sizeof(mmCRTCV_DOUBLE_BUFFER_CONTROL)/sizeof(mmCRTCV_DOUBLE_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x47b7, &mmCRTCV_VGA_PARAMETER_CAPTURE_MODE[0], sizeof(mmCRTCV_VGA_PARAMETER_CAPTURE_MODE)/sizeof(mmCRTCV_VGA_PARAMETER_CAPTURE_MODE[0]), 0, 0 },
+	{ "mmCRTCV_TEST_PATTERN_CONTROL", REG_MMIO, 0x47ba, &mmCRTCV_TEST_PATTERN_CONTROL[0], sizeof(mmCRTCV_TEST_PATTERN_CONTROL)/sizeof(mmCRTCV_TEST_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x47bb, &mmCRTCV_TEST_PATTERN_PARAMETERS[0], sizeof(mmCRTCV_TEST_PATTERN_PARAMETERS)/sizeof(mmCRTCV_TEST_PATTERN_PARAMETERS[0]), 0, 0 },
+	{ "mmCRTCV_TEST_PATTERN_COLOR", REG_MMIO, 0x47bc, &mmCRTCV_TEST_PATTERN_COLOR[0], sizeof(mmCRTCV_TEST_PATTERN_COLOR)/sizeof(mmCRTCV_TEST_PATTERN_COLOR[0]), 0, 0 },
+	{ "mmCRTCV_MASTER_UPDATE_LOCK", REG_MMIO, 0x47bd, &mmCRTCV_MASTER_UPDATE_LOCK[0], sizeof(mmCRTCV_MASTER_UPDATE_LOCK)/sizeof(mmCRTCV_MASTER_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTCV_MASTER_UPDATE_MODE", REG_MMIO, 0x47be, &mmCRTCV_MASTER_UPDATE_MODE[0], sizeof(mmCRTCV_MASTER_UPDATE_MODE)/sizeof(mmCRTCV_MASTER_UPDATE_MODE[0]), 0, 0 },
+	{ "mmCRTCV_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x47bf, &mmCRTCV_MVP_INBAND_CNTL_INSERT[0], sizeof(mmCRTCV_MVP_INBAND_CNTL_INSERT)/sizeof(mmCRTCV_MVP_INBAND_CNTL_INSERT[0]), 0, 0 },
+	{ "mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x47c0, &mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER[0], sizeof(mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER)/sizeof(mmCRTCV_MVP_INBAND_CNTL_INSERT_TIMER[0]), 0, 0 },
+	{ "mmCRTCV_MVP_STATUS", REG_MMIO, 0x47c1, &mmCRTCV_MVP_STATUS[0], sizeof(mmCRTCV_MVP_STATUS)/sizeof(mmCRTCV_MVP_STATUS[0]), 0, 0 },
+	{ "mmCRTCV_MASTER_EN", REG_MMIO, 0x47c2, &mmCRTCV_MASTER_EN[0], sizeof(mmCRTCV_MASTER_EN)/sizeof(mmCRTCV_MASTER_EN[0]), 0, 0 },
+	{ "mmCRTCV_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x47c3, &mmCRTCV_ALLOW_STOP_OFF_V_CNT[0], sizeof(mmCRTCV_ALLOW_STOP_OFF_V_CNT)/sizeof(mmCRTCV_ALLOW_STOP_OFF_V_CNT[0]), 0, 0 },
+	{ "mmCRTCV_V_UPDATE_INT_STATUS", REG_MMIO, 0x47c4, &mmCRTCV_V_UPDATE_INT_STATUS[0], sizeof(mmCRTCV_V_UPDATE_INT_STATUS)/sizeof(mmCRTCV_V_UPDATE_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTCV_TEST_DEBUG_INDEX", REG_MMIO, 0x47c6, &mmCRTCV_TEST_DEBUG_INDEX[0], sizeof(mmCRTCV_TEST_DEBUG_INDEX)/sizeof(mmCRTCV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCRTCV_TEST_DEBUG_DATA", REG_MMIO, 0x47c7, &mmCRTCV_TEST_DEBUG_DATA[0], sizeof(mmCRTCV_TEST_DEBUG_DATA)/sizeof(mmCRTCV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmCRTCV_OVERSCAN_COLOR", REG_MMIO, 0x47c8, &mmCRTCV_OVERSCAN_COLOR[0], sizeof(mmCRTCV_OVERSCAN_COLOR)/sizeof(mmCRTCV_OVERSCAN_COLOR[0]), 0, 0 },
+	{ "mmCRTCV_OVERSCAN_COLOR_EXT", REG_MMIO, 0x47c9, &mmCRTCV_OVERSCAN_COLOR_EXT[0], sizeof(mmCRTCV_OVERSCAN_COLOR_EXT)/sizeof(mmCRTCV_OVERSCAN_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTCV_BLANK_DATA_COLOR", REG_MMIO, 0x47ca, &mmCRTCV_BLANK_DATA_COLOR[0], sizeof(mmCRTCV_BLANK_DATA_COLOR)/sizeof(mmCRTCV_BLANK_DATA_COLOR[0]), 0, 0 },
+	{ "mmCRTCV_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x47cb, &mmCRTCV_BLANK_DATA_COLOR_EXT[0], sizeof(mmCRTCV_BLANK_DATA_COLOR_EXT)/sizeof(mmCRTCV_BLANK_DATA_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTCV_BLACK_COLOR", REG_MMIO, 0x47cc, &mmCRTCV_BLACK_COLOR[0], sizeof(mmCRTCV_BLACK_COLOR)/sizeof(mmCRTCV_BLACK_COLOR[0]), 0, 0 },
+	{ "mmCRTCV_BLACK_COLOR_EXT", REG_MMIO, 0x47cd, &mmCRTCV_BLACK_COLOR_EXT[0], sizeof(mmCRTCV_BLACK_COLOR_EXT)/sizeof(mmCRTCV_BLACK_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTCV_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x47ce, &mmCRTCV_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmCRTCV_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmCRTCV_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 },
+	{ "mmCRTCV_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x47cf, &mmCRTCV_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmCRTCV_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmCRTCV_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x47d0, &mmCRTCV_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmCRTCV_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmCRTCV_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 },
+	{ "mmCRTCV_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x47d1, &mmCRTCV_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmCRTCV_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmCRTCV_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x47d2, &mmCRTCV_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmCRTCV_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmCRTCV_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 },
+	{ "mmCRTCV_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x47d3, &mmCRTCV_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmCRTCV_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmCRTCV_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC_CNTL", REG_MMIO, 0x47d4, &mmCRTCV_CRC_CNTL[0], sizeof(mmCRTCV_CRC_CNTL)/sizeof(mmCRTCV_CRC_CNTL[0]), 0, 0 },
+	{ "mmCRTCV_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x47d5, &mmCRTCV_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmCRTCV_CRC0_WINDOWA_X_CONTROL)/sizeof(mmCRTCV_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x47d6, &mmCRTCV_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmCRTCV_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmCRTCV_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x47d7, &mmCRTCV_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmCRTCV_CRC0_WINDOWB_X_CONTROL)/sizeof(mmCRTCV_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x47d8, &mmCRTCV_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmCRTCV_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmCRTCV_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC0_DATA_RG", REG_MMIO, 0x47d9, &mmCRTCV_CRC0_DATA_RG[0], sizeof(mmCRTCV_CRC0_DATA_RG)/sizeof(mmCRTCV_CRC0_DATA_RG[0]), 0, 0 },
+	{ "mmCRTCV_CRC0_DATA_B", REG_MMIO, 0x47da, &mmCRTCV_CRC0_DATA_B[0], sizeof(mmCRTCV_CRC0_DATA_B)/sizeof(mmCRTCV_CRC0_DATA_B[0]), 0, 0 },
+	{ "mmCRTCV_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x47db, &mmCRTCV_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmCRTCV_CRC1_WINDOWA_X_CONTROL)/sizeof(mmCRTCV_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x47dc, &mmCRTCV_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmCRTCV_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmCRTCV_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x47dd, &mmCRTCV_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmCRTCV_CRC1_WINDOWB_X_CONTROL)/sizeof(mmCRTCV_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x47de, &mmCRTCV_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmCRTCV_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmCRTCV_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV_CRC1_DATA_RG", REG_MMIO, 0x47df, &mmCRTCV_CRC1_DATA_RG[0], sizeof(mmCRTCV_CRC1_DATA_RG)/sizeof(mmCRTCV_CRC1_DATA_RG[0]), 0, 0 },
+	{ "mmCRTCV_CRC1_DATA_B", REG_MMIO, 0x47e0, &mmCRTCV_CRC1_DATA_B[0], sizeof(mmCRTCV_CRC1_DATA_B)/sizeof(mmCRTCV_CRC1_DATA_B[0]), 0, 0 },
+	{ "mmCRTCV_STATIC_SCREEN_CONTROL", REG_MMIO, 0x47e7, &mmCRTCV_STATIC_SCREEN_CONTROL[0], sizeof(mmCRTCV_STATIC_SCREEN_CONTROL)/sizeof(mmCRTCV_STATIC_SCREEN_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x480, NULL, 0, 0, 0 },
+	{ "mmDC_GENERICA", REG_MMIO, 0x4800, &mmDC_GENERICA[0], sizeof(mmDC_GENERICA)/sizeof(mmDC_GENERICA[0]), 0, 0 },
+	{ "mmDC_GENERICB", REG_MMIO, 0x4801, &mmDC_GENERICB[0], sizeof(mmDC_GENERICB)/sizeof(mmDC_GENERICB[0]), 0, 0 },
+	{ "mmDC_PAD_EXTERN_SIG", REG_MMIO, 0x4802, &mmDC_PAD_EXTERN_SIG[0], sizeof(mmDC_PAD_EXTERN_SIG)/sizeof(mmDC_PAD_EXTERN_SIG[0]), 0, 0 },
+	{ "mmDC_REF_CLK_CNTL", REG_MMIO, 0x4803, &mmDC_REF_CLK_CNTL[0], sizeof(mmDC_REF_CLK_CNTL)/sizeof(mmDC_REF_CLK_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_DEBUG", REG_MMIO, 0x4804, &mmDC_GPIO_DEBUG[0], sizeof(mmDC_GPIO_DEBUG)/sizeof(mmDC_GPIO_DEBUG[0]), 0, 0 },
+	{ "mmUNIPHYA_LINK_CNTL", REG_MMIO, 0x4805, &mmUNIPHYA_LINK_CNTL[0], sizeof(mmUNIPHYA_LINK_CNTL)/sizeof(mmUNIPHYA_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYA_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4806, &mmUNIPHYA_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYA_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYA_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYB_LINK_CNTL", REG_MMIO, 0x4807, &mmUNIPHYB_LINK_CNTL[0], sizeof(mmUNIPHYB_LINK_CNTL)/sizeof(mmUNIPHYB_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYB_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4808, &mmUNIPHYB_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYB_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYB_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYC_LINK_CNTL", REG_MMIO, 0x4809, &mmUNIPHYC_LINK_CNTL[0], sizeof(mmUNIPHYC_LINK_CNTL)/sizeof(mmUNIPHYC_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYC_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480a, &mmUNIPHYC_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYC_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYC_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYD_LINK_CNTL", REG_MMIO, 0x480b, &mmUNIPHYD_LINK_CNTL[0], sizeof(mmUNIPHYD_LINK_CNTL)/sizeof(mmUNIPHYD_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYD_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480c, &mmUNIPHYD_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYD_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYD_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYE_LINK_CNTL", REG_MMIO, 0x480d, &mmUNIPHYE_LINK_CNTL[0], sizeof(mmUNIPHYE_LINK_CNTL)/sizeof(mmUNIPHYE_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYE_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480e, &mmUNIPHYE_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYE_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYE_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYF_LINK_CNTL", REG_MMIO, 0x480f, &mmUNIPHYF_LINK_CNTL[0], sizeof(mmUNIPHYF_LINK_CNTL)/sizeof(mmUNIPHYF_LINK_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x481, NULL, 0, 0, 0 },
+	{ "mmUNIPHYF_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4810, &mmUNIPHYF_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYF_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYF_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYG_LINK_CNTL", REG_MMIO, 0x4811, &mmUNIPHYG_LINK_CNTL[0], sizeof(mmUNIPHYG_LINK_CNTL)/sizeof(mmUNIPHYG_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYG_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4812, &mmUNIPHYG_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmDCIO_WRCMD_DELAY", REG_MMIO, 0x4816, &mmDCIO_WRCMD_DELAY[0], sizeof(mmDCIO_WRCMD_DELAY)/sizeof(mmDCIO_WRCMD_DELAY[0]), 0, 0 },
+	{ "mmDC_PINSTRAPS", REG_MMIO, 0x4818, &mmDC_PINSTRAPS[0], sizeof(mmDC_PINSTRAPS)/sizeof(mmDC_PINSTRAPS[0]), 0, 0 },
+	{ "mmDC_DVODATA_CONFIG", REG_MMIO, 0x481a, &mmDC_DVODATA_CONFIG[0], sizeof(mmDC_DVODATA_CONFIG)/sizeof(mmDC_DVODATA_CONFIG[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_CNTL", REG_MMIO, 0x481b, &mmLVTMA_PWRSEQ_CNTL[0], sizeof(mmLVTMA_PWRSEQ_CNTL)/sizeof(mmLVTMA_PWRSEQ_CNTL[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_STATE", REG_MMIO, 0x481c, &mmLVTMA_PWRSEQ_STATE[0], sizeof(mmLVTMA_PWRSEQ_STATE)/sizeof(mmLVTMA_PWRSEQ_STATE[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_REF_DIV", REG_MMIO, 0x481d, &mmLVTMA_PWRSEQ_REF_DIV[0], sizeof(mmLVTMA_PWRSEQ_REF_DIV)/sizeof(mmLVTMA_PWRSEQ_REF_DIV[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY1", REG_MMIO, 0x481e, &mmLVTMA_PWRSEQ_DELAY1[0], sizeof(mmLVTMA_PWRSEQ_DELAY1)/sizeof(mmLVTMA_PWRSEQ_DELAY1[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY2", REG_MMIO, 0x481f, &mmLVTMA_PWRSEQ_DELAY2[0], sizeof(mmLVTMA_PWRSEQ_DELAY2)/sizeof(mmLVTMA_PWRSEQ_DELAY2[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x482, NULL, 0, 0, 0 },
+	{ "mmBL_PWM_CNTL", REG_MMIO, 0x4820, &mmBL_PWM_CNTL[0], sizeof(mmBL_PWM_CNTL)/sizeof(mmBL_PWM_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_CNTL2", REG_MMIO, 0x4821, &mmBL_PWM_CNTL2[0], sizeof(mmBL_PWM_CNTL2)/sizeof(mmBL_PWM_CNTL2[0]), 0, 0 },
+	{ "mmBL_PWM_PERIOD_CNTL", REG_MMIO, 0x4822, &mmBL_PWM_PERIOD_CNTL[0], sizeof(mmBL_PWM_PERIOD_CNTL)/sizeof(mmBL_PWM_PERIOD_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_GRP1_REG_LOCK", REG_MMIO, 0x4823, &mmBL_PWM_GRP1_REG_LOCK[0], sizeof(mmBL_PWM_GRP1_REG_LOCK)/sizeof(mmBL_PWM_GRP1_REG_LOCK[0]), 0, 0 },
+	{ "mmDCIO_GSL_GENLK_PAD_CNTL", REG_MMIO, 0x4824, &mmDCIO_GSL_GENLK_PAD_CNTL[0], sizeof(mmDCIO_GSL_GENLK_PAD_CNTL)/sizeof(mmDCIO_GSL_GENLK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL_SWAPLOCK_PAD_CNTL", REG_MMIO, 0x4825, &mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0], sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL)/sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL0_CNTL", REG_MMIO, 0x4826, &mmDCIO_GSL0_CNTL[0], sizeof(mmDCIO_GSL0_CNTL)/sizeof(mmDCIO_GSL0_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL1_CNTL", REG_MMIO, 0x4827, &mmDCIO_GSL1_CNTL[0], sizeof(mmDCIO_GSL1_CNTL)/sizeof(mmDCIO_GSL1_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL2_CNTL", REG_MMIO, 0x4828, &mmDCIO_GSL2_CNTL[0], sizeof(mmDCIO_GSL2_CNTL)/sizeof(mmDCIO_GSL2_CNTL[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_V_UPDATE", REG_MMIO, 0x4829, &mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0], sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE)/sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_P_FLIP", REG_MMIO, 0x482a, &mmDC_GPU_TIMER_START_POSITION_P_FLIP[0], sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP)/sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ", REG_MMIO, 0x482b, &mmDC_GPU_TIMER_READ[0], sizeof(mmDC_GPU_TIMER_READ)/sizeof(mmDC_GPU_TIMER_READ[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ_CNTL", REG_MMIO, 0x482c, &mmDC_GPU_TIMER_READ_CNTL[0], sizeof(mmDC_GPU_TIMER_READ_CNTL)/sizeof(mmDC_GPU_TIMER_READ_CNTL[0]), 0, 0 },
+	{ "mmDCIO_CLOCK_CNTL", REG_MMIO, 0x482d, &mmDCIO_CLOCK_CNTL[0], sizeof(mmDCIO_CLOCK_CNTL)/sizeof(mmDCIO_CLOCK_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DEBUG", REG_MMIO, 0x482f, &mmDCIO_DEBUG[0], sizeof(mmDCIO_DEBUG)/sizeof(mmDCIO_DEBUG[0]), 0, 0 },
+	{ "mmDCO_DCFE_EXT_VSYNC_CNTL", REG_MMIO, 0x4830, &mmDCO_DCFE_EXT_VSYNC_CNTL[0], sizeof(mmDCO_DCFE_EXT_VSYNC_CNTL)/sizeof(mmDCO_DCFE_EXT_VSYNC_CNTL[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_INDEX", REG_MMIO, 0x4831, &mmDCIO_TEST_DEBUG_INDEX[0], sizeof(mmDCIO_TEST_DEBUG_INDEX)/sizeof(mmDCIO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_DATA", REG_MMIO, 0x4832, &mmDCIO_TEST_DEBUG_DATA[0], sizeof(mmDCIO_TEST_DEBUG_DATA)/sizeof(mmDCIO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDBG_OUT_CNTL", REG_MMIO, 0x4834, &mmDBG_OUT_CNTL[0], sizeof(mmDBG_OUT_CNTL)/sizeof(mmDBG_OUT_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DEBUG_CONFIG", REG_MMIO, 0x4835, &mmDCIO_DEBUG_CONFIG[0], sizeof(mmDCIO_DEBUG_CONFIG)/sizeof(mmDCIO_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmDCIO_SOFT_RESET", REG_MMIO, 0x4836, &mmDCIO_SOFT_RESET[0], sizeof(mmDCIO_SOFT_RESET)/sizeof(mmDCIO_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCIO_DPHY_SEL", REG_MMIO, 0x4837, &mmDCIO_DPHY_SEL[0], sizeof(mmDCIO_DPHY_SEL)/sizeof(mmDCIO_DPHY_SEL[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKA", REG_MMIO, 0x4838, &mmUNIPHY_IMPCAL_LINKA[0], sizeof(mmUNIPHY_IMPCAL_LINKA)/sizeof(mmUNIPHY_IMPCAL_LINKA[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKB", REG_MMIO, 0x4839, &mmUNIPHY_IMPCAL_LINKB[0], sizeof(mmUNIPHY_IMPCAL_LINKB)/sizeof(mmUNIPHY_IMPCAL_LINKB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PERIOD", REG_MMIO, 0x483a, &mmUNIPHY_IMPCAL_PERIOD[0], sizeof(mmUNIPHY_IMPCAL_PERIOD)/sizeof(mmUNIPHY_IMPCAL_PERIOD[0]), 0, 0 },
+	{ "mmAUXP_IMPCAL", REG_MMIO, 0x483b, &mmAUXP_IMPCAL[0], sizeof(mmAUXP_IMPCAL)/sizeof(mmAUXP_IMPCAL[0]), 0, 0 },
+	{ "mmAUXN_IMPCAL", REG_MMIO, 0x483c, &mmAUXN_IMPCAL[0], sizeof(mmAUXN_IMPCAL)/sizeof(mmAUXN_IMPCAL[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL", REG_MMIO, 0x483d, &mmDCIO_IMPCAL_CNTL[0], sizeof(mmDCIO_IMPCAL_CNTL)/sizeof(mmDCIO_IMPCAL_CNTL[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_AB", REG_MMIO, 0x483e, &mmUNIPHY_IMPCAL_PSW_AB[0], sizeof(mmUNIPHY_IMPCAL_PSW_AB)/sizeof(mmUNIPHY_IMPCAL_PSW_AB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKC", REG_MMIO, 0x483f, &mmUNIPHY_IMPCAL_LINKC[0], sizeof(mmUNIPHY_IMPCAL_LINKC)/sizeof(mmUNIPHY_IMPCAL_LINKC[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKD", REG_MMIO, 0x4840, &mmUNIPHY_IMPCAL_LINKD[0], sizeof(mmUNIPHY_IMPCAL_LINKD)/sizeof(mmUNIPHY_IMPCAL_LINKD[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_CD", REG_MMIO, 0x4841, &mmDCIO_IMPCAL_CNTL_CD[0], sizeof(mmDCIO_IMPCAL_CNTL_CD)/sizeof(mmDCIO_IMPCAL_CNTL_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_CD", REG_MMIO, 0x4842, &mmUNIPHY_IMPCAL_PSW_CD[0], sizeof(mmUNIPHY_IMPCAL_PSW_CD)/sizeof(mmUNIPHY_IMPCAL_PSW_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKE", REG_MMIO, 0x4843, &mmUNIPHY_IMPCAL_LINKE[0], sizeof(mmUNIPHY_IMPCAL_LINKE)/sizeof(mmUNIPHY_IMPCAL_LINKE[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKF", REG_MMIO, 0x4844, &mmUNIPHY_IMPCAL_LINKF[0], sizeof(mmUNIPHY_IMPCAL_LINKF)/sizeof(mmUNIPHY_IMPCAL_LINKF[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_EF", REG_MMIO, 0x4845, &mmDCIO_IMPCAL_CNTL_EF[0], sizeof(mmDCIO_IMPCAL_CNTL_EF)/sizeof(mmDCIO_IMPCAL_CNTL_EF[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_EF", REG_MMIO, 0x4846, &mmUNIPHY_IMPCAL_PSW_EF[0], sizeof(mmUNIPHY_IMPCAL_PSW_EF)/sizeof(mmUNIPHY_IMPCAL_PSW_EF[0]), 0, 0 },
+	{ "mmUNIPHYLPA_LINK_CNTL", REG_MMIO, 0x4847, &mmUNIPHYLPA_LINK_CNTL[0], sizeof(mmUNIPHYLPA_LINK_CNTL)/sizeof(mmUNIPHYLPA_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYLPB_LINK_CNTL", REG_MMIO, 0x4848, &mmUNIPHYLPB_LINK_CNTL[0], sizeof(mmUNIPHYLPB_LINK_CNTL)/sizeof(mmUNIPHYLPB_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYLPA_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4849, &mmUNIPHYLPA_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYLPA_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYLPA_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYLPB_CHANNEL_XBAR_CNTL", REG_MMIO, 0x484a, &mmUNIPHYLPB_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYLPB_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYLPB_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_MASK", REG_MMIO, 0x4860, &mmDC_GPIO_GENERIC_MASK[0], sizeof(mmDC_GPIO_GENERIC_MASK)/sizeof(mmDC_GPIO_GENERIC_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_A", REG_MMIO, 0x4861, &mmDC_GPIO_GENERIC_A[0], sizeof(mmDC_GPIO_GENERIC_A)/sizeof(mmDC_GPIO_GENERIC_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_EN", REG_MMIO, 0x4862, &mmDC_GPIO_GENERIC_EN[0], sizeof(mmDC_GPIO_GENERIC_EN)/sizeof(mmDC_GPIO_GENERIC_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_Y", REG_MMIO, 0x4863, &mmDC_GPIO_GENERIC_Y[0], sizeof(mmDC_GPIO_GENERIC_Y)/sizeof(mmDC_GPIO_GENERIC_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_MASK", REG_MMIO, 0x4864, &mmDC_GPIO_DVODATA_MASK[0], sizeof(mmDC_GPIO_DVODATA_MASK)/sizeof(mmDC_GPIO_DVODATA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_A", REG_MMIO, 0x4865, &mmDC_GPIO_DVODATA_A[0], sizeof(mmDC_GPIO_DVODATA_A)/sizeof(mmDC_GPIO_DVODATA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_EN", REG_MMIO, 0x4866, &mmDC_GPIO_DVODATA_EN[0], sizeof(mmDC_GPIO_DVODATA_EN)/sizeof(mmDC_GPIO_DVODATA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_Y", REG_MMIO, 0x4867, &mmDC_GPIO_DVODATA_Y[0], sizeof(mmDC_GPIO_DVODATA_Y)/sizeof(mmDC_GPIO_DVODATA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_MASK", REG_MMIO, 0x4868, &mmDC_GPIO_DDC1_MASK[0], sizeof(mmDC_GPIO_DDC1_MASK)/sizeof(mmDC_GPIO_DDC1_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_A", REG_MMIO, 0x4869, &mmDC_GPIO_DDC1_A[0], sizeof(mmDC_GPIO_DDC1_A)/sizeof(mmDC_GPIO_DDC1_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_EN", REG_MMIO, 0x486a, &mmDC_GPIO_DDC1_EN[0], sizeof(mmDC_GPIO_DDC1_EN)/sizeof(mmDC_GPIO_DDC1_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_Y", REG_MMIO, 0x486b, &mmDC_GPIO_DDC1_Y[0], sizeof(mmDC_GPIO_DDC1_Y)/sizeof(mmDC_GPIO_DDC1_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_MASK", REG_MMIO, 0x486c, &mmDC_GPIO_DDC2_MASK[0], sizeof(mmDC_GPIO_DDC2_MASK)/sizeof(mmDC_GPIO_DDC2_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_A", REG_MMIO, 0x486d, &mmDC_GPIO_DDC2_A[0], sizeof(mmDC_GPIO_DDC2_A)/sizeof(mmDC_GPIO_DDC2_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_EN", REG_MMIO, 0x486e, &mmDC_GPIO_DDC2_EN[0], sizeof(mmDC_GPIO_DDC2_EN)/sizeof(mmDC_GPIO_DDC2_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_Y", REG_MMIO, 0x486f, &mmDC_GPIO_DDC2_Y[0], sizeof(mmDC_GPIO_DDC2_Y)/sizeof(mmDC_GPIO_DDC2_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_MASK", REG_MMIO, 0x4870, &mmDC_GPIO_DDC3_MASK[0], sizeof(mmDC_GPIO_DDC3_MASK)/sizeof(mmDC_GPIO_DDC3_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_A", REG_MMIO, 0x4871, &mmDC_GPIO_DDC3_A[0], sizeof(mmDC_GPIO_DDC3_A)/sizeof(mmDC_GPIO_DDC3_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_EN", REG_MMIO, 0x4872, &mmDC_GPIO_DDC3_EN[0], sizeof(mmDC_GPIO_DDC3_EN)/sizeof(mmDC_GPIO_DDC3_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_Y", REG_MMIO, 0x4873, &mmDC_GPIO_DDC3_Y[0], sizeof(mmDC_GPIO_DDC3_Y)/sizeof(mmDC_GPIO_DDC3_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_MASK", REG_MMIO, 0x4874, &mmDC_GPIO_DDC4_MASK[0], sizeof(mmDC_GPIO_DDC4_MASK)/sizeof(mmDC_GPIO_DDC4_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_A", REG_MMIO, 0x4875, &mmDC_GPIO_DDC4_A[0], sizeof(mmDC_GPIO_DDC4_A)/sizeof(mmDC_GPIO_DDC4_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_EN", REG_MMIO, 0x4876, &mmDC_GPIO_DDC4_EN[0], sizeof(mmDC_GPIO_DDC4_EN)/sizeof(mmDC_GPIO_DDC4_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_Y", REG_MMIO, 0x4877, &mmDC_GPIO_DDC4_Y[0], sizeof(mmDC_GPIO_DDC4_Y)/sizeof(mmDC_GPIO_DDC4_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_MASK", REG_MMIO, 0x4878, &mmDC_GPIO_DDC5_MASK[0], sizeof(mmDC_GPIO_DDC5_MASK)/sizeof(mmDC_GPIO_DDC5_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_A", REG_MMIO, 0x4879, &mmDC_GPIO_DDC5_A[0], sizeof(mmDC_GPIO_DDC5_A)/sizeof(mmDC_GPIO_DDC5_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_EN", REG_MMIO, 0x487a, &mmDC_GPIO_DDC5_EN[0], sizeof(mmDC_GPIO_DDC5_EN)/sizeof(mmDC_GPIO_DDC5_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_Y", REG_MMIO, 0x487b, &mmDC_GPIO_DDC5_Y[0], sizeof(mmDC_GPIO_DDC5_Y)/sizeof(mmDC_GPIO_DDC5_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_MASK", REG_MMIO, 0x487c, &mmDC_GPIO_DDC6_MASK[0], sizeof(mmDC_GPIO_DDC6_MASK)/sizeof(mmDC_GPIO_DDC6_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_A", REG_MMIO, 0x487d, &mmDC_GPIO_DDC6_A[0], sizeof(mmDC_GPIO_DDC6_A)/sizeof(mmDC_GPIO_DDC6_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_EN", REG_MMIO, 0x487e, &mmDC_GPIO_DDC6_EN[0], sizeof(mmDC_GPIO_DDC6_EN)/sizeof(mmDC_GPIO_DDC6_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_Y", REG_MMIO, 0x487f, &mmDC_GPIO_DDC6_Y[0], sizeof(mmDC_GPIO_DDC6_Y)/sizeof(mmDC_GPIO_DDC6_Y[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x488, NULL, 0, 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_MASK", REG_MMIO, 0x4880, &mmDC_GPIO_DDCVGA_MASK[0], sizeof(mmDC_GPIO_DDCVGA_MASK)/sizeof(mmDC_GPIO_DDCVGA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_A", REG_MMIO, 0x4881, &mmDC_GPIO_DDCVGA_A[0], sizeof(mmDC_GPIO_DDCVGA_A)/sizeof(mmDC_GPIO_DDCVGA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_EN", REG_MMIO, 0x4882, &mmDC_GPIO_DDCVGA_EN[0], sizeof(mmDC_GPIO_DDCVGA_EN)/sizeof(mmDC_GPIO_DDCVGA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_Y", REG_MMIO, 0x4883, &mmDC_GPIO_DDCVGA_Y[0], sizeof(mmDC_GPIO_DDCVGA_Y)/sizeof(mmDC_GPIO_DDCVGA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_MASK", REG_MMIO, 0x4884, &mmDC_GPIO_SYNCA_MASK[0], sizeof(mmDC_GPIO_SYNCA_MASK)/sizeof(mmDC_GPIO_SYNCA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_A", REG_MMIO, 0x4885, &mmDC_GPIO_SYNCA_A[0], sizeof(mmDC_GPIO_SYNCA_A)/sizeof(mmDC_GPIO_SYNCA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_EN", REG_MMIO, 0x4886, &mmDC_GPIO_SYNCA_EN[0], sizeof(mmDC_GPIO_SYNCA_EN)/sizeof(mmDC_GPIO_SYNCA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_Y", REG_MMIO, 0x4887, &mmDC_GPIO_SYNCA_Y[0], sizeof(mmDC_GPIO_SYNCA_Y)/sizeof(mmDC_GPIO_SYNCA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_MASK", REG_MMIO, 0x4888, &mmDC_GPIO_GENLK_MASK[0], sizeof(mmDC_GPIO_GENLK_MASK)/sizeof(mmDC_GPIO_GENLK_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_A", REG_MMIO, 0x4889, &mmDC_GPIO_GENLK_A[0], sizeof(mmDC_GPIO_GENLK_A)/sizeof(mmDC_GPIO_GENLK_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_EN", REG_MMIO, 0x488a, &mmDC_GPIO_GENLK_EN[0], sizeof(mmDC_GPIO_GENLK_EN)/sizeof(mmDC_GPIO_GENLK_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_Y", REG_MMIO, 0x488b, &mmDC_GPIO_GENLK_Y[0], sizeof(mmDC_GPIO_GENLK_Y)/sizeof(mmDC_GPIO_GENLK_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_MASK", REG_MMIO, 0x488c, &mmDC_GPIO_HPD_MASK[0], sizeof(mmDC_GPIO_HPD_MASK)/sizeof(mmDC_GPIO_HPD_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_A", REG_MMIO, 0x488d, &mmDC_GPIO_HPD_A[0], sizeof(mmDC_GPIO_HPD_A)/sizeof(mmDC_GPIO_HPD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_EN", REG_MMIO, 0x488e, &mmDC_GPIO_HPD_EN[0], sizeof(mmDC_GPIO_HPD_EN)/sizeof(mmDC_GPIO_HPD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_Y", REG_MMIO, 0x488f, &mmDC_GPIO_HPD_Y[0], sizeof(mmDC_GPIO_HPD_Y)/sizeof(mmDC_GPIO_HPD_Y[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x489, NULL, 0, 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_MASK", REG_MMIO, 0x4890, &mmDC_GPIO_PWRSEQ_MASK[0], sizeof(mmDC_GPIO_PWRSEQ_MASK)/sizeof(mmDC_GPIO_PWRSEQ_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_A", REG_MMIO, 0x4891, &mmDC_GPIO_PWRSEQ_A[0], sizeof(mmDC_GPIO_PWRSEQ_A)/sizeof(mmDC_GPIO_PWRSEQ_A[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_EN", REG_MMIO, 0x4892, &mmDC_GPIO_PWRSEQ_EN[0], sizeof(mmDC_GPIO_PWRSEQ_EN)/sizeof(mmDC_GPIO_PWRSEQ_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_Y", REG_MMIO, 0x4893, &mmDC_GPIO_PWRSEQ_Y[0], sizeof(mmDC_GPIO_PWRSEQ_Y)/sizeof(mmDC_GPIO_PWRSEQ_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_1", REG_MMIO, 0x4894, &mmDC_GPIO_PAD_STRENGTH_1[0], sizeof(mmDC_GPIO_PAD_STRENGTH_1)/sizeof(mmDC_GPIO_PAD_STRENGTH_1[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_2", REG_MMIO, 0x4895, &mmDC_GPIO_PAD_STRENGTH_2[0], sizeof(mmDC_GPIO_PAD_STRENGTH_2)/sizeof(mmDC_GPIO_PAD_STRENGTH_2[0]), 0, 0 },
+	{ "mmPHY_AUX_CNTL", REG_MMIO, 0x4897, &mmPHY_AUX_CNTL[0], sizeof(mmPHY_AUX_CNTL)/sizeof(mmPHY_AUX_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_MASK", REG_MMIO, 0x4898, &mmDC_GPIO_I2CPAD_MASK[0], sizeof(mmDC_GPIO_I2CPAD_MASK)/sizeof(mmDC_GPIO_I2CPAD_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_A", REG_MMIO, 0x4899, &mmDC_GPIO_I2CPAD_A[0], sizeof(mmDC_GPIO_I2CPAD_A)/sizeof(mmDC_GPIO_I2CPAD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_EN", REG_MMIO, 0x489a, &mmDC_GPIO_I2CPAD_EN[0], sizeof(mmDC_GPIO_I2CPAD_EN)/sizeof(mmDC_GPIO_I2CPAD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_Y", REG_MMIO, 0x489b, &mmDC_GPIO_I2CPAD_Y[0], sizeof(mmDC_GPIO_I2CPAD_Y)/sizeof(mmDC_GPIO_I2CPAD_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_STRENGTH", REG_MMIO, 0x489c, &mmDC_GPIO_I2CPAD_STRENGTH[0], sizeof(mmDC_GPIO_I2CPAD_STRENGTH)/sizeof(mmDC_GPIO_I2CPAD_STRENGTH[0]), 0, 0 },
+	{ "mmDVO_VREF_CONTROL", REG_MMIO, 0x489e, &mmDVO_VREF_CONTROL[0], sizeof(mmDVO_VREF_CONTROL)/sizeof(mmDVO_VREF_CONTROL[0]), 0, 0 },
+	{ "mmDVO_SKEW_ADJUST", REG_MMIO, 0x489f, &mmDVO_SKEW_ADJUST[0], sizeof(mmDVO_SKEW_ADJUST)/sizeof(mmDVO_SKEW_ADJUST[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x48a, NULL, 0, 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48b8, &mmDAC_MACRO_CNTL_RESERVED0[0], sizeof(mmDAC_MACRO_CNTL_RESERVED0)/sizeof(mmDAC_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48b9, &mmDAC_MACRO_CNTL_RESERVED1[0], sizeof(mmDAC_MACRO_CNTL_RESERVED1)/sizeof(mmDAC_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmBPHYC_DAC_MACRO_CNTL", REG_MMIO, 0x48b9, &mmBPHYC_DAC_MACRO_CNTL[0], sizeof(mmBPHYC_DAC_MACRO_CNTL)/sizeof(mmBPHYC_DAC_MACRO_CNTL[0]), 0, 0 },
+	{ "mmBPHYC_DAC_AUTO_CALIB_CONTROL", REG_MMIO, 0x48ba, &mmBPHYC_DAC_AUTO_CALIB_CONTROL[0], sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL)/sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48ba, &mmDAC_MACRO_CNTL_RESERVED2[0], sizeof(mmDAC_MACRO_CNTL_RESERVED2)/sizeof(mmDAC_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48bb, &mmDAC_MACRO_CNTL_RESERVED3[0], sizeof(mmDAC_MACRO_CNTL_RESERVED3)/sizeof(mmDAC_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48c0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL1", REG_MMIO, 0x48c0, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48c0, &mmUNIPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED0)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL1", REG_MMIO, 0x48c0, &mmUNIPHY_TX_CONTROL1[0], sizeof(mmUNIPHY_TX_CONTROL1)/sizeof(mmUNIPHY_TX_CONTROL1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48c1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL2", REG_MMIO, 0x48c1, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48c1, &mmUNIPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED1)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL2", REG_MMIO, 0x48c1, &mmUNIPHY_TX_CONTROL2[0], sizeof(mmUNIPHY_TX_CONTROL2)/sizeof(mmUNIPHY_TX_CONTROL2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48c2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL3", REG_MMIO, 0x48c2, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48c2, &mmUNIPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED2)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL3", REG_MMIO, 0x48c2, &mmUNIPHY_TX_CONTROL3[0], sizeof(mmUNIPHY_TX_CONTROL3)/sizeof(mmUNIPHY_TX_CONTROL3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48c3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TX_CONTROL4", REG_MMIO, 0x48c3, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48c3, &mmUNIPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED3)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL4", REG_MMIO, 0x48c3, &mmUNIPHY_TX_CONTROL4[0], sizeof(mmUNIPHY_TX_CONTROL4)/sizeof(mmUNIPHY_TX_CONTROL4[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x48c4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_POWER_CONTROL", REG_MMIO, 0x48c4, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x48c4, &mmUNIPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED4)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmUNIPHY_POWER_CONTROL", REG_MMIO, 0x48c4, &mmUNIPHY_POWER_CONTROL[0], sizeof(mmUNIPHY_POWER_CONTROL)/sizeof(mmUNIPHY_POWER_CONTROL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x48c5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_FBDIV", REG_MMIO, 0x48c5, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x48c5, &mmUNIPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED5)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_FBDIV", REG_MMIO, 0x48c5, &mmUNIPHY_PLL_FBDIV[0], sizeof(mmUNIPHY_PLL_FBDIV)/sizeof(mmUNIPHY_PLL_FBDIV[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x48c6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x48c6, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x48c6, &mmUNIPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED6)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_CONTROL1", REG_MMIO, 0x48c6, &mmUNIPHY_PLL_CONTROL1[0], sizeof(mmUNIPHY_PLL_CONTROL1)/sizeof(mmUNIPHY_PLL_CONTROL1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x48c7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x48c7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x48c7, &mmUNIPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED7)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_CONTROL2", REG_MMIO, 0x48c7, &mmUNIPHY_PLL_CONTROL2[0], sizeof(mmUNIPHY_PLL_CONTROL2)/sizeof(mmUNIPHY_PLL_CONTROL2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x48c8, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x48c8, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x48c8, &mmUNIPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED8)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x48c8, &mmUNIPHY_PLL_SS_STEP_SIZE[0], sizeof(mmUNIPHY_PLL_SS_STEP_SIZE)/sizeof(mmUNIPHY_PLL_SS_STEP_SIZE[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x48c9, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x48c9, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x48c9, &mmUNIPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED9)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmUNIPHY_PLL_SS_CNTL", REG_MMIO, 0x48c9, &mmUNIPHY_PLL_SS_CNTL[0], sizeof(mmUNIPHY_PLL_SS_CNTL)/sizeof(mmUNIPHY_PLL_SS_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x48ca, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x48ca, &mmUNIPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED10)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmUNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x48ca, &mmUNIPHY_DATA_SYNCHRONIZATION[0], sizeof(mmUNIPHY_DATA_SYNCHRONIZATION)/sizeof(mmUNIPHY_DATA_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x48cb, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x48cb, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x48cb, &mmUNIPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED11)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmUNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x48cb, &mmUNIPHY_REG_TEST_OUTPUT[0], sizeof(mmUNIPHY_REG_TEST_OUTPUT)/sizeof(mmUNIPHY_REG_TEST_OUTPUT[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x48cc, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x48cc, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x48cc, &mmUNIPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED12)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmUNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x48cc, &mmUNIPHY_ANG_BIST_CNTL[0], sizeof(mmUNIPHY_ANG_BIST_CNTL)/sizeof(mmUNIPHY_ANG_BIST_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x48cd, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x48cd, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x48cd, &mmUNIPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED13)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmUNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x48cd, &mmUNIPHY_REG_TEST_OUTPUT2[0], sizeof(mmUNIPHY_REG_TEST_OUTPUT2)/sizeof(mmUNIPHY_REG_TEST_OUTPUT2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x48ce, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG0", REG_MMIO, 0x48ce, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x48ce, &mmUNIPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED14)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG0", REG_MMIO, 0x48ce, &mmUNIPHY_TMDP_REG0[0], sizeof(mmUNIPHY_TMDP_REG0)/sizeof(mmUNIPHY_TMDP_REG0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x48cf, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG1", REG_MMIO, 0x48cf, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x48cf, &mmUNIPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED15)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG1", REG_MMIO, 0x48cf, &mmUNIPHY_TMDP_REG1[0], sizeof(mmUNIPHY_TMDP_REG1)/sizeof(mmUNIPHY_TMDP_REG1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x48d0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG2", REG_MMIO, 0x48d0, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x48d0, &mmUNIPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED16)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG2", REG_MMIO, 0x48d0, &mmUNIPHY_TMDP_REG2[0], sizeof(mmUNIPHY_TMDP_REG2)/sizeof(mmUNIPHY_TMDP_REG2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x48d1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG3", REG_MMIO, 0x48d1, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x48d1, &mmUNIPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED17)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG3", REG_MMIO, 0x48d1, &mmUNIPHY_TMDP_REG3[0], sizeof(mmUNIPHY_TMDP_REG3)/sizeof(mmUNIPHY_TMDP_REG3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x48d2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG4", REG_MMIO, 0x48d2, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x48d2, &mmUNIPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED18)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG4", REG_MMIO, 0x48d2, &mmUNIPHY_TMDP_REG4[0], sizeof(mmUNIPHY_TMDP_REG4)/sizeof(mmUNIPHY_TMDP_REG4[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x48d3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG5", REG_MMIO, 0x48d3, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x48d3, &mmUNIPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED19)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG5", REG_MMIO, 0x48d3, &mmUNIPHY_TMDP_REG5[0], sizeof(mmUNIPHY_TMDP_REG5)/sizeof(mmUNIPHY_TMDP_REG5[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x48d4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TMDP_REG6", REG_MMIO, 0x48d4, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x48d4, &mmUNIPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED20)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmUNIPHY_TMDP_REG6", REG_MMIO, 0x48d4, &mmUNIPHY_TMDP_REG6[0], sizeof(mmUNIPHY_TMDP_REG6)/sizeof(mmUNIPHY_TMDP_REG6[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x48d5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TPG_CONTROL", REG_MMIO, 0x48d5, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x48d5, &mmUNIPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED21)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmUNIPHY_TPG_CONTROL", REG_MMIO, 0x48d5, &mmUNIPHY_TPG_CONTROL[0], sizeof(mmUNIPHY_TPG_CONTROL)/sizeof(mmUNIPHY_TPG_CONTROL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x48d6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_TPG_SEED", REG_MMIO, 0x48d6, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x48d6, &mmUNIPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED22)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmUNIPHY_TPG_SEED", REG_MMIO, 0x48d6, &mmUNIPHY_TPG_SEED[0], sizeof(mmUNIPHY_TPG_SEED)/sizeof(mmUNIPHY_TPG_SEED[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x48d7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x48d7, &mmUNIPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED23)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmBPHYC_UNIPHY0_UNIPHY_DEBUG", REG_MMIO, 0x48d7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_DEBUG", REG_MMIO, 0x48d7, &mmUNIPHY_DEBUG[0], sizeof(mmUNIPHY_DEBUG)/sizeof(mmUNIPHY_DEBUG[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x48d8, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x48d8, &mmUNIPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED24)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x48d9, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x48d9, &mmUNIPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED25)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x48da, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x48da, &mmUNIPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED26)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x48db, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x48db, &mmUNIPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED27)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x48dc, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x48dc, &mmUNIPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED28)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x48dd, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x48dd, &mmUNIPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED29)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x48de, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x48de, &mmUNIPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED30)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x48df, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x48df, &mmUNIPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED31)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48e0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL1", REG_MMIO, 0x48e0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48e1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL2", REG_MMIO, 0x48e1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48e2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL3", REG_MMIO, 0x48e2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48e3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TX_CONTROL4", REG_MMIO, 0x48e3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x48e4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_POWER_CONTROL", REG_MMIO, 0x48e4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x48e5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_FBDIV", REG_MMIO, 0x48e5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x48e6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x48e6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x48e7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x48e7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x48e8, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x48e8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x48e9, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x48e9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x48ea, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x48eb, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x48eb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x48ec, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x48ec, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x48ed, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x48ed, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x48ee, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG0", REG_MMIO, 0x48ee, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x48ef, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG1", REG_MMIO, 0x48ef, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x48f0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG2", REG_MMIO, 0x48f0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x48f1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG3", REG_MMIO, 0x48f1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x48f2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG4", REG_MMIO, 0x48f2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x48f3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG5", REG_MMIO, 0x48f3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x48f4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TMDP_REG6", REG_MMIO, 0x48f4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x48f5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TPG_CONTROL", REG_MMIO, 0x48f5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x48f6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_TPG_SEED", REG_MMIO, 0x48f6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x48f7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY1_UNIPHY_DEBUG", REG_MMIO, 0x48f7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x48f8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x48f9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x48fa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x48fb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x48fc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x48fd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x48fe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x48ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x490, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4900, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4900, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4901, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4901, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4902, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4902, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4903, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4903, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4904, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4904, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4905, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4905, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4906, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4906, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4907, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4907, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4908, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4908, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4909, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4909, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x490a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x490b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x490b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x490c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x490c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x490d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x490d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x490e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG0", REG_MMIO, 0x490e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x490f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG1", REG_MMIO, 0x490f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x491, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4910, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG2", REG_MMIO, 0x4910, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4911, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG3", REG_MMIO, 0x4911, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4912, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG4", REG_MMIO, 0x4912, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4913, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG5", REG_MMIO, 0x4913, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4914, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TMDP_REG6", REG_MMIO, 0x4914, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4915, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4915, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4916, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_TPG_SEED", REG_MMIO, 0x4916, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4917, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY2_UNIPHY_DEBUG", REG_MMIO, 0x4917, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4918, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4919, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x491a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x491b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x491c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x491d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x491e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x491f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x492, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4920, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4920, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4921, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4921, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4922, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4922, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4923, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4923, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4924, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4924, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4925, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4925, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4926, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4926, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4927, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4927, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4929, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4929, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x492a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x492b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x492b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x492c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x492c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x492d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x492d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x492e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG0", REG_MMIO, 0x492e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x492f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG1", REG_MMIO, 0x492f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4930, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG2", REG_MMIO, 0x4930, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4931, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG3", REG_MMIO, 0x4931, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4932, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG4", REG_MMIO, 0x4932, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4933, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG5", REG_MMIO, 0x4933, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4934, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TMDP_REG6", REG_MMIO, 0x4934, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4935, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4935, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4936, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_TPG_SEED", REG_MMIO, 0x4936, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4937, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY3_UNIPHY_DEBUG", REG_MMIO, 0x4937, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4938, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4939, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x493a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x493b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x493c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x493d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x493e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x493f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4940, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4940, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4941, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4941, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4942, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4942, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4943, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4943, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4944, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4944, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4945, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4945, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4946, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4946, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4947, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4947, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4948, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4948, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4949, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4949, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x494a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x494b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x494b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x494c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x494c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x494d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x494d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x494e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG0", REG_MMIO, 0x494e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x494f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG1", REG_MMIO, 0x494f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4950, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG2", REG_MMIO, 0x4950, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4951, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG3", REG_MMIO, 0x4951, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4952, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG4", REG_MMIO, 0x4952, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4953, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG5", REG_MMIO, 0x4953, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4954, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TMDP_REG6", REG_MMIO, 0x4954, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4955, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4955, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4956, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_TPG_SEED", REG_MMIO, 0x4956, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4957, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY4_UNIPHY_DEBUG", REG_MMIO, 0x4957, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4958, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4959, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x495a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x495b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x495c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x495d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x495e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x495f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4960, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4960, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4961, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4961, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4962, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4962, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4963, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4963, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4964, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4964, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4965, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4965, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4966, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4966, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4967, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4967, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4968, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4968, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4969, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4969, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x496a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x496b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x496b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x496c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x496c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x496d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x496d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x496e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG0", REG_MMIO, 0x496e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x496f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG1", REG_MMIO, 0x496f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4970, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG2", REG_MMIO, 0x4970, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4971, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG3", REG_MMIO, 0x4971, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4972, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG4", REG_MMIO, 0x4972, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4973, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG5", REG_MMIO, 0x4973, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4974, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TMDP_REG6", REG_MMIO, 0x4974, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4975, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4975, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4976, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_TPG_SEED", REG_MMIO, 0x4976, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4977, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY5_UNIPHY_DEBUG", REG_MMIO, 0x4977, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4978, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4979, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x497a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x497b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x497c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x497d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x497e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x497f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x498, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4980, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4980, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4981, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4981, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4982, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4982, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4983, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4983, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4984, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4984, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4985, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4985, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4986, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4986, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4987, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4987, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4988, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4988, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4989, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4989, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x498a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x498b, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x498b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x498c, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x498c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x498d, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x498d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x498e, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG0", REG_MMIO, 0x498e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x498f, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG1", REG_MMIO, 0x498f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x499, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4990, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG2", REG_MMIO, 0x4990, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4991, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG3", REG_MMIO, 0x4991, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4992, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG4", REG_MMIO, 0x4992, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4993, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG5", REG_MMIO, 0x4993, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4994, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TMDP_REG6", REG_MMIO, 0x4994, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4995, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TPG_CONTROL", REG_MMIO, 0x4995, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4996, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_TPG_SEED", REG_MMIO, 0x4996, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4997, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY6_UNIPHY_DEBUG", REG_MMIO, 0x4997, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4998, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4999, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x499a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x499b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x499c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x499d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x499e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x499f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x49a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x49c0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL1", REG_MMIO, 0x49c0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x49c1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL2", REG_MMIO, 0x49c1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x49c2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL3", REG_MMIO, 0x49c2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x49c3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TX_CONTROL4", REG_MMIO, 0x49c3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x49c4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_POWER_CONTROL", REG_MMIO, 0x49c4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x49c5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_PLL_FBDIV", REG_MMIO, 0x49c5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x49c6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x49c6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x49c7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x49c7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x49c8, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x49c8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x49c9, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x49c9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x49ca, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x49cb, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x49cb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x49cc, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x49cc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x49cd, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x49cd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x49ce, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG0", REG_MMIO, 0x49ce, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x49cf, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG1", REG_MMIO, 0x49cf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x49d0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG2", REG_MMIO, 0x49d0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x49d1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG3", REG_MMIO, 0x49d1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x49d2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG4", REG_MMIO, 0x49d2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x49d3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG5", REG_MMIO, 0x49d3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x49d4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TMDP_REG6", REG_MMIO, 0x49d4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x49d5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TPG_CONTROL", REG_MMIO, 0x49d5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x49d6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_TPG_SEED", REG_MMIO, 0x49d6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x49d7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY7_UNIPHY_DEBUG", REG_MMIO, 0x49d7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x49d8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x49d9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x49da, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x49db, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x49dc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x49dd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x49de, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x49df, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x49e0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL1", REG_MMIO, 0x49e0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x49e1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL2", REG_MMIO, 0x49e1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x49e2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL3", REG_MMIO, 0x49e2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x49e3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TX_CONTROL4", REG_MMIO, 0x49e3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x49e4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_POWER_CONTROL", REG_MMIO, 0x49e4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x49e5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_PLL_FBDIV", REG_MMIO, 0x49e5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x49e6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x49e6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x49e7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x49e7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x49e8, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x49e8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x49e9, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x49e9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x49ea, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x49eb, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x49eb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x49ec, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x49ec, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x49ed, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x49ed, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x49ee, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG0", REG_MMIO, 0x49ee, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x49ef, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG1", REG_MMIO, 0x49ef, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x49f0, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG2", REG_MMIO, 0x49f0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x49f1, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG3", REG_MMIO, 0x49f1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x49f2, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG4", REG_MMIO, 0x49f2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x49f3, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG5", REG_MMIO, 0x49f3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x49f4, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TMDP_REG6", REG_MMIO, 0x49f4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x49f5, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TPG_CONTROL", REG_MMIO, 0x49f5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x49f6, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_TPG_SEED", REG_MMIO, 0x49f6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x49f7, NULL, 0, 0, 0 },
+	{ "mmBPHYC_UNIPHY8_UNIPHY_DEBUG", REG_MMIO, 0x49f7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x49f8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x49f9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x49fa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x49fb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x49fc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x49fd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x49fe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY8_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x49ff, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_FE_CNTL", REG_MMIO, 0x4a00, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_CNTL", REG_MMIO, 0x4a00, &mmDIG_FE_CNTL[0], sizeof(mmDIG_FE_CNTL)/sizeof(mmDIG_FE_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4a01, NULL, 0, 0, 0 },
+	{ "mmDIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4a01, &mmDIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG_OUTPUT_CRC_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4a02, NULL, 0, 0, 0 },
+	{ "mmDIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4a02, &mmDIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG_OUTPUT_CRC_RESULT[0]), 0, 0 },
+	{ "mmDIG0_DIG_CLOCK_PATTERN", REG_MMIO, 0x4a03, NULL, 0, 0, 0 },
+	{ "mmDIG_CLOCK_PATTERN", REG_MMIO, 0x4a03, &mmDIG_CLOCK_PATTERN[0], sizeof(mmDIG_CLOCK_PATTERN)/sizeof(mmDIG_CLOCK_PATTERN[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_PATTERN", REG_MMIO, 0x4a04, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_PATTERN", REG_MMIO, 0x4a04, &mmDIG_TEST_PATTERN[0], sizeof(mmDIG_TEST_PATTERN)/sizeof(mmDIG_TEST_PATTERN[0]), 0, 0 },
+	{ "mmDIG0_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4a05, NULL, 0, 0, 0 },
+	{ "mmDIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4a05, &mmDIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG_RANDOM_PATTERN_SEED[0]), 0, 0 },
+	{ "mmDIG0_DIG_FIFO_STATUS", REG_MMIO, 0x4a06, NULL, 0, 0, 0 },
+	{ "mmDIG_FIFO_STATUS", REG_MMIO, 0x4a06, &mmDIG_FIFO_STATUS[0], sizeof(mmDIG_FIFO_STATUS)/sizeof(mmDIG_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4a07, NULL, 0, 0, 0 },
+	{ "mmDIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4a07, &mmDIG_DISPCLK_SWITCH_CNTL[0], sizeof(mmDIG_DISPCLK_SWITCH_CNTL)/sizeof(mmDIG_DISPCLK_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4a08, NULL, 0, 0, 0 },
+	{ "mmDIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4a08, &mmDIG_DISPCLK_SWITCH_STATUS[0], sizeof(mmDIG_DISPCLK_SWITCH_STATUS)/sizeof(mmDIG_DISPCLK_SWITCH_STATUS[0]), 0, 0 },
+	{ "mmDIG0_HDMI_CONTROL", REG_MMIO, 0x4a09, NULL, 0, 0, 0 },
+	{ "mmHDMI_CONTROL", REG_MMIO, 0x4a09, &mmHDMI_CONTROL[0], sizeof(mmHDMI_CONTROL)/sizeof(mmHDMI_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_STATUS", REG_MMIO, 0x4a0a, NULL, 0, 0, 0 },
+	{ "mmHDMI_STATUS", REG_MMIO, 0x4a0a, &mmHDMI_STATUS[0], sizeof(mmHDMI_STATUS)/sizeof(mmHDMI_STATUS[0]), 0, 0 },
+	{ "mmDIG0_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a0b, NULL, 0, 0, 0 },
+	{ "mmHDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a0b, &mmHDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmHDMI_AUDIO_PACKET_CONTROL)/sizeof(mmHDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4a0c, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4a0c, &mmHDMI_ACR_PACKET_CONTROL[0], sizeof(mmHDMI_ACR_PACKET_CONTROL)/sizeof(mmHDMI_ACR_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4a0d, NULL, 0, 0, 0 },
+	{ "mmHDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4a0d, &mmHDMI_VBI_PACKET_CONTROL[0], sizeof(mmHDMI_VBI_PACKET_CONTROL)/sizeof(mmHDMI_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4a0e, NULL, 0, 0, 0 },
+	{ "mmHDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4a0e, &mmHDMI_INFOFRAME_CONTROL0[0], sizeof(mmHDMI_INFOFRAME_CONTROL0)/sizeof(mmHDMI_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4a0f, NULL, 0, 0, 0 },
+	{ "mmHDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4a0f, &mmHDMI_INFOFRAME_CONTROL1[0], sizeof(mmHDMI_INFOFRAME_CONTROL1)/sizeof(mmHDMI_INFOFRAME_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4a10, NULL, 0, 0, 0 },
+	{ "mmHDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4a10, &mmHDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmHDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmHDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4a11, NULL, 0, 0, 0 },
+	{ "mmAFMT_INTERRUPT_STATUS", REG_MMIO, 0x4a11, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_GC", REG_MMIO, 0x4a13, NULL, 0, 0, 0 },
+	{ "mmHDMI_GC", REG_MMIO, 0x4a13, &mmHDMI_GC[0], sizeof(mmHDMI_GC)/sizeof(mmHDMI_GC[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4a14, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4a14, &mmAFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_0", REG_MMIO, 0x4a15, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_0", REG_MMIO, 0x4a15, &mmAFMT_ISRC1_0[0], sizeof(mmAFMT_ISRC1_0)/sizeof(mmAFMT_ISRC1_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_1", REG_MMIO, 0x4a16, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_1", REG_MMIO, 0x4a16, &mmAFMT_ISRC1_1[0], sizeof(mmAFMT_ISRC1_1)/sizeof(mmAFMT_ISRC1_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_2", REG_MMIO, 0x4a17, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_2", REG_MMIO, 0x4a17, &mmAFMT_ISRC1_2[0], sizeof(mmAFMT_ISRC1_2)/sizeof(mmAFMT_ISRC1_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_3", REG_MMIO, 0x4a18, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_3", REG_MMIO, 0x4a18, &mmAFMT_ISRC1_3[0], sizeof(mmAFMT_ISRC1_3)/sizeof(mmAFMT_ISRC1_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_4", REG_MMIO, 0x4a19, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_4", REG_MMIO, 0x4a19, &mmAFMT_ISRC1_4[0], sizeof(mmAFMT_ISRC1_4)/sizeof(mmAFMT_ISRC1_4[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_0", REG_MMIO, 0x4a1a, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_0", REG_MMIO, 0x4a1a, &mmAFMT_ISRC2_0[0], sizeof(mmAFMT_ISRC2_0)/sizeof(mmAFMT_ISRC2_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_1", REG_MMIO, 0x4a1b, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_1", REG_MMIO, 0x4a1b, &mmAFMT_ISRC2_1[0], sizeof(mmAFMT_ISRC2_1)/sizeof(mmAFMT_ISRC2_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_2", REG_MMIO, 0x4a1c, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_2", REG_MMIO, 0x4a1c, &mmAFMT_ISRC2_2[0], sizeof(mmAFMT_ISRC2_2)/sizeof(mmAFMT_ISRC2_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_3", REG_MMIO, 0x4a1d, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_3", REG_MMIO, 0x4a1d, &mmAFMT_ISRC2_3[0], sizeof(mmAFMT_ISRC2_3)/sizeof(mmAFMT_ISRC2_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO0", REG_MMIO, 0x4a1e, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO0", REG_MMIO, 0x4a1e, &mmAFMT_AVI_INFO0[0], sizeof(mmAFMT_AVI_INFO0)/sizeof(mmAFMT_AVI_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO1", REG_MMIO, 0x4a1f, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO1", REG_MMIO, 0x4a1f, &mmAFMT_AVI_INFO1[0], sizeof(mmAFMT_AVI_INFO1)/sizeof(mmAFMT_AVI_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO2", REG_MMIO, 0x4a20, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO2", REG_MMIO, 0x4a20, &mmAFMT_AVI_INFO2[0], sizeof(mmAFMT_AVI_INFO2)/sizeof(mmAFMT_AVI_INFO2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO3", REG_MMIO, 0x4a21, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO3", REG_MMIO, 0x4a21, &mmAFMT_AVI_INFO3[0], sizeof(mmAFMT_AVI_INFO3)/sizeof(mmAFMT_AVI_INFO3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_MPEG_INFO0", REG_MMIO, 0x4a22, NULL, 0, 0, 0 },
+	{ "mmAFMT_MPEG_INFO0", REG_MMIO, 0x4a22, &mmAFMT_MPEG_INFO0[0], sizeof(mmAFMT_MPEG_INFO0)/sizeof(mmAFMT_MPEG_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_MPEG_INFO1", REG_MMIO, 0x4a23, NULL, 0, 0, 0 },
+	{ "mmAFMT_MPEG_INFO1", REG_MMIO, 0x4a23, &mmAFMT_MPEG_INFO1[0], sizeof(mmAFMT_MPEG_INFO1)/sizeof(mmAFMT_MPEG_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_HDR", REG_MMIO, 0x4a24, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_HDR", REG_MMIO, 0x4a24, &mmAFMT_GENERIC_HDR[0], sizeof(mmAFMT_GENERIC_HDR)/sizeof(mmAFMT_GENERIC_HDR[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_0", REG_MMIO, 0x4a25, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_0", REG_MMIO, 0x4a25, &mmAFMT_GENERIC_0[0], sizeof(mmAFMT_GENERIC_0)/sizeof(mmAFMT_GENERIC_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_1", REG_MMIO, 0x4a26, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_1", REG_MMIO, 0x4a26, &mmAFMT_GENERIC_1[0], sizeof(mmAFMT_GENERIC_1)/sizeof(mmAFMT_GENERIC_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_2", REG_MMIO, 0x4a27, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_2", REG_MMIO, 0x4a27, &mmAFMT_GENERIC_2[0], sizeof(mmAFMT_GENERIC_2)/sizeof(mmAFMT_GENERIC_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_3", REG_MMIO, 0x4a28, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_3", REG_MMIO, 0x4a28, &mmAFMT_GENERIC_3[0], sizeof(mmAFMT_GENERIC_3)/sizeof(mmAFMT_GENERIC_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_4", REG_MMIO, 0x4a29, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_4", REG_MMIO, 0x4a29, &mmAFMT_GENERIC_4[0], sizeof(mmAFMT_GENERIC_4)/sizeof(mmAFMT_GENERIC_4[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_5", REG_MMIO, 0x4a2a, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_5", REG_MMIO, 0x4a2a, &mmAFMT_GENERIC_5[0], sizeof(mmAFMT_GENERIC_5)/sizeof(mmAFMT_GENERIC_5[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_6", REG_MMIO, 0x4a2b, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_6", REG_MMIO, 0x4a2b, &mmAFMT_GENERIC_6[0], sizeof(mmAFMT_GENERIC_6)/sizeof(mmAFMT_GENERIC_6[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_7", REG_MMIO, 0x4a2c, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_7", REG_MMIO, 0x4a2c, &mmAFMT_GENERIC_7[0], sizeof(mmAFMT_GENERIC_7)/sizeof(mmAFMT_GENERIC_7[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4a2d, NULL, 0, 0, 0 },
+	{ "mmHDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4a2d, &mmHDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmHDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmHDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_0", REG_MMIO, 0x4a2e, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_32_0", REG_MMIO, 0x4a2e, &mmHDMI_ACR_32_0[0], sizeof(mmHDMI_ACR_32_0)/sizeof(mmHDMI_ACR_32_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_1", REG_MMIO, 0x4a2f, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_32_1", REG_MMIO, 0x4a2f, &mmHDMI_ACR_32_1[0], sizeof(mmHDMI_ACR_32_1)/sizeof(mmHDMI_ACR_32_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_0", REG_MMIO, 0x4a30, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_44_0", REG_MMIO, 0x4a30, &mmHDMI_ACR_44_0[0], sizeof(mmHDMI_ACR_44_0)/sizeof(mmHDMI_ACR_44_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_1", REG_MMIO, 0x4a31, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_44_1", REG_MMIO, 0x4a31, &mmHDMI_ACR_44_1[0], sizeof(mmHDMI_ACR_44_1)/sizeof(mmHDMI_ACR_44_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_0", REG_MMIO, 0x4a32, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_48_0", REG_MMIO, 0x4a32, &mmHDMI_ACR_48_0[0], sizeof(mmHDMI_ACR_48_0)/sizeof(mmHDMI_ACR_48_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_1", REG_MMIO, 0x4a33, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_48_1", REG_MMIO, 0x4a33, &mmHDMI_ACR_48_1[0], sizeof(mmHDMI_ACR_48_1)/sizeof(mmHDMI_ACR_48_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_0", REG_MMIO, 0x4a34, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_STATUS_0", REG_MMIO, 0x4a34, &mmHDMI_ACR_STATUS_0[0], sizeof(mmHDMI_ACR_STATUS_0)/sizeof(mmHDMI_ACR_STATUS_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_1", REG_MMIO, 0x4a35, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_STATUS_1", REG_MMIO, 0x4a35, &mmHDMI_ACR_STATUS_1[0], sizeof(mmHDMI_ACR_STATUS_1)/sizeof(mmHDMI_ACR_STATUS_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_INFO0", REG_MMIO, 0x4a36, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO0", REG_MMIO, 0x4a36, &mmAFMT_AUDIO_INFO0[0], sizeof(mmAFMT_AUDIO_INFO0)/sizeof(mmAFMT_AUDIO_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_INFO1", REG_MMIO, 0x4a37, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO1", REG_MMIO, 0x4a37, &mmAFMT_AUDIO_INFO1[0], sizeof(mmAFMT_AUDIO_INFO1)/sizeof(mmAFMT_AUDIO_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_0", REG_MMIO, 0x4a38, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_0", REG_MMIO, 0x4a38, &mmAFMT_60958_0[0], sizeof(mmAFMT_60958_0)/sizeof(mmAFMT_60958_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_1", REG_MMIO, 0x4a39, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_1", REG_MMIO, 0x4a39, &mmAFMT_60958_1[0], sizeof(mmAFMT_60958_1)/sizeof(mmAFMT_60958_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4a3a, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4a3a, &mmAFMT_AUDIO_CRC_CONTROL[0], sizeof(mmAFMT_AUDIO_CRC_CONTROL)/sizeof(mmAFMT_AUDIO_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4a3b, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL0", REG_MMIO, 0x4a3b, &mmAFMT_RAMP_CONTROL0[0], sizeof(mmAFMT_RAMP_CONTROL0)/sizeof(mmAFMT_RAMP_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4a3c, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL1", REG_MMIO, 0x4a3c, &mmAFMT_RAMP_CONTROL1[0], sizeof(mmAFMT_RAMP_CONTROL1)/sizeof(mmAFMT_RAMP_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4a3d, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL2", REG_MMIO, 0x4a3d, &mmAFMT_RAMP_CONTROL2[0], sizeof(mmAFMT_RAMP_CONTROL2)/sizeof(mmAFMT_RAMP_CONTROL2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4a3e, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL3", REG_MMIO, 0x4a3e, &mmAFMT_RAMP_CONTROL3[0], sizeof(mmAFMT_RAMP_CONTROL3)/sizeof(mmAFMT_RAMP_CONTROL3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_2", REG_MMIO, 0x4a3f, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_2", REG_MMIO, 0x4a3f, &mmAFMT_60958_2[0], sizeof(mmAFMT_60958_2)/sizeof(mmAFMT_60958_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4a40, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4a40, &mmAFMT_AUDIO_CRC_RESULT[0], sizeof(mmAFMT_AUDIO_CRC_RESULT)/sizeof(mmAFMT_AUDIO_CRC_RESULT[0]), 0, 0 },
+	{ "mmDIG0_AFMT_STATUS", REG_MMIO, 0x4a41, NULL, 0, 0, 0 },
+	{ "mmAFMT_STATUS", REG_MMIO, 0x4a41, &mmAFMT_STATUS[0], sizeof(mmAFMT_STATUS)/sizeof(mmAFMT_STATUS[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a42, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a42, &mmAFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4a43, NULL, 0, 0, 0 },
+	{ "mmAFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4a43, &mmAFMT_VBI_PACKET_CONTROL[0], sizeof(mmAFMT_VBI_PACKET_CONTROL)/sizeof(mmAFMT_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4a44, NULL, 0, 0, 0 },
+	{ "mmAFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4a44, &mmAFMT_INFOFRAME_CONTROL0[0], sizeof(mmAFMT_INFOFRAME_CONTROL0)/sizeof(mmAFMT_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4a45, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4a45, &mmAFMT_AUDIO_SRC_CONTROL[0], sizeof(mmAFMT_AUDIO_SRC_CONTROL)/sizeof(mmAFMT_AUDIO_SRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4a46, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4a46, &mmAFMT_AUDIO_DBG_DTO_CNTL[0], sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL)/sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_CNTL", REG_MMIO, 0x4a47, NULL, 0, 0, 0 },
+	{ "mmDIG_BE_CNTL", REG_MMIO, 0x4a47, &mmDIG_BE_CNTL[0], sizeof(mmDIG_BE_CNTL)/sizeof(mmDIG_BE_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_EN_CNTL", REG_MMIO, 0x4a48, NULL, 0, 0, 0 },
+	{ "mmDIG_BE_EN_CNTL", REG_MMIO, 0x4a48, &mmDIG_BE_EN_CNTL[0], sizeof(mmDIG_BE_EN_CNTL)/sizeof(mmDIG_BE_EN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CNTL", REG_MMIO, 0x4a6b, NULL, 0, 0, 0 },
+	{ "mmTMDS_CNTL", REG_MMIO, 0x4a6b, &mmTMDS_CNTL[0], sizeof(mmTMDS_CNTL)/sizeof(mmTMDS_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL_CHAR", REG_MMIO, 0x4a6c, NULL, 0, 0, 0 },
+	{ "mmTMDS_CONTROL_CHAR", REG_MMIO, 0x4a6c, &mmTMDS_CONTROL_CHAR[0], sizeof(mmTMDS_CONTROL_CHAR)/sizeof(mmTMDS_CONTROL_CHAR[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4a6d, NULL, 0, 0, 0 },
+	{ "mmTMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4a6d, &mmTMDS_CONTROL0_FEEDBACK[0], sizeof(mmTMDS_CONTROL0_FEEDBACK)/sizeof(mmTMDS_CONTROL0_FEEDBACK[0]), 0, 0 },
+	{ "mmDIG0_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4a6e, NULL, 0, 0, 0 },
+	{ "mmTMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4a6e, &mmTMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmTMDS_STEREOSYNC_CTL_SEL)/sizeof(mmTMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4a6f, NULL, 0, 0, 0 },
+	{ "mmTMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4a6f, &mmTMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmTMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmTMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4a70, NULL, 0, 0, 0 },
+	{ "mmTMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4a70, &mmTMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmTMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmTMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 },
+	{ "mmDIG0_TMDS_DEBUG", REG_MMIO, 0x4a71, NULL, 0, 0, 0 },
+	{ "mmTMDS_DEBUG", REG_MMIO, 0x4a71, &mmTMDS_DEBUG[0], sizeof(mmTMDS_DEBUG)/sizeof(mmTMDS_DEBUG[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL_BITS", REG_MMIO, 0x4a72, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL_BITS", REG_MMIO, 0x4a72, &mmTMDS_CTL_BITS[0], sizeof(mmTMDS_CTL_BITS)/sizeof(mmTMDS_CTL_BITS[0]), 0, 0 },
+	{ "mmDIG0_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4a73, NULL, 0, 0, 0 },
+	{ "mmTMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4a73, &mmTMDS_DCBALANCER_CONTROL[0], sizeof(mmTMDS_DCBALANCER_CONTROL)/sizeof(mmTMDS_DCBALANCER_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4a75, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4a75, &mmTMDS_CTL0_1_GEN_CNTL[0], sizeof(mmTMDS_CTL0_1_GEN_CNTL)/sizeof(mmTMDS_CTL0_1_GEN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4a76, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4a76, &mmTMDS_CTL2_3_GEN_CNTL[0], sizeof(mmTMDS_CTL2_3_GEN_CNTL)/sizeof(mmTMDS_CTL2_3_GEN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_VERSION", REG_MMIO, 0x4a78, NULL, 0, 0, 0 },
+	{ "mmDIG_VERSION", REG_MMIO, 0x4a78, &mmDIG_VERSION[0], sizeof(mmDIG_VERSION)/sizeof(mmDIG_VERSION[0]), 0, 0 },
+	{ "mmDIG0_DIG_LANE_ENABLE", REG_MMIO, 0x4a79, NULL, 0, 0, 0 },
+	{ "mmDIG_LANE_ENABLE", REG_MMIO, 0x4a79, &mmDIG_LANE_ENABLE[0], sizeof(mmDIG_LANE_ENABLE)/sizeof(mmDIG_LANE_ENABLE[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7a, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7a, &mmDIG_TEST_DEBUG_INDEX[0], sizeof(mmDIG_TEST_DEBUG_INDEX)/sizeof(mmDIG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4a7b, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_DEBUG_DATA", REG_MMIO, 0x4a7b, &mmDIG_TEST_DEBUG_DATA[0], sizeof(mmDIG_TEST_DEBUG_DATA)/sizeof(mmDIG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDIG0_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7c, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7c, &mmDIG_FE_TEST_DEBUG_INDEX[0], sizeof(mmDIG_FE_TEST_DEBUG_INDEX)/sizeof(mmDIG_FE_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDIG0_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4a7d, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4a7d, &mmDIG_FE_TEST_DEBUG_DATA[0], sizeof(mmDIG_FE_TEST_DEBUG_DATA)/sizeof(mmDIG_FE_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDIG0_AFMT_CNTL", REG_MMIO, 0x4a7e, NULL, 0, 0, 0 },
+	{ "mmAFMT_CNTL", REG_MMIO, 0x4a7e, &mmAFMT_CNTL[0], sizeof(mmAFMT_CNTL)/sizeof(mmAFMT_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_LINK_CNTL", REG_MMIO, 0x4aa0, NULL, 0, 0, 0 },
+	{ "mmDP_LINK_CNTL", REG_MMIO, 0x4aa0, &mmDP_LINK_CNTL[0], sizeof(mmDP_LINK_CNTL)/sizeof(mmDP_LINK_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_PIXEL_FORMAT", REG_MMIO, 0x4aa1, NULL, 0, 0, 0 },
+	{ "mmDP_PIXEL_FORMAT", REG_MMIO, 0x4aa1, &mmDP_PIXEL_FORMAT[0], sizeof(mmDP_PIXEL_FORMAT)/sizeof(mmDP_PIXEL_FORMAT[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_COLORIMETRY", REG_MMIO, 0x4aa2, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_COLORIMETRY", REG_MMIO, 0x4aa2, &mmDP_MSA_COLORIMETRY[0], sizeof(mmDP_MSA_COLORIMETRY)/sizeof(mmDP_MSA_COLORIMETRY[0]), 0, 0 },
+	{ "mmDP0_DP_CONFIG", REG_MMIO, 0x4aa3, NULL, 0, 0, 0 },
+	{ "mmDP_CONFIG", REG_MMIO, 0x4aa3, &mmDP_CONFIG[0], sizeof(mmDP_CONFIG)/sizeof(mmDP_CONFIG[0]), 0, 0 },
+	{ "mmDP0_DP_VID_STREAM_CNTL", REG_MMIO, 0x4aa4, NULL, 0, 0, 0 },
+	{ "mmDP_VID_STREAM_CNTL", REG_MMIO, 0x4aa4, &mmDP_VID_STREAM_CNTL[0], sizeof(mmDP_VID_STREAM_CNTL)/sizeof(mmDP_VID_STREAM_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_STEER_FIFO", REG_MMIO, 0x4aa5, NULL, 0, 0, 0 },
+	{ "mmDP_STEER_FIFO", REG_MMIO, 0x4aa5, &mmDP_STEER_FIFO[0], sizeof(mmDP_STEER_FIFO)/sizeof(mmDP_STEER_FIFO[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_MISC", REG_MMIO, 0x4aa6, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_MISC", REG_MMIO, 0x4aa6, &mmDP_MSA_MISC[0], sizeof(mmDP_MSA_MISC)/sizeof(mmDP_MSA_MISC[0]), 0, 0 },
+	{ "mmDP0_DP_VID_TIMING", REG_MMIO, 0x4aa8, NULL, 0, 0, 0 },
+	{ "mmDP_VID_TIMING", REG_MMIO, 0x4aa8, &mmDP_VID_TIMING[0], sizeof(mmDP_VID_TIMING)/sizeof(mmDP_VID_TIMING[0]), 0, 0 },
+	{ "mmDP0_DP_VID_N", REG_MMIO, 0x4aa9, NULL, 0, 0, 0 },
+	{ "mmDP_VID_N", REG_MMIO, 0x4aa9, &mmDP_VID_N[0], sizeof(mmDP_VID_N)/sizeof(mmDP_VID_N[0]), 0, 0 },
+	{ "mmDP0_DP_VID_M", REG_MMIO, 0x4aaa, NULL, 0, 0, 0 },
+	{ "mmDP_VID_M", REG_MMIO, 0x4aaa, &mmDP_VID_M[0], sizeof(mmDP_VID_M)/sizeof(mmDP_VID_M[0]), 0, 0 },
+	{ "mmDP0_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4aab, NULL, 0, 0, 0 },
+	{ "mmDP_LINK_FRAMING_CNTL", REG_MMIO, 0x4aab, &mmDP_LINK_FRAMING_CNTL[0], sizeof(mmDP_LINK_FRAMING_CNTL)/sizeof(mmDP_LINK_FRAMING_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4aac, NULL, 0, 0, 0 },
+	{ "mmDP_HBR2_EYE_PATTERN", REG_MMIO, 0x4aac, &mmDP_HBR2_EYE_PATTERN[0], sizeof(mmDP_HBR2_EYE_PATTERN)/sizeof(mmDP_HBR2_EYE_PATTERN[0]), 0, 0 },
+	{ "mmDP0_DP_VID_MSA_VBID", REG_MMIO, 0x4aad, NULL, 0, 0, 0 },
+	{ "mmDP_VID_MSA_VBID", REG_MMIO, 0x4aad, &mmDP_VID_MSA_VBID[0], sizeof(mmDP_VID_MSA_VBID)/sizeof(mmDP_VID_MSA_VBID[0]), 0, 0 },
+	{ "mmDP0_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4aae, NULL, 0, 0, 0 },
+	{ "mmDP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4aae, &mmDP_VID_INTERRUPT_CNTL[0], sizeof(mmDP_VID_INTERRUPT_CNTL)/sizeof(mmDP_VID_INTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CNTL", REG_MMIO, 0x4aaf, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CNTL", REG_MMIO, 0x4aaf, &mmDP_DPHY_CNTL[0], sizeof(mmDP_DPHY_CNTL)/sizeof(mmDP_DPHY_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4ab0, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4ab0, &mmDP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM0", REG_MMIO, 0x4ab1, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM0", REG_MMIO, 0x4ab1, &mmDP_DPHY_SYM0[0], sizeof(mmDP_DPHY_SYM0)/sizeof(mmDP_DPHY_SYM0[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM1", REG_MMIO, 0x4ab2, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM1", REG_MMIO, 0x4ab2, &mmDP_DPHY_SYM1[0], sizeof(mmDP_DPHY_SYM1)/sizeof(mmDP_DPHY_SYM1[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM2", REG_MMIO, 0x4ab3, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM2", REG_MMIO, 0x4ab3, &mmDP_DPHY_SYM2[0], sizeof(mmDP_DPHY_SYM2)/sizeof(mmDP_DPHY_SYM2[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4ab4, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_8B10B_CNTL", REG_MMIO, 0x4ab4, &mmDP_DPHY_8B10B_CNTL[0], sizeof(mmDP_DPHY_8B10B_CNTL)/sizeof(mmDP_DPHY_8B10B_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4ab5, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_PRBS_CNTL", REG_MMIO, 0x4ab5, &mmDP_DPHY_PRBS_CNTL[0], sizeof(mmDP_DPHY_PRBS_CNTL)/sizeof(mmDP_DPHY_PRBS_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4ab6, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4ab6, &mmDP_DPHY_SCRAM_CNTL[0], sizeof(mmDP_DPHY_SCRAM_CNTL)/sizeof(mmDP_DPHY_SCRAM_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_EN", REG_MMIO, 0x4ab7, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_EN", REG_MMIO, 0x4ab7, &mmDP_DPHY_CRC_EN[0], sizeof(mmDP_DPHY_CRC_EN)/sizeof(mmDP_DPHY_CRC_EN[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4ab8, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_CNTL", REG_MMIO, 0x4ab8, &mmDP_DPHY_CRC_CNTL[0], sizeof(mmDP_DPHY_CRC_CNTL)/sizeof(mmDP_DPHY_CRC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4ab9, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_RESULT", REG_MMIO, 0x4ab9, &mmDP_DPHY_CRC_RESULT[0], sizeof(mmDP_DPHY_CRC_RESULT)/sizeof(mmDP_DPHY_CRC_RESULT[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4aba, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4aba, &mmDP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP_DPHY_CRC_MST_CNTL)/sizeof(mmDP_DPHY_CRC_MST_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4abb, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4abb, &mmDP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP_DPHY_CRC_MST_STATUS)/sizeof(mmDP_DPHY_CRC_MST_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4abc, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_FAST_TRAINING", REG_MMIO, 0x4abc, &mmDP_DPHY_FAST_TRAINING[0], sizeof(mmDP_DPHY_FAST_TRAINING)/sizeof(mmDP_DPHY_FAST_TRAINING[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4abd, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4abd, &mmDP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4abe, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4abe, &mmDP_MSA_V_TIMING_OVERRIDE1[0], sizeof(mmDP_MSA_V_TIMING_OVERRIDE1)/sizeof(mmDP_MSA_V_TIMING_OVERRIDE1[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4abf, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4abf, &mmDP_MSA_V_TIMING_OVERRIDE2[0], sizeof(mmDP_MSA_V_TIMING_OVERRIDE2)/sizeof(mmDP_MSA_V_TIMING_OVERRIDE2[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL", REG_MMIO, 0x4ac3, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_CNTL", REG_MMIO, 0x4ac3, &mmDP_SEC_CNTL[0], sizeof(mmDP_SEC_CNTL)/sizeof(mmDP_SEC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL1", REG_MMIO, 0x4ac4, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_CNTL1", REG_MMIO, 0x4ac4, &mmDP_SEC_CNTL1[0], sizeof(mmDP_SEC_CNTL1)/sizeof(mmDP_SEC_CNTL1[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING1", REG_MMIO, 0x4ac5, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING1", REG_MMIO, 0x4ac5, &mmDP_SEC_FRAMING1[0], sizeof(mmDP_SEC_FRAMING1)/sizeof(mmDP_SEC_FRAMING1[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING2", REG_MMIO, 0x4ac6, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING2", REG_MMIO, 0x4ac6, &mmDP_SEC_FRAMING2[0], sizeof(mmDP_SEC_FRAMING2)/sizeof(mmDP_SEC_FRAMING2[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING3", REG_MMIO, 0x4ac7, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING3", REG_MMIO, 0x4ac7, &mmDP_SEC_FRAMING3[0], sizeof(mmDP_SEC_FRAMING3)/sizeof(mmDP_SEC_FRAMING3[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING4", REG_MMIO, 0x4ac8, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING4", REG_MMIO, 0x4ac8, &mmDP_SEC_FRAMING4[0], sizeof(mmDP_SEC_FRAMING4)/sizeof(mmDP_SEC_FRAMING4[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N", REG_MMIO, 0x4ac9, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_N", REG_MMIO, 0x4ac9, &mmDP_SEC_AUD_N[0], sizeof(mmDP_SEC_AUD_N)/sizeof(mmDP_SEC_AUD_N[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4aca, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_N_READBACK", REG_MMIO, 0x4aca, &mmDP_SEC_AUD_N_READBACK[0], sizeof(mmDP_SEC_AUD_N_READBACK)/sizeof(mmDP_SEC_AUD_N_READBACK[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M", REG_MMIO, 0x4acb, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_M", REG_MMIO, 0x4acb, &mmDP_SEC_AUD_M[0], sizeof(mmDP_SEC_AUD_M)/sizeof(mmDP_SEC_AUD_M[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4acc, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_M_READBACK", REG_MMIO, 0x4acc, &mmDP_SEC_AUD_M_READBACK[0], sizeof(mmDP_SEC_AUD_M_READBACK)/sizeof(mmDP_SEC_AUD_M_READBACK[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_TIMESTAMP", REG_MMIO, 0x4acd, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_TIMESTAMP", REG_MMIO, 0x4acd, &mmDP_SEC_TIMESTAMP[0], sizeof(mmDP_SEC_TIMESTAMP)/sizeof(mmDP_SEC_TIMESTAMP[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4ace, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_PACKET_CNTL", REG_MMIO, 0x4ace, &mmDP_SEC_PACKET_CNTL[0], sizeof(mmDP_SEC_PACKET_CNTL)/sizeof(mmDP_SEC_PACKET_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_CNTL", REG_MMIO, 0x4acf, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_RATE_CNTL", REG_MMIO, 0x4acf, &mmDP_MSE_RATE_CNTL[0], sizeof(mmDP_MSE_RATE_CNTL)/sizeof(mmDP_MSE_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4ad1, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_RATE_UPDATE", REG_MMIO, 0x4ad1, &mmDP_MSE_RATE_UPDATE[0], sizeof(mmDP_MSE_RATE_UPDATE)/sizeof(mmDP_MSE_RATE_UPDATE[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT0", REG_MMIO, 0x4ad2, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT0", REG_MMIO, 0x4ad2, &mmDP_MSE_SAT0[0], sizeof(mmDP_MSE_SAT0)/sizeof(mmDP_MSE_SAT0[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT1", REG_MMIO, 0x4ad3, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT1", REG_MMIO, 0x4ad3, &mmDP_MSE_SAT1[0], sizeof(mmDP_MSE_SAT1)/sizeof(mmDP_MSE_SAT1[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT2", REG_MMIO, 0x4ad4, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT2", REG_MMIO, 0x4ad4, &mmDP_MSE_SAT2[0], sizeof(mmDP_MSE_SAT2)/sizeof(mmDP_MSE_SAT2[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4ad5, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT_UPDATE", REG_MMIO, 0x4ad5, &mmDP_MSE_SAT_UPDATE[0], sizeof(mmDP_MSE_SAT_UPDATE)/sizeof(mmDP_MSE_SAT_UPDATE[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_LINK_TIMING", REG_MMIO, 0x4ad6, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_LINK_TIMING", REG_MMIO, 0x4ad6, &mmDP_MSE_LINK_TIMING[0], sizeof(mmDP_MSE_LINK_TIMING)/sizeof(mmDP_MSE_LINK_TIMING[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_MISC_CNTL", REG_MMIO, 0x4ad7, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_MISC_CNTL", REG_MMIO, 0x4ad7, &mmDP_MSE_MISC_CNTL[0], sizeof(mmDP_MSE_MISC_CNTL)/sizeof(mmDP_MSE_MISC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ad8, NULL, 0, 0, 0 },
+	{ "mmDP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ad8, &mmDP_TEST_DEBUG_INDEX[0], sizeof(mmDP_TEST_DEBUG_INDEX)/sizeof(mmDP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4ad9, NULL, 0, 0, 0 },
+	{ "mmDP_TEST_DEBUG_DATA", REG_MMIO, 0x4ad9, &mmDP_TEST_DEBUG_DATA[0], sizeof(mmDP_TEST_DEBUG_DATA)/sizeof(mmDP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP0_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4ada, NULL, 0, 0, 0 },
+	{ "mmDP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4ada, &mmDP_FE_TEST_DEBUG_INDEX[0], sizeof(mmDP_FE_TEST_DEBUG_INDEX)/sizeof(mmDP_FE_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP0_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4adb, NULL, 0, 0, 0 },
+	{ "mmDP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4adb, &mmDP_FE_TEST_DEBUG_DATA[0], sizeof(mmDP_FE_TEST_DEBUG_DATA)/sizeof(mmDP_FE_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4adc, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4adc, &mmDP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4add, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4add, &mmDP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmDIG1_DIG_FE_CNTL", REG_MMIO, 0x4b00, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4b01, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4b02, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_CLOCK_PATTERN", REG_MMIO, 0x4b03, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_PATTERN", REG_MMIO, 0x4b04, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4b05, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FIFO_STATUS", REG_MMIO, 0x4b06, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4b07, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4b08, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_CONTROL", REG_MMIO, 0x4b09, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_STATUS", REG_MMIO, 0x4b0a, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4b0b, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4b0c, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4b0d, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4b0e, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4b0f, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4b10, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4b11, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GC", REG_MMIO, 0x4b13, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4b14, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_0", REG_MMIO, 0x4b15, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_1", REG_MMIO, 0x4b16, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_2", REG_MMIO, 0x4b17, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_3", REG_MMIO, 0x4b18, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_4", REG_MMIO, 0x4b19, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_0", REG_MMIO, 0x4b1a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_1", REG_MMIO, 0x4b1b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_2", REG_MMIO, 0x4b1c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_3", REG_MMIO, 0x4b1d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO0", REG_MMIO, 0x4b1e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO1", REG_MMIO, 0x4b1f, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO2", REG_MMIO, 0x4b20, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO3", REG_MMIO, 0x4b21, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO0", REG_MMIO, 0x4b22, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO1", REG_MMIO, 0x4b23, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_HDR", REG_MMIO, 0x4b24, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_0", REG_MMIO, 0x4b25, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_1", REG_MMIO, 0x4b26, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_2", REG_MMIO, 0x4b27, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_3", REG_MMIO, 0x4b28, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_4", REG_MMIO, 0x4b29, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_5", REG_MMIO, 0x4b2a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_6", REG_MMIO, 0x4b2b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_7", REG_MMIO, 0x4b2c, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4b2d, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_0", REG_MMIO, 0x4b2e, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_1", REG_MMIO, 0x4b2f, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_0", REG_MMIO, 0x4b30, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_1", REG_MMIO, 0x4b31, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_0", REG_MMIO, 0x4b32, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_1", REG_MMIO, 0x4b33, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_0", REG_MMIO, 0x4b34, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_1", REG_MMIO, 0x4b35, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO0", REG_MMIO, 0x4b36, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO1", REG_MMIO, 0x4b37, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_0", REG_MMIO, 0x4b38, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_1", REG_MMIO, 0x4b39, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4b3a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4b3b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4b3c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4b3d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4b3e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_2", REG_MMIO, 0x4b3f, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4b40, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_STATUS", REG_MMIO, 0x4b41, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4b42, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4b43, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4b44, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4b45, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4b46, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_CNTL", REG_MMIO, 0x4b47, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_EN_CNTL", REG_MMIO, 0x4b48, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CNTL", REG_MMIO, 0x4b6b, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL_CHAR", REG_MMIO, 0x4b6c, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4b6d, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4b6e, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4b6f, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4b70, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DEBUG", REG_MMIO, 0x4b71, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL_BITS", REG_MMIO, 0x4b72, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4b73, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4b75, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4b76, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_VERSION", REG_MMIO, 0x4b78, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_LANE_ENABLE", REG_MMIO, 0x4b79, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4b7a, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4b7b, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4b7c, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4b7d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_CNTL", REG_MMIO, 0x4b7e, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_CNTL", REG_MMIO, 0x4ba0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_PIXEL_FORMAT", REG_MMIO, 0x4ba1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ba2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_CONFIG", REG_MMIO, 0x4ba3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ba4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_STEER_FIFO", REG_MMIO, 0x4ba5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_MISC", REG_MMIO, 0x4ba6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_TIMING", REG_MMIO, 0x4ba8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_N", REG_MMIO, 0x4ba9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_M", REG_MMIO, 0x4baa, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4bab, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4bac, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_MSA_VBID", REG_MMIO, 0x4bad, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4bae, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CNTL", REG_MMIO, 0x4baf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4bb0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM0", REG_MMIO, 0x4bb1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM1", REG_MMIO, 0x4bb2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM2", REG_MMIO, 0x4bb3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4bb4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4bb5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4bb6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_EN", REG_MMIO, 0x4bb7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4bb8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4bb9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4bba, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4bbb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4bbc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4bbd, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4bbe, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4bbf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL", REG_MMIO, 0x4bc3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL1", REG_MMIO, 0x4bc4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING1", REG_MMIO, 0x4bc5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING2", REG_MMIO, 0x4bc6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING3", REG_MMIO, 0x4bc7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING4", REG_MMIO, 0x4bc8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N", REG_MMIO, 0x4bc9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4bca, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M", REG_MMIO, 0x4bcb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4bcc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_TIMESTAMP", REG_MMIO, 0x4bcd, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4bce, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_CNTL", REG_MMIO, 0x4bcf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4bd1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT0", REG_MMIO, 0x4bd2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT1", REG_MMIO, 0x4bd3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT2", REG_MMIO, 0x4bd4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4bd5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_LINK_TIMING", REG_MMIO, 0x4bd6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_MISC_CNTL", REG_MMIO, 0x4bd7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4bd8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4bd9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4bda, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4bdb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4bdc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4bdd, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_CNTL", REG_MMIO, 0x4c00, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4c01, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4c02, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_CLOCK_PATTERN", REG_MMIO, 0x4c03, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_PATTERN", REG_MMIO, 0x4c04, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4c05, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FIFO_STATUS", REG_MMIO, 0x4c06, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4c07, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4c08, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_CONTROL", REG_MMIO, 0x4c09, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_STATUS", REG_MMIO, 0x4c0a, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4c0b, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4c0c, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4c0d, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4c0e, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4c0f, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4c10, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4c11, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GC", REG_MMIO, 0x4c13, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4c14, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_0", REG_MMIO, 0x4c15, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_1", REG_MMIO, 0x4c16, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_2", REG_MMIO, 0x4c17, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_3", REG_MMIO, 0x4c18, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_4", REG_MMIO, 0x4c19, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_0", REG_MMIO, 0x4c1a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_1", REG_MMIO, 0x4c1b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_2", REG_MMIO, 0x4c1c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_3", REG_MMIO, 0x4c1d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO0", REG_MMIO, 0x4c1e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO1", REG_MMIO, 0x4c1f, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO2", REG_MMIO, 0x4c20, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO3", REG_MMIO, 0x4c21, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO0", REG_MMIO, 0x4c22, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO1", REG_MMIO, 0x4c23, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_HDR", REG_MMIO, 0x4c24, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_0", REG_MMIO, 0x4c25, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_1", REG_MMIO, 0x4c26, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_2", REG_MMIO, 0x4c27, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_3", REG_MMIO, 0x4c28, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_4", REG_MMIO, 0x4c29, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_5", REG_MMIO, 0x4c2a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_6", REG_MMIO, 0x4c2b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_7", REG_MMIO, 0x4c2c, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4c2d, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_0", REG_MMIO, 0x4c2e, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_1", REG_MMIO, 0x4c2f, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_0", REG_MMIO, 0x4c30, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_1", REG_MMIO, 0x4c31, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_0", REG_MMIO, 0x4c32, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_1", REG_MMIO, 0x4c33, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_0", REG_MMIO, 0x4c34, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_1", REG_MMIO, 0x4c35, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO0", REG_MMIO, 0x4c36, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO1", REG_MMIO, 0x4c37, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_0", REG_MMIO, 0x4c38, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_1", REG_MMIO, 0x4c39, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4c3a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4c3b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4c3c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4c3d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4c3e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_2", REG_MMIO, 0x4c3f, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4c40, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_STATUS", REG_MMIO, 0x4c41, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4c42, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4c43, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4c44, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4c45, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4c46, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_CNTL", REG_MMIO, 0x4c47, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_EN_CNTL", REG_MMIO, 0x4c48, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CNTL", REG_MMIO, 0x4c6b, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL_CHAR", REG_MMIO, 0x4c6c, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4c6d, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4c6e, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4c6f, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4c70, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DEBUG", REG_MMIO, 0x4c71, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL_BITS", REG_MMIO, 0x4c72, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4c73, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4c75, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4c76, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_VERSION", REG_MMIO, 0x4c78, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_LANE_ENABLE", REG_MMIO, 0x4c79, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4c7a, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4c7b, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4c7c, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4c7d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_CNTL", REG_MMIO, 0x4c7e, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_CNTL", REG_MMIO, 0x4ca0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_PIXEL_FORMAT", REG_MMIO, 0x4ca1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ca2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_CONFIG", REG_MMIO, 0x4ca3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ca4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_STEER_FIFO", REG_MMIO, 0x4ca5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_MISC", REG_MMIO, 0x4ca6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_TIMING", REG_MMIO, 0x4ca8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_N", REG_MMIO, 0x4ca9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_M", REG_MMIO, 0x4caa, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4cab, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4cac, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_MSA_VBID", REG_MMIO, 0x4cad, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4cae, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CNTL", REG_MMIO, 0x4caf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4cb0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM0", REG_MMIO, 0x4cb1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM1", REG_MMIO, 0x4cb2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM2", REG_MMIO, 0x4cb3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4cb4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4cb5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4cb6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_EN", REG_MMIO, 0x4cb7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4cb8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4cb9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4cba, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4cbb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4cbc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4cbd, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4cbe, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4cbf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL", REG_MMIO, 0x4cc3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL1", REG_MMIO, 0x4cc4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING1", REG_MMIO, 0x4cc5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING2", REG_MMIO, 0x4cc6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING3", REG_MMIO, 0x4cc7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING4", REG_MMIO, 0x4cc8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N", REG_MMIO, 0x4cc9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4cca, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M", REG_MMIO, 0x4ccb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4ccc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_TIMESTAMP", REG_MMIO, 0x4ccd, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4cce, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_CNTL", REG_MMIO, 0x4ccf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4cd1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT0", REG_MMIO, 0x4cd2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT1", REG_MMIO, 0x4cd3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT2", REG_MMIO, 0x4cd4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4cd5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_LINK_TIMING", REG_MMIO, 0x4cd6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_MISC_CNTL", REG_MMIO, 0x4cd7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4cd8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4cd9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4cda, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4cdb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4cdc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4cdd, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_CNTL", REG_MMIO, 0x4d00, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4d01, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4d02, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_CLOCK_PATTERN", REG_MMIO, 0x4d03, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_PATTERN", REG_MMIO, 0x4d04, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4d05, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FIFO_STATUS", REG_MMIO, 0x4d06, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4d07, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4d08, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_CONTROL", REG_MMIO, 0x4d09, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_STATUS", REG_MMIO, 0x4d0a, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4d0b, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4d0c, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4d0d, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4d0e, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4d0f, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4d10, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4d11, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GC", REG_MMIO, 0x4d13, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4d14, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_0", REG_MMIO, 0x4d15, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_1", REG_MMIO, 0x4d16, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_2", REG_MMIO, 0x4d17, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_3", REG_MMIO, 0x4d18, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_4", REG_MMIO, 0x4d19, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_0", REG_MMIO, 0x4d1a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_1", REG_MMIO, 0x4d1b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_2", REG_MMIO, 0x4d1c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_3", REG_MMIO, 0x4d1d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO0", REG_MMIO, 0x4d1e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO1", REG_MMIO, 0x4d1f, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO2", REG_MMIO, 0x4d20, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO3", REG_MMIO, 0x4d21, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO0", REG_MMIO, 0x4d22, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO1", REG_MMIO, 0x4d23, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_HDR", REG_MMIO, 0x4d24, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_0", REG_MMIO, 0x4d25, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_1", REG_MMIO, 0x4d26, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_2", REG_MMIO, 0x4d27, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_3", REG_MMIO, 0x4d28, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_4", REG_MMIO, 0x4d29, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_5", REG_MMIO, 0x4d2a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_6", REG_MMIO, 0x4d2b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_7", REG_MMIO, 0x4d2c, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4d2d, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_0", REG_MMIO, 0x4d2e, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_1", REG_MMIO, 0x4d2f, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_0", REG_MMIO, 0x4d30, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_1", REG_MMIO, 0x4d31, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_0", REG_MMIO, 0x4d32, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_1", REG_MMIO, 0x4d33, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_0", REG_MMIO, 0x4d34, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_1", REG_MMIO, 0x4d35, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO0", REG_MMIO, 0x4d36, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO1", REG_MMIO, 0x4d37, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_0", REG_MMIO, 0x4d38, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_1", REG_MMIO, 0x4d39, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4d3a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4d3b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4d3c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4d3d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4d3e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_2", REG_MMIO, 0x4d3f, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4d40, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_STATUS", REG_MMIO, 0x4d41, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4d42, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4d43, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4d44, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4d45, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4d46, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_CNTL", REG_MMIO, 0x4d47, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_EN_CNTL", REG_MMIO, 0x4d48, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CNTL", REG_MMIO, 0x4d6b, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL_CHAR", REG_MMIO, 0x4d6c, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4d6d, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4d6e, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4d6f, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4d70, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DEBUG", REG_MMIO, 0x4d71, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL_BITS", REG_MMIO, 0x4d72, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4d73, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4d75, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4d76, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_VERSION", REG_MMIO, 0x4d78, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_LANE_ENABLE", REG_MMIO, 0x4d79, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4d7a, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4d7b, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4d7c, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4d7d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_CNTL", REG_MMIO, 0x4d7e, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_CNTL", REG_MMIO, 0x4da0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_PIXEL_FORMAT", REG_MMIO, 0x4da1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_COLORIMETRY", REG_MMIO, 0x4da2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_CONFIG", REG_MMIO, 0x4da3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_STREAM_CNTL", REG_MMIO, 0x4da4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_STEER_FIFO", REG_MMIO, 0x4da5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_MISC", REG_MMIO, 0x4da6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_TIMING", REG_MMIO, 0x4da8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_N", REG_MMIO, 0x4da9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_M", REG_MMIO, 0x4daa, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4dab, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4dac, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_MSA_VBID", REG_MMIO, 0x4dad, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4dae, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CNTL", REG_MMIO, 0x4daf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4db0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM0", REG_MMIO, 0x4db1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM1", REG_MMIO, 0x4db2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM2", REG_MMIO, 0x4db3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4db4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4db5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4db6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_EN", REG_MMIO, 0x4db7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4db8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4db9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4dba, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4dbb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4dbc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4dbd, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4dbe, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4dbf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL", REG_MMIO, 0x4dc3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL1", REG_MMIO, 0x4dc4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING1", REG_MMIO, 0x4dc5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING2", REG_MMIO, 0x4dc6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING3", REG_MMIO, 0x4dc7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING4", REG_MMIO, 0x4dc8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N", REG_MMIO, 0x4dc9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4dca, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M", REG_MMIO, 0x4dcb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4dcc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_TIMESTAMP", REG_MMIO, 0x4dcd, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4dce, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_CNTL", REG_MMIO, 0x4dcf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4dd1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT0", REG_MMIO, 0x4dd2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT1", REG_MMIO, 0x4dd3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT2", REG_MMIO, 0x4dd4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4dd5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_LINK_TIMING", REG_MMIO, 0x4dd6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_MISC_CNTL", REG_MMIO, 0x4dd7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4dd8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4dd9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4dda, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4ddb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4ddc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4ddd, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_CNTL", REG_MMIO, 0x4e00, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4e01, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4e02, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_CLOCK_PATTERN", REG_MMIO, 0x4e03, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_PATTERN", REG_MMIO, 0x4e04, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4e05, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FIFO_STATUS", REG_MMIO, 0x4e06, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4e07, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4e08, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_CONTROL", REG_MMIO, 0x4e09, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_STATUS", REG_MMIO, 0x4e0a, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4e0b, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4e0c, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4e0d, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4e0e, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4e0f, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4e10, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4e11, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GC", REG_MMIO, 0x4e13, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4e14, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_0", REG_MMIO, 0x4e15, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_1", REG_MMIO, 0x4e16, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_2", REG_MMIO, 0x4e17, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_3", REG_MMIO, 0x4e18, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_4", REG_MMIO, 0x4e19, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_0", REG_MMIO, 0x4e1a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_1", REG_MMIO, 0x4e1b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_2", REG_MMIO, 0x4e1c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_3", REG_MMIO, 0x4e1d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO0", REG_MMIO, 0x4e1e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO1", REG_MMIO, 0x4e1f, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO2", REG_MMIO, 0x4e20, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO3", REG_MMIO, 0x4e21, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO0", REG_MMIO, 0x4e22, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO1", REG_MMIO, 0x4e23, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_HDR", REG_MMIO, 0x4e24, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_0", REG_MMIO, 0x4e25, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_1", REG_MMIO, 0x4e26, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_2", REG_MMIO, 0x4e27, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_3", REG_MMIO, 0x4e28, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_4", REG_MMIO, 0x4e29, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_5", REG_MMIO, 0x4e2a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_6", REG_MMIO, 0x4e2b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_7", REG_MMIO, 0x4e2c, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4e2d, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_0", REG_MMIO, 0x4e2e, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_1", REG_MMIO, 0x4e2f, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_0", REG_MMIO, 0x4e30, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_1", REG_MMIO, 0x4e31, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_0", REG_MMIO, 0x4e32, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_1", REG_MMIO, 0x4e33, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_0", REG_MMIO, 0x4e34, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_1", REG_MMIO, 0x4e35, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO0", REG_MMIO, 0x4e36, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO1", REG_MMIO, 0x4e37, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_0", REG_MMIO, 0x4e38, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_1", REG_MMIO, 0x4e39, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4e3a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4e3b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4e3c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4e3d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4e3e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_2", REG_MMIO, 0x4e3f, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4e40, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_STATUS", REG_MMIO, 0x4e41, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4e42, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4e43, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4e44, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4e45, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4e46, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_CNTL", REG_MMIO, 0x4e47, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_EN_CNTL", REG_MMIO, 0x4e48, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CNTL", REG_MMIO, 0x4e6b, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL_CHAR", REG_MMIO, 0x4e6c, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4e6d, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4e6e, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4e6f, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4e70, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DEBUG", REG_MMIO, 0x4e71, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL_BITS", REG_MMIO, 0x4e72, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4e73, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4e75, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4e76, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_VERSION", REG_MMIO, 0x4e78, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_LANE_ENABLE", REG_MMIO, 0x4e79, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4e7a, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4e7b, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4e7c, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4e7d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_CNTL", REG_MMIO, 0x4e7e, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_CNTL", REG_MMIO, 0x4ea0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_PIXEL_FORMAT", REG_MMIO, 0x4ea1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ea2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_CONFIG", REG_MMIO, 0x4ea3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ea4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_STEER_FIFO", REG_MMIO, 0x4ea5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_MISC", REG_MMIO, 0x4ea6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_TIMING", REG_MMIO, 0x4ea8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_N", REG_MMIO, 0x4ea9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_M", REG_MMIO, 0x4eaa, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4eab, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4eac, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_MSA_VBID", REG_MMIO, 0x4ead, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4eae, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CNTL", REG_MMIO, 0x4eaf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4eb0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM0", REG_MMIO, 0x4eb1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM1", REG_MMIO, 0x4eb2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM2", REG_MMIO, 0x4eb3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4eb4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4eb5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4eb6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_EN", REG_MMIO, 0x4eb7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4eb8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4eb9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4eba, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4ebb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4ebc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4ebd, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4ebe, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4ebf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL", REG_MMIO, 0x4ec3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL1", REG_MMIO, 0x4ec4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING1", REG_MMIO, 0x4ec5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING2", REG_MMIO, 0x4ec6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING3", REG_MMIO, 0x4ec7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING4", REG_MMIO, 0x4ec8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N", REG_MMIO, 0x4ec9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4eca, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M", REG_MMIO, 0x4ecb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4ecc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_TIMESTAMP", REG_MMIO, 0x4ecd, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4ece, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_CNTL", REG_MMIO, 0x4ecf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4ed1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT0", REG_MMIO, 0x4ed2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT1", REG_MMIO, 0x4ed3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT2", REG_MMIO, 0x4ed4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4ed5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_LINK_TIMING", REG_MMIO, 0x4ed6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_MISC_CNTL", REG_MMIO, 0x4ed7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ed8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4ed9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4eda, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4edb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4edc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4edd, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_CNTL", REG_MMIO, 0x4f00, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4f01, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4f02, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_CLOCK_PATTERN", REG_MMIO, 0x4f03, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_PATTERN", REG_MMIO, 0x4f04, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4f05, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FIFO_STATUS", REG_MMIO, 0x4f06, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4f07, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4f08, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_CONTROL", REG_MMIO, 0x4f09, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_STATUS", REG_MMIO, 0x4f0a, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4f0b, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4f0c, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4f0d, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4f0e, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4f0f, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4f10, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4f11, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GC", REG_MMIO, 0x4f13, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4f14, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_0", REG_MMIO, 0x4f15, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_1", REG_MMIO, 0x4f16, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_2", REG_MMIO, 0x4f17, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_3", REG_MMIO, 0x4f18, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_4", REG_MMIO, 0x4f19, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_0", REG_MMIO, 0x4f1a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_1", REG_MMIO, 0x4f1b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_2", REG_MMIO, 0x4f1c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_3", REG_MMIO, 0x4f1d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO0", REG_MMIO, 0x4f1e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO1", REG_MMIO, 0x4f1f, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO2", REG_MMIO, 0x4f20, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO3", REG_MMIO, 0x4f21, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO0", REG_MMIO, 0x4f22, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO1", REG_MMIO, 0x4f23, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_HDR", REG_MMIO, 0x4f24, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_0", REG_MMIO, 0x4f25, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_1", REG_MMIO, 0x4f26, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_2", REG_MMIO, 0x4f27, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_3", REG_MMIO, 0x4f28, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_4", REG_MMIO, 0x4f29, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_5", REG_MMIO, 0x4f2a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_6", REG_MMIO, 0x4f2b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_7", REG_MMIO, 0x4f2c, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4f2d, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_0", REG_MMIO, 0x4f2e, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_1", REG_MMIO, 0x4f2f, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_0", REG_MMIO, 0x4f30, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_1", REG_MMIO, 0x4f31, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_0", REG_MMIO, 0x4f32, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_1", REG_MMIO, 0x4f33, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_0", REG_MMIO, 0x4f34, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_1", REG_MMIO, 0x4f35, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO0", REG_MMIO, 0x4f36, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO1", REG_MMIO, 0x4f37, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_0", REG_MMIO, 0x4f38, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_1", REG_MMIO, 0x4f39, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4f3a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4f3b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4f3c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4f3d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4f3e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_2", REG_MMIO, 0x4f3f, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4f40, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_STATUS", REG_MMIO, 0x4f41, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4f42, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4f43, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4f44, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4f45, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4f46, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_CNTL", REG_MMIO, 0x4f47, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_EN_CNTL", REG_MMIO, 0x4f48, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CNTL", REG_MMIO, 0x4f6b, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL_CHAR", REG_MMIO, 0x4f6c, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4f6d, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4f6e, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4f6f, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4f70, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DEBUG", REG_MMIO, 0x4f71, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL_BITS", REG_MMIO, 0x4f72, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4f73, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4f75, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4f76, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_VERSION", REG_MMIO, 0x4f78, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_LANE_ENABLE", REG_MMIO, 0x4f79, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4f7a, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4f7b, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4f7c, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4f7d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_CNTL", REG_MMIO, 0x4f7e, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_CNTL", REG_MMIO, 0x4fa0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_PIXEL_FORMAT", REG_MMIO, 0x4fa1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_COLORIMETRY", REG_MMIO, 0x4fa2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_CONFIG", REG_MMIO, 0x4fa3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_STREAM_CNTL", REG_MMIO, 0x4fa4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_STEER_FIFO", REG_MMIO, 0x4fa5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_MISC", REG_MMIO, 0x4fa6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_TIMING", REG_MMIO, 0x4fa8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_N", REG_MMIO, 0x4fa9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_M", REG_MMIO, 0x4faa, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4fab, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4fac, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_MSA_VBID", REG_MMIO, 0x4fad, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4fae, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CNTL", REG_MMIO, 0x4faf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4fb0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM0", REG_MMIO, 0x4fb1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM1", REG_MMIO, 0x4fb2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM2", REG_MMIO, 0x4fb3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4fb4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4fb5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4fb6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_EN", REG_MMIO, 0x4fb7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4fb8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4fb9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4fba, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4fbb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4fbc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4fbd, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4fbe, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4fbf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL", REG_MMIO, 0x4fc3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL1", REG_MMIO, 0x4fc4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING1", REG_MMIO, 0x4fc5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING2", REG_MMIO, 0x4fc6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING3", REG_MMIO, 0x4fc7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING4", REG_MMIO, 0x4fc8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N", REG_MMIO, 0x4fc9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4fca, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M", REG_MMIO, 0x4fcb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4fcc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_TIMESTAMP", REG_MMIO, 0x4fcd, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4fce, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_CNTL", REG_MMIO, 0x4fcf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4fd1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT0", REG_MMIO, 0x4fd2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT1", REG_MMIO, 0x4fd3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT2", REG_MMIO, 0x4fd4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4fd5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_LINK_TIMING", REG_MMIO, 0x4fd6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_MISC_CNTL", REG_MMIO, 0x4fd7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4fd8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4fd9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4fda, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4fdb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4fdc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4fdd, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x5, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x5, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL5", REG_SMC, 0x5, &ixAZALIA_INPUT_CRC0_CHANNEL5[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL5)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL5[0]), 0, 0 },
+	{ "ixDPGV0_DEBUG04_DMIFARB", REG_SMC, 0x5, NULL, 0, 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL5", REG_SMC, 0x5, &ixAZALIA_CRC0_CHANNEL5[0], sizeof(ixAZALIA_CRC0_CHANNEL5)/sizeof(ixAZALIA_CRC0_CHANNEL5[0]), 0, 0 },
+	{ "ixAZALIA_STREAM_DEBUG", REG_SMC, 0x5, &ixAZALIA_STREAM_DEBUG[0], sizeof(ixAZALIA_STREAM_DEBUG)/sizeof(ixAZALIA_STREAM_DEBUG[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR4", REG_SMC, 0x5, &ixAUDIO_DESCRIPTOR4[0], sizeof(ixAUDIO_DESCRIPTOR4)/sizeof(ixAUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "ixDCIO_DEBUG5", REG_SMC, 0x5, &ixDCIO_DEBUG5[0], sizeof(ixDCIO_DEBUG5)/sizeof(ixDCIO_DEBUG5[0]), 0, 0 },
+	{ "ixATTR05", REG_SMC, 0x5, &ixATTR05[0], sizeof(ixATTR05)/sizeof(ixATTR05[0]), 0, 0 },
+	{ "ixCRT05", REG_SMC, 0x5, &ixCRT05[0], sizeof(ixCRT05)/sizeof(ixCRT05[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x53, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x54, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x54, &ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 },
+	{ "mmDIG6_DIG_FE_CNTL", REG_MMIO, 0x5400, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x5401, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x5402, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_CLOCK_PATTERN", REG_MMIO, 0x5403, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_PATTERN", REG_MMIO, 0x5404, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x5405, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FIFO_STATUS", REG_MMIO, 0x5406, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x5407, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x5408, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_CONTROL", REG_MMIO, 0x5409, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_STATUS", REG_MMIO, 0x540a, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x540b, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x540c, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x540d, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x540e, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x540f, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x5410, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x5411, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GC", REG_MMIO, 0x5413, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x5414, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_0", REG_MMIO, 0x5415, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_1", REG_MMIO, 0x5416, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_2", REG_MMIO, 0x5417, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_3", REG_MMIO, 0x5418, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_4", REG_MMIO, 0x5419, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_0", REG_MMIO, 0x541a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_1", REG_MMIO, 0x541b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_2", REG_MMIO, 0x541c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_3", REG_MMIO, 0x541d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO0", REG_MMIO, 0x541e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO1", REG_MMIO, 0x541f, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO2", REG_MMIO, 0x5420, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO3", REG_MMIO, 0x5421, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_MPEG_INFO0", REG_MMIO, 0x5422, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_MPEG_INFO1", REG_MMIO, 0x5423, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_HDR", REG_MMIO, 0x5424, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_0", REG_MMIO, 0x5425, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_1", REG_MMIO, 0x5426, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_2", REG_MMIO, 0x5427, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_3", REG_MMIO, 0x5428, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_4", REG_MMIO, 0x5429, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_5", REG_MMIO, 0x542a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_6", REG_MMIO, 0x542b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_7", REG_MMIO, 0x542c, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x542d, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_32_0", REG_MMIO, 0x542e, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_32_1", REG_MMIO, 0x542f, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_44_0", REG_MMIO, 0x5430, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_44_1", REG_MMIO, 0x5431, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_48_0", REG_MMIO, 0x5432, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_48_1", REG_MMIO, 0x5433, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_STATUS_0", REG_MMIO, 0x5434, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_STATUS_1", REG_MMIO, 0x5435, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_INFO0", REG_MMIO, 0x5436, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_INFO1", REG_MMIO, 0x5437, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_0", REG_MMIO, 0x5438, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_1", REG_MMIO, 0x5439, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x543a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL0", REG_MMIO, 0x543b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL1", REG_MMIO, 0x543c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL2", REG_MMIO, 0x543d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL3", REG_MMIO, 0x543e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_2", REG_MMIO, 0x543f, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x5440, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_STATUS", REG_MMIO, 0x5441, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x5442, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x5443, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x5444, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x5445, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x5446, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_BE_CNTL", REG_MMIO, 0x5447, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_BE_EN_CNTL", REG_MMIO, 0x5448, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CNTL", REG_MMIO, 0x546b, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CONTROL_CHAR", REG_MMIO, 0x546c, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x546d, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x546e, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x546f, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x5470, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_DEBUG", REG_MMIO, 0x5471, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL_BITS", REG_MMIO, 0x5472, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x5473, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x5475, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x5476, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_VERSION", REG_MMIO, 0x5478, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_LANE_ENABLE", REG_MMIO, 0x5479, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x547a, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x547b, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x547c, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x547d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_CNTL", REG_MMIO, 0x547e, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_LINK_CNTL", REG_MMIO, 0x54a0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_PIXEL_FORMAT", REG_MMIO, 0x54a1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_COLORIMETRY", REG_MMIO, 0x54a2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_CONFIG", REG_MMIO, 0x54a3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_STREAM_CNTL", REG_MMIO, 0x54a4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_STEER_FIFO", REG_MMIO, 0x54a5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_MISC", REG_MMIO, 0x54a6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_TIMING", REG_MMIO, 0x54a8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_N", REG_MMIO, 0x54a9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_M", REG_MMIO, 0x54aa, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x54ab, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x54ac, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_MSA_VBID", REG_MMIO, 0x54ad, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x54ae, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CNTL", REG_MMIO, 0x54af, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x54b0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM0", REG_MMIO, 0x54b1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM1", REG_MMIO, 0x54b2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM2", REG_MMIO, 0x54b3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x54b4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x54b5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x54b6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_EN", REG_MMIO, 0x54b7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_CNTL", REG_MMIO, 0x54b8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_RESULT", REG_MMIO, 0x54b9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x54ba, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x54bb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x54bc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x54bd, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x54be, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x54bf, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_CNTL", REG_MMIO, 0x54c3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_CNTL1", REG_MMIO, 0x54c4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING1", REG_MMIO, 0x54c5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING2", REG_MMIO, 0x54c6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING3", REG_MMIO, 0x54c7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING4", REG_MMIO, 0x54c8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_N", REG_MMIO, 0x54c9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x54ca, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_M", REG_MMIO, 0x54cb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x54cc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_TIMESTAMP", REG_MMIO, 0x54cd, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_PACKET_CNTL", REG_MMIO, 0x54ce, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_RATE_CNTL", REG_MMIO, 0x54cf, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_RATE_UPDATE", REG_MMIO, 0x54d1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT0", REG_MMIO, 0x54d2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT1", REG_MMIO, 0x54d3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT2", REG_MMIO, 0x54d4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT_UPDATE", REG_MMIO, 0x54d5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_LINK_TIMING", REG_MMIO, 0x54d6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_MISC_CNTL", REG_MMIO, 0x54d7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x54d8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_TEST_DEBUG_DATA", REG_MMIO, 0x54d9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x54da, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x54db, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x54dc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x54dd, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x55, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x55, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x56, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x56, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "mmDIG7_DIG_FE_CNTL", REG_MMIO, 0x5600, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x5601, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x5602, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_CLOCK_PATTERN", REG_MMIO, 0x5603, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_TEST_PATTERN", REG_MMIO, 0x5604, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x5605, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_FIFO_STATUS", REG_MMIO, 0x5606, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x5607, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x5608, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_CONTROL", REG_MMIO, 0x5609, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_STATUS", REG_MMIO, 0x560a, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x560b, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x560c, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x560d, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x560e, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x560f, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x5610, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x5611, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_GC", REG_MMIO, 0x5613, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x5614, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_0", REG_MMIO, 0x5615, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_1", REG_MMIO, 0x5616, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_2", REG_MMIO, 0x5617, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_3", REG_MMIO, 0x5618, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_4", REG_MMIO, 0x5619, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC2_0", REG_MMIO, 0x561a, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC2_1", REG_MMIO, 0x561b, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC2_2", REG_MMIO, 0x561c, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC2_3", REG_MMIO, 0x561d, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AVI_INFO0", REG_MMIO, 0x561e, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AVI_INFO1", REG_MMIO, 0x561f, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AVI_INFO2", REG_MMIO, 0x5620, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AVI_INFO3", REG_MMIO, 0x5621, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_MPEG_INFO0", REG_MMIO, 0x5622, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_MPEG_INFO1", REG_MMIO, 0x5623, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_HDR", REG_MMIO, 0x5624, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_0", REG_MMIO, 0x5625, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_1", REG_MMIO, 0x5626, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_2", REG_MMIO, 0x5627, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_3", REG_MMIO, 0x5628, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_4", REG_MMIO, 0x5629, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_5", REG_MMIO, 0x562a, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_6", REG_MMIO, 0x562b, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_7", REG_MMIO, 0x562c, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x562d, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_32_0", REG_MMIO, 0x562e, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_32_1", REG_MMIO, 0x562f, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_44_0", REG_MMIO, 0x5630, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_44_1", REG_MMIO, 0x5631, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_48_0", REG_MMIO, 0x5632, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_48_1", REG_MMIO, 0x5633, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_STATUS_0", REG_MMIO, 0x5634, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_STATUS_1", REG_MMIO, 0x5635, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_INFO0", REG_MMIO, 0x5636, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_INFO1", REG_MMIO, 0x5637, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_60958_0", REG_MMIO, 0x5638, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_60958_1", REG_MMIO, 0x5639, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x563a, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_RAMP_CONTROL0", REG_MMIO, 0x563b, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_RAMP_CONTROL1", REG_MMIO, 0x563c, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_RAMP_CONTROL2", REG_MMIO, 0x563d, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_RAMP_CONTROL3", REG_MMIO, 0x563e, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_60958_2", REG_MMIO, 0x563f, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x5640, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_STATUS", REG_MMIO, 0x5641, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x5642, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x5643, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x5644, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x5645, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x5646, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_BE_CNTL", REG_MMIO, 0x5647, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_BE_EN_CNTL", REG_MMIO, 0x5648, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CNTL", REG_MMIO, 0x566b, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CONTROL_CHAR", REG_MMIO, 0x566c, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x566d, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x566e, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x566f, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x5670, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_DEBUG", REG_MMIO, 0x5671, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CTL_BITS", REG_MMIO, 0x5672, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x5673, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x5675, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x5676, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_VERSION", REG_MMIO, 0x5678, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_LANE_ENABLE", REG_MMIO, 0x5679, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x567a, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x567b, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x567c, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x567d, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_CNTL", REG_MMIO, 0x567e, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_LINK_CNTL", REG_MMIO, 0x56a0, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_PIXEL_FORMAT", REG_MMIO, 0x56a1, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSA_COLORIMETRY", REG_MMIO, 0x56a2, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_CONFIG", REG_MMIO, 0x56a3, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_STREAM_CNTL", REG_MMIO, 0x56a4, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_STEER_FIFO", REG_MMIO, 0x56a5, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSA_MISC", REG_MMIO, 0x56a6, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_TIMING", REG_MMIO, 0x56a8, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_N", REG_MMIO, 0x56a9, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_M", REG_MMIO, 0x56aa, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x56ab, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x56ac, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_MSA_VBID", REG_MMIO, 0x56ad, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x56ae, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CNTL", REG_MMIO, 0x56af, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x56b0, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_SYM0", REG_MMIO, 0x56b1, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_SYM1", REG_MMIO, 0x56b2, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_SYM2", REG_MMIO, 0x56b3, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x56b4, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x56b5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x56b6, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_EN", REG_MMIO, 0x56b7, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_CNTL", REG_MMIO, 0x56b8, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_RESULT", REG_MMIO, 0x56b9, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x56ba, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x56bb, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x56bc, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x56bd, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x56be, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x56bf, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_CNTL", REG_MMIO, 0x56c3, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_CNTL1", REG_MMIO, 0x56c4, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_FRAMING1", REG_MMIO, 0x56c5, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_FRAMING2", REG_MMIO, 0x56c6, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_FRAMING3", REG_MMIO, 0x56c7, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_FRAMING4", REG_MMIO, 0x56c8, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_AUD_N", REG_MMIO, 0x56c9, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x56ca, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_AUD_M", REG_MMIO, 0x56cb, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x56cc, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_TIMESTAMP", REG_MMIO, 0x56cd, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_PACKET_CNTL", REG_MMIO, 0x56ce, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_RATE_CNTL", REG_MMIO, 0x56cf, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_RATE_UPDATE", REG_MMIO, 0x56d1, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT0", REG_MMIO, 0x56d2, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT1", REG_MMIO, 0x56d3, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT2", REG_MMIO, 0x56d4, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT_UPDATE", REG_MMIO, 0x56d5, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_LINK_TIMING", REG_MMIO, 0x56d6, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_MISC_CNTL", REG_MMIO, 0x56d7, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x56d8, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_TEST_DEBUG_DATA", REG_MMIO, 0x56d9, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x56da, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x56db, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x56dc, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x56dd, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x57, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 },
+	{ "mmDIG8_DIG_FE_CNTL", REG_MMIO, 0x5700, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x5701, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x5702, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_CLOCK_PATTERN", REG_MMIO, 0x5703, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_TEST_PATTERN", REG_MMIO, 0x5704, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x5705, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_FIFO_STATUS", REG_MMIO, 0x5706, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x5707, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x5708, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_CONTROL", REG_MMIO, 0x5709, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_STATUS", REG_MMIO, 0x570a, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x570b, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x570c, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x570d, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x570e, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x570f, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x5710, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x5711, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_GC", REG_MMIO, 0x5713, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x5714, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_0", REG_MMIO, 0x5715, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_1", REG_MMIO, 0x5716, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_2", REG_MMIO, 0x5717, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_3", REG_MMIO, 0x5718, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_4", REG_MMIO, 0x5719, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC2_0", REG_MMIO, 0x571a, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC2_1", REG_MMIO, 0x571b, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC2_2", REG_MMIO, 0x571c, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC2_3", REG_MMIO, 0x571d, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AVI_INFO0", REG_MMIO, 0x571e, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AVI_INFO1", REG_MMIO, 0x571f, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AVI_INFO2", REG_MMIO, 0x5720, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AVI_INFO3", REG_MMIO, 0x5721, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_MPEG_INFO0", REG_MMIO, 0x5722, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_MPEG_INFO1", REG_MMIO, 0x5723, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_HDR", REG_MMIO, 0x5724, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_0", REG_MMIO, 0x5725, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_1", REG_MMIO, 0x5726, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_2", REG_MMIO, 0x5727, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_3", REG_MMIO, 0x5728, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_4", REG_MMIO, 0x5729, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_5", REG_MMIO, 0x572a, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_6", REG_MMIO, 0x572b, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_7", REG_MMIO, 0x572c, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x572d, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_32_0", REG_MMIO, 0x572e, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_32_1", REG_MMIO, 0x572f, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_44_0", REG_MMIO, 0x5730, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_44_1", REG_MMIO, 0x5731, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_48_0", REG_MMIO, 0x5732, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_48_1", REG_MMIO, 0x5733, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_STATUS_0", REG_MMIO, 0x5734, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_STATUS_1", REG_MMIO, 0x5735, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_INFO0", REG_MMIO, 0x5736, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_INFO1", REG_MMIO, 0x5737, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_60958_0", REG_MMIO, 0x5738, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_60958_1", REG_MMIO, 0x5739, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x573a, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_RAMP_CONTROL0", REG_MMIO, 0x573b, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_RAMP_CONTROL1", REG_MMIO, 0x573c, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_RAMP_CONTROL2", REG_MMIO, 0x573d, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_RAMP_CONTROL3", REG_MMIO, 0x573e, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_60958_2", REG_MMIO, 0x573f, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x5740, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_STATUS", REG_MMIO, 0x5741, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x5742, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x5743, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x5744, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x5745, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x5746, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_BE_CNTL", REG_MMIO, 0x5747, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_BE_EN_CNTL", REG_MMIO, 0x5748, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CNTL", REG_MMIO, 0x576b, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CONTROL_CHAR", REG_MMIO, 0x576c, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x576d, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x576e, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x576f, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x5770, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_DEBUG", REG_MMIO, 0x5771, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CTL_BITS", REG_MMIO, 0x5772, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x5773, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x5775, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x5776, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_VERSION", REG_MMIO, 0x5778, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_LANE_ENABLE", REG_MMIO, 0x5779, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x577a, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x577b, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x577c, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x577d, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_CNTL", REG_MMIO, 0x577e, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_LINK_CNTL", REG_MMIO, 0x57a0, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_PIXEL_FORMAT", REG_MMIO, 0x57a1, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSA_COLORIMETRY", REG_MMIO, 0x57a2, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_CONFIG", REG_MMIO, 0x57a3, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_STREAM_CNTL", REG_MMIO, 0x57a4, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_STEER_FIFO", REG_MMIO, 0x57a5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSA_MISC", REG_MMIO, 0x57a6, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_TIMING", REG_MMIO, 0x57a8, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_N", REG_MMIO, 0x57a9, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_M", REG_MMIO, 0x57aa, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x57ab, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x57ac, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_MSA_VBID", REG_MMIO, 0x57ad, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x57ae, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CNTL", REG_MMIO, 0x57af, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x57b0, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_SYM0", REG_MMIO, 0x57b1, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_SYM1", REG_MMIO, 0x57b2, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_SYM2", REG_MMIO, 0x57b3, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x57b4, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x57b5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_EN", REG_MMIO, 0x57b7, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_CNTL", REG_MMIO, 0x57b8, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_RESULT", REG_MMIO, 0x57b9, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x57ba, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x57bb, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x57bc, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x57bd, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x57be, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x57bf, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_CNTL", REG_MMIO, 0x57c3, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_CNTL1", REG_MMIO, 0x57c4, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_FRAMING1", REG_MMIO, 0x57c5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_FRAMING2", REG_MMIO, 0x57c6, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_FRAMING3", REG_MMIO, 0x57c7, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_FRAMING4", REG_MMIO, 0x57c8, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_AUD_N", REG_MMIO, 0x57c9, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x57ca, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_AUD_M", REG_MMIO, 0x57cb, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x57cc, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_TIMESTAMP", REG_MMIO, 0x57cd, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_PACKET_CNTL", REG_MMIO, 0x57ce, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_RATE_CNTL", REG_MMIO, 0x57cf, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_RATE_UPDATE", REG_MMIO, 0x57d1, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT0", REG_MMIO, 0x57d2, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT1", REG_MMIO, 0x57d3, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT2", REG_MMIO, 0x57d4, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT_UPDATE", REG_MMIO, 0x57d5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_LINK_TIMING", REG_MMIO, 0x57d6, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_MISC_CNTL", REG_MMIO, 0x57d7, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x57d8, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_TEST_DEBUG_DATA", REG_MMIO, 0x57d9, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x57da, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x57db, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x57dc, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x57dd, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x58, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x59, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "mmDC_PERFMON10_PERFCOUNTER_CNTL", REG_MMIO, 0x59a0, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFCOUNTER_STATE", REG_MMIO, 0x59a1, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x59a2, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CNTL", REG_MMIO, 0x59a3, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CVALUE_LOW", REG_MMIO, 0x59a4, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_HI", REG_MMIO, 0x59a5, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_LOW", REG_MMIO, 0x59a6, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x59a7, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x59a8, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CNTL2", REG_MMIO, 0x59aa, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM8_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c0, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM8_AZALIA_STREAM_DATA", REG_MMIO, 0x59c1, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM9_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c2, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM9_AZALIA_STREAM_DATA", REG_MMIO, 0x59c3, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM10_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c4, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM10_AZALIA_STREAM_DATA", REG_MMIO, 0x59c5, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM11_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c6, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM11_AZALIA_STREAM_DATA", REG_MMIO, 0x59c7, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM12_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c8, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM12_AZALIA_STREAM_DATA", REG_MMIO, 0x59c9, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM13_AZALIA_STREAM_INDEX", REG_MMIO, 0x59ca, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM13_AZALIA_STREAM_DATA", REG_MMIO, 0x59cb, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM14_AZALIA_STREAM_INDEX", REG_MMIO, 0x59cc, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM14_AZALIA_STREAM_DATA", REG_MMIO, 0x59cd, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM15_AZALIA_STREAM_INDEX", REG_MMIO, 0x59ce, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM15_AZALIA_STREAM_DATA", REG_MMIO, 0x59cf, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d4, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d4, &mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 },
+	{ "mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d5, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d5, &mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 },
+	{ "mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d8, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d9, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59dc, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59dd, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e0, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e1, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e4, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e5, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e8, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e9, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59ec, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59ed, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59f0, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59f1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x5a, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5a84, &mmDCRX_PHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED0)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5a85, &mmDCRX_PHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED1)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5a86, &mmDCRX_PHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED2)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5a87, &mmDCRX_PHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED3)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5a88, &mmDCRX_PHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED4)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5a89, &mmDCRX_PHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED5)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5a8a, &mmDCRX_PHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED6)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5a8b, &mmDCRX_PHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED7)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5a8c, &mmDCRX_PHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED8)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5a8d, &mmDCRX_PHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED9)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5a8e, &mmDCRX_PHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED10)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5a8f, &mmDCRX_PHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED11)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x5a90, &mmDCRX_PHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED12)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x5a91, &mmDCRX_PHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED13)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x5a92, &mmDCRX_PHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED14)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x5a93, &mmDCRX_PHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED15)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x5a94, &mmDCRX_PHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED16)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x5a95, &mmDCRX_PHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED17)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x5a96, &mmDCRX_PHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED18)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x5a97, &mmDCRX_PHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED19)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x5a98, &mmDCRX_PHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED20)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x5a99, &mmDCRX_PHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED21)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x5a9a, &mmDCRX_PHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED22)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x5a9b, &mmDCRX_PHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED23)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x5a9c, &mmDCRX_PHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED24)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x5a9d, &mmDCRX_PHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED25)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x5a9e, &mmDCRX_PHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED26)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x5a9f, &mmDCRX_PHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED27)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x5aa0, &mmDCRX_PHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED28)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x5aa1, &mmDCRX_PHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED29)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x5aa2, &mmDCRX_PHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED30)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x5aa3, &mmDCRX_PHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED31)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x5aa4, &mmDCRX_PHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED32)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x5aa5, &mmDCRX_PHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED33)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x5aa6, &mmDCRX_PHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED34)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x5aa7, &mmDCRX_PHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED35)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x5aa8, &mmDCRX_PHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED36)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x5aa9, &mmDCRX_PHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED37)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x5aaa, &mmDCRX_PHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED38)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x5aab, &mmDCRX_PHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED39)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x5aac, &mmDCRX_PHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED40)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x5aad, &mmDCRX_PHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED41)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x5aae, &mmDCRX_PHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED42)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED42[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x5aaf, &mmDCRX_PHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED43)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED43[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x5ab0, &mmDCRX_PHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED44)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED44[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x5ab1, &mmDCRX_PHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED45)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED45[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x5ab2, &mmDCRX_PHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED46)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED46[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x5ab3, &mmDCRX_PHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED47)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED47[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x5ab4, &mmDCRX_PHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED48)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED48[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x5ab5, &mmDCRX_PHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED49)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED49[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x5ab6, &mmDCRX_PHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED50)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED50[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x5ab7, &mmDCRX_PHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED51)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED51[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x5ab8, &mmDCRX_PHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED52)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED52[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x5ab9, &mmDCRX_PHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED53)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED53[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x5aba, &mmDCRX_PHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED54)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED54[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x5abb, &mmDCRX_PHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED55)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED55[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x5abc, &mmDCRX_PHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED56)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED56[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x5abd, &mmDCRX_PHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED57)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED57[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x5abe, &mmDCRX_PHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED58)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED58[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x5abf, &mmDCRX_PHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED59)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED59[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x5ac0, &mmDCRX_PHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED60)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED60[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x5ac1, &mmDCRX_PHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED61)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED61[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x5ac2, &mmDCRX_PHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED62)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED62[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x5ac3, &mmDCRX_PHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED63)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED63[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x5ac4, &mmDCRX_PHY_MACRO_CNTL_RESERVED64[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED64)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED64[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x5ac5, &mmDCRX_PHY_MACRO_CNTL_RESERVED65[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED65)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED65[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x5ac6, &mmDCRX_PHY_MACRO_CNTL_RESERVED66[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED66)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED66[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x5ac7, &mmDCRX_PHY_MACRO_CNTL_RESERVED67[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED67)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED67[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x5ac8, &mmDCRX_PHY_MACRO_CNTL_RESERVED68[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED68)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED68[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x5ac9, &mmDCRX_PHY_MACRO_CNTL_RESERVED69[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED69)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED69[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x5aca, &mmDCRX_PHY_MACRO_CNTL_RESERVED70[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED70)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED70[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x5acb, &mmDCRX_PHY_MACRO_CNTL_RESERVED71[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED71)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED71[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x5acc, &mmDCRX_PHY_MACRO_CNTL_RESERVED72[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED72)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED72[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x5acd, &mmDCRX_PHY_MACRO_CNTL_RESERVED73[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED73)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED73[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x5ace, &mmDCRX_PHY_MACRO_CNTL_RESERVED74[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED74)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED74[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x5acf, &mmDCRX_PHY_MACRO_CNTL_RESERVED75[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED75)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED75[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x5ad0, &mmDCRX_PHY_MACRO_CNTL_RESERVED76[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED76)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED76[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x5ad1, &mmDCRX_PHY_MACRO_CNTL_RESERVED77[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED77)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED77[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x5ad2, &mmDCRX_PHY_MACRO_CNTL_RESERVED78[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED78)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED78[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x5ad3, &mmDCRX_PHY_MACRO_CNTL_RESERVED79[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED79)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED79[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x5ad4, &mmDCRX_PHY_MACRO_CNTL_RESERVED80[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED80)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED80[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x5ad5, &mmDCRX_PHY_MACRO_CNTL_RESERVED81[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED81)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED81[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x5ad6, &mmDCRX_PHY_MACRO_CNTL_RESERVED82[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED82)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED82[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x5ad7, &mmDCRX_PHY_MACRO_CNTL_RESERVED83[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED83)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED83[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x5ad8, &mmDCRX_PHY_MACRO_CNTL_RESERVED84[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED84)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED84[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x5ad9, &mmDCRX_PHY_MACRO_CNTL_RESERVED85[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED85)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED85[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x5ada, &mmDCRX_PHY_MACRO_CNTL_RESERVED86[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED86)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED86[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x5adb, &mmDCRX_PHY_MACRO_CNTL_RESERVED87[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED87)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED87[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x5adc, &mmDCRX_PHY_MACRO_CNTL_RESERVED88[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED88)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED88[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x5add, &mmDCRX_PHY_MACRO_CNTL_RESERVED89[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED89)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED89[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x5ade, &mmDCRX_PHY_MACRO_CNTL_RESERVED90[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED90)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED90[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x5adf, &mmDCRX_PHY_MACRO_CNTL_RESERVED91[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED91)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED91[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x5ae0, &mmDCRX_PHY_MACRO_CNTL_RESERVED92[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED92)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED92[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x5ae1, &mmDCRX_PHY_MACRO_CNTL_RESERVED93[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED93)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED93[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x5ae2, &mmDCRX_PHY_MACRO_CNTL_RESERVED94[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED94)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED94[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x5ae3, &mmDCRX_PHY_MACRO_CNTL_RESERVED95[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED95)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED95[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x5ae4, &mmDCRX_PHY_MACRO_CNTL_RESERVED96[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED96)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED96[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x5ae5, &mmDCRX_PHY_MACRO_CNTL_RESERVED97[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED97)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED97[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x5ae6, &mmDCRX_PHY_MACRO_CNTL_RESERVED98[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED98)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED98[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x5ae7, &mmDCRX_PHY_MACRO_CNTL_RESERVED99[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED99)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED99[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x5ae8, &mmDCRX_PHY_MACRO_CNTL_RESERVED100[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED100)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED100[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x5ae9, &mmDCRX_PHY_MACRO_CNTL_RESERVED101[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED101)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED101[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x5aea, &mmDCRX_PHY_MACRO_CNTL_RESERVED102[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED102)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED102[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x5aeb, &mmDCRX_PHY_MACRO_CNTL_RESERVED103[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED103)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED103[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x5aec, &mmDCRX_PHY_MACRO_CNTL_RESERVED104[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED104)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED104[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x5aed, &mmDCRX_PHY_MACRO_CNTL_RESERVED105[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED105)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED105[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x5aee, &mmDCRX_PHY_MACRO_CNTL_RESERVED106[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED106)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED106[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x5aef, &mmDCRX_PHY_MACRO_CNTL_RESERVED107[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED107)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED107[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x5af0, &mmDCRX_PHY_MACRO_CNTL_RESERVED108[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED108)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED108[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x5af1, &mmDCRX_PHY_MACRO_CNTL_RESERVED109[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED109)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED109[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x5af2, &mmDCRX_PHY_MACRO_CNTL_RESERVED110[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED110)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED110[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x5af3, &mmDCRX_PHY_MACRO_CNTL_RESERVED111[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED111)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED111[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x5af4, &mmDCRX_PHY_MACRO_CNTL_RESERVED112[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED112)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED112[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x5af5, &mmDCRX_PHY_MACRO_CNTL_RESERVED113[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED113)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED113[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x5af6, &mmDCRX_PHY_MACRO_CNTL_RESERVED114[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED114)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED114[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x5af7, &mmDCRX_PHY_MACRO_CNTL_RESERVED115[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED115)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED115[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x5af8, &mmDCRX_PHY_MACRO_CNTL_RESERVED116[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED116)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED116[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x5af9, &mmDCRX_PHY_MACRO_CNTL_RESERVED117[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED117)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED117[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x5afa, &mmDCRX_PHY_MACRO_CNTL_RESERVED118[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED118)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED118[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x5afb, &mmDCRX_PHY_MACRO_CNTL_RESERVED119[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED119)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED119[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x5afc, &mmDCRX_PHY_MACRO_CNTL_RESERVED120[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED120)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED120[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x5afd, &mmDCRX_PHY_MACRO_CNTL_RESERVED121[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED121)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED121[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x5afe, &mmDCRX_PHY_MACRO_CNTL_RESERVED122[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED122)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED122[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x5aff, &mmDCRX_PHY_MACRO_CNTL_RESERVED123[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED123)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED123[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x5b, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x5b00, &mmDCRX_PHY_MACRO_CNTL_RESERVED124[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED124)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED124[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x5b01, &mmDCRX_PHY_MACRO_CNTL_RESERVED125[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED125)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED125[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x5b02, &mmDCRX_PHY_MACRO_CNTL_RESERVED126[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED126)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED126[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x5b03, &mmDCRX_PHY_MACRO_CNTL_RESERVED127[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED127)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED127[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x5b04, &mmDCRX_PHY_MACRO_CNTL_RESERVED128[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED128)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED128[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x5b05, &mmDCRX_PHY_MACRO_CNTL_RESERVED129[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED129)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED129[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x5b06, &mmDCRX_PHY_MACRO_CNTL_RESERVED130[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED130)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED130[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x5b07, &mmDCRX_PHY_MACRO_CNTL_RESERVED131[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED131)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED131[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x5b08, &mmDCRX_PHY_MACRO_CNTL_RESERVED132[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED132)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED132[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x5b09, &mmDCRX_PHY_MACRO_CNTL_RESERVED133[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED133)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED133[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x5b0a, &mmDCRX_PHY_MACRO_CNTL_RESERVED134[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED134)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED134[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x5b0b, &mmDCRX_PHY_MACRO_CNTL_RESERVED135[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED135)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED135[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x5b0c, &mmDCRX_PHY_MACRO_CNTL_RESERVED136[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED136)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED136[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x5b0d, &mmDCRX_PHY_MACRO_CNTL_RESERVED137[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED137)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED137[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x5b0e, &mmDCRX_PHY_MACRO_CNTL_RESERVED138[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED138)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED138[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x5b0f, &mmDCRX_PHY_MACRO_CNTL_RESERVED139[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED139)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED139[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x5b10, &mmDCRX_PHY_MACRO_CNTL_RESERVED140[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED140)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED140[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x5b11, &mmDCRX_PHY_MACRO_CNTL_RESERVED141[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED141)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED141[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x5b12, &mmDCRX_PHY_MACRO_CNTL_RESERVED142[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED142)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED142[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x5b13, &mmDCRX_PHY_MACRO_CNTL_RESERVED143[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED143)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED143[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x5b14, &mmDCRX_PHY_MACRO_CNTL_RESERVED144[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED144)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED144[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x5b15, &mmDCRX_PHY_MACRO_CNTL_RESERVED145[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED145)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED145[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x5b16, &mmDCRX_PHY_MACRO_CNTL_RESERVED146[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED146)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED146[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x5b17, &mmDCRX_PHY_MACRO_CNTL_RESERVED147[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED147)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED147[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x5b18, &mmDCRX_PHY_MACRO_CNTL_RESERVED148[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED148)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED148[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x5b19, &mmDCRX_PHY_MACRO_CNTL_RESERVED149[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED149)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED149[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x5b1a, &mmDCRX_PHY_MACRO_CNTL_RESERVED150[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED150)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED150[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x5b1b, &mmDCRX_PHY_MACRO_CNTL_RESERVED151[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED151)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED151[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x5b1c, &mmDCRX_PHY_MACRO_CNTL_RESERVED152[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED152)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED152[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x5b1d, &mmDCRX_PHY_MACRO_CNTL_RESERVED153[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED153)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED153[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x5b1e, &mmDCRX_PHY_MACRO_CNTL_RESERVED154[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED154)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED154[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x5b1f, &mmDCRX_PHY_MACRO_CNTL_RESERVED155[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED155)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED155[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x5b20, &mmDCRX_PHY_MACRO_CNTL_RESERVED156[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED156)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED156[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x5b21, &mmDCRX_PHY_MACRO_CNTL_RESERVED157[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED157)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED157[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x5b22, &mmDCRX_PHY_MACRO_CNTL_RESERVED158[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED158)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED158[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x5b23, &mmDCRX_PHY_MACRO_CNTL_RESERVED159[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED159)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED159[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED160", REG_MMIO, 0x5b24, &mmDCRX_PHY_MACRO_CNTL_RESERVED160[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED160)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED160[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED161", REG_MMIO, 0x5b25, &mmDCRX_PHY_MACRO_CNTL_RESERVED161[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED161)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED161[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED162", REG_MMIO, 0x5b26, &mmDCRX_PHY_MACRO_CNTL_RESERVED162[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED162)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED162[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED163", REG_MMIO, 0x5b27, &mmDCRX_PHY_MACRO_CNTL_RESERVED163[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED163)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED163[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED164", REG_MMIO, 0x5b28, &mmDCRX_PHY_MACRO_CNTL_RESERVED164[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED164)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED164[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED165", REG_MMIO, 0x5b29, &mmDCRX_PHY_MACRO_CNTL_RESERVED165[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED165)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED165[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED166", REG_MMIO, 0x5b2a, &mmDCRX_PHY_MACRO_CNTL_RESERVED166[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED166)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED166[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED167", REG_MMIO, 0x5b2b, &mmDCRX_PHY_MACRO_CNTL_RESERVED167[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED167)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED167[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED168", REG_MMIO, 0x5b2c, &mmDCRX_PHY_MACRO_CNTL_RESERVED168[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED168)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED168[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED169", REG_MMIO, 0x5b2d, &mmDCRX_PHY_MACRO_CNTL_RESERVED169[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED169)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED169[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED170", REG_MMIO, 0x5b2e, &mmDCRX_PHY_MACRO_CNTL_RESERVED170[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED170)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED170[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED171", REG_MMIO, 0x5b2f, &mmDCRX_PHY_MACRO_CNTL_RESERVED171[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED171)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED171[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED172", REG_MMIO, 0x5b30, &mmDCRX_PHY_MACRO_CNTL_RESERVED172[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED172)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED172[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED173", REG_MMIO, 0x5b31, &mmDCRX_PHY_MACRO_CNTL_RESERVED173[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED173)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED173[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED174", REG_MMIO, 0x5b32, &mmDCRX_PHY_MACRO_CNTL_RESERVED174[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED174)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED174[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED175", REG_MMIO, 0x5b33, &mmDCRX_PHY_MACRO_CNTL_RESERVED175[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED175)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED175[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED176", REG_MMIO, 0x5b34, &mmDCRX_PHY_MACRO_CNTL_RESERVED176[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED176)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED176[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED177", REG_MMIO, 0x5b35, &mmDCRX_PHY_MACRO_CNTL_RESERVED177[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED177)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED177[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED178", REG_MMIO, 0x5b36, &mmDCRX_PHY_MACRO_CNTL_RESERVED178[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED178)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED178[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED179", REG_MMIO, 0x5b37, &mmDCRX_PHY_MACRO_CNTL_RESERVED179[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED179)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED179[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED180", REG_MMIO, 0x5b38, &mmDCRX_PHY_MACRO_CNTL_RESERVED180[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED180)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED180[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED181", REG_MMIO, 0x5b39, &mmDCRX_PHY_MACRO_CNTL_RESERVED181[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED181)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED181[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED182", REG_MMIO, 0x5b3a, &mmDCRX_PHY_MACRO_CNTL_RESERVED182[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED182)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED182[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED183", REG_MMIO, 0x5b3b, &mmDCRX_PHY_MACRO_CNTL_RESERVED183[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED183)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED183[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED184", REG_MMIO, 0x5b3c, &mmDCRX_PHY_MACRO_CNTL_RESERVED184[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED184)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED184[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED185", REG_MMIO, 0x5b3d, &mmDCRX_PHY_MACRO_CNTL_RESERVED185[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED185)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED185[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED186", REG_MMIO, 0x5b3e, &mmDCRX_PHY_MACRO_CNTL_RESERVED186[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED186)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED186[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED187", REG_MMIO, 0x5b3f, &mmDCRX_PHY_MACRO_CNTL_RESERVED187[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED187)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED187[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED188", REG_MMIO, 0x5b40, &mmDCRX_PHY_MACRO_CNTL_RESERVED188[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED188)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED188[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED189", REG_MMIO, 0x5b41, &mmDCRX_PHY_MACRO_CNTL_RESERVED189[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED189)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED189[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED190", REG_MMIO, 0x5b42, &mmDCRX_PHY_MACRO_CNTL_RESERVED190[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED190)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED190[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED191", REG_MMIO, 0x5b43, &mmDCRX_PHY_MACRO_CNTL_RESERVED191[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED191)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED191[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED192", REG_MMIO, 0x5b44, &mmDCRX_PHY_MACRO_CNTL_RESERVED192[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED192)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED192[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED193", REG_MMIO, 0x5b45, &mmDCRX_PHY_MACRO_CNTL_RESERVED193[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED193)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED193[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED194", REG_MMIO, 0x5b46, &mmDCRX_PHY_MACRO_CNTL_RESERVED194[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED194)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED194[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED195", REG_MMIO, 0x5b47, &mmDCRX_PHY_MACRO_CNTL_RESERVED195[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED195)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED195[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED196", REG_MMIO, 0x5b48, &mmDCRX_PHY_MACRO_CNTL_RESERVED196[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED196)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED196[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED197", REG_MMIO, 0x5b49, &mmDCRX_PHY_MACRO_CNTL_RESERVED197[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED197)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED197[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED198", REG_MMIO, 0x5b4a, &mmDCRX_PHY_MACRO_CNTL_RESERVED198[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED198)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED198[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED199", REG_MMIO, 0x5b4b, &mmDCRX_PHY_MACRO_CNTL_RESERVED199[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED199)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED199[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED200", REG_MMIO, 0x5b4c, &mmDCRX_PHY_MACRO_CNTL_RESERVED200[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED200)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED200[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED201", REG_MMIO, 0x5b4d, &mmDCRX_PHY_MACRO_CNTL_RESERVED201[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED201)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED201[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED202", REG_MMIO, 0x5b4e, &mmDCRX_PHY_MACRO_CNTL_RESERVED202[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED202)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED202[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED203", REG_MMIO, 0x5b4f, &mmDCRX_PHY_MACRO_CNTL_RESERVED203[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED203)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED203[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED204", REG_MMIO, 0x5b50, &mmDCRX_PHY_MACRO_CNTL_RESERVED204[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED204)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED204[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED205", REG_MMIO, 0x5b51, &mmDCRX_PHY_MACRO_CNTL_RESERVED205[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED205)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED205[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED206", REG_MMIO, 0x5b52, &mmDCRX_PHY_MACRO_CNTL_RESERVED206[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED206)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED206[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED207", REG_MMIO, 0x5b53, &mmDCRX_PHY_MACRO_CNTL_RESERVED207[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED207)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED207[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED208", REG_MMIO, 0x5b54, &mmDCRX_PHY_MACRO_CNTL_RESERVED208[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED208)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED208[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED209", REG_MMIO, 0x5b55, &mmDCRX_PHY_MACRO_CNTL_RESERVED209[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED209)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED209[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED210", REG_MMIO, 0x5b56, &mmDCRX_PHY_MACRO_CNTL_RESERVED210[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED210)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED210[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED211", REG_MMIO, 0x5b57, &mmDCRX_PHY_MACRO_CNTL_RESERVED211[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED211)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED211[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED212", REG_MMIO, 0x5b58, &mmDCRX_PHY_MACRO_CNTL_RESERVED212[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED212)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED212[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED213", REG_MMIO, 0x5b59, &mmDCRX_PHY_MACRO_CNTL_RESERVED213[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED213)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED213[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED214", REG_MMIO, 0x5b5a, &mmDCRX_PHY_MACRO_CNTL_RESERVED214[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED214)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED214[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED215", REG_MMIO, 0x5b5b, &mmDCRX_PHY_MACRO_CNTL_RESERVED215[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED215)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED215[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED216", REG_MMIO, 0x5b5c, &mmDCRX_PHY_MACRO_CNTL_RESERVED216[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED216)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED216[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED217", REG_MMIO, 0x5b5d, &mmDCRX_PHY_MACRO_CNTL_RESERVED217[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED217)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED217[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED218", REG_MMIO, 0x5b5e, &mmDCRX_PHY_MACRO_CNTL_RESERVED218[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED218)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED218[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED219", REG_MMIO, 0x5b5f, &mmDCRX_PHY_MACRO_CNTL_RESERVED219[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED219)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED219[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED220", REG_MMIO, 0x5b60, &mmDCRX_PHY_MACRO_CNTL_RESERVED220[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED220)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED220[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED221", REG_MMIO, 0x5b61, &mmDCRX_PHY_MACRO_CNTL_RESERVED221[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED221)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED221[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED222", REG_MMIO, 0x5b62, &mmDCRX_PHY_MACRO_CNTL_RESERVED222[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED222)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED222[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED223", REG_MMIO, 0x5b63, &mmDCRX_PHY_MACRO_CNTL_RESERVED223[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED223)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED223[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED224", REG_MMIO, 0x5b64, &mmDCRX_PHY_MACRO_CNTL_RESERVED224[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED224)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED224[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED225", REG_MMIO, 0x5b65, &mmDCRX_PHY_MACRO_CNTL_RESERVED225[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED225)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED225[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED226", REG_MMIO, 0x5b66, &mmDCRX_PHY_MACRO_CNTL_RESERVED226[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED226)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED226[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED227", REG_MMIO, 0x5b67, &mmDCRX_PHY_MACRO_CNTL_RESERVED227[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED227)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED227[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED228", REG_MMIO, 0x5b68, &mmDCRX_PHY_MACRO_CNTL_RESERVED228[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED228)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED228[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED229", REG_MMIO, 0x5b69, &mmDCRX_PHY_MACRO_CNTL_RESERVED229[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED229)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED229[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED230", REG_MMIO, 0x5b6a, &mmDCRX_PHY_MACRO_CNTL_RESERVED230[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED230)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED230[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED231", REG_MMIO, 0x5b6b, &mmDCRX_PHY_MACRO_CNTL_RESERVED231[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED231)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED231[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED232", REG_MMIO, 0x5b6c, &mmDCRX_PHY_MACRO_CNTL_RESERVED232[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED232)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED232[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED233", REG_MMIO, 0x5b6d, &mmDCRX_PHY_MACRO_CNTL_RESERVED233[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED233)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED233[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED234", REG_MMIO, 0x5b6e, &mmDCRX_PHY_MACRO_CNTL_RESERVED234[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED234)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED234[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED235", REG_MMIO, 0x5b6f, &mmDCRX_PHY_MACRO_CNTL_RESERVED235[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED235)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED235[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED236", REG_MMIO, 0x5b70, &mmDCRX_PHY_MACRO_CNTL_RESERVED236[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED236)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED236[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED237", REG_MMIO, 0x5b71, &mmDCRX_PHY_MACRO_CNTL_RESERVED237[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED237)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED237[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED238", REG_MMIO, 0x5b72, &mmDCRX_PHY_MACRO_CNTL_RESERVED238[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED238)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED238[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED239", REG_MMIO, 0x5b73, &mmDCRX_PHY_MACRO_CNTL_RESERVED239[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED239)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED239[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED240", REG_MMIO, 0x5b74, &mmDCRX_PHY_MACRO_CNTL_RESERVED240[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED240)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED240[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED241", REG_MMIO, 0x5b75, &mmDCRX_PHY_MACRO_CNTL_RESERVED241[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED241)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED241[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED242", REG_MMIO, 0x5b76, &mmDCRX_PHY_MACRO_CNTL_RESERVED242[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED242)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED242[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED243", REG_MMIO, 0x5b77, &mmDCRX_PHY_MACRO_CNTL_RESERVED243[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED243)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED243[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED244", REG_MMIO, 0x5b78, &mmDCRX_PHY_MACRO_CNTL_RESERVED244[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED244)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED244[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED245", REG_MMIO, 0x5b79, &mmDCRX_PHY_MACRO_CNTL_RESERVED245[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED245)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED245[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED246", REG_MMIO, 0x5b7a, &mmDCRX_PHY_MACRO_CNTL_RESERVED246[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED246)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED246[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED247", REG_MMIO, 0x5b7b, &mmDCRX_PHY_MACRO_CNTL_RESERVED247[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED247)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED247[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED248", REG_MMIO, 0x5b7c, &mmDCRX_PHY_MACRO_CNTL_RESERVED248[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED248)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED248[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED249", REG_MMIO, 0x5b7d, &mmDCRX_PHY_MACRO_CNTL_RESERVED249[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED249)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED249[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED250", REG_MMIO, 0x5b7e, &mmDCRX_PHY_MACRO_CNTL_RESERVED250[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED250)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED250[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED251", REG_MMIO, 0x5b7f, &mmDCRX_PHY_MACRO_CNTL_RESERVED251[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED251)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED251[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED252", REG_MMIO, 0x5b80, &mmDCRX_PHY_MACRO_CNTL_RESERVED252[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED252)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED252[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED253", REG_MMIO, 0x5b81, &mmDCRX_PHY_MACRO_CNTL_RESERVED253[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED253)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED253[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED254", REG_MMIO, 0x5b82, &mmDCRX_PHY_MACRO_CNTL_RESERVED254[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED254)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED254[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED255", REG_MMIO, 0x5b83, &mmDCRX_PHY_MACRO_CNTL_RESERVED255[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED255)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED255[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED256", REG_MMIO, 0x5b84, &mmDCRX_PHY_MACRO_CNTL_RESERVED256[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED256)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED256[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED257", REG_MMIO, 0x5b85, &mmDCRX_PHY_MACRO_CNTL_RESERVED257[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED257)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED257[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED258", REG_MMIO, 0x5b86, &mmDCRX_PHY_MACRO_CNTL_RESERVED258[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED258)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED258[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED259", REG_MMIO, 0x5b87, &mmDCRX_PHY_MACRO_CNTL_RESERVED259[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED259)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED259[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED260", REG_MMIO, 0x5b88, &mmDCRX_PHY_MACRO_CNTL_RESERVED260[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED260)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED260[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED261", REG_MMIO, 0x5b89, &mmDCRX_PHY_MACRO_CNTL_RESERVED261[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED261)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED261[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED262", REG_MMIO, 0x5b8a, &mmDCRX_PHY_MACRO_CNTL_RESERVED262[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED262)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED262[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED263", REG_MMIO, 0x5b8b, &mmDCRX_PHY_MACRO_CNTL_RESERVED263[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED263)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED263[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED264", REG_MMIO, 0x5b8c, &mmDCRX_PHY_MACRO_CNTL_RESERVED264[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED264)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED264[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED265", REG_MMIO, 0x5b8d, &mmDCRX_PHY_MACRO_CNTL_RESERVED265[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED265)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED265[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED266", REG_MMIO, 0x5b8e, &mmDCRX_PHY_MACRO_CNTL_RESERVED266[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED266)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED266[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED267", REG_MMIO, 0x5b8f, &mmDCRX_PHY_MACRO_CNTL_RESERVED267[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED267)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED267[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED268", REG_MMIO, 0x5b90, &mmDCRX_PHY_MACRO_CNTL_RESERVED268[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED268)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED268[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED269", REG_MMIO, 0x5b91, &mmDCRX_PHY_MACRO_CNTL_RESERVED269[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED269)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED269[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED270", REG_MMIO, 0x5b92, &mmDCRX_PHY_MACRO_CNTL_RESERVED270[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED270)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED270[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED271", REG_MMIO, 0x5b93, &mmDCRX_PHY_MACRO_CNTL_RESERVED271[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED271)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED271[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED272", REG_MMIO, 0x5b94, &mmDCRX_PHY_MACRO_CNTL_RESERVED272[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED272)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED272[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED273", REG_MMIO, 0x5b95, &mmDCRX_PHY_MACRO_CNTL_RESERVED273[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED273)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED273[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED274", REG_MMIO, 0x5b96, &mmDCRX_PHY_MACRO_CNTL_RESERVED274[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED274)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED274[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED275", REG_MMIO, 0x5b97, &mmDCRX_PHY_MACRO_CNTL_RESERVED275[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED275)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED275[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED276", REG_MMIO, 0x5b98, &mmDCRX_PHY_MACRO_CNTL_RESERVED276[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED276)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED276[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED277", REG_MMIO, 0x5b99, &mmDCRX_PHY_MACRO_CNTL_RESERVED277[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED277)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED277[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED278", REG_MMIO, 0x5b9a, &mmDCRX_PHY_MACRO_CNTL_RESERVED278[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED278)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED278[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED279", REG_MMIO, 0x5b9b, &mmDCRX_PHY_MACRO_CNTL_RESERVED279[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED279)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED279[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED280", REG_MMIO, 0x5b9c, &mmDCRX_PHY_MACRO_CNTL_RESERVED280[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED280)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED280[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED281", REG_MMIO, 0x5b9d, &mmDCRX_PHY_MACRO_CNTL_RESERVED281[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED281)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED281[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED282", REG_MMIO, 0x5b9e, &mmDCRX_PHY_MACRO_CNTL_RESERVED282[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED282)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED282[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED283", REG_MMIO, 0x5b9f, &mmDCRX_PHY_MACRO_CNTL_RESERVED283[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED283)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED283[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED284", REG_MMIO, 0x5ba0, &mmDCRX_PHY_MACRO_CNTL_RESERVED284[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED284)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED284[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED285", REG_MMIO, 0x5ba1, &mmDCRX_PHY_MACRO_CNTL_RESERVED285[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED285)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED285[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED286", REG_MMIO, 0x5ba2, &mmDCRX_PHY_MACRO_CNTL_RESERVED286[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED286)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED286[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED287", REG_MMIO, 0x5ba3, &mmDCRX_PHY_MACRO_CNTL_RESERVED287[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED287)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED287[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED288", REG_MMIO, 0x5ba4, &mmDCRX_PHY_MACRO_CNTL_RESERVED288[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED288)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED288[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED289", REG_MMIO, 0x5ba5, &mmDCRX_PHY_MACRO_CNTL_RESERVED289[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED289)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED289[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED290", REG_MMIO, 0x5ba6, &mmDCRX_PHY_MACRO_CNTL_RESERVED290[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED290)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED290[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED291", REG_MMIO, 0x5ba7, &mmDCRX_PHY_MACRO_CNTL_RESERVED291[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED291)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED291[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED292", REG_MMIO, 0x5ba8, &mmDCRX_PHY_MACRO_CNTL_RESERVED292[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED292)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED292[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED293", REG_MMIO, 0x5ba9, &mmDCRX_PHY_MACRO_CNTL_RESERVED293[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED293)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED293[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED294", REG_MMIO, 0x5baa, &mmDCRX_PHY_MACRO_CNTL_RESERVED294[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED294)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED294[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED295", REG_MMIO, 0x5bab, &mmDCRX_PHY_MACRO_CNTL_RESERVED295[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED295)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED295[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED296", REG_MMIO, 0x5bac, &mmDCRX_PHY_MACRO_CNTL_RESERVED296[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED296)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED296[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED297", REG_MMIO, 0x5bad, &mmDCRX_PHY_MACRO_CNTL_RESERVED297[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED297)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED297[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED298", REG_MMIO, 0x5bae, &mmDCRX_PHY_MACRO_CNTL_RESERVED298[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED298)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED298[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED299", REG_MMIO, 0x5baf, &mmDCRX_PHY_MACRO_CNTL_RESERVED299[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED299)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED299[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED300", REG_MMIO, 0x5bb0, &mmDCRX_PHY_MACRO_CNTL_RESERVED300[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED300)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED300[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED301", REG_MMIO, 0x5bb1, &mmDCRX_PHY_MACRO_CNTL_RESERVED301[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED301)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED301[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED302", REG_MMIO, 0x5bb2, &mmDCRX_PHY_MACRO_CNTL_RESERVED302[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED302)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED302[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED303", REG_MMIO, 0x5bb3, &mmDCRX_PHY_MACRO_CNTL_RESERVED303[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED303)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED303[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED304", REG_MMIO, 0x5bb4, &mmDCRX_PHY_MACRO_CNTL_RESERVED304[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED304)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED304[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED305", REG_MMIO, 0x5bb5, &mmDCRX_PHY_MACRO_CNTL_RESERVED305[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED305)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED305[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED306", REG_MMIO, 0x5bb6, &mmDCRX_PHY_MACRO_CNTL_RESERVED306[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED306)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED306[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED307", REG_MMIO, 0x5bb7, &mmDCRX_PHY_MACRO_CNTL_RESERVED307[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED307)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED307[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED308", REG_MMIO, 0x5bb8, &mmDCRX_PHY_MACRO_CNTL_RESERVED308[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED308)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED308[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED309", REG_MMIO, 0x5bb9, &mmDCRX_PHY_MACRO_CNTL_RESERVED309[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED309)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED309[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED310", REG_MMIO, 0x5bba, &mmDCRX_PHY_MACRO_CNTL_RESERVED310[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED310)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED310[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED311", REG_MMIO, 0x5bbb, &mmDCRX_PHY_MACRO_CNTL_RESERVED311[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED311)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED311[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED312", REG_MMIO, 0x5bbc, &mmDCRX_PHY_MACRO_CNTL_RESERVED312[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED312)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED312[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED313", REG_MMIO, 0x5bbd, &mmDCRX_PHY_MACRO_CNTL_RESERVED313[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED313)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED313[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED314", REG_MMIO, 0x5bbe, &mmDCRX_PHY_MACRO_CNTL_RESERVED314[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED314)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED314[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED315", REG_MMIO, 0x5bbf, &mmDCRX_PHY_MACRO_CNTL_RESERVED315[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED315)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED315[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED316", REG_MMIO, 0x5bc0, &mmDCRX_PHY_MACRO_CNTL_RESERVED316[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED316)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED316[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED317", REG_MMIO, 0x5bc1, &mmDCRX_PHY_MACRO_CNTL_RESERVED317[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED317)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED317[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED318", REG_MMIO, 0x5bc2, &mmDCRX_PHY_MACRO_CNTL_RESERVED318[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED318)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED318[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED319", REG_MMIO, 0x5bc3, &mmDCRX_PHY_MACRO_CNTL_RESERVED319[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED319)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED319[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED320", REG_MMIO, 0x5bc4, &mmDCRX_PHY_MACRO_CNTL_RESERVED320[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED320)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED320[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED321", REG_MMIO, 0x5bc5, &mmDCRX_PHY_MACRO_CNTL_RESERVED321[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED321)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED321[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED322", REG_MMIO, 0x5bc6, &mmDCRX_PHY_MACRO_CNTL_RESERVED322[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED322)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED322[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED323", REG_MMIO, 0x5bc7, &mmDCRX_PHY_MACRO_CNTL_RESERVED323[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED323)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED323[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED324", REG_MMIO, 0x5bc8, &mmDCRX_PHY_MACRO_CNTL_RESERVED324[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED324)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED324[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED325", REG_MMIO, 0x5bc9, &mmDCRX_PHY_MACRO_CNTL_RESERVED325[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED325)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED325[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED326", REG_MMIO, 0x5bca, &mmDCRX_PHY_MACRO_CNTL_RESERVED326[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED326)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED326[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED327", REG_MMIO, 0x5bcb, &mmDCRX_PHY_MACRO_CNTL_RESERVED327[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED327)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED327[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED328", REG_MMIO, 0x5bcc, &mmDCRX_PHY_MACRO_CNTL_RESERVED328[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED328)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED328[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED329", REG_MMIO, 0x5bcd, &mmDCRX_PHY_MACRO_CNTL_RESERVED329[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED329)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED329[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED330", REG_MMIO, 0x5bce, &mmDCRX_PHY_MACRO_CNTL_RESERVED330[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED330)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED330[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED331", REG_MMIO, 0x5bcf, &mmDCRX_PHY_MACRO_CNTL_RESERVED331[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED331)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED331[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED332", REG_MMIO, 0x5bd0, &mmDCRX_PHY_MACRO_CNTL_RESERVED332[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED332)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED332[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED333", REG_MMIO, 0x5bd1, &mmDCRX_PHY_MACRO_CNTL_RESERVED333[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED333)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED333[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED334", REG_MMIO, 0x5bd2, &mmDCRX_PHY_MACRO_CNTL_RESERVED334[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED334)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED334[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED335", REG_MMIO, 0x5bd3, &mmDCRX_PHY_MACRO_CNTL_RESERVED335[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED335)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED335[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED336", REG_MMIO, 0x5bd4, &mmDCRX_PHY_MACRO_CNTL_RESERVED336[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED336)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED336[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED337", REG_MMIO, 0x5bd5, &mmDCRX_PHY_MACRO_CNTL_RESERVED337[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED337)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED337[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED338", REG_MMIO, 0x5bd6, &mmDCRX_PHY_MACRO_CNTL_RESERVED338[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED338)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED338[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED339", REG_MMIO, 0x5bd7, &mmDCRX_PHY_MACRO_CNTL_RESERVED339[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED339)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED339[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED340", REG_MMIO, 0x5bd8, &mmDCRX_PHY_MACRO_CNTL_RESERVED340[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED340)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED340[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED341", REG_MMIO, 0x5bd9, &mmDCRX_PHY_MACRO_CNTL_RESERVED341[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED341)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED341[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED342", REG_MMIO, 0x5bda, &mmDCRX_PHY_MACRO_CNTL_RESERVED342[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED342)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED342[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED343", REG_MMIO, 0x5bdb, &mmDCRX_PHY_MACRO_CNTL_RESERVED343[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED343)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED343[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED344", REG_MMIO, 0x5bdc, &mmDCRX_PHY_MACRO_CNTL_RESERVED344[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED344)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED344[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED345", REG_MMIO, 0x5bdd, &mmDCRX_PHY_MACRO_CNTL_RESERVED345[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED345)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED345[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED346", REG_MMIO, 0x5bde, &mmDCRX_PHY_MACRO_CNTL_RESERVED346[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED346)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED346[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED347", REG_MMIO, 0x5bdf, &mmDCRX_PHY_MACRO_CNTL_RESERVED347[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED347)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED347[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED348", REG_MMIO, 0x5be0, &mmDCRX_PHY_MACRO_CNTL_RESERVED348[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED348)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED348[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED349", REG_MMIO, 0x5be1, &mmDCRX_PHY_MACRO_CNTL_RESERVED349[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED349)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED349[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED350", REG_MMIO, 0x5be2, &mmDCRX_PHY_MACRO_CNTL_RESERVED350[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED350)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED350[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED351", REG_MMIO, 0x5be3, &mmDCRX_PHY_MACRO_CNTL_RESERVED351[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED351)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED351[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED352", REG_MMIO, 0x5be4, &mmDCRX_PHY_MACRO_CNTL_RESERVED352[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED352)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED352[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED353", REG_MMIO, 0x5be5, &mmDCRX_PHY_MACRO_CNTL_RESERVED353[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED353)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED353[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED354", REG_MMIO, 0x5be6, &mmDCRX_PHY_MACRO_CNTL_RESERVED354[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED354)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED354[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED355", REG_MMIO, 0x5be7, &mmDCRX_PHY_MACRO_CNTL_RESERVED355[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED355)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED355[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED356", REG_MMIO, 0x5be8, &mmDCRX_PHY_MACRO_CNTL_RESERVED356[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED356)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED356[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED357", REG_MMIO, 0x5be9, &mmDCRX_PHY_MACRO_CNTL_RESERVED357[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED357)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED357[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED358", REG_MMIO, 0x5bea, &mmDCRX_PHY_MACRO_CNTL_RESERVED358[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED358)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED358[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED359", REG_MMIO, 0x5beb, &mmDCRX_PHY_MACRO_CNTL_RESERVED359[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED359)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED359[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED360", REG_MMIO, 0x5bec, &mmDCRX_PHY_MACRO_CNTL_RESERVED360[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED360)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED360[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED361", REG_MMIO, 0x5bed, &mmDCRX_PHY_MACRO_CNTL_RESERVED361[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED361)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED361[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED362", REG_MMIO, 0x5bee, &mmDCRX_PHY_MACRO_CNTL_RESERVED362[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED362)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED362[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED363", REG_MMIO, 0x5bef, &mmDCRX_PHY_MACRO_CNTL_RESERVED363[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED363)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED363[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED364", REG_MMIO, 0x5bf0, &mmDCRX_PHY_MACRO_CNTL_RESERVED364[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED364)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED364[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED365", REG_MMIO, 0x5bf1, &mmDCRX_PHY_MACRO_CNTL_RESERVED365[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED365)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED365[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED366", REG_MMIO, 0x5bf2, &mmDCRX_PHY_MACRO_CNTL_RESERVED366[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED366)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED366[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED367", REG_MMIO, 0x5bf3, &mmDCRX_PHY_MACRO_CNTL_RESERVED367[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED367)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED367[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED368", REG_MMIO, 0x5bf4, &mmDCRX_PHY_MACRO_CNTL_RESERVED368[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED368)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED368[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED369", REG_MMIO, 0x5bf5, &mmDCRX_PHY_MACRO_CNTL_RESERVED369[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED369)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED369[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED370", REG_MMIO, 0x5bf6, &mmDCRX_PHY_MACRO_CNTL_RESERVED370[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED370)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED370[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED371", REG_MMIO, 0x5bf7, &mmDCRX_PHY_MACRO_CNTL_RESERVED371[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED371)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED371[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED372", REG_MMIO, 0x5bf8, &mmDCRX_PHY_MACRO_CNTL_RESERVED372[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED372)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED372[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED373", REG_MMIO, 0x5bf9, &mmDCRX_PHY_MACRO_CNTL_RESERVED373[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED373)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED373[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED374", REG_MMIO, 0x5bfa, &mmDCRX_PHY_MACRO_CNTL_RESERVED374[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED374)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED374[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED375", REG_MMIO, 0x5bfb, &mmDCRX_PHY_MACRO_CNTL_RESERVED375[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED375)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED375[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED376", REG_MMIO, 0x5bfc, &mmDCRX_PHY_MACRO_CNTL_RESERVED376[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED376)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED376[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED377", REG_MMIO, 0x5bfd, &mmDCRX_PHY_MACRO_CNTL_RESERVED377[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED377)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED377[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED378", REG_MMIO, 0x5bfe, &mmDCRX_PHY_MACRO_CNTL_RESERVED378[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED378)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED378[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED379", REG_MMIO, 0x5bff, &mmDCRX_PHY_MACRO_CNTL_RESERVED379[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED379)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED379[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x5c, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_CONTROL", REG_MMIO, 0x5c00, NULL, 0, 0, 0 },
+	{ "mmAUX_CONTROL", REG_MMIO, 0x5c00, &mmAUX_CONTROL[0], sizeof(mmAUX_CONTROL)/sizeof(mmAUX_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_CONTROL", REG_MMIO, 0x5c01, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_CONTROL", REG_MMIO, 0x5c01, &mmAUX_SW_CONTROL[0], sizeof(mmAUX_SW_CONTROL)/sizeof(mmAUX_SW_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_ARB_CONTROL", REG_MMIO, 0x5c02, NULL, 0, 0, 0 },
+	{ "mmAUX_ARB_CONTROL", REG_MMIO, 0x5c02, &mmAUX_ARB_CONTROL[0], sizeof(mmAUX_ARB_CONTROL)/sizeof(mmAUX_ARB_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c03, NULL, 0, 0, 0 },
+	{ "mmAUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c03, &mmAUX_INTERRUPT_CONTROL[0], sizeof(mmAUX_INTERRUPT_CONTROL)/sizeof(mmAUX_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_STATUS", REG_MMIO, 0x5c04, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_STATUS", REG_MMIO, 0x5c04, &mmAUX_SW_STATUS[0], sizeof(mmAUX_SW_STATUS)/sizeof(mmAUX_SW_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_LS_STATUS", REG_MMIO, 0x5c05, NULL, 0, 0, 0 },
+	{ "mmAUX_LS_STATUS", REG_MMIO, 0x5c05, &mmAUX_LS_STATUS[0], sizeof(mmAUX_LS_STATUS)/sizeof(mmAUX_LS_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_DATA", REG_MMIO, 0x5c06, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_DATA", REG_MMIO, 0x5c06, &mmAUX_SW_DATA[0], sizeof(mmAUX_SW_DATA)/sizeof(mmAUX_SW_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_LS_DATA", REG_MMIO, 0x5c07, NULL, 0, 0, 0 },
+	{ "mmAUX_LS_DATA", REG_MMIO, 0x5c07, &mmAUX_LS_DATA[0], sizeof(mmAUX_LS_DATA)/sizeof(mmAUX_LS_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c08, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c08, &mmAUX_DPHY_TX_REF_CONTROL[0], sizeof(mmAUX_DPHY_TX_REF_CONTROL)/sizeof(mmAUX_DPHY_TX_REF_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c09, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c09, &mmAUX_DPHY_TX_CONTROL[0], sizeof(mmAUX_DPHY_TX_CONTROL)/sizeof(mmAUX_DPHY_TX_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c0a, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c0a, &mmAUX_DPHY_RX_CONTROL0[0], sizeof(mmAUX_DPHY_RX_CONTROL0)/sizeof(mmAUX_DPHY_RX_CONTROL0[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c0b, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c0b, &mmAUX_DPHY_RX_CONTROL1[0], sizeof(mmAUX_DPHY_RX_CONTROL1)/sizeof(mmAUX_DPHY_RX_CONTROL1[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c0c, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_STATUS", REG_MMIO, 0x5c0c, &mmAUX_DPHY_TX_STATUS[0], sizeof(mmAUX_DPHY_TX_STATUS)/sizeof(mmAUX_DPHY_TX_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c0d, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_STATUS", REG_MMIO, 0x5c0d, &mmAUX_DPHY_RX_STATUS[0], sizeof(mmAUX_DPHY_RX_STATUS)/sizeof(mmAUX_DPHY_RX_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c0e, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c0e, &mmAUX_GTC_SYNC_CONTROL[0], sizeof(mmAUX_GTC_SYNC_CONTROL)/sizeof(mmAUX_GTC_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c0f, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c0f, &mmAUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmAUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmAUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c10, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c10, &mmAUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmAUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmAUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c11, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c11, &mmAUX_GTC_SYNC_STATUS[0], sizeof(mmAUX_GTC_SYNC_STATUS)/sizeof(mmAUX_GTC_SYNC_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c12, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_DATA", REG_MMIO, 0x5c12, &mmAUX_GTC_SYNC_DATA[0], sizeof(mmAUX_GTC_SYNC_DATA)/sizeof(mmAUX_GTC_SYNC_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c13, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c13, &mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[0], sizeof(mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE)/sizeof(mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c14, NULL, 0, 0, 0 },
+	{ "mmAUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c14, &mmAUX_TEST_DEBUG_INDEX[0], sizeof(mmAUX_TEST_DEBUG_INDEX)/sizeof(mmAUX_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c15, NULL, 0, 0, 0 },
+	{ "mmAUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c15, &mmAUX_TEST_DEBUG_DATA[0], sizeof(mmAUX_TEST_DEBUG_DATA)/sizeof(mmAUX_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP_AUX1_AUX_CONTROL", REG_MMIO, 0x5c1c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_CONTROL", REG_MMIO, 0x5c1d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_ARB_CONTROL", REG_MMIO, 0x5c1e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c1f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_STATUS", REG_MMIO, 0x5c20, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_STATUS", REG_MMIO, 0x5c21, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_DATA", REG_MMIO, 0x5c22, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_DATA", REG_MMIO, 0x5c23, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c24, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c25, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c26, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c27, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c28, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c29, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c2a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c2b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c2c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c2d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c2e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c2f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c30, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c31, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_CONTROL", REG_MMIO, 0x5c38, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_CONTROL", REG_MMIO, 0x5c39, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_ARB_CONTROL", REG_MMIO, 0x5c3a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c3b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_STATUS", REG_MMIO, 0x5c3c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_STATUS", REG_MMIO, 0x5c3d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_DATA", REG_MMIO, 0x5c3e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_DATA", REG_MMIO, 0x5c3f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c40, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c41, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c42, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c43, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c44, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c45, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c46, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c47, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c48, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c49, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c4a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c4b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c4c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c4d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_CONTROL", REG_MMIO, 0x5c54, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_CONTROL", REG_MMIO, 0x5c55, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_ARB_CONTROL", REG_MMIO, 0x5c56, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c57, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_STATUS", REG_MMIO, 0x5c58, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_STATUS", REG_MMIO, 0x5c59, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_DATA", REG_MMIO, 0x5c5a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_DATA", REG_MMIO, 0x5c5b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c5c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c5d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c5e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c5f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c60, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c61, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c62, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c63, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c64, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c65, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c66, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c67, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c68, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c69, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_CONTROL", REG_MMIO, 0x5c70, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_CONTROL", REG_MMIO, 0x5c71, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_ARB_CONTROL", REG_MMIO, 0x5c72, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c73, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_STATUS", REG_MMIO, 0x5c74, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_STATUS", REG_MMIO, 0x5c75, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_DATA", REG_MMIO, 0x5c76, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_DATA", REG_MMIO, 0x5c77, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c78, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c79, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c7a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c7b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c7c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c7d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c7e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c7f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c80, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c81, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c82, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c83, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c84, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c85, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_CONTROL", REG_MMIO, 0x5c8c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_CONTROL", REG_MMIO, 0x5c8d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_ARB_CONTROL", REG_MMIO, 0x5c8e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c8f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_STATUS", REG_MMIO, 0x5c90, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_STATUS", REG_MMIO, 0x5c91, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_DATA", REG_MMIO, 0x5c92, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_DATA", REG_MMIO, 0x5c93, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c94, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c95, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c96, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c97, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c98, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c99, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x5c9a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c9b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c9c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c9d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_DATA", REG_MMIO, 0x5c9e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x5c9f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5ca0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5ca1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x5d, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5d98, &mmDPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED0)/sizeof(mmDPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5d99, &mmDPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED1)/sizeof(mmDPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5d9a, &mmDPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED2)/sizeof(mmDPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5d9b, &mmDPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED3)/sizeof(mmDPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5d9c, &mmDPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED4)/sizeof(mmDPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5d9d, &mmDPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED5)/sizeof(mmDPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5d9e, &mmDPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED6)/sizeof(mmDPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5d9f, &mmDPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED7)/sizeof(mmDPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5da0, &mmDPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED8)/sizeof(mmDPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5da1, &mmDPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED9)/sizeof(mmDPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5da2, &mmDPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED10)/sizeof(mmDPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5da3, &mmDPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED11)/sizeof(mmDPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x5da4, &mmDPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED12)/sizeof(mmDPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x5da5, &mmDPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED13)/sizeof(mmDPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x5da6, &mmDPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED14)/sizeof(mmDPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x5da7, &mmDPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED15)/sizeof(mmDPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x5da8, &mmDPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED16)/sizeof(mmDPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x5da9, &mmDPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED17)/sizeof(mmDPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x5daa, &mmDPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED18)/sizeof(mmDPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x5dab, &mmDPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED19)/sizeof(mmDPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x5dac, &mmDPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED20)/sizeof(mmDPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x5dad, &mmDPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED21)/sizeof(mmDPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x5dae, &mmDPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED22)/sizeof(mmDPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x5daf, &mmDPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED23)/sizeof(mmDPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x5db0, &mmDPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED24)/sizeof(mmDPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x5db1, &mmDPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED25)/sizeof(mmDPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x5db2, &mmDPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED26)/sizeof(mmDPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x5db3, &mmDPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED27)/sizeof(mmDPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x5db4, &mmDPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED28)/sizeof(mmDPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x5db5, &mmDPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED29)/sizeof(mmDPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x5db6, &mmDPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED30)/sizeof(mmDPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x5db7, &mmDPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED31)/sizeof(mmDPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x5db8, &mmDPHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED32)/sizeof(mmDPHY_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x5db9, &mmDPHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED33)/sizeof(mmDPHY_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x5dba, &mmDPHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED34)/sizeof(mmDPHY_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x5dbb, &mmDPHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED35)/sizeof(mmDPHY_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x5dbc, &mmDPHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED36)/sizeof(mmDPHY_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x5dbd, &mmDPHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED37)/sizeof(mmDPHY_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x5dbe, &mmDPHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED38)/sizeof(mmDPHY_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x5dbf, &mmDPHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED39)/sizeof(mmDPHY_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x5dc0, &mmDPHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED40)/sizeof(mmDPHY_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x5dc1, &mmDPHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED41)/sizeof(mmDPHY_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x5dc2, &mmDPHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED42)/sizeof(mmDPHY_MACRO_CNTL_RESERVED42[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x5dc3, &mmDPHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED43)/sizeof(mmDPHY_MACRO_CNTL_RESERVED43[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x5dc4, &mmDPHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED44)/sizeof(mmDPHY_MACRO_CNTL_RESERVED44[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x5dc5, &mmDPHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED45)/sizeof(mmDPHY_MACRO_CNTL_RESERVED45[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x5dc6, &mmDPHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED46)/sizeof(mmDPHY_MACRO_CNTL_RESERVED46[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x5dc7, &mmDPHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED47)/sizeof(mmDPHY_MACRO_CNTL_RESERVED47[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x5dc8, &mmDPHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED48)/sizeof(mmDPHY_MACRO_CNTL_RESERVED48[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x5dc9, &mmDPHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED49)/sizeof(mmDPHY_MACRO_CNTL_RESERVED49[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x5dca, &mmDPHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED50)/sizeof(mmDPHY_MACRO_CNTL_RESERVED50[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x5dcb, &mmDPHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED51)/sizeof(mmDPHY_MACRO_CNTL_RESERVED51[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x5dcc, &mmDPHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED52)/sizeof(mmDPHY_MACRO_CNTL_RESERVED52[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x5dcd, &mmDPHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED53)/sizeof(mmDPHY_MACRO_CNTL_RESERVED53[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x5dce, &mmDPHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED54)/sizeof(mmDPHY_MACRO_CNTL_RESERVED54[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x5dcf, &mmDPHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED55)/sizeof(mmDPHY_MACRO_CNTL_RESERVED55[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x5dd0, &mmDPHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED56)/sizeof(mmDPHY_MACRO_CNTL_RESERVED56[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x5dd1, &mmDPHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED57)/sizeof(mmDPHY_MACRO_CNTL_RESERVED57[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x5dd2, &mmDPHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED58)/sizeof(mmDPHY_MACRO_CNTL_RESERVED58[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x5dd3, &mmDPHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED59)/sizeof(mmDPHY_MACRO_CNTL_RESERVED59[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x5dd4, &mmDPHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED60)/sizeof(mmDPHY_MACRO_CNTL_RESERVED60[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x5dd5, &mmDPHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED61)/sizeof(mmDPHY_MACRO_CNTL_RESERVED61[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x5dd6, &mmDPHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED62)/sizeof(mmDPHY_MACRO_CNTL_RESERVED62[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x5dd7, &mmDPHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED63)/sizeof(mmDPHY_MACRO_CNTL_RESERVED63[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x5e, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "mmWB_ENABLE", REG_MMIO, 0x5e18, &mmWB_ENABLE[0], sizeof(mmWB_ENABLE)/sizeof(mmWB_ENABLE[0]), 0, 0 },
+	{ "mmWB_EC_CONFIG", REG_MMIO, 0x5e19, &mmWB_EC_CONFIG[0], sizeof(mmWB_EC_CONFIG)/sizeof(mmWB_EC_CONFIG[0]), 0, 0 },
+	{ "mmCNV_MODE", REG_MMIO, 0x5e1a, &mmCNV_MODE[0], sizeof(mmCNV_MODE)/sizeof(mmCNV_MODE[0]), 0, 0 },
+	{ "mmCNV_WINDOW_START", REG_MMIO, 0x5e1b, &mmCNV_WINDOW_START[0], sizeof(mmCNV_WINDOW_START)/sizeof(mmCNV_WINDOW_START[0]), 0, 0 },
+	{ "mmCNV_WINDOW_SIZE", REG_MMIO, 0x5e1c, &mmCNV_WINDOW_SIZE[0], sizeof(mmCNV_WINDOW_SIZE)/sizeof(mmCNV_WINDOW_SIZE[0]), 0, 0 },
+	{ "mmCNV_UPDATE", REG_MMIO, 0x5e1d, &mmCNV_UPDATE[0], sizeof(mmCNV_UPDATE)/sizeof(mmCNV_UPDATE[0]), 0, 0 },
+	{ "mmCNV_SOURCE_SIZE", REG_MMIO, 0x5e1e, &mmCNV_SOURCE_SIZE[0], sizeof(mmCNV_SOURCE_SIZE)/sizeof(mmCNV_SOURCE_SIZE[0]), 0, 0 },
+	{ "mmCNV_CSC_CONTROL", REG_MMIO, 0x5e1f, &mmCNV_CSC_CONTROL[0], sizeof(mmCNV_CSC_CONTROL)/sizeof(mmCNV_CSC_CONTROL[0]), 0, 0 },
+	{ "mmCNV_CSC_C11_C12", REG_MMIO, 0x5e20, &mmCNV_CSC_C11_C12[0], sizeof(mmCNV_CSC_C11_C12)/sizeof(mmCNV_CSC_C11_C12[0]), 0, 0 },
+	{ "mmCNV_CSC_C13_C14", REG_MMIO, 0x5e21, &mmCNV_CSC_C13_C14[0], sizeof(mmCNV_CSC_C13_C14)/sizeof(mmCNV_CSC_C13_C14[0]), 0, 0 },
+	{ "mmCNV_CSC_C21_C22", REG_MMIO, 0x5e22, &mmCNV_CSC_C21_C22[0], sizeof(mmCNV_CSC_C21_C22)/sizeof(mmCNV_CSC_C21_C22[0]), 0, 0 },
+	{ "mmCNV_CSC_C23_C24", REG_MMIO, 0x5e23, &mmCNV_CSC_C23_C24[0], sizeof(mmCNV_CSC_C23_C24)/sizeof(mmCNV_CSC_C23_C24[0]), 0, 0 },
+	{ "mmCNV_CSC_C31_C32", REG_MMIO, 0x5e24, &mmCNV_CSC_C31_C32[0], sizeof(mmCNV_CSC_C31_C32)/sizeof(mmCNV_CSC_C31_C32[0]), 0, 0 },
+	{ "mmCNV_CSC_C33_C34", REG_MMIO, 0x5e25, &mmCNV_CSC_C33_C34[0], sizeof(mmCNV_CSC_C33_C34)/sizeof(mmCNV_CSC_C33_C34[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_R", REG_MMIO, 0x5e26, &mmCNV_CSC_ROUND_OFFSET_R[0], sizeof(mmCNV_CSC_ROUND_OFFSET_R)/sizeof(mmCNV_CSC_ROUND_OFFSET_R[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_G", REG_MMIO, 0x5e27, &mmCNV_CSC_ROUND_OFFSET_G[0], sizeof(mmCNV_CSC_ROUND_OFFSET_G)/sizeof(mmCNV_CSC_ROUND_OFFSET_G[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_B", REG_MMIO, 0x5e28, &mmCNV_CSC_ROUND_OFFSET_B[0], sizeof(mmCNV_CSC_ROUND_OFFSET_B)/sizeof(mmCNV_CSC_ROUND_OFFSET_B[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_R", REG_MMIO, 0x5e29, &mmCNV_CSC_CLAMP_R[0], sizeof(mmCNV_CSC_CLAMP_R)/sizeof(mmCNV_CSC_CLAMP_R[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_G", REG_MMIO, 0x5e2a, &mmCNV_CSC_CLAMP_G[0], sizeof(mmCNV_CSC_CLAMP_G)/sizeof(mmCNV_CSC_CLAMP_G[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_B", REG_MMIO, 0x5e2b, &mmCNV_CSC_CLAMP_B[0], sizeof(mmCNV_CSC_CLAMP_B)/sizeof(mmCNV_CSC_CLAMP_B[0]), 0, 0 },
+	{ "mmCNV_TEST_CNTL", REG_MMIO, 0x5e2c, &mmCNV_TEST_CNTL[0], sizeof(mmCNV_TEST_CNTL)/sizeof(mmCNV_TEST_CNTL[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_RED", REG_MMIO, 0x5e2d, &mmCNV_TEST_CRC_RED[0], sizeof(mmCNV_TEST_CRC_RED)/sizeof(mmCNV_TEST_CRC_RED[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_GREEN", REG_MMIO, 0x5e2e, &mmCNV_TEST_CRC_GREEN[0], sizeof(mmCNV_TEST_CRC_GREEN)/sizeof(mmCNV_TEST_CRC_GREEN[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_BLUE", REG_MMIO, 0x5e2f, &mmCNV_TEST_CRC_BLUE[0], sizeof(mmCNV_TEST_CRC_BLUE)/sizeof(mmCNV_TEST_CRC_BLUE[0]), 0, 0 },
+	{ "mmWB_DEBUG_CTRL", REG_MMIO, 0x5e30, &mmWB_DEBUG_CTRL[0], sizeof(mmWB_DEBUG_CTRL)/sizeof(mmWB_DEBUG_CTRL[0]), 0, 0 },
+	{ "mmWB_DBG_MODE", REG_MMIO, 0x5e31, &mmWB_DBG_MODE[0], sizeof(mmWB_DBG_MODE)/sizeof(mmWB_DBG_MODE[0]), 0, 0 },
+	{ "mmWB_HW_DEBUG", REG_MMIO, 0x5e32, &mmWB_HW_DEBUG[0], sizeof(mmWB_HW_DEBUG)/sizeof(mmWB_HW_DEBUG[0]), 0, 0 },
+	{ "mmCNV_INPUT_SELECT", REG_MMIO, 0x5e33, &mmCNV_INPUT_SELECT[0], sizeof(mmCNV_INPUT_SELECT)/sizeof(mmCNV_INPUT_SELECT[0]), 0, 0 },
+	{ "mmCNV_TEST_DEBUG_INDEX", REG_MMIO, 0x5e34, &mmCNV_TEST_DEBUG_INDEX[0], sizeof(mmCNV_TEST_DEBUG_INDEX)/sizeof(mmCNV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCNV_TEST_DEBUG_DATA", REG_MMIO, 0x5e35, &mmCNV_TEST_DEBUG_DATA[0], sizeof(mmCNV_TEST_DEBUG_DATA)/sizeof(mmCNV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmWB_SOFT_RESET", REG_MMIO, 0x5e36, &mmWB_SOFT_RESET[0], sizeof(mmWB_SOFT_RESET)/sizeof(mmWB_SOFT_RESET[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x5f, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "mmDC_PERFMON11_PERFCOUNTER_CNTL", REG_MMIO, 0x5f68, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFCOUNTER_STATE", REG_MMIO, 0x5f69, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x5f6a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CNTL", REG_MMIO, 0x5f6b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CVALUE_LOW", REG_MMIO, 0x5f6c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_HI", REG_MMIO, 0x5f6d, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_LOW", REG_MMIO, 0x5f6e, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x5f6f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x5f70, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CNTL2", REG_MMIO, 0x5f72, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fd0, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fd0, &mmCPLL_MACRO_CNTL_RESERVED0[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED0)/sizeof(mmCPLL_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fd1, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fd1, &mmCPLL_MACRO_CNTL_RESERVED1[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED1)/sizeof(mmCPLL_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fd2, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fd2, &mmCPLL_MACRO_CNTL_RESERVED2[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED2)/sizeof(mmCPLL_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fd3, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fd3, &mmCPLL_MACRO_CNTL_RESERVED3[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED3)/sizeof(mmCPLL_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fd4, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fd4, &mmCPLL_MACRO_CNTL_RESERVED4[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED4)/sizeof(mmCPLL_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fd5, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fd5, &mmCPLL_MACRO_CNTL_RESERVED5[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED5)/sizeof(mmCPLL_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fd6, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fd6, &mmCPLL_MACRO_CNTL_RESERVED6[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED6)/sizeof(mmCPLL_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fd7, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fd7, &mmCPLL_MACRO_CNTL_RESERVED7[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED7)/sizeof(mmCPLL_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fd8, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fd8, &mmCPLL_MACRO_CNTL_RESERVED8[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED8)/sizeof(mmCPLL_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fd9, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fd9, &mmCPLL_MACRO_CNTL_RESERVED9[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED9)/sizeof(mmCPLL_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fda, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fda, &mmCPLL_MACRO_CNTL_RESERVED10[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED10)/sizeof(mmCPLL_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fdb, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fdb, &mmCPLL_MACRO_CNTL_RESERVED11[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED11)/sizeof(mmCPLL_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fdc, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fdd, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fde, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fdf, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fe0, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fe1, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fe2, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fe3, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fe4, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fe5, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fe6, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fe7, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fe8, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fe9, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fea, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5feb, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fec, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fed, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fee, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fef, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5ff0, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5ff1, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5ff2, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5ff3, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5ff4, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5ff5, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5ff6, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5ff7, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5ff8, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5ff9, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5ffa, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5ffb, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5ffc, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5ffd, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5ffe, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_PAYLOAD_CAPABILITY", REG_MMIO, 0x6, &mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[0], sizeof(mmOUTPUT_STREAM_PAYLOAD_CAPABILITY)/sizeof(mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmINPUT_STREAM_PAYLOAD_CAPABILITY", REG_MMIO, 0x6, &mmINPUT_STREAM_PAYLOAD_CAPABILITY[0], sizeof(mmINPUT_STREAM_PAYLOAD_CAPABILITY)/sizeof(mmINPUT_STREAM_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL6", REG_SMC, 0x6, &ixAZALIA_INPUT_CRC0_CHANNEL6[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL6)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL6[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL6", REG_SMC, 0x6, &ixAZALIA_CRC0_CHANNEL6[0], sizeof(ixAZALIA_CRC0_CHANNEL6)/sizeof(ixAZALIA_CRC0_CHANNEL6[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR5", REG_SMC, 0x6, &ixAUDIO_DESCRIPTOR5[0], sizeof(ixAUDIO_DESCRIPTOR5)/sizeof(ixAUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "ixDPGV0_DEBUG00", REG_SMC, 0x6, NULL, 0, 0, 0 },
+	{ "ixDCIO_DEBUG6", REG_SMC, 0x6, &ixDCIO_DEBUG6[0], sizeof(ixDCIO_DEBUG6)/sizeof(ixDCIO_DEBUG6[0]), 0, 0 },
+	{ "ixATTR06", REG_SMC, 0x6, &ixATTR06[0], sizeof(ixATTR06)/sizeof(ixATTR06[0]), 0, 0 },
+	{ "ixCRT06", REG_SMC, 0x6, &ixCRT06[0], sizeof(ixCRT06)/sizeof(ixCRT06[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x60, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x61, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x62, &ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x6200, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x63, &ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x64, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x64, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x65, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x65, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x66, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x66, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x67, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x67, &ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x6706, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x670d, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x68, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x68, &ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x69, &ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x6a, &ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 },
+	{ "ixDPGV1_DEBUG00_DMIFARB", REG_SMC, 0x6a, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x6b, &ixAZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 },
+	{ "ixDPGV1_DEBUG01_DMIFARB", REG_SMC, 0x6b, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x6c, &ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 },
+	{ "ixDPGV1_DEBUG02_DMIFARB", REG_SMC, 0x6c, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x6d, &ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 },
+	{ "ixDPGV1_DEBUG03_DMIFARB", REG_SMC, 0x6d, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x6e, &ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 },
+	{ "ixDPGV1_DEBUG04_DMIFARB", REG_SMC, 0x6e, NULL, 0, 0, 0 },
+	{ "ixDPGV1_DEBUG00", REG_SMC, 0x6f, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x6f09, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6f0a, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x6f0b, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x7, &ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL7", REG_SMC, 0x7, &ixAZALIA_INPUT_CRC0_CHANNEL7[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL7)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL7[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL7", REG_SMC, 0x7, &ixAZALIA_CRC0_CHANNEL7[0], sizeof(ixAZALIA_CRC0_CHANNEL7)/sizeof(ixAZALIA_CRC0_CHANNEL7[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR6", REG_SMC, 0x7, &ixAUDIO_DESCRIPTOR6[0], sizeof(ixAUDIO_DESCRIPTOR6)/sizeof(ixAUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "ixDPGV0_DEBUG01", REG_SMC, 0x7, NULL, 0, 0, 0 },
+	{ "ixDCIO_DEBUG7", REG_SMC, 0x7, &ixDCIO_DEBUG7[0], sizeof(ixDCIO_DEBUG7)/sizeof(ixDCIO_DEBUG7[0]), 0, 0 },
+	{ "ixATTR07", REG_SMC, 0x7, &ixATTR07[0], sizeof(ixATTR07)/sizeof(ixATTR07[0]), 0, 0 },
+	{ "ixCRT07", REG_SMC, 0x7, &ixCRT07[0], sizeof(ixCRT07)/sizeof(ixCRT07[0]), 0, 0 },
+	{ "ixDPGV1_DEBUG01", REG_SMC, 0x70, NULL, 0, 0, 0 },
+	{ "ixDPGV1_DEBUG02", REG_SMC, 0x71, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x7707, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x7708, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x7709, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x771c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x771d, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x771e, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x771f, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x7771, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE", REG_SMC, 0x7777, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE", REG_SMC, 0x7778, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE", REG_SMC, 0x7779, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE", REG_SMC, 0x777a, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR", REG_SMC, 0x777c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x7785, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x7786, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x7787, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x7788, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x7798, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x7799, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x779a, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x779b, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x779c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L", REG_SMC, 0x779d, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H", REG_SMC, 0x779e, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[0]), 0, 0 },
+	{ "ixVGADCC_DBG_DCCIF_C", REG_SMC, 0x7e, &ixVGADCC_DBG_DCCIF_C[0], sizeof(ixVGADCC_DBG_DCCIF_C)/sizeof(ixVGADCC_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x7f09, &ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x7f0c, &ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x8, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "mmINTERRUPT_CONTROL", REG_MMIO, 0x8, &mmINTERRUPT_CONTROL[0], sizeof(mmINTERRUPT_CONTROL)/sizeof(mmINTERRUPT_CONTROL[0]), 0, 0 },
+	{ "ixDPGV0_DEBUG02", REG_SMC, 0x8, NULL, 0, 0, 0 },
+	{ "ixDCIO_DEBUG8", REG_SMC, 0x8, &ixDCIO_DEBUG8[0], sizeof(ixDCIO_DEBUG8)/sizeof(ixDCIO_DEBUG8[0]), 0, 0 },
+	{ "ixATTR08", REG_SMC, 0x8, &ixATTR08[0], sizeof(ixATTR08)/sizeof(ixATTR08[0]), 0, 0 },
+	{ "ixCRT08", REG_SMC, 0x8, &ixCRT08[0], sizeof(ixCRT08)/sizeof(ixCRT08[0]), 0, 0 },
+	{ "mmWALL_CLOCK_COUNTER_ALIAS", REG_MMIO, 0x80c, &mmWALL_CLOCK_COUNTER_ALIAS[0], sizeof(mmWALL_CLOCK_COUNTER_ALIAS)/sizeof(mmWALL_CLOCK_COUNTER_ALIAS[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x821, &mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x9, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 },
+	{ "ixIDDCCIF02_DBG_DCCIF_C", REG_SMC, 0x9, &ixIDDCCIF02_DBG_DCCIF_C[0], sizeof(ixIDDCCIF02_DBG_DCCIF_C)/sizeof(ixIDDCCIF02_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR8", REG_SMC, 0x9, &ixAUDIO_DESCRIPTOR8[0], sizeof(ixAUDIO_DESCRIPTOR8)/sizeof(ixAUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "mmINTERRUPT_STATUS", REG_MMIO, 0x9, &mmINTERRUPT_STATUS[0], sizeof(mmINTERRUPT_STATUS)/sizeof(mmINTERRUPT_STATUS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG9", REG_SMC, 0x9, &ixDCIO_DEBUG9[0], sizeof(ixDCIO_DEBUG9)/sizeof(ixDCIO_DEBUG9[0]), 0, 0 },
+	{ "ixATTR09", REG_SMC, 0x9, &ixATTR09[0], sizeof(ixATTR09)/sizeof(ixATTR09[0]), 0, 0 },
+	{ "ixCRT09", REG_SMC, 0x9, &ixCRT09[0], sizeof(ixCRT09)/sizeof(ixCRT09[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG", REG_SMC, 0xa, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[0]), 0, 0 },
+	{ "ixDMIF_DEBUG02_CORE1", REG_SMC, 0xa, &ixDMIF_DEBUG02_CORE1[0], sizeof(ixDMIF_DEBUG02_CORE1)/sizeof(ixDMIF_DEBUG02_CORE1[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR9", REG_SMC, 0xa, &ixAUDIO_DESCRIPTOR9[0], sizeof(ixAUDIO_DESCRIPTOR9)/sizeof(ixAUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "ixDCIO_DEBUGA", REG_SMC, 0xa, &ixDCIO_DEBUGA[0], sizeof(ixDCIO_DEBUGA)/sizeof(ixDCIO_DEBUGA[0]), 0, 0 },
+	{ "ixATTR0A", REG_SMC, 0xa, &ixATTR0A[0], sizeof(ixATTR0A)/sizeof(ixATTR0A[0]), 0, 0 },
+	{ "ixCRT0A", REG_SMC, 0xa, &ixCRT0A[0], sizeof(ixCRT0A)/sizeof(ixCRT0A[0]), 0, 0 },
+	{ "ixIDDCCIF04_DBG_DCCIF_E", REG_SMC, 0xb, &ixIDDCCIF04_DBG_DCCIF_E[0], sizeof(ixIDDCCIF04_DBG_DCCIF_E)/sizeof(ixIDDCCIF04_DBG_DCCIF_E[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR10", REG_SMC, 0xb, &ixAUDIO_DESCRIPTOR10[0], sizeof(ixAUDIO_DESCRIPTOR10)/sizeof(ixAUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION6", REG_SMC, 0xb, &ixSINK_DESCRIPTION6[0], sizeof(ixSINK_DESCRIPTION6)/sizeof(ixSINK_DESCRIPTION6[0]), 0, 0 },
+	{ "ixDCIO_DEBUGB", REG_SMC, 0xb, &ixDCIO_DEBUGB[0], sizeof(ixDCIO_DEBUGB)/sizeof(ixDCIO_DEBUGB[0]), 0, 0 },
+	{ "ixATTR0B", REG_SMC, 0xb, &ixATTR0B[0], sizeof(ixATTR0B)/sizeof(ixATTR0B[0]), 0, 0 },
+	{ "ixCRT0B", REG_SMC, 0xb, &ixCRT0B[0], sizeof(ixCRT0B)/sizeof(ixCRT0B[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0xc, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 },
+	{ "ixIDDCCIF05_DBG_DCCIF_F", REG_SMC, 0xc, &ixIDDCCIF05_DBG_DCCIF_F[0], sizeof(ixIDDCCIF05_DBG_DCCIF_F)/sizeof(ixIDDCCIF05_DBG_DCCIF_F[0]), 0, 0 },
+	{ "mmWALL_CLOCK_COUNTER", REG_MMIO, 0xc, &mmWALL_CLOCK_COUNTER[0], sizeof(mmWALL_CLOCK_COUNTER)/sizeof(mmWALL_CLOCK_COUNTER[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION7", REG_SMC, 0xc, &ixSINK_DESCRIPTION7[0], sizeof(ixSINK_DESCRIPTION7)/sizeof(ixSINK_DESCRIPTION7[0]), 0, 0 },
+	{ "ixMVP_DEBUG_12", REG_SMC, 0xc, &ixMVP_DEBUG_12[0], sizeof(ixMVP_DEBUG_12)/sizeof(ixMVP_DEBUG_12[0]), 0, 0 },
+	{ "ixDCIO_DEBUGC", REG_SMC, 0xc, &ixDCIO_DEBUGC[0], sizeof(ixDCIO_DEBUGC)/sizeof(ixDCIO_DEBUGC[0]), 0, 0 },
+	{ "ixATTR0C", REG_SMC, 0xc, &ixATTR0C[0], sizeof(ixATTR0C)/sizeof(ixATTR0C[0]), 0, 0 },
+	{ "ixCRT0C", REG_SMC, 0xc, &ixCRT0C[0], sizeof(ixCRT0C)/sizeof(ixCRT0C[0]), 0, 0 },
+	{ "mmVGA_RENDER_CONTROL", REG_MMIO, 0xc0, &mmVGA_RENDER_CONTROL[0], sizeof(mmVGA_RENDER_CONTROL)/sizeof(mmVGA_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SEQUENCER_RESET_CONTROL", REG_MMIO, 0xc1, &mmVGA_SEQUENCER_RESET_CONTROL[0], sizeof(mmVGA_SEQUENCER_RESET_CONTROL)/sizeof(mmVGA_SEQUENCER_RESET_CONTROL[0]), 0, 0 },
+	{ "mmVGA_MODE_CONTROL", REG_MMIO, 0xc2, &mmVGA_MODE_CONTROL[0], sizeof(mmVGA_MODE_CONTROL)/sizeof(mmVGA_MODE_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SURFACE_PITCH_SELECT", REG_MMIO, 0xc3, &mmVGA_SURFACE_PITCH_SELECT[0], sizeof(mmVGA_SURFACE_PITCH_SELECT)/sizeof(mmVGA_SURFACE_PITCH_SELECT[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS", REG_MMIO, 0xc4, &mmVGA_MEMORY_BASE_ADDRESS[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS)/sizeof(mmVGA_MEMORY_BASE_ADDRESS[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_INDEX", REG_MMIO, 0xc5, &mmVGA_TEST_DEBUG_INDEX[0], sizeof(mmVGA_TEST_DEBUG_INDEX)/sizeof(mmVGA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmVGA_DISPBUF1_SURFACE_ADDR", REG_MMIO, 0xc6, &mmVGA_DISPBUF1_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF1_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF1_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_DATA", REG_MMIO, 0xc7, &mmVGA_TEST_DEBUG_DATA[0], sizeof(mmVGA_TEST_DEBUG_DATA)/sizeof(mmVGA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGA_DISPBUF2_SURFACE_ADDR", REG_MMIO, 0xc8, &mmVGA_DISPBUF2_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF2_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF2_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS_HIGH", REG_MMIO, 0xc9, &mmVGA_MEMORY_BASE_ADDRESS_HIGH[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH)/sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmVGA_HDP_CONTROL", REG_MMIO, 0xca, &mmVGA_HDP_CONTROL[0], sizeof(mmVGA_HDP_CONTROL)/sizeof(mmVGA_HDP_CONTROL[0]), 0, 0 },
+	{ "mmVGA_CACHE_CONTROL", REG_MMIO, 0xcb, &mmVGA_CACHE_CONTROL[0], sizeof(mmVGA_CACHE_CONTROL)/sizeof(mmVGA_CACHE_CONTROL[0]), 0, 0 },
+	{ "mmD1VGA_CONTROL", REG_MMIO, 0xcc, &mmD1VGA_CONTROL[0], sizeof(mmD1VGA_CONTROL)/sizeof(mmD1VGA_CONTROL[0]), 0, 0 },
+	{ "mmD2VGA_CONTROL", REG_MMIO, 0xce, &mmD2VGA_CONTROL[0], sizeof(mmD2VGA_CONTROL)/sizeof(mmD2VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_HW_DEBUG", REG_MMIO, 0xcf, &mmVGA_HW_DEBUG[0], sizeof(mmVGA_HW_DEBUG)/sizeof(mmVGA_HW_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0xd, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR12", REG_SMC, 0xd, &ixAUDIO_DESCRIPTOR12[0], sizeof(ixAUDIO_DESCRIPTOR12)/sizeof(ixAUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION8", REG_SMC, 0xd, &ixSINK_DESCRIPTION8[0], sizeof(ixSINK_DESCRIPTION8)/sizeof(ixSINK_DESCRIPTION8[0]), 0, 0 },
+	{ "ixMVP_DEBUG_13", REG_SMC, 0xd, &ixMVP_DEBUG_13[0], sizeof(ixMVP_DEBUG_13)/sizeof(ixMVP_DEBUG_13[0]), 0, 0 },
+	{ "ixDCIO_DEBUGD", REG_SMC, 0xd, &ixDCIO_DEBUGD[0], sizeof(ixDCIO_DEBUGD)/sizeof(ixDCIO_DEBUGD[0]), 0, 0 },
+	{ "ixATTR0D", REG_SMC, 0xd, &ixATTR0D[0], sizeof(ixATTR0D)/sizeof(ixATTR0D[0]), 0, 0 },
+	{ "ixCRT0D", REG_SMC, 0xd, &ixCRT0D[0], sizeof(ixCRT0D)/sizeof(ixCRT0D[0]), 0, 0 },
+	{ "mmVGA_STATUS", REG_MMIO, 0xd0, &mmVGA_STATUS[0], sizeof(mmVGA_STATUS)/sizeof(mmVGA_STATUS[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_CONTROL", REG_MMIO, 0xd1, &mmVGA_INTERRUPT_CONTROL[0], sizeof(mmVGA_INTERRUPT_CONTROL)/sizeof(mmVGA_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmVGA_STATUS_CLEAR", REG_MMIO, 0xd2, &mmVGA_STATUS_CLEAR[0], sizeof(mmVGA_STATUS_CLEAR)/sizeof(mmVGA_STATUS_CLEAR[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_STATUS", REG_MMIO, 0xd3, &mmVGA_INTERRUPT_STATUS[0], sizeof(mmVGA_INTERRUPT_STATUS)/sizeof(mmVGA_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmVGA_MAIN_CONTROL", REG_MMIO, 0xd4, &mmVGA_MAIN_CONTROL[0], sizeof(mmVGA_MAIN_CONTROL)/sizeof(mmVGA_MAIN_CONTROL[0]), 0, 0 },
+	{ "mmVGA_TEST_CONTROL", REG_MMIO, 0xd5, &mmVGA_TEST_CONTROL[0], sizeof(mmVGA_TEST_CONTROL)/sizeof(mmVGA_TEST_CONTROL[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_INDEX", REG_MMIO, 0xd6, &mmVGA_DEBUG_READBACK_INDEX[0], sizeof(mmVGA_DEBUG_READBACK_INDEX)/sizeof(mmVGA_DEBUG_READBACK_INDEX[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_DATA", REG_MMIO, 0xd7, &mmVGA_DEBUG_READBACK_DATA[0], sizeof(mmVGA_DEBUG_READBACK_DATA)/sizeof(mmVGA_DEBUG_READBACK_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0xe, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 },
+	{ "mmSTREAM_SYNCHRONIZATION", REG_MMIO, 0xe, &mmSTREAM_SYNCHRONIZATION[0], sizeof(mmSTREAM_SYNCHRONIZATION)/sizeof(mmSTREAM_SYNCHRONIZATION[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR13", REG_SMC, 0xe, &ixAUDIO_DESCRIPTOR13[0], sizeof(ixAUDIO_DESCRIPTOR13)/sizeof(ixAUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION9", REG_SMC, 0xe, &ixSINK_DESCRIPTION9[0], sizeof(ixSINK_DESCRIPTION9)/sizeof(ixSINK_DESCRIPTION9[0]), 0, 0 },
+	{ "ixMVP_DEBUG_14", REG_SMC, 0xe, &ixMVP_DEBUG_14[0], sizeof(ixMVP_DEBUG_14)/sizeof(ixMVP_DEBUG_14[0]), 0, 0 },
+	{ "ixDCIO_DEBUGE", REG_SMC, 0xe, &ixDCIO_DEBUGE[0], sizeof(ixDCIO_DEBUGE)/sizeof(ixDCIO_DEBUGE[0]), 0, 0 },
+	{ "ixATTR0E", REG_SMC, 0xe, &ixATTR0E[0], sizeof(ixATTR0E)/sizeof(ixATTR0E[0]), 0, 0 },
+	{ "ixCRT0E", REG_SMC, 0xe, &ixCRT0E[0], sizeof(ixCRT0E)/sizeof(ixCRT0E[0]), 0, 0 },
+	{ "mmVGA0_CRTC8_DATA", REG_MMIO, 0xed, NULL, 0, 0, 0 },
+	{ "mmVGA0_CRTC8_IDX", REG_MMIO, 0xed, NULL, 0, 0, 0 },
+	{ "mmCRTC8_DATA", REG_MMIO, 0xed, &mmCRTC8_DATA[0], sizeof(mmCRTC8_DATA)/sizeof(mmCRTC8_DATA[0]), 0, 0 },
+	{ "mmCRTC8_IDX", REG_MMIO, 0xed, &mmCRTC8_IDX[0], sizeof(mmCRTC8_IDX)/sizeof(mmCRTC8_IDX[0]), 0, 0 },
+	{ "mmVGA0_GENFC_WT", REG_MMIO, 0xee, NULL, 0, 0, 0 },
+	{ "mmVGA0_GENS1", REG_MMIO, 0xee, NULL, 0, 0, 0 },
+	{ "mmGENFC_WT", REG_MMIO, 0xee, &mmGENFC_WT[0], sizeof(mmGENFC_WT)/sizeof(mmGENFC_WT[0]), 0, 0 },
+	{ "mmGENS1", REG_MMIO, 0xee, &mmGENS1[0], sizeof(mmGENS1)/sizeof(mmGENS1[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION10", REG_SMC, 0xf, &ixSINK_DESCRIPTION10[0], sizeof(ixSINK_DESCRIPTION10)/sizeof(ixSINK_DESCRIPTION10[0]), 0, 0 },
+	{ "ixMVP_DEBUG_15", REG_SMC, 0xf, &ixMVP_DEBUG_15[0], sizeof(ixMVP_DEBUG_15)/sizeof(ixMVP_DEBUG_15[0]), 0, 0 },
+	{ "ixDCIO_DEBUGF", REG_SMC, 0xf, &ixDCIO_DEBUGF[0], sizeof(ixDCIO_DEBUGF)/sizeof(ixDCIO_DEBUGF[0]), 0, 0 },
+	{ "ixATTR0F", REG_SMC, 0xf, &ixATTR0F[0], sizeof(ixATTR0F)/sizeof(ixATTR0F[0]), 0, 0 },
+	{ "ixCRT0F", REG_SMC, 0xf, &ixCRT0F[0], sizeof(ixCRT0F)/sizeof(ixCRT0F[0]), 0, 0 },
+	{ "mmGENMO_WT", REG_MMIO, 0xf0, &mmGENMO_WT[0], sizeof(mmGENMO_WT)/sizeof(mmGENMO_WT[0]), 0, 0 },
+	{ "mmGENENB", REG_MMIO, 0xf0, &mmGENENB[0], sizeof(mmGENENB)/sizeof(mmGENENB[0]), 0, 0 },
+	{ "mmGENS0", REG_MMIO, 0xf0, &mmGENS0[0], sizeof(mmGENS0)/sizeof(mmGENS0[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_SMC, 0xf00, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID", REG_SMC, 0xf02, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0xf04, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "mmDAC_R_INDEX", REG_MMIO, 0xf1, &mmDAC_R_INDEX[0], sizeof(mmDAC_R_INDEX)/sizeof(mmDAC_R_INDEX[0]), 0, 0 },
+	{ "mmSEQ8_DATA", REG_MMIO, 0xf1, &mmSEQ8_DATA[0], sizeof(mmSEQ8_DATA)/sizeof(mmSEQ8_DATA[0]), 0, 0 },
+	{ "mmDAC_MASK", REG_MMIO, 0xf1, &mmDAC_MASK[0], sizeof(mmDAC_MASK)/sizeof(mmDAC_MASK[0]), 0, 0 },
+	{ "mmDAC_W_INDEX", REG_MMIO, 0xf2, &mmDAC_W_INDEX[0], sizeof(mmDAC_W_INDEX)/sizeof(mmDAC_W_INDEX[0]), 0, 0 },
+	{ "mmGENFC_RD", REG_MMIO, 0xf2, &mmGENFC_RD[0], sizeof(mmGENFC_RD)/sizeof(mmGENFC_RD[0]), 0, 0 },
+	{ "mmGRPH8_DATA", REG_MMIO, 0xf3, &mmGRPH8_DATA[0], sizeof(mmGRPH8_DATA)/sizeof(mmGRPH8_DATA[0]), 0, 0 },
+	{ "mmGRPH8_IDX", REG_MMIO, 0xf3, &mmGRPH8_IDX[0], sizeof(mmGRPH8_IDX)/sizeof(mmGRPH8_IDX[0]), 0, 0 },
+	{ "mmGENMO_RD", REG_MMIO, 0xf3, &mmGENMO_RD[0], sizeof(mmGENMO_RD)/sizeof(mmGENMO_RD[0]), 0, 0 },
+	{ "mmVGA1_CRTC8_DATA", REG_MMIO, 0xf5, NULL, 0, 0, 0 },
+	{ "mmVGA1_CRTC8_IDX", REG_MMIO, 0xf5, NULL, 0, 0, 0 },
+	{ "mmVGA1_GENFC_WT", REG_MMIO, 0xf6, NULL, 0, 0, 0 },
+	{ "mmVGA1_GENS1", REG_MMIO, 0xf6, NULL, 0, 0, 0 },
+	{ "mmD3VGA_CONTROL", REG_MMIO, 0xf8, &mmD3VGA_CONTROL[0], sizeof(mmD3VGA_CONTROL)/sizeof(mmD3VGA_CONTROL[0]), 0, 0 },
+	{ "mmD4VGA_CONTROL", REG_MMIO, 0xf9, &mmD4VGA_CONTROL[0], sizeof(mmD4VGA_CONTROL)/sizeof(mmD4VGA_CONTROL[0]), 0, 0 },
+	{ "mmD5VGA_CONTROL", REG_MMIO, 0xfa, &mmD5VGA_CONTROL[0], sizeof(mmD5VGA_CONTROL)/sizeof(mmD5VGA_CONTROL[0]), 0, 0 },
+	{ "mmD6VGA_CONTROL", REG_MMIO, 0xfb, &mmD6VGA_CONTROL[0], sizeof(mmD6VGA_CONTROL)/sizeof(mmD6VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SOURCE_SELECT", REG_MMIO, 0xfc, &mmVGA_SOURCE_SELECT[0], sizeof(mmVGA_SOURCE_SELECT)/sizeof(mmVGA_SOURCE_SELECT[0]), 0, 0 },
diff --git a/src/lib/ip/dce112.c b/src/lib/ip/dce112.c
new file mode 100644
index 0000000..181b425
--- /dev/null
+++ b/src/lib/ip/dce112.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "dce112_bits.i"
+
+static const struct umr_reg dce112_registers[] = {
+#include "dce112_regs.i"
+};
+
+struct umr_ip_block *umr_create_dce112(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "dce112";
+	ip->no_regs = sizeof(dce112_registers)/sizeof(dce112_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(dce112_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, dce112_registers, sizeof(dce112_registers));
+	return ip;
+}
diff --git a/src/lib/ip/dce112_bits.i b/src/lib/ip/dce112_bits.i
new file mode 100644
index 0000000..db00e91
--- /dev/null
+++ b/src/lib/ip/dce112_bits.i
@@ -0,0 +1,15075 @@
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[] = {
+	 { "AZALIA_INPUT_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[] = {
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL0[] = {
+	 { "INPUT_CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_FIFO_SIZE_CONTROL[] = {
+	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
+	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
+	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL0[] = {
+	 { "CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_CAPABILITIES[] = {
+	 { "SIXTY_FOUR_BIT_ADDRESS_SUPPORTED", 0, 0, &umr_bitfield_default },
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+	 { "NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED", 3, 7, &umr_bitfield_default },
+	 { "NUMBER_OF_INPUT_STREAMS_SUPPORTED", 8, 11, &umr_bitfield_default },
+	 { "NUMBER_OF_OUTPUT_STREAMS_SUPPORTED", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG_ID[] = {
+	 { "DCIO_DEBUG_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG_ID[] = {
+	 { "FMT_DEBUG_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR00[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ00[] = {
+	 { "SEQ_RST0B", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RST1B", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[] = {
+	 { "PRODUCT_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_LATENCY_COUNTER_CONTROL[] = {
+	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL1[] = {
+	 { "INPUT_CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_PAYLOAD_CAPABILITY[] = {
+	 { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL1[] = {
+	 { "CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR0[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1[] = {
+	 { "DCO_DCIO_MVP_DVOCNTL_A0_REG", 0, 1, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_MASK_REG", 2, 3, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_EN_REG", 4, 5, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_A0", 6, 7, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_SEL0", 8, 9, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCNTL_EN", 10, 11, &umr_bitfield_default },
+	 { "DCO_DCIO_MVP_DVOCLK_C", 12, 12, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0_REG", 13, 13, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0_PREMUX", 14, 14, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_A0", 15, 15, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN_REG", 16, 16, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_HSYNC_TRISTATE", 17, 17, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_CLK_TRISTATE", 18, 18, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN_PREMUX", 19, 19, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_EN", 20, 20, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_MUX", 21, 21, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_MASK_REG", 22, 22, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_VSYNC_TRISTATE", 24, 24, &umr_bitfield_default },
+	 { "DCO_DCIO_DVO_RATE_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_SEL0_PREMUX", 26, 26, &umr_bitfield_default },
+	 { "DCO_DCIO_DVOCNTL1_SEL0", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG0[] = {
+	 { "FMT_DEBUG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR01[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ01[] = {
+	 { "SEQ_DOT8", 0, 0, &umr_bitfield_default },
+	 { "SEQ_SHIFT2", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PCLKBY2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_SHIFT4", 4, 4, &umr_bitfield_default },
+	 { "SEQ_MAXBW", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_LOWER_BASE_ADDRESS[] = {
+	 { "CORB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "CORB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION11[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_A[] = {
+	 { "DP_AUX_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG10[] = {
+	 { "DCIO_DIGC_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR10[] = {
+	 { "ATTR_GRPH_MODE", 0, 0, &umr_bitfield_default },
+	 { "ATTR_MONO_EN", 1, 1, &umr_bitfield_default },
+	 { "ATTR_LGRPH_EN", 2, 2, &umr_bitfield_default },
+	 { "ATTR_BLINK_EN", 3, 3, &umr_bitfield_default },
+	 { "ATTR_PANTOPONLY", 5, 5, &umr_bitfield_default },
+	 { "ATTR_PCLKBY2", 6, 6, &umr_bitfield_default },
+	 { "ATTR_CSEL_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT10[] = {
+	 { "V_SYNC_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHYPLLA_PIXCLK_RESYNC_CNTL[] = {
+	 { "PHYPLLA_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PHYPLLA_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PHYPLLA_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHYPLLB_PIXCLK_RESYNC_CNTL[] = {
+	 { "PHYPLLB_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PHYPLLB_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PHYPLLB_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "PHYPLLB_PIXCLK_DOUBLE_RATE_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHYPLLC_PIXCLK_RESYNC_CNTL[] = {
+	 { "PHYPLLC_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PHYPLLC_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PHYPLLC_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "PHYPLLC_PIXCLK_DOUBLE_RATE_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHYPLLD_PIXCLK_RESYNC_CNTL[] = {
+	 { "PHYPLLD_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PHYPLLD_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PHYPLLD_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "PHYPLLD_PIXCLK_DOUBLE_RATE_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPREFCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "DPREFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DPREFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREFCLK_CNTL[] = {
+	 { "REFCLK_CLOCK_EN", 0, 0, &umr_bitfield_default },
+	 { "REFCLK_SRC_SEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREFCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "REFCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REFCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHYPLLE_PIXCLK_RESYNC_CNTL[] = {
+	 { "PHYPLLE_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PHYPLLE_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PHYPLLE_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "PHYPLLE_PIXCLK_DOUBLE_RATE_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_CLK_FORCE_CONTROL[] = {
+	 { "DPDBG_CLK_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "DPDBG_CLK_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_PERFMON_CNTL2[] = {
+	 { "DCCG_PERF_DSICLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERF_REFCLK_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK1_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK2_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERF_UNIPHYC_PIXCLK_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERF_UNIPHYD_PIXCLK_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERF_UNIPHYE_PIXCLK_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERF_UNIPHYF_PIXCLK_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERF_UNIPHYG_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_UPPER_BASE_ADDRESS[] = {
+	 { "CORB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION12[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_B[] = {
+	 { "DP_AUX_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG11[] = {
+	 { "DCIO_DIGD_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR11[] = {
+	 { "ATTR_OVSC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT11[] = {
+	 { "V_SYNC_END", 0, 3, &umr_bitfield_default },
+	 { "V_INTR_CLR", 4, 4, &umr_bitfield_default },
+	 { "V_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "SEL5_REFRESH_CYC", 6, 6, &umr_bitfield_default },
+	 { "C0T7_WR_ONLY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CBUS_WRCMD_DELAY[] = {
+	 { "CBUS_PLL_WRCMD_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DEBUG_CNTL[] = {
+	 { "DCCG_DS_DEBUG_COUNT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_VALUE", 4, 12, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT_SRC_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DTO_INCR[] = {
+	 { "DCCG_DS_DTO_INCR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DTO_MODULO[] = {
+	 { "DCCG_DS_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_CNTL[] = {
+	 { "DCCG_DS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DS_REF_SRC", 4, 5, &umr_bitfield_default },
+	 { "DCCG_DS_HW_CAL_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DCCG_DS_ENABLED_STATUS", 9, 9, &umr_bitfield_default },
+	 { "DCCG_DS_XTALIN_RATE_DIV", 16, 17, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_REMOVE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DCCG_DS_DELAY_XTAL_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_HW_CAL_INTERVAL[] = {
+	 { "DCCG_DS_HW_CAL_INTERVAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPREFCLK_CNTL[] = {
+	 { "DPREFCLK_SRC_SEL", 0, 2, &umr_bitfield_default },
+	 { "UNB_DB_CLK_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCE_VERSION[] = {
+	 { "MAJOR_VERSION", 0, 7, &umr_bitfield_default },
+	 { "MINOR_VERSION", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEM_WRITE_PAGE_ADDR[] = {
+	 { "VGA_MEM_WRITE_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
+	 { "VGA_MEM_WRITE_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_WRITE_POINTER[] = {
+	 { "CORB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_READ_POINTER[] = {
+	 { "CORB_READ_POINTER", 0, 7, &umr_bitfield_default },
+	 { "CORB_READ_POINTER_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_C[] = {
+	 { "DP_AUX_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG12[] = {
+	 { "DCIO_DIGE_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR12[] = {
+	 { "ATTR_MAP_EN", 0, 3, &umr_bitfield_default },
+	 { "ATTR_VSMUX", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT12[] = {
+	 { "V_DISP_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CNTL[] = {
+	 { "DCCG_GTC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_INCR[] = {
+	 { "DCCG_GTC_DTO_INCR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_MODULO[] = {
+	 { "DCCG_GTC_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CURRENT[] = {
+	 { "DCCG_GTC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENTIST_DISPCLK_CNTL[] = {
+	 { "DENTIST_DISPCLK_WDIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_RDIVIDER", 8, 14, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_MODE", 15, 16, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHGTOG", 17, 17, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_DONETOG", 18, 18, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_DONE", 19, 19, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHG_DONE", 20, 20, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHGTOG", 21, 21, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_DONETOG", 22, 22, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_WDIVIDER", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CLK_ENABLE[] = {
+	 { "DACA_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DACB_CLK_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CLK_ENABLE[] = {
+	 { "DVO_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_WRITE[] = {
+	 { "AVSYNC_COUNTER_WRVALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_CONTROL[] = {
+	 { "AVSYNC_COUNTER_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_SMU_INTERRUPT_CNTL[] = {
+	 { "DMCU_SMU_STATIC_SCREEN_INT", 0, 0, &umr_bitfield_default },
+	 { "DMCU_SMU_STATIC_SCREEN_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_CONTROL[] = {
+	 { "DISPLAY0_FORCE_VBI", 0, 0, &umr_bitfield_default },
+	 { "DISPLAY1_FORCE_VBI", 1, 1, &umr_bitfield_default },
+	 { "DISPLAY2_FORCE_VBI", 2, 2, &umr_bitfield_default },
+	 { "DISPLAY3_FORCE_VBI", 3, 3, &umr_bitfield_default },
+	 { "DISPLAY4_FORCE_VBI", 4, 4, &umr_bitfield_default },
+	 { "DISPLAY5_FORCE_VBI", 5, 5, &umr_bitfield_default },
+	 { "DISPLAY_V0_FORCE_VBI", 6, 6, &umr_bitfield_default },
+	 { "DISPLAY_V1_FORCE_VBI", 7, 7, &umr_bitfield_default },
+	 { "MCIF_WB_FORCE_VBI", 8, 8, &umr_bitfield_default },
+	 { "SMU_DC_INT_CLEAR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_INTERRUPT_CONTROL[] = {
+	 { "DC_SMU_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DC_SMU_INT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DC_SMU_INT_EVENT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAVSYNC_COUNTER_READ[] = {
+	 { "AVSYNC_COUNTER_RDVALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEM_READ_PAGE_ADDR[] = {
+	 { "VGA_MEM_READ_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
+	 { "VGA_MEM_READ_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION14[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_D[] = {
+	 { "DP_AUX_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG13[] = {
+	 { "DCIO_DIGF_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_STATUS[] = {
+	 { "CORB_MEMORY_ERROR_INDICATION", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_SIZE[] = {
+	 { "CORB_SIZE", 0, 1, &umr_bitfield_default },
+	 { "CORB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR13[] = {
+	 { "ATTR_PPAN", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT13[] = {
+	 { "DISP_PITCH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMILLISECOND_TIME_BASE_DIV[] = {
+	 { "MILLISECOND_TIME_BASE_DIV", 0, 16, &umr_bitfield_default },
+	 { "MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_FREQ_CHANGE_CNTL[] = {
+	 { "DISPCLK_STEP_DELAY", 0, 13, &umr_bitfield_default },
+	 { "DISPCLK_STEP_SIZE", 16, 19, &umr_bitfield_default },
+	 { "DISPCLK_FREQ_RAMP_DONE", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_MAX_ERRDET_CYCLES", 25, 27, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_RESET", 28, 28, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_STATE", 29, 29, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_OVR_EN", 30, 30, &umr_bitfield_default },
+	 { "DISPCLK_CHG_FWD_CORR_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_MEM_GLOBAL_PWR_REQ_CNTL[] = {
+	 { "DC_MEM_GLOBAL_PWR_REQ_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_PERFMON_CNTL[] = {
+	 { "DCCG_PERF_DISPCLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERF_DPREFCLK_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERF_UNIPHYA_PIXCLK_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERF_UNIPHYB_PIXCLK_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERF_RUN", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_VSYNC", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_HSYNC", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERF_CRTC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCCG_PERF_XTALIN_PULSE_DIV", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL[] = {
+	 { "DISPCLK_DCCG_GATE_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_R_DCCG_GATE_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "SCLK_GATE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "DPREFCLK_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "DACACLK_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "DACBCLK_GATE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DVOACLK_GATE_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "DPDBG_CLK_GATE_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "DPREFCLK_R_DCCG_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "AOMCLK0_GATE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "AOMCLK1_GATE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "AOMCLK2_GATE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "AUDIO_DTO2_CLK_GATE_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "DPREFCLK_GTC_GATE_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "UNB_DB_CLK_GATE_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "REFCLK_GATE_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "REFCLK_R_DIG_GATE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "DSICLK_GATE_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "BYTECLK_GATE_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "ESCCLK_GATE_DISABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "DISPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DISPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_SCLK_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CAC_STATUS[] = {
+	 { "CAC_STATUS_RDDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK0_RESYNC_CNTL[] = {
+	 { "PIXCLK0_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL0", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMICROSECOND_TIME_BASE_DIV[] = {
+	 { "MICROSECOND_TIME_BASE_DIV", 0, 6, &umr_bitfield_default },
+	 { "XTAL_REF_DIV", 8, 14, &umr_bitfield_default },
+	 { "XTAL_REF_SEL", 16, 16, &umr_bitfield_default },
+	 { "XTAL_REF_CLOCK_SOURCE_SEL", 17, 17, &umr_bitfield_default },
+	 { "MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL2[] = {
+	 { "SYMCLKA_FE_GATE_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_GATE_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "SYMCLKC_FE_GATE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "SYMCLKD_FE_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "SYMCLKE_FE_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_GATE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "SYMCLKG_FE_GATE_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "SYMCLKLPA_FE_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SYMCLKLPB_FE_GATE_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "SYMCLKA_GATE_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "SYMCLKB_GATE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "SYMCLKC_GATE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "SYMCLKD_GATE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "SYMCLKE_GATE_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "SYMCLKF_GATE_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "SYMCLKG_GATE_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "SYMCLKLPA_GATE_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "SYMCLKLPB_GATE_DISABLE", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "SYMCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SYMCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHYPLLF_PIXCLK_RESYNC_CNTL[] = {
+	 { "PHYPLLF_PIXCLK_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PHYPLLF_DCCG_DEEP_COLOR_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PHYPLLF_PIXCLK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DISP_CNTL_REG[] = {
+	 { "ALLOW_SR_ON_TRANS_REQ", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_LOWER_BASE_ADDRESS[] = {
+	 { "RIRB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "RIRB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION15[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_E[] = {
+	 { "DP_AUX_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG14[] = {
+	 { "DCIO_DIGG_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR14[] = {
+	 { "ATTR_CSEL1", 0, 1, &umr_bitfield_default },
+	 { "ATTR_CSEL2", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT14[] = {
+	 { "UNDRLN_LOC", 0, 4, &umr_bitfield_default },
+	 { "ADDR_CNT_BY4", 5, 5, &umr_bitfield_default },
+	 { "DOUBLE_WORD", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC0_PIXEL_RATE_CNTL[] = {
+	 { "CRTC0_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO0_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC0_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC0_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_HALF_RATE_EN", 11, 11, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_PHASE[] = {
+	 { "DP_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_MODULO[] = {
+	 { "DP_DTO0_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC0_PHYPLL_PIXEL_RATE_CNTL[] = {
+	 { "CRTC0_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
+	 { "CRTC0_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC1_PIXEL_RATE_CNTL[] = {
+	 { "CRTC1_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO1_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO1_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_HALF_RATE_EN", 11, 11, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_PHASE[] = {
+	 { "DP_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_MODULO[] = {
+	 { "DP_DTO1_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC1_PHYPLL_PIXEL_RATE_CNTL[] = {
+	 { "CRTC1_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
+	 { "CRTC1_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC2_PIXEL_RATE_CNTL[] = {
+	 { "CRTC2_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO2_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO2_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_HALF_RATE_EN", 11, 11, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_PHASE[] = {
+	 { "DP_DTO2_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_MODULO[] = {
+	 { "DP_DTO2_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC2_PHYPLL_PIXEL_RATE_CNTL[] = {
+	 { "CRTC2_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
+	 { "CRTC2_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC3_PIXEL_RATE_CNTL[] = {
+	 { "CRTC3_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO3_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO3_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_HALF_RATE_EN", 11, 11, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_PHASE[] = {
+	 { "DP_DTO3_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_MODULO[] = {
+	 { "DP_DTO3_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC3_PHYPLL_PIXEL_RATE_CNTL[] = {
+	 { "CRTC3_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
+	 { "CRTC3_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_UPPER_BASE_ADDRESS[] = {
+	 { "RIRB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION16[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_F[] = {
+	 { "DP_AUX_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG15[] = {
+	 { "DCIO_DEBUG15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT15[] = {
+	 { "V_BLANK_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC4_PIXEL_RATE_CNTL[] = {
+	 { "CRTC4_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO4_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO4_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_HALF_RATE_EN", 11, 11, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_PHASE[] = {
+	 { "DP_DTO4_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_MODULO[] = {
+	 { "DP_DTO4_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC4_PHYPLL_PIXEL_RATE_CNTL[] = {
+	 { "CRTC4_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
+	 { "CRTC4_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC5_PIXEL_RATE_CNTL[] = {
+	 { "CRTC5_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO5_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO5_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_HALF_RATE_EN", 11, 11, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_PHASE[] = {
+	 { "DP_DTO5_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_MODULO[] = {
+	 { "DP_DTO5_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC5_PHYPLL_PIXEL_RATE_CNTL[] = {
+	 { "CRTC5_PHYPLL_PIXEL_RATE_SOURCE", 0, 2, &umr_bitfield_default },
+	 { "CRTC5_PIXEL_RATE_PLL_SOURCE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CBUS_ANTIGLITCH_RESETB[] = {
+	 { "P0PLL_CBUS_ANTIGLITCH_RESETB", 0, 0, &umr_bitfield_default },
+	 { "P1PLL_CBUS_ANTIGLITCH_RESETB", 1, 1, &umr_bitfield_default },
+	 { "P2PLL_CBUS_ANTIGLITCH_RESETB", 2, 2, &umr_bitfield_default },
+	 { "P3PLL_CBUS_ANTIGLITCH_RESETB", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CBUS_SPARE[] = {
+	 { "P0PLL_CBUS_SPARE", 0, 7, &umr_bitfield_default },
+	 { "P1PLL_CBUS_SPARE", 8, 15, &umr_bitfield_default },
+	 { "P2PLL_CBUS_SPARE", 16, 23, &umr_bitfield_default },
+	 { "P3PLL_CBUS_SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_SOFT_RESET[] = {
+	 { "REFCLK_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "PCIE_REFCLK_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SOFT_RESET_DVO", 2, 2, &umr_bitfield_default },
+	 { "DVO_ENABLE_RST", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_DTO2_CLK_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DPREFCLK_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "AMCLK0_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "AMCLK1_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "P0PLL_CFG_IF_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "P1PLL_CFG_IF_SOFT_RESET", 15, 15, &umr_bitfield_default },
+	 { "P2PLL_CFG_IF_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "A0PLL_CFG_IF_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "A1PLL_CFG_IF_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "C0PLL_CFG_IF_SOFT_RESET", 19, 19, &umr_bitfield_default },
+	 { "C1PLL_CFG_IF_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "C2PLL_CFG_IF_SOFT_RESET", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRESPONSE_INTERRUPT_COUNT[] = {
+	 { "N_RESPONSE_INTERRUPT_COUNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_WRITE_POINTER[] = {
+	 { "RIRB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
+	 { "RIRB_WRITE_POINTER_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_G[] = {
+	 { "DP_AUX_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG16[] = {
+	 { "DCIO_DEBUG16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT16[] = {
+	 { "V_BLANK_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKA_CLOCK_ENABLE[] = {
+	 { "SYMCLKA_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_CTRL[] = {
+	 { "RESET_UC", 0, 0, &umr_bitfield_default },
+	 { "IGNORE_PWRMGT", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_IRQ_TO_UC", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_XIRQ_TO_UC", 3, 3, &umr_bitfield_default },
+	 { "DMCU_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DMCU_DYN_CLK_GATING_EN", 8, 8, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_STATUS[] = {
+	 { "UC_IN_RESET", 0, 0, &umr_bitfield_default },
+	 { "UC_IN_WAIT_MODE", 1, 1, &umr_bitfield_default },
+	 { "UC_IN_STOP_MODE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PC_START_ADDR[] = {
+	 { "PC_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "PC_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_START_ADDR[] = {
+	 { "FW_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_END_ADDR[] = {
+	 { "FW_END_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_END_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_ISR_START_ADDR[] = {
+	 { "FW_ISR_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_ISR_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_HI[] = {
+	 { "FW_CHECKSUM_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_LO[] = {
+	 { "FW_CHECKSUM_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_RAM_ACCESS_CTRL[] = {
+	 { "ERAM_WR_ADDR_AUTO_INC", 0, 0, &umr_bitfield_default },
+	 { "ERAM_RD_ADDR_AUTO_INC", 1, 1, &umr_bitfield_default },
+	 { "IRAM_WR_ADDR_AUTO_INC", 2, 2, &umr_bitfield_default },
+	 { "IRAM_RD_ADDR_AUTO_INC", 3, 3, &umr_bitfield_default },
+	 { "ERAM_HOST_ACCESS_EN", 4, 4, &umr_bitfield_default },
+	 { "IRAM_HOST_ACCESS_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_CTRL[] = {
+	 { "ERAM_WR_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_WR_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_WR_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_DATA[] = {
+	 { "ERAM_WR_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_CTRL[] = {
+	 { "ERAM_RD_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_RD_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_RD_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_DATA[] = {
+	 { "ERAM_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_CTRL[] = {
+	 { "IRAM_WR_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_DATA[] = {
+	 { "IRAM_WR_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_CTRL[] = {
+	 { "IRAM_RD_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKB_CLOCK_ENABLE[] = {
+	 { "SYMCLKB_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_DATA[] = {
+	 { "IRAM_RD_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_EVENT_TRIGGER[] = {
+	 { "GEN_SW_INT_TO_UC", 0, 0, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CODE", 16, 22, &umr_bitfield_default },
+	 { "GEN_UC_INTERNAL_INT_TO_HOST", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_INTERNAL_INT_STATUS[] = {
+	 { "UC_INT_IRQ_N_PIN", 0, 0, &umr_bitfield_default },
+	 { "UC_INT_XIRQ_N_PIN", 1, 1, &umr_bitfield_default },
+	 { "UC_INT_SOFTWARE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "UC_INT_ILLEGAL_OPCODE_TRAP", 3, 3, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_4", 4, 4, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_3", 5, 5, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_2", 6, 6, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_1", 7, 7, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "UC_INT_REAL_TIME_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5", 10, 10, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_3", 11, 11, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_2", 12, 12, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_1", 13, 13, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE", 14, 14, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_OVERFLOW", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_SS_INTERRUPT_CNTL_STATUS[] = {
+	 { "STATIC_SCREEN1_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_STATUS", 21, 21, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_STATUS[] = {
+	 { "ABM1_HG_READY_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "SCP_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "VBLANK1_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "VBLANK2_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "VBLANK3_INT_CLEAR", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_OCCURRED", 27, 27, &umr_bitfield_default },
+	 { "VBLANK4_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_OCCURRED", 28, 28, &umr_bitfield_default },
+	 { "VBLANK5_INT_CLEAR", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_OCCURRED", 29, 29, &umr_bitfield_default },
+	 { "VBLANK6_INT_CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_HOST_EN_MASK[] = {
+	 { "ABM1_HG_READY_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "SCP_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_MASK", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK[] = {
+	 { "ABM1_HG_READY_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_TO_UC_EN", 29, 29, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_TO_UC_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[] = {
+	 { "ABM1_HG_READY_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_UP_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCPG_IHC_DSI_POWER_DOWN_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_XIRQ_IRQ_SEL", 29, 29, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_XIRQ_IRQ_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DMCU_SCRATCH[] = {
+	 { "DMCU_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INT_CNT[] = {
+	 { "DMCU_ABM1_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default },
+	 { "DMCU_ABM1_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default },
+	 { "DMCU_ABM1_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[] = {
+	 { "DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS", 0, 1, &umr_bitfield_default },
+	 { "DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_CLK_GATING_CNTL[] = {
+	 { "UC_IRAM_RD_DELAY", 0, 2, &umr_bitfield_default },
+	 { "UC_ERAM_RD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "UC_RBBM_RD_CLK_GATING_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG1[] = {
+	 { "MASTER_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG2[] = {
+	 { "MASTER_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG3[] = {
+	 { "MASTER_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CMD_REG[] = {
+	 { "MASTER_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKC_CLOCK_ENABLE[] = {
+	 { "SYMCLKC_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CNTL_REG[] = {
+	 { "MASTER_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG1[] = {
+	 { "SLAVE_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG2[] = {
+	 { "SLAVE_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG3[] = {
+	 { "SLAVE_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CMD_REG[] = {
+	 { "SLAVE_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CNTL_REG[] = {
+	 { "SLAVE_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "COMM_PORT_MSG_TO_HOST_IN_PROGRESS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_INDEX[] = {
+	 { "DMCU_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMCU_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_DATA[] = {
+	 { "DMCU_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_AMBIENT_LIGHT_LEVEL[] = {
+	 { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_USER_LEVEL[] = {
+	 { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_TARGET_ABM_LEVEL[] = {
+	 { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_CURRENT_ABM_LEVEL[] = {
+	 { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_FINAL_DUTY_CYCLE[] = {
+	 { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_MINIMUM_DUTY_CYCLE[] = {
+	 { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_ABM_CNTL[] = {
+	 { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[] = {
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKD_CLOCK_ENABLE[] = {
+	 { "SYMCLKD_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_GRP2_REG_LOCK[] = {
+	 { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[] = {
+	 { "DCPG_IHC_DCFEV0_POWER_UP_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_DOWN_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFEV0_VBLANK_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV1_POWER_UP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV1_POWER_DOWN_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFEV1_VBLANK_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DMCU_GENERIC_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[] = {
+	 { "DCPG_IHC_DCFEV0_POWER_UP_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFEV0_VBLANK_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV1_POWER_UP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFEV1_VBLANK_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DMCU_GENERIC_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_STATUS_1[] = {
+	 { "DCPG_IHC_DCFEV0_POWER_UP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_UP_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV1_POWER_UP_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV1_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_DOWN_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV0_POWER_DOWN_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV1_POWER_DOWN_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFEV1_POWER_DOWN_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFEV0_VBLANK_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFEV0_VBLANK_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFEV1_VBLANK_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFEV1_VBLANK_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DMCU_GENERIC_INTERRUPT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DMCU_GENERIC_INTERRUPT_CLEAR", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_STATUS1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_CLEAR", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_OCCURRED", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_OCCURRED", 28, 28, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
+	 { "DPRX_SD0P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DPRX_SD0P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DPRX_SD0P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DPRX_SD1P0_MSA_RECEIVED_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VBID_VID_STREAM_STATUS_TOGGLED_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT0_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DPRX_SD1P0_VERTICAL_INT1_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DPRX_SD1P0_SDP_RECEIVED_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_BS_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SR_INTERVAL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_SYMBOL_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DISPARITY_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TRAINING_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_TEST_PATTERN_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_ECF_ERROR_THRESH_EXCEEDED_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DETECT_SR_LOCK_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_ALIGN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_LOSS_OF_DESKEW_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_EXCESSIVE_ERROR_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DPRX_DPHY_P0_DESKEW_FIFO_OVERFLOW_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_AUX_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_I2C_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_CPU_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG1_TIMEOUT_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG2_TIMEOUT_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG3_TIMEOUT_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
+	 { "DPRX_AUX_P0_MSG4_TIMEOUT_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_CNTL[] = {
+	 { "ABM1_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default },
+	 { "ABM1_BLANK_MODE_SUPPORT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_IPCSC_COEFF_SEL[] = {
+	 { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_0[] = {
+	 { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_1[] = {
+	 { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_2[] = {
+	 { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_3[] = {
+	 { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_4[] = {
+	 { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_12[] = {
+	 { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKE_CLOCK_ENABLE[] = {
+	 { "SYMCLKE_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_34[] = {
+	 { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default },
+	 { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default },
+	 { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_CNTL_MISC[] = {
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default },
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS5[] = {
+	 { "DCFEV0_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER_OFF_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER_OFF_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER_OFF_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER_OFF_INT_CLEAR", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[] = {
+	 { "DCFEV0_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER0_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER1_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER2_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER3_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER4_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER5_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER6_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER7_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_DEBUG_MISC[] = {
+	 { "ABM1_HG_FORCE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_FORCE_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "ABM1_BL_FORCE_INTERRUPT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HGLS_REG_READ_PROGRESS[] = {
+	 { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_MISC_CTRL[] = {
+	 { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default },
+	 { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default },
+	 { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default },
+	 { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default },
+	 { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default },
+	 { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SUM_OF_LUMA[] = {
+	 { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_PIXEL_COUNT[] = {
+	 { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKF_CLOCK_ENABLE[] = {
+	 { "SYMCLKF_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_OVR_SCAN_BIN[] = {
+	 { "ABM1_LS_OVR_SCAN_BIN", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_SAMPLE_RATE[] = {
+	 { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SAMPLE_RATE[] = {
+	 { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = {
+	 { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_1[] = {
+	 { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_2[] = {
+	 { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_3[] = {
+	 { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_4[] = {
+	 { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_5[] = {
+	 { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_6[] = {
+	 { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_7[] = {
+	 { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_8[] = {
+	 { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_9[] = {
+	 { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_10[] = {
+	 { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_11[] = {
+	 { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_12[] = {
+	 { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_13[] = {
+	 { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_14[] = {
+	 { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_15[] = {
+	 { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_16[] = {
+	 { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_17[] = {
+	 { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_18[] = {
+	 { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_19[] = {
+	 { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_20[] = {
+	 { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_21[] = {
+	 { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_22[] = {
+	 { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_23[] = {
+	 { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_24[] = {
+	 { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[] = {
+	 { "DCFEV0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFEV0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFEV1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[] = {
+	 { "WB_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_OVERSCAN_PIXEL_VALUE[] = {
+	 { "ABM1_OVERSCAN_R_PIXEL_VALUE", 0, 9, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_G_PIXEL_VALUE", 10, 19, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_B_PIXEL_VALUE", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_BL_MASTER_LOCK[] = {
+	 { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_INDEX[] = {
+	 { "ABM_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "ABM_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_DATA[] = {
+	 { "ABM_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_ENABLE[] = {
+	 { "DVO_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DVO_PIXEL_WIDTH", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SOURCE_SELECT[] = {
+	 { "DVO_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DVO_STEREOSYNC_SELECT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_OUTPUT[] = {
+	 { "DVO_OUTPUT_ENABLE_MODE", 0, 1, &umr_bitfield_default },
+	 { "DVO_CLOCK_MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CONTROL[] = {
+	 { "DVO_RATE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "DVO_SDRCLK_SEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_DVPDATA_WIDTH", 4, 5, &umr_bitfield_default },
+	 { "DVO_DUAL_CHANNEL_EN", 8, 8, &umr_bitfield_default },
+	 { "DVO_RESET_FIFO", 16, 16, &umr_bitfield_default },
+	 { "DVO_SYNC_PHASE", 17, 17, &umr_bitfield_default },
+	 { "DVO_INVERT_DVOCLK", 18, 18, &umr_bitfield_default },
+	 { "DVO_HSYNC_POLARITY", 20, 20, &umr_bitfield_default },
+	 { "DVO_VSYNC_POLARITY", 21, 21, &umr_bitfield_default },
+	 { "DVO_DE_POLARITY", 22, 22, &umr_bitfield_default },
+	 { "DVO_COLOR_FORMAT", 24, 25, &umr_bitfield_default },
+	 { "DVO_CTL3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC_EN[] = {
+	 { "DVO_CRC2_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_MASK[] = {
+	 { "DVO_CRC2_SIG_MASK", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_RESULT[] = {
+	 { "DVO_CRC2_SIG_RESULT", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_FIFO_ERROR_STATUS[] = {
+	 { "DVO_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DVO_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DVO_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DVO_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DVO_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DVO_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DVO_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_TEST_DEBUG_INDEX[] = {
+	 { "DVO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DVO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_TEST_DEBUG_DATA[] = {
+	 { "DVO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_ENABLE[] = {
+	 { "DAC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_POINTER_SKEW", 2, 3, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR", 4, 4, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR_ACK", 5, 5, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_TVOUT_SIM", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SOURCE_SELECT[] = {
+	 { "DAC_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DAC_TV_SELECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_EN[] = {
+	 { "DAC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_CONT_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_CONTROL[] = {
+	 { "DAC_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_ONLY_BLANKB", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB_MASK[] = {
+	 { "DAC_CRC_SIG_BLUE_MASK", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN_MASK", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED_MASK", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL_MASK[] = {
+	 { "DAC_CRC_SIG_CONTROL_MASK", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO_SOURCE[] = {
+	 { "DCCG_AUDIO_DTO0_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_SOURCE_SEL", 12, 13, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_CLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_USE_512FBR_DTO", 20, 20, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO0_USE_512FBR_DTO", 24, 24, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO1_USE_512FBR_DTO", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB[] = {
+	 { "DAC_CRC_SIG_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL[] = {
+	 { "DAC_CRC_SIG_CONTROL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SYNC_TRISTATE_CONTROL[] = {
+	 { "DAC_HSYNCA_TRISTATE", 0, 0, &umr_bitfield_default },
+	 { "DAC_VSYNCA_TRISTATE", 8, 8, &umr_bitfield_default },
+	 { "DAC_SYNCA_TRISTATE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_STEREOSYNC_SELECT[] = {
+	 { "DAC_STEREOSYNC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL[] = {
+	 { "DAC_AUTODETECT_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_FRAME_TIME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CHECK_MASK", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL2[] = {
+	 { "DAC_AUTODETECT_POWERUP_COUNTER", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_TESTMODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL3[] = {
+	 { "DAC_AUTODET_COMPARATOR_IN_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODET_COMPARATOR_OUT_DELAY", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_STATUS[] = {
+	 { "DAC_AUTODETECT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CONNECT", 4, 4, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_RED_SENSE", 8, 9, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_GREEN_SENSE", 16, 17, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_BLUE_SENSE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_INT_CONTROL[] = {
+	 { "DAC_AUTODETECT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_INT_ENABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_OUTPUT_CNTL[] = {
+	 { "DAC_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_SEL", 8, 10, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_ON_BLANKB_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_DATA[] = {
+	 { "DAC_FORCE_DATA", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_POWERDOWN[] = {
+	 { "DAC_POWERDOWN", 0, 0, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_BLUE", 8, 8, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_GREEN", 16, 16, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_RED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CONTROL[] = {
+	 { "DAC_DFORCE_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_TV_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DAC_ZSCALE_SHIFT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_ENABLE[] = {
+	 { "DAC_COMP_DDET_REF_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMP_SDET_REF_EN", 8, 8, &umr_bitfield_default },
+	 { "DAC_R_ASYNC_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DAC_G_ASYNC_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "DAC_B_ASYNC_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_OUTPUT[] = {
+	 { "DAC_COMPARATOR_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_BLUE", 1, 1, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_GREEN", 2, 2, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_RED", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_PWR_CNTL[] = {
+	 { "DAC_BG_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_PWRCNTL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_PHASE[] = {
+	 { "DCCG_AUDIO_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_DFT_CONFIG[] = {
+	 { "DAC_DFT_CONFIG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FIFO_STATUS[] = {
+	 { "DAC_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DAC_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DAC_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DAC_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DAC_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DAC_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_TEST_DEBUG_INDEX[] = {
+	 { "DAC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DAC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_TEST_DEBUG_DATA[] = {
+	 { "DAC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK1_SEL[] = {
+	 { "DCDEBUG_BUS_CLK1_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK2_SEL[] = {
+	 { "DCDEBUG_BUS_CLK2_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK3_SEL[] = {
+	 { "DCDEBUG_BUS_CLK3_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK4_SEL[] = {
+	 { "DCDEBUG_BUS_CLK4_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK5_SEL[] = {
+	 { "DCDEBUG_BUS_CLK5_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_PIN_OVERRIDE[] = {
+	 { "DCDEBUG_OUT_OVERRIDE1_PIN_SEL", 0, 4, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL", 5, 9, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_EN", 12, 12, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_PIN_SEL", 15, 19, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL", 20, 24, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_CNTL[] = {
+	 { "DCDEBUG_BLOCK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_24BIT_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCDEBUG_CLK_SEL", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_DATA[] = {
+	 { "DCDEBUG_OUT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_MODULE[] = {
+	 { "DCCG_AUDIO_DTO0_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_CONTROL[] = {
+	 { "DC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_STATUS_RESET", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC_SELECT", 8, 10, &umr_bitfield_default },
+	 { "DC_I2C_TRANSACTION_COUNT", 20, 21, &umr_bitfield_default },
+	 { "DC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_ARBITRATION[] = {
+	 { "DC_I2C_SW_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "DC_I2C_NO_QUEUED_SW_GO", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_HW_XFER", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_SW_XFER", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_USE_I2C_REG_REQ", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_USING_I2C_REG", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_USE_I2C_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_DONE_USING_I2C_REG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_INTERRUPT_CONTROL[] = {
+	 { "DC_I2C_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_MASK", 10, 10, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_INT", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_ACK", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_MASK", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_INT", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_ACK", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_MASK", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_INT", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_ACK", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_INT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_ACK", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_MASK", 26, 26, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_INT", 27, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_ACK", 28, 28, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_MASK", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_SW_STATUS[] = {
+	 { "DC_I2C_SW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_ABORTED", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_SW_TIMEOUT", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_SW_INTERRUPTED", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_SW_BUFFER_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_SW_STOPPED_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK2", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK3", 15, 15, &umr_bitfield_default },
+	 { "DC_I2C_SW_REQ", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_HW_STATUS[] = {
+	 { "DC_I2C_DDC1_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_HW_STATUS[] = {
+	 { "DC_I2C_DDC2_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_HW_STATUS[] = {
+	 { "DC_I2C_DDC3_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_HW_STATUS[] = {
+	 { "DC_I2C_DDC4_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_HW_STATUS[] = {
+	 { "DC_I2C_DDC5_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_HW_STATUS[] = {
+	 { "DC_I2C_DDC6_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SPEED[] = {
+	 { "DC_I2C_DDC1_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SETUP[] = {
+	 { "DC_I2C_DDC1_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_PHASE[] = {
+	 { "DCCG_AUDIO_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SPEED[] = {
+	 { "DC_I2C_DDC2_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SETUP[] = {
+	 { "DC_I2C_DDC2_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SPEED[] = {
+	 { "DC_I2C_DDC3_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SETUP[] = {
+	 { "DC_I2C_DDC3_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SPEED[] = {
+	 { "DC_I2C_DDC4_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SETUP[] = {
+	 { "DC_I2C_DDC4_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SPEED[] = {
+	 { "DC_I2C_DDC5_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SETUP[] = {
+	 { "DC_I2C_DDC5_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SPEED[] = {
+	 { "DC_I2C_DDC6_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SETUP[] = {
+	 { "DC_I2C_DDC6_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION0[] = {
+	 { "DC_I2C_RW0", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK0", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP0", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT0", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION1[] = {
+	 { "DC_I2C_RW1", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK1", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START1", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION2[] = {
+	 { "DC_I2C_RW2", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK2", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START2", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP2", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION3[] = {
+	 { "DC_I2C_RW3", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK3", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START3", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP3", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT3", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DATA[] = {
+	 { "DC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_INDEX", 16, 25, &umr_bitfield_default },
+	 { "DC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_HW_STATUS[] = {
+	 { "DC_I2C_DDCVGA_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_MODULE[] = {
+	 { "DCCG_AUDIO_DTO1_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SPEED[] = {
+	 { "DC_I2C_DDCVGA_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SETUP[] = {
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_EDID_DETECT_CTRL[] = {
+	 { "DC_I2C_EDID_DETECT_WAIT_TIME", 0, 15, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID", 20, 23, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_SEND_RESET", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_READ_REQUEST_INTERRUPT[] = {
+	 { "DC_I2C_DDC1_READ_REQUEST_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_INT", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_ACK", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_READ_REQUEST_MASK", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_INT", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_ACK", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_READ_REQUEST_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_INT", 9, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_ACK", 10, 10, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_READ_REQUEST_MASK", 11, 11, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_INT", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_ACK", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_READ_REQUEST_MASK", 15, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_INT", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_ACK", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_READ_REQUEST_MASK", 19, 19, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_INT", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_ACK", 22, 22, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_READ_REQUEST_MASK", 23, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_INT", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_ACK", 26, 26, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_READ_REQUEST_MASK", 27, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC_READ_REQUEST_ACK_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC_READ_REQUEST_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_CONTROL[] = {
+	 { "GENERIC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_INTERRUPT_CONTROL[] = {
+	 { "GENERIC_I2C_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_INT", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_ACK", 10, 10, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_MASK", 11, 11, &umr_bitfield_default },
+	 { "GENERIC_I2C_DDC_READ_REQUEST_INT_TYPE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_STATUS[] = {
+	 { "GENERIC_I2C_STATUS", 0, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_ABORTED", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOPPED_ON_NACK", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_NACK", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SPEED[] = {
+	 { "GENERIC_I2C_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_START_STOP_TIMING_CNTL", 8, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SETUP[] = {
+	 { "GENERIC_I2C_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "GENERIC_I2C_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_TRANSACTION[] = {
+	 { "GENERIC_I2C_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "GENERIC_I2C_ACK_ON_READ", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_START", 12, 12, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP", 13, 13, &umr_bitfield_default },
+	 { "GENERIC_I2C_COUNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_DATA[] = {
+	 { "GENERIC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX", 16, 19, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_SELECTION[] = {
+	 { "GENERIC_I2C_SCL_PIN_SEL", 0, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_PIN_SEL", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_DEBUG[] = {
+	 { "GENERIC_I2C_SCL_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_INPUT", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_EN", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_OUTPUT", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_INPUT", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_H[] = {
+	 { "DP_AUX_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG17[] = {
+	 { "DCIO_DEBUG17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_STATUS[] = {
+	 { "RESPONSE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "RESPONSE_OVERRUN_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_SIZE[] = {
+	 { "RIRB_SIZE", 0, 1, &umr_bitfield_default },
+	 { "RIRB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT17[] = {
+	 { "RA0_AS_A13B", 0, 0, &umr_bitfield_default },
+	 { "RA1_AS_A14B", 1, 1, &umr_bitfield_default },
+	 { "VCOUNT_BY2", 2, 2, &umr_bitfield_default },
+	 { "ADDR_CNT_BY2", 3, 3, &umr_bitfield_default },
+	 { "WRAP_A15TOA0", 5, 5, &umr_bitfield_default },
+	 { "BYTE_MODE", 6, 6, &umr_bitfield_default },
+	 { "CRTC_SYNC_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFCOUNTER_CNTL[] = {
+	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERFCOUNTER_CVALUE_SEL", 9, 11, &umr_bitfield_default },
+	 { "PERFCOUNTER_INC_MODE", 12, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_HW_CNTL_SEL", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_RUNEN_MODE", 15, 15, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTOFF_SEL", 16, 20, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTOFF_START_DIS", 21, 21, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESTART_EN", 22, 22, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT_EN", 23, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_OFF_MASK", 24, 24, &umr_bitfield_default },
+	 { "PERFCOUNTER_ACTIVE", 25, 25, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT_TYPE", 26, 26, &umr_bitfield_default },
+	 { "PERFCOUNTER_COUNTED_VALUE_TYPE", 27, 27, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED0[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_VREG_CFG[] = {
+	 { "pw_pc_bleeder_ac", 0, 0, &umr_bitfield_default },
+	 { "pw_pc_bleeder_en", 1, 1, &umr_bitfield_default },
+	 { "pw_pc_is_1p2", 2, 2, &umr_bitfield_default },
+	 { "pw_pc_reg_obs_sel", 3, 4, &umr_bitfield_default },
+	 { "pw_pc_reg_on_mode", 5, 6, &umr_bitfield_default },
+	 { "pw_pc_rlad_tap_sel", 7, 10, &umr_bitfield_default },
+	 { "pw_pc_reg_off_hi", 11, 11, &umr_bitfield_default },
+	 { "pw_pc_reg_off_lo", 12, 12, &umr_bitfield_default },
+	 { "pw_pc_scale_driver", 13, 14, &umr_bitfield_default },
+	 { "pw_pc_sel_bump", 15, 15, &umr_bitfield_default },
+	 { "pw_pc_sel_rladder_x", 16, 16, &umr_bitfield_default },
+	 { "pw_pc_short_rc_filt_x", 17, 17, &umr_bitfield_default },
+	 { "pw_pc_vref_pwr_on", 18, 18, &umr_bitfield_default },
+	 { "pw_pc_dpll_cfg_2", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED1[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_MODE_CNTL[] = {
+	 { "pw_pc_refclk_gate_dis", 0, 0, &umr_bitfield_default },
+	 { "pw_pc_multi_phase_en", 8, 11, &umr_bitfield_default },
+	 { "reg_tmg_pwr_state", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED2[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_FREQ_CTRL0[] = {
+	 { "reg_tmg_fcw0_frac", 0, 15, &umr_bitfield_default },
+	 { "reg_tmg_fcw0_int", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED3[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_FREQ_CTRL1[] = {
+	 { "reg_tmg_fcw1_frac", 0, 15, &umr_bitfield_default },
+	 { "reg_tmg_fcw1_int", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED4[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_FREQ_CTRL2[] = {
+	 { "reg_tmg_fcw_denom", 0, 15, &umr_bitfield_default },
+	 { "reg_tmg_fcw_slew_frac", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED5[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_FREQ_CTRL3[] = {
+	 { "reg_tmg_refclk_div", 0, 1, &umr_bitfield_default },
+	 { "reg_tmg_vco_pre_div", 3, 4, &umr_bitfield_default },
+	 { "reg_tmg_fracn_en", 6, 6, &umr_bitfield_default },
+	 { "reg_tmg_ssc_en", 8, 8, &umr_bitfield_default },
+	 { "reg_tmg_fcw_sel", 10, 10, &umr_bitfield_default },
+	 { "reg_tmg_freq_jump_en", 12, 12, &umr_bitfield_default },
+	 { "reg_tmg_tdc_resol", 16, 23, &umr_bitfield_default },
+	 { "pw_pc_dpll_cfg_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED6[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_BW_CTRL_COARSE[] = {
+	 { "reg_tmg_gi_crse_mant", 0, 1, &umr_bitfield_default },
+	 { "reg_tmg_gi_crse_exp", 2, 5, &umr_bitfield_default },
+	 { "reg_tmg_gp_crse_mant", 7, 10, &umr_bitfield_default },
+	 { "reg_tmg_gp_crse_exp", 12, 15, &umr_bitfield_default },
+	 { "reg_tmg_nctl_crse_res", 17, 22, &umr_bitfield_default },
+	 { "reg_tmg_nctl_crse_frac_res", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED7[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED8[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_BW_CTRL_FINE[] = {
+	 { "pw_pc_dpll_cfg_3", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED9[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_CAL_CTRL[] = {
+	 { "pw_pc_bypass_freq_lock", 0, 0, &umr_bitfield_default },
+	 { "pw_pc_tdc_cal_en", 1, 1, &umr_bitfield_default },
+	 { "pw_pc_tdc_cal_ctrl", 3, 8, &umr_bitfield_default },
+	 { "pw_pc_meas_win_sel", 9, 10, &umr_bitfield_default },
+	 { "pw_pc_kdco_cal_dis", 11, 11, &umr_bitfield_default },
+	 { "pw_pc_kdco_ratio", 13, 20, &umr_bitfield_default },
+	 { "pw_pc_kdco_incr_cal_dis", 22, 22, &umr_bitfield_default },
+	 { "pw_pc_nctl_adj_dis", 23, 23, &umr_bitfield_default },
+	 { "pw_pc_refclk_rate", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED10[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_LOOP_CTRL[] = {
+	 { "pw_pc_fbdiv_mask_en", 0, 0, &umr_bitfield_default },
+	 { "pw_pc_fb_slip_dis", 2, 2, &umr_bitfield_default },
+	 { "pw_pc_clk_tdc_sel", 4, 5, &umr_bitfield_default },
+	 { "pw_pc_clk_nctl_sel", 7, 8, &umr_bitfield_default },
+	 { "pw_pc_sig_del_patt_sel", 10, 10, &umr_bitfield_default },
+	 { "pw_pc_nctl_sig_del_dis", 12, 12, &umr_bitfield_default },
+	 { "pw_pc_fbclk_track_refclk", 14, 14, &umr_bitfield_default },
+	 { "pw_pc_prbs_en", 16, 16, &umr_bitfield_default },
+	 { "pw_pc_tdc_clk_gate_en", 18, 18, &umr_bitfield_default },
+	 { "pw_pc_phase_offset", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED11[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED12[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED13[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED14[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED15[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFCOUNTER_STATE[] = {
+	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED16[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED17[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED18[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED19[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED20[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED21[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED22[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED23[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED24[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_REFCLK_CNTL[] = {
+	 { "regs_pw_refclk0_recv_en", 0, 0, &umr_bitfield_default },
+	 { "regs_pw_refclk1_recv_en", 1, 1, &umr_bitfield_default },
+	 { "regs_pw_refclk2_recv_en", 2, 2, &umr_bitfield_default },
+	 { "regs_pw_refclk3_recv_en", 3, 3, &umr_bitfield_default },
+	 { "regs_pw_refclk0_recv_sel", 8, 8, &umr_bitfield_default },
+	 { "regs_pw_refclk1_recv_sel", 9, 9, &umr_bitfield_default },
+	 { "regs_pw_refclk2_recv_sel", 10, 10, &umr_bitfield_default },
+	 { "regs_pw_refclk3_recv_sel", 11, 11, &umr_bitfield_default },
+	 { "regs_pw_refdivsrc", 14, 15, &umr_bitfield_default },
+	 { "regs_pw_ref2core_sel", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED25[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_CLKOUT_CNTL[] = {
+	 { "regs_pw_pixclk_pre_pdivsel", 8, 8, &umr_bitfield_default },
+	 { "regs_pw_pixclk_pdivsel", 9, 9, &umr_bitfield_default },
+	 { "regs_pw_dvoclk_pre_pdivsel", 10, 10, &umr_bitfield_default },
+	 { "regs_pw_dvoclk_pdivsel", 11, 11, &umr_bitfield_default },
+	 { "regs_pw_idclk_en", 12, 12, &umr_bitfield_default },
+	 { "regs_pw_idclk_pre_pdivsel", 13, 13, &umr_bitfield_default },
+	 { "regs_pw_idclk_pdivsel", 14, 14, &umr_bitfield_default },
+	 { "regs_pw_idclk_obs_sel", 15, 15, &umr_bitfield_default },
+	 { "regs_pw_refclk_sel", 16, 17, &umr_bitfield_default },
+	 { "regs_cc_resetb", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED26[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_DFT_CNTL[] = {
+	 { "regs_pw_obs_en", 0, 0, &umr_bitfield_default },
+	 { "regs_pw_obs_div_sel_1", 1, 2, &umr_bitfield_default },
+	 { "regs_pw_obs_clk_sel_1", 4, 7, &umr_bitfield_default },
+	 { "regs_pw_obs_clk_sel_2", 8, 11, &umr_bitfield_default },
+	 { "regs_pw_obs_sel", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED27[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_ANALOG_CNTL[] = {
+	 { "regs_pw_spare", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED28[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_POSTDIV[] = {
+	 { "reg_tmg_postdiv", 8, 11, &umr_bitfield_default },
+	 { "reg_tmg_pixclk_pdiv2", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED29[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED30[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED31[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CVALUE_INT_MISC[] = {
+	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
+	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED32[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_DEBUG0[] = {
+	 { "pw_pc_phase_jump_trig", 1, 1, &umr_bitfield_default },
+	 { "pw_pc_fine_tdc_dis", 2, 2, &umr_bitfield_default },
+	 { "pw_pc_coarse_tdc_dis", 3, 3, &umr_bitfield_default },
+	 { "pw_pc_alt_nctl_en", 4, 4, &umr_bitfield_default },
+	 { "pw_pc_alt_nctl", 5, 24, &umr_bitfield_default },
+	 { "pw_pc_nctl_coarse_step_dis", 25, 25, &umr_bitfield_default },
+	 { "pw_pc_trig_coarse_step", 26, 26, &umr_bitfield_default },
+	 { "pw_pc_dft_sel", 27, 29, &umr_bitfield_default },
+	 { "pw_pc_dft_capture", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[] = {
+	 { "SUBSYSTEM_ID_BYTE1", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED33[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_OBSERVE0[] = {
+	 { "pw_pc_lock_det_tdc_steps", 0, 4, &umr_bitfield_default },
+	 { "pw_pc_clear_sticky_lock", 6, 6, &umr_bitfield_default },
+	 { "pw_pc_lock_det_dis", 8, 8, &umr_bitfield_default },
+	 { "pw_pc_dco_cfg", 10, 17, &umr_bitfield_default },
+	 { "pw_pc_anaobs_sel", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[] = {
+	 { "SUBSYSTEM_ID_BYTE2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED34[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_OBSERVE1[] = {
+	 { "pw_pc_digobs_sel", 0, 3, &umr_bitfield_default },
+	 { "pw_pc_digobs_trig_sel", 5, 8, &umr_bitfield_default },
+	 { "pw_pc_digobs_div", 10, 11, &umr_bitfield_default },
+	 { "pw_pc_digobs_trig_div", 12, 13, &umr_bitfield_default },
+	 { "reg_tmg_lock_timer", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[] = {
+	 { "SUBSYSTEM_ID_BYTE3", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED35[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED36[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_UPDATE_CNTL[] = {
+	 { "reg_tmg_PLL_UPDATE_LOCK", 2, 2, &umr_bitfield_default },
+	 { "reg_tmg_PLL_UPDATE_POINT", 3, 3, &umr_bitfield_default },
+	 { "tmg_reg_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "pc_pw_pll_rdy", 9, 9, &umr_bitfield_default },
+	 { "TieLow1", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED37[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_OBSERVE0_OUT[] = {
+	 { "disppll_core_obsout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED38[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_STATUS_DEBUG1[] = {
+	 { "dbg_pll_rdy", 0, 0, &umr_bitfield_default },
+	 { "core_disppll_pwr_ok_vddp", 1, 1, &umr_bitfield_default },
+	 { "core_disppll_rcu_dc_resetb_vddp", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED39[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_DEBUG_MUX_CNTL[] = {
+	 { "DEBUG_BUS_MUX_SEL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED40[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_DIV_UPDATE_DEBUG[] = {
+	 { "TieLow2", 0, 0, &umr_bitfield_default },
+	 { "tmg_reg_FB_DIV_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "dbg_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "tmg_reg_CURRENT_STATE", 3, 4, &umr_bitfield_default },
+	 { "tmg_reg_UPDATE_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "tmg_reg_UPDATE_REQ", 6, 6, &umr_bitfield_default },
+	 { "tmg_reg_UPDATE_ACK", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_MACRO_CNTL_RESERVED41[] = {
+	 { "PLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPPLL_STATUS_DEBUG0[] = {
+	 { "obsout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
+	 { "PERFMON_RUN_ENABLE_SEL", 2, 7, &umr_bitfield_default },
+	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CVALUE_LOW[] = {
+	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_HI[] = {
+	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
+	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_LOW[] = {
+	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_TEST_DEBUG_INDEX[] = {
+	 { "PERFMON_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "PERFMON_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_TEST_DEBUG_DATA[] = {
+	 { "PERFMON_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_INDEX[] = {
+	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_DATA[] = {
+	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CNTL2[] = {
+	 { "PERFMON_CNTOFF_INT_TYPE", 0, 0, &umr_bitfield_default },
+	 { "PERFMON_CLK_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
+	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
+	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_INDEX[] = {
+	 { "DCCG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCCG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_DATA[] = {
+	 { "DCCG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_CLK_SEL[] = {
+	 { "DCCG_TEST_CLK_GENERICA_SEL", 0, 8, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICA_INV", 12, 12, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_SEL", 16, 24, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_INV", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_CLOCK_GATING[] = {
+	 { "ENABLE_CLOCK_GATING", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO[] = {
+	 { "AZALIA_AUDIO_DTO_PHASE", 0, 15, &umr_bitfield_default },
+	 { "AZALIA_AUDIO_DTO_MODULE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO_CONTROL[] = {
+	 { "AZALIA_AUDIO_FORCE_DTO", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_SCLK_CONTROL[] = {
+	 { "AUDIO_SCLK_CONTROL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_UNDERFLOW_FILLER_SAMPLE[] = {
+	 { "AZALIA_UNDERFLOW_FILLER_SAMPLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_DATA_DMA_CONTROL[] = {
+	 { "DATA_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+	 { "INPUT_DATA_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default },
+	 { "DATA_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "INPUT_DATA_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default },
+	 { "AZALIA_IOC_GENERATION_METHOD", 16, 16, &umr_bitfield_default },
+	 { "AZALIA_UNDERFLOW_CONTROL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_BDL_DMA_CONTROL[] = {
+	 { "BDL_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+	 { "INPUT_BDL_DMA_NON_SNOOP", 2, 3, &umr_bitfield_default },
+	 { "BDL_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "INPUT_BDL_DMA_ISOCHRONOUS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_RIRB_AND_DP_CONTROL[] = {
+	 { "RIRB_NON_SNOOP", 0, 0, &umr_bitfield_default },
+	 { "DP_DMA_NON_SNOOP", 4, 4, &umr_bitfield_default },
+	 { "DP_UPDATE_FREQ_DIVIDER", 5, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CORB_DMA_CONTROL[] = {
+	 { "CORB_DMA_NON_SNOOP", 0, 0, &umr_bitfield_default },
+	 { "CORB_DMA_ISOCHRONOUS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[] = {
+	 { "APPLICATION_POSITION_IN_CYCLIC_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CYCLIC_BUFFER_SYNC[] = {
+	 { "CYCLIC_BUFFER_SYNC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_GLOBAL_CAPABILITIES[] = {
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+	 { "OUTSTRMPAY", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[] = {
+	 { "LATENCY_HIDING_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "SYS_MEM_ACTIVE_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "INPUT_LATENCY_HIDING_LEVEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_PAYLOAD_CAPABILITY[] = {
+	 { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+	 { "INSTRMPAY", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_DEBUG[] = {
+	 { "CONTROLLER_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL0[] = {
+	 { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL1[] = {
+	 { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL2[] = {
+	 { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_CONTROL3[] = {
+	 { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC0_RESULT[] = {
+	 { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[] = {
+	 { "IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD", 0, 27, &umr_bitfield_default },
+	 { "IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_I[] = {
+	 { "DP_AUX_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG18[] = {
+	 { "DCIO_DEBUG18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT18[] = {
+	 { "LINE_CMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL0[] = {
+	 { "INPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL1[] = {
+	 { "INPUT_CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL2[] = {
+	 { "INPUT_CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_CONTROL3[] = {
+	 { "INPUT_CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_INPUT_CRC1_RESULT[] = {
+	 { "INPUT_CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL0[] = {
+	 { "CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL1[] = {
+	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL2[] = {
+	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL3[] = {
+	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_RESULT[] = {
+	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL0[] = {
+	 { "CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL1[] = {
+	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL2[] = {
+	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL3[] = {
+	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_RESULT[] = {
+	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_MEM_PWR_CTRL[] = {
+	 { "AZ_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "AZ_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "AZ_MEM_PWR_MODE_SEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_MEM_PWR_STATUS[] = {
+	 { "AZ_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM0_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM1_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM2_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM3_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM4_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "AZ_INPUT_STREAM5_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_PG_DEBUG_CONFIG[] = {
+	 { "DCI_PG_DBG_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_INDEX[] = {
+	 { "AZ_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZ_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_DATA[] = {
+	 { "AZ_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[] = {
+	 { "HBR_CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "COMPRESSED_CHANNEL_COUNT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[] = {
+	 { "RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[] = {
+	 { "PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[] = {
+	 { "INPUT_PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
+	 { "INPUT_PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_DEBUG[] = {
+	 { "DISABLE_FORMAT_COMPARISON", 0, 5, &umr_bitfield_default },
+	 { "CODEC_DEBUG", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET0[] = {
+	 { "GTC_GROUP_OFFSET0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET1[] = {
+	 { "GTC_GROUP_OFFSET1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET2[] = {
+	 { "GTC_GROUP_OFFSET2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET3[] = {
+	 { "GTC_GROUP_OFFSET3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET4[] = {
+	 { "GTC_GROUP_OFFSET4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET5[] = {
+	 { "GTC_GROUP_OFFSET5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET6[] = {
+	 { "GTC_GROUP_OFFSET6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH0[] = {
+	 { "DCO_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH1[] = {
+	 { "DCO_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH2[] = {
+	 { "DCO_SCRATCH2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH3[] = {
+	 { "DCO_SCRATCH3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH4[] = {
+	 { "DCO_SCRATCH4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH5[] = {
+	 { "DCO_SCRATCH5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH6[] = {
+	 { "DCO_SCRATCH6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SCRATCH7[] = {
+	 { "DCO_SCRATCH7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCE_VCE_CONTROL[] = {
+	 { "DC_VCE_VIDEO_PIPE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DC_VCE_AUDIO_STREAM_SELECT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS[] = {
+	 { "SCL_DISP1_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D1BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D1_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D1_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC1_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC1_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC1_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGA_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD1_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX1_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX1_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DACA_AUTODETECT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DACB_AUTODETECT_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_HW_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DMCU_UC_INTERNAL_INT", 26, 26, &umr_bitfield_default },
+	 { "DMCU_SCP_INT", 27, 27, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT", 28, 28, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT", 29, 29, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE[] = {
+	 { "SCL_DISP2_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D2BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D2_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D2_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC2_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC2_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC2_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGB_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD2_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX2_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX2_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "LB_D1_VLINE2_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "LB_D2_VLINE2_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "LB_D3_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE2[] = {
+	 { "SCL_DISP3_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D3BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D3_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D3_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC3_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC3_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC3_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGC_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD3_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX3_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX3_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "LB_D4_VLINE2_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "LB_D5_VLINE2_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "LB_D6_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE3[] = {
+	 { "SCL_DISP4_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D4BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D4_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D4_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC4_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC4_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC4_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGD_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD4_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX4_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX4_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "BUFMGR_IHIF_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "WBSCL_HOST_CONFLICT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "WBSCL_DATA_OVERFLOW_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE4", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE4[] = {
+	 { "SCL_DISP5_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D5BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D5_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D5_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC5_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC5_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC5_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGE_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD5_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX5_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX5_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE5", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE5[] = {
+	 { "SCL_DISP6_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D6BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D6_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D6_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC6_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC6_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC6_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC6_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC6_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGF_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD6_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX6_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX6_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT0", 25, 25, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT1", 26, 26, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT2", 27, 27, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE6", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE6[] = {
+	 { "DCRX_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCRX_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "BUFMGR_CWB0_IHIF_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "BUFMGR_CWB1_IHIF_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGG_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "AUX1_GTC_SYNC_ERROR_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX2_GTC_SYNC_ERROR_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "AUX3_GTC_SYNC_ERROR_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "AUX4_GTC_SYNC_ERROR_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "AUX5_GTC_SYNC_ERROR_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "AUX6_GTC_SYNC_ERROR_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE7[] = {
+	 { "DCCG_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER0_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER1_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER2_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER3_INTERRUPT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE8", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE8[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER4_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER5_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER6_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER7_INTERRUPT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE9", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE9[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "WB_PERFMON_COUNTER_OFF_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE10", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_STATUS[] = {
+	 { "I2C_MEM_PWR_STATE", 0, 0, &umr_bitfield_default },
+	 { "MVP_MEM_PWR_STATE", 2, 2, &umr_bitfield_default },
+	 { "DPA_MEM_PWR_STATE", 3, 3, &umr_bitfield_default },
+	 { "DPB_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "DPC_MEM_PWR_STATE", 5, 5, &umr_bitfield_default },
+	 { "DPD_MEM_PWR_STATE", 6, 6, &umr_bitfield_default },
+	 { "DPE_MEM_PWR_STATE", 7, 7, &umr_bitfield_default },
+	 { "DPF_MEM_PWR_STATE", 8, 8, &umr_bitfield_default },
+	 { "DPG_MEM_PWR_STATE", 9, 9, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_CTRL[] = {
+	 { "I2C_LIGHT_SLEEP_FORCE", 0, 0, &umr_bitfield_default },
+	 { "I2C_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default },
+	 { "MVP_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DPA_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DPB_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DPC_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DPD_LIGHT_SLEEP_DIS", 7, 7, &umr_bitfield_default },
+	 { "DPE_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DPF_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
+	 { "DPG_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_FORCE", 14, 15, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_DIS", 19, 19, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_FORCE", 23, 24, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_DIS", 25, 25, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_FORCE", 26, 27, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_DIS", 28, 28, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_FORCE", 29, 30, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_CTRL2[] = {
+	 { "HDMI_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
+	 { "DPLPA_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "DPLPB_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HDMILP0_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
+	 { "HDMILP0_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
+	 { "HDMILP1_MEM_PWR_FORCE", 19, 20, &umr_bitfield_default },
+	 { "HDMILP1_MEM_PWR_DIS", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL[] = {
+	 { "DISPCLK_R_DCO_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_G_ABM_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_G_DVO_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_DACA_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_DACB_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "REFCLK_R_DCO_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGLPA_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGLPB_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGA_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGB_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGC_GATE_DIS", 26, 26, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGD_GATE_DIS", 27, 27, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGE_GATE_DIS", 28, 28, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGF_GATE_DIS", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGG_GATE_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_CNTL[] = {
+	 { "DPDBG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DPDBG_INPUT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DPDBG_SYMCLK_ON", 4, 4, &umr_bitfield_default },
+	 { "DPDBG_ERROR_DETECTION_MODE", 8, 8, &umr_bitfield_default },
+	 { "DPDBG_LINE_LENGTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPDBG_INTERRUPT[] = {
+	 { "DPDBG_FIFO_OVERFLOW_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_TYPE", 1, 1, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DPDBG_FIFO_OVERFLOW_INT_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_POWER_MANAGEMENT_CNTL[] = {
+	 { "PM_ASSERT_RESET", 0, 0, &umr_bitfield_default },
+	 { "PM_ALL_BUSY_OFF", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_SOFT_RESET_2[] = {
+	 { "DIGLPA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DIGLPA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DIGLPB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DIGLPB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_STEREOSYNC_SEL[] = {
+	 { "GENERICA_STEREOSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "GENERICB_STEREOSYNC_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_TEST_DEBUG_INDEX[] = {
+	 { "DCO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_TEST_DEBUG_DATA[] = {
+	 { "DCO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SOFT_RESET[] = {
+	 { "DACA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "I2S0_SPDIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "I2S1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "SPDIF1_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DB_CLK_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "FMT0_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "FMT1_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FMT2_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "FMT3_SOFT_RESET", 19, 19, &umr_bitfield_default },
+	 { "FMT4_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "FMT5_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "MVP_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "ABM_SOFT_RESET", 25, 25, &umr_bitfield_default },
+	 { "DVO_SOFT_RESET", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_SOFT_RESET[] = {
+	 { "DIGA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DIGA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DIGB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DIGB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIGC_FE_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DIGC_BE_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DIGD_FE_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DIGD_BE_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DIGE_FE_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "DIGE_BE_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "DIGF_FE_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "DIGF_BE_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "DIGG_FE_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "DIGG_BE_SOFT_RESET", 25, 25, &umr_bitfield_default },
+	 { "DPDBG_SOFT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_PWR_STATUS1[] = {
+	 { "DPLPA_MEM_PWR_STATE", 0, 0, &umr_bitfield_default },
+	 { "DPLPB_MEM_PWR_STATE", 1, 1, &umr_bitfield_default },
+	 { "HDMILP0_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "HDMILP1_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE10[] = {
+	 { "DIGLPA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DIGLPA_DP_VID_STREAM_DISABLE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DIGLPB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DIGLPB_DP_VID_STREAM_DISABLE_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER0_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER1_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER2_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER3_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER4_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER5_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER6_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER7_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON2_COUNTER_OFF_INTERRUPT", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL2[] = {
+	 { "DCO_TEST_CLK_SEL", 0, 6, &umr_bitfield_default },
+	 { "SCLK_G_AFMTA_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "SCLK_G_AFMTB_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "SCLK_G_AFMTC_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "SCLK_G_AFMTD_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "SCLK_G_AFMTE_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "SCLK_G_AFMTF_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "SCLK_G_AFMTG_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "SCLK_G_AFMTLPA_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "SCLK_G_AFMTLPB_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "SYMCLKA_FE_G_AFMT_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "SYMCLKB_FE_G_AFMT_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "SYMCLKC_FE_G_AFMT_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "SYMCLKD_FE_G_AFMT_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "SYMCLKE_FE_G_AFMT_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "SYMCLKF_FE_G_AFMT_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "SYMCLKG_FE_G_AFMT_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "SYMCLKLPA_FE_G_AFMT_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "SYMCLKLPB_FE_G_AFMT_GATE_DIS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL3[] = {
+	 { "SYMCLKA_FE_G_TMDS_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_G_TMDS_GATE_DIS", 1, 1, &umr_bitfield_default },
+	 { "SYMCLKC_FE_G_TMDS_GATE_DIS", 2, 2, &umr_bitfield_default },
+	 { "SYMCLKD_FE_G_TMDS_GATE_DIS", 3, 3, &umr_bitfield_default },
+	 { "SYMCLKE_FE_G_TMDS_GATE_DIS", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_G_TMDS_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "SYMCLKG_FE_G_TMDS_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "SYMCLKLPA_FE_G_TMDS_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "SYMCLKLPB_FE_G_TMDS_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "SYMCLKA_G_TMDS_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "SYMCLKB_G_TMDS_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "SYMCLKC_G_TMDS_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "SYMCLKD_G_TMDS_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "SYMCLKE_G_TMDS_GATE_DIS", 14, 14, &umr_bitfield_default },
+	 { "SYMCLKF_G_TMDS_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "SYMCLKG_G_TMDS_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "SYMCLKLPA_G_TMDS_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "SYMCLKLPB_G_TMDS_GATE_DIS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_HDMI_RXSTATUS_TIMER_CONTROL[] = {
+	 { "DCO_HDMI_RXSTATUS_TIMER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCO_HDMI_RXSTATUS_TIMER_TYPE", 4, 4, &umr_bitfield_default },
+	 { "DCO_HDMI_RXSTATUS_TIMER_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DCO_HDMI_RXSTATUS_TIMER_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCO_HDMI_RXSTATUS_TIMER_INTERVAL", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_PSP_INTERRUPT_STATUS[] = {
+	 { "DCO_PSP_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DCO_PSP_INTERRUPT_MESSAGE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_PSP_INTERRUPT_CLEAR[] = {
+	 { "DCO_PSP_INTERRUPT_CLEAR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_GENERIC_INTERRUPT_MESSAGE[] = {
+	 { "DCO_GENERIC_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DCO_GENERIC_INTERRUPT_MESSAGE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_GENERIC_INTERRUPT_CLEAR[] = {
+	 { "DCO_GENERIC_INTERRUPT_CLEAR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_MEMORY0_CONTROL[] = {
+	 { "FMT420_MEM0_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "FMT420_MEM0_PWR_FORCE", 4, 5, &umr_bitfield_default },
+	 { "FMT420_MEM0_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "FMT420_MEM0_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_MEMORY1_CONTROL[] = {
+	 { "FMT420_MEM1_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "FMT420_MEM1_PWR_FORCE", 4, 5, &umr_bitfield_default },
+	 { "FMT420_MEM1_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "FMT420_MEM1_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_MEMORY2_CONTROL[] = {
+	 { "FMT420_MEM2_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "FMT420_MEM2_PWR_FORCE", 4, 5, &umr_bitfield_default },
+	 { "FMT420_MEM2_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "FMT420_MEM2_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_MEMORY3_CONTROL[] = {
+	 { "FMT420_MEM3_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "FMT420_MEM3_PWR_FORCE", 4, 5, &umr_bitfield_default },
+	 { "FMT420_MEM3_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "FMT420_MEM3_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_MEMORY4_CONTROL[] = {
+	 { "FMT420_MEM4_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "FMT420_MEM4_PWR_FORCE", 4, 5, &umr_bitfield_default },
+	 { "FMT420_MEM4_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "FMT420_MEM4_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_MEMORY5_CONTROL[] = {
+	 { "FMT420_MEM5_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "FMT420_MEM5_PWR_FORCE", 4, 5, &umr_bitfield_default },
+	 { "FMT420_MEM5_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "FMT420_MEM5_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_INT_STATUS[] = {
+	 { "DC_HPD_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_INT_CONTROL[] = {
+	 { "DC_HPD_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_CONTROL[] = {
+	 { "DC_HPD_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[] = {
+	 { "IMMEDIATE_RESPONSE_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_J[] = {
+	 { "DP_AUX_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG19[] = {
+	 { "DCIO_DIGLPA_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_STATUS[] = {
+	 { "IMMEDIATE_COMMAND_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IMMEDIATE_RESULT_VALID", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_K[] = {
+	 { "DP_AUX_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1A[] = {
+	 { "DCIO_DIGLPB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_ENABLE[] = {
+	 { "GRPH_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_KEYER_ALPHA_SEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_CONTROL[] = {
+	 { "GRPH_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "GRPH_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "GRPH_Z", 4, 5, &umr_bitfield_default },
+	 { "GRPH_BANK_WIDTH", 6, 7, &umr_bitfield_default },
+	 { "GRPH_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "GRPH_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "GRPH_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT", 18, 19, &umr_bitfield_default },
+	 { "GRPH_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "GRPH_PIPE_CONFIG", 24, 28, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE", 29, 30, &umr_bitfield_default },
+	 { "GRPH_COLOR_EXPANSION_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_LUT_10BIT_BYPASS[] = {
+	 { "GRPH_LUT_10BIT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SWAP_CNTL[] = {
+	 { "GRPH_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "GRPH_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "GRPH_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+	 { "GRPH_ALPHA_CROSSBAR", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PRIMARY_SURFACE_ADDRESS[] = {
+	 { "GRPH_PRIMARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SECONDARY_SURFACE_ADDRESS[] = {
+	 { "GRPH_SECONDARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PITCH[] = {
+	 { "GRPH_PITCH", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_OFFSET_X[] = {
+	 { "GRPH_SURFACE_OFFSET_X", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_OFFSET_Y[] = {
+	 { "GRPH_SURFACE_OFFSET_Y", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_X_START[] = {
+	 { "GRPH_X_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_Y_START[] = {
+	 { "GRPH_Y_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_X_END[] = {
+	 { "GRPH_X_END", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_Y_END[] = {
+	 { "GRPH_Y_END", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_COUNTER_CONTROL[] = {
+	 { "GRPH_SURFACE_COUNTER_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SURFACE_COUNTER_EVENT_SELECT", 1, 4, &umr_bitfield_default },
+	 { "GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_CONTROL[] = {
+	 { "GRPH_INPUT_GAMMA_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_UPDATE[] = {
+	 { "GRPH_MODE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "GRPH_MODE_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_TAKEN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_SURFACE_XDMA_PENDING_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "GRPH_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SURFACE_IGNORE_UPDATE_LOCK", 20, 20, &umr_bitfield_default },
+	 { "GRPH_MODE_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_FLIP_CONTROL[] = {
+	 { "GRPH_SURFACE_UPDATE_H_RETRACE_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_XDMA_SUPER_AA_EN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_IMMEDIATE_EN", 4, 4, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING_MODE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_ADDRESS_INUSE[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_DFQ_CONTROL[] = {
+	 { "GRPH_DFQ_RESET", 0, 0, &umr_bitfield_default },
+	 { "GRPH_DFQ_SIZE", 4, 6, &umr_bitfield_default },
+	 { "GRPH_DFQ_MIN_FREE_ENTRIES", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_DFQ_STATUS[] = {
+	 { "GRPH_PRIMARY_DFQ_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_DFQ_NUM_ENTRIES", 4, 7, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_INTERRUPT_STATUS[] = {
+	 { "GRPH_PFLIP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_INTERRUPT_CONTROL[] = {
+	 { "GRPH_PFLIP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_SURFACE_ADDRESS[] = {
+	 { "GRPH_COMPRESS_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_PITCH[] = {
+	 { "GRPH_COMPRESS_PITCH", 6, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT[] = {
+	 { "GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_COUNTER_OUTPUT[] = {
+	 { "GRPH_SURFACE_COUNTER_MIN", 0, 15, &umr_bitfield_default },
+	 { "GRPH_SURFACE_COUNTER_MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_GRPH_CONTROL[] = {
+	 { "GRPH_PRESCALE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_R_SIGN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_G_SIGN", 2, 2, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_B_SIGN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_BYPASS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_R[] = {
+	 { "GRPH_PRESCALE_BIAS_R", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_G[] = {
+	 { "GRPH_PRESCALE_BIAS_G", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_B[] = {
+	 { "GRPH_PRESCALE_BIAS_B", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_CONTROL[] = {
+	 { "INPUT_CSC_GRPH_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12[] = {
+	 { "INPUT_CSC_C11", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14[] = {
+	 { "INPUT_CSC_C13", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22[] = {
+	 { "INPUT_CSC_C21", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24[] = {
+	 { "INPUT_CSC_C23", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32[] = {
+	 { "INPUT_CSC_C31", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34[] = {
+	 { "INPUT_CSC_C33", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_CONTROL[] = {
+	 { "OUTPUT_CSC_GRPH_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12[] = {
+	 { "OUTPUT_CSC_C11", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14[] = {
+	 { "OUTPUT_CSC_C13", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22[] = {
+	 { "OUTPUT_CSC_C21", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24[] = {
+	 { "OUTPUT_CSC_C23", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32[] = {
+	 { "OUTPUT_CSC_C31", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34[] = {
+	 { "OUTPUT_CSC_C33", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXA_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXA_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXA_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXA_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXA_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXA_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXB_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXB_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXB_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXB_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXB_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXB_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CONTROL[] = {
+	 { "DENORM_MODE", 0, 2, &umr_bitfield_default },
+	 { "DENORM_14BIT_OUT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_ROUND_CONTROL[] = {
+	 { "OUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_R_CR[] = {
+	 { "OUT_CLAMP_MAX_R_CR", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_R_CR", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_CONTROL[] = {
+	 { "KEY_MODE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_ALPHA[] = {
+	 { "KEY_ALPHA_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_ALPHA_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_RED[] = {
+	 { "KEY_RED_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_RED_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_GREEN[] = {
+	 { "KEY_GREEN_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_GREEN_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_BLUE[] = {
+	 { "KEY_BLUE_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_BLUE_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEGAMMA_CONTROL[] = {
+	 { "GRPH_DEGAMMA_MODE", 0, 1, &umr_bitfield_default },
+	 { "CURSOR2_DEGAMMA_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_DEGAMMA_MODE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_CONTROL[] = {
+	 { "GRPH_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C11_C12[] = {
+	 { "GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C13_C14[] = {
+	 { "GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C21_C22[] = {
+	 { "GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C23_C24[] = {
+	 { "GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C31_C32[] = {
+	 { "GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C33_C34[] = {
+	 { "GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_SPATIAL_DITHER_CNTL[] = {
+	 { "DCP_SPATIAL_DITHER_EN", 0, 0, &umr_bitfield_default },
+	 { "DCP_SPATIAL_DITHER_MODE", 4, 5, &umr_bitfield_default },
+	 { "DCP_SPATIAL_DITHER_DEPTH", 6, 7, &umr_bitfield_default },
+	 { "DCP_FRAME_RANDOM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DCP_RGB_RANDOM_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "DCP_HIGHPASS_RANDOM_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_RANDOM_SEEDS[] = {
+	 { "DCP_RAND_R_SEED", 0, 7, &umr_bitfield_default },
+	 { "DCP_RAND_G_SEED", 8, 15, &umr_bitfield_default },
+	 { "DCP_RAND_B_SEED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_FP_CONVERTED_FIELD[] = {
+	 { "DCP_FP_CONVERTED_FIELD_DATA", 0, 17, &umr_bitfield_default },
+	 { "DCP_FP_CONVERTED_FIELD_INDEX", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_CONTROL[] = {
+	 { "CURSOR_EN", 0, 0, &umr_bitfield_default },
+	 { "CUR_INV_TRANS_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_BUSY_START_LINE_POSITION", 12, 15, &umr_bitfield_default },
+	 { "CURSOR_2X_MAGNIFY", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_FORCE_MC_ON", 20, 20, &umr_bitfield_default },
+	 { "CURSOR_URGENT_CONTROL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS[] = {
+	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SIZE[] = {
+	 { "CURSOR_HEIGHT", 0, 6, &umr_bitfield_default },
+	 { "CURSOR_WIDTH", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS_HIGH[] = {
+	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_POSITION[] = {
+	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
+	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_HOT_SPOT[] = {
+	 { "CURSOR_HOT_SPOT_Y", 0, 6, &umr_bitfield_default },
+	 { "CURSOR_HOT_SPOT_X", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR1[] = {
+	 { "CUR_COLOR1_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR1_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR1_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR2[] = {
+	 { "CUR_COLOR2_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR2_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR2_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_UPDATE[] = {
+	 { "CURSOR_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_STEREO_MODE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_MODE[] = {
+	 { "DC_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
+	 { "DC_LUT_ERROR", 16, 16, &umr_bitfield_default },
+	 { "DC_LUT_ERROR_RST", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_INDEX[] = {
+	 { "DC_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_SEQ_COLOR[] = {
+	 { "DC_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_PWL_DATA[] = {
+	 { "DC_LUT_BASE", 0, 15, &umr_bitfield_default },
+	 { "DC_LUT_DELTA", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_30_COLOR[] = {
+	 { "DC_LUT_COLOR_10_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_VGA_ACCESS_ENABLE[] = {
+	 { "DC_LUT_VGA_ACCESS_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WRITE_EN_MASK[] = {
+	 { "DC_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_AUTOFILL[] = {
+	 { "DC_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
+	 { "DC_LUT_AUTOFILL_DONE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_CONTROL[] = {
+	 { "DC_LUT_INC_B", 0, 3, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_SIGNED_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FLOAT_POINT_EN", 5, 5, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FORMAT", 6, 7, &umr_bitfield_default },
+	 { "DC_LUT_INC_G", 8, 11, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_SIGNED_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FLOAT_POINT_EN", 13, 13, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FORMAT", 14, 15, &umr_bitfield_default },
+	 { "DC_LUT_INC_R", 16, 19, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_SIGNED_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FLOAT_POINT_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FORMAT", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_BLUE[] = {
+	 { "DC_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_GREEN[] = {
+	 { "DC_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_RED[] = {
+	 { "DC_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_BLUE[] = {
+	 { "DC_LUT_WHITE_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_GREEN[] = {
+	 { "DC_LUT_WHITE_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_RED[] = {
+	 { "DC_LUT_WHITE_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_CONTROL[] = {
+	 { "DCP_CRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCP_CRC_SOURCE_SEL", 2, 4, &umr_bitfield_default },
+	 { "DCP_CRC_LINE_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_MASK[] = {
+	 { "DCP_CRC_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_CURRENT[] = {
+	 { "DCP_CRC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_CONTROL[] = {
+	 { "DVMM_USE_SINGLE_PTE", 0, 0, &umr_bitfield_default },
+	 { "DVMM_PAGE_WIDTH", 1, 4, &umr_bitfield_default },
+	 { "DVMM_PAGE_HEIGHT", 5, 8, &umr_bitfield_default },
+	 { "DVMM_MIN_PTE_BEFORE_FLIP", 9, 18, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE0", 20, 20, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE1", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_LAST[] = {
+	 { "DCP_CRC_LAST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG[] = {
+	 { "DCP_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_FLIP_RATE_CNTL[] = {
+	 { "GRPH_FLIP_RATE", 0, 2, &umr_bitfield_default },
+	 { "GRPH_FLIP_RATE_ENABLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_GSL_CONTROL[] = {
+	 { "DCP_GSL0_EN", 0, 0, &umr_bitfield_default },
+	 { "DCP_GSL1_EN", 1, 1, &umr_bitfield_default },
+	 { "DCP_GSL2_EN", 2, 2, &umr_bitfield_default },
+	 { "DCP_GSL_HSYNC_FLIP_FORCE_DELAY", 12, 15, &umr_bitfield_default },
+	 { "DCP_GSL_MASTER_EN", 16, 16, &umr_bitfield_default },
+	 { "DCP_GSL_XDMA_GROUP", 17, 18, &umr_bitfield_default },
+	 { "DCP_GSL_XDMA_GROUP_UNDERFLOW_EN", 19, 19, &umr_bitfield_default },
+	 { "DCP_GSL_SYNC_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "DCP_GSL_DELAY_SURFACE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
+	 { "DCP_GSL_HSYNC_FLIP_CHECK_DELAY", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[] = {
+	 { "DCP_LB_GAP_BETWEEN_CHUNK_20BPP", 0, 3, &umr_bitfield_default },
+	 { "DCP_LB_GAP_BETWEEN_CHUNK_30BPP", 4, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG_SG[] = {
+	 { "DCP_DEBUG_SG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DVMM_DEBUG[] = {
+	 { "DCP_DVMM_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG_SG2[] = {
+	 { "DCP_DEBUG_SG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_TEST_DEBUG_INDEX[] = {
+	 { "DCP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_TEST_DEBUG_DATA[] = {
+	 { "DCP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_STEREOSYNC_FLIP[] = {
+	 { "GRPH_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_FLIP_MODE", 8, 9, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG2[] = {
+	 { "DCP_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_REQUEST_FILTER_CNTL[] = {
+	 { "CUR_REQUEST_FILTER_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_STEREO_CONTROL[] = {
+	 { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_STEREO_OFFSET_YNX", 1, 1, &umr_bitfield_default },
+	 { "CURSOR_PRIMARY_OFFSET", 4, 13, &umr_bitfield_default },
+	 { "CURSOR_SECONDARY_OFFSET", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_G_Y[] = {
+	 { "OUT_CLAMP_MAX_G_Y", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_G_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_B_CB[] = {
+	 { "OUT_CLAMP_MAX_B_CB", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_B_CB", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHW_ROTATION[] = {
+	 { "GRPH_ROTATION_ANGLE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[] = {
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE", 1, 1, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT", 4, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CONTROL[] = {
+	 { "GRPH_REGAMMA_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_INDEX[] = {
+	 { "REGAMMA_LUT_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_DATA[] = {
+	 { "REGAMMA_LUT_DATA", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_WRITE_EN_MASK[] = {
+	 { "REGAMMA_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_START_CNTL[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_SLOPE_CNTL[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_END_CNTL1[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_END_CNTL2[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_0_1[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_2_3[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_4_5[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_6_7[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_8_9[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_10_11[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_12_13[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_14_15[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_START_CNTL[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_SLOPE_CNTL[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_END_CNTL1[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_END_CNTL2[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_0_1[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_2_3[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_4_5[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_6_7[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_8_9[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_10_11[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_12_13[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_14_15[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmALPHA_CONTROL[] = {
+	 { "ALPHA_ROUND_TRUNC_MODE", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_ALPHA_BLND_ENA", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[] = {
+	 { "GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[] = {
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT", 0, 19, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK", 25, 25, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK", 26, 26, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT", 28, 28, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK", 29, 29, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DATA_FORMAT[] = {
+	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "PIXEL_EXPAN_MODE", 2, 2, &umr_bitfield_default },
+	 { "INTERLEAVE_EN", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_REDUCE_MODE", 4, 4, &umr_bitfield_default },
+	 { "DYNAMIC_PIXEL_DEPTH", 5, 5, &umr_bitfield_default },
+	 { "PREFILL_EN", 8, 8, &umr_bitfield_default },
+	 { "PREFETCH", 12, 12, &umr_bitfield_default },
+	 { "REQUEST_MODE", 24, 24, &umr_bitfield_default },
+	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_MEMORY_CTRL[] = {
+	 { "LB_MEMORY_SIZE", 0, 12, &umr_bitfield_default },
+	 { "LB_NUM_PARTITIONS", 16, 19, &umr_bitfield_default },
+	 { "LB_MEMORY_CONFIG", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_MEMORY_SIZE_STATUS[] = {
+	 { "LB_MEMORY_SIZE_STATUS", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DESKTOP_HEIGHT[] = {
+	 { "DESKTOP_HEIGHT", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE_START_END[] = {
+	 { "VLINE_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE2_START_END[] = {
+	 { "VLINE2_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE2_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE2_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_V_COUNTER[] = {
+	 { "V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_SNAPSHOT_V_COUNTER[] = {
+	 { "SNAPSHOT_V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_INTERRUPT_MASK[] = {
+	 { "VBLANK_INTERRUPT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_MASK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE_STATUS[] = {
+	 { "VLINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE2_STATUS[] = {
+	 { "VLINE2_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE2_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VBLANK_STATUS[] = {
+	 { "VBLANK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VBLANK_ACK", 4, 4, &umr_bitfield_default },
+	 { "VBLANK_STAT", 12, 12, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_SYNC_RESET_SEL[] = {
+	 { "LB_SYNC_RESET_SEL", 0, 1, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_SEL2", 4, 4, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LB_SYNC_DURATION", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_R_CR[] = {
+	 { "LB_BLACK_KEYER_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_G_Y[] = {
+	 { "LB_BLACK_KEYER_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_B_CB[] = {
+	 { "LB_BLACK_KEYER_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_CTRL[] = {
+	 { "LB_KEYER_COLOR_EN", 0, 0, &umr_bitfield_default },
+	 { "LB_KEYER_COLOR_REP_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_R_CR[] = {
+	 { "LB_KEYER_COLOR_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_G_Y[] = {
+	 { "LB_KEYER_COLOR_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_B_CB[] = {
+	 { "LB_KEYER_COLOR_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_R_CR[] = {
+	 { "LB_KEYER_COLOR_REP_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_G_Y[] = {
+	 { "LB_KEYER_COLOR_REP_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_B_CB[] = {
+	 { "LB_KEYER_COLOR_REP_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_LEVEL_STATUS[] = {
+	 { "REQ_FIFO_LEVEL", 0, 5, &umr_bitfield_default },
+	 { "REQ_FIFO_FULL_CNTL", 10, 15, &umr_bitfield_default },
+	 { "DATA_BUFFER_LEVEL", 16, 27, &umr_bitfield_default },
+	 { "DATA_FIFO_FULL_CNTL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_URGENCY_CTRL[] = {
+	 { "LB_BUFFER_URGENCY_MARK_ON", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_MARK_OFF", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_URGENCY_STATUS[] = {
+	 { "LB_BUFFER_URGENCY_LEVEL", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_STAT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_STATUS[] = {
+	 { "LB_BUFFER_EMPTY_MARGIN", 0, 3, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_STAT", 4, 4, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_ACK", 12, 12, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_STAT", 16, 16, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_ACK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_NO_OUTSTANDING_REQ_STATUS[] = {
+	 { "LB_NO_OUTSTANDING_REQ_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_AFR_FLIP_MODE[] = {
+	 { "MVP_AFR_FLIP_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_AFR_FLIP_FIFO_CNTL[] = {
+	 { "MVP_AFR_FLIP_FIFO_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET", 4, 4, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FLIP_LINE_NUM_INSERT[] = {
+	 { "MVP_FLIP_LINE_NUM_INSERT_MODE", 0, 1, &umr_bitfield_default },
+	 { "MVP_FLIP_LINE_NUM_INSERT", 8, 22, &umr_bitfield_default },
+	 { "MVP_FLIP_LINE_NUM_OFFSET", 24, 29, &umr_bitfield_default },
+	 { "MVP_FLIP_AUTO_ENABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_MVP_LB_CONTROL[] = {
+	 { "MVP_SWAP_LOCK_IN_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_SEL", 8, 8, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_IN_CAP", 28, 28, &umr_bitfield_default },
+	 { "DC_MVP_SPARE_FLOPS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG[] = {
+	 { "LB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG2[] = {
+	 { "LB_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG3[] = {
+	 { "LB_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_TEST_DEBUG_INDEX[] = {
+	 { "LB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "LB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_TEST_DEBUG_DATA[] = {
+	 { "LB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_L[] = {
+	 { "DP_AUX_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1B[] = {
+	 { "DCIO_DEBUGHPD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_CLOCK_CONTROL[] = {
+	 { "DISPCLK_R_DCFE_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "DISPCLK_G_DCP_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_SCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "DISPCLK_G_PSCL_GATE_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DISPCLK_G_PIPE_REQUEST_DIS_GATE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "DCFE_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DCFE_CLOCK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_SOFT_RESET[] = {
+	 { "DCP_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "PSCL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_DBG_CONFIG[] = {
+	 { "DCFE_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE_DBG_SEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_CTRL[] = {
+	 { "DCP_LUT_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DCP_LUT_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_FORCE", 21, 22, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_FORCE", 27, 28, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_DIS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_CTRL2[] = {
+	 { "DCP_LUT_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_MODE_SEL", 2, 3, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_MODE_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_MODE_SEL", 6, 7, &umr_bitfield_default },
+	 { "LB_ALPHA_MEM_PWR_MODE_SEL", 8, 9, &umr_bitfield_default },
+	 { "LB_MEM_PWR_MODE_SEL", 10, 11, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_MODE_SEL", 14, 15, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_FORCE", 21, 22, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_PWR_STATUS[] = {
+	 { "DCP_LUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DCP_REGAMMA_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "SCL_COEFF_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "LB0_ALPHA_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "LB1_ALPHA_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "LB2_ALPHA_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "LB0_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "LB1_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "LB2_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "BLND_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MISC[] = {
+	 { "DCFE_DPG_ALLOW_SR_ECO_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_FLUSH[] = {
+	 { "FLUSH_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "CLEAR_FLUSH_OCCURED", 1, 1, &umr_bitfield_default },
+	 { "FLUSH_DEEP", 2, 2, &umr_bitfield_default },
+	 { "CLEAR_FLUSH_DEEP", 3, 3, &umr_bitfield_default },
+	 { "ALL_MC_REQ_RET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_ARBITRATION_CONTROL1[] = {
+	 { "PIXEL_DURATION", 0, 15, &umr_bitfield_default },
+	 { "BASE_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_ARBITRATION_CONTROL2[] = {
+	 { "TIME_WEIGHT", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_WATERMARK_MASK_CONTROL[] = {
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK", 0, 2, &umr_bitfield_default },
+	 { "URGENCY_WATERMARK_MASK", 8, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 16, 18, &umr_bitfield_default },
+	 { "DISABLE_FLIP_URGENT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_URGENCY_CONTROL[] = {
+	 { "URGENCY_LOW_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_HIGH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_DPM_CONTROL[] = {
+	 { "DPM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCLK_CHANGE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCLK_CHANGE_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK_MASK", 12, 13, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_STUTTER_CONTROL[] = {
+	 { "STUTTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON", 11, 11, &umr_bitfield_default },
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[] = {
+	 { "NB_PSTATE_CHANGE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_FORCE_ON", 9, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_ALLOW_FOR_URGENT", 10, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[] = {
+	 { "STUTTER_ENABLE_NONLPTCH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR_NONLPTCH", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON_NONLPTCH", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA_NONLPTCH", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC_NONLPTCH", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON_NONLPTCH", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_TEST_DEBUG_INDEX[] = {
+	 { "DPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_TEST_DEBUG_DATA[] = {
+	 { "DPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_REPEATER_PROGRAM[] = {
+	 { "REG_DPG_DMIFRC_REPEATER", 0, 2, &umr_bitfield_default },
+	 { "REG_DMIFRC_DPG_REPEATER", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_A[] = {
+	 { "DPG_HW_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_B[] = {
+	 { "DPG_HW_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_11[] = {
+	 { "DPG_HW_DEBUG_11", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_CHK_PRE_PROC_CNTL[] = {
+	 { "DPG_DISABLE_DMIF_BUF_CHK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_DVMM_STATUS[] = {
+	 { "DPG_DVMM_FORCED_FLIP_TO_UNMAPPED", 0, 0, &umr_bitfield_default },
+	 { "DPG_DVMM_FORCED_FLIP_TO_MAPPED", 1, 1, &umr_bitfield_default },
+	 { "DPG_DVMM_FORCED_FLIP_TO_UNMAPPED_CLR", 4, 4, &umr_bitfield_default },
+	 { "DPG_DVMM_FORCED_FLIP_TO_MAPPED_CLR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_SELECT[] = {
+	 { "SCL_C_RAM_TAP_PAIR_IDX", 0, 3, &umr_bitfield_default },
+	 { "SCL_C_RAM_PHASE", 8, 11, &umr_bitfield_default },
+	 { "SCL_C_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_TAP_DATA[] = {
+	 { "SCL_C_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
+	 { "SCL_C_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE[] = {
+	 { "SCL_MODE", 0, 1, &umr_bitfield_default },
+	 { "SCL_PSCL_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TAP_CONTROL[] = {
+	 { "SCL_V_NUM_OF_TAPS", 0, 2, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_CONTROL[] = {
+	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_EARLY_EOL_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_BYPASS_CONTROL[] = {
+	 { "SCL_BYPASS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MANUAL_REPLICATE_CONTROL[] = {
+	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
+	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_AUTOMATIC_MODE_CONTROL[] = {
+	 { "SCL_V_CALC_AUTO_RATIO_EN", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_CALC_AUTO_RATIO_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_CONTROL[] = {
+	 { "SCL_H_FILTER_PICK_NEAREST", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_SCALE_RATIO[] = {
+	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_INIT[] = {
+	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_CONTROL[] = {
+	 { "SCL_V_FILTER_PICK_NEAREST", 0, 0, &umr_bitfield_default },
+	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_SCALE_RATIO[] = {
+	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_INIT[] = {
+	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_INIT_BOT[] = {
+	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_ROUND_OFFSET[] = {
+	 { "SCL_ROUND_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
+	 { "SCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_UPDATE[] = {
+	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "SCL_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "SCL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "SCL_COEF_UPDATE_COMPLETE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_F_SHARP_CONTROL[] = {
+	 { "SCL_HF_SHARP_SCALE_FACTOR", 0, 2, &umr_bitfield_default },
+	 { "SCL_HF_SHARP_EN", 4, 4, &umr_bitfield_default },
+	 { "SCL_VF_SHARP_SCALE_FACTOR", 8, 10, &umr_bitfield_default },
+	 { "SCL_VF_SHARP_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_ALU_CONTROL[] = {
+	 { "SCL_ALU_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_CONFLICT_STATUS[] = {
+	 { "SCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_START_SECONDARY[] = {
+	 { "VIEWPORT_Y_START_SECONDARY", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_START[] = {
+	 { "VIEWPORT_Y_START", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_SIZE[] = {
+	 { "VIEWPORT_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_LEFT_RIGHT[] = {
+	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_TOP_BOTTOM[] = {
+	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET1[] = {
+	 { "SCL_MODE_CHANGE", 0, 0, &umr_bitfield_default },
+	 { "SCL_MODE_CHANGE_ACK", 4, 4, &umr_bitfield_default },
+	 { "SCL_ALU_H_SCALE_RATIO", 7, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET2[] = {
+	 { "SCL_ALU_V_SCALE_RATIO", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET3[] = {
+	 { "SCL_ALU_SOURCE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "SCL_ALU_SOURCE_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_MASK[] = {
+	 { "SCL_MODE_CHANGE_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_DEBUG2[] = {
+	 { "SCL_DEBUG_REQ_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_DEBUG_EOF_MODE", 1, 2, &umr_bitfield_default },
+	 { "SCL_DEBUG2", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_DEBUG[] = {
+	 { "SCL_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TEST_DEBUG_INDEX[] = {
+	 { "SCL_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SCL_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TEST_DEBUG_DATA[] = {
+	 { "SCL_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_CONTROL[] = {
+	 { "BLND_GLOBAL_GAIN", 0, 7, &umr_bitfield_default },
+	 { "BLND_MODE", 8, 9, &umr_bitfield_default },
+	 { "BLND_STEREO_TYPE", 10, 11, &umr_bitfield_default },
+	 { "BLND_STEREO_POLARITY", 12, 12, &umr_bitfield_default },
+	 { "BLND_FEEDTHROUGH_EN", 13, 13, &umr_bitfield_default },
+	 { "BLND_ALPHA_MODE", 16, 17, &umr_bitfield_default },
+	 { "BLND_ACTIVE_OVERLAP_ONLY", 18, 18, &umr_bitfield_default },
+	 { "BLND_MULTIPLIED_MODE", 20, 20, &umr_bitfield_default },
+	 { "BLND_GLOBAL_ALPHA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_SM_CONTROL2[] = {
+	 { "SM_MODE", 0, 2, &umr_bitfield_default },
+	 { "SM_FRAME_ALTERNATE", 4, 4, &umr_bitfield_default },
+	 { "SM_FIELD_ALTERNATE", 5, 5, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
+	 { "SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_CONTROL2[] = {
+	 { "PTI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PTI_NEW_PIXEL_GAP", 4, 5, &umr_bitfield_default },
+	 { "BLND_NEW_PIXEL_MODE", 6, 6, &umr_bitfield_default },
+	 { "BLND_SUPERAA_DEGAMMA_EN", 7, 7, &umr_bitfield_default },
+	 { "BLND_SUPERAA_REGAMMA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_UPDATE[] = {
+	 { "BLND_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "BLND_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "BLND_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_UNDERFLOW_INTERRUPT[] = {
+	 { "BLND_UNDERFLOW_INT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_PIPE_INDEX", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_V_UPDATE_LOCK[] = {
+	 { "BLND_DCP_GRPH_V_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BLND_DCP_GRPH_SURF_V_UPDATE_LOCK", 1, 1, &umr_bitfield_default },
+	 { "BLND_DCP_CUR_V_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "BLND_DCP_CUR2_V_UPDATE_LOCK", 24, 24, &umr_bitfield_default },
+	 { "BLND_SCL_V_UPDATE_LOCK", 28, 28, &umr_bitfield_default },
+	 { "BLND_BLND_V_UPDATE_LOCK", 29, 29, &umr_bitfield_default },
+	 { "BLND_V_UPDATE_LOCK_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_DEBUG[] = {
+	 { "BLND_CNV_MUX_SELECT", 0, 0, &umr_bitfield_default },
+	 { "BLND_DEBUG", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_TEST_DEBUG_INDEX[] = {
+	 { "BLND_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "BLND_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_TEST_DEBUG_DATA[] = {
+	 { "BLND_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_REG_UPDATE_STATUS[] = {
+	 { "DCP_BLNDC_GRPH_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
+	 { "DCP_BLNDC_GRPH_SURF_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_SURF_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
+	 { "DCP_BLNDC_CUR_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
+	 { "DCP_BLNDO_CUR_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
+	 { "SCL_BLNDC_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "SCL_BLNDO_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
+	 { "BLND_BLNDC_UPDATE_PENDING", 10, 10, &umr_bitfield_default },
+	 { "BLND_BLNDO_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_3D_STRUCTURE_CONTROL[] = {
+	 { "CRTC_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_EN_DB", 4, 4, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_VSYNC_GAP[] = {
+	 { "CRTC_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_WINDOW[] = {
+	 { "CRTC_GSL_WINDOW_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_GSL_WINDOW_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_CONTROL[] = {
+	 { "CRTC_GSL_CHECK_LINE_NUM", 0, 13, &umr_bitfield_default },
+	 { "CRTC_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_BLANK_EARLY_NUM[] = {
+	 { "CRTC_H_BLANK_EARLY_NUM", 0, 9, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_EARLY_NUM_DIS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_TOTAL[] = {
+	 { "CRTC_H_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_BLANK_START_END[] = {
+	 { "CRTC_H_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_A[] = {
+	 { "CRTC_H_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_A_CNTL[] = {
+	 { "CRTC_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_B[] = {
+	 { "CRTC_H_SYNC_B_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_B_CNTL[] = {
+	 { "CRTC_H_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_B_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VBI_END[] = {
+	 { "CRTC_VBI_V_END", 0, 13, &umr_bitfield_default },
+	 { "CRTC_VBI_H_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL[] = {
+	 { "CRTC_V_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_MIN[] = {
+	 { "CRTC_V_TOTAL_MIN", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_MAX[] = {
+	 { "CRTC_V_TOTAL_MAX", 0, 13, &umr_bitfield_default },
+	 { "CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_CONTROL[] = {
+	 { "CRTC_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_TOTAL_MAX_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_ON_EVENT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_TO_MASTER_VSYNC", 12, 12, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK_EN", 15, 15, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_INT_STATUS[] = {
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VSYNC_NOM_INT_STATUS[] = {
+	 { "CRTC_VSYNC_NOM", 0, 0, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_BLANK_START_END[] = {
+	 { "CRTC_V_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_A[] = {
+	 { "CRTC_V_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_A_CNTL[] = {
+	 { "CRTC_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_B[] = {
+	 { "CRTC_V_SYNC_B_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_B_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_B_CNTL[] = {
+	 { "CRTC_V_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DTMTEST_CNTL[] = {
+	 { "CRTC_DTMTEST_CRTC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_CLK_DIV", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DTMTEST_STATUS_POSITION[] = {
+	 { "CRTC_DTMTEST_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGA_CNTL[] = {
+	 { "CRTC_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGA_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGA_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGB_CNTL[] = {
+	 { "CRTC_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGB_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGB_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FORCE_COUNT_NOW_CNTL[] = {
+	 { "CRTC_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FLOW_CONTROL[] = {
+	 { "CRTC_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_FORCE_NEXT_EYE[] = {
+	 { "CRTC_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_FRAME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LINE_COUNTER", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_AVSYNC_COUNTER[] = {
+	 { "CRTC_AVSYNC_COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CONTROL[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SYNC_RESET_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
+	 { "CRTC_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
+	 { "CRTC_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_HBLANK_EARLY_CONTROL", 20, 22, &umr_bitfield_default },
+	 { "CRTC_DISP_READ_REQUEST_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SOF_PULL_EN", 29, 29, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LOCK_SNAPSHOT", 30, 30, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_VSYNC_N_HSYNC_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_CONTROL[] = {
+	 { "CRTC_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERLACE_CONTROL[] = {
+	 { "CRTC_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERLACE_STATUS[] = {
+	 { "CRTC_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FIELD_INDICATION_CONTROL[] = {
+	 { "CRTC_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_PIXEL_DATA_READBACK0[] = {
+	 { "CRTC_PIXEL_DATA_BLUE_CB", 0, 11, &umr_bitfield_default },
+	 { "CRTC_PIXEL_DATA_GREEN_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_PIXEL_DATA_READBACK1[] = {
+	 { "CRTC_PIXEL_DATA_RED_CR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS[] = {
+	 { "CRTC_V_BLANK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A", 2, 2, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "CRTC_V_START_LINE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_H_BLANK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_POSITION[] = {
+	 { "CRTC_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_NOM_VERT_POSITION[] = {
+	 { "CRTC_VERT_COUNT_NOM", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_FRAME_COUNT[] = {
+	 { "CRTC_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_VF_COUNT[] = {
+	 { "CRTC_VF_COUNT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_HV_COUNT[] = {
+	 { "CRTC_HV_COUNT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_COUNT_CONTROL[] = {
+	 { "CRTC_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_COUNT_RESET[] = {
+	 { "CRTC_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
+	 { "CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERT_SYNC_CONTROL[] = {
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "CRTC_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_STATUS[] = {
+	 { "CRTC_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EYE_FLAG", 20, 20, &umr_bitfield_default },
+	 { "CRTC_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_CONTROL[] = {
+	 { "CRTC_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 13, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT_POLARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EYE_FLAG_POLARITY", 17, 17, &umr_bitfield_default },
+	 { "CRTC_DISABLE_STEREOSYNC_OUTPUT_FOR_DP", 18, 18, &umr_bitfield_default },
+	 { "CRTC_DISABLE_FIELD_NUM", 19, 19, &umr_bitfield_default },
+	 { "CRTC_DISABLE_V_BLANK_FOR_DP_FIX", 20, 20, &umr_bitfield_default },
+	 { "CRTC_STEREO_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_STATUS[] = {
+	 { "CRTC_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_CONTROL[] = {
+	 { "CRTC_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_POSITION[] = {
+	 { "CRTC_SNAPSHOT_VERT_COUNT", 0, 13, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_HORZ_COUNT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_FRAME[] = {
+	 { "CRTC_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_START_LINE_CONTROL[] = {
+	 { "CRTC_PROGRESSIVE_START_LINE_EARLY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_START_LINE_EARLY", 1, 1, &umr_bitfield_default },
+	 { "CRTC_PREFETCH_EN", 2, 2, &umr_bitfield_default },
+	 { "CRTC_LEGACY_REQUESTOR_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_ADVANCED_START_LINE_POSITION", 12, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERRUPT_CONTROL[] = {
+	 { "CRTC_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_MSK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_TYPE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_UPDATE_LOCK[] = {
+	 { "CRTC_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DOUBLE_BUFFER_CONTROL[] = {
+	 { "CRTC_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CRTC_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VGA_PARAMETER_CAPTURE_MODE[] = {
+	 { "CRTC_VGA_PARAMETER_CAPTURE_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_CONTROL[] = {
+	 { "CRTC_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_PARAMETERS[] = {
+	 { "CRTC_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_COLOR[] = {
+	 { "CRTC_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MASTER_UPDATE_LOCK[] = {
+	 { "MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "GSL_CONTROL_MASTER_UPDATE_LOCK", 8, 8, &umr_bitfield_default },
+	 { "UNDERFLOW_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MASTER_UPDATE_MODE[] = {
+	 { "MASTER_UPDATE_MODE", 0, 2, &umr_bitfield_default },
+	 { "MASTER_UPDATE_INTERLACED_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_INBAND_CNTL_INSERT[] = {
+	 { "CRTC_MVP_INBAND_OUT_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[] = {
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_STATUS[] = {
+	 { "CRTC_FLIP_NOW_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FLIP_NOW_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MASTER_EN[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_ALLOW_STOP_OFF_V_CNT[] = {
+	 { "CRTC_ALLOW_STOP_OFF_V_CNT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_UPDATE_INT_STATUS[] = {
+	 { "CRTC_V_UPDATE_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_DEBUG_INDEX[] = {
+	 { "CRTC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_DEBUG_DATA[] = {
+	 { "CRTC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_OVERSCAN_COLOR[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE", 0, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN", 10, 19, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_OVERSCAN_COLOR_EXT[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_DATA_COLOR[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_DATA_COLOR_EXT[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLACK_COLOR[] = {
+	 { "CRTC_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLACK_COLOR_EXT[] = {
+	 { "CRTC_BLACK_COLOR_B_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT0_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT0_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT1_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_LINE_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT1_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT2_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_LINE_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT2_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC_CNTL[] = {
+	 { "CRTC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "CRTC_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_CRC0_SELECT", 20, 22, &umr_bitfield_default },
+	 { "CRTC_CRC1_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_DATA_RG[] = {
+	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_DATA_B[] = {
+	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_DATA_RG[] = {
+	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_DATA_B[] = {
+	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW", 5, 6, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE", 9, 9, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY", 12, 12, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY", 13, 13, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INTERLACE_MODE", 14, 14, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE", 24, 26, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_WINDOW_START[] = {
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_START_X", 0, 13, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_START_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_WINDOW_END[] = {
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_END_X", 0, 13, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_END_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE", 20, 20, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INT_TYPE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATIC_SCREEN_CONTROL[] = {
+	 { "CRTC_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
+	 { "CRTC_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SS_STATUS", 25, 25, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
+	 { "CRTC_STATIC_SCREEN_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "CRTC_STATIC_SCREEN_OVERRIDE_VALUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_R[] = {
+	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_G[] = {
+	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_B[] = {
+	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEST_DEBUG_INDEX[] = {
+	 { "FMT_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FMT_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEST_DEBUG_DATA[] = {
+	 { "FMT_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DYNAMIC_EXP_CNTL[] = {
+	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CONTROL[] = {
+	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "FMT_STEREOSYNC_OVR_POL", 4, 4, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX", 8, 11, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP", 12, 13, &umr_bitfield_default },
+	 { "FMT_PIXEL_ENCODING", 16, 17, &umr_bitfield_default },
+	 { "FMT_SUBSAMPLING_MODE", 18, 19, &umr_bitfield_default },
+	 { "FMT_SUBSAMPLING_ORDER", 20, 20, &umr_bitfield_default },
+	 { "FMT_CBCR_BIT_REDUCTION_BYPASS", 21, 21, &umr_bitfield_default },
+	 { "FMT_SRC_SELECT", 24, 26, &umr_bitfield_default },
+	 { "FMT_420_PIXEL_PHASE_LOCKED", 30, 30, &umr_bitfield_default },
+	 { "FMT_420_PIXEL_PHASE_LOCKED_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_SIDE_BY_SIDE_STEREO_CONTROL[] = {
+	 { "FMT_SIDE_BY_SIDE_STEREO_ACTIVE_WIDTH", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_420_HBLANK_EARLY_START[] = {
+	 { "FMT_420_HBLANK_EARLY_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_BIT_DEPTH_CONTROL[] = {
+	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
+	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
+	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
+	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
+	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
+	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_R_SEED[] = {
+	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_G_SEED[] = {
+	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_B_SEED[] = {
+	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_CNTL[] = {
+	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_CNTL[] = {
+	 { "FMT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_DTMTEST_CRC_EN", 1, 1, &umr_bitfield_default },
+	 { "FMT_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "FMT_ONE_SHOT_CRC_PENDING", 5, 5, &umr_bitfield_default },
+	 { "FMT_CRC_INCLUDE_OVERSCAN", 6, 6, &umr_bitfield_default },
+	 { "FMT_CRC_ONLY_BLANKB", 8, 8, &umr_bitfield_default },
+	 { "FMT_CRC_PSR_MODE_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "FMT_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "FMT_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "FMT_CRC_EVEN_ODD_PIX_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FMT_CRC_EVEN_ODD_PIX_SELECT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_RED_GREEN_MASK[] = {
+	 { "FMT_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_BLUE_CONTROL_MASK[] = {
+	 { "FMT_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_RED_GREEN[] = {
+	 { "FMT_CRC_SIG_RED", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_BLUE_CONTROL[] = {
+	 { "FMT_CRC_SIG_BLUE", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_CONTROL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DEBUG_CNTL[] = {
+	 { "FMT_DEBUG_COLOR_SELECT", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMA_POSITION_LOWER_BASE_ADDRESS[] = {
+	 { "DMA_POSITION_BUFFER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS", 1, 6, &umr_bitfield_default },
+	 { "DMA_POSITION_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_M[] = {
+	 { "DP_AUX_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1C[] = {
+	 { "DCIO_DEBUG_UNIPHYA_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMA_POSITION_UPPER_BASE_ADDRESS[] = {
+	 { "DMA_POSITION_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_N[] = {
+	 { "DP_AUX_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1D[] = {
+	 { "DCIO_DEBUG_UNIPHYB_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_O[] = {
+	 { "DP_AUX_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1E[] = {
+	 { "DCIO_DEBUG_UNIPHYC_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1E[] = {
+	 { "GRPH_DEC_RD1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_P[] = {
+	 { "DP_AUX_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1F[] = {
+	 { "DCIO_DEBUG_UNIPHYD_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1F[] = {
+	 { "GRPH_DEC_RD0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_WORSTCASE_LATENCY_COUNT[] = {
+	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL2[] = {
+	 { "INPUT_CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL2[] = {
+	 { "CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMIF_DEBUG02_CORE0[] = {
+	 { "DB_DATA", 0, 15, &umr_bitfield_default },
+	 { "MC_RDRET_COUNT_EN", 16, 16, &umr_bitfield_default },
+	 { "MC_RDRET_COUNTER", 17, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR1[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_CONTROL[] = {
+	 { "CONTROLLER_RESET", 0, 0, &umr_bitfield_default },
+	 { "FLUSH_CONTROL", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_UNSOLICITED_RESPONSE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG2[] = {
+	 { "DCIO_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG1[] = {
+	 { "FMT_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR02[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ02[] = {
+	 { "SEQ_MAP0_EN", 0, 0, &umr_bitfield_default },
+	 { "SEQ_MAP1_EN", 1, 1, &umr_bitfield_default },
+	 { "SEQ_MAP2_EN", 2, 2, &umr_bitfield_default },
+	 { "SEQ_MAP3_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
+	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
+	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
+	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
+	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
+	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
+	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
+	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
+	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX_DEBUG_Q[] = {
+	 { "DP_AUX_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG20[] = {
+	 { "DCIO_DEBUG_UNIPHYE_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
+	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG21[] = {
+	 { "DCIO_DEBUG_UNIPHYF_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
+	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG22[] = {
+	 { "DCIO_DEBUG_UNIPHYG_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT22[] = {
+	 { "GRPH_LATCH_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+	 { "STREAM_TYPE_R", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
+	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG23[] = {
+	 { "DCIO_DEBUG_UNIPHYLPA_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
+	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG24[] = {
+	 { "DCIO_DEBUG_UNIPHYLPB_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
+	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
+	 { "LFE_PLAYBACK_LEVEL", 24, 25, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG25[] = {
+	 { "DCIO_DEBUG_DCRXPHY_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
+	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG26[] = {
+	 { "DCIO_DEBUG_DPHY_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
+	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG27[] = {
+	 { "DCIO_DEBUG_DACA_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[] = {
+	 { "CC", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[] = {
+	 { "KEEPALIVE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
+	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG28[] = {
+	 { "DCIO_DEBUG_ZCAL_CFG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CNTL[] = {
+	 { "FBC_GRPH_COMP_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_SRC_SEL", 1, 3, &umr_bitfield_default },
+	 { "FBC_COMP_CLK_GATE_EN", 8, 8, &umr_bitfield_default },
+	 { "FBC_DECOMP_CLK_GATE_EN", 10, 10, &umr_bitfield_default },
+	 { "FBC_COHERENCY_MODE", 16, 17, &umr_bitfield_default },
+	 { "FBC_SOFT_COMPRESS_EN", 25, 25, &umr_bitfield_default },
+	 { "FBC_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_FORCE_CLEAR_MASK[] = {
+	 { "FBC_IDLE_FORCE_CLEAR_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_START_STOP_DELAY[] = {
+	 { "FBC_DECOMP_START_DELAY", 0, 4, &umr_bitfield_default },
+	 { "FBC_DECOMP_STOP_DELAY", 7, 7, &umr_bitfield_default },
+	 { "FBC_COMP_START_DELAY", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_CNTL[] = {
+	 { "FBC_MIN_COMPRESSION", 0, 3, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO08_EN", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO16_EN", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB04_EN", 18, 18, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB08_EN", 19, 19, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB16_EN", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_MODE[] = {
+	 { "FBC_RLE_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_DPCM4_RGB_EN", 8, 8, &umr_bitfield_default },
+	 { "FBC_DPCM8_RGB_EN", 9, 9, &umr_bitfield_default },
+	 { "FBC_DPCM4_YUV_EN", 10, 10, &umr_bitfield_default },
+	 { "FBC_DPCM8_YUV_EN", 11, 11, &umr_bitfield_default },
+	 { "FBC_IND_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG0[] = {
+	 { "FBC_PERF_MUX0", 0, 7, &umr_bitfield_default },
+	 { "FBC_PERF_MUX1", 8, 15, &umr_bitfield_default },
+	 { "FBC_COMP_WAKE_DIS", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG0", 17, 23, &umr_bitfield_default },
+	 { "FBC_DEBUG_MUX", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG1[] = {
+	 { "FBC_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG2[] = {
+	 { "FBC_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT0[] = {
+	 { "FBC_IND_LUT0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT1[] = {
+	 { "FBC_IND_LUT1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT2[] = {
+	 { "FBC_IND_LUT2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT3[] = {
+	 { "FBC_IND_LUT3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT4[] = {
+	 { "FBC_IND_LUT4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT5[] = {
+	 { "FBC_IND_LUT5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT6[] = {
+	 { "FBC_IND_LUT6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT7[] = {
+	 { "FBC_IND_LUT7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT8[] = {
+	 { "FBC_IND_LUT8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT9[] = {
+	 { "FBC_IND_LUT9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT10[] = {
+	 { "FBC_IND_LUT10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT11[] = {
+	 { "FBC_IND_LUT11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT12[] = {
+	 { "FBC_IND_LUT12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT13[] = {
+	 { "FBC_IND_LUT13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT14[] = {
+	 { "FBC_IND_LUT14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT15[] = {
+	 { "FBC_IND_LUT15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_01[] = {
+	 { "FBC_CSM_REGION_OFFSET_0", 0, 11, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_1", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_23[] = {
+	 { "FBC_CSM_REGION_OFFSET_2", 0, 11, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_3", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CLIENT_REGION_MASK[] = {
+	 { "FBC_MEMORY_REGION_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_COMP[] = {
+	 { "FBC_COMP_SWAP", 0, 1, &umr_bitfield_default },
+	 { "FBC_COMP_RSIZE", 3, 3, &umr_bitfield_default },
+	 { "FBC_COMP_BUSY_HYSTERESIS", 4, 7, &umr_bitfield_default },
+	 { "FBC_COMP_CLK_CNTL", 8, 9, &umr_bitfield_default },
+	 { "FBC_COMP_PRIVILEGED_ACCESS_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "FBC_COMP_ADDRESS_TRANSLATION_ENABLE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR[] = {
+	 { "FBC_DEBUG_CSR_ADDR", 0, 11, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_WR_DATA", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_RD_DATA", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA[] = {
+	 { "FBC_DEBUG_CSR_RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA[] = {
+	 { "FBC_DEBUG_CSR_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_RDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_WDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_MISC[] = {
+	 { "FBC_DECOMPRESS_ERROR", 0, 1, &umr_bitfield_default },
+	 { "FBC_STOP_ON_ERROR", 2, 2, &umr_bitfield_default },
+	 { "FBC_INVALIDATE_ON_ERROR", 3, 3, &umr_bitfield_default },
+	 { "FBC_ERROR_PIXEL", 4, 7, &umr_bitfield_default },
+	 { "FBC_DIVIDE_X", 8, 9, &umr_bitfield_default },
+	 { "FBC_DIVIDE_Y", 10, 10, &umr_bitfield_default },
+	 { "FBC_RSM_WRITE_VALUE", 11, 11, &umr_bitfield_default },
+	 { "FBC_RSM_UNCOMP_DATA_IMMEDIATELY", 12, 12, &umr_bitfield_default },
+	 { "FBC_STOP_ON_HFLIP_EVENT", 13, 13, &umr_bitfield_default },
+	 { "FBC_DECOMPRESS_ERROR_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "FBC_RESET_AT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FBC_RESET_AT_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "FBC_SLOW_REQ_INTERVAL", 24, 28, &umr_bitfield_default },
+	 { "FBC_FORCE_DECOMPRESSOR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_STATUS[] = {
+	 { "FBC_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_INDEX[] = {
+	 { "FBC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FBC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_DATA[] = {
+	 { "FBC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_ALPHA_CNTL[] = {
+	 { "FBC_ALPHA_COMP_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_FORCE_COPY_TO_COMP_BUF", 4, 4, &umr_bitfield_default },
+	 { "FBC_ZERO_ALPHA_CHUNK_SKIP_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_ALPHA_RGB_OVERRIDE[] = {
+	 { "FBC_ZERO_ALPHA_R_VAL", 0, 7, &umr_bitfield_default },
+	 { "FBC_ZERO_ALPHA_G_VAL", 12, 19, &umr_bitfield_default },
+	 { "FBC_ZERO_ALPHA_B_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL1[] = {
+	 { "MVP_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_MIXER_MODE", 4, 6, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK", 9, 9, &umr_bitfield_default },
+	 { "MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE", 10, 10, &umr_bitfield_default },
+	 { "MVP_RATE_CONTROL", 12, 12, &umr_bitfield_default },
+	 { "MVP_CHANNEL_CONTROL", 16, 16, &umr_bitfield_default },
+	 { "MVP_GPU_CHAIN_LOCATION", 20, 21, &umr_bitfield_default },
+	 { "MVP_DISABLE_MSB_EXPAND", 24, 24, &umr_bitfield_default },
+	 { "MVP_30BPP_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_A", 30, 30, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_B", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL2[] = {
+	 { "MVP_MUX_DE_DVOCNTL0_SEL", 0, 0, &umr_bitfield_default },
+	 { "MVP_MUX_DE_DVOCNTL2_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_MUXA_CLK_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MUXB_CLK_SEL", 12, 12, &umr_bitfield_default },
+	 { "MVP_DVOCNTL_MUX", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_OUT_EN", 24, 24, &umr_bitfield_default },
+	 { "MVP_SWAP_AB_IN_DC_DDR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_CONTROL[] = {
+	 { "MVP_STOP_SLAVE_WM", 0, 7, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_WM", 8, 15, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_CNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_STATUS[] = {
+	 { "MVP_FIFO_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_ACK", 16, 16, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW", 20, 20, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_ACK", 28, 28, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_MASK", 30, 30, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_SLAVE_STATUS[] = {
+	 { "MVP_SLAVE_PIXELS_PER_LINE_RCVED", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINES_PER_FRAME_RCVED", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_INBAND_CNTL_CAP[] = {
+	 { "MVP_IGNOR_INBAND_CNTL", 0, 0, &umr_bitfield_default },
+	 { "MVP_PASSING_INBAND_CNTL_EN", 4, 4, &umr_bitfield_default },
+	 { "MVP_INBAND_CNTL_CHAR_CAP", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_BLACK_KEYER[] = {
+	 { "MVP_BLACK_KEYER_R", 0, 9, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_G", 10, 19, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_B", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_CNTL[] = {
+	 { "MVP_CRC_BLUE_MASK", 0, 7, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_MASK", 8, 15, &umr_bitfield_default },
+	 { "MVP_CRC_RED_MASK", 16, 23, &umr_bitfield_default },
+	 { "MVP_CRC_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_CRC_CONT_EN", 29, 29, &umr_bitfield_default },
+	 { "MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_BLUE_GREEN[] = {
+	 { "MVP_CRC_BLUE_RESULT", 0, 15, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_RESULT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_RED[] = {
+	 { "MVP_CRC_RED_RESULT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL3[] = {
+	 { "MVP_RESET_IN_BETWEEN_FRAMES", 0, 0, &umr_bitfield_default },
+	 { "MVP_DDR_SC_AB_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_DDR_SC_B_START_MODE", 8, 8, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_CASCADE_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_48BIT_EN", 24, 24, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_CAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL1[] = {
+	 { "MVP_SLAVE_PIXEL_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINE_ERROR_CNT", 16, 28, &umr_bitfield_default },
+	 { "MVP_SLAVE_DATA_CHK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL2[] = {
+	 { "MVP_SLAVE_FRAME_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_FRAME_ERROR_CNT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_INDEX[] = {
+	 { "MVP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MVP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_DATA[] = {
+	 { "MVP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_DEBUG[] = {
+	 { "MVP_SWAP_LOCK_IN_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_EN", 1, 1, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_IN_SEL", 2, 2, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_SEL", 3, 3, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP", 4, 4, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP", 5, 5, &umr_bitfield_default },
+	 { "MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR", 6, 6, &umr_bitfield_default },
+	 { "MVP_DIS_READ_POINTER_RESET_DELAY", 7, 7, &umr_bitfield_default },
+	 { "MVP_DEBUG_BITS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_CONFIG[] = {
+	 { "PIPE0_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_ENABLE[] = {
+	 { "PIPE0_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_STATUS[] = {
+	 { "PIPE0_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE0_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE0_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_CONFIG[] = {
+	 { "PIPE1_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_ENABLE[] = {
+	 { "PIPE1_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_STATUS[] = {
+	 { "PIPE1_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE1_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE1_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE1_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE1_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_CONFIG[] = {
+	 { "PIPE2_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_ENABLE[] = {
+	 { "PIPE2_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_STATUS[] = {
+	 { "PIPE2_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE2_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE2_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE2_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE2_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_CONFIG[] = {
+	 { "PIPE3_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_ENABLE[] = {
+	 { "PIPE3_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_STATUS[] = {
+	 { "PIPE3_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE3_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE3_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE3_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE3_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_CONFIG[] = {
+	 { "PIPE4_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_ENABLE[] = {
+	 { "PIPE4_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_STATUS[] = {
+	 { "PIPE4_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE4_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE4_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE4_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE4_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_CONFIG[] = {
+	 { "PIPE5_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_ENABLE[] = {
+	 { "PIPE5_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_STATUS[] = {
+	 { "PIPE5_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE5_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE5_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE5_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE5_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_IP_REQUEST_CNTL[] = {
+	 { "IP_REQUEST_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_CONFIG_REG[] = {
+	 { "PGFSM_CONFIG_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_WRITE_REG[] = {
+	 { "PGFSM_WRITE_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGCNTL_STATUS_REG[] = {
+	 { "SWREQ_RWOP_BUSY", 0, 0, &umr_bitfield_default },
+	 { "SWREQ_RWOP_FORCE", 1, 1, &umr_bitfield_default },
+	 { "IPREQ_IGNORE_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DCPG_ECO_DEBUG", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_INDEX[] = {
+	 { "DCPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_DATA[] = {
+	 { "DCPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_INTERRUPT_STATUS[] = {
+	 { "DCFE0_POWER_UP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_POWER_DOWN_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE1_POWER_UP_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE1_POWER_DOWN_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE2_POWER_UP_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE2_POWER_DOWN_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_POWER_UP_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_POWER_DOWN_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_POWER_UP_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_POWER_DOWN_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE5_POWER_UP_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE5_POWER_DOWN_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFEV0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFEV0_POWER_DOWN_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DSI_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DSI_POWER_DOWN_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFEV1_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFEV1_POWER_DOWN_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_INTERRUPT_CONTROL[] = {
+	 { "DCFE0_POWER_UP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_POWER_UP_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_POWER_DOWN_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_POWER_DOWN_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE1_POWER_UP_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCFE1_POWER_UP_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE1_POWER_DOWN_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCFE1_POWER_DOWN_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE2_POWER_UP_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCFE2_POWER_UP_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE2_POWER_DOWN_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCFE2_POWER_DOWN_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE3_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCFE3_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE3_POWER_DOWN_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCFE3_POWER_DOWN_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCFE4_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE4_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCFE4_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_POWER_UP_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_POWER_UP_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFEV0_POWER_UP_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCFEV0_POWER_UP_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFEV0_POWER_DOWN_INT_MASK", 26, 26, &umr_bitfield_default },
+	 { "DCFEV0_POWER_DOWN_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "DSI_POWER_UP_INT_MASK", 28, 28, &umr_bitfield_default },
+	 { "DSI_POWER_UP_INT_CLEAR", 29, 29, &umr_bitfield_default },
+	 { "DSI_POWER_DOWN_INT_MASK", 30, 30, &umr_bitfield_default },
+	 { "DSI_POWER_DOWN_INT_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_INTERRUPT_CONTROL2[] = {
+	 { "DCFEV1_POWER_UP_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCFEV1_POWER_UP_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFEV1_POWER_DOWN_INT_MASK", 26, 26, &umr_bitfield_default },
+	 { "DCFEV1_POWER_DOWN_INT_CLEAR", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIFV_STATUS[] = {
+	 { "DMIFV_MC_SEND_ON_IDLE", 0, 3, &umr_bitfield_default },
+	 { "DMIFV_CLEAR_MC_SEND_ON_IDLE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_CONTROL[] = {
+	 { "DMIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_GROUP_REQUESTS_IN_CHUNK", 2, 2, &umr_bitfield_default },
+	 { "DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT", 4, 4, &umr_bitfield_default },
+	 { "DMIF_REQ_BURST_SIZE", 8, 10, &umr_bitfield_default },
+	 { "DMIF_UNDERFLOW_RECOVERY_EN", 11, 11, &umr_bitfield_default },
+	 { "DMIF_FORCE_TOTAL_REQ_BURST_SIZE", 12, 16, &umr_bitfield_default },
+	 { "DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS", 17, 22, &umr_bitfield_default },
+	 { "DMIF_DELAY_ARBITRATION", 24, 28, &umr_bitfield_default },
+	 { "DMIF_CHUNK_BUFF_MARGIN", 29, 30, &umr_bitfield_default },
+	 { "DMIF_PSTATE_URGENT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS[] = {
+	 { "DMIF_MC_SEND_ON_IDLE", 0, 5, &umr_bitfield_default },
+	 { "DMIF_CLEAR_MC_SEND_ON_IDLE", 8, 13, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_URGENT_ONLY", 17, 17, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT", 20, 23, &umr_bitfield_default },
+	 { "DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT", 24, 27, &umr_bitfield_default },
+	 { "DMIF_UNDERFLOW", 28, 28, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_TAP_POINT", 29, 30, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_REQ_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_HW_DEBUG[] = {
+	 { "DMIF_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ARBITRATION_CONTROL[] = {
+	 { "DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "PIPE_SWITCH_EFFICIENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[] = {
+	 { "PORTID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CUMULATIVE_LATENCY_COUNT[] = {
+	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL3[] = {
+	 { "INPUT_CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL3[] = {
+	 { "CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTATE_CHANGE_STATUS[] = {
+	 { "STATE_CHANGE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR2[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG3[] = {
+	 { "DCIO_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG2[] = {
+	 { "FMT_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR03[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ03[] = {
+	 { "SEQ_FONT_B1", 0, 0, &umr_bitfield_default },
+	 { "SEQ_FONT_B2", 1, 1, &umr_bitfield_default },
+	 { "SEQ_FONT_A1", 2, 2, &umr_bitfield_default },
+	 { "SEQ_FONT_A2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_FONT_B0", 4, 4, &umr_bitfield_default },
+	 { "SEQ_FONT_A0", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_P_VMID[] = {
+	 { "P_VMID_PIPE0", 0, 3, &umr_bitfield_default },
+	 { "P_VMID_PIPE1", 4, 7, &umr_bitfield_default },
+	 { "P_VMID_PIPE2", 8, 11, &umr_bitfield_default },
+	 { "P_VMID_PIPE3", 12, 15, &umr_bitfield_default },
+	 { "P_VMID_PIPE4", 16, 19, &umr_bitfield_default },
+	 { "P_VMID_PIPE5", 20, 23, &umr_bitfield_default },
+	 { "P_VMID_PIPE6", 24, 27, &umr_bitfield_default },
+	 { "P_VMID_PIPE7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_INDEX[] = {
+	 { "DMIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_DATA[] = {
+	 { "DMIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CALC[] = {
+	 { "ADDR_CONFIG_PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ADDR_CONFIG_ROW_SIZE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS2[] = {
+	 { "DMIF_PIPE0_DISPCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DMIF_PIPE1_DISPCLK_STATUS", 1, 1, &umr_bitfield_default },
+	 { "DMIF_PIPE2_DISPCLK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DMIF_PIPE3_DISPCLK_STATUS", 3, 3, &umr_bitfield_default },
+	 { "DMIF_PIPE4_DISPCLK_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DMIF_PIPE5_DISPCLK_STATUS", 5, 5, &umr_bitfield_default },
+	 { "DMIF_CHUNK_TRACKER_SCLK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DMIF_FBC_TRACKER_SCLK_STATUS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLOW_POWER_TILING_CONTROL[] = {
+	 { "LOW_POWER_TILING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_MODE", 3, 4, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_PIPES", 5, 7, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_BANKS", 8, 10, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE", 11, 11, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROW_SIZE", 12, 14, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROWS_PER_CHAN", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_CONTROL[] = {
+	 { "MCIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "ADDRESS_TRANSLATION_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "PRIVILEGED_ACCESS_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MCIF_SLOW_REQ_INTERVAL", 12, 15, &umr_bitfield_default },
+	 { "LOW_READ_URG_LEVEL", 16, 23, &umr_bitfield_default },
+	 { "MC_CLEAN_DEASSERT_LATENCY", 24, 29, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_URGENT_ONLY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WRITE_COMBINE_CONTROL[] = {
+	 { "MCIF_WRITE_COMBINE_TIMEOUT", 0, 7, &umr_bitfield_default },
+	 { "VIP_WRITE_COMBINE_TIMEOUT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_INDEX[] = {
+	 { "MCIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MCIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_DATA[] = {
+	 { "MCIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_VMID[] = {
+	 { "MCIF_WR_VMID", 0, 3, &umr_bitfield_default },
+	 { "VIP_WR_VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_MEM_CONTROL[] = {
+	 { "MCIFMEM_CACHE_MODE_DIS", 0, 0, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_MODE", 4, 5, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_SIZE", 8, 15, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_PIPE", 16, 18, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_TYPE", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
+	 { "DC_PIPE_DIS", 1, 6, &umr_bitfield_default },
+	 { "DC_UNDERLAY_PIPE_DIS", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DC_INTERFACE_NACK_STATUS[] = {
+	 { "DMIF_RDRET_NACK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DMIF_RDRET_NACK_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_TIMEOUT[] = {
+	 { "RBBMIF_TIMEOUT_DELAY", 0, 19, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_TO_REQ_HOLD", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_STATUS[] = {
+	 { "RBBMIF_TIMEOUT_CLIENTS_DEC", 0, 15, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_OP", 28, 28, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_RDWR_STATUS", 29, 29, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_ACK", 30, 30, &umr_bitfield_default },
+	 { "RBBMIF_TIMEOUT_MASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_TIMEOUT_DIS[] = {
+	 { "CLIENT0_TIMEOUT_DIS", 0, 0, &umr_bitfield_default },
+	 { "CLIENT1_TIMEOUT_DIS", 1, 1, &umr_bitfield_default },
+	 { "CLIENT2_TIMEOUT_DIS", 2, 2, &umr_bitfield_default },
+	 { "CLIENT3_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "CLIENT4_TIMEOUT_DIS", 4, 4, &umr_bitfield_default },
+	 { "CLIENT5_TIMEOUT_DIS", 5, 5, &umr_bitfield_default },
+	 { "CLIENT6_TIMEOUT_DIS", 6, 6, &umr_bitfield_default },
+	 { "CLIENT7_TIMEOUT_DIS", 7, 7, &umr_bitfield_default },
+	 { "CLIENT8_TIMEOUT_DIS", 8, 8, &umr_bitfield_default },
+	 { "CLIENT9_TIMEOUT_DIS", 9, 9, &umr_bitfield_default },
+	 { "CLIENT10_TIMEOUT_DIS", 10, 10, &umr_bitfield_default },
+	 { "CLIENT11_TIMEOUT_DIS", 11, 11, &umr_bitfield_default },
+	 { "CLIENT12_TIMEOUT_DIS", 12, 12, &umr_bitfield_default },
+	 { "CLIENT13_TIMEOUT_DIS", 13, 13, &umr_bitfield_default },
+	 { "CLIENT14_TIMEOUT_DIS", 14, 14, &umr_bitfield_default },
+	 { "CLIENT15_TIMEOUT_DIS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATUS[] = {
+	 { "DMIF_RDREQ_MEM1_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM2_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_STATE", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_STATE", 8, 8, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_STATE", 9, 10, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_STATE", 11, 11, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_STATE", 22, 22, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_STATE", 26, 27, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM3_PWR_STATE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATUS2[] = {
+	 { "DMIF1_ASYNC_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_STATE", 4, 4, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_STATE", 5, 6, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_STATE", 7, 8, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_STATE", 9, 9, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_STATE", 14, 14, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_PWR_STATE", 15, 16, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_STATE", 17, 18, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_STATE", 19, 19, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_STATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_CLK_CNTL[] = {
+	 { "DCI_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCI_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_M_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "SCLK_G_STREAM_AZ_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "SCLK_R_AZ_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_FBC_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIFV1_L_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "DISPCLK_G_VGA_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIFV1_C_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "DISPCLK_G_VIP_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "VPCLK_POL", 14, 14, &umr_bitfield_default },
+	 { "DISPCLK_G_DMCU_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "SCLK_G_DMIF_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "SCLK_G_DMIFTRK_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "SCLK_G_CNTL_AZ_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIFV0_L_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIFV0_C_GATE_DIS", 26, 26, &umr_bitfield_default },
+	 { "DCI_PG_TEST_CLK_SEL", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_CLK_RAMP_CNTL[] = {
+	 { "DISPCLK_G_MCIF_DWB_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "SCLK_G_MCIF_DWB_GATE_DIS", 1, 1, &umr_bitfield_default },
+	 { "DISPCLK_G_MCIF_CWB0_GATE_DIS", 2, 2, &umr_bitfield_default },
+	 { "SCLK_G_MCIF_CWB0_GATE_DIS", 3, 3, &umr_bitfield_default },
+	 { "DISPCLK_G_MCIF_CWB1_GATE_DIS", 4, 4, &umr_bitfield_default },
+	 { "SCLK_G_MCIF_CWB1_GATE_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL[] = {
+	 { "DMIF_RDREQ_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_FORCE", 3, 3, &umr_bitfield_default },
+	 { "MCIF_RDREQ_MEM_PWR_DIS", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_FORCE", 5, 5, &umr_bitfield_default },
+	 { "MCIF_WRREQ_MEM_PWR_DIS", 6, 6, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_FORCE", 7, 7, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_FORCE", 12, 12, &umr_bitfield_default },
+	 { "DMCU_IRAM_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_FORCE", 14, 15, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_DIS", 16, 16, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_FORCE", 17, 18, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_DIS", 19, 19, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_FORCE", 20, 21, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_DIS", 22, 22, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_FORCE", 23, 24, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_DIS", 25, 25, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_FORCE", 26, 27, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_DIS", 28, 28, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_FORCE", 29, 29, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL2[] = {
+	 { "DMIF0_ASYNC_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DMIF0_DATA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIF0_CHUNK_MEM_PWR_DIS", 7, 7, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "DMIF1_DATA_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_FORCE", 14, 14, &umr_bitfield_default },
+	 { "DMIF1_CHUNK_MEM_PWR_DIS", 15, 15, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_FORCE", 16, 17, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_DIS", 18, 18, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_FORCE", 19, 20, &umr_bitfield_default },
+	 { "DMIF2_DATA_MEM_PWR_DIS", 21, 21, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_FORCE", 22, 22, &umr_bitfield_default },
+	 { "DMIF2_CHUNK_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_FORCE", 24, 25, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_DIS", 26, 26, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_FORCE", 27, 28, &umr_bitfield_default },
+	 { "DMIF3_DATA_MEM_PWR_DIS", 29, 29, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_FORCE", 30, 30, &umr_bitfield_default },
+	 { "DMIF3_CHUNK_MEM_PWR_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL3[] = {
+	 { "DMIF4_ASYNC_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DMIF4_DATA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIF4_CHUNK_MEM_PWR_DIS", 7, 7, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_FORCE", 8, 9, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_FORCE", 11, 12, &umr_bitfield_default },
+	 { "DMIF5_DATA_MEM_PWR_DIS", 13, 13, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_FORCE", 14, 14, &umr_bitfield_default },
+	 { "DMIF5_CHUNK_MEM_PWR_DIS", 15, 15, &umr_bitfield_default },
+	 { "DMIF_RDREQ_MEM_PWR_MODE_SEL", 16, 17, &umr_bitfield_default },
+	 { "DMIF_ASYNC_MEM_PWR_MODE_SEL", 18, 19, &umr_bitfield_default },
+	 { "DMIF_DATA_MEM_PWR_MODE_SEL", 20, 21, &umr_bitfield_default },
+	 { "DMCU_ERAM_MEM_PWR_MODE_SEL", 22, 22, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_MODE_SEL", 23, 24, &umr_bitfield_default },
+	 { "MCIF_CWB0_MEM_PWR_MODE_SEL", 25, 26, &umr_bitfield_default },
+	 { "MCIF_CWB1_MEM_PWR_MODE_SEL", 27, 28, &umr_bitfield_default },
+	 { "MCIF_DWB_MEM_PWR_MODE_SEL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_INDEX[] = {
+	 { "DCI_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCI_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_DATA[] = {
+	 { "DCI_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_DEBUG_CONFIG[] = {
+	 { "DCI_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCI_DBG_BLOCK_SEL", 4, 7, &umr_bitfield_default },
+	 { "DCI_DBG_CLOCK_SEL", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRBBMIF_STATUS_FLAG[] = {
+	 { "RBBMIF_STATE", 0, 1, &umr_bitfield_default },
+	 { "RBBMIF_READ_TIMEOUT", 4, 4, &umr_bitfield_default },
+	 { "RBBMIF_FIFO_EMPTY", 5, 5, &umr_bitfield_default },
+	 { "RBBMIF_FIFO_FULL", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_SOFT_RESET[] = {
+	 { "VGA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "VIP_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "MCIF_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "FBC_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "DMIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DMIF1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DMIF2_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DMIF3_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "DMIF4_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DMIF5_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DCFEV0_L_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "DCFEV0_C_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "DCFEV1_L_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DCFEV1_C_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DMIFARB_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "MCIF_DWB_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "MCIF_CWB0_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "MCIF_CWB1_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "MCIF_WB_SOFT_RESET", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_URG_OVERRIDE[] = {
+	 { "DMIF_URG_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "DMIF_URG_OVERRIDE_LEVEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE6_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE7_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE6_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE7_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_REG_RD_STATUS[] = {
+	 { "DVMM_REG_RD_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_REG_RD_DATA[] = {
+	 { "DVMM_REG_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_REQ[] = {
+	 { "MAX_PTEREQ_TO_ISSUE", 0, 7, &umr_bitfield_default },
+	 { "HFLIP_PTEREQ_PER_CHUNK_INT", 8, 15, &umr_bitfield_default },
+	 { "HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_CNTL[] = {
+	 { "PDE_CACHE_INVALIDATE_CNTL", 0, 1, &umr_bitfield_default },
+	 { "DEBUG_SYSTEM_ACCESS_MODE", 4, 5, &umr_bitfield_default },
+	 { "FORCE_SYSTEM_ACCESS_MODE", 7, 7, &umr_bitfield_default },
+	 { "DBG_DCE_VMID", 8, 11, &umr_bitfield_default },
+	 { "FORCE_DBG_DCE_VMID", 15, 15, &umr_bitfield_default },
+	 { "OVERRIDE_SNOOP", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_PDE_INVALIDATE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_FAULT_STATUS[] = {
+	 { "DVMM_FAULT_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_FAULT_ADDR[] = {
+	 { "DVMM_FAULT_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_PGMEM_CONTROL[] = {
+	 { "DVMM_PTE0_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "DVMM_PTE0_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "DVMM_PTE1_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "DVMM_PTE1_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "DVMM_PTE2_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "DVMM_PTE2_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "DVMM_PTE3_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "DVMM_PTE3_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "DVMM_PTE4_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "DVMM_PTE4_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "DVMM_PTE5_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "DVMM_PTE5_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+	 { "DVMM_PTE6_MEM_PWR_FORCE", 18, 19, &umr_bitfield_default },
+	 { "DVMM_PTE6_MEM_PWR_DIS", 20, 20, &umr_bitfield_default },
+	 { "DVMM_PTE7_MEM_PWR_FORCE", 21, 22, &umr_bitfield_default },
+	 { "DVMM_PTE7_MEM_PWR_DIS", 23, 23, &umr_bitfield_default },
+	 { "DVMM_PTE_MEM_PWR_MODE_SEL", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVMM_PTE_PGMEM_STATE[] = {
+	 { "DVMM_PIPE0_PTE_PGMEM_STATE", 0, 1, &umr_bitfield_default },
+	 { "DVMM_PIPE1_PTE_PGMEM_STATE", 2, 3, &umr_bitfield_default },
+	 { "DVMM_PIPE2_PTE_PGMEM_STATE", 4, 5, &umr_bitfield_default },
+	 { "DVMM_PIPE3_PTE_PGMEM_STATE", 6, 7, &umr_bitfield_default },
+	 { "DVMM_PIPE4_PTE_PGMEM_STATE", 8, 9, &umr_bitfield_default },
+	 { "DVMM_PIPE5_PTE_PGMEM_STATE", 10, 11, &umr_bitfield_default },
+	 { "DVMM_PIPE6_PTE_PGMEM_STATE", 12, 13, &umr_bitfield_default },
+	 { "DVMM_PIPE7_PTE_PGMEM_STATE", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL4[] = {
+	 { "MCIF_DWB_LUMA_MEM_EN_NUM", 0, 0, &umr_bitfield_default },
+	 { "MCIF_DWB_CHROMA_MEM_EN_NUM", 1, 1, &umr_bitfield_default },
+	 { "MCIF_CWB0_LUMA_MEM_EN_NUM", 2, 2, &umr_bitfield_default },
+	 { "MCIF_CWB0_CHROMA_MEM_EN_NUM", 3, 3, &umr_bitfield_default },
+	 { "MCIF_CWB1_LUMA_MEM_EN_NUM", 4, 4, &umr_bitfield_default },
+	 { "MCIF_CWB1_CHROMA_MEM_EN_NUM", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MISC[] = {
+	 { "MCIF_WB_URG_OVRD", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_URG_LVL", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATUS3[] = {
+	 { "MCIF_DWB_LUMA_MEM0_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "MCIF_DWB_LUMA_MEM1_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "MCIF_DWB_CHROMA_MEM0_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "MCIF_DWB_CHROMA_MEM1_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "MCIF_CWB0_LUMA_MEM0_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "MCIF_CWB0_LUMA_MEM1_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "MCIF_CWB0_CHROMA_MEM0_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "MCIF_CWB0_CHROMA_MEM1_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "MCIF_CWB1_LUMA_MEM0_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "MCIF_CWB1_LUMA_MEM1_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "MCIF_CWB1_CHROMA_MEM0_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "MCIF_CWB1_CHROMA_MEM1_PWR_STATE", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
+	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL1_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL2_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL2_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL2_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
+	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL6_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL6_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL6_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[] = {
+	 { "CONNECTION_LIST_ENTRY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
+	 { "MISC", 0, 3, &umr_bitfield_default },
+	 { "COLOR", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
+	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
+	 { "LOCATION", 0, 5, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[] = {
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 8, 8, &umr_bitfield_default },
+	 { "DP_CONNECTION", 9, 9, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[] = {
+	 { "LFE_PLAYBACK_LEVEL", 0, 1, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 3, 6, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[] = {
+	 { "DESCRIPTOR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "FORMAT_CODE", 3, 6, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[] = {
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[] = {
+	 { "MULTICHANNEL23_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[] = {
+	 { "MULTICHANNEL45_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[] = {
+	 { "MULTICHANNEL67_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[] = {
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[] = {
+	 { "SINK_INFO_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[] = {
+	 { "SINK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
+	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
+	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
+	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
+	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[] = {
+	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
+	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
+	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
+	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
+	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
+	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
+	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
+	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MC_PCIE_CLIENT_CONFIG[] = {
+	 { "XDMA_MC_PCIE_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING1[] = {
+	 { "XDMA_LOCAL_ARRAY_MODE", 0, 3, &umr_bitfield_default },
+	 { "XDMA_LOCAL_TILE_SPLIT", 4, 6, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_WIDTH", 8, 9, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MACRO_TILE_ASPECT", 12, 13, &umr_bitfield_default },
+	 { "XDMA_LOCAL_NUM_BANKS", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING2[] = {
+	 { "XDMA_LOCAL_PIPE_INTERLEAVE_SIZE", 0, 2, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MICRO_TILE_MODE", 20, 22, &umr_bitfield_default },
+	 { "XDMA_LOCAL_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_INTERRUPT[] = {
+	 { "XDMA_MSTR_MEM_URGENT_STAT", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_MASK", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_ACK", 10, 10, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_STAT", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_MASK", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_ACK", 18, 18, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_STAT", 20, 20, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_MASK", 21, 21, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_ACK", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_CLOCK_GATING_CNTL[] = {
+	 { "XDMA_SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "XDMA_SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "XDMA_SCLK_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "XDMA_SCLK_REG_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1", 18, 18, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4", 21, 21, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5", 22, 22, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SDYN_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MSTAT_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SSTAT_GATE_DIS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MEM_POWER_CNTL[] = {
+	 { "XDMA_MEM_CORE_IDLE_STATE", 0, 1, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_IDLE_STATE", 2, 3, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_PCIE_STATE", 19, 20, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_PCIE_TRANS", 21, 21, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_RD_STATE", 22, 23, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_RD_TRANS", 25, 25, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_WR_STATE", 26, 27, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_WR_TRANS", 28, 28, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_BIF_STATE", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MEM_IF_BIF_TRANS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_BIF_STATUS[] = {
+	 { "XDMA_IF_BIF_ERROR_STATUS", 0, 3, &umr_bitfield_default },
+	 { "XDMA_IF_BIF_ERROR_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PERF_MEAS_STATUS[] = {
+	 { "XDMA_PERF_MEAS_STATUS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_STATUS[] = {
+	 { "XDMA_MC_PCIEWR_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_DATA[] = {
+	 { "XDMA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CNTL[] = {
+	 { "XDMA_MSTR_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_READY", 14, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_DEBUG_MODE", 18, 18, &umr_bitfield_default },
+	 { "XDMA_MSTR_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "XDMA_MSTR_BIF_STALL_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_STATUS[] = {
+	 { "XDMA_MSTR_VCOUNT_CURRENT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_WRITE_LINE_CURRENT", 16, 27, &umr_bitfield_default },
+	 { "XDMA_MSTR_STATUS_SELECT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
+	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[] = {
+	 { "CONNECTION_LIST_LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_PITCH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_PITCH", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CMD_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_CMD_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_CMD_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_CMD_STALL_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PCIE_NACK_STATUS[] = {
+	 { "XDMA_MSTR_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_NACK_STATUS[] = {
+	 { "XDMA_MSTR_MEM_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_VSYNC_GSL_CHECK[] = {
+	 { "XDMA_MSTR_VSYNC_GSL_CHECK_SEL", 0, 2, &umr_bitfield_default },
+	 { "XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT", 8, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_RBBMIF_RDWR_CNTL[] = {
+	 { "XDMA_RBBMIF_RDWR_DELAY", 0, 2, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_TIMEOUT_DELAY", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_CONTROL[] = {
+	 { "XDMA_PG_CONTROL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_WDATA[] = {
+	 { "XDMA_PG_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_STATUS[] = {
+	 { "XDMA_SERDES_RDATA", 0, 23, &umr_bitfield_default },
+	 { "XDMA_PGFSM_READ_READY", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SERDES_BUSY", 25, 25, &umr_bitfield_default },
+	 { "XDMA_SERDES_SMU_POWER_STATUS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_AON_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_AON_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_AON_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+	 { "XDMA_DEBUG_SEL", 9, 9, &umr_bitfield_default },
+	 { "XDMA_DEBUG_OUT_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_AON_TEST_DEBUG_DATA[] = {
+	 { "XDMA_AON_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[] = {
+	 { "PORTID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CUMULATIVE_REQUEST_COUNT[] = {
+	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL4[] = {
+	 { "INPUT_CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL4[] = {
+	 { "CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR3[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_STATUS[] = {
+	 { "FLUSH_STATUS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG4[] = {
+	 { "DCIO_DEBUG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG3[] = {
+	 { "FMT_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR04[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ04[] = {
+	 { "SEQ_256K", 1, 1, &umr_bitfield_default },
+	 { "SEQ_ODDEVEN", 2, 2, &umr_bitfield_default },
+	 { "SEQ_CHAIN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
+	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PIPE_CNTL[] = {
+	 { "XDMA_MSTR_CACHE_LINES", 0, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_READ_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FRAME_MODE", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_INVALIDATE", 11, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_CHANNEL_ID", 12, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_FLIP_MODE", 15, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_MIN", 16, 23, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_ACTIVE", 24, 24, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FLUSHING", 25, 25, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FLIP_PENDING", 26, 26, &umr_bitfield_default },
+	 { "XDMA_MSTR_VSYNC_GSL_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "XDMA_MSTR_SUPERAA_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "XDMA_MSTR_HSYNC_GSL_GROUP", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_GSL_GROUP_MASTER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_READ_COMMAND[] = {
+	 { "XDMA_MSTR_REQUEST_SIZE", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_PREFETCH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CHANNEL_DIM[] = {
+	 { "XDMA_MSTR_CHANNEL_WIDTH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CHANNEL_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_HEIGHT[] = {
+	 { "XDMA_MSTR_ACTIVE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_FRAME_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_CACHE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_CACHE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE[] = {
+	 { "XDMA_MSTR_CACHE_PITCH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_TLB_PG_STATE", 29, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_TLB_PG_TRANS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CHANNEL_START[] = {
+	 { "XDMA_MSTR_CHANNEL_START_X", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CHANNEL_START_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_STATUS[] = {
+	 { "XDMA_MSTR_PERFMEAS_DATA", 0, 23, &umr_bitfield_default },
+	 { "XDMA_MSTR_PERFMEAS_INDEX", 24, 26, &umr_bitfield_default },
+	 { "XDMA_MSTR_PERFMEAS_INDEX_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_CNTL[] = {
+	 { "XDMA_MSTR_CACHE_BW_MEAS_ITER", 0, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_BW_SEGID_SEL", 12, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_BW_COUNTER_RST", 17, 17, &umr_bitfield_default },
+	 { "XDMA_MSTR_LT_MEAS_ITER", 19, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_LT_COUNTER_RST", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
+	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
+	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CNTL[] = {
+	 { "XDMA_SLV_READ_LINES", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_READY", 9, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "XDMA_SLV_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SLV_REQ_MAXED_OUT", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SLV_WB_BURST_RESET", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_ENABLE[] = {
+	 { "GRPH_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_CONTROL[] = {
+	 { "GRPH_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "GRPH_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "GRPH_Z", 4, 5, &umr_bitfield_default },
+	 { "GRPH_BANK_WIDTH_L", 6, 7, &umr_bitfield_default },
+	 { "GRPH_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT_L", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT_L", 13, 15, &umr_bitfield_default },
+	 { "GRPH_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "GRPH_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT_L", 18, 19, &umr_bitfield_default },
+	 { "GRPH_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "GRPH_PIPE_CONFIG", 24, 28, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE_L", 29, 30, &umr_bitfield_default },
+	 { "GRPH_COLOR_EXPANSION_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_CONTROL_C[] = {
+	 { "GRPH_BANK_WIDTH_C", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT_C", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT_C", 13, 15, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT_C", 18, 19, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE_C", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_CONTROL_EXP[] = {
+	 { "VIDEO_FORMAT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SWAP_CNTL[] = {
+	 { "GRPH_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "GRPH_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "GRPH_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_SLV_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[] = {
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PITCH_L[] = {
+	 { "GRPH_PITCH_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_PITCH_C[] = {
+	 { "GRPH_PITCH_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_X_L[] = {
+	 { "GRPH_SURFACE_OFFSET_X_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_X_C[] = {
+	 { "GRPH_SURFACE_OFFSET_X_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_Y_L[] = {
+	 { "GRPH_SURFACE_OFFSET_Y_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_OFFSET_Y_C[] = {
+	 { "GRPH_SURFACE_OFFSET_Y_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_START_L[] = {
+	 { "GRPH_X_START_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_START_C[] = {
+	 { "GRPH_X_START_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_START_L[] = {
+	 { "GRPH_Y_START_L", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_START_C[] = {
+	 { "GRPH_Y_START_C", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_SLS_PITCH[] = {
+	 { "XDMA_SLV_SLS_PITCH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_SLS_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_END_L[] = {
+	 { "GRPH_X_END_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_X_END_C[] = {
+	 { "GRPH_X_END_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_END_L[] = {
+	 { "GRPH_Y_END_L", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_Y_END_C[] = {
+	 { "GRPH_Y_END_C", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_UPDATE[] = {
+	 { "GRPH_MODE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "GRPH_MODE_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_TAKEN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SURFACE_IGNORE_UPDATE_LOCK", 20, 20, &umr_bitfield_default },
+	 { "GRPH_MODE_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE_L", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE_C", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE_L", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE_C", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DVMM_PTE_CONTROL[] = {
+	 { "DVMM_USE_SINGLE_PTE", 0, 0, &umr_bitfield_default },
+	 { "DVMM_PAGE_WIDTH", 1, 4, &umr_bitfield_default },
+	 { "DVMM_PAGE_HEIGHT", 5, 8, &umr_bitfield_default },
+	 { "DVMM_MIN_PTE_BEFORE_FLIP", 9, 18, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE0", 20, 20, &umr_bitfield_default },
+	 { "DVMM_PTE_BUFFER_MODE1", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_INTERRUPT_STATUS[] = {
+	 { "GRPH_PFLIP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_INTERRUPT_CONTROL[] = {
+	 { "GRPH_PFLIP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_GRPH_STEREOSYNC_FLIP[] = {
+	 { "GRPH_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_FLIP_MODE", 4, 5, &umr_bitfield_default },
+	 { "GRPH_STACK_INTERLACE_FLIP_EN", 8, 8, &umr_bitfield_default },
+	 { "GRPH_STACK_INTERLACE_FLIP_MODE", 12, 13, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_BOTTOM_SURFACE_PENDING", 18, 18, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_BOTTOM_SURFACE_PENDING", 19, 19, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_FLIP_CONTROL[] = {
+	 { "GRPH_SURFACE_UPDATE_PENDING_MODE", 0, 0, &umr_bitfield_default },
+	 { "UNP_DEBUG_SG", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_URGENT_CNTL[] = {
+	 { "XDMA_SLV_READ_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_CONTROL[] = {
+	 { "UNP_CRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "UNP_CRC_SOURCE_SEL", 2, 4, &umr_bitfield_default },
+	 { "UNP_CRC_LINE_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_MASK[] = {
+	 { "UNP_CRC_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_CURRENT[] = {
+	 { "UNP_CRC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_CRC_LAST[] = {
+	 { "UNP_CRC_LAST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[] = {
+	 { "UNP_LB_GAP_BETWEEN_CHUNK", 4, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_HW_ROTATION[] = {
+	 { "ROTATION_ANGLE", 0, 2, &umr_bitfield_default },
+	 { "PIXEL_DROP", 4, 4, &umr_bitfield_default },
+	 { "BUFFER_MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DEBUG[] = {
+	 { "UNP_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DEBUG2[] = {
+	 { "UNP_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_TEST_DEBUG_INDEX[] = {
+	 { "UNP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "UNP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_TEST_DEBUG_DATA[] = {
+	 { "UNP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT[] = {
+	 { "UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L", 0, 7, &umr_bitfield_default },
+	 { "UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNP_DVMM_DEBUG[] = {
+	 { "UNP_L_DVMM_DEBUG", 0, 15, &umr_bitfield_default },
+	 { "UNP_C_DVMM_DEBUG", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DATA_FORMAT[] = {
+	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "PIXEL_EXPAN_MODE", 2, 2, &umr_bitfield_default },
+	 { "INTERLEAVE_EN", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_REDUCE_MODE", 4, 4, &umr_bitfield_default },
+	 { "DYNAMIC_PIXEL_DEPTH", 5, 5, &umr_bitfield_default },
+	 { "DITHER_EN", 6, 6, &umr_bitfield_default },
+	 { "DOWNSCALE_PREFETCH_EN", 7, 7, &umr_bitfield_default },
+	 { "PREFETCH", 12, 12, &umr_bitfield_default },
+	 { "REQUEST_MODE", 24, 24, &umr_bitfield_default },
+	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_MEMORY_CTRL[] = {
+	 { "LB_MEMORY_SIZE", 0, 11, &umr_bitfield_default },
+	 { "LB_NUM_PARTITIONS", 16, 19, &umr_bitfield_default },
+	 { "LB_MEMORY_CONFIG", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_MEMORY_SIZE_STATUS[] = {
+	 { "LB_MEMORY_SIZE_STATUS", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DESKTOP_HEIGHT[] = {
+	 { "DESKTOP_HEIGHT", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WRITE_URGENT_CNTL[] = {
+	 { "XDMA_SLV_WRITE_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_STALL_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE_START_END[] = {
+	 { "VLINE_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE2_START_END[] = {
+	 { "VLINE2_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE2_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE2_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_V_COUNTER[] = {
+	 { "V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SNAPSHOT_V_COUNTER[] = {
+	 { "SNAPSHOT_V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_V_COUNTER_CHROMA[] = {
+	 { "V_COUNTER_CHROMA", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SNAPSHOT_V_COUNTER_CHROMA[] = {
+	 { "SNAPSHOT_V_COUNTER_CHROMA", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_INTERRUPT_MASK[] = {
+	 { "VBLANK_INTERRUPT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_MASK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE_STATUS[] = {
+	 { "VLINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VLINE2_STATUS[] = {
+	 { "VLINE2_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE2_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_VBLANK_STATUS[] = {
+	 { "VBLANK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VBLANK_ACK", 4, 4, &umr_bitfield_default },
+	 { "VBLANK_STAT", 12, 12, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_SYNC_RESET_SEL[] = {
+	 { "LB_SYNC_RESET_SEL", 0, 1, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_SEL2", 4, 4, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LB_SYNC_DURATION", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_R_CR[] = {
+	 { "LB_BLACK_KEYER_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_G_Y[] = {
+	 { "LB_BLACK_KEYER_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BLACK_KEYER_B_CB[] = {
+	 { "LB_BLACK_KEYER_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_CTRL[] = {
+	 { "LB_KEYER_COLOR_EN", 0, 0, &umr_bitfield_default },
+	 { "LB_KEYER_COLOR_REP_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_R_CR[] = {
+	 { "LB_KEYER_COLOR_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WB_RATE_CNTL[] = {
+	 { "XDMA_SLV_WB_BURST_SIZE", 0, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_WB_BURST_PERIOD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_G_Y[] = {
+	 { "LB_KEYER_COLOR_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_B_CB[] = {
+	 { "LB_KEYER_COLOR_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_R_CR[] = {
+	 { "LB_KEYER_COLOR_REP_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_G_Y[] = {
+	 { "LB_KEYER_COLOR_REP_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_KEYER_COLOR_REP_B_CB[] = {
+	 { "LB_KEYER_COLOR_REP_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_LEVEL_STATUS[] = {
+	 { "REQ_FIFO_LEVEL", 0, 5, &umr_bitfield_default },
+	 { "REQ_FIFO_FULL_CNTL", 10, 15, &umr_bitfield_default },
+	 { "DATA_BUFFER_LEVEL", 16, 27, &umr_bitfield_default },
+	 { "DATA_FIFO_FULL_CNTL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_URGENCY_CTRL[] = {
+	 { "LB_BUFFER_URGENCY_MARK_ON", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_MARK_OFF", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_URGENCY_STATUS[] = {
+	 { "LB_BUFFER_URGENCY_LEVEL", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_STAT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_BUFFER_STATUS[] = {
+	 { "LB_BUFFER_EMPTY_MARGIN", 0, 3, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_STAT", 4, 4, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_ACK", 12, 12, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_STAT", 16, 16, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_ACK", 24, 24, &umr_bitfield_default },
+	 { "LB_ENABLE_HIGH_THROUGHPUT", 25, 25, &umr_bitfield_default },
+	 { "LB_HIGH_THROUGHPUT_CNTL", 26, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_NO_OUTSTANDING_REQ_STATUS[] = {
+	 { "LB_NO_OUTSTANDING_REQ_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG[] = {
+	 { "LB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG2[] = {
+	 { "LB_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_DEBUG3[] = {
+	 { "LB_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_MINMAX[] = {
+	 { "XDMA_SLV_READ_LATENCY_MIN", 0, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_TEST_DEBUG_INDEX[] = {
+	 { "LB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "LB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLBV_TEST_DEBUG_DATA[] = {
+	 { "LB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_AVE[] = {
+	 { "XDMA_SLV_READ_LATENCY_ACC", 0, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_COUNT", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_COEF_RAM_SELECT[] = {
+	 { "SCL_C_RAM_TAP_PAIR_IDX", 0, 1, &umr_bitfield_default },
+	 { "SCL_C_RAM_PHASE", 8, 14, &umr_bitfield_default },
+	 { "SCL_C_RAM_FILTER_TYPE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_COEF_RAM_TAP_DATA[] = {
+	 { "SCL_C_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
+	 { "SCL_C_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE[] = {
+	 { "SCL_MODE", 0, 1, &umr_bitfield_default },
+	 { "SCL_MODE_C", 2, 3, &umr_bitfield_default },
+	 { "SCL_PSCL_EN", 4, 4, &umr_bitfield_default },
+	 { "SCL_PSCL_EN_C", 5, 5, &umr_bitfield_default },
+	 { "SCL_INTERLACE_SOURCE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TAP_CONTROL[] = {
+	 { "SCL_V_NUM_OF_TAPS", 0, 2, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS", 4, 6, &umr_bitfield_default },
+	 { "SCL_V_NUM_OF_TAPS_C", 8, 10, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS_C", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_CONTROL[] = {
+	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_EARLY_EOL_MODE", 4, 4, &umr_bitfield_default },
+	 { "SCL_TOTAL_PHASE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MANUAL_REPLICATE_CONTROL[] = {
+	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
+	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_AUTOMATIC_MODE_CONTROL[] = {
+	 { "SCL_V_CALC_AUTO_RATIO_EN", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_CALC_AUTO_RATIO_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_CONTROL[] = {
+	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_SCALE_RATIO[] = {
+	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT[] = {
+	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_SCALE_RATIO_C[] = {
+	 { "SCL_H_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT_C[] = {
+	 { "SCL_H_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT_C", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_CONTROL[] = {
+	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_SCALE_RATIO[] = {
+	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT[] = {
+	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_BOT[] = {
+	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_PCIE_NACK_STATUS[] = {
+	 { "XDMA_SLV_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_SCALE_RATIO_C[] = {
+	 { "SCL_V_SCALE_RATIO_C", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_C[] = {
+	 { "SCL_V_INIT_FRAC_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_C", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VERT_FILTER_INIT_BOT_C[] = {
+	 { "SCL_V_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT_C", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_ROUND_OFFSET[] = {
+	 { "SCL_ROUND_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
+	 { "SCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_UPDATE[] = {
+	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "SCL_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "SCL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "SCL_COEF_UPDATE_COMPLETE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_ALU_CONTROL[] = {
+	 { "SCL_ALU_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START[] = {
+	 { "VIEWPORT_Y_START", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_SECONDARY[] = {
+	 { "VIEWPORT_Y_START_SECONDARY", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_SIZE[] = {
+	 { "VIEWPORT_HEIGHT", 0, 12, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_C[] = {
+	 { "VIEWPORT_Y_START_C", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_C", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_START_SECONDARY_C[] = {
+	 { "VIEWPORT_Y_START_SECONDARY_C", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START_SECONDARY_C", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_VIEWPORT_SIZE_C[] = {
+	 { "VIEWPORT_HEIGHT_C", 0, 12, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH_C", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[] = {
+	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[] = {
+	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET1[] = {
+	 { "SCL_MODE_CHANGE", 0, 0, &umr_bitfield_default },
+	 { "SCL_MODE_CHANGE_ACK", 4, 4, &umr_bitfield_default },
+	 { "SCL_ALU_H_SCALE_RATIO", 7, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET2[] = {
+	 { "SCL_ALU_V_SCALE_RATIO", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_NACK_STATUS[] = {
+	 { "XDMA_SLV_MEM_NACK_TAG", 0, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK", 16, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK_CLR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_DET3[] = {
+	 { "SCL_ALU_SOURCE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "SCL_ALU_SOURCE_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_MODE_CHANGE_MASK[] = {
+	 { "SCL_MODE_CHANGE_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT_BOT[] = {
+	 { "SCL_H_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT_BOT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_HORZ_FILTER_INIT_BOT_C[] = {
+	 { "SCL_H_INIT_FRAC_BOT_C", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT_BOT_C", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_DEBUG2[] = {
+	 { "SCL_DEBUG_REQ_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_DEBUG_EOF_MODE", 1, 2, &umr_bitfield_default },
+	 { "SCL_DEBUG2", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_DEBUG[] = {
+	 { "SCL_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TEST_DEBUG_INDEX[] = {
+	 { "SCL_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SCL_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLV_TEST_DEBUG_DATA[] = {
+	 { "SCL_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_RDRET_BUF_STATUS[] = {
+	 { "XDMA_SLV_RDRET_FREE_ENTRIES", 0, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_BUF_SIZE", 12, 21, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_PG_STATE", 22, 23, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_PG_TRANS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_UPDATE[] = {
+	 { "COL_MAN_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "COL_MAN_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "COL_MAN_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "COL_MAN_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_INPUT_CSC_CONTROL[] = {
+	 { "INPUT_CSC_MODE", 0, 1, &umr_bitfield_default },
+	 { "INPUT_CSC_INPUT_TYPE", 8, 9, &umr_bitfield_default },
+	 { "INPUT_CSC_CONVERSION_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12_A[] = {
+	 { "INPUT_CSC_C11_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14_A[] = {
+	 { "INPUT_CSC_C13_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22_A[] = {
+	 { "INPUT_CSC_C21_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24_A[] = {
+	 { "INPUT_CSC_C23_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32_A[] = {
+	 { "INPUT_CSC_C31_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34_A[] = {
+	 { "INPUT_CSC_C33_A", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12_B[] = {
+	 { "INPUT_CSC_C11_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14_B[] = {
+	 { "INPUT_CSC_C13_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22_B[] = {
+	 { "INPUT_CSC_C21_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24_B[] = {
+	 { "INPUT_CSC_C23_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_TIMER[] = {
+	 { "XDMA_SLV_READ_LATENCY_TIMER", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32_B[] = {
+	 { "INPUT_CSC_C31_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34_B[] = {
+	 { "INPUT_CSC_C33_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_CONTROL[] = {
+	 { "PRESCALE_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_R[] = {
+	 { "PRESCALE_BIAS_R", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_G[] = {
+	 { "PRESCALE_BIAS_G", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_B[] = {
+	 { "PRESCALE_BIAS_B", 0, 15, &umr_bitfield_default },
+	 { "PRESCALE_SCALE_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_OUTPUT_CSC_CONTROL[] = {
+	 { "OUTPUT_CSC_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12_A[] = {
+	 { "OUTPUT_CSC_C11_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14_A[] = {
+	 { "OUTPUT_CSC_C13_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22_A[] = {
+	 { "OUTPUT_CSC_C21_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24_A[] = {
+	 { "OUTPUT_CSC_C23_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32_A[] = {
+	 { "OUTPUT_CSC_C31_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34_A[] = {
+	 { "OUTPUT_CSC_C33_A", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34_A", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12_B[] = {
+	 { "OUTPUT_CSC_C11_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14_B[] = {
+	 { "OUTPUT_CSC_C13_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22_B[] = {
+	 { "OUTPUT_CSC_C21_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_FLIP_PENDING[] = {
+	 { "XDMA_SLV_FLIP_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24_B[] = {
+	 { "OUTPUT_CSC_C23_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32_B[] = {
+	 { "OUTPUT_CSC_C31_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34_B[] = {
+	 { "OUTPUT_CSC_C33_B", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_CONTROL[] = {
+	 { "DENORM_MODE", 0, 1, &umr_bitfield_default },
+	 { "DENORM_10BIT_OUT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_R_CR[] = {
+	 { "RANGE_CLAMP_MAX_R_CR", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_R_CR", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_G_Y[] = {
+	 { "RANGE_CLAMP_MAX_G_Y", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_G_Y", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CLAMP_RANGE_B_CB[] = {
+	 { "RANGE_CLAMP_MAX_B_CB", 0, 11, &umr_bitfield_default },
+	 { "RANGE_CLAMP_MIN_B_CB", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_FP_CONVERTED_FIELD[] = {
+	 { "COL_MAN_FP_CONVERTED_FIELD_DATA", 0, 17, &umr_bitfield_default },
+	 { "COL_MAN_FP_CONVERTED_FIELD_INDEX", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CONTROL[] = {
+	 { "GAMMA_CORR_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_INDEX[] = {
+	 { "GAMMA_CORR_LUT_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_DATA[] = {
+	 { "GAMMA_CORR_LUT_DATA", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_LUT_WRITE_EN_MASK[] = {
+	 { "GAMMA_CORR_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_START_CNTL[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_SLOPE_CNTL[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_END_CNTL1[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_END_CNTL2[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_0_1[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION0_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION0_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION1_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION1_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_2_3[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION2_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION2_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION3_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION3_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_4_5[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION4_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION4_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION5_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION5_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_6_7[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION6_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION6_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION7_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION7_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_8_9[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION8_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION8_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION9_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION9_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_10_11[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION10_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION10_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION11_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION11_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_12_13[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION12_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION12_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION13_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION13_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLA_REGION_14_15[] = {
+	 { "GAMMA_CORR_CNTLA_EXP_REGION14_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION14_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION15_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLA_EXP_REGION15_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_START_CNTL[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_SLOPE_CNTL[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_END_CNTL1[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_END_CNTL2[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_0_1[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION0_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION0_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION1_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION1_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_2_3[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION2_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION2_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION3_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION3_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_4_5[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION4_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION4_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION5_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION5_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_6_7[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION6_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION6_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION7_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION7_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_8_9[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION8_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION8_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION9_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION9_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_10_11[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION10_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION10_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION11_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION11_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_12_13[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION12_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION12_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION13_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION13_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMMA_CORR_CNTLB_REGION_14_15[] = {
+	 { "GAMMA_CORR_CNTLB_EXP_REGION14_LUT_OFFSET", 0, 7, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION14_NUM_SEGMENTS", 11, 13, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION15_LUT_OFFSET", 15, 22, &umr_bitfield_default },
+	 { "GAMMA_CORR_CNTLB_EXP_REGION15_NUM_SEGMENTS", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPACK_FIFO_ERROR[] = {
+	 { "PACK_FIFO_L_UNDERFLOW_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "PACK_FIFO_L_UNDERFLOW_ACK", 1, 1, &umr_bitfield_default },
+	 { "PACK_FIFO_C_UNDERFLOW_OCCURED", 8, 8, &umr_bitfield_default },
+	 { "PACK_FIFO_C_UNDERFLOW_ACK", 9, 9, &umr_bitfield_default },
+	 { "PACK_FIFO_L_OVERFLOW_OCCURED", 16, 16, &umr_bitfield_default },
+	 { "PACK_FIFO_L_OVERFLOW_ACK", 17, 17, &umr_bitfield_default },
+	 { "PACK_FIFO_C_OVERFLOW_OCCURED", 24, 24, &umr_bitfield_default },
+	 { "PACK_FIFO_C_OVERFLOW_ACK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_FIFO_ERROR[] = {
+	 { "OUTPUT_FIFO_UNDERFLOW_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "OUTPUT_FIFO_UNDERFLOW_ACK", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_FIFO_OVERFLOW_OCCURED", 8, 8, &umr_bitfield_default },
+	 { "OUTPUT_FIFO_OVERFLOW_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_AUTOFILL[] = {
+	 { "INPUT_GAMMA_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_AUTOFILL_DONE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_RW_INDEX[] = {
+	 { "INPUT_GAMMA_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_SEQ_COLOR[] = {
+	 { "INPUT_GAMMA_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_PWL_DATA[] = {
+	 { "INPUT_GAMMA_LUT_BASE", 0, 15, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_DELTA", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_LUT_30_COLOR[] = {
+	 { "INPUT_GAMMA_LUT_COLOR_10_BLUE", 0, 9, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_COLOR_10_GREEN", 10, 19, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_COLOR_10_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_INPUT_GAMMA_CONTROL1[] = {
+	 { "INPUT_GAMMA_MODE", 0, 1, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_10BIT_BYPASS_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_INPUT_GAMMA_CONTROL2[] = {
+	 { "INPUT_GAMMA_INC_B", 1, 4, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_B_SIGNED_EN", 5, 5, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_B_FORMAT", 6, 7, &umr_bitfield_default },
+	 { "INPUT_GAMMA_INC_G", 8, 11, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_G_SIGNED_EN", 12, 12, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_G_FORMAT", 13, 14, &umr_bitfield_default },
+	 { "INPUT_GAMMA_INC_R", 15, 18, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_R_SIGNED_EN", 19, 19, &umr_bitfield_default },
+	 { "INPUT_GAMMA_DATA_R_FORMAT", 20, 21, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_RW_MODE", 22, 22, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_WRITE_EN_MASK", 23, 25, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_VGA_ACCESS_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "INPUT_GAMMA_LUT_10BIT_BYPASS_DBL_BUF_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_BW_OFFSETS_B[] = {
+	 { "INPUT_GAMMA_BLACK_OFFSET_B", 0, 15, &umr_bitfield_default },
+	 { "INPUT_GAMMA_WHITE_OFFSET_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_BW_OFFSETS_G[] = {
+	 { "INPUT_GAMMA_BLACK_OFFSET_G", 0, 15, &umr_bitfield_default },
+	 { "INPUT_GAMMA_WHITE_OFFSET_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_BW_OFFSETS_R[] = {
+	 { "INPUT_GAMMA_BLACK_OFFSET_R", 0, 15, &umr_bitfield_default },
+	 { "INPUT_GAMMA_WHITE_OFFSET_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_DEBUG_CONTROL[] = {
+	 { "COL_MAN_GLOBAL_PASSTHROUGH_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_TEST_DEBUG_INDEX[] = {
+	 { "COL_MAN_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "COL_MAN_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOL_MAN_TEST_DEBUG_DATA[] = {
+	 { "COL_MAN_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_CLOCK_CONTROL[] = {
+	 { "DISPCLK_R_DCFEV_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "DISPCLK_G_UNP_GATE_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_SCLV_GATE_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_COL_MAN_GATE_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "DISPCLK_G_PSCLV_GATE_DISABLE", 13, 13, &umr_bitfield_default },
+	 { "DISPCLK_G_CRTC_GATE_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DCFEV_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DCFEV_CLOCK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_SOFT_RESET[] = {
+	 { "UNP_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "UNP_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCLV_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCLV_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "PSCLV_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "COL_MAN_SOFT_RESET", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_CLOCK_CONTROL[] = {
+	 { "DMIFV_SCLK_G_DMIFTRK_GATE_DIS", 3, 3, &umr_bitfield_default },
+	 { "DMIFV_DISPCLK_G_DMIFVL_GATE_DIS", 4, 4, &umr_bitfield_default },
+	 { "DMIFV_DISPCLK_G_DMIFVC_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIFV_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DMIFV_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "DMIFV_BUFFER_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DBG_CONFIG[] = {
+	 { "DCFEV_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFEV_DBG_SEL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_MEM_PWR_CTRL[] = {
+	 { "DMIFV_MEM_PWR_SEL", 0, 1, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_0_FORCE", 2, 2, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_1_FORCE", 3, 3, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_2_FORCE", 4, 4, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_3_FORCE", 5, 5, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_4_FORCE", 6, 6, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_0_FORCE", 7, 7, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_1_FORCE", 8, 8, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_2_FORCE", 9, 9, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_3_FORCE", 10, 10, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_4_FORCE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_MEM_PWR_STATUS[] = {
+	 { "DMIFV_MEM_PWR_LUMA_0_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_1_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_2_STATE", 4, 5, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_3_STATE", 6, 7, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_LUMA_4_STATE", 8, 9, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_0_STATE", 10, 11, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_1_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_2_STATE", 14, 15, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_3_STATE", 16, 17, &umr_bitfield_default },
+	 { "DMIFV_MEM_PWR_CHROMA_4_STATE", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_MEM_PWR_CTRL[] = {
+	 { "COL_MAN_GAMMA_CORR_MEM_PWR_FORCE", 0, 1, &umr_bitfield_default },
+	 { "COL_MAN_GAMMA_CORR_MEM_PWR_DIS", 2, 2, &umr_bitfield_default },
+	 { "COL_MAN_INPUT_GAMMA_MEM_PWR_FORCE", 3, 4, &umr_bitfield_default },
+	 { "COL_MAN_INPUT_GAMMA_MEM_PWR_DIS", 5, 5, &umr_bitfield_default },
+	 { "SCLV_COEFF_MEM_PWR_FORCE", 6, 7, &umr_bitfield_default },
+	 { "SCLV_COEFF_MEM_PWR_DIS", 8, 8, &umr_bitfield_default },
+	 { "LBV0_MEM_PWR_FORCE", 9, 10, &umr_bitfield_default },
+	 { "LBV0_MEM_PWR_DIS", 11, 11, &umr_bitfield_default },
+	 { "LBV1_MEM_PWR_FORCE", 12, 13, &umr_bitfield_default },
+	 { "LBV1_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "LBV2_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "LBV2_MEM_PWR_DIS", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_MEM_PWR_CTRL2[] = {
+	 { "COL_MAN_GAMMA_CORR_MEM_PWR_MODE_SEL", 0, 1, &umr_bitfield_default },
+	 { "COL_MAN_INPUT_GAMMA_MEM_PWR_MODE_SEL", 2, 3, &umr_bitfield_default },
+	 { "SCLV_COEFF_MEM_PWR_MODE_SEL", 4, 5, &umr_bitfield_default },
+	 { "LBV_MEM_PWR_MODE_SEL", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_MEM_PWR_STATUS[] = {
+	 { "COL_MAN_GAMMA_CORR_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "COL_MAN_INPUT_GAMMA_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "SCLV_COEFF_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "LBV0_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "LBV1_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "LBV2_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "LBV3_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_DMIFV_DEBUG[] = {
+	 { "DMIFV_DEBUG_BUS_SEL", 0, 3, &umr_bitfield_default },
+	 { "DMIFV_DEBUG_LUMA_VS_CHROMA", 4, 4, &umr_bitfield_default },
+	 { "DMIFV_DEBUG_LOWER_UPPER", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_MISC[] = {
+	 { "DCFEV_DPG_ALLOW_SR_ECO_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_L_FLUSH[] = {
+	 { "FLUSH_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "CLEAR_FLUSH_OCCURED", 1, 1, &umr_bitfield_default },
+	 { "FLUSH_DEEP", 2, 2, &umr_bitfield_default },
+	 { "CLEAR_FLUSH_DEEP", 3, 3, &umr_bitfield_default },
+	 { "ALL_MC_REQ_RET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CHANNEL_CNTL[] = {
+	 { "XDMA_SLV_CHANNEL_WEIGHT", 0, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_STOP_TRANSFER", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_CHANNEL_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_CHANNEL_ACTIVE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFEV_C_FLUSH[] = {
+	 { "FLUSH_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "CLEAR_FLUSH_OCCURED", 1, 1, &umr_bitfield_default },
+	 { "FLUSH_DEEP", 2, 2, &umr_bitfield_default },
+	 { "CLEAR_FLUSH_DEEP", 3, 3, &umr_bitfield_default },
+	 { "ALL_MC_REQ_RET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_ARBITRATION_CONTROL1[] = {
+	 { "PIXEL_DURATION", 0, 15, &umr_bitfield_default },
+	 { "BASE_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_ARBITRATION_CONTROL2[] = {
+	 { "TIME_WEIGHT", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_WATERMARK_MASK_CONTROL[] = {
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK", 0, 1, &umr_bitfield_default },
+	 { "URGENCY_WATERMARK_MASK", 8, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 16, 17, &umr_bitfield_default },
+	 { "DISABLE_FLIP_URGENT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_URGENCY_CONTROL[] = {
+	 { "URGENCY_LOW_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_HIGH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_DPM_CONTROL[] = {
+	 { "DPM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCLK_CHANGE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCLK_CHANGE_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK_MASK", 12, 13, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_STUTTER_CONTROL[] = {
+	 { "STUTTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON", 11, 11, &umr_bitfield_default },
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL[] = {
+	 { "NB_PSTATE_CHANGE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_FORCE_ON", 9, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_ALLOW_FOR_URGENT", 10, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH[] = {
+	 { "STUTTER_ENABLE_NONLPTCH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR_NONLPTCH", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON_NONLPTCH", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA_NONLPTCH", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC_NONLPTCH", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON_NONLPTCH", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_REPEATER_PROGRAM[] = {
+	 { "REG_DPG_DMIFRC_REPEATER", 0, 2, &umr_bitfield_default },
+	 { "REG_DMIFRC_DPG_REPEATER", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_HW_DEBUG_A[] = {
+	 { "DPG_HW_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_HW_DEBUG_B[] = {
+	 { "DPG_HW_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_HW_DEBUG_11[] = {
+	 { "DPG_HW_DEBUG_11", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV0_CHK_PRE_PROC_CNTL[] = {
+	 { "DPG_DISABLE_DMIF_BUF_CHK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_ARBITRATION_CONTROL1[] = {
+	 { "PIXEL_DURATION", 0, 15, &umr_bitfield_default },
+	 { "BASE_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_ARBITRATION_CONTROL2[] = {
+	 { "TIME_WEIGHT", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_WATERMARK_MASK_CONTROL[] = {
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK", 0, 1, &umr_bitfield_default },
+	 { "URGENCY_WATERMARK_MASK", 8, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 16, 17, &umr_bitfield_default },
+	 { "DISABLE_FLIP_URGENT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_URGENCY_CONTROL[] = {
+	 { "URGENCY_LOW_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_HIGH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_DPM_CONTROL[] = {
+	 { "DPM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCLK_CHANGE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCLK_CHANGE_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK_MASK", 12, 13, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_STUTTER_CONTROL[] = {
+	 { "STUTTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON", 11, 11, &umr_bitfield_default },
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL[] = {
+	 { "NB_PSTATE_CHANGE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_FORCE_ON", 9, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_ALLOW_FOR_URGENT", 10, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH[] = {
+	 { "STUTTER_ENABLE_NONLPTCH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR_NONLPTCH", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON_NONLPTCH", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA_NONLPTCH", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC_NONLPTCH", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON_NONLPTCH", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_REPEATER_PROGRAM[] = {
+	 { "REG_DPG_DMIFRC_REPEATER", 0, 2, &umr_bitfield_default },
+	 { "REG_DMIFRC_DPG_REPEATER", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_HW_DEBUG_A[] = {
+	 { "DPG_HW_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_HW_DEBUG_B[] = {
+	 { "DPG_HW_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_HW_DEBUG_11[] = {
+	 { "DPG_HW_DEBUG_11", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV1_CHK_PRE_PROC_CNTL[] = {
+	 { "DPG_DISABLE_DMIF_BUF_CHK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV_TEST_DEBUG_INDEX[] = {
+	 { "DPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPGV_TEST_DEBUG_DATA[] = {
+	 { "DPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_CONTROL[] = {
+	 { "BLND_GLOBAL_GAIN", 0, 7, &umr_bitfield_default },
+	 { "BLND_MODE", 8, 9, &umr_bitfield_default },
+	 { "BLND_STEREO_TYPE", 10, 11, &umr_bitfield_default },
+	 { "BLND_STEREO_POLARITY", 12, 12, &umr_bitfield_default },
+	 { "BLND_FEEDTHROUGH_EN", 13, 13, &umr_bitfield_default },
+	 { "BLND_ALPHA_MODE", 16, 17, &umr_bitfield_default },
+	 { "BLND_ACTIVE_OVERLAP_ONLY", 18, 18, &umr_bitfield_default },
+	 { "BLND_MULTIPLIED_MODE", 20, 20, &umr_bitfield_default },
+	 { "BLND_GLOBAL_ALPHA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_SM_CONTROL2[] = {
+	 { "SM_MODE", 0, 2, &umr_bitfield_default },
+	 { "SM_FRAME_ALTERNATE", 4, 4, &umr_bitfield_default },
+	 { "SM_FIELD_ALTERNATE", 5, 5, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
+	 { "SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_CONTROL2[] = {
+	 { "PTI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PTI_NEW_PIXEL_GAP", 4, 5, &umr_bitfield_default },
+	 { "BLND_NEW_PIXEL_MODE", 6, 6, &umr_bitfield_default },
+	 { "BLND_SUPERAA_DEGAMMA_EN", 7, 7, &umr_bitfield_default },
+	 { "BLND_SUPERAA_REGAMMA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_UPDATE[] = {
+	 { "BLND_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "BLND_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "BLND_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_UNDERFLOW_INTERRUPT[] = {
+	 { "BLND_UNDERFLOW_INT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_PIPE_INDEX", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_V_UPDATE_LOCK[] = {
+	 { "BLND_DCP_GRPH_V_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BLND_DCP_GRPH_SURF_V_UPDATE_LOCK", 1, 1, &umr_bitfield_default },
+	 { "BLND_DCP_CUR_V_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "BLND_DCP_CUR2_V_UPDATE_LOCK", 24, 24, &umr_bitfield_default },
+	 { "BLND_SCL_V_UPDATE_LOCK", 28, 28, &umr_bitfield_default },
+	 { "BLND_BLND_V_UPDATE_LOCK", 29, 29, &umr_bitfield_default },
+	 { "BLND_V_UPDATE_LOCK_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_DEBUG[] = {
+	 { "BLND_CNV_MUX_SELECT", 0, 0, &umr_bitfield_default },
+	 { "BLND_DEBUG", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_TEST_DEBUG_INDEX[] = {
+	 { "BLND_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "BLND_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_TEST_DEBUG_DATA[] = {
+	 { "BLND_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLNDV_REG_UPDATE_STATUS[] = {
+	 { "DCP_BLNDC_GRPH_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
+	 { "DCP_BLNDC_GRPH_SURF_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "DCP_BLNDO_GRPH_SURF_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
+	 { "DCP_BLNDC_CUR_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
+	 { "DCP_BLNDO_CUR_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
+	 { "SCL_BLNDC_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "SCL_BLNDO_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
+	 { "BLND_BLNDC_UPDATE_PENDING", 10, 10, &umr_bitfield_default },
+	 { "BLND_BLNDO_UPDATE_PENDING", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_TOTAL[] = {
+	 { "CRTC_H_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_BLANK_START_END[] = {
+	 { "CRTC_H_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_H_SYNC_A[] = {
+	 { "CRTC_H_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_TOTAL[] = {
+	 { "CRTC_V_TOTAL", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_BLANK_START_END[] = {
+	 { "CRTC_V_BLANK_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_V_SYNC_A[] = {
+	 { "CRTC_V_SYNC_A_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CONTROL[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SYNC_RESET_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
+	 { "CRTC_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
+	 { "CRTC_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_HBLANK_EARLY_CONTROL", 20, 22, &umr_bitfield_default },
+	 { "CRTC_DISP_READ_REQUEST_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SOF_PULL_EN", 29, 29, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_LOCK_SNAPSHOT", 30, 30, &umr_bitfield_default },
+	 { "CRTC_AVSYNC_VSYNC_N_HSYNC_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_START_LINE_CONTROL[] = {
+	 { "CRTC_PROGRESSIVE_START_LINE_EARLY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_START_LINE_EARLY", 1, 1, &umr_bitfield_default },
+	 { "CRTC_PREFETCH_EN", 2, 2, &umr_bitfield_default },
+	 { "CRTC_LEGACY_REQUESTOR_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_ADVANCED_START_LINE_POSITION", 12, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TEST_DEBUG_INDEX[] = {
+	 { "CRTC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_TEST_DEBUG_DATA[] = {
+	 { "CRTC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_OVERSCAN_COLOR[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE", 0, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN", 10, 19, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_OVERSCAN_COLOR_EXT[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_BLACK_COLOR[] = {
+	 { "CRTC_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_BLACK_COLOR_EXT[] = {
+	 { "CRTC_BLACK_COLOR_B_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC_CNTL[] = {
+	 { "CRTC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "CRTC_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_CRC0_SELECT", 20, 22, &umr_bitfield_default },
+	 { "CRTC_CRC1_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_DATA_RG[] = {
+	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC0_DATA_B[] = {
+	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_X_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_X_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_Y_START", 0, 13, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_Y_END", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_DATA_RG[] = {
+	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTCV_CRC1_DATA_B[] = {
+	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICA[] = {
+	 { "GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICA_SEL", 7, 11, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_REFDIV_CLK_SEL", 12, 15, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_SEL", 16, 19, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 23, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICB[] = {
+	 { "GENERICB_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICB_SEL", 8, 11, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_REFDIV_CLK_SEL", 12, 15, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_SEL", 16, 19, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 23, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PAD_EXTERN_SIG[] = {
+	 { "DC_PAD_EXTERN_SIG_SEL", 0, 3, &umr_bitfield_default },
+	 { "MVP_PIXEL_SRC_STATUS", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_REF_CLK_CNTL[] = {
+	 { "HSYNCA_OUTPUT_SEL", 0, 1, &umr_bitfield_default },
+	 { "GENLK_CLK_OUTPUT_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DEBUG[] = {
+	 { "DC_GPIO_VIP_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_MACRO_DEBUG", 8, 9, &umr_bitfield_default },
+	 { "DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DEBUG_BUS_FLOP_EN", 17, 17, &umr_bitfield_default },
+	 { "DPRX_LOOPBACK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYA_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYA_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYB_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYB_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYC_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYC_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYD_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYD_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYE_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYE_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYF_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYF_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYG_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYG_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_WRCMD_DELAY[] = {
+	 { "UNIPHY_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DAC_DELAY", 4, 7, &umr_bitfield_default },
+	 { "DPHY_DELAY", 8, 11, &umr_bitfield_default },
+	 { "DCRXPHY_DELAY", 12, 15, &umr_bitfield_default },
+	 { "ZCAL_DELAY", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PINSTRAPS[] = {
+	 { "DC_PINSTRAPS_BIF_CEC_DIS", 10, 10, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_SMS_EN_HARD", 13, 13, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_AUDIO", 14, 15, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_CCBYPASS", 16, 16, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_CONNECTIVITY", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DVODATA_CONFIG[] = {
+	 { "VIP_MUX_EN", 19, 19, &umr_bitfield_default },
+	 { "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default },
+	 { "DVO_ALTER_MAPPING_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_CNTL[] = {
+	 { "LVTMA_PWRSEQ_EN", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_TARGET_STATE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN", 8, 8, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_OVRD", 9, 9, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_POL", 10, 10, &umr_bitfield_default },
+	 { "LVTMA_DIGON", 16, 16, &umr_bitfield_default },
+	 { "LVTMA_DIGON_OVRD", 17, 17, &umr_bitfield_default },
+	 { "LVTMA_DIGON_POL", 18, 18, &umr_bitfield_default },
+	 { "LVTMA_BLON", 24, 24, &umr_bitfield_default },
+	 { "LVTMA_BLON_OVRD", 25, 25, &umr_bitfield_default },
+	 { "LVTMA_BLON_POL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_STATE[] = {
+	 { "LVTMA_PWRSEQ_TARGET_STATE_R", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DIGON", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_SYNCEN", 2, 2, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_BLON", 3, 3, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DONE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_STATE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_REF_DIV[] = {
+	 { "LVTMA_PWRSEQ_REF_DIV", 0, 11, &umr_bitfield_default },
+	 { "BL_PWM_REF_DIV", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY1[] = {
+	 { "LVTMA_PWRUP_DELAY1", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY2", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY1", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY2[] = {
+	 { "LVTMA_PWRDN_MIN_LENGTH", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY3", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY3", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_VARY_BL_OVERRIDE_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL[] = {
+	 { "BL_ACTIVE_INT_FRAC_CNT", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_FRACTIONAL_EN", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL2[] = {
+	 { "BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE", 0, 15, &umr_bitfield_default },
+	 { "DBG_BL_PWM_INPUT_REFCLK_SELECT", 28, 29, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_BL_OUT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_PERIOD_CNTL[] = {
+	 { "BL_PWM_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_PERIOD_BITCNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_GRP1_REG_LOCK[] = {
+	 { "BL_PWM_GRP1_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_GENLK_PAD_CNTL[] = {
+	 { "DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_SWAPLOCK_PAD_CNTL[] = {
+	 { "DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL0_CNTL[] = {
+	 { "DCIO_GSL0_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL0_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL0_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL1_CNTL[] = {
+	 { "DCIO_GSL1_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL1_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL1_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL2_CNTL[] = {
+	 { "DCIO_GSL2_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL2_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL2_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_P_FLIP[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_P_FLIP", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_P_FLIP", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_P_FLIP", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_P_FLIP", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_P_FLIP", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_P_FLIP", 20, 22, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_DCFEV0_P_FLIP", 23, 25, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_DCFEV1_P_FLIP", 26, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ[] = {
+	 { "DC_GPU_TIMER_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ_CNTL[] = {
+	 { "DC_GPU_TIMER_READ_SELECT", 0, 5, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM", 11, 13, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM", 14, 16, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM", 17, 19, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM", 20, 22, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_CLOCK_CNTL[] = {
+	 { "DCIO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCIO_GATE_DIS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DEBUG[] = {
+	 { "DCIO_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_DCFE_EXT_VSYNC_CNTL[] = {
+	 { "DCO_DCFE0_EXT_VSYNC_MUX", 0, 2, &umr_bitfield_default },
+	 { "DCO_DCFE1_EXT_VSYNC_MUX", 4, 6, &umr_bitfield_default },
+	 { "DCO_DCFE2_EXT_VSYNC_MUX", 8, 10, &umr_bitfield_default },
+	 { "DCO_DCFE3_EXT_VSYNC_MUX", 12, 14, &umr_bitfield_default },
+	 { "DCO_DCFE4_EXT_VSYNC_MUX", 16, 18, &umr_bitfield_default },
+	 { "DCO_DCFE5_EXT_VSYNC_MUX", 20, 22, &umr_bitfield_default },
+	 { "DCO_SWAPLOCKB_EXT_VSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DCO_GENERICB_EXT_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+	 { "DCO_CRTC_MANUAL_FLOW_CONTROL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_INDEX[] = {
+	 { "DCIO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCIO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_DATA[] = {
+	 { "DCIO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDBG_OUT_CNTL[] = {
+	 { "DBG_OUT_PIN_EN", 0, 0, &umr_bitfield_default },
+	 { "DBG_OUT_PIN_SEL", 4, 4, &umr_bitfield_default },
+	 { "DBG_OUT_12BIT_SEL", 8, 9, &umr_bitfield_default },
+	 { "DBG_OUT_TEST_DATA", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DEBUG_CONFIG[] = {
+	 { "DCIO_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DCIO_DBG_SEL", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SOFT_RESET[] = {
+	 { "UNIPHYA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DSYNCA_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHYB_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "DSYNCB_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "UNIPHYC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DSYNCC_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "UNIPHYD_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DSYNCD_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "UNIPHYE_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DSYNCE_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "UNIPHYF_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "DSYNCF_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "UNIPHYG_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DSYNCG_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DACA_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "DCRXPHY_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "DPHY_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "ZCAL_SOFT_RESET", 26, 26, &umr_bitfield_default },
+	 { "UNIPHYLPA_SOFT_RESET", 28, 28, &umr_bitfield_default },
+	 { "DSYNCLPA_SOFT_RESET", 29, 29, &umr_bitfield_default },
+	 { "UNIPHYLPB_SOFT_RESET", 30, 30, &umr_bitfield_default },
+	 { "DSYNCLPB_SOFT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DPHY_SEL[] = {
+	 { "DPHY_LANE0_SEL", 0, 1, &umr_bitfield_default },
+	 { "DPHY_LANE1_SEL", 2, 3, &umr_bitfield_default },
+	 { "DPHY_LANE2_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_LANE3_SEL", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKA[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKA", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKA", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKA", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKA", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKA", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKA", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKB[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKB", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKB", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKB", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKB", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKB", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PERIOD[] = {
+	 { "UNIPHY_IMPCAL_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXP_IMPCAL[] = {
+	 { "AUXP_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXN_IMPCAL[] = {
+	 { "AUXN_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+	 { "AUX_IMPCAL_INTERVAL", 15, 18, &umr_bitfield_default },
+	 { "AUX_IMPCAL_BIASENTST", 19, 21, &umr_bitfield_default },
+	 { "AUX_IMPCAL_RESBIASEN", 22, 22, &umr_bitfield_default },
+	 { "AUX_IMPCAL_SPARE_CONTROL", 23, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_AB[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKA", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKB", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKC[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKC", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKC", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKC", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKC", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKC", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKC", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKD[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKD", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKD", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKD", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKD", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKD", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKD", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_CD[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_CD[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKC", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKD", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKE[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKE", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKE", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKE", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKE", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKE", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKF[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKF", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKF", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKF", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKF", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKF", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKF", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_EF[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_EF[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKE", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKF", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYLPA_LINK_CNTL[] = {
+	 { "UNIPHYLP_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHYLP_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHYLP_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHYLP_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYLPB_LINK_CNTL[] = {
+	 { "UNIPHYLP_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHYLP_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHYLP_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHYLP_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+	 { "UNIPHYLP_LINK_ENABLE_HPD_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYLPA_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHYLP_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHYLP_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYLPB_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHYLP_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHYLP_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "UNIPHYLP_LINK_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DPCS_TX_INTERRUPT[] = {
+	 { "DCIO_DPCS_TXA_INT_TYPE", 0, 0, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXA_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXA_INT_OCCUR", 2, 2, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXB_INT_TYPE", 3, 3, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXB_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXB_INT_OCCUR", 5, 5, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXC_INT_TYPE", 6, 6, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXC_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXC_INT_OCCUR", 8, 8, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXD_INT_TYPE", 9, 9, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXD_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXD_INT_OCCUR", 11, 11, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXE_INT_TYPE", 12, 12, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXE_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXE_INT_OCCUR", 14, 14, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXF_INT_TYPE", 15, 15, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXF_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXF_INT_OCCUR", 17, 17, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXG_INT_TYPE", 18, 18, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXG_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXG_INT_OCCUR", 20, 20, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXLPA_INT_TYPE", 24, 24, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXLPA_INT_MASK", 25, 25, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXLPA_INT_OCCUR", 26, 26, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXLPB_INT_TYPE", 27, 27, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXLPB_INT_MASK", 28, 28, &umr_bitfield_default },
+	 { "DCIO_DPCS_TXLPB_INT_OCCUR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DPCS_RX_INTERRUPT[] = {
+	 { "DCIO_DPCS_RXA_INT_TYPE", 0, 0, &umr_bitfield_default },
+	 { "DCIO_DPCS_RXA_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCIO_DPCS_RXA_INT_OCCUR", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SEMAPHORE0[] = {
+	 { "DCIO_SEMAPHORE0_REQ", 0, 15, &umr_bitfield_default },
+	 { "DCIO_SEMAPHORE0_GNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SEMAPHORE1[] = {
+	 { "DCIO_SEMAPHORE1_REQ", 0, 15, &umr_bitfield_default },
+	 { "DCIO_SEMAPHORE1_GNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SEMAPHORE2[] = {
+	 { "DCIO_SEMAPHORE2_REQ", 0, 15, &umr_bitfield_default },
+	 { "DCIO_SEMAPHORE2_GNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SEMAPHORE3[] = {
+	 { "DCIO_SEMAPHORE3_REQ", 0, 15, &umr_bitfield_default },
+	 { "DCIO_SEMAPHORE3_GNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SEMAPHORE4[] = {
+	 { "DCIO_SEMAPHORE4_REQ", 0, 15, &umr_bitfield_default },
+	 { "DCIO_SEMAPHORE4_GNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SEMAPHORE5[] = {
+	 { "DCIO_SEMAPHORE5_REQ", 0, 15, &umr_bitfield_default },
+	 { "DCIO_SEMAPHORE5_GNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SEMAPHORE6[] = {
+	 { "DCIO_SEMAPHORE6_REQ", 0, 15, &umr_bitfield_default },
+	 { "DCIO_SEMAPHORE6_GNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_SEMAPHORE7[] = {
+	 { "DCIO_SEMAPHORE7_REQ", 0, 15, &umr_bitfield_default },
+	 { "DCIO_SEMAPHORE7_GNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_MASK[] = {
+	 { "DC_GPIO_GENERICA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_RECV1", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_PD_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_RECV1", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_MASK", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_PD_DIS", 13, 13, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_RECV1", 15, 15, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_RECV1", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_RECV1", 23, 23, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_RECV1", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_A[] = {
+	 { "DC_GPIO_GENERICA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_A", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_A", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_A", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_A", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_EN[] = {
+	 { "DC_GPIO_GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_Y[] = {
+	 { "DC_GPIO_GENERICA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_Y", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_Y", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_Y", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_Y", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_MASK[] = {
+	 { "DC_GPIO_DDC1CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_RECV1", 15, 15, &umr_bitfield_default },
+	 { "AUX_PAD1_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX1_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC1_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_A[] = {
+	 { "DC_GPIO_DDC1CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_EN[] = {
+	 { "DC_GPIO_DDC1CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_Y[] = {
+	 { "DC_GPIO_DDC1CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_MASK[] = {
+	 { "DC_GPIO_DDC2CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_RECV1", 15, 15, &umr_bitfield_default },
+	 { "AUX_PAD2_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX2_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC2_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_A[] = {
+	 { "DC_GPIO_DDC2CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_EN[] = {
+	 { "DC_GPIO_DDC2CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_Y[] = {
+	 { "DC_GPIO_DDC2CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_MASK[] = {
+	 { "DC_GPIO_DDC3CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_RECV1", 15, 15, &umr_bitfield_default },
+	 { "AUX_PAD3_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX3_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC3_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_A[] = {
+	 { "DC_GPIO_DDC3CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_EN[] = {
+	 { "DC_GPIO_DDC3CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_Y[] = {
+	 { "DC_GPIO_DDC3CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_MASK[] = {
+	 { "DC_GPIO_DDC4CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_RECV1", 15, 15, &umr_bitfield_default },
+	 { "AUX_PAD4_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX4_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC4_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_A[] = {
+	 { "DC_GPIO_DDC4CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_EN[] = {
+	 { "DC_GPIO_DDC4CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_Y[] = {
+	 { "DC_GPIO_DDC4CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_MASK[] = {
+	 { "DC_GPIO_DDC5CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_RECV1", 15, 15, &umr_bitfield_default },
+	 { "AUX_PAD5_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX5_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC5_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_A[] = {
+	 { "DC_GPIO_DDC5CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_EN[] = {
+	 { "DC_GPIO_DDC5CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_Y[] = {
+	 { "DC_GPIO_DDC5CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_MASK[] = {
+	 { "DC_GPIO_DDC6CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_RECV1", 15, 15, &umr_bitfield_default },
+	 { "AUX_PAD6_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX6_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC6_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_A[] = {
+	 { "DC_GPIO_DDC6CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_EN[] = {
+	 { "DC_GPIO_DDC6CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_Y[] = {
+	 { "DC_GPIO_DDC6CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_MASK[] = {
+	 { "DC_GPIO_DDCVGACLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_RECV1", 15, 15, &umr_bitfield_default },
+	 { "AUX_PADVGA_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUXVGA_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDCVGA_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_A[] = {
+	 { "DC_GPIO_DDCVGACLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_EN[] = {
+	 { "DC_GPIO_DDCVGACLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_RXSEL", 16, 17, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_SPARE", 18, 19, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_BIASCRTEN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_CSEL0P9", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_CSEL1P1", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_COMPSEL", 23, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_RSEL0P9", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_RSEL1P1", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_SPIKERCEN", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_SPIKERCSEL", 27, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_FALLSLEWSEL", 28, 29, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_RESBIASEN", 30, 30, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PAD_SLEWN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_Y[] = {
+	 { "DC_GPIO_DDCVGACLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_MASK[] = {
+	 { "DC_GPIO_HSYNCA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_RECV1", 15, 15, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_CRTC_HSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_CRTC_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_A[] = {
+	 { "DC_GPIO_HSYNCA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_EN[] = {
+	 { "DC_GPIO_HSYNCA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_Y[] = {
+	 { "DC_GPIO_HSYNCA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_MASK[] = {
+	 { "DC_GPIO_GENLK_CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PU_EN", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_RECV1", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_RECV1", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PU_EN", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PU_EN", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_RECV1", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_RECV1", 23, 23, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PU_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_A[] = {
+	 { "DC_GPIO_GENLK_CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_A", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_EN[] = {
+	 { "DC_GPIO_GENLK_CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_Y[] = {
+	 { "DC_GPIO_GENLK_CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_Y", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_MASK[] = {
+	 { "DC_GPIO_HPD1_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_MASK", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_PD_DIS", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_RECV", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_RECV1", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_RECV1", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_RECV1", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_RECV1", 23, 23, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_RECV1", 27, 27, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_RECV", 30, 30, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_RECV1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_A[] = {
+	 { "DC_GPIO_HPD1_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_A", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_A", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_EN[] = {
+	 { "DC_GPIO_HPD1_EN", 0, 0, &umr_bitfield_default },
+	 { "HPD1_SCHMEN_PI", 1, 1, &umr_bitfield_default },
+	 { "HPD1_SLEWNCORE", 2, 2, &umr_bitfield_default },
+	 { "RX_HPD_SCHMEN_PI", 3, 3, &umr_bitfield_default },
+	 { "RX_HPD_SLEWNCORE", 4, 4, &umr_bitfield_default },
+	 { "HPD12_SPARE0", 5, 5, &umr_bitfield_default },
+	 { "HPD1_SEL0", 6, 6, &umr_bitfield_default },
+	 { "RX_HPD_SEL0", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_EN", 8, 8, &umr_bitfield_default },
+	 { "HPD2_SCHMEN_PI", 9, 9, &umr_bitfield_default },
+	 { "HPD12_SPARE1", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_EN", 16, 16, &umr_bitfield_default },
+	 { "HPD3_SCHMEN_PI", 17, 17, &umr_bitfield_default },
+	 { "HPD34_SPARE0", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_EN", 20, 20, &umr_bitfield_default },
+	 { "HPD4_SCHMEN_PI", 21, 21, &umr_bitfield_default },
+	 { "HPD34_SPARE1", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_EN", 24, 24, &umr_bitfield_default },
+	 { "HPD5_SCHMEN_PI", 25, 25, &umr_bitfield_default },
+	 { "HPD56_SPARE0", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_EN", 28, 28, &umr_bitfield_default },
+	 { "HPD6_SCHMEN_PI", 29, 29, &umr_bitfield_default },
+	 { "HPD56_SPARE1", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_Y[] = {
+	 { "DC_GPIO_HPD1_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_Y", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_Y", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_Y", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_MASK[] = {
+	 { "DC_GPIO_BLON_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_RECV1", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_RECV1", 15, 15, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_PD_DIS", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_RECV1", 23, 23, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_RECV1", 27, 27, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_RECV", 30, 30, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_RECV1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_A[] = {
+	 { "DC_GPIO_BLON_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_A", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_EN[] = {
+	 { "DC_GPIO_BLON_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VARY_BL_GENERICA_EN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_Y[] = {
+	 { "DC_GPIO_BLON_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_1[] = {
+	 { "GENLK_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GENLK_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "RX_HPD_STRENGTH_SN", 8, 11, &umr_bitfield_default },
+	 { "RX_HPD_STRENGTH_SP", 12, 15, &umr_bitfield_default },
+	 { "TX_HPD_STRENGTH_SN", 16, 19, &umr_bitfield_default },
+	 { "TX_HPD_STRENGTH_SP", 20, 23, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SN", 24, 27, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SP", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_2[] = {
+	 { "STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "EXT_RESET_DRVSTRENGTH", 8, 10, &umr_bitfield_default },
+	 { "REF_27_DRVSTRENGTH", 12, 14, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SN", 16, 19, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SP", 20, 23, &umr_bitfield_default },
+	 { "REF_27_SRC_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHY_AUX_CNTL[] = {
+	 { "AUXSLAVE_PAD_SLEWN", 0, 0, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_WAKE", 1, 1, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_RXSEL", 2, 2, &umr_bitfield_default },
+	 { "AUXSLAVE_PAD_MODE", 3, 3, &umr_bitfield_default },
+	 { "DDCSLAVE_DATA_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DDCSLAVE_DATA_EN", 5, 5, &umr_bitfield_default },
+	 { "DDCSLAVE_CLK_PD_EN", 6, 6, &umr_bitfield_default },
+	 { "DDCSLAVE_CLK_EN", 7, 7, &umr_bitfield_default },
+	 { "AUX_PAD_SLEWN", 12, 12, &umr_bitfield_default },
+	 { "AUXSLAVE_CLK_PD_EN", 13, 13, &umr_bitfield_default },
+	 { "AUX_PAD_WAKE", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD_RXSEL", 16, 17, &umr_bitfield_default },
+	 { "AUX_PAD_RESBIASEN", 18, 18, &umr_bitfield_default },
+	 { "AUX_PAD_COMPSEL", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_A[] = {
+	 { "DC_GPIO_SCL_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_A", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_EN[] = {
+	 { "DC_GPIO_SCL_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_EN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_DATA_PD_EN", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_RXSEL", 16, 17, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_SPARE", 18, 19, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_BIASCRTEN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_CSEL0P9", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_CSEL1P1", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_COMPSEL", 23, 23, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_RSEL0P9", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_RSEL1P1", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_SPIKERCEN", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_SPIKERCSEL", 27, 27, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_FALLSLEWSEL", 28, 29, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_RESBIASEN", 30, 30, &umr_bitfield_default },
+	 { "DC_GPIO_I2C_PAD_SLEWN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_Y[] = {
+	 { "DC_GPIO_SCL_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_Y", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_STRENGTH[] = {
+	 { "I2C_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "I2C_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_VREF_CONTROL[] = {
+	 { "DVO_VREFPON", 0, 0, &umr_bitfield_default },
+	 { "DVO_VREFSEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_VREFCAL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SKEW_ADJUST[] = {
+	 { "DVO_SKEW_ADJUST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_RECEIVER_EN0[] = {
+	 { "VIPPAD_SCL_RECEN", 0, 0, &umr_bitfield_default },
+	 { "VIPPAD_SDA_RECEN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_RX_HPD_RECEN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_RECEN", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_RECEN", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_RECEN", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_RECEN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_RECEN", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_RECEN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_RECEN", 23, 23, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_RECEN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_RECEN", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_RECEN", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_RECEN", 27, 27, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_RECEN", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_RECEN", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_RECEN", 30, 30, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_RECEN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_RECEIVER_EN1[] = {
+	 { "DC_GPIO_DDC2CLK_RECEN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_RECEN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_RECEN", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_RECEN", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_RECEN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_RECEN", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_RECEN", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_RECEN", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_RECEN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_RECEN", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_RECEN", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_RECEN", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_RECEN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_RECEN", 13, 13, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_RECEN", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_RECEN", 15, 15, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_RECEN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_RECEN", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_RECEN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_MASK[] = {
+	 { "DC_GPIO_I2SDATA0_MASK", 0, 3, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK0_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK0_MASK", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK0_MASK", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF0_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_I2SDATA1_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK1_MASK", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK1_MASK", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK1_MASK", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF1_MASK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_A[] = {
+	 { "DC_GPIO_I2SDATA0_A", 0, 3, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK0_A", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK0_A", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK0_A", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF0_A", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_I2SDATA1_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK1_A", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK1_A", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK1_A", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF1_A", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_EN[] = {
+	 { "DC_GPIO_I2SDATA0_EN", 0, 3, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK0_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK0_EN", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK0_EN", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF0_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_I2SDATA1_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK1_EN", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK1_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK1_EN", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF1_EN", 12, 12, &umr_bitfield_default },
+	 { "SPDIF1_APORT", 13, 13, &umr_bitfield_default },
+	 { "SPDIF1_PU", 14, 14, &umr_bitfield_default },
+	 { "SPDIF1_RXSEL", 15, 15, &umr_bitfield_default },
+	 { "SPDIF1_SCHMEN", 16, 16, &umr_bitfield_default },
+	 { "SPDIF1_SMODE_EN", 17, 17, &umr_bitfield_default },
+	 { "SPDIF1_IMODE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_Y[] = {
+	 { "DC_GPIO_I2SDATA0_Y", 0, 3, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK0_Y", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK0_Y", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK0_Y", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF0_Y", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_I2SDATA1_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK1_Y", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK1_Y", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK1_Y", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF1_Y", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_STRENGTH[] = {
+	 { "I2S0_DRVSTRENGTH", 0, 2, &umr_bitfield_default },
+	 { "SPDIF0_DRVSTRENGTH_SN", 8, 10, &umr_bitfield_default },
+	 { "SPDIF0_DRVSTRENGTH_SP", 11, 13, &umr_bitfield_default },
+	 { "I2S1_DRVSTRENGTH", 16, 18, &umr_bitfield_default },
+	 { "SPDIF1_DRVSTRENGTH_SN", 24, 26, &umr_bitfield_default },
+	 { "SPDIF1_DRVSTRENGTH_SP", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_TX12_EN[] = {
+	 { "DC_GPIO_BLON_TX12_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_TX12_EN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_TX12_EN", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_TX12_EN", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_TX12_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_TX12_EN", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_TX12_EN", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_TX12_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_TX12_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_TX12_EN", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_AUX_CTRL_0[] = {
+	 { "DC_GPIO_AUX1_FALLSLEWSEL", 0, 1, &umr_bitfield_default },
+	 { "DC_GPIO_AUX2_FALLSLEWSEL", 2, 3, &umr_bitfield_default },
+	 { "DC_GPIO_AUX3_FALLSLEWSEL", 4, 5, &umr_bitfield_default },
+	 { "DC_GPIO_AUX4_FALLSLEWSEL", 6, 7, &umr_bitfield_default },
+	 { "DC_GPIO_AUX5_FALLSLEWSEL", 8, 9, &umr_bitfield_default },
+	 { "DC_GPIO_AUX6_FALLSLEWSEL", 10, 11, &umr_bitfield_default },
+	 { "DC_GPIO_AUX1_SPIKERCEN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_AUX2_SPIKERCEN", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_AUX3_SPIKERCEN", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_AUX4_SPIKERCEN", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_AUX5_SPIKERCEN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_AUX6_SPIKERCEN", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_AUX1_SPIKERCSEL", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_AUX2_SPIKERCSEL", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_AUX3_SPIKERCSEL", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_AUX4_SPIKERCSEL", 27, 27, &umr_bitfield_default },
+	 { "DC_GPIO_AUX5_SPIKERCSEL", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_AUX6_SPIKERCSEL", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_AUX_CTRL_1[] = {
+	 { "DC_GPIO_AUX1_CSEL_0P9", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_AUX2_CSEL_0P9", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_AUX3_CSEL_0P9", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_AUX4_CSEL_0P9", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_AUX5_CSEL_0P9", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_AUX6_CSEL_0P9", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_AUX1_CSEL_1P1", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_AUX2_CSEL_1P1", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_AUX3_CSEL_1P1", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_AUX4_CSEL_1P1", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_AUX5_CSEL_1P1", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_AUX6_CSEL_1P1", 13, 13, &umr_bitfield_default },
+	 { "DC_GPIO_AUX1_RSEL_0P9", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_AUX2_RSEL_0P9", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_AUX3_RSEL_0P9", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_AUX4_RSEL_0P9", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_AUX5_RSEL_0P9", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_AUX6_RSEL_0P9", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_AUX1_RSEL_1P1", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_AUX2_RSEL_1P1", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_AUX3_RSEL_1P1", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_AUX4_RSEL_1P1", 27, 27, &umr_bitfield_default },
+	 { "DC_GPIO_AUX5_RSEL_1P1", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_AUX6_RSEL_1P1", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_AUX_CTRL_2[] = {
+	 { "DC_GPIO_AUX1_BIASCRTEN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_AUX2_BIASCRTEN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_AUX3_BIASCRTEN", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_AUX4_BIASCRTEN", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_AUX5_BIASCRTEN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_AUX6_BIASCRTEN", 5, 5, &umr_bitfield_default },
+	 { "DC_IO_AUX1_SPARE", 6, 7, &umr_bitfield_default },
+	 { "DC_IO_AUX2_SPARE", 8, 9, &umr_bitfield_default },
+	 { "DC_IO_AUX3_SPARE", 10, 11, &umr_bitfield_default },
+	 { "DC_IO_AUX4_SPARE", 12, 13, &umr_bitfield_default },
+	 { "DC_IO_AUX5_SPARE", 14, 15, &umr_bitfield_default },
+	 { "DC_IO_AUX6_SPARE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_CTRL_0[] = {
+	 { "DC_GPIO_HPD12_FALLSLEWSEL", 0, 1, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_FALLSLEWSEL", 2, 3, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_FALLSLEWSEL", 4, 5, &umr_bitfield_default },
+	 { "DC_GPIO_HPD12_SPIKERCEN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_SPIKERCEN", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_SPIKERCEN", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD12_SPIKERCSEL", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_SPIKERCSEL", 13, 13, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_SPIKERCSEL", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_HPD12_CSEL_0P9", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_CSEL_0P9", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_CSEL_0P9", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_HPD12_CSEL_1P1", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_CSEL_1P1", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_CSEL_1P1", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_HPD12_RSEL_0P9", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_RSEL_0P9", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_RSEL_0P9", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD12_RSEL_1P1", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_RSEL_1P1", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_RSEL_1P1", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_CTRL_1[] = {
+	 { "DC_GPIO_HPD12_BIASCRTEN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_BIASCRTEN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_BIASCRTEN", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_HPD12_SLEWN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HPD34_SLEWN", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_HPD56_SLEWN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED0[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED1[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_MACRO_CNTL[] = {
+	 { "BPHYC_DAC_WHITE_LEVEL", 0, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_WHITE_FINE_CONTROL", 8, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_BANDGAP_ADJUSTMENT", 16, 21, &umr_bitfield_default },
+	 { "BPHYC_DAC_ANALOG_MONITOR", 24, 27, &umr_bitfield_default },
+	 { "BPHYC_DAC_COREMON", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_AUTO_CALIB_CONTROL[] = {
+	 { "BPHYC_DAC_CAL_INITB", 0, 0, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_EN", 1, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_DACADJ_EN", 2, 2, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_WAIT_ADJUST", 4, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_MASK", 20, 22, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_COMPLETE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED2[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED3[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED0[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED1[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED2[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED3[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_MAR_DEEMPH_NOM[] = {
+	 { "tx_margin_nom", 0, 7, &umr_bitfield_default },
+	 { "deemph_gen1_nom", 8, 15, &umr_bitfield_default },
+	 { "deemph35_gen2_nom", 16, 23, &umr_bitfield_default },
+	 { "deemph60_gen2_nom", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED4[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_LANE_PWRMGMT[] = {
+	 { "pgdelay", 0, 3, &umr_bitfield_default },
+	 { "pgmask", 4, 9, &umr_bitfield_default },
+	 { "vprot_en", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED5[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_TXCNTRL[] = {
+	 { "rdptr_rst_val_gen3", 0, 4, &umr_bitfield_default },
+	 { "clkgate_dis", 5, 5, &umr_bitfield_default },
+	 { "slew_rate_ctl_gen1", 6, 8, &umr_bitfield_default },
+	 { "slew_rate_ctl_gen2", 9, 11, &umr_bitfield_default },
+	 { "slew_rate_ctl_gen3", 12, 14, &umr_bitfield_default },
+	 { "dual_dvi_mstr_en", 15, 15, &umr_bitfield_default },
+	 { "dual_dvi_en", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED6[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_TMDP[] = {
+	 { "tmdp_spare", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED7[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_LANE_RESETS[] = {
+	 { "lane_0_reset_l", 0, 0, &umr_bitfield_default },
+	 { "lane_1_reset_l", 1, 1, &umr_bitfield_default },
+	 { "lane_2_reset_l", 2, 2, &umr_bitfield_default },
+	 { "lane_3_reset_l", 3, 3, &umr_bitfield_default },
+	 { "lane_4_reset_l", 4, 4, &umr_bitfield_default },
+	 { "lane_5_reset_l", 5, 5, &umr_bitfield_default },
+	 { "lane_6_reset_l", 6, 6, &umr_bitfield_default },
+	 { "lane_7_reset_l", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED8[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_ZCALCODE_CTRL[] = {
+	 { "zcalcode_override", 0, 0, &umr_bitfield_default },
+	 { "tx_binary_code_override_val", 1, 5, &umr_bitfield_default },
+	 { "tx_driver_fifty_ohms", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED9[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_DISP_RFU1[] = {
+	 { "rfu_value1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED10[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_DISP_RFU2[] = {
+	 { "rfu_value2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED11[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_DISP_RFU3[] = {
+	 { "rfu_value3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED12[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_DISP_RFU4[] = {
+	 { "rfu_value4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED13[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_DISP_RFU5[] = {
+	 { "rfu_value5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED14[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_DISP_RFU6[] = {
+	 { "rfu_value6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED15[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMMON_DISP_RFU7[] = {
+	 { "rfu_value7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED16[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_PHY_CNTL[] = {
+	 { "DPCS_PHY_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED17[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_TX_CLOCK_CNTL[] = {
+	 { "DPCS_SYMCLK_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "DPCS_SYMCLK_EN", 1, 1, &umr_bitfield_default },
+	 { "DPCS_SYMCLK_CLOCK_ON", 2, 2, &umr_bitfield_default },
+	 { "DPCS_SYMCLK_DIV2_CLOCK_ON", 3, 3, &umr_bitfield_default },
+	 { "DPCS_SYMCLK_DIV2_TX0_EN", 4, 4, &umr_bitfield_default },
+	 { "DPCS_SYMCLK_DIV2_TX1_EN", 5, 5, &umr_bitfield_default },
+	 { "DPCS_SYMCLK_DIV2_TX2_EN", 6, 6, &umr_bitfield_default },
+	 { "DPCS_SYMCLK_DIV2_TX3_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED18[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED19[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_TX_CNTL[] = {
+	 { "DPCS_TX_RESYNC", 0, 0, &umr_bitfield_default },
+	 { "DPCS_TX_STAGGERING_EN", 1, 1, &umr_bitfield_default },
+	 { "DPCS_TX_HIGH_IMP_IDLE_OVERRIDE_EN", 2, 2, &umr_bitfield_default },
+	 { "DPCS_TX_HIGH_IMP_IDLE", 4, 7, &umr_bitfield_default },
+	 { "DPCS_TX_STAGGERING_DELAY", 8, 10, &umr_bitfield_default },
+	 { "DPCS_TX_PLL_UPDATE_REQ", 12, 12, &umr_bitfield_default },
+	 { "DPCS_TX_PLL_UPDATE_PENDING", 13, 13, &umr_bitfield_default },
+	 { "DPCS_TX_DATA_SWAP", 14, 14, &umr_bitfield_default },
+	 { "DPCS_TX_FIFO_EN", 16, 16, &umr_bitfield_default },
+	 { "DPCS_TX_FIFO_START", 17, 17, &umr_bitfield_default },
+	 { "DPCS_TX_FIFO_WR_START_DELAY", 20, 23, &umr_bitfield_default },
+	 { "DPCS_TX_DVI_LINK_MODE", 24, 25, &umr_bitfield_default },
+	 { "DPCS_TX_SOFT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED20[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED21[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_CBUS_CNTL[] = {
+	 { "DPCS_CBUS_WR_CMD_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DPCS_PHY_MASTER_REQ_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DPCS_CBUS_SOFT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED22[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_REG_ERROR_STATUS[] = {
+	 { "DPCS_REG_FIFO_OVERFLOW", 0, 0, &umr_bitfield_default },
+	 { "DPCS_REG_ERROR_CLR", 1, 1, &umr_bitfield_default },
+	 { "DPCS_REG_FIFO_ERROR_MASK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED23[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_TX_ERROR_STATUS[] = {
+	 { "DPCS_TX0_FIFO_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DPCS_TX1_FIFO_ERROR", 1, 1, &umr_bitfield_default },
+	 { "DPCS_TX2_FIFO_ERROR", 2, 2, &umr_bitfield_default },
+	 { "DPCS_TX3_FIFO_ERROR", 3, 3, &umr_bitfield_default },
+	 { "DPCS_TX_ERROR_CLR", 8, 8, &umr_bitfield_default },
+	 { "DPCS_TX_FIFO_ERROR_MASK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED24[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_PLL_UPDATE_ADDR[] = {
+	 { "DPCS_PLL_UPDATE_ADDR", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED25[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_PLL_UPDATE_DATA[] = {
+	 { "DPCS_PLL_UPDATE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED26[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_INDEX_MODE_ADDR[] = {
+	 { "DPCS_INDEX_MODE_ADDR", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED27[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_INDEX_MODE_DATA[] = {
+	 { "DPCS_INDEX_MODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED28[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_DEBUG_CONFIG[] = {
+	 { "DPCS_DBG_EN", 0, 0, &umr_bitfield_default },
+	 { "DPCS_DBG_CFGCLK_SEL", 1, 2, &umr_bitfield_default },
+	 { "DPCS_DBG_TX_SYMCLK_SEL", 3, 5, &umr_bitfield_default },
+	 { "DPCS_DBG_CLOCK_SEL", 8, 10, &umr_bitfield_default },
+	 { "DPCS_DBG_BLOCK_SEL", 11, 13, &umr_bitfield_default },
+	 { "DPCS_DBG_CBUS_DIS", 14, 14, &umr_bitfield_default },
+	 { "DPCS_TEST_DEBUG_WRITE_EN", 16, 16, &umr_bitfield_default },
+	 { "DPCS_DBG_TX_SYMCLK_DIV2_SEL", 17, 19, &umr_bitfield_default },
+	 { "DPCS_TEST_DEBUG_INDEX", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED29[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPCSTX_TEST_DEBUG_DATA[] = {
+	 { "DPCS_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED30[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED31[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED32[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCMD_BUS_TX_CONTROL_LANE0[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "tx_rdy", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED33[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMARGIN_DEEMPH_LANE0[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph_sel", 3, 4, &umr_bitfield_default },
+	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED34[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCMD_BUS_GLOBAL_FOR_TX_LANE0[] = {
+	 { "twosym_en", 1, 2, &umr_bitfield_default },
+	 { "link_speed", 3, 4, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+	 { "max_linkrate", 8, 9, &umr_bitfield_default },
+	 { "pcs_freq", 10, 11, &umr_bitfield_default },
+	 { "pcs_clken", 12, 12, &umr_bitfield_default },
+	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
+	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
+	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
+	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
+	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
+	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED35[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU0_LANE0[] = {
+	 { "rfu_value0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED36[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU1_LANE0[] = {
+	 { "rfu_value1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED37[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU2_LANE0[] = {
+	 { "rfu_value2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED38[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU3_LANE0[] = {
+	 { "rfu_value3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED39[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU4_LANE0[] = {
+	 { "rfu_value4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED40[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU5_LANE0[] = {
+	 { "rfu_value5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED41[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU6_LANE0[] = {
+	 { "rfu_value6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED42[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU7_LANE0[] = {
+	 { "rfu_value7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED43[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU8_LANE0[] = {
+	 { "rfu_value8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED44[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU9_LANE0[] = {
+	 { "rfu_value9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED45[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU10_LANE0[] = {
+	 { "rfu_value10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED46[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU11_LANE0[] = {
+	 { "rfu_value11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED47[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU12_LANE0[] = {
+	 { "rfu_value12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED48[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCMD_BUS_TX_CONTROL_LANE1[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "tx_rdy", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED49[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMARGIN_DEEMPH_LANE1[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph_sel", 3, 4, &umr_bitfield_default },
+	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED50[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCMD_BUS_GLOBAL_FOR_TX_LANE1[] = {
+	 { "twosym_en", 1, 2, &umr_bitfield_default },
+	 { "link_speed", 3, 4, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+	 { "max_linkrate", 8, 9, &umr_bitfield_default },
+	 { "pcs_freq", 10, 11, &umr_bitfield_default },
+	 { "pcs_clken", 12, 12, &umr_bitfield_default },
+	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
+	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
+	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
+	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
+	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
+	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED51[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU0_LANE1[] = {
+	 { "rfu_value0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED52[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU1_LANE1[] = {
+	 { "rfu_value1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED53[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU2_LANE1[] = {
+	 { "rfu_value2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED54[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU3_LANE1[] = {
+	 { "rfu_value3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED55[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU4_LANE1[] = {
+	 { "rfu_value4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED56[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU5_LANE1[] = {
+	 { "rfu_value5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED57[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU6_LANE1[] = {
+	 { "rfu_value6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED58[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU7_LANE1[] = {
+	 { "rfu_value7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED59[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU8_LANE1[] = {
+	 { "rfu_value8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED60[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU9_LANE1[] = {
+	 { "rfu_value9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED61[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU10_LANE1[] = {
+	 { "rfu_value10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED62[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU11_LANE1[] = {
+	 { "rfu_value11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED63[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU12_LANE1[] = {
+	 { "rfu_value12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED64[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCMD_BUS_TX_CONTROL_LANE2[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "tx_rdy", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED65[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMARGIN_DEEMPH_LANE2[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph_sel", 3, 4, &umr_bitfield_default },
+	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED66[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCMD_BUS_GLOBAL_FOR_TX_LANE2[] = {
+	 { "twosym_en", 1, 2, &umr_bitfield_default },
+	 { "link_speed", 3, 4, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+	 { "max_linkrate", 8, 9, &umr_bitfield_default },
+	 { "pcs_freq", 10, 11, &umr_bitfield_default },
+	 { "pcs_clken", 12, 12, &umr_bitfield_default },
+	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
+	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
+	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
+	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
+	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
+	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED67[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU0_LANE2[] = {
+	 { "rfu_value0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED68[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU1_LANE2[] = {
+	 { "rfu_value1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED69[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU2_LANE2[] = {
+	 { "rfu_value2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED70[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU3_LANE2[] = {
+	 { "rfu_value3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED71[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU4_LANE2[] = {
+	 { "rfu_value4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED72[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU5_LANE2[] = {
+	 { "rfu_value5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED73[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU6_LANE2[] = {
+	 { "rfu_value6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED74[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU7_LANE2[] = {
+	 { "rfu_value7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED75[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU8_LANE2[] = {
+	 { "rfu_value8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED76[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU9_LANE2[] = {
+	 { "rfu_value9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED77[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU10_LANE2[] = {
+	 { "rfu_value10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED78[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU11_LANE2[] = {
+	 { "rfu_value11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED79[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU12_LANE2[] = {
+	 { "rfu_value12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED80[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCMD_BUS_TX_CONTROL_LANE3[] = {
+	 { "tx_pwr", 0, 2, &umr_bitfield_default },
+	 { "tx_pg_en", 3, 4, &umr_bitfield_default },
+	 { "tx_rdy", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED81[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMARGIN_DEEMPH_LANE3[] = {
+	 { "txmarg_sel", 0, 2, &umr_bitfield_default },
+	 { "deemph_sel", 3, 4, &umr_bitfield_default },
+	 { "tx_margin_en", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED82[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCMD_BUS_GLOBAL_FOR_TX_LANE3[] = {
+	 { "twosym_en", 1, 2, &umr_bitfield_default },
+	 { "link_speed", 3, 4, &umr_bitfield_default },
+	 { "gang_mode", 5, 7, &umr_bitfield_default },
+	 { "max_linkrate", 8, 9, &umr_bitfield_default },
+	 { "pcs_freq", 10, 11, &umr_bitfield_default },
+	 { "pcs_clken", 12, 12, &umr_bitfield_default },
+	 { "pcs_clkdone", 13, 13, &umr_bitfield_default },
+	 { "pll1_always_on", 14, 14, &umr_bitfield_default },
+	 { "rdclk_div2_en", 15, 15, &umr_bitfield_default },
+	 { "tx_boost_adj", 16, 19, &umr_bitfield_default },
+	 { "tx_boost_en", 20, 20, &umr_bitfield_default },
+	 { "tx_binary_ron_code_offset", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED83[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU0_LANE3[] = {
+	 { "rfu_value0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED84[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU1_LANE3[] = {
+	 { "rfu_value1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED85[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU2_LANE3[] = {
+	 { "rfu_value2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED86[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU3_LANE3[] = {
+	 { "rfu_value3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED87[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU4_LANE3[] = {
+	 { "rfu_value4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED88[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU5_LANE3[] = {
+	 { "rfu_value5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED89[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU6_LANE3[] = {
+	 { "rfu_value6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED90[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU7_LANE3[] = {
+	 { "rfu_value7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED91[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU8_LANE3[] = {
+	 { "rfu_value8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED92[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU9_LANE3[] = {
+	 { "rfu_value9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED93[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU10_LANE3[] = {
+	 { "rfu_value10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED94[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU11_LANE3[] = {
+	 { "rfu_value11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED95[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTX_DISP_RFU12_LANE3[] = {
+	 { "rfu_value12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED96[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFREQ_CTRL0[] = {
+	 { "fcw0_frac", 0, 15, &umr_bitfield_default },
+	 { "fcw0_int", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED97[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFREQ_CTRL1[] = {
+	 { "fcw1_frac", 0, 15, &umr_bitfield_default },
+	 { "fcw1_int", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED98[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFREQ_CTRL2[] = {
+	 { "fcw_denom", 0, 15, &umr_bitfield_default },
+	 { "fcw_slew_frac", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED99[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFREQ_CTRL3[] = {
+	 { "refclk_div", 0, 1, &umr_bitfield_default },
+	 { "vco_pre_div", 3, 4, &umr_bitfield_default },
+	 { "fracn_en", 6, 6, &umr_bitfield_default },
+	 { "ssc_en", 8, 8, &umr_bitfield_default },
+	 { "fcw_sel", 10, 10, &umr_bitfield_default },
+	 { "freq_jump_en", 12, 12, &umr_bitfield_default },
+	 { "tdc_resolution", 16, 23, &umr_bitfield_default },
+	 { "dpll_cfg_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED100[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBW_CTRL_COARSE[] = {
+	 { "gi_coarse_mant", 0, 1, &umr_bitfield_default },
+	 { "gi_coarse_exp", 2, 5, &umr_bitfield_default },
+	 { "gp_coarse_mant", 7, 10, &umr_bitfield_default },
+	 { "gp_coarse_exp", 12, 15, &umr_bitfield_default },
+	 { "nctl_coarse_res", 17, 22, &umr_bitfield_default },
+	 { "nctl_coarse_frac_res", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED101[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBW_CTRL_FINE[] = {
+	 { "dpll_cfg_3", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED102[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCAL_CTRL[] = {
+	 { "bypass_freq_lock", 0, 0, &umr_bitfield_default },
+	 { "tdc_cal_en", 1, 1, &umr_bitfield_default },
+	 { "tdc_cal_ctrl", 3, 8, &umr_bitfield_default },
+	 { "meas_win_sel", 9, 10, &umr_bitfield_default },
+	 { "kdco_cal_dis", 11, 11, &umr_bitfield_default },
+	 { "kdco_ratio", 13, 20, &umr_bitfield_default },
+	 { "kdco_incr_cal_dis", 22, 22, &umr_bitfield_default },
+	 { "nctl_adj_dis", 23, 23, &umr_bitfield_default },
+	 { "refclk_rate", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED103[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLOOP_CTRL[] = {
+	 { "fbdiv_mask_en", 0, 0, &umr_bitfield_default },
+	 { "fb_slip_dis", 2, 2, &umr_bitfield_default },
+	 { "clk_tdc_sel", 4, 5, &umr_bitfield_default },
+	 { "clk_nctl_sel", 7, 8, &umr_bitfield_default },
+	 { "sig_del_patt_sel", 10, 10, &umr_bitfield_default },
+	 { "nctl_sig_del_dis", 12, 12, &umr_bitfield_default },
+	 { "fbclk_track_refclk", 14, 14, &umr_bitfield_default },
+	 { "prbs_en", 16, 16, &umr_bitfield_default },
+	 { "tdc_clk_gate_en", 18, 18, &umr_bitfield_default },
+	 { "phase_offset", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED104[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED105[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVREG_CFG[] = {
+	 { "bleeder_ac", 0, 0, &umr_bitfield_default },
+	 { "bleeder_en", 1, 1, &umr_bitfield_default },
+	 { "is_1p2", 2, 2, &umr_bitfield_default },
+	 { "reg_obs_sel", 3, 4, &umr_bitfield_default },
+	 { "reg_on_mode", 5, 6, &umr_bitfield_default },
+	 { "rlad_tap_sel", 7, 10, &umr_bitfield_default },
+	 { "reg_off_hi", 11, 11, &umr_bitfield_default },
+	 { "reg_off_lo", 12, 12, &umr_bitfield_default },
+	 { "scale_driver", 13, 14, &umr_bitfield_default },
+	 { "sel_bump", 15, 15, &umr_bitfield_default },
+	 { "sel_rladder_x", 16, 16, &umr_bitfield_default },
+	 { "short_rc_filt_x", 17, 17, &umr_bitfield_default },
+	 { "vref_pwr_on", 18, 18, &umr_bitfield_default },
+	 { "dpll_cfg_2", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED106[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOBSERVE0[] = {
+	 { "lock_det_tdc_steps", 0, 4, &umr_bitfield_default },
+	 { "clear_sticky_lock", 6, 6, &umr_bitfield_default },
+	 { "lock_det_dis", 8, 8, &umr_bitfield_default },
+	 { "dco_cfg", 10, 17, &umr_bitfield_default },
+	 { "anaobs_sel", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED107[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOBSERVE1[] = {
+	 { "digobs_sel", 0, 3, &umr_bitfield_default },
+	 { "digobs_trig_sel", 5, 8, &umr_bitfield_default },
+	 { "digobs_div", 10, 11, &umr_bitfield_default },
+	 { "digobs_trig_div", 13, 14, &umr_bitfield_default },
+	 { "lock_timer", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED108[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDFT_OUT[] = {
+	 { "dft_data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED109[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED110[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED111[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED112[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED113[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED114[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED115[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED116[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED117[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED118[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED119[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED120[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED121[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED122[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED123[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED124[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED125[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED126[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED127[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED128[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED129[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED130[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED131[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED132[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED133[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED134[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED135[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED136[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED137[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED138[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED139[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED140[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED141[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED142[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED143[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED144[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED145[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED146[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED147[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED148[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED149[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED150[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED151[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED152[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED153[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED154[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED155[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED156[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED157[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED158[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_WRAP_CNTRL1[] = {
+	 { "wrap_cfg_sel_clk", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_MACRO_CNTL_RESERVED159[] = {
+	 { "UNIPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_WRAP_CNTRL[] = {
+	 { "wrap_cfg_pll_freq_programming_ovveride", 0, 0, &umr_bitfield_default },
+	 { "wrap_cfg_pll_pwr_state_ovrride", 1, 1, &umr_bitfield_default },
+	 { "wrap_cfg_pll_pwr_state", 2, 3, &umr_bitfield_default },
+	 { "wrap_cfg_tx_pdiv_val", 5, 7, &umr_bitfield_default },
+	 { "wrap_cfg_tx_pixdiv_val", 8, 8, &umr_bitfield_default },
+	 { "wrap_cfg_cml_cmos_sel", 10, 10, &umr_bitfield_default },
+	 { "wrap_cfg_pll_rdy", 13, 13, &umr_bitfield_default },
+	 { "wrap_cfg_pll_update", 14, 14, &umr_bitfield_default },
+	 { "wrap_cfg_ref_values_chg", 15, 15, &umr_bitfield_default },
+	 { "wrap_cfg_clk_gate_w_rdy", 16, 16, &umr_bitfield_default },
+	 { "wrap_cfg_pll_dsm_sel", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_CNTL[] = {
+	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
+	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
+	 { "DIG_START", 10, 10, &umr_bitfield_default },
+	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
+	 { "TMDS_PIXEL_ENCODING", 28, 28, &umr_bitfield_default },
+	 { "TMDS_COLOR_FORMAT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_OUTPUT_CRC_CNTL[] = {
+	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
+	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_OUTPUT_CRC_RESULT[] = {
+	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_CLOCK_PATTERN[] = {
+	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_PATTERN[] = {
+	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
+	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
+	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
+	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_RANDOM_PATTERN_SEED[] = {
+	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
+	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FIFO_STATUS[] = {
+	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
+	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DIG_FIFO_READ_CLOCK_SRC", 26, 26, &umr_bitfield_default },
+	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_DISPCLK_SWITCH_CNTL[] = {
+	 { "DIG_DISPCLK_SWITCH_POINT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_DISPCLK_SWITCH_STATUS[] = {
+	 { "DIG_DISPCLK_SWITCH_ALLOWED", 0, 0, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT", 4, 4, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_CONTROL[] = {
+	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_DATA_SCRAMBLE_EN", 1, 1, &umr_bitfield_default },
+	 { "HDMI_CLOCK_CHANNEL_RATE", 2, 2, &umr_bitfield_default },
+	 { "HDMI_NO_EXTRA_NULL_PACKET_FILLED", 3, 3, &umr_bitfield_default },
+	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
+	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
+	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_STATUS[] = {
+	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
+	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
+	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_AUDIO_PACKET_CONTROL[] = {
+	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
+	 { "HDMI_AUDIO_SEND_MAX_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_PACKET_CONTROL[] = {
+	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
+	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
+	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
+	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_VBI_PACKET_CONTROL[] = {
+	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
+	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_INFOFRAME_CONTROL0[] = {
+	 { "HDMI_AVI_INFO_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_AVI_INFO_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_INFOFRAME_CONTROL1[] = {
+	 { "HDMI_AVI_INFO_LINE", 0, 5, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GENERIC_PACKET_CONTROL0[] = {
+	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GC[] = {
+	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
+	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
+	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
+	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL2[] = {
+	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
+	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
+	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_0[] = {
+	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
+	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_1[] = {
+	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_2[] = {
+	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_3[] = {
+	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_4[] = {
+	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_0[] = {
+	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_1[] = {
+	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_2[] = {
+	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_3[] = {
+	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO0[] = {
+	 { "AFMT_AVI_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_S", 8, 9, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_B", 10, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_A", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Y", 13, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_R", 16, 19, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_M", 20, 21, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_C", 22, 23, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_SC", 24, 25, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Q", 26, 27, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_EC", 28, 30, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_ITC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO1[] = {
+	 { "AFMT_AVI_INFO_VIC", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PR", 8, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_CN", 12, 13, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_YQ", 14, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO2[] = {
+	 { "AFMT_AVI_INFO_BOTTOM", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_LEFT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO3[] = {
+	 { "AFMT_AVI_INFO_RIGHT", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_VERSION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO0[] = {
+	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO1[] = {
+	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_HDR[] = {
+	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_0[] = {
+	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_1[] = {
+	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_2[] = {
+	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_3[] = {
+	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_4[] = {
+	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_5[] = {
+	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_6[] = {
+	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_7[] = {
+	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GENERIC_PACKET_CONTROL1[] = {
+	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_32_0[] = {
+	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_32_1[] = {
+	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_44_0[] = {
+	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_44_1[] = {
+	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_48_0[] = {
+	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_48_1[] = {
+	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_STATUS_0[] = {
+	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_STATUS_1[] = {
+	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO0[] = {
+	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO1[] = {
+	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_0[] = {
+	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
+	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
+	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
+	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
+	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_1[] = {
+	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_CONTROL[] = {
+	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL0[] = {
+	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
+	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL1[] = {
+	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL2[] = {
+	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL3[] = {
+	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_2[] = {
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_RESULT[] = {
+	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_STATUS[] = {
+	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL[] = {
+	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
+	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
+	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
+	 { "AFMT_BLANK_TEST_DATA_ON_ENC_ENB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_VBI_PACKET_CONTROL[] = {
+	 { "AFMT_GENERIC0_UPDATE", 2, 2, &umr_bitfield_default },
+	 { "AFMT_GENERIC2_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "AFMT_GENERIC_INDEX", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_INFOFRAME_CONTROL0[] = {
+	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_SRC_CONTROL[] = {
+	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_DBG_DTO_CNTL[] = {
+	 { "AFMT_AUDIO_DTO_FS_DIV_SEL", 0, 2, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_BASE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_MULTI", 12, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_DIV", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_BE_CNTL[] = {
+	 { "DIG_DUAL_LINK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DIG_SWAP", 1, 1, &umr_bitfield_default },
+	 { "DIG_RB_SWITCH_EN", 2, 2, &umr_bitfield_default },
+	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
+	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
+	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_BE_EN_CNTL[] = {
+	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CNTL[] = {
+	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CONTROL_CHAR[] = {
+	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CONTROL0_FEEDBACK[] = {
+	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
+	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_STEREOSYNC_CTL_SEL[] = {
+	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_SYNC_CHAR_PATTERN_0_1[] = {
+	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
+	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_SYNC_CHAR_PATTERN_2_3[] = {
+	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
+	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_DEBUG[] = {
+	 { "TMDS_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_DEBUG_HSYNC", 8, 8, &umr_bitfield_default },
+	 { "TMDS_DEBUG_HSYNC_EN", 9, 9, &umr_bitfield_default },
+	 { "TMDS_DEBUG_VSYNC", 16, 16, &umr_bitfield_default },
+	 { "TMDS_DEBUG_VSYNC_EN", 17, 17, &umr_bitfield_default },
+	 { "TMDS_DEBUG_DE", 24, 24, &umr_bitfield_default },
+	 { "TMDS_DEBUG_DE_EN", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL_BITS[] = {
+	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
+	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
+	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
+	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_DCBALANCER_CONTROL[] = {
+	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_SYNC_DCBAL_EN", 4, 6, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL0_1_GEN_CNTL[] = {
+	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
+	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
+	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
+	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
+	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
+	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
+	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
+	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL2_3_GEN_CNTL[] = {
+	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
+	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
+	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
+	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
+	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
+	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
+	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_VERSION[] = {
+	 { "DIG_TYPE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_LANE_ENABLE[] = {
+	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
+	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
+	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
+	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_DEBUG_INDEX[] = {
+	 { "DIG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DIG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_DEBUG_DATA[] = {
+	 { "DIG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_TEST_DEBUG_INDEX[] = {
+	 { "DIG_FE_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DIG_FE_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_TEST_DEBUG_DATA[] = {
+	 { "DIG_FE_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_CNTL[] = {
+	 { "AFMT_AUDIO_CLOCK_EN", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CLOCK_ON", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_LINK_CNTL[] = {
+	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
+	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_PIXEL_FORMAT[] = {
+	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
+	 { "DP_DYN_RANGE", 8, 8, &umr_bitfield_default },
+	 { "DP_YCBCR_RANGE", 16, 16, &umr_bitfield_default },
+	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_COLORIMETRY[] = {
+	 { "DP_MSA_MISC0_OVERRIDE", 0, 7, &umr_bitfield_default },
+	 { "DP_MSA_MISC0_OVERRIDE_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DP_MSA_MISC1_BIT7_OVERRIDE", 9, 9, &umr_bitfield_default },
+	 { "DP_MSA_MISC1_BIT7_OVERRIDE_ENABLE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_CONFIG[] = {
+	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_STREAM_CNTL[] = {
+	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
+	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
+	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_STEER_FIFO[] = {
+	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
+	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
+	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_MISC[] = {
+	 { "DP_MSA_MISC1", 3, 6, &umr_bitfield_default },
+	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
+	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
+	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_TIMING[] = {
+	 { "DP_VID_TIMING_MODE", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_M_N_DOUBLE_BUFFER_MODE", 4, 4, &umr_bitfield_default },
+	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
+	 { "DP_VID_M_DOUBLE_VALUE_EN", 9, 9, &umr_bitfield_default },
+	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_N[] = {
+	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_M[] = {
+	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_LINK_FRAMING_CNTL[] = {
+	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
+	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_HBR2_EYE_PATTERN[] = {
+	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_MSA_VBID[] = {
+	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
+	 { "DP_VID_MSA_TOP_FIELD_MODE", 16, 16, &umr_bitfield_default },
+	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_INTERRUPT_CNTL[] = {
+	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CNTL[] = {
+	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
+	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_TRAINING_PATTERN_SEL[] = {
+	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM0[] = {
+	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
+	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM1[] = {
+	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
+	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM2[] = {
+	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_8B10B_CNTL[] = {
+	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
+	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
+	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_PRBS_CNTL[] = {
+	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SCRAM_CNTL[] = {
+	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
+	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_EN[] = {
+	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_CNTL[] = {
+	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_RESULT[] = {
+	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_MST_CNTL[] = {
+	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_MST_STATUS[] = {
+	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_FAST_TRAINING[] = {
+	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_FAST_TRAINING_STATUS[] = {
+	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_V_TIMING_OVERRIDE1[] = {
+	 { "DP_MSA_V_TIMING_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "DP_MSA_V_TOTAL_OVERRIDE", 4, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_V_TIMING_OVERRIDE2[] = {
+	 { "DP_MSA_V_BLANK_START_OVERRIDE", 0, 13, &umr_bitfield_default },
+	 { "DP_MSA_V_BLANK_END_OVERRIDE", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_CNTL[] = {
+	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "DP_SEC_AVI_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_CNTL1[] = {
+	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_PRIORITY", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_SEND", 5, 5, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_SEND_PENDING", 6, 6, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_SEND_DEADLINE_MISSED", 7, 7, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_LINE_NUM", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING1[] = {
+	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
+	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING2[] = {
+	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
+	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING3[] = {
+	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
+	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING4[] = {
+	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
+	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
+	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_N[] = {
+	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_N_READBACK[] = {
+	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_M[] = {
+	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_M_READBACK[] = {
+	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_TIMESTAMP[] = {
+	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_PACKET_CNTL[] = {
+	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
+	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
+	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_RATE_CNTL[] = {
+	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
+	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_RATE_UPDATE[] = {
+	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT0[] = {
+	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT1[] = {
+	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT2[] = {
+	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT_UPDATE[] = {
+	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
+	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_LINK_TIMING[] = {
+	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
+	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_MISC_CNTL[] = {
+	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
+	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
+	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
+	 { "DP_MSE_OUTPUT_DPDBG_DATA", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_TEST_DEBUG_INDEX[] = {
+	 { "DP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_TEST_DEBUG_DATA[] = {
+	 { "DP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_FE_TEST_DEBUG_INDEX[] = {
+	 { "DP_FE_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DP_FE_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_FE_TEST_DEBUG_DATA[] = {
+	 { "DP_FE_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_BS_SR_SWAP_CNTL[] = {
+	 { "DPHY_LOAD_BS_COUNT", 0, 9, &umr_bitfield_default },
+	 { "DPHY_BS_SR_SWAP_DONE", 15, 15, &umr_bitfield_default },
+	 { "DPHY_LOAD_BS_COUNT_START", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_HBR2_PATTERN_CONTROL[] = {
+	 { "DP_DPHY_HBR2_PATTERN_CONTROL", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT0_STATUS[] = {
+	 { "DP_MSE_SAT_SRC0_STATUS", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT0_STATUS", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC1_STATUS", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT1_STATUS", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT1_STATUS[] = {
+	 { "DP_MSE_SAT_SRC2_STATUS", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT2_STATUS", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC3_STATUS", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT3_STATUS", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT2_STATUS[] = {
+	 { "DP_MSE_SAT_SRC4_STATUS", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT4_STATUS", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC5_STATUS", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT5_STATUS", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL5[] = {
+	 { "INPUT_CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL5[] = {
+	 { "CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_STREAM_DEBUG[] = {
+	 { "STREAM_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR4[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG5[] = {
+	 { "DCIO_DEBUG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR05[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT05[] = {
+	 { "H_SYNC_END", 0, 4, &umr_bitfield_default },
+	 { "H_SYNC_SKEW", 5, 6, &umr_bitfield_default },
+	 { "H_BLANK_END_B5", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
+	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
+	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
+	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
+	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[] = {
+	 { "AZALIA_INPUT_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[] = {
+	 { "AZALIA_INPUT_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED0[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED1[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED2[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED3[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED4[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED5[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED6[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED7[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED8[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED9[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED10[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED11[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED12[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED13[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED14[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED15[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED16[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED17[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED18[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED19[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED20[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED21[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED22[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED23[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED24[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED25[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED26[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED27[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED28[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED29[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED30[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED31[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED32[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED33[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED34[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED35[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED36[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED37[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED38[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED39[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED40[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED41[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED42[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED43[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED44[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED45[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED46[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED47[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED48[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED49[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED50[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED51[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED52[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED53[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED54[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED55[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED56[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED57[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED58[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED59[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED60[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED61[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED62[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED63[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED64[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED65[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED66[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED67[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED68[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED69[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED70[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED71[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED72[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED73[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED74[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED75[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED76[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED77[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED78[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED79[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED80[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED81[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED82[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED83[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED84[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED85[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED86[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED87[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED88[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED89[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED90[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED91[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED92[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED93[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED94[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED95[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED96[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED97[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED98[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED99[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED100[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED101[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED102[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED103[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED104[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED105[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED106[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED107[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED108[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED109[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED110[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED111[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED112[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED113[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED114[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED115[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED116[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED117[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED118[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED119[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED120[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED121[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED122[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED123[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED124[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED125[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED126[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED127[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED128[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED129[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED130[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED131[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED132[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED133[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED134[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED135[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED136[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED137[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED138[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED139[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED140[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED141[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED142[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED143[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED144[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED145[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED146[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED147[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED148[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED149[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED150[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED151[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED152[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED153[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED154[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED155[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED156[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED157[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED158[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED159[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED160[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED161[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED162[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED163[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED164[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED165[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED166[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED167[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED168[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED169[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED170[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED171[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED172[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED173[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED174[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED175[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED176[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED177[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED178[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED179[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED180[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED181[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED182[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED183[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED184[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED185[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED186[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED187[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED188[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED189[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED190[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED191[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED192[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED193[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED194[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED195[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED196[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED197[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED198[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED199[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED200[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED201[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED202[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED203[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED204[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED205[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED206[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED207[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED208[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED209[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED210[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED211[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED212[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED213[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED214[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED215[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED216[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED217[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED218[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED219[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED220[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED221[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED222[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED223[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED224[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED225[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED226[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED227[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED228[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED229[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED230[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED231[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED232[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED233[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED234[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED235[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED236[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED237[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED238[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED239[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED240[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED241[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED242[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED243[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED244[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED245[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED246[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED247[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED248[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED249[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED250[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED251[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED252[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED253[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED254[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED255[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED256[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED257[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED258[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED259[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED260[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED261[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED262[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED263[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED264[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED265[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED266[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED267[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED268[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED269[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED270[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED271[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED272[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED273[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED274[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED275[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED276[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED277[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED278[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED279[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED280[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED281[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED282[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED283[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED284[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED285[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED286[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED287[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED288[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED289[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED290[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED291[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED292[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED293[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED294[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED295[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED296[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED297[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED298[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED299[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED300[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED301[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED302[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED303[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED304[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED305[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED306[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED307[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED308[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED309[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED310[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED311[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED312[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED313[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED314[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED315[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED316[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED317[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED318[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED319[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED320[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED321[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED322[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED323[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED324[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED325[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED326[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED327[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED328[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED329[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED330[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED331[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED332[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED333[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED334[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED335[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED336[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED337[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED338[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED339[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED340[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED341[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED342[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED343[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED344[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED345[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED346[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED347[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED348[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED349[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED350[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED351[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED352[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED353[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED354[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED355[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED356[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED357[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED358[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED359[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED360[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED361[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED362[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED363[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED364[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED365[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED366[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED367[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED368[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED369[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED370[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED371[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED372[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED373[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED374[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED375[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED376[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED377[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED378[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCRX_PHY_MACRO_CNTL_RESERVED379[] = {
+	 { "DCRX_PHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_CONTROL[] = {
+	 { "AUX_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_RESET", 4, 4, &umr_bitfield_default },
+	 { "AUX_RESET_DONE", 5, 5, &umr_bitfield_default },
+	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
+	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
+	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
+	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
+	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
+	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
+	 { "SPARE_0", 30, 30, &umr_bitfield_default },
+	 { "SPARE_1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_CONTROL[] = {
+	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
+	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
+	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_ARB_CONTROL[] = {
+	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
+	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_INTERRUPT_CONTROL[] = {
+	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_STATUS[] = {
+	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_STATUS[] = {
+	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_DATA[] = {
+	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
+	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_DATA[] = {
+	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_REF_CONTROL[] = {
+	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
+	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_CONTROL[] = {
+	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
+	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
+	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL0[] = {
+	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
+	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
+	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
+	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
+	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
+	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL1[] = {
+	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_STATUS[] = {
+	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_STATUS[] = {
+	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
+	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_ERROR_CONTROL[] = {
+	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
+	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_CONTROLLER_STATUS[] = {
+	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_STATUS[] = {
+	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
+	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_TEST_DEBUG_INDEX[] = {
+	 { "AUX_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AUX_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_TEST_DEBUG_DATA[] = {
+	 { "AUX_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED0[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED1[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED2[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED3[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED4[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED5[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED6[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED7[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED8[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED9[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED10[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED11[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED12[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED13[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED14[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED15[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED16[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED17[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED18[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED19[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED20[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED21[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED22[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED23[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED24[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED25[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED26[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED27[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED28[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED29[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED30[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED31[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED32[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED33[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED34[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED35[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED36[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED37[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED38[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED39[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED40[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED41[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED42[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED43[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED44[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED45[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED46[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED47[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED48[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED49[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED50[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED51[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED52[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED53[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED54[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED55[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED56[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED57[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED58[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED59[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED60[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED61[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED62[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPHY_MACRO_CNTL_RESERVED63[] = {
+	 { "DPHY_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_ENABLE[] = {
+	 { "WB_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_EC_CONFIG[] = {
+	 { "DISPCLK_R_WB_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_G_WB_GATE_DIS", 1, 1, &umr_bitfield_default },
+	 { "DISPCLK_G_WBSCL_GATE_DIS", 2, 2, &umr_bitfield_default },
+	 { "WB_TEST_CLK_SEL", 3, 6, &umr_bitfield_default },
+	 { "WB_LB_LS_DIS", 7, 7, &umr_bitfield_default },
+	 { "WB_LB_SD_DIS", 8, 8, &umr_bitfield_default },
+	 { "WB_LUT_LS_DIS", 9, 9, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_MODE_SEL", 12, 13, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_DIS", 14, 14, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_FORCE", 15, 16, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_STATE_SM", 17, 18, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_STATE_BG", 19, 20, &umr_bitfield_default },
+	 { "WBSCL_LB_MEM_PWR_STATE", 21, 22, &umr_bitfield_default },
+	 { "WB_RAM_PW_SAVE_MODE", 23, 23, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE_SM", 24, 25, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE_BG", 26, 27, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
+	 { "LUT_MEM_PWR_STATE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_MODE[] = {
+	 { "CNV_FRAME_CAPTURE_RATE", 8, 9, &umr_bitfield_default },
+	 { "CNV_WINDOW_CROP_EN", 12, 12, &umr_bitfield_default },
+	 { "CNV_STEREO_TYPE", 13, 14, &umr_bitfield_default },
+	 { "CNV_INTERLACED_MODE", 15, 15, &umr_bitfield_default },
+	 { "CNV_EYE_SELECTION", 16, 17, &umr_bitfield_default },
+	 { "CNV_STEREO_POLARITY", 18, 18, &umr_bitfield_default },
+	 { "CNV_INTERLACED_FIELD_ORDER", 19, 19, &umr_bitfield_default },
+	 { "CNV_STEREO_SPLIT", 20, 20, &umr_bitfield_default },
+	 { "CNV_NEW_CONTENT", 24, 24, &umr_bitfield_default },
+	 { "CNV_FRAME_CAPTURE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_WINDOW_START[] = {
+	 { "CNV_WINDOW_START_X", 0, 11, &umr_bitfield_default },
+	 { "CNV_WINDOW_START_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_WINDOW_SIZE[] = {
+	 { "CNV_WINDOW_WIDTH", 0, 11, &umr_bitfield_default },
+	 { "CNV_WINDOW_HEIGHT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_UPDATE[] = {
+	 { "CNV_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CNV_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "CNV_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_SOURCE_SIZE[] = {
+	 { "CNV_SOURCE_WIDTH", 0, 14, &umr_bitfield_default },
+	 { "CNV_SOURCE_HEIGHT", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CONTROL[] = {
+	 { "CNV_CSC_BYPASS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C11_C12[] = {
+	 { "CNV_CSC_C11", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C12", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C13_C14[] = {
+	 { "CNV_CSC_C13", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C14", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C21_C22[] = {
+	 { "CNV_CSC_C21", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C22", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C23_C24[] = {
+	 { "CNV_CSC_C23", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C24", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C31_C32[] = {
+	 { "CNV_CSC_C31", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C32", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C33_C34[] = {
+	 { "CNV_CSC_C33", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C34", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_R[] = {
+	 { "CNV_CSC_ROUND_OFFSET_R", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_G[] = {
+	 { "CNV_CSC_ROUND_OFFSET_G", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_B[] = {
+	 { "CNV_CSC_ROUND_OFFSET_B", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_R[] = {
+	 { "CNV_CSC_CLAMP_UPPER_R", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_G[] = {
+	 { "CNV_CSC_CLAMP_UPPER_G", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_B[] = {
+	 { "CNV_CSC_CLAMP_UPPER_B", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CNTL[] = {
+	 { "CNV_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_RED[] = {
+	 { "CNV_TEST_CRC_RED_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_GREEN[] = {
+	 { "CNV_TEST_CRC_GREEN_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_BLUE[] = {
+	 { "CNV_TEST_CRC_BLUE_MASK", 4, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_DEBUG_CTRL[] = {
+	 { "WB_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_DEBUG_SEL", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_DBG_MODE[] = {
+	 { "WB_DBG_MODE_EN", 0, 0, &umr_bitfield_default },
+	 { "WB_DBG_DIN_FMT", 1, 1, &umr_bitfield_default },
+	 { "WB_DBG_36MODE", 2, 2, &umr_bitfield_default },
+	 { "WB_DBG_CMAP", 3, 3, &umr_bitfield_default },
+	 { "WB_DBG_PXLRATE_ERROR", 8, 8, &umr_bitfield_default },
+	 { "WB_DBG_SOURCE_WIDTH", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_HW_DEBUG[] = {
+	 { "WB_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_INPUT_SELECT[] = {
+	 { "CNV_INPUT_SRC_SELECT", 0, 1, &umr_bitfield_default },
+	 { "CNV_INPUT_PIPE_SELECT", 2, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_DEBUG_INDEX[] = {
+	 { "CNV_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CNV_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_DEBUG_DATA[] = {
+	 { "CNV_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_SOFT_RESET[] = {
+	 { "WB_SOFT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_WARM_UP_MODE_CTL1[] = {
+	 { "WIDTH_WARMUP", 0, 14, &umr_bitfield_default },
+	 { "HEIGHT_WARMUP", 16, 30, &umr_bitfield_default },
+	 { "GMC_WARM_UP_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWB_WARM_UP_MODE_CTL2[] = {
+	 { "DATA_VALUE_WARMUP", 0, 7, &umr_bitfield_default },
+	 { "MODE_WARMUP", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED0[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED1[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED2[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED3[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED4[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED5[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED6[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED7[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED8[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED9[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED10[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPLL_MACRO_CNTL_RESERVED11[] = {
+	 { "CPLL_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[] = {
+	 { "OUTSTRMPAY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_STREAM_PAYLOAD_CAPABILITY[] = {
+	 { "INSTRMPAY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL6[] = {
+	 { "INPUT_CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL6[] = {
+	 { "CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR5[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG6[] = {
+	 { "DCIO_DEBUG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR06[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT06[] = {
+	 { "V_TOTAL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
+	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
+	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
+	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
+	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[] = {
+	 { "CODING_TYPE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
+	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
+	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[] = {
+	 { "FORMAT_CHANGED", 0, 0, &umr_bitfield_default },
+	 { "FORMAT_CHANGED_ACK_UR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_REASON", 8, 15, &umr_bitfield_default },
+	 { "FORMAT_CHANGE_RESPONSE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[] = {
+	 { "WIRELESS_DISPLAY_IDENTIFICATION", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[] = {
+	 { "REMOTE_KEEP_ALIVE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REMOTE_KEEP_ALIVE_CAPABILITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_ENABLE_STATUS[] = {
+	 { "AUDIO_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[] = {
+	 { "AUDIO_ENABLED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_ENABLED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[] = {
+	 { "AUDIO_DISABLED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_DISABLED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_DISABLED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[] = {
+	 { "AUDIO_FORMAT_CHANGED_FLAG", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_FORMAT_CHANGED_MASK", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_FORMAT_CHANGED_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_INPUT_CRC0_CHANNEL7[] = {
+	 { "INPUT_CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL7[] = {
+	 { "CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR6[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG7[] = {
+	 { "DCIO_DEBUG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR07[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT07[] = {
+	 { "V_TOTAL_B8", 0, 0, &umr_bitfield_default },
+	 { "V_DISP_END_B8", 1, 1, &umr_bitfield_default },
+	 { "V_SYNC_START_B8", 2, 2, &umr_bitfield_default },
+	 { "V_BLANK_START_B8", 3, 3, &umr_bitfield_default },
+	 { "LINE_CMP_B8", 4, 4, &umr_bitfield_default },
+	 { "V_TOTAL_B9", 5, 5, &umr_bitfield_default },
+	 { "V_DISP_END_B9", 6, 6, &umr_bitfield_default },
+	 { "V_SYNC_START_B9", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "IN_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
+	 { "MISC", 0, 3, &umr_bitfield_default },
+	 { "COLOR", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
+	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
+	 { "LOCATION", 0, 5, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[] = {
+	 { "MULTICHANNEL0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL0_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL0_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[] = {
+	 { "MULTICHANNEL2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL2_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL2_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[] = {
+	 { "MULTICHANNEL4_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL4_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL4_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[] = {
+	 { "MULTICHANNEL6_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL6_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL6_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
+	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
+	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
+	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[] = {
+	 { "LPIB_SNAPSHOT_LOCK", 0, 0, &umr_bitfield_default },
+	 { "CYCLIC_BUFFER_WRAP_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[] = {
+	 { "LPIB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[] = {
+	 { "LPIB_TIMER_SNAPSHOT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[] = {
+	 { "INPUT_ACTIVITY", 0, 0, &umr_bitfield_default },
+	 { "CHANNEL_LAYOUT", 1, 2, &umr_bitfield_default },
+	 { "INPUT_ACTIVITY_UR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CL_CS_INFOFRAME_CHANGE_UR_ENABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[] = {
+	 { "CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "INFOFRAME_BYTE_5", 16, 23, &umr_bitfield_default },
+	 { "INFOFRAME_VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[] = {
+	 { "CHANNEL_STATUS_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[] = {
+	 { "CHANNEL_STATUS_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGADCC_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CONTROL[] = {
+	 { "STREAM_0_INTERRUPT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_INTERRUPT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_INTERRUPT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_INTERRUPT_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_INTERRUPT_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_INTERRUPT_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_INTERRUPT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_INTERRUPT_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_INTERRUPT_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_INTERRUPT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_INTERRUPT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_INTERRUPT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_INTERRUPT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_INTERRUPT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "CONTROLLER_INTERRUPT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GLOBAL_INTERRUPT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG8[] = {
+	 { "DCIO_DEBUG8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR08[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT08[] = {
+	 { "ROW_SCAN_START", 0, 4, &umr_bitfield_default },
+	 { "BYTE_PAN", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWALL_CLOCK_COUNTER_ALIAS[] = {
+	 { "WALL_CLOCK_COUNTER_ALIAS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
+	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
+	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF02_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR8[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_STATUS[] = {
+	 { "STREAM_0_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_INTERRUPT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_INTERRUPT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_INTERRUPT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_INTERRUPT_STATUS", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_INTERRUPT_STATUS", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_INTERRUPT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_INTERRUPT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_INTERRUPT_STATUS", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_INTERRUPT_STATUS", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_INTERRUPT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_INTERRUPT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_INTERRUPT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_INTERRUPT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "CONTROLLER_INTERRUPT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GLOBAL_INTERRUPT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG9[] = {
+	 { "DCIO_DEBUG9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR09[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT09[] = {
+	 { "MAX_ROW_SCAN", 0, 4, &umr_bitfield_default },
+	 { "V_BLANK_START_B9", 5, 5, &umr_bitfield_default },
+	 { "LINE_CMP_B9", 6, 6, &umr_bitfield_default },
+	 { "DOUBLE_CHAR_HEIGHT", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMP_EN_CTL[] = {
+	 { "comp_en", 0, 0, &umr_bitfield_default },
+	 { "comp_en_override", 2, 2, &umr_bitfield_default },
+	 { "comp_done", 4, 4, &umr_bitfield_default },
+	 { "zcal_code_override", 6, 6, &umr_bitfield_default },
+	 { "zcal_cal_rtt", 7, 7, &umr_bitfield_default },
+	 { "zcal_base_en", 8, 8, &umr_bitfield_default },
+	 { "zcal_ht_rtt_sel", 9, 9, &umr_bitfield_default },
+	 { "zcal_code", 10, 14, &umr_bitfield_default },
+	 { "zcal_ron_cal_mode", 16, 16, &umr_bitfield_default },
+	 { "zcal_ana_dbg_sel", 17, 18, &umr_bitfield_default },
+	 { "cfg_cml_cmos_sel", 19, 19, &umr_bitfield_default },
+	 { "dsm_sel", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[] = {
+	 { "PRESENTATION_TIME_OFFSET_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMIF_DEBUG02_CORE1[] = {
+	 { "DB_DATA", 0, 15, &umr_bitfield_default },
+	 { "MC_RDRET_COUNT_EN", 16, 16, &umr_bitfield_default },
+	 { "MC_RDRET_COUNTER", 17, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR9[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGA[] = {
+	 { "DCIO_DEBUGA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0A[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0A[] = {
+	 { "CURSOR_START", 0, 4, &umr_bitfield_default },
+	 { "CURSOR_DISABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF04_DBG_DCCIF_E[] = {
+	 { "DBG_DCCIF_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR10[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION6[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGB[] = {
+	 { "DCIO_DEBUGB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0B[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0B[] = {
+	 { "CURSOR_END", 0, 4, &umr_bitfield_default },
+	 { "CURSOR_SKEW", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
+	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF05_DBG_DCCIF_F[] = {
+	 { "DBG_DCCIF_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWALL_CLOCK_COUNTER[] = {
+	 { "WALL_CLOCK_COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION7[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_12[] = {
+	 { "IDEC_MVP_DATA_A_H", 0, 0, &umr_bitfield_default },
+	 { "IDEC_MVP_DATA_A", 1, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGC[] = {
+	 { "DCIO_DEBUGC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0C[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0C[] = {
+	 { "DISP_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_RENDER_CONTROL[] = {
+	 { "VGA_BLINK_RATE", 0, 4, &umr_bitfield_default },
+	 { "VGA_BLINK_MODE", 5, 6, &umr_bitfield_default },
+	 { "VGA_CURSOR_BLINK_INVERT", 7, 7, &umr_bitfield_default },
+	 { "VGA_EXTD_ADDR_COUNT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_VSTATUS_CNTL", 16, 17, &umr_bitfield_default },
+	 { "VGA_LOCK_8DOT", 24, 24, &umr_bitfield_default },
+	 { "VGAREG_LINECMP_COMPATIBILITY_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SEQUENCER_RESET_CONTROL[] = {
+	 { "D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 0, 0, &umr_bitfield_default },
+	 { "D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 1, 1, &umr_bitfield_default },
+	 { "D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 2, 2, &umr_bitfield_default },
+	 { "D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 3, 3, &umr_bitfield_default },
+	 { "D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 4, 4, &umr_bitfield_default },
+	 { "D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 5, 5, &umr_bitfield_default },
+	 { "D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 8, 8, &umr_bitfield_default },
+	 { "D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 9, 9, &umr_bitfield_default },
+	 { "D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 10, 10, &umr_bitfield_default },
+	 { "D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 11, 11, &umr_bitfield_default },
+	 { "D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 12, 12, &umr_bitfield_default },
+	 { "D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 13, 13, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT", 17, 17, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INDEX_SELECT", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MODE_CONTROL[] = {
+	 { "VGA_ATI_LINEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_LUT_PALETTE_UPDATE_MODE", 4, 5, &umr_bitfield_default },
+	 { "VGA_128K_APERTURE_PAGING", 8, 8, &umr_bitfield_default },
+	 { "VGA_TEXT_132_COLUMNS_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SURFACE_PITCH_SELECT[] = {
+	 { "VGA_SURFACE_PITCH_SELECT", 0, 1, &umr_bitfield_default },
+	 { "VGA_SURFACE_HEIGHT_SELECT", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_INDEX[] = {
+	 { "VGA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "VGA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF1_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF1_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_DATA[] = {
+	 { "VGA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF2_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF2_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS_HIGH[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HDP_CONTROL[] = {
+	 { "VGA_MEM_PAGE_SELECT_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_MEMORY_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "VGA_RBBM_LOCK_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RESET_CONTROL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_CACHE_CONTROL[] = {
+	 { "VGA_WRITE_THROUGH_CACHE_DIS", 0, 0, &umr_bitfield_default },
+	 { "VGA_READ_CACHE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_READ_BUFFER_INVALIDATE", 16, 16, &umr_bitfield_default },
+	 { "VGA_DCCIF_W256ONLY", 20, 20, &umr_bitfield_default },
+	 { "VGA_DCCIF_WC_TIMEOUT", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD1VGA_CONTROL[] = {
+	 { "D1VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D1VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D1VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D1VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D1VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD2VGA_CONTROL[] = {
+	 { "D2VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D2VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D2VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D2VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D2VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HW_DEBUG[] = {
+	 { "VGA_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
+	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR12[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION8[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_13[] = {
+	 { "IDED_MVP_DATA_B_H", 0, 0, &umr_bitfield_default },
+	 { "IDED_MVP_DATA_B", 1, 24, &umr_bitfield_default },
+	 { "IDED_START_READ_B", 25, 25, &umr_bitfield_default },
+	 { "IDED_READ_FIFO_ENTRY_DE_B", 26, 26, &umr_bitfield_default },
+	 { "IDED_WRITE_ADD_B", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGD[] = {
+	 { "DCIO_DEBUGD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0D[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0D[] = {
+	 { "DISP_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS[] = {
+	 { "VGA_MEM_ACCESS_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_STATUS", 1, 1, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_CONTROL[] = {
+	 { "VGA_MEM_ACCESS_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_MASK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS_CLEAR[] = {
+	 { "VGA_MEM_ACCESS_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_STATUS[] = {
+	 { "VGA_MEM_ACCESS_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MAIN_CONTROL[] = {
+	 { "VGA_CRTC_TIMEOUT", 0, 1, &umr_bitfield_default },
+	 { "VGA_RENDER_TIMEOUT_COUNT", 3, 4, &umr_bitfield_default },
+	 { "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION", 5, 7, &umr_bitfield_default },
+	 { "VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT", 8, 9, &umr_bitfield_default },
+	 { "VGA_MC_WRITE_CLEAN_WAIT_DELAY", 12, 15, &umr_bitfield_default },
+	 { "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT", 16, 17, &umr_bitfield_default },
+	 { "VGA_READBACK_CRT_INTR_SOURCE_SELECT", 24, 25, &umr_bitfield_default },
+	 { "VGA_READBACK_SENSE_SWITCH_SELECT", 26, 26, &umr_bitfield_default },
+	 { "VGA_READ_URGENT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "VGA_WRITES_URGENT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "VGA_EXTERNAL_DAC_SENSE", 29, 29, &umr_bitfield_default },
+	 { "VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_CONTROL[] = {
+	 { "VGA_TEST_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_START", 8, 8, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DONE", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DISPBUF_SELECT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_INDEX[] = {
+	 { "VGA_DEBUG_READBACK_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_DATA[] = {
+	 { "VGA_DEBUG_READBACK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
+	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTREAM_SYNCHRONIZATION[] = {
+	 { "STREAM_0_SYNCHRONIZATION", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_SYNCHRONIZATION", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_SYNCHRONIZATION", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_SYNCHRONIZATION", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_SYNCHRONIZATION", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_SYNCHRONIZATION", 5, 5, &umr_bitfield_default },
+	 { "STREAM_6_SYNCHRONIZATION", 6, 6, &umr_bitfield_default },
+	 { "STREAM_7_SYNCHRONIZATION", 7, 7, &umr_bitfield_default },
+	 { "STREAM_8_SYNCHRONIZATION", 8, 8, &umr_bitfield_default },
+	 { "STREAM_9_SYNCHRONIZATION", 9, 9, &umr_bitfield_default },
+	 { "STREAM_10_SYNCHRONIZATION", 10, 10, &umr_bitfield_default },
+	 { "STREAM_11_SYNCHRONIZATION", 11, 11, &umr_bitfield_default },
+	 { "STREAM_12_SYNCHRONIZATION", 12, 12, &umr_bitfield_default },
+	 { "STREAM_13_SYNCHRONIZATION", 13, 13, &umr_bitfield_default },
+	 { "STREAM_14_SYNCHRONIZATION", 14, 14, &umr_bitfield_default },
+	 { "STREAM_15_SYNCHRONIZATION", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR13[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION9[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_14[] = {
+	 { "IDEE_READ_ADD", 0, 2, &umr_bitfield_default },
+	 { "IDEE_WRITE_ADD_A", 3, 5, &umr_bitfield_default },
+	 { "IDEE_WRITE_ADD_B", 6, 8, &umr_bitfield_default },
+	 { "IDEE_START_READ", 9, 9, &umr_bitfield_default },
+	 { "IDEE_START_READ_B", 10, 10, &umr_bitfield_default },
+	 { "IDEE_START_INCR_WR_A", 11, 11, &umr_bitfield_default },
+	 { "IDEE_START_INCR_WR_B", 12, 12, &umr_bitfield_default },
+	 { "IDEE_WRITE2FIFO", 13, 13, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENTRY_DE", 14, 14, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENTRY_DE_B", 15, 15, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_DE", 16, 16, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_DE_B", 17, 17, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "IDEE_CRTC1_CNTL_CAPTURE_START_A", 19, 19, &umr_bitfield_default },
+	 { "IDEE_CRC_PHASE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGE[] = {
+	 { "DCIO_DIGA_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0E[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0E[] = {
+	 { "CURSOR_LOC_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_DATA[] = {
+	 { "VCRTC_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_IDX[] = {
+	 { "VCRTC_IDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_WT[] = {
+	 { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENS1[] = {
+	 { "NO_DISPLAY", 0, 0, &umr_bitfield_default },
+	 { "VGA_VSTATUS", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_READ_BACK", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION10[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_15[] = {
+	 { "IDEF_MVP_ASYNC_FIFO_WEN", 0, 0, &umr_bitfield_default },
+	 { "IDEF_MVP_ASYNC_FIFO_WDATA", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGF[] = {
+	 { "DCIO_DIGB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0F[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0F[] = {
+	 { "CURSOR_LOC_LO", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_WT[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENENB[] = {
+	 { "BLK_IO_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENS0[] = {
+	 { "SENSE_SWITCH", 4, 4, &umr_bitfield_default },
+	 { "CRT_INTR", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_R_INDEX[] = {
+	 { "DAC_R_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEQ8_DATA[] = {
+	 { "SEQ_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MASK[] = {
+	 { "DAC_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_W_INDEX[] = {
+	 { "DAC_W_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_RD[] = {
+	 { "VSYNC_SEL_R", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH8_DATA[] = {
+	 { "GRPH_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH8_IDX[] = {
+	 { "GRPH_IDX", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_RD[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD3VGA_CONTROL[] = {
+	 { "D3VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D3VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D3VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D3VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D3VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD4VGA_CONTROL[] = {
+	 { "D4VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D4VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D4VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D4VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D4VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD5VGA_CONTROL[] = {
+	 { "D5VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D5VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D5VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D5VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D5VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD6VGA_CONTROL[] = {
+	 { "D6VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D6VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D6VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D6VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D6VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SOURCE_SELECT[] = {
+	 { "VGA_SOURCE_SEL_A", 0, 2, &umr_bitfield_default },
+	 { "VGA_SOURCE_SEL_B", 8, 10, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/dce112_regs.i b/src/lib/ip/dce112_regs.i
new file mode 100644
index 0000000..f1e22ae
--- /dev/null
+++ b/src/lib/ip/dce112_regs.i
@@ -0,0 +1,9969 @@
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID", REG_SMC, 0x0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG", REG_SMC, 0x0, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PIN_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG", REG_SMC, 0x0, &ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL0", REG_SMC, 0x0, &ixAZALIA_INPUT_CRC0_CHANNEL0[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL0)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL0[0]), 0, 0 },
+	{ "ixAZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0, &ixAZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL0", REG_SMC, 0x0, &ixAZALIA_CRC0_CHANNEL0[0], sizeof(ixAZALIA_CRC0_CHANNEL0)/sizeof(ixAZALIA_CRC0_CHANNEL0[0]), 0, 0 },
+	{ "mmGLOBAL_CAPABILITIES", REG_MMIO, 0x0, &mmGLOBAL_CAPABILITIES[0], sizeof(mmGLOBAL_CAPABILITIES)/sizeof(mmGLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "ixDCIO_DEBUG_ID", REG_SMC, 0x0, &ixDCIO_DEBUG_ID[0], sizeof(ixDCIO_DEBUG_ID)/sizeof(ixDCIO_DEBUG_ID[0]), 0, 0 },
+	{ "ixFMT_DEBUG_ID", REG_SMC, 0x0, &ixFMT_DEBUG_ID[0], sizeof(ixFMT_DEBUG_ID)/sizeof(ixFMT_DEBUG_ID[0]), 0, 0 },
+	{ "ixATTR00", REG_SMC, 0x0, &ixATTR00[0], sizeof(ixATTR00)/sizeof(ixATTR00[0]), 0, 0 },
+	{ "ixSEQ00", REG_SMC, 0x0, &ixSEQ00[0], sizeof(ixSEQ00)/sizeof(ixSEQ00[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x1, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x1, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID", REG_SMC, 0x1, &ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0]), 0, 0 },
+	{ "ixAZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x1, &ixAZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL1", REG_SMC, 0x1, &ixAZALIA_INPUT_CRC0_CHANNEL1[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL1)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL1[0]), 0, 0 },
+	{ "mmOUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x1, &mmOUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmOUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmOUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmINPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x1, &mmINPUT_PAYLOAD_CAPABILITY[0], sizeof(mmINPUT_PAYLOAD_CAPABILITY)/sizeof(mmINPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL1", REG_SMC, 0x1, &ixAZALIA_CRC0_CHANNEL1[0], sizeof(ixAZALIA_CRC0_CHANNEL1)/sizeof(ixAZALIA_CRC0_CHANNEL1[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR0", REG_SMC, 0x1, &ixAUDIO_DESCRIPTOR0[0], sizeof(ixAUDIO_DESCRIPTOR0)/sizeof(ixAUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1", REG_SMC, 0x1, &ixDCIO_DEBUG1[0], sizeof(ixDCIO_DEBUG1)/sizeof(ixDCIO_DEBUG1[0]), 0, 0 },
+	{ "ixFMT_DEBUG0", REG_SMC, 0x1, &ixFMT_DEBUG0[0], sizeof(ixFMT_DEBUG0)/sizeof(ixFMT_DEBUG0[0]), 0, 0 },
+	{ "ixATTR01", REG_SMC, 0x1, &ixATTR01[0], sizeof(ixATTR01)/sizeof(ixATTR01[0]), 0, 0 },
+	{ "ixSEQ01", REG_SMC, 0x1, &ixSEQ01[0], sizeof(ixSEQ01)/sizeof(ixSEQ01[0]), 0, 0 },
+	{ "mmCORB_LOWER_BASE_ADDRESS", REG_MMIO, 0x10, &mmCORB_LOWER_BASE_ADDRESS[0], sizeof(mmCORB_LOWER_BASE_ADDRESS)/sizeof(mmCORB_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION11", REG_SMC, 0x10, &ixSINK_DESCRIPTION11[0], sizeof(ixSINK_DESCRIPTION11)/sizeof(ixSINK_DESCRIPTION11[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_A", REG_SMC, 0x10, &ixDP_AUX_DEBUG_A[0], sizeof(ixDP_AUX_DEBUG_A)/sizeof(ixDP_AUX_DEBUG_A[0]), 0, 0 },
+	{ "ixDCIO_DEBUG10", REG_SMC, 0x10, &ixDCIO_DEBUG10[0], sizeof(ixDCIO_DEBUG10)/sizeof(ixDCIO_DEBUG10[0]), 0, 0 },
+	{ "ixATTR10", REG_SMC, 0x10, &ixATTR10[0], sizeof(ixATTR10)/sizeof(ixATTR10[0]), 0, 0 },
+	{ "ixCRT10", REG_SMC, 0x10, &ixCRT10[0], sizeof(ixCRT10)/sizeof(ixCRT10[0]), 0, 0 },
+	{ "mmPHYPLLA_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x100, &mmPHYPLLA_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLA_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLA_PIXCLK_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPHYPLLB_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x101, &mmPHYPLLB_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLB_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLB_PIXCLK_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPHYPLLC_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x102, &mmPHYPLLC_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLC_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLC_PIXCLK_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPHYPLLD_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x103, &mmPHYPLLD_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLD_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLD_PIXCLK_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmDPREFCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x108, &mmDPREFCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDPREFCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDPREFCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmREFCLK_CNTL", REG_MMIO, 0x109, &mmREFCLK_CNTL[0], sizeof(mmREFCLK_CNTL)/sizeof(mmREFCLK_CNTL[0]), 0, 0 },
+	{ "mmREFCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x10b, &mmREFCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmREFCLK_CGTT_BLK_CTRL_REG)/sizeof(mmREFCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmPHYPLLE_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x10c, &mmPHYPLLE_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLE_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLE_PIXCLK_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmDPDBG_CLK_FORCE_CONTROL", REG_MMIO, 0x10d, &mmDPDBG_CLK_FORCE_CONTROL[0], sizeof(mmDPDBG_CLK_FORCE_CONTROL)/sizeof(mmDPDBG_CLK_FORCE_CONTROL[0]), 0, 0 },
+	{ "mmDCCG_PERFMON_CNTL2", REG_MMIO, 0x10e, &mmDCCG_PERFMON_CNTL2[0], sizeof(mmDCCG_PERFMON_CNTL2)/sizeof(mmDCCG_PERFMON_CNTL2[0]), 0, 0 },
+	{ "mmCORB_UPPER_BASE_ADDRESS", REG_MMIO, 0x11, &mmCORB_UPPER_BASE_ADDRESS[0], sizeof(mmCORB_UPPER_BASE_ADDRESS)/sizeof(mmCORB_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION12", REG_SMC, 0x11, &ixSINK_DESCRIPTION12[0], sizeof(ixSINK_DESCRIPTION12)/sizeof(ixSINK_DESCRIPTION12[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_B", REG_SMC, 0x11, &ixDP_AUX_DEBUG_B[0], sizeof(ixDP_AUX_DEBUG_B)/sizeof(ixDP_AUX_DEBUG_B[0]), 0, 0 },
+	{ "ixDCIO_DEBUG11", REG_SMC, 0x11, &ixDCIO_DEBUG11[0], sizeof(ixDCIO_DEBUG11)/sizeof(ixDCIO_DEBUG11[0]), 0, 0 },
+	{ "ixATTR11", REG_SMC, 0x11, &ixATTR11[0], sizeof(ixATTR11)/sizeof(ixATTR11[0]), 0, 0 },
+	{ "ixCRT11", REG_SMC, 0x11, &ixCRT11[0], sizeof(ixCRT11)/sizeof(ixCRT11[0]), 0, 0 },
+	{ "mmDCCG_CBUS_WRCMD_DELAY", REG_MMIO, 0x110, &mmDCCG_CBUS_WRCMD_DELAY[0], sizeof(mmDCCG_CBUS_WRCMD_DELAY)/sizeof(mmDCCG_CBUS_WRCMD_DELAY[0]), 0, 0 },
+	{ "mmDCCG_DS_DEBUG_CNTL", REG_MMIO, 0x112, &mmDCCG_DS_DEBUG_CNTL[0], sizeof(mmDCCG_DS_DEBUG_CNTL)/sizeof(mmDCCG_DS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DS_DTO_INCR", REG_MMIO, 0x113, &mmDCCG_DS_DTO_INCR[0], sizeof(mmDCCG_DS_DTO_INCR)/sizeof(mmDCCG_DS_DTO_INCR[0]), 0, 0 },
+	{ "mmDCCG_DS_DTO_MODULO", REG_MMIO, 0x114, &mmDCCG_DS_DTO_MODULO[0], sizeof(mmDCCG_DS_DTO_MODULO)/sizeof(mmDCCG_DS_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_DS_CNTL", REG_MMIO, 0x115, &mmDCCG_DS_CNTL[0], sizeof(mmDCCG_DS_CNTL)/sizeof(mmDCCG_DS_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DS_HW_CAL_INTERVAL", REG_MMIO, 0x116, &mmDCCG_DS_HW_CAL_INTERVAL[0], sizeof(mmDCCG_DS_HW_CAL_INTERVAL)/sizeof(mmDCCG_DS_HW_CAL_INTERVAL[0]), 0, 0 },
+	{ "mmDPREFCLK_CNTL", REG_MMIO, 0x118, &mmDPREFCLK_CNTL[0], sizeof(mmDPREFCLK_CNTL)/sizeof(mmDPREFCLK_CNTL[0]), 0, 0 },
+	{ "mmDCE_VERSION", REG_MMIO, 0x11e, &mmDCE_VERSION[0], sizeof(mmDCE_VERSION)/sizeof(mmDCE_VERSION[0]), 0, 0 },
+	{ "mmVGA_MEM_WRITE_PAGE_ADDR", REG_MMIO, 0x12, &mmVGA_MEM_WRITE_PAGE_ADDR[0], sizeof(mmVGA_MEM_WRITE_PAGE_ADDR)/sizeof(mmVGA_MEM_WRITE_PAGE_ADDR[0]), 0, 0 },
+	{ "mmCORB_WRITE_POINTER", REG_MMIO, 0x12, &mmCORB_WRITE_POINTER[0], sizeof(mmCORB_WRITE_POINTER)/sizeof(mmCORB_WRITE_POINTER[0]), 0, 0 },
+	{ "mmCORB_READ_POINTER", REG_MMIO, 0x12, &mmCORB_READ_POINTER[0], sizeof(mmCORB_READ_POINTER)/sizeof(mmCORB_READ_POINTER[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_C", REG_SMC, 0x12, &ixDP_AUX_DEBUG_C[0], sizeof(ixDP_AUX_DEBUG_C)/sizeof(ixDP_AUX_DEBUG_C[0]), 0, 0 },
+	{ "ixDCIO_DEBUG12", REG_SMC, 0x12, &ixDCIO_DEBUG12[0], sizeof(ixDCIO_DEBUG12)/sizeof(ixDCIO_DEBUG12[0]), 0, 0 },
+	{ "ixATTR12", REG_SMC, 0x12, &ixATTR12[0], sizeof(ixATTR12)/sizeof(ixATTR12[0]), 0, 0 },
+	{ "ixCRT12", REG_SMC, 0x12, &ixCRT12[0], sizeof(ixCRT12)/sizeof(ixCRT12[0]), 0, 0 },
+	{ "mmDCCG_GTC_CNTL", REG_MMIO, 0x120, &mmDCCG_GTC_CNTL[0], sizeof(mmDCCG_GTC_CNTL)/sizeof(mmDCCG_GTC_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_INCR", REG_MMIO, 0x121, &mmDCCG_GTC_DTO_INCR[0], sizeof(mmDCCG_GTC_DTO_INCR)/sizeof(mmDCCG_GTC_DTO_INCR[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_MODULO", REG_MMIO, 0x122, &mmDCCG_GTC_DTO_MODULO[0], sizeof(mmDCCG_GTC_DTO_MODULO)/sizeof(mmDCCG_GTC_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_GTC_CURRENT", REG_MMIO, 0x123, &mmDCCG_GTC_CURRENT[0], sizeof(mmDCCG_GTC_CURRENT)/sizeof(mmDCCG_GTC_CURRENT[0]), 0, 0 },
+	{ "mmDENTIST_DISPCLK_CNTL", REG_MMIO, 0x124, &mmDENTIST_DISPCLK_CNTL[0], sizeof(mmDENTIST_DISPCLK_CNTL)/sizeof(mmDENTIST_DISPCLK_CNTL[0]), 0, 0 },
+	{ "mmDAC_CLK_ENABLE", REG_MMIO, 0x128, &mmDAC_CLK_ENABLE[0], sizeof(mmDAC_CLK_ENABLE)/sizeof(mmDAC_CLK_ENABLE[0]), 0, 0 },
+	{ "mmDVO_CLK_ENABLE", REG_MMIO, 0x129, &mmDVO_CLK_ENABLE[0], sizeof(mmDVO_CLK_ENABLE)/sizeof(mmDVO_CLK_ENABLE[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_WRITE", REG_MMIO, 0x12a, &mmAVSYNC_COUNTER_WRITE[0], sizeof(mmAVSYNC_COUNTER_WRITE)/sizeof(mmAVSYNC_COUNTER_WRITE[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_CONTROL", REG_MMIO, 0x12b, &mmAVSYNC_COUNTER_CONTROL[0], sizeof(mmAVSYNC_COUNTER_CONTROL)/sizeof(mmAVSYNC_COUNTER_CONTROL[0]), 0, 0 },
+	{ "mmDMCU_SMU_INTERRUPT_CNTL", REG_MMIO, 0x12c, &mmDMCU_SMU_INTERRUPT_CNTL[0], sizeof(mmDMCU_SMU_INTERRUPT_CNTL)/sizeof(mmDMCU_SMU_INTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmSMU_CONTROL", REG_MMIO, 0x12d, &mmSMU_CONTROL[0], sizeof(mmSMU_CONTROL)/sizeof(mmSMU_CONTROL[0]), 0, 0 },
+	{ "mmSMU_INTERRUPT_CONTROL", REG_MMIO, 0x12e, &mmSMU_INTERRUPT_CONTROL[0], sizeof(mmSMU_INTERRUPT_CONTROL)/sizeof(mmSMU_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmAVSYNC_COUNTER_READ", REG_MMIO, 0x12f, &mmAVSYNC_COUNTER_READ[0], sizeof(mmAVSYNC_COUNTER_READ)/sizeof(mmAVSYNC_COUNTER_READ[0]), 0, 0 },
+	{ "mmVGA_MEM_READ_PAGE_ADDR", REG_MMIO, 0x13, &mmVGA_MEM_READ_PAGE_ADDR[0], sizeof(mmVGA_MEM_READ_PAGE_ADDR)/sizeof(mmVGA_MEM_READ_PAGE_ADDR[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION14", REG_SMC, 0x13, &ixSINK_DESCRIPTION14[0], sizeof(ixSINK_DESCRIPTION14)/sizeof(ixSINK_DESCRIPTION14[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_D", REG_SMC, 0x13, &ixDP_AUX_DEBUG_D[0], sizeof(ixDP_AUX_DEBUG_D)/sizeof(ixDP_AUX_DEBUG_D[0]), 0, 0 },
+	{ "ixDCIO_DEBUG13", REG_SMC, 0x13, &ixDCIO_DEBUG13[0], sizeof(ixDCIO_DEBUG13)/sizeof(ixDCIO_DEBUG13[0]), 0, 0 },
+	{ "mmCORB_STATUS", REG_MMIO, 0x13, &mmCORB_STATUS[0], sizeof(mmCORB_STATUS)/sizeof(mmCORB_STATUS[0]), 0, 0 },
+	{ "mmCORB_SIZE", REG_MMIO, 0x13, &mmCORB_SIZE[0], sizeof(mmCORB_SIZE)/sizeof(mmCORB_SIZE[0]), 0, 0 },
+	{ "ixATTR13", REG_SMC, 0x13, &ixATTR13[0], sizeof(ixATTR13)/sizeof(ixATTR13[0]), 0, 0 },
+	{ "ixCRT13", REG_SMC, 0x13, &ixCRT13[0], sizeof(ixCRT13)/sizeof(ixCRT13[0]), 0, 0 },
+	{ "mmMILLISECOND_TIME_BASE_DIV", REG_MMIO, 0x130, &mmMILLISECOND_TIME_BASE_DIV[0], sizeof(mmMILLISECOND_TIME_BASE_DIV)/sizeof(mmMILLISECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDISPCLK_FREQ_CHANGE_CNTL", REG_MMIO, 0x131, &mmDISPCLK_FREQ_CHANGE_CNTL[0], sizeof(mmDISPCLK_FREQ_CHANGE_CNTL)/sizeof(mmDISPCLK_FREQ_CHANGE_CNTL[0]), 0, 0 },
+	{ "mmDC_MEM_GLOBAL_PWR_REQ_CNTL", REG_MMIO, 0x132, &mmDC_MEM_GLOBAL_PWR_REQ_CNTL[0], sizeof(mmDC_MEM_GLOBAL_PWR_REQ_CNTL)/sizeof(mmDC_MEM_GLOBAL_PWR_REQ_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PERFMON_CNTL", REG_MMIO, 0x133, &mmDCCG_PERFMON_CNTL[0], sizeof(mmDCCG_PERFMON_CNTL)/sizeof(mmDCCG_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GATE_DISABLE_CNTL", REG_MMIO, 0x134, &mmDCCG_GATE_DISABLE_CNTL[0], sizeof(mmDCCG_GATE_DISABLE_CNTL)/sizeof(mmDCCG_GATE_DISABLE_CNTL[0]), 0, 0 },
+	{ "mmDISPCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x135, &mmDISPCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmSCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x136, &mmSCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmDCCG_CAC_STATUS", REG_MMIO, 0x137, &mmDCCG_CAC_STATUS[0], sizeof(mmDCCG_CAC_STATUS)/sizeof(mmDCCG_CAC_STATUS[0]), 0, 0 },
+	{ "mmPIXCLK0_RESYNC_CNTL", REG_MMIO, 0x13a, &mmPIXCLK0_RESYNC_CNTL[0], sizeof(mmPIXCLK0_RESYNC_CNTL)/sizeof(mmPIXCLK0_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmMICROSECOND_TIME_BASE_DIV", REG_MMIO, 0x13b, &mmMICROSECOND_TIME_BASE_DIV[0], sizeof(mmMICROSECOND_TIME_BASE_DIV)/sizeof(mmMICROSECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDCCG_GATE_DISABLE_CNTL2", REG_MMIO, 0x13c, &mmDCCG_GATE_DISABLE_CNTL2[0], sizeof(mmDCCG_GATE_DISABLE_CNTL2)/sizeof(mmDCCG_GATE_DISABLE_CNTL2[0]), 0, 0 },
+	{ "mmSYMCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x13d, &mmSYMCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSYMCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSYMCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmPHYPLLF_PIXCLK_RESYNC_CNTL", REG_MMIO, 0x13e, &mmPHYPLLF_PIXCLK_RESYNC_CNTL[0], sizeof(mmPHYPLLF_PIXCLK_RESYNC_CNTL)/sizeof(mmPHYPLLF_PIXCLK_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DISP_CNTL_REG", REG_MMIO, 0x13f, &mmDCCG_DISP_CNTL_REG[0], sizeof(mmDCCG_DISP_CNTL_REG)/sizeof(mmDCCG_DISP_CNTL_REG[0]), 0, 0 },
+	{ "mmRIRB_LOWER_BASE_ADDRESS", REG_MMIO, 0x14, &mmRIRB_LOWER_BASE_ADDRESS[0], sizeof(mmRIRB_LOWER_BASE_ADDRESS)/sizeof(mmRIRB_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION15", REG_SMC, 0x14, &ixSINK_DESCRIPTION15[0], sizeof(ixSINK_DESCRIPTION15)/sizeof(ixSINK_DESCRIPTION15[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_E", REG_SMC, 0x14, &ixDP_AUX_DEBUG_E[0], sizeof(ixDP_AUX_DEBUG_E)/sizeof(ixDP_AUX_DEBUG_E[0]), 0, 0 },
+	{ "ixDCIO_DEBUG14", REG_SMC, 0x14, &ixDCIO_DEBUG14[0], sizeof(ixDCIO_DEBUG14)/sizeof(ixDCIO_DEBUG14[0]), 0, 0 },
+	{ "ixATTR14", REG_SMC, 0x14, &ixATTR14[0], sizeof(ixATTR14)/sizeof(ixATTR14[0]), 0, 0 },
+	{ "ixCRT14", REG_SMC, 0x14, &ixCRT14[0], sizeof(ixCRT14)/sizeof(ixCRT14[0]), 0, 0 },
+	{ "mmCRTC0_PIXEL_RATE_CNTL", REG_MMIO, 0x140, &mmCRTC0_PIXEL_RATE_CNTL[0], sizeof(mmCRTC0_PIXEL_RATE_CNTL)/sizeof(mmCRTC0_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO0_PHASE", REG_MMIO, 0x141, &mmDP_DTO0_PHASE[0], sizeof(mmDP_DTO0_PHASE)/sizeof(mmDP_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO0_MODULO", REG_MMIO, 0x142, &mmDP_DTO0_MODULO[0], sizeof(mmDP_DTO0_MODULO)/sizeof(mmDP_DTO0_MODULO[0]), 0, 0 },
+	{ "mmCRTC0_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x143, &mmCRTC0_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmCRTC0_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmCRTC0_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmCRTC1_PIXEL_RATE_CNTL", REG_MMIO, 0x144, &mmCRTC1_PIXEL_RATE_CNTL[0], sizeof(mmCRTC1_PIXEL_RATE_CNTL)/sizeof(mmCRTC1_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO1_PHASE", REG_MMIO, 0x145, &mmDP_DTO1_PHASE[0], sizeof(mmDP_DTO1_PHASE)/sizeof(mmDP_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO1_MODULO", REG_MMIO, 0x146, &mmDP_DTO1_MODULO[0], sizeof(mmDP_DTO1_MODULO)/sizeof(mmDP_DTO1_MODULO[0]), 0, 0 },
+	{ "mmCRTC1_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x147, &mmCRTC1_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmCRTC1_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmCRTC1_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmCRTC2_PIXEL_RATE_CNTL", REG_MMIO, 0x148, &mmCRTC2_PIXEL_RATE_CNTL[0], sizeof(mmCRTC2_PIXEL_RATE_CNTL)/sizeof(mmCRTC2_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO2_PHASE", REG_MMIO, 0x149, &mmDP_DTO2_PHASE[0], sizeof(mmDP_DTO2_PHASE)/sizeof(mmDP_DTO2_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO2_MODULO", REG_MMIO, 0x14a, &mmDP_DTO2_MODULO[0], sizeof(mmDP_DTO2_MODULO)/sizeof(mmDP_DTO2_MODULO[0]), 0, 0 },
+	{ "mmCRTC2_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x14b, &mmCRTC2_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmCRTC2_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmCRTC2_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmCRTC3_PIXEL_RATE_CNTL", REG_MMIO, 0x14c, &mmCRTC3_PIXEL_RATE_CNTL[0], sizeof(mmCRTC3_PIXEL_RATE_CNTL)/sizeof(mmCRTC3_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO3_PHASE", REG_MMIO, 0x14d, &mmDP_DTO3_PHASE[0], sizeof(mmDP_DTO3_PHASE)/sizeof(mmDP_DTO3_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO3_MODULO", REG_MMIO, 0x14e, &mmDP_DTO3_MODULO[0], sizeof(mmDP_DTO3_MODULO)/sizeof(mmDP_DTO3_MODULO[0]), 0, 0 },
+	{ "mmCRTC3_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x14f, &mmCRTC3_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmCRTC3_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmCRTC3_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmRIRB_UPPER_BASE_ADDRESS", REG_MMIO, 0x15, &mmRIRB_UPPER_BASE_ADDRESS[0], sizeof(mmRIRB_UPPER_BASE_ADDRESS)/sizeof(mmRIRB_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION16", REG_SMC, 0x15, &ixSINK_DESCRIPTION16[0], sizeof(ixSINK_DESCRIPTION16)/sizeof(ixSINK_DESCRIPTION16[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_F", REG_SMC, 0x15, &ixDP_AUX_DEBUG_F[0], sizeof(ixDP_AUX_DEBUG_F)/sizeof(ixDP_AUX_DEBUG_F[0]), 0, 0 },
+	{ "ixDCIO_DEBUG15", REG_SMC, 0x15, &ixDCIO_DEBUG15[0], sizeof(ixDCIO_DEBUG15)/sizeof(ixDCIO_DEBUG15[0]), 0, 0 },
+	{ "ixCRT15", REG_SMC, 0x15, &ixCRT15[0], sizeof(ixCRT15)/sizeof(ixCRT15[0]), 0, 0 },
+	{ "mmCRTC4_PIXEL_RATE_CNTL", REG_MMIO, 0x150, &mmCRTC4_PIXEL_RATE_CNTL[0], sizeof(mmCRTC4_PIXEL_RATE_CNTL)/sizeof(mmCRTC4_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO4_PHASE", REG_MMIO, 0x151, &mmDP_DTO4_PHASE[0], sizeof(mmDP_DTO4_PHASE)/sizeof(mmDP_DTO4_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO4_MODULO", REG_MMIO, 0x152, &mmDP_DTO4_MODULO[0], sizeof(mmDP_DTO4_MODULO)/sizeof(mmDP_DTO4_MODULO[0]), 0, 0 },
+	{ "mmCRTC4_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x153, &mmCRTC4_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmCRTC4_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmCRTC4_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmCRTC5_PIXEL_RATE_CNTL", REG_MMIO, 0x154, &mmCRTC5_PIXEL_RATE_CNTL[0], sizeof(mmCRTC5_PIXEL_RATE_CNTL)/sizeof(mmCRTC5_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO5_PHASE", REG_MMIO, 0x155, &mmDP_DTO5_PHASE[0], sizeof(mmDP_DTO5_PHASE)/sizeof(mmDP_DTO5_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO5_MODULO", REG_MMIO, 0x156, &mmDP_DTO5_MODULO[0], sizeof(mmDP_DTO5_MODULO)/sizeof(mmDP_DTO5_MODULO[0]), 0, 0 },
+	{ "mmCRTC5_PHYPLL_PIXEL_RATE_CNTL", REG_MMIO, 0x157, &mmCRTC5_PHYPLL_PIXEL_RATE_CNTL[0], sizeof(mmCRTC5_PHYPLL_PIXEL_RATE_CNTL)/sizeof(mmCRTC5_PHYPLL_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDCCG_CBUS_ANTIGLITCH_RESETB", REG_MMIO, 0x15c, &mmDCCG_CBUS_ANTIGLITCH_RESETB[0], sizeof(mmDCCG_CBUS_ANTIGLITCH_RESETB)/sizeof(mmDCCG_CBUS_ANTIGLITCH_RESETB[0]), 0, 0 },
+	{ "mmDCCG_CBUS_SPARE", REG_MMIO, 0x15d, &mmDCCG_CBUS_SPARE[0], sizeof(mmDCCG_CBUS_SPARE)/sizeof(mmDCCG_CBUS_SPARE[0]), 0, 0 },
+	{ "mmDCCG_SOFT_RESET", REG_MMIO, 0x15f, &mmDCCG_SOFT_RESET[0], sizeof(mmDCCG_SOFT_RESET)/sizeof(mmDCCG_SOFT_RESET[0]), 0, 0 },
+	{ "mmRESPONSE_INTERRUPT_COUNT", REG_MMIO, 0x16, &mmRESPONSE_INTERRUPT_COUNT[0], sizeof(mmRESPONSE_INTERRUPT_COUNT)/sizeof(mmRESPONSE_INTERRUPT_COUNT[0]), 0, 0 },
+	{ "mmRIRB_WRITE_POINTER", REG_MMIO, 0x16, &mmRIRB_WRITE_POINTER[0], sizeof(mmRIRB_WRITE_POINTER)/sizeof(mmRIRB_WRITE_POINTER[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_G", REG_SMC, 0x16, &ixDP_AUX_DEBUG_G[0], sizeof(ixDP_AUX_DEBUG_G)/sizeof(ixDP_AUX_DEBUG_G[0]), 0, 0 },
+	{ "ixDCIO_DEBUG16", REG_SMC, 0x16, &ixDCIO_DEBUG16[0], sizeof(ixDCIO_DEBUG16)/sizeof(ixDCIO_DEBUG16[0]), 0, 0 },
+	{ "ixCRT16", REG_SMC, 0x16, &ixCRT16[0], sizeof(ixCRT16)/sizeof(ixCRT16[0]), 0, 0 },
+	{ "mmSYMCLKA_CLOCK_ENABLE", REG_MMIO, 0x160, &mmSYMCLKA_CLOCK_ENABLE[0], sizeof(mmSYMCLKA_CLOCK_ENABLE)/sizeof(mmSYMCLKA_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_CTRL", REG_MMIO, 0x1600, &mmDMCU_CTRL[0], sizeof(mmDMCU_CTRL)/sizeof(mmDMCU_CTRL[0]), 0, 0 },
+	{ "mmDMCU_STATUS", REG_MMIO, 0x1601, &mmDMCU_STATUS[0], sizeof(mmDMCU_STATUS)/sizeof(mmDMCU_STATUS[0]), 0, 0 },
+	{ "mmDMCU_PC_START_ADDR", REG_MMIO, 0x1602, &mmDMCU_PC_START_ADDR[0], sizeof(mmDMCU_PC_START_ADDR)/sizeof(mmDMCU_PC_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_START_ADDR", REG_MMIO, 0x1603, &mmDMCU_FW_START_ADDR[0], sizeof(mmDMCU_FW_START_ADDR)/sizeof(mmDMCU_FW_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_END_ADDR", REG_MMIO, 0x1604, &mmDMCU_FW_END_ADDR[0], sizeof(mmDMCU_FW_END_ADDR)/sizeof(mmDMCU_FW_END_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_ISR_START_ADDR", REG_MMIO, 0x1605, &mmDMCU_FW_ISR_START_ADDR[0], sizeof(mmDMCU_FW_ISR_START_ADDR)/sizeof(mmDMCU_FW_ISR_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_HI", REG_MMIO, 0x1606, &mmDMCU_FW_CS_HI[0], sizeof(mmDMCU_FW_CS_HI)/sizeof(mmDMCU_FW_CS_HI[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_LO", REG_MMIO, 0x1607, &mmDMCU_FW_CS_LO[0], sizeof(mmDMCU_FW_CS_LO)/sizeof(mmDMCU_FW_CS_LO[0]), 0, 0 },
+	{ "mmDMCU_RAM_ACCESS_CTRL", REG_MMIO, 0x1608, &mmDMCU_RAM_ACCESS_CTRL[0], sizeof(mmDMCU_RAM_ACCESS_CTRL)/sizeof(mmDMCU_RAM_ACCESS_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_CTRL", REG_MMIO, 0x1609, &mmDMCU_ERAM_WR_CTRL[0], sizeof(mmDMCU_ERAM_WR_CTRL)/sizeof(mmDMCU_ERAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_DATA", REG_MMIO, 0x160a, &mmDMCU_ERAM_WR_DATA[0], sizeof(mmDMCU_ERAM_WR_DATA)/sizeof(mmDMCU_ERAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_CTRL", REG_MMIO, 0x160b, &mmDMCU_ERAM_RD_CTRL[0], sizeof(mmDMCU_ERAM_RD_CTRL)/sizeof(mmDMCU_ERAM_RD_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_DATA", REG_MMIO, 0x160c, &mmDMCU_ERAM_RD_DATA[0], sizeof(mmDMCU_ERAM_RD_DATA)/sizeof(mmDMCU_ERAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_CTRL", REG_MMIO, 0x160d, &mmDMCU_IRAM_WR_CTRL[0], sizeof(mmDMCU_IRAM_WR_CTRL)/sizeof(mmDMCU_IRAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_DATA", REG_MMIO, 0x160e, &mmDMCU_IRAM_WR_DATA[0], sizeof(mmDMCU_IRAM_WR_DATA)/sizeof(mmDMCU_IRAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_CTRL", REG_MMIO, 0x160f, &mmDMCU_IRAM_RD_CTRL[0], sizeof(mmDMCU_IRAM_RD_CTRL)/sizeof(mmDMCU_IRAM_RD_CTRL[0]), 0, 0 },
+	{ "mmSYMCLKB_CLOCK_ENABLE", REG_MMIO, 0x161, &mmSYMCLKB_CLOCK_ENABLE[0], sizeof(mmSYMCLKB_CLOCK_ENABLE)/sizeof(mmSYMCLKB_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_DATA", REG_MMIO, 0x1610, &mmDMCU_IRAM_RD_DATA[0], sizeof(mmDMCU_IRAM_RD_DATA)/sizeof(mmDMCU_IRAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_EVENT_TRIGGER", REG_MMIO, 0x1611, &mmDMCU_EVENT_TRIGGER[0], sizeof(mmDMCU_EVENT_TRIGGER)/sizeof(mmDMCU_EVENT_TRIGGER[0]), 0, 0 },
+	{ "mmDMCU_UC_INTERNAL_INT_STATUS", REG_MMIO, 0x1612, &mmDMCU_UC_INTERNAL_INT_STATUS[0], sizeof(mmDMCU_UC_INTERNAL_INT_STATUS)/sizeof(mmDMCU_UC_INTERNAL_INT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_SS_INTERRUPT_CNTL_STATUS", REG_MMIO, 0x1613, &mmDMCU_SS_INTERRUPT_CNTL_STATUS[0], sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS)/sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_STATUS", REG_MMIO, 0x1614, &mmDMCU_INTERRUPT_STATUS[0], sizeof(mmDMCU_INTERRUPT_STATUS)/sizeof(mmDMCU_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_HOST_EN_MASK", REG_MMIO, 0x1615, &mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_EN_MASK", REG_MMIO, 0x1616, &mmDMCU_INTERRUPT_TO_UC_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL", REG_MMIO, 0x1617, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0]), 0, 0 },
+	{ "mmDC_DMCU_SCRATCH", REG_MMIO, 0x1618, &mmDC_DMCU_SCRATCH[0], sizeof(mmDC_DMCU_SCRATCH)/sizeof(mmDC_DMCU_SCRATCH[0]), 0, 0 },
+	{ "mmDMCU_INT_CNT", REG_MMIO, 0x1619, &mmDMCU_INT_CNT[0], sizeof(mmDMCU_INT_CNT)/sizeof(mmDMCU_INT_CNT[0]), 0, 0 },
+	{ "mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS", REG_MMIO, 0x161a, &mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0], sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS)/sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0]), 0, 0 },
+	{ "mmDMCU_UC_CLK_GATING_CNTL", REG_MMIO, 0x161b, &mmDMCU_UC_CLK_GATING_CNTL[0], sizeof(mmDMCU_UC_CLK_GATING_CNTL)/sizeof(mmDMCU_UC_CLK_GATING_CNTL[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG1", REG_MMIO, 0x161c, &mmMASTER_COMM_DATA_REG1[0], sizeof(mmMASTER_COMM_DATA_REG1)/sizeof(mmMASTER_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG2", REG_MMIO, 0x161d, &mmMASTER_COMM_DATA_REG2[0], sizeof(mmMASTER_COMM_DATA_REG2)/sizeof(mmMASTER_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG3", REG_MMIO, 0x161e, &mmMASTER_COMM_DATA_REG3[0], sizeof(mmMASTER_COMM_DATA_REG3)/sizeof(mmMASTER_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmMASTER_COMM_CMD_REG", REG_MMIO, 0x161f, &mmMASTER_COMM_CMD_REG[0], sizeof(mmMASTER_COMM_CMD_REG)/sizeof(mmMASTER_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSYMCLKC_CLOCK_ENABLE", REG_MMIO, 0x162, &mmSYMCLKC_CLOCK_ENABLE[0], sizeof(mmSYMCLKC_CLOCK_ENABLE)/sizeof(mmSYMCLKC_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmMASTER_COMM_CNTL_REG", REG_MMIO, 0x1620, &mmMASTER_COMM_CNTL_REG[0], sizeof(mmMASTER_COMM_CNTL_REG)/sizeof(mmMASTER_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG1", REG_MMIO, 0x1621, &mmSLAVE_COMM_DATA_REG1[0], sizeof(mmSLAVE_COMM_DATA_REG1)/sizeof(mmSLAVE_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG2", REG_MMIO, 0x1622, &mmSLAVE_COMM_DATA_REG2[0], sizeof(mmSLAVE_COMM_DATA_REG2)/sizeof(mmSLAVE_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG3", REG_MMIO, 0x1623, &mmSLAVE_COMM_DATA_REG3[0], sizeof(mmSLAVE_COMM_DATA_REG3)/sizeof(mmSLAVE_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CMD_REG", REG_MMIO, 0x1624, &mmSLAVE_COMM_CMD_REG[0], sizeof(mmSLAVE_COMM_CMD_REG)/sizeof(mmSLAVE_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CNTL_REG", REG_MMIO, 0x1625, &mmSLAVE_COMM_CNTL_REG[0], sizeof(mmSLAVE_COMM_CNTL_REG)/sizeof(mmSLAVE_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_INDEX", REG_MMIO, 0x1626, &mmDMCU_TEST_DEBUG_INDEX[0], sizeof(mmDMCU_TEST_DEBUG_INDEX)/sizeof(mmDMCU_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_DATA", REG_MMIO, 0x1627, &mmDMCU_TEST_DEBUG_DATA[0], sizeof(mmDMCU_TEST_DEBUG_DATA)/sizeof(mmDMCU_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBL1_PWM_AMBIENT_LIGHT_LEVEL", REG_MMIO, 0x1628, &mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0], sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL)/sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_USER_LEVEL", REG_MMIO, 0x1629, &mmBL1_PWM_USER_LEVEL[0], sizeof(mmBL1_PWM_USER_LEVEL)/sizeof(mmBL1_PWM_USER_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_TARGET_ABM_LEVEL", REG_MMIO, 0x162a, &mmBL1_PWM_TARGET_ABM_LEVEL[0], sizeof(mmBL1_PWM_TARGET_ABM_LEVEL)/sizeof(mmBL1_PWM_TARGET_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_CURRENT_ABM_LEVEL", REG_MMIO, 0x162b, &mmBL1_PWM_CURRENT_ABM_LEVEL[0], sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL)/sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_FINAL_DUTY_CYCLE", REG_MMIO, 0x162c, &mmBL1_PWM_FINAL_DUTY_CYCLE[0], sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE)/sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_MINIMUM_DUTY_CYCLE", REG_MMIO, 0x162d, &mmBL1_PWM_MINIMUM_DUTY_CYCLE[0], sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE)/sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_ABM_CNTL", REG_MMIO, 0x162e, &mmBL1_PWM_ABM_CNTL[0], sizeof(mmBL1_PWM_ABM_CNTL)/sizeof(mmBL1_PWM_ABM_CNTL[0]), 0, 0 },
+	{ "mmBL1_PWM_BL_UPDATE_SAMPLE_RATE", REG_MMIO, 0x162f, &mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0], sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE)/sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmSYMCLKD_CLOCK_ENABLE", REG_MMIO, 0x163, &mmSYMCLKD_CLOCK_ENABLE[0], sizeof(mmSYMCLKD_CLOCK_ENABLE)/sizeof(mmSYMCLKD_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmBL1_PWM_GRP2_REG_LOCK", REG_MMIO, 0x1630, &mmBL1_PWM_GRP2_REG_LOCK[0], sizeof(mmBL1_PWM_GRP2_REG_LOCK)/sizeof(mmBL1_PWM_GRP2_REG_LOCK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_EN_MASK_1", REG_MMIO, 0x1631, &mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK_1)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK_1[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1", REG_MMIO, 0x1632, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_STATUS_1", REG_MMIO, 0x1633, &mmDMCU_INTERRUPT_STATUS_1[0], sizeof(mmDMCU_INTERRUPT_STATUS_1)/sizeof(mmDMCU_INTERRUPT_STATUS_1[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_STATUS1", REG_MMIO, 0x1634, &mmDMCU_DPRX_INTERRUPT_STATUS1[0], sizeof(mmDMCU_DPRX_INTERRUPT_STATUS1)/sizeof(mmDMCU_DPRX_INTERRUPT_STATUS1[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x1635, &mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x1636, &mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 },
+	{ "mmDC_ABM1_CNTL", REG_MMIO, 0x1638, &mmDC_ABM1_CNTL[0], sizeof(mmDC_ABM1_CNTL)/sizeof(mmDC_ABM1_CNTL[0]), 0, 0 },
+	{ "mmDC_ABM1_IPCSC_COEFF_SEL", REG_MMIO, 0x1639, &mmDC_ABM1_IPCSC_COEFF_SEL[0], sizeof(mmDC_ABM1_IPCSC_COEFF_SEL)/sizeof(mmDC_ABM1_IPCSC_COEFF_SEL[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_0", REG_MMIO, 0x163a, &mmDC_ABM1_ACE_OFFSET_SLOPE_0[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_1", REG_MMIO, 0x163b, &mmDC_ABM1_ACE_OFFSET_SLOPE_1[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_2", REG_MMIO, 0x163c, &mmDC_ABM1_ACE_OFFSET_SLOPE_2[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_3", REG_MMIO, 0x163d, &mmDC_ABM1_ACE_OFFSET_SLOPE_3[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_4", REG_MMIO, 0x163e, &mmDC_ABM1_ACE_OFFSET_SLOPE_4[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_12", REG_MMIO, 0x163f, &mmDC_ABM1_ACE_THRES_12[0], sizeof(mmDC_ABM1_ACE_THRES_12)/sizeof(mmDC_ABM1_ACE_THRES_12[0]), 0, 0 },
+	{ "mmSYMCLKE_CLOCK_ENABLE", REG_MMIO, 0x164, &mmSYMCLKE_CLOCK_ENABLE[0], sizeof(mmSYMCLKE_CLOCK_ENABLE)/sizeof(mmSYMCLKE_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_34", REG_MMIO, 0x1640, &mmDC_ABM1_ACE_THRES_34[0], sizeof(mmDC_ABM1_ACE_THRES_34)/sizeof(mmDC_ABM1_ACE_THRES_34[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_CNTL_MISC", REG_MMIO, 0x1641, &mmDC_ABM1_ACE_CNTL_MISC[0], sizeof(mmDC_ABM1_ACE_CNTL_MISC)/sizeof(mmDC_ABM1_ACE_CNTL_MISC[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS5", REG_MMIO, 0x1642, &mmDMCU_PERFMON_INTERRUPT_STATUS5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS5)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5", REG_MMIO, 0x1643, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS1", REG_MMIO, 0x1644, &mmDMCU_PERFMON_INTERRUPT_STATUS1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS2", REG_MMIO, 0x1645, &mmDMCU_PERFMON_INTERRUPT_STATUS2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS3", REG_MMIO, 0x1646, &mmDMCU_PERFMON_INTERRUPT_STATUS3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS4", REG_MMIO, 0x1647, &mmDMCU_PERFMON_INTERRUPT_STATUS4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4[0]), 0, 0 },
+	{ "mmDC_ABM1_DEBUG_MISC", REG_MMIO, 0x1649, &mmDC_ABM1_DEBUG_MISC[0], sizeof(mmDC_ABM1_DEBUG_MISC)/sizeof(mmDC_ABM1_DEBUG_MISC[0]), 0, 0 },
+	{ "mmDC_ABM1_HGLS_REG_READ_PROGRESS", REG_MMIO, 0x164a, &mmDC_ABM1_HGLS_REG_READ_PROGRESS[0], sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS)/sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_MISC_CTRL", REG_MMIO, 0x164b, &mmDC_ABM1_HG_MISC_CTRL[0], sizeof(mmDC_ABM1_HG_MISC_CTRL)/sizeof(mmDC_ABM1_HG_MISC_CTRL[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SUM_OF_LUMA", REG_MMIO, 0x164c, &mmDC_ABM1_LS_SUM_OF_LUMA[0], sizeof(mmDC_ABM1_LS_SUM_OF_LUMA)/sizeof(mmDC_ABM1_LS_SUM_OF_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_LUMA", REG_MMIO, 0x164d, &mmDC_ABM1_LS_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA", REG_MMIO, 0x164e, &mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_PIXEL_COUNT", REG_MMIO, 0x164f, &mmDC_ABM1_LS_PIXEL_COUNT[0], sizeof(mmDC_ABM1_LS_PIXEL_COUNT)/sizeof(mmDC_ABM1_LS_PIXEL_COUNT[0]), 0, 0 },
+	{ "mmSYMCLKF_CLOCK_ENABLE", REG_MMIO, 0x165, &mmSYMCLKF_CLOCK_ENABLE[0], sizeof(mmSYMCLKF_CLOCK_ENABLE)/sizeof(mmSYMCLKF_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_OVR_SCAN_BIN", REG_MMIO, 0x1650, &mmDC_ABM1_LS_OVR_SCAN_BIN[0], sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN)/sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES", REG_MMIO, 0x1651, &mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0], sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES)/sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT", REG_MMIO, 0x1652, &mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT", REG_MMIO, 0x1653, &mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_SAMPLE_RATE", REG_MMIO, 0x1654, &mmDC_ABM1_HG_SAMPLE_RATE[0], sizeof(mmDC_ABM1_HG_SAMPLE_RATE)/sizeof(mmDC_ABM1_HG_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SAMPLE_RATE", REG_MMIO, 0x1655, &mmDC_ABM1_LS_SAMPLE_RATE[0], sizeof(mmDC_ABM1_LS_SAMPLE_RATE)/sizeof(mmDC_ABM1_LS_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG", REG_MMIO, 0x1656, &mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0], sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG)/sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX", REG_MMIO, 0x1657, &mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX", REG_MMIO, 0x1658, &mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX", REG_MMIO, 0x1659, &mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX", REG_MMIO, 0x165a, &mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_1", REG_MMIO, 0x165b, &mmDC_ABM1_HG_RESULT_1[0], sizeof(mmDC_ABM1_HG_RESULT_1)/sizeof(mmDC_ABM1_HG_RESULT_1[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_2", REG_MMIO, 0x165c, &mmDC_ABM1_HG_RESULT_2[0], sizeof(mmDC_ABM1_HG_RESULT_2)/sizeof(mmDC_ABM1_HG_RESULT_2[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_3", REG_MMIO, 0x165d, &mmDC_ABM1_HG_RESULT_3[0], sizeof(mmDC_ABM1_HG_RESULT_3)/sizeof(mmDC_ABM1_HG_RESULT_3[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_4", REG_MMIO, 0x165e, &mmDC_ABM1_HG_RESULT_4[0], sizeof(mmDC_ABM1_HG_RESULT_4)/sizeof(mmDC_ABM1_HG_RESULT_4[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_5", REG_MMIO, 0x165f, &mmDC_ABM1_HG_RESULT_5[0], sizeof(mmDC_ABM1_HG_RESULT_5)/sizeof(mmDC_ABM1_HG_RESULT_5[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_6", REG_MMIO, 0x1660, &mmDC_ABM1_HG_RESULT_6[0], sizeof(mmDC_ABM1_HG_RESULT_6)/sizeof(mmDC_ABM1_HG_RESULT_6[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_7", REG_MMIO, 0x1661, &mmDC_ABM1_HG_RESULT_7[0], sizeof(mmDC_ABM1_HG_RESULT_7)/sizeof(mmDC_ABM1_HG_RESULT_7[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_8", REG_MMIO, 0x1662, &mmDC_ABM1_HG_RESULT_8[0], sizeof(mmDC_ABM1_HG_RESULT_8)/sizeof(mmDC_ABM1_HG_RESULT_8[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_9", REG_MMIO, 0x1663, &mmDC_ABM1_HG_RESULT_9[0], sizeof(mmDC_ABM1_HG_RESULT_9)/sizeof(mmDC_ABM1_HG_RESULT_9[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_10", REG_MMIO, 0x1664, &mmDC_ABM1_HG_RESULT_10[0], sizeof(mmDC_ABM1_HG_RESULT_10)/sizeof(mmDC_ABM1_HG_RESULT_10[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_11", REG_MMIO, 0x1665, &mmDC_ABM1_HG_RESULT_11[0], sizeof(mmDC_ABM1_HG_RESULT_11)/sizeof(mmDC_ABM1_HG_RESULT_11[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_12", REG_MMIO, 0x1666, &mmDC_ABM1_HG_RESULT_12[0], sizeof(mmDC_ABM1_HG_RESULT_12)/sizeof(mmDC_ABM1_HG_RESULT_12[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_13", REG_MMIO, 0x1667, &mmDC_ABM1_HG_RESULT_13[0], sizeof(mmDC_ABM1_HG_RESULT_13)/sizeof(mmDC_ABM1_HG_RESULT_13[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_14", REG_MMIO, 0x1668, &mmDC_ABM1_HG_RESULT_14[0], sizeof(mmDC_ABM1_HG_RESULT_14)/sizeof(mmDC_ABM1_HG_RESULT_14[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_15", REG_MMIO, 0x1669, &mmDC_ABM1_HG_RESULT_15[0], sizeof(mmDC_ABM1_HG_RESULT_15)/sizeof(mmDC_ABM1_HG_RESULT_15[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_16", REG_MMIO, 0x166a, &mmDC_ABM1_HG_RESULT_16[0], sizeof(mmDC_ABM1_HG_RESULT_16)/sizeof(mmDC_ABM1_HG_RESULT_16[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_17", REG_MMIO, 0x166b, &mmDC_ABM1_HG_RESULT_17[0], sizeof(mmDC_ABM1_HG_RESULT_17)/sizeof(mmDC_ABM1_HG_RESULT_17[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_18", REG_MMIO, 0x166c, &mmDC_ABM1_HG_RESULT_18[0], sizeof(mmDC_ABM1_HG_RESULT_18)/sizeof(mmDC_ABM1_HG_RESULT_18[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_19", REG_MMIO, 0x166d, &mmDC_ABM1_HG_RESULT_19[0], sizeof(mmDC_ABM1_HG_RESULT_19)/sizeof(mmDC_ABM1_HG_RESULT_19[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_20", REG_MMIO, 0x166e, &mmDC_ABM1_HG_RESULT_20[0], sizeof(mmDC_ABM1_HG_RESULT_20)/sizeof(mmDC_ABM1_HG_RESULT_20[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_21", REG_MMIO, 0x166f, &mmDC_ABM1_HG_RESULT_21[0], sizeof(mmDC_ABM1_HG_RESULT_21)/sizeof(mmDC_ABM1_HG_RESULT_21[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_22", REG_MMIO, 0x1670, &mmDC_ABM1_HG_RESULT_22[0], sizeof(mmDC_ABM1_HG_RESULT_22)/sizeof(mmDC_ABM1_HG_RESULT_22[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_23", REG_MMIO, 0x1671, &mmDC_ABM1_HG_RESULT_23[0], sizeof(mmDC_ABM1_HG_RESULT_23)/sizeof(mmDC_ABM1_HG_RESULT_23[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_24", REG_MMIO, 0x1672, &mmDC_ABM1_HG_RESULT_24[0], sizeof(mmDC_ABM1_HG_RESULT_24)/sizeof(mmDC_ABM1_HG_RESULT_24[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5", REG_MMIO, 0x1673, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x1674, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2", REG_MMIO, 0x1675, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3", REG_MMIO, 0x1676, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4", REG_MMIO, 0x1677, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x1678, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2", REG_MMIO, 0x1679, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3", REG_MMIO, 0x167a, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4", REG_MMIO, 0x167b, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0]), 0, 0 },
+	{ "mmDC_ABM1_OVERSCAN_PIXEL_VALUE", REG_MMIO, 0x169b, &mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0], sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE)/sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0]), 0, 0 },
+	{ "mmDC_ABM1_BL_MASTER_LOCK", REG_MMIO, 0x169c, &mmDC_ABM1_BL_MASTER_LOCK[0], sizeof(mmDC_ABM1_BL_MASTER_LOCK)/sizeof(mmDC_ABM1_BL_MASTER_LOCK[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_INDEX", REG_MMIO, 0x169e, &mmABM_TEST_DEBUG_INDEX[0], sizeof(mmABM_TEST_DEBUG_INDEX)/sizeof(mmABM_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_DATA", REG_MMIO, 0x169f, &mmABM_TEST_DEBUG_DATA[0], sizeof(mmABM_TEST_DEBUG_DATA)/sizeof(mmABM_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDVO_ENABLE", REG_MMIO, 0x16a0, &mmDVO_ENABLE[0], sizeof(mmDVO_ENABLE)/sizeof(mmDVO_ENABLE[0]), 0, 0 },
+	{ "mmDVO_SOURCE_SELECT", REG_MMIO, 0x16a1, &mmDVO_SOURCE_SELECT[0], sizeof(mmDVO_SOURCE_SELECT)/sizeof(mmDVO_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDVO_OUTPUT", REG_MMIO, 0x16a2, &mmDVO_OUTPUT[0], sizeof(mmDVO_OUTPUT)/sizeof(mmDVO_OUTPUT[0]), 0, 0 },
+	{ "mmDVO_CONTROL", REG_MMIO, 0x16a3, &mmDVO_CONTROL[0], sizeof(mmDVO_CONTROL)/sizeof(mmDVO_CONTROL[0]), 0, 0 },
+	{ "mmDVO_CRC_EN", REG_MMIO, 0x16a4, &mmDVO_CRC_EN[0], sizeof(mmDVO_CRC_EN)/sizeof(mmDVO_CRC_EN[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_MASK", REG_MMIO, 0x16a5, &mmDVO_CRC2_SIG_MASK[0], sizeof(mmDVO_CRC2_SIG_MASK)/sizeof(mmDVO_CRC2_SIG_MASK[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_RESULT", REG_MMIO, 0x16a6, &mmDVO_CRC2_SIG_RESULT[0], sizeof(mmDVO_CRC2_SIG_RESULT)/sizeof(mmDVO_CRC2_SIG_RESULT[0]), 0, 0 },
+	{ "mmDVO_FIFO_ERROR_STATUS", REG_MMIO, 0x16a7, &mmDVO_FIFO_ERROR_STATUS[0], sizeof(mmDVO_FIFO_ERROR_STATUS)/sizeof(mmDVO_FIFO_ERROR_STATUS[0]), 0, 0 },
+	{ "mmDVO_TEST_DEBUG_INDEX", REG_MMIO, 0x16a8, &mmDVO_TEST_DEBUG_INDEX[0], sizeof(mmDVO_TEST_DEBUG_INDEX)/sizeof(mmDVO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDVO_TEST_DEBUG_DATA", REG_MMIO, 0x16a9, &mmDVO_TEST_DEBUG_DATA[0], sizeof(mmDVO_TEST_DEBUG_DATA)/sizeof(mmDVO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDAC_ENABLE", REG_MMIO, 0x16aa, &mmDAC_ENABLE[0], sizeof(mmDAC_ENABLE)/sizeof(mmDAC_ENABLE[0]), 0, 0 },
+	{ "mmDAC_SOURCE_SELECT", REG_MMIO, 0x16ab, &mmDAC_SOURCE_SELECT[0], sizeof(mmDAC_SOURCE_SELECT)/sizeof(mmDAC_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDAC_CRC_EN", REG_MMIO, 0x16ac, &mmDAC_CRC_EN[0], sizeof(mmDAC_CRC_EN)/sizeof(mmDAC_CRC_EN[0]), 0, 0 },
+	{ "mmDAC_CRC_CONTROL", REG_MMIO, 0x16ad, &mmDAC_CRC_CONTROL[0], sizeof(mmDAC_CRC_CONTROL)/sizeof(mmDAC_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB_MASK", REG_MMIO, 0x16ae, &mmDAC_CRC_SIG_RGB_MASK[0], sizeof(mmDAC_CRC_SIG_RGB_MASK)/sizeof(mmDAC_CRC_SIG_RGB_MASK[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL_MASK", REG_MMIO, 0x16af, &mmDAC_CRC_SIG_CONTROL_MASK[0], sizeof(mmDAC_CRC_SIG_CONTROL_MASK)/sizeof(mmDAC_CRC_SIG_CONTROL_MASK[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO_SOURCE", REG_MMIO, 0x16b, &mmDCCG_AUDIO_DTO_SOURCE[0], sizeof(mmDCCG_AUDIO_DTO_SOURCE)/sizeof(mmDCCG_AUDIO_DTO_SOURCE[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB", REG_MMIO, 0x16b0, &mmDAC_CRC_SIG_RGB[0], sizeof(mmDAC_CRC_SIG_RGB)/sizeof(mmDAC_CRC_SIG_RGB[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL", REG_MMIO, 0x16b1, &mmDAC_CRC_SIG_CONTROL[0], sizeof(mmDAC_CRC_SIG_CONTROL)/sizeof(mmDAC_CRC_SIG_CONTROL[0]), 0, 0 },
+	{ "mmDAC_SYNC_TRISTATE_CONTROL", REG_MMIO, 0x16b2, &mmDAC_SYNC_TRISTATE_CONTROL[0], sizeof(mmDAC_SYNC_TRISTATE_CONTROL)/sizeof(mmDAC_SYNC_TRISTATE_CONTROL[0]), 0, 0 },
+	{ "mmDAC_STEREOSYNC_SELECT", REG_MMIO, 0x16b3, &mmDAC_STEREOSYNC_SELECT[0], sizeof(mmDAC_STEREOSYNC_SELECT)/sizeof(mmDAC_STEREOSYNC_SELECT[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL", REG_MMIO, 0x16b4, &mmDAC_AUTODETECT_CONTROL[0], sizeof(mmDAC_AUTODETECT_CONTROL)/sizeof(mmDAC_AUTODETECT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL2", REG_MMIO, 0x16b5, &mmDAC_AUTODETECT_CONTROL2[0], sizeof(mmDAC_AUTODETECT_CONTROL2)/sizeof(mmDAC_AUTODETECT_CONTROL2[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL3", REG_MMIO, 0x16b6, &mmDAC_AUTODETECT_CONTROL3[0], sizeof(mmDAC_AUTODETECT_CONTROL3)/sizeof(mmDAC_AUTODETECT_CONTROL3[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_STATUS", REG_MMIO, 0x16b7, &mmDAC_AUTODETECT_STATUS[0], sizeof(mmDAC_AUTODETECT_STATUS)/sizeof(mmDAC_AUTODETECT_STATUS[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_INT_CONTROL", REG_MMIO, 0x16b8, &mmDAC_AUTODETECT_INT_CONTROL[0], sizeof(mmDAC_AUTODETECT_INT_CONTROL)/sizeof(mmDAC_AUTODETECT_INT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_FORCE_OUTPUT_CNTL", REG_MMIO, 0x16b9, &mmDAC_FORCE_OUTPUT_CNTL[0], sizeof(mmDAC_FORCE_OUTPUT_CNTL)/sizeof(mmDAC_FORCE_OUTPUT_CNTL[0]), 0, 0 },
+	{ "mmDAC_FORCE_DATA", REG_MMIO, 0x16ba, &mmDAC_FORCE_DATA[0], sizeof(mmDAC_FORCE_DATA)/sizeof(mmDAC_FORCE_DATA[0]), 0, 0 },
+	{ "mmDAC_POWERDOWN", REG_MMIO, 0x16bb, &mmDAC_POWERDOWN[0], sizeof(mmDAC_POWERDOWN)/sizeof(mmDAC_POWERDOWN[0]), 0, 0 },
+	{ "mmDAC_CONTROL", REG_MMIO, 0x16bc, &mmDAC_CONTROL[0], sizeof(mmDAC_CONTROL)/sizeof(mmDAC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_ENABLE", REG_MMIO, 0x16bd, &mmDAC_COMPARATOR_ENABLE[0], sizeof(mmDAC_COMPARATOR_ENABLE)/sizeof(mmDAC_COMPARATOR_ENABLE[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_OUTPUT", REG_MMIO, 0x16be, &mmDAC_COMPARATOR_OUTPUT[0], sizeof(mmDAC_COMPARATOR_OUTPUT)/sizeof(mmDAC_COMPARATOR_OUTPUT[0]), 0, 0 },
+	{ "mmDAC_PWR_CNTL", REG_MMIO, 0x16bf, &mmDAC_PWR_CNTL[0], sizeof(mmDAC_PWR_CNTL)/sizeof(mmDAC_PWR_CNTL[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_PHASE", REG_MMIO, 0x16c, &mmDCCG_AUDIO_DTO0_PHASE[0], sizeof(mmDCCG_AUDIO_DTO0_PHASE)/sizeof(mmDCCG_AUDIO_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDAC_DFT_CONFIG", REG_MMIO, 0x16c0, &mmDAC_DFT_CONFIG[0], sizeof(mmDAC_DFT_CONFIG)/sizeof(mmDAC_DFT_CONFIG[0]), 0, 0 },
+	{ "mmDAC_FIFO_STATUS", REG_MMIO, 0x16c1, &mmDAC_FIFO_STATUS[0], sizeof(mmDAC_FIFO_STATUS)/sizeof(mmDAC_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDAC_TEST_DEBUG_INDEX", REG_MMIO, 0x16c2, &mmDAC_TEST_DEBUG_INDEX[0], sizeof(mmDAC_TEST_DEBUG_INDEX)/sizeof(mmDAC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDAC_TEST_DEBUG_DATA", REG_MMIO, 0x16c3, &mmDAC_TEST_DEBUG_DATA[0], sizeof(mmDAC_TEST_DEBUG_DATA)/sizeof(mmDAC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK1_SEL", REG_MMIO, 0x16c4, &mmDCDEBUG_BUS_CLK1_SEL[0], sizeof(mmDCDEBUG_BUS_CLK1_SEL)/sizeof(mmDCDEBUG_BUS_CLK1_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK2_SEL", REG_MMIO, 0x16c5, &mmDCDEBUG_BUS_CLK2_SEL[0], sizeof(mmDCDEBUG_BUS_CLK2_SEL)/sizeof(mmDCDEBUG_BUS_CLK2_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK3_SEL", REG_MMIO, 0x16c6, &mmDCDEBUG_BUS_CLK3_SEL[0], sizeof(mmDCDEBUG_BUS_CLK3_SEL)/sizeof(mmDCDEBUG_BUS_CLK3_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK4_SEL", REG_MMIO, 0x16c7, &mmDCDEBUG_BUS_CLK4_SEL[0], sizeof(mmDCDEBUG_BUS_CLK4_SEL)/sizeof(mmDCDEBUG_BUS_CLK4_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK5_SEL", REG_MMIO, 0x16c8, &mmDCDEBUG_BUS_CLK5_SEL[0], sizeof(mmDCDEBUG_BUS_CLK5_SEL)/sizeof(mmDCDEBUG_BUS_CLK5_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_PIN_OVERRIDE", REG_MMIO, 0x16c9, &mmDCDEBUG_OUT_PIN_OVERRIDE[0], sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE)/sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_CNTL", REG_MMIO, 0x16ca, &mmDCDEBUG_OUT_CNTL[0], sizeof(mmDCDEBUG_OUT_CNTL)/sizeof(mmDCDEBUG_OUT_CNTL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_DATA", REG_MMIO, 0x16cb, &mmDCDEBUG_OUT_DATA[0], sizeof(mmDCDEBUG_OUT_DATA)/sizeof(mmDCDEBUG_OUT_DATA[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_MODULE", REG_MMIO, 0x16d, &mmDCCG_AUDIO_DTO0_MODULE[0], sizeof(mmDCCG_AUDIO_DTO0_MODULE)/sizeof(mmDCCG_AUDIO_DTO0_MODULE[0]), 0, 0 },
+	{ "mmDC_I2C_CONTROL", REG_MMIO, 0x16d4, &mmDC_I2C_CONTROL[0], sizeof(mmDC_I2C_CONTROL)/sizeof(mmDC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_ARBITRATION", REG_MMIO, 0x16d5, &mmDC_I2C_ARBITRATION[0], sizeof(mmDC_I2C_ARBITRATION)/sizeof(mmDC_I2C_ARBITRATION[0]), 0, 0 },
+	{ "mmDC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x16d6, &mmDC_I2C_INTERRUPT_CONTROL[0], sizeof(mmDC_I2C_INTERRUPT_CONTROL)/sizeof(mmDC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_SW_STATUS", REG_MMIO, 0x16d7, &mmDC_I2C_SW_STATUS[0], sizeof(mmDC_I2C_SW_STATUS)/sizeof(mmDC_I2C_SW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_HW_STATUS", REG_MMIO, 0x16d8, &mmDC_I2C_DDC1_HW_STATUS[0], sizeof(mmDC_I2C_DDC1_HW_STATUS)/sizeof(mmDC_I2C_DDC1_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_HW_STATUS", REG_MMIO, 0x16d9, &mmDC_I2C_DDC2_HW_STATUS[0], sizeof(mmDC_I2C_DDC2_HW_STATUS)/sizeof(mmDC_I2C_DDC2_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_HW_STATUS", REG_MMIO, 0x16da, &mmDC_I2C_DDC3_HW_STATUS[0], sizeof(mmDC_I2C_DDC3_HW_STATUS)/sizeof(mmDC_I2C_DDC3_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_HW_STATUS", REG_MMIO, 0x16db, &mmDC_I2C_DDC4_HW_STATUS[0], sizeof(mmDC_I2C_DDC4_HW_STATUS)/sizeof(mmDC_I2C_DDC4_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_HW_STATUS", REG_MMIO, 0x16dc, &mmDC_I2C_DDC5_HW_STATUS[0], sizeof(mmDC_I2C_DDC5_HW_STATUS)/sizeof(mmDC_I2C_DDC5_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_HW_STATUS", REG_MMIO, 0x16dd, &mmDC_I2C_DDC6_HW_STATUS[0], sizeof(mmDC_I2C_DDC6_HW_STATUS)/sizeof(mmDC_I2C_DDC6_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SPEED", REG_MMIO, 0x16de, &mmDC_I2C_DDC1_SPEED[0], sizeof(mmDC_I2C_DDC1_SPEED)/sizeof(mmDC_I2C_DDC1_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SETUP", REG_MMIO, 0x16df, &mmDC_I2C_DDC1_SETUP[0], sizeof(mmDC_I2C_DDC1_SETUP)/sizeof(mmDC_I2C_DDC1_SETUP[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_PHASE", REG_MMIO, 0x16e, &mmDCCG_AUDIO_DTO1_PHASE[0], sizeof(mmDCCG_AUDIO_DTO1_PHASE)/sizeof(mmDCCG_AUDIO_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SPEED", REG_MMIO, 0x16e0, &mmDC_I2C_DDC2_SPEED[0], sizeof(mmDC_I2C_DDC2_SPEED)/sizeof(mmDC_I2C_DDC2_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SETUP", REG_MMIO, 0x16e1, &mmDC_I2C_DDC2_SETUP[0], sizeof(mmDC_I2C_DDC2_SETUP)/sizeof(mmDC_I2C_DDC2_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SPEED", REG_MMIO, 0x16e2, &mmDC_I2C_DDC3_SPEED[0], sizeof(mmDC_I2C_DDC3_SPEED)/sizeof(mmDC_I2C_DDC3_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SETUP", REG_MMIO, 0x16e3, &mmDC_I2C_DDC3_SETUP[0], sizeof(mmDC_I2C_DDC3_SETUP)/sizeof(mmDC_I2C_DDC3_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SPEED", REG_MMIO, 0x16e4, &mmDC_I2C_DDC4_SPEED[0], sizeof(mmDC_I2C_DDC4_SPEED)/sizeof(mmDC_I2C_DDC4_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SETUP", REG_MMIO, 0x16e5, &mmDC_I2C_DDC4_SETUP[0], sizeof(mmDC_I2C_DDC4_SETUP)/sizeof(mmDC_I2C_DDC4_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SPEED", REG_MMIO, 0x16e6, &mmDC_I2C_DDC5_SPEED[0], sizeof(mmDC_I2C_DDC5_SPEED)/sizeof(mmDC_I2C_DDC5_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SETUP", REG_MMIO, 0x16e7, &mmDC_I2C_DDC5_SETUP[0], sizeof(mmDC_I2C_DDC5_SETUP)/sizeof(mmDC_I2C_DDC5_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SPEED", REG_MMIO, 0x16e8, &mmDC_I2C_DDC6_SPEED[0], sizeof(mmDC_I2C_DDC6_SPEED)/sizeof(mmDC_I2C_DDC6_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SETUP", REG_MMIO, 0x16e9, &mmDC_I2C_DDC6_SETUP[0], sizeof(mmDC_I2C_DDC6_SETUP)/sizeof(mmDC_I2C_DDC6_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION0", REG_MMIO, 0x16ea, &mmDC_I2C_TRANSACTION0[0], sizeof(mmDC_I2C_TRANSACTION0)/sizeof(mmDC_I2C_TRANSACTION0[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION1", REG_MMIO, 0x16eb, &mmDC_I2C_TRANSACTION1[0], sizeof(mmDC_I2C_TRANSACTION1)/sizeof(mmDC_I2C_TRANSACTION1[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION2", REG_MMIO, 0x16ec, &mmDC_I2C_TRANSACTION2[0], sizeof(mmDC_I2C_TRANSACTION2)/sizeof(mmDC_I2C_TRANSACTION2[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION3", REG_MMIO, 0x16ed, &mmDC_I2C_TRANSACTION3[0], sizeof(mmDC_I2C_TRANSACTION3)/sizeof(mmDC_I2C_TRANSACTION3[0]), 0, 0 },
+	{ "mmDC_I2C_DATA", REG_MMIO, 0x16ee, &mmDC_I2C_DATA[0], sizeof(mmDC_I2C_DATA)/sizeof(mmDC_I2C_DATA[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_HW_STATUS", REG_MMIO, 0x16ef, &mmDC_I2C_DDCVGA_HW_STATUS[0], sizeof(mmDC_I2C_DDCVGA_HW_STATUS)/sizeof(mmDC_I2C_DDCVGA_HW_STATUS[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_MODULE", REG_MMIO, 0x16f, &mmDCCG_AUDIO_DTO1_MODULE[0], sizeof(mmDCCG_AUDIO_DTO1_MODULE)/sizeof(mmDCCG_AUDIO_DTO1_MODULE[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SPEED", REG_MMIO, 0x16f0, &mmDC_I2C_DDCVGA_SPEED[0], sizeof(mmDC_I2C_DDCVGA_SPEED)/sizeof(mmDC_I2C_DDCVGA_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SETUP", REG_MMIO, 0x16f1, &mmDC_I2C_DDCVGA_SETUP[0], sizeof(mmDC_I2C_DDCVGA_SETUP)/sizeof(mmDC_I2C_DDCVGA_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_EDID_DETECT_CTRL", REG_MMIO, 0x16f2, &mmDC_I2C_EDID_DETECT_CTRL[0], sizeof(mmDC_I2C_EDID_DETECT_CTRL)/sizeof(mmDC_I2C_EDID_DETECT_CTRL[0]), 0, 0 },
+	{ "mmDC_I2C_READ_REQUEST_INTERRUPT", REG_MMIO, 0x16f3, &mmDC_I2C_READ_REQUEST_INTERRUPT[0], sizeof(mmDC_I2C_READ_REQUEST_INTERRUPT)/sizeof(mmDC_I2C_READ_REQUEST_INTERRUPT[0]), 0, 0 },
+	{ "mmGENERIC_I2C_CONTROL", REG_MMIO, 0x16f4, &mmGENERIC_I2C_CONTROL[0], sizeof(mmGENERIC_I2C_CONTROL)/sizeof(mmGENERIC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x16f5, &mmGENERIC_I2C_INTERRUPT_CONTROL[0], sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL)/sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_STATUS", REG_MMIO, 0x16f6, &mmGENERIC_I2C_STATUS[0], sizeof(mmGENERIC_I2C_STATUS)/sizeof(mmGENERIC_I2C_STATUS[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SPEED", REG_MMIO, 0x16f7, &mmGENERIC_I2C_SPEED[0], sizeof(mmGENERIC_I2C_SPEED)/sizeof(mmGENERIC_I2C_SPEED[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SETUP", REG_MMIO, 0x16f8, &mmGENERIC_I2C_SETUP[0], sizeof(mmGENERIC_I2C_SETUP)/sizeof(mmGENERIC_I2C_SETUP[0]), 0, 0 },
+	{ "mmGENERIC_I2C_TRANSACTION", REG_MMIO, 0x16f9, &mmGENERIC_I2C_TRANSACTION[0], sizeof(mmGENERIC_I2C_TRANSACTION)/sizeof(mmGENERIC_I2C_TRANSACTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_DATA", REG_MMIO, 0x16fa, &mmGENERIC_I2C_DATA[0], sizeof(mmGENERIC_I2C_DATA)/sizeof(mmGENERIC_I2C_DATA[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_SELECTION", REG_MMIO, 0x16fb, &mmGENERIC_I2C_PIN_SELECTION[0], sizeof(mmGENERIC_I2C_PIN_SELECTION)/sizeof(mmGENERIC_I2C_PIN_SELECTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_DEBUG", REG_MMIO, 0x16fc, &mmGENERIC_I2C_PIN_DEBUG[0], sizeof(mmGENERIC_I2C_PIN_DEBUG)/sizeof(mmGENERIC_I2C_PIN_DEBUG[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_H", REG_SMC, 0x17, &ixDP_AUX_DEBUG_H[0], sizeof(ixDP_AUX_DEBUG_H)/sizeof(ixDP_AUX_DEBUG_H[0]), 0, 0 },
+	{ "ixDCIO_DEBUG17", REG_SMC, 0x17, &ixDCIO_DEBUG17[0], sizeof(ixDCIO_DEBUG17)/sizeof(ixDCIO_DEBUG17[0]), 0, 0 },
+	{ "mmRIRB_STATUS", REG_MMIO, 0x17, &mmRIRB_STATUS[0], sizeof(mmRIRB_STATUS)/sizeof(mmRIRB_STATUS[0]), 0, 0 },
+	{ "mmRIRB_SIZE", REG_MMIO, 0x17, &mmRIRB_SIZE[0], sizeof(mmRIRB_SIZE)/sizeof(mmRIRB_SIZE[0]), 0, 0 },
+	{ "ixCRT17", REG_SMC, 0x17, &ixCRT17[0], sizeof(ixCRT17)/sizeof(ixCRT17[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFCOUNTER_CNTL", REG_MMIO, 0x170, NULL, 0, 0, 0 },
+	{ "mmPERFCOUNTER_CNTL", REG_MMIO, 0x170, &mmPERFCOUNTER_CNTL[0], sizeof(mmPERFCOUNTER_CNTL)/sizeof(mmPERFCOUNTER_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1700, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_VREG_CFG", REG_MMIO, 0x1700, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1700, &mmPLL_MACRO_CNTL_RESERVED0[0], sizeof(mmPLL_MACRO_CNTL_RESERVED0)/sizeof(mmPLL_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmPPLL_VREG_CFG", REG_MMIO, 0x1700, &mmPPLL_VREG_CFG[0], sizeof(mmPPLL_VREG_CFG)/sizeof(mmPPLL_VREG_CFG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1701, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_MODE_CNTL", REG_MMIO, 0x1701, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1701, &mmPLL_MACRO_CNTL_RESERVED1[0], sizeof(mmPLL_MACRO_CNTL_RESERVED1)/sizeof(mmPLL_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmPPLL_MODE_CNTL", REG_MMIO, 0x1701, &mmPPLL_MODE_CNTL[0], sizeof(mmPPLL_MODE_CNTL)/sizeof(mmPPLL_MODE_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1702, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1702, &mmPLL_MACRO_CNTL_RESERVED2[0], sizeof(mmPLL_MACRO_CNTL_RESERVED2)/sizeof(mmPLL_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmPPLL_FREQ_CTRL0", REG_MMIO, 0x1702, &mmPPLL_FREQ_CTRL0[0], sizeof(mmPPLL_FREQ_CTRL0)/sizeof(mmPPLL_FREQ_CTRL0[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1703, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1703, &mmPLL_MACRO_CNTL_RESERVED3[0], sizeof(mmPLL_MACRO_CNTL_RESERVED3)/sizeof(mmPLL_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmPPLL_FREQ_CTRL1", REG_MMIO, 0x1703, &mmPPLL_FREQ_CTRL1[0], sizeof(mmPPLL_FREQ_CTRL1)/sizeof(mmPPLL_FREQ_CTRL1[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1704, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1704, &mmPLL_MACRO_CNTL_RESERVED4[0], sizeof(mmPLL_MACRO_CNTL_RESERVED4)/sizeof(mmPLL_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmPPLL_FREQ_CTRL2", REG_MMIO, 0x1704, &mmPPLL_FREQ_CTRL2[0], sizeof(mmPPLL_FREQ_CTRL2)/sizeof(mmPPLL_FREQ_CTRL2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_SMC, 0x1705, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1705, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1705, &mmPLL_MACRO_CNTL_RESERVED5[0], sizeof(mmPLL_MACRO_CNTL_RESERVED5)/sizeof(mmPLL_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmPPLL_FREQ_CTRL3", REG_MMIO, 0x1705, &mmPPLL_FREQ_CTRL3[0], sizeof(mmPPLL_FREQ_CTRL3)/sizeof(mmPPLL_FREQ_CTRL3[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_COARSE", REG_MMIO, 0x1706, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1706, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1706, &mmPLL_MACRO_CNTL_RESERVED6[0], sizeof(mmPLL_MACRO_CNTL_RESERVED6)/sizeof(mmPLL_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmPPLL_BW_CTRL_COARSE", REG_MMIO, 0x1706, &mmPPLL_BW_CTRL_COARSE[0], sizeof(mmPPLL_BW_CTRL_COARSE)/sizeof(mmPPLL_BW_CTRL_COARSE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1707, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1707, &mmPLL_MACRO_CNTL_RESERVED7[0], sizeof(mmPLL_MACRO_CNTL_RESERVED7)/sizeof(mmPLL_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_BW_CTRL_FINE", REG_MMIO, 0x1708, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1708, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1708, &mmPLL_MACRO_CNTL_RESERVED8[0], sizeof(mmPLL_MACRO_CNTL_RESERVED8)/sizeof(mmPLL_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmPPLL_BW_CTRL_FINE", REG_MMIO, 0x1708, &mmPPLL_BW_CTRL_FINE[0], sizeof(mmPPLL_BW_CTRL_FINE)/sizeof(mmPPLL_BW_CTRL_FINE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1709, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_CAL_CTRL", REG_MMIO, 0x1709, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1709, &mmPLL_MACRO_CNTL_RESERVED9[0], sizeof(mmPLL_MACRO_CNTL_RESERVED9)/sizeof(mmPLL_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmPPLL_CAL_CTRL", REG_MMIO, 0x1709, &mmPPLL_CAL_CTRL[0], sizeof(mmPPLL_CAL_CTRL)/sizeof(mmPPLL_CAL_CTRL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x170a, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_LOOP_CTRL", REG_MMIO, 0x170a, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x170a, &mmPLL_MACRO_CNTL_RESERVED10[0], sizeof(mmPLL_MACRO_CNTL_RESERVED10)/sizeof(mmPLL_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmPPLL_LOOP_CTRL", REG_MMIO, 0x170a, &mmPPLL_LOOP_CTRL[0], sizeof(mmPPLL_LOOP_CTRL)/sizeof(mmPPLL_LOOP_CTRL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x170b, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x170b, &mmPLL_MACRO_CNTL_RESERVED11[0], sizeof(mmPLL_MACRO_CNTL_RESERVED11)/sizeof(mmPLL_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x170c, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x170c, &mmPLL_MACRO_CNTL_RESERVED12[0], sizeof(mmPLL_MACRO_CNTL_RESERVED12)/sizeof(mmPLL_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x170d, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x170d, &mmPLL_MACRO_CNTL_RESERVED13[0], sizeof(mmPLL_MACRO_CNTL_RESERVED13)/sizeof(mmPLL_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x170e, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x170e, &mmPLL_MACRO_CNTL_RESERVED14[0], sizeof(mmPLL_MACRO_CNTL_RESERVED14)/sizeof(mmPLL_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x170f, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x170f, &mmPLL_MACRO_CNTL_RESERVED15[0], sizeof(mmPLL_MACRO_CNTL_RESERVED15)/sizeof(mmPLL_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFCOUNTER_STATE", REG_MMIO, 0x171, NULL, 0, 0, 0 },
+	{ "mmPERFCOUNTER_STATE", REG_MMIO, 0x171, &mmPERFCOUNTER_STATE[0], sizeof(mmPERFCOUNTER_STATE)/sizeof(mmPERFCOUNTER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1710, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1710, &mmPLL_MACRO_CNTL_RESERVED16[0], sizeof(mmPLL_MACRO_CNTL_RESERVED16)/sizeof(mmPLL_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1711, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1711, &mmPLL_MACRO_CNTL_RESERVED17[0], sizeof(mmPLL_MACRO_CNTL_RESERVED17)/sizeof(mmPLL_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1712, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1712, &mmPLL_MACRO_CNTL_RESERVED18[0], sizeof(mmPLL_MACRO_CNTL_RESERVED18)/sizeof(mmPLL_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1713, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1713, &mmPLL_MACRO_CNTL_RESERVED19[0], sizeof(mmPLL_MACRO_CNTL_RESERVED19)/sizeof(mmPLL_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1714, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1714, &mmPLL_MACRO_CNTL_RESERVED20[0], sizeof(mmPLL_MACRO_CNTL_RESERVED20)/sizeof(mmPLL_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1715, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1715, &mmPLL_MACRO_CNTL_RESERVED21[0], sizeof(mmPLL_MACRO_CNTL_RESERVED21)/sizeof(mmPLL_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1716, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1716, &mmPLL_MACRO_CNTL_RESERVED22[0], sizeof(mmPLL_MACRO_CNTL_RESERVED22)/sizeof(mmPLL_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1717, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1717, &mmPLL_MACRO_CNTL_RESERVED23[0], sizeof(mmPLL_MACRO_CNTL_RESERVED23)/sizeof(mmPLL_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1718, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1718, &mmPLL_MACRO_CNTL_RESERVED24[0], sizeof(mmPLL_MACRO_CNTL_RESERVED24)/sizeof(mmPLL_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmPPLL_REFCLK_CNTL", REG_MMIO, 0x1718, &mmPPLL_REFCLK_CNTL[0], sizeof(mmPPLL_REFCLK_CNTL)/sizeof(mmPPLL_REFCLK_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1719, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1719, &mmPLL_MACRO_CNTL_RESERVED25[0], sizeof(mmPLL_MACRO_CNTL_RESERVED25)/sizeof(mmPLL_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmPPLL_CLKOUT_CNTL", REG_MMIO, 0x1719, &mmPPLL_CLKOUT_CNTL[0], sizeof(mmPPLL_CLKOUT_CNTL)/sizeof(mmPPLL_CLKOUT_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x171a, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_DFT_CNTL", REG_MMIO, 0x171a, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x171a, &mmPLL_MACRO_CNTL_RESERVED26[0], sizeof(mmPLL_MACRO_CNTL_RESERVED26)/sizeof(mmPLL_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmPPLL_DFT_CNTL", REG_MMIO, 0x171a, &mmPPLL_DFT_CNTL[0], sizeof(mmPPLL_DFT_CNTL)/sizeof(mmPPLL_DFT_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x171b, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x171b, &mmPLL_MACRO_CNTL_RESERVED27[0], sizeof(mmPLL_MACRO_CNTL_RESERVED27)/sizeof(mmPLL_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmPPLL_ANALOG_CNTL", REG_MMIO, 0x171b, &mmPPLL_ANALOG_CNTL[0], sizeof(mmPPLL_ANALOG_CNTL)/sizeof(mmPPLL_ANALOG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x171c, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_POSTDIV", REG_MMIO, 0x171c, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x171c, &mmPLL_MACRO_CNTL_RESERVED28[0], sizeof(mmPLL_MACRO_CNTL_RESERVED28)/sizeof(mmPLL_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmPPLL_POSTDIV", REG_MMIO, 0x171c, &mmPPLL_POSTDIV[0], sizeof(mmPPLL_POSTDIV)/sizeof(mmPPLL_POSTDIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x171d, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x171d, &mmPLL_MACRO_CNTL_RESERVED29[0], sizeof(mmPLL_MACRO_CNTL_RESERVED29)/sizeof(mmPLL_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x171e, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x171e, &mmPLL_MACRO_CNTL_RESERVED30[0], sizeof(mmPLL_MACRO_CNTL_RESERVED30)/sizeof(mmPLL_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x171f, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x171f, &mmPLL_MACRO_CNTL_RESERVED31[0], sizeof(mmPLL_MACRO_CNTL_RESERVED31)/sizeof(mmPLL_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x172, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CVALUE_INT_MISC", REG_MMIO, 0x172, &mmPERFMON_CVALUE_INT_MISC[0], sizeof(mmPERFMON_CVALUE_INT_MISC)/sizeof(mmPERFMON_CVALUE_INT_MISC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_SMC, 0x1720, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1720, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_DEBUG0", REG_MMIO, 0x1720, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1720, &mmPLL_MACRO_CNTL_RESERVED32[0], sizeof(mmPLL_MACRO_CNTL_RESERVED32)/sizeof(mmPLL_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmPPLL_DEBUG0", REG_MMIO, 0x1720, &mmPPLL_DEBUG0[0], sizeof(mmPPLL_DEBUG0)/sizeof(mmPPLL_DEBUG0[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2", REG_SMC, 0x1721, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1721, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0", REG_MMIO, 0x1721, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1721, &mmPLL_MACRO_CNTL_RESERVED33[0], sizeof(mmPLL_MACRO_CNTL_RESERVED33)/sizeof(mmPLL_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmPPLL_OBSERVE0", REG_MMIO, 0x1721, &mmPPLL_OBSERVE0[0], sizeof(mmPPLL_OBSERVE0)/sizeof(mmPPLL_OBSERVE0[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3", REG_SMC, 0x1722, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1722, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE1", REG_MMIO, 0x1722, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1722, &mmPLL_MACRO_CNTL_RESERVED34[0], sizeof(mmPLL_MACRO_CNTL_RESERVED34)/sizeof(mmPLL_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmPPLL_OBSERVE1", REG_MMIO, 0x1722, &mmPPLL_OBSERVE1[0], sizeof(mmPPLL_OBSERVE1)/sizeof(mmPPLL_OBSERVE1[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4", REG_SMC, 0x1723, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1723, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1723, &mmPLL_MACRO_CNTL_RESERVED35[0], sizeof(mmPLL_MACRO_CNTL_RESERVED35)/sizeof(mmPLL_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1724, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1724, &mmPLL_MACRO_CNTL_RESERVED36[0], sizeof(mmPLL_MACRO_CNTL_RESERVED36)/sizeof(mmPLL_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmPPLL_UPDATE_CNTL", REG_MMIO, 0x1724, &mmPPLL_UPDATE_CNTL[0], sizeof(mmPPLL_UPDATE_CNTL)/sizeof(mmPPLL_UPDATE_CNTL[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_OBSERVE0_OUT", REG_MMIO, 0x1725, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1725, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1725, &mmPLL_MACRO_CNTL_RESERVED37[0], sizeof(mmPLL_MACRO_CNTL_RESERVED37)/sizeof(mmPLL_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmPPLL_OBSERVE0_OUT", REG_MMIO, 0x1725, &mmPPLL_OBSERVE0_OUT[0], sizeof(mmPPLL_OBSERVE0_OUT)/sizeof(mmPPLL_OBSERVE0_OUT[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG1", REG_MMIO, 0x1726, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1726, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1726, &mmPLL_MACRO_CNTL_RESERVED38[0], sizeof(mmPLL_MACRO_CNTL_RESERVED38)/sizeof(mmPLL_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmPPLL_STATUS_DEBUG1", REG_MMIO, 0x1726, &mmPPLL_STATUS_DEBUG1[0], sizeof(mmPPLL_STATUS_DEBUG1)/sizeof(mmPPLL_STATUS_DEBUG1[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1727, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1727, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1727, &mmPLL_MACRO_CNTL_RESERVED39[0], sizeof(mmPLL_MACRO_CNTL_RESERVED39)/sizeof(mmPLL_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmPPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1727, &mmPPLL_DEBUG_MUX_CNTL[0], sizeof(mmPPLL_DEBUG_MUX_CNTL)/sizeof(mmPPLL_DEBUG_MUX_CNTL[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x1728, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1728, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1728, &mmPLL_MACRO_CNTL_RESERVED40[0], sizeof(mmPLL_MACRO_CNTL_RESERVED40)/sizeof(mmPLL_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmPPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x1728, &mmPPLL_DIV_UPDATE_DEBUG[0], sizeof(mmPPLL_DIV_UPDATE_DEBUG)/sizeof(mmPPLL_DIV_UPDATE_DEBUG[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS0_PPLL_STATUS_DEBUG0", REG_MMIO, 0x1729, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1729, NULL, 0, 0, 0 },
+	{ "mmPLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1729, &mmPLL_MACRO_CNTL_RESERVED41[0], sizeof(mmPLL_MACRO_CNTL_RESERVED41)/sizeof(mmPLL_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmPPLL_STATUS_DEBUG0", REG_MMIO, 0x1729, &mmPPLL_STATUS_DEBUG0[0], sizeof(mmPPLL_STATUS_DEBUG0)/sizeof(mmPPLL_STATUS_DEBUG0[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x172a, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_VREG_CFG", REG_MMIO, 0x172a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x172b, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_MODE_CNTL", REG_MMIO, 0x172b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x172c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x172d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x172e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x172f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CNTL", REG_MMIO, 0x173, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CNTL", REG_MMIO, 0x173, &mmPERFMON_CNTL[0], sizeof(mmPERFMON_CNTL)/sizeof(mmPERFMON_CNTL[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_COARSE", REG_MMIO, 0x1730, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x1730, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x1731, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_BW_CTRL_FINE", REG_MMIO, 0x1732, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x1732, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x1733, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_CAL_CTRL", REG_MMIO, 0x1733, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x1734, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_LOOP_CTRL", REG_MMIO, 0x1734, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x1735, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x1736, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x1737, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x1738, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x1739, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x173a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x173b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x173c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x173d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x173e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x173f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CVALUE_LOW", REG_MMIO, 0x174, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CVALUE_LOW", REG_MMIO, 0x174, &mmPERFMON_CVALUE_LOW[0], sizeof(mmPERFMON_CVALUE_LOW)/sizeof(mmPERFMON_CVALUE_LOW[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x1740, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x1741, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x1742, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x1743, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x1744, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_DFT_CNTL", REG_MMIO, 0x1744, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x1745, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x1746, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_POSTDIV", REG_MMIO, 0x1746, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x1747, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x1748, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x1749, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x174a, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_DEBUG0", REG_MMIO, 0x174a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x174b, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0", REG_MMIO, 0x174b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x174c, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE1", REG_MMIO, 0x174c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x174d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x174e, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_OBSERVE0_OUT", REG_MMIO, 0x174f, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x174f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_HI", REG_MMIO, 0x175, NULL, 0, 0, 0 },
+	{ "mmPERFMON_HI", REG_MMIO, 0x175, &mmPERFMON_HI[0], sizeof(mmPERFMON_HI)/sizeof(mmPERFMON_HI[0]), 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG1", REG_MMIO, 0x1750, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x1750, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x1751, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x1751, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x1752, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x1752, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS1_PPLL_STATUS_DEBUG0", REG_MMIO, 0x1753, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x1753, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x1754, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_VREG_CFG", REG_MMIO, 0x1754, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x1755, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_MODE_CNTL", REG_MMIO, 0x1755, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x1756, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x1757, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x1758, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x1759, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_COARSE", REG_MMIO, 0x175a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x175a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x175b, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_BW_CTRL_FINE", REG_MMIO, 0x175c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x175c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x175d, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_CAL_CTRL", REG_MMIO, 0x175d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x175e, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_LOOP_CTRL", REG_MMIO, 0x175e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x175f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_LOW", REG_MMIO, 0x176, NULL, 0, 0, 0 },
+	{ "mmPERFMON_LOW", REG_MMIO, 0x176, &mmPERFMON_LOW[0], sizeof(mmPERFMON_LOW)/sizeof(mmPERFMON_LOW[0]), 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED12", REG_MMIO, 0x1760, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED13", REG_MMIO, 0x1761, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED14", REG_MMIO, 0x1762, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED15", REG_MMIO, 0x1763, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED16", REG_MMIO, 0x1764, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED17", REG_MMIO, 0x1765, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED18", REG_MMIO, 0x1766, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED19", REG_MMIO, 0x1767, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED20", REG_MMIO, 0x1768, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED21", REG_MMIO, 0x1769, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED22", REG_MMIO, 0x176a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED23", REG_MMIO, 0x176b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED24", REG_MMIO, 0x176c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED25", REG_MMIO, 0x176d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED26", REG_MMIO, 0x176e, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_DFT_CNTL", REG_MMIO, 0x176e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED27", REG_MMIO, 0x176f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x177, NULL, 0, 0, 0 },
+	{ "mmPERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x177, &mmPERFMON_TEST_DEBUG_INDEX[0], sizeof(mmPERFMON_TEST_DEBUG_INDEX)/sizeof(mmPERFMON_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_SMC, 0x1770, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED28", REG_MMIO, 0x1770, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_POSTDIV", REG_MMIO, 0x1770, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED29", REG_MMIO, 0x1771, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED30", REG_MMIO, 0x1772, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED31", REG_MMIO, 0x1773, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED32", REG_MMIO, 0x1774, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_DEBUG0", REG_MMIO, 0x1774, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED33", REG_MMIO, 0x1775, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0", REG_MMIO, 0x1775, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED34", REG_MMIO, 0x1776, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE1", REG_MMIO, 0x1776, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED35", REG_MMIO, 0x1777, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED36", REG_MMIO, 0x1778, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_OBSERVE0_OUT", REG_MMIO, 0x1779, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED37", REG_MMIO, 0x1779, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG1", REG_MMIO, 0x177a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED38", REG_MMIO, 0x177a, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_DEBUG_MUX_CNTL", REG_MMIO, 0x177b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED39", REG_MMIO, 0x177b, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_DIV_UPDATE_DEBUG", REG_MMIO, 0x177c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED40", REG_MMIO, 0x177c, NULL, 0, 0, 0 },
+	{ "mmDC_DISPLAYPLLREGS2_PPLL_STATUS_DEBUG0", REG_MMIO, 0x177d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_MACRO_CNTL_RESERVED41", REG_MMIO, 0x177d, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x178, NULL, 0, 0, 0 },
+	{ "mmPERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x178, &mmPERFMON_TEST_DEBUG_DATA[0], sizeof(mmPERFMON_TEST_DEBUG_DATA)/sizeof(mmPERFMON_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZF0STREAM0_AZALIA_STREAM_INDEX", REG_MMIO, 0x1780, NULL, 0, 0, 0 },
+	{ "mmAZALIA_STREAM_INDEX", REG_MMIO, 0x1780, &mmAZALIA_STREAM_INDEX[0], sizeof(mmAZALIA_STREAM_INDEX)/sizeof(mmAZALIA_STREAM_INDEX[0]), 0, 0 },
+	{ "mmAZF0STREAM0_AZALIA_STREAM_DATA", REG_MMIO, 0x1781, NULL, 0, 0, 0 },
+	{ "mmAZALIA_STREAM_DATA", REG_MMIO, 0x1781, &mmAZALIA_STREAM_DATA[0], sizeof(mmAZALIA_STREAM_DATA)/sizeof(mmAZALIA_STREAM_DATA[0]), 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_INDEX", REG_MMIO, 0x1782, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_DATA", REG_MMIO, 0x1783, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_INDEX", REG_MMIO, 0x1784, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_DATA", REG_MMIO, 0x1785, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_INDEX", REG_MMIO, 0x1786, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_DATA", REG_MMIO, 0x1787, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_INDEX", REG_MMIO, 0x1788, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_DATA", REG_MMIO, 0x1789, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_INDEX", REG_MMIO, 0x178a, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_DATA", REG_MMIO, 0x178b, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM6_AZALIA_STREAM_INDEX", REG_MMIO, 0x178c, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM6_AZALIA_STREAM_DATA", REG_MMIO, 0x178d, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM7_AZALIA_STREAM_INDEX", REG_MMIO, 0x178e, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM7_AZALIA_STREAM_DATA", REG_MMIO, 0x178f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CNTL2", REG_MMIO, 0x17a, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CNTL2", REG_MMIO, 0x17a, &mmPERFMON_CNTL2[0], sizeof(mmPERFMON_CNTL2)/sizeof(mmPERFMON_CNTL2[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17a8, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17a8, &mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17a9, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17a9, &mmAZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17ac, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17ad, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b0, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b1, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b4, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b5, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17b8, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17b9, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17bc, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17bd, NULL, 0, 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_INDEX", REG_MMIO, 0x17c, &mmDCCG_TEST_DEBUG_INDEX[0], sizeof(mmDCCG_TEST_DEBUG_INDEX)/sizeof(mmDCCG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17c0, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17c1, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17c4, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17c5, NULL, 0, 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_DATA", REG_MMIO, 0x17d, &mmDCCG_TEST_DEBUG_DATA[0], sizeof(mmDCCG_TEST_DEBUG_DATA)/sizeof(mmDCCG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCCG_TEST_CLK_SEL", REG_MMIO, 0x17e, &mmDCCG_TEST_CLK_SEL[0], sizeof(mmDCCG_TEST_CLK_SEL)/sizeof(mmDCCG_TEST_CLK_SEL[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_CLOCK_GATING", REG_MMIO, 0x17e4, &mmAZALIA_CONTROLLER_CLOCK_GATING[0], sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING)/sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO", REG_MMIO, 0x17e5, &mmAZALIA_AUDIO_DTO[0], sizeof(mmAZALIA_AUDIO_DTO)/sizeof(mmAZALIA_AUDIO_DTO[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO_CONTROL", REG_MMIO, 0x17e6, &mmAZALIA_AUDIO_DTO_CONTROL[0], sizeof(mmAZALIA_AUDIO_DTO_CONTROL)/sizeof(mmAZALIA_AUDIO_DTO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_SCLK_CONTROL", REG_MMIO, 0x17e7, &mmAZALIA_SCLK_CONTROL[0], sizeof(mmAZALIA_SCLK_CONTROL)/sizeof(mmAZALIA_SCLK_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_UNDERFLOW_FILLER_SAMPLE", REG_MMIO, 0x17e8, &mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0], sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE)/sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0]), 0, 0 },
+	{ "mmAZALIA_DATA_DMA_CONTROL", REG_MMIO, 0x17e9, &mmAZALIA_DATA_DMA_CONTROL[0], sizeof(mmAZALIA_DATA_DMA_CONTROL)/sizeof(mmAZALIA_DATA_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_BDL_DMA_CONTROL", REG_MMIO, 0x17ea, &mmAZALIA_BDL_DMA_CONTROL[0], sizeof(mmAZALIA_BDL_DMA_CONTROL)/sizeof(mmAZALIA_BDL_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_RIRB_AND_DP_CONTROL", REG_MMIO, 0x17eb, &mmAZALIA_RIRB_AND_DP_CONTROL[0], sizeof(mmAZALIA_RIRB_AND_DP_CONTROL)/sizeof(mmAZALIA_RIRB_AND_DP_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_CORB_DMA_CONTROL", REG_MMIO, 0x17ec, &mmAZALIA_CORB_DMA_CONTROL[0], sizeof(mmAZALIA_CORB_DMA_CONTROL)/sizeof(mmAZALIA_CORB_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER", REG_MMIO, 0x17f3, &mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0], sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER)/sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0]), 0, 0 },
+	{ "mmAZALIA_CYCLIC_BUFFER_SYNC", REG_MMIO, 0x17f4, &mmAZALIA_CYCLIC_BUFFER_SYNC[0], sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC)/sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC[0]), 0, 0 },
+	{ "mmAZALIA_GLOBAL_CAPABILITIES", REG_MMIO, 0x17f5, &mmAZALIA_GLOBAL_CAPABILITIES[0], sizeof(mmAZALIA_GLOBAL_CAPABILITIES)/sizeof(mmAZALIA_GLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x17f6, &mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL", REG_MMIO, 0x17f7, &mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0], sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL)/sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x17f8, &mmAZALIA_INPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_INPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_INPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_DEBUG", REG_MMIO, 0x17f9, &mmAZALIA_CONTROLLER_DEBUG[0], sizeof(mmAZALIA_CONTROLLER_DEBUG)/sizeof(mmAZALIA_CONTROLLER_DEBUG[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL0", REG_MMIO, 0x17fb, &mmAZALIA_INPUT_CRC0_CONTROL0[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL0)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL1", REG_MMIO, 0x17fc, &mmAZALIA_INPUT_CRC0_CONTROL1[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL1)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL2", REG_MMIO, 0x17fd, &mmAZALIA_INPUT_CRC0_CONTROL2[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL2)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_CONTROL3", REG_MMIO, 0x17fe, &mmAZALIA_INPUT_CRC0_CONTROL3[0], sizeof(mmAZALIA_INPUT_CRC0_CONTROL3)/sizeof(mmAZALIA_INPUT_CRC0_CONTROL3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET", REG_SMC, 0x17ff, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC0_RESULT", REG_MMIO, 0x17ff, &mmAZALIA_INPUT_CRC0_RESULT[0], sizeof(mmAZALIA_INPUT_CRC0_RESULT)/sizeof(mmAZALIA_INPUT_CRC0_RESULT[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_I", REG_SMC, 0x18, &ixDP_AUX_DEBUG_I[0], sizeof(ixDP_AUX_DEBUG_I)/sizeof(ixDP_AUX_DEBUG_I[0]), 0, 0 },
+	{ "ixDCIO_DEBUG18", REG_SMC, 0x18, &ixDCIO_DEBUG18[0], sizeof(ixDCIO_DEBUG18)/sizeof(ixDCIO_DEBUG18[0]), 0, 0 },
+	{ "ixCRT18", REG_SMC, 0x18, &ixCRT18[0], sizeof(ixCRT18)/sizeof(ixCRT18[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL0", REG_MMIO, 0x1800, &mmAZALIA_INPUT_CRC1_CONTROL0[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL0)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL1", REG_MMIO, 0x1801, &mmAZALIA_INPUT_CRC1_CONTROL1[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL1)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL2", REG_MMIO, 0x1802, &mmAZALIA_INPUT_CRC1_CONTROL2[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL2)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_CONTROL3", REG_MMIO, 0x1803, &mmAZALIA_INPUT_CRC1_CONTROL3[0], sizeof(mmAZALIA_INPUT_CRC1_CONTROL3)/sizeof(mmAZALIA_INPUT_CRC1_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_INPUT_CRC1_RESULT", REG_MMIO, 0x1804, &mmAZALIA_INPUT_CRC1_RESULT[0], sizeof(mmAZALIA_INPUT_CRC1_RESULT)/sizeof(mmAZALIA_INPUT_CRC1_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL0", REG_MMIO, 0x1805, &mmAZALIA_CRC0_CONTROL0[0], sizeof(mmAZALIA_CRC0_CONTROL0)/sizeof(mmAZALIA_CRC0_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL1", REG_MMIO, 0x1806, &mmAZALIA_CRC0_CONTROL1[0], sizeof(mmAZALIA_CRC0_CONTROL1)/sizeof(mmAZALIA_CRC0_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL2", REG_MMIO, 0x1807, &mmAZALIA_CRC0_CONTROL2[0], sizeof(mmAZALIA_CRC0_CONTROL2)/sizeof(mmAZALIA_CRC0_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL3", REG_MMIO, 0x1808, &mmAZALIA_CRC0_CONTROL3[0], sizeof(mmAZALIA_CRC0_CONTROL3)/sizeof(mmAZALIA_CRC0_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_RESULT", REG_MMIO, 0x1809, &mmAZALIA_CRC0_RESULT[0], sizeof(mmAZALIA_CRC0_RESULT)/sizeof(mmAZALIA_CRC0_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL0", REG_MMIO, 0x180a, &mmAZALIA_CRC1_CONTROL0[0], sizeof(mmAZALIA_CRC1_CONTROL0)/sizeof(mmAZALIA_CRC1_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL1", REG_MMIO, 0x180b, &mmAZALIA_CRC1_CONTROL1[0], sizeof(mmAZALIA_CRC1_CONTROL1)/sizeof(mmAZALIA_CRC1_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL2", REG_MMIO, 0x180c, &mmAZALIA_CRC1_CONTROL2[0], sizeof(mmAZALIA_CRC1_CONTROL2)/sizeof(mmAZALIA_CRC1_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL3", REG_MMIO, 0x180d, &mmAZALIA_CRC1_CONTROL3[0], sizeof(mmAZALIA_CRC1_CONTROL3)/sizeof(mmAZALIA_CRC1_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_RESULT", REG_MMIO, 0x180e, &mmAZALIA_CRC1_RESULT[0], sizeof(mmAZALIA_CRC1_RESULT)/sizeof(mmAZALIA_CRC1_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_MEM_PWR_CTRL", REG_MMIO, 0x1810, &mmAZALIA_MEM_PWR_CTRL[0], sizeof(mmAZALIA_MEM_PWR_CTRL)/sizeof(mmAZALIA_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmAZALIA_MEM_PWR_STATUS", REG_MMIO, 0x1811, &mmAZALIA_MEM_PWR_STATUS[0], sizeof(mmAZALIA_MEM_PWR_STATUS)/sizeof(mmAZALIA_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCI_PG_DEBUG_CONFIG", REG_MMIO, 0x1812, &mmDCI_PG_DEBUG_CONFIG[0], sizeof(mmDCI_PG_DEBUG_CONFIG)/sizeof(mmDCI_PG_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_INDEX", REG_MMIO, 0x181f, &mmAZ_TEST_DEBUG_INDEX[0], sizeof(mmAZ_TEST_DEBUG_INDEX)/sizeof(mmAZ_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_DATA", REG_MMIO, 0x1820, &mmAZ_TEST_DEBUG_DATA[0], sizeof(mmAZ_TEST_DEBUG_DATA)/sizeof(mmAZ_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_MMIO, 0x1828, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID", REG_MMIO, 0x1829, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL", REG_MMIO, 0x182a, &mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL)/sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL", REG_MMIO, 0x182b, &mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL)/sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_MMIO, 0x182c, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_MMIO, 0x182d, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_MMIO, 0x182e, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_MMIO, 0x182f, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_MMIO, 0x1830, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET", REG_MMIO, 0x1831, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_MMIO, 0x1832, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_MMIO, 0x1833, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY", REG_MMIO, 0x1834, &mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0]), 0, 0 },
+	{ "mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY", REG_MMIO, 0x1835, &mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_DEBUG", REG_MMIO, 0x1836, &mmAZALIA_F0_CODEC_DEBUG[0], sizeof(mmAZALIA_F0_CODEC_DEBUG)/sizeof(mmAZALIA_F0_CODEC_DEBUG[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET0", REG_MMIO, 0x1837, &mmAZALIA_F0_GTC_GROUP_OFFSET0[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET1", REG_MMIO, 0x1838, &mmAZALIA_F0_GTC_GROUP_OFFSET1[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET2", REG_MMIO, 0x1839, &mmAZALIA_F0_GTC_GROUP_OFFSET2[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET3", REG_MMIO, 0x183a, &mmAZALIA_F0_GTC_GROUP_OFFSET3[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET4", REG_MMIO, 0x183b, &mmAZALIA_F0_GTC_GROUP_OFFSET4[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET5", REG_MMIO, 0x183c, &mmAZALIA_F0_GTC_GROUP_OFFSET5[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET6", REG_MMIO, 0x183d, &mmAZALIA_F0_GTC_GROUP_OFFSET6[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6[0]), 0, 0 },
+	{ "mmDCO_SCRATCH0", REG_MMIO, 0x184e, &mmDCO_SCRATCH0[0], sizeof(mmDCO_SCRATCH0)/sizeof(mmDCO_SCRATCH0[0]), 0, 0 },
+	{ "mmDCO_SCRATCH1", REG_MMIO, 0x184f, &mmDCO_SCRATCH1[0], sizeof(mmDCO_SCRATCH1)/sizeof(mmDCO_SCRATCH1[0]), 0, 0 },
+	{ "mmDCO_SCRATCH2", REG_MMIO, 0x1850, &mmDCO_SCRATCH2[0], sizeof(mmDCO_SCRATCH2)/sizeof(mmDCO_SCRATCH2[0]), 0, 0 },
+	{ "mmDCO_SCRATCH3", REG_MMIO, 0x1851, &mmDCO_SCRATCH3[0], sizeof(mmDCO_SCRATCH3)/sizeof(mmDCO_SCRATCH3[0]), 0, 0 },
+	{ "mmDCO_SCRATCH4", REG_MMIO, 0x1852, &mmDCO_SCRATCH4[0], sizeof(mmDCO_SCRATCH4)/sizeof(mmDCO_SCRATCH4[0]), 0, 0 },
+	{ "mmDCO_SCRATCH5", REG_MMIO, 0x1853, &mmDCO_SCRATCH5[0], sizeof(mmDCO_SCRATCH5)/sizeof(mmDCO_SCRATCH5[0]), 0, 0 },
+	{ "mmDCO_SCRATCH6", REG_MMIO, 0x1854, &mmDCO_SCRATCH6[0], sizeof(mmDCO_SCRATCH6)/sizeof(mmDCO_SCRATCH6[0]), 0, 0 },
+	{ "mmDCO_SCRATCH7", REG_MMIO, 0x1855, &mmDCO_SCRATCH7[0], sizeof(mmDCO_SCRATCH7)/sizeof(mmDCO_SCRATCH7[0]), 0, 0 },
+	{ "mmDCE_VCE_CONTROL", REG_MMIO, 0x1856, &mmDCE_VCE_CONTROL[0], sizeof(mmDCE_VCE_CONTROL)/sizeof(mmDCE_VCE_CONTROL[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS", REG_MMIO, 0x1857, &mmDISP_INTERRUPT_STATUS[0], sizeof(mmDISP_INTERRUPT_STATUS)/sizeof(mmDISP_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE", REG_MMIO, 0x1858, &mmDISP_INTERRUPT_STATUS_CONTINUE[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE2", REG_MMIO, 0x1859, &mmDISP_INTERRUPT_STATUS_CONTINUE2[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE3", REG_MMIO, 0x185a, &mmDISP_INTERRUPT_STATUS_CONTINUE3[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE4", REG_MMIO, 0x185b, &mmDISP_INTERRUPT_STATUS_CONTINUE4[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE5", REG_MMIO, 0x185c, &mmDISP_INTERRUPT_STATUS_CONTINUE5[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE6", REG_MMIO, 0x185d, &mmDISP_INTERRUPT_STATUS_CONTINUE6[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE7", REG_MMIO, 0x185e, &mmDISP_INTERRUPT_STATUS_CONTINUE7[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE8", REG_MMIO, 0x185f, &mmDISP_INTERRUPT_STATUS_CONTINUE8[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE9", REG_MMIO, 0x1860, &mmDISP_INTERRUPT_STATUS_CONTINUE9[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_STATUS", REG_MMIO, 0x1861, &mmDCO_MEM_PWR_STATUS[0], sizeof(mmDCO_MEM_PWR_STATUS)/sizeof(mmDCO_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_CTRL", REG_MMIO, 0x1862, &mmDCO_MEM_PWR_CTRL[0], sizeof(mmDCO_MEM_PWR_CTRL)/sizeof(mmDCO_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_CTRL2", REG_MMIO, 0x1863, &mmDCO_MEM_PWR_CTRL2[0], sizeof(mmDCO_MEM_PWR_CTRL2)/sizeof(mmDCO_MEM_PWR_CTRL2[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL", REG_MMIO, 0x1864, &mmDCO_CLK_CNTL[0], sizeof(mmDCO_CLK_CNTL)/sizeof(mmDCO_CLK_CNTL[0]), 0, 0 },
+	{ "mmDPDBG_CNTL", REG_MMIO, 0x1866, &mmDPDBG_CNTL[0], sizeof(mmDPDBG_CNTL)/sizeof(mmDPDBG_CNTL[0]), 0, 0 },
+	{ "mmDPDBG_INTERRUPT", REG_MMIO, 0x1867, &mmDPDBG_INTERRUPT[0], sizeof(mmDPDBG_INTERRUPT)/sizeof(mmDPDBG_INTERRUPT[0]), 0, 0 },
+	{ "mmDCO_POWER_MANAGEMENT_CNTL", REG_MMIO, 0x1868, &mmDCO_POWER_MANAGEMENT_CNTL[0], sizeof(mmDCO_POWER_MANAGEMENT_CNTL)/sizeof(mmDCO_POWER_MANAGEMENT_CNTL[0]), 0, 0 },
+	{ "mmDIG_SOFT_RESET_2", REG_MMIO, 0x186a, &mmDIG_SOFT_RESET_2[0], sizeof(mmDIG_SOFT_RESET_2)/sizeof(mmDIG_SOFT_RESET_2[0]), 0, 0 },
+	{ "mmDCO_STEREOSYNC_SEL", REG_MMIO, 0x186e, &mmDCO_STEREOSYNC_SEL[0], sizeof(mmDCO_STEREOSYNC_SEL)/sizeof(mmDCO_STEREOSYNC_SEL[0]), 0, 0 },
+	{ "mmDCO_TEST_DEBUG_INDEX", REG_MMIO, 0x186f, &mmDCO_TEST_DEBUG_INDEX[0], sizeof(mmDCO_TEST_DEBUG_INDEX)/sizeof(mmDCO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCO_TEST_DEBUG_DATA", REG_MMIO, 0x1870, &mmDCO_TEST_DEBUG_DATA[0], sizeof(mmDCO_TEST_DEBUG_DATA)/sizeof(mmDCO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCO_SOFT_RESET", REG_MMIO, 0x1871, &mmDCO_SOFT_RESET[0], sizeof(mmDCO_SOFT_RESET)/sizeof(mmDCO_SOFT_RESET[0]), 0, 0 },
+	{ "mmDIG_SOFT_RESET", REG_MMIO, 0x1872, &mmDIG_SOFT_RESET[0], sizeof(mmDIG_SOFT_RESET)/sizeof(mmDIG_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCO_MEM_PWR_STATUS1", REG_MMIO, 0x1874, &mmDCO_MEM_PWR_STATUS1[0], sizeof(mmDCO_MEM_PWR_STATUS1)/sizeof(mmDCO_MEM_PWR_STATUS1[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE10", REG_MMIO, 0x1875, &mmDISP_INTERRUPT_STATUS_CONTINUE10[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE10)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE10[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL2", REG_MMIO, 0x1876, &mmDCO_CLK_CNTL2[0], sizeof(mmDCO_CLK_CNTL2)/sizeof(mmDCO_CLK_CNTL2[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL3", REG_MMIO, 0x1877, &mmDCO_CLK_CNTL3[0], sizeof(mmDCO_CLK_CNTL3)/sizeof(mmDCO_CLK_CNTL3[0]), 0, 0 },
+	{ "mmDCO_HDMI_RXSTATUS_TIMER_CONTROL", REG_MMIO, 0x1883, &mmDCO_HDMI_RXSTATUS_TIMER_CONTROL[0], sizeof(mmDCO_HDMI_RXSTATUS_TIMER_CONTROL)/sizeof(mmDCO_HDMI_RXSTATUS_TIMER_CONTROL[0]), 0, 0 },
+	{ "mmDCO_PSP_INTERRUPT_STATUS", REG_MMIO, 0x1884, &mmDCO_PSP_INTERRUPT_STATUS[0], sizeof(mmDCO_PSP_INTERRUPT_STATUS)/sizeof(mmDCO_PSP_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDCO_PSP_INTERRUPT_CLEAR", REG_MMIO, 0x1885, &mmDCO_PSP_INTERRUPT_CLEAR[0], sizeof(mmDCO_PSP_INTERRUPT_CLEAR)/sizeof(mmDCO_PSP_INTERRUPT_CLEAR[0]), 0, 0 },
+	{ "mmDCO_GENERIC_INTERRUPT_MESSAGE", REG_MMIO, 0x1886, &mmDCO_GENERIC_INTERRUPT_MESSAGE[0], sizeof(mmDCO_GENERIC_INTERRUPT_MESSAGE)/sizeof(mmDCO_GENERIC_INTERRUPT_MESSAGE[0]), 0, 0 },
+	{ "mmDCO_GENERIC_INTERRUPT_CLEAR", REG_MMIO, 0x1887, &mmDCO_GENERIC_INTERRUPT_CLEAR[0], sizeof(mmDCO_GENERIC_INTERRUPT_CLEAR)/sizeof(mmDCO_GENERIC_INTERRUPT_CLEAR[0]), 0, 0 },
+	{ "mmFMT_MEMORY0_CONTROL", REG_MMIO, 0x1888, &mmFMT_MEMORY0_CONTROL[0], sizeof(mmFMT_MEMORY0_CONTROL)/sizeof(mmFMT_MEMORY0_CONTROL[0]), 0, 0 },
+	{ "mmFMT_MEMORY1_CONTROL", REG_MMIO, 0x1889, &mmFMT_MEMORY1_CONTROL[0], sizeof(mmFMT_MEMORY1_CONTROL)/sizeof(mmFMT_MEMORY1_CONTROL[0]), 0, 0 },
+	{ "mmFMT_MEMORY2_CONTROL", REG_MMIO, 0x188a, &mmFMT_MEMORY2_CONTROL[0], sizeof(mmFMT_MEMORY2_CONTROL)/sizeof(mmFMT_MEMORY2_CONTROL[0]), 0, 0 },
+	{ "mmFMT_MEMORY3_CONTROL", REG_MMIO, 0x188b, &mmFMT_MEMORY3_CONTROL[0], sizeof(mmFMT_MEMORY3_CONTROL)/sizeof(mmFMT_MEMORY3_CONTROL[0]), 0, 0 },
+	{ "mmFMT_MEMORY4_CONTROL", REG_MMIO, 0x188c, &mmFMT_MEMORY4_CONTROL[0], sizeof(mmFMT_MEMORY4_CONTROL)/sizeof(mmFMT_MEMORY4_CONTROL[0]), 0, 0 },
+	{ "mmFMT_MEMORY5_CONTROL", REG_MMIO, 0x188d, &mmFMT_MEMORY5_CONTROL[0], sizeof(mmFMT_MEMORY5_CONTROL)/sizeof(mmFMT_MEMORY5_CONTROL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_INT_STATUS", REG_MMIO, 0x1898, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_INT_STATUS", REG_MMIO, 0x1898, &mmDC_HPD_INT_STATUS[0], sizeof(mmDC_HPD_INT_STATUS)/sizeof(mmDC_HPD_INT_STATUS[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_INT_CONTROL", REG_MMIO, 0x1899, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_INT_CONTROL", REG_MMIO, 0x1899, &mmDC_HPD_INT_CONTROL[0], sizeof(mmDC_HPD_INT_CONTROL)/sizeof(mmDC_HPD_INT_CONTROL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_CONTROL", REG_MMIO, 0x189a, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_CONTROL", REG_MMIO, 0x189a, &mmDC_HPD_CONTROL[0], sizeof(mmDC_HPD_CONTROL)/sizeof(mmDC_HPD_CONTROL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x189b, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x189b, &mmDC_HPD_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmHPD0_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x189c, NULL, 0, 0, 0 },
+	{ "mmDC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x189c, &mmDC_HPD_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmHPD1_DC_HPD_INT_STATUS", REG_MMIO, 0x18a0, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_INT_CONTROL", REG_MMIO, 0x18a1, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_CONTROL", REG_MMIO, 0x18a2, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18a3, NULL, 0, 0, 0 },
+	{ "mmHPD1_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18a4, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_INT_STATUS", REG_MMIO, 0x18a8, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_INT_CONTROL", REG_MMIO, 0x18a9, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_CONTROL", REG_MMIO, 0x18aa, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18ab, NULL, 0, 0, 0 },
+	{ "mmHPD2_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18ac, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_INT_STATUS", REG_MMIO, 0x18b0, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_INT_CONTROL", REG_MMIO, 0x18b1, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_CONTROL", REG_MMIO, 0x18b2, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18b3, NULL, 0, 0, 0 },
+	{ "mmHPD3_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18b4, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_INT_STATUS", REG_MMIO, 0x18b8, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_INT_CONTROL", REG_MMIO, 0x18b9, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_CONTROL", REG_MMIO, 0x18ba, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18bb, NULL, 0, 0, 0 },
+	{ "mmHPD4_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18bc, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_INT_STATUS", REG_MMIO, 0x18c0, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_INT_CONTROL", REG_MMIO, 0x18c1, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_CONTROL", REG_MMIO, 0x18c2, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_FAST_TRAIN_CNTL", REG_MMIO, 0x18c3, NULL, 0, 0, 0 },
+	{ "mmHPD5_DC_HPD_TOGGLE_FILT_CNTL", REG_MMIO, 0x18c4, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFCOUNTER_CNTL", REG_MMIO, 0x18c8, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFCOUNTER_STATE", REG_MMIO, 0x18c9, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x18ca, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CNTL", REG_MMIO, 0x18cb, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CVALUE_LOW", REG_MMIO, 0x18cc, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_HI", REG_MMIO, 0x18cd, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_LOW", REG_MMIO, 0x18ce, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x18cf, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x18d0, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CNTL2", REG_MMIO, 0x18d2, NULL, 0, 0, 0 },
+	{ "mmIMMEDIATE_RESPONSE_INPUT_INTERFACE", REG_MMIO, 0x19, &mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0], sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE)/sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_J", REG_SMC, 0x19, &ixDP_AUX_DEBUG_J[0], sizeof(ixDP_AUX_DEBUG_J)/sizeof(ixDP_AUX_DEBUG_J[0]), 0, 0 },
+	{ "ixDCIO_DEBUG19", REG_SMC, 0x19, &ixDCIO_DEBUG19[0], sizeof(ixDCIO_DEBUG19)/sizeof(ixDCIO_DEBUG19[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_STATUS", REG_MMIO, 0x1a, &mmIMMEDIATE_COMMAND_STATUS[0], sizeof(mmIMMEDIATE_COMMAND_STATUS)/sizeof(mmIMMEDIATE_COMMAND_STATUS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_K", REG_SMC, 0x1a, &ixDP_AUX_DEBUG_K[0], sizeof(ixDP_AUX_DEBUG_K)/sizeof(ixDP_AUX_DEBUG_K[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1A", REG_SMC, 0x1a, &ixDCIO_DEBUG1A[0], sizeof(ixDCIO_DEBUG1A)/sizeof(ixDCIO_DEBUG1A[0]), 0, 0 },
+	{ "mmDCP0_GRPH_ENABLE", REG_MMIO, 0x1a00, NULL, 0, 0, 0 },
+	{ "mmGRPH_ENABLE", REG_MMIO, 0x1a00, &mmGRPH_ENABLE[0], sizeof(mmGRPH_ENABLE)/sizeof(mmGRPH_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_CONTROL", REG_MMIO, 0x1a01, NULL, 0, 0, 0 },
+	{ "mmGRPH_CONTROL", REG_MMIO, 0x1a01, &mmGRPH_CONTROL[0], sizeof(mmGRPH_CONTROL)/sizeof(mmGRPH_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1a02, NULL, 0, 0, 0 },
+	{ "mmGRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1a02, &mmGRPH_LUT_10BIT_BYPASS[0], sizeof(mmGRPH_LUT_10BIT_BYPASS)/sizeof(mmGRPH_LUT_10BIT_BYPASS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SWAP_CNTL", REG_MMIO, 0x1a03, NULL, 0, 0, 0 },
+	{ "mmGRPH_SWAP_CNTL", REG_MMIO, 0x1a03, &mmGRPH_SWAP_CNTL[0], sizeof(mmGRPH_SWAP_CNTL)/sizeof(mmGRPH_SWAP_CNTL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1a04, NULL, 0, 0, 0 },
+	{ "mmGRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1a04, &mmGRPH_PRIMARY_SURFACE_ADDRESS[0], sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS)/sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a05, NULL, 0, 0, 0 },
+	{ "mmGRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a05, &mmGRPH_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS)/sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PITCH", REG_MMIO, 0x1a06, NULL, 0, 0, 0 },
+	{ "mmGRPH_PITCH", REG_MMIO, 0x1a06, &mmGRPH_PITCH[0], sizeof(mmGRPH_PITCH)/sizeof(mmGRPH_PITCH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a07, NULL, 0, 0, 0 },
+	{ "mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a07, &mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a08, NULL, 0, 0, 0 },
+	{ "mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a08, &mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1a09, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1a09, &mmGRPH_SURFACE_OFFSET_X[0], sizeof(mmGRPH_SURFACE_OFFSET_X)/sizeof(mmGRPH_SURFACE_OFFSET_X[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1a0a, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1a0a, &mmGRPH_SURFACE_OFFSET_Y[0], sizeof(mmGRPH_SURFACE_OFFSET_Y)/sizeof(mmGRPH_SURFACE_OFFSET_Y[0]), 0, 0 },
+	{ "mmDCP0_GRPH_X_START", REG_MMIO, 0x1a0b, NULL, 0, 0, 0 },
+	{ "mmGRPH_X_START", REG_MMIO, 0x1a0b, &mmGRPH_X_START[0], sizeof(mmGRPH_X_START)/sizeof(mmGRPH_X_START[0]), 0, 0 },
+	{ "mmDCP0_GRPH_Y_START", REG_MMIO, 0x1a0c, NULL, 0, 0, 0 },
+	{ "mmGRPH_Y_START", REG_MMIO, 0x1a0c, &mmGRPH_Y_START[0], sizeof(mmGRPH_Y_START)/sizeof(mmGRPH_Y_START[0]), 0, 0 },
+	{ "mmDCP0_GRPH_X_END", REG_MMIO, 0x1a0d, NULL, 0, 0, 0 },
+	{ "mmGRPH_X_END", REG_MMIO, 0x1a0d, &mmGRPH_X_END[0], sizeof(mmGRPH_X_END)/sizeof(mmGRPH_X_END[0]), 0, 0 },
+	{ "mmDCP0_GRPH_Y_END", REG_MMIO, 0x1a0e, NULL, 0, 0, 0 },
+	{ "mmGRPH_Y_END", REG_MMIO, 0x1a0e, &mmGRPH_Y_END[0], sizeof(mmGRPH_Y_END)/sizeof(mmGRPH_Y_END[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x1a0f, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x1a0f, &mmGRPH_SURFACE_COUNTER_CONTROL[0], sizeof(mmGRPH_SURFACE_COUNTER_CONTROL)/sizeof(mmGRPH_SURFACE_COUNTER_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1a10, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_CONTROL", REG_MMIO, 0x1a10, &mmINPUT_GAMMA_CONTROL[0], sizeof(mmINPUT_GAMMA_CONTROL)/sizeof(mmINPUT_GAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_UPDATE", REG_MMIO, 0x1a11, NULL, 0, 0, 0 },
+	{ "mmGRPH_UPDATE", REG_MMIO, 0x1a11, &mmGRPH_UPDATE[0], sizeof(mmGRPH_UPDATE)/sizeof(mmGRPH_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_CONTROL", REG_MMIO, 0x1a12, NULL, 0, 0, 0 },
+	{ "mmGRPH_FLIP_CONTROL", REG_MMIO, 0x1a12, &mmGRPH_FLIP_CONTROL[0], sizeof(mmGRPH_FLIP_CONTROL)/sizeof(mmGRPH_FLIP_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a13, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a13, &mmGRPH_SURFACE_ADDRESS_INUSE[0], sizeof(mmGRPH_SURFACE_ADDRESS_INUSE)/sizeof(mmGRPH_SURFACE_ADDRESS_INUSE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_CONTROL", REG_MMIO, 0x1a14, NULL, 0, 0, 0 },
+	{ "mmGRPH_DFQ_CONTROL", REG_MMIO, 0x1a14, &mmGRPH_DFQ_CONTROL[0], sizeof(mmGRPH_DFQ_CONTROL)/sizeof(mmGRPH_DFQ_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_STATUS", REG_MMIO, 0x1a15, NULL, 0, 0, 0 },
+	{ "mmGRPH_DFQ_STATUS", REG_MMIO, 0x1a15, &mmGRPH_DFQ_STATUS[0], sizeof(mmGRPH_DFQ_STATUS)/sizeof(mmGRPH_DFQ_STATUS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1a16, NULL, 0, 0, 0 },
+	{ "mmGRPH_INTERRUPT_STATUS", REG_MMIO, 0x1a16, &mmGRPH_INTERRUPT_STATUS[0], sizeof(mmGRPH_INTERRUPT_STATUS)/sizeof(mmGRPH_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1a17, NULL, 0, 0, 0 },
+	{ "mmGRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1a17, &mmGRPH_INTERRUPT_CONTROL[0], sizeof(mmGRPH_INTERRUPT_CONTROL)/sizeof(mmGRPH_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a18, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a18, &mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[0], sizeof(mmGRPH_SURFACE_ADDRESS_HIGH_INUSE)/sizeof(mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1a19, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1a19, &mmGRPH_COMPRESS_SURFACE_ADDRESS[0], sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS)/sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1a1a, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_PITCH", REG_MMIO, 0x1a1a, &mmGRPH_COMPRESS_PITCH[0], sizeof(mmGRPH_COMPRESS_PITCH)/sizeof(mmGRPH_COMPRESS_PITCH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a1b, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a1b, &mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x1a1c, NULL, 0, 0, 0 },
+	{ "mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x1a1c, &mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT[0], sizeof(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT)/sizeof(mmGRPH_PIPE_OUTSTANDING_REQUEST_LIMIT[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x1a1d, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x1a1d, &mmGRPH_SURFACE_COUNTER_OUTPUT[0], sizeof(mmGRPH_SURFACE_COUNTER_OUTPUT)/sizeof(mmGRPH_SURFACE_COUNTER_OUTPUT[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1a2d, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_GRPH_CONTROL", REG_MMIO, 0x1a2d, &mmPRESCALE_GRPH_CONTROL[0], sizeof(mmPRESCALE_GRPH_CONTROL)/sizeof(mmPRESCALE_GRPH_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1a2e, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1a2e, &mmPRESCALE_VALUES_GRPH_R[0], sizeof(mmPRESCALE_VALUES_GRPH_R)/sizeof(mmPRESCALE_VALUES_GRPH_R[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1a2f, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1a2f, &mmPRESCALE_VALUES_GRPH_G[0], sizeof(mmPRESCALE_VALUES_GRPH_G)/sizeof(mmPRESCALE_VALUES_GRPH_G[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1a30, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1a30, &mmPRESCALE_VALUES_GRPH_B[0], sizeof(mmPRESCALE_VALUES_GRPH_B)/sizeof(mmPRESCALE_VALUES_GRPH_B[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_CONTROL", REG_MMIO, 0x1a35, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_CONTROL", REG_MMIO, 0x1a35, &mmINPUT_CSC_CONTROL[0], sizeof(mmINPUT_CSC_CONTROL)/sizeof(mmINPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C11_C12", REG_MMIO, 0x1a36, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C11_C12", REG_MMIO, 0x1a36, &mmINPUT_CSC_C11_C12[0], sizeof(mmINPUT_CSC_C11_C12)/sizeof(mmINPUT_CSC_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C13_C14", REG_MMIO, 0x1a37, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C13_C14", REG_MMIO, 0x1a37, &mmINPUT_CSC_C13_C14[0], sizeof(mmINPUT_CSC_C13_C14)/sizeof(mmINPUT_CSC_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C21_C22", REG_MMIO, 0x1a38, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C21_C22", REG_MMIO, 0x1a38, &mmINPUT_CSC_C21_C22[0], sizeof(mmINPUT_CSC_C21_C22)/sizeof(mmINPUT_CSC_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C23_C24", REG_MMIO, 0x1a39, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C23_C24", REG_MMIO, 0x1a39, &mmINPUT_CSC_C23_C24[0], sizeof(mmINPUT_CSC_C23_C24)/sizeof(mmINPUT_CSC_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C31_C32", REG_MMIO, 0x1a3a, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C31_C32", REG_MMIO, 0x1a3a, &mmINPUT_CSC_C31_C32[0], sizeof(mmINPUT_CSC_C31_C32)/sizeof(mmINPUT_CSC_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C33_C34", REG_MMIO, 0x1a3b, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C33_C34", REG_MMIO, 0x1a3b, &mmINPUT_CSC_C33_C34[0], sizeof(mmINPUT_CSC_C33_C34)/sizeof(mmINPUT_CSC_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1a3c, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_CONTROL", REG_MMIO, 0x1a3c, &mmOUTPUT_CSC_CONTROL[0], sizeof(mmOUTPUT_CSC_CONTROL)/sizeof(mmOUTPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1a3d, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12", REG_MMIO, 0x1a3d, &mmOUTPUT_CSC_C11_C12[0], sizeof(mmOUTPUT_CSC_C11_C12)/sizeof(mmOUTPUT_CSC_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1a3e, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14", REG_MMIO, 0x1a3e, &mmOUTPUT_CSC_C13_C14[0], sizeof(mmOUTPUT_CSC_C13_C14)/sizeof(mmOUTPUT_CSC_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1a3f, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22", REG_MMIO, 0x1a3f, &mmOUTPUT_CSC_C21_C22[0], sizeof(mmOUTPUT_CSC_C21_C22)/sizeof(mmOUTPUT_CSC_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1a40, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24", REG_MMIO, 0x1a40, &mmOUTPUT_CSC_C23_C24[0], sizeof(mmOUTPUT_CSC_C23_C24)/sizeof(mmOUTPUT_CSC_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1a41, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32", REG_MMIO, 0x1a41, &mmOUTPUT_CSC_C31_C32[0], sizeof(mmOUTPUT_CSC_C31_C32)/sizeof(mmOUTPUT_CSC_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1a42, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34", REG_MMIO, 0x1a42, &mmOUTPUT_CSC_C33_C34[0], sizeof(mmOUTPUT_CSC_C33_C34)/sizeof(mmOUTPUT_CSC_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1a43, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1a43, &mmCOMM_MATRIXA_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXA_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXA_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1a44, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1a44, &mmCOMM_MATRIXA_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXA_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXA_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1a45, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1a45, &mmCOMM_MATRIXA_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXA_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXA_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1a46, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1a46, &mmCOMM_MATRIXA_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXA_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXA_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1a47, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1a47, &mmCOMM_MATRIXA_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXA_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXA_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1a48, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1a48, &mmCOMM_MATRIXA_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXA_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXA_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1a49, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1a49, &mmCOMM_MATRIXB_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXB_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXB_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1a4a, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1a4a, &mmCOMM_MATRIXB_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXB_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXB_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1a4b, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1a4b, &mmCOMM_MATRIXB_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXB_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXB_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1a4c, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1a4c, &mmCOMM_MATRIXB_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXB_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXB_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1a4d, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1a4d, &mmCOMM_MATRIXB_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXB_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXB_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1a4e, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1a4e, &mmCOMM_MATRIXB_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXB_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXB_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DENORM_CONTROL", REG_MMIO, 0x1a50, NULL, 0, 0, 0 },
+	{ "mmDENORM_CONTROL", REG_MMIO, 0x1a50, &mmDENORM_CONTROL[0], sizeof(mmDENORM_CONTROL)/sizeof(mmDENORM_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_ROUND_CONTROL", REG_MMIO, 0x1a51, NULL, 0, 0, 0 },
+	{ "mmOUT_ROUND_CONTROL", REG_MMIO, 0x1a51, &mmOUT_ROUND_CONTROL[0], sizeof(mmOUT_ROUND_CONTROL)/sizeof(mmOUT_ROUND_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1a52, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1a52, &mmOUT_CLAMP_CONTROL_R_CR[0], sizeof(mmOUT_CLAMP_CONTROL_R_CR)/sizeof(mmOUT_CLAMP_CONTROL_R_CR[0]), 0, 0 },
+	{ "mmDCP0_KEY_CONTROL", REG_MMIO, 0x1a53, NULL, 0, 0, 0 },
+	{ "mmKEY_CONTROL", REG_MMIO, 0x1a53, &mmKEY_CONTROL[0], sizeof(mmKEY_CONTROL)/sizeof(mmKEY_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_ALPHA", REG_MMIO, 0x1a54, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_ALPHA", REG_MMIO, 0x1a54, &mmKEY_RANGE_ALPHA[0], sizeof(mmKEY_RANGE_ALPHA)/sizeof(mmKEY_RANGE_ALPHA[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_RED", REG_MMIO, 0x1a55, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_RED", REG_MMIO, 0x1a55, &mmKEY_RANGE_RED[0], sizeof(mmKEY_RANGE_RED)/sizeof(mmKEY_RANGE_RED[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_GREEN", REG_MMIO, 0x1a56, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_GREEN", REG_MMIO, 0x1a56, &mmKEY_RANGE_GREEN[0], sizeof(mmKEY_RANGE_GREEN)/sizeof(mmKEY_RANGE_GREEN[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_BLUE", REG_MMIO, 0x1a57, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_BLUE", REG_MMIO, 0x1a57, &mmKEY_RANGE_BLUE[0], sizeof(mmKEY_RANGE_BLUE)/sizeof(mmKEY_RANGE_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DEGAMMA_CONTROL", REG_MMIO, 0x1a58, NULL, 0, 0, 0 },
+	{ "mmDEGAMMA_CONTROL", REG_MMIO, 0x1a58, &mmDEGAMMA_CONTROL[0], sizeof(mmDEGAMMA_CONTROL)/sizeof(mmDEGAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1a59, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_CONTROL", REG_MMIO, 0x1a59, &mmGAMUT_REMAP_CONTROL[0], sizeof(mmGAMUT_REMAP_CONTROL)/sizeof(mmGAMUT_REMAP_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1a5a, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C11_C12", REG_MMIO, 0x1a5a, &mmGAMUT_REMAP_C11_C12[0], sizeof(mmGAMUT_REMAP_C11_C12)/sizeof(mmGAMUT_REMAP_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1a5b, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C13_C14", REG_MMIO, 0x1a5b, &mmGAMUT_REMAP_C13_C14[0], sizeof(mmGAMUT_REMAP_C13_C14)/sizeof(mmGAMUT_REMAP_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1a5c, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C21_C22", REG_MMIO, 0x1a5c, &mmGAMUT_REMAP_C21_C22[0], sizeof(mmGAMUT_REMAP_C21_C22)/sizeof(mmGAMUT_REMAP_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1a5d, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C23_C24", REG_MMIO, 0x1a5d, &mmGAMUT_REMAP_C23_C24[0], sizeof(mmGAMUT_REMAP_C23_C24)/sizeof(mmGAMUT_REMAP_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1a5e, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C31_C32", REG_MMIO, 0x1a5e, &mmGAMUT_REMAP_C31_C32[0], sizeof(mmGAMUT_REMAP_C31_C32)/sizeof(mmGAMUT_REMAP_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1a5f, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C33_C34", REG_MMIO, 0x1a5f, &mmGAMUT_REMAP_C33_C34[0], sizeof(mmGAMUT_REMAP_C33_C34)/sizeof(mmGAMUT_REMAP_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1a60, NULL, 0, 0, 0 },
+	{ "mmDCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1a60, &mmDCP_SPATIAL_DITHER_CNTL[0], sizeof(mmDCP_SPATIAL_DITHER_CNTL)/sizeof(mmDCP_SPATIAL_DITHER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_DCP_RANDOM_SEEDS", REG_MMIO, 0x1a61, NULL, 0, 0, 0 },
+	{ "mmDCP_RANDOM_SEEDS", REG_MMIO, 0x1a61, &mmDCP_RANDOM_SEEDS[0], sizeof(mmDCP_RANDOM_SEEDS)/sizeof(mmDCP_RANDOM_SEEDS[0]), 0, 0 },
+	{ "mmDCP0_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1a65, NULL, 0, 0, 0 },
+	{ "mmDCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1a65, &mmDCP_FP_CONVERTED_FIELD[0], sizeof(mmDCP_FP_CONVERTED_FIELD)/sizeof(mmDCP_FP_CONVERTED_FIELD[0]), 0, 0 },
+	{ "mmDCP0_CUR_CONTROL", REG_MMIO, 0x1a66, NULL, 0, 0, 0 },
+	{ "mmCUR_CONTROL", REG_MMIO, 0x1a66, &mmCUR_CONTROL[0], sizeof(mmCUR_CONTROL)/sizeof(mmCUR_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1a67, NULL, 0, 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS", REG_MMIO, 0x1a67, &mmCUR_SURFACE_ADDRESS[0], sizeof(mmCUR_SURFACE_ADDRESS)/sizeof(mmCUR_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_CUR_SIZE", REG_MMIO, 0x1a68, NULL, 0, 0, 0 },
+	{ "mmCUR_SIZE", REG_MMIO, 0x1a68, &mmCUR_SIZE[0], sizeof(mmCUR_SIZE)/sizeof(mmCUR_SIZE[0]), 0, 0 },
+	{ "mmDCP0_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a69, NULL, 0, 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a69, &mmCUR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCUR_SURFACE_ADDRESS_HIGH)/sizeof(mmCUR_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_CUR_POSITION", REG_MMIO, 0x1a6a, NULL, 0, 0, 0 },
+	{ "mmCUR_POSITION", REG_MMIO, 0x1a6a, &mmCUR_POSITION[0], sizeof(mmCUR_POSITION)/sizeof(mmCUR_POSITION[0]), 0, 0 },
+	{ "mmDCP0_CUR_HOT_SPOT", REG_MMIO, 0x1a6b, NULL, 0, 0, 0 },
+	{ "mmCUR_HOT_SPOT", REG_MMIO, 0x1a6b, &mmCUR_HOT_SPOT[0], sizeof(mmCUR_HOT_SPOT)/sizeof(mmCUR_HOT_SPOT[0]), 0, 0 },
+	{ "mmDCP0_CUR_COLOR1", REG_MMIO, 0x1a6c, NULL, 0, 0, 0 },
+	{ "mmCUR_COLOR1", REG_MMIO, 0x1a6c, &mmCUR_COLOR1[0], sizeof(mmCUR_COLOR1)/sizeof(mmCUR_COLOR1[0]), 0, 0 },
+	{ "mmDCP0_CUR_COLOR2", REG_MMIO, 0x1a6d, NULL, 0, 0, 0 },
+	{ "mmCUR_COLOR2", REG_MMIO, 0x1a6d, &mmCUR_COLOR2[0], sizeof(mmCUR_COLOR2)/sizeof(mmCUR_COLOR2[0]), 0, 0 },
+	{ "mmDCP0_CUR_UPDATE", REG_MMIO, 0x1a6e, NULL, 0, 0, 0 },
+	{ "mmCUR_UPDATE", REG_MMIO, 0x1a6e, &mmCUR_UPDATE[0], sizeof(mmCUR_UPDATE)/sizeof(mmCUR_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_RW_MODE", REG_MMIO, 0x1a78, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_RW_MODE", REG_MMIO, 0x1a78, &mmDC_LUT_RW_MODE[0], sizeof(mmDC_LUT_RW_MODE)/sizeof(mmDC_LUT_RW_MODE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_RW_INDEX", REG_MMIO, 0x1a79, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_RW_INDEX", REG_MMIO, 0x1a79, &mmDC_LUT_RW_INDEX[0], sizeof(mmDC_LUT_RW_INDEX)/sizeof(mmDC_LUT_RW_INDEX[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1a7a, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_SEQ_COLOR", REG_MMIO, 0x1a7a, &mmDC_LUT_SEQ_COLOR[0], sizeof(mmDC_LUT_SEQ_COLOR)/sizeof(mmDC_LUT_SEQ_COLOR[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_PWL_DATA", REG_MMIO, 0x1a7b, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_PWL_DATA", REG_MMIO, 0x1a7b, &mmDC_LUT_PWL_DATA[0], sizeof(mmDC_LUT_PWL_DATA)/sizeof(mmDC_LUT_PWL_DATA[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_30_COLOR", REG_MMIO, 0x1a7c, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_30_COLOR", REG_MMIO, 0x1a7c, &mmDC_LUT_30_COLOR[0], sizeof(mmDC_LUT_30_COLOR)/sizeof(mmDC_LUT_30_COLOR[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1a7d, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1a7d, &mmDC_LUT_VGA_ACCESS_ENABLE[0], sizeof(mmDC_LUT_VGA_ACCESS_ENABLE)/sizeof(mmDC_LUT_VGA_ACCESS_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1a7e, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1a7e, &mmDC_LUT_WRITE_EN_MASK[0], sizeof(mmDC_LUT_WRITE_EN_MASK)/sizeof(mmDC_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_AUTOFILL", REG_MMIO, 0x1a7f, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_AUTOFILL", REG_MMIO, 0x1a7f, &mmDC_LUT_AUTOFILL[0], sizeof(mmDC_LUT_AUTOFILL)/sizeof(mmDC_LUT_AUTOFILL[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_CONTROL", REG_MMIO, 0x1a80, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_CONTROL", REG_MMIO, 0x1a80, &mmDC_LUT_CONTROL[0], sizeof(mmDC_LUT_CONTROL)/sizeof(mmDC_LUT_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1a81, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1a81, &mmDC_LUT_BLACK_OFFSET_BLUE[0], sizeof(mmDC_LUT_BLACK_OFFSET_BLUE)/sizeof(mmDC_LUT_BLACK_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1a82, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1a82, &mmDC_LUT_BLACK_OFFSET_GREEN[0], sizeof(mmDC_LUT_BLACK_OFFSET_GREEN)/sizeof(mmDC_LUT_BLACK_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1a83, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1a83, &mmDC_LUT_BLACK_OFFSET_RED[0], sizeof(mmDC_LUT_BLACK_OFFSET_RED)/sizeof(mmDC_LUT_BLACK_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1a84, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1a84, &mmDC_LUT_WHITE_OFFSET_BLUE[0], sizeof(mmDC_LUT_WHITE_OFFSET_BLUE)/sizeof(mmDC_LUT_WHITE_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1a85, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1a85, &mmDC_LUT_WHITE_OFFSET_GREEN[0], sizeof(mmDC_LUT_WHITE_OFFSET_GREEN)/sizeof(mmDC_LUT_WHITE_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1a86, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1a86, &mmDC_LUT_WHITE_OFFSET_RED[0], sizeof(mmDC_LUT_WHITE_OFFSET_RED)/sizeof(mmDC_LUT_WHITE_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CONTROL", REG_MMIO, 0x1a87, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_CONTROL", REG_MMIO, 0x1a87, &mmDCP_CRC_CONTROL[0], sizeof(mmDCP_CRC_CONTROL)/sizeof(mmDCP_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_MASK", REG_MMIO, 0x1a88, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_MASK", REG_MMIO, 0x1a88, &mmDCP_CRC_MASK[0], sizeof(mmDCP_CRC_MASK)/sizeof(mmDCP_CRC_MASK[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CURRENT", REG_MMIO, 0x1a89, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_CURRENT", REG_MMIO, 0x1a89, &mmDCP_CRC_CURRENT[0], sizeof(mmDCP_CRC_CURRENT)/sizeof(mmDCP_CRC_CURRENT[0]), 0, 0 },
+	{ "mmDCP0_DVMM_PTE_CONTROL", REG_MMIO, 0x1a8a, NULL, 0, 0, 0 },
+	{ "mmDVMM_PTE_CONTROL", REG_MMIO, 0x1a8a, &mmDVMM_PTE_CONTROL[0], sizeof(mmDVMM_PTE_CONTROL)/sizeof(mmDVMM_PTE_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_LAST", REG_MMIO, 0x1a8b, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_LAST", REG_MMIO, 0x1a8b, &mmDCP_CRC_LAST[0], sizeof(mmDCP_CRC_LAST)/sizeof(mmDCP_CRC_LAST[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG", REG_MMIO, 0x1a8d, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG", REG_MMIO, 0x1a8d, &mmDCP_DEBUG[0], sizeof(mmDCP_DEBUG)/sizeof(mmDCP_DEBUG[0]), 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1a8e, NULL, 0, 0, 0 },
+	{ "mmGRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1a8e, &mmGRPH_FLIP_RATE_CNTL[0], sizeof(mmGRPH_FLIP_RATE_CNTL)/sizeof(mmGRPH_FLIP_RATE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_DCP_GSL_CONTROL", REG_MMIO, 0x1a90, NULL, 0, 0, 0 },
+	{ "mmDCP_GSL_CONTROL", REG_MMIO, 0x1a90, &mmDCP_GSL_CONTROL[0], sizeof(mmDCP_GSL_CONTROL)/sizeof(mmDCP_GSL_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1a91, NULL, 0, 0, 0 },
+	{ "mmDCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1a91, &mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[0], sizeof(mmDCP_LB_DATA_GAP_BETWEEN_CHUNK)/sizeof(mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG_SG", REG_MMIO, 0x1a92, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG_SG", REG_MMIO, 0x1a92, &mmDCP_DEBUG_SG[0], sizeof(mmDCP_DEBUG_SG)/sizeof(mmDCP_DEBUG_SG[0]), 0, 0 },
+	{ "mmDCP0_DCP_DVMM_DEBUG", REG_MMIO, 0x1a93, NULL, 0, 0, 0 },
+	{ "mmDCP_DVMM_DEBUG", REG_MMIO, 0x1a93, &mmDCP_DVMM_DEBUG[0], sizeof(mmDCP_DVMM_DEBUG)/sizeof(mmDCP_DVMM_DEBUG[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG_SG2", REG_MMIO, 0x1a94, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG_SG2", REG_MMIO, 0x1a94, &mmDCP_DEBUG_SG2[0], sizeof(mmDCP_DEBUG_SG2)/sizeof(mmDCP_DEBUG_SG2[0]), 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1a95, NULL, 0, 0, 0 },
+	{ "mmDCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1a95, &mmDCP_TEST_DEBUG_INDEX[0], sizeof(mmDCP_TEST_DEBUG_INDEX)/sizeof(mmDCP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1a96, NULL, 0, 0, 0 },
+	{ "mmDCP_TEST_DEBUG_DATA", REG_MMIO, 0x1a96, &mmDCP_TEST_DEBUG_DATA[0], sizeof(mmDCP_TEST_DEBUG_DATA)/sizeof(mmDCP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCP0_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1a97, NULL, 0, 0, 0 },
+	{ "mmGRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1a97, &mmGRPH_STEREOSYNC_FLIP[0], sizeof(mmGRPH_STEREOSYNC_FLIP)/sizeof(mmGRPH_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG2", REG_MMIO, 0x1a98, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG2", REG_MMIO, 0x1a98, &mmDCP_DEBUG2[0], sizeof(mmDCP_DEBUG2)/sizeof(mmDCP_DEBUG2[0]), 0, 0 },
+	{ "mmDCP0_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1a99, NULL, 0, 0, 0 },
+	{ "mmCUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1a99, &mmCUR_REQUEST_FILTER_CNTL[0], sizeof(mmCUR_REQUEST_FILTER_CNTL)/sizeof(mmCUR_REQUEST_FILTER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_CUR_STEREO_CONTROL", REG_MMIO, 0x1a9a, NULL, 0, 0, 0 },
+	{ "mmCUR_STEREO_CONTROL", REG_MMIO, 0x1a9a, &mmCUR_STEREO_CONTROL[0], sizeof(mmCUR_STEREO_CONTROL)/sizeof(mmCUR_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1a9c, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1a9c, &mmOUT_CLAMP_CONTROL_G_Y[0], sizeof(mmOUT_CLAMP_CONTROL_G_Y)/sizeof(mmOUT_CLAMP_CONTROL_G_Y[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1a9d, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1a9d, &mmOUT_CLAMP_CONTROL_B_CB[0], sizeof(mmOUT_CLAMP_CONTROL_B_CB)/sizeof(mmOUT_CLAMP_CONTROL_B_CB[0]), 0, 0 },
+	{ "mmDCP0_HW_ROTATION", REG_MMIO, 0x1a9e, NULL, 0, 0, 0 },
+	{ "mmHW_ROTATION", REG_MMIO, 0x1a9e, &mmHW_ROTATION[0], sizeof(mmHW_ROTATION)/sizeof(mmHW_ROTATION[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1a9f, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1a9f, &mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[0], sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL)/sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CONTROL", REG_MMIO, 0x1aa0, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CONTROL", REG_MMIO, 0x1aa0, &mmREGAMMA_CONTROL[0], sizeof(mmREGAMMA_CONTROL)/sizeof(mmREGAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_INDEX", REG_MMIO, 0x1aa1, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_INDEX", REG_MMIO, 0x1aa1, &mmREGAMMA_LUT_INDEX[0], sizeof(mmREGAMMA_LUT_INDEX)/sizeof(mmREGAMMA_LUT_INDEX[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_DATA", REG_MMIO, 0x1aa2, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_DATA", REG_MMIO, 0x1aa2, &mmREGAMMA_LUT_DATA[0], sizeof(mmREGAMMA_LUT_DATA)/sizeof(mmREGAMMA_LUT_DATA[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1aa3, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1aa3, &mmREGAMMA_LUT_WRITE_EN_MASK[0], sizeof(mmREGAMMA_LUT_WRITE_EN_MASK)/sizeof(mmREGAMMA_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1aa4, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1aa4, &mmREGAMMA_CNTLA_START_CNTL[0], sizeof(mmREGAMMA_CNTLA_START_CNTL)/sizeof(mmREGAMMA_CNTLA_START_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1aa5, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1aa5, &mmREGAMMA_CNTLA_SLOPE_CNTL[0], sizeof(mmREGAMMA_CNTLA_SLOPE_CNTL)/sizeof(mmREGAMMA_CNTLA_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1aa6, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1aa6, &mmREGAMMA_CNTLA_END_CNTL1[0], sizeof(mmREGAMMA_CNTLA_END_CNTL1)/sizeof(mmREGAMMA_CNTLA_END_CNTL1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1aa7, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1aa7, &mmREGAMMA_CNTLA_END_CNTL2[0], sizeof(mmREGAMMA_CNTLA_END_CNTL2)/sizeof(mmREGAMMA_CNTLA_END_CNTL2[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1aa8, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1aa8, &mmREGAMMA_CNTLA_REGION_0_1[0], sizeof(mmREGAMMA_CNTLA_REGION_0_1)/sizeof(mmREGAMMA_CNTLA_REGION_0_1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1aa9, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1aa9, &mmREGAMMA_CNTLA_REGION_2_3[0], sizeof(mmREGAMMA_CNTLA_REGION_2_3)/sizeof(mmREGAMMA_CNTLA_REGION_2_3[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1aaa, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1aaa, &mmREGAMMA_CNTLA_REGION_4_5[0], sizeof(mmREGAMMA_CNTLA_REGION_4_5)/sizeof(mmREGAMMA_CNTLA_REGION_4_5[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1aab, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1aab, &mmREGAMMA_CNTLA_REGION_6_7[0], sizeof(mmREGAMMA_CNTLA_REGION_6_7)/sizeof(mmREGAMMA_CNTLA_REGION_6_7[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1aac, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1aac, &mmREGAMMA_CNTLA_REGION_8_9[0], sizeof(mmREGAMMA_CNTLA_REGION_8_9)/sizeof(mmREGAMMA_CNTLA_REGION_8_9[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1aad, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1aad, &mmREGAMMA_CNTLA_REGION_10_11[0], sizeof(mmREGAMMA_CNTLA_REGION_10_11)/sizeof(mmREGAMMA_CNTLA_REGION_10_11[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1aae, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1aae, &mmREGAMMA_CNTLA_REGION_12_13[0], sizeof(mmREGAMMA_CNTLA_REGION_12_13)/sizeof(mmREGAMMA_CNTLA_REGION_12_13[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1aaf, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1aaf, &mmREGAMMA_CNTLA_REGION_14_15[0], sizeof(mmREGAMMA_CNTLA_REGION_14_15)/sizeof(mmREGAMMA_CNTLA_REGION_14_15[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1ab0, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1ab0, &mmREGAMMA_CNTLB_START_CNTL[0], sizeof(mmREGAMMA_CNTLB_START_CNTL)/sizeof(mmREGAMMA_CNTLB_START_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1ab1, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1ab1, &mmREGAMMA_CNTLB_SLOPE_CNTL[0], sizeof(mmREGAMMA_CNTLB_SLOPE_CNTL)/sizeof(mmREGAMMA_CNTLB_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1ab2, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1ab2, &mmREGAMMA_CNTLB_END_CNTL1[0], sizeof(mmREGAMMA_CNTLB_END_CNTL1)/sizeof(mmREGAMMA_CNTLB_END_CNTL1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1ab3, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1ab3, &mmREGAMMA_CNTLB_END_CNTL2[0], sizeof(mmREGAMMA_CNTLB_END_CNTL2)/sizeof(mmREGAMMA_CNTLB_END_CNTL2[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1ab4, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1ab4, &mmREGAMMA_CNTLB_REGION_0_1[0], sizeof(mmREGAMMA_CNTLB_REGION_0_1)/sizeof(mmREGAMMA_CNTLB_REGION_0_1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1ab5, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1ab5, &mmREGAMMA_CNTLB_REGION_2_3[0], sizeof(mmREGAMMA_CNTLB_REGION_2_3)/sizeof(mmREGAMMA_CNTLB_REGION_2_3[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1ab6, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1ab6, &mmREGAMMA_CNTLB_REGION_4_5[0], sizeof(mmREGAMMA_CNTLB_REGION_4_5)/sizeof(mmREGAMMA_CNTLB_REGION_4_5[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1ab7, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1ab7, &mmREGAMMA_CNTLB_REGION_6_7[0], sizeof(mmREGAMMA_CNTLB_REGION_6_7)/sizeof(mmREGAMMA_CNTLB_REGION_6_7[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1ab8, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1ab8, &mmREGAMMA_CNTLB_REGION_8_9[0], sizeof(mmREGAMMA_CNTLB_REGION_8_9)/sizeof(mmREGAMMA_CNTLB_REGION_8_9[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1ab9, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1ab9, &mmREGAMMA_CNTLB_REGION_10_11[0], sizeof(mmREGAMMA_CNTLB_REGION_10_11)/sizeof(mmREGAMMA_CNTLB_REGION_10_11[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1aba, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1aba, &mmREGAMMA_CNTLB_REGION_12_13[0], sizeof(mmREGAMMA_CNTLB_REGION_12_13)/sizeof(mmREGAMMA_CNTLB_REGION_12_13[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1abb, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1abb, &mmREGAMMA_CNTLB_REGION_14_15[0], sizeof(mmREGAMMA_CNTLB_REGION_14_15)/sizeof(mmREGAMMA_CNTLB_REGION_14_15[0]), 0, 0 },
+	{ "mmDCP0_ALPHA_CONTROL", REG_MMIO, 0x1abc, NULL, 0, 0, 0 },
+	{ "mmALPHA_CONTROL", REG_MMIO, 0x1abc, &mmALPHA_CONTROL[0], sizeof(mmALPHA_CONTROL)/sizeof(mmALPHA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1abd, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1abd, &mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[0], sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS)/sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1abe, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1abe, &mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1abf, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1abf, &mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[0], sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS)/sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_DATA_FORMAT", REG_MMIO, 0x1ac0, NULL, 0, 0, 0 },
+	{ "mmLB_DATA_FORMAT", REG_MMIO, 0x1ac0, &mmLB_DATA_FORMAT[0], sizeof(mmLB_DATA_FORMAT)/sizeof(mmLB_DATA_FORMAT[0]), 0, 0 },
+	{ "mmLB0_LB_MEMORY_CTRL", REG_MMIO, 0x1ac1, NULL, 0, 0, 0 },
+	{ "mmLB_MEMORY_CTRL", REG_MMIO, 0x1ac1, &mmLB_MEMORY_CTRL[0], sizeof(mmLB_MEMORY_CTRL)/sizeof(mmLB_MEMORY_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ac2, NULL, 0, 0, 0 },
+	{ "mmLB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ac2, &mmLB_MEMORY_SIZE_STATUS[0], sizeof(mmLB_MEMORY_SIZE_STATUS)/sizeof(mmLB_MEMORY_SIZE_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1ac3, NULL, 0, 0, 0 },
+	{ "mmLB_DESKTOP_HEIGHT", REG_MMIO, 0x1ac3, &mmLB_DESKTOP_HEIGHT[0], sizeof(mmLB_DESKTOP_HEIGHT)/sizeof(mmLB_DESKTOP_HEIGHT[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE_START_END", REG_MMIO, 0x1ac4, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE_START_END", REG_MMIO, 0x1ac4, &mmLB_VLINE_START_END[0], sizeof(mmLB_VLINE_START_END)/sizeof(mmLB_VLINE_START_END[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE2_START_END", REG_MMIO, 0x1ac5, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE2_START_END", REG_MMIO, 0x1ac5, &mmLB_VLINE2_START_END[0], sizeof(mmLB_VLINE2_START_END)/sizeof(mmLB_VLINE2_START_END[0]), 0, 0 },
+	{ "mmLB0_LB_V_COUNTER", REG_MMIO, 0x1ac6, NULL, 0, 0, 0 },
+	{ "mmLB_V_COUNTER", REG_MMIO, 0x1ac6, &mmLB_V_COUNTER[0], sizeof(mmLB_V_COUNTER)/sizeof(mmLB_V_COUNTER[0]), 0, 0 },
+	{ "mmLB0_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ac7, NULL, 0, 0, 0 },
+	{ "mmLB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ac7, &mmLB_SNAPSHOT_V_COUNTER[0], sizeof(mmLB_SNAPSHOT_V_COUNTER)/sizeof(mmLB_SNAPSHOT_V_COUNTER[0]), 0, 0 },
+	{ "mmLB0_LB_INTERRUPT_MASK", REG_MMIO, 0x1ac8, NULL, 0, 0, 0 },
+	{ "mmLB_INTERRUPT_MASK", REG_MMIO, 0x1ac8, &mmLB_INTERRUPT_MASK[0], sizeof(mmLB_INTERRUPT_MASK)/sizeof(mmLB_INTERRUPT_MASK[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE_STATUS", REG_MMIO, 0x1ac9, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE_STATUS", REG_MMIO, 0x1ac9, &mmLB_VLINE_STATUS[0], sizeof(mmLB_VLINE_STATUS)/sizeof(mmLB_VLINE_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE2_STATUS", REG_MMIO, 0x1aca, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE2_STATUS", REG_MMIO, 0x1aca, &mmLB_VLINE2_STATUS[0], sizeof(mmLB_VLINE2_STATUS)/sizeof(mmLB_VLINE2_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_VBLANK_STATUS", REG_MMIO, 0x1acb, NULL, 0, 0, 0 },
+	{ "mmLB_VBLANK_STATUS", REG_MMIO, 0x1acb, &mmLB_VBLANK_STATUS[0], sizeof(mmLB_VBLANK_STATUS)/sizeof(mmLB_VBLANK_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_SYNC_RESET_SEL", REG_MMIO, 0x1acc, NULL, 0, 0, 0 },
+	{ "mmLB_SYNC_RESET_SEL", REG_MMIO, 0x1acc, &mmLB_SYNC_RESET_SEL[0], sizeof(mmLB_SYNC_RESET_SEL)/sizeof(mmLB_SYNC_RESET_SEL[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1acd, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_R_CR", REG_MMIO, 0x1acd, &mmLB_BLACK_KEYER_R_CR[0], sizeof(mmLB_BLACK_KEYER_R_CR)/sizeof(mmLB_BLACK_KEYER_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ace, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ace, &mmLB_BLACK_KEYER_G_Y[0], sizeof(mmLB_BLACK_KEYER_G_Y)/sizeof(mmLB_BLACK_KEYER_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1acf, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_B_CB", REG_MMIO, 0x1acf, &mmLB_BLACK_KEYER_B_CB[0], sizeof(mmLB_BLACK_KEYER_B_CB)/sizeof(mmLB_BLACK_KEYER_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ad0, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ad0, &mmLB_KEYER_COLOR_CTRL[0], sizeof(mmLB_KEYER_COLOR_CTRL)/sizeof(mmLB_KEYER_COLOR_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ad1, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ad1, &mmLB_KEYER_COLOR_R_CR[0], sizeof(mmLB_KEYER_COLOR_R_CR)/sizeof(mmLB_KEYER_COLOR_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ad2, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ad2, &mmLB_KEYER_COLOR_G_Y[0], sizeof(mmLB_KEYER_COLOR_G_Y)/sizeof(mmLB_KEYER_COLOR_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ad3, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ad3, &mmLB_KEYER_COLOR_B_CB[0], sizeof(mmLB_KEYER_COLOR_B_CB)/sizeof(mmLB_KEYER_COLOR_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ad4, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ad4, &mmLB_KEYER_COLOR_REP_R_CR[0], sizeof(mmLB_KEYER_COLOR_REP_R_CR)/sizeof(mmLB_KEYER_COLOR_REP_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ad5, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ad5, &mmLB_KEYER_COLOR_REP_G_Y[0], sizeof(mmLB_KEYER_COLOR_REP_G_Y)/sizeof(mmLB_KEYER_COLOR_REP_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ad6, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ad6, &mmLB_KEYER_COLOR_REP_B_CB[0], sizeof(mmLB_KEYER_COLOR_REP_B_CB)/sizeof(mmLB_KEYER_COLOR_REP_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ad7, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ad7, &mmLB_BUFFER_LEVEL_STATUS[0], sizeof(mmLB_BUFFER_LEVEL_STATUS)/sizeof(mmLB_BUFFER_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ad8, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ad8, &mmLB_BUFFER_URGENCY_CTRL[0], sizeof(mmLB_BUFFER_URGENCY_CTRL)/sizeof(mmLB_BUFFER_URGENCY_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ad9, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ad9, &mmLB_BUFFER_URGENCY_STATUS[0], sizeof(mmLB_BUFFER_URGENCY_STATUS)/sizeof(mmLB_BUFFER_URGENCY_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_STATUS", REG_MMIO, 0x1ada, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_STATUS", REG_MMIO, 0x1ada, &mmLB_BUFFER_STATUS[0], sizeof(mmLB_BUFFER_STATUS)/sizeof(mmLB_BUFFER_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1adc, NULL, 0, 0, 0 },
+	{ "mmLB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1adc, &mmLB_NO_OUTSTANDING_REQ_STATUS[0], sizeof(mmLB_NO_OUTSTANDING_REQ_STATUS)/sizeof(mmLB_NO_OUTSTANDING_REQ_STATUS[0]), 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ae0, NULL, 0, 0, 0 },
+	{ "mmMVP_AFR_FLIP_MODE", REG_MMIO, 0x1ae0, &mmMVP_AFR_FLIP_MODE[0], sizeof(mmMVP_AFR_FLIP_MODE)/sizeof(mmMVP_AFR_FLIP_MODE[0]), 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ae1, NULL, 0, 0, 0 },
+	{ "mmMVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ae1, &mmMVP_AFR_FLIP_FIFO_CNTL[0], sizeof(mmMVP_AFR_FLIP_FIFO_CNTL)/sizeof(mmMVP_AFR_FLIP_FIFO_CNTL[0]), 0, 0 },
+	{ "mmLB0_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ae2, NULL, 0, 0, 0 },
+	{ "mmMVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ae2, &mmMVP_FLIP_LINE_NUM_INSERT[0], sizeof(mmMVP_FLIP_LINE_NUM_INSERT)/sizeof(mmMVP_FLIP_LINE_NUM_INSERT[0]), 0, 0 },
+	{ "mmLB0_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ae3, NULL, 0, 0, 0 },
+	{ "mmDC_MVP_LB_CONTROL", REG_MMIO, 0x1ae3, &mmDC_MVP_LB_CONTROL[0], sizeof(mmDC_MVP_LB_CONTROL)/sizeof(mmDC_MVP_LB_CONTROL[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG", REG_MMIO, 0x1ae4, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG", REG_MMIO, 0x1ae4, &mmLB_DEBUG[0], sizeof(mmLB_DEBUG)/sizeof(mmLB_DEBUG[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG2", REG_MMIO, 0x1ae5, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG2", REG_MMIO, 0x1ae5, &mmLB_DEBUG2[0], sizeof(mmLB_DEBUG2)/sizeof(mmLB_DEBUG2[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG3", REG_MMIO, 0x1ae6, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG3", REG_MMIO, 0x1ae6, &mmLB_DEBUG3[0], sizeof(mmLB_DEBUG3)/sizeof(mmLB_DEBUG3[0]), 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1afe, NULL, 0, 0, 0 },
+	{ "mmLB_TEST_DEBUG_INDEX", REG_MMIO, 0x1afe, &mmLB_TEST_DEBUG_INDEX[0], sizeof(mmLB_TEST_DEBUG_INDEX)/sizeof(mmLB_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1aff, NULL, 0, 0, 0 },
+	{ "mmLB_TEST_DEBUG_DATA", REG_MMIO, 0x1aff, &mmLB_TEST_DEBUG_DATA[0], sizeof(mmLB_TEST_DEBUG_DATA)/sizeof(mmLB_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_L", REG_SMC, 0x1b, &ixDP_AUX_DEBUG_L[0], sizeof(ixDP_AUX_DEBUG_L)/sizeof(ixDP_AUX_DEBUG_L[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1B", REG_SMC, 0x1b, &ixDCIO_DEBUG1B[0], sizeof(ixDCIO_DEBUG1B)/sizeof(ixDCIO_DEBUG1B[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1b00, NULL, 0, 0, 0 },
+	{ "mmDCFE_CLOCK_CONTROL", REG_MMIO, 0x1b00, &mmDCFE_CLOCK_CONTROL[0], sizeof(mmDCFE_CLOCK_CONTROL)/sizeof(mmDCFE_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_SOFT_RESET", REG_MMIO, 0x1b01, NULL, 0, 0, 0 },
+	{ "mmDCFE_SOFT_RESET", REG_MMIO, 0x1b01, &mmDCFE_SOFT_RESET[0], sizeof(mmDCFE_SOFT_RESET)/sizeof(mmDCFE_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_DBG_CONFIG", REG_MMIO, 0x1b02, NULL, 0, 0, 0 },
+	{ "mmDCFE_DBG_CONFIG", REG_MMIO, 0x1b02, &mmDCFE_DBG_CONFIG[0], sizeof(mmDCFE_DBG_CONFIG)/sizeof(mmDCFE_DBG_CONFIG[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1b03, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_CTRL", REG_MMIO, 0x1b03, &mmDCFE_MEM_PWR_CTRL[0], sizeof(mmDCFE_MEM_PWR_CTRL)/sizeof(mmDCFE_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1b04, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1b04, &mmDCFE_MEM_PWR_CTRL2[0], sizeof(mmDCFE_MEM_PWR_CTRL2)/sizeof(mmDCFE_MEM_PWR_CTRL2[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1b05, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_PWR_STATUS", REG_MMIO, 0x1b05, &mmDCFE_MEM_PWR_STATUS[0], sizeof(mmDCFE_MEM_PWR_STATUS)/sizeof(mmDCFE_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_MISC", REG_MMIO, 0x1b06, NULL, 0, 0, 0 },
+	{ "mmDCFE_MISC", REG_MMIO, 0x1b06, &mmDCFE_MISC[0], sizeof(mmDCFE_MISC)/sizeof(mmDCFE_MISC[0]), 0, 0 },
+	{ "mmDCFE0_DCFE_FLUSH", REG_MMIO, 0x1b07, NULL, 0, 0, 0 },
+	{ "mmDCFE_FLUSH", REG_MMIO, 0x1b07, &mmDCFE_FLUSH[0], sizeof(mmDCFE_FLUSH)/sizeof(mmDCFE_FLUSH[0]), 0, 0 },
+	{ "mmDC_PERFMON4_PERFCOUNTER_CNTL", REG_MMIO, 0x1b24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFCOUNTER_STATE", REG_MMIO, 0x1b25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1b26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CNTL", REG_MMIO, 0x1b27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CVALUE_LOW", REG_MMIO, 0x1b28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_HI", REG_MMIO, 0x1b29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_LOW", REG_MMIO, 0x1b2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1b2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1b2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CNTL2", REG_MMIO, 0x1b2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1b30, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1b30, &mmDPG_PIPE_ARBITRATION_CONTROL1[0], sizeof(mmDPG_PIPE_ARBITRATION_CONTROL1)/sizeof(mmDPG_PIPE_ARBITRATION_CONTROL1[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1b31, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1b31, &mmDPG_PIPE_ARBITRATION_CONTROL2[0], sizeof(mmDPG_PIPE_ARBITRATION_CONTROL2)/sizeof(mmDPG_PIPE_ARBITRATION_CONTROL2[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1b32, NULL, 0, 0, 0 },
+	{ "mmDPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1b32, &mmDPG_WATERMARK_MASK_CONTROL[0], sizeof(mmDPG_WATERMARK_MASK_CONTROL)/sizeof(mmDPG_WATERMARK_MASK_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1b33, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1b33, &mmDPG_PIPE_URGENCY_CONTROL[0], sizeof(mmDPG_PIPE_URGENCY_CONTROL)/sizeof(mmDPG_PIPE_URGENCY_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1b34, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1b34, &mmDPG_PIPE_DPM_CONTROL[0], sizeof(mmDPG_PIPE_DPM_CONTROL)/sizeof(mmDPG_PIPE_DPM_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1b35, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1b35, &mmDPG_PIPE_STUTTER_CONTROL[0], sizeof(mmDPG_PIPE_STUTTER_CONTROL)/sizeof(mmDPG_PIPE_STUTTER_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1b36, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1b36, &mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[0], sizeof(mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL)/sizeof(mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1b37, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1b37, &mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[0], sizeof(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)/sizeof(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1b38, NULL, 0, 0, 0 },
+	{ "mmDPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1b38, &mmDPG_TEST_DEBUG_INDEX[0], sizeof(mmDPG_TEST_DEBUG_INDEX)/sizeof(mmDPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1b39, NULL, 0, 0, 0 },
+	{ "mmDPG_TEST_DEBUG_DATA", REG_MMIO, 0x1b39, &mmDPG_TEST_DEBUG_DATA[0], sizeof(mmDPG_TEST_DEBUG_DATA)/sizeof(mmDPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1b3a, NULL, 0, 0, 0 },
+	{ "mmDPG_REPEATER_PROGRAM", REG_MMIO, 0x1b3a, &mmDPG_REPEATER_PROGRAM[0], sizeof(mmDPG_REPEATER_PROGRAM)/sizeof(mmDPG_REPEATER_PROGRAM[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_A", REG_MMIO, 0x1b3b, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_A", REG_MMIO, 0x1b3b, &mmDPG_HW_DEBUG_A[0], sizeof(mmDPG_HW_DEBUG_A)/sizeof(mmDPG_HW_DEBUG_A[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_B", REG_MMIO, 0x1b3c, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_B", REG_MMIO, 0x1b3c, &mmDPG_HW_DEBUG_B[0], sizeof(mmDPG_HW_DEBUG_B)/sizeof(mmDPG_HW_DEBUG_B[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_11", REG_MMIO, 0x1b3d, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_11", REG_MMIO, 0x1b3d, &mmDPG_HW_DEBUG_11[0], sizeof(mmDPG_HW_DEBUG_11)/sizeof(mmDPG_HW_DEBUG_11[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x1b3e, NULL, 0, 0, 0 },
+	{ "mmDPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x1b3e, &mmDPG_CHK_PRE_PROC_CNTL[0], sizeof(mmDPG_CHK_PRE_PROC_CNTL)/sizeof(mmDPG_CHK_PRE_PROC_CNTL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_DVMM_STATUS", REG_MMIO, 0x1b3f, NULL, 0, 0, 0 },
+	{ "mmDPG_DVMM_STATUS", REG_MMIO, 0x1b3f, &mmDPG_DVMM_STATUS[0], sizeof(mmDPG_DVMM_STATUS)/sizeof(mmDPG_DVMM_STATUS[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1b40, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_SELECT", REG_MMIO, 0x1b40, &mmSCL_COEF_RAM_SELECT[0], sizeof(mmSCL_COEF_RAM_SELECT)/sizeof(mmSCL_COEF_RAM_SELECT[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1b41, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1b41, &mmSCL_COEF_RAM_TAP_DATA[0], sizeof(mmSCL_COEF_RAM_TAP_DATA)/sizeof(mmSCL_COEF_RAM_TAP_DATA[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE", REG_MMIO, 0x1b42, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE", REG_MMIO, 0x1b42, &mmSCL_MODE[0], sizeof(mmSCL_MODE)/sizeof(mmSCL_MODE[0]), 0, 0 },
+	{ "mmSCL0_SCL_TAP_CONTROL", REG_MMIO, 0x1b43, NULL, 0, 0, 0 },
+	{ "mmSCL_TAP_CONTROL", REG_MMIO, 0x1b43, &mmSCL_TAP_CONTROL[0], sizeof(mmSCL_TAP_CONTROL)/sizeof(mmSCL_TAP_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_CONTROL", REG_MMIO, 0x1b44, NULL, 0, 0, 0 },
+	{ "mmSCL_CONTROL", REG_MMIO, 0x1b44, &mmSCL_CONTROL[0], sizeof(mmSCL_CONTROL)/sizeof(mmSCL_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_BYPASS_CONTROL", REG_MMIO, 0x1b45, NULL, 0, 0, 0 },
+	{ "mmSCL_BYPASS_CONTROL", REG_MMIO, 0x1b45, &mmSCL_BYPASS_CONTROL[0], sizeof(mmSCL_BYPASS_CONTROL)/sizeof(mmSCL_BYPASS_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1b46, NULL, 0, 0, 0 },
+	{ "mmSCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1b46, &mmSCL_MANUAL_REPLICATE_CONTROL[0], sizeof(mmSCL_MANUAL_REPLICATE_CONTROL)/sizeof(mmSCL_MANUAL_REPLICATE_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1b47, NULL, 0, 0, 0 },
+	{ "mmSCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1b47, &mmSCL_AUTOMATIC_MODE_CONTROL[0], sizeof(mmSCL_AUTOMATIC_MODE_CONTROL)/sizeof(mmSCL_AUTOMATIC_MODE_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1b48, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1b48, &mmSCL_HORZ_FILTER_CONTROL[0], sizeof(mmSCL_HORZ_FILTER_CONTROL)/sizeof(mmSCL_HORZ_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1b49, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1b49, &mmSCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmSCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmSCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1b4a, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_INIT", REG_MMIO, 0x1b4a, &mmSCL_HORZ_FILTER_INIT[0], sizeof(mmSCL_HORZ_FILTER_INIT)/sizeof(mmSCL_HORZ_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1b4b, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1b4b, &mmSCL_VERT_FILTER_CONTROL[0], sizeof(mmSCL_VERT_FILTER_CONTROL)/sizeof(mmSCL_VERT_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1b4c, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1b4c, &mmSCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmSCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmSCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1b4d, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_INIT", REG_MMIO, 0x1b4d, &mmSCL_VERT_FILTER_INIT[0], sizeof(mmSCL_VERT_FILTER_INIT)/sizeof(mmSCL_VERT_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1b4e, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1b4e, &mmSCL_VERT_FILTER_INIT_BOT[0], sizeof(mmSCL_VERT_FILTER_INIT_BOT)/sizeof(mmSCL_VERT_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmSCL0_SCL_ROUND_OFFSET", REG_MMIO, 0x1b4f, NULL, 0, 0, 0 },
+	{ "mmSCL_ROUND_OFFSET", REG_MMIO, 0x1b4f, &mmSCL_ROUND_OFFSET[0], sizeof(mmSCL_ROUND_OFFSET)/sizeof(mmSCL_ROUND_OFFSET[0]), 0, 0 },
+	{ "mmSCL0_SCL_UPDATE", REG_MMIO, 0x1b51, NULL, 0, 0, 0 },
+	{ "mmSCL_UPDATE", REG_MMIO, 0x1b51, &mmSCL_UPDATE[0], sizeof(mmSCL_UPDATE)/sizeof(mmSCL_UPDATE[0]), 0, 0 },
+	{ "mmSCL0_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1b53, NULL, 0, 0, 0 },
+	{ "mmSCL_F_SHARP_CONTROL", REG_MMIO, 0x1b53, &mmSCL_F_SHARP_CONTROL[0], sizeof(mmSCL_F_SHARP_CONTROL)/sizeof(mmSCL_F_SHARP_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_ALU_CONTROL", REG_MMIO, 0x1b54, NULL, 0, 0, 0 },
+	{ "mmSCL_ALU_CONTROL", REG_MMIO, 0x1b54, &mmSCL_ALU_CONTROL[0], sizeof(mmSCL_ALU_CONTROL)/sizeof(mmSCL_ALU_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1b55, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1b55, &mmSCL_COEF_RAM_CONFLICT_STATUS[0], sizeof(mmSCL_COEF_RAM_CONFLICT_STATUS)/sizeof(mmSCL_COEF_RAM_CONFLICT_STATUS[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1b5b, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_START_SECONDARY", REG_MMIO, 0x1b5b, &mmVIEWPORT_START_SECONDARY[0], sizeof(mmVIEWPORT_START_SECONDARY)/sizeof(mmVIEWPORT_START_SECONDARY[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_START", REG_MMIO, 0x1b5c, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_START", REG_MMIO, 0x1b5c, &mmVIEWPORT_START[0], sizeof(mmVIEWPORT_START)/sizeof(mmVIEWPORT_START[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_SIZE", REG_MMIO, 0x1b5d, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_SIZE", REG_MMIO, 0x1b5d, &mmVIEWPORT_SIZE[0], sizeof(mmVIEWPORT_SIZE)/sizeof(mmVIEWPORT_SIZE[0]), 0, 0 },
+	{ "mmSCL0_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1b5e, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1b5e, &mmEXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmEXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmEXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 },
+	{ "mmSCL0_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1b5f, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1b5f, &mmEXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmEXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmEXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1b60, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET1", REG_MMIO, 0x1b60, &mmSCL_MODE_CHANGE_DET1[0], sizeof(mmSCL_MODE_CHANGE_DET1)/sizeof(mmSCL_MODE_CHANGE_DET1[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1b61, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET2", REG_MMIO, 0x1b61, &mmSCL_MODE_CHANGE_DET2[0], sizeof(mmSCL_MODE_CHANGE_DET2)/sizeof(mmSCL_MODE_CHANGE_DET2[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1b62, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET3", REG_MMIO, 0x1b62, &mmSCL_MODE_CHANGE_DET3[0], sizeof(mmSCL_MODE_CHANGE_DET3)/sizeof(mmSCL_MODE_CHANGE_DET3[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1b63, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_MASK", REG_MMIO, 0x1b63, &mmSCL_MODE_CHANGE_MASK[0], sizeof(mmSCL_MODE_CHANGE_MASK)/sizeof(mmSCL_MODE_CHANGE_MASK[0]), 0, 0 },
+	{ "mmSCL0_SCL_DEBUG2", REG_MMIO, 0x1b69, NULL, 0, 0, 0 },
+	{ "mmSCL_DEBUG2", REG_MMIO, 0x1b69, &mmSCL_DEBUG2[0], sizeof(mmSCL_DEBUG2)/sizeof(mmSCL_DEBUG2[0]), 0, 0 },
+	{ "mmSCL0_SCL_DEBUG", REG_MMIO, 0x1b6a, NULL, 0, 0, 0 },
+	{ "mmSCL_DEBUG", REG_MMIO, 0x1b6a, &mmSCL_DEBUG[0], sizeof(mmSCL_DEBUG)/sizeof(mmSCL_DEBUG[0]), 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1b6b, NULL, 0, 0, 0 },
+	{ "mmSCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1b6b, &mmSCL_TEST_DEBUG_INDEX[0], sizeof(mmSCL_TEST_DEBUG_INDEX)/sizeof(mmSCL_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1b6c, NULL, 0, 0, 0 },
+	{ "mmSCL_TEST_DEBUG_DATA", REG_MMIO, 0x1b6c, &mmSCL_TEST_DEBUG_DATA[0], sizeof(mmSCL_TEST_DEBUG_DATA)/sizeof(mmSCL_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLND0_BLND_CONTROL", REG_MMIO, 0x1b6d, NULL, 0, 0, 0 },
+	{ "mmBLND_CONTROL", REG_MMIO, 0x1b6d, &mmBLND_CONTROL[0], sizeof(mmBLND_CONTROL)/sizeof(mmBLND_CONTROL[0]), 0, 0 },
+	{ "mmBLND0_BLND_SM_CONTROL2", REG_MMIO, 0x1b6e, NULL, 0, 0, 0 },
+	{ "mmBLND_SM_CONTROL2", REG_MMIO, 0x1b6e, &mmBLND_SM_CONTROL2[0], sizeof(mmBLND_SM_CONTROL2)/sizeof(mmBLND_SM_CONTROL2[0]), 0, 0 },
+	{ "mmBLND0_BLND_CONTROL2", REG_MMIO, 0x1b6f, NULL, 0, 0, 0 },
+	{ "mmBLND_CONTROL2", REG_MMIO, 0x1b6f, &mmBLND_CONTROL2[0], sizeof(mmBLND_CONTROL2)/sizeof(mmBLND_CONTROL2[0]), 0, 0 },
+	{ "mmBLND0_BLND_UPDATE", REG_MMIO, 0x1b70, NULL, 0, 0, 0 },
+	{ "mmBLND_UPDATE", REG_MMIO, 0x1b70, &mmBLND_UPDATE[0], sizeof(mmBLND_UPDATE)/sizeof(mmBLND_UPDATE[0]), 0, 0 },
+	{ "mmBLND0_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1b71, NULL, 0, 0, 0 },
+	{ "mmBLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1b71, &mmBLND_UNDERFLOW_INTERRUPT[0], sizeof(mmBLND_UNDERFLOW_INTERRUPT)/sizeof(mmBLND_UNDERFLOW_INTERRUPT[0]), 0, 0 },
+	{ "mmBLND0_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1b73, NULL, 0, 0, 0 },
+	{ "mmBLND_V_UPDATE_LOCK", REG_MMIO, 0x1b73, &mmBLND_V_UPDATE_LOCK[0], sizeof(mmBLND_V_UPDATE_LOCK)/sizeof(mmBLND_V_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmBLND0_BLND_DEBUG", REG_MMIO, 0x1b74, NULL, 0, 0, 0 },
+	{ "mmBLND_DEBUG", REG_MMIO, 0x1b74, &mmBLND_DEBUG[0], sizeof(mmBLND_DEBUG)/sizeof(mmBLND_DEBUG[0]), 0, 0 },
+	{ "mmBLND0_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1b75, NULL, 0, 0, 0 },
+	{ "mmBLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1b75, &mmBLND_TEST_DEBUG_INDEX[0], sizeof(mmBLND_TEST_DEBUG_INDEX)/sizeof(mmBLND_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmBLND0_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1b76, NULL, 0, 0, 0 },
+	{ "mmBLND_TEST_DEBUG_DATA", REG_MMIO, 0x1b76, &mmBLND_TEST_DEBUG_DATA[0], sizeof(mmBLND_TEST_DEBUG_DATA)/sizeof(mmBLND_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLND0_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1b77, NULL, 0, 0, 0 },
+	{ "mmBLND_REG_UPDATE_STATUS", REG_MMIO, 0x1b77, &mmBLND_REG_UPDATE_STATUS[0], sizeof(mmBLND_REG_UPDATE_STATUS)/sizeof(mmBLND_REG_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b78, NULL, 0, 0, 0 },
+	{ "mmCRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b78, &mmCRTC_3D_STRUCTURE_CONTROL[0], sizeof(mmCRTC_3D_STRUCTURE_CONTROL)/sizeof(mmCRTC_3D_STRUCTURE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1b79, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1b79, &mmCRTC_GSL_VSYNC_GAP[0], sizeof(mmCRTC_GSL_VSYNC_GAP)/sizeof(mmCRTC_GSL_VSYNC_GAP[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_WINDOW", REG_MMIO, 0x1b7a, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_WINDOW", REG_MMIO, 0x1b7a, &mmCRTC_GSL_WINDOW[0], sizeof(mmCRTC_GSL_WINDOW)/sizeof(mmCRTC_GSL_WINDOW[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_CONTROL", REG_MMIO, 0x1b7b, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_CONTROL", REG_MMIO, 0x1b7b, &mmCRTC_GSL_CONTROL[0], sizeof(mmCRTC_GSL_CONTROL)/sizeof(mmCRTC_GSL_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1b7d, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1b7d, &mmCRTC_H_BLANK_EARLY_NUM[0], sizeof(mmCRTC_H_BLANK_EARLY_NUM)/sizeof(mmCRTC_H_BLANK_EARLY_NUM[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_TOTAL", REG_MMIO, 0x1b80, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_TOTAL", REG_MMIO, 0x1b80, &mmCRTC_H_TOTAL[0], sizeof(mmCRTC_H_TOTAL)/sizeof(mmCRTC_H_TOTAL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_START_END", REG_MMIO, 0x1b81, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_BLANK_START_END", REG_MMIO, 0x1b81, &mmCRTC_H_BLANK_START_END[0], sizeof(mmCRTC_H_BLANK_START_END)/sizeof(mmCRTC_H_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A", REG_MMIO, 0x1b82, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_A", REG_MMIO, 0x1b82, &mmCRTC_H_SYNC_A[0], sizeof(mmCRTC_H_SYNC_A)/sizeof(mmCRTC_H_SYNC_A[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1b83, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1b83, &mmCRTC_H_SYNC_A_CNTL[0], sizeof(mmCRTC_H_SYNC_A_CNTL)/sizeof(mmCRTC_H_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B", REG_MMIO, 0x1b84, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_B", REG_MMIO, 0x1b84, &mmCRTC_H_SYNC_B[0], sizeof(mmCRTC_H_SYNC_B)/sizeof(mmCRTC_H_SYNC_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1b85, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1b85, &mmCRTC_H_SYNC_B_CNTL[0], sizeof(mmCRTC_H_SYNC_B_CNTL)/sizeof(mmCRTC_H_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VBI_END", REG_MMIO, 0x1b86, NULL, 0, 0, 0 },
+	{ "mmCRTC_VBI_END", REG_MMIO, 0x1b86, &mmCRTC_VBI_END[0], sizeof(mmCRTC_VBI_END)/sizeof(mmCRTC_VBI_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL", REG_MMIO, 0x1b87, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL", REG_MMIO, 0x1b87, &mmCRTC_V_TOTAL[0], sizeof(mmCRTC_V_TOTAL)/sizeof(mmCRTC_V_TOTAL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1b88, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_MIN", REG_MMIO, 0x1b88, &mmCRTC_V_TOTAL_MIN[0], sizeof(mmCRTC_V_TOTAL_MIN)/sizeof(mmCRTC_V_TOTAL_MIN[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1b89, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_MAX", REG_MMIO, 0x1b89, &mmCRTC_V_TOTAL_MAX[0], sizeof(mmCRTC_V_TOTAL_MAX)/sizeof(mmCRTC_V_TOTAL_MAX[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1b8a, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1b8a, &mmCRTC_V_TOTAL_CONTROL[0], sizeof(mmCRTC_V_TOTAL_CONTROL)/sizeof(mmCRTC_V_TOTAL_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b8b, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b8b, &mmCRTC_V_TOTAL_INT_STATUS[0], sizeof(mmCRTC_V_TOTAL_INT_STATUS)/sizeof(mmCRTC_V_TOTAL_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b8c, NULL, 0, 0, 0 },
+	{ "mmCRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b8c, &mmCRTC_VSYNC_NOM_INT_STATUS[0], sizeof(mmCRTC_VSYNC_NOM_INT_STATUS)/sizeof(mmCRTC_VSYNC_NOM_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_BLANK_START_END", REG_MMIO, 0x1b8d, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_BLANK_START_END", REG_MMIO, 0x1b8d, &mmCRTC_V_BLANK_START_END[0], sizeof(mmCRTC_V_BLANK_START_END)/sizeof(mmCRTC_V_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A", REG_MMIO, 0x1b8e, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_A", REG_MMIO, 0x1b8e, &mmCRTC_V_SYNC_A[0], sizeof(mmCRTC_V_SYNC_A)/sizeof(mmCRTC_V_SYNC_A[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1b8f, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1b8f, &mmCRTC_V_SYNC_A_CNTL[0], sizeof(mmCRTC_V_SYNC_A_CNTL)/sizeof(mmCRTC_V_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B", REG_MMIO, 0x1b90, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_B", REG_MMIO, 0x1b90, &mmCRTC_V_SYNC_B[0], sizeof(mmCRTC_V_SYNC_B)/sizeof(mmCRTC_V_SYNC_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1b91, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1b91, &mmCRTC_V_SYNC_B_CNTL[0], sizeof(mmCRTC_V_SYNC_B_CNTL)/sizeof(mmCRTC_V_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1b92, NULL, 0, 0, 0 },
+	{ "mmCRTC_DTMTEST_CNTL", REG_MMIO, 0x1b92, &mmCRTC_DTMTEST_CNTL[0], sizeof(mmCRTC_DTMTEST_CNTL)/sizeof(mmCRTC_DTMTEST_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1b93, NULL, 0, 0, 0 },
+	{ "mmCRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1b93, &mmCRTC_DTMTEST_STATUS_POSITION[0], sizeof(mmCRTC_DTMTEST_STATUS_POSITION)/sizeof(mmCRTC_DTMTEST_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_CNTL", REG_MMIO, 0x1b94, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGA_CNTL", REG_MMIO, 0x1b94, &mmCRTC_TRIGA_CNTL[0], sizeof(mmCRTC_TRIGA_CNTL)/sizeof(mmCRTC_TRIGA_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b95, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b95, &mmCRTC_TRIGA_MANUAL_TRIG[0], sizeof(mmCRTC_TRIGA_MANUAL_TRIG)/sizeof(mmCRTC_TRIGA_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_CNTL", REG_MMIO, 0x1b96, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGB_CNTL", REG_MMIO, 0x1b96, &mmCRTC_TRIGB_CNTL[0], sizeof(mmCRTC_TRIGB_CNTL)/sizeof(mmCRTC_TRIGB_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b97, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b97, &mmCRTC_TRIGB_MANUAL_TRIG[0], sizeof(mmCRTC_TRIGB_MANUAL_TRIG)/sizeof(mmCRTC_TRIGB_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b98, NULL, 0, 0, 0 },
+	{ "mmCRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b98, &mmCRTC_FORCE_COUNT_NOW_CNTL[0], sizeof(mmCRTC_FORCE_COUNT_NOW_CNTL)/sizeof(mmCRTC_FORCE_COUNT_NOW_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FLOW_CONTROL", REG_MMIO, 0x1b99, NULL, 0, 0, 0 },
+	{ "mmCRTC_FLOW_CONTROL", REG_MMIO, 0x1b99, &mmCRTC_FLOW_CONTROL[0], sizeof(mmCRTC_FLOW_CONTROL)/sizeof(mmCRTC_FLOW_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b9a, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b9a, &mmCRTC_STEREO_FORCE_NEXT_EYE[0], sizeof(mmCRTC_STEREO_FORCE_NEXT_EYE)/sizeof(mmCRTC_STEREO_FORCE_NEXT_EYE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1b9b, NULL, 0, 0, 0 },
+	{ "mmCRTC_AVSYNC_COUNTER", REG_MMIO, 0x1b9b, &mmCRTC_AVSYNC_COUNTER[0], sizeof(mmCRTC_AVSYNC_COUNTER)/sizeof(mmCRTC_AVSYNC_COUNTER[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CONTROL", REG_MMIO, 0x1b9c, NULL, 0, 0, 0 },
+	{ "mmCRTC_CONTROL", REG_MMIO, 0x1b9c, &mmCRTC_CONTROL[0], sizeof(mmCRTC_CONTROL)/sizeof(mmCRTC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_CONTROL", REG_MMIO, 0x1b9d, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_CONTROL", REG_MMIO, 0x1b9d, &mmCRTC_BLANK_CONTROL[0], sizeof(mmCRTC_BLANK_CONTROL)/sizeof(mmCRTC_BLANK_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1b9e, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERLACE_CONTROL", REG_MMIO, 0x1b9e, &mmCRTC_INTERLACE_CONTROL[0], sizeof(mmCRTC_INTERLACE_CONTROL)/sizeof(mmCRTC_INTERLACE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1b9f, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERLACE_STATUS", REG_MMIO, 0x1b9f, &mmCRTC_INTERLACE_STATUS[0], sizeof(mmCRTC_INTERLACE_STATUS)/sizeof(mmCRTC_INTERLACE_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ba0, NULL, 0, 0, 0 },
+	{ "mmCRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ba0, &mmCRTC_FIELD_INDICATION_CONTROL[0], sizeof(mmCRTC_FIELD_INDICATION_CONTROL)/sizeof(mmCRTC_FIELD_INDICATION_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ba1, NULL, 0, 0, 0 },
+	{ "mmCRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ba1, &mmCRTC_PIXEL_DATA_READBACK0[0], sizeof(mmCRTC_PIXEL_DATA_READBACK0)/sizeof(mmCRTC_PIXEL_DATA_READBACK0[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ba2, NULL, 0, 0, 0 },
+	{ "mmCRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ba2, &mmCRTC_PIXEL_DATA_READBACK1[0], sizeof(mmCRTC_PIXEL_DATA_READBACK1)/sizeof(mmCRTC_PIXEL_DATA_READBACK1[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS", REG_MMIO, 0x1ba3, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS", REG_MMIO, 0x1ba3, &mmCRTC_STATUS[0], sizeof(mmCRTC_STATUS)/sizeof(mmCRTC_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_POSITION", REG_MMIO, 0x1ba4, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_POSITION", REG_MMIO, 0x1ba4, &mmCRTC_STATUS_POSITION[0], sizeof(mmCRTC_STATUS_POSITION)/sizeof(mmCRTC_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ba5, NULL, 0, 0, 0 },
+	{ "mmCRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ba5, &mmCRTC_NOM_VERT_POSITION[0], sizeof(mmCRTC_NOM_VERT_POSITION)/sizeof(mmCRTC_NOM_VERT_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ba6, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ba6, &mmCRTC_STATUS_FRAME_COUNT[0], sizeof(mmCRTC_STATUS_FRAME_COUNT)/sizeof(mmCRTC_STATUS_FRAME_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ba7, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ba7, &mmCRTC_STATUS_VF_COUNT[0], sizeof(mmCRTC_STATUS_VF_COUNT)/sizeof(mmCRTC_STATUS_VF_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ba8, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ba8, &mmCRTC_STATUS_HV_COUNT[0], sizeof(mmCRTC_STATUS_HV_COUNT)/sizeof(mmCRTC_STATUS_HV_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_CONTROL", REG_MMIO, 0x1ba9, NULL, 0, 0, 0 },
+	{ "mmCRTC_COUNT_CONTROL", REG_MMIO, 0x1ba9, &mmCRTC_COUNT_CONTROL[0], sizeof(mmCRTC_COUNT_CONTROL)/sizeof(mmCRTC_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_RESET", REG_MMIO, 0x1baa, NULL, 0, 0, 0 },
+	{ "mmCRTC_COUNT_RESET", REG_MMIO, 0x1baa, &mmCRTC_COUNT_RESET[0], sizeof(mmCRTC_COUNT_RESET)/sizeof(mmCRTC_COUNT_RESET[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bab, NULL, 0, 0, 0 },
+	{ "mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bab, &mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1bac, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1bac, &mmCRTC_VERT_SYNC_CONTROL[0], sizeof(mmCRTC_VERT_SYNC_CONTROL)/sizeof(mmCRTC_VERT_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_STATUS", REG_MMIO, 0x1bad, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_STATUS", REG_MMIO, 0x1bad, &mmCRTC_STEREO_STATUS[0], sizeof(mmCRTC_STEREO_STATUS)/sizeof(mmCRTC_STEREO_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_CONTROL", REG_MMIO, 0x1bae, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_CONTROL", REG_MMIO, 0x1bae, &mmCRTC_STEREO_CONTROL[0], sizeof(mmCRTC_STEREO_CONTROL)/sizeof(mmCRTC_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1baf, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1baf, &mmCRTC_SNAPSHOT_STATUS[0], sizeof(mmCRTC_SNAPSHOT_STATUS)/sizeof(mmCRTC_SNAPSHOT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1bb0, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1bb0, &mmCRTC_SNAPSHOT_CONTROL[0], sizeof(mmCRTC_SNAPSHOT_CONTROL)/sizeof(mmCRTC_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1bb1, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1bb1, &mmCRTC_SNAPSHOT_POSITION[0], sizeof(mmCRTC_SNAPSHOT_POSITION)/sizeof(mmCRTC_SNAPSHOT_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1bb2, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1bb2, &mmCRTC_SNAPSHOT_FRAME[0], sizeof(mmCRTC_SNAPSHOT_FRAME)/sizeof(mmCRTC_SNAPSHOT_FRAME[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1bb3, NULL, 0, 0, 0 },
+	{ "mmCRTC_START_LINE_CONTROL", REG_MMIO, 0x1bb3, &mmCRTC_START_LINE_CONTROL[0], sizeof(mmCRTC_START_LINE_CONTROL)/sizeof(mmCRTC_START_LINE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1bb4, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1bb4, &mmCRTC_INTERRUPT_CONTROL[0], sizeof(mmCRTC_INTERRUPT_CONTROL)/sizeof(mmCRTC_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_UPDATE_LOCK", REG_MMIO, 0x1bb5, NULL, 0, 0, 0 },
+	{ "mmCRTC_UPDATE_LOCK", REG_MMIO, 0x1bb5, &mmCRTC_UPDATE_LOCK[0], sizeof(mmCRTC_UPDATE_LOCK)/sizeof(mmCRTC_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bb6, NULL, 0, 0, 0 },
+	{ "mmCRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bb6, &mmCRTC_DOUBLE_BUFFER_CONTROL[0], sizeof(mmCRTC_DOUBLE_BUFFER_CONTROL)/sizeof(mmCRTC_DOUBLE_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1bb7, NULL, 0, 0, 0 },
+	{ "mmCRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1bb7, &mmCRTC_VGA_PARAMETER_CAPTURE_MODE[0], sizeof(mmCRTC_VGA_PARAMETER_CAPTURE_MODE)/sizeof(mmCRTC_VGA_PARAMETER_CAPTURE_MODE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bba, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bba, &mmCRTC_TEST_PATTERN_CONTROL[0], sizeof(mmCRTC_TEST_PATTERN_CONTROL)/sizeof(mmCRTC_TEST_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bbb, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bbb, &mmCRTC_TEST_PATTERN_PARAMETERS[0], sizeof(mmCRTC_TEST_PATTERN_PARAMETERS)/sizeof(mmCRTC_TEST_PATTERN_PARAMETERS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1bbc, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1bbc, &mmCRTC_TEST_PATTERN_COLOR[0], sizeof(mmCRTC_TEST_PATTERN_COLOR)/sizeof(mmCRTC_TEST_PATTERN_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x1bbd, NULL, 0, 0, 0 },
+	{ "mmCRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x1bbd, &mmCRTC_MASTER_UPDATE_LOCK[0], sizeof(mmCRTC_MASTER_UPDATE_LOCK)/sizeof(mmCRTC_MASTER_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x1bbe, NULL, 0, 0, 0 },
+	{ "mmCRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x1bbe, &mmCRTC_MASTER_UPDATE_MODE[0], sizeof(mmCRTC_MASTER_UPDATE_MODE)/sizeof(mmCRTC_MASTER_UPDATE_MODE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1bbf, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1bbf, &mmCRTC_MVP_INBAND_CNTL_INSERT[0], sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT)/sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1bc0, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1bc0, &mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[0], sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER)/sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_STATUS", REG_MMIO, 0x1bc1, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_STATUS", REG_MMIO, 0x1bc1, &mmCRTC_MVP_STATUS[0], sizeof(mmCRTC_MVP_STATUS)/sizeof(mmCRTC_MVP_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_EN", REG_MMIO, 0x1bc2, NULL, 0, 0, 0 },
+	{ "mmCRTC_MASTER_EN", REG_MMIO, 0x1bc2, &mmCRTC_MASTER_EN[0], sizeof(mmCRTC_MASTER_EN)/sizeof(mmCRTC_MASTER_EN[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1bc3, NULL, 0, 0, 0 },
+	{ "mmCRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1bc3, &mmCRTC_ALLOW_STOP_OFF_V_CNT[0], sizeof(mmCRTC_ALLOW_STOP_OFF_V_CNT)/sizeof(mmCRTC_ALLOW_STOP_OFF_V_CNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1bc4, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1bc4, &mmCRTC_V_UPDATE_INT_STATUS[0], sizeof(mmCRTC_V_UPDATE_INT_STATUS)/sizeof(mmCRTC_V_UPDATE_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1bc6, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1bc6, &mmCRTC_TEST_DEBUG_INDEX[0], sizeof(mmCRTC_TEST_DEBUG_INDEX)/sizeof(mmCRTC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1bc7, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1bc7, &mmCRTC_TEST_DEBUG_DATA[0], sizeof(mmCRTC_TEST_DEBUG_DATA)/sizeof(mmCRTC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1bc8, NULL, 0, 0, 0 },
+	{ "mmCRTC_OVERSCAN_COLOR", REG_MMIO, 0x1bc8, &mmCRTC_OVERSCAN_COLOR[0], sizeof(mmCRTC_OVERSCAN_COLOR)/sizeof(mmCRTC_OVERSCAN_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1bc9, NULL, 0, 0, 0 },
+	{ "mmCRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1bc9, &mmCRTC_OVERSCAN_COLOR_EXT[0], sizeof(mmCRTC_OVERSCAN_COLOR_EXT)/sizeof(mmCRTC_OVERSCAN_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1bca, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1bca, &mmCRTC_BLANK_DATA_COLOR[0], sizeof(mmCRTC_BLANK_DATA_COLOR)/sizeof(mmCRTC_BLANK_DATA_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1bcb, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1bcb, &mmCRTC_BLANK_DATA_COLOR_EXT[0], sizeof(mmCRTC_BLANK_DATA_COLOR_EXT)/sizeof(mmCRTC_BLANK_DATA_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR", REG_MMIO, 0x1bcc, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLACK_COLOR", REG_MMIO, 0x1bcc, &mmCRTC_BLACK_COLOR[0], sizeof(mmCRTC_BLACK_COLOR)/sizeof(mmCRTC_BLACK_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1bcd, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1bcd, &mmCRTC_BLACK_COLOR_EXT[0], sizeof(mmCRTC_BLACK_COLOR_EXT)/sizeof(mmCRTC_BLACK_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1bce, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1bce, &mmCRTC_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1bcf, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1bcf, &mmCRTC_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1bd0, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1bd0, &mmCRTC_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1bd1, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1bd1, &mmCRTC_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1bd2, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1bd2, &mmCRTC_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bd3, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bd3, &mmCRTC_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC_CNTL", REG_MMIO, 0x1bd4, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC_CNTL", REG_MMIO, 0x1bd4, &mmCRTC_CRC_CNTL[0], sizeof(mmCRTC_CRC_CNTL)/sizeof(mmCRTC_CRC_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bd5, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bd5, &mmCRTC_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWA_X_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bd6, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bd6, &mmCRTC_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bd7, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bd7, &mmCRTC_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWB_X_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bd8, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bd8, &mmCRTC_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1bd9, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_DATA_RG", REG_MMIO, 0x1bd9, &mmCRTC_CRC0_DATA_RG[0], sizeof(mmCRTC_CRC0_DATA_RG)/sizeof(mmCRTC_CRC0_DATA_RG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_DATA_B", REG_MMIO, 0x1bda, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_DATA_B", REG_MMIO, 0x1bda, &mmCRTC_CRC0_DATA_B[0], sizeof(mmCRTC_CRC0_DATA_B)/sizeof(mmCRTC_CRC0_DATA_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bdb, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bdb, &mmCRTC_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWA_X_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bdc, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bdc, &mmCRTC_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bdd, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bdd, &mmCRTC_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWB_X_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bde, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bde, &mmCRTC_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1bdf, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_DATA_RG", REG_MMIO, 0x1bdf, &mmCRTC_CRC1_DATA_RG[0], sizeof(mmCRTC_CRC1_DATA_RG)/sizeof(mmCRTC_CRC1_DATA_RG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_DATA_B", REG_MMIO, 0x1be0, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_DATA_B", REG_MMIO, 0x1be0, &mmCRTC_CRC1_DATA_B[0], sizeof(mmCRTC_CRC1_DATA_B)/sizeof(mmCRTC_CRC1_DATA_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1be1, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1be1, &mmCRTC_EXT_TIMING_SYNC_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1be2, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1be2, &mmCRTC_EXT_TIMING_SYNC_WINDOW_START[0], sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_START)/sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_START[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1be3, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1be3, &mmCRTC_EXT_TIMING_SYNC_WINDOW_END[0], sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_END)/sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1be4, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1be4, &mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1be5, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1be5, &mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1be6, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1be6, &mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1be7, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1be7, &mmCRTC_STATIC_SCREEN_CONTROL[0], sizeof(mmCRTC_STATIC_SCREEN_CONTROL)/sizeof(mmCRTC_STATIC_SCREEN_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1be8, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1be8, &mmFMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT_CLAMP_COMPONENT_R)/sizeof(mmFMT_CLAMP_COMPONENT_R[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1be9, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1be9, &mmFMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT_CLAMP_COMPONENT_G)/sizeof(mmFMT_CLAMP_COMPONENT_G[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1bea, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1bea, &mmFMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT_CLAMP_COMPONENT_B)/sizeof(mmFMT_CLAMP_COMPONENT_B[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1beb, NULL, 0, 0, 0 },
+	{ "mmFMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1beb, &mmFMT_TEST_DEBUG_INDEX[0], sizeof(mmFMT_TEST_DEBUG_INDEX)/sizeof(mmFMT_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1bec, NULL, 0, 0, 0 },
+	{ "mmFMT_TEST_DEBUG_DATA", REG_MMIO, 0x1bec, &mmFMT_TEST_DEBUG_DATA[0], sizeof(mmFMT_TEST_DEBUG_DATA)/sizeof(mmFMT_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmFMT0_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1bed, NULL, 0, 0, 0 },
+	{ "mmFMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1bed, &mmFMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT_DYNAMIC_EXP_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CONTROL", REG_MMIO, 0x1bee, NULL, 0, 0, 0 },
+	{ "mmFMT_CONTROL", REG_MMIO, 0x1bee, &mmFMT_CONTROL[0], sizeof(mmFMT_CONTROL)/sizeof(mmFMT_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x1bf0, NULL, 0, 0, 0 },
+	{ "mmFMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x1bf0, &mmFMT_SIDE_BY_SIDE_STEREO_CONTROL[0], sizeof(mmFMT_SIDE_BY_SIDE_STEREO_CONTROL)/sizeof(mmFMT_SIDE_BY_SIDE_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_420_HBLANK_EARLY_START", REG_MMIO, 0x1bf1, NULL, 0, 0, 0 },
+	{ "mmFMT_420_HBLANK_EARLY_START", REG_MMIO, 0x1bf1, &mmFMT_420_HBLANK_EARLY_START[0], sizeof(mmFMT_420_HBLANK_EARLY_START)/sizeof(mmFMT_420_HBLANK_EARLY_START[0]), 0, 0 },
+	{ "mmFMT0_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1bf2, NULL, 0, 0, 0 },
+	{ "mmFMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1bf2, &mmFMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT_BIT_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1bf3, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1bf3, &mmFMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT_DITHER_RAND_R_SEED)/sizeof(mmFMT_DITHER_RAND_R_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1bf4, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1bf4, &mmFMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT_DITHER_RAND_G_SEED)/sizeof(mmFMT_DITHER_RAND_G_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1bf5, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1bf5, &mmFMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT_DITHER_RAND_B_SEED)/sizeof(mmFMT_DITHER_RAND_B_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1bf6, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1bf6, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1bf7, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1bf7, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1bf8, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1bf8, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_CNTL", REG_MMIO, 0x1bf9, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_CNTL", REG_MMIO, 0x1bf9, &mmFMT_CLAMP_CNTL[0], sizeof(mmFMT_CLAMP_CNTL)/sizeof(mmFMT_CLAMP_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_CNTL", REG_MMIO, 0x1bfa, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_CNTL", REG_MMIO, 0x1bfa, &mmFMT_CRC_CNTL[0], sizeof(mmFMT_CRC_CNTL)/sizeof(mmFMT_CRC_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfb, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfb, &mmFMT_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmFMT_CRC_SIG_RED_GREEN_MASK)/sizeof(mmFMT_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfc, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfc, &mmFMT_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmFMT_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmFMT_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1bfd, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1bfd, &mmFMT_CRC_SIG_RED_GREEN[0], sizeof(mmFMT_CRC_SIG_RED_GREEN)/sizeof(mmFMT_CRC_SIG_RED_GREEN[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1bfe, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1bfe, &mmFMT_CRC_SIG_BLUE_CONTROL[0], sizeof(mmFMT_CRC_SIG_BLUE_CONTROL)/sizeof(mmFMT_CRC_SIG_BLUE_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_DEBUG_CNTL", REG_MMIO, 0x1bff, NULL, 0, 0, 0 },
+	{ "mmFMT_DEBUG_CNTL", REG_MMIO, 0x1bff, &mmFMT_DEBUG_CNTL[0], sizeof(mmFMT_DEBUG_CNTL)/sizeof(mmFMT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDMA_POSITION_LOWER_BASE_ADDRESS", REG_MMIO, 0x1c, &mmDMA_POSITION_LOWER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_M", REG_SMC, 0x1c, &ixDP_AUX_DEBUG_M[0], sizeof(ixDP_AUX_DEBUG_M)/sizeof(ixDP_AUX_DEBUG_M[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1C", REG_SMC, 0x1c, &ixDCIO_DEBUG1C[0], sizeof(ixDCIO_DEBUG1C)/sizeof(ixDCIO_DEBUG1C[0]), 0, 0 },
+	{ "mmDCP1_GRPH_ENABLE", REG_MMIO, 0x1c00, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_CONTROL", REG_MMIO, 0x1c01, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1c02, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SWAP_CNTL", REG_MMIO, 0x1c03, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1c04, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1c05, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PITCH", REG_MMIO, 0x1c06, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c07, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c08, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1c09, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1c0a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_START", REG_MMIO, 0x1c0b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_START", REG_MMIO, 0x1c0c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_END", REG_MMIO, 0x1c0d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_END", REG_MMIO, 0x1c0e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x1c0f, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1c10, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_UPDATE", REG_MMIO, 0x1c11, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_CONTROL", REG_MMIO, 0x1c12, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1c13, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_CONTROL", REG_MMIO, 0x1c14, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_STATUS", REG_MMIO, 0x1c15, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1c16, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1c17, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1c18, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1c19, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1c1a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c1b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x1c1c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x1c1d, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1c2d, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1c2e, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1c2f, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1c30, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_CONTROL", REG_MMIO, 0x1c35, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C11_C12", REG_MMIO, 0x1c36, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C13_C14", REG_MMIO, 0x1c37, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C21_C22", REG_MMIO, 0x1c38, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C23_C24", REG_MMIO, 0x1c39, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C31_C32", REG_MMIO, 0x1c3a, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C33_C34", REG_MMIO, 0x1c3b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1c3c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1c3d, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1c3e, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1c3f, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1c40, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1c41, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1c42, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1c43, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1c44, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1c45, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1c46, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1c47, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1c48, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1c49, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1c4a, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1c4b, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1c4c, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1c4d, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1c4e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DENORM_CONTROL", REG_MMIO, 0x1c50, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_ROUND_CONTROL", REG_MMIO, 0x1c51, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1c52, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_CONTROL", REG_MMIO, 0x1c53, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_ALPHA", REG_MMIO, 0x1c54, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_RED", REG_MMIO, 0x1c55, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_GREEN", REG_MMIO, 0x1c56, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_BLUE", REG_MMIO, 0x1c57, NULL, 0, 0, 0 },
+	{ "mmDCP1_DEGAMMA_CONTROL", REG_MMIO, 0x1c58, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1c59, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1c5a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1c5b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1c5c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1c5d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1c5e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1c5f, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1c60, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_RANDOM_SEEDS", REG_MMIO, 0x1c61, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1c65, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_CONTROL", REG_MMIO, 0x1c66, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1c67, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SIZE", REG_MMIO, 0x1c68, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1c69, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_POSITION", REG_MMIO, 0x1c6a, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_HOT_SPOT", REG_MMIO, 0x1c6b, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR1", REG_MMIO, 0x1c6c, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR2", REG_MMIO, 0x1c6d, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_UPDATE", REG_MMIO, 0x1c6e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_MODE", REG_MMIO, 0x1c78, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_INDEX", REG_MMIO, 0x1c79, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1c7a, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_PWL_DATA", REG_MMIO, 0x1c7b, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_30_COLOR", REG_MMIO, 0x1c7c, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1c7d, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1c7e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_AUTOFILL", REG_MMIO, 0x1c7f, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_CONTROL", REG_MMIO, 0x1c80, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1c81, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1c82, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1c83, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1c84, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1c85, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1c86, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CONTROL", REG_MMIO, 0x1c87, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_MASK", REG_MMIO, 0x1c88, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CURRENT", REG_MMIO, 0x1c89, NULL, 0, 0, 0 },
+	{ "mmDCP1_DVMM_PTE_CONTROL", REG_MMIO, 0x1c8a, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_LAST", REG_MMIO, 0x1c8b, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG", REG_MMIO, 0x1c8d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1c8e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_GSL_CONTROL", REG_MMIO, 0x1c90, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1c91, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG_SG", REG_MMIO, 0x1c92, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DVMM_DEBUG", REG_MMIO, 0x1c93, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG_SG2", REG_MMIO, 0x1c94, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1c95, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1c96, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1c97, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG2", REG_MMIO, 0x1c98, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1c99, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_STEREO_CONTROL", REG_MMIO, 0x1c9a, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1c9c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1c9d, NULL, 0, 0, 0 },
+	{ "mmDCP1_HW_ROTATION", REG_MMIO, 0x1c9e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1c9f, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CONTROL", REG_MMIO, 0x1ca0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_INDEX", REG_MMIO, 0x1ca1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_DATA", REG_MMIO, 0x1ca2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1ca3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1ca4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1ca5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1ca6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1ca7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1ca8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1ca9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1caa, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1cab, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1cac, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1cad, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1cae, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1caf, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1cb0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1cb1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1cb2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1cb3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1cb4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1cb5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1cb6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1cb7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1cb8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1cb9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1cba, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1cbb, NULL, 0, 0, 0 },
+	{ "mmDCP1_ALPHA_CONTROL", REG_MMIO, 0x1cbc, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1cbd, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1cbe, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1cbf, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DATA_FORMAT", REG_MMIO, 0x1cc0, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_MEMORY_CTRL", REG_MMIO, 0x1cc1, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1cc2, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1cc3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE_START_END", REG_MMIO, 0x1cc4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE2_START_END", REG_MMIO, 0x1cc5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_V_COUNTER", REG_MMIO, 0x1cc6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1cc7, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_INTERRUPT_MASK", REG_MMIO, 0x1cc8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE_STATUS", REG_MMIO, 0x1cc9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE2_STATUS", REG_MMIO, 0x1cca, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VBLANK_STATUS", REG_MMIO, 0x1ccb, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SYNC_RESET_SEL", REG_MMIO, 0x1ccc, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1ccd, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1cce, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1ccf, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1cd0, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1cd1, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1cd2, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1cd3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1cd4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1cd5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1cd6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1cd7, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1cd8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1cd9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_STATUS", REG_MMIO, 0x1cda, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1cdc, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ce0, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ce1, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ce2, NULL, 0, 0, 0 },
+	{ "mmLB1_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ce3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG", REG_MMIO, 0x1ce4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG2", REG_MMIO, 0x1ce5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG3", REG_MMIO, 0x1ce6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1cfe, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1cff, NULL, 0, 0, 0 },
+	{ "mmDMA_POSITION_UPPER_BASE_ADDRESS", REG_MMIO, 0x1d, &mmDMA_POSITION_UPPER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_N", REG_SMC, 0x1d, &ixDP_AUX_DEBUG_N[0], sizeof(ixDP_AUX_DEBUG_N)/sizeof(ixDP_AUX_DEBUG_N[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1D", REG_SMC, 0x1d, &ixDCIO_DEBUG1D[0], sizeof(ixDCIO_DEBUG1D)/sizeof(ixDCIO_DEBUG1D[0]), 0, 0 },
+	{ "mmDCFE1_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1d00, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_SOFT_RESET", REG_MMIO, 0x1d01, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_DBG_CONFIG", REG_MMIO, 0x1d02, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1d03, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1d04, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1d05, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_MISC", REG_MMIO, 0x1d06, NULL, 0, 0, 0 },
+	{ "mmDCFE1_DCFE_FLUSH", REG_MMIO, 0x1d07, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFCOUNTER_CNTL", REG_MMIO, 0x1d24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFCOUNTER_STATE", REG_MMIO, 0x1d25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1d26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CNTL", REG_MMIO, 0x1d27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CVALUE_LOW", REG_MMIO, 0x1d28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_HI", REG_MMIO, 0x1d29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_LOW", REG_MMIO, 0x1d2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1d2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1d2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CNTL2", REG_MMIO, 0x1d2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1d30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1d31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1d32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1d33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1d34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1d35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1d36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1d37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1d38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1d39, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1d3a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_A", REG_MMIO, 0x1d3b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_B", REG_MMIO, 0x1d3c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_11", REG_MMIO, 0x1d3d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x1d3e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_DVMM_STATUS", REG_MMIO, 0x1d3f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1d40, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1d41, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE", REG_MMIO, 0x1d42, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TAP_CONTROL", REG_MMIO, 0x1d43, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_CONTROL", REG_MMIO, 0x1d44, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_BYPASS_CONTROL", REG_MMIO, 0x1d45, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1d46, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1d47, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1d48, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1d49, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1d4a, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1d4b, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1d4c, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1d4d, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1d4e, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ROUND_OFFSET", REG_MMIO, 0x1d4f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_UPDATE", REG_MMIO, 0x1d51, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1d53, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ALU_CONTROL", REG_MMIO, 0x1d54, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1d55, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1d5b, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_START", REG_MMIO, 0x1d5c, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_SIZE", REG_MMIO, 0x1d5d, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1d5e, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1d5f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1d60, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1d61, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1d62, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1d63, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG2", REG_MMIO, 0x1d69, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG", REG_MMIO, 0x1d6a, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1d6b, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1d6c, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_CONTROL", REG_MMIO, 0x1d6d, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_SM_CONTROL2", REG_MMIO, 0x1d6e, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_CONTROL2", REG_MMIO, 0x1d6f, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_UPDATE", REG_MMIO, 0x1d70, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1d71, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1d73, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_DEBUG", REG_MMIO, 0x1d74, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1d75, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1d76, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1d77, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1d78, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1d79, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_WINDOW", REG_MMIO, 0x1d7a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_CONTROL", REG_MMIO, 0x1d7b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1d7d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_TOTAL", REG_MMIO, 0x1d80, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_START_END", REG_MMIO, 0x1d81, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A", REG_MMIO, 0x1d82, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1d83, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B", REG_MMIO, 0x1d84, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1d85, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VBI_END", REG_MMIO, 0x1d86, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL", REG_MMIO, 0x1d87, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1d88, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1d89, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1d8a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1d8b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1d8c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_BLANK_START_END", REG_MMIO, 0x1d8d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A", REG_MMIO, 0x1d8e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1d8f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B", REG_MMIO, 0x1d90, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1d91, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1d92, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1d93, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_CNTL", REG_MMIO, 0x1d94, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1d95, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_CNTL", REG_MMIO, 0x1d96, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1d97, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1d98, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FLOW_CONTROL", REG_MMIO, 0x1d99, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1d9a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1d9b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CONTROL", REG_MMIO, 0x1d9c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_CONTROL", REG_MMIO, 0x1d9d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1d9e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1d9f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1da0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1da1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1da2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS", REG_MMIO, 0x1da3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_POSITION", REG_MMIO, 0x1da4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1da5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1da6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1da7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1da8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_CONTROL", REG_MMIO, 0x1da9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_RESET", REG_MMIO, 0x1daa, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1dab, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1dac, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_STATUS", REG_MMIO, 0x1dad, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_CONTROL", REG_MMIO, 0x1dae, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1daf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1db0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1db1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1db2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1db3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1db4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_UPDATE_LOCK", REG_MMIO, 0x1db5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1db6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1db7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1dba, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1dbb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1dbc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x1dbd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x1dbe, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1dbf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1dc0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_STATUS", REG_MMIO, 0x1dc1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_EN", REG_MMIO, 0x1dc2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1dc3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1dc4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1dc6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1dc7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1dc8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1dc9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1dca, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1dcb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR", REG_MMIO, 0x1dcc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1dcd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1dce, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1dcf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1dd0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1dd1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1dd2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1dd3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC_CNTL", REG_MMIO, 0x1dd4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1dd5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1dd6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1dd7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1dd8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1dd9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_DATA_B", REG_MMIO, 0x1dda, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1ddb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1ddc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1ddd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1dde, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1ddf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_DATA_B", REG_MMIO, 0x1de0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1de1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1de2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1de3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1de4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1de5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1de6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1de7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1de8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1de9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1dea, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1deb, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1dec, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1ded, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CONTROL", REG_MMIO, 0x1dee, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x1df0, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_420_HBLANK_EARLY_START", REG_MMIO, 0x1df1, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1df2, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1df3, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1df4, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1df5, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1df6, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1df7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1df8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_CNTL", REG_MMIO, 0x1df9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_CNTL", REG_MMIO, 0x1dfa, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1dfb, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1dfc, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1dfd, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1dfe, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DEBUG_CNTL", REG_MMIO, 0x1dff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX_DEBUG_O", REG_SMC, 0x1e, &ixDP_AUX_DEBUG_O[0], sizeof(ixDP_AUX_DEBUG_O)/sizeof(ixDP_AUX_DEBUG_O[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1E", REG_SMC, 0x1e, &ixDCIO_DEBUG1E[0], sizeof(ixDCIO_DEBUG1E)/sizeof(ixDCIO_DEBUG1E[0]), 0, 0 },
+	{ "ixCRT1E", REG_SMC, 0x1e, &ixCRT1E[0], sizeof(ixCRT1E)/sizeof(ixCRT1E[0]), 0, 0 },
+	{ "mmDCP2_GRPH_ENABLE", REG_MMIO, 0x1e00, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_CONTROL", REG_MMIO, 0x1e01, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1e02, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SWAP_CNTL", REG_MMIO, 0x1e03, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1e04, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1e05, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PITCH", REG_MMIO, 0x1e06, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e07, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e08, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1e09, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1e0a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_START", REG_MMIO, 0x1e0b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_START", REG_MMIO, 0x1e0c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_END", REG_MMIO, 0x1e0d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_END", REG_MMIO, 0x1e0e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x1e0f, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1e10, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_UPDATE", REG_MMIO, 0x1e11, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_CONTROL", REG_MMIO, 0x1e12, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1e13, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_CONTROL", REG_MMIO, 0x1e14, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_STATUS", REG_MMIO, 0x1e15, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1e16, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1e17, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1e18, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1e19, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1e1a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e1b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x1e1c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x1e1d, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1e2d, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1e2e, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1e2f, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1e30, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_CONTROL", REG_MMIO, 0x1e35, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C11_C12", REG_MMIO, 0x1e36, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C13_C14", REG_MMIO, 0x1e37, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C21_C22", REG_MMIO, 0x1e38, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C23_C24", REG_MMIO, 0x1e39, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C31_C32", REG_MMIO, 0x1e3a, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C33_C34", REG_MMIO, 0x1e3b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1e3c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1e3d, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1e3e, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1e3f, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1e40, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1e41, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1e42, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1e43, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1e44, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1e45, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1e46, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1e47, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1e48, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1e49, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1e4a, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1e4b, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1e4c, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1e4d, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1e4e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DENORM_CONTROL", REG_MMIO, 0x1e50, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_ROUND_CONTROL", REG_MMIO, 0x1e51, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1e52, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_CONTROL", REG_MMIO, 0x1e53, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_ALPHA", REG_MMIO, 0x1e54, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_RED", REG_MMIO, 0x1e55, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_GREEN", REG_MMIO, 0x1e56, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_BLUE", REG_MMIO, 0x1e57, NULL, 0, 0, 0 },
+	{ "mmDCP2_DEGAMMA_CONTROL", REG_MMIO, 0x1e58, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1e59, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1e5a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1e5b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1e5c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1e5d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1e5e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1e5f, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1e60, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_RANDOM_SEEDS", REG_MMIO, 0x1e61, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1e65, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_CONTROL", REG_MMIO, 0x1e66, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1e67, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SIZE", REG_MMIO, 0x1e68, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1e69, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_POSITION", REG_MMIO, 0x1e6a, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_HOT_SPOT", REG_MMIO, 0x1e6b, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR1", REG_MMIO, 0x1e6c, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR2", REG_MMIO, 0x1e6d, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_UPDATE", REG_MMIO, 0x1e6e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_MODE", REG_MMIO, 0x1e78, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_INDEX", REG_MMIO, 0x1e79, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1e7a, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_PWL_DATA", REG_MMIO, 0x1e7b, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_30_COLOR", REG_MMIO, 0x1e7c, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1e7d, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1e7e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_AUTOFILL", REG_MMIO, 0x1e7f, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_CONTROL", REG_MMIO, 0x1e80, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1e81, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1e82, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1e83, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1e84, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1e85, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1e86, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CONTROL", REG_MMIO, 0x1e87, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_MASK", REG_MMIO, 0x1e88, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CURRENT", REG_MMIO, 0x1e89, NULL, 0, 0, 0 },
+	{ "mmDCP2_DVMM_PTE_CONTROL", REG_MMIO, 0x1e8a, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_LAST", REG_MMIO, 0x1e8b, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG", REG_MMIO, 0x1e8d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1e8e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_GSL_CONTROL", REG_MMIO, 0x1e90, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1e91, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG_SG", REG_MMIO, 0x1e92, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DVMM_DEBUG", REG_MMIO, 0x1e93, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG_SG2", REG_MMIO, 0x1e94, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1e95, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1e96, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1e97, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG2", REG_MMIO, 0x1e98, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1e99, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_STEREO_CONTROL", REG_MMIO, 0x1e9a, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1e9c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1e9d, NULL, 0, 0, 0 },
+	{ "mmDCP2_HW_ROTATION", REG_MMIO, 0x1e9e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1e9f, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CONTROL", REG_MMIO, 0x1ea0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_INDEX", REG_MMIO, 0x1ea1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_DATA", REG_MMIO, 0x1ea2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1ea3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1ea4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1ea5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1ea6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1ea7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1ea8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1ea9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1eaa, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1eab, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1eac, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1ead, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1eae, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1eaf, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1eb0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1eb1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1eb2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1eb3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1eb4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1eb5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1eb6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1eb7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1eb8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1eb9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1eba, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1ebb, NULL, 0, 0, 0 },
+	{ "mmDCP2_ALPHA_CONTROL", REG_MMIO, 0x1ebc, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1ebd, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1ebe, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1ebf, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DATA_FORMAT", REG_MMIO, 0x1ec0, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_MEMORY_CTRL", REG_MMIO, 0x1ec1, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ec2, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1ec3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE_START_END", REG_MMIO, 0x1ec4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE2_START_END", REG_MMIO, 0x1ec5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_V_COUNTER", REG_MMIO, 0x1ec6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ec7, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_INTERRUPT_MASK", REG_MMIO, 0x1ec8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE_STATUS", REG_MMIO, 0x1ec9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE2_STATUS", REG_MMIO, 0x1eca, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VBLANK_STATUS", REG_MMIO, 0x1ecb, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SYNC_RESET_SEL", REG_MMIO, 0x1ecc, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1ecd, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ece, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1ecf, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ed0, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ed1, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ed2, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ed3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ed4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ed5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ed6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ed7, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ed8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ed9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_STATUS", REG_MMIO, 0x1eda, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1edc, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ee0, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ee1, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ee2, NULL, 0, 0, 0 },
+	{ "mmLB2_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ee3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG", REG_MMIO, 0x1ee4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG2", REG_MMIO, 0x1ee5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG3", REG_MMIO, 0x1ee6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1efe, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1eff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX_DEBUG_P", REG_SMC, 0x1f, &ixDP_AUX_DEBUG_P[0], sizeof(ixDP_AUX_DEBUG_P)/sizeof(ixDP_AUX_DEBUG_P[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1F", REG_SMC, 0x1f, &ixDCIO_DEBUG1F[0], sizeof(ixDCIO_DEBUG1F)/sizeof(ixDCIO_DEBUG1F[0]), 0, 0 },
+	{ "ixCRT1F", REG_SMC, 0x1f, &ixCRT1F[0], sizeof(ixCRT1F)/sizeof(ixCRT1F[0]), 0, 0 },
+	{ "mmDCFE2_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1f00, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_SOFT_RESET", REG_MMIO, 0x1f01, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_DBG_CONFIG", REG_MMIO, 0x1f02, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x1f03, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0x1f04, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "mmDCFE2_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x1f04, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_SMC, 0x1f05, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmDCFE2_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x1f05, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_MISC", REG_MMIO, 0x1f06, NULL, 0, 0, 0 },
+	{ "mmDCFE2_DCFE_FLUSH", REG_MMIO, 0x1f07, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x1f0a, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_SMC, 0x1f0b, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_SMC, 0x1f0f, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmDC_PERFMON6_PERFCOUNTER_CNTL", REG_MMIO, 0x1f24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFCOUNTER_STATE", REG_MMIO, 0x1f25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1f26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CNTL", REG_MMIO, 0x1f27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CVALUE_LOW", REG_MMIO, 0x1f28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_HI", REG_MMIO, 0x1f29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_LOW", REG_MMIO, 0x1f2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1f2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1f2c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CNTL2", REG_MMIO, 0x1f2e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1f30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1f31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1f32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1f33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1f34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1f35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1f36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1f37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1f38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1f39, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1f3a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_A", REG_MMIO, 0x1f3b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_B", REG_MMIO, 0x1f3c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_11", REG_MMIO, 0x1f3d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x1f3e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_DVMM_STATUS", REG_MMIO, 0x1f3f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1f40, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1f41, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE", REG_MMIO, 0x1f42, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TAP_CONTROL", REG_MMIO, 0x1f43, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_CONTROL", REG_MMIO, 0x1f44, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_BYPASS_CONTROL", REG_MMIO, 0x1f45, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1f46, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1f47, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1f48, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1f49, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1f4a, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1f4b, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1f4c, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1f4d, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1f4e, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ROUND_OFFSET", REG_MMIO, 0x1f4f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_UPDATE", REG_MMIO, 0x1f51, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1f53, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ALU_CONTROL", REG_MMIO, 0x1f54, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1f55, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_START_SECONDARY", REG_MMIO, 0x1f5b, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_START", REG_MMIO, 0x1f5c, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_SIZE", REG_MMIO, 0x1f5d, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1f5e, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1f5f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1f60, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1f61, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1f62, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1f63, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG2", REG_MMIO, 0x1f69, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG", REG_MMIO, 0x1f6a, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1f6b, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1f6c, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_CONTROL", REG_MMIO, 0x1f6d, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_SM_CONTROL2", REG_MMIO, 0x1f6e, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_CONTROL2", REG_MMIO, 0x1f6f, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_UPDATE", REG_MMIO, 0x1f70, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1f71, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1f73, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_DEBUG", REG_MMIO, 0x1f74, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1f75, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1f76, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1f77, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1f78, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1f79, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_WINDOW", REG_MMIO, 0x1f7a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_CONTROL", REG_MMIO, 0x1f7b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1f7d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_TOTAL", REG_MMIO, 0x1f80, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_START_END", REG_MMIO, 0x1f81, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A", REG_MMIO, 0x1f82, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1f83, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B", REG_MMIO, 0x1f84, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1f85, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VBI_END", REG_MMIO, 0x1f86, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL", REG_MMIO, 0x1f87, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1f88, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1f89, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1f8a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1f8b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1f8c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_BLANK_START_END", REG_MMIO, 0x1f8d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A", REG_MMIO, 0x1f8e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1f8f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B", REG_MMIO, 0x1f90, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1f91, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1f92, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1f93, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_CNTL", REG_MMIO, 0x1f94, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1f95, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_CNTL", REG_MMIO, 0x1f96, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1f97, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1f98, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FLOW_CONTROL", REG_MMIO, 0x1f99, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1f9a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x1f9b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CONTROL", REG_MMIO, 0x1f9c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_CONTROL", REG_MMIO, 0x1f9d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1f9e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1f9f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1fa0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1fa1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1fa2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS", REG_MMIO, 0x1fa3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_POSITION", REG_MMIO, 0x1fa4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1fa5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1fa6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1fa7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1fa8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_CONTROL", REG_MMIO, 0x1fa9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_RESET", REG_MMIO, 0x1faa, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1fab, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1fac, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_STATUS", REG_MMIO, 0x1fad, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_CONTROL", REG_MMIO, 0x1fae, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1faf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1fb0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1fb1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1fb2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1fb3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1fb4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_UPDATE_LOCK", REG_MMIO, 0x1fb5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1fb6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1fb7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1fba, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1fbb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1fbc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x1fbd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x1fbe, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1fbf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1fc0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_STATUS", REG_MMIO, 0x1fc1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_EN", REG_MMIO, 0x1fc2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1fc3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1fc4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1fc6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1fc7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1fc8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1fc9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1fca, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1fcb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR", REG_MMIO, 0x1fcc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1fcd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1fce, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1fcf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1fd0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1fd1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1fd2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1fd3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC_CNTL", REG_MMIO, 0x1fd4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1fd5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1fd6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1fd7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1fd8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1fd9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_DATA_B", REG_MMIO, 0x1fda, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1fdb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1fdc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1fdd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1fde, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1fdf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_DATA_B", REG_MMIO, 0x1fe0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1fe1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1fe2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1fe3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1fe4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1fe5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1fe6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1fe7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1fe8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1fe9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1fea, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1feb, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1fec, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1fed, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CONTROL", REG_MMIO, 0x1fee, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x1ff0, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_420_HBLANK_EARLY_START", REG_MMIO, 0x1ff1, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1ff2, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1ff3, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1ff4, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1ff5, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1ff6, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1ff7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1ff8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_CNTL", REG_MMIO, 0x1ff9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_CNTL", REG_MMIO, 0x1ffa, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1ffb, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1ffc, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1ffd, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1ffe, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DEBUG_CNTL", REG_MMIO, 0x1fff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN", REG_SMC, 0x2, &ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0]), 0, 0 },
+	{ "ixAZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x2, &ixAZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL2", REG_SMC, 0x2, &ixAZALIA_INPUT_CRC0_CHANNEL2[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL2)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL2[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL2", REG_SMC, 0x2, &ixAZALIA_CRC0_CHANNEL2[0], sizeof(ixAZALIA_CRC0_CHANNEL2)/sizeof(ixAZALIA_CRC0_CHANNEL2[0]), 0, 0 },
+	{ "ixDMIF_DEBUG02_CORE0", REG_SMC, 0x2, &ixDMIF_DEBUG02_CORE0[0], sizeof(ixDMIF_DEBUG02_CORE0)/sizeof(ixDMIF_DEBUG02_CORE0[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR1", REG_SMC, 0x2, &ixAUDIO_DESCRIPTOR1[0], sizeof(ixAUDIO_DESCRIPTOR1)/sizeof(ixAUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "mmGLOBAL_CONTROL", REG_MMIO, 0x2, &mmGLOBAL_CONTROL[0], sizeof(mmGLOBAL_CONTROL)/sizeof(mmGLOBAL_CONTROL[0]), 0, 0 },
+	{ "ixDCIO_DEBUG2", REG_SMC, 0x2, &ixDCIO_DEBUG2[0], sizeof(ixDCIO_DEBUG2)/sizeof(ixDCIO_DEBUG2[0]), 0, 0 },
+	{ "ixFMT_DEBUG1", REG_SMC, 0x2, &ixFMT_DEBUG1[0], sizeof(ixFMT_DEBUG1)/sizeof(ixFMT_DEBUG1[0]), 0, 0 },
+	{ "ixATTR02", REG_SMC, 0x2, &ixATTR02[0], sizeof(ixATTR02)/sizeof(ixATTR02[0]), 0, 0 },
+	{ "ixSEQ02", REG_SMC, 0x2, &ixSEQ02[0], sizeof(ixSEQ02)/sizeof(ixSEQ02[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x20, &ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x20, &ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x20, &mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 },
+	{ "ixDP_AUX_DEBUG_Q", REG_SMC, 0x20, &ixDP_AUX_DEBUG_Q[0], sizeof(ixDP_AUX_DEBUG_Q)/sizeof(ixDP_AUX_DEBUG_Q[0]), 0, 0 },
+	{ "ixDCIO_DEBUG20", REG_SMC, 0x20, &ixDCIO_DEBUG20[0], sizeof(ixDCIO_DEBUG20)/sizeof(ixDCIO_DEBUG20[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x21, &mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x21, &ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x21, &ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixDCIO_DEBUG21", REG_SMC, 0x21, &ixDCIO_DEBUG21[0], sizeof(ixDCIO_DEBUG21)/sizeof(ixDCIO_DEBUG21[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x22, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x22, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x22, &mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 },
+	{ "ixDCIO_DEBUG22", REG_SMC, 0x22, &ixDCIO_DEBUG22[0], sizeof(ixDCIO_DEBUG22)/sizeof(ixDCIO_DEBUG22[0]), 0, 0 },
+	{ "ixCRT22", REG_SMC, 0x22, &ixCRT22[0], sizeof(ixCRT22)/sizeof(ixCRT22[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2200, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE", REG_SMC, 0x23, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x23, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x23, &mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 },
+	{ "ixDCIO_DEBUG23", REG_SMC, 0x23, &ixDCIO_DEBUG23[0], sizeof(ixDCIO_DEBUG23)/sizeof(ixDCIO_DEBUG23[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x24, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x24, &ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x24, &mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x24, &mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 },
+	{ "ixDCIO_DEBUG24", REG_SMC, 0x24, &ixDCIO_DEBUG24[0], sizeof(ixDCIO_DEBUG24)/sizeof(ixDCIO_DEBUG24[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x25, &ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 },
+	{ "ixDCIO_DEBUG25", REG_SMC, 0x25, &ixDCIO_DEBUG25[0], sizeof(ixDCIO_DEBUG25)/sizeof(ixDCIO_DEBUG25[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x26, &mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG26", REG_SMC, 0x26, &ixDCIO_DEBUG26[0], sizeof(ixDCIO_DEBUG26)/sizeof(ixDCIO_DEBUG26[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x27, &mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG27", REG_SMC, 0x27, &ixDCIO_DEBUG27[0], sizeof(ixDCIO_DEBUG27)/sizeof(ixDCIO_DEBUG27[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x2706, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x270d, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2", REG_SMC, 0x270e, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x2724, &ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3", REG_SMC, 0x273e, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x2770, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x2771, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x28, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "ixDCIO_DEBUG28", REG_SMC, 0x28, &ixDCIO_DEBUG28[0], sizeof(ixDCIO_DEBUG28)/sizeof(ixDCIO_DEBUG28[0]), 0, 0 },
+	{ "mmFBC_CNTL", REG_MMIO, 0x280, &mmFBC_CNTL[0], sizeof(mmFBC_CNTL)/sizeof(mmFBC_CNTL[0]), 0, 0 },
+	{ "mmFBC_IDLE_FORCE_CLEAR_MASK", REG_MMIO, 0x282, &mmFBC_IDLE_FORCE_CLEAR_MASK[0], sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK)/sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK[0]), 0, 0 },
+	{ "mmFBC_START_STOP_DELAY", REG_MMIO, 0x283, &mmFBC_START_STOP_DELAY[0], sizeof(mmFBC_START_STOP_DELAY)/sizeof(mmFBC_START_STOP_DELAY[0]), 0, 0 },
+	{ "mmFBC_COMP_CNTL", REG_MMIO, 0x284, &mmFBC_COMP_CNTL[0], sizeof(mmFBC_COMP_CNTL)/sizeof(mmFBC_COMP_CNTL[0]), 0, 0 },
+	{ "mmFBC_COMP_MODE", REG_MMIO, 0x285, &mmFBC_COMP_MODE[0], sizeof(mmFBC_COMP_MODE)/sizeof(mmFBC_COMP_MODE[0]), 0, 0 },
+	{ "mmFBC_DEBUG0", REG_MMIO, 0x286, &mmFBC_DEBUG0[0], sizeof(mmFBC_DEBUG0)/sizeof(mmFBC_DEBUG0[0]), 0, 0 },
+	{ "mmFBC_DEBUG1", REG_MMIO, 0x287, &mmFBC_DEBUG1[0], sizeof(mmFBC_DEBUG1)/sizeof(mmFBC_DEBUG1[0]), 0, 0 },
+	{ "mmFBC_DEBUG2", REG_MMIO, 0x288, &mmFBC_DEBUG2[0], sizeof(mmFBC_DEBUG2)/sizeof(mmFBC_DEBUG2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT0", REG_MMIO, 0x289, &mmFBC_IND_LUT0[0], sizeof(mmFBC_IND_LUT0)/sizeof(mmFBC_IND_LUT0[0]), 0, 0 },
+	{ "mmFBC_IND_LUT1", REG_MMIO, 0x28a, &mmFBC_IND_LUT1[0], sizeof(mmFBC_IND_LUT1)/sizeof(mmFBC_IND_LUT1[0]), 0, 0 },
+	{ "mmFBC_IND_LUT2", REG_MMIO, 0x28b, &mmFBC_IND_LUT2[0], sizeof(mmFBC_IND_LUT2)/sizeof(mmFBC_IND_LUT2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT3", REG_MMIO, 0x28c, &mmFBC_IND_LUT3[0], sizeof(mmFBC_IND_LUT3)/sizeof(mmFBC_IND_LUT3[0]), 0, 0 },
+	{ "mmFBC_IND_LUT4", REG_MMIO, 0x28d, &mmFBC_IND_LUT4[0], sizeof(mmFBC_IND_LUT4)/sizeof(mmFBC_IND_LUT4[0]), 0, 0 },
+	{ "mmFBC_IND_LUT5", REG_MMIO, 0x28e, &mmFBC_IND_LUT5[0], sizeof(mmFBC_IND_LUT5)/sizeof(mmFBC_IND_LUT5[0]), 0, 0 },
+	{ "mmFBC_IND_LUT6", REG_MMIO, 0x28f, &mmFBC_IND_LUT6[0], sizeof(mmFBC_IND_LUT6)/sizeof(mmFBC_IND_LUT6[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x29, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "mmFBC_IND_LUT7", REG_MMIO, 0x290, &mmFBC_IND_LUT7[0], sizeof(mmFBC_IND_LUT7)/sizeof(mmFBC_IND_LUT7[0]), 0, 0 },
+	{ "mmFBC_IND_LUT8", REG_MMIO, 0x291, &mmFBC_IND_LUT8[0], sizeof(mmFBC_IND_LUT8)/sizeof(mmFBC_IND_LUT8[0]), 0, 0 },
+	{ "mmFBC_IND_LUT9", REG_MMIO, 0x292, &mmFBC_IND_LUT9[0], sizeof(mmFBC_IND_LUT9)/sizeof(mmFBC_IND_LUT9[0]), 0, 0 },
+	{ "mmFBC_IND_LUT10", REG_MMIO, 0x293, &mmFBC_IND_LUT10[0], sizeof(mmFBC_IND_LUT10)/sizeof(mmFBC_IND_LUT10[0]), 0, 0 },
+	{ "mmFBC_IND_LUT11", REG_MMIO, 0x294, &mmFBC_IND_LUT11[0], sizeof(mmFBC_IND_LUT11)/sizeof(mmFBC_IND_LUT11[0]), 0, 0 },
+	{ "mmFBC_IND_LUT12", REG_MMIO, 0x295, &mmFBC_IND_LUT12[0], sizeof(mmFBC_IND_LUT12)/sizeof(mmFBC_IND_LUT12[0]), 0, 0 },
+	{ "mmFBC_IND_LUT13", REG_MMIO, 0x296, &mmFBC_IND_LUT13[0], sizeof(mmFBC_IND_LUT13)/sizeof(mmFBC_IND_LUT13[0]), 0, 0 },
+	{ "mmFBC_IND_LUT14", REG_MMIO, 0x297, &mmFBC_IND_LUT14[0], sizeof(mmFBC_IND_LUT14)/sizeof(mmFBC_IND_LUT14[0]), 0, 0 },
+	{ "mmFBC_IND_LUT15", REG_MMIO, 0x298, &mmFBC_IND_LUT15[0], sizeof(mmFBC_IND_LUT15)/sizeof(mmFBC_IND_LUT15[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_01", REG_MMIO, 0x299, &mmFBC_CSM_REGION_OFFSET_01[0], sizeof(mmFBC_CSM_REGION_OFFSET_01)/sizeof(mmFBC_CSM_REGION_OFFSET_01[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_23", REG_MMIO, 0x29a, &mmFBC_CSM_REGION_OFFSET_23[0], sizeof(mmFBC_CSM_REGION_OFFSET_23)/sizeof(mmFBC_CSM_REGION_OFFSET_23[0]), 0, 0 },
+	{ "mmFBC_CLIENT_REGION_MASK", REG_MMIO, 0x29b, &mmFBC_CLIENT_REGION_MASK[0], sizeof(mmFBC_CLIENT_REGION_MASK)/sizeof(mmFBC_CLIENT_REGION_MASK[0]), 0, 0 },
+	{ "mmFBC_DEBUG_COMP", REG_MMIO, 0x29c, &mmFBC_DEBUG_COMP[0], sizeof(mmFBC_DEBUG_COMP)/sizeof(mmFBC_DEBUG_COMP[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR", REG_MMIO, 0x29d, &mmFBC_DEBUG_CSR[0], sizeof(mmFBC_DEBUG_CSR)/sizeof(mmFBC_DEBUG_CSR[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA", REG_MMIO, 0x29e, &mmFBC_DEBUG_CSR_RDATA[0], sizeof(mmFBC_DEBUG_CSR_RDATA)/sizeof(mmFBC_DEBUG_CSR_RDATA[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA", REG_MMIO, 0x29f, &mmFBC_DEBUG_CSR_WDATA[0], sizeof(mmFBC_DEBUG_CSR_WDATA)/sizeof(mmFBC_DEBUG_CSR_WDATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x2a, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA_HI", REG_MMIO, 0x2a0, &mmFBC_DEBUG_CSR_RDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_RDATA_HI)/sizeof(mmFBC_DEBUG_CSR_RDATA_HI[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA_HI", REG_MMIO, 0x2a1, &mmFBC_DEBUG_CSR_WDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_WDATA_HI)/sizeof(mmFBC_DEBUG_CSR_WDATA_HI[0]), 0, 0 },
+	{ "mmFBC_MISC", REG_MMIO, 0x2a2, &mmFBC_MISC[0], sizeof(mmFBC_MISC)/sizeof(mmFBC_MISC[0]), 0, 0 },
+	{ "mmFBC_STATUS", REG_MMIO, 0x2a3, &mmFBC_STATUS[0], sizeof(mmFBC_STATUS)/sizeof(mmFBC_STATUS[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_INDEX", REG_MMIO, 0x2a4, &mmFBC_TEST_DEBUG_INDEX[0], sizeof(mmFBC_TEST_DEBUG_INDEX)/sizeof(mmFBC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_DATA", REG_MMIO, 0x2a5, &mmFBC_TEST_DEBUG_DATA[0], sizeof(mmFBC_TEST_DEBUG_DATA)/sizeof(mmFBC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmFBC_ALPHA_CNTL", REG_MMIO, 0x2a6, &mmFBC_ALPHA_CNTL[0], sizeof(mmFBC_ALPHA_CNTL)/sizeof(mmFBC_ALPHA_CNTL[0]), 0, 0 },
+	{ "mmFBC_ALPHA_RGB_OVERRIDE", REG_MMIO, 0x2a7, &mmFBC_ALPHA_RGB_OVERRIDE[0], sizeof(mmFBC_ALPHA_RGB_OVERRIDE)/sizeof(mmFBC_ALPHA_RGB_OVERRIDE[0]), 0, 0 },
+	{ "mmMVP_CONTROL1", REG_MMIO, 0x2ac, &mmMVP_CONTROL1[0], sizeof(mmMVP_CONTROL1)/sizeof(mmMVP_CONTROL1[0]), 0, 0 },
+	{ "mmMVP_CONTROL2", REG_MMIO, 0x2ad, &mmMVP_CONTROL2[0], sizeof(mmMVP_CONTROL2)/sizeof(mmMVP_CONTROL2[0]), 0, 0 },
+	{ "mmMVP_FIFO_CONTROL", REG_MMIO, 0x2ae, &mmMVP_FIFO_CONTROL[0], sizeof(mmMVP_FIFO_CONTROL)/sizeof(mmMVP_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmMVP_FIFO_STATUS", REG_MMIO, 0x2af, &mmMVP_FIFO_STATUS[0], sizeof(mmMVP_FIFO_STATUS)/sizeof(mmMVP_FIFO_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x2b, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "mmMVP_SLAVE_STATUS", REG_MMIO, 0x2b0, &mmMVP_SLAVE_STATUS[0], sizeof(mmMVP_SLAVE_STATUS)/sizeof(mmMVP_SLAVE_STATUS[0]), 0, 0 },
+	{ "mmMVP_INBAND_CNTL_CAP", REG_MMIO, 0x2b1, &mmMVP_INBAND_CNTL_CAP[0], sizeof(mmMVP_INBAND_CNTL_CAP)/sizeof(mmMVP_INBAND_CNTL_CAP[0]), 0, 0 },
+	{ "mmMVP_BLACK_KEYER", REG_MMIO, 0x2b2, &mmMVP_BLACK_KEYER[0], sizeof(mmMVP_BLACK_KEYER)/sizeof(mmMVP_BLACK_KEYER[0]), 0, 0 },
+	{ "mmMVP_CRC_CNTL", REG_MMIO, 0x2b3, &mmMVP_CRC_CNTL[0], sizeof(mmMVP_CRC_CNTL)/sizeof(mmMVP_CRC_CNTL[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_BLUE_GREEN", REG_MMIO, 0x2b4, &mmMVP_CRC_RESULT_BLUE_GREEN[0], sizeof(mmMVP_CRC_RESULT_BLUE_GREEN)/sizeof(mmMVP_CRC_RESULT_BLUE_GREEN[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_RED", REG_MMIO, 0x2b5, &mmMVP_CRC_RESULT_RED[0], sizeof(mmMVP_CRC_RESULT_RED)/sizeof(mmMVP_CRC_RESULT_RED[0]), 0, 0 },
+	{ "mmMVP_CONTROL3", REG_MMIO, 0x2b6, &mmMVP_CONTROL3[0], sizeof(mmMVP_CONTROL3)/sizeof(mmMVP_CONTROL3[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL1", REG_MMIO, 0x2b7, &mmMVP_RECEIVE_CNT_CNTL1[0], sizeof(mmMVP_RECEIVE_CNT_CNTL1)/sizeof(mmMVP_RECEIVE_CNT_CNTL1[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL2", REG_MMIO, 0x2b8, &mmMVP_RECEIVE_CNT_CNTL2[0], sizeof(mmMVP_RECEIVE_CNT_CNTL2)/sizeof(mmMVP_RECEIVE_CNT_CNTL2[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_INDEX", REG_MMIO, 0x2b9, &mmMVP_TEST_DEBUG_INDEX[0], sizeof(mmMVP_TEST_DEBUG_INDEX)/sizeof(mmMVP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_DATA", REG_MMIO, 0x2ba, &mmMVP_TEST_DEBUG_DATA[0], sizeof(mmMVP_TEST_DEBUG_DATA)/sizeof(mmMVP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMVP_DEBUG", REG_MMIO, 0x2bb, &mmMVP_DEBUG[0], sizeof(mmMVP_DEBUG)/sizeof(mmMVP_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x2c, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "mmPIPE0_PG_CONFIG", REG_MMIO, 0x2c0, &mmPIPE0_PG_CONFIG[0], sizeof(mmPIPE0_PG_CONFIG)/sizeof(mmPIPE0_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE0_PG_ENABLE", REG_MMIO, 0x2c1, &mmPIPE0_PG_ENABLE[0], sizeof(mmPIPE0_PG_ENABLE)/sizeof(mmPIPE0_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE0_PG_STATUS", REG_MMIO, 0x2c2, &mmPIPE0_PG_STATUS[0], sizeof(mmPIPE0_PG_STATUS)/sizeof(mmPIPE0_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE1_PG_CONFIG", REG_MMIO, 0x2c3, &mmPIPE1_PG_CONFIG[0], sizeof(mmPIPE1_PG_CONFIG)/sizeof(mmPIPE1_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE1_PG_ENABLE", REG_MMIO, 0x2c4, &mmPIPE1_PG_ENABLE[0], sizeof(mmPIPE1_PG_ENABLE)/sizeof(mmPIPE1_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE1_PG_STATUS", REG_MMIO, 0x2c5, &mmPIPE1_PG_STATUS[0], sizeof(mmPIPE1_PG_STATUS)/sizeof(mmPIPE1_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE2_PG_CONFIG", REG_MMIO, 0x2c6, &mmPIPE2_PG_CONFIG[0], sizeof(mmPIPE2_PG_CONFIG)/sizeof(mmPIPE2_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE2_PG_ENABLE", REG_MMIO, 0x2c7, &mmPIPE2_PG_ENABLE[0], sizeof(mmPIPE2_PG_ENABLE)/sizeof(mmPIPE2_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE2_PG_STATUS", REG_MMIO, 0x2c8, &mmPIPE2_PG_STATUS[0], sizeof(mmPIPE2_PG_STATUS)/sizeof(mmPIPE2_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE3_PG_CONFIG", REG_MMIO, 0x2c9, &mmPIPE3_PG_CONFIG[0], sizeof(mmPIPE3_PG_CONFIG)/sizeof(mmPIPE3_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE3_PG_ENABLE", REG_MMIO, 0x2ca, &mmPIPE3_PG_ENABLE[0], sizeof(mmPIPE3_PG_ENABLE)/sizeof(mmPIPE3_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE3_PG_STATUS", REG_MMIO, 0x2cb, &mmPIPE3_PG_STATUS[0], sizeof(mmPIPE3_PG_STATUS)/sizeof(mmPIPE3_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE4_PG_CONFIG", REG_MMIO, 0x2cc, &mmPIPE4_PG_CONFIG[0], sizeof(mmPIPE4_PG_CONFIG)/sizeof(mmPIPE4_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE4_PG_ENABLE", REG_MMIO, 0x2cd, &mmPIPE4_PG_ENABLE[0], sizeof(mmPIPE4_PG_ENABLE)/sizeof(mmPIPE4_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE4_PG_STATUS", REG_MMIO, 0x2ce, &mmPIPE4_PG_STATUS[0], sizeof(mmPIPE4_PG_STATUS)/sizeof(mmPIPE4_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE5_PG_CONFIG", REG_MMIO, 0x2cf, &mmPIPE5_PG_CONFIG[0], sizeof(mmPIPE5_PG_CONFIG)/sizeof(mmPIPE5_PG_CONFIG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x2d, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "mmPIPE5_PG_ENABLE", REG_MMIO, 0x2d0, &mmPIPE5_PG_ENABLE[0], sizeof(mmPIPE5_PG_ENABLE)/sizeof(mmPIPE5_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE5_PG_STATUS", REG_MMIO, 0x2d1, &mmPIPE5_PG_STATUS[0], sizeof(mmPIPE5_PG_STATUS)/sizeof(mmPIPE5_PG_STATUS[0]), 0, 0 },
+	{ "mmDC_IP_REQUEST_CNTL", REG_MMIO, 0x2d2, &mmDC_IP_REQUEST_CNTL[0], sizeof(mmDC_IP_REQUEST_CNTL)/sizeof(mmDC_IP_REQUEST_CNTL[0]), 0, 0 },
+	{ "mmDC_PGFSM_CONFIG_REG", REG_MMIO, 0x2d3, &mmDC_PGFSM_CONFIG_REG[0], sizeof(mmDC_PGFSM_CONFIG_REG)/sizeof(mmDC_PGFSM_CONFIG_REG[0]), 0, 0 },
+	{ "mmDC_PGFSM_WRITE_REG", REG_MMIO, 0x2d4, &mmDC_PGFSM_WRITE_REG[0], sizeof(mmDC_PGFSM_WRITE_REG)/sizeof(mmDC_PGFSM_WRITE_REG[0]), 0, 0 },
+	{ "mmDC_PGCNTL_STATUS_REG", REG_MMIO, 0x2d5, &mmDC_PGCNTL_STATUS_REG[0], sizeof(mmDC_PGCNTL_STATUS_REG)/sizeof(mmDC_PGCNTL_STATUS_REG[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_INDEX", REG_MMIO, 0x2d6, &mmDCPG_TEST_DEBUG_INDEX[0], sizeof(mmDCPG_TEST_DEBUG_INDEX)/sizeof(mmDCPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_DATA", REG_MMIO, 0x2d7, &mmDCPG_TEST_DEBUG_DATA[0], sizeof(mmDCPG_TEST_DEBUG_DATA)/sizeof(mmDCPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCPG_INTERRUPT_STATUS", REG_MMIO, 0x2de, &mmDCPG_INTERRUPT_STATUS[0], sizeof(mmDCPG_INTERRUPT_STATUS)/sizeof(mmDCPG_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDCPG_INTERRUPT_CONTROL", REG_MMIO, 0x2df, &mmDCPG_INTERRUPT_CONTROL[0], sizeof(mmDCPG_INTERRUPT_CONTROL)/sizeof(mmDCPG_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x2e, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "mmDCPG_INTERRUPT_CONTROL2", REG_MMIO, 0x2e0, &mmDCPG_INTERRUPT_CONTROL2[0], sizeof(mmDCPG_INTERRUPT_CONTROL2)/sizeof(mmDCPG_INTERRUPT_CONTROL2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x2f, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x2f09, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x2f0a, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x2f0b, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmDMIFV_STATUS", REG_MMIO, 0x2f5, &mmDMIFV_STATUS[0], sizeof(mmDMIFV_STATUS)/sizeof(mmDMIFV_STATUS[0]), 0, 0 },
+	{ "mmDMIF_CONTROL", REG_MMIO, 0x2f6, &mmDMIF_CONTROL[0], sizeof(mmDMIF_CONTROL)/sizeof(mmDMIF_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_STATUS", REG_MMIO, 0x2f7, &mmDMIF_STATUS[0], sizeof(mmDMIF_STATUS)/sizeof(mmDMIF_STATUS[0]), 0, 0 },
+	{ "mmDMIF_HW_DEBUG", REG_MMIO, 0x2f8, &mmDMIF_HW_DEBUG[0], sizeof(mmDMIF_HW_DEBUG)/sizeof(mmDMIF_HW_DEBUG[0]), 0, 0 },
+	{ "mmDMIF_ARBITRATION_CONTROL", REG_MMIO, 0x2f9, &mmDMIF_ARBITRATION_CONTROL[0], sizeof(mmDMIF_ARBITRATION_CONTROL)/sizeof(mmDMIF_ARBITRATION_CONTROL[0]), 0, 0 },
+	{ "mmPIPE0_ARBITRATION_CONTROL3", REG_MMIO, 0x2fa, &mmPIPE0_ARBITRATION_CONTROL3[0], sizeof(mmPIPE0_ARBITRATION_CONTROL3)/sizeof(mmPIPE0_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE1_ARBITRATION_CONTROL3", REG_MMIO, 0x2fb, &mmPIPE1_ARBITRATION_CONTROL3[0], sizeof(mmPIPE1_ARBITRATION_CONTROL3)/sizeof(mmPIPE1_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE2_ARBITRATION_CONTROL3", REG_MMIO, 0x2fc, &mmPIPE2_ARBITRATION_CONTROL3[0], sizeof(mmPIPE2_ARBITRATION_CONTROL3)/sizeof(mmPIPE2_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE3_ARBITRATION_CONTROL3", REG_MMIO, 0x2fd, &mmPIPE3_ARBITRATION_CONTROL3[0], sizeof(mmPIPE3_ARBITRATION_CONTROL3)/sizeof(mmPIPE3_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE4_ARBITRATION_CONTROL3", REG_MMIO, 0x2fe, &mmPIPE4_ARBITRATION_CONTROL3[0], sizeof(mmPIPE4_ARBITRATION_CONTROL3)/sizeof(mmPIPE4_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE5_ARBITRATION_CONTROL3", REG_MMIO, 0x2ff, &mmPIPE5_ARBITRATION_CONTROL3[0], sizeof(mmPIPE5_ARBITRATION_CONTROL3)/sizeof(mmPIPE5_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x3, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x3, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0", REG_SMC, 0x3, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0]), 0, 0 },
+	{ "ixAZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x3, &ixAZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL3", REG_SMC, 0x3, &ixAZALIA_INPUT_CRC0_CHANNEL3[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL3)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL3[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL3", REG_SMC, 0x3, &ixAZALIA_CRC0_CHANNEL3[0], sizeof(ixAZALIA_CRC0_CHANNEL3)/sizeof(ixAZALIA_CRC0_CHANNEL3[0]), 0, 0 },
+	{ "mmSTATE_CHANGE_STATUS", REG_MMIO, 0x3, &mmSTATE_CHANGE_STATUS[0], sizeof(mmSTATE_CHANGE_STATUS)/sizeof(mmSTATE_CHANGE_STATUS[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR2", REG_SMC, 0x3, &ixAUDIO_DESCRIPTOR2[0], sizeof(ixAUDIO_DESCRIPTOR2)/sizeof(ixAUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "ixDCIO_DEBUG3", REG_SMC, 0x3, &ixDCIO_DEBUG3[0], sizeof(ixDCIO_DEBUG3)/sizeof(ixDCIO_DEBUG3[0]), 0, 0 },
+	{ "ixFMT_DEBUG2", REG_SMC, 0x3, &ixFMT_DEBUG2[0], sizeof(ixFMT_DEBUG2)/sizeof(ixFMT_DEBUG2[0]), 0, 0 },
+	{ "ixATTR03", REG_SMC, 0x3, &ixATTR03[0], sizeof(ixATTR03)/sizeof(ixATTR03[0]), 0, 0 },
+	{ "ixSEQ03", REG_SMC, 0x3, &ixSEQ03[0], sizeof(ixSEQ03)/sizeof(ixSEQ03[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x30, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "mmDMIF_P_VMID", REG_MMIO, 0x300, &mmDMIF_P_VMID[0], sizeof(mmDMIF_P_VMID)/sizeof(mmDMIF_P_VMID[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_INDEX", REG_MMIO, 0x301, &mmDMIF_TEST_DEBUG_INDEX[0], sizeof(mmDMIF_TEST_DEBUG_INDEX)/sizeof(mmDMIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_DATA", REG_MMIO, 0x302, &mmDMIF_TEST_DEBUG_DATA[0], sizeof(mmDMIF_TEST_DEBUG_DATA)/sizeof(mmDMIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CALC", REG_MMIO, 0x303, &mmDMIF_ADDR_CALC[0], sizeof(mmDMIF_ADDR_CALC)/sizeof(mmDMIF_ADDR_CALC[0]), 0, 0 },
+	{ "mmDMIF_STATUS2", REG_MMIO, 0x304, &mmDMIF_STATUS2[0], sizeof(mmDMIF_STATUS2)/sizeof(mmDMIF_STATUS2[0]), 0, 0 },
+	{ "mmPIPE0_MAX_REQUESTS", REG_MMIO, 0x305, &mmPIPE0_MAX_REQUESTS[0], sizeof(mmPIPE0_MAX_REQUESTS)/sizeof(mmPIPE0_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE1_MAX_REQUESTS", REG_MMIO, 0x306, &mmPIPE1_MAX_REQUESTS[0], sizeof(mmPIPE1_MAX_REQUESTS)/sizeof(mmPIPE1_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE2_MAX_REQUESTS", REG_MMIO, 0x307, &mmPIPE2_MAX_REQUESTS[0], sizeof(mmPIPE2_MAX_REQUESTS)/sizeof(mmPIPE2_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE3_MAX_REQUESTS", REG_MMIO, 0x308, &mmPIPE3_MAX_REQUESTS[0], sizeof(mmPIPE3_MAX_REQUESTS)/sizeof(mmPIPE3_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE4_MAX_REQUESTS", REG_MMIO, 0x309, &mmPIPE4_MAX_REQUESTS[0], sizeof(mmPIPE4_MAX_REQUESTS)/sizeof(mmPIPE4_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE5_MAX_REQUESTS", REG_MMIO, 0x30a, &mmPIPE5_MAX_REQUESTS[0], sizeof(mmPIPE5_MAX_REQUESTS)/sizeof(mmPIPE5_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmLOW_POWER_TILING_CONTROL", REG_MMIO, 0x30b, &mmLOW_POWER_TILING_CONTROL[0], sizeof(mmLOW_POWER_TILING_CONTROL)/sizeof(mmLOW_POWER_TILING_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_CONTROL", REG_MMIO, 0x30c, &mmMCIF_CONTROL[0], sizeof(mmMCIF_CONTROL)/sizeof(mmMCIF_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WRITE_COMBINE_CONTROL", REG_MMIO, 0x30d, &mmMCIF_WRITE_COMBINE_CONTROL[0], sizeof(mmMCIF_WRITE_COMBINE_CONTROL)/sizeof(mmMCIF_WRITE_COMBINE_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_INDEX", REG_MMIO, 0x30e, &mmMCIF_TEST_DEBUG_INDEX[0], sizeof(mmMCIF_TEST_DEBUG_INDEX)/sizeof(mmMCIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_DATA", REG_MMIO, 0x30f, &mmMCIF_TEST_DEBUG_DATA[0], sizeof(mmMCIF_TEST_DEBUG_DATA)/sizeof(mmMCIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x31, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "mmMCIF_VMID", REG_MMIO, 0x310, &mmMCIF_VMID[0], sizeof(mmMCIF_VMID)/sizeof(mmMCIF_VMID[0]), 0, 0 },
+	{ "mmMCIF_MEM_CONTROL", REG_MMIO, 0x311, &mmMCIF_MEM_CONTROL[0], sizeof(mmMCIF_MEM_CONTROL)/sizeof(mmMCIF_MEM_CONTROL[0]), 0, 0 },
+	{ "mmCC_DC_PIPE_DIS", REG_MMIO, 0x312, &mmCC_DC_PIPE_DIS[0], sizeof(mmCC_DC_PIPE_DIS)/sizeof(mmCC_DC_PIPE_DIS[0]), 0, 0 },
+	{ "mmMC_DC_INTERFACE_NACK_STATUS", REG_MMIO, 0x313, &mmMC_DC_INTERFACE_NACK_STATUS[0], sizeof(mmMC_DC_INTERFACE_NACK_STATUS)/sizeof(mmMC_DC_INTERFACE_NACK_STATUS[0]), 0, 0 },
+	{ "mmRBBMIF_TIMEOUT", REG_MMIO, 0x314, &mmRBBMIF_TIMEOUT[0], sizeof(mmRBBMIF_TIMEOUT)/sizeof(mmRBBMIF_TIMEOUT[0]), 0, 0 },
+	{ "mmRBBMIF_STATUS", REG_MMIO, 0x315, &mmRBBMIF_STATUS[0], sizeof(mmRBBMIF_STATUS)/sizeof(mmRBBMIF_STATUS[0]), 0, 0 },
+	{ "mmRBBMIF_TIMEOUT_DIS", REG_MMIO, 0x316, &mmRBBMIF_TIMEOUT_DIS[0], sizeof(mmRBBMIF_TIMEOUT_DIS)/sizeof(mmRBBMIF_TIMEOUT_DIS[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATUS", REG_MMIO, 0x317, &mmDCI_MEM_PWR_STATUS[0], sizeof(mmDCI_MEM_PWR_STATUS)/sizeof(mmDCI_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATUS2", REG_MMIO, 0x318, &mmDCI_MEM_PWR_STATUS2[0], sizeof(mmDCI_MEM_PWR_STATUS2)/sizeof(mmDCI_MEM_PWR_STATUS2[0]), 0, 0 },
+	{ "mmDCI_CLK_CNTL", REG_MMIO, 0x319, &mmDCI_CLK_CNTL[0], sizeof(mmDCI_CLK_CNTL)/sizeof(mmDCI_CLK_CNTL[0]), 0, 0 },
+	{ "mmDCI_CLK_RAMP_CNTL", REG_MMIO, 0x31a, &mmDCI_CLK_RAMP_CNTL[0], sizeof(mmDCI_CLK_RAMP_CNTL)/sizeof(mmDCI_CLK_RAMP_CNTL[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL", REG_MMIO, 0x31b, &mmDCI_MEM_PWR_CNTL[0], sizeof(mmDCI_MEM_PWR_CNTL)/sizeof(mmDCI_MEM_PWR_CNTL[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL2", REG_MMIO, 0x31c, &mmDCI_MEM_PWR_CNTL2[0], sizeof(mmDCI_MEM_PWR_CNTL2)/sizeof(mmDCI_MEM_PWR_CNTL2[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL3", REG_MMIO, 0x31d, &mmDCI_MEM_PWR_CNTL3[0], sizeof(mmDCI_MEM_PWR_CNTL3)/sizeof(mmDCI_MEM_PWR_CNTL3[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_INDEX", REG_MMIO, 0x31e, &mmDCI_TEST_DEBUG_INDEX[0], sizeof(mmDCI_TEST_DEBUG_INDEX)/sizeof(mmDCI_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_DATA", REG_MMIO, 0x31f, &mmDCI_TEST_DEBUG_DATA[0], sizeof(mmDCI_TEST_DEBUG_DATA)/sizeof(mmDCI_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x32, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "mmDCI_DEBUG_CONFIG", REG_MMIO, 0x320, &mmDCI_DEBUG_CONFIG[0], sizeof(mmDCI_DEBUG_CONFIG)/sizeof(mmDCI_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE0_DMIF_BUFFER_CONTROL", REG_MMIO, 0x321, &mmPIPE0_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE0_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE0_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE1_DMIF_BUFFER_CONTROL", REG_MMIO, 0x322, &mmPIPE1_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE1_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE1_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE2_DMIF_BUFFER_CONTROL", REG_MMIO, 0x323, &mmPIPE2_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE2_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE2_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE3_DMIF_BUFFER_CONTROL", REG_MMIO, 0x324, &mmPIPE3_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE3_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE3_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE4_DMIF_BUFFER_CONTROL", REG_MMIO, 0x325, &mmPIPE4_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE4_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE4_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE5_DMIF_BUFFER_CONTROL", REG_MMIO, 0x326, &mmPIPE5_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE5_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE5_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmRBBMIF_STATUS_FLAG", REG_MMIO, 0x327, &mmRBBMIF_STATUS_FLAG[0], sizeof(mmRBBMIF_STATUS_FLAG)/sizeof(mmRBBMIF_STATUS_FLAG[0]), 0, 0 },
+	{ "mmDCI_SOFT_RESET", REG_MMIO, 0x328, &mmDCI_SOFT_RESET[0], sizeof(mmDCI_SOFT_RESET)/sizeof(mmDCI_SOFT_RESET[0]), 0, 0 },
+	{ "mmDMIF_URG_OVERRIDE", REG_MMIO, 0x329, &mmDMIF_URG_OVERRIDE[0], sizeof(mmDMIF_URG_OVERRIDE)/sizeof(mmDMIF_URG_OVERRIDE[0]), 0, 0 },
+	{ "mmPIPE6_ARBITRATION_CONTROL3", REG_MMIO, 0x32a, &mmPIPE6_ARBITRATION_CONTROL3[0], sizeof(mmPIPE6_ARBITRATION_CONTROL3)/sizeof(mmPIPE6_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE7_ARBITRATION_CONTROL3", REG_MMIO, 0x32b, &mmPIPE7_ARBITRATION_CONTROL3[0], sizeof(mmPIPE7_ARBITRATION_CONTROL3)/sizeof(mmPIPE7_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE6_MAX_REQUESTS", REG_MMIO, 0x32c, &mmPIPE6_MAX_REQUESTS[0], sizeof(mmPIPE6_MAX_REQUESTS)/sizeof(mmPIPE6_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE7_MAX_REQUESTS", REG_MMIO, 0x32d, &mmPIPE7_MAX_REQUESTS[0], sizeof(mmPIPE7_MAX_REQUESTS)/sizeof(mmPIPE7_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmDVMM_REG_RD_STATUS", REG_MMIO, 0x32e, &mmDVMM_REG_RD_STATUS[0], sizeof(mmDVMM_REG_RD_STATUS)/sizeof(mmDVMM_REG_RD_STATUS[0]), 0, 0 },
+	{ "mmDVMM_REG_RD_DATA", REG_MMIO, 0x32f, &mmDVMM_REG_RD_DATA[0], sizeof(mmDVMM_REG_RD_DATA)/sizeof(mmDVMM_REG_RD_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x33, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 },
+	{ "mmDVMM_PTE_REQ", REG_MMIO, 0x330, &mmDVMM_PTE_REQ[0], sizeof(mmDVMM_PTE_REQ)/sizeof(mmDVMM_PTE_REQ[0]), 0, 0 },
+	{ "mmDVMM_CNTL", REG_MMIO, 0x331, &mmDVMM_CNTL[0], sizeof(mmDVMM_CNTL)/sizeof(mmDVMM_CNTL[0]), 0, 0 },
+	{ "mmDVMM_FAULT_STATUS", REG_MMIO, 0x332, &mmDVMM_FAULT_STATUS[0], sizeof(mmDVMM_FAULT_STATUS)/sizeof(mmDVMM_FAULT_STATUS[0]), 0, 0 },
+	{ "mmDVMM_FAULT_ADDR", REG_MMIO, 0x333, &mmDVMM_FAULT_ADDR[0], sizeof(mmDVMM_FAULT_ADDR)/sizeof(mmDVMM_FAULT_ADDR[0]), 0, 0 },
+	{ "mmDVMM_PTE_PGMEM_CONTROL", REG_MMIO, 0x335, &mmDVMM_PTE_PGMEM_CONTROL[0], sizeof(mmDVMM_PTE_PGMEM_CONTROL)/sizeof(mmDVMM_PTE_PGMEM_CONTROL[0]), 0, 0 },
+	{ "mmDVMM_PTE_PGMEM_STATE", REG_MMIO, 0x336, &mmDVMM_PTE_PGMEM_STATE[0], sizeof(mmDVMM_PTE_PGMEM_STATE)/sizeof(mmDVMM_PTE_PGMEM_STATE[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL4", REG_MMIO, 0x33b, &mmDCI_MEM_PWR_CNTL4[0], sizeof(mmDCI_MEM_PWR_CNTL4)/sizeof(mmDCI_MEM_PWR_CNTL4[0]), 0, 0 },
+	{ "mmDCI_MISC", REG_MMIO, 0x33c, &mmDCI_MISC[0], sizeof(mmDCI_MISC)/sizeof(mmDCI_MISC[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATUS3", REG_MMIO, 0x33d, &mmDCI_MEM_PWR_STATUS3[0], sizeof(mmDCI_MEM_PWR_STATUS3)/sizeof(mmDCI_MEM_PWR_STATUS3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x34, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x35, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "mmDC_PERFMON1_PERFCOUNTER_CNTL", REG_MMIO, 0x358, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFCOUNTER_STATE", REG_MMIO, 0x359, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x35a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CNTL", REG_MMIO, 0x35b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CVALUE_LOW", REG_MMIO, 0x35c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_HI", REG_MMIO, 0x35d, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_LOW", REG_MMIO, 0x35e, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x35f, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x36, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x36, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x360, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CNTL2", REG_MMIO, 0x362, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFCOUNTER_CNTL", REG_MMIO, 0x364, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFCOUNTER_STATE", REG_MMIO, 0x365, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x366, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CNTL", REG_MMIO, 0x367, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CVALUE_LOW", REG_MMIO, 0x368, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_HI", REG_MMIO, 0x369, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_LOW", REG_MMIO, 0x36a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x36b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x36c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CNTL2", REG_MMIO, 0x36e, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x37, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x37, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY", REG_SMC, 0x3702, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x3707, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x3708, &ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x3709, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x371c, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x371d, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x371e, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x371f, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION", REG_SMC, 0x3770, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x3771, &ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO", REG_SMC, 0x3772, &ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE", REG_SMC, 0x3777, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE", REG_SMC, 0x3778, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE", REG_SMC, 0x3779, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE", REG_SMC, 0x377a, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC", REG_SMC, 0x377b, &ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_HBR", REG_SMC, 0x377c, &ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX", REG_SMC, 0x3780, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA", REG_SMC, 0x3781, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x3785, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x3786, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x3787, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x3788, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x3789, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x378a, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x378b, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x378c, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x378d, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x378e, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x378f, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x3790, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x3791, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x3792, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x3793, &ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x3797, &ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x3798, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x3799, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x379a, &ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x379b, &ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x379c, &ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x379d, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x379e, &ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x38, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x38, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x3a, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x3b, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x3c, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x3d, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x3e, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 },
+	{ "mmXDMA_MC_PCIE_CLIENT_CONFIG", REG_MMIO, 0x3e0, &mmXDMA_MC_PCIE_CLIENT_CONFIG[0], sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG)/sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING1", REG_MMIO, 0x3e1, &mmXDMA_LOCAL_SURFACE_TILING1[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING1)/sizeof(mmXDMA_LOCAL_SURFACE_TILING1[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING2", REG_MMIO, 0x3e2, &mmXDMA_LOCAL_SURFACE_TILING2[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING2)/sizeof(mmXDMA_LOCAL_SURFACE_TILING2[0]), 0, 0 },
+	{ "mmXDMA_INTERRUPT", REG_MMIO, 0x3e3, &mmXDMA_INTERRUPT[0], sizeof(mmXDMA_INTERRUPT)/sizeof(mmXDMA_INTERRUPT[0]), 0, 0 },
+	{ "mmXDMA_CLOCK_GATING_CNTL", REG_MMIO, 0x3e4, &mmXDMA_CLOCK_GATING_CNTL[0], sizeof(mmXDMA_CLOCK_GATING_CNTL)/sizeof(mmXDMA_CLOCK_GATING_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MEM_POWER_CNTL", REG_MMIO, 0x3e6, &mmXDMA_MEM_POWER_CNTL[0], sizeof(mmXDMA_MEM_POWER_CNTL)/sizeof(mmXDMA_MEM_POWER_CNTL[0]), 0, 0 },
+	{ "mmXDMA_IF_BIF_STATUS", REG_MMIO, 0x3e7, &mmXDMA_IF_BIF_STATUS[0], sizeof(mmXDMA_IF_BIF_STATUS)/sizeof(mmXDMA_IF_BIF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_PERF_MEAS_STATUS", REG_MMIO, 0x3e8, &mmXDMA_PERF_MEAS_STATUS[0], sizeof(mmXDMA_PERF_MEAS_STATUS)/sizeof(mmXDMA_PERF_MEAS_STATUS[0]), 0, 0 },
+	{ "mmXDMA_IF_STATUS", REG_MMIO, 0x3e9, &mmXDMA_IF_STATUS[0], sizeof(mmXDMA_IF_STATUS)/sizeof(mmXDMA_IF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_INDEX", REG_MMIO, 0x3ea, &mmXDMA_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_TEST_DEBUG_INDEX)/sizeof(mmXDMA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_DATA", REG_MMIO, 0x3eb, &mmXDMA_TEST_DEBUG_DATA[0], sizeof(mmXDMA_TEST_DEBUG_DATA)/sizeof(mmXDMA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CNTL", REG_MMIO, 0x3ec, &mmXDMA_MSTR_CNTL[0], sizeof(mmXDMA_MSTR_CNTL)/sizeof(mmXDMA_MSTR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_STATUS", REG_MMIO, 0x3ed, &mmXDMA_MSTR_STATUS[0], sizeof(mmXDMA_MSTR_STATUS)/sizeof(mmXDMA_MSTR_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_CLIENT_CONFIG", REG_MMIO, 0x3ee, &mmXDMA_MSTR_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", REG_MMIO, 0x3ef, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x3f, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", REG_MMIO, 0x3f0, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x3f09, &ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x3f0c, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH", REG_SMC, 0x3f0e, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_PITCH", REG_MMIO, 0x3f1, &mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CMD_URGENT_CNTL", REG_MMIO, 0x3f2, &mmXDMA_MSTR_CMD_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL)/sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_URGENT_CNTL", REG_MMIO, 0x3f3, &mmXDMA_MSTR_MEM_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL)/sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PCIE_NACK_STATUS", REG_MMIO, 0x3f5, &mmXDMA_MSTR_PCIE_NACK_STATUS[0], sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS)/sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_NACK_STATUS", REG_MMIO, 0x3f6, &mmXDMA_MSTR_MEM_NACK_STATUS[0], sizeof(mmXDMA_MSTR_MEM_NACK_STATUS)/sizeof(mmXDMA_MSTR_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_VSYNC_GSL_CHECK", REG_MMIO, 0x3f7, &mmXDMA_MSTR_VSYNC_GSL_CHECK[0], sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK)/sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK[0]), 0, 0 },
+	{ "mmXDMA_RBBMIF_RDWR_CNTL", REG_MMIO, 0x3f8, &mmXDMA_RBBMIF_RDWR_CNTL[0], sizeof(mmXDMA_RBBMIF_RDWR_CNTL)/sizeof(mmXDMA_RBBMIF_RDWR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_PG_CONTROL", REG_MMIO, 0x3f9, &mmXDMA_PG_CONTROL[0], sizeof(mmXDMA_PG_CONTROL)/sizeof(mmXDMA_PG_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_PG_WDATA", REG_MMIO, 0x3fa, &mmXDMA_PG_WDATA[0], sizeof(mmXDMA_PG_WDATA)/sizeof(mmXDMA_PG_WDATA[0]), 0, 0 },
+	{ "mmXDMA_PG_STATUS", REG_MMIO, 0x3fb, &mmXDMA_PG_STATUS[0], sizeof(mmXDMA_PG_STATUS)/sizeof(mmXDMA_PG_STATUS[0]), 0, 0 },
+	{ "mmXDMA_AON_TEST_DEBUG_INDEX", REG_MMIO, 0x3fc, &mmXDMA_AON_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_AON_TEST_DEBUG_INDEX)/sizeof(mmXDMA_AON_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_AON_TEST_DEBUG_DATA", REG_MMIO, 0x3fd, &mmXDMA_AON_TEST_DEBUG_DATA[0], sizeof(mmXDMA_AON_TEST_DEBUG_DATA)/sizeof(mmXDMA_AON_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x4, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x4, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1", REG_SMC, 0x4, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0]), 0, 0 },
+	{ "ixAZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x4, &ixAZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL4", REG_SMC, 0x4, &ixAZALIA_INPUT_CRC0_CHANNEL4[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL4)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL4[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL4", REG_SMC, 0x4, &ixAZALIA_CRC0_CHANNEL4[0], sizeof(ixAZALIA_CRC0_CHANNEL4)/sizeof(ixAZALIA_CRC0_CHANNEL4[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR3", REG_SMC, 0x4, &ixAUDIO_DESCRIPTOR3[0], sizeof(ixAUDIO_DESCRIPTOR3)/sizeof(ixAUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "mmGLOBAL_STATUS", REG_MMIO, 0x4, &mmGLOBAL_STATUS[0], sizeof(mmGLOBAL_STATUS)/sizeof(mmGLOBAL_STATUS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG4", REG_SMC, 0x4, &ixDCIO_DEBUG4[0], sizeof(ixDCIO_DEBUG4)/sizeof(ixDCIO_DEBUG4[0]), 0, 0 },
+	{ "ixFMT_DEBUG3", REG_SMC, 0x4, &ixFMT_DEBUG3[0], sizeof(ixFMT_DEBUG3)/sizeof(ixFMT_DEBUG3[0]), 0, 0 },
+	{ "ixATTR04", REG_SMC, 0x4, &ixATTR04[0], sizeof(ixATTR04)/sizeof(ixATTR04[0]), 0, 0 },
+	{ "ixSEQ04", REG_SMC, 0x4, &ixSEQ04[0], sizeof(ixSEQ04)/sizeof(ixSEQ04[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x40, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, &mmXDMA_MSTR_PIPE_CNTL[0], sizeof(mmXDMA_MSTR_PIPE_CNTL)/sizeof(mmXDMA_MSTR_PIPE_CNTL[0]), 0, 0 },
+	{ "mmDCP3_GRPH_ENABLE", REG_MMIO, 0x4000, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_CONTROL", REG_MMIO, 0x4001, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4002, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SWAP_CNTL", REG_MMIO, 0x4003, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4004, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4005, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PITCH", REG_MMIO, 0x4006, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4007, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4008, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4009, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x400a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_START", REG_MMIO, 0x400b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_START", REG_MMIO, 0x400c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_END", REG_MMIO, 0x400d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_END", REG_MMIO, 0x400e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x400f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, &mmXDMA_MSTR_READ_COMMAND[0], sizeof(mmXDMA_MSTR_READ_COMMAND)/sizeof(mmXDMA_MSTR_READ_COMMAND[0]), 0, 0 },
+	{ "mmDCP3_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4010, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_UPDATE", REG_MMIO, 0x4011, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_CONTROL", REG_MMIO, 0x4012, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4013, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_CONTROL", REG_MMIO, 0x4014, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_STATUS", REG_MMIO, 0x4015, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4016, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4017, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4018, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4019, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_PITCH", REG_MMIO, 0x401a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x401b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x401c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x401d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, &mmXDMA_MSTR_CHANNEL_DIM[0], sizeof(mmXDMA_MSTR_CHANNEL_DIM)/sizeof(mmXDMA_MSTR_CHANNEL_DIM[0]), 0, 0 },
+	{ "mmDCP3_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x402d, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x402e, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x402f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_HEIGHT", REG_MMIO, 0x403, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_HEIGHT", REG_MMIO, 0x403, &mmXDMA_MSTR_HEIGHT[0], sizeof(mmXDMA_MSTR_HEIGHT)/sizeof(mmXDMA_MSTR_HEIGHT[0]), 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4030, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_CONTROL", REG_MMIO, 0x4035, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C11_C12", REG_MMIO, 0x4036, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C13_C14", REG_MMIO, 0x4037, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C21_C22", REG_MMIO, 0x4038, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C23_C24", REG_MMIO, 0x4039, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C31_C32", REG_MMIO, 0x403a, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C33_C34", REG_MMIO, 0x403b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_CONTROL", REG_MMIO, 0x403c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C11_C12", REG_MMIO, 0x403d, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C13_C14", REG_MMIO, 0x403e, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C21_C22", REG_MMIO, 0x403f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, &mmXDMA_MSTR_REMOTE_SURFACE_BASE[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE[0]), 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4040, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4041, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4042, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4043, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4044, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4045, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4046, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4047, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4048, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4049, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x404a, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x404b, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x404c, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x404d, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x404e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, &mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DENORM_CONTROL", REG_MMIO, 0x4050, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_ROUND_CONTROL", REG_MMIO, 0x4051, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4052, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_CONTROL", REG_MMIO, 0x4053, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_ALPHA", REG_MMIO, 0x4054, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_RED", REG_MMIO, 0x4055, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_GREEN", REG_MMIO, 0x4056, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_BLUE", REG_MMIO, 0x4057, NULL, 0, 0, 0 },
+	{ "mmDCP3_DEGAMMA_CONTROL", REG_MMIO, 0x4058, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4059, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C11_C12", REG_MMIO, 0x405a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C13_C14", REG_MMIO, 0x405b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C21_C22", REG_MMIO, 0x405c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C23_C24", REG_MMIO, 0x405d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C31_C32", REG_MMIO, 0x405e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C33_C34", REG_MMIO, 0x405f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmDCP3_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4060, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_RANDOM_SEEDS", REG_MMIO, 0x4061, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4065, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_CONTROL", REG_MMIO, 0x4066, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4067, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SIZE", REG_MMIO, 0x4068, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4069, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_POSITION", REG_MMIO, 0x406a, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_HOT_SPOT", REG_MMIO, 0x406b, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR1", REG_MMIO, 0x406c, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR2", REG_MMIO, 0x406d, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_UPDATE", REG_MMIO, 0x406e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_MODE", REG_MMIO, 0x4078, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_INDEX", REG_MMIO, 0x4079, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_SEQ_COLOR", REG_MMIO, 0x407a, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_PWL_DATA", REG_MMIO, 0x407b, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_30_COLOR", REG_MMIO, 0x407c, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x407d, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x407e, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_AUTOFILL", REG_MMIO, 0x407f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, &mmXDMA_MSTR_CACHE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR[0]), 0, 0 },
+	{ "mmDCP3_DC_LUT_CONTROL", REG_MMIO, 0x4080, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4081, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4082, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4083, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4084, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4085, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4086, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CONTROL", REG_MMIO, 0x4087, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_MASK", REG_MMIO, 0x4088, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CURRENT", REG_MMIO, 0x4089, NULL, 0, 0, 0 },
+	{ "mmDCP3_DVMM_PTE_CONTROL", REG_MMIO, 0x408a, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_LAST", REG_MMIO, 0x408b, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG", REG_MMIO, 0x408d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x408e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, &mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "mmDCP3_DCP_GSL_CONTROL", REG_MMIO, 0x4090, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4091, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG_SG", REG_MMIO, 0x4092, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DVMM_DEBUG", REG_MMIO, 0x4093, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG_SG2", REG_MMIO, 0x4094, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4095, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4096, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4097, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG2", REG_MMIO, 0x4098, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4099, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_STEREO_CONTROL", REG_MMIO, 0x409a, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x409c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x409d, NULL, 0, 0, 0 },
+	{ "mmDCP3_HW_ROTATION", REG_MMIO, 0x409e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x409f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CACHE", REG_MMIO, 0x40a, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE", REG_MMIO, 0x40a, &mmXDMA_MSTR_CACHE[0], sizeof(mmXDMA_MSTR_CACHE)/sizeof(mmXDMA_MSTR_CACHE[0]), 0, 0 },
+	{ "mmDCP3_REGAMMA_CONTROL", REG_MMIO, 0x40a0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_INDEX", REG_MMIO, 0x40a1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_DATA", REG_MMIO, 0x40a2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x40a3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x40a4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x40a5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x40a6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x40a7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x40a8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x40a9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x40aa, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x40ab, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x40ac, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x40ad, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x40ae, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x40af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, &mmXDMA_MSTR_CHANNEL_START[0], sizeof(mmXDMA_MSTR_CHANNEL_START)/sizeof(mmXDMA_MSTR_CHANNEL_START[0]), 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x40b0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x40b1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x40b2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x40b3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x40b4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x40b5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x40b6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x40b7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x40b8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x40b9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x40ba, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x40bb, NULL, 0, 0, 0 },
+	{ "mmDCP3_ALPHA_CONTROL", REG_MMIO, 0x40bc, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x40bd, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x40be, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x40bf, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DATA_FORMAT", REG_MMIO, 0x40c0, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_MEMORY_CTRL", REG_MMIO, 0x40c1, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x40c2, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DESKTOP_HEIGHT", REG_MMIO, 0x40c3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE_START_END", REG_MMIO, 0x40c4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE2_START_END", REG_MMIO, 0x40c5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_V_COUNTER", REG_MMIO, 0x40c6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x40c7, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_INTERRUPT_MASK", REG_MMIO, 0x40c8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE_STATUS", REG_MMIO, 0x40c9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE2_STATUS", REG_MMIO, 0x40ca, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VBLANK_STATUS", REG_MMIO, 0x40cb, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SYNC_RESET_SEL", REG_MMIO, 0x40cc, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x40cd, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x40ce, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x40cf, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x40d0, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x40d1, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x40d2, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x40d3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x40d4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x40d5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x40d6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x40d7, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x40d8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x40d9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_STATUS", REG_MMIO, 0x40da, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x40dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, &mmXDMA_MSTR_PERFMEAS_STATUS[0], sizeof(mmXDMA_MSTR_PERFMEAS_STATUS)/sizeof(mmXDMA_MSTR_PERFMEAS_STATUS[0]), 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_MODE", REG_MMIO, 0x40e0, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x40e1, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x40e2, NULL, 0, 0, 0 },
+	{ "mmLB3_DC_MVP_LB_CONTROL", REG_MMIO, 0x40e3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG", REG_MMIO, 0x40e4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG2", REG_MMIO, 0x40e5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG3", REG_MMIO, 0x40e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE0_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, &mmXDMA_MSTR_PERFMEAS_CNTL[0], sizeof(mmXDMA_MSTR_PERFMEAS_CNTL)/sizeof(mmXDMA_MSTR_PERFMEAS_CNTL[0]), 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x40fe, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_DATA", REG_MMIO, 0x40ff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x41, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x410, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4100, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_SOFT_RESET", REG_MMIO, 0x4101, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_DBG_CONFIG", REG_MMIO, 0x4102, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x4103, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x4104, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x4105, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_MISC", REG_MMIO, 0x4106, NULL, 0, 0, 0 },
+	{ "mmDCFE3_DCFE_FLUSH", REG_MMIO, 0x4107, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x411, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x412, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFCOUNTER_CNTL", REG_MMIO, 0x4124, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFCOUNTER_STATE", REG_MMIO, 0x4125, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4126, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CNTL", REG_MMIO, 0x4127, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CVALUE_LOW", REG_MMIO, 0x4128, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_HI", REG_MMIO, 0x4129, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_LOW", REG_MMIO, 0x412a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x412b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x412c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CNTL2", REG_MMIO, 0x412e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_HEIGHT", REG_MMIO, 0x413, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4130, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4131, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4132, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4133, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4134, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4135, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4136, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4137, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4138, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4139, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_REPEATER_PROGRAM", REG_MMIO, 0x413a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_A", REG_MMIO, 0x413b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_B", REG_MMIO, 0x413c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_11", REG_MMIO, 0x413d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x413e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_DVMM_STATUS", REG_MMIO, 0x413f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x414, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4140, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4141, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE", REG_MMIO, 0x4142, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TAP_CONTROL", REG_MMIO, 0x4143, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_CONTROL", REG_MMIO, 0x4144, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_BYPASS_CONTROL", REG_MMIO, 0x4145, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4146, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4147, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4148, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4149, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x414a, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x414b, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x414c, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT", REG_MMIO, 0x414d, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x414e, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ROUND_OFFSET", REG_MMIO, 0x414f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x415, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_UPDATE", REG_MMIO, 0x4151, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4153, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ALU_CONTROL", REG_MMIO, 0x4154, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4155, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_START_SECONDARY", REG_MMIO, 0x415b, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_START", REG_MMIO, 0x415c, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_SIZE", REG_MMIO, 0x415d, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x415e, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x415f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x416, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4160, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4161, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4162, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4163, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG2", REG_MMIO, 0x4169, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG", REG_MMIO, 0x416a, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x416b, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x416c, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_CONTROL", REG_MMIO, 0x416d, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_SM_CONTROL2", REG_MMIO, 0x416e, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_CONTROL2", REG_MMIO, 0x416f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x417, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_UPDATE", REG_MMIO, 0x4170, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4171, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4173, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_DEBUG", REG_MMIO, 0x4174, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4175, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4176, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4177, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4178, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4179, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_WINDOW", REG_MMIO, 0x417a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_CONTROL", REG_MMIO, 0x417b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x417d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x418, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_TOTAL", REG_MMIO, 0x4180, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_START_END", REG_MMIO, 0x4181, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A", REG_MMIO, 0x4182, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4183, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B", REG_MMIO, 0x4184, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4185, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VBI_END", REG_MMIO, 0x4186, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL", REG_MMIO, 0x4187, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4188, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4189, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x418a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x418b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x418c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_BLANK_START_END", REG_MMIO, 0x418d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A", REG_MMIO, 0x418e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x418f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x419, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B", REG_MMIO, 0x4190, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4191, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4192, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4193, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_CNTL", REG_MMIO, 0x4194, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4195, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_CNTL", REG_MMIO, 0x4196, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4197, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4198, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FLOW_CONTROL", REG_MMIO, 0x4199, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x419a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x419b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CONTROL", REG_MMIO, 0x419c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_CONTROL", REG_MMIO, 0x419d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x419e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_STATUS", REG_MMIO, 0x419f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CACHE", REG_MMIO, 0x41a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x41a0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x41a1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x41a2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS", REG_MMIO, 0x41a3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_POSITION", REG_MMIO, 0x41a4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x41a5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x41a6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x41a7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x41a8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_CONTROL", REG_MMIO, 0x41a9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_RESET", REG_MMIO, 0x41aa, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x41ab, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x41ac, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_STATUS", REG_MMIO, 0x41ad, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_CONTROL", REG_MMIO, 0x41ae, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x41af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x41b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x41b0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x41b1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x41b2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_START_LINE_CONTROL", REG_MMIO, 0x41b3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x41b4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_UPDATE_LOCK", REG_MMIO, 0x41b5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x41b6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x41b7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x41ba, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x41bb, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x41bc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x41bd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x41be, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x41bf, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x41c0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_STATUS", REG_MMIO, 0x41c1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_EN", REG_MMIO, 0x41c2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x41c3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x41c4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x41c6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x41c7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x41c8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x41c9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x41ca, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x41cb, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR", REG_MMIO, 0x41cc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x41cd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x41ce, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x41cf, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x41d0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x41d1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x41d2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x41d3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC_CNTL", REG_MMIO, 0x41d4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x41d5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x41d6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x41d7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x41d8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_DATA_RG", REG_MMIO, 0x41d9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_DATA_B", REG_MMIO, 0x41da, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x41db, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x41dc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x41dd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x41de, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_DATA_RG", REG_MMIO, 0x41df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x41e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_DATA_B", REG_MMIO, 0x41e0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x41e1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x41e2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x41e3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x41e4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x41e5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x41e6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x41e7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x41e8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x41e9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x41ea, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x41eb, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x41ec, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x41ed, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CONTROL", REG_MMIO, 0x41ee, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE1_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x41f, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x41f0, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_420_HBLANK_EARLY_START", REG_MMIO, 0x41f1, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x41f2, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x41f3, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x41f4, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x41f5, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x41f6, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x41f7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x41f8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_CNTL", REG_MMIO, 0x41f9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_CNTL", REG_MMIO, 0x41fa, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x41fb, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x41fc, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x41fd, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x41fe, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DEBUG_CNTL", REG_MMIO, 0x41ff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x42, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x420, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_ENABLE", REG_MMIO, 0x4200, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_CONTROL", REG_MMIO, 0x4201, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4202, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SWAP_CNTL", REG_MMIO, 0x4203, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4204, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4205, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PITCH", REG_MMIO, 0x4206, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4207, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4208, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4209, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x420a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_START", REG_MMIO, 0x420b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_START", REG_MMIO, 0x420c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_END", REG_MMIO, 0x420d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_END", REG_MMIO, 0x420e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x420f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x421, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4210, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_UPDATE", REG_MMIO, 0x4211, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_CONTROL", REG_MMIO, 0x4212, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4213, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_CONTROL", REG_MMIO, 0x4214, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_STATUS", REG_MMIO, 0x4215, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4216, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4217, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4218, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4219, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_PITCH", REG_MMIO, 0x421a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x421b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x421c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x421d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x422, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x422d, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x422e, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x422f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_HEIGHT", REG_MMIO, 0x423, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4230, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_CONTROL", REG_MMIO, 0x4235, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C11_C12", REG_MMIO, 0x4236, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C13_C14", REG_MMIO, 0x4237, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C21_C22", REG_MMIO, 0x4238, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C23_C24", REG_MMIO, 0x4239, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C31_C32", REG_MMIO, 0x423a, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C33_C34", REG_MMIO, 0x423b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_CONTROL", REG_MMIO, 0x423c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C11_C12", REG_MMIO, 0x423d, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C13_C14", REG_MMIO, 0x423e, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C21_C22", REG_MMIO, 0x423f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x424, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4240, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4241, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4242, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4243, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4244, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4245, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4246, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4247, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4248, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4249, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x424a, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x424b, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x424c, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x424d, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x424e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x425, NULL, 0, 0, 0 },
+	{ "mmDCP4_DENORM_CONTROL", REG_MMIO, 0x4250, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_ROUND_CONTROL", REG_MMIO, 0x4251, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4252, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_CONTROL", REG_MMIO, 0x4253, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_ALPHA", REG_MMIO, 0x4254, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_RED", REG_MMIO, 0x4255, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_GREEN", REG_MMIO, 0x4256, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_BLUE", REG_MMIO, 0x4257, NULL, 0, 0, 0 },
+	{ "mmDCP4_DEGAMMA_CONTROL", REG_MMIO, 0x4258, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4259, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C11_C12", REG_MMIO, 0x425a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C13_C14", REG_MMIO, 0x425b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C21_C22", REG_MMIO, 0x425c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C23_C24", REG_MMIO, 0x425d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C31_C32", REG_MMIO, 0x425e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C33_C34", REG_MMIO, 0x425f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x426, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4260, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_RANDOM_SEEDS", REG_MMIO, 0x4261, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4265, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_CONTROL", REG_MMIO, 0x4266, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4267, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SIZE", REG_MMIO, 0x4268, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4269, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_POSITION", REG_MMIO, 0x426a, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_HOT_SPOT", REG_MMIO, 0x426b, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR1", REG_MMIO, 0x426c, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR2", REG_MMIO, 0x426d, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_UPDATE", REG_MMIO, 0x426e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x427, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_MODE", REG_MMIO, 0x4278, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_INDEX", REG_MMIO, 0x4279, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_SEQ_COLOR", REG_MMIO, 0x427a, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_PWL_DATA", REG_MMIO, 0x427b, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_30_COLOR", REG_MMIO, 0x427c, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x427d, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x427e, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_AUTOFILL", REG_MMIO, 0x427f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x428, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_CONTROL", REG_MMIO, 0x4280, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4281, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4282, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4283, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4284, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4285, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4286, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CONTROL", REG_MMIO, 0x4287, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_MASK", REG_MMIO, 0x4288, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CURRENT", REG_MMIO, 0x4289, NULL, 0, 0, 0 },
+	{ "mmDCP4_DVMM_PTE_CONTROL", REG_MMIO, 0x428a, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_LAST", REG_MMIO, 0x428b, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG", REG_MMIO, 0x428d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x428e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x429, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_GSL_CONTROL", REG_MMIO, 0x4290, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4291, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG_SG", REG_MMIO, 0x4292, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DVMM_DEBUG", REG_MMIO, 0x4293, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG_SG2", REG_MMIO, 0x4294, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4295, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4296, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4297, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG2", REG_MMIO, 0x4298, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4299, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_STEREO_CONTROL", REG_MMIO, 0x429a, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x429c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x429d, NULL, 0, 0, 0 },
+	{ "mmDCP4_HW_ROTATION", REG_MMIO, 0x429e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x429f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CACHE", REG_MMIO, 0x42a, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CONTROL", REG_MMIO, 0x42a0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_INDEX", REG_MMIO, 0x42a1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_DATA", REG_MMIO, 0x42a2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x42a3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x42a4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x42a5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x42a6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x42a7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x42a8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x42a9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x42aa, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x42ab, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x42ac, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x42ad, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x42ae, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x42af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x42b, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x42b0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x42b1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x42b2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x42b3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x42b4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x42b5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x42b6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x42b7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x42b8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x42b9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x42ba, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x42bb, NULL, 0, 0, 0 },
+	{ "mmDCP4_ALPHA_CONTROL", REG_MMIO, 0x42bc, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x42bd, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x42be, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x42bf, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DATA_FORMAT", REG_MMIO, 0x42c0, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_MEMORY_CTRL", REG_MMIO, 0x42c1, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x42c2, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DESKTOP_HEIGHT", REG_MMIO, 0x42c3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE_START_END", REG_MMIO, 0x42c4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE2_START_END", REG_MMIO, 0x42c5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_V_COUNTER", REG_MMIO, 0x42c6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x42c7, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_INTERRUPT_MASK", REG_MMIO, 0x42c8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE_STATUS", REG_MMIO, 0x42c9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE2_STATUS", REG_MMIO, 0x42ca, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VBLANK_STATUS", REG_MMIO, 0x42cb, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SYNC_RESET_SEL", REG_MMIO, 0x42cc, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x42cd, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x42ce, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x42cf, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x42d0, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x42d1, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x42d2, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x42d3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x42d4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x42d5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x42d6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x42d7, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x42d8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x42d9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_STATUS", REG_MMIO, 0x42da, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x42dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x42e, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_MODE", REG_MMIO, 0x42e0, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x42e1, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x42e2, NULL, 0, 0, 0 },
+	{ "mmLB4_DC_MVP_LB_CONTROL", REG_MMIO, 0x42e3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG", REG_MMIO, 0x42e4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG2", REG_MMIO, 0x42e5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG3", REG_MMIO, 0x42e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE2_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x42f, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x42fe, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_DATA", REG_MMIO, 0x42ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x430, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4300, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_SOFT_RESET", REG_MMIO, 0x4301, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_DBG_CONFIG", REG_MMIO, 0x4302, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x4303, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x4304, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x4305, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_MISC", REG_MMIO, 0x4306, NULL, 0, 0, 0 },
+	{ "mmDCFE4_DCFE_FLUSH", REG_MMIO, 0x4307, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x431, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x432, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFCOUNTER_CNTL", REG_MMIO, 0x4324, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFCOUNTER_STATE", REG_MMIO, 0x4325, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4326, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CNTL", REG_MMIO, 0x4327, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CVALUE_LOW", REG_MMIO, 0x4328, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_HI", REG_MMIO, 0x4329, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_LOW", REG_MMIO, 0x432a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x432b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x432c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CNTL2", REG_MMIO, 0x432e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_HEIGHT", REG_MMIO, 0x433, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4330, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4331, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4332, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4333, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4334, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4335, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4336, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4337, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4338, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4339, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_REPEATER_PROGRAM", REG_MMIO, 0x433a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_A", REG_MMIO, 0x433b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_B", REG_MMIO, 0x433c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_11", REG_MMIO, 0x433d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x433e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_DVMM_STATUS", REG_MMIO, 0x433f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x434, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4340, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4341, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE", REG_MMIO, 0x4342, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TAP_CONTROL", REG_MMIO, 0x4343, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_CONTROL", REG_MMIO, 0x4344, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_BYPASS_CONTROL", REG_MMIO, 0x4345, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4346, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4347, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4348, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4349, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x434a, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x434b, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x434c, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT", REG_MMIO, 0x434d, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x434e, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ROUND_OFFSET", REG_MMIO, 0x434f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x435, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_UPDATE", REG_MMIO, 0x4351, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4353, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ALU_CONTROL", REG_MMIO, 0x4354, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4355, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_START_SECONDARY", REG_MMIO, 0x435b, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_START", REG_MMIO, 0x435c, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_SIZE", REG_MMIO, 0x435d, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x435e, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x435f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x436, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4360, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4361, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4362, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4363, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG2", REG_MMIO, 0x4369, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG", REG_MMIO, 0x436a, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x436b, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x436c, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_CONTROL", REG_MMIO, 0x436d, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_SM_CONTROL2", REG_MMIO, 0x436e, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_CONTROL2", REG_MMIO, 0x436f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x437, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_UPDATE", REG_MMIO, 0x4370, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4371, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4373, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_DEBUG", REG_MMIO, 0x4374, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4375, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4376, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4377, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4378, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4379, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_WINDOW", REG_MMIO, 0x437a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_CONTROL", REG_MMIO, 0x437b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x437d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x438, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_TOTAL", REG_MMIO, 0x4380, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_START_END", REG_MMIO, 0x4381, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A", REG_MMIO, 0x4382, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4383, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B", REG_MMIO, 0x4384, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4385, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VBI_END", REG_MMIO, 0x4386, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL", REG_MMIO, 0x4387, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4388, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4389, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x438a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x438b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x438c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_BLANK_START_END", REG_MMIO, 0x438d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A", REG_MMIO, 0x438e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x438f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x439, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B", REG_MMIO, 0x4390, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4391, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4392, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4393, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_CNTL", REG_MMIO, 0x4394, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4395, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_CNTL", REG_MMIO, 0x4396, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4397, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4398, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FLOW_CONTROL", REG_MMIO, 0x4399, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x439a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x439b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CONTROL", REG_MMIO, 0x439c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_CONTROL", REG_MMIO, 0x439d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x439e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_STATUS", REG_MMIO, 0x439f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CACHE", REG_MMIO, 0x43a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x43a0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x43a1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x43a2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS", REG_MMIO, 0x43a3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_POSITION", REG_MMIO, 0x43a4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x43a5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x43a6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x43a7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x43a8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_CONTROL", REG_MMIO, 0x43a9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_RESET", REG_MMIO, 0x43aa, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x43ab, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x43ac, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_STATUS", REG_MMIO, 0x43ad, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_CONTROL", REG_MMIO, 0x43ae, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x43af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x43b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x43b0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x43b1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x43b2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_START_LINE_CONTROL", REG_MMIO, 0x43b3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x43b4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_UPDATE_LOCK", REG_MMIO, 0x43b5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x43b6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x43b7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x43ba, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x43bb, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x43bc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x43bd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x43be, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x43bf, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x43c0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_STATUS", REG_MMIO, 0x43c1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_EN", REG_MMIO, 0x43c2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x43c3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x43c4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x43c6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x43c7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x43c8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x43c9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x43ca, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x43cb, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR", REG_MMIO, 0x43cc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x43cd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x43ce, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x43cf, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x43d0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x43d1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x43d2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x43d3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC_CNTL", REG_MMIO, 0x43d4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x43d5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x43d6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x43d7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x43d8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_DATA_RG", REG_MMIO, 0x43d9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_DATA_B", REG_MMIO, 0x43da, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x43db, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x43dc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x43dd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x43de, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_DATA_RG", REG_MMIO, 0x43df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x43e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_DATA_B", REG_MMIO, 0x43e0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x43e1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x43e2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x43e3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x43e4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x43e5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x43e6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x43e7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x43e8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x43e9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x43ea, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x43eb, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x43ec, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x43ed, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CONTROL", REG_MMIO, 0x43ee, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE3_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x43f, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x43f0, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_420_HBLANK_EARLY_START", REG_MMIO, 0x43f1, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x43f2, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x43f3, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x43f4, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x43f5, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x43f6, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x43f7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x43f8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_CNTL", REG_MMIO, 0x43f9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_CNTL", REG_MMIO, 0x43fa, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x43fb, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x43fc, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x43fd, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x43fe, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DEBUG_CNTL", REG_MMIO, 0x43ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x440, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_ENABLE", REG_MMIO, 0x4400, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_CONTROL", REG_MMIO, 0x4401, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4402, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SWAP_CNTL", REG_MMIO, 0x4403, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4404, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4405, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PITCH", REG_MMIO, 0x4406, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4407, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4408, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4409, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x440a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_START", REG_MMIO, 0x440b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_START", REG_MMIO, 0x440c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_END", REG_MMIO, 0x440d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_END", REG_MMIO, 0x440e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_COUNTER_CONTROL", REG_MMIO, 0x440f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x441, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4410, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_UPDATE", REG_MMIO, 0x4411, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_CONTROL", REG_MMIO, 0x4412, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4413, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_CONTROL", REG_MMIO, 0x4414, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_STATUS", REG_MMIO, 0x4415, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4416, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4417, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4418, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4419, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_PITCH", REG_MMIO, 0x441a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x441b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x441c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_COUNTER_OUTPUT", REG_MMIO, 0x441d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x442, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x442d, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x442e, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x442f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_HEIGHT", REG_MMIO, 0x443, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4430, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_CONTROL", REG_MMIO, 0x4435, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C11_C12", REG_MMIO, 0x4436, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C13_C14", REG_MMIO, 0x4437, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C21_C22", REG_MMIO, 0x4438, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C23_C24", REG_MMIO, 0x4439, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C31_C32", REG_MMIO, 0x443a, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C33_C34", REG_MMIO, 0x443b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_CONTROL", REG_MMIO, 0x443c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C11_C12", REG_MMIO, 0x443d, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C13_C14", REG_MMIO, 0x443e, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C21_C22", REG_MMIO, 0x443f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x444, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4440, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4441, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4442, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4443, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4444, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4445, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4446, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4447, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4448, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4449, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x444a, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x444b, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x444c, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x444d, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x444e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x445, NULL, 0, 0, 0 },
+	{ "mmDCP5_DENORM_CONTROL", REG_MMIO, 0x4450, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_ROUND_CONTROL", REG_MMIO, 0x4451, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4452, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_CONTROL", REG_MMIO, 0x4453, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_ALPHA", REG_MMIO, 0x4454, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_RED", REG_MMIO, 0x4455, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_GREEN", REG_MMIO, 0x4456, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_BLUE", REG_MMIO, 0x4457, NULL, 0, 0, 0 },
+	{ "mmDCP5_DEGAMMA_CONTROL", REG_MMIO, 0x4458, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4459, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C11_C12", REG_MMIO, 0x445a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C13_C14", REG_MMIO, 0x445b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C21_C22", REG_MMIO, 0x445c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C23_C24", REG_MMIO, 0x445d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C31_C32", REG_MMIO, 0x445e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C33_C34", REG_MMIO, 0x445f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x446, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4460, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_RANDOM_SEEDS", REG_MMIO, 0x4461, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4465, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_CONTROL", REG_MMIO, 0x4466, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4467, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SIZE", REG_MMIO, 0x4468, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4469, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_POSITION", REG_MMIO, 0x446a, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_HOT_SPOT", REG_MMIO, 0x446b, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR1", REG_MMIO, 0x446c, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR2", REG_MMIO, 0x446d, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_UPDATE", REG_MMIO, 0x446e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x447, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_MODE", REG_MMIO, 0x4478, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_INDEX", REG_MMIO, 0x4479, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_SEQ_COLOR", REG_MMIO, 0x447a, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_PWL_DATA", REG_MMIO, 0x447b, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_30_COLOR", REG_MMIO, 0x447c, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x447d, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x447e, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_AUTOFILL", REG_MMIO, 0x447f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x448, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_CONTROL", REG_MMIO, 0x4480, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4481, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4482, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4483, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4484, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4485, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4486, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CONTROL", REG_MMIO, 0x4487, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_MASK", REG_MMIO, 0x4488, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CURRENT", REG_MMIO, 0x4489, NULL, 0, 0, 0 },
+	{ "mmDCP5_DVMM_PTE_CONTROL", REG_MMIO, 0x448a, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_LAST", REG_MMIO, 0x448b, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG", REG_MMIO, 0x448d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x448e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x449, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_GSL_CONTROL", REG_MMIO, 0x4490, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4491, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG_SG", REG_MMIO, 0x4492, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DVMM_DEBUG", REG_MMIO, 0x4493, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG_SG2", REG_MMIO, 0x4494, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4495, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4496, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4497, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG2", REG_MMIO, 0x4498, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4499, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_STEREO_CONTROL", REG_MMIO, 0x449a, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x449c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x449d, NULL, 0, 0, 0 },
+	{ "mmDCP5_HW_ROTATION", REG_MMIO, 0x449e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x449f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CACHE", REG_MMIO, 0x44a, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CONTROL", REG_MMIO, 0x44a0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_INDEX", REG_MMIO, 0x44a1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_DATA", REG_MMIO, 0x44a2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x44a3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x44a4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x44a5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x44a6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x44a7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x44a8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x44a9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x44aa, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x44ab, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x44ac, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x44ad, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x44ae, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x44af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x44b, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x44b0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x44b1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x44b2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x44b3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x44b4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x44b5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x44b6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x44b7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x44b8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x44b9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x44ba, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x44bb, NULL, 0, 0, 0 },
+	{ "mmDCP5_ALPHA_CONTROL", REG_MMIO, 0x44bc, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x44bd, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x44be, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x44bf, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DATA_FORMAT", REG_MMIO, 0x44c0, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_MEMORY_CTRL", REG_MMIO, 0x44c1, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x44c2, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DESKTOP_HEIGHT", REG_MMIO, 0x44c3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE_START_END", REG_MMIO, 0x44c4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE2_START_END", REG_MMIO, 0x44c5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_V_COUNTER", REG_MMIO, 0x44c6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x44c7, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_INTERRUPT_MASK", REG_MMIO, 0x44c8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE_STATUS", REG_MMIO, 0x44c9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE2_STATUS", REG_MMIO, 0x44ca, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VBLANK_STATUS", REG_MMIO, 0x44cb, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SYNC_RESET_SEL", REG_MMIO, 0x44cc, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x44cd, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x44ce, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x44cf, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x44d0, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x44d1, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x44d2, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x44d3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x44d4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x44d5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x44d6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x44d7, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x44d8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x44d9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_STATUS", REG_MMIO, 0x44da, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x44dc, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x44e, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_MODE", REG_MMIO, 0x44e0, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x44e1, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x44e2, NULL, 0, 0, 0 },
+	{ "mmLB5_DC_MVP_LB_CONTROL", REG_MMIO, 0x44e3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG", REG_MMIO, 0x44e4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG2", REG_MMIO, 0x44e5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG3", REG_MMIO, 0x44e6, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE4_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x44f, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x44fe, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_DATA", REG_MMIO, 0x44ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x450, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4500, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_SOFT_RESET", REG_MMIO, 0x4501, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_DBG_CONFIG", REG_MMIO, 0x4502, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_MEM_PWR_CTRL", REG_MMIO, 0x4503, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_MEM_PWR_CTRL2", REG_MMIO, 0x4504, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_MEM_PWR_STATUS", REG_MMIO, 0x4505, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_MISC", REG_MMIO, 0x4506, NULL, 0, 0, 0 },
+	{ "mmDCFE5_DCFE_FLUSH", REG_MMIO, 0x4507, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x451, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x452, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFCOUNTER_CNTL", REG_MMIO, 0x4524, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFCOUNTER_STATE", REG_MMIO, 0x4525, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4526, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CNTL", REG_MMIO, 0x4527, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CVALUE_LOW", REG_MMIO, 0x4528, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_HI", REG_MMIO, 0x4529, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_LOW", REG_MMIO, 0x452a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x452b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x452c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CNTL2", REG_MMIO, 0x452e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_HEIGHT", REG_MMIO, 0x453, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4530, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4531, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4532, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4533, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4534, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4535, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4536, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4537, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4538, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4539, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_REPEATER_PROGRAM", REG_MMIO, 0x453a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_A", REG_MMIO, 0x453b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_B", REG_MMIO, 0x453c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_11", REG_MMIO, 0x453d, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_CHK_PRE_PROC_CNTL", REG_MMIO, 0x453e, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_DVMM_STATUS", REG_MMIO, 0x453f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x454, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4540, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4541, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE", REG_MMIO, 0x4542, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TAP_CONTROL", REG_MMIO, 0x4543, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_CONTROL", REG_MMIO, 0x4544, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_BYPASS_CONTROL", REG_MMIO, 0x4545, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4546, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4547, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4548, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4549, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x454a, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x454b, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x454c, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT", REG_MMIO, 0x454d, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x454e, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ROUND_OFFSET", REG_MMIO, 0x454f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x455, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_UPDATE", REG_MMIO, 0x4551, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4553, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ALU_CONTROL", REG_MMIO, 0x4554, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4555, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_START_SECONDARY", REG_MMIO, 0x455b, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_START", REG_MMIO, 0x455c, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_SIZE", REG_MMIO, 0x455d, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x455e, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x455f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x456, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4560, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4561, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4562, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4563, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG2", REG_MMIO, 0x4569, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG", REG_MMIO, 0x456a, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x456b, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x456c, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_CONTROL", REG_MMIO, 0x456d, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_SM_CONTROL2", REG_MMIO, 0x456e, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_CONTROL2", REG_MMIO, 0x456f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x457, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_UPDATE", REG_MMIO, 0x4570, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4571, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4573, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_DEBUG", REG_MMIO, 0x4574, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4575, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4576, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4577, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4578, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4579, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_WINDOW", REG_MMIO, 0x457a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_CONTROL", REG_MMIO, 0x457b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x457d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x458, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_TOTAL", REG_MMIO, 0x4580, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_START_END", REG_MMIO, 0x4581, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A", REG_MMIO, 0x4582, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4583, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B", REG_MMIO, 0x4584, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4585, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VBI_END", REG_MMIO, 0x4586, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL", REG_MMIO, 0x4587, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4588, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4589, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x458a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x458b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x458c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_BLANK_START_END", REG_MMIO, 0x458d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A", REG_MMIO, 0x458e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x458f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x459, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B", REG_MMIO, 0x4590, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4591, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4592, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4593, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_CNTL", REG_MMIO, 0x4594, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4595, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_CNTL", REG_MMIO, 0x4596, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4597, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4598, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FLOW_CONTROL", REG_MMIO, 0x4599, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x459a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_AVSYNC_COUNTER", REG_MMIO, 0x459b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CONTROL", REG_MMIO, 0x459c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_CONTROL", REG_MMIO, 0x459d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x459e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_STATUS", REG_MMIO, 0x459f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CACHE", REG_MMIO, 0x45a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x45a0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x45a1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x45a2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS", REG_MMIO, 0x45a3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_POSITION", REG_MMIO, 0x45a4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x45a5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x45a6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x45a7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x45a8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_CONTROL", REG_MMIO, 0x45a9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_RESET", REG_MMIO, 0x45aa, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x45ab, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x45ac, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_STATUS", REG_MMIO, 0x45ad, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_CONTROL", REG_MMIO, 0x45ae, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x45af, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x45b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x45b0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x45b1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x45b2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_START_LINE_CONTROL", REG_MMIO, 0x45b3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x45b4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_UPDATE_LOCK", REG_MMIO, 0x45b5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x45b6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x45b7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x45ba, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x45bb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x45bc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_UPDATE_LOCK", REG_MMIO, 0x45bd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_UPDATE_MODE", REG_MMIO, 0x45be, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x45bf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x45c0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_STATUS", REG_MMIO, 0x45c1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_EN", REG_MMIO, 0x45c2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x45c3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x45c4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x45c6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x45c7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x45c8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x45c9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x45ca, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x45cb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR", REG_MMIO, 0x45cc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x45cd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x45ce, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x45cf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x45d0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x45d1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x45d2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x45d3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC_CNTL", REG_MMIO, 0x45d4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x45d5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x45d6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x45d7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x45d8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_DATA_RG", REG_MMIO, 0x45d9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_DATA_B", REG_MMIO, 0x45da, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x45db, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x45dc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x45dd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x45de, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_DATA_RG", REG_MMIO, 0x45df, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x45e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_DATA_B", REG_MMIO, 0x45e0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x45e1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x45e2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x45e3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x45e4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x45e5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x45e6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x45e7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x45e8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x45e9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x45ea, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x45eb, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x45ec, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x45ed, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CONTROL", REG_MMIO, 0x45ee, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE5_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x45f, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL", REG_MMIO, 0x45f0, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_420_HBLANK_EARLY_START", REG_MMIO, 0x45f1, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x45f2, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x45f3, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x45f4, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x45f5, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x45f6, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x45f7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x45f8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_CNTL", REG_MMIO, 0x45f9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_CNTL", REG_MMIO, 0x45fa, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x45fb, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x45fc, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x45fd, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x45fe, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DEBUG_CNTL", REG_MMIO, 0x45ff, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CNTL", REG_MMIO, 0x460, &mmXDMA_SLV_CNTL[0], sizeof(mmXDMA_SLV_CNTL)/sizeof(mmXDMA_SLV_CNTL[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_ENABLE", REG_MMIO, 0x4600, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_ENABLE", REG_MMIO, 0x4600, &mmUNP_GRPH_ENABLE[0], sizeof(mmUNP_GRPH_ENABLE)/sizeof(mmUNP_GRPH_ENABLE[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_CONTROL", REG_MMIO, 0x4601, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_CONTROL", REG_MMIO, 0x4601, &mmUNP_GRPH_CONTROL[0], sizeof(mmUNP_GRPH_CONTROL)/sizeof(mmUNP_GRPH_CONTROL[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_CONTROL_C", REG_MMIO, 0x4602, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_CONTROL_C", REG_MMIO, 0x4602, &mmUNP_GRPH_CONTROL_C[0], sizeof(mmUNP_GRPH_CONTROL_C)/sizeof(mmUNP_GRPH_CONTROL_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_CONTROL_EXP", REG_MMIO, 0x4603, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_CONTROL_EXP", REG_MMIO, 0x4603, &mmUNP_GRPH_CONTROL_EXP[0], sizeof(mmUNP_GRPH_CONTROL_EXP)/sizeof(mmUNP_GRPH_CONTROL_EXP[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SWAP_CNTL", REG_MMIO, 0x4605, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SWAP_CNTL", REG_MMIO, 0x4605, &mmUNP_GRPH_SWAP_CNTL[0], sizeof(mmUNP_GRPH_SWAP_CNTL)/sizeof(mmUNP_GRPH_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L", REG_MMIO, 0x4606, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L", REG_MMIO, 0x4606, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x4607, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x4607, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4608, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4608, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4609, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4609, &mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x460a, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x460a, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x460b, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x460b, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x460c, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x460c, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x460d, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x460d, &mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L", REG_MMIO, 0x460e, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L", REG_MMIO, 0x460e, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x460f, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x460f, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_CLIENT_CONFIG", REG_MMIO, 0x461, &mmXDMA_SLV_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4610, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4610, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4611, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4611, &mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x4612, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x4612, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x4613, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x4613, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4614, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x4614, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4615, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x4615, &mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0], sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C)/sizeof(mmUNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PITCH_L", REG_MMIO, 0x4616, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PITCH_L", REG_MMIO, 0x4616, &mmUNP_GRPH_PITCH_L[0], sizeof(mmUNP_GRPH_PITCH_L)/sizeof(mmUNP_GRPH_PITCH_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_PITCH_C", REG_MMIO, 0x4617, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_PITCH_C", REG_MMIO, 0x4617, &mmUNP_GRPH_PITCH_C[0], sizeof(mmUNP_GRPH_PITCH_C)/sizeof(mmUNP_GRPH_PITCH_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_L", REG_MMIO, 0x4618, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_X_L", REG_MMIO, 0x4618, &mmUNP_GRPH_SURFACE_OFFSET_X_L[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_L)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SURFACE_OFFSET_X_C", REG_MMIO, 0x4619, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_X_C", REG_MMIO, 0x4619, &mmUNP_GRPH_SURFACE_OFFSET_X_C[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_C)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_X_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_L", REG_MMIO, 0x461a, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_Y_L", REG_MMIO, 0x461a, &mmUNP_GRPH_SURFACE_OFFSET_Y_L[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_L)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SURFACE_OFFSET_Y_C", REG_MMIO, 0x461b, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_OFFSET_Y_C", REG_MMIO, 0x461b, &mmUNP_GRPH_SURFACE_OFFSET_Y_C[0], sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_C)/sizeof(mmUNP_GRPH_SURFACE_OFFSET_Y_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_X_START_L", REG_MMIO, 0x461c, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_X_START_L", REG_MMIO, 0x461c, &mmUNP_GRPH_X_START_L[0], sizeof(mmUNP_GRPH_X_START_L)/sizeof(mmUNP_GRPH_X_START_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_X_START_C", REG_MMIO, 0x461d, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_X_START_C", REG_MMIO, 0x461d, &mmUNP_GRPH_X_START_C[0], sizeof(mmUNP_GRPH_X_START_C)/sizeof(mmUNP_GRPH_X_START_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_Y_START_L", REG_MMIO, 0x461e, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_Y_START_L", REG_MMIO, 0x461e, &mmUNP_GRPH_Y_START_L[0], sizeof(mmUNP_GRPH_Y_START_L)/sizeof(mmUNP_GRPH_Y_START_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_Y_START_C", REG_MMIO, 0x461f, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_Y_START_C", REG_MMIO, 0x461f, &mmUNP_GRPH_Y_START_C[0], sizeof(mmUNP_GRPH_Y_START_C)/sizeof(mmUNP_GRPH_Y_START_C[0]), 0, 0 },
+	{ "mmXDMA_SLV_SLS_PITCH", REG_MMIO, 0x462, &mmXDMA_SLV_SLS_PITCH[0], sizeof(mmXDMA_SLV_SLS_PITCH)/sizeof(mmXDMA_SLV_SLS_PITCH[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_X_END_L", REG_MMIO, 0x4620, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_X_END_L", REG_MMIO, 0x4620, &mmUNP_GRPH_X_END_L[0], sizeof(mmUNP_GRPH_X_END_L)/sizeof(mmUNP_GRPH_X_END_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_X_END_C", REG_MMIO, 0x4621, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_X_END_C", REG_MMIO, 0x4621, &mmUNP_GRPH_X_END_C[0], sizeof(mmUNP_GRPH_X_END_C)/sizeof(mmUNP_GRPH_X_END_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_Y_END_L", REG_MMIO, 0x4622, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_Y_END_L", REG_MMIO, 0x4622, &mmUNP_GRPH_Y_END_L[0], sizeof(mmUNP_GRPH_Y_END_L)/sizeof(mmUNP_GRPH_Y_END_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_Y_END_C", REG_MMIO, 0x4623, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_Y_END_C", REG_MMIO, 0x4623, &mmUNP_GRPH_Y_END_C[0], sizeof(mmUNP_GRPH_Y_END_C)/sizeof(mmUNP_GRPH_Y_END_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_UPDATE", REG_MMIO, 0x4624, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_UPDATE", REG_MMIO, 0x4624, &mmUNP_GRPH_UPDATE[0], sizeof(mmUNP_GRPH_UPDATE)/sizeof(mmUNP_GRPH_UPDATE[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_L", REG_MMIO, 0x4625, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L", REG_MMIO, 0x4625, &mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SURFACE_ADDRESS_INUSE_C", REG_MMIO, 0x4626, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C", REG_MMIO, 0x4626, &mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_INUSE_C[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L", REG_MMIO, 0x4627, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L", REG_MMIO, 0x4627, &mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C", REG_MMIO, 0x4628, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C", REG_MMIO, 0x4628, &mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[0], sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C)/sizeof(mmUNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C[0]), 0, 0 },
+	{ "mmUNP_DVMM_PTE_CONTROL", REG_MMIO, 0x4629, &mmUNP_DVMM_PTE_CONTROL[0], sizeof(mmUNP_DVMM_PTE_CONTROL)/sizeof(mmUNP_DVMM_PTE_CONTROL[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x462b, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x462b, &mmUNP_GRPH_INTERRUPT_STATUS[0], sizeof(mmUNP_GRPH_INTERRUPT_STATUS)/sizeof(mmUNP_GRPH_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x462c, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x462c, &mmUNP_GRPH_INTERRUPT_CONTROL[0], sizeof(mmUNP_GRPH_INTERRUPT_CONTROL)/sizeof(mmUNP_GRPH_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmUNP0_UNP_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x462e, NULL, 0, 0, 0 },
+	{ "mmUNP_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x462e, &mmUNP_GRPH_STEREOSYNC_FLIP[0], sizeof(mmUNP_GRPH_STEREOSYNC_FLIP)/sizeof(mmUNP_GRPH_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmUNP0_UNP_FLIP_CONTROL", REG_MMIO, 0x462f, NULL, 0, 0, 0 },
+	{ "mmUNP_FLIP_CONTROL", REG_MMIO, 0x462f, &mmUNP_FLIP_CONTROL[0], sizeof(mmUNP_FLIP_CONTROL)/sizeof(mmUNP_FLIP_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_URGENT_CNTL", REG_MMIO, 0x463, &mmXDMA_SLV_READ_URGENT_CNTL[0], sizeof(mmXDMA_SLV_READ_URGENT_CNTL)/sizeof(mmXDMA_SLV_READ_URGENT_CNTL[0]), 0, 0 },
+	{ "mmUNP0_UNP_CRC_CONTROL", REG_MMIO, 0x4630, NULL, 0, 0, 0 },
+	{ "mmUNP_CRC_CONTROL", REG_MMIO, 0x4630, &mmUNP_CRC_CONTROL[0], sizeof(mmUNP_CRC_CONTROL)/sizeof(mmUNP_CRC_CONTROL[0]), 0, 0 },
+	{ "mmUNP0_UNP_CRC_MASK", REG_MMIO, 0x4631, NULL, 0, 0, 0 },
+	{ "mmUNP_CRC_MASK", REG_MMIO, 0x4631, &mmUNP_CRC_MASK[0], sizeof(mmUNP_CRC_MASK)/sizeof(mmUNP_CRC_MASK[0]), 0, 0 },
+	{ "mmUNP0_UNP_CRC_CURRENT", REG_MMIO, 0x4632, NULL, 0, 0, 0 },
+	{ "mmUNP_CRC_CURRENT", REG_MMIO, 0x4632, &mmUNP_CRC_CURRENT[0], sizeof(mmUNP_CRC_CURRENT)/sizeof(mmUNP_CRC_CURRENT[0]), 0, 0 },
+	{ "mmUNP0_UNP_CRC_LAST", REG_MMIO, 0x4633, NULL, 0, 0, 0 },
+	{ "mmUNP_CRC_LAST", REG_MMIO, 0x4633, &mmUNP_CRC_LAST[0], sizeof(mmUNP_CRC_LAST)/sizeof(mmUNP_CRC_LAST[0]), 0, 0 },
+	{ "mmUNP0_UNP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4634, NULL, 0, 0, 0 },
+	{ "mmUNP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4634, &mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[0], sizeof(mmUNP_LB_DATA_GAP_BETWEEN_CHUNK)/sizeof(mmUNP_LB_DATA_GAP_BETWEEN_CHUNK[0]), 0, 0 },
+	{ "mmUNP0_UNP_HW_ROTATION", REG_MMIO, 0x4635, NULL, 0, 0, 0 },
+	{ "mmUNP_HW_ROTATION", REG_MMIO, 0x4635, &mmUNP_HW_ROTATION[0], sizeof(mmUNP_HW_ROTATION)/sizeof(mmUNP_HW_ROTATION[0]), 0, 0 },
+	{ "mmUNP0_UNP_DEBUG", REG_MMIO, 0x4636, NULL, 0, 0, 0 },
+	{ "mmUNP_DEBUG", REG_MMIO, 0x4636, &mmUNP_DEBUG[0], sizeof(mmUNP_DEBUG)/sizeof(mmUNP_DEBUG[0]), 0, 0 },
+	{ "mmUNP0_UNP_DEBUG2", REG_MMIO, 0x4637, NULL, 0, 0, 0 },
+	{ "mmUNP_DEBUG2", REG_MMIO, 0x4637, &mmUNP_DEBUG2[0], sizeof(mmUNP_DEBUG2)/sizeof(mmUNP_DEBUG2[0]), 0, 0 },
+	{ "mmUNP0_UNP_TEST_DEBUG_INDEX", REG_MMIO, 0x4638, NULL, 0, 0, 0 },
+	{ "mmUNP_TEST_DEBUG_INDEX", REG_MMIO, 0x4638, &mmUNP_TEST_DEBUG_INDEX[0], sizeof(mmUNP_TEST_DEBUG_INDEX)/sizeof(mmUNP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmUNP0_UNP_TEST_DEBUG_DATA", REG_MMIO, 0x4639, NULL, 0, 0, 0 },
+	{ "mmUNP_TEST_DEBUG_DATA", REG_MMIO, 0x4639, &mmUNP_TEST_DEBUG_DATA[0], sizeof(mmUNP_TEST_DEBUG_DATA)/sizeof(mmUNP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmUNP0_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x463a, NULL, 0, 0, 0 },
+	{ "mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x463a, &mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT[0], sizeof(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT)/sizeof(mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT[0]), 0, 0 },
+	{ "mmUNP0_UNP_DVMM_DEBUG", REG_MMIO, 0x463b, NULL, 0, 0, 0 },
+	{ "mmUNP_DVMM_DEBUG", REG_MMIO, 0x463b, &mmUNP_DVMM_DEBUG[0], sizeof(mmUNP_DVMM_DEBUG)/sizeof(mmUNP_DVMM_DEBUG[0]), 0, 0 },
+	{ "mmLBV0_LBV_DATA_FORMAT", REG_MMIO, 0x463c, NULL, 0, 0, 0 },
+	{ "mmLBV_DATA_FORMAT", REG_MMIO, 0x463c, &mmLBV_DATA_FORMAT[0], sizeof(mmLBV_DATA_FORMAT)/sizeof(mmLBV_DATA_FORMAT[0]), 0, 0 },
+	{ "mmLBV0_LBV_MEMORY_CTRL", REG_MMIO, 0x463d, NULL, 0, 0, 0 },
+	{ "mmLBV_MEMORY_CTRL", REG_MMIO, 0x463d, &mmLBV_MEMORY_CTRL[0], sizeof(mmLBV_MEMORY_CTRL)/sizeof(mmLBV_MEMORY_CTRL[0]), 0, 0 },
+	{ "mmLBV0_LBV_MEMORY_SIZE_STATUS", REG_MMIO, 0x463e, NULL, 0, 0, 0 },
+	{ "mmLBV_MEMORY_SIZE_STATUS", REG_MMIO, 0x463e, &mmLBV_MEMORY_SIZE_STATUS[0], sizeof(mmLBV_MEMORY_SIZE_STATUS)/sizeof(mmLBV_MEMORY_SIZE_STATUS[0]), 0, 0 },
+	{ "mmLBV0_LBV_DESKTOP_HEIGHT", REG_MMIO, 0x463f, NULL, 0, 0, 0 },
+	{ "mmLBV_DESKTOP_HEIGHT", REG_MMIO, 0x463f, &mmLBV_DESKTOP_HEIGHT[0], sizeof(mmLBV_DESKTOP_HEIGHT)/sizeof(mmLBV_DESKTOP_HEIGHT[0]), 0, 0 },
+	{ "mmXDMA_SLV_WRITE_URGENT_CNTL", REG_MMIO, 0x464, &mmXDMA_SLV_WRITE_URGENT_CNTL[0], sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL)/sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL[0]), 0, 0 },
+	{ "mmLBV0_LBV_VLINE_START_END", REG_MMIO, 0x4640, NULL, 0, 0, 0 },
+	{ "mmLBV_VLINE_START_END", REG_MMIO, 0x4640, &mmLBV_VLINE_START_END[0], sizeof(mmLBV_VLINE_START_END)/sizeof(mmLBV_VLINE_START_END[0]), 0, 0 },
+	{ "mmLBV0_LBV_VLINE2_START_END", REG_MMIO, 0x4641, NULL, 0, 0, 0 },
+	{ "mmLBV_VLINE2_START_END", REG_MMIO, 0x4641, &mmLBV_VLINE2_START_END[0], sizeof(mmLBV_VLINE2_START_END)/sizeof(mmLBV_VLINE2_START_END[0]), 0, 0 },
+	{ "mmLBV0_LBV_V_COUNTER", REG_MMIO, 0x4642, NULL, 0, 0, 0 },
+	{ "mmLBV_V_COUNTER", REG_MMIO, 0x4642, &mmLBV_V_COUNTER[0], sizeof(mmLBV_V_COUNTER)/sizeof(mmLBV_V_COUNTER[0]), 0, 0 },
+	{ "mmLBV0_LBV_SNAPSHOT_V_COUNTER", REG_MMIO, 0x4643, NULL, 0, 0, 0 },
+	{ "mmLBV_SNAPSHOT_V_COUNTER", REG_MMIO, 0x4643, &mmLBV_SNAPSHOT_V_COUNTER[0], sizeof(mmLBV_SNAPSHOT_V_COUNTER)/sizeof(mmLBV_SNAPSHOT_V_COUNTER[0]), 0, 0 },
+	{ "mmLBV0_LBV_V_COUNTER_CHROMA", REG_MMIO, 0x4644, NULL, 0, 0, 0 },
+	{ "mmLBV_V_COUNTER_CHROMA", REG_MMIO, 0x4644, &mmLBV_V_COUNTER_CHROMA[0], sizeof(mmLBV_V_COUNTER_CHROMA)/sizeof(mmLBV_V_COUNTER_CHROMA[0]), 0, 0 },
+	{ "mmLBV0_LBV_SNAPSHOT_V_COUNTER_CHROMA", REG_MMIO, 0x4645, NULL, 0, 0, 0 },
+	{ "mmLBV_SNAPSHOT_V_COUNTER_CHROMA", REG_MMIO, 0x4645, &mmLBV_SNAPSHOT_V_COUNTER_CHROMA[0], sizeof(mmLBV_SNAPSHOT_V_COUNTER_CHROMA)/sizeof(mmLBV_SNAPSHOT_V_COUNTER_CHROMA[0]), 0, 0 },
+	{ "mmLBV0_LBV_INTERRUPT_MASK", REG_MMIO, 0x4646, NULL, 0, 0, 0 },
+	{ "mmLBV_INTERRUPT_MASK", REG_MMIO, 0x4646, &mmLBV_INTERRUPT_MASK[0], sizeof(mmLBV_INTERRUPT_MASK)/sizeof(mmLBV_INTERRUPT_MASK[0]), 0, 0 },
+	{ "mmLBV0_LBV_VLINE_STATUS", REG_MMIO, 0x4647, NULL, 0, 0, 0 },
+	{ "mmLBV_VLINE_STATUS", REG_MMIO, 0x4647, &mmLBV_VLINE_STATUS[0], sizeof(mmLBV_VLINE_STATUS)/sizeof(mmLBV_VLINE_STATUS[0]), 0, 0 },
+	{ "mmLBV0_LBV_VLINE2_STATUS", REG_MMIO, 0x4648, NULL, 0, 0, 0 },
+	{ "mmLBV_VLINE2_STATUS", REG_MMIO, 0x4648, &mmLBV_VLINE2_STATUS[0], sizeof(mmLBV_VLINE2_STATUS)/sizeof(mmLBV_VLINE2_STATUS[0]), 0, 0 },
+	{ "mmLBV0_LBV_VBLANK_STATUS", REG_MMIO, 0x4649, NULL, 0, 0, 0 },
+	{ "mmLBV_VBLANK_STATUS", REG_MMIO, 0x4649, &mmLBV_VBLANK_STATUS[0], sizeof(mmLBV_VBLANK_STATUS)/sizeof(mmLBV_VBLANK_STATUS[0]), 0, 0 },
+	{ "mmLBV0_LBV_SYNC_RESET_SEL", REG_MMIO, 0x464a, NULL, 0, 0, 0 },
+	{ "mmLBV_SYNC_RESET_SEL", REG_MMIO, 0x464a, &mmLBV_SYNC_RESET_SEL[0], sizeof(mmLBV_SYNC_RESET_SEL)/sizeof(mmLBV_SYNC_RESET_SEL[0]), 0, 0 },
+	{ "mmLBV0_LBV_BLACK_KEYER_R_CR", REG_MMIO, 0x464b, NULL, 0, 0, 0 },
+	{ "mmLBV_BLACK_KEYER_R_CR", REG_MMIO, 0x464b, &mmLBV_BLACK_KEYER_R_CR[0], sizeof(mmLBV_BLACK_KEYER_R_CR)/sizeof(mmLBV_BLACK_KEYER_R_CR[0]), 0, 0 },
+	{ "mmLBV0_LBV_BLACK_KEYER_G_Y", REG_MMIO, 0x464c, NULL, 0, 0, 0 },
+	{ "mmLBV_BLACK_KEYER_G_Y", REG_MMIO, 0x464c, &mmLBV_BLACK_KEYER_G_Y[0], sizeof(mmLBV_BLACK_KEYER_G_Y)/sizeof(mmLBV_BLACK_KEYER_G_Y[0]), 0, 0 },
+	{ "mmLBV0_LBV_BLACK_KEYER_B_CB", REG_MMIO, 0x464d, NULL, 0, 0, 0 },
+	{ "mmLBV_BLACK_KEYER_B_CB", REG_MMIO, 0x464d, &mmLBV_BLACK_KEYER_B_CB[0], sizeof(mmLBV_BLACK_KEYER_B_CB)/sizeof(mmLBV_BLACK_KEYER_B_CB[0]), 0, 0 },
+	{ "mmLBV0_LBV_KEYER_COLOR_CTRL", REG_MMIO, 0x464e, NULL, 0, 0, 0 },
+	{ "mmLBV_KEYER_COLOR_CTRL", REG_MMIO, 0x464e, &mmLBV_KEYER_COLOR_CTRL[0], sizeof(mmLBV_KEYER_COLOR_CTRL)/sizeof(mmLBV_KEYER_COLOR_CTRL[0]), 0, 0 },
+	{ "mmLBV0_LBV_KEYER_COLOR_R_CR", REG_MMIO, 0x464f, NULL, 0, 0, 0 },
+	{ "mmLBV_KEYER_COLOR_R_CR", REG_MMIO, 0x464f, &mmLBV_KEYER_COLOR_R_CR[0], sizeof(mmLBV_KEYER_COLOR_R_CR)/sizeof(mmLBV_KEYER_COLOR_R_CR[0]), 0, 0 },
+	{ "mmXDMA_SLV_WB_RATE_CNTL", REG_MMIO, 0x465, &mmXDMA_SLV_WB_RATE_CNTL[0], sizeof(mmXDMA_SLV_WB_RATE_CNTL)/sizeof(mmXDMA_SLV_WB_RATE_CNTL[0]), 0, 0 },
+	{ "mmLBV0_LBV_KEYER_COLOR_G_Y", REG_MMIO, 0x4650, NULL, 0, 0, 0 },
+	{ "mmLBV_KEYER_COLOR_G_Y", REG_MMIO, 0x4650, &mmLBV_KEYER_COLOR_G_Y[0], sizeof(mmLBV_KEYER_COLOR_G_Y)/sizeof(mmLBV_KEYER_COLOR_G_Y[0]), 0, 0 },
+	{ "mmLBV0_LBV_KEYER_COLOR_B_CB", REG_MMIO, 0x4651, NULL, 0, 0, 0 },
+	{ "mmLBV_KEYER_COLOR_B_CB", REG_MMIO, 0x4651, &mmLBV_KEYER_COLOR_B_CB[0], sizeof(mmLBV_KEYER_COLOR_B_CB)/sizeof(mmLBV_KEYER_COLOR_B_CB[0]), 0, 0 },
+	{ "mmLBV0_LBV_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x4652, NULL, 0, 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x4652, &mmLBV_KEYER_COLOR_REP_R_CR[0], sizeof(mmLBV_KEYER_COLOR_REP_R_CR)/sizeof(mmLBV_KEYER_COLOR_REP_R_CR[0]), 0, 0 },
+	{ "mmLBV0_LBV_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x4653, NULL, 0, 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x4653, &mmLBV_KEYER_COLOR_REP_G_Y[0], sizeof(mmLBV_KEYER_COLOR_REP_G_Y)/sizeof(mmLBV_KEYER_COLOR_REP_G_Y[0]), 0, 0 },
+	{ "mmLBV0_LBV_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x4654, NULL, 0, 0, 0 },
+	{ "mmLBV_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x4654, &mmLBV_KEYER_COLOR_REP_B_CB[0], sizeof(mmLBV_KEYER_COLOR_REP_B_CB)/sizeof(mmLBV_KEYER_COLOR_REP_B_CB[0]), 0, 0 },
+	{ "mmLBV0_LBV_BUFFER_LEVEL_STATUS", REG_MMIO, 0x4655, NULL, 0, 0, 0 },
+	{ "mmLBV_BUFFER_LEVEL_STATUS", REG_MMIO, 0x4655, &mmLBV_BUFFER_LEVEL_STATUS[0], sizeof(mmLBV_BUFFER_LEVEL_STATUS)/sizeof(mmLBV_BUFFER_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmLBV0_LBV_BUFFER_URGENCY_CTRL", REG_MMIO, 0x4656, NULL, 0, 0, 0 },
+	{ "mmLBV_BUFFER_URGENCY_CTRL", REG_MMIO, 0x4656, &mmLBV_BUFFER_URGENCY_CTRL[0], sizeof(mmLBV_BUFFER_URGENCY_CTRL)/sizeof(mmLBV_BUFFER_URGENCY_CTRL[0]), 0, 0 },
+	{ "mmLBV0_LBV_BUFFER_URGENCY_STATUS", REG_MMIO, 0x4657, NULL, 0, 0, 0 },
+	{ "mmLBV_BUFFER_URGENCY_STATUS", REG_MMIO, 0x4657, &mmLBV_BUFFER_URGENCY_STATUS[0], sizeof(mmLBV_BUFFER_URGENCY_STATUS)/sizeof(mmLBV_BUFFER_URGENCY_STATUS[0]), 0, 0 },
+	{ "mmLBV0_LBV_BUFFER_STATUS", REG_MMIO, 0x4658, NULL, 0, 0, 0 },
+	{ "mmLBV_BUFFER_STATUS", REG_MMIO, 0x4658, &mmLBV_BUFFER_STATUS[0], sizeof(mmLBV_BUFFER_STATUS)/sizeof(mmLBV_BUFFER_STATUS[0]), 0, 0 },
+	{ "mmLBV0_LBV_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x4659, NULL, 0, 0, 0 },
+	{ "mmLBV_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x4659, &mmLBV_NO_OUTSTANDING_REQ_STATUS[0], sizeof(mmLBV_NO_OUTSTANDING_REQ_STATUS)/sizeof(mmLBV_NO_OUTSTANDING_REQ_STATUS[0]), 0, 0 },
+	{ "mmLBV0_LBV_DEBUG", REG_MMIO, 0x465a, NULL, 0, 0, 0 },
+	{ "mmLBV_DEBUG", REG_MMIO, 0x465a, &mmLBV_DEBUG[0], sizeof(mmLBV_DEBUG)/sizeof(mmLBV_DEBUG[0]), 0, 0 },
+	{ "mmLBV0_LBV_DEBUG2", REG_MMIO, 0x465b, NULL, 0, 0, 0 },
+	{ "mmLBV_DEBUG2", REG_MMIO, 0x465b, &mmLBV_DEBUG2[0], sizeof(mmLBV_DEBUG2)/sizeof(mmLBV_DEBUG2[0]), 0, 0 },
+	{ "mmLBV0_LBV_DEBUG3", REG_MMIO, 0x465c, NULL, 0, 0, 0 },
+	{ "mmLBV_DEBUG3", REG_MMIO, 0x465c, &mmLBV_DEBUG3[0], sizeof(mmLBV_DEBUG3)/sizeof(mmLBV_DEBUG3[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_MINMAX", REG_MMIO, 0x466, &mmXDMA_SLV_READ_LATENCY_MINMAX[0], sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX)/sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX[0]), 0, 0 },
+	{ "mmLBV0_LBV_TEST_DEBUG_INDEX", REG_MMIO, 0x4666, NULL, 0, 0, 0 },
+	{ "mmLBV_TEST_DEBUG_INDEX", REG_MMIO, 0x4666, &mmLBV_TEST_DEBUG_INDEX[0], sizeof(mmLBV_TEST_DEBUG_INDEX)/sizeof(mmLBV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmLBV0_LBV_TEST_DEBUG_DATA", REG_MMIO, 0x4667, NULL, 0, 0, 0 },
+	{ "mmLBV_TEST_DEBUG_DATA", REG_MMIO, 0x4667, &mmLBV_TEST_DEBUG_DATA[0], sizeof(mmLBV_TEST_DEBUG_DATA)/sizeof(mmLBV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_AVE", REG_MMIO, 0x467, &mmXDMA_SLV_READ_LATENCY_AVE[0], sizeof(mmXDMA_SLV_READ_LATENCY_AVE)/sizeof(mmXDMA_SLV_READ_LATENCY_AVE[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_COEF_RAM_SELECT", REG_MMIO, 0x4670, NULL, 0, 0, 0 },
+	{ "mmSCLV_COEF_RAM_SELECT", REG_MMIO, 0x4670, &mmSCLV_COEF_RAM_SELECT[0], sizeof(mmSCLV_COEF_RAM_SELECT)/sizeof(mmSCLV_COEF_RAM_SELECT[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_COEF_RAM_TAP_DATA", REG_MMIO, 0x4671, NULL, 0, 0, 0 },
+	{ "mmSCLV_COEF_RAM_TAP_DATA", REG_MMIO, 0x4671, &mmSCLV_COEF_RAM_TAP_DATA[0], sizeof(mmSCLV_COEF_RAM_TAP_DATA)/sizeof(mmSCLV_COEF_RAM_TAP_DATA[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_MODE", REG_MMIO, 0x4672, NULL, 0, 0, 0 },
+	{ "mmSCLV_MODE", REG_MMIO, 0x4672, &mmSCLV_MODE[0], sizeof(mmSCLV_MODE)/sizeof(mmSCLV_MODE[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_TAP_CONTROL", REG_MMIO, 0x4673, NULL, 0, 0, 0 },
+	{ "mmSCLV_TAP_CONTROL", REG_MMIO, 0x4673, &mmSCLV_TAP_CONTROL[0], sizeof(mmSCLV_TAP_CONTROL)/sizeof(mmSCLV_TAP_CONTROL[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_CONTROL", REG_MMIO, 0x4674, NULL, 0, 0, 0 },
+	{ "mmSCLV_CONTROL", REG_MMIO, 0x4674, &mmSCLV_CONTROL[0], sizeof(mmSCLV_CONTROL)/sizeof(mmSCLV_CONTROL[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4675, NULL, 0, 0, 0 },
+	{ "mmSCLV_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4675, &mmSCLV_MANUAL_REPLICATE_CONTROL[0], sizeof(mmSCLV_MANUAL_REPLICATE_CONTROL)/sizeof(mmSCLV_MANUAL_REPLICATE_CONTROL[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4676, NULL, 0, 0, 0 },
+	{ "mmSCLV_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4676, &mmSCLV_AUTOMATIC_MODE_CONTROL[0], sizeof(mmSCLV_AUTOMATIC_MODE_CONTROL)/sizeof(mmSCLV_AUTOMATIC_MODE_CONTROL[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_HORZ_FILTER_CONTROL", REG_MMIO, 0x4677, NULL, 0, 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_CONTROL", REG_MMIO, 0x4677, &mmSCLV_HORZ_FILTER_CONTROL[0], sizeof(mmSCLV_HORZ_FILTER_CONTROL)/sizeof(mmSCLV_HORZ_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4678, NULL, 0, 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4678, &mmSCLV_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO)/sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_HORZ_FILTER_INIT", REG_MMIO, 0x4679, NULL, 0, 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT", REG_MMIO, 0x4679, &mmSCLV_HORZ_FILTER_INIT[0], sizeof(mmSCLV_HORZ_FILTER_INIT)/sizeof(mmSCLV_HORZ_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x467a, NULL, 0, 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x467a, &mmSCLV_HORZ_FILTER_SCALE_RATIO_C[0], sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO_C)/sizeof(mmSCLV_HORZ_FILTER_SCALE_RATIO_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_HORZ_FILTER_INIT_C", REG_MMIO, 0x467b, NULL, 0, 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT_C", REG_MMIO, 0x467b, &mmSCLV_HORZ_FILTER_INIT_C[0], sizeof(mmSCLV_HORZ_FILTER_INIT_C)/sizeof(mmSCLV_HORZ_FILTER_INIT_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VERT_FILTER_CONTROL", REG_MMIO, 0x467c, NULL, 0, 0, 0 },
+	{ "mmSCLV_VERT_FILTER_CONTROL", REG_MMIO, 0x467c, &mmSCLV_VERT_FILTER_CONTROL[0], sizeof(mmSCLV_VERT_FILTER_CONTROL)/sizeof(mmSCLV_VERT_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x467d, NULL, 0, 0, 0 },
+	{ "mmSCLV_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x467d, &mmSCLV_VERT_FILTER_SCALE_RATIO[0], sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO)/sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VERT_FILTER_INIT", REG_MMIO, 0x467e, NULL, 0, 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT", REG_MMIO, 0x467e, &mmSCLV_VERT_FILTER_INIT[0], sizeof(mmSCLV_VERT_FILTER_INIT)/sizeof(mmSCLV_VERT_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VERT_FILTER_INIT_BOT", REG_MMIO, 0x467f, NULL, 0, 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_BOT", REG_MMIO, 0x467f, &mmSCLV_VERT_FILTER_INIT_BOT[0], sizeof(mmSCLV_VERT_FILTER_INIT_BOT)/sizeof(mmSCLV_VERT_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmXDMA_SLV_PCIE_NACK_STATUS", REG_MMIO, 0x468, &mmXDMA_SLV_PCIE_NACK_STATUS[0], sizeof(mmXDMA_SLV_PCIE_NACK_STATUS)/sizeof(mmXDMA_SLV_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x4680, NULL, 0, 0, 0 },
+	{ "mmSCLV_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x4680, &mmSCLV_VERT_FILTER_SCALE_RATIO_C[0], sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO_C)/sizeof(mmSCLV_VERT_FILTER_SCALE_RATIO_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VERT_FILTER_INIT_C", REG_MMIO, 0x4681, NULL, 0, 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_C", REG_MMIO, 0x4681, &mmSCLV_VERT_FILTER_INIT_C[0], sizeof(mmSCLV_VERT_FILTER_INIT_C)/sizeof(mmSCLV_VERT_FILTER_INIT_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x4682, NULL, 0, 0, 0 },
+	{ "mmSCLV_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x4682, &mmSCLV_VERT_FILTER_INIT_BOT_C[0], sizeof(mmSCLV_VERT_FILTER_INIT_BOT_C)/sizeof(mmSCLV_VERT_FILTER_INIT_BOT_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_ROUND_OFFSET", REG_MMIO, 0x4683, NULL, 0, 0, 0 },
+	{ "mmSCLV_ROUND_OFFSET", REG_MMIO, 0x4683, &mmSCLV_ROUND_OFFSET[0], sizeof(mmSCLV_ROUND_OFFSET)/sizeof(mmSCLV_ROUND_OFFSET[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_UPDATE", REG_MMIO, 0x4684, NULL, 0, 0, 0 },
+	{ "mmSCLV_UPDATE", REG_MMIO, 0x4684, &mmSCLV_UPDATE[0], sizeof(mmSCLV_UPDATE)/sizeof(mmSCLV_UPDATE[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_ALU_CONTROL", REG_MMIO, 0x4685, NULL, 0, 0, 0 },
+	{ "mmSCLV_ALU_CONTROL", REG_MMIO, 0x4685, &mmSCLV_ALU_CONTROL[0], sizeof(mmSCLV_ALU_CONTROL)/sizeof(mmSCLV_ALU_CONTROL[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VIEWPORT_START", REG_MMIO, 0x4686, NULL, 0, 0, 0 },
+	{ "mmSCLV_VIEWPORT_START", REG_MMIO, 0x4686, &mmSCLV_VIEWPORT_START[0], sizeof(mmSCLV_VIEWPORT_START)/sizeof(mmSCLV_VIEWPORT_START[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VIEWPORT_START_SECONDARY", REG_MMIO, 0x4687, NULL, 0, 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_SECONDARY", REG_MMIO, 0x4687, &mmSCLV_VIEWPORT_START_SECONDARY[0], sizeof(mmSCLV_VIEWPORT_START_SECONDARY)/sizeof(mmSCLV_VIEWPORT_START_SECONDARY[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VIEWPORT_SIZE", REG_MMIO, 0x4688, NULL, 0, 0, 0 },
+	{ "mmSCLV_VIEWPORT_SIZE", REG_MMIO, 0x4688, &mmSCLV_VIEWPORT_SIZE[0], sizeof(mmSCLV_VIEWPORT_SIZE)/sizeof(mmSCLV_VIEWPORT_SIZE[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VIEWPORT_START_C", REG_MMIO, 0x4689, NULL, 0, 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_C", REG_MMIO, 0x4689, &mmSCLV_VIEWPORT_START_C[0], sizeof(mmSCLV_VIEWPORT_START_C)/sizeof(mmSCLV_VIEWPORT_START_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VIEWPORT_START_SECONDARY_C", REG_MMIO, 0x468a, NULL, 0, 0, 0 },
+	{ "mmSCLV_VIEWPORT_START_SECONDARY_C", REG_MMIO, 0x468a, &mmSCLV_VIEWPORT_START_SECONDARY_C[0], sizeof(mmSCLV_VIEWPORT_START_SECONDARY_C)/sizeof(mmSCLV_VIEWPORT_START_SECONDARY_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_VIEWPORT_SIZE_C", REG_MMIO, 0x468b, NULL, 0, 0, 0 },
+	{ "mmSCLV_VIEWPORT_SIZE_C", REG_MMIO, 0x468b, &mmSCLV_VIEWPORT_SIZE_C[0], sizeof(mmSCLV_VIEWPORT_SIZE_C)/sizeof(mmSCLV_VIEWPORT_SIZE_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x468c, NULL, 0, 0, 0 },
+	{ "mmSCLV_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x468c, &mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmSCLV_EXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmSCLV_EXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x468d, NULL, 0, 0, 0 },
+	{ "mmSCLV_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x468d, &mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmSCLV_EXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmSCLV_EXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_MODE_CHANGE_DET1", REG_MMIO, 0x468e, NULL, 0, 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET1", REG_MMIO, 0x468e, &mmSCLV_MODE_CHANGE_DET1[0], sizeof(mmSCLV_MODE_CHANGE_DET1)/sizeof(mmSCLV_MODE_CHANGE_DET1[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_MODE_CHANGE_DET2", REG_MMIO, 0x468f, NULL, 0, 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET2", REG_MMIO, 0x468f, &mmSCLV_MODE_CHANGE_DET2[0], sizeof(mmSCLV_MODE_CHANGE_DET2)/sizeof(mmSCLV_MODE_CHANGE_DET2[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_NACK_STATUS", REG_MMIO, 0x469, &mmXDMA_SLV_MEM_NACK_STATUS[0], sizeof(mmXDMA_SLV_MEM_NACK_STATUS)/sizeof(mmXDMA_SLV_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_MODE_CHANGE_DET3", REG_MMIO, 0x4690, NULL, 0, 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_DET3", REG_MMIO, 0x4690, &mmSCLV_MODE_CHANGE_DET3[0], sizeof(mmSCLV_MODE_CHANGE_DET3)/sizeof(mmSCLV_MODE_CHANGE_DET3[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_MODE_CHANGE_MASK", REG_MMIO, 0x4691, NULL, 0, 0, 0 },
+	{ "mmSCLV_MODE_CHANGE_MASK", REG_MMIO, 0x4691, &mmSCLV_MODE_CHANGE_MASK[0], sizeof(mmSCLV_MODE_CHANGE_MASK)/sizeof(mmSCLV_MODE_CHANGE_MASK[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT", REG_MMIO, 0x4692, NULL, 0, 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT_BOT", REG_MMIO, 0x4692, &mmSCLV_HORZ_FILTER_INIT_BOT[0], sizeof(mmSCLV_HORZ_FILTER_INIT_BOT)/sizeof(mmSCLV_HORZ_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_HORZ_FILTER_INIT_BOT_C", REG_MMIO, 0x4693, NULL, 0, 0, 0 },
+	{ "mmSCLV_HORZ_FILTER_INIT_BOT_C", REG_MMIO, 0x4693, &mmSCLV_HORZ_FILTER_INIT_BOT_C[0], sizeof(mmSCLV_HORZ_FILTER_INIT_BOT_C)/sizeof(mmSCLV_HORZ_FILTER_INIT_BOT_C[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_DEBUG2", REG_MMIO, 0x4694, NULL, 0, 0, 0 },
+	{ "mmSCLV_DEBUG2", REG_MMIO, 0x4694, &mmSCLV_DEBUG2[0], sizeof(mmSCLV_DEBUG2)/sizeof(mmSCLV_DEBUG2[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_DEBUG", REG_MMIO, 0x4695, NULL, 0, 0, 0 },
+	{ "mmSCLV_DEBUG", REG_MMIO, 0x4695, &mmSCLV_DEBUG[0], sizeof(mmSCLV_DEBUG)/sizeof(mmSCLV_DEBUG[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_TEST_DEBUG_INDEX", REG_MMIO, 0x4696, NULL, 0, 0, 0 },
+	{ "mmSCLV_TEST_DEBUG_INDEX", REG_MMIO, 0x4696, &mmSCLV_TEST_DEBUG_INDEX[0], sizeof(mmSCLV_TEST_DEBUG_INDEX)/sizeof(mmSCLV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmSCLV0_SCLV_TEST_DEBUG_DATA", REG_MMIO, 0x4697, NULL, 0, 0, 0 },
+	{ "mmSCLV_TEST_DEBUG_DATA", REG_MMIO, 0x4697, &mmSCLV_TEST_DEBUG_DATA[0], sizeof(mmSCLV_TEST_DEBUG_DATA)/sizeof(mmSCLV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmXDMA_SLV_RDRET_BUF_STATUS", REG_MMIO, 0x46a, &mmXDMA_SLV_RDRET_BUF_STATUS[0], sizeof(mmXDMA_SLV_RDRET_BUF_STATUS)/sizeof(mmXDMA_SLV_RDRET_BUF_STATUS[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_UPDATE", REG_MMIO, 0x46a4, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_UPDATE", REG_MMIO, 0x46a4, &mmCOL_MAN_UPDATE[0], sizeof(mmCOL_MAN_UPDATE)/sizeof(mmCOL_MAN_UPDATE[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_INPUT_CSC_CONTROL", REG_MMIO, 0x46a5, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_INPUT_CSC_CONTROL", REG_MMIO, 0x46a5, &mmCOL_MAN_INPUT_CSC_CONTROL[0], sizeof(mmCOL_MAN_INPUT_CSC_CONTROL)/sizeof(mmCOL_MAN_INPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C11_C12_A", REG_MMIO, 0x46a6, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C11_C12_A", REG_MMIO, 0x46a6, &mmINPUT_CSC_C11_C12_A[0], sizeof(mmINPUT_CSC_C11_C12_A)/sizeof(mmINPUT_CSC_C11_C12_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C13_C14_A", REG_MMIO, 0x46a7, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C13_C14_A", REG_MMIO, 0x46a7, &mmINPUT_CSC_C13_C14_A[0], sizeof(mmINPUT_CSC_C13_C14_A)/sizeof(mmINPUT_CSC_C13_C14_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C21_C22_A", REG_MMIO, 0x46a8, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C21_C22_A", REG_MMIO, 0x46a8, &mmINPUT_CSC_C21_C22_A[0], sizeof(mmINPUT_CSC_C21_C22_A)/sizeof(mmINPUT_CSC_C21_C22_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C23_C24_A", REG_MMIO, 0x46a9, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C23_C24_A", REG_MMIO, 0x46a9, &mmINPUT_CSC_C23_C24_A[0], sizeof(mmINPUT_CSC_C23_C24_A)/sizeof(mmINPUT_CSC_C23_C24_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C31_C32_A", REG_MMIO, 0x46aa, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C31_C32_A", REG_MMIO, 0x46aa, &mmINPUT_CSC_C31_C32_A[0], sizeof(mmINPUT_CSC_C31_C32_A)/sizeof(mmINPUT_CSC_C31_C32_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C33_C34_A", REG_MMIO, 0x46ab, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C33_C34_A", REG_MMIO, 0x46ab, &mmINPUT_CSC_C33_C34_A[0], sizeof(mmINPUT_CSC_C33_C34_A)/sizeof(mmINPUT_CSC_C33_C34_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C11_C12_B", REG_MMIO, 0x46ac, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C11_C12_B", REG_MMIO, 0x46ac, &mmINPUT_CSC_C11_C12_B[0], sizeof(mmINPUT_CSC_C11_C12_B)/sizeof(mmINPUT_CSC_C11_C12_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C13_C14_B", REG_MMIO, 0x46ad, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C13_C14_B", REG_MMIO, 0x46ad, &mmINPUT_CSC_C13_C14_B[0], sizeof(mmINPUT_CSC_C13_C14_B)/sizeof(mmINPUT_CSC_C13_C14_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C21_C22_B", REG_MMIO, 0x46ae, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C21_C22_B", REG_MMIO, 0x46ae, &mmINPUT_CSC_C21_C22_B[0], sizeof(mmINPUT_CSC_C21_C22_B)/sizeof(mmINPUT_CSC_C21_C22_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C23_C24_B", REG_MMIO, 0x46af, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C23_C24_B", REG_MMIO, 0x46af, &mmINPUT_CSC_C23_C24_B[0], sizeof(mmINPUT_CSC_C23_C24_B)/sizeof(mmINPUT_CSC_C23_C24_B[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_TIMER", REG_MMIO, 0x46b, &mmXDMA_SLV_READ_LATENCY_TIMER[0], sizeof(mmXDMA_SLV_READ_LATENCY_TIMER)/sizeof(mmXDMA_SLV_READ_LATENCY_TIMER[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C31_C32_B", REG_MMIO, 0x46b0, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C31_C32_B", REG_MMIO, 0x46b0, &mmINPUT_CSC_C31_C32_B[0], sizeof(mmINPUT_CSC_C31_C32_B)/sizeof(mmINPUT_CSC_C31_C32_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_CSC_C33_C34_B", REG_MMIO, 0x46b1, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C33_C34_B", REG_MMIO, 0x46b1, &mmINPUT_CSC_C33_C34_B[0], sizeof(mmINPUT_CSC_C33_C34_B)/sizeof(mmINPUT_CSC_C33_C34_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_PRESCALE_CONTROL", REG_MMIO, 0x46b2, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_CONTROL", REG_MMIO, 0x46b2, &mmPRESCALE_CONTROL[0], sizeof(mmPRESCALE_CONTROL)/sizeof(mmPRESCALE_CONTROL[0]), 0, 0 },
+	{ "mmCOL_MAN0_PRESCALE_VALUES_R", REG_MMIO, 0x46b3, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_R", REG_MMIO, 0x46b3, &mmPRESCALE_VALUES_R[0], sizeof(mmPRESCALE_VALUES_R)/sizeof(mmPRESCALE_VALUES_R[0]), 0, 0 },
+	{ "mmCOL_MAN0_PRESCALE_VALUES_G", REG_MMIO, 0x46b4, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_G", REG_MMIO, 0x46b4, &mmPRESCALE_VALUES_G[0], sizeof(mmPRESCALE_VALUES_G)/sizeof(mmPRESCALE_VALUES_G[0]), 0, 0 },
+	{ "mmCOL_MAN0_PRESCALE_VALUES_B", REG_MMIO, 0x46b5, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_B", REG_MMIO, 0x46b5, &mmPRESCALE_VALUES_B[0], sizeof(mmPRESCALE_VALUES_B)/sizeof(mmPRESCALE_VALUES_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_OUTPUT_CSC_CONTROL", REG_MMIO, 0x46b6, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_OUTPUT_CSC_CONTROL", REG_MMIO, 0x46b6, &mmCOL_MAN_OUTPUT_CSC_CONTROL[0], sizeof(mmCOL_MAN_OUTPUT_CSC_CONTROL)/sizeof(mmCOL_MAN_OUTPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C11_C12_A", REG_MMIO, 0x46b7, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12_A", REG_MMIO, 0x46b7, &mmOUTPUT_CSC_C11_C12_A[0], sizeof(mmOUTPUT_CSC_C11_C12_A)/sizeof(mmOUTPUT_CSC_C11_C12_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C13_C14_A", REG_MMIO, 0x46b8, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14_A", REG_MMIO, 0x46b8, &mmOUTPUT_CSC_C13_C14_A[0], sizeof(mmOUTPUT_CSC_C13_C14_A)/sizeof(mmOUTPUT_CSC_C13_C14_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C21_C22_A", REG_MMIO, 0x46b9, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22_A", REG_MMIO, 0x46b9, &mmOUTPUT_CSC_C21_C22_A[0], sizeof(mmOUTPUT_CSC_C21_C22_A)/sizeof(mmOUTPUT_CSC_C21_C22_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C23_C24_A", REG_MMIO, 0x46ba, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24_A", REG_MMIO, 0x46ba, &mmOUTPUT_CSC_C23_C24_A[0], sizeof(mmOUTPUT_CSC_C23_C24_A)/sizeof(mmOUTPUT_CSC_C23_C24_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C31_C32_A", REG_MMIO, 0x46bb, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32_A", REG_MMIO, 0x46bb, &mmOUTPUT_CSC_C31_C32_A[0], sizeof(mmOUTPUT_CSC_C31_C32_A)/sizeof(mmOUTPUT_CSC_C31_C32_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C33_C34_A", REG_MMIO, 0x46bc, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34_A", REG_MMIO, 0x46bc, &mmOUTPUT_CSC_C33_C34_A[0], sizeof(mmOUTPUT_CSC_C33_C34_A)/sizeof(mmOUTPUT_CSC_C33_C34_A[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C11_C12_B", REG_MMIO, 0x46bd, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12_B", REG_MMIO, 0x46bd, &mmOUTPUT_CSC_C11_C12_B[0], sizeof(mmOUTPUT_CSC_C11_C12_B)/sizeof(mmOUTPUT_CSC_C11_C12_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C13_C14_B", REG_MMIO, 0x46be, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14_B", REG_MMIO, 0x46be, &mmOUTPUT_CSC_C13_C14_B[0], sizeof(mmOUTPUT_CSC_C13_C14_B)/sizeof(mmOUTPUT_CSC_C13_C14_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C21_C22_B", REG_MMIO, 0x46bf, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22_B", REG_MMIO, 0x46bf, &mmOUTPUT_CSC_C21_C22_B[0], sizeof(mmOUTPUT_CSC_C21_C22_B)/sizeof(mmOUTPUT_CSC_C21_C22_B[0]), 0, 0 },
+	{ "mmXDMA_SLV_FLIP_PENDING", REG_MMIO, 0x46c, &mmXDMA_SLV_FLIP_PENDING[0], sizeof(mmXDMA_SLV_FLIP_PENDING)/sizeof(mmXDMA_SLV_FLIP_PENDING[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C23_C24_B", REG_MMIO, 0x46c0, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24_B", REG_MMIO, 0x46c0, &mmOUTPUT_CSC_C23_C24_B[0], sizeof(mmOUTPUT_CSC_C23_C24_B)/sizeof(mmOUTPUT_CSC_C23_C24_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C31_C32_B", REG_MMIO, 0x46c1, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32_B", REG_MMIO, 0x46c1, &mmOUTPUT_CSC_C31_C32_B[0], sizeof(mmOUTPUT_CSC_C31_C32_B)/sizeof(mmOUTPUT_CSC_C31_C32_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_CSC_C33_C34_B", REG_MMIO, 0x46c2, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34_B", REG_MMIO, 0x46c2, &mmOUTPUT_CSC_C33_C34_B[0], sizeof(mmOUTPUT_CSC_C33_C34_B)/sizeof(mmOUTPUT_CSC_C33_C34_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_DENORM_CLAMP_CONTROL", REG_MMIO, 0x46c3, NULL, 0, 0, 0 },
+	{ "mmDENORM_CLAMP_CONTROL", REG_MMIO, 0x46c3, &mmDENORM_CLAMP_CONTROL[0], sizeof(mmDENORM_CLAMP_CONTROL)/sizeof(mmDENORM_CLAMP_CONTROL[0]), 0, 0 },
+	{ "mmCOL_MAN0_DENORM_CLAMP_RANGE_R_CR", REG_MMIO, 0x46c4, NULL, 0, 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_R_CR", REG_MMIO, 0x46c4, &mmDENORM_CLAMP_RANGE_R_CR[0], sizeof(mmDENORM_CLAMP_RANGE_R_CR)/sizeof(mmDENORM_CLAMP_RANGE_R_CR[0]), 0, 0 },
+	{ "mmCOL_MAN0_DENORM_CLAMP_RANGE_G_Y", REG_MMIO, 0x46c5, NULL, 0, 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_G_Y", REG_MMIO, 0x46c5, &mmDENORM_CLAMP_RANGE_G_Y[0], sizeof(mmDENORM_CLAMP_RANGE_G_Y)/sizeof(mmDENORM_CLAMP_RANGE_G_Y[0]), 0, 0 },
+	{ "mmCOL_MAN0_DENORM_CLAMP_RANGE_B_CB", REG_MMIO, 0x46c6, NULL, 0, 0, 0 },
+	{ "mmDENORM_CLAMP_RANGE_B_CB", REG_MMIO, 0x46c6, &mmDENORM_CLAMP_RANGE_B_CB[0], sizeof(mmDENORM_CLAMP_RANGE_B_CB)/sizeof(mmDENORM_CLAMP_RANGE_B_CB[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_FP_CONVERTED_FIELD", REG_MMIO, 0x46c7, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_FP_CONVERTED_FIELD", REG_MMIO, 0x46c7, &mmCOL_MAN_FP_CONVERTED_FIELD[0], sizeof(mmCOL_MAN_FP_CONVERTED_FIELD)/sizeof(mmCOL_MAN_FP_CONVERTED_FIELD[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CONTROL", REG_MMIO, 0x46c8, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CONTROL", REG_MMIO, 0x46c8, &mmGAMMA_CORR_CONTROL[0], sizeof(mmGAMMA_CORR_CONTROL)/sizeof(mmGAMMA_CORR_CONTROL[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_LUT_INDEX", REG_MMIO, 0x46c9, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_LUT_INDEX", REG_MMIO, 0x46c9, &mmGAMMA_CORR_LUT_INDEX[0], sizeof(mmGAMMA_CORR_LUT_INDEX)/sizeof(mmGAMMA_CORR_LUT_INDEX[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_LUT_DATA", REG_MMIO, 0x46ca, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_LUT_DATA", REG_MMIO, 0x46ca, &mmGAMMA_CORR_LUT_DATA[0], sizeof(mmGAMMA_CORR_LUT_DATA)/sizeof(mmGAMMA_CORR_LUT_DATA[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_LUT_WRITE_EN_MASK", REG_MMIO, 0x46cb, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_LUT_WRITE_EN_MASK", REG_MMIO, 0x46cb, &mmGAMMA_CORR_LUT_WRITE_EN_MASK[0], sizeof(mmGAMMA_CORR_LUT_WRITE_EN_MASK)/sizeof(mmGAMMA_CORR_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_START_CNTL", REG_MMIO, 0x46cc, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_START_CNTL", REG_MMIO, 0x46cc, &mmGAMMA_CORR_CNTLA_START_CNTL[0], sizeof(mmGAMMA_CORR_CNTLA_START_CNTL)/sizeof(mmGAMMA_CORR_CNTLA_START_CNTL[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_SLOPE_CNTL", REG_MMIO, 0x46cd, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_SLOPE_CNTL", REG_MMIO, 0x46cd, &mmGAMMA_CORR_CNTLA_SLOPE_CNTL[0], sizeof(mmGAMMA_CORR_CNTLA_SLOPE_CNTL)/sizeof(mmGAMMA_CORR_CNTLA_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL1", REG_MMIO, 0x46ce, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_END_CNTL1", REG_MMIO, 0x46ce, &mmGAMMA_CORR_CNTLA_END_CNTL1[0], sizeof(mmGAMMA_CORR_CNTLA_END_CNTL1)/sizeof(mmGAMMA_CORR_CNTLA_END_CNTL1[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_END_CNTL2", REG_MMIO, 0x46cf, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_END_CNTL2", REG_MMIO, 0x46cf, &mmGAMMA_CORR_CNTLA_END_CNTL2[0], sizeof(mmGAMMA_CORR_CNTLA_END_CNTL2)/sizeof(mmGAMMA_CORR_CNTLA_END_CNTL2[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_0_1", REG_MMIO, 0x46d0, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_0_1", REG_MMIO, 0x46d0, &mmGAMMA_CORR_CNTLA_REGION_0_1[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_0_1)/sizeof(mmGAMMA_CORR_CNTLA_REGION_0_1[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_2_3", REG_MMIO, 0x46d1, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_2_3", REG_MMIO, 0x46d1, &mmGAMMA_CORR_CNTLA_REGION_2_3[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_2_3)/sizeof(mmGAMMA_CORR_CNTLA_REGION_2_3[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_4_5", REG_MMIO, 0x46d2, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_4_5", REG_MMIO, 0x46d2, &mmGAMMA_CORR_CNTLA_REGION_4_5[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_4_5)/sizeof(mmGAMMA_CORR_CNTLA_REGION_4_5[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_6_7", REG_MMIO, 0x46d3, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_6_7", REG_MMIO, 0x46d3, &mmGAMMA_CORR_CNTLA_REGION_6_7[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_6_7)/sizeof(mmGAMMA_CORR_CNTLA_REGION_6_7[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_8_9", REG_MMIO, 0x46d4, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_8_9", REG_MMIO, 0x46d4, &mmGAMMA_CORR_CNTLA_REGION_8_9[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_8_9)/sizeof(mmGAMMA_CORR_CNTLA_REGION_8_9[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_10_11", REG_MMIO, 0x46d5, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_10_11", REG_MMIO, 0x46d5, &mmGAMMA_CORR_CNTLA_REGION_10_11[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_10_11)/sizeof(mmGAMMA_CORR_CNTLA_REGION_10_11[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_12_13", REG_MMIO, 0x46d6, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_12_13", REG_MMIO, 0x46d6, &mmGAMMA_CORR_CNTLA_REGION_12_13[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_12_13)/sizeof(mmGAMMA_CORR_CNTLA_REGION_12_13[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLA_REGION_14_15", REG_MMIO, 0x46d7, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLA_REGION_14_15", REG_MMIO, 0x46d7, &mmGAMMA_CORR_CNTLA_REGION_14_15[0], sizeof(mmGAMMA_CORR_CNTLA_REGION_14_15)/sizeof(mmGAMMA_CORR_CNTLA_REGION_14_15[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_START_CNTL", REG_MMIO, 0x46d8, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_START_CNTL", REG_MMIO, 0x46d8, &mmGAMMA_CORR_CNTLB_START_CNTL[0], sizeof(mmGAMMA_CORR_CNTLB_START_CNTL)/sizeof(mmGAMMA_CORR_CNTLB_START_CNTL[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_SLOPE_CNTL", REG_MMIO, 0x46d9, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_SLOPE_CNTL", REG_MMIO, 0x46d9, &mmGAMMA_CORR_CNTLB_SLOPE_CNTL[0], sizeof(mmGAMMA_CORR_CNTLB_SLOPE_CNTL)/sizeof(mmGAMMA_CORR_CNTLB_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL1", REG_MMIO, 0x46da, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_END_CNTL1", REG_MMIO, 0x46da, &mmGAMMA_CORR_CNTLB_END_CNTL1[0], sizeof(mmGAMMA_CORR_CNTLB_END_CNTL1)/sizeof(mmGAMMA_CORR_CNTLB_END_CNTL1[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_END_CNTL2", REG_MMIO, 0x46db, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_END_CNTL2", REG_MMIO, 0x46db, &mmGAMMA_CORR_CNTLB_END_CNTL2[0], sizeof(mmGAMMA_CORR_CNTLB_END_CNTL2)/sizeof(mmGAMMA_CORR_CNTLB_END_CNTL2[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_0_1", REG_MMIO, 0x46dc, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_0_1", REG_MMIO, 0x46dc, &mmGAMMA_CORR_CNTLB_REGION_0_1[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_0_1)/sizeof(mmGAMMA_CORR_CNTLB_REGION_0_1[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_2_3", REG_MMIO, 0x46dd, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_2_3", REG_MMIO, 0x46dd, &mmGAMMA_CORR_CNTLB_REGION_2_3[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_2_3)/sizeof(mmGAMMA_CORR_CNTLB_REGION_2_3[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_4_5", REG_MMIO, 0x46de, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_4_5", REG_MMIO, 0x46de, &mmGAMMA_CORR_CNTLB_REGION_4_5[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_4_5)/sizeof(mmGAMMA_CORR_CNTLB_REGION_4_5[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_6_7", REG_MMIO, 0x46df, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_6_7", REG_MMIO, 0x46df, &mmGAMMA_CORR_CNTLB_REGION_6_7[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_6_7)/sizeof(mmGAMMA_CORR_CNTLB_REGION_6_7[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_8_9", REG_MMIO, 0x46e0, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_8_9", REG_MMIO, 0x46e0, &mmGAMMA_CORR_CNTLB_REGION_8_9[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_8_9)/sizeof(mmGAMMA_CORR_CNTLB_REGION_8_9[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_10_11", REG_MMIO, 0x46e1, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_10_11", REG_MMIO, 0x46e1, &mmGAMMA_CORR_CNTLB_REGION_10_11[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_10_11)/sizeof(mmGAMMA_CORR_CNTLB_REGION_10_11[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_12_13", REG_MMIO, 0x46e2, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_12_13", REG_MMIO, 0x46e2, &mmGAMMA_CORR_CNTLB_REGION_12_13[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_12_13)/sizeof(mmGAMMA_CORR_CNTLB_REGION_12_13[0]), 0, 0 },
+	{ "mmCOL_MAN0_GAMMA_CORR_CNTLB_REGION_14_15", REG_MMIO, 0x46e3, NULL, 0, 0, 0 },
+	{ "mmGAMMA_CORR_CNTLB_REGION_14_15", REG_MMIO, 0x46e3, &mmGAMMA_CORR_CNTLB_REGION_14_15[0], sizeof(mmGAMMA_CORR_CNTLB_REGION_14_15)/sizeof(mmGAMMA_CORR_CNTLB_REGION_14_15[0]), 0, 0 },
+	{ "mmCOL_MAN0_PACK_FIFO_ERROR", REG_MMIO, 0x46e4, NULL, 0, 0, 0 },
+	{ "mmPACK_FIFO_ERROR", REG_MMIO, 0x46e4, &mmPACK_FIFO_ERROR[0], sizeof(mmPACK_FIFO_ERROR)/sizeof(mmPACK_FIFO_ERROR[0]), 0, 0 },
+	{ "mmCOL_MAN0_OUTPUT_FIFO_ERROR", REG_MMIO, 0x46e5, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_FIFO_ERROR", REG_MMIO, 0x46e5, &mmOUTPUT_FIFO_ERROR[0], sizeof(mmOUTPUT_FIFO_ERROR)/sizeof(mmOUTPUT_FIFO_ERROR[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_GAMMA_LUT_AUTOFILL", REG_MMIO, 0x46e6, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_AUTOFILL", REG_MMIO, 0x46e6, &mmINPUT_GAMMA_LUT_AUTOFILL[0], sizeof(mmINPUT_GAMMA_LUT_AUTOFILL)/sizeof(mmINPUT_GAMMA_LUT_AUTOFILL[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_GAMMA_LUT_RW_INDEX", REG_MMIO, 0x46e7, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_RW_INDEX", REG_MMIO, 0x46e7, &mmINPUT_GAMMA_LUT_RW_INDEX[0], sizeof(mmINPUT_GAMMA_LUT_RW_INDEX)/sizeof(mmINPUT_GAMMA_LUT_RW_INDEX[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_GAMMA_LUT_SEQ_COLOR", REG_MMIO, 0x46e8, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_SEQ_COLOR", REG_MMIO, 0x46e8, &mmINPUT_GAMMA_LUT_SEQ_COLOR[0], sizeof(mmINPUT_GAMMA_LUT_SEQ_COLOR)/sizeof(mmINPUT_GAMMA_LUT_SEQ_COLOR[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_GAMMA_LUT_PWL_DATA", REG_MMIO, 0x46e9, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_PWL_DATA", REG_MMIO, 0x46e9, &mmINPUT_GAMMA_LUT_PWL_DATA[0], sizeof(mmINPUT_GAMMA_LUT_PWL_DATA)/sizeof(mmINPUT_GAMMA_LUT_PWL_DATA[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_GAMMA_LUT_30_COLOR", REG_MMIO, 0x46ea, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_LUT_30_COLOR", REG_MMIO, 0x46ea, &mmINPUT_GAMMA_LUT_30_COLOR[0], sizeof(mmINPUT_GAMMA_LUT_30_COLOR)/sizeof(mmINPUT_GAMMA_LUT_30_COLOR[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL1", REG_MMIO, 0x46eb, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_INPUT_GAMMA_CONTROL1", REG_MMIO, 0x46eb, &mmCOL_MAN_INPUT_GAMMA_CONTROL1[0], sizeof(mmCOL_MAN_INPUT_GAMMA_CONTROL1)/sizeof(mmCOL_MAN_INPUT_GAMMA_CONTROL1[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_INPUT_GAMMA_CONTROL2", REG_MMIO, 0x46ec, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_INPUT_GAMMA_CONTROL2", REG_MMIO, 0x46ec, &mmCOL_MAN_INPUT_GAMMA_CONTROL2[0], sizeof(mmCOL_MAN_INPUT_GAMMA_CONTROL2)/sizeof(mmCOL_MAN_INPUT_GAMMA_CONTROL2[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_B", REG_MMIO, 0x46ed, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_BW_OFFSETS_B", REG_MMIO, 0x46ed, &mmINPUT_GAMMA_BW_OFFSETS_B[0], sizeof(mmINPUT_GAMMA_BW_OFFSETS_B)/sizeof(mmINPUT_GAMMA_BW_OFFSETS_B[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_G", REG_MMIO, 0x46ee, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_BW_OFFSETS_G", REG_MMIO, 0x46ee, &mmINPUT_GAMMA_BW_OFFSETS_G[0], sizeof(mmINPUT_GAMMA_BW_OFFSETS_G)/sizeof(mmINPUT_GAMMA_BW_OFFSETS_G[0]), 0, 0 },
+	{ "mmCOL_MAN0_INPUT_GAMMA_BW_OFFSETS_R", REG_MMIO, 0x46ef, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_BW_OFFSETS_R", REG_MMIO, 0x46ef, &mmINPUT_GAMMA_BW_OFFSETS_R[0], sizeof(mmINPUT_GAMMA_BW_OFFSETS_R)/sizeof(mmINPUT_GAMMA_BW_OFFSETS_R[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_DEBUG_CONTROL", REG_MMIO, 0x46f0, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_DEBUG_CONTROL", REG_MMIO, 0x46f0, &mmCOL_MAN_DEBUG_CONTROL[0], sizeof(mmCOL_MAN_DEBUG_CONTROL)/sizeof(mmCOL_MAN_DEBUG_CONTROL[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_TEST_DEBUG_INDEX", REG_MMIO, 0x46f1, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_TEST_DEBUG_INDEX", REG_MMIO, 0x46f1, &mmCOL_MAN_TEST_DEBUG_INDEX[0], sizeof(mmCOL_MAN_TEST_DEBUG_INDEX)/sizeof(mmCOL_MAN_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCOL_MAN0_COL_MAN_TEST_DEBUG_DATA", REG_MMIO, 0x46f3, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN_TEST_DEBUG_DATA", REG_MMIO, 0x46f3, &mmCOL_MAN_TEST_DEBUG_DATA[0], sizeof(mmCOL_MAN_TEST_DEBUG_DATA)/sizeof(mmCOL_MAN_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_CLOCK_CONTROL", REG_MMIO, 0x46f4, NULL, 0, 0, 0 },
+	{ "mmDCFEV_CLOCK_CONTROL", REG_MMIO, 0x46f4, &mmDCFEV_CLOCK_CONTROL[0], sizeof(mmDCFEV_CLOCK_CONTROL)/sizeof(mmDCFEV_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_SOFT_RESET", REG_MMIO, 0x46f5, NULL, 0, 0, 0 },
+	{ "mmDCFEV_SOFT_RESET", REG_MMIO, 0x46f5, &mmDCFEV_SOFT_RESET[0], sizeof(mmDCFEV_SOFT_RESET)/sizeof(mmDCFEV_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_DMIFV_CLOCK_CONTROL", REG_MMIO, 0x46f6, NULL, 0, 0, 0 },
+	{ "mmDCFEV_DMIFV_CLOCK_CONTROL", REG_MMIO, 0x46f6, &mmDCFEV_DMIFV_CLOCK_CONTROL[0], sizeof(mmDCFEV_DMIFV_CLOCK_CONTROL)/sizeof(mmDCFEV_DMIFV_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_DBG_CONFIG", REG_MMIO, 0x46f7, NULL, 0, 0, 0 },
+	{ "mmDCFEV_DBG_CONFIG", REG_MMIO, 0x46f7, &mmDCFEV_DBG_CONFIG[0], sizeof(mmDCFEV_DBG_CONFIG)/sizeof(mmDCFEV_DBG_CONFIG[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_DMIFV_MEM_PWR_CTRL", REG_MMIO, 0x46f8, NULL, 0, 0, 0 },
+	{ "mmDCFEV_DMIFV_MEM_PWR_CTRL", REG_MMIO, 0x46f8, &mmDCFEV_DMIFV_MEM_PWR_CTRL[0], sizeof(mmDCFEV_DMIFV_MEM_PWR_CTRL)/sizeof(mmDCFEV_DMIFV_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_DMIFV_MEM_PWR_STATUS", REG_MMIO, 0x46f9, NULL, 0, 0, 0 },
+	{ "mmDCFEV_DMIFV_MEM_PWR_STATUS", REG_MMIO, 0x46f9, &mmDCFEV_DMIFV_MEM_PWR_STATUS[0], sizeof(mmDCFEV_DMIFV_MEM_PWR_STATUS)/sizeof(mmDCFEV_DMIFV_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_MEM_PWR_CTRL", REG_MMIO, 0x46fa, NULL, 0, 0, 0 },
+	{ "mmDCFEV_MEM_PWR_CTRL", REG_MMIO, 0x46fa, &mmDCFEV_MEM_PWR_CTRL[0], sizeof(mmDCFEV_MEM_PWR_CTRL)/sizeof(mmDCFEV_MEM_PWR_CTRL[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_MEM_PWR_CTRL2", REG_MMIO, 0x46fb, NULL, 0, 0, 0 },
+	{ "mmDCFEV_MEM_PWR_CTRL2", REG_MMIO, 0x46fb, &mmDCFEV_MEM_PWR_CTRL2[0], sizeof(mmDCFEV_MEM_PWR_CTRL2)/sizeof(mmDCFEV_MEM_PWR_CTRL2[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_MEM_PWR_STATUS", REG_MMIO, 0x46fc, NULL, 0, 0, 0 },
+	{ "mmDCFEV_MEM_PWR_STATUS", REG_MMIO, 0x46fc, &mmDCFEV_MEM_PWR_STATUS[0], sizeof(mmDCFEV_MEM_PWR_STATUS)/sizeof(mmDCFEV_MEM_PWR_STATUS[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_DMIFV_DEBUG", REG_MMIO, 0x46fd, NULL, 0, 0, 0 },
+	{ "mmDCFEV_DMIFV_DEBUG", REG_MMIO, 0x46fd, &mmDCFEV_DMIFV_DEBUG[0], sizeof(mmDCFEV_DMIFV_DEBUG)/sizeof(mmDCFEV_DMIFV_DEBUG[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_MISC", REG_MMIO, 0x46fe, NULL, 0, 0, 0 },
+	{ "mmDCFEV_MISC", REG_MMIO, 0x46fe, &mmDCFEV_MISC[0], sizeof(mmDCFEV_MISC)/sizeof(mmDCFEV_MISC[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_L_FLUSH", REG_MMIO, 0x46ff, NULL, 0, 0, 0 },
+	{ "mmDCFEV_L_FLUSH", REG_MMIO, 0x46ff, &mmDCFEV_L_FLUSH[0], sizeof(mmDCFEV_L_FLUSH)/sizeof(mmDCFEV_L_FLUSH[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, &mmXDMA_SLV_CHANNEL_CNTL[0], sizeof(mmXDMA_SLV_CHANNEL_CNTL)/sizeof(mmXDMA_SLV_CHANNEL_CNTL[0]), 0, 0 },
+	{ "mmDCFEV0_DCFEV_C_FLUSH", REG_MMIO, 0x4700, NULL, 0, 0, 0 },
+	{ "mmDCFEV_C_FLUSH", REG_MMIO, 0x4700, &mmDCFEV_C_FLUSH[0], sizeof(mmDCFEV_C_FLUSH)/sizeof(mmDCFEV_C_FLUSH[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, &mmXDMA_SLV_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, &mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDC_PERFMON10_PERFCOUNTER_CNTL", REG_MMIO, 0x4724, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFCOUNTER_STATE", REG_MMIO, 0x4725, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4726, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CNTL", REG_MMIO, 0x4727, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CVALUE_LOW", REG_MMIO, 0x4728, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_HI", REG_MMIO, 0x4729, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_LOW", REG_MMIO, 0x472a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x472b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x472c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON10_PERFMON_CNTL2", REG_MMIO, 0x472e, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4730, NULL, 0, 0, 0 },
+	{ "mmDPGV0_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4730, &mmDPGV0_PIPE_ARBITRATION_CONTROL1[0], sizeof(mmDPGV0_PIPE_ARBITRATION_CONTROL1)/sizeof(mmDPGV0_PIPE_ARBITRATION_CONTROL1[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4731, NULL, 0, 0, 0 },
+	{ "mmDPGV0_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4731, &mmDPGV0_PIPE_ARBITRATION_CONTROL2[0], sizeof(mmDPGV0_PIPE_ARBITRATION_CONTROL2)/sizeof(mmDPGV0_PIPE_ARBITRATION_CONTROL2[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4732, NULL, 0, 0, 0 },
+	{ "mmDPGV0_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4732, &mmDPGV0_WATERMARK_MASK_CONTROL[0], sizeof(mmDPGV0_WATERMARK_MASK_CONTROL)/sizeof(mmDPGV0_WATERMARK_MASK_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4733, NULL, 0, 0, 0 },
+	{ "mmDPGV0_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4733, &mmDPGV0_PIPE_URGENCY_CONTROL[0], sizeof(mmDPGV0_PIPE_URGENCY_CONTROL)/sizeof(mmDPGV0_PIPE_URGENCY_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_PIPE_DPM_CONTROL", REG_MMIO, 0x4734, NULL, 0, 0, 0 },
+	{ "mmDPGV0_PIPE_DPM_CONTROL", REG_MMIO, 0x4734, &mmDPGV0_PIPE_DPM_CONTROL[0], sizeof(mmDPGV0_PIPE_DPM_CONTROL)/sizeof(mmDPGV0_PIPE_DPM_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4735, NULL, 0, 0, 0 },
+	{ "mmDPGV0_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4735, &mmDPGV0_PIPE_STUTTER_CONTROL[0], sizeof(mmDPGV0_PIPE_STUTTER_CONTROL)/sizeof(mmDPGV0_PIPE_STUTTER_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4736, NULL, 0, 0, 0 },
+	{ "mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4736, &mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL[0], sizeof(mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL)/sizeof(mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4737, NULL, 0, 0, 0 },
+	{ "mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4737, &mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH[0], sizeof(mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH)/sizeof(mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_REPEATER_PROGRAM", REG_MMIO, 0x4738, NULL, 0, 0, 0 },
+	{ "mmDPGV0_REPEATER_PROGRAM", REG_MMIO, 0x4738, &mmDPGV0_REPEATER_PROGRAM[0], sizeof(mmDPGV0_REPEATER_PROGRAM)/sizeof(mmDPGV0_REPEATER_PROGRAM[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_HW_DEBUG_A", REG_MMIO, 0x4739, NULL, 0, 0, 0 },
+	{ "mmDPGV0_HW_DEBUG_A", REG_MMIO, 0x4739, &mmDPGV0_HW_DEBUG_A[0], sizeof(mmDPGV0_HW_DEBUG_A)/sizeof(mmDPGV0_HW_DEBUG_A[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_HW_DEBUG_B", REG_MMIO, 0x473a, NULL, 0, 0, 0 },
+	{ "mmDPGV0_HW_DEBUG_B", REG_MMIO, 0x473a, &mmDPGV0_HW_DEBUG_B[0], sizeof(mmDPGV0_HW_DEBUG_B)/sizeof(mmDPGV0_HW_DEBUG_B[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_HW_DEBUG_11", REG_MMIO, 0x473b, NULL, 0, 0, 0 },
+	{ "mmDPGV0_HW_DEBUG_11", REG_MMIO, 0x473b, &mmDPGV0_HW_DEBUG_11[0], sizeof(mmDPGV0_HW_DEBUG_11)/sizeof(mmDPGV0_HW_DEBUG_11[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV0_CHK_PRE_PROC_CNTL", REG_MMIO, 0x473c, NULL, 0, 0, 0 },
+	{ "mmDPGV0_CHK_PRE_PROC_CNTL", REG_MMIO, 0x473c, &mmDPGV0_CHK_PRE_PROC_CNTL[0], sizeof(mmDPGV0_CHK_PRE_PROC_CNTL)/sizeof(mmDPGV0_CHK_PRE_PROC_CNTL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x473d, NULL, 0, 0, 0 },
+	{ "mmDPGV1_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x473d, &mmDPGV1_PIPE_ARBITRATION_CONTROL1[0], sizeof(mmDPGV1_PIPE_ARBITRATION_CONTROL1)/sizeof(mmDPGV1_PIPE_ARBITRATION_CONTROL1[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x473e, NULL, 0, 0, 0 },
+	{ "mmDPGV1_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x473e, &mmDPGV1_PIPE_ARBITRATION_CONTROL2[0], sizeof(mmDPGV1_PIPE_ARBITRATION_CONTROL2)/sizeof(mmDPGV1_PIPE_ARBITRATION_CONTROL2[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_WATERMARK_MASK_CONTROL", REG_MMIO, 0x473f, NULL, 0, 0, 0 },
+	{ "mmDPGV1_WATERMARK_MASK_CONTROL", REG_MMIO, 0x473f, &mmDPGV1_WATERMARK_MASK_CONTROL[0], sizeof(mmDPGV1_WATERMARK_MASK_CONTROL)/sizeof(mmDPGV1_WATERMARK_MASK_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4740, NULL, 0, 0, 0 },
+	{ "mmDPGV1_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4740, &mmDPGV1_PIPE_URGENCY_CONTROL[0], sizeof(mmDPGV1_PIPE_URGENCY_CONTROL)/sizeof(mmDPGV1_PIPE_URGENCY_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_PIPE_DPM_CONTROL", REG_MMIO, 0x4741, NULL, 0, 0, 0 },
+	{ "mmDPGV1_PIPE_DPM_CONTROL", REG_MMIO, 0x4741, &mmDPGV1_PIPE_DPM_CONTROL[0], sizeof(mmDPGV1_PIPE_DPM_CONTROL)/sizeof(mmDPGV1_PIPE_DPM_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4742, NULL, 0, 0, 0 },
+	{ "mmDPGV1_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4742, &mmDPGV1_PIPE_STUTTER_CONTROL[0], sizeof(mmDPGV1_PIPE_STUTTER_CONTROL)/sizeof(mmDPGV1_PIPE_STUTTER_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4743, NULL, 0, 0, 0 },
+	{ "mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4743, &mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL[0], sizeof(mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL)/sizeof(mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4744, NULL, 0, 0, 0 },
+	{ "mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4744, &mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH[0], sizeof(mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH)/sizeof(mmDPGV1_PIPE_STUTTER_CONTROL_NONLPTCH[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_REPEATER_PROGRAM", REG_MMIO, 0x4745, NULL, 0, 0, 0 },
+	{ "mmDPGV1_REPEATER_PROGRAM", REG_MMIO, 0x4745, &mmDPGV1_REPEATER_PROGRAM[0], sizeof(mmDPGV1_REPEATER_PROGRAM)/sizeof(mmDPGV1_REPEATER_PROGRAM[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_HW_DEBUG_A", REG_MMIO, 0x4746, NULL, 0, 0, 0 },
+	{ "mmDPGV1_HW_DEBUG_A", REG_MMIO, 0x4746, &mmDPGV1_HW_DEBUG_A[0], sizeof(mmDPGV1_HW_DEBUG_A)/sizeof(mmDPGV1_HW_DEBUG_A[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_HW_DEBUG_B", REG_MMIO, 0x4747, NULL, 0, 0, 0 },
+	{ "mmDPGV1_HW_DEBUG_B", REG_MMIO, 0x4747, &mmDPGV1_HW_DEBUG_B[0], sizeof(mmDPGV1_HW_DEBUG_B)/sizeof(mmDPGV1_HW_DEBUG_B[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_HW_DEBUG_11", REG_MMIO, 0x4748, NULL, 0, 0, 0 },
+	{ "mmDPGV1_HW_DEBUG_11", REG_MMIO, 0x4748, &mmDPGV1_HW_DEBUG_11[0], sizeof(mmDPGV1_HW_DEBUG_11)/sizeof(mmDPGV1_HW_DEBUG_11[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV1_CHK_PRE_PROC_CNTL", REG_MMIO, 0x4749, NULL, 0, 0, 0 },
+	{ "mmDPGV1_CHK_PRE_PROC_CNTL", REG_MMIO, 0x4749, &mmDPGV1_CHK_PRE_PROC_CNTL[0], sizeof(mmDPGV1_CHK_PRE_PROC_CNTL)/sizeof(mmDPGV1_CHK_PRE_PROC_CNTL[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV_TEST_DEBUG_INDEX", REG_MMIO, 0x474e, NULL, 0, 0, 0 },
+	{ "mmDPGV_TEST_DEBUG_INDEX", REG_MMIO, 0x474e, &mmDPGV_TEST_DEBUG_INDEX[0], sizeof(mmDPGV_TEST_DEBUG_INDEX)/sizeof(mmDPGV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIFV_PG0_DPGV_TEST_DEBUG_DATA", REG_MMIO, 0x474f, NULL, 0, 0, 0 },
+	{ "mmDPGV_TEST_DEBUG_DATA", REG_MMIO, 0x474f, &mmDPGV_TEST_DEBUG_DATA[0], sizeof(mmDPGV_TEST_DEBUG_DATA)/sizeof(mmDPGV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_CONTROL", REG_MMIO, 0x476d, NULL, 0, 0, 0 },
+	{ "mmBLNDV_CONTROL", REG_MMIO, 0x476d, &mmBLNDV_CONTROL[0], sizeof(mmBLNDV_CONTROL)/sizeof(mmBLNDV_CONTROL[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_SM_CONTROL2", REG_MMIO, 0x476e, NULL, 0, 0, 0 },
+	{ "mmBLNDV_SM_CONTROL2", REG_MMIO, 0x476e, &mmBLNDV_SM_CONTROL2[0], sizeof(mmBLNDV_SM_CONTROL2)/sizeof(mmBLNDV_SM_CONTROL2[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_CONTROL2", REG_MMIO, 0x476f, NULL, 0, 0, 0 },
+	{ "mmBLNDV_CONTROL2", REG_MMIO, 0x476f, &mmBLNDV_CONTROL2[0], sizeof(mmBLNDV_CONTROL2)/sizeof(mmBLNDV_CONTROL2[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_UPDATE", REG_MMIO, 0x4770, NULL, 0, 0, 0 },
+	{ "mmBLNDV_UPDATE", REG_MMIO, 0x4770, &mmBLNDV_UPDATE[0], sizeof(mmBLNDV_UPDATE)/sizeof(mmBLNDV_UPDATE[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4771, NULL, 0, 0, 0 },
+	{ "mmBLNDV_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4771, &mmBLNDV_UNDERFLOW_INTERRUPT[0], sizeof(mmBLNDV_UNDERFLOW_INTERRUPT)/sizeof(mmBLNDV_UNDERFLOW_INTERRUPT[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_V_UPDATE_LOCK", REG_MMIO, 0x4773, NULL, 0, 0, 0 },
+	{ "mmBLNDV_V_UPDATE_LOCK", REG_MMIO, 0x4773, &mmBLNDV_V_UPDATE_LOCK[0], sizeof(mmBLNDV_V_UPDATE_LOCK)/sizeof(mmBLNDV_V_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_DEBUG", REG_MMIO, 0x4774, NULL, 0, 0, 0 },
+	{ "mmBLNDV_DEBUG", REG_MMIO, 0x4774, &mmBLNDV_DEBUG[0], sizeof(mmBLNDV_DEBUG)/sizeof(mmBLNDV_DEBUG[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_TEST_DEBUG_INDEX", REG_MMIO, 0x4775, NULL, 0, 0, 0 },
+	{ "mmBLNDV_TEST_DEBUG_INDEX", REG_MMIO, 0x4775, &mmBLNDV_TEST_DEBUG_INDEX[0], sizeof(mmBLNDV_TEST_DEBUG_INDEX)/sizeof(mmBLNDV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_TEST_DEBUG_DATA", REG_MMIO, 0x4776, NULL, 0, 0, 0 },
+	{ "mmBLNDV_TEST_DEBUG_DATA", REG_MMIO, 0x4776, &mmBLNDV_TEST_DEBUG_DATA[0], sizeof(mmBLNDV_TEST_DEBUG_DATA)/sizeof(mmBLNDV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLNDV0_BLNDV_REG_UPDATE_STATUS", REG_MMIO, 0x4777, NULL, 0, 0, 0 },
+	{ "mmBLNDV_REG_UPDATE_STATUS", REG_MMIO, 0x4777, &mmBLNDV_REG_UPDATE_STATUS[0], sizeof(mmBLNDV_REG_UPDATE_STATUS)/sizeof(mmBLNDV_REG_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x478, NULL, 0, 0, 0 },
+	{ "mmCRTCV0_CRTCV_H_TOTAL", REG_MMIO, 0x4780, NULL, 0, 0, 0 },
+	{ "mmCRTCV_H_TOTAL", REG_MMIO, 0x4780, &mmCRTCV_H_TOTAL[0], sizeof(mmCRTCV_H_TOTAL)/sizeof(mmCRTCV_H_TOTAL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_H_BLANK_START_END", REG_MMIO, 0x4781, NULL, 0, 0, 0 },
+	{ "mmCRTCV_H_BLANK_START_END", REG_MMIO, 0x4781, &mmCRTCV_H_BLANK_START_END[0], sizeof(mmCRTCV_H_BLANK_START_END)/sizeof(mmCRTCV_H_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_H_SYNC_A", REG_MMIO, 0x4782, NULL, 0, 0, 0 },
+	{ "mmCRTCV_H_SYNC_A", REG_MMIO, 0x4782, &mmCRTCV_H_SYNC_A[0], sizeof(mmCRTCV_H_SYNC_A)/sizeof(mmCRTCV_H_SYNC_A[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_V_TOTAL", REG_MMIO, 0x4787, NULL, 0, 0, 0 },
+	{ "mmCRTCV_V_TOTAL", REG_MMIO, 0x4787, &mmCRTCV_V_TOTAL[0], sizeof(mmCRTCV_V_TOTAL)/sizeof(mmCRTCV_V_TOTAL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_V_BLANK_START_END", REG_MMIO, 0x478d, NULL, 0, 0, 0 },
+	{ "mmCRTCV_V_BLANK_START_END", REG_MMIO, 0x478d, &mmCRTCV_V_BLANK_START_END[0], sizeof(mmCRTCV_V_BLANK_START_END)/sizeof(mmCRTCV_V_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_V_SYNC_A", REG_MMIO, 0x478e, NULL, 0, 0, 0 },
+	{ "mmCRTCV_V_SYNC_A", REG_MMIO, 0x478e, &mmCRTCV_V_SYNC_A[0], sizeof(mmCRTCV_V_SYNC_A)/sizeof(mmCRTCV_V_SYNC_A[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x479, NULL, 0, 0, 0 },
+	{ "mmCRTCV0_CRTCV_CONTROL", REG_MMIO, 0x479c, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CONTROL", REG_MMIO, 0x479c, &mmCRTCV_CONTROL[0], sizeof(mmCRTCV_CONTROL)/sizeof(mmCRTCV_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x47a, NULL, 0, 0, 0 },
+	{ "mmCRTCV0_CRTCV_START_LINE_CONTROL", REG_MMIO, 0x47b3, NULL, 0, 0, 0 },
+	{ "mmCRTCV_START_LINE_CONTROL", REG_MMIO, 0x47b3, &mmCRTCV_START_LINE_CONTROL[0], sizeof(mmCRTCV_START_LINE_CONTROL)/sizeof(mmCRTCV_START_LINE_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_TEST_DEBUG_INDEX", REG_MMIO, 0x47c6, NULL, 0, 0, 0 },
+	{ "mmCRTCV_TEST_DEBUG_INDEX", REG_MMIO, 0x47c6, &mmCRTCV_TEST_DEBUG_INDEX[0], sizeof(mmCRTCV_TEST_DEBUG_INDEX)/sizeof(mmCRTCV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_TEST_DEBUG_DATA", REG_MMIO, 0x47c7, NULL, 0, 0, 0 },
+	{ "mmCRTCV_TEST_DEBUG_DATA", REG_MMIO, 0x47c7, &mmCRTCV_TEST_DEBUG_DATA[0], sizeof(mmCRTCV_TEST_DEBUG_DATA)/sizeof(mmCRTCV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_OVERSCAN_COLOR", REG_MMIO, 0x47c8, NULL, 0, 0, 0 },
+	{ "mmCRTCV_OVERSCAN_COLOR", REG_MMIO, 0x47c8, &mmCRTCV_OVERSCAN_COLOR[0], sizeof(mmCRTCV_OVERSCAN_COLOR)/sizeof(mmCRTCV_OVERSCAN_COLOR[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_OVERSCAN_COLOR_EXT", REG_MMIO, 0x47c9, NULL, 0, 0, 0 },
+	{ "mmCRTCV_OVERSCAN_COLOR_EXT", REG_MMIO, 0x47c9, &mmCRTCV_OVERSCAN_COLOR_EXT[0], sizeof(mmCRTCV_OVERSCAN_COLOR_EXT)/sizeof(mmCRTCV_OVERSCAN_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_BLACK_COLOR", REG_MMIO, 0x47cc, NULL, 0, 0, 0 },
+	{ "mmCRTCV_BLACK_COLOR", REG_MMIO, 0x47cc, &mmCRTCV_BLACK_COLOR[0], sizeof(mmCRTCV_BLACK_COLOR)/sizeof(mmCRTCV_BLACK_COLOR[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_BLACK_COLOR_EXT", REG_MMIO, 0x47cd, NULL, 0, 0, 0 },
+	{ "mmCRTCV_BLACK_COLOR_EXT", REG_MMIO, 0x47cd, &mmCRTCV_BLACK_COLOR_EXT[0], sizeof(mmCRTCV_BLACK_COLOR_EXT)/sizeof(mmCRTCV_BLACK_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC_CNTL", REG_MMIO, 0x47d4, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC_CNTL", REG_MMIO, 0x47d4, &mmCRTCV_CRC_CNTL[0], sizeof(mmCRTCV_CRC_CNTL)/sizeof(mmCRTCV_CRC_CNTL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x47d5, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x47d5, &mmCRTCV_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmCRTCV_CRC0_WINDOWA_X_CONTROL)/sizeof(mmCRTCV_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x47d6, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x47d6, &mmCRTCV_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmCRTCV_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmCRTCV_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x47d7, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x47d7, &mmCRTCV_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmCRTCV_CRC0_WINDOWB_X_CONTROL)/sizeof(mmCRTCV_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x47d8, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x47d8, &mmCRTCV_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmCRTCV_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmCRTCV_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC0_DATA_RG", REG_MMIO, 0x47d9, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC0_DATA_RG", REG_MMIO, 0x47d9, &mmCRTCV_CRC0_DATA_RG[0], sizeof(mmCRTCV_CRC0_DATA_RG)/sizeof(mmCRTCV_CRC0_DATA_RG[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC0_DATA_B", REG_MMIO, 0x47da, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC0_DATA_B", REG_MMIO, 0x47da, &mmCRTCV_CRC0_DATA_B[0], sizeof(mmCRTCV_CRC0_DATA_B)/sizeof(mmCRTCV_CRC0_DATA_B[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x47db, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x47db, &mmCRTCV_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmCRTCV_CRC1_WINDOWA_X_CONTROL)/sizeof(mmCRTCV_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x47dc, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x47dc, &mmCRTCV_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmCRTCV_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmCRTCV_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x47dd, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x47dd, &mmCRTCV_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmCRTCV_CRC1_WINDOWB_X_CONTROL)/sizeof(mmCRTCV_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x47de, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x47de, &mmCRTCV_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmCRTCV_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmCRTCV_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC1_DATA_RG", REG_MMIO, 0x47df, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC1_DATA_RG", REG_MMIO, 0x47df, &mmCRTCV_CRC1_DATA_RG[0], sizeof(mmCRTCV_CRC1_DATA_RG)/sizeof(mmCRTCV_CRC1_DATA_RG[0]), 0, 0 },
+	{ "mmCRTCV0_CRTCV_CRC1_DATA_B", REG_MMIO, 0x47e0, NULL, 0, 0, 0 },
+	{ "mmCRTCV_CRC1_DATA_B", REG_MMIO, 0x47e0, &mmCRTCV_CRC1_DATA_B[0], sizeof(mmCRTCV_CRC1_DATA_B)/sizeof(mmCRTCV_CRC1_DATA_B[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x480, NULL, 0, 0, 0 },
+	{ "mmDC_GENERICA", REG_MMIO, 0x4800, &mmDC_GENERICA[0], sizeof(mmDC_GENERICA)/sizeof(mmDC_GENERICA[0]), 0, 0 },
+	{ "mmDC_GENERICB", REG_MMIO, 0x4801, &mmDC_GENERICB[0], sizeof(mmDC_GENERICB)/sizeof(mmDC_GENERICB[0]), 0, 0 },
+	{ "mmDC_PAD_EXTERN_SIG", REG_MMIO, 0x4802, &mmDC_PAD_EXTERN_SIG[0], sizeof(mmDC_PAD_EXTERN_SIG)/sizeof(mmDC_PAD_EXTERN_SIG[0]), 0, 0 },
+	{ "mmDC_REF_CLK_CNTL", REG_MMIO, 0x4803, &mmDC_REF_CLK_CNTL[0], sizeof(mmDC_REF_CLK_CNTL)/sizeof(mmDC_REF_CLK_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_DEBUG", REG_MMIO, 0x4804, &mmDC_GPIO_DEBUG[0], sizeof(mmDC_GPIO_DEBUG)/sizeof(mmDC_GPIO_DEBUG[0]), 0, 0 },
+	{ "mmUNIPHYA_LINK_CNTL", REG_MMIO, 0x4805, &mmUNIPHYA_LINK_CNTL[0], sizeof(mmUNIPHYA_LINK_CNTL)/sizeof(mmUNIPHYA_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYA_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4806, &mmUNIPHYA_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYA_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYA_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYB_LINK_CNTL", REG_MMIO, 0x4807, &mmUNIPHYB_LINK_CNTL[0], sizeof(mmUNIPHYB_LINK_CNTL)/sizeof(mmUNIPHYB_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYB_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4808, &mmUNIPHYB_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYB_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYB_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYC_LINK_CNTL", REG_MMIO, 0x4809, &mmUNIPHYC_LINK_CNTL[0], sizeof(mmUNIPHYC_LINK_CNTL)/sizeof(mmUNIPHYC_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYC_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480a, &mmUNIPHYC_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYC_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYC_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYD_LINK_CNTL", REG_MMIO, 0x480b, &mmUNIPHYD_LINK_CNTL[0], sizeof(mmUNIPHYD_LINK_CNTL)/sizeof(mmUNIPHYD_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYD_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480c, &mmUNIPHYD_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYD_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYD_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYE_LINK_CNTL", REG_MMIO, 0x480d, &mmUNIPHYE_LINK_CNTL[0], sizeof(mmUNIPHYE_LINK_CNTL)/sizeof(mmUNIPHYE_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYE_CHANNEL_XBAR_CNTL", REG_MMIO, 0x480e, &mmUNIPHYE_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYE_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYE_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYF_LINK_CNTL", REG_MMIO, 0x480f, &mmUNIPHYF_LINK_CNTL[0], sizeof(mmUNIPHYF_LINK_CNTL)/sizeof(mmUNIPHYF_LINK_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x481, NULL, 0, 0, 0 },
+	{ "mmUNIPHYF_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4810, &mmUNIPHYF_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYF_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYF_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYG_LINK_CNTL", REG_MMIO, 0x4811, &mmUNIPHYG_LINK_CNTL[0], sizeof(mmUNIPHYG_LINK_CNTL)/sizeof(mmUNIPHYG_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYG_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4812, &mmUNIPHYG_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYG_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmDCIO_WRCMD_DELAY", REG_MMIO, 0x4816, &mmDCIO_WRCMD_DELAY[0], sizeof(mmDCIO_WRCMD_DELAY)/sizeof(mmDCIO_WRCMD_DELAY[0]), 0, 0 },
+	{ "mmDC_PINSTRAPS", REG_MMIO, 0x4818, &mmDC_PINSTRAPS[0], sizeof(mmDC_PINSTRAPS)/sizeof(mmDC_PINSTRAPS[0]), 0, 0 },
+	{ "mmDC_DVODATA_CONFIG", REG_MMIO, 0x481a, &mmDC_DVODATA_CONFIG[0], sizeof(mmDC_DVODATA_CONFIG)/sizeof(mmDC_DVODATA_CONFIG[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_CNTL", REG_MMIO, 0x481b, &mmLVTMA_PWRSEQ_CNTL[0], sizeof(mmLVTMA_PWRSEQ_CNTL)/sizeof(mmLVTMA_PWRSEQ_CNTL[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_STATE", REG_MMIO, 0x481c, &mmLVTMA_PWRSEQ_STATE[0], sizeof(mmLVTMA_PWRSEQ_STATE)/sizeof(mmLVTMA_PWRSEQ_STATE[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_REF_DIV", REG_MMIO, 0x481d, &mmLVTMA_PWRSEQ_REF_DIV[0], sizeof(mmLVTMA_PWRSEQ_REF_DIV)/sizeof(mmLVTMA_PWRSEQ_REF_DIV[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY1", REG_MMIO, 0x481e, &mmLVTMA_PWRSEQ_DELAY1[0], sizeof(mmLVTMA_PWRSEQ_DELAY1)/sizeof(mmLVTMA_PWRSEQ_DELAY1[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY2", REG_MMIO, 0x481f, &mmLVTMA_PWRSEQ_DELAY2[0], sizeof(mmLVTMA_PWRSEQ_DELAY2)/sizeof(mmLVTMA_PWRSEQ_DELAY2[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x482, NULL, 0, 0, 0 },
+	{ "mmBL_PWM_CNTL", REG_MMIO, 0x4820, &mmBL_PWM_CNTL[0], sizeof(mmBL_PWM_CNTL)/sizeof(mmBL_PWM_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_CNTL2", REG_MMIO, 0x4821, &mmBL_PWM_CNTL2[0], sizeof(mmBL_PWM_CNTL2)/sizeof(mmBL_PWM_CNTL2[0]), 0, 0 },
+	{ "mmBL_PWM_PERIOD_CNTL", REG_MMIO, 0x4822, &mmBL_PWM_PERIOD_CNTL[0], sizeof(mmBL_PWM_PERIOD_CNTL)/sizeof(mmBL_PWM_PERIOD_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_GRP1_REG_LOCK", REG_MMIO, 0x4823, &mmBL_PWM_GRP1_REG_LOCK[0], sizeof(mmBL_PWM_GRP1_REG_LOCK)/sizeof(mmBL_PWM_GRP1_REG_LOCK[0]), 0, 0 },
+	{ "mmDCIO_GSL_GENLK_PAD_CNTL", REG_MMIO, 0x4824, &mmDCIO_GSL_GENLK_PAD_CNTL[0], sizeof(mmDCIO_GSL_GENLK_PAD_CNTL)/sizeof(mmDCIO_GSL_GENLK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL_SWAPLOCK_PAD_CNTL", REG_MMIO, 0x4825, &mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0], sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL)/sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL0_CNTL", REG_MMIO, 0x4826, &mmDCIO_GSL0_CNTL[0], sizeof(mmDCIO_GSL0_CNTL)/sizeof(mmDCIO_GSL0_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL1_CNTL", REG_MMIO, 0x4827, &mmDCIO_GSL1_CNTL[0], sizeof(mmDCIO_GSL1_CNTL)/sizeof(mmDCIO_GSL1_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL2_CNTL", REG_MMIO, 0x4828, &mmDCIO_GSL2_CNTL[0], sizeof(mmDCIO_GSL2_CNTL)/sizeof(mmDCIO_GSL2_CNTL[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_V_UPDATE", REG_MMIO, 0x4829, &mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0], sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE)/sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_P_FLIP", REG_MMIO, 0x482a, &mmDC_GPU_TIMER_START_POSITION_P_FLIP[0], sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP)/sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ", REG_MMIO, 0x482b, &mmDC_GPU_TIMER_READ[0], sizeof(mmDC_GPU_TIMER_READ)/sizeof(mmDC_GPU_TIMER_READ[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ_CNTL", REG_MMIO, 0x482c, &mmDC_GPU_TIMER_READ_CNTL[0], sizeof(mmDC_GPU_TIMER_READ_CNTL)/sizeof(mmDC_GPU_TIMER_READ_CNTL[0]), 0, 0 },
+	{ "mmDCIO_CLOCK_CNTL", REG_MMIO, 0x482d, &mmDCIO_CLOCK_CNTL[0], sizeof(mmDCIO_CLOCK_CNTL)/sizeof(mmDCIO_CLOCK_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DEBUG", REG_MMIO, 0x482f, &mmDCIO_DEBUG[0], sizeof(mmDCIO_DEBUG)/sizeof(mmDCIO_DEBUG[0]), 0, 0 },
+	{ "mmDCO_DCFE_EXT_VSYNC_CNTL", REG_MMIO, 0x4830, &mmDCO_DCFE_EXT_VSYNC_CNTL[0], sizeof(mmDCO_DCFE_EXT_VSYNC_CNTL)/sizeof(mmDCO_DCFE_EXT_VSYNC_CNTL[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_INDEX", REG_MMIO, 0x4831, &mmDCIO_TEST_DEBUG_INDEX[0], sizeof(mmDCIO_TEST_DEBUG_INDEX)/sizeof(mmDCIO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_DATA", REG_MMIO, 0x4832, &mmDCIO_TEST_DEBUG_DATA[0], sizeof(mmDCIO_TEST_DEBUG_DATA)/sizeof(mmDCIO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDBG_OUT_CNTL", REG_MMIO, 0x4834, &mmDBG_OUT_CNTL[0], sizeof(mmDBG_OUT_CNTL)/sizeof(mmDBG_OUT_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DEBUG_CONFIG", REG_MMIO, 0x4835, &mmDCIO_DEBUG_CONFIG[0], sizeof(mmDCIO_DEBUG_CONFIG)/sizeof(mmDCIO_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmDCIO_SOFT_RESET", REG_MMIO, 0x4836, &mmDCIO_SOFT_RESET[0], sizeof(mmDCIO_SOFT_RESET)/sizeof(mmDCIO_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCIO_DPHY_SEL", REG_MMIO, 0x4837, &mmDCIO_DPHY_SEL[0], sizeof(mmDCIO_DPHY_SEL)/sizeof(mmDCIO_DPHY_SEL[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKA", REG_MMIO, 0x4838, &mmUNIPHY_IMPCAL_LINKA[0], sizeof(mmUNIPHY_IMPCAL_LINKA)/sizeof(mmUNIPHY_IMPCAL_LINKA[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKB", REG_MMIO, 0x4839, &mmUNIPHY_IMPCAL_LINKB[0], sizeof(mmUNIPHY_IMPCAL_LINKB)/sizeof(mmUNIPHY_IMPCAL_LINKB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PERIOD", REG_MMIO, 0x483a, &mmUNIPHY_IMPCAL_PERIOD[0], sizeof(mmUNIPHY_IMPCAL_PERIOD)/sizeof(mmUNIPHY_IMPCAL_PERIOD[0]), 0, 0 },
+	{ "mmAUXP_IMPCAL", REG_MMIO, 0x483b, &mmAUXP_IMPCAL[0], sizeof(mmAUXP_IMPCAL)/sizeof(mmAUXP_IMPCAL[0]), 0, 0 },
+	{ "mmAUXN_IMPCAL", REG_MMIO, 0x483c, &mmAUXN_IMPCAL[0], sizeof(mmAUXN_IMPCAL)/sizeof(mmAUXN_IMPCAL[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL", REG_MMIO, 0x483d, &mmDCIO_IMPCAL_CNTL[0], sizeof(mmDCIO_IMPCAL_CNTL)/sizeof(mmDCIO_IMPCAL_CNTL[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_AB", REG_MMIO, 0x483e, &mmUNIPHY_IMPCAL_PSW_AB[0], sizeof(mmUNIPHY_IMPCAL_PSW_AB)/sizeof(mmUNIPHY_IMPCAL_PSW_AB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKC", REG_MMIO, 0x483f, &mmUNIPHY_IMPCAL_LINKC[0], sizeof(mmUNIPHY_IMPCAL_LINKC)/sizeof(mmUNIPHY_IMPCAL_LINKC[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKD", REG_MMIO, 0x4840, &mmUNIPHY_IMPCAL_LINKD[0], sizeof(mmUNIPHY_IMPCAL_LINKD)/sizeof(mmUNIPHY_IMPCAL_LINKD[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_CD", REG_MMIO, 0x4841, &mmDCIO_IMPCAL_CNTL_CD[0], sizeof(mmDCIO_IMPCAL_CNTL_CD)/sizeof(mmDCIO_IMPCAL_CNTL_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_CD", REG_MMIO, 0x4842, &mmUNIPHY_IMPCAL_PSW_CD[0], sizeof(mmUNIPHY_IMPCAL_PSW_CD)/sizeof(mmUNIPHY_IMPCAL_PSW_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKE", REG_MMIO, 0x4843, &mmUNIPHY_IMPCAL_LINKE[0], sizeof(mmUNIPHY_IMPCAL_LINKE)/sizeof(mmUNIPHY_IMPCAL_LINKE[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKF", REG_MMIO, 0x4844, &mmUNIPHY_IMPCAL_LINKF[0], sizeof(mmUNIPHY_IMPCAL_LINKF)/sizeof(mmUNIPHY_IMPCAL_LINKF[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_EF", REG_MMIO, 0x4845, &mmDCIO_IMPCAL_CNTL_EF[0], sizeof(mmDCIO_IMPCAL_CNTL_EF)/sizeof(mmDCIO_IMPCAL_CNTL_EF[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_EF", REG_MMIO, 0x4846, &mmUNIPHY_IMPCAL_PSW_EF[0], sizeof(mmUNIPHY_IMPCAL_PSW_EF)/sizeof(mmUNIPHY_IMPCAL_PSW_EF[0]), 0, 0 },
+	{ "mmUNIPHYLPA_LINK_CNTL", REG_MMIO, 0x4847, &mmUNIPHYLPA_LINK_CNTL[0], sizeof(mmUNIPHYLPA_LINK_CNTL)/sizeof(mmUNIPHYLPA_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYLPB_LINK_CNTL", REG_MMIO, 0x4848, &mmUNIPHYLPB_LINK_CNTL[0], sizeof(mmUNIPHYLPB_LINK_CNTL)/sizeof(mmUNIPHYLPB_LINK_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYLPA_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4849, &mmUNIPHYLPA_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYLPA_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYLPA_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYLPB_CHANNEL_XBAR_CNTL", REG_MMIO, 0x484a, &mmUNIPHYLPB_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHYLPB_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHYLPB_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DPCS_TX_INTERRUPT", REG_MMIO, 0x484b, &mmDCIO_DPCS_TX_INTERRUPT[0], sizeof(mmDCIO_DPCS_TX_INTERRUPT)/sizeof(mmDCIO_DPCS_TX_INTERRUPT[0]), 0, 0 },
+	{ "mmDCIO_DPCS_RX_INTERRUPT", REG_MMIO, 0x484c, &mmDCIO_DPCS_RX_INTERRUPT[0], sizeof(mmDCIO_DPCS_RX_INTERRUPT)/sizeof(mmDCIO_DPCS_RX_INTERRUPT[0]), 0, 0 },
+	{ "mmDCIO_SEMAPHORE0", REG_MMIO, 0x484d, &mmDCIO_SEMAPHORE0[0], sizeof(mmDCIO_SEMAPHORE0)/sizeof(mmDCIO_SEMAPHORE0[0]), 0, 0 },
+	{ "mmDCIO_SEMAPHORE1", REG_MMIO, 0x484e, &mmDCIO_SEMAPHORE1[0], sizeof(mmDCIO_SEMAPHORE1)/sizeof(mmDCIO_SEMAPHORE1[0]), 0, 0 },
+	{ "mmDCIO_SEMAPHORE2", REG_MMIO, 0x484f, &mmDCIO_SEMAPHORE2[0], sizeof(mmDCIO_SEMAPHORE2)/sizeof(mmDCIO_SEMAPHORE2[0]), 0, 0 },
+	{ "mmDCIO_SEMAPHORE3", REG_MMIO, 0x4850, &mmDCIO_SEMAPHORE3[0], sizeof(mmDCIO_SEMAPHORE3)/sizeof(mmDCIO_SEMAPHORE3[0]), 0, 0 },
+	{ "mmDCIO_SEMAPHORE4", REG_MMIO, 0x4851, &mmDCIO_SEMAPHORE4[0], sizeof(mmDCIO_SEMAPHORE4)/sizeof(mmDCIO_SEMAPHORE4[0]), 0, 0 },
+	{ "mmDCIO_SEMAPHORE5", REG_MMIO, 0x4852, &mmDCIO_SEMAPHORE5[0], sizeof(mmDCIO_SEMAPHORE5)/sizeof(mmDCIO_SEMAPHORE5[0]), 0, 0 },
+	{ "mmDCIO_SEMAPHORE6", REG_MMIO, 0x4853, &mmDCIO_SEMAPHORE6[0], sizeof(mmDCIO_SEMAPHORE6)/sizeof(mmDCIO_SEMAPHORE6[0]), 0, 0 },
+	{ "mmDCIO_SEMAPHORE7", REG_MMIO, 0x4854, &mmDCIO_SEMAPHORE7[0], sizeof(mmDCIO_SEMAPHORE7)/sizeof(mmDCIO_SEMAPHORE7[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_MASK", REG_MMIO, 0x4860, &mmDC_GPIO_GENERIC_MASK[0], sizeof(mmDC_GPIO_GENERIC_MASK)/sizeof(mmDC_GPIO_GENERIC_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_A", REG_MMIO, 0x4861, &mmDC_GPIO_GENERIC_A[0], sizeof(mmDC_GPIO_GENERIC_A)/sizeof(mmDC_GPIO_GENERIC_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_EN", REG_MMIO, 0x4862, &mmDC_GPIO_GENERIC_EN[0], sizeof(mmDC_GPIO_GENERIC_EN)/sizeof(mmDC_GPIO_GENERIC_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_Y", REG_MMIO, 0x4863, &mmDC_GPIO_GENERIC_Y[0], sizeof(mmDC_GPIO_GENERIC_Y)/sizeof(mmDC_GPIO_GENERIC_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_MASK", REG_MMIO, 0x4868, &mmDC_GPIO_DDC1_MASK[0], sizeof(mmDC_GPIO_DDC1_MASK)/sizeof(mmDC_GPIO_DDC1_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_A", REG_MMIO, 0x4869, &mmDC_GPIO_DDC1_A[0], sizeof(mmDC_GPIO_DDC1_A)/sizeof(mmDC_GPIO_DDC1_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_EN", REG_MMIO, 0x486a, &mmDC_GPIO_DDC1_EN[0], sizeof(mmDC_GPIO_DDC1_EN)/sizeof(mmDC_GPIO_DDC1_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_Y", REG_MMIO, 0x486b, &mmDC_GPIO_DDC1_Y[0], sizeof(mmDC_GPIO_DDC1_Y)/sizeof(mmDC_GPIO_DDC1_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_MASK", REG_MMIO, 0x486c, &mmDC_GPIO_DDC2_MASK[0], sizeof(mmDC_GPIO_DDC2_MASK)/sizeof(mmDC_GPIO_DDC2_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_A", REG_MMIO, 0x486d, &mmDC_GPIO_DDC2_A[0], sizeof(mmDC_GPIO_DDC2_A)/sizeof(mmDC_GPIO_DDC2_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_EN", REG_MMIO, 0x486e, &mmDC_GPIO_DDC2_EN[0], sizeof(mmDC_GPIO_DDC2_EN)/sizeof(mmDC_GPIO_DDC2_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_Y", REG_MMIO, 0x486f, &mmDC_GPIO_DDC2_Y[0], sizeof(mmDC_GPIO_DDC2_Y)/sizeof(mmDC_GPIO_DDC2_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_MASK", REG_MMIO, 0x4870, &mmDC_GPIO_DDC3_MASK[0], sizeof(mmDC_GPIO_DDC3_MASK)/sizeof(mmDC_GPIO_DDC3_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_A", REG_MMIO, 0x4871, &mmDC_GPIO_DDC3_A[0], sizeof(mmDC_GPIO_DDC3_A)/sizeof(mmDC_GPIO_DDC3_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_EN", REG_MMIO, 0x4872, &mmDC_GPIO_DDC3_EN[0], sizeof(mmDC_GPIO_DDC3_EN)/sizeof(mmDC_GPIO_DDC3_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_Y", REG_MMIO, 0x4873, &mmDC_GPIO_DDC3_Y[0], sizeof(mmDC_GPIO_DDC3_Y)/sizeof(mmDC_GPIO_DDC3_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_MASK", REG_MMIO, 0x4874, &mmDC_GPIO_DDC4_MASK[0], sizeof(mmDC_GPIO_DDC4_MASK)/sizeof(mmDC_GPIO_DDC4_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_A", REG_MMIO, 0x4875, &mmDC_GPIO_DDC4_A[0], sizeof(mmDC_GPIO_DDC4_A)/sizeof(mmDC_GPIO_DDC4_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_EN", REG_MMIO, 0x4876, &mmDC_GPIO_DDC4_EN[0], sizeof(mmDC_GPIO_DDC4_EN)/sizeof(mmDC_GPIO_DDC4_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_Y", REG_MMIO, 0x4877, &mmDC_GPIO_DDC4_Y[0], sizeof(mmDC_GPIO_DDC4_Y)/sizeof(mmDC_GPIO_DDC4_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_MASK", REG_MMIO, 0x4878, &mmDC_GPIO_DDC5_MASK[0], sizeof(mmDC_GPIO_DDC5_MASK)/sizeof(mmDC_GPIO_DDC5_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_A", REG_MMIO, 0x4879, &mmDC_GPIO_DDC5_A[0], sizeof(mmDC_GPIO_DDC5_A)/sizeof(mmDC_GPIO_DDC5_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_EN", REG_MMIO, 0x487a, &mmDC_GPIO_DDC5_EN[0], sizeof(mmDC_GPIO_DDC5_EN)/sizeof(mmDC_GPIO_DDC5_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_Y", REG_MMIO, 0x487b, &mmDC_GPIO_DDC5_Y[0], sizeof(mmDC_GPIO_DDC5_Y)/sizeof(mmDC_GPIO_DDC5_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_MASK", REG_MMIO, 0x487c, &mmDC_GPIO_DDC6_MASK[0], sizeof(mmDC_GPIO_DDC6_MASK)/sizeof(mmDC_GPIO_DDC6_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_A", REG_MMIO, 0x487d, &mmDC_GPIO_DDC6_A[0], sizeof(mmDC_GPIO_DDC6_A)/sizeof(mmDC_GPIO_DDC6_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_EN", REG_MMIO, 0x487e, &mmDC_GPIO_DDC6_EN[0], sizeof(mmDC_GPIO_DDC6_EN)/sizeof(mmDC_GPIO_DDC6_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_Y", REG_MMIO, 0x487f, &mmDC_GPIO_DDC6_Y[0], sizeof(mmDC_GPIO_DDC6_Y)/sizeof(mmDC_GPIO_DDC6_Y[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x488, NULL, 0, 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_MASK", REG_MMIO, 0x4880, &mmDC_GPIO_DDCVGA_MASK[0], sizeof(mmDC_GPIO_DDCVGA_MASK)/sizeof(mmDC_GPIO_DDCVGA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_A", REG_MMIO, 0x4881, &mmDC_GPIO_DDCVGA_A[0], sizeof(mmDC_GPIO_DDCVGA_A)/sizeof(mmDC_GPIO_DDCVGA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_EN", REG_MMIO, 0x4882, &mmDC_GPIO_DDCVGA_EN[0], sizeof(mmDC_GPIO_DDCVGA_EN)/sizeof(mmDC_GPIO_DDCVGA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_Y", REG_MMIO, 0x4883, &mmDC_GPIO_DDCVGA_Y[0], sizeof(mmDC_GPIO_DDCVGA_Y)/sizeof(mmDC_GPIO_DDCVGA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_MASK", REG_MMIO, 0x4884, &mmDC_GPIO_SYNCA_MASK[0], sizeof(mmDC_GPIO_SYNCA_MASK)/sizeof(mmDC_GPIO_SYNCA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_A", REG_MMIO, 0x4885, &mmDC_GPIO_SYNCA_A[0], sizeof(mmDC_GPIO_SYNCA_A)/sizeof(mmDC_GPIO_SYNCA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_EN", REG_MMIO, 0x4886, &mmDC_GPIO_SYNCA_EN[0], sizeof(mmDC_GPIO_SYNCA_EN)/sizeof(mmDC_GPIO_SYNCA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_Y", REG_MMIO, 0x4887, &mmDC_GPIO_SYNCA_Y[0], sizeof(mmDC_GPIO_SYNCA_Y)/sizeof(mmDC_GPIO_SYNCA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_MASK", REG_MMIO, 0x4888, &mmDC_GPIO_GENLK_MASK[0], sizeof(mmDC_GPIO_GENLK_MASK)/sizeof(mmDC_GPIO_GENLK_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_A", REG_MMIO, 0x4889, &mmDC_GPIO_GENLK_A[0], sizeof(mmDC_GPIO_GENLK_A)/sizeof(mmDC_GPIO_GENLK_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_EN", REG_MMIO, 0x488a, &mmDC_GPIO_GENLK_EN[0], sizeof(mmDC_GPIO_GENLK_EN)/sizeof(mmDC_GPIO_GENLK_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_Y", REG_MMIO, 0x488b, &mmDC_GPIO_GENLK_Y[0], sizeof(mmDC_GPIO_GENLK_Y)/sizeof(mmDC_GPIO_GENLK_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_MASK", REG_MMIO, 0x488c, &mmDC_GPIO_HPD_MASK[0], sizeof(mmDC_GPIO_HPD_MASK)/sizeof(mmDC_GPIO_HPD_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_A", REG_MMIO, 0x488d, &mmDC_GPIO_HPD_A[0], sizeof(mmDC_GPIO_HPD_A)/sizeof(mmDC_GPIO_HPD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_EN", REG_MMIO, 0x488e, &mmDC_GPIO_HPD_EN[0], sizeof(mmDC_GPIO_HPD_EN)/sizeof(mmDC_GPIO_HPD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_Y", REG_MMIO, 0x488f, &mmDC_GPIO_HPD_Y[0], sizeof(mmDC_GPIO_HPD_Y)/sizeof(mmDC_GPIO_HPD_Y[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x489, NULL, 0, 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_MASK", REG_MMIO, 0x4890, &mmDC_GPIO_PWRSEQ_MASK[0], sizeof(mmDC_GPIO_PWRSEQ_MASK)/sizeof(mmDC_GPIO_PWRSEQ_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_A", REG_MMIO, 0x4891, &mmDC_GPIO_PWRSEQ_A[0], sizeof(mmDC_GPIO_PWRSEQ_A)/sizeof(mmDC_GPIO_PWRSEQ_A[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_EN", REG_MMIO, 0x4892, &mmDC_GPIO_PWRSEQ_EN[0], sizeof(mmDC_GPIO_PWRSEQ_EN)/sizeof(mmDC_GPIO_PWRSEQ_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_Y", REG_MMIO, 0x4893, &mmDC_GPIO_PWRSEQ_Y[0], sizeof(mmDC_GPIO_PWRSEQ_Y)/sizeof(mmDC_GPIO_PWRSEQ_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_1", REG_MMIO, 0x4894, &mmDC_GPIO_PAD_STRENGTH_1[0], sizeof(mmDC_GPIO_PAD_STRENGTH_1)/sizeof(mmDC_GPIO_PAD_STRENGTH_1[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_2", REG_MMIO, 0x4895, &mmDC_GPIO_PAD_STRENGTH_2[0], sizeof(mmDC_GPIO_PAD_STRENGTH_2)/sizeof(mmDC_GPIO_PAD_STRENGTH_2[0]), 0, 0 },
+	{ "mmPHY_AUX_CNTL", REG_MMIO, 0x4897, &mmPHY_AUX_CNTL[0], sizeof(mmPHY_AUX_CNTL)/sizeof(mmPHY_AUX_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_A", REG_MMIO, 0x4899, &mmDC_GPIO_I2CPAD_A[0], sizeof(mmDC_GPIO_I2CPAD_A)/sizeof(mmDC_GPIO_I2CPAD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_EN", REG_MMIO, 0x489a, &mmDC_GPIO_I2CPAD_EN[0], sizeof(mmDC_GPIO_I2CPAD_EN)/sizeof(mmDC_GPIO_I2CPAD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_Y", REG_MMIO, 0x489b, &mmDC_GPIO_I2CPAD_Y[0], sizeof(mmDC_GPIO_I2CPAD_Y)/sizeof(mmDC_GPIO_I2CPAD_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_STRENGTH", REG_MMIO, 0x489c, &mmDC_GPIO_I2CPAD_STRENGTH[0], sizeof(mmDC_GPIO_I2CPAD_STRENGTH)/sizeof(mmDC_GPIO_I2CPAD_STRENGTH[0]), 0, 0 },
+	{ "mmDVO_VREF_CONTROL", REG_MMIO, 0x489e, &mmDVO_VREF_CONTROL[0], sizeof(mmDVO_VREF_CONTROL)/sizeof(mmDVO_VREF_CONTROL[0]), 0, 0 },
+	{ "mmDVO_SKEW_ADJUST", REG_MMIO, 0x489f, &mmDVO_SKEW_ADJUST[0], sizeof(mmDVO_SKEW_ADJUST)/sizeof(mmDVO_SKEW_ADJUST[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x48a, NULL, 0, 0, 0 },
+	{ "mmDC_GPIO_RECEIVER_EN0", REG_MMIO, 0x48a0, &mmDC_GPIO_RECEIVER_EN0[0], sizeof(mmDC_GPIO_RECEIVER_EN0)/sizeof(mmDC_GPIO_RECEIVER_EN0[0]), 0, 0 },
+	{ "mmDC_GPIO_RECEIVER_EN1", REG_MMIO, 0x48a1, &mmDC_GPIO_RECEIVER_EN1[0], sizeof(mmDC_GPIO_RECEIVER_EN1)/sizeof(mmDC_GPIO_RECEIVER_EN1[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_MASK", REG_MMIO, 0x48a8, &mmDC_GPIO_I2S_SPDIF_MASK[0], sizeof(mmDC_GPIO_I2S_SPDIF_MASK)/sizeof(mmDC_GPIO_I2S_SPDIF_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_A", REG_MMIO, 0x48a9, &mmDC_GPIO_I2S_SPDIF_A[0], sizeof(mmDC_GPIO_I2S_SPDIF_A)/sizeof(mmDC_GPIO_I2S_SPDIF_A[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_EN", REG_MMIO, 0x48aa, &mmDC_GPIO_I2S_SPDIF_EN[0], sizeof(mmDC_GPIO_I2S_SPDIF_EN)/sizeof(mmDC_GPIO_I2S_SPDIF_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_Y", REG_MMIO, 0x48ab, &mmDC_GPIO_I2S_SPDIF_Y[0], sizeof(mmDC_GPIO_I2S_SPDIF_Y)/sizeof(mmDC_GPIO_I2S_SPDIF_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_STRENGTH", REG_MMIO, 0x48ac, &mmDC_GPIO_I2S_SPDIF_STRENGTH[0], sizeof(mmDC_GPIO_I2S_SPDIF_STRENGTH)/sizeof(mmDC_GPIO_I2S_SPDIF_STRENGTH[0]), 0, 0 },
+	{ "mmDC_GPIO_TX12_EN", REG_MMIO, 0x48ad, &mmDC_GPIO_TX12_EN[0], sizeof(mmDC_GPIO_TX12_EN)/sizeof(mmDC_GPIO_TX12_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_AUX_CTRL_0", REG_MMIO, 0x48ae, &mmDC_GPIO_AUX_CTRL_0[0], sizeof(mmDC_GPIO_AUX_CTRL_0)/sizeof(mmDC_GPIO_AUX_CTRL_0[0]), 0, 0 },
+	{ "mmDC_GPIO_AUX_CTRL_1", REG_MMIO, 0x48af, &mmDC_GPIO_AUX_CTRL_1[0], sizeof(mmDC_GPIO_AUX_CTRL_1)/sizeof(mmDC_GPIO_AUX_CTRL_1[0]), 0, 0 },
+	{ "mmDC_GPIO_AUX_CTRL_2", REG_MMIO, 0x48b0, &mmDC_GPIO_AUX_CTRL_2[0], sizeof(mmDC_GPIO_AUX_CTRL_2)/sizeof(mmDC_GPIO_AUX_CTRL_2[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_CTRL_0", REG_MMIO, 0x48b1, &mmDC_GPIO_HPD_CTRL_0[0], sizeof(mmDC_GPIO_HPD_CTRL_0)/sizeof(mmDC_GPIO_HPD_CTRL_0[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_CTRL_1", REG_MMIO, 0x48b2, &mmDC_GPIO_HPD_CTRL_1[0], sizeof(mmDC_GPIO_HPD_CTRL_1)/sizeof(mmDC_GPIO_HPD_CTRL_1[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48b8, &mmDAC_MACRO_CNTL_RESERVED0[0], sizeof(mmDAC_MACRO_CNTL_RESERVED0)/sizeof(mmDAC_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48b9, &mmDAC_MACRO_CNTL_RESERVED1[0], sizeof(mmDAC_MACRO_CNTL_RESERVED1)/sizeof(mmDAC_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmBPHYC_DAC_MACRO_CNTL", REG_MMIO, 0x48b9, &mmBPHYC_DAC_MACRO_CNTL[0], sizeof(mmBPHYC_DAC_MACRO_CNTL)/sizeof(mmBPHYC_DAC_MACRO_CNTL[0]), 0, 0 },
+	{ "mmBPHYC_DAC_AUTO_CALIB_CONTROL", REG_MMIO, 0x48ba, &mmBPHYC_DAC_AUTO_CALIB_CONTROL[0], sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL)/sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48ba, &mmDAC_MACRO_CNTL_RESERVED2[0], sizeof(mmDAC_MACRO_CNTL_RESERVED2)/sizeof(mmDAC_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48bb, &mmDAC_MACRO_CNTL_RESERVED3[0], sizeof(mmDAC_MACRO_CNTL_RESERVED3)/sizeof(mmDAC_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48c0, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x48c0, &mmUNIPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED0)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48c1, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x48c1, &mmUNIPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED1)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48c2, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x48c2, &mmUNIPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED2)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48c3, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x48c3, &mmUNIPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED3)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmCOMMON_MAR_DEEMPH_NOM", REG_MMIO, 0x48c3, &mmCOMMON_MAR_DEEMPH_NOM[0], sizeof(mmCOMMON_MAR_DEEMPH_NOM)/sizeof(mmCOMMON_MAR_DEEMPH_NOM[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x48c4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT", REG_MMIO, 0x48c4, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x48c4, &mmUNIPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED4)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmCOMMON_LANE_PWRMGMT", REG_MMIO, 0x48c4, &mmCOMMON_LANE_PWRMGMT[0], sizeof(mmCOMMON_LANE_PWRMGMT)/sizeof(mmCOMMON_LANE_PWRMGMT[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x48c5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL", REG_MMIO, 0x48c5, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x48c5, &mmUNIPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED5)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmCOMMON_TXCNTRL", REG_MMIO, 0x48c5, &mmCOMMON_TXCNTRL[0], sizeof(mmCOMMON_TXCNTRL)/sizeof(mmCOMMON_TXCNTRL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x48c6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_TMDP", REG_MMIO, 0x48c6, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x48c6, &mmUNIPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED6)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmCOMMON_TMDP", REG_MMIO, 0x48c6, &mmCOMMON_TMDP[0], sizeof(mmCOMMON_TMDP)/sizeof(mmCOMMON_TMDP[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x48c7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS", REG_MMIO, 0x48c7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x48c7, &mmUNIPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED7)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmCOMMON_LANE_RESETS", REG_MMIO, 0x48c7, &mmCOMMON_LANE_RESETS[0], sizeof(mmCOMMON_LANE_RESETS)/sizeof(mmCOMMON_LANE_RESETS[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x48c8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x48c8, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x48c8, &mmUNIPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED8)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmCOMMON_ZCALCODE_CTRL", REG_MMIO, 0x48c8, &mmCOMMON_ZCALCODE_CTRL[0], sizeof(mmCOMMON_ZCALCODE_CTRL)/sizeof(mmCOMMON_ZCALCODE_CTRL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x48c9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1", REG_MMIO, 0x48c9, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x48c9, &mmUNIPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED9)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmCOMMON_DISP_RFU1", REG_MMIO, 0x48c9, &mmCOMMON_DISP_RFU1[0], sizeof(mmCOMMON_DISP_RFU1)/sizeof(mmCOMMON_DISP_RFU1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x48ca, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2", REG_MMIO, 0x48ca, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x48ca, &mmUNIPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED10)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmCOMMON_DISP_RFU2", REG_MMIO, 0x48ca, &mmCOMMON_DISP_RFU2[0], sizeof(mmCOMMON_DISP_RFU2)/sizeof(mmCOMMON_DISP_RFU2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x48cb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3", REG_MMIO, 0x48cb, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x48cb, &mmUNIPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED11)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmCOMMON_DISP_RFU3", REG_MMIO, 0x48cb, &mmCOMMON_DISP_RFU3[0], sizeof(mmCOMMON_DISP_RFU3)/sizeof(mmCOMMON_DISP_RFU3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x48cc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4", REG_MMIO, 0x48cc, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x48cc, &mmUNIPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED12)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmCOMMON_DISP_RFU4", REG_MMIO, 0x48cc, &mmCOMMON_DISP_RFU4[0], sizeof(mmCOMMON_DISP_RFU4)/sizeof(mmCOMMON_DISP_RFU4[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x48cd, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5", REG_MMIO, 0x48cd, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x48cd, &mmUNIPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED13)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmCOMMON_DISP_RFU5", REG_MMIO, 0x48cd, &mmCOMMON_DISP_RFU5[0], sizeof(mmCOMMON_DISP_RFU5)/sizeof(mmCOMMON_DISP_RFU5[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x48ce, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6", REG_MMIO, 0x48ce, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x48ce, &mmUNIPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED14)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmCOMMON_DISP_RFU6", REG_MMIO, 0x48ce, &mmCOMMON_DISP_RFU6[0], sizeof(mmCOMMON_DISP_RFU6)/sizeof(mmCOMMON_DISP_RFU6[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x48cf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7", REG_MMIO, 0x48cf, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x48cf, &mmUNIPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED15)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmCOMMON_DISP_RFU7", REG_MMIO, 0x48cf, &mmCOMMON_DISP_RFU7[0], sizeof(mmCOMMON_DISP_RFU7)/sizeof(mmCOMMON_DISP_RFU7[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x48d0, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x48d0, &mmUNIPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED16)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_PHY_CNTL", REG_MMIO, 0x48d0, NULL, 0, 0, 0 },
+	{ "mmDPCSTX_PHY_CNTL", REG_MMIO, 0x48d0, &mmDPCSTX_PHY_CNTL[0], sizeof(mmDPCSTX_PHY_CNTL)/sizeof(mmDPCSTX_PHY_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x48d1, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x48d1, &mmUNIPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED17)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmDPCSTX_TX_CLOCK_CNTL", REG_MMIO, 0x48d1, &mmDPCSTX_TX_CLOCK_CNTL[0], sizeof(mmDPCSTX_TX_CLOCK_CNTL)/sizeof(mmDPCSTX_TX_CLOCK_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x48d2, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x48d2, &mmUNIPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED18)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x48d3, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x48d3, &mmUNIPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED19)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_TX_CNTL", REG_MMIO, 0x48d3, NULL, 0, 0, 0 },
+	{ "mmDPCSTX_TX_CNTL", REG_MMIO, 0x48d3, &mmDPCSTX_TX_CNTL[0], sizeof(mmDPCSTX_TX_CNTL)/sizeof(mmDPCSTX_TX_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x48d4, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x48d4, &mmUNIPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED20)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x48d5, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x48d5, &mmUNIPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED21)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_CBUS_CNTL", REG_MMIO, 0x48d5, NULL, 0, 0, 0 },
+	{ "mmDPCSTX_CBUS_CNTL", REG_MMIO, 0x48d5, &mmDPCSTX_CBUS_CNTL[0], sizeof(mmDPCSTX_CBUS_CNTL)/sizeof(mmDPCSTX_CBUS_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x48d6, NULL, 0, 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x48d6, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x48d6, &mmUNIPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED22)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmDPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x48d6, &mmDPCSTX_REG_ERROR_STATUS[0], sizeof(mmDPCSTX_REG_ERROR_STATUS)/sizeof(mmDPCSTX_REG_ERROR_STATUS[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x48d7, NULL, 0, 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x48d7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x48d7, &mmUNIPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED23)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmDPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x48d7, &mmDPCSTX_TX_ERROR_STATUS[0], sizeof(mmDPCSTX_TX_ERROR_STATUS)/sizeof(mmDPCSTX_TX_ERROR_STATUS[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x48d8, NULL, 0, 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x48d8, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x48d8, &mmUNIPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED24)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x48d8, &mmDPCSTX_PLL_UPDATE_ADDR[0], sizeof(mmDPCSTX_PLL_UPDATE_ADDR)/sizeof(mmDPCSTX_PLL_UPDATE_ADDR[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x48d9, NULL, 0, 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x48d9, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x48d9, &mmUNIPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED25)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x48d9, &mmDPCSTX_PLL_UPDATE_DATA[0], sizeof(mmDPCSTX_PLL_UPDATE_DATA)/sizeof(mmDPCSTX_PLL_UPDATE_DATA[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x48da, NULL, 0, 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x48da, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x48da, &mmUNIPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED26)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x48da, &mmDPCSTX_INDEX_MODE_ADDR[0], sizeof(mmDPCSTX_INDEX_MODE_ADDR)/sizeof(mmDPCSTX_INDEX_MODE_ADDR[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x48db, NULL, 0, 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x48db, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x48db, &mmUNIPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED27)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x48db, &mmDPCSTX_INDEX_MODE_DATA[0], sizeof(mmDPCSTX_INDEX_MODE_DATA)/sizeof(mmDPCSTX_INDEX_MODE_DATA[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x48dc, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x48dc, &mmUNIPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED28)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_DEBUG_CONFIG", REG_MMIO, 0x48dc, NULL, 0, 0, 0 },
+	{ "mmDPCSTX_DEBUG_CONFIG", REG_MMIO, 0x48dc, &mmDPCSTX_DEBUG_CONFIG[0], sizeof(mmDPCSTX_DEBUG_CONFIG)/sizeof(mmDPCSTX_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x48dd, NULL, 0, 0, 0 },
+	{ "mmDPCSTX0_DPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x48dd, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x48dd, &mmUNIPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED29)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x48dd, &mmDPCSTX_TEST_DEBUG_DATA[0], sizeof(mmDPCSTX_TEST_DEBUG_DATA)/sizeof(mmDPCSTX_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x48de, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x48de, &mmUNIPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED30)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x48df, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x48df, &mmUNIPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED31)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x48e0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x48e0, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x48e0, &mmUNIPHY_MACRO_CNTL_RESERVED32[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED32)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmCMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x48e0, &mmCMD_BUS_TX_CONTROL_LANE0[0], sizeof(mmCMD_BUS_TX_CONTROL_LANE0)/sizeof(mmCMD_BUS_TX_CONTROL_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x48e1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x48e1, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x48e1, &mmUNIPHY_MACRO_CNTL_RESERVED33[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED33)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmMARGIN_DEEMPH_LANE0", REG_MMIO, 0x48e1, &mmMARGIN_DEEMPH_LANE0[0], sizeof(mmMARGIN_DEEMPH_LANE0)/sizeof(mmMARGIN_DEEMPH_LANE0[0]), 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x48e2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x48e2, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x48e2, &mmUNIPHY_MACRO_CNTL_RESERVED34[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED34)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmCMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x48e2, &mmCMD_BUS_GLOBAL_FOR_TX_LANE0[0], sizeof(mmCMD_BUS_GLOBAL_FOR_TX_LANE0)/sizeof(mmCMD_BUS_GLOBAL_FOR_TX_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x48e3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0", REG_MMIO, 0x48e3, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x48e3, &mmUNIPHY_MACRO_CNTL_RESERVED35[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED35)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmTX_DISP_RFU0_LANE0", REG_MMIO, 0x48e3, &mmTX_DISP_RFU0_LANE0[0], sizeof(mmTX_DISP_RFU0_LANE0)/sizeof(mmTX_DISP_RFU0_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x48e4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0", REG_MMIO, 0x48e4, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x48e4, &mmUNIPHY_MACRO_CNTL_RESERVED36[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED36)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmTX_DISP_RFU1_LANE0", REG_MMIO, 0x48e4, &mmTX_DISP_RFU1_LANE0[0], sizeof(mmTX_DISP_RFU1_LANE0)/sizeof(mmTX_DISP_RFU1_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x48e5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0", REG_MMIO, 0x48e5, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x48e5, &mmUNIPHY_MACRO_CNTL_RESERVED37[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED37)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmTX_DISP_RFU2_LANE0", REG_MMIO, 0x48e5, &mmTX_DISP_RFU2_LANE0[0], sizeof(mmTX_DISP_RFU2_LANE0)/sizeof(mmTX_DISP_RFU2_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x48e6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0", REG_MMIO, 0x48e6, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x48e6, &mmUNIPHY_MACRO_CNTL_RESERVED38[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED38)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmTX_DISP_RFU3_LANE0", REG_MMIO, 0x48e6, &mmTX_DISP_RFU3_LANE0[0], sizeof(mmTX_DISP_RFU3_LANE0)/sizeof(mmTX_DISP_RFU3_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x48e7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0", REG_MMIO, 0x48e7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x48e7, &mmUNIPHY_MACRO_CNTL_RESERVED39[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED39)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmTX_DISP_RFU4_LANE0", REG_MMIO, 0x48e7, &mmTX_DISP_RFU4_LANE0[0], sizeof(mmTX_DISP_RFU4_LANE0)/sizeof(mmTX_DISP_RFU4_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x48e8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0", REG_MMIO, 0x48e8, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x48e8, &mmUNIPHY_MACRO_CNTL_RESERVED40[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED40)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmTX_DISP_RFU5_LANE0", REG_MMIO, 0x48e8, &mmTX_DISP_RFU5_LANE0[0], sizeof(mmTX_DISP_RFU5_LANE0)/sizeof(mmTX_DISP_RFU5_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x48e9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0", REG_MMIO, 0x48e9, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x48e9, &mmUNIPHY_MACRO_CNTL_RESERVED41[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED41)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmTX_DISP_RFU6_LANE0", REG_MMIO, 0x48e9, &mmTX_DISP_RFU6_LANE0[0], sizeof(mmTX_DISP_RFU6_LANE0)/sizeof(mmTX_DISP_RFU6_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x48ea, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0", REG_MMIO, 0x48ea, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x48ea, &mmUNIPHY_MACRO_CNTL_RESERVED42[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED42)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED42[0]), 0, 0 },
+	{ "mmTX_DISP_RFU7_LANE0", REG_MMIO, 0x48ea, &mmTX_DISP_RFU7_LANE0[0], sizeof(mmTX_DISP_RFU7_LANE0)/sizeof(mmTX_DISP_RFU7_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x48eb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0", REG_MMIO, 0x48eb, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x48eb, &mmUNIPHY_MACRO_CNTL_RESERVED43[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED43)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED43[0]), 0, 0 },
+	{ "mmTX_DISP_RFU8_LANE0", REG_MMIO, 0x48eb, &mmTX_DISP_RFU8_LANE0[0], sizeof(mmTX_DISP_RFU8_LANE0)/sizeof(mmTX_DISP_RFU8_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x48ec, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0", REG_MMIO, 0x48ec, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x48ec, &mmUNIPHY_MACRO_CNTL_RESERVED44[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED44)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED44[0]), 0, 0 },
+	{ "mmTX_DISP_RFU9_LANE0", REG_MMIO, 0x48ec, &mmTX_DISP_RFU9_LANE0[0], sizeof(mmTX_DISP_RFU9_LANE0)/sizeof(mmTX_DISP_RFU9_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x48ed, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0", REG_MMIO, 0x48ed, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x48ed, &mmUNIPHY_MACRO_CNTL_RESERVED45[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED45)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED45[0]), 0, 0 },
+	{ "mmTX_DISP_RFU10_LANE0", REG_MMIO, 0x48ed, &mmTX_DISP_RFU10_LANE0[0], sizeof(mmTX_DISP_RFU10_LANE0)/sizeof(mmTX_DISP_RFU10_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x48ee, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0", REG_MMIO, 0x48ee, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x48ee, &mmUNIPHY_MACRO_CNTL_RESERVED46[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED46)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED46[0]), 0, 0 },
+	{ "mmTX_DISP_RFU11_LANE0", REG_MMIO, 0x48ee, &mmTX_DISP_RFU11_LANE0[0], sizeof(mmTX_DISP_RFU11_LANE0)/sizeof(mmTX_DISP_RFU11_LANE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x48ef, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0", REG_MMIO, 0x48ef, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x48ef, &mmUNIPHY_MACRO_CNTL_RESERVED47[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED47)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED47[0]), 0, 0 },
+	{ "mmTX_DISP_RFU12_LANE0", REG_MMIO, 0x48ef, &mmTX_DISP_RFU12_LANE0[0], sizeof(mmTX_DISP_RFU12_LANE0)/sizeof(mmTX_DISP_RFU12_LANE0[0]), 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x48f0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x48f0, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x48f0, &mmUNIPHY_MACRO_CNTL_RESERVED48[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED48)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED48[0]), 0, 0 },
+	{ "mmCMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x48f0, &mmCMD_BUS_TX_CONTROL_LANE1[0], sizeof(mmCMD_BUS_TX_CONTROL_LANE1)/sizeof(mmCMD_BUS_TX_CONTROL_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x48f1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x48f1, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x48f1, &mmUNIPHY_MACRO_CNTL_RESERVED49[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED49)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED49[0]), 0, 0 },
+	{ "mmMARGIN_DEEMPH_LANE1", REG_MMIO, 0x48f1, &mmMARGIN_DEEMPH_LANE1[0], sizeof(mmMARGIN_DEEMPH_LANE1)/sizeof(mmMARGIN_DEEMPH_LANE1[0]), 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x48f2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x48f2, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x48f2, &mmUNIPHY_MACRO_CNTL_RESERVED50[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED50)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED50[0]), 0, 0 },
+	{ "mmCMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x48f2, &mmCMD_BUS_GLOBAL_FOR_TX_LANE1[0], sizeof(mmCMD_BUS_GLOBAL_FOR_TX_LANE1)/sizeof(mmCMD_BUS_GLOBAL_FOR_TX_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x48f3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1", REG_MMIO, 0x48f3, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x48f3, &mmUNIPHY_MACRO_CNTL_RESERVED51[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED51)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED51[0]), 0, 0 },
+	{ "mmTX_DISP_RFU0_LANE1", REG_MMIO, 0x48f3, &mmTX_DISP_RFU0_LANE1[0], sizeof(mmTX_DISP_RFU0_LANE1)/sizeof(mmTX_DISP_RFU0_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x48f4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1", REG_MMIO, 0x48f4, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x48f4, &mmUNIPHY_MACRO_CNTL_RESERVED52[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED52)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED52[0]), 0, 0 },
+	{ "mmTX_DISP_RFU1_LANE1", REG_MMIO, 0x48f4, &mmTX_DISP_RFU1_LANE1[0], sizeof(mmTX_DISP_RFU1_LANE1)/sizeof(mmTX_DISP_RFU1_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x48f5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1", REG_MMIO, 0x48f5, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x48f5, &mmUNIPHY_MACRO_CNTL_RESERVED53[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED53)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED53[0]), 0, 0 },
+	{ "mmTX_DISP_RFU2_LANE1", REG_MMIO, 0x48f5, &mmTX_DISP_RFU2_LANE1[0], sizeof(mmTX_DISP_RFU2_LANE1)/sizeof(mmTX_DISP_RFU2_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x48f6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1", REG_MMIO, 0x48f6, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x48f6, &mmUNIPHY_MACRO_CNTL_RESERVED54[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED54)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED54[0]), 0, 0 },
+	{ "mmTX_DISP_RFU3_LANE1", REG_MMIO, 0x48f6, &mmTX_DISP_RFU3_LANE1[0], sizeof(mmTX_DISP_RFU3_LANE1)/sizeof(mmTX_DISP_RFU3_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x48f7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1", REG_MMIO, 0x48f7, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x48f7, &mmUNIPHY_MACRO_CNTL_RESERVED55[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED55)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED55[0]), 0, 0 },
+	{ "mmTX_DISP_RFU4_LANE1", REG_MMIO, 0x48f7, &mmTX_DISP_RFU4_LANE1[0], sizeof(mmTX_DISP_RFU4_LANE1)/sizeof(mmTX_DISP_RFU4_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x48f8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1", REG_MMIO, 0x48f8, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x48f8, &mmUNIPHY_MACRO_CNTL_RESERVED56[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED56)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED56[0]), 0, 0 },
+	{ "mmTX_DISP_RFU5_LANE1", REG_MMIO, 0x48f8, &mmTX_DISP_RFU5_LANE1[0], sizeof(mmTX_DISP_RFU5_LANE1)/sizeof(mmTX_DISP_RFU5_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x48f9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1", REG_MMIO, 0x48f9, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x48f9, &mmUNIPHY_MACRO_CNTL_RESERVED57[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED57)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED57[0]), 0, 0 },
+	{ "mmTX_DISP_RFU6_LANE1", REG_MMIO, 0x48f9, &mmTX_DISP_RFU6_LANE1[0], sizeof(mmTX_DISP_RFU6_LANE1)/sizeof(mmTX_DISP_RFU6_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x48fa, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1", REG_MMIO, 0x48fa, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x48fa, &mmUNIPHY_MACRO_CNTL_RESERVED58[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED58)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED58[0]), 0, 0 },
+	{ "mmTX_DISP_RFU7_LANE1", REG_MMIO, 0x48fa, &mmTX_DISP_RFU7_LANE1[0], sizeof(mmTX_DISP_RFU7_LANE1)/sizeof(mmTX_DISP_RFU7_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x48fb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1", REG_MMIO, 0x48fb, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x48fb, &mmUNIPHY_MACRO_CNTL_RESERVED59[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED59)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED59[0]), 0, 0 },
+	{ "mmTX_DISP_RFU8_LANE1", REG_MMIO, 0x48fb, &mmTX_DISP_RFU8_LANE1[0], sizeof(mmTX_DISP_RFU8_LANE1)/sizeof(mmTX_DISP_RFU8_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x48fc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1", REG_MMIO, 0x48fc, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x48fc, &mmUNIPHY_MACRO_CNTL_RESERVED60[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED60)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED60[0]), 0, 0 },
+	{ "mmTX_DISP_RFU9_LANE1", REG_MMIO, 0x48fc, &mmTX_DISP_RFU9_LANE1[0], sizeof(mmTX_DISP_RFU9_LANE1)/sizeof(mmTX_DISP_RFU9_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x48fd, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1", REG_MMIO, 0x48fd, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x48fd, &mmUNIPHY_MACRO_CNTL_RESERVED61[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED61)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED61[0]), 0, 0 },
+	{ "mmTX_DISP_RFU10_LANE1", REG_MMIO, 0x48fd, &mmTX_DISP_RFU10_LANE1[0], sizeof(mmTX_DISP_RFU10_LANE1)/sizeof(mmTX_DISP_RFU10_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x48fe, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1", REG_MMIO, 0x48fe, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x48fe, &mmUNIPHY_MACRO_CNTL_RESERVED62[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED62)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED62[0]), 0, 0 },
+	{ "mmTX_DISP_RFU11_LANE1", REG_MMIO, 0x48fe, &mmTX_DISP_RFU11_LANE1[0], sizeof(mmTX_DISP_RFU11_LANE1)/sizeof(mmTX_DISP_RFU11_LANE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x48ff, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1", REG_MMIO, 0x48ff, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x48ff, &mmUNIPHY_MACRO_CNTL_RESERVED63[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED63)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED63[0]), 0, 0 },
+	{ "mmTX_DISP_RFU12_LANE1", REG_MMIO, 0x48ff, &mmTX_DISP_RFU12_LANE1[0], sizeof(mmTX_DISP_RFU12_LANE1)/sizeof(mmTX_DISP_RFU12_LANE1[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x490, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x4900, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x4900, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x4900, &mmUNIPHY_MACRO_CNTL_RESERVED64[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED64)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED64[0]), 0, 0 },
+	{ "mmCMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x4900, &mmCMD_BUS_TX_CONTROL_LANE2[0], sizeof(mmCMD_BUS_TX_CONTROL_LANE2)/sizeof(mmCMD_BUS_TX_CONTROL_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x4901, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x4901, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x4901, &mmUNIPHY_MACRO_CNTL_RESERVED65[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED65)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED65[0]), 0, 0 },
+	{ "mmMARGIN_DEEMPH_LANE2", REG_MMIO, 0x4901, &mmMARGIN_DEEMPH_LANE2[0], sizeof(mmMARGIN_DEEMPH_LANE2)/sizeof(mmMARGIN_DEEMPH_LANE2[0]), 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x4902, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x4902, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x4902, &mmUNIPHY_MACRO_CNTL_RESERVED66[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED66)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED66[0]), 0, 0 },
+	{ "mmCMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x4902, &mmCMD_BUS_GLOBAL_FOR_TX_LANE2[0], sizeof(mmCMD_BUS_GLOBAL_FOR_TX_LANE2)/sizeof(mmCMD_BUS_GLOBAL_FOR_TX_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x4903, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2", REG_MMIO, 0x4903, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x4903, &mmUNIPHY_MACRO_CNTL_RESERVED67[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED67)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED67[0]), 0, 0 },
+	{ "mmTX_DISP_RFU0_LANE2", REG_MMIO, 0x4903, &mmTX_DISP_RFU0_LANE2[0], sizeof(mmTX_DISP_RFU0_LANE2)/sizeof(mmTX_DISP_RFU0_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x4904, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2", REG_MMIO, 0x4904, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x4904, &mmUNIPHY_MACRO_CNTL_RESERVED68[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED68)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED68[0]), 0, 0 },
+	{ "mmTX_DISP_RFU1_LANE2", REG_MMIO, 0x4904, &mmTX_DISP_RFU1_LANE2[0], sizeof(mmTX_DISP_RFU1_LANE2)/sizeof(mmTX_DISP_RFU1_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x4905, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2", REG_MMIO, 0x4905, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x4905, &mmUNIPHY_MACRO_CNTL_RESERVED69[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED69)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED69[0]), 0, 0 },
+	{ "mmTX_DISP_RFU2_LANE2", REG_MMIO, 0x4905, &mmTX_DISP_RFU2_LANE2[0], sizeof(mmTX_DISP_RFU2_LANE2)/sizeof(mmTX_DISP_RFU2_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x4906, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2", REG_MMIO, 0x4906, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x4906, &mmUNIPHY_MACRO_CNTL_RESERVED70[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED70)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED70[0]), 0, 0 },
+	{ "mmTX_DISP_RFU3_LANE2", REG_MMIO, 0x4906, &mmTX_DISP_RFU3_LANE2[0], sizeof(mmTX_DISP_RFU3_LANE2)/sizeof(mmTX_DISP_RFU3_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x4907, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2", REG_MMIO, 0x4907, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x4907, &mmUNIPHY_MACRO_CNTL_RESERVED71[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED71)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED71[0]), 0, 0 },
+	{ "mmTX_DISP_RFU4_LANE2", REG_MMIO, 0x4907, &mmTX_DISP_RFU4_LANE2[0], sizeof(mmTX_DISP_RFU4_LANE2)/sizeof(mmTX_DISP_RFU4_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x4908, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2", REG_MMIO, 0x4908, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x4908, &mmUNIPHY_MACRO_CNTL_RESERVED72[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED72)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED72[0]), 0, 0 },
+	{ "mmTX_DISP_RFU5_LANE2", REG_MMIO, 0x4908, &mmTX_DISP_RFU5_LANE2[0], sizeof(mmTX_DISP_RFU5_LANE2)/sizeof(mmTX_DISP_RFU5_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x4909, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2", REG_MMIO, 0x4909, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x4909, &mmUNIPHY_MACRO_CNTL_RESERVED73[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED73)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED73[0]), 0, 0 },
+	{ "mmTX_DISP_RFU6_LANE2", REG_MMIO, 0x4909, &mmTX_DISP_RFU6_LANE2[0], sizeof(mmTX_DISP_RFU6_LANE2)/sizeof(mmTX_DISP_RFU6_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x490a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2", REG_MMIO, 0x490a, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x490a, &mmUNIPHY_MACRO_CNTL_RESERVED74[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED74)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED74[0]), 0, 0 },
+	{ "mmTX_DISP_RFU7_LANE2", REG_MMIO, 0x490a, &mmTX_DISP_RFU7_LANE2[0], sizeof(mmTX_DISP_RFU7_LANE2)/sizeof(mmTX_DISP_RFU7_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x490b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2", REG_MMIO, 0x490b, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x490b, &mmUNIPHY_MACRO_CNTL_RESERVED75[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED75)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED75[0]), 0, 0 },
+	{ "mmTX_DISP_RFU8_LANE2", REG_MMIO, 0x490b, &mmTX_DISP_RFU8_LANE2[0], sizeof(mmTX_DISP_RFU8_LANE2)/sizeof(mmTX_DISP_RFU8_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x490c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2", REG_MMIO, 0x490c, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x490c, &mmUNIPHY_MACRO_CNTL_RESERVED76[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED76)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED76[0]), 0, 0 },
+	{ "mmTX_DISP_RFU9_LANE2", REG_MMIO, 0x490c, &mmTX_DISP_RFU9_LANE2[0], sizeof(mmTX_DISP_RFU9_LANE2)/sizeof(mmTX_DISP_RFU9_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x490d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2", REG_MMIO, 0x490d, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x490d, &mmUNIPHY_MACRO_CNTL_RESERVED77[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED77)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED77[0]), 0, 0 },
+	{ "mmTX_DISP_RFU10_LANE2", REG_MMIO, 0x490d, &mmTX_DISP_RFU10_LANE2[0], sizeof(mmTX_DISP_RFU10_LANE2)/sizeof(mmTX_DISP_RFU10_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x490e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2", REG_MMIO, 0x490e, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x490e, &mmUNIPHY_MACRO_CNTL_RESERVED78[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED78)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED78[0]), 0, 0 },
+	{ "mmTX_DISP_RFU11_LANE2", REG_MMIO, 0x490e, &mmTX_DISP_RFU11_LANE2[0], sizeof(mmTX_DISP_RFU11_LANE2)/sizeof(mmTX_DISP_RFU11_LANE2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x490f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2", REG_MMIO, 0x490f, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x490f, &mmUNIPHY_MACRO_CNTL_RESERVED79[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED79)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED79[0]), 0, 0 },
+	{ "mmTX_DISP_RFU12_LANE2", REG_MMIO, 0x490f, &mmTX_DISP_RFU12_LANE2[0], sizeof(mmTX_DISP_RFU12_LANE2)/sizeof(mmTX_DISP_RFU12_LANE2[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x491, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x4910, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x4910, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x4910, &mmUNIPHY_MACRO_CNTL_RESERVED80[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED80)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED80[0]), 0, 0 },
+	{ "mmCMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x4910, &mmCMD_BUS_TX_CONTROL_LANE3[0], sizeof(mmCMD_BUS_TX_CONTROL_LANE3)/sizeof(mmCMD_BUS_TX_CONTROL_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x4911, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x4911, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x4911, &mmUNIPHY_MACRO_CNTL_RESERVED81[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED81)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED81[0]), 0, 0 },
+	{ "mmMARGIN_DEEMPH_LANE3", REG_MMIO, 0x4911, &mmMARGIN_DEEMPH_LANE3[0], sizeof(mmMARGIN_DEEMPH_LANE3)/sizeof(mmMARGIN_DEEMPH_LANE3[0]), 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x4912, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x4912, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x4912, &mmUNIPHY_MACRO_CNTL_RESERVED82[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED82)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED82[0]), 0, 0 },
+	{ "mmCMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x4912, &mmCMD_BUS_GLOBAL_FOR_TX_LANE3[0], sizeof(mmCMD_BUS_GLOBAL_FOR_TX_LANE3)/sizeof(mmCMD_BUS_GLOBAL_FOR_TX_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x4913, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3", REG_MMIO, 0x4913, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x4913, &mmUNIPHY_MACRO_CNTL_RESERVED83[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED83)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED83[0]), 0, 0 },
+	{ "mmTX_DISP_RFU0_LANE3", REG_MMIO, 0x4913, &mmTX_DISP_RFU0_LANE3[0], sizeof(mmTX_DISP_RFU0_LANE3)/sizeof(mmTX_DISP_RFU0_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x4914, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3", REG_MMIO, 0x4914, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x4914, &mmUNIPHY_MACRO_CNTL_RESERVED84[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED84)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED84[0]), 0, 0 },
+	{ "mmTX_DISP_RFU1_LANE3", REG_MMIO, 0x4914, &mmTX_DISP_RFU1_LANE3[0], sizeof(mmTX_DISP_RFU1_LANE3)/sizeof(mmTX_DISP_RFU1_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x4915, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3", REG_MMIO, 0x4915, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x4915, &mmUNIPHY_MACRO_CNTL_RESERVED85[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED85)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED85[0]), 0, 0 },
+	{ "mmTX_DISP_RFU2_LANE3", REG_MMIO, 0x4915, &mmTX_DISP_RFU2_LANE3[0], sizeof(mmTX_DISP_RFU2_LANE3)/sizeof(mmTX_DISP_RFU2_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x4916, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3", REG_MMIO, 0x4916, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x4916, &mmUNIPHY_MACRO_CNTL_RESERVED86[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED86)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED86[0]), 0, 0 },
+	{ "mmTX_DISP_RFU3_LANE3", REG_MMIO, 0x4916, &mmTX_DISP_RFU3_LANE3[0], sizeof(mmTX_DISP_RFU3_LANE3)/sizeof(mmTX_DISP_RFU3_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x4917, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3", REG_MMIO, 0x4917, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x4917, &mmUNIPHY_MACRO_CNTL_RESERVED87[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED87)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED87[0]), 0, 0 },
+	{ "mmTX_DISP_RFU4_LANE3", REG_MMIO, 0x4917, &mmTX_DISP_RFU4_LANE3[0], sizeof(mmTX_DISP_RFU4_LANE3)/sizeof(mmTX_DISP_RFU4_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x4918, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3", REG_MMIO, 0x4918, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x4918, &mmUNIPHY_MACRO_CNTL_RESERVED88[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED88)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED88[0]), 0, 0 },
+	{ "mmTX_DISP_RFU5_LANE3", REG_MMIO, 0x4918, &mmTX_DISP_RFU5_LANE3[0], sizeof(mmTX_DISP_RFU5_LANE3)/sizeof(mmTX_DISP_RFU5_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x4919, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3", REG_MMIO, 0x4919, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x4919, &mmUNIPHY_MACRO_CNTL_RESERVED89[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED89)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED89[0]), 0, 0 },
+	{ "mmTX_DISP_RFU6_LANE3", REG_MMIO, 0x4919, &mmTX_DISP_RFU6_LANE3[0], sizeof(mmTX_DISP_RFU6_LANE3)/sizeof(mmTX_DISP_RFU6_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x491a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3", REG_MMIO, 0x491a, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x491a, &mmUNIPHY_MACRO_CNTL_RESERVED90[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED90)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED90[0]), 0, 0 },
+	{ "mmTX_DISP_RFU7_LANE3", REG_MMIO, 0x491a, &mmTX_DISP_RFU7_LANE3[0], sizeof(mmTX_DISP_RFU7_LANE3)/sizeof(mmTX_DISP_RFU7_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x491b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3", REG_MMIO, 0x491b, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x491b, &mmUNIPHY_MACRO_CNTL_RESERVED91[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED91)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED91[0]), 0, 0 },
+	{ "mmTX_DISP_RFU8_LANE3", REG_MMIO, 0x491b, &mmTX_DISP_RFU8_LANE3[0], sizeof(mmTX_DISP_RFU8_LANE3)/sizeof(mmTX_DISP_RFU8_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x491c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3", REG_MMIO, 0x491c, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x491c, &mmUNIPHY_MACRO_CNTL_RESERVED92[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED92)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED92[0]), 0, 0 },
+	{ "mmTX_DISP_RFU9_LANE3", REG_MMIO, 0x491c, &mmTX_DISP_RFU9_LANE3[0], sizeof(mmTX_DISP_RFU9_LANE3)/sizeof(mmTX_DISP_RFU9_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x491d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3", REG_MMIO, 0x491d, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x491d, &mmUNIPHY_MACRO_CNTL_RESERVED93[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED93)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED93[0]), 0, 0 },
+	{ "mmTX_DISP_RFU10_LANE3", REG_MMIO, 0x491d, &mmTX_DISP_RFU10_LANE3[0], sizeof(mmTX_DISP_RFU10_LANE3)/sizeof(mmTX_DISP_RFU10_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x491e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3", REG_MMIO, 0x491e, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x491e, &mmUNIPHY_MACRO_CNTL_RESERVED94[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED94)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED94[0]), 0, 0 },
+	{ "mmTX_DISP_RFU11_LANE3", REG_MMIO, 0x491e, &mmTX_DISP_RFU11_LANE3[0], sizeof(mmTX_DISP_RFU11_LANE3)/sizeof(mmTX_DISP_RFU11_LANE3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x491f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3", REG_MMIO, 0x491f, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x491f, &mmUNIPHY_MACRO_CNTL_RESERVED95[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED95)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED95[0]), 0, 0 },
+	{ "mmTX_DISP_RFU12_LANE3", REG_MMIO, 0x491f, &mmTX_DISP_RFU12_LANE3[0], sizeof(mmTX_DISP_RFU12_LANE3)/sizeof(mmTX_DISP_RFU12_LANE3[0]), 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x492, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x4920, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0", REG_MMIO, 0x4920, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x4920, &mmUNIPHY_MACRO_CNTL_RESERVED96[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED96)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED96[0]), 0, 0 },
+	{ "mmFREQ_CTRL0", REG_MMIO, 0x4920, &mmFREQ_CTRL0[0], sizeof(mmFREQ_CTRL0)/sizeof(mmFREQ_CTRL0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x4921, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1", REG_MMIO, 0x4921, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x4921, &mmUNIPHY_MACRO_CNTL_RESERVED97[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED97)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED97[0]), 0, 0 },
+	{ "mmFREQ_CTRL1", REG_MMIO, 0x4921, &mmFREQ_CTRL1[0], sizeof(mmFREQ_CTRL1)/sizeof(mmFREQ_CTRL1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x4922, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2", REG_MMIO, 0x4922, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x4922, &mmUNIPHY_MACRO_CNTL_RESERVED98[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED98)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED98[0]), 0, 0 },
+	{ "mmFREQ_CTRL2", REG_MMIO, 0x4922, &mmFREQ_CTRL2[0], sizeof(mmFREQ_CTRL2)/sizeof(mmFREQ_CTRL2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x4923, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3", REG_MMIO, 0x4923, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x4923, &mmUNIPHY_MACRO_CNTL_RESERVED99[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED99)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED99[0]), 0, 0 },
+	{ "mmFREQ_CTRL3", REG_MMIO, 0x4923, &mmFREQ_CTRL3[0], sizeof(mmFREQ_CTRL3)/sizeof(mmFREQ_CTRL3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x4924, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE", REG_MMIO, 0x4924, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x4924, &mmUNIPHY_MACRO_CNTL_RESERVED100[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED100)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED100[0]), 0, 0 },
+	{ "mmBW_CTRL_COARSE", REG_MMIO, 0x4924, &mmBW_CTRL_COARSE[0], sizeof(mmBW_CTRL_COARSE)/sizeof(mmBW_CTRL_COARSE[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x4925, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE", REG_MMIO, 0x4925, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x4925, &mmUNIPHY_MACRO_CNTL_RESERVED101[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED101)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED101[0]), 0, 0 },
+	{ "mmBW_CTRL_FINE", REG_MMIO, 0x4925, &mmBW_CTRL_FINE[0], sizeof(mmBW_CTRL_FINE)/sizeof(mmBW_CTRL_FINE[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x4926, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x4926, &mmUNIPHY_MACRO_CNTL_RESERVED102[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED102)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED102[0]), 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_CAL_CTRL", REG_MMIO, 0x4926, NULL, 0, 0, 0 },
+	{ "mmCAL_CTRL", REG_MMIO, 0x4926, &mmCAL_CTRL[0], sizeof(mmCAL_CTRL)/sizeof(mmCAL_CTRL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x4927, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x4927, &mmUNIPHY_MACRO_CNTL_RESERVED103[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED103)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED103[0]), 0, 0 },
+	{ "mmLOOP_CTRL", REG_MMIO, 0x4927, &mmLOOP_CTRL[0], sizeof(mmLOOP_CTRL)/sizeof(mmLOOP_CTRL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x4928, &mmUNIPHY_MACRO_CNTL_RESERVED104[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED104)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED104[0]), 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_DEBUG0", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmDEBUG0", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x4929, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x4929, &mmUNIPHY_MACRO_CNTL_RESERVED105[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED105)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED105[0]), 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_VREG_CFG", REG_MMIO, 0x4929, NULL, 0, 0, 0 },
+	{ "mmVREG_CFG", REG_MMIO, 0x4929, &mmVREG_CFG[0], sizeof(mmVREG_CFG)/sizeof(mmVREG_CFG[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x492a, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x492a, &mmUNIPHY_MACRO_CNTL_RESERVED106[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED106)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED106[0]), 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_OBSERVE0", REG_MMIO, 0x492a, NULL, 0, 0, 0 },
+	{ "mmOBSERVE0", REG_MMIO, 0x492a, &mmOBSERVE0[0], sizeof(mmOBSERVE0)/sizeof(mmOBSERVE0[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x492b, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x492b, &mmUNIPHY_MACRO_CNTL_RESERVED107[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED107)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED107[0]), 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_OBSERVE1", REG_MMIO, 0x492b, NULL, 0, 0, 0 },
+	{ "mmOBSERVE1", REG_MMIO, 0x492b, &mmOBSERVE1[0], sizeof(mmOBSERVE1)/sizeof(mmOBSERVE1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x492c, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x492c, &mmUNIPHY_MACRO_CNTL_RESERVED108[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED108)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED108[0]), 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_DFT_OUT", REG_MMIO, 0x492c, NULL, 0, 0, 0 },
+	{ "mmDFT_OUT", REG_MMIO, 0x492c, &mmDFT_OUT[0], sizeof(mmDFT_OUT)/sizeof(mmDFT_OUT[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x492d, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x492d, &mmUNIPHY_MACRO_CNTL_RESERVED109[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED109)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED109[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x492e, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x492e, &mmUNIPHY_MACRO_CNTL_RESERVED110[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED110)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED110[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x492f, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x492f, &mmUNIPHY_MACRO_CNTL_RESERVED111[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED111)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED111[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x4930, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x4930, &mmUNIPHY_MACRO_CNTL_RESERVED112[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED112)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED112[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x4931, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x4931, &mmUNIPHY_MACRO_CNTL_RESERVED113[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED113)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED113[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x4932, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x4932, &mmUNIPHY_MACRO_CNTL_RESERVED114[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED114)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED114[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x4933, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x4933, &mmUNIPHY_MACRO_CNTL_RESERVED115[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED115)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED115[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x4934, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x4934, &mmUNIPHY_MACRO_CNTL_RESERVED116[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED116)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED116[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x4935, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x4935, &mmUNIPHY_MACRO_CNTL_RESERVED117[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED117)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED117[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x4936, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x4936, &mmUNIPHY_MACRO_CNTL_RESERVED118[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED118)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED118[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x4937, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x4937, &mmUNIPHY_MACRO_CNTL_RESERVED119[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED119)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED119[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x4938, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x4938, &mmUNIPHY_MACRO_CNTL_RESERVED120[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED120)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED120[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x4939, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x4939, &mmUNIPHY_MACRO_CNTL_RESERVED121[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED121)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED121[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x493a, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x493a, &mmUNIPHY_MACRO_CNTL_RESERVED122[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED122)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED122[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x493b, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x493b, &mmUNIPHY_MACRO_CNTL_RESERVED123[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED123)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED123[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x493c, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x493c, &mmUNIPHY_MACRO_CNTL_RESERVED124[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED124)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED124[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x493d, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x493d, &mmUNIPHY_MACRO_CNTL_RESERVED125[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED125)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED125[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x493e, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x493e, &mmUNIPHY_MACRO_CNTL_RESERVED126[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED126)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED126[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x493f, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x493f, &mmUNIPHY_MACRO_CNTL_RESERVED127[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED127)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED127[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x4940, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x4940, &mmUNIPHY_MACRO_CNTL_RESERVED128[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED128)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED128[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x4941, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x4941, &mmUNIPHY_MACRO_CNTL_RESERVED129[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED129)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED129[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x4942, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x4942, &mmUNIPHY_MACRO_CNTL_RESERVED130[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED130)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED130[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x4943, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x4943, &mmUNIPHY_MACRO_CNTL_RESERVED131[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED131)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED131[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x4944, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x4944, &mmUNIPHY_MACRO_CNTL_RESERVED132[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED132)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED132[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x4945, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x4945, &mmUNIPHY_MACRO_CNTL_RESERVED133[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED133)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED133[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x4946, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x4946, &mmUNIPHY_MACRO_CNTL_RESERVED134[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED134)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED134[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x4947, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x4947, &mmUNIPHY_MACRO_CNTL_RESERVED135[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED135)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED135[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x4948, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x4948, &mmUNIPHY_MACRO_CNTL_RESERVED136[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED136)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED136[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x4949, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x4949, &mmUNIPHY_MACRO_CNTL_RESERVED137[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED137)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED137[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x494a, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x494a, &mmUNIPHY_MACRO_CNTL_RESERVED138[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED138)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED138[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x494b, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x494b, &mmUNIPHY_MACRO_CNTL_RESERVED139[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED139)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED139[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x494c, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x494c, &mmUNIPHY_MACRO_CNTL_RESERVED140[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED140)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED140[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x494d, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x494d, &mmUNIPHY_MACRO_CNTL_RESERVED141[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED141)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED141[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x494e, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x494e, &mmUNIPHY_MACRO_CNTL_RESERVED142[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED142)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED142[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x494f, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x494f, &mmUNIPHY_MACRO_CNTL_RESERVED143[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED143)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED143[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x4950, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x4950, &mmUNIPHY_MACRO_CNTL_RESERVED144[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED144)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED144[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x4951, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x4951, &mmUNIPHY_MACRO_CNTL_RESERVED145[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED145)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED145[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x4952, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x4952, &mmUNIPHY_MACRO_CNTL_RESERVED146[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED146)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED146[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x4953, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x4953, &mmUNIPHY_MACRO_CNTL_RESERVED147[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED147)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED147[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x4954, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x4954, &mmUNIPHY_MACRO_CNTL_RESERVED148[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED148)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED148[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x4955, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x4955, &mmUNIPHY_MACRO_CNTL_RESERVED149[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED149)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED149[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x4956, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x4956, &mmUNIPHY_MACRO_CNTL_RESERVED150[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED150)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED150[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x4957, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x4957, &mmUNIPHY_MACRO_CNTL_RESERVED151[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED151)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED151[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x4958, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x4958, &mmUNIPHY_MACRO_CNTL_RESERVED152[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED152)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED152[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x4959, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x4959, &mmUNIPHY_MACRO_CNTL_RESERVED153[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED153)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED153[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x495a, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x495a, &mmUNIPHY_MACRO_CNTL_RESERVED154[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED154)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED154[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x495b, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x495b, &mmUNIPHY_MACRO_CNTL_RESERVED155[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED155)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED155[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x495c, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x495c, &mmUNIPHY_MACRO_CNTL_RESERVED156[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED156)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED156[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x495d, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x495d, &mmUNIPHY_MACRO_CNTL_RESERVED157[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED157)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED157[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x495e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1", REG_MMIO, 0x495e, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x495e, &mmUNIPHY_MACRO_CNTL_RESERVED158[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED158)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED158[0]), 0, 0 },
+	{ "mmPLL_WRAP_CNTRL1", REG_MMIO, 0x495e, &mmPLL_WRAP_CNTRL1[0], sizeof(mmPLL_WRAP_CNTRL1)/sizeof(mmPLL_WRAP_CNTRL1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x495f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL", REG_MMIO, 0x495f, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x495f, &mmUNIPHY_MACRO_CNTL_RESERVED159[0], sizeof(mmUNIPHY_MACRO_CNTL_RESERVED159)/sizeof(mmUNIPHY_MACRO_CNTL_RESERVED159[0]), 0, 0 },
+	{ "mmPLL_WRAP_CNTRL", REG_MMIO, 0x495f, &mmPLL_WRAP_CNTRL[0], sizeof(mmPLL_WRAP_CNTRL)/sizeof(mmPLL_WRAP_CNTRL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x4960, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x4961, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x4962, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x4963, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x4964, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT", REG_MMIO, 0x4964, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x4965, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL", REG_MMIO, 0x4965, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x4966, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_TMDP", REG_MMIO, 0x4966, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x4967, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS", REG_MMIO, 0x4967, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x4968, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x4968, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x4969, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1", REG_MMIO, 0x4969, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x496a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2", REG_MMIO, 0x496a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x496b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3", REG_MMIO, 0x496b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x496c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4", REG_MMIO, 0x496c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x496d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5", REG_MMIO, 0x496d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x496e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6", REG_MMIO, 0x496e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x496f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7", REG_MMIO, 0x496f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x4970, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_PHY_CNTL", REG_MMIO, 0x4970, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x4971, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_TX_CLOCK_CNTL", REG_MMIO, 0x4971, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x4972, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x4973, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_TX_CNTL", REG_MMIO, 0x4973, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x4974, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x4975, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_CBUS_CNTL", REG_MMIO, 0x4975, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x4976, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x4976, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x4977, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x4977, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x4978, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x4978, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x4979, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x4979, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x497a, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x497a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x497b, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x497b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x497c, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_DEBUG_CONFIG", REG_MMIO, 0x497c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x497d, NULL, 0, 0, 0 },
+	{ "mmDPCSTX1_DPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x497d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x497e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x497f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x498, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x4980, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x4980, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x4981, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x4981, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x4982, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x4982, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x4983, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0", REG_MMIO, 0x4983, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x4984, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0", REG_MMIO, 0x4984, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x4985, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0", REG_MMIO, 0x4985, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x4986, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0", REG_MMIO, 0x4986, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x4987, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0", REG_MMIO, 0x4987, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x4988, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0", REG_MMIO, 0x4988, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x4989, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0", REG_MMIO, 0x4989, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x498a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0", REG_MMIO, 0x498a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x498b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0", REG_MMIO, 0x498b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x498c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0", REG_MMIO, 0x498c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x498d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0", REG_MMIO, 0x498d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x498e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0", REG_MMIO, 0x498e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x498f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0", REG_MMIO, 0x498f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x499, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x4990, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x4990, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x4991, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x4991, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x4992, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x4992, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x4993, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1", REG_MMIO, 0x4993, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x4994, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1", REG_MMIO, 0x4994, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x4995, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1", REG_MMIO, 0x4995, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x4996, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1", REG_MMIO, 0x4996, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x4997, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1", REG_MMIO, 0x4997, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x4998, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1", REG_MMIO, 0x4998, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x4999, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1", REG_MMIO, 0x4999, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x499a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1", REG_MMIO, 0x499a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x499b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1", REG_MMIO, 0x499b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x499c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1", REG_MMIO, 0x499c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x499d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1", REG_MMIO, 0x499d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x499e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1", REG_MMIO, 0x499e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x499f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1", REG_MMIO, 0x499f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x49a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x49a0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x49a0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x49a1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x49a1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x49a2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x49a2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x49a3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2", REG_MMIO, 0x49a3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x49a4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2", REG_MMIO, 0x49a4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x49a5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2", REG_MMIO, 0x49a5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x49a6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2", REG_MMIO, 0x49a6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x49a7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2", REG_MMIO, 0x49a7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x49a8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2", REG_MMIO, 0x49a8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x49a9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2", REG_MMIO, 0x49a9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x49aa, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2", REG_MMIO, 0x49aa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x49ab, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2", REG_MMIO, 0x49ab, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x49ac, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2", REG_MMIO, 0x49ac, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x49ad, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2", REG_MMIO, 0x49ad, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x49ae, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2", REG_MMIO, 0x49ae, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x49af, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2", REG_MMIO, 0x49af, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x49b0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x49b0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x49b1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x49b1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x49b2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x49b2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x49b3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3", REG_MMIO, 0x49b3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x49b4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3", REG_MMIO, 0x49b4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x49b5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3", REG_MMIO, 0x49b5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x49b6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3", REG_MMIO, 0x49b6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x49b7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3", REG_MMIO, 0x49b7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x49b8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3", REG_MMIO, 0x49b8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x49b9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3", REG_MMIO, 0x49b9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x49ba, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3", REG_MMIO, 0x49ba, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x49bb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3", REG_MMIO, 0x49bb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x49bc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3", REG_MMIO, 0x49bc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x49bd, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3", REG_MMIO, 0x49bd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x49be, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3", REG_MMIO, 0x49be, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x49bf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3", REG_MMIO, 0x49bf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x49c0, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0", REG_MMIO, 0x49c0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x49c1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1", REG_MMIO, 0x49c1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x49c2, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2", REG_MMIO, 0x49c2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x49c3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3", REG_MMIO, 0x49c3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x49c4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE", REG_MMIO, 0x49c4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x49c5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE", REG_MMIO, 0x49c5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x49c6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_CAL_CTRL", REG_MMIO, 0x49c6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x49c7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_LOOP_CTRL", REG_MMIO, 0x49c7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x49c8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_DEBUG0", REG_MMIO, 0x49c8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x49c9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_VREG_CFG", REG_MMIO, 0x49c9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x49ca, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_OBSERVE0", REG_MMIO, 0x49ca, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x49cb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_OBSERVE1", REG_MMIO, 0x49cb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x49cc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_DFT_OUT", REG_MMIO, 0x49cc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x49cd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x49ce, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x49cf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x49d0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x49d1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x49d2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x49d3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x49d4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x49d5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x49d6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x49d7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x49d8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x49d9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x49da, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x49db, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x49dc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x49dd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x49de, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x49df, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x49e0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x49e1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x49e2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x49e3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x49e4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x49e5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x49e6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x49e7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x49e8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x49e9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x49ea, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x49eb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x49ec, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x49ed, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x49ee, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x49ef, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x49f0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x49f1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x49f2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x49f3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x49f4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x49f5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x49f6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x49f7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x49f8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x49f9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x49fa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x49fb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x49fc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x49fd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x49fe, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1", REG_MMIO, 0x49fe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x49ff, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL", REG_MMIO, 0x49ff, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_FE_CNTL", REG_MMIO, 0x4a00, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_CNTL", REG_MMIO, 0x4a00, &mmDIG_FE_CNTL[0], sizeof(mmDIG_FE_CNTL)/sizeof(mmDIG_FE_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4a01, NULL, 0, 0, 0 },
+	{ "mmDIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4a01, &mmDIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG_OUTPUT_CRC_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4a02, NULL, 0, 0, 0 },
+	{ "mmDIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4a02, &mmDIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG_OUTPUT_CRC_RESULT[0]), 0, 0 },
+	{ "mmDIG0_DIG_CLOCK_PATTERN", REG_MMIO, 0x4a03, NULL, 0, 0, 0 },
+	{ "mmDIG_CLOCK_PATTERN", REG_MMIO, 0x4a03, &mmDIG_CLOCK_PATTERN[0], sizeof(mmDIG_CLOCK_PATTERN)/sizeof(mmDIG_CLOCK_PATTERN[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_PATTERN", REG_MMIO, 0x4a04, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_PATTERN", REG_MMIO, 0x4a04, &mmDIG_TEST_PATTERN[0], sizeof(mmDIG_TEST_PATTERN)/sizeof(mmDIG_TEST_PATTERN[0]), 0, 0 },
+	{ "mmDIG0_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4a05, NULL, 0, 0, 0 },
+	{ "mmDIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4a05, &mmDIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG_RANDOM_PATTERN_SEED[0]), 0, 0 },
+	{ "mmDIG0_DIG_FIFO_STATUS", REG_MMIO, 0x4a06, NULL, 0, 0, 0 },
+	{ "mmDIG_FIFO_STATUS", REG_MMIO, 0x4a06, &mmDIG_FIFO_STATUS[0], sizeof(mmDIG_FIFO_STATUS)/sizeof(mmDIG_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4a07, NULL, 0, 0, 0 },
+	{ "mmDIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4a07, &mmDIG_DISPCLK_SWITCH_CNTL[0], sizeof(mmDIG_DISPCLK_SWITCH_CNTL)/sizeof(mmDIG_DISPCLK_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4a08, NULL, 0, 0, 0 },
+	{ "mmDIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4a08, &mmDIG_DISPCLK_SWITCH_STATUS[0], sizeof(mmDIG_DISPCLK_SWITCH_STATUS)/sizeof(mmDIG_DISPCLK_SWITCH_STATUS[0]), 0, 0 },
+	{ "mmDIG0_HDMI_CONTROL", REG_MMIO, 0x4a09, NULL, 0, 0, 0 },
+	{ "mmHDMI_CONTROL", REG_MMIO, 0x4a09, &mmHDMI_CONTROL[0], sizeof(mmHDMI_CONTROL)/sizeof(mmHDMI_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_STATUS", REG_MMIO, 0x4a0a, NULL, 0, 0, 0 },
+	{ "mmHDMI_STATUS", REG_MMIO, 0x4a0a, &mmHDMI_STATUS[0], sizeof(mmHDMI_STATUS)/sizeof(mmHDMI_STATUS[0]), 0, 0 },
+	{ "mmDIG0_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a0b, NULL, 0, 0, 0 },
+	{ "mmHDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a0b, &mmHDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmHDMI_AUDIO_PACKET_CONTROL)/sizeof(mmHDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4a0c, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4a0c, &mmHDMI_ACR_PACKET_CONTROL[0], sizeof(mmHDMI_ACR_PACKET_CONTROL)/sizeof(mmHDMI_ACR_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4a0d, NULL, 0, 0, 0 },
+	{ "mmHDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4a0d, &mmHDMI_VBI_PACKET_CONTROL[0], sizeof(mmHDMI_VBI_PACKET_CONTROL)/sizeof(mmHDMI_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4a0e, NULL, 0, 0, 0 },
+	{ "mmHDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4a0e, &mmHDMI_INFOFRAME_CONTROL0[0], sizeof(mmHDMI_INFOFRAME_CONTROL0)/sizeof(mmHDMI_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4a0f, NULL, 0, 0, 0 },
+	{ "mmHDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4a0f, &mmHDMI_INFOFRAME_CONTROL1[0], sizeof(mmHDMI_INFOFRAME_CONTROL1)/sizeof(mmHDMI_INFOFRAME_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4a10, NULL, 0, 0, 0 },
+	{ "mmHDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4a10, &mmHDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmHDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmHDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4a11, NULL, 0, 0, 0 },
+	{ "mmAFMT_INTERRUPT_STATUS", REG_MMIO, 0x4a11, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_GC", REG_MMIO, 0x4a13, NULL, 0, 0, 0 },
+	{ "mmHDMI_GC", REG_MMIO, 0x4a13, &mmHDMI_GC[0], sizeof(mmHDMI_GC)/sizeof(mmHDMI_GC[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4a14, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4a14, &mmAFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_0", REG_MMIO, 0x4a15, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_0", REG_MMIO, 0x4a15, &mmAFMT_ISRC1_0[0], sizeof(mmAFMT_ISRC1_0)/sizeof(mmAFMT_ISRC1_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_1", REG_MMIO, 0x4a16, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_1", REG_MMIO, 0x4a16, &mmAFMT_ISRC1_1[0], sizeof(mmAFMT_ISRC1_1)/sizeof(mmAFMT_ISRC1_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_2", REG_MMIO, 0x4a17, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_2", REG_MMIO, 0x4a17, &mmAFMT_ISRC1_2[0], sizeof(mmAFMT_ISRC1_2)/sizeof(mmAFMT_ISRC1_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_3", REG_MMIO, 0x4a18, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_3", REG_MMIO, 0x4a18, &mmAFMT_ISRC1_3[0], sizeof(mmAFMT_ISRC1_3)/sizeof(mmAFMT_ISRC1_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_4", REG_MMIO, 0x4a19, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_4", REG_MMIO, 0x4a19, &mmAFMT_ISRC1_4[0], sizeof(mmAFMT_ISRC1_4)/sizeof(mmAFMT_ISRC1_4[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_0", REG_MMIO, 0x4a1a, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_0", REG_MMIO, 0x4a1a, &mmAFMT_ISRC2_0[0], sizeof(mmAFMT_ISRC2_0)/sizeof(mmAFMT_ISRC2_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_1", REG_MMIO, 0x4a1b, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_1", REG_MMIO, 0x4a1b, &mmAFMT_ISRC2_1[0], sizeof(mmAFMT_ISRC2_1)/sizeof(mmAFMT_ISRC2_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_2", REG_MMIO, 0x4a1c, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_2", REG_MMIO, 0x4a1c, &mmAFMT_ISRC2_2[0], sizeof(mmAFMT_ISRC2_2)/sizeof(mmAFMT_ISRC2_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_3", REG_MMIO, 0x4a1d, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_3", REG_MMIO, 0x4a1d, &mmAFMT_ISRC2_3[0], sizeof(mmAFMT_ISRC2_3)/sizeof(mmAFMT_ISRC2_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO0", REG_MMIO, 0x4a1e, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO0", REG_MMIO, 0x4a1e, &mmAFMT_AVI_INFO0[0], sizeof(mmAFMT_AVI_INFO0)/sizeof(mmAFMT_AVI_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO1", REG_MMIO, 0x4a1f, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO1", REG_MMIO, 0x4a1f, &mmAFMT_AVI_INFO1[0], sizeof(mmAFMT_AVI_INFO1)/sizeof(mmAFMT_AVI_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO2", REG_MMIO, 0x4a20, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO2", REG_MMIO, 0x4a20, &mmAFMT_AVI_INFO2[0], sizeof(mmAFMT_AVI_INFO2)/sizeof(mmAFMT_AVI_INFO2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO3", REG_MMIO, 0x4a21, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO3", REG_MMIO, 0x4a21, &mmAFMT_AVI_INFO3[0], sizeof(mmAFMT_AVI_INFO3)/sizeof(mmAFMT_AVI_INFO3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_MPEG_INFO0", REG_MMIO, 0x4a22, NULL, 0, 0, 0 },
+	{ "mmAFMT_MPEG_INFO0", REG_MMIO, 0x4a22, &mmAFMT_MPEG_INFO0[0], sizeof(mmAFMT_MPEG_INFO0)/sizeof(mmAFMT_MPEG_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_MPEG_INFO1", REG_MMIO, 0x4a23, NULL, 0, 0, 0 },
+	{ "mmAFMT_MPEG_INFO1", REG_MMIO, 0x4a23, &mmAFMT_MPEG_INFO1[0], sizeof(mmAFMT_MPEG_INFO1)/sizeof(mmAFMT_MPEG_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_HDR", REG_MMIO, 0x4a24, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_HDR", REG_MMIO, 0x4a24, &mmAFMT_GENERIC_HDR[0], sizeof(mmAFMT_GENERIC_HDR)/sizeof(mmAFMT_GENERIC_HDR[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_0", REG_MMIO, 0x4a25, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_0", REG_MMIO, 0x4a25, &mmAFMT_GENERIC_0[0], sizeof(mmAFMT_GENERIC_0)/sizeof(mmAFMT_GENERIC_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_1", REG_MMIO, 0x4a26, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_1", REG_MMIO, 0x4a26, &mmAFMT_GENERIC_1[0], sizeof(mmAFMT_GENERIC_1)/sizeof(mmAFMT_GENERIC_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_2", REG_MMIO, 0x4a27, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_2", REG_MMIO, 0x4a27, &mmAFMT_GENERIC_2[0], sizeof(mmAFMT_GENERIC_2)/sizeof(mmAFMT_GENERIC_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_3", REG_MMIO, 0x4a28, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_3", REG_MMIO, 0x4a28, &mmAFMT_GENERIC_3[0], sizeof(mmAFMT_GENERIC_3)/sizeof(mmAFMT_GENERIC_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_4", REG_MMIO, 0x4a29, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_4", REG_MMIO, 0x4a29, &mmAFMT_GENERIC_4[0], sizeof(mmAFMT_GENERIC_4)/sizeof(mmAFMT_GENERIC_4[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_5", REG_MMIO, 0x4a2a, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_5", REG_MMIO, 0x4a2a, &mmAFMT_GENERIC_5[0], sizeof(mmAFMT_GENERIC_5)/sizeof(mmAFMT_GENERIC_5[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_6", REG_MMIO, 0x4a2b, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_6", REG_MMIO, 0x4a2b, &mmAFMT_GENERIC_6[0], sizeof(mmAFMT_GENERIC_6)/sizeof(mmAFMT_GENERIC_6[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_7", REG_MMIO, 0x4a2c, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_7", REG_MMIO, 0x4a2c, &mmAFMT_GENERIC_7[0], sizeof(mmAFMT_GENERIC_7)/sizeof(mmAFMT_GENERIC_7[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4a2d, NULL, 0, 0, 0 },
+	{ "mmHDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4a2d, &mmHDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmHDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmHDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_0", REG_MMIO, 0x4a2e, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_32_0", REG_MMIO, 0x4a2e, &mmHDMI_ACR_32_0[0], sizeof(mmHDMI_ACR_32_0)/sizeof(mmHDMI_ACR_32_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_1", REG_MMIO, 0x4a2f, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_32_1", REG_MMIO, 0x4a2f, &mmHDMI_ACR_32_1[0], sizeof(mmHDMI_ACR_32_1)/sizeof(mmHDMI_ACR_32_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_0", REG_MMIO, 0x4a30, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_44_0", REG_MMIO, 0x4a30, &mmHDMI_ACR_44_0[0], sizeof(mmHDMI_ACR_44_0)/sizeof(mmHDMI_ACR_44_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_1", REG_MMIO, 0x4a31, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_44_1", REG_MMIO, 0x4a31, &mmHDMI_ACR_44_1[0], sizeof(mmHDMI_ACR_44_1)/sizeof(mmHDMI_ACR_44_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_0", REG_MMIO, 0x4a32, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_48_0", REG_MMIO, 0x4a32, &mmHDMI_ACR_48_0[0], sizeof(mmHDMI_ACR_48_0)/sizeof(mmHDMI_ACR_48_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_1", REG_MMIO, 0x4a33, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_48_1", REG_MMIO, 0x4a33, &mmHDMI_ACR_48_1[0], sizeof(mmHDMI_ACR_48_1)/sizeof(mmHDMI_ACR_48_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_0", REG_MMIO, 0x4a34, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_STATUS_0", REG_MMIO, 0x4a34, &mmHDMI_ACR_STATUS_0[0], sizeof(mmHDMI_ACR_STATUS_0)/sizeof(mmHDMI_ACR_STATUS_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_1", REG_MMIO, 0x4a35, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_STATUS_1", REG_MMIO, 0x4a35, &mmHDMI_ACR_STATUS_1[0], sizeof(mmHDMI_ACR_STATUS_1)/sizeof(mmHDMI_ACR_STATUS_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_INFO0", REG_MMIO, 0x4a36, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO0", REG_MMIO, 0x4a36, &mmAFMT_AUDIO_INFO0[0], sizeof(mmAFMT_AUDIO_INFO0)/sizeof(mmAFMT_AUDIO_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_INFO1", REG_MMIO, 0x4a37, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO1", REG_MMIO, 0x4a37, &mmAFMT_AUDIO_INFO1[0], sizeof(mmAFMT_AUDIO_INFO1)/sizeof(mmAFMT_AUDIO_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_0", REG_MMIO, 0x4a38, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_0", REG_MMIO, 0x4a38, &mmAFMT_60958_0[0], sizeof(mmAFMT_60958_0)/sizeof(mmAFMT_60958_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_1", REG_MMIO, 0x4a39, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_1", REG_MMIO, 0x4a39, &mmAFMT_60958_1[0], sizeof(mmAFMT_60958_1)/sizeof(mmAFMT_60958_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4a3a, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4a3a, &mmAFMT_AUDIO_CRC_CONTROL[0], sizeof(mmAFMT_AUDIO_CRC_CONTROL)/sizeof(mmAFMT_AUDIO_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4a3b, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL0", REG_MMIO, 0x4a3b, &mmAFMT_RAMP_CONTROL0[0], sizeof(mmAFMT_RAMP_CONTROL0)/sizeof(mmAFMT_RAMP_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4a3c, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL1", REG_MMIO, 0x4a3c, &mmAFMT_RAMP_CONTROL1[0], sizeof(mmAFMT_RAMP_CONTROL1)/sizeof(mmAFMT_RAMP_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4a3d, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL2", REG_MMIO, 0x4a3d, &mmAFMT_RAMP_CONTROL2[0], sizeof(mmAFMT_RAMP_CONTROL2)/sizeof(mmAFMT_RAMP_CONTROL2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4a3e, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL3", REG_MMIO, 0x4a3e, &mmAFMT_RAMP_CONTROL3[0], sizeof(mmAFMT_RAMP_CONTROL3)/sizeof(mmAFMT_RAMP_CONTROL3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_2", REG_MMIO, 0x4a3f, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_2", REG_MMIO, 0x4a3f, &mmAFMT_60958_2[0], sizeof(mmAFMT_60958_2)/sizeof(mmAFMT_60958_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4a40, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4a40, &mmAFMT_AUDIO_CRC_RESULT[0], sizeof(mmAFMT_AUDIO_CRC_RESULT)/sizeof(mmAFMT_AUDIO_CRC_RESULT[0]), 0, 0 },
+	{ "mmDIG0_AFMT_STATUS", REG_MMIO, 0x4a41, NULL, 0, 0, 0 },
+	{ "mmAFMT_STATUS", REG_MMIO, 0x4a41, &mmAFMT_STATUS[0], sizeof(mmAFMT_STATUS)/sizeof(mmAFMT_STATUS[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a42, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4a42, &mmAFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4a43, NULL, 0, 0, 0 },
+	{ "mmAFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4a43, &mmAFMT_VBI_PACKET_CONTROL[0], sizeof(mmAFMT_VBI_PACKET_CONTROL)/sizeof(mmAFMT_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4a44, NULL, 0, 0, 0 },
+	{ "mmAFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4a44, &mmAFMT_INFOFRAME_CONTROL0[0], sizeof(mmAFMT_INFOFRAME_CONTROL0)/sizeof(mmAFMT_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4a45, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4a45, &mmAFMT_AUDIO_SRC_CONTROL[0], sizeof(mmAFMT_AUDIO_SRC_CONTROL)/sizeof(mmAFMT_AUDIO_SRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4a46, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4a46, &mmAFMT_AUDIO_DBG_DTO_CNTL[0], sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL)/sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_CNTL", REG_MMIO, 0x4a47, NULL, 0, 0, 0 },
+	{ "mmDIG_BE_CNTL", REG_MMIO, 0x4a47, &mmDIG_BE_CNTL[0], sizeof(mmDIG_BE_CNTL)/sizeof(mmDIG_BE_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_EN_CNTL", REG_MMIO, 0x4a48, NULL, 0, 0, 0 },
+	{ "mmDIG_BE_EN_CNTL", REG_MMIO, 0x4a48, &mmDIG_BE_EN_CNTL[0], sizeof(mmDIG_BE_EN_CNTL)/sizeof(mmDIG_BE_EN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CNTL", REG_MMIO, 0x4a6b, NULL, 0, 0, 0 },
+	{ "mmTMDS_CNTL", REG_MMIO, 0x4a6b, &mmTMDS_CNTL[0], sizeof(mmTMDS_CNTL)/sizeof(mmTMDS_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL_CHAR", REG_MMIO, 0x4a6c, NULL, 0, 0, 0 },
+	{ "mmTMDS_CONTROL_CHAR", REG_MMIO, 0x4a6c, &mmTMDS_CONTROL_CHAR[0], sizeof(mmTMDS_CONTROL_CHAR)/sizeof(mmTMDS_CONTROL_CHAR[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4a6d, NULL, 0, 0, 0 },
+	{ "mmTMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4a6d, &mmTMDS_CONTROL0_FEEDBACK[0], sizeof(mmTMDS_CONTROL0_FEEDBACK)/sizeof(mmTMDS_CONTROL0_FEEDBACK[0]), 0, 0 },
+	{ "mmDIG0_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4a6e, NULL, 0, 0, 0 },
+	{ "mmTMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4a6e, &mmTMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmTMDS_STEREOSYNC_CTL_SEL)/sizeof(mmTMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4a6f, NULL, 0, 0, 0 },
+	{ "mmTMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4a6f, &mmTMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmTMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmTMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4a70, NULL, 0, 0, 0 },
+	{ "mmTMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4a70, &mmTMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmTMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmTMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 },
+	{ "mmDIG0_TMDS_DEBUG", REG_MMIO, 0x4a71, NULL, 0, 0, 0 },
+	{ "mmTMDS_DEBUG", REG_MMIO, 0x4a71, &mmTMDS_DEBUG[0], sizeof(mmTMDS_DEBUG)/sizeof(mmTMDS_DEBUG[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL_BITS", REG_MMIO, 0x4a72, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL_BITS", REG_MMIO, 0x4a72, &mmTMDS_CTL_BITS[0], sizeof(mmTMDS_CTL_BITS)/sizeof(mmTMDS_CTL_BITS[0]), 0, 0 },
+	{ "mmDIG0_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4a73, NULL, 0, 0, 0 },
+	{ "mmTMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4a73, &mmTMDS_DCBALANCER_CONTROL[0], sizeof(mmTMDS_DCBALANCER_CONTROL)/sizeof(mmTMDS_DCBALANCER_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4a75, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4a75, &mmTMDS_CTL0_1_GEN_CNTL[0], sizeof(mmTMDS_CTL0_1_GEN_CNTL)/sizeof(mmTMDS_CTL0_1_GEN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4a76, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4a76, &mmTMDS_CTL2_3_GEN_CNTL[0], sizeof(mmTMDS_CTL2_3_GEN_CNTL)/sizeof(mmTMDS_CTL2_3_GEN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_VERSION", REG_MMIO, 0x4a78, NULL, 0, 0, 0 },
+	{ "mmDIG_VERSION", REG_MMIO, 0x4a78, &mmDIG_VERSION[0], sizeof(mmDIG_VERSION)/sizeof(mmDIG_VERSION[0]), 0, 0 },
+	{ "mmDIG0_DIG_LANE_ENABLE", REG_MMIO, 0x4a79, NULL, 0, 0, 0 },
+	{ "mmDIG_LANE_ENABLE", REG_MMIO, 0x4a79, &mmDIG_LANE_ENABLE[0], sizeof(mmDIG_LANE_ENABLE)/sizeof(mmDIG_LANE_ENABLE[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7a, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7a, &mmDIG_TEST_DEBUG_INDEX[0], sizeof(mmDIG_TEST_DEBUG_INDEX)/sizeof(mmDIG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4a7b, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_DEBUG_DATA", REG_MMIO, 0x4a7b, &mmDIG_TEST_DEBUG_DATA[0], sizeof(mmDIG_TEST_DEBUG_DATA)/sizeof(mmDIG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDIG0_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7c, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4a7c, &mmDIG_FE_TEST_DEBUG_INDEX[0], sizeof(mmDIG_FE_TEST_DEBUG_INDEX)/sizeof(mmDIG_FE_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDIG0_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4a7d, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4a7d, &mmDIG_FE_TEST_DEBUG_DATA[0], sizeof(mmDIG_FE_TEST_DEBUG_DATA)/sizeof(mmDIG_FE_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDIG0_AFMT_CNTL", REG_MMIO, 0x4a7e, NULL, 0, 0, 0 },
+	{ "mmAFMT_CNTL", REG_MMIO, 0x4a7e, &mmAFMT_CNTL[0], sizeof(mmAFMT_CNTL)/sizeof(mmAFMT_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_LINK_CNTL", REG_MMIO, 0x4aa0, NULL, 0, 0, 0 },
+	{ "mmDP_LINK_CNTL", REG_MMIO, 0x4aa0, &mmDP_LINK_CNTL[0], sizeof(mmDP_LINK_CNTL)/sizeof(mmDP_LINK_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_PIXEL_FORMAT", REG_MMIO, 0x4aa1, NULL, 0, 0, 0 },
+	{ "mmDP_PIXEL_FORMAT", REG_MMIO, 0x4aa1, &mmDP_PIXEL_FORMAT[0], sizeof(mmDP_PIXEL_FORMAT)/sizeof(mmDP_PIXEL_FORMAT[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_COLORIMETRY", REG_MMIO, 0x4aa2, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_COLORIMETRY", REG_MMIO, 0x4aa2, &mmDP_MSA_COLORIMETRY[0], sizeof(mmDP_MSA_COLORIMETRY)/sizeof(mmDP_MSA_COLORIMETRY[0]), 0, 0 },
+	{ "mmDP0_DP_CONFIG", REG_MMIO, 0x4aa3, NULL, 0, 0, 0 },
+	{ "mmDP_CONFIG", REG_MMIO, 0x4aa3, &mmDP_CONFIG[0], sizeof(mmDP_CONFIG)/sizeof(mmDP_CONFIG[0]), 0, 0 },
+	{ "mmDP0_DP_VID_STREAM_CNTL", REG_MMIO, 0x4aa4, NULL, 0, 0, 0 },
+	{ "mmDP_VID_STREAM_CNTL", REG_MMIO, 0x4aa4, &mmDP_VID_STREAM_CNTL[0], sizeof(mmDP_VID_STREAM_CNTL)/sizeof(mmDP_VID_STREAM_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_STEER_FIFO", REG_MMIO, 0x4aa5, NULL, 0, 0, 0 },
+	{ "mmDP_STEER_FIFO", REG_MMIO, 0x4aa5, &mmDP_STEER_FIFO[0], sizeof(mmDP_STEER_FIFO)/sizeof(mmDP_STEER_FIFO[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_MISC", REG_MMIO, 0x4aa6, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_MISC", REG_MMIO, 0x4aa6, &mmDP_MSA_MISC[0], sizeof(mmDP_MSA_MISC)/sizeof(mmDP_MSA_MISC[0]), 0, 0 },
+	{ "mmDP0_DP_VID_TIMING", REG_MMIO, 0x4aa8, NULL, 0, 0, 0 },
+	{ "mmDP_VID_TIMING", REG_MMIO, 0x4aa8, &mmDP_VID_TIMING[0], sizeof(mmDP_VID_TIMING)/sizeof(mmDP_VID_TIMING[0]), 0, 0 },
+	{ "mmDP0_DP_VID_N", REG_MMIO, 0x4aa9, NULL, 0, 0, 0 },
+	{ "mmDP_VID_N", REG_MMIO, 0x4aa9, &mmDP_VID_N[0], sizeof(mmDP_VID_N)/sizeof(mmDP_VID_N[0]), 0, 0 },
+	{ "mmDP0_DP_VID_M", REG_MMIO, 0x4aaa, NULL, 0, 0, 0 },
+	{ "mmDP_VID_M", REG_MMIO, 0x4aaa, &mmDP_VID_M[0], sizeof(mmDP_VID_M)/sizeof(mmDP_VID_M[0]), 0, 0 },
+	{ "mmDP0_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4aab, NULL, 0, 0, 0 },
+	{ "mmDP_LINK_FRAMING_CNTL", REG_MMIO, 0x4aab, &mmDP_LINK_FRAMING_CNTL[0], sizeof(mmDP_LINK_FRAMING_CNTL)/sizeof(mmDP_LINK_FRAMING_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4aac, NULL, 0, 0, 0 },
+	{ "mmDP_HBR2_EYE_PATTERN", REG_MMIO, 0x4aac, &mmDP_HBR2_EYE_PATTERN[0], sizeof(mmDP_HBR2_EYE_PATTERN)/sizeof(mmDP_HBR2_EYE_PATTERN[0]), 0, 0 },
+	{ "mmDP0_DP_VID_MSA_VBID", REG_MMIO, 0x4aad, NULL, 0, 0, 0 },
+	{ "mmDP_VID_MSA_VBID", REG_MMIO, 0x4aad, &mmDP_VID_MSA_VBID[0], sizeof(mmDP_VID_MSA_VBID)/sizeof(mmDP_VID_MSA_VBID[0]), 0, 0 },
+	{ "mmDP0_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4aae, NULL, 0, 0, 0 },
+	{ "mmDP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4aae, &mmDP_VID_INTERRUPT_CNTL[0], sizeof(mmDP_VID_INTERRUPT_CNTL)/sizeof(mmDP_VID_INTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CNTL", REG_MMIO, 0x4aaf, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CNTL", REG_MMIO, 0x4aaf, &mmDP_DPHY_CNTL[0], sizeof(mmDP_DPHY_CNTL)/sizeof(mmDP_DPHY_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4ab0, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4ab0, &mmDP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM0", REG_MMIO, 0x4ab1, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM0", REG_MMIO, 0x4ab1, &mmDP_DPHY_SYM0[0], sizeof(mmDP_DPHY_SYM0)/sizeof(mmDP_DPHY_SYM0[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM1", REG_MMIO, 0x4ab2, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM1", REG_MMIO, 0x4ab2, &mmDP_DPHY_SYM1[0], sizeof(mmDP_DPHY_SYM1)/sizeof(mmDP_DPHY_SYM1[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM2", REG_MMIO, 0x4ab3, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM2", REG_MMIO, 0x4ab3, &mmDP_DPHY_SYM2[0], sizeof(mmDP_DPHY_SYM2)/sizeof(mmDP_DPHY_SYM2[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4ab4, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_8B10B_CNTL", REG_MMIO, 0x4ab4, &mmDP_DPHY_8B10B_CNTL[0], sizeof(mmDP_DPHY_8B10B_CNTL)/sizeof(mmDP_DPHY_8B10B_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4ab5, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_PRBS_CNTL", REG_MMIO, 0x4ab5, &mmDP_DPHY_PRBS_CNTL[0], sizeof(mmDP_DPHY_PRBS_CNTL)/sizeof(mmDP_DPHY_PRBS_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4ab6, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4ab6, &mmDP_DPHY_SCRAM_CNTL[0], sizeof(mmDP_DPHY_SCRAM_CNTL)/sizeof(mmDP_DPHY_SCRAM_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_EN", REG_MMIO, 0x4ab7, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_EN", REG_MMIO, 0x4ab7, &mmDP_DPHY_CRC_EN[0], sizeof(mmDP_DPHY_CRC_EN)/sizeof(mmDP_DPHY_CRC_EN[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4ab8, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_CNTL", REG_MMIO, 0x4ab8, &mmDP_DPHY_CRC_CNTL[0], sizeof(mmDP_DPHY_CRC_CNTL)/sizeof(mmDP_DPHY_CRC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4ab9, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_RESULT", REG_MMIO, 0x4ab9, &mmDP_DPHY_CRC_RESULT[0], sizeof(mmDP_DPHY_CRC_RESULT)/sizeof(mmDP_DPHY_CRC_RESULT[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4aba, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4aba, &mmDP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP_DPHY_CRC_MST_CNTL)/sizeof(mmDP_DPHY_CRC_MST_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4abb, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4abb, &mmDP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP_DPHY_CRC_MST_STATUS)/sizeof(mmDP_DPHY_CRC_MST_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4abc, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_FAST_TRAINING", REG_MMIO, 0x4abc, &mmDP_DPHY_FAST_TRAINING[0], sizeof(mmDP_DPHY_FAST_TRAINING)/sizeof(mmDP_DPHY_FAST_TRAINING[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4abd, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4abd, &mmDP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4abe, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4abe, &mmDP_MSA_V_TIMING_OVERRIDE1[0], sizeof(mmDP_MSA_V_TIMING_OVERRIDE1)/sizeof(mmDP_MSA_V_TIMING_OVERRIDE1[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4abf, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4abf, &mmDP_MSA_V_TIMING_OVERRIDE2[0], sizeof(mmDP_MSA_V_TIMING_OVERRIDE2)/sizeof(mmDP_MSA_V_TIMING_OVERRIDE2[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL", REG_MMIO, 0x4ac3, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_CNTL", REG_MMIO, 0x4ac3, &mmDP_SEC_CNTL[0], sizeof(mmDP_SEC_CNTL)/sizeof(mmDP_SEC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL1", REG_MMIO, 0x4ac4, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_CNTL1", REG_MMIO, 0x4ac4, &mmDP_SEC_CNTL1[0], sizeof(mmDP_SEC_CNTL1)/sizeof(mmDP_SEC_CNTL1[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING1", REG_MMIO, 0x4ac5, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING1", REG_MMIO, 0x4ac5, &mmDP_SEC_FRAMING1[0], sizeof(mmDP_SEC_FRAMING1)/sizeof(mmDP_SEC_FRAMING1[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING2", REG_MMIO, 0x4ac6, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING2", REG_MMIO, 0x4ac6, &mmDP_SEC_FRAMING2[0], sizeof(mmDP_SEC_FRAMING2)/sizeof(mmDP_SEC_FRAMING2[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING3", REG_MMIO, 0x4ac7, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING3", REG_MMIO, 0x4ac7, &mmDP_SEC_FRAMING3[0], sizeof(mmDP_SEC_FRAMING3)/sizeof(mmDP_SEC_FRAMING3[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING4", REG_MMIO, 0x4ac8, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING4", REG_MMIO, 0x4ac8, &mmDP_SEC_FRAMING4[0], sizeof(mmDP_SEC_FRAMING4)/sizeof(mmDP_SEC_FRAMING4[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N", REG_MMIO, 0x4ac9, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_N", REG_MMIO, 0x4ac9, &mmDP_SEC_AUD_N[0], sizeof(mmDP_SEC_AUD_N)/sizeof(mmDP_SEC_AUD_N[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4aca, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_N_READBACK", REG_MMIO, 0x4aca, &mmDP_SEC_AUD_N_READBACK[0], sizeof(mmDP_SEC_AUD_N_READBACK)/sizeof(mmDP_SEC_AUD_N_READBACK[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M", REG_MMIO, 0x4acb, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_M", REG_MMIO, 0x4acb, &mmDP_SEC_AUD_M[0], sizeof(mmDP_SEC_AUD_M)/sizeof(mmDP_SEC_AUD_M[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4acc, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_M_READBACK", REG_MMIO, 0x4acc, &mmDP_SEC_AUD_M_READBACK[0], sizeof(mmDP_SEC_AUD_M_READBACK)/sizeof(mmDP_SEC_AUD_M_READBACK[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_TIMESTAMP", REG_MMIO, 0x4acd, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_TIMESTAMP", REG_MMIO, 0x4acd, &mmDP_SEC_TIMESTAMP[0], sizeof(mmDP_SEC_TIMESTAMP)/sizeof(mmDP_SEC_TIMESTAMP[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4ace, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_PACKET_CNTL", REG_MMIO, 0x4ace, &mmDP_SEC_PACKET_CNTL[0], sizeof(mmDP_SEC_PACKET_CNTL)/sizeof(mmDP_SEC_PACKET_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_CNTL", REG_MMIO, 0x4acf, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_RATE_CNTL", REG_MMIO, 0x4acf, &mmDP_MSE_RATE_CNTL[0], sizeof(mmDP_MSE_RATE_CNTL)/sizeof(mmDP_MSE_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4ad1, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_RATE_UPDATE", REG_MMIO, 0x4ad1, &mmDP_MSE_RATE_UPDATE[0], sizeof(mmDP_MSE_RATE_UPDATE)/sizeof(mmDP_MSE_RATE_UPDATE[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT0", REG_MMIO, 0x4ad2, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT0", REG_MMIO, 0x4ad2, &mmDP_MSE_SAT0[0], sizeof(mmDP_MSE_SAT0)/sizeof(mmDP_MSE_SAT0[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT1", REG_MMIO, 0x4ad3, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT1", REG_MMIO, 0x4ad3, &mmDP_MSE_SAT1[0], sizeof(mmDP_MSE_SAT1)/sizeof(mmDP_MSE_SAT1[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT2", REG_MMIO, 0x4ad4, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT2", REG_MMIO, 0x4ad4, &mmDP_MSE_SAT2[0], sizeof(mmDP_MSE_SAT2)/sizeof(mmDP_MSE_SAT2[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4ad5, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT_UPDATE", REG_MMIO, 0x4ad5, &mmDP_MSE_SAT_UPDATE[0], sizeof(mmDP_MSE_SAT_UPDATE)/sizeof(mmDP_MSE_SAT_UPDATE[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_LINK_TIMING", REG_MMIO, 0x4ad6, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_LINK_TIMING", REG_MMIO, 0x4ad6, &mmDP_MSE_LINK_TIMING[0], sizeof(mmDP_MSE_LINK_TIMING)/sizeof(mmDP_MSE_LINK_TIMING[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_MISC_CNTL", REG_MMIO, 0x4ad7, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_MISC_CNTL", REG_MMIO, 0x4ad7, &mmDP_MSE_MISC_CNTL[0], sizeof(mmDP_MSE_MISC_CNTL)/sizeof(mmDP_MSE_MISC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ad8, NULL, 0, 0, 0 },
+	{ "mmDP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ad8, &mmDP_TEST_DEBUG_INDEX[0], sizeof(mmDP_TEST_DEBUG_INDEX)/sizeof(mmDP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4ad9, NULL, 0, 0, 0 },
+	{ "mmDP_TEST_DEBUG_DATA", REG_MMIO, 0x4ad9, &mmDP_TEST_DEBUG_DATA[0], sizeof(mmDP_TEST_DEBUG_DATA)/sizeof(mmDP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP0_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4ada, NULL, 0, 0, 0 },
+	{ "mmDP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4ada, &mmDP_FE_TEST_DEBUG_INDEX[0], sizeof(mmDP_FE_TEST_DEBUG_INDEX)/sizeof(mmDP_FE_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP0_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4adb, NULL, 0, 0, 0 },
+	{ "mmDP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4adb, &mmDP_FE_TEST_DEBUG_DATA[0], sizeof(mmDP_FE_TEST_DEBUG_DATA)/sizeof(mmDP_FE_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4adc, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4adc, &mmDP_DPHY_BS_SR_SWAP_CNTL[0], sizeof(mmDP_DPHY_BS_SR_SWAP_CNTL)/sizeof(mmDP_DPHY_BS_SR_SWAP_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4add, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4add, &mmDP_DPHY_HBR2_PATTERN_CONTROL[0], sizeof(mmDP_DPHY_HBR2_PATTERN_CONTROL)/sizeof(mmDP_DPHY_HBR2_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT0_STATUS", REG_MMIO, 0x4adf, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT0_STATUS", REG_MMIO, 0x4adf, &mmDP_MSE_SAT0_STATUS[0], sizeof(mmDP_MSE_SAT0_STATUS)/sizeof(mmDP_MSE_SAT0_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT1_STATUS", REG_MMIO, 0x4ae0, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT1_STATUS", REG_MMIO, 0x4ae0, &mmDP_MSE_SAT1_STATUS[0], sizeof(mmDP_MSE_SAT1_STATUS)/sizeof(mmDP_MSE_SAT1_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT2_STATUS", REG_MMIO, 0x4ae1, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT2_STATUS", REG_MMIO, 0x4ae1, &mmDP_MSE_SAT2_STATUS[0], sizeof(mmDP_MSE_SAT2_STATUS)/sizeof(mmDP_MSE_SAT2_STATUS[0]), 0, 0 },
+	{ "mmDIG1_DIG_FE_CNTL", REG_MMIO, 0x4b00, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4b01, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4b02, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_CLOCK_PATTERN", REG_MMIO, 0x4b03, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_PATTERN", REG_MMIO, 0x4b04, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4b05, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FIFO_STATUS", REG_MMIO, 0x4b06, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4b07, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4b08, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_CONTROL", REG_MMIO, 0x4b09, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_STATUS", REG_MMIO, 0x4b0a, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4b0b, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4b0c, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4b0d, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4b0e, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4b0f, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4b10, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4b11, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GC", REG_MMIO, 0x4b13, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4b14, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_0", REG_MMIO, 0x4b15, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_1", REG_MMIO, 0x4b16, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_2", REG_MMIO, 0x4b17, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_3", REG_MMIO, 0x4b18, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_4", REG_MMIO, 0x4b19, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_0", REG_MMIO, 0x4b1a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_1", REG_MMIO, 0x4b1b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_2", REG_MMIO, 0x4b1c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_3", REG_MMIO, 0x4b1d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO0", REG_MMIO, 0x4b1e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO1", REG_MMIO, 0x4b1f, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO2", REG_MMIO, 0x4b20, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO3", REG_MMIO, 0x4b21, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO0", REG_MMIO, 0x4b22, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO1", REG_MMIO, 0x4b23, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_HDR", REG_MMIO, 0x4b24, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_0", REG_MMIO, 0x4b25, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_1", REG_MMIO, 0x4b26, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_2", REG_MMIO, 0x4b27, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_3", REG_MMIO, 0x4b28, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_4", REG_MMIO, 0x4b29, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_5", REG_MMIO, 0x4b2a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_6", REG_MMIO, 0x4b2b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_7", REG_MMIO, 0x4b2c, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4b2d, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_0", REG_MMIO, 0x4b2e, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_1", REG_MMIO, 0x4b2f, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_0", REG_MMIO, 0x4b30, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_1", REG_MMIO, 0x4b31, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_0", REG_MMIO, 0x4b32, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_1", REG_MMIO, 0x4b33, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_0", REG_MMIO, 0x4b34, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_1", REG_MMIO, 0x4b35, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO0", REG_MMIO, 0x4b36, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO1", REG_MMIO, 0x4b37, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_0", REG_MMIO, 0x4b38, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_1", REG_MMIO, 0x4b39, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4b3a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4b3b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4b3c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4b3d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4b3e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_2", REG_MMIO, 0x4b3f, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4b40, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_STATUS", REG_MMIO, 0x4b41, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4b42, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4b43, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4b44, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4b45, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4b46, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_CNTL", REG_MMIO, 0x4b47, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_EN_CNTL", REG_MMIO, 0x4b48, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CNTL", REG_MMIO, 0x4b6b, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL_CHAR", REG_MMIO, 0x4b6c, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4b6d, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4b6e, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4b6f, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4b70, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DEBUG", REG_MMIO, 0x4b71, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL_BITS", REG_MMIO, 0x4b72, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4b73, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4b75, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4b76, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_VERSION", REG_MMIO, 0x4b78, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_LANE_ENABLE", REG_MMIO, 0x4b79, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4b7a, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4b7b, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4b7c, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4b7d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_CNTL", REG_MMIO, 0x4b7e, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_CNTL", REG_MMIO, 0x4ba0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_PIXEL_FORMAT", REG_MMIO, 0x4ba1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ba2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_CONFIG", REG_MMIO, 0x4ba3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ba4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_STEER_FIFO", REG_MMIO, 0x4ba5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_MISC", REG_MMIO, 0x4ba6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_TIMING", REG_MMIO, 0x4ba8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_N", REG_MMIO, 0x4ba9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_M", REG_MMIO, 0x4baa, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4bab, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4bac, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_MSA_VBID", REG_MMIO, 0x4bad, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4bae, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CNTL", REG_MMIO, 0x4baf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4bb0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM0", REG_MMIO, 0x4bb1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM1", REG_MMIO, 0x4bb2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM2", REG_MMIO, 0x4bb3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4bb4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4bb5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4bb6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_EN", REG_MMIO, 0x4bb7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4bb8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4bb9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4bba, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4bbb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4bbc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4bbd, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4bbe, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4bbf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL", REG_MMIO, 0x4bc3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL1", REG_MMIO, 0x4bc4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING1", REG_MMIO, 0x4bc5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING2", REG_MMIO, 0x4bc6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING3", REG_MMIO, 0x4bc7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING4", REG_MMIO, 0x4bc8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N", REG_MMIO, 0x4bc9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4bca, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M", REG_MMIO, 0x4bcb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4bcc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_TIMESTAMP", REG_MMIO, 0x4bcd, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4bce, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_CNTL", REG_MMIO, 0x4bcf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4bd1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT0", REG_MMIO, 0x4bd2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT1", REG_MMIO, 0x4bd3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT2", REG_MMIO, 0x4bd4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4bd5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_LINK_TIMING", REG_MMIO, 0x4bd6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_MISC_CNTL", REG_MMIO, 0x4bd7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4bd8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4bd9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4bda, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4bdb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4bdc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4bdd, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT0_STATUS", REG_MMIO, 0x4bdf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT1_STATUS", REG_MMIO, 0x4be0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT2_STATUS", REG_MMIO, 0x4be1, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_CNTL", REG_MMIO, 0x4c00, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4c01, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4c02, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_CLOCK_PATTERN", REG_MMIO, 0x4c03, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_PATTERN", REG_MMIO, 0x4c04, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4c05, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FIFO_STATUS", REG_MMIO, 0x4c06, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4c07, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4c08, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_CONTROL", REG_MMIO, 0x4c09, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_STATUS", REG_MMIO, 0x4c0a, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4c0b, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4c0c, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4c0d, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4c0e, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4c0f, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4c10, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4c11, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GC", REG_MMIO, 0x4c13, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4c14, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_0", REG_MMIO, 0x4c15, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_1", REG_MMIO, 0x4c16, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_2", REG_MMIO, 0x4c17, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_3", REG_MMIO, 0x4c18, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_4", REG_MMIO, 0x4c19, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_0", REG_MMIO, 0x4c1a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_1", REG_MMIO, 0x4c1b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_2", REG_MMIO, 0x4c1c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_3", REG_MMIO, 0x4c1d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO0", REG_MMIO, 0x4c1e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO1", REG_MMIO, 0x4c1f, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO2", REG_MMIO, 0x4c20, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO3", REG_MMIO, 0x4c21, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO0", REG_MMIO, 0x4c22, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO1", REG_MMIO, 0x4c23, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_HDR", REG_MMIO, 0x4c24, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_0", REG_MMIO, 0x4c25, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_1", REG_MMIO, 0x4c26, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_2", REG_MMIO, 0x4c27, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_3", REG_MMIO, 0x4c28, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_4", REG_MMIO, 0x4c29, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_5", REG_MMIO, 0x4c2a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_6", REG_MMIO, 0x4c2b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_7", REG_MMIO, 0x4c2c, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4c2d, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_0", REG_MMIO, 0x4c2e, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_1", REG_MMIO, 0x4c2f, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_0", REG_MMIO, 0x4c30, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_1", REG_MMIO, 0x4c31, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_0", REG_MMIO, 0x4c32, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_1", REG_MMIO, 0x4c33, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_0", REG_MMIO, 0x4c34, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_1", REG_MMIO, 0x4c35, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO0", REG_MMIO, 0x4c36, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO1", REG_MMIO, 0x4c37, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_0", REG_MMIO, 0x4c38, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_1", REG_MMIO, 0x4c39, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4c3a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4c3b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4c3c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4c3d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4c3e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_2", REG_MMIO, 0x4c3f, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4c40, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_STATUS", REG_MMIO, 0x4c41, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4c42, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4c43, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4c44, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4c45, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4c46, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_CNTL", REG_MMIO, 0x4c47, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_EN_CNTL", REG_MMIO, 0x4c48, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CNTL", REG_MMIO, 0x4c6b, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL_CHAR", REG_MMIO, 0x4c6c, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4c6d, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4c6e, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4c6f, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4c70, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DEBUG", REG_MMIO, 0x4c71, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL_BITS", REG_MMIO, 0x4c72, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4c73, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4c75, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4c76, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_VERSION", REG_MMIO, 0x4c78, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_LANE_ENABLE", REG_MMIO, 0x4c79, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4c7a, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4c7b, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4c7c, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4c7d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_CNTL", REG_MMIO, 0x4c7e, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_CNTL", REG_MMIO, 0x4ca0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_PIXEL_FORMAT", REG_MMIO, 0x4ca1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ca2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_CONFIG", REG_MMIO, 0x4ca3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ca4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_STEER_FIFO", REG_MMIO, 0x4ca5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_MISC", REG_MMIO, 0x4ca6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_TIMING", REG_MMIO, 0x4ca8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_N", REG_MMIO, 0x4ca9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_M", REG_MMIO, 0x4caa, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4cab, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4cac, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_MSA_VBID", REG_MMIO, 0x4cad, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4cae, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CNTL", REG_MMIO, 0x4caf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4cb0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM0", REG_MMIO, 0x4cb1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM1", REG_MMIO, 0x4cb2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM2", REG_MMIO, 0x4cb3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4cb4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4cb5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4cb6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_EN", REG_MMIO, 0x4cb7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4cb8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4cb9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4cba, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4cbb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4cbc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4cbd, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4cbe, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4cbf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL", REG_MMIO, 0x4cc3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL1", REG_MMIO, 0x4cc4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING1", REG_MMIO, 0x4cc5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING2", REG_MMIO, 0x4cc6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING3", REG_MMIO, 0x4cc7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING4", REG_MMIO, 0x4cc8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N", REG_MMIO, 0x4cc9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4cca, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M", REG_MMIO, 0x4ccb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4ccc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_TIMESTAMP", REG_MMIO, 0x4ccd, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4cce, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_CNTL", REG_MMIO, 0x4ccf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4cd1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT0", REG_MMIO, 0x4cd2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT1", REG_MMIO, 0x4cd3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT2", REG_MMIO, 0x4cd4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4cd5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_LINK_TIMING", REG_MMIO, 0x4cd6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_MISC_CNTL", REG_MMIO, 0x4cd7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4cd8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4cd9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4cda, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4cdb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4cdc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4cdd, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT0_STATUS", REG_MMIO, 0x4cdf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT1_STATUS", REG_MMIO, 0x4ce0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT2_STATUS", REG_MMIO, 0x4ce1, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_CNTL", REG_MMIO, 0x4d00, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4d01, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4d02, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_CLOCK_PATTERN", REG_MMIO, 0x4d03, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_PATTERN", REG_MMIO, 0x4d04, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4d05, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FIFO_STATUS", REG_MMIO, 0x4d06, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4d07, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4d08, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_CONTROL", REG_MMIO, 0x4d09, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_STATUS", REG_MMIO, 0x4d0a, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4d0b, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4d0c, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4d0d, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4d0e, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4d0f, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4d10, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4d11, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GC", REG_MMIO, 0x4d13, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4d14, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_0", REG_MMIO, 0x4d15, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_1", REG_MMIO, 0x4d16, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_2", REG_MMIO, 0x4d17, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_3", REG_MMIO, 0x4d18, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_4", REG_MMIO, 0x4d19, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_0", REG_MMIO, 0x4d1a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_1", REG_MMIO, 0x4d1b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_2", REG_MMIO, 0x4d1c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_3", REG_MMIO, 0x4d1d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO0", REG_MMIO, 0x4d1e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO1", REG_MMIO, 0x4d1f, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO2", REG_MMIO, 0x4d20, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO3", REG_MMIO, 0x4d21, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO0", REG_MMIO, 0x4d22, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO1", REG_MMIO, 0x4d23, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_HDR", REG_MMIO, 0x4d24, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_0", REG_MMIO, 0x4d25, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_1", REG_MMIO, 0x4d26, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_2", REG_MMIO, 0x4d27, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_3", REG_MMIO, 0x4d28, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_4", REG_MMIO, 0x4d29, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_5", REG_MMIO, 0x4d2a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_6", REG_MMIO, 0x4d2b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_7", REG_MMIO, 0x4d2c, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4d2d, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_0", REG_MMIO, 0x4d2e, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_1", REG_MMIO, 0x4d2f, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_0", REG_MMIO, 0x4d30, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_1", REG_MMIO, 0x4d31, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_0", REG_MMIO, 0x4d32, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_1", REG_MMIO, 0x4d33, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_0", REG_MMIO, 0x4d34, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_1", REG_MMIO, 0x4d35, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO0", REG_MMIO, 0x4d36, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO1", REG_MMIO, 0x4d37, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_0", REG_MMIO, 0x4d38, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_1", REG_MMIO, 0x4d39, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4d3a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4d3b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4d3c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4d3d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4d3e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_2", REG_MMIO, 0x4d3f, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4d40, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_STATUS", REG_MMIO, 0x4d41, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4d42, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4d43, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4d44, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4d45, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4d46, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_CNTL", REG_MMIO, 0x4d47, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_EN_CNTL", REG_MMIO, 0x4d48, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CNTL", REG_MMIO, 0x4d6b, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL_CHAR", REG_MMIO, 0x4d6c, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4d6d, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4d6e, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4d6f, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4d70, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DEBUG", REG_MMIO, 0x4d71, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL_BITS", REG_MMIO, 0x4d72, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4d73, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4d75, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4d76, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_VERSION", REG_MMIO, 0x4d78, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_LANE_ENABLE", REG_MMIO, 0x4d79, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4d7a, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4d7b, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4d7c, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4d7d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_CNTL", REG_MMIO, 0x4d7e, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_CNTL", REG_MMIO, 0x4da0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_PIXEL_FORMAT", REG_MMIO, 0x4da1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_COLORIMETRY", REG_MMIO, 0x4da2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_CONFIG", REG_MMIO, 0x4da3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_STREAM_CNTL", REG_MMIO, 0x4da4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_STEER_FIFO", REG_MMIO, 0x4da5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_MISC", REG_MMIO, 0x4da6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_TIMING", REG_MMIO, 0x4da8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_N", REG_MMIO, 0x4da9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_M", REG_MMIO, 0x4daa, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4dab, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4dac, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_MSA_VBID", REG_MMIO, 0x4dad, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4dae, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CNTL", REG_MMIO, 0x4daf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4db0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM0", REG_MMIO, 0x4db1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM1", REG_MMIO, 0x4db2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM2", REG_MMIO, 0x4db3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4db4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4db5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4db6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_EN", REG_MMIO, 0x4db7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4db8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4db9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4dba, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4dbb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4dbc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4dbd, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4dbe, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4dbf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL", REG_MMIO, 0x4dc3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL1", REG_MMIO, 0x4dc4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING1", REG_MMIO, 0x4dc5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING2", REG_MMIO, 0x4dc6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING3", REG_MMIO, 0x4dc7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING4", REG_MMIO, 0x4dc8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N", REG_MMIO, 0x4dc9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4dca, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M", REG_MMIO, 0x4dcb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4dcc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_TIMESTAMP", REG_MMIO, 0x4dcd, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4dce, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_CNTL", REG_MMIO, 0x4dcf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4dd1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT0", REG_MMIO, 0x4dd2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT1", REG_MMIO, 0x4dd3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT2", REG_MMIO, 0x4dd4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4dd5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_LINK_TIMING", REG_MMIO, 0x4dd6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_MISC_CNTL", REG_MMIO, 0x4dd7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4dd8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4dd9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4dda, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4ddb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4ddc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4ddd, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT0_STATUS", REG_MMIO, 0x4ddf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT1_STATUS", REG_MMIO, 0x4de0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT2_STATUS", REG_MMIO, 0x4de1, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_CNTL", REG_MMIO, 0x4e00, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4e01, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4e02, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_CLOCK_PATTERN", REG_MMIO, 0x4e03, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_PATTERN", REG_MMIO, 0x4e04, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4e05, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FIFO_STATUS", REG_MMIO, 0x4e06, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4e07, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4e08, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_CONTROL", REG_MMIO, 0x4e09, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_STATUS", REG_MMIO, 0x4e0a, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4e0b, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4e0c, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4e0d, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4e0e, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4e0f, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4e10, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4e11, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GC", REG_MMIO, 0x4e13, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4e14, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_0", REG_MMIO, 0x4e15, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_1", REG_MMIO, 0x4e16, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_2", REG_MMIO, 0x4e17, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_3", REG_MMIO, 0x4e18, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_4", REG_MMIO, 0x4e19, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_0", REG_MMIO, 0x4e1a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_1", REG_MMIO, 0x4e1b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_2", REG_MMIO, 0x4e1c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_3", REG_MMIO, 0x4e1d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO0", REG_MMIO, 0x4e1e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO1", REG_MMIO, 0x4e1f, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO2", REG_MMIO, 0x4e20, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO3", REG_MMIO, 0x4e21, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO0", REG_MMIO, 0x4e22, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO1", REG_MMIO, 0x4e23, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_HDR", REG_MMIO, 0x4e24, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_0", REG_MMIO, 0x4e25, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_1", REG_MMIO, 0x4e26, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_2", REG_MMIO, 0x4e27, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_3", REG_MMIO, 0x4e28, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_4", REG_MMIO, 0x4e29, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_5", REG_MMIO, 0x4e2a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_6", REG_MMIO, 0x4e2b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_7", REG_MMIO, 0x4e2c, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4e2d, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_0", REG_MMIO, 0x4e2e, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_1", REG_MMIO, 0x4e2f, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_0", REG_MMIO, 0x4e30, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_1", REG_MMIO, 0x4e31, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_0", REG_MMIO, 0x4e32, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_1", REG_MMIO, 0x4e33, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_0", REG_MMIO, 0x4e34, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_1", REG_MMIO, 0x4e35, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO0", REG_MMIO, 0x4e36, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO1", REG_MMIO, 0x4e37, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_0", REG_MMIO, 0x4e38, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_1", REG_MMIO, 0x4e39, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4e3a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4e3b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4e3c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4e3d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4e3e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_2", REG_MMIO, 0x4e3f, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4e40, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_STATUS", REG_MMIO, 0x4e41, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4e42, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4e43, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4e44, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4e45, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4e46, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_CNTL", REG_MMIO, 0x4e47, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_EN_CNTL", REG_MMIO, 0x4e48, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CNTL", REG_MMIO, 0x4e6b, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL_CHAR", REG_MMIO, 0x4e6c, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4e6d, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4e6e, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4e6f, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4e70, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DEBUG", REG_MMIO, 0x4e71, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL_BITS", REG_MMIO, 0x4e72, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4e73, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4e75, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4e76, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_VERSION", REG_MMIO, 0x4e78, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_LANE_ENABLE", REG_MMIO, 0x4e79, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4e7a, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4e7b, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4e7c, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4e7d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_CNTL", REG_MMIO, 0x4e7e, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_CNTL", REG_MMIO, 0x4ea0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_PIXEL_FORMAT", REG_MMIO, 0x4ea1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_COLORIMETRY", REG_MMIO, 0x4ea2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_CONFIG", REG_MMIO, 0x4ea3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ea4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_STEER_FIFO", REG_MMIO, 0x4ea5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_MISC", REG_MMIO, 0x4ea6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_TIMING", REG_MMIO, 0x4ea8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_N", REG_MMIO, 0x4ea9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_M", REG_MMIO, 0x4eaa, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4eab, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4eac, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_MSA_VBID", REG_MMIO, 0x4ead, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4eae, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CNTL", REG_MMIO, 0x4eaf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4eb0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM0", REG_MMIO, 0x4eb1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM1", REG_MMIO, 0x4eb2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM2", REG_MMIO, 0x4eb3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4eb4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4eb5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4eb6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_EN", REG_MMIO, 0x4eb7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4eb8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4eb9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4eba, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4ebb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4ebc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4ebd, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4ebe, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4ebf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL", REG_MMIO, 0x4ec3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL1", REG_MMIO, 0x4ec4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING1", REG_MMIO, 0x4ec5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING2", REG_MMIO, 0x4ec6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING3", REG_MMIO, 0x4ec7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING4", REG_MMIO, 0x4ec8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N", REG_MMIO, 0x4ec9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4eca, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M", REG_MMIO, 0x4ecb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4ecc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_TIMESTAMP", REG_MMIO, 0x4ecd, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4ece, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_CNTL", REG_MMIO, 0x4ecf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4ed1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT0", REG_MMIO, 0x4ed2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT1", REG_MMIO, 0x4ed3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT2", REG_MMIO, 0x4ed4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4ed5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_LINK_TIMING", REG_MMIO, 0x4ed6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_MISC_CNTL", REG_MMIO, 0x4ed7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4ed8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4ed9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4eda, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4edb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4edc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4edd, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT0_STATUS", REG_MMIO, 0x4edf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT1_STATUS", REG_MMIO, 0x4ee0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT2_STATUS", REG_MMIO, 0x4ee1, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_CNTL", REG_MMIO, 0x4f00, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4f01, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4f02, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_CLOCK_PATTERN", REG_MMIO, 0x4f03, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_PATTERN", REG_MMIO, 0x4f04, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4f05, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FIFO_STATUS", REG_MMIO, 0x4f06, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4f07, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4f08, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_CONTROL", REG_MMIO, 0x4f09, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_STATUS", REG_MMIO, 0x4f0a, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4f0b, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4f0c, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4f0d, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4f0e, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4f0f, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4f10, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4f11, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GC", REG_MMIO, 0x4f13, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4f14, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_0", REG_MMIO, 0x4f15, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_1", REG_MMIO, 0x4f16, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_2", REG_MMIO, 0x4f17, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_3", REG_MMIO, 0x4f18, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_4", REG_MMIO, 0x4f19, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_0", REG_MMIO, 0x4f1a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_1", REG_MMIO, 0x4f1b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_2", REG_MMIO, 0x4f1c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_3", REG_MMIO, 0x4f1d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO0", REG_MMIO, 0x4f1e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO1", REG_MMIO, 0x4f1f, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO2", REG_MMIO, 0x4f20, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO3", REG_MMIO, 0x4f21, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO0", REG_MMIO, 0x4f22, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO1", REG_MMIO, 0x4f23, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_HDR", REG_MMIO, 0x4f24, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_0", REG_MMIO, 0x4f25, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_1", REG_MMIO, 0x4f26, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_2", REG_MMIO, 0x4f27, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_3", REG_MMIO, 0x4f28, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_4", REG_MMIO, 0x4f29, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_5", REG_MMIO, 0x4f2a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_6", REG_MMIO, 0x4f2b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_7", REG_MMIO, 0x4f2c, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4f2d, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_0", REG_MMIO, 0x4f2e, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_1", REG_MMIO, 0x4f2f, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_0", REG_MMIO, 0x4f30, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_1", REG_MMIO, 0x4f31, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_0", REG_MMIO, 0x4f32, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_1", REG_MMIO, 0x4f33, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_0", REG_MMIO, 0x4f34, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_1", REG_MMIO, 0x4f35, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO0", REG_MMIO, 0x4f36, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO1", REG_MMIO, 0x4f37, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_0", REG_MMIO, 0x4f38, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_1", REG_MMIO, 0x4f39, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4f3a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4f3b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4f3c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4f3d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4f3e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_2", REG_MMIO, 0x4f3f, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4f40, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_STATUS", REG_MMIO, 0x4f41, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4f42, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4f43, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4f44, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4f45, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4f46, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_CNTL", REG_MMIO, 0x4f47, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_EN_CNTL", REG_MMIO, 0x4f48, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CNTL", REG_MMIO, 0x4f6b, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL_CHAR", REG_MMIO, 0x4f6c, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4f6d, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4f6e, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4f6f, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4f70, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DEBUG", REG_MMIO, 0x4f71, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL_BITS", REG_MMIO, 0x4f72, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4f73, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4f75, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4f76, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_VERSION", REG_MMIO, 0x4f78, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_LANE_ENABLE", REG_MMIO, 0x4f79, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x4f7a, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x4f7b, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4f7c, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4f7d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_CNTL", REG_MMIO, 0x4f7e, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_CNTL", REG_MMIO, 0x4fa0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_PIXEL_FORMAT", REG_MMIO, 0x4fa1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_COLORIMETRY", REG_MMIO, 0x4fa2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_CONFIG", REG_MMIO, 0x4fa3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_STREAM_CNTL", REG_MMIO, 0x4fa4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_STEER_FIFO", REG_MMIO, 0x4fa5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_MISC", REG_MMIO, 0x4fa6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_TIMING", REG_MMIO, 0x4fa8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_N", REG_MMIO, 0x4fa9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_M", REG_MMIO, 0x4faa, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4fab, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4fac, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_MSA_VBID", REG_MMIO, 0x4fad, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4fae, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CNTL", REG_MMIO, 0x4faf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4fb0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM0", REG_MMIO, 0x4fb1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM1", REG_MMIO, 0x4fb2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM2", REG_MMIO, 0x4fb3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4fb4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4fb5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4fb6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_EN", REG_MMIO, 0x4fb7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4fb8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4fb9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4fba, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4fbb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4fbc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4fbd, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4fbe, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4fbf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL", REG_MMIO, 0x4fc3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL1", REG_MMIO, 0x4fc4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING1", REG_MMIO, 0x4fc5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING2", REG_MMIO, 0x4fc6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING3", REG_MMIO, 0x4fc7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING4", REG_MMIO, 0x4fc8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N", REG_MMIO, 0x4fc9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4fca, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M", REG_MMIO, 0x4fcb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4fcc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_TIMESTAMP", REG_MMIO, 0x4fcd, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4fce, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_CNTL", REG_MMIO, 0x4fcf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4fd1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT0", REG_MMIO, 0x4fd2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT1", REG_MMIO, 0x4fd3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT2", REG_MMIO, 0x4fd4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4fd5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_LINK_TIMING", REG_MMIO, 0x4fd6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_MISC_CNTL", REG_MMIO, 0x4fd7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4fd8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4fd9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x4fda, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x4fdb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x4fdc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x4fdd, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT0_STATUS", REG_MMIO, 0x4fdf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT1_STATUS", REG_MMIO, 0x4fe0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT2_STATUS", REG_MMIO, 0x4fe1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x5, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x5, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL5", REG_SMC, 0x5, &ixAZALIA_INPUT_CRC0_CHANNEL5[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL5)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL5[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL5", REG_SMC, 0x5, &ixAZALIA_CRC0_CHANNEL5[0], sizeof(ixAZALIA_CRC0_CHANNEL5)/sizeof(ixAZALIA_CRC0_CHANNEL5[0]), 0, 0 },
+	{ "ixAZALIA_STREAM_DEBUG", REG_SMC, 0x5, &ixAZALIA_STREAM_DEBUG[0], sizeof(ixAZALIA_STREAM_DEBUG)/sizeof(ixAZALIA_STREAM_DEBUG[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR4", REG_SMC, 0x5, &ixAUDIO_DESCRIPTOR4[0], sizeof(ixAUDIO_DESCRIPTOR4)/sizeof(ixAUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "ixDCIO_DEBUG5", REG_SMC, 0x5, &ixDCIO_DEBUG5[0], sizeof(ixDCIO_DEBUG5)/sizeof(ixDCIO_DEBUG5[0]), 0, 0 },
+	{ "ixATTR05", REG_SMC, 0x5, &ixATTR05[0], sizeof(ixATTR05)/sizeof(ixATTR05[0]), 0, 0 },
+	{ "ixCRT05", REG_SMC, 0x5, &ixCRT05[0], sizeof(ixCRT05)/sizeof(ixCRT05[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x53, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x54, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x54, &ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 },
+	{ "mmDIG6_DIG_FE_CNTL", REG_MMIO, 0x5400, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x5401, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x5402, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_CLOCK_PATTERN", REG_MMIO, 0x5403, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_PATTERN", REG_MMIO, 0x5404, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x5405, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FIFO_STATUS", REG_MMIO, 0x5406, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x5407, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x5408, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_CONTROL", REG_MMIO, 0x5409, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_STATUS", REG_MMIO, 0x540a, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x540b, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x540c, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x540d, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x540e, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x540f, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x5410, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x5411, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GC", REG_MMIO, 0x5413, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x5414, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_0", REG_MMIO, 0x5415, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_1", REG_MMIO, 0x5416, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_2", REG_MMIO, 0x5417, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_3", REG_MMIO, 0x5418, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_4", REG_MMIO, 0x5419, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_0", REG_MMIO, 0x541a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_1", REG_MMIO, 0x541b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_2", REG_MMIO, 0x541c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_3", REG_MMIO, 0x541d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO0", REG_MMIO, 0x541e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO1", REG_MMIO, 0x541f, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO2", REG_MMIO, 0x5420, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO3", REG_MMIO, 0x5421, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_MPEG_INFO0", REG_MMIO, 0x5422, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_MPEG_INFO1", REG_MMIO, 0x5423, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_HDR", REG_MMIO, 0x5424, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_0", REG_MMIO, 0x5425, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_1", REG_MMIO, 0x5426, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_2", REG_MMIO, 0x5427, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_3", REG_MMIO, 0x5428, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_4", REG_MMIO, 0x5429, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_5", REG_MMIO, 0x542a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_6", REG_MMIO, 0x542b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_7", REG_MMIO, 0x542c, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x542d, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_32_0", REG_MMIO, 0x542e, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_32_1", REG_MMIO, 0x542f, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_44_0", REG_MMIO, 0x5430, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_44_1", REG_MMIO, 0x5431, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_48_0", REG_MMIO, 0x5432, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_48_1", REG_MMIO, 0x5433, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_STATUS_0", REG_MMIO, 0x5434, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_STATUS_1", REG_MMIO, 0x5435, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_INFO0", REG_MMIO, 0x5436, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_INFO1", REG_MMIO, 0x5437, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_0", REG_MMIO, 0x5438, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_1", REG_MMIO, 0x5439, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x543a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL0", REG_MMIO, 0x543b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL1", REG_MMIO, 0x543c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL2", REG_MMIO, 0x543d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL3", REG_MMIO, 0x543e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_2", REG_MMIO, 0x543f, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x5440, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_STATUS", REG_MMIO, 0x5441, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x5442, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x5443, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x5444, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x5445, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x5446, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_BE_CNTL", REG_MMIO, 0x5447, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_BE_EN_CNTL", REG_MMIO, 0x5448, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CNTL", REG_MMIO, 0x546b, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CONTROL_CHAR", REG_MMIO, 0x546c, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x546d, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x546e, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x546f, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x5470, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_DEBUG", REG_MMIO, 0x5471, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL_BITS", REG_MMIO, 0x5472, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x5473, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x5475, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x5476, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_VERSION", REG_MMIO, 0x5478, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_LANE_ENABLE", REG_MMIO, 0x5479, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x547a, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x547b, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x547c, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x547d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_CNTL", REG_MMIO, 0x547e, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_LINK_CNTL", REG_MMIO, 0x54a0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_PIXEL_FORMAT", REG_MMIO, 0x54a1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_COLORIMETRY", REG_MMIO, 0x54a2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_CONFIG", REG_MMIO, 0x54a3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_STREAM_CNTL", REG_MMIO, 0x54a4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_STEER_FIFO", REG_MMIO, 0x54a5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_MISC", REG_MMIO, 0x54a6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_TIMING", REG_MMIO, 0x54a8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_N", REG_MMIO, 0x54a9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_M", REG_MMIO, 0x54aa, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x54ab, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x54ac, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_MSA_VBID", REG_MMIO, 0x54ad, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x54ae, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CNTL", REG_MMIO, 0x54af, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x54b0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM0", REG_MMIO, 0x54b1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM1", REG_MMIO, 0x54b2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM2", REG_MMIO, 0x54b3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x54b4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x54b5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x54b6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_EN", REG_MMIO, 0x54b7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_CNTL", REG_MMIO, 0x54b8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_RESULT", REG_MMIO, 0x54b9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x54ba, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x54bb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x54bc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x54bd, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x54be, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x54bf, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_CNTL", REG_MMIO, 0x54c3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_CNTL1", REG_MMIO, 0x54c4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING1", REG_MMIO, 0x54c5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING2", REG_MMIO, 0x54c6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING3", REG_MMIO, 0x54c7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING4", REG_MMIO, 0x54c8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_N", REG_MMIO, 0x54c9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x54ca, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_M", REG_MMIO, 0x54cb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x54cc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_TIMESTAMP", REG_MMIO, 0x54cd, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_PACKET_CNTL", REG_MMIO, 0x54ce, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_RATE_CNTL", REG_MMIO, 0x54cf, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_RATE_UPDATE", REG_MMIO, 0x54d1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT0", REG_MMIO, 0x54d2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT1", REG_MMIO, 0x54d3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT2", REG_MMIO, 0x54d4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT_UPDATE", REG_MMIO, 0x54d5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_LINK_TIMING", REG_MMIO, 0x54d6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_MISC_CNTL", REG_MMIO, 0x54d7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x54d8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_TEST_DEBUG_DATA", REG_MMIO, 0x54d9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x54da, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x54db, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x54dc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x54dd, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT0_STATUS", REG_MMIO, 0x54df, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT1_STATUS", REG_MMIO, 0x54e0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT2_STATUS", REG_MMIO, 0x54e1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x55, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x55, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x56, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x56, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "mmDIG7_DIG_FE_CNTL", REG_MMIO, 0x5600, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x5601, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x5602, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_CLOCK_PATTERN", REG_MMIO, 0x5603, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_TEST_PATTERN", REG_MMIO, 0x5604, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x5605, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_FIFO_STATUS", REG_MMIO, 0x5606, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x5607, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x5608, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_CONTROL", REG_MMIO, 0x5609, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_STATUS", REG_MMIO, 0x560a, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x560b, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x560c, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x560d, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x560e, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x560f, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x5610, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x5611, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_GC", REG_MMIO, 0x5613, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x5614, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_0", REG_MMIO, 0x5615, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_1", REG_MMIO, 0x5616, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_2", REG_MMIO, 0x5617, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_3", REG_MMIO, 0x5618, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC1_4", REG_MMIO, 0x5619, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC2_0", REG_MMIO, 0x561a, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC2_1", REG_MMIO, 0x561b, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC2_2", REG_MMIO, 0x561c, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_ISRC2_3", REG_MMIO, 0x561d, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AVI_INFO0", REG_MMIO, 0x561e, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AVI_INFO1", REG_MMIO, 0x561f, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AVI_INFO2", REG_MMIO, 0x5620, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AVI_INFO3", REG_MMIO, 0x5621, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_MPEG_INFO0", REG_MMIO, 0x5622, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_MPEG_INFO1", REG_MMIO, 0x5623, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_HDR", REG_MMIO, 0x5624, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_0", REG_MMIO, 0x5625, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_1", REG_MMIO, 0x5626, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_2", REG_MMIO, 0x5627, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_3", REG_MMIO, 0x5628, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_4", REG_MMIO, 0x5629, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_5", REG_MMIO, 0x562a, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_6", REG_MMIO, 0x562b, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_GENERIC_7", REG_MMIO, 0x562c, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x562d, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_32_0", REG_MMIO, 0x562e, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_32_1", REG_MMIO, 0x562f, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_44_0", REG_MMIO, 0x5630, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_44_1", REG_MMIO, 0x5631, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_48_0", REG_MMIO, 0x5632, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_48_1", REG_MMIO, 0x5633, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_STATUS_0", REG_MMIO, 0x5634, NULL, 0, 0, 0 },
+	{ "mmDIG7_HDMI_ACR_STATUS_1", REG_MMIO, 0x5635, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_INFO0", REG_MMIO, 0x5636, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_INFO1", REG_MMIO, 0x5637, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_60958_0", REG_MMIO, 0x5638, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_60958_1", REG_MMIO, 0x5639, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x563a, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_RAMP_CONTROL0", REG_MMIO, 0x563b, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_RAMP_CONTROL1", REG_MMIO, 0x563c, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_RAMP_CONTROL2", REG_MMIO, 0x563d, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_RAMP_CONTROL3", REG_MMIO, 0x563e, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_60958_2", REG_MMIO, 0x563f, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x5640, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_STATUS", REG_MMIO, 0x5641, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x5642, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x5643, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x5644, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x5645, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x5646, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_BE_CNTL", REG_MMIO, 0x5647, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_BE_EN_CNTL", REG_MMIO, 0x5648, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CNTL", REG_MMIO, 0x566b, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CONTROL_CHAR", REG_MMIO, 0x566c, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x566d, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x566e, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x566f, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x5670, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_DEBUG", REG_MMIO, 0x5671, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CTL_BITS", REG_MMIO, 0x5672, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x5673, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x5675, NULL, 0, 0, 0 },
+	{ "mmDIG7_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x5676, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_VERSION", REG_MMIO, 0x5678, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_LANE_ENABLE", REG_MMIO, 0x5679, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x567a, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x567b, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x567c, NULL, 0, 0, 0 },
+	{ "mmDIG7_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x567d, NULL, 0, 0, 0 },
+	{ "mmDIG7_AFMT_CNTL", REG_MMIO, 0x567e, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_LINK_CNTL", REG_MMIO, 0x56a0, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_PIXEL_FORMAT", REG_MMIO, 0x56a1, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSA_COLORIMETRY", REG_MMIO, 0x56a2, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_CONFIG", REG_MMIO, 0x56a3, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_STREAM_CNTL", REG_MMIO, 0x56a4, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_STEER_FIFO", REG_MMIO, 0x56a5, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSA_MISC", REG_MMIO, 0x56a6, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_TIMING", REG_MMIO, 0x56a8, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_N", REG_MMIO, 0x56a9, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_M", REG_MMIO, 0x56aa, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x56ab, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x56ac, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_MSA_VBID", REG_MMIO, 0x56ad, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x56ae, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CNTL", REG_MMIO, 0x56af, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x56b0, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_SYM0", REG_MMIO, 0x56b1, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_SYM1", REG_MMIO, 0x56b2, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_SYM2", REG_MMIO, 0x56b3, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x56b4, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x56b5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x56b6, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_EN", REG_MMIO, 0x56b7, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_CNTL", REG_MMIO, 0x56b8, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_RESULT", REG_MMIO, 0x56b9, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x56ba, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x56bb, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x56bc, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x56bd, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x56be, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x56bf, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_CNTL", REG_MMIO, 0x56c3, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_CNTL1", REG_MMIO, 0x56c4, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_FRAMING1", REG_MMIO, 0x56c5, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_FRAMING2", REG_MMIO, 0x56c6, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_FRAMING3", REG_MMIO, 0x56c7, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_FRAMING4", REG_MMIO, 0x56c8, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_AUD_N", REG_MMIO, 0x56c9, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x56ca, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_AUD_M", REG_MMIO, 0x56cb, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x56cc, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_TIMESTAMP", REG_MMIO, 0x56cd, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_SEC_PACKET_CNTL", REG_MMIO, 0x56ce, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_RATE_CNTL", REG_MMIO, 0x56cf, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_RATE_UPDATE", REG_MMIO, 0x56d1, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT0", REG_MMIO, 0x56d2, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT1", REG_MMIO, 0x56d3, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT2", REG_MMIO, 0x56d4, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT_UPDATE", REG_MMIO, 0x56d5, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_LINK_TIMING", REG_MMIO, 0x56d6, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_MISC_CNTL", REG_MMIO, 0x56d7, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x56d8, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_TEST_DEBUG_DATA", REG_MMIO, 0x56d9, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x56da, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x56db, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x56dc, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x56dd, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT0_STATUS", REG_MMIO, 0x56df, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT1_STATUS", REG_MMIO, 0x56e0, NULL, 0, 0, 0 },
+	{ "mmDP7_DP_MSE_SAT2_STATUS", REG_MMIO, 0x56e1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x57, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 },
+	{ "mmDIG8_DIG_FE_CNTL", REG_MMIO, 0x5700, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x5701, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x5702, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_CLOCK_PATTERN", REG_MMIO, 0x5703, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_TEST_PATTERN", REG_MMIO, 0x5704, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x5705, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_FIFO_STATUS", REG_MMIO, 0x5706, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x5707, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x5708, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_CONTROL", REG_MMIO, 0x5709, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_STATUS", REG_MMIO, 0x570a, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x570b, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x570c, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x570d, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x570e, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x570f, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x5710, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x5711, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_GC", REG_MMIO, 0x5713, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x5714, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_0", REG_MMIO, 0x5715, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_1", REG_MMIO, 0x5716, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_2", REG_MMIO, 0x5717, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_3", REG_MMIO, 0x5718, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC1_4", REG_MMIO, 0x5719, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC2_0", REG_MMIO, 0x571a, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC2_1", REG_MMIO, 0x571b, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC2_2", REG_MMIO, 0x571c, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_ISRC2_3", REG_MMIO, 0x571d, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AVI_INFO0", REG_MMIO, 0x571e, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AVI_INFO1", REG_MMIO, 0x571f, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AVI_INFO2", REG_MMIO, 0x5720, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AVI_INFO3", REG_MMIO, 0x5721, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_MPEG_INFO0", REG_MMIO, 0x5722, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_MPEG_INFO1", REG_MMIO, 0x5723, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_HDR", REG_MMIO, 0x5724, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_0", REG_MMIO, 0x5725, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_1", REG_MMIO, 0x5726, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_2", REG_MMIO, 0x5727, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_3", REG_MMIO, 0x5728, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_4", REG_MMIO, 0x5729, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_5", REG_MMIO, 0x572a, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_6", REG_MMIO, 0x572b, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_GENERIC_7", REG_MMIO, 0x572c, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x572d, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_32_0", REG_MMIO, 0x572e, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_32_1", REG_MMIO, 0x572f, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_44_0", REG_MMIO, 0x5730, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_44_1", REG_MMIO, 0x5731, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_48_0", REG_MMIO, 0x5732, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_48_1", REG_MMIO, 0x5733, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_STATUS_0", REG_MMIO, 0x5734, NULL, 0, 0, 0 },
+	{ "mmDIG8_HDMI_ACR_STATUS_1", REG_MMIO, 0x5735, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_INFO0", REG_MMIO, 0x5736, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_INFO1", REG_MMIO, 0x5737, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_60958_0", REG_MMIO, 0x5738, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_60958_1", REG_MMIO, 0x5739, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x573a, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_RAMP_CONTROL0", REG_MMIO, 0x573b, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_RAMP_CONTROL1", REG_MMIO, 0x573c, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_RAMP_CONTROL2", REG_MMIO, 0x573d, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_RAMP_CONTROL3", REG_MMIO, 0x573e, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_60958_2", REG_MMIO, 0x573f, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x5740, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_STATUS", REG_MMIO, 0x5741, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x5742, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x5743, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x5744, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x5745, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x5746, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_BE_CNTL", REG_MMIO, 0x5747, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_BE_EN_CNTL", REG_MMIO, 0x5748, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CNTL", REG_MMIO, 0x576b, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CONTROL_CHAR", REG_MMIO, 0x576c, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x576d, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x576e, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x576f, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x5770, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_DEBUG", REG_MMIO, 0x5771, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CTL_BITS", REG_MMIO, 0x5772, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x5773, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x5775, NULL, 0, 0, 0 },
+	{ "mmDIG8_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x5776, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_VERSION", REG_MMIO, 0x5778, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_LANE_ENABLE", REG_MMIO, 0x5779, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_TEST_DEBUG_INDEX", REG_MMIO, 0x577a, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_TEST_DEBUG_DATA", REG_MMIO, 0x577b, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x577c, NULL, 0, 0, 0 },
+	{ "mmDIG8_DIG_FE_TEST_DEBUG_DATA", REG_MMIO, 0x577d, NULL, 0, 0, 0 },
+	{ "mmDIG8_AFMT_CNTL", REG_MMIO, 0x577e, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_LINK_CNTL", REG_MMIO, 0x57a0, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_PIXEL_FORMAT", REG_MMIO, 0x57a1, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSA_COLORIMETRY", REG_MMIO, 0x57a2, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_CONFIG", REG_MMIO, 0x57a3, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_STREAM_CNTL", REG_MMIO, 0x57a4, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_STEER_FIFO", REG_MMIO, 0x57a5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSA_MISC", REG_MMIO, 0x57a6, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_TIMING", REG_MMIO, 0x57a8, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_N", REG_MMIO, 0x57a9, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_M", REG_MMIO, 0x57aa, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x57ab, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x57ac, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_MSA_VBID", REG_MMIO, 0x57ad, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x57ae, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CNTL", REG_MMIO, 0x57af, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x57b0, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_SYM0", REG_MMIO, 0x57b1, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_SYM1", REG_MMIO, 0x57b2, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_SYM2", REG_MMIO, 0x57b3, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x57b4, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x57b5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_EN", REG_MMIO, 0x57b7, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_CNTL", REG_MMIO, 0x57b8, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_RESULT", REG_MMIO, 0x57b9, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x57ba, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x57bb, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x57bc, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x57bd, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x57be, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x57bf, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_CNTL", REG_MMIO, 0x57c3, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_CNTL1", REG_MMIO, 0x57c4, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_FRAMING1", REG_MMIO, 0x57c5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_FRAMING2", REG_MMIO, 0x57c6, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_FRAMING3", REG_MMIO, 0x57c7, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_FRAMING4", REG_MMIO, 0x57c8, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_AUD_N", REG_MMIO, 0x57c9, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x57ca, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_AUD_M", REG_MMIO, 0x57cb, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x57cc, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_TIMESTAMP", REG_MMIO, 0x57cd, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_SEC_PACKET_CNTL", REG_MMIO, 0x57ce, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_RATE_CNTL", REG_MMIO, 0x57cf, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_RATE_UPDATE", REG_MMIO, 0x57d1, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT0", REG_MMIO, 0x57d2, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT1", REG_MMIO, 0x57d3, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT2", REG_MMIO, 0x57d4, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT_UPDATE", REG_MMIO, 0x57d5, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_LINK_TIMING", REG_MMIO, 0x57d6, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_MISC_CNTL", REG_MMIO, 0x57d7, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x57d8, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_TEST_DEBUG_DATA", REG_MMIO, 0x57d9, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_FE_TEST_DEBUG_INDEX", REG_MMIO, 0x57da, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_FE_TEST_DEBUG_DATA", REG_MMIO, 0x57db, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_BS_SR_SWAP_CNTL", REG_MMIO, 0x57dc, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_DPHY_HBR2_PATTERN_CONTROL", REG_MMIO, 0x57dd, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT0_STATUS", REG_MMIO, 0x57df, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT1_STATUS", REG_MMIO, 0x57e0, NULL, 0, 0, 0 },
+	{ "mmDP8_DP_MSE_SAT2_STATUS", REG_MMIO, 0x57e1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x58, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x59, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "mmDC_PERFMON11_PERFCOUNTER_CNTL", REG_MMIO, 0x59a0, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFCOUNTER_STATE", REG_MMIO, 0x59a1, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x59a2, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CNTL", REG_MMIO, 0x59a3, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CVALUE_LOW", REG_MMIO, 0x59a4, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_HI", REG_MMIO, 0x59a5, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_LOW", REG_MMIO, 0x59a6, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x59a7, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x59a8, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON11_PERFMON_CNTL2", REG_MMIO, 0x59aa, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM8_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c0, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM8_AZALIA_STREAM_DATA", REG_MMIO, 0x59c1, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM9_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c2, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM9_AZALIA_STREAM_DATA", REG_MMIO, 0x59c3, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM10_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c4, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM10_AZALIA_STREAM_DATA", REG_MMIO, 0x59c5, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM11_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c6, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM11_AZALIA_STREAM_DATA", REG_MMIO, 0x59c7, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM12_AZALIA_STREAM_INDEX", REG_MMIO, 0x59c8, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM12_AZALIA_STREAM_DATA", REG_MMIO, 0x59c9, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM13_AZALIA_STREAM_INDEX", REG_MMIO, 0x59ca, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM13_AZALIA_STREAM_DATA", REG_MMIO, 0x59cb, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM14_AZALIA_STREAM_INDEX", REG_MMIO, 0x59cc, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM14_AZALIA_STREAM_DATA", REG_MMIO, 0x59cd, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM15_AZALIA_STREAM_INDEX", REG_MMIO, 0x59ce, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM15_AZALIA_STREAM_DATA", REG_MMIO, 0x59cf, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d4, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d4, &mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0], sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX)/sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX[0]), 0, 0 },
+	{ "mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d5, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d5, &mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0], sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA)/sizeof(mmAZALIA_F0_CODEC_INPUT_ENDPOINT_DATA[0]), 0, 0 },
+	{ "mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59d8, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59d9, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59dc, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59dd, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e0, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e1, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e4, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e5, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59e8, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59e9, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59ec, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59ed, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX", REG_MMIO, 0x59f0, NULL, 0, 0, 0 },
+	{ "mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA", REG_MMIO, 0x59f1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x5a, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5a84, &mmDCRX_PHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED0)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5a85, &mmDCRX_PHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED1)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5a86, &mmDCRX_PHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED2)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5a87, &mmDCRX_PHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED3)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5a88, &mmDCRX_PHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED4)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5a89, &mmDCRX_PHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED5)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5a8a, &mmDCRX_PHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED6)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5a8b, &mmDCRX_PHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED7)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5a8c, &mmDCRX_PHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED8)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5a8d, &mmDCRX_PHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED9)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5a8e, &mmDCRX_PHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED10)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5a8f, &mmDCRX_PHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED11)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x5a90, &mmDCRX_PHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED12)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x5a91, &mmDCRX_PHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED13)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x5a92, &mmDCRX_PHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED14)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x5a93, &mmDCRX_PHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED15)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x5a94, &mmDCRX_PHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED16)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x5a95, &mmDCRX_PHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED17)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x5a96, &mmDCRX_PHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED18)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x5a97, &mmDCRX_PHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED19)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x5a98, &mmDCRX_PHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED20)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x5a99, &mmDCRX_PHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED21)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x5a9a, &mmDCRX_PHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED22)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x5a9b, &mmDCRX_PHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED23)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x5a9c, &mmDCRX_PHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED24)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x5a9d, &mmDCRX_PHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED25)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x5a9e, &mmDCRX_PHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED26)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x5a9f, &mmDCRX_PHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED27)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x5aa0, &mmDCRX_PHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED28)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x5aa1, &mmDCRX_PHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED29)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x5aa2, &mmDCRX_PHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED30)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x5aa3, &mmDCRX_PHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED31)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x5aa4, &mmDCRX_PHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED32)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x5aa5, &mmDCRX_PHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED33)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x5aa6, &mmDCRX_PHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED34)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x5aa7, &mmDCRX_PHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED35)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x5aa8, &mmDCRX_PHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED36)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x5aa9, &mmDCRX_PHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED37)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x5aaa, &mmDCRX_PHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED38)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x5aab, &mmDCRX_PHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED39)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x5aac, &mmDCRX_PHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED40)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x5aad, &mmDCRX_PHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED41)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x5aae, &mmDCRX_PHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED42)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED42[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x5aaf, &mmDCRX_PHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED43)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED43[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x5ab0, &mmDCRX_PHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED44)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED44[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x5ab1, &mmDCRX_PHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED45)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED45[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x5ab2, &mmDCRX_PHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED46)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED46[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x5ab3, &mmDCRX_PHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED47)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED47[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x5ab4, &mmDCRX_PHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED48)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED48[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x5ab5, &mmDCRX_PHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED49)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED49[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x5ab6, &mmDCRX_PHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED50)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED50[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x5ab7, &mmDCRX_PHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED51)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED51[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x5ab8, &mmDCRX_PHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED52)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED52[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x5ab9, &mmDCRX_PHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED53)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED53[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x5aba, &mmDCRX_PHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED54)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED54[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x5abb, &mmDCRX_PHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED55)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED55[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x5abc, &mmDCRX_PHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED56)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED56[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x5abd, &mmDCRX_PHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED57)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED57[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x5abe, &mmDCRX_PHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED58)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED58[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x5abf, &mmDCRX_PHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED59)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED59[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x5ac0, &mmDCRX_PHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED60)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED60[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x5ac1, &mmDCRX_PHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED61)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED61[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x5ac2, &mmDCRX_PHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED62)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED62[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x5ac3, &mmDCRX_PHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED63)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED63[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x5ac4, &mmDCRX_PHY_MACRO_CNTL_RESERVED64[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED64)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED64[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x5ac5, &mmDCRX_PHY_MACRO_CNTL_RESERVED65[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED65)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED65[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x5ac6, &mmDCRX_PHY_MACRO_CNTL_RESERVED66[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED66)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED66[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x5ac7, &mmDCRX_PHY_MACRO_CNTL_RESERVED67[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED67)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED67[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x5ac8, &mmDCRX_PHY_MACRO_CNTL_RESERVED68[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED68)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED68[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x5ac9, &mmDCRX_PHY_MACRO_CNTL_RESERVED69[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED69)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED69[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x5aca, &mmDCRX_PHY_MACRO_CNTL_RESERVED70[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED70)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED70[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x5acb, &mmDCRX_PHY_MACRO_CNTL_RESERVED71[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED71)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED71[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x5acc, &mmDCRX_PHY_MACRO_CNTL_RESERVED72[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED72)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED72[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x5acd, &mmDCRX_PHY_MACRO_CNTL_RESERVED73[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED73)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED73[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x5ace, &mmDCRX_PHY_MACRO_CNTL_RESERVED74[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED74)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED74[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x5acf, &mmDCRX_PHY_MACRO_CNTL_RESERVED75[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED75)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED75[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x5ad0, &mmDCRX_PHY_MACRO_CNTL_RESERVED76[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED76)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED76[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x5ad1, &mmDCRX_PHY_MACRO_CNTL_RESERVED77[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED77)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED77[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x5ad2, &mmDCRX_PHY_MACRO_CNTL_RESERVED78[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED78)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED78[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x5ad3, &mmDCRX_PHY_MACRO_CNTL_RESERVED79[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED79)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED79[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x5ad4, &mmDCRX_PHY_MACRO_CNTL_RESERVED80[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED80)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED80[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x5ad5, &mmDCRX_PHY_MACRO_CNTL_RESERVED81[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED81)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED81[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x5ad6, &mmDCRX_PHY_MACRO_CNTL_RESERVED82[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED82)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED82[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x5ad7, &mmDCRX_PHY_MACRO_CNTL_RESERVED83[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED83)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED83[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x5ad8, &mmDCRX_PHY_MACRO_CNTL_RESERVED84[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED84)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED84[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x5ad9, &mmDCRX_PHY_MACRO_CNTL_RESERVED85[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED85)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED85[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x5ada, &mmDCRX_PHY_MACRO_CNTL_RESERVED86[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED86)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED86[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x5adb, &mmDCRX_PHY_MACRO_CNTL_RESERVED87[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED87)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED87[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x5adc, &mmDCRX_PHY_MACRO_CNTL_RESERVED88[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED88)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED88[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x5add, &mmDCRX_PHY_MACRO_CNTL_RESERVED89[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED89)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED89[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x5ade, &mmDCRX_PHY_MACRO_CNTL_RESERVED90[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED90)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED90[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x5adf, &mmDCRX_PHY_MACRO_CNTL_RESERVED91[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED91)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED91[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x5ae0, &mmDCRX_PHY_MACRO_CNTL_RESERVED92[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED92)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED92[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x5ae1, &mmDCRX_PHY_MACRO_CNTL_RESERVED93[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED93)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED93[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x5ae2, &mmDCRX_PHY_MACRO_CNTL_RESERVED94[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED94)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED94[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x5ae3, &mmDCRX_PHY_MACRO_CNTL_RESERVED95[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED95)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED95[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x5ae4, &mmDCRX_PHY_MACRO_CNTL_RESERVED96[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED96)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED96[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x5ae5, &mmDCRX_PHY_MACRO_CNTL_RESERVED97[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED97)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED97[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x5ae6, &mmDCRX_PHY_MACRO_CNTL_RESERVED98[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED98)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED98[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x5ae7, &mmDCRX_PHY_MACRO_CNTL_RESERVED99[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED99)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED99[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x5ae8, &mmDCRX_PHY_MACRO_CNTL_RESERVED100[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED100)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED100[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x5ae9, &mmDCRX_PHY_MACRO_CNTL_RESERVED101[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED101)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED101[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x5aea, &mmDCRX_PHY_MACRO_CNTL_RESERVED102[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED102)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED102[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x5aeb, &mmDCRX_PHY_MACRO_CNTL_RESERVED103[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED103)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED103[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x5aec, &mmDCRX_PHY_MACRO_CNTL_RESERVED104[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED104)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED104[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x5aed, &mmDCRX_PHY_MACRO_CNTL_RESERVED105[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED105)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED105[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x5aee, &mmDCRX_PHY_MACRO_CNTL_RESERVED106[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED106)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED106[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x5aef, &mmDCRX_PHY_MACRO_CNTL_RESERVED107[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED107)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED107[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x5af0, &mmDCRX_PHY_MACRO_CNTL_RESERVED108[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED108)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED108[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x5af1, &mmDCRX_PHY_MACRO_CNTL_RESERVED109[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED109)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED109[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x5af2, &mmDCRX_PHY_MACRO_CNTL_RESERVED110[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED110)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED110[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x5af3, &mmDCRX_PHY_MACRO_CNTL_RESERVED111[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED111)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED111[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x5af4, &mmDCRX_PHY_MACRO_CNTL_RESERVED112[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED112)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED112[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x5af5, &mmDCRX_PHY_MACRO_CNTL_RESERVED113[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED113)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED113[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x5af6, &mmDCRX_PHY_MACRO_CNTL_RESERVED114[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED114)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED114[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x5af7, &mmDCRX_PHY_MACRO_CNTL_RESERVED115[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED115)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED115[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x5af8, &mmDCRX_PHY_MACRO_CNTL_RESERVED116[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED116)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED116[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x5af9, &mmDCRX_PHY_MACRO_CNTL_RESERVED117[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED117)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED117[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x5afa, &mmDCRX_PHY_MACRO_CNTL_RESERVED118[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED118)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED118[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x5afb, &mmDCRX_PHY_MACRO_CNTL_RESERVED119[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED119)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED119[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x5afc, &mmDCRX_PHY_MACRO_CNTL_RESERVED120[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED120)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED120[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x5afd, &mmDCRX_PHY_MACRO_CNTL_RESERVED121[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED121)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED121[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x5afe, &mmDCRX_PHY_MACRO_CNTL_RESERVED122[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED122)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED122[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x5aff, &mmDCRX_PHY_MACRO_CNTL_RESERVED123[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED123)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED123[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x5b, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x5b00, &mmDCRX_PHY_MACRO_CNTL_RESERVED124[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED124)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED124[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x5b01, &mmDCRX_PHY_MACRO_CNTL_RESERVED125[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED125)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED125[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x5b02, &mmDCRX_PHY_MACRO_CNTL_RESERVED126[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED126)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED126[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x5b03, &mmDCRX_PHY_MACRO_CNTL_RESERVED127[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED127)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED127[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x5b04, &mmDCRX_PHY_MACRO_CNTL_RESERVED128[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED128)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED128[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x5b05, &mmDCRX_PHY_MACRO_CNTL_RESERVED129[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED129)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED129[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x5b06, &mmDCRX_PHY_MACRO_CNTL_RESERVED130[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED130)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED130[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x5b07, &mmDCRX_PHY_MACRO_CNTL_RESERVED131[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED131)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED131[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x5b08, &mmDCRX_PHY_MACRO_CNTL_RESERVED132[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED132)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED132[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x5b09, &mmDCRX_PHY_MACRO_CNTL_RESERVED133[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED133)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED133[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x5b0a, &mmDCRX_PHY_MACRO_CNTL_RESERVED134[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED134)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED134[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x5b0b, &mmDCRX_PHY_MACRO_CNTL_RESERVED135[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED135)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED135[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x5b0c, &mmDCRX_PHY_MACRO_CNTL_RESERVED136[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED136)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED136[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x5b0d, &mmDCRX_PHY_MACRO_CNTL_RESERVED137[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED137)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED137[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x5b0e, &mmDCRX_PHY_MACRO_CNTL_RESERVED138[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED138)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED138[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x5b0f, &mmDCRX_PHY_MACRO_CNTL_RESERVED139[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED139)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED139[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x5b10, &mmDCRX_PHY_MACRO_CNTL_RESERVED140[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED140)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED140[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x5b11, &mmDCRX_PHY_MACRO_CNTL_RESERVED141[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED141)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED141[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x5b12, &mmDCRX_PHY_MACRO_CNTL_RESERVED142[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED142)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED142[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x5b13, &mmDCRX_PHY_MACRO_CNTL_RESERVED143[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED143)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED143[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x5b14, &mmDCRX_PHY_MACRO_CNTL_RESERVED144[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED144)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED144[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x5b15, &mmDCRX_PHY_MACRO_CNTL_RESERVED145[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED145)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED145[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x5b16, &mmDCRX_PHY_MACRO_CNTL_RESERVED146[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED146)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED146[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x5b17, &mmDCRX_PHY_MACRO_CNTL_RESERVED147[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED147)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED147[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x5b18, &mmDCRX_PHY_MACRO_CNTL_RESERVED148[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED148)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED148[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x5b19, &mmDCRX_PHY_MACRO_CNTL_RESERVED149[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED149)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED149[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x5b1a, &mmDCRX_PHY_MACRO_CNTL_RESERVED150[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED150)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED150[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x5b1b, &mmDCRX_PHY_MACRO_CNTL_RESERVED151[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED151)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED151[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x5b1c, &mmDCRX_PHY_MACRO_CNTL_RESERVED152[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED152)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED152[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x5b1d, &mmDCRX_PHY_MACRO_CNTL_RESERVED153[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED153)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED153[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x5b1e, &mmDCRX_PHY_MACRO_CNTL_RESERVED154[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED154)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED154[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x5b1f, &mmDCRX_PHY_MACRO_CNTL_RESERVED155[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED155)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED155[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x5b20, &mmDCRX_PHY_MACRO_CNTL_RESERVED156[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED156)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED156[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x5b21, &mmDCRX_PHY_MACRO_CNTL_RESERVED157[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED157)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED157[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x5b22, &mmDCRX_PHY_MACRO_CNTL_RESERVED158[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED158)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED158[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x5b23, &mmDCRX_PHY_MACRO_CNTL_RESERVED159[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED159)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED159[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED160", REG_MMIO, 0x5b24, &mmDCRX_PHY_MACRO_CNTL_RESERVED160[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED160)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED160[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED161", REG_MMIO, 0x5b25, &mmDCRX_PHY_MACRO_CNTL_RESERVED161[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED161)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED161[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED162", REG_MMIO, 0x5b26, &mmDCRX_PHY_MACRO_CNTL_RESERVED162[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED162)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED162[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED163", REG_MMIO, 0x5b27, &mmDCRX_PHY_MACRO_CNTL_RESERVED163[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED163)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED163[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED164", REG_MMIO, 0x5b28, &mmDCRX_PHY_MACRO_CNTL_RESERVED164[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED164)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED164[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED165", REG_MMIO, 0x5b29, &mmDCRX_PHY_MACRO_CNTL_RESERVED165[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED165)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED165[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED166", REG_MMIO, 0x5b2a, &mmDCRX_PHY_MACRO_CNTL_RESERVED166[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED166)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED166[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED167", REG_MMIO, 0x5b2b, &mmDCRX_PHY_MACRO_CNTL_RESERVED167[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED167)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED167[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED168", REG_MMIO, 0x5b2c, &mmDCRX_PHY_MACRO_CNTL_RESERVED168[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED168)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED168[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED169", REG_MMIO, 0x5b2d, &mmDCRX_PHY_MACRO_CNTL_RESERVED169[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED169)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED169[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED170", REG_MMIO, 0x5b2e, &mmDCRX_PHY_MACRO_CNTL_RESERVED170[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED170)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED170[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED171", REG_MMIO, 0x5b2f, &mmDCRX_PHY_MACRO_CNTL_RESERVED171[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED171)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED171[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED172", REG_MMIO, 0x5b30, &mmDCRX_PHY_MACRO_CNTL_RESERVED172[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED172)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED172[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED173", REG_MMIO, 0x5b31, &mmDCRX_PHY_MACRO_CNTL_RESERVED173[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED173)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED173[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED174", REG_MMIO, 0x5b32, &mmDCRX_PHY_MACRO_CNTL_RESERVED174[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED174)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED174[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED175", REG_MMIO, 0x5b33, &mmDCRX_PHY_MACRO_CNTL_RESERVED175[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED175)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED175[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED176", REG_MMIO, 0x5b34, &mmDCRX_PHY_MACRO_CNTL_RESERVED176[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED176)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED176[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED177", REG_MMIO, 0x5b35, &mmDCRX_PHY_MACRO_CNTL_RESERVED177[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED177)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED177[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED178", REG_MMIO, 0x5b36, &mmDCRX_PHY_MACRO_CNTL_RESERVED178[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED178)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED178[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED179", REG_MMIO, 0x5b37, &mmDCRX_PHY_MACRO_CNTL_RESERVED179[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED179)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED179[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED180", REG_MMIO, 0x5b38, &mmDCRX_PHY_MACRO_CNTL_RESERVED180[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED180)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED180[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED181", REG_MMIO, 0x5b39, &mmDCRX_PHY_MACRO_CNTL_RESERVED181[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED181)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED181[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED182", REG_MMIO, 0x5b3a, &mmDCRX_PHY_MACRO_CNTL_RESERVED182[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED182)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED182[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED183", REG_MMIO, 0x5b3b, &mmDCRX_PHY_MACRO_CNTL_RESERVED183[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED183)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED183[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED184", REG_MMIO, 0x5b3c, &mmDCRX_PHY_MACRO_CNTL_RESERVED184[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED184)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED184[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED185", REG_MMIO, 0x5b3d, &mmDCRX_PHY_MACRO_CNTL_RESERVED185[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED185)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED185[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED186", REG_MMIO, 0x5b3e, &mmDCRX_PHY_MACRO_CNTL_RESERVED186[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED186)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED186[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED187", REG_MMIO, 0x5b3f, &mmDCRX_PHY_MACRO_CNTL_RESERVED187[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED187)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED187[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED188", REG_MMIO, 0x5b40, &mmDCRX_PHY_MACRO_CNTL_RESERVED188[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED188)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED188[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED189", REG_MMIO, 0x5b41, &mmDCRX_PHY_MACRO_CNTL_RESERVED189[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED189)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED189[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED190", REG_MMIO, 0x5b42, &mmDCRX_PHY_MACRO_CNTL_RESERVED190[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED190)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED190[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED191", REG_MMIO, 0x5b43, &mmDCRX_PHY_MACRO_CNTL_RESERVED191[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED191)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED191[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED192", REG_MMIO, 0x5b44, &mmDCRX_PHY_MACRO_CNTL_RESERVED192[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED192)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED192[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED193", REG_MMIO, 0x5b45, &mmDCRX_PHY_MACRO_CNTL_RESERVED193[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED193)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED193[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED194", REG_MMIO, 0x5b46, &mmDCRX_PHY_MACRO_CNTL_RESERVED194[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED194)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED194[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED195", REG_MMIO, 0x5b47, &mmDCRX_PHY_MACRO_CNTL_RESERVED195[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED195)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED195[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED196", REG_MMIO, 0x5b48, &mmDCRX_PHY_MACRO_CNTL_RESERVED196[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED196)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED196[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED197", REG_MMIO, 0x5b49, &mmDCRX_PHY_MACRO_CNTL_RESERVED197[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED197)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED197[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED198", REG_MMIO, 0x5b4a, &mmDCRX_PHY_MACRO_CNTL_RESERVED198[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED198)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED198[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED199", REG_MMIO, 0x5b4b, &mmDCRX_PHY_MACRO_CNTL_RESERVED199[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED199)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED199[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED200", REG_MMIO, 0x5b4c, &mmDCRX_PHY_MACRO_CNTL_RESERVED200[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED200)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED200[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED201", REG_MMIO, 0x5b4d, &mmDCRX_PHY_MACRO_CNTL_RESERVED201[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED201)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED201[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED202", REG_MMIO, 0x5b4e, &mmDCRX_PHY_MACRO_CNTL_RESERVED202[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED202)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED202[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED203", REG_MMIO, 0x5b4f, &mmDCRX_PHY_MACRO_CNTL_RESERVED203[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED203)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED203[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED204", REG_MMIO, 0x5b50, &mmDCRX_PHY_MACRO_CNTL_RESERVED204[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED204)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED204[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED205", REG_MMIO, 0x5b51, &mmDCRX_PHY_MACRO_CNTL_RESERVED205[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED205)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED205[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED206", REG_MMIO, 0x5b52, &mmDCRX_PHY_MACRO_CNTL_RESERVED206[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED206)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED206[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED207", REG_MMIO, 0x5b53, &mmDCRX_PHY_MACRO_CNTL_RESERVED207[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED207)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED207[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED208", REG_MMIO, 0x5b54, &mmDCRX_PHY_MACRO_CNTL_RESERVED208[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED208)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED208[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED209", REG_MMIO, 0x5b55, &mmDCRX_PHY_MACRO_CNTL_RESERVED209[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED209)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED209[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED210", REG_MMIO, 0x5b56, &mmDCRX_PHY_MACRO_CNTL_RESERVED210[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED210)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED210[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED211", REG_MMIO, 0x5b57, &mmDCRX_PHY_MACRO_CNTL_RESERVED211[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED211)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED211[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED212", REG_MMIO, 0x5b58, &mmDCRX_PHY_MACRO_CNTL_RESERVED212[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED212)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED212[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED213", REG_MMIO, 0x5b59, &mmDCRX_PHY_MACRO_CNTL_RESERVED213[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED213)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED213[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED214", REG_MMIO, 0x5b5a, &mmDCRX_PHY_MACRO_CNTL_RESERVED214[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED214)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED214[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED215", REG_MMIO, 0x5b5b, &mmDCRX_PHY_MACRO_CNTL_RESERVED215[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED215)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED215[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED216", REG_MMIO, 0x5b5c, &mmDCRX_PHY_MACRO_CNTL_RESERVED216[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED216)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED216[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED217", REG_MMIO, 0x5b5d, &mmDCRX_PHY_MACRO_CNTL_RESERVED217[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED217)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED217[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED218", REG_MMIO, 0x5b5e, &mmDCRX_PHY_MACRO_CNTL_RESERVED218[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED218)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED218[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED219", REG_MMIO, 0x5b5f, &mmDCRX_PHY_MACRO_CNTL_RESERVED219[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED219)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED219[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED220", REG_MMIO, 0x5b60, &mmDCRX_PHY_MACRO_CNTL_RESERVED220[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED220)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED220[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED221", REG_MMIO, 0x5b61, &mmDCRX_PHY_MACRO_CNTL_RESERVED221[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED221)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED221[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED222", REG_MMIO, 0x5b62, &mmDCRX_PHY_MACRO_CNTL_RESERVED222[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED222)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED222[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED223", REG_MMIO, 0x5b63, &mmDCRX_PHY_MACRO_CNTL_RESERVED223[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED223)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED223[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED224", REG_MMIO, 0x5b64, &mmDCRX_PHY_MACRO_CNTL_RESERVED224[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED224)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED224[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED225", REG_MMIO, 0x5b65, &mmDCRX_PHY_MACRO_CNTL_RESERVED225[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED225)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED225[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED226", REG_MMIO, 0x5b66, &mmDCRX_PHY_MACRO_CNTL_RESERVED226[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED226)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED226[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED227", REG_MMIO, 0x5b67, &mmDCRX_PHY_MACRO_CNTL_RESERVED227[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED227)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED227[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED228", REG_MMIO, 0x5b68, &mmDCRX_PHY_MACRO_CNTL_RESERVED228[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED228)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED228[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED229", REG_MMIO, 0x5b69, &mmDCRX_PHY_MACRO_CNTL_RESERVED229[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED229)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED229[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED230", REG_MMIO, 0x5b6a, &mmDCRX_PHY_MACRO_CNTL_RESERVED230[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED230)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED230[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED231", REG_MMIO, 0x5b6b, &mmDCRX_PHY_MACRO_CNTL_RESERVED231[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED231)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED231[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED232", REG_MMIO, 0x5b6c, &mmDCRX_PHY_MACRO_CNTL_RESERVED232[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED232)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED232[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED233", REG_MMIO, 0x5b6d, &mmDCRX_PHY_MACRO_CNTL_RESERVED233[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED233)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED233[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED234", REG_MMIO, 0x5b6e, &mmDCRX_PHY_MACRO_CNTL_RESERVED234[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED234)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED234[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED235", REG_MMIO, 0x5b6f, &mmDCRX_PHY_MACRO_CNTL_RESERVED235[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED235)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED235[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED236", REG_MMIO, 0x5b70, &mmDCRX_PHY_MACRO_CNTL_RESERVED236[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED236)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED236[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED237", REG_MMIO, 0x5b71, &mmDCRX_PHY_MACRO_CNTL_RESERVED237[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED237)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED237[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED238", REG_MMIO, 0x5b72, &mmDCRX_PHY_MACRO_CNTL_RESERVED238[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED238)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED238[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED239", REG_MMIO, 0x5b73, &mmDCRX_PHY_MACRO_CNTL_RESERVED239[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED239)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED239[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED240", REG_MMIO, 0x5b74, &mmDCRX_PHY_MACRO_CNTL_RESERVED240[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED240)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED240[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED241", REG_MMIO, 0x5b75, &mmDCRX_PHY_MACRO_CNTL_RESERVED241[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED241)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED241[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED242", REG_MMIO, 0x5b76, &mmDCRX_PHY_MACRO_CNTL_RESERVED242[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED242)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED242[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED243", REG_MMIO, 0x5b77, &mmDCRX_PHY_MACRO_CNTL_RESERVED243[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED243)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED243[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED244", REG_MMIO, 0x5b78, &mmDCRX_PHY_MACRO_CNTL_RESERVED244[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED244)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED244[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED245", REG_MMIO, 0x5b79, &mmDCRX_PHY_MACRO_CNTL_RESERVED245[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED245)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED245[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED246", REG_MMIO, 0x5b7a, &mmDCRX_PHY_MACRO_CNTL_RESERVED246[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED246)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED246[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED247", REG_MMIO, 0x5b7b, &mmDCRX_PHY_MACRO_CNTL_RESERVED247[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED247)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED247[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED248", REG_MMIO, 0x5b7c, &mmDCRX_PHY_MACRO_CNTL_RESERVED248[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED248)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED248[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED249", REG_MMIO, 0x5b7d, &mmDCRX_PHY_MACRO_CNTL_RESERVED249[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED249)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED249[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED250", REG_MMIO, 0x5b7e, &mmDCRX_PHY_MACRO_CNTL_RESERVED250[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED250)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED250[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED251", REG_MMIO, 0x5b7f, &mmDCRX_PHY_MACRO_CNTL_RESERVED251[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED251)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED251[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED252", REG_MMIO, 0x5b80, &mmDCRX_PHY_MACRO_CNTL_RESERVED252[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED252)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED252[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED253", REG_MMIO, 0x5b81, &mmDCRX_PHY_MACRO_CNTL_RESERVED253[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED253)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED253[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED254", REG_MMIO, 0x5b82, &mmDCRX_PHY_MACRO_CNTL_RESERVED254[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED254)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED254[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED255", REG_MMIO, 0x5b83, &mmDCRX_PHY_MACRO_CNTL_RESERVED255[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED255)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED255[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED256", REG_MMIO, 0x5b84, &mmDCRX_PHY_MACRO_CNTL_RESERVED256[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED256)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED256[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED257", REG_MMIO, 0x5b85, &mmDCRX_PHY_MACRO_CNTL_RESERVED257[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED257)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED257[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED258", REG_MMIO, 0x5b86, &mmDCRX_PHY_MACRO_CNTL_RESERVED258[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED258)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED258[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED259", REG_MMIO, 0x5b87, &mmDCRX_PHY_MACRO_CNTL_RESERVED259[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED259)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED259[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED260", REG_MMIO, 0x5b88, &mmDCRX_PHY_MACRO_CNTL_RESERVED260[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED260)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED260[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED261", REG_MMIO, 0x5b89, &mmDCRX_PHY_MACRO_CNTL_RESERVED261[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED261)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED261[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED262", REG_MMIO, 0x5b8a, &mmDCRX_PHY_MACRO_CNTL_RESERVED262[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED262)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED262[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED263", REG_MMIO, 0x5b8b, &mmDCRX_PHY_MACRO_CNTL_RESERVED263[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED263)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED263[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED264", REG_MMIO, 0x5b8c, &mmDCRX_PHY_MACRO_CNTL_RESERVED264[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED264)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED264[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED265", REG_MMIO, 0x5b8d, &mmDCRX_PHY_MACRO_CNTL_RESERVED265[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED265)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED265[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED266", REG_MMIO, 0x5b8e, &mmDCRX_PHY_MACRO_CNTL_RESERVED266[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED266)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED266[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED267", REG_MMIO, 0x5b8f, &mmDCRX_PHY_MACRO_CNTL_RESERVED267[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED267)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED267[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED268", REG_MMIO, 0x5b90, &mmDCRX_PHY_MACRO_CNTL_RESERVED268[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED268)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED268[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED269", REG_MMIO, 0x5b91, &mmDCRX_PHY_MACRO_CNTL_RESERVED269[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED269)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED269[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED270", REG_MMIO, 0x5b92, &mmDCRX_PHY_MACRO_CNTL_RESERVED270[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED270)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED270[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED271", REG_MMIO, 0x5b93, &mmDCRX_PHY_MACRO_CNTL_RESERVED271[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED271)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED271[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED272", REG_MMIO, 0x5b94, &mmDCRX_PHY_MACRO_CNTL_RESERVED272[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED272)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED272[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED273", REG_MMIO, 0x5b95, &mmDCRX_PHY_MACRO_CNTL_RESERVED273[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED273)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED273[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED274", REG_MMIO, 0x5b96, &mmDCRX_PHY_MACRO_CNTL_RESERVED274[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED274)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED274[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED275", REG_MMIO, 0x5b97, &mmDCRX_PHY_MACRO_CNTL_RESERVED275[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED275)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED275[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED276", REG_MMIO, 0x5b98, &mmDCRX_PHY_MACRO_CNTL_RESERVED276[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED276)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED276[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED277", REG_MMIO, 0x5b99, &mmDCRX_PHY_MACRO_CNTL_RESERVED277[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED277)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED277[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED278", REG_MMIO, 0x5b9a, &mmDCRX_PHY_MACRO_CNTL_RESERVED278[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED278)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED278[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED279", REG_MMIO, 0x5b9b, &mmDCRX_PHY_MACRO_CNTL_RESERVED279[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED279)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED279[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED280", REG_MMIO, 0x5b9c, &mmDCRX_PHY_MACRO_CNTL_RESERVED280[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED280)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED280[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED281", REG_MMIO, 0x5b9d, &mmDCRX_PHY_MACRO_CNTL_RESERVED281[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED281)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED281[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED282", REG_MMIO, 0x5b9e, &mmDCRX_PHY_MACRO_CNTL_RESERVED282[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED282)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED282[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED283", REG_MMIO, 0x5b9f, &mmDCRX_PHY_MACRO_CNTL_RESERVED283[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED283)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED283[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED284", REG_MMIO, 0x5ba0, &mmDCRX_PHY_MACRO_CNTL_RESERVED284[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED284)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED284[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED285", REG_MMIO, 0x5ba1, &mmDCRX_PHY_MACRO_CNTL_RESERVED285[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED285)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED285[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED286", REG_MMIO, 0x5ba2, &mmDCRX_PHY_MACRO_CNTL_RESERVED286[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED286)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED286[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED287", REG_MMIO, 0x5ba3, &mmDCRX_PHY_MACRO_CNTL_RESERVED287[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED287)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED287[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED288", REG_MMIO, 0x5ba4, &mmDCRX_PHY_MACRO_CNTL_RESERVED288[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED288)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED288[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED289", REG_MMIO, 0x5ba5, &mmDCRX_PHY_MACRO_CNTL_RESERVED289[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED289)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED289[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED290", REG_MMIO, 0x5ba6, &mmDCRX_PHY_MACRO_CNTL_RESERVED290[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED290)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED290[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED291", REG_MMIO, 0x5ba7, &mmDCRX_PHY_MACRO_CNTL_RESERVED291[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED291)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED291[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED292", REG_MMIO, 0x5ba8, &mmDCRX_PHY_MACRO_CNTL_RESERVED292[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED292)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED292[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED293", REG_MMIO, 0x5ba9, &mmDCRX_PHY_MACRO_CNTL_RESERVED293[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED293)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED293[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED294", REG_MMIO, 0x5baa, &mmDCRX_PHY_MACRO_CNTL_RESERVED294[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED294)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED294[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED295", REG_MMIO, 0x5bab, &mmDCRX_PHY_MACRO_CNTL_RESERVED295[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED295)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED295[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED296", REG_MMIO, 0x5bac, &mmDCRX_PHY_MACRO_CNTL_RESERVED296[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED296)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED296[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED297", REG_MMIO, 0x5bad, &mmDCRX_PHY_MACRO_CNTL_RESERVED297[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED297)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED297[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED298", REG_MMIO, 0x5bae, &mmDCRX_PHY_MACRO_CNTL_RESERVED298[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED298)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED298[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED299", REG_MMIO, 0x5baf, &mmDCRX_PHY_MACRO_CNTL_RESERVED299[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED299)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED299[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED300", REG_MMIO, 0x5bb0, &mmDCRX_PHY_MACRO_CNTL_RESERVED300[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED300)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED300[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED301", REG_MMIO, 0x5bb1, &mmDCRX_PHY_MACRO_CNTL_RESERVED301[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED301)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED301[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED302", REG_MMIO, 0x5bb2, &mmDCRX_PHY_MACRO_CNTL_RESERVED302[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED302)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED302[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED303", REG_MMIO, 0x5bb3, &mmDCRX_PHY_MACRO_CNTL_RESERVED303[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED303)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED303[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED304", REG_MMIO, 0x5bb4, &mmDCRX_PHY_MACRO_CNTL_RESERVED304[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED304)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED304[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED305", REG_MMIO, 0x5bb5, &mmDCRX_PHY_MACRO_CNTL_RESERVED305[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED305)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED305[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED306", REG_MMIO, 0x5bb6, &mmDCRX_PHY_MACRO_CNTL_RESERVED306[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED306)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED306[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED307", REG_MMIO, 0x5bb7, &mmDCRX_PHY_MACRO_CNTL_RESERVED307[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED307)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED307[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED308", REG_MMIO, 0x5bb8, &mmDCRX_PHY_MACRO_CNTL_RESERVED308[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED308)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED308[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED309", REG_MMIO, 0x5bb9, &mmDCRX_PHY_MACRO_CNTL_RESERVED309[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED309)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED309[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED310", REG_MMIO, 0x5bba, &mmDCRX_PHY_MACRO_CNTL_RESERVED310[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED310)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED310[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED311", REG_MMIO, 0x5bbb, &mmDCRX_PHY_MACRO_CNTL_RESERVED311[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED311)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED311[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED312", REG_MMIO, 0x5bbc, &mmDCRX_PHY_MACRO_CNTL_RESERVED312[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED312)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED312[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED313", REG_MMIO, 0x5bbd, &mmDCRX_PHY_MACRO_CNTL_RESERVED313[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED313)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED313[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED314", REG_MMIO, 0x5bbe, &mmDCRX_PHY_MACRO_CNTL_RESERVED314[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED314)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED314[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED315", REG_MMIO, 0x5bbf, &mmDCRX_PHY_MACRO_CNTL_RESERVED315[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED315)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED315[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED316", REG_MMIO, 0x5bc0, &mmDCRX_PHY_MACRO_CNTL_RESERVED316[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED316)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED316[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED317", REG_MMIO, 0x5bc1, &mmDCRX_PHY_MACRO_CNTL_RESERVED317[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED317)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED317[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED318", REG_MMIO, 0x5bc2, &mmDCRX_PHY_MACRO_CNTL_RESERVED318[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED318)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED318[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED319", REG_MMIO, 0x5bc3, &mmDCRX_PHY_MACRO_CNTL_RESERVED319[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED319)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED319[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED320", REG_MMIO, 0x5bc4, &mmDCRX_PHY_MACRO_CNTL_RESERVED320[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED320)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED320[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED321", REG_MMIO, 0x5bc5, &mmDCRX_PHY_MACRO_CNTL_RESERVED321[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED321)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED321[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED322", REG_MMIO, 0x5bc6, &mmDCRX_PHY_MACRO_CNTL_RESERVED322[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED322)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED322[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED323", REG_MMIO, 0x5bc7, &mmDCRX_PHY_MACRO_CNTL_RESERVED323[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED323)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED323[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED324", REG_MMIO, 0x5bc8, &mmDCRX_PHY_MACRO_CNTL_RESERVED324[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED324)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED324[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED325", REG_MMIO, 0x5bc9, &mmDCRX_PHY_MACRO_CNTL_RESERVED325[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED325)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED325[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED326", REG_MMIO, 0x5bca, &mmDCRX_PHY_MACRO_CNTL_RESERVED326[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED326)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED326[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED327", REG_MMIO, 0x5bcb, &mmDCRX_PHY_MACRO_CNTL_RESERVED327[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED327)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED327[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED328", REG_MMIO, 0x5bcc, &mmDCRX_PHY_MACRO_CNTL_RESERVED328[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED328)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED328[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED329", REG_MMIO, 0x5bcd, &mmDCRX_PHY_MACRO_CNTL_RESERVED329[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED329)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED329[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED330", REG_MMIO, 0x5bce, &mmDCRX_PHY_MACRO_CNTL_RESERVED330[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED330)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED330[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED331", REG_MMIO, 0x5bcf, &mmDCRX_PHY_MACRO_CNTL_RESERVED331[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED331)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED331[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED332", REG_MMIO, 0x5bd0, &mmDCRX_PHY_MACRO_CNTL_RESERVED332[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED332)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED332[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED333", REG_MMIO, 0x5bd1, &mmDCRX_PHY_MACRO_CNTL_RESERVED333[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED333)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED333[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED334", REG_MMIO, 0x5bd2, &mmDCRX_PHY_MACRO_CNTL_RESERVED334[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED334)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED334[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED335", REG_MMIO, 0x5bd3, &mmDCRX_PHY_MACRO_CNTL_RESERVED335[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED335)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED335[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED336", REG_MMIO, 0x5bd4, &mmDCRX_PHY_MACRO_CNTL_RESERVED336[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED336)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED336[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED337", REG_MMIO, 0x5bd5, &mmDCRX_PHY_MACRO_CNTL_RESERVED337[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED337)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED337[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED338", REG_MMIO, 0x5bd6, &mmDCRX_PHY_MACRO_CNTL_RESERVED338[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED338)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED338[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED339", REG_MMIO, 0x5bd7, &mmDCRX_PHY_MACRO_CNTL_RESERVED339[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED339)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED339[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED340", REG_MMIO, 0x5bd8, &mmDCRX_PHY_MACRO_CNTL_RESERVED340[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED340)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED340[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED341", REG_MMIO, 0x5bd9, &mmDCRX_PHY_MACRO_CNTL_RESERVED341[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED341)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED341[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED342", REG_MMIO, 0x5bda, &mmDCRX_PHY_MACRO_CNTL_RESERVED342[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED342)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED342[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED343", REG_MMIO, 0x5bdb, &mmDCRX_PHY_MACRO_CNTL_RESERVED343[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED343)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED343[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED344", REG_MMIO, 0x5bdc, &mmDCRX_PHY_MACRO_CNTL_RESERVED344[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED344)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED344[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED345", REG_MMIO, 0x5bdd, &mmDCRX_PHY_MACRO_CNTL_RESERVED345[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED345)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED345[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED346", REG_MMIO, 0x5bde, &mmDCRX_PHY_MACRO_CNTL_RESERVED346[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED346)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED346[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED347", REG_MMIO, 0x5bdf, &mmDCRX_PHY_MACRO_CNTL_RESERVED347[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED347)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED347[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED348", REG_MMIO, 0x5be0, &mmDCRX_PHY_MACRO_CNTL_RESERVED348[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED348)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED348[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED349", REG_MMIO, 0x5be1, &mmDCRX_PHY_MACRO_CNTL_RESERVED349[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED349)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED349[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED350", REG_MMIO, 0x5be2, &mmDCRX_PHY_MACRO_CNTL_RESERVED350[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED350)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED350[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED351", REG_MMIO, 0x5be3, &mmDCRX_PHY_MACRO_CNTL_RESERVED351[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED351)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED351[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED352", REG_MMIO, 0x5be4, &mmDCRX_PHY_MACRO_CNTL_RESERVED352[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED352)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED352[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED353", REG_MMIO, 0x5be5, &mmDCRX_PHY_MACRO_CNTL_RESERVED353[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED353)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED353[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED354", REG_MMIO, 0x5be6, &mmDCRX_PHY_MACRO_CNTL_RESERVED354[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED354)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED354[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED355", REG_MMIO, 0x5be7, &mmDCRX_PHY_MACRO_CNTL_RESERVED355[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED355)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED355[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED356", REG_MMIO, 0x5be8, &mmDCRX_PHY_MACRO_CNTL_RESERVED356[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED356)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED356[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED357", REG_MMIO, 0x5be9, &mmDCRX_PHY_MACRO_CNTL_RESERVED357[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED357)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED357[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED358", REG_MMIO, 0x5bea, &mmDCRX_PHY_MACRO_CNTL_RESERVED358[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED358)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED358[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED359", REG_MMIO, 0x5beb, &mmDCRX_PHY_MACRO_CNTL_RESERVED359[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED359)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED359[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED360", REG_MMIO, 0x5bec, &mmDCRX_PHY_MACRO_CNTL_RESERVED360[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED360)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED360[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED361", REG_MMIO, 0x5bed, &mmDCRX_PHY_MACRO_CNTL_RESERVED361[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED361)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED361[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED362", REG_MMIO, 0x5bee, &mmDCRX_PHY_MACRO_CNTL_RESERVED362[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED362)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED362[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED363", REG_MMIO, 0x5bef, &mmDCRX_PHY_MACRO_CNTL_RESERVED363[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED363)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED363[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED364", REG_MMIO, 0x5bf0, &mmDCRX_PHY_MACRO_CNTL_RESERVED364[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED364)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED364[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED365", REG_MMIO, 0x5bf1, &mmDCRX_PHY_MACRO_CNTL_RESERVED365[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED365)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED365[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED366", REG_MMIO, 0x5bf2, &mmDCRX_PHY_MACRO_CNTL_RESERVED366[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED366)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED366[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED367", REG_MMIO, 0x5bf3, &mmDCRX_PHY_MACRO_CNTL_RESERVED367[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED367)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED367[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED368", REG_MMIO, 0x5bf4, &mmDCRX_PHY_MACRO_CNTL_RESERVED368[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED368)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED368[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED369", REG_MMIO, 0x5bf5, &mmDCRX_PHY_MACRO_CNTL_RESERVED369[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED369)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED369[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED370", REG_MMIO, 0x5bf6, &mmDCRX_PHY_MACRO_CNTL_RESERVED370[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED370)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED370[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED371", REG_MMIO, 0x5bf7, &mmDCRX_PHY_MACRO_CNTL_RESERVED371[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED371)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED371[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED372", REG_MMIO, 0x5bf8, &mmDCRX_PHY_MACRO_CNTL_RESERVED372[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED372)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED372[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED373", REG_MMIO, 0x5bf9, &mmDCRX_PHY_MACRO_CNTL_RESERVED373[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED373)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED373[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED374", REG_MMIO, 0x5bfa, &mmDCRX_PHY_MACRO_CNTL_RESERVED374[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED374)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED374[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED375", REG_MMIO, 0x5bfb, &mmDCRX_PHY_MACRO_CNTL_RESERVED375[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED375)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED375[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED376", REG_MMIO, 0x5bfc, &mmDCRX_PHY_MACRO_CNTL_RESERVED376[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED376)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED376[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED377", REG_MMIO, 0x5bfd, &mmDCRX_PHY_MACRO_CNTL_RESERVED377[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED377)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED377[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED378", REG_MMIO, 0x5bfe, &mmDCRX_PHY_MACRO_CNTL_RESERVED378[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED378)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED378[0]), 0, 0 },
+	{ "mmDCRX_PHY_MACRO_CNTL_RESERVED379", REG_MMIO, 0x5bff, &mmDCRX_PHY_MACRO_CNTL_RESERVED379[0], sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED379)/sizeof(mmDCRX_PHY_MACRO_CNTL_RESERVED379[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x5c, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_CONTROL", REG_MMIO, 0x5c00, NULL, 0, 0, 0 },
+	{ "mmAUX_CONTROL", REG_MMIO, 0x5c00, &mmAUX_CONTROL[0], sizeof(mmAUX_CONTROL)/sizeof(mmAUX_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_CONTROL", REG_MMIO, 0x5c01, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_CONTROL", REG_MMIO, 0x5c01, &mmAUX_SW_CONTROL[0], sizeof(mmAUX_SW_CONTROL)/sizeof(mmAUX_SW_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_ARB_CONTROL", REG_MMIO, 0x5c02, NULL, 0, 0, 0 },
+	{ "mmAUX_ARB_CONTROL", REG_MMIO, 0x5c02, &mmAUX_ARB_CONTROL[0], sizeof(mmAUX_ARB_CONTROL)/sizeof(mmAUX_ARB_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c03, NULL, 0, 0, 0 },
+	{ "mmAUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c03, &mmAUX_INTERRUPT_CONTROL[0], sizeof(mmAUX_INTERRUPT_CONTROL)/sizeof(mmAUX_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_STATUS", REG_MMIO, 0x5c04, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_STATUS", REG_MMIO, 0x5c04, &mmAUX_SW_STATUS[0], sizeof(mmAUX_SW_STATUS)/sizeof(mmAUX_SW_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_LS_STATUS", REG_MMIO, 0x5c05, NULL, 0, 0, 0 },
+	{ "mmAUX_LS_STATUS", REG_MMIO, 0x5c05, &mmAUX_LS_STATUS[0], sizeof(mmAUX_LS_STATUS)/sizeof(mmAUX_LS_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_DATA", REG_MMIO, 0x5c06, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_DATA", REG_MMIO, 0x5c06, &mmAUX_SW_DATA[0], sizeof(mmAUX_SW_DATA)/sizeof(mmAUX_SW_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_LS_DATA", REG_MMIO, 0x5c07, NULL, 0, 0, 0 },
+	{ "mmAUX_LS_DATA", REG_MMIO, 0x5c07, &mmAUX_LS_DATA[0], sizeof(mmAUX_LS_DATA)/sizeof(mmAUX_LS_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c08, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c08, &mmAUX_DPHY_TX_REF_CONTROL[0], sizeof(mmAUX_DPHY_TX_REF_CONTROL)/sizeof(mmAUX_DPHY_TX_REF_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c09, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c09, &mmAUX_DPHY_TX_CONTROL[0], sizeof(mmAUX_DPHY_TX_CONTROL)/sizeof(mmAUX_DPHY_TX_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c0a, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c0a, &mmAUX_DPHY_RX_CONTROL0[0], sizeof(mmAUX_DPHY_RX_CONTROL0)/sizeof(mmAUX_DPHY_RX_CONTROL0[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c0b, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c0b, &mmAUX_DPHY_RX_CONTROL1[0], sizeof(mmAUX_DPHY_RX_CONTROL1)/sizeof(mmAUX_DPHY_RX_CONTROL1[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c0c, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_STATUS", REG_MMIO, 0x5c0c, &mmAUX_DPHY_TX_STATUS[0], sizeof(mmAUX_DPHY_TX_STATUS)/sizeof(mmAUX_DPHY_TX_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c0d, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_STATUS", REG_MMIO, 0x5c0d, &mmAUX_DPHY_RX_STATUS[0], sizeof(mmAUX_DPHY_RX_STATUS)/sizeof(mmAUX_DPHY_RX_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c0f, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c0f, &mmAUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmAUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmAUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c10, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c10, &mmAUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmAUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmAUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c11, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c11, &mmAUX_GTC_SYNC_STATUS[0], sizeof(mmAUX_GTC_SYNC_STATUS)/sizeof(mmAUX_GTC_SYNC_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c14, NULL, 0, 0, 0 },
+	{ "mmAUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c14, &mmAUX_TEST_DEBUG_INDEX[0], sizeof(mmAUX_TEST_DEBUG_INDEX)/sizeof(mmAUX_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c15, NULL, 0, 0, 0 },
+	{ "mmAUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c15, &mmAUX_TEST_DEBUG_DATA[0], sizeof(mmAUX_TEST_DEBUG_DATA)/sizeof(mmAUX_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDP_AUX1_AUX_CONTROL", REG_MMIO, 0x5c1c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_CONTROL", REG_MMIO, 0x5c1d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_ARB_CONTROL", REG_MMIO, 0x5c1e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c1f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_STATUS", REG_MMIO, 0x5c20, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_STATUS", REG_MMIO, 0x5c21, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_DATA", REG_MMIO, 0x5c22, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_DATA", REG_MMIO, 0x5c23, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c24, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c25, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c26, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c27, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c28, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c29, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c2b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c2c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c2d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c30, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c31, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_CONTROL", REG_MMIO, 0x5c38, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_CONTROL", REG_MMIO, 0x5c39, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_ARB_CONTROL", REG_MMIO, 0x5c3a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c3b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_STATUS", REG_MMIO, 0x5c3c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_STATUS", REG_MMIO, 0x5c3d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_DATA", REG_MMIO, 0x5c3e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_DATA", REG_MMIO, 0x5c3f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c40, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c41, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c42, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c43, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c44, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c45, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c47, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c48, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c49, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c4c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c4d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_CONTROL", REG_MMIO, 0x5c54, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_CONTROL", REG_MMIO, 0x5c55, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_ARB_CONTROL", REG_MMIO, 0x5c56, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c57, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_STATUS", REG_MMIO, 0x5c58, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_STATUS", REG_MMIO, 0x5c59, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_DATA", REG_MMIO, 0x5c5a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_DATA", REG_MMIO, 0x5c5b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c5c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c5d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c5e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c5f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c60, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c61, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c63, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c64, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c65, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c68, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c69, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_CONTROL", REG_MMIO, 0x5c70, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_CONTROL", REG_MMIO, 0x5c71, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_ARB_CONTROL", REG_MMIO, 0x5c72, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c73, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_STATUS", REG_MMIO, 0x5c74, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_STATUS", REG_MMIO, 0x5c75, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_DATA", REG_MMIO, 0x5c76, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_DATA", REG_MMIO, 0x5c77, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c78, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c79, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c7a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c7b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c7c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c7d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c7f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c80, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c81, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5c84, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5c85, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_CONTROL", REG_MMIO, 0x5c8c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_CONTROL", REG_MMIO, 0x5c8d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_ARB_CONTROL", REG_MMIO, 0x5c8e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x5c8f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_STATUS", REG_MMIO, 0x5c90, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_STATUS", REG_MMIO, 0x5c91, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_DATA", REG_MMIO, 0x5c92, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_DATA", REG_MMIO, 0x5c93, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x5c94, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x5c95, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x5c96, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x5c97, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_STATUS", REG_MMIO, 0x5c98, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_STATUS", REG_MMIO, 0x5c99, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x5c9b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x5c9c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x5c9d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_TEST_DEBUG_INDEX", REG_MMIO, 0x5ca0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_TEST_DEBUG_DATA", REG_MMIO, 0x5ca1, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x5d, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5d98, &mmDPHY_MACRO_CNTL_RESERVED0[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED0)/sizeof(mmDPHY_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5d99, &mmDPHY_MACRO_CNTL_RESERVED1[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED1)/sizeof(mmDPHY_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5d9a, &mmDPHY_MACRO_CNTL_RESERVED2[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED2)/sizeof(mmDPHY_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5d9b, &mmDPHY_MACRO_CNTL_RESERVED3[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED3)/sizeof(mmDPHY_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5d9c, &mmDPHY_MACRO_CNTL_RESERVED4[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED4)/sizeof(mmDPHY_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5d9d, &mmDPHY_MACRO_CNTL_RESERVED5[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED5)/sizeof(mmDPHY_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5d9e, &mmDPHY_MACRO_CNTL_RESERVED6[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED6)/sizeof(mmDPHY_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5d9f, &mmDPHY_MACRO_CNTL_RESERVED7[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED7)/sizeof(mmDPHY_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5da0, &mmDPHY_MACRO_CNTL_RESERVED8[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED8)/sizeof(mmDPHY_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5da1, &mmDPHY_MACRO_CNTL_RESERVED9[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED9)/sizeof(mmDPHY_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5da2, &mmDPHY_MACRO_CNTL_RESERVED10[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED10)/sizeof(mmDPHY_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5da3, &mmDPHY_MACRO_CNTL_RESERVED11[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED11)/sizeof(mmDPHY_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x5da4, &mmDPHY_MACRO_CNTL_RESERVED12[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED12)/sizeof(mmDPHY_MACRO_CNTL_RESERVED12[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x5da5, &mmDPHY_MACRO_CNTL_RESERVED13[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED13)/sizeof(mmDPHY_MACRO_CNTL_RESERVED13[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x5da6, &mmDPHY_MACRO_CNTL_RESERVED14[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED14)/sizeof(mmDPHY_MACRO_CNTL_RESERVED14[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x5da7, &mmDPHY_MACRO_CNTL_RESERVED15[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED15)/sizeof(mmDPHY_MACRO_CNTL_RESERVED15[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x5da8, &mmDPHY_MACRO_CNTL_RESERVED16[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED16)/sizeof(mmDPHY_MACRO_CNTL_RESERVED16[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x5da9, &mmDPHY_MACRO_CNTL_RESERVED17[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED17)/sizeof(mmDPHY_MACRO_CNTL_RESERVED17[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x5daa, &mmDPHY_MACRO_CNTL_RESERVED18[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED18)/sizeof(mmDPHY_MACRO_CNTL_RESERVED18[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x5dab, &mmDPHY_MACRO_CNTL_RESERVED19[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED19)/sizeof(mmDPHY_MACRO_CNTL_RESERVED19[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x5dac, &mmDPHY_MACRO_CNTL_RESERVED20[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED20)/sizeof(mmDPHY_MACRO_CNTL_RESERVED20[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x5dad, &mmDPHY_MACRO_CNTL_RESERVED21[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED21)/sizeof(mmDPHY_MACRO_CNTL_RESERVED21[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x5dae, &mmDPHY_MACRO_CNTL_RESERVED22[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED22)/sizeof(mmDPHY_MACRO_CNTL_RESERVED22[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x5daf, &mmDPHY_MACRO_CNTL_RESERVED23[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED23)/sizeof(mmDPHY_MACRO_CNTL_RESERVED23[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x5db0, &mmDPHY_MACRO_CNTL_RESERVED24[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED24)/sizeof(mmDPHY_MACRO_CNTL_RESERVED24[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x5db1, &mmDPHY_MACRO_CNTL_RESERVED25[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED25)/sizeof(mmDPHY_MACRO_CNTL_RESERVED25[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x5db2, &mmDPHY_MACRO_CNTL_RESERVED26[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED26)/sizeof(mmDPHY_MACRO_CNTL_RESERVED26[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x5db3, &mmDPHY_MACRO_CNTL_RESERVED27[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED27)/sizeof(mmDPHY_MACRO_CNTL_RESERVED27[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x5db4, &mmDPHY_MACRO_CNTL_RESERVED28[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED28)/sizeof(mmDPHY_MACRO_CNTL_RESERVED28[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x5db5, &mmDPHY_MACRO_CNTL_RESERVED29[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED29)/sizeof(mmDPHY_MACRO_CNTL_RESERVED29[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x5db6, &mmDPHY_MACRO_CNTL_RESERVED30[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED30)/sizeof(mmDPHY_MACRO_CNTL_RESERVED30[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x5db7, &mmDPHY_MACRO_CNTL_RESERVED31[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED31)/sizeof(mmDPHY_MACRO_CNTL_RESERVED31[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x5db8, &mmDPHY_MACRO_CNTL_RESERVED32[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED32)/sizeof(mmDPHY_MACRO_CNTL_RESERVED32[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x5db9, &mmDPHY_MACRO_CNTL_RESERVED33[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED33)/sizeof(mmDPHY_MACRO_CNTL_RESERVED33[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x5dba, &mmDPHY_MACRO_CNTL_RESERVED34[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED34)/sizeof(mmDPHY_MACRO_CNTL_RESERVED34[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x5dbb, &mmDPHY_MACRO_CNTL_RESERVED35[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED35)/sizeof(mmDPHY_MACRO_CNTL_RESERVED35[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x5dbc, &mmDPHY_MACRO_CNTL_RESERVED36[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED36)/sizeof(mmDPHY_MACRO_CNTL_RESERVED36[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x5dbd, &mmDPHY_MACRO_CNTL_RESERVED37[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED37)/sizeof(mmDPHY_MACRO_CNTL_RESERVED37[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x5dbe, &mmDPHY_MACRO_CNTL_RESERVED38[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED38)/sizeof(mmDPHY_MACRO_CNTL_RESERVED38[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x5dbf, &mmDPHY_MACRO_CNTL_RESERVED39[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED39)/sizeof(mmDPHY_MACRO_CNTL_RESERVED39[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x5dc0, &mmDPHY_MACRO_CNTL_RESERVED40[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED40)/sizeof(mmDPHY_MACRO_CNTL_RESERVED40[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x5dc1, &mmDPHY_MACRO_CNTL_RESERVED41[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED41)/sizeof(mmDPHY_MACRO_CNTL_RESERVED41[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x5dc2, &mmDPHY_MACRO_CNTL_RESERVED42[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED42)/sizeof(mmDPHY_MACRO_CNTL_RESERVED42[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x5dc3, &mmDPHY_MACRO_CNTL_RESERVED43[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED43)/sizeof(mmDPHY_MACRO_CNTL_RESERVED43[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x5dc4, &mmDPHY_MACRO_CNTL_RESERVED44[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED44)/sizeof(mmDPHY_MACRO_CNTL_RESERVED44[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x5dc5, &mmDPHY_MACRO_CNTL_RESERVED45[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED45)/sizeof(mmDPHY_MACRO_CNTL_RESERVED45[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x5dc6, &mmDPHY_MACRO_CNTL_RESERVED46[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED46)/sizeof(mmDPHY_MACRO_CNTL_RESERVED46[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x5dc7, &mmDPHY_MACRO_CNTL_RESERVED47[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED47)/sizeof(mmDPHY_MACRO_CNTL_RESERVED47[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x5dc8, &mmDPHY_MACRO_CNTL_RESERVED48[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED48)/sizeof(mmDPHY_MACRO_CNTL_RESERVED48[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x5dc9, &mmDPHY_MACRO_CNTL_RESERVED49[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED49)/sizeof(mmDPHY_MACRO_CNTL_RESERVED49[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x5dca, &mmDPHY_MACRO_CNTL_RESERVED50[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED50)/sizeof(mmDPHY_MACRO_CNTL_RESERVED50[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x5dcb, &mmDPHY_MACRO_CNTL_RESERVED51[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED51)/sizeof(mmDPHY_MACRO_CNTL_RESERVED51[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x5dcc, &mmDPHY_MACRO_CNTL_RESERVED52[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED52)/sizeof(mmDPHY_MACRO_CNTL_RESERVED52[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x5dcd, &mmDPHY_MACRO_CNTL_RESERVED53[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED53)/sizeof(mmDPHY_MACRO_CNTL_RESERVED53[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x5dce, &mmDPHY_MACRO_CNTL_RESERVED54[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED54)/sizeof(mmDPHY_MACRO_CNTL_RESERVED54[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x5dcf, &mmDPHY_MACRO_CNTL_RESERVED55[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED55)/sizeof(mmDPHY_MACRO_CNTL_RESERVED55[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x5dd0, &mmDPHY_MACRO_CNTL_RESERVED56[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED56)/sizeof(mmDPHY_MACRO_CNTL_RESERVED56[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x5dd1, &mmDPHY_MACRO_CNTL_RESERVED57[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED57)/sizeof(mmDPHY_MACRO_CNTL_RESERVED57[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x5dd2, &mmDPHY_MACRO_CNTL_RESERVED58[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED58)/sizeof(mmDPHY_MACRO_CNTL_RESERVED58[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x5dd3, &mmDPHY_MACRO_CNTL_RESERVED59[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED59)/sizeof(mmDPHY_MACRO_CNTL_RESERVED59[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x5dd4, &mmDPHY_MACRO_CNTL_RESERVED60[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED60)/sizeof(mmDPHY_MACRO_CNTL_RESERVED60[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x5dd5, &mmDPHY_MACRO_CNTL_RESERVED61[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED61)/sizeof(mmDPHY_MACRO_CNTL_RESERVED61[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x5dd6, &mmDPHY_MACRO_CNTL_RESERVED62[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED62)/sizeof(mmDPHY_MACRO_CNTL_RESERVED62[0]), 0, 0 },
+	{ "mmDPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x5dd7, &mmDPHY_MACRO_CNTL_RESERVED63[0], sizeof(mmDPHY_MACRO_CNTL_RESERVED63)/sizeof(mmDPHY_MACRO_CNTL_RESERVED63[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x5e, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "mmWB_ENABLE", REG_MMIO, 0x5e18, &mmWB_ENABLE[0], sizeof(mmWB_ENABLE)/sizeof(mmWB_ENABLE[0]), 0, 0 },
+	{ "mmWB_EC_CONFIG", REG_MMIO, 0x5e19, &mmWB_EC_CONFIG[0], sizeof(mmWB_EC_CONFIG)/sizeof(mmWB_EC_CONFIG[0]), 0, 0 },
+	{ "mmCNV_MODE", REG_MMIO, 0x5e1a, &mmCNV_MODE[0], sizeof(mmCNV_MODE)/sizeof(mmCNV_MODE[0]), 0, 0 },
+	{ "mmCNV_WINDOW_START", REG_MMIO, 0x5e1b, &mmCNV_WINDOW_START[0], sizeof(mmCNV_WINDOW_START)/sizeof(mmCNV_WINDOW_START[0]), 0, 0 },
+	{ "mmCNV_WINDOW_SIZE", REG_MMIO, 0x5e1c, &mmCNV_WINDOW_SIZE[0], sizeof(mmCNV_WINDOW_SIZE)/sizeof(mmCNV_WINDOW_SIZE[0]), 0, 0 },
+	{ "mmCNV_UPDATE", REG_MMIO, 0x5e1d, &mmCNV_UPDATE[0], sizeof(mmCNV_UPDATE)/sizeof(mmCNV_UPDATE[0]), 0, 0 },
+	{ "mmCNV_SOURCE_SIZE", REG_MMIO, 0x5e1e, &mmCNV_SOURCE_SIZE[0], sizeof(mmCNV_SOURCE_SIZE)/sizeof(mmCNV_SOURCE_SIZE[0]), 0, 0 },
+	{ "mmCNV_CSC_CONTROL", REG_MMIO, 0x5e1f, &mmCNV_CSC_CONTROL[0], sizeof(mmCNV_CSC_CONTROL)/sizeof(mmCNV_CSC_CONTROL[0]), 0, 0 },
+	{ "mmCNV_CSC_C11_C12", REG_MMIO, 0x5e20, &mmCNV_CSC_C11_C12[0], sizeof(mmCNV_CSC_C11_C12)/sizeof(mmCNV_CSC_C11_C12[0]), 0, 0 },
+	{ "mmCNV_CSC_C13_C14", REG_MMIO, 0x5e21, &mmCNV_CSC_C13_C14[0], sizeof(mmCNV_CSC_C13_C14)/sizeof(mmCNV_CSC_C13_C14[0]), 0, 0 },
+	{ "mmCNV_CSC_C21_C22", REG_MMIO, 0x5e22, &mmCNV_CSC_C21_C22[0], sizeof(mmCNV_CSC_C21_C22)/sizeof(mmCNV_CSC_C21_C22[0]), 0, 0 },
+	{ "mmCNV_CSC_C23_C24", REG_MMIO, 0x5e23, &mmCNV_CSC_C23_C24[0], sizeof(mmCNV_CSC_C23_C24)/sizeof(mmCNV_CSC_C23_C24[0]), 0, 0 },
+	{ "mmCNV_CSC_C31_C32", REG_MMIO, 0x5e24, &mmCNV_CSC_C31_C32[0], sizeof(mmCNV_CSC_C31_C32)/sizeof(mmCNV_CSC_C31_C32[0]), 0, 0 },
+	{ "mmCNV_CSC_C33_C34", REG_MMIO, 0x5e25, &mmCNV_CSC_C33_C34[0], sizeof(mmCNV_CSC_C33_C34)/sizeof(mmCNV_CSC_C33_C34[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_R", REG_MMIO, 0x5e26, &mmCNV_CSC_ROUND_OFFSET_R[0], sizeof(mmCNV_CSC_ROUND_OFFSET_R)/sizeof(mmCNV_CSC_ROUND_OFFSET_R[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_G", REG_MMIO, 0x5e27, &mmCNV_CSC_ROUND_OFFSET_G[0], sizeof(mmCNV_CSC_ROUND_OFFSET_G)/sizeof(mmCNV_CSC_ROUND_OFFSET_G[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_B", REG_MMIO, 0x5e28, &mmCNV_CSC_ROUND_OFFSET_B[0], sizeof(mmCNV_CSC_ROUND_OFFSET_B)/sizeof(mmCNV_CSC_ROUND_OFFSET_B[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_R", REG_MMIO, 0x5e29, &mmCNV_CSC_CLAMP_R[0], sizeof(mmCNV_CSC_CLAMP_R)/sizeof(mmCNV_CSC_CLAMP_R[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_G", REG_MMIO, 0x5e2a, &mmCNV_CSC_CLAMP_G[0], sizeof(mmCNV_CSC_CLAMP_G)/sizeof(mmCNV_CSC_CLAMP_G[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_B", REG_MMIO, 0x5e2b, &mmCNV_CSC_CLAMP_B[0], sizeof(mmCNV_CSC_CLAMP_B)/sizeof(mmCNV_CSC_CLAMP_B[0]), 0, 0 },
+	{ "mmCNV_TEST_CNTL", REG_MMIO, 0x5e2c, &mmCNV_TEST_CNTL[0], sizeof(mmCNV_TEST_CNTL)/sizeof(mmCNV_TEST_CNTL[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_RED", REG_MMIO, 0x5e2d, &mmCNV_TEST_CRC_RED[0], sizeof(mmCNV_TEST_CRC_RED)/sizeof(mmCNV_TEST_CRC_RED[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_GREEN", REG_MMIO, 0x5e2e, &mmCNV_TEST_CRC_GREEN[0], sizeof(mmCNV_TEST_CRC_GREEN)/sizeof(mmCNV_TEST_CRC_GREEN[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_BLUE", REG_MMIO, 0x5e2f, &mmCNV_TEST_CRC_BLUE[0], sizeof(mmCNV_TEST_CRC_BLUE)/sizeof(mmCNV_TEST_CRC_BLUE[0]), 0, 0 },
+	{ "mmWB_DEBUG_CTRL", REG_MMIO, 0x5e30, &mmWB_DEBUG_CTRL[0], sizeof(mmWB_DEBUG_CTRL)/sizeof(mmWB_DEBUG_CTRL[0]), 0, 0 },
+	{ "mmWB_DBG_MODE", REG_MMIO, 0x5e31, &mmWB_DBG_MODE[0], sizeof(mmWB_DBG_MODE)/sizeof(mmWB_DBG_MODE[0]), 0, 0 },
+	{ "mmWB_HW_DEBUG", REG_MMIO, 0x5e32, &mmWB_HW_DEBUG[0], sizeof(mmWB_HW_DEBUG)/sizeof(mmWB_HW_DEBUG[0]), 0, 0 },
+	{ "mmCNV_INPUT_SELECT", REG_MMIO, 0x5e33, &mmCNV_INPUT_SELECT[0], sizeof(mmCNV_INPUT_SELECT)/sizeof(mmCNV_INPUT_SELECT[0]), 0, 0 },
+	{ "mmCNV_TEST_DEBUG_INDEX", REG_MMIO, 0x5e34, &mmCNV_TEST_DEBUG_INDEX[0], sizeof(mmCNV_TEST_DEBUG_INDEX)/sizeof(mmCNV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCNV_TEST_DEBUG_DATA", REG_MMIO, 0x5e35, &mmCNV_TEST_DEBUG_DATA[0], sizeof(mmCNV_TEST_DEBUG_DATA)/sizeof(mmCNV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmWB_SOFT_RESET", REG_MMIO, 0x5e36, &mmWB_SOFT_RESET[0], sizeof(mmWB_SOFT_RESET)/sizeof(mmWB_SOFT_RESET[0]), 0, 0 },
+	{ "mmWB_WARM_UP_MODE_CTL1", REG_MMIO, 0x5e37, &mmWB_WARM_UP_MODE_CTL1[0], sizeof(mmWB_WARM_UP_MODE_CTL1)/sizeof(mmWB_WARM_UP_MODE_CTL1[0]), 0, 0 },
+	{ "mmWB_WARM_UP_MODE_CTL2", REG_MMIO, 0x5e38, &mmWB_WARM_UP_MODE_CTL2[0], sizeof(mmWB_WARM_UP_MODE_CTL2)/sizeof(mmWB_WARM_UP_MODE_CTL2[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x5f, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "mmDC_PERFMON12_PERFCOUNTER_CNTL", REG_MMIO, 0x5f68, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFCOUNTER_STATE", REG_MMIO, 0x5f69, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x5f6a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFMON_CNTL", REG_MMIO, 0x5f6b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFMON_CVALUE_LOW", REG_MMIO, 0x5f6c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFMON_HI", REG_MMIO, 0x5f6d, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFMON_LOW", REG_MMIO, 0x5f6e, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x5f6f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x5f70, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON12_PERFMON_CNTL2", REG_MMIO, 0x5f72, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fd0, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fd0, &mmCPLL_MACRO_CNTL_RESERVED0[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED0)/sizeof(mmCPLL_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fd1, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fd1, &mmCPLL_MACRO_CNTL_RESERVED1[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED1)/sizeof(mmCPLL_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fd2, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fd2, &mmCPLL_MACRO_CNTL_RESERVED2[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED2)/sizeof(mmCPLL_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fd3, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fd3, &mmCPLL_MACRO_CNTL_RESERVED3[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED3)/sizeof(mmCPLL_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fd4, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fd4, &mmCPLL_MACRO_CNTL_RESERVED4[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED4)/sizeof(mmCPLL_MACRO_CNTL_RESERVED4[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fd5, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fd5, &mmCPLL_MACRO_CNTL_RESERVED5[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED5)/sizeof(mmCPLL_MACRO_CNTL_RESERVED5[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fd6, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fd6, &mmCPLL_MACRO_CNTL_RESERVED6[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED6)/sizeof(mmCPLL_MACRO_CNTL_RESERVED6[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fd7, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fd7, &mmCPLL_MACRO_CNTL_RESERVED7[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED7)/sizeof(mmCPLL_MACRO_CNTL_RESERVED7[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fd8, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fd8, &mmCPLL_MACRO_CNTL_RESERVED8[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED8)/sizeof(mmCPLL_MACRO_CNTL_RESERVED8[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fd9, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fd9, &mmCPLL_MACRO_CNTL_RESERVED9[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED9)/sizeof(mmCPLL_MACRO_CNTL_RESERVED9[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fda, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fda, &mmCPLL_MACRO_CNTL_RESERVED10[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED10)/sizeof(mmCPLL_MACRO_CNTL_RESERVED10[0]), 0, 0 },
+	{ "mmDCCG_CPLL0_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fdb, NULL, 0, 0, 0 },
+	{ "mmCPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fdb, &mmCPLL_MACRO_CNTL_RESERVED11[0], sizeof(mmCPLL_MACRO_CNTL_RESERVED11)/sizeof(mmCPLL_MACRO_CNTL_RESERVED11[0]), 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fdc, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fdd, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fde, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5fdf, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fe0, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fe1, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fe2, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fe3, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5fe4, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5fe5, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5fe6, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL1_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fe7, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5fe8, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5fe9, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5fea, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5feb, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5fec, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5fed, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5fee, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5fef, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5ff0, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5ff1, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5ff2, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL2_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5ff3, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED0", REG_MMIO, 0x5ff4, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED1", REG_MMIO, 0x5ff5, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED2", REG_MMIO, 0x5ff6, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED3", REG_MMIO, 0x5ff7, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED4", REG_MMIO, 0x5ff8, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED5", REG_MMIO, 0x5ff9, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED6", REG_MMIO, 0x5ffa, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED7", REG_MMIO, 0x5ffb, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED8", REG_MMIO, 0x5ffc, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED9", REG_MMIO, 0x5ffd, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED10", REG_MMIO, 0x5ffe, NULL, 0, 0, 0 },
+	{ "mmDCCG_CPLL3_CPLL_MACRO_CNTL_RESERVED11", REG_MMIO, 0x5fff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6, &ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_PAYLOAD_CAPABILITY", REG_MMIO, 0x6, &mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[0], sizeof(mmOUTPUT_STREAM_PAYLOAD_CAPABILITY)/sizeof(mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmINPUT_STREAM_PAYLOAD_CAPABILITY", REG_MMIO, 0x6, &mmINPUT_STREAM_PAYLOAD_CAPABILITY[0], sizeof(mmINPUT_STREAM_PAYLOAD_CAPABILITY)/sizeof(mmINPUT_STREAM_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL6", REG_SMC, 0x6, &ixAZALIA_INPUT_CRC0_CHANNEL6[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL6)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL6[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL6", REG_SMC, 0x6, &ixAZALIA_CRC0_CHANNEL6[0], sizeof(ixAZALIA_CRC0_CHANNEL6)/sizeof(ixAZALIA_CRC0_CHANNEL6[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR5", REG_SMC, 0x6, &ixAUDIO_DESCRIPTOR5[0], sizeof(ixAUDIO_DESCRIPTOR5)/sizeof(ixAUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "ixDCIO_DEBUG6", REG_SMC, 0x6, &ixDCIO_DEBUG6[0], sizeof(ixDCIO_DEBUG6)/sizeof(ixDCIO_DEBUG6[0]), 0, 0 },
+	{ "ixATTR06", REG_SMC, 0x6, &ixATTR06[0], sizeof(ixATTR06)/sizeof(ixATTR06[0]), 0, 0 },
+	{ "ixCRT06", REG_SMC, 0x6, &ixCRT06[0], sizeof(ixCRT06)/sizeof(ixCRT06[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x60, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x61, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x62, &ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x6200, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x63, &ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x64, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x64, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x65, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB", REG_SMC, 0x65, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x66, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x66, &ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x67, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE", REG_SMC, 0x67, &ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x6706, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x670d, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x68, &ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED", REG_SMC, 0x68, &ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION", REG_SMC, 0x69, &ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE", REG_SMC, 0x6a, &ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE[0]), 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_ENABLE_STATUS", REG_SMC, 0x6b, &ixAZALIA_F0_AUDIO_ENABLE_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_ENABLE_STATUS)/sizeof(ixAZALIA_F0_AUDIO_ENABLE_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS", REG_SMC, 0x6c, &ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_ENABLED_INT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS", REG_SMC, 0x6d, &ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_DISABLED_INT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS", REG_SMC, 0x6e, &ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0], sizeof(ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS)/sizeof(ixAZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x6f09, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6f0a, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x6f0b, &ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x7, &ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_INPUT_CRC0_CHANNEL7", REG_SMC, 0x7, &ixAZALIA_INPUT_CRC0_CHANNEL7[0], sizeof(ixAZALIA_INPUT_CRC0_CHANNEL7)/sizeof(ixAZALIA_INPUT_CRC0_CHANNEL7[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL7", REG_SMC, 0x7, &ixAZALIA_CRC0_CHANNEL7[0], sizeof(ixAZALIA_CRC0_CHANNEL7)/sizeof(ixAZALIA_CRC0_CHANNEL7[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR6", REG_SMC, 0x7, &ixAUDIO_DESCRIPTOR6[0], sizeof(ixAUDIO_DESCRIPTOR6)/sizeof(ixAUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "ixDCIO_DEBUG7", REG_SMC, 0x7, &ixDCIO_DEBUG7[0], sizeof(ixDCIO_DEBUG7)/sizeof(ixDCIO_DEBUG7[0]), 0, 0 },
+	{ "ixATTR07", REG_SMC, 0x7, &ixATTR07[0], sizeof(ixATTR07)/sizeof(ixATTR07[0]), 0, 0 },
+	{ "ixCRT07", REG_SMC, 0x7, &ixCRT07[0], sizeof(ixCRT07)/sizeof(ixCRT07[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x7707, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x7708, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x7709, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x771c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x771d, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x771e, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x771f, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x7771, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE", REG_SMC, 0x7777, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE", REG_SMC, 0x7778, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE", REG_SMC, 0x7779, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE", REG_SMC, 0x777a, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR", REG_SMC, 0x777c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x7785, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x7786, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x7787, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x7788, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL", REG_SMC, 0x7798, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB", REG_SMC, 0x7799, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT", REG_SMC, 0x779a, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL", REG_SMC, 0x779b, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME", REG_SMC, 0x779c, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L", REG_SMC, 0x779d, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H", REG_SMC, 0x779e, &ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H[0]), 0, 0 },
+	{ "ixVGADCC_DBG_DCCIF_C", REG_SMC, 0x7e, &ixVGADCC_DBG_DCCIF_C[0], sizeof(ixVGADCC_DBG_DCCIF_C)/sizeof(ixVGADCC_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x7f09, &ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x7f0c, &ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x8, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "mmINTERRUPT_CONTROL", REG_MMIO, 0x8, &mmINTERRUPT_CONTROL[0], sizeof(mmINTERRUPT_CONTROL)/sizeof(mmINTERRUPT_CONTROL[0]), 0, 0 },
+	{ "ixDCIO_DEBUG8", REG_SMC, 0x8, &ixDCIO_DEBUG8[0], sizeof(ixDCIO_DEBUG8)/sizeof(ixDCIO_DEBUG8[0]), 0, 0 },
+	{ "ixATTR08", REG_SMC, 0x8, &ixATTR08[0], sizeof(ixATTR08)/sizeof(ixATTR08[0]), 0, 0 },
+	{ "ixCRT08", REG_SMC, 0x8, &ixCRT08[0], sizeof(ixCRT08)/sizeof(ixCRT08[0]), 0, 0 },
+	{ "mmWALL_CLOCK_COUNTER_ALIAS", REG_MMIO, 0x80c, &mmWALL_CLOCK_COUNTER_ALIAS[0], sizeof(mmWALL_CLOCK_COUNTER_ALIAS)/sizeof(mmWALL_CLOCK_COUNTER_ALIAS[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x821, &mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x9, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 },
+	{ "ixIDDCCIF02_DBG_DCCIF_C", REG_SMC, 0x9, &ixIDDCCIF02_DBG_DCCIF_C[0], sizeof(ixIDDCCIF02_DBG_DCCIF_C)/sizeof(ixIDDCCIF02_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR8", REG_SMC, 0x9, &ixAUDIO_DESCRIPTOR8[0], sizeof(ixAUDIO_DESCRIPTOR8)/sizeof(ixAUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "mmINTERRUPT_STATUS", REG_MMIO, 0x9, &mmINTERRUPT_STATUS[0], sizeof(mmINTERRUPT_STATUS)/sizeof(mmINTERRUPT_STATUS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG9", REG_SMC, 0x9, &ixDCIO_DEBUG9[0], sizeof(ixDCIO_DEBUG9)/sizeof(ixDCIO_DEBUG9[0]), 0, 0 },
+	{ "ixATTR09", REG_SMC, 0x9, &ixATTR09[0], sizeof(ixATTR09)/sizeof(ixATTR09[0]), 0, 0 },
+	{ "ixCRT09", REG_SMC, 0x9, &ixCRT09[0], sizeof(ixCRT09)/sizeof(ixCRT09[0]), 0, 0 },
+	{ "mmUNP1_UNP_GRPH_ENABLE", REG_MMIO, 0x9800, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_CONTROL", REG_MMIO, 0x9801, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_CONTROL_C", REG_MMIO, 0x9802, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_CONTROL_EXP", REG_MMIO, 0x9803, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SWAP_CNTL", REG_MMIO, 0x9805, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L", REG_MMIO, 0x9806, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C", REG_MMIO, 0x9807, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x9808, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x9809, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x980a, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x980b, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x980c, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PRIMARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x980d, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_L", REG_MMIO, 0x980e, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_C", REG_MMIO, 0x980f, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x9810, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x9811, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_L", REG_MMIO, 0x9812, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_C", REG_MMIO, 0x9813, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_L", REG_MMIO, 0x9814, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SECONDARY_BOTTOM_SURFACE_ADDRESS_HIGH_C", REG_MMIO, 0x9815, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PITCH_L", REG_MMIO, 0x9816, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_PITCH_C", REG_MMIO, 0x9817, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_L", REG_MMIO, 0x9818, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SURFACE_OFFSET_X_C", REG_MMIO, 0x9819, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_L", REG_MMIO, 0x981a, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SURFACE_OFFSET_Y_C", REG_MMIO, 0x981b, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_X_START_L", REG_MMIO, 0x981c, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_X_START_C", REG_MMIO, 0x981d, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_Y_START_L", REG_MMIO, 0x981e, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_Y_START_C", REG_MMIO, 0x981f, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_X_END_L", REG_MMIO, 0x9820, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_X_END_C", REG_MMIO, 0x9821, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_Y_END_L", REG_MMIO, 0x9822, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_Y_END_C", REG_MMIO, 0x9823, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_UPDATE", REG_MMIO, 0x9824, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_L", REG_MMIO, 0x9825, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SURFACE_ADDRESS_INUSE_C", REG_MMIO, 0x9826, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_L", REG_MMIO, 0x9827, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_SURFACE_ADDRESS_HIGH_INUSE_C", REG_MMIO, 0x9828, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x982b, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x982c, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x982e, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_FLIP_CONTROL", REG_MMIO, 0x982f, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_CRC_CONTROL", REG_MMIO, 0x9830, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_CRC_MASK", REG_MMIO, 0x9831, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_CRC_CURRENT", REG_MMIO, 0x9832, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_CRC_LAST", REG_MMIO, 0x9833, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x9834, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_HW_ROTATION", REG_MMIO, 0x9835, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_DEBUG", REG_MMIO, 0x9836, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_DEBUG2", REG_MMIO, 0x9837, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_TEST_DEBUG_INDEX", REG_MMIO, 0x9838, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_TEST_DEBUG_DATA", REG_MMIO, 0x9839, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_PIPE_OUTSTANDING_REQUEST_LIMIT", REG_MMIO, 0x983a, NULL, 0, 0, 0 },
+	{ "mmUNP1_UNP_DVMM_DEBUG", REG_MMIO, 0x983b, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_DATA_FORMAT", REG_MMIO, 0x983c, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_MEMORY_CTRL", REG_MMIO, 0x983d, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_MEMORY_SIZE_STATUS", REG_MMIO, 0x983e, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_DESKTOP_HEIGHT", REG_MMIO, 0x983f, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_VLINE_START_END", REG_MMIO, 0x9840, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_VLINE2_START_END", REG_MMIO, 0x9841, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_V_COUNTER", REG_MMIO, 0x9842, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_SNAPSHOT_V_COUNTER", REG_MMIO, 0x9843, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_V_COUNTER_CHROMA", REG_MMIO, 0x9844, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_SNAPSHOT_V_COUNTER_CHROMA", REG_MMIO, 0x9845, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_INTERRUPT_MASK", REG_MMIO, 0x9846, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_VLINE_STATUS", REG_MMIO, 0x9847, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_VLINE2_STATUS", REG_MMIO, 0x9848, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_VBLANK_STATUS", REG_MMIO, 0x9849, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_SYNC_RESET_SEL", REG_MMIO, 0x984a, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_BLACK_KEYER_R_CR", REG_MMIO, 0x984b, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_BLACK_KEYER_G_Y", REG_MMIO, 0x984c, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_BLACK_KEYER_B_CB", REG_MMIO, 0x984d, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_KEYER_COLOR_CTRL", REG_MMIO, 0x984e, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_KEYER_COLOR_R_CR", REG_MMIO, 0x984f, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_KEYER_COLOR_G_Y", REG_MMIO, 0x9850, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_KEYER_COLOR_B_CB", REG_MMIO, 0x9851, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x9852, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x9853, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x9854, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_BUFFER_LEVEL_STATUS", REG_MMIO, 0x9855, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_BUFFER_URGENCY_CTRL", REG_MMIO, 0x9856, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_BUFFER_URGENCY_STATUS", REG_MMIO, 0x9857, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_BUFFER_STATUS", REG_MMIO, 0x9858, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x9859, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_DEBUG", REG_MMIO, 0x985a, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_DEBUG2", REG_MMIO, 0x985b, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_DEBUG3", REG_MMIO, 0x985c, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_TEST_DEBUG_INDEX", REG_MMIO, 0x9866, NULL, 0, 0, 0 },
+	{ "mmLBV1_LBV_TEST_DEBUG_DATA", REG_MMIO, 0x9867, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_COEF_RAM_SELECT", REG_MMIO, 0x9870, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_COEF_RAM_TAP_DATA", REG_MMIO, 0x9871, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_MODE", REG_MMIO, 0x9872, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_TAP_CONTROL", REG_MMIO, 0x9873, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_CONTROL", REG_MMIO, 0x9874, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x9875, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x9876, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_HORZ_FILTER_CONTROL", REG_MMIO, 0x9877, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x9878, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_HORZ_FILTER_INIT", REG_MMIO, 0x9879, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_HORZ_FILTER_SCALE_RATIO_C", REG_MMIO, 0x987a, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_HORZ_FILTER_INIT_C", REG_MMIO, 0x987b, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VERT_FILTER_CONTROL", REG_MMIO, 0x987c, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x987d, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VERT_FILTER_INIT", REG_MMIO, 0x987e, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VERT_FILTER_INIT_BOT", REG_MMIO, 0x987f, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VERT_FILTER_SCALE_RATIO_C", REG_MMIO, 0x9880, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VERT_FILTER_INIT_C", REG_MMIO, 0x9881, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VERT_FILTER_INIT_BOT_C", REG_MMIO, 0x9882, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_ROUND_OFFSET", REG_MMIO, 0x9883, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_UPDATE", REG_MMIO, 0x9884, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_ALU_CONTROL", REG_MMIO, 0x9885, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VIEWPORT_START", REG_MMIO, 0x9886, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VIEWPORT_START_SECONDARY", REG_MMIO, 0x9887, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VIEWPORT_SIZE", REG_MMIO, 0x9888, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VIEWPORT_START_C", REG_MMIO, 0x9889, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VIEWPORT_START_SECONDARY_C", REG_MMIO, 0x988a, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_VIEWPORT_SIZE_C", REG_MMIO, 0x988b, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x988c, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x988d, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_MODE_CHANGE_DET1", REG_MMIO, 0x988e, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_MODE_CHANGE_DET2", REG_MMIO, 0x988f, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_MODE_CHANGE_DET3", REG_MMIO, 0x9890, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_MODE_CHANGE_MASK", REG_MMIO, 0x9891, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT", REG_MMIO, 0x9892, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_HORZ_FILTER_INIT_BOT_C", REG_MMIO, 0x9893, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_DEBUG2", REG_MMIO, 0x9894, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_DEBUG", REG_MMIO, 0x9895, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_TEST_DEBUG_INDEX", REG_MMIO, 0x9896, NULL, 0, 0, 0 },
+	{ "mmSCLV1_SCLV_TEST_DEBUG_DATA", REG_MMIO, 0x9897, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_UPDATE", REG_MMIO, 0x98a4, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_INPUT_CSC_CONTROL", REG_MMIO, 0x98a5, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C11_C12_A", REG_MMIO, 0x98a6, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C13_C14_A", REG_MMIO, 0x98a7, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C21_C22_A", REG_MMIO, 0x98a8, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C23_C24_A", REG_MMIO, 0x98a9, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C31_C32_A", REG_MMIO, 0x98aa, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C33_C34_A", REG_MMIO, 0x98ab, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C11_C12_B", REG_MMIO, 0x98ac, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C13_C14_B", REG_MMIO, 0x98ad, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C21_C22_B", REG_MMIO, 0x98ae, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C23_C24_B", REG_MMIO, 0x98af, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C31_C32_B", REG_MMIO, 0x98b0, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_CSC_C33_C34_B", REG_MMIO, 0x98b1, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_PRESCALE_CONTROL", REG_MMIO, 0x98b2, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_PRESCALE_VALUES_R", REG_MMIO, 0x98b3, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_PRESCALE_VALUES_G", REG_MMIO, 0x98b4, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_PRESCALE_VALUES_B", REG_MMIO, 0x98b5, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_OUTPUT_CSC_CONTROL", REG_MMIO, 0x98b6, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C11_C12_A", REG_MMIO, 0x98b7, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C13_C14_A", REG_MMIO, 0x98b8, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C21_C22_A", REG_MMIO, 0x98b9, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C23_C24_A", REG_MMIO, 0x98ba, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C31_C32_A", REG_MMIO, 0x98bb, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C33_C34_A", REG_MMIO, 0x98bc, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C11_C12_B", REG_MMIO, 0x98bd, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C13_C14_B", REG_MMIO, 0x98be, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C21_C22_B", REG_MMIO, 0x98bf, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C23_C24_B", REG_MMIO, 0x98c0, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C31_C32_B", REG_MMIO, 0x98c1, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_CSC_C33_C34_B", REG_MMIO, 0x98c2, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_DENORM_CLAMP_CONTROL", REG_MMIO, 0x98c3, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_DENORM_CLAMP_RANGE_R_CR", REG_MMIO, 0x98c4, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_DENORM_CLAMP_RANGE_G_Y", REG_MMIO, 0x98c5, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_DENORM_CLAMP_RANGE_B_CB", REG_MMIO, 0x98c6, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_FP_CONVERTED_FIELD", REG_MMIO, 0x98c7, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CONTROL", REG_MMIO, 0x98c8, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_LUT_INDEX", REG_MMIO, 0x98c9, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_LUT_DATA", REG_MMIO, 0x98ca, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_LUT_WRITE_EN_MASK", REG_MMIO, 0x98cb, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_START_CNTL", REG_MMIO, 0x98cc, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_SLOPE_CNTL", REG_MMIO, 0x98cd, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL1", REG_MMIO, 0x98ce, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_END_CNTL2", REG_MMIO, 0x98cf, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_0_1", REG_MMIO, 0x98d0, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_2_3", REG_MMIO, 0x98d1, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_4_5", REG_MMIO, 0x98d2, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_6_7", REG_MMIO, 0x98d3, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_8_9", REG_MMIO, 0x98d4, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_10_11", REG_MMIO, 0x98d5, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_12_13", REG_MMIO, 0x98d6, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLA_REGION_14_15", REG_MMIO, 0x98d7, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_START_CNTL", REG_MMIO, 0x98d8, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_SLOPE_CNTL", REG_MMIO, 0x98d9, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL1", REG_MMIO, 0x98da, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_END_CNTL2", REG_MMIO, 0x98db, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_0_1", REG_MMIO, 0x98dc, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_2_3", REG_MMIO, 0x98dd, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_4_5", REG_MMIO, 0x98de, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_6_7", REG_MMIO, 0x98df, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_8_9", REG_MMIO, 0x98e0, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_10_11", REG_MMIO, 0x98e1, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_12_13", REG_MMIO, 0x98e2, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_GAMMA_CORR_CNTLB_REGION_14_15", REG_MMIO, 0x98e3, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_PACK_FIFO_ERROR", REG_MMIO, 0x98e4, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_OUTPUT_FIFO_ERROR", REG_MMIO, 0x98e5, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_GAMMA_LUT_AUTOFILL", REG_MMIO, 0x98e6, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_GAMMA_LUT_RW_INDEX", REG_MMIO, 0x98e7, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_GAMMA_LUT_SEQ_COLOR", REG_MMIO, 0x98e8, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_GAMMA_LUT_PWL_DATA", REG_MMIO, 0x98e9, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_GAMMA_LUT_30_COLOR", REG_MMIO, 0x98ea, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL1", REG_MMIO, 0x98eb, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_INPUT_GAMMA_CONTROL2", REG_MMIO, 0x98ec, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_B", REG_MMIO, 0x98ed, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_G", REG_MMIO, 0x98ee, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_INPUT_GAMMA_BW_OFFSETS_R", REG_MMIO, 0x98ef, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_DEBUG_CONTROL", REG_MMIO, 0x98f0, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_TEST_DEBUG_INDEX", REG_MMIO, 0x98f1, NULL, 0, 0, 0 },
+	{ "mmCOL_MAN1_COL_MAN_TEST_DEBUG_DATA", REG_MMIO, 0x98f3, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_CLOCK_CONTROL", REG_MMIO, 0x98f4, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_SOFT_RESET", REG_MMIO, 0x98f5, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_DMIFV_CLOCK_CONTROL", REG_MMIO, 0x98f6, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_DBG_CONFIG", REG_MMIO, 0x98f7, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_DMIFV_MEM_PWR_CTRL", REG_MMIO, 0x98f8, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_DMIFV_MEM_PWR_STATUS", REG_MMIO, 0x98f9, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_MEM_PWR_CTRL", REG_MMIO, 0x98fa, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_MEM_PWR_CTRL2", REG_MMIO, 0x98fb, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_MEM_PWR_STATUS", REG_MMIO, 0x98fc, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_DMIFV_DEBUG", REG_MMIO, 0x98fd, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_MISC", REG_MMIO, 0x98fe, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_L_FLUSH", REG_MMIO, 0x98ff, NULL, 0, 0, 0 },
+	{ "mmDCFEV1_DCFEV_C_FLUSH", REG_MMIO, 0x9900, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFCOUNTER_CNTL", REG_MMIO, 0x9924, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFCOUNTER_STATE", REG_MMIO, 0x9925, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x9926, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFMON_CNTL", REG_MMIO, 0x9927, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFMON_CVALUE_LOW", REG_MMIO, 0x9928, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFMON_HI", REG_MMIO, 0x9929, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFMON_LOW", REG_MMIO, 0x992a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x992b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x992c, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON13_PERFMON_CNTL2", REG_MMIO, 0x992e, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x9930, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x9931, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_WATERMARK_MASK_CONTROL", REG_MMIO, 0x9932, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_PIPE_URGENCY_CONTROL", REG_MMIO, 0x9933, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_PIPE_DPM_CONTROL", REG_MMIO, 0x9934, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL", REG_MMIO, 0x9935, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x9936, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x9937, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_REPEATER_PROGRAM", REG_MMIO, 0x9938, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_HW_DEBUG_A", REG_MMIO, 0x9939, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_HW_DEBUG_B", REG_MMIO, 0x993a, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_HW_DEBUG_11", REG_MMIO, 0x993b, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV0_CHK_PRE_PROC_CNTL", REG_MMIO, 0x993c, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x993d, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x993e, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_WATERMARK_MASK_CONTROL", REG_MMIO, 0x993f, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_PIPE_URGENCY_CONTROL", REG_MMIO, 0x9940, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_PIPE_DPM_CONTROL", REG_MMIO, 0x9941, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL", REG_MMIO, 0x9942, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x9943, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x9944, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_REPEATER_PROGRAM", REG_MMIO, 0x9945, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_HW_DEBUG_A", REG_MMIO, 0x9946, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_HW_DEBUG_B", REG_MMIO, 0x9947, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_HW_DEBUG_11", REG_MMIO, 0x9948, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV1_CHK_PRE_PROC_CNTL", REG_MMIO, 0x9949, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV_TEST_DEBUG_INDEX", REG_MMIO, 0x994e, NULL, 0, 0, 0 },
+	{ "mmDMIFV_PG1_DPGV_TEST_DEBUG_DATA", REG_MMIO, 0x994f, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_CONTROL", REG_MMIO, 0x996d, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_SM_CONTROL2", REG_MMIO, 0x996e, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_CONTROL2", REG_MMIO, 0x996f, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_UPDATE", REG_MMIO, 0x9970, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_UNDERFLOW_INTERRUPT", REG_MMIO, 0x9971, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_V_UPDATE_LOCK", REG_MMIO, 0x9973, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_DEBUG", REG_MMIO, 0x9974, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_TEST_DEBUG_INDEX", REG_MMIO, 0x9975, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_TEST_DEBUG_DATA", REG_MMIO, 0x9976, NULL, 0, 0, 0 },
+	{ "mmBLNDV1_BLNDV_REG_UPDATE_STATUS", REG_MMIO, 0x9977, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_H_TOTAL", REG_MMIO, 0x9980, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_H_BLANK_START_END", REG_MMIO, 0x9981, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_H_SYNC_A", REG_MMIO, 0x9982, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_V_TOTAL", REG_MMIO, 0x9987, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_V_BLANK_START_END", REG_MMIO, 0x998d, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_V_SYNC_A", REG_MMIO, 0x998e, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CONTROL", REG_MMIO, 0x999c, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_START_LINE_CONTROL", REG_MMIO, 0x99b3, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_TEST_DEBUG_INDEX", REG_MMIO, 0x99c6, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_TEST_DEBUG_DATA", REG_MMIO, 0x99c7, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_OVERSCAN_COLOR", REG_MMIO, 0x99c8, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_OVERSCAN_COLOR_EXT", REG_MMIO, 0x99c9, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_BLACK_COLOR", REG_MMIO, 0x99cc, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_BLACK_COLOR_EXT", REG_MMIO, 0x99cd, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC_CNTL", REG_MMIO, 0x99d4, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x99d5, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x99d6, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x99d7, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x99d8, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC0_DATA_RG", REG_MMIO, 0x99d9, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC0_DATA_B", REG_MMIO, 0x99da, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x99db, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x99dc, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x99dd, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x99de, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC1_DATA_RG", REG_MMIO, 0x99df, NULL, 0, 0, 0 },
+	{ "mmCRTCV1_CRTCV_CRC1_DATA_B", REG_MMIO, 0x99e0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x9a00, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x9a01, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x9a02, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x9a03, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x9a04, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT", REG_MMIO, 0x9a04, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x9a05, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL", REG_MMIO, 0x9a05, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x9a06, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_TMDP", REG_MMIO, 0x9a06, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x9a07, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS", REG_MMIO, 0x9a07, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x9a08, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x9a08, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x9a09, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1", REG_MMIO, 0x9a09, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x9a0a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2", REG_MMIO, 0x9a0a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x9a0b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3", REG_MMIO, 0x9a0b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x9a0c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4", REG_MMIO, 0x9a0c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x9a0d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5", REG_MMIO, 0x9a0d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x9a0e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6", REG_MMIO, 0x9a0e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x9a0f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7", REG_MMIO, 0x9a0f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x9a10, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_PHY_CNTL", REG_MMIO, 0x9a10, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x9a11, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_TX_CLOCK_CNTL", REG_MMIO, 0x9a11, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x9a12, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x9a13, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_TX_CNTL", REG_MMIO, 0x9a13, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x9a14, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x9a15, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_CBUS_CNTL", REG_MMIO, 0x9a15, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x9a16, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x9a16, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x9a17, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x9a17, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x9a18, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x9a18, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x9a19, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x9a19, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x9a1a, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x9a1a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x9a1b, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x9a1b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x9a1c, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_DEBUG_CONFIG", REG_MMIO, 0x9a1c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x9a1d, NULL, 0, 0, 0 },
+	{ "mmDPCSTX2_DPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x9a1d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x9a1e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x9a1f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x9a20, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x9a20, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x9a21, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x9a21, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x9a22, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x9a22, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x9a23, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0", REG_MMIO, 0x9a23, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x9a24, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0", REG_MMIO, 0x9a24, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x9a25, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0", REG_MMIO, 0x9a25, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x9a26, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0", REG_MMIO, 0x9a26, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x9a27, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0", REG_MMIO, 0x9a27, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x9a28, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0", REG_MMIO, 0x9a28, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x9a29, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0", REG_MMIO, 0x9a29, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x9a2a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0", REG_MMIO, 0x9a2a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x9a2b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0", REG_MMIO, 0x9a2b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x9a2c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0", REG_MMIO, 0x9a2c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x9a2d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0", REG_MMIO, 0x9a2d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x9a2e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0", REG_MMIO, 0x9a2e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x9a2f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0", REG_MMIO, 0x9a2f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x9a30, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x9a30, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x9a31, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x9a31, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x9a32, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x9a32, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x9a33, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1", REG_MMIO, 0x9a33, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x9a34, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1", REG_MMIO, 0x9a34, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x9a35, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1", REG_MMIO, 0x9a35, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x9a36, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1", REG_MMIO, 0x9a36, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x9a37, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1", REG_MMIO, 0x9a37, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x9a38, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1", REG_MMIO, 0x9a38, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x9a39, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1", REG_MMIO, 0x9a39, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x9a3a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1", REG_MMIO, 0x9a3a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x9a3b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1", REG_MMIO, 0x9a3b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x9a3c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1", REG_MMIO, 0x9a3c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x9a3d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1", REG_MMIO, 0x9a3d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x9a3e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1", REG_MMIO, 0x9a3e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x9a3f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1", REG_MMIO, 0x9a3f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x9a40, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x9a40, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x9a41, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x9a41, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x9a42, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x9a42, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x9a43, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2", REG_MMIO, 0x9a43, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x9a44, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2", REG_MMIO, 0x9a44, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x9a45, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2", REG_MMIO, 0x9a45, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x9a46, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2", REG_MMIO, 0x9a46, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x9a47, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2", REG_MMIO, 0x9a47, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x9a48, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2", REG_MMIO, 0x9a48, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x9a49, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2", REG_MMIO, 0x9a49, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x9a4a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2", REG_MMIO, 0x9a4a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x9a4b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2", REG_MMIO, 0x9a4b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x9a4c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2", REG_MMIO, 0x9a4c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x9a4d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2", REG_MMIO, 0x9a4d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x9a4e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2", REG_MMIO, 0x9a4e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x9a4f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2", REG_MMIO, 0x9a4f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x9a50, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x9a50, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x9a51, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x9a51, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x9a52, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x9a52, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x9a53, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3", REG_MMIO, 0x9a53, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x9a54, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3", REG_MMIO, 0x9a54, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x9a55, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3", REG_MMIO, 0x9a55, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x9a56, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3", REG_MMIO, 0x9a56, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x9a57, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3", REG_MMIO, 0x9a57, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x9a58, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3", REG_MMIO, 0x9a58, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x9a59, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3", REG_MMIO, 0x9a59, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x9a5a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3", REG_MMIO, 0x9a5a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x9a5b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3", REG_MMIO, 0x9a5b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x9a5c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3", REG_MMIO, 0x9a5c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x9a5d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3", REG_MMIO, 0x9a5d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x9a5e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3", REG_MMIO, 0x9a5e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x9a5f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3", REG_MMIO, 0x9a5f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x9a60, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0", REG_MMIO, 0x9a60, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x9a61, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1", REG_MMIO, 0x9a61, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x9a62, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2", REG_MMIO, 0x9a62, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x9a63, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3", REG_MMIO, 0x9a63, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x9a64, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE", REG_MMIO, 0x9a64, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x9a65, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE", REG_MMIO, 0x9a65, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x9a66, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_CAL_CTRL", REG_MMIO, 0x9a66, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x9a67, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_LOOP_CTRL", REG_MMIO, 0x9a67, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x9a68, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_DEBUG0", REG_MMIO, 0x9a68, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x9a69, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_VREG_CFG", REG_MMIO, 0x9a69, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x9a6a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_OBSERVE0", REG_MMIO, 0x9a6a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x9a6b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_OBSERVE1", REG_MMIO, 0x9a6b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x9a6c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_DFT_OUT", REG_MMIO, 0x9a6c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x9a6d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x9a6e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x9a6f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x9a70, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x9a71, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x9a72, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x9a73, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x9a74, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x9a75, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x9a76, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x9a77, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x9a78, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x9a79, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x9a7a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x9a7b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x9a7c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x9a7d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x9a7e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x9a7f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x9a80, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x9a81, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x9a82, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x9a83, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x9a84, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x9a85, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x9a86, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x9a87, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x9a88, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x9a89, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x9a8a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x9a8b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x9a8c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x9a8d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x9a8e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x9a8f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x9a90, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x9a91, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x9a92, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x9a93, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x9a94, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x9a95, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x9a96, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x9a97, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x9a98, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x9a99, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x9a9a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x9a9b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x9a9c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x9a9d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x9a9e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1", REG_MMIO, 0x9a9e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x9a9f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL", REG_MMIO, 0x9a9f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x9aa0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x9aa1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x9aa2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x9aa3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x9aa4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT", REG_MMIO, 0x9aa4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x9aa5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL", REG_MMIO, 0x9aa5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x9aa6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_TMDP", REG_MMIO, 0x9aa6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x9aa7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS", REG_MMIO, 0x9aa7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x9aa8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x9aa8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x9aa9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1", REG_MMIO, 0x9aa9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x9aaa, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2", REG_MMIO, 0x9aaa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x9aab, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3", REG_MMIO, 0x9aab, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x9aac, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4", REG_MMIO, 0x9aac, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x9aad, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5", REG_MMIO, 0x9aad, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x9aae, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6", REG_MMIO, 0x9aae, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x9aaf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7", REG_MMIO, 0x9aaf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x9ab0, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_PHY_CNTL", REG_MMIO, 0x9ab0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x9ab1, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_TX_CLOCK_CNTL", REG_MMIO, 0x9ab1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x9ab2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x9ab3, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_TX_CNTL", REG_MMIO, 0x9ab3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x9ab4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x9ab5, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_CBUS_CNTL", REG_MMIO, 0x9ab5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x9ab6, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x9ab6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x9ab7, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x9ab7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x9ab8, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x9ab8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x9ab9, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x9ab9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x9aba, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x9aba, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x9abb, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x9abb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x9abc, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_DEBUG_CONFIG", REG_MMIO, 0x9abc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x9abd, NULL, 0, 0, 0 },
+	{ "mmDPCSTX3_DPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x9abd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x9abe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x9abf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x9ac0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x9ac0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x9ac1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x9ac1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x9ac2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x9ac2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x9ac3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0", REG_MMIO, 0x9ac3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x9ac4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0", REG_MMIO, 0x9ac4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x9ac5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0", REG_MMIO, 0x9ac5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x9ac6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0", REG_MMIO, 0x9ac6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x9ac7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0", REG_MMIO, 0x9ac7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x9ac8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0", REG_MMIO, 0x9ac8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x9ac9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0", REG_MMIO, 0x9ac9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x9aca, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0", REG_MMIO, 0x9aca, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x9acb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0", REG_MMIO, 0x9acb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x9acc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0", REG_MMIO, 0x9acc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x9acd, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0", REG_MMIO, 0x9acd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x9ace, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0", REG_MMIO, 0x9ace, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x9acf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0", REG_MMIO, 0x9acf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x9ad0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x9ad0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x9ad1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x9ad1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x9ad2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x9ad2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x9ad3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1", REG_MMIO, 0x9ad3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x9ad4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1", REG_MMIO, 0x9ad4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x9ad5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1", REG_MMIO, 0x9ad5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x9ad6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1", REG_MMIO, 0x9ad6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x9ad7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1", REG_MMIO, 0x9ad7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x9ad8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1", REG_MMIO, 0x9ad8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x9ad9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1", REG_MMIO, 0x9ad9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x9ada, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1", REG_MMIO, 0x9ada, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x9adb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1", REG_MMIO, 0x9adb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x9adc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1", REG_MMIO, 0x9adc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x9add, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1", REG_MMIO, 0x9add, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x9ade, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1", REG_MMIO, 0x9ade, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x9adf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1", REG_MMIO, 0x9adf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x9ae0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x9ae0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x9ae1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x9ae1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x9ae2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x9ae2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x9ae3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2", REG_MMIO, 0x9ae3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x9ae4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2", REG_MMIO, 0x9ae4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x9ae5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2", REG_MMIO, 0x9ae5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x9ae6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2", REG_MMIO, 0x9ae6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x9ae7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2", REG_MMIO, 0x9ae7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x9ae8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2", REG_MMIO, 0x9ae8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x9ae9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2", REG_MMIO, 0x9ae9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x9aea, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2", REG_MMIO, 0x9aea, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x9aeb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2", REG_MMIO, 0x9aeb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x9aec, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2", REG_MMIO, 0x9aec, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x9aed, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2", REG_MMIO, 0x9aed, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x9aee, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2", REG_MMIO, 0x9aee, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x9aef, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2", REG_MMIO, 0x9aef, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x9af0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x9af0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x9af1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x9af1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x9af2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x9af2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x9af3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3", REG_MMIO, 0x9af3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x9af4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3", REG_MMIO, 0x9af4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x9af5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3", REG_MMIO, 0x9af5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x9af6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3", REG_MMIO, 0x9af6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x9af7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3", REG_MMIO, 0x9af7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x9af8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3", REG_MMIO, 0x9af8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x9af9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3", REG_MMIO, 0x9af9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x9afa, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3", REG_MMIO, 0x9afa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x9afb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3", REG_MMIO, 0x9afb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x9afc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3", REG_MMIO, 0x9afc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x9afd, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3", REG_MMIO, 0x9afd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x9afe, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3", REG_MMIO, 0x9afe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x9aff, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3", REG_MMIO, 0x9aff, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x9b00, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0", REG_MMIO, 0x9b00, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x9b01, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1", REG_MMIO, 0x9b01, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x9b02, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2", REG_MMIO, 0x9b02, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x9b03, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3", REG_MMIO, 0x9b03, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x9b04, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE", REG_MMIO, 0x9b04, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x9b05, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE", REG_MMIO, 0x9b05, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x9b06, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_CAL_CTRL", REG_MMIO, 0x9b06, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x9b07, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_LOOP_CTRL", REG_MMIO, 0x9b07, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x9b08, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_DEBUG0", REG_MMIO, 0x9b08, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x9b09, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_VREG_CFG", REG_MMIO, 0x9b09, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x9b0a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_OBSERVE0", REG_MMIO, 0x9b0a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x9b0b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_OBSERVE1", REG_MMIO, 0x9b0b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x9b0c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_DFT_OUT", REG_MMIO, 0x9b0c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x9b0d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x9b0e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x9b0f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x9b10, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x9b11, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x9b12, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x9b13, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x9b14, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x9b15, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x9b16, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x9b17, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x9b18, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x9b19, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x9b1a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x9b1b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x9b1c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x9b1d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x9b1e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x9b1f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x9b20, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x9b21, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x9b22, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x9b23, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x9b24, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x9b25, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x9b26, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x9b27, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x9b28, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x9b29, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x9b2a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x9b2b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x9b2c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x9b2d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x9b2e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x9b2f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x9b30, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x9b31, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x9b32, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x9b33, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x9b34, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x9b35, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x9b36, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x9b37, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x9b38, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x9b39, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x9b3a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x9b3b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x9b3c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x9b3d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x9b3e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1", REG_MMIO, 0x9b3e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x9b3f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL", REG_MMIO, 0x9b3f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x9b40, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x9b41, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x9b42, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x9b43, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x9b44, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_LANE_PWRMGMT", REG_MMIO, 0x9b44, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x9b45, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_TXCNTRL", REG_MMIO, 0x9b45, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x9b46, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_TMDP", REG_MMIO, 0x9b46, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x9b47, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_LANE_RESETS", REG_MMIO, 0x9b47, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x9b48, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x9b48, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x9b49, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU1", REG_MMIO, 0x9b49, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x9b4a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU2", REG_MMIO, 0x9b4a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x9b4b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU3", REG_MMIO, 0x9b4b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x9b4c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU4", REG_MMIO, 0x9b4c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x9b4d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU5", REG_MMIO, 0x9b4d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x9b4e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU6", REG_MMIO, 0x9b4e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x9b4f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS4_COMMON_DISP_RFU7", REG_MMIO, 0x9b4f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x9b50, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_PHY_CNTL", REG_MMIO, 0x9b50, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x9b51, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_TX_CLOCK_CNTL", REG_MMIO, 0x9b51, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x9b52, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x9b53, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_TX_CNTL", REG_MMIO, 0x9b53, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x9b54, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x9b55, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_CBUS_CNTL", REG_MMIO, 0x9b55, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x9b56, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x9b56, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x9b57, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x9b57, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x9b58, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x9b58, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x9b59, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x9b59, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x9b5a, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x9b5a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x9b5b, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x9b5b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x9b5c, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_DEBUG_CONFIG", REG_MMIO, 0x9b5c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x9b5d, NULL, 0, 0, 0 },
+	{ "mmDPCSTX4_DPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x9b5d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x9b5e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x9b5f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x9b60, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x9b60, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x9b61, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x9b61, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x9b62, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x9b62, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x9b63, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE0", REG_MMIO, 0x9b63, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x9b64, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE0", REG_MMIO, 0x9b64, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x9b65, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE0", REG_MMIO, 0x9b65, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x9b66, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE0", REG_MMIO, 0x9b66, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x9b67, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE0", REG_MMIO, 0x9b67, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x9b68, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE0", REG_MMIO, 0x9b68, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x9b69, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE0", REG_MMIO, 0x9b69, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x9b6a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE0", REG_MMIO, 0x9b6a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x9b6b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE0", REG_MMIO, 0x9b6b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x9b6c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE0", REG_MMIO, 0x9b6c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x9b6d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE0", REG_MMIO, 0x9b6d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x9b6e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE0", REG_MMIO, 0x9b6e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x9b6f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE0", REG_MMIO, 0x9b6f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x9b70, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x9b70, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x9b71, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x9b71, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x9b72, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x9b72, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x9b73, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE1", REG_MMIO, 0x9b73, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x9b74, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE1", REG_MMIO, 0x9b74, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x9b75, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE1", REG_MMIO, 0x9b75, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x9b76, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE1", REG_MMIO, 0x9b76, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x9b77, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE1", REG_MMIO, 0x9b77, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x9b78, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE1", REG_MMIO, 0x9b78, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x9b79, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE1", REG_MMIO, 0x9b79, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x9b7a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE1", REG_MMIO, 0x9b7a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x9b7b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE1", REG_MMIO, 0x9b7b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x9b7c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE1", REG_MMIO, 0x9b7c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x9b7d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE1", REG_MMIO, 0x9b7d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x9b7e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE1", REG_MMIO, 0x9b7e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x9b7f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE1", REG_MMIO, 0x9b7f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x9b80, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x9b80, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x9b81, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x9b81, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x9b82, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x9b82, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x9b83, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE2", REG_MMIO, 0x9b83, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x9b84, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE2", REG_MMIO, 0x9b84, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x9b85, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE2", REG_MMIO, 0x9b85, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x9b86, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE2", REG_MMIO, 0x9b86, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x9b87, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE2", REG_MMIO, 0x9b87, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x9b88, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE2", REG_MMIO, 0x9b88, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x9b89, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE2", REG_MMIO, 0x9b89, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x9b8a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE2", REG_MMIO, 0x9b8a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x9b8b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE2", REG_MMIO, 0x9b8b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x9b8c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE2", REG_MMIO, 0x9b8c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x9b8d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE2", REG_MMIO, 0x9b8d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x9b8e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE2", REG_MMIO, 0x9b8e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x9b8f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE2", REG_MMIO, 0x9b8f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x9b90, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x9b90, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x9b91, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x9b91, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x9b92, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x9b92, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x9b93, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU0_LANE3", REG_MMIO, 0x9b93, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x9b94, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU1_LANE3", REG_MMIO, 0x9b94, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x9b95, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU2_LANE3", REG_MMIO, 0x9b95, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x9b96, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU3_LANE3", REG_MMIO, 0x9b96, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x9b97, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU4_LANE3", REG_MMIO, 0x9b97, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x9b98, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU5_LANE3", REG_MMIO, 0x9b98, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x9b99, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU6_LANE3", REG_MMIO, 0x9b99, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x9b9a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU7_LANE3", REG_MMIO, 0x9b9a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x9b9b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU8_LANE3", REG_MMIO, 0x9b9b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x9b9c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU9_LANE3", REG_MMIO, 0x9b9c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x9b9d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU10_LANE3", REG_MMIO, 0x9b9d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x9b9e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU11_LANE3", REG_MMIO, 0x9b9e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x9b9f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS4_TX_DISP_RFU12_LANE3", REG_MMIO, 0x9b9f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x9ba0, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_FREQ_CTRL0", REG_MMIO, 0x9ba0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x9ba1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_FREQ_CTRL1", REG_MMIO, 0x9ba1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x9ba2, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_FREQ_CTRL2", REG_MMIO, 0x9ba2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x9ba3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_FREQ_CTRL3", REG_MMIO, 0x9ba3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x9ba4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_BW_CTRL_COARSE", REG_MMIO, 0x9ba4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x9ba5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_BW_CTRL_FINE", REG_MMIO, 0x9ba5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x9ba6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_CAL_CTRL", REG_MMIO, 0x9ba6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x9ba7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_LOOP_CTRL", REG_MMIO, 0x9ba7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x9ba8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_DEBUG0", REG_MMIO, 0x9ba8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x9ba9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_VREG_CFG", REG_MMIO, 0x9ba9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x9baa, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_OBSERVE0", REG_MMIO, 0x9baa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x9bab, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_OBSERVE1", REG_MMIO, 0x9bab, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x9bac, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_DFT_OUT", REG_MMIO, 0x9bac, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x9bad, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x9bae, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x9baf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x9bb0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x9bb1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x9bb2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x9bb3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x9bb4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x9bb5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x9bb6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x9bb7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x9bb8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x9bb9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x9bba, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x9bbb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x9bbc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x9bbd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x9bbe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x9bbf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x9bc0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x9bc1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x9bc2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x9bc3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x9bc4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x9bc5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x9bc6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x9bc7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x9bc8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x9bc9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x9bca, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x9bcb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x9bcc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x9bcd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x9bce, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x9bcf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x9bd0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x9bd1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x9bd2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x9bd3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x9bd4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x9bd5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x9bd6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x9bd7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x9bd8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x9bd9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x9bda, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x9bdb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x9bdc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x9bdd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x9bde, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL1", REG_MMIO, 0x9bde, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x9bdf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS4_PLL_WRAP_CNTRL", REG_MMIO, 0x9bdf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x9be0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x9be1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x9be2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x9be3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x9be4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_LANE_PWRMGMT", REG_MMIO, 0x9be4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x9be5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_TXCNTRL", REG_MMIO, 0x9be5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x9be6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_TMDP", REG_MMIO, 0x9be6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x9be7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_LANE_RESETS", REG_MMIO, 0x9be7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x9be8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x9be8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x9be9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU1", REG_MMIO, 0x9be9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x9bea, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU2", REG_MMIO, 0x9bea, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x9beb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU3", REG_MMIO, 0x9beb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x9bec, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU4", REG_MMIO, 0x9bec, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x9bed, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU5", REG_MMIO, 0x9bed, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x9bee, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU6", REG_MMIO, 0x9bee, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x9bef, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS5_COMMON_DISP_RFU7", REG_MMIO, 0x9bef, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x9bf0, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_PHY_CNTL", REG_MMIO, 0x9bf0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x9bf1, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_TX_CLOCK_CNTL", REG_MMIO, 0x9bf1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x9bf2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x9bf3, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_TX_CNTL", REG_MMIO, 0x9bf3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x9bf4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x9bf5, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_CBUS_CNTL", REG_MMIO, 0x9bf5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x9bf6, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x9bf6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x9bf7, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x9bf7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x9bf8, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x9bf8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x9bf9, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x9bf9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x9bfa, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x9bfa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x9bfb, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x9bfb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x9bfc, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_DEBUG_CONFIG", REG_MMIO, 0x9bfc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x9bfd, NULL, 0, 0, 0 },
+	{ "mmDPCSTX5_DPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x9bfd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x9bfe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x9bff, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x9c00, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x9c00, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x9c01, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x9c01, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x9c02, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x9c02, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x9c03, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE0", REG_MMIO, 0x9c03, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x9c04, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE0", REG_MMIO, 0x9c04, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x9c05, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE0", REG_MMIO, 0x9c05, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x9c06, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE0", REG_MMIO, 0x9c06, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x9c07, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE0", REG_MMIO, 0x9c07, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x9c08, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE0", REG_MMIO, 0x9c08, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x9c09, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE0", REG_MMIO, 0x9c09, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x9c0a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE0", REG_MMIO, 0x9c0a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x9c0b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE0", REG_MMIO, 0x9c0b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x9c0c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE0", REG_MMIO, 0x9c0c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x9c0d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE0", REG_MMIO, 0x9c0d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x9c0e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE0", REG_MMIO, 0x9c0e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x9c0f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE0", REG_MMIO, 0x9c0f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x9c10, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x9c10, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x9c11, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x9c11, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x9c12, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x9c12, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x9c13, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE1", REG_MMIO, 0x9c13, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x9c14, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE1", REG_MMIO, 0x9c14, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x9c15, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE1", REG_MMIO, 0x9c15, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x9c16, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE1", REG_MMIO, 0x9c16, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x9c17, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE1", REG_MMIO, 0x9c17, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x9c18, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE1", REG_MMIO, 0x9c18, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x9c19, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE1", REG_MMIO, 0x9c19, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x9c1a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE1", REG_MMIO, 0x9c1a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x9c1b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE1", REG_MMIO, 0x9c1b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x9c1c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE1", REG_MMIO, 0x9c1c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x9c1d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE1", REG_MMIO, 0x9c1d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x9c1e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE1", REG_MMIO, 0x9c1e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x9c1f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE1", REG_MMIO, 0x9c1f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x9c20, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x9c20, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x9c21, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x9c21, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x9c22, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x9c22, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x9c23, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE2", REG_MMIO, 0x9c23, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x9c24, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE2", REG_MMIO, 0x9c24, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x9c25, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE2", REG_MMIO, 0x9c25, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x9c26, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE2", REG_MMIO, 0x9c26, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x9c27, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE2", REG_MMIO, 0x9c27, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x9c28, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE2", REG_MMIO, 0x9c28, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x9c29, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE2", REG_MMIO, 0x9c29, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x9c2a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE2", REG_MMIO, 0x9c2a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x9c2b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE2", REG_MMIO, 0x9c2b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x9c2c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE2", REG_MMIO, 0x9c2c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x9c2d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE2", REG_MMIO, 0x9c2d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x9c2e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE2", REG_MMIO, 0x9c2e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x9c2f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE2", REG_MMIO, 0x9c2f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x9c30, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x9c30, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x9c31, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x9c31, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x9c32, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x9c32, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x9c33, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU0_LANE3", REG_MMIO, 0x9c33, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x9c34, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU1_LANE3", REG_MMIO, 0x9c34, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x9c35, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU2_LANE3", REG_MMIO, 0x9c35, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x9c36, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU3_LANE3", REG_MMIO, 0x9c36, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x9c37, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU4_LANE3", REG_MMIO, 0x9c37, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x9c38, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU5_LANE3", REG_MMIO, 0x9c38, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x9c39, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU6_LANE3", REG_MMIO, 0x9c39, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x9c3a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU7_LANE3", REG_MMIO, 0x9c3a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x9c3b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU8_LANE3", REG_MMIO, 0x9c3b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x9c3c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU9_LANE3", REG_MMIO, 0x9c3c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x9c3d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU10_LANE3", REG_MMIO, 0x9c3d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x9c3e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU11_LANE3", REG_MMIO, 0x9c3e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x9c3f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS5_TX_DISP_RFU12_LANE3", REG_MMIO, 0x9c3f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x9c40, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_FREQ_CTRL0", REG_MMIO, 0x9c40, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x9c41, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_FREQ_CTRL1", REG_MMIO, 0x9c41, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x9c42, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_FREQ_CTRL2", REG_MMIO, 0x9c42, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x9c43, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_FREQ_CTRL3", REG_MMIO, 0x9c43, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x9c44, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_BW_CTRL_COARSE", REG_MMIO, 0x9c44, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x9c45, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_BW_CTRL_FINE", REG_MMIO, 0x9c45, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x9c46, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_CAL_CTRL", REG_MMIO, 0x9c46, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x9c47, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_LOOP_CTRL", REG_MMIO, 0x9c47, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x9c48, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_DEBUG0", REG_MMIO, 0x9c48, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x9c49, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_VREG_CFG", REG_MMIO, 0x9c49, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x9c4a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_OBSERVE0", REG_MMIO, 0x9c4a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x9c4b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_OBSERVE1", REG_MMIO, 0x9c4b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x9c4c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_DFT_OUT", REG_MMIO, 0x9c4c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x9c4d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x9c4e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x9c4f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x9c50, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x9c51, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x9c52, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x9c53, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x9c54, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x9c55, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x9c56, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x9c57, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x9c58, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x9c59, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x9c5a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x9c5b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x9c5c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x9c5d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x9c5e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x9c5f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x9c60, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x9c61, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x9c62, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x9c63, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x9c64, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x9c65, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x9c66, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x9c67, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x9c68, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x9c69, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x9c6a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x9c6b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x9c6c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x9c6d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x9c6e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x9c6f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x9c70, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x9c71, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x9c72, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x9c73, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x9c74, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x9c75, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x9c76, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x9c77, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x9c78, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x9c79, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x9c7a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x9c7b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x9c7c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x9c7d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x9c7e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL1", REG_MMIO, 0x9c7e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x9c7f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS5_PLL_WRAP_CNTRL", REG_MMIO, 0x9c7f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x9c80, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x9c81, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x9c82, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x9c83, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x9c84, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_LANE_PWRMGMT", REG_MMIO, 0x9c84, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x9c85, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_TXCNTRL", REG_MMIO, 0x9c85, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x9c86, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_TMDP", REG_MMIO, 0x9c86, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x9c87, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_LANE_RESETS", REG_MMIO, 0x9c87, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x9c88, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x9c88, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x9c89, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU1", REG_MMIO, 0x9c89, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x9c8a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU2", REG_MMIO, 0x9c8a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x9c8b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU3", REG_MMIO, 0x9c8b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x9c8c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU4", REG_MMIO, 0x9c8c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x9c8d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU5", REG_MMIO, 0x9c8d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x9c8e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU6", REG_MMIO, 0x9c8e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x9c8f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS6_COMMON_DISP_RFU7", REG_MMIO, 0x9c8f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x9c90, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_PHY_CNTL", REG_MMIO, 0x9c90, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x9c91, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_TX_CLOCK_CNTL", REG_MMIO, 0x9c91, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x9c92, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x9c93, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_TX_CNTL", REG_MMIO, 0x9c93, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x9c94, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x9c95, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_CBUS_CNTL", REG_MMIO, 0x9c95, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x9c96, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x9c96, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x9c97, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x9c97, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x9c98, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x9c98, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x9c99, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x9c99, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x9c9a, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x9c9a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x9c9b, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x9c9b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x9c9c, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_DEBUG_CONFIG", REG_MMIO, 0x9c9c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x9c9d, NULL, 0, 0, 0 },
+	{ "mmDPCSTX6_DPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x9c9d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x9c9e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x9c9f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x9ca0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x9ca0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x9ca1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x9ca1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x9ca2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x9ca2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x9ca3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE0", REG_MMIO, 0x9ca3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x9ca4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE0", REG_MMIO, 0x9ca4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x9ca5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE0", REG_MMIO, 0x9ca5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x9ca6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE0", REG_MMIO, 0x9ca6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x9ca7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE0", REG_MMIO, 0x9ca7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x9ca8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE0", REG_MMIO, 0x9ca8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x9ca9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE0", REG_MMIO, 0x9ca9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x9caa, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE0", REG_MMIO, 0x9caa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x9cab, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE0", REG_MMIO, 0x9cab, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x9cac, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE0", REG_MMIO, 0x9cac, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x9cad, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE0", REG_MMIO, 0x9cad, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x9cae, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE0", REG_MMIO, 0x9cae, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x9caf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE0", REG_MMIO, 0x9caf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x9cb0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x9cb0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x9cb1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x9cb1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x9cb2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x9cb2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x9cb3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE1", REG_MMIO, 0x9cb3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x9cb4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE1", REG_MMIO, 0x9cb4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x9cb5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE1", REG_MMIO, 0x9cb5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x9cb6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE1", REG_MMIO, 0x9cb6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x9cb7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE1", REG_MMIO, 0x9cb7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x9cb8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE1", REG_MMIO, 0x9cb8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x9cb9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE1", REG_MMIO, 0x9cb9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x9cba, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE1", REG_MMIO, 0x9cba, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x9cbb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE1", REG_MMIO, 0x9cbb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x9cbc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE1", REG_MMIO, 0x9cbc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x9cbd, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE1", REG_MMIO, 0x9cbd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x9cbe, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE1", REG_MMIO, 0x9cbe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x9cbf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE1", REG_MMIO, 0x9cbf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x9cc0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x9cc0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x9cc1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x9cc1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x9cc2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x9cc2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x9cc3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE2", REG_MMIO, 0x9cc3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x9cc4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE2", REG_MMIO, 0x9cc4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x9cc5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE2", REG_MMIO, 0x9cc5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x9cc6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE2", REG_MMIO, 0x9cc6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x9cc7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE2", REG_MMIO, 0x9cc7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x9cc8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE2", REG_MMIO, 0x9cc8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x9cc9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE2", REG_MMIO, 0x9cc9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x9cca, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE2", REG_MMIO, 0x9cca, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x9ccb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE2", REG_MMIO, 0x9ccb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x9ccc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE2", REG_MMIO, 0x9ccc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x9ccd, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE2", REG_MMIO, 0x9ccd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x9cce, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE2", REG_MMIO, 0x9cce, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x9ccf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE2", REG_MMIO, 0x9ccf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x9cd0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x9cd0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x9cd1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x9cd1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x9cd2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x9cd2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x9cd3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU0_LANE3", REG_MMIO, 0x9cd3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x9cd4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU1_LANE3", REG_MMIO, 0x9cd4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x9cd5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU2_LANE3", REG_MMIO, 0x9cd5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x9cd6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU3_LANE3", REG_MMIO, 0x9cd6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x9cd7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU4_LANE3", REG_MMIO, 0x9cd7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x9cd8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU5_LANE3", REG_MMIO, 0x9cd8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x9cd9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU6_LANE3", REG_MMIO, 0x9cd9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x9cda, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU7_LANE3", REG_MMIO, 0x9cda, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x9cdb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU8_LANE3", REG_MMIO, 0x9cdb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x9cdc, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU9_LANE3", REG_MMIO, 0x9cdc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x9cdd, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU10_LANE3", REG_MMIO, 0x9cdd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x9cde, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU11_LANE3", REG_MMIO, 0x9cde, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x9cdf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS6_TX_DISP_RFU12_LANE3", REG_MMIO, 0x9cdf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x9ce0, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_FREQ_CTRL0", REG_MMIO, 0x9ce0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x9ce1, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_FREQ_CTRL1", REG_MMIO, 0x9ce1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x9ce2, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_FREQ_CTRL2", REG_MMIO, 0x9ce2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x9ce3, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_FREQ_CTRL3", REG_MMIO, 0x9ce3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x9ce4, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_BW_CTRL_COARSE", REG_MMIO, 0x9ce4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x9ce5, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_BW_CTRL_FINE", REG_MMIO, 0x9ce5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x9ce6, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_CAL_CTRL", REG_MMIO, 0x9ce6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x9ce7, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_LOOP_CTRL", REG_MMIO, 0x9ce7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x9ce8, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_DEBUG0", REG_MMIO, 0x9ce8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x9ce9, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_VREG_CFG", REG_MMIO, 0x9ce9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x9cea, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_OBSERVE0", REG_MMIO, 0x9cea, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x9ceb, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_OBSERVE1", REG_MMIO, 0x9ceb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x9cec, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_DFT_OUT", REG_MMIO, 0x9cec, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x9ced, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x9cee, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x9cef, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x9cf0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x9cf1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x9cf2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x9cf3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x9cf4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x9cf5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x9cf6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x9cf7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x9cf8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x9cf9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x9cfa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x9cfb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x9cfc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x9cfd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x9cfe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x9cff, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x9d00, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x9d01, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x9d02, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x9d03, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x9d04, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x9d05, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x9d06, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x9d07, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x9d08, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x9d09, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x9d0a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x9d0b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x9d0c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x9d0d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x9d0e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x9d0f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x9d10, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x9d11, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x9d12, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x9d13, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x9d14, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x9d15, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x9d16, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x9d17, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x9d18, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x9d19, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x9d1a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x9d1b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x9d1c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x9d1d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x9d1e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL1", REG_MMIO, 0x9d1e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x9d1f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS6_PLL_WRAP_CNTRL", REG_MMIO, 0x9d1f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED0", REG_MMIO, 0x9d20, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED1", REG_MMIO, 0x9d21, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED2", REG_MMIO, 0x9d22, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED3", REG_MMIO, 0x9d23, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED4", REG_MMIO, 0x9d24, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_LANE_PWRMGMT", REG_MMIO, 0x9d24, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED5", REG_MMIO, 0x9d25, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_TXCNTRL", REG_MMIO, 0x9d25, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED6", REG_MMIO, 0x9d26, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_TMDP", REG_MMIO, 0x9d26, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED7", REG_MMIO, 0x9d27, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_LANE_RESETS", REG_MMIO, 0x9d27, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED8", REG_MMIO, 0x9d28, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_ZCALCODE_CTRL", REG_MMIO, 0x9d28, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED9", REG_MMIO, 0x9d29, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU1", REG_MMIO, 0x9d29, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED10", REG_MMIO, 0x9d2a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU2", REG_MMIO, 0x9d2a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED11", REG_MMIO, 0x9d2b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU3", REG_MMIO, 0x9d2b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED12", REG_MMIO, 0x9d2c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU4", REG_MMIO, 0x9d2c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED13", REG_MMIO, 0x9d2d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU5", REG_MMIO, 0x9d2d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED14", REG_MMIO, 0x9d2e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU6", REG_MMIO, 0x9d2e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED15", REG_MMIO, 0x9d2f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYCMREGS7_COMMON_DISP_RFU7", REG_MMIO, 0x9d2f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED16", REG_MMIO, 0x9d30, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_PHY_CNTL", REG_MMIO, 0x9d30, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED17", REG_MMIO, 0x9d31, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_TX_CLOCK_CNTL", REG_MMIO, 0x9d31, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED18", REG_MMIO, 0x9d32, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED19", REG_MMIO, 0x9d33, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_TX_CNTL", REG_MMIO, 0x9d33, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED20", REG_MMIO, 0x9d34, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED21", REG_MMIO, 0x9d35, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_CBUS_CNTL", REG_MMIO, 0x9d35, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED22", REG_MMIO, 0x9d36, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_REG_ERROR_STATUS", REG_MMIO, 0x9d36, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED23", REG_MMIO, 0x9d37, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_TX_ERROR_STATUS", REG_MMIO, 0x9d37, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED24", REG_MMIO, 0x9d38, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_PLL_UPDATE_ADDR", REG_MMIO, 0x9d38, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED25", REG_MMIO, 0x9d39, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_PLL_UPDATE_DATA", REG_MMIO, 0x9d39, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED26", REG_MMIO, 0x9d3a, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_INDEX_MODE_ADDR", REG_MMIO, 0x9d3a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED27", REG_MMIO, 0x9d3b, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_INDEX_MODE_DATA", REG_MMIO, 0x9d3b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED28", REG_MMIO, 0x9d3c, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_DEBUG_CONFIG", REG_MMIO, 0x9d3c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED29", REG_MMIO, 0x9d3d, NULL, 0, 0, 0 },
+	{ "mmDPCSTX7_DPCSTX_TEST_DEBUG_DATA", REG_MMIO, 0x9d3d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED30", REG_MMIO, 0x9d3e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED31", REG_MMIO, 0x9d3f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE0", REG_MMIO, 0x9d40, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED32", REG_MMIO, 0x9d40, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED33", REG_MMIO, 0x9d41, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE0", REG_MMIO, 0x9d41, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE0", REG_MMIO, 0x9d42, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED34", REG_MMIO, 0x9d42, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED35", REG_MMIO, 0x9d43, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE0", REG_MMIO, 0x9d43, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED36", REG_MMIO, 0x9d44, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE0", REG_MMIO, 0x9d44, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED37", REG_MMIO, 0x9d45, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE0", REG_MMIO, 0x9d45, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED38", REG_MMIO, 0x9d46, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE0", REG_MMIO, 0x9d46, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED39", REG_MMIO, 0x9d47, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE0", REG_MMIO, 0x9d47, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED40", REG_MMIO, 0x9d48, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE0", REG_MMIO, 0x9d48, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED41", REG_MMIO, 0x9d49, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE0", REG_MMIO, 0x9d49, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED42", REG_MMIO, 0x9d4a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE0", REG_MMIO, 0x9d4a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED43", REG_MMIO, 0x9d4b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE0", REG_MMIO, 0x9d4b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED44", REG_MMIO, 0x9d4c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE0", REG_MMIO, 0x9d4c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED45", REG_MMIO, 0x9d4d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE0", REG_MMIO, 0x9d4d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED46", REG_MMIO, 0x9d4e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE0", REG_MMIO, 0x9d4e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED47", REG_MMIO, 0x9d4f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE0", REG_MMIO, 0x9d4f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE1", REG_MMIO, 0x9d50, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED48", REG_MMIO, 0x9d50, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED49", REG_MMIO, 0x9d51, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE1", REG_MMIO, 0x9d51, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE1", REG_MMIO, 0x9d52, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED50", REG_MMIO, 0x9d52, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED51", REG_MMIO, 0x9d53, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE1", REG_MMIO, 0x9d53, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED52", REG_MMIO, 0x9d54, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE1", REG_MMIO, 0x9d54, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED53", REG_MMIO, 0x9d55, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE1", REG_MMIO, 0x9d55, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED54", REG_MMIO, 0x9d56, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE1", REG_MMIO, 0x9d56, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED55", REG_MMIO, 0x9d57, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE1", REG_MMIO, 0x9d57, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED56", REG_MMIO, 0x9d58, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE1", REG_MMIO, 0x9d58, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED57", REG_MMIO, 0x9d59, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE1", REG_MMIO, 0x9d59, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED58", REG_MMIO, 0x9d5a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE1", REG_MMIO, 0x9d5a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED59", REG_MMIO, 0x9d5b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE1", REG_MMIO, 0x9d5b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED60", REG_MMIO, 0x9d5c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE1", REG_MMIO, 0x9d5c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED61", REG_MMIO, 0x9d5d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE1", REG_MMIO, 0x9d5d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED62", REG_MMIO, 0x9d5e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE1", REG_MMIO, 0x9d5e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED63", REG_MMIO, 0x9d5f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE1", REG_MMIO, 0x9d5f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE2", REG_MMIO, 0x9d60, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED64", REG_MMIO, 0x9d60, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED65", REG_MMIO, 0x9d61, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE2", REG_MMIO, 0x9d61, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE2", REG_MMIO, 0x9d62, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED66", REG_MMIO, 0x9d62, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED67", REG_MMIO, 0x9d63, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE2", REG_MMIO, 0x9d63, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED68", REG_MMIO, 0x9d64, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE2", REG_MMIO, 0x9d64, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED69", REG_MMIO, 0x9d65, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE2", REG_MMIO, 0x9d65, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED70", REG_MMIO, 0x9d66, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE2", REG_MMIO, 0x9d66, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED71", REG_MMIO, 0x9d67, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE2", REG_MMIO, 0x9d67, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED72", REG_MMIO, 0x9d68, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE2", REG_MMIO, 0x9d68, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED73", REG_MMIO, 0x9d69, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE2", REG_MMIO, 0x9d69, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED74", REG_MMIO, 0x9d6a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE2", REG_MMIO, 0x9d6a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED75", REG_MMIO, 0x9d6b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE2", REG_MMIO, 0x9d6b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED76", REG_MMIO, 0x9d6c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE2", REG_MMIO, 0x9d6c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED77", REG_MMIO, 0x9d6d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE2", REG_MMIO, 0x9d6d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED78", REG_MMIO, 0x9d6e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE2", REG_MMIO, 0x9d6e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED79", REG_MMIO, 0x9d6f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE2", REG_MMIO, 0x9d6f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_CMD_BUS_TX_CONTROL_LANE3", REG_MMIO, 0x9d70, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED80", REG_MMIO, 0x9d70, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED81", REG_MMIO, 0x9d71, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_MARGIN_DEEMPH_LANE3", REG_MMIO, 0x9d71, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_CMD_BUS_GLOBAL_FOR_TX_LANE3", REG_MMIO, 0x9d72, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED82", REG_MMIO, 0x9d72, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED83", REG_MMIO, 0x9d73, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU0_LANE3", REG_MMIO, 0x9d73, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED84", REG_MMIO, 0x9d74, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU1_LANE3", REG_MMIO, 0x9d74, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED85", REG_MMIO, 0x9d75, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU2_LANE3", REG_MMIO, 0x9d75, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED86", REG_MMIO, 0x9d76, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU3_LANE3", REG_MMIO, 0x9d76, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED87", REG_MMIO, 0x9d77, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU4_LANE3", REG_MMIO, 0x9d77, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED88", REG_MMIO, 0x9d78, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU5_LANE3", REG_MMIO, 0x9d78, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED89", REG_MMIO, 0x9d79, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU6_LANE3", REG_MMIO, 0x9d79, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED90", REG_MMIO, 0x9d7a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU7_LANE3", REG_MMIO, 0x9d7a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED91", REG_MMIO, 0x9d7b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU8_LANE3", REG_MMIO, 0x9d7b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED92", REG_MMIO, 0x9d7c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU9_LANE3", REG_MMIO, 0x9d7c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED93", REG_MMIO, 0x9d7d, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU10_LANE3", REG_MMIO, 0x9d7d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED94", REG_MMIO, 0x9d7e, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU11_LANE3", REG_MMIO, 0x9d7e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED95", REG_MMIO, 0x9d7f, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYTXREGS7_TX_DISP_RFU12_LANE3", REG_MMIO, 0x9d7f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED96", REG_MMIO, 0x9d80, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_FREQ_CTRL0", REG_MMIO, 0x9d80, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED97", REG_MMIO, 0x9d81, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_FREQ_CTRL1", REG_MMIO, 0x9d81, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED98", REG_MMIO, 0x9d82, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_FREQ_CTRL2", REG_MMIO, 0x9d82, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED99", REG_MMIO, 0x9d83, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_FREQ_CTRL3", REG_MMIO, 0x9d83, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED100", REG_MMIO, 0x9d84, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_BW_CTRL_COARSE", REG_MMIO, 0x9d84, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED101", REG_MMIO, 0x9d85, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_BW_CTRL_FINE", REG_MMIO, 0x9d85, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED102", REG_MMIO, 0x9d86, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_CAL_CTRL", REG_MMIO, 0x9d86, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED103", REG_MMIO, 0x9d87, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_LOOP_CTRL", REG_MMIO, 0x9d87, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED104", REG_MMIO, 0x9d88, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_DEBUG0", REG_MMIO, 0x9d88, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED105", REG_MMIO, 0x9d89, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_VREG_CFG", REG_MMIO, 0x9d89, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED106", REG_MMIO, 0x9d8a, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_OBSERVE0", REG_MMIO, 0x9d8a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED107", REG_MMIO, 0x9d8b, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_OBSERVE1", REG_MMIO, 0x9d8b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED108", REG_MMIO, 0x9d8c, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_DFT_OUT", REG_MMIO, 0x9d8c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED109", REG_MMIO, 0x9d8d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED110", REG_MMIO, 0x9d8e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED111", REG_MMIO, 0x9d8f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED112", REG_MMIO, 0x9d90, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED113", REG_MMIO, 0x9d91, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED114", REG_MMIO, 0x9d92, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED115", REG_MMIO, 0x9d93, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED116", REG_MMIO, 0x9d94, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED117", REG_MMIO, 0x9d95, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED118", REG_MMIO, 0x9d96, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED119", REG_MMIO, 0x9d97, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED120", REG_MMIO, 0x9d98, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED121", REG_MMIO, 0x9d99, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED122", REG_MMIO, 0x9d9a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED123", REG_MMIO, 0x9d9b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED124", REG_MMIO, 0x9d9c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED125", REG_MMIO, 0x9d9d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED126", REG_MMIO, 0x9d9e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED127", REG_MMIO, 0x9d9f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED128", REG_MMIO, 0x9da0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED129", REG_MMIO, 0x9da1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED130", REG_MMIO, 0x9da2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED131", REG_MMIO, 0x9da3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED132", REG_MMIO, 0x9da4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED133", REG_MMIO, 0x9da5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED134", REG_MMIO, 0x9da6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED135", REG_MMIO, 0x9da7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED136", REG_MMIO, 0x9da8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED137", REG_MMIO, 0x9da9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED138", REG_MMIO, 0x9daa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED139", REG_MMIO, 0x9dab, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED140", REG_MMIO, 0x9dac, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED141", REG_MMIO, 0x9dad, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED142", REG_MMIO, 0x9dae, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED143", REG_MMIO, 0x9daf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED144", REG_MMIO, 0x9db0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED145", REG_MMIO, 0x9db1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED146", REG_MMIO, 0x9db2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED147", REG_MMIO, 0x9db3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED148", REG_MMIO, 0x9db4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED149", REG_MMIO, 0x9db5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED150", REG_MMIO, 0x9db6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED151", REG_MMIO, 0x9db7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED152", REG_MMIO, 0x9db8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED153", REG_MMIO, 0x9db9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED154", REG_MMIO, 0x9dba, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED155", REG_MMIO, 0x9dbb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED156", REG_MMIO, 0x9dbc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED157", REG_MMIO, 0x9dbd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED158", REG_MMIO, 0x9dbe, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL1", REG_MMIO, 0x9dbe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY7_UNIPHY_MACRO_CNTL_RESERVED159", REG_MMIO, 0x9dbf, NULL, 0, 0, 0 },
+	{ "mmDC_COMBOPHYPLLREGS7_PLL_WRAP_CNTRL", REG_MMIO, 0x9dbf, NULL, 0, 0, 0 },
+	{ "mmCOMP_EN_CTL", REG_MMIO, 0x9dc0, &mmCOMP_EN_CTL[0], sizeof(mmCOMP_EN_CTL)/sizeof(mmCOMP_EN_CTL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG", REG_SMC, 0xa, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[0]), 0, 0 },
+	{ "ixDMIF_DEBUG02_CORE1", REG_SMC, 0xa, &ixDMIF_DEBUG02_CORE1[0], sizeof(ixDMIF_DEBUG02_CORE1)/sizeof(ixDMIF_DEBUG02_CORE1[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR9", REG_SMC, 0xa, &ixAUDIO_DESCRIPTOR9[0], sizeof(ixAUDIO_DESCRIPTOR9)/sizeof(ixAUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "ixDCIO_DEBUGA", REG_SMC, 0xa, &ixDCIO_DEBUGA[0], sizeof(ixDCIO_DEBUGA)/sizeof(ixDCIO_DEBUGA[0]), 0, 0 },
+	{ "ixATTR0A", REG_SMC, 0xa, &ixATTR0A[0], sizeof(ixATTR0A)/sizeof(ixATTR0A[0]), 0, 0 },
+	{ "ixCRT0A", REG_SMC, 0xa, &ixCRT0A[0], sizeof(ixCRT0A)/sizeof(ixCRT0A[0]), 0, 0 },
+	{ "ixIDDCCIF04_DBG_DCCIF_E", REG_SMC, 0xb, &ixIDDCCIF04_DBG_DCCIF_E[0], sizeof(ixIDDCCIF04_DBG_DCCIF_E)/sizeof(ixIDDCCIF04_DBG_DCCIF_E[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR10", REG_SMC, 0xb, &ixAUDIO_DESCRIPTOR10[0], sizeof(ixAUDIO_DESCRIPTOR10)/sizeof(ixAUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION6", REG_SMC, 0xb, &ixSINK_DESCRIPTION6[0], sizeof(ixSINK_DESCRIPTION6)/sizeof(ixSINK_DESCRIPTION6[0]), 0, 0 },
+	{ "ixDCIO_DEBUGB", REG_SMC, 0xb, &ixDCIO_DEBUGB[0], sizeof(ixDCIO_DEBUGB)/sizeof(ixDCIO_DEBUGB[0]), 0, 0 },
+	{ "ixATTR0B", REG_SMC, 0xb, &ixATTR0B[0], sizeof(ixATTR0B)/sizeof(ixATTR0B[0]), 0, 0 },
+	{ "ixCRT0B", REG_SMC, 0xb, &ixCRT0B[0], sizeof(ixCRT0B)/sizeof(ixCRT0B[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0xc, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 },
+	{ "ixIDDCCIF05_DBG_DCCIF_F", REG_SMC, 0xc, &ixIDDCCIF05_DBG_DCCIF_F[0], sizeof(ixIDDCCIF05_DBG_DCCIF_F)/sizeof(ixIDDCCIF05_DBG_DCCIF_F[0]), 0, 0 },
+	{ "mmWALL_CLOCK_COUNTER", REG_MMIO, 0xc, &mmWALL_CLOCK_COUNTER[0], sizeof(mmWALL_CLOCK_COUNTER)/sizeof(mmWALL_CLOCK_COUNTER[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION7", REG_SMC, 0xc, &ixSINK_DESCRIPTION7[0], sizeof(ixSINK_DESCRIPTION7)/sizeof(ixSINK_DESCRIPTION7[0]), 0, 0 },
+	{ "ixMVP_DEBUG_12", REG_SMC, 0xc, &ixMVP_DEBUG_12[0], sizeof(ixMVP_DEBUG_12)/sizeof(ixMVP_DEBUG_12[0]), 0, 0 },
+	{ "ixDCIO_DEBUGC", REG_SMC, 0xc, &ixDCIO_DEBUGC[0], sizeof(ixDCIO_DEBUGC)/sizeof(ixDCIO_DEBUGC[0]), 0, 0 },
+	{ "ixATTR0C", REG_SMC, 0xc, &ixATTR0C[0], sizeof(ixATTR0C)/sizeof(ixATTR0C[0]), 0, 0 },
+	{ "ixCRT0C", REG_SMC, 0xc, &ixCRT0C[0], sizeof(ixCRT0C)/sizeof(ixCRT0C[0]), 0, 0 },
+	{ "mmVGA_RENDER_CONTROL", REG_MMIO, 0xc0, &mmVGA_RENDER_CONTROL[0], sizeof(mmVGA_RENDER_CONTROL)/sizeof(mmVGA_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SEQUENCER_RESET_CONTROL", REG_MMIO, 0xc1, &mmVGA_SEQUENCER_RESET_CONTROL[0], sizeof(mmVGA_SEQUENCER_RESET_CONTROL)/sizeof(mmVGA_SEQUENCER_RESET_CONTROL[0]), 0, 0 },
+	{ "mmVGA_MODE_CONTROL", REG_MMIO, 0xc2, &mmVGA_MODE_CONTROL[0], sizeof(mmVGA_MODE_CONTROL)/sizeof(mmVGA_MODE_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SURFACE_PITCH_SELECT", REG_MMIO, 0xc3, &mmVGA_SURFACE_PITCH_SELECT[0], sizeof(mmVGA_SURFACE_PITCH_SELECT)/sizeof(mmVGA_SURFACE_PITCH_SELECT[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS", REG_MMIO, 0xc4, &mmVGA_MEMORY_BASE_ADDRESS[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS)/sizeof(mmVGA_MEMORY_BASE_ADDRESS[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_INDEX", REG_MMIO, 0xc5, &mmVGA_TEST_DEBUG_INDEX[0], sizeof(mmVGA_TEST_DEBUG_INDEX)/sizeof(mmVGA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmVGA_DISPBUF1_SURFACE_ADDR", REG_MMIO, 0xc6, &mmVGA_DISPBUF1_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF1_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF1_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_DATA", REG_MMIO, 0xc7, &mmVGA_TEST_DEBUG_DATA[0], sizeof(mmVGA_TEST_DEBUG_DATA)/sizeof(mmVGA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGA_DISPBUF2_SURFACE_ADDR", REG_MMIO, 0xc8, &mmVGA_DISPBUF2_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF2_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF2_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS_HIGH", REG_MMIO, 0xc9, &mmVGA_MEMORY_BASE_ADDRESS_HIGH[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH)/sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmVGA_HDP_CONTROL", REG_MMIO, 0xca, &mmVGA_HDP_CONTROL[0], sizeof(mmVGA_HDP_CONTROL)/sizeof(mmVGA_HDP_CONTROL[0]), 0, 0 },
+	{ "mmVGA_CACHE_CONTROL", REG_MMIO, 0xcb, &mmVGA_CACHE_CONTROL[0], sizeof(mmVGA_CACHE_CONTROL)/sizeof(mmVGA_CACHE_CONTROL[0]), 0, 0 },
+	{ "mmD1VGA_CONTROL", REG_MMIO, 0xcc, &mmD1VGA_CONTROL[0], sizeof(mmD1VGA_CONTROL)/sizeof(mmD1VGA_CONTROL[0]), 0, 0 },
+	{ "mmD2VGA_CONTROL", REG_MMIO, 0xce, &mmD2VGA_CONTROL[0], sizeof(mmD2VGA_CONTROL)/sizeof(mmD2VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_HW_DEBUG", REG_MMIO, 0xcf, &mmVGA_HW_DEBUG[0], sizeof(mmVGA_HW_DEBUG)/sizeof(mmVGA_HW_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0xd, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR12", REG_SMC, 0xd, &ixAUDIO_DESCRIPTOR12[0], sizeof(ixAUDIO_DESCRIPTOR12)/sizeof(ixAUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION8", REG_SMC, 0xd, &ixSINK_DESCRIPTION8[0], sizeof(ixSINK_DESCRIPTION8)/sizeof(ixSINK_DESCRIPTION8[0]), 0, 0 },
+	{ "ixMVP_DEBUG_13", REG_SMC, 0xd, &ixMVP_DEBUG_13[0], sizeof(ixMVP_DEBUG_13)/sizeof(ixMVP_DEBUG_13[0]), 0, 0 },
+	{ "ixDCIO_DEBUGD", REG_SMC, 0xd, &ixDCIO_DEBUGD[0], sizeof(ixDCIO_DEBUGD)/sizeof(ixDCIO_DEBUGD[0]), 0, 0 },
+	{ "ixATTR0D", REG_SMC, 0xd, &ixATTR0D[0], sizeof(ixATTR0D)/sizeof(ixATTR0D[0]), 0, 0 },
+	{ "ixCRT0D", REG_SMC, 0xd, &ixCRT0D[0], sizeof(ixCRT0D)/sizeof(ixCRT0D[0]), 0, 0 },
+	{ "mmVGA_STATUS", REG_MMIO, 0xd0, &mmVGA_STATUS[0], sizeof(mmVGA_STATUS)/sizeof(mmVGA_STATUS[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_CONTROL", REG_MMIO, 0xd1, &mmVGA_INTERRUPT_CONTROL[0], sizeof(mmVGA_INTERRUPT_CONTROL)/sizeof(mmVGA_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmVGA_STATUS_CLEAR", REG_MMIO, 0xd2, &mmVGA_STATUS_CLEAR[0], sizeof(mmVGA_STATUS_CLEAR)/sizeof(mmVGA_STATUS_CLEAR[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_STATUS", REG_MMIO, 0xd3, &mmVGA_INTERRUPT_STATUS[0], sizeof(mmVGA_INTERRUPT_STATUS)/sizeof(mmVGA_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmVGA_MAIN_CONTROL", REG_MMIO, 0xd4, &mmVGA_MAIN_CONTROL[0], sizeof(mmVGA_MAIN_CONTROL)/sizeof(mmVGA_MAIN_CONTROL[0]), 0, 0 },
+	{ "mmVGA_TEST_CONTROL", REG_MMIO, 0xd5, &mmVGA_TEST_CONTROL[0], sizeof(mmVGA_TEST_CONTROL)/sizeof(mmVGA_TEST_CONTROL[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_INDEX", REG_MMIO, 0xd6, &mmVGA_DEBUG_READBACK_INDEX[0], sizeof(mmVGA_DEBUG_READBACK_INDEX)/sizeof(mmVGA_DEBUG_READBACK_INDEX[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_DATA", REG_MMIO, 0xd7, &mmVGA_DEBUG_READBACK_DATA[0], sizeof(mmVGA_DEBUG_READBACK_DATA)/sizeof(mmVGA_DEBUG_READBACK_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0xe, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 },
+	{ "mmSTREAM_SYNCHRONIZATION", REG_MMIO, 0xe, &mmSTREAM_SYNCHRONIZATION[0], sizeof(mmSTREAM_SYNCHRONIZATION)/sizeof(mmSTREAM_SYNCHRONIZATION[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR13", REG_SMC, 0xe, &ixAUDIO_DESCRIPTOR13[0], sizeof(ixAUDIO_DESCRIPTOR13)/sizeof(ixAUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION9", REG_SMC, 0xe, &ixSINK_DESCRIPTION9[0], sizeof(ixSINK_DESCRIPTION9)/sizeof(ixSINK_DESCRIPTION9[0]), 0, 0 },
+	{ "ixMVP_DEBUG_14", REG_SMC, 0xe, &ixMVP_DEBUG_14[0], sizeof(ixMVP_DEBUG_14)/sizeof(ixMVP_DEBUG_14[0]), 0, 0 },
+	{ "ixDCIO_DEBUGE", REG_SMC, 0xe, &ixDCIO_DEBUGE[0], sizeof(ixDCIO_DEBUGE)/sizeof(ixDCIO_DEBUGE[0]), 0, 0 },
+	{ "ixATTR0E", REG_SMC, 0xe, &ixATTR0E[0], sizeof(ixATTR0E)/sizeof(ixATTR0E[0]), 0, 0 },
+	{ "ixCRT0E", REG_SMC, 0xe, &ixCRT0E[0], sizeof(ixCRT0E)/sizeof(ixCRT0E[0]), 0, 0 },
+	{ "mmVGA0_CRTC8_DATA", REG_MMIO, 0xed, NULL, 0, 0, 0 },
+	{ "mmVGA0_CRTC8_IDX", REG_MMIO, 0xed, NULL, 0, 0, 0 },
+	{ "mmCRTC8_DATA", REG_MMIO, 0xed, &mmCRTC8_DATA[0], sizeof(mmCRTC8_DATA)/sizeof(mmCRTC8_DATA[0]), 0, 0 },
+	{ "mmCRTC8_IDX", REG_MMIO, 0xed, &mmCRTC8_IDX[0], sizeof(mmCRTC8_IDX)/sizeof(mmCRTC8_IDX[0]), 0, 0 },
+	{ "mmVGA0_GENFC_WT", REG_MMIO, 0xee, NULL, 0, 0, 0 },
+	{ "mmVGA0_GENS1", REG_MMIO, 0xee, NULL, 0, 0, 0 },
+	{ "mmGENFC_WT", REG_MMIO, 0xee, &mmGENFC_WT[0], sizeof(mmGENFC_WT)/sizeof(mmGENFC_WT[0]), 0, 0 },
+	{ "mmGENS1", REG_MMIO, 0xee, &mmGENS1[0], sizeof(mmGENS1)/sizeof(mmGENS1[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION10", REG_SMC, 0xf, &ixSINK_DESCRIPTION10[0], sizeof(ixSINK_DESCRIPTION10)/sizeof(ixSINK_DESCRIPTION10[0]), 0, 0 },
+	{ "ixMVP_DEBUG_15", REG_SMC, 0xf, &ixMVP_DEBUG_15[0], sizeof(ixMVP_DEBUG_15)/sizeof(ixMVP_DEBUG_15[0]), 0, 0 },
+	{ "ixDCIO_DEBUGF", REG_SMC, 0xf, &ixDCIO_DEBUGF[0], sizeof(ixDCIO_DEBUGF)/sizeof(ixDCIO_DEBUGF[0]), 0, 0 },
+	{ "ixATTR0F", REG_SMC, 0xf, &ixATTR0F[0], sizeof(ixATTR0F)/sizeof(ixATTR0F[0]), 0, 0 },
+	{ "ixCRT0F", REG_SMC, 0xf, &ixCRT0F[0], sizeof(ixCRT0F)/sizeof(ixCRT0F[0]), 0, 0 },
+	{ "mmGENMO_WT", REG_MMIO, 0xf0, &mmGENMO_WT[0], sizeof(mmGENMO_WT)/sizeof(mmGENMO_WT[0]), 0, 0 },
+	{ "mmGENENB", REG_MMIO, 0xf0, &mmGENENB[0], sizeof(mmGENENB)/sizeof(mmGENENB[0]), 0, 0 },
+	{ "mmGENS0", REG_MMIO, 0xf0, &mmGENS0[0], sizeof(mmGENS0)/sizeof(mmGENS0[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_SMC, 0xf00, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID", REG_SMC, 0xf02, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0xf04, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "mmDAC_R_INDEX", REG_MMIO, 0xf1, &mmDAC_R_INDEX[0], sizeof(mmDAC_R_INDEX)/sizeof(mmDAC_R_INDEX[0]), 0, 0 },
+	{ "mmSEQ8_DATA", REG_MMIO, 0xf1, &mmSEQ8_DATA[0], sizeof(mmSEQ8_DATA)/sizeof(mmSEQ8_DATA[0]), 0, 0 },
+	{ "mmDAC_MASK", REG_MMIO, 0xf1, &mmDAC_MASK[0], sizeof(mmDAC_MASK)/sizeof(mmDAC_MASK[0]), 0, 0 },
+	{ "mmDAC_W_INDEX", REG_MMIO, 0xf2, &mmDAC_W_INDEX[0], sizeof(mmDAC_W_INDEX)/sizeof(mmDAC_W_INDEX[0]), 0, 0 },
+	{ "mmGENFC_RD", REG_MMIO, 0xf2, &mmGENFC_RD[0], sizeof(mmGENFC_RD)/sizeof(mmGENFC_RD[0]), 0, 0 },
+	{ "mmGRPH8_DATA", REG_MMIO, 0xf3, &mmGRPH8_DATA[0], sizeof(mmGRPH8_DATA)/sizeof(mmGRPH8_DATA[0]), 0, 0 },
+	{ "mmGRPH8_IDX", REG_MMIO, 0xf3, &mmGRPH8_IDX[0], sizeof(mmGRPH8_IDX)/sizeof(mmGRPH8_IDX[0]), 0, 0 },
+	{ "mmGENMO_RD", REG_MMIO, 0xf3, &mmGENMO_RD[0], sizeof(mmGENMO_RD)/sizeof(mmGENMO_RD[0]), 0, 0 },
+	{ "mmVGA1_CRTC8_DATA", REG_MMIO, 0xf5, NULL, 0, 0, 0 },
+	{ "mmVGA1_CRTC8_IDX", REG_MMIO, 0xf5, NULL, 0, 0, 0 },
+	{ "mmVGA1_GENFC_WT", REG_MMIO, 0xf6, NULL, 0, 0, 0 },
+	{ "mmVGA1_GENS1", REG_MMIO, 0xf6, NULL, 0, 0, 0 },
+	{ "mmD3VGA_CONTROL", REG_MMIO, 0xf8, &mmD3VGA_CONTROL[0], sizeof(mmD3VGA_CONTROL)/sizeof(mmD3VGA_CONTROL[0]), 0, 0 },
+	{ "mmD4VGA_CONTROL", REG_MMIO, 0xf9, &mmD4VGA_CONTROL[0], sizeof(mmD4VGA_CONTROL)/sizeof(mmD4VGA_CONTROL[0]), 0, 0 },
+	{ "mmD5VGA_CONTROL", REG_MMIO, 0xfa, &mmD5VGA_CONTROL[0], sizeof(mmD5VGA_CONTROL)/sizeof(mmD5VGA_CONTROL[0]), 0, 0 },
+	{ "mmD6VGA_CONTROL", REG_MMIO, 0xfb, &mmD6VGA_CONTROL[0], sizeof(mmD6VGA_CONTROL)/sizeof(mmD6VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SOURCE_SELECT", REG_MMIO, 0xfc, &mmVGA_SOURCE_SELECT[0], sizeof(mmVGA_SOURCE_SELECT)/sizeof(mmVGA_SOURCE_SELECT[0]), 0, 0 },
diff --git a/src/lib/ip/dce60.c b/src/lib/ip/dce60.c
new file mode 100644
index 0000000..851b9ce
--- /dev/null
+++ b/src/lib/ip/dce60.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "dce60_bits.i"
+
+static const struct umr_reg dce60_registers[] = {
+#include "dce60_regs.i"
+};
+
+struct umr_ip_block *umr_create_dce60(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "dce60";
+	ip->no_regs = sizeof(dce60_registers)/sizeof(dce60_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(dce60_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, dce60_registers, sizeof(dce60_registers));
+	return ip;
+}
diff --git a/src/lib/ip/dce60_bits.i b/src/lib/ip/dce60_bits.i
new file mode 100644
index 0000000..50ae01e
--- /dev/null
+++ b/src/lib/ip/dce60_bits.i
@@ -0,0 +1,5167 @@
+static struct umr_bitfield ixATTR00[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR01[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR02[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR03[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR04[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR05[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR06[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR07[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR08[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR09[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0A[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0B[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0C[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0D[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0E[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0F[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR10[] = {
+	 { "ATTR_BLINK_EN", 3, 3, &umr_bitfield_default },
+	 { "ATTR_CSEL_EN", 7, 7, &umr_bitfield_default },
+	 { "ATTR_GRPH_MODE", 0, 0, &umr_bitfield_default },
+	 { "ATTR_LGRPH_EN", 2, 2, &umr_bitfield_default },
+	 { "ATTR_MONO_EN", 1, 1, &umr_bitfield_default },
+	 { "ATTR_PANTOPONLY", 5, 5, &umr_bitfield_default },
+	 { "ATTR_PCLKBY2", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR11[] = {
+	 { "ATTR_OVSC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR12[] = {
+	 { "ATTR_MAP_EN", 0, 3, &umr_bitfield_default },
+	 { "ATTR_VSMUX", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR13[] = {
+	 { "ATTR_PPAN", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR14[] = {
+	 { "ATTR_CSEL1", 0, 1, &umr_bitfield_default },
+	 { "ATTR_CSEL2", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT15[] = {
+	 { "V_BLANK_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT16[] = {
+	 { "V_BLANK_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT17[] = {
+	 { "ADDR_CNT_BY2", 3, 3, &umr_bitfield_default },
+	 { "BYTE_MODE", 6, 6, &umr_bitfield_default },
+	 { "CRTC_SYNC_EN", 7, 7, &umr_bitfield_default },
+	 { "RA0_AS_A13B", 0, 0, &umr_bitfield_default },
+	 { "RA1_AS_A14B", 1, 1, &umr_bitfield_default },
+	 { "VCOUNT_BY2", 2, 2, &umr_bitfield_default },
+	 { "WRAP_A15TOA0", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT18[] = {
+	 { "LINE_CMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1E[] = {
+	 { "GRPH_DEC_RD1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1F[] = {
+	 { "GRPH_DEC_RD0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+	 { "TAG", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
+	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_G[] = {
+	 { "DP_AUX2_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_H[] = {
+	 { "DP_AUX2_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
+	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
+	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
+	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
+	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
+	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
+	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
+	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
+	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_D[] = {
+	 { "DP_AUX4_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_E[] = {
+	 { "DP_AUX4_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_F[] = {
+	 { "DP_AUX4_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_G[] = {
+	 { "DP_AUX4_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_H[] = {
+	 { "DP_AUX4_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_I[] = {
+	 { "DP_AUX4_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
+	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
+	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_A[] = {
+	 { "DP_AUX5_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_B[] = {
+	 { "DP_AUX5_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_C[] = {
+	 { "DP_AUX5_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_D[] = {
+	 { "DP_AUX5_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_E[] = {
+	 { "DP_AUX5_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_F[] = {
+	 { "DP_AUX5_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_G[] = {
+	 { "DP_AUX5_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_H[] = {
+	 { "DP_AUX5_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_I[] = {
+	 { "DP_AUX5_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGADCC_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_A[] = {
+	 { "DP_AUX6_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_B[] = {
+	 { "DP_AUX6_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_C[] = {
+	 { "DP_AUX6_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_D[] = {
+	 { "DP_AUX6_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_E[] = {
+	 { "DP_AUX6_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_F[] = {
+	 { "DP_AUX6_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_G[] = {
+	 { "DP_AUX6_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_H[] = {
+	 { "DP_AUX6_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_I[] = {
+	 { "DP_AUX6_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_RENDER_CONTROL[] = {
+	 { "VGA_BLINK_MODE", 5, 6, &umr_bitfield_default },
+	 { "VGA_BLINK_RATE", 0, 4, &umr_bitfield_default },
+	 { "VGA_CURSOR_BLINK_INVERT", 7, 7, &umr_bitfield_default },
+	 { "VGA_EXTD_ADDR_COUNT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_LOCK_8DOT", 24, 24, &umr_bitfield_default },
+	 { "VGAREG_LINECMP_COMPATIBILITY_SEL", 25, 25, &umr_bitfield_default },
+	 { "VGA_VSTATUS_CNTL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SEQUENCER_RESET_CONTROL[] = {
+	 { "D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 0, 0, &umr_bitfield_default },
+	 { "D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 8, 8, &umr_bitfield_default },
+	 { "D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 1, 1, &umr_bitfield_default },
+	 { "D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 9, 9, &umr_bitfield_default },
+	 { "D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 2, 2, &umr_bitfield_default },
+	 { "D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 10, 10, &umr_bitfield_default },
+	 { "D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 3, 3, &umr_bitfield_default },
+	 { "D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 11, 11, &umr_bitfield_default },
+	 { "D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 4, 4, &umr_bitfield_default },
+	 { "D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 12, 12, &umr_bitfield_default },
+	 { "D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 5, 5, &umr_bitfield_default },
+	 { "D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 13, 13, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INDEX_SELECT", 18, 23, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MODE_CONTROL[] = {
+	 { "VGA_128K_APERTURE_PAGING", 8, 8, &umr_bitfield_default },
+	 { "VGA_ATI_LINEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_LUT_PALETTE_UPDATE_MODE", 4, 5, &umr_bitfield_default },
+	 { "VGA_TEXT_132_COLUMNS_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SURFACE_PITCH_SELECT[] = {
+	 { "VGA_SURFACE_HEIGHT_SELECT", 8, 9, &umr_bitfield_default },
+	 { "VGA_SURFACE_PITCH_SELECT", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_INDEX[] = {
+	 { "VGA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "VGA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF1_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF1_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_DATA[] = {
+	 { "VGA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF2_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF2_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS_HIGH[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HDP_CONTROL[] = {
+	 { "VGA_MEMORY_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "VGA_MEM_PAGE_SELECT_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_RBBM_LOCK_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RESET_CONTROL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_CACHE_CONTROL[] = {
+	 { "VGA_DCCIF_W256ONLY", 20, 20, &umr_bitfield_default },
+	 { "VGA_DCCIF_WC_TIMEOUT", 24, 29, &umr_bitfield_default },
+	 { "VGA_READ_BUFFER_INVALIDATE", 16, 16, &umr_bitfield_default },
+	 { "VGA_READ_CACHE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_WRITE_THROUGH_CACHE_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD1VGA_CONTROL[] = {
+	 { "D1VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D1VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D1VGA_ROTATE", 24, 25, &umr_bitfield_default },
+	 { "D1VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D1VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD2VGA_CONTROL[] = {
+	 { "D2VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D2VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D2VGA_ROTATE", 24, 25, &umr_bitfield_default },
+	 { "D2VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D2VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HW_DEBUG[] = {
+	 { "VGA_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS[] = {
+	 { "VGA_DISPLAY_SWITCH_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MEM_ACCESS_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_STATUS", 3, 3, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_STATUS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_CONTROL[] = {
+	 { "VGA_DISPLAY_SWITCH_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "VGA_MEM_ACCESS_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS_CLEAR[] = {
+	 { "VGA_DISPLAY_SWITCH_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "VGA_MEM_ACCESS_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_STATUS[] = {
+	 { "VGA_DISPLAY_SWITCH_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MEM_ACCESS_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_STATUS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MAIN_CONTROL[] = {
+	 { "VGA_CRTC_TIMEOUT", 0, 1, &umr_bitfield_default },
+	 { "VGA_EXTERNAL_DAC_SENSE", 29, 29, &umr_bitfield_default },
+	 { "VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT", 31, 31, &umr_bitfield_default },
+	 { "VGA_READBACK_CRT_INTR_SOURCE_SELECT", 24, 25, &umr_bitfield_default },
+	 { "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT", 16, 17, &umr_bitfield_default },
+	 { "VGA_READBACK_SENSE_SWITCH_SELECT", 26, 26, &umr_bitfield_default },
+	 { "VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT", 8, 9, &umr_bitfield_default },
+	 { "VGA_READ_URGENT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "VGA_RENDER_TIMEOUT_COUNT", 3, 4, &umr_bitfield_default },
+	 { "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION", 5, 7, &umr_bitfield_default },
+	 { "VGA_WRITES_URGENT_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_CONTROL[] = {
+	 { "VGA_TEST_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DISPBUF_SELECT", 24, 24, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DONE", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_START", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_INDEX[] = {
+	 { "VGA_DEBUG_READBACK_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_DATA[] = {
+	 { "VGA_DEBUG_READBACK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_REF_DIV[] = {
+	 { "VGA25_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_REF_DIV[] = {
+	 { "VGA28_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_REF_DIV[] = {
+	 { "VGA41_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_FB_DIV[] = {
+	 { "VGA25_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA25_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA25_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_FB_DIV[] = {
+	 { "VGA28_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA28_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA28_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_FB_DIV[] = {
+	 { "VGA41_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA41_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA41_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_POST_DIV[] = {
+	 { "VGA25_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA25_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+	 { "VGA25_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_POST_DIV[] = {
+	 { "VGA28_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA28_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+	 { "VGA28_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_POST_DIV[] = {
+	 { "VGA41_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA41_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+	 { "VGA41_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_ANALOG[] = {
+	 { "VGA25_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA25_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA25_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+	 { "VGA25_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA25_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_ANALOG[] = {
+	 { "VGA28_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA28_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA28_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+	 { "VGA28_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA28_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_ANALOG[] = {
+	 { "VGA41_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA41_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA41_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+	 { "VGA41_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA41_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_DATA[] = {
+	 { "VCRTC_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_WT[] = {
+	 { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATTRDR[] = {
+	 { "ATTR_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MASK[] = {
+	 { "DAC_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_DATA[] = {
+	 { "DAC_DATA", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_RD[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD3VGA_CONTROL[] = {
+	 { "D3VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D3VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D3VGA_ROTATE", 24, 25, &umr_bitfield_default },
+	 { "D3VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D3VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD4VGA_CONTROL[] = {
+	 { "D4VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D4VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D4VGA_ROTATE", 24, 25, &umr_bitfield_default },
+	 { "D4VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D4VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD5VGA_CONTROL[] = {
+	 { "D5VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D5VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D5VGA_ROTATE", 24, 25, &umr_bitfield_default },
+	 { "D5VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D5VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD6VGA_CONTROL[] = {
+	 { "D6VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D6VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D6VGA_ROTATE", 24, 25, &umr_bitfield_default },
+	 { "D6VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D6VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SOURCE_SELECT[] = {
+	 { "VGA_SOURCE_SEL_A", 0, 2, &umr_bitfield_default },
+	 { "VGA_SOURCE_SEL_B", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CNTL[] = {
+	 { "DCCG_GTC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_MODULO[] = {
+	 { "DCCG_GTC_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CURRENT[] = {
+	 { "DCCG_GTC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENTIST_DISPCLK_CNTL[] = {
+	 { "DENTIST_DISPCLK_CHG_DONE", 19, 19, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_MODE", 15, 16, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHGTOG", 17, 17, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_DONETOG", 18, 18, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_RDIVIDER", 8, 14, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_WDIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHG_DONE", 20, 20, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHGTOG", 21, 21, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_DONETOG", 22, 22, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_WDIVIDER", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CLK_ENABLE[] = {
+	 { "DACA_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DACB_CLK_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CLK_ENABLE[] = {
+	 { "DVO_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMILLISECOND_TIME_BASE_DIV[] = {
+	 { "MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+	 { "MILLISECOND_TIME_BASE_DIV", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_FREQ_CHANGE_CNTL[] = {
+	 { "DCCG_FIFO_ERRDET_OVR_EN", 30, 30, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_RESET", 28, 28, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_STATE", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_CHG_FWD_CORR_DISABLE", 31, 31, &umr_bitfield_default },
+	 { "DISPCLK_FREQ_RAMP_DONE", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_MAX_ERRDET_CYCLES", 25, 27, &umr_bitfield_default },
+	 { "DISPCLK_STEP_DELAY", 0, 13, &umr_bitfield_default },
+	 { "DISPCLK_STEP_SIZE", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLIGHT_SLEEP_CNTL[] = {
+	 { "LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+	 { "MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_PERFMON_CNTL[] = {
+	 { "DCCG_PERF_CRTC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCCG_PERF_DISPCLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERF_DPREFCLK_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_HSYNC", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_VSYNC", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK1_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK2_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERF_RUN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL[] = {
+	 { "DACACLK_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "DACBCLK_GATE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_DCCG_GATE_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_RAMP_DIV_ID", 24, 26, &umr_bitfield_default },
+	 { "DISPCLK_R_DCCG_GATE_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "DISPCLK_R_DCCG_RAMP_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "DVOACLK_GATE_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "PCLK_TV_GATE_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "SCLK_GATE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "SCLK_RAMP_DIV_ID", 28, 30, &umr_bitfield_default },
+	 { "SYMCLKA_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SYMCLKB_GATE_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "SYMCLKC_GATE_DISABLE", 10, 10, &umr_bitfield_default },
+	 { "SYMCLKD_GATE_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "SYMCLKE_GATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "SYMCLKF_GATE_DISABLE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "DISPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "DISPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CAC_STATUS[] = {
+	 { "CAC_STATUS_RDDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK1_RESYNC_CNTL[] = {
+	 { "DCCG_DEEP_COLOR_CNTL1", 4, 5, &umr_bitfield_default },
+	 { "PIXCLK1_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK2_RESYNC_CNTL[] = {
+	 { "DCCG_DEEP_COLOR_CNTL2", 4, 5, &umr_bitfield_default },
+	 { "PIXCLK2_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK0_RESYNC_CNTL[] = {
+	 { "DCCG_DEEP_COLOR_CNTL0", 4, 5, &umr_bitfield_default },
+	 { "PIXCLK0_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMICROSECOND_TIME_BASE_DIV[] = {
+	 { "MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+	 { "MICROSECOND_TIME_BASE_DIV", 0, 6, &umr_bitfield_default },
+	 { "XTAL_REF_CLOCK_SOURCE_SEL", 17, 17, &umr_bitfield_default },
+	 { "XTAL_REF_DIV", 8, 14, &umr_bitfield_default },
+	 { "XTAL_REF_SEL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPPLL_BG_CNTL[] = {
+	 { "DISPPLL_BG_ADJ", 4, 7, &umr_bitfield_default },
+	 { "DISPPLL_BG_PDN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_SOFT_RESET[] = {
+	 { "DIGA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DIGA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DIGB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIGB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DIGC_BE_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DIGC_FE_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DIGD_BE_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DIGD_FE_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DIGE_BE_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "DIGE_FE_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "DIGF_BE_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "DIGF_FE_SOFT_RESET", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC0_PIXEL_RATE_CNTL[] = {
+	 { "CRTC0_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC0_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC0_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO0_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_PHASE[] = {
+	 { "DP_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_MODULO[] = {
+	 { "DP_DTO0_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC1_PIXEL_RATE_CNTL[] = {
+	 { "CRTC1_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC1_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO1_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_PHASE[] = {
+	 { "DP_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_MODULO[] = {
+	 { "DP_DTO1_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC2_PIXEL_RATE_CNTL[] = {
+	 { "CRTC2_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC2_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO2_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_PHASE[] = {
+	 { "DP_DTO2_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_MODULO[] = {
+	 { "DP_DTO2_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC3_PIXEL_RATE_CNTL[] = {
+	 { "CRTC3_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC3_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO3_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_PHASE[] = {
+	 { "DP_DTO3_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_MODULO[] = {
+	 { "DP_DTO3_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC4_PIXEL_RATE_CNTL[] = {
+	 { "CRTC4_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC4_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO4_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_PHASE[] = {
+	 { "DP_DTO4_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_MODULO[] = {
+	 { "DP_DTO4_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC5_PIXEL_RATE_CNTL[] = {
+	 { "CRTC5_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC5_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO5_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_PHASE[] = {
+	 { "DP_DTO5_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_MODULO[] = {
+	 { "DP_DTO5_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE0_SOFT_RESET[] = {
+	 { "CRTC0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DCP0_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP0_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL0_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL0_SOFT_RESET", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE1_SOFT_RESET[] = {
+	 { "CRTC1_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DCP1_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP1_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL1_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL1_SOFT_RESET", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE2_SOFT_RESET[] = {
+	 { "CRTC2_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DCP2_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP2_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL2_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL2_SOFT_RESET", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE3_SOFT_RESET[] = {
+	 { "CRTC3_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DCP3_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP3_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL3_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL3_SOFT_RESET", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE4_SOFT_RESET[] = {
+	 { "CRTC4_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DCP4_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP4_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL4_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL4_SOFT_RESET", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE5_SOFT_RESET[] = {
+	 { "CRTC5_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DCP5_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP5_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL5_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL5_SOFT_RESET", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_SOFT_RESET[] = {
+	 { "DMIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DMIF1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DMIF2_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DMIF3_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "DMIF4_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DMIF5_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DMIFARB_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "FBC_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "MCIF_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "VGA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "VIP_SOFT_RESET", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_SOFT_RESET[] = {
+	 { "REFCLK_SOFT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKA_CLOCK_ENABLE[] = {
+	 { "SYMCLKA_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKB_CLOCK_ENABLE[] = {
+	 { "SYMCLKB_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKC_CLOCK_ENABLE[] = {
+	 { "SYMCLKC_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKD_CLOCK_ENABLE[] = {
+	 { "SYMCLKD_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKE_CLOCK_ENABLE[] = {
+	 { "SYMCLKE_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKF_CLOCK_ENABLE[] = {
+	 { "SYMCLKF_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_SOFT_RESET[] = {
+	 { "DSYNCA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DSYNCB_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DSYNCC_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "DSYNCD_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "DSYNCE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DSYNCF_SOFT_RESET", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SOFT_RESET[] = {
+	 { "ABM_SOFT_RESET", 25, 25, &umr_bitfield_default },
+	 { "DACA_CFG_IF_SOFT_RESET", 29, 29, &umr_bitfield_default },
+	 { "DACA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DACB_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DVO_ENABLE_RST", 3, 3, &umr_bitfield_default },
+	 { "DVO_SOFT_RESET", 27, 27, &umr_bitfield_default },
+	 { "FMT0_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "FMT1_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FMT2_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "FMT3_SOFT_RESET", 19, 19, &umr_bitfield_default },
+	 { "FMT4_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "FMT5_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "MVP_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "SOFT_RESET_DVO", 2, 2, &umr_bitfield_default },
+	 { "SRBM_SOFT_RESET_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "TVOUT_SOFT_RESET", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKD_CNTL[] = {
+	 { "DVOACLKD_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKD_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKD_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKD_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKD_IN_PHASE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKC_MVP_CNTL[] = {
+	 { "DVOACLKC_MVP_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_IN_PHASE", 18, 18, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_SKEW_PHASE_OVERRIDE", 20, 20, &umr_bitfield_default },
+	 { "MVP_CLK_A_SRC_SEL", 24, 25, &umr_bitfield_default },
+	 { "MVP_CLK_B_SRC_SEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKC_CNTL[] = {
+	 { "DVOACLKC_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKC_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKC_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKC_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKC_IN_PHASE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO_SOURCE[] = {
+	 { "DCCG_AUDIO_DTO0_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO_SEL", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_PHASE[] = {
+	 { "DCCG_AUDIO_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_MODULE[] = {
+	 { "DCCG_AUDIO_DTO0_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_PHASE[] = {
+	 { "DCCG_AUDIO_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_MODULE[] = {
+	 { "DCCG_AUDIO_DTO1_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_INDEX[] = {
+	 { "DCCG_DBG_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCCG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCCG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_DATA[] = {
+	 { "DCCG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_CLK_SEL[] = {
+	 { "DCCG_TEST_CLK_GENERICA_INV", 16, 16, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICA_SEL", 0, 7, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_INV", 24, 24, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_CONTROL[] = {
+	 { "DMIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_CHUNK_BUFF_MARGIN", 29, 30, &umr_bitfield_default },
+	 { "DMIF_DELAY_ARBITRATION", 24, 28, &umr_bitfield_default },
+	 { "DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT", 4, 4, &umr_bitfield_default },
+	 { "DMIF_FORCE_TOTAL_REQ_BURST_SIZE", 12, 15, &umr_bitfield_default },
+	 { "DMIF_GROUP_REQUESTS_IN_CHUNK", 2, 2, &umr_bitfield_default },
+	 { "DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS", 16, 21, &umr_bitfield_default },
+	 { "DMIF_REQ_BURST_SIZE", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS[] = {
+	 { "DMIF_CLEAR_MC_SEND_ON_IDLE", 8, 13, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT", 20, 22, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_URGENT_ONLY", 17, 17, &umr_bitfield_default },
+	 { "DMIF_MC_SEND_ON_IDLE", 0, 5, &umr_bitfield_default },
+	 { "DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT", 24, 26, &umr_bitfield_default },
+	 { "DMIF_UNDERFLOW", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_HW_DEBUG[] = {
+	 { "DMIF_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ARBITRATION_CONTROL[] = {
+	 { "DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "PIPE_SWITCH_EFFICIENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CALC[] = {
+	 { "ADDR_CONFIG_PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ADDR_CONFIG_ROW_SIZE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS2[] = {
+	 { "DMIF_CHUNK_TRACKER_SCLK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DMIF_FBC_TRACKER_SCLK_STATUS", 9, 9, &umr_bitfield_default },
+	 { "DMIF_PIPE0_DISPCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DMIF_PIPE1_DISPCLK_STATUS", 1, 1, &umr_bitfield_default },
+	 { "DMIF_PIPE2_DISPCLK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DMIF_PIPE3_DISPCLK_STATUS", 3, 3, &umr_bitfield_default },
+	 { "DMIF_PIPE4_DISPCLK_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DMIF_PIPE5_DISPCLK_STATUS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_INDEX[] = {
+	 { "DMIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_DATA[] = {
+	 { "DMIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_CONTROL[] = {
+	 { "ADDRESS_TRANSLATION_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "LOW_READ_URG_LEVEL", 16, 23, &umr_bitfield_default },
+	 { "MC_CLEAN_DEASSERT_LATENCY", 24, 29, &umr_bitfield_default },
+	 { "MCIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_URGENT_ONLY", 31, 31, &umr_bitfield_default },
+	 { "MCIF_SLOW_REQ_INTERVAL", 12, 15, &umr_bitfield_default },
+	 { "PRIVILEGED_ACCESS_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WRITE_COMBINE_CONTROL[] = {
+	 { "MCIF_WRITE_COMBINE_TIMEOUT", 0, 7, &umr_bitfield_default },
+	 { "VIP_WRITE_COMBINE_TIMEOUT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_INDEX[] = {
+	 { "MCIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MCIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_DATA[] = {
+	 { "MCIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_VMID[] = {
+	 { "MCIF_WR_VMID", 0, 3, &umr_bitfield_default },
+	 { "VIP_WR_VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_MEM_CONTROL[] = {
+	 { "MCIFMEM_CACHE_MODE_DIS", 0, 0, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_MODE", 4, 5, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_PIPE", 16, 18, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_SIZE", 8, 14, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_TYPE", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_RBBMIF_RDWR_CNTL1[] = {
+	 { "DC_RBBMIF_CLIENT0_RDWR_DELAY", 0, 2, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT1_RDWR_DELAY", 4, 6, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS", 7, 7, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT2_RDWR_DELAY", 8, 10, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS", 11, 11, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT3_RDWR_DELAY", 12, 14, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS", 15, 15, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT4_RDWR_DELAY", 16, 18, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATE[] = {
+	 { "AZ_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "DMCU_IRAM_PWR_STATE", 28, 29, &umr_bitfield_default },
+	 { "DMCU_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIF0_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMIF1_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "DMIF2_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "DMIF3_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "DMIF4_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "DMIF5_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIF_XLR_MEM1_PWR_STATE", 26, 27, &umr_bitfield_default },
+	 { "DMIF_XLR_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DC_INTERFACE_NACK_STATUS[] = {
+	 { "DMIF_RDRET_NACK_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DMIF_RDRET_NACK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_CLEAR", 28, 28, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_OCCURRED", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_RBBMIF_RDWR_CNTL2[] = {
+	 { "DC_RBBMIF_CLIENT8_RDWR_DELAY", 0, 2, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT9_RDWR_DELAY", 4, 6, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_CLK_CNTL[] = {
+	 { "DCI_PG_TEST_CLK_SEL", 27, 31, &umr_bitfield_default },
+	 { "DCI_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_G_DMCU_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_G_FBC_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_VGA_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "DISPCLK_G_VIP_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "DISPCLK_M_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_R_DCI_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_R_DMCU_GATE_DIS", 14, 14, &umr_bitfield_default },
+	 { "DISPCLK_R_VGA_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "DISPCLK_R_VIP_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "SCLK_G_DMIF_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "SCLK_G_DMIFTRK_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "SCLK_R_AZ_GATE_DIS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_VPCLK_CNTL[] = {
+	 { "AZ_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "AZ_MEM_SHUTDOWN_DIS", 26, 26, &umr_bitfield_default },
+	 { "DCCG_VPCLK_POL", 0, 0, &umr_bitfield_default },
+	 { "DMCU_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DMCU_MEM_SHUTDOWN_DIS", 16, 16, &umr_bitfield_default },
+	 { "DMIF0_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DMIF0_MEM_SHUTDOWN_DIS", 20, 20, &umr_bitfield_default },
+	 { "DMIF1_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
+	 { "DMIF1_MEM_SHUTDOWN_DIS", 21, 21, &umr_bitfield_default },
+	 { "DMIF2_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF2_MEM_SHUTDOWN_DIS", 22, 22, &umr_bitfield_default },
+	 { "DMIF3_LIGHT_SLEEP_DIS", 11, 11, &umr_bitfield_default },
+	 { "DMIF3_MEM_SHUTDOWN_DIS", 23, 23, &umr_bitfield_default },
+	 { "DMIF4_LIGHT_SLEEP_DIS", 12, 12, &umr_bitfield_default },
+	 { "DMIF4_MEM_SHUTDOWN_DIS", 24, 24, &umr_bitfield_default },
+	 { "DMIF5_LIGHT_SLEEP_DIS", 13, 13, &umr_bitfield_default },
+	 { "DMIF5_MEM_SHUTDOWN_DIS", 25, 25, &umr_bitfield_default },
+	 { "DMIF_XLR_LIGHT_SLEEP_MODE_FORCE", 5, 5, &umr_bitfield_default },
+	 { "DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE", 18, 18, &umr_bitfield_default },
+	 { "FBC_LIGHT_SLEEP_DIS", 14, 14, &umr_bitfield_default },
+	 { "FBC_MEM_SHUTDOWN_DIS", 19, 19, &umr_bitfield_default },
+	 { "MCIF_LIGHT_SLEEP_MODE_FORCE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_MEM_SHUTDOWN_MODE_FORCE", 17, 17, &umr_bitfield_default },
+	 { "VGA_LIGHT_SLEEP_MODE_FORCE", 1, 1, &umr_bitfield_default },
+	 { "VIP_LIGHT_SLEEP_DIS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_INDEX[] = {
+	 { "DCI_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCI_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_DATA[] = {
+	 { "DCI_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATE2[] = {
+	 { "DMCU_ERAM1_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMCU_ERAM2_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMCU_ERAM3_PWR_STATE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_DEBUG_CONFIG[] = {
+	 { "DCI_DBG_SEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLOW_POWER_TILING_CONTROL[] = {
+	 { "LOW_POWER_TILING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_MODE", 3, 4, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_BANKS", 8, 10, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_PIPES", 5, 7, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE", 11, 11, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROW_SIZE", 12, 14, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROWS_PER_CHAN", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL[] = {
+	 { "DMIF0_ASYNC_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_SHUTDOWN_DIS", 6, 6, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_SHUTDOWN_DIS", 7, 7, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_SHUTDOWN_DIS", 9, 9, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_SHUTDOWN_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_SHUTDOWN_DIS", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_XDMA_INTERFACE_CNTL[] = {
+	 { "DC_FLIP_PENDING_TO_DCP", 22, 22, &umr_bitfield_default },
+	 { "DC_XDMA_FLIP_PENDING", 16, 16, &umr_bitfield_default },
+	 { "XDMA_M_FLIP_PENDING_TO_DCP", 20, 20, &umr_bitfield_default },
+	 { "XDMA_PIPE_ENABLE", 0, 5, &umr_bitfield_default },
+	 { "XDMA_PIPE_SEL", 8, 10, &umr_bitfield_default },
+	 { "XDMA_S_FLIP_PENDING_TO_DCP", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CNTL[] = {
+	 { "XDMA_MSTR_DEBUG_MODE", 18, 18, &umr_bitfield_default },
+	 { "XDMA_MSTR_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_READY", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_SOFT_RESET", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_READ_COMMAND[] = {
+	 { "XDMA_MSTR_REQUEST_PREFETCH", 16, 29, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_SIZE", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_HEIGHT[] = {
+	 { "XDMA_MSTR_ACTIVE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_FRAME_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_STATUS[] = {
+	 { "XDMA_MSTR_VCOUNT_CURRENT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_WRITE_LINE_CURRENT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MC_PCIE_CLIENT_CONFIG[] = {
+	 { "XDMA_MC_PCIE_PRIV", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_VMID", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_PITCH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_PITCH", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING1[] = {
+	 { "XDMA_LOCAL_ARRAY_MODE", 0, 3, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_WIDTH", 8, 9, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MACRO_TILE_ASPECT", 12, 13, &umr_bitfield_default },
+	 { "XDMA_LOCAL_NUM_BANKS", 20, 21, &umr_bitfield_default },
+	 { "XDMA_LOCAL_TILE_SPLIT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING2[] = {
+	 { "XDMA_LOCAL_MICRO_TILE_MODE", 22, 23, &umr_bitfield_default },
+	 { "XDMA_LOCAL_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
+	 { "XDMA_LOCAL_PIPE_INTERLEAVE_SIZE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CMD_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_CMD_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CNTL[] = {
+	 { "XDMA_SLV_ACTIVE", 8, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_READY", 9, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_SOFT_RESET", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_SLV_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_SLS_PITCH[] = {
+	 { "XDMA_SLV_SLS_PITCH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_SLS_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_URGENT_CNTL[] = {
+	 { "XDMA_SLV_READ_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WRITE_URGENT_CNTL[] = {
+	 { "XDMA_SLV_WRITE_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WB_RATE_CNTL[] = {
+	 { "XDMA_SLV_WB_BURST_PERIOD", 16, 31, &umr_bitfield_default },
+	 { "XDMA_SLV_WB_BURST_SIZE", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_MINMAX[] = {
+	 { "XDMA_SLV_READ_LATENCY_MAX", 16, 31, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_MIN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_AVE[] = {
+	 { "XDMA_SLV_READ_LATENCY_ACC", 0, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_COUNT", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_INTERRUPT[] = {
+	 { "XDMA_MSTR_MEM_URGENT_ACK", 10, 10, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_MASK", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_STAT", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_ACK", 14, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_MASK", 13, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_STAT", 12, 12, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_ACK", 18, 18, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_MASK", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_STAT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_FLIP_PENDING[] = {
+	 { "XDMA_SLV_FLIP_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_CLOCK_GATING_CNTL[] = {
+	 { "XDMA_SCLK_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MSTAT_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SDYN_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SSTAT_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SCLK_REG_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "XDMA_SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_RBBMIF_RDWR_CNTL[] = {
+	 { "XDMA_RBBMIF_RDWR_DELAY", 0, 2, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_TIMEOUT_DELAY", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MEM_POWER_CNTL[] = {
+	 { "XDMA_MEM_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MEM_LIGHT_SLEEP_MODE_FORCE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MEM_POWER_STATE", 30, 31, &umr_bitfield_default },
+	 { "XDMA_MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MEM_SHUTDOWN_MODE_FORCE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PCIE_NACK_STATUS[] = {
+	 { "XDMA_MSTR_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_NACK_STATUS[] = {
+	 { "XDMA_MSTR_MEM_NACK_CLR", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK_TAG", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_PCIE_NACK_STATUS[] = {
+	 { "XDMA_SLV_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_NACK_STATUS[] = {
+	 { "XDMA_SLV_MEM_NACK_CLR", 31, 31, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK", 16, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK_TAG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_TIMER[] = {
+	 { "XDMA_SLV_READ_LATENCY_TIMER", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_BIF_STATUS[] = {
+	 { "XDMA_IF_BIF_ERROR_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "XDMA_IF_BIF_ERROR_STATUS", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_DATA[] = {
+	 { "XDMA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_CTRL[] = {
+	 { "DISABLE_IRQ_TO_UC", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_XIRQ_TO_UC", 3, 3, &umr_bitfield_default },
+	 { "DMCU_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "IGNORE_PWRMGT", 1, 1, &umr_bitfield_default },
+	 { "RESET_UC", 0, 0, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_STATUS[] = {
+	 { "UC_IN_RESET", 0, 0, &umr_bitfield_default },
+	 { "UC_IN_STOP_MODE", 2, 2, &umr_bitfield_default },
+	 { "UC_IN_WAIT_MODE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PC_START_ADDR[] = {
+	 { "PC_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "PC_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_START_ADDR[] = {
+	 { "FW_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_END_ADDR[] = {
+	 { "FW_END_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_END_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_ISR_START_ADDR[] = {
+	 { "FW_ISR_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_ISR_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_HI[] = {
+	 { "FW_CHECKSUM_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_LO[] = {
+	 { "FW_CHECKSUM_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_RAM_ACCESS_CTRL[] = {
+	 { "ERAM_HOST_ACCESS_EN", 4, 4, &umr_bitfield_default },
+	 { "ERAM_RD_ADDR_AUTO_INC", 1, 1, &umr_bitfield_default },
+	 { "ERAM_WR_ADDR_AUTO_INC", 0, 0, &umr_bitfield_default },
+	 { "IRAM_HOST_ACCESS_EN", 5, 5, &umr_bitfield_default },
+	 { "IRAM_RD_ADDR_AUTO_INC", 3, 3, &umr_bitfield_default },
+	 { "IRAM_WR_ADDR_AUTO_INC", 2, 2, &umr_bitfield_default },
+	 { "UC_RST_RELEASE_DELAY_CNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_CTRL[] = {
+	 { "ERAM_WR_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_WR_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_WR_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_DATA[] = {
+	 { "ERAM_WR_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_CTRL[] = {
+	 { "ERAM_RD_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_RD_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_RD_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_DATA[] = {
+	 { "ERAM_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_CTRL[] = {
+	 { "IRAM_WR_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_DATA[] = {
+	 { "IRAM_WR_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_CTRL[] = {
+	 { "IRAM_RD_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_DATA[] = {
+	 { "IRAM_RD_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_EVENT_TRIGGER[] = {
+	 { "GEN_SW_INT_TO_UC", 0, 0, &umr_bitfield_default },
+	 { "GEN_UC_INTERNAL_INT_TO_HOST", 23, 23, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CODE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_INTERNAL_INT_STATUS[] = {
+	 { "UC_INT_ILLEGAL_OPCODE_TRAP", 3, 3, &umr_bitfield_default },
+	 { "UC_INT_IRQ_N_PIN", 0, 0, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE", 14, 14, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_OVERFLOW", 15, 15, &umr_bitfield_default },
+	 { "UC_INT_REAL_TIME_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "UC_INT_SOFTWARE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_1", 13, 13, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_2", 12, 12, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_3", 11, 11, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5", 10, 10, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_1", 7, 7, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_2", 6, 6, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_3", 5, 5, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_4", 4, 4, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "UC_INT_XIRQ_N_PIN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_STATUS[] = {
+	 { "ABM1_BL_UPDATE_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "MCP_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "SCP_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "VBLANK1_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "VBLANK1_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "VBLANK2_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_CLEAR", 26, 26, &umr_bitfield_default },
+	 { "VBLANK3_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "VBLANK4_INT_OCCURRED", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_CLEAR", 28, 28, &umr_bitfield_default },
+	 { "VBLANK5_INT_OCCURRED", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_CLEAR", 29, 29, &umr_bitfield_default },
+	 { "VBLANK6_INT_OCCURRED", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_HOST_EN_MASK[] = {
+	 { "ABM1_BL_UPDATE_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "SCP_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_MASK", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK[] = {
+	 { "ABM1_BL_UPDATE_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "MCP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "VBLANK1_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_TO_UC_EN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[] = {
+	 { "ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "MCP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "VBLANK1_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_XIRQ_IRQ_SEL", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DMCU_SCRATCH[] = {
+	 { "DMCU_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INT_CNT[] = {
+	 { "DMCU_ABM1_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default },
+	 { "DMCU_ABM1_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default },
+	 { "DMCU_ABM1_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[] = {
+	 { "DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS", 2, 3, &umr_bitfield_default },
+	 { "DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_CLK_GATING_CNTL[] = {
+	 { "UC_ERAM_RD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "UC_IRAM_RD_DELAY", 0, 2, &umr_bitfield_default },
+	 { "UC_RBBM_RD_CLK_GATING_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG1[] = {
+	 { "MASTER_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG2[] = {
+	 { "MASTER_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG3[] = {
+	 { "MASTER_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CMD_REG[] = {
+	 { "MASTER_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CNTL_REG[] = {
+	 { "MASTER_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG1[] = {
+	 { "SLAVE_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG2[] = {
+	 { "SLAVE_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG3[] = {
+	 { "SLAVE_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CMD_REG[] = {
+	 { "SLAVE_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CNTL_REG[] = {
+	 { "COMM_PORT_MSG_TO_HOST_IN_PROGRESS", 8, 8, &umr_bitfield_default },
+	 { "SLAVE_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_INDEX[] = {
+	 { "DMCU_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMCU_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_DATA[] = {
+	 { "DMCU_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_AMBIENT_LIGHT_LEVEL[] = {
+	 { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_USER_LEVEL[] = {
+	 { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_TARGET_ABM_LEVEL[] = {
+	 { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_CURRENT_ABM_LEVEL[] = {
+	 { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_FINAL_DUTY_CYCLE[] = {
+	 { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_MINIMUM_DUTY_CYCLE[] = {
+	 { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_ABM_CNTL[] = {
+	 { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default },
+	 { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[] = {
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_GRP2_REG_LOCK[] = {
+	 { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_CNTL[] = {
+	 { "ABM1_BLANK_MODE_SUPPORT_ENABLE", 31, 31, &umr_bitfield_default },
+	 { "ABM1_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_IPCSC_COEFF_SEL[] = {
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_0[] = {
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_1[] = {
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_2[] = {
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_3[] = {
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_4[] = {
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_12[] = {
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_34[] = {
+	 { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_CNTL_MISC[] = {
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_DEBUG_MISC[] = {
+	 { "ABM1_BL_FORCE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "ABM1_HG_FORCE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_FORCE_INTERRUPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HGLS_REG_READ_PROGRESS[] = {
+	 { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_MISC_CTRL[] = {
+	 { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default },
+	 { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default },
+	 { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default },
+	 { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default },
+	 { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SUM_OF_LUMA[] = {
+	 { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default },
+	 { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default },
+	 { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_PIXEL_COUNT[] = {
+	 { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_OVR_SCAN_BIN[] = {
+	 { "ABM1_LS_OVR_SCAN_BIN", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = {
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default },
+	 { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_SAMPLE_RATE[] = {
+	 { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SAMPLE_RATE[] = {
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+	 { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = {
+	 { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_1[] = {
+	 { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_2[] = {
+	 { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_3[] = {
+	 { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_4[] = {
+	 { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_5[] = {
+	 { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_6[] = {
+	 { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_7[] = {
+	 { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_8[] = {
+	 { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_9[] = {
+	 { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_10[] = {
+	 { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_11[] = {
+	 { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_12[] = {
+	 { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_13[] = {
+	 { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_14[] = {
+	 { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_15[] = {
+	 { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_16[] = {
+	 { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_17[] = {
+	 { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_18[] = {
+	 { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_19[] = {
+	 { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_20[] = {
+	 { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_21[] = {
+	 { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_22[] = {
+	 { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_23[] = {
+	 { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_24[] = {
+	 { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL1[] = {
+	 { "MVP_30BPP_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE", 10, 10, &umr_bitfield_default },
+	 { "MVP_CHANNEL_CONTROL", 16, 16, &umr_bitfield_default },
+	 { "MVP_DISABLE_MSB_EXPAND", 24, 24, &umr_bitfield_default },
+	 { "MVP_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_GPU_CHAIN_LOCATION", 20, 21, &umr_bitfield_default },
+	 { "MVP_MIXER_MODE", 4, 6, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK", 9, 9, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_RATE_CONTROL", 12, 12, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_A", 30, 30, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_B", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL2[] = {
+	 { "MVP_DVOCNTL_MUX", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_MUXA_CLK_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MUXB_CLK_SEL", 12, 12, &umr_bitfield_default },
+	 { "MVP_MUX_DE_DVOCNTL0_SEL", 0, 0, &umr_bitfield_default },
+	 { "MVP_MUX_DE_DVOCNTL2_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_SWAP_AB_IN_DC_DDR", 28, 28, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_OUT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_CONTROL[] = {
+	 { "MVP_PAUSE_SLAVE_CNT", 16, 23, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_WM", 8, 15, &umr_bitfield_default },
+	 { "MVP_STOP_SLAVE_WM", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_STATUS[] = {
+	 { "MVP_FIFO_ERROR_INT_STATUS", 31, 31, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_MASK", 30, 30, &umr_bitfield_default },
+	 { "MVP_FIFO_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_ACK", 16, 16, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_ACK", 28, 28, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW", 20, 20, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_OCCURRED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_SLAVE_STATUS[] = {
+	 { "MVP_SLAVE_LINES_PER_FRAME_RCVED", 16, 28, &umr_bitfield_default },
+	 { "MVP_SLAVE_PIXELS_PER_LINE_RCVED", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_INBAND_CNTL_CAP[] = {
+	 { "MVP_IGNOR_INBAND_CNTL", 0, 0, &umr_bitfield_default },
+	 { "MVP_INBAND_CNTL_CHAR_CAP", 8, 31, &umr_bitfield_default },
+	 { "MVP_PASSING_INBAND_CNTL_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_BLACK_KEYER[] = {
+	 { "MVP_BLACK_KEYER_B", 20, 29, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_G", 10, 19, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_R", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_CNTL[] = {
+	 { "MVP_CRC_BLUE_MASK", 0, 7, &umr_bitfield_default },
+	 { "MVP_CRC_CONT_EN", 29, 29, &umr_bitfield_default },
+	 { "MVP_CRC_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_MASK", 8, 15, &umr_bitfield_default },
+	 { "MVP_CRC_RED_MASK", 16, 23, &umr_bitfield_default },
+	 { "MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_BLUE_GREEN[] = {
+	 { "MVP_CRC_BLUE_RESULT", 0, 15, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_RESULT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_RED[] = {
+	 { "MVP_CRC_RED_RESULT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL3[] = {
+	 { "MVP_DDR_SC_AB_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_DDR_SC_B_START_MODE", 8, 8, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_CASCADE_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_CAP", 28, 28, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "MVP_RESET_IN_BETWEEN_FRAMES", 0, 0, &umr_bitfield_default },
+	 { "MVP_SWAP_48BIT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL1[] = {
+	 { "MVP_SLAVE_DATA_CHK_EN", 31, 31, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINE_ERROR_CNT", 16, 28, &umr_bitfield_default },
+	 { "MVP_SLAVE_PIXEL_ERROR_CNT", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL2[] = {
+	 { "MVP_SLAVE_FRAME_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_FRAME_ERROR_CNT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_INDEX[] = {
+	 { "MVP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MVP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_DATA[] = {
+	 { "MVP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_DEBUG[] = {
+	 { "MVP_DEBUG_BITS", 8, 31, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP", 5, 5, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP", 4, 4, &umr_bitfield_default },
+	 { "MVP_DIS_READ_POINTER_RESET_DELAY", 7, 7, &umr_bitfield_default },
+	 { "MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR", 6, 6, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_EN", 1, 1, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_SEL", 3, 3, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_IN_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_IN_SEL", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_OVERSCAN_PIXEL_VALUE[] = {
+	 { "ABM1_OVERSCAN_B_PIXEL_VALUE", 20, 29, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_G_PIXEL_VALUE", 10, 19, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_R_PIXEL_VALUE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_BL_MASTER_LOCK[] = {
+	 { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_INDEX[] = {
+	 { "ABM_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "ABM_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_DATA[] = {
+	 { "ABM_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CNTL[] = {
+	 { "FBC_COHERENCY_MODE", 16, 17, &umr_bitfield_default },
+	 { "FBC_EN", 31, 31, &umr_bitfield_default },
+	 { "FBC_GRPH_COMP_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_SOFT_COMPRESS_EN", 25, 25, &umr_bitfield_default },
+	 { "FBC_SRC_SEL", 1, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_MASK[] = {
+	 { "FBC_IDLE_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_FORCE_CLEAR_MASK[] = {
+	 { "FBC_IDLE_FORCE_CLEAR_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_START_STOP_DELAY[] = {
+	 { "FBC_COMP_START_DELAY", 8, 12, &umr_bitfield_default },
+	 { "FBC_DECOMP_START_DELAY", 0, 4, &umr_bitfield_default },
+	 { "FBC_DECOMP_STOP_DELAY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_CNTL[] = {
+	 { "FBC_DEPTH_MONO08_EN", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO16_EN", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB04_EN", 18, 18, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB08_EN", 19, 19, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB16_EN", 20, 20, &umr_bitfield_default },
+	 { "FBC_MIN_COMPRESSION", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_MODE[] = {
+	 { "FBC_DPCM4_RGB_EN", 8, 8, &umr_bitfield_default },
+	 { "FBC_DPCM4_YUV_EN", 10, 10, &umr_bitfield_default },
+	 { "FBC_DPCM8_RGB_EN", 9, 9, &umr_bitfield_default },
+	 { "FBC_DPCM8_YUV_EN", 11, 11, &umr_bitfield_default },
+	 { "FBC_IND_EN", 16, 16, &umr_bitfield_default },
+	 { "FBC_RLE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG0[] = {
+	 { "FBC_COMP_WAKE_DIS", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG0", 17, 23, &umr_bitfield_default },
+	 { "FBC_DEBUG_MUX", 24, 31, &umr_bitfield_default },
+	 { "FBC_PERF_MUX0", 0, 7, &umr_bitfield_default },
+	 { "FBC_PERF_MUX1", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG1[] = {
+	 { "FBC_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG2[] = {
+	 { "FBC_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT0[] = {
+	 { "FBC_IND_LUT0", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT1[] = {
+	 { "FBC_IND_LUT1", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT2[] = {
+	 { "FBC_IND_LUT2", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT3[] = {
+	 { "FBC_IND_LUT3", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT4[] = {
+	 { "FBC_IND_LUT4", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT5[] = {
+	 { "FBC_IND_LUT5", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT6[] = {
+	 { "FBC_IND_LUT6", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT7[] = {
+	 { "FBC_IND_LUT7", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT8[] = {
+	 { "FBC_IND_LUT8", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT9[] = {
+	 { "FBC_IND_LUT9", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT10[] = {
+	 { "FBC_IND_LUT10", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT11[] = {
+	 { "FBC_IND_LUT11", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT12[] = {
+	 { "FBC_IND_LUT12", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT13[] = {
+	 { "FBC_IND_LUT13", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT14[] = {
+	 { "FBC_IND_LUT14", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT15[] = {
+	 { "FBC_IND_LUT15", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_01[] = {
+	 { "FBC_CSM_REGION_OFFSET_0", 0, 9, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_23[] = {
+	 { "FBC_CSM_REGION_OFFSET_2", 0, 9, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_3", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CLIENT_REGION_MASK[] = {
+	 { "FBC_MEMORY_REGION_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_COMP[] = {
+	 { "FBC_COMP_ADDRESS_TRANSLATION_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "FBC_COMP_BUSY_HYSTERESIS", 4, 7, &umr_bitfield_default },
+	 { "FBC_COMP_CLK_CNTL", 8, 9, &umr_bitfield_default },
+	 { "FBC_COMP_PRIVILEGED_ACCESS_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "FBC_COMP_RSIZE", 3, 3, &umr_bitfield_default },
+	 { "FBC_COMP_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR[] = {
+	 { "FBC_DEBUG_CSR_ADDR", 0, 9, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_EN", 31, 31, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_RD_DATA", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_WR_DATA", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA[] = {
+	 { "FBC_DEBUG_CSR_RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA[] = {
+	 { "FBC_DEBUG_CSR_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_MISC[] = {
+	 { "FBC_DECOMPRESS_ERROR_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "FBC_DECOMPRESS_ERROR", 0, 1, &umr_bitfield_default },
+	 { "FBC_DIVIDE_X", 8, 9, &umr_bitfield_default },
+	 { "FBC_DIVIDE_Y", 10, 10, &umr_bitfield_default },
+	 { "FBC_ERROR_PIXEL", 4, 7, &umr_bitfield_default },
+	 { "FBC_INVALIDATE_ON_ERROR", 3, 3, &umr_bitfield_default },
+	 { "FBC_RESET_AT_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "FBC_RESET_AT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FBC_RSM_UNCOMP_DATA_IMMEDIATELY", 12, 12, &umr_bitfield_default },
+	 { "FBC_RSM_WRITE_VALUE", 11, 11, &umr_bitfield_default },
+	 { "FBC_SLOW_REQ_INTERVAL", 28, 31, &umr_bitfield_default },
+	 { "FBC_STOP_ON_ERROR", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_STATUS[] = {
+	 { "FBC_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_INDEX[] = {
+	 { "FBC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FBC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_DATA[] = {
+	 { "FBC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_RDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_WDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[] = {
+	 { "SUBSYSTEM_ID_BYTE1", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[] = {
+	 { "SUBSYSTEM_ID_BYTE2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[] = {
+	 { "SUBSYSTEM_ID_BYTE3", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_CONFIG[] = {
+	 { "PIPE0_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_ENABLE[] = {
+	 { "PIPE0_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_STATUS[] = {
+	 { "PIPE0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+	 { "PIPE0_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE0_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_CONFIG[] = {
+	 { "PIPE1_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_ENABLE[] = {
+	 { "PIPE1_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_STATUS[] = {
+	 { "PIPE1_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE1_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+	 { "PIPE1_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE1_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_CONFIG[] = {
+	 { "PIPE2_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_ENABLE[] = {
+	 { "PIPE2_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_STATUS[] = {
+	 { "PIPE2_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE2_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+	 { "PIPE2_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE2_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_CONFIG[] = {
+	 { "PIPE3_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_ENABLE[] = {
+	 { "PIPE3_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_STATUS[] = {
+	 { "PIPE3_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE3_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+	 { "PIPE3_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE3_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_ENABLE[] = {
+	 { "PIPE4_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_STATUS[] = {
+	 { "PIPE4_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE4_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+	 { "PIPE4_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE4_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_CONFIG[] = {
+	 { "PIPE5_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_ENABLE[] = {
+	 { "PIPE5_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_STATUS[] = {
+	 { "PIPE5_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE5_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+	 { "PIPE5_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE5_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_INDEX[] = {
+	 { "DCPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_DATA[] = {
+	 { "DCPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_CONFIG_REG[] = {
+	 { "PGFSM_CONFIG_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_WRITE_REG[] = {
+	 { "PGFSM_WRITE_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGCNTL_STATUS_REG[] = {
+	 { "DCPG_ECO_DEBUG", 16, 31, &umr_bitfield_default },
+	 { "IPREQ_IGNORE_STATUS", 2, 2, &umr_bitfield_default },
+	 { "SWREQ_RWOP_BUSY", 0, 0, &umr_bitfield_default },
+	 { "SWREQ_RWOP_FORCE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
+	 { "DC_PIPE_DIS", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
+	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
+	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO[] = {
+	 { "AZALIA_AUDIO_DTO_MODULE", 16, 31, &umr_bitfield_default },
+	 { "AZALIA_AUDIO_DTO_PHASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO_CONTROL[] = {
+	 { "AZALIA_AUDIO_FORCE_DTO", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_SCLK_CONTROL[] = {
+	 { "AUDIO_SCLK_CONTROL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_UNDERFLOW_FILLER_SAMPLE[] = {
+	 { "AZALIA_UNDERFLOW_FILLER_SAMPLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_DATA_DMA_CONTROL[] = {
+	 { "AZALIA_IOC_GENERATION_METHOD", 16, 16, &umr_bitfield_default },
+	 { "AZALIA_UNDERFLOW_CONTROL", 17, 17, &umr_bitfield_default },
+	 { "DATA_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "DATA_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_BDL_DMA_CONTROL[] = {
+	 { "BDL_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "BDL_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_RIRB_AND_DP_CONTROL[] = {
+	 { "DP_DMA_NON_SNOOP", 4, 4, &umr_bitfield_default },
+	 { "RIRB_NON_SNOOP", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CORB_DMA_CONTROL[] = {
+	 { "CORB_DMA_ISOCHRONOUS", 4, 4, &umr_bitfield_default },
+	 { "CORB_DMA_NON_SNOOP", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[] = {
+	 { "APPLICATION_POSITION_IN_CYCLIC_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CYCLIC_BUFFER_SYNC[] = {
+	 { "CYCLIC_BUFFER_SYNC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_GLOBAL_CAPABILITIES[] = {
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+	 { "OUTSTRMPAY", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[] = {
+	 { "LATENCY_HIDING_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "SYS_MEM_ACTIVE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_DEBUG[] = {
+	 { "CONTROLLER_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_INDEX[] = {
+	 { "AZ_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZ_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_DATA[] = {
+	 { "AZ_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[] = {
+	 { "PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[] = {
+	 { "COMPRESSED_CHANNEL_COUNT", 4, 6, &umr_bitfield_default },
+	 { "HBR_CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[] = {
+	 { "RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_DEBUG[] = {
+	 { "CODEC_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_INDEX[] = {
+	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_DATA[] = {
+	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_INT_STATUS[] = {
+	 { "DC_HPD1_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD1_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD1_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_INT_CONTROL[] = {
+	 { "DC_HPD1_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD1_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD1_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_CONTROL[] = {
+	 { "DC_HPD1_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD1_EN", 28, 28, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_INT_STATUS[] = {
+	 { "DC_HPD2_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD2_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD2_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_INT_CONTROL[] = {
+	 { "DC_HPD2_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD2_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD2_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_CONTROL[] = {
+	 { "DC_HPD2_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD2_EN", 28, 28, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_INT_STATUS[] = {
+	 { "DC_HPD3_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD3_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD3_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_INT_CONTROL[] = {
+	 { "DC_HPD3_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD3_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD3_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_CONTROL[] = {
+	 { "DC_HPD3_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD3_EN", 28, 28, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_INT_STATUS[] = {
+	 { "DC_HPD4_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD4_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD4_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_INT_CONTROL[] = {
+	 { "DC_HPD4_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD4_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD4_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_CONTROL[] = {
+	 { "DC_HPD4_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD4_EN", 28, 28, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_INT_STATUS[] = {
+	 { "DC_HPD5_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD5_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD5_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_INT_CONTROL[] = {
+	 { "DC_HPD5_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD5_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD5_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_CONTROL[] = {
+	 { "DC_HPD5_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD5_EN", 28, 28, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_INT_STATUS[] = {
+	 { "DC_HPD6_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD6_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD6_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_INT_CONTROL[] = {
+	 { "DC_HPD6_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD6_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD6_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_CONTROL[] = {
+	 { "DC_HPD6_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD6_EN", 28, 28, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_CONTROL[] = {
+	 { "DC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+	 { "DC_I2C_DDC_SELECT", 8, 10, &umr_bitfield_default },
+	 { "DC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_STATUS_RESET", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_TRANSACTION_COUNT", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_ARBITRATION[] = {
+	 { "DC_I2C_ABORT_HW_XFER", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_SW_XFER", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_DONE_USING_I2C_REG", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_USE_I2C_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_NO_QUEUED_SW_GO", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_USING_I2C_REG", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_SW_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_USE_I2C_REG_REQ", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_INTERRUPT_CONTROL[] = {
+	 { "DC_I2C_DDC1_HW_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_MASK", 10, 10, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_ACK", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_INT", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_MASK", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_ACK", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_INT", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_MASK", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_ACK", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_INT", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_ACK", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_INT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_MASK", 26, 26, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_ACK", 28, 28, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_INT", 27, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_MASK", 29, 29, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_SW_STATUS[] = {
+	 { "DC_I2C_SW_ABORTED", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_SW_BUFFER_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_INTERRUPTED", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK2", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK3", 15, 15, &umr_bitfield_default },
+	 { "DC_I2C_SW_REQ", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_SW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_STOPPED_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_SW_TIMEOUT", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_HW_STATUS[] = {
+	 { "DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_URG", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_HW_STATUS[] = {
+	 { "DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_URG", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_HW_STATUS[] = {
+	 { "DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_URG", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_HW_STATUS[] = {
+	 { "DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_URG", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_HW_STATUS[] = {
+	 { "DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_URG", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_HW_STATUS[] = {
+	 { "DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_URG", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SPEED[] = {
+	 { "DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_PRESCALE", 16, 31, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_THRESHOLD", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SETUP[] = {
+	 { "DC_I2C_DDC1_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SPEED[] = {
+	 { "DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_PRESCALE", 16, 31, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_THRESHOLD", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SETUP[] = {
+	 { "DC_I2C_DDC2_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SPEED[] = {
+	 { "DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_PRESCALE", 16, 31, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_THRESHOLD", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SETUP[] = {
+	 { "DC_I2C_DDC3_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SPEED[] = {
+	 { "DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_PRESCALE", 16, 31, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_THRESHOLD", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SETUP[] = {
+	 { "DC_I2C_DDC4_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SPEED[] = {
+	 { "DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_PRESCALE", 16, 31, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_THRESHOLD", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SETUP[] = {
+	 { "DC_I2C_DDC5_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SPEED[] = {
+	 { "DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_PRESCALE", 16, 31, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_THRESHOLD", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SETUP[] = {
+	 { "DC_I2C_DDC6_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION0[] = {
+	 { "DC_I2C_COUNT0", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_RW0", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_START0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP0", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK0", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION1[] = {
+	 { "DC_I2C_COUNT1", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_RW1", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_START1", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK1", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION2[] = {
+	 { "DC_I2C_COUNT2", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_RW2", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_START2", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP2", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK2", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION3[] = {
+	 { "DC_I2C_COUNT3", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_RW3", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_START3", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP3", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK3", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DATA[] = {
+	 { "DC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_INDEX", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_CONTROL[] = {
+	 { "GENERIC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+	 { "GENERIC_I2C_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_INTERRUPT_CONTROL[] = {
+	 { "GENERIC_I2C_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_MASK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_STATUS[] = {
+	 { "GENERIC_I2C_ABORTED", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_NACK", 10, 10, &umr_bitfield_default },
+	 { "GENERIC_I2C_STATUS", 0, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOPPED_ON_NACK", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIMEOUT", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SPEED[] = {
+	 { "GENERIC_I2C_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_PRESCALE", 16, 31, &umr_bitfield_default },
+	 { "GENERIC_I2C_THRESHOLD", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SETUP[] = {
+	 { "GENERIC_I2C_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_TRANSACTION[] = {
+	 { "GENERIC_I2C_ACK_ON_READ", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_COUNT", 16, 19, &umr_bitfield_default },
+	 { "GENERIC_I2C_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_START", 12, 12, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP", 13, 13, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP_ON_NACK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_DATA[] = {
+	 { "GENERIC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX", 16, 19, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_SELECTION[] = {
+	 { "GENERIC_I2C_SCL_PIN_SEL", 0, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_PIN_SEL", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_DEBUG[] = {
+	 { "GENERIC_I2C_SCL_EN", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_INPUT", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_EN", 6, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_INPUT", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_OUTPUT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS[] = {
+	 { "ABM1_BL_UPDATE_INT", 30, 30, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT", 28, 28, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT", 29, 29, &umr_bitfield_default },
+	 { "AUX1_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX1_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "CRTC1_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "CRTC1_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC1_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC1_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DACA_AUTODETECT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DACB_AUTODETECT_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DC_HPD1_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_HW_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGA_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE", 31, 31, &umr_bitfield_default },
+	 { "DMCU_SCP_INT", 27, 27, &umr_bitfield_default },
+	 { "DMCU_UC_INTERNAL_INT", 26, 26, &umr_bitfield_default },
+	 { "LB_D1_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "LB_D1_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "SCL_DISP1_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE[] = {
+	 { "AUX2_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX2_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "CRTC2_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "CRTC2_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC2_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC2_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DC_HPD2_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGB_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE2", 31, 31, &umr_bitfield_default },
+	 { "DISP_TIMER_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "LB_D2_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "LB_D2_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "SCL_DISP2_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE2[] = {
+	 { "AUX3_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX3_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "CRTC3_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "CRTC3_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC3_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC3_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DC_HPD3_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGC_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE3", 31, 31, &umr_bitfield_default },
+	 { "LB_D3_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "LB_D3_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "SCL_DISP3_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE3[] = {
+	 { "AUX4_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX4_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "CRTC4_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "CRTC4_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC4_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC4_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DC_HPD4_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGD_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE4", 31, 31, &umr_bitfield_default },
+	 { "LB_D4_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "LB_D4_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "SCL_DISP4_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_POWER_MANAGEMENT_CNTL[] = {
+	 { "PM_ALL_BUSY_OFF", 8, 8, &umr_bitfield_default },
+	 { "PM_ASSERT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_TIMER_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MSK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH0[] = {
+	 { "DOUT_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH1[] = {
+	 { "DOUT_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH2[] = {
+	 { "DOUT_SCRATCH2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH3[] = {
+	 { "DOUT_SCRATCH3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH4[] = {
+	 { "DOUT_SCRATCH4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH5[] = {
+	 { "DOUT_SCRATCH5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH6[] = {
+	 { "DOUT_SCRATCH6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH7[] = {
+	 { "DOUT_SCRATCH7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_TEST_DEBUG_INDEX[] = {
+	 { "DOUT_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DOUT_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_TEST_DEBUG_DATA[] = {
+	 { "DOUT_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE4[] = {
+	 { "AUX5_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX5_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "CRTC5_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "CRTC5_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC5_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC5_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DC_HPD5_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGE_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE5", 31, 31, &umr_bitfield_default },
+	 { "LB_D5_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "LB_D5_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "SCL_DISP5_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE5[] = {
+	 { "AUX6_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX6_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "CRTC6_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "CRTC6_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC6_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC6_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC6_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DC_HPD6_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGF_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "LB_D6_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "LB_D6_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "SCL_DISP6_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_HW_STATUS[] = {
+	 { "DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_URG", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SPEED[] = {
+	 { "DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_PRESCALE", 16, 31, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_THRESHOLD", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SETUP[] = {
+	 { "DC_I2C_DDCVGA_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_ENABLE[] = {
+	 { "DVO_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SOURCE_SELECT[] = {
+	 { "DVO_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DVO_STEREOSYNC_SELECT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_OUTPUT[] = {
+	 { "DVO_CLOCK_MODE", 8, 8, &umr_bitfield_default },
+	 { "DVO_OUTPUT_ENABLE_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CONTROL[] = {
+	 { "DVO_COLOR_FORMAT", 24, 25, &umr_bitfield_default },
+	 { "DVO_CTL3", 31, 31, &umr_bitfield_default },
+	 { "DVO_DUAL_CHANNEL_EN", 8, 8, &umr_bitfield_default },
+	 { "DVO_INVERT_DVOCLK", 18, 18, &umr_bitfield_default },
+	 { "DVO_RATE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "DVO_RESET_FIFO", 16, 16, &umr_bitfield_default },
+	 { "DVO_SDRCLK_SEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_SYNC_PHASE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC_EN[] = {
+	 { "DVO_CRC2_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_MASK[] = {
+	 { "DVO_CRC2_SIG_MASK", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_RESULT[] = {
+	 { "DVO_CRC2_SIG_RESULT", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_FIFO_ERROR_STATUS[] = {
+	 { "DVO_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DVO_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DVO_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+	 { "DVO_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DVO_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DVO_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DVO_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DVO_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK1_SEL[] = {
+	 { "DCDEBUG_BUS_CLK1_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK2_SEL[] = {
+	 { "DCDEBUG_BUS_CLK2_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK3_SEL[] = {
+	 { "DCDEBUG_BUS_CLK3_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK4_SEL[] = {
+	 { "DCDEBUG_BUS_CLK4_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD1_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD1_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD1_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD1_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD2_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD2_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD2_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD2_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD3_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD3_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD3_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD3_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD4_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD4_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD4_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD4_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD5_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD5_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD5_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD5_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD6_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD6_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD6_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD6_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_PIN_OVERRIDE[] = {
+	 { "DCDEBUG_OUT_OVERRIDE1_EN", 12, 12, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_PIN_SEL", 0, 3, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL", 4, 8, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_EN", 28, 28, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_PIN_SEL", 16, 19, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL", 20, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_CNTL[] = {
+	 { "DCDEBUG_BLOCK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_EN", 5, 5, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_PIN_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_TEST_DATA_EN", 7, 7, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_TEST_DATA", 8, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_DATA[] = {
+	 { "DCDEBUG_OUT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_EDID_DETECT_CTRL[] = {
+	 { "DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID", 20, 23, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_SEND_RESET", 28, 28, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_WAIT_TIME", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_CONTROL[] = {
+	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
+	 { "AUX_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
+	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
+	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
+	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
+	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
+	 { "SPARE_0", 30, 30, &umr_bitfield_default },
+	 { "SPARE_1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_CONTROL[] = {
+	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
+	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
+	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_ARB_CONTROL[] = {
+	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
+	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
+	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
+	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_INTERRUPT_CONTROL[] = {
+	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_STATUS[] = {
+	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
+	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_STATUS[] = {
+	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
+	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_DATA[] = {
+	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
+	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_DATA[] = {
+	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_REF_CONTROL[] = {
+	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
+	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
+	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_CONTROL[] = {
+	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
+	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL0[] = {
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
+	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
+	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
+	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
+	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
+	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
+	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL1[] = {
+	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_STATUS[] = {
+	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
+	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_STATUS[] = {
+	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
+	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
+	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_CONTROL[] = {
+	 { "AUX_GTC_SYNC_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD1_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD1_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD2_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD2_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD3_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD3_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPOUT_STEREOSYNC_SEL[] = {
+	 { "GENERICA_STEREOSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "GENERICB_STEREOSYNC_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD4_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD4_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD5_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD5_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD6_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD6_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_DCE_VCE_CONTROL[] = {
+	 { "DC_VCE_AUDIO_STREAM_SELECT", 4, 6, &umr_bitfield_default },
+	 { "DC_VCE_VIDEO_PIPE_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICA[] = {
+	 { "GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICA_SEL", 8, 11, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 26, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_SEL", 16, 18, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 22, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_REFDIV_CLK_SEL", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICB[] = {
+	 { "GENERICB_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICB_SEL", 8, 11, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 26, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_SEL", 16, 18, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 22, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_REFDIV_CLK_SEL", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PAD_EXTERN_SIG[] = {
+	 { "DC_PAD_EXTERN_SIG_SEL", 0, 3, &umr_bitfield_default },
+	 { "MVP_PIXEL_SRC_STATUS", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_REF_CLK_CNTL[] = {
+	 { "GENLK_CLK_OUTPUT_SEL", 8, 9, &umr_bitfield_default },
+	 { "HSYNCA_OUTPUT_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DEBUG[] = {
+	 { "DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_MACRO_DEBUG", 8, 9, &umr_bitfield_default },
+	 { "DC_GPIO_VIP_DEBUG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DVODATA_CONFIG[] = {
+	 { "DVO_ALTER_MAPPING_EN", 21, 21, &umr_bitfield_default },
+	 { "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default },
+	 { "VIP_MUX_EN", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_POWER_STATE[] = {
+	 { "DPA_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "DPB_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "DPC_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "DPD_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "DPE_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "DPF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_STATE", 26, 27, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
+	 { "I2C_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "MVP_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "TVOUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_LIGHT_SLEEP_DIS[] = {
+	 { "DPA_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DPA_MEM_SHUTDOWN_DIS", 17, 17, &umr_bitfield_default },
+	 { "DPB_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DPB_MEM_SHUTDOWN_DIS", 18, 18, &umr_bitfield_default },
+	 { "DPC_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DPC_MEM_SHUTDOWN_DIS", 19, 19, &umr_bitfield_default },
+	 { "DPD_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DPD_MEM_SHUTDOWN_DIS", 20, 20, &umr_bitfield_default },
+	 { "DPE_LIGHT_SLEEP_DIS", 7, 7, &umr_bitfield_default },
+	 { "DPE_MEM_SHUTDOWN_DIS", 21, 21, &umr_bitfield_default },
+	 { "DPF_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DPF_MEM_SHUTDOWN_DIS", 22, 22, &umr_bitfield_default },
+	 { "HDMI0_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
+	 { "HDMI1_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
+	 { "HDMI2_LIGHT_SLEEP_DIS", 11, 11, &umr_bitfield_default },
+	 { "HDMI3_LIGHT_SLEEP_DIS", 12, 12, &umr_bitfield_default },
+	 { "HDMI4_LIGHT_SLEEP_DIS", 13, 13, &umr_bitfield_default },
+	 { "HDMI5_LIGHT_SLEEP_DIS", 14, 14, &umr_bitfield_default },
+	 { "I2C_LIGHT_SLEEP_FORCE", 1, 1, &umr_bitfield_default },
+	 { "MVP_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "MVP_MEM_SHUTDOWN_DIS", 16, 16, &umr_bitfield_default },
+	 { "TVOUT_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKA[] = {
+	 { "UNIPHY_CALOUT_ERROR_LINKA_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKA", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_ENABLE_LINKA", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKA", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKA", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKA", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKA", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKB[] = {
+	 { "UNIPHY_CALOUT_ERROR_LINKB_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKB", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_ENABLE_LINKB", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKB", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKB", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKB", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKB", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PERIOD[] = {
+	 { "UNIPHY_IMPCAL_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXP_IMPCAL[] = {
+	 { "AUXP_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXN_IMPCAL[] = {
+	 { "AUXN_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_AB[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_AB[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKA", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKB", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKC[] = {
+	 { "UNIPHY_CALOUT_ERROR_LINKC_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKC", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_ENABLE_LINKC", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKC", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKC", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKC", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKC", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKD[] = {
+	 { "UNIPHY_CALOUT_ERROR_LINKD_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKD", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_ENABLE_LINKD", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKD", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKD", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKD", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKD", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_CD[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_CD[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKC", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKD", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKE[] = {
+	 { "UNIPHY_CALOUT_ERROR_LINKE_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKE", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_ENABLE_LINKE", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKE", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKE", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKE", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKE", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKF[] = {
+	 { "UNIPHY_CALOUT_ERROR_LINKF_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKF", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_ENABLE_LINKF", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKF", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKF", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKF", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKF", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_EF[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_EF[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKE", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKF", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PINSTRAPS[] = {
+	 { "DC_PINSTRAPS_AUDIO", 14, 15, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_BIF_CEC_DIS", 10, 10, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_CCBYPASS", 16, 16, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_SMS_EN_HARD", 13, 13, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_VIP_DEVICE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_CNTL[] = {
+	 { "LVTMA_BLON", 24, 24, &umr_bitfield_default },
+	 { "LVTMA_BLON_OVRD", 25, 25, &umr_bitfield_default },
+	 { "LVTMA_BLON_POL", 26, 26, &umr_bitfield_default },
+	 { "LVTMA_DIGON", 16, 16, &umr_bitfield_default },
+	 { "LVTMA_DIGON_OVRD", 17, 17, &umr_bitfield_default },
+	 { "LVTMA_DIGON_POL", 18, 18, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_EN", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_TARGET_STATE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN", 8, 8, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_OVRD", 9, 9, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_POL", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_STATE[] = {
+	 { "LVTMA_PWRSEQ_BLON", 3, 3, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DIGON", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DONE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_STATE", 8, 11, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_SYNCEN", 2, 2, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_TARGET_STATE_R", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_REF_DIV[] = {
+	 { "BL_PWM_REF_DIV", 16, 31, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_REF_DIV", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY1[] = {
+	 { "LVTMA_PWRDN_DELAY1", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY2", 24, 31, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY1", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY2", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY2[] = {
+	 { "LVTMA_PWRDN_DELAY3", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_MIN_LENGTH", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY3", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_VARY_BL_OVERRIDE_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL[] = {
+	 { "BL_ACTIVE_INT_FRAC_CNT", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_EN", 31, 31, &umr_bitfield_default },
+	 { "BL_PWM_FRACTIONAL_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL2[] = {
+	 { "BL_PWM_OVERRIDE_BL_OUT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN", 31, 31, &umr_bitfield_default },
+	 { "BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE", 0, 15, &umr_bitfield_default },
+	 { "DBG_BL_PWM_INPUT_REFCLK_SELECT", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_PERIOD_CNTL[] = {
+	 { "BL_PWM_PERIOD_BITCNT", 16, 19, &umr_bitfield_default },
+	 { "BL_PWM_PERIOD", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_GRP1_REG_LOCK[] = {
+	 { "BL_PWM_GRP1_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_GENLK_PAD_CNTL[] = {
+	 { "DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_MASK", 24, 25, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_SWAPLOCK_PAD_CNTL[] = {
+	 { "DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_MASK", 24, 25, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL0_CNTL[] = {
+	 { "DCIO_GSL0_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+	 { "DCIO_GSL0_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL0_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL1_CNTL[] = {
+	 { "DCIO_GSL1_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+	 { "DCIO_GSL1_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL1_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL2_CNTL[] = {
+	 { "DCIO_GSL2_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+	 { "DCIO_GSL2_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL2_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_P_FLIP[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_P_FLIP", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_P_FLIP", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_P_FLIP", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_P_FLIP", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_P_FLIP", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_P_FLIP", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ[] = {
+	 { "DC_GPU_TIMER_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ_CNTL[] = {
+	 { "DC_GPU_TIMER_READ_SELECT", 0, 5, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM", 11, 13, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM", 14, 16, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM", 17, 19, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM", 20, 22, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL[] = {
+	 { "DCO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_G_ABM_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_G_DACA_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_DACB_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGA_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGB_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGC_GATE_DIS", 26, 26, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGD_GATE_DIS", 27, 27, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGE_GATE_DIS", 28, 28, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGF_GATE_DIS", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_G_DVO_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_R_ABM_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "DISPCLK_R_DCO_GATE_DIS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_RAMP_CNTL[] = {
+	 { "DISPCLK_G_ABM_RAMP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_G_DACA_RAMP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_DACB_RAMP_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGA_RAMP_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGB_RAMP_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGC_RAMP_DIS", 26, 26, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGD_RAMP_DIS", 27, 27, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGE_RAMP_DIS", 28, 28, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGF_RAMP_DIS", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_G_DVO_RAMP_DIS", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT0_RAMP_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT1_RAMP_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT2_RAMP_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT3_RAMP_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT4_RAMP_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT5_RAMP_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_R_ABM_RAMP_DIS", 12, 12, &umr_bitfield_default },
+	 { "DISPCLK_R_DCO_RAMP_DIS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DEBUG[] = {
+	 { "DCIO_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_INDEX[] = {
+	 { "DCIO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCIO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_DATA[] = {
+	 { "DCIO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYAB_TPG_CONTROL[] = {
+	 { "UNIPHYAB_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHYAB_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHYAB_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYAB_TPG_SEED[] = {
+	 { "UNIPHYAB_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYCD_TPG_CONTROL[] = {
+	 { "UNIPHYCD_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHYCD_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHYCD_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYCD_TPG_SEED[] = {
+	 { "UNIPHYCD_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYEF_TPG_CONTROL[] = {
+	 { "UNIPHYEF_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHYEF_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHYEF_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYEF_TPG_SEED[] = {
+	 { "UNIPHYEF_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_MASK[] = {
+	 { "DC_GPIO_BLON_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_PD_DIS", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_RECV", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_A[] = {
+	 { "DC_GPIO_BLON_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_A", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_EN[] = {
+	 { "DC_GPIO_BLON_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VARY_BL_GENERICA_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_Y[] = {
+	 { "DC_GPIO_BLON_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_Y", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_MASK[] = {
+	 { "DC_GPIO_GENERICA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_PD_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_MASK", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_PD_DIS", 13, 13, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_RECV", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_A[] = {
+	 { "DC_GPIO_GENERICA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_A", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_A", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_A", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_A", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_EN[] = {
+	 { "DC_GPIO_GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_Y[] = {
+	 { "DC_GPIO_GENERICA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_Y", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_Y", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_Y", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_Y", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_MASK[] = {
+	 { "DC_GPIO_DVOCLK_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_MASK", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_DVODATA_MASK", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_MASK", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_A[] = {
+	 { "DC_GPIO_DVOCLK_A", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_A", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_DVODATA_A", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_A", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_EN[] = {
+	 { "DC_GPIO_DVOCLK_EN", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_EN", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_DVODATA_EN", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_EN", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_Y[] = {
+	 { "DC_GPIO_DVOCLK_Y", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_Y", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_DVODATA_Y", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_Y", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_MASK[] = {
+	 { "ALLOW_HW_DDC1_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "AUX1_POL", 20, 20, &umr_bitfield_default },
+	 { "AUX_PAD1_MODE", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_A[] = {
+	 { "DC_GPIO_DDC1CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_EN[] = {
+	 { "DC_GPIO_DDC1CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_Y[] = {
+	 { "DC_GPIO_DDC1CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_MASK[] = {
+	 { "ALLOW_HW_DDC2_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "AUX2_POL", 20, 20, &umr_bitfield_default },
+	 { "AUX_PAD2_MODE", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_A[] = {
+	 { "DC_GPIO_DDC2CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_EN[] = {
+	 { "DC_GPIO_DDC2CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_Y[] = {
+	 { "DC_GPIO_DDC2CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_MASK[] = {
+	 { "ALLOW_HW_DDC3_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "AUX3_POL", 20, 20, &umr_bitfield_default },
+	 { "AUX_PAD3_MODE", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_A[] = {
+	 { "DC_GPIO_DDC3CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_EN[] = {
+	 { "DC_GPIO_DDC3CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_Y[] = {
+	 { "DC_GPIO_DDC3CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_MASK[] = {
+	 { "ALLOW_HW_DDC4_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "AUX4_POL", 20, 20, &umr_bitfield_default },
+	 { "AUX_PAD4_MODE", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_A[] = {
+	 { "DC_GPIO_DDC4CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_EN[] = {
+	 { "DC_GPIO_DDC4CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_Y[] = {
+	 { "DC_GPIO_DDC4CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_MASK[] = {
+	 { "ALLOW_HW_DDC5_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "AUX5_POL", 20, 20, &umr_bitfield_default },
+	 { "AUX_PAD5_MODE", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_A[] = {
+	 { "DC_GPIO_DDC5CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_EN[] = {
+	 { "DC_GPIO_DDC5CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_Y[] = {
+	 { "DC_GPIO_DDC5CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_MASK[] = {
+	 { "ALLOW_HW_DDC6_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "AUX6_POL", 20, 20, &umr_bitfield_default },
+	 { "AUX_PAD6_MODE", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_A[] = {
+	 { "DC_GPIO_DDC6CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_EN[] = {
+	 { "DC_GPIO_DDC6CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_Y[] = {
+	 { "DC_GPIO_DDC6CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_MASK[] = {
+	 { "DC_GPIO_HSYNCA_CRTC_HSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_CRTC_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_RECV", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_A[] = {
+	 { "DC_GPIO_HSYNCA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_EN[] = {
+	 { "DC_GPIO_HSYNCA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_Y[] = {
+	 { "DC_GPIO_HSYNCA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_MASK[] = {
+	 { "DC_GPIO_GENLK_CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PU_EN", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PU_EN", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PU_EN", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PU_EN", 27, 27, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_RECV", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_A[] = {
+	 { "DC_GPIO_GENLK_CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_A", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_EN[] = {
+	 { "DC_GPIO_GENLK_CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_Y[] = {
+	 { "DC_GPIO_GENLK_CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_Y", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_MASK[] = {
+	 { "DC_GPIO_HPD1_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_RECV", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_A[] = {
+	 { "DC_GPIO_HPD1_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_A", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_A", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_EN[] = {
+	 { "DC_GPIO_HPD1_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_EN", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_Y[] = {
+	 { "DC_GPIO_HPD1_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_Y", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_Y", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_Y", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_MASK[] = {
+	 { "ALLOW_HW_DDCVGA_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "AUX_PADVGA_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUXVGA_POL", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_A[] = {
+	 { "DC_GPIO_DDCVGACLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_EN[] = {
+	 { "DC_GPIO_DDCVGACLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_Y[] = {
+	 { "DC_GPIO_DDCVGACLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_MASK[] = {
+	 { "DC_GPIO_SCL_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SCL_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_SCL_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_PD_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_RECV", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_A[] = {
+	 { "DC_GPIO_SCL_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_A", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_EN[] = {
+	 { "DC_GPIO_SCL_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_Y[] = {
+	 { "DC_GPIO_SCL_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_Y", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_1[] = {
+	 { "GENLK_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GENLK_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SN", 24, 27, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SP", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_2[] = {
+	 { "PWRSEQ_STRENGTH_SN", 16, 19, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SP", 20, 23, &umr_bitfield_default },
+	 { "STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_STRENGTH[] = {
+	 { "I2C_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "I2C_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_STRENGTH_CONTROL[] = {
+	 { "DVOCLK_SN", 12, 15, &umr_bitfield_default },
+	 { "DVOCLK_SP", 8, 11, &umr_bitfield_default },
+	 { "DVO_LSB_VMODE", 28, 28, &umr_bitfield_default },
+	 { "DVO_MSB_VMODE", 29, 29, &umr_bitfield_default },
+	 { "DVO_SN", 4, 7, &umr_bitfield_default },
+	 { "DVO_SP", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_VREF_CONTROL[] = {
+	 { "DVO_VREFCAL", 4, 7, &umr_bitfield_default },
+	 { "DVO_VREFPON", 0, 0, &umr_bitfield_default },
+	 { "DVO_VREFSEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SKEW_ADJUST[] = {
+	 { "DVO_SKEW_ADJUST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHY_AUX_CNTL[] = {
+	 { "AUX_PAD_RXSEL", 16, 16, &umr_bitfield_default },
+	 { "AUX_PAD_SLEWN", 12, 12, &umr_bitfield_default },
+	 { "AUX_PAD_WAKE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_ENABLE[] = {
+	 { "DAC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR_ACK", 5, 5, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR", 4, 4, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_POINTER_SKEW", 2, 3, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_TVOUT_SIM", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SOURCE_SELECT[] = {
+	 { "DAC_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DAC_TV_SELECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_EN[] = {
+	 { "DAC_CRC_CONT_EN", 16, 16, &umr_bitfield_default },
+	 { "DAC_CRC_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_CONTROL[] = {
+	 { "DAC_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_ONLY_BLANKb", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB_MASK[] = {
+	 { "DAC_CRC_SIG_BLUE_MASK", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN_MASK", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED_MASK", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL_MASK[] = {
+	 { "DAC_CRC_SIG_CONTROL_MASK", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB[] = {
+	 { "DAC_CRC_SIG_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL[] = {
+	 { "DAC_CRC_SIG_CONTROL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SYNC_TRISTATE_CONTROL[] = {
+	 { "DAC_HSYNCA_TRISTATE", 0, 0, &umr_bitfield_default },
+	 { "DAC_SYNCA_TRISTATE", 16, 16, &umr_bitfield_default },
+	 { "DAC_VSYNCA_TRISTATE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_STEREOSYNC_SELECT[] = {
+	 { "DAC_STEREOSYNC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL[] = {
+	 { "DAC_AUTODETECT_CHECK_MASK", 16, 18, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_FRAME_TIME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL2[] = {
+	 { "DAC_AUTODETECT_POWERUP_COUNTER", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_TESTMODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL3[] = {
+	 { "DAC_AUTODET_COMPARATOR_IN_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODET_COMPARATOR_OUT_DELAY", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_STATUS[] = {
+	 { "DAC_AUTODETECT_BLUE_SENSE", 24, 25, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CONNECT", 4, 4, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_GREEN_SENSE", 16, 17, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_RED_SENSE", 8, 9, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_INT_CONTROL[] = {
+	 { "DAC_AUTODETECT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_INT_ENABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_OUTPUT_CNTL[] = {
+	 { "DAC_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_ON_BLANKb_ONLY", 24, 24, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_DATA[] = {
+	 { "DAC_FORCE_DATA", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_POWERDOWN[] = {
+	 { "DAC_POWERDOWN_BLUE", 8, 8, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_GREEN", 16, 16, &umr_bitfield_default },
+	 { "DAC_POWERDOWN", 0, 0, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_RED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CONTROL[] = {
+	 { "DAC_DFORCE_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_TV_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DAC_ZSCALE_SHIFT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_ENABLE[] = {
+	 { "DAC_B_ASYNC_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "DAC_COMP_DDET_REF_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMP_SDET_REF_EN", 8, 8, &umr_bitfield_default },
+	 { "DAC_G_ASYNC_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "DAC_R_ASYNC_ENABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_OUTPUT[] = {
+	 { "DAC_COMPARATOR_OUTPUT_BLUE", 1, 1, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_GREEN", 2, 2, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_RED", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_PWR_CNTL[] = {
+	 { "DAC_BG_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_PWRCNTL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_DFT_CONFIG[] = {
+	 { "DAC_DFT_CONFIG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FIFO_STATUS[] = {
+	 { "DAC_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DAC_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+	 { "DAC_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DAC_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DAC_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DAC_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED0[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_MACRO_CNTL[] = {
+	 { "BPHYC_DAC_ANALOG_MONITOR", 24, 27, &umr_bitfield_default },
+	 { "BPHYC_DAC_BANDGAP_ADJUSTMENT", 16, 21, &umr_bitfield_default },
+	 { "BPHYC_DAC_COREMON", 28, 28, &umr_bitfield_default },
+	 { "BPHYC_DAC_WHITE_FINE_CONTROL", 8, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_WHITE_LEVEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_AUTO_CALIB_CONTROL[] = {
+	 { "BPHYC_DAC_CAL_COMPLETE", 28, 28, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_DACADJ_EN", 2, 2, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_EN", 1, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_INITB", 0, 0, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_MASK", 20, 22, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_WAIT_ADJUST", 4, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED3[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXA_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXA_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXA_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXA_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXA_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXA_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXB_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXB_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXB_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXB_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXB_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXB_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_CONTROL[] = {
+	 { "CUR_INV_TRANS_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "CURSOR_2X_MAGNIFY", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_EN", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_FORCE_MC_ON", 20, 20, &umr_bitfield_default },
+	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_URGENT_CONTROL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS[] = {
+	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SIZE[] = {
+	 { "CURSOR_HEIGHT", 0, 5, &umr_bitfield_default },
+	 { "CURSOR_WIDTH", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS_HIGH[] = {
+	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_POSITION[] = {
+	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
+	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_HOT_SPOT[] = {
+	 { "CURSOR_HOT_SPOT_X", 16, 21, &umr_bitfield_default },
+	 { "CURSOR_HOT_SPOT_Y", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR1[] = {
+	 { "CUR_COLOR1_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR1_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR1_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR2[] = {
+	 { "CUR_COLOR2_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR2_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR2_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_UPDATE[] = {
+	 { "CURSOR_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_MODE[] = {
+	 { "DC_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_INDEX[] = {
+	 { "DC_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_SEQ_COLOR[] = {
+	 { "DC_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_PWL_DATA[] = {
+	 { "DC_LUT_BASE", 0, 15, &umr_bitfield_default },
+	 { "DC_LUT_DELTA", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_30_COLOR[] = {
+	 { "DC_LUT_COLOR_10_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_VGA_ACCESS_ENABLE[] = {
+	 { "DC_LUT_VGA_ACCESS_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WRITE_EN_MASK[] = {
+	 { "DC_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_AUTOFILL[] = {
+	 { "DC_LUT_AUTOFILL_DONE", 1, 1, &umr_bitfield_default },
+	 { "DC_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_CONTROL[] = {
+	 { "DC_LUT_DATA_B_FLOAT_POINT_EN", 5, 5, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FORMAT", 6, 7, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_SIGNED_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FLOAT_POINT_EN", 13, 13, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FORMAT", 14, 15, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_SIGNED_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FLOAT_POINT_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FORMAT", 22, 23, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_SIGNED_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_LUT_INC_B", 0, 3, &umr_bitfield_default },
+	 { "DC_LUT_INC_G", 8, 11, &umr_bitfield_default },
+	 { "DC_LUT_INC_R", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_BLUE[] = {
+	 { "DC_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_GREEN[] = {
+	 { "DC_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_RED[] = {
+	 { "DC_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_BLUE[] = {
+	 { "DC_LUT_WHITE_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_GREEN[] = {
+	 { "DC_LUT_WHITE_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_RED[] = {
+	 { "DC_LUT_WHITE_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_REQUEST_FILTER_CNTL[] = {
+	 { "CUR_REQUEST_FILTER_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_MVP_LB_CONTROL[] = {
+	 { "DC_MVP_SPARE_FLOPS", 31, 31, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_IN_CAP", 28, 28, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_SEL", 8, 8, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_STATUS", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_IN_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_LEFT_RIGHT[] = {
+	 { "EXT_OVERSCAN_LEFT", 16, 27, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_RIGHT", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_TOP_BOTTOM[] = {
+	 { "EXT_OVERSCAN_BOTTOM", 0, 11, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_TOP", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL2[] = {
+	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
+	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
+	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_0[] = {
+	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
+	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_1[] = {
+	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_2[] = {
+	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_3[] = {
+	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_4[] = {
+	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_0[] = {
+	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_1[] = {
+	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_2[] = {
+	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_3[] = {
+	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO0[] = {
+	 { "AFMT_AVI_INFO_A", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_B", 10, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_C", 22, 23, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_EC", 28, 30, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_ITC", 31, 31, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_M", 20, 21, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PB1_RSVD", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Q", 26, 27, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_R", 16, 19, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_SC", 24, 25, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_S", 8, 9, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Y", 13, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO1[] = {
+	 { "AFMT_AVI_INFO_CN", 12, 13, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PB4_RSVD", 7, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PR", 8, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_TOP", 16, 31, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_VIC", 0, 6, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_YQ", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO2[] = {
+	 { "AFMT_AVI_INFO_BOTTOM", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_LEFT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO3[] = {
+	 { "AFMT_AVI_INFO_RIGHT", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_VERSION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO0[] = {
+	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO1[] = {
+	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_HDR[] = {
+	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_0[] = {
+	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_1[] = {
+	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_2[] = {
+	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_3[] = {
+	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_4[] = {
+	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_5[] = {
+	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_6[] = {
+	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_7[] = {
+	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO0[] = {
+	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO1[] = {
+	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_0[] = {
+	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
+	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
+	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
+	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
+	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_1[] = {
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
+	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_CONTROL[] = {
+	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL0[] = {
+	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
+	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL1[] = {
+	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
+	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL2[] = {
+	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL3[] = {
+	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_2[] = {
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_RESULT[] = {
+	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_STATUS[] = {
+	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
+	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL[] = {
+	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
+	 { "AFMT_BLANK_TEST_DATA_ON_ENC_ENB", 31, 31, &umr_bitfield_default },
+	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_VBI_PACKET_CONTROL[] = {
+	 { "AFMT_GENERIC0_UPDATE", 2, 2, &umr_bitfield_default },
+	 { "AFMT_GENERIC2_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "AFMT_GENERIC_INDEX", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_INFOFRAME_CONTROL0[] = {
+	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_SRC_CONTROL[] = {
+	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_DBG_DTO_CNTL[] = {
+	 { "AFMT_AUDIO_DTO_DBG_BASE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_DIV", 16, 18, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_MULTI", 12, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_FS_DIV_SEL", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+	 { "STREAM_TYPE_R", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[] = {
+	 { "CC", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[] = {
+	 { "KEEPALIVE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[] = {
+	 { "CONNECTION_LIST_ENTRY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+	 { "TAG", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
+	 { "COLOR", 4, 7, &umr_bitfield_default },
+	 { "MISC", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
+	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
+	 { "LOCATION", 0, 5, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[] = {
+	 { "DP_CONNECTION", 9, 9, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 10, 15, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 8, 8, &umr_bitfield_default },
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[] = {
+	 { "DOWN_MIX_INHIBIT", 7, 7, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 3, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[] = {
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "FORMAT_CODE", 3, 6, &umr_bitfield_default },
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[] = {
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[] = {
+	 { "MULTICHANNEL23_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL23_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[] = {
+	 { "MULTICHANNEL45_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL45_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[] = {
+	 { "MULTICHANNEL67_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL67_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[] = {
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[] = {
+	 { "SINK_INFO_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[] = {
+	 { "SINK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
+	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
+	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
+	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[] = {
+	 { "CONNECTION_LIST_LENGTH", 0, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/dce60_regs.i b/src/lib/ip/dce60_regs.i
new file mode 100644
index 0000000..d3b0911
--- /dev/null
+++ b/src/lib/ip/dce60_regs.i
@@ -0,0 +1,3750 @@
+	{ "ixATTR00", REG_SMC, 0x0000, &ixATTR00[0], sizeof(ixATTR00)/sizeof(ixATTR00[0]), 0, 0 },
+	{ "ixATTR01", REG_SMC, 0x0001, &ixATTR01[0], sizeof(ixATTR01)/sizeof(ixATTR01[0]), 0, 0 },
+	{ "ixATTR02", REG_SMC, 0x0002, &ixATTR02[0], sizeof(ixATTR02)/sizeof(ixATTR02[0]), 0, 0 },
+	{ "ixATTR03", REG_SMC, 0x0003, &ixATTR03[0], sizeof(ixATTR03)/sizeof(ixATTR03[0]), 0, 0 },
+	{ "ixATTR04", REG_SMC, 0x0004, &ixATTR04[0], sizeof(ixATTR04)/sizeof(ixATTR04[0]), 0, 0 },
+	{ "ixATTR05", REG_SMC, 0x0005, &ixATTR05[0], sizeof(ixATTR05)/sizeof(ixATTR05[0]), 0, 0 },
+	{ "ixATTR06", REG_SMC, 0x0006, &ixATTR06[0], sizeof(ixATTR06)/sizeof(ixATTR06[0]), 0, 0 },
+	{ "ixATTR07", REG_SMC, 0x0007, &ixATTR07[0], sizeof(ixATTR07)/sizeof(ixATTR07[0]), 0, 0 },
+	{ "ixATTR08", REG_SMC, 0x0008, &ixATTR08[0], sizeof(ixATTR08)/sizeof(ixATTR08[0]), 0, 0 },
+	{ "ixATTR09", REG_SMC, 0x0009, &ixATTR09[0], sizeof(ixATTR09)/sizeof(ixATTR09[0]), 0, 0 },
+	{ "ixATTR0A", REG_SMC, 0x000A, &ixATTR0A[0], sizeof(ixATTR0A)/sizeof(ixATTR0A[0]), 0, 0 },
+	{ "ixATTR0B", REG_SMC, 0x000B, &ixATTR0B[0], sizeof(ixATTR0B)/sizeof(ixATTR0B[0]), 0, 0 },
+	{ "ixATTR0C", REG_SMC, 0x000C, &ixATTR0C[0], sizeof(ixATTR0C)/sizeof(ixATTR0C[0]), 0, 0 },
+	{ "ixATTR0D", REG_SMC, 0x000D, &ixATTR0D[0], sizeof(ixATTR0D)/sizeof(ixATTR0D[0]), 0, 0 },
+	{ "ixATTR0E", REG_SMC, 0x000E, &ixATTR0E[0], sizeof(ixATTR0E)/sizeof(ixATTR0E[0]), 0, 0 },
+	{ "ixATTR0F", REG_SMC, 0x000F, &ixATTR0F[0], sizeof(ixATTR0F)/sizeof(ixATTR0F[0]), 0, 0 },
+	{ "ixATTR10", REG_SMC, 0x0010, &ixATTR10[0], sizeof(ixATTR10)/sizeof(ixATTR10[0]), 0, 0 },
+	{ "ixATTR11", REG_SMC, 0x0011, &ixATTR11[0], sizeof(ixATTR11)/sizeof(ixATTR11[0]), 0, 0 },
+	{ "ixATTR12", REG_SMC, 0x0012, &ixATTR12[0], sizeof(ixATTR12)/sizeof(ixATTR12[0]), 0, 0 },
+	{ "ixATTR13", REG_SMC, 0x0013, &ixATTR13[0], sizeof(ixATTR13)/sizeof(ixATTR13[0]), 0, 0 },
+	{ "ixATTR14", REG_SMC, 0x0014, &ixATTR14[0], sizeof(ixATTR14)/sizeof(ixATTR14[0]), 0, 0 },
+	{ "ixCRT15", REG_SMC, 0x0015, &ixCRT15[0], sizeof(ixCRT15)/sizeof(ixCRT15[0]), 0, 0 },
+	{ "ixCRT16", REG_SMC, 0x0016, &ixCRT16[0], sizeof(ixCRT16)/sizeof(ixCRT16[0]), 0, 0 },
+	{ "ixCRT17", REG_SMC, 0x0017, &ixCRT17[0], sizeof(ixCRT17)/sizeof(ixCRT17[0]), 0, 0 },
+	{ "ixCRT18", REG_SMC, 0x0018, &ixCRT18[0], sizeof(ixCRT18)/sizeof(ixCRT18[0]), 0, 0 },
+	{ "ixCRT1E", REG_SMC, 0x001E, &ixCRT1E[0], sizeof(ixCRT1E)/sizeof(ixCRT1E[0]), 0, 0 },
+	{ "ixCRT1F", REG_SMC, 0x001F, &ixCRT1F[0], sizeof(ixCRT1F)/sizeof(ixCRT1F[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x0020, &ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x0021, &ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x0022, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x0023, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x0024, &ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x0025, &ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_G", REG_SMC, 0x0026, &ixDP_AUX2_DEBUG_G[0], sizeof(ixDP_AUX2_DEBUG_G)/sizeof(ixDP_AUX2_DEBUG_G[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_H", REG_SMC, 0x0027, &ixDP_AUX2_DEBUG_H[0], sizeof(ixDP_AUX2_DEBUG_H)/sizeof(ixDP_AUX2_DEBUG_H[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x0028, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x0029, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x002A, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x002B, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x002C, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x002D, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x002E, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x002F, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x0030, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x0031, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x0032, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x0033, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x0034, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x0035, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x0036, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x0037, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x0038, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x003A, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x003B, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x003C, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x003D, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x003E, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x003F, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x0040, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x0041, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x0042, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_D", REG_SMC, 0x0043, &ixDP_AUX4_DEBUG_D[0], sizeof(ixDP_AUX4_DEBUG_D)/sizeof(ixDP_AUX4_DEBUG_D[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_E", REG_SMC, 0x0044, &ixDP_AUX4_DEBUG_E[0], sizeof(ixDP_AUX4_DEBUG_E)/sizeof(ixDP_AUX4_DEBUG_E[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_F", REG_SMC, 0x0045, &ixDP_AUX4_DEBUG_F[0], sizeof(ixDP_AUX4_DEBUG_F)/sizeof(ixDP_AUX4_DEBUG_F[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_G", REG_SMC, 0x0046, &ixDP_AUX4_DEBUG_G[0], sizeof(ixDP_AUX4_DEBUG_G)/sizeof(ixDP_AUX4_DEBUG_G[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_H", REG_SMC, 0x0047, &ixDP_AUX4_DEBUG_H[0], sizeof(ixDP_AUX4_DEBUG_H)/sizeof(ixDP_AUX4_DEBUG_H[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_I", REG_SMC, 0x0048, &ixDP_AUX4_DEBUG_I[0], sizeof(ixDP_AUX4_DEBUG_I)/sizeof(ixDP_AUX4_DEBUG_I[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x0054, &ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x0055, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x0056, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x0057, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x0058, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x0059, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x005A, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x005B, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x005C, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x005D, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x005E, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x005F, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x0060, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x0061, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x0062, &ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_A", REG_SMC, 0x0070, &ixDP_AUX5_DEBUG_A[0], sizeof(ixDP_AUX5_DEBUG_A)/sizeof(ixDP_AUX5_DEBUG_A[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_B", REG_SMC, 0x0071, &ixDP_AUX5_DEBUG_B[0], sizeof(ixDP_AUX5_DEBUG_B)/sizeof(ixDP_AUX5_DEBUG_B[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_C", REG_SMC, 0x0072, &ixDP_AUX5_DEBUG_C[0], sizeof(ixDP_AUX5_DEBUG_C)/sizeof(ixDP_AUX5_DEBUG_C[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_D", REG_SMC, 0x0073, &ixDP_AUX5_DEBUG_D[0], sizeof(ixDP_AUX5_DEBUG_D)/sizeof(ixDP_AUX5_DEBUG_D[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_E", REG_SMC, 0x0074, &ixDP_AUX5_DEBUG_E[0], sizeof(ixDP_AUX5_DEBUG_E)/sizeof(ixDP_AUX5_DEBUG_E[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_F", REG_SMC, 0x0075, &ixDP_AUX5_DEBUG_F[0], sizeof(ixDP_AUX5_DEBUG_F)/sizeof(ixDP_AUX5_DEBUG_F[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_G", REG_SMC, 0x0076, &ixDP_AUX5_DEBUG_G[0], sizeof(ixDP_AUX5_DEBUG_G)/sizeof(ixDP_AUX5_DEBUG_G[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_H", REG_SMC, 0x0077, &ixDP_AUX5_DEBUG_H[0], sizeof(ixDP_AUX5_DEBUG_H)/sizeof(ixDP_AUX5_DEBUG_H[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_I", REG_SMC, 0x0078, &ixDP_AUX5_DEBUG_I[0], sizeof(ixDP_AUX5_DEBUG_I)/sizeof(ixDP_AUX5_DEBUG_I[0]), 0, 0 },
+	{ "ixVGADCC_DBG_DCCIF_C", REG_SMC, 0x007E, &ixVGADCC_DBG_DCCIF_C[0], sizeof(ixVGADCC_DBG_DCCIF_C)/sizeof(ixVGADCC_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_A", REG_SMC, 0x0080, &ixDP_AUX6_DEBUG_A[0], sizeof(ixDP_AUX6_DEBUG_A)/sizeof(ixDP_AUX6_DEBUG_A[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_B", REG_SMC, 0x0081, &ixDP_AUX6_DEBUG_B[0], sizeof(ixDP_AUX6_DEBUG_B)/sizeof(ixDP_AUX6_DEBUG_B[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_C", REG_SMC, 0x0082, &ixDP_AUX6_DEBUG_C[0], sizeof(ixDP_AUX6_DEBUG_C)/sizeof(ixDP_AUX6_DEBUG_C[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_D", REG_SMC, 0x0083, &ixDP_AUX6_DEBUG_D[0], sizeof(ixDP_AUX6_DEBUG_D)/sizeof(ixDP_AUX6_DEBUG_D[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_E", REG_SMC, 0x0084, &ixDP_AUX6_DEBUG_E[0], sizeof(ixDP_AUX6_DEBUG_E)/sizeof(ixDP_AUX6_DEBUG_E[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_F", REG_SMC, 0x0085, &ixDP_AUX6_DEBUG_F[0], sizeof(ixDP_AUX6_DEBUG_F)/sizeof(ixDP_AUX6_DEBUG_F[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_G", REG_SMC, 0x0086, &ixDP_AUX6_DEBUG_G[0], sizeof(ixDP_AUX6_DEBUG_G)/sizeof(ixDP_AUX6_DEBUG_G[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_H", REG_SMC, 0x0087, &ixDP_AUX6_DEBUG_H[0], sizeof(ixDP_AUX6_DEBUG_H)/sizeof(ixDP_AUX6_DEBUG_H[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_I", REG_SMC, 0x0088, &ixDP_AUX6_DEBUG_I[0], sizeof(ixDP_AUX6_DEBUG_I)/sizeof(ixDP_AUX6_DEBUG_I[0]), 0, 0 },
+	{ "mmVGA_RENDER_CONTROL", REG_MMIO, 0x00C0, &mmVGA_RENDER_CONTROL[0], sizeof(mmVGA_RENDER_CONTROL)/sizeof(mmVGA_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SEQUENCER_RESET_CONTROL", REG_MMIO, 0x00C1, &mmVGA_SEQUENCER_RESET_CONTROL[0], sizeof(mmVGA_SEQUENCER_RESET_CONTROL)/sizeof(mmVGA_SEQUENCER_RESET_CONTROL[0]), 0, 0 },
+	{ "mmVGA_MODE_CONTROL", REG_MMIO, 0x00C2, &mmVGA_MODE_CONTROL[0], sizeof(mmVGA_MODE_CONTROL)/sizeof(mmVGA_MODE_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SURFACE_PITCH_SELECT", REG_MMIO, 0x00C3, &mmVGA_SURFACE_PITCH_SELECT[0], sizeof(mmVGA_SURFACE_PITCH_SELECT)/sizeof(mmVGA_SURFACE_PITCH_SELECT[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS", REG_MMIO, 0x00C4, &mmVGA_MEMORY_BASE_ADDRESS[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS)/sizeof(mmVGA_MEMORY_BASE_ADDRESS[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_INDEX", REG_MMIO, 0x00C5, &mmVGA_TEST_DEBUG_INDEX[0], sizeof(mmVGA_TEST_DEBUG_INDEX)/sizeof(mmVGA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmVGA_DISPBUF1_SURFACE_ADDR", REG_MMIO, 0x00C6, &mmVGA_DISPBUF1_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF1_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF1_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_DATA", REG_MMIO, 0x00C7, &mmVGA_TEST_DEBUG_DATA[0], sizeof(mmVGA_TEST_DEBUG_DATA)/sizeof(mmVGA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGA_DISPBUF2_SURFACE_ADDR", REG_MMIO, 0x00C8, &mmVGA_DISPBUF2_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF2_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF2_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS_HIGH", REG_MMIO, 0x00C9, &mmVGA_MEMORY_BASE_ADDRESS_HIGH[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH)/sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmVGA_HDP_CONTROL", REG_MMIO, 0x00CA, &mmVGA_HDP_CONTROL[0], sizeof(mmVGA_HDP_CONTROL)/sizeof(mmVGA_HDP_CONTROL[0]), 0, 0 },
+	{ "mmVGA_CACHE_CONTROL", REG_MMIO, 0x00CB, &mmVGA_CACHE_CONTROL[0], sizeof(mmVGA_CACHE_CONTROL)/sizeof(mmVGA_CACHE_CONTROL[0]), 0, 0 },
+	{ "mmD1VGA_CONTROL", REG_MMIO, 0x00CC, &mmD1VGA_CONTROL[0], sizeof(mmD1VGA_CONTROL)/sizeof(mmD1VGA_CONTROL[0]), 0, 0 },
+	{ "mmD2VGA_CONTROL", REG_MMIO, 0x00CE, &mmD2VGA_CONTROL[0], sizeof(mmD2VGA_CONTROL)/sizeof(mmD2VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_HW_DEBUG", REG_MMIO, 0x00CF, &mmVGA_HW_DEBUG[0], sizeof(mmVGA_HW_DEBUG)/sizeof(mmVGA_HW_DEBUG[0]), 0, 0 },
+	{ "mmVGA_STATUS", REG_MMIO, 0x00D0, &mmVGA_STATUS[0], sizeof(mmVGA_STATUS)/sizeof(mmVGA_STATUS[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_CONTROL", REG_MMIO, 0x00D1, &mmVGA_INTERRUPT_CONTROL[0], sizeof(mmVGA_INTERRUPT_CONTROL)/sizeof(mmVGA_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmVGA_STATUS_CLEAR", REG_MMIO, 0x00D2, &mmVGA_STATUS_CLEAR[0], sizeof(mmVGA_STATUS_CLEAR)/sizeof(mmVGA_STATUS_CLEAR[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_STATUS", REG_MMIO, 0x00D3, &mmVGA_INTERRUPT_STATUS[0], sizeof(mmVGA_INTERRUPT_STATUS)/sizeof(mmVGA_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmVGA_MAIN_CONTROL", REG_MMIO, 0x00D4, &mmVGA_MAIN_CONTROL[0], sizeof(mmVGA_MAIN_CONTROL)/sizeof(mmVGA_MAIN_CONTROL[0]), 0, 0 },
+	{ "mmVGA_TEST_CONTROL", REG_MMIO, 0x00D5, &mmVGA_TEST_CONTROL[0], sizeof(mmVGA_TEST_CONTROL)/sizeof(mmVGA_TEST_CONTROL[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_INDEX", REG_MMIO, 0x00D6, &mmVGA_DEBUG_READBACK_INDEX[0], sizeof(mmVGA_DEBUG_READBACK_INDEX)/sizeof(mmVGA_DEBUG_READBACK_INDEX[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_DATA", REG_MMIO, 0x00D7, &mmVGA_DEBUG_READBACK_DATA[0], sizeof(mmVGA_DEBUG_READBACK_DATA)/sizeof(mmVGA_DEBUG_READBACK_DATA[0]), 0, 0 },
+	{ "mmVGA25_PPLL_REF_DIV", REG_MMIO, 0x00D8, &mmVGA25_PPLL_REF_DIV[0], sizeof(mmVGA25_PPLL_REF_DIV)/sizeof(mmVGA25_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmVGA28_PPLL_REF_DIV", REG_MMIO, 0x00D9, &mmVGA28_PPLL_REF_DIV[0], sizeof(mmVGA28_PPLL_REF_DIV)/sizeof(mmVGA28_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmVGA41_PPLL_REF_DIV", REG_MMIO, 0x00DA, &mmVGA41_PPLL_REF_DIV[0], sizeof(mmVGA41_PPLL_REF_DIV)/sizeof(mmVGA41_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmVGA25_PPLL_FB_DIV", REG_MMIO, 0x00DC, &mmVGA25_PPLL_FB_DIV[0], sizeof(mmVGA25_PPLL_FB_DIV)/sizeof(mmVGA25_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmVGA28_PPLL_FB_DIV", REG_MMIO, 0x00DD, &mmVGA28_PPLL_FB_DIV[0], sizeof(mmVGA28_PPLL_FB_DIV)/sizeof(mmVGA28_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmVGA41_PPLL_FB_DIV", REG_MMIO, 0x00DE, &mmVGA41_PPLL_FB_DIV[0], sizeof(mmVGA41_PPLL_FB_DIV)/sizeof(mmVGA41_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmVGA25_PPLL_POST_DIV", REG_MMIO, 0x00E0, &mmVGA25_PPLL_POST_DIV[0], sizeof(mmVGA25_PPLL_POST_DIV)/sizeof(mmVGA25_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmVGA28_PPLL_POST_DIV", REG_MMIO, 0x00E1, &mmVGA28_PPLL_POST_DIV[0], sizeof(mmVGA28_PPLL_POST_DIV)/sizeof(mmVGA28_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmVGA41_PPLL_POST_DIV", REG_MMIO, 0x00E2, &mmVGA41_PPLL_POST_DIV[0], sizeof(mmVGA41_PPLL_POST_DIV)/sizeof(mmVGA41_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmVGA25_PPLL_ANALOG", REG_MMIO, 0x00E4, &mmVGA25_PPLL_ANALOG[0], sizeof(mmVGA25_PPLL_ANALOG)/sizeof(mmVGA25_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmVGA28_PPLL_ANALOG", REG_MMIO, 0x00E5, &mmVGA28_PPLL_ANALOG[0], sizeof(mmVGA28_PPLL_ANALOG)/sizeof(mmVGA28_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmVGA41_PPLL_ANALOG", REG_MMIO, 0x00E6, &mmVGA41_PPLL_ANALOG[0], sizeof(mmVGA41_PPLL_ANALOG)/sizeof(mmVGA41_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmCRTC8_DATA", REG_MMIO, 0x00ED, &mmCRTC8_DATA[0], sizeof(mmCRTC8_DATA)/sizeof(mmCRTC8_DATA[0]), 0, 0 },
+	{ "mmGENFC_WT", REG_MMIO, 0x00EE, &mmGENFC_WT[0], sizeof(mmGENFC_WT)/sizeof(mmGENFC_WT[0]), 0, 0 },
+	{ "mmATTRDR", REG_MMIO, 0x00F0, &mmATTRDR[0], sizeof(mmATTRDR)/sizeof(mmATTRDR[0]), 0, 0 },
+	{ "mmDAC_MASK", REG_MMIO, 0x00F1, &mmDAC_MASK[0], sizeof(mmDAC_MASK)/sizeof(mmDAC_MASK[0]), 0, 0 },
+	{ "mmDAC_DATA", REG_MMIO, 0x00F2, &mmDAC_DATA[0], sizeof(mmDAC_DATA)/sizeof(mmDAC_DATA[0]), 0, 0 },
+	{ "mmGENMO_RD", REG_MMIO, 0x00F3, &mmGENMO_RD[0], sizeof(mmGENMO_RD)/sizeof(mmGENMO_RD[0]), 0, 0 },
+	{ "mmD3VGA_CONTROL", REG_MMIO, 0x00F8, &mmD3VGA_CONTROL[0], sizeof(mmD3VGA_CONTROL)/sizeof(mmD3VGA_CONTROL[0]), 0, 0 },
+	{ "mmD4VGA_CONTROL", REG_MMIO, 0x00F9, &mmD4VGA_CONTROL[0], sizeof(mmD4VGA_CONTROL)/sizeof(mmD4VGA_CONTROL[0]), 0, 0 },
+	{ "mmD5VGA_CONTROL", REG_MMIO, 0x00FA, &mmD5VGA_CONTROL[0], sizeof(mmD5VGA_CONTROL)/sizeof(mmD5VGA_CONTROL[0]), 0, 0 },
+	{ "mmD6VGA_CONTROL", REG_MMIO, 0x00FB, &mmD6VGA_CONTROL[0], sizeof(mmD6VGA_CONTROL)/sizeof(mmD6VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SOURCE_SELECT", REG_MMIO, 0x00FC, &mmVGA_SOURCE_SELECT[0], sizeof(mmVGA_SOURCE_SELECT)/sizeof(mmVGA_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDCCG_GTC_CNTL", REG_MMIO, 0x0120, &mmDCCG_GTC_CNTL[0], sizeof(mmDCCG_GTC_CNTL)/sizeof(mmDCCG_GTC_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_MODULO", REG_MMIO, 0x0122, &mmDCCG_GTC_DTO_MODULO[0], sizeof(mmDCCG_GTC_DTO_MODULO)/sizeof(mmDCCG_GTC_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_GTC_CURRENT", REG_MMIO, 0x0123, &mmDCCG_GTC_CURRENT[0], sizeof(mmDCCG_GTC_CURRENT)/sizeof(mmDCCG_GTC_CURRENT[0]), 0, 0 },
+	{ "mmDENTIST_DISPCLK_CNTL", REG_MMIO, 0x0124, &mmDENTIST_DISPCLK_CNTL[0], sizeof(mmDENTIST_DISPCLK_CNTL)/sizeof(mmDENTIST_DISPCLK_CNTL[0]), 0, 0 },
+	{ "mmDAC_CLK_ENABLE", REG_MMIO, 0x0128, &mmDAC_CLK_ENABLE[0], sizeof(mmDAC_CLK_ENABLE)/sizeof(mmDAC_CLK_ENABLE[0]), 0, 0 },
+	{ "mmDVO_CLK_ENABLE", REG_MMIO, 0x0129, &mmDVO_CLK_ENABLE[0], sizeof(mmDVO_CLK_ENABLE)/sizeof(mmDVO_CLK_ENABLE[0]), 0, 0 },
+	{ "mmMILLISECOND_TIME_BASE_DIV", REG_MMIO, 0x0130, &mmMILLISECOND_TIME_BASE_DIV[0], sizeof(mmMILLISECOND_TIME_BASE_DIV)/sizeof(mmMILLISECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDISPCLK_FREQ_CHANGE_CNTL", REG_MMIO, 0x0131, &mmDISPCLK_FREQ_CHANGE_CNTL[0], sizeof(mmDISPCLK_FREQ_CHANGE_CNTL)/sizeof(mmDISPCLK_FREQ_CHANGE_CNTL[0]), 0, 0 },
+	{ "mmLIGHT_SLEEP_CNTL", REG_MMIO, 0x0132, &mmLIGHT_SLEEP_CNTL[0], sizeof(mmLIGHT_SLEEP_CNTL)/sizeof(mmLIGHT_SLEEP_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PERFMON_CNTL", REG_MMIO, 0x0133, &mmDCCG_PERFMON_CNTL[0], sizeof(mmDCCG_PERFMON_CNTL)/sizeof(mmDCCG_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GATE_DISABLE_CNTL", REG_MMIO, 0x0134, &mmDCCG_GATE_DISABLE_CNTL[0], sizeof(mmDCCG_GATE_DISABLE_CNTL)/sizeof(mmDCCG_GATE_DISABLE_CNTL[0]), 0, 0 },
+	{ "mmDISPCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x0135, &mmDISPCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmSCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x0136, &mmSCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmDCCG_CAC_STATUS", REG_MMIO, 0x0137, &mmDCCG_CAC_STATUS[0], sizeof(mmDCCG_CAC_STATUS)/sizeof(mmDCCG_CAC_STATUS[0]), 0, 0 },
+	{ "mmPIXCLK1_RESYNC_CNTL", REG_MMIO, 0x0138, &mmPIXCLK1_RESYNC_CNTL[0], sizeof(mmPIXCLK1_RESYNC_CNTL)/sizeof(mmPIXCLK1_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPIXCLK2_RESYNC_CNTL", REG_MMIO, 0x0139, &mmPIXCLK2_RESYNC_CNTL[0], sizeof(mmPIXCLK2_RESYNC_CNTL)/sizeof(mmPIXCLK2_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPIXCLK0_RESYNC_CNTL", REG_MMIO, 0x013A, &mmPIXCLK0_RESYNC_CNTL[0], sizeof(mmPIXCLK0_RESYNC_CNTL)/sizeof(mmPIXCLK0_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmMICROSECOND_TIME_BASE_DIV", REG_MMIO, 0x013B, &mmMICROSECOND_TIME_BASE_DIV[0], sizeof(mmMICROSECOND_TIME_BASE_DIV)/sizeof(mmMICROSECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDISPPLL_BG_CNTL", REG_MMIO, 0x013C, &mmDISPPLL_BG_CNTL[0], sizeof(mmDISPPLL_BG_CNTL)/sizeof(mmDISPPLL_BG_CNTL[0]), 0, 0 },
+	{ "mmDIG_SOFT_RESET", REG_MMIO, 0x013D, &mmDIG_SOFT_RESET[0], sizeof(mmDIG_SOFT_RESET)/sizeof(mmDIG_SOFT_RESET[0]), 0, 0 },
+	{ "mmCRTC0_PIXEL_RATE_CNTL", REG_MMIO, 0x0140, &mmCRTC0_PIXEL_RATE_CNTL[0], sizeof(mmCRTC0_PIXEL_RATE_CNTL)/sizeof(mmCRTC0_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO0_PHASE", REG_MMIO, 0x0141, &mmDP_DTO0_PHASE[0], sizeof(mmDP_DTO0_PHASE)/sizeof(mmDP_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO0_MODULO", REG_MMIO, 0x0142, &mmDP_DTO0_MODULO[0], sizeof(mmDP_DTO0_MODULO)/sizeof(mmDP_DTO0_MODULO[0]), 0, 0 },
+	{ "mmCRTC1_PIXEL_RATE_CNTL", REG_MMIO, 0x0144, &mmCRTC1_PIXEL_RATE_CNTL[0], sizeof(mmCRTC1_PIXEL_RATE_CNTL)/sizeof(mmCRTC1_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO1_PHASE", REG_MMIO, 0x0145, &mmDP_DTO1_PHASE[0], sizeof(mmDP_DTO1_PHASE)/sizeof(mmDP_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO1_MODULO", REG_MMIO, 0x0146, &mmDP_DTO1_MODULO[0], sizeof(mmDP_DTO1_MODULO)/sizeof(mmDP_DTO1_MODULO[0]), 0, 0 },
+	{ "mmCRTC2_PIXEL_RATE_CNTL", REG_MMIO, 0x0148, &mmCRTC2_PIXEL_RATE_CNTL[0], sizeof(mmCRTC2_PIXEL_RATE_CNTL)/sizeof(mmCRTC2_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO2_PHASE", REG_MMIO, 0x0149, &mmDP_DTO2_PHASE[0], sizeof(mmDP_DTO2_PHASE)/sizeof(mmDP_DTO2_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO2_MODULO", REG_MMIO, 0x014A, &mmDP_DTO2_MODULO[0], sizeof(mmDP_DTO2_MODULO)/sizeof(mmDP_DTO2_MODULO[0]), 0, 0 },
+	{ "mmCRTC3_PIXEL_RATE_CNTL", REG_MMIO, 0x014C, &mmCRTC3_PIXEL_RATE_CNTL[0], sizeof(mmCRTC3_PIXEL_RATE_CNTL)/sizeof(mmCRTC3_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO3_PHASE", REG_MMIO, 0x014D, &mmDP_DTO3_PHASE[0], sizeof(mmDP_DTO3_PHASE)/sizeof(mmDP_DTO3_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO3_MODULO", REG_MMIO, 0x014E, &mmDP_DTO3_MODULO[0], sizeof(mmDP_DTO3_MODULO)/sizeof(mmDP_DTO3_MODULO[0]), 0, 0 },
+	{ "mmCRTC4_PIXEL_RATE_CNTL", REG_MMIO, 0x0150, &mmCRTC4_PIXEL_RATE_CNTL[0], sizeof(mmCRTC4_PIXEL_RATE_CNTL)/sizeof(mmCRTC4_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO4_PHASE", REG_MMIO, 0x0151, &mmDP_DTO4_PHASE[0], sizeof(mmDP_DTO4_PHASE)/sizeof(mmDP_DTO4_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO4_MODULO", REG_MMIO, 0x0152, &mmDP_DTO4_MODULO[0], sizeof(mmDP_DTO4_MODULO)/sizeof(mmDP_DTO4_MODULO[0]), 0, 0 },
+	{ "mmCRTC5_PIXEL_RATE_CNTL", REG_MMIO, 0x0154, &mmCRTC5_PIXEL_RATE_CNTL[0], sizeof(mmCRTC5_PIXEL_RATE_CNTL)/sizeof(mmCRTC5_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO5_PHASE", REG_MMIO, 0x0155, &mmDP_DTO5_PHASE[0], sizeof(mmDP_DTO5_PHASE)/sizeof(mmDP_DTO5_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO5_MODULO", REG_MMIO, 0x0156, &mmDP_DTO5_MODULO[0], sizeof(mmDP_DTO5_MODULO)/sizeof(mmDP_DTO5_MODULO[0]), 0, 0 },
+	{ "mmDCFE0_SOFT_RESET", REG_MMIO, 0x0158, &mmDCFE0_SOFT_RESET[0], sizeof(mmDCFE0_SOFT_RESET)/sizeof(mmDCFE0_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE1_SOFT_RESET", REG_MMIO, 0x0159, &mmDCFE1_SOFT_RESET[0], sizeof(mmDCFE1_SOFT_RESET)/sizeof(mmDCFE1_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE2_SOFT_RESET", REG_MMIO, 0x015A, &mmDCFE2_SOFT_RESET[0], sizeof(mmDCFE2_SOFT_RESET)/sizeof(mmDCFE2_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE3_SOFT_RESET", REG_MMIO, 0x015B, &mmDCFE3_SOFT_RESET[0], sizeof(mmDCFE3_SOFT_RESET)/sizeof(mmDCFE3_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE4_SOFT_RESET", REG_MMIO, 0x015C, &mmDCFE4_SOFT_RESET[0], sizeof(mmDCFE4_SOFT_RESET)/sizeof(mmDCFE4_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE5_SOFT_RESET", REG_MMIO, 0x015D, &mmDCFE5_SOFT_RESET[0], sizeof(mmDCFE5_SOFT_RESET)/sizeof(mmDCFE5_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCI_SOFT_RESET", REG_MMIO, 0x015E, &mmDCI_SOFT_RESET[0], sizeof(mmDCI_SOFT_RESET)/sizeof(mmDCI_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCCG_SOFT_RESET", REG_MMIO, 0x015F, &mmDCCG_SOFT_RESET[0], sizeof(mmDCCG_SOFT_RESET)/sizeof(mmDCCG_SOFT_RESET[0]), 0, 0 },
+	{ "mmSYMCLKA_CLOCK_ENABLE", REG_MMIO, 0x0160, &mmSYMCLKA_CLOCK_ENABLE[0], sizeof(mmSYMCLKA_CLOCK_ENABLE)/sizeof(mmSYMCLKA_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmSYMCLKB_CLOCK_ENABLE", REG_MMIO, 0x0161, &mmSYMCLKB_CLOCK_ENABLE[0], sizeof(mmSYMCLKB_CLOCK_ENABLE)/sizeof(mmSYMCLKB_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmSYMCLKC_CLOCK_ENABLE", REG_MMIO, 0x0162, &mmSYMCLKC_CLOCK_ENABLE[0], sizeof(mmSYMCLKC_CLOCK_ENABLE)/sizeof(mmSYMCLKC_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmSYMCLKD_CLOCK_ENABLE", REG_MMIO, 0x0163, &mmSYMCLKD_CLOCK_ENABLE[0], sizeof(mmSYMCLKD_CLOCK_ENABLE)/sizeof(mmSYMCLKD_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmSYMCLKE_CLOCK_ENABLE", REG_MMIO, 0x0164, &mmSYMCLKE_CLOCK_ENABLE[0], sizeof(mmSYMCLKE_CLOCK_ENABLE)/sizeof(mmSYMCLKE_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmSYMCLKF_CLOCK_ENABLE", REG_MMIO, 0x0165, &mmSYMCLKF_CLOCK_ENABLE[0], sizeof(mmSYMCLKF_CLOCK_ENABLE)/sizeof(mmSYMCLKF_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmUNIPHY_SOFT_RESET", REG_MMIO, 0x0166, &mmUNIPHY_SOFT_RESET[0], sizeof(mmUNIPHY_SOFT_RESET)/sizeof(mmUNIPHY_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCO_SOFT_RESET", REG_MMIO, 0x0167, &mmDCO_SOFT_RESET[0], sizeof(mmDCO_SOFT_RESET)/sizeof(mmDCO_SOFT_RESET[0]), 0, 0 },
+	{ "mmDVOACLKD_CNTL", REG_MMIO, 0x0168, &mmDVOACLKD_CNTL[0], sizeof(mmDVOACLKD_CNTL)/sizeof(mmDVOACLKD_CNTL[0]), 0, 0 },
+	{ "mmDVOACLKC_MVP_CNTL", REG_MMIO, 0x0169, &mmDVOACLKC_MVP_CNTL[0], sizeof(mmDVOACLKC_MVP_CNTL)/sizeof(mmDVOACLKC_MVP_CNTL[0]), 0, 0 },
+	{ "mmDVOACLKC_CNTL", REG_MMIO, 0x016A, &mmDVOACLKC_CNTL[0], sizeof(mmDVOACLKC_CNTL)/sizeof(mmDVOACLKC_CNTL[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO_SOURCE", REG_MMIO, 0x016B, &mmDCCG_AUDIO_DTO_SOURCE[0], sizeof(mmDCCG_AUDIO_DTO_SOURCE)/sizeof(mmDCCG_AUDIO_DTO_SOURCE[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_PHASE", REG_MMIO, 0x016C, &mmDCCG_AUDIO_DTO0_PHASE[0], sizeof(mmDCCG_AUDIO_DTO0_PHASE)/sizeof(mmDCCG_AUDIO_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_MODULE", REG_MMIO, 0x016D, &mmDCCG_AUDIO_DTO0_MODULE[0], sizeof(mmDCCG_AUDIO_DTO0_MODULE)/sizeof(mmDCCG_AUDIO_DTO0_MODULE[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_PHASE", REG_MMIO, 0x0170, &mmDCCG_AUDIO_DTO1_PHASE[0], sizeof(mmDCCG_AUDIO_DTO1_PHASE)/sizeof(mmDCCG_AUDIO_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_MODULE", REG_MMIO, 0x0171, &mmDCCG_AUDIO_DTO1_MODULE[0], sizeof(mmDCCG_AUDIO_DTO1_MODULE)/sizeof(mmDCCG_AUDIO_DTO1_MODULE[0]), 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_INDEX", REG_MMIO, 0x017C, &mmDCCG_TEST_DEBUG_INDEX[0], sizeof(mmDCCG_TEST_DEBUG_INDEX)/sizeof(mmDCCG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_DATA", REG_MMIO, 0x017D, &mmDCCG_TEST_DEBUG_DATA[0], sizeof(mmDCCG_TEST_DEBUG_DATA)/sizeof(mmDCCG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCCG_TEST_CLK_SEL", REG_MMIO, 0x017E, &mmDCCG_TEST_CLK_SEL[0], sizeof(mmDCCG_TEST_CLK_SEL)/sizeof(mmDCCG_TEST_CLK_SEL[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CONFIG", REG_MMIO, 0x02F5, &mmDMIF_ADDR_CONFIG[0], sizeof(mmDMIF_ADDR_CONFIG)/sizeof(mmDMIF_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmDMIF_CONTROL", REG_MMIO, 0x02F6, &mmDMIF_CONTROL[0], sizeof(mmDMIF_CONTROL)/sizeof(mmDMIF_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_STATUS", REG_MMIO, 0x02F7, &mmDMIF_STATUS[0], sizeof(mmDMIF_STATUS)/sizeof(mmDMIF_STATUS[0]), 0, 0 },
+	{ "mmDMIF_HW_DEBUG", REG_MMIO, 0x02F8, &mmDMIF_HW_DEBUG[0], sizeof(mmDMIF_HW_DEBUG)/sizeof(mmDMIF_HW_DEBUG[0]), 0, 0 },
+	{ "mmDMIF_ARBITRATION_CONTROL", REG_MMIO, 0x02F9, &mmDMIF_ARBITRATION_CONTROL[0], sizeof(mmDMIF_ARBITRATION_CONTROL)/sizeof(mmDMIF_ARBITRATION_CONTROL[0]), 0, 0 },
+	{ "mmPIPE0_ARBITRATION_CONTROL3", REG_MMIO, 0x02FA, &mmPIPE0_ARBITRATION_CONTROL3[0], sizeof(mmPIPE0_ARBITRATION_CONTROL3)/sizeof(mmPIPE0_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE1_ARBITRATION_CONTROL3", REG_MMIO, 0x02FB, &mmPIPE1_ARBITRATION_CONTROL3[0], sizeof(mmPIPE1_ARBITRATION_CONTROL3)/sizeof(mmPIPE1_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE2_ARBITRATION_CONTROL3", REG_MMIO, 0x02FC, &mmPIPE2_ARBITRATION_CONTROL3[0], sizeof(mmPIPE2_ARBITRATION_CONTROL3)/sizeof(mmPIPE2_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE3_ARBITRATION_CONTROL3", REG_MMIO, 0x02FD, &mmPIPE3_ARBITRATION_CONTROL3[0], sizeof(mmPIPE3_ARBITRATION_CONTROL3)/sizeof(mmPIPE3_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE4_ARBITRATION_CONTROL3", REG_MMIO, 0x02FE, &mmPIPE4_ARBITRATION_CONTROL3[0], sizeof(mmPIPE4_ARBITRATION_CONTROL3)/sizeof(mmPIPE4_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE5_ARBITRATION_CONTROL3", REG_MMIO, 0x02FF, &mmPIPE5_ARBITRATION_CONTROL3[0], sizeof(mmPIPE5_ARBITRATION_CONTROL3)/sizeof(mmPIPE5_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CALC", REG_MMIO, 0x0300, &mmDMIF_ADDR_CALC[0], sizeof(mmDMIF_ADDR_CALC)/sizeof(mmDMIF_ADDR_CALC[0]), 0, 0 },
+	{ "mmDMIF_STATUS2", REG_MMIO, 0x0301, &mmDMIF_STATUS2[0], sizeof(mmDMIF_STATUS2)/sizeof(mmDMIF_STATUS2[0]), 0, 0 },
+	{ "mmPIPE0_MAX_REQUESTS", REG_MMIO, 0x0302, &mmPIPE0_MAX_REQUESTS[0], sizeof(mmPIPE0_MAX_REQUESTS)/sizeof(mmPIPE0_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE1_MAX_REQUESTS", REG_MMIO, 0x0303, &mmPIPE1_MAX_REQUESTS[0], sizeof(mmPIPE1_MAX_REQUESTS)/sizeof(mmPIPE1_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE2_MAX_REQUESTS", REG_MMIO, 0x0304, &mmPIPE2_MAX_REQUESTS[0], sizeof(mmPIPE2_MAX_REQUESTS)/sizeof(mmPIPE2_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE3_MAX_REQUESTS", REG_MMIO, 0x0305, &mmPIPE3_MAX_REQUESTS[0], sizeof(mmPIPE3_MAX_REQUESTS)/sizeof(mmPIPE3_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE4_MAX_REQUESTS", REG_MMIO, 0x0306, &mmPIPE4_MAX_REQUESTS[0], sizeof(mmPIPE4_MAX_REQUESTS)/sizeof(mmPIPE4_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE5_MAX_REQUESTS", REG_MMIO, 0x0307, &mmPIPE5_MAX_REQUESTS[0], sizeof(mmPIPE5_MAX_REQUESTS)/sizeof(mmPIPE5_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_INDEX", REG_MMIO, 0x0312, &mmDMIF_TEST_DEBUG_INDEX[0], sizeof(mmDMIF_TEST_DEBUG_INDEX)/sizeof(mmDMIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_DATA", REG_MMIO, 0x0313, &mmDMIF_TEST_DEBUG_DATA[0], sizeof(mmDMIF_TEST_DEBUG_DATA)/sizeof(mmDMIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMCIF_CONTROL", REG_MMIO, 0x0314, &mmMCIF_CONTROL[0], sizeof(mmMCIF_CONTROL)/sizeof(mmMCIF_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WRITE_COMBINE_CONTROL", REG_MMIO, 0x0315, &mmMCIF_WRITE_COMBINE_CONTROL[0], sizeof(mmMCIF_WRITE_COMBINE_CONTROL)/sizeof(mmMCIF_WRITE_COMBINE_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_INDEX", REG_MMIO, 0x0316, &mmMCIF_TEST_DEBUG_INDEX[0], sizeof(mmMCIF_TEST_DEBUG_INDEX)/sizeof(mmMCIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_DATA", REG_MMIO, 0x0317, &mmMCIF_TEST_DEBUG_DATA[0], sizeof(mmMCIF_TEST_DEBUG_DATA)/sizeof(mmMCIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMCIF_VMID", REG_MMIO, 0x0318, &mmMCIF_VMID[0], sizeof(mmMCIF_VMID)/sizeof(mmMCIF_VMID[0]), 0, 0 },
+	{ "mmMCIF_MEM_CONTROL", REG_MMIO, 0x0319, &mmMCIF_MEM_CONTROL[0], sizeof(mmMCIF_MEM_CONTROL)/sizeof(mmMCIF_MEM_CONTROL[0]), 0, 0 },
+	{ "mmDC_RBBMIF_RDWR_CNTL1", REG_MMIO, 0x031A, &mmDC_RBBMIF_RDWR_CNTL1[0], sizeof(mmDC_RBBMIF_RDWR_CNTL1)/sizeof(mmDC_RBBMIF_RDWR_CNTL1[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATE", REG_MMIO, 0x031B, &mmDCI_MEM_PWR_STATE[0], sizeof(mmDCI_MEM_PWR_STATE)/sizeof(mmDCI_MEM_PWR_STATE[0]), 0, 0 },
+	{ "mmMC_DC_INTERFACE_NACK_STATUS", REG_MMIO, 0x031C, &mmMC_DC_INTERFACE_NACK_STATUS[0], sizeof(mmMC_DC_INTERFACE_NACK_STATUS)/sizeof(mmMC_DC_INTERFACE_NACK_STATUS[0]), 0, 0 },
+	{ "mmDC_RBBMIF_RDWR_CNTL2", REG_MMIO, 0x031D, &mmDC_RBBMIF_RDWR_CNTL2[0], sizeof(mmDC_RBBMIF_RDWR_CNTL2)/sizeof(mmDC_RBBMIF_RDWR_CNTL2[0]), 0, 0 },
+	{ "mmDCI_CLK_CNTL", REG_MMIO, 0x031E, &mmDCI_CLK_CNTL[0], sizeof(mmDCI_CLK_CNTL)/sizeof(mmDCI_CLK_CNTL[0]), 0, 0 },
+	{ "mmDCCG_VPCLK_CNTL", REG_MMIO, 0x031F, &mmDCCG_VPCLK_CNTL[0], sizeof(mmDCCG_VPCLK_CNTL)/sizeof(mmDCCG_VPCLK_CNTL[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_INDEX", REG_MMIO, 0x0320, &mmDCI_TEST_DEBUG_INDEX[0], sizeof(mmDCI_TEST_DEBUG_INDEX)/sizeof(mmDCI_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_DATA", REG_MMIO, 0x0321, &mmDCI_TEST_DEBUG_DATA[0], sizeof(mmDCI_TEST_DEBUG_DATA)/sizeof(mmDCI_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATE2", REG_MMIO, 0x0322, &mmDCI_MEM_PWR_STATE2[0], sizeof(mmDCI_MEM_PWR_STATE2)/sizeof(mmDCI_MEM_PWR_STATE2[0]), 0, 0 },
+	{ "mmDCI_DEBUG_CONFIG", REG_MMIO, 0x0323, &mmDCI_DEBUG_CONFIG[0], sizeof(mmDCI_DEBUG_CONFIG)/sizeof(mmDCI_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmDCI_CLK_RAMP_CNTL", REG_MMIO, 0x0324, NULL, 0, 0, 0 },
+	{ "mmLOW_POWER_TILING_CONTROL", REG_MMIO, 0x0325, &mmLOW_POWER_TILING_CONTROL[0], sizeof(mmLOW_POWER_TILING_CONTROL)/sizeof(mmLOW_POWER_TILING_CONTROL[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL", REG_MMIO, 0x0326, &mmDCI_MEM_PWR_CNTL[0], sizeof(mmDCI_MEM_PWR_CNTL)/sizeof(mmDCI_MEM_PWR_CNTL[0]), 0, 0 },
+	{ "mmDC_XDMA_INTERFACE_CNTL", REG_MMIO, 0x0327, &mmDC_XDMA_INTERFACE_CNTL[0], sizeof(mmDC_XDMA_INTERFACE_CNTL)/sizeof(mmDC_XDMA_INTERFACE_CNTL[0]), 0, 0 },
+	{ "mmPIPE0_DMIF_BUFFER_CONTROL", REG_MMIO, 0x0328, &mmPIPE0_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE0_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE0_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE1_DMIF_BUFFER_CONTROL", REG_MMIO, 0x0330, &mmPIPE1_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE1_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE1_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE2_DMIF_BUFFER_CONTROL", REG_MMIO, 0x0338, &mmPIPE2_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE2_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE2_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE3_DMIF_BUFFER_CONTROL", REG_MMIO, 0x0340, &mmPIPE3_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE3_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE3_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE4_DMIF_BUFFER_CONTROL", REG_MMIO, 0x0348, &mmPIPE4_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE4_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE4_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE5_DMIF_BUFFER_CONTROL", REG_MMIO, 0x0350, &mmPIPE5_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE5_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE5_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CNTL", REG_MMIO, 0x03E0, &mmXDMA_MSTR_CNTL[0], sizeof(mmXDMA_MSTR_CNTL)/sizeof(mmXDMA_MSTR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_READ_COMMAND", REG_MMIO, 0x03E1, &mmXDMA_MSTR_READ_COMMAND[0], sizeof(mmXDMA_MSTR_READ_COMMAND)/sizeof(mmXDMA_MSTR_READ_COMMAND[0]), 0, 0 },
+	{ "mmXDMA_MSTR_HEIGHT", REG_MMIO, 0x03E3, &mmXDMA_MSTR_HEIGHT[0], sizeof(mmXDMA_MSTR_HEIGHT)/sizeof(mmXDMA_MSTR_HEIGHT[0]), 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x03E4, &mmXDMA_MSTR_REMOTE_SURFACE_BASE[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE[0]), 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x03E5, &mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x03E6, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x03E7, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_STATUS", REG_MMIO, 0x03E8, &mmXDMA_MSTR_STATUS[0], sizeof(mmXDMA_MSTR_STATUS)/sizeof(mmXDMA_MSTR_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MC_PCIE_CLIENT_CONFIG", REG_MMIO, 0x03E9, &mmXDMA_MC_PCIE_CLIENT_CONFIG[0], sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG)/sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_CLIENT_CONFIG", REG_MMIO, 0x03EA, &mmXDMA_MSTR_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", REG_MMIO, 0x03F1, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", REG_MMIO, 0x03F2, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_PITCH", REG_MMIO, 0x03F3, &mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING1", REG_MMIO, 0x03F4, &mmXDMA_LOCAL_SURFACE_TILING1[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING1)/sizeof(mmXDMA_LOCAL_SURFACE_TILING1[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING2", REG_MMIO, 0x03F5, &mmXDMA_LOCAL_SURFACE_TILING2[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING2)/sizeof(mmXDMA_LOCAL_SURFACE_TILING2[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CMD_URGENT_CNTL", REG_MMIO, 0x03F6, &mmXDMA_MSTR_CMD_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL)/sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_URGENT_CNTL", REG_MMIO, 0x03F7, &mmXDMA_MSTR_MEM_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL)/sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_CNTL", REG_MMIO, 0x03FB, &mmXDMA_SLV_CNTL[0], sizeof(mmXDMA_SLV_CNTL)/sizeof(mmXDMA_SLV_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_CLIENT_CONFIG", REG_MMIO, 0x03FD, &mmXDMA_SLV_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_SLV_SLS_PITCH", REG_MMIO, 0x03FE, &mmXDMA_SLV_SLS_PITCH[0], sizeof(mmXDMA_SLV_SLS_PITCH)/sizeof(mmXDMA_SLV_SLS_PITCH[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_URGENT_CNTL", REG_MMIO, 0x03FF, &mmXDMA_SLV_READ_URGENT_CNTL[0], sizeof(mmXDMA_SLV_READ_URGENT_CNTL)/sizeof(mmXDMA_SLV_READ_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_WRITE_URGENT_CNTL", REG_MMIO, 0x0400, &mmXDMA_SLV_WRITE_URGENT_CNTL[0], sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL)/sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_WB_RATE_CNTL", REG_MMIO, 0x0401, &mmXDMA_SLV_WB_RATE_CNTL[0], sizeof(mmXDMA_SLV_WB_RATE_CNTL)/sizeof(mmXDMA_SLV_WB_RATE_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x0402, &mmXDMA_SLV_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x0403, &mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_MINMAX", REG_MMIO, 0x0404, &mmXDMA_SLV_READ_LATENCY_MINMAX[0], sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX)/sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_AVE", REG_MMIO, 0x0405, &mmXDMA_SLV_READ_LATENCY_AVE[0], sizeof(mmXDMA_SLV_READ_LATENCY_AVE)/sizeof(mmXDMA_SLV_READ_LATENCY_AVE[0]), 0, 0 },
+	{ "mmXDMA_INTERRUPT", REG_MMIO, 0x0406, &mmXDMA_INTERRUPT[0], sizeof(mmXDMA_INTERRUPT)/sizeof(mmXDMA_INTERRUPT[0]), 0, 0 },
+	{ "mmXDMA_SLV_FLIP_PENDING", REG_MMIO, 0x0407, &mmXDMA_SLV_FLIP_PENDING[0], sizeof(mmXDMA_SLV_FLIP_PENDING)/sizeof(mmXDMA_SLV_FLIP_PENDING[0]), 0, 0 },
+	{ "mmXDMA_CLOCK_GATING_CNTL", REG_MMIO, 0x0409, &mmXDMA_CLOCK_GATING_CNTL[0], sizeof(mmXDMA_CLOCK_GATING_CNTL)/sizeof(mmXDMA_CLOCK_GATING_CNTL[0]), 0, 0 },
+	{ "mmXDMA_RBBMIF_RDWR_CNTL", REG_MMIO, 0x040A, &mmXDMA_RBBMIF_RDWR_CNTL[0], sizeof(mmXDMA_RBBMIF_RDWR_CNTL)/sizeof(mmXDMA_RBBMIF_RDWR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MEM_POWER_CNTL", REG_MMIO, 0x040B, &mmXDMA_MEM_POWER_CNTL[0], sizeof(mmXDMA_MEM_POWER_CNTL)/sizeof(mmXDMA_MEM_POWER_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PCIE_NACK_STATUS", REG_MMIO, 0x040C, &mmXDMA_MSTR_PCIE_NACK_STATUS[0], sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS)/sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_NACK_STATUS", REG_MMIO, 0x040D, &mmXDMA_MSTR_MEM_NACK_STATUS[0], sizeof(mmXDMA_MSTR_MEM_NACK_STATUS)/sizeof(mmXDMA_MSTR_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_PCIE_NACK_STATUS", REG_MMIO, 0x040E, &mmXDMA_SLV_PCIE_NACK_STATUS[0], sizeof(mmXDMA_SLV_PCIE_NACK_STATUS)/sizeof(mmXDMA_SLV_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_NACK_STATUS", REG_MMIO, 0x040F, &mmXDMA_SLV_MEM_NACK_STATUS[0], sizeof(mmXDMA_SLV_MEM_NACK_STATUS)/sizeof(mmXDMA_SLV_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_TIMER", REG_MMIO, 0x0412, &mmXDMA_SLV_READ_LATENCY_TIMER[0], sizeof(mmXDMA_SLV_READ_LATENCY_TIMER)/sizeof(mmXDMA_SLV_READ_LATENCY_TIMER[0]), 0, 0 },
+	{ "mmXDMA_IF_BIF_STATUS", REG_MMIO, 0x0418, &mmXDMA_IF_BIF_STATUS[0], sizeof(mmXDMA_IF_BIF_STATUS)/sizeof(mmXDMA_IF_BIF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_INDEX", REG_MMIO, 0x041C, &mmXDMA_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_TEST_DEBUG_INDEX)/sizeof(mmXDMA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_DATA", REG_MMIO, 0x041D, &mmXDMA_TEST_DEBUG_DATA[0], sizeof(mmXDMA_TEST_DEBUG_DATA)/sizeof(mmXDMA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_SMC, 0x0F00, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID", REG_SMC, 0x0F02, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0x0F04, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "mmDMCU_CTRL", REG_MMIO, 0x1600, &mmDMCU_CTRL[0], sizeof(mmDMCU_CTRL)/sizeof(mmDMCU_CTRL[0]), 0, 0 },
+	{ "mmDMCU_STATUS", REG_MMIO, 0x1601, &mmDMCU_STATUS[0], sizeof(mmDMCU_STATUS)/sizeof(mmDMCU_STATUS[0]), 0, 0 },
+	{ "mmDMCU_PC_START_ADDR", REG_MMIO, 0x1602, &mmDMCU_PC_START_ADDR[0], sizeof(mmDMCU_PC_START_ADDR)/sizeof(mmDMCU_PC_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_START_ADDR", REG_MMIO, 0x1603, &mmDMCU_FW_START_ADDR[0], sizeof(mmDMCU_FW_START_ADDR)/sizeof(mmDMCU_FW_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_END_ADDR", REG_MMIO, 0x1604, &mmDMCU_FW_END_ADDR[0], sizeof(mmDMCU_FW_END_ADDR)/sizeof(mmDMCU_FW_END_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_ISR_START_ADDR", REG_MMIO, 0x1605, &mmDMCU_FW_ISR_START_ADDR[0], sizeof(mmDMCU_FW_ISR_START_ADDR)/sizeof(mmDMCU_FW_ISR_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_HI", REG_MMIO, 0x1606, &mmDMCU_FW_CS_HI[0], sizeof(mmDMCU_FW_CS_HI)/sizeof(mmDMCU_FW_CS_HI[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_LO", REG_MMIO, 0x1607, &mmDMCU_FW_CS_LO[0], sizeof(mmDMCU_FW_CS_LO)/sizeof(mmDMCU_FW_CS_LO[0]), 0, 0 },
+	{ "mmDMCU_RAM_ACCESS_CTRL", REG_MMIO, 0x1608, &mmDMCU_RAM_ACCESS_CTRL[0], sizeof(mmDMCU_RAM_ACCESS_CTRL)/sizeof(mmDMCU_RAM_ACCESS_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_CTRL", REG_MMIO, 0x1609, &mmDMCU_ERAM_WR_CTRL[0], sizeof(mmDMCU_ERAM_WR_CTRL)/sizeof(mmDMCU_ERAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_DATA", REG_MMIO, 0x160A, &mmDMCU_ERAM_WR_DATA[0], sizeof(mmDMCU_ERAM_WR_DATA)/sizeof(mmDMCU_ERAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_CTRL", REG_MMIO, 0x160B, &mmDMCU_ERAM_RD_CTRL[0], sizeof(mmDMCU_ERAM_RD_CTRL)/sizeof(mmDMCU_ERAM_RD_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_DATA", REG_MMIO, 0x160C, &mmDMCU_ERAM_RD_DATA[0], sizeof(mmDMCU_ERAM_RD_DATA)/sizeof(mmDMCU_ERAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_CTRL", REG_MMIO, 0x160D, &mmDMCU_IRAM_WR_CTRL[0], sizeof(mmDMCU_IRAM_WR_CTRL)/sizeof(mmDMCU_IRAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_DATA", REG_MMIO, 0x160E, &mmDMCU_IRAM_WR_DATA[0], sizeof(mmDMCU_IRAM_WR_DATA)/sizeof(mmDMCU_IRAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_CTRL", REG_MMIO, 0x160F, &mmDMCU_IRAM_RD_CTRL[0], sizeof(mmDMCU_IRAM_RD_CTRL)/sizeof(mmDMCU_IRAM_RD_CTRL[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_DATA", REG_MMIO, 0x1610, &mmDMCU_IRAM_RD_DATA[0], sizeof(mmDMCU_IRAM_RD_DATA)/sizeof(mmDMCU_IRAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_EVENT_TRIGGER", REG_MMIO, 0x1611, &mmDMCU_EVENT_TRIGGER[0], sizeof(mmDMCU_EVENT_TRIGGER)/sizeof(mmDMCU_EVENT_TRIGGER[0]), 0, 0 },
+	{ "mmDMCU_UC_INTERNAL_INT_STATUS", REG_MMIO, 0x1612, &mmDMCU_UC_INTERNAL_INT_STATUS[0], sizeof(mmDMCU_UC_INTERNAL_INT_STATUS)/sizeof(mmDMCU_UC_INTERNAL_INT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_STATUS", REG_MMIO, 0x1614, &mmDMCU_INTERRUPT_STATUS[0], sizeof(mmDMCU_INTERRUPT_STATUS)/sizeof(mmDMCU_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_HOST_EN_MASK", REG_MMIO, 0x1615, &mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_EN_MASK", REG_MMIO, 0x1616, &mmDMCU_INTERRUPT_TO_UC_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL", REG_MMIO, 0x1617, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0]), 0, 0 },
+	{ "mmDC_DMCU_SCRATCH", REG_MMIO, 0x1618, &mmDC_DMCU_SCRATCH[0], sizeof(mmDC_DMCU_SCRATCH)/sizeof(mmDC_DMCU_SCRATCH[0]), 0, 0 },
+	{ "mmDMCU_INT_CNT", REG_MMIO, 0x1619, &mmDMCU_INT_CNT[0], sizeof(mmDMCU_INT_CNT)/sizeof(mmDMCU_INT_CNT[0]), 0, 0 },
+	{ "mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS", REG_MMIO, 0x161A, &mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0], sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS)/sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0]), 0, 0 },
+	{ "mmDMCU_UC_CLK_GATING_CNTL", REG_MMIO, 0x161B, &mmDMCU_UC_CLK_GATING_CNTL[0], sizeof(mmDMCU_UC_CLK_GATING_CNTL)/sizeof(mmDMCU_UC_CLK_GATING_CNTL[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG1", REG_MMIO, 0x161C, &mmMASTER_COMM_DATA_REG1[0], sizeof(mmMASTER_COMM_DATA_REG1)/sizeof(mmMASTER_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG2", REG_MMIO, 0x161D, &mmMASTER_COMM_DATA_REG2[0], sizeof(mmMASTER_COMM_DATA_REG2)/sizeof(mmMASTER_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG3", REG_MMIO, 0x161E, &mmMASTER_COMM_DATA_REG3[0], sizeof(mmMASTER_COMM_DATA_REG3)/sizeof(mmMASTER_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmMASTER_COMM_CMD_REG", REG_MMIO, 0x161F, &mmMASTER_COMM_CMD_REG[0], sizeof(mmMASTER_COMM_CMD_REG)/sizeof(mmMASTER_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmMASTER_COMM_CNTL_REG", REG_MMIO, 0x1620, &mmMASTER_COMM_CNTL_REG[0], sizeof(mmMASTER_COMM_CNTL_REG)/sizeof(mmMASTER_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG1", REG_MMIO, 0x1621, &mmSLAVE_COMM_DATA_REG1[0], sizeof(mmSLAVE_COMM_DATA_REG1)/sizeof(mmSLAVE_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG2", REG_MMIO, 0x1622, &mmSLAVE_COMM_DATA_REG2[0], sizeof(mmSLAVE_COMM_DATA_REG2)/sizeof(mmSLAVE_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG3", REG_MMIO, 0x1623, &mmSLAVE_COMM_DATA_REG3[0], sizeof(mmSLAVE_COMM_DATA_REG3)/sizeof(mmSLAVE_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CMD_REG", REG_MMIO, 0x1624, &mmSLAVE_COMM_CMD_REG[0], sizeof(mmSLAVE_COMM_CMD_REG)/sizeof(mmSLAVE_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CNTL_REG", REG_MMIO, 0x1625, &mmSLAVE_COMM_CNTL_REG[0], sizeof(mmSLAVE_COMM_CNTL_REG)/sizeof(mmSLAVE_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_INDEX", REG_MMIO, 0x1626, &mmDMCU_TEST_DEBUG_INDEX[0], sizeof(mmDMCU_TEST_DEBUG_INDEX)/sizeof(mmDMCU_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_DATA", REG_MMIO, 0x1627, &mmDMCU_TEST_DEBUG_DATA[0], sizeof(mmDMCU_TEST_DEBUG_DATA)/sizeof(mmDMCU_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBL1_PWM_AMBIENT_LIGHT_LEVEL", REG_MMIO, 0x1628, &mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0], sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL)/sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_USER_LEVEL", REG_MMIO, 0x1629, &mmBL1_PWM_USER_LEVEL[0], sizeof(mmBL1_PWM_USER_LEVEL)/sizeof(mmBL1_PWM_USER_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_TARGET_ABM_LEVEL", REG_MMIO, 0x162A, &mmBL1_PWM_TARGET_ABM_LEVEL[0], sizeof(mmBL1_PWM_TARGET_ABM_LEVEL)/sizeof(mmBL1_PWM_TARGET_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_CURRENT_ABM_LEVEL", REG_MMIO, 0x162B, &mmBL1_PWM_CURRENT_ABM_LEVEL[0], sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL)/sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_FINAL_DUTY_CYCLE", REG_MMIO, 0x162C, &mmBL1_PWM_FINAL_DUTY_CYCLE[0], sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE)/sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_MINIMUM_DUTY_CYCLE", REG_MMIO, 0x162D, &mmBL1_PWM_MINIMUM_DUTY_CYCLE[0], sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE)/sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_ABM_CNTL", REG_MMIO, 0x162E, &mmBL1_PWM_ABM_CNTL[0], sizeof(mmBL1_PWM_ABM_CNTL)/sizeof(mmBL1_PWM_ABM_CNTL[0]), 0, 0 },
+	{ "mmBL1_PWM_BL_UPDATE_SAMPLE_RATE", REG_MMIO, 0x162F, &mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0], sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE)/sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmBL1_PWM_GRP2_REG_LOCK", REG_MMIO, 0x1630, &mmBL1_PWM_GRP2_REG_LOCK[0], sizeof(mmBL1_PWM_GRP2_REG_LOCK)/sizeof(mmBL1_PWM_GRP2_REG_LOCK[0]), 0, 0 },
+	{ "mmDC_ABM1_CNTL", REG_MMIO, 0x1638, &mmDC_ABM1_CNTL[0], sizeof(mmDC_ABM1_CNTL)/sizeof(mmDC_ABM1_CNTL[0]), 0, 0 },
+	{ "mmDC_ABM1_IPCSC_COEFF_SEL", REG_MMIO, 0x1639, &mmDC_ABM1_IPCSC_COEFF_SEL[0], sizeof(mmDC_ABM1_IPCSC_COEFF_SEL)/sizeof(mmDC_ABM1_IPCSC_COEFF_SEL[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_0", REG_MMIO, 0x163A, &mmDC_ABM1_ACE_OFFSET_SLOPE_0[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_1", REG_MMIO, 0x163B, &mmDC_ABM1_ACE_OFFSET_SLOPE_1[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_2", REG_MMIO, 0x163C, &mmDC_ABM1_ACE_OFFSET_SLOPE_2[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_3", REG_MMIO, 0x163D, &mmDC_ABM1_ACE_OFFSET_SLOPE_3[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_4", REG_MMIO, 0x163E, &mmDC_ABM1_ACE_OFFSET_SLOPE_4[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_12", REG_MMIO, 0x163F, &mmDC_ABM1_ACE_THRES_12[0], sizeof(mmDC_ABM1_ACE_THRES_12)/sizeof(mmDC_ABM1_ACE_THRES_12[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_34", REG_MMIO, 0x1640, &mmDC_ABM1_ACE_THRES_34[0], sizeof(mmDC_ABM1_ACE_THRES_34)/sizeof(mmDC_ABM1_ACE_THRES_34[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_CNTL_MISC", REG_MMIO, 0x1641, &mmDC_ABM1_ACE_CNTL_MISC[0], sizeof(mmDC_ABM1_ACE_CNTL_MISC)/sizeof(mmDC_ABM1_ACE_CNTL_MISC[0]), 0, 0 },
+	{ "mmDC_ABM1_DEBUG_MISC", REG_MMIO, 0x1649, &mmDC_ABM1_DEBUG_MISC[0], sizeof(mmDC_ABM1_DEBUG_MISC)/sizeof(mmDC_ABM1_DEBUG_MISC[0]), 0, 0 },
+	{ "mmDC_ABM1_HGLS_REG_READ_PROGRESS", REG_MMIO, 0x164A, &mmDC_ABM1_HGLS_REG_READ_PROGRESS[0], sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS)/sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_MISC_CTRL", REG_MMIO, 0x164B, &mmDC_ABM1_HG_MISC_CTRL[0], sizeof(mmDC_ABM1_HG_MISC_CTRL)/sizeof(mmDC_ABM1_HG_MISC_CTRL[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SUM_OF_LUMA", REG_MMIO, 0x164C, &mmDC_ABM1_LS_SUM_OF_LUMA[0], sizeof(mmDC_ABM1_LS_SUM_OF_LUMA)/sizeof(mmDC_ABM1_LS_SUM_OF_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_LUMA", REG_MMIO, 0x164D, &mmDC_ABM1_LS_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA", REG_MMIO, 0x164E, &mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_PIXEL_COUNT", REG_MMIO, 0x164F, &mmDC_ABM1_LS_PIXEL_COUNT[0], sizeof(mmDC_ABM1_LS_PIXEL_COUNT)/sizeof(mmDC_ABM1_LS_PIXEL_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_OVR_SCAN_BIN", REG_MMIO, 0x1650, &mmDC_ABM1_LS_OVR_SCAN_BIN[0], sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN)/sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES", REG_MMIO, 0x1651, &mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0], sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES)/sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT", REG_MMIO, 0x1652, &mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT", REG_MMIO, 0x1653, &mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_SAMPLE_RATE", REG_MMIO, 0x1654, &mmDC_ABM1_HG_SAMPLE_RATE[0], sizeof(mmDC_ABM1_HG_SAMPLE_RATE)/sizeof(mmDC_ABM1_HG_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SAMPLE_RATE", REG_MMIO, 0x1655, &mmDC_ABM1_LS_SAMPLE_RATE[0], sizeof(mmDC_ABM1_LS_SAMPLE_RATE)/sizeof(mmDC_ABM1_LS_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG", REG_MMIO, 0x1656, &mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0], sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG)/sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX", REG_MMIO, 0x1657, &mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX", REG_MMIO, 0x1658, &mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX", REG_MMIO, 0x1659, &mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX", REG_MMIO, 0x165A, &mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_1", REG_MMIO, 0x165B, &mmDC_ABM1_HG_RESULT_1[0], sizeof(mmDC_ABM1_HG_RESULT_1)/sizeof(mmDC_ABM1_HG_RESULT_1[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_2", REG_MMIO, 0x165C, &mmDC_ABM1_HG_RESULT_2[0], sizeof(mmDC_ABM1_HG_RESULT_2)/sizeof(mmDC_ABM1_HG_RESULT_2[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_3", REG_MMIO, 0x165D, &mmDC_ABM1_HG_RESULT_3[0], sizeof(mmDC_ABM1_HG_RESULT_3)/sizeof(mmDC_ABM1_HG_RESULT_3[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_4", REG_MMIO, 0x165E, &mmDC_ABM1_HG_RESULT_4[0], sizeof(mmDC_ABM1_HG_RESULT_4)/sizeof(mmDC_ABM1_HG_RESULT_4[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_5", REG_MMIO, 0x165F, &mmDC_ABM1_HG_RESULT_5[0], sizeof(mmDC_ABM1_HG_RESULT_5)/sizeof(mmDC_ABM1_HG_RESULT_5[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_6", REG_MMIO, 0x1660, &mmDC_ABM1_HG_RESULT_6[0], sizeof(mmDC_ABM1_HG_RESULT_6)/sizeof(mmDC_ABM1_HG_RESULT_6[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_7", REG_MMIO, 0x1661, &mmDC_ABM1_HG_RESULT_7[0], sizeof(mmDC_ABM1_HG_RESULT_7)/sizeof(mmDC_ABM1_HG_RESULT_7[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_8", REG_MMIO, 0x1662, &mmDC_ABM1_HG_RESULT_8[0], sizeof(mmDC_ABM1_HG_RESULT_8)/sizeof(mmDC_ABM1_HG_RESULT_8[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_9", REG_MMIO, 0x1663, &mmDC_ABM1_HG_RESULT_9[0], sizeof(mmDC_ABM1_HG_RESULT_9)/sizeof(mmDC_ABM1_HG_RESULT_9[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_10", REG_MMIO, 0x1664, &mmDC_ABM1_HG_RESULT_10[0], sizeof(mmDC_ABM1_HG_RESULT_10)/sizeof(mmDC_ABM1_HG_RESULT_10[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_11", REG_MMIO, 0x1665, &mmDC_ABM1_HG_RESULT_11[0], sizeof(mmDC_ABM1_HG_RESULT_11)/sizeof(mmDC_ABM1_HG_RESULT_11[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_12", REG_MMIO, 0x1666, &mmDC_ABM1_HG_RESULT_12[0], sizeof(mmDC_ABM1_HG_RESULT_12)/sizeof(mmDC_ABM1_HG_RESULT_12[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_13", REG_MMIO, 0x1667, &mmDC_ABM1_HG_RESULT_13[0], sizeof(mmDC_ABM1_HG_RESULT_13)/sizeof(mmDC_ABM1_HG_RESULT_13[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_14", REG_MMIO, 0x1668, &mmDC_ABM1_HG_RESULT_14[0], sizeof(mmDC_ABM1_HG_RESULT_14)/sizeof(mmDC_ABM1_HG_RESULT_14[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_15", REG_MMIO, 0x1669, &mmDC_ABM1_HG_RESULT_15[0], sizeof(mmDC_ABM1_HG_RESULT_15)/sizeof(mmDC_ABM1_HG_RESULT_15[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_16", REG_MMIO, 0x166A, &mmDC_ABM1_HG_RESULT_16[0], sizeof(mmDC_ABM1_HG_RESULT_16)/sizeof(mmDC_ABM1_HG_RESULT_16[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_17", REG_MMIO, 0x166B, &mmDC_ABM1_HG_RESULT_17[0], sizeof(mmDC_ABM1_HG_RESULT_17)/sizeof(mmDC_ABM1_HG_RESULT_17[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_18", REG_MMIO, 0x166C, &mmDC_ABM1_HG_RESULT_18[0], sizeof(mmDC_ABM1_HG_RESULT_18)/sizeof(mmDC_ABM1_HG_RESULT_18[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_19", REG_MMIO, 0x166D, &mmDC_ABM1_HG_RESULT_19[0], sizeof(mmDC_ABM1_HG_RESULT_19)/sizeof(mmDC_ABM1_HG_RESULT_19[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_20", REG_MMIO, 0x166E, &mmDC_ABM1_HG_RESULT_20[0], sizeof(mmDC_ABM1_HG_RESULT_20)/sizeof(mmDC_ABM1_HG_RESULT_20[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_21", REG_MMIO, 0x166F, &mmDC_ABM1_HG_RESULT_21[0], sizeof(mmDC_ABM1_HG_RESULT_21)/sizeof(mmDC_ABM1_HG_RESULT_21[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_22", REG_MMIO, 0x1670, &mmDC_ABM1_HG_RESULT_22[0], sizeof(mmDC_ABM1_HG_RESULT_22)/sizeof(mmDC_ABM1_HG_RESULT_22[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_23", REG_MMIO, 0x1671, &mmDC_ABM1_HG_RESULT_23[0], sizeof(mmDC_ABM1_HG_RESULT_23)/sizeof(mmDC_ABM1_HG_RESULT_23[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_24", REG_MMIO, 0x1672, &mmDC_ABM1_HG_RESULT_24[0], sizeof(mmDC_ABM1_HG_RESULT_24)/sizeof(mmDC_ABM1_HG_RESULT_24[0]), 0, 0 },
+	{ "mmMVP_CONTROL1", REG_MMIO, 0x1680, &mmMVP_CONTROL1[0], sizeof(mmMVP_CONTROL1)/sizeof(mmMVP_CONTROL1[0]), 0, 0 },
+	{ "mmMVP_CONTROL2", REG_MMIO, 0x1681, &mmMVP_CONTROL2[0], sizeof(mmMVP_CONTROL2)/sizeof(mmMVP_CONTROL2[0]), 0, 0 },
+	{ "mmMVP_FIFO_CONTROL", REG_MMIO, 0x1682, &mmMVP_FIFO_CONTROL[0], sizeof(mmMVP_FIFO_CONTROL)/sizeof(mmMVP_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmMVP_FIFO_STATUS", REG_MMIO, 0x1683, &mmMVP_FIFO_STATUS[0], sizeof(mmMVP_FIFO_STATUS)/sizeof(mmMVP_FIFO_STATUS[0]), 0, 0 },
+	{ "mmMVP_SLAVE_STATUS", REG_MMIO, 0x1684, &mmMVP_SLAVE_STATUS[0], sizeof(mmMVP_SLAVE_STATUS)/sizeof(mmMVP_SLAVE_STATUS[0]), 0, 0 },
+	{ "mmMVP_INBAND_CNTL_CAP", REG_MMIO, 0x1685, &mmMVP_INBAND_CNTL_CAP[0], sizeof(mmMVP_INBAND_CNTL_CAP)/sizeof(mmMVP_INBAND_CNTL_CAP[0]), 0, 0 },
+	{ "mmMVP_BLACK_KEYER", REG_MMIO, 0x1686, &mmMVP_BLACK_KEYER[0], sizeof(mmMVP_BLACK_KEYER)/sizeof(mmMVP_BLACK_KEYER[0]), 0, 0 },
+	{ "mmMVP_CRC_CNTL", REG_MMIO, 0x1687, &mmMVP_CRC_CNTL[0], sizeof(mmMVP_CRC_CNTL)/sizeof(mmMVP_CRC_CNTL[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_BLUE_GREEN", REG_MMIO, 0x1688, &mmMVP_CRC_RESULT_BLUE_GREEN[0], sizeof(mmMVP_CRC_RESULT_BLUE_GREEN)/sizeof(mmMVP_CRC_RESULT_BLUE_GREEN[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_RED", REG_MMIO, 0x1689, &mmMVP_CRC_RESULT_RED[0], sizeof(mmMVP_CRC_RESULT_RED)/sizeof(mmMVP_CRC_RESULT_RED[0]), 0, 0 },
+	{ "mmMVP_CONTROL3", REG_MMIO, 0x168A, &mmMVP_CONTROL3[0], sizeof(mmMVP_CONTROL3)/sizeof(mmMVP_CONTROL3[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL1", REG_MMIO, 0x168B, &mmMVP_RECEIVE_CNT_CNTL1[0], sizeof(mmMVP_RECEIVE_CNT_CNTL1)/sizeof(mmMVP_RECEIVE_CNT_CNTL1[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL2", REG_MMIO, 0x168C, &mmMVP_RECEIVE_CNT_CNTL2[0], sizeof(mmMVP_RECEIVE_CNT_CNTL2)/sizeof(mmMVP_RECEIVE_CNT_CNTL2[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_INDEX", REG_MMIO, 0x168D, &mmMVP_TEST_DEBUG_INDEX[0], sizeof(mmMVP_TEST_DEBUG_INDEX)/sizeof(mmMVP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_DATA", REG_MMIO, 0x168E, &mmMVP_TEST_DEBUG_DATA[0], sizeof(mmMVP_TEST_DEBUG_DATA)/sizeof(mmMVP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMVP_DEBUG", REG_MMIO, 0x168F, &mmMVP_DEBUG[0], sizeof(mmMVP_DEBUG)/sizeof(mmMVP_DEBUG[0]), 0, 0 },
+	{ "mmDC_ABM1_OVERSCAN_PIXEL_VALUE", REG_MMIO, 0x169B, &mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0], sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE)/sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0]), 0, 0 },
+	{ "mmDC_ABM1_BL_MASTER_LOCK", REG_MMIO, 0x169C, &mmDC_ABM1_BL_MASTER_LOCK[0], sizeof(mmDC_ABM1_BL_MASTER_LOCK)/sizeof(mmDC_ABM1_BL_MASTER_LOCK[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_INDEX", REG_MMIO, 0x169E, &mmABM_TEST_DEBUG_INDEX[0], sizeof(mmABM_TEST_DEBUG_INDEX)/sizeof(mmABM_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_DATA", REG_MMIO, 0x169F, &mmABM_TEST_DEBUG_DATA[0], sizeof(mmABM_TEST_DEBUG_DATA)/sizeof(mmABM_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmFBC_CNTL", REG_MMIO, 0x16D0, &mmFBC_CNTL[0], sizeof(mmFBC_CNTL)/sizeof(mmFBC_CNTL[0]), 0, 0 },
+	{ "mmFBC_IDLE_MASK", REG_MMIO, 0x16D1, &mmFBC_IDLE_MASK[0], sizeof(mmFBC_IDLE_MASK)/sizeof(mmFBC_IDLE_MASK[0]), 0, 0 },
+	{ "mmFBC_IDLE_FORCE_CLEAR_MASK", REG_MMIO, 0x16D2, &mmFBC_IDLE_FORCE_CLEAR_MASK[0], sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK)/sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK[0]), 0, 0 },
+	{ "mmFBC_START_STOP_DELAY", REG_MMIO, 0x16D3, &mmFBC_START_STOP_DELAY[0], sizeof(mmFBC_START_STOP_DELAY)/sizeof(mmFBC_START_STOP_DELAY[0]), 0, 0 },
+	{ "mmFBC_COMP_CNTL", REG_MMIO, 0x16D4, &mmFBC_COMP_CNTL[0], sizeof(mmFBC_COMP_CNTL)/sizeof(mmFBC_COMP_CNTL[0]), 0, 0 },
+	{ "mmFBC_COMP_MODE", REG_MMIO, 0x16D5, &mmFBC_COMP_MODE[0], sizeof(mmFBC_COMP_MODE)/sizeof(mmFBC_COMP_MODE[0]), 0, 0 },
+	{ "mmFBC_DEBUG0", REG_MMIO, 0x16D6, &mmFBC_DEBUG0[0], sizeof(mmFBC_DEBUG0)/sizeof(mmFBC_DEBUG0[0]), 0, 0 },
+	{ "mmFBC_DEBUG1", REG_MMIO, 0x16D7, &mmFBC_DEBUG1[0], sizeof(mmFBC_DEBUG1)/sizeof(mmFBC_DEBUG1[0]), 0, 0 },
+	{ "mmFBC_DEBUG2", REG_MMIO, 0x16D8, &mmFBC_DEBUG2[0], sizeof(mmFBC_DEBUG2)/sizeof(mmFBC_DEBUG2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT0", REG_MMIO, 0x16D9, &mmFBC_IND_LUT0[0], sizeof(mmFBC_IND_LUT0)/sizeof(mmFBC_IND_LUT0[0]), 0, 0 },
+	{ "mmFBC_IND_LUT1", REG_MMIO, 0x16DA, &mmFBC_IND_LUT1[0], sizeof(mmFBC_IND_LUT1)/sizeof(mmFBC_IND_LUT1[0]), 0, 0 },
+	{ "mmFBC_IND_LUT2", REG_MMIO, 0x16DB, &mmFBC_IND_LUT2[0], sizeof(mmFBC_IND_LUT2)/sizeof(mmFBC_IND_LUT2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT3", REG_MMIO, 0x16DC, &mmFBC_IND_LUT3[0], sizeof(mmFBC_IND_LUT3)/sizeof(mmFBC_IND_LUT3[0]), 0, 0 },
+	{ "mmFBC_IND_LUT4", REG_MMIO, 0x16DD, &mmFBC_IND_LUT4[0], sizeof(mmFBC_IND_LUT4)/sizeof(mmFBC_IND_LUT4[0]), 0, 0 },
+	{ "mmFBC_IND_LUT5", REG_MMIO, 0x16DE, &mmFBC_IND_LUT5[0], sizeof(mmFBC_IND_LUT5)/sizeof(mmFBC_IND_LUT5[0]), 0, 0 },
+	{ "mmFBC_IND_LUT6", REG_MMIO, 0x16DF, &mmFBC_IND_LUT6[0], sizeof(mmFBC_IND_LUT6)/sizeof(mmFBC_IND_LUT6[0]), 0, 0 },
+	{ "mmFBC_IND_LUT7", REG_MMIO, 0x16E0, &mmFBC_IND_LUT7[0], sizeof(mmFBC_IND_LUT7)/sizeof(mmFBC_IND_LUT7[0]), 0, 0 },
+	{ "mmFBC_IND_LUT8", REG_MMIO, 0x16E1, &mmFBC_IND_LUT8[0], sizeof(mmFBC_IND_LUT8)/sizeof(mmFBC_IND_LUT8[0]), 0, 0 },
+	{ "mmFBC_IND_LUT9", REG_MMIO, 0x16E2, &mmFBC_IND_LUT9[0], sizeof(mmFBC_IND_LUT9)/sizeof(mmFBC_IND_LUT9[0]), 0, 0 },
+	{ "mmFBC_IND_LUT10", REG_MMIO, 0x16E3, &mmFBC_IND_LUT10[0], sizeof(mmFBC_IND_LUT10)/sizeof(mmFBC_IND_LUT10[0]), 0, 0 },
+	{ "mmFBC_IND_LUT11", REG_MMIO, 0x16E4, &mmFBC_IND_LUT11[0], sizeof(mmFBC_IND_LUT11)/sizeof(mmFBC_IND_LUT11[0]), 0, 0 },
+	{ "mmFBC_IND_LUT12", REG_MMIO, 0x16E5, &mmFBC_IND_LUT12[0], sizeof(mmFBC_IND_LUT12)/sizeof(mmFBC_IND_LUT12[0]), 0, 0 },
+	{ "mmFBC_IND_LUT13", REG_MMIO, 0x16E6, &mmFBC_IND_LUT13[0], sizeof(mmFBC_IND_LUT13)/sizeof(mmFBC_IND_LUT13[0]), 0, 0 },
+	{ "mmFBC_IND_LUT14", REG_MMIO, 0x16E7, &mmFBC_IND_LUT14[0], sizeof(mmFBC_IND_LUT14)/sizeof(mmFBC_IND_LUT14[0]), 0, 0 },
+	{ "mmFBC_IND_LUT15", REG_MMIO, 0x16E8, &mmFBC_IND_LUT15[0], sizeof(mmFBC_IND_LUT15)/sizeof(mmFBC_IND_LUT15[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_01", REG_MMIO, 0x16E9, &mmFBC_CSM_REGION_OFFSET_01[0], sizeof(mmFBC_CSM_REGION_OFFSET_01)/sizeof(mmFBC_CSM_REGION_OFFSET_01[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_23", REG_MMIO, 0x16EA, &mmFBC_CSM_REGION_OFFSET_23[0], sizeof(mmFBC_CSM_REGION_OFFSET_23)/sizeof(mmFBC_CSM_REGION_OFFSET_23[0]), 0, 0 },
+	{ "mmFBC_CLIENT_REGION_MASK", REG_MMIO, 0x16EB, &mmFBC_CLIENT_REGION_MASK[0], sizeof(mmFBC_CLIENT_REGION_MASK)/sizeof(mmFBC_CLIENT_REGION_MASK[0]), 0, 0 },
+	{ "mmFBC_DEBUG_COMP", REG_MMIO, 0x16EC, &mmFBC_DEBUG_COMP[0], sizeof(mmFBC_DEBUG_COMP)/sizeof(mmFBC_DEBUG_COMP[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR", REG_MMIO, 0x16ED, &mmFBC_DEBUG_CSR[0], sizeof(mmFBC_DEBUG_CSR)/sizeof(mmFBC_DEBUG_CSR[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA", REG_MMIO, 0x16EE, &mmFBC_DEBUG_CSR_RDATA[0], sizeof(mmFBC_DEBUG_CSR_RDATA)/sizeof(mmFBC_DEBUG_CSR_RDATA[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA", REG_MMIO, 0x16EF, &mmFBC_DEBUG_CSR_WDATA[0], sizeof(mmFBC_DEBUG_CSR_WDATA)/sizeof(mmFBC_DEBUG_CSR_WDATA[0]), 0, 0 },
+	{ "mmFBC_MISC", REG_MMIO, 0x16F0, &mmFBC_MISC[0], sizeof(mmFBC_MISC)/sizeof(mmFBC_MISC[0]), 0, 0 },
+	{ "mmFBC_STATUS", REG_MMIO, 0x16F1, &mmFBC_STATUS[0], sizeof(mmFBC_STATUS)/sizeof(mmFBC_STATUS[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_INDEX", REG_MMIO, 0x16F4, &mmFBC_TEST_DEBUG_INDEX[0], sizeof(mmFBC_TEST_DEBUG_INDEX)/sizeof(mmFBC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_DATA", REG_MMIO, 0x16F5, &mmFBC_TEST_DEBUG_DATA[0], sizeof(mmFBC_TEST_DEBUG_DATA)/sizeof(mmFBC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA_HI", REG_MMIO, 0x16F6, &mmFBC_DEBUG_CSR_RDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_RDATA_HI)/sizeof(mmFBC_DEBUG_CSR_RDATA_HI[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA_HI", REG_MMIO, 0x16F7, &mmFBC_DEBUG_CSR_WDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_WDATA_HI)/sizeof(mmFBC_DEBUG_CSR_WDATA_HI[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_REF_DIV", REG_MMIO, 0x1700, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_FB_DIV", REG_MMIO, 0x1701, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_POST_DIV", REG_MMIO, 0x1702, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1703, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_SS_CNTL", REG_MMIO, 0x1704, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_SMC, 0x1705, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_IDCLK_CNTL", REG_MMIO, 0x1706, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_CNTL", REG_MMIO, 0x1707, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_ANALOG", REG_MMIO, 0x1708, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_VREG_CNTL", REG_MMIO, 0x1709, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x170A, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_DEBUG_CNTL", REG_MMIO, 0x170B, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_UPDATE_LOCK", REG_MMIO, 0x170C, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_UPDATE_CNTL", REG_MMIO, 0x170D, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL", REG_MMIO, 0x170E, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE", REG_MMIO, 0x170F, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_REF_DIV", REG_MMIO, 0x1710, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_FB_DIV", REG_MMIO, 0x1711, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_POST_DIV", REG_MMIO, 0x1712, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1713, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_SS_CNTL", REG_MMIO, 0x1714, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_DS_CNTL", REG_MMIO, 0x1715, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_IDCLK_CNTL", REG_MMIO, 0x1716, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_CNTL", REG_MMIO, 0x1717, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_ANALOG", REG_MMIO, 0x1718, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_VREG_CNTL", REG_MMIO, 0x1719, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x171A, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_DEBUG_CNTL", REG_MMIO, 0x171B, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_UPDATE_LOCK", REG_MMIO, 0x171C, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_UPDATE_CNTL", REG_MMIO, 0x171D, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL", REG_MMIO, 0x171E, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE", REG_MMIO, 0x171F, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_SMC, 0x1720, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2", REG_SMC, 0x1721, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3", REG_SMC, 0x1722, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4", REG_SMC, 0x1723, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0]), 0, 0 },
+	{ "mmDCCG_PLL2_PLL_SS_CNTL", REG_MMIO, 0x1724, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_DS_CNTL", REG_MMIO, 0x1725, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_IDCLK_CNTL", REG_MMIO, 0x1726, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_CNTL", REG_MMIO, 0x1727, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_ANALOG", REG_MMIO, 0x1728, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_VREG_CNTL", REG_MMIO, 0x1729, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x172A, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_DEBUG_CNTL", REG_MMIO, 0x172B, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_UPDATE_LOCK", REG_MMIO, 0x172C, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_UPDATE_CNTL", REG_MMIO, 0x172D, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL", REG_MMIO, 0x172E, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE", REG_MMIO, 0x172F, NULL, 0, 0, 0 },
+	{ "mmPIPE0_PG_CONFIG", REG_MMIO, 0x1760, &mmPIPE0_PG_CONFIG[0], sizeof(mmPIPE0_PG_CONFIG)/sizeof(mmPIPE0_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE0_PG_ENABLE", REG_MMIO, 0x1761, &mmPIPE0_PG_ENABLE[0], sizeof(mmPIPE0_PG_ENABLE)/sizeof(mmPIPE0_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE0_PG_STATUS", REG_MMIO, 0x1762, &mmPIPE0_PG_STATUS[0], sizeof(mmPIPE0_PG_STATUS)/sizeof(mmPIPE0_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE1_PG_CONFIG", REG_MMIO, 0x1764, &mmPIPE1_PG_CONFIG[0], sizeof(mmPIPE1_PG_CONFIG)/sizeof(mmPIPE1_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE1_PG_ENABLE", REG_MMIO, 0x1765, &mmPIPE1_PG_ENABLE[0], sizeof(mmPIPE1_PG_ENABLE)/sizeof(mmPIPE1_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE1_PG_STATUS", REG_MMIO, 0x1766, &mmPIPE1_PG_STATUS[0], sizeof(mmPIPE1_PG_STATUS)/sizeof(mmPIPE1_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE2_PG_CONFIG", REG_MMIO, 0x1768, &mmPIPE2_PG_CONFIG[0], sizeof(mmPIPE2_PG_CONFIG)/sizeof(mmPIPE2_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE2_PG_ENABLE", REG_MMIO, 0x1769, &mmPIPE2_PG_ENABLE[0], sizeof(mmPIPE2_PG_ENABLE)/sizeof(mmPIPE2_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE2_PG_STATUS", REG_MMIO, 0x176A, &mmPIPE2_PG_STATUS[0], sizeof(mmPIPE2_PG_STATUS)/sizeof(mmPIPE2_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE3_PG_CONFIG", REG_MMIO, 0x176C, &mmPIPE3_PG_CONFIG[0], sizeof(mmPIPE3_PG_CONFIG)/sizeof(mmPIPE3_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE3_PG_ENABLE", REG_MMIO, 0x176D, &mmPIPE3_PG_ENABLE[0], sizeof(mmPIPE3_PG_ENABLE)/sizeof(mmPIPE3_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE3_PG_STATUS", REG_MMIO, 0x176E, &mmPIPE3_PG_STATUS[0], sizeof(mmPIPE3_PG_STATUS)/sizeof(mmPIPE3_PG_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_SMC, 0x1770, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmPIPE4_PG_ENABLE", REG_MMIO, 0x1771, &mmPIPE4_PG_ENABLE[0], sizeof(mmPIPE4_PG_ENABLE)/sizeof(mmPIPE4_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE4_PG_STATUS", REG_MMIO, 0x1772, &mmPIPE4_PG_STATUS[0], sizeof(mmPIPE4_PG_STATUS)/sizeof(mmPIPE4_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE5_PG_CONFIG", REG_MMIO, 0x1774, &mmPIPE5_PG_CONFIG[0], sizeof(mmPIPE5_PG_CONFIG)/sizeof(mmPIPE5_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE5_PG_ENABLE", REG_MMIO, 0x1775, &mmPIPE5_PG_ENABLE[0], sizeof(mmPIPE5_PG_ENABLE)/sizeof(mmPIPE5_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE5_PG_STATUS", REG_MMIO, 0x1776, &mmPIPE5_PG_STATUS[0], sizeof(mmPIPE5_PG_STATUS)/sizeof(mmPIPE5_PG_STATUS[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1779, &mmDCPG_TEST_DEBUG_INDEX[0], sizeof(mmDCPG_TEST_DEBUG_INDEX)/sizeof(mmDCPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_DATA", REG_MMIO, 0x177B, &mmDCPG_TEST_DEBUG_DATA[0], sizeof(mmDCPG_TEST_DEBUG_DATA)/sizeof(mmDCPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDC_PGFSM_CONFIG_REG", REG_MMIO, 0x177C, &mmDC_PGFSM_CONFIG_REG[0], sizeof(mmDC_PGFSM_CONFIG_REG)/sizeof(mmDC_PGFSM_CONFIG_REG[0]), 0, 0 },
+	{ "mmDC_PGFSM_WRITE_REG", REG_MMIO, 0x177D, &mmDC_PGFSM_WRITE_REG[0], sizeof(mmDC_PGFSM_WRITE_REG)/sizeof(mmDC_PGFSM_WRITE_REG[0]), 0, 0 },
+	{ "mmDC_PGCNTL_STATUS_REG", REG_MMIO, 0x177E, &mmDC_PGCNTL_STATUS_REG[0], sizeof(mmDC_PGCNTL_STATUS_REG)/sizeof(mmDC_PGCNTL_STATUS_REG[0]), 0, 0 },
+	{ "mmCC_DC_PIPE_DIS", REG_MMIO, 0x177F, &mmCC_DC_PIPE_DIS[0], sizeof(mmCC_DC_PIPE_DIS)/sizeof(mmCC_DC_PIPE_DIS[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1780, &mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1781, &mmAZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1786, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1787, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x178C, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x178D, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1792, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1793, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1798, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1799, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x179E, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x179F, NULL, 0, 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO", REG_MMIO, 0x17BA, &mmAZALIA_AUDIO_DTO[0], sizeof(mmAZALIA_AUDIO_DTO)/sizeof(mmAZALIA_AUDIO_DTO[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO_CONTROL", REG_MMIO, 0x17BB, &mmAZALIA_AUDIO_DTO_CONTROL[0], sizeof(mmAZALIA_AUDIO_DTO_CONTROL)/sizeof(mmAZALIA_AUDIO_DTO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_SCLK_CONTROL", REG_MMIO, 0x17BC, &mmAZALIA_SCLK_CONTROL[0], sizeof(mmAZALIA_SCLK_CONTROL)/sizeof(mmAZALIA_SCLK_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_UNDERFLOW_FILLER_SAMPLE", REG_MMIO, 0x17BD, &mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0], sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE)/sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0]), 0, 0 },
+	{ "mmAZALIA_DATA_DMA_CONTROL", REG_MMIO, 0x17BE, &mmAZALIA_DATA_DMA_CONTROL[0], sizeof(mmAZALIA_DATA_DMA_CONTROL)/sizeof(mmAZALIA_DATA_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_BDL_DMA_CONTROL", REG_MMIO, 0x17BF, &mmAZALIA_BDL_DMA_CONTROL[0], sizeof(mmAZALIA_BDL_DMA_CONTROL)/sizeof(mmAZALIA_BDL_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_RIRB_AND_DP_CONTROL", REG_MMIO, 0x17C0, &mmAZALIA_RIRB_AND_DP_CONTROL[0], sizeof(mmAZALIA_RIRB_AND_DP_CONTROL)/sizeof(mmAZALIA_RIRB_AND_DP_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_CORB_DMA_CONTROL", REG_MMIO, 0x17C1, &mmAZALIA_CORB_DMA_CONTROL[0], sizeof(mmAZALIA_CORB_DMA_CONTROL)/sizeof(mmAZALIA_CORB_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER", REG_MMIO, 0x17C9, &mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0], sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER)/sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0]), 0, 0 },
+	{ "mmAZALIA_CYCLIC_BUFFER_SYNC", REG_MMIO, 0x17CA, &mmAZALIA_CYCLIC_BUFFER_SYNC[0], sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC)/sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC[0]), 0, 0 },
+	{ "mmAZALIA_GLOBAL_CAPABILITIES", REG_MMIO, 0x17CB, &mmAZALIA_GLOBAL_CAPABILITIES[0], sizeof(mmAZALIA_GLOBAL_CAPABILITIES)/sizeof(mmAZALIA_GLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x17CC, &mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL", REG_MMIO, 0x17CD, &mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0], sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL)/sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_DEBUG", REG_MMIO, 0x17CF, &mmAZALIA_CONTROLLER_DEBUG[0], sizeof(mmAZALIA_CONTROLLER_DEBUG)/sizeof(mmAZALIA_CONTROLLER_DEBUG[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_INDEX", REG_MMIO, 0x17D0, &mmAZ_TEST_DEBUG_INDEX[0], sizeof(mmAZ_TEST_DEBUG_INDEX)/sizeof(mmAZ_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_DATA", REG_MMIO, 0x17D1, &mmAZ_TEST_DEBUG_DATA[0], sizeof(mmAZ_TEST_DEBUG_DATA)/sizeof(mmAZ_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_MMIO, 0x17D2, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID", REG_MMIO, 0x17D3, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY", REG_MMIO, 0x17D4, &mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL", REG_MMIO, 0x17D5, &mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL)/sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL", REG_MMIO, 0x17D6, &mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL)/sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_MMIO, 0x17D7, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_MMIO, 0x17D8, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_MMIO, 0x17D9, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_MMIO, 0x17DA, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_MMIO, 0x17DB, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET", REG_MMIO, 0x17DC, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_MMIO, 0x17DD, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_MMIO, 0x17DE, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_DEBUG", REG_MMIO, 0x17DF, &mmAZALIA_F0_CODEC_DEBUG[0], sizeof(mmAZALIA_F0_CODEC_DEBUG)/sizeof(mmAZALIA_F0_CODEC_DEBUG[0]), 0, 0 },
+	{ "mmAZALIA_STREAM_INDEX", REG_MMIO, 0x17E8, &mmAZALIA_STREAM_INDEX[0], sizeof(mmAZALIA_STREAM_INDEX)/sizeof(mmAZALIA_STREAM_INDEX[0]), 0, 0 },
+	{ "mmAZALIA_STREAM_DATA", REG_MMIO, 0x17E9, &mmAZALIA_STREAM_DATA[0], sizeof(mmAZALIA_STREAM_DATA)/sizeof(mmAZALIA_STREAM_DATA[0]), 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_INDEX", REG_MMIO, 0x17EC, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_DATA", REG_MMIO, 0x17ED, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_INDEX", REG_MMIO, 0x17F0, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_DATA", REG_MMIO, 0x17F1, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_INDEX", REG_MMIO, 0x17F4, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_DATA", REG_MMIO, 0x17F5, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_INDEX", REG_MMIO, 0x17F8, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_DATA", REG_MMIO, 0x17F9, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_INDEX", REG_MMIO, 0x17FC, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_DATA", REG_MMIO, 0x17FD, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET", REG_SMC, 0x17FF, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmDC_HPD1_INT_STATUS", REG_MMIO, 0x1807, &mmDC_HPD1_INT_STATUS[0], sizeof(mmDC_HPD1_INT_STATUS)/sizeof(mmDC_HPD1_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD1_INT_CONTROL", REG_MMIO, 0x1808, &mmDC_HPD1_INT_CONTROL[0], sizeof(mmDC_HPD1_INT_CONTROL)/sizeof(mmDC_HPD1_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD1_CONTROL", REG_MMIO, 0x1809, &mmDC_HPD1_CONTROL[0], sizeof(mmDC_HPD1_CONTROL)/sizeof(mmDC_HPD1_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD2_INT_STATUS", REG_MMIO, 0x180A, &mmDC_HPD2_INT_STATUS[0], sizeof(mmDC_HPD2_INT_STATUS)/sizeof(mmDC_HPD2_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD2_INT_CONTROL", REG_MMIO, 0x180B, &mmDC_HPD2_INT_CONTROL[0], sizeof(mmDC_HPD2_INT_CONTROL)/sizeof(mmDC_HPD2_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD2_CONTROL", REG_MMIO, 0x180C, &mmDC_HPD2_CONTROL[0], sizeof(mmDC_HPD2_CONTROL)/sizeof(mmDC_HPD2_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD3_INT_STATUS", REG_MMIO, 0x180D, &mmDC_HPD3_INT_STATUS[0], sizeof(mmDC_HPD3_INT_STATUS)/sizeof(mmDC_HPD3_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD3_INT_CONTROL", REG_MMIO, 0x180E, &mmDC_HPD3_INT_CONTROL[0], sizeof(mmDC_HPD3_INT_CONTROL)/sizeof(mmDC_HPD3_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD3_CONTROL", REG_MMIO, 0x180F, &mmDC_HPD3_CONTROL[0], sizeof(mmDC_HPD3_CONTROL)/sizeof(mmDC_HPD3_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD4_INT_STATUS", REG_MMIO, 0x1810, &mmDC_HPD4_INT_STATUS[0], sizeof(mmDC_HPD4_INT_STATUS)/sizeof(mmDC_HPD4_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD4_INT_CONTROL", REG_MMIO, 0x1811, &mmDC_HPD4_INT_CONTROL[0], sizeof(mmDC_HPD4_INT_CONTROL)/sizeof(mmDC_HPD4_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD4_CONTROL", REG_MMIO, 0x1812, &mmDC_HPD4_CONTROL[0], sizeof(mmDC_HPD4_CONTROL)/sizeof(mmDC_HPD4_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD5_INT_STATUS", REG_MMIO, 0x1813, &mmDC_HPD5_INT_STATUS[0], sizeof(mmDC_HPD5_INT_STATUS)/sizeof(mmDC_HPD5_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD5_INT_CONTROL", REG_MMIO, 0x1814, &mmDC_HPD5_INT_CONTROL[0], sizeof(mmDC_HPD5_INT_CONTROL)/sizeof(mmDC_HPD5_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD5_CONTROL", REG_MMIO, 0x1815, &mmDC_HPD5_CONTROL[0], sizeof(mmDC_HPD5_CONTROL)/sizeof(mmDC_HPD5_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD6_INT_STATUS", REG_MMIO, 0x1816, &mmDC_HPD6_INT_STATUS[0], sizeof(mmDC_HPD6_INT_STATUS)/sizeof(mmDC_HPD6_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD6_INT_CONTROL", REG_MMIO, 0x1817, &mmDC_HPD6_INT_CONTROL[0], sizeof(mmDC_HPD6_INT_CONTROL)/sizeof(mmDC_HPD6_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD6_CONTROL", REG_MMIO, 0x1818, &mmDC_HPD6_CONTROL[0], sizeof(mmDC_HPD6_CONTROL)/sizeof(mmDC_HPD6_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_CONTROL", REG_MMIO, 0x1819, &mmDC_I2C_CONTROL[0], sizeof(mmDC_I2C_CONTROL)/sizeof(mmDC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_ARBITRATION", REG_MMIO, 0x181A, &mmDC_I2C_ARBITRATION[0], sizeof(mmDC_I2C_ARBITRATION)/sizeof(mmDC_I2C_ARBITRATION[0]), 0, 0 },
+	{ "mmDC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x181B, &mmDC_I2C_INTERRUPT_CONTROL[0], sizeof(mmDC_I2C_INTERRUPT_CONTROL)/sizeof(mmDC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_SW_STATUS", REG_MMIO, 0x181C, &mmDC_I2C_SW_STATUS[0], sizeof(mmDC_I2C_SW_STATUS)/sizeof(mmDC_I2C_SW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_HW_STATUS", REG_MMIO, 0x181D, &mmDC_I2C_DDC1_HW_STATUS[0], sizeof(mmDC_I2C_DDC1_HW_STATUS)/sizeof(mmDC_I2C_DDC1_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_HW_STATUS", REG_MMIO, 0x181E, &mmDC_I2C_DDC2_HW_STATUS[0], sizeof(mmDC_I2C_DDC2_HW_STATUS)/sizeof(mmDC_I2C_DDC2_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_HW_STATUS", REG_MMIO, 0x181F, &mmDC_I2C_DDC3_HW_STATUS[0], sizeof(mmDC_I2C_DDC3_HW_STATUS)/sizeof(mmDC_I2C_DDC3_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_HW_STATUS", REG_MMIO, 0x1820, &mmDC_I2C_DDC4_HW_STATUS[0], sizeof(mmDC_I2C_DDC4_HW_STATUS)/sizeof(mmDC_I2C_DDC4_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_HW_STATUS", REG_MMIO, 0x1821, &mmDC_I2C_DDC5_HW_STATUS[0], sizeof(mmDC_I2C_DDC5_HW_STATUS)/sizeof(mmDC_I2C_DDC5_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_HW_STATUS", REG_MMIO, 0x1822, &mmDC_I2C_DDC6_HW_STATUS[0], sizeof(mmDC_I2C_DDC6_HW_STATUS)/sizeof(mmDC_I2C_DDC6_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SPEED", REG_MMIO, 0x1823, &mmDC_I2C_DDC1_SPEED[0], sizeof(mmDC_I2C_DDC1_SPEED)/sizeof(mmDC_I2C_DDC1_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SETUP", REG_MMIO, 0x1824, &mmDC_I2C_DDC1_SETUP[0], sizeof(mmDC_I2C_DDC1_SETUP)/sizeof(mmDC_I2C_DDC1_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SPEED", REG_MMIO, 0x1825, &mmDC_I2C_DDC2_SPEED[0], sizeof(mmDC_I2C_DDC2_SPEED)/sizeof(mmDC_I2C_DDC2_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SETUP", REG_MMIO, 0x1826, &mmDC_I2C_DDC2_SETUP[0], sizeof(mmDC_I2C_DDC2_SETUP)/sizeof(mmDC_I2C_DDC2_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SPEED", REG_MMIO, 0x1827, &mmDC_I2C_DDC3_SPEED[0], sizeof(mmDC_I2C_DDC3_SPEED)/sizeof(mmDC_I2C_DDC3_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SETUP", REG_MMIO, 0x1828, &mmDC_I2C_DDC3_SETUP[0], sizeof(mmDC_I2C_DDC3_SETUP)/sizeof(mmDC_I2C_DDC3_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SPEED", REG_MMIO, 0x1829, &mmDC_I2C_DDC4_SPEED[0], sizeof(mmDC_I2C_DDC4_SPEED)/sizeof(mmDC_I2C_DDC4_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SETUP", REG_MMIO, 0x182A, &mmDC_I2C_DDC4_SETUP[0], sizeof(mmDC_I2C_DDC4_SETUP)/sizeof(mmDC_I2C_DDC4_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SPEED", REG_MMIO, 0x182B, &mmDC_I2C_DDC5_SPEED[0], sizeof(mmDC_I2C_DDC5_SPEED)/sizeof(mmDC_I2C_DDC5_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SETUP", REG_MMIO, 0x182C, &mmDC_I2C_DDC5_SETUP[0], sizeof(mmDC_I2C_DDC5_SETUP)/sizeof(mmDC_I2C_DDC5_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SPEED", REG_MMIO, 0x182D, &mmDC_I2C_DDC6_SPEED[0], sizeof(mmDC_I2C_DDC6_SPEED)/sizeof(mmDC_I2C_DDC6_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SETUP", REG_MMIO, 0x182E, &mmDC_I2C_DDC6_SETUP[0], sizeof(mmDC_I2C_DDC6_SETUP)/sizeof(mmDC_I2C_DDC6_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION0", REG_MMIO, 0x182F, &mmDC_I2C_TRANSACTION0[0], sizeof(mmDC_I2C_TRANSACTION0)/sizeof(mmDC_I2C_TRANSACTION0[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION1", REG_MMIO, 0x1830, &mmDC_I2C_TRANSACTION1[0], sizeof(mmDC_I2C_TRANSACTION1)/sizeof(mmDC_I2C_TRANSACTION1[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION2", REG_MMIO, 0x1831, &mmDC_I2C_TRANSACTION2[0], sizeof(mmDC_I2C_TRANSACTION2)/sizeof(mmDC_I2C_TRANSACTION2[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION3", REG_MMIO, 0x1832, &mmDC_I2C_TRANSACTION3[0], sizeof(mmDC_I2C_TRANSACTION3)/sizeof(mmDC_I2C_TRANSACTION3[0]), 0, 0 },
+	{ "mmDC_I2C_DATA", REG_MMIO, 0x1833, &mmDC_I2C_DATA[0], sizeof(mmDC_I2C_DATA)/sizeof(mmDC_I2C_DATA[0]), 0, 0 },
+	{ "mmGENERIC_I2C_CONTROL", REG_MMIO, 0x1834, &mmGENERIC_I2C_CONTROL[0], sizeof(mmGENERIC_I2C_CONTROL)/sizeof(mmGENERIC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x1835, &mmGENERIC_I2C_INTERRUPT_CONTROL[0], sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL)/sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_STATUS", REG_MMIO, 0x1836, &mmGENERIC_I2C_STATUS[0], sizeof(mmGENERIC_I2C_STATUS)/sizeof(mmGENERIC_I2C_STATUS[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SPEED", REG_MMIO, 0x1837, &mmGENERIC_I2C_SPEED[0], sizeof(mmGENERIC_I2C_SPEED)/sizeof(mmGENERIC_I2C_SPEED[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SETUP", REG_MMIO, 0x1838, &mmGENERIC_I2C_SETUP[0], sizeof(mmGENERIC_I2C_SETUP)/sizeof(mmGENERIC_I2C_SETUP[0]), 0, 0 },
+	{ "mmGENERIC_I2C_TRANSACTION", REG_MMIO, 0x1839, &mmGENERIC_I2C_TRANSACTION[0], sizeof(mmGENERIC_I2C_TRANSACTION)/sizeof(mmGENERIC_I2C_TRANSACTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_DATA", REG_MMIO, 0x183A, &mmGENERIC_I2C_DATA[0], sizeof(mmGENERIC_I2C_DATA)/sizeof(mmGENERIC_I2C_DATA[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_SELECTION", REG_MMIO, 0x183B, &mmGENERIC_I2C_PIN_SELECTION[0], sizeof(mmGENERIC_I2C_PIN_SELECTION)/sizeof(mmGENERIC_I2C_PIN_SELECTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_DEBUG", REG_MMIO, 0x183C, &mmGENERIC_I2C_PIN_DEBUG[0], sizeof(mmGENERIC_I2C_PIN_DEBUG)/sizeof(mmGENERIC_I2C_PIN_DEBUG[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS", REG_MMIO, 0x183D, &mmDISP_INTERRUPT_STATUS[0], sizeof(mmDISP_INTERRUPT_STATUS)/sizeof(mmDISP_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE", REG_MMIO, 0x183E, &mmDISP_INTERRUPT_STATUS_CONTINUE[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE2", REG_MMIO, 0x183F, &mmDISP_INTERRUPT_STATUS_CONTINUE2[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE3", REG_MMIO, 0x1840, &mmDISP_INTERRUPT_STATUS_CONTINUE3[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3[0]), 0, 0 },
+	{ "mmDOUT_POWER_MANAGEMENT_CNTL", REG_MMIO, 0x1841, &mmDOUT_POWER_MANAGEMENT_CNTL[0], sizeof(mmDOUT_POWER_MANAGEMENT_CNTL)/sizeof(mmDOUT_POWER_MANAGEMENT_CNTL[0]), 0, 0 },
+	{ "mmDISP_TIMER_CONTROL", REG_MMIO, 0x1842, &mmDISP_TIMER_CONTROL[0], sizeof(mmDISP_TIMER_CONTROL)/sizeof(mmDISP_TIMER_CONTROL[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH0", REG_MMIO, 0x1844, &mmDOUT_SCRATCH0[0], sizeof(mmDOUT_SCRATCH0)/sizeof(mmDOUT_SCRATCH0[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH1", REG_MMIO, 0x1845, &mmDOUT_SCRATCH1[0], sizeof(mmDOUT_SCRATCH1)/sizeof(mmDOUT_SCRATCH1[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH2", REG_MMIO, 0x1846, &mmDOUT_SCRATCH2[0], sizeof(mmDOUT_SCRATCH2)/sizeof(mmDOUT_SCRATCH2[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH3", REG_MMIO, 0x1847, &mmDOUT_SCRATCH3[0], sizeof(mmDOUT_SCRATCH3)/sizeof(mmDOUT_SCRATCH3[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH4", REG_MMIO, 0x1848, &mmDOUT_SCRATCH4[0], sizeof(mmDOUT_SCRATCH4)/sizeof(mmDOUT_SCRATCH4[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH5", REG_MMIO, 0x1849, &mmDOUT_SCRATCH5[0], sizeof(mmDOUT_SCRATCH5)/sizeof(mmDOUT_SCRATCH5[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH6", REG_MMIO, 0x184A, &mmDOUT_SCRATCH6[0], sizeof(mmDOUT_SCRATCH6)/sizeof(mmDOUT_SCRATCH6[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH7", REG_MMIO, 0x184B, &mmDOUT_SCRATCH7[0], sizeof(mmDOUT_SCRATCH7)/sizeof(mmDOUT_SCRATCH7[0]), 0, 0 },
+	{ "mmDOUT_TEST_DEBUG_INDEX", REG_MMIO, 0x184D, &mmDOUT_TEST_DEBUG_INDEX[0], sizeof(mmDOUT_TEST_DEBUG_INDEX)/sizeof(mmDOUT_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDOUT_TEST_DEBUG_DATA", REG_MMIO, 0x184E, &mmDOUT_TEST_DEBUG_DATA[0], sizeof(mmDOUT_TEST_DEBUG_DATA)/sizeof(mmDOUT_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE4", REG_MMIO, 0x1853, &mmDISP_INTERRUPT_STATUS_CONTINUE4[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE5", REG_MMIO, 0x1854, &mmDISP_INTERRUPT_STATUS_CONTINUE5[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_HW_STATUS", REG_MMIO, 0x1855, &mmDC_I2C_DDCVGA_HW_STATUS[0], sizeof(mmDC_I2C_DDCVGA_HW_STATUS)/sizeof(mmDC_I2C_DDCVGA_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SPEED", REG_MMIO, 0x1856, &mmDC_I2C_DDCVGA_SPEED[0], sizeof(mmDC_I2C_DDCVGA_SPEED)/sizeof(mmDC_I2C_DDCVGA_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SETUP", REG_MMIO, 0x1857, &mmDC_I2C_DDCVGA_SETUP[0], sizeof(mmDC_I2C_DDCVGA_SETUP)/sizeof(mmDC_I2C_DDCVGA_SETUP[0]), 0, 0 },
+	{ "mmDVO_ENABLE", REG_MMIO, 0x1858, &mmDVO_ENABLE[0], sizeof(mmDVO_ENABLE)/sizeof(mmDVO_ENABLE[0]), 0, 0 },
+	{ "mmDVO_SOURCE_SELECT", REG_MMIO, 0x1859, &mmDVO_SOURCE_SELECT[0], sizeof(mmDVO_SOURCE_SELECT)/sizeof(mmDVO_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDVO_OUTPUT", REG_MMIO, 0x185A, &mmDVO_OUTPUT[0], sizeof(mmDVO_OUTPUT)/sizeof(mmDVO_OUTPUT[0]), 0, 0 },
+	{ "mmDVO_CONTROL", REG_MMIO, 0x185B, &mmDVO_CONTROL[0], sizeof(mmDVO_CONTROL)/sizeof(mmDVO_CONTROL[0]), 0, 0 },
+	{ "mmDVO_CRC_EN", REG_MMIO, 0x185C, &mmDVO_CRC_EN[0], sizeof(mmDVO_CRC_EN)/sizeof(mmDVO_CRC_EN[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_MASK", REG_MMIO, 0x185D, &mmDVO_CRC2_SIG_MASK[0], sizeof(mmDVO_CRC2_SIG_MASK)/sizeof(mmDVO_CRC2_SIG_MASK[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_RESULT", REG_MMIO, 0x185E, &mmDVO_CRC2_SIG_RESULT[0], sizeof(mmDVO_CRC2_SIG_RESULT)/sizeof(mmDVO_CRC2_SIG_RESULT[0]), 0, 0 },
+	{ "mmDVO_FIFO_ERROR_STATUS", REG_MMIO, 0x185F, &mmDVO_FIFO_ERROR_STATUS[0], sizeof(mmDVO_FIFO_ERROR_STATUS)/sizeof(mmDVO_FIFO_ERROR_STATUS[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK1_SEL", REG_MMIO, 0x1860, &mmDCDEBUG_BUS_CLK1_SEL[0], sizeof(mmDCDEBUG_BUS_CLK1_SEL)/sizeof(mmDCDEBUG_BUS_CLK1_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK2_SEL", REG_MMIO, 0x1861, &mmDCDEBUG_BUS_CLK2_SEL[0], sizeof(mmDCDEBUG_BUS_CLK2_SEL)/sizeof(mmDCDEBUG_BUS_CLK2_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK3_SEL", REG_MMIO, 0x1862, &mmDCDEBUG_BUS_CLK3_SEL[0], sizeof(mmDCDEBUG_BUS_CLK3_SEL)/sizeof(mmDCDEBUG_BUS_CLK3_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK4_SEL", REG_MMIO, 0x1863, &mmDCDEBUG_BUS_CLK4_SEL[0], sizeof(mmDCDEBUG_BUS_CLK4_SEL)/sizeof(mmDCDEBUG_BUS_CLK4_SEL[0]), 0, 0 },
+	{ "mmDC_HPD1_FAST_TRAIN_CNTL", REG_MMIO, 0x1864, &mmDC_HPD1_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD1_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD1_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD2_FAST_TRAIN_CNTL", REG_MMIO, 0x1865, &mmDC_HPD2_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD2_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD2_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD3_FAST_TRAIN_CNTL", REG_MMIO, 0x1866, &mmDC_HPD3_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD3_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD3_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD4_FAST_TRAIN_CNTL", REG_MMIO, 0x1867, &mmDC_HPD4_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD4_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD4_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD5_FAST_TRAIN_CNTL", REG_MMIO, 0x1868, &mmDC_HPD5_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD5_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD5_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD6_FAST_TRAIN_CNTL", REG_MMIO, 0x1869, &mmDC_HPD6_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD6_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD6_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_PIN_OVERRIDE", REG_MMIO, 0x186A, &mmDCDEBUG_OUT_PIN_OVERRIDE[0], sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE)/sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_CNTL", REG_MMIO, 0x186B, &mmDCDEBUG_OUT_CNTL[0], sizeof(mmDCDEBUG_OUT_CNTL)/sizeof(mmDCDEBUG_OUT_CNTL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_DATA", REG_MMIO, 0x186E, &mmDCDEBUG_OUT_DATA[0], sizeof(mmDCDEBUG_OUT_DATA)/sizeof(mmDCDEBUG_OUT_DATA[0]), 0, 0 },
+	{ "mmDC_I2C_EDID_DETECT_CTRL", REG_MMIO, 0x186F, &mmDC_I2C_EDID_DETECT_CTRL[0], sizeof(mmDC_I2C_EDID_DETECT_CTRL)/sizeof(mmDC_I2C_EDID_DETECT_CTRL[0]), 0, 0 },
+	{ "mmAUX_CONTROL", REG_MMIO, 0x1880, &mmAUX_CONTROL[0], sizeof(mmAUX_CONTROL)/sizeof(mmAUX_CONTROL[0]), 0, 0 },
+	{ "mmAUX_SW_CONTROL", REG_MMIO, 0x1881, &mmAUX_SW_CONTROL[0], sizeof(mmAUX_SW_CONTROL)/sizeof(mmAUX_SW_CONTROL[0]), 0, 0 },
+	{ "mmAUX_ARB_CONTROL", REG_MMIO, 0x1882, &mmAUX_ARB_CONTROL[0], sizeof(mmAUX_ARB_CONTROL)/sizeof(mmAUX_ARB_CONTROL[0]), 0, 0 },
+	{ "mmAUX_INTERRUPT_CONTROL", REG_MMIO, 0x1883, &mmAUX_INTERRUPT_CONTROL[0], sizeof(mmAUX_INTERRUPT_CONTROL)/sizeof(mmAUX_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmAUX_SW_STATUS", REG_MMIO, 0x1884, &mmAUX_SW_STATUS[0], sizeof(mmAUX_SW_STATUS)/sizeof(mmAUX_SW_STATUS[0]), 0, 0 },
+	{ "mmAUX_LS_STATUS", REG_MMIO, 0x1885, &mmAUX_LS_STATUS[0], sizeof(mmAUX_LS_STATUS)/sizeof(mmAUX_LS_STATUS[0]), 0, 0 },
+	{ "mmAUX_SW_DATA", REG_MMIO, 0x1886, &mmAUX_SW_DATA[0], sizeof(mmAUX_SW_DATA)/sizeof(mmAUX_SW_DATA[0]), 0, 0 },
+	{ "mmAUX_LS_DATA", REG_MMIO, 0x1887, &mmAUX_LS_DATA[0], sizeof(mmAUX_LS_DATA)/sizeof(mmAUX_LS_DATA[0]), 0, 0 },
+	{ "mmAUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1888, &mmAUX_DPHY_TX_REF_CONTROL[0], sizeof(mmAUX_DPHY_TX_REF_CONTROL)/sizeof(mmAUX_DPHY_TX_REF_CONTROL[0]), 0, 0 },
+	{ "mmAUX_DPHY_TX_CONTROL", REG_MMIO, 0x1889, &mmAUX_DPHY_TX_CONTROL[0], sizeof(mmAUX_DPHY_TX_CONTROL)/sizeof(mmAUX_DPHY_TX_CONTROL[0]), 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL0", REG_MMIO, 0x188A, &mmAUX_DPHY_RX_CONTROL0[0], sizeof(mmAUX_DPHY_RX_CONTROL0)/sizeof(mmAUX_DPHY_RX_CONTROL0[0]), 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL1", REG_MMIO, 0x188B, &mmAUX_DPHY_RX_CONTROL1[0], sizeof(mmAUX_DPHY_RX_CONTROL1)/sizeof(mmAUX_DPHY_RX_CONTROL1[0]), 0, 0 },
+	{ "mmAUX_DPHY_TX_STATUS", REG_MMIO, 0x188C, &mmAUX_DPHY_TX_STATUS[0], sizeof(mmAUX_DPHY_TX_STATUS)/sizeof(mmAUX_DPHY_TX_STATUS[0]), 0, 0 },
+	{ "mmAUX_DPHY_RX_STATUS", REG_MMIO, 0x188D, &mmAUX_DPHY_RX_STATUS[0], sizeof(mmAUX_DPHY_RX_STATUS)/sizeof(mmAUX_DPHY_RX_STATUS[0]), 0, 0 },
+	{ "mmAUX_GTC_SYNC_CONTROL", REG_MMIO, 0x188E, &mmAUX_GTC_SYNC_CONTROL[0], sizeof(mmAUX_GTC_SYNC_CONTROL)/sizeof(mmAUX_GTC_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmAUX_GTC_SYNC_DATA", REG_MMIO, 0x1890, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_CONTROL", REG_MMIO, 0x1894, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_CONTROL", REG_MMIO, 0x1895, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_ARB_CONTROL", REG_MMIO, 0x1896, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1897, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_STATUS", REG_MMIO, 0x1898, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_STATUS", REG_MMIO, 0x1899, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_DATA", REG_MMIO, 0x189A, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_DATA", REG_MMIO, 0x189B, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x189C, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x189D, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x189E, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x189F, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18A0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18A1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18A2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18A4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_CONTROL", REG_MMIO, 0x18A8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_CONTROL", REG_MMIO, 0x18A9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_ARB_CONTROL", REG_MMIO, 0x18AA, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x18AB, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_STATUS", REG_MMIO, 0x18AC, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_STATUS", REG_MMIO, 0x18AD, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_DATA", REG_MMIO, 0x18AE, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_DATA", REG_MMIO, 0x18AF, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x18B0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x18B1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x18B2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x18B3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18B4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18B5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18B6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18B8, NULL, 0, 0, 0 },
+	{ "mmDC_HPD1_TOGGLE_FILT_CNTL", REG_MMIO, 0x18BC, &mmDC_HPD1_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD1_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD1_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD2_TOGGLE_FILT_CNTL", REG_MMIO, 0x18BD, &mmDC_HPD2_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD2_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD2_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD3_TOGGLE_FILT_CNTL", REG_MMIO, 0x18BE, &mmDC_HPD3_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD3_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD3_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDISPOUT_STEREOSYNC_SEL", REG_MMIO, 0x18BF, &mmDISPOUT_STEREOSYNC_SEL[0], sizeof(mmDISPOUT_STEREOSYNC_SEL)/sizeof(mmDISPOUT_STEREOSYNC_SEL[0]), 0, 0 },
+	{ "mmDP_AUX3_AUX_CONTROL", REG_MMIO, 0x18C0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_CONTROL", REG_MMIO, 0x18C1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_ARB_CONTROL", REG_MMIO, 0x18C2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x18C3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_STATUS", REG_MMIO, 0x18C4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_STATUS", REG_MMIO, 0x18C5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_DATA", REG_MMIO, 0x18C6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_DATA", REG_MMIO, 0x18C7, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x18C8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x18C9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x18CA, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x18CB, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18CC, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18CD, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18CE, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18D0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_CONTROL", REG_MMIO, 0x18D4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_CONTROL", REG_MMIO, 0x18D5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_ARB_CONTROL", REG_MMIO, 0x18D6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x18D7, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_STATUS", REG_MMIO, 0x18D8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_STATUS", REG_MMIO, 0x18D9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_DATA", REG_MMIO, 0x18DA, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_DATA", REG_MMIO, 0x18DB, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x18DC, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x18DD, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x18DE, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x18DF, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18E0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18E1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18E2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18E4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_CONTROL", REG_MMIO, 0x18E8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_CONTROL", REG_MMIO, 0x18E9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_ARB_CONTROL", REG_MMIO, 0x18EA, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x18EB, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_STATUS", REG_MMIO, 0x18EC, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_STATUS", REG_MMIO, 0x18ED, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_DATA", REG_MMIO, 0x18EE, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_DATA", REG_MMIO, 0x18EF, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x18F0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x18F1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x18F2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x18F3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18F4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18F5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18F6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18F8, NULL, 0, 0, 0 },
+	{ "mmDC_HPD4_TOGGLE_FILT_CNTL", REG_MMIO, 0x18FC, &mmDC_HPD4_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD4_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD4_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD5_TOGGLE_FILT_CNTL", REG_MMIO, 0x18FD, &mmDC_HPD5_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD5_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD5_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD6_TOGGLE_FILT_CNTL", REG_MMIO, 0x18FE, &mmDC_HPD6_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD6_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD6_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDOUT_DCE_VCE_CONTROL", REG_MMIO, 0x18FF, &mmDOUT_DCE_VCE_CONTROL[0], sizeof(mmDOUT_DCE_VCE_CONTROL)/sizeof(mmDOUT_DCE_VCE_CONTROL[0]), 0, 0 },
+	{ "mmDC_GENERICA", REG_MMIO, 0x1900, &mmDC_GENERICA[0], sizeof(mmDC_GENERICA)/sizeof(mmDC_GENERICA[0]), 0, 0 },
+	{ "mmDC_GENERICB", REG_MMIO, 0x1901, &mmDC_GENERICB[0], sizeof(mmDC_GENERICB)/sizeof(mmDC_GENERICB[0]), 0, 0 },
+	{ "mmDC_PAD_EXTERN_SIG", REG_MMIO, 0x1902, &mmDC_PAD_EXTERN_SIG[0], sizeof(mmDC_PAD_EXTERN_SIG)/sizeof(mmDC_PAD_EXTERN_SIG[0]), 0, 0 },
+	{ "mmDC_REF_CLK_CNTL", REG_MMIO, 0x1903, &mmDC_REF_CLK_CNTL[0], sizeof(mmDC_REF_CLK_CNTL)/sizeof(mmDC_REF_CLK_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_DEBUG", REG_MMIO, 0x1904, &mmDC_GPIO_DEBUG[0], sizeof(mmDC_GPIO_DEBUG)/sizeof(mmDC_GPIO_DEBUG[0]), 0, 0 },
+	{ "mmDC_DVODATA_CONFIG", REG_MMIO, 0x1905, &mmDC_DVODATA_CONFIG[0], sizeof(mmDC_DVODATA_CONFIG)/sizeof(mmDC_DVODATA_CONFIG[0]), 0, 0 },
+	{ "mmDCO_MEM_POWER_STATE", REG_MMIO, 0x1906, &mmDCO_MEM_POWER_STATE[0], sizeof(mmDCO_MEM_POWER_STATE)/sizeof(mmDCO_MEM_POWER_STATE[0]), 0, 0 },
+	{ "mmDCO_LIGHT_SLEEP_DIS", REG_MMIO, 0x1907, &mmDCO_LIGHT_SLEEP_DIS[0], sizeof(mmDCO_LIGHT_SLEEP_DIS)/sizeof(mmDCO_LIGHT_SLEEP_DIS[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKA", REG_MMIO, 0x1908, &mmUNIPHY_IMPCAL_LINKA[0], sizeof(mmUNIPHY_IMPCAL_LINKA)/sizeof(mmUNIPHY_IMPCAL_LINKA[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKB", REG_MMIO, 0x1909, &mmUNIPHY_IMPCAL_LINKB[0], sizeof(mmUNIPHY_IMPCAL_LINKB)/sizeof(mmUNIPHY_IMPCAL_LINKB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PERIOD", REG_MMIO, 0x190A, &mmUNIPHY_IMPCAL_PERIOD[0], sizeof(mmUNIPHY_IMPCAL_PERIOD)/sizeof(mmUNIPHY_IMPCAL_PERIOD[0]), 0, 0 },
+	{ "mmAUXP_IMPCAL", REG_MMIO, 0x190B, &mmAUXP_IMPCAL[0], sizeof(mmAUXP_IMPCAL)/sizeof(mmAUXP_IMPCAL[0]), 0, 0 },
+	{ "mmAUXN_IMPCAL", REG_MMIO, 0x190C, &mmAUXN_IMPCAL[0], sizeof(mmAUXN_IMPCAL)/sizeof(mmAUXN_IMPCAL[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_AB", REG_MMIO, 0x190D, &mmDCIO_IMPCAL_CNTL_AB[0], sizeof(mmDCIO_IMPCAL_CNTL_AB)/sizeof(mmDCIO_IMPCAL_CNTL_AB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_AB", REG_MMIO, 0x190E, &mmUNIPHY_IMPCAL_PSW_AB[0], sizeof(mmUNIPHY_IMPCAL_PSW_AB)/sizeof(mmUNIPHY_IMPCAL_PSW_AB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKC", REG_MMIO, 0x190F, &mmUNIPHY_IMPCAL_LINKC[0], sizeof(mmUNIPHY_IMPCAL_LINKC)/sizeof(mmUNIPHY_IMPCAL_LINKC[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKD", REG_MMIO, 0x1910, &mmUNIPHY_IMPCAL_LINKD[0], sizeof(mmUNIPHY_IMPCAL_LINKD)/sizeof(mmUNIPHY_IMPCAL_LINKD[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_CD", REG_MMIO, 0x1911, &mmDCIO_IMPCAL_CNTL_CD[0], sizeof(mmDCIO_IMPCAL_CNTL_CD)/sizeof(mmDCIO_IMPCAL_CNTL_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_CD", REG_MMIO, 0x1912, &mmUNIPHY_IMPCAL_PSW_CD[0], sizeof(mmUNIPHY_IMPCAL_PSW_CD)/sizeof(mmUNIPHY_IMPCAL_PSW_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKE", REG_MMIO, 0x1913, &mmUNIPHY_IMPCAL_LINKE[0], sizeof(mmUNIPHY_IMPCAL_LINKE)/sizeof(mmUNIPHY_IMPCAL_LINKE[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKF", REG_MMIO, 0x1914, &mmUNIPHY_IMPCAL_LINKF[0], sizeof(mmUNIPHY_IMPCAL_LINKF)/sizeof(mmUNIPHY_IMPCAL_LINKF[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_EF", REG_MMIO, 0x1915, &mmDCIO_IMPCAL_CNTL_EF[0], sizeof(mmDCIO_IMPCAL_CNTL_EF)/sizeof(mmDCIO_IMPCAL_CNTL_EF[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_EF", REG_MMIO, 0x1916, &mmUNIPHY_IMPCAL_PSW_EF[0], sizeof(mmUNIPHY_IMPCAL_PSW_EF)/sizeof(mmUNIPHY_IMPCAL_PSW_EF[0]), 0, 0 },
+	{ "mmDC_PINSTRAPS", REG_MMIO, 0x1917, &mmDC_PINSTRAPS[0], sizeof(mmDC_PINSTRAPS)/sizeof(mmDC_PINSTRAPS[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_CNTL", REG_MMIO, 0x1919, &mmLVTMA_PWRSEQ_CNTL[0], sizeof(mmLVTMA_PWRSEQ_CNTL)/sizeof(mmLVTMA_PWRSEQ_CNTL[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_STATE", REG_MMIO, 0x191A, &mmLVTMA_PWRSEQ_STATE[0], sizeof(mmLVTMA_PWRSEQ_STATE)/sizeof(mmLVTMA_PWRSEQ_STATE[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_REF_DIV", REG_MMIO, 0x191B, &mmLVTMA_PWRSEQ_REF_DIV[0], sizeof(mmLVTMA_PWRSEQ_REF_DIV)/sizeof(mmLVTMA_PWRSEQ_REF_DIV[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY1", REG_MMIO, 0x191C, &mmLVTMA_PWRSEQ_DELAY1[0], sizeof(mmLVTMA_PWRSEQ_DELAY1)/sizeof(mmLVTMA_PWRSEQ_DELAY1[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY2", REG_MMIO, 0x191D, &mmLVTMA_PWRSEQ_DELAY2[0], sizeof(mmLVTMA_PWRSEQ_DELAY2)/sizeof(mmLVTMA_PWRSEQ_DELAY2[0]), 0, 0 },
+	{ "mmBL_PWM_CNTL", REG_MMIO, 0x191E, &mmBL_PWM_CNTL[0], sizeof(mmBL_PWM_CNTL)/sizeof(mmBL_PWM_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_CNTL2", REG_MMIO, 0x191F, &mmBL_PWM_CNTL2[0], sizeof(mmBL_PWM_CNTL2)/sizeof(mmBL_PWM_CNTL2[0]), 0, 0 },
+	{ "mmBL_PWM_PERIOD_CNTL", REG_MMIO, 0x1920, &mmBL_PWM_PERIOD_CNTL[0], sizeof(mmBL_PWM_PERIOD_CNTL)/sizeof(mmBL_PWM_PERIOD_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_GRP1_REG_LOCK", REG_MMIO, 0x1921, &mmBL_PWM_GRP1_REG_LOCK[0], sizeof(mmBL_PWM_GRP1_REG_LOCK)/sizeof(mmBL_PWM_GRP1_REG_LOCK[0]), 0, 0 },
+	{ "mmDCIO_GSL_GENLK_PAD_CNTL", REG_MMIO, 0x1922, &mmDCIO_GSL_GENLK_PAD_CNTL[0], sizeof(mmDCIO_GSL_GENLK_PAD_CNTL)/sizeof(mmDCIO_GSL_GENLK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL_SWAPLOCK_PAD_CNTL", REG_MMIO, 0x1923, &mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0], sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL)/sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL0_CNTL", REG_MMIO, 0x1924, &mmDCIO_GSL0_CNTL[0], sizeof(mmDCIO_GSL0_CNTL)/sizeof(mmDCIO_GSL0_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL1_CNTL", REG_MMIO, 0x1925, &mmDCIO_GSL1_CNTL[0], sizeof(mmDCIO_GSL1_CNTL)/sizeof(mmDCIO_GSL1_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL2_CNTL", REG_MMIO, 0x1926, &mmDCIO_GSL2_CNTL[0], sizeof(mmDCIO_GSL2_CNTL)/sizeof(mmDCIO_GSL2_CNTL[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_V_UPDATE", REG_MMIO, 0x1927, &mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0], sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE)/sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_P_FLIP", REG_MMIO, 0x1928, &mmDC_GPU_TIMER_START_POSITION_P_FLIP[0], sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP)/sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ", REG_MMIO, 0x1929, &mmDC_GPU_TIMER_READ[0], sizeof(mmDC_GPU_TIMER_READ)/sizeof(mmDC_GPU_TIMER_READ[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ_CNTL", REG_MMIO, 0x192A, &mmDC_GPU_TIMER_READ_CNTL[0], sizeof(mmDC_GPU_TIMER_READ_CNTL)/sizeof(mmDC_GPU_TIMER_READ_CNTL[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL", REG_MMIO, 0x192B, &mmDCO_CLK_CNTL[0], sizeof(mmDCO_CLK_CNTL)/sizeof(mmDCO_CLK_CNTL[0]), 0, 0 },
+	{ "mmDCO_CLK_RAMP_CNTL", REG_MMIO, 0x192C, &mmDCO_CLK_RAMP_CNTL[0], sizeof(mmDCO_CLK_RAMP_CNTL)/sizeof(mmDCO_CLK_RAMP_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DEBUG", REG_MMIO, 0x192E, &mmDCIO_DEBUG[0], sizeof(mmDCIO_DEBUG)/sizeof(mmDCIO_DEBUG[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_INDEX", REG_MMIO, 0x192F, &mmDCIO_TEST_DEBUG_INDEX[0], sizeof(mmDCIO_TEST_DEBUG_INDEX)/sizeof(mmDCIO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_DATA", REG_MMIO, 0x1930, &mmDCIO_TEST_DEBUG_DATA[0], sizeof(mmDCIO_TEST_DEBUG_DATA)/sizeof(mmDCIO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmUNIPHYAB_TPG_CONTROL", REG_MMIO, 0x1931, &mmUNIPHYAB_TPG_CONTROL[0], sizeof(mmUNIPHYAB_TPG_CONTROL)/sizeof(mmUNIPHYAB_TPG_CONTROL[0]), 0, 0 },
+	{ "mmUNIPHYAB_TPG_SEED", REG_MMIO, 0x1932, &mmUNIPHYAB_TPG_SEED[0], sizeof(mmUNIPHYAB_TPG_SEED)/sizeof(mmUNIPHYAB_TPG_SEED[0]), 0, 0 },
+	{ "mmUNIPHYCD_TPG_CONTROL", REG_MMIO, 0x1933, &mmUNIPHYCD_TPG_CONTROL[0], sizeof(mmUNIPHYCD_TPG_CONTROL)/sizeof(mmUNIPHYCD_TPG_CONTROL[0]), 0, 0 },
+	{ "mmUNIPHYCD_TPG_SEED", REG_MMIO, 0x1934, &mmUNIPHYCD_TPG_SEED[0], sizeof(mmUNIPHYCD_TPG_SEED)/sizeof(mmUNIPHYCD_TPG_SEED[0]), 0, 0 },
+	{ "mmUNIPHYEF_TPG_CONTROL", REG_MMIO, 0x1935, &mmUNIPHYEF_TPG_CONTROL[0], sizeof(mmUNIPHYEF_TPG_CONTROL)/sizeof(mmUNIPHYEF_TPG_CONTROL[0]), 0, 0 },
+	{ "mmUNIPHYEF_TPG_SEED", REG_MMIO, 0x1936, &mmUNIPHYEF_TPG_SEED[0], sizeof(mmUNIPHYEF_TPG_SEED)/sizeof(mmUNIPHYEF_TPG_SEED[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_MASK", REG_MMIO, 0x1940, &mmDC_GPIO_PWRSEQ_MASK[0], sizeof(mmDC_GPIO_PWRSEQ_MASK)/sizeof(mmDC_GPIO_PWRSEQ_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_A", REG_MMIO, 0x1941, &mmDC_GPIO_PWRSEQ_A[0], sizeof(mmDC_GPIO_PWRSEQ_A)/sizeof(mmDC_GPIO_PWRSEQ_A[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_EN", REG_MMIO, 0x1942, &mmDC_GPIO_PWRSEQ_EN[0], sizeof(mmDC_GPIO_PWRSEQ_EN)/sizeof(mmDC_GPIO_PWRSEQ_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_Y", REG_MMIO, 0x1943, &mmDC_GPIO_PWRSEQ_Y[0], sizeof(mmDC_GPIO_PWRSEQ_Y)/sizeof(mmDC_GPIO_PWRSEQ_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_MASK", REG_MMIO, 0x1944, &mmDC_GPIO_GENERIC_MASK[0], sizeof(mmDC_GPIO_GENERIC_MASK)/sizeof(mmDC_GPIO_GENERIC_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_A", REG_MMIO, 0x1945, &mmDC_GPIO_GENERIC_A[0], sizeof(mmDC_GPIO_GENERIC_A)/sizeof(mmDC_GPIO_GENERIC_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_EN", REG_MMIO, 0x1946, &mmDC_GPIO_GENERIC_EN[0], sizeof(mmDC_GPIO_GENERIC_EN)/sizeof(mmDC_GPIO_GENERIC_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_Y", REG_MMIO, 0x1947, &mmDC_GPIO_GENERIC_Y[0], sizeof(mmDC_GPIO_GENERIC_Y)/sizeof(mmDC_GPIO_GENERIC_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_MASK", REG_MMIO, 0x1948, &mmDC_GPIO_DVODATA_MASK[0], sizeof(mmDC_GPIO_DVODATA_MASK)/sizeof(mmDC_GPIO_DVODATA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_A", REG_MMIO, 0x1949, &mmDC_GPIO_DVODATA_A[0], sizeof(mmDC_GPIO_DVODATA_A)/sizeof(mmDC_GPIO_DVODATA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_EN", REG_MMIO, 0x194A, &mmDC_GPIO_DVODATA_EN[0], sizeof(mmDC_GPIO_DVODATA_EN)/sizeof(mmDC_GPIO_DVODATA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_Y", REG_MMIO, 0x194B, &mmDC_GPIO_DVODATA_Y[0], sizeof(mmDC_GPIO_DVODATA_Y)/sizeof(mmDC_GPIO_DVODATA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_MASK", REG_MMIO, 0x194C, &mmDC_GPIO_DDC1_MASK[0], sizeof(mmDC_GPIO_DDC1_MASK)/sizeof(mmDC_GPIO_DDC1_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_A", REG_MMIO, 0x194D, &mmDC_GPIO_DDC1_A[0], sizeof(mmDC_GPIO_DDC1_A)/sizeof(mmDC_GPIO_DDC1_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_EN", REG_MMIO, 0x194E, &mmDC_GPIO_DDC1_EN[0], sizeof(mmDC_GPIO_DDC1_EN)/sizeof(mmDC_GPIO_DDC1_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_Y", REG_MMIO, 0x194F, &mmDC_GPIO_DDC1_Y[0], sizeof(mmDC_GPIO_DDC1_Y)/sizeof(mmDC_GPIO_DDC1_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_MASK", REG_MMIO, 0x1950, &mmDC_GPIO_DDC2_MASK[0], sizeof(mmDC_GPIO_DDC2_MASK)/sizeof(mmDC_GPIO_DDC2_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_A", REG_MMIO, 0x1951, &mmDC_GPIO_DDC2_A[0], sizeof(mmDC_GPIO_DDC2_A)/sizeof(mmDC_GPIO_DDC2_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_EN", REG_MMIO, 0x1952, &mmDC_GPIO_DDC2_EN[0], sizeof(mmDC_GPIO_DDC2_EN)/sizeof(mmDC_GPIO_DDC2_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_Y", REG_MMIO, 0x1953, &mmDC_GPIO_DDC2_Y[0], sizeof(mmDC_GPIO_DDC2_Y)/sizeof(mmDC_GPIO_DDC2_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_MASK", REG_MMIO, 0x1954, &mmDC_GPIO_DDC3_MASK[0], sizeof(mmDC_GPIO_DDC3_MASK)/sizeof(mmDC_GPIO_DDC3_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_A", REG_MMIO, 0x1955, &mmDC_GPIO_DDC3_A[0], sizeof(mmDC_GPIO_DDC3_A)/sizeof(mmDC_GPIO_DDC3_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_EN", REG_MMIO, 0x1956, &mmDC_GPIO_DDC3_EN[0], sizeof(mmDC_GPIO_DDC3_EN)/sizeof(mmDC_GPIO_DDC3_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_Y", REG_MMIO, 0x1957, &mmDC_GPIO_DDC3_Y[0], sizeof(mmDC_GPIO_DDC3_Y)/sizeof(mmDC_GPIO_DDC3_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_MASK", REG_MMIO, 0x1958, &mmDC_GPIO_DDC4_MASK[0], sizeof(mmDC_GPIO_DDC4_MASK)/sizeof(mmDC_GPIO_DDC4_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_A", REG_MMIO, 0x1959, &mmDC_GPIO_DDC4_A[0], sizeof(mmDC_GPIO_DDC4_A)/sizeof(mmDC_GPIO_DDC4_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_EN", REG_MMIO, 0x195A, &mmDC_GPIO_DDC4_EN[0], sizeof(mmDC_GPIO_DDC4_EN)/sizeof(mmDC_GPIO_DDC4_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_Y", REG_MMIO, 0x195B, &mmDC_GPIO_DDC4_Y[0], sizeof(mmDC_GPIO_DDC4_Y)/sizeof(mmDC_GPIO_DDC4_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_MASK", REG_MMIO, 0x195C, &mmDC_GPIO_DDC5_MASK[0], sizeof(mmDC_GPIO_DDC5_MASK)/sizeof(mmDC_GPIO_DDC5_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_A", REG_MMIO, 0x195D, &mmDC_GPIO_DDC5_A[0], sizeof(mmDC_GPIO_DDC5_A)/sizeof(mmDC_GPIO_DDC5_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_EN", REG_MMIO, 0x195E, &mmDC_GPIO_DDC5_EN[0], sizeof(mmDC_GPIO_DDC5_EN)/sizeof(mmDC_GPIO_DDC5_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_Y", REG_MMIO, 0x195F, &mmDC_GPIO_DDC5_Y[0], sizeof(mmDC_GPIO_DDC5_Y)/sizeof(mmDC_GPIO_DDC5_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_MASK", REG_MMIO, 0x1960, &mmDC_GPIO_DDC6_MASK[0], sizeof(mmDC_GPIO_DDC6_MASK)/sizeof(mmDC_GPIO_DDC6_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_A", REG_MMIO, 0x1961, &mmDC_GPIO_DDC6_A[0], sizeof(mmDC_GPIO_DDC6_A)/sizeof(mmDC_GPIO_DDC6_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_EN", REG_MMIO, 0x1962, &mmDC_GPIO_DDC6_EN[0], sizeof(mmDC_GPIO_DDC6_EN)/sizeof(mmDC_GPIO_DDC6_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_Y", REG_MMIO, 0x1963, &mmDC_GPIO_DDC6_Y[0], sizeof(mmDC_GPIO_DDC6_Y)/sizeof(mmDC_GPIO_DDC6_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_MASK", REG_MMIO, 0x1964, &mmDC_GPIO_SYNCA_MASK[0], sizeof(mmDC_GPIO_SYNCA_MASK)/sizeof(mmDC_GPIO_SYNCA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_A", REG_MMIO, 0x1965, &mmDC_GPIO_SYNCA_A[0], sizeof(mmDC_GPIO_SYNCA_A)/sizeof(mmDC_GPIO_SYNCA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_EN", REG_MMIO, 0x1966, &mmDC_GPIO_SYNCA_EN[0], sizeof(mmDC_GPIO_SYNCA_EN)/sizeof(mmDC_GPIO_SYNCA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_Y", REG_MMIO, 0x1967, &mmDC_GPIO_SYNCA_Y[0], sizeof(mmDC_GPIO_SYNCA_Y)/sizeof(mmDC_GPIO_SYNCA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_MASK", REG_MMIO, 0x1968, &mmDC_GPIO_GENLK_MASK[0], sizeof(mmDC_GPIO_GENLK_MASK)/sizeof(mmDC_GPIO_GENLK_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_A", REG_MMIO, 0x1969, &mmDC_GPIO_GENLK_A[0], sizeof(mmDC_GPIO_GENLK_A)/sizeof(mmDC_GPIO_GENLK_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_EN", REG_MMIO, 0x196A, &mmDC_GPIO_GENLK_EN[0], sizeof(mmDC_GPIO_GENLK_EN)/sizeof(mmDC_GPIO_GENLK_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_Y", REG_MMIO, 0x196B, &mmDC_GPIO_GENLK_Y[0], sizeof(mmDC_GPIO_GENLK_Y)/sizeof(mmDC_GPIO_GENLK_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_MASK", REG_MMIO, 0x196C, &mmDC_GPIO_HPD_MASK[0], sizeof(mmDC_GPIO_HPD_MASK)/sizeof(mmDC_GPIO_HPD_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_A", REG_MMIO, 0x196D, &mmDC_GPIO_HPD_A[0], sizeof(mmDC_GPIO_HPD_A)/sizeof(mmDC_GPIO_HPD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_EN", REG_MMIO, 0x196E, &mmDC_GPIO_HPD_EN[0], sizeof(mmDC_GPIO_HPD_EN)/sizeof(mmDC_GPIO_HPD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_Y", REG_MMIO, 0x196F, &mmDC_GPIO_HPD_Y[0], sizeof(mmDC_GPIO_HPD_Y)/sizeof(mmDC_GPIO_HPD_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_MASK", REG_MMIO, 0x1970, &mmDC_GPIO_DDCVGA_MASK[0], sizeof(mmDC_GPIO_DDCVGA_MASK)/sizeof(mmDC_GPIO_DDCVGA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_A", REG_MMIO, 0x1971, &mmDC_GPIO_DDCVGA_A[0], sizeof(mmDC_GPIO_DDCVGA_A)/sizeof(mmDC_GPIO_DDCVGA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_EN", REG_MMIO, 0x1972, &mmDC_GPIO_DDCVGA_EN[0], sizeof(mmDC_GPIO_DDCVGA_EN)/sizeof(mmDC_GPIO_DDCVGA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_Y", REG_MMIO, 0x1973, &mmDC_GPIO_DDCVGA_Y[0], sizeof(mmDC_GPIO_DDCVGA_Y)/sizeof(mmDC_GPIO_DDCVGA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_MASK", REG_MMIO, 0x1974, &mmDC_GPIO_I2CPAD_MASK[0], sizeof(mmDC_GPIO_I2CPAD_MASK)/sizeof(mmDC_GPIO_I2CPAD_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_A", REG_MMIO, 0x1975, &mmDC_GPIO_I2CPAD_A[0], sizeof(mmDC_GPIO_I2CPAD_A)/sizeof(mmDC_GPIO_I2CPAD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_EN", REG_MMIO, 0x1976, &mmDC_GPIO_I2CPAD_EN[0], sizeof(mmDC_GPIO_I2CPAD_EN)/sizeof(mmDC_GPIO_I2CPAD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_Y", REG_MMIO, 0x1977, &mmDC_GPIO_I2CPAD_Y[0], sizeof(mmDC_GPIO_I2CPAD_Y)/sizeof(mmDC_GPIO_I2CPAD_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_1", REG_MMIO, 0x1978, &mmDC_GPIO_PAD_STRENGTH_1[0], sizeof(mmDC_GPIO_PAD_STRENGTH_1)/sizeof(mmDC_GPIO_PAD_STRENGTH_1[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_2", REG_MMIO, 0x1979, &mmDC_GPIO_PAD_STRENGTH_2[0], sizeof(mmDC_GPIO_PAD_STRENGTH_2)/sizeof(mmDC_GPIO_PAD_STRENGTH_2[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_STRENGTH", REG_MMIO, 0x197A, &mmDC_GPIO_I2CPAD_STRENGTH[0], sizeof(mmDC_GPIO_I2CPAD_STRENGTH)/sizeof(mmDC_GPIO_I2CPAD_STRENGTH[0]), 0, 0 },
+	{ "mmDVO_STRENGTH_CONTROL", REG_MMIO, 0x197B, &mmDVO_STRENGTH_CONTROL[0], sizeof(mmDVO_STRENGTH_CONTROL)/sizeof(mmDVO_STRENGTH_CONTROL[0]), 0, 0 },
+	{ "mmDVO_VREF_CONTROL", REG_MMIO, 0x197C, &mmDVO_VREF_CONTROL[0], sizeof(mmDVO_VREF_CONTROL)/sizeof(mmDVO_VREF_CONTROL[0]), 0, 0 },
+	{ "mmDVO_SKEW_ADJUST", REG_MMIO, 0x197D, &mmDVO_SKEW_ADJUST[0], sizeof(mmDVO_SKEW_ADJUST)/sizeof(mmDVO_SKEW_ADJUST[0]), 0, 0 },
+	{ "mmPHY_AUX_CNTL", REG_MMIO, 0x197F, &mmPHY_AUX_CNTL[0], sizeof(mmPHY_AUX_CNTL)/sizeof(mmPHY_AUX_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1", REG_MMIO, 0x1980, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2", REG_MMIO, 0x1981, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3", REG_MMIO, 0x1982, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4", REG_MMIO, 0x1983, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL", REG_MMIO, 0x1984, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV", REG_MMIO, 0x1985, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x1986, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x1987, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x1988, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x1989, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x198A, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x198B, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x198C, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL", REG_MMIO, 0x198D, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x198E, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1", REG_MMIO, 0x1990, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2", REG_MMIO, 0x1991, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3", REG_MMIO, 0x1992, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4", REG_MMIO, 0x1993, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL", REG_MMIO, 0x1994, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV", REG_MMIO, 0x1995, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x1996, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x1997, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x1998, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x1999, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x199A, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x199B, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x199C, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL", REG_MMIO, 0x199D, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x199E, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1", REG_MMIO, 0x19A0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2", REG_MMIO, 0x19A1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3", REG_MMIO, 0x19A2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4", REG_MMIO, 0x19A3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL", REG_MMIO, 0x19A4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV", REG_MMIO, 0x19A5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x19A6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x19A7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x19A8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x19A9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x19AA, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x19AB, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x19AC, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL", REG_MMIO, 0x19AD, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x19AE, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1", REG_MMIO, 0x19B0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2", REG_MMIO, 0x19B1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3", REG_MMIO, 0x19B2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4", REG_MMIO, 0x19B3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL", REG_MMIO, 0x19B4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV", REG_MMIO, 0x19B5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x19B6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x19B7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x19B8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x19B9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x19BA, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x19BB, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x19BC, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL", REG_MMIO, 0x19BD, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x19BE, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1", REG_MMIO, 0x19C0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2", REG_MMIO, 0x19C1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3", REG_MMIO, 0x19C2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4", REG_MMIO, 0x19C3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL", REG_MMIO, 0x19C4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV", REG_MMIO, 0x19C5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x19C6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x19C7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x19C8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x19C9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x19CA, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x19CB, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x19CC, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL", REG_MMIO, 0x19CD, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x19CE, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1", REG_MMIO, 0x19D0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2", REG_MMIO, 0x19D1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3", REG_MMIO, 0x19D2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4", REG_MMIO, 0x19D3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL", REG_MMIO, 0x19D4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV", REG_MMIO, 0x19D5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x19D6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x19D7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x19D8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x19D9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x19DA, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x19DB, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x19DC, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL", REG_MMIO, 0x19DD, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x19DE, NULL, 0, 0, 0 },
+	{ "mmDAC_ENABLE", REG_MMIO, 0x19E4, &mmDAC_ENABLE[0], sizeof(mmDAC_ENABLE)/sizeof(mmDAC_ENABLE[0]), 0, 0 },
+	{ "mmDAC_SOURCE_SELECT", REG_MMIO, 0x19E5, &mmDAC_SOURCE_SELECT[0], sizeof(mmDAC_SOURCE_SELECT)/sizeof(mmDAC_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDAC_CRC_EN", REG_MMIO, 0x19E6, &mmDAC_CRC_EN[0], sizeof(mmDAC_CRC_EN)/sizeof(mmDAC_CRC_EN[0]), 0, 0 },
+	{ "mmDAC_CRC_CONTROL", REG_MMIO, 0x19E7, &mmDAC_CRC_CONTROL[0], sizeof(mmDAC_CRC_CONTROL)/sizeof(mmDAC_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB_MASK", REG_MMIO, 0x19E8, &mmDAC_CRC_SIG_RGB_MASK[0], sizeof(mmDAC_CRC_SIG_RGB_MASK)/sizeof(mmDAC_CRC_SIG_RGB_MASK[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL_MASK", REG_MMIO, 0x19E9, &mmDAC_CRC_SIG_CONTROL_MASK[0], sizeof(mmDAC_CRC_SIG_CONTROL_MASK)/sizeof(mmDAC_CRC_SIG_CONTROL_MASK[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB", REG_MMIO, 0x19EA, &mmDAC_CRC_SIG_RGB[0], sizeof(mmDAC_CRC_SIG_RGB)/sizeof(mmDAC_CRC_SIG_RGB[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL", REG_MMIO, 0x19EB, &mmDAC_CRC_SIG_CONTROL[0], sizeof(mmDAC_CRC_SIG_CONTROL)/sizeof(mmDAC_CRC_SIG_CONTROL[0]), 0, 0 },
+	{ "mmDAC_SYNC_TRISTATE_CONTROL", REG_MMIO, 0x19EC, &mmDAC_SYNC_TRISTATE_CONTROL[0], sizeof(mmDAC_SYNC_TRISTATE_CONTROL)/sizeof(mmDAC_SYNC_TRISTATE_CONTROL[0]), 0, 0 },
+	{ "mmDAC_STEREOSYNC_SELECT", REG_MMIO, 0x19ED, &mmDAC_STEREOSYNC_SELECT[0], sizeof(mmDAC_STEREOSYNC_SELECT)/sizeof(mmDAC_STEREOSYNC_SELECT[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL", REG_MMIO, 0x19EE, &mmDAC_AUTODETECT_CONTROL[0], sizeof(mmDAC_AUTODETECT_CONTROL)/sizeof(mmDAC_AUTODETECT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL2", REG_MMIO, 0x19EF, &mmDAC_AUTODETECT_CONTROL2[0], sizeof(mmDAC_AUTODETECT_CONTROL2)/sizeof(mmDAC_AUTODETECT_CONTROL2[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL3", REG_MMIO, 0x19F0, &mmDAC_AUTODETECT_CONTROL3[0], sizeof(mmDAC_AUTODETECT_CONTROL3)/sizeof(mmDAC_AUTODETECT_CONTROL3[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_STATUS", REG_MMIO, 0x19F1, &mmDAC_AUTODETECT_STATUS[0], sizeof(mmDAC_AUTODETECT_STATUS)/sizeof(mmDAC_AUTODETECT_STATUS[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_INT_CONTROL", REG_MMIO, 0x19F2, &mmDAC_AUTODETECT_INT_CONTROL[0], sizeof(mmDAC_AUTODETECT_INT_CONTROL)/sizeof(mmDAC_AUTODETECT_INT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_FORCE_OUTPUT_CNTL", REG_MMIO, 0x19F3, &mmDAC_FORCE_OUTPUT_CNTL[0], sizeof(mmDAC_FORCE_OUTPUT_CNTL)/sizeof(mmDAC_FORCE_OUTPUT_CNTL[0]), 0, 0 },
+	{ "mmDAC_FORCE_DATA", REG_MMIO, 0x19F4, &mmDAC_FORCE_DATA[0], sizeof(mmDAC_FORCE_DATA)/sizeof(mmDAC_FORCE_DATA[0]), 0, 0 },
+	{ "mmDAC_POWERDOWN", REG_MMIO, 0x19F5, &mmDAC_POWERDOWN[0], sizeof(mmDAC_POWERDOWN)/sizeof(mmDAC_POWERDOWN[0]), 0, 0 },
+	{ "mmDAC_CONTROL", REG_MMIO, 0x19F6, &mmDAC_CONTROL[0], sizeof(mmDAC_CONTROL)/sizeof(mmDAC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_ENABLE", REG_MMIO, 0x19F7, &mmDAC_COMPARATOR_ENABLE[0], sizeof(mmDAC_COMPARATOR_ENABLE)/sizeof(mmDAC_COMPARATOR_ENABLE[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_OUTPUT", REG_MMIO, 0x19F8, &mmDAC_COMPARATOR_OUTPUT[0], sizeof(mmDAC_COMPARATOR_OUTPUT)/sizeof(mmDAC_COMPARATOR_OUTPUT[0]), 0, 0 },
+	{ "mmDAC_PWR_CNTL", REG_MMIO, 0x19F9, &mmDAC_PWR_CNTL[0], sizeof(mmDAC_PWR_CNTL)/sizeof(mmDAC_PWR_CNTL[0]), 0, 0 },
+	{ "mmDAC_DFT_CONFIG", REG_MMIO, 0x19FA, &mmDAC_DFT_CONFIG[0], sizeof(mmDAC_DFT_CONFIG)/sizeof(mmDAC_DFT_CONFIG[0]), 0, 0 },
+	{ "mmDAC_FIFO_STATUS", REG_MMIO, 0x19FB, &mmDAC_FIFO_STATUS[0], sizeof(mmDAC_FIFO_STATUS)/sizeof(mmDAC_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED0", REG_MMIO, 0x19FC, &mmDAC_MACRO_CNTL_RESERVED0[0], sizeof(mmDAC_MACRO_CNTL_RESERVED0)/sizeof(mmDAC_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmBPHYC_DAC_MACRO_CNTL", REG_MMIO, 0x19FD, &mmBPHYC_DAC_MACRO_CNTL[0], sizeof(mmBPHYC_DAC_MACRO_CNTL)/sizeof(mmBPHYC_DAC_MACRO_CNTL[0]), 0, 0 },
+	{ "mmBPHYC_DAC_AUTO_CALIB_CONTROL", REG_MMIO, 0x19FE, &mmBPHYC_DAC_AUTO_CALIB_CONTROL[0], sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL)/sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED3", REG_MMIO, 0x19FF, &mmDAC_MACRO_CNTL_RESERVED3[0], sizeof(mmDAC_MACRO_CNTL_RESERVED3)/sizeof(mmDAC_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmDCP0_GRPH_ENABLE", REG_MMIO, 0x1A00, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_CONTROL", REG_MMIO, 0x1A01, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1A02, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_SWAP_CNTL", REG_MMIO, 0x1A03, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1A04, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1A05, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_PITCH", REG_MMIO, 0x1A06, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1A07, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1A08, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1A09, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1A0A, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_X_START", REG_MMIO, 0x1A0B, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_Y_START", REG_MMIO, 0x1A0C, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_X_END", REG_MMIO, 0x1A0D, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_Y_END", REG_MMIO, 0x1A0E, NULL, 0, 0, 0 },
+	{ "mmDCP0_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1A10, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_UPDATE", REG_MMIO, 0x1A11, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_CONTROL", REG_MMIO, 0x1A12, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1A13, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_CONTROL", REG_MMIO, 0x1A14, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_STATUS", REG_MMIO, 0x1A15, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1A16, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1A17, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1A18, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1A19, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1A1A, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1A1B, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_ENABLE", REG_MMIO, 0x1A1C, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_CONTROL1", REG_MMIO, 0x1A1D, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_CONTROL2", REG_MMIO, 0x1A1E, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SWAP_CNTL", REG_MMIO, 0x1A1F, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS", REG_MMIO, 0x1A20, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_PITCH", REG_MMIO, 0x1A21, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1A22, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x1A23, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1A24, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_START", REG_MMIO, 0x1A25, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_END", REG_MMIO, 0x1A26, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_UPDATE", REG_MMIO, 0x1A27, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1A28, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_DFQ_CONTROL", REG_MMIO, 0x1A29, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_DFQ_STATUS", REG_MMIO, 0x1A2A, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1A2B, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1A2C, NULL, 0, 0, 0 },
+	{ "mmDCP0_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1A2D, NULL, 0, 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1A2E, NULL, 0, 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1A2F, NULL, 0, 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1A30, NULL, 0, 0, 0 },
+	{ "mmDCP0_PRESCALE_OVL_CONTROL", REG_MMIO, 0x1A31, NULL, 0, 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1A32, NULL, 0, 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1A33, NULL, 0, 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1A34, NULL, 0, 0, 0 },
+	{ "mmDCP0_INPUT_CSC_CONTROL", REG_MMIO, 0x1A35, NULL, 0, 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C11_C12", REG_MMIO, 0x1A36, NULL, 0, 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C13_C14", REG_MMIO, 0x1A37, NULL, 0, 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C21_C22", REG_MMIO, 0x1A38, NULL, 0, 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C23_C24", REG_MMIO, 0x1A39, NULL, 0, 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C31_C32", REG_MMIO, 0x1A3A, NULL, 0, 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C33_C34", REG_MMIO, 0x1A3B, NULL, 0, 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1A3C, NULL, 0, 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1A3D, NULL, 0, 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1A3E, NULL, 0, 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1A3F, NULL, 0, 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1A40, NULL, 0, 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1A41, NULL, 0, 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1A42, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1A43, &mmCOMM_MATRIXA_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXA_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXA_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1A44, &mmCOMM_MATRIXA_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXA_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXA_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1A45, &mmCOMM_MATRIXA_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXA_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXA_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1A46, &mmCOMM_MATRIXA_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXA_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXA_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1A47, &mmCOMM_MATRIXA_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXA_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXA_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1A48, &mmCOMM_MATRIXA_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXA_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXA_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1A49, &mmCOMM_MATRIXB_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXB_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXB_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1A4A, &mmCOMM_MATRIXB_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXB_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXB_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1A4B, &mmCOMM_MATRIXB_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXB_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXB_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1A4C, &mmCOMM_MATRIXB_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXB_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXB_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1A4D, &mmCOMM_MATRIXB_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXB_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXB_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1A4E, &mmCOMM_MATRIXB_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXB_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXB_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DENORM_CONTROL", REG_MMIO, 0x1A50, NULL, 0, 0, 0 },
+	{ "mmDCP0_OUT_ROUND_CONTROL", REG_MMIO, 0x1A51, NULL, 0, 0, 0 },
+	{ "mmDCP0_KEY_CONTROL", REG_MMIO, 0x1A53, NULL, 0, 0, 0 },
+	{ "mmDCP0_KEY_RANGE_ALPHA", REG_MMIO, 0x1A54, NULL, 0, 0, 0 },
+	{ "mmDCP0_KEY_RANGE_RED", REG_MMIO, 0x1A55, NULL, 0, 0, 0 },
+	{ "mmDCP0_KEY_RANGE_GREEN", REG_MMIO, 0x1A56, NULL, 0, 0, 0 },
+	{ "mmDCP0_KEY_RANGE_BLUE", REG_MMIO, 0x1A57, NULL, 0, 0, 0 },
+	{ "mmDCP0_DEGAMMA_CONTROL", REG_MMIO, 0x1A58, NULL, 0, 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1A59, NULL, 0, 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1A5A, NULL, 0, 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1A5B, NULL, 0, 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1A5C, NULL, 0, 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1A5D, NULL, 0, 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1A5E, NULL, 0, 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1A5F, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1A60, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_RANDOM_SEEDS", REG_MMIO, 0x1A61, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1A65, NULL, 0, 0, 0 },
+	{ "mmCUR_CONTROL", REG_MMIO, 0x1A66, &mmCUR_CONTROL[0], sizeof(mmCUR_CONTROL)/sizeof(mmCUR_CONTROL[0]), 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS", REG_MMIO, 0x1A67, &mmCUR_SURFACE_ADDRESS[0], sizeof(mmCUR_SURFACE_ADDRESS)/sizeof(mmCUR_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmCUR_SIZE", REG_MMIO, 0x1A68, &mmCUR_SIZE[0], sizeof(mmCUR_SIZE)/sizeof(mmCUR_SIZE[0]), 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1A69, &mmCUR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCUR_SURFACE_ADDRESS_HIGH)/sizeof(mmCUR_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmCUR_POSITION", REG_MMIO, 0x1A6A, &mmCUR_POSITION[0], sizeof(mmCUR_POSITION)/sizeof(mmCUR_POSITION[0]), 0, 0 },
+	{ "mmCUR_HOT_SPOT", REG_MMIO, 0x1A6B, &mmCUR_HOT_SPOT[0], sizeof(mmCUR_HOT_SPOT)/sizeof(mmCUR_HOT_SPOT[0]), 0, 0 },
+	{ "mmCUR_COLOR1", REG_MMIO, 0x1A6C, &mmCUR_COLOR1[0], sizeof(mmCUR_COLOR1)/sizeof(mmCUR_COLOR1[0]), 0, 0 },
+	{ "mmCUR_COLOR2", REG_MMIO, 0x1A6D, &mmCUR_COLOR2[0], sizeof(mmCUR_COLOR2)/sizeof(mmCUR_COLOR2[0]), 0, 0 },
+	{ "mmCUR_UPDATE", REG_MMIO, 0x1A6E, &mmCUR_UPDATE[0], sizeof(mmCUR_UPDATE)/sizeof(mmCUR_UPDATE[0]), 0, 0 },
+	{ "mmDC_LUT_RW_MODE", REG_MMIO, 0x1A78, &mmDC_LUT_RW_MODE[0], sizeof(mmDC_LUT_RW_MODE)/sizeof(mmDC_LUT_RW_MODE[0]), 0, 0 },
+	{ "mmDC_LUT_RW_INDEX", REG_MMIO, 0x1A79, &mmDC_LUT_RW_INDEX[0], sizeof(mmDC_LUT_RW_INDEX)/sizeof(mmDC_LUT_RW_INDEX[0]), 0, 0 },
+	{ "mmDC_LUT_SEQ_COLOR", REG_MMIO, 0x1A7A, &mmDC_LUT_SEQ_COLOR[0], sizeof(mmDC_LUT_SEQ_COLOR)/sizeof(mmDC_LUT_SEQ_COLOR[0]), 0, 0 },
+	{ "mmDC_LUT_PWL_DATA", REG_MMIO, 0x1A7B, &mmDC_LUT_PWL_DATA[0], sizeof(mmDC_LUT_PWL_DATA)/sizeof(mmDC_LUT_PWL_DATA[0]), 0, 0 },
+	{ "mmDC_LUT_30_COLOR", REG_MMIO, 0x1A7C, &mmDC_LUT_30_COLOR[0], sizeof(mmDC_LUT_30_COLOR)/sizeof(mmDC_LUT_30_COLOR[0]), 0, 0 },
+	{ "mmDC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1A7D, &mmDC_LUT_VGA_ACCESS_ENABLE[0], sizeof(mmDC_LUT_VGA_ACCESS_ENABLE)/sizeof(mmDC_LUT_VGA_ACCESS_ENABLE[0]), 0, 0 },
+	{ "mmDC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1A7E, &mmDC_LUT_WRITE_EN_MASK[0], sizeof(mmDC_LUT_WRITE_EN_MASK)/sizeof(mmDC_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDC_LUT_AUTOFILL", REG_MMIO, 0x1A7F, &mmDC_LUT_AUTOFILL[0], sizeof(mmDC_LUT_AUTOFILL)/sizeof(mmDC_LUT_AUTOFILL[0]), 0, 0 },
+	{ "mmDC_LUT_CONTROL", REG_MMIO, 0x1A80, &mmDC_LUT_CONTROL[0], sizeof(mmDC_LUT_CONTROL)/sizeof(mmDC_LUT_CONTROL[0]), 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1A81, &mmDC_LUT_BLACK_OFFSET_BLUE[0], sizeof(mmDC_LUT_BLACK_OFFSET_BLUE)/sizeof(mmDC_LUT_BLACK_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1A82, &mmDC_LUT_BLACK_OFFSET_GREEN[0], sizeof(mmDC_LUT_BLACK_OFFSET_GREEN)/sizeof(mmDC_LUT_BLACK_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1A83, &mmDC_LUT_BLACK_OFFSET_RED[0], sizeof(mmDC_LUT_BLACK_OFFSET_RED)/sizeof(mmDC_LUT_BLACK_OFFSET_RED[0]), 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1A84, &mmDC_LUT_WHITE_OFFSET_BLUE[0], sizeof(mmDC_LUT_WHITE_OFFSET_BLUE)/sizeof(mmDC_LUT_WHITE_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1A85, &mmDC_LUT_WHITE_OFFSET_GREEN[0], sizeof(mmDC_LUT_WHITE_OFFSET_GREEN)/sizeof(mmDC_LUT_WHITE_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1A86, &mmDC_LUT_WHITE_OFFSET_RED[0], sizeof(mmDC_LUT_WHITE_OFFSET_RED)/sizeof(mmDC_LUT_WHITE_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CONTROL", REG_MMIO, 0x1A87, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_CRC_MASK", REG_MMIO, 0x1A88, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_CRC_CURRENT", REG_MMIO, 0x1A89, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_CRC_LAST", REG_MMIO, 0x1A8B, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_DEBUG", REG_MMIO, 0x1A8D, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_GSL_CONTROL", REG_MMIO, 0x1A90, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1A91, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1A92, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x1A93, NULL, 0, 0, 0 },
+	{ "mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1A94, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1A95, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1A96, NULL, 0, 0, 0 },
+	{ "mmDCP0_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1A97, NULL, 0, 0, 0 },
+	{ "mmDCP0_DCP_DEBUG2", REG_MMIO, 0x1A98, NULL, 0, 0, 0 },
+	{ "mmCUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1A99, &mmCUR_REQUEST_FILTER_CNTL[0], sizeof(mmCUR_REQUEST_FILTER_CNTL)/sizeof(mmCUR_REQUEST_FILTER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CONTROL", REG_MMIO, 0x1AA0, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_INDEX", REG_MMIO, 0x1AA1, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_DATA", REG_MMIO, 0x1AA2, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1AA3, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1AA4, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1AA5, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1AA6, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1AA7, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1AA8, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1AA9, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1AAA, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1AAB, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1AAC, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1AAD, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1AAE, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1AAF, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1AB0, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1AB1, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1AB2, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1AB3, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1AB4, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1AB5, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1AB6, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1AB7, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1AB8, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1AB9, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1ABA, NULL, 0, 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1ABB, NULL, 0, 0, 0 },
+	{ "mmDATA_FORMAT", REG_MMIO, 0x1AC0, NULL, 0, 0, 0 },
+	{ "mmDESKTOP_HEIGHT", REG_MMIO, 0x1AC1, NULL, 0, 0, 0 },
+	{ "mmDC_LB_MEMORY_SPLIT", REG_MMIO, 0x1AC3, NULL, 0, 0, 0 },
+	{ "mmPRIORITY_A_CNT", REG_MMIO, 0x1AC6, NULL, 0, 0, 0 },
+	{ "mmPRIORITY_B_CNT", REG_MMIO, 0x1AC7, NULL, 0, 0, 0 },
+	{ "mmLB0_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1AC8, NULL, 0, 0, 0 },
+	{ "mmLB0_LB_DEBUG2", REG_MMIO, 0x1AC9, NULL, 0, 0, 0 },
+	{ "mmLB0_LB_SYNC_RESET_SEL", REG_MMIO, 0x1ACA, NULL, 0, 0, 0 },
+	{ "mmINT_MASK", REG_MMIO, 0x1AD0, NULL, 0, 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1AD8, NULL, 0, 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1AD9, NULL, 0, 0, 0 },
+	{ "mmLB0_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ADA, NULL, 0, 0, 0 },
+	{ "mmDC_MVP_LB_CONTROL", REG_MMIO, 0x1ADB, &mmDC_MVP_LB_CONTROL[0], sizeof(mmDC_MVP_LB_CONTROL)/sizeof(mmDC_MVP_LB_CONTROL[0]), 0, 0 },
+	{ "mmVLINE_STATUS", REG_MMIO, 0x1AEE, NULL, 0, 0, 0 },
+	{ "mmVBLANK_STATUS", REG_MMIO, 0x1AEF, NULL, 0, 0, 0 },
+	{ "mmLB0_LB_DEBUG", REG_MMIO, 0x1AFC, NULL, 0, 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1AFE, NULL, 0, 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1AFF, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1B30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1B31, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL3", REG_MMIO, 0x1B32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1B33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1B34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1B35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1B36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1B37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1B38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1B39, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1B40, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1B41, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_TAP_CONTROL", REG_MMIO, 0x1B43, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_CONTROL", REG_MMIO, 0x1B44, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_BYPASS_CONTROL", REG_MMIO, 0x1B45, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1B46, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1B47, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1B4A, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1B4B, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1B4E, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1B4F, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1B50, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_UPDATE", REG_MMIO, 0x1B51, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1B53, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_ALU_CONTROL", REG_MMIO, 0x1B54, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1B55, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1B57, NULL, 0, 0, 0 },
+	{ "mmSCL0_VIEWPORT_START", REG_MMIO, 0x1B5C, NULL, 0, 0, 0 },
+	{ "mmSCL0_VIEWPORT_SIZE", REG_MMIO, 0x1B5D, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1B5E, &mmEXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmEXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmEXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 },
+	{ "mmEXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1B5F, &mmEXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmEXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmEXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1B60, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1B61, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1B62, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1B63, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_DEBUG2", REG_MMIO, 0x1B69, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_DEBUG", REG_MMIO, 0x1B6A, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1B6B, NULL, 0, 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1B6C, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1B78, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1B79, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_WINDOW", REG_MMIO, 0x1B7A, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_CONTROL", REG_MMIO, 0x1B7B, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1B7C, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1B7D, NULL, 0, 0, 0 },
+	{ "mmCRTC0_DCFE_DBG_SEL", REG_MMIO, 0x1B7E, NULL, 0, 0, 0 },
+	{ "mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x1B7F, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_H_TOTAL", REG_MMIO, 0x1B80, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_START_END", REG_MMIO, 0x1B81, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A", REG_MMIO, 0x1B82, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1B83, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B", REG_MMIO, 0x1B84, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1B85, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_VBI_END", REG_MMIO, 0x1B86, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL", REG_MMIO, 0x1B87, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1B88, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1B89, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1B8A, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1B8B, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1B8C, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_BLANK_START_END", REG_MMIO, 0x1B8D, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A", REG_MMIO, 0x1B8E, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1B8F, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B", REG_MMIO, 0x1B90, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1B91, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1B92, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1B93, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_CNTL", REG_MMIO, 0x1B94, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1B95, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_CNTL", REG_MMIO, 0x1B96, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1B97, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1B98, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_FLOW_CONTROL", REG_MMIO, 0x1B99, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1B9B, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_CONTROL", REG_MMIO, 0x1B9C, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_CONTROL", REG_MMIO, 0x1B9D, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1B9E, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1B9F, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1BA0, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1BA1, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR", REG_MMIO, 0x1BA2, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS", REG_MMIO, 0x1BA3, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_POSITION", REG_MMIO, 0x1BA4, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1BA5, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1BA6, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1BA7, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1BA8, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_CONTROL", REG_MMIO, 0x1BA9, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_RESET", REG_MMIO, 0x1BAA, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1BAB, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1BAC, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_STATUS", REG_MMIO, 0x1BAD, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_CONTROL", REG_MMIO, 0x1BAE, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1BAF, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1BB0, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1BB1, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1BB2, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1BB3, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1BB4, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_UPDATE_LOCK", REG_MMIO, 0x1BB5, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1BB6, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1BB7, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1BBA, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1BBB, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1BBC, NULL, 0, 0, 0 },
+	{ "mmCRTC0_MASTER_UPDATE_LOCK", REG_MMIO, 0x1BBD, NULL, 0, 0, 0 },
+	{ "mmCRTC0_MASTER_UPDATE_MODE", REG_MMIO, 0x1BBE, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1BBF, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1BC0, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_STATUS", REG_MMIO, 0x1BC1, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_EN", REG_MMIO, 0x1BC2, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1BC3, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1BC4, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1BC6, NULL, 0, 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1BC7, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1BEB, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1BEC, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1BED, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_CONTROL", REG_MMIO, 0x1BEE, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1BEF, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_FORCE_DATA_0_1", REG_MMIO, 0x1BF0, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_FORCE_DATA_2_3", REG_MMIO, 0x1BF1, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1BF2, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1BF3, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1BF4, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1BF5, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1BF6, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1BF7, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1BF8, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_CNTL", REG_MMIO, 0x1BF9, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_CRC_CNTL", REG_MMIO, 0x1BFA, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1BFB, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1BFC, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1BFD, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1BFE, NULL, 0, 0, 0 },
+	{ "mmFMT0_FMT_DEBUG_CNTL", REG_MMIO, 0x1BFF, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_FE_CNTL", REG_MMIO, 0x1C00, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x1C01, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x1C02, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_CLOCK_PATTERN", REG_MMIO, 0x1C03, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_TEST_PATTERN", REG_MMIO, 0x1C04, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x1C05, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x1C08, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x1C09, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_FIFO_STATUS", REG_MMIO, 0x1C0A, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_CONTROL", REG_MMIO, 0x1C0C, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_STATUS", REG_MMIO, 0x1C0D, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1C0E, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x1C0F, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x1C10, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x1C11, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x1C12, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x1C13, NULL, 0, 0, 0 },
+	{ "mmAFMT_INTERRUPT_STATUS", REG_MMIO, 0x1C14, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_GC", REG_MMIO, 0x1C16, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x1C17, &mmAFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 },
+	{ "mmAFMT_ISRC1_0", REG_MMIO, 0x1C18, &mmAFMT_ISRC1_0[0], sizeof(mmAFMT_ISRC1_0)/sizeof(mmAFMT_ISRC1_0[0]), 0, 0 },
+	{ "mmAFMT_ISRC1_1", REG_MMIO, 0x1C19, &mmAFMT_ISRC1_1[0], sizeof(mmAFMT_ISRC1_1)/sizeof(mmAFMT_ISRC1_1[0]), 0, 0 },
+	{ "mmAFMT_ISRC1_2", REG_MMIO, 0x1C1A, &mmAFMT_ISRC1_2[0], sizeof(mmAFMT_ISRC1_2)/sizeof(mmAFMT_ISRC1_2[0]), 0, 0 },
+	{ "mmAFMT_ISRC1_3", REG_MMIO, 0x1C1B, &mmAFMT_ISRC1_3[0], sizeof(mmAFMT_ISRC1_3)/sizeof(mmAFMT_ISRC1_3[0]), 0, 0 },
+	{ "mmAFMT_ISRC1_4", REG_MMIO, 0x1C1C, &mmAFMT_ISRC1_4[0], sizeof(mmAFMT_ISRC1_4)/sizeof(mmAFMT_ISRC1_4[0]), 0, 0 },
+	{ "mmAFMT_ISRC2_0", REG_MMIO, 0x1C1D, &mmAFMT_ISRC2_0[0], sizeof(mmAFMT_ISRC2_0)/sizeof(mmAFMT_ISRC2_0[0]), 0, 0 },
+	{ "mmAFMT_ISRC2_1", REG_MMIO, 0x1C1E, &mmAFMT_ISRC2_1[0], sizeof(mmAFMT_ISRC2_1)/sizeof(mmAFMT_ISRC2_1[0]), 0, 0 },
+	{ "mmAFMT_ISRC2_2", REG_MMIO, 0x1C1F, &mmAFMT_ISRC2_2[0], sizeof(mmAFMT_ISRC2_2)/sizeof(mmAFMT_ISRC2_2[0]), 0, 0 },
+	{ "mmAFMT_ISRC2_3", REG_MMIO, 0x1C20, &mmAFMT_ISRC2_3[0], sizeof(mmAFMT_ISRC2_3)/sizeof(mmAFMT_ISRC2_3[0]), 0, 0 },
+	{ "mmAFMT_AVI_INFO0", REG_MMIO, 0x1C21, &mmAFMT_AVI_INFO0[0], sizeof(mmAFMT_AVI_INFO0)/sizeof(mmAFMT_AVI_INFO0[0]), 0, 0 },
+	{ "mmAFMT_AVI_INFO1", REG_MMIO, 0x1C22, &mmAFMT_AVI_INFO1[0], sizeof(mmAFMT_AVI_INFO1)/sizeof(mmAFMT_AVI_INFO1[0]), 0, 0 },
+	{ "mmAFMT_AVI_INFO2", REG_MMIO, 0x1C23, &mmAFMT_AVI_INFO2[0], sizeof(mmAFMT_AVI_INFO2)/sizeof(mmAFMT_AVI_INFO2[0]), 0, 0 },
+	{ "mmAFMT_AVI_INFO3", REG_MMIO, 0x1C24, &mmAFMT_AVI_INFO3[0], sizeof(mmAFMT_AVI_INFO3)/sizeof(mmAFMT_AVI_INFO3[0]), 0, 0 },
+	{ "mmAFMT_MPEG_INFO0", REG_MMIO, 0x1C25, &mmAFMT_MPEG_INFO0[0], sizeof(mmAFMT_MPEG_INFO0)/sizeof(mmAFMT_MPEG_INFO0[0]), 0, 0 },
+	{ "mmAFMT_MPEG_INFO1", REG_MMIO, 0x1C26, &mmAFMT_MPEG_INFO1[0], sizeof(mmAFMT_MPEG_INFO1)/sizeof(mmAFMT_MPEG_INFO1[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_HDR", REG_MMIO, 0x1C27, &mmAFMT_GENERIC_HDR[0], sizeof(mmAFMT_GENERIC_HDR)/sizeof(mmAFMT_GENERIC_HDR[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_0", REG_MMIO, 0x1C28, &mmAFMT_GENERIC_0[0], sizeof(mmAFMT_GENERIC_0)/sizeof(mmAFMT_GENERIC_0[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_1", REG_MMIO, 0x1C29, &mmAFMT_GENERIC_1[0], sizeof(mmAFMT_GENERIC_1)/sizeof(mmAFMT_GENERIC_1[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_2", REG_MMIO, 0x1C2A, &mmAFMT_GENERIC_2[0], sizeof(mmAFMT_GENERIC_2)/sizeof(mmAFMT_GENERIC_2[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_3", REG_MMIO, 0x1C2B, &mmAFMT_GENERIC_3[0], sizeof(mmAFMT_GENERIC_3)/sizeof(mmAFMT_GENERIC_3[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_4", REG_MMIO, 0x1C2C, &mmAFMT_GENERIC_4[0], sizeof(mmAFMT_GENERIC_4)/sizeof(mmAFMT_GENERIC_4[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_5", REG_MMIO, 0x1C2D, &mmAFMT_GENERIC_5[0], sizeof(mmAFMT_GENERIC_5)/sizeof(mmAFMT_GENERIC_5[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_6", REG_MMIO, 0x1C2E, &mmAFMT_GENERIC_6[0], sizeof(mmAFMT_GENERIC_6)/sizeof(mmAFMT_GENERIC_6[0]), 0, 0 },
+	{ "mmAFMT_GENERIC_7", REG_MMIO, 0x1C2F, &mmAFMT_GENERIC_7[0], sizeof(mmAFMT_GENERIC_7)/sizeof(mmAFMT_GENERIC_7[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x1C30, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_0", REG_MMIO, 0x1C37, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_1", REG_MMIO, 0x1C38, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_0", REG_MMIO, 0x1C39, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_1", REG_MMIO, 0x1C3A, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_0", REG_MMIO, 0x1C3B, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_1", REG_MMIO, 0x1C3C, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_0", REG_MMIO, 0x1C3D, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_1", REG_MMIO, 0x1C3E, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO0", REG_MMIO, 0x1C3F, &mmAFMT_AUDIO_INFO0[0], sizeof(mmAFMT_AUDIO_INFO0)/sizeof(mmAFMT_AUDIO_INFO0[0]), 0, 0 },
+	{ "mmAFMT_AUDIO_INFO1", REG_MMIO, 0x1C40, &mmAFMT_AUDIO_INFO1[0], sizeof(mmAFMT_AUDIO_INFO1)/sizeof(mmAFMT_AUDIO_INFO1[0]), 0, 0 },
+	{ "mmAFMT_60958_0", REG_MMIO, 0x1C41, &mmAFMT_60958_0[0], sizeof(mmAFMT_60958_0)/sizeof(mmAFMT_60958_0[0]), 0, 0 },
+	{ "mmAFMT_60958_1", REG_MMIO, 0x1C42, &mmAFMT_60958_1[0], sizeof(mmAFMT_60958_1)/sizeof(mmAFMT_60958_1[0]), 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x1C43, &mmAFMT_AUDIO_CRC_CONTROL[0], sizeof(mmAFMT_AUDIO_CRC_CONTROL)/sizeof(mmAFMT_AUDIO_CRC_CONTROL[0]), 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL0", REG_MMIO, 0x1C44, &mmAFMT_RAMP_CONTROL0[0], sizeof(mmAFMT_RAMP_CONTROL0)/sizeof(mmAFMT_RAMP_CONTROL0[0]), 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL1", REG_MMIO, 0x1C45, &mmAFMT_RAMP_CONTROL1[0], sizeof(mmAFMT_RAMP_CONTROL1)/sizeof(mmAFMT_RAMP_CONTROL1[0]), 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL2", REG_MMIO, 0x1C46, &mmAFMT_RAMP_CONTROL2[0], sizeof(mmAFMT_RAMP_CONTROL2)/sizeof(mmAFMT_RAMP_CONTROL2[0]), 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL3", REG_MMIO, 0x1C47, &mmAFMT_RAMP_CONTROL3[0], sizeof(mmAFMT_RAMP_CONTROL3)/sizeof(mmAFMT_RAMP_CONTROL3[0]), 0, 0 },
+	{ "mmAFMT_60958_2", REG_MMIO, 0x1C48, &mmAFMT_60958_2[0], sizeof(mmAFMT_60958_2)/sizeof(mmAFMT_60958_2[0]), 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x1C49, &mmAFMT_AUDIO_CRC_RESULT[0], sizeof(mmAFMT_AUDIO_CRC_RESULT)/sizeof(mmAFMT_AUDIO_CRC_RESULT[0]), 0, 0 },
+	{ "mmAFMT_STATUS", REG_MMIO, 0x1C4A, &mmAFMT_STATUS[0], sizeof(mmAFMT_STATUS)/sizeof(mmAFMT_STATUS[0]), 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1C4B, &mmAFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmAFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x1C4C, &mmAFMT_VBI_PACKET_CONTROL[0], sizeof(mmAFMT_VBI_PACKET_CONTROL)/sizeof(mmAFMT_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmAFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x1C4D, &mmAFMT_INFOFRAME_CONTROL0[0], sizeof(mmAFMT_INFOFRAME_CONTROL0)/sizeof(mmAFMT_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmAFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x1C4F, &mmAFMT_AUDIO_SRC_CONTROL[0], sizeof(mmAFMT_AUDIO_SRC_CONTROL)/sizeof(mmAFMT_AUDIO_SRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_CNTL", REG_MMIO, 0x1C50, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_BE_EN_CNTL", REG_MMIO, 0x1C51, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x1C52, &mmAFMT_AUDIO_DBG_DTO_CNTL[0], sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL)/sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CNTL", REG_MMIO, 0x1C7C, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL_CHAR", REG_MMIO, 0x1C7D, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x1C7E, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x1C7F, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x1C80, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x1C81, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_DEBUG", REG_MMIO, 0x1C82, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_CTL_BITS", REG_MMIO, 0x1C83, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x1C84, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x1C86, NULL, 0, 0, 0 },
+	{ "mmDIG0_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x1C87, NULL, 0, 0, 0 },
+	{ "mmDIG0_LVDS_DATA_CNTL", REG_MMIO, 0x1C8C, NULL, 0, 0, 0 },
+	{ "mmDIG0_DIG_LANE_ENABLE", REG_MMIO, 0x1C8D, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL", REG_MMIO, 0x1CA0, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING1", REG_MMIO, 0x1CA1, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING2", REG_MMIO, 0x1CA2, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING3", REG_MMIO, 0x1CA3, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING4", REG_MMIO, 0x1CA4, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N", REG_MMIO, 0x1CA5, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x1CA6, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M", REG_MMIO, 0x1CA7, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x1CA8, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_TIMESTAMP", REG_MMIO, 0x1CA9, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_PACKET_CNTL", REG_MMIO, 0x1CAA, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL1", REG_MMIO, 0x1CAB, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_LINK_CNTL", REG_MMIO, 0x1CC0, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_PIXEL_FORMAT", REG_MMIO, 0x1CC1, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_CONFIG", REG_MMIO, 0x1CC2, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_VID_STREAM_CNTL", REG_MMIO, 0x1CC3, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_STEER_FIFO", REG_MMIO, 0x1CC4, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSA_MISC", REG_MMIO, 0x1CC5, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x1CC6, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x1CC7, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x1CC8, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_VID_TIMING", REG_MMIO, 0x1CC9, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_VID_N", REG_MMIO, 0x1CCA, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_VID_M", REG_MMIO, 0x1CCB, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x1CCC, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_VID_MSA_VBID", REG_MMIO, 0x1CCD, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x1CCE, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x1CCF, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_CNTL", REG_MMIO, 0x1CD0, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x1CD1, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM0", REG_MMIO, 0x1CD2, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x1CD3, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x1CD4, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_EN", REG_MMIO, 0x1CD6, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_CNTL", REG_MMIO, 0x1CD7, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_RESULT", REG_MMIO, 0x1CD8, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSA_COLORIMETRY", REG_MMIO, 0x1CDA, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSE_MISC_CNTL", REG_MMIO, 0x1CDB, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM2", REG_MMIO, 0x1CDF, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM1", REG_MMIO, 0x1CE0, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_CNTL", REG_MMIO, 0x1CE1, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_UPDATE", REG_MMIO, 0x1CE3, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSE_SAT0", REG_MMIO, 0x1CE4, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSE_SAT1", REG_MMIO, 0x1CE5, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSE_SAT2", REG_MMIO, 0x1CE6, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSE_SAT_UPDATE", REG_MMIO, 0x1CE7, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSE_LINK_TIMING", REG_MMIO, 0x1CE8, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x1CE9, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x1CEA, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x1CEB, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x1CFC, NULL, 0, 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_DATA", REG_MMIO, 0x1CFD, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_ENABLE", REG_MMIO, 0x1D00, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_CONTROL", REG_MMIO, 0x1D01, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1D02, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SWAP_CNTL", REG_MMIO, 0x1D03, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1D04, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1D05, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PITCH", REG_MMIO, 0x1D06, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1D07, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1D08, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1D09, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1D0A, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_START", REG_MMIO, 0x1D0B, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_START", REG_MMIO, 0x1D0C, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_END", REG_MMIO, 0x1D0D, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_END", REG_MMIO, 0x1D0E, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1D10, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_UPDATE", REG_MMIO, 0x1D11, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_CONTROL", REG_MMIO, 0x1D12, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1D13, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_CONTROL", REG_MMIO, 0x1D14, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_STATUS", REG_MMIO, 0x1D15, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1D16, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1D17, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1D18, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1D19, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1D1A, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1D1B, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_ENABLE", REG_MMIO, 0x1D1C, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_CONTROL1", REG_MMIO, 0x1D1D, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_CONTROL2", REG_MMIO, 0x1D1E, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SWAP_CNTL", REG_MMIO, 0x1D1F, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS", REG_MMIO, 0x1D20, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_PITCH", REG_MMIO, 0x1D21, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1D22, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x1D23, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1D24, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_START", REG_MMIO, 0x1D25, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_END", REG_MMIO, 0x1D26, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_UPDATE", REG_MMIO, 0x1D27, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1D28, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_DFQ_CONTROL", REG_MMIO, 0x1D29, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_DFQ_STATUS", REG_MMIO, 0x1D2A, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1D2B, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1D2C, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1D2D, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1D2E, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1D2F, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1D30, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_OVL_CONTROL", REG_MMIO, 0x1D31, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1D32, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1D33, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1D34, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_CONTROL", REG_MMIO, 0x1D35, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C11_C12", REG_MMIO, 0x1D36, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C13_C14", REG_MMIO, 0x1D37, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C21_C22", REG_MMIO, 0x1D38, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C23_C24", REG_MMIO, 0x1D39, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C31_C32", REG_MMIO, 0x1D3A, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C33_C34", REG_MMIO, 0x1D3B, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1D3C, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1D3D, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1D3E, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1D3F, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1D40, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1D41, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1D42, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1D43, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1D44, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1D45, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1D46, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1D47, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1D48, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1D49, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1D4A, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1D4B, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1D4C, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1D4D, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1D4E, NULL, 0, 0, 0 },
+	{ "mmDCP1_DENORM_CONTROL", REG_MMIO, 0x1D50, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_ROUND_CONTROL", REG_MMIO, 0x1D51, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_CONTROL", REG_MMIO, 0x1D53, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_ALPHA", REG_MMIO, 0x1D54, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_RED", REG_MMIO, 0x1D55, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_GREEN", REG_MMIO, 0x1D56, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_BLUE", REG_MMIO, 0x1D57, NULL, 0, 0, 0 },
+	{ "mmDCP1_DEGAMMA_CONTROL", REG_MMIO, 0x1D58, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1D59, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1D5A, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1D5B, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1D5C, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1D5D, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1D5E, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1D5F, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1D60, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_RANDOM_SEEDS", REG_MMIO, 0x1D61, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1D65, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_CONTROL", REG_MMIO, 0x1D66, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1D67, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SIZE", REG_MMIO, 0x1D68, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1D69, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_POSITION", REG_MMIO, 0x1D6A, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_HOT_SPOT", REG_MMIO, 0x1D6B, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR1", REG_MMIO, 0x1D6C, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR2", REG_MMIO, 0x1D6D, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_UPDATE", REG_MMIO, 0x1D6E, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_MODE", REG_MMIO, 0x1D78, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_INDEX", REG_MMIO, 0x1D79, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1D7A, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_PWL_DATA", REG_MMIO, 0x1D7B, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_30_COLOR", REG_MMIO, 0x1D7C, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1D7D, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1D7E, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_AUTOFILL", REG_MMIO, 0x1D7F, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_CONTROL", REG_MMIO, 0x1D80, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1D81, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1D82, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1D83, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1D84, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1D85, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1D86, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CONTROL", REG_MMIO, 0x1D87, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_MASK", REG_MMIO, 0x1D88, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CURRENT", REG_MMIO, 0x1D89, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_LAST", REG_MMIO, 0x1D8B, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG", REG_MMIO, 0x1D8D, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_GSL_CONTROL", REG_MMIO, 0x1D90, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1D91, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1D92, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x1D93, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1D94, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1D95, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1D96, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1D97, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG2", REG_MMIO, 0x1D98, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1D99, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CONTROL", REG_MMIO, 0x1DA0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_INDEX", REG_MMIO, 0x1DA1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_DATA", REG_MMIO, 0x1DA2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1DA3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1DA4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1DA5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1DA6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1DA7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1DA8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1DA9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1DAA, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1DAB, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1DAC, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1DAD, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1DAE, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1DAF, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1DB0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1DB1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1DB2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1DB3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1DB4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1DB5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1DB6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1DB7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1DB8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1DB9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1DBA, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1DBB, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1DC8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG2", REG_MMIO, 0x1DC9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SYNC_RESET_SEL", REG_MMIO, 0x1DCA, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1DD8, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1DD9, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1DDA, NULL, 0, 0, 0 },
+	{ "mmLB1_DC_MVP_LB_CONTROL", REG_MMIO, 0x1DDB, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG", REG_MMIO, 0x1DFC, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1DFE, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1DFF, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1E30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1E31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1E33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1E34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1E35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1E36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1E37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1E38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1E39, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1E40, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1E41, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TAP_CONTROL", REG_MMIO, 0x1E43, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_CONTROL", REG_MMIO, 0x1E44, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_BYPASS_CONTROL", REG_MMIO, 0x1E45, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1E46, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1E47, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1E4A, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1E4B, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1E4E, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1E4F, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1E50, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_UPDATE", REG_MMIO, 0x1E51, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1E53, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ALU_CONTROL", REG_MMIO, 0x1E54, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1E55, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1E57, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_START", REG_MMIO, 0x1E5C, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_SIZE", REG_MMIO, 0x1E5D, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1E5E, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1E5F, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1E60, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1E61, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1E62, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1E63, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG2", REG_MMIO, 0x1E69, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG", REG_MMIO, 0x1E6A, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1E6B, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1E6C, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1E78, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1E79, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_WINDOW", REG_MMIO, 0x1E7A, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_CONTROL", REG_MMIO, 0x1E7B, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1E7C, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1E7D, NULL, 0, 0, 0 },
+	{ "mmCRTC1_DCFE_DBG_SEL", REG_MMIO, 0x1E7E, NULL, 0, 0, 0 },
+	{ "mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x1E7F, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_TOTAL", REG_MMIO, 0x1E80, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_START_END", REG_MMIO, 0x1E81, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A", REG_MMIO, 0x1E82, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1E83, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B", REG_MMIO, 0x1E84, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1E85, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VBI_END", REG_MMIO, 0x1E86, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL", REG_MMIO, 0x1E87, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1E88, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1E89, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1E8A, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1E8B, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1E8C, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_BLANK_START_END", REG_MMIO, 0x1E8D, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A", REG_MMIO, 0x1E8E, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1E8F, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B", REG_MMIO, 0x1E90, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1E91, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1E92, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1E93, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_CNTL", REG_MMIO, 0x1E94, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1E95, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_CNTL", REG_MMIO, 0x1E96, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1E97, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1E98, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FLOW_CONTROL", REG_MMIO, 0x1E99, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1E9B, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CONTROL", REG_MMIO, 0x1E9C, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_CONTROL", REG_MMIO, 0x1E9D, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1E9E, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1E9F, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1EA0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1EA1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR", REG_MMIO, 0x1EA2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS", REG_MMIO, 0x1EA3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_POSITION", REG_MMIO, 0x1EA4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1EA5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1EA6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1EA7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1EA8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_CONTROL", REG_MMIO, 0x1EA9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_RESET", REG_MMIO, 0x1EAA, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1EAB, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1EAC, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_STATUS", REG_MMIO, 0x1EAD, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_CONTROL", REG_MMIO, 0x1EAE, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1EAF, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1EB0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1EB1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1EB2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1EB3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1EB4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_UPDATE_LOCK", REG_MMIO, 0x1EB5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1EB6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1EB7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1EBA, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1EBB, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1EBC, NULL, 0, 0, 0 },
+	{ "mmCRTC1_MASTER_UPDATE_LOCK", REG_MMIO, 0x1EBD, NULL, 0, 0, 0 },
+	{ "mmCRTC1_MASTER_UPDATE_MODE", REG_MMIO, 0x1EBE, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1EBF, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1EC0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_STATUS", REG_MMIO, 0x1EC1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_EN", REG_MMIO, 0x1EC2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1EC3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1EC4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1EC6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1EC7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1EEB, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1EEC, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1EED, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CONTROL", REG_MMIO, 0x1EEE, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1EEF, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_DATA_0_1", REG_MMIO, 0x1EF0, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_DATA_2_3", REG_MMIO, 0x1EF1, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1EF2, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1EF3, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1EF4, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1EF5, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1EF6, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1EF7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1EF8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_CNTL", REG_MMIO, 0x1EF9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_CNTL", REG_MMIO, 0x1EFA, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1EFB, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1EFC, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1EFD, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1EFE, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DEBUG_CNTL", REG_MMIO, 0x1EFF, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_FE_CNTL", REG_MMIO, 0x1F00, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x1F01, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x1F02, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_CLOCK_PATTERN", REG_MMIO, 0x1F03, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0x1F04, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_SMC, 0x1F05, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x1F08, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x1F09, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x1F0A, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_SMC, 0x1F0B, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmDIG1_HDMI_CONTROL", REG_MMIO, 0x1F0C, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_STATUS", REG_MMIO, 0x1F0D, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1F0E, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_SMC, 0x1F0F, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmDIG1_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x1F10, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x1F11, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x1F12, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x1F13, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x1F14, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GC", REG_MMIO, 0x1F16, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x1F17, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_0", REG_MMIO, 0x1F18, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_1", REG_MMIO, 0x1F19, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_2", REG_MMIO, 0x1F1A, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_3", REG_MMIO, 0x1F1B, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_4", REG_MMIO, 0x1F1C, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_0", REG_MMIO, 0x1F1D, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_1", REG_MMIO, 0x1F1E, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_2", REG_MMIO, 0x1F1F, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_3", REG_MMIO, 0x1F20, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO0", REG_MMIO, 0x1F21, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO1", REG_MMIO, 0x1F22, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO2", REG_MMIO, 0x1F23, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO3", REG_MMIO, 0x1F24, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO0", REG_MMIO, 0x1F25, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO1", REG_MMIO, 0x1F26, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_HDR", REG_MMIO, 0x1F27, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_0", REG_MMIO, 0x1F28, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_1", REG_MMIO, 0x1F29, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_2", REG_MMIO, 0x1F2A, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_3", REG_MMIO, 0x1F2B, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_4", REG_MMIO, 0x1F2C, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_5", REG_MMIO, 0x1F2D, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_6", REG_MMIO, 0x1F2E, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_7", REG_MMIO, 0x1F2F, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x1F30, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_0", REG_MMIO, 0x1F37, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_1", REG_MMIO, 0x1F38, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_0", REG_MMIO, 0x1F39, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_1", REG_MMIO, 0x1F3A, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_0", REG_MMIO, 0x1F3B, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_1", REG_MMIO, 0x1F3C, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_0", REG_MMIO, 0x1F3D, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_1", REG_MMIO, 0x1F3E, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO0", REG_MMIO, 0x1F3F, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO1", REG_MMIO, 0x1F40, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_0", REG_MMIO, 0x1F41, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_1", REG_MMIO, 0x1F42, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x1F43, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL0", REG_MMIO, 0x1F44, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL1", REG_MMIO, 0x1F45, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL2", REG_MMIO, 0x1F46, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL3", REG_MMIO, 0x1F47, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_2", REG_MMIO, 0x1F48, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x1F49, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_STATUS", REG_MMIO, 0x1F4A, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1F4B, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x1F4C, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x1F4D, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x1F4F, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_CNTL", REG_MMIO, 0x1F50, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_EN_CNTL", REG_MMIO, 0x1F51, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x1F52, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CNTL", REG_MMIO, 0x1F7C, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL_CHAR", REG_MMIO, 0x1F7D, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x1F7E, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x1F7F, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x1F80, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x1F81, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DEBUG", REG_MMIO, 0x1F82, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL_BITS", REG_MMIO, 0x1F83, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x1F84, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x1F86, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x1F87, NULL, 0, 0, 0 },
+	{ "mmDIG1_LVDS_DATA_CNTL", REG_MMIO, 0x1F8C, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_LANE_ENABLE", REG_MMIO, 0x1F8D, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL", REG_MMIO, 0x1FA0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING1", REG_MMIO, 0x1FA1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING2", REG_MMIO, 0x1FA2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING3", REG_MMIO, 0x1FA3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING4", REG_MMIO, 0x1FA4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N", REG_MMIO, 0x1FA5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x1FA6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M", REG_MMIO, 0x1FA7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x1FA8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_TIMESTAMP", REG_MMIO, 0x1FA9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_PACKET_CNTL", REG_MMIO, 0x1FAA, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL1", REG_MMIO, 0x1FAB, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_CNTL", REG_MMIO, 0x1FC0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_PIXEL_FORMAT", REG_MMIO, 0x1FC1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_CONFIG", REG_MMIO, 0x1FC2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_STREAM_CNTL", REG_MMIO, 0x1FC3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_STEER_FIFO", REG_MMIO, 0x1FC4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_MISC", REG_MMIO, 0x1FC5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x1FC6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x1FC7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x1FC8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_TIMING", REG_MMIO, 0x1FC9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_N", REG_MMIO, 0x1FCA, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_M", REG_MMIO, 0x1FCB, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x1FCC, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_MSA_VBID", REG_MMIO, 0x1FCD, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x1FCE, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x1FCF, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CNTL", REG_MMIO, 0x1FD0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x1FD1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM0", REG_MMIO, 0x1FD2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x1FD3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x1FD4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_EN", REG_MMIO, 0x1FD6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_CNTL", REG_MMIO, 0x1FD7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_RESULT", REG_MMIO, 0x1FD8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_COLORIMETRY", REG_MMIO, 0x1FDA, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_MISC_CNTL", REG_MMIO, 0x1FDB, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM2", REG_MMIO, 0x1FDF, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM1", REG_MMIO, 0x1FE0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_CNTL", REG_MMIO, 0x1FE1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_UPDATE", REG_MMIO, 0x1FE3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT0", REG_MMIO, 0x1FE4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT1", REG_MMIO, 0x1FE5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT2", REG_MMIO, 0x1FE6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT_UPDATE", REG_MMIO, 0x1FE7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_LINK_TIMING", REG_MMIO, 0x1FE8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x1FE9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x1FEA, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x1FEB, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x1FFC, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_DATA", REG_MMIO, 0x1FFD, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2200, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x2706, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x270D, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2", REG_SMC, 0x270E, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x2724, &ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3", REG_SMC, 0x273E, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x2770, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x2F09, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x2F0A, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x2F0B, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY", REG_SMC, 0x3702, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x3707, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x3708, &ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x3709, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x371C, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x371D, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x371E, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x371F, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION", REG_SMC, 0x3770, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x3771, &ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO", REG_SMC, 0x3772, &ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE", REG_SMC, 0x3777, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE", REG_SMC, 0x3778, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE", REG_SMC, 0x3779, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE", REG_SMC, 0x377A, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC", REG_SMC, 0x377B, &ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_HBR", REG_SMC, 0x377C, &ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX", REG_SMC, 0x3780, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA", REG_SMC, 0x3781, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x3785, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x3786, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x3787, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x3788, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x3789, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x378A, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x378B, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x378C, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x378D, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x378E, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x378F, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x3790, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x3791, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x3792, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x3793, &ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x3F09, &ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x3F0C, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH", REG_SMC, 0x3F0E, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0]), 0, 0 },
+	{ "mmDCP2_GRPH_ENABLE", REG_MMIO, 0x4000, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_CONTROL", REG_MMIO, 0x4001, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4002, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SWAP_CNTL", REG_MMIO, 0x4003, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4004, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4005, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PITCH", REG_MMIO, 0x4006, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4007, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4008, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4009, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x400A, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_START", REG_MMIO, 0x400B, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_START", REG_MMIO, 0x400C, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_END", REG_MMIO, 0x400D, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_END", REG_MMIO, 0x400E, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4010, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_UPDATE", REG_MMIO, 0x4011, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_CONTROL", REG_MMIO, 0x4012, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4013, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_CONTROL", REG_MMIO, 0x4014, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_STATUS", REG_MMIO, 0x4015, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4016, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4017, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4018, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4019, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_PITCH", REG_MMIO, 0x401A, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x401B, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_ENABLE", REG_MMIO, 0x401C, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_CONTROL1", REG_MMIO, 0x401D, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_CONTROL2", REG_MMIO, 0x401E, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SWAP_CNTL", REG_MMIO, 0x401F, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4020, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_PITCH", REG_MMIO, 0x4021, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4022, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4023, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4024, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_START", REG_MMIO, 0x4025, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_END", REG_MMIO, 0x4026, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_UPDATE", REG_MMIO, 0x4027, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4028, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_DFQ_CONTROL", REG_MMIO, 0x4029, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_DFQ_STATUS", REG_MMIO, 0x402A, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x402B, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x402C, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x402D, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x402E, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x402F, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4030, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4031, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4032, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4033, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4034, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_CONTROL", REG_MMIO, 0x4035, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C11_C12", REG_MMIO, 0x4036, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C13_C14", REG_MMIO, 0x4037, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C21_C22", REG_MMIO, 0x4038, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C23_C24", REG_MMIO, 0x4039, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C31_C32", REG_MMIO, 0x403A, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C33_C34", REG_MMIO, 0x403B, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_CONTROL", REG_MMIO, 0x403C, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C11_C12", REG_MMIO, 0x403D, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C13_C14", REG_MMIO, 0x403E, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C21_C22", REG_MMIO, 0x403F, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4040, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4041, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4042, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4043, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4044, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4045, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4046, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4047, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4048, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4049, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x404A, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x404B, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x404C, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x404D, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x404E, NULL, 0, 0, 0 },
+	{ "mmDCP2_DENORM_CONTROL", REG_MMIO, 0x4050, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_ROUND_CONTROL", REG_MMIO, 0x4051, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_CONTROL", REG_MMIO, 0x4053, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_ALPHA", REG_MMIO, 0x4054, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_RED", REG_MMIO, 0x4055, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_GREEN", REG_MMIO, 0x4056, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_BLUE", REG_MMIO, 0x4057, NULL, 0, 0, 0 },
+	{ "mmDCP2_DEGAMMA_CONTROL", REG_MMIO, 0x4058, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4059, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C11_C12", REG_MMIO, 0x405A, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C13_C14", REG_MMIO, 0x405B, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C21_C22", REG_MMIO, 0x405C, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C23_C24", REG_MMIO, 0x405D, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C31_C32", REG_MMIO, 0x405E, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C33_C34", REG_MMIO, 0x405F, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4060, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_RANDOM_SEEDS", REG_MMIO, 0x4061, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4065, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_CONTROL", REG_MMIO, 0x4066, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4067, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SIZE", REG_MMIO, 0x4068, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4069, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_POSITION", REG_MMIO, 0x406A, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_HOT_SPOT", REG_MMIO, 0x406B, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR1", REG_MMIO, 0x406C, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR2", REG_MMIO, 0x406D, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_UPDATE", REG_MMIO, 0x406E, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_MODE", REG_MMIO, 0x4078, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_INDEX", REG_MMIO, 0x4079, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_SEQ_COLOR", REG_MMIO, 0x407A, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_PWL_DATA", REG_MMIO, 0x407B, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_30_COLOR", REG_MMIO, 0x407C, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x407D, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x407E, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_AUTOFILL", REG_MMIO, 0x407F, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_CONTROL", REG_MMIO, 0x4080, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4081, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4082, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4083, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4084, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4085, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4086, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CONTROL", REG_MMIO, 0x4087, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_MASK", REG_MMIO, 0x4088, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CURRENT", REG_MMIO, 0x4089, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_LAST", REG_MMIO, 0x408B, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG", REG_MMIO, 0x408D, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_GSL_CONTROL", REG_MMIO, 0x4090, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4091, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4092, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4093, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4094, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4095, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4096, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4097, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG2", REG_MMIO, 0x4098, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4099, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CONTROL", REG_MMIO, 0x40A0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_INDEX", REG_MMIO, 0x40A1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_DATA", REG_MMIO, 0x40A2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x40A3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x40A4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x40A5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x40A6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x40A7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x40A8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x40A9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x40AA, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x40AB, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x40AC, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x40AD, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x40AE, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x40AF, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x40B0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x40B1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x40B2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x40B3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x40B4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x40B5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x40B6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x40B7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x40B8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x40B9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x40BA, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x40BB, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x40C8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG2", REG_MMIO, 0x40C9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SYNC_RESET_SEL", REG_MMIO, 0x40CA, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_MODE", REG_MMIO, 0x40D8, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x40D9, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x40DA, NULL, 0, 0, 0 },
+	{ "mmLB2_DC_MVP_LB_CONTROL", REG_MMIO, 0x40DB, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG", REG_MMIO, 0x40FC, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x40FE, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_DATA", REG_MMIO, 0x40FF, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4130, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4131, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4133, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4134, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4135, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4136, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4137, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4138, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4139, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4140, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4141, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TAP_CONTROL", REG_MMIO, 0x4143, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_CONTROL", REG_MMIO, 0x4144, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_BYPASS_CONTROL", REG_MMIO, 0x4145, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4146, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4147, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x414A, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x414B, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x414E, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x414F, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT", REG_MMIO, 0x4150, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_UPDATE", REG_MMIO, 0x4151, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4153, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ALU_CONTROL", REG_MMIO, 0x4154, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4155, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x4157, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_START", REG_MMIO, 0x415C, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_SIZE", REG_MMIO, 0x415D, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x415E, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x415F, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4160, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4161, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4162, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4163, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG2", REG_MMIO, 0x4169, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG", REG_MMIO, 0x416A, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x416B, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x416C, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4178, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4179, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_WINDOW", REG_MMIO, 0x417A, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_CONTROL", REG_MMIO, 0x417B, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x417C, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x417D, NULL, 0, 0, 0 },
+	{ "mmCRTC2_DCFE_DBG_SEL", REG_MMIO, 0x417E, NULL, 0, 0, 0 },
+	{ "mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x417F, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_TOTAL", REG_MMIO, 0x4180, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_START_END", REG_MMIO, 0x4181, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A", REG_MMIO, 0x4182, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4183, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B", REG_MMIO, 0x4184, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4185, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VBI_END", REG_MMIO, 0x4186, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL", REG_MMIO, 0x4187, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4188, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4189, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x418A, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x418B, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x418C, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_BLANK_START_END", REG_MMIO, 0x418D, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A", REG_MMIO, 0x418E, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x418F, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B", REG_MMIO, 0x4190, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4191, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4192, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4193, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_CNTL", REG_MMIO, 0x4194, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4195, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_CNTL", REG_MMIO, 0x4196, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4197, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4198, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FLOW_CONTROL", REG_MMIO, 0x4199, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x419B, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CONTROL", REG_MMIO, 0x419C, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_CONTROL", REG_MMIO, 0x419D, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x419E, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_STATUS", REG_MMIO, 0x419F, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x41A0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x41A1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR", REG_MMIO, 0x41A2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS", REG_MMIO, 0x41A3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_POSITION", REG_MMIO, 0x41A4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x41A5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x41A6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x41A7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x41A8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_CONTROL", REG_MMIO, 0x41A9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_RESET", REG_MMIO, 0x41AA, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x41AB, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x41AC, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_STATUS", REG_MMIO, 0x41AD, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_CONTROL", REG_MMIO, 0x41AE, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x41AF, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x41B0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x41B1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x41B2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_START_LINE_CONTROL", REG_MMIO, 0x41B3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x41B4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_UPDATE_LOCK", REG_MMIO, 0x41B5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x41B6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x41B7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x41BA, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x41BB, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x41BC, NULL, 0, 0, 0 },
+	{ "mmCRTC2_MASTER_UPDATE_LOCK", REG_MMIO, 0x41BD, NULL, 0, 0, 0 },
+	{ "mmCRTC2_MASTER_UPDATE_MODE", REG_MMIO, 0x41BE, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x41BF, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x41C0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_STATUS", REG_MMIO, 0x41C1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_EN", REG_MMIO, 0x41C2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x41C3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x41C4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x41C6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x41C7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x41EB, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x41EC, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x41ED, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CONTROL", REG_MMIO, 0x41EE, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x41EF, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_DATA_0_1", REG_MMIO, 0x41F0, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_DATA_2_3", REG_MMIO, 0x41F1, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x41F2, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x41F3, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x41F4, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x41F5, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x41F6, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x41F7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x41F8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_CNTL", REG_MMIO, 0x41F9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_CNTL", REG_MMIO, 0x41FA, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x41FB, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x41FC, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x41FD, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x41FE, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DEBUG_CNTL", REG_MMIO, 0x41FF, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FE_CNTL", REG_MMIO, 0x4200, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4201, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4202, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_CLOCK_PATTERN", REG_MMIO, 0x4203, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_PATTERN", REG_MMIO, 0x4204, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4205, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4208, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4209, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FIFO_STATUS", REG_MMIO, 0x420A, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_CONTROL", REG_MMIO, 0x420C, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_STATUS", REG_MMIO, 0x420D, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x420E, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x420F, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4210, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4211, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4212, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4213, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4214, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GC", REG_MMIO, 0x4216, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4217, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_0", REG_MMIO, 0x4218, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_1", REG_MMIO, 0x4219, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_2", REG_MMIO, 0x421A, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_3", REG_MMIO, 0x421B, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_4", REG_MMIO, 0x421C, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_0", REG_MMIO, 0x421D, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_1", REG_MMIO, 0x421E, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_2", REG_MMIO, 0x421F, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_3", REG_MMIO, 0x4220, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO0", REG_MMIO, 0x4221, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO1", REG_MMIO, 0x4222, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO2", REG_MMIO, 0x4223, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO3", REG_MMIO, 0x4224, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO0", REG_MMIO, 0x4225, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO1", REG_MMIO, 0x4226, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_HDR", REG_MMIO, 0x4227, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_0", REG_MMIO, 0x4228, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_1", REG_MMIO, 0x4229, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_2", REG_MMIO, 0x422A, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_3", REG_MMIO, 0x422B, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_4", REG_MMIO, 0x422C, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_5", REG_MMIO, 0x422D, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_6", REG_MMIO, 0x422E, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_7", REG_MMIO, 0x422F, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4230, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_0", REG_MMIO, 0x4237, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_1", REG_MMIO, 0x4238, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_0", REG_MMIO, 0x4239, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_1", REG_MMIO, 0x423A, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_0", REG_MMIO, 0x423B, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_1", REG_MMIO, 0x423C, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_0", REG_MMIO, 0x423D, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_1", REG_MMIO, 0x423E, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO0", REG_MMIO, 0x423F, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO1", REG_MMIO, 0x4240, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_0", REG_MMIO, 0x4241, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_1", REG_MMIO, 0x4242, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4243, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4244, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4245, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4246, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4247, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_2", REG_MMIO, 0x4248, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4249, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_STATUS", REG_MMIO, 0x424A, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x424B, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x424C, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x424D, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x424F, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_CNTL", REG_MMIO, 0x4250, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_EN_CNTL", REG_MMIO, 0x4251, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4252, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CNTL", REG_MMIO, 0x427C, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL_CHAR", REG_MMIO, 0x427D, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x427E, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x427F, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4280, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4281, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DEBUG", REG_MMIO, 0x4282, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL_BITS", REG_MMIO, 0x4283, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4284, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4286, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4287, NULL, 0, 0, 0 },
+	{ "mmDIG2_LVDS_DATA_CNTL", REG_MMIO, 0x428C, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_LANE_ENABLE", REG_MMIO, 0x428D, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL", REG_MMIO, 0x42A0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING1", REG_MMIO, 0x42A1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING2", REG_MMIO, 0x42A2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING3", REG_MMIO, 0x42A3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING4", REG_MMIO, 0x42A4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N", REG_MMIO, 0x42A5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x42A6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M", REG_MMIO, 0x42A7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x42A8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_TIMESTAMP", REG_MMIO, 0x42A9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_PACKET_CNTL", REG_MMIO, 0x42AA, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL1", REG_MMIO, 0x42AB, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_CNTL", REG_MMIO, 0x42C0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_PIXEL_FORMAT", REG_MMIO, 0x42C1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_CONFIG", REG_MMIO, 0x42C2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_STREAM_CNTL", REG_MMIO, 0x42C3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_STEER_FIFO", REG_MMIO, 0x42C4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_MISC", REG_MMIO, 0x42C5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x42C6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x42C7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x42C8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_TIMING", REG_MMIO, 0x42C9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_N", REG_MMIO, 0x42CA, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_M", REG_MMIO, 0x42CB, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x42CC, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_MSA_VBID", REG_MMIO, 0x42CD, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x42CE, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x42CF, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CNTL", REG_MMIO, 0x42D0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x42D1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM0", REG_MMIO, 0x42D2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x42D3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x42D4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_EN", REG_MMIO, 0x42D6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_CNTL", REG_MMIO, 0x42D7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_RESULT", REG_MMIO, 0x42D8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_COLORIMETRY", REG_MMIO, 0x42DA, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_MISC_CNTL", REG_MMIO, 0x42DB, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM2", REG_MMIO, 0x42DF, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM1", REG_MMIO, 0x42E0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_CNTL", REG_MMIO, 0x42E1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_UPDATE", REG_MMIO, 0x42E3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT0", REG_MMIO, 0x42E4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT1", REG_MMIO, 0x42E5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT2", REG_MMIO, 0x42E6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT_UPDATE", REG_MMIO, 0x42E7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_LINK_TIMING", REG_MMIO, 0x42E8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x42E9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x42EA, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x42EB, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x42FC, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_DATA", REG_MMIO, 0x42FD, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_ENABLE", REG_MMIO, 0x4300, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_CONTROL", REG_MMIO, 0x4301, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4302, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SWAP_CNTL", REG_MMIO, 0x4303, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4304, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4305, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PITCH", REG_MMIO, 0x4306, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4307, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4308, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4309, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x430A, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_START", REG_MMIO, 0x430B, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_START", REG_MMIO, 0x430C, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_END", REG_MMIO, 0x430D, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_END", REG_MMIO, 0x430E, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4310, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_UPDATE", REG_MMIO, 0x4311, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_CONTROL", REG_MMIO, 0x4312, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4313, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_CONTROL", REG_MMIO, 0x4314, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_STATUS", REG_MMIO, 0x4315, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4316, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4317, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4318, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4319, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_PITCH", REG_MMIO, 0x431A, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x431B, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_ENABLE", REG_MMIO, 0x431C, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_CONTROL1", REG_MMIO, 0x431D, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_CONTROL2", REG_MMIO, 0x431E, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SWAP_CNTL", REG_MMIO, 0x431F, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4320, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_PITCH", REG_MMIO, 0x4321, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4322, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4323, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4324, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_START", REG_MMIO, 0x4325, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_END", REG_MMIO, 0x4326, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_UPDATE", REG_MMIO, 0x4327, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4328, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_DFQ_CONTROL", REG_MMIO, 0x4329, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_DFQ_STATUS", REG_MMIO, 0x432A, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x432B, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x432C, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x432D, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x432E, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x432F, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4330, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4331, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4332, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4333, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4334, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_CONTROL", REG_MMIO, 0x4335, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C11_C12", REG_MMIO, 0x4336, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C13_C14", REG_MMIO, 0x4337, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C21_C22", REG_MMIO, 0x4338, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C23_C24", REG_MMIO, 0x4339, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C31_C32", REG_MMIO, 0x433A, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C33_C34", REG_MMIO, 0x433B, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_CONTROL", REG_MMIO, 0x433C, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C11_C12", REG_MMIO, 0x433D, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C13_C14", REG_MMIO, 0x433E, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C21_C22", REG_MMIO, 0x433F, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4340, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4341, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4342, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4343, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4344, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4345, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4346, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4347, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4348, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4349, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x434A, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x434B, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x434C, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x434D, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x434E, NULL, 0, 0, 0 },
+	{ "mmDCP3_DENORM_CONTROL", REG_MMIO, 0x4350, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_ROUND_CONTROL", REG_MMIO, 0x4351, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_CONTROL", REG_MMIO, 0x4353, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_ALPHA", REG_MMIO, 0x4354, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_RED", REG_MMIO, 0x4355, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_GREEN", REG_MMIO, 0x4356, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_BLUE", REG_MMIO, 0x4357, NULL, 0, 0, 0 },
+	{ "mmDCP3_DEGAMMA_CONTROL", REG_MMIO, 0x4358, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4359, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C11_C12", REG_MMIO, 0x435A, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C13_C14", REG_MMIO, 0x435B, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C21_C22", REG_MMIO, 0x435C, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C23_C24", REG_MMIO, 0x435D, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C31_C32", REG_MMIO, 0x435E, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C33_C34", REG_MMIO, 0x435F, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4360, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_RANDOM_SEEDS", REG_MMIO, 0x4361, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4365, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_CONTROL", REG_MMIO, 0x4366, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4367, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SIZE", REG_MMIO, 0x4368, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4369, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_POSITION", REG_MMIO, 0x436A, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_HOT_SPOT", REG_MMIO, 0x436B, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR1", REG_MMIO, 0x436C, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR2", REG_MMIO, 0x436D, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_UPDATE", REG_MMIO, 0x436E, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_MODE", REG_MMIO, 0x4378, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_INDEX", REG_MMIO, 0x4379, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_SEQ_COLOR", REG_MMIO, 0x437A, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_PWL_DATA", REG_MMIO, 0x437B, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_30_COLOR", REG_MMIO, 0x437C, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x437D, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x437E, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_AUTOFILL", REG_MMIO, 0x437F, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_CONTROL", REG_MMIO, 0x4380, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4381, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4382, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4383, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4384, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4385, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4386, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CONTROL", REG_MMIO, 0x4387, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_MASK", REG_MMIO, 0x4388, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CURRENT", REG_MMIO, 0x4389, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_LAST", REG_MMIO, 0x438B, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG", REG_MMIO, 0x438D, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_GSL_CONTROL", REG_MMIO, 0x4390, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4391, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4392, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4393, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4394, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4395, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4396, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4397, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG2", REG_MMIO, 0x4398, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4399, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CONTROL", REG_MMIO, 0x43A0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_INDEX", REG_MMIO, 0x43A1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_DATA", REG_MMIO, 0x43A2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x43A3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x43A4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x43A5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x43A6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x43A7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x43A8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x43A9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x43AA, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x43AB, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x43AC, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x43AD, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x43AE, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x43AF, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x43B0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x43B1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x43B2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x43B3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x43B4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x43B5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x43B6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x43B7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x43B8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x43B9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x43BA, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x43BB, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x43C8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG2", REG_MMIO, 0x43C9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SYNC_RESET_SEL", REG_MMIO, 0x43CA, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_MODE", REG_MMIO, 0x43D8, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x43D9, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x43DA, NULL, 0, 0, 0 },
+	{ "mmLB3_DC_MVP_LB_CONTROL", REG_MMIO, 0x43DB, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG", REG_MMIO, 0x43FC, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x43FE, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_DATA", REG_MMIO, 0x43FF, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4430, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4431, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4433, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4434, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4435, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4436, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4437, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4438, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4439, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4440, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4441, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TAP_CONTROL", REG_MMIO, 0x4443, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_CONTROL", REG_MMIO, 0x4444, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_BYPASS_CONTROL", REG_MMIO, 0x4445, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4446, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4447, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x444A, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x444B, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x444E, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x444F, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT", REG_MMIO, 0x4450, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_UPDATE", REG_MMIO, 0x4451, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4453, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ALU_CONTROL", REG_MMIO, 0x4454, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4455, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x4457, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_START", REG_MMIO, 0x445C, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_SIZE", REG_MMIO, 0x445D, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x445E, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x445F, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4460, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4461, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4462, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4463, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG2", REG_MMIO, 0x4469, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG", REG_MMIO, 0x446A, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x446B, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x446C, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4478, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4479, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_WINDOW", REG_MMIO, 0x447A, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_CONTROL", REG_MMIO, 0x447B, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x447C, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x447D, NULL, 0, 0, 0 },
+	{ "mmCRTC3_DCFE_DBG_SEL", REG_MMIO, 0x447E, NULL, 0, 0, 0 },
+	{ "mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x447F, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_TOTAL", REG_MMIO, 0x4480, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_START_END", REG_MMIO, 0x4481, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A", REG_MMIO, 0x4482, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4483, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B", REG_MMIO, 0x4484, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4485, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VBI_END", REG_MMIO, 0x4486, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL", REG_MMIO, 0x4487, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4488, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4489, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x448A, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x448B, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x448C, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_BLANK_START_END", REG_MMIO, 0x448D, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A", REG_MMIO, 0x448E, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x448F, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B", REG_MMIO, 0x4490, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4491, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4492, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4493, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_CNTL", REG_MMIO, 0x4494, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4495, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_CNTL", REG_MMIO, 0x4496, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4497, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4498, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FLOW_CONTROL", REG_MMIO, 0x4499, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x449B, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CONTROL", REG_MMIO, 0x449C, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_CONTROL", REG_MMIO, 0x449D, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x449E, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_STATUS", REG_MMIO, 0x449F, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x44A0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x44A1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR", REG_MMIO, 0x44A2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS", REG_MMIO, 0x44A3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_POSITION", REG_MMIO, 0x44A4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x44A5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x44A6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x44A7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x44A8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_CONTROL", REG_MMIO, 0x44A9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_RESET", REG_MMIO, 0x44AA, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x44AB, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x44AC, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_STATUS", REG_MMIO, 0x44AD, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_CONTROL", REG_MMIO, 0x44AE, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x44AF, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x44B0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x44B1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x44B2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_START_LINE_CONTROL", REG_MMIO, 0x44B3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x44B4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_UPDATE_LOCK", REG_MMIO, 0x44B5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x44B6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x44B7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x44BA, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x44BB, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x44BC, NULL, 0, 0, 0 },
+	{ "mmCRTC3_MASTER_UPDATE_LOCK", REG_MMIO, 0x44BD, NULL, 0, 0, 0 },
+	{ "mmCRTC3_MASTER_UPDATE_MODE", REG_MMIO, 0x44BE, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x44BF, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x44C0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_STATUS", REG_MMIO, 0x44C1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_EN", REG_MMIO, 0x44C2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x44C3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x44C4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x44C6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x44C7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x44EB, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x44EC, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x44ED, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CONTROL", REG_MMIO, 0x44EE, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x44EF, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_DATA_0_1", REG_MMIO, 0x44F0, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_DATA_2_3", REG_MMIO, 0x44F1, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x44F2, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x44F3, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x44F4, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x44F5, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x44F6, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x44F7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x44F8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_CNTL", REG_MMIO, 0x44F9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_CNTL", REG_MMIO, 0x44FA, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x44FB, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x44FC, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x44FD, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x44FE, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DEBUG_CNTL", REG_MMIO, 0x44FF, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FE_CNTL", REG_MMIO, 0x4500, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4501, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4502, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_CLOCK_PATTERN", REG_MMIO, 0x4503, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_PATTERN", REG_MMIO, 0x4504, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4505, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4508, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4509, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FIFO_STATUS", REG_MMIO, 0x450A, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_CONTROL", REG_MMIO, 0x450C, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_STATUS", REG_MMIO, 0x450D, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x450E, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x450F, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4510, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4511, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4512, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4513, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4514, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GC", REG_MMIO, 0x4516, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4517, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_0", REG_MMIO, 0x4518, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_1", REG_MMIO, 0x4519, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_2", REG_MMIO, 0x451A, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_3", REG_MMIO, 0x451B, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_4", REG_MMIO, 0x451C, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_0", REG_MMIO, 0x451D, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_1", REG_MMIO, 0x451E, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_2", REG_MMIO, 0x451F, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_3", REG_MMIO, 0x4520, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO0", REG_MMIO, 0x4521, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO1", REG_MMIO, 0x4522, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO2", REG_MMIO, 0x4523, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO3", REG_MMIO, 0x4524, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO0", REG_MMIO, 0x4525, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO1", REG_MMIO, 0x4526, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_HDR", REG_MMIO, 0x4527, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_0", REG_MMIO, 0x4528, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_1", REG_MMIO, 0x4529, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_2", REG_MMIO, 0x452A, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_3", REG_MMIO, 0x452B, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_4", REG_MMIO, 0x452C, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_5", REG_MMIO, 0x452D, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_6", REG_MMIO, 0x452E, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_7", REG_MMIO, 0x452F, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4530, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_0", REG_MMIO, 0x4537, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_1", REG_MMIO, 0x4538, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_0", REG_MMIO, 0x4539, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_1", REG_MMIO, 0x453A, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_0", REG_MMIO, 0x453B, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_1", REG_MMIO, 0x453C, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_0", REG_MMIO, 0x453D, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_1", REG_MMIO, 0x453E, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO0", REG_MMIO, 0x453F, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO1", REG_MMIO, 0x4540, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_0", REG_MMIO, 0x4541, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_1", REG_MMIO, 0x4542, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4543, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4544, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4545, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4546, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4547, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_2", REG_MMIO, 0x4548, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4549, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_STATUS", REG_MMIO, 0x454A, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x454B, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x454C, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x454D, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x454F, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_CNTL", REG_MMIO, 0x4550, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_EN_CNTL", REG_MMIO, 0x4551, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4552, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CNTL", REG_MMIO, 0x457C, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL_CHAR", REG_MMIO, 0x457D, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x457E, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x457F, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4580, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4581, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DEBUG", REG_MMIO, 0x4582, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL_BITS", REG_MMIO, 0x4583, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4584, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4586, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4587, NULL, 0, 0, 0 },
+	{ "mmDIG3_LVDS_DATA_CNTL", REG_MMIO, 0x458C, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_LANE_ENABLE", REG_MMIO, 0x458D, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL", REG_MMIO, 0x45A0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING1", REG_MMIO, 0x45A1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING2", REG_MMIO, 0x45A2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING3", REG_MMIO, 0x45A3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING4", REG_MMIO, 0x45A4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N", REG_MMIO, 0x45A5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x45A6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M", REG_MMIO, 0x45A7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x45A8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_TIMESTAMP", REG_MMIO, 0x45A9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_PACKET_CNTL", REG_MMIO, 0x45AA, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL1", REG_MMIO, 0x45AB, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_CNTL", REG_MMIO, 0x45C0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_PIXEL_FORMAT", REG_MMIO, 0x45C1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_CONFIG", REG_MMIO, 0x45C2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_STREAM_CNTL", REG_MMIO, 0x45C3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_STEER_FIFO", REG_MMIO, 0x45C4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_MISC", REG_MMIO, 0x45C5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x45C6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x45C7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x45C8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_TIMING", REG_MMIO, 0x45C9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_N", REG_MMIO, 0x45CA, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_M", REG_MMIO, 0x45CB, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x45CC, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_MSA_VBID", REG_MMIO, 0x45CD, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x45CE, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x45CF, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CNTL", REG_MMIO, 0x45D0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x45D1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM0", REG_MMIO, 0x45D2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x45D3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x45D4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_EN", REG_MMIO, 0x45D6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_CNTL", REG_MMIO, 0x45D7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_RESULT", REG_MMIO, 0x45D8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_COLORIMETRY", REG_MMIO, 0x45DA, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_MISC_CNTL", REG_MMIO, 0x45DB, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM2", REG_MMIO, 0x45DF, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM1", REG_MMIO, 0x45E0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_CNTL", REG_MMIO, 0x45E1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_UPDATE", REG_MMIO, 0x45E3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT0", REG_MMIO, 0x45E4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT1", REG_MMIO, 0x45E5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT2", REG_MMIO, 0x45E6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT_UPDATE", REG_MMIO, 0x45E7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_LINK_TIMING", REG_MMIO, 0x45E8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x45E9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x45EA, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x45EB, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x45FC, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_DATA", REG_MMIO, 0x45FD, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_ENABLE", REG_MMIO, 0x4600, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_CONTROL", REG_MMIO, 0x4601, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4602, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SWAP_CNTL", REG_MMIO, 0x4603, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4604, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4605, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PITCH", REG_MMIO, 0x4606, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4607, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4608, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4609, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x460A, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_START", REG_MMIO, 0x460B, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_START", REG_MMIO, 0x460C, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_END", REG_MMIO, 0x460D, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_END", REG_MMIO, 0x460E, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4610, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_UPDATE", REG_MMIO, 0x4611, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_CONTROL", REG_MMIO, 0x4612, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4613, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_CONTROL", REG_MMIO, 0x4614, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_STATUS", REG_MMIO, 0x4615, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4616, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4617, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4618, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4619, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_PITCH", REG_MMIO, 0x461A, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x461B, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_ENABLE", REG_MMIO, 0x461C, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_CONTROL1", REG_MMIO, 0x461D, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_CONTROL2", REG_MMIO, 0x461E, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SWAP_CNTL", REG_MMIO, 0x461F, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4620, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_PITCH", REG_MMIO, 0x4621, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4622, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4623, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4624, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_START", REG_MMIO, 0x4625, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_END", REG_MMIO, 0x4626, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_UPDATE", REG_MMIO, 0x4627, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4628, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_DFQ_CONTROL", REG_MMIO, 0x4629, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_DFQ_STATUS", REG_MMIO, 0x462A, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x462B, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x462C, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x462D, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x462E, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x462F, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4630, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4631, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4632, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4633, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4634, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_CONTROL", REG_MMIO, 0x4635, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C11_C12", REG_MMIO, 0x4636, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C13_C14", REG_MMIO, 0x4637, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C21_C22", REG_MMIO, 0x4638, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C23_C24", REG_MMIO, 0x4639, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C31_C32", REG_MMIO, 0x463A, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C33_C34", REG_MMIO, 0x463B, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_CONTROL", REG_MMIO, 0x463C, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C11_C12", REG_MMIO, 0x463D, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C13_C14", REG_MMIO, 0x463E, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C21_C22", REG_MMIO, 0x463F, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4640, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4641, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4642, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4643, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4644, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4645, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4646, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4647, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4648, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4649, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x464A, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x464B, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x464C, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x464D, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x464E, NULL, 0, 0, 0 },
+	{ "mmDCP4_DENORM_CONTROL", REG_MMIO, 0x4650, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_ROUND_CONTROL", REG_MMIO, 0x4651, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_CONTROL", REG_MMIO, 0x4653, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_ALPHA", REG_MMIO, 0x4654, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_RED", REG_MMIO, 0x4655, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_GREEN", REG_MMIO, 0x4656, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_BLUE", REG_MMIO, 0x4657, NULL, 0, 0, 0 },
+	{ "mmDCP4_DEGAMMA_CONTROL", REG_MMIO, 0x4658, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4659, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C11_C12", REG_MMIO, 0x465A, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C13_C14", REG_MMIO, 0x465B, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C21_C22", REG_MMIO, 0x465C, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C23_C24", REG_MMIO, 0x465D, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C31_C32", REG_MMIO, 0x465E, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C33_C34", REG_MMIO, 0x465F, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4660, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_RANDOM_SEEDS", REG_MMIO, 0x4661, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4665, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_CONTROL", REG_MMIO, 0x4666, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4667, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SIZE", REG_MMIO, 0x4668, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4669, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_POSITION", REG_MMIO, 0x466A, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_HOT_SPOT", REG_MMIO, 0x466B, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR1", REG_MMIO, 0x466C, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR2", REG_MMIO, 0x466D, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_UPDATE", REG_MMIO, 0x466E, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_MODE", REG_MMIO, 0x4678, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_INDEX", REG_MMIO, 0x4679, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_SEQ_COLOR", REG_MMIO, 0x467A, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_PWL_DATA", REG_MMIO, 0x467B, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_30_COLOR", REG_MMIO, 0x467C, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x467D, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x467E, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_AUTOFILL", REG_MMIO, 0x467F, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_CONTROL", REG_MMIO, 0x4680, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4681, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4682, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4683, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4684, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4685, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4686, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CONTROL", REG_MMIO, 0x4687, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_MASK", REG_MMIO, 0x4688, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CURRENT", REG_MMIO, 0x4689, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_LAST", REG_MMIO, 0x468B, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG", REG_MMIO, 0x468D, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_GSL_CONTROL", REG_MMIO, 0x4690, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4691, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4692, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4693, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4694, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4695, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4696, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4697, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG2", REG_MMIO, 0x4698, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4699, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CONTROL", REG_MMIO, 0x46A0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_INDEX", REG_MMIO, 0x46A1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_DATA", REG_MMIO, 0x46A2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x46A3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x46A4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x46A5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x46A6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x46A7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x46A8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x46A9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x46AA, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x46AB, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x46AC, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x46AD, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x46AE, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x46AF, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x46B0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x46B1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x46B2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x46B3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x46B4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x46B5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x46B6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x46B7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x46B8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x46B9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x46BA, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x46BB, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x46C8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG2", REG_MMIO, 0x46C9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SYNC_RESET_SEL", REG_MMIO, 0x46CA, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_MODE", REG_MMIO, 0x46D8, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x46D9, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x46DA, NULL, 0, 0, 0 },
+	{ "mmLB4_DC_MVP_LB_CONTROL", REG_MMIO, 0x46DB, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG", REG_MMIO, 0x46FC, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x46FE, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_DATA", REG_MMIO, 0x46FF, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4730, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4731, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4733, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4734, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4735, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4736, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4737, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4738, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4739, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4740, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4741, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TAP_CONTROL", REG_MMIO, 0x4743, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_CONTROL", REG_MMIO, 0x4744, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_BYPASS_CONTROL", REG_MMIO, 0x4745, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4746, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4747, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x474A, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x474B, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x474E, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x474F, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT", REG_MMIO, 0x4750, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_UPDATE", REG_MMIO, 0x4751, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4753, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ALU_CONTROL", REG_MMIO, 0x4754, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4755, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x4757, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_START", REG_MMIO, 0x475C, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_SIZE", REG_MMIO, 0x475D, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x475E, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x475F, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4760, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4761, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4762, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4763, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG2", REG_MMIO, 0x4769, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG", REG_MMIO, 0x476A, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x476B, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x476C, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4778, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4779, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_WINDOW", REG_MMIO, 0x477A, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_CONTROL", REG_MMIO, 0x477B, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x477C, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x477D, NULL, 0, 0, 0 },
+	{ "mmCRTC4_DCFE_DBG_SEL", REG_MMIO, 0x477E, NULL, 0, 0, 0 },
+	{ "mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x477F, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_TOTAL", REG_MMIO, 0x4780, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_START_END", REG_MMIO, 0x4781, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A", REG_MMIO, 0x4782, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4783, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B", REG_MMIO, 0x4784, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4785, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VBI_END", REG_MMIO, 0x4786, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL", REG_MMIO, 0x4787, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4788, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4789, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x478A, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x478B, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x478C, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_BLANK_START_END", REG_MMIO, 0x478D, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A", REG_MMIO, 0x478E, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x478F, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B", REG_MMIO, 0x4790, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4791, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4792, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4793, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_CNTL", REG_MMIO, 0x4794, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4795, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_CNTL", REG_MMIO, 0x4796, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4797, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4798, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FLOW_CONTROL", REG_MMIO, 0x4799, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x479B, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CONTROL", REG_MMIO, 0x479C, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_CONTROL", REG_MMIO, 0x479D, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x479E, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_STATUS", REG_MMIO, 0x479F, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x47A0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x47A1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR", REG_MMIO, 0x47A2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS", REG_MMIO, 0x47A3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_POSITION", REG_MMIO, 0x47A4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x47A5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x47A6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x47A7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x47A8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_CONTROL", REG_MMIO, 0x47A9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_RESET", REG_MMIO, 0x47AA, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x47AB, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x47AC, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_STATUS", REG_MMIO, 0x47AD, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_CONTROL", REG_MMIO, 0x47AE, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x47AF, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x47B0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x47B1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x47B2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_START_LINE_CONTROL", REG_MMIO, 0x47B3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x47B4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_UPDATE_LOCK", REG_MMIO, 0x47B5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x47B6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x47B7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x47BA, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x47BB, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x47BC, NULL, 0, 0, 0 },
+	{ "mmCRTC4_MASTER_UPDATE_LOCK", REG_MMIO, 0x47BD, NULL, 0, 0, 0 },
+	{ "mmCRTC4_MASTER_UPDATE_MODE", REG_MMIO, 0x47BE, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x47BF, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x47C0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_STATUS", REG_MMIO, 0x47C1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_EN", REG_MMIO, 0x47C2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x47C3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x47C4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x47C6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x47C7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x47EB, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x47EC, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x47ED, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CONTROL", REG_MMIO, 0x47EE, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x47EF, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_DATA_0_1", REG_MMIO, 0x47F0, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_DATA_2_3", REG_MMIO, 0x47F1, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x47F2, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x47F3, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x47F4, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x47F5, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x47F6, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x47F7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x47F8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_CNTL", REG_MMIO, 0x47F9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_CNTL", REG_MMIO, 0x47FA, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x47FB, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x47FC, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x47FD, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x47FE, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DEBUG_CNTL", REG_MMIO, 0x47FF, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FE_CNTL", REG_MMIO, 0x4800, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4801, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4802, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_CLOCK_PATTERN", REG_MMIO, 0x4803, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_PATTERN", REG_MMIO, 0x4804, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4805, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4808, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4809, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FIFO_STATUS", REG_MMIO, 0x480A, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_CONTROL", REG_MMIO, 0x480C, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_STATUS", REG_MMIO, 0x480D, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x480E, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x480F, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4810, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4811, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4812, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4813, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4814, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GC", REG_MMIO, 0x4816, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4817, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_0", REG_MMIO, 0x4818, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_1", REG_MMIO, 0x4819, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_2", REG_MMIO, 0x481A, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_3", REG_MMIO, 0x481B, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_4", REG_MMIO, 0x481C, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_0", REG_MMIO, 0x481D, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_1", REG_MMIO, 0x481E, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_2", REG_MMIO, 0x481F, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_3", REG_MMIO, 0x4820, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO0", REG_MMIO, 0x4821, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO1", REG_MMIO, 0x4822, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO2", REG_MMIO, 0x4823, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO3", REG_MMIO, 0x4824, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO0", REG_MMIO, 0x4825, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO1", REG_MMIO, 0x4826, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_HDR", REG_MMIO, 0x4827, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_0", REG_MMIO, 0x4828, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_1", REG_MMIO, 0x4829, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_2", REG_MMIO, 0x482A, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_3", REG_MMIO, 0x482B, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_4", REG_MMIO, 0x482C, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_5", REG_MMIO, 0x482D, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_6", REG_MMIO, 0x482E, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_7", REG_MMIO, 0x482F, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4830, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_0", REG_MMIO, 0x4837, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_1", REG_MMIO, 0x4838, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_0", REG_MMIO, 0x4839, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_1", REG_MMIO, 0x483A, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_0", REG_MMIO, 0x483B, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_1", REG_MMIO, 0x483C, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_0", REG_MMIO, 0x483D, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_1", REG_MMIO, 0x483E, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO0", REG_MMIO, 0x483F, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO1", REG_MMIO, 0x4840, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_0", REG_MMIO, 0x4841, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_1", REG_MMIO, 0x4842, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4843, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4844, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4845, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4846, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4847, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_2", REG_MMIO, 0x4848, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4849, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_STATUS", REG_MMIO, 0x484A, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x484B, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x484C, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x484D, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x484F, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_CNTL", REG_MMIO, 0x4850, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_EN_CNTL", REG_MMIO, 0x4851, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4852, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CNTL", REG_MMIO, 0x487C, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL_CHAR", REG_MMIO, 0x487D, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x487E, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x487F, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4880, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4881, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DEBUG", REG_MMIO, 0x4882, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL_BITS", REG_MMIO, 0x4883, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4884, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4886, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4887, NULL, 0, 0, 0 },
+	{ "mmDIG4_LVDS_DATA_CNTL", REG_MMIO, 0x488C, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_LANE_ENABLE", REG_MMIO, 0x488D, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL", REG_MMIO, 0x48A0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING1", REG_MMIO, 0x48A1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING2", REG_MMIO, 0x48A2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING3", REG_MMIO, 0x48A3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING4", REG_MMIO, 0x48A4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N", REG_MMIO, 0x48A5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x48A6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M", REG_MMIO, 0x48A7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x48A8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_TIMESTAMP", REG_MMIO, 0x48A9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_PACKET_CNTL", REG_MMIO, 0x48AA, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL1", REG_MMIO, 0x48AB, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_CNTL", REG_MMIO, 0x48C0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_PIXEL_FORMAT", REG_MMIO, 0x48C1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_CONFIG", REG_MMIO, 0x48C2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_STREAM_CNTL", REG_MMIO, 0x48C3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_STEER_FIFO", REG_MMIO, 0x48C4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_MISC", REG_MMIO, 0x48C5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x48C6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x48C7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x48C8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_TIMING", REG_MMIO, 0x48C9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_N", REG_MMIO, 0x48CA, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_M", REG_MMIO, 0x48CB, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x48CC, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_MSA_VBID", REG_MMIO, 0x48CD, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x48CE, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x48CF, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CNTL", REG_MMIO, 0x48D0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x48D1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM0", REG_MMIO, 0x48D2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x48D3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x48D4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_EN", REG_MMIO, 0x48D6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_CNTL", REG_MMIO, 0x48D7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_RESULT", REG_MMIO, 0x48D8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_COLORIMETRY", REG_MMIO, 0x48DA, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_MISC_CNTL", REG_MMIO, 0x48DB, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM2", REG_MMIO, 0x48DF, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM1", REG_MMIO, 0x48E0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_CNTL", REG_MMIO, 0x48E1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_UPDATE", REG_MMIO, 0x48E3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT0", REG_MMIO, 0x48E4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT1", REG_MMIO, 0x48E5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT2", REG_MMIO, 0x48E6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT_UPDATE", REG_MMIO, 0x48E7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_LINK_TIMING", REG_MMIO, 0x48E8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x48E9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x48EA, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x48EB, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x48FC, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_DATA", REG_MMIO, 0x48FD, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_ENABLE", REG_MMIO, 0x4900, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_CONTROL", REG_MMIO, 0x4901, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4902, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SWAP_CNTL", REG_MMIO, 0x4903, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4904, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4905, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PITCH", REG_MMIO, 0x4906, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4907, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4908, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4909, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x490A, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_START", REG_MMIO, 0x490B, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_START", REG_MMIO, 0x490C, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_END", REG_MMIO, 0x490D, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_END", REG_MMIO, 0x490E, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4910, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_UPDATE", REG_MMIO, 0x4911, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_CONTROL", REG_MMIO, 0x4912, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4913, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_CONTROL", REG_MMIO, 0x4914, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_STATUS", REG_MMIO, 0x4915, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4916, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4917, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4918, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4919, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_PITCH", REG_MMIO, 0x491A, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x491B, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_ENABLE", REG_MMIO, 0x491C, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_CONTROL1", REG_MMIO, 0x491D, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_CONTROL2", REG_MMIO, 0x491E, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SWAP_CNTL", REG_MMIO, 0x491F, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4920, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_PITCH", REG_MMIO, 0x4921, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4922, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4923, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4924, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_START", REG_MMIO, 0x4925, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_END", REG_MMIO, 0x4926, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_UPDATE", REG_MMIO, 0x4927, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_DFQ_CONTROL", REG_MMIO, 0x4929, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_DFQ_STATUS", REG_MMIO, 0x492A, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x492B, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x492C, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x492D, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x492E, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x492F, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4930, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4931, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4932, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4933, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4934, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_CONTROL", REG_MMIO, 0x4935, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C11_C12", REG_MMIO, 0x4936, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C13_C14", REG_MMIO, 0x4937, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C21_C22", REG_MMIO, 0x4938, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C23_C24", REG_MMIO, 0x4939, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C31_C32", REG_MMIO, 0x493A, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C33_C34", REG_MMIO, 0x493B, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_CONTROL", REG_MMIO, 0x493C, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C11_C12", REG_MMIO, 0x493D, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C13_C14", REG_MMIO, 0x493E, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C21_C22", REG_MMIO, 0x493F, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4940, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4941, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4942, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4943, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4944, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4945, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4946, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4947, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4948, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4949, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x494A, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x494B, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x494C, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x494D, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x494E, NULL, 0, 0, 0 },
+	{ "mmDCP5_DENORM_CONTROL", REG_MMIO, 0x4950, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_ROUND_CONTROL", REG_MMIO, 0x4951, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_CONTROL", REG_MMIO, 0x4953, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_ALPHA", REG_MMIO, 0x4954, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_RED", REG_MMIO, 0x4955, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_GREEN", REG_MMIO, 0x4956, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_BLUE", REG_MMIO, 0x4957, NULL, 0, 0, 0 },
+	{ "mmDCP5_DEGAMMA_CONTROL", REG_MMIO, 0x4958, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4959, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C11_C12", REG_MMIO, 0x495A, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C13_C14", REG_MMIO, 0x495B, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C21_C22", REG_MMIO, 0x495C, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C23_C24", REG_MMIO, 0x495D, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C31_C32", REG_MMIO, 0x495E, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C33_C34", REG_MMIO, 0x495F, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4960, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_RANDOM_SEEDS", REG_MMIO, 0x4961, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4965, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_CONTROL", REG_MMIO, 0x4966, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4967, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SIZE", REG_MMIO, 0x4968, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4969, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_POSITION", REG_MMIO, 0x496A, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_HOT_SPOT", REG_MMIO, 0x496B, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR1", REG_MMIO, 0x496C, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR2", REG_MMIO, 0x496D, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_UPDATE", REG_MMIO, 0x496E, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_MODE", REG_MMIO, 0x4978, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_INDEX", REG_MMIO, 0x4979, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_SEQ_COLOR", REG_MMIO, 0x497A, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_PWL_DATA", REG_MMIO, 0x497B, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_30_COLOR", REG_MMIO, 0x497C, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x497D, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x497E, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_AUTOFILL", REG_MMIO, 0x497F, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_CONTROL", REG_MMIO, 0x4980, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4981, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4982, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4983, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4984, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4985, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4986, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CONTROL", REG_MMIO, 0x4987, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_MASK", REG_MMIO, 0x4988, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CURRENT", REG_MMIO, 0x4989, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_LAST", REG_MMIO, 0x498B, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG", REG_MMIO, 0x498D, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_GSL_CONTROL", REG_MMIO, 0x4990, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4991, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4992, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4993, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4994, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4995, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4996, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4997, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG2", REG_MMIO, 0x4998, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4999, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CONTROL", REG_MMIO, 0x49A0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_INDEX", REG_MMIO, 0x49A1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_DATA", REG_MMIO, 0x49A2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x49A3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x49A4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x49A5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x49A6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x49A7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x49A8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x49A9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x49AA, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x49AB, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x49AC, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x49AD, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x49AE, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x49AF, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x49B0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x49B1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x49B2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x49B3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x49B4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x49B5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x49B6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x49B7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x49B8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x49B9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x49BA, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x49BB, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x49C8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG2", REG_MMIO, 0x49C9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SYNC_RESET_SEL", REG_MMIO, 0x49CA, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_MODE", REG_MMIO, 0x49D8, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x49D9, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x49DA, NULL, 0, 0, 0 },
+	{ "mmLB5_DC_MVP_LB_CONTROL", REG_MMIO, 0x49DB, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG", REG_MMIO, 0x49FC, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x49FE, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_DATA", REG_MMIO, 0x49FF, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4A30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4A31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4A33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4A34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4A35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4A36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4A37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4A38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4A39, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4A40, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4A41, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TAP_CONTROL", REG_MMIO, 0x4A43, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_CONTROL", REG_MMIO, 0x4A44, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_BYPASS_CONTROL", REG_MMIO, 0x4A45, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4A46, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4A47, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4A4A, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4A4B, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x4A4E, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x4A4F, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT", REG_MMIO, 0x4A50, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_UPDATE", REG_MMIO, 0x4A51, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4A53, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ALU_CONTROL", REG_MMIO, 0x4A54, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4A55, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x4A57, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_START", REG_MMIO, 0x4A5C, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_SIZE", REG_MMIO, 0x4A5D, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x4A5E, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x4A5F, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4A60, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4A61, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4A62, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4A63, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG2", REG_MMIO, 0x4A69, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG", REG_MMIO, 0x4A6A, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x4A6B, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x4A6C, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4A78, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4A79, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_WINDOW", REG_MMIO, 0x4A7A, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_CONTROL", REG_MMIO, 0x4A7B, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4A7C, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x4A7D, NULL, 0, 0, 0 },
+	{ "mmCRTC5_DCFE_DBG_SEL", REG_MMIO, 0x4A7E, NULL, 0, 0, 0 },
+	{ "mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x4A7F, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_TOTAL", REG_MMIO, 0x4A80, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_START_END", REG_MMIO, 0x4A81, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A", REG_MMIO, 0x4A82, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4A83, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B", REG_MMIO, 0x4A84, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4A85, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VBI_END", REG_MMIO, 0x4A86, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL", REG_MMIO, 0x4A87, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4A88, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4A89, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x4A8A, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x4A8B, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x4A8C, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_BLANK_START_END", REG_MMIO, 0x4A8D, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A", REG_MMIO, 0x4A8E, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x4A8F, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B", REG_MMIO, 0x4A90, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4A91, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4A92, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4A93, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_CNTL", REG_MMIO, 0x4A94, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4A95, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_CNTL", REG_MMIO, 0x4A96, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4A97, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4A98, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FLOW_CONTROL", REG_MMIO, 0x4A99, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x4A9B, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CONTROL", REG_MMIO, 0x4A9C, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_CONTROL", REG_MMIO, 0x4A9D, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x4A9E, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_STATUS", REG_MMIO, 0x4A9F, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x4AA0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x4AA1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR", REG_MMIO, 0x4AA2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS", REG_MMIO, 0x4AA3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_POSITION", REG_MMIO, 0x4AA4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x4AA5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x4AA6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x4AA7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x4AA8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_CONTROL", REG_MMIO, 0x4AA9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_RESET", REG_MMIO, 0x4AAA, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x4AAB, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x4AAC, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_STATUS", REG_MMIO, 0x4AAD, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_CONTROL", REG_MMIO, 0x4AAE, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x4AAF, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x4AB0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x4AB1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x4AB2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_START_LINE_CONTROL", REG_MMIO, 0x4AB3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x4AB4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_UPDATE_LOCK", REG_MMIO, 0x4AB5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x4AB6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x4AB7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x4ABA, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x4ABB, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x4ABC, NULL, 0, 0, 0 },
+	{ "mmCRTC5_MASTER_UPDATE_LOCK", REG_MMIO, 0x4ABD, NULL, 0, 0, 0 },
+	{ "mmCRTC5_MASTER_UPDATE_MODE", REG_MMIO, 0x4ABE, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x4ABF, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x4AC0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_STATUS", REG_MMIO, 0x4AC1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_EN", REG_MMIO, 0x4AC2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x4AC3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x4AC4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x4AC6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x4AC7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x4AEB, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x4AEC, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x4AED, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CONTROL", REG_MMIO, 0x4AEE, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x4AEF, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_DATA_0_1", REG_MMIO, 0x4AF0, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_DATA_2_3", REG_MMIO, 0x4AF1, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x4AF2, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x4AF3, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x4AF4, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x4AF5, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x4AF6, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x4AF7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x4AF8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_CNTL", REG_MMIO, 0x4AF9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_CNTL", REG_MMIO, 0x4AFA, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x4AFB, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x4AFC, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x4AFD, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x4AFE, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DEBUG_CNTL", REG_MMIO, 0x4AFF, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FE_CNTL", REG_MMIO, 0x4B00, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4B01, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4B02, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_CLOCK_PATTERN", REG_MMIO, 0x4B03, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_PATTERN", REG_MMIO, 0x4B04, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4B05, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4B08, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4B09, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FIFO_STATUS", REG_MMIO, 0x4B0A, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_CONTROL", REG_MMIO, 0x4B0C, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_STATUS", REG_MMIO, 0x4B0D, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4B0E, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4B0F, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4B10, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4B11, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4B12, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4B13, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4B14, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GC", REG_MMIO, 0x4B16, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4B17, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_0", REG_MMIO, 0x4B18, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_1", REG_MMIO, 0x4B19, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_2", REG_MMIO, 0x4B1A, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_3", REG_MMIO, 0x4B1B, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_4", REG_MMIO, 0x4B1C, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_0", REG_MMIO, 0x4B1D, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_1", REG_MMIO, 0x4B1E, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_2", REG_MMIO, 0x4B1F, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_3", REG_MMIO, 0x4B20, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO0", REG_MMIO, 0x4B21, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO1", REG_MMIO, 0x4B22, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO2", REG_MMIO, 0x4B23, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO3", REG_MMIO, 0x4B24, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO0", REG_MMIO, 0x4B25, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO1", REG_MMIO, 0x4B26, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_HDR", REG_MMIO, 0x4B27, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_0", REG_MMIO, 0x4B28, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_1", REG_MMIO, 0x4B29, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_2", REG_MMIO, 0x4B2A, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_3", REG_MMIO, 0x4B2B, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_4", REG_MMIO, 0x4B2C, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_5", REG_MMIO, 0x4B2D, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_6", REG_MMIO, 0x4B2E, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_7", REG_MMIO, 0x4B2F, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4B30, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_0", REG_MMIO, 0x4B37, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_1", REG_MMIO, 0x4B38, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_0", REG_MMIO, 0x4B39, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_1", REG_MMIO, 0x4B3A, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_0", REG_MMIO, 0x4B3B, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_1", REG_MMIO, 0x4B3C, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_0", REG_MMIO, 0x4B3D, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_1", REG_MMIO, 0x4B3E, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO0", REG_MMIO, 0x4B3F, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO1", REG_MMIO, 0x4B40, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_0", REG_MMIO, 0x4B41, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_1", REG_MMIO, 0x4B42, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4B43, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4B44, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4B45, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4B46, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4B47, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_2", REG_MMIO, 0x4B48, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4B49, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_STATUS", REG_MMIO, 0x4B4A, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4B4B, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4B4C, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4B4D, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4B4F, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_CNTL", REG_MMIO, 0x4B50, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_EN_CNTL", REG_MMIO, 0x4B51, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4B52, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CNTL", REG_MMIO, 0x4B7C, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL_CHAR", REG_MMIO, 0x4B7D, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4B7E, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4B7F, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4B80, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4B81, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DEBUG", REG_MMIO, 0x4B82, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL_BITS", REG_MMIO, 0x4B83, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4B84, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4B86, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4B87, NULL, 0, 0, 0 },
+	{ "mmDIG5_LVDS_DATA_CNTL", REG_MMIO, 0x4B8C, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_LANE_ENABLE", REG_MMIO, 0x4B8D, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL", REG_MMIO, 0x4BA0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING1", REG_MMIO, 0x4BA1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING2", REG_MMIO, 0x4BA2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING3", REG_MMIO, 0x4BA3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING4", REG_MMIO, 0x4BA4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N", REG_MMIO, 0x4BA5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4BA6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M", REG_MMIO, 0x4BA7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4BA8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_TIMESTAMP", REG_MMIO, 0x4BA9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4BAA, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL1", REG_MMIO, 0x4BAB, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_CNTL", REG_MMIO, 0x4BC0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_PIXEL_FORMAT", REG_MMIO, 0x4BC1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_CONFIG", REG_MMIO, 0x4BC2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_STREAM_CNTL", REG_MMIO, 0x4BC3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_STEER_FIFO", REG_MMIO, 0x4BC4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_MISC", REG_MMIO, 0x4BC5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4BC6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4BC7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4BC8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_TIMING", REG_MMIO, 0x4BC9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_N", REG_MMIO, 0x4BCA, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_M", REG_MMIO, 0x4BCB, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4BCC, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_MSA_VBID", REG_MMIO, 0x4BCD, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4BCE, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4BCF, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CNTL", REG_MMIO, 0x4BD0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4BD1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM0", REG_MMIO, 0x4BD2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4BD3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4BD4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_EN", REG_MMIO, 0x4BD6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4BD7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4BD8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_COLORIMETRY", REG_MMIO, 0x4BDA, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_MISC_CNTL", REG_MMIO, 0x4BDB, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM2", REG_MMIO, 0x4BDF, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM1", REG_MMIO, 0x4BE0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_CNTL", REG_MMIO, 0x4BE1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4BE3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT0", REG_MMIO, 0x4BE4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT1", REG_MMIO, 0x4BE5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT2", REG_MMIO, 0x4BE6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4BE7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_LINK_TIMING", REG_MMIO, 0x4BE8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4BE9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4BEA, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4BEB, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4BFC, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4BFD, NULL, 0, 0, 0 },
diff --git a/src/lib/ip/dce80.c b/src/lib/ip/dce80.c
new file mode 100644
index 0000000..41cb152
--- /dev/null
+++ b/src/lib/ip/dce80.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "dce80_bits.i"
+
+static const struct umr_reg dce80_registers[] = {
+#include "dce80_regs.i"
+};
+
+struct umr_ip_block *umr_create_dce80(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "dce80";
+	ip->no_regs = sizeof(dce80_registers)/sizeof(dce80_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(dce80_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, dce80_registers, sizeof(dce80_registers));
+	return ip;
+}
diff --git a/src/lib/ip/dce80_bits.i b/src/lib/ip/dce80_bits.i
new file mode 100644
index 0000000..a0a753e
--- /dev/null
+++ b/src/lib/ip/dce80_bits.i
@@ -0,0 +1,10063 @@
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[] = {
+};
+static struct umr_bitfield ixAZALIA_FIFO_SIZE_CONTROL[] = {
+	 { "MIN_FIFO_SIZE", 0, 6, &umr_bitfield_default },
+	 { "MAX_FIFO_SIZE", 8, 14, &umr_bitfield_default },
+	 { "MAX_LATENCY_SUPPORT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL0[] = {
+	 { "CRC_CHANNEL0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_CAPABILITIES[] = {
+	 { "SIXTY_FOUR_BIT_ADDRESS_SUPPORTED", 0, 0, &umr_bitfield_default },
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+	 { "NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED", 3, 7, &umr_bitfield_default },
+	 { "NUMBER_OF_INPUT_STREAMS_SUPPORTED", 8, 11, &umr_bitfield_default },
+	 { "NUMBER_OF_OUTPUT_STREAMS_SUPPORTED", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG_ID[] = {
+	 { "DCIO_DEBUG_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG_ID[] = {
+	 { "FMT_DEBUG_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR00[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ00[] = {
+	 { "SEQ_RST0B", 0, 0, &umr_bitfield_default },
+	 { "SEQ_RST1B", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[] = {
+	 { "PRODUCT_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_LATENCY_COUNTER_CONTROL[] = {
+	 { "AZALIA_LATENCY_COUNTER_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_PAYLOAD_CAPABILITY[] = {
+	 { "INPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL1[] = {
+	 { "CRC_CHANNEL1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR0[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG1[] = {
+	 { "DOUT_DCIO_MVP_DVOCNTL_A0_REG", 0, 1, &umr_bitfield_default },
+	 { "DOUT_DCIO_MVP_DVOCNTL_MASK_REG", 2, 3, &umr_bitfield_default },
+	 { "DOUT_DCIO_MVP_DVOCNTL_EN_REG", 4, 5, &umr_bitfield_default },
+	 { "DOUT_DCIO_MVP_DVOCNTL_A0", 6, 7, &umr_bitfield_default },
+	 { "DOUT_DCIO_MVP_DVOCNTL_SEL0", 8, 9, &umr_bitfield_default },
+	 { "DOUT_DCIO_MVP_DVOCNTL_EN", 10, 11, &umr_bitfield_default },
+	 { "DOUT_DCIO_MVP_DVOCLK_C", 12, 12, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_A0_REG", 13, 13, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_A0_PREMUX", 14, 14, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_A0", 15, 15, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_EN_REG", 16, 16, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVO_HSYNC_TRISTATE", 17, 17, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVO_CLK_TRISTATE", 18, 18, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_EN_PREMUX", 19, 19, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_EN", 20, 20, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_MUX", 21, 21, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_MASK_REG", 22, 22, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVO_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVO_VSYNC_TRISTATE", 24, 24, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVO_RATE_SEL", 25, 25, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_SEL0_PREMUX", 26, 26, &umr_bitfield_default },
+	 { "DOUT_DCIO_DVOCNTL1_SEL0", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG0[] = {
+	 { "FMT_DEBUG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR01[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ01[] = {
+	 { "SEQ_DOT8", 0, 0, &umr_bitfield_default },
+	 { "SEQ_SHIFT2", 2, 2, &umr_bitfield_default },
+	 { "SEQ_PCLKBY2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_SHIFT4", 4, 4, &umr_bitfield_default },
+	 { "SEQ_MAXBW", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_LOWER_BASE_ADDRESS[] = {
+	 { "CORB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "CORB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION11[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_A[] = {
+	 { "DP_AUX1_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG10[] = {
+	 { "DCIO_DIGC_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR10[] = {
+	 { "ATTR_GRPH_MODE", 0, 0, &umr_bitfield_default },
+	 { "ATTR_MONO_EN", 1, 1, &umr_bitfield_default },
+	 { "ATTR_LGRPH_EN", 2, 2, &umr_bitfield_default },
+	 { "ATTR_BLINK_EN", 3, 3, &umr_bitfield_default },
+	 { "ATTR_PANTOPONLY", 5, 5, &umr_bitfield_default },
+	 { "ATTR_PCLKBY2", 6, 6, &umr_bitfield_default },
+	 { "ATTR_CSEL_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT10[] = {
+	 { "V_SYNC_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_UPPER_BASE_ADDRESS[] = {
+	 { "CORB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION12[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_B[] = {
+	 { "DP_AUX1_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG11[] = {
+	 { "DCIO_DIGD_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR11[] = {
+	 { "ATTR_OVSC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT11[] = {
+	 { "V_SYNC_END", 0, 3, &umr_bitfield_default },
+	 { "V_INTR_CLR", 4, 4, &umr_bitfield_default },
+	 { "V_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "SEL5_REFRESH_CYC", 6, 6, &umr_bitfield_default },
+	 { "C0T7_WR_ONLY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DEBUG_CNTL[] = {
+	 { "DCCG_DS_DEBUG_COUNT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_VALUE", 4, 12, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_DS_DEBUG_COUNT_TRIG_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT_SRC_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DTO_INCR[] = {
+	 { "DCCG_DS_DTO_INCR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_DTO_MODULO[] = {
+	 { "DCCG_DS_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_CNTL[] = {
+	 { "DCCG_DS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DS_HW_CAL_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DCCG_DS_ENABLED_STATUS", 9, 9, &umr_bitfield_default },
+	 { "DCCG_DS_XTALIN_RATE_DIV", 16, 17, &umr_bitfield_default },
+	 { "DCCG_DS_JITTER_REMOVE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DCCG_DS_DELAY_XTAL_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DS_HW_CAL_INTERVAL[] = {
+	 { "DCCG_DS_HW_CAL_INTERVAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKG_CLOCK_ENABLE[] = {
+	 { "SYMCLKG_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKG_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKG_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPREFCLK_CNTL[] = {
+	 { "DPREFCLK_SRC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DPREFCLK_CLOCK_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCANIN_SOFT_RESET[] = {
+	 { "SCANIN_SOFT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEM_WRITE_PAGE_ADDR[] = {
+	 { "VGA_MEM_WRITE_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
+	 { "VGA_MEM_WRITE_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_WRITE_POINTER[] = {
+	 { "CORB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_READ_POINTER[] = {
+	 { "CORB_READ_POINTER", 0, 7, &umr_bitfield_default },
+	 { "CORB_READ_POINTER_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_C[] = {
+	 { "DP_AUX1_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG12[] = {
+	 { "DCIO_DIGE_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR12[] = {
+	 { "ATTR_MAP_EN", 0, 3, &umr_bitfield_default },
+	 { "ATTR_VSMUX", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT12[] = {
+	 { "V_DISP_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CNTL[] = {
+	 { "DCCG_GTC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_INCR[] = {
+	 { "DCCG_GTC_DTO_INCR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_DTO_MODULO[] = {
+	 { "DCCG_GTC_DTO_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GTC_CURRENT[] = {
+	 { "DCCG_GTC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENTIST_DISPCLK_CNTL[] = {
+	 { "DENTIST_DISPCLK_WDIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_RDIVIDER", 8, 14, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_MODE", 15, 16, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHGTOG", 17, 17, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_DONETOG", 18, 18, &umr_bitfield_default },
+	 { "DENTIST_DISPCLK_CHG_DONE", 19, 19, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHG_DONE", 20, 20, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_CHGTOG", 21, 21, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_DONETOG", 22, 22, &umr_bitfield_default },
+	 { "DENTIST_DPREFCLK_WDIVIDER", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CLK_ENABLE[] = {
+	 { "DACA_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DACB_CLK_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CLK_ENABLE[] = {
+	 { "DVO_CLK_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_SMU_INTERRUPT_CNTL[] = {
+	 { "DMCU_SMU_STATIC_SCREEN_INT", 0, 0, &umr_bitfield_default },
+	 { "DMCU_SMU_STATIC_SCREEN_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_CONTROL[] = {
+	 { "DISPLAY0_FORCE_VBI", 0, 0, &umr_bitfield_default },
+	 { "DISPLAY1_FORCE_VBI", 1, 1, &umr_bitfield_default },
+	 { "DISPLAY2_FORCE_VBI", 2, 2, &umr_bitfield_default },
+	 { "DISPLAY3_FORCE_VBI", 3, 3, &umr_bitfield_default },
+	 { "DISPLAY4_FORCE_VBI", 4, 4, &umr_bitfield_default },
+	 { "DISPLAY5_FORCE_VBI", 5, 5, &umr_bitfield_default },
+	 { "SMU_DC_INT_CLEAR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_INTERRUPT_CONTROL[] = {
+	 { "DC_SMU_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DC_SMU_INT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DC_SMU_INT_EVENT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEM_READ_PAGE_ADDR[] = {
+	 { "VGA_MEM_READ_PAGE0_ADDR", 0, 9, &umr_bitfield_default },
+	 { "VGA_MEM_READ_PAGE1_ADDR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION14[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_D[] = {
+	 { "DP_AUX1_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG13[] = {
+	 { "DCIO_DIGF_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_STATUS[] = {
+	 { "CORB_MEMORY_ERROR_INDICATION", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCORB_SIZE[] = {
+	 { "CORB_SIZE", 0, 1, &umr_bitfield_default },
+	 { "CORB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR13[] = {
+	 { "ATTR_PPAN", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT13[] = {
+	 { "DISP_PITCH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMILLISECOND_TIME_BASE_DIV[] = {
+	 { "MILLISECOND_TIME_BASE_DIV", 0, 16, &umr_bitfield_default },
+	 { "MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_FREQ_CHANGE_CNTL[] = {
+	 { "DISPCLK_STEP_DELAY", 0, 13, &umr_bitfield_default },
+	 { "DISPCLK_STEP_SIZE", 16, 19, &umr_bitfield_default },
+	 { "DISPCLK_FREQ_RAMP_DONE", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_MAX_ERRDET_CYCLES", 25, 27, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_RESET", 28, 28, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_STATE", 29, 29, &umr_bitfield_default },
+	 { "DCCG_FIFO_ERRDET_OVR_EN", 30, 30, &umr_bitfield_default },
+	 { "DISPCLK_CHG_FWD_CORR_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLIGHT_SLEEP_CNTL[] = {
+	 { "LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+	 { "MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_PERFMON_CNTL[] = {
+	 { "DCCG_PERF_DISPCLK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERF_DPREFCLK_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK1_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK2_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERF_PIXCLK0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERF_RUN", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_VSYNC", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERF_MODE_HSYNC", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERF_CRTC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCCG_PERF_XTALIN_PULSE_DIV", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_GATE_DISABLE_CNTL[] = {
+	 { "DISPCLK_DCCG_GATE_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_R_DCCG_GATE_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "SCLK_GATE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "DPREFCLK_GATE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "DACACLK_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "DACBCLK_GATE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DVOACLK_GATE_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "SYMCLKA_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SYMCLKB_GATE_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "SYMCLKC_GATE_DISABLE", 10, 10, &umr_bitfield_default },
+	 { "SYMCLKD_GATE_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "SYMCLKE_GATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "SYMCLKF_GATE_DISABLE", 13, 13, &umr_bitfield_default },
+	 { "SYMCLKG_GATE_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "PCLK_TV_GATE_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "AOMCLK0_GATE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "AOMCLK1_GATE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "AOMCLK2_GATE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_R_DCCG_RAMP_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "AUDIO_DTO2_CLK_GATE_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "DPREFCLK_GTC_GATE_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "DISPCLK_RAMP_DIV_ID", 24, 26, &umr_bitfield_default },
+	 { "SCLK_RAMP_DIV_ID", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "DISPCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DISPCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_DISPCLK_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCLK_CGTT_BLK_CTRL_REG[] = {
+	 { "SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_SCLK_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_CAC_STATUS[] = {
+	 { "CAC_STATUS_RDDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK1_RESYNC_CNTL[] = {
+	 { "PIXCLK1_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL1", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK2_RESYNC_CNTL[] = {
+	 { "PIXCLK2_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL2", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIXCLK0_RESYNC_CNTL[] = {
+	 { "PIXCLK0_RESYNC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCCG_DEEP_COLOR_CNTL0", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMICROSECOND_TIME_BASE_DIV[] = {
+	 { "MICROSECOND_TIME_BASE_DIV", 0, 6, &umr_bitfield_default },
+	 { "XTAL_REF_DIV", 8, 14, &umr_bitfield_default },
+	 { "XTAL_REF_SEL", 16, 16, &umr_bitfield_default },
+	 { "XTAL_REF_CLOCK_SOURCE_SEL", 17, 17, &umr_bitfield_default },
+	 { "MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPPLL_BG_CNTL[] = {
+	 { "DISPPLL_BG_PDN", 0, 0, &umr_bitfield_default },
+	 { "DISPPLL_BG_ADJ", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_SOFT_RESET[] = {
+	 { "DIGA_FE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DIGA_BE_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DIGB_FE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DIGB_BE_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIGC_FE_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DIGC_BE_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DIGD_FE_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "DIGD_BE_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "DIGE_FE_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "DIGE_BE_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "DIGF_FE_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "DIGF_BE_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "DIGG_FE_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "DIGG_BE_SOFT_RESET", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_DISP_CNTL_REG[] = {
+	 { "ALLOW_SR_ON_TRANS_REQ", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_LOWER_BASE_ADDRESS[] = {
+	 { "RIRB_LOWER_BASE_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "RIRB_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION15[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_E[] = {
+	 { "DP_AUX1_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG14[] = {
+	 { "DCIO_DIGG_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR14[] = {
+	 { "ATTR_CSEL1", 0, 1, &umr_bitfield_default },
+	 { "ATTR_CSEL2", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT14[] = {
+	 { "UNDRLN_LOC", 0, 4, &umr_bitfield_default },
+	 { "ADDR_CNT_BY4", 5, 5, &umr_bitfield_default },
+	 { "DOUBLE_WORD", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC0_PIXEL_RATE_CNTL[] = {
+	 { "CRTC0_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO0_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO0_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC0_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC0_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC0_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_PHASE[] = {
+	 { "DP_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO0_MODULO[] = {
+	 { "DP_DTO0_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC1_PIXEL_RATE_CNTL[] = {
+	 { "CRTC1_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO1_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO1_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC1_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_PHASE[] = {
+	 { "DP_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO1_MODULO[] = {
+	 { "DP_DTO1_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC2_PIXEL_RATE_CNTL[] = {
+	 { "CRTC2_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO2_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO2_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC2_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_PHASE[] = {
+	 { "DP_DTO2_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO2_MODULO[] = {
+	 { "DP_DTO2_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC3_PIXEL_RATE_CNTL[] = {
+	 { "CRTC3_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO3_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO3_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC3_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_PHASE[] = {
+	 { "DP_DTO3_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO3_MODULO[] = {
+	 { "DP_DTO3_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_UPPER_BASE_ADDRESS[] = {
+	 { "RIRB_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION16[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_F[] = {
+	 { "DP_AUX1_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG15[] = {
+	 { "DCIO_DEBUG15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT15[] = {
+	 { "V_BLANK_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC4_PIXEL_RATE_CNTL[] = {
+	 { "CRTC4_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO4_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO4_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC4_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_PHASE[] = {
+	 { "DP_DTO4_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO4_MODULO[] = {
+	 { "DP_DTO4_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC5_PIXEL_RATE_CNTL[] = {
+	 { "CRTC5_PIXEL_RATE_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "DP_DTO5_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_DTO5_DS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_ADD_PIXEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_DROP_PIXEL", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_FIFO_ERROR", 14, 15, &umr_bitfield_default },
+	 { "CRTC5_DISPOUT_ERROR_COUNT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_PHASE[] = {
+	 { "DP_DTO5_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DTO5_MODULO[] = {
+	 { "DP_DTO5_MODULO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE0_SOFT_RESET[] = {
+	 { "DCP0_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP0_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL0_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL0_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE1_SOFT_RESET[] = {
+	 { "DCP1_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP1_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL1_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL1_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC1_SOFT_RESET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE2_SOFT_RESET[] = {
+	 { "DCP2_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP2_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL2_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL2_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC2_SOFT_RESET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE3_SOFT_RESET[] = {
+	 { "DCP3_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP3_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL3_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL3_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC3_SOFT_RESET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE4_SOFT_RESET[] = {
+	 { "DCP4_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP4_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL4_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL4_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC4_SOFT_RESET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE5_SOFT_RESET[] = {
+	 { "DCP5_PIXPIPE_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DCP5_REQ_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SCL5_ALU_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "SCL5_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "CRTC5_SOFT_RESET", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_SOFT_RESET[] = {
+	 { "VGA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "VIP_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "MCIF_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "FBC_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "DMIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DMIF1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DMIF2_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "DMIF3_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "DMIF4_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "DMIF5_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "DMIFARB_SOFT_RESET", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_SOFT_RESET[] = {
+	 { "REFCLK_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "AUDIO_DTO2_CLK_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DPREFCLK_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "AMCLK0_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "AMCLK1_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "CASCADED_AMCLK0_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "CASCADED_AMCLK1_SOFT_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRESPONSE_INTERRUPT_COUNT[] = {
+	 { "N_RESPONSE_INTERRUPT_COUNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_WRITE_POINTER[] = {
+	 { "RIRB_WRITE_POINTER", 0, 7, &umr_bitfield_default },
+	 { "RIRB_WRITE_POINTER_RESET", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_G[] = {
+	 { "DP_AUX1_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT16[] = {
+	 { "V_BLANK_END", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKA_CLOCK_ENABLE[] = {
+	 { "SYMCLKA_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKA_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_CTRL[] = {
+	 { "RESET_UC", 0, 0, &umr_bitfield_default },
+	 { "IGNORE_PWRMGT", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_IRQ_TO_UC", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_XIRQ_TO_UC", 3, 3, &umr_bitfield_default },
+	 { "DMCU_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_STATUS[] = {
+	 { "UC_IN_RESET", 0, 0, &umr_bitfield_default },
+	 { "UC_IN_WAIT_MODE", 1, 1, &umr_bitfield_default },
+	 { "UC_IN_STOP_MODE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PC_START_ADDR[] = {
+	 { "PC_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "PC_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_START_ADDR[] = {
+	 { "FW_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_END_ADDR[] = {
+	 { "FW_END_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_END_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_ISR_START_ADDR[] = {
+	 { "FW_ISR_START_ADDR_LSB", 0, 7, &umr_bitfield_default },
+	 { "FW_ISR_START_ADDR_MSB", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_HI[] = {
+	 { "FW_CHECKSUM_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CS_LO[] = {
+	 { "FW_CHECKSUM_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_RAM_ACCESS_CTRL[] = {
+	 { "ERAM_WR_ADDR_AUTO_INC", 0, 0, &umr_bitfield_default },
+	 { "ERAM_RD_ADDR_AUTO_INC", 1, 1, &umr_bitfield_default },
+	 { "IRAM_WR_ADDR_AUTO_INC", 2, 2, &umr_bitfield_default },
+	 { "IRAM_RD_ADDR_AUTO_INC", 3, 3, &umr_bitfield_default },
+	 { "ERAM_HOST_ACCESS_EN", 4, 4, &umr_bitfield_default },
+	 { "IRAM_HOST_ACCESS_EN", 5, 5, &umr_bitfield_default },
+	 { "UC_RST_RELEASE_DELAY_CNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_CTRL[] = {
+	 { "ERAM_WR_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_WR_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_WR_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_WR_DATA[] = {
+	 { "ERAM_WR_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_CTRL[] = {
+	 { "ERAM_RD_ADDR", 0, 15, &umr_bitfield_default },
+	 { "ERAM_RD_BE", 16, 19, &umr_bitfield_default },
+	 { "ERAM_RD_BYTE_MODE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_ERAM_RD_DATA[] = {
+	 { "ERAM_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_CTRL[] = {
+	 { "IRAM_WR_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_WR_DATA[] = {
+	 { "IRAM_WR_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_CTRL[] = {
+	 { "IRAM_RD_ADDR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKB_CLOCK_ENABLE[] = {
+	 { "SYMCLKB_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKB_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_IRAM_RD_DATA[] = {
+	 { "IRAM_RD_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_EVENT_TRIGGER[] = {
+	 { "GEN_SW_INT_TO_UC", 0, 0, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CODE", 16, 22, &umr_bitfield_default },
+	 { "GEN_UC_INTERNAL_INT_TO_HOST", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_INTERNAL_INT_STATUS[] = {
+	 { "UC_INT_IRQ_N_PIN", 0, 0, &umr_bitfield_default },
+	 { "UC_INT_XIRQ_N_PIN", 1, 1, &umr_bitfield_default },
+	 { "UC_INT_SOFTWARE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "UC_INT_ILLEGAL_OPCODE_TRAP", 3, 3, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_4", 4, 4, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_3", 5, 5, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_2", 6, 6, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OUTPUT_COMPARE_1", 7, 7, &umr_bitfield_default },
+	 { "UC_INT_TIMER_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "UC_INT_REAL_TIME_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5", 10, 10, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_3", 11, 11, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_2", 12, 12, &umr_bitfield_default },
+	 { "UC_INT_TIMER_INPUT_CAPTURE_1", 13, 13, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE", 14, 14, &umr_bitfield_default },
+	 { "UC_INT_PULSE_ACCUMULATOR_OVERFLOW", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_SS_INTERRUPT_CNTL_STATUS[] = {
+	 { "STATIC_SCREEN1_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "STATIC_SCREEN1_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "STATIC_SCREEN2_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "STATIC_SCREEN3_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_STATUS", 19, 19, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "STATIC_SCREEN4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_STATUS", 21, 21, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "STATIC_SCREEN5_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "STATIC_SCREEN6_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_STATUS[] = {
+	 { "ABM1_HG_READY_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "SCP_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "VBLANK1_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "VBLANK2_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "VBLANK3_INT_CLEAR", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_OCCURRED", 27, 27, &umr_bitfield_default },
+	 { "VBLANK4_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_OCCURRED", 28, 28, &umr_bitfield_default },
+	 { "VBLANK5_INT_CLEAR", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_OCCURRED", 29, 29, &umr_bitfield_default },
+	 { "VBLANK6_INT_CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_HOST_EN_MASK[] = {
+	 { "ABM1_HG_READY_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "SCP_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "UC_INTERNAL_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "UC_REG_RD_TIMEOUT_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_EN_MASK[] = {
+	 { "ABM1_HG_READY_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_TO_UC_EN", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_TO_UC_EN", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_TO_UC_EN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[] = {
+	 { "ABM1_HG_READY_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "MCP_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "EXTERNAL_SW_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "VBLANK1_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "VBLANK2_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "VBLANK3_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+	 { "VBLANK4_INT_XIRQ_IRQ_SEL", 27, 27, &umr_bitfield_default },
+	 { "VBLANK5_INT_XIRQ_IRQ_SEL", 28, 28, &umr_bitfield_default },
+	 { "VBLANK6_INT_XIRQ_IRQ_SEL", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DMCU_SCRATCH[] = {
+	 { "DMCU_SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_INT_CNT[] = {
+	 { "DMCU_ABM1_HG_READY_INT_CNT", 0, 7, &umr_bitfield_default },
+	 { "DMCU_ABM1_LS_READY_INT_CNT", 8, 15, &umr_bitfield_default },
+	 { "DMCU_ABM1_BL_UPDATE_INT_CNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[] = {
+	 { "DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS", 0, 1, &umr_bitfield_default },
+	 { "DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_UC_CLK_GATING_CNTL[] = {
+	 { "UC_IRAM_RD_DELAY", 0, 2, &umr_bitfield_default },
+	 { "UC_ERAM_RD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "UC_RBBM_RD_CLK_GATING_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG1[] = {
+	 { "MASTER_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG2[] = {
+	 { "MASTER_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_DATA_REG3[] = {
+	 { "MASTER_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CMD_REG[] = {
+	 { "MASTER_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "MASTER_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKC_CLOCK_ENABLE[] = {
+	 { "SYMCLKC_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKC_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_COMM_CNTL_REG[] = {
+	 { "MASTER_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG1[] = {
+	 { "SLAVE_COMM_DATA_REG1_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG1_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG2[] = {
+	 { "SLAVE_COMM_DATA_REG2_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG2_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_DATA_REG3[] = {
+	 { "SLAVE_COMM_DATA_REG3_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_DATA_REG3_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CMD_REG[] = {
+	 { "SLAVE_COMM_CMD_REG_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SLAVE_COMM_CMD_REG_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSLAVE_COMM_CNTL_REG[] = {
+	 { "SLAVE_COMM_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "COMM_PORT_MSG_TO_HOST_IN_PROGRESS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_INDEX[] = {
+	 { "DMCU_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMCU_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_TEST_DEBUG_DATA[] = {
+	 { "DMCU_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_AMBIENT_LIGHT_LEVEL[] = {
+	 { "BL1_PWM_AMBIENT_LIGHT_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_USER_LEVEL[] = {
+	 { "BL1_PWM_USER_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_TARGET_ABM_LEVEL[] = {
+	 { "BL1_PWM_TARGET_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_CURRENT_ABM_LEVEL[] = {
+	 { "BL1_PWM_CURRENT_ABM_LEVEL", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_FINAL_DUTY_CYCLE[] = {
+	 { "BL1_PWM_FINAL_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_MINIMUM_DUTY_CYCLE[] = {
+	 { "BL1_PWM_MINIMUM_DUTY_CYCLE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_ABM_CNTL[] = {
+	 { "BL1_PWM_USE_ABM_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_USE_AMBIENT_LEVEL_EN", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN", 2, 2, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN", 3, 3, &umr_bitfield_default },
+	 { "BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[] = {
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKD_CLOCK_ENABLE[] = {
+	 { "SYMCLKD_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKD_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL1_PWM_GRP2_REG_LOCK[] = {
+	 { "BL1_PWM_GRP2_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_CNTL[] = {
+	 { "ABM1_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_SOURCE_SELECT", 8, 10, &umr_bitfield_default },
+	 { "ABM1_BLANK_MODE_SUPPORT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_IPCSC_COEFF_SEL[] = {
+	 { "ABM1_IPCSC_COEFF_SEL_B", 0, 3, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_G", 8, 11, &umr_bitfield_default },
+	 { "ABM1_IPCSC_COEFF_SEL_R", 16, 19, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_0[] = {
+	 { "ABM1_ACE_SLOPE_0", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_0", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_1[] = {
+	 { "ABM1_ACE_SLOPE_1", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_1", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_2[] = {
+	 { "ABM1_ACE_SLOPE_2", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_2", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_3[] = {
+	 { "ABM1_ACE_SLOPE_3", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_3", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_OFFSET_SLOPE_4[] = {
+	 { "ABM1_ACE_SLOPE_4", 0, 14, &umr_bitfield_default },
+	 { "ABM1_ACE_OFFSET_4", 16, 26, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_12[] = {
+	 { "ABM1_ACE_THRES_1", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_2", 16, 25, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKE_CLOCK_ENABLE[] = {
+	 { "SYMCLKE_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKE_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_THRES_34[] = {
+	 { "ABM1_ACE_THRES_3", 0, 9, &umr_bitfield_default },
+	 { "ABM1_ACE_THRES_4", 16, 25, &umr_bitfield_default },
+	 { "ABM1_ACE_IGNORE_MASTER_LOCK_EN", 28, 28, &umr_bitfield_default },
+	 { "ABM1_ACE_READBACK_DB_REG_VALUE_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_ACE_DBUF_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_ACE_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_ACE_CNTL_MISC[] = {
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME", 0, 0, &umr_bitfield_default },
+	 { "ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_DEBUG_MISC[] = {
+	 { "ABM1_HG_FORCE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_FORCE_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "ABM1_BL_FORCE_INTERRUPT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HGLS_REG_READ_PROGRESS[] = {
+	 { "ABM1_HG_REG_READ_IN_PROGRESS", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_IN_PROGRESS", 1, 1, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_IN_PROGRESS", 2, 2, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME", 8, 8, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME", 9, 9, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME", 10, 10, &umr_bitfield_default },
+	 { "ABM1_HG_REG_READ_MISSED_FRAME_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "ABM1_LS_REG_READ_MISSED_FRAME_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "ABM1_BL_REG_READ_MISSED_FRAME_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_MISC_CTRL[] = {
+	 { "ABM1_HG_NUM_OF_BINS_SEL", 0, 1, &umr_bitfield_default },
+	 { "ABM1_HG_VMAX_SEL", 8, 8, &umr_bitfield_default },
+	 { "ABM1_HG_FINE_MODE_BIN_SEL", 12, 12, &umr_bitfield_default },
+	 { "ABM1_HG_BIN_BITWIDTH_SIZE_SEL", 16, 17, &umr_bitfield_default },
+	 { "ABM1_OVR_SCAN_PIXEL_PROCESS_EN", 20, 20, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN", 23, 23, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL", 24, 26, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START", 28, 28, &umr_bitfield_default },
+	 { "ABM1_HGLS_IGNORE_MASTER_LOCK_EN", 29, 29, &umr_bitfield_default },
+	 { "ABM1_DBUF_HGLS_REG_UPDATE_PENDING", 30, 30, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SUM_OF_LUMA[] = {
+	 { "ABM1_LS_SUM_OF_LUMA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_MIN_LUMA", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_LUMA", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[] = {
+	 { "ABM1_LS_FILTERED_MIN_LUMA", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_FILTERED_MAX_LUMA", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_PIXEL_COUNT[] = {
+	 { "ABM1_LS_PIXEL_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYMCLKF_CLOCK_ENABLE[] = {
+	 { "SYMCLKF_CLOCK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_EN", 4, 4, &umr_bitfield_default },
+	 { "SYMCLKF_FE_FORCE_SRC", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_OVR_SCAN_BIN[] = {
+	 { "ABM1_LS_OVR_SCAN_BIN", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_THRES", 0, 9, &umr_bitfield_default },
+	 { "ABM1_LS_MAX_PIXEL_VALUE_THRES", 16, 25, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MIN_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[] = {
+	 { "ABM1_LS_MAX_PIXEL_VALUE_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_SAMPLE_RATE[] = {
+	 { "ABM1_HG_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_HG_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_LS_SAMPLE_RATE[] = {
+	 { "ABM1_LS_SAMPLE_RATE_COUNT_EN", 0, 0, &umr_bitfield_default },
+	 { "ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER", 1, 1, &umr_bitfield_default },
+	 { "ABM1_LS_SAMPLE_RATE_FRAME_COUNT", 8, 15, &umr_bitfield_default },
+	 { "ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET", 16, 23, &umr_bitfield_default },
+	 { "ABM1_HGLS_REG_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[] = {
+	 { "ABM1_HG_BIN_1_32_SHIFT_FLAG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_1_8_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_9_16_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_17_24_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[] = {
+	 { "ABM1_HG_BIN_25_32_SHIFT_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_1[] = {
+	 { "ABM1_HG_RESULT_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_2[] = {
+	 { "ABM1_HG_RESULT_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_3[] = {
+	 { "ABM1_HG_RESULT_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_4[] = {
+	 { "ABM1_HG_RESULT_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_5[] = {
+	 { "ABM1_HG_RESULT_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_SOFT_RESET[] = {
+	 { "DSYNCA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DSYNCB_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DSYNCC_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "DSYNCD_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "DSYNCE_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "DSYNCF_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "DSYNCG_SOFT_RESET", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_6[] = {
+	 { "ABM1_HG_RESULT_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_7[] = {
+	 { "ABM1_HG_RESULT_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_8[] = {
+	 { "ABM1_HG_RESULT_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_9[] = {
+	 { "ABM1_HG_RESULT_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_10[] = {
+	 { "ABM1_HG_RESULT_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_11[] = {
+	 { "ABM1_HG_RESULT_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_12[] = {
+	 { "ABM1_HG_RESULT_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_13[] = {
+	 { "ABM1_HG_RESULT_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_14[] = {
+	 { "ABM1_HG_RESULT_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_15[] = {
+	 { "ABM1_HG_RESULT_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_16[] = {
+	 { "ABM1_HG_RESULT_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_17[] = {
+	 { "ABM1_HG_RESULT_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_18[] = {
+	 { "ABM1_HG_RESULT_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_19[] = {
+	 { "ABM1_HG_RESULT_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_20[] = {
+	 { "ABM1_HG_RESULT_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_21[] = {
+	 { "ABM1_HG_RESULT_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_SOFT_RESET[] = {
+	 { "DACA_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "DACB_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "SOFT_RESET_DVO", 2, 2, &umr_bitfield_default },
+	 { "DVO_ENABLE_RST", 3, 3, &umr_bitfield_default },
+	 { "I2S0_SPDIF0_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "I2S1_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "SPDIF1_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "FMT0_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "FMT1_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FMT2_SOFT_RESET", 18, 18, &umr_bitfield_default },
+	 { "FMT3_SOFT_RESET", 19, 19, &umr_bitfield_default },
+	 { "FMT4_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "FMT5_SOFT_RESET", 21, 21, &umr_bitfield_default },
+	 { "MVP_SOFT_RESET", 24, 24, &umr_bitfield_default },
+	 { "ABM_SOFT_RESET", 25, 25, &umr_bitfield_default },
+	 { "TVOUT_SOFT_RESET", 26, 26, &umr_bitfield_default },
+	 { "DVO_SOFT_RESET", 27, 27, &umr_bitfield_default },
+	 { "SRBM_SOFT_RESET_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "DACA_CFG_IF_SOFT_RESET", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_22[] = {
+	 { "ABM1_HG_RESULT_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_23[] = {
+	 { "ABM1_HG_RESULT_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_HG_RESULT_24[] = {
+	 { "ABM1_HG_RESULT_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKD_CNTL[] = {
+	 { "DVOACLKD_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKD_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKD_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKD_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKD_IN_PHASE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL1[] = {
+	 { "MVP_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_MIXER_MODE", 4, 6, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK", 9, 9, &umr_bitfield_default },
+	 { "MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE", 10, 10, &umr_bitfield_default },
+	 { "MVP_RATE_CONTROL", 12, 12, &umr_bitfield_default },
+	 { "MVP_CHANNEL_CONTROL", 16, 16, &umr_bitfield_default },
+	 { "MVP_GPU_CHAIN_LOCATION", 20, 21, &umr_bitfield_default },
+	 { "MVP_DISABLE_MSB_EXPAND", 24, 24, &umr_bitfield_default },
+	 { "MVP_30BPP_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_A", 30, 30, &umr_bitfield_default },
+	 { "MVP_TERMINATION_CNTL_B", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL2[] = {
+	 { "MVP_MUX_DE_DVOCNTL0_SEL", 0, 0, &umr_bitfield_default },
+	 { "MVP_MUX_DE_DVOCNTL2_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_MUXA_CLK_SEL", 8, 8, &umr_bitfield_default },
+	 { "MVP_MUXB_CLK_SEL", 12, 12, &umr_bitfield_default },
+	 { "MVP_DVOCNTL_MUX", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_OUT_EN", 24, 24, &umr_bitfield_default },
+	 { "MVP_SWAP_AB_IN_DC_DDR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_CONTROL[] = {
+	 { "MVP_STOP_SLAVE_WM", 0, 7, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_WM", 8, 15, &umr_bitfield_default },
+	 { "MVP_PAUSE_SLAVE_CNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FIFO_STATUS[] = {
+	 { "MVP_FIFO_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "MVP_FIFO_OVERFLOW_ACK", 16, 16, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW", 20, 20, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "MVP_FIFO_UNDERFLOW_ACK", 28, 28, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_MASK", 30, 30, &umr_bitfield_default },
+	 { "MVP_FIFO_ERROR_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_SLAVE_STATUS[] = {
+	 { "MVP_SLAVE_PIXELS_PER_LINE_RCVED", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINES_PER_FRAME_RCVED", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_INBAND_CNTL_CAP[] = {
+	 { "MVP_IGNOR_INBAND_CNTL", 0, 0, &umr_bitfield_default },
+	 { "MVP_PASSING_INBAND_CNTL_EN", 4, 4, &umr_bitfield_default },
+	 { "MVP_INBAND_CNTL_CHAR_CAP", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_BLACK_KEYER[] = {
+	 { "MVP_BLACK_KEYER_R", 0, 9, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_G", 10, 19, &umr_bitfield_default },
+	 { "MVP_BLACK_KEYER_B", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_CNTL[] = {
+	 { "MVP_CRC_BLUE_MASK", 0, 7, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_MASK", 8, 15, &umr_bitfield_default },
+	 { "MVP_CRC_RED_MASK", 16, 23, &umr_bitfield_default },
+	 { "MVP_CRC_EN", 28, 28, &umr_bitfield_default },
+	 { "MVP_CRC_CONT_EN", 29, 29, &umr_bitfield_default },
+	 { "MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_BLUE_GREEN[] = {
+	 { "MVP_CRC_BLUE_RESULT", 0, 15, &umr_bitfield_default },
+	 { "MVP_CRC_GREEN_RESULT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CRC_RESULT_RED[] = {
+	 { "MVP_CRC_RED_RESULT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_CONTROL3[] = {
+	 { "MVP_RESET_IN_BETWEEN_FRAMES", 0, 0, &umr_bitfield_default },
+	 { "MVP_DDR_SC_AB_SEL", 4, 4, &umr_bitfield_default },
+	 { "MVP_DDR_SC_B_START_MODE", 8, 8, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_CASCADE_EN", 20, 20, &umr_bitfield_default },
+	 { "MVP_SWAP_48BIT_EN", 24, 24, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_CAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL1[] = {
+	 { "MVP_SLAVE_PIXEL_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_LINE_ERROR_CNT", 16, 28, &umr_bitfield_default },
+	 { "MVP_SLAVE_DATA_CHK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_RECEIVE_CNT_CNTL2[] = {
+	 { "MVP_SLAVE_FRAME_ERROR_CNT", 0, 12, &umr_bitfield_default },
+	 { "MVP_SLAVE_FRAME_ERROR_CNT_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_INDEX[] = {
+	 { "MVP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MVP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_TEST_DEBUG_DATA[] = {
+	 { "MVP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_DEBUG[] = {
+	 { "MVP_SWAP_LOCK_IN_EN", 0, 0, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_EN", 1, 1, &umr_bitfield_default },
+	 { "MVP_SWAP_LOCK_IN_SEL", 2, 2, &umr_bitfield_default },
+	 { "MVP_FLOW_CONTROL_IN_SEL", 3, 3, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP", 4, 4, &umr_bitfield_default },
+	 { "MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP", 5, 5, &umr_bitfield_default },
+	 { "MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR", 6, 6, &umr_bitfield_default },
+	 { "MVP_DIS_READ_POINTER_RESET_DELAY", 7, 7, &umr_bitfield_default },
+	 { "MVP_DEBUG_BITS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKC_MVP_CNTL[] = {
+	 { "DVOACLKC_MVP_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_IN_PHASE", 18, 18, &umr_bitfield_default },
+	 { "DVOACLKC_MVP_SKEW_PHASE_OVERRIDE", 20, 20, &umr_bitfield_default },
+	 { "MVP_CLK_A_SRC_SEL", 24, 25, &umr_bitfield_default },
+	 { "MVP_CLK_B_SRC_SEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_OVERSCAN_PIXEL_VALUE[] = {
+	 { "ABM1_OVERSCAN_R_PIXEL_VALUE", 0, 9, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_G_PIXEL_VALUE", 10, 19, &umr_bitfield_default },
+	 { "ABM1_OVERSCAN_B_PIXEL_VALUE", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_ABM1_BL_MASTER_LOCK[] = {
+	 { "ABM1_BL_MASTER_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_INDEX[] = {
+	 { "ABM_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "ABM_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmABM_TEST_DEBUG_DATA[] = {
+	 { "ABM_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVOACLKC_CNTL[] = {
+	 { "DVOACLKC_FINE_SKEW_CNTL", 0, 2, &umr_bitfield_default },
+	 { "DVOACLKC_COARSE_SKEW_CNTL", 8, 12, &umr_bitfield_default },
+	 { "DVOACLKC_FINE_ADJUST_EN", 16, 16, &umr_bitfield_default },
+	 { "DVOACLKC_COARSE_ADJUST_EN", 17, 17, &umr_bitfield_default },
+	 { "DVOACLKC_IN_PHASE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO_SOURCE[] = {
+	 { "DCCG_AUDIO_DTO0_SOURCE_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_SOURCE_SEL", 12, 13, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_CLOCK_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO2_USE_512FBR_DTO", 20, 20, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO0_USE_512FBR_DTO", 24, 24, &umr_bitfield_default },
+	 { "DCCG_AUDIO_DTO1_USE_512FBR_DTO", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_PHASE[] = {
+	 { "DCCG_AUDIO_DTO0_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO0_MODULE[] = {
+	 { "DCCG_AUDIO_DTO0_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CNTL[] = {
+	 { "FBC_GRPH_COMP_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_SRC_SEL", 1, 3, &umr_bitfield_default },
+	 { "FBC_COHERENCY_MODE", 16, 17, &umr_bitfield_default },
+	 { "FBC_SOFT_COMPRESS_EN", 25, 25, &umr_bitfield_default },
+	 { "FBC_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_MASK[] = {
+	 { "FBC_IDLE_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IDLE_FORCE_CLEAR_MASK[] = {
+	 { "FBC_IDLE_FORCE_CLEAR_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_START_STOP_DELAY[] = {
+	 { "FBC_DECOMP_START_DELAY", 0, 4, &umr_bitfield_default },
+	 { "FBC_DECOMP_STOP_DELAY", 7, 7, &umr_bitfield_default },
+	 { "FBC_COMP_START_DELAY", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_CNTL[] = {
+	 { "FBC_MIN_COMPRESSION", 0, 3, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO08_EN", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEPTH_MONO16_EN", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB04_EN", 18, 18, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB08_EN", 19, 19, &umr_bitfield_default },
+	 { "FBC_DEPTH_RGB16_EN", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_COMP_MODE[] = {
+	 { "FBC_RLE_EN", 0, 0, &umr_bitfield_default },
+	 { "FBC_DPCM4_RGB_EN", 8, 8, &umr_bitfield_default },
+	 { "FBC_DPCM8_RGB_EN", 9, 9, &umr_bitfield_default },
+	 { "FBC_DPCM4_YUV_EN", 10, 10, &umr_bitfield_default },
+	 { "FBC_DPCM8_YUV_EN", 11, 11, &umr_bitfield_default },
+	 { "FBC_IND_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG0[] = {
+	 { "FBC_PERF_MUX0", 0, 7, &umr_bitfield_default },
+	 { "FBC_PERF_MUX1", 8, 15, &umr_bitfield_default },
+	 { "FBC_COMP_WAKE_DIS", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG0", 17, 23, &umr_bitfield_default },
+	 { "FBC_DEBUG_MUX", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG1[] = {
+	 { "FBC_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG2[] = {
+	 { "FBC_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT0[] = {
+	 { "FBC_IND_LUT0", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT1[] = {
+	 { "FBC_IND_LUT1", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT2[] = {
+	 { "FBC_IND_LUT2", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT3[] = {
+	 { "FBC_IND_LUT3", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT4[] = {
+	 { "FBC_IND_LUT4", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT5[] = {
+	 { "FBC_IND_LUT5", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT6[] = {
+	 { "FBC_IND_LUT6", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_PHASE[] = {
+	 { "DCCG_AUDIO_DTO1_PHASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT7[] = {
+	 { "FBC_IND_LUT7", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT8[] = {
+	 { "FBC_IND_LUT8", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT9[] = {
+	 { "FBC_IND_LUT9", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT10[] = {
+	 { "FBC_IND_LUT10", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT11[] = {
+	 { "FBC_IND_LUT11", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT12[] = {
+	 { "FBC_IND_LUT12", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT13[] = {
+	 { "FBC_IND_LUT13", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT14[] = {
+	 { "FBC_IND_LUT14", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_IND_LUT15[] = {
+	 { "FBC_IND_LUT15", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_01[] = {
+	 { "FBC_CSM_REGION_OFFSET_0", 0, 9, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CSM_REGION_OFFSET_23[] = {
+	 { "FBC_CSM_REGION_OFFSET_2", 0, 9, &umr_bitfield_default },
+	 { "FBC_CSM_REGION_OFFSET_3", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_CLIENT_REGION_MASK[] = {
+	 { "FBC_MEMORY_REGION_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_COMP[] = {
+	 { "FBC_COMP_SWAP", 0, 1, &umr_bitfield_default },
+	 { "FBC_COMP_RSIZE", 3, 3, &umr_bitfield_default },
+	 { "FBC_COMP_BUSY_HYSTERESIS", 4, 7, &umr_bitfield_default },
+	 { "FBC_COMP_CLK_CNTL", 8, 9, &umr_bitfield_default },
+	 { "FBC_COMP_PRIVILEGED_ACCESS_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "FBC_COMP_ADDRESS_TRANSLATION_ENABLE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR[] = {
+	 { "FBC_DEBUG_CSR_ADDR", 0, 9, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_WR_DATA", 16, 16, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_RD_DATA", 17, 17, &umr_bitfield_default },
+	 { "FBC_DEBUG_CSR_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA[] = {
+	 { "FBC_DEBUG_CSR_RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA[] = {
+	 { "FBC_DEBUG_CSR_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_AUDIO_DTO1_MODULE[] = {
+	 { "DCCG_AUDIO_DTO1_MODULE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_MISC[] = {
+	 { "FBC_DECOMPRESS_ERROR", 0, 1, &umr_bitfield_default },
+	 { "FBC_STOP_ON_ERROR", 2, 2, &umr_bitfield_default },
+	 { "FBC_INVALIDATE_ON_ERROR", 3, 3, &umr_bitfield_default },
+	 { "FBC_ERROR_PIXEL", 4, 7, &umr_bitfield_default },
+	 { "FBC_DIVIDE_X", 8, 9, &umr_bitfield_default },
+	 { "FBC_DIVIDE_Y", 10, 10, &umr_bitfield_default },
+	 { "FBC_RSM_WRITE_VALUE", 11, 11, &umr_bitfield_default },
+	 { "FBC_RSM_UNCOMP_DATA_IMMEDIATELY", 12, 12, &umr_bitfield_default },
+	 { "FBC_DECOMPRESS_ERROR_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "FBC_RESET_AT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FBC_RESET_AT_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "FBC_SLOW_REQ_INTERVAL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_STATUS[] = {
+	 { "FBC_ENABLE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_INDEX[] = {
+	 { "FBC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FBC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_TEST_DEBUG_DATA[] = {
+	 { "FBC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_RDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_RDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFBC_DEBUG_CSR_WDATA_HI[] = {
+	 { "FBC_DEBUG_CSR_WDATA_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_H[] = {
+	 { "DP_AUX1_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_CONTROL[] = {
+	 { "RESPONSE_INTERRUPT_CONTROL", 0, 0, &umr_bitfield_default },
+	 { "RIRB_DMA_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "RESPONSE_OVERRUN_INTERRUPT_CONTROL", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_STATUS[] = {
+	 { "RESPONSE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "RESPONSE_OVERRUN_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRIRB_SIZE[] = {
+	 { "RIRB_SIZE", 0, 1, &umr_bitfield_default },
+	 { "RIRB_SIZE_CAPABILITY", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT17[] = {
+	 { "RA0_AS_A13B", 0, 0, &umr_bitfield_default },
+	 { "RA1_AS_A14B", 1, 1, &umr_bitfield_default },
+	 { "VCOUNT_BY2", 2, 2, &umr_bitfield_default },
+	 { "ADDR_CNT_BY2", 3, 3, &umr_bitfield_default },
+	 { "WRAP_A15TOA0", 5, 5, &umr_bitfield_default },
+	 { "BYTE_MODE", 6, 6, &umr_bitfield_default },
+	 { "CRTC_SYNC_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFCOUNTER_CNTL[] = {
+	 { "PERFCOUNTER_EVENT_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERFCOUNTER_INC_MODE", 12, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_HW_CNTL_SEL", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_RUNEN_MODE", 15, 15, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTOFF_SEL", 16, 20, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTOFF_START_DIS", 21, 21, &umr_bitfield_default },
+	 { "PERFCOUNTER_RESTART_EN", 22, 22, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT_EN", 23, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_OFF_MASK", 24, 24, &umr_bitfield_default },
+	 { "PERFCOUNTER_ACTIVE", 25, 25, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNTL_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_REF_DIV[] = {
+	 { "PLL_REF_DIV", 0, 9, &umr_bitfield_default },
+	 { "PLL_CALIBRATION_REF_DIV", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_FB_DIV[] = {
+	 { "PLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "PLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "PLL_FB_DIV", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_POST_DIV[] = {
+	 { "PLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "PLL_POST_DIV1P5_DISPCLK", 7, 7, &umr_bitfield_default },
+	 { "PLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "PLL_POST_DIV1P5_DPREFCLK", 15, 15, &umr_bitfield_default },
+	 { "PLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_SS_AMOUNT_DSFRAC[] = {
+	 { "PLL_SS_AMOUNT_DSFRAC", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_SS_CNTL[] = {
+	 { "PLL_SS_AMOUNT_FBDIV", 0, 7, &umr_bitfield_default },
+	 { "PLL_SS_AMOUNT_NFRAC_SLIP", 8, 11, &umr_bitfield_default },
+	 { "PLL_SS_EN", 12, 12, &umr_bitfield_default },
+	 { "PLL_SS_MODE", 13, 13, &umr_bitfield_default },
+	 { "PLL_SS_STEP_SIZE_DSFRAC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_DS_CNTL[] = {
+	 { "PLL_DS_FRAC", 0, 15, &umr_bitfield_default },
+	 { "PLL_DS_ORDER", 16, 17, &umr_bitfield_default },
+	 { "PLL_DS_MODE", 18, 18, &umr_bitfield_default },
+	 { "PLL_DS_PRBS_EN", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_IDCLK_CNTL[] = {
+	 { "PLL_LTDP_IDCLK_EN", 0, 0, &umr_bitfield_default },
+	 { "PLL_LTDP_IDCLK_DIFF_EN", 1, 1, &umr_bitfield_default },
+	 { "PLL_TMDP_IDCLK_EN", 2, 2, &umr_bitfield_default },
+	 { "PLL_TMDP_IDCLK_DIFF_EN", 3, 3, &umr_bitfield_default },
+	 { "PLL_UNIPHY_IDCLK_DIFF_EN", 4, 4, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV_RESET", 8, 8, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV_SELECT", 12, 12, &umr_bitfield_default },
+	 { "PLL_DIFF_POST_DIV", 16, 19, &umr_bitfield_default },
+	 { "PLL_CUR_LTDP", 20, 21, &umr_bitfield_default },
+	 { "PLL_CUR_PREDRV", 22, 23, &umr_bitfield_default },
+	 { "PLL_CUR_TMDP", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_CNTL[] = {
+	 { "PLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "PLL_POWER_DOWN", 1, 1, &umr_bitfield_default },
+	 { "PLL_BYPASS_CAL", 2, 2, &umr_bitfield_default },
+	 { "PLL_POST_DIV_SRC", 3, 3, &umr_bitfield_default },
+	 { "PLL_VCOREF", 4, 5, &umr_bitfield_default },
+	 { "PLL_PCIE_REFCLK_SEL", 6, 6, &umr_bitfield_default },
+	 { "PLL_ANTIGLITCH_RESETB", 7, 7, &umr_bitfield_default },
+	 { "PLL_CALREF", 8, 9, &umr_bitfield_default },
+	 { "PLL_CAL_BYPASS_REFDIV", 10, 10, &umr_bitfield_default },
+	 { "PLL_REFCLK_SEL", 11, 12, &umr_bitfield_default },
+	 { "PLL_ANTI_GLITCH_RESET", 13, 13, &umr_bitfield_default },
+	 { "PLL_XOCLK_DRV_R_EN", 14, 14, &umr_bitfield_default },
+	 { "PLL_REF_DIV_SRC", 16, 18, &umr_bitfield_default },
+	 { "PLL_LOCK_FREQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "PLL_CALIB_DONE", 20, 20, &umr_bitfield_default },
+	 { "PLL_LOCKED", 21, 21, &umr_bitfield_default },
+	 { "PLL_TIMING_MODE_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PLL_DIG_SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_ANALOG[] = {
+	 { "PLL_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "PLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "PLL_CP", 8, 11, &umr_bitfield_default },
+	 { "PLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "PLL_VREG_FB_TRIM", 21, 23, &umr_bitfield_default },
+	 { "PLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_VREG_CNTL[] = {
+	 { "PLL_VREG_CNTL", 0, 19, &umr_bitfield_default },
+	 { "PLL_BG_VREG_BIAS", 20, 21, &umr_bitfield_default },
+	 { "PLL_VREF_SEL", 26, 26, &umr_bitfield_default },
+	 { "PLL_VREG_BIAS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UNLOCK_DETECT_CNTL[] = {
+	 { "PLL_UNLOCK_DETECT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PLL_UNLOCK_DET_RES100_SELECT", 1, 1, &umr_bitfield_default },
+	 { "PLL_UNLOCK_STICKY_STATUS", 2, 2, &umr_bitfield_default },
+	 { "PLL_UNLOCK_STICKY_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "PLL_UNLOCK_DET_COUNT", 4, 6, &umr_bitfield_default },
+	 { "PLL_UNLOCKED_STICKY_RST_TEST", 7, 7, &umr_bitfield_default },
+	 { "PLL_UNLOCKED_STICKY_TEST_READBACK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_DEBUG_CNTL[] = {
+	 { "PLL_DEBUG_SIGNALS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PLL_DEBUG_MUXOUT_SEL", 4, 7, &umr_bitfield_default },
+	 { "PLL_DEBUG_CLK_SEL", 8, 12, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_CNTL", 16, 23, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_READBACK", 24, 26, &umr_bitfield_default },
+	 { "PLL_DEBUG_ADC_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UPDATE_LOCK[] = {
+	 { "PLL_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_UPDATE_CNTL[] = {
+	 { "PLL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "PLL_UPDATE_POINT", 8, 8, &umr_bitfield_default },
+	 { "PLL_AUTO_RESET_DISABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_DISPCLK_DTO_CNTL[] = {
+	 { "PLL_DISPCLK_DTO_PHASE", 0, 8, &umr_bitfield_default },
+	 { "PLL_DISPCLK_DTO_DIS", 16, 16, &umr_bitfield_default },
+	 { "PLL_DISPCLK_DTO_UPDATE_MODE", 17, 18, &umr_bitfield_default },
+	 { "PLL_DISPCLK_DTO_UPDATE_PENDING", 20, 20, &umr_bitfield_default },
+	 { "PLL_DISPCLK_DTO_UPDATE_REQ", 21, 21, &umr_bitfield_default },
+	 { "PLL_DISPCLK_DTO_UPDATE_ACK", 22, 22, &umr_bitfield_default },
+	 { "PLL_DISPCLK_DTO_COMPL_DELAY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_DISPCLK_CURRENT_DTO_PHASE[] = {
+	 { "PLL_DISPCLK_CURRENT_DTO_PHASE", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFCOUNTER_STATE[] = {
+	 { "PERFCOUNTER_CNT0_STATE", 0, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL0", 2, 2, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT1_STATE", 4, 5, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL1", 6, 6, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT2_STATE", 8, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL2", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT3_STATE", 12, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL3", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT4_STATE", 16, 17, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL4", 18, 18, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT5_STATE", 20, 21, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL5", 22, 22, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT6_STATE", 24, 25, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL6", 26, 26, &umr_bitfield_default },
+	 { "PERFCOUNTER_CNT7_STATE", 28, 29, &umr_bitfield_default },
+	 { "PERFCOUNTER_STATE_SEL7", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_XOR_LOCK[] = {
+	 { "PLL_XOR_LOCK", 0, 0, &umr_bitfield_default },
+	 { "PLL_XOR_LOCK_READBACK", 1, 1, &umr_bitfield_default },
+	 { "PLL_SPARE", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPLL_ANALOG_CNTL[] = {
+	 { "PLL_ANALOG_TEST_EN", 0, 0, &umr_bitfield_default },
+	 { "PLL_ANALOG_MUX_CNTL", 1, 4, &umr_bitfield_default },
+	 { "PLL_ANALOGOUT_MUX_CNTL", 5, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CVALUE_INT_MISC[] = {
+	 { "PERFCOUNTER_INT0_STATUS", 0, 0, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT1_STATUS", 1, 1, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT2_STATUS", 2, 2, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT3_STATUS", 3, 3, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT4_STATUS", 4, 4, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT5_STATUS", 5, 5, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT6_STATUS", 6, 6, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT7_STATUS", 7, 7, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT0_ACK", 8, 8, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT1_ACK", 9, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT2_ACK", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT3_ACK", 11, 11, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT4_ACK", 12, 12, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT5_ACK", 13, 13, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT6_ACK", 14, 14, &umr_bitfield_default },
+	 { "PERFCOUNTER_INT7_ACK", 15, 15, &umr_bitfield_default },
+	 { "PERFMON_CVALUE_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[] = {
+	 { "SUBSYSTEM_ID_BYTE1", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[] = {
+	 { "SUBSYSTEM_ID_BYTE2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[] = {
+	 { "SUBSYSTEM_ID_BYTE3", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 1, &umr_bitfield_default },
+	 { "PERFMON_RUN_ENABLE_SEL", 4, 7, &umr_bitfield_default },
+	 { "PERFMON_RPT_COUNT", 8, 27, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_AND_OR", 28, 28, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_EN", 29, 29, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "PERFMON_CNTOFF_INT_ACK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_CVALUE_LOW[] = {
+	 { "PERFMON_CVALUE_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_HI[] = {
+	 { "PERFMON_HI", 0, 15, &umr_bitfield_default },
+	 { "PERFMON_READ_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_OCCURRED", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_CLEAR", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_OCCURRED", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_CLEAR", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_CLEAR", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_OCCURRED", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_OCCURRED", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_OCCURRED", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_CLEAR", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_OCCURRED", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_CLEAR", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_OCCURRED", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_CLEAR", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_OCCURRED", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_CLEAR", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_OCCURRED", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_OCCURRED", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_OCCURRED", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_CLEAR", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_OCCURRED", 23, 23, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_CLEAR", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_OCCURRED", 25, 25, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_CLEAR", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_OCCURRED", 26, 26, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_CLEAR", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_STATUS4[] = {
+	 { "SCANIN_PERFMON_COUNTER0_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER0_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER1_INT_OCCURRED", 1, 1, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER1_INT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER2_INT_OCCURRED", 2, 2, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER2_INT_CLEAR", 2, 2, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER3_INT_OCCURRED", 3, 3, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER3_INT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER4_INT_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER4_INT_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER5_INT_OCCURRED", 5, 5, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER5_INT_CLEAR", 5, 5, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER6_INT_OCCURRED", 6, 6, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER6_INT_CLEAR", 6, 6, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER7_INT_OCCURRED", 7, 7, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER7_INT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER_OFF_INT_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER_OFF_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_TO_UC_EN", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_TO_UC_EN", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_TO_UC_EN", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_TO_UC_EN", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_TO_UC_EN", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_TO_UC_EN", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_TO_UC_EN", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_TO_UC_EN", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_TO_UC_EN", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_TO_UC_EN", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_TO_UC_EN", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_TO_UC_EN", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_TO_UC_EN", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_TO_UC_EN", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_TO_UC_EN", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_TO_UC_EN", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[] = {
+	 { "SCANIN_PERFMON_COUNTER0_INT_TO_UC_EN", 0, 0, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER1_INT_TO_UC_EN", 1, 1, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER2_INT_TO_UC_EN", 2, 2, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER3_INT_TO_UC_EN", 3, 3, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER4_INT_TO_UC_EN", 4, 4, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER5_INT_TO_UC_EN", 5, 5, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER6_INT_TO_UC_EN", 6, 6, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER7_INT_TO_UC_EN", 7, 7, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER_OFF_INT_TO_UC_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[] = {
+	 { "SCANIN_PERFMON_COUNTER0_INT_XIRQ_IRQ_SEL", 0, 0, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER1_INT_XIRQ_IRQ_SEL", 1, 1, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER2_INT_XIRQ_IRQ_SEL", 2, 2, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER3_INT_XIRQ_IRQ_SEL", 3, 3, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER4_INT_XIRQ_IRQ_SEL", 4, 4, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER5_INT_XIRQ_IRQ_SEL", 5, 5, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER6_INT_XIRQ_IRQ_SEL", 6, 6, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER7_INT_XIRQ_IRQ_SEL", 7, 7, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER_OFF_INT_XIRQ_IRQ_SEL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1[] = {
+	 { "DCI_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER0_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INT_MASK", 23, 23, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INT_MASK", 25, 25, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INT_MASK", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INT_MASK", 23, 23, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INT_MASK", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INT_MASK", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INT_MASK", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INT_MASK", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INT_MASK", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INT_MASK", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INT_MASK", 15, 15, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INT_MASK", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INT_MASK", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INT_MASK", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INT_MASK", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INT_MASK", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INT_MASK", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INT_MASK", 23, 23, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INT_MASK", 24, 24, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INT_MASK", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INT_MASK", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4[] = {
+	 { "SCANIN_PERFMON_COUNTER0_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER1_INT_MASK", 1, 1, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER2_INT_MASK", 2, 2, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER3_INT_MASK", 3, 3, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER4_INT_MASK", 4, 4, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER5_INT_MASK", 5, 5, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER6_INT_MASK", 6, 6, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER7_INT_MASK", 7, 7, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER_OFF_INT_MASK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_LOW[] = {
+	 { "PERFMON_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_CONFIG[] = {
+	 { "PIPE0_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_ENABLE[] = {
+	 { "PIPE0_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_PG_STATUS[] = {
+	 { "PIPE0_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE0_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE0_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE0_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE0_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_CONFIG[] = {
+	 { "PIPE1_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_ENABLE[] = {
+	 { "PIPE1_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_PG_STATUS[] = {
+	 { "PIPE1_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE1_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE1_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE1_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE1_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_CONFIG[] = {
+	 { "PIPE2_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_ENABLE[] = {
+	 { "PIPE2_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_PG_STATUS[] = {
+	 { "PIPE2_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE2_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE2_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE2_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE2_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_CONFIG[] = {
+	 { "PIPE3_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_ENABLE[] = {
+	 { "PIPE3_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_PG_STATUS[] = {
+	 { "PIPE3_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE3_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE3_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE3_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE3_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_TEST_DEBUG_INDEX[] = {
+	 { "PERFMON_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "PERFMON_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_CONFIG[] = {
+	 { "PIPE4_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_ENABLE[] = {
+	 { "PIPE4_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_PG_STATUS[] = {
+	 { "PIPE4_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE4_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE4_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE4_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE4_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_CONFIG[] = {
+	 { "PIPE5_POWER_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_ENABLE[] = {
+	 { "PIPE5_POWER_GATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_PG_STATUS[] = {
+	 { "PIPE5_PGFSM_READ_DATA", 0, 23, &umr_bitfield_default },
+	 { "PIPE5_DEBUG_PWR_STATUS", 24, 25, &umr_bitfield_default },
+	 { "PIPE5_DESIRED_PWR_STATE", 28, 28, &umr_bitfield_default },
+	 { "PIPE5_REQUESTED_PWR_STATE", 29, 29, &umr_bitfield_default },
+	 { "PIPE5_PGFSM_PWR_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_IP_REQUEST_CNTL[] = {
+	 { "IP_REQUEST_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_INDEX[] = {
+	 { "DCPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCPG_TEST_DEBUG_DATA[] = {
+	 { "DCPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_CONFIG_REG[] = {
+	 { "PGFSM_CONFIG_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGFSM_WRITE_REG[] = {
+	 { "PGFSM_WRITE_REG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PGCNTL_STATUS_REG[] = {
+	 { "SWREQ_RWOP_BUSY", 0, 0, &umr_bitfield_default },
+	 { "SWREQ_RWOP_FORCE", 1, 1, &umr_bitfield_default },
+	 { "IPREQ_IGNORE_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DCPG_ECO_DEBUG", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DC_PIPE_DIS[] = {
+	 { "DC_PIPE_DIS", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPERFMON_TEST_DEBUG_DATA[] = {
+	 { "PERFMON_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_INDEX[] = {
+	 { "AZALIA_ENDPOINT_REG_INDEX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ENDPOINT_DATA[] = {
+	 { "AZALIA_ENDPOINT_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL0[] = {
+	 { "CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL1[] = {
+	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL2[] = {
+	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_CONTROL3[] = {
+	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC0_RESULT[] = {
+	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL0[] = {
+	 { "CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_MODE", 4, 4, &umr_bitfield_default },
+	 { "CRC_INSTANCE_SEL", 8, 10, &umr_bitfield_default },
+	 { "CRC_SOURCE_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL1[] = {
+	 { "CRC_BLOCK_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL2[] = {
+	 { "CRC_BLOCK_ITERATION", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_CONTROL3[] = {
+	 { "CRC_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "CRC_BLOCK_COMPLETE_PHASE", 4, 4, &umr_bitfield_default },
+	 { "CRC_CHANNEL_RESULT_SEL", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CRC1_RESULT[] = {
+	 { "CRC_RESULT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_CLOCK_GATING[] = {
+	 { "ENABLE_CLOCK_GATING", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO[] = {
+	 { "AZALIA_AUDIO_DTO_PHASE", 0, 15, &umr_bitfield_default },
+	 { "AZALIA_AUDIO_DTO_MODULE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_AUDIO_DTO_CONTROL[] = {
+	 { "AZALIA_AUDIO_FORCE_DTO", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_SCLK_CONTROL[] = {
+	 { "AUDIO_SCLK_CONTROL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_UNDERFLOW_FILLER_SAMPLE[] = {
+	 { "AZALIA_UNDERFLOW_FILLER_SAMPLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_DATA_DMA_CONTROL[] = {
+	 { "DATA_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+	 { "DATA_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+	 { "AZALIA_IOC_GENERATION_METHOD", 16, 16, &umr_bitfield_default },
+	 { "AZALIA_UNDERFLOW_CONTROL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_BDL_DMA_CONTROL[] = {
+	 { "BDL_DMA_NON_SNOOP", 0, 1, &umr_bitfield_default },
+	 { "BDL_DMA_ISOCHRONOUS", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_INDEX[] = {
+	 { "DCCG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCCG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+	 { "DCCG_DBG_SEL", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_RIRB_AND_DP_CONTROL[] = {
+	 { "RIRB_NON_SNOOP", 0, 0, &umr_bitfield_default },
+	 { "DP_DMA_NON_SNOOP", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CORB_DMA_CONTROL[] = {
+	 { "CORB_DMA_NON_SNOOP", 0, 0, &umr_bitfield_default },
+	 { "CORB_DMA_ISOCHRONOUS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[] = {
+	 { "APPLICATION_POSITION_IN_CYCLIC_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CYCLIC_BUFFER_SYNC[] = {
+	 { "CYCLIC_BUFFER_SYNC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_GLOBAL_CAPABILITIES[] = {
+	 { "NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[] = {
+	 { "OUTPUT_PAYLOAD_CAPABILITY", 0, 15, &umr_bitfield_default },
+	 { "OUTSTRMPAY", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[] = {
+	 { "LATENCY_HIDING_LEVEL", 0, 7, &umr_bitfield_default },
+	 { "SYS_MEM_ACTIVE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_CONTROLLER_DEBUG[] = {
+	 { "CONTROLLER_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_DEBUG_DATA[] = {
+	 { "DCCG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_INDEX[] = {
+	 { "AZ_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZ_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZ_TEST_DEBUG_DATA[] = {
+	 { "AZ_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[] = {
+	 { "PORT_CONNECTIVITY", 0, 2, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY_OVERRIDE_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[] = {
+	 { "HBR_CHANNEL_COUNT", 0, 2, &umr_bitfield_default },
+	 { "COMPRESSED_CHANNEL_COUNT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[] = {
+	 { "RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[] = {
+	 { "POWER_STATE_SET", 0, 3, &umr_bitfield_default },
+	 { "POWER_STATE_ACT", 4, 7, &umr_bitfield_default },
+	 { "CLKSTOPOK", 9, 9, &umr_bitfield_default },
+	 { "POWER_STATE_SETTINGS_RESET", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[] = {
+	 { "SUBSYSTEM_ID_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "SUBSYSTEM_ID_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[] = {
+	 { "CONVERTER_SYNCHRONIZATION", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_CODEC_DEBUG[] = {
+	 { "CODEC_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_TEST_CLK_SEL[] = {
+	 { "DCCG_TEST_CLK_GENERICA_SEL", 0, 8, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICA_INV", 12, 12, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_SEL", 16, 24, &umr_bitfield_default },
+	 { "DCCG_TEST_CLK_GENERICB_INV", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET0[] = {
+	 { "GTC_GROUP_OFFSET0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET1[] = {
+	 { "GTC_GROUP_OFFSET1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET2[] = {
+	 { "GTC_GROUP_OFFSET2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET3[] = {
+	 { "GTC_GROUP_OFFSET3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET4[] = {
+	 { "GTC_GROUP_OFFSET4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET5[] = {
+	 { "GTC_GROUP_OFFSET5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_F0_GTC_GROUP_OFFSET6[] = {
+	 { "GTC_GROUP_OFFSET6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_INDEX[] = {
+	 { "AZALIA_STREAM_REG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "AZALIA_STREAM_REG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZALIA_STREAM_DATA[] = {
+	 { "AZALIA_STREAM_REG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[] = {
+	 { "CODEC_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[] = {
+	 { "IMMEDIATE_COMMAND_WRITE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[] = {
+	 { "IMMEDIATE_COMMAND_WRITE_VERB_AND_PAYLOAD", 0, 27, &umr_bitfield_default },
+	 { "IMMEDIATE_COMMAND_WRITE_CODEC_ADDRESS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_I[] = {
+	 { "DP_AUX1_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT18[] = {
+	 { "LINE_CMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_INT_STATUS[] = {
+	 { "DC_HPD1_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD1_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD1_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_INT_CONTROL[] = {
+	 { "DC_HPD1_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD1_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD1_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_CONTROL[] = {
+	 { "DC_HPD1_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD1_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_INT_STATUS[] = {
+	 { "DC_HPD2_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD2_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD2_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_INT_CONTROL[] = {
+	 { "DC_HPD2_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD2_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD2_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_CONTROL[] = {
+	 { "DC_HPD2_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD2_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_INT_STATUS[] = {
+	 { "DC_HPD3_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD3_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD3_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_INT_CONTROL[] = {
+	 { "DC_HPD3_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD3_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD3_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_CONTROL[] = {
+	 { "DC_HPD3_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD3_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_INT_STATUS[] = {
+	 { "DC_HPD4_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD4_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD4_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_INT_CONTROL[] = {
+	 { "DC_HPD4_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD4_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD4_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_CONTROL[] = {
+	 { "DC_HPD4_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD4_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_INT_STATUS[] = {
+	 { "DC_HPD5_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD5_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD5_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_INT_CONTROL[] = {
+	 { "DC_HPD5_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD5_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD5_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_CONTROL[] = {
+	 { "DC_HPD5_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD5_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_INT_STATUS[] = {
+	 { "DC_HPD6_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD6_SENSE", 1, 1, &umr_bitfield_default },
+	 { "DC_HPD6_SENSE_DELAYED", 4, 4, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_INT_CONTROL[] = {
+	 { "DC_HPD6_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DC_HPD6_INT_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "DC_HPD6_INT_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INT_ACK", 20, 20, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INT_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_CONTROL[] = {
+	 { "DC_HPD6_CONNECTION_TIMER", 0, 12, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INT_TIMER", 16, 25, &umr_bitfield_default },
+	 { "DC_HPD6_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_CONTROL[] = {
+	 { "DC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_STATUS_RESET", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC_SELECT", 8, 10, &umr_bitfield_default },
+	 { "DC_I2C_TRANSACTION_COUNT", 20, 21, &umr_bitfield_default },
+	 { "DC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_ARBITRATION[] = {
+	 { "DC_I2C_SW_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "DC_I2C_NO_QUEUED_SW_GO", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_HW_XFER", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_ABORT_SW_XFER", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_USE_I2C_REG_REQ", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_USING_I2C_REG", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_USE_I2C_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DMCU_DONE_USING_I2C_REG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_INTERRUPT_CONTROL[] = {
+	 { "DC_I2C_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE_MASK", 10, 10, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_INT", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_ACK", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE_MASK", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_INT", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_ACK", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE_MASK", 18, 18, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_INT", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_ACK", 21, 21, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_INT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_ACK", 25, 25, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE_MASK", 26, 26, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_INT", 27, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_ACK", 28, 28, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE_MASK", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_SW_STATUS[] = {
+	 { "DC_I2C_SW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE", 2, 2, &umr_bitfield_default },
+	 { "DC_I2C_SW_ABORTED", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_SW_TIMEOUT", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_SW_INTERRUPTED", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_SW_BUFFER_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_SW_STOPPED_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK2", 14, 14, &umr_bitfield_default },
+	 { "DC_I2C_SW_NACK3", 15, 15, &umr_bitfield_default },
+	 { "DC_I2C_SW_REQ", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_HW_STATUS[] = {
+	 { "DC_I2C_DDC1_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_HW_STATUS[] = {
+	 { "DC_I2C_DDC2_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_HW_STATUS[] = {
+	 { "DC_I2C_DDC3_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_HW_STATUS[] = {
+	 { "DC_I2C_DDC4_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_HW_STATUS[] = {
+	 { "DC_I2C_DDC5_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_HW_STATUS[] = {
+	 { "DC_I2C_DDC6_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SPEED[] = {
+	 { "DC_I2C_DDC1_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC1_SETUP[] = {
+	 { "DC_I2C_DDC1_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC1_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SPEED[] = {
+	 { "DC_I2C_DDC2_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC2_SETUP[] = {
+	 { "DC_I2C_DDC2_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC2_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SPEED[] = {
+	 { "DC_I2C_DDC3_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC3_SETUP[] = {
+	 { "DC_I2C_DDC3_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC3_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SPEED[] = {
+	 { "DC_I2C_DDC4_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC4_SETUP[] = {
+	 { "DC_I2C_DDC4_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC4_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SPEED[] = {
+	 { "DC_I2C_DDC5_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC5_SETUP[] = {
+	 { "DC_I2C_DDC5_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC5_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SPEED[] = {
+	 { "DC_I2C_DDC6_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDC6_SETUP[] = {
+	 { "DC_I2C_DDC6_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDC6_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION0[] = {
+	 { "DC_I2C_RW0", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK0", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START0", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP0", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT0", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION1[] = {
+	 { "DC_I2C_RW1", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK1", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START1", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP1", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT1", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION2[] = {
+	 { "DC_I2C_RW2", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK2", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START2", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP2", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_TRANSACTION3[] = {
+	 { "DC_I2C_RW3", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_STOP_ON_NACK3", 8, 8, &umr_bitfield_default },
+	 { "DC_I2C_START3", 12, 12, &umr_bitfield_default },
+	 { "DC_I2C_STOP3", 13, 13, &umr_bitfield_default },
+	 { "DC_I2C_COUNT3", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DATA[] = {
+	 { "DC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_INDEX", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_CONTROL[] = {
+	 { "GENERIC_I2C_GO", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SEND_RESET", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_DBG_REF_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_INTERRUPT_CONTROL[] = {
+	 { "GENERIC_I2C_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE_MASK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_STATUS[] = {
+	 { "GENERIC_I2C_STATUS", 0, 3, &umr_bitfield_default },
+	 { "GENERIC_I2C_DONE", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_ABORTED", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOPPED_ON_NACK", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_NACK", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SPEED[] = {
+	 { "GENERIC_I2C_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_SETUP[] = {
+	 { "GENERIC_I2C_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "GENERIC_I2C_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_TRANSACTION[] = {
+	 { "GENERIC_I2C_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP_ON_NACK", 8, 8, &umr_bitfield_default },
+	 { "GENERIC_I2C_ACK_ON_READ", 9, 9, &umr_bitfield_default },
+	 { "GENERIC_I2C_START", 12, 12, &umr_bitfield_default },
+	 { "GENERIC_I2C_STOP", 13, 13, &umr_bitfield_default },
+	 { "GENERIC_I2C_COUNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_DATA[] = {
+	 { "GENERIC_I2C_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_DATA", 8, 15, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX", 16, 19, &umr_bitfield_default },
+	 { "GENERIC_I2C_INDEX_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_SELECTION[] = {
+	 { "GENERIC_I2C_SCL_PIN_SEL", 0, 6, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_PIN_SEL", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENERIC_I2C_PIN_DEBUG[] = {
+	 { "GENERIC_I2C_SCL_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_INPUT", 1, 1, &umr_bitfield_default },
+	 { "GENERIC_I2C_SCL_EN", 2, 2, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_OUTPUT", 4, 4, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_INPUT", 5, 5, &umr_bitfield_default },
+	 { "GENERIC_I2C_SDA_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS[] = {
+	 { "SCL_DISP1_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D1BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D1_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D1_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC1_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC1_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC1_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC1_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC1_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGA_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD1_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD1_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX1_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX1_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DACA_AUTODETECT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DACB_AUTODETECT_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DC_I2C_SW_DONE_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DC_I2C_HW_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DMCU_UC_INTERNAL_INT", 26, 26, &umr_bitfield_default },
+	 { "DMCU_SCP_INT", 27, 27, &umr_bitfield_default },
+	 { "ABM1_HG_READY_INT", 28, 28, &umr_bitfield_default },
+	 { "ABM1_LS_READY_INT", 29, 29, &umr_bitfield_default },
+	 { "ABM1_BL_UPDATE_INT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE[] = {
+	 { "SCL_DISP2_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D2BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D2_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D2_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC2_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC2_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC2_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC2_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC2_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGB_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD2_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD2_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX2_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX2_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "LB_D1_VLINE2_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "LB_D2_VLINE2_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "LB_D3_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DISP_TIMER_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC1_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE2[] = {
+	 { "SCL_DISP3_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D3BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D3_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D3_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC3_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC3_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC3_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC3_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC3_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGC_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD3_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD3_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX3_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX3_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "LB_D4_VLINE2_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "LB_D5_VLINE2_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "LB_D6_VLINE2_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC2_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE3[] = {
+	 { "SCL_DISP4_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D4BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D4_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D4_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC4_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC4_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC4_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC4_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC4_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGD_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD4_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD4_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX4_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX4_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "BUFMGR_IHIF_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "SISCL_HOST_CONFLICT_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "SISCL_DATA_OVERFLOW_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC3_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE4", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_POWER_MANAGEMENT_CNTL[] = {
+	 { "PM_ASSERT_RESET", 0, 0, &umr_bitfield_default },
+	 { "PM_ALL_BUSY_OFF", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_TIMER_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MSK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH0[] = {
+	 { "DOUT_SCRATCH0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH1[] = {
+	 { "DOUT_SCRATCH1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH2[] = {
+	 { "DOUT_SCRATCH2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH3[] = {
+	 { "DOUT_SCRATCH3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH4[] = {
+	 { "DOUT_SCRATCH4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH5[] = {
+	 { "DOUT_SCRATCH5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH6[] = {
+	 { "DOUT_SCRATCH6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_SCRATCH7[] = {
+	 { "DOUT_SCRATCH7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_TEST_DEBUG_INDEX[] = {
+	 { "DOUT_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DOUT_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_TEST_DEBUG_DATA[] = {
+	 { "DOUT_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE4[] = {
+	 { "SCL_DISP5_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D5BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D5_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D5_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC5_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC5_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC5_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC5_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC5_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGE_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD5_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD5_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX5_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX5_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_LOSS_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "CRTC5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC4_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE5", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE5[] = {
+	 { "SCL_DISP6_MODE_CHANGE_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "D6BLND_DATA_UNDERFLOW_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "LB_D6_VLINE_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "LB_D6_VBLANK_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "CRTC6_SNAPSHOT_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "CRTC6_FORCE_COUNT_NOW_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "CRTC6_TRIGA_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "CRTC6_TRIGB_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "CRTC6_VSYNC_NOM_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 10, 10, &umr_bitfield_default },
+	 { "DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGF_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DC_HPD6_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DC_HPD6_RX_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX6_SW_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX6_LS_DONE_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_LOSS_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "CRTC6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT0", 25, 25, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT1", 26, 26, &umr_bitfield_default },
+	 { "CRTC5_VERTICAL_INTERRUPT2", 27, 27, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT0", 28, 28, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT1", 29, 29, &umr_bitfield_default },
+	 { "CRTC6_VERTICAL_INTERRUPT2", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE6", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_HW_STATUS[] = {
+	 { "DC_I2C_DDCVGA_HW_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_DONE", 3, 3, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_REQ", 16, 16, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_HW_URG", 17, 17, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES", 24, 27, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_STATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SPEED[] = {
+	 { "DC_I2C_DDCVGA_THRESHOLD", 0, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_PRESCALE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_DDCVGA_SETUP[] = {
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_DATA_DRIVE_SEL", 1, 1, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_EDID_DETECT_MODE", 5, 5, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_CLK_DRIVE_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_BYTE_DELAY", 8, 15, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY", 16, 23, &umr_bitfield_default },
+	 { "DC_I2C_DDCVGA_TIME_LIMIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_ENABLE[] = {
+	 { "DVO_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DVO_PIXEL_WIDTH", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SOURCE_SELECT[] = {
+	 { "DVO_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DVO_STEREOSYNC_SELECT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_OUTPUT[] = {
+	 { "DVO_OUTPUT_ENABLE_MODE", 0, 1, &umr_bitfield_default },
+	 { "DVO_CLOCK_MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CONTROL[] = {
+	 { "DVO_RATE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "DVO_SDRCLK_SEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_DVPDATA_WIDTH", 4, 5, &umr_bitfield_default },
+	 { "DVO_DUAL_CHANNEL_EN", 8, 8, &umr_bitfield_default },
+	 { "DVO_RESET_FIFO", 16, 16, &umr_bitfield_default },
+	 { "DVO_SYNC_PHASE", 17, 17, &umr_bitfield_default },
+	 { "DVO_INVERT_DVOCLK", 18, 18, &umr_bitfield_default },
+	 { "DVO_HSYNC_POLARITY", 20, 20, &umr_bitfield_default },
+	 { "DVO_VSYNC_POLARITY", 21, 21, &umr_bitfield_default },
+	 { "DVO_DE_POLARITY", 22, 22, &umr_bitfield_default },
+	 { "DVO_COLOR_FORMAT", 24, 25, &umr_bitfield_default },
+	 { "DVO_CTL3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC_EN[] = {
+	 { "DVO_CRC2_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_MASK[] = {
+	 { "DVO_CRC2_SIG_MASK", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_CRC2_SIG_RESULT[] = {
+	 { "DVO_CRC2_SIG_RESULT", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_FIFO_ERROR_STATUS[] = {
+	 { "DVO_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DVO_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DVO_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DVO_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DVO_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DVO_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DVO_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DVO_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK1_SEL[] = {
+	 { "DCDEBUG_BUS_CLK1_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK2_SEL[] = {
+	 { "DCDEBUG_BUS_CLK2_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK3_SEL[] = {
+	 { "DCDEBUG_BUS_CLK3_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_BUS_CLK4_SEL[] = {
+	 { "DCDEBUG_BUS_CLK4_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD1_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD1_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD1_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD1_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD2_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD2_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD2_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD2_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD3_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD3_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD3_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD3_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD4_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD4_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD4_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD4_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD5_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD5_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD5_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD5_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_FAST_TRAIN_CNTL[] = {
+	 { "DC_HPD6_CONNECT_AUX_TX_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD6_CONNECT_FAST_TRAIN_DELAY", 12, 19, &umr_bitfield_default },
+	 { "DC_HPD6_CONNECT_AUX_TX_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_HPD6_CONNECT_FAST_TRAIN_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_PIN_OVERRIDE[] = {
+	 { "DCDEBUG_OUT_OVERRIDE1_PIN_SEL", 0, 3, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL", 4, 8, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE1_EN", 12, 12, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_PIN_SEL", 16, 19, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL", 20, 24, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_OVERRIDE2_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_CNTL[] = {
+	 { "DCDEBUG_BLOCK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_EN", 5, 5, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_PIN_SEL", 6, 6, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_TEST_DATA_EN", 7, 7, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_TEST_DATA", 8, 19, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCDEBUG_OUT_24BIT_SEL", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCDEBUG_OUT_DATA[] = {
+	 { "DCDEBUG_OUT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_I2C_EDID_DETECT_CTRL[] = {
+	 { "DC_I2C_EDID_DETECT_WAIT_TIME", 0, 15, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID", 20, 23, &umr_bitfield_default },
+	 { "DC_I2C_EDID_DETECT_SEND_RESET", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_CONTROL[] = {
+	 { "AUX_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_READ_EN", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_UPDATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "AUX_IGNORE_HPD_DISCON", 16, 16, &umr_bitfield_default },
+	 { "AUX_MODE_DET_EN", 18, 18, &umr_bitfield_default },
+	 { "AUX_HPD_SEL", 20, 22, &umr_bitfield_default },
+	 { "AUX_IMPCAL_REQ_EN", 24, 24, &umr_bitfield_default },
+	 { "AUX_TEST_MODE", 28, 28, &umr_bitfield_default },
+	 { "AUX_DEGLITCH_EN", 29, 29, &umr_bitfield_default },
+	 { "SPARE_0", 30, 30, &umr_bitfield_default },
+	 { "SPARE_1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_CONTROL[] = {
+	 { "AUX_SW_GO", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_READ_TRIG", 2, 2, &umr_bitfield_default },
+	 { "AUX_SW_START_DELAY", 4, 7, &umr_bitfield_default },
+	 { "AUX_SW_WR_BYTES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_ARB_CONTROL[] = {
+	 { "AUX_ARB_PRIORITY", 0, 1, &umr_bitfield_default },
+	 { "AUX_REG_RW_CNTL_STATUS", 2, 3, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_SW_GO", 8, 8, &umr_bitfield_default },
+	 { "AUX_NO_QUEUED_LS_GO", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_PENDING_USE_AUX_REG_REQ", 16, 16, &umr_bitfield_default },
+	 { "AUX_SW_DONE_USING_AUX_REG", 17, 17, &umr_bitfield_default },
+	 { "AUX_DMCU_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_PENDING_USE_AUX_REG_REQ", 24, 24, &umr_bitfield_default },
+	 { "AUX_DMCU_DONE_USING_AUX_REG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_INTERRUPT_CONTROL[] = {
+	 { "AUX_SW_DONE_INT", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DONE_ACK", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_DONE_MASK", 2, 2, &umr_bitfield_default },
+	 { "AUX_LS_DONE_INT", 4, 4, &umr_bitfield_default },
+	 { "AUX_LS_DONE_ACK", 5, 5, &umr_bitfield_default },
+	 { "AUX_LS_DONE_MASK", 6, 6, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_INT", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_ACK", 9, 9, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_DONE_INT_MASK", 10, 10, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_INT", 12, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_ACK", 13, 13, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_ERROR_INT_MASK", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_STATUS[] = {
+	 { "AUX_SW_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_SW_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_SW_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_SW_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_SW_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_SW_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_SW_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_SW_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_SW_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_SW_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_SW_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_ARB_STATUS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_STATUS[] = {
+	 { "AUX_LS_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_LS_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_LS_RX_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_LS_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_LS_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_LS_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_LS_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_LS_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_LS_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_LS_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_LS_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_LS_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_LS_CP_IRQ", 29, 29, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED", 30, 30, &umr_bitfield_default },
+	 { "AUX_LS_UPDATED_ACK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_SW_DATA[] = {
+	 { "AUX_SW_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "AUX_SW_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_SW_INDEX", 16, 20, &umr_bitfield_default },
+	 { "AUX_SW_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_LS_DATA[] = {
+	 { "AUX_LS_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_LS_INDEX", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_REF_CONTROL[] = {
+	 { "AUX_TX_REF_SEL", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_RATE", 4, 5, &umr_bitfield_default },
+	 { "AUX_TX_REF_DIV", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_CONTROL[] = {
+	 { "AUX_TX_PRECHARGE_LEN", 0, 2, &umr_bitfield_default },
+	 { "AUX_TX_PRECHARGE_SYMBOLS", 8, 13, &umr_bitfield_default },
+	 { "AUX_MODE_DET_CHECK_DELAY", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL0[] = {
+	 { "AUX_RX_START_WINDOW", 4, 6, &umr_bitfield_default },
+	 { "AUX_RX_RECEIVE_WINDOW", 8, 10, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_DETECT_LEN", 12, 13, &umr_bitfield_default },
+	 { "AUX_RX_TRANSITION_FILTER_EN", 16, 16, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT", 17, 17, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_START", 18, 18, &umr_bitfield_default },
+	 { "AUX_RX_ALLOW_BELOW_THRESHOLD_STOP", 19, 19, &umr_bitfield_default },
+	 { "AUX_RX_PHASE_DETECT_LEN", 20, 21, &umr_bitfield_default },
+	 { "AUX_RX_TIMEOUT_LEN", 24, 26, &umr_bitfield_default },
+	 { "AUX_RX_DETECTION_THRESHOLD", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_CONTROL1[] = {
+	 { "AUX_RX_PRECHARGE_SKIP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_TX_STATUS[] = {
+	 { "AUX_TX_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "AUX_TX_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_TX_HALF_SYM_PERIOD", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_DPHY_RX_STATUS[] = {
+	 { "AUX_RX_STATE", 0, 2, &umr_bitfield_default },
+	 { "AUX_RX_SYNC_VALID_COUNT", 8, 12, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD_FRACT", 16, 20, &umr_bitfield_default },
+	 { "AUX_RX_HALF_SYM_PERIOD", 21, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_CONTROL[] = {
+	 { "AUX_GTC_SYNC_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_IMPCAL_EN", 4, 4, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_IMPCAL_INTERVAL", 8, 11, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_PERIOD", 12, 15, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_MAINT_PERIOD", 16, 18, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_BLOCK_REQ", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_INTERVAL_RESET_WINDOW", 22, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_OFFSET_CALC_MAX_ATTEMPT", 24, 25, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_MAX_ATTEMPT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_ERROR_CONTROL[] = {
+	 { "AUX_GTC_POTENTIAL_ERROR_THRESHOLD", 0, 4, &umr_bitfield_default },
+	 { "AUX_GTC_DEFINITE_ERROR_THRESHOLD", 8, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_LEN", 16, 17, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NUM_RETRY_FOR_LOCK_MAINT", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_CONTROLLER_STATUS[] = {
+	 { "AUX_GTC_SYNC_LOCK_ACQ_COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_LOST", 4, 4, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_LOCK_ACQ_TIMEOUT_STATE", 9, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_PHASE_ADJUST_TIME_VIOL", 16, 16, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CRITICAL_ERR_OCCURRED_ACK", 21, 21, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED", 22, 22, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_POTENTIAL_ERR_REACHED_ACK", 23, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED", 24, 24, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_MAX_DEFINITE_ERR_REACHED_ACK", 25, 25, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_CTRL_STATE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_STATUS[] = {
+	 { "AUX_GTC_SYNC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_REQ", 1, 1, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_TIMEOUT_STATE", 4, 6, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_TIMEOUT", 7, 7, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_OVERFLOW", 8, 8, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_HPD_DISCON", 9, 9, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_PARTIAL_BYTE", 10, 10, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NON_AUX_MODE", 11, 11, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_MIN_COUNT_VIOL", 12, 12, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_INVALID_STOP", 14, 14, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_L", 17, 17, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_SYNC_INVALID_H", 18, 18, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_INVALID_START", 19, 19, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_NO_DET", 20, 20, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_INVALID_H", 22, 22, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_RX_RECV_INVALID_L", 23, 23, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_REPLY_BYTE_COUNT", 24, 28, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_NACKED", 29, 29, &umr_bitfield_default },
+	 { "AUX_GTC_MASTER_REQ_BY_RX", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_DATA[] = {
+	 { "AUX_GTC_DATA_RW", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_DATA", 8, 15, &umr_bitfield_default },
+	 { "AUX_GTC_INDEX", 16, 21, &umr_bitfield_default },
+	 { "AUX_GTC_INDEX_AUTOINCREMENT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[] = {
+	 { "AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE_VALUE", 4, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD1_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD1_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD1_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD2_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD2_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD2_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD3_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD3_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD3_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISPOUT_STEREOSYNC_SEL[] = {
+	 { "GENERICA_STEREOSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "GENERICB_STEREOSYNC_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD4_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD4_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD4_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD5_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD5_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD5_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_HPD6_TOGGLE_FILT_CNTL[] = {
+	 { "DC_HPD6_CONNECT_INT_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DC_HPD6_DISCONNECT_INT_DELAY", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDOUT_DCE_VCE_CONTROL[] = {
+	 { "DC_VCE_VIDEO_PIPE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DC_VCE_AUDIO_STREAM_SELECT", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[] = {
+	 { "IMMEDIATE_RESPONSE_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_J[] = {
+	 { "DP_AUX1_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICA[] = {
+	 { "GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICA_SEL", 8, 11, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_REFDIV_CLK_SEL", 12, 14, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_SEL", 16, 18, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 22, &umr_bitfield_default },
+	 { "GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GENERICB[] = {
+	 { "GENERICB_EN", 0, 0, &umr_bitfield_default },
+	 { "GENERICB_SEL", 8, 11, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_REFDIV_CLK_SEL", 12, 14, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_SEL", 16, 18, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL", 20, 22, &umr_bitfield_default },
+	 { "GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PAD_EXTERN_SIG[] = {
+	 { "DC_PAD_EXTERN_SIG_SEL", 0, 3, &umr_bitfield_default },
+	 { "MVP_PIXEL_SRC_STATUS", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_REF_CLK_CNTL[] = {
+	 { "HSYNCA_OUTPUT_SEL", 0, 1, &umr_bitfield_default },
+	 { "GENLK_CLK_OUTPUT_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DEBUG[] = {
+	 { "DC_GPIO_VIP_DEBUG", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_MACRO_DEBUG", 8, 9, &umr_bitfield_default },
+	 { "DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_DEBUG_BUS_FLOP_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_DVODATA_CONFIG[] = {
+	 { "VIP_MUX_EN", 19, 19, &umr_bitfield_default },
+	 { "VIP_ALTER_MAPPING_EN", 20, 20, &umr_bitfield_default },
+	 { "DVO_ALTER_MAPPING_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_POWER_STATE[] = {
+	 { "TVOUT_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "I2C_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "MVP_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "DPA_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "DPB_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "DPC_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "DPD_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "DPE_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "DPF_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "HDMI0_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "HDMI1_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "HDMI2_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "HDMI3_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
+	 { "HDMI4_MEM_PWR_STATE", 26, 27, &umr_bitfield_default },
+	 { "HDMI5_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_LIGHT_SLEEP_DIS[] = {
+	 { "TVOUT_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+	 { "I2C_LIGHT_SLEEP_FORCE", 1, 1, &umr_bitfield_default },
+	 { "MVP_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "DPA_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DPB_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DPC_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DPD_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DPE_LIGHT_SLEEP_DIS", 7, 7, &umr_bitfield_default },
+	 { "DPF_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
+	 { "HDMI0_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
+	 { "HDMI1_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
+	 { "HDMI2_LIGHT_SLEEP_DIS", 11, 11, &umr_bitfield_default },
+	 { "HDMI3_LIGHT_SLEEP_DIS", 12, 12, &umr_bitfield_default },
+	 { "HDMI4_LIGHT_SLEEP_DIS", 13, 13, &umr_bitfield_default },
+	 { "HDMI5_LIGHT_SLEEP_DIS", 14, 14, &umr_bitfield_default },
+	 { "HDMI6_LIGHT_SLEEP_DIS", 15, 15, &umr_bitfield_default },
+	 { "MVP_MEM_SHUTDOWN_DIS", 16, 16, &umr_bitfield_default },
+	 { "DPA_MEM_SHUTDOWN_DIS", 17, 17, &umr_bitfield_default },
+	 { "DPB_MEM_SHUTDOWN_DIS", 18, 18, &umr_bitfield_default },
+	 { "DPC_MEM_SHUTDOWN_DIS", 19, 19, &umr_bitfield_default },
+	 { "DPD_MEM_SHUTDOWN_DIS", 20, 20, &umr_bitfield_default },
+	 { "DPE_MEM_SHUTDOWN_DIS", 21, 21, &umr_bitfield_default },
+	 { "DPF_MEM_SHUTDOWN_DIS", 22, 22, &umr_bitfield_default },
+	 { "DPG_MEM_SHUTDOWN_DIS", 23, 23, &umr_bitfield_default },
+	 { "DPG_LIGHT_SLEEP_DIS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKA[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKA", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKA", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKA_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKA", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKA", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKA", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKA", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKB[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKB", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKB", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKB_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKB", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKB", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKB", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PERIOD[] = {
+	 { "UNIPHY_IMPCAL_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXP_IMPCAL[] = {
+	 { "AUXP_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXP_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXP_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAUXN_IMPCAL[] = {
+	 { "AUXN_IMPCAL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_CALOUT", 8, 8, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR", 9, 9, &umr_bitfield_default },
+	 { "AUXN_CALOUT_ERROR_AK", 10, 10, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_VALUE", 16, 19, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_STEP_DELAY", 20, 23, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE", 24, 27, &umr_bitfield_default },
+	 { "AUXN_IMPCAL_OVERRIDE_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_AB[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_AB[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKA", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKB", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKC[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKC", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKC", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKC_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKC", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKC", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKC", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKC", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKD[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKD", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKD", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKD_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKD", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKD", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKD", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKD", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_CD[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_CD[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKC", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKD", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKE[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKE", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKE", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKE_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKE", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKE", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKE", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_LINKF[] = {
+	 { "UNIPHY_IMPCAL_ENABLE_LINKF", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_CALOUT_LINKF", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_CALOUT_ERROR_LINKF_AK", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_VALUE_LINKF", 16, 19, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_STEP_DELAY_LINKF", 20, 23, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_LINKF", 24, 27, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_SEL_LINKF", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_IMPCAL_CNTL_EF[] = {
+	 { "CALR_CNTL_OVERRIDE", 0, 3, &umr_bitfield_default },
+	 { "IMPCAL_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "IMPCAL_STATUS", 8, 9, &umr_bitfield_default },
+	 { "IMPCAL_ARB_STATE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_IMPCAL_PSW_EF[] = {
+	 { "UNIPHY_IMPCAL_PSW_LINKE", 0, 14, &umr_bitfield_default },
+	 { "UNIPHY_IMPCAL_PSW_LINKF", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_PINSTRAPS[] = {
+	 { "DC_PINSTRAPS_BIF_CEC_DIS", 10, 10, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_VIP_DEVICE", 11, 11, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_SMS_EN_HARD", 13, 13, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_AUDIO", 14, 15, &umr_bitfield_default },
+	 { "DC_PINSTRAPS_CCBYPASS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_CNTL[] = {
+	 { "LVTMA_PWRSEQ_EN", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_TARGET_STATE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN", 8, 8, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_OVRD", 9, 9, &umr_bitfield_default },
+	 { "LVTMA_SYNCEN_POL", 10, 10, &umr_bitfield_default },
+	 { "LVTMA_DIGON", 16, 16, &umr_bitfield_default },
+	 { "LVTMA_DIGON_OVRD", 17, 17, &umr_bitfield_default },
+	 { "LVTMA_DIGON_POL", 18, 18, &umr_bitfield_default },
+	 { "LVTMA_BLON", 24, 24, &umr_bitfield_default },
+	 { "LVTMA_BLON_OVRD", 25, 25, &umr_bitfield_default },
+	 { "LVTMA_BLON_POL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_STATE[] = {
+	 { "LVTMA_PWRSEQ_TARGET_STATE_R", 0, 0, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DIGON", 1, 1, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_SYNCEN", 2, 2, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_BLON", 3, 3, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_DONE", 4, 4, &umr_bitfield_default },
+	 { "LVTMA_PWRSEQ_STATE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_REF_DIV[] = {
+	 { "LVTMA_PWRSEQ_REF_DIV", 0, 11, &umr_bitfield_default },
+	 { "BL_PWM_REF_DIV", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY1[] = {
+	 { "LVTMA_PWRUP_DELAY1", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY2", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY1", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVTMA_PWRSEQ_DELAY2[] = {
+	 { "LVTMA_PWRDN_MIN_LENGTH", 0, 7, &umr_bitfield_default },
+	 { "LVTMA_PWRUP_DELAY3", 8, 15, &umr_bitfield_default },
+	 { "LVTMA_PWRDN_DELAY3", 16, 23, &umr_bitfield_default },
+	 { "LVTMA_VARY_BL_OVERRIDE_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL[] = {
+	 { "BL_ACTIVE_INT_FRAC_CNT", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_FRACTIONAL_EN", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_CNTL2[] = {
+	 { "BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE", 0, 15, &umr_bitfield_default },
+	 { "DBG_BL_PWM_INPUT_REFCLK_SELECT", 28, 29, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_BL_OUT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_PERIOD_CNTL[] = {
+	 { "BL_PWM_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "BL_PWM_PERIOD_BITCNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBL_PWM_GRP1_REG_LOCK[] = {
+	 { "BL_PWM_GRP1_REG_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_REG_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_UPDATE_AT_FRAME_START", 16, 16, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_FRAME_START_DISP_SEL", 17, 19, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN", 24, 24, &umr_bitfield_default },
+	 { "BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_GENLK_PAD_CNTL[] = {
+	 { "DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_GENLK_CLK_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_GENLK_VSYNC_GSL_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL_SWAPLOCK_PAD_CNTL[] = {
+	 { "DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL", 0, 1, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL", 4, 5, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_A_GSL_MASK", 8, 9, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL", 16, 17, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL", 20, 21, &umr_bitfield_default },
+	 { "DCIO_SWAPLOCK_B_GSL_MASK", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL0_CNTL[] = {
+	 { "DCIO_GSL0_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL0_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL0_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL1_CNTL[] = {
+	 { "DCIO_GSL1_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL1_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL1_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_GSL2_CNTL[] = {
+	 { "DCIO_GSL2_VSYNC_SEL", 0, 2, &umr_bitfield_default },
+	 { "DCIO_GSL2_TIMING_SYNC_SEL", 8, 10, &umr_bitfield_default },
+	 { "DCIO_GSL2_GLOBAL_UNLOCK_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_V_UPDATE[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_V_UPDATE", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_V_UPDATE", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_V_UPDATE", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_V_UPDATE", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_V_UPDATE", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_V_UPDATE", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_START_POSITION_P_FLIP[] = {
+	 { "DC_GPU_TIMER_START_POSITION_D1_P_FLIP", 0, 2, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_P_FLIP", 4, 6, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_P_FLIP", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_P_FLIP", 12, 14, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_P_FLIP", 16, 18, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_P_FLIP", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ[] = {
+	 { "DC_GPU_TIMER_READ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPU_TIMER_READ_CNTL[] = {
+	 { "DC_GPU_TIMER_READ_SELECT", 0, 5, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM", 8, 10, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM", 11, 13, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM", 14, 16, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM", 17, 19, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM", 20, 22, &umr_bitfield_default },
+	 { "DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_CNTL[] = {
+	 { "DCO_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCO_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_G_ABM_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_G_DVO_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_DACA_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_DACB_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_R_ABM_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGA_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGB_GATE_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGC_GATE_DIS", 26, 26, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGD_GATE_DIS", 27, 27, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGE_GATE_DIS", 28, 28, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGF_GATE_DIS", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGG_GATE_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_CLK_RAMP_CNTL[] = {
+	 { "DISPCLK_R_DCO_RAMP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_G_ABM_RAMP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DISPCLK_G_DVO_RAMP_DIS", 7, 7, &umr_bitfield_default },
+	 { "DISPCLK_G_DACA_RAMP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_DACB_RAMP_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_R_ABM_RAMP_DIS", 12, 12, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT0_RAMP_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT1_RAMP_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT2_RAMP_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT3_RAMP_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT4_RAMP_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_FMT5_RAMP_DIS", 21, 21, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGA_RAMP_DIS", 24, 24, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGB_RAMP_DIS", 25, 25, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGC_RAMP_DIS", 26, 26, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGD_RAMP_DIS", 27, 27, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGE_RAMP_DIS", 28, 28, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGF_RAMP_DIS", 29, 29, &umr_bitfield_default },
+	 { "DISPCLK_G_DIGG_RAMP_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_DEBUG[] = {
+	 { "DCIO_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_INDEX[] = {
+	 { "DCIO_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCIO_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCIO_TEST_DEBUG_DATA[] = {
+	 { "DCIO_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYAB_TPG_CONTROL[] = {
+	 { "UNIPHYAB_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHYAB_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHYAB_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYAB_TPG_SEED[] = {
+	 { "UNIPHYAB_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYCD_TPG_CONTROL[] = {
+	 { "UNIPHYCD_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHYCD_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHYCD_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYCD_TPG_SEED[] = {
+	 { "UNIPHYCD_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYEF_TPG_CONTROL[] = {
+	 { "UNIPHYEF_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHYEF_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHYEF_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYEF_TPG_SEED[] = {
+	 { "UNIPHYEF_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_DCFE_EXT_VSYNC_CNTL[] = {
+	 { "DCO_DCFE0_EXT_VSYNC_MUX", 0, 2, &umr_bitfield_default },
+	 { "DCO_DCFE1_EXT_VSYNC_MUX", 4, 6, &umr_bitfield_default },
+	 { "DCO_DCFE2_EXT_VSYNC_MUX", 8, 10, &umr_bitfield_default },
+	 { "DCO_DCFE3_EXT_VSYNC_MUX", 12, 14, &umr_bitfield_default },
+	 { "DCO_DCFE4_EXT_VSYNC_MUX", 16, 18, &umr_bitfield_default },
+	 { "DCO_DCFE5_EXT_VSYNC_MUX", 20, 22, &umr_bitfield_default },
+	 { "DCO_SWAPLOCKB_EXT_VSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DCO_GENERICB_EXT_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+	 { "DCO_CRTC_MANUAL_FLOW_CONTROL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYGH_TPG_CONTROL[] = {
+	 { "UNIPHYGH_STATIC_TEST_PATTERN", 0, 9, &umr_bitfield_default },
+	 { "UNIPHYGH_TPG_EN", 16, 16, &umr_bitfield_default },
+	 { "UNIPHYGH_TPG_SEL", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHYGH_TPG_SEED[] = {
+	 { "UNIPHYGH_TPG_SEED", 0, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCO_MEM_POWER_STATE_2[] = {
+	 { "DPG_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "HDMI6_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_STRENGTH[] = {
+	 { "I2S0_DRVSTRENGTH", 0, 2, &umr_bitfield_default },
+	 { "SPDIF0_DRVSTRENGTH", 8, 10, &umr_bitfield_default },
+	 { "I2S1_DRVSTRENGTH", 16, 18, &umr_bitfield_default },
+	 { "SPDIF1_DRVSTRENGTH", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_MASK[] = {
+	 { "DC_GPIO_I2SDATA0_MASK", 0, 3, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK0_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK0_MASK", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK0_MASK", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF0_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_I2SDATA1_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK1_MASK", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK1_MASK", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK1_MASK", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF1_MASK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_A[] = {
+	 { "DC_GPIO_I2SDATA0_A", 0, 3, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK0_A", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK0_A", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK0_A", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF0_A", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_I2SDATA1_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK1_A", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK1_A", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK1_A", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF1_A", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_EN[] = {
+	 { "DC_GPIO_I2SDATA0_EN", 0, 3, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK0_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK0_EN", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK0_EN", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF0_EN", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_I2SDATA1_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK1_EN", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK1_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK1_EN", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF1_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2S_SPDIF_Y[] = {
+	 { "DC_GPIO_I2SDATA0_Y", 0, 3, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK0_Y", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK0_Y", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK0_Y", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF0_Y", 7, 7, &umr_bitfield_default },
+	 { "DC_GPIO_I2SDATA1_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_MCLK1_Y", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_BCLK1_Y", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_LRCK1_Y", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SPDIF1_Y", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_MASK[] = {
+	 { "DC_GPIO_BLON_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_BLON_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_PD_DIS", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_RECV", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_A[] = {
+	 { "DC_GPIO_BLON_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_A", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_EN[] = {
+	 { "DC_GPIO_BLON_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VARY_BL_GENERICA_EN", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PWRSEQ_Y[] = {
+	 { "DC_GPIO_BLON_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DIGON_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_ENA_BL_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNC_IN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNC_IN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_MASK[] = {
+	 { "DC_GPIO_GENERICA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICA_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_PD_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_MASK", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_PD_DIS", 13, 13, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_RECV", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_A[] = {
+	 { "DC_GPIO_GENERICA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_A", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_A", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_A", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_A", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_EN[] = {
+	 { "DC_GPIO_GENERICA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_EN", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENERIC_Y[] = {
+	 { "DC_GPIO_GENERICA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICB_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICC_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICD_Y", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICE_Y", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICF_Y", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_GENERICG_Y", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_MASK[] = {
+	 { "DC_GPIO_DVODATA_MASK", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_MASK", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_MASK", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_MASK", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_A[] = {
+	 { "DC_GPIO_DVODATA_A", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_A", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_A", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_A", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_EN[] = {
+	 { "DC_GPIO_DVODATA_EN", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_EN", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_EN", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_EN", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DVODATA_Y[] = {
+	 { "DC_GPIO_DVODATA_Y", 0, 23, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCNTL_Y", 24, 28, &umr_bitfield_default },
+	 { "DC_GPIO_DVOCLK_Y", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_MVP_DVOCNTL_Y", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_MASK[] = {
+	 { "DC_GPIO_DDC1CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD1_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX1_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC1_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_A[] = {
+	 { "DC_GPIO_DDC1CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_EN[] = {
+	 { "DC_GPIO_DDC1CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC1_Y[] = {
+	 { "DC_GPIO_DDC1CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC1DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_MASK[] = {
+	 { "DC_GPIO_DDC2CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD2_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX2_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC2_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_A[] = {
+	 { "DC_GPIO_DDC2CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_EN[] = {
+	 { "DC_GPIO_DDC2CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC2_Y[] = {
+	 { "DC_GPIO_DDC2CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC2DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_MASK[] = {
+	 { "DC_GPIO_DDC3CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD3_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX3_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC3_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_A[] = {
+	 { "DC_GPIO_DDC3CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_EN[] = {
+	 { "DC_GPIO_DDC3CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC3_Y[] = {
+	 { "DC_GPIO_DDC3CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC3DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_MASK[] = {
+	 { "DC_GPIO_DDC4CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD4_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX4_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC4_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_A[] = {
+	 { "DC_GPIO_DDC4CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_EN[] = {
+	 { "DC_GPIO_DDC4CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC4_Y[] = {
+	 { "DC_GPIO_DDC4CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC4DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_MASK[] = {
+	 { "DC_GPIO_DDC5CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD5_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX5_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC5_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_A[] = {
+	 { "DC_GPIO_DDC5CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_EN[] = {
+	 { "DC_GPIO_DDC5CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC5_Y[] = {
+	 { "DC_GPIO_DDC5CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC5DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_MASK[] = {
+	 { "DC_GPIO_DDC6CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_PD_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD6_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUX6_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDC6_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6CLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_A[] = {
+	 { "DC_GPIO_DDC6CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_EN[] = {
+	 { "DC_GPIO_DDC6CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDC6_Y[] = {
+	 { "DC_GPIO_DDC6CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDC6DATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_MASK[] = {
+	 { "DC_GPIO_HSYNCA_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_PD_DIS", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_RECV", 14, 14, &umr_bitfield_default },
+	 { "DC_GPIO_HSYNCA_CRTC_HSYNC_MASK", 24, 26, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_CRTC_VSYNC_MASK", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_A[] = {
+	 { "DC_GPIO_HSYNCA_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_EN[] = {
+	 { "DC_GPIO_HSYNCA_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_SYNCA_Y[] = {
+	 { "DC_GPIO_HSYNCA_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_VSYNCA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_MASK[] = {
+	 { "DC_GPIO_GENLK_CLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_CLK_PU_EN", 3, 3, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_PU_EN", 11, 11, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_PU_EN", 19, 19, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_PU_EN", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_A[] = {
+	 { "DC_GPIO_GENLK_CLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_A", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_EN[] = {
+	 { "DC_GPIO_GENLK_CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_GENLK_Y[] = {
+	 { "DC_GPIO_GENLK_CLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_GENLK_VSYNC_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_A_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_SWAPLOCK_B_Y", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_MASK[] = {
+	 { "DC_GPIO_HPD1_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_PD_DIS", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_HPD1_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_PD_DIS", 9, 9, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_RECV", 10, 10, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_MASK", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_PD_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_RECV", 18, 18, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_MASK", 20, 20, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_PD_DIS", 21, 21, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_RECV", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_MASK", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_PD_DIS", 25, 25, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_RECV", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_MASK", 28, 28, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_PD_DIS", 29, 29, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_RECV", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_A[] = {
+	 { "DC_GPIO_HPD1_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_A", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_A", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_A", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_A", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_A", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_EN[] = {
+	 { "DC_GPIO_HPD1_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_EN", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_EN", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_EN", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_EN", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_HPD_Y[] = {
+	 { "DC_GPIO_HPD1_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_HPD2_Y", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_HPD3_Y", 16, 16, &umr_bitfield_default },
+	 { "DC_GPIO_HPD4_Y", 24, 24, &umr_bitfield_default },
+	 { "DC_GPIO_HPD5_Y", 26, 26, &umr_bitfield_default },
+	 { "DC_GPIO_HPD6_Y", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_MASK[] = {
+	 { "DC_GPIO_DDCVGACLK_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_RECV", 6, 6, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_MASK", 8, 8, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_PD_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_RECV", 14, 14, &umr_bitfield_default },
+	 { "AUX_PADVGA_MODE", 16, 16, &umr_bitfield_default },
+	 { "AUXVGA_POL", 20, 20, &umr_bitfield_default },
+	 { "ALLOW_HW_DDCVGA_PD_EN", 22, 22, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGACLK_STR", 24, 27, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_STR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_A[] = {
+	 { "DC_GPIO_DDCVGACLK_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_A", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_EN[] = {
+	 { "DC_GPIO_DDCVGACLK_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_DDCVGA_Y[] = {
+	 { "DC_GPIO_DDCVGACLK_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_DDCVGADATA_Y", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_MASK[] = {
+	 { "DC_GPIO_SCL_MASK", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SCL_PD_DIS", 1, 1, &umr_bitfield_default },
+	 { "DC_GPIO_SCL_RECV", 2, 2, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_MASK", 4, 4, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_PD_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_RECV", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_A[] = {
+	 { "DC_GPIO_SCL_A", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_A", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_EN[] = {
+	 { "DC_GPIO_SCL_EN", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_Y[] = {
+	 { "DC_GPIO_SCL_Y", 0, 0, &umr_bitfield_default },
+	 { "DC_GPIO_SDA_Y", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_1[] = {
+	 { "GENLK_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GENLK_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SN", 24, 27, &umr_bitfield_default },
+	 { "SYNC_STRENGTH_SP", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_PAD_STRENGTH_2[] = {
+	 { "STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "STRENGTH_SP", 4, 7, &umr_bitfield_default },
+	 { "EXT_RESET_DRVSTRENGTH", 8, 10, &umr_bitfield_default },
+	 { "REF_27_DRVSTRENGTH", 12, 14, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SN", 16, 19, &umr_bitfield_default },
+	 { "PWRSEQ_STRENGTH_SP", 20, 23, &umr_bitfield_default },
+	 { "REF_27_SRC_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_GPIO_I2CPAD_STRENGTH[] = {
+	 { "I2C_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "I2C_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_STRENGTH_CONTROL[] = {
+	 { "DVO_SP", 0, 3, &umr_bitfield_default },
+	 { "DVO_SN", 4, 7, &umr_bitfield_default },
+	 { "DVOCLK_SP", 8, 11, &umr_bitfield_default },
+	 { "DVOCLK_SN", 12, 15, &umr_bitfield_default },
+	 { "DVO_DRVSTRENGTH", 16, 18, &umr_bitfield_default },
+	 { "DVOCLK_DRVSTRENGTH", 20, 22, &umr_bitfield_default },
+	 { "FLDO_VITNE_DRVSTRENGTH", 24, 26, &umr_bitfield_default },
+	 { "DVO_LSB_VMODE", 28, 28, &umr_bitfield_default },
+	 { "DVO_MSB_VMODE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_VREF_CONTROL[] = {
+	 { "DVO_VREFPON", 0, 0, &umr_bitfield_default },
+	 { "DVO_VREFSEL", 1, 1, &umr_bitfield_default },
+	 { "DVO_VREFCAL", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDVO_SKEW_ADJUST[] = {
+	 { "DVO_SKEW_ADJUST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPHY_AUX_CNTL[] = {
+	 { "AUX_PAD_SLEWN", 12, 12, &umr_bitfield_default },
+	 { "AUX_PAD_WAKE", 14, 14, &umr_bitfield_default },
+	 { "AUX_PAD_RXSEL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL1[] = {
+	 { "UNIPHY_PREMPH_STR0", 0, 2, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR1", 4, 6, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR2", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR3", 12, 14, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR4", 16, 18, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS0", 20, 21, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS1", 22, 23, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS2", 24, 25, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS3", 26, 27, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS4", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL2[] = {
+	 { "UNIPHY_PREMPH0_PC", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH1_PC", 4, 5, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH2_PC", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH3_PC", 12, 13, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH4_PC", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_SEL", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_RT0_CPSEL", 21, 22, &umr_bitfield_default },
+	 { "UNIPHY_RT1_CPSEL", 23, 24, &umr_bitfield_default },
+	 { "UNIPHY_RT2_CPSEL", 25, 26, &umr_bitfield_default },
+	 { "UNIPHY_RT3_CPSEL", 27, 28, &umr_bitfield_default },
+	 { "UNIPHY_RT4_CPSEL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL3[] = {
+	 { "UNIPHY_PREMPH_PW_CLK", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_PW_DAT", 2, 3, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_CS_CLK", 4, 7, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_CS_DAT", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR_CLK", 12, 14, &umr_bitfield_default },
+	 { "UNIPHY_PREMPH_STR_DAT", 16, 18, &umr_bitfield_default },
+	 { "UNIPHY_PESEL0", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_PESEL1", 21, 21, &umr_bitfield_default },
+	 { "UNIPHY_PESEL2", 22, 22, &umr_bitfield_default },
+	 { "UNIPHY_PESEL3", 23, 23, &umr_bitfield_default },
+	 { "UNIPHY_TX_VS_ADJ", 24, 28, &umr_bitfield_default },
+	 { "UNIPHY_LVDS_PULLDWN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_TX_CONTROL4[] = {
+	 { "UNIPHY_TX_NVS_CLK", 0, 4, &umr_bitfield_default },
+	 { "UNIPHY_TX_NVS_DAT", 5, 9, &umr_bitfield_default },
+	 { "UNIPHY_TX_PVS_CLK", 12, 16, &umr_bitfield_default },
+	 { "UNIPHY_TX_PVS_DAT", 17, 21, &umr_bitfield_default },
+	 { "UNIPHY_TX_OP_CLK", 24, 26, &umr_bitfield_default },
+	 { "UNIPHY_TX_OP_DAT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_POWER_CONTROL[] = {
+	 { "UNIPHY_BGPDN", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_RST_LOGIC", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_BIASREF_SEL", 2, 2, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ1P00", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ1P25", 12, 15, &umr_bitfield_default },
+	 { "UNIPHY_BGADJ0P45", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_FBDIV[] = {
+	 { "UNIPHY_PLL_FBDIV_FRACTION", 2, 15, &umr_bitfield_default },
+	 { "UNIPHY_PLL_FBDIV", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_CONTROL1[] = {
+	 { "UNIPHY_PLL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PLL_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_PLL_EXT_RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "UNIPHY_PLL_CLK_EN", 3, 3, &umr_bitfield_default },
+	 { "UNIPHY_PLL_CLKPH_EN", 4, 7, &umr_bitfield_default },
+	 { "UNIPHY_PLL_LF_CNTL", 8, 14, &umr_bitfield_default },
+	 { "UNIPHY_PLL_BW_CNTL", 16, 23, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_BYPCLK_SRC", 24, 24, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_BYPCLK_EN", 25, 25, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL_ADC_EN", 26, 26, &umr_bitfield_default },
+	 { "UNIPHY_VCO_MODE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_CONTROL2[] = {
+	 { "UNIPHY_PLL_DISPCLK_MODE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_DPLLSEL", 2, 3, &umr_bitfield_default },
+	 { "UNIPHY_IDCLK_SEL", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_IPCIE_REFCLK_SEL", 5, 5, &umr_bitfield_default },
+	 { "UNIPHY_IXTALIN_SEL", 6, 6, &umr_bitfield_default },
+	 { "UNIPHY_PLL_REFCLK_SRC", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_PCIEREF_CLK_EN", 11, 11, &umr_bitfield_default },
+	 { "UNIPHY_IDCLK_EN", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CLKINV", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_PLL_VTOI_BIAS_CNTL", 16, 16, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS", 19, 19, &umr_bitfield_default },
+	 { "UNIPHY_PDIVFRAC_SEL", 20, 20, &umr_bitfield_default },
+	 { "UNIPHY_PLL_REFDIV", 24, 28, &umr_bitfield_default },
+	 { "UNIPHY_PDIV_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_SS_STEP_SIZE[] = {
+	 { "UNIPHY_PLL_SS_STEP_SIZE", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_PLL_SS_CNTL[] = {
+	 { "UNIPHY_PLL_SS_STEP_NUM", 0, 11, &umr_bitfield_default },
+	 { "UNIPHY_PLL_DSMOD_EN", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_PLL_SS_EN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_DATA_SYNCHRONIZATION[] = {
+	 { "UNIPHY_DSYNSEL", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_DSYN_LEVEL", 4, 5, &umr_bitfield_default },
+	 { "UNIPHY_DSYN_ERROR", 6, 6, &umr_bitfield_default },
+	 { "UNIPHY_SOURCE_SELECT", 8, 8, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_DUAL_LINK_PHASE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_REG_TEST_OUTPUT[] = {
+	 { "UNIPHY_TEST_CNTL", 0, 4, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL", 5, 8, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_SSAMP_EN", 9, 9, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_UNLOCK_CLR", 10, 10, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_RESET", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_SEL", 16, 16, &umr_bitfield_default },
+	 { "UNIPHY_TEST_VCTL_EN", 17, 17, &umr_bitfield_default },
+	 { "UNIPHY_DIG_BIST_ERROR", 20, 24, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_VCTL_ADC", 25, 27, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_FREQ_LOCK", 28, 28, &umr_bitfield_default },
+	 { "UNIPHY_PLL_INTRESET", 29, 29, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_UNLOCK_STICKY", 30, 30, &umr_bitfield_default },
+	 { "UNIPHY_PLL_TEST_LOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_ANG_BIST_CNTL[] = {
+	 { "UNIPHY_TEST_RX_EN", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_ANG_BIST_RESET", 1, 1, &umr_bitfield_default },
+	 { "UNIPHY_RX_BIAS", 8, 11, &umr_bitfield_default },
+	 { "UNIPHY_ANG_BIST_ERROR", 16, 20, &umr_bitfield_default },
+	 { "UNIPHY_PRESETB", 24, 24, &umr_bitfield_default },
+	 { "UNIPHY_BIST_EN", 25, 25, &umr_bitfield_default },
+	 { "UNIPHY_CLK_CH_EN4_DFT", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_LINK_CNTL[] = {
+	 { "UNIPHY_PFREQCHG", 0, 0, &umr_bitfield_default },
+	 { "UNIPHY_PIXVLD_RESET", 4, 4, &umr_bitfield_default },
+	 { "UNIPHY_MINIMUM_PIXVLD_LOW_DURATION", 8, 10, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL0_INVERT", 12, 12, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_INVERT", 13, 13, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_INVERT", 14, 14, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_INVERT", 15, 15, &umr_bitfield_default },
+	 { "UNIPHY_LINK_ENABLE_HPD_MASK", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_LANE_STAGGER_DELAY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_CHANNEL_XBAR_CNTL[] = {
+	 { "UNIPHY_CHANNEL0_XBAR_SOURCE", 0, 1, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL1_XBAR_SOURCE", 8, 9, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL2_XBAR_SOURCE", 16, 17, &umr_bitfield_default },
+	 { "UNIPHY_CHANNEL3_XBAR_SOURCE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUNIPHY_REG_TEST_OUTPUT2[] = {
+	 { "UNIPHY_TX", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE6[] = {
+	 { "DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DIGG_DP_VID_STREAM_DISABLE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "AUX1_GTC_SYNC_ERROR_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "AUX2_GTC_SYNC_ERROR_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "AUX3_GTC_SYNC_ERROR_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "AUX4_GTC_SYNC_ERROR_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "AUX5_GTC_SYNC_ERROR_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "AUX6_GTC_SYNC_ERROR_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE7[] = {
+	 { "DCCG_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCCG_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCI_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCO_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER0_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER1_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER2_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER3_INTERRUPT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE8", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE8[] = {
+	 { "DCFE0_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCFE0_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCFE1_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCFE2_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER4_INTERRUPT", 27, 27, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER5_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER6_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER7_INTERRUPT", 30, 30, &umr_bitfield_default },
+	 { "DISP_INTERRUPT_STATUS_CONTINUE9", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDISP_INTERRUPT_STATUS_CONTINUE9[] = {
+	 { "DCFE3_PERFMON_COUNTER0_INTERRUPT", 0, 0, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER1_INTERRUPT", 1, 1, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER2_INTERRUPT", 2, 2, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER3_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER4_INTERRUPT", 4, 4, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER5_INTERRUPT", 5, 5, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER6_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER7_INTERRUPT", 7, 7, &umr_bitfield_default },
+	 { "DCFE3_PERFMON_COUNTER_OFF_INTERRUPT", 8, 8, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER0_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER1_INTERRUPT", 10, 10, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER2_INTERRUPT", 11, 11, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER3_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER4_INTERRUPT", 13, 13, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER5_INTERRUPT", 14, 14, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER6_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER7_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "DCFE4_PERFMON_COUNTER_OFF_INTERRUPT", 17, 17, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER0_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER1_INTERRUPT", 19, 19, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER2_INTERRUPT", 20, 20, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER3_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER4_INTERRUPT", 22, 22, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER5_INTERRUPT", 23, 23, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER6_INTERRUPT", 24, 24, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER7_INTERRUPT", 25, 25, &umr_bitfield_default },
+	 { "DCFE5_PERFMON_COUNTER_OFF_INTERRUPT", 26, 26, &umr_bitfield_default },
+	 { "SCANIN_PERFMON_COUNTER_OFF_INTERRUPT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_ENABLE[] = {
+	 { "DAC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_POINTER_SKEW", 2, 3, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR", 4, 4, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_ERROR_ACK", 5, 5, &umr_bitfield_default },
+	 { "DAC_RESYNC_FIFO_TVOUT_SIM", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SOURCE_SELECT[] = {
+	 { "DAC_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DAC_TV_SELECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_EN[] = {
+	 { "DAC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_CONT_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_CONTROL[] = {
+	 { "DAC_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DAC_CRC_ONLY_BLANKb", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB_MASK[] = {
+	 { "DAC_CRC_SIG_BLUE_MASK", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN_MASK", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED_MASK", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL_MASK[] = {
+	 { "DAC_CRC_SIG_CONTROL_MASK", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_RGB[] = {
+	 { "DAC_CRC_SIG_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DAC_CRC_SIG_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CRC_SIG_CONTROL[] = {
+	 { "DAC_CRC_SIG_CONTROL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_SYNC_TRISTATE_CONTROL[] = {
+	 { "DAC_HSYNCA_TRISTATE", 0, 0, &umr_bitfield_default },
+	 { "DAC_VSYNCA_TRISTATE", 8, 8, &umr_bitfield_default },
+	 { "DAC_SYNCA_TRISTATE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_STEREOSYNC_SELECT[] = {
+	 { "DAC_STEREOSYNC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL[] = {
+	 { "DAC_AUTODETECT_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_FRAME_TIME_COUNTER", 8, 15, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CHECK_MASK", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL2[] = {
+	 { "DAC_AUTODETECT_POWERUP_COUNTER", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_TESTMODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_CONTROL3[] = {
+	 { "DAC_AUTODET_COMPARATOR_IN_DELAY", 0, 7, &umr_bitfield_default },
+	 { "DAC_AUTODET_COMPARATOR_OUT_DELAY", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_STATUS[] = {
+	 { "DAC_AUTODETECT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_CONNECT", 4, 4, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_RED_SENSE", 8, 9, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_GREEN_SENSE", 16, 17, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_BLUE_SENSE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_AUTODETECT_INT_CONTROL[] = {
+	 { "DAC_AUTODETECT_ACK", 0, 0, &umr_bitfield_default },
+	 { "DAC_AUTODETECT_INT_ENABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_OUTPUT_CNTL[] = {
+	 { "DAC_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_SEL", 8, 10, &umr_bitfield_default },
+	 { "DAC_FORCE_DATA_ON_BLANKb_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FORCE_DATA[] = {
+	 { "DAC_FORCE_DATA", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_POWERDOWN[] = {
+	 { "DAC_POWERDOWN", 0, 0, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_BLUE", 8, 8, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_GREEN", 16, 16, &umr_bitfield_default },
+	 { "DAC_POWERDOWN_RED", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_CONTROL[] = {
+	 { "DAC_DFORCE_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_TV_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DAC_ZSCALE_SHIFT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_ENABLE[] = {
+	 { "DAC_COMP_DDET_REF_EN", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMP_SDET_REF_EN", 8, 8, &umr_bitfield_default },
+	 { "DAC_R_ASYNC_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DAC_G_ASYNC_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "DAC_B_ASYNC_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_COMPARATOR_OUTPUT[] = {
+	 { "DAC_COMPARATOR_OUTPUT", 0, 0, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_BLUE", 1, 1, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_GREEN", 2, 2, &umr_bitfield_default },
+	 { "DAC_COMPARATOR_OUTPUT_RED", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_PWR_CNTL[] = {
+	 { "DAC_BG_MODE", 0, 1, &umr_bitfield_default },
+	 { "DAC_PWRCNTL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_DFT_CONFIG[] = {
+	 { "DAC_DFT_CONFIG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_FIFO_STATUS[] = {
+	 { "DAC_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DAC_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DAC_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DAC_FIFO_MAXIMUM_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "DAC_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DAC_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DAC_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED0[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED1[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_MACRO_CNTL[] = {
+	 { "BPHYC_DAC_WHITE_LEVEL", 0, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_WHITE_FINE_CONTROL", 8, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_BANDGAP_ADJUSTMENT", 16, 21, &umr_bitfield_default },
+	 { "BPHYC_DAC_ANALOG_MONITOR", 24, 27, &umr_bitfield_default },
+	 { "BPHYC_DAC_COREMON", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBPHYC_DAC_AUTO_CALIB_CONTROL[] = {
+	 { "BPHYC_DAC_CAL_INITB", 0, 0, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_EN", 1, 1, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_DACADJ_EN", 2, 2, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_WAIT_ADJUST", 4, 13, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_MASK", 20, 22, &umr_bitfield_default },
+	 { "BPHYC_DAC_CAL_COMPLETE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED2[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MACRO_CNTL_RESERVED3[] = {
+	 { "DAC_MACRO_CNTL_RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIMMEDIATE_COMMAND_STATUS[] = {
+	 { "IMMEDIATE_COMMAND_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IMMEDIATE_RESULT_VALID", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_K[] = {
+	 { "DP_AUX1_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_ENABLE[] = {
+	 { "GRPH_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_CONTROL[] = {
+	 { "GRPH_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "GRPH_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "GRPH_Z", 4, 5, &umr_bitfield_default },
+	 { "GRPH_BANK_WIDTH", 6, 7, &umr_bitfield_default },
+	 { "GRPH_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "GRPH_BANK_HEIGHT", 11, 12, &umr_bitfield_default },
+	 { "GRPH_TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "GRPH_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "GRPH_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "GRPH_MACRO_TILE_ASPECT", 18, 19, &umr_bitfield_default },
+	 { "GRPH_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "GRPH_PIPE_CONFIG", 24, 28, &umr_bitfield_default },
+	 { "GRPH_MICRO_TILE_MODE", 29, 30, &umr_bitfield_default },
+	 { "GRPH_COLOR_EXPANSION_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_LUT_10BIT_BYPASS[] = {
+	 { "GRPH_LUT_10BIT_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SWAP_CNTL[] = {
+	 { "GRPH_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "GRPH_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "GRPH_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "GRPH_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+	 { "GRPH_ALPHA_CROSSBAR", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PRIMARY_SURFACE_ADDRESS[] = {
+	 { "GRPH_PRIMARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SECONDARY_SURFACE_ADDRESS[] = {
+	 { "GRPH_SECONDARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PITCH[] = {
+	 { "GRPH_PITCH", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_OFFSET_X[] = {
+	 { "GRPH_SURFACE_OFFSET_X", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_OFFSET_Y[] = {
+	 { "GRPH_SURFACE_OFFSET_Y", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_X_START[] = {
+	 { "GRPH_X_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_Y_START[] = {
+	 { "GRPH_Y_START", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_X_END[] = {
+	 { "GRPH_X_END", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_Y_END[] = {
+	 { "GRPH_Y_END", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_GAMMA_CONTROL[] = {
+	 { "GRPH_INPUT_GAMMA_MODE", 0, 1, &umr_bitfield_default },
+	 { "OVL_INPUT_GAMMA_MODE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_UPDATE[] = {
+	 { "GRPH_MODE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "GRPH_MODE_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "GRPH_SURFACE_UPDATE_TAKEN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_SURFACE_XDMA_PENDING_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "GRPH_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SURFACE_IGNORE_UPDATE_LOCK", 20, 20, &umr_bitfield_default },
+	 { "GRPH_MODE_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_FLIP_CONTROL[] = {
+	 { "GRPH_SURFACE_UPDATE_H_RETRACE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_ADDRESS_INUSE[] = {
+	 { "GRPH_SURFACE_ADDRESS_INUSE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_DFQ_CONTROL[] = {
+	 { "GRPH_DFQ_RESET", 0, 0, &umr_bitfield_default },
+	 { "GRPH_DFQ_SIZE", 4, 6, &umr_bitfield_default },
+	 { "GRPH_DFQ_MIN_FREE_ENTRIES", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_DFQ_STATUS[] = {
+	 { "GRPH_PRIMARY_DFQ_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_DFQ_NUM_ENTRIES", 4, 7, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "GRPH_DFQ_RESET_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_INTERRUPT_STATUS[] = {
+	 { "GRPH_PFLIP_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_INTERRUPT_CONTROL[] = {
+	 { "GRPH_PFLIP_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PFLIP_INT_TYPE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[] = {
+	 { "GRPH_SURFACE_ADDRESS_HIGH_INUSE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_SURFACE_ADDRESS[] = {
+	 { "GRPH_COMPRESS_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_PITCH[] = {
+	 { "GRPH_COMPRESS_PITCH", 6, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_ENABLE[] = {
+	 { "OVL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OVLSCL_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_CONTROL1[] = {
+	 { "OVL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "OVL_NUM_BANKS", 2, 3, &umr_bitfield_default },
+	 { "OVL_Z", 4, 5, &umr_bitfield_default },
+	 { "OVL_BANK_WIDTH", 6, 7, &umr_bitfield_default },
+	 { "OVL_FORMAT", 8, 10, &umr_bitfield_default },
+	 { "OVL_BANK_HEIGHT", 11, 12, &umr_bitfield_default },
+	 { "OVL_TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "OVL_ADDRESS_TRANSLATION_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OVL_PRIVILEGED_ACCESS_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "OVL_MACRO_TILE_ASPECT", 18, 19, &umr_bitfield_default },
+	 { "OVL_ARRAY_MODE", 20, 23, &umr_bitfield_default },
+	 { "OVL_COLOR_EXPANSION_MODE", 24, 24, &umr_bitfield_default },
+	 { "OVL_PIPE_CONFIG", 25, 29, &umr_bitfield_default },
+	 { "OVL_MICRO_TILE_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_CONTROL2[] = {
+	 { "OVL_HALF_RESOLUTION_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SWAP_CNTL[] = {
+	 { "OVL_ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+	 { "OVL_RED_CROSSBAR", 4, 5, &umr_bitfield_default },
+	 { "OVL_GREEN_CROSSBAR", 6, 7, &umr_bitfield_default },
+	 { "OVL_BLUE_CROSSBAR", 8, 9, &umr_bitfield_default },
+	 { "OVL_ALPHA_CROSSBAR", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_ADDRESS[] = {
+	 { "OVL_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OVL_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_PITCH[] = {
+	 { "OVL_PITCH", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_ADDRESS_HIGH[] = {
+	 { "OVL_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_OFFSET_X[] = {
+	 { "OVL_SURFACE_OFFSET_X", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_OFFSET_Y[] = {
+	 { "OVL_SURFACE_OFFSET_Y", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_START[] = {
+	 { "OVL_Y_START", 0, 13, &umr_bitfield_default },
+	 { "OVL_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_END[] = {
+	 { "OVL_Y_END", 0, 14, &umr_bitfield_default },
+	 { "OVL_X_END", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_UPDATE[] = {
+	 { "OVL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "OVL_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "OVL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "OVL_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_ADDRESS_INUSE[] = {
+	 { "OVL_SURFACE_ADDRESS_INUSE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_DFQ_CONTROL[] = {
+	 { "OVL_DFQ_RESET", 0, 0, &umr_bitfield_default },
+	 { "OVL_DFQ_SIZE", 4, 6, &umr_bitfield_default },
+	 { "OVL_DFQ_MIN_FREE_ENTRIES", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_DFQ_STATUS[] = {
+	 { "OVL_DFQ_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "OVL_SECONDARY_DFQ_NUM_ENTRIES", 4, 7, &umr_bitfield_default },
+	 { "OVL_DFQ_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "OVL_DFQ_RESET_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SURFACE_ADDRESS_HIGH_INUSE[] = {
+	 { "OVL_SURFACE_ADDRESS_HIGH_INUSE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVLSCL_EDGE_PIXEL_CNTL[] = {
+	 { "OVLSCL_BLACK_COLOR_BCB", 0, 9, &umr_bitfield_default },
+	 { "OVLSCL_BLACK_COLOR_GY", 10, 19, &umr_bitfield_default },
+	 { "OVLSCL_BLACK_COLOR_RCR", 20, 29, &umr_bitfield_default },
+	 { "OVLSCL_EDGE_PIXEL_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_GRPH_CONTROL[] = {
+	 { "GRPH_PRESCALE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_R_SIGN", 1, 1, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_G_SIGN", 2, 2, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_B_SIGN", 3, 3, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_BYPASS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_R[] = {
+	 { "GRPH_PRESCALE_BIAS_R", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_G[] = {
+	 { "GRPH_PRESCALE_BIAS_G", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_GRPH_B[] = {
+	 { "GRPH_PRESCALE_BIAS_B", 0, 15, &umr_bitfield_default },
+	 { "GRPH_PRESCALE_SCALE_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_OVL_CONTROL[] = {
+	 { "OVL_PRESCALE_SELECT", 0, 0, &umr_bitfield_default },
+	 { "OVL_PRESCALE_CB_SIGN", 1, 1, &umr_bitfield_default },
+	 { "OVL_PRESCALE_Y_SIGN", 2, 2, &umr_bitfield_default },
+	 { "OVL_PRESCALE_CR_SIGN", 3, 3, &umr_bitfield_default },
+	 { "OVL_PRESCALE_BYPASS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_OVL_CB[] = {
+	 { "OVL_PRESCALE_BIAS_CB", 0, 15, &umr_bitfield_default },
+	 { "OVL_PRESCALE_SCALE_CB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_OVL_Y[] = {
+	 { "OVL_PRESCALE_BIAS_Y", 0, 15, &umr_bitfield_default },
+	 { "OVL_PRESCALE_SCALE_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPRESCALE_VALUES_OVL_CR[] = {
+	 { "OVL_PRESCALE_BIAS_CR", 0, 15, &umr_bitfield_default },
+	 { "OVL_PRESCALE_SCALE_CR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_CONTROL[] = {
+	 { "INPUT_CSC_GRPH_MODE", 0, 1, &umr_bitfield_default },
+	 { "INPUT_CSC_OVL_MODE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C11_C12[] = {
+	 { "INPUT_CSC_C11", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C13_C14[] = {
+	 { "INPUT_CSC_C13", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C21_C22[] = {
+	 { "INPUT_CSC_C21", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C23_C24[] = {
+	 { "INPUT_CSC_C23", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C31_C32[] = {
+	 { "INPUT_CSC_C31", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINPUT_CSC_C33_C34[] = {
+	 { "INPUT_CSC_C33", 0, 15, &umr_bitfield_default },
+	 { "INPUT_CSC_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_CONTROL[] = {
+	 { "OUTPUT_CSC_GRPH_MODE", 0, 2, &umr_bitfield_default },
+	 { "OUTPUT_CSC_OVL_MODE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C11_C12[] = {
+	 { "OUTPUT_CSC_C11", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C13_C14[] = {
+	 { "OUTPUT_CSC_C13", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C21_C22[] = {
+	 { "OUTPUT_CSC_C21", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C23_C24[] = {
+	 { "OUTPUT_CSC_C23", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C31_C32[] = {
+	 { "OUTPUT_CSC_C31", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_CSC_C33_C34[] = {
+	 { "OUTPUT_CSC_C33", 0, 15, &umr_bitfield_default },
+	 { "OUTPUT_CSC_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXA_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXA_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXA_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXA_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXA_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXA_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXA_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXA_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C11_C12[] = {
+	 { "COMM_MATRIXB_TRANS_C11", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C13_C14[] = {
+	 { "COMM_MATRIXB_TRANS_C13", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C21_C22[] = {
+	 { "COMM_MATRIXB_TRANS_C21", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C23_C24[] = {
+	 { "COMM_MATRIXB_TRANS_C23", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C31_C32[] = {
+	 { "COMM_MATRIXB_TRANS_C31", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMM_MATRIXB_TRANS_C33_C34[] = {
+	 { "COMM_MATRIXB_TRANS_C33", 0, 15, &umr_bitfield_default },
+	 { "COMM_MATRIXB_TRANS_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDENORM_CONTROL[] = {
+	 { "DENORM_MODE", 0, 2, &umr_bitfield_default },
+	 { "DENORM_14BIT_OUT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_ROUND_CONTROL[] = {
+	 { "OUT_ROUND_TRUNC_MODE", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_R_CR[] = {
+	 { "OUT_CLAMP_MAX_R_CR", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_R_CR", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_CONTROL[] = {
+	 { "KEY_SELECT", 0, 0, &umr_bitfield_default },
+	 { "KEY_MODE", 1, 2, &umr_bitfield_default },
+	 { "GRPH_OVL_HALF_BLEND", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_ALPHA[] = {
+	 { "KEY_ALPHA_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_ALPHA_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_RED[] = {
+	 { "KEY_RED_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_RED_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_GREEN[] = {
+	 { "KEY_GREEN_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_GREEN_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmKEY_RANGE_BLUE[] = {
+	 { "KEY_BLUE_LOW", 0, 15, &umr_bitfield_default },
+	 { "KEY_BLUE_HIGH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEGAMMA_CONTROL[] = {
+	 { "GRPH_DEGAMMA_MODE", 0, 1, &umr_bitfield_default },
+	 { "OVL_DEGAMMA_MODE", 4, 5, &umr_bitfield_default },
+	 { "CURSOR2_DEGAMMA_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_DEGAMMA_MODE", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_CONTROL[] = {
+	 { "GRPH_GAMUT_REMAP_MODE", 0, 1, &umr_bitfield_default },
+	 { "OVL_GAMUT_REMAP_MODE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C11_C12[] = {
+	 { "GAMUT_REMAP_C11", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C13_C14[] = {
+	 { "GAMUT_REMAP_C13", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C21_C22[] = {
+	 { "GAMUT_REMAP_C21", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C22", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C23_C24[] = {
+	 { "GAMUT_REMAP_C23", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C24", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C31_C32[] = {
+	 { "GAMUT_REMAP_C31", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C32", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGAMUT_REMAP_C33_C34[] = {
+	 { "GAMUT_REMAP_C33", 0, 15, &umr_bitfield_default },
+	 { "GAMUT_REMAP_C34", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_SPATIAL_DITHER_CNTL[] = {
+	 { "DCP_SPATIAL_DITHER_EN", 0, 0, &umr_bitfield_default },
+	 { "DCP_SPATIAL_DITHER_MODE", 4, 5, &umr_bitfield_default },
+	 { "DCP_SPATIAL_DITHER_DEPTH", 6, 7, &umr_bitfield_default },
+	 { "DCP_FRAME_RANDOM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DCP_RGB_RANDOM_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "DCP_HIGHPASS_RANDOM_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_RANDOM_SEEDS[] = {
+	 { "DCP_RAND_R_SEED", 0, 7, &umr_bitfield_default },
+	 { "DCP_RAND_G_SEED", 8, 15, &umr_bitfield_default },
+	 { "DCP_RAND_B_SEED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_FP_CONVERTED_FIELD[] = {
+	 { "DCP_FP_CONVERTED_FIELD_DATA", 0, 17, &umr_bitfield_default },
+	 { "DCP_FP_CONVERTED_FIELD_INDEX", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_CONTROL[] = {
+	 { "CURSOR_EN", 0, 0, &umr_bitfield_default },
+	 { "CUR_INV_TRANS_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "CURSOR_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR_2X_MAGNIFY", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_FORCE_MC_ON", 20, 20, &umr_bitfield_default },
+	 { "CURSOR_URGENT_CONTROL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS[] = {
+	 { "CURSOR_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SIZE[] = {
+	 { "CURSOR_HEIGHT", 0, 6, &umr_bitfield_default },
+	 { "CURSOR_WIDTH", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_SURFACE_ADDRESS_HIGH[] = {
+	 { "CURSOR_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_POSITION[] = {
+	 { "CURSOR_Y_POSITION", 0, 13, &umr_bitfield_default },
+	 { "CURSOR_X_POSITION", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_HOT_SPOT[] = {
+	 { "CURSOR_HOT_SPOT_Y", 0, 6, &umr_bitfield_default },
+	 { "CURSOR_HOT_SPOT_X", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR1[] = {
+	 { "CUR_COLOR1_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR1_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR1_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_COLOR2[] = {
+	 { "CUR_COLOR2_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR_COLOR2_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR_COLOR2_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_UPDATE[] = {
+	 { "CURSOR_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "CURSOR_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "CURSOR_UPDATE_STEREO_MODE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_CONTROL[] = {
+	 { "CURSOR2_EN", 0, 0, &umr_bitfield_default },
+	 { "CUR2_INV_TRANS_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "CURSOR2_MODE", 8, 9, &umr_bitfield_default },
+	 { "CURSOR2_2X_MAGNIFY", 16, 16, &umr_bitfield_default },
+	 { "CURSOR2_FORCE_MC_ON", 20, 20, &umr_bitfield_default },
+	 { "CURSOR2_URGENT_CONTROL", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_SURFACE_ADDRESS[] = {
+	 { "CURSOR2_SURFACE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_SIZE[] = {
+	 { "CURSOR2_HEIGHT", 0, 6, &umr_bitfield_default },
+	 { "CURSOR2_WIDTH", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_SURFACE_ADDRESS_HIGH[] = {
+	 { "CURSOR2_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_POSITION[] = {
+	 { "CURSOR2_Y_POSITION", 0, 13, &umr_bitfield_default },
+	 { "CURSOR2_X_POSITION", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_HOT_SPOT[] = {
+	 { "CURSOR2_HOT_SPOT_Y", 0, 6, &umr_bitfield_default },
+	 { "CURSOR2_HOT_SPOT_X", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_COLOR1[] = {
+	 { "CUR2_COLOR1_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR2_COLOR1_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR2_COLOR1_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_COLOR2[] = {
+	 { "CUR2_COLOR2_BLUE", 0, 7, &umr_bitfield_default },
+	 { "CUR2_COLOR2_GREEN", 8, 15, &umr_bitfield_default },
+	 { "CUR2_COLOR2_RED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_UPDATE[] = {
+	 { "CURSOR2_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CURSOR2_UPDATE_TAKEN", 1, 1, &umr_bitfield_default },
+	 { "CURSOR2_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "CURSOR2_DISABLE_MULTIPLE_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "CURSOR2_UPDATE_STEREO_MODE", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_MODE[] = {
+	 { "DC_LUT_RW_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_RW_INDEX[] = {
+	 { "DC_LUT_RW_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_SEQ_COLOR[] = {
+	 { "DC_LUT_SEQ_COLOR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_PWL_DATA[] = {
+	 { "DC_LUT_BASE", 0, 15, &umr_bitfield_default },
+	 { "DC_LUT_DELTA", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_30_COLOR[] = {
+	 { "DC_LUT_COLOR_10_BLUE", 0, 9, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_GREEN", 10, 19, &umr_bitfield_default },
+	 { "DC_LUT_COLOR_10_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_VGA_ACCESS_ENABLE[] = {
+	 { "DC_LUT_VGA_ACCESS_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WRITE_EN_MASK[] = {
+	 { "DC_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_AUTOFILL[] = {
+	 { "DC_LUT_AUTOFILL", 0, 0, &umr_bitfield_default },
+	 { "DC_LUT_AUTOFILL_DONE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_CONTROL[] = {
+	 { "DC_LUT_INC_B", 0, 3, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_SIGNED_EN", 4, 4, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FLOAT_POINT_EN", 5, 5, &umr_bitfield_default },
+	 { "DC_LUT_DATA_B_FORMAT", 6, 7, &umr_bitfield_default },
+	 { "DC_LUT_INC_G", 8, 11, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_SIGNED_EN", 12, 12, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FLOAT_POINT_EN", 13, 13, &umr_bitfield_default },
+	 { "DC_LUT_DATA_G_FORMAT", 14, 15, &umr_bitfield_default },
+	 { "DC_LUT_INC_R", 16, 19, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_SIGNED_EN", 20, 20, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FLOAT_POINT_EN", 21, 21, &umr_bitfield_default },
+	 { "DC_LUT_DATA_R_FORMAT", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_BLUE[] = {
+	 { "DC_LUT_BLACK_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_GREEN[] = {
+	 { "DC_LUT_BLACK_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_BLACK_OFFSET_RED[] = {
+	 { "DC_LUT_BLACK_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_BLUE[] = {
+	 { "DC_LUT_WHITE_OFFSET_BLUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_GREEN[] = {
+	 { "DC_LUT_WHITE_OFFSET_GREEN", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_LUT_WHITE_OFFSET_RED[] = {
+	 { "DC_LUT_WHITE_OFFSET_RED", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_CONTROL[] = {
+	 { "DCP_CRC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DCP_CRC_SOURCE_SEL", 2, 4, &umr_bitfield_default },
+	 { "DCP_CRC_LINE_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_MASK[] = {
+	 { "DCP_CRC_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_CURRENT[] = {
+	 { "DCP_CRC_CURRENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_CRC_LAST[] = {
+	 { "DCP_CRC_LAST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG[] = {
+	 { "DCP_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_FLIP_RATE_CNTL[] = {
+	 { "GRPH_FLIP_RATE", 0, 2, &umr_bitfield_default },
+	 { "GRPH_FLIP_RATE_ENABLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_GSL_CONTROL[] = {
+	 { "DCP_GSL0_EN", 0, 0, &umr_bitfield_default },
+	 { "DCP_GSL1_EN", 1, 1, &umr_bitfield_default },
+	 { "DCP_GSL2_EN", 2, 2, &umr_bitfield_default },
+	 { "DCP_GSL_MODE", 8, 9, &umr_bitfield_default },
+	 { "DCP_GSL_HSYNC_FLIP_FORCE_DELAY", 12, 15, &umr_bitfield_default },
+	 { "DCP_GSL_MASTER_EN", 16, 16, &umr_bitfield_default },
+	 { "DCP_GSL_SYNC_SOURCE", 24, 25, &umr_bitfield_default },
+	 { "DCP_GSL_DELAY_SURFACE_UPDATE_PENDING", 27, 27, &umr_bitfield_default },
+	 { "DCP_GSL_HSYNC_FLIP_CHECK_DELAY", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[] = {
+	 { "DCP_LB_GAP_BETWEEN_CHUNK_20BPP", 0, 3, &umr_bitfield_default },
+	 { "DCP_LB_GAP_BETWEEN_CHUNK_30BPP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SECONDARY_SURFACE_ADDRESS[] = {
+	 { "OVL_SECONDARY_DFQ_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OVL_SECONDARY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_STEREOSYNC_FLIP[] = {
+	 { "OVL_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "OVL_STEREOSYNC_FLIP_MODE", 8, 9, &umr_bitfield_default },
+	 { "OVL_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "OVL_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "OVL_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH[] = {
+	 { "OVL_SECONDARY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_TEST_DEBUG_INDEX[] = {
+	 { "DCP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_TEST_DEBUG_DATA[] = {
+	 { "DCP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_STEREOSYNC_FLIP[] = {
+	 { "GRPH_STEREOSYNC_FLIP_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_FLIP_MODE", 8, 9, &umr_bitfield_default },
+	 { "GRPH_PRIMARY_SURFACE_PENDING", 16, 16, &umr_bitfield_default },
+	 { "GRPH_SECONDARY_SURFACE_PENDING", 17, 17, &umr_bitfield_default },
+	 { "GRPH_STEREOSYNC_SELECT_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCP_DEBUG2[] = {
+	 { "DCP_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_REQUEST_FILTER_CNTL[] = {
+	 { "CUR_REQUEST_FILTER_DIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR_STEREO_CONTROL[] = {
+	 { "CURSOR_STEREO_EN", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_STEREO_OFFSET_YNX", 1, 1, &umr_bitfield_default },
+	 { "CURSOR_PRIMARY_OFFSET", 4, 13, &umr_bitfield_default },
+	 { "CURSOR_SECONDARY_OFFSET", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCUR2_STEREO_CONTROL[] = {
+	 { "CURSOR2_STEREO_EN", 0, 0, &umr_bitfield_default },
+	 { "CURSOR2_STEREO_OFFSET_YNX", 1, 1, &umr_bitfield_default },
+	 { "CURSOR2_PRIMARY_OFFSET", 4, 13, &umr_bitfield_default },
+	 { "CURSOR2_SECONDARY_OFFSET", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_G_Y[] = {
+	 { "OUT_CLAMP_MAX_G_Y", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_G_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUT_CLAMP_CONTROL_B_CB[] = {
+	 { "OUT_CLAMP_MAX_B_CB", 0, 13, &umr_bitfield_default },
+	 { "OUT_CLAMP_MIN_B_CB", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHW_ROTATION[] = {
+	 { "GRPH_ROTATION_ANGLE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[] = {
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN", 0, 0, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE", 1, 1, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_CNT", 4, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CONTROL[] = {
+	 { "GRPH_REGAMMA_MODE", 0, 2, &umr_bitfield_default },
+	 { "OVL_REGAMMA_MODE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_INDEX[] = {
+	 { "REGAMMA_LUT_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_DATA[] = {
+	 { "REGAMMA_LUT_DATA", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_LUT_WRITE_EN_MASK[] = {
+	 { "REGAMMA_LUT_WRITE_EN_MASK", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_START_CNTL[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_SLOPE_CNTL[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_END_CNTL1[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_END_CNTL2[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_0_1[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_2_3[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_4_5[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_6_7[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_8_9[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_10_11[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_12_13[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLA_REGION_14_15[] = {
+	 { "REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_START_CNTL[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_START", 0, 17, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION_START_SEGMENT", 20, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_SLOPE_CNTL[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_END_CNTL1[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_END", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_END_CNTL2[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION_END_SLOPE", 0, 15, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION_END_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_0_1[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_2_3[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_4_5[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_6_7[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_8_9[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_10_11[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_12_13[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmREGAMMA_CNTLB_REGION_14_15[] = {
+	 { "REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET", 0, 8, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS", 12, 14, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET", 16, 24, &umr_bitfield_default },
+	 { "REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmALPHA_CONTROL[] = {
+	 { "ALPHA_ROUND_TRUNC_MODE", 0, 0, &umr_bitfield_default },
+	 { "CURSOR_ALPHA_BLND_ENA", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[] = {
+	 { "GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[] = {
+	 { "GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[] = {
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT", 0, 19, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_CNT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK", 25, 25, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK", 26, 26, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT", 28, 28, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK", 29, 29, &umr_bitfield_default },
+	 { "GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DATA_FORMAT[] = {
+	 { "PIXEL_DEPTH", 0, 1, &umr_bitfield_default },
+	 { "PIXEL_EXPAN_MODE", 2, 2, &umr_bitfield_default },
+	 { "INTERLEAVE_EN", 3, 3, &umr_bitfield_default },
+	 { "PREFETCH", 12, 12, &umr_bitfield_default },
+	 { "REQUEST_MODE", 24, 24, &umr_bitfield_default },
+	 { "ALPHA_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_MEMORY_CTRL[] = {
+	 { "LB_MEMORY_SIZE", 0, 11, &umr_bitfield_default },
+	 { "LB_NUM_PARTITIONS", 16, 19, &umr_bitfield_default },
+	 { "LB_MEMORY_CONFIG", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_MEMORY_SIZE_STATUS[] = {
+	 { "LB_MEMORY_SIZE_STATUS", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DESKTOP_HEIGHT[] = {
+	 { "DESKTOP_HEIGHT", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE_START_END[] = {
+	 { "VLINE_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE2_START_END[] = {
+	 { "VLINE2_START", 0, 13, &umr_bitfield_default },
+	 { "VLINE2_END", 16, 30, &umr_bitfield_default },
+	 { "VLINE2_INV", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_V_COUNTER[] = {
+	 { "V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_SNAPSHOT_V_COUNTER[] = {
+	 { "SNAPSHOT_V_COUNTER", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_INTERRUPT_MASK[] = {
+	 { "VBLANK_INTERRUPT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_MASK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_MASK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE_STATUS[] = {
+	 { "VLINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VLINE2_STATUS[] = {
+	 { "VLINE2_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VLINE2_ACK", 4, 4, &umr_bitfield_default },
+	 { "VLINE2_STAT", 12, 12, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VLINE2_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_VBLANK_STATUS[] = {
+	 { "VBLANK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "VBLANK_ACK", 4, 4, &umr_bitfield_default },
+	 { "VBLANK_STAT", 12, 12, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT", 16, 16, &umr_bitfield_default },
+	 { "VBLANK_INTERRUPT_TYPE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_SYNC_RESET_SEL[] = {
+	 { "LB_SYNC_RESET_SEL", 0, 1, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_SEL2", 4, 4, &umr_bitfield_default },
+	 { "LB_SYNC_RESET_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LB_SYNC_DURATION", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_R_CR[] = {
+	 { "LB_BLACK_KEYER_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_G_Y[] = {
+	 { "LB_BLACK_KEYER_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BLACK_KEYER_B_CB[] = {
+	 { "LB_BLACK_KEYER_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_CTRL[] = {
+	 { "LB_KEYER_COLOR_EN", 0, 0, &umr_bitfield_default },
+	 { "LB_KEYER_COLOR_REP_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_R_CR[] = {
+	 { "LB_KEYER_COLOR_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_G_Y[] = {
+	 { "LB_KEYER_COLOR_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_B_CB[] = {
+	 { "LB_KEYER_COLOR_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_R_CR[] = {
+	 { "LB_KEYER_COLOR_REP_R_CR", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_G_Y[] = {
+	 { "LB_KEYER_COLOR_REP_G_Y", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_KEYER_COLOR_REP_B_CB[] = {
+	 { "LB_KEYER_COLOR_REP_B_CB", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_LEVEL_STATUS[] = {
+	 { "REQ_FIFO_LEVEL", 0, 5, &umr_bitfield_default },
+	 { "REQ_FIFO_FULL_CNTL", 10, 15, &umr_bitfield_default },
+	 { "DATA_BUFFER_LEVEL", 16, 27, &umr_bitfield_default },
+	 { "DATA_FIFO_FULL_CNTL", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_URGENCY_CTRL[] = {
+	 { "LB_BUFFER_URGENCY_MARK_ON", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_MARK_OFF", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_URGENCY_STATUS[] = {
+	 { "LB_BUFFER_URGENCY_LEVEL", 0, 11, &umr_bitfield_default },
+	 { "LB_BUFFER_URGENCY_STAT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_BUFFER_STATUS[] = {
+	 { "LB_BUFFER_EMPTY_MARGIN", 0, 3, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_STAT", 4, 4, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "LB_BUFFER_EMPTY_ACK", 12, 12, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_STAT", 16, 16, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "LB_BUFFER_FULL_ACK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_NO_OUTSTANDING_REQ_STATUS[] = {
+	 { "LB_NO_OUTSTANDING_REQ_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_AFR_FLIP_MODE[] = {
+	 { "MVP_AFR_FLIP_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_AFR_FLIP_FIFO_CNTL[] = {
+	 { "MVP_AFR_FLIP_FIFO_NUM_ENTRIES", 0, 3, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET", 4, 4, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET_FLAG", 8, 8, &umr_bitfield_default },
+	 { "MVP_AFR_FLIP_FIFO_RESET_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMVP_FLIP_LINE_NUM_INSERT[] = {
+	 { "MVP_FLIP_LINE_NUM_INSERT_MODE", 0, 1, &umr_bitfield_default },
+	 { "MVP_FLIP_LINE_NUM_INSERT", 8, 22, &umr_bitfield_default },
+	 { "MVP_FLIP_LINE_NUM_OFFSET", 24, 29, &umr_bitfield_default },
+	 { "MVP_FLIP_AUTO_ENABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_MVP_LB_CONTROL[] = {
+	 { "MVP_SWAP_LOCK_IN_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_SEL", 8, 8, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ONE", 12, 12, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO", 16, 16, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DC_MVP_SWAP_LOCK_IN_CAP", 28, 28, &umr_bitfield_default },
+	 { "DC_MVP_SPARE_FLOPS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG[] = {
+	 { "LB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG2[] = {
+	 { "LB_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_DEBUG3[] = {
+	 { "LB_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_TEST_DEBUG_INDEX[] = {
+	 { "LB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "LB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLB_TEST_DEBUG_DATA[] = {
+	 { "LB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_L[] = {
+	 { "DP_AUX1_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_ARBITRATION_CONTROL1[] = {
+	 { "PIXEL_DURATION", 0, 15, &umr_bitfield_default },
+	 { "BASE_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_ARBITRATION_CONTROL2[] = {
+	 { "TIME_WEIGHT", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_WATERMARK_MASK_CONTROL[] = {
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK", 0, 1, &umr_bitfield_default },
+	 { "URGENCY_WATERMARK_MASK", 8, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK_MASK", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_URGENCY_CONTROL[] = {
+	 { "URGENCY_LOW_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "URGENCY_HIGH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_DPM_CONTROL[] = {
+	 { "DPM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCLK_CHANGE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCLK_CHANGE_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK_MASK", 12, 13, &umr_bitfield_default },
+	 { "MCLK_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_STUTTER_CONTROL[] = {
+	 { "STUTTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON", 11, 11, &umr_bitfield_default },
+	 { "STUTTER_EXIT_SELF_REFRESH_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[] = {
+	 { "NB_PSTATE_CHANGE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_URGENT_DURING_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_FORCE_ON", 9, 9, &umr_bitfield_default },
+	 { "NB_PSTATE_ALLOW_FOR_URGENT", 10, 10, &umr_bitfield_default },
+	 { "NB_PSTATE_CHANGE_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[] = {
+	 { "STUTTER_ENABLE_NONLPTCH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_CURSOR_NONLPTCH", 4, 4, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_ICON_NONLPTCH", 5, 5, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_VGA_NONLPTCH", 6, 6, &umr_bitfield_default },
+	 { "STUTTER_IGNORE_FBC_NONLPTCH", 7, 7, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_FORCE_ON_NONLPTCH", 8, 8, &umr_bitfield_default },
+	 { "STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH", 10, 10, &umr_bitfield_default },
+	 { "STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_TEST_DEBUG_INDEX[] = {
+	 { "DPG_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DPG_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_TEST_DEBUG_DATA[] = {
+	 { "DPG_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_REPEATER_PROGRAM[] = {
+	 { "REG_DPG_DMIFRC_REPEATER", 0, 2, &umr_bitfield_default },
+	 { "REG_DMIFRC_DPG_REPEATER", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_A[] = {
+	 { "DPG_HW_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDPG_HW_DEBUG_B[] = {
+	 { "DPG_HW_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_SELECT[] = {
+	 { "SCL_C_RAM_TAP_PAIR_IDX", 0, 3, &umr_bitfield_default },
+	 { "SCL_C_RAM_PHASE", 8, 11, &umr_bitfield_default },
+	 { "SCL_C_RAM_FILTER_TYPE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_TAP_DATA[] = {
+	 { "SCL_C_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
+	 { "SCL_C_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
+	 { "SCL_C_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE[] = {
+	 { "SCL_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TAP_CONTROL[] = {
+	 { "SCL_V_NUM_OF_TAPS", 0, 2, &umr_bitfield_default },
+	 { "SCL_H_NUM_OF_TAPS", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_CONTROL[] = {
+	 { "SCL_BOUNDARY_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_BYPASS_CONTROL[] = {
+	 { "SCL_BYPASS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MANUAL_REPLICATE_CONTROL[] = {
+	 { "SCL_V_MANUAL_REPLICATE_FACTOR", 0, 3, &umr_bitfield_default },
+	 { "SCL_H_MANUAL_REPLICATE_FACTOR", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_AUTOMATIC_MODE_CONTROL[] = {
+	 { "SCL_V_CALC_AUTO_RATIO_EN", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_CALC_AUTO_RATIO_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_CONTROL[] = {
+	 { "SCL_H_FILTER_PICK_NEAREST", 0, 0, &umr_bitfield_default },
+	 { "SCL_H_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_SCALE_RATIO[] = {
+	 { "SCL_H_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_HORZ_FILTER_INIT[] = {
+	 { "SCL_H_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_H_INIT_INT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_CONTROL[] = {
+	 { "SCL_V_FILTER_PICK_NEAREST", 0, 0, &umr_bitfield_default },
+	 { "SCL_V_2TAP_HARDCODE_COEF_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_SCALE_RATIO[] = {
+	 { "SCL_V_SCALE_RATIO", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_INIT[] = {
+	 { "SCL_V_INIT_FRAC", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_VERT_FILTER_INIT_BOT[] = {
+	 { "SCL_V_INIT_FRAC_BOT", 0, 23, &umr_bitfield_default },
+	 { "SCL_V_INIT_INT_BOT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_ROUND_OFFSET[] = {
+	 { "SCL_ROUND_OFFSET_RGB_Y", 0, 15, &umr_bitfield_default },
+	 { "SCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_UPDATE[] = {
+	 { "SCL_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "SCL_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "SCL_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "SCL_COEF_UPDATE_COMPLETE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_F_SHARP_CONTROL[] = {
+	 { "SCL_HF_SHARP_SCALE_FACTOR", 0, 2, &umr_bitfield_default },
+	 { "SCL_HF_SHARP_EN", 4, 4, &umr_bitfield_default },
+	 { "SCL_VF_SHARP_SCALE_FACTOR", 8, 10, &umr_bitfield_default },
+	 { "SCL_VF_SHARP_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_ALU_CONTROL[] = {
+	 { "SCL_ALU_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_COEF_RAM_CONFLICT_STATUS[] = {
+	 { "SCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default },
+	 { "SCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_START[] = {
+	 { "VIEWPORT_Y_START", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_X_START", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVIEWPORT_SIZE[] = {
+	 { "VIEWPORT_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "VIEWPORT_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_LEFT_RIGHT[] = {
+	 { "EXT_OVERSCAN_RIGHT", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_LEFT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmEXT_OVERSCAN_TOP_BOTTOM[] = {
+	 { "EXT_OVERSCAN_BOTTOM", 0, 12, &umr_bitfield_default },
+	 { "EXT_OVERSCAN_TOP", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET1[] = {
+	 { "SCL_MODE_CHANGE", 0, 0, &umr_bitfield_default },
+	 { "SCL_MODE_CHANGE_ACK", 4, 4, &umr_bitfield_default },
+	 { "SCL_ALU_H_SCALE_RATIO", 7, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET2[] = {
+	 { "SCL_ALU_V_SCALE_RATIO", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_DET3[] = {
+	 { "SCL_ALU_SOURCE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "SCL_ALU_SOURCE_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_MODE_CHANGE_MASK[] = {
+	 { "SCL_MODE_CHANGE_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_DEBUG2[] = {
+	 { "SCL_DEBUG_REQ_MODE", 0, 0, &umr_bitfield_default },
+	 { "SCL_DEBUG_EOF_MODE", 1, 2, &umr_bitfield_default },
+	 { "SCL_DEBUG2", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_DEBUG[] = {
+	 { "SCL_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TEST_DEBUG_INDEX[] = {
+	 { "SCL_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SCL_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCL_TEST_DEBUG_DATA[] = {
+	 { "SCL_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_CONTROL[] = {
+	 { "BLND_MODE", 8, 9, &umr_bitfield_default },
+	 { "BLND_ALPHA_MODE", 16, 17, &umr_bitfield_default },
+	 { "BLND_MULTIPLIED_MODE", 20, 20, &umr_bitfield_default },
+	 { "BLND_GLOBAL_ALPHA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSM_CONTROL2[] = {
+	 { "SM_MODE", 0, 2, &umr_bitfield_default },
+	 { "SM_FRAME_ALTERNATE", 4, 4, &umr_bitfield_default },
+	 { "SM_FIELD_ALTERNATE", 5, 5, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_FRAME_POL", 8, 9, &umr_bitfield_default },
+	 { "SM_FORCE_NEXT_TOP_POL", 16, 17, &umr_bitfield_default },
+	 { "SM_CURRENT_FRAME_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPTI_CONTROL[] = {
+	 { "PTI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PTI_NEW_PIXEL_GAP", 4, 5, &umr_bitfield_default },
+	 { "BLND_NEW_PIXEL_MODE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_UPDATE[] = {
+	 { "BLND_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "BLND_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "BLND_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_UNDERFLOW_INTERRUPT[] = {
+	 { "BLND_UNDERFLOW_INT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_MASK", 12, 12, &umr_bitfield_default },
+	 { "BLND_UNDERFLOW_INT_PIPE_INDEX", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_V_UPDATE_LOCK[] = {
+	 { "BLND_DCP_GRPH_V_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "BLND_DCP_GRPH_SURF_V_UPDATE_LOCK", 1, 1, &umr_bitfield_default },
+	 { "BLND_DCP_OVL_V_UPDATE_LOCK", 8, 8, &umr_bitfield_default },
+	 { "BLND_DCP_CUR_V_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+	 { "BLND_DCP_CUR2_V_UPDATE_LOCK", 24, 24, &umr_bitfield_default },
+	 { "BLND_SCL_V_UPDATE_LOCK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_DEBUG[] = {
+	 { "BLND_CNV_MUX_SELECT", 0, 0, &umr_bitfield_default },
+	 { "BLND_DEBUG", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_TEST_DEBUG_INDEX[] = {
+	 { "BLND_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "BLND_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_TEST_DEBUG_DATA[] = {
+	 { "BLND_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBLND_REG_UPDATE_STATUS[] = {
+	 { "DCP_BLNDc_GRPH_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "DCP_BLNDo_GRPH_UPDATE_PENDING", 1, 1, &umr_bitfield_default },
+	 { "DCP_BLNDc_GRPH_SURF_UPDATE_PENDING", 2, 2, &umr_bitfield_default },
+	 { "DCP_BLNDo_GRPH_SURF_UPDATE_PENDING", 3, 3, &umr_bitfield_default },
+	 { "DCP_BLNDc_OVL_UPDATE_PENDING", 4, 4, &umr_bitfield_default },
+	 { "DCP_BLNDo_OVL_UPDATE_PENDING", 5, 5, &umr_bitfield_default },
+	 { "DCP_BLNDc_CUR_UPDATE_PENDING", 6, 6, &umr_bitfield_default },
+	 { "DCP_BLNDo_CUR_UPDATE_PENDING", 7, 7, &umr_bitfield_default },
+	 { "SCL_BLNDc_UPDATE_PENDING", 8, 8, &umr_bitfield_default },
+	 { "SCL_BLNDo_UPDATE_PENDING", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_3D_STRUCTURE_CONTROL[] = {
+	 { "CRTC_3D_STRUCTURE_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_EN_DB", 4, 4, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_V_UPDATE_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_STEREO_SEL_OVR", 12, 12, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET", 16, 16, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING", 17, 17, &umr_bitfield_default },
+	 { "CRTC_3D_STRUCTURE_F_COUNT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_VSYNC_GAP[] = {
+	 { "CRTC_GSL_VSYNC_GAP_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_SOURCE_SEL", 16, 16, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MODE", 17, 18, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_CLEAR", 19, 19, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_OCCURRED", 20, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_MASTER_FASTER", 23, 23, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_WINDOW[] = {
+	 { "CRTC_GSL_WINDOW_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_GSL_WINDOW_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_GSL_CONTROL[] = {
+	 { "CRTC_GSL_CHECK_LINE_NUM", 0, 12, &umr_bitfield_default },
+	 { "CRTC_GSL_FORCE_DELAY", 16, 20, &umr_bitfield_default },
+	 { "CRTC_GSL_CHECK_ALL_FIELDS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DCFE_CLOCK_CONTROL[] = {
+	 { "CRTC_DISPCLK_R_DCFE_GATE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_DISPCLK_G_DCP_GATE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_DISPCLK_G_SCL_GATE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "CRTC_DCFE_TEST_CLK_SEL", 24, 28, &umr_bitfield_default },
+	 { "CRTC_DCFE_CLOCK_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_BLANK_EARLY_NUM[] = {
+	 { "CRTC_H_BLANK_EARLY_NUM", 0, 9, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_EARLY_NUM_DIS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_DBG_SEL[] = {
+	 { "DCFE_DBG_SEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCFE_MEM_LIGHT_SLEEP_CNTL[] = {
+	 { "DCP_CURSOR_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+	 { "DCP_CURSOR2_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default },
+	 { "DCP_LUT_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "OVLSCL_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "LB_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
+	 { "SCL_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
+	 { "REGAMMA_LUT_LIGHT_SLEEP_DIS", 6, 6, &umr_bitfield_default },
+	 { "DCP_CURSOR_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "DCP_CURSOR2_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "DCP_LUT_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "OVLSCL_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE_0", 16, 17, &umr_bitfield_default },
+	 { "SCL_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "REGAMMA_LUT_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE_1", 22, 23, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE_2", 24, 25, &umr_bitfield_default },
+	 { "PIPE_MEM_SHUTDOWN_DIS", 28, 28, &umr_bitfield_default },
+	 { "LB1_MEM_SHUTDOWN_DIS", 29, 29, &umr_bitfield_default },
+	 { "LB2_MEM_SHUTDOWN_DIS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_TOTAL[] = {
+	 { "CRTC_H_TOTAL", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_BLANK_START_END[] = {
+	 { "CRTC_H_BLANK_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_H_BLANK_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_A[] = {
+	 { "CRTC_H_SYNC_A_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_A_CNTL[] = {
+	 { "CRTC_H_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_A_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_B[] = {
+	 { "CRTC_H_SYNC_B_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_H_SYNC_B_CNTL[] = {
+	 { "CRTC_H_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_COMP_SYNC_B_EN", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_B_CUTOFF", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VBI_END[] = {
+	 { "CRTC_VBI_V_END", 0, 12, &umr_bitfield_default },
+	 { "CRTC_VBI_H_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL[] = {
+	 { "CRTC_V_TOTAL", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_MIN[] = {
+	 { "CRTC_V_TOTAL_MIN", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_MAX[] = {
+	 { "CRTC_V_TOTAL_MAX", 0, 12, &umr_bitfield_default },
+	 { "CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_CONTROL[] = {
+	 { "CRTC_V_TOTAL_MIN_SEL", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_TOTAL_MAX_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_ON_EVENT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_LOCK_TO_MASTER_VSYNC", 12, 12, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK_EN", 15, 15, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_TOTAL_INT_STATUS[] = {
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT", 4, 4, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VSYNC_NOM_INT_STATUS[] = {
+	 { "CRTC_VSYNC_NOM", 0, 0, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_CLEAR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_BLANK_START_END[] = {
+	 { "CRTC_V_BLANK_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_A[] = {
+	 { "CRTC_V_SYNC_A_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_A_CNTL[] = {
+	 { "CRTC_V_SYNC_A_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_B[] = {
+	 { "CRTC_V_SYNC_B_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_B_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_SYNC_B_CNTL[] = {
+	 { "CRTC_V_SYNC_B_POL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DTMTEST_CNTL[] = {
+	 { "CRTC_DTMTEST_CRTC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_CLK_DIV", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DTMTEST_STATUS_POSITION[] = {
+	 { "CRTC_DTMTEST_VERT_COUNT", 0, 12, &umr_bitfield_default },
+	 { "CRTC_DTMTEST_HORZ_COUNT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGA_CNTL[] = {
+	 { "CRTC_TRIGA_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGA_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGA_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGA_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGA_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGA_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGA_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGA_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGB_CNTL[] = {
+	 { "CRTC_TRIGB_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_SELECT", 5, 7, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RESYNC_BYPASS_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INPUT_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CRTC_TRIGB_POLARITY_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CRTC_TRIGB_OCCURRED", 11, 11, &umr_bitfield_default },
+	 { "CRTC_TRIGB_RISING_EDGE_DETECT_CNTL", 12, 13, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL", 16, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGB_FREQUENCY_SELECT", 20, 21, &umr_bitfield_default },
+	 { "CRTC_TRIGB_DELAY", 24, 28, &umr_bitfield_default },
+	 { "CRTC_TRIGB_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TRIGB_MANUAL_TRIG[] = {
+	 { "CRTC_TRIGB_MANUAL_TRIG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FORCE_COUNT_NOW_CNTL[] = {
+	 { "CRTC_FORCE_COUNT_NOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CHECK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_TRIG_SEL", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FLOW_CONTROL[] = {
+	 { "CRTC_FLOW_CONTROL_SOURCE_SELECT", 0, 4, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_POLARITY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_GRANULARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FLOW_CONTROL_INPUT_STATUS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_FORCE_NEXT_EYE[] = {
+	 { "CRTC_STEREO_FORCE_NEXT_EYE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CONTROL[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SYNC_RESET_SEL", 4, 4, &umr_bitfield_default },
+	 { "CRTC_DISABLE_POINT_CNTL", 8, 9, &umr_bitfield_default },
+	 { "CRTC_START_POINT_CNTL", 12, 12, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_CNTL", 13, 13, &umr_bitfield_default },
+	 { "CRTC_FIELD_NUMBER_POLARITY", 14, 14, &umr_bitfield_default },
+	 { "CRTC_CURRENT_MASTER_EN_STATE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_HBLANK_EARLY_CONTROL", 20, 22, &umr_bitfield_default },
+	 { "CRTC_DISP_READ_REQUEST_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SOF_PULL_EN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_CONTROL[] = {
+	 { "CRTC_CURRENT_BLANK_STATE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_EN", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DE_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERLACE_CONTROL[] = {
+	 { "CRTC_INTERLACE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_FORCE_NEXT_FIELD", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERLACE_STATUS[] = {
+	 { "CRTC_INTERLACE_CURRENT_FIELD", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_NEXT_FIELD", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_FIELD_INDICATION_CONTROL[] = {
+	 { "CRTC_FIELD_INDICATION_OUTPUT_POLARITY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FIELD_ALIGNMENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_PIXEL_DATA_READBACK0[] = {
+	 { "CRTC_PIXEL_DATA_BLUE_CB", 0, 11, &umr_bitfield_default },
+	 { "CRTC_PIXEL_DATA_GREEN_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_PIXEL_DATA_READBACK1[] = {
+	 { "CRTC_PIXEL_DATA_RED_CR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS[] = {
+	 { "CRTC_V_BLANK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_ACTIVE_DISP", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_SYNC_A", 2, 2, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "CRTC_V_START_LINE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_BLANK_3D_STRUCTURE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_H_BLANK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_H_ACTIVE_DISP", 17, 17, &umr_bitfield_default },
+	 { "CRTC_H_SYNC_A", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_POSITION[] = {
+	 { "CRTC_VERT_COUNT", 0, 12, &umr_bitfield_default },
+	 { "CRTC_HORZ_COUNT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_NOM_VERT_POSITION[] = {
+	 { "CRTC_VERT_COUNT_NOM", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_FRAME_COUNT[] = {
+	 { "CRTC_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_VF_COUNT[] = {
+	 { "CRTC_VF_COUNT", 0, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATUS_HV_COUNT[] = {
+	 { "CRTC_HV_COUNT", 0, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_COUNT_CONTROL[] = {
+	 { "CRTC_HORZ_COUNT_BY2_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_HORZ_REPETITION_COUNT", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_COUNT_RESET[] = {
+	 { "CRTC_RESET_FRAME_COUNT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[] = {
+	 { "CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERT_SYNC_CONTROL[] = {
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "CRTC_AUTO_FORCE_VSYNC_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_STATUS[] = {
+	 { "CRTC_STEREO_CURRENT_EYE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT", 8, 8, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_FORCE_NEXT_EYE_PENDING", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STEREO_CONTROL[] = {
+	 { "CRTC_STEREO_SYNC_OUTPUT_LINE_NUM", 0, 12, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_OUTPUT_POLARITY", 15, 15, &umr_bitfield_default },
+	 { "CRTC_STEREO_SYNC_SELECT_POLARITY", 16, 16, &umr_bitfield_default },
+	 { "CRTC_STEREO_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_STATUS[] = {
+	 { "CRTC_SNAPSHOT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_MANUAL_TRIGGER", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_CONTROL[] = {
+	 { "CRTC_AUTO_SNAPSHOT_TRIG_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_POSITION[] = {
+	 { "CRTC_SNAPSHOT_VERT_COUNT", 0, 12, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_HORZ_COUNT", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_SNAPSHOT_FRAME[] = {
+	 { "CRTC_SNAPSHOT_FRAME_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_START_LINE_CONTROL[] = {
+	 { "CRTC_PROGRESSIVE_START_LINE_EARLY", 0, 0, &umr_bitfield_default },
+	 { "CRTC_INTERLACE_START_LINE_EARLY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_ADVANCED_START_LINE_POSITION", 16, 19, &umr_bitfield_default },
+	 { "CRTC_LEGACY_REQUESTOR_EN", 20, 20, &umr_bitfield_default },
+	 { "CRTC_PREFETCH_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_INTERRUPT_CONTROL[] = {
+	 { "CRTC_SNAPSHOT_INT_MSK", 0, 0, &umr_bitfield_default },
+	 { "CRTC_SNAPSHOT_INT_TYPE", 1, 1, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_MSK", 4, 4, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_TYPE", 5, 5, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_MSK", 8, 8, &umr_bitfield_default },
+	 { "CRTC_FORCE_COUNT_NOW_INT_TYPE", 9, 9, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK", 16, 16, &umr_bitfield_default },
+	 { "CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE", 17, 17, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_MSK", 24, 24, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_MSK", 25, 25, &umr_bitfield_default },
+	 { "CRTC_TRIGA_INT_TYPE", 26, 26, &umr_bitfield_default },
+	 { "CRTC_TRIGB_INT_TYPE", 27, 27, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_MSK", 28, 28, &umr_bitfield_default },
+	 { "CRTC_VSYNC_NOM_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_MSK", 30, 30, &umr_bitfield_default },
+	 { "CRTC_GSL_VSYNC_GAP_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_UPDATE_LOCK[] = {
+	 { "CRTC_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_DOUBLE_BUFFER_CONTROL[] = {
+	 { "CRTC_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CRTC_UPDATE_INSTANTLY", 8, 8, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_DOUBLE_BUFFER_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VGA_PARAMETER_CAPTURE_MODE[] = {
+	 { "CRTC_VGA_PARAMETER_CAPTURE_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_CONTROL[] = {
+	 { "CRTC_TEST_PATTERN_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MODE", 8, 10, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_DYNAMIC_RANGE", 16, 16, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_COLOR_FORMAT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_PARAMETERS[] = {
+	 { "CRTC_TEST_PATTERN_INC0", 0, 3, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_INC1", 4, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_VRES", 8, 11, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_HRES", 12, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_RAMP0_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_PATTERN_COLOR[] = {
+	 { "CRTC_TEST_PATTERN_DATA", 0, 15, &umr_bitfield_default },
+	 { "CRTC_TEST_PATTERN_MASK", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_UPDATE_LOCK[] = {
+	 { "MASTER_UPDATE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "GSL_CONTROL_MASTER_UPDATE_LOCK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMASTER_UPDATE_MODE[] = {
+	 { "MASTER_UPDATE_MODE", 0, 2, &umr_bitfield_default },
+	 { "MASTER_UPDATE_INTERLACED_MODE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_INBAND_CNTL_INSERT[] = {
+	 { "CRTC_MVP_INBAND_OUT_MODE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[] = {
+	 { "CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MVP_STATUS[] = {
+	 { "CRTC_FLIP_NOW_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "CRTC_FLIP_NOW_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_MASTER_EN[] = {
+	 { "CRTC_MASTER_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_ALLOW_STOP_OFF_V_CNT[] = {
+	 { "CRTC_ALLOW_STOP_OFF_V_CNT", 0, 7, &umr_bitfield_default },
+	 { "CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_V_UPDATE_INT_STATUS[] = {
+	 { "CRTC_V_UPDATE_INT_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "CRTC_V_UPDATE_INT_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_DEBUG_INDEX[] = {
+	 { "CRTC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CRTC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_TEST_DEBUG_DATA[] = {
+	 { "CRTC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_OVERSCAN_COLOR[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE", 0, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN", 10, 19, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_OVERSCAN_COLOR_EXT[] = {
+	 { "CRTC_OVERSCAN_COLOR_BLUE_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_GREEN_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_OVERSCAN_COLOR_RED_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_DATA_COLOR[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLANK_DATA_COLOR_EXT[] = {
+	 { "CRTC_BLANK_DATA_COLOR_BLUE_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_GREEN_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLANK_DATA_COLOR_RED_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLACK_COLOR[] = {
+	 { "CRTC_BLACK_COLOR_B_CB", 0, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y", 10, 19, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_BLACK_COLOR_EXT[] = {
+	 { "CRTC_BLACK_COLOR_B_CB_EXT", 0, 1, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_G_Y_EXT", 8, 9, &umr_bitfield_default },
+	 { "CRTC_BLACK_COLOR_R_CR_EXT", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT0_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_LINE_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT0_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY", 4, 4, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT0_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT1_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_LINE_START", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT1_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT1_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT2_POSITION[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_LINE_START", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_VERTICAL_INTERRUPT2_CONTROL[] = {
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_STATUS", 12, 12, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "CRTC_VERTICAL_INTERRUPT2_INT_TYPE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC_CNTL[] = {
+	 { "CRTC_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "CRTC_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "CRTC_CRC_STEREO_MODE", 8, 9, &umr_bitfield_default },
+	 { "CRTC_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "CRTC_CRC0_SELECT", 20, 22, &umr_bitfield_default },
+	 { "CRTC_CRC1_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_X_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_X_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWA_Y_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWA_Y_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_X_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_X_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC0_WINDOWB_Y_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_CRC0_WINDOWB_Y_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_DATA_RG[] = {
+	 { "CRC0_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC0_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC0_DATA_B[] = {
+	 { "CRC0_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWA_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_X_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_X_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWA_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWA_Y_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWA_Y_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWB_X_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_X_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_X_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_WINDOWB_Y_CONTROL[] = {
+	 { "CRTC_CRC1_WINDOWB_Y_START", 0, 12, &umr_bitfield_default },
+	 { "CRTC_CRC1_WINDOWB_Y_END", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_DATA_RG[] = {
+	 { "CRC1_R_CR", 0, 15, &umr_bitfield_default },
+	 { "CRC1_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_CRC1_DATA_B[] = {
+	 { "CRC1_B_CB", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW", 5, 6, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_UPDATE", 9, 9, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_VSYNC_POLARITY", 12, 12, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_HSYNC_POLARITY", 13, 13, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INTERLACE_MODE", 14, 14, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_MASTER_FRAME_RATE", 24, 26, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SLAVE_FRAME_RATE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_WINDOW_START[] = {
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_START_X", 0, 12, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_START_Y", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_WINDOW_END[] = {
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_END_X", 0, 12, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_WINDOW_END_Y", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_INT_TYPE", 20, 20, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_LOSS_FRAME_COUNT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_INT_TYPE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[] = {
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "CRTC_EXT_TIMING_SYNC_SIGNAL_INT_TYPE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC_STATIC_SCREEN_CONTROL[] = {
+	 { "CRTC_STATIC_SCREEN_EVENT_MASK", 0, 15, &umr_bitfield_default },
+	 { "CRTC_STATIC_SCREEN_FRAME_COUNT", 16, 23, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CRTC_SS_STATUS", 25, 25, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "CRTC_CPU_SS_INT_TYPE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_R[] = {
+	 { "FMT_CLAMP_LOWER_R", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_G[] = {
+	 { "FMT_CLAMP_LOWER_G", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_COMPONENT_B[] = {
+	 { "FMT_CLAMP_LOWER_B", 0, 15, &umr_bitfield_default },
+	 { "FMT_CLAMP_UPPER_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEST_DEBUG_INDEX[] = {
+	 { "FMT_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "FMT_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEST_DEBUG_DATA[] = {
+	 { "FMT_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DYNAMIC_EXP_CNTL[] = {
+	 { "FMT_DYNAMIC_EXP_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_DYNAMIC_EXP_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CONTROL[] = {
+	 { "FMT_STEREOSYNC_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "FMT_STEREOSYNC_OVR_POL", 4, 4, &umr_bitfield_default },
+	 { "FMT_PIXEL_ENCODING", 16, 16, &umr_bitfield_default },
+	 { "FMT_SUBSAMPLING_MODE", 17, 17, &umr_bitfield_default },
+	 { "FMT_SUBSAMPLING_ORDER", 18, 18, &umr_bitfield_default },
+	 { "FMT_SRC_SELECT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_FORCE_OUTPUT_CNTL[] = {
+	 { "FMT_FORCE_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA_SEL_COLOR", 8, 10, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA_SEL_SLOT", 12, 15, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA_ON_BLANKb_ONLY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_FORCE_DATA_0_1[] = {
+	 { "FMT_FORCE_DATA0", 0, 15, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_FORCE_DATA_2_3[] = {
+	 { "FMT_FORCE_DATA2", 0, 15, &umr_bitfield_default },
+	 { "FMT_FORCE_DATA3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_BIT_DEPTH_CONTROL[] = {
+	 { "FMT_TRUNCATE_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_TRUNCATE_MODE", 1, 1, &umr_bitfield_default },
+	 { "FMT_TRUNCATE_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_EN", 8, 8, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_MODE", 9, 10, &umr_bitfield_default },
+	 { "FMT_SPATIAL_DITHER_DEPTH", 11, 12, &umr_bitfield_default },
+	 { "FMT_FRAME_RANDOM_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "FMT_RGB_RANDOM_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "FMT_HIGHPASS_RANDOM_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_EN", 16, 16, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_DEPTH", 17, 18, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_OFFSET", 21, 22, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_LEVEL", 24, 24, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_RESET", 25, 25, &umr_bitfield_default },
+	 { "FMT_25FRC_SEL", 26, 27, &umr_bitfield_default },
+	 { "FMT_50FRC_SEL", 28, 29, &umr_bitfield_default },
+	 { "FMT_75FRC_SEL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_R_SEED[] = {
+	 { "FMT_RAND_R_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_R_CR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_G_SEED[] = {
+	 { "FMT_RAND_G_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_G_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DITHER_RAND_B_SEED[] = {
+	 { "FMT_RAND_B_SEED", 0, 7, &umr_bitfield_default },
+	 { "FMT_OFFSET_B_CB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT", 0, 0, &umr_bitfield_default },
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[] = {
+	 { "FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CLAMP_CNTL[] = {
+	 { "FMT_CLAMP_DATA_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_CLAMP_COLOR_FORMAT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_CNTL[] = {
+	 { "FMT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "FMT_DTMTEST_CRC_EN", 1, 1, &umr_bitfield_default },
+	 { "FMT_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "FMT_CRC_ONLY_BLANKb", 8, 8, &umr_bitfield_default },
+	 { "FMT_CRC_INTERLACE_MODE", 12, 13, &umr_bitfield_default },
+	 { "FMT_CRC_USE_NEW_AND_REPEATED_PIXELS", 16, 16, &umr_bitfield_default },
+	 { "FMT_CRC_EVEN_ODD_PIX_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "FMT_CRC_EVEN_ODD_PIX_SELECT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_RED_GREEN_MASK[] = {
+	 { "FMT_CRC_SIG_RED_MASK", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_GREEN_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_BLUE_CONTROL_MASK[] = {
+	 { "FMT_CRC_SIG_BLUE_MASK", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_CONTROL_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_RED_GREEN[] = {
+	 { "FMT_CRC_SIG_RED", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_CRC_SIG_BLUE_CONTROL[] = {
+	 { "FMT_CRC_SIG_BLUE", 0, 15, &umr_bitfield_default },
+	 { "FMT_CRC_SIG_CONTROL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmFMT_DEBUG_CNTL[] = {
+	 { "FMT_DEBUG_COLOR_SELECT", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMA_POSITION_LOWER_BASE_ADDRESS[] = {
+	 { "DMA_POSITION_BUFFER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DMA_POSITION_LOWER_BASE_UNIMPLEMENTED_BITS", 1, 6, &umr_bitfield_default },
+	 { "DMA_POSITION_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_M[] = {
+	 { "DP_AUX1_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FE_CNTL[] = {
+	 { "DIG_SOURCE_SELECT", 0, 2, &umr_bitfield_default },
+	 { "DIG_STEREOSYNC_SELECT", 4, 6, &umr_bitfield_default },
+	 { "DIG_STEREOSYNC_GATE_EN", 8, 8, &umr_bitfield_default },
+	 { "DIG_START", 10, 10, &umr_bitfield_default },
+	 { "DIG_DUAL_LINK_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DIG_SWAP", 18, 18, &umr_bitfield_default },
+	 { "DIG_RB_SWITCH_EN", 20, 20, &umr_bitfield_default },
+	 { "DIG_SYMCLK_FE_ON", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_OUTPUT_CRC_CNTL[] = {
+	 { "DIG_OUTPUT_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_OUTPUT_CRC_LINK_SEL", 4, 4, &umr_bitfield_default },
+	 { "DIG_OUTPUT_CRC_DATA_SEL", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_OUTPUT_CRC_RESULT[] = {
+	 { "DIG_OUTPUT_CRC_RESULT", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_CLOCK_PATTERN[] = {
+	 { "DIG_CLOCK_PATTERN", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_TEST_PATTERN[] = {
+	 { "DIG_TEST_PATTERN_OUT_EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_HALF_CLOCK_PATTERN_SEL", 1, 1, &umr_bitfield_default },
+	 { "LVDS_TEST_CLOCK_DATA", 2, 2, &umr_bitfield_default },
+	 { "DIG_RANDOM_PATTERN_OUT_EN", 4, 4, &umr_bitfield_default },
+	 { "DIG_RANDOM_PATTERN_RESET", 5, 5, &umr_bitfield_default },
+	 { "DIG_TEST_PATTERN_EXTERNAL_RESET_EN", 6, 6, &umr_bitfield_default },
+	 { "LVDS_EYE_PATTERN", 8, 8, &umr_bitfield_default },
+	 { "DIG_STATIC_TEST_PATTERN", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_RANDOM_PATTERN_SEED[] = {
+	 { "DIG_RANDOM_PATTERN_SEED", 0, 23, &umr_bitfield_default },
+	 { "DIG_RAN_PAT_DURING_DE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_DISPCLK_SWITCH_CNTL[] = {
+	 { "DIG_DISPCLK_SWITCH_POINT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_DISPCLK_SWITCH_STATUS[] = {
+	 { "DIG_DISPCLK_SWITCH_ALLOWED", 0, 0, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT", 4, 4, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK", 8, 8, &umr_bitfield_default },
+	 { "DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_FIFO_STATUS[] = {
+	 { "DIG_FIFO_LEVEL_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DIG_FIFO_USE_OVERWRITE_LEVEL", 1, 1, &umr_bitfield_default },
+	 { "DIG_FIFO_OVERWRITE_LEVEL", 2, 7, &umr_bitfield_default },
+	 { "DIG_FIFO_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "DIG_FIFO_CAL_AVERAGE_LEVEL", 10, 15, &umr_bitfield_default },
+	 { "DIG_FIFO_MAXIMUM_LEVEL", 16, 20, &umr_bitfield_default },
+	 { "DIG_FIFO_MINIMUM_LEVEL", 22, 25, &umr_bitfield_default },
+	 { "DIG_FIFO_CALIBRATED", 29, 29, &umr_bitfield_default },
+	 { "DIG_FIFO_FORCE_RECAL_AVERAGE", 30, 30, &umr_bitfield_default },
+	 { "DIG_FIFO_FORCE_RECOMP_MINMAX", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_CONTROL[] = {
+	 { "HDMI_KEEPOUT_MODE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_PACKET_GEN_VERSION", 4, 4, &umr_bitfield_default },
+	 { "HDMI_ERROR_ACK", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ERROR_MASK", 9, 9, &umr_bitfield_default },
+	 { "HDMI_DEEP_COLOR_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "HDMI_DEEP_COLOR_DEPTH", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_STATUS[] = {
+	 { "HDMI_ACTIVE_AVMUTE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_AUDIO_PACKET_ERROR", 16, 16, &umr_bitfield_default },
+	 { "HDMI_VBI_PACKET_ERROR", 20, 20, &umr_bitfield_default },
+	 { "HDMI_ERROR_INT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_AUDIO_PACKET_CONTROL[] = {
+	 { "HDMI_AUDIO_DELAY_EN", 4, 5, &umr_bitfield_default },
+	 { "HDMI_AUDIO_SEND_MAX_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "HDMI_AUDIO_PACKETS_PER_LINE", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_PACKET_CONTROL[] = {
+	 { "HDMI_ACR_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_ACR_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_ACR_SELECT", 4, 5, &umr_bitfield_default },
+	 { "HDMI_ACR_SOURCE", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ACR_AUTO_SEND", 12, 12, &umr_bitfield_default },
+	 { "HDMI_ACR_N_MULTIPLE", 16, 18, &umr_bitfield_default },
+	 { "HDMI_ACR_AUDIO_PRIORITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_VBI_PACKET_CONTROL[] = {
+	 { "HDMI_NULL_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GC_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GC_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_ISRC_SEND", 8, 8, &umr_bitfield_default },
+	 { "HDMI_ISRC_CONT", 9, 9, &umr_bitfield_default },
+	 { "HDMI_ISRC_LINE", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_INFOFRAME_CONTROL0[] = {
+	 { "HDMI_AVI_INFO_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_AVI_INFO_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_SEND", 8, 8, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_CONT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_INFOFRAME_CONTROL1[] = {
+	 { "HDMI_AVI_INFO_LINE", 0, 5, &umr_bitfield_default },
+	 { "HDMI_AUDIO_INFO_LINE", 8, 13, &umr_bitfield_default },
+	 { "HDMI_MPEG_INFO_LINE", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GENERIC_PACKET_CONTROL0[] = {
+	 { "HDMI_GENERIC0_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GENERIC0_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_GENERIC0_LINE", 16, 21, &umr_bitfield_default },
+	 { "HDMI_GENERIC1_LINE", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GC[] = {
+	 { "HDMI_GC_AVMUTE", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GC_AVMUTE_CONT", 2, 2, &umr_bitfield_default },
+	 { "HDMI_DEFAULT_PHASE", 4, 4, &umr_bitfield_default },
+	 { "HDMI_PACKING_PHASE", 8, 11, &umr_bitfield_default },
+	 { "HDMI_PACKING_PHASE_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL2[] = {
+	 { "AFMT_AUDIO_LAYOUT_OVRD", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_LAYOUT_SELECT", 1, 1, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_ENABLE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_DP_AUDIO_STREAM_ID", 16, 23, &umr_bitfield_default },
+	 { "AFMT_HBR_ENABLE_OVRD", 24, 24, &umr_bitfield_default },
+	 { "AFMT_60958_OSF_OVRD", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_0[] = {
+	 { "AFMT_ISRC_STATUS", 0, 2, &umr_bitfield_default },
+	 { "AFMT_ISRC_CONTINUE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_ISRC_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_1[] = {
+	 { "AFMT_UPC_EAN_ISRC0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_2[] = {
+	 { "AFMT_UPC_EAN_ISRC4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_3[] = {
+	 { "AFMT_UPC_EAN_ISRC8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC9", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC1_4[] = {
+	 { "AFMT_UPC_EAN_ISRC12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_0[] = {
+	 { "AFMT_UPC_EAN_ISRC16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_1[] = {
+	 { "AFMT_UPC_EAN_ISRC20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_2[] = {
+	 { "AFMT_UPC_EAN_ISRC24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_ISRC2_3[] = {
+	 { "AFMT_UPC_EAN_ISRC28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_UPC_EAN_ISRC31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO0[] = {
+	 { "AFMT_AVI_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_S", 8, 9, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_B", 10, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_A", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Y", 13, 14, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PB1_RSVD", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_R", 16, 19, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_M", 20, 21, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_C", 22, 23, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_SC", 24, 25, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_Q", 26, 27, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_EC", 28, 30, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_ITC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO1[] = {
+	 { "AFMT_AVI_INFO_VIC", 0, 6, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PB4_RSVD", 7, 7, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_PR", 8, 11, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_CN", 12, 13, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_YQ", 14, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO2[] = {
+	 { "AFMT_AVI_INFO_BOTTOM", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_LEFT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AVI_INFO3[] = {
+	 { "AFMT_AVI_INFO_RIGHT", 0, 15, &umr_bitfield_default },
+	 { "AFMT_AVI_INFO_VERSION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO0[] = {
+	 { "AFMT_MPEG_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB0", 8, 15, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB1", 16, 23, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MB2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_MPEG_INFO1[] = {
+	 { "AFMT_MPEG_INFO_MB3", 0, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_MF", 8, 9, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_FR", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_HDR[] = {
+	 { "AFMT_GENERIC_HB0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_HB3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_0[] = {
+	 { "AFMT_GENERIC_BYTE0", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE1", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE2", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_1[] = {
+	 { "AFMT_GENERIC_BYTE4", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE5", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE6", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_2[] = {
+	 { "AFMT_GENERIC_BYTE8", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE9", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE10", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_3[] = {
+	 { "AFMT_GENERIC_BYTE12", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE13", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE14", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_4[] = {
+	 { "AFMT_GENERIC_BYTE16", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE17", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE18", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE19", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_5[] = {
+	 { "AFMT_GENERIC_BYTE20", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE21", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE22", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE23", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_6[] = {
+	 { "AFMT_GENERIC_BYTE24", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE25", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE26", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE27", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_GENERIC_7[] = {
+	 { "AFMT_GENERIC_BYTE28", 0, 7, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE29", 8, 15, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE30", 16, 23, &umr_bitfield_default },
+	 { "AFMT_GENERIC_BYTE31", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_GENERIC_PACKET_CONTROL1[] = {
+	 { "HDMI_GENERIC2_SEND", 0, 0, &umr_bitfield_default },
+	 { "HDMI_GENERIC2_CONT", 1, 1, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_SEND", 4, 4, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_CONT", 5, 5, &umr_bitfield_default },
+	 { "HDMI_GENERIC2_LINE", 16, 21, &umr_bitfield_default },
+	 { "HDMI_GENERIC3_LINE", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_32_0[] = {
+	 { "HDMI_ACR_CTS_32", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_32_1[] = {
+	 { "HDMI_ACR_N_32", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_44_0[] = {
+	 { "HDMI_ACR_CTS_44", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_44_1[] = {
+	 { "HDMI_ACR_N_44", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_48_0[] = {
+	 { "HDMI_ACR_CTS_48", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_48_1[] = {
+	 { "HDMI_ACR_N_48", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_STATUS_0[] = {
+	 { "HDMI_ACR_CTS", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDMI_ACR_STATUS_1[] = {
+	 { "HDMI_ACR_N", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO0[] = {
+	 { "AFMT_AUDIO_INFO_CHECKSUM", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CC", 8, 10, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CT", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CHECKSUM_OFFSET", 16, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_CXT", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_INFO1[] = {
+	 { "AFMT_AUDIO_INFO_CA", 0, 7, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LSV", 11, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_DM_INH", 15, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_LFEPBL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_0[] = {
+	 { "AFMT_60958_CS_A", 0, 0, &umr_bitfield_default },
+	 { "AFMT_60958_CS_B", 1, 1, &umr_bitfield_default },
+	 { "AFMT_60958_CS_C", 2, 2, &umr_bitfield_default },
+	 { "AFMT_60958_CS_D", 3, 5, &umr_bitfield_default },
+	 { "AFMT_60958_CS_MODE", 6, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CATEGORY_CODE", 8, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SOURCE_NUMBER", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_L", 20, 23, &umr_bitfield_default },
+	 { "AFMT_60958_CS_SAMPLING_FREQUENCY", 24, 27, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CLOCK_ACCURACY", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_1[] = {
+	 { "AFMT_60958_CS_WORD_LENGTH", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_L", 16, 16, &umr_bitfield_default },
+	 { "AFMT_60958_VALID_R", 18, 18, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_R", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_CONTROL[] = {
+	 { "AFMT_AUDIO_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CONT", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_SOURCE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_CH_SEL", 12, 15, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL0[] = {
+	 { "AFMT_RAMP_MAX_COUNT", 0, 23, &umr_bitfield_default },
+	 { "AFMT_RAMP_DATA_SIGN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL1[] = {
+	 { "AFMT_RAMP_MIN_COUNT", 0, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_CH_DISABLE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL2[] = {
+	 { "AFMT_RAMP_INC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_RAMP_CONTROL3[] = {
+	 { "AFMT_RAMP_DEC_COUNT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_60958_2[] = {
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_4", 8, 11, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_5", 12, 15, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_6", 16, 19, &umr_bitfield_default },
+	 { "AFMT_60958_CS_CHANNEL_NUMBER_7", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_CRC_RESULT[] = {
+	 { "AFMT_AUDIO_CRC_DONE", 0, 0, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CRC", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_STATUS[] = {
+	 { "AFMT_AUDIO_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "AFMT_AZ_HBR_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW", 24, 24, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_PACKET_CONTROL[] = {
+	 { "AFMT_AUDIO_SAMPLE_SEND", 0, 0, &umr_bitfield_default },
+	 { "AFMT_RESET_FIFO_WHEN_AUDIO_DIS", 11, 11, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_EN", 12, 12, &umr_bitfield_default },
+	 { "AFMT_AUDIO_TEST_MODE", 14, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_FIFO_OVERFLOW_ACK", 23, 23, &umr_bitfield_default },
+	 { "AFMT_AUDIO_CHANNEL_SWAP", 24, 24, &umr_bitfield_default },
+	 { "AFMT_60958_CS_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "AFMT_AZ_AUDIO_ENABLE_CHG_ACK", 30, 30, &umr_bitfield_default },
+	 { "AFMT_BLANK_TEST_DATA_ON_ENC_ENB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_VBI_PACKET_CONTROL[] = {
+	 { "AFMT_GENERIC0_UPDATE", 2, 2, &umr_bitfield_default },
+	 { "AFMT_GENERIC2_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "AFMT_GENERIC_INDEX", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_INFOFRAME_CONTROL0[] = {
+	 { "AFMT_AUDIO_INFO_SOURCE", 6, 6, &umr_bitfield_default },
+	 { "AFMT_AUDIO_INFO_UPDATE", 7, 7, &umr_bitfield_default },
+	 { "AFMT_MPEG_INFO_UPDATE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_SRC_CONTROL[] = {
+	 { "AFMT_AUDIO_SRC_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_BE_CNTL[] = {
+	 { "DIG_FE_SOURCE_SELECT", 8, 14, &umr_bitfield_default },
+	 { "DIG_MODE", 16, 18, &umr_bitfield_default },
+	 { "DIG_HPD_SELECT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_BE_EN_CNTL[] = {
+	 { "DIG_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DIG_SYMCLK_BE_ON", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmAFMT_AUDIO_DBG_DTO_CNTL[] = {
+	 { "AFMT_AUDIO_DTO_FS_DIV_SEL", 0, 2, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_BASE", 8, 8, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_MULTI", 12, 14, &umr_bitfield_default },
+	 { "AFMT_AUDIO_DTO_DBG_DIV", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CNTL[] = {
+	 { "TMDS_SYNC_PHASE", 0, 0, &umr_bitfield_default },
+	 { "TMDS_PIXEL_ENCODING", 4, 4, &umr_bitfield_default },
+	 { "TMDS_COLOR_FORMAT", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CONTROL_CHAR[] = {
+	 { "TMDS_CONTROL_CHAR0_OUT_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR1_OUT_EN", 1, 1, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR2_OUT_EN", 2, 2, &umr_bitfield_default },
+	 { "TMDS_CONTROL_CHAR3_OUT_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CONTROL0_FEEDBACK[] = {
+	 { "TMDS_CONTROL0_FEEDBACK_SELECT", 0, 1, &umr_bitfield_default },
+	 { "TMDS_CONTROL0_FEEDBACK_DELAY", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_STEREOSYNC_CTL_SEL[] = {
+	 { "TMDS_STEREOSYNC_CTL_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_SYNC_CHAR_PATTERN_0_1[] = {
+	 { "TMDS_SYNC_CHAR_PATTERN0", 0, 9, &umr_bitfield_default },
+	 { "TMDS_SYNC_CHAR_PATTERN1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_SYNC_CHAR_PATTERN_2_3[] = {
+	 { "TMDS_SYNC_CHAR_PATTERN2", 0, 9, &umr_bitfield_default },
+	 { "TMDS_SYNC_CHAR_PATTERN3", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_DEBUG[] = {
+	 { "TMDS_DEBUG_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_DEBUG_HSYNC", 8, 8, &umr_bitfield_default },
+	 { "TMDS_DEBUG_HSYNC_EN", 9, 9, &umr_bitfield_default },
+	 { "TMDS_DEBUG_VSYNC", 16, 16, &umr_bitfield_default },
+	 { "TMDS_DEBUG_VSYNC_EN", 17, 17, &umr_bitfield_default },
+	 { "TMDS_DEBUG_DE", 24, 24, &umr_bitfield_default },
+	 { "TMDS_DEBUG_DE_EN", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL_BITS[] = {
+	 { "TMDS_CTL0", 0, 0, &umr_bitfield_default },
+	 { "TMDS_CTL1", 8, 8, &umr_bitfield_default },
+	 { "TMDS_CTL2", 16, 16, &umr_bitfield_default },
+	 { "TMDS_CTL3", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_DCBALANCER_CONTROL[] = {
+	 { "TMDS_DCBALANCER_EN", 0, 0, &umr_bitfield_default },
+	 { "TMDS_SYNC_DCBAL_EN", 4, 6, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_TEST_EN", 8, 8, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_TEST_IN", 16, 19, &umr_bitfield_default },
+	 { "TMDS_DCBALANCER_FORCE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL0_1_GEN_CNTL[] = {
+	 { "TMDS_CTL0_DATA_SEL", 0, 3, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_DELAY", 4, 6, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_INVERT", 7, 7, &umr_bitfield_default },
+	 { "TMDS_CTL0_DATA_MODULATION", 8, 9, &umr_bitfield_default },
+	 { "TMDS_CTL0_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
+	 { "TMDS_CTL0_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
+	 { "TMDS_CTL0_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_SEL", 16, 19, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_DELAY", 20, 22, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_INVERT", 23, 23, &umr_bitfield_default },
+	 { "TMDS_CTL1_DATA_MODULATION", 24, 25, &umr_bitfield_default },
+	 { "TMDS_CTL1_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
+	 { "TMDS_CTL1_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
+	 { "TMDS_CTL1_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
+	 { "TMDS_2BIT_COUNTER_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTMDS_CTL2_3_GEN_CNTL[] = {
+	 { "TMDS_CTL2_DATA_SEL", 0, 3, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_DELAY", 4, 6, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_INVERT", 7, 7, &umr_bitfield_default },
+	 { "TMDS_CTL2_DATA_MODULATION", 8, 9, &umr_bitfield_default },
+	 { "TMDS_CTL2_USE_FEEDBACK_PATH", 10, 10, &umr_bitfield_default },
+	 { "TMDS_CTL2_FB_SYNC_CONT", 11, 11, &umr_bitfield_default },
+	 { "TMDS_CTL2_PATTERN_OUT_EN", 12, 12, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_SEL", 16, 19, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_DELAY", 20, 22, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_INVERT", 23, 23, &umr_bitfield_default },
+	 { "TMDS_CTL3_DATA_MODULATION", 24, 25, &umr_bitfield_default },
+	 { "TMDS_CTL3_USE_FEEDBACK_PATH", 26, 26, &umr_bitfield_default },
+	 { "TMDS_CTL3_FB_SYNC_CONT", 27, 27, &umr_bitfield_default },
+	 { "TMDS_CTL3_PATTERN_OUT_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLVDS_DATA_CNTL[] = {
+	 { "LVDS_24BIT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LVDS_24BIT_FORMAT", 4, 4, &umr_bitfield_default },
+	 { "LVDS_2ND_CHAN_DE", 8, 8, &umr_bitfield_default },
+	 { "LVDS_2ND_CHAN_VS", 9, 9, &umr_bitfield_default },
+	 { "LVDS_2ND_CHAN_HS", 10, 10, &umr_bitfield_default },
+	 { "LVDS_2ND_LINK_CNTL_BITS", 12, 14, &umr_bitfield_default },
+	 { "LVDS_FP_POL", 16, 16, &umr_bitfield_default },
+	 { "LVDS_LP_POL", 17, 17, &umr_bitfield_default },
+	 { "LVDS_DTMG_POL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIG_LANE_ENABLE[] = {
+	 { "DIG_LANE0EN", 0, 0, &umr_bitfield_default },
+	 { "DIG_LANE1EN", 1, 1, &umr_bitfield_default },
+	 { "DIG_LANE2EN", 2, 2, &umr_bitfield_default },
+	 { "DIG_LANE3EN", 3, 3, &umr_bitfield_default },
+	 { "DIG_CLK_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_CNTL[] = {
+	 { "DP_SEC_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_SEC_ASP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_ATP_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "DP_SEC_AIP_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DP_SEC_ACM_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DP_SEC_GSP0_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "DP_SEC_GSP1_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "DP_SEC_GSP2_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "DP_SEC_GSP3_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "DP_SEC_AVI_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "DP_SEC_MPG_ENABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING1[] = {
+	 { "DP_SEC_FRAME_START_LOCATION", 0, 11, &umr_bitfield_default },
+	 { "DP_SEC_VBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING2[] = {
+	 { "DP_SEC_START_POSITION", 0, 15, &umr_bitfield_default },
+	 { "DP_SEC_HBLANK_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING3[] = {
+	 { "DP_SEC_IDLE_FRAME_SIZE", 0, 13, &umr_bitfield_default },
+	 { "DP_SEC_IDLE_TRANSMIT_WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_FRAMING4[] = {
+	 { "DP_SEC_COLLISION_STATUS", 20, 20, &umr_bitfield_default },
+	 { "DP_SEC_COLLISION_ACK", 24, 24, &umr_bitfield_default },
+	 { "DP_SEC_AUDIO_MUTE", 28, 28, &umr_bitfield_default },
+	 { "DP_SEC_AUDIO_MUTE_STATUS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_N[] = {
+	 { "DP_SEC_AUD_N", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_N_READBACK[] = {
+	 { "DP_SEC_AUD_N_READBACK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_M[] = {
+	 { "DP_SEC_AUD_M", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_AUD_M_READBACK[] = {
+	 { "DP_SEC_AUD_M_READBACK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_TIMESTAMP[] = {
+	 { "DP_SEC_TIMESTAMP_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_PACKET_CNTL[] = {
+	 { "DP_SEC_ASP_CODING_TYPE", 1, 3, &umr_bitfield_default },
+	 { "DP_SEC_ASP_PRIORITY", 4, 4, &umr_bitfield_default },
+	 { "DP_SEC_VERSION", 8, 13, &umr_bitfield_default },
+	 { "DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_SEC_CNTL1[] = {
+	 { "DP_SEC_ISRC_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_LINK_CNTL[] = {
+	 { "DP_LINK_TRAINING_COMPLETE", 4, 4, &umr_bitfield_default },
+	 { "DP_LINK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DP_EMBEDDED_PANEL_MODE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_PIXEL_FORMAT[] = {
+	 { "DP_PIXEL_ENCODING", 0, 2, &umr_bitfield_default },
+	 { "DP_DYN_RANGE", 8, 8, &umr_bitfield_default },
+	 { "DP_YCBCR_RANGE", 16, 16, &umr_bitfield_default },
+	 { "DP_COMPONENT_DEPTH", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_CONFIG[] = {
+	 { "DP_UDI_LANES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_STREAM_CNTL[] = {
+	 { "DP_VID_STREAM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DIS_DEFER", 8, 9, &umr_bitfield_default },
+	 { "DP_VID_STREAM_STATUS", 16, 16, &umr_bitfield_default },
+	 { "DP_VID_STREAM_CHANGE_KEEPOUT", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_STEER_FIFO[] = {
+	 { "DP_STEER_FIFO_RESET", 0, 0, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_FLAG", 4, 4, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_INT", 5, 5, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_ACK", 6, 6, &umr_bitfield_default },
+	 { "DP_STEER_OVERFLOW_MASK", 7, 7, &umr_bitfield_default },
+	 { "DP_TU_OVERFLOW_FLAG", 8, 8, &umr_bitfield_default },
+	 { "DP_TU_OVERFLOW_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_MISC[] = {
+	 { "DP_MSA_MISC1", 3, 6, &umr_bitfield_default },
+	 { "DP_MSA_MISC2", 8, 15, &umr_bitfield_default },
+	 { "DP_MSA_MISC3", 16, 23, &umr_bitfield_default },
+	 { "DP_MSA_MISC4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_MST_CNTL[] = {
+	 { "DPHY_CRC_MST_FIRST_SLOT", 0, 5, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_LAST_SLOT", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_MST_STATUS[] = {
+	 { "DPHY_CRC_MST_PHASE_LOCK", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_PHASE_ERROR", 8, 8, &umr_bitfield_default },
+	 { "DPHY_CRC_MST_PHASE_ERROR_ACK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_HBR2_EYE_PATTERN[] = {
+	 { "DP_HBR2_EYE_PATTERN_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_TIMING[] = {
+	 { "DP_VID_TIMING_MODE", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_M_N_GEN_EN", 8, 8, &umr_bitfield_default },
+	 { "DP_VID_N_DIV", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_N[] = {
+	 { "DP_VID_N", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_M[] = {
+	 { "DP_VID_M", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_LINK_FRAMING_CNTL[] = {
+	 { "DP_IDLE_BS_INTERVAL", 0, 17, &umr_bitfield_default },
+	 { "DP_VBID_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "DP_VID_ENHANCED_FRAME_MODE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_MSA_VBID[] = {
+	 { "DP_VID_MSA_LOCATION", 0, 11, &umr_bitfield_default },
+	 { "DP_VID_MSA_TOP_FIELD_MODE", 16, 16, &umr_bitfield_default },
+	 { "DP_VID_VBID_FIELD_POL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_FAST_TRAINING[] = {
+	 { "DPHY_RX_FAST_TRAINING_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "DPHY_SW_FAST_TRAINING_START", 1, 1, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN", 2, 2, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_TP1_TIME", 8, 19, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_TP2_TIME", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_VID_INTERRUPT_CNTL[] = {
+	 { "DP_VID_STREAM_DISABLE_INT", 0, 0, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DISABLE_ACK", 1, 1, &umr_bitfield_default },
+	 { "DP_VID_STREAM_DISABLE_MASK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CNTL[] = {
+	 { "DPHY_ATEST_SEL_LANE0", 0, 0, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE1", 1, 1, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE2", 2, 2, &umr_bitfield_default },
+	 { "DPHY_ATEST_SEL_LANE3", 3, 3, &umr_bitfield_default },
+	 { "DPHY_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "DPHY_SKEW_BYPASS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_TRAINING_PATTERN_SEL[] = {
+	 { "DPHY_TRAINING_PATTERN_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM0[] = {
+	 { "DPHY_SYM1", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM2", 10, 19, &umr_bitfield_default },
+	 { "DPHY_SYM3", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_8B10B_CNTL[] = {
+	 { "DPHY_8B10B_RESET", 8, 8, &umr_bitfield_default },
+	 { "DPHY_8B10B_EXT_DISP", 16, 16, &umr_bitfield_default },
+	 { "DPHY_8B10B_CUR_DISP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_PRBS_CNTL[] = {
+	 { "DPHY_PRBS_EN", 0, 0, &umr_bitfield_default },
+	 { "DPHY_PRBS_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_PRBS_SEED", 8, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SCRAM_CNTL[] = {
+	 { "DPHY_SCRAMBLER_ADVANCE", 4, 4, &umr_bitfield_default },
+	 { "DPHY_SCRAMBLER_BS_COUNT", 8, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_EN[] = {
+	 { "DPHY_CRC_EN", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_CONT_EN", 4, 4, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT_VALID", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_CNTL[] = {
+	 { "DPHY_CRC_FIELD", 0, 0, &umr_bitfield_default },
+	 { "DPHY_CRC_SEL", 4, 5, &umr_bitfield_default },
+	 { "DPHY_CRC_MASK", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_CRC_RESULT[] = {
+	 { "DPHY_CRC_RESULT", 0, 7, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT1", 8, 15, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT2", 16, 23, &umr_bitfield_default },
+	 { "DPHY_CRC_RESULT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_COLORIMETRY[] = {
+	 { "DP_MSA_MISC0_OVERRIDE", 0, 7, &umr_bitfield_default },
+	 { "DP_MSA_MISC0_OVERRIDE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_MISC_CNTL[] = {
+	 { "DP_MSE_BLANK_CODE", 0, 0, &umr_bitfield_default },
+	 { "DP_MSE_TIMESTAMP_MODE", 4, 4, &umr_bitfield_default },
+	 { "DP_MSE_ZERO_ENCODER", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM2[] = {
+	 { "DPHY_SYM7", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM8", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_SYM1[] = {
+	 { "DPHY_SYM4", 0, 9, &umr_bitfield_default },
+	 { "DPHY_SYM5", 10, 19, &umr_bitfield_default },
+	 { "DPHY_SYM6", 20, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_RATE_CNTL[] = {
+	 { "DP_MSE_RATE_Y", 0, 25, &umr_bitfield_default },
+	 { "DP_MSE_RATE_X", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_RATE_UPDATE[] = {
+	 { "DP_MSE_RATE_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT0[] = {
+	 { "DP_MSE_SAT_SRC0", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT0", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC1", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT1", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT1[] = {
+	 { "DP_MSE_SAT_SRC2", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT2", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC3", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT3", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT2[] = {
+	 { "DP_MSE_SAT_SRC4", 0, 2, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT4", 8, 13, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SRC5", 16, 18, &umr_bitfield_default },
+	 { "DP_MSE_SAT_SLOT_COUNT5", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_SAT_UPDATE[] = {
+	 { "DP_MSE_SAT_UPDATE", 0, 1, &umr_bitfield_default },
+	 { "DP_MSE_16_MTP_KEEPOUT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSE_LINK_TIMING[] = {
+	 { "DP_MSE_LINK_FRAME", 0, 9, &umr_bitfield_default },
+	 { "DP_MSE_LINK_LINE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_DPHY_FAST_TRAINING_STATUS[] = {
+	 { "DPHY_FAST_TRAINING_STATE", 0, 2, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_OCCURRED", 4, 4, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_MASK", 8, 8, &umr_bitfield_default },
+	 { "DPHY_FAST_TRAINING_COMPLETE_ACK", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_V_TIMING_OVERRIDE1[] = {
+	 { "DP_MSA_V_TIMING_OVERRIDE_EN", 0, 0, &umr_bitfield_default },
+	 { "DP_MSA_V_TOTAL_OVERRIDE", 4, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_MSA_V_TIMING_OVERRIDE2[] = {
+	 { "DP_MSA_V_BLANK_START_OVERRIDE", 0, 12, &umr_bitfield_default },
+	 { "DP_MSA_V_BLANK_END_OVERRIDE", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_TEST_DEBUG_INDEX[] = {
+	 { "DP_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DP_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDP_TEST_DEBUG_DATA[] = {
+	 { "DP_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMA_POSITION_UPPER_BASE_ADDRESS[] = {
+	 { "DMA_POSITION_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_N[] = {
+	 { "DP_AUX1_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_O[] = {
+	 { "DP_AUX1_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1E[] = {
+	 { "GRPH_DEC_RD1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_P[] = {
+	 { "DP_AUX1_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT1F[] = {
+	 { "GRPH_DEC_RD0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[] = {
+	 { "AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES", 0, 29, &umr_bitfield_default },
+	 { "CLKSTOP", 30, 30, &umr_bitfield_default },
+	 { "EPSS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_WORSTCASE_LATENCY_COUNT[] = {
+	 { "AZALIA_WORSTCASE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL2[] = {
+	 { "CRC_CHANNEL2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMIF_DEBUG02_CORE0[] = {
+	 { "DB_DATA", 0, 15, &umr_bitfield_default },
+	 { "MC_RDRET_COUNT_EN", 16, 16, &umr_bitfield_default },
+	 { "MC_RDRET_COUNTER", 17, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR1[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_CONTROL[] = {
+	 { "CONTROLLER_RESET", 0, 0, &umr_bitfield_default },
+	 { "FLUSH_CONTROL", 1, 1, &umr_bitfield_default },
+	 { "ACCEPT_UNSOLICITED_RESPONSE_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG2[] = {
+	 { "DCIO_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG1[] = {
+	 { "FMT_DEBUG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR02[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ02[] = {
+	 { "SEQ_MAP0_EN", 0, 0, &umr_bitfield_default },
+	 { "SEQ_MAP1_EN", 1, 1, &umr_bitfield_default },
+	 { "SEQ_MAP2_EN", 2, 2, &umr_bitfield_default },
+	 { "SEQ_MAP3_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[] = {
+	 { "STREAM_RESET", 0, 0, &umr_bitfield_default },
+	 { "STREAM_RUN", 1, 1, &umr_bitfield_default },
+	 { "INTERRUPT_ON_COMPLETION_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FIFO_ERROR_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DESCRIPTOR_ERROR_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE_CONTROL", 16, 17, &umr_bitfield_default },
+	 { "TRAFFIC_PRIORITY", 18, 18, &umr_bitfield_default },
+	 { "STREAM_NUMBER", 20, 23, &umr_bitfield_default },
+	 { "BUFFER_COMPLETION_INTERRUPT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "FIFO_ERROR", 27, 27, &umr_bitfield_default },
+	 { "DESCRIPTOR_ERROR", 28, 28, &umr_bitfield_default },
+	 { "FIFO_READY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_A[] = {
+	 { "DP_AUX2_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[] = {
+	 { "LINK_POSITION_IN_BUFFER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_B[] = {
+	 { "DP_AUX2_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[] = {
+	 { "CYCLIC_BUFFER_LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_C[] = {
+	 { "DP_AUX2_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT22[] = {
+	 { "GRPH_LATCH_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+	 { "STREAM_TYPE", 15, 15, &umr_bitfield_default },
+	 { "STREAM_TYPE_R", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[] = {
+	 { "LAST_VALID_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_D[] = {
+	 { "DP_AUX2_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[] = {
+	 { "FIFO_SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[] = {
+	 { "NUMBER_OF_CHANNELS", 0, 3, &umr_bitfield_default },
+	 { "BITS_PER_SAMPLE", 4, 6, &umr_bitfield_default },
+	 { "SAMPLE_BASE_DIVISOR", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_BASE_MULTIPLE", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_BASE_RATE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_E[] = {
+	 { "DP_AUX2_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[] = {
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+	 { "CHANNEL_ALLOCATION", 8, 15, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 16, 16, &umr_bitfield_default },
+	 { "DP_CONNECTION", 17, 17, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 18, 23, &umr_bitfield_default },
+	 { "LEVEL_SHIFT", 27, 30, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_F[] = {
+	 { "DP_AUX2_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[] = {
+	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS_UNIMPLEMENTED_BITS", 0, 6, &umr_bitfield_default },
+	 { "BUFFER_DESCRIPTOR_LIST_LOWER_BASE_ADDRESS", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_G[] = {
+	 { "DP_AUX2_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[] = {
+	 { "BUFFER_DESCRIPTOR_LIST_UPPER_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_H[] = {
+	 { "DP_AUX2_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[] = {
+	 { "CC", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[] = {
+	 { "KEEPALIVE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
+	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_I[] = {
+	 { "DP_AUX2_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_J[] = {
+	 { "DP_AUX2_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_K[] = {
+	 { "DP_AUX2_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_L[] = {
+	 { "DP_AUX2_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_M[] = {
+	 { "DP_AUX2_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_N[] = {
+	 { "DP_AUX2_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_O[] = {
+	 { "DP_AUX2_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_P[] = {
+	 { "DP_AUX2_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "FORMAT_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_CONTROL[] = {
+	 { "DMIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DMIF_GROUP_REQUESTS_IN_CHUNK", 2, 2, &umr_bitfield_default },
+	 { "DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT", 4, 4, &umr_bitfield_default },
+	 { "DMIF_REQ_BURST_SIZE", 8, 10, &umr_bitfield_default },
+	 { "DMIF_FORCE_TOTAL_REQ_BURST_SIZE", 12, 15, &umr_bitfield_default },
+	 { "DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS", 16, 21, &umr_bitfield_default },
+	 { "DMIF_DELAY_ARBITRATION", 24, 28, &umr_bitfield_default },
+	 { "DMIF_CHUNK_BUFF_MARGIN", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS[] = {
+	 { "DMIF_MC_SEND_ON_IDLE", 0, 5, &umr_bitfield_default },
+	 { "DMIF_CLEAR_MC_SEND_ON_IDLE", 8, 13, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_URGENT_ONLY", 17, 17, &umr_bitfield_default },
+	 { "DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT", 20, 22, &umr_bitfield_default },
+	 { "DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT", 24, 26, &umr_bitfield_default },
+	 { "DMIF_UNDERFLOW", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_HW_DEBUG[] = {
+	 { "DMIF_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ARBITRATION_CONTROL[] = {
+	 { "DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD", 0, 15, &umr_bitfield_default },
+	 { "PIPE_SWITCH_EFFICIENCY_WEIGHT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_ARBITRATION_CONTROL3[] = {
+	 { "EFFICIENCY_WEIGHT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[] = {
+	 { "CHANNEL_ID", 0, 3, &umr_bitfield_default },
+	 { "STREAM_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[] = {
+	 { "PORTID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CUMULATIVE_LATENCY_COUNT[] = {
+	 { "AZALIA_CUMULATIVE_LATENCY_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL3[] = {
+	 { "CRC_CHANNEL3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTATE_CHANGE_STATUS[] = {
+	 { "STATE_CHANGE_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR2[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG3[] = {
+	 { "DCIO_DEBUG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFMT_DEBUG2[] = {
+	 { "FMT_DEBUG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR03[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ03[] = {
+	 { "SEQ_FONT_B1", 0, 0, &umr_bitfield_default },
+	 { "SEQ_FONT_B2", 1, 1, &umr_bitfield_default },
+	 { "SEQ_FONT_A1", 2, 2, &umr_bitfield_default },
+	 { "SEQ_FONT_A2", 3, 3, &umr_bitfield_default },
+	 { "SEQ_FONT_B0", 4, 4, &umr_bitfield_default },
+	 { "SEQ_FONT_A0", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_A[] = {
+	 { "DP_AUX3_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_ADDR_CALC[] = {
+	 { "ADDR_CONFIG_PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ADDR_CONFIG_ROW_SIZE", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_STATUS2[] = {
+	 { "DMIF_PIPE0_DISPCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DMIF_PIPE1_DISPCLK_STATUS", 1, 1, &umr_bitfield_default },
+	 { "DMIF_PIPE2_DISPCLK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "DMIF_PIPE3_DISPCLK_STATUS", 3, 3, &umr_bitfield_default },
+	 { "DMIF_PIPE4_DISPCLK_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DMIF_PIPE5_DISPCLK_STATUS", 5, 5, &umr_bitfield_default },
+	 { "DMIF_CHUNK_TRACKER_SCLK_STATUS", 8, 8, &umr_bitfield_default },
+	 { "DMIF_FBC_TRACKER_SCLK_STATUS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_MAX_REQUESTS[] = {
+	 { "MAX_REQUESTS", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_B[] = {
+	 { "DP_AUX3_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_RBBMIF_RDWR_CNTL3[] = {
+	 { "DC_RBBMIF_CLIENT10_RDWR_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT10_RDWR_TIMEOUT_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_RBBMIF_TIMEOUT_DELAY", 12, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_INDEX[] = {
+	 { "DMIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DMIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDMIF_TEST_DEBUG_DATA[] = {
+	 { "DMIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_CONTROL[] = {
+	 { "MCIF_BUFF_SIZE", 0, 1, &umr_bitfield_default },
+	 { "MCIF_SCANIN_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "ADDRESS_TRANSLATION_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "PRIVILEGED_ACCESS_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MCIF_SLOW_REQ_INTERVAL", 12, 15, &umr_bitfield_default },
+	 { "LOW_READ_URG_LEVEL", 16, 23, &umr_bitfield_default },
+	 { "MC_CLEAN_DEASSERT_LATENCY", 24, 29, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "MCIF_MC_LATENCY_COUNTER_URGENT_ONLY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WRITE_COMBINE_CONTROL[] = {
+	 { "MCIF_WRITE_COMBINE_TIMEOUT", 0, 7, &umr_bitfield_default },
+	 { "VIP_WRITE_COMBINE_TIMEOUT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_INDEX[] = {
+	 { "MCIF_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MCIF_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_TEST_DEBUG_DATA[] = {
+	 { "MCIF_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_VMID[] = {
+	 { "MCIF_WR_VMID", 0, 3, &umr_bitfield_default },
+	 { "VIP_WR_VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_MEM_CONTROL[] = {
+	 { "MCIFMEM_CACHE_MODE_DIS", 0, 0, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_MODE", 4, 5, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_SIZE", 8, 15, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_PIPE", 16, 18, &umr_bitfield_default },
+	 { "MCIFMEM_CACHE_TYPE", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_RBBMIF_RDWR_CNTL1[] = {
+	 { "DC_RBBMIF_CLIENT0_RDWR_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT1_RDWR_DELAY", 6, 9, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS", 11, 11, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT2_RDWR_DELAY", 12, 15, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT3_RDWR_DELAY", 18, 21, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS", 23, 23, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT4_RDWR_DELAY", 24, 27, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATE[] = {
+	 { "DMCU_MEM_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMIF0_MEM_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMIF1_MEM_PWR_STATE", 4, 5, &umr_bitfield_default },
+	 { "DMIF2_MEM_PWR_STATE", 6, 7, &umr_bitfield_default },
+	 { "DMIF3_MEM_PWR_STATE", 8, 9, &umr_bitfield_default },
+	 { "DMIF4_MEM_PWR_STATE", 10, 11, &umr_bitfield_default },
+	 { "DMIF5_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "VGA_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "FBC_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "MCIF_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "VIP_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "AZ_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+	 { "DMIF_XLR_MEM_PWR_STATE", 24, 25, &umr_bitfield_default },
+	 { "DMIF_XLR_MEM1_PWR_STATE", 26, 27, &umr_bitfield_default },
+	 { "DMCU_IRAM_PWR_STATE", 28, 29, &umr_bitfield_default },
+	 { "MCIFWB_MEM_PWR_STATE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DC_INTERFACE_NACK_STATUS[] = {
+	 { "DMIF_RDRET_NACK_OCCURRED", 0, 0, &umr_bitfield_default },
+	 { "DMIF_RDRET_NACK_CLEAR", 4, 4, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_OCCURRED", 8, 8, &umr_bitfield_default },
+	 { "VIP_WRRET_NACK_CLEAR", 12, 12, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_OCCURRED", 16, 16, &umr_bitfield_default },
+	 { "MCIF_RDRET_NACK_CLEAR", 20, 20, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_OCCURRED", 24, 24, &umr_bitfield_default },
+	 { "MCIF_WRRET_NACK_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_RBBMIF_RDWR_CNTL2[] = {
+	 { "DC_RBBMIF_CLIENT5_RDWR_DELAY", 0, 3, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT5_RDWR_TIMEOUT_DIS", 5, 5, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT6_RDWR_DELAY", 6, 9, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT6_RDWR_TIMEOUT_DIS", 11, 11, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT7_RDWR_DELAY", 12, 15, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT7_RDWR_TIMEOUT_DIS", 17, 17, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT8_RDWR_DELAY", 18, 21, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS", 23, 23, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT9_RDWR_DELAY", 24, 27, &umr_bitfield_default },
+	 { "DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_CLK_CNTL[] = {
+	 { "DCI_TEST_CLK_SEL", 0, 4, &umr_bitfield_default },
+	 { "DISPCLK_R_DCI_GATE_DIS", 5, 5, &umr_bitfield_default },
+	 { "DISPCLK_M_GATE_DIS", 6, 6, &umr_bitfield_default },
+	 { "SCLK_G_STREAM_AZ_GATE_DIS", 7, 7, &umr_bitfield_default },
+	 { "SCLK_R_AZ_GATE_DIS", 8, 8, &umr_bitfield_default },
+	 { "DISPCLK_G_FBC_GATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "DISPCLK_R_VGA_GATE_DIS", 10, 10, &umr_bitfield_default },
+	 { "DISPCLK_G_VGA_GATE_DIS", 11, 11, &umr_bitfield_default },
+	 { "DISPCLK_R_VIP_GATE_DIS", 12, 12, &umr_bitfield_default },
+	 { "DISPCLK_G_VIP_GATE_DIS", 13, 13, &umr_bitfield_default },
+	 { "DISPCLK_R_DMCU_GATE_DIS", 14, 14, &umr_bitfield_default },
+	 { "DISPCLK_G_DMCU_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF0_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF1_GATE_DIS", 17, 17, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF2_GATE_DIS", 18, 18, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF3_GATE_DIS", 19, 19, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF4_GATE_DIS", 20, 20, &umr_bitfield_default },
+	 { "DISPCLK_G_DMIF5_GATE_DIS", 21, 21, &umr_bitfield_default },
+	 { "SCLK_G_DMIF_GATE_DIS", 22, 22, &umr_bitfield_default },
+	 { "SCLK_G_DMIFTRK_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "SCLK_G_CNTL_AZ_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "DCI_PG_TEST_CLK_SEL", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCCG_VPCLK_CNTL[] = {
+	 { "DCCG_VPCLK_POL", 0, 0, &umr_bitfield_default },
+	 { "VGA_LIGHT_SLEEP_MODE_FORCE", 1, 1, &umr_bitfield_default },
+	 { "AZ_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMCU_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "MCIF_LIGHT_SLEEP_MODE_FORCE", 4, 4, &umr_bitfield_default },
+	 { "DMIF_XLR_LIGHT_SLEEP_MODE_FORCE", 5, 5, &umr_bitfield_default },
+	 { "DMIF0_LIGHT_SLEEP_DIS", 8, 8, &umr_bitfield_default },
+	 { "DMIF1_LIGHT_SLEEP_DIS", 9, 9, &umr_bitfield_default },
+	 { "DMIF2_LIGHT_SLEEP_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF3_LIGHT_SLEEP_DIS", 11, 11, &umr_bitfield_default },
+	 { "DMIF4_LIGHT_SLEEP_DIS", 12, 12, &umr_bitfield_default },
+	 { "DMIF5_LIGHT_SLEEP_DIS", 13, 13, &umr_bitfield_default },
+	 { "FBC_LIGHT_SLEEP_DIS", 14, 14, &umr_bitfield_default },
+	 { "VIP_LIGHT_SLEEP_DIS", 15, 15, &umr_bitfield_default },
+	 { "DMCU_MEM_SHUTDOWN_DIS", 16, 16, &umr_bitfield_default },
+	 { "MCIF_MEM_SHUTDOWN_MODE_FORCE", 17, 17, &umr_bitfield_default },
+	 { "DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE", 18, 18, &umr_bitfield_default },
+	 { "FBC_MEM_SHUTDOWN_DIS", 19, 19, &umr_bitfield_default },
+	 { "DMIF0_MEM_SHUTDOWN_DIS", 20, 20, &umr_bitfield_default },
+	 { "DMIF1_MEM_SHUTDOWN_DIS", 21, 21, &umr_bitfield_default },
+	 { "DMIF2_MEM_SHUTDOWN_DIS", 22, 22, &umr_bitfield_default },
+	 { "DMIF3_MEM_SHUTDOWN_DIS", 23, 23, &umr_bitfield_default },
+	 { "DMIF4_MEM_SHUTDOWN_DIS", 24, 24, &umr_bitfield_default },
+	 { "DMIF5_MEM_SHUTDOWN_DIS", 25, 25, &umr_bitfield_default },
+	 { "AZ_MEM_SHUTDOWN_DIS", 26, 26, &umr_bitfield_default },
+	 { "MCIFWB_LIGHT_SLEEP_MODE_FORCE", 27, 27, &umr_bitfield_default },
+	 { "MCIFWB_MEM_SHUTDOWN_MODE_FORCE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_C[] = {
+	 { "DP_AUX3_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_INDEX[] = {
+	 { "DCI_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DCI_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_TEST_DEBUG_DATA[] = {
+	 { "DCI_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_STATE2[] = {
+	 { "DMCU_ERAM1_PWR_STATE", 0, 1, &umr_bitfield_default },
+	 { "DMCU_ERAM2_PWR_STATE", 2, 3, &umr_bitfield_default },
+	 { "DMCU_ERAM3_PWR_STATE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_DEBUG_CONFIG[] = {
+	 { "DCI_DBG_SEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmLOW_POWER_TILING_CONTROL[] = {
+	 { "LOW_POWER_TILING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_MODE", 3, 4, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_PIPES", 5, 7, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_NUM_BANKS", 8, 10, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE", 11, 11, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROW_SIZE", 12, 14, &umr_bitfield_default },
+	 { "LOW_POWER_TILING_ROWS_PER_CHAN", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDCI_MEM_PWR_CNTL[] = {
+	 { "DMIF0_ASYNC_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_LIGHT_SLEEP_DIS", 1, 1, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_LIGHT_SLEEP_DIS", 2, 2, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_LIGHT_SLEEP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_LIGHT_SLEEP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_LIGHT_SLEEP_DIS", 5, 5, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_SHUTDOWN_DIS", 6, 6, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_SHUTDOWN_DIS", 7, 7, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_SHUTDOWN_DIS", 9, 9, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_SHUTDOWN_DIS", 10, 10, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_SHUTDOWN_DIS", 11, 11, &umr_bitfield_default },
+	 { "DMIF0_ASYNC_MEM_PWR_STATE", 12, 13, &umr_bitfield_default },
+	 { "DMIF1_ASYNC_MEM_PWR_STATE", 14, 15, &umr_bitfield_default },
+	 { "DMIF2_ASYNC_MEM_PWR_STATE", 16, 17, &umr_bitfield_default },
+	 { "DMIF3_ASYNC_MEM_PWR_STATE", 18, 19, &umr_bitfield_default },
+	 { "DMIF4_ASYNC_MEM_PWR_STATE", 20, 21, &umr_bitfield_default },
+	 { "DMIF5_ASYNC_MEM_PWR_STATE", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_XDMA_INTERFACE_CNTL[] = {
+	 { "XDMA_PIPE_ENABLE", 0, 5, &umr_bitfield_default },
+	 { "XDMA_PIPE_SEL", 8, 10, &umr_bitfield_default },
+	 { "DC_XDMA_FLIP_PENDING", 16, 16, &umr_bitfield_default },
+	 { "XDMA_M_FLIP_PENDING_TO_DCP", 20, 20, &umr_bitfield_default },
+	 { "XDMA_S_FLIP_PENDING_TO_DCP", 21, 21, &umr_bitfield_default },
+	 { "DC_FLIP_PENDING_TO_DCP", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE0_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_D[] = {
+	 { "DP_AUX3_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE1_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE2_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_E[] = {
+	 { "DP_AUX3_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE3_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE4_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_F[] = {
+	 { "DP_AUX3_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPIPE5_DMIF_BUFFER_CONTROL[] = {
+	 { "DMIF_BUFFERS_ALLOCATED", 0, 2, &umr_bitfield_default },
+	 { "DMIF_BUFFERS_ALLOCATION_COMPLETED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUFMGR_SW_CONTROL[] = {
+	 { "MCIF_BUFMGR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_BUFMGR_SW_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "MCIF_BUFMGR_SW_INT_ACK", 5, 5, &umr_bitfield_default },
+	 { "MCIF_BUFMGR_SW_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "MCIF_BUFMGR_SW_LOCK", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUFMGR_STATUS[] = {
+	 { "MCIF_BUFMGR_SW_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "MCIF_BUFMGR_CUR_BUF", 4, 6, &umr_bitfield_default },
+	 { "MCIF_BUFMGR_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_BUFMGR_CUR_LINE", 12, 24, &umr_bitfield_default },
+	 { "MCIF_BUFMGR_NEXT_BUF", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_PITCH[] = {
+	 { "MCIF_BUF_LUMA_PITCH", 0, 15, &umr_bitfield_default },
+	 { "MCIF_BUF_CHROMA_PITCH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_1_ADDR_Y_LOW[] = {
+	 { "MCIF_BUF_ADDR_Y_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_1_ADDR_UP[] = {
+	 { "MCIF_BUF_ADDR_Y_UP", 0, 7, &umr_bitfield_default },
+	 { "MCIF_BUF_ADDR_C_UP", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_1_ADDR_C_LOW[] = {
+	 { "MCIF_BUF_ADDR_C_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_1_STATUS[] = {
+	 { "MCIF_BUF_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_BUF_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_BUF_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_BUF_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_BUF_NEW_CONTENT", 5, 5, &umr_bitfield_default },
+	 { "MCIF_BUF_STEREOSYNC", 6, 6, &umr_bitfield_default },
+	 { "MCIF_BUF_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCIF_BUF_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_BUF_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_BUF_CUR_LINE", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[] = {
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL23_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL45_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL67_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_G[] = {
+	 { "DP_AUX3_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_2_ADDR_Y_LOW[] = {
+	 { "MCIF_BUF_ADDR_Y_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_2_ADDR_UP[] = {
+	 { "MCIF_BUF_ADDR_Y_UP", 0, 7, &umr_bitfield_default },
+	 { "MCIF_BUF_ADDR_C_UP", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_2_ADDR_C_LOW[] = {
+	 { "MCIF_BUF_ADDR_C_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_2_STATUS[] = {
+	 { "MCIF_BUF_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_BUF_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_BUF_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_BUF_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_BUF_NEW_CONTENT", 5, 5, &umr_bitfield_default },
+	 { "MCIF_BUF_STEREOSYNC", 6, 6, &umr_bitfield_default },
+	 { "MCIF_BUF_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCIF_BUF_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_BUF_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_BUF_CUR_LINE", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_3_ADDR_Y_LOW[] = {
+	 { "MCIF_BUF_ADDR_Y_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_3_ADDR_UP[] = {
+	 { "MCIF_BUF_ADDR_Y_UP", 0, 7, &umr_bitfield_default },
+	 { "MCIF_BUF_ADDR_C_UP", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_3_ADDR_C_LOW[] = {
+	 { "MCIF_BUF_ADDR_C_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_3_STATUS[] = {
+	 { "MCIF_BUF_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_BUF_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_BUF_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_BUF_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_BUF_NEW_CONTENT", 5, 5, &umr_bitfield_default },
+	 { "MCIF_BUF_STEREOSYNC", 6, 6, &umr_bitfield_default },
+	 { "MCIF_BUF_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCIF_BUF_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_BUF_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_BUF_CUR_LINE", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_4_ADDR_Y_LOW[] = {
+	 { "MCIF_BUF_ADDR_Y_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_4_ADDR_UP[] = {
+	 { "MCIF_BUF_ADDR_Y_UP", 0, 7, &umr_bitfield_default },
+	 { "MCIF_BUF_ADDR_C_UP", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_4_ADDR_C_LOW[] = {
+	 { "MCIF_BUF_ADDR_C_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_BUF_4_STATUS[] = {
+	 { "MCIF_BUF_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_BUF_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_BUF_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_BUF_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_BUF_NEW_CONTENT", 5, 5, &umr_bitfield_default },
+	 { "MCIF_BUF_STEREOSYNC", 6, 6, &umr_bitfield_default },
+	 { "MCIF_BUF_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCIF_BUF_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_BUF_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_BUF_CUR_LINE", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_SI_ARBITRATION_CONTROL[] = {
+	 { "MCIF_SI_CLIENT0_ARBITRATION_SLICE", 0, 1, &umr_bitfield_default },
+	 { "MCIF_SI_CLIENT1_ARBITRATION_SLICE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_URGENCY_WATERMARK[] = {
+	 { "MCIF_SI_CLIENT0_URGENCY_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "MCIF_SI_CLIENT1_URGENCY_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[] = {
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_H[] = {
+	 { "DP_AUX3_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[] = {
+	 { "CONNECTION_LIST_ENTRY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[] = {
+	 { "OUT_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[] = {
+	 { "TAG", 0, 5, &umr_bitfield_default },
+	 { "ENABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[] = {
+	 { "IMPEDANCE_SENSE", 0, 30, &umr_bitfield_default },
+	 { "PRESENCE_DETECT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[] = {
+	 { "MISC", 0, 3, &umr_bitfield_default },
+	 { "COLOR", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[] = {
+	 { "CONNECTION_TYPE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[] = {
+	 { "LOCATION", 0, 5, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[] = {
+	 { "SPEAKER_ALLOCATION", 0, 6, &umr_bitfield_default },
+	 { "HDMI_CONNECTION", 8, 8, &umr_bitfield_default },
+	 { "DP_CONNECTION", 9, 9, &umr_bitfield_default },
+	 { "EXTRA_CONNECTION_INFO", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[] = {
+	 { "CHANNEL_ALLOCATION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[] = {
+	 { "LEVEL_SHIFT", 3, 6, &umr_bitfield_default },
+	 { "DOWN_MIX_INHIBIT", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[] = {
+	 { "DESCRIPTOR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "FORMAT_CODE", 3, 6, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[] = {
+	 { "MULTICHANNEL01_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL01_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL01_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[] = {
+	 { "MULTICHANNEL23_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL23_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL23_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[] = {
+	 { "MULTICHANNEL45_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL45_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL45_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[] = {
+	 { "MULTICHANNEL67_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL67_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL67_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[] = {
+	 { "VIDEO_LIPSYNC", 0, 7, &umr_bitfield_default },
+	 { "AUDIO_LIPSYNC", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[] = {
+	 { "SINK_INFO_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[] = {
+	 { "SINK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[] = {
+	 { "MULTICHANNEL3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[] = {
+	 { "MULTICHANNEL5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[] = {
+	 { "MULTICHANNEL7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
+	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[] = {
+	 { "HBR_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "HBR_ENABLE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_I[] = {
+	 { "DP_AUX3_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_J[] = {
+	 { "DP_AUX3_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[] = {
+	 { "MANUFACTURER_ID", 0, 15, &umr_bitfield_default },
+	 { "PRODUCT_ID", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_K[] = {
+	 { "DP_AUX3_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[] = {
+	 { "SINK_DESCRIPTION_LEN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_L[] = {
+	 { "DP_AUX3_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[] = {
+	 { "PORT_ID0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_M[] = {
+	 { "DP_AUX3_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[] = {
+	 { "PORT_ID1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_N[] = {
+	 { "DP_AUX3_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[] = {
+	 { "DESCRIPTION0", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION1", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION2", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_O[] = {
+	 { "DP_AUX3_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MC_PCIE_CLIENT_CONFIG[] = {
+	 { "XDMA_MC_PCIE_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MC_PCIE_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING1[] = {
+	 { "XDMA_LOCAL_ARRAY_MODE", 0, 3, &umr_bitfield_default },
+	 { "XDMA_LOCAL_TILE_SPLIT", 4, 6, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_WIDTH", 8, 9, &umr_bitfield_default },
+	 { "XDMA_LOCAL_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MACRO_TILE_ASPECT", 12, 13, &umr_bitfield_default },
+	 { "XDMA_LOCAL_NUM_BANKS", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_LOCAL_SURFACE_TILING2[] = {
+	 { "XDMA_LOCAL_PIPE_INTERLEAVE_SIZE", 0, 2, &umr_bitfield_default },
+	 { "XDMA_LOCAL_MICRO_TILE_MODE", 20, 22, &umr_bitfield_default },
+	 { "XDMA_LOCAL_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_INTERRUPT[] = {
+	 { "XDMA_MSTR_MEM_URGENT_STAT", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_MASK", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_ACK", 10, 10, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_STAT", 12, 12, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_MASK", 13, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_ACK", 14, 14, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_STAT", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_MASK", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_ACK", 18, 18, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_STAT", 20, 20, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_MASK", 21, 21, &umr_bitfield_default },
+	 { "XDMA_PERF_MEAS_ACK", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_CLOCK_GATING_CNTL[] = {
+	 { "XDMA_SCLK_TURN_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "XDMA_SCLK_TURN_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "XDMA_SCLK_GATE_DIS", 15, 15, &umr_bitfield_default },
+	 { "XDMA_SCLK_REG_GATE_DIS", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_0", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_1", 18, 18, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_2", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_3", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_4", 21, 21, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MDYN_GATE_DIS_PIPE_5", 22, 22, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SDYN_GATE_DIS", 23, 23, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_MSTAT_GATE_DIS", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SCLK_G_SSTAT_GATE_DIS", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MEM_POWER_CNTL[] = {
+	 { "XDMA_MEM_LIGHT_SLEEP_DIS", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MEM_SHUTDOWN_DIS", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MEM_LIGHT_SLEEP_MODE_FORCE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MEM_SHUTDOWN_MODE_FORCE", 24, 24, &umr_bitfield_default },
+	 { "XDMA_MEM_POWER_STATE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_BIF_STATUS[] = {
+	 { "XDMA_IF_BIF_ERROR_STATUS", 0, 3, &umr_bitfield_default },
+	 { "XDMA_IF_BIF_ERROR_CLEAR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PERF_MEAS_STATUS[] = {
+	 { "XDMA_PERF_MEAS_STATUS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_IF_STATUS[] = {
+	 { "XDMA_MC_PCIEWR_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_TEST_DEBUG_DATA[] = {
+	 { "XDMA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[] = {
+	 { "DESCRIPTION4", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION5", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION6", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_P[] = {
+	 { "DP_AUX3_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[] = {
+	 { "AUDIO_CHANNEL_CAPABILITIES", 0, 0, &umr_bitfield_default },
+	 { "INPUT_AMPLIFIER_PRESENT", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_AMPLIFIER_PRESENT", 2, 2, &umr_bitfield_default },
+	 { "AMPLIFIER_PARAMETER_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "STRIPE", 5, 5, &umr_bitfield_default },
+	 { "PROCESSING_WIDGET", 6, 6, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_CAPABILITY", 7, 7, &umr_bitfield_default },
+	 { "CONNECTION_LIST", 8, 8, &umr_bitfield_default },
+	 { "DIGITAL", 9, 9, &umr_bitfield_default },
+	 { "POWER_CONTROL", 10, 10, &umr_bitfield_default },
+	 { "LR_SWAP", 11, 11, &umr_bitfield_default },
+	 { "AUDIO_WIDGET_CAPABILITIES_DELAY", 16, 19, &umr_bitfield_default },
+	 { "TYPE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[] = {
+	 { "IMPEDANCE_SENSE_CAPABLE", 0, 0, &umr_bitfield_default },
+	 { "TRIGGER_REQUIRED", 1, 1, &umr_bitfield_default },
+	 { "JACK_DETECTION_CAPABILITY", 2, 2, &umr_bitfield_default },
+	 { "HEADPHONE_DRIVE_CAPABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_CAPABLE", 4, 4, &umr_bitfield_default },
+	 { "INPUT_CAPABLE", 5, 5, &umr_bitfield_default },
+	 { "BALANCED_I_O_PINS", 6, 6, &umr_bitfield_default },
+	 { "HDMI", 7, 7, &umr_bitfield_default },
+	 { "VREF_CONTROL", 8, 15, &umr_bitfield_default },
+	 { "EAPD_CAPABLE", 16, 16, &umr_bitfield_default },
+	 { "DP", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[] = {
+	 { "CONNECTION_LIST_LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_RBBMIF_RDWR_CNTL[] = {
+	 { "XDMA_RBBMIF_RDWR_DELAY", 0, 2, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_RDWR_TIMEOUT_DIS", 3, 3, &umr_bitfield_default },
+	 { "XDMA_RBBMIF_TIMEOUT_DELAY", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_CONTROL[] = {
+	 { "XDMA_PG_CONTROL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_WDATA[] = {
+	 { "XDMA_PG_WDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_PG_STATUS[] = {
+	 { "XDMA_SERDES_RDATA", 0, 23, &umr_bitfield_default },
+	 { "XDMA_PGFSM_READ_READY", 24, 24, &umr_bitfield_default },
+	 { "XDMA_SERDES_BUSY", 25, 25, &umr_bitfield_default },
+	 { "XDMA_SERDES_SMU_POWER_STATUS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_AON_TEST_DEBUG_INDEX[] = {
+	 { "XDMA_AON_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "XDMA_AON_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+	 { "XDMA_DEBUG_SEL", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_AON_TEST_DEBUG_DATA[] = {
+	 { "XDMA_AON_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[] = {
+	 { "DIGEN", 0, 0, &umr_bitfield_default },
+	 { "V", 1, 1, &umr_bitfield_default },
+	 { "VCFG", 2, 2, &umr_bitfield_default },
+	 { "PRE", 3, 3, &umr_bitfield_default },
+	 { "COPY", 4, 4, &umr_bitfield_default },
+	 { "NON_AUDIO", 5, 5, &umr_bitfield_default },
+	 { "PRO", 6, 6, &umr_bitfield_default },
+	 { "L", 7, 7, &umr_bitfield_default },
+	 { "CC", 8, 14, &umr_bitfield_default },
+	 { "KEEPALIVE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[] = {
+	 { "PORTID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CUMULATIVE_REQUEST_COUNT[] = {
+	 { "AZALIA_CUMULATIVE_REQUEST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL4[] = {
+	 { "CRC_CHANNEL4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR3[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGLOBAL_STATUS[] = {
+	 { "FLUSH_STATUS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG4[] = {
+	 { "DCIO_DEBUG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR04[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSEQ04[] = {
+	 { "SEQ_256K", 1, 1, &umr_bitfield_default },
+	 { "SEQ_ODDEVEN", 2, 2, &umr_bitfield_default },
+	 { "SEQ_CHAIN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[] = {
+	 { "DESCRIPTION8", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION9", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION10", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_A[] = {
+	 { "DP_AUX4_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[] = {
+	 { "DESCRIPTION12", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION13", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTION14", 16, 23, &umr_bitfield_default },
+	 { "DESCRIPTION15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_B[] = {
+	 { "DP_AUX4_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[] = {
+	 { "DESCRIPTION16", 0, 7, &umr_bitfield_default },
+	 { "DESCRIPTION17", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_C[] = {
+	 { "DP_AUX4_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_D[] = {
+	 { "DP_AUX4_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_E[] = {
+	 { "DP_AUX4_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_F[] = {
+	 { "DP_AUX4_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_G[] = {
+	 { "DP_AUX4_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_H[] = {
+	 { "DP_AUX4_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_I[] = {
+	 { "DP_AUX4_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_J[] = {
+	 { "DP_AUX4_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_K[] = {
+	 { "DP_AUX4_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_L[] = {
+	 { "DP_AUX4_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_M[] = {
+	 { "DP_AUX4_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSI_ENABLE[] = {
+	 { "SI_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSI_EC_CONFIG[] = {
+	 { "DISPCLK_R_SCANIN_GATE_DIS", 0, 0, &umr_bitfield_default },
+	 { "DISPCLK_G_SCANIN_GATE_DIS", 1, 1, &umr_bitfield_default },
+	 { "DISPCLK_G_SISCL_GATE_DIS", 2, 2, &umr_bitfield_default },
+	 { "DISPCLK_R_SCANIN_RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "DISPCLK_G_SCANIN_RAMP_DIS", 4, 4, &umr_bitfield_default },
+	 { "DISPCLK_G_SISCL_RAMP_DIS", 5, 5, &umr_bitfield_default },
+	 { "SI_LB_LS_DIS", 6, 6, &umr_bitfield_default },
+	 { "SI_LB_SD_DIS", 7, 7, &umr_bitfield_default },
+	 { "SI_LUT_LS_DIS", 8, 8, &umr_bitfield_default },
+	 { "SCANIN_TEST_CLK_SEL", 12, 15, &umr_bitfield_default },
+	 { "SI_RAM_PW_SAVE_MODE", 23, 23, &umr_bitfield_default },
+	 { "LB_MEM_PWR_STATE", 28, 29, &umr_bitfield_default },
+	 { "LUT_MEM_PWR_STATE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_MODE[] = {
+	 { "CNV_INPUT_SRC_SELECT", 0, 1, &umr_bitfield_default },
+	 { "CNV_INPUT_PIPE_SELECT", 2, 4, &umr_bitfield_default },
+	 { "CNV_FRAME_COUNT", 8, 9, &umr_bitfield_default },
+	 { "CNV_WINDOW_EN", 12, 12, &umr_bitfield_default },
+	 { "CNV_EYE_SELECTION", 16, 17, &umr_bitfield_default },
+	 { "CNV_STEREO_EYE_ORDER", 18, 18, &umr_bitfield_default },
+	 { "CNV_NEW_CONTENT", 24, 24, &umr_bitfield_default },
+	 { "CNV_FRAME_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_WINDOW_START[] = {
+	 { "CNV_WINDOW_START_X", 0, 11, &umr_bitfield_default },
+	 { "CNV_WINDOW_START_Y", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_WINDOW_SIZE[] = {
+	 { "CNV_WINDOW_WIDTH", 0, 11, &umr_bitfield_default },
+	 { "CNV_WINDOW_HEIGHT", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_UPDATE[] = {
+	 { "CNV_UPDATE_PENDING", 0, 0, &umr_bitfield_default },
+	 { "CNV_UPDATE_TAKEN", 8, 8, &umr_bitfield_default },
+	 { "CNV_UPDATE_LOCK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_SOURCE_SIZE[] = {
+	 { "CNV_SOURCE_WIDTH", 0, 14, &umr_bitfield_default },
+	 { "CNV_SOURCE_HEIGHT", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CONTROL[] = {
+	 { "CNV_CSC_bypass", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C11_C12[] = {
+	 { "CNV_CSC_C11", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C12", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C13_C14[] = {
+	 { "CNV_CSC_C13", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C14", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C21_C22[] = {
+	 { "CNV_CSC_C21", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C22", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C23_C24[] = {
+	 { "CNV_CSC_C23", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C24", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C31_C32[] = {
+	 { "CNV_CSC_C31", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C32", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_C33_C34[] = {
+	 { "CNV_CSC_C33", 0, 12, &umr_bitfield_default },
+	 { "CNV_CSC_C34", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_R[] = {
+	 { "CNV_CSC_ROUND_OFFSET_R", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_G[] = {
+	 { "CNV_CSC_ROUND_OFFSET_G", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_ROUND_OFFSET_B[] = {
+	 { "CNV_CSC_ROUND_OFFSET_B", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_R[] = {
+	 { "CNV_CSC_CLAMP_UPPER_R", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_R", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_G[] = {
+	 { "CNV_CSC_CLAMP_UPPER_G", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_G", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_CSC_CLAMP_B[] = {
+	 { "CNV_CSC_CLAMP_UPPER_B", 0, 15, &umr_bitfield_default },
+	 { "CNV_CSC_CLAMP_LOWER_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CNTL[] = {
+	 { "CNV_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_RED[] = {
+	 { "CNV_TEST_CRC_RED_MASK", 0, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_GREEN[] = {
+	 { "CNV_TEST_CRC_GREEN_MASK", 0, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_CRC_BLUE[] = {
+	 { "CNV_TEST_CRC_BLUE_MASK", 0, 15, &umr_bitfield_default },
+	 { "CNV_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSI_DEBUG_CTRL[] = {
+	 { "SI_DEBUG_SEL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_DEBUG_INDEX[] = {
+	 { "CNV_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "CNV_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCNV_TEST_DEBUG_DATA[] = {
+	 { "CNV_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSI_DBG_MODE[] = {
+	 { "SI_DBG_MODE_EN", 0, 0, &umr_bitfield_default },
+	 { "SI_DBG_DIN_FMT", 1, 1, &umr_bitfield_default },
+	 { "SI_DBG_36MODE", 2, 2, &umr_bitfield_default },
+	 { "SI_DBG_CMAP", 3, 3, &umr_bitfield_default },
+	 { "SI_DBG_PXLRATE_ERROR", 8, 8, &umr_bitfield_default },
+	 { "SI_DBG_SOURCE_WIDTH", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSI_HARD_DEBUG[] = {
+	 { "SI_HARD_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_COEF_RAM_SELECT[] = {
+	 { "SISCL_COEF_RAM_TAP_PAIR_IDX", 0, 2, &umr_bitfield_default },
+	 { "SISCL_COEF_RAM_PHASE", 8, 11, &umr_bitfield_default },
+	 { "SISCL_COEF_RAM_FILTER_TYPE", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_COEF_RAM_TAP_DATA[] = {
+	 { "SISCL_COEF_RAM_EVEN_TAP_COEF", 0, 13, &umr_bitfield_default },
+	 { "SISCL_COEF_RAM_EVEN_TAP_COEF_EN", 15, 15, &umr_bitfield_default },
+	 { "SISCL_COEF_RAM_ODD_TAP_COEF", 16, 29, &umr_bitfield_default },
+	 { "SISCL_COEF_RAM_ODD_TAP_COEF_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_MODE[] = {
+	 { "SISCL_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_TAP_CONTROL[] = {
+	 { "SISCL_V_NUM_OF_TAPS_Y_RGB", 0, 3, &umr_bitfield_default },
+	 { "SISCL_V_NUM_OF_TAPS_CBCR", 4, 7, &umr_bitfield_default },
+	 { "SISCL_H_NUM_OF_TAPS_Y_RGB", 8, 11, &umr_bitfield_default },
+	 { "SISCL_H_NUM_OF_TAPS_CBCR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_DEST_SIZE[] = {
+	 { "SISCL_DEST_HEIGHT", 0, 14, &umr_bitfield_default },
+	 { "SISCL_DEST_WIDTH", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_HORZ_FILTER_SCALE_RATIO[] = {
+	 { "SISCL_H_SCALE_RATIO", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_HORZ_FILTER_INIT_Y_RGB[] = {
+	 { "SISCL_H_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default },
+	 { "SISCL_H_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_HORZ_FILTER_INIT_CBCR[] = {
+	 { "SISCL_H_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default },
+	 { "SISCL_H_INIT_INT_CBCR", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_VERT_FILTER_SCALE_RATIO[] = {
+	 { "SISCL_V_SCALE_RATIO", 0, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_VERT_FILTER_INIT_Y_RGB[] = {
+	 { "SISCL_V_INIT_FRAC_Y_RGB", 0, 23, &umr_bitfield_default },
+	 { "SISCL_V_INIT_INT_Y_RGB", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_VERT_FILTER_INIT_CBCR[] = {
+	 { "SISCL_V_INIT_FRAC_CBCR", 0, 23, &umr_bitfield_default },
+	 { "SISCL_V_INIT_INT_CBCR", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_ROUND_OFFSET[] = {
+	 { "SISCL_ROUND_OFFSET_Y_RGB", 0, 15, &umr_bitfield_default },
+	 { "SISCL_ROUND_OFFSET_CBCR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_CLAMP[] = {
+	 { "SISCL_CLAMP_UPPER_Y_RGB", 0, 7, &umr_bitfield_default },
+	 { "SISCL_CLAMP_LOWER_Y_RGB", 8, 15, &umr_bitfield_default },
+	 { "SISCL_CLAMP_UPPER_CBCR", 16, 23, &umr_bitfield_default },
+	 { "SISCL_CLAMP_LOWER_CBCR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_OVERFLOW_STATUS[] = {
+	 { "SISCL_DATA_OVERFLOW_FLAG", 0, 0, &umr_bitfield_default },
+	 { "SISCL_DATA_OVERFLOW_ACK", 8, 8, &umr_bitfield_default },
+	 { "SISCL_DATA_OVERFLOW_MASK", 12, 12, &umr_bitfield_default },
+	 { "SISCL_DATA_OVERFLOW_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "SISCL_DATA_OVERFLOW_INT_TYPE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_COEF_RAM_CONFLICT_STATUS[] = {
+	 { "SISCL_HOST_CONFLICT_FLAG", 0, 0, &umr_bitfield_default },
+	 { "SISCL_HOST_CONFLICT_ACK", 8, 8, &umr_bitfield_default },
+	 { "SISCL_HOST_CONFLICT_MASK", 12, 12, &umr_bitfield_default },
+	 { "SISCL_HOST_CONFLICT_INT_STATUS", 16, 16, &umr_bitfield_default },
+	 { "SISCL_HOST_CONFLICT_INT_TYPE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_OUTSIDE_PIX_STRATEGY[] = {
+	 { "SISCL_OUTSIDE_PIX_STRATEGY", 0, 0, &umr_bitfield_default },
+	 { "SISCL_BLACK_COLOR_B_CB", 8, 15, &umr_bitfield_default },
+	 { "SISCL_BLACK_COLOR_G_Y", 16, 23, &umr_bitfield_default },
+	 { "SISCL_BLACK_COLOR_R_CR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_TEST_CNTL[] = {
+	 { "SISCL_TEST_CRC_EN", 4, 4, &umr_bitfield_default },
+	 { "SISCL_TEST_CRC_CONT_EN", 8, 8, &umr_bitfield_default },
+	 { "SISCL_TEST_CRC_DE_ONLY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_TEST_CRC_RED[] = {
+	 { "SISCL_TEST_CRC_RED_MASK", 0, 15, &umr_bitfield_default },
+	 { "SISCL_TEST_CRC_SIG_RED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_TEST_CRC_GREEN[] = {
+	 { "SISCL_TEST_CRC_GREEN_MASK", 0, 15, &umr_bitfield_default },
+	 { "SISCL_TEST_CRC_SIG_GREEN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_TEST_CRC_BLUE[] = {
+	 { "SISCL_TEST_CRC_BLUE_MASK", 0, 15, &umr_bitfield_default },
+	 { "SISCL_TEST_CRC_SIG_BLUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_TEST_DEBUG_INDEX[] = {
+	 { "SISCL_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SISCL_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_TEST_DEBUG_DATA[] = {
+	 { "SISCL_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_BACKPRESSURE_CNT_EN[] = {
+	 { "SISCL_BACKPRESSURE_CNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSISCL_MCIF_BACKPRESSURE_CNT[] = {
+	 { "SISCL_MCIF_Y_MAX_BACKPRESSURE", 0, 15, &umr_bitfield_default },
+	 { "SISCL_MCIF_C_MAX_BACKPRESSURE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_N[] = {
+	 { "DP_AUX4_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_O[] = {
+	 { "DP_AUX4_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_P[] = {
+	 { "DP_AUX4_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[] = {
+	 { "STREAM_FORMATS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL5[] = {
+	 { "CRC_CHANNEL5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_STREAM_DEBUG[] = {
+	 { "STREAM_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR4[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG5[] = {
+	 { "DCIO_DEBUG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR05[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT05[] = {
+	 { "H_SYNC_END", 0, 4, &umr_bitfield_default },
+	 { "H_SYNC_SKEW", 5, 6, &umr_bitfield_default },
+	 { "H_BLANK_END_B5", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[] = {
+	 { "CLOCK_GATING_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "CLOCK_ON_STATE", 4, 4, &umr_bitfield_default },
+	 { "AUDIO_ENABLED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[] = {
+	 { "UNSOLICITED_RESPONSE_PAYLOAD", 0, 25, &umr_bitfield_default },
+	 { "UNSOLICITED_RESPONSE_FORCE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[] = {
+	 { "SEQUENCE", 0, 3, &umr_bitfield_default },
+	 { "DEFAULT_ASSOCIATION", 4, 7, &umr_bitfield_default },
+	 { "MISC", 8, 11, &umr_bitfield_default },
+	 { "COLOR", 12, 15, &umr_bitfield_default },
+	 { "CONNECTION_TYPE", 16, 19, &umr_bitfield_default },
+	 { "DEFAULT_DEVICE", 20, 23, &umr_bitfield_default },
+	 { "LOCATION", 24, 29, &umr_bitfield_default },
+	 { "PORT_CONNECTIVITY", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[] = {
+	 { "MULTICHANNEL1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MULTICHANNEL1_MUTE", 1, 1, &umr_bitfield_default },
+	 { "MULTICHANNEL1_CHANNEL_ID", 4, 7, &umr_bitfield_default },
+	 { "MULTICHANNEL3_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MULTICHANNEL3_MUTE", 9, 9, &umr_bitfield_default },
+	 { "MULTICHANNEL3_CHANNEL_ID", 12, 15, &umr_bitfield_default },
+	 { "MULTICHANNEL5_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "MULTICHANNEL5_MUTE", 17, 17, &umr_bitfield_default },
+	 { "MULTICHANNEL5_CHANNEL_ID", 20, 23, &umr_bitfield_default },
+	 { "MULTICHANNEL7_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTICHANNEL7_MUTE", 25, 25, &umr_bitfield_default },
+	 { "MULTICHANNEL7_CHANNEL_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[] = {
+	 { "MULTICHANNEL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[] = {
+	 { "IEC_60958_CS_MODE", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_SOURCE_NUMBER", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[] = {
+	 { "IEC_60958_CS_CLOCK_ACCURACY", 0, 1, &umr_bitfield_default },
+	 { "IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN", 2, 2, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH", 3, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_WORD_LENGTH_OVRRD_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY", 0, 5, &umr_bitfield_default },
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[] = {
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[] = {
+	 { "IEC_60958_CS_SAMPLING_FREQUENCY_COEFF", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_MPEG_SURROUND_INFO", 4, 4, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A", 5, 6, &umr_bitfield_default },
+	 { "IEC_60958_CS_CGMS_A_VALID", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_L", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_R", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_2", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_3", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[] = {
+	 { "AUDIO_RATE_CAPABILITIES", 0, 11, &umr_bitfield_default },
+	 { "AUDIO_BIT_CAPABILITIES", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[] = {
+	 { "OUTSTRMPAY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL6[] = {
+	 { "CRC_CHANNEL6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR5[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG6[] = {
+	 { "DCIO_DEBUG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR06[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT06[] = {
+	 { "V_TOTAL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_4", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_5", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[] = {
+	 { "IEC_60958_CS_CHANNEL_NUMBER_6", 0, 3, &umr_bitfield_default },
+	 { "IEC_60958_CS_CHANNEL_NUMBER_7", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[] = {
+	 { "ASSOCIATION_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[] = {
+	 { "OUTPUT_ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[] = {
+	 { "STRIPE_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "STRIPE_CAPABILITY", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_CRC0_CHANNEL7[] = {
+	 { "CRC_CHANNEL7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR6[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG7[] = {
+	 { "DCIO_DEBUG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR07[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT07[] = {
+	 { "V_TOTAL_B8", 0, 0, &umr_bitfield_default },
+	 { "V_DISP_END_B8", 1, 1, &umr_bitfield_default },
+	 { "V_SYNC_START_B8", 2, 2, &umr_bitfield_default },
+	 { "V_BLANK_START_B8", 3, 3, &umr_bitfield_default },
+	 { "LINE_CMP_B8", 4, 4, &umr_bitfield_default },
+	 { "V_TOTAL_B9", 5, 5, &umr_bitfield_default },
+	 { "V_DISP_END_B9", 6, 6, &umr_bitfield_default },
+	 { "V_SYNC_START_B9", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_A[] = {
+	 { "DP_AUX5_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_B[] = {
+	 { "DP_AUX5_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_C[] = {
+	 { "DP_AUX5_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_D[] = {
+	 { "DP_AUX5_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_E[] = {
+	 { "DP_AUX5_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_F[] = {
+	 { "DP_AUX5_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_G[] = {
+	 { "DP_AUX5_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_H[] = {
+	 { "DP_AUX5_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_I[] = {
+	 { "DP_AUX5_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_J[] = {
+	 { "DP_AUX5_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_K[] = {
+	 { "DP_AUX5_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_L[] = {
+	 { "DP_AUX5_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_M[] = {
+	 { "DP_AUX5_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_N[] = {
+	 { "DP_AUX5_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGADCC_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_O[] = {
+	 { "DP_AUX5_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[] = {
+	 { "RAMP_RATE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_CONTROL[] = {
+	 { "OUTPUT_STREAM_0_INTERRUPT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_1_INTERRUPT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_2_INTERRUPT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_3_INTERRUPT_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_4_INTERRUPT_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_5_INTERRUPT_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "CONTROLLER_INTERRUPT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GLOBAL_INTERRUPT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG8[] = {
+	 { "DCIO_DEBUG8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR08[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT08[] = {
+	 { "ROW_SCAN_START", 0, 4, &umr_bitfield_default },
+	 { "BYTE_PAN", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_A[] = {
+	 { "DP_AUX6_DEBUG_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWALL_CLOCK_COUNTER_ALIAS[] = {
+	 { "WALL_CLOCK_COUNTER_ALIAS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_B[] = {
+	 { "DP_AUX6_DEBUG_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_C[] = {
+	 { "DP_AUX6_DEBUG_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[] = {
+	 { "LINK_POSITION_IN_BUFFER_ALIAS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_D[] = {
+	 { "DP_AUX6_DEBUG_D", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_E[] = {
+	 { "DP_AUX6_DEBUG_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_F[] = {
+	 { "DP_AUX6_DEBUG_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_G[] = {
+	 { "DP_AUX6_DEBUG_G", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_H[] = {
+	 { "DP_AUX6_DEBUG_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_I[] = {
+	 { "DP_AUX6_DEBUG_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_J[] = {
+	 { "DP_AUX6_DEBUG_J", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_K[] = {
+	 { "DP_AUX6_DEBUG_K", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_L[] = {
+	 { "DP_AUX6_DEBUG_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_M[] = {
+	 { "DP_AUX6_DEBUG_M", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_N[] = {
+	 { "DP_AUX6_DEBUG_N", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_O[] = {
+	 { "DP_AUX6_DEBUG_O", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[] = {
+	 { "PRESENTATION_TIME_EMBEDDING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_OFFSET_CHANGED", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_GTC_COUNTER_MIN_MAX_DELTA", 2, 2, &umr_bitfield_default },
+	 { "PRESENTATION_TIME_EMBEDDING_GROUP", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF02_DBG_DCCIF_C[] = {
+	 { "DBG_DCCIF_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR8[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmINTERRUPT_STATUS[] = {
+	 { "OUTPUT_STREAM_0_INTERRUPT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_1_INTERRUPT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_2_INTERRUPT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_3_INTERRUPT_STATUS", 3, 3, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_4_INTERRUPT_STATUS", 4, 4, &umr_bitfield_default },
+	 { "OUTPUT_STREAM_5_INTERRUPT_STATUS", 5, 5, &umr_bitfield_default },
+	 { "CONTROLLER_INTERRUPT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GLOBAL_INTERRUPT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUG9[] = {
+	 { "DCIO_DEBUG9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR09[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT09[] = {
+	 { "MAX_ROW_SCAN", 0, 4, &umr_bitfield_default },
+	 { "V_BLANK_START_B9", 5, 5, &umr_bitfield_default },
+	 { "LINE_CMP_B9", 6, 6, &umr_bitfield_default },
+	 { "DOUBLE_CHAR_HEIGHT", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX1_DEBUG_Q[] = {
+	 { "DP_AUX1_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX2_DEBUG_Q[] = {
+	 { "DP_AUX2_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX3_DEBUG_Q[] = {
+	 { "DP_AUX3_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX4_DEBUG_Q[] = {
+	 { "DP_AUX4_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_P[] = {
+	 { "DP_AUX5_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX5_DEBUG_Q[] = {
+	 { "DP_AUX5_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_P[] = {
+	 { "DP_AUX6_DEBUG_P", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDP_AUX6_DEBUG_Q[] = {
+	 { "DP_AUX6_DEBUG_Q", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[] = {
+	 { "PRESENTATION_TIME_OFFSET_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMIF_DEBUG02_CORE1[] = {
+	 { "DB_DATA", 0, 15, &umr_bitfield_default },
+	 { "MC_RDRET_COUNT_EN", 16, 16, &umr_bitfield_default },
+	 { "MC_RDRET_COUNTER", 17, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR9[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGA[] = {
+	 { "DCIO_DEBUGA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0A[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0A[] = {
+	 { "CURSOR_START", 0, 4, &umr_bitfield_default },
+	 { "CURSOR_DISABLE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF04_DBG_DCCIF_E[] = {
+	 { "DBG_DCCIF_E", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR10[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION6[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGB[] = {
+	 { "DCIO_DEBUGB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0B[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0B[] = {
+	 { "CURSOR_END", 0, 4, &umr_bitfield_default },
+	 { "CURSOR_SKEW", 5, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[] = {
+	 { "GTC_COUNTER_DELTA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIDDCCIF05_DBG_DCCIF_F[] = {
+	 { "DBG_DCCIF_F", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWALL_CLOCK_COUNTER[] = {
+	 { "WALL_CLOCK_COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION7[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_12[] = {
+	 { "IDEC_MVP_DATA_A_H", 0, 0, &umr_bitfield_default },
+	 { "IDEC_MVP_DATA_A", 1, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGC[] = {
+	 { "DCIO_DEBUGC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0C[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0C[] = {
+	 { "DISP_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_RENDER_CONTROL[] = {
+	 { "VGA_BLINK_RATE", 0, 4, &umr_bitfield_default },
+	 { "VGA_BLINK_MODE", 5, 6, &umr_bitfield_default },
+	 { "VGA_CURSOR_BLINK_INVERT", 7, 7, &umr_bitfield_default },
+	 { "VGA_EXTD_ADDR_COUNT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_VSTATUS_CNTL", 16, 17, &umr_bitfield_default },
+	 { "VGA_LOCK_8DOT", 24, 24, &umr_bitfield_default },
+	 { "VGAREG_LINECMP_COMPATIBILITY_SEL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SEQUENCER_RESET_CONTROL[] = {
+	 { "D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 0, 0, &umr_bitfield_default },
+	 { "D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 1, 1, &umr_bitfield_default },
+	 { "D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 2, 2, &umr_bitfield_default },
+	 { "D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 3, 3, &umr_bitfield_default },
+	 { "D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 4, 4, &umr_bitfield_default },
+	 { "D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET", 5, 5, &umr_bitfield_default },
+	 { "D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 8, 8, &umr_bitfield_default },
+	 { "D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 9, 9, &umr_bitfield_default },
+	 { "D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 10, 10, &umr_bitfield_default },
+	 { "D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 11, 11, &umr_bitfield_default },
+	 { "D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 12, 12, &umr_bitfield_default },
+	 { "D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET", 13, 13, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT", 17, 17, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INDEX_SELECT", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MODE_CONTROL[] = {
+	 { "VGA_ATI_LINEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_LUT_PALETTE_UPDATE_MODE", 4, 5, &umr_bitfield_default },
+	 { "VGA_128K_APERTURE_PAGING", 8, 8, &umr_bitfield_default },
+	 { "VGA_TEXT_132_COLUMNS_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SURFACE_PITCH_SELECT[] = {
+	 { "VGA_SURFACE_PITCH_SELECT", 0, 1, &umr_bitfield_default },
+	 { "VGA_SURFACE_HEIGHT_SELECT", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_INDEX[] = {
+	 { "VGA_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "VGA_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF1_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF1_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_DEBUG_DATA[] = {
+	 { "VGA_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DISPBUF2_SURFACE_ADDR[] = {
+	 { "VGA_DISPBUF2_SURFACE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MEMORY_BASE_ADDRESS_HIGH[] = {
+	 { "VGA_MEMORY_BASE_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HDP_CONTROL[] = {
+	 { "VGA_MEM_PAGE_SELECT_EN", 0, 0, &umr_bitfield_default },
+	 { "VGA_MEMORY_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "VGA_RBBM_LOCK_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RESET_CONTROL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_CACHE_CONTROL[] = {
+	 { "VGA_WRITE_THROUGH_CACHE_DIS", 0, 0, &umr_bitfield_default },
+	 { "VGA_READ_CACHE_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "VGA_READ_BUFFER_INVALIDATE", 16, 16, &umr_bitfield_default },
+	 { "VGA_DCCIF_W256ONLY", 20, 20, &umr_bitfield_default },
+	 { "VGA_DCCIF_WC_TIMEOUT", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD1VGA_CONTROL[] = {
+	 { "D1VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D1VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D1VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D1VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D1VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD2VGA_CONTROL[] = {
+	 { "D2VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D2VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D2VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D2VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D2VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_HW_DEBUG[] = {
+	 { "VGA_HW_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[] = {
+	 { "GTC_COUNTER_DELTA_MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR12[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION8[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_13[] = {
+	 { "IDED_MVP_DATA_B_H", 0, 0, &umr_bitfield_default },
+	 { "IDED_MVP_DATA_B", 1, 24, &umr_bitfield_default },
+	 { "IDED_START_READ_B", 25, 25, &umr_bitfield_default },
+	 { "IDED_READ_FIFO_ENTRY_DE_B", 26, 26, &umr_bitfield_default },
+	 { "IDED_WRITE_ADD_B", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGD[] = {
+	 { "DCIO_DEBUGD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0D[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0D[] = {
+	 { "DISP_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS[] = {
+	 { "VGA_MEM_ACCESS_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_STATUS", 1, 1, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_CONTROL[] = {
+	 { "VGA_MEM_ACCESS_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_MASK", 8, 8, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_MASK", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_MASK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_STATUS_CLEAR[] = {
+	 { "VGA_MEM_ACCESS_INT_CLEAR", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_CLEAR", 8, 8, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_CLEAR", 16, 16, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_CLEAR", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_INTERRUPT_STATUS[] = {
+	 { "VGA_MEM_ACCESS_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VGA_REG_ACCESS_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "VGA_DISPLAY_SWITCH_INT_STATUS", 2, 2, &umr_bitfield_default },
+	 { "VGA_MODE_AUTO_TRIGGER_INT_STATUS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_MAIN_CONTROL[] = {
+	 { "VGA_CRTC_TIMEOUT", 0, 1, &umr_bitfield_default },
+	 { "VGA_RENDER_TIMEOUT_COUNT", 3, 4, &umr_bitfield_default },
+	 { "VGA_VIRTUAL_VERTICAL_RETRACE_DURATION", 5, 7, &umr_bitfield_default },
+	 { "VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT", 8, 9, &umr_bitfield_default },
+	 { "VGA_READBACK_NO_DISPLAY_SOURCE_SELECT", 16, 17, &umr_bitfield_default },
+	 { "VGA_READBACK_CRT_INTR_SOURCE_SELECT", 24, 25, &umr_bitfield_default },
+	 { "VGA_READBACK_SENSE_SWITCH_SELECT", 26, 26, &umr_bitfield_default },
+	 { "VGA_READ_URGENT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "VGA_WRITES_URGENT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "VGA_EXTERNAL_DAC_SENSE", 29, 29, &umr_bitfield_default },
+	 { "VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_TEST_CONTROL[] = {
+	 { "VGA_TEST_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_START", 8, 8, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DONE", 16, 16, &umr_bitfield_default },
+	 { "VGA_TEST_RENDER_DISPBUF_SELECT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_INDEX[] = {
+	 { "VGA_DEBUG_READBACK_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_DEBUG_READBACK_DATA[] = {
+	 { "VGA_DEBUG_READBACK_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_REF_DIV[] = {
+	 { "VGA25_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_REF_DIV[] = {
+	 { "VGA28_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_REF_DIV[] = {
+	 { "VGA41_PPLL_REF_DIV", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_FB_DIV[] = {
+	 { "VGA25_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA25_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA25_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_FB_DIV[] = {
+	 { "VGA28_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA28_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA28_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_FB_DIV[] = {
+	 { "VGA41_PPLL_FB_DIV_FRACTION", 0, 3, &umr_bitfield_default },
+	 { "VGA41_PPLL_FB_DIV_FRACTION_CNTL", 4, 5, &umr_bitfield_default },
+	 { "VGA41_PPLL_FB_DIV", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[] = {
+	 { "GTC_COUNTER_DELTA_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSTREAM_SYNCHRONIZATION[] = {
+	 { "STREAM_0_SYNCHRONIZATION", 0, 0, &umr_bitfield_default },
+	 { "STREAM_1_SYNCHRONIZATION", 1, 1, &umr_bitfield_default },
+	 { "STREAM_2_SYNCHRONIZATION", 2, 2, &umr_bitfield_default },
+	 { "STREAM_3_SYNCHRONIZATION", 3, 3, &umr_bitfield_default },
+	 { "STREAM_4_SYNCHRONIZATION", 4, 4, &umr_bitfield_default },
+	 { "STREAM_5_SYNCHRONIZATION", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAUDIO_DESCRIPTOR13[] = {
+	 { "MAX_CHANNELS", 0, 2, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES", 8, 15, &umr_bitfield_default },
+	 { "DESCRIPTOR_BYTE_2", 16, 23, &umr_bitfield_default },
+	 { "SUPPORTED_FREQUENCIES_STEREO", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION9[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_14[] = {
+	 { "IDEE_READ_ADD", 0, 2, &umr_bitfield_default },
+	 { "IDEE_WRITE_ADD_A", 3, 5, &umr_bitfield_default },
+	 { "IDEE_WRITE_ADD_B", 6, 8, &umr_bitfield_default },
+	 { "IDEE_START_READ", 9, 9, &umr_bitfield_default },
+	 { "IDEE_START_READ_B", 10, 10, &umr_bitfield_default },
+	 { "IDEE_START_INCR_WR_A", 11, 11, &umr_bitfield_default },
+	 { "IDEE_START_INCR_WR_B", 12, 12, &umr_bitfield_default },
+	 { "IDEE_WRITE2FIFO", 13, 13, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENTRY_DE", 14, 14, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENTRY_DE_B", 15, 15, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_DE", 16, 16, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_DE_B", 17, 17, &umr_bitfield_default },
+	 { "IDEE_READ_FIFO_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "IDEE_CRTC1_CNTL_CAPTURE_START_A", 19, 19, &umr_bitfield_default },
+	 { "IDEE_CRC_PHASE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGE[] = {
+	 { "DCIO_DIGA_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0E[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0E[] = {
+	 { "CURSOR_LOC_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_POST_DIV[] = {
+	 { "VGA25_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA25_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA25_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_POST_DIV[] = {
+	 { "VGA28_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA28_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA28_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_POST_DIV[] = {
+	 { "VGA41_PPLL_POST_DIV_PIXCLK", 0, 6, &umr_bitfield_default },
+	 { "VGA41_PPLL_POST_DIV_DVOCLK", 8, 14, &umr_bitfield_default },
+	 { "VGA41_PPLL_POST_DIV_IDCLK", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA25_PPLL_ANALOG[] = {
+	 { "VGA25_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA25_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA25_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA25_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA25_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA28_PPLL_ANALOG[] = {
+	 { "VGA28_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA28_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA28_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA28_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA28_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA41_PPLL_ANALOG[] = {
+	 { "VGA41_CAL_MODE", 0, 4, &umr_bitfield_default },
+	 { "VGA41_PPLL_PFD_PULSE_SEL", 5, 6, &umr_bitfield_default },
+	 { "VGA41_PPLL_CP", 8, 11, &umr_bitfield_default },
+	 { "VGA41_PPLL_LF_MODE", 12, 20, &umr_bitfield_default },
+	 { "VGA41_PPLL_IBIAS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_DATA[] = {
+	 { "VCRTC_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCRTC8_IDX[] = {
+	 { "VCRTC_IDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_WT[] = {
+	 { "VSYNC_SEL_W", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENS1[] = {
+	 { "NO_DISPLAY", 0, 0, &umr_bitfield_default },
+	 { "VGA_VSTATUS", 3, 3, &umr_bitfield_default },
+	 { "PIXEL_READ_BACK", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSINK_DESCRIPTION10[] = {
+	 { "DESCRIPTION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMVP_DEBUG_15[] = {
+	 { "IDEF_MVP_ASYNC_FIFO_WEN", 0, 0, &umr_bitfield_default },
+	 { "IDEF_MVP_ASYNC_FIFO_WDATA", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDCIO_DEBUGF[] = {
+	 { "DCIO_DIGB_DEBUG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixATTR0F[] = {
+	 { "ATTR_PAL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCRT0F[] = {
+	 { "CURSOR_LOC_LO", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_WT[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENENB[] = {
+	 { "BLK_IO_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENS0[] = {
+	 { "SENSE_SWITCH", 4, 4, &umr_bitfield_default },
+	 { "CRT_INTR", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[] = {
+	 { "AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_R_INDEX[] = {
+	 { "DAC_R_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEQ8_DATA[] = {
+	 { "SEQ_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_MASK[] = {
+	 { "DAC_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDAC_W_INDEX[] = {
+	 { "DAC_W_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENFC_RD[] = {
+	 { "VSYNC_SEL_R", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH8_DATA[] = {
+	 { "GRPH_DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRPH8_IDX[] = {
+	 { "GRPH_IDX", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGENMO_RD[] = {
+	 { "GENMO_MONO_ADDRESS_B", 0, 0, &umr_bitfield_default },
+	 { "VGA_RAM_EN", 1, 1, &umr_bitfield_default },
+	 { "VGA_CKSEL", 2, 3, &umr_bitfield_default },
+	 { "ODD_EVEN_MD_PGSEL", 5, 5, &umr_bitfield_default },
+	 { "VGA_HSYNC_POL", 6, 6, &umr_bitfield_default },
+	 { "VGA_VSYNC_POL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD3VGA_CONTROL[] = {
+	 { "D3VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D3VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D3VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D3VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D3VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD4VGA_CONTROL[] = {
+	 { "D4VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D4VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D4VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D4VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D4VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD5VGA_CONTROL[] = {
+	 { "D5VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D5VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D5VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D5VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D5VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmD6VGA_CONTROL[] = {
+	 { "D6VGA_MODE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "D6VGA_TIMING_SELECT", 8, 8, &umr_bitfield_default },
+	 { "D6VGA_SYNC_POLARITY_SELECT", 9, 9, &umr_bitfield_default },
+	 { "D6VGA_OVERSCAN_COLOR_EN", 16, 16, &umr_bitfield_default },
+	 { "D6VGA_ROTATE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGA_SOURCE_SELECT[] = {
+	 { "VGA_SOURCE_SEL_A", 0, 2, &umr_bitfield_default },
+	 { "VGA_SOURCE_SEL_B", 8, 10, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/dce80_regs.i b/src/lib/ip/dce80_regs.i
new file mode 100644
index 0000000..b9d030b
--- /dev/null
+++ b/src/lib/ip/dce80_regs.i
@@ -0,0 +1,5641 @@
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID", REG_SMC, 0x0, &ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG", REG_SMC, 0x0, &ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_FIFO_SIZE_CONTROL", REG_SMC, 0x0, &ixAZALIA_FIFO_SIZE_CONTROL[0], sizeof(ixAZALIA_FIFO_SIZE_CONTROL)/sizeof(ixAZALIA_FIFO_SIZE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL0", REG_SMC, 0x0, &ixAZALIA_CRC0_CHANNEL0[0], sizeof(ixAZALIA_CRC0_CHANNEL0)/sizeof(ixAZALIA_CRC0_CHANNEL0[0]), 0, 0 },
+	{ "mmGLOBAL_CAPABILITIES", REG_MMIO, 0x0, &mmGLOBAL_CAPABILITIES[0], sizeof(mmGLOBAL_CAPABILITIES)/sizeof(mmGLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "ixDCIO_DEBUG_ID", REG_SMC, 0x0, &ixDCIO_DEBUG_ID[0], sizeof(ixDCIO_DEBUG_ID)/sizeof(ixDCIO_DEBUG_ID[0]), 0, 0 },
+	{ "ixFMT_DEBUG_ID", REG_SMC, 0x0, &ixFMT_DEBUG_ID[0], sizeof(ixFMT_DEBUG_ID)/sizeof(ixFMT_DEBUG_ID[0]), 0, 0 },
+	{ "ixATTR00", REG_SMC, 0x0, &ixATTR00[0], sizeof(ixATTR00)/sizeof(ixATTR00[0]), 0, 0 },
+	{ "ixSEQ00", REG_SMC, 0x0, &ixSEQ00[0], sizeof(ixSEQ00)/sizeof(ixSEQ00[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x1, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID", REG_SMC, 0x1, &ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID[0]), 0, 0 },
+	{ "ixAZALIA_LATENCY_COUNTER_CONTROL", REG_SMC, 0x1, &ixAZALIA_LATENCY_COUNTER_CONTROL[0], sizeof(ixAZALIA_LATENCY_COUNTER_CONTROL)/sizeof(ixAZALIA_LATENCY_COUNTER_CONTROL[0]), 0, 0 },
+	{ "mmOUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x1, &mmOUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmOUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmOUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmINPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x1, &mmINPUT_PAYLOAD_CAPABILITY[0], sizeof(mmINPUT_PAYLOAD_CAPABILITY)/sizeof(mmINPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL1", REG_SMC, 0x1, &ixAZALIA_CRC0_CHANNEL1[0], sizeof(ixAZALIA_CRC0_CHANNEL1)/sizeof(ixAZALIA_CRC0_CHANNEL1[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR0", REG_SMC, 0x1, &ixAUDIO_DESCRIPTOR0[0], sizeof(ixAUDIO_DESCRIPTOR0)/sizeof(ixAUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "ixDCIO_DEBUG1", REG_SMC, 0x1, &ixDCIO_DEBUG1[0], sizeof(ixDCIO_DEBUG1)/sizeof(ixDCIO_DEBUG1[0]), 0, 0 },
+	{ "ixFMT_DEBUG0", REG_SMC, 0x1, &ixFMT_DEBUG0[0], sizeof(ixFMT_DEBUG0)/sizeof(ixFMT_DEBUG0[0]), 0, 0 },
+	{ "ixATTR01", REG_SMC, 0x1, &ixATTR01[0], sizeof(ixATTR01)/sizeof(ixATTR01[0]), 0, 0 },
+	{ "ixSEQ01", REG_SMC, 0x1, &ixSEQ01[0], sizeof(ixSEQ01)/sizeof(ixSEQ01[0]), 0, 0 },
+	{ "mmCORB_LOWER_BASE_ADDRESS", REG_MMIO, 0x10, &mmCORB_LOWER_BASE_ADDRESS[0], sizeof(mmCORB_LOWER_BASE_ADDRESS)/sizeof(mmCORB_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION11", REG_SMC, 0x10, &ixSINK_DESCRIPTION11[0], sizeof(ixSINK_DESCRIPTION11)/sizeof(ixSINK_DESCRIPTION11[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_A", REG_SMC, 0x10, &ixDP_AUX1_DEBUG_A[0], sizeof(ixDP_AUX1_DEBUG_A)/sizeof(ixDP_AUX1_DEBUG_A[0]), 0, 0 },
+	{ "ixDCIO_DEBUG10", REG_SMC, 0x10, &ixDCIO_DEBUG10[0], sizeof(ixDCIO_DEBUG10)/sizeof(ixDCIO_DEBUG10[0]), 0, 0 },
+	{ "ixATTR10", REG_SMC, 0x10, &ixATTR10[0], sizeof(ixATTR10)/sizeof(ixATTR10[0]), 0, 0 },
+	{ "ixCRT10", REG_SMC, 0x10, &ixCRT10[0], sizeof(ixCRT10)/sizeof(ixCRT10[0]), 0, 0 },
+	{ "mmCORB_UPPER_BASE_ADDRESS", REG_MMIO, 0x11, &mmCORB_UPPER_BASE_ADDRESS[0], sizeof(mmCORB_UPPER_BASE_ADDRESS)/sizeof(mmCORB_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION12", REG_SMC, 0x11, &ixSINK_DESCRIPTION12[0], sizeof(ixSINK_DESCRIPTION12)/sizeof(ixSINK_DESCRIPTION12[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_B", REG_SMC, 0x11, &ixDP_AUX1_DEBUG_B[0], sizeof(ixDP_AUX1_DEBUG_B)/sizeof(ixDP_AUX1_DEBUG_B[0]), 0, 0 },
+	{ "ixDCIO_DEBUG11", REG_SMC, 0x11, &ixDCIO_DEBUG11[0], sizeof(ixDCIO_DEBUG11)/sizeof(ixDCIO_DEBUG11[0]), 0, 0 },
+	{ "ixATTR11", REG_SMC, 0x11, &ixATTR11[0], sizeof(ixATTR11)/sizeof(ixATTR11[0]), 0, 0 },
+	{ "ixCRT11", REG_SMC, 0x11, &ixCRT11[0], sizeof(ixCRT11)/sizeof(ixCRT11[0]), 0, 0 },
+	{ "mmDCCG_DS_DEBUG_CNTL", REG_MMIO, 0x112, &mmDCCG_DS_DEBUG_CNTL[0], sizeof(mmDCCG_DS_DEBUG_CNTL)/sizeof(mmDCCG_DS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DS_DTO_INCR", REG_MMIO, 0x113, &mmDCCG_DS_DTO_INCR[0], sizeof(mmDCCG_DS_DTO_INCR)/sizeof(mmDCCG_DS_DTO_INCR[0]), 0, 0 },
+	{ "mmDCCG_DS_DTO_MODULO", REG_MMIO, 0x114, &mmDCCG_DS_DTO_MODULO[0], sizeof(mmDCCG_DS_DTO_MODULO)/sizeof(mmDCCG_DS_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_DS_CNTL", REG_MMIO, 0x115, &mmDCCG_DS_CNTL[0], sizeof(mmDCCG_DS_CNTL)/sizeof(mmDCCG_DS_CNTL[0]), 0, 0 },
+	{ "mmDCCG_DS_HW_CAL_INTERVAL", REG_MMIO, 0x116, &mmDCCG_DS_HW_CAL_INTERVAL[0], sizeof(mmDCCG_DS_HW_CAL_INTERVAL)/sizeof(mmDCCG_DS_HW_CAL_INTERVAL[0]), 0, 0 },
+	{ "mmSYMCLKG_CLOCK_ENABLE", REG_MMIO, 0x117, &mmSYMCLKG_CLOCK_ENABLE[0], sizeof(mmSYMCLKG_CLOCK_ENABLE)/sizeof(mmSYMCLKG_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDPREFCLK_CNTL", REG_MMIO, 0x118, &mmDPREFCLK_CNTL[0], sizeof(mmDPREFCLK_CNTL)/sizeof(mmDPREFCLK_CNTL[0]), 0, 0 },
+	{ "mmSCANIN_SOFT_RESET", REG_MMIO, 0x11e, &mmSCANIN_SOFT_RESET[0], sizeof(mmSCANIN_SOFT_RESET)/sizeof(mmSCANIN_SOFT_RESET[0]), 0, 0 },
+	{ "mmVGA_MEM_WRITE_PAGE_ADDR", REG_MMIO, 0x12, &mmVGA_MEM_WRITE_PAGE_ADDR[0], sizeof(mmVGA_MEM_WRITE_PAGE_ADDR)/sizeof(mmVGA_MEM_WRITE_PAGE_ADDR[0]), 0, 0 },
+	{ "mmCORB_WRITE_POINTER", REG_MMIO, 0x12, &mmCORB_WRITE_POINTER[0], sizeof(mmCORB_WRITE_POINTER)/sizeof(mmCORB_WRITE_POINTER[0]), 0, 0 },
+	{ "mmCORB_READ_POINTER", REG_MMIO, 0x12, &mmCORB_READ_POINTER[0], sizeof(mmCORB_READ_POINTER)/sizeof(mmCORB_READ_POINTER[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_C", REG_SMC, 0x12, &ixDP_AUX1_DEBUG_C[0], sizeof(ixDP_AUX1_DEBUG_C)/sizeof(ixDP_AUX1_DEBUG_C[0]), 0, 0 },
+	{ "ixDCIO_DEBUG12", REG_SMC, 0x12, &ixDCIO_DEBUG12[0], sizeof(ixDCIO_DEBUG12)/sizeof(ixDCIO_DEBUG12[0]), 0, 0 },
+	{ "ixATTR12", REG_SMC, 0x12, &ixATTR12[0], sizeof(ixATTR12)/sizeof(ixATTR12[0]), 0, 0 },
+	{ "ixCRT12", REG_SMC, 0x12, &ixCRT12[0], sizeof(ixCRT12)/sizeof(ixCRT12[0]), 0, 0 },
+	{ "mmDCCG_GTC_CNTL", REG_MMIO, 0x120, &mmDCCG_GTC_CNTL[0], sizeof(mmDCCG_GTC_CNTL)/sizeof(mmDCCG_GTC_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_INCR", REG_MMIO, 0x121, &mmDCCG_GTC_DTO_INCR[0], sizeof(mmDCCG_GTC_DTO_INCR)/sizeof(mmDCCG_GTC_DTO_INCR[0]), 0, 0 },
+	{ "mmDCCG_GTC_DTO_MODULO", REG_MMIO, 0x122, &mmDCCG_GTC_DTO_MODULO[0], sizeof(mmDCCG_GTC_DTO_MODULO)/sizeof(mmDCCG_GTC_DTO_MODULO[0]), 0, 0 },
+	{ "mmDCCG_GTC_CURRENT", REG_MMIO, 0x123, &mmDCCG_GTC_CURRENT[0], sizeof(mmDCCG_GTC_CURRENT)/sizeof(mmDCCG_GTC_CURRENT[0]), 0, 0 },
+	{ "mmDENTIST_DISPCLK_CNTL", REG_MMIO, 0x124, &mmDENTIST_DISPCLK_CNTL[0], sizeof(mmDENTIST_DISPCLK_CNTL)/sizeof(mmDENTIST_DISPCLK_CNTL[0]), 0, 0 },
+	{ "mmDAC_CLK_ENABLE", REG_MMIO, 0x128, &mmDAC_CLK_ENABLE[0], sizeof(mmDAC_CLK_ENABLE)/sizeof(mmDAC_CLK_ENABLE[0]), 0, 0 },
+	{ "mmDVO_CLK_ENABLE", REG_MMIO, 0x129, &mmDVO_CLK_ENABLE[0], sizeof(mmDVO_CLK_ENABLE)/sizeof(mmDVO_CLK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_SMU_INTERRUPT_CNTL", REG_MMIO, 0x12c, &mmDMCU_SMU_INTERRUPT_CNTL[0], sizeof(mmDMCU_SMU_INTERRUPT_CNTL)/sizeof(mmDMCU_SMU_INTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmSMU_CONTROL", REG_MMIO, 0x12d, &mmSMU_CONTROL[0], sizeof(mmSMU_CONTROL)/sizeof(mmSMU_CONTROL[0]), 0, 0 },
+	{ "mmSMU_INTERRUPT_CONTROL", REG_MMIO, 0x12e, &mmSMU_INTERRUPT_CONTROL[0], sizeof(mmSMU_INTERRUPT_CONTROL)/sizeof(mmSMU_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmVGA_MEM_READ_PAGE_ADDR", REG_MMIO, 0x13, &mmVGA_MEM_READ_PAGE_ADDR[0], sizeof(mmVGA_MEM_READ_PAGE_ADDR)/sizeof(mmVGA_MEM_READ_PAGE_ADDR[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION14", REG_SMC, 0x13, &ixSINK_DESCRIPTION14[0], sizeof(ixSINK_DESCRIPTION14)/sizeof(ixSINK_DESCRIPTION14[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_D", REG_SMC, 0x13, &ixDP_AUX1_DEBUG_D[0], sizeof(ixDP_AUX1_DEBUG_D)/sizeof(ixDP_AUX1_DEBUG_D[0]), 0, 0 },
+	{ "ixDCIO_DEBUG13", REG_SMC, 0x13, &ixDCIO_DEBUG13[0], sizeof(ixDCIO_DEBUG13)/sizeof(ixDCIO_DEBUG13[0]), 0, 0 },
+	{ "mmCORB_STATUS", REG_MMIO, 0x13, &mmCORB_STATUS[0], sizeof(mmCORB_STATUS)/sizeof(mmCORB_STATUS[0]), 0, 0 },
+	{ "mmCORB_SIZE", REG_MMIO, 0x13, &mmCORB_SIZE[0], sizeof(mmCORB_SIZE)/sizeof(mmCORB_SIZE[0]), 0, 0 },
+	{ "ixATTR13", REG_SMC, 0x13, &ixATTR13[0], sizeof(ixATTR13)/sizeof(ixATTR13[0]), 0, 0 },
+	{ "ixCRT13", REG_SMC, 0x13, &ixCRT13[0], sizeof(ixCRT13)/sizeof(ixCRT13[0]), 0, 0 },
+	{ "mmMILLISECOND_TIME_BASE_DIV", REG_MMIO, 0x130, &mmMILLISECOND_TIME_BASE_DIV[0], sizeof(mmMILLISECOND_TIME_BASE_DIV)/sizeof(mmMILLISECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDISPCLK_FREQ_CHANGE_CNTL", REG_MMIO, 0x131, &mmDISPCLK_FREQ_CHANGE_CNTL[0], sizeof(mmDISPCLK_FREQ_CHANGE_CNTL)/sizeof(mmDISPCLK_FREQ_CHANGE_CNTL[0]), 0, 0 },
+	{ "mmLIGHT_SLEEP_CNTL", REG_MMIO, 0x132, &mmLIGHT_SLEEP_CNTL[0], sizeof(mmLIGHT_SLEEP_CNTL)/sizeof(mmLIGHT_SLEEP_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PERFMON_CNTL", REG_MMIO, 0x133, &mmDCCG_PERFMON_CNTL[0], sizeof(mmDCCG_PERFMON_CNTL)/sizeof(mmDCCG_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmDCCG_GATE_DISABLE_CNTL", REG_MMIO, 0x134, &mmDCCG_GATE_DISABLE_CNTL[0], sizeof(mmDCCG_GATE_DISABLE_CNTL)/sizeof(mmDCCG_GATE_DISABLE_CNTL[0]), 0, 0 },
+	{ "mmDISPCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x135, &mmDISPCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG)/sizeof(mmDISPCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmSCLK_CGTT_BLK_CTRL_REG", REG_MMIO, 0x136, &mmSCLK_CGTT_BLK_CTRL_REG[0], sizeof(mmSCLK_CGTT_BLK_CTRL_REG)/sizeof(mmSCLK_CGTT_BLK_CTRL_REG[0]), 0, 0 },
+	{ "mmDCCG_CAC_STATUS", REG_MMIO, 0x137, &mmDCCG_CAC_STATUS[0], sizeof(mmDCCG_CAC_STATUS)/sizeof(mmDCCG_CAC_STATUS[0]), 0, 0 },
+	{ "mmPIXCLK1_RESYNC_CNTL", REG_MMIO, 0x138, &mmPIXCLK1_RESYNC_CNTL[0], sizeof(mmPIXCLK1_RESYNC_CNTL)/sizeof(mmPIXCLK1_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPIXCLK2_RESYNC_CNTL", REG_MMIO, 0x139, &mmPIXCLK2_RESYNC_CNTL[0], sizeof(mmPIXCLK2_RESYNC_CNTL)/sizeof(mmPIXCLK2_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmPIXCLK0_RESYNC_CNTL", REG_MMIO, 0x13a, &mmPIXCLK0_RESYNC_CNTL[0], sizeof(mmPIXCLK0_RESYNC_CNTL)/sizeof(mmPIXCLK0_RESYNC_CNTL[0]), 0, 0 },
+	{ "mmMICROSECOND_TIME_BASE_DIV", REG_MMIO, 0x13b, &mmMICROSECOND_TIME_BASE_DIV[0], sizeof(mmMICROSECOND_TIME_BASE_DIV)/sizeof(mmMICROSECOND_TIME_BASE_DIV[0]), 0, 0 },
+	{ "mmDISPPLL_BG_CNTL", REG_MMIO, 0x13c, &mmDISPPLL_BG_CNTL[0], sizeof(mmDISPPLL_BG_CNTL)/sizeof(mmDISPPLL_BG_CNTL[0]), 0, 0 },
+	{ "mmDIG_SOFT_RESET", REG_MMIO, 0x13d, &mmDIG_SOFT_RESET[0], sizeof(mmDIG_SOFT_RESET)/sizeof(mmDIG_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCCG_DISP_CNTL_REG", REG_MMIO, 0x13f, &mmDCCG_DISP_CNTL_REG[0], sizeof(mmDCCG_DISP_CNTL_REG)/sizeof(mmDCCG_DISP_CNTL_REG[0]), 0, 0 },
+	{ "mmRIRB_LOWER_BASE_ADDRESS", REG_MMIO, 0x14, &mmRIRB_LOWER_BASE_ADDRESS[0], sizeof(mmRIRB_LOWER_BASE_ADDRESS)/sizeof(mmRIRB_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION15", REG_SMC, 0x14, &ixSINK_DESCRIPTION15[0], sizeof(ixSINK_DESCRIPTION15)/sizeof(ixSINK_DESCRIPTION15[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_E", REG_SMC, 0x14, &ixDP_AUX1_DEBUG_E[0], sizeof(ixDP_AUX1_DEBUG_E)/sizeof(ixDP_AUX1_DEBUG_E[0]), 0, 0 },
+	{ "ixDCIO_DEBUG14", REG_SMC, 0x14, &ixDCIO_DEBUG14[0], sizeof(ixDCIO_DEBUG14)/sizeof(ixDCIO_DEBUG14[0]), 0, 0 },
+	{ "ixATTR14", REG_SMC, 0x14, &ixATTR14[0], sizeof(ixATTR14)/sizeof(ixATTR14[0]), 0, 0 },
+	{ "ixCRT14", REG_SMC, 0x14, &ixCRT14[0], sizeof(ixCRT14)/sizeof(ixCRT14[0]), 0, 0 },
+	{ "mmCRTC0_PIXEL_RATE_CNTL", REG_MMIO, 0x140, &mmCRTC0_PIXEL_RATE_CNTL[0], sizeof(mmCRTC0_PIXEL_RATE_CNTL)/sizeof(mmCRTC0_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO0_PHASE", REG_MMIO, 0x141, &mmDP_DTO0_PHASE[0], sizeof(mmDP_DTO0_PHASE)/sizeof(mmDP_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO0_MODULO", REG_MMIO, 0x142, &mmDP_DTO0_MODULO[0], sizeof(mmDP_DTO0_MODULO)/sizeof(mmDP_DTO0_MODULO[0]), 0, 0 },
+	{ "mmCRTC1_PIXEL_RATE_CNTL", REG_MMIO, 0x144, &mmCRTC1_PIXEL_RATE_CNTL[0], sizeof(mmCRTC1_PIXEL_RATE_CNTL)/sizeof(mmCRTC1_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO1_PHASE", REG_MMIO, 0x145, &mmDP_DTO1_PHASE[0], sizeof(mmDP_DTO1_PHASE)/sizeof(mmDP_DTO1_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO1_MODULO", REG_MMIO, 0x146, &mmDP_DTO1_MODULO[0], sizeof(mmDP_DTO1_MODULO)/sizeof(mmDP_DTO1_MODULO[0]), 0, 0 },
+	{ "mmCRTC2_PIXEL_RATE_CNTL", REG_MMIO, 0x148, &mmCRTC2_PIXEL_RATE_CNTL[0], sizeof(mmCRTC2_PIXEL_RATE_CNTL)/sizeof(mmCRTC2_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO2_PHASE", REG_MMIO, 0x149, &mmDP_DTO2_PHASE[0], sizeof(mmDP_DTO2_PHASE)/sizeof(mmDP_DTO2_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO2_MODULO", REG_MMIO, 0x14a, &mmDP_DTO2_MODULO[0], sizeof(mmDP_DTO2_MODULO)/sizeof(mmDP_DTO2_MODULO[0]), 0, 0 },
+	{ "mmCRTC3_PIXEL_RATE_CNTL", REG_MMIO, 0x14c, &mmCRTC3_PIXEL_RATE_CNTL[0], sizeof(mmCRTC3_PIXEL_RATE_CNTL)/sizeof(mmCRTC3_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO3_PHASE", REG_MMIO, 0x14d, &mmDP_DTO3_PHASE[0], sizeof(mmDP_DTO3_PHASE)/sizeof(mmDP_DTO3_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO3_MODULO", REG_MMIO, 0x14e, &mmDP_DTO3_MODULO[0], sizeof(mmDP_DTO3_MODULO)/sizeof(mmDP_DTO3_MODULO[0]), 0, 0 },
+	{ "mmRIRB_UPPER_BASE_ADDRESS", REG_MMIO, 0x15, &mmRIRB_UPPER_BASE_ADDRESS[0], sizeof(mmRIRB_UPPER_BASE_ADDRESS)/sizeof(mmRIRB_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION16", REG_SMC, 0x15, &ixSINK_DESCRIPTION16[0], sizeof(ixSINK_DESCRIPTION16)/sizeof(ixSINK_DESCRIPTION16[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_F", REG_SMC, 0x15, &ixDP_AUX1_DEBUG_F[0], sizeof(ixDP_AUX1_DEBUG_F)/sizeof(ixDP_AUX1_DEBUG_F[0]), 0, 0 },
+	{ "ixDCIO_DEBUG15", REG_SMC, 0x15, &ixDCIO_DEBUG15[0], sizeof(ixDCIO_DEBUG15)/sizeof(ixDCIO_DEBUG15[0]), 0, 0 },
+	{ "ixCRT15", REG_SMC, 0x15, &ixCRT15[0], sizeof(ixCRT15)/sizeof(ixCRT15[0]), 0, 0 },
+	{ "mmCRTC4_PIXEL_RATE_CNTL", REG_MMIO, 0x150, &mmCRTC4_PIXEL_RATE_CNTL[0], sizeof(mmCRTC4_PIXEL_RATE_CNTL)/sizeof(mmCRTC4_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO4_PHASE", REG_MMIO, 0x151, &mmDP_DTO4_PHASE[0], sizeof(mmDP_DTO4_PHASE)/sizeof(mmDP_DTO4_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO4_MODULO", REG_MMIO, 0x152, &mmDP_DTO4_MODULO[0], sizeof(mmDP_DTO4_MODULO)/sizeof(mmDP_DTO4_MODULO[0]), 0, 0 },
+	{ "mmCRTC5_PIXEL_RATE_CNTL", REG_MMIO, 0x154, &mmCRTC5_PIXEL_RATE_CNTL[0], sizeof(mmCRTC5_PIXEL_RATE_CNTL)/sizeof(mmCRTC5_PIXEL_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP_DTO5_PHASE", REG_MMIO, 0x155, &mmDP_DTO5_PHASE[0], sizeof(mmDP_DTO5_PHASE)/sizeof(mmDP_DTO5_PHASE[0]), 0, 0 },
+	{ "mmDP_DTO5_MODULO", REG_MMIO, 0x156, &mmDP_DTO5_MODULO[0], sizeof(mmDP_DTO5_MODULO)/sizeof(mmDP_DTO5_MODULO[0]), 0, 0 },
+	{ "mmDCFE0_SOFT_RESET", REG_MMIO, 0x158, &mmDCFE0_SOFT_RESET[0], sizeof(mmDCFE0_SOFT_RESET)/sizeof(mmDCFE0_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE1_SOFT_RESET", REG_MMIO, 0x159, &mmDCFE1_SOFT_RESET[0], sizeof(mmDCFE1_SOFT_RESET)/sizeof(mmDCFE1_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE2_SOFT_RESET", REG_MMIO, 0x15a, &mmDCFE2_SOFT_RESET[0], sizeof(mmDCFE2_SOFT_RESET)/sizeof(mmDCFE2_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE3_SOFT_RESET", REG_MMIO, 0x15b, &mmDCFE3_SOFT_RESET[0], sizeof(mmDCFE3_SOFT_RESET)/sizeof(mmDCFE3_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE4_SOFT_RESET", REG_MMIO, 0x15c, &mmDCFE4_SOFT_RESET[0], sizeof(mmDCFE4_SOFT_RESET)/sizeof(mmDCFE4_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCFE5_SOFT_RESET", REG_MMIO, 0x15d, &mmDCFE5_SOFT_RESET[0], sizeof(mmDCFE5_SOFT_RESET)/sizeof(mmDCFE5_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCI_SOFT_RESET", REG_MMIO, 0x15e, &mmDCI_SOFT_RESET[0], sizeof(mmDCI_SOFT_RESET)/sizeof(mmDCI_SOFT_RESET[0]), 0, 0 },
+	{ "mmDCCG_SOFT_RESET", REG_MMIO, 0x15f, &mmDCCG_SOFT_RESET[0], sizeof(mmDCCG_SOFT_RESET)/sizeof(mmDCCG_SOFT_RESET[0]), 0, 0 },
+	{ "mmRESPONSE_INTERRUPT_COUNT", REG_MMIO, 0x16, &mmRESPONSE_INTERRUPT_COUNT[0], sizeof(mmRESPONSE_INTERRUPT_COUNT)/sizeof(mmRESPONSE_INTERRUPT_COUNT[0]), 0, 0 },
+	{ "mmRIRB_WRITE_POINTER", REG_MMIO, 0x16, &mmRIRB_WRITE_POINTER[0], sizeof(mmRIRB_WRITE_POINTER)/sizeof(mmRIRB_WRITE_POINTER[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_G", REG_SMC, 0x16, &ixDP_AUX1_DEBUG_G[0], sizeof(ixDP_AUX1_DEBUG_G)/sizeof(ixDP_AUX1_DEBUG_G[0]), 0, 0 },
+	{ "ixCRT16", REG_SMC, 0x16, &ixCRT16[0], sizeof(ixCRT16)/sizeof(ixCRT16[0]), 0, 0 },
+	{ "mmSYMCLKA_CLOCK_ENABLE", REG_MMIO, 0x160, &mmSYMCLKA_CLOCK_ENABLE[0], sizeof(mmSYMCLKA_CLOCK_ENABLE)/sizeof(mmSYMCLKA_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_CTRL", REG_MMIO, 0x1600, &mmDMCU_CTRL[0], sizeof(mmDMCU_CTRL)/sizeof(mmDMCU_CTRL[0]), 0, 0 },
+	{ "mmDMCU_STATUS", REG_MMIO, 0x1601, &mmDMCU_STATUS[0], sizeof(mmDMCU_STATUS)/sizeof(mmDMCU_STATUS[0]), 0, 0 },
+	{ "mmDMCU_PC_START_ADDR", REG_MMIO, 0x1602, &mmDMCU_PC_START_ADDR[0], sizeof(mmDMCU_PC_START_ADDR)/sizeof(mmDMCU_PC_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_START_ADDR", REG_MMIO, 0x1603, &mmDMCU_FW_START_ADDR[0], sizeof(mmDMCU_FW_START_ADDR)/sizeof(mmDMCU_FW_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_END_ADDR", REG_MMIO, 0x1604, &mmDMCU_FW_END_ADDR[0], sizeof(mmDMCU_FW_END_ADDR)/sizeof(mmDMCU_FW_END_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_ISR_START_ADDR", REG_MMIO, 0x1605, &mmDMCU_FW_ISR_START_ADDR[0], sizeof(mmDMCU_FW_ISR_START_ADDR)/sizeof(mmDMCU_FW_ISR_START_ADDR[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_HI", REG_MMIO, 0x1606, &mmDMCU_FW_CS_HI[0], sizeof(mmDMCU_FW_CS_HI)/sizeof(mmDMCU_FW_CS_HI[0]), 0, 0 },
+	{ "mmDMCU_FW_CS_LO", REG_MMIO, 0x1607, &mmDMCU_FW_CS_LO[0], sizeof(mmDMCU_FW_CS_LO)/sizeof(mmDMCU_FW_CS_LO[0]), 0, 0 },
+	{ "mmDMCU_RAM_ACCESS_CTRL", REG_MMIO, 0x1608, &mmDMCU_RAM_ACCESS_CTRL[0], sizeof(mmDMCU_RAM_ACCESS_CTRL)/sizeof(mmDMCU_RAM_ACCESS_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_CTRL", REG_MMIO, 0x1609, &mmDMCU_ERAM_WR_CTRL[0], sizeof(mmDMCU_ERAM_WR_CTRL)/sizeof(mmDMCU_ERAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_WR_DATA", REG_MMIO, 0x160a, &mmDMCU_ERAM_WR_DATA[0], sizeof(mmDMCU_ERAM_WR_DATA)/sizeof(mmDMCU_ERAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_CTRL", REG_MMIO, 0x160b, &mmDMCU_ERAM_RD_CTRL[0], sizeof(mmDMCU_ERAM_RD_CTRL)/sizeof(mmDMCU_ERAM_RD_CTRL[0]), 0, 0 },
+	{ "mmDMCU_ERAM_RD_DATA", REG_MMIO, 0x160c, &mmDMCU_ERAM_RD_DATA[0], sizeof(mmDMCU_ERAM_RD_DATA)/sizeof(mmDMCU_ERAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_CTRL", REG_MMIO, 0x160d, &mmDMCU_IRAM_WR_CTRL[0], sizeof(mmDMCU_IRAM_WR_CTRL)/sizeof(mmDMCU_IRAM_WR_CTRL[0]), 0, 0 },
+	{ "mmDMCU_IRAM_WR_DATA", REG_MMIO, 0x160e, &mmDMCU_IRAM_WR_DATA[0], sizeof(mmDMCU_IRAM_WR_DATA)/sizeof(mmDMCU_IRAM_WR_DATA[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_CTRL", REG_MMIO, 0x160f, &mmDMCU_IRAM_RD_CTRL[0], sizeof(mmDMCU_IRAM_RD_CTRL)/sizeof(mmDMCU_IRAM_RD_CTRL[0]), 0, 0 },
+	{ "mmSYMCLKB_CLOCK_ENABLE", REG_MMIO, 0x161, &mmSYMCLKB_CLOCK_ENABLE[0], sizeof(mmSYMCLKB_CLOCK_ENABLE)/sizeof(mmSYMCLKB_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDMCU_IRAM_RD_DATA", REG_MMIO, 0x1610, &mmDMCU_IRAM_RD_DATA[0], sizeof(mmDMCU_IRAM_RD_DATA)/sizeof(mmDMCU_IRAM_RD_DATA[0]), 0, 0 },
+	{ "mmDMCU_EVENT_TRIGGER", REG_MMIO, 0x1611, &mmDMCU_EVENT_TRIGGER[0], sizeof(mmDMCU_EVENT_TRIGGER)/sizeof(mmDMCU_EVENT_TRIGGER[0]), 0, 0 },
+	{ "mmDMCU_UC_INTERNAL_INT_STATUS", REG_MMIO, 0x1612, &mmDMCU_UC_INTERNAL_INT_STATUS[0], sizeof(mmDMCU_UC_INTERNAL_INT_STATUS)/sizeof(mmDMCU_UC_INTERNAL_INT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_SS_INTERRUPT_CNTL_STATUS", REG_MMIO, 0x1613, &mmDMCU_SS_INTERRUPT_CNTL_STATUS[0], sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS)/sizeof(mmDMCU_SS_INTERRUPT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_STATUS", REG_MMIO, 0x1614, &mmDMCU_INTERRUPT_STATUS[0], sizeof(mmDMCU_INTERRUPT_STATUS)/sizeof(mmDMCU_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_HOST_EN_MASK", REG_MMIO, 0x1615, &mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_HOST_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_EN_MASK", REG_MMIO, 0x1616, &mmDMCU_INTERRUPT_TO_UC_EN_MASK[0], sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK)/sizeof(mmDMCU_INTERRUPT_TO_UC_EN_MASK[0]), 0, 0 },
+	{ "mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL", REG_MMIO, 0x1617, &mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0], sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL)/sizeof(mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL[0]), 0, 0 },
+	{ "mmDC_DMCU_SCRATCH", REG_MMIO, 0x1618, &mmDC_DMCU_SCRATCH[0], sizeof(mmDC_DMCU_SCRATCH)/sizeof(mmDC_DMCU_SCRATCH[0]), 0, 0 },
+	{ "mmDMCU_INT_CNT", REG_MMIO, 0x1619, &mmDMCU_INT_CNT[0], sizeof(mmDMCU_INT_CNT)/sizeof(mmDMCU_INT_CNT[0]), 0, 0 },
+	{ "mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS", REG_MMIO, 0x161a, &mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0], sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS)/sizeof(mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS[0]), 0, 0 },
+	{ "mmDMCU_UC_CLK_GATING_CNTL", REG_MMIO, 0x161b, &mmDMCU_UC_CLK_GATING_CNTL[0], sizeof(mmDMCU_UC_CLK_GATING_CNTL)/sizeof(mmDMCU_UC_CLK_GATING_CNTL[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG1", REG_MMIO, 0x161c, &mmMASTER_COMM_DATA_REG1[0], sizeof(mmMASTER_COMM_DATA_REG1)/sizeof(mmMASTER_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG2", REG_MMIO, 0x161d, &mmMASTER_COMM_DATA_REG2[0], sizeof(mmMASTER_COMM_DATA_REG2)/sizeof(mmMASTER_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmMASTER_COMM_DATA_REG3", REG_MMIO, 0x161e, &mmMASTER_COMM_DATA_REG3[0], sizeof(mmMASTER_COMM_DATA_REG3)/sizeof(mmMASTER_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmMASTER_COMM_CMD_REG", REG_MMIO, 0x161f, &mmMASTER_COMM_CMD_REG[0], sizeof(mmMASTER_COMM_CMD_REG)/sizeof(mmMASTER_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSYMCLKC_CLOCK_ENABLE", REG_MMIO, 0x162, &mmSYMCLKC_CLOCK_ENABLE[0], sizeof(mmSYMCLKC_CLOCK_ENABLE)/sizeof(mmSYMCLKC_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmMASTER_COMM_CNTL_REG", REG_MMIO, 0x1620, &mmMASTER_COMM_CNTL_REG[0], sizeof(mmMASTER_COMM_CNTL_REG)/sizeof(mmMASTER_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG1", REG_MMIO, 0x1621, &mmSLAVE_COMM_DATA_REG1[0], sizeof(mmSLAVE_COMM_DATA_REG1)/sizeof(mmSLAVE_COMM_DATA_REG1[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG2", REG_MMIO, 0x1622, &mmSLAVE_COMM_DATA_REG2[0], sizeof(mmSLAVE_COMM_DATA_REG2)/sizeof(mmSLAVE_COMM_DATA_REG2[0]), 0, 0 },
+	{ "mmSLAVE_COMM_DATA_REG3", REG_MMIO, 0x1623, &mmSLAVE_COMM_DATA_REG3[0], sizeof(mmSLAVE_COMM_DATA_REG3)/sizeof(mmSLAVE_COMM_DATA_REG3[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CMD_REG", REG_MMIO, 0x1624, &mmSLAVE_COMM_CMD_REG[0], sizeof(mmSLAVE_COMM_CMD_REG)/sizeof(mmSLAVE_COMM_CMD_REG[0]), 0, 0 },
+	{ "mmSLAVE_COMM_CNTL_REG", REG_MMIO, 0x1625, &mmSLAVE_COMM_CNTL_REG[0], sizeof(mmSLAVE_COMM_CNTL_REG)/sizeof(mmSLAVE_COMM_CNTL_REG[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_INDEX", REG_MMIO, 0x1626, &mmDMCU_TEST_DEBUG_INDEX[0], sizeof(mmDMCU_TEST_DEBUG_INDEX)/sizeof(mmDMCU_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMCU_TEST_DEBUG_DATA", REG_MMIO, 0x1627, &mmDMCU_TEST_DEBUG_DATA[0], sizeof(mmDMCU_TEST_DEBUG_DATA)/sizeof(mmDMCU_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBL1_PWM_AMBIENT_LIGHT_LEVEL", REG_MMIO, 0x1628, &mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0], sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL)/sizeof(mmBL1_PWM_AMBIENT_LIGHT_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_USER_LEVEL", REG_MMIO, 0x1629, &mmBL1_PWM_USER_LEVEL[0], sizeof(mmBL1_PWM_USER_LEVEL)/sizeof(mmBL1_PWM_USER_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_TARGET_ABM_LEVEL", REG_MMIO, 0x162a, &mmBL1_PWM_TARGET_ABM_LEVEL[0], sizeof(mmBL1_PWM_TARGET_ABM_LEVEL)/sizeof(mmBL1_PWM_TARGET_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_CURRENT_ABM_LEVEL", REG_MMIO, 0x162b, &mmBL1_PWM_CURRENT_ABM_LEVEL[0], sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL)/sizeof(mmBL1_PWM_CURRENT_ABM_LEVEL[0]), 0, 0 },
+	{ "mmBL1_PWM_FINAL_DUTY_CYCLE", REG_MMIO, 0x162c, &mmBL1_PWM_FINAL_DUTY_CYCLE[0], sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE)/sizeof(mmBL1_PWM_FINAL_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_MINIMUM_DUTY_CYCLE", REG_MMIO, 0x162d, &mmBL1_PWM_MINIMUM_DUTY_CYCLE[0], sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE)/sizeof(mmBL1_PWM_MINIMUM_DUTY_CYCLE[0]), 0, 0 },
+	{ "mmBL1_PWM_ABM_CNTL", REG_MMIO, 0x162e, &mmBL1_PWM_ABM_CNTL[0], sizeof(mmBL1_PWM_ABM_CNTL)/sizeof(mmBL1_PWM_ABM_CNTL[0]), 0, 0 },
+	{ "mmBL1_PWM_BL_UPDATE_SAMPLE_RATE", REG_MMIO, 0x162f, &mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0], sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE)/sizeof(mmBL1_PWM_BL_UPDATE_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmSYMCLKD_CLOCK_ENABLE", REG_MMIO, 0x163, &mmSYMCLKD_CLOCK_ENABLE[0], sizeof(mmSYMCLKD_CLOCK_ENABLE)/sizeof(mmSYMCLKD_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmBL1_PWM_GRP2_REG_LOCK", REG_MMIO, 0x1630, &mmBL1_PWM_GRP2_REG_LOCK[0], sizeof(mmBL1_PWM_GRP2_REG_LOCK)/sizeof(mmBL1_PWM_GRP2_REG_LOCK[0]), 0, 0 },
+	{ "mmDC_ABM1_CNTL", REG_MMIO, 0x1638, &mmDC_ABM1_CNTL[0], sizeof(mmDC_ABM1_CNTL)/sizeof(mmDC_ABM1_CNTL[0]), 0, 0 },
+	{ "mmDC_ABM1_IPCSC_COEFF_SEL", REG_MMIO, 0x1639, &mmDC_ABM1_IPCSC_COEFF_SEL[0], sizeof(mmDC_ABM1_IPCSC_COEFF_SEL)/sizeof(mmDC_ABM1_IPCSC_COEFF_SEL[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_0", REG_MMIO, 0x163a, &mmDC_ABM1_ACE_OFFSET_SLOPE_0[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_0[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_1", REG_MMIO, 0x163b, &mmDC_ABM1_ACE_OFFSET_SLOPE_1[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_1[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_2", REG_MMIO, 0x163c, &mmDC_ABM1_ACE_OFFSET_SLOPE_2[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_2[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_3", REG_MMIO, 0x163d, &mmDC_ABM1_ACE_OFFSET_SLOPE_3[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_3[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_OFFSET_SLOPE_4", REG_MMIO, 0x163e, &mmDC_ABM1_ACE_OFFSET_SLOPE_4[0], sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4)/sizeof(mmDC_ABM1_ACE_OFFSET_SLOPE_4[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_12", REG_MMIO, 0x163f, &mmDC_ABM1_ACE_THRES_12[0], sizeof(mmDC_ABM1_ACE_THRES_12)/sizeof(mmDC_ABM1_ACE_THRES_12[0]), 0, 0 },
+	{ "mmSYMCLKE_CLOCK_ENABLE", REG_MMIO, 0x164, &mmSYMCLKE_CLOCK_ENABLE[0], sizeof(mmSYMCLKE_CLOCK_ENABLE)/sizeof(mmSYMCLKE_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_THRES_34", REG_MMIO, 0x1640, &mmDC_ABM1_ACE_THRES_34[0], sizeof(mmDC_ABM1_ACE_THRES_34)/sizeof(mmDC_ABM1_ACE_THRES_34[0]), 0, 0 },
+	{ "mmDC_ABM1_ACE_CNTL_MISC", REG_MMIO, 0x1641, &mmDC_ABM1_ACE_CNTL_MISC[0], sizeof(mmDC_ABM1_ACE_CNTL_MISC)/sizeof(mmDC_ABM1_ACE_CNTL_MISC[0]), 0, 0 },
+	{ "mmDC_ABM1_DEBUG_MISC", REG_MMIO, 0x1649, &mmDC_ABM1_DEBUG_MISC[0], sizeof(mmDC_ABM1_DEBUG_MISC)/sizeof(mmDC_ABM1_DEBUG_MISC[0]), 0, 0 },
+	{ "mmDC_ABM1_HGLS_REG_READ_PROGRESS", REG_MMIO, 0x164a, &mmDC_ABM1_HGLS_REG_READ_PROGRESS[0], sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS)/sizeof(mmDC_ABM1_HGLS_REG_READ_PROGRESS[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_MISC_CTRL", REG_MMIO, 0x164b, &mmDC_ABM1_HG_MISC_CTRL[0], sizeof(mmDC_ABM1_HG_MISC_CTRL)/sizeof(mmDC_ABM1_HG_MISC_CTRL[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SUM_OF_LUMA", REG_MMIO, 0x164c, &mmDC_ABM1_LS_SUM_OF_LUMA[0], sizeof(mmDC_ABM1_LS_SUM_OF_LUMA)/sizeof(mmDC_ABM1_LS_SUM_OF_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_LUMA", REG_MMIO, 0x164d, &mmDC_ABM1_LS_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA", REG_MMIO, 0x164e, &mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0], sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA)/sizeof(mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_PIXEL_COUNT", REG_MMIO, 0x164f, &mmDC_ABM1_LS_PIXEL_COUNT[0], sizeof(mmDC_ABM1_LS_PIXEL_COUNT)/sizeof(mmDC_ABM1_LS_PIXEL_COUNT[0]), 0, 0 },
+	{ "mmSYMCLKF_CLOCK_ENABLE", REG_MMIO, 0x165, &mmSYMCLKF_CLOCK_ENABLE[0], sizeof(mmSYMCLKF_CLOCK_ENABLE)/sizeof(mmSYMCLKF_CLOCK_ENABLE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_OVR_SCAN_BIN", REG_MMIO, 0x1650, &mmDC_ABM1_LS_OVR_SCAN_BIN[0], sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN)/sizeof(mmDC_ABM1_LS_OVR_SCAN_BIN[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES", REG_MMIO, 0x1651, &mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0], sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES)/sizeof(mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT", REG_MMIO, 0x1652, &mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT", REG_MMIO, 0x1653, &mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0], sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT)/sizeof(mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_SAMPLE_RATE", REG_MMIO, 0x1654, &mmDC_ABM1_HG_SAMPLE_RATE[0], sizeof(mmDC_ABM1_HG_SAMPLE_RATE)/sizeof(mmDC_ABM1_HG_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_LS_SAMPLE_RATE", REG_MMIO, 0x1655, &mmDC_ABM1_LS_SAMPLE_RATE[0], sizeof(mmDC_ABM1_LS_SAMPLE_RATE)/sizeof(mmDC_ABM1_LS_SAMPLE_RATE[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG", REG_MMIO, 0x1656, &mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0], sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG)/sizeof(mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX", REG_MMIO, 0x1657, &mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX", REG_MMIO, 0x1658, &mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX", REG_MMIO, 0x1659, &mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX", REG_MMIO, 0x165a, &mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0], sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX)/sizeof(mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_1", REG_MMIO, 0x165b, &mmDC_ABM1_HG_RESULT_1[0], sizeof(mmDC_ABM1_HG_RESULT_1)/sizeof(mmDC_ABM1_HG_RESULT_1[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_2", REG_MMIO, 0x165c, &mmDC_ABM1_HG_RESULT_2[0], sizeof(mmDC_ABM1_HG_RESULT_2)/sizeof(mmDC_ABM1_HG_RESULT_2[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_3", REG_MMIO, 0x165d, &mmDC_ABM1_HG_RESULT_3[0], sizeof(mmDC_ABM1_HG_RESULT_3)/sizeof(mmDC_ABM1_HG_RESULT_3[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_4", REG_MMIO, 0x165e, &mmDC_ABM1_HG_RESULT_4[0], sizeof(mmDC_ABM1_HG_RESULT_4)/sizeof(mmDC_ABM1_HG_RESULT_4[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_5", REG_MMIO, 0x165f, &mmDC_ABM1_HG_RESULT_5[0], sizeof(mmDC_ABM1_HG_RESULT_5)/sizeof(mmDC_ABM1_HG_RESULT_5[0]), 0, 0 },
+	{ "mmUNIPHY_SOFT_RESET", REG_MMIO, 0x166, &mmUNIPHY_SOFT_RESET[0], sizeof(mmUNIPHY_SOFT_RESET)/sizeof(mmUNIPHY_SOFT_RESET[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_6", REG_MMIO, 0x1660, &mmDC_ABM1_HG_RESULT_6[0], sizeof(mmDC_ABM1_HG_RESULT_6)/sizeof(mmDC_ABM1_HG_RESULT_6[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_7", REG_MMIO, 0x1661, &mmDC_ABM1_HG_RESULT_7[0], sizeof(mmDC_ABM1_HG_RESULT_7)/sizeof(mmDC_ABM1_HG_RESULT_7[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_8", REG_MMIO, 0x1662, &mmDC_ABM1_HG_RESULT_8[0], sizeof(mmDC_ABM1_HG_RESULT_8)/sizeof(mmDC_ABM1_HG_RESULT_8[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_9", REG_MMIO, 0x1663, &mmDC_ABM1_HG_RESULT_9[0], sizeof(mmDC_ABM1_HG_RESULT_9)/sizeof(mmDC_ABM1_HG_RESULT_9[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_10", REG_MMIO, 0x1664, &mmDC_ABM1_HG_RESULT_10[0], sizeof(mmDC_ABM1_HG_RESULT_10)/sizeof(mmDC_ABM1_HG_RESULT_10[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_11", REG_MMIO, 0x1665, &mmDC_ABM1_HG_RESULT_11[0], sizeof(mmDC_ABM1_HG_RESULT_11)/sizeof(mmDC_ABM1_HG_RESULT_11[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_12", REG_MMIO, 0x1666, &mmDC_ABM1_HG_RESULT_12[0], sizeof(mmDC_ABM1_HG_RESULT_12)/sizeof(mmDC_ABM1_HG_RESULT_12[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_13", REG_MMIO, 0x1667, &mmDC_ABM1_HG_RESULT_13[0], sizeof(mmDC_ABM1_HG_RESULT_13)/sizeof(mmDC_ABM1_HG_RESULT_13[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_14", REG_MMIO, 0x1668, &mmDC_ABM1_HG_RESULT_14[0], sizeof(mmDC_ABM1_HG_RESULT_14)/sizeof(mmDC_ABM1_HG_RESULT_14[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_15", REG_MMIO, 0x1669, &mmDC_ABM1_HG_RESULT_15[0], sizeof(mmDC_ABM1_HG_RESULT_15)/sizeof(mmDC_ABM1_HG_RESULT_15[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_16", REG_MMIO, 0x166a, &mmDC_ABM1_HG_RESULT_16[0], sizeof(mmDC_ABM1_HG_RESULT_16)/sizeof(mmDC_ABM1_HG_RESULT_16[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_17", REG_MMIO, 0x166b, &mmDC_ABM1_HG_RESULT_17[0], sizeof(mmDC_ABM1_HG_RESULT_17)/sizeof(mmDC_ABM1_HG_RESULT_17[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_18", REG_MMIO, 0x166c, &mmDC_ABM1_HG_RESULT_18[0], sizeof(mmDC_ABM1_HG_RESULT_18)/sizeof(mmDC_ABM1_HG_RESULT_18[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_19", REG_MMIO, 0x166d, &mmDC_ABM1_HG_RESULT_19[0], sizeof(mmDC_ABM1_HG_RESULT_19)/sizeof(mmDC_ABM1_HG_RESULT_19[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_20", REG_MMIO, 0x166e, &mmDC_ABM1_HG_RESULT_20[0], sizeof(mmDC_ABM1_HG_RESULT_20)/sizeof(mmDC_ABM1_HG_RESULT_20[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_21", REG_MMIO, 0x166f, &mmDC_ABM1_HG_RESULT_21[0], sizeof(mmDC_ABM1_HG_RESULT_21)/sizeof(mmDC_ABM1_HG_RESULT_21[0]), 0, 0 },
+	{ "mmDCO_SOFT_RESET", REG_MMIO, 0x167, &mmDCO_SOFT_RESET[0], sizeof(mmDCO_SOFT_RESET)/sizeof(mmDCO_SOFT_RESET[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_22", REG_MMIO, 0x1670, &mmDC_ABM1_HG_RESULT_22[0], sizeof(mmDC_ABM1_HG_RESULT_22)/sizeof(mmDC_ABM1_HG_RESULT_22[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_23", REG_MMIO, 0x1671, &mmDC_ABM1_HG_RESULT_23[0], sizeof(mmDC_ABM1_HG_RESULT_23)/sizeof(mmDC_ABM1_HG_RESULT_23[0]), 0, 0 },
+	{ "mmDC_ABM1_HG_RESULT_24", REG_MMIO, 0x1672, &mmDC_ABM1_HG_RESULT_24[0], sizeof(mmDC_ABM1_HG_RESULT_24)/sizeof(mmDC_ABM1_HG_RESULT_24[0]), 0, 0 },
+	{ "mmDVOACLKD_CNTL", REG_MMIO, 0x168, &mmDVOACLKD_CNTL[0], sizeof(mmDVOACLKD_CNTL)/sizeof(mmDVOACLKD_CNTL[0]), 0, 0 },
+	{ "mmMVP_CONTROL1", REG_MMIO, 0x1680, &mmMVP_CONTROL1[0], sizeof(mmMVP_CONTROL1)/sizeof(mmMVP_CONTROL1[0]), 0, 0 },
+	{ "mmMVP_CONTROL2", REG_MMIO, 0x1681, &mmMVP_CONTROL2[0], sizeof(mmMVP_CONTROL2)/sizeof(mmMVP_CONTROL2[0]), 0, 0 },
+	{ "mmMVP_FIFO_CONTROL", REG_MMIO, 0x1682, &mmMVP_FIFO_CONTROL[0], sizeof(mmMVP_FIFO_CONTROL)/sizeof(mmMVP_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmMVP_FIFO_STATUS", REG_MMIO, 0x1683, &mmMVP_FIFO_STATUS[0], sizeof(mmMVP_FIFO_STATUS)/sizeof(mmMVP_FIFO_STATUS[0]), 0, 0 },
+	{ "mmMVP_SLAVE_STATUS", REG_MMIO, 0x1684, &mmMVP_SLAVE_STATUS[0], sizeof(mmMVP_SLAVE_STATUS)/sizeof(mmMVP_SLAVE_STATUS[0]), 0, 0 },
+	{ "mmMVP_INBAND_CNTL_CAP", REG_MMIO, 0x1685, &mmMVP_INBAND_CNTL_CAP[0], sizeof(mmMVP_INBAND_CNTL_CAP)/sizeof(mmMVP_INBAND_CNTL_CAP[0]), 0, 0 },
+	{ "mmMVP_BLACK_KEYER", REG_MMIO, 0x1686, &mmMVP_BLACK_KEYER[0], sizeof(mmMVP_BLACK_KEYER)/sizeof(mmMVP_BLACK_KEYER[0]), 0, 0 },
+	{ "mmMVP_CRC_CNTL", REG_MMIO, 0x1687, &mmMVP_CRC_CNTL[0], sizeof(mmMVP_CRC_CNTL)/sizeof(mmMVP_CRC_CNTL[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_BLUE_GREEN", REG_MMIO, 0x1688, &mmMVP_CRC_RESULT_BLUE_GREEN[0], sizeof(mmMVP_CRC_RESULT_BLUE_GREEN)/sizeof(mmMVP_CRC_RESULT_BLUE_GREEN[0]), 0, 0 },
+	{ "mmMVP_CRC_RESULT_RED", REG_MMIO, 0x1689, &mmMVP_CRC_RESULT_RED[0], sizeof(mmMVP_CRC_RESULT_RED)/sizeof(mmMVP_CRC_RESULT_RED[0]), 0, 0 },
+	{ "mmMVP_CONTROL3", REG_MMIO, 0x168a, &mmMVP_CONTROL3[0], sizeof(mmMVP_CONTROL3)/sizeof(mmMVP_CONTROL3[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL1", REG_MMIO, 0x168b, &mmMVP_RECEIVE_CNT_CNTL1[0], sizeof(mmMVP_RECEIVE_CNT_CNTL1)/sizeof(mmMVP_RECEIVE_CNT_CNTL1[0]), 0, 0 },
+	{ "mmMVP_RECEIVE_CNT_CNTL2", REG_MMIO, 0x168c, &mmMVP_RECEIVE_CNT_CNTL2[0], sizeof(mmMVP_RECEIVE_CNT_CNTL2)/sizeof(mmMVP_RECEIVE_CNT_CNTL2[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_INDEX", REG_MMIO, 0x168d, &mmMVP_TEST_DEBUG_INDEX[0], sizeof(mmMVP_TEST_DEBUG_INDEX)/sizeof(mmMVP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMVP_TEST_DEBUG_DATA", REG_MMIO, 0x168e, &mmMVP_TEST_DEBUG_DATA[0], sizeof(mmMVP_TEST_DEBUG_DATA)/sizeof(mmMVP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMVP_DEBUG", REG_MMIO, 0x168f, &mmMVP_DEBUG[0], sizeof(mmMVP_DEBUG)/sizeof(mmMVP_DEBUG[0]), 0, 0 },
+	{ "mmDVOACLKC_MVP_CNTL", REG_MMIO, 0x169, &mmDVOACLKC_MVP_CNTL[0], sizeof(mmDVOACLKC_MVP_CNTL)/sizeof(mmDVOACLKC_MVP_CNTL[0]), 0, 0 },
+	{ "mmDC_ABM1_OVERSCAN_PIXEL_VALUE", REG_MMIO, 0x169b, &mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0], sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE)/sizeof(mmDC_ABM1_OVERSCAN_PIXEL_VALUE[0]), 0, 0 },
+	{ "mmDC_ABM1_BL_MASTER_LOCK", REG_MMIO, 0x169c, &mmDC_ABM1_BL_MASTER_LOCK[0], sizeof(mmDC_ABM1_BL_MASTER_LOCK)/sizeof(mmDC_ABM1_BL_MASTER_LOCK[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_INDEX", REG_MMIO, 0x169e, &mmABM_TEST_DEBUG_INDEX[0], sizeof(mmABM_TEST_DEBUG_INDEX)/sizeof(mmABM_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmABM_TEST_DEBUG_DATA", REG_MMIO, 0x169f, &mmABM_TEST_DEBUG_DATA[0], sizeof(mmABM_TEST_DEBUG_DATA)/sizeof(mmABM_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDVOACLKC_CNTL", REG_MMIO, 0x16a, &mmDVOACLKC_CNTL[0], sizeof(mmDVOACLKC_CNTL)/sizeof(mmDVOACLKC_CNTL[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO_SOURCE", REG_MMIO, 0x16b, &mmDCCG_AUDIO_DTO_SOURCE[0], sizeof(mmDCCG_AUDIO_DTO_SOURCE)/sizeof(mmDCCG_AUDIO_DTO_SOURCE[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_PHASE", REG_MMIO, 0x16c, &mmDCCG_AUDIO_DTO0_PHASE[0], sizeof(mmDCCG_AUDIO_DTO0_PHASE)/sizeof(mmDCCG_AUDIO_DTO0_PHASE[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO0_MODULE", REG_MMIO, 0x16d, &mmDCCG_AUDIO_DTO0_MODULE[0], sizeof(mmDCCG_AUDIO_DTO0_MODULE)/sizeof(mmDCCG_AUDIO_DTO0_MODULE[0]), 0, 0 },
+	{ "mmFBC_CNTL", REG_MMIO, 0x16d0, &mmFBC_CNTL[0], sizeof(mmFBC_CNTL)/sizeof(mmFBC_CNTL[0]), 0, 0 },
+	{ "mmFBC_IDLE_MASK", REG_MMIO, 0x16d1, &mmFBC_IDLE_MASK[0], sizeof(mmFBC_IDLE_MASK)/sizeof(mmFBC_IDLE_MASK[0]), 0, 0 },
+	{ "mmFBC_IDLE_FORCE_CLEAR_MASK", REG_MMIO, 0x16d2, &mmFBC_IDLE_FORCE_CLEAR_MASK[0], sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK)/sizeof(mmFBC_IDLE_FORCE_CLEAR_MASK[0]), 0, 0 },
+	{ "mmFBC_START_STOP_DELAY", REG_MMIO, 0x16d3, &mmFBC_START_STOP_DELAY[0], sizeof(mmFBC_START_STOP_DELAY)/sizeof(mmFBC_START_STOP_DELAY[0]), 0, 0 },
+	{ "mmFBC_COMP_CNTL", REG_MMIO, 0x16d4, &mmFBC_COMP_CNTL[0], sizeof(mmFBC_COMP_CNTL)/sizeof(mmFBC_COMP_CNTL[0]), 0, 0 },
+	{ "mmFBC_COMP_MODE", REG_MMIO, 0x16d5, &mmFBC_COMP_MODE[0], sizeof(mmFBC_COMP_MODE)/sizeof(mmFBC_COMP_MODE[0]), 0, 0 },
+	{ "mmFBC_DEBUG0", REG_MMIO, 0x16d6, &mmFBC_DEBUG0[0], sizeof(mmFBC_DEBUG0)/sizeof(mmFBC_DEBUG0[0]), 0, 0 },
+	{ "mmFBC_DEBUG1", REG_MMIO, 0x16d7, &mmFBC_DEBUG1[0], sizeof(mmFBC_DEBUG1)/sizeof(mmFBC_DEBUG1[0]), 0, 0 },
+	{ "mmFBC_DEBUG2", REG_MMIO, 0x16d8, &mmFBC_DEBUG2[0], sizeof(mmFBC_DEBUG2)/sizeof(mmFBC_DEBUG2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT0", REG_MMIO, 0x16d9, &mmFBC_IND_LUT0[0], sizeof(mmFBC_IND_LUT0)/sizeof(mmFBC_IND_LUT0[0]), 0, 0 },
+	{ "mmFBC_IND_LUT1", REG_MMIO, 0x16da, &mmFBC_IND_LUT1[0], sizeof(mmFBC_IND_LUT1)/sizeof(mmFBC_IND_LUT1[0]), 0, 0 },
+	{ "mmFBC_IND_LUT2", REG_MMIO, 0x16db, &mmFBC_IND_LUT2[0], sizeof(mmFBC_IND_LUT2)/sizeof(mmFBC_IND_LUT2[0]), 0, 0 },
+	{ "mmFBC_IND_LUT3", REG_MMIO, 0x16dc, &mmFBC_IND_LUT3[0], sizeof(mmFBC_IND_LUT3)/sizeof(mmFBC_IND_LUT3[0]), 0, 0 },
+	{ "mmFBC_IND_LUT4", REG_MMIO, 0x16dd, &mmFBC_IND_LUT4[0], sizeof(mmFBC_IND_LUT4)/sizeof(mmFBC_IND_LUT4[0]), 0, 0 },
+	{ "mmFBC_IND_LUT5", REG_MMIO, 0x16de, &mmFBC_IND_LUT5[0], sizeof(mmFBC_IND_LUT5)/sizeof(mmFBC_IND_LUT5[0]), 0, 0 },
+	{ "mmFBC_IND_LUT6", REG_MMIO, 0x16df, &mmFBC_IND_LUT6[0], sizeof(mmFBC_IND_LUT6)/sizeof(mmFBC_IND_LUT6[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_PHASE", REG_MMIO, 0x16e, &mmDCCG_AUDIO_DTO1_PHASE[0], sizeof(mmDCCG_AUDIO_DTO1_PHASE)/sizeof(mmDCCG_AUDIO_DTO1_PHASE[0]), 0, 0 },
+	{ "mmFBC_IND_LUT7", REG_MMIO, 0x16e0, &mmFBC_IND_LUT7[0], sizeof(mmFBC_IND_LUT7)/sizeof(mmFBC_IND_LUT7[0]), 0, 0 },
+	{ "mmFBC_IND_LUT8", REG_MMIO, 0x16e1, &mmFBC_IND_LUT8[0], sizeof(mmFBC_IND_LUT8)/sizeof(mmFBC_IND_LUT8[0]), 0, 0 },
+	{ "mmFBC_IND_LUT9", REG_MMIO, 0x16e2, &mmFBC_IND_LUT9[0], sizeof(mmFBC_IND_LUT9)/sizeof(mmFBC_IND_LUT9[0]), 0, 0 },
+	{ "mmFBC_IND_LUT10", REG_MMIO, 0x16e3, &mmFBC_IND_LUT10[0], sizeof(mmFBC_IND_LUT10)/sizeof(mmFBC_IND_LUT10[0]), 0, 0 },
+	{ "mmFBC_IND_LUT11", REG_MMIO, 0x16e4, &mmFBC_IND_LUT11[0], sizeof(mmFBC_IND_LUT11)/sizeof(mmFBC_IND_LUT11[0]), 0, 0 },
+	{ "mmFBC_IND_LUT12", REG_MMIO, 0x16e5, &mmFBC_IND_LUT12[0], sizeof(mmFBC_IND_LUT12)/sizeof(mmFBC_IND_LUT12[0]), 0, 0 },
+	{ "mmFBC_IND_LUT13", REG_MMIO, 0x16e6, &mmFBC_IND_LUT13[0], sizeof(mmFBC_IND_LUT13)/sizeof(mmFBC_IND_LUT13[0]), 0, 0 },
+	{ "mmFBC_IND_LUT14", REG_MMIO, 0x16e7, &mmFBC_IND_LUT14[0], sizeof(mmFBC_IND_LUT14)/sizeof(mmFBC_IND_LUT14[0]), 0, 0 },
+	{ "mmFBC_IND_LUT15", REG_MMIO, 0x16e8, &mmFBC_IND_LUT15[0], sizeof(mmFBC_IND_LUT15)/sizeof(mmFBC_IND_LUT15[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_01", REG_MMIO, 0x16e9, &mmFBC_CSM_REGION_OFFSET_01[0], sizeof(mmFBC_CSM_REGION_OFFSET_01)/sizeof(mmFBC_CSM_REGION_OFFSET_01[0]), 0, 0 },
+	{ "mmFBC_CSM_REGION_OFFSET_23", REG_MMIO, 0x16ea, &mmFBC_CSM_REGION_OFFSET_23[0], sizeof(mmFBC_CSM_REGION_OFFSET_23)/sizeof(mmFBC_CSM_REGION_OFFSET_23[0]), 0, 0 },
+	{ "mmFBC_CLIENT_REGION_MASK", REG_MMIO, 0x16eb, &mmFBC_CLIENT_REGION_MASK[0], sizeof(mmFBC_CLIENT_REGION_MASK)/sizeof(mmFBC_CLIENT_REGION_MASK[0]), 0, 0 },
+	{ "mmFBC_DEBUG_COMP", REG_MMIO, 0x16ec, &mmFBC_DEBUG_COMP[0], sizeof(mmFBC_DEBUG_COMP)/sizeof(mmFBC_DEBUG_COMP[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR", REG_MMIO, 0x16ed, &mmFBC_DEBUG_CSR[0], sizeof(mmFBC_DEBUG_CSR)/sizeof(mmFBC_DEBUG_CSR[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA", REG_MMIO, 0x16ee, &mmFBC_DEBUG_CSR_RDATA[0], sizeof(mmFBC_DEBUG_CSR_RDATA)/sizeof(mmFBC_DEBUG_CSR_RDATA[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA", REG_MMIO, 0x16ef, &mmFBC_DEBUG_CSR_WDATA[0], sizeof(mmFBC_DEBUG_CSR_WDATA)/sizeof(mmFBC_DEBUG_CSR_WDATA[0]), 0, 0 },
+	{ "mmDCCG_AUDIO_DTO1_MODULE", REG_MMIO, 0x16f, &mmDCCG_AUDIO_DTO1_MODULE[0], sizeof(mmDCCG_AUDIO_DTO1_MODULE)/sizeof(mmDCCG_AUDIO_DTO1_MODULE[0]), 0, 0 },
+	{ "mmFBC_MISC", REG_MMIO, 0x16f0, &mmFBC_MISC[0], sizeof(mmFBC_MISC)/sizeof(mmFBC_MISC[0]), 0, 0 },
+	{ "mmFBC_STATUS", REG_MMIO, 0x16f1, &mmFBC_STATUS[0], sizeof(mmFBC_STATUS)/sizeof(mmFBC_STATUS[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_INDEX", REG_MMIO, 0x16f4, &mmFBC_TEST_DEBUG_INDEX[0], sizeof(mmFBC_TEST_DEBUG_INDEX)/sizeof(mmFBC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFBC_TEST_DEBUG_DATA", REG_MMIO, 0x16f5, &mmFBC_TEST_DEBUG_DATA[0], sizeof(mmFBC_TEST_DEBUG_DATA)/sizeof(mmFBC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_RDATA_HI", REG_MMIO, 0x16f6, &mmFBC_DEBUG_CSR_RDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_RDATA_HI)/sizeof(mmFBC_DEBUG_CSR_RDATA_HI[0]), 0, 0 },
+	{ "mmFBC_DEBUG_CSR_WDATA_HI", REG_MMIO, 0x16f7, &mmFBC_DEBUG_CSR_WDATA_HI[0], sizeof(mmFBC_DEBUG_CSR_WDATA_HI)/sizeof(mmFBC_DEBUG_CSR_WDATA_HI[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_H", REG_SMC, 0x17, &ixDP_AUX1_DEBUG_H[0], sizeof(ixDP_AUX1_DEBUG_H)/sizeof(ixDP_AUX1_DEBUG_H[0]), 0, 0 },
+	{ "mmRIRB_CONTROL", REG_MMIO, 0x17, &mmRIRB_CONTROL[0], sizeof(mmRIRB_CONTROL)/sizeof(mmRIRB_CONTROL[0]), 0, 0 },
+	{ "mmRIRB_STATUS", REG_MMIO, 0x17, &mmRIRB_STATUS[0], sizeof(mmRIRB_STATUS)/sizeof(mmRIRB_STATUS[0]), 0, 0 },
+	{ "mmRIRB_SIZE", REG_MMIO, 0x17, &mmRIRB_SIZE[0], sizeof(mmRIRB_SIZE)/sizeof(mmRIRB_SIZE[0]), 0, 0 },
+	{ "ixCRT17", REG_SMC, 0x17, &ixCRT17[0], sizeof(ixCRT17)/sizeof(ixCRT17[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFCOUNTER_CNTL", REG_MMIO, 0x170, NULL, 0, 0, 0 },
+	{ "mmPERFCOUNTER_CNTL", REG_MMIO, 0x170, &mmPERFCOUNTER_CNTL[0], sizeof(mmPERFCOUNTER_CNTL)/sizeof(mmPERFCOUNTER_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_REF_DIV", REG_MMIO, 0x1700, NULL, 0, 0, 0 },
+	{ "mmPLL_REF_DIV", REG_MMIO, 0x1700, &mmPLL_REF_DIV[0], sizeof(mmPLL_REF_DIV)/sizeof(mmPLL_REF_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_FB_DIV", REG_MMIO, 0x1701, NULL, 0, 0, 0 },
+	{ "mmPLL_FB_DIV", REG_MMIO, 0x1701, &mmPLL_FB_DIV[0], sizeof(mmPLL_FB_DIV)/sizeof(mmPLL_FB_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_POST_DIV", REG_MMIO, 0x1702, NULL, 0, 0, 0 },
+	{ "mmPLL_POST_DIV", REG_MMIO, 0x1702, &mmPLL_POST_DIV[0], sizeof(mmPLL_POST_DIV)/sizeof(mmPLL_POST_DIV[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1703, NULL, 0, 0, 0 },
+	{ "mmPLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1703, &mmPLL_SS_AMOUNT_DSFRAC[0], sizeof(mmPLL_SS_AMOUNT_DSFRAC)/sizeof(mmPLL_SS_AMOUNT_DSFRAC[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_SS_CNTL", REG_MMIO, 0x1704, NULL, 0, 0, 0 },
+	{ "mmPLL_SS_CNTL", REG_MMIO, 0x1704, &mmPLL_SS_CNTL[0], sizeof(mmPLL_SS_CNTL)/sizeof(mmPLL_SS_CNTL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_SMC, 0x1705, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_DS_CNTL", REG_MMIO, 0x1705, NULL, 0, 0, 0 },
+	{ "mmPLL_DS_CNTL", REG_MMIO, 0x1705, &mmPLL_DS_CNTL[0], sizeof(mmPLL_DS_CNTL)/sizeof(mmPLL_DS_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_IDCLK_CNTL", REG_MMIO, 0x1706, NULL, 0, 0, 0 },
+	{ "mmPLL_IDCLK_CNTL", REG_MMIO, 0x1706, &mmPLL_IDCLK_CNTL[0], sizeof(mmPLL_IDCLK_CNTL)/sizeof(mmPLL_IDCLK_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_CNTL", REG_MMIO, 0x1707, NULL, 0, 0, 0 },
+	{ "mmPLL_CNTL", REG_MMIO, 0x1707, &mmPLL_CNTL[0], sizeof(mmPLL_CNTL)/sizeof(mmPLL_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_ANALOG", REG_MMIO, 0x1708, NULL, 0, 0, 0 },
+	{ "mmPLL_ANALOG", REG_MMIO, 0x1708, &mmPLL_ANALOG[0], sizeof(mmPLL_ANALOG)/sizeof(mmPLL_ANALOG[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_VREG_CNTL", REG_MMIO, 0x1709, NULL, 0, 0, 0 },
+	{ "mmPLL_VREG_CNTL", REG_MMIO, 0x1709, &mmPLL_VREG_CNTL[0], sizeof(mmPLL_VREG_CNTL)/sizeof(mmPLL_VREG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x170a, NULL, 0, 0, 0 },
+	{ "mmPLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x170a, &mmPLL_UNLOCK_DETECT_CNTL[0], sizeof(mmPLL_UNLOCK_DETECT_CNTL)/sizeof(mmPLL_UNLOCK_DETECT_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_DEBUG_CNTL", REG_MMIO, 0x170b, NULL, 0, 0, 0 },
+	{ "mmPLL_DEBUG_CNTL", REG_MMIO, 0x170b, &mmPLL_DEBUG_CNTL[0], sizeof(mmPLL_DEBUG_CNTL)/sizeof(mmPLL_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_UPDATE_LOCK", REG_MMIO, 0x170c, NULL, 0, 0, 0 },
+	{ "mmPLL_UPDATE_LOCK", REG_MMIO, 0x170c, &mmPLL_UPDATE_LOCK[0], sizeof(mmPLL_UPDATE_LOCK)/sizeof(mmPLL_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_UPDATE_CNTL", REG_MMIO, 0x170d, NULL, 0, 0, 0 },
+	{ "mmPLL_UPDATE_CNTL", REG_MMIO, 0x170d, &mmPLL_UPDATE_CNTL[0], sizeof(mmPLL_UPDATE_CNTL)/sizeof(mmPLL_UPDATE_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL", REG_MMIO, 0x170e, NULL, 0, 0, 0 },
+	{ "mmPLL_DISPCLK_DTO_CNTL", REG_MMIO, 0x170e, &mmPLL_DISPCLK_DTO_CNTL[0], sizeof(mmPLL_DISPCLK_DTO_CNTL)/sizeof(mmPLL_DISPCLK_DTO_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE", REG_MMIO, 0x170f, NULL, 0, 0, 0 },
+	{ "mmPLL_DISPCLK_CURRENT_DTO_PHASE", REG_MMIO, 0x170f, &mmPLL_DISPCLK_CURRENT_DTO_PHASE[0], sizeof(mmPLL_DISPCLK_CURRENT_DTO_PHASE)/sizeof(mmPLL_DISPCLK_CURRENT_DTO_PHASE[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFCOUNTER_STATE", REG_MMIO, 0x171, NULL, 0, 0, 0 },
+	{ "mmPERFCOUNTER_STATE", REG_MMIO, 0x171, &mmPERFCOUNTER_STATE[0], sizeof(mmPERFCOUNTER_STATE)/sizeof(mmPERFCOUNTER_STATE[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_XOR_LOCK", REG_MMIO, 0x1710, NULL, 0, 0, 0 },
+	{ "mmPLL_XOR_LOCK", REG_MMIO, 0x1710, &mmPLL_XOR_LOCK[0], sizeof(mmPLL_XOR_LOCK)/sizeof(mmPLL_XOR_LOCK[0]), 0, 0 },
+	{ "mmDCCG_PLL0_PLL_ANALOG_CNTL", REG_MMIO, 0x1711, NULL, 0, 0, 0 },
+	{ "mmPLL_ANALOG_CNTL", REG_MMIO, 0x1711, &mmPLL_ANALOG_CNTL[0], sizeof(mmPLL_ANALOG_CNTL)/sizeof(mmPLL_ANALOG_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_REF_DIV", REG_MMIO, 0x1714, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_FB_DIV", REG_MMIO, 0x1715, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_POST_DIV", REG_MMIO, 0x1716, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x1717, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_SS_CNTL", REG_MMIO, 0x1718, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_DS_CNTL", REG_MMIO, 0x1719, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_IDCLK_CNTL", REG_MMIO, 0x171a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_CNTL", REG_MMIO, 0x171b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_ANALOG", REG_MMIO, 0x171c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_VREG_CNTL", REG_MMIO, 0x171d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x171e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_DEBUG_CNTL", REG_MMIO, 0x171f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x172, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CVALUE_INT_MISC", REG_MMIO, 0x172, &mmPERFMON_CVALUE_INT_MISC[0], sizeof(mmPERFMON_CVALUE_INT_MISC)/sizeof(mmPERFMON_CVALUE_INT_MISC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_SMC, 0x1720, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_UPDATE_LOCK", REG_MMIO, 0x1720, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2", REG_SMC, 0x1721, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_UPDATE_CNTL", REG_MMIO, 0x1721, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3", REG_SMC, 0x1722, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL", REG_MMIO, 0x1722, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4", REG_SMC, 0x1723, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4[0]), 0, 0 },
+	{ "mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE", REG_MMIO, 0x1723, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_XOR_LOCK", REG_MMIO, 0x1724, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL1_PLL_ANALOG_CNTL", REG_MMIO, 0x1725, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_REF_DIV", REG_MMIO, 0x1728, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_FB_DIV", REG_MMIO, 0x1729, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_POST_DIV", REG_MMIO, 0x172a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x172b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_SS_CNTL", REG_MMIO, 0x172c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_DS_CNTL", REG_MMIO, 0x172d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_IDCLK_CNTL", REG_MMIO, 0x172e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_CNTL", REG_MMIO, 0x172f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CNTL", REG_MMIO, 0x173, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CNTL", REG_MMIO, 0x173, &mmPERFMON_CNTL[0], sizeof(mmPERFMON_CNTL)/sizeof(mmPERFMON_CNTL[0]), 0, 0 },
+	{ "mmDCCG_PLL2_PLL_ANALOG", REG_MMIO, 0x1730, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_VREG_CNTL", REG_MMIO, 0x1731, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x1732, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_DEBUG_CNTL", REG_MMIO, 0x1733, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_UPDATE_LOCK", REG_MMIO, 0x1734, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_UPDATE_CNTL", REG_MMIO, 0x1735, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL", REG_MMIO, 0x1736, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE", REG_MMIO, 0x1737, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_XOR_LOCK", REG_MMIO, 0x1738, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL2_PLL_ANALOG_CNTL", REG_MMIO, 0x1739, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_REF_DIV", REG_MMIO, 0x173c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_FB_DIV", REG_MMIO, 0x173d, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_POST_DIV", REG_MMIO, 0x173e, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_SS_AMOUNT_DSFRAC", REG_MMIO, 0x173f, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_CVALUE_LOW", REG_MMIO, 0x174, NULL, 0, 0, 0 },
+	{ "mmPERFMON_CVALUE_LOW", REG_MMIO, 0x174, &mmPERFMON_CVALUE_LOW[0], sizeof(mmPERFMON_CVALUE_LOW)/sizeof(mmPERFMON_CVALUE_LOW[0]), 0, 0 },
+	{ "mmDCCG_PLL3_PLL_SS_CNTL", REG_MMIO, 0x1740, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_DS_CNTL", REG_MMIO, 0x1741, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_IDCLK_CNTL", REG_MMIO, 0x1742, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_CNTL", REG_MMIO, 0x1743, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_ANALOG", REG_MMIO, 0x1744, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_VREG_CNTL", REG_MMIO, 0x1745, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_UNLOCK_DETECT_CNTL", REG_MMIO, 0x1746, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_DEBUG_CNTL", REG_MMIO, 0x1747, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_UPDATE_LOCK", REG_MMIO, 0x1748, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_UPDATE_CNTL", REG_MMIO, 0x1749, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_DISPCLK_DTO_CNTL", REG_MMIO, 0x174a, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_DISPCLK_CURRENT_DTO_PHASE", REG_MMIO, 0x174b, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_XOR_LOCK", REG_MMIO, 0x174c, NULL, 0, 0, 0 },
+	{ "mmDCCG_PLL3_PLL_ANALOG_CNTL", REG_MMIO, 0x174d, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_HI", REG_MMIO, 0x175, NULL, 0, 0, 0 },
+	{ "mmPERFMON_HI", REG_MMIO, 0x175, &mmPERFMON_HI[0], sizeof(mmPERFMON_HI)/sizeof(mmPERFMON_HI[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS1", REG_MMIO, 0x1750, &mmDMCU_PERFMON_INTERRUPT_STATUS1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS2", REG_MMIO, 0x1751, &mmDMCU_PERFMON_INTERRUPT_STATUS2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS3", REG_MMIO, 0x1752, &mmDMCU_PERFMON_INTERRUPT_STATUS3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_STATUS4", REG_MMIO, 0x1753, &mmDMCU_PERFMON_INTERRUPT_STATUS4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4)/sizeof(mmDMCU_PERFMON_INTERRUPT_STATUS4[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1", REG_MMIO, 0x1754, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2", REG_MMIO, 0x1755, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3", REG_MMIO, 0x1756, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4", REG_MMIO, 0x1757, &mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1", REG_MMIO, 0x1758, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2", REG_MMIO, 0x1759, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3", REG_MMIO, 0x175a, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4", REG_MMIO, 0x175b, &mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1", REG_MMIO, 0x175c, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK1[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2", REG_MMIO, 0x175d, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK2[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3", REG_MMIO, 0x175e, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK3[0]), 0, 0 },
+	{ "mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4", REG_MMIO, 0x175f, &mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4[0], sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4)/sizeof(mmDMCU_PERFMON_INTERRUPT_TO_HOST_EN_MASK4[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_LOW", REG_MMIO, 0x176, NULL, 0, 0, 0 },
+	{ "mmPERFMON_LOW", REG_MMIO, 0x176, &mmPERFMON_LOW[0], sizeof(mmPERFMON_LOW)/sizeof(mmPERFMON_LOW[0]), 0, 0 },
+	{ "mmPIPE0_PG_CONFIG", REG_MMIO, 0x1760, &mmPIPE0_PG_CONFIG[0], sizeof(mmPIPE0_PG_CONFIG)/sizeof(mmPIPE0_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE0_PG_ENABLE", REG_MMIO, 0x1761, &mmPIPE0_PG_ENABLE[0], sizeof(mmPIPE0_PG_ENABLE)/sizeof(mmPIPE0_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE0_PG_STATUS", REG_MMIO, 0x1762, &mmPIPE0_PG_STATUS[0], sizeof(mmPIPE0_PG_STATUS)/sizeof(mmPIPE0_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE1_PG_CONFIG", REG_MMIO, 0x1764, &mmPIPE1_PG_CONFIG[0], sizeof(mmPIPE1_PG_CONFIG)/sizeof(mmPIPE1_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE1_PG_ENABLE", REG_MMIO, 0x1765, &mmPIPE1_PG_ENABLE[0], sizeof(mmPIPE1_PG_ENABLE)/sizeof(mmPIPE1_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE1_PG_STATUS", REG_MMIO, 0x1766, &mmPIPE1_PG_STATUS[0], sizeof(mmPIPE1_PG_STATUS)/sizeof(mmPIPE1_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE2_PG_CONFIG", REG_MMIO, 0x1768, &mmPIPE2_PG_CONFIG[0], sizeof(mmPIPE2_PG_CONFIG)/sizeof(mmPIPE2_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE2_PG_ENABLE", REG_MMIO, 0x1769, &mmPIPE2_PG_ENABLE[0], sizeof(mmPIPE2_PG_ENABLE)/sizeof(mmPIPE2_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE2_PG_STATUS", REG_MMIO, 0x176a, &mmPIPE2_PG_STATUS[0], sizeof(mmPIPE2_PG_STATUS)/sizeof(mmPIPE2_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE3_PG_CONFIG", REG_MMIO, 0x176c, &mmPIPE3_PG_CONFIG[0], sizeof(mmPIPE3_PG_CONFIG)/sizeof(mmPIPE3_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE3_PG_ENABLE", REG_MMIO, 0x176d, &mmPIPE3_PG_ENABLE[0], sizeof(mmPIPE3_PG_ENABLE)/sizeof(mmPIPE3_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE3_PG_STATUS", REG_MMIO, 0x176e, &mmPIPE3_PG_STATUS[0], sizeof(mmPIPE3_PG_STATUS)/sizeof(mmPIPE3_PG_STATUS[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x177, NULL, 0, 0, 0 },
+	{ "mmPERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x177, &mmPERFMON_TEST_DEBUG_INDEX[0], sizeof(mmPERFMON_TEST_DEBUG_INDEX)/sizeof(mmPERFMON_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_SMC, 0x1770, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmPIPE4_PG_CONFIG", REG_MMIO, 0x1770, &mmPIPE4_PG_CONFIG[0], sizeof(mmPIPE4_PG_CONFIG)/sizeof(mmPIPE4_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE4_PG_ENABLE", REG_MMIO, 0x1771, &mmPIPE4_PG_ENABLE[0], sizeof(mmPIPE4_PG_ENABLE)/sizeof(mmPIPE4_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE4_PG_STATUS", REG_MMIO, 0x1772, &mmPIPE4_PG_STATUS[0], sizeof(mmPIPE4_PG_STATUS)/sizeof(mmPIPE4_PG_STATUS[0]), 0, 0 },
+	{ "mmPIPE5_PG_CONFIG", REG_MMIO, 0x1774, &mmPIPE5_PG_CONFIG[0], sizeof(mmPIPE5_PG_CONFIG)/sizeof(mmPIPE5_PG_CONFIG[0]), 0, 0 },
+	{ "mmPIPE5_PG_ENABLE", REG_MMIO, 0x1775, &mmPIPE5_PG_ENABLE[0], sizeof(mmPIPE5_PG_ENABLE)/sizeof(mmPIPE5_PG_ENABLE[0]), 0, 0 },
+	{ "mmPIPE5_PG_STATUS", REG_MMIO, 0x1776, &mmPIPE5_PG_STATUS[0], sizeof(mmPIPE5_PG_STATUS)/sizeof(mmPIPE5_PG_STATUS[0]), 0, 0 },
+	{ "mmDC_IP_REQUEST_CNTL", REG_MMIO, 0x1778, &mmDC_IP_REQUEST_CNTL[0], sizeof(mmDC_IP_REQUEST_CNTL)/sizeof(mmDC_IP_REQUEST_CNTL[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1779, &mmDCPG_TEST_DEBUG_INDEX[0], sizeof(mmDCPG_TEST_DEBUG_INDEX)/sizeof(mmDCPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCPG_TEST_DEBUG_DATA", REG_MMIO, 0x177b, &mmDCPG_TEST_DEBUG_DATA[0], sizeof(mmDCPG_TEST_DEBUG_DATA)/sizeof(mmDCPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDC_PGFSM_CONFIG_REG", REG_MMIO, 0x177c, &mmDC_PGFSM_CONFIG_REG[0], sizeof(mmDC_PGFSM_CONFIG_REG)/sizeof(mmDC_PGFSM_CONFIG_REG[0]), 0, 0 },
+	{ "mmDC_PGFSM_WRITE_REG", REG_MMIO, 0x177d, &mmDC_PGFSM_WRITE_REG[0], sizeof(mmDC_PGFSM_WRITE_REG)/sizeof(mmDC_PGFSM_WRITE_REG[0]), 0, 0 },
+	{ "mmDC_PGCNTL_STATUS_REG", REG_MMIO, 0x177e, &mmDC_PGCNTL_STATUS_REG[0], sizeof(mmDC_PGCNTL_STATUS_REG)/sizeof(mmDC_PGCNTL_STATUS_REG[0]), 0, 0 },
+	{ "mmCC_DC_PIPE_DIS", REG_MMIO, 0x177f, &mmCC_DC_PIPE_DIS[0], sizeof(mmCC_DC_PIPE_DIS)/sizeof(mmCC_DC_PIPE_DIS[0]), 0, 0 },
+	{ "mmDC_PERFMON0_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x178, NULL, 0, 0, 0 },
+	{ "mmPERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x178, &mmPERFMON_TEST_DEBUG_DATA[0], sizeof(mmPERFMON_TEST_DEBUG_DATA)/sizeof(mmPERFMON_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1780, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1780, &mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_INDEX[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1781, NULL, 0, 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1781, &mmAZALIA_F0_CODEC_ENDPOINT_DATA[0], sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA)/sizeof(mmAZALIA_F0_CODEC_ENDPOINT_DATA[0]), 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1786, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1787, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x178c, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x178d, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1792, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1793, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x1798, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x1799, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x179e, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x179f, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX", REG_MMIO, 0x17a4, NULL, 0, 0, 0 },
+	{ "mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA", REG_MMIO, 0x17a5, NULL, 0, 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL0", REG_MMIO, 0x17ae, &mmAZALIA_CRC0_CONTROL0[0], sizeof(mmAZALIA_CRC0_CONTROL0)/sizeof(mmAZALIA_CRC0_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL1", REG_MMIO, 0x17af, &mmAZALIA_CRC0_CONTROL1[0], sizeof(mmAZALIA_CRC0_CONTROL1)/sizeof(mmAZALIA_CRC0_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL2", REG_MMIO, 0x17b0, &mmAZALIA_CRC0_CONTROL2[0], sizeof(mmAZALIA_CRC0_CONTROL2)/sizeof(mmAZALIA_CRC0_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_CONTROL3", REG_MMIO, 0x17b1, &mmAZALIA_CRC0_CONTROL3[0], sizeof(mmAZALIA_CRC0_CONTROL3)/sizeof(mmAZALIA_CRC0_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_CRC0_RESULT", REG_MMIO, 0x17b2, &mmAZALIA_CRC0_RESULT[0], sizeof(mmAZALIA_CRC0_RESULT)/sizeof(mmAZALIA_CRC0_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL0", REG_MMIO, 0x17b3, &mmAZALIA_CRC1_CONTROL0[0], sizeof(mmAZALIA_CRC1_CONTROL0)/sizeof(mmAZALIA_CRC1_CONTROL0[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL1", REG_MMIO, 0x17b4, &mmAZALIA_CRC1_CONTROL1[0], sizeof(mmAZALIA_CRC1_CONTROL1)/sizeof(mmAZALIA_CRC1_CONTROL1[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL2", REG_MMIO, 0x17b5, &mmAZALIA_CRC1_CONTROL2[0], sizeof(mmAZALIA_CRC1_CONTROL2)/sizeof(mmAZALIA_CRC1_CONTROL2[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_CONTROL3", REG_MMIO, 0x17b6, &mmAZALIA_CRC1_CONTROL3[0], sizeof(mmAZALIA_CRC1_CONTROL3)/sizeof(mmAZALIA_CRC1_CONTROL3[0]), 0, 0 },
+	{ "mmAZALIA_CRC1_RESULT", REG_MMIO, 0x17b7, &mmAZALIA_CRC1_RESULT[0], sizeof(mmAZALIA_CRC1_RESULT)/sizeof(mmAZALIA_CRC1_RESULT[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_CLOCK_GATING", REG_MMIO, 0x17b9, &mmAZALIA_CONTROLLER_CLOCK_GATING[0], sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING)/sizeof(mmAZALIA_CONTROLLER_CLOCK_GATING[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO", REG_MMIO, 0x17ba, &mmAZALIA_AUDIO_DTO[0], sizeof(mmAZALIA_AUDIO_DTO)/sizeof(mmAZALIA_AUDIO_DTO[0]), 0, 0 },
+	{ "mmAZALIA_AUDIO_DTO_CONTROL", REG_MMIO, 0x17bb, &mmAZALIA_AUDIO_DTO_CONTROL[0], sizeof(mmAZALIA_AUDIO_DTO_CONTROL)/sizeof(mmAZALIA_AUDIO_DTO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_SCLK_CONTROL", REG_MMIO, 0x17bc, &mmAZALIA_SCLK_CONTROL[0], sizeof(mmAZALIA_SCLK_CONTROL)/sizeof(mmAZALIA_SCLK_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_UNDERFLOW_FILLER_SAMPLE", REG_MMIO, 0x17bd, &mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0], sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE)/sizeof(mmAZALIA_UNDERFLOW_FILLER_SAMPLE[0]), 0, 0 },
+	{ "mmAZALIA_DATA_DMA_CONTROL", REG_MMIO, 0x17be, &mmAZALIA_DATA_DMA_CONTROL[0], sizeof(mmAZALIA_DATA_DMA_CONTROL)/sizeof(mmAZALIA_DATA_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_BDL_DMA_CONTROL", REG_MMIO, 0x17bf, &mmAZALIA_BDL_DMA_CONTROL[0], sizeof(mmAZALIA_BDL_DMA_CONTROL)/sizeof(mmAZALIA_BDL_DMA_CONTROL[0]), 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_INDEX", REG_MMIO, 0x17c, &mmDCCG_TEST_DEBUG_INDEX[0], sizeof(mmDCCG_TEST_DEBUG_INDEX)/sizeof(mmDCCG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZALIA_RIRB_AND_DP_CONTROL", REG_MMIO, 0x17c0, &mmAZALIA_RIRB_AND_DP_CONTROL[0], sizeof(mmAZALIA_RIRB_AND_DP_CONTROL)/sizeof(mmAZALIA_RIRB_AND_DP_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_CORB_DMA_CONTROL", REG_MMIO, 0x17c1, &mmAZALIA_CORB_DMA_CONTROL[0], sizeof(mmAZALIA_CORB_DMA_CONTROL)/sizeof(mmAZALIA_CORB_DMA_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER", REG_MMIO, 0x17c9, &mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0], sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER)/sizeof(mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER[0]), 0, 0 },
+	{ "mmAZALIA_CYCLIC_BUFFER_SYNC", REG_MMIO, 0x17ca, &mmAZALIA_CYCLIC_BUFFER_SYNC[0], sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC)/sizeof(mmAZALIA_CYCLIC_BUFFER_SYNC[0]), 0, 0 },
+	{ "mmAZALIA_GLOBAL_CAPABILITIES", REG_MMIO, 0x17cb, &mmAZALIA_GLOBAL_CAPABILITIES[0], sizeof(mmAZALIA_GLOBAL_CAPABILITIES)/sizeof(mmAZALIA_GLOBAL_CAPABILITIES[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY", REG_MMIO, 0x17cc, &mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0], sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY)/sizeof(mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL", REG_MMIO, 0x17cd, &mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0], sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL)/sizeof(mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_CONTROLLER_DEBUG", REG_MMIO, 0x17cf, &mmAZALIA_CONTROLLER_DEBUG[0], sizeof(mmAZALIA_CONTROLLER_DEBUG)/sizeof(mmAZALIA_CONTROLLER_DEBUG[0]), 0, 0 },
+	{ "mmDCCG_TEST_DEBUG_DATA", REG_MMIO, 0x17d, &mmDCCG_TEST_DEBUG_DATA[0], sizeof(mmDCCG_TEST_DEBUG_DATA)/sizeof(mmDCCG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_INDEX", REG_MMIO, 0x17d0, &mmAZ_TEST_DEBUG_INDEX[0], sizeof(mmAZ_TEST_DEBUG_INDEX)/sizeof(mmAZ_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmAZ_TEST_DEBUG_DATA", REG_MMIO, 0x17d1, &mmAZ_TEST_DEBUG_DATA[0], sizeof(mmAZ_TEST_DEBUG_DATA)/sizeof(mmAZ_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_MMIO, 0x17d2, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID", REG_MMIO, 0x17d3, &mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY", REG_MMIO, 0x17d4, &mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0], sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY)/sizeof(mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL", REG_MMIO, 0x17d5, &mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL)/sizeof(mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL", REG_MMIO, 0x17d6, &mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0], sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL)/sizeof(mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_MMIO, 0x17d7, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_MMIO, 0x17d8, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_MMIO, 0x17d9, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_MMIO, 0x17da, &mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE", REG_MMIO, 0x17db, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET", REG_MMIO, 0x17dc, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID", REG_MMIO, 0x17dd, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION", REG_MMIO, 0x17de, &mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0], sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION)/sizeof(mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmAZALIA_F0_CODEC_DEBUG", REG_MMIO, 0x17df, &mmAZALIA_F0_CODEC_DEBUG[0], sizeof(mmAZALIA_F0_CODEC_DEBUG)/sizeof(mmAZALIA_F0_CODEC_DEBUG[0]), 0, 0 },
+	{ "mmDCCG_TEST_CLK_SEL", REG_MMIO, 0x17e, &mmDCCG_TEST_CLK_SEL[0], sizeof(mmDCCG_TEST_CLK_SEL)/sizeof(mmDCCG_TEST_CLK_SEL[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET0", REG_MMIO, 0x17e1, &mmAZALIA_F0_GTC_GROUP_OFFSET0[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET0[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET1", REG_MMIO, 0x17e2, &mmAZALIA_F0_GTC_GROUP_OFFSET1[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET1[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET2", REG_MMIO, 0x17e3, &mmAZALIA_F0_GTC_GROUP_OFFSET2[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET2[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET3", REG_MMIO, 0x17e4, &mmAZALIA_F0_GTC_GROUP_OFFSET3[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET3[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET4", REG_MMIO, 0x17e5, &mmAZALIA_F0_GTC_GROUP_OFFSET4[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET4[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET5", REG_MMIO, 0x17e6, &mmAZALIA_F0_GTC_GROUP_OFFSET5[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET5[0]), 0, 0 },
+	{ "mmAZALIA_F0_GTC_GROUP_OFFSET6", REG_MMIO, 0x17e7, &mmAZALIA_F0_GTC_GROUP_OFFSET6[0], sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6)/sizeof(mmAZALIA_F0_GTC_GROUP_OFFSET6[0]), 0, 0 },
+	{ "mmAZF0STREAM0_AZALIA_STREAM_INDEX", REG_MMIO, 0x17e8, NULL, 0, 0, 0 },
+	{ "mmAZALIA_STREAM_INDEX", REG_MMIO, 0x17e8, &mmAZALIA_STREAM_INDEX[0], sizeof(mmAZALIA_STREAM_INDEX)/sizeof(mmAZALIA_STREAM_INDEX[0]), 0, 0 },
+	{ "mmAZF0STREAM0_AZALIA_STREAM_DATA", REG_MMIO, 0x17e9, NULL, 0, 0, 0 },
+	{ "mmAZALIA_STREAM_DATA", REG_MMIO, 0x17e9, &mmAZALIA_STREAM_DATA[0], sizeof(mmAZALIA_STREAM_DATA)/sizeof(mmAZALIA_STREAM_DATA[0]), 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_INDEX", REG_MMIO, 0x17ec, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM1_AZALIA_STREAM_DATA", REG_MMIO, 0x17ed, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_INDEX", REG_MMIO, 0x17f0, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM2_AZALIA_STREAM_DATA", REG_MMIO, 0x17f1, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_INDEX", REG_MMIO, 0x17f4, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM3_AZALIA_STREAM_DATA", REG_MMIO, 0x17f5, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_INDEX", REG_MMIO, 0x17f8, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM4_AZALIA_STREAM_DATA", REG_MMIO, 0x17f9, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_INDEX", REG_MMIO, 0x17fc, NULL, 0, 0, 0 },
+	{ "mmAZF0STREAM5_AZALIA_STREAM_DATA", REG_MMIO, 0x17fd, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET", REG_SMC, 0x17ff, &ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE", REG_MMIO, 0x18, &mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0], sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE)/sizeof(mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_I", REG_SMC, 0x18, &ixDP_AUX1_DEBUG_I[0], sizeof(ixDP_AUX1_DEBUG_I)/sizeof(ixDP_AUX1_DEBUG_I[0]), 0, 0 },
+	{ "ixCRT18", REG_SMC, 0x18, &ixCRT18[0], sizeof(ixCRT18)/sizeof(ixCRT18[0]), 0, 0 },
+	{ "mmDC_HPD1_INT_STATUS", REG_MMIO, 0x1807, &mmDC_HPD1_INT_STATUS[0], sizeof(mmDC_HPD1_INT_STATUS)/sizeof(mmDC_HPD1_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD1_INT_CONTROL", REG_MMIO, 0x1808, &mmDC_HPD1_INT_CONTROL[0], sizeof(mmDC_HPD1_INT_CONTROL)/sizeof(mmDC_HPD1_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD1_CONTROL", REG_MMIO, 0x1809, &mmDC_HPD1_CONTROL[0], sizeof(mmDC_HPD1_CONTROL)/sizeof(mmDC_HPD1_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD2_INT_STATUS", REG_MMIO, 0x180a, &mmDC_HPD2_INT_STATUS[0], sizeof(mmDC_HPD2_INT_STATUS)/sizeof(mmDC_HPD2_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD2_INT_CONTROL", REG_MMIO, 0x180b, &mmDC_HPD2_INT_CONTROL[0], sizeof(mmDC_HPD2_INT_CONTROL)/sizeof(mmDC_HPD2_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD2_CONTROL", REG_MMIO, 0x180c, &mmDC_HPD2_CONTROL[0], sizeof(mmDC_HPD2_CONTROL)/sizeof(mmDC_HPD2_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD3_INT_STATUS", REG_MMIO, 0x180d, &mmDC_HPD3_INT_STATUS[0], sizeof(mmDC_HPD3_INT_STATUS)/sizeof(mmDC_HPD3_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD3_INT_CONTROL", REG_MMIO, 0x180e, &mmDC_HPD3_INT_CONTROL[0], sizeof(mmDC_HPD3_INT_CONTROL)/sizeof(mmDC_HPD3_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD3_CONTROL", REG_MMIO, 0x180f, &mmDC_HPD3_CONTROL[0], sizeof(mmDC_HPD3_CONTROL)/sizeof(mmDC_HPD3_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD4_INT_STATUS", REG_MMIO, 0x1810, &mmDC_HPD4_INT_STATUS[0], sizeof(mmDC_HPD4_INT_STATUS)/sizeof(mmDC_HPD4_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD4_INT_CONTROL", REG_MMIO, 0x1811, &mmDC_HPD4_INT_CONTROL[0], sizeof(mmDC_HPD4_INT_CONTROL)/sizeof(mmDC_HPD4_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD4_CONTROL", REG_MMIO, 0x1812, &mmDC_HPD4_CONTROL[0], sizeof(mmDC_HPD4_CONTROL)/sizeof(mmDC_HPD4_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD5_INT_STATUS", REG_MMIO, 0x1813, &mmDC_HPD5_INT_STATUS[0], sizeof(mmDC_HPD5_INT_STATUS)/sizeof(mmDC_HPD5_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD5_INT_CONTROL", REG_MMIO, 0x1814, &mmDC_HPD5_INT_CONTROL[0], sizeof(mmDC_HPD5_INT_CONTROL)/sizeof(mmDC_HPD5_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD5_CONTROL", REG_MMIO, 0x1815, &mmDC_HPD5_CONTROL[0], sizeof(mmDC_HPD5_CONTROL)/sizeof(mmDC_HPD5_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD6_INT_STATUS", REG_MMIO, 0x1816, &mmDC_HPD6_INT_STATUS[0], sizeof(mmDC_HPD6_INT_STATUS)/sizeof(mmDC_HPD6_INT_STATUS[0]), 0, 0 },
+	{ "mmDC_HPD6_INT_CONTROL", REG_MMIO, 0x1817, &mmDC_HPD6_INT_CONTROL[0], sizeof(mmDC_HPD6_INT_CONTROL)/sizeof(mmDC_HPD6_INT_CONTROL[0]), 0, 0 },
+	{ "mmDC_HPD6_CONTROL", REG_MMIO, 0x1818, &mmDC_HPD6_CONTROL[0], sizeof(mmDC_HPD6_CONTROL)/sizeof(mmDC_HPD6_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_CONTROL", REG_MMIO, 0x1819, &mmDC_I2C_CONTROL[0], sizeof(mmDC_I2C_CONTROL)/sizeof(mmDC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_ARBITRATION", REG_MMIO, 0x181a, &mmDC_I2C_ARBITRATION[0], sizeof(mmDC_I2C_ARBITRATION)/sizeof(mmDC_I2C_ARBITRATION[0]), 0, 0 },
+	{ "mmDC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x181b, &mmDC_I2C_INTERRUPT_CONTROL[0], sizeof(mmDC_I2C_INTERRUPT_CONTROL)/sizeof(mmDC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDC_I2C_SW_STATUS", REG_MMIO, 0x181c, &mmDC_I2C_SW_STATUS[0], sizeof(mmDC_I2C_SW_STATUS)/sizeof(mmDC_I2C_SW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_HW_STATUS", REG_MMIO, 0x181d, &mmDC_I2C_DDC1_HW_STATUS[0], sizeof(mmDC_I2C_DDC1_HW_STATUS)/sizeof(mmDC_I2C_DDC1_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_HW_STATUS", REG_MMIO, 0x181e, &mmDC_I2C_DDC2_HW_STATUS[0], sizeof(mmDC_I2C_DDC2_HW_STATUS)/sizeof(mmDC_I2C_DDC2_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_HW_STATUS", REG_MMIO, 0x181f, &mmDC_I2C_DDC3_HW_STATUS[0], sizeof(mmDC_I2C_DDC3_HW_STATUS)/sizeof(mmDC_I2C_DDC3_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_HW_STATUS", REG_MMIO, 0x1820, &mmDC_I2C_DDC4_HW_STATUS[0], sizeof(mmDC_I2C_DDC4_HW_STATUS)/sizeof(mmDC_I2C_DDC4_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_HW_STATUS", REG_MMIO, 0x1821, &mmDC_I2C_DDC5_HW_STATUS[0], sizeof(mmDC_I2C_DDC5_HW_STATUS)/sizeof(mmDC_I2C_DDC5_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_HW_STATUS", REG_MMIO, 0x1822, &mmDC_I2C_DDC6_HW_STATUS[0], sizeof(mmDC_I2C_DDC6_HW_STATUS)/sizeof(mmDC_I2C_DDC6_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SPEED", REG_MMIO, 0x1823, &mmDC_I2C_DDC1_SPEED[0], sizeof(mmDC_I2C_DDC1_SPEED)/sizeof(mmDC_I2C_DDC1_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC1_SETUP", REG_MMIO, 0x1824, &mmDC_I2C_DDC1_SETUP[0], sizeof(mmDC_I2C_DDC1_SETUP)/sizeof(mmDC_I2C_DDC1_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SPEED", REG_MMIO, 0x1825, &mmDC_I2C_DDC2_SPEED[0], sizeof(mmDC_I2C_DDC2_SPEED)/sizeof(mmDC_I2C_DDC2_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC2_SETUP", REG_MMIO, 0x1826, &mmDC_I2C_DDC2_SETUP[0], sizeof(mmDC_I2C_DDC2_SETUP)/sizeof(mmDC_I2C_DDC2_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SPEED", REG_MMIO, 0x1827, &mmDC_I2C_DDC3_SPEED[0], sizeof(mmDC_I2C_DDC3_SPEED)/sizeof(mmDC_I2C_DDC3_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC3_SETUP", REG_MMIO, 0x1828, &mmDC_I2C_DDC3_SETUP[0], sizeof(mmDC_I2C_DDC3_SETUP)/sizeof(mmDC_I2C_DDC3_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SPEED", REG_MMIO, 0x1829, &mmDC_I2C_DDC4_SPEED[0], sizeof(mmDC_I2C_DDC4_SPEED)/sizeof(mmDC_I2C_DDC4_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC4_SETUP", REG_MMIO, 0x182a, &mmDC_I2C_DDC4_SETUP[0], sizeof(mmDC_I2C_DDC4_SETUP)/sizeof(mmDC_I2C_DDC4_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SPEED", REG_MMIO, 0x182b, &mmDC_I2C_DDC5_SPEED[0], sizeof(mmDC_I2C_DDC5_SPEED)/sizeof(mmDC_I2C_DDC5_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC5_SETUP", REG_MMIO, 0x182c, &mmDC_I2C_DDC5_SETUP[0], sizeof(mmDC_I2C_DDC5_SETUP)/sizeof(mmDC_I2C_DDC5_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SPEED", REG_MMIO, 0x182d, &mmDC_I2C_DDC6_SPEED[0], sizeof(mmDC_I2C_DDC6_SPEED)/sizeof(mmDC_I2C_DDC6_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDC6_SETUP", REG_MMIO, 0x182e, &mmDC_I2C_DDC6_SETUP[0], sizeof(mmDC_I2C_DDC6_SETUP)/sizeof(mmDC_I2C_DDC6_SETUP[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION0", REG_MMIO, 0x182f, &mmDC_I2C_TRANSACTION0[0], sizeof(mmDC_I2C_TRANSACTION0)/sizeof(mmDC_I2C_TRANSACTION0[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION1", REG_MMIO, 0x1830, &mmDC_I2C_TRANSACTION1[0], sizeof(mmDC_I2C_TRANSACTION1)/sizeof(mmDC_I2C_TRANSACTION1[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION2", REG_MMIO, 0x1831, &mmDC_I2C_TRANSACTION2[0], sizeof(mmDC_I2C_TRANSACTION2)/sizeof(mmDC_I2C_TRANSACTION2[0]), 0, 0 },
+	{ "mmDC_I2C_TRANSACTION3", REG_MMIO, 0x1832, &mmDC_I2C_TRANSACTION3[0], sizeof(mmDC_I2C_TRANSACTION3)/sizeof(mmDC_I2C_TRANSACTION3[0]), 0, 0 },
+	{ "mmDC_I2C_DATA", REG_MMIO, 0x1833, &mmDC_I2C_DATA[0], sizeof(mmDC_I2C_DATA)/sizeof(mmDC_I2C_DATA[0]), 0, 0 },
+	{ "mmGENERIC_I2C_CONTROL", REG_MMIO, 0x1834, &mmGENERIC_I2C_CONTROL[0], sizeof(mmGENERIC_I2C_CONTROL)/sizeof(mmGENERIC_I2C_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_INTERRUPT_CONTROL", REG_MMIO, 0x1835, &mmGENERIC_I2C_INTERRUPT_CONTROL[0], sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL)/sizeof(mmGENERIC_I2C_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmGENERIC_I2C_STATUS", REG_MMIO, 0x1836, &mmGENERIC_I2C_STATUS[0], sizeof(mmGENERIC_I2C_STATUS)/sizeof(mmGENERIC_I2C_STATUS[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SPEED", REG_MMIO, 0x1837, &mmGENERIC_I2C_SPEED[0], sizeof(mmGENERIC_I2C_SPEED)/sizeof(mmGENERIC_I2C_SPEED[0]), 0, 0 },
+	{ "mmGENERIC_I2C_SETUP", REG_MMIO, 0x1838, &mmGENERIC_I2C_SETUP[0], sizeof(mmGENERIC_I2C_SETUP)/sizeof(mmGENERIC_I2C_SETUP[0]), 0, 0 },
+	{ "mmGENERIC_I2C_TRANSACTION", REG_MMIO, 0x1839, &mmGENERIC_I2C_TRANSACTION[0], sizeof(mmGENERIC_I2C_TRANSACTION)/sizeof(mmGENERIC_I2C_TRANSACTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_DATA", REG_MMIO, 0x183a, &mmGENERIC_I2C_DATA[0], sizeof(mmGENERIC_I2C_DATA)/sizeof(mmGENERIC_I2C_DATA[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_SELECTION", REG_MMIO, 0x183b, &mmGENERIC_I2C_PIN_SELECTION[0], sizeof(mmGENERIC_I2C_PIN_SELECTION)/sizeof(mmGENERIC_I2C_PIN_SELECTION[0]), 0, 0 },
+	{ "mmGENERIC_I2C_PIN_DEBUG", REG_MMIO, 0x183c, &mmGENERIC_I2C_PIN_DEBUG[0], sizeof(mmGENERIC_I2C_PIN_DEBUG)/sizeof(mmGENERIC_I2C_PIN_DEBUG[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS", REG_MMIO, 0x183d, &mmDISP_INTERRUPT_STATUS[0], sizeof(mmDISP_INTERRUPT_STATUS)/sizeof(mmDISP_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE", REG_MMIO, 0x183e, &mmDISP_INTERRUPT_STATUS_CONTINUE[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE2", REG_MMIO, 0x183f, &mmDISP_INTERRUPT_STATUS_CONTINUE2[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE2[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE3", REG_MMIO, 0x1840, &mmDISP_INTERRUPT_STATUS_CONTINUE3[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE3[0]), 0, 0 },
+	{ "mmDOUT_POWER_MANAGEMENT_CNTL", REG_MMIO, 0x1841, &mmDOUT_POWER_MANAGEMENT_CNTL[0], sizeof(mmDOUT_POWER_MANAGEMENT_CNTL)/sizeof(mmDOUT_POWER_MANAGEMENT_CNTL[0]), 0, 0 },
+	{ "mmDISP_TIMER_CONTROL", REG_MMIO, 0x1842, &mmDISP_TIMER_CONTROL[0], sizeof(mmDISP_TIMER_CONTROL)/sizeof(mmDISP_TIMER_CONTROL[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH0", REG_MMIO, 0x1844, &mmDOUT_SCRATCH0[0], sizeof(mmDOUT_SCRATCH0)/sizeof(mmDOUT_SCRATCH0[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH1", REG_MMIO, 0x1845, &mmDOUT_SCRATCH1[0], sizeof(mmDOUT_SCRATCH1)/sizeof(mmDOUT_SCRATCH1[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH2", REG_MMIO, 0x1846, &mmDOUT_SCRATCH2[0], sizeof(mmDOUT_SCRATCH2)/sizeof(mmDOUT_SCRATCH2[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH3", REG_MMIO, 0x1847, &mmDOUT_SCRATCH3[0], sizeof(mmDOUT_SCRATCH3)/sizeof(mmDOUT_SCRATCH3[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH4", REG_MMIO, 0x1848, &mmDOUT_SCRATCH4[0], sizeof(mmDOUT_SCRATCH4)/sizeof(mmDOUT_SCRATCH4[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH5", REG_MMIO, 0x1849, &mmDOUT_SCRATCH5[0], sizeof(mmDOUT_SCRATCH5)/sizeof(mmDOUT_SCRATCH5[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH6", REG_MMIO, 0x184a, &mmDOUT_SCRATCH6[0], sizeof(mmDOUT_SCRATCH6)/sizeof(mmDOUT_SCRATCH6[0]), 0, 0 },
+	{ "mmDOUT_SCRATCH7", REG_MMIO, 0x184b, &mmDOUT_SCRATCH7[0], sizeof(mmDOUT_SCRATCH7)/sizeof(mmDOUT_SCRATCH7[0]), 0, 0 },
+	{ "mmDOUT_TEST_DEBUG_INDEX", REG_MMIO, 0x184d, &mmDOUT_TEST_DEBUG_INDEX[0], sizeof(mmDOUT_TEST_DEBUG_INDEX)/sizeof(mmDOUT_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDOUT_TEST_DEBUG_DATA", REG_MMIO, 0x184e, &mmDOUT_TEST_DEBUG_DATA[0], sizeof(mmDOUT_TEST_DEBUG_DATA)/sizeof(mmDOUT_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE4", REG_MMIO, 0x1853, &mmDISP_INTERRUPT_STATUS_CONTINUE4[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE4[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE5", REG_MMIO, 0x1854, &mmDISP_INTERRUPT_STATUS_CONTINUE5[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE5[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_HW_STATUS", REG_MMIO, 0x1855, &mmDC_I2C_DDCVGA_HW_STATUS[0], sizeof(mmDC_I2C_DDCVGA_HW_STATUS)/sizeof(mmDC_I2C_DDCVGA_HW_STATUS[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SPEED", REG_MMIO, 0x1856, &mmDC_I2C_DDCVGA_SPEED[0], sizeof(mmDC_I2C_DDCVGA_SPEED)/sizeof(mmDC_I2C_DDCVGA_SPEED[0]), 0, 0 },
+	{ "mmDC_I2C_DDCVGA_SETUP", REG_MMIO, 0x1857, &mmDC_I2C_DDCVGA_SETUP[0], sizeof(mmDC_I2C_DDCVGA_SETUP)/sizeof(mmDC_I2C_DDCVGA_SETUP[0]), 0, 0 },
+	{ "mmDVO_ENABLE", REG_MMIO, 0x1858, &mmDVO_ENABLE[0], sizeof(mmDVO_ENABLE)/sizeof(mmDVO_ENABLE[0]), 0, 0 },
+	{ "mmDVO_SOURCE_SELECT", REG_MMIO, 0x1859, &mmDVO_SOURCE_SELECT[0], sizeof(mmDVO_SOURCE_SELECT)/sizeof(mmDVO_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDVO_OUTPUT", REG_MMIO, 0x185a, &mmDVO_OUTPUT[0], sizeof(mmDVO_OUTPUT)/sizeof(mmDVO_OUTPUT[0]), 0, 0 },
+	{ "mmDVO_CONTROL", REG_MMIO, 0x185b, &mmDVO_CONTROL[0], sizeof(mmDVO_CONTROL)/sizeof(mmDVO_CONTROL[0]), 0, 0 },
+	{ "mmDVO_CRC_EN", REG_MMIO, 0x185c, &mmDVO_CRC_EN[0], sizeof(mmDVO_CRC_EN)/sizeof(mmDVO_CRC_EN[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_MASK", REG_MMIO, 0x185d, &mmDVO_CRC2_SIG_MASK[0], sizeof(mmDVO_CRC2_SIG_MASK)/sizeof(mmDVO_CRC2_SIG_MASK[0]), 0, 0 },
+	{ "mmDVO_CRC2_SIG_RESULT", REG_MMIO, 0x185e, &mmDVO_CRC2_SIG_RESULT[0], sizeof(mmDVO_CRC2_SIG_RESULT)/sizeof(mmDVO_CRC2_SIG_RESULT[0]), 0, 0 },
+	{ "mmDVO_FIFO_ERROR_STATUS", REG_MMIO, 0x185f, &mmDVO_FIFO_ERROR_STATUS[0], sizeof(mmDVO_FIFO_ERROR_STATUS)/sizeof(mmDVO_FIFO_ERROR_STATUS[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK1_SEL", REG_MMIO, 0x1860, &mmDCDEBUG_BUS_CLK1_SEL[0], sizeof(mmDCDEBUG_BUS_CLK1_SEL)/sizeof(mmDCDEBUG_BUS_CLK1_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK2_SEL", REG_MMIO, 0x1861, &mmDCDEBUG_BUS_CLK2_SEL[0], sizeof(mmDCDEBUG_BUS_CLK2_SEL)/sizeof(mmDCDEBUG_BUS_CLK2_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK3_SEL", REG_MMIO, 0x1862, &mmDCDEBUG_BUS_CLK3_SEL[0], sizeof(mmDCDEBUG_BUS_CLK3_SEL)/sizeof(mmDCDEBUG_BUS_CLK3_SEL[0]), 0, 0 },
+	{ "mmDCDEBUG_BUS_CLK4_SEL", REG_MMIO, 0x1863, &mmDCDEBUG_BUS_CLK4_SEL[0], sizeof(mmDCDEBUG_BUS_CLK4_SEL)/sizeof(mmDCDEBUG_BUS_CLK4_SEL[0]), 0, 0 },
+	{ "mmDC_HPD1_FAST_TRAIN_CNTL", REG_MMIO, 0x1864, &mmDC_HPD1_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD1_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD1_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD2_FAST_TRAIN_CNTL", REG_MMIO, 0x1865, &mmDC_HPD2_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD2_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD2_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD3_FAST_TRAIN_CNTL", REG_MMIO, 0x1866, &mmDC_HPD3_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD3_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD3_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD4_FAST_TRAIN_CNTL", REG_MMIO, 0x1867, &mmDC_HPD4_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD4_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD4_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD5_FAST_TRAIN_CNTL", REG_MMIO, 0x1868, &mmDC_HPD5_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD5_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD5_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD6_FAST_TRAIN_CNTL", REG_MMIO, 0x1869, &mmDC_HPD6_FAST_TRAIN_CNTL[0], sizeof(mmDC_HPD6_FAST_TRAIN_CNTL)/sizeof(mmDC_HPD6_FAST_TRAIN_CNTL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_PIN_OVERRIDE", REG_MMIO, 0x186a, &mmDCDEBUG_OUT_PIN_OVERRIDE[0], sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE)/sizeof(mmDCDEBUG_OUT_PIN_OVERRIDE[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_CNTL", REG_MMIO, 0x186b, &mmDCDEBUG_OUT_CNTL[0], sizeof(mmDCDEBUG_OUT_CNTL)/sizeof(mmDCDEBUG_OUT_CNTL[0]), 0, 0 },
+	{ "mmDCDEBUG_OUT_DATA", REG_MMIO, 0x186e, &mmDCDEBUG_OUT_DATA[0], sizeof(mmDCDEBUG_OUT_DATA)/sizeof(mmDCDEBUG_OUT_DATA[0]), 0, 0 },
+	{ "mmDC_I2C_EDID_DETECT_CTRL", REG_MMIO, 0x186f, &mmDC_I2C_EDID_DETECT_CTRL[0], sizeof(mmDC_I2C_EDID_DETECT_CTRL)/sizeof(mmDC_I2C_EDID_DETECT_CTRL[0]), 0, 0 },
+	{ "mmDC_PERFMON1_PERFCOUNTER_CNTL", REG_MMIO, 0x1870, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFCOUNTER_STATE", REG_MMIO, 0x1871, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1872, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CNTL", REG_MMIO, 0x1873, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_CVALUE_LOW", REG_MMIO, 0x1874, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_HI", REG_MMIO, 0x1875, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_LOW", REG_MMIO, 0x1876, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1877, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON1_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1878, NULL, 0, 0, 0 },
+	{ "mmDP_AUX0_AUX_CONTROL", REG_MMIO, 0x1880, NULL, 0, 0, 0 },
+	{ "mmAUX_CONTROL", REG_MMIO, 0x1880, &mmAUX_CONTROL[0], sizeof(mmAUX_CONTROL)/sizeof(mmAUX_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_CONTROL", REG_MMIO, 0x1881, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_CONTROL", REG_MMIO, 0x1881, &mmAUX_SW_CONTROL[0], sizeof(mmAUX_SW_CONTROL)/sizeof(mmAUX_SW_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_ARB_CONTROL", REG_MMIO, 0x1882, NULL, 0, 0, 0 },
+	{ "mmAUX_ARB_CONTROL", REG_MMIO, 0x1882, &mmAUX_ARB_CONTROL[0], sizeof(mmAUX_ARB_CONTROL)/sizeof(mmAUX_ARB_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1883, NULL, 0, 0, 0 },
+	{ "mmAUX_INTERRUPT_CONTROL", REG_MMIO, 0x1883, &mmAUX_INTERRUPT_CONTROL[0], sizeof(mmAUX_INTERRUPT_CONTROL)/sizeof(mmAUX_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_STATUS", REG_MMIO, 0x1884, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_STATUS", REG_MMIO, 0x1884, &mmAUX_SW_STATUS[0], sizeof(mmAUX_SW_STATUS)/sizeof(mmAUX_SW_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_LS_STATUS", REG_MMIO, 0x1885, NULL, 0, 0, 0 },
+	{ "mmAUX_LS_STATUS", REG_MMIO, 0x1885, &mmAUX_LS_STATUS[0], sizeof(mmAUX_LS_STATUS)/sizeof(mmAUX_LS_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_SW_DATA", REG_MMIO, 0x1886, NULL, 0, 0, 0 },
+	{ "mmAUX_SW_DATA", REG_MMIO, 0x1886, &mmAUX_SW_DATA[0], sizeof(mmAUX_SW_DATA)/sizeof(mmAUX_SW_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_LS_DATA", REG_MMIO, 0x1887, NULL, 0, 0, 0 },
+	{ "mmAUX_LS_DATA", REG_MMIO, 0x1887, &mmAUX_LS_DATA[0], sizeof(mmAUX_LS_DATA)/sizeof(mmAUX_LS_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1888, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x1888, &mmAUX_DPHY_TX_REF_CONTROL[0], sizeof(mmAUX_DPHY_TX_REF_CONTROL)/sizeof(mmAUX_DPHY_TX_REF_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x1889, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_CONTROL", REG_MMIO, 0x1889, &mmAUX_DPHY_TX_CONTROL[0], sizeof(mmAUX_DPHY_TX_CONTROL)/sizeof(mmAUX_DPHY_TX_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x188a, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL0", REG_MMIO, 0x188a, &mmAUX_DPHY_RX_CONTROL0[0], sizeof(mmAUX_DPHY_RX_CONTROL0)/sizeof(mmAUX_DPHY_RX_CONTROL0[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x188b, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_CONTROL1", REG_MMIO, 0x188b, &mmAUX_DPHY_RX_CONTROL1[0], sizeof(mmAUX_DPHY_RX_CONTROL1)/sizeof(mmAUX_DPHY_RX_CONTROL1[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_TX_STATUS", REG_MMIO, 0x188c, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_TX_STATUS", REG_MMIO, 0x188c, &mmAUX_DPHY_TX_STATUS[0], sizeof(mmAUX_DPHY_TX_STATUS)/sizeof(mmAUX_DPHY_TX_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_DPHY_RX_STATUS", REG_MMIO, 0x188d, NULL, 0, 0, 0 },
+	{ "mmAUX_DPHY_RX_STATUS", REG_MMIO, 0x188d, &mmAUX_DPHY_RX_STATUS[0], sizeof(mmAUX_DPHY_RX_STATUS)/sizeof(mmAUX_DPHY_RX_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x188e, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_CONTROL", REG_MMIO, 0x188e, &mmAUX_GTC_SYNC_CONTROL[0], sizeof(mmAUX_GTC_SYNC_CONTROL)/sizeof(mmAUX_GTC_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x188f, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x188f, &mmAUX_GTC_SYNC_ERROR_CONTROL[0], sizeof(mmAUX_GTC_SYNC_ERROR_CONTROL)/sizeof(mmAUX_GTC_SYNC_ERROR_CONTROL[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x1890, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x1890, &mmAUX_GTC_SYNC_CONTROLLER_STATUS[0], sizeof(mmAUX_GTC_SYNC_CONTROLLER_STATUS)/sizeof(mmAUX_GTC_SYNC_CONTROLLER_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x1891, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_STATUS", REG_MMIO, 0x1891, &mmAUX_GTC_SYNC_STATUS[0], sizeof(mmAUX_GTC_SYNC_STATUS)/sizeof(mmAUX_GTC_SYNC_STATUS[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_DATA", REG_MMIO, 0x1892, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_DATA", REG_MMIO, 0x1892, &mmAUX_GTC_SYNC_DATA[0], sizeof(mmAUX_GTC_SYNC_DATA)/sizeof(mmAUX_GTC_SYNC_DATA[0]), 0, 0 },
+	{ "mmDP_AUX0_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x1893, NULL, 0, 0, 0 },
+	{ "mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x1893, &mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[0], sizeof(mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE)/sizeof(mmAUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE[0]), 0, 0 },
+	{ "mmDP_AUX1_AUX_CONTROL", REG_MMIO, 0x1894, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_CONTROL", REG_MMIO, 0x1895, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_ARB_CONTROL", REG_MMIO, 0x1896, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x1897, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_STATUS", REG_MMIO, 0x1898, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_STATUS", REG_MMIO, 0x1899, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_SW_DATA", REG_MMIO, 0x189a, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_LS_DATA", REG_MMIO, 0x189b, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x189c, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x189d, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x189e, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x189f, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18a0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18a1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18a2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x18a3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x18a4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x18a5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18a6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX1_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x18a7, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_CONTROL", REG_MMIO, 0x18a8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_CONTROL", REG_MMIO, 0x18a9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_ARB_CONTROL", REG_MMIO, 0x18aa, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x18ab, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_STATUS", REG_MMIO, 0x18ac, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_STATUS", REG_MMIO, 0x18ad, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_SW_DATA", REG_MMIO, 0x18ae, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_LS_DATA", REG_MMIO, 0x18af, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x18b0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x18b1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x18b2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x18b3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18b4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18b5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18b6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x18b7, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x18b8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x18b9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18ba, NULL, 0, 0, 0 },
+	{ "mmDP_AUX2_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x18bb, NULL, 0, 0, 0 },
+	{ "mmDC_HPD1_TOGGLE_FILT_CNTL", REG_MMIO, 0x18bc, &mmDC_HPD1_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD1_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD1_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD2_TOGGLE_FILT_CNTL", REG_MMIO, 0x18bd, &mmDC_HPD2_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD2_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD2_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD3_TOGGLE_FILT_CNTL", REG_MMIO, 0x18be, &mmDC_HPD3_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD3_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD3_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDISPOUT_STEREOSYNC_SEL", REG_MMIO, 0x18bf, &mmDISPOUT_STEREOSYNC_SEL[0], sizeof(mmDISPOUT_STEREOSYNC_SEL)/sizeof(mmDISPOUT_STEREOSYNC_SEL[0]), 0, 0 },
+	{ "mmDP_AUX3_AUX_CONTROL", REG_MMIO, 0x18c0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_CONTROL", REG_MMIO, 0x18c1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_ARB_CONTROL", REG_MMIO, 0x18c2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x18c3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_STATUS", REG_MMIO, 0x18c4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_STATUS", REG_MMIO, 0x18c5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_SW_DATA", REG_MMIO, 0x18c6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_LS_DATA", REG_MMIO, 0x18c7, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x18c8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x18c9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x18ca, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x18cb, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18cc, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18cd, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18ce, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x18cf, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x18d0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x18d1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18d2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX3_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x18d3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_CONTROL", REG_MMIO, 0x18d4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_CONTROL", REG_MMIO, 0x18d5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_ARB_CONTROL", REG_MMIO, 0x18d6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x18d7, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_STATUS", REG_MMIO, 0x18d8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_STATUS", REG_MMIO, 0x18d9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_SW_DATA", REG_MMIO, 0x18da, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_LS_DATA", REG_MMIO, 0x18db, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x18dc, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x18dd, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x18de, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x18df, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18e0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18e1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18e2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x18e3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x18e4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x18e5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18e6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX4_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x18e7, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_CONTROL", REG_MMIO, 0x18e8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_CONTROL", REG_MMIO, 0x18e9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_ARB_CONTROL", REG_MMIO, 0x18ea, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_INTERRUPT_CONTROL", REG_MMIO, 0x18eb, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_STATUS", REG_MMIO, 0x18ec, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_STATUS", REG_MMIO, 0x18ed, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_SW_DATA", REG_MMIO, 0x18ee, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_LS_DATA", REG_MMIO, 0x18ef, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL", REG_MMIO, 0x18f0, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_CONTROL", REG_MMIO, 0x18f1, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL0", REG_MMIO, 0x18f2, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_CONTROL1", REG_MMIO, 0x18f3, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_TX_STATUS", REG_MMIO, 0x18f4, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_DPHY_RX_STATUS", REG_MMIO, 0x18f5, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_CONTROL", REG_MMIO, 0x18f6, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL", REG_MMIO, 0x18f7, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS", REG_MMIO, 0x18f8, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_STATUS", REG_MMIO, 0x18f9, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_DATA", REG_MMIO, 0x18fa, NULL, 0, 0, 0 },
+	{ "mmDP_AUX5_AUX_GTC_SYNC_PHASE_OFFSET_OVERRIDE", REG_MMIO, 0x18fb, NULL, 0, 0, 0 },
+	{ "mmDC_HPD4_TOGGLE_FILT_CNTL", REG_MMIO, 0x18fc, &mmDC_HPD4_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD4_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD4_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD5_TOGGLE_FILT_CNTL", REG_MMIO, 0x18fd, &mmDC_HPD5_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD5_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD5_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDC_HPD6_TOGGLE_FILT_CNTL", REG_MMIO, 0x18fe, &mmDC_HPD6_TOGGLE_FILT_CNTL[0], sizeof(mmDC_HPD6_TOGGLE_FILT_CNTL)/sizeof(mmDC_HPD6_TOGGLE_FILT_CNTL[0]), 0, 0 },
+	{ "mmDOUT_DCE_VCE_CONTROL", REG_MMIO, 0x18ff, &mmDOUT_DCE_VCE_CONTROL[0], sizeof(mmDOUT_DCE_VCE_CONTROL)/sizeof(mmDOUT_DCE_VCE_CONTROL[0]), 0, 0 },
+	{ "mmIMMEDIATE_RESPONSE_INPUT_INTERFACE", REG_MMIO, 0x19, &mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0], sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE)/sizeof(mmIMMEDIATE_RESPONSE_INPUT_INTERFACE[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_J", REG_SMC, 0x19, &ixDP_AUX1_DEBUG_J[0], sizeof(ixDP_AUX1_DEBUG_J)/sizeof(ixDP_AUX1_DEBUG_J[0]), 0, 0 },
+	{ "mmDC_GENERICA", REG_MMIO, 0x1900, &mmDC_GENERICA[0], sizeof(mmDC_GENERICA)/sizeof(mmDC_GENERICA[0]), 0, 0 },
+	{ "mmDC_GENERICB", REG_MMIO, 0x1901, &mmDC_GENERICB[0], sizeof(mmDC_GENERICB)/sizeof(mmDC_GENERICB[0]), 0, 0 },
+	{ "mmDC_PAD_EXTERN_SIG", REG_MMIO, 0x1902, &mmDC_PAD_EXTERN_SIG[0], sizeof(mmDC_PAD_EXTERN_SIG)/sizeof(mmDC_PAD_EXTERN_SIG[0]), 0, 0 },
+	{ "mmDC_REF_CLK_CNTL", REG_MMIO, 0x1903, &mmDC_REF_CLK_CNTL[0], sizeof(mmDC_REF_CLK_CNTL)/sizeof(mmDC_REF_CLK_CNTL[0]), 0, 0 },
+	{ "mmDC_GPIO_DEBUG", REG_MMIO, 0x1904, &mmDC_GPIO_DEBUG[0], sizeof(mmDC_GPIO_DEBUG)/sizeof(mmDC_GPIO_DEBUG[0]), 0, 0 },
+	{ "mmDC_DVODATA_CONFIG", REG_MMIO, 0x1905, &mmDC_DVODATA_CONFIG[0], sizeof(mmDC_DVODATA_CONFIG)/sizeof(mmDC_DVODATA_CONFIG[0]), 0, 0 },
+	{ "mmDCO_MEM_POWER_STATE", REG_MMIO, 0x1906, &mmDCO_MEM_POWER_STATE[0], sizeof(mmDCO_MEM_POWER_STATE)/sizeof(mmDCO_MEM_POWER_STATE[0]), 0, 0 },
+	{ "mmDCO_LIGHT_SLEEP_DIS", REG_MMIO, 0x1907, &mmDCO_LIGHT_SLEEP_DIS[0], sizeof(mmDCO_LIGHT_SLEEP_DIS)/sizeof(mmDCO_LIGHT_SLEEP_DIS[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKA", REG_MMIO, 0x1908, &mmUNIPHY_IMPCAL_LINKA[0], sizeof(mmUNIPHY_IMPCAL_LINKA)/sizeof(mmUNIPHY_IMPCAL_LINKA[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKB", REG_MMIO, 0x1909, &mmUNIPHY_IMPCAL_LINKB[0], sizeof(mmUNIPHY_IMPCAL_LINKB)/sizeof(mmUNIPHY_IMPCAL_LINKB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PERIOD", REG_MMIO, 0x190a, &mmUNIPHY_IMPCAL_PERIOD[0], sizeof(mmUNIPHY_IMPCAL_PERIOD)/sizeof(mmUNIPHY_IMPCAL_PERIOD[0]), 0, 0 },
+	{ "mmAUXP_IMPCAL", REG_MMIO, 0x190b, &mmAUXP_IMPCAL[0], sizeof(mmAUXP_IMPCAL)/sizeof(mmAUXP_IMPCAL[0]), 0, 0 },
+	{ "mmAUXN_IMPCAL", REG_MMIO, 0x190c, &mmAUXN_IMPCAL[0], sizeof(mmAUXN_IMPCAL)/sizeof(mmAUXN_IMPCAL[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_AB", REG_MMIO, 0x190d, &mmDCIO_IMPCAL_CNTL_AB[0], sizeof(mmDCIO_IMPCAL_CNTL_AB)/sizeof(mmDCIO_IMPCAL_CNTL_AB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_AB", REG_MMIO, 0x190e, &mmUNIPHY_IMPCAL_PSW_AB[0], sizeof(mmUNIPHY_IMPCAL_PSW_AB)/sizeof(mmUNIPHY_IMPCAL_PSW_AB[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKC", REG_MMIO, 0x190f, &mmUNIPHY_IMPCAL_LINKC[0], sizeof(mmUNIPHY_IMPCAL_LINKC)/sizeof(mmUNIPHY_IMPCAL_LINKC[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKD", REG_MMIO, 0x1910, &mmUNIPHY_IMPCAL_LINKD[0], sizeof(mmUNIPHY_IMPCAL_LINKD)/sizeof(mmUNIPHY_IMPCAL_LINKD[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_CD", REG_MMIO, 0x1911, &mmDCIO_IMPCAL_CNTL_CD[0], sizeof(mmDCIO_IMPCAL_CNTL_CD)/sizeof(mmDCIO_IMPCAL_CNTL_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_CD", REG_MMIO, 0x1912, &mmUNIPHY_IMPCAL_PSW_CD[0], sizeof(mmUNIPHY_IMPCAL_PSW_CD)/sizeof(mmUNIPHY_IMPCAL_PSW_CD[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKE", REG_MMIO, 0x1913, &mmUNIPHY_IMPCAL_LINKE[0], sizeof(mmUNIPHY_IMPCAL_LINKE)/sizeof(mmUNIPHY_IMPCAL_LINKE[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_LINKF", REG_MMIO, 0x1914, &mmUNIPHY_IMPCAL_LINKF[0], sizeof(mmUNIPHY_IMPCAL_LINKF)/sizeof(mmUNIPHY_IMPCAL_LINKF[0]), 0, 0 },
+	{ "mmDCIO_IMPCAL_CNTL_EF", REG_MMIO, 0x1915, &mmDCIO_IMPCAL_CNTL_EF[0], sizeof(mmDCIO_IMPCAL_CNTL_EF)/sizeof(mmDCIO_IMPCAL_CNTL_EF[0]), 0, 0 },
+	{ "mmUNIPHY_IMPCAL_PSW_EF", REG_MMIO, 0x1916, &mmUNIPHY_IMPCAL_PSW_EF[0], sizeof(mmUNIPHY_IMPCAL_PSW_EF)/sizeof(mmUNIPHY_IMPCAL_PSW_EF[0]), 0, 0 },
+	{ "mmDC_PINSTRAPS", REG_MMIO, 0x1917, &mmDC_PINSTRAPS[0], sizeof(mmDC_PINSTRAPS)/sizeof(mmDC_PINSTRAPS[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_CNTL", REG_MMIO, 0x1919, &mmLVTMA_PWRSEQ_CNTL[0], sizeof(mmLVTMA_PWRSEQ_CNTL)/sizeof(mmLVTMA_PWRSEQ_CNTL[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_STATE", REG_MMIO, 0x191a, &mmLVTMA_PWRSEQ_STATE[0], sizeof(mmLVTMA_PWRSEQ_STATE)/sizeof(mmLVTMA_PWRSEQ_STATE[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_REF_DIV", REG_MMIO, 0x191b, &mmLVTMA_PWRSEQ_REF_DIV[0], sizeof(mmLVTMA_PWRSEQ_REF_DIV)/sizeof(mmLVTMA_PWRSEQ_REF_DIV[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY1", REG_MMIO, 0x191c, &mmLVTMA_PWRSEQ_DELAY1[0], sizeof(mmLVTMA_PWRSEQ_DELAY1)/sizeof(mmLVTMA_PWRSEQ_DELAY1[0]), 0, 0 },
+	{ "mmLVTMA_PWRSEQ_DELAY2", REG_MMIO, 0x191d, &mmLVTMA_PWRSEQ_DELAY2[0], sizeof(mmLVTMA_PWRSEQ_DELAY2)/sizeof(mmLVTMA_PWRSEQ_DELAY2[0]), 0, 0 },
+	{ "mmBL_PWM_CNTL", REG_MMIO, 0x191e, &mmBL_PWM_CNTL[0], sizeof(mmBL_PWM_CNTL)/sizeof(mmBL_PWM_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_CNTL2", REG_MMIO, 0x191f, &mmBL_PWM_CNTL2[0], sizeof(mmBL_PWM_CNTL2)/sizeof(mmBL_PWM_CNTL2[0]), 0, 0 },
+	{ "mmBL_PWM_PERIOD_CNTL", REG_MMIO, 0x1920, &mmBL_PWM_PERIOD_CNTL[0], sizeof(mmBL_PWM_PERIOD_CNTL)/sizeof(mmBL_PWM_PERIOD_CNTL[0]), 0, 0 },
+	{ "mmBL_PWM_GRP1_REG_LOCK", REG_MMIO, 0x1921, &mmBL_PWM_GRP1_REG_LOCK[0], sizeof(mmBL_PWM_GRP1_REG_LOCK)/sizeof(mmBL_PWM_GRP1_REG_LOCK[0]), 0, 0 },
+	{ "mmDCIO_GSL_GENLK_PAD_CNTL", REG_MMIO, 0x1922, &mmDCIO_GSL_GENLK_PAD_CNTL[0], sizeof(mmDCIO_GSL_GENLK_PAD_CNTL)/sizeof(mmDCIO_GSL_GENLK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL_SWAPLOCK_PAD_CNTL", REG_MMIO, 0x1923, &mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0], sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL)/sizeof(mmDCIO_GSL_SWAPLOCK_PAD_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL0_CNTL", REG_MMIO, 0x1924, &mmDCIO_GSL0_CNTL[0], sizeof(mmDCIO_GSL0_CNTL)/sizeof(mmDCIO_GSL0_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL1_CNTL", REG_MMIO, 0x1925, &mmDCIO_GSL1_CNTL[0], sizeof(mmDCIO_GSL1_CNTL)/sizeof(mmDCIO_GSL1_CNTL[0]), 0, 0 },
+	{ "mmDCIO_GSL2_CNTL", REG_MMIO, 0x1926, &mmDCIO_GSL2_CNTL[0], sizeof(mmDCIO_GSL2_CNTL)/sizeof(mmDCIO_GSL2_CNTL[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_V_UPDATE", REG_MMIO, 0x1927, &mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0], sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE)/sizeof(mmDC_GPU_TIMER_START_POSITION_V_UPDATE[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_START_POSITION_P_FLIP", REG_MMIO, 0x1928, &mmDC_GPU_TIMER_START_POSITION_P_FLIP[0], sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP)/sizeof(mmDC_GPU_TIMER_START_POSITION_P_FLIP[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ", REG_MMIO, 0x1929, &mmDC_GPU_TIMER_READ[0], sizeof(mmDC_GPU_TIMER_READ)/sizeof(mmDC_GPU_TIMER_READ[0]), 0, 0 },
+	{ "mmDC_GPU_TIMER_READ_CNTL", REG_MMIO, 0x192a, &mmDC_GPU_TIMER_READ_CNTL[0], sizeof(mmDC_GPU_TIMER_READ_CNTL)/sizeof(mmDC_GPU_TIMER_READ_CNTL[0]), 0, 0 },
+	{ "mmDCO_CLK_CNTL", REG_MMIO, 0x192b, &mmDCO_CLK_CNTL[0], sizeof(mmDCO_CLK_CNTL)/sizeof(mmDCO_CLK_CNTL[0]), 0, 0 },
+	{ "mmDCO_CLK_RAMP_CNTL", REG_MMIO, 0x192c, &mmDCO_CLK_RAMP_CNTL[0], sizeof(mmDCO_CLK_RAMP_CNTL)/sizeof(mmDCO_CLK_RAMP_CNTL[0]), 0, 0 },
+	{ "mmDCIO_DEBUG", REG_MMIO, 0x192e, &mmDCIO_DEBUG[0], sizeof(mmDCIO_DEBUG)/sizeof(mmDCIO_DEBUG[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_INDEX", REG_MMIO, 0x192f, &mmDCIO_TEST_DEBUG_INDEX[0], sizeof(mmDCIO_TEST_DEBUG_INDEX)/sizeof(mmDCIO_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCIO_TEST_DEBUG_DATA", REG_MMIO, 0x1930, &mmDCIO_TEST_DEBUG_DATA[0], sizeof(mmDCIO_TEST_DEBUG_DATA)/sizeof(mmDCIO_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmUNIPHYAB_TPG_CONTROL", REG_MMIO, 0x1931, &mmUNIPHYAB_TPG_CONTROL[0], sizeof(mmUNIPHYAB_TPG_CONTROL)/sizeof(mmUNIPHYAB_TPG_CONTROL[0]), 0, 0 },
+	{ "mmUNIPHYAB_TPG_SEED", REG_MMIO, 0x1932, &mmUNIPHYAB_TPG_SEED[0], sizeof(mmUNIPHYAB_TPG_SEED)/sizeof(mmUNIPHYAB_TPG_SEED[0]), 0, 0 },
+	{ "mmUNIPHYCD_TPG_CONTROL", REG_MMIO, 0x1933, &mmUNIPHYCD_TPG_CONTROL[0], sizeof(mmUNIPHYCD_TPG_CONTROL)/sizeof(mmUNIPHYCD_TPG_CONTROL[0]), 0, 0 },
+	{ "mmUNIPHYCD_TPG_SEED", REG_MMIO, 0x1934, &mmUNIPHYCD_TPG_SEED[0], sizeof(mmUNIPHYCD_TPG_SEED)/sizeof(mmUNIPHYCD_TPG_SEED[0]), 0, 0 },
+	{ "mmUNIPHYEF_TPG_CONTROL", REG_MMIO, 0x1935, &mmUNIPHYEF_TPG_CONTROL[0], sizeof(mmUNIPHYEF_TPG_CONTROL)/sizeof(mmUNIPHYEF_TPG_CONTROL[0]), 0, 0 },
+	{ "mmUNIPHYEF_TPG_SEED", REG_MMIO, 0x1936, &mmUNIPHYEF_TPG_SEED[0], sizeof(mmUNIPHYEF_TPG_SEED)/sizeof(mmUNIPHYEF_TPG_SEED[0]), 0, 0 },
+	{ "mmDCO_DCFE_EXT_VSYNC_CNTL", REG_MMIO, 0x1937, &mmDCO_DCFE_EXT_VSYNC_CNTL[0], sizeof(mmDCO_DCFE_EXT_VSYNC_CNTL)/sizeof(mmDCO_DCFE_EXT_VSYNC_CNTL[0]), 0, 0 },
+	{ "mmUNIPHYGH_TPG_CONTROL", REG_MMIO, 0x1938, &mmUNIPHYGH_TPG_CONTROL[0], sizeof(mmUNIPHYGH_TPG_CONTROL)/sizeof(mmUNIPHYGH_TPG_CONTROL[0]), 0, 0 },
+	{ "mmUNIPHYGH_TPG_SEED", REG_MMIO, 0x1939, &mmUNIPHYGH_TPG_SEED[0], sizeof(mmUNIPHYGH_TPG_SEED)/sizeof(mmUNIPHYGH_TPG_SEED[0]), 0, 0 },
+	{ "mmDCO_MEM_POWER_STATE_2", REG_MMIO, 0x193a, &mmDCO_MEM_POWER_STATE_2[0], sizeof(mmDCO_MEM_POWER_STATE_2)/sizeof(mmDCO_MEM_POWER_STATE_2[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_STRENGTH", REG_MMIO, 0x193b, &mmDC_GPIO_I2S_SPDIF_STRENGTH[0], sizeof(mmDC_GPIO_I2S_SPDIF_STRENGTH)/sizeof(mmDC_GPIO_I2S_SPDIF_STRENGTH[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_MASK", REG_MMIO, 0x193c, &mmDC_GPIO_I2S_SPDIF_MASK[0], sizeof(mmDC_GPIO_I2S_SPDIF_MASK)/sizeof(mmDC_GPIO_I2S_SPDIF_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_A", REG_MMIO, 0x193d, &mmDC_GPIO_I2S_SPDIF_A[0], sizeof(mmDC_GPIO_I2S_SPDIF_A)/sizeof(mmDC_GPIO_I2S_SPDIF_A[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_EN", REG_MMIO, 0x193e, &mmDC_GPIO_I2S_SPDIF_EN[0], sizeof(mmDC_GPIO_I2S_SPDIF_EN)/sizeof(mmDC_GPIO_I2S_SPDIF_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_I2S_SPDIF_Y", REG_MMIO, 0x193f, &mmDC_GPIO_I2S_SPDIF_Y[0], sizeof(mmDC_GPIO_I2S_SPDIF_Y)/sizeof(mmDC_GPIO_I2S_SPDIF_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_MASK", REG_MMIO, 0x1940, &mmDC_GPIO_PWRSEQ_MASK[0], sizeof(mmDC_GPIO_PWRSEQ_MASK)/sizeof(mmDC_GPIO_PWRSEQ_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_A", REG_MMIO, 0x1941, &mmDC_GPIO_PWRSEQ_A[0], sizeof(mmDC_GPIO_PWRSEQ_A)/sizeof(mmDC_GPIO_PWRSEQ_A[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_EN", REG_MMIO, 0x1942, &mmDC_GPIO_PWRSEQ_EN[0], sizeof(mmDC_GPIO_PWRSEQ_EN)/sizeof(mmDC_GPIO_PWRSEQ_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_PWRSEQ_Y", REG_MMIO, 0x1943, &mmDC_GPIO_PWRSEQ_Y[0], sizeof(mmDC_GPIO_PWRSEQ_Y)/sizeof(mmDC_GPIO_PWRSEQ_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_MASK", REG_MMIO, 0x1944, &mmDC_GPIO_GENERIC_MASK[0], sizeof(mmDC_GPIO_GENERIC_MASK)/sizeof(mmDC_GPIO_GENERIC_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_A", REG_MMIO, 0x1945, &mmDC_GPIO_GENERIC_A[0], sizeof(mmDC_GPIO_GENERIC_A)/sizeof(mmDC_GPIO_GENERIC_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_EN", REG_MMIO, 0x1946, &mmDC_GPIO_GENERIC_EN[0], sizeof(mmDC_GPIO_GENERIC_EN)/sizeof(mmDC_GPIO_GENERIC_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENERIC_Y", REG_MMIO, 0x1947, &mmDC_GPIO_GENERIC_Y[0], sizeof(mmDC_GPIO_GENERIC_Y)/sizeof(mmDC_GPIO_GENERIC_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_MASK", REG_MMIO, 0x1948, &mmDC_GPIO_DVODATA_MASK[0], sizeof(mmDC_GPIO_DVODATA_MASK)/sizeof(mmDC_GPIO_DVODATA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_A", REG_MMIO, 0x1949, &mmDC_GPIO_DVODATA_A[0], sizeof(mmDC_GPIO_DVODATA_A)/sizeof(mmDC_GPIO_DVODATA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_EN", REG_MMIO, 0x194a, &mmDC_GPIO_DVODATA_EN[0], sizeof(mmDC_GPIO_DVODATA_EN)/sizeof(mmDC_GPIO_DVODATA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DVODATA_Y", REG_MMIO, 0x194b, &mmDC_GPIO_DVODATA_Y[0], sizeof(mmDC_GPIO_DVODATA_Y)/sizeof(mmDC_GPIO_DVODATA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_MASK", REG_MMIO, 0x194c, &mmDC_GPIO_DDC1_MASK[0], sizeof(mmDC_GPIO_DDC1_MASK)/sizeof(mmDC_GPIO_DDC1_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_A", REG_MMIO, 0x194d, &mmDC_GPIO_DDC1_A[0], sizeof(mmDC_GPIO_DDC1_A)/sizeof(mmDC_GPIO_DDC1_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_EN", REG_MMIO, 0x194e, &mmDC_GPIO_DDC1_EN[0], sizeof(mmDC_GPIO_DDC1_EN)/sizeof(mmDC_GPIO_DDC1_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC1_Y", REG_MMIO, 0x194f, &mmDC_GPIO_DDC1_Y[0], sizeof(mmDC_GPIO_DDC1_Y)/sizeof(mmDC_GPIO_DDC1_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_MASK", REG_MMIO, 0x1950, &mmDC_GPIO_DDC2_MASK[0], sizeof(mmDC_GPIO_DDC2_MASK)/sizeof(mmDC_GPIO_DDC2_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_A", REG_MMIO, 0x1951, &mmDC_GPIO_DDC2_A[0], sizeof(mmDC_GPIO_DDC2_A)/sizeof(mmDC_GPIO_DDC2_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_EN", REG_MMIO, 0x1952, &mmDC_GPIO_DDC2_EN[0], sizeof(mmDC_GPIO_DDC2_EN)/sizeof(mmDC_GPIO_DDC2_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC2_Y", REG_MMIO, 0x1953, &mmDC_GPIO_DDC2_Y[0], sizeof(mmDC_GPIO_DDC2_Y)/sizeof(mmDC_GPIO_DDC2_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_MASK", REG_MMIO, 0x1954, &mmDC_GPIO_DDC3_MASK[0], sizeof(mmDC_GPIO_DDC3_MASK)/sizeof(mmDC_GPIO_DDC3_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_A", REG_MMIO, 0x1955, &mmDC_GPIO_DDC3_A[0], sizeof(mmDC_GPIO_DDC3_A)/sizeof(mmDC_GPIO_DDC3_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_EN", REG_MMIO, 0x1956, &mmDC_GPIO_DDC3_EN[0], sizeof(mmDC_GPIO_DDC3_EN)/sizeof(mmDC_GPIO_DDC3_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC3_Y", REG_MMIO, 0x1957, &mmDC_GPIO_DDC3_Y[0], sizeof(mmDC_GPIO_DDC3_Y)/sizeof(mmDC_GPIO_DDC3_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_MASK", REG_MMIO, 0x1958, &mmDC_GPIO_DDC4_MASK[0], sizeof(mmDC_GPIO_DDC4_MASK)/sizeof(mmDC_GPIO_DDC4_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_A", REG_MMIO, 0x1959, &mmDC_GPIO_DDC4_A[0], sizeof(mmDC_GPIO_DDC4_A)/sizeof(mmDC_GPIO_DDC4_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_EN", REG_MMIO, 0x195a, &mmDC_GPIO_DDC4_EN[0], sizeof(mmDC_GPIO_DDC4_EN)/sizeof(mmDC_GPIO_DDC4_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC4_Y", REG_MMIO, 0x195b, &mmDC_GPIO_DDC4_Y[0], sizeof(mmDC_GPIO_DDC4_Y)/sizeof(mmDC_GPIO_DDC4_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_MASK", REG_MMIO, 0x195c, &mmDC_GPIO_DDC5_MASK[0], sizeof(mmDC_GPIO_DDC5_MASK)/sizeof(mmDC_GPIO_DDC5_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_A", REG_MMIO, 0x195d, &mmDC_GPIO_DDC5_A[0], sizeof(mmDC_GPIO_DDC5_A)/sizeof(mmDC_GPIO_DDC5_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_EN", REG_MMIO, 0x195e, &mmDC_GPIO_DDC5_EN[0], sizeof(mmDC_GPIO_DDC5_EN)/sizeof(mmDC_GPIO_DDC5_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC5_Y", REG_MMIO, 0x195f, &mmDC_GPIO_DDC5_Y[0], sizeof(mmDC_GPIO_DDC5_Y)/sizeof(mmDC_GPIO_DDC5_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_MASK", REG_MMIO, 0x1960, &mmDC_GPIO_DDC6_MASK[0], sizeof(mmDC_GPIO_DDC6_MASK)/sizeof(mmDC_GPIO_DDC6_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_A", REG_MMIO, 0x1961, &mmDC_GPIO_DDC6_A[0], sizeof(mmDC_GPIO_DDC6_A)/sizeof(mmDC_GPIO_DDC6_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_EN", REG_MMIO, 0x1962, &mmDC_GPIO_DDC6_EN[0], sizeof(mmDC_GPIO_DDC6_EN)/sizeof(mmDC_GPIO_DDC6_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDC6_Y", REG_MMIO, 0x1963, &mmDC_GPIO_DDC6_Y[0], sizeof(mmDC_GPIO_DDC6_Y)/sizeof(mmDC_GPIO_DDC6_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_MASK", REG_MMIO, 0x1964, &mmDC_GPIO_SYNCA_MASK[0], sizeof(mmDC_GPIO_SYNCA_MASK)/sizeof(mmDC_GPIO_SYNCA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_A", REG_MMIO, 0x1965, &mmDC_GPIO_SYNCA_A[0], sizeof(mmDC_GPIO_SYNCA_A)/sizeof(mmDC_GPIO_SYNCA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_EN", REG_MMIO, 0x1966, &mmDC_GPIO_SYNCA_EN[0], sizeof(mmDC_GPIO_SYNCA_EN)/sizeof(mmDC_GPIO_SYNCA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_SYNCA_Y", REG_MMIO, 0x1967, &mmDC_GPIO_SYNCA_Y[0], sizeof(mmDC_GPIO_SYNCA_Y)/sizeof(mmDC_GPIO_SYNCA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_MASK", REG_MMIO, 0x1968, &mmDC_GPIO_GENLK_MASK[0], sizeof(mmDC_GPIO_GENLK_MASK)/sizeof(mmDC_GPIO_GENLK_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_A", REG_MMIO, 0x1969, &mmDC_GPIO_GENLK_A[0], sizeof(mmDC_GPIO_GENLK_A)/sizeof(mmDC_GPIO_GENLK_A[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_EN", REG_MMIO, 0x196a, &mmDC_GPIO_GENLK_EN[0], sizeof(mmDC_GPIO_GENLK_EN)/sizeof(mmDC_GPIO_GENLK_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_GENLK_Y", REG_MMIO, 0x196b, &mmDC_GPIO_GENLK_Y[0], sizeof(mmDC_GPIO_GENLK_Y)/sizeof(mmDC_GPIO_GENLK_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_MASK", REG_MMIO, 0x196c, &mmDC_GPIO_HPD_MASK[0], sizeof(mmDC_GPIO_HPD_MASK)/sizeof(mmDC_GPIO_HPD_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_A", REG_MMIO, 0x196d, &mmDC_GPIO_HPD_A[0], sizeof(mmDC_GPIO_HPD_A)/sizeof(mmDC_GPIO_HPD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_EN", REG_MMIO, 0x196e, &mmDC_GPIO_HPD_EN[0], sizeof(mmDC_GPIO_HPD_EN)/sizeof(mmDC_GPIO_HPD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_HPD_Y", REG_MMIO, 0x196f, &mmDC_GPIO_HPD_Y[0], sizeof(mmDC_GPIO_HPD_Y)/sizeof(mmDC_GPIO_HPD_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_MASK", REG_MMIO, 0x1970, &mmDC_GPIO_DDCVGA_MASK[0], sizeof(mmDC_GPIO_DDCVGA_MASK)/sizeof(mmDC_GPIO_DDCVGA_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_A", REG_MMIO, 0x1971, &mmDC_GPIO_DDCVGA_A[0], sizeof(mmDC_GPIO_DDCVGA_A)/sizeof(mmDC_GPIO_DDCVGA_A[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_EN", REG_MMIO, 0x1972, &mmDC_GPIO_DDCVGA_EN[0], sizeof(mmDC_GPIO_DDCVGA_EN)/sizeof(mmDC_GPIO_DDCVGA_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_DDCVGA_Y", REG_MMIO, 0x1973, &mmDC_GPIO_DDCVGA_Y[0], sizeof(mmDC_GPIO_DDCVGA_Y)/sizeof(mmDC_GPIO_DDCVGA_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_MASK", REG_MMIO, 0x1974, &mmDC_GPIO_I2CPAD_MASK[0], sizeof(mmDC_GPIO_I2CPAD_MASK)/sizeof(mmDC_GPIO_I2CPAD_MASK[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_A", REG_MMIO, 0x1975, &mmDC_GPIO_I2CPAD_A[0], sizeof(mmDC_GPIO_I2CPAD_A)/sizeof(mmDC_GPIO_I2CPAD_A[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_EN", REG_MMIO, 0x1976, &mmDC_GPIO_I2CPAD_EN[0], sizeof(mmDC_GPIO_I2CPAD_EN)/sizeof(mmDC_GPIO_I2CPAD_EN[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_Y", REG_MMIO, 0x1977, &mmDC_GPIO_I2CPAD_Y[0], sizeof(mmDC_GPIO_I2CPAD_Y)/sizeof(mmDC_GPIO_I2CPAD_Y[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_1", REG_MMIO, 0x1978, &mmDC_GPIO_PAD_STRENGTH_1[0], sizeof(mmDC_GPIO_PAD_STRENGTH_1)/sizeof(mmDC_GPIO_PAD_STRENGTH_1[0]), 0, 0 },
+	{ "mmDC_GPIO_PAD_STRENGTH_2", REG_MMIO, 0x1979, &mmDC_GPIO_PAD_STRENGTH_2[0], sizeof(mmDC_GPIO_PAD_STRENGTH_2)/sizeof(mmDC_GPIO_PAD_STRENGTH_2[0]), 0, 0 },
+	{ "mmDC_GPIO_I2CPAD_STRENGTH", REG_MMIO, 0x197a, &mmDC_GPIO_I2CPAD_STRENGTH[0], sizeof(mmDC_GPIO_I2CPAD_STRENGTH)/sizeof(mmDC_GPIO_I2CPAD_STRENGTH[0]), 0, 0 },
+	{ "mmDVO_STRENGTH_CONTROL", REG_MMIO, 0x197b, &mmDVO_STRENGTH_CONTROL[0], sizeof(mmDVO_STRENGTH_CONTROL)/sizeof(mmDVO_STRENGTH_CONTROL[0]), 0, 0 },
+	{ "mmDVO_VREF_CONTROL", REG_MMIO, 0x197c, &mmDVO_VREF_CONTROL[0], sizeof(mmDVO_VREF_CONTROL)/sizeof(mmDVO_VREF_CONTROL[0]), 0, 0 },
+	{ "mmDVO_SKEW_ADJUST", REG_MMIO, 0x197d, &mmDVO_SKEW_ADJUST[0], sizeof(mmDVO_SKEW_ADJUST)/sizeof(mmDVO_SKEW_ADJUST[0]), 0, 0 },
+	{ "mmPHY_AUX_CNTL", REG_MMIO, 0x197f, &mmPHY_AUX_CNTL[0], sizeof(mmPHY_AUX_CNTL)/sizeof(mmPHY_AUX_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1", REG_MMIO, 0x1980, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL1", REG_MMIO, 0x1980, &mmUNIPHY_TX_CONTROL1[0], sizeof(mmUNIPHY_TX_CONTROL1)/sizeof(mmUNIPHY_TX_CONTROL1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2", REG_MMIO, 0x1981, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL2", REG_MMIO, 0x1981, &mmUNIPHY_TX_CONTROL2[0], sizeof(mmUNIPHY_TX_CONTROL2)/sizeof(mmUNIPHY_TX_CONTROL2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3", REG_MMIO, 0x1982, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL3", REG_MMIO, 0x1982, &mmUNIPHY_TX_CONTROL3[0], sizeof(mmUNIPHY_TX_CONTROL3)/sizeof(mmUNIPHY_TX_CONTROL3[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4", REG_MMIO, 0x1983, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_TX_CONTROL4", REG_MMIO, 0x1983, &mmUNIPHY_TX_CONTROL4[0], sizeof(mmUNIPHY_TX_CONTROL4)/sizeof(mmUNIPHY_TX_CONTROL4[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL", REG_MMIO, 0x1984, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_POWER_CONTROL", REG_MMIO, 0x1984, &mmUNIPHY_POWER_CONTROL[0], sizeof(mmUNIPHY_POWER_CONTROL)/sizeof(mmUNIPHY_POWER_CONTROL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV", REG_MMIO, 0x1985, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_PLL_FBDIV", REG_MMIO, 0x1985, &mmUNIPHY_PLL_FBDIV[0], sizeof(mmUNIPHY_PLL_FBDIV)/sizeof(mmUNIPHY_PLL_FBDIV[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x1986, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_PLL_CONTROL1", REG_MMIO, 0x1986, &mmUNIPHY_PLL_CONTROL1[0], sizeof(mmUNIPHY_PLL_CONTROL1)/sizeof(mmUNIPHY_PLL_CONTROL1[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x1987, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_PLL_CONTROL2", REG_MMIO, 0x1987, &mmUNIPHY_PLL_CONTROL2[0], sizeof(mmUNIPHY_PLL_CONTROL2)/sizeof(mmUNIPHY_PLL_CONTROL2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x1988, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x1988, &mmUNIPHY_PLL_SS_STEP_SIZE[0], sizeof(mmUNIPHY_PLL_SS_STEP_SIZE)/sizeof(mmUNIPHY_PLL_SS_STEP_SIZE[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x1989, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_PLL_SS_CNTL", REG_MMIO, 0x1989, &mmUNIPHY_PLL_SS_CNTL[0], sizeof(mmUNIPHY_PLL_SS_CNTL)/sizeof(mmUNIPHY_PLL_SS_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x198a, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x198a, &mmUNIPHY_DATA_SYNCHRONIZATION[0], sizeof(mmUNIPHY_DATA_SYNCHRONIZATION)/sizeof(mmUNIPHY_DATA_SYNCHRONIZATION[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x198b, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x198b, &mmUNIPHY_REG_TEST_OUTPUT[0], sizeof(mmUNIPHY_REG_TEST_OUTPUT)/sizeof(mmUNIPHY_REG_TEST_OUTPUT[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x198c, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x198c, &mmUNIPHY_ANG_BIST_CNTL[0], sizeof(mmUNIPHY_ANG_BIST_CNTL)/sizeof(mmUNIPHY_ANG_BIST_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL", REG_MMIO, 0x198d, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_LINK_CNTL", REG_MMIO, 0x198d, &mmUNIPHY_LINK_CNTL[0], sizeof(mmUNIPHY_LINK_CNTL)/sizeof(mmUNIPHY_LINK_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x198e, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x198e, &mmUNIPHY_CHANNEL_XBAR_CNTL[0], sizeof(mmUNIPHY_CHANNEL_XBAR_CNTL)/sizeof(mmUNIPHY_CHANNEL_XBAR_CNTL[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x198f, NULL, 0, 0, 0 },
+	{ "mmUNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x198f, &mmUNIPHY_REG_TEST_OUTPUT2[0], sizeof(mmUNIPHY_REG_TEST_OUTPUT2)/sizeof(mmUNIPHY_REG_TEST_OUTPUT2[0]), 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1", REG_MMIO, 0x1990, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2", REG_MMIO, 0x1991, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3", REG_MMIO, 0x1992, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4", REG_MMIO, 0x1993, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL", REG_MMIO, 0x1994, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV", REG_MMIO, 0x1995, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x1996, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x1997, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x1998, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x1999, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x199a, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x199b, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x199c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL", REG_MMIO, 0x199d, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x199e, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x199f, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1", REG_MMIO, 0x19a0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2", REG_MMIO, 0x19a1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3", REG_MMIO, 0x19a2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4", REG_MMIO, 0x19a3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL", REG_MMIO, 0x19a4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV", REG_MMIO, 0x19a5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x19a6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x19a7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x19a8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x19a9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x19aa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x19ab, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x19ac, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL", REG_MMIO, 0x19ad, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x19ae, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x19af, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1", REG_MMIO, 0x19b0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2", REG_MMIO, 0x19b1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3", REG_MMIO, 0x19b2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4", REG_MMIO, 0x19b3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL", REG_MMIO, 0x19b4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV", REG_MMIO, 0x19b5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x19b6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x19b7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x19b8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x19b9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x19ba, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x19bb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x19bc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL", REG_MMIO, 0x19bd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x19be, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x19bf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1", REG_MMIO, 0x19c0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2", REG_MMIO, 0x19c1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3", REG_MMIO, 0x19c2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4", REG_MMIO, 0x19c3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL", REG_MMIO, 0x19c4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV", REG_MMIO, 0x19c5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x19c6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x19c7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x19c8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x19c9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x19ca, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x19cb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x19cc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL", REG_MMIO, 0x19cd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x19ce, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x19cf, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1", REG_MMIO, 0x19d0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2", REG_MMIO, 0x19d1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3", REG_MMIO, 0x19d2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4", REG_MMIO, 0x19d3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL", REG_MMIO, 0x19d4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV", REG_MMIO, 0x19d5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x19d6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x19d7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x19d8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x19d9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x19da, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x19db, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x19dc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL", REG_MMIO, 0x19dd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x19de, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x19df, NULL, 0, 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE6", REG_MMIO, 0x19e0, &mmDISP_INTERRUPT_STATUS_CONTINUE6[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE6[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE7", REG_MMIO, 0x19e1, &mmDISP_INTERRUPT_STATUS_CONTINUE7[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE7[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE8", REG_MMIO, 0x19e2, &mmDISP_INTERRUPT_STATUS_CONTINUE8[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE8[0]), 0, 0 },
+	{ "mmDISP_INTERRUPT_STATUS_CONTINUE9", REG_MMIO, 0x19e3, &mmDISP_INTERRUPT_STATUS_CONTINUE9[0], sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9)/sizeof(mmDISP_INTERRUPT_STATUS_CONTINUE9[0]), 0, 0 },
+	{ "mmDAC_ENABLE", REG_MMIO, 0x19e4, &mmDAC_ENABLE[0], sizeof(mmDAC_ENABLE)/sizeof(mmDAC_ENABLE[0]), 0, 0 },
+	{ "mmDAC_SOURCE_SELECT", REG_MMIO, 0x19e5, &mmDAC_SOURCE_SELECT[0], sizeof(mmDAC_SOURCE_SELECT)/sizeof(mmDAC_SOURCE_SELECT[0]), 0, 0 },
+	{ "mmDAC_CRC_EN", REG_MMIO, 0x19e6, &mmDAC_CRC_EN[0], sizeof(mmDAC_CRC_EN)/sizeof(mmDAC_CRC_EN[0]), 0, 0 },
+	{ "mmDAC_CRC_CONTROL", REG_MMIO, 0x19e7, &mmDAC_CRC_CONTROL[0], sizeof(mmDAC_CRC_CONTROL)/sizeof(mmDAC_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB_MASK", REG_MMIO, 0x19e8, &mmDAC_CRC_SIG_RGB_MASK[0], sizeof(mmDAC_CRC_SIG_RGB_MASK)/sizeof(mmDAC_CRC_SIG_RGB_MASK[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL_MASK", REG_MMIO, 0x19e9, &mmDAC_CRC_SIG_CONTROL_MASK[0], sizeof(mmDAC_CRC_SIG_CONTROL_MASK)/sizeof(mmDAC_CRC_SIG_CONTROL_MASK[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_RGB", REG_MMIO, 0x19ea, &mmDAC_CRC_SIG_RGB[0], sizeof(mmDAC_CRC_SIG_RGB)/sizeof(mmDAC_CRC_SIG_RGB[0]), 0, 0 },
+	{ "mmDAC_CRC_SIG_CONTROL", REG_MMIO, 0x19eb, &mmDAC_CRC_SIG_CONTROL[0], sizeof(mmDAC_CRC_SIG_CONTROL)/sizeof(mmDAC_CRC_SIG_CONTROL[0]), 0, 0 },
+	{ "mmDAC_SYNC_TRISTATE_CONTROL", REG_MMIO, 0x19ec, &mmDAC_SYNC_TRISTATE_CONTROL[0], sizeof(mmDAC_SYNC_TRISTATE_CONTROL)/sizeof(mmDAC_SYNC_TRISTATE_CONTROL[0]), 0, 0 },
+	{ "mmDAC_STEREOSYNC_SELECT", REG_MMIO, 0x19ed, &mmDAC_STEREOSYNC_SELECT[0], sizeof(mmDAC_STEREOSYNC_SELECT)/sizeof(mmDAC_STEREOSYNC_SELECT[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL", REG_MMIO, 0x19ee, &mmDAC_AUTODETECT_CONTROL[0], sizeof(mmDAC_AUTODETECT_CONTROL)/sizeof(mmDAC_AUTODETECT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL2", REG_MMIO, 0x19ef, &mmDAC_AUTODETECT_CONTROL2[0], sizeof(mmDAC_AUTODETECT_CONTROL2)/sizeof(mmDAC_AUTODETECT_CONTROL2[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_CONTROL3", REG_MMIO, 0x19f0, &mmDAC_AUTODETECT_CONTROL3[0], sizeof(mmDAC_AUTODETECT_CONTROL3)/sizeof(mmDAC_AUTODETECT_CONTROL3[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_STATUS", REG_MMIO, 0x19f1, &mmDAC_AUTODETECT_STATUS[0], sizeof(mmDAC_AUTODETECT_STATUS)/sizeof(mmDAC_AUTODETECT_STATUS[0]), 0, 0 },
+	{ "mmDAC_AUTODETECT_INT_CONTROL", REG_MMIO, 0x19f2, &mmDAC_AUTODETECT_INT_CONTROL[0], sizeof(mmDAC_AUTODETECT_INT_CONTROL)/sizeof(mmDAC_AUTODETECT_INT_CONTROL[0]), 0, 0 },
+	{ "mmDAC_FORCE_OUTPUT_CNTL", REG_MMIO, 0x19f3, &mmDAC_FORCE_OUTPUT_CNTL[0], sizeof(mmDAC_FORCE_OUTPUT_CNTL)/sizeof(mmDAC_FORCE_OUTPUT_CNTL[0]), 0, 0 },
+	{ "mmDAC_FORCE_DATA", REG_MMIO, 0x19f4, &mmDAC_FORCE_DATA[0], sizeof(mmDAC_FORCE_DATA)/sizeof(mmDAC_FORCE_DATA[0]), 0, 0 },
+	{ "mmDAC_POWERDOWN", REG_MMIO, 0x19f5, &mmDAC_POWERDOWN[0], sizeof(mmDAC_POWERDOWN)/sizeof(mmDAC_POWERDOWN[0]), 0, 0 },
+	{ "mmDAC_CONTROL", REG_MMIO, 0x19f6, &mmDAC_CONTROL[0], sizeof(mmDAC_CONTROL)/sizeof(mmDAC_CONTROL[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_ENABLE", REG_MMIO, 0x19f7, &mmDAC_COMPARATOR_ENABLE[0], sizeof(mmDAC_COMPARATOR_ENABLE)/sizeof(mmDAC_COMPARATOR_ENABLE[0]), 0, 0 },
+	{ "mmDAC_COMPARATOR_OUTPUT", REG_MMIO, 0x19f8, &mmDAC_COMPARATOR_OUTPUT[0], sizeof(mmDAC_COMPARATOR_OUTPUT)/sizeof(mmDAC_COMPARATOR_OUTPUT[0]), 0, 0 },
+	{ "mmDAC_PWR_CNTL", REG_MMIO, 0x19f9, &mmDAC_PWR_CNTL[0], sizeof(mmDAC_PWR_CNTL)/sizeof(mmDAC_PWR_CNTL[0]), 0, 0 },
+	{ "mmDAC_DFT_CONFIG", REG_MMIO, 0x19fa, &mmDAC_DFT_CONFIG[0], sizeof(mmDAC_DFT_CONFIG)/sizeof(mmDAC_DFT_CONFIG[0]), 0, 0 },
+	{ "mmDAC_FIFO_STATUS", REG_MMIO, 0x19fb, &mmDAC_FIFO_STATUS[0], sizeof(mmDAC_FIFO_STATUS)/sizeof(mmDAC_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED0", REG_MMIO, 0x19fc, &mmDAC_MACRO_CNTL_RESERVED0[0], sizeof(mmDAC_MACRO_CNTL_RESERVED0)/sizeof(mmDAC_MACRO_CNTL_RESERVED0[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED1", REG_MMIO, 0x19fd, &mmDAC_MACRO_CNTL_RESERVED1[0], sizeof(mmDAC_MACRO_CNTL_RESERVED1)/sizeof(mmDAC_MACRO_CNTL_RESERVED1[0]), 0, 0 },
+	{ "mmBPHYC_DAC_MACRO_CNTL", REG_MMIO, 0x19fd, &mmBPHYC_DAC_MACRO_CNTL[0], sizeof(mmBPHYC_DAC_MACRO_CNTL)/sizeof(mmBPHYC_DAC_MACRO_CNTL[0]), 0, 0 },
+	{ "mmBPHYC_DAC_AUTO_CALIB_CONTROL", REG_MMIO, 0x19fe, &mmBPHYC_DAC_AUTO_CALIB_CONTROL[0], sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL)/sizeof(mmBPHYC_DAC_AUTO_CALIB_CONTROL[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED2", REG_MMIO, 0x19fe, &mmDAC_MACRO_CNTL_RESERVED2[0], sizeof(mmDAC_MACRO_CNTL_RESERVED2)/sizeof(mmDAC_MACRO_CNTL_RESERVED2[0]), 0, 0 },
+	{ "mmDAC_MACRO_CNTL_RESERVED3", REG_MMIO, 0x19ff, &mmDAC_MACRO_CNTL_RESERVED3[0], sizeof(mmDAC_MACRO_CNTL_RESERVED3)/sizeof(mmDAC_MACRO_CNTL_RESERVED3[0]), 0, 0 },
+	{ "mmIMMEDIATE_COMMAND_STATUS", REG_MMIO, 0x1a, &mmIMMEDIATE_COMMAND_STATUS[0], sizeof(mmIMMEDIATE_COMMAND_STATUS)/sizeof(mmIMMEDIATE_COMMAND_STATUS[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_K", REG_SMC, 0x1a, &ixDP_AUX1_DEBUG_K[0], sizeof(ixDP_AUX1_DEBUG_K)/sizeof(ixDP_AUX1_DEBUG_K[0]), 0, 0 },
+	{ "mmDCP0_GRPH_ENABLE", REG_MMIO, 0x1a00, NULL, 0, 0, 0 },
+	{ "mmGRPH_ENABLE", REG_MMIO, 0x1a00, &mmGRPH_ENABLE[0], sizeof(mmGRPH_ENABLE)/sizeof(mmGRPH_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_CONTROL", REG_MMIO, 0x1a01, NULL, 0, 0, 0 },
+	{ "mmGRPH_CONTROL", REG_MMIO, 0x1a01, &mmGRPH_CONTROL[0], sizeof(mmGRPH_CONTROL)/sizeof(mmGRPH_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1a02, NULL, 0, 0, 0 },
+	{ "mmGRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1a02, &mmGRPH_LUT_10BIT_BYPASS[0], sizeof(mmGRPH_LUT_10BIT_BYPASS)/sizeof(mmGRPH_LUT_10BIT_BYPASS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SWAP_CNTL", REG_MMIO, 0x1a03, NULL, 0, 0, 0 },
+	{ "mmGRPH_SWAP_CNTL", REG_MMIO, 0x1a03, &mmGRPH_SWAP_CNTL[0], sizeof(mmGRPH_SWAP_CNTL)/sizeof(mmGRPH_SWAP_CNTL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1a04, NULL, 0, 0, 0 },
+	{ "mmGRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1a04, &mmGRPH_PRIMARY_SURFACE_ADDRESS[0], sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS)/sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a05, NULL, 0, 0, 0 },
+	{ "mmGRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a05, &mmGRPH_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS)/sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PITCH", REG_MMIO, 0x1a06, NULL, 0, 0, 0 },
+	{ "mmGRPH_PITCH", REG_MMIO, 0x1a06, &mmGRPH_PITCH[0], sizeof(mmGRPH_PITCH)/sizeof(mmGRPH_PITCH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a07, NULL, 0, 0, 0 },
+	{ "mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a07, &mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a08, NULL, 0, 0, 0 },
+	{ "mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a08, &mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1a09, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1a09, &mmGRPH_SURFACE_OFFSET_X[0], sizeof(mmGRPH_SURFACE_OFFSET_X)/sizeof(mmGRPH_SURFACE_OFFSET_X[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1a0a, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1a0a, &mmGRPH_SURFACE_OFFSET_Y[0], sizeof(mmGRPH_SURFACE_OFFSET_Y)/sizeof(mmGRPH_SURFACE_OFFSET_Y[0]), 0, 0 },
+	{ "mmDCP0_GRPH_X_START", REG_MMIO, 0x1a0b, NULL, 0, 0, 0 },
+	{ "mmGRPH_X_START", REG_MMIO, 0x1a0b, &mmGRPH_X_START[0], sizeof(mmGRPH_X_START)/sizeof(mmGRPH_X_START[0]), 0, 0 },
+	{ "mmDCP0_GRPH_Y_START", REG_MMIO, 0x1a0c, NULL, 0, 0, 0 },
+	{ "mmGRPH_Y_START", REG_MMIO, 0x1a0c, &mmGRPH_Y_START[0], sizeof(mmGRPH_Y_START)/sizeof(mmGRPH_Y_START[0]), 0, 0 },
+	{ "mmDCP0_GRPH_X_END", REG_MMIO, 0x1a0d, NULL, 0, 0, 0 },
+	{ "mmGRPH_X_END", REG_MMIO, 0x1a0d, &mmGRPH_X_END[0], sizeof(mmGRPH_X_END)/sizeof(mmGRPH_X_END[0]), 0, 0 },
+	{ "mmDCP0_GRPH_Y_END", REG_MMIO, 0x1a0e, NULL, 0, 0, 0 },
+	{ "mmGRPH_Y_END", REG_MMIO, 0x1a0e, &mmGRPH_Y_END[0], sizeof(mmGRPH_Y_END)/sizeof(mmGRPH_Y_END[0]), 0, 0 },
+	{ "mmDCP0_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1a10, NULL, 0, 0, 0 },
+	{ "mmINPUT_GAMMA_CONTROL", REG_MMIO, 0x1a10, &mmINPUT_GAMMA_CONTROL[0], sizeof(mmINPUT_GAMMA_CONTROL)/sizeof(mmINPUT_GAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_UPDATE", REG_MMIO, 0x1a11, NULL, 0, 0, 0 },
+	{ "mmGRPH_UPDATE", REG_MMIO, 0x1a11, &mmGRPH_UPDATE[0], sizeof(mmGRPH_UPDATE)/sizeof(mmGRPH_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_CONTROL", REG_MMIO, 0x1a12, NULL, 0, 0, 0 },
+	{ "mmGRPH_FLIP_CONTROL", REG_MMIO, 0x1a12, &mmGRPH_FLIP_CONTROL[0], sizeof(mmGRPH_FLIP_CONTROL)/sizeof(mmGRPH_FLIP_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a13, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a13, &mmGRPH_SURFACE_ADDRESS_INUSE[0], sizeof(mmGRPH_SURFACE_ADDRESS_INUSE)/sizeof(mmGRPH_SURFACE_ADDRESS_INUSE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_CONTROL", REG_MMIO, 0x1a14, NULL, 0, 0, 0 },
+	{ "mmGRPH_DFQ_CONTROL", REG_MMIO, 0x1a14, &mmGRPH_DFQ_CONTROL[0], sizeof(mmGRPH_DFQ_CONTROL)/sizeof(mmGRPH_DFQ_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_DFQ_STATUS", REG_MMIO, 0x1a15, NULL, 0, 0, 0 },
+	{ "mmGRPH_DFQ_STATUS", REG_MMIO, 0x1a15, &mmGRPH_DFQ_STATUS[0], sizeof(mmGRPH_DFQ_STATUS)/sizeof(mmGRPH_DFQ_STATUS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1a16, NULL, 0, 0, 0 },
+	{ "mmGRPH_INTERRUPT_STATUS", REG_MMIO, 0x1a16, &mmGRPH_INTERRUPT_STATUS[0], sizeof(mmGRPH_INTERRUPT_STATUS)/sizeof(mmGRPH_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1a17, NULL, 0, 0, 0 },
+	{ "mmGRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1a17, &mmGRPH_INTERRUPT_CONTROL[0], sizeof(mmGRPH_INTERRUPT_CONTROL)/sizeof(mmGRPH_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a18, NULL, 0, 0, 0 },
+	{ "mmGRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a18, &mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[0], sizeof(mmGRPH_SURFACE_ADDRESS_HIGH_INUSE)/sizeof(mmGRPH_SURFACE_ADDRESS_HIGH_INUSE[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1a19, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1a19, &mmGRPH_COMPRESS_SURFACE_ADDRESS[0], sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS)/sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1a1a, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_PITCH", REG_MMIO, 0x1a1a, &mmGRPH_COMPRESS_PITCH[0], sizeof(mmGRPH_COMPRESS_PITCH)/sizeof(mmGRPH_COMPRESS_PITCH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a1b, NULL, 0, 0, 0 },
+	{ "mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a1b, &mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_OVL_ENABLE", REG_MMIO, 0x1a1c, NULL, 0, 0, 0 },
+	{ "mmOVL_ENABLE", REG_MMIO, 0x1a1c, &mmOVL_ENABLE[0], sizeof(mmOVL_ENABLE)/sizeof(mmOVL_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_OVL_CONTROL1", REG_MMIO, 0x1a1d, NULL, 0, 0, 0 },
+	{ "mmOVL_CONTROL1", REG_MMIO, 0x1a1d, &mmOVL_CONTROL1[0], sizeof(mmOVL_CONTROL1)/sizeof(mmOVL_CONTROL1[0]), 0, 0 },
+	{ "mmDCP0_OVL_CONTROL2", REG_MMIO, 0x1a1e, NULL, 0, 0, 0 },
+	{ "mmOVL_CONTROL2", REG_MMIO, 0x1a1e, &mmOVL_CONTROL2[0], sizeof(mmOVL_CONTROL2)/sizeof(mmOVL_CONTROL2[0]), 0, 0 },
+	{ "mmDCP0_OVL_SWAP_CNTL", REG_MMIO, 0x1a1f, NULL, 0, 0, 0 },
+	{ "mmOVL_SWAP_CNTL", REG_MMIO, 0x1a1f, &mmOVL_SWAP_CNTL[0], sizeof(mmOVL_SWAP_CNTL)/sizeof(mmOVL_SWAP_CNTL[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS", REG_MMIO, 0x1a20, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_ADDRESS", REG_MMIO, 0x1a20, &mmOVL_SURFACE_ADDRESS[0], sizeof(mmOVL_SURFACE_ADDRESS)/sizeof(mmOVL_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_OVL_PITCH", REG_MMIO, 0x1a21, NULL, 0, 0, 0 },
+	{ "mmOVL_PITCH", REG_MMIO, 0x1a21, &mmOVL_PITCH[0], sizeof(mmOVL_PITCH)/sizeof(mmOVL_PITCH[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a22, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a22, &mmOVL_SURFACE_ADDRESS_HIGH[0], sizeof(mmOVL_SURFACE_ADDRESS_HIGH)/sizeof(mmOVL_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x1a23, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_OFFSET_X", REG_MMIO, 0x1a23, &mmOVL_SURFACE_OFFSET_X[0], sizeof(mmOVL_SURFACE_OFFSET_X)/sizeof(mmOVL_SURFACE_OFFSET_X[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1a24, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1a24, &mmOVL_SURFACE_OFFSET_Y[0], sizeof(mmOVL_SURFACE_OFFSET_Y)/sizeof(mmOVL_SURFACE_OFFSET_Y[0]), 0, 0 },
+	{ "mmDCP0_OVL_START", REG_MMIO, 0x1a25, NULL, 0, 0, 0 },
+	{ "mmOVL_START", REG_MMIO, 0x1a25, &mmOVL_START[0], sizeof(mmOVL_START)/sizeof(mmOVL_START[0]), 0, 0 },
+	{ "mmDCP0_OVL_END", REG_MMIO, 0x1a26, NULL, 0, 0, 0 },
+	{ "mmOVL_END", REG_MMIO, 0x1a26, &mmOVL_END[0], sizeof(mmOVL_END)/sizeof(mmOVL_END[0]), 0, 0 },
+	{ "mmDCP0_OVL_UPDATE", REG_MMIO, 0x1a27, NULL, 0, 0, 0 },
+	{ "mmOVL_UPDATE", REG_MMIO, 0x1a27, &mmOVL_UPDATE[0], sizeof(mmOVL_UPDATE)/sizeof(mmOVL_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a28, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1a28, &mmOVL_SURFACE_ADDRESS_INUSE[0], sizeof(mmOVL_SURFACE_ADDRESS_INUSE)/sizeof(mmOVL_SURFACE_ADDRESS_INUSE[0]), 0, 0 },
+	{ "mmDCP0_OVL_DFQ_CONTROL", REG_MMIO, 0x1a29, NULL, 0, 0, 0 },
+	{ "mmOVL_DFQ_CONTROL", REG_MMIO, 0x1a29, &mmOVL_DFQ_CONTROL[0], sizeof(mmOVL_DFQ_CONTROL)/sizeof(mmOVL_DFQ_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OVL_DFQ_STATUS", REG_MMIO, 0x1a2a, NULL, 0, 0, 0 },
+	{ "mmOVL_DFQ_STATUS", REG_MMIO, 0x1a2a, &mmOVL_DFQ_STATUS[0], sizeof(mmOVL_DFQ_STATUS)/sizeof(mmOVL_DFQ_STATUS[0]), 0, 0 },
+	{ "mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a2b, NULL, 0, 0, 0 },
+	{ "mmOVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1a2b, &mmOVL_SURFACE_ADDRESS_HIGH_INUSE[0], sizeof(mmOVL_SURFACE_ADDRESS_HIGH_INUSE)/sizeof(mmOVL_SURFACE_ADDRESS_HIGH_INUSE[0]), 0, 0 },
+	{ "mmDCP0_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1a2c, NULL, 0, 0, 0 },
+	{ "mmOVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1a2c, &mmOVLSCL_EDGE_PIXEL_CNTL[0], sizeof(mmOVLSCL_EDGE_PIXEL_CNTL)/sizeof(mmOVLSCL_EDGE_PIXEL_CNTL[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1a2d, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_GRPH_CONTROL", REG_MMIO, 0x1a2d, &mmPRESCALE_GRPH_CONTROL[0], sizeof(mmPRESCALE_GRPH_CONTROL)/sizeof(mmPRESCALE_GRPH_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1a2e, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1a2e, &mmPRESCALE_VALUES_GRPH_R[0], sizeof(mmPRESCALE_VALUES_GRPH_R)/sizeof(mmPRESCALE_VALUES_GRPH_R[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1a2f, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1a2f, &mmPRESCALE_VALUES_GRPH_G[0], sizeof(mmPRESCALE_VALUES_GRPH_G)/sizeof(mmPRESCALE_VALUES_GRPH_G[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1a30, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1a30, &mmPRESCALE_VALUES_GRPH_B[0], sizeof(mmPRESCALE_VALUES_GRPH_B)/sizeof(mmPRESCALE_VALUES_GRPH_B[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_OVL_CONTROL", REG_MMIO, 0x1a31, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_OVL_CONTROL", REG_MMIO, 0x1a31, &mmPRESCALE_OVL_CONTROL[0], sizeof(mmPRESCALE_OVL_CONTROL)/sizeof(mmPRESCALE_OVL_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1a32, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1a32, &mmPRESCALE_VALUES_OVL_CB[0], sizeof(mmPRESCALE_VALUES_OVL_CB)/sizeof(mmPRESCALE_VALUES_OVL_CB[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1a33, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1a33, &mmPRESCALE_VALUES_OVL_Y[0], sizeof(mmPRESCALE_VALUES_OVL_Y)/sizeof(mmPRESCALE_VALUES_OVL_Y[0]), 0, 0 },
+	{ "mmDCP0_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1a34, NULL, 0, 0, 0 },
+	{ "mmPRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1a34, &mmPRESCALE_VALUES_OVL_CR[0], sizeof(mmPRESCALE_VALUES_OVL_CR)/sizeof(mmPRESCALE_VALUES_OVL_CR[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_CONTROL", REG_MMIO, 0x1a35, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_CONTROL", REG_MMIO, 0x1a35, &mmINPUT_CSC_CONTROL[0], sizeof(mmINPUT_CSC_CONTROL)/sizeof(mmINPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C11_C12", REG_MMIO, 0x1a36, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C11_C12", REG_MMIO, 0x1a36, &mmINPUT_CSC_C11_C12[0], sizeof(mmINPUT_CSC_C11_C12)/sizeof(mmINPUT_CSC_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C13_C14", REG_MMIO, 0x1a37, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C13_C14", REG_MMIO, 0x1a37, &mmINPUT_CSC_C13_C14[0], sizeof(mmINPUT_CSC_C13_C14)/sizeof(mmINPUT_CSC_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C21_C22", REG_MMIO, 0x1a38, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C21_C22", REG_MMIO, 0x1a38, &mmINPUT_CSC_C21_C22[0], sizeof(mmINPUT_CSC_C21_C22)/sizeof(mmINPUT_CSC_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C23_C24", REG_MMIO, 0x1a39, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C23_C24", REG_MMIO, 0x1a39, &mmINPUT_CSC_C23_C24[0], sizeof(mmINPUT_CSC_C23_C24)/sizeof(mmINPUT_CSC_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C31_C32", REG_MMIO, 0x1a3a, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C31_C32", REG_MMIO, 0x1a3a, &mmINPUT_CSC_C31_C32[0], sizeof(mmINPUT_CSC_C31_C32)/sizeof(mmINPUT_CSC_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_INPUT_CSC_C33_C34", REG_MMIO, 0x1a3b, NULL, 0, 0, 0 },
+	{ "mmINPUT_CSC_C33_C34", REG_MMIO, 0x1a3b, &mmINPUT_CSC_C33_C34[0], sizeof(mmINPUT_CSC_C33_C34)/sizeof(mmINPUT_CSC_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1a3c, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_CONTROL", REG_MMIO, 0x1a3c, &mmOUTPUT_CSC_CONTROL[0], sizeof(mmOUTPUT_CSC_CONTROL)/sizeof(mmOUTPUT_CSC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1a3d, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C11_C12", REG_MMIO, 0x1a3d, &mmOUTPUT_CSC_C11_C12[0], sizeof(mmOUTPUT_CSC_C11_C12)/sizeof(mmOUTPUT_CSC_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1a3e, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C13_C14", REG_MMIO, 0x1a3e, &mmOUTPUT_CSC_C13_C14[0], sizeof(mmOUTPUT_CSC_C13_C14)/sizeof(mmOUTPUT_CSC_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1a3f, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C21_C22", REG_MMIO, 0x1a3f, &mmOUTPUT_CSC_C21_C22[0], sizeof(mmOUTPUT_CSC_C21_C22)/sizeof(mmOUTPUT_CSC_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1a40, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C23_C24", REG_MMIO, 0x1a40, &mmOUTPUT_CSC_C23_C24[0], sizeof(mmOUTPUT_CSC_C23_C24)/sizeof(mmOUTPUT_CSC_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1a41, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C31_C32", REG_MMIO, 0x1a41, &mmOUTPUT_CSC_C31_C32[0], sizeof(mmOUTPUT_CSC_C31_C32)/sizeof(mmOUTPUT_CSC_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1a42, NULL, 0, 0, 0 },
+	{ "mmOUTPUT_CSC_C33_C34", REG_MMIO, 0x1a42, &mmOUTPUT_CSC_C33_C34[0], sizeof(mmOUTPUT_CSC_C33_C34)/sizeof(mmOUTPUT_CSC_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1a43, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1a43, &mmCOMM_MATRIXA_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXA_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXA_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1a44, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1a44, &mmCOMM_MATRIXA_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXA_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXA_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1a45, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1a45, &mmCOMM_MATRIXA_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXA_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXA_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1a46, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1a46, &mmCOMM_MATRIXA_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXA_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXA_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1a47, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1a47, &mmCOMM_MATRIXA_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXA_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXA_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1a48, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1a48, &mmCOMM_MATRIXA_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXA_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXA_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1a49, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1a49, &mmCOMM_MATRIXB_TRANS_C11_C12[0], sizeof(mmCOMM_MATRIXB_TRANS_C11_C12)/sizeof(mmCOMM_MATRIXB_TRANS_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1a4a, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1a4a, &mmCOMM_MATRIXB_TRANS_C13_C14[0], sizeof(mmCOMM_MATRIXB_TRANS_C13_C14)/sizeof(mmCOMM_MATRIXB_TRANS_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1a4b, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1a4b, &mmCOMM_MATRIXB_TRANS_C21_C22[0], sizeof(mmCOMM_MATRIXB_TRANS_C21_C22)/sizeof(mmCOMM_MATRIXB_TRANS_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1a4c, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1a4c, &mmCOMM_MATRIXB_TRANS_C23_C24[0], sizeof(mmCOMM_MATRIXB_TRANS_C23_C24)/sizeof(mmCOMM_MATRIXB_TRANS_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1a4d, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1a4d, &mmCOMM_MATRIXB_TRANS_C31_C32[0], sizeof(mmCOMM_MATRIXB_TRANS_C31_C32)/sizeof(mmCOMM_MATRIXB_TRANS_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1a4e, NULL, 0, 0, 0 },
+	{ "mmCOMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1a4e, &mmCOMM_MATRIXB_TRANS_C33_C34[0], sizeof(mmCOMM_MATRIXB_TRANS_C33_C34)/sizeof(mmCOMM_MATRIXB_TRANS_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DENORM_CONTROL", REG_MMIO, 0x1a50, NULL, 0, 0, 0 },
+	{ "mmDENORM_CONTROL", REG_MMIO, 0x1a50, &mmDENORM_CONTROL[0], sizeof(mmDENORM_CONTROL)/sizeof(mmDENORM_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_ROUND_CONTROL", REG_MMIO, 0x1a51, NULL, 0, 0, 0 },
+	{ "mmOUT_ROUND_CONTROL", REG_MMIO, 0x1a51, &mmOUT_ROUND_CONTROL[0], sizeof(mmOUT_ROUND_CONTROL)/sizeof(mmOUT_ROUND_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1a52, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1a52, &mmOUT_CLAMP_CONTROL_R_CR[0], sizeof(mmOUT_CLAMP_CONTROL_R_CR)/sizeof(mmOUT_CLAMP_CONTROL_R_CR[0]), 0, 0 },
+	{ "mmDCP0_KEY_CONTROL", REG_MMIO, 0x1a53, NULL, 0, 0, 0 },
+	{ "mmKEY_CONTROL", REG_MMIO, 0x1a53, &mmKEY_CONTROL[0], sizeof(mmKEY_CONTROL)/sizeof(mmKEY_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_ALPHA", REG_MMIO, 0x1a54, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_ALPHA", REG_MMIO, 0x1a54, &mmKEY_RANGE_ALPHA[0], sizeof(mmKEY_RANGE_ALPHA)/sizeof(mmKEY_RANGE_ALPHA[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_RED", REG_MMIO, 0x1a55, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_RED", REG_MMIO, 0x1a55, &mmKEY_RANGE_RED[0], sizeof(mmKEY_RANGE_RED)/sizeof(mmKEY_RANGE_RED[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_GREEN", REG_MMIO, 0x1a56, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_GREEN", REG_MMIO, 0x1a56, &mmKEY_RANGE_GREEN[0], sizeof(mmKEY_RANGE_GREEN)/sizeof(mmKEY_RANGE_GREEN[0]), 0, 0 },
+	{ "mmDCP0_KEY_RANGE_BLUE", REG_MMIO, 0x1a57, NULL, 0, 0, 0 },
+	{ "mmKEY_RANGE_BLUE", REG_MMIO, 0x1a57, &mmKEY_RANGE_BLUE[0], sizeof(mmKEY_RANGE_BLUE)/sizeof(mmKEY_RANGE_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DEGAMMA_CONTROL", REG_MMIO, 0x1a58, NULL, 0, 0, 0 },
+	{ "mmDEGAMMA_CONTROL", REG_MMIO, 0x1a58, &mmDEGAMMA_CONTROL[0], sizeof(mmDEGAMMA_CONTROL)/sizeof(mmDEGAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1a59, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_CONTROL", REG_MMIO, 0x1a59, &mmGAMUT_REMAP_CONTROL[0], sizeof(mmGAMUT_REMAP_CONTROL)/sizeof(mmGAMUT_REMAP_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1a5a, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C11_C12", REG_MMIO, 0x1a5a, &mmGAMUT_REMAP_C11_C12[0], sizeof(mmGAMUT_REMAP_C11_C12)/sizeof(mmGAMUT_REMAP_C11_C12[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1a5b, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C13_C14", REG_MMIO, 0x1a5b, &mmGAMUT_REMAP_C13_C14[0], sizeof(mmGAMUT_REMAP_C13_C14)/sizeof(mmGAMUT_REMAP_C13_C14[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1a5c, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C21_C22", REG_MMIO, 0x1a5c, &mmGAMUT_REMAP_C21_C22[0], sizeof(mmGAMUT_REMAP_C21_C22)/sizeof(mmGAMUT_REMAP_C21_C22[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1a5d, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C23_C24", REG_MMIO, 0x1a5d, &mmGAMUT_REMAP_C23_C24[0], sizeof(mmGAMUT_REMAP_C23_C24)/sizeof(mmGAMUT_REMAP_C23_C24[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1a5e, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C31_C32", REG_MMIO, 0x1a5e, &mmGAMUT_REMAP_C31_C32[0], sizeof(mmGAMUT_REMAP_C31_C32)/sizeof(mmGAMUT_REMAP_C31_C32[0]), 0, 0 },
+	{ "mmDCP0_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1a5f, NULL, 0, 0, 0 },
+	{ "mmGAMUT_REMAP_C33_C34", REG_MMIO, 0x1a5f, &mmGAMUT_REMAP_C33_C34[0], sizeof(mmGAMUT_REMAP_C33_C34)/sizeof(mmGAMUT_REMAP_C33_C34[0]), 0, 0 },
+	{ "mmDCP0_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1a60, NULL, 0, 0, 0 },
+	{ "mmDCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1a60, &mmDCP_SPATIAL_DITHER_CNTL[0], sizeof(mmDCP_SPATIAL_DITHER_CNTL)/sizeof(mmDCP_SPATIAL_DITHER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_DCP_RANDOM_SEEDS", REG_MMIO, 0x1a61, NULL, 0, 0, 0 },
+	{ "mmDCP_RANDOM_SEEDS", REG_MMIO, 0x1a61, &mmDCP_RANDOM_SEEDS[0], sizeof(mmDCP_RANDOM_SEEDS)/sizeof(mmDCP_RANDOM_SEEDS[0]), 0, 0 },
+	{ "mmDCP0_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1a65, NULL, 0, 0, 0 },
+	{ "mmDCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1a65, &mmDCP_FP_CONVERTED_FIELD[0], sizeof(mmDCP_FP_CONVERTED_FIELD)/sizeof(mmDCP_FP_CONVERTED_FIELD[0]), 0, 0 },
+	{ "mmDCP0_CUR_CONTROL", REG_MMIO, 0x1a66, NULL, 0, 0, 0 },
+	{ "mmCUR_CONTROL", REG_MMIO, 0x1a66, &mmCUR_CONTROL[0], sizeof(mmCUR_CONTROL)/sizeof(mmCUR_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1a67, NULL, 0, 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS", REG_MMIO, 0x1a67, &mmCUR_SURFACE_ADDRESS[0], sizeof(mmCUR_SURFACE_ADDRESS)/sizeof(mmCUR_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_CUR_SIZE", REG_MMIO, 0x1a68, NULL, 0, 0, 0 },
+	{ "mmCUR_SIZE", REG_MMIO, 0x1a68, &mmCUR_SIZE[0], sizeof(mmCUR_SIZE)/sizeof(mmCUR_SIZE[0]), 0, 0 },
+	{ "mmDCP0_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a69, NULL, 0, 0, 0 },
+	{ "mmCUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a69, &mmCUR_SURFACE_ADDRESS_HIGH[0], sizeof(mmCUR_SURFACE_ADDRESS_HIGH)/sizeof(mmCUR_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_CUR_POSITION", REG_MMIO, 0x1a6a, NULL, 0, 0, 0 },
+	{ "mmCUR_POSITION", REG_MMIO, 0x1a6a, &mmCUR_POSITION[0], sizeof(mmCUR_POSITION)/sizeof(mmCUR_POSITION[0]), 0, 0 },
+	{ "mmDCP0_CUR_HOT_SPOT", REG_MMIO, 0x1a6b, NULL, 0, 0, 0 },
+	{ "mmCUR_HOT_SPOT", REG_MMIO, 0x1a6b, &mmCUR_HOT_SPOT[0], sizeof(mmCUR_HOT_SPOT)/sizeof(mmCUR_HOT_SPOT[0]), 0, 0 },
+	{ "mmDCP0_CUR_COLOR1", REG_MMIO, 0x1a6c, NULL, 0, 0, 0 },
+	{ "mmCUR_COLOR1", REG_MMIO, 0x1a6c, &mmCUR_COLOR1[0], sizeof(mmCUR_COLOR1)/sizeof(mmCUR_COLOR1[0]), 0, 0 },
+	{ "mmDCP0_CUR_COLOR2", REG_MMIO, 0x1a6d, NULL, 0, 0, 0 },
+	{ "mmCUR_COLOR2", REG_MMIO, 0x1a6d, &mmCUR_COLOR2[0], sizeof(mmCUR_COLOR2)/sizeof(mmCUR_COLOR2[0]), 0, 0 },
+	{ "mmDCP0_CUR_UPDATE", REG_MMIO, 0x1a6e, NULL, 0, 0, 0 },
+	{ "mmCUR_UPDATE", REG_MMIO, 0x1a6e, &mmCUR_UPDATE[0], sizeof(mmCUR_UPDATE)/sizeof(mmCUR_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_CUR2_CONTROL", REG_MMIO, 0x1a6f, NULL, 0, 0, 0 },
+	{ "mmCUR2_CONTROL", REG_MMIO, 0x1a6f, &mmCUR2_CONTROL[0], sizeof(mmCUR2_CONTROL)/sizeof(mmCUR2_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_CUR2_SURFACE_ADDRESS", REG_MMIO, 0x1a70, NULL, 0, 0, 0 },
+	{ "mmCUR2_SURFACE_ADDRESS", REG_MMIO, 0x1a70, &mmCUR2_SURFACE_ADDRESS[0], sizeof(mmCUR2_SURFACE_ADDRESS)/sizeof(mmCUR2_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_CUR2_SIZE", REG_MMIO, 0x1a71, NULL, 0, 0, 0 },
+	{ "mmCUR2_SIZE", REG_MMIO, 0x1a71, &mmCUR2_SIZE[0], sizeof(mmCUR2_SIZE)/sizeof(mmCUR2_SIZE[0]), 0, 0 },
+	{ "mmDCP0_CUR2_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a72, NULL, 0, 0, 0 },
+	{ "mmCUR2_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a72, &mmCUR2_SURFACE_ADDRESS_HIGH[0], sizeof(mmCUR2_SURFACE_ADDRESS_HIGH)/sizeof(mmCUR2_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_CUR2_POSITION", REG_MMIO, 0x1a73, NULL, 0, 0, 0 },
+	{ "mmCUR2_POSITION", REG_MMIO, 0x1a73, &mmCUR2_POSITION[0], sizeof(mmCUR2_POSITION)/sizeof(mmCUR2_POSITION[0]), 0, 0 },
+	{ "mmDCP0_CUR2_HOT_SPOT", REG_MMIO, 0x1a74, NULL, 0, 0, 0 },
+	{ "mmCUR2_HOT_SPOT", REG_MMIO, 0x1a74, &mmCUR2_HOT_SPOT[0], sizeof(mmCUR2_HOT_SPOT)/sizeof(mmCUR2_HOT_SPOT[0]), 0, 0 },
+	{ "mmDCP0_CUR2_COLOR1", REG_MMIO, 0x1a75, NULL, 0, 0, 0 },
+	{ "mmCUR2_COLOR1", REG_MMIO, 0x1a75, &mmCUR2_COLOR1[0], sizeof(mmCUR2_COLOR1)/sizeof(mmCUR2_COLOR1[0]), 0, 0 },
+	{ "mmDCP0_CUR2_COLOR2", REG_MMIO, 0x1a76, NULL, 0, 0, 0 },
+	{ "mmCUR2_COLOR2", REG_MMIO, 0x1a76, &mmCUR2_COLOR2[0], sizeof(mmCUR2_COLOR2)/sizeof(mmCUR2_COLOR2[0]), 0, 0 },
+	{ "mmDCP0_CUR2_UPDATE", REG_MMIO, 0x1a77, NULL, 0, 0, 0 },
+	{ "mmCUR2_UPDATE", REG_MMIO, 0x1a77, &mmCUR2_UPDATE[0], sizeof(mmCUR2_UPDATE)/sizeof(mmCUR2_UPDATE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_RW_MODE", REG_MMIO, 0x1a78, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_RW_MODE", REG_MMIO, 0x1a78, &mmDC_LUT_RW_MODE[0], sizeof(mmDC_LUT_RW_MODE)/sizeof(mmDC_LUT_RW_MODE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_RW_INDEX", REG_MMIO, 0x1a79, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_RW_INDEX", REG_MMIO, 0x1a79, &mmDC_LUT_RW_INDEX[0], sizeof(mmDC_LUT_RW_INDEX)/sizeof(mmDC_LUT_RW_INDEX[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1a7a, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_SEQ_COLOR", REG_MMIO, 0x1a7a, &mmDC_LUT_SEQ_COLOR[0], sizeof(mmDC_LUT_SEQ_COLOR)/sizeof(mmDC_LUT_SEQ_COLOR[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_PWL_DATA", REG_MMIO, 0x1a7b, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_PWL_DATA", REG_MMIO, 0x1a7b, &mmDC_LUT_PWL_DATA[0], sizeof(mmDC_LUT_PWL_DATA)/sizeof(mmDC_LUT_PWL_DATA[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_30_COLOR", REG_MMIO, 0x1a7c, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_30_COLOR", REG_MMIO, 0x1a7c, &mmDC_LUT_30_COLOR[0], sizeof(mmDC_LUT_30_COLOR)/sizeof(mmDC_LUT_30_COLOR[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1a7d, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1a7d, &mmDC_LUT_VGA_ACCESS_ENABLE[0], sizeof(mmDC_LUT_VGA_ACCESS_ENABLE)/sizeof(mmDC_LUT_VGA_ACCESS_ENABLE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1a7e, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1a7e, &mmDC_LUT_WRITE_EN_MASK[0], sizeof(mmDC_LUT_WRITE_EN_MASK)/sizeof(mmDC_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_AUTOFILL", REG_MMIO, 0x1a7f, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_AUTOFILL", REG_MMIO, 0x1a7f, &mmDC_LUT_AUTOFILL[0], sizeof(mmDC_LUT_AUTOFILL)/sizeof(mmDC_LUT_AUTOFILL[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_CONTROL", REG_MMIO, 0x1a80, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_CONTROL", REG_MMIO, 0x1a80, &mmDC_LUT_CONTROL[0], sizeof(mmDC_LUT_CONTROL)/sizeof(mmDC_LUT_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1a81, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1a81, &mmDC_LUT_BLACK_OFFSET_BLUE[0], sizeof(mmDC_LUT_BLACK_OFFSET_BLUE)/sizeof(mmDC_LUT_BLACK_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1a82, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1a82, &mmDC_LUT_BLACK_OFFSET_GREEN[0], sizeof(mmDC_LUT_BLACK_OFFSET_GREEN)/sizeof(mmDC_LUT_BLACK_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1a83, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1a83, &mmDC_LUT_BLACK_OFFSET_RED[0], sizeof(mmDC_LUT_BLACK_OFFSET_RED)/sizeof(mmDC_LUT_BLACK_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1a84, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1a84, &mmDC_LUT_WHITE_OFFSET_BLUE[0], sizeof(mmDC_LUT_WHITE_OFFSET_BLUE)/sizeof(mmDC_LUT_WHITE_OFFSET_BLUE[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1a85, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1a85, &mmDC_LUT_WHITE_OFFSET_GREEN[0], sizeof(mmDC_LUT_WHITE_OFFSET_GREEN)/sizeof(mmDC_LUT_WHITE_OFFSET_GREEN[0]), 0, 0 },
+	{ "mmDCP0_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1a86, NULL, 0, 0, 0 },
+	{ "mmDC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1a86, &mmDC_LUT_WHITE_OFFSET_RED[0], sizeof(mmDC_LUT_WHITE_OFFSET_RED)/sizeof(mmDC_LUT_WHITE_OFFSET_RED[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CONTROL", REG_MMIO, 0x1a87, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_CONTROL", REG_MMIO, 0x1a87, &mmDCP_CRC_CONTROL[0], sizeof(mmDCP_CRC_CONTROL)/sizeof(mmDCP_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_MASK", REG_MMIO, 0x1a88, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_MASK", REG_MMIO, 0x1a88, &mmDCP_CRC_MASK[0], sizeof(mmDCP_CRC_MASK)/sizeof(mmDCP_CRC_MASK[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_CURRENT", REG_MMIO, 0x1a89, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_CURRENT", REG_MMIO, 0x1a89, &mmDCP_CRC_CURRENT[0], sizeof(mmDCP_CRC_CURRENT)/sizeof(mmDCP_CRC_CURRENT[0]), 0, 0 },
+	{ "mmDCP0_DCP_CRC_LAST", REG_MMIO, 0x1a8b, NULL, 0, 0, 0 },
+	{ "mmDCP_CRC_LAST", REG_MMIO, 0x1a8b, &mmDCP_CRC_LAST[0], sizeof(mmDCP_CRC_LAST)/sizeof(mmDCP_CRC_LAST[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG", REG_MMIO, 0x1a8d, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG", REG_MMIO, 0x1a8d, &mmDCP_DEBUG[0], sizeof(mmDCP_DEBUG)/sizeof(mmDCP_DEBUG[0]), 0, 0 },
+	{ "mmDCP0_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1a8e, NULL, 0, 0, 0 },
+	{ "mmGRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1a8e, &mmGRPH_FLIP_RATE_CNTL[0], sizeof(mmGRPH_FLIP_RATE_CNTL)/sizeof(mmGRPH_FLIP_RATE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_DCP_GSL_CONTROL", REG_MMIO, 0x1a90, NULL, 0, 0, 0 },
+	{ "mmDCP_GSL_CONTROL", REG_MMIO, 0x1a90, &mmDCP_GSL_CONTROL[0], sizeof(mmDCP_GSL_CONTROL)/sizeof(mmDCP_GSL_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1a91, NULL, 0, 0, 0 },
+	{ "mmDCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1a91, &mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[0], sizeof(mmDCP_LB_DATA_GAP_BETWEEN_CHUNK)/sizeof(mmDCP_LB_DATA_GAP_BETWEEN_CHUNK[0]), 0, 0 },
+	{ "mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a92, NULL, 0, 0, 0 },
+	{ "mmOVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1a92, &mmOVL_SECONDARY_SURFACE_ADDRESS[0], sizeof(mmOVL_SECONDARY_SURFACE_ADDRESS)/sizeof(mmOVL_SECONDARY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x1a93, NULL, 0, 0, 0 },
+	{ "mmOVL_STEREOSYNC_FLIP", REG_MMIO, 0x1a93, &mmOVL_STEREOSYNC_FLIP[0], sizeof(mmOVL_STEREOSYNC_FLIP)/sizeof(mmOVL_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a94, NULL, 0, 0, 0 },
+	{ "mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1a94, &mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH[0], sizeof(mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH)/sizeof(mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1a95, NULL, 0, 0, 0 },
+	{ "mmDCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1a95, &mmDCP_TEST_DEBUG_INDEX[0], sizeof(mmDCP_TEST_DEBUG_INDEX)/sizeof(mmDCP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCP0_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1a96, NULL, 0, 0, 0 },
+	{ "mmDCP_TEST_DEBUG_DATA", REG_MMIO, 0x1a96, &mmDCP_TEST_DEBUG_DATA[0], sizeof(mmDCP_TEST_DEBUG_DATA)/sizeof(mmDCP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCP0_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1a97, NULL, 0, 0, 0 },
+	{ "mmGRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1a97, &mmGRPH_STEREOSYNC_FLIP[0], sizeof(mmGRPH_STEREOSYNC_FLIP)/sizeof(mmGRPH_STEREOSYNC_FLIP[0]), 0, 0 },
+	{ "mmDCP0_DCP_DEBUG2", REG_MMIO, 0x1a98, NULL, 0, 0, 0 },
+	{ "mmDCP_DEBUG2", REG_MMIO, 0x1a98, &mmDCP_DEBUG2[0], sizeof(mmDCP_DEBUG2)/sizeof(mmDCP_DEBUG2[0]), 0, 0 },
+	{ "mmDCP0_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1a99, NULL, 0, 0, 0 },
+	{ "mmCUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1a99, &mmCUR_REQUEST_FILTER_CNTL[0], sizeof(mmCUR_REQUEST_FILTER_CNTL)/sizeof(mmCUR_REQUEST_FILTER_CNTL[0]), 0, 0 },
+	{ "mmDCP0_CUR_STEREO_CONTROL", REG_MMIO, 0x1a9a, NULL, 0, 0, 0 },
+	{ "mmCUR_STEREO_CONTROL", REG_MMIO, 0x1a9a, &mmCUR_STEREO_CONTROL[0], sizeof(mmCUR_STEREO_CONTROL)/sizeof(mmCUR_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_CUR2_STEREO_CONTROL", REG_MMIO, 0x1a9b, NULL, 0, 0, 0 },
+	{ "mmCUR2_STEREO_CONTROL", REG_MMIO, 0x1a9b, &mmCUR2_STEREO_CONTROL[0], sizeof(mmCUR2_STEREO_CONTROL)/sizeof(mmCUR2_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1a9c, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1a9c, &mmOUT_CLAMP_CONTROL_G_Y[0], sizeof(mmOUT_CLAMP_CONTROL_G_Y)/sizeof(mmOUT_CLAMP_CONTROL_G_Y[0]), 0, 0 },
+	{ "mmDCP0_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1a9d, NULL, 0, 0, 0 },
+	{ "mmOUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1a9d, &mmOUT_CLAMP_CONTROL_B_CB[0], sizeof(mmOUT_CLAMP_CONTROL_B_CB)/sizeof(mmOUT_CLAMP_CONTROL_B_CB[0]), 0, 0 },
+	{ "mmDCP0_HW_ROTATION", REG_MMIO, 0x1a9e, NULL, 0, 0, 0 },
+	{ "mmHW_ROTATION", REG_MMIO, 0x1a9e, &mmHW_ROTATION[0], sizeof(mmHW_ROTATION)/sizeof(mmHW_ROTATION[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1a9f, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1a9f, &mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[0], sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL)/sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CONTROL", REG_MMIO, 0x1aa0, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CONTROL", REG_MMIO, 0x1aa0, &mmREGAMMA_CONTROL[0], sizeof(mmREGAMMA_CONTROL)/sizeof(mmREGAMMA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_INDEX", REG_MMIO, 0x1aa1, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_INDEX", REG_MMIO, 0x1aa1, &mmREGAMMA_LUT_INDEX[0], sizeof(mmREGAMMA_LUT_INDEX)/sizeof(mmREGAMMA_LUT_INDEX[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_DATA", REG_MMIO, 0x1aa2, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_DATA", REG_MMIO, 0x1aa2, &mmREGAMMA_LUT_DATA[0], sizeof(mmREGAMMA_LUT_DATA)/sizeof(mmREGAMMA_LUT_DATA[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1aa3, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1aa3, &mmREGAMMA_LUT_WRITE_EN_MASK[0], sizeof(mmREGAMMA_LUT_WRITE_EN_MASK)/sizeof(mmREGAMMA_LUT_WRITE_EN_MASK[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1aa4, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1aa4, &mmREGAMMA_CNTLA_START_CNTL[0], sizeof(mmREGAMMA_CNTLA_START_CNTL)/sizeof(mmREGAMMA_CNTLA_START_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1aa5, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1aa5, &mmREGAMMA_CNTLA_SLOPE_CNTL[0], sizeof(mmREGAMMA_CNTLA_SLOPE_CNTL)/sizeof(mmREGAMMA_CNTLA_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1aa6, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1aa6, &mmREGAMMA_CNTLA_END_CNTL1[0], sizeof(mmREGAMMA_CNTLA_END_CNTL1)/sizeof(mmREGAMMA_CNTLA_END_CNTL1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1aa7, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1aa7, &mmREGAMMA_CNTLA_END_CNTL2[0], sizeof(mmREGAMMA_CNTLA_END_CNTL2)/sizeof(mmREGAMMA_CNTLA_END_CNTL2[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1aa8, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1aa8, &mmREGAMMA_CNTLA_REGION_0_1[0], sizeof(mmREGAMMA_CNTLA_REGION_0_1)/sizeof(mmREGAMMA_CNTLA_REGION_0_1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1aa9, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1aa9, &mmREGAMMA_CNTLA_REGION_2_3[0], sizeof(mmREGAMMA_CNTLA_REGION_2_3)/sizeof(mmREGAMMA_CNTLA_REGION_2_3[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1aaa, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1aaa, &mmREGAMMA_CNTLA_REGION_4_5[0], sizeof(mmREGAMMA_CNTLA_REGION_4_5)/sizeof(mmREGAMMA_CNTLA_REGION_4_5[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1aab, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1aab, &mmREGAMMA_CNTLA_REGION_6_7[0], sizeof(mmREGAMMA_CNTLA_REGION_6_7)/sizeof(mmREGAMMA_CNTLA_REGION_6_7[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1aac, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1aac, &mmREGAMMA_CNTLA_REGION_8_9[0], sizeof(mmREGAMMA_CNTLA_REGION_8_9)/sizeof(mmREGAMMA_CNTLA_REGION_8_9[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1aad, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1aad, &mmREGAMMA_CNTLA_REGION_10_11[0], sizeof(mmREGAMMA_CNTLA_REGION_10_11)/sizeof(mmREGAMMA_CNTLA_REGION_10_11[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1aae, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1aae, &mmREGAMMA_CNTLA_REGION_12_13[0], sizeof(mmREGAMMA_CNTLA_REGION_12_13)/sizeof(mmREGAMMA_CNTLA_REGION_12_13[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1aaf, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1aaf, &mmREGAMMA_CNTLA_REGION_14_15[0], sizeof(mmREGAMMA_CNTLA_REGION_14_15)/sizeof(mmREGAMMA_CNTLA_REGION_14_15[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1ab0, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1ab0, &mmREGAMMA_CNTLB_START_CNTL[0], sizeof(mmREGAMMA_CNTLB_START_CNTL)/sizeof(mmREGAMMA_CNTLB_START_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1ab1, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1ab1, &mmREGAMMA_CNTLB_SLOPE_CNTL[0], sizeof(mmREGAMMA_CNTLB_SLOPE_CNTL)/sizeof(mmREGAMMA_CNTLB_SLOPE_CNTL[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1ab2, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1ab2, &mmREGAMMA_CNTLB_END_CNTL1[0], sizeof(mmREGAMMA_CNTLB_END_CNTL1)/sizeof(mmREGAMMA_CNTLB_END_CNTL1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1ab3, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1ab3, &mmREGAMMA_CNTLB_END_CNTL2[0], sizeof(mmREGAMMA_CNTLB_END_CNTL2)/sizeof(mmREGAMMA_CNTLB_END_CNTL2[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1ab4, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1ab4, &mmREGAMMA_CNTLB_REGION_0_1[0], sizeof(mmREGAMMA_CNTLB_REGION_0_1)/sizeof(mmREGAMMA_CNTLB_REGION_0_1[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1ab5, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1ab5, &mmREGAMMA_CNTLB_REGION_2_3[0], sizeof(mmREGAMMA_CNTLB_REGION_2_3)/sizeof(mmREGAMMA_CNTLB_REGION_2_3[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1ab6, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1ab6, &mmREGAMMA_CNTLB_REGION_4_5[0], sizeof(mmREGAMMA_CNTLB_REGION_4_5)/sizeof(mmREGAMMA_CNTLB_REGION_4_5[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1ab7, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1ab7, &mmREGAMMA_CNTLB_REGION_6_7[0], sizeof(mmREGAMMA_CNTLB_REGION_6_7)/sizeof(mmREGAMMA_CNTLB_REGION_6_7[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1ab8, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1ab8, &mmREGAMMA_CNTLB_REGION_8_9[0], sizeof(mmREGAMMA_CNTLB_REGION_8_9)/sizeof(mmREGAMMA_CNTLB_REGION_8_9[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1ab9, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1ab9, &mmREGAMMA_CNTLB_REGION_10_11[0], sizeof(mmREGAMMA_CNTLB_REGION_10_11)/sizeof(mmREGAMMA_CNTLB_REGION_10_11[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1aba, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1aba, &mmREGAMMA_CNTLB_REGION_12_13[0], sizeof(mmREGAMMA_CNTLB_REGION_12_13)/sizeof(mmREGAMMA_CNTLB_REGION_12_13[0]), 0, 0 },
+	{ "mmDCP0_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1abb, NULL, 0, 0, 0 },
+	{ "mmREGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1abb, &mmREGAMMA_CNTLB_REGION_14_15[0], sizeof(mmREGAMMA_CNTLB_REGION_14_15)/sizeof(mmREGAMMA_CNTLB_REGION_14_15[0]), 0, 0 },
+	{ "mmDCP0_ALPHA_CONTROL", REG_MMIO, 0x1abc, NULL, 0, 0, 0 },
+	{ "mmALPHA_CONTROL", REG_MMIO, 0x1abc, &mmALPHA_CONTROL[0], sizeof(mmALPHA_CONTROL)/sizeof(mmALPHA_CONTROL[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1abd, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1abd, &mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[0], sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS)/sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1abe, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1abe, &mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[0], sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH)/sizeof(mmGRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmDCP0_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1abf, NULL, 0, 0, 0 },
+	{ "mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1abf, &mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[0], sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS)/sizeof(mmGRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_DATA_FORMAT", REG_MMIO, 0x1ac0, NULL, 0, 0, 0 },
+	{ "mmLB_DATA_FORMAT", REG_MMIO, 0x1ac0, &mmLB_DATA_FORMAT[0], sizeof(mmLB_DATA_FORMAT)/sizeof(mmLB_DATA_FORMAT[0]), 0, 0 },
+	{ "mmLB0_LB_MEMORY_CTRL", REG_MMIO, 0x1ac1, NULL, 0, 0, 0 },
+	{ "mmLB_MEMORY_CTRL", REG_MMIO, 0x1ac1, &mmLB_MEMORY_CTRL[0], sizeof(mmLB_MEMORY_CTRL)/sizeof(mmLB_MEMORY_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ac2, NULL, 0, 0, 0 },
+	{ "mmLB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1ac2, &mmLB_MEMORY_SIZE_STATUS[0], sizeof(mmLB_MEMORY_SIZE_STATUS)/sizeof(mmLB_MEMORY_SIZE_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1ac3, NULL, 0, 0, 0 },
+	{ "mmLB_DESKTOP_HEIGHT", REG_MMIO, 0x1ac3, &mmLB_DESKTOP_HEIGHT[0], sizeof(mmLB_DESKTOP_HEIGHT)/sizeof(mmLB_DESKTOP_HEIGHT[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE_START_END", REG_MMIO, 0x1ac4, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE_START_END", REG_MMIO, 0x1ac4, &mmLB_VLINE_START_END[0], sizeof(mmLB_VLINE_START_END)/sizeof(mmLB_VLINE_START_END[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE2_START_END", REG_MMIO, 0x1ac5, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE2_START_END", REG_MMIO, 0x1ac5, &mmLB_VLINE2_START_END[0], sizeof(mmLB_VLINE2_START_END)/sizeof(mmLB_VLINE2_START_END[0]), 0, 0 },
+	{ "mmLB0_LB_V_COUNTER", REG_MMIO, 0x1ac6, NULL, 0, 0, 0 },
+	{ "mmLB_V_COUNTER", REG_MMIO, 0x1ac6, &mmLB_V_COUNTER[0], sizeof(mmLB_V_COUNTER)/sizeof(mmLB_V_COUNTER[0]), 0, 0 },
+	{ "mmLB0_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ac7, NULL, 0, 0, 0 },
+	{ "mmLB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1ac7, &mmLB_SNAPSHOT_V_COUNTER[0], sizeof(mmLB_SNAPSHOT_V_COUNTER)/sizeof(mmLB_SNAPSHOT_V_COUNTER[0]), 0, 0 },
+	{ "mmLB0_LB_INTERRUPT_MASK", REG_MMIO, 0x1ac8, NULL, 0, 0, 0 },
+	{ "mmLB_INTERRUPT_MASK", REG_MMIO, 0x1ac8, &mmLB_INTERRUPT_MASK[0], sizeof(mmLB_INTERRUPT_MASK)/sizeof(mmLB_INTERRUPT_MASK[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE_STATUS", REG_MMIO, 0x1ac9, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE_STATUS", REG_MMIO, 0x1ac9, &mmLB_VLINE_STATUS[0], sizeof(mmLB_VLINE_STATUS)/sizeof(mmLB_VLINE_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_VLINE2_STATUS", REG_MMIO, 0x1aca, NULL, 0, 0, 0 },
+	{ "mmLB_VLINE2_STATUS", REG_MMIO, 0x1aca, &mmLB_VLINE2_STATUS[0], sizeof(mmLB_VLINE2_STATUS)/sizeof(mmLB_VLINE2_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_VBLANK_STATUS", REG_MMIO, 0x1acb, NULL, 0, 0, 0 },
+	{ "mmLB_VBLANK_STATUS", REG_MMIO, 0x1acb, &mmLB_VBLANK_STATUS[0], sizeof(mmLB_VBLANK_STATUS)/sizeof(mmLB_VBLANK_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_SYNC_RESET_SEL", REG_MMIO, 0x1acc, NULL, 0, 0, 0 },
+	{ "mmLB_SYNC_RESET_SEL", REG_MMIO, 0x1acc, &mmLB_SYNC_RESET_SEL[0], sizeof(mmLB_SYNC_RESET_SEL)/sizeof(mmLB_SYNC_RESET_SEL[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1acd, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_R_CR", REG_MMIO, 0x1acd, &mmLB_BLACK_KEYER_R_CR[0], sizeof(mmLB_BLACK_KEYER_R_CR)/sizeof(mmLB_BLACK_KEYER_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ace, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_G_Y", REG_MMIO, 0x1ace, &mmLB_BLACK_KEYER_G_Y[0], sizeof(mmLB_BLACK_KEYER_G_Y)/sizeof(mmLB_BLACK_KEYER_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1acf, NULL, 0, 0, 0 },
+	{ "mmLB_BLACK_KEYER_B_CB", REG_MMIO, 0x1acf, &mmLB_BLACK_KEYER_B_CB[0], sizeof(mmLB_BLACK_KEYER_B_CB)/sizeof(mmLB_BLACK_KEYER_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ad0, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_CTRL", REG_MMIO, 0x1ad0, &mmLB_KEYER_COLOR_CTRL[0], sizeof(mmLB_KEYER_COLOR_CTRL)/sizeof(mmLB_KEYER_COLOR_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ad1, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_R_CR", REG_MMIO, 0x1ad1, &mmLB_KEYER_COLOR_R_CR[0], sizeof(mmLB_KEYER_COLOR_R_CR)/sizeof(mmLB_KEYER_COLOR_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ad2, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_G_Y", REG_MMIO, 0x1ad2, &mmLB_KEYER_COLOR_G_Y[0], sizeof(mmLB_KEYER_COLOR_G_Y)/sizeof(mmLB_KEYER_COLOR_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ad3, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_B_CB", REG_MMIO, 0x1ad3, &mmLB_KEYER_COLOR_B_CB[0], sizeof(mmLB_KEYER_COLOR_B_CB)/sizeof(mmLB_KEYER_COLOR_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ad4, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1ad4, &mmLB_KEYER_COLOR_REP_R_CR[0], sizeof(mmLB_KEYER_COLOR_REP_R_CR)/sizeof(mmLB_KEYER_COLOR_REP_R_CR[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ad5, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1ad5, &mmLB_KEYER_COLOR_REP_G_Y[0], sizeof(mmLB_KEYER_COLOR_REP_G_Y)/sizeof(mmLB_KEYER_COLOR_REP_G_Y[0]), 0, 0 },
+	{ "mmLB0_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ad6, NULL, 0, 0, 0 },
+	{ "mmLB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1ad6, &mmLB_KEYER_COLOR_REP_B_CB[0], sizeof(mmLB_KEYER_COLOR_REP_B_CB)/sizeof(mmLB_KEYER_COLOR_REP_B_CB[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ad7, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1ad7, &mmLB_BUFFER_LEVEL_STATUS[0], sizeof(mmLB_BUFFER_LEVEL_STATUS)/sizeof(mmLB_BUFFER_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ad8, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1ad8, &mmLB_BUFFER_URGENCY_CTRL[0], sizeof(mmLB_BUFFER_URGENCY_CTRL)/sizeof(mmLB_BUFFER_URGENCY_CTRL[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ad9, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1ad9, &mmLB_BUFFER_URGENCY_STATUS[0], sizeof(mmLB_BUFFER_URGENCY_STATUS)/sizeof(mmLB_BUFFER_URGENCY_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_BUFFER_STATUS", REG_MMIO, 0x1ada, NULL, 0, 0, 0 },
+	{ "mmLB_BUFFER_STATUS", REG_MMIO, 0x1ada, &mmLB_BUFFER_STATUS[0], sizeof(mmLB_BUFFER_STATUS)/sizeof(mmLB_BUFFER_STATUS[0]), 0, 0 },
+	{ "mmLB0_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1adc, NULL, 0, 0, 0 },
+	{ "mmLB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1adc, &mmLB_NO_OUTSTANDING_REQ_STATUS[0], sizeof(mmLB_NO_OUTSTANDING_REQ_STATUS)/sizeof(mmLB_NO_OUTSTANDING_REQ_STATUS[0]), 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1ae0, NULL, 0, 0, 0 },
+	{ "mmMVP_AFR_FLIP_MODE", REG_MMIO, 0x1ae0, &mmMVP_AFR_FLIP_MODE[0], sizeof(mmMVP_AFR_FLIP_MODE)/sizeof(mmMVP_AFR_FLIP_MODE[0]), 0, 0 },
+	{ "mmLB0_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ae1, NULL, 0, 0, 0 },
+	{ "mmMVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1ae1, &mmMVP_AFR_FLIP_FIFO_CNTL[0], sizeof(mmMVP_AFR_FLIP_FIFO_CNTL)/sizeof(mmMVP_AFR_FLIP_FIFO_CNTL[0]), 0, 0 },
+	{ "mmLB0_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ae2, NULL, 0, 0, 0 },
+	{ "mmMVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1ae2, &mmMVP_FLIP_LINE_NUM_INSERT[0], sizeof(mmMVP_FLIP_LINE_NUM_INSERT)/sizeof(mmMVP_FLIP_LINE_NUM_INSERT[0]), 0, 0 },
+	{ "mmLB0_DC_MVP_LB_CONTROL", REG_MMIO, 0x1ae3, NULL, 0, 0, 0 },
+	{ "mmDC_MVP_LB_CONTROL", REG_MMIO, 0x1ae3, &mmDC_MVP_LB_CONTROL[0], sizeof(mmDC_MVP_LB_CONTROL)/sizeof(mmDC_MVP_LB_CONTROL[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG", REG_MMIO, 0x1ae4, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG", REG_MMIO, 0x1ae4, &mmLB_DEBUG[0], sizeof(mmLB_DEBUG)/sizeof(mmLB_DEBUG[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG2", REG_MMIO, 0x1ae5, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG2", REG_MMIO, 0x1ae5, &mmLB_DEBUG2[0], sizeof(mmLB_DEBUG2)/sizeof(mmLB_DEBUG2[0]), 0, 0 },
+	{ "mmLB0_LB_DEBUG3", REG_MMIO, 0x1ae6, NULL, 0, 0, 0 },
+	{ "mmLB_DEBUG3", REG_MMIO, 0x1ae6, &mmLB_DEBUG3[0], sizeof(mmLB_DEBUG3)/sizeof(mmLB_DEBUG3[0]), 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1afe, NULL, 0, 0, 0 },
+	{ "mmLB_TEST_DEBUG_INDEX", REG_MMIO, 0x1afe, &mmLB_TEST_DEBUG_INDEX[0], sizeof(mmLB_TEST_DEBUG_INDEX)/sizeof(mmLB_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmLB0_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1aff, NULL, 0, 0, 0 },
+	{ "mmLB_TEST_DEBUG_DATA", REG_MMIO, 0x1aff, &mmLB_TEST_DEBUG_DATA[0], sizeof(mmLB_TEST_DEBUG_DATA)/sizeof(mmLB_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_L", REG_SMC, 0x1b, &ixDP_AUX1_DEBUG_L[0], sizeof(ixDP_AUX1_DEBUG_L)/sizeof(ixDP_AUX1_DEBUG_L[0]), 0, 0 },
+	{ "mmDC_PERFMON2_PERFCOUNTER_CNTL", REG_MMIO, 0x1b24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFCOUNTER_STATE", REG_MMIO, 0x1b25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1b26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CNTL", REG_MMIO, 0x1b27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_CVALUE_LOW", REG_MMIO, 0x1b28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_HI", REG_MMIO, 0x1b29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_LOW", REG_MMIO, 0x1b2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1b2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON2_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1b2c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1b30, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1b30, &mmDPG_PIPE_ARBITRATION_CONTROL1[0], sizeof(mmDPG_PIPE_ARBITRATION_CONTROL1)/sizeof(mmDPG_PIPE_ARBITRATION_CONTROL1[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1b31, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1b31, &mmDPG_PIPE_ARBITRATION_CONTROL2[0], sizeof(mmDPG_PIPE_ARBITRATION_CONTROL2)/sizeof(mmDPG_PIPE_ARBITRATION_CONTROL2[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1b32, NULL, 0, 0, 0 },
+	{ "mmDPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1b32, &mmDPG_WATERMARK_MASK_CONTROL[0], sizeof(mmDPG_WATERMARK_MASK_CONTROL)/sizeof(mmDPG_WATERMARK_MASK_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1b33, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1b33, &mmDPG_PIPE_URGENCY_CONTROL[0], sizeof(mmDPG_PIPE_URGENCY_CONTROL)/sizeof(mmDPG_PIPE_URGENCY_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1b34, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1b34, &mmDPG_PIPE_DPM_CONTROL[0], sizeof(mmDPG_PIPE_DPM_CONTROL)/sizeof(mmDPG_PIPE_DPM_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1b35, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1b35, &mmDPG_PIPE_STUTTER_CONTROL[0], sizeof(mmDPG_PIPE_STUTTER_CONTROL)/sizeof(mmDPG_PIPE_STUTTER_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1b36, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1b36, &mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[0], sizeof(mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL)/sizeof(mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1b37, NULL, 0, 0, 0 },
+	{ "mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1b37, &mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[0], sizeof(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH)/sizeof(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1b38, NULL, 0, 0, 0 },
+	{ "mmDPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1b38, &mmDPG_TEST_DEBUG_INDEX[0], sizeof(mmDPG_TEST_DEBUG_INDEX)/sizeof(mmDPG_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1b39, NULL, 0, 0, 0 },
+	{ "mmDPG_TEST_DEBUG_DATA", REG_MMIO, 0x1b39, &mmDPG_TEST_DEBUG_DATA[0], sizeof(mmDPG_TEST_DEBUG_DATA)/sizeof(mmDPG_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1b3a, NULL, 0, 0, 0 },
+	{ "mmDPG_REPEATER_PROGRAM", REG_MMIO, 0x1b3a, &mmDPG_REPEATER_PROGRAM[0], sizeof(mmDPG_REPEATER_PROGRAM)/sizeof(mmDPG_REPEATER_PROGRAM[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_A", REG_MMIO, 0x1b3b, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_A", REG_MMIO, 0x1b3b, &mmDPG_HW_DEBUG_A[0], sizeof(mmDPG_HW_DEBUG_A)/sizeof(mmDPG_HW_DEBUG_A[0]), 0, 0 },
+	{ "mmDMIF_PG0_DPG_HW_DEBUG_B", REG_MMIO, 0x1b3c, NULL, 0, 0, 0 },
+	{ "mmDPG_HW_DEBUG_B", REG_MMIO, 0x1b3c, &mmDPG_HW_DEBUG_B[0], sizeof(mmDPG_HW_DEBUG_B)/sizeof(mmDPG_HW_DEBUG_B[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1b40, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_SELECT", REG_MMIO, 0x1b40, &mmSCL_COEF_RAM_SELECT[0], sizeof(mmSCL_COEF_RAM_SELECT)/sizeof(mmSCL_COEF_RAM_SELECT[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1b41, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1b41, &mmSCL_COEF_RAM_TAP_DATA[0], sizeof(mmSCL_COEF_RAM_TAP_DATA)/sizeof(mmSCL_COEF_RAM_TAP_DATA[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE", REG_MMIO, 0x1b42, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE", REG_MMIO, 0x1b42, &mmSCL_MODE[0], sizeof(mmSCL_MODE)/sizeof(mmSCL_MODE[0]), 0, 0 },
+	{ "mmSCL0_SCL_TAP_CONTROL", REG_MMIO, 0x1b43, NULL, 0, 0, 0 },
+	{ "mmSCL_TAP_CONTROL", REG_MMIO, 0x1b43, &mmSCL_TAP_CONTROL[0], sizeof(mmSCL_TAP_CONTROL)/sizeof(mmSCL_TAP_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_CONTROL", REG_MMIO, 0x1b44, NULL, 0, 0, 0 },
+	{ "mmSCL_CONTROL", REG_MMIO, 0x1b44, &mmSCL_CONTROL[0], sizeof(mmSCL_CONTROL)/sizeof(mmSCL_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_BYPASS_CONTROL", REG_MMIO, 0x1b45, NULL, 0, 0, 0 },
+	{ "mmSCL_BYPASS_CONTROL", REG_MMIO, 0x1b45, &mmSCL_BYPASS_CONTROL[0], sizeof(mmSCL_BYPASS_CONTROL)/sizeof(mmSCL_BYPASS_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1b46, NULL, 0, 0, 0 },
+	{ "mmSCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1b46, &mmSCL_MANUAL_REPLICATE_CONTROL[0], sizeof(mmSCL_MANUAL_REPLICATE_CONTROL)/sizeof(mmSCL_MANUAL_REPLICATE_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1b47, NULL, 0, 0, 0 },
+	{ "mmSCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1b47, &mmSCL_AUTOMATIC_MODE_CONTROL[0], sizeof(mmSCL_AUTOMATIC_MODE_CONTROL)/sizeof(mmSCL_AUTOMATIC_MODE_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1b48, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1b48, &mmSCL_HORZ_FILTER_CONTROL[0], sizeof(mmSCL_HORZ_FILTER_CONTROL)/sizeof(mmSCL_HORZ_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1b49, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1b49, &mmSCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmSCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmSCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCL0_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1b4a, NULL, 0, 0, 0 },
+	{ "mmSCL_HORZ_FILTER_INIT", REG_MMIO, 0x1b4a, &mmSCL_HORZ_FILTER_INIT[0], sizeof(mmSCL_HORZ_FILTER_INIT)/sizeof(mmSCL_HORZ_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1b4b, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1b4b, &mmSCL_VERT_FILTER_CONTROL[0], sizeof(mmSCL_VERT_FILTER_CONTROL)/sizeof(mmSCL_VERT_FILTER_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1b4c, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1b4c, &mmSCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmSCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmSCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1b4d, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_INIT", REG_MMIO, 0x1b4d, &mmSCL_VERT_FILTER_INIT[0], sizeof(mmSCL_VERT_FILTER_INIT)/sizeof(mmSCL_VERT_FILTER_INIT[0]), 0, 0 },
+	{ "mmSCL0_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1b4e, NULL, 0, 0, 0 },
+	{ "mmSCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1b4e, &mmSCL_VERT_FILTER_INIT_BOT[0], sizeof(mmSCL_VERT_FILTER_INIT_BOT)/sizeof(mmSCL_VERT_FILTER_INIT_BOT[0]), 0, 0 },
+	{ "mmSCL0_SCL_ROUND_OFFSET", REG_MMIO, 0x1b4f, NULL, 0, 0, 0 },
+	{ "mmSCL_ROUND_OFFSET", REG_MMIO, 0x1b4f, &mmSCL_ROUND_OFFSET[0], sizeof(mmSCL_ROUND_OFFSET)/sizeof(mmSCL_ROUND_OFFSET[0]), 0, 0 },
+	{ "mmSCL0_SCL_UPDATE", REG_MMIO, 0x1b51, NULL, 0, 0, 0 },
+	{ "mmSCL_UPDATE", REG_MMIO, 0x1b51, &mmSCL_UPDATE[0], sizeof(mmSCL_UPDATE)/sizeof(mmSCL_UPDATE[0]), 0, 0 },
+	{ "mmSCL0_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1b53, NULL, 0, 0, 0 },
+	{ "mmSCL_F_SHARP_CONTROL", REG_MMIO, 0x1b53, &mmSCL_F_SHARP_CONTROL[0], sizeof(mmSCL_F_SHARP_CONTROL)/sizeof(mmSCL_F_SHARP_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_ALU_CONTROL", REG_MMIO, 0x1b54, NULL, 0, 0, 0 },
+	{ "mmSCL_ALU_CONTROL", REG_MMIO, 0x1b54, &mmSCL_ALU_CONTROL[0], sizeof(mmSCL_ALU_CONTROL)/sizeof(mmSCL_ALU_CONTROL[0]), 0, 0 },
+	{ "mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1b55, NULL, 0, 0, 0 },
+	{ "mmSCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1b55, &mmSCL_COEF_RAM_CONFLICT_STATUS[0], sizeof(mmSCL_COEF_RAM_CONFLICT_STATUS)/sizeof(mmSCL_COEF_RAM_CONFLICT_STATUS[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_START", REG_MMIO, 0x1b5c, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_START", REG_MMIO, 0x1b5c, &mmVIEWPORT_START[0], sizeof(mmVIEWPORT_START)/sizeof(mmVIEWPORT_START[0]), 0, 0 },
+	{ "mmSCL0_VIEWPORT_SIZE", REG_MMIO, 0x1b5d, NULL, 0, 0, 0 },
+	{ "mmVIEWPORT_SIZE", REG_MMIO, 0x1b5d, &mmVIEWPORT_SIZE[0], sizeof(mmVIEWPORT_SIZE)/sizeof(mmVIEWPORT_SIZE[0]), 0, 0 },
+	{ "mmSCL0_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1b5e, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1b5e, &mmEXT_OVERSCAN_LEFT_RIGHT[0], sizeof(mmEXT_OVERSCAN_LEFT_RIGHT)/sizeof(mmEXT_OVERSCAN_LEFT_RIGHT[0]), 0, 0 },
+	{ "mmSCL0_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1b5f, NULL, 0, 0, 0 },
+	{ "mmEXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1b5f, &mmEXT_OVERSCAN_TOP_BOTTOM[0], sizeof(mmEXT_OVERSCAN_TOP_BOTTOM)/sizeof(mmEXT_OVERSCAN_TOP_BOTTOM[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1b60, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET1", REG_MMIO, 0x1b60, &mmSCL_MODE_CHANGE_DET1[0], sizeof(mmSCL_MODE_CHANGE_DET1)/sizeof(mmSCL_MODE_CHANGE_DET1[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1b61, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET2", REG_MMIO, 0x1b61, &mmSCL_MODE_CHANGE_DET2[0], sizeof(mmSCL_MODE_CHANGE_DET2)/sizeof(mmSCL_MODE_CHANGE_DET2[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1b62, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_DET3", REG_MMIO, 0x1b62, &mmSCL_MODE_CHANGE_DET3[0], sizeof(mmSCL_MODE_CHANGE_DET3)/sizeof(mmSCL_MODE_CHANGE_DET3[0]), 0, 0 },
+	{ "mmSCL0_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1b63, NULL, 0, 0, 0 },
+	{ "mmSCL_MODE_CHANGE_MASK", REG_MMIO, 0x1b63, &mmSCL_MODE_CHANGE_MASK[0], sizeof(mmSCL_MODE_CHANGE_MASK)/sizeof(mmSCL_MODE_CHANGE_MASK[0]), 0, 0 },
+	{ "mmSCL0_SCL_DEBUG2", REG_MMIO, 0x1b69, NULL, 0, 0, 0 },
+	{ "mmSCL_DEBUG2", REG_MMIO, 0x1b69, &mmSCL_DEBUG2[0], sizeof(mmSCL_DEBUG2)/sizeof(mmSCL_DEBUG2[0]), 0, 0 },
+	{ "mmSCL0_SCL_DEBUG", REG_MMIO, 0x1b6a, NULL, 0, 0, 0 },
+	{ "mmSCL_DEBUG", REG_MMIO, 0x1b6a, &mmSCL_DEBUG[0], sizeof(mmSCL_DEBUG)/sizeof(mmSCL_DEBUG[0]), 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1b6b, NULL, 0, 0, 0 },
+	{ "mmSCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1b6b, &mmSCL_TEST_DEBUG_INDEX[0], sizeof(mmSCL_TEST_DEBUG_INDEX)/sizeof(mmSCL_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmSCL0_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1b6c, NULL, 0, 0, 0 },
+	{ "mmSCL_TEST_DEBUG_DATA", REG_MMIO, 0x1b6c, &mmSCL_TEST_DEBUG_DATA[0], sizeof(mmSCL_TEST_DEBUG_DATA)/sizeof(mmSCL_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLND0_BLND_CONTROL", REG_MMIO, 0x1b6d, NULL, 0, 0, 0 },
+	{ "mmBLND_CONTROL", REG_MMIO, 0x1b6d, &mmBLND_CONTROL[0], sizeof(mmBLND_CONTROL)/sizeof(mmBLND_CONTROL[0]), 0, 0 },
+	{ "mmBLND0_SM_CONTROL2", REG_MMIO, 0x1b6e, NULL, 0, 0, 0 },
+	{ "mmSM_CONTROL2", REG_MMIO, 0x1b6e, &mmSM_CONTROL2[0], sizeof(mmSM_CONTROL2)/sizeof(mmSM_CONTROL2[0]), 0, 0 },
+	{ "mmBLND0_PTI_CONTROL", REG_MMIO, 0x1b6f, NULL, 0, 0, 0 },
+	{ "mmPTI_CONTROL", REG_MMIO, 0x1b6f, &mmPTI_CONTROL[0], sizeof(mmPTI_CONTROL)/sizeof(mmPTI_CONTROL[0]), 0, 0 },
+	{ "mmBLND0_BLND_UPDATE", REG_MMIO, 0x1b70, NULL, 0, 0, 0 },
+	{ "mmBLND_UPDATE", REG_MMIO, 0x1b70, &mmBLND_UPDATE[0], sizeof(mmBLND_UPDATE)/sizeof(mmBLND_UPDATE[0]), 0, 0 },
+	{ "mmBLND0_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1b71, NULL, 0, 0, 0 },
+	{ "mmBLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1b71, &mmBLND_UNDERFLOW_INTERRUPT[0], sizeof(mmBLND_UNDERFLOW_INTERRUPT)/sizeof(mmBLND_UNDERFLOW_INTERRUPT[0]), 0, 0 },
+	{ "mmBLND0_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1b73, NULL, 0, 0, 0 },
+	{ "mmBLND_V_UPDATE_LOCK", REG_MMIO, 0x1b73, &mmBLND_V_UPDATE_LOCK[0], sizeof(mmBLND_V_UPDATE_LOCK)/sizeof(mmBLND_V_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmBLND0_BLND_DEBUG", REG_MMIO, 0x1b74, NULL, 0, 0, 0 },
+	{ "mmBLND_DEBUG", REG_MMIO, 0x1b74, &mmBLND_DEBUG[0], sizeof(mmBLND_DEBUG)/sizeof(mmBLND_DEBUG[0]), 0, 0 },
+	{ "mmBLND0_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1b75, NULL, 0, 0, 0 },
+	{ "mmBLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1b75, &mmBLND_TEST_DEBUG_INDEX[0], sizeof(mmBLND_TEST_DEBUG_INDEX)/sizeof(mmBLND_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmBLND0_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1b76, NULL, 0, 0, 0 },
+	{ "mmBLND_TEST_DEBUG_DATA", REG_MMIO, 0x1b76, &mmBLND_TEST_DEBUG_DATA[0], sizeof(mmBLND_TEST_DEBUG_DATA)/sizeof(mmBLND_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmBLND0_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1b77, NULL, 0, 0, 0 },
+	{ "mmBLND_REG_UPDATE_STATUS", REG_MMIO, 0x1b77, &mmBLND_REG_UPDATE_STATUS[0], sizeof(mmBLND_REG_UPDATE_STATUS)/sizeof(mmBLND_REG_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b78, NULL, 0, 0, 0 },
+	{ "mmCRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1b78, &mmCRTC_3D_STRUCTURE_CONTROL[0], sizeof(mmCRTC_3D_STRUCTURE_CONTROL)/sizeof(mmCRTC_3D_STRUCTURE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1b79, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1b79, &mmCRTC_GSL_VSYNC_GAP[0], sizeof(mmCRTC_GSL_VSYNC_GAP)/sizeof(mmCRTC_GSL_VSYNC_GAP[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_WINDOW", REG_MMIO, 0x1b7a, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_WINDOW", REG_MMIO, 0x1b7a, &mmCRTC_GSL_WINDOW[0], sizeof(mmCRTC_GSL_WINDOW)/sizeof(mmCRTC_GSL_WINDOW[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_GSL_CONTROL", REG_MMIO, 0x1b7b, NULL, 0, 0, 0 },
+	{ "mmCRTC_GSL_CONTROL", REG_MMIO, 0x1b7b, &mmCRTC_GSL_CONTROL[0], sizeof(mmCRTC_GSL_CONTROL)/sizeof(mmCRTC_GSL_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1b7c, NULL, 0, 0, 0 },
+	{ "mmCRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1b7c, &mmCRTC_DCFE_CLOCK_CONTROL[0], sizeof(mmCRTC_DCFE_CLOCK_CONTROL)/sizeof(mmCRTC_DCFE_CLOCK_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1b7d, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1b7d, &mmCRTC_H_BLANK_EARLY_NUM[0], sizeof(mmCRTC_H_BLANK_EARLY_NUM)/sizeof(mmCRTC_H_BLANK_EARLY_NUM[0]), 0, 0 },
+	{ "mmCRTC0_DCFE_DBG_SEL", REG_MMIO, 0x1b7e, NULL, 0, 0, 0 },
+	{ "mmDCFE_DBG_SEL", REG_MMIO, 0x1b7e, &mmDCFE_DBG_SEL[0], sizeof(mmDCFE_DBG_SEL)/sizeof(mmDCFE_DBG_SEL[0]), 0, 0 },
+	{ "mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x1b7f, NULL, 0, 0, 0 },
+	{ "mmDCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x1b7f, &mmDCFE_MEM_LIGHT_SLEEP_CNTL[0], sizeof(mmDCFE_MEM_LIGHT_SLEEP_CNTL)/sizeof(mmDCFE_MEM_LIGHT_SLEEP_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_TOTAL", REG_MMIO, 0x1b80, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_TOTAL", REG_MMIO, 0x1b80, &mmCRTC_H_TOTAL[0], sizeof(mmCRTC_H_TOTAL)/sizeof(mmCRTC_H_TOTAL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_BLANK_START_END", REG_MMIO, 0x1b81, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_BLANK_START_END", REG_MMIO, 0x1b81, &mmCRTC_H_BLANK_START_END[0], sizeof(mmCRTC_H_BLANK_START_END)/sizeof(mmCRTC_H_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A", REG_MMIO, 0x1b82, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_A", REG_MMIO, 0x1b82, &mmCRTC_H_SYNC_A[0], sizeof(mmCRTC_H_SYNC_A)/sizeof(mmCRTC_H_SYNC_A[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1b83, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1b83, &mmCRTC_H_SYNC_A_CNTL[0], sizeof(mmCRTC_H_SYNC_A_CNTL)/sizeof(mmCRTC_H_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B", REG_MMIO, 0x1b84, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_B", REG_MMIO, 0x1b84, &mmCRTC_H_SYNC_B[0], sizeof(mmCRTC_H_SYNC_B)/sizeof(mmCRTC_H_SYNC_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1b85, NULL, 0, 0, 0 },
+	{ "mmCRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1b85, &mmCRTC_H_SYNC_B_CNTL[0], sizeof(mmCRTC_H_SYNC_B_CNTL)/sizeof(mmCRTC_H_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VBI_END", REG_MMIO, 0x1b86, NULL, 0, 0, 0 },
+	{ "mmCRTC_VBI_END", REG_MMIO, 0x1b86, &mmCRTC_VBI_END[0], sizeof(mmCRTC_VBI_END)/sizeof(mmCRTC_VBI_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL", REG_MMIO, 0x1b87, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL", REG_MMIO, 0x1b87, &mmCRTC_V_TOTAL[0], sizeof(mmCRTC_V_TOTAL)/sizeof(mmCRTC_V_TOTAL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1b88, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_MIN", REG_MMIO, 0x1b88, &mmCRTC_V_TOTAL_MIN[0], sizeof(mmCRTC_V_TOTAL_MIN)/sizeof(mmCRTC_V_TOTAL_MIN[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1b89, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_MAX", REG_MMIO, 0x1b89, &mmCRTC_V_TOTAL_MAX[0], sizeof(mmCRTC_V_TOTAL_MAX)/sizeof(mmCRTC_V_TOTAL_MAX[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1b8a, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1b8a, &mmCRTC_V_TOTAL_CONTROL[0], sizeof(mmCRTC_V_TOTAL_CONTROL)/sizeof(mmCRTC_V_TOTAL_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b8b, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1b8b, &mmCRTC_V_TOTAL_INT_STATUS[0], sizeof(mmCRTC_V_TOTAL_INT_STATUS)/sizeof(mmCRTC_V_TOTAL_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b8c, NULL, 0, 0, 0 },
+	{ "mmCRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1b8c, &mmCRTC_VSYNC_NOM_INT_STATUS[0], sizeof(mmCRTC_VSYNC_NOM_INT_STATUS)/sizeof(mmCRTC_VSYNC_NOM_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_BLANK_START_END", REG_MMIO, 0x1b8d, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_BLANK_START_END", REG_MMIO, 0x1b8d, &mmCRTC_V_BLANK_START_END[0], sizeof(mmCRTC_V_BLANK_START_END)/sizeof(mmCRTC_V_BLANK_START_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A", REG_MMIO, 0x1b8e, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_A", REG_MMIO, 0x1b8e, &mmCRTC_V_SYNC_A[0], sizeof(mmCRTC_V_SYNC_A)/sizeof(mmCRTC_V_SYNC_A[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1b8f, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1b8f, &mmCRTC_V_SYNC_A_CNTL[0], sizeof(mmCRTC_V_SYNC_A_CNTL)/sizeof(mmCRTC_V_SYNC_A_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B", REG_MMIO, 0x1b90, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_B", REG_MMIO, 0x1b90, &mmCRTC_V_SYNC_B[0], sizeof(mmCRTC_V_SYNC_B)/sizeof(mmCRTC_V_SYNC_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1b91, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1b91, &mmCRTC_V_SYNC_B_CNTL[0], sizeof(mmCRTC_V_SYNC_B_CNTL)/sizeof(mmCRTC_V_SYNC_B_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1b92, NULL, 0, 0, 0 },
+	{ "mmCRTC_DTMTEST_CNTL", REG_MMIO, 0x1b92, &mmCRTC_DTMTEST_CNTL[0], sizeof(mmCRTC_DTMTEST_CNTL)/sizeof(mmCRTC_DTMTEST_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1b93, NULL, 0, 0, 0 },
+	{ "mmCRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1b93, &mmCRTC_DTMTEST_STATUS_POSITION[0], sizeof(mmCRTC_DTMTEST_STATUS_POSITION)/sizeof(mmCRTC_DTMTEST_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_CNTL", REG_MMIO, 0x1b94, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGA_CNTL", REG_MMIO, 0x1b94, &mmCRTC_TRIGA_CNTL[0], sizeof(mmCRTC_TRIGA_CNTL)/sizeof(mmCRTC_TRIGA_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b95, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1b95, &mmCRTC_TRIGA_MANUAL_TRIG[0], sizeof(mmCRTC_TRIGA_MANUAL_TRIG)/sizeof(mmCRTC_TRIGA_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_CNTL", REG_MMIO, 0x1b96, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGB_CNTL", REG_MMIO, 0x1b96, &mmCRTC_TRIGB_CNTL[0], sizeof(mmCRTC_TRIGB_CNTL)/sizeof(mmCRTC_TRIGB_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b97, NULL, 0, 0, 0 },
+	{ "mmCRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1b97, &mmCRTC_TRIGB_MANUAL_TRIG[0], sizeof(mmCRTC_TRIGB_MANUAL_TRIG)/sizeof(mmCRTC_TRIGB_MANUAL_TRIG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b98, NULL, 0, 0, 0 },
+	{ "mmCRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1b98, &mmCRTC_FORCE_COUNT_NOW_CNTL[0], sizeof(mmCRTC_FORCE_COUNT_NOW_CNTL)/sizeof(mmCRTC_FORCE_COUNT_NOW_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FLOW_CONTROL", REG_MMIO, 0x1b99, NULL, 0, 0, 0 },
+	{ "mmCRTC_FLOW_CONTROL", REG_MMIO, 0x1b99, &mmCRTC_FLOW_CONTROL[0], sizeof(mmCRTC_FLOW_CONTROL)/sizeof(mmCRTC_FLOW_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b9b, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1b9b, &mmCRTC_STEREO_FORCE_NEXT_EYE[0], sizeof(mmCRTC_STEREO_FORCE_NEXT_EYE)/sizeof(mmCRTC_STEREO_FORCE_NEXT_EYE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CONTROL", REG_MMIO, 0x1b9c, NULL, 0, 0, 0 },
+	{ "mmCRTC_CONTROL", REG_MMIO, 0x1b9c, &mmCRTC_CONTROL[0], sizeof(mmCRTC_CONTROL)/sizeof(mmCRTC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_CONTROL", REG_MMIO, 0x1b9d, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_CONTROL", REG_MMIO, 0x1b9d, &mmCRTC_BLANK_CONTROL[0], sizeof(mmCRTC_BLANK_CONTROL)/sizeof(mmCRTC_BLANK_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1b9e, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERLACE_CONTROL", REG_MMIO, 0x1b9e, &mmCRTC_INTERLACE_CONTROL[0], sizeof(mmCRTC_INTERLACE_CONTROL)/sizeof(mmCRTC_INTERLACE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1b9f, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERLACE_STATUS", REG_MMIO, 0x1b9f, &mmCRTC_INTERLACE_STATUS[0], sizeof(mmCRTC_INTERLACE_STATUS)/sizeof(mmCRTC_INTERLACE_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ba0, NULL, 0, 0, 0 },
+	{ "mmCRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ba0, &mmCRTC_FIELD_INDICATION_CONTROL[0], sizeof(mmCRTC_FIELD_INDICATION_CONTROL)/sizeof(mmCRTC_FIELD_INDICATION_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ba1, NULL, 0, 0, 0 },
+	{ "mmCRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ba1, &mmCRTC_PIXEL_DATA_READBACK0[0], sizeof(mmCRTC_PIXEL_DATA_READBACK0)/sizeof(mmCRTC_PIXEL_DATA_READBACK0[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ba2, NULL, 0, 0, 0 },
+	{ "mmCRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ba2, &mmCRTC_PIXEL_DATA_READBACK1[0], sizeof(mmCRTC_PIXEL_DATA_READBACK1)/sizeof(mmCRTC_PIXEL_DATA_READBACK1[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS", REG_MMIO, 0x1ba3, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS", REG_MMIO, 0x1ba3, &mmCRTC_STATUS[0], sizeof(mmCRTC_STATUS)/sizeof(mmCRTC_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_POSITION", REG_MMIO, 0x1ba4, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_POSITION", REG_MMIO, 0x1ba4, &mmCRTC_STATUS_POSITION[0], sizeof(mmCRTC_STATUS_POSITION)/sizeof(mmCRTC_STATUS_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ba5, NULL, 0, 0, 0 },
+	{ "mmCRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ba5, &mmCRTC_NOM_VERT_POSITION[0], sizeof(mmCRTC_NOM_VERT_POSITION)/sizeof(mmCRTC_NOM_VERT_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ba6, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ba6, &mmCRTC_STATUS_FRAME_COUNT[0], sizeof(mmCRTC_STATUS_FRAME_COUNT)/sizeof(mmCRTC_STATUS_FRAME_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ba7, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ba7, &mmCRTC_STATUS_VF_COUNT[0], sizeof(mmCRTC_STATUS_VF_COUNT)/sizeof(mmCRTC_STATUS_VF_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ba8, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ba8, &mmCRTC_STATUS_HV_COUNT[0], sizeof(mmCRTC_STATUS_HV_COUNT)/sizeof(mmCRTC_STATUS_HV_COUNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_CONTROL", REG_MMIO, 0x1ba9, NULL, 0, 0, 0 },
+	{ "mmCRTC_COUNT_CONTROL", REG_MMIO, 0x1ba9, &mmCRTC_COUNT_CONTROL[0], sizeof(mmCRTC_COUNT_CONTROL)/sizeof(mmCRTC_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_COUNT_RESET", REG_MMIO, 0x1baa, NULL, 0, 0, 0 },
+	{ "mmCRTC_COUNT_RESET", REG_MMIO, 0x1baa, &mmCRTC_COUNT_RESET[0], sizeof(mmCRTC_COUNT_RESET)/sizeof(mmCRTC_COUNT_RESET[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bab, NULL, 0, 0, 0 },
+	{ "mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1bab, &mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[0], sizeof(mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE)/sizeof(mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1bac, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1bac, &mmCRTC_VERT_SYNC_CONTROL[0], sizeof(mmCRTC_VERT_SYNC_CONTROL)/sizeof(mmCRTC_VERT_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_STATUS", REG_MMIO, 0x1bad, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_STATUS", REG_MMIO, 0x1bad, &mmCRTC_STEREO_STATUS[0], sizeof(mmCRTC_STEREO_STATUS)/sizeof(mmCRTC_STEREO_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STEREO_CONTROL", REG_MMIO, 0x1bae, NULL, 0, 0, 0 },
+	{ "mmCRTC_STEREO_CONTROL", REG_MMIO, 0x1bae, &mmCRTC_STEREO_CONTROL[0], sizeof(mmCRTC_STEREO_CONTROL)/sizeof(mmCRTC_STEREO_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1baf, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1baf, &mmCRTC_SNAPSHOT_STATUS[0], sizeof(mmCRTC_SNAPSHOT_STATUS)/sizeof(mmCRTC_SNAPSHOT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1bb0, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1bb0, &mmCRTC_SNAPSHOT_CONTROL[0], sizeof(mmCRTC_SNAPSHOT_CONTROL)/sizeof(mmCRTC_SNAPSHOT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1bb1, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1bb1, &mmCRTC_SNAPSHOT_POSITION[0], sizeof(mmCRTC_SNAPSHOT_POSITION)/sizeof(mmCRTC_SNAPSHOT_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1bb2, NULL, 0, 0, 0 },
+	{ "mmCRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1bb2, &mmCRTC_SNAPSHOT_FRAME[0], sizeof(mmCRTC_SNAPSHOT_FRAME)/sizeof(mmCRTC_SNAPSHOT_FRAME[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1bb3, NULL, 0, 0, 0 },
+	{ "mmCRTC_START_LINE_CONTROL", REG_MMIO, 0x1bb3, &mmCRTC_START_LINE_CONTROL[0], sizeof(mmCRTC_START_LINE_CONTROL)/sizeof(mmCRTC_START_LINE_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1bb4, NULL, 0, 0, 0 },
+	{ "mmCRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1bb4, &mmCRTC_INTERRUPT_CONTROL[0], sizeof(mmCRTC_INTERRUPT_CONTROL)/sizeof(mmCRTC_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_UPDATE_LOCK", REG_MMIO, 0x1bb5, NULL, 0, 0, 0 },
+	{ "mmCRTC_UPDATE_LOCK", REG_MMIO, 0x1bb5, &mmCRTC_UPDATE_LOCK[0], sizeof(mmCRTC_UPDATE_LOCK)/sizeof(mmCRTC_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bb6, NULL, 0, 0, 0 },
+	{ "mmCRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1bb6, &mmCRTC_DOUBLE_BUFFER_CONTROL[0], sizeof(mmCRTC_DOUBLE_BUFFER_CONTROL)/sizeof(mmCRTC_DOUBLE_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1bb7, NULL, 0, 0, 0 },
+	{ "mmCRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1bb7, &mmCRTC_VGA_PARAMETER_CAPTURE_MODE[0], sizeof(mmCRTC_VGA_PARAMETER_CAPTURE_MODE)/sizeof(mmCRTC_VGA_PARAMETER_CAPTURE_MODE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bba, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1bba, &mmCRTC_TEST_PATTERN_CONTROL[0], sizeof(mmCRTC_TEST_PATTERN_CONTROL)/sizeof(mmCRTC_TEST_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bbb, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1bbb, &mmCRTC_TEST_PATTERN_PARAMETERS[0], sizeof(mmCRTC_TEST_PATTERN_PARAMETERS)/sizeof(mmCRTC_TEST_PATTERN_PARAMETERS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1bbc, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1bbc, &mmCRTC_TEST_PATTERN_COLOR[0], sizeof(mmCRTC_TEST_PATTERN_COLOR)/sizeof(mmCRTC_TEST_PATTERN_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_MASTER_UPDATE_LOCK", REG_MMIO, 0x1bbd, NULL, 0, 0, 0 },
+	{ "mmMASTER_UPDATE_LOCK", REG_MMIO, 0x1bbd, &mmMASTER_UPDATE_LOCK[0], sizeof(mmMASTER_UPDATE_LOCK)/sizeof(mmMASTER_UPDATE_LOCK[0]), 0, 0 },
+	{ "mmCRTC0_MASTER_UPDATE_MODE", REG_MMIO, 0x1bbe, NULL, 0, 0, 0 },
+	{ "mmMASTER_UPDATE_MODE", REG_MMIO, 0x1bbe, &mmMASTER_UPDATE_MODE[0], sizeof(mmMASTER_UPDATE_MODE)/sizeof(mmMASTER_UPDATE_MODE[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1bbf, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1bbf, &mmCRTC_MVP_INBAND_CNTL_INSERT[0], sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT)/sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1bc0, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1bc0, &mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[0], sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER)/sizeof(mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MVP_STATUS", REG_MMIO, 0x1bc1, NULL, 0, 0, 0 },
+	{ "mmCRTC_MVP_STATUS", REG_MMIO, 0x1bc1, &mmCRTC_MVP_STATUS[0], sizeof(mmCRTC_MVP_STATUS)/sizeof(mmCRTC_MVP_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_MASTER_EN", REG_MMIO, 0x1bc2, NULL, 0, 0, 0 },
+	{ "mmCRTC_MASTER_EN", REG_MMIO, 0x1bc2, &mmCRTC_MASTER_EN[0], sizeof(mmCRTC_MASTER_EN)/sizeof(mmCRTC_MASTER_EN[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1bc3, NULL, 0, 0, 0 },
+	{ "mmCRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1bc3, &mmCRTC_ALLOW_STOP_OFF_V_CNT[0], sizeof(mmCRTC_ALLOW_STOP_OFF_V_CNT)/sizeof(mmCRTC_ALLOW_STOP_OFF_V_CNT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1bc4, NULL, 0, 0, 0 },
+	{ "mmCRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1bc4, &mmCRTC_V_UPDATE_INT_STATUS[0], sizeof(mmCRTC_V_UPDATE_INT_STATUS)/sizeof(mmCRTC_V_UPDATE_INT_STATUS[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1bc6, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1bc6, &mmCRTC_TEST_DEBUG_INDEX[0], sizeof(mmCRTC_TEST_DEBUG_INDEX)/sizeof(mmCRTC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1bc7, NULL, 0, 0, 0 },
+	{ "mmCRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1bc7, &mmCRTC_TEST_DEBUG_DATA[0], sizeof(mmCRTC_TEST_DEBUG_DATA)/sizeof(mmCRTC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1bc8, NULL, 0, 0, 0 },
+	{ "mmCRTC_OVERSCAN_COLOR", REG_MMIO, 0x1bc8, &mmCRTC_OVERSCAN_COLOR[0], sizeof(mmCRTC_OVERSCAN_COLOR)/sizeof(mmCRTC_OVERSCAN_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1bc9, NULL, 0, 0, 0 },
+	{ "mmCRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1bc9, &mmCRTC_OVERSCAN_COLOR_EXT[0], sizeof(mmCRTC_OVERSCAN_COLOR_EXT)/sizeof(mmCRTC_OVERSCAN_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1bca, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1bca, &mmCRTC_BLANK_DATA_COLOR[0], sizeof(mmCRTC_BLANK_DATA_COLOR)/sizeof(mmCRTC_BLANK_DATA_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1bcb, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1bcb, &mmCRTC_BLANK_DATA_COLOR_EXT[0], sizeof(mmCRTC_BLANK_DATA_COLOR_EXT)/sizeof(mmCRTC_BLANK_DATA_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR", REG_MMIO, 0x1bcc, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLACK_COLOR", REG_MMIO, 0x1bcc, &mmCRTC_BLACK_COLOR[0], sizeof(mmCRTC_BLACK_COLOR)/sizeof(mmCRTC_BLACK_COLOR[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1bcd, NULL, 0, 0, 0 },
+	{ "mmCRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1bcd, &mmCRTC_BLACK_COLOR_EXT[0], sizeof(mmCRTC_BLACK_COLOR_EXT)/sizeof(mmCRTC_BLACK_COLOR_EXT[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1bce, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1bce, &mmCRTC_VERTICAL_INTERRUPT0_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT0_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT0_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1bcf, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1bcf, &mmCRTC_VERTICAL_INTERRUPT0_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT0_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT0_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1bd0, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1bd0, &mmCRTC_VERTICAL_INTERRUPT1_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT1_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT1_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1bd1, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1bd1, &mmCRTC_VERTICAL_INTERRUPT1_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT1_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT1_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1bd2, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1bd2, &mmCRTC_VERTICAL_INTERRUPT2_POSITION[0], sizeof(mmCRTC_VERTICAL_INTERRUPT2_POSITION)/sizeof(mmCRTC_VERTICAL_INTERRUPT2_POSITION[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bd3, NULL, 0, 0, 0 },
+	{ "mmCRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1bd3, &mmCRTC_VERTICAL_INTERRUPT2_CONTROL[0], sizeof(mmCRTC_VERTICAL_INTERRUPT2_CONTROL)/sizeof(mmCRTC_VERTICAL_INTERRUPT2_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC_CNTL", REG_MMIO, 0x1bd4, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC_CNTL", REG_MMIO, 0x1bd4, &mmCRTC_CRC_CNTL[0], sizeof(mmCRTC_CRC_CNTL)/sizeof(mmCRTC_CRC_CNTL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bd5, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1bd5, &mmCRTC_CRC0_WINDOWA_X_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWA_X_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bd6, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bd6, &mmCRTC_CRC0_WINDOWA_Y_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWA_Y_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bd7, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1bd7, &mmCRTC_CRC0_WINDOWB_X_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWB_X_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bd8, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bd8, &mmCRTC_CRC0_WINDOWB_Y_CONTROL[0], sizeof(mmCRTC_CRC0_WINDOWB_Y_CONTROL)/sizeof(mmCRTC_CRC0_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1bd9, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_DATA_RG", REG_MMIO, 0x1bd9, &mmCRTC_CRC0_DATA_RG[0], sizeof(mmCRTC_CRC0_DATA_RG)/sizeof(mmCRTC_CRC0_DATA_RG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC0_DATA_B", REG_MMIO, 0x1bda, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC0_DATA_B", REG_MMIO, 0x1bda, &mmCRTC_CRC0_DATA_B[0], sizeof(mmCRTC_CRC0_DATA_B)/sizeof(mmCRTC_CRC0_DATA_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bdb, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1bdb, &mmCRTC_CRC1_WINDOWA_X_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWA_X_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWA_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bdc, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1bdc, &mmCRTC_CRC1_WINDOWA_Y_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWA_Y_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWA_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bdd, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1bdd, &mmCRTC_CRC1_WINDOWB_X_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWB_X_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWB_X_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bde, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1bde, &mmCRTC_CRC1_WINDOWB_Y_CONTROL[0], sizeof(mmCRTC_CRC1_WINDOWB_Y_CONTROL)/sizeof(mmCRTC_CRC1_WINDOWB_Y_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1bdf, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_DATA_RG", REG_MMIO, 0x1bdf, &mmCRTC_CRC1_DATA_RG[0], sizeof(mmCRTC_CRC1_DATA_RG)/sizeof(mmCRTC_CRC1_DATA_RG[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_CRC1_DATA_B", REG_MMIO, 0x1be0, NULL, 0, 0, 0 },
+	{ "mmCRTC_CRC1_DATA_B", REG_MMIO, 0x1be0, &mmCRTC_CRC1_DATA_B[0], sizeof(mmCRTC_CRC1_DATA_B)/sizeof(mmCRTC_CRC1_DATA_B[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1be1, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1be1, &mmCRTC_EXT_TIMING_SYNC_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1be2, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1be2, &mmCRTC_EXT_TIMING_SYNC_WINDOW_START[0], sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_START)/sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_START[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1be3, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1be3, &mmCRTC_EXT_TIMING_SYNC_WINDOW_END[0], sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_END)/sizeof(mmCRTC_EXT_TIMING_SYNC_WINDOW_END[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1be4, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1be4, &mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1be5, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1be5, &mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1be6, NULL, 0, 0, 0 },
+	{ "mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1be6, &mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[0], sizeof(mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL)/sizeof(mmCRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmCRTC0_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1be7, NULL, 0, 0, 0 },
+	{ "mmCRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1be7, &mmCRTC_STATIC_SCREEN_CONTROL[0], sizeof(mmCRTC_STATIC_SCREEN_CONTROL)/sizeof(mmCRTC_STATIC_SCREEN_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1be8, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1be8, &mmFMT_CLAMP_COMPONENT_R[0], sizeof(mmFMT_CLAMP_COMPONENT_R)/sizeof(mmFMT_CLAMP_COMPONENT_R[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1be9, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1be9, &mmFMT_CLAMP_COMPONENT_G[0], sizeof(mmFMT_CLAMP_COMPONENT_G)/sizeof(mmFMT_CLAMP_COMPONENT_G[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1bea, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1bea, &mmFMT_CLAMP_COMPONENT_B[0], sizeof(mmFMT_CLAMP_COMPONENT_B)/sizeof(mmFMT_CLAMP_COMPONENT_B[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1beb, NULL, 0, 0, 0 },
+	{ "mmFMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1beb, &mmFMT_TEST_DEBUG_INDEX[0], sizeof(mmFMT_TEST_DEBUG_INDEX)/sizeof(mmFMT_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1bec, NULL, 0, 0, 0 },
+	{ "mmFMT_TEST_DEBUG_DATA", REG_MMIO, 0x1bec, &mmFMT_TEST_DEBUG_DATA[0], sizeof(mmFMT_TEST_DEBUG_DATA)/sizeof(mmFMT_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmFMT0_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1bed, NULL, 0, 0, 0 },
+	{ "mmFMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1bed, &mmFMT_DYNAMIC_EXP_CNTL[0], sizeof(mmFMT_DYNAMIC_EXP_CNTL)/sizeof(mmFMT_DYNAMIC_EXP_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CONTROL", REG_MMIO, 0x1bee, NULL, 0, 0, 0 },
+	{ "mmFMT_CONTROL", REG_MMIO, 0x1bee, &mmFMT_CONTROL[0], sizeof(mmFMT_CONTROL)/sizeof(mmFMT_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1bef, NULL, 0, 0, 0 },
+	{ "mmFMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1bef, &mmFMT_FORCE_OUTPUT_CNTL[0], sizeof(mmFMT_FORCE_OUTPUT_CNTL)/sizeof(mmFMT_FORCE_OUTPUT_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_FORCE_DATA_0_1", REG_MMIO, 0x1bf0, NULL, 0, 0, 0 },
+	{ "mmFMT_FORCE_DATA_0_1", REG_MMIO, 0x1bf0, &mmFMT_FORCE_DATA_0_1[0], sizeof(mmFMT_FORCE_DATA_0_1)/sizeof(mmFMT_FORCE_DATA_0_1[0]), 0, 0 },
+	{ "mmFMT0_FMT_FORCE_DATA_2_3", REG_MMIO, 0x1bf1, NULL, 0, 0, 0 },
+	{ "mmFMT_FORCE_DATA_2_3", REG_MMIO, 0x1bf1, &mmFMT_FORCE_DATA_2_3[0], sizeof(mmFMT_FORCE_DATA_2_3)/sizeof(mmFMT_FORCE_DATA_2_3[0]), 0, 0 },
+	{ "mmFMT0_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1bf2, NULL, 0, 0, 0 },
+	{ "mmFMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1bf2, &mmFMT_BIT_DEPTH_CONTROL[0], sizeof(mmFMT_BIT_DEPTH_CONTROL)/sizeof(mmFMT_BIT_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1bf3, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1bf3, &mmFMT_DITHER_RAND_R_SEED[0], sizeof(mmFMT_DITHER_RAND_R_SEED)/sizeof(mmFMT_DITHER_RAND_R_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1bf4, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1bf4, &mmFMT_DITHER_RAND_G_SEED[0], sizeof(mmFMT_DITHER_RAND_G_SEED)/sizeof(mmFMT_DITHER_RAND_G_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1bf5, NULL, 0, 0, 0 },
+	{ "mmFMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1bf5, &mmFMT_DITHER_RAND_B_SEED[0], sizeof(mmFMT_DITHER_RAND_B_SEED)/sizeof(mmFMT_DITHER_RAND_B_SEED[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1bf6, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1bf6, &mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[0], sizeof(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL)/sizeof(mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1bf7, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1bf7, &mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[0], sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX)/sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX[0]), 0, 0 },
+	{ "mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1bf8, NULL, 0, 0, 0 },
+	{ "mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1bf8, &mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[0], sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX)/sizeof(mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX[0]), 0, 0 },
+	{ "mmFMT0_FMT_CLAMP_CNTL", REG_MMIO, 0x1bf9, NULL, 0, 0, 0 },
+	{ "mmFMT_CLAMP_CNTL", REG_MMIO, 0x1bf9, &mmFMT_CLAMP_CNTL[0], sizeof(mmFMT_CLAMP_CNTL)/sizeof(mmFMT_CLAMP_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_CNTL", REG_MMIO, 0x1bfa, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_CNTL", REG_MMIO, 0x1bfa, &mmFMT_CRC_CNTL[0], sizeof(mmFMT_CRC_CNTL)/sizeof(mmFMT_CRC_CNTL[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfb, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1bfb, &mmFMT_CRC_SIG_RED_GREEN_MASK[0], sizeof(mmFMT_CRC_SIG_RED_GREEN_MASK)/sizeof(mmFMT_CRC_SIG_RED_GREEN_MASK[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfc, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1bfc, &mmFMT_CRC_SIG_BLUE_CONTROL_MASK[0], sizeof(mmFMT_CRC_SIG_BLUE_CONTROL_MASK)/sizeof(mmFMT_CRC_SIG_BLUE_CONTROL_MASK[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1bfd, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1bfd, &mmFMT_CRC_SIG_RED_GREEN[0], sizeof(mmFMT_CRC_SIG_RED_GREEN)/sizeof(mmFMT_CRC_SIG_RED_GREEN[0]), 0, 0 },
+	{ "mmFMT0_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1bfe, NULL, 0, 0, 0 },
+	{ "mmFMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1bfe, &mmFMT_CRC_SIG_BLUE_CONTROL[0], sizeof(mmFMT_CRC_SIG_BLUE_CONTROL)/sizeof(mmFMT_CRC_SIG_BLUE_CONTROL[0]), 0, 0 },
+	{ "mmFMT0_FMT_DEBUG_CNTL", REG_MMIO, 0x1bff, NULL, 0, 0, 0 },
+	{ "mmFMT_DEBUG_CNTL", REG_MMIO, 0x1bff, &mmFMT_DEBUG_CNTL[0], sizeof(mmFMT_DEBUG_CNTL)/sizeof(mmFMT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmDMA_POSITION_LOWER_BASE_ADDRESS", REG_MMIO, 0x1c, &mmDMA_POSITION_LOWER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_M", REG_SMC, 0x1c, &ixDP_AUX1_DEBUG_M[0], sizeof(ixDP_AUX1_DEBUG_M)/sizeof(ixDP_AUX1_DEBUG_M[0]), 0, 0 },
+	{ "mmDIG0_DIG_FE_CNTL", REG_MMIO, 0x1c00, NULL, 0, 0, 0 },
+	{ "mmDIG_FE_CNTL", REG_MMIO, 0x1c00, &mmDIG_FE_CNTL[0], sizeof(mmDIG_FE_CNTL)/sizeof(mmDIG_FE_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x1c01, NULL, 0, 0, 0 },
+	{ "mmDIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x1c01, &mmDIG_OUTPUT_CRC_CNTL[0], sizeof(mmDIG_OUTPUT_CRC_CNTL)/sizeof(mmDIG_OUTPUT_CRC_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x1c02, NULL, 0, 0, 0 },
+	{ "mmDIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x1c02, &mmDIG_OUTPUT_CRC_RESULT[0], sizeof(mmDIG_OUTPUT_CRC_RESULT)/sizeof(mmDIG_OUTPUT_CRC_RESULT[0]), 0, 0 },
+	{ "mmDIG0_DIG_CLOCK_PATTERN", REG_MMIO, 0x1c03, NULL, 0, 0, 0 },
+	{ "mmDIG_CLOCK_PATTERN", REG_MMIO, 0x1c03, &mmDIG_CLOCK_PATTERN[0], sizeof(mmDIG_CLOCK_PATTERN)/sizeof(mmDIG_CLOCK_PATTERN[0]), 0, 0 },
+	{ "mmDIG0_DIG_TEST_PATTERN", REG_MMIO, 0x1c04, NULL, 0, 0, 0 },
+	{ "mmDIG_TEST_PATTERN", REG_MMIO, 0x1c04, &mmDIG_TEST_PATTERN[0], sizeof(mmDIG_TEST_PATTERN)/sizeof(mmDIG_TEST_PATTERN[0]), 0, 0 },
+	{ "mmDIG0_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x1c05, NULL, 0, 0, 0 },
+	{ "mmDIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x1c05, &mmDIG_RANDOM_PATTERN_SEED[0], sizeof(mmDIG_RANDOM_PATTERN_SEED)/sizeof(mmDIG_RANDOM_PATTERN_SEED[0]), 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x1c08, NULL, 0, 0, 0 },
+	{ "mmDIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x1c08, &mmDIG_DISPCLK_SWITCH_CNTL[0], sizeof(mmDIG_DISPCLK_SWITCH_CNTL)/sizeof(mmDIG_DISPCLK_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x1c09, NULL, 0, 0, 0 },
+	{ "mmDIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x1c09, &mmDIG_DISPCLK_SWITCH_STATUS[0], sizeof(mmDIG_DISPCLK_SWITCH_STATUS)/sizeof(mmDIG_DISPCLK_SWITCH_STATUS[0]), 0, 0 },
+	{ "mmDIG0_DIG_FIFO_STATUS", REG_MMIO, 0x1c0a, NULL, 0, 0, 0 },
+	{ "mmDIG_FIFO_STATUS", REG_MMIO, 0x1c0a, &mmDIG_FIFO_STATUS[0], sizeof(mmDIG_FIFO_STATUS)/sizeof(mmDIG_FIFO_STATUS[0]), 0, 0 },
+	{ "mmDIG0_HDMI_CONTROL", REG_MMIO, 0x1c0c, NULL, 0, 0, 0 },
+	{ "mmHDMI_CONTROL", REG_MMIO, 0x1c0c, &mmHDMI_CONTROL[0], sizeof(mmHDMI_CONTROL)/sizeof(mmHDMI_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_STATUS", REG_MMIO, 0x1c0d, NULL, 0, 0, 0 },
+	{ "mmHDMI_STATUS", REG_MMIO, 0x1c0d, &mmHDMI_STATUS[0], sizeof(mmHDMI_STATUS)/sizeof(mmHDMI_STATUS[0]), 0, 0 },
+	{ "mmDIG0_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1c0e, NULL, 0, 0, 0 },
+	{ "mmHDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1c0e, &mmHDMI_AUDIO_PACKET_CONTROL[0], sizeof(mmHDMI_AUDIO_PACKET_CONTROL)/sizeof(mmHDMI_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x1c0f, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x1c0f, &mmHDMI_ACR_PACKET_CONTROL[0], sizeof(mmHDMI_ACR_PACKET_CONTROL)/sizeof(mmHDMI_ACR_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x1c10, NULL, 0, 0, 0 },
+	{ "mmHDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x1c10, &mmHDMI_VBI_PACKET_CONTROL[0], sizeof(mmHDMI_VBI_PACKET_CONTROL)/sizeof(mmHDMI_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x1c11, NULL, 0, 0, 0 },
+	{ "mmHDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x1c11, &mmHDMI_INFOFRAME_CONTROL0[0], sizeof(mmHDMI_INFOFRAME_CONTROL0)/sizeof(mmHDMI_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x1c12, NULL, 0, 0, 0 },
+	{ "mmHDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x1c12, &mmHDMI_INFOFRAME_CONTROL1[0], sizeof(mmHDMI_INFOFRAME_CONTROL1)/sizeof(mmHDMI_INFOFRAME_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x1c13, NULL, 0, 0, 0 },
+	{ "mmHDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x1c13, &mmHDMI_GENERIC_PACKET_CONTROL0[0], sizeof(mmHDMI_GENERIC_PACKET_CONTROL0)/sizeof(mmHDMI_GENERIC_PACKET_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x1c14, NULL, 0, 0, 0 },
+	{ "mmAFMT_INTERRUPT_STATUS", REG_MMIO, 0x1c14, NULL, 0, 0, 0 },
+	{ "mmDIG0_HDMI_GC", REG_MMIO, 0x1c16, NULL, 0, 0, 0 },
+	{ "mmHDMI_GC", REG_MMIO, 0x1c16, &mmHDMI_GC[0], sizeof(mmHDMI_GC)/sizeof(mmHDMI_GC[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x1c17, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x1c17, &mmAFMT_AUDIO_PACKET_CONTROL2[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL2)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_0", REG_MMIO, 0x1c18, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_0", REG_MMIO, 0x1c18, &mmAFMT_ISRC1_0[0], sizeof(mmAFMT_ISRC1_0)/sizeof(mmAFMT_ISRC1_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_1", REG_MMIO, 0x1c19, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_1", REG_MMIO, 0x1c19, &mmAFMT_ISRC1_1[0], sizeof(mmAFMT_ISRC1_1)/sizeof(mmAFMT_ISRC1_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_2", REG_MMIO, 0x1c1a, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_2", REG_MMIO, 0x1c1a, &mmAFMT_ISRC1_2[0], sizeof(mmAFMT_ISRC1_2)/sizeof(mmAFMT_ISRC1_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_3", REG_MMIO, 0x1c1b, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_3", REG_MMIO, 0x1c1b, &mmAFMT_ISRC1_3[0], sizeof(mmAFMT_ISRC1_3)/sizeof(mmAFMT_ISRC1_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC1_4", REG_MMIO, 0x1c1c, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC1_4", REG_MMIO, 0x1c1c, &mmAFMT_ISRC1_4[0], sizeof(mmAFMT_ISRC1_4)/sizeof(mmAFMT_ISRC1_4[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_0", REG_MMIO, 0x1c1d, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_0", REG_MMIO, 0x1c1d, &mmAFMT_ISRC2_0[0], sizeof(mmAFMT_ISRC2_0)/sizeof(mmAFMT_ISRC2_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_1", REG_MMIO, 0x1c1e, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_1", REG_MMIO, 0x1c1e, &mmAFMT_ISRC2_1[0], sizeof(mmAFMT_ISRC2_1)/sizeof(mmAFMT_ISRC2_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_2", REG_MMIO, 0x1c1f, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_2", REG_MMIO, 0x1c1f, &mmAFMT_ISRC2_2[0], sizeof(mmAFMT_ISRC2_2)/sizeof(mmAFMT_ISRC2_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_ISRC2_3", REG_MMIO, 0x1c20, NULL, 0, 0, 0 },
+	{ "mmAFMT_ISRC2_3", REG_MMIO, 0x1c20, &mmAFMT_ISRC2_3[0], sizeof(mmAFMT_ISRC2_3)/sizeof(mmAFMT_ISRC2_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO0", REG_MMIO, 0x1c21, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO0", REG_MMIO, 0x1c21, &mmAFMT_AVI_INFO0[0], sizeof(mmAFMT_AVI_INFO0)/sizeof(mmAFMT_AVI_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO1", REG_MMIO, 0x1c22, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO1", REG_MMIO, 0x1c22, &mmAFMT_AVI_INFO1[0], sizeof(mmAFMT_AVI_INFO1)/sizeof(mmAFMT_AVI_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO2", REG_MMIO, 0x1c23, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO2", REG_MMIO, 0x1c23, &mmAFMT_AVI_INFO2[0], sizeof(mmAFMT_AVI_INFO2)/sizeof(mmAFMT_AVI_INFO2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AVI_INFO3", REG_MMIO, 0x1c24, NULL, 0, 0, 0 },
+	{ "mmAFMT_AVI_INFO3", REG_MMIO, 0x1c24, &mmAFMT_AVI_INFO3[0], sizeof(mmAFMT_AVI_INFO3)/sizeof(mmAFMT_AVI_INFO3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_MPEG_INFO0", REG_MMIO, 0x1c25, NULL, 0, 0, 0 },
+	{ "mmAFMT_MPEG_INFO0", REG_MMIO, 0x1c25, &mmAFMT_MPEG_INFO0[0], sizeof(mmAFMT_MPEG_INFO0)/sizeof(mmAFMT_MPEG_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_MPEG_INFO1", REG_MMIO, 0x1c26, NULL, 0, 0, 0 },
+	{ "mmAFMT_MPEG_INFO1", REG_MMIO, 0x1c26, &mmAFMT_MPEG_INFO1[0], sizeof(mmAFMT_MPEG_INFO1)/sizeof(mmAFMT_MPEG_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_HDR", REG_MMIO, 0x1c27, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_HDR", REG_MMIO, 0x1c27, &mmAFMT_GENERIC_HDR[0], sizeof(mmAFMT_GENERIC_HDR)/sizeof(mmAFMT_GENERIC_HDR[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_0", REG_MMIO, 0x1c28, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_0", REG_MMIO, 0x1c28, &mmAFMT_GENERIC_0[0], sizeof(mmAFMT_GENERIC_0)/sizeof(mmAFMT_GENERIC_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_1", REG_MMIO, 0x1c29, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_1", REG_MMIO, 0x1c29, &mmAFMT_GENERIC_1[0], sizeof(mmAFMT_GENERIC_1)/sizeof(mmAFMT_GENERIC_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_2", REG_MMIO, 0x1c2a, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_2", REG_MMIO, 0x1c2a, &mmAFMT_GENERIC_2[0], sizeof(mmAFMT_GENERIC_2)/sizeof(mmAFMT_GENERIC_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_3", REG_MMIO, 0x1c2b, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_3", REG_MMIO, 0x1c2b, &mmAFMT_GENERIC_3[0], sizeof(mmAFMT_GENERIC_3)/sizeof(mmAFMT_GENERIC_3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_4", REG_MMIO, 0x1c2c, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_4", REG_MMIO, 0x1c2c, &mmAFMT_GENERIC_4[0], sizeof(mmAFMT_GENERIC_4)/sizeof(mmAFMT_GENERIC_4[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_5", REG_MMIO, 0x1c2d, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_5", REG_MMIO, 0x1c2d, &mmAFMT_GENERIC_5[0], sizeof(mmAFMT_GENERIC_5)/sizeof(mmAFMT_GENERIC_5[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_6", REG_MMIO, 0x1c2e, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_6", REG_MMIO, 0x1c2e, &mmAFMT_GENERIC_6[0], sizeof(mmAFMT_GENERIC_6)/sizeof(mmAFMT_GENERIC_6[0]), 0, 0 },
+	{ "mmDIG0_AFMT_GENERIC_7", REG_MMIO, 0x1c2f, NULL, 0, 0, 0 },
+	{ "mmAFMT_GENERIC_7", REG_MMIO, 0x1c2f, &mmAFMT_GENERIC_7[0], sizeof(mmAFMT_GENERIC_7)/sizeof(mmAFMT_GENERIC_7[0]), 0, 0 },
+	{ "mmDIG0_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x1c30, NULL, 0, 0, 0 },
+	{ "mmHDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x1c30, &mmHDMI_GENERIC_PACKET_CONTROL1[0], sizeof(mmHDMI_GENERIC_PACKET_CONTROL1)/sizeof(mmHDMI_GENERIC_PACKET_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_0", REG_MMIO, 0x1c37, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_32_0", REG_MMIO, 0x1c37, &mmHDMI_ACR_32_0[0], sizeof(mmHDMI_ACR_32_0)/sizeof(mmHDMI_ACR_32_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_32_1", REG_MMIO, 0x1c38, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_32_1", REG_MMIO, 0x1c38, &mmHDMI_ACR_32_1[0], sizeof(mmHDMI_ACR_32_1)/sizeof(mmHDMI_ACR_32_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_0", REG_MMIO, 0x1c39, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_44_0", REG_MMIO, 0x1c39, &mmHDMI_ACR_44_0[0], sizeof(mmHDMI_ACR_44_0)/sizeof(mmHDMI_ACR_44_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_44_1", REG_MMIO, 0x1c3a, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_44_1", REG_MMIO, 0x1c3a, &mmHDMI_ACR_44_1[0], sizeof(mmHDMI_ACR_44_1)/sizeof(mmHDMI_ACR_44_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_0", REG_MMIO, 0x1c3b, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_48_0", REG_MMIO, 0x1c3b, &mmHDMI_ACR_48_0[0], sizeof(mmHDMI_ACR_48_0)/sizeof(mmHDMI_ACR_48_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_48_1", REG_MMIO, 0x1c3c, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_48_1", REG_MMIO, 0x1c3c, &mmHDMI_ACR_48_1[0], sizeof(mmHDMI_ACR_48_1)/sizeof(mmHDMI_ACR_48_1[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_0", REG_MMIO, 0x1c3d, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_STATUS_0", REG_MMIO, 0x1c3d, &mmHDMI_ACR_STATUS_0[0], sizeof(mmHDMI_ACR_STATUS_0)/sizeof(mmHDMI_ACR_STATUS_0[0]), 0, 0 },
+	{ "mmDIG0_HDMI_ACR_STATUS_1", REG_MMIO, 0x1c3e, NULL, 0, 0, 0 },
+	{ "mmHDMI_ACR_STATUS_1", REG_MMIO, 0x1c3e, &mmHDMI_ACR_STATUS_1[0], sizeof(mmHDMI_ACR_STATUS_1)/sizeof(mmHDMI_ACR_STATUS_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_INFO0", REG_MMIO, 0x1c3f, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO0", REG_MMIO, 0x1c3f, &mmAFMT_AUDIO_INFO0[0], sizeof(mmAFMT_AUDIO_INFO0)/sizeof(mmAFMT_AUDIO_INFO0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_INFO1", REG_MMIO, 0x1c40, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_INFO1", REG_MMIO, 0x1c40, &mmAFMT_AUDIO_INFO1[0], sizeof(mmAFMT_AUDIO_INFO1)/sizeof(mmAFMT_AUDIO_INFO1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_0", REG_MMIO, 0x1c41, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_0", REG_MMIO, 0x1c41, &mmAFMT_60958_0[0], sizeof(mmAFMT_60958_0)/sizeof(mmAFMT_60958_0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_1", REG_MMIO, 0x1c42, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_1", REG_MMIO, 0x1c42, &mmAFMT_60958_1[0], sizeof(mmAFMT_60958_1)/sizeof(mmAFMT_60958_1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x1c43, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x1c43, &mmAFMT_AUDIO_CRC_CONTROL[0], sizeof(mmAFMT_AUDIO_CRC_CONTROL)/sizeof(mmAFMT_AUDIO_CRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL0", REG_MMIO, 0x1c44, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL0", REG_MMIO, 0x1c44, &mmAFMT_RAMP_CONTROL0[0], sizeof(mmAFMT_RAMP_CONTROL0)/sizeof(mmAFMT_RAMP_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL1", REG_MMIO, 0x1c45, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL1", REG_MMIO, 0x1c45, &mmAFMT_RAMP_CONTROL1[0], sizeof(mmAFMT_RAMP_CONTROL1)/sizeof(mmAFMT_RAMP_CONTROL1[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL2", REG_MMIO, 0x1c46, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL2", REG_MMIO, 0x1c46, &mmAFMT_RAMP_CONTROL2[0], sizeof(mmAFMT_RAMP_CONTROL2)/sizeof(mmAFMT_RAMP_CONTROL2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_RAMP_CONTROL3", REG_MMIO, 0x1c47, NULL, 0, 0, 0 },
+	{ "mmAFMT_RAMP_CONTROL3", REG_MMIO, 0x1c47, &mmAFMT_RAMP_CONTROL3[0], sizeof(mmAFMT_RAMP_CONTROL3)/sizeof(mmAFMT_RAMP_CONTROL3[0]), 0, 0 },
+	{ "mmDIG0_AFMT_60958_2", REG_MMIO, 0x1c48, NULL, 0, 0, 0 },
+	{ "mmAFMT_60958_2", REG_MMIO, 0x1c48, &mmAFMT_60958_2[0], sizeof(mmAFMT_60958_2)/sizeof(mmAFMT_60958_2[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x1c49, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x1c49, &mmAFMT_AUDIO_CRC_RESULT[0], sizeof(mmAFMT_AUDIO_CRC_RESULT)/sizeof(mmAFMT_AUDIO_CRC_RESULT[0]), 0, 0 },
+	{ "mmDIG0_AFMT_STATUS", REG_MMIO, 0x1c4a, NULL, 0, 0, 0 },
+	{ "mmAFMT_STATUS", REG_MMIO, 0x1c4a, &mmAFMT_STATUS[0], sizeof(mmAFMT_STATUS)/sizeof(mmAFMT_STATUS[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1c4b, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1c4b, &mmAFMT_AUDIO_PACKET_CONTROL[0], sizeof(mmAFMT_AUDIO_PACKET_CONTROL)/sizeof(mmAFMT_AUDIO_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x1c4c, NULL, 0, 0, 0 },
+	{ "mmAFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x1c4c, &mmAFMT_VBI_PACKET_CONTROL[0], sizeof(mmAFMT_VBI_PACKET_CONTROL)/sizeof(mmAFMT_VBI_PACKET_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x1c4d, NULL, 0, 0, 0 },
+	{ "mmAFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x1c4d, &mmAFMT_INFOFRAME_CONTROL0[0], sizeof(mmAFMT_INFOFRAME_CONTROL0)/sizeof(mmAFMT_INFOFRAME_CONTROL0[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x1c4f, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x1c4f, &mmAFMT_AUDIO_SRC_CONTROL[0], sizeof(mmAFMT_AUDIO_SRC_CONTROL)/sizeof(mmAFMT_AUDIO_SRC_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_CNTL", REG_MMIO, 0x1c50, NULL, 0, 0, 0 },
+	{ "mmDIG_BE_CNTL", REG_MMIO, 0x1c50, &mmDIG_BE_CNTL[0], sizeof(mmDIG_BE_CNTL)/sizeof(mmDIG_BE_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_BE_EN_CNTL", REG_MMIO, 0x1c51, NULL, 0, 0, 0 },
+	{ "mmDIG_BE_EN_CNTL", REG_MMIO, 0x1c51, &mmDIG_BE_EN_CNTL[0], sizeof(mmDIG_BE_EN_CNTL)/sizeof(mmDIG_BE_EN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x1c52, NULL, 0, 0, 0 },
+	{ "mmAFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x1c52, &mmAFMT_AUDIO_DBG_DTO_CNTL[0], sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL)/sizeof(mmAFMT_AUDIO_DBG_DTO_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CNTL", REG_MMIO, 0x1c7c, NULL, 0, 0, 0 },
+	{ "mmTMDS_CNTL", REG_MMIO, 0x1c7c, &mmTMDS_CNTL[0], sizeof(mmTMDS_CNTL)/sizeof(mmTMDS_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL_CHAR", REG_MMIO, 0x1c7d, NULL, 0, 0, 0 },
+	{ "mmTMDS_CONTROL_CHAR", REG_MMIO, 0x1c7d, &mmTMDS_CONTROL_CHAR[0], sizeof(mmTMDS_CONTROL_CHAR)/sizeof(mmTMDS_CONTROL_CHAR[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x1c7e, NULL, 0, 0, 0 },
+	{ "mmTMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x1c7e, &mmTMDS_CONTROL0_FEEDBACK[0], sizeof(mmTMDS_CONTROL0_FEEDBACK)/sizeof(mmTMDS_CONTROL0_FEEDBACK[0]), 0, 0 },
+	{ "mmDIG0_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x1c7f, NULL, 0, 0, 0 },
+	{ "mmTMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x1c7f, &mmTMDS_STEREOSYNC_CTL_SEL[0], sizeof(mmTMDS_STEREOSYNC_CTL_SEL)/sizeof(mmTMDS_STEREOSYNC_CTL_SEL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x1c80, NULL, 0, 0, 0 },
+	{ "mmTMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x1c80, &mmTMDS_SYNC_CHAR_PATTERN_0_1[0], sizeof(mmTMDS_SYNC_CHAR_PATTERN_0_1)/sizeof(mmTMDS_SYNC_CHAR_PATTERN_0_1[0]), 0, 0 },
+	{ "mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x1c81, NULL, 0, 0, 0 },
+	{ "mmTMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x1c81, &mmTMDS_SYNC_CHAR_PATTERN_2_3[0], sizeof(mmTMDS_SYNC_CHAR_PATTERN_2_3)/sizeof(mmTMDS_SYNC_CHAR_PATTERN_2_3[0]), 0, 0 },
+	{ "mmDIG0_TMDS_DEBUG", REG_MMIO, 0x1c82, NULL, 0, 0, 0 },
+	{ "mmTMDS_DEBUG", REG_MMIO, 0x1c82, &mmTMDS_DEBUG[0], sizeof(mmTMDS_DEBUG)/sizeof(mmTMDS_DEBUG[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL_BITS", REG_MMIO, 0x1c83, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL_BITS", REG_MMIO, 0x1c83, &mmTMDS_CTL_BITS[0], sizeof(mmTMDS_CTL_BITS)/sizeof(mmTMDS_CTL_BITS[0]), 0, 0 },
+	{ "mmDIG0_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x1c84, NULL, 0, 0, 0 },
+	{ "mmTMDS_DCBALANCER_CONTROL", REG_MMIO, 0x1c84, &mmTMDS_DCBALANCER_CONTROL[0], sizeof(mmTMDS_DCBALANCER_CONTROL)/sizeof(mmTMDS_DCBALANCER_CONTROL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x1c86, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x1c86, &mmTMDS_CTL0_1_GEN_CNTL[0], sizeof(mmTMDS_CTL0_1_GEN_CNTL)/sizeof(mmTMDS_CTL0_1_GEN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x1c87, NULL, 0, 0, 0 },
+	{ "mmTMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x1c87, &mmTMDS_CTL2_3_GEN_CNTL[0], sizeof(mmTMDS_CTL2_3_GEN_CNTL)/sizeof(mmTMDS_CTL2_3_GEN_CNTL[0]), 0, 0 },
+	{ "mmDIG0_LVDS_DATA_CNTL", REG_MMIO, 0x1c8c, NULL, 0, 0, 0 },
+	{ "mmLVDS_DATA_CNTL", REG_MMIO, 0x1c8c, &mmLVDS_DATA_CNTL[0], sizeof(mmLVDS_DATA_CNTL)/sizeof(mmLVDS_DATA_CNTL[0]), 0, 0 },
+	{ "mmDIG0_DIG_LANE_ENABLE", REG_MMIO, 0x1c8d, NULL, 0, 0, 0 },
+	{ "mmDIG_LANE_ENABLE", REG_MMIO, 0x1c8d, &mmDIG_LANE_ENABLE[0], sizeof(mmDIG_LANE_ENABLE)/sizeof(mmDIG_LANE_ENABLE[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL", REG_MMIO, 0x1ca0, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_CNTL", REG_MMIO, 0x1ca0, &mmDP_SEC_CNTL[0], sizeof(mmDP_SEC_CNTL)/sizeof(mmDP_SEC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING1", REG_MMIO, 0x1ca1, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING1", REG_MMIO, 0x1ca1, &mmDP_SEC_FRAMING1[0], sizeof(mmDP_SEC_FRAMING1)/sizeof(mmDP_SEC_FRAMING1[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING2", REG_MMIO, 0x1ca2, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING2", REG_MMIO, 0x1ca2, &mmDP_SEC_FRAMING2[0], sizeof(mmDP_SEC_FRAMING2)/sizeof(mmDP_SEC_FRAMING2[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING3", REG_MMIO, 0x1ca3, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING3", REG_MMIO, 0x1ca3, &mmDP_SEC_FRAMING3[0], sizeof(mmDP_SEC_FRAMING3)/sizeof(mmDP_SEC_FRAMING3[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_FRAMING4", REG_MMIO, 0x1ca4, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_FRAMING4", REG_MMIO, 0x1ca4, &mmDP_SEC_FRAMING4[0], sizeof(mmDP_SEC_FRAMING4)/sizeof(mmDP_SEC_FRAMING4[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N", REG_MMIO, 0x1ca5, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_N", REG_MMIO, 0x1ca5, &mmDP_SEC_AUD_N[0], sizeof(mmDP_SEC_AUD_N)/sizeof(mmDP_SEC_AUD_N[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x1ca6, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_N_READBACK", REG_MMIO, 0x1ca6, &mmDP_SEC_AUD_N_READBACK[0], sizeof(mmDP_SEC_AUD_N_READBACK)/sizeof(mmDP_SEC_AUD_N_READBACK[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M", REG_MMIO, 0x1ca7, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_M", REG_MMIO, 0x1ca7, &mmDP_SEC_AUD_M[0], sizeof(mmDP_SEC_AUD_M)/sizeof(mmDP_SEC_AUD_M[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x1ca8, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_AUD_M_READBACK", REG_MMIO, 0x1ca8, &mmDP_SEC_AUD_M_READBACK[0], sizeof(mmDP_SEC_AUD_M_READBACK)/sizeof(mmDP_SEC_AUD_M_READBACK[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_TIMESTAMP", REG_MMIO, 0x1ca9, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_TIMESTAMP", REG_MMIO, 0x1ca9, &mmDP_SEC_TIMESTAMP[0], sizeof(mmDP_SEC_TIMESTAMP)/sizeof(mmDP_SEC_TIMESTAMP[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_PACKET_CNTL", REG_MMIO, 0x1caa, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_PACKET_CNTL", REG_MMIO, 0x1caa, &mmDP_SEC_PACKET_CNTL[0], sizeof(mmDP_SEC_PACKET_CNTL)/sizeof(mmDP_SEC_PACKET_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_SEC_CNTL1", REG_MMIO, 0x1cab, NULL, 0, 0, 0 },
+	{ "mmDP_SEC_CNTL1", REG_MMIO, 0x1cab, &mmDP_SEC_CNTL1[0], sizeof(mmDP_SEC_CNTL1)/sizeof(mmDP_SEC_CNTL1[0]), 0, 0 },
+	{ "mmDP0_DP_LINK_CNTL", REG_MMIO, 0x1cc0, NULL, 0, 0, 0 },
+	{ "mmDP_LINK_CNTL", REG_MMIO, 0x1cc0, &mmDP_LINK_CNTL[0], sizeof(mmDP_LINK_CNTL)/sizeof(mmDP_LINK_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_PIXEL_FORMAT", REG_MMIO, 0x1cc1, NULL, 0, 0, 0 },
+	{ "mmDP_PIXEL_FORMAT", REG_MMIO, 0x1cc1, &mmDP_PIXEL_FORMAT[0], sizeof(mmDP_PIXEL_FORMAT)/sizeof(mmDP_PIXEL_FORMAT[0]), 0, 0 },
+	{ "mmDP0_DP_CONFIG", REG_MMIO, 0x1cc2, NULL, 0, 0, 0 },
+	{ "mmDP_CONFIG", REG_MMIO, 0x1cc2, &mmDP_CONFIG[0], sizeof(mmDP_CONFIG)/sizeof(mmDP_CONFIG[0]), 0, 0 },
+	{ "mmDP0_DP_VID_STREAM_CNTL", REG_MMIO, 0x1cc3, NULL, 0, 0, 0 },
+	{ "mmDP_VID_STREAM_CNTL", REG_MMIO, 0x1cc3, &mmDP_VID_STREAM_CNTL[0], sizeof(mmDP_VID_STREAM_CNTL)/sizeof(mmDP_VID_STREAM_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_STEER_FIFO", REG_MMIO, 0x1cc4, NULL, 0, 0, 0 },
+	{ "mmDP_STEER_FIFO", REG_MMIO, 0x1cc4, &mmDP_STEER_FIFO[0], sizeof(mmDP_STEER_FIFO)/sizeof(mmDP_STEER_FIFO[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_MISC", REG_MMIO, 0x1cc5, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_MISC", REG_MMIO, 0x1cc5, &mmDP_MSA_MISC[0], sizeof(mmDP_MSA_MISC)/sizeof(mmDP_MSA_MISC[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x1cc6, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x1cc6, &mmDP_DPHY_CRC_MST_CNTL[0], sizeof(mmDP_DPHY_CRC_MST_CNTL)/sizeof(mmDP_DPHY_CRC_MST_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x1cc7, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x1cc7, &mmDP_DPHY_CRC_MST_STATUS[0], sizeof(mmDP_DPHY_CRC_MST_STATUS)/sizeof(mmDP_DPHY_CRC_MST_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x1cc8, NULL, 0, 0, 0 },
+	{ "mmDP_HBR2_EYE_PATTERN", REG_MMIO, 0x1cc8, &mmDP_HBR2_EYE_PATTERN[0], sizeof(mmDP_HBR2_EYE_PATTERN)/sizeof(mmDP_HBR2_EYE_PATTERN[0]), 0, 0 },
+	{ "mmDP0_DP_VID_TIMING", REG_MMIO, 0x1cc9, NULL, 0, 0, 0 },
+	{ "mmDP_VID_TIMING", REG_MMIO, 0x1cc9, &mmDP_VID_TIMING[0], sizeof(mmDP_VID_TIMING)/sizeof(mmDP_VID_TIMING[0]), 0, 0 },
+	{ "mmDP0_DP_VID_N", REG_MMIO, 0x1cca, NULL, 0, 0, 0 },
+	{ "mmDP_VID_N", REG_MMIO, 0x1cca, &mmDP_VID_N[0], sizeof(mmDP_VID_N)/sizeof(mmDP_VID_N[0]), 0, 0 },
+	{ "mmDP0_DP_VID_M", REG_MMIO, 0x1ccb, NULL, 0, 0, 0 },
+	{ "mmDP_VID_M", REG_MMIO, 0x1ccb, &mmDP_VID_M[0], sizeof(mmDP_VID_M)/sizeof(mmDP_VID_M[0]), 0, 0 },
+	{ "mmDP0_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x1ccc, NULL, 0, 0, 0 },
+	{ "mmDP_LINK_FRAMING_CNTL", REG_MMIO, 0x1ccc, &mmDP_LINK_FRAMING_CNTL[0], sizeof(mmDP_LINK_FRAMING_CNTL)/sizeof(mmDP_LINK_FRAMING_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_VID_MSA_VBID", REG_MMIO, 0x1ccd, NULL, 0, 0, 0 },
+	{ "mmDP_VID_MSA_VBID", REG_MMIO, 0x1ccd, &mmDP_VID_MSA_VBID[0], sizeof(mmDP_VID_MSA_VBID)/sizeof(mmDP_VID_MSA_VBID[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x1cce, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_FAST_TRAINING", REG_MMIO, 0x1cce, &mmDP_DPHY_FAST_TRAINING[0], sizeof(mmDP_DPHY_FAST_TRAINING)/sizeof(mmDP_DPHY_FAST_TRAINING[0]), 0, 0 },
+	{ "mmDP0_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x1ccf, NULL, 0, 0, 0 },
+	{ "mmDP_VID_INTERRUPT_CNTL", REG_MMIO, 0x1ccf, &mmDP_VID_INTERRUPT_CNTL[0], sizeof(mmDP_VID_INTERRUPT_CNTL)/sizeof(mmDP_VID_INTERRUPT_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CNTL", REG_MMIO, 0x1cd0, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CNTL", REG_MMIO, 0x1cd0, &mmDP_DPHY_CNTL[0], sizeof(mmDP_DPHY_CNTL)/sizeof(mmDP_DPHY_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x1cd1, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x1cd1, &mmDP_DPHY_TRAINING_PATTERN_SEL[0], sizeof(mmDP_DPHY_TRAINING_PATTERN_SEL)/sizeof(mmDP_DPHY_TRAINING_PATTERN_SEL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM0", REG_MMIO, 0x1cd2, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM0", REG_MMIO, 0x1cd2, &mmDP_DPHY_SYM0[0], sizeof(mmDP_DPHY_SYM0)/sizeof(mmDP_DPHY_SYM0[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x1cd3, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_8B10B_CNTL", REG_MMIO, 0x1cd3, &mmDP_DPHY_8B10B_CNTL[0], sizeof(mmDP_DPHY_8B10B_CNTL)/sizeof(mmDP_DPHY_8B10B_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x1cd4, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_PRBS_CNTL", REG_MMIO, 0x1cd4, &mmDP_DPHY_PRBS_CNTL[0], sizeof(mmDP_DPHY_PRBS_CNTL)/sizeof(mmDP_DPHY_PRBS_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x1cd5, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SCRAM_CNTL", REG_MMIO, 0x1cd5, &mmDP_DPHY_SCRAM_CNTL[0], sizeof(mmDP_DPHY_SCRAM_CNTL)/sizeof(mmDP_DPHY_SCRAM_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_EN", REG_MMIO, 0x1cd6, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_EN", REG_MMIO, 0x1cd6, &mmDP_DPHY_CRC_EN[0], sizeof(mmDP_DPHY_CRC_EN)/sizeof(mmDP_DPHY_CRC_EN[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_CNTL", REG_MMIO, 0x1cd7, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_CNTL", REG_MMIO, 0x1cd7, &mmDP_DPHY_CRC_CNTL[0], sizeof(mmDP_DPHY_CRC_CNTL)/sizeof(mmDP_DPHY_CRC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_CRC_RESULT", REG_MMIO, 0x1cd8, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_CRC_RESULT", REG_MMIO, 0x1cd8, &mmDP_DPHY_CRC_RESULT[0], sizeof(mmDP_DPHY_CRC_RESULT)/sizeof(mmDP_DPHY_CRC_RESULT[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_COLORIMETRY", REG_MMIO, 0x1cda, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_COLORIMETRY", REG_MMIO, 0x1cda, &mmDP_MSA_COLORIMETRY[0], sizeof(mmDP_MSA_COLORIMETRY)/sizeof(mmDP_MSA_COLORIMETRY[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_MISC_CNTL", REG_MMIO, 0x1cdb, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_MISC_CNTL", REG_MMIO, 0x1cdb, &mmDP_MSE_MISC_CNTL[0], sizeof(mmDP_MSE_MISC_CNTL)/sizeof(mmDP_MSE_MISC_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM2", REG_MMIO, 0x1cdf, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM2", REG_MMIO, 0x1cdf, &mmDP_DPHY_SYM2[0], sizeof(mmDP_DPHY_SYM2)/sizeof(mmDP_DPHY_SYM2[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_SYM1", REG_MMIO, 0x1ce0, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_SYM1", REG_MMIO, 0x1ce0, &mmDP_DPHY_SYM1[0], sizeof(mmDP_DPHY_SYM1)/sizeof(mmDP_DPHY_SYM1[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_CNTL", REG_MMIO, 0x1ce1, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_RATE_CNTL", REG_MMIO, 0x1ce1, &mmDP_MSE_RATE_CNTL[0], sizeof(mmDP_MSE_RATE_CNTL)/sizeof(mmDP_MSE_RATE_CNTL[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_RATE_UPDATE", REG_MMIO, 0x1ce3, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_RATE_UPDATE", REG_MMIO, 0x1ce3, &mmDP_MSE_RATE_UPDATE[0], sizeof(mmDP_MSE_RATE_UPDATE)/sizeof(mmDP_MSE_RATE_UPDATE[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT0", REG_MMIO, 0x1ce4, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT0", REG_MMIO, 0x1ce4, &mmDP_MSE_SAT0[0], sizeof(mmDP_MSE_SAT0)/sizeof(mmDP_MSE_SAT0[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT1", REG_MMIO, 0x1ce5, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT1", REG_MMIO, 0x1ce5, &mmDP_MSE_SAT1[0], sizeof(mmDP_MSE_SAT1)/sizeof(mmDP_MSE_SAT1[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT2", REG_MMIO, 0x1ce6, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT2", REG_MMIO, 0x1ce6, &mmDP_MSE_SAT2[0], sizeof(mmDP_MSE_SAT2)/sizeof(mmDP_MSE_SAT2[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_SAT_UPDATE", REG_MMIO, 0x1ce7, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_SAT_UPDATE", REG_MMIO, 0x1ce7, &mmDP_MSE_SAT_UPDATE[0], sizeof(mmDP_MSE_SAT_UPDATE)/sizeof(mmDP_MSE_SAT_UPDATE[0]), 0, 0 },
+	{ "mmDP0_DP_MSE_LINK_TIMING", REG_MMIO, 0x1ce8, NULL, 0, 0, 0 },
+	{ "mmDP_MSE_LINK_TIMING", REG_MMIO, 0x1ce8, &mmDP_MSE_LINK_TIMING[0], sizeof(mmDP_MSE_LINK_TIMING)/sizeof(mmDP_MSE_LINK_TIMING[0]), 0, 0 },
+	{ "mmDP0_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x1ce9, NULL, 0, 0, 0 },
+	{ "mmDP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x1ce9, &mmDP_DPHY_FAST_TRAINING_STATUS[0], sizeof(mmDP_DPHY_FAST_TRAINING_STATUS)/sizeof(mmDP_DPHY_FAST_TRAINING_STATUS[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x1cea, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x1cea, &mmDP_MSA_V_TIMING_OVERRIDE1[0], sizeof(mmDP_MSA_V_TIMING_OVERRIDE1)/sizeof(mmDP_MSA_V_TIMING_OVERRIDE1[0]), 0, 0 },
+	{ "mmDP0_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x1ceb, NULL, 0, 0, 0 },
+	{ "mmDP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x1ceb, &mmDP_MSA_V_TIMING_OVERRIDE2[0], sizeof(mmDP_MSA_V_TIMING_OVERRIDE2)/sizeof(mmDP_MSA_V_TIMING_OVERRIDE2[0]), 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x1cfc, NULL, 0, 0, 0 },
+	{ "mmDP_TEST_DEBUG_INDEX", REG_MMIO, 0x1cfc, &mmDP_TEST_DEBUG_INDEX[0], sizeof(mmDP_TEST_DEBUG_INDEX)/sizeof(mmDP_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDP0_DP_TEST_DEBUG_DATA", REG_MMIO, 0x1cfd, NULL, 0, 0, 0 },
+	{ "mmDP_TEST_DEBUG_DATA", REG_MMIO, 0x1cfd, &mmDP_TEST_DEBUG_DATA[0], sizeof(mmDP_TEST_DEBUG_DATA)/sizeof(mmDP_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMA_POSITION_UPPER_BASE_ADDRESS", REG_MMIO, 0x1d, &mmDMA_POSITION_UPPER_BASE_ADDRESS[0], sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS)/sizeof(mmDMA_POSITION_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_N", REG_SMC, 0x1d, &ixDP_AUX1_DEBUG_N[0], sizeof(ixDP_AUX1_DEBUG_N)/sizeof(ixDP_AUX1_DEBUG_N[0]), 0, 0 },
+	{ "mmDCP1_GRPH_ENABLE", REG_MMIO, 0x1d00, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_CONTROL", REG_MMIO, 0x1d01, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x1d02, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SWAP_CNTL", REG_MMIO, 0x1d03, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x1d04, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1d05, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PITCH", REG_MMIO, 0x1d06, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1d07, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1d08, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x1d09, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x1d0a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_START", REG_MMIO, 0x1d0b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_START", REG_MMIO, 0x1d0c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_X_END", REG_MMIO, 0x1d0d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_Y_END", REG_MMIO, 0x1d0e, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_GAMMA_CONTROL", REG_MMIO, 0x1d10, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_UPDATE", REG_MMIO, 0x1d11, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_CONTROL", REG_MMIO, 0x1d12, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1d13, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_CONTROL", REG_MMIO, 0x1d14, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_DFQ_STATUS", REG_MMIO, 0x1d15, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x1d16, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x1d17, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1d18, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x1d19, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_PITCH", REG_MMIO, 0x1d1a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1d1b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_ENABLE", REG_MMIO, 0x1d1c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_CONTROL1", REG_MMIO, 0x1d1d, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_CONTROL2", REG_MMIO, 0x1d1e, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SWAP_CNTL", REG_MMIO, 0x1d1f, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS", REG_MMIO, 0x1d20, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_PITCH", REG_MMIO, 0x1d21, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1d22, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x1d23, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x1d24, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_START", REG_MMIO, 0x1d25, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_END", REG_MMIO, 0x1d26, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_UPDATE", REG_MMIO, 0x1d27, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x1d28, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_DFQ_CONTROL", REG_MMIO, 0x1d29, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_DFQ_STATUS", REG_MMIO, 0x1d2a, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x1d2b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x1d2c, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x1d2d, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x1d2e, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x1d2f, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x1d30, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_OVL_CONTROL", REG_MMIO, 0x1d31, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x1d32, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x1d33, NULL, 0, 0, 0 },
+	{ "mmDCP1_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x1d34, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_CONTROL", REG_MMIO, 0x1d35, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C11_C12", REG_MMIO, 0x1d36, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C13_C14", REG_MMIO, 0x1d37, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C21_C22", REG_MMIO, 0x1d38, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C23_C24", REG_MMIO, 0x1d39, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C31_C32", REG_MMIO, 0x1d3a, NULL, 0, 0, 0 },
+	{ "mmDCP1_INPUT_CSC_C33_C34", REG_MMIO, 0x1d3b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_CONTROL", REG_MMIO, 0x1d3c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C11_C12", REG_MMIO, 0x1d3d, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C13_C14", REG_MMIO, 0x1d3e, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C21_C22", REG_MMIO, 0x1d3f, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C23_C24", REG_MMIO, 0x1d40, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C31_C32", REG_MMIO, 0x1d41, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUTPUT_CSC_C33_C34", REG_MMIO, 0x1d42, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x1d43, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x1d44, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x1d45, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x1d46, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x1d47, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x1d48, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x1d49, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x1d4a, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x1d4b, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x1d4c, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x1d4d, NULL, 0, 0, 0 },
+	{ "mmDCP1_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x1d4e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DENORM_CONTROL", REG_MMIO, 0x1d50, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_ROUND_CONTROL", REG_MMIO, 0x1d51, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x1d52, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_CONTROL", REG_MMIO, 0x1d53, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_ALPHA", REG_MMIO, 0x1d54, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_RED", REG_MMIO, 0x1d55, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_GREEN", REG_MMIO, 0x1d56, NULL, 0, 0, 0 },
+	{ "mmDCP1_KEY_RANGE_BLUE", REG_MMIO, 0x1d57, NULL, 0, 0, 0 },
+	{ "mmDCP1_DEGAMMA_CONTROL", REG_MMIO, 0x1d58, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_CONTROL", REG_MMIO, 0x1d59, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C11_C12", REG_MMIO, 0x1d5a, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C13_C14", REG_MMIO, 0x1d5b, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C21_C22", REG_MMIO, 0x1d5c, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C23_C24", REG_MMIO, 0x1d5d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C31_C32", REG_MMIO, 0x1d5e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GAMUT_REMAP_C33_C34", REG_MMIO, 0x1d5f, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x1d60, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_RANDOM_SEEDS", REG_MMIO, 0x1d61, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x1d65, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_CONTROL", REG_MMIO, 0x1d66, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS", REG_MMIO, 0x1d67, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SIZE", REG_MMIO, 0x1d68, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1d69, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_POSITION", REG_MMIO, 0x1d6a, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_HOT_SPOT", REG_MMIO, 0x1d6b, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR1", REG_MMIO, 0x1d6c, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_COLOR2", REG_MMIO, 0x1d6d, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_UPDATE", REG_MMIO, 0x1d6e, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_CONTROL", REG_MMIO, 0x1d6f, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_SURFACE_ADDRESS", REG_MMIO, 0x1d70, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_SIZE", REG_MMIO, 0x1d71, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1d72, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_POSITION", REG_MMIO, 0x1d73, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_HOT_SPOT", REG_MMIO, 0x1d74, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_COLOR1", REG_MMIO, 0x1d75, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_COLOR2", REG_MMIO, 0x1d76, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_UPDATE", REG_MMIO, 0x1d77, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_MODE", REG_MMIO, 0x1d78, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_RW_INDEX", REG_MMIO, 0x1d79, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_SEQ_COLOR", REG_MMIO, 0x1d7a, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_PWL_DATA", REG_MMIO, 0x1d7b, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_30_COLOR", REG_MMIO, 0x1d7c, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x1d7d, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x1d7e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_AUTOFILL", REG_MMIO, 0x1d7f, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_CONTROL", REG_MMIO, 0x1d80, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x1d81, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x1d82, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x1d83, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x1d84, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x1d85, NULL, 0, 0, 0 },
+	{ "mmDCP1_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x1d86, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CONTROL", REG_MMIO, 0x1d87, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_MASK", REG_MMIO, 0x1d88, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_CURRENT", REG_MMIO, 0x1d89, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_CRC_LAST", REG_MMIO, 0x1d8b, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG", REG_MMIO, 0x1d8d, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x1d8e, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_GSL_CONTROL", REG_MMIO, 0x1d90, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x1d91, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x1d92, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x1d93, NULL, 0, 0, 0 },
+	{ "mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1d94, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x1d95, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x1d96, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x1d97, NULL, 0, 0, 0 },
+	{ "mmDCP1_DCP_DEBUG2", REG_MMIO, 0x1d98, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x1d99, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR_STEREO_CONTROL", REG_MMIO, 0x1d9a, NULL, 0, 0, 0 },
+	{ "mmDCP1_CUR2_STEREO_CONTROL", REG_MMIO, 0x1d9b, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x1d9c, NULL, 0, 0, 0 },
+	{ "mmDCP1_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x1d9d, NULL, 0, 0, 0 },
+	{ "mmDCP1_HW_ROTATION", REG_MMIO, 0x1d9e, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x1d9f, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CONTROL", REG_MMIO, 0x1da0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_INDEX", REG_MMIO, 0x1da1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_DATA", REG_MMIO, 0x1da2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x1da3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x1da4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x1da5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x1da6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x1da7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x1da8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x1da9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x1daa, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x1dab, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x1dac, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x1dad, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x1dae, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x1daf, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x1db0, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x1db1, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x1db2, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x1db3, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x1db4, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x1db5, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x1db6, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x1db7, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x1db8, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x1db9, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x1dba, NULL, 0, 0, 0 },
+	{ "mmDCP1_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x1dbb, NULL, 0, 0, 0 },
+	{ "mmDCP1_ALPHA_CONTROL", REG_MMIO, 0x1dbc, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x1dbd, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x1dbe, NULL, 0, 0, 0 },
+	{ "mmDCP1_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x1dbf, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DATA_FORMAT", REG_MMIO, 0x1dc0, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_MEMORY_CTRL", REG_MMIO, 0x1dc1, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x1dc2, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DESKTOP_HEIGHT", REG_MMIO, 0x1dc3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE_START_END", REG_MMIO, 0x1dc4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE2_START_END", REG_MMIO, 0x1dc5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_V_COUNTER", REG_MMIO, 0x1dc6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x1dc7, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_INTERRUPT_MASK", REG_MMIO, 0x1dc8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE_STATUS", REG_MMIO, 0x1dc9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VLINE2_STATUS", REG_MMIO, 0x1dca, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_VBLANK_STATUS", REG_MMIO, 0x1dcb, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_SYNC_RESET_SEL", REG_MMIO, 0x1dcc, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x1dcd, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x1dce, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x1dcf, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x1dd0, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x1dd1, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x1dd2, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x1dd3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x1dd4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x1dd5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x1dd6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x1dd7, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x1dd8, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x1dd9, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_BUFFER_STATUS", REG_MMIO, 0x1dda, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x1ddc, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_MODE", REG_MMIO, 0x1de0, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x1de1, NULL, 0, 0, 0 },
+	{ "mmLB1_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x1de2, NULL, 0, 0, 0 },
+	{ "mmLB1_DC_MVP_LB_CONTROL", REG_MMIO, 0x1de3, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG", REG_MMIO, 0x1de4, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG2", REG_MMIO, 0x1de5, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_DEBUG3", REG_MMIO, 0x1de6, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x1dfe, NULL, 0, 0, 0 },
+	{ "mmLB1_LB_TEST_DEBUG_DATA", REG_MMIO, 0x1dff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX1_DEBUG_O", REG_SMC, 0x1e, &ixDP_AUX1_DEBUG_O[0], sizeof(ixDP_AUX1_DEBUG_O)/sizeof(ixDP_AUX1_DEBUG_O[0]), 0, 0 },
+	{ "ixCRT1E", REG_SMC, 0x1e, &ixCRT1E[0], sizeof(ixCRT1E)/sizeof(ixCRT1E[0]), 0, 0 },
+	{ "mmDC_PERFMON3_PERFCOUNTER_CNTL", REG_MMIO, 0x1e24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFCOUNTER_STATE", REG_MMIO, 0x1e25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x1e26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CNTL", REG_MMIO, 0x1e27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_CVALUE_LOW", REG_MMIO, 0x1e28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_HI", REG_MMIO, 0x1e29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_LOW", REG_MMIO, 0x1e2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x1e2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON3_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x1e2c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x1e30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x1e31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x1e32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x1e33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x1e34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x1e35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x1e36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x1e37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x1e38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x1e39, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_REPEATER_PROGRAM", REG_MMIO, 0x1e3a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_A", REG_MMIO, 0x1e3b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG1_DPG_HW_DEBUG_B", REG_MMIO, 0x1e3c, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_SELECT", REG_MMIO, 0x1e40, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x1e41, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE", REG_MMIO, 0x1e42, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TAP_CONTROL", REG_MMIO, 0x1e43, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_CONTROL", REG_MMIO, 0x1e44, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_BYPASS_CONTROL", REG_MMIO, 0x1e45, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x1e46, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x1e47, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x1e48, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x1e49, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x1e4a, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x1e4b, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x1e4c, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT", REG_MMIO, 0x1e4d, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x1e4e, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ROUND_OFFSET", REG_MMIO, 0x1e4f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_UPDATE", REG_MMIO, 0x1e51, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_F_SHARP_CONTROL", REG_MMIO, 0x1e53, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_ALU_CONTROL", REG_MMIO, 0x1e54, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x1e55, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_START", REG_MMIO, 0x1e5c, NULL, 0, 0, 0 },
+	{ "mmSCL1_VIEWPORT_SIZE", REG_MMIO, 0x1e5d, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x1e5e, NULL, 0, 0, 0 },
+	{ "mmSCL1_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x1e5f, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x1e60, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x1e61, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x1e62, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x1e63, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG2", REG_MMIO, 0x1e69, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_DEBUG", REG_MMIO, 0x1e6a, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x1e6b, NULL, 0, 0, 0 },
+	{ "mmSCL1_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x1e6c, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_CONTROL", REG_MMIO, 0x1e6d, NULL, 0, 0, 0 },
+	{ "mmBLND1_SM_CONTROL2", REG_MMIO, 0x1e6e, NULL, 0, 0, 0 },
+	{ "mmBLND1_PTI_CONTROL", REG_MMIO, 0x1e6f, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_UPDATE", REG_MMIO, 0x1e70, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x1e71, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_V_UPDATE_LOCK", REG_MMIO, 0x1e73, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_DEBUG", REG_MMIO, 0x1e74, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x1e75, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x1e76, NULL, 0, 0, 0 },
+	{ "mmBLND1_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x1e77, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x1e78, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x1e79, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_WINDOW", REG_MMIO, 0x1e7a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_GSL_CONTROL", REG_MMIO, 0x1e7b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x1e7c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x1e7d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_DCFE_DBG_SEL", REG_MMIO, 0x1e7e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x1e7f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_TOTAL", REG_MMIO, 0x1e80, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_BLANK_START_END", REG_MMIO, 0x1e81, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A", REG_MMIO, 0x1e82, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x1e83, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B", REG_MMIO, 0x1e84, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x1e85, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VBI_END", REG_MMIO, 0x1e86, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL", REG_MMIO, 0x1e87, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MIN", REG_MMIO, 0x1e88, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_MAX", REG_MMIO, 0x1e89, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x1e8a, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x1e8b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x1e8c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_BLANK_START_END", REG_MMIO, 0x1e8d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A", REG_MMIO, 0x1e8e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x1e8f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B", REG_MMIO, 0x1e90, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x1e91, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_CNTL", REG_MMIO, 0x1e92, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x1e93, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_CNTL", REG_MMIO, 0x1e94, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x1e95, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_CNTL", REG_MMIO, 0x1e96, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x1e97, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x1e98, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FLOW_CONTROL", REG_MMIO, 0x1e99, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x1e9b, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CONTROL", REG_MMIO, 0x1e9c, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_CONTROL", REG_MMIO, 0x1e9d, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x1e9e, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERLACE_STATUS", REG_MMIO, 0x1e9f, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x1ea0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x1ea1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x1ea2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS", REG_MMIO, 0x1ea3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_POSITION", REG_MMIO, 0x1ea4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x1ea5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x1ea6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x1ea7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x1ea8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_CONTROL", REG_MMIO, 0x1ea9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_COUNT_RESET", REG_MMIO, 0x1eaa, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x1eab, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x1eac, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_STATUS", REG_MMIO, 0x1ead, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STEREO_CONTROL", REG_MMIO, 0x1eae, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x1eaf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x1eb0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x1eb1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x1eb2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_START_LINE_CONTROL", REG_MMIO, 0x1eb3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x1eb4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_UPDATE_LOCK", REG_MMIO, 0x1eb5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x1eb6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x1eb7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x1eba, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x1ebb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x1ebc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_MASTER_UPDATE_LOCK", REG_MMIO, 0x1ebd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_MASTER_UPDATE_MODE", REG_MMIO, 0x1ebe, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x1ebf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x1ec0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MVP_STATUS", REG_MMIO, 0x1ec1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_MASTER_EN", REG_MMIO, 0x1ec2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x1ec3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x1ec4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x1ec6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x1ec7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x1ec8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x1ec9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x1eca, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x1ecb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR", REG_MMIO, 0x1ecc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x1ecd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x1ece, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x1ecf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x1ed0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x1ed1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x1ed2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x1ed3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC_CNTL", REG_MMIO, 0x1ed4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x1ed5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x1ed6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x1ed7, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x1ed8, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_DATA_RG", REG_MMIO, 0x1ed9, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC0_DATA_B", REG_MMIO, 0x1eda, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x1edb, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x1edc, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x1edd, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x1ede, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_DATA_RG", REG_MMIO, 0x1edf, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_CRC1_DATA_B", REG_MMIO, 0x1ee0, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x1ee1, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x1ee2, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x1ee3, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x1ee4, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x1ee5, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x1ee6, NULL, 0, 0, 0 },
+	{ "mmCRTC1_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x1ee7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x1ee8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x1ee9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x1eea, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x1eeb, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x1eec, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x1eed, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CONTROL", REG_MMIO, 0x1eee, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x1eef, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_DATA_0_1", REG_MMIO, 0x1ef0, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_FORCE_DATA_2_3", REG_MMIO, 0x1ef1, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x1ef2, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x1ef3, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x1ef4, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x1ef5, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x1ef6, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x1ef7, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x1ef8, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CLAMP_CNTL", REG_MMIO, 0x1ef9, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_CNTL", REG_MMIO, 0x1efa, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x1efb, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x1efc, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x1efd, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x1efe, NULL, 0, 0, 0 },
+	{ "mmFMT1_FMT_DEBUG_CNTL", REG_MMIO, 0x1eff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX1_DEBUG_P", REG_SMC, 0x1f, &ixDP_AUX1_DEBUG_P[0], sizeof(ixDP_AUX1_DEBUG_P)/sizeof(ixDP_AUX1_DEBUG_P[0]), 0, 0 },
+	{ "ixCRT1F", REG_SMC, 0x1f, &ixCRT1F[0], sizeof(ixCRT1F)/sizeof(ixCRT1F[0]), 0, 0 },
+	{ "mmDIG1_DIG_FE_CNTL", REG_MMIO, 0x1f00, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x1f01, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x1f02, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_CLOCK_PATTERN", REG_MMIO, 0x1f03, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0x1f04, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "mmDIG1_DIG_TEST_PATTERN", REG_MMIO, 0x1f04, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE", REG_SMC, 0x1f05, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE[0]), 0, 0 },
+	{ "mmDIG1_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x1f05, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x1f08, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x1f09, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x1f0a, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmDIG1_DIG_FIFO_STATUS", REG_MMIO, 0x1f0a, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS", REG_SMC, 0x1f0b, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmDIG1_HDMI_CONTROL", REG_MMIO, 0x1f0c, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_STATUS", REG_MMIO, 0x1f0d, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1f0e, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES", REG_SMC, 0x1f0f, &ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0], sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES)/sizeof(ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES[0]), 0, 0 },
+	{ "mmDIG1_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x1f0f, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x1f10, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x1f11, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x1f12, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x1f13, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x1f14, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GC", REG_MMIO, 0x1f16, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x1f17, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_0", REG_MMIO, 0x1f18, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_1", REG_MMIO, 0x1f19, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_2", REG_MMIO, 0x1f1a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_3", REG_MMIO, 0x1f1b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC1_4", REG_MMIO, 0x1f1c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_0", REG_MMIO, 0x1f1d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_1", REG_MMIO, 0x1f1e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_2", REG_MMIO, 0x1f1f, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_ISRC2_3", REG_MMIO, 0x1f20, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO0", REG_MMIO, 0x1f21, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO1", REG_MMIO, 0x1f22, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO2", REG_MMIO, 0x1f23, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AVI_INFO3", REG_MMIO, 0x1f24, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO0", REG_MMIO, 0x1f25, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_MPEG_INFO1", REG_MMIO, 0x1f26, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_HDR", REG_MMIO, 0x1f27, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_0", REG_MMIO, 0x1f28, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_1", REG_MMIO, 0x1f29, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_2", REG_MMIO, 0x1f2a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_3", REG_MMIO, 0x1f2b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_4", REG_MMIO, 0x1f2c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_5", REG_MMIO, 0x1f2d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_6", REG_MMIO, 0x1f2e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_GENERIC_7", REG_MMIO, 0x1f2f, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x1f30, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_0", REG_MMIO, 0x1f37, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_32_1", REG_MMIO, 0x1f38, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_0", REG_MMIO, 0x1f39, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_44_1", REG_MMIO, 0x1f3a, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_0", REG_MMIO, 0x1f3b, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_48_1", REG_MMIO, 0x1f3c, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_0", REG_MMIO, 0x1f3d, NULL, 0, 0, 0 },
+	{ "mmDIG1_HDMI_ACR_STATUS_1", REG_MMIO, 0x1f3e, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO0", REG_MMIO, 0x1f3f, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_INFO1", REG_MMIO, 0x1f40, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_0", REG_MMIO, 0x1f41, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_1", REG_MMIO, 0x1f42, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x1f43, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL0", REG_MMIO, 0x1f44, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL1", REG_MMIO, 0x1f45, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL2", REG_MMIO, 0x1f46, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_RAMP_CONTROL3", REG_MMIO, 0x1f47, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_60958_2", REG_MMIO, 0x1f48, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x1f49, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_STATUS", REG_MMIO, 0x1f4a, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x1f4b, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x1f4c, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x1f4d, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x1f4f, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_CNTL", REG_MMIO, 0x1f50, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_BE_EN_CNTL", REG_MMIO, 0x1f51, NULL, 0, 0, 0 },
+	{ "mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x1f52, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CNTL", REG_MMIO, 0x1f7c, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL_CHAR", REG_MMIO, 0x1f7d, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x1f7e, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x1f7f, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x1f80, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x1f81, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DEBUG", REG_MMIO, 0x1f82, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL_BITS", REG_MMIO, 0x1f83, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x1f84, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x1f86, NULL, 0, 0, 0 },
+	{ "mmDIG1_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x1f87, NULL, 0, 0, 0 },
+	{ "mmDIG1_LVDS_DATA_CNTL", REG_MMIO, 0x1f8c, NULL, 0, 0, 0 },
+	{ "mmDIG1_DIG_LANE_ENABLE", REG_MMIO, 0x1f8d, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL", REG_MMIO, 0x1fa0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING1", REG_MMIO, 0x1fa1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING2", REG_MMIO, 0x1fa2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING3", REG_MMIO, 0x1fa3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_FRAMING4", REG_MMIO, 0x1fa4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N", REG_MMIO, 0x1fa5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x1fa6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M", REG_MMIO, 0x1fa7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x1fa8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_TIMESTAMP", REG_MMIO, 0x1fa9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_PACKET_CNTL", REG_MMIO, 0x1faa, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_SEC_CNTL1", REG_MMIO, 0x1fab, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_CNTL", REG_MMIO, 0x1fc0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_PIXEL_FORMAT", REG_MMIO, 0x1fc1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_CONFIG", REG_MMIO, 0x1fc2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_STREAM_CNTL", REG_MMIO, 0x1fc3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_STEER_FIFO", REG_MMIO, 0x1fc4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_MISC", REG_MMIO, 0x1fc5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x1fc6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x1fc7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x1fc8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_TIMING", REG_MMIO, 0x1fc9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_N", REG_MMIO, 0x1fca, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_M", REG_MMIO, 0x1fcb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x1fcc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_MSA_VBID", REG_MMIO, 0x1fcd, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x1fce, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x1fcf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CNTL", REG_MMIO, 0x1fd0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x1fd1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM0", REG_MMIO, 0x1fd2, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x1fd3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x1fd4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x1fd5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_EN", REG_MMIO, 0x1fd6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_CNTL", REG_MMIO, 0x1fd7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_CRC_RESULT", REG_MMIO, 0x1fd8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_COLORIMETRY", REG_MMIO, 0x1fda, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_MISC_CNTL", REG_MMIO, 0x1fdb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM2", REG_MMIO, 0x1fdf, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_SYM1", REG_MMIO, 0x1fe0, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_CNTL", REG_MMIO, 0x1fe1, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_RATE_UPDATE", REG_MMIO, 0x1fe3, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT0", REG_MMIO, 0x1fe4, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT1", REG_MMIO, 0x1fe5, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT2", REG_MMIO, 0x1fe6, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_SAT_UPDATE", REG_MMIO, 0x1fe7, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSE_LINK_TIMING", REG_MMIO, 0x1fe8, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x1fe9, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x1fea, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x1feb, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x1ffc, NULL, 0, 0, 0 },
+	{ "mmDP1_DP_TEST_DEBUG_DATA", REG_MMIO, 0x1ffd, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN", REG_SMC, 0x2, &ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN[0]), 0, 0 },
+	{ "ixAZALIA_WORSTCASE_LATENCY_COUNT", REG_SMC, 0x2, &ixAZALIA_WORSTCASE_LATENCY_COUNT[0], sizeof(ixAZALIA_WORSTCASE_LATENCY_COUNT)/sizeof(ixAZALIA_WORSTCASE_LATENCY_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL2", REG_SMC, 0x2, &ixAZALIA_CRC0_CHANNEL2[0], sizeof(ixAZALIA_CRC0_CHANNEL2)/sizeof(ixAZALIA_CRC0_CHANNEL2[0]), 0, 0 },
+	{ "ixDMIF_DEBUG02_CORE0", REG_SMC, 0x2, &ixDMIF_DEBUG02_CORE0[0], sizeof(ixDMIF_DEBUG02_CORE0)/sizeof(ixDMIF_DEBUG02_CORE0[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR1", REG_SMC, 0x2, &ixAUDIO_DESCRIPTOR1[0], sizeof(ixAUDIO_DESCRIPTOR1)/sizeof(ixAUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "mmGLOBAL_CONTROL", REG_MMIO, 0x2, &mmGLOBAL_CONTROL[0], sizeof(mmGLOBAL_CONTROL)/sizeof(mmGLOBAL_CONTROL[0]), 0, 0 },
+	{ "ixDCIO_DEBUG2", REG_SMC, 0x2, &ixDCIO_DEBUG2[0], sizeof(ixDCIO_DEBUG2)/sizeof(ixDCIO_DEBUG2[0]), 0, 0 },
+	{ "ixFMT_DEBUG1", REG_SMC, 0x2, &ixFMT_DEBUG1[0], sizeof(ixFMT_DEBUG1)/sizeof(ixFMT_DEBUG1[0]), 0, 0 },
+	{ "ixATTR02", REG_SMC, 0x2, &ixATTR02[0], sizeof(ixATTR02)/sizeof(ixATTR02[0]), 0, 0 },
+	{ "ixSEQ02", REG_SMC, 0x2, &ixSEQ02[0], sizeof(ixSEQ02)/sizeof(ixSEQ02[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x20, &ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS", REG_MMIO, 0x20, &mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_A", REG_SMC, 0x20, &ixDP_AUX2_DEBUG_A[0], sizeof(ixDP_AUX2_DEBUG_A)/sizeof(ixDP_AUX2_DEBUG_A[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER", REG_MMIO, 0x21, &mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x21, &ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_B", REG_SMC, 0x21, &ixDP_AUX2_DEBUG_B[0], sizeof(ixDP_AUX2_DEBUG_B)/sizeof(ixDP_AUX2_DEBUG_B[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x22, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH", REG_MMIO, 0x22, &mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_C", REG_SMC, 0x22, &ixDP_AUX2_DEBUG_C[0], sizeof(ixDP_AUX2_DEBUG_C)/sizeof(ixDP_AUX2_DEBUG_C[0]), 0, 0 },
+	{ "ixCRT22", REG_SMC, 0x22, &ixCRT22[0], sizeof(ixCRT22)/sizeof(ixCRT22[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT", REG_SMC, 0x2200, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x23, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX", REG_MMIO, 0x23, &mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_D", REG_SMC, 0x23, &ixDP_AUX2_DEBUG_D[0], sizeof(ixDP_AUX2_DEBUG_D)/sizeof(ixDP_AUX2_DEBUG_D[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x24, &ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE", REG_MMIO, 0x24, &mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_FORMAT", REG_MMIO, 0x24, &mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FORMAT)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_FORMAT[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_E", REG_SMC, 0x24, &ixDP_AUX2_DEBUG_E[0], sizeof(ixDP_AUX2_DEBUG_E)/sizeof(ixDP_AUX2_DEBUG_E[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER", REG_SMC, 0x25, &ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_F", REG_SMC, 0x25, &ixDP_AUX2_DEBUG_F[0], sizeof(ixDP_AUX2_DEBUG_F)/sizeof(ixDP_AUX2_DEBUG_F[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS", REG_MMIO, 0x26, &mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_G", REG_SMC, 0x26, &ixDP_AUX2_DEBUG_G[0], sizeof(ixDP_AUX2_DEBUG_G)/sizeof(ixDP_AUX2_DEBUG_G[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS", REG_MMIO, 0x27, &mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_H", REG_SMC, 0x27, &ixDP_AUX2_DEBUG_H[0], sizeof(ixDP_AUX2_DEBUG_H)/sizeof(ixDP_AUX2_DEBUG_H[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x2706, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x270d, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2", REG_SMC, 0x270e, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x2724, &ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3", REG_SMC, 0x273e, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x2770, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x2771, &ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0", REG_SMC, 0x28, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_I", REG_SMC, 0x28, &ixDP_AUX2_DEBUG_I[0], sizeof(ixDP_AUX2_DEBUG_I)/sizeof(ixDP_AUX2_DEBUG_I[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1", REG_SMC, 0x29, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_J", REG_SMC, 0x29, &ixDP_AUX2_DEBUG_J[0], sizeof(ixDP_AUX2_DEBUG_J)/sizeof(ixDP_AUX2_DEBUG_J[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2", REG_SMC, 0x2a, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_K", REG_SMC, 0x2a, &ixDP_AUX2_DEBUG_K[0], sizeof(ixDP_AUX2_DEBUG_K)/sizeof(ixDP_AUX2_DEBUG_K[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3", REG_SMC, 0x2b, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_L", REG_SMC, 0x2b, &ixDP_AUX2_DEBUG_L[0], sizeof(ixDP_AUX2_DEBUG_L)/sizeof(ixDP_AUX2_DEBUG_L[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4", REG_SMC, 0x2c, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_M", REG_SMC, 0x2c, &ixDP_AUX2_DEBUG_M[0], sizeof(ixDP_AUX2_DEBUG_M)/sizeof(ixDP_AUX2_DEBUG_M[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5", REG_SMC, 0x2d, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_N", REG_SMC, 0x2d, &ixDP_AUX2_DEBUG_N[0], sizeof(ixDP_AUX2_DEBUG_N)/sizeof(ixDP_AUX2_DEBUG_N[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6", REG_SMC, 0x2e, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_O", REG_SMC, 0x2e, &ixDP_AUX2_DEBUG_O[0], sizeof(ixDP_AUX2_DEBUG_O)/sizeof(ixDP_AUX2_DEBUG_O[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7", REG_SMC, 0x2f, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_P", REG_SMC, 0x2f, &ixDP_AUX2_DEBUG_P[0], sizeof(ixDP_AUX2_DEBUG_P)/sizeof(ixDP_AUX2_DEBUG_P[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x2f09, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x2f0a, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x2f0b, &ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CONFIG", REG_MMIO, 0x2f5, &mmDMIF_ADDR_CONFIG[0], sizeof(mmDMIF_ADDR_CONFIG)/sizeof(mmDMIF_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmDMIF_CONTROL", REG_MMIO, 0x2f6, &mmDMIF_CONTROL[0], sizeof(mmDMIF_CONTROL)/sizeof(mmDMIF_CONTROL[0]), 0, 0 },
+	{ "mmDMIF_STATUS", REG_MMIO, 0x2f7, &mmDMIF_STATUS[0], sizeof(mmDMIF_STATUS)/sizeof(mmDMIF_STATUS[0]), 0, 0 },
+	{ "mmDMIF_HW_DEBUG", REG_MMIO, 0x2f8, &mmDMIF_HW_DEBUG[0], sizeof(mmDMIF_HW_DEBUG)/sizeof(mmDMIF_HW_DEBUG[0]), 0, 0 },
+	{ "mmDMIF_ARBITRATION_CONTROL", REG_MMIO, 0x2f9, &mmDMIF_ARBITRATION_CONTROL[0], sizeof(mmDMIF_ARBITRATION_CONTROL)/sizeof(mmDMIF_ARBITRATION_CONTROL[0]), 0, 0 },
+	{ "mmPIPE0_ARBITRATION_CONTROL3", REG_MMIO, 0x2fa, &mmPIPE0_ARBITRATION_CONTROL3[0], sizeof(mmPIPE0_ARBITRATION_CONTROL3)/sizeof(mmPIPE0_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE1_ARBITRATION_CONTROL3", REG_MMIO, 0x2fb, &mmPIPE1_ARBITRATION_CONTROL3[0], sizeof(mmPIPE1_ARBITRATION_CONTROL3)/sizeof(mmPIPE1_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE2_ARBITRATION_CONTROL3", REG_MMIO, 0x2fc, &mmPIPE2_ARBITRATION_CONTROL3[0], sizeof(mmPIPE2_ARBITRATION_CONTROL3)/sizeof(mmPIPE2_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE3_ARBITRATION_CONTROL3", REG_MMIO, 0x2fd, &mmPIPE3_ARBITRATION_CONTROL3[0], sizeof(mmPIPE3_ARBITRATION_CONTROL3)/sizeof(mmPIPE3_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE4_ARBITRATION_CONTROL3", REG_MMIO, 0x2fe, &mmPIPE4_ARBITRATION_CONTROL3[0], sizeof(mmPIPE4_ARBITRATION_CONTROL3)/sizeof(mmPIPE4_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "mmPIPE5_ARBITRATION_CONTROL3", REG_MMIO, 0x2ff, &mmPIPE5_ARBITRATION_CONTROL3[0], sizeof(mmPIPE5_ARBITRATION_CONTROL3)/sizeof(mmPIPE5_ARBITRATION_CONTROL3[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID", REG_SMC, 0x3, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0", REG_SMC, 0x3, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0[0]), 0, 0 },
+	{ "ixAZALIA_CUMULATIVE_LATENCY_COUNT", REG_SMC, 0x3, &ixAZALIA_CUMULATIVE_LATENCY_COUNT[0], sizeof(ixAZALIA_CUMULATIVE_LATENCY_COUNT)/sizeof(ixAZALIA_CUMULATIVE_LATENCY_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL3", REG_SMC, 0x3, &ixAZALIA_CRC0_CHANNEL3[0], sizeof(ixAZALIA_CRC0_CHANNEL3)/sizeof(ixAZALIA_CRC0_CHANNEL3[0]), 0, 0 },
+	{ "mmSTATE_CHANGE_STATUS", REG_MMIO, 0x3, &mmSTATE_CHANGE_STATUS[0], sizeof(mmSTATE_CHANGE_STATUS)/sizeof(mmSTATE_CHANGE_STATUS[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR2", REG_SMC, 0x3, &ixAUDIO_DESCRIPTOR2[0], sizeof(ixAUDIO_DESCRIPTOR2)/sizeof(ixAUDIO_DESCRIPTOR2[0]), 0, 0 },
+	{ "ixDCIO_DEBUG3", REG_SMC, 0x3, &ixDCIO_DEBUG3[0], sizeof(ixDCIO_DEBUG3)/sizeof(ixDCIO_DEBUG3[0]), 0, 0 },
+	{ "ixFMT_DEBUG2", REG_SMC, 0x3, &ixFMT_DEBUG2[0], sizeof(ixFMT_DEBUG2)/sizeof(ixFMT_DEBUG2[0]), 0, 0 },
+	{ "ixATTR03", REG_SMC, 0x3, &ixATTR03[0], sizeof(ixATTR03)/sizeof(ixATTR03[0]), 0, 0 },
+	{ "ixSEQ03", REG_SMC, 0x3, &ixSEQ03[0], sizeof(ixSEQ03)/sizeof(ixSEQ03[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8", REG_SMC, 0x30, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_A", REG_SMC, 0x30, &ixDP_AUX3_DEBUG_A[0], sizeof(ixDP_AUX3_DEBUG_A)/sizeof(ixDP_AUX3_DEBUG_A[0]), 0, 0 },
+	{ "mmDMIF_ADDR_CALC", REG_MMIO, 0x300, &mmDMIF_ADDR_CALC[0], sizeof(mmDMIF_ADDR_CALC)/sizeof(mmDMIF_ADDR_CALC[0]), 0, 0 },
+	{ "mmDMIF_STATUS2", REG_MMIO, 0x301, &mmDMIF_STATUS2[0], sizeof(mmDMIF_STATUS2)/sizeof(mmDMIF_STATUS2[0]), 0, 0 },
+	{ "mmPIPE0_MAX_REQUESTS", REG_MMIO, 0x302, &mmPIPE0_MAX_REQUESTS[0], sizeof(mmPIPE0_MAX_REQUESTS)/sizeof(mmPIPE0_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE1_MAX_REQUESTS", REG_MMIO, 0x303, &mmPIPE1_MAX_REQUESTS[0], sizeof(mmPIPE1_MAX_REQUESTS)/sizeof(mmPIPE1_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE2_MAX_REQUESTS", REG_MMIO, 0x304, &mmPIPE2_MAX_REQUESTS[0], sizeof(mmPIPE2_MAX_REQUESTS)/sizeof(mmPIPE2_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE3_MAX_REQUESTS", REG_MMIO, 0x305, &mmPIPE3_MAX_REQUESTS[0], sizeof(mmPIPE3_MAX_REQUESTS)/sizeof(mmPIPE3_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE4_MAX_REQUESTS", REG_MMIO, 0x306, &mmPIPE4_MAX_REQUESTS[0], sizeof(mmPIPE4_MAX_REQUESTS)/sizeof(mmPIPE4_MAX_REQUESTS[0]), 0, 0 },
+	{ "mmPIPE5_MAX_REQUESTS", REG_MMIO, 0x307, &mmPIPE5_MAX_REQUESTS[0], sizeof(mmPIPE5_MAX_REQUESTS)/sizeof(mmPIPE5_MAX_REQUESTS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9", REG_SMC, 0x31, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_B", REG_SMC, 0x31, &ixDP_AUX3_DEBUG_B[0], sizeof(ixDP_AUX3_DEBUG_B)/sizeof(ixDP_AUX3_DEBUG_B[0]), 0, 0 },
+	{ "mmDC_RBBMIF_RDWR_CNTL3", REG_MMIO, 0x311, &mmDC_RBBMIF_RDWR_CNTL3[0], sizeof(mmDC_RBBMIF_RDWR_CNTL3)/sizeof(mmDC_RBBMIF_RDWR_CNTL3[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_INDEX", REG_MMIO, 0x312, &mmDMIF_TEST_DEBUG_INDEX[0], sizeof(mmDMIF_TEST_DEBUG_INDEX)/sizeof(mmDMIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDMIF_TEST_DEBUG_DATA", REG_MMIO, 0x313, &mmDMIF_TEST_DEBUG_DATA[0], sizeof(mmDMIF_TEST_DEBUG_DATA)/sizeof(mmDMIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMCIF_CONTROL", REG_MMIO, 0x314, &mmMCIF_CONTROL[0], sizeof(mmMCIF_CONTROL)/sizeof(mmMCIF_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WRITE_COMBINE_CONTROL", REG_MMIO, 0x315, &mmMCIF_WRITE_COMBINE_CONTROL[0], sizeof(mmMCIF_WRITE_COMBINE_CONTROL)/sizeof(mmMCIF_WRITE_COMBINE_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_INDEX", REG_MMIO, 0x316, &mmMCIF_TEST_DEBUG_INDEX[0], sizeof(mmMCIF_TEST_DEBUG_INDEX)/sizeof(mmMCIF_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMCIF_TEST_DEBUG_DATA", REG_MMIO, 0x317, &mmMCIF_TEST_DEBUG_DATA[0], sizeof(mmMCIF_TEST_DEBUG_DATA)/sizeof(mmMCIF_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMCIF_VMID", REG_MMIO, 0x318, &mmMCIF_VMID[0], sizeof(mmMCIF_VMID)/sizeof(mmMCIF_VMID[0]), 0, 0 },
+	{ "mmMCIF_MEM_CONTROL", REG_MMIO, 0x319, &mmMCIF_MEM_CONTROL[0], sizeof(mmMCIF_MEM_CONTROL)/sizeof(mmMCIF_MEM_CONTROL[0]), 0, 0 },
+	{ "mmDC_RBBMIF_RDWR_CNTL1", REG_MMIO, 0x31a, &mmDC_RBBMIF_RDWR_CNTL1[0], sizeof(mmDC_RBBMIF_RDWR_CNTL1)/sizeof(mmDC_RBBMIF_RDWR_CNTL1[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATE", REG_MMIO, 0x31b, &mmDCI_MEM_PWR_STATE[0], sizeof(mmDCI_MEM_PWR_STATE)/sizeof(mmDCI_MEM_PWR_STATE[0]), 0, 0 },
+	{ "mmMC_DC_INTERFACE_NACK_STATUS", REG_MMIO, 0x31c, &mmMC_DC_INTERFACE_NACK_STATUS[0], sizeof(mmMC_DC_INTERFACE_NACK_STATUS)/sizeof(mmMC_DC_INTERFACE_NACK_STATUS[0]), 0, 0 },
+	{ "mmDC_RBBMIF_RDWR_CNTL2", REG_MMIO, 0x31d, &mmDC_RBBMIF_RDWR_CNTL2[0], sizeof(mmDC_RBBMIF_RDWR_CNTL2)/sizeof(mmDC_RBBMIF_RDWR_CNTL2[0]), 0, 0 },
+	{ "mmDCI_CLK_CNTL", REG_MMIO, 0x31e, &mmDCI_CLK_CNTL[0], sizeof(mmDCI_CLK_CNTL)/sizeof(mmDCI_CLK_CNTL[0]), 0, 0 },
+	{ "mmDCCG_VPCLK_CNTL", REG_MMIO, 0x31f, &mmDCCG_VPCLK_CNTL[0], sizeof(mmDCCG_VPCLK_CNTL)/sizeof(mmDCCG_VPCLK_CNTL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10", REG_SMC, 0x32, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_C", REG_SMC, 0x32, &ixDP_AUX3_DEBUG_C[0], sizeof(ixDP_AUX3_DEBUG_C)/sizeof(ixDP_AUX3_DEBUG_C[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_INDEX", REG_MMIO, 0x320, &mmDCI_TEST_DEBUG_INDEX[0], sizeof(mmDCI_TEST_DEBUG_INDEX)/sizeof(mmDCI_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDCI_TEST_DEBUG_DATA", REG_MMIO, 0x321, &mmDCI_TEST_DEBUG_DATA[0], sizeof(mmDCI_TEST_DEBUG_DATA)/sizeof(mmDCI_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_STATE2", REG_MMIO, 0x322, &mmDCI_MEM_PWR_STATE2[0], sizeof(mmDCI_MEM_PWR_STATE2)/sizeof(mmDCI_MEM_PWR_STATE2[0]), 0, 0 },
+	{ "mmDCI_DEBUG_CONFIG", REG_MMIO, 0x323, &mmDCI_DEBUG_CONFIG[0], sizeof(mmDCI_DEBUG_CONFIG)/sizeof(mmDCI_DEBUG_CONFIG[0]), 0, 0 },
+	{ "mmLOW_POWER_TILING_CONTROL", REG_MMIO, 0x325, &mmLOW_POWER_TILING_CONTROL[0], sizeof(mmLOW_POWER_TILING_CONTROL)/sizeof(mmLOW_POWER_TILING_CONTROL[0]), 0, 0 },
+	{ "mmDCI_MEM_PWR_CNTL", REG_MMIO, 0x326, &mmDCI_MEM_PWR_CNTL[0], sizeof(mmDCI_MEM_PWR_CNTL)/sizeof(mmDCI_MEM_PWR_CNTL[0]), 0, 0 },
+	{ "mmDC_XDMA_INTERFACE_CNTL", REG_MMIO, 0x327, &mmDC_XDMA_INTERFACE_CNTL[0], sizeof(mmDC_XDMA_INTERFACE_CNTL)/sizeof(mmDC_XDMA_INTERFACE_CNTL[0]), 0, 0 },
+	{ "mmPIPE0_DMIF_BUFFER_CONTROL", REG_MMIO, 0x328, &mmPIPE0_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE0_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE0_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11", REG_SMC, 0x33, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_D", REG_SMC, 0x33, &ixDP_AUX3_DEBUG_D[0], sizeof(ixDP_AUX3_DEBUG_D)/sizeof(ixDP_AUX3_DEBUG_D[0]), 0, 0 },
+	{ "mmPIPE1_DMIF_BUFFER_CONTROL", REG_MMIO, 0x330, &mmPIPE1_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE1_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE1_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE2_DMIF_BUFFER_CONTROL", REG_MMIO, 0x338, &mmPIPE2_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE2_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE2_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12", REG_SMC, 0x34, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_E", REG_SMC, 0x34, &ixDP_AUX3_DEBUG_E[0], sizeof(ixDP_AUX3_DEBUG_E)/sizeof(ixDP_AUX3_DEBUG_E[0]), 0, 0 },
+	{ "mmPIPE3_DMIF_BUFFER_CONTROL", REG_MMIO, 0x340, &mmPIPE3_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE3_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE3_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmPIPE4_DMIF_BUFFER_CONTROL", REG_MMIO, 0x348, &mmPIPE4_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE4_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE4_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13", REG_SMC, 0x35, &ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_F", REG_SMC, 0x35, &ixDP_AUX3_DEBUG_F[0], sizeof(ixDP_AUX3_DEBUG_F)/sizeof(ixDP_AUX3_DEBUG_F[0]), 0, 0 },
+	{ "mmPIPE5_DMIF_BUFFER_CONTROL", REG_MMIO, 0x350, &mmPIPE5_DMIF_BUFFER_CONTROL[0], sizeof(mmPIPE5_DMIF_BUFFER_CONTROL)/sizeof(mmPIPE5_DMIF_BUFFER_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_BUFMGR_SW_CONTROL", REG_MMIO, 0x358, &mmMCIF_BUFMGR_SW_CONTROL[0], sizeof(mmMCIF_BUFMGR_SW_CONTROL)/sizeof(mmMCIF_BUFMGR_SW_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_BUFMGR_STATUS", REG_MMIO, 0x35a, &mmMCIF_BUFMGR_STATUS[0], sizeof(mmMCIF_BUFMGR_STATUS)/sizeof(mmMCIF_BUFMGR_STATUS[0]), 0, 0 },
+	{ "mmMCIF_BUF_PITCH", REG_MMIO, 0x35b, &mmMCIF_BUF_PITCH[0], sizeof(mmMCIF_BUF_PITCH)/sizeof(mmMCIF_BUF_PITCH[0]), 0, 0 },
+	{ "mmMCIF_BUF_1_ADDR_Y_LOW", REG_MMIO, 0x35c, &mmMCIF_BUF_1_ADDR_Y_LOW[0], sizeof(mmMCIF_BUF_1_ADDR_Y_LOW)/sizeof(mmMCIF_BUF_1_ADDR_Y_LOW[0]), 0, 0 },
+	{ "mmMCIF_BUF_1_ADDR_UP", REG_MMIO, 0x35d, &mmMCIF_BUF_1_ADDR_UP[0], sizeof(mmMCIF_BUF_1_ADDR_UP)/sizeof(mmMCIF_BUF_1_ADDR_UP[0]), 0, 0 },
+	{ "mmMCIF_BUF_1_ADDR_C_LOW", REG_MMIO, 0x35e, &mmMCIF_BUF_1_ADDR_C_LOW[0], sizeof(mmMCIF_BUF_1_ADDR_C_LOW)/sizeof(mmMCIF_BUF_1_ADDR_C_LOW[0]), 0, 0 },
+	{ "mmMCIF_BUF_1_STATUS", REG_MMIO, 0x35f, &mmMCIF_BUF_1_STATUS[0], sizeof(mmMCIF_BUF_1_STATUS)/sizeof(mmMCIF_BUF_1_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE", REG_SMC, 0x36, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_G", REG_SMC, 0x36, &ixDP_AUX3_DEBUG_G[0], sizeof(ixDP_AUX3_DEBUG_G)/sizeof(ixDP_AUX3_DEBUG_G[0]), 0, 0 },
+	{ "mmMCIF_BUF_2_ADDR_Y_LOW", REG_MMIO, 0x360, &mmMCIF_BUF_2_ADDR_Y_LOW[0], sizeof(mmMCIF_BUF_2_ADDR_Y_LOW)/sizeof(mmMCIF_BUF_2_ADDR_Y_LOW[0]), 0, 0 },
+	{ "mmMCIF_BUF_2_ADDR_UP", REG_MMIO, 0x361, &mmMCIF_BUF_2_ADDR_UP[0], sizeof(mmMCIF_BUF_2_ADDR_UP)/sizeof(mmMCIF_BUF_2_ADDR_UP[0]), 0, 0 },
+	{ "mmMCIF_BUF_2_ADDR_C_LOW", REG_MMIO, 0x362, &mmMCIF_BUF_2_ADDR_C_LOW[0], sizeof(mmMCIF_BUF_2_ADDR_C_LOW)/sizeof(mmMCIF_BUF_2_ADDR_C_LOW[0]), 0, 0 },
+	{ "mmMCIF_BUF_2_STATUS", REG_MMIO, 0x363, &mmMCIF_BUF_2_STATUS[0], sizeof(mmMCIF_BUF_2_STATUS)/sizeof(mmMCIF_BUF_2_STATUS[0]), 0, 0 },
+	{ "mmMCIF_BUF_3_ADDR_Y_LOW", REG_MMIO, 0x364, &mmMCIF_BUF_3_ADDR_Y_LOW[0], sizeof(mmMCIF_BUF_3_ADDR_Y_LOW)/sizeof(mmMCIF_BUF_3_ADDR_Y_LOW[0]), 0, 0 },
+	{ "mmMCIF_BUF_3_ADDR_UP", REG_MMIO, 0x365, &mmMCIF_BUF_3_ADDR_UP[0], sizeof(mmMCIF_BUF_3_ADDR_UP)/sizeof(mmMCIF_BUF_3_ADDR_UP[0]), 0, 0 },
+	{ "mmMCIF_BUF_3_ADDR_C_LOW", REG_MMIO, 0x366, &mmMCIF_BUF_3_ADDR_C_LOW[0], sizeof(mmMCIF_BUF_3_ADDR_C_LOW)/sizeof(mmMCIF_BUF_3_ADDR_C_LOW[0]), 0, 0 },
+	{ "mmMCIF_BUF_3_STATUS", REG_MMIO, 0x367, &mmMCIF_BUF_3_STATUS[0], sizeof(mmMCIF_BUF_3_STATUS)/sizeof(mmMCIF_BUF_3_STATUS[0]), 0, 0 },
+	{ "mmMCIF_BUF_4_ADDR_Y_LOW", REG_MMIO, 0x368, &mmMCIF_BUF_4_ADDR_Y_LOW[0], sizeof(mmMCIF_BUF_4_ADDR_Y_LOW)/sizeof(mmMCIF_BUF_4_ADDR_Y_LOW[0]), 0, 0 },
+	{ "mmMCIF_BUF_4_ADDR_UP", REG_MMIO, 0x369, &mmMCIF_BUF_4_ADDR_UP[0], sizeof(mmMCIF_BUF_4_ADDR_UP)/sizeof(mmMCIF_BUF_4_ADDR_UP[0]), 0, 0 },
+	{ "mmMCIF_BUF_4_ADDR_C_LOW", REG_MMIO, 0x36a, &mmMCIF_BUF_4_ADDR_C_LOW[0], sizeof(mmMCIF_BUF_4_ADDR_C_LOW)/sizeof(mmMCIF_BUF_4_ADDR_C_LOW[0]), 0, 0 },
+	{ "mmMCIF_BUF_4_STATUS", REG_MMIO, 0x36b, &mmMCIF_BUF_4_STATUS[0], sizeof(mmMCIF_BUF_4_STATUS)/sizeof(mmMCIF_BUF_4_STATUS[0]), 0, 0 },
+	{ "mmMCIF_SI_ARBITRATION_CONTROL", REG_MMIO, 0x36c, &mmMCIF_SI_ARBITRATION_CONTROL[0], sizeof(mmMCIF_SI_ARBITRATION_CONTROL)/sizeof(mmMCIF_SI_ARBITRATION_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_URGENCY_WATERMARK", REG_MMIO, 0x36d, &mmMCIF_URGENCY_WATERMARK[0], sizeof(mmMCIF_URGENCY_WATERMARK)/sizeof(mmMCIF_URGENCY_WATERMARK[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC", REG_SMC, 0x37, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_H", REG_SMC, 0x37, &ixDP_AUX3_DEBUG_H[0], sizeof(ixDP_AUX3_DEBUG_H)/sizeof(ixDP_AUX3_DEBUG_H[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY", REG_SMC, 0x3702, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL", REG_SMC, 0x3707, &ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE", REG_SMC, 0x3708, &ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE", REG_SMC, 0x3709, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x371c, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2", REG_SMC, 0x371d, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3", REG_SMC, 0x371e, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4", REG_SMC, 0x371f, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION", REG_SMC, 0x3770, &ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION", REG_SMC, 0x3771, &ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO", REG_SMC, 0x3772, &ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR", REG_SMC, 0x3776, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE", REG_SMC, 0x3777, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE", REG_SMC, 0x3778, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE", REG_SMC, 0x3779, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE", REG_SMC, 0x377a, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC", REG_SMC, 0x377b, &ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_HBR", REG_SMC, 0x377c, &ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_HBR[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX", REG_SMC, 0x3780, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA", REG_SMC, 0x3781, &ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE", REG_SMC, 0x3785, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE", REG_SMC, 0x3786, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE", REG_SMC, 0x3787, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE", REG_SMC, 0x3788, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x3789, &ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x378a, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x378b, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x378c, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x378d, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x378e, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x378f, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x3790, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x3791, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x3792, &ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x3793, &ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x3797, &ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR", REG_SMC, 0x38, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_I", REG_SMC, 0x38, &ixDP_AUX3_DEBUG_I[0], sizeof(ixDP_AUX3_DEBUG_I)/sizeof(ixDP_AUX3_DEBUG_I[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_J", REG_SMC, 0x39, &ixDP_AUX3_DEBUG_J[0], sizeof(ixDP_AUX3_DEBUG_J)/sizeof(ixDP_AUX3_DEBUG_J[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0", REG_SMC, 0x3a, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_K", REG_SMC, 0x3a, &ixDP_AUX3_DEBUG_K[0], sizeof(ixDP_AUX3_DEBUG_K)/sizeof(ixDP_AUX3_DEBUG_K[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1", REG_SMC, 0x3b, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_L", REG_SMC, 0x3b, &ixDP_AUX3_DEBUG_L[0], sizeof(ixDP_AUX3_DEBUG_L)/sizeof(ixDP_AUX3_DEBUG_L[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2", REG_SMC, 0x3c, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_M", REG_SMC, 0x3c, &ixDP_AUX3_DEBUG_M[0], sizeof(ixDP_AUX3_DEBUG_M)/sizeof(ixDP_AUX3_DEBUG_M[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3", REG_SMC, 0x3d, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_N", REG_SMC, 0x3d, &ixDP_AUX3_DEBUG_N[0], sizeof(ixDP_AUX3_DEBUG_N)/sizeof(ixDP_AUX3_DEBUG_N[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4", REG_SMC, 0x3e, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_O", REG_SMC, 0x3e, &ixDP_AUX3_DEBUG_O[0], sizeof(ixDP_AUX3_DEBUG_O)/sizeof(ixDP_AUX3_DEBUG_O[0]), 0, 0 },
+	{ "mmXDMA_MC_PCIE_CLIENT_CONFIG", REG_MMIO, 0x3e0, &mmXDMA_MC_PCIE_CLIENT_CONFIG[0], sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG)/sizeof(mmXDMA_MC_PCIE_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING1", REG_MMIO, 0x3e1, &mmXDMA_LOCAL_SURFACE_TILING1[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING1)/sizeof(mmXDMA_LOCAL_SURFACE_TILING1[0]), 0, 0 },
+	{ "mmXDMA_LOCAL_SURFACE_TILING2", REG_MMIO, 0x3e2, &mmXDMA_LOCAL_SURFACE_TILING2[0], sizeof(mmXDMA_LOCAL_SURFACE_TILING2)/sizeof(mmXDMA_LOCAL_SURFACE_TILING2[0]), 0, 0 },
+	{ "mmXDMA_INTERRUPT", REG_MMIO, 0x3e3, &mmXDMA_INTERRUPT[0], sizeof(mmXDMA_INTERRUPT)/sizeof(mmXDMA_INTERRUPT[0]), 0, 0 },
+	{ "mmXDMA_CLOCK_GATING_CNTL", REG_MMIO, 0x3e4, &mmXDMA_CLOCK_GATING_CNTL[0], sizeof(mmXDMA_CLOCK_GATING_CNTL)/sizeof(mmXDMA_CLOCK_GATING_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MEM_POWER_CNTL", REG_MMIO, 0x3e6, &mmXDMA_MEM_POWER_CNTL[0], sizeof(mmXDMA_MEM_POWER_CNTL)/sizeof(mmXDMA_MEM_POWER_CNTL[0]), 0, 0 },
+	{ "mmXDMA_IF_BIF_STATUS", REG_MMIO, 0x3e7, &mmXDMA_IF_BIF_STATUS[0], sizeof(mmXDMA_IF_BIF_STATUS)/sizeof(mmXDMA_IF_BIF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_PERF_MEAS_STATUS", REG_MMIO, 0x3e8, &mmXDMA_PERF_MEAS_STATUS[0], sizeof(mmXDMA_PERF_MEAS_STATUS)/sizeof(mmXDMA_PERF_MEAS_STATUS[0]), 0, 0 },
+	{ "mmXDMA_IF_STATUS", REG_MMIO, 0x3e9, &mmXDMA_IF_STATUS[0], sizeof(mmXDMA_IF_STATUS)/sizeof(mmXDMA_IF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_INDEX", REG_MMIO, 0x3ea, &mmXDMA_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_TEST_DEBUG_INDEX)/sizeof(mmXDMA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_TEST_DEBUG_DATA", REG_MMIO, 0x3eb, &mmXDMA_TEST_DEBUG_DATA[0], sizeof(mmXDMA_TEST_DEBUG_DATA)/sizeof(mmXDMA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5", REG_SMC, 0x3f, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_P", REG_SMC, 0x3f, &ixDP_AUX3_DEBUG_P[0], sizeof(ixDP_AUX3_DEBUG_P)/sizeof(ixDP_AUX3_DEBUG_P[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES", REG_SMC, 0x3f09, &ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES", REG_SMC, 0x3f0c, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH", REG_SMC, 0x3f0e, &ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0], sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH)/sizeof(ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH[0]), 0, 0 },
+	{ "mmXDMA_RBBMIF_RDWR_CNTL", REG_MMIO, 0x3f8, &mmXDMA_RBBMIF_RDWR_CNTL[0], sizeof(mmXDMA_RBBMIF_RDWR_CNTL)/sizeof(mmXDMA_RBBMIF_RDWR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_PG_CONTROL", REG_MMIO, 0x3f9, &mmXDMA_PG_CONTROL[0], sizeof(mmXDMA_PG_CONTROL)/sizeof(mmXDMA_PG_CONTROL[0]), 0, 0 },
+	{ "mmXDMA_PG_WDATA", REG_MMIO, 0x3fa, &mmXDMA_PG_WDATA[0], sizeof(mmXDMA_PG_WDATA)/sizeof(mmXDMA_PG_WDATA[0]), 0, 0 },
+	{ "mmXDMA_PG_STATUS", REG_MMIO, 0x3fb, &mmXDMA_PG_STATUS[0], sizeof(mmXDMA_PG_STATUS)/sizeof(mmXDMA_PG_STATUS[0]), 0, 0 },
+	{ "mmXDMA_AON_TEST_DEBUG_INDEX", REG_MMIO, 0x3fc, &mmXDMA_AON_TEST_DEBUG_INDEX[0], sizeof(mmXDMA_AON_TEST_DEBUG_INDEX)/sizeof(mmXDMA_AON_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmXDMA_AON_TEST_DEBUG_DATA", REG_MMIO, 0x3fd, &mmXDMA_AON_TEST_DEBUG_DATA[0], sizeof(mmXDMA_AON_TEST_DEBUG_DATA)/sizeof(mmXDMA_AON_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER", REG_SMC, 0x4, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1", REG_SMC, 0x4, &ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0], sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1)/sizeof(ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1[0]), 0, 0 },
+	{ "ixAZALIA_CUMULATIVE_REQUEST_COUNT", REG_SMC, 0x4, &ixAZALIA_CUMULATIVE_REQUEST_COUNT[0], sizeof(ixAZALIA_CUMULATIVE_REQUEST_COUNT)/sizeof(ixAZALIA_CUMULATIVE_REQUEST_COUNT[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL4", REG_SMC, 0x4, &ixAZALIA_CRC0_CHANNEL4[0], sizeof(ixAZALIA_CRC0_CHANNEL4)/sizeof(ixAZALIA_CRC0_CHANNEL4[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR3", REG_SMC, 0x4, &ixAUDIO_DESCRIPTOR3[0], sizeof(ixAUDIO_DESCRIPTOR3)/sizeof(ixAUDIO_DESCRIPTOR3[0]), 0, 0 },
+	{ "mmGLOBAL_STATUS", REG_MMIO, 0x4, &mmGLOBAL_STATUS[0], sizeof(mmGLOBAL_STATUS)/sizeof(mmGLOBAL_STATUS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG4", REG_SMC, 0x4, &ixDCIO_DEBUG4[0], sizeof(ixDCIO_DEBUG4)/sizeof(ixDCIO_DEBUG4[0]), 0, 0 },
+	{ "ixATTR04", REG_SMC, 0x4, &ixATTR04[0], sizeof(ixATTR04)/sizeof(ixATTR04[0]), 0, 0 },
+	{ "ixSEQ04", REG_SMC, 0x4, &ixSEQ04[0], sizeof(ixSEQ04)/sizeof(ixSEQ04[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6", REG_SMC, 0x40, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_A", REG_SMC, 0x40, &ixDP_AUX4_DEBUG_A[0], sizeof(ixDP_AUX4_DEBUG_A)/sizeof(ixDP_AUX4_DEBUG_A[0]), 0, 0 },
+	{ "mmDCP2_GRPH_ENABLE", REG_MMIO, 0x4000, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_CONTROL", REG_MMIO, 0x4001, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4002, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SWAP_CNTL", REG_MMIO, 0x4003, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4004, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4005, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PITCH", REG_MMIO, 0x4006, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4007, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4008, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4009, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x400a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_START", REG_MMIO, 0x400b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_START", REG_MMIO, 0x400c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_X_END", REG_MMIO, 0x400d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_Y_END", REG_MMIO, 0x400e, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4010, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_UPDATE", REG_MMIO, 0x4011, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_CONTROL", REG_MMIO, 0x4012, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4013, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_CONTROL", REG_MMIO, 0x4014, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_DFQ_STATUS", REG_MMIO, 0x4015, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4016, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4017, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4018, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4019, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_PITCH", REG_MMIO, 0x401a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x401b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_ENABLE", REG_MMIO, 0x401c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_CONTROL1", REG_MMIO, 0x401d, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_CONTROL2", REG_MMIO, 0x401e, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SWAP_CNTL", REG_MMIO, 0x401f, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4020, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_PITCH", REG_MMIO, 0x4021, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4022, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4023, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4024, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_START", REG_MMIO, 0x4025, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_END", REG_MMIO, 0x4026, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_UPDATE", REG_MMIO, 0x4027, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4028, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_DFQ_CONTROL", REG_MMIO, 0x4029, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_DFQ_STATUS", REG_MMIO, 0x402a, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x402b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x402c, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x402d, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x402e, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x402f, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4030, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4031, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4032, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4033, NULL, 0, 0, 0 },
+	{ "mmDCP2_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4034, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_CONTROL", REG_MMIO, 0x4035, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C11_C12", REG_MMIO, 0x4036, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C13_C14", REG_MMIO, 0x4037, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C21_C22", REG_MMIO, 0x4038, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C23_C24", REG_MMIO, 0x4039, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C31_C32", REG_MMIO, 0x403a, NULL, 0, 0, 0 },
+	{ "mmDCP2_INPUT_CSC_C33_C34", REG_MMIO, 0x403b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_CONTROL", REG_MMIO, 0x403c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C11_C12", REG_MMIO, 0x403d, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C13_C14", REG_MMIO, 0x403e, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C21_C22", REG_MMIO, 0x403f, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4040, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4041, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4042, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4043, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4044, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4045, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4046, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4047, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4048, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4049, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x404a, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x404b, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x404c, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x404d, NULL, 0, 0, 0 },
+	{ "mmDCP2_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x404e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DENORM_CONTROL", REG_MMIO, 0x4050, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_ROUND_CONTROL", REG_MMIO, 0x4051, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4052, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_CONTROL", REG_MMIO, 0x4053, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_ALPHA", REG_MMIO, 0x4054, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_RED", REG_MMIO, 0x4055, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_GREEN", REG_MMIO, 0x4056, NULL, 0, 0, 0 },
+	{ "mmDCP2_KEY_RANGE_BLUE", REG_MMIO, 0x4057, NULL, 0, 0, 0 },
+	{ "mmDCP2_DEGAMMA_CONTROL", REG_MMIO, 0x4058, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4059, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C11_C12", REG_MMIO, 0x405a, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C13_C14", REG_MMIO, 0x405b, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C21_C22", REG_MMIO, 0x405c, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C23_C24", REG_MMIO, 0x405d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C31_C32", REG_MMIO, 0x405e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GAMUT_REMAP_C33_C34", REG_MMIO, 0x405f, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4060, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_RANDOM_SEEDS", REG_MMIO, 0x4061, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4065, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_CONTROL", REG_MMIO, 0x4066, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4067, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SIZE", REG_MMIO, 0x4068, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4069, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_POSITION", REG_MMIO, 0x406a, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_HOT_SPOT", REG_MMIO, 0x406b, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR1", REG_MMIO, 0x406c, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_COLOR2", REG_MMIO, 0x406d, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_UPDATE", REG_MMIO, 0x406e, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_CONTROL", REG_MMIO, 0x406f, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_SURFACE_ADDRESS", REG_MMIO, 0x4070, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_SIZE", REG_MMIO, 0x4071, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4072, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_POSITION", REG_MMIO, 0x4073, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_HOT_SPOT", REG_MMIO, 0x4074, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_COLOR1", REG_MMIO, 0x4075, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_COLOR2", REG_MMIO, 0x4076, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_UPDATE", REG_MMIO, 0x4077, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_MODE", REG_MMIO, 0x4078, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_RW_INDEX", REG_MMIO, 0x4079, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_SEQ_COLOR", REG_MMIO, 0x407a, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_PWL_DATA", REG_MMIO, 0x407b, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_30_COLOR", REG_MMIO, 0x407c, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x407d, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x407e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_AUTOFILL", REG_MMIO, 0x407f, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_CONTROL", REG_MMIO, 0x4080, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4081, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4082, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4083, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4084, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4085, NULL, 0, 0, 0 },
+	{ "mmDCP2_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4086, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CONTROL", REG_MMIO, 0x4087, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_MASK", REG_MMIO, 0x4088, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_CURRENT", REG_MMIO, 0x4089, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_CRC_LAST", REG_MMIO, 0x408b, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG", REG_MMIO, 0x408d, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x408e, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_GSL_CONTROL", REG_MMIO, 0x4090, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4091, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4092, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4093, NULL, 0, 0, 0 },
+	{ "mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4094, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4095, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4096, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4097, NULL, 0, 0, 0 },
+	{ "mmDCP2_DCP_DEBUG2", REG_MMIO, 0x4098, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4099, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR_STEREO_CONTROL", REG_MMIO, 0x409a, NULL, 0, 0, 0 },
+	{ "mmDCP2_CUR2_STEREO_CONTROL", REG_MMIO, 0x409b, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x409c, NULL, 0, 0, 0 },
+	{ "mmDCP2_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x409d, NULL, 0, 0, 0 },
+	{ "mmDCP2_HW_ROTATION", REG_MMIO, 0x409e, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x409f, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CONTROL", REG_MMIO, 0x40a0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_INDEX", REG_MMIO, 0x40a1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_DATA", REG_MMIO, 0x40a2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x40a3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x40a4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x40a5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x40a6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x40a7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x40a8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x40a9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x40aa, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x40ab, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x40ac, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x40ad, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x40ae, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x40af, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x40b0, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x40b1, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x40b2, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x40b3, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x40b4, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x40b5, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x40b6, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x40b7, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x40b8, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x40b9, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x40ba, NULL, 0, 0, 0 },
+	{ "mmDCP2_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x40bb, NULL, 0, 0, 0 },
+	{ "mmDCP2_ALPHA_CONTROL", REG_MMIO, 0x40bc, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x40bd, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x40be, NULL, 0, 0, 0 },
+	{ "mmDCP2_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x40bf, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DATA_FORMAT", REG_MMIO, 0x40c0, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_MEMORY_CTRL", REG_MMIO, 0x40c1, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x40c2, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DESKTOP_HEIGHT", REG_MMIO, 0x40c3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE_START_END", REG_MMIO, 0x40c4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE2_START_END", REG_MMIO, 0x40c5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_V_COUNTER", REG_MMIO, 0x40c6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x40c7, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_INTERRUPT_MASK", REG_MMIO, 0x40c8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE_STATUS", REG_MMIO, 0x40c9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VLINE2_STATUS", REG_MMIO, 0x40ca, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_VBLANK_STATUS", REG_MMIO, 0x40cb, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_SYNC_RESET_SEL", REG_MMIO, 0x40cc, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x40cd, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x40ce, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x40cf, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x40d0, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x40d1, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x40d2, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x40d3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x40d4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x40d5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x40d6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x40d7, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x40d8, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x40d9, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_BUFFER_STATUS", REG_MMIO, 0x40da, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x40dc, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_MODE", REG_MMIO, 0x40e0, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x40e1, NULL, 0, 0, 0 },
+	{ "mmLB2_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x40e2, NULL, 0, 0, 0 },
+	{ "mmLB2_DC_MVP_LB_CONTROL", REG_MMIO, 0x40e3, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG", REG_MMIO, 0x40e4, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG2", REG_MMIO, 0x40e5, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_DEBUG3", REG_MMIO, 0x40e6, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x40fe, NULL, 0, 0, 0 },
+	{ "mmLB2_LB_TEST_DEBUG_DATA", REG_MMIO, 0x40ff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7", REG_SMC, 0x41, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_B", REG_SMC, 0x41, &ixDP_AUX4_DEBUG_B[0], sizeof(ixDP_AUX4_DEBUG_B)/sizeof(ixDP_AUX4_DEBUG_B[0]), 0, 0 },
+	{ "mmDC_PERFMON4_PERFCOUNTER_CNTL", REG_MMIO, 0x4124, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFCOUNTER_STATE", REG_MMIO, 0x4125, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4126, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CNTL", REG_MMIO, 0x4127, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_CVALUE_LOW", REG_MMIO, 0x4128, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_HI", REG_MMIO, 0x4129, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_LOW", REG_MMIO, 0x412a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x412b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON4_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x412c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4130, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4131, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4132, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4133, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4134, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4135, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4136, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4137, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4138, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4139, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_REPEATER_PROGRAM", REG_MMIO, 0x413a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_A", REG_MMIO, 0x413b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG2_DPG_HW_DEBUG_B", REG_MMIO, 0x413c, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4140, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4141, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE", REG_MMIO, 0x4142, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TAP_CONTROL", REG_MMIO, 0x4143, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_CONTROL", REG_MMIO, 0x4144, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_BYPASS_CONTROL", REG_MMIO, 0x4145, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4146, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4147, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4148, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4149, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x414a, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x414b, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x414c, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT", REG_MMIO, 0x414d, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x414e, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ROUND_OFFSET", REG_MMIO, 0x414f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_UPDATE", REG_MMIO, 0x4151, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4153, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_ALU_CONTROL", REG_MMIO, 0x4154, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4155, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_START", REG_MMIO, 0x415c, NULL, 0, 0, 0 },
+	{ "mmSCL2_VIEWPORT_SIZE", REG_MMIO, 0x415d, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x415e, NULL, 0, 0, 0 },
+	{ "mmSCL2_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x415f, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4160, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4161, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4162, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4163, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG2", REG_MMIO, 0x4169, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_DEBUG", REG_MMIO, 0x416a, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x416b, NULL, 0, 0, 0 },
+	{ "mmSCL2_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x416c, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_CONTROL", REG_MMIO, 0x416d, NULL, 0, 0, 0 },
+	{ "mmBLND2_SM_CONTROL2", REG_MMIO, 0x416e, NULL, 0, 0, 0 },
+	{ "mmBLND2_PTI_CONTROL", REG_MMIO, 0x416f, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_UPDATE", REG_MMIO, 0x4170, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4171, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4173, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_DEBUG", REG_MMIO, 0x4174, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4175, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4176, NULL, 0, 0, 0 },
+	{ "mmBLND2_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4177, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4178, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4179, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_WINDOW", REG_MMIO, 0x417a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_GSL_CONTROL", REG_MMIO, 0x417b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x417c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x417d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_DCFE_DBG_SEL", REG_MMIO, 0x417e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x417f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_TOTAL", REG_MMIO, 0x4180, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_BLANK_START_END", REG_MMIO, 0x4181, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A", REG_MMIO, 0x4182, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4183, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B", REG_MMIO, 0x4184, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4185, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VBI_END", REG_MMIO, 0x4186, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL", REG_MMIO, 0x4187, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4188, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4189, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x418a, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x418b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x418c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_BLANK_START_END", REG_MMIO, 0x418d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A", REG_MMIO, 0x418e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x418f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B", REG_MMIO, 0x4190, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4191, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4192, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4193, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_CNTL", REG_MMIO, 0x4194, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4195, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_CNTL", REG_MMIO, 0x4196, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4197, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4198, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FLOW_CONTROL", REG_MMIO, 0x4199, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x419b, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CONTROL", REG_MMIO, 0x419c, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_CONTROL", REG_MMIO, 0x419d, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x419e, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERLACE_STATUS", REG_MMIO, 0x419f, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x41a0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x41a1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x41a2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS", REG_MMIO, 0x41a3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_POSITION", REG_MMIO, 0x41a4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x41a5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x41a6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x41a7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x41a8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_CONTROL", REG_MMIO, 0x41a9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_COUNT_RESET", REG_MMIO, 0x41aa, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x41ab, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x41ac, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_STATUS", REG_MMIO, 0x41ad, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STEREO_CONTROL", REG_MMIO, 0x41ae, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x41af, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x41b0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x41b1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x41b2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_START_LINE_CONTROL", REG_MMIO, 0x41b3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x41b4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_UPDATE_LOCK", REG_MMIO, 0x41b5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x41b6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x41b7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x41ba, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x41bb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x41bc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_MASTER_UPDATE_LOCK", REG_MMIO, 0x41bd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_MASTER_UPDATE_MODE", REG_MMIO, 0x41be, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x41bf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x41c0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MVP_STATUS", REG_MMIO, 0x41c1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_MASTER_EN", REG_MMIO, 0x41c2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x41c3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x41c4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x41c6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x41c7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x41c8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x41c9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x41ca, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x41cb, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR", REG_MMIO, 0x41cc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x41cd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x41ce, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x41cf, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x41d0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x41d1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x41d2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x41d3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC_CNTL", REG_MMIO, 0x41d4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x41d5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x41d6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x41d7, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x41d8, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_DATA_RG", REG_MMIO, 0x41d9, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC0_DATA_B", REG_MMIO, 0x41da, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x41db, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x41dc, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x41dd, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x41de, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_DATA_RG", REG_MMIO, 0x41df, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_CRC1_DATA_B", REG_MMIO, 0x41e0, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x41e1, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x41e2, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x41e3, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x41e4, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x41e5, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x41e6, NULL, 0, 0, 0 },
+	{ "mmCRTC2_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x41e7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x41e8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x41e9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x41ea, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x41eb, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x41ec, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x41ed, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CONTROL", REG_MMIO, 0x41ee, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x41ef, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_DATA_0_1", REG_MMIO, 0x41f0, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_FORCE_DATA_2_3", REG_MMIO, 0x41f1, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x41f2, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x41f3, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x41f4, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x41f5, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x41f6, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x41f7, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x41f8, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CLAMP_CNTL", REG_MMIO, 0x41f9, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_CNTL", REG_MMIO, 0x41fa, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x41fb, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x41fc, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x41fd, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x41fe, NULL, 0, 0, 0 },
+	{ "mmFMT2_FMT_DEBUG_CNTL", REG_MMIO, 0x41ff, NULL, 0, 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8", REG_SMC, 0x42, &ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_C", REG_SMC, 0x42, &ixDP_AUX4_DEBUG_C[0], sizeof(ixDP_AUX4_DEBUG_C)/sizeof(ixDP_AUX4_DEBUG_C[0]), 0, 0 },
+	{ "mmDIG2_DIG_FE_CNTL", REG_MMIO, 0x4200, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4201, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4202, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_CLOCK_PATTERN", REG_MMIO, 0x4203, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_TEST_PATTERN", REG_MMIO, 0x4204, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4205, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4208, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4209, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_FIFO_STATUS", REG_MMIO, 0x420a, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_CONTROL", REG_MMIO, 0x420c, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_STATUS", REG_MMIO, 0x420d, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x420e, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x420f, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4210, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4211, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4212, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4213, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4214, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GC", REG_MMIO, 0x4216, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4217, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_0", REG_MMIO, 0x4218, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_1", REG_MMIO, 0x4219, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_2", REG_MMIO, 0x421a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_3", REG_MMIO, 0x421b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC1_4", REG_MMIO, 0x421c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_0", REG_MMIO, 0x421d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_1", REG_MMIO, 0x421e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_2", REG_MMIO, 0x421f, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_ISRC2_3", REG_MMIO, 0x4220, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO0", REG_MMIO, 0x4221, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO1", REG_MMIO, 0x4222, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO2", REG_MMIO, 0x4223, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AVI_INFO3", REG_MMIO, 0x4224, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO0", REG_MMIO, 0x4225, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_MPEG_INFO1", REG_MMIO, 0x4226, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_HDR", REG_MMIO, 0x4227, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_0", REG_MMIO, 0x4228, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_1", REG_MMIO, 0x4229, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_2", REG_MMIO, 0x422a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_3", REG_MMIO, 0x422b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_4", REG_MMIO, 0x422c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_5", REG_MMIO, 0x422d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_6", REG_MMIO, 0x422e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_GENERIC_7", REG_MMIO, 0x422f, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4230, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_0", REG_MMIO, 0x4237, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_32_1", REG_MMIO, 0x4238, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_0", REG_MMIO, 0x4239, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_44_1", REG_MMIO, 0x423a, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_0", REG_MMIO, 0x423b, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_48_1", REG_MMIO, 0x423c, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_0", REG_MMIO, 0x423d, NULL, 0, 0, 0 },
+	{ "mmDIG2_HDMI_ACR_STATUS_1", REG_MMIO, 0x423e, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO0", REG_MMIO, 0x423f, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_INFO1", REG_MMIO, 0x4240, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_0", REG_MMIO, 0x4241, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_1", REG_MMIO, 0x4242, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4243, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4244, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4245, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4246, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4247, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_60958_2", REG_MMIO, 0x4248, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4249, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_STATUS", REG_MMIO, 0x424a, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x424b, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x424c, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x424d, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x424f, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_CNTL", REG_MMIO, 0x4250, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_BE_EN_CNTL", REG_MMIO, 0x4251, NULL, 0, 0, 0 },
+	{ "mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4252, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CNTL", REG_MMIO, 0x427c, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL_CHAR", REG_MMIO, 0x427d, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x427e, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x427f, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4280, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4281, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DEBUG", REG_MMIO, 0x4282, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL_BITS", REG_MMIO, 0x4283, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4284, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4286, NULL, 0, 0, 0 },
+	{ "mmDIG2_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4287, NULL, 0, 0, 0 },
+	{ "mmDIG2_LVDS_DATA_CNTL", REG_MMIO, 0x428c, NULL, 0, 0, 0 },
+	{ "mmDIG2_DIG_LANE_ENABLE", REG_MMIO, 0x428d, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL", REG_MMIO, 0x42a0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING1", REG_MMIO, 0x42a1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING2", REG_MMIO, 0x42a2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING3", REG_MMIO, 0x42a3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_FRAMING4", REG_MMIO, 0x42a4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N", REG_MMIO, 0x42a5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x42a6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M", REG_MMIO, 0x42a7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x42a8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_TIMESTAMP", REG_MMIO, 0x42a9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_PACKET_CNTL", REG_MMIO, 0x42aa, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_SEC_CNTL1", REG_MMIO, 0x42ab, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_CNTL", REG_MMIO, 0x42c0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_PIXEL_FORMAT", REG_MMIO, 0x42c1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_CONFIG", REG_MMIO, 0x42c2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_STREAM_CNTL", REG_MMIO, 0x42c3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_STEER_FIFO", REG_MMIO, 0x42c4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_MISC", REG_MMIO, 0x42c5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x42c6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x42c7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x42c8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_TIMING", REG_MMIO, 0x42c9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_N", REG_MMIO, 0x42ca, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_M", REG_MMIO, 0x42cb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x42cc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_MSA_VBID", REG_MMIO, 0x42cd, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x42ce, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x42cf, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CNTL", REG_MMIO, 0x42d0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x42d1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM0", REG_MMIO, 0x42d2, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x42d3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x42d4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x42d5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_EN", REG_MMIO, 0x42d6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_CNTL", REG_MMIO, 0x42d7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_CRC_RESULT", REG_MMIO, 0x42d8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_COLORIMETRY", REG_MMIO, 0x42da, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_MISC_CNTL", REG_MMIO, 0x42db, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM2", REG_MMIO, 0x42df, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_SYM1", REG_MMIO, 0x42e0, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_CNTL", REG_MMIO, 0x42e1, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_RATE_UPDATE", REG_MMIO, 0x42e3, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT0", REG_MMIO, 0x42e4, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT1", REG_MMIO, 0x42e5, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT2", REG_MMIO, 0x42e6, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_SAT_UPDATE", REG_MMIO, 0x42e7, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSE_LINK_TIMING", REG_MMIO, 0x42e8, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x42e9, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x42ea, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x42eb, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x42fc, NULL, 0, 0, 0 },
+	{ "mmDP2_DP_TEST_DEBUG_DATA", REG_MMIO, 0x42fd, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_D", REG_SMC, 0x43, &ixDP_AUX4_DEBUG_D[0], sizeof(ixDP_AUX4_DEBUG_D)/sizeof(ixDP_AUX4_DEBUG_D[0]), 0, 0 },
+	{ "mmDCP3_GRPH_ENABLE", REG_MMIO, 0x4300, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_CONTROL", REG_MMIO, 0x4301, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4302, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SWAP_CNTL", REG_MMIO, 0x4303, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4304, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4305, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PITCH", REG_MMIO, 0x4306, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4307, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4308, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4309, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x430a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_START", REG_MMIO, 0x430b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_START", REG_MMIO, 0x430c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_X_END", REG_MMIO, 0x430d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_Y_END", REG_MMIO, 0x430e, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4310, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_UPDATE", REG_MMIO, 0x4311, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_CONTROL", REG_MMIO, 0x4312, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4313, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_CONTROL", REG_MMIO, 0x4314, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_DFQ_STATUS", REG_MMIO, 0x4315, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4316, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4317, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4318, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4319, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_PITCH", REG_MMIO, 0x431a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x431b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_ENABLE", REG_MMIO, 0x431c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_CONTROL1", REG_MMIO, 0x431d, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_CONTROL2", REG_MMIO, 0x431e, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SWAP_CNTL", REG_MMIO, 0x431f, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4320, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_PITCH", REG_MMIO, 0x4321, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4322, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4323, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4324, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_START", REG_MMIO, 0x4325, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_END", REG_MMIO, 0x4326, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_UPDATE", REG_MMIO, 0x4327, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4328, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_DFQ_CONTROL", REG_MMIO, 0x4329, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_DFQ_STATUS", REG_MMIO, 0x432a, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x432b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x432c, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x432d, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x432e, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x432f, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4330, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4331, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4332, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4333, NULL, 0, 0, 0 },
+	{ "mmDCP3_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4334, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_CONTROL", REG_MMIO, 0x4335, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C11_C12", REG_MMIO, 0x4336, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C13_C14", REG_MMIO, 0x4337, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C21_C22", REG_MMIO, 0x4338, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C23_C24", REG_MMIO, 0x4339, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C31_C32", REG_MMIO, 0x433a, NULL, 0, 0, 0 },
+	{ "mmDCP3_INPUT_CSC_C33_C34", REG_MMIO, 0x433b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_CONTROL", REG_MMIO, 0x433c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C11_C12", REG_MMIO, 0x433d, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C13_C14", REG_MMIO, 0x433e, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C21_C22", REG_MMIO, 0x433f, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4340, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4341, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4342, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4343, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4344, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4345, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4346, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4347, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4348, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4349, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x434a, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x434b, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x434c, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x434d, NULL, 0, 0, 0 },
+	{ "mmDCP3_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x434e, NULL, 0, 0, 0 },
+	{ "mmDCP3_DENORM_CONTROL", REG_MMIO, 0x4350, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_ROUND_CONTROL", REG_MMIO, 0x4351, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4352, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_CONTROL", REG_MMIO, 0x4353, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_ALPHA", REG_MMIO, 0x4354, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_RED", REG_MMIO, 0x4355, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_GREEN", REG_MMIO, 0x4356, NULL, 0, 0, 0 },
+	{ "mmDCP3_KEY_RANGE_BLUE", REG_MMIO, 0x4357, NULL, 0, 0, 0 },
+	{ "mmDCP3_DEGAMMA_CONTROL", REG_MMIO, 0x4358, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4359, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C11_C12", REG_MMIO, 0x435a, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C13_C14", REG_MMIO, 0x435b, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C21_C22", REG_MMIO, 0x435c, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C23_C24", REG_MMIO, 0x435d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C31_C32", REG_MMIO, 0x435e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GAMUT_REMAP_C33_C34", REG_MMIO, 0x435f, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4360, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_RANDOM_SEEDS", REG_MMIO, 0x4361, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4365, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_CONTROL", REG_MMIO, 0x4366, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4367, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SIZE", REG_MMIO, 0x4368, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4369, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_POSITION", REG_MMIO, 0x436a, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_HOT_SPOT", REG_MMIO, 0x436b, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR1", REG_MMIO, 0x436c, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_COLOR2", REG_MMIO, 0x436d, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_UPDATE", REG_MMIO, 0x436e, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_CONTROL", REG_MMIO, 0x436f, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_SURFACE_ADDRESS", REG_MMIO, 0x4370, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_SIZE", REG_MMIO, 0x4371, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4372, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_POSITION", REG_MMIO, 0x4373, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_HOT_SPOT", REG_MMIO, 0x4374, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_COLOR1", REG_MMIO, 0x4375, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_COLOR2", REG_MMIO, 0x4376, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_UPDATE", REG_MMIO, 0x4377, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_MODE", REG_MMIO, 0x4378, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_RW_INDEX", REG_MMIO, 0x4379, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_SEQ_COLOR", REG_MMIO, 0x437a, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_PWL_DATA", REG_MMIO, 0x437b, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_30_COLOR", REG_MMIO, 0x437c, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x437d, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x437e, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_AUTOFILL", REG_MMIO, 0x437f, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_CONTROL", REG_MMIO, 0x4380, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4381, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4382, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4383, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4384, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4385, NULL, 0, 0, 0 },
+	{ "mmDCP3_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4386, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CONTROL", REG_MMIO, 0x4387, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_MASK", REG_MMIO, 0x4388, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_CURRENT", REG_MMIO, 0x4389, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_CRC_LAST", REG_MMIO, 0x438b, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG", REG_MMIO, 0x438d, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x438e, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_GSL_CONTROL", REG_MMIO, 0x4390, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4391, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4392, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4393, NULL, 0, 0, 0 },
+	{ "mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4394, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4395, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4396, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4397, NULL, 0, 0, 0 },
+	{ "mmDCP3_DCP_DEBUG2", REG_MMIO, 0x4398, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4399, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR_STEREO_CONTROL", REG_MMIO, 0x439a, NULL, 0, 0, 0 },
+	{ "mmDCP3_CUR2_STEREO_CONTROL", REG_MMIO, 0x439b, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x439c, NULL, 0, 0, 0 },
+	{ "mmDCP3_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x439d, NULL, 0, 0, 0 },
+	{ "mmDCP3_HW_ROTATION", REG_MMIO, 0x439e, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x439f, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CONTROL", REG_MMIO, 0x43a0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_INDEX", REG_MMIO, 0x43a1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_DATA", REG_MMIO, 0x43a2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x43a3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x43a4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x43a5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x43a6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x43a7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x43a8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x43a9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x43aa, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x43ab, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x43ac, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x43ad, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x43ae, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x43af, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x43b0, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x43b1, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x43b2, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x43b3, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x43b4, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x43b5, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x43b6, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x43b7, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x43b8, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x43b9, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x43ba, NULL, 0, 0, 0 },
+	{ "mmDCP3_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x43bb, NULL, 0, 0, 0 },
+	{ "mmDCP3_ALPHA_CONTROL", REG_MMIO, 0x43bc, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x43bd, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x43be, NULL, 0, 0, 0 },
+	{ "mmDCP3_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x43bf, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DATA_FORMAT", REG_MMIO, 0x43c0, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_MEMORY_CTRL", REG_MMIO, 0x43c1, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x43c2, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DESKTOP_HEIGHT", REG_MMIO, 0x43c3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE_START_END", REG_MMIO, 0x43c4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE2_START_END", REG_MMIO, 0x43c5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_V_COUNTER", REG_MMIO, 0x43c6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x43c7, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_INTERRUPT_MASK", REG_MMIO, 0x43c8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE_STATUS", REG_MMIO, 0x43c9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VLINE2_STATUS", REG_MMIO, 0x43ca, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_VBLANK_STATUS", REG_MMIO, 0x43cb, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_SYNC_RESET_SEL", REG_MMIO, 0x43cc, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x43cd, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x43ce, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x43cf, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x43d0, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x43d1, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x43d2, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x43d3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x43d4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x43d5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x43d6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x43d7, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x43d8, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x43d9, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_BUFFER_STATUS", REG_MMIO, 0x43da, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x43dc, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_MODE", REG_MMIO, 0x43e0, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x43e1, NULL, 0, 0, 0 },
+	{ "mmLB3_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x43e2, NULL, 0, 0, 0 },
+	{ "mmLB3_DC_MVP_LB_CONTROL", REG_MMIO, 0x43e3, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG", REG_MMIO, 0x43e4, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG2", REG_MMIO, 0x43e5, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_DEBUG3", REG_MMIO, 0x43e6, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x43fe, NULL, 0, 0, 0 },
+	{ "mmLB3_LB_TEST_DEBUG_DATA", REG_MMIO, 0x43ff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_E", REG_SMC, 0x44, &ixDP_AUX4_DEBUG_E[0], sizeof(ixDP_AUX4_DEBUG_E)/sizeof(ixDP_AUX4_DEBUG_E[0]), 0, 0 },
+	{ "mmDC_PERFMON5_PERFCOUNTER_CNTL", REG_MMIO, 0x4424, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFCOUNTER_STATE", REG_MMIO, 0x4425, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4426, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CNTL", REG_MMIO, 0x4427, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_CVALUE_LOW", REG_MMIO, 0x4428, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_HI", REG_MMIO, 0x4429, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_LOW", REG_MMIO, 0x442a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x442b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON5_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x442c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4430, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4431, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4432, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4433, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4434, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4435, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4436, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4437, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4438, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4439, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_REPEATER_PROGRAM", REG_MMIO, 0x443a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_A", REG_MMIO, 0x443b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG3_DPG_HW_DEBUG_B", REG_MMIO, 0x443c, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4440, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4441, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE", REG_MMIO, 0x4442, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TAP_CONTROL", REG_MMIO, 0x4443, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_CONTROL", REG_MMIO, 0x4444, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_BYPASS_CONTROL", REG_MMIO, 0x4445, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4446, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4447, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4448, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4449, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x444a, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x444b, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x444c, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT", REG_MMIO, 0x444d, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x444e, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ROUND_OFFSET", REG_MMIO, 0x444f, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_UPDATE", REG_MMIO, 0x4451, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4453, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_ALU_CONTROL", REG_MMIO, 0x4454, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4455, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_START", REG_MMIO, 0x445c, NULL, 0, 0, 0 },
+	{ "mmSCL3_VIEWPORT_SIZE", REG_MMIO, 0x445d, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x445e, NULL, 0, 0, 0 },
+	{ "mmSCL3_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x445f, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4460, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4461, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4462, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4463, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG2", REG_MMIO, 0x4469, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_DEBUG", REG_MMIO, 0x446a, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x446b, NULL, 0, 0, 0 },
+	{ "mmSCL3_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x446c, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_CONTROL", REG_MMIO, 0x446d, NULL, 0, 0, 0 },
+	{ "mmBLND3_SM_CONTROL2", REG_MMIO, 0x446e, NULL, 0, 0, 0 },
+	{ "mmBLND3_PTI_CONTROL", REG_MMIO, 0x446f, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_UPDATE", REG_MMIO, 0x4470, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4471, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4473, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_DEBUG", REG_MMIO, 0x4474, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4475, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4476, NULL, 0, 0, 0 },
+	{ "mmBLND3_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4477, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4478, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4479, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_WINDOW", REG_MMIO, 0x447a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_GSL_CONTROL", REG_MMIO, 0x447b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x447c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x447d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_DCFE_DBG_SEL", REG_MMIO, 0x447e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x447f, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_TOTAL", REG_MMIO, 0x4480, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_BLANK_START_END", REG_MMIO, 0x4481, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A", REG_MMIO, 0x4482, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4483, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B", REG_MMIO, 0x4484, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4485, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VBI_END", REG_MMIO, 0x4486, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL", REG_MMIO, 0x4487, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4488, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4489, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x448a, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x448b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x448c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_BLANK_START_END", REG_MMIO, 0x448d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A", REG_MMIO, 0x448e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x448f, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B", REG_MMIO, 0x4490, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4491, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4492, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4493, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_CNTL", REG_MMIO, 0x4494, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4495, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_CNTL", REG_MMIO, 0x4496, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4497, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4498, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FLOW_CONTROL", REG_MMIO, 0x4499, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x449b, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CONTROL", REG_MMIO, 0x449c, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_CONTROL", REG_MMIO, 0x449d, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x449e, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERLACE_STATUS", REG_MMIO, 0x449f, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x44a0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x44a1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x44a2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS", REG_MMIO, 0x44a3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_POSITION", REG_MMIO, 0x44a4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x44a5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x44a6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x44a7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x44a8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_CONTROL", REG_MMIO, 0x44a9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_COUNT_RESET", REG_MMIO, 0x44aa, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x44ab, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x44ac, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_STATUS", REG_MMIO, 0x44ad, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STEREO_CONTROL", REG_MMIO, 0x44ae, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x44af, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x44b0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x44b1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x44b2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_START_LINE_CONTROL", REG_MMIO, 0x44b3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x44b4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_UPDATE_LOCK", REG_MMIO, 0x44b5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x44b6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x44b7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x44ba, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x44bb, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x44bc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_MASTER_UPDATE_LOCK", REG_MMIO, 0x44bd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_MASTER_UPDATE_MODE", REG_MMIO, 0x44be, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x44bf, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x44c0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MVP_STATUS", REG_MMIO, 0x44c1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_MASTER_EN", REG_MMIO, 0x44c2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x44c3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x44c4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x44c6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x44c7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x44c8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x44c9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x44ca, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x44cb, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR", REG_MMIO, 0x44cc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x44cd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x44ce, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x44cf, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x44d0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x44d1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x44d2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x44d3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC_CNTL", REG_MMIO, 0x44d4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x44d5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x44d6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x44d7, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x44d8, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_DATA_RG", REG_MMIO, 0x44d9, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC0_DATA_B", REG_MMIO, 0x44da, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x44db, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x44dc, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x44dd, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x44de, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_DATA_RG", REG_MMIO, 0x44df, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_CRC1_DATA_B", REG_MMIO, 0x44e0, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x44e1, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x44e2, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x44e3, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x44e4, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x44e5, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x44e6, NULL, 0, 0, 0 },
+	{ "mmCRTC3_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x44e7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x44e8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x44e9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x44ea, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x44eb, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x44ec, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x44ed, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CONTROL", REG_MMIO, 0x44ee, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x44ef, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_DATA_0_1", REG_MMIO, 0x44f0, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_FORCE_DATA_2_3", REG_MMIO, 0x44f1, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x44f2, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x44f3, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x44f4, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x44f5, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x44f6, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x44f7, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x44f8, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CLAMP_CNTL", REG_MMIO, 0x44f9, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_CNTL", REG_MMIO, 0x44fa, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x44fb, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x44fc, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x44fd, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x44fe, NULL, 0, 0, 0 },
+	{ "mmFMT3_FMT_DEBUG_CNTL", REG_MMIO, 0x44ff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_F", REG_SMC, 0x45, &ixDP_AUX4_DEBUG_F[0], sizeof(ixDP_AUX4_DEBUG_F)/sizeof(ixDP_AUX4_DEBUG_F[0]), 0, 0 },
+	{ "mmDIG3_DIG_FE_CNTL", REG_MMIO, 0x4500, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4501, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4502, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_CLOCK_PATTERN", REG_MMIO, 0x4503, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_TEST_PATTERN", REG_MMIO, 0x4504, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4505, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4508, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4509, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_FIFO_STATUS", REG_MMIO, 0x450a, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_CONTROL", REG_MMIO, 0x450c, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_STATUS", REG_MMIO, 0x450d, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x450e, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x450f, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4510, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4511, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4512, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4513, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4514, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GC", REG_MMIO, 0x4516, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4517, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_0", REG_MMIO, 0x4518, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_1", REG_MMIO, 0x4519, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_2", REG_MMIO, 0x451a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_3", REG_MMIO, 0x451b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC1_4", REG_MMIO, 0x451c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_0", REG_MMIO, 0x451d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_1", REG_MMIO, 0x451e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_2", REG_MMIO, 0x451f, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_ISRC2_3", REG_MMIO, 0x4520, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO0", REG_MMIO, 0x4521, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO1", REG_MMIO, 0x4522, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO2", REG_MMIO, 0x4523, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AVI_INFO3", REG_MMIO, 0x4524, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO0", REG_MMIO, 0x4525, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_MPEG_INFO1", REG_MMIO, 0x4526, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_HDR", REG_MMIO, 0x4527, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_0", REG_MMIO, 0x4528, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_1", REG_MMIO, 0x4529, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_2", REG_MMIO, 0x452a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_3", REG_MMIO, 0x452b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_4", REG_MMIO, 0x452c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_5", REG_MMIO, 0x452d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_6", REG_MMIO, 0x452e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_GENERIC_7", REG_MMIO, 0x452f, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4530, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_0", REG_MMIO, 0x4537, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_32_1", REG_MMIO, 0x4538, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_0", REG_MMIO, 0x4539, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_44_1", REG_MMIO, 0x453a, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_0", REG_MMIO, 0x453b, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_48_1", REG_MMIO, 0x453c, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_0", REG_MMIO, 0x453d, NULL, 0, 0, 0 },
+	{ "mmDIG3_HDMI_ACR_STATUS_1", REG_MMIO, 0x453e, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO0", REG_MMIO, 0x453f, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_INFO1", REG_MMIO, 0x4540, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_0", REG_MMIO, 0x4541, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_1", REG_MMIO, 0x4542, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4543, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4544, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4545, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4546, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4547, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_60958_2", REG_MMIO, 0x4548, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4549, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_STATUS", REG_MMIO, 0x454a, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x454b, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x454c, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x454d, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x454f, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_CNTL", REG_MMIO, 0x4550, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_BE_EN_CNTL", REG_MMIO, 0x4551, NULL, 0, 0, 0 },
+	{ "mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4552, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CNTL", REG_MMIO, 0x457c, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL_CHAR", REG_MMIO, 0x457d, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x457e, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x457f, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4580, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4581, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DEBUG", REG_MMIO, 0x4582, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL_BITS", REG_MMIO, 0x4583, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4584, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4586, NULL, 0, 0, 0 },
+	{ "mmDIG3_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4587, NULL, 0, 0, 0 },
+	{ "mmDIG3_LVDS_DATA_CNTL", REG_MMIO, 0x458c, NULL, 0, 0, 0 },
+	{ "mmDIG3_DIG_LANE_ENABLE", REG_MMIO, 0x458d, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL", REG_MMIO, 0x45a0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING1", REG_MMIO, 0x45a1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING2", REG_MMIO, 0x45a2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING3", REG_MMIO, 0x45a3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_FRAMING4", REG_MMIO, 0x45a4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N", REG_MMIO, 0x45a5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x45a6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M", REG_MMIO, 0x45a7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x45a8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_TIMESTAMP", REG_MMIO, 0x45a9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_PACKET_CNTL", REG_MMIO, 0x45aa, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_SEC_CNTL1", REG_MMIO, 0x45ab, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_CNTL", REG_MMIO, 0x45c0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_PIXEL_FORMAT", REG_MMIO, 0x45c1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_CONFIG", REG_MMIO, 0x45c2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_STREAM_CNTL", REG_MMIO, 0x45c3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_STEER_FIFO", REG_MMIO, 0x45c4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_MISC", REG_MMIO, 0x45c5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x45c6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x45c7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x45c8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_TIMING", REG_MMIO, 0x45c9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_N", REG_MMIO, 0x45ca, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_M", REG_MMIO, 0x45cb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x45cc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_MSA_VBID", REG_MMIO, 0x45cd, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x45ce, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x45cf, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CNTL", REG_MMIO, 0x45d0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x45d1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM0", REG_MMIO, 0x45d2, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x45d3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x45d4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x45d5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_EN", REG_MMIO, 0x45d6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_CNTL", REG_MMIO, 0x45d7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_CRC_RESULT", REG_MMIO, 0x45d8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_COLORIMETRY", REG_MMIO, 0x45da, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_MISC_CNTL", REG_MMIO, 0x45db, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM2", REG_MMIO, 0x45df, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_SYM1", REG_MMIO, 0x45e0, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_CNTL", REG_MMIO, 0x45e1, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_RATE_UPDATE", REG_MMIO, 0x45e3, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT0", REG_MMIO, 0x45e4, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT1", REG_MMIO, 0x45e5, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT2", REG_MMIO, 0x45e6, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_SAT_UPDATE", REG_MMIO, 0x45e7, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSE_LINK_TIMING", REG_MMIO, 0x45e8, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x45e9, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x45ea, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x45eb, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x45fc, NULL, 0, 0, 0 },
+	{ "mmDP3_DP_TEST_DEBUG_DATA", REG_MMIO, 0x45fd, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_G", REG_SMC, 0x46, &ixDP_AUX4_DEBUG_G[0], sizeof(ixDP_AUX4_DEBUG_G)/sizeof(ixDP_AUX4_DEBUG_G[0]), 0, 0 },
+	{ "mmDCP4_GRPH_ENABLE", REG_MMIO, 0x4600, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_CONTROL", REG_MMIO, 0x4601, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4602, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SWAP_CNTL", REG_MMIO, 0x4603, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4604, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4605, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PITCH", REG_MMIO, 0x4606, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4607, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4608, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4609, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x460a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_START", REG_MMIO, 0x460b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_START", REG_MMIO, 0x460c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_X_END", REG_MMIO, 0x460d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_Y_END", REG_MMIO, 0x460e, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4610, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_UPDATE", REG_MMIO, 0x4611, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_CONTROL", REG_MMIO, 0x4612, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4613, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_CONTROL", REG_MMIO, 0x4614, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_DFQ_STATUS", REG_MMIO, 0x4615, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4616, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4617, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4618, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4619, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_PITCH", REG_MMIO, 0x461a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x461b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_ENABLE", REG_MMIO, 0x461c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_CONTROL1", REG_MMIO, 0x461d, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_CONTROL2", REG_MMIO, 0x461e, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SWAP_CNTL", REG_MMIO, 0x461f, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4620, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_PITCH", REG_MMIO, 0x4621, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4622, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4623, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4624, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_START", REG_MMIO, 0x4625, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_END", REG_MMIO, 0x4626, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_UPDATE", REG_MMIO, 0x4627, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4628, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_DFQ_CONTROL", REG_MMIO, 0x4629, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_DFQ_STATUS", REG_MMIO, 0x462a, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x462b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x462c, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x462d, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x462e, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x462f, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4630, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4631, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4632, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4633, NULL, 0, 0, 0 },
+	{ "mmDCP4_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4634, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_CONTROL", REG_MMIO, 0x4635, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C11_C12", REG_MMIO, 0x4636, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C13_C14", REG_MMIO, 0x4637, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C21_C22", REG_MMIO, 0x4638, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C23_C24", REG_MMIO, 0x4639, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C31_C32", REG_MMIO, 0x463a, NULL, 0, 0, 0 },
+	{ "mmDCP4_INPUT_CSC_C33_C34", REG_MMIO, 0x463b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_CONTROL", REG_MMIO, 0x463c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C11_C12", REG_MMIO, 0x463d, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C13_C14", REG_MMIO, 0x463e, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C21_C22", REG_MMIO, 0x463f, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4640, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4641, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4642, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4643, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4644, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4645, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4646, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4647, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4648, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4649, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x464a, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x464b, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x464c, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x464d, NULL, 0, 0, 0 },
+	{ "mmDCP4_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x464e, NULL, 0, 0, 0 },
+	{ "mmDCP4_DENORM_CONTROL", REG_MMIO, 0x4650, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_ROUND_CONTROL", REG_MMIO, 0x4651, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4652, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_CONTROL", REG_MMIO, 0x4653, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_ALPHA", REG_MMIO, 0x4654, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_RED", REG_MMIO, 0x4655, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_GREEN", REG_MMIO, 0x4656, NULL, 0, 0, 0 },
+	{ "mmDCP4_KEY_RANGE_BLUE", REG_MMIO, 0x4657, NULL, 0, 0, 0 },
+	{ "mmDCP4_DEGAMMA_CONTROL", REG_MMIO, 0x4658, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4659, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C11_C12", REG_MMIO, 0x465a, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C13_C14", REG_MMIO, 0x465b, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C21_C22", REG_MMIO, 0x465c, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C23_C24", REG_MMIO, 0x465d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C31_C32", REG_MMIO, 0x465e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GAMUT_REMAP_C33_C34", REG_MMIO, 0x465f, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4660, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_RANDOM_SEEDS", REG_MMIO, 0x4661, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4665, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_CONTROL", REG_MMIO, 0x4666, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4667, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SIZE", REG_MMIO, 0x4668, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4669, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_POSITION", REG_MMIO, 0x466a, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_HOT_SPOT", REG_MMIO, 0x466b, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR1", REG_MMIO, 0x466c, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_COLOR2", REG_MMIO, 0x466d, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_UPDATE", REG_MMIO, 0x466e, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_CONTROL", REG_MMIO, 0x466f, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_SURFACE_ADDRESS", REG_MMIO, 0x4670, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_SIZE", REG_MMIO, 0x4671, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4672, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_POSITION", REG_MMIO, 0x4673, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_HOT_SPOT", REG_MMIO, 0x4674, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_COLOR1", REG_MMIO, 0x4675, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_COLOR2", REG_MMIO, 0x4676, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_UPDATE", REG_MMIO, 0x4677, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_MODE", REG_MMIO, 0x4678, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_RW_INDEX", REG_MMIO, 0x4679, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_SEQ_COLOR", REG_MMIO, 0x467a, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_PWL_DATA", REG_MMIO, 0x467b, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_30_COLOR", REG_MMIO, 0x467c, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x467d, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x467e, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_AUTOFILL", REG_MMIO, 0x467f, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_CONTROL", REG_MMIO, 0x4680, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4681, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4682, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4683, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4684, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4685, NULL, 0, 0, 0 },
+	{ "mmDCP4_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4686, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CONTROL", REG_MMIO, 0x4687, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_MASK", REG_MMIO, 0x4688, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_CURRENT", REG_MMIO, 0x4689, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_CRC_LAST", REG_MMIO, 0x468b, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG", REG_MMIO, 0x468d, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x468e, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_GSL_CONTROL", REG_MMIO, 0x4690, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4691, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4692, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4693, NULL, 0, 0, 0 },
+	{ "mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4694, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4695, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4696, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4697, NULL, 0, 0, 0 },
+	{ "mmDCP4_DCP_DEBUG2", REG_MMIO, 0x4698, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4699, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR_STEREO_CONTROL", REG_MMIO, 0x469a, NULL, 0, 0, 0 },
+	{ "mmDCP4_CUR2_STEREO_CONTROL", REG_MMIO, 0x469b, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x469c, NULL, 0, 0, 0 },
+	{ "mmDCP4_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x469d, NULL, 0, 0, 0 },
+	{ "mmDCP4_HW_ROTATION", REG_MMIO, 0x469e, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x469f, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CONTROL", REG_MMIO, 0x46a0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_INDEX", REG_MMIO, 0x46a1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_DATA", REG_MMIO, 0x46a2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x46a3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x46a4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x46a5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x46a6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x46a7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x46a8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x46a9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x46aa, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x46ab, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x46ac, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x46ad, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x46ae, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x46af, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x46b0, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x46b1, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x46b2, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x46b3, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x46b4, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x46b5, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x46b6, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x46b7, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x46b8, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x46b9, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x46ba, NULL, 0, 0, 0 },
+	{ "mmDCP4_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x46bb, NULL, 0, 0, 0 },
+	{ "mmDCP4_ALPHA_CONTROL", REG_MMIO, 0x46bc, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x46bd, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x46be, NULL, 0, 0, 0 },
+	{ "mmDCP4_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x46bf, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DATA_FORMAT", REG_MMIO, 0x46c0, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_MEMORY_CTRL", REG_MMIO, 0x46c1, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x46c2, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DESKTOP_HEIGHT", REG_MMIO, 0x46c3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE_START_END", REG_MMIO, 0x46c4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE2_START_END", REG_MMIO, 0x46c5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_V_COUNTER", REG_MMIO, 0x46c6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x46c7, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_INTERRUPT_MASK", REG_MMIO, 0x46c8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE_STATUS", REG_MMIO, 0x46c9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VLINE2_STATUS", REG_MMIO, 0x46ca, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_VBLANK_STATUS", REG_MMIO, 0x46cb, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_SYNC_RESET_SEL", REG_MMIO, 0x46cc, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x46cd, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x46ce, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x46cf, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x46d0, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x46d1, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x46d2, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x46d3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x46d4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x46d5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x46d6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x46d7, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x46d8, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x46d9, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_BUFFER_STATUS", REG_MMIO, 0x46da, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x46dc, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_MODE", REG_MMIO, 0x46e0, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x46e1, NULL, 0, 0, 0 },
+	{ "mmLB4_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x46e2, NULL, 0, 0, 0 },
+	{ "mmLB4_DC_MVP_LB_CONTROL", REG_MMIO, 0x46e3, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG", REG_MMIO, 0x46e4, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG2", REG_MMIO, 0x46e5, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_DEBUG3", REG_MMIO, 0x46e6, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x46fe, NULL, 0, 0, 0 },
+	{ "mmLB4_LB_TEST_DEBUG_DATA", REG_MMIO, 0x46ff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_H", REG_SMC, 0x47, &ixDP_AUX4_DEBUG_H[0], sizeof(ixDP_AUX4_DEBUG_H)/sizeof(ixDP_AUX4_DEBUG_H[0]), 0, 0 },
+	{ "mmDC_PERFMON6_PERFCOUNTER_CNTL", REG_MMIO, 0x4724, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFCOUNTER_STATE", REG_MMIO, 0x4725, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4726, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CNTL", REG_MMIO, 0x4727, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_CVALUE_LOW", REG_MMIO, 0x4728, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_HI", REG_MMIO, 0x4729, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_LOW", REG_MMIO, 0x472a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x472b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON6_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x472c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4730, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4731, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4732, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4733, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4734, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4735, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4736, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4737, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4738, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4739, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_REPEATER_PROGRAM", REG_MMIO, 0x473a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_A", REG_MMIO, 0x473b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG4_DPG_HW_DEBUG_B", REG_MMIO, 0x473c, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4740, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4741, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE", REG_MMIO, 0x4742, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TAP_CONTROL", REG_MMIO, 0x4743, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_CONTROL", REG_MMIO, 0x4744, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_BYPASS_CONTROL", REG_MMIO, 0x4745, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4746, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4747, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4748, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4749, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x474a, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x474b, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x474c, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT", REG_MMIO, 0x474d, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x474e, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ROUND_OFFSET", REG_MMIO, 0x474f, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_UPDATE", REG_MMIO, 0x4751, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4753, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_ALU_CONTROL", REG_MMIO, 0x4754, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4755, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_START", REG_MMIO, 0x475c, NULL, 0, 0, 0 },
+	{ "mmSCL4_VIEWPORT_SIZE", REG_MMIO, 0x475d, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x475e, NULL, 0, 0, 0 },
+	{ "mmSCL4_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x475f, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4760, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4761, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4762, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4763, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG2", REG_MMIO, 0x4769, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_DEBUG", REG_MMIO, 0x476a, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x476b, NULL, 0, 0, 0 },
+	{ "mmSCL4_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x476c, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_CONTROL", REG_MMIO, 0x476d, NULL, 0, 0, 0 },
+	{ "mmBLND4_SM_CONTROL2", REG_MMIO, 0x476e, NULL, 0, 0, 0 },
+	{ "mmBLND4_PTI_CONTROL", REG_MMIO, 0x476f, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_UPDATE", REG_MMIO, 0x4770, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4771, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4773, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_DEBUG", REG_MMIO, 0x4774, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4775, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4776, NULL, 0, 0, 0 },
+	{ "mmBLND4_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4777, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4778, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4779, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_WINDOW", REG_MMIO, 0x477a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_GSL_CONTROL", REG_MMIO, 0x477b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x477c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x477d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_DCFE_DBG_SEL", REG_MMIO, 0x477e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x477f, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_TOTAL", REG_MMIO, 0x4780, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_BLANK_START_END", REG_MMIO, 0x4781, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A", REG_MMIO, 0x4782, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4783, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B", REG_MMIO, 0x4784, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4785, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VBI_END", REG_MMIO, 0x4786, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL", REG_MMIO, 0x4787, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4788, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4789, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x478a, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x478b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x478c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_BLANK_START_END", REG_MMIO, 0x478d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A", REG_MMIO, 0x478e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x478f, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B", REG_MMIO, 0x4790, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4791, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4792, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4793, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_CNTL", REG_MMIO, 0x4794, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4795, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_CNTL", REG_MMIO, 0x4796, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4797, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4798, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FLOW_CONTROL", REG_MMIO, 0x4799, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x479b, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CONTROL", REG_MMIO, 0x479c, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_CONTROL", REG_MMIO, 0x479d, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x479e, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERLACE_STATUS", REG_MMIO, 0x479f, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x47a0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x47a1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x47a2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS", REG_MMIO, 0x47a3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_POSITION", REG_MMIO, 0x47a4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x47a5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x47a6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x47a7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x47a8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_CONTROL", REG_MMIO, 0x47a9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_COUNT_RESET", REG_MMIO, 0x47aa, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x47ab, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x47ac, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_STATUS", REG_MMIO, 0x47ad, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STEREO_CONTROL", REG_MMIO, 0x47ae, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x47af, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x47b0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x47b1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x47b2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_START_LINE_CONTROL", REG_MMIO, 0x47b3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x47b4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_UPDATE_LOCK", REG_MMIO, 0x47b5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x47b6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x47b7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x47ba, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x47bb, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x47bc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_MASTER_UPDATE_LOCK", REG_MMIO, 0x47bd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_MASTER_UPDATE_MODE", REG_MMIO, 0x47be, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x47bf, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x47c0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MVP_STATUS", REG_MMIO, 0x47c1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_MASTER_EN", REG_MMIO, 0x47c2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x47c3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x47c4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x47c6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x47c7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x47c8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x47c9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x47ca, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x47cb, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR", REG_MMIO, 0x47cc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x47cd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x47ce, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x47cf, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x47d0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x47d1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x47d2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x47d3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC_CNTL", REG_MMIO, 0x47d4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x47d5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x47d6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x47d7, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x47d8, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_DATA_RG", REG_MMIO, 0x47d9, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC0_DATA_B", REG_MMIO, 0x47da, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x47db, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x47dc, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x47dd, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x47de, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_DATA_RG", REG_MMIO, 0x47df, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_CRC1_DATA_B", REG_MMIO, 0x47e0, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x47e1, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x47e2, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x47e3, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x47e4, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x47e5, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x47e6, NULL, 0, 0, 0 },
+	{ "mmCRTC4_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x47e7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x47e8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x47e9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x47ea, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x47eb, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x47ec, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x47ed, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CONTROL", REG_MMIO, 0x47ee, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x47ef, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_DATA_0_1", REG_MMIO, 0x47f0, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_FORCE_DATA_2_3", REG_MMIO, 0x47f1, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x47f2, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x47f3, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x47f4, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x47f5, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x47f6, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x47f7, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x47f8, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CLAMP_CNTL", REG_MMIO, 0x47f9, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_CNTL", REG_MMIO, 0x47fa, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x47fb, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x47fc, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x47fd, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x47fe, NULL, 0, 0, 0 },
+	{ "mmFMT4_FMT_DEBUG_CNTL", REG_MMIO, 0x47ff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_I", REG_SMC, 0x48, &ixDP_AUX4_DEBUG_I[0], sizeof(ixDP_AUX4_DEBUG_I)/sizeof(ixDP_AUX4_DEBUG_I[0]), 0, 0 },
+	{ "mmDIG4_DIG_FE_CNTL", REG_MMIO, 0x4800, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4801, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4802, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_CLOCK_PATTERN", REG_MMIO, 0x4803, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_TEST_PATTERN", REG_MMIO, 0x4804, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4805, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4808, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4809, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_FIFO_STATUS", REG_MMIO, 0x480a, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_CONTROL", REG_MMIO, 0x480c, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_STATUS", REG_MMIO, 0x480d, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x480e, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x480f, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4810, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4811, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4812, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4813, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4814, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GC", REG_MMIO, 0x4816, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4817, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_0", REG_MMIO, 0x4818, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_1", REG_MMIO, 0x4819, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_2", REG_MMIO, 0x481a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_3", REG_MMIO, 0x481b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC1_4", REG_MMIO, 0x481c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_0", REG_MMIO, 0x481d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_1", REG_MMIO, 0x481e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_2", REG_MMIO, 0x481f, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_ISRC2_3", REG_MMIO, 0x4820, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO0", REG_MMIO, 0x4821, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO1", REG_MMIO, 0x4822, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO2", REG_MMIO, 0x4823, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AVI_INFO3", REG_MMIO, 0x4824, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO0", REG_MMIO, 0x4825, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_MPEG_INFO1", REG_MMIO, 0x4826, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_HDR", REG_MMIO, 0x4827, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_0", REG_MMIO, 0x4828, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_1", REG_MMIO, 0x4829, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_2", REG_MMIO, 0x482a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_3", REG_MMIO, 0x482b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_4", REG_MMIO, 0x482c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_5", REG_MMIO, 0x482d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_6", REG_MMIO, 0x482e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_GENERIC_7", REG_MMIO, 0x482f, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4830, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_0", REG_MMIO, 0x4837, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_32_1", REG_MMIO, 0x4838, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_0", REG_MMIO, 0x4839, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_44_1", REG_MMIO, 0x483a, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_0", REG_MMIO, 0x483b, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_48_1", REG_MMIO, 0x483c, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_0", REG_MMIO, 0x483d, NULL, 0, 0, 0 },
+	{ "mmDIG4_HDMI_ACR_STATUS_1", REG_MMIO, 0x483e, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO0", REG_MMIO, 0x483f, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_INFO1", REG_MMIO, 0x4840, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_0", REG_MMIO, 0x4841, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_1", REG_MMIO, 0x4842, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4843, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4844, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4845, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4846, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4847, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_60958_2", REG_MMIO, 0x4848, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4849, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_STATUS", REG_MMIO, 0x484a, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x484b, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x484c, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x484d, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x484f, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_CNTL", REG_MMIO, 0x4850, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_BE_EN_CNTL", REG_MMIO, 0x4851, NULL, 0, 0, 0 },
+	{ "mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4852, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CNTL", REG_MMIO, 0x487c, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL_CHAR", REG_MMIO, 0x487d, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x487e, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x487f, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4880, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4881, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DEBUG", REG_MMIO, 0x4882, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL_BITS", REG_MMIO, 0x4883, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4884, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4886, NULL, 0, 0, 0 },
+	{ "mmDIG4_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4887, NULL, 0, 0, 0 },
+	{ "mmDIG4_LVDS_DATA_CNTL", REG_MMIO, 0x488c, NULL, 0, 0, 0 },
+	{ "mmDIG4_DIG_LANE_ENABLE", REG_MMIO, 0x488d, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL", REG_MMIO, 0x48a0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING1", REG_MMIO, 0x48a1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING2", REG_MMIO, 0x48a2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING3", REG_MMIO, 0x48a3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_FRAMING4", REG_MMIO, 0x48a4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N", REG_MMIO, 0x48a5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x48a6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M", REG_MMIO, 0x48a7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x48a8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_TIMESTAMP", REG_MMIO, 0x48a9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_PACKET_CNTL", REG_MMIO, 0x48aa, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_SEC_CNTL1", REG_MMIO, 0x48ab, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_CNTL", REG_MMIO, 0x48c0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_PIXEL_FORMAT", REG_MMIO, 0x48c1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_CONFIG", REG_MMIO, 0x48c2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_STREAM_CNTL", REG_MMIO, 0x48c3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_STEER_FIFO", REG_MMIO, 0x48c4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_MISC", REG_MMIO, 0x48c5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x48c6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x48c7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x48c8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_TIMING", REG_MMIO, 0x48c9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_N", REG_MMIO, 0x48ca, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_M", REG_MMIO, 0x48cb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x48cc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_MSA_VBID", REG_MMIO, 0x48cd, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x48ce, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x48cf, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CNTL", REG_MMIO, 0x48d0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x48d1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM0", REG_MMIO, 0x48d2, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x48d3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x48d4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x48d5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_EN", REG_MMIO, 0x48d6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_CNTL", REG_MMIO, 0x48d7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_CRC_RESULT", REG_MMIO, 0x48d8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_COLORIMETRY", REG_MMIO, 0x48da, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_MISC_CNTL", REG_MMIO, 0x48db, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM2", REG_MMIO, 0x48df, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_SYM1", REG_MMIO, 0x48e0, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_CNTL", REG_MMIO, 0x48e1, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_RATE_UPDATE", REG_MMIO, 0x48e3, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT0", REG_MMIO, 0x48e4, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT1", REG_MMIO, 0x48e5, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT2", REG_MMIO, 0x48e6, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_SAT_UPDATE", REG_MMIO, 0x48e7, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSE_LINK_TIMING", REG_MMIO, 0x48e8, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x48e9, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x48ea, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x48eb, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x48fc, NULL, 0, 0, 0 },
+	{ "mmDP4_DP_TEST_DEBUG_DATA", REG_MMIO, 0x48fd, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_J", REG_SMC, 0x49, &ixDP_AUX4_DEBUG_J[0], sizeof(ixDP_AUX4_DEBUG_J)/sizeof(ixDP_AUX4_DEBUG_J[0]), 0, 0 },
+	{ "mmDCP5_GRPH_ENABLE", REG_MMIO, 0x4900, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_CONTROL", REG_MMIO, 0x4901, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_LUT_10BIT_BYPASS", REG_MMIO, 0x4902, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SWAP_CNTL", REG_MMIO, 0x4903, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS", REG_MMIO, 0x4904, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4905, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PITCH", REG_MMIO, 0x4906, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4907, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4908, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_X", REG_MMIO, 0x4909, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_OFFSET_Y", REG_MMIO, 0x490a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_START", REG_MMIO, 0x490b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_START", REG_MMIO, 0x490c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_X_END", REG_MMIO, 0x490d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_Y_END", REG_MMIO, 0x490e, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_GAMMA_CONTROL", REG_MMIO, 0x4910, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_UPDATE", REG_MMIO, 0x4911, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_CONTROL", REG_MMIO, 0x4912, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4913, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_CONTROL", REG_MMIO, 0x4914, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_DFQ_STATUS", REG_MMIO, 0x4915, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_STATUS", REG_MMIO, 0x4916, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_INTERRUPT_CONTROL", REG_MMIO, 0x4917, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x4918, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS", REG_MMIO, 0x4919, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_PITCH", REG_MMIO, 0x491a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x491b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_ENABLE", REG_MMIO, 0x491c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_CONTROL1", REG_MMIO, 0x491d, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_CONTROL2", REG_MMIO, 0x491e, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SWAP_CNTL", REG_MMIO, 0x491f, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS", REG_MMIO, 0x4920, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_PITCH", REG_MMIO, 0x4921, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4922, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_OFFSET_X", REG_MMIO, 0x4923, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_OFFSET_Y", REG_MMIO, 0x4924, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_START", REG_MMIO, 0x4925, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_END", REG_MMIO, 0x4926, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_UPDATE", REG_MMIO, 0x4927, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_INUSE", REG_MMIO, 0x4928, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_DFQ_CONTROL", REG_MMIO, 0x4929, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_DFQ_STATUS", REG_MMIO, 0x492a, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE", REG_MMIO, 0x492b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVLSCL_EDGE_PIXEL_CNTL", REG_MMIO, 0x492c, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_GRPH_CONTROL", REG_MMIO, 0x492d, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_R", REG_MMIO, 0x492e, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_G", REG_MMIO, 0x492f, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_GRPH_B", REG_MMIO, 0x4930, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_OVL_CONTROL", REG_MMIO, 0x4931, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_CB", REG_MMIO, 0x4932, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_Y", REG_MMIO, 0x4933, NULL, 0, 0, 0 },
+	{ "mmDCP5_PRESCALE_VALUES_OVL_CR", REG_MMIO, 0x4934, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_CONTROL", REG_MMIO, 0x4935, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C11_C12", REG_MMIO, 0x4936, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C13_C14", REG_MMIO, 0x4937, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C21_C22", REG_MMIO, 0x4938, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C23_C24", REG_MMIO, 0x4939, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C31_C32", REG_MMIO, 0x493a, NULL, 0, 0, 0 },
+	{ "mmDCP5_INPUT_CSC_C33_C34", REG_MMIO, 0x493b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_CONTROL", REG_MMIO, 0x493c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C11_C12", REG_MMIO, 0x493d, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C13_C14", REG_MMIO, 0x493e, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C21_C22", REG_MMIO, 0x493f, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C23_C24", REG_MMIO, 0x4940, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C31_C32", REG_MMIO, 0x4941, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUTPUT_CSC_C33_C34", REG_MMIO, 0x4942, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C11_C12", REG_MMIO, 0x4943, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C13_C14", REG_MMIO, 0x4944, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C21_C22", REG_MMIO, 0x4945, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C23_C24", REG_MMIO, 0x4946, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C31_C32", REG_MMIO, 0x4947, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXA_TRANS_C33_C34", REG_MMIO, 0x4948, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C11_C12", REG_MMIO, 0x4949, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C13_C14", REG_MMIO, 0x494a, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C21_C22", REG_MMIO, 0x494b, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C23_C24", REG_MMIO, 0x494c, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C31_C32", REG_MMIO, 0x494d, NULL, 0, 0, 0 },
+	{ "mmDCP5_COMM_MATRIXB_TRANS_C33_C34", REG_MMIO, 0x494e, NULL, 0, 0, 0 },
+	{ "mmDCP5_DENORM_CONTROL", REG_MMIO, 0x4950, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_ROUND_CONTROL", REG_MMIO, 0x4951, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_R_CR", REG_MMIO, 0x4952, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_CONTROL", REG_MMIO, 0x4953, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_ALPHA", REG_MMIO, 0x4954, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_RED", REG_MMIO, 0x4955, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_GREEN", REG_MMIO, 0x4956, NULL, 0, 0, 0 },
+	{ "mmDCP5_KEY_RANGE_BLUE", REG_MMIO, 0x4957, NULL, 0, 0, 0 },
+	{ "mmDCP5_DEGAMMA_CONTROL", REG_MMIO, 0x4958, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_CONTROL", REG_MMIO, 0x4959, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C11_C12", REG_MMIO, 0x495a, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C13_C14", REG_MMIO, 0x495b, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C21_C22", REG_MMIO, 0x495c, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C23_C24", REG_MMIO, 0x495d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C31_C32", REG_MMIO, 0x495e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GAMUT_REMAP_C33_C34", REG_MMIO, 0x495f, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_SPATIAL_DITHER_CNTL", REG_MMIO, 0x4960, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_RANDOM_SEEDS", REG_MMIO, 0x4961, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_FP_CONVERTED_FIELD", REG_MMIO, 0x4965, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_CONTROL", REG_MMIO, 0x4966, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS", REG_MMIO, 0x4967, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SIZE", REG_MMIO, 0x4968, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4969, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_POSITION", REG_MMIO, 0x496a, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_HOT_SPOT", REG_MMIO, 0x496b, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR1", REG_MMIO, 0x496c, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_COLOR2", REG_MMIO, 0x496d, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_UPDATE", REG_MMIO, 0x496e, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_CONTROL", REG_MMIO, 0x496f, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_SURFACE_ADDRESS", REG_MMIO, 0x4970, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_SIZE", REG_MMIO, 0x4971, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4972, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_POSITION", REG_MMIO, 0x4973, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_HOT_SPOT", REG_MMIO, 0x4974, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_COLOR1", REG_MMIO, 0x4975, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_COLOR2", REG_MMIO, 0x4976, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_UPDATE", REG_MMIO, 0x4977, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_MODE", REG_MMIO, 0x4978, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_RW_INDEX", REG_MMIO, 0x4979, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_SEQ_COLOR", REG_MMIO, 0x497a, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_PWL_DATA", REG_MMIO, 0x497b, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_30_COLOR", REG_MMIO, 0x497c, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_VGA_ACCESS_ENABLE", REG_MMIO, 0x497d, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WRITE_EN_MASK", REG_MMIO, 0x497e, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_AUTOFILL", REG_MMIO, 0x497f, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_CONTROL", REG_MMIO, 0x4980, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_BLUE", REG_MMIO, 0x4981, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_GREEN", REG_MMIO, 0x4982, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_BLACK_OFFSET_RED", REG_MMIO, 0x4983, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_BLUE", REG_MMIO, 0x4984, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_GREEN", REG_MMIO, 0x4985, NULL, 0, 0, 0 },
+	{ "mmDCP5_DC_LUT_WHITE_OFFSET_RED", REG_MMIO, 0x4986, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CONTROL", REG_MMIO, 0x4987, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_MASK", REG_MMIO, 0x4988, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_CURRENT", REG_MMIO, 0x4989, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_CRC_LAST", REG_MMIO, 0x498b, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG", REG_MMIO, 0x498d, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_FLIP_RATE_CNTL", REG_MMIO, 0x498e, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_GSL_CONTROL", REG_MMIO, 0x4990, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK", REG_MMIO, 0x4991, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS", REG_MMIO, 0x4992, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_STEREOSYNC_FLIP", REG_MMIO, 0x4993, NULL, 0, 0, 0 },
+	{ "mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x4994, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_INDEX", REG_MMIO, 0x4995, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_TEST_DEBUG_DATA", REG_MMIO, 0x4996, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_STEREOSYNC_FLIP", REG_MMIO, 0x4997, NULL, 0, 0, 0 },
+	{ "mmDCP5_DCP_DEBUG2", REG_MMIO, 0x4998, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_REQUEST_FILTER_CNTL", REG_MMIO, 0x4999, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR_STEREO_CONTROL", REG_MMIO, 0x499a, NULL, 0, 0, 0 },
+	{ "mmDCP5_CUR2_STEREO_CONTROL", REG_MMIO, 0x499b, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_G_Y", REG_MMIO, 0x499c, NULL, 0, 0, 0 },
+	{ "mmDCP5_OUT_CLAMP_CONTROL_B_CB", REG_MMIO, 0x499d, NULL, 0, 0, 0 },
+	{ "mmDCP5_HW_ROTATION", REG_MMIO, 0x499e, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_CNTL", REG_MMIO, 0x499f, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CONTROL", REG_MMIO, 0x49a0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_INDEX", REG_MMIO, 0x49a1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_DATA", REG_MMIO, 0x49a2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_LUT_WRITE_EN_MASK", REG_MMIO, 0x49a3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_START_CNTL", REG_MMIO, 0x49a4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL", REG_MMIO, 0x49a5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL1", REG_MMIO, 0x49a6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_END_CNTL2", REG_MMIO, 0x49a7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_0_1", REG_MMIO, 0x49a8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_2_3", REG_MMIO, 0x49a9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_4_5", REG_MMIO, 0x49aa, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_6_7", REG_MMIO, 0x49ab, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_8_9", REG_MMIO, 0x49ac, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_10_11", REG_MMIO, 0x49ad, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_12_13", REG_MMIO, 0x49ae, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLA_REGION_14_15", REG_MMIO, 0x49af, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_START_CNTL", REG_MMIO, 0x49b0, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL", REG_MMIO, 0x49b1, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL1", REG_MMIO, 0x49b2, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_END_CNTL2", REG_MMIO, 0x49b3, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_0_1", REG_MMIO, 0x49b4, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_2_3", REG_MMIO, 0x49b5, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_4_5", REG_MMIO, 0x49b6, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_6_7", REG_MMIO, 0x49b7, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_8_9", REG_MMIO, 0x49b8, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_10_11", REG_MMIO, 0x49b9, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_12_13", REG_MMIO, 0x49ba, NULL, 0, 0, 0 },
+	{ "mmDCP5_REGAMMA_CNTLB_REGION_14_15", REG_MMIO, 0x49bb, NULL, 0, 0, 0 },
+	{ "mmDCP5_ALPHA_CONTROL", REG_MMIO, 0x49bc, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS", REG_MMIO, 0x49bd, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_RECOVERY_SURFACE_ADDRESS_HIGH", REG_MMIO, 0x49be, NULL, 0, 0, 0 },
+	{ "mmDCP5_GRPH_XDMA_CACHE_UNDERFLOW_DET_STATUS", REG_MMIO, 0x49bf, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DATA_FORMAT", REG_MMIO, 0x49c0, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_MEMORY_CTRL", REG_MMIO, 0x49c1, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_MEMORY_SIZE_STATUS", REG_MMIO, 0x49c2, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DESKTOP_HEIGHT", REG_MMIO, 0x49c3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE_START_END", REG_MMIO, 0x49c4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE2_START_END", REG_MMIO, 0x49c5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_V_COUNTER", REG_MMIO, 0x49c6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SNAPSHOT_V_COUNTER", REG_MMIO, 0x49c7, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_INTERRUPT_MASK", REG_MMIO, 0x49c8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE_STATUS", REG_MMIO, 0x49c9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VLINE2_STATUS", REG_MMIO, 0x49ca, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_VBLANK_STATUS", REG_MMIO, 0x49cb, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_SYNC_RESET_SEL", REG_MMIO, 0x49cc, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_R_CR", REG_MMIO, 0x49cd, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_G_Y", REG_MMIO, 0x49ce, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BLACK_KEYER_B_CB", REG_MMIO, 0x49cf, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_CTRL", REG_MMIO, 0x49d0, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_R_CR", REG_MMIO, 0x49d1, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_G_Y", REG_MMIO, 0x49d2, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_B_CB", REG_MMIO, 0x49d3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_R_CR", REG_MMIO, 0x49d4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_G_Y", REG_MMIO, 0x49d5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_KEYER_COLOR_REP_B_CB", REG_MMIO, 0x49d6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_LEVEL_STATUS", REG_MMIO, 0x49d7, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_URGENCY_CTRL", REG_MMIO, 0x49d8, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_URGENCY_STATUS", REG_MMIO, 0x49d9, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_BUFFER_STATUS", REG_MMIO, 0x49da, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_NO_OUTSTANDING_REQ_STATUS", REG_MMIO, 0x49dc, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_MODE", REG_MMIO, 0x49e0, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_AFR_FLIP_FIFO_CNTL", REG_MMIO, 0x49e1, NULL, 0, 0, 0 },
+	{ "mmLB5_MVP_FLIP_LINE_NUM_INSERT", REG_MMIO, 0x49e2, NULL, 0, 0, 0 },
+	{ "mmLB5_DC_MVP_LB_CONTROL", REG_MMIO, 0x49e3, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG", REG_MMIO, 0x49e4, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG2", REG_MMIO, 0x49e5, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_DEBUG3", REG_MMIO, 0x49e6, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_INDEX", REG_MMIO, 0x49fe, NULL, 0, 0, 0 },
+	{ "mmLB5_LB_TEST_DEBUG_DATA", REG_MMIO, 0x49ff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_K", REG_SMC, 0x4a, &ixDP_AUX4_DEBUG_K[0], sizeof(ixDP_AUX4_DEBUG_K)/sizeof(ixDP_AUX4_DEBUG_K[0]), 0, 0 },
+	{ "mmDC_PERFMON7_PERFCOUNTER_CNTL", REG_MMIO, 0x4a24, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFCOUNTER_STATE", REG_MMIO, 0x4a25, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4a26, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CNTL", REG_MMIO, 0x4a27, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_CVALUE_LOW", REG_MMIO, 0x4a28, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_HI", REG_MMIO, 0x4a29, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_LOW", REG_MMIO, 0x4a2a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x4a2b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON7_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x4a2c, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1", REG_MMIO, 0x4a30, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2", REG_MMIO, 0x4a31, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL", REG_MMIO, 0x4a32, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL", REG_MMIO, 0x4a33, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_DPM_CONTROL", REG_MMIO, 0x4a34, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL", REG_MMIO, 0x4a35, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL", REG_MMIO, 0x4a36, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH", REG_MMIO, 0x4a37, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_INDEX", REG_MMIO, 0x4a38, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_TEST_DEBUG_DATA", REG_MMIO, 0x4a39, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_REPEATER_PROGRAM", REG_MMIO, 0x4a3a, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_A", REG_MMIO, 0x4a3b, NULL, 0, 0, 0 },
+	{ "mmDMIF_PG5_DPG_HW_DEBUG_B", REG_MMIO, 0x4a3c, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_SELECT", REG_MMIO, 0x4a40, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4a41, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE", REG_MMIO, 0x4a42, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TAP_CONTROL", REG_MMIO, 0x4a43, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_CONTROL", REG_MMIO, 0x4a44, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_BYPASS_CONTROL", REG_MMIO, 0x4a45, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MANUAL_REPLICATE_CONTROL", REG_MMIO, 0x4a46, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_AUTOMATIC_MODE_CONTROL", REG_MMIO, 0x4a47, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_CONTROL", REG_MMIO, 0x4a48, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4a49, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_HORZ_FILTER_INIT", REG_MMIO, 0x4a4a, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_CONTROL", REG_MMIO, 0x4a4b, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x4a4c, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT", REG_MMIO, 0x4a4d, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_VERT_FILTER_INIT_BOT", REG_MMIO, 0x4a4e, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ROUND_OFFSET", REG_MMIO, 0x4a4f, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_UPDATE", REG_MMIO, 0x4a51, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_F_SHARP_CONTROL", REG_MMIO, 0x4a53, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_ALU_CONTROL", REG_MMIO, 0x4a54, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4a55, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_START", REG_MMIO, 0x4a5c, NULL, 0, 0, 0 },
+	{ "mmSCL5_VIEWPORT_SIZE", REG_MMIO, 0x4a5d, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_LEFT_RIGHT", REG_MMIO, 0x4a5e, NULL, 0, 0, 0 },
+	{ "mmSCL5_EXT_OVERSCAN_TOP_BOTTOM", REG_MMIO, 0x4a5f, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET1", REG_MMIO, 0x4a60, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET2", REG_MMIO, 0x4a61, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_DET3", REG_MMIO, 0x4a62, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_MODE_CHANGE_MASK", REG_MMIO, 0x4a63, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG2", REG_MMIO, 0x4a69, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_DEBUG", REG_MMIO, 0x4a6a, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_INDEX", REG_MMIO, 0x4a6b, NULL, 0, 0, 0 },
+	{ "mmSCL5_SCL_TEST_DEBUG_DATA", REG_MMIO, 0x4a6c, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_CONTROL", REG_MMIO, 0x4a6d, NULL, 0, 0, 0 },
+	{ "mmBLND5_SM_CONTROL2", REG_MMIO, 0x4a6e, NULL, 0, 0, 0 },
+	{ "mmBLND5_PTI_CONTROL", REG_MMIO, 0x4a6f, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_UPDATE", REG_MMIO, 0x4a70, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_UNDERFLOW_INTERRUPT", REG_MMIO, 0x4a71, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_V_UPDATE_LOCK", REG_MMIO, 0x4a73, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_DEBUG", REG_MMIO, 0x4a74, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_TEST_DEBUG_INDEX", REG_MMIO, 0x4a75, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_TEST_DEBUG_DATA", REG_MMIO, 0x4a76, NULL, 0, 0, 0 },
+	{ "mmBLND5_BLND_REG_UPDATE_STATUS", REG_MMIO, 0x4a77, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_3D_STRUCTURE_CONTROL", REG_MMIO, 0x4a78, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_VSYNC_GAP", REG_MMIO, 0x4a79, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_WINDOW", REG_MMIO, 0x4a7a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_GSL_CONTROL", REG_MMIO, 0x4a7b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DCFE_CLOCK_CONTROL", REG_MMIO, 0x4a7c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_EARLY_NUM", REG_MMIO, 0x4a7d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_DCFE_DBG_SEL", REG_MMIO, 0x4a7e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL", REG_MMIO, 0x4a7f, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_TOTAL", REG_MMIO, 0x4a80, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_BLANK_START_END", REG_MMIO, 0x4a81, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A", REG_MMIO, 0x4a82, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_A_CNTL", REG_MMIO, 0x4a83, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B", REG_MMIO, 0x4a84, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_H_SYNC_B_CNTL", REG_MMIO, 0x4a85, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VBI_END", REG_MMIO, 0x4a86, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL", REG_MMIO, 0x4a87, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MIN", REG_MMIO, 0x4a88, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_MAX", REG_MMIO, 0x4a89, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_CONTROL", REG_MMIO, 0x4a8a, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_TOTAL_INT_STATUS", REG_MMIO, 0x4a8b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS", REG_MMIO, 0x4a8c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_BLANK_START_END", REG_MMIO, 0x4a8d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A", REG_MMIO, 0x4a8e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_A_CNTL", REG_MMIO, 0x4a8f, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B", REG_MMIO, 0x4a90, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_SYNC_B_CNTL", REG_MMIO, 0x4a91, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_CNTL", REG_MMIO, 0x4a92, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DTMTEST_STATUS_POSITION", REG_MMIO, 0x4a93, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_CNTL", REG_MMIO, 0x4a94, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGA_MANUAL_TRIG", REG_MMIO, 0x4a95, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_CNTL", REG_MMIO, 0x4a96, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TRIGB_MANUAL_TRIG", REG_MMIO, 0x4a97, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL", REG_MMIO, 0x4a98, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FLOW_CONTROL", REG_MMIO, 0x4a99, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE", REG_MMIO, 0x4a9b, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CONTROL", REG_MMIO, 0x4a9c, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_CONTROL", REG_MMIO, 0x4a9d, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_CONTROL", REG_MMIO, 0x4a9e, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERLACE_STATUS", REG_MMIO, 0x4a9f, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_FIELD_INDICATION_CONTROL", REG_MMIO, 0x4aa0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_PIXEL_DATA_READBACK0", REG_MMIO, 0x4aa1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_PIXEL_DATA_READBACK1", REG_MMIO, 0x4aa2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS", REG_MMIO, 0x4aa3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_POSITION", REG_MMIO, 0x4aa4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_NOM_VERT_POSITION", REG_MMIO, 0x4aa5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_FRAME_COUNT", REG_MMIO, 0x4aa6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_VF_COUNT", REG_MMIO, 0x4aa7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATUS_HV_COUNT", REG_MMIO, 0x4aa8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_CONTROL", REG_MMIO, 0x4aa9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_COUNT_RESET", REG_MMIO, 0x4aaa, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", REG_MMIO, 0x4aab, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERT_SYNC_CONTROL", REG_MMIO, 0x4aac, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_STATUS", REG_MMIO, 0x4aad, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STEREO_CONTROL", REG_MMIO, 0x4aae, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_STATUS", REG_MMIO, 0x4aaf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_CONTROL", REG_MMIO, 0x4ab0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_POSITION", REG_MMIO, 0x4ab1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_SNAPSHOT_FRAME", REG_MMIO, 0x4ab2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_START_LINE_CONTROL", REG_MMIO, 0x4ab3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_INTERRUPT_CONTROL", REG_MMIO, 0x4ab4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_UPDATE_LOCK", REG_MMIO, 0x4ab5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL", REG_MMIO, 0x4ab6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE", REG_MMIO, 0x4ab7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_CONTROL", REG_MMIO, 0x4aba, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS", REG_MMIO, 0x4abb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_PATTERN_COLOR", REG_MMIO, 0x4abc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_MASTER_UPDATE_LOCK", REG_MMIO, 0x4abd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_MASTER_UPDATE_MODE", REG_MMIO, 0x4abe, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT", REG_MMIO, 0x4abf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER", REG_MMIO, 0x4ac0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MVP_STATUS", REG_MMIO, 0x4ac1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_MASTER_EN", REG_MMIO, 0x4ac2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT", REG_MMIO, 0x4ac3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_V_UPDATE_INT_STATUS", REG_MMIO, 0x4ac4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_INDEX", REG_MMIO, 0x4ac6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_TEST_DEBUG_DATA", REG_MMIO, 0x4ac7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR", REG_MMIO, 0x4ac8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_OVERSCAN_COLOR_EXT", REG_MMIO, 0x4ac9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR", REG_MMIO, 0x4aca, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLANK_DATA_COLOR_EXT", REG_MMIO, 0x4acb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR", REG_MMIO, 0x4acc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_BLACK_COLOR_EXT", REG_MMIO, 0x4acd, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT0_POSITION", REG_MMIO, 0x4ace, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT0_CONTROL", REG_MMIO, 0x4acf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT1_POSITION", REG_MMIO, 0x4ad0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT1_CONTROL", REG_MMIO, 0x4ad1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT2_POSITION", REG_MMIO, 0x4ad2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_VERTICAL_INTERRUPT2_CONTROL", REG_MMIO, 0x4ad3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC_CNTL", REG_MMIO, 0x4ad4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWA_X_CONTROL", REG_MMIO, 0x4ad5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWA_Y_CONTROL", REG_MMIO, 0x4ad6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWB_X_CONTROL", REG_MMIO, 0x4ad7, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_WINDOWB_Y_CONTROL", REG_MMIO, 0x4ad8, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_DATA_RG", REG_MMIO, 0x4ad9, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC0_DATA_B", REG_MMIO, 0x4ada, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWA_X_CONTROL", REG_MMIO, 0x4adb, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWA_Y_CONTROL", REG_MMIO, 0x4adc, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWB_X_CONTROL", REG_MMIO, 0x4add, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_WINDOWB_Y_CONTROL", REG_MMIO, 0x4ade, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_DATA_RG", REG_MMIO, 0x4adf, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_CRC1_DATA_B", REG_MMIO, 0x4ae0, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_CONTROL", REG_MMIO, 0x4ae1, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_START", REG_MMIO, 0x4ae2, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_WINDOW_END", REG_MMIO, 0x4ae3, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL", REG_MMIO, 0x4ae4, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_INTERRUPT_CONTROL", REG_MMIO, 0x4ae5, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL", REG_MMIO, 0x4ae6, NULL, 0, 0, 0 },
+	{ "mmCRTC5_CRTC_STATIC_SCREEN_CONTROL", REG_MMIO, 0x4ae7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_R", REG_MMIO, 0x4ae8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_G", REG_MMIO, 0x4ae9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_COMPONENT_B", REG_MMIO, 0x4aea, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_INDEX", REG_MMIO, 0x4aeb, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEST_DEBUG_DATA", REG_MMIO, 0x4aec, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DYNAMIC_EXP_CNTL", REG_MMIO, 0x4aed, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CONTROL", REG_MMIO, 0x4aee, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_OUTPUT_CNTL", REG_MMIO, 0x4aef, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_DATA_0_1", REG_MMIO, 0x4af0, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_FORCE_DATA_2_3", REG_MMIO, 0x4af1, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_BIT_DEPTH_CONTROL", REG_MMIO, 0x4af2, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_R_SEED", REG_MMIO, 0x4af3, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_G_SEED", REG_MMIO, 0x4af4, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DITHER_RAND_B_SEED", REG_MMIO, 0x4af5, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL", REG_MMIO, 0x4af6, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX", REG_MMIO, 0x4af7, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX", REG_MMIO, 0x4af8, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CLAMP_CNTL", REG_MMIO, 0x4af9, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_CNTL", REG_MMIO, 0x4afa, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK", REG_MMIO, 0x4afb, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK", REG_MMIO, 0x4afc, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_RED_GREEN", REG_MMIO, 0x4afd, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_CRC_SIG_BLUE_CONTROL", REG_MMIO, 0x4afe, NULL, 0, 0, 0 },
+	{ "mmFMT5_FMT_DEBUG_CNTL", REG_MMIO, 0x4aff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_L", REG_SMC, 0x4b, &ixDP_AUX4_DEBUG_L[0], sizeof(ixDP_AUX4_DEBUG_L)/sizeof(ixDP_AUX4_DEBUG_L[0]), 0, 0 },
+	{ "mmDIG5_DIG_FE_CNTL", REG_MMIO, 0x4b00, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4b01, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4b02, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_CLOCK_PATTERN", REG_MMIO, 0x4b03, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_TEST_PATTERN", REG_MMIO, 0x4b04, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4b05, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4b08, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4b09, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_FIFO_STATUS", REG_MMIO, 0x4b0a, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_CONTROL", REG_MMIO, 0x4b0c, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_STATUS", REG_MMIO, 0x4b0d, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4b0e, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4b0f, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4b10, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4b11, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4b12, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4b13, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4b14, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GC", REG_MMIO, 0x4b16, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4b17, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_0", REG_MMIO, 0x4b18, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_1", REG_MMIO, 0x4b19, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_2", REG_MMIO, 0x4b1a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_3", REG_MMIO, 0x4b1b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC1_4", REG_MMIO, 0x4b1c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_0", REG_MMIO, 0x4b1d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_1", REG_MMIO, 0x4b1e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_2", REG_MMIO, 0x4b1f, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_ISRC2_3", REG_MMIO, 0x4b20, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO0", REG_MMIO, 0x4b21, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO1", REG_MMIO, 0x4b22, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO2", REG_MMIO, 0x4b23, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AVI_INFO3", REG_MMIO, 0x4b24, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO0", REG_MMIO, 0x4b25, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_MPEG_INFO1", REG_MMIO, 0x4b26, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_HDR", REG_MMIO, 0x4b27, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_0", REG_MMIO, 0x4b28, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_1", REG_MMIO, 0x4b29, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_2", REG_MMIO, 0x4b2a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_3", REG_MMIO, 0x4b2b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_4", REG_MMIO, 0x4b2c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_5", REG_MMIO, 0x4b2d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_6", REG_MMIO, 0x4b2e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_GENERIC_7", REG_MMIO, 0x4b2f, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4b30, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_0", REG_MMIO, 0x4b37, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_32_1", REG_MMIO, 0x4b38, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_0", REG_MMIO, 0x4b39, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_44_1", REG_MMIO, 0x4b3a, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_0", REG_MMIO, 0x4b3b, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_48_1", REG_MMIO, 0x4b3c, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_0", REG_MMIO, 0x4b3d, NULL, 0, 0, 0 },
+	{ "mmDIG5_HDMI_ACR_STATUS_1", REG_MMIO, 0x4b3e, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO0", REG_MMIO, 0x4b3f, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_INFO1", REG_MMIO, 0x4b40, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_0", REG_MMIO, 0x4b41, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_1", REG_MMIO, 0x4b42, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4b43, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4b44, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4b45, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4b46, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4b47, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_60958_2", REG_MMIO, 0x4b48, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4b49, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_STATUS", REG_MMIO, 0x4b4a, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4b4b, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4b4c, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4b4d, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4b4f, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_CNTL", REG_MMIO, 0x4b50, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_BE_EN_CNTL", REG_MMIO, 0x4b51, NULL, 0, 0, 0 },
+	{ "mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4b52, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CNTL", REG_MMIO, 0x4b7c, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL_CHAR", REG_MMIO, 0x4b7d, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4b7e, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4b7f, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4b80, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4b81, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DEBUG", REG_MMIO, 0x4b82, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL_BITS", REG_MMIO, 0x4b83, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4b84, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4b86, NULL, 0, 0, 0 },
+	{ "mmDIG5_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4b87, NULL, 0, 0, 0 },
+	{ "mmDIG5_LVDS_DATA_CNTL", REG_MMIO, 0x4b8c, NULL, 0, 0, 0 },
+	{ "mmDIG5_DIG_LANE_ENABLE", REG_MMIO, 0x4b8d, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL", REG_MMIO, 0x4ba0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING1", REG_MMIO, 0x4ba1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING2", REG_MMIO, 0x4ba2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING3", REG_MMIO, 0x4ba3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_FRAMING4", REG_MMIO, 0x4ba4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N", REG_MMIO, 0x4ba5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4ba6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M", REG_MMIO, 0x4ba7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4ba8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_TIMESTAMP", REG_MMIO, 0x4ba9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4baa, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_SEC_CNTL1", REG_MMIO, 0x4bab, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_CNTL", REG_MMIO, 0x4bc0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_PIXEL_FORMAT", REG_MMIO, 0x4bc1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_CONFIG", REG_MMIO, 0x4bc2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_STREAM_CNTL", REG_MMIO, 0x4bc3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_STEER_FIFO", REG_MMIO, 0x4bc4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_MISC", REG_MMIO, 0x4bc5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4bc6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4bc7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4bc8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_TIMING", REG_MMIO, 0x4bc9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_N", REG_MMIO, 0x4bca, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_M", REG_MMIO, 0x4bcb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4bcc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_MSA_VBID", REG_MMIO, 0x4bcd, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4bce, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4bcf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CNTL", REG_MMIO, 0x4bd0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4bd1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM0", REG_MMIO, 0x4bd2, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4bd3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4bd4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4bd5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_EN", REG_MMIO, 0x4bd6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4bd7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4bd8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_COLORIMETRY", REG_MMIO, 0x4bda, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_MISC_CNTL", REG_MMIO, 0x4bdb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM2", REG_MMIO, 0x4bdf, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_SYM1", REG_MMIO, 0x4be0, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_CNTL", REG_MMIO, 0x4be1, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4be3, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT0", REG_MMIO, 0x4be4, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT1", REG_MMIO, 0x4be5, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT2", REG_MMIO, 0x4be6, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4be7, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSE_LINK_TIMING", REG_MMIO, 0x4be8, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4be9, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4bea, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4beb, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4bfc, NULL, 0, 0, 0 },
+	{ "mmDP5_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4bfd, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_M", REG_SMC, 0x4c, &ixDP_AUX4_DEBUG_M[0], sizeof(ixDP_AUX4_DEBUG_M)/sizeof(ixDP_AUX4_DEBUG_M[0]), 0, 0 },
+	{ "mmSI_ENABLE", REG_MMIO, 0x4c00, &mmSI_ENABLE[0], sizeof(mmSI_ENABLE)/sizeof(mmSI_ENABLE[0]), 0, 0 },
+	{ "mmSI_EC_CONFIG", REG_MMIO, 0x4c01, &mmSI_EC_CONFIG[0], sizeof(mmSI_EC_CONFIG)/sizeof(mmSI_EC_CONFIG[0]), 0, 0 },
+	{ "mmCNV_MODE", REG_MMIO, 0x4c02, &mmCNV_MODE[0], sizeof(mmCNV_MODE)/sizeof(mmCNV_MODE[0]), 0, 0 },
+	{ "mmCNV_WINDOW_START", REG_MMIO, 0x4c03, &mmCNV_WINDOW_START[0], sizeof(mmCNV_WINDOW_START)/sizeof(mmCNV_WINDOW_START[0]), 0, 0 },
+	{ "mmCNV_WINDOW_SIZE", REG_MMIO, 0x4c04, &mmCNV_WINDOW_SIZE[0], sizeof(mmCNV_WINDOW_SIZE)/sizeof(mmCNV_WINDOW_SIZE[0]), 0, 0 },
+	{ "mmCNV_UPDATE", REG_MMIO, 0x4c05, &mmCNV_UPDATE[0], sizeof(mmCNV_UPDATE)/sizeof(mmCNV_UPDATE[0]), 0, 0 },
+	{ "mmCNV_SOURCE_SIZE", REG_MMIO, 0x4c06, &mmCNV_SOURCE_SIZE[0], sizeof(mmCNV_SOURCE_SIZE)/sizeof(mmCNV_SOURCE_SIZE[0]), 0, 0 },
+	{ "mmCNV_CSC_CONTROL", REG_MMIO, 0x4c07, &mmCNV_CSC_CONTROL[0], sizeof(mmCNV_CSC_CONTROL)/sizeof(mmCNV_CSC_CONTROL[0]), 0, 0 },
+	{ "mmCNV_CSC_C11_C12", REG_MMIO, 0x4c08, &mmCNV_CSC_C11_C12[0], sizeof(mmCNV_CSC_C11_C12)/sizeof(mmCNV_CSC_C11_C12[0]), 0, 0 },
+	{ "mmCNV_CSC_C13_C14", REG_MMIO, 0x4c09, &mmCNV_CSC_C13_C14[0], sizeof(mmCNV_CSC_C13_C14)/sizeof(mmCNV_CSC_C13_C14[0]), 0, 0 },
+	{ "mmCNV_CSC_C21_C22", REG_MMIO, 0x4c0a, &mmCNV_CSC_C21_C22[0], sizeof(mmCNV_CSC_C21_C22)/sizeof(mmCNV_CSC_C21_C22[0]), 0, 0 },
+	{ "mmCNV_CSC_C23_C24", REG_MMIO, 0x4c0b, &mmCNV_CSC_C23_C24[0], sizeof(mmCNV_CSC_C23_C24)/sizeof(mmCNV_CSC_C23_C24[0]), 0, 0 },
+	{ "mmCNV_CSC_C31_C32", REG_MMIO, 0x4c0c, &mmCNV_CSC_C31_C32[0], sizeof(mmCNV_CSC_C31_C32)/sizeof(mmCNV_CSC_C31_C32[0]), 0, 0 },
+	{ "mmCNV_CSC_C33_C34", REG_MMIO, 0x4c0d, &mmCNV_CSC_C33_C34[0], sizeof(mmCNV_CSC_C33_C34)/sizeof(mmCNV_CSC_C33_C34[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_R", REG_MMIO, 0x4c0e, &mmCNV_CSC_ROUND_OFFSET_R[0], sizeof(mmCNV_CSC_ROUND_OFFSET_R)/sizeof(mmCNV_CSC_ROUND_OFFSET_R[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_G", REG_MMIO, 0x4c0f, &mmCNV_CSC_ROUND_OFFSET_G[0], sizeof(mmCNV_CSC_ROUND_OFFSET_G)/sizeof(mmCNV_CSC_ROUND_OFFSET_G[0]), 0, 0 },
+	{ "mmCNV_CSC_ROUND_OFFSET_B", REG_MMIO, 0x4c10, &mmCNV_CSC_ROUND_OFFSET_B[0], sizeof(mmCNV_CSC_ROUND_OFFSET_B)/sizeof(mmCNV_CSC_ROUND_OFFSET_B[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_R", REG_MMIO, 0x4c11, &mmCNV_CSC_CLAMP_R[0], sizeof(mmCNV_CSC_CLAMP_R)/sizeof(mmCNV_CSC_CLAMP_R[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_G", REG_MMIO, 0x4c12, &mmCNV_CSC_CLAMP_G[0], sizeof(mmCNV_CSC_CLAMP_G)/sizeof(mmCNV_CSC_CLAMP_G[0]), 0, 0 },
+	{ "mmCNV_CSC_CLAMP_B", REG_MMIO, 0x4c13, &mmCNV_CSC_CLAMP_B[0], sizeof(mmCNV_CSC_CLAMP_B)/sizeof(mmCNV_CSC_CLAMP_B[0]), 0, 0 },
+	{ "mmCNV_TEST_CNTL", REG_MMIO, 0x4c14, &mmCNV_TEST_CNTL[0], sizeof(mmCNV_TEST_CNTL)/sizeof(mmCNV_TEST_CNTL[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_RED", REG_MMIO, 0x4c15, &mmCNV_TEST_CRC_RED[0], sizeof(mmCNV_TEST_CRC_RED)/sizeof(mmCNV_TEST_CRC_RED[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_GREEN", REG_MMIO, 0x4c16, &mmCNV_TEST_CRC_GREEN[0], sizeof(mmCNV_TEST_CRC_GREEN)/sizeof(mmCNV_TEST_CRC_GREEN[0]), 0, 0 },
+	{ "mmCNV_TEST_CRC_BLUE", REG_MMIO, 0x4c17, &mmCNV_TEST_CRC_BLUE[0], sizeof(mmCNV_TEST_CRC_BLUE)/sizeof(mmCNV_TEST_CRC_BLUE[0]), 0, 0 },
+	{ "mmSI_DEBUG_CTRL", REG_MMIO, 0x4c18, &mmSI_DEBUG_CTRL[0], sizeof(mmSI_DEBUG_CTRL)/sizeof(mmSI_DEBUG_CTRL[0]), 0, 0 },
+	{ "mmCNV_TEST_DEBUG_INDEX", REG_MMIO, 0x4c19, &mmCNV_TEST_DEBUG_INDEX[0], sizeof(mmCNV_TEST_DEBUG_INDEX)/sizeof(mmCNV_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmCNV_TEST_DEBUG_DATA", REG_MMIO, 0x4c1a, &mmCNV_TEST_DEBUG_DATA[0], sizeof(mmCNV_TEST_DEBUG_DATA)/sizeof(mmCNV_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmSI_DBG_MODE", REG_MMIO, 0x4c1b, &mmSI_DBG_MODE[0], sizeof(mmSI_DBG_MODE)/sizeof(mmSI_DBG_MODE[0]), 0, 0 },
+	{ "mmSI_HARD_DEBUG", REG_MMIO, 0x4c1c, &mmSI_HARD_DEBUG[0], sizeof(mmSI_HARD_DEBUG)/sizeof(mmSI_HARD_DEBUG[0]), 0, 0 },
+	{ "mmSISCL_COEF_RAM_SELECT", REG_MMIO, 0x4c20, &mmSISCL_COEF_RAM_SELECT[0], sizeof(mmSISCL_COEF_RAM_SELECT)/sizeof(mmSISCL_COEF_RAM_SELECT[0]), 0, 0 },
+	{ "mmSISCL_COEF_RAM_TAP_DATA", REG_MMIO, 0x4c21, &mmSISCL_COEF_RAM_TAP_DATA[0], sizeof(mmSISCL_COEF_RAM_TAP_DATA)/sizeof(mmSISCL_COEF_RAM_TAP_DATA[0]), 0, 0 },
+	{ "mmSISCL_MODE", REG_MMIO, 0x4c22, &mmSISCL_MODE[0], sizeof(mmSISCL_MODE)/sizeof(mmSISCL_MODE[0]), 0, 0 },
+	{ "mmSISCL_TAP_CONTROL", REG_MMIO, 0x4c23, &mmSISCL_TAP_CONTROL[0], sizeof(mmSISCL_TAP_CONTROL)/sizeof(mmSISCL_TAP_CONTROL[0]), 0, 0 },
+	{ "mmSISCL_DEST_SIZE", REG_MMIO, 0x4c24, &mmSISCL_DEST_SIZE[0], sizeof(mmSISCL_DEST_SIZE)/sizeof(mmSISCL_DEST_SIZE[0]), 0, 0 },
+	{ "mmSISCL_HORZ_FILTER_SCALE_RATIO", REG_MMIO, 0x4c25, &mmSISCL_HORZ_FILTER_SCALE_RATIO[0], sizeof(mmSISCL_HORZ_FILTER_SCALE_RATIO)/sizeof(mmSISCL_HORZ_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSISCL_HORZ_FILTER_INIT_Y_RGB", REG_MMIO, 0x4c26, &mmSISCL_HORZ_FILTER_INIT_Y_RGB[0], sizeof(mmSISCL_HORZ_FILTER_INIT_Y_RGB)/sizeof(mmSISCL_HORZ_FILTER_INIT_Y_RGB[0]), 0, 0 },
+	{ "mmSISCL_HORZ_FILTER_INIT_CBCR", REG_MMIO, 0x4c27, &mmSISCL_HORZ_FILTER_INIT_CBCR[0], sizeof(mmSISCL_HORZ_FILTER_INIT_CBCR)/sizeof(mmSISCL_HORZ_FILTER_INIT_CBCR[0]), 0, 0 },
+	{ "mmSISCL_VERT_FILTER_SCALE_RATIO", REG_MMIO, 0x4c28, &mmSISCL_VERT_FILTER_SCALE_RATIO[0], sizeof(mmSISCL_VERT_FILTER_SCALE_RATIO)/sizeof(mmSISCL_VERT_FILTER_SCALE_RATIO[0]), 0, 0 },
+	{ "mmSISCL_VERT_FILTER_INIT_Y_RGB", REG_MMIO, 0x4c29, &mmSISCL_VERT_FILTER_INIT_Y_RGB[0], sizeof(mmSISCL_VERT_FILTER_INIT_Y_RGB)/sizeof(mmSISCL_VERT_FILTER_INIT_Y_RGB[0]), 0, 0 },
+	{ "mmSISCL_VERT_FILTER_INIT_CBCR", REG_MMIO, 0x4c2a, &mmSISCL_VERT_FILTER_INIT_CBCR[0], sizeof(mmSISCL_VERT_FILTER_INIT_CBCR)/sizeof(mmSISCL_VERT_FILTER_INIT_CBCR[0]), 0, 0 },
+	{ "mmSISCL_ROUND_OFFSET", REG_MMIO, 0x4c2b, &mmSISCL_ROUND_OFFSET[0], sizeof(mmSISCL_ROUND_OFFSET)/sizeof(mmSISCL_ROUND_OFFSET[0]), 0, 0 },
+	{ "mmSISCL_CLAMP", REG_MMIO, 0x4c2c, &mmSISCL_CLAMP[0], sizeof(mmSISCL_CLAMP)/sizeof(mmSISCL_CLAMP[0]), 0, 0 },
+	{ "mmSISCL_OVERFLOW_STATUS", REG_MMIO, 0x4c2d, &mmSISCL_OVERFLOW_STATUS[0], sizeof(mmSISCL_OVERFLOW_STATUS)/sizeof(mmSISCL_OVERFLOW_STATUS[0]), 0, 0 },
+	{ "mmSISCL_COEF_RAM_CONFLICT_STATUS", REG_MMIO, 0x4c2e, &mmSISCL_COEF_RAM_CONFLICT_STATUS[0], sizeof(mmSISCL_COEF_RAM_CONFLICT_STATUS)/sizeof(mmSISCL_COEF_RAM_CONFLICT_STATUS[0]), 0, 0 },
+	{ "mmSISCL_OUTSIDE_PIX_STRATEGY", REG_MMIO, 0x4c2f, &mmSISCL_OUTSIDE_PIX_STRATEGY[0], sizeof(mmSISCL_OUTSIDE_PIX_STRATEGY)/sizeof(mmSISCL_OUTSIDE_PIX_STRATEGY[0]), 0, 0 },
+	{ "mmSISCL_TEST_CNTL", REG_MMIO, 0x4c30, &mmSISCL_TEST_CNTL[0], sizeof(mmSISCL_TEST_CNTL)/sizeof(mmSISCL_TEST_CNTL[0]), 0, 0 },
+	{ "mmSISCL_TEST_CRC_RED", REG_MMIO, 0x4c31, &mmSISCL_TEST_CRC_RED[0], sizeof(mmSISCL_TEST_CRC_RED)/sizeof(mmSISCL_TEST_CRC_RED[0]), 0, 0 },
+	{ "mmSISCL_TEST_CRC_GREEN", REG_MMIO, 0x4c32, &mmSISCL_TEST_CRC_GREEN[0], sizeof(mmSISCL_TEST_CRC_GREEN)/sizeof(mmSISCL_TEST_CRC_GREEN[0]), 0, 0 },
+	{ "mmSISCL_TEST_CRC_BLUE", REG_MMIO, 0x4c33, &mmSISCL_TEST_CRC_BLUE[0], sizeof(mmSISCL_TEST_CRC_BLUE)/sizeof(mmSISCL_TEST_CRC_BLUE[0]), 0, 0 },
+	{ "mmSISCL_TEST_DEBUG_INDEX", REG_MMIO, 0x4c34, &mmSISCL_TEST_DEBUG_INDEX[0], sizeof(mmSISCL_TEST_DEBUG_INDEX)/sizeof(mmSISCL_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmSISCL_TEST_DEBUG_DATA", REG_MMIO, 0x4c35, &mmSISCL_TEST_DEBUG_DATA[0], sizeof(mmSISCL_TEST_DEBUG_DATA)/sizeof(mmSISCL_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmSISCL_BACKPRESSURE_CNT_EN", REG_MMIO, 0x4c36, &mmSISCL_BACKPRESSURE_CNT_EN[0], sizeof(mmSISCL_BACKPRESSURE_CNT_EN)/sizeof(mmSISCL_BACKPRESSURE_CNT_EN[0]), 0, 0 },
+	{ "mmSISCL_MCIF_BACKPRESSURE_CNT", REG_MMIO, 0x4c37, &mmSISCL_MCIF_BACKPRESSURE_CNT[0], sizeof(mmSISCL_MCIF_BACKPRESSURE_CNT)/sizeof(mmSISCL_MCIF_BACKPRESSURE_CNT[0]), 0, 0 },
+	{ "mmDC_PERFMON8_PERFCOUNTER_CNTL", REG_MMIO, 0x4c40, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFCOUNTER_STATE", REG_MMIO, 0x4c41, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4c42, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CNTL", REG_MMIO, 0x4c43, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_CVALUE_LOW", REG_MMIO, 0x4c44, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_HI", REG_MMIO, 0x4c45, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_LOW", REG_MMIO, 0x4c46, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x4c47, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON8_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x4c48, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_N", REG_SMC, 0x4d, &ixDP_AUX4_DEBUG_N[0], sizeof(ixDP_AUX4_DEBUG_N)/sizeof(ixDP_AUX4_DEBUG_N[0]), 0, 0 },
+	{ "mmDC_PERFMON9_PERFCOUNTER_CNTL", REG_MMIO, 0x4d14, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFCOUNTER_STATE", REG_MMIO, 0x4d15, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC", REG_MMIO, 0x4d16, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CNTL", REG_MMIO, 0x4d17, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_CVALUE_LOW", REG_MMIO, 0x4d18, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_HI", REG_MMIO, 0x4d19, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_LOW", REG_MMIO, 0x4d1a, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_TEST_DEBUG_INDEX", REG_MMIO, 0x4d1b, NULL, 0, 0, 0 },
+	{ "mmDC_PERFMON9_PERFMON_TEST_DEBUG_DATA", REG_MMIO, 0x4d1c, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL1", REG_MMIO, 0x4df0, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL2", REG_MMIO, 0x4df1, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL3", REG_MMIO, 0x4df2, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_TX_CONTROL4", REG_MMIO, 0x4df3, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_POWER_CONTROL", REG_MMIO, 0x4df4, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_PLL_FBDIV", REG_MMIO, 0x4df5, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL1", REG_MMIO, 0x4df6, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_PLL_CONTROL2", REG_MMIO, 0x4df7, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_PLL_SS_STEP_SIZE", REG_MMIO, 0x4df8, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_PLL_SS_CNTL", REG_MMIO, 0x4df9, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_DATA_SYNCHRONIZATION", REG_MMIO, 0x4dfa, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT", REG_MMIO, 0x4dfb, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_ANG_BIST_CNTL", REG_MMIO, 0x4dfc, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_LINK_CNTL", REG_MMIO, 0x4dfd, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_CHANNEL_XBAR_CNTL", REG_MMIO, 0x4dfe, NULL, 0, 0, 0 },
+	{ "mmDCIO_UNIPHY6_UNIPHY_REG_TEST_OUTPUT2", REG_MMIO, 0x4dff, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_O", REG_SMC, 0x4e, &ixDP_AUX4_DEBUG_O[0], sizeof(ixDP_AUX4_DEBUG_O)/sizeof(ixDP_AUX4_DEBUG_O[0]), 0, 0 },
+	{ "mmDIG6_DIG_FE_CNTL", REG_MMIO, 0x4e00, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_OUTPUT_CRC_CNTL", REG_MMIO, 0x4e01, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_OUTPUT_CRC_RESULT", REG_MMIO, 0x4e02, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_CLOCK_PATTERN", REG_MMIO, 0x4e03, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_TEST_PATTERN", REG_MMIO, 0x4e04, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_RANDOM_PATTERN_SEED", REG_MMIO, 0x4e05, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_DISPCLK_SWITCH_CNTL", REG_MMIO, 0x4e08, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_DISPCLK_SWITCH_STATUS", REG_MMIO, 0x4e09, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_FIFO_STATUS", REG_MMIO, 0x4e0a, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_CONTROL", REG_MMIO, 0x4e0c, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_STATUS", REG_MMIO, 0x4e0d, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4e0e, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_PACKET_CONTROL", REG_MMIO, 0x4e0f, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_VBI_PACKET_CONTROL", REG_MMIO, 0x4e10, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_INFOFRAME_CONTROL0", REG_MMIO, 0x4e11, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_INFOFRAME_CONTROL1", REG_MMIO, 0x4e12, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GENERIC_PACKET_CONTROL0", REG_MMIO, 0x4e13, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_INTERRUPT_STATUS", REG_MMIO, 0x4e14, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GC", REG_MMIO, 0x4e16, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_PACKET_CONTROL2", REG_MMIO, 0x4e17, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_0", REG_MMIO, 0x4e18, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_1", REG_MMIO, 0x4e19, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_2", REG_MMIO, 0x4e1a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_3", REG_MMIO, 0x4e1b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC1_4", REG_MMIO, 0x4e1c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_0", REG_MMIO, 0x4e1d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_1", REG_MMIO, 0x4e1e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_2", REG_MMIO, 0x4e1f, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_ISRC2_3", REG_MMIO, 0x4e20, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO0", REG_MMIO, 0x4e21, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO1", REG_MMIO, 0x4e22, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO2", REG_MMIO, 0x4e23, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AVI_INFO3", REG_MMIO, 0x4e24, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_MPEG_INFO0", REG_MMIO, 0x4e25, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_MPEG_INFO1", REG_MMIO, 0x4e26, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_HDR", REG_MMIO, 0x4e27, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_0", REG_MMIO, 0x4e28, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_1", REG_MMIO, 0x4e29, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_2", REG_MMIO, 0x4e2a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_3", REG_MMIO, 0x4e2b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_4", REG_MMIO, 0x4e2c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_5", REG_MMIO, 0x4e2d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_6", REG_MMIO, 0x4e2e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_GENERIC_7", REG_MMIO, 0x4e2f, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_GENERIC_PACKET_CONTROL1", REG_MMIO, 0x4e30, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_32_0", REG_MMIO, 0x4e37, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_32_1", REG_MMIO, 0x4e38, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_44_0", REG_MMIO, 0x4e39, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_44_1", REG_MMIO, 0x4e3a, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_48_0", REG_MMIO, 0x4e3b, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_48_1", REG_MMIO, 0x4e3c, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_STATUS_0", REG_MMIO, 0x4e3d, NULL, 0, 0, 0 },
+	{ "mmDIG6_HDMI_ACR_STATUS_1", REG_MMIO, 0x4e3e, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_INFO0", REG_MMIO, 0x4e3f, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_INFO1", REG_MMIO, 0x4e40, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_0", REG_MMIO, 0x4e41, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_1", REG_MMIO, 0x4e42, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_CRC_CONTROL", REG_MMIO, 0x4e43, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL0", REG_MMIO, 0x4e44, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL1", REG_MMIO, 0x4e45, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL2", REG_MMIO, 0x4e46, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_RAMP_CONTROL3", REG_MMIO, 0x4e47, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_60958_2", REG_MMIO, 0x4e48, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_CRC_RESULT", REG_MMIO, 0x4e49, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_STATUS", REG_MMIO, 0x4e4a, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_PACKET_CONTROL", REG_MMIO, 0x4e4b, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_VBI_PACKET_CONTROL", REG_MMIO, 0x4e4c, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_INFOFRAME_CONTROL0", REG_MMIO, 0x4e4d, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_SRC_CONTROL", REG_MMIO, 0x4e4f, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_BE_CNTL", REG_MMIO, 0x4e50, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_BE_EN_CNTL", REG_MMIO, 0x4e51, NULL, 0, 0, 0 },
+	{ "mmDIG6_AFMT_AUDIO_DBG_DTO_CNTL", REG_MMIO, 0x4e52, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CNTL", REG_MMIO, 0x4e7c, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CONTROL_CHAR", REG_MMIO, 0x4e7d, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CONTROL0_FEEDBACK", REG_MMIO, 0x4e7e, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_STEREOSYNC_CTL_SEL", REG_MMIO, 0x4e7f, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1", REG_MMIO, 0x4e80, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3", REG_MMIO, 0x4e81, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_DEBUG", REG_MMIO, 0x4e82, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL_BITS", REG_MMIO, 0x4e83, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_DCBALANCER_CONTROL", REG_MMIO, 0x4e84, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL0_1_GEN_CNTL", REG_MMIO, 0x4e86, NULL, 0, 0, 0 },
+	{ "mmDIG6_TMDS_CTL2_3_GEN_CNTL", REG_MMIO, 0x4e87, NULL, 0, 0, 0 },
+	{ "mmDIG6_LVDS_DATA_CNTL", REG_MMIO, 0x4e8c, NULL, 0, 0, 0 },
+	{ "mmDIG6_DIG_LANE_ENABLE", REG_MMIO, 0x4e8d, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_CNTL", REG_MMIO, 0x4ea0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING1", REG_MMIO, 0x4ea1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING2", REG_MMIO, 0x4ea2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING3", REG_MMIO, 0x4ea3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_FRAMING4", REG_MMIO, 0x4ea4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_N", REG_MMIO, 0x4ea5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_N_READBACK", REG_MMIO, 0x4ea6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_M", REG_MMIO, 0x4ea7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_AUD_M_READBACK", REG_MMIO, 0x4ea8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_TIMESTAMP", REG_MMIO, 0x4ea9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_PACKET_CNTL", REG_MMIO, 0x4eaa, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_SEC_CNTL1", REG_MMIO, 0x4eab, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_LINK_CNTL", REG_MMIO, 0x4ec0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_PIXEL_FORMAT", REG_MMIO, 0x4ec1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_CONFIG", REG_MMIO, 0x4ec2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_STREAM_CNTL", REG_MMIO, 0x4ec3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_STEER_FIFO", REG_MMIO, 0x4ec4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_MISC", REG_MMIO, 0x4ec5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_MST_CNTL", REG_MMIO, 0x4ec6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_MST_STATUS", REG_MMIO, 0x4ec7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_HBR2_EYE_PATTERN", REG_MMIO, 0x4ec8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_TIMING", REG_MMIO, 0x4ec9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_N", REG_MMIO, 0x4eca, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_M", REG_MMIO, 0x4ecb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_LINK_FRAMING_CNTL", REG_MMIO, 0x4ecc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_MSA_VBID", REG_MMIO, 0x4ecd, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_FAST_TRAINING", REG_MMIO, 0x4ece, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_VID_INTERRUPT_CNTL", REG_MMIO, 0x4ecf, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CNTL", REG_MMIO, 0x4ed0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_TRAINING_PATTERN_SEL", REG_MMIO, 0x4ed1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM0", REG_MMIO, 0x4ed2, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_8B10B_CNTL", REG_MMIO, 0x4ed3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_PRBS_CNTL", REG_MMIO, 0x4ed4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SCRAM_CNTL", REG_MMIO, 0x4ed5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_EN", REG_MMIO, 0x4ed6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_CNTL", REG_MMIO, 0x4ed7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_CRC_RESULT", REG_MMIO, 0x4ed8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_COLORIMETRY", REG_MMIO, 0x4eda, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_MISC_CNTL", REG_MMIO, 0x4edb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM2", REG_MMIO, 0x4edf, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_SYM1", REG_MMIO, 0x4ee0, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_RATE_CNTL", REG_MMIO, 0x4ee1, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_RATE_UPDATE", REG_MMIO, 0x4ee3, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT0", REG_MMIO, 0x4ee4, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT1", REG_MMIO, 0x4ee5, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT2", REG_MMIO, 0x4ee6, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_SAT_UPDATE", REG_MMIO, 0x4ee7, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSE_LINK_TIMING", REG_MMIO, 0x4ee8, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_DPHY_FAST_TRAINING_STATUS", REG_MMIO, 0x4ee9, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_V_TIMING_OVERRIDE1", REG_MMIO, 0x4eea, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_MSA_V_TIMING_OVERRIDE2", REG_MMIO, 0x4eeb, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_TEST_DEBUG_INDEX", REG_MMIO, 0x4efc, NULL, 0, 0, 0 },
+	{ "mmDP6_DP_TEST_DEBUG_DATA", REG_MMIO, 0x4efd, NULL, 0, 0, 0 },
+	{ "ixDP_AUX4_DEBUG_P", REG_SMC, 0x4f, &ixDP_AUX4_DEBUG_P[0], sizeof(ixDP_AUX4_DEBUG_P)/sizeof(ixDP_AUX4_DEBUG_P[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS", REG_SMC, 0x5, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL5", REG_SMC, 0x5, &ixAZALIA_CRC0_CHANNEL5[0], sizeof(ixAZALIA_CRC0_CHANNEL5)/sizeof(ixAZALIA_CRC0_CHANNEL5[0]), 0, 0 },
+	{ "ixAZALIA_STREAM_DEBUG", REG_SMC, 0x5, &ixAZALIA_STREAM_DEBUG[0], sizeof(ixAZALIA_STREAM_DEBUG)/sizeof(ixAZALIA_STREAM_DEBUG[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR4", REG_SMC, 0x5, &ixAUDIO_DESCRIPTOR4[0], sizeof(ixAUDIO_DESCRIPTOR4)/sizeof(ixAUDIO_DESCRIPTOR4[0]), 0, 0 },
+	{ "ixDCIO_DEBUG5", REG_SMC, 0x5, &ixDCIO_DEBUG5[0], sizeof(ixDCIO_DEBUG5)/sizeof(ixDCIO_DEBUG5[0]), 0, 0 },
+	{ "ixATTR05", REG_SMC, 0x5, &ixATTR05[0], sizeof(ixATTR05)/sizeof(ixATTR05[0]), 0, 0 },
+	{ "ixCRT05", REG_SMC, 0x5, &ixCRT05[0], sizeof(ixCRT05)/sizeof(ixCRT05[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL", REG_SMC, 0x54, &ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE", REG_SMC, 0x55, &ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT", REG_SMC, 0x56, &ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2", REG_SMC, 0x57, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE", REG_SMC, 0x58, &ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0", REG_SMC, 0x59, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1", REG_SMC, 0x5a, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2", REG_SMC, 0x5b, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3", REG_SMC, 0x5c, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4", REG_SMC, 0x5d, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5", REG_SMC, 0x5e, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6", REG_SMC, 0x5f, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES", REG_SMC, 0x6, &ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_PAYLOAD_CAPABILITY", REG_MMIO, 0x6, &mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[0], sizeof(mmOUTPUT_STREAM_PAYLOAD_CAPABILITY)/sizeof(mmOUTPUT_STREAM_PAYLOAD_CAPABILITY[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL6", REG_SMC, 0x6, &ixAZALIA_CRC0_CHANNEL6[0], sizeof(ixAZALIA_CRC0_CHANNEL6)/sizeof(ixAZALIA_CRC0_CHANNEL6[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR5", REG_SMC, 0x6, &ixAUDIO_DESCRIPTOR5[0], sizeof(ixAUDIO_DESCRIPTOR5)/sizeof(ixAUDIO_DESCRIPTOR5[0]), 0, 0 },
+	{ "ixDCIO_DEBUG6", REG_SMC, 0x6, &ixDCIO_DEBUG6[0], sizeof(ixDCIO_DEBUG6)/sizeof(ixDCIO_DEBUG6[0]), 0, 0 },
+	{ "ixATTR06", REG_SMC, 0x6, &ixATTR06[0], sizeof(ixATTR06)/sizeof(ixATTR06[0]), 0, 0 },
+	{ "ixCRT06", REG_SMC, 0x6, &ixCRT06[0], sizeof(ixCRT06)/sizeof(ixCRT06[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7", REG_SMC, 0x60, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7[0]), 0, 0 },
+	{ "ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8", REG_SMC, 0x61, &ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0], sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8)/sizeof(ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO", REG_SMC, 0x62, &ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0], sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO)/sizeof(ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS", REG_SMC, 0x63, &ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0], sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS)/sizeof(ixAZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL", REG_SMC, 0x7, &ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL[0]), 0, 0 },
+	{ "ixAZALIA_CRC0_CHANNEL7", REG_SMC, 0x7, &ixAZALIA_CRC0_CHANNEL7[0], sizeof(ixAZALIA_CRC0_CHANNEL7)/sizeof(ixAZALIA_CRC0_CHANNEL7[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR6", REG_SMC, 0x7, &ixAUDIO_DESCRIPTOR6[0], sizeof(ixAUDIO_DESCRIPTOR6)/sizeof(ixAUDIO_DESCRIPTOR6[0]), 0, 0 },
+	{ "ixDCIO_DEBUG7", REG_SMC, 0x7, &ixDCIO_DEBUG7[0], sizeof(ixDCIO_DEBUG7)/sizeof(ixDCIO_DEBUG7[0]), 0, 0 },
+	{ "ixATTR07", REG_SMC, 0x7, &ixATTR07[0], sizeof(ixATTR07)/sizeof(ixATTR07[0]), 0, 0 },
+	{ "ixCRT07", REG_SMC, 0x7, &ixCRT07[0], sizeof(ixCRT07)/sizeof(ixCRT07[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_A", REG_SMC, 0x70, &ixDP_AUX5_DEBUG_A[0], sizeof(ixDP_AUX5_DEBUG_A)/sizeof(ixDP_AUX5_DEBUG_A[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_B", REG_SMC, 0x71, &ixDP_AUX5_DEBUG_B[0], sizeof(ixDP_AUX5_DEBUG_B)/sizeof(ixDP_AUX5_DEBUG_B[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_C", REG_SMC, 0x72, &ixDP_AUX5_DEBUG_C[0], sizeof(ixDP_AUX5_DEBUG_C)/sizeof(ixDP_AUX5_DEBUG_C[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_D", REG_SMC, 0x73, &ixDP_AUX5_DEBUG_D[0], sizeof(ixDP_AUX5_DEBUG_D)/sizeof(ixDP_AUX5_DEBUG_D[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_E", REG_SMC, 0x74, &ixDP_AUX5_DEBUG_E[0], sizeof(ixDP_AUX5_DEBUG_E)/sizeof(ixDP_AUX5_DEBUG_E[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_F", REG_SMC, 0x75, &ixDP_AUX5_DEBUG_F[0], sizeof(ixDP_AUX5_DEBUG_F)/sizeof(ixDP_AUX5_DEBUG_F[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_G", REG_SMC, 0x76, &ixDP_AUX5_DEBUG_G[0], sizeof(ixDP_AUX5_DEBUG_G)/sizeof(ixDP_AUX5_DEBUG_G[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_H", REG_SMC, 0x77, &ixDP_AUX5_DEBUG_H[0], sizeof(ixDP_AUX5_DEBUG_H)/sizeof(ixDP_AUX5_DEBUG_H[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_I", REG_SMC, 0x78, &ixDP_AUX5_DEBUG_I[0], sizeof(ixDP_AUX5_DEBUG_I)/sizeof(ixDP_AUX5_DEBUG_I[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_J", REG_SMC, 0x79, &ixDP_AUX5_DEBUG_J[0], sizeof(ixDP_AUX5_DEBUG_J)/sizeof(ixDP_AUX5_DEBUG_J[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_K", REG_SMC, 0x7a, &ixDP_AUX5_DEBUG_K[0], sizeof(ixDP_AUX5_DEBUG_K)/sizeof(ixDP_AUX5_DEBUG_K[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_L", REG_SMC, 0x7b, &ixDP_AUX5_DEBUG_L[0], sizeof(ixDP_AUX5_DEBUG_L)/sizeof(ixDP_AUX5_DEBUG_L[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_M", REG_SMC, 0x7c, &ixDP_AUX5_DEBUG_M[0], sizeof(ixDP_AUX5_DEBUG_M)/sizeof(ixDP_AUX5_DEBUG_M[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_N", REG_SMC, 0x7d, &ixDP_AUX5_DEBUG_N[0], sizeof(ixDP_AUX5_DEBUG_N)/sizeof(ixDP_AUX5_DEBUG_N[0]), 0, 0 },
+	{ "ixVGADCC_DBG_DCCIF_C", REG_SMC, 0x7e, &ixVGADCC_DBG_DCCIF_C[0], sizeof(ixVGADCC_DBG_DCCIF_C)/sizeof(ixVGADCC_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_O", REG_SMC, 0x7f, &ixDP_AUX5_DEBUG_O[0], sizeof(ixDP_AUX5_DEBUG_O)/sizeof(ixDP_AUX5_DEBUG_O[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE", REG_SMC, 0x8, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE[0]), 0, 0 },
+	{ "mmINTERRUPT_CONTROL", REG_MMIO, 0x8, &mmINTERRUPT_CONTROL[0], sizeof(mmINTERRUPT_CONTROL)/sizeof(mmINTERRUPT_CONTROL[0]), 0, 0 },
+	{ "ixDCIO_DEBUG8", REG_SMC, 0x8, &ixDCIO_DEBUG8[0], sizeof(ixDCIO_DEBUG8)/sizeof(ixDCIO_DEBUG8[0]), 0, 0 },
+	{ "ixATTR08", REG_SMC, 0x8, &ixATTR08[0], sizeof(ixATTR08)/sizeof(ixATTR08[0]), 0, 0 },
+	{ "ixCRT08", REG_SMC, 0x8, &ixCRT08[0], sizeof(ixCRT08)/sizeof(ixCRT08[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_A", REG_SMC, 0x80, &ixDP_AUX6_DEBUG_A[0], sizeof(ixDP_AUX6_DEBUG_A)/sizeof(ixDP_AUX6_DEBUG_A[0]), 0, 0 },
+	{ "mmWALL_CLOCK_COUNTER_ALIAS", REG_MMIO, 0x80c, &mmWALL_CLOCK_COUNTER_ALIAS[0], sizeof(mmWALL_CLOCK_COUNTER_ALIAS)/sizeof(mmWALL_CLOCK_COUNTER_ALIAS[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_B", REG_SMC, 0x81, &ixDP_AUX6_DEBUG_B[0], sizeof(ixDP_AUX6_DEBUG_B)/sizeof(ixDP_AUX6_DEBUG_B[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_C", REG_SMC, 0x82, &ixDP_AUX6_DEBUG_C[0], sizeof(ixDP_AUX6_DEBUG_C)/sizeof(ixDP_AUX6_DEBUG_C[0]), 0, 0 },
+	{ "mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS", REG_MMIO, 0x821, &mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0], sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS)/sizeof(mmOUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_D", REG_SMC, 0x83, &ixDP_AUX6_DEBUG_D[0], sizeof(ixDP_AUX6_DEBUG_D)/sizeof(ixDP_AUX6_DEBUG_D[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_E", REG_SMC, 0x84, &ixDP_AUX6_DEBUG_E[0], sizeof(ixDP_AUX6_DEBUG_E)/sizeof(ixDP_AUX6_DEBUG_E[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_F", REG_SMC, 0x85, &ixDP_AUX6_DEBUG_F[0], sizeof(ixDP_AUX6_DEBUG_F)/sizeof(ixDP_AUX6_DEBUG_F[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_G", REG_SMC, 0x86, &ixDP_AUX6_DEBUG_G[0], sizeof(ixDP_AUX6_DEBUG_G)/sizeof(ixDP_AUX6_DEBUG_G[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_H", REG_SMC, 0x87, &ixDP_AUX6_DEBUG_H[0], sizeof(ixDP_AUX6_DEBUG_H)/sizeof(ixDP_AUX6_DEBUG_H[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_I", REG_SMC, 0x88, &ixDP_AUX6_DEBUG_I[0], sizeof(ixDP_AUX6_DEBUG_I)/sizeof(ixDP_AUX6_DEBUG_I[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_J", REG_SMC, 0x89, &ixDP_AUX6_DEBUG_J[0], sizeof(ixDP_AUX6_DEBUG_J)/sizeof(ixDP_AUX6_DEBUG_J[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_K", REG_SMC, 0x8a, &ixDP_AUX6_DEBUG_K[0], sizeof(ixDP_AUX6_DEBUG_K)/sizeof(ixDP_AUX6_DEBUG_K[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_L", REG_SMC, 0x8b, &ixDP_AUX6_DEBUG_L[0], sizeof(ixDP_AUX6_DEBUG_L)/sizeof(ixDP_AUX6_DEBUG_L[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_M", REG_SMC, 0x8c, &ixDP_AUX6_DEBUG_M[0], sizeof(ixDP_AUX6_DEBUG_M)/sizeof(ixDP_AUX6_DEBUG_M[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_N", REG_SMC, 0x8d, &ixDP_AUX6_DEBUG_N[0], sizeof(ixDP_AUX6_DEBUG_N)/sizeof(ixDP_AUX6_DEBUG_N[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_O", REG_SMC, 0x8f, &ixDP_AUX6_DEBUG_O[0], sizeof(ixDP_AUX6_DEBUG_O)/sizeof(ixDP_AUX6_DEBUG_O[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING", REG_SMC, 0x9, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING[0]), 0, 0 },
+	{ "ixIDDCCIF02_DBG_DCCIF_C", REG_SMC, 0x9, &ixIDDCCIF02_DBG_DCCIF_C[0], sizeof(ixIDDCCIF02_DBG_DCCIF_C)/sizeof(ixIDDCCIF02_DBG_DCCIF_C[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR8", REG_SMC, 0x9, &ixAUDIO_DESCRIPTOR8[0], sizeof(ixAUDIO_DESCRIPTOR8)/sizeof(ixAUDIO_DESCRIPTOR8[0]), 0, 0 },
+	{ "mmINTERRUPT_STATUS", REG_MMIO, 0x9, &mmINTERRUPT_STATUS[0], sizeof(mmINTERRUPT_STATUS)/sizeof(mmINTERRUPT_STATUS[0]), 0, 0 },
+	{ "ixDCIO_DEBUG9", REG_SMC, 0x9, &ixDCIO_DEBUG9[0], sizeof(ixDCIO_DEBUG9)/sizeof(ixDCIO_DEBUG9[0]), 0, 0 },
+	{ "ixATTR09", REG_SMC, 0x9, &ixATTR09[0], sizeof(ixATTR09)/sizeof(ixATTR09[0]), 0, 0 },
+	{ "ixCRT09", REG_SMC, 0x9, &ixCRT09[0], sizeof(ixCRT09)/sizeof(ixCRT09[0]), 0, 0 },
+	{ "ixDP_AUX1_DEBUG_Q", REG_SMC, 0x90, &ixDP_AUX1_DEBUG_Q[0], sizeof(ixDP_AUX1_DEBUG_Q)/sizeof(ixDP_AUX1_DEBUG_Q[0]), 0, 0 },
+	{ "ixDP_AUX2_DEBUG_Q", REG_SMC, 0x91, &ixDP_AUX2_DEBUG_Q[0], sizeof(ixDP_AUX2_DEBUG_Q)/sizeof(ixDP_AUX2_DEBUG_Q[0]), 0, 0 },
+	{ "ixDP_AUX3_DEBUG_Q", REG_SMC, 0x92, &ixDP_AUX3_DEBUG_Q[0], sizeof(ixDP_AUX3_DEBUG_Q)/sizeof(ixDP_AUX3_DEBUG_Q[0]), 0, 0 },
+	{ "ixDP_AUX4_DEBUG_Q", REG_SMC, 0x93, &ixDP_AUX4_DEBUG_Q[0], sizeof(ixDP_AUX4_DEBUG_Q)/sizeof(ixDP_AUX4_DEBUG_Q[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_P", REG_SMC, 0x94, &ixDP_AUX5_DEBUG_P[0], sizeof(ixDP_AUX5_DEBUG_P)/sizeof(ixDP_AUX5_DEBUG_P[0]), 0, 0 },
+	{ "ixDP_AUX5_DEBUG_Q", REG_SMC, 0x95, &ixDP_AUX5_DEBUG_Q[0], sizeof(ixDP_AUX5_DEBUG_Q)/sizeof(ixDP_AUX5_DEBUG_Q[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_P", REG_SMC, 0x96, &ixDP_AUX6_DEBUG_P[0], sizeof(ixDP_AUX6_DEBUG_P)/sizeof(ixDP_AUX6_DEBUG_P[0]), 0, 0 },
+	{ "ixDP_AUX6_DEBUG_Q", REG_SMC, 0x97, &ixDP_AUX6_DEBUG_Q[0], sizeof(ixDP_AUX6_DEBUG_Q)/sizeof(ixDP_AUX6_DEBUG_Q[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG", REG_SMC, 0xa, &ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_OFFSET_DEBUG[0]), 0, 0 },
+	{ "ixDMIF_DEBUG02_CORE1", REG_SMC, 0xa, &ixDMIF_DEBUG02_CORE1[0], sizeof(ixDMIF_DEBUG02_CORE1)/sizeof(ixDMIF_DEBUG02_CORE1[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR9", REG_SMC, 0xa, &ixAUDIO_DESCRIPTOR9[0], sizeof(ixAUDIO_DESCRIPTOR9)/sizeof(ixAUDIO_DESCRIPTOR9[0]), 0, 0 },
+	{ "ixDCIO_DEBUGA", REG_SMC, 0xa, &ixDCIO_DEBUGA[0], sizeof(ixDCIO_DEBUGA)/sizeof(ixDCIO_DEBUGA[0]), 0, 0 },
+	{ "ixATTR0A", REG_SMC, 0xa, &ixATTR0A[0], sizeof(ixATTR0A)/sizeof(ixATTR0A[0]), 0, 0 },
+	{ "ixCRT0A", REG_SMC, 0xa, &ixCRT0A[0], sizeof(ixCRT0A)/sizeof(ixCRT0A[0]), 0, 0 },
+	{ "ixIDDCCIF04_DBG_DCCIF_E", REG_SMC, 0xb, &ixIDDCCIF04_DBG_DCCIF_E[0], sizeof(ixIDDCCIF04_DBG_DCCIF_E)/sizeof(ixIDDCCIF04_DBG_DCCIF_E[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR10", REG_SMC, 0xb, &ixAUDIO_DESCRIPTOR10[0], sizeof(ixAUDIO_DESCRIPTOR10)/sizeof(ixAUDIO_DESCRIPTOR10[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION6", REG_SMC, 0xb, &ixSINK_DESCRIPTION6[0], sizeof(ixSINK_DESCRIPTION6)/sizeof(ixSINK_DESCRIPTION6[0]), 0, 0 },
+	{ "ixDCIO_DEBUGB", REG_SMC, 0xb, &ixDCIO_DEBUGB[0], sizeof(ixDCIO_DEBUGB)/sizeof(ixDCIO_DEBUGB[0]), 0, 0 },
+	{ "ixATTR0B", REG_SMC, 0xb, &ixATTR0B[0], sizeof(ixATTR0B)/sizeof(ixATTR0B[0]), 0, 0 },
+	{ "ixCRT0B", REG_SMC, 0xb, &ixCRT0B[0], sizeof(ixCRT0B)/sizeof(ixCRT0B[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA", REG_SMC, 0xc, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA[0]), 0, 0 },
+	{ "ixIDDCCIF05_DBG_DCCIF_F", REG_SMC, 0xc, &ixIDDCCIF05_DBG_DCCIF_F[0], sizeof(ixIDDCCIF05_DBG_DCCIF_F)/sizeof(ixIDDCCIF05_DBG_DCCIF_F[0]), 0, 0 },
+	{ "mmWALL_CLOCK_COUNTER", REG_MMIO, 0xc, &mmWALL_CLOCK_COUNTER[0], sizeof(mmWALL_CLOCK_COUNTER)/sizeof(mmWALL_CLOCK_COUNTER[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION7", REG_SMC, 0xc, &ixSINK_DESCRIPTION7[0], sizeof(ixSINK_DESCRIPTION7)/sizeof(ixSINK_DESCRIPTION7[0]), 0, 0 },
+	{ "ixMVP_DEBUG_12", REG_SMC, 0xc, &ixMVP_DEBUG_12[0], sizeof(ixMVP_DEBUG_12)/sizeof(ixMVP_DEBUG_12[0]), 0, 0 },
+	{ "ixDCIO_DEBUGC", REG_SMC, 0xc, &ixDCIO_DEBUGC[0], sizeof(ixDCIO_DEBUGC)/sizeof(ixDCIO_DEBUGC[0]), 0, 0 },
+	{ "ixATTR0C", REG_SMC, 0xc, &ixATTR0C[0], sizeof(ixATTR0C)/sizeof(ixATTR0C[0]), 0, 0 },
+	{ "ixCRT0C", REG_SMC, 0xc, &ixCRT0C[0], sizeof(ixCRT0C)/sizeof(ixCRT0C[0]), 0, 0 },
+	{ "mmVGA_RENDER_CONTROL", REG_MMIO, 0xc0, &mmVGA_RENDER_CONTROL[0], sizeof(mmVGA_RENDER_CONTROL)/sizeof(mmVGA_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SEQUENCER_RESET_CONTROL", REG_MMIO, 0xc1, &mmVGA_SEQUENCER_RESET_CONTROL[0], sizeof(mmVGA_SEQUENCER_RESET_CONTROL)/sizeof(mmVGA_SEQUENCER_RESET_CONTROL[0]), 0, 0 },
+	{ "mmVGA_MODE_CONTROL", REG_MMIO, 0xc2, &mmVGA_MODE_CONTROL[0], sizeof(mmVGA_MODE_CONTROL)/sizeof(mmVGA_MODE_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SURFACE_PITCH_SELECT", REG_MMIO, 0xc3, &mmVGA_SURFACE_PITCH_SELECT[0], sizeof(mmVGA_SURFACE_PITCH_SELECT)/sizeof(mmVGA_SURFACE_PITCH_SELECT[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS", REG_MMIO, 0xc4, &mmVGA_MEMORY_BASE_ADDRESS[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS)/sizeof(mmVGA_MEMORY_BASE_ADDRESS[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_INDEX", REG_MMIO, 0xc5, &mmVGA_TEST_DEBUG_INDEX[0], sizeof(mmVGA_TEST_DEBUG_INDEX)/sizeof(mmVGA_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmVGA_DISPBUF1_SURFACE_ADDR", REG_MMIO, 0xc6, &mmVGA_DISPBUF1_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF1_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF1_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_TEST_DEBUG_DATA", REG_MMIO, 0xc7, &mmVGA_TEST_DEBUG_DATA[0], sizeof(mmVGA_TEST_DEBUG_DATA)/sizeof(mmVGA_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGA_DISPBUF2_SURFACE_ADDR", REG_MMIO, 0xc8, &mmVGA_DISPBUF2_SURFACE_ADDR[0], sizeof(mmVGA_DISPBUF2_SURFACE_ADDR)/sizeof(mmVGA_DISPBUF2_SURFACE_ADDR[0]), 0, 0 },
+	{ "mmVGA_MEMORY_BASE_ADDRESS_HIGH", REG_MMIO, 0xc9, &mmVGA_MEMORY_BASE_ADDRESS_HIGH[0], sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH)/sizeof(mmVGA_MEMORY_BASE_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmVGA_HDP_CONTROL", REG_MMIO, 0xca, &mmVGA_HDP_CONTROL[0], sizeof(mmVGA_HDP_CONTROL)/sizeof(mmVGA_HDP_CONTROL[0]), 0, 0 },
+	{ "mmVGA_CACHE_CONTROL", REG_MMIO, 0xcb, &mmVGA_CACHE_CONTROL[0], sizeof(mmVGA_CACHE_CONTROL)/sizeof(mmVGA_CACHE_CONTROL[0]), 0, 0 },
+	{ "mmD1VGA_CONTROL", REG_MMIO, 0xcc, &mmD1VGA_CONTROL[0], sizeof(mmD1VGA_CONTROL)/sizeof(mmD1VGA_CONTROL[0]), 0, 0 },
+	{ "mmD2VGA_CONTROL", REG_MMIO, 0xce, &mmD2VGA_CONTROL[0], sizeof(mmD2VGA_CONTROL)/sizeof(mmD2VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_HW_DEBUG", REG_MMIO, 0xcf, &mmVGA_HW_DEBUG[0], sizeof(mmVGA_HW_DEBUG)/sizeof(mmVGA_HW_DEBUG[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN", REG_SMC, 0xd, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR12", REG_SMC, 0xd, &ixAUDIO_DESCRIPTOR12[0], sizeof(ixAUDIO_DESCRIPTOR12)/sizeof(ixAUDIO_DESCRIPTOR12[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION8", REG_SMC, 0xd, &ixSINK_DESCRIPTION8[0], sizeof(ixSINK_DESCRIPTION8)/sizeof(ixSINK_DESCRIPTION8[0]), 0, 0 },
+	{ "ixMVP_DEBUG_13", REG_SMC, 0xd, &ixMVP_DEBUG_13[0], sizeof(ixMVP_DEBUG_13)/sizeof(ixMVP_DEBUG_13[0]), 0, 0 },
+	{ "ixDCIO_DEBUGD", REG_SMC, 0xd, &ixDCIO_DEBUGD[0], sizeof(ixDCIO_DEBUGD)/sizeof(ixDCIO_DEBUGD[0]), 0, 0 },
+	{ "ixATTR0D", REG_SMC, 0xd, &ixATTR0D[0], sizeof(ixATTR0D)/sizeof(ixATTR0D[0]), 0, 0 },
+	{ "ixCRT0D", REG_SMC, 0xd, &ixCRT0D[0], sizeof(ixCRT0D)/sizeof(ixCRT0D[0]), 0, 0 },
+	{ "mmVGA_STATUS", REG_MMIO, 0xd0, &mmVGA_STATUS[0], sizeof(mmVGA_STATUS)/sizeof(mmVGA_STATUS[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_CONTROL", REG_MMIO, 0xd1, &mmVGA_INTERRUPT_CONTROL[0], sizeof(mmVGA_INTERRUPT_CONTROL)/sizeof(mmVGA_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "mmVGA_STATUS_CLEAR", REG_MMIO, 0xd2, &mmVGA_STATUS_CLEAR[0], sizeof(mmVGA_STATUS_CLEAR)/sizeof(mmVGA_STATUS_CLEAR[0]), 0, 0 },
+	{ "mmVGA_INTERRUPT_STATUS", REG_MMIO, 0xd3, &mmVGA_INTERRUPT_STATUS[0], sizeof(mmVGA_INTERRUPT_STATUS)/sizeof(mmVGA_INTERRUPT_STATUS[0]), 0, 0 },
+	{ "mmVGA_MAIN_CONTROL", REG_MMIO, 0xd4, &mmVGA_MAIN_CONTROL[0], sizeof(mmVGA_MAIN_CONTROL)/sizeof(mmVGA_MAIN_CONTROL[0]), 0, 0 },
+	{ "mmVGA_TEST_CONTROL", REG_MMIO, 0xd5, &mmVGA_TEST_CONTROL[0], sizeof(mmVGA_TEST_CONTROL)/sizeof(mmVGA_TEST_CONTROL[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_INDEX", REG_MMIO, 0xd6, &mmVGA_DEBUG_READBACK_INDEX[0], sizeof(mmVGA_DEBUG_READBACK_INDEX)/sizeof(mmVGA_DEBUG_READBACK_INDEX[0]), 0, 0 },
+	{ "mmVGA_DEBUG_READBACK_DATA", REG_MMIO, 0xd7, &mmVGA_DEBUG_READBACK_DATA[0], sizeof(mmVGA_DEBUG_READBACK_DATA)/sizeof(mmVGA_DEBUG_READBACK_DATA[0]), 0, 0 },
+	{ "mmVGA25_PPLL_REF_DIV", REG_MMIO, 0xd8, &mmVGA25_PPLL_REF_DIV[0], sizeof(mmVGA25_PPLL_REF_DIV)/sizeof(mmVGA25_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmVGA28_PPLL_REF_DIV", REG_MMIO, 0xd9, &mmVGA28_PPLL_REF_DIV[0], sizeof(mmVGA28_PPLL_REF_DIV)/sizeof(mmVGA28_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmVGA41_PPLL_REF_DIV", REG_MMIO, 0xda, &mmVGA41_PPLL_REF_DIV[0], sizeof(mmVGA41_PPLL_REF_DIV)/sizeof(mmVGA41_PPLL_REF_DIV[0]), 0, 0 },
+	{ "mmVGA25_PPLL_FB_DIV", REG_MMIO, 0xdc, &mmVGA25_PPLL_FB_DIV[0], sizeof(mmVGA25_PPLL_FB_DIV)/sizeof(mmVGA25_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmVGA28_PPLL_FB_DIV", REG_MMIO, 0xdd, &mmVGA28_PPLL_FB_DIV[0], sizeof(mmVGA28_PPLL_FB_DIV)/sizeof(mmVGA28_PPLL_FB_DIV[0]), 0, 0 },
+	{ "mmVGA41_PPLL_FB_DIV", REG_MMIO, 0xde, &mmVGA41_PPLL_FB_DIV[0], sizeof(mmVGA41_PPLL_FB_DIV)/sizeof(mmVGA41_PPLL_FB_DIV[0]), 0, 0 },
+	{ "ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX", REG_SMC, 0xe, &ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0], sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX)/sizeof(ixAZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX[0]), 0, 0 },
+	{ "mmSTREAM_SYNCHRONIZATION", REG_MMIO, 0xe, &mmSTREAM_SYNCHRONIZATION[0], sizeof(mmSTREAM_SYNCHRONIZATION)/sizeof(mmSTREAM_SYNCHRONIZATION[0]), 0, 0 },
+	{ "ixAUDIO_DESCRIPTOR13", REG_SMC, 0xe, &ixAUDIO_DESCRIPTOR13[0], sizeof(ixAUDIO_DESCRIPTOR13)/sizeof(ixAUDIO_DESCRIPTOR13[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION9", REG_SMC, 0xe, &ixSINK_DESCRIPTION9[0], sizeof(ixSINK_DESCRIPTION9)/sizeof(ixSINK_DESCRIPTION9[0]), 0, 0 },
+	{ "ixMVP_DEBUG_14", REG_SMC, 0xe, &ixMVP_DEBUG_14[0], sizeof(ixMVP_DEBUG_14)/sizeof(ixMVP_DEBUG_14[0]), 0, 0 },
+	{ "ixDCIO_DEBUGE", REG_SMC, 0xe, &ixDCIO_DEBUGE[0], sizeof(ixDCIO_DEBUGE)/sizeof(ixDCIO_DEBUGE[0]), 0, 0 },
+	{ "ixATTR0E", REG_SMC, 0xe, &ixATTR0E[0], sizeof(ixATTR0E)/sizeof(ixATTR0E[0]), 0, 0 },
+	{ "ixCRT0E", REG_SMC, 0xe, &ixCRT0E[0], sizeof(ixCRT0E)/sizeof(ixCRT0E[0]), 0, 0 },
+	{ "mmVGA25_PPLL_POST_DIV", REG_MMIO, 0xe0, &mmVGA25_PPLL_POST_DIV[0], sizeof(mmVGA25_PPLL_POST_DIV)/sizeof(mmVGA25_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmVGA28_PPLL_POST_DIV", REG_MMIO, 0xe1, &mmVGA28_PPLL_POST_DIV[0], sizeof(mmVGA28_PPLL_POST_DIV)/sizeof(mmVGA28_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmVGA41_PPLL_POST_DIV", REG_MMIO, 0xe2, &mmVGA41_PPLL_POST_DIV[0], sizeof(mmVGA41_PPLL_POST_DIV)/sizeof(mmVGA41_PPLL_POST_DIV[0]), 0, 0 },
+	{ "mmVGA25_PPLL_ANALOG", REG_MMIO, 0xe4, &mmVGA25_PPLL_ANALOG[0], sizeof(mmVGA25_PPLL_ANALOG)/sizeof(mmVGA25_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmVGA28_PPLL_ANALOG", REG_MMIO, 0xe5, &mmVGA28_PPLL_ANALOG[0], sizeof(mmVGA28_PPLL_ANALOG)/sizeof(mmVGA28_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmVGA41_PPLL_ANALOG", REG_MMIO, 0xe6, &mmVGA41_PPLL_ANALOG[0], sizeof(mmVGA41_PPLL_ANALOG)/sizeof(mmVGA41_PPLL_ANALOG[0]), 0, 0 },
+	{ "mmVGA0_CRTC8_DATA", REG_MMIO, 0xed, NULL, 0, 0, 0 },
+	{ "mmVGA0_CRTC8_IDX", REG_MMIO, 0xed, NULL, 0, 0, 0 },
+	{ "mmCRTC8_DATA", REG_MMIO, 0xed, &mmCRTC8_DATA[0], sizeof(mmCRTC8_DATA)/sizeof(mmCRTC8_DATA[0]), 0, 0 },
+	{ "mmCRTC8_IDX", REG_MMIO, 0xed, &mmCRTC8_IDX[0], sizeof(mmCRTC8_IDX)/sizeof(mmCRTC8_IDX[0]), 0, 0 },
+	{ "mmVGA0_GENFC_WT", REG_MMIO, 0xee, NULL, 0, 0, 0 },
+	{ "mmVGA0_GENS1", REG_MMIO, 0xee, NULL, 0, 0, 0 },
+	{ "mmGENFC_WT", REG_MMIO, 0xee, &mmGENFC_WT[0], sizeof(mmGENFC_WT)/sizeof(mmGENFC_WT[0]), 0, 0 },
+	{ "mmGENS1", REG_MMIO, 0xee, &mmGENS1[0], sizeof(mmGENS1)/sizeof(mmGENS1[0]), 0, 0 },
+	{ "ixSINK_DESCRIPTION10", REG_SMC, 0xf, &ixSINK_DESCRIPTION10[0], sizeof(ixSINK_DESCRIPTION10)/sizeof(ixSINK_DESCRIPTION10[0]), 0, 0 },
+	{ "ixMVP_DEBUG_15", REG_SMC, 0xf, &ixMVP_DEBUG_15[0], sizeof(ixMVP_DEBUG_15)/sizeof(ixMVP_DEBUG_15[0]), 0, 0 },
+	{ "ixDCIO_DEBUGF", REG_SMC, 0xf, &ixDCIO_DEBUGF[0], sizeof(ixDCIO_DEBUGF)/sizeof(ixDCIO_DEBUGF[0]), 0, 0 },
+	{ "ixATTR0F", REG_SMC, 0xf, &ixATTR0F[0], sizeof(ixATTR0F)/sizeof(ixATTR0F[0]), 0, 0 },
+	{ "ixCRT0F", REG_SMC, 0xf, &ixCRT0F[0], sizeof(ixCRT0F)/sizeof(ixCRT0F[0]), 0, 0 },
+	{ "mmGENMO_WT", REG_MMIO, 0xf0, &mmGENMO_WT[0], sizeof(mmGENMO_WT)/sizeof(mmGENMO_WT[0]), 0, 0 },
+	{ "mmGENENB", REG_MMIO, 0xf0, &mmGENENB[0], sizeof(mmGENENB)/sizeof(mmGENENB[0]), 0, 0 },
+	{ "mmGENS0", REG_MMIO, 0xf0, &mmGENS0[0], sizeof(mmGENS0)/sizeof(mmGENS0[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID", REG_SMC, 0xf00, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID", REG_SMC, 0xf02, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID[0]), 0, 0 },
+	{ "ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT", REG_SMC, 0xf04, &ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0], sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT)/sizeof(ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT[0]), 0, 0 },
+	{ "mmDAC_R_INDEX", REG_MMIO, 0xf1, &mmDAC_R_INDEX[0], sizeof(mmDAC_R_INDEX)/sizeof(mmDAC_R_INDEX[0]), 0, 0 },
+	{ "mmSEQ8_DATA", REG_MMIO, 0xf1, &mmSEQ8_DATA[0], sizeof(mmSEQ8_DATA)/sizeof(mmSEQ8_DATA[0]), 0, 0 },
+	{ "mmDAC_MASK", REG_MMIO, 0xf1, &mmDAC_MASK[0], sizeof(mmDAC_MASK)/sizeof(mmDAC_MASK[0]), 0, 0 },
+	{ "mmDAC_W_INDEX", REG_MMIO, 0xf2, &mmDAC_W_INDEX[0], sizeof(mmDAC_W_INDEX)/sizeof(mmDAC_W_INDEX[0]), 0, 0 },
+	{ "mmGENFC_RD", REG_MMIO, 0xf2, &mmGENFC_RD[0], sizeof(mmGENFC_RD)/sizeof(mmGENFC_RD[0]), 0, 0 },
+	{ "mmGRPH8_DATA", REG_MMIO, 0xf3, &mmGRPH8_DATA[0], sizeof(mmGRPH8_DATA)/sizeof(mmGRPH8_DATA[0]), 0, 0 },
+	{ "mmGRPH8_IDX", REG_MMIO, 0xf3, &mmGRPH8_IDX[0], sizeof(mmGRPH8_IDX)/sizeof(mmGRPH8_IDX[0]), 0, 0 },
+	{ "mmGENMO_RD", REG_MMIO, 0xf3, &mmGENMO_RD[0], sizeof(mmGENMO_RD)/sizeof(mmGENMO_RD[0]), 0, 0 },
+	{ "mmVGA1_CRTC8_DATA", REG_MMIO, 0xf5, NULL, 0, 0, 0 },
+	{ "mmVGA1_CRTC8_IDX", REG_MMIO, 0xf5, NULL, 0, 0, 0 },
+	{ "mmVGA1_GENFC_WT", REG_MMIO, 0xf6, NULL, 0, 0, 0 },
+	{ "mmVGA1_GENS1", REG_MMIO, 0xf6, NULL, 0, 0, 0 },
+	{ "mmD3VGA_CONTROL", REG_MMIO, 0xf8, &mmD3VGA_CONTROL[0], sizeof(mmD3VGA_CONTROL)/sizeof(mmD3VGA_CONTROL[0]), 0, 0 },
+	{ "mmD4VGA_CONTROL", REG_MMIO, 0xf9, &mmD4VGA_CONTROL[0], sizeof(mmD4VGA_CONTROL)/sizeof(mmD4VGA_CONTROL[0]), 0, 0 },
+	{ "mmD5VGA_CONTROL", REG_MMIO, 0xfa, &mmD5VGA_CONTROL[0], sizeof(mmD5VGA_CONTROL)/sizeof(mmD5VGA_CONTROL[0]), 0, 0 },
+	{ "mmD6VGA_CONTROL", REG_MMIO, 0xfb, &mmD6VGA_CONTROL[0], sizeof(mmD6VGA_CONTROL)/sizeof(mmD6VGA_CONTROL[0]), 0, 0 },
+	{ "mmVGA_SOURCE_SELECT", REG_MMIO, 0xfc, &mmVGA_SOURCE_SELECT[0], sizeof(mmVGA_SOURCE_SELECT)/sizeof(mmVGA_SOURCE_SELECT[0]), 0, 0 },
diff --git a/src/lib/ip/gfx60.c b/src/lib/ip/gfx60.c
new file mode 100644
index 0000000..73cf787
--- /dev/null
+++ b/src/lib/ip/gfx60.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gfx60_bits.i"
+
+static const struct umr_reg gfx60_registers[] = {
+#include "gfx60_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_gfx60(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gfx60";
+	ip->no_regs = sizeof(gfx60_registers)/sizeof(gfx60_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gfx60_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 1) ? grant : deny;
+	memcpy(ip->regs, gfx60_registers, sizeof(gfx60_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gfx60_bits.i b/src/lib/ip/gfx60_bits.i
new file mode 100644
index 0000000..3cc4326
--- /dev/null
+++ b/src/lib/ip/gfx60_bits.i
@@ -0,0 +1,8311 @@
+static struct umr_bitfield ixCLIPPER_DEBUG_REG00[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "clipcode_fifo_fifo_empty", 21, 21, &umr_bitfield_default },
+	 { "clipcode_fifo_full", 22, 22, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 8, 8, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_full", 12, 12, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 11, 11, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_full", 16, 16, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_empty", 13, 13, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_full", 14, 14, &umr_bitfield_default },
+	 { "su_clip_baryc_free", 9, 10, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_empty", 17, 17, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_full", 18, 18, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_write", 31, 31, &umr_bitfield_default },
+	 { "vgt_to_clips_fifo_empty", 19, 19, &umr_bitfield_default },
+	 { "vgt_to_clips_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_empty", 23, 23, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_write", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG01[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_extra_bc_valid", 8, 10, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 28, 28, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "clip_to_outsm_deallocate_slot", 17, 19, &umr_bitfield_default },
+	 { "clip_to_outsm_null_primitive", 20, 20, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_deallocate", 14, 16, &umr_bitfield_default },
+	 { "clip_vert_vte_valid", 11, 13, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_empty", 31, 31, &umr_bitfield_default },
+	 { "vte_out_clip_rd_extra_bc_valid", 24, 24, &umr_bitfield_default },
+	 { "vte_out_clip_rd_vertex_store_indx", 26, 27, &umr_bitfield_default },
+	 { "vte_out_clip_rd_vte_naninf_kill", 25, 25, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_0", 23, 23, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_1", 22, 22, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_2", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG02[] = {
+	 { "clip_extra_bc_valid", 0, 2, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 28, 28, &umr_bitfield_default },
+	 { "clip_to_clipga_extra_bc_coords", 20, 20, &umr_bitfield_default },
+	 { "clip_to_clipga_vte_naninf_kill", 21, 21, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "clip_to_outsm_clipped_prim", 24, 24, &umr_bitfield_default },
+	 { "clip_to_outsm_clip_seq_indx", 6, 7, &umr_bitfield_default },
+	 { "clip_to_outsm_end_of_packet", 22, 22, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_empty", 31, 31, &umr_bitfield_default },
+	 { "clip_to_outsm_first_prim_of_slot", 23, 23, &umr_bitfield_default },
+	 { "clip_to_outsm_null_primitive", 25, 25, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_0", 16, 19, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_1", 12, 15, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_2", 8, 11, &umr_bitfield_default },
+	 { "clip_vert_vte_valid", 3, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG03[] = {
+	 { "clipsm0_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG04[] = {
+	 { "clipsm0_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG05[] = {
+	 { "clipsm1_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG06[] = {
+	 { "clipsm1_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG07[] = {
+	 { "clipsm2_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG08[] = {
+	 { "clipsm2_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG09[] = {
+	 { "clipsm3_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG10[] = {
+	 { "clipsm3_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG11[] = {
+	 { "clipsm0_clip_to_clipga_clip_primitive", 7, 7, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_clip_to_outsm_cnt", 20, 23, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_event", 3, 3, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_prim_valid", 27, 27, &umr_bitfield_default },
+	 { "clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt", 31, 31, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_clip_primitive", 6, 6, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_clip_to_outsm_cnt", 16, 19, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_event", 2, 2, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_prim_valid", 26, 26, &umr_bitfield_default },
+	 { "clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_clip_primitive", 5, 5, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_clip_to_outsm_cnt", 12, 15, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_event", 1, 1, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_prim_valid", 25, 25, &umr_bitfield_default },
+	 { "clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_clip_primitive", 4, 4, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_clip_to_outsm_cnt", 8, 11, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_event", 0, 0, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_prim_valid", 24, 24, &umr_bitfield_default },
+	 { "clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG12[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_priority_available_clip_verts", 13, 17, &umr_bitfield_default },
+	 { "clip_priority_available_vte_out_clip", 8, 12, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_load", 22, 23, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_out", 18, 19, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_vert", 20, 21, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_clip_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_clip_primitive", 28, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_clip_primitive", 26, 26, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 27, 27, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_clip_primitive", 24, 24, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG13[] = {
+	 { "ccgen_to_clipcc_fifo_empty", 16, 16, &umr_bitfield_default },
+	 { "clipcc_vertex_store_indx", 12, 13, &umr_bitfield_default },
+	 { "clipcode_fifo_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_out_cnt", 17, 20, &umr_bitfield_default },
+	 { "clprim_clip_primitive", 5, 5, &umr_bitfield_default },
+	 { "clprim_cull_primitive", 6, 6, &umr_bitfield_default },
+	 { "clprim_in_back_state_var_indx", 0, 2, &umr_bitfield_default },
+	 { "outsm_clr_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "outsm_clr_fifo_contents", 24, 28, &umr_bitfield_default },
+	 { "outsm_clr_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "outsm_clr_fifo_write", 31, 31, &umr_bitfield_default },
+	 { "outsm_clr_rd_clipsm_wait", 23, 23, &umr_bitfield_default },
+	 { "outsm_clr_rd_orig_vertices", 21, 22, &umr_bitfield_default },
+	 { "point_clip_candidate", 3, 3, &umr_bitfield_default },
+	 { "prim_back_valid", 7, 7, &umr_bitfield_default },
+	 { "prim_nan_kill", 4, 4, &umr_bitfield_default },
+	 { "vertval_bits_vertex_cc_next_valid", 8, 11, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_empty", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG14[] = {
+	 { "clprim_in_back_deallocate_slot", 21, 23, &umr_bitfield_default },
+	 { "clprim_in_back_end_of_packet", 19, 19, &umr_bitfield_default },
+	 { "clprim_in_back_event_id", 24, 29, &umr_bitfield_default },
+	 { "clprim_in_back_event", 30, 30, &umr_bitfield_default },
+	 { "clprim_in_back_first_prim_of_slot", 20, 20, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_0", 12, 17, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_1", 6, 11, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_2", 0, 5, &umr_bitfield_default },
+	 { "outputclprimtoclip_null_primitive", 18, 18, &umr_bitfield_default },
+	 { "prim_back_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG15[] = {
+	 { "primic_to_clprim_fifo_vertex_store_indx_0", 26, 30, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_1", 21, 25, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_2", 16, 20, &umr_bitfield_default },
+	 { "primic_to_clprim_valid", 31, 31, &umr_bitfield_default },
+	 { "vertval_bits_vertex_vertex_store_msb", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG16[] = {
+	 { "sm0_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm0_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm0_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "sm0_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm0_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm0_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm0_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm0_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm0_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm0_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm0_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG17[] = {
+	 { "sm1_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm1_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm1_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "sm1_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm1_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm1_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm1_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm1_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm1_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm1_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm1_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG18[] = {
+	 { "sm2_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm2_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm2_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "sm2_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm2_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm2_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm2_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm2_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm2_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm2_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm2_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG19[] = {
+	 { "sm3_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm3_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm3_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+	 { "sm3_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm3_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm3_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm3_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm3_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm3_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm3_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm3_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_HW_ID[] = {
+	 { "CU_ID", 8, 11, &umr_bitfield_default },
+	 { "ME_ID", 30, 31, &umr_bitfield_default },
+	 { "PIPE_ID", 6, 7, &umr_bitfield_default },
+	 { "QUEUE_ID", 24, 26, &umr_bitfield_default },
+	 { "SE_ID", 13, 13, &umr_bitfield_default },
+	 { "SH_ID", 12, 12, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "STATE_ID", 27, 29, &umr_bitfield_default },
+	 { "TG_ID", 16, 19, &umr_bitfield_default },
+	 { "VM_ID", 20, 23, &umr_bitfield_default },
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_GPR_ALLOC[] = {
+	 { "SGPR_BASE", 16, 21, &umr_bitfield_default },
+	 { "SGPR_SIZE", 24, 27, &umr_bitfield_default },
+	 { "VGPR_BASE", 0, 5, &umr_bitfield_default },
+	 { "VGPR_SIZE", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_LDS_ALLOC[] = {
+	 { "LDS_BASE", 0, 7, &umr_bitfield_default },
+	 { "LDS_SIZE", 12, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_STS[] = {
+	 { "EXP_CNT", 4, 6, &umr_bitfield_default },
+	 { "LGKM_CNT", 8, 12, &umr_bitfield_default },
+	 { "VALU_CNT", 13, 15, &umr_bitfield_default },
+	 { "VM_CNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG0[] = {
+	 { "cl_dyn_sclk_vld", 31, 31, &umr_bitfield_default },
+	 { "event_gated", 28, 28, &umr_bitfield_default },
+	 { "event_id_gated", 22, 27, &umr_bitfield_default },
+	 { "geom_busy", 21, 21, &umr_bitfield_default },
+	 { "geom_enable", 15, 15, &umr_bitfield_default },
+	 { "ge_stallb", 14, 14, &umr_bitfield_default },
+	 { "pfifo_busy", 19, 19, &umr_bitfield_default },
+	 { "pmode_prim_gated", 29, 29, &umr_bitfield_default },
+	 { "pmode_state", 8, 13, &umr_bitfield_default },
+	 { "su_baryc_cntl_state", 0, 1, &umr_bitfield_default },
+	 { "su_clip_baryc_free", 16, 17, &umr_bitfield_default },
+	 { "su_clip_rtr", 18, 18, &umr_bitfield_default },
+	 { "su_cntl_busy", 20, 20, &umr_bitfield_default },
+	 { "su_cntl_state", 2, 5, &umr_bitfield_default },
+	 { "su_dyn_sclk_vld", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG1[] = {
+	 { "x_sort0_gated_23_8", 16, 31, &umr_bitfield_default },
+	 { "y_sort0_gated_23_8", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG2[] = {
+	 { "x_sort1_gated_23_8", 16, 31, &umr_bitfield_default },
+	 { "y_sort1_gated_23_8", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG3[] = {
+	 { "x_sort2_gated_23_8", 16, 31, &umr_bitfield_default },
+	 { "y_sort2_gated_23_8", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG4[] = {
+	 { "attr_indx_sort0_gated", 0, 13, &umr_bitfield_default },
+	 { "backfacing_gated", 15, 15, &umr_bitfield_default },
+	 { "clipped_gated", 19, 19, &umr_bitfield_default },
+	 { "dealloc_slot_gated", 20, 22, &umr_bitfield_default },
+	 { "diamond_rule_gated", 24, 25, &umr_bitfield_default },
+	 { "eop_gated", 31, 31, &umr_bitfield_default },
+	 { "fpov_gated", 29, 30, &umr_bitfield_default },
+	 { "null_prim_gated", 14, 14, &umr_bitfield_default },
+	 { "st_indx_gated", 16, 18, &umr_bitfield_default },
+	 { "type_gated", 26, 28, &umr_bitfield_default },
+	 { "xmajor_gated", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG5[] = {
+	 { "attr_indx_sort1_gated", 14, 27, &umr_bitfield_default },
+	 { "attr_indx_sort2_gated", 0, 13, &umr_bitfield_default },
+	 { "pa_reg_sclk_vld", 31, 31, &umr_bitfield_default },
+	 { "provoking_vtx_gated", 28, 29, &umr_bitfield_default },
+	 { "valid_prim_gated", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG30[] = {
+	 { "dynamic_hs_p0_q", 24, 24, &umr_bitfield_default },
+	 { "event_or_null_p0_q", 3, 3, &umr_bitfield_default },
+	 { "first_data_chunk_invalid_p0_q", 27, 27, &umr_bitfield_default },
+	 { "first_data_ret_of_req_p0_q", 26, 26, &umr_bitfield_default },
+	 { "first_fetch_of_tg_p0_q", 25, 25, &umr_bitfield_default },
+	 { "last_tf_of_tg", 19, 19, &umr_bitfield_default },
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "pipe0_tf_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipe1_tf_rtr", 6, 6, &umr_bitfield_default },
+	 { "pipe2_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe2_rtr", 7, 7, &umr_bitfield_default },
+	 { "pipe4_dr", 30, 30, &umr_bitfield_default },
+	 { "pipe4_rtr", 31, 31, &umr_bitfield_default },
+	 { "tf_fetch_state_q", 16, 18, &umr_bitfield_default },
+	 { "tf_pointer_p0_q", 20, 23, &umr_bitfield_default },
+	 { "tf_xfer_count_p2_q", 28, 29, &umr_bitfield_default },
+	 { "ttp_patch_fifo_empty", 9, 9, &umr_bitfield_default },
+	 { "ttp_patch_fifo_full", 8, 8, &umr_bitfield_default },
+	 { "ttp_tf0_fifo_empty", 10, 10, &umr_bitfield_default },
+	 { "ttp_tf1_fifo_empty", 11, 11, &umr_bitfield_default },
+	 { "ttp_tf2_fifo_empty", 12, 12, &umr_bitfield_default },
+	 { "ttp_tf3_fifo_empty", 13, 13, &umr_bitfield_default },
+	 { "ttp_tf4_fifo_empty", 14, 14, &umr_bitfield_default },
+	 { "ttp_tf5_fifo_empty", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG31[] = {
+	 { "inner_ring_done_q", 31, 31, &umr_bitfield_default },
+	 { "outer_ring_done_q", 30, 30, &umr_bitfield_default },
+	 { "pg_con_inner_point1_rts", 22, 22, &umr_bitfield_default },
+	 { "pg_con_inner_point2_rts", 23, 23, &umr_bitfield_default },
+	 { "pg_con_outer_point1_rts", 20, 20, &umr_bitfield_default },
+	 { "pg_con_outer_point2_rts", 21, 21, &umr_bitfield_default },
+	 { "pg_edge_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "pg_edge_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "pg_inner3_perp_fifo_empty", 26, 26, &umr_bitfield_default },
+	 { "pg_inner_perp_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "pg_patch_fifo_empty", 24, 24, &umr_bitfield_default },
+	 { "pg_patch_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe0_rtr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_inner_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe1_outer_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe2_inner_dr", 5, 5, &umr_bitfield_default },
+	 { "pipe2_inner_rtr", 13, 13, &umr_bitfield_default },
+	 { "pipe2_outer_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe2_outer_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe3_inner_dr", 7, 7, &umr_bitfield_default },
+	 { "pipe3_inner_rtr", 15, 15, &umr_bitfield_default },
+	 { "pipe3_outer_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe3_outer_rtr", 14, 14, &umr_bitfield_default },
+	 { "pipe4_inner_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe4_inner_rtr", 17, 17, &umr_bitfield_default },
+	 { "pipe4_outer_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe4_outer_rtr", 16, 16, &umr_bitfield_default },
+	 { "pipe5_inner_dr", 11, 11, &umr_bitfield_default },
+	 { "pipe5_inner_rtr", 19, 19, &umr_bitfield_default },
+	 { "pipe5_outer_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe5_outer_rtr", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG32[] = {
+	 { "event_flag_p5_q", 8, 8, &umr_bitfield_default },
+	 { "event_null_special_p0_q", 7, 7, &umr_bitfield_default },
+	 { "fifos_rtr", 27, 27, &umr_bitfield_default },
+	 { "first_point_of_edge_p5_q", 10, 10, &umr_bitfield_default },
+	 { "first_point_of_patch_p5_q", 9, 9, &umr_bitfield_default },
+	 { "first_ring_of_patch", 0, 0, &umr_bitfield_default },
+	 { "inner2_fifos_rtr", 24, 24, &umr_bitfield_default },
+	 { "inner_fifos_rtr", 25, 25, &umr_bitfield_default },
+	 { "last_edge_of_inner_ring", 4, 4, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring", 2, 2, &umr_bitfield_default },
+	 { "last_patch_of_tg_p0_q", 6, 6, &umr_bitfield_default },
+	 { "last_patch_of_tg_p5_q", 11, 11, &umr_bitfield_default },
+	 { "last_point_of_inner_edge", 5, 5, &umr_bitfield_default },
+	 { "last_point_of_outer_edge", 3, 3, &umr_bitfield_default },
+	 { "last_ring_of_patch", 1, 1, &umr_bitfield_default },
+	 { "outer_fifos_rtr", 26, 26, &umr_bitfield_default },
+	 { "pg_edge_fifo2_full", 17, 17, &umr_bitfield_default },
+	 { "pg_edge_fifo3_full", 16, 16, &umr_bitfield_default },
+	 { "pg_inner2_point_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "pg_inner3_point_fifo_full", 18, 18, &umr_bitfield_default },
+	 { "pg_inner_point_fifo_full", 22, 22, &umr_bitfield_default },
+	 { "pg_outer2_point_fifo_full", 21, 21, &umr_bitfield_default },
+	 { "pg_outer3_point_fifo_full", 19, 19, &umr_bitfield_default },
+	 { "pg_outer_point_fifo_full", 23, 23, &umr_bitfield_default },
+	 { "pipe5_inner2_rtr", 15, 15, &umr_bitfield_default },
+	 { "pipe5_inner3_rtr", 14, 14, &umr_bitfield_default },
+	 { "SPARE", 31, 31, &umr_bitfield_default },
+	 { "tess_topology_p5_q", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG33[] = {
+	 { "con_prim_fifo_empty", 18, 18, &umr_bitfield_default },
+	 { "con_prim_fifo_full", 16, 16, &umr_bitfield_default },
+	 { "con_ring1_busy", 31, 31, &umr_bitfield_default },
+	 { "con_ring2_busy", 30, 30, &umr_bitfield_default },
+	 { "con_ring3_busy", 29, 29, &umr_bitfield_default },
+	 { "con_vert_fifo_empty", 19, 19, &umr_bitfield_default },
+	 { "con_vert_fifo_full", 17, 17, &umr_bitfield_default },
+	 { "first_prim_of_patch_q", 15, 15, &umr_bitfield_default },
+	 { "last_patch_of_tg_p0_q", 20, 20, &umr_bitfield_default },
+	 { "pipe0_patch_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe2_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe2_rtr", 7, 7, &umr_bitfield_default },
+	 { "pipe3_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe3_rtr", 9, 9, &umr_bitfield_default },
+	 { "ring1_in_sync_q", 11, 11, &umr_bitfield_default },
+	 { "ring1_pipe1_dr", 6, 6, &umr_bitfield_default },
+	 { "ring1_valid_p2", 23, 23, &umr_bitfield_default },
+	 { "ring2_in_sync_q", 10, 10, &umr_bitfield_default },
+	 { "ring2_pipe1_dr", 5, 5, &umr_bitfield_default },
+	 { "ring2_valid_p2", 22, 22, &umr_bitfield_default },
+	 { "ring3_in_sync_q", 13, 13, &umr_bitfield_default },
+	 { "ring3_pipe1_dr", 1, 1, &umr_bitfield_default },
+	 { "ring3_valid_p2", 21, 21, &umr_bitfield_default },
+	 { "te11_out_vert_gs_en", 28, 28, &umr_bitfield_default },
+	 { "tess_topology_p0_q", 26, 27, &umr_bitfield_default },
+	 { "tess_type_p0_q", 24, 25, &umr_bitfield_default },
+	 { "tm_te11_event_rtr", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG34[] = {
+	 { "advance_inner_point_p1", 23, 23, &umr_bitfield_default },
+	 { "advance_outer_point_p1", 22, 22, &umr_bitfield_default },
+	 { "con_state_q", 0, 3, &umr_bitfield_default },
+	 { "first_ring_of_patch_p0_q", 16, 16, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring_p0_q", 18, 18, &umr_bitfield_default },
+	 { "last_point_of_inner_ring_p1", 20, 20, &umr_bitfield_default },
+	 { "last_point_of_outer_ring_p1", 19, 19, &umr_bitfield_default },
+	 { "last_ring_of_patch_p0_q", 17, 17, &umr_bitfield_default },
+	 { "next_ring_is_rect_p0_q", 24, 24, &umr_bitfield_default },
+	 { "outer_edge_tf_eq_one_p0_q", 21, 21, &umr_bitfield_default },
+	 { "outer_parity_p0_q", 14, 14, &umr_bitfield_default },
+	 { "parallel_parity_p0_q", 15, 15, &umr_bitfield_default },
+	 { "pipe0_edge_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe0_edge_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe0_patch_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 11, 11, &umr_bitfield_default },
+	 { "pipe1_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe1_edge_rtr", 30, 30, &umr_bitfield_default },
+	 { "pipe1_inner1_rtr", 27, 27, &umr_bitfield_default },
+	 { "pipe1_inner2_rtr", 28, 28, &umr_bitfield_default },
+	 { "pipe1_outer1_rtr", 25, 25, &umr_bitfield_default },
+	 { "pipe1_outer2_rtr", 26, 26, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 29, 29, &umr_bitfield_default },
+	 { "pipe1_rtr", 13, 13, &umr_bitfield_default },
+	 { "process_tri_1st_2nd_half_p0_q", 6, 6, &umr_bitfield_default },
+	 { "process_tri_center_poly_p0_q", 7, 7, &umr_bitfield_default },
+	 { "process_tri_middle_p0_q", 5, 5, &umr_bitfield_default },
+	 { "second_cycle_q", 4, 4, &umr_bitfield_default },
+	 { "use_stored_inner_q_ring1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG35[] = {
+	 { "event_flag_p1_q", 18, 18, &umr_bitfield_default },
+	 { "first_req_of_tg_p1_q", 28, 28, &umr_bitfield_default },
+	 { "last_req_of_tg_p2", 11, 11, &umr_bitfield_default },
+	 { "null_flag_p1_q", 19, 19, &umr_bitfield_default },
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe0_rtr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_rtr", 3, 3, &umr_bitfield_default },
+	 { "second_tf_ret_data_q", 27, 27, &umr_bitfield_default },
+	 { "spi_vgt_hs_done_cnt_q", 12, 17, &umr_bitfield_default },
+	 { "TC_VGT_rdret_data_in", 31, 31, &umr_bitfield_default },
+	 { "tf_data_fifo_busy_q", 6, 6, &umr_bitfield_default },
+	 { "tf_data_fifo_cnt_q", 20, 26, &umr_bitfield_default },
+	 { "tf_data_fifo_rtr_q", 7, 7, &umr_bitfield_default },
+	 { "tfreq_tg_fifo_empty", 4, 4, &umr_bitfield_default },
+	 { "tfreq_tg_fifo_full", 5, 5, &umr_bitfield_default },
+	 { "tf_skid_fifo_empty", 8, 8, &umr_bitfield_default },
+	 { "tf_skid_fifo_full", 9, 9, &umr_bitfield_default },
+	 { "VGT_TC_rdnfo_stall_out", 30, 30, &umr_bitfield_default },
+	 { "vgt_tc_rdreq_rtr_q", 10, 10, &umr_bitfield_default },
+	 { "VGT_TC_rdreq_send_out", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TBA_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TBA_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TMA_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TMA_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_M0[] = {
+	 { "M0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_EXEC_LO[] = {
+	 { "EXEC_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_EXEC_HI[] = {
+	 { "EXEC_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CNTL[] = {
+	 { "READ_TIMEOUT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SKEW_CNTL[] = {
+	 { "SKEW_COUNT", 6, 11, &umr_bitfield_default },
+	 { "SKEW_TOP_THRESHOLD", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS2[] = {
+	 { "CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPF_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CPG_BUSY", 30, 30, &umr_bitfield_default },
+	 { "ME0PIPE1_CF_RQ_PENDING", 4, 4, &umr_bitfield_default },
+	 { "ME0PIPE1_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "ME0PIPE1_PF_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME1PIPE0_RQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "ME1PIPE1_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME1PIPE2_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "ME1PIPE3_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "ME2PIPE0_RQ_PENDING", 10, 10, &umr_bitfield_default },
+	 { "ME2PIPE1_RQ_PENDING", 11, 11, &umr_bitfield_default },
+	 { "ME2PIPE2_RQ_PENDING", 12, 12, &umr_bitfield_default },
+	 { "ME2PIPE3_RQ_PENDING", 13, 13, &umr_bitfield_default },
+	 { "RLC_BUSY", 8, 8, &umr_bitfield_default },
+	 { "RLC_RQ_PENDING", 0, 0, &umr_bitfield_default },
+	 { "TC_BUSY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PWR_CNTL[] = {
+	 { "REQ_TYPE", 0, 3, &umr_bitfield_default },
+	 { "RSP_TYPE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS[] = {
+	 { "BCI_BUSY", 23, 23, &umr_bitfield_default },
+	 { "CB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_CLEAN", 13, 13, &umr_bitfield_default },
+	 { "CP_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CP_COHERENCY_BUSY", 28, 28, &umr_bitfield_default },
+	 { "DB_BUSY", 26, 26, &umr_bitfield_default },
+	 { "DB_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "GDS_BUSY", 15, 15, &umr_bitfield_default },
+	 { "GDS_DMA_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "GUI_ACTIVE", 31, 31, &umr_bitfield_default },
+	 { "IA_BUSY", 19, 19, &umr_bitfield_default },
+	 { "IA_BUSY_NO_DMA", 18, 18, &umr_bitfield_default },
+	 { "ME0PIPE0_CF_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME0PIPE0_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "ME0PIPE0_PF_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "PA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "SPI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "SRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "SX_BUSY", 20, 20, &umr_bitfield_default },
+	 { "TA_BUSY", 14, 14, &umr_bitfield_default },
+	 { "VGT_BUSY", 17, 17, &umr_bitfield_default },
+	 { "WD_BUSY", 21, 21, &umr_bitfield_default },
+	 { "WD_BUSY_NO_DMA", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE0[] = {
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE1[] = {
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SOFT_RESET[] = {
+	 { "SOFT_RESET_CPC", 18, 18, &umr_bitfield_default },
+	 { "SOFT_RESET_CPF", 17, 17, &umr_bitfield_default },
+	 { "SOFT_RESET_CPG", 19, 19, &umr_bitfield_default },
+	 { "SOFT_RESET_CP", 0, 0, &umr_bitfield_default },
+	 { "SOFT_RESET_GFX", 16, 16, &umr_bitfield_default },
+	 { "SOFT_RESET_RLC", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_CNTL[] = {
+	 { "GRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_GFX_INDEX[] = {
+	 { "INSTANCE_BROADCAST_WRITES", 30, 30, &umr_bitfield_default },
+	 { "INSTANCE_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SE_BROADCAST_WRITES", 31, 31, &umr_bitfield_default },
+	 { "SE_INDEX", 16, 23, &umr_bitfield_default },
+	 { "SH_BROADCAST_WRITES", 29, 29, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_GFX_CLKEN_CNTL[] = {
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_WAIT_IDLE_CLOCKS[] = {
+	 { "WAIT_IDLE_CLOCKS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG[] = {
+	 { "DISABLE_READ_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "GFX_CLOCK_DOMAIN_OVERRIDE", 12, 12, &umr_bitfield_default },
+	 { "HYSTERESIS_GUI_ACTIVE", 8, 11, &umr_bitfield_default },
+	 { "IGNORE_FAO", 5, 5, &umr_bitfield_default },
+	 { "IGNORE_RDY", 1, 1, &umr_bitfield_default },
+	 { "SNAPSHOT_FREE_CNTRS", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_SNAPSHOT[] = {
+	 { "CPF_RDY", 0, 0, &umr_bitfield_default },
+	 { "CPG_RDY", 1, 1, &umr_bitfield_default },
+	 { "GDS_RDY", 9, 9, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY0", 6, 6, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY1", 14, 14, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY0", 7, 7, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY1", 15, 15, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY0", 8, 8, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY1", 16, 16, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY0", 9, 9, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY1", 17, 17, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY0", 10, 10, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY1", 18, 18, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY0", 11, 11, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY1", 19, 19, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY0", 12, 12, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY1", 20, 20, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY0", 13, 13, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY1", 21, 21, &umr_bitfield_default },
+	 { "SRBM_RDY", 1, 1, &umr_bitfield_default },
+	 { "WD_ME0PIPE0_RDY", 3, 3, &umr_bitfield_default },
+	 { "WD_ME0PIPE1_RDY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_READ_ERROR[] = {
+	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
+	 { "READ_MEID", 22, 23, &umr_bitfield_default },
+	 { "READ_PIPEID", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_INT_CNTL[] = {
+	 { "GUI_IDLE_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "RDERR_INT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_SELECT[] = {
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_SELECT[] = {
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_SELECT[] = {
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_SELECT[] = {
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEBUG_INDEX[] = {
+	 { "DEBUG_INDEX", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEBUG_DATA[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_NOWHERE[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_INTERRUPT_WORD_AUTO[] = {
+	 { "CMD_TIMESTAMP", 4, 4, &umr_bitfield_default },
+	 { "ENCODING", 26, 27, &umr_bitfield_default },
+	 { "HOST_CMD_OVERFLOW", 5, 5, &umr_bitfield_default },
+	 { "HOST_REG_OVERFLOW", 6, 6, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "REG_TIMESTAMP", 3, 3, &umr_bitfield_default },
+	 { "SE_ID", 25, 25, &umr_bitfield_default },
+	 { "THREAD_TRACE_BUF_FULL", 2, 2, &umr_bitfield_default },
+	 { "THREAD_TRACE", 0, 0, &umr_bitfield_default },
+	 { "WLT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_ADDR_LO[] = {
+	 { "ADDR_LO", 2, 31, &umr_bitfield_default },
+	 { "ADDR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_LO[] = {
+	 { "DATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_HI[] = {
+	 { "DATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_LAST_FENCE_LO[] = {
+	 { "LAST_FENCE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_LAST_FENCE_HI[] = {
+	 { "LAST_FENCE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_ADDR_LO[] = {
+	 { "STREAM_OUT_ADDR_LO", 2, 31, &umr_bitfield_default },
+	 { "STREAM_OUT_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_ADDR_HI[] = {
+	 { "STREAM_OUT_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_ADDR_LO[] = {
+	 { "PIPE_STATS_ADDR_LO", 2, 31, &umr_bitfield_default },
+	 { "PIPE_STATS_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_ADDR_HI[] = {
+	 { "PIPE_STATS_ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_LO[] = {
+	 { "IAVERT_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_HI[] = {
+	 { "IAVERT_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_LO[] = {
+	 { "IAPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_HI[] = {
+	 { "IAPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_LO[] = {
+	 { "GSPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_HI[] = {
+	 { "GSPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_LO[] = {
+	 { "VSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_HI[] = {
+	 { "VSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_LO[] = {
+	 { "GSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_HI[] = {
+	 { "GSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_LO[] = {
+	 { "HSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_HI[] = {
+	 { "HSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_LO[] = {
+	 { "DSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_HI[] = {
+	 { "DSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CINVOC_COUNT_LO[] = {
+	 { "CINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CINVOC_COUNT_HI[] = {
+	 { "CINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CPRIM_COUNT_LO[] = {
+	 { "CPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CPRIM_COUNT_HI[] = {
+	 { "CPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_LO[] = {
+	 { "PSINVOC_COUNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_HI[] = {
+	 { "PSINVOC_COUNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_LO[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_HI[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_LO[] = {
+	 { "CSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_HI[] = {
+	 { "CSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STRMOUT_CNTL[] = {
+	 { "OFFSET_UPDATE_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_UMSK[] = {
+	 { "OBSOLETE_SWAP", 16, 17, &umr_bitfield_default },
+	 { "OBSOLETE_UMSK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_ADDR[] = {
+	 { "OBSOLETE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_ADDR_LO[] = {
+	 { "MEM_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_ADDR_HI[] = {
+	 { "COMMAND", 29, 31, &umr_bitfield_default },
+	 { "CS_PS_SEL", 16, 17, &umr_bitfield_default },
+	 { "MEM_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_LAST_CS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_LAST_PS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WADDR_LO[] = {
+	 { "ME_MC_WADDR_LO", 2, 31, &umr_bitfield_default },
+	 { "ME_MC_WADDR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WADDR_HI[] = {
+	 { "ME_MC_WADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WDATA_LO[] = {
+	 { "ME_MC_WDATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WDATA_HI[] = {
+	 { "ME_MC_WDATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_RADDR_LO[] = {
+	 { "ME_MC_RADDR_LO", 2, 31, &umr_bitfield_default },
+	 { "ME_MC_RADDR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_RADDR_HI[] = {
+	 { "ME_MC_RADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SEM_WAIT_TIMER[] = {
+	 { "SEM_WAIT_TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SIG_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SIG_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 7, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_REG_MEM_TIMEOUT[] = {
+	 { "WAIT_REG_MEM_TIMEOUT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 7, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_START_DELAY[] = {
+	 { "START_DELAY_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_CNTL[] = {
+	 { "CB0_DEST_BASE_ENA", 6, 6, &umr_bitfield_default },
+	 { "CB1_DEST_BASE_ENA", 7, 7, &umr_bitfield_default },
+	 { "CB2_DEST_BASE_ENA", 8, 8, &umr_bitfield_default },
+	 { "CB3_DEST_BASE_ENA", 9, 9, &umr_bitfield_default },
+	 { "CB4_DEST_BASE_ENA", 10, 10, &umr_bitfield_default },
+	 { "CB5_DEST_BASE_ENA", 11, 11, &umr_bitfield_default },
+	 { "CB6_DEST_BASE_ENA", 12, 12, &umr_bitfield_default },
+	 { "CB7_DEST_BASE_ENA", 13, 13, &umr_bitfield_default },
+	 { "CB_ACTION_ENA", 25, 25, &umr_bitfield_default },
+	 { "DB_ACTION_ENA", 26, 26, &umr_bitfield_default },
+	 { "DB_DEST_BASE_ENA", 14, 14, &umr_bitfield_default },
+	 { "DEST_BASE_0_ENA", 0, 0, &umr_bitfield_default },
+	 { "DEST_BASE_1_ENA", 1, 1, &umr_bitfield_default },
+	 { "DEST_BASE_2_ENA", 19, 19, &umr_bitfield_default },
+	 { "DEST_BASE_3_ENA", 21, 21, &umr_bitfield_default },
+	 { "SH_ICACHE_ACTION_ENA", 29, 29, &umr_bitfield_default },
+	 { "SH_KCACHE_ACTION_ENA", 27, 27, &umr_bitfield_default },
+	 { "SH_KCACHE_VOL_ACTION_ENA", 28, 28, &umr_bitfield_default },
+	 { "TC_ACTION_ENA", 23, 23, &umr_bitfield_default },
+	 { "TCL1_ACTION_ENA", 22, 22, &umr_bitfield_default },
+	 { "TCL1_VOL_ACTION_ENA", 15, 15, &umr_bitfield_default },
+	 { "TC_VOL_ACTION_ENA", 16, 16, &umr_bitfield_default },
+	 { "TC_WB_ACTION_ENA", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_SIZE[] = {
+	 { "COHER_SIZE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_BASE[] = {
+	 { "COHER_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_STATUS[] = {
+	 { "MATCHING_GFX_CNTX", 0, 7, &umr_bitfield_default },
+	 { "MEID", 24, 25, &umr_bitfield_default },
+	 { "PHASE1_STATUS", 30, 30, &umr_bitfield_default },
+	 { "STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_CNTL[] = {
+	 { "BUFFER_DEPTH", 16, 19, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 4, 5, &umr_bitfield_default },
+	 { "PIO_COUNT", 30, 31, &umr_bitfield_default },
+	 { "PIO_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
+	 { "PIO_FIFO_FULL", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_READ_TAGS[] = {
+	 { "DMA_READ_TAG", 0, 25, &umr_bitfield_default },
+	 { "DMA_READ_TAG_VALID", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_IB_CONTROL[] = {
+	 { "IB_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_LOAD_CONTROL[] = {
+	 { "CNTX_REG_EN", 1, 1, &umr_bitfield_default },
+	 { "CONFIG_REG_EN", 0, 0, &umr_bitfield_default },
+	 { "SH_CS_REG_EN", 24, 24, &umr_bitfield_default },
+	 { "SH_GFX_REG_EN", 16, 16, &umr_bitfield_default },
+	 { "UCONFIG_REG_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_OFFSET[] = {
+	 { "RB_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_OFFSET[] = {
+	 { "IB1_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_OFFSET[] = {
+	 { "IB2_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_PREAMBLE_BEGIN[] = {
+	 { "IB1_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_PREAMBLE_END[] = {
+	 { "IB1_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_PREAMBLE_BEGIN[] = {
+	 { "IB2_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_PREAMBLE_END[] = {
+	 { "IB2_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT3[] = {
+	 { "CE_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "CE_TO_INC_FIFO_NOT_RDY_TO_RCV", 6, 6, &umr_bitfield_default },
+	 { "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV", 8, 8, &umr_bitfield_default },
+	 { "CE_TO_RAM_DUMP_NOT_RDY", 4, 4, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_NOT_RDY", 3, 3, &umr_bitfield_default },
+	 { "CE_TO_RAM_WRITE_NOT_RDY", 5, 5, &umr_bitfield_default },
+	 { "CE_TO_WR_FIFO_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default },
+	 { "CE_WAITING_ON_BUFFER_DATA", 10, 10, &umr_bitfield_default },
+	 { "CE_WAITING_ON_CE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER", 2, 2, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER", 12, 12, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER_UNDERFLOW", 13, 13, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 14, 14, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT1[] = {
+	 { "ME_HAS_ACTIVE_CE_BUFFER_FLAG", 10, 10, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_DE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "ME_STALLED_ON_ATOMIC_RTN_DATA", 13, 13, &umr_bitfield_default },
+	 { "ME_STALLED_ON_TC_WR_CONFIRM", 12, 12, &umr_bitfield_default },
+	 { "ME_WAITING_ON_MC_READ_DATA", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_REG_READ_DATA", 15, 15, &umr_bitfield_default },
+	 { "MIU_WAITING_ON_RDREQ_FREE", 16, 16, &umr_bitfield_default },
+	 { "MIU_WAITING_ON_WRREQ_FREE", 17, 17, &umr_bitfield_default },
+	 { "RBIU_TO_DMA_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "RBIU_TO_MEMWR_NOT_RDY_TO_RCV", 4, 4, &umr_bitfield_default },
+	 { "RBIU_TO_SEM_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "RCIU_HALTED_BY_REG_VIOLATION", 28, 28, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_APPEND_READ", 28, 28, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_DMA_READ", 27, 27, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_ME_READ", 26, 26, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GDS_FREE", 23, 23, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GRBM_FREE", 24, 24, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_VGT_FREE", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT2[] = {
+	 { "APPEND_ACTIVE_PARTITION", 28, 28, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_CS_DONE", 25, 25, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_PS_DONE", 26, 26, &umr_bitfield_default },
+	 { "APPEND_WAITING_TO_SEND_MEMWRITE", 29, 29, &umr_bitfield_default },
+	 { "APPEND_WAIT_ON_WR_CONFIRM", 27, 27, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_SC_EOP_DONE", 21, 21, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_WR_CONFIRM", 22, 22, &umr_bitfield_default },
+	 { "GFX_CNTX_NOT_AVAIL_TO_ME", 11, 11, &umr_bitfield_default },
+	 { "MEQ_TO_ME_NOT_RDY_TO_RCV", 16, 16, &umr_bitfield_default },
+	 { "ME_RCIU_NOT_RDY_TO_RCV", 12, 12, &umr_bitfield_default },
+	 { "ME_TO_CONST_NOT_RDY_TO_RCV", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_PFP", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_STQ", 18, 18, &umr_bitfield_default },
+	 { "ME_WAITING_ON_PARTIAL_FLUSH", 15, 15, &umr_bitfield_default },
+	 { "ME_WAIT_ON_AVAIL_BUFFER", 10, 10, &umr_bitfield_default },
+	 { "ME_WAIT_ON_CE_COUNTER", 9, 9, &umr_bitfield_default },
+	 { "PFP_MIU_READ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "PFP_RCIU_READ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_ATOMIC_RTN_DATA", 20, 20, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_TC_WR_CONFIRM", 19, 19, &umr_bitfield_default },
+	 { "PFP_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "PFP_TO_MEQ_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default },
+	 { "PFP_TO_RCIU_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "PFP_TO_VGT_WRITES_PENDING", 4, 4, &umr_bitfield_default },
+	 { "PFP_WAITING_ON_BUFFER_DATA", 8, 8, &umr_bitfield_default },
+	 { "PIPE_STATS_WR_DATA_PENDING", 24, 24, &umr_bitfield_default },
+	 { "STQ_TO_ME_NOT_RDY_TO_RCV", 17, 17, &umr_bitfield_default },
+	 { "STRMO_WR_OF_PRIM_DATA_PENDING", 23, 23, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_ALL_CLEAN", 31, 31, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_IDLE_CNTXS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_BUSY_STAT[] = {
+	 { "CE_PARSING_PACKETS", 22, 22, &umr_bitfield_default },
+	 { "COHER_CNT_NEQ_ZERO", 6, 6, &umr_bitfield_default },
+	 { "EOP_DONE_BUSY", 18, 18, &umr_bitfield_default },
+	 { "GFX_CONTEXT_BUSY", 15, 15, &umr_bitfield_default },
+	 { "ME_PARSER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "ME_PARSING_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "PFP_PARSING_PACKETS", 7, 7, &umr_bitfield_default },
+	 { "PIPE_STATS_BUSY", 20, 20, &umr_bitfield_default },
+	 { "RCIU_CE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "RCIU_ME_BUSY", 10, 10, &umr_bitfield_default },
+	 { "RCIU_PFP_BUSY", 9, 9, &umr_bitfield_default },
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "SEM_CMDFIFO_NOT_EMPTY", 12, 12, &umr_bitfield_default },
+	 { "SEM_FAILED_AND_HOLDING", 13, 13, &umr_bitfield_default },
+	 { "SEM_POLLING_FOR_PASS", 14, 14, &umr_bitfield_default },
+	 { "STRM_OUT_BUSY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STAT[] = {
+	 { "CE_BUSY", 26, 26, &umr_bitfield_default },
+	 { "CP_BUSY", 31, 31, &umr_bitfield_default },
+	 { "CPC_CPG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "DC_BUSY", 13, 13, &umr_bitfield_default },
+	 { "DMA_BUSY", 22, 22, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 20, 20, &umr_bitfield_default },
+	 { "ME_BUSY", 17, 17, &umr_bitfield_default },
+	 { "MEQ_BUSY", 16, 16, &umr_bitfield_default },
+	 { "MIU_RDREQ_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MIU_WRREQ_BUSY", 8, 8, &umr_bitfield_default },
+	 { "PFP_BUSY", 15, 15, &umr_bitfield_default },
+	 { "QUERY_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RCIU_BUSY", 23, 23, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 29, 29, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 28, 28, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "ROQ_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 24, 24, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SURFACE_SYNC_BUSY", 21, 21, &umr_bitfield_default },
+	 { "TCIU_BUSY", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_HEADER_DUMP[] = {
+	 { "ME_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_HEADER_DUMP[] = {
+	 { "PFP_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT_GDS", 8, 13, &umr_bitfield_default },
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+	 { "FREE_COUNT_PFP", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_HEADER_DUMP[] = {
+	 { "CE_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MC_PACK_DELAY_CNT[] = {
+	 { "PACK_DELAY_CNT", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CSF_STAT[] = {
+	 { "BUFFER_REQUEST_COUNT", 8, 13, &umr_bitfield_default },
+	 { "BUFFER_SLOTS_ALLOCATED", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CSF_CNTL[] = {
+	 { "FETCH_BUFFER_DEPTH", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_CNTL[] = {
+	 { "CE_HALT", 24, 24, &umr_bitfield_default },
+	 { "CE_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "CE_STEP", 25, 25, &umr_bitfield_default },
+	 { "ME_HALT", 28, 28, &umr_bitfield_default },
+	 { "ME_INVALIDATE_ICACHE", 8, 8, &umr_bitfield_default },
+	 { "ME_STEP", 29, 29, &umr_bitfield_default },
+	 { "PFP_HALT", 26, 26, &umr_bitfield_default },
+	 { "PFP_INVALIDATE_ICACHE", 6, 6, &umr_bitfield_default },
+	 { "PFP_STEP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CNTX_STAT[] = {
+	 { "ACTIVE_GFX_CONTEXTS", 20, 27, &umr_bitfield_default },
+	 { "ACTIVE_HP3D_CONTEXTS", 0, 7, &umr_bitfield_default },
+	 { "CURRENT_GFX_CONTEXT", 28, 30, &umr_bitfield_default },
+	 { "CURRENT_HP3D_CONTEXT", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_PREEMPTION[] = {
+	 { "ME_CNTXSW_PREEMPTION", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_DELAY[] = {
+	 { "PRE_WRITE_LIMIT", 28, 31, &umr_bitfield_default },
+	 { "PRE_WRITE_TIMER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_CNTL[] = {
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+	 { "POLL_FREQUENCY", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BASE_LO[] = {
+	 { "INIT_BASE_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BASE_HI[] = {
+	 { "INIT_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BUFSZ[] = {
+	 { "INIT_BUFSZ", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BASE_LO[] = {
+	 { "ST_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BASE_HI[] = {
+	 { "ST_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BUFSZ[] = {
+	 { "ST_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ1_THRESHOLDS[] = {
+	 { "R0_IB1_START", 16, 23, &umr_bitfield_default },
+	 { "R1_IB1_START", 24, 31, &umr_bitfield_default },
+	 { "RB1_START", 0, 7, &umr_bitfield_default },
+	 { "RB2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ2_THRESHOLDS[] = {
+	 { "R0_IB2_START", 8, 15, &umr_bitfield_default },
+	 { "R1_IB2_START", 16, 23, &umr_bitfield_default },
+	 { "R2_IB1_START", 0, 7, &umr_bitfield_default },
+	 { "R2_IB2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_THRESHOLDS[] = {
+	 { "STQ0_START", 0, 7, &umr_bitfield_default },
+	 { "STQ1_START", 8, 15, &umr_bitfield_default },
+	 { "STQ2_START", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_QUEUE_THRESHOLDS[] = {
+	 { "ROQ_IB1_START", 0, 5, &umr_bitfield_default },
+	 { "ROQ_IB2_START", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_THRESHOLDS[] = {
+	 { "MEQ1_START", 0, 7, &umr_bitfield_default },
+	 { "MEQ2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_AVAIL[] = {
+	 { "ROQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+	 { "ROQ_CNT_RING", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_AVAIL[] = {
+	 { "STQ_CNT", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ2_AVAIL[] = {
+	 { "ROQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_AVAIL[] = {
+	 { "MEQ_CNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CMD_INDEX[] = {
+	 { "CMD_INDEX", 0, 10, &umr_bitfield_default },
+	 { "CMD_ME_SEL", 12, 13, &umr_bitfield_default },
+	 { "CMD_QUEUE_SEL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CMD_DATA[] = {
+	 { "CMD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_RB_STAT[] = {
+	 { "ROQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_IB1_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_IB2_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_STAT[] = {
+	 { "STQ_RPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_STAT[] = {
+	 { "MEQ_RPTR", 0, 9, &umr_bitfield_default },
+	 { "MEQ_WPTR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CEQ1_AVAIL[] = {
+	 { "CEQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+	 { "CEQ_CNT_RING", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CEQ2_AVAIL[] = {
+	 { "CEQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_RB_STAT[] = {
+	 { "CEQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_IB1_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_IB2_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STAT_DEBUG[] = {
+	 { "CNTX_BUSY_INT_ASSERTED", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ASSERTED", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ASSERTED", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PERFMON_CNTL[] = {
+	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
+	 { "SPM_PERFMON_STATE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VTX_VECT_EJECT_REG[] = {
+	 { "PRIM_COUNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_DATA_FIFO_DEPTH[] = {
+	 { "DMA_DATA_FIFO_DEPTH", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_REQ_FIFO_DEPTH[] = {
+	 { "DMA_REQ_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DRAW_INIT_FIFO_DEPTH[] = {
+	 { "DRAW_INIT_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_LAST_COPY_STATE[] = {
+	 { "DST_STATE_ID", 16, 18, &umr_bitfield_default },
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_CACHE_INVALIDATION[] = {
+	 { "AUTO_INVLD_EN", 6, 7, &umr_bitfield_default },
+	 { "CACHE_INVALIDATION", 0, 1, &umr_bitfield_default },
+	 { "DIS_RANGE_FULL_INVLD", 11, 11, &umr_bitfield_default },
+	 { "ES_LIMIT", 16, 20, &umr_bitfield_default },
+	 { "GS_LATE_ALLOC_EN", 12, 12, &umr_bitfield_default },
+	 { "STREAMOUT_FULL_FLUSH", 13, 13, &umr_bitfield_default },
+	 { "USE_GS_DONE", 9, 9, &umr_bitfield_default },
+	 { "VS_NO_EXTRA_BUFFER", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ESGS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_FIFO_DEPTHS[] = {
+	 { "CLIPP_FIFO_DEPTH", 8, 21, &umr_bitfield_default },
+	 { "RESERVED_0", 7, 7, &umr_bitfield_default },
+	 { "RESERVED_1", 22, 31, &umr_bitfield_default },
+	 { "VS_DEALLOC_TBL_DEPTH", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERTEX_REUSE[] = {
+	 { "VERT_REUSE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MC_LAT_CNTL[] = {
+	 { "MC_TIME_STAMP_RES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_CNTL_STATUS[] = {
+	 { "IA_ADC_BUSY", 4, 4, &umr_bitfield_default },
+	 { "IA_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IA_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "IA_DMA_REQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "IA_GRP_BUSY", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DEBUG_CNTL[] = {
+	 { "VGT_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "VGT_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_DEBUG_CNTL[] = {
+	 { "IA_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "IA_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_CNTL_STATUS[] = {
+	 { "VGT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VGT_GS_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGT_HS_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VGT_OUT_BUSY", 2, 2, &umr_bitfield_default },
+	 { "VGT_OUT_INDX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "VGT_PI_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGT_PT_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VGT_TE11_BUSY", 9, 9, &umr_bitfield_default },
+	 { "VGT_TE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGT_VR_BUSY", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER_SEID_MASK[] = {
+	 { "PERF_SEID_IGNORE_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_NUM_INDICES[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_VGT_CLK_CTRL[] = {
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "GS_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_VMID_OVERRIDE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VMID", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_IA_CLK_CTRL[] = {
+	 { "CORE_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_RING_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_SYS_CONFIG[] = {
+	 { "ADC_EVENT_FILTER_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "DUAL_CORE_EN", 0, 0, &umr_bitfield_default },
+	 { "MAX_LS_HS_THDGRP", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HS_OFFCHIP_PARAM[] = {
+	 { "OFFCHIP_BUFFERING", 0, 6, &umr_bitfield_default },
+	 { "OFFCHIP_GRANULARITY", 9, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_MEMORY_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_SHADER_ARRAY_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SHADER_ARRAY_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_DEBUG_CNTL[] = {
+	 { "SU_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_CNTL_STATUS[] = {
+	 { "CL_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_ENHANCE[] = {
+	 { "CLIPPED_PRIM_SEQ_STALL", 3, 3, &umr_bitfield_default },
+	 { "CLIP_VTX_REORDER_ENA", 0, 0, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE2", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE3", 28, 28, &umr_bitfield_default },
+	 { "NUM_CLIP_SEQ", 1, 2, &umr_bitfield_default },
+	 { "VE_NAN_PROC_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "XTRA_DEBUG_REG_SEL", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_PA_CLK_CTRL[] = {
+	 { "CL_CLK_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REG_CLK_OVERRIDE", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SU_CLK_OVERRIDE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_CNTL_STATUS[] = {
+	 { "SU_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FIFO_DEPTH_CNTL[] = {
+	 { "DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_VALUE[] = {
+	 { "LINE_STIPPLE_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_STIPPLE_STATE[] = {
+	 { "CURRENT_COUNT", 8, 15, &umr_bitfield_default },
+	 { "CURRENT_PTR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FORCE_EOV_MAX_CNTS[] = {
+	 { "FORCE_EOV_MAX_CLK_CNT", 0, 15, &umr_bitfield_default },
+	 { "FORCE_EOV_MAX_REZ_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SC_CLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FIFO_SIZE[] = {
+	 { "SC_BACKEND_PRIM_FIFO_SIZE", 6, 14, &umr_bitfield_default },
+	 { "SC_EARLYZ_TILE_FIFO_SIZE", 23, 31, &umr_bitfield_default },
+	 { "SC_FRONTEND_PRIM_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_HIZ_TILE_FIFO_SIZE", 15, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_IF_FIFO_SIZE[] = {
+	 { "SC_BCI_IF_FIFO_SIZE", 18, 23, &umr_bitfield_default },
+	 { "SC_DB_QUAD_IF_FIFO_SIZE", 6, 11, &umr_bitfield_default },
+	 { "SC_DB_TILE_IF_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_SPI_IF_FIFO_SIZE", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DEBUG_CNTL[] = {
+	 { "SC_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_ENHANCE[] = {
+	 { "DISABLE_AA_MASK_FULL_FIX", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_DUALGRAD_PERF_OPTIMIZATION", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_PA_SC_GUIDANCE", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_PW_BUBBLE_COLLAPSE", 6, 7, &umr_bitfield_default },
+	 { "DISABLE_SC_DB_TILE_FIX", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_SCISSOR_FIX", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_PRIM", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_SUPERTILE", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_TILE", 12, 12, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOCATIONS", 3, 3, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID", 4, 4, &umr_bitfield_default },
+	 { "ENABLE_MULTICYCLE_BUBBLE_FREEZE", 15, 15, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID", 24, 24, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_POLY_MODE", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_PA_SC_OUT_OF_ORDER", 0, 0, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PACKER", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CONFIG[] = {
+	 { "DEBUG_EN", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_IB_DEP_CHECK", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_SCA_BYPASS", 9, 9, &umr_bitfield_default },
+	 { "DUA_FLAT_LDS_PINGPONG_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DUA_FLAT_LOCK_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "DUA_LDS_BYPASS_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "EARLY_TA_DONE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "ENABLE_SOFT_CLAUSE", 11, 11, &umr_bitfield_default },
+	 { "UNUSED", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_CONFIG[] = {
+	 { "DATA_CACHE_SIZE", 2, 3, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_MISS", 7, 7, &umr_bitfield_default },
+	 { "FORCE_IN_ORDER", 8, 8, &umr_bitfield_default },
+	 { "HIT_FIFO_DEPTH", 6, 6, &umr_bitfield_default },
+	 { "IDENTITY_HASH_BANK", 9, 9, &umr_bitfield_default },
+	 { "IDENTITY_HASH_SET", 10, 10, &umr_bitfield_default },
+	 { "INST_CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "MISS_FIFO_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "PER_VMID_INV_DISABLE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_CACHES[] = {
+	 { "DATA_INVALIDATE", 1, 1, &umr_bitfield_default },
+	 { "INST_INVALIDATE", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_VOLATILE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_RANDOM_WAVE_PRI[] = {
+	 { "RET", 0, 6, &umr_bitfield_default },
+	 { "RNG", 10, 20, &umr_bitfield_default },
+	 { "RUI", 7, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_REG_CREDITS[] = {
+	 { "CMD_CREDITS", 8, 11, &umr_bitfield_default },
+	 { "CMD_OVERFLOW", 31, 31, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 30, 30, &umr_bitfield_default },
+	 { "REG_BUSY", 28, 28, &umr_bitfield_default },
+	 { "SRBM_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "SRBM_OVERFLOW", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FIFO_SIZES[] = {
+	 { "EXPORT_BUF_SIZE", 16, 17, &umr_bitfield_default },
+	 { "INTERRUPT_FIFO_SIZE", 0, 3, &umr_bitfield_default },
+	 { "TTRACE_FIFO_SIZE", 8, 11, &umr_bitfield_default },
+	 { "VMEM_DATA_FIFO_SIZE", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL[] = {
+	 { "CNTR_RATE", 8, 12, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_FLUSH", 13, 13, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUSER_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "INTERRUPT_MSG_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH0", 4, 15, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH1", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_SELECT[] = {
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_ALU_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TEX_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SQ_CLK_CTRL[] = {
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SQG_CLK_CTRL[] = {
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IND_INDEX[] = {
+	 { "AUTO_INCR", 12, 12, &umr_bitfield_default },
+	 { "FORCE_READ", 13, 13, &umr_bitfield_default },
+	 { "INDEX", 16, 31, &umr_bitfield_default },
+	 { "READ_TIMEOUT", 14, 14, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "THREAD_ID", 6, 11, &umr_bitfield_default },
+	 { "UNINDEXED", 15, 15, &umr_bitfield_default },
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TIME_HI[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TIME_LO[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DS_0[] = {
+	 { "ENCODING", 26, 31, &umr_bitfield_default },
+	 { "GDS", 17, 17, &umr_bitfield_default },
+	 { "OFFSET0", 0, 7, &umr_bitfield_default },
+	 { "OFFSET1", 8, 15, &umr_bitfield_default },
+	 { "OP", 18, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_SIZE[] = {
+	 { "SIZE", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_MASK[] = {
+	 { "CU_SEL", 0, 4, &umr_bitfield_default },
+	 { "RANDOM_SEED", 16, 31, &umr_bitfield_default },
+	 { "REG_STALL_EN", 7, 7, &umr_bitfield_default },
+	 { "SH_SEL", 5, 5, &umr_bitfield_default },
+	 { "SPI_STALL_EN", 14, 14, &umr_bitfield_default },
+	 { "SQ_STALL_EN", 15, 15, &umr_bitfield_default },
+	 { "VM_ID_MASK", 12, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK[] = {
+	 { "REG_DROP_ON_STALL", 24, 24, &umr_bitfield_default },
+	 { "REG_MASK", 16, 23, &umr_bitfield_default },
+	 { "TOKEN_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_PERF_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WPTR[] = {
+	 { "READ_OFFSET", 30, 31, &umr_bitfield_default },
+	 { "WPTR", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_STATUS[] = {
+	 { "BUSY", 30, 30, &umr_bitfield_default },
+	 { "FINISH_DONE", 16, 18, &umr_bitfield_default },
+	 { "FINISH_PENDING", 0, 2, &umr_bitfield_default },
+	 { "FULL", 31, 31, &umr_bitfield_default },
+	 { "NEW_BUF", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_MODE[] = {
+	 { "AUTOFLUSH_EN", 25, 25, &umr_bitfield_default },
+	 { "CAPTURE_MODE", 23, 24, &umr_bitfield_default },
+	 { "INTERRUPT_EN", 30, 30, &umr_bitfield_default },
+	 { "ISSUE_MASK", 27, 28, &umr_bitfield_default },
+	 { "MASK_CS", 18, 20, &umr_bitfield_default },
+	 { "MASK_ES", 9, 11, &umr_bitfield_default },
+	 { "MASK_GS", 6, 8, &umr_bitfield_default },
+	 { "MASK_HS", 12, 14, &umr_bitfield_default },
+	 { "MASK_LS", 15, 17, &umr_bitfield_default },
+	 { "MASK_PS", 0, 2, &umr_bitfield_default },
+	 { "MASK_VS", 3, 5, &umr_bitfield_default },
+	 { "MODE", 21, 22, &umr_bitfield_default },
+	 { "PRIV", 26, 26, &umr_bitfield_default },
+	 { "TEST_MODE", 29, 29, &umr_bitfield_default },
+	 { "WRAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_CTRL[] = {
+	 { "RESET_BUFFER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_CNTR[] = {
+	 { "CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_HIWATER[] = {
+	 { "HIWATER", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_POWER_THROTTLE[] = {
+	 { "MAX_POWER", 16, 29, &umr_bitfield_default },
+	 { "MIN_POWER", 0, 13, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_POWER_THROTTLE2[] = {
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_CTR_CTRL[] = {
+	 { "CLEAR", 2, 2, &umr_bitfield_default },
+	 { "LOAD", 1, 1, &umr_bitfield_default },
+	 { "START", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_ALU_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_TEX_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_ALU_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_TEX_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_SECDED_CNT[] = {
+	 { "DATA_DED", 24, 31, &umr_bitfield_default },
+	 { "DATA_SEC", 16, 23, &umr_bitfield_default },
+	 { "INST_DED", 8, 15, &umr_bitfield_default },
+	 { "INST_SEC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_SEC_CNT[] = {
+	 { "LDS_SEC", 0, 5, &umr_bitfield_default },
+	 { "SGPR_SEC", 8, 12, &umr_bitfield_default },
+	 { "VGPR_SEC", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DED_CNT[] = {
+	 { "LDS_DED", 0, 5, &umr_bitfield_default },
+	 { "SGPR_DED", 8, 12, &umr_bitfield_default },
+	 { "VGPR_DED", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DED_INFO[] = {
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "SOURCE", 6, 8, &umr_bitfield_default },
+	 { "VM_ID", 9, 12, &umr_bitfield_default },
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_CMN[] = {
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[] = {
+	 { "PC_HI", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 15, &umr_bitfield_default },
+	 { "CACHE_SWIZZLE", 30, 30, &umr_bitfield_default },
+	 { "STRIDE", 16, 29, &umr_bitfield_default },
+	 { "SWIZZLE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD2[] = {
+	 { "NUM_RECORDS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD3[] = {
+	 { "ADD_TID_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "ATC", 24, 24, &umr_bitfield_default },
+	 { "DATA_FORMAT", 15, 18, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 19, 20, &umr_bitfield_default },
+	 { "HASH_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "HEAP", 26, 26, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 21, 22, &umr_bitfield_default },
+	 { "MTYPE", 27, 29, &umr_bitfield_default },
+	 { "NUM_FORMAT", 12, 14, &umr_bitfield_default },
+	 { "TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 7, &umr_bitfield_default },
+	 { "DATA_FORMAT", 20, 25, &umr_bitfield_default },
+	 { "MIN_LOD", 8, 19, &umr_bitfield_default },
+	 { "MTYPE", 30, 31, &umr_bitfield_default },
+	 { "NUM_FORMAT", 26, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD2[] = {
+	 { "HEIGHT", 14, 27, &umr_bitfield_default },
+	 { "INTERLACED", 31, 31, &umr_bitfield_default },
+	 { "PERF_MOD", 28, 30, &umr_bitfield_default },
+	 { "WIDTH", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD3[] = {
+	 { "ATC", 27, 27, &umr_bitfield_default },
+	 { "BASE_LEVEL", 12, 15, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "LAST_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "MTYPE", 26, 26, &umr_bitfield_default },
+	 { "POW2_PAD", 25, 25, &umr_bitfield_default },
+	 { "TILING_INDEX", 20, 24, &umr_bitfield_default },
+	 { "TYPE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD4[] = {
+	 { "DEPTH", 0, 12, &umr_bitfield_default },
+	 { "PITCH", 13, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD5[] = {
+	 { "BASE_ARRAY", 0, 12, &umr_bitfield_default },
+	 { "LAST_ARRAY", 13, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD6[] = {
+	 { "COUNTER_BANK_ID", 12, 19, &umr_bitfield_default },
+	 { "LOD_HDW_CNT_EN", 20, 20, &umr_bitfield_default },
+	 { "MIN_LOD_WARN", 0, 11, &umr_bitfield_default },
+	 { "UNUNSED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD7[] = {
+	 { "UNUNSED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD0[] = {
+	 { "ANISO_BIAS", 21, 26, &umr_bitfield_default },
+	 { "ANISO_THRESHOLD", 16, 18, &umr_bitfield_default },
+	 { "CLAMP_X", 0, 2, &umr_bitfield_default },
+	 { "CLAMP_Y", 3, 5, &umr_bitfield_default },
+	 { "CLAMP_Z", 6, 8, &umr_bitfield_default },
+	 { "DEPTH_COMPARE_FUNC", 12, 14, &umr_bitfield_default },
+	 { "DISABLE_CUBE_WRAP", 28, 28, &umr_bitfield_default },
+	 { "FILTER_MODE", 29, 30, &umr_bitfield_default },
+	 { "FORCE_DEGAMMA", 20, 20, &umr_bitfield_default },
+	 { "FORCE_UNNORMALIZED", 15, 15, &umr_bitfield_default },
+	 { "MAX_ANISO_RATIO", 9, 11, &umr_bitfield_default },
+	 { "MC_COORD_TRUNC", 19, 19, &umr_bitfield_default },
+	 { "TRUNC_COORD", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD1[] = {
+	 { "MAX_LOD", 12, 23, &umr_bitfield_default },
+	 { "MIN_LOD", 0, 11, &umr_bitfield_default },
+	 { "PERF_MIP", 24, 27, &umr_bitfield_default },
+	 { "PERF_Z", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD2[] = {
+	 { "DISABLE_LSB_CEIL", 29, 29, &umr_bitfield_default },
+	 { "FILTER_PREC_FIX", 30, 30, &umr_bitfield_default },
+	 { "LOD_BIAS", 0, 13, &umr_bitfield_default },
+	 { "LOD_BIAS_SEC", 14, 19, &umr_bitfield_default },
+	 { "MIP_FILTER", 26, 27, &umr_bitfield_default },
+	 { "MIP_POINT_PRECLAMP", 28, 28, &umr_bitfield_default },
+	 { "XY_MAG_FILTER", 20, 21, &umr_bitfield_default },
+	 { "XY_MIN_FILTER", 22, 23, &umr_bitfield_default },
+	 { "Z_FILTER", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD3[] = {
+	 { "BORDER_COLOR_PTR", 0, 11, &umr_bitfield_default },
+	 { "BORDER_COLOR_TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL0[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL1[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL2[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL3[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL4[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY[] = {
+	 { "ADDR_BUSYORVAL", 31, 31, &umr_bitfield_default },
+	 { "CMD_BUSYORVAL", 30, 30, &umr_bitfield_default },
+	 { "PA_SX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "PCCMD_VALID", 27, 27, &umr_bitfield_default },
+	 { "POS_BANK0VAL0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "POS_BANK0VAL1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "POS_BANK0VAL2_BUSY", 17, 17, &umr_bitfield_default },
+	 { "POS_BANK0VAL3_BUSY", 16, 16, &umr_bitfield_default },
+	 { "POS_BANK1VAL0_BUSY", 15, 15, &umr_bitfield_default },
+	 { "POS_BANK1VAL1_BUSY", 14, 14, &umr_bitfield_default },
+	 { "POS_BANK1VAL2_BUSY", 13, 13, &umr_bitfield_default },
+	 { "POS_BANK1VAL3_BUSY", 12, 12, &umr_bitfield_default },
+	 { "POS_BANK2VAL0_BUSY", 11, 11, &umr_bitfield_default },
+	 { "POS_BANK2VAL1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "POS_BANK2VAL2_BUSY", 9, 9, &umr_bitfield_default },
+	 { "POS_BANK2VAL3_BUSY", 8, 8, &umr_bitfield_default },
+	 { "POS_BANK3VAL0_BUSY", 7, 7, &umr_bitfield_default },
+	 { "POS_BANK3VAL1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "POS_BANK3VAL2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "POS_BANK3VAL3_BUSY", 4, 4, &umr_bitfield_default },
+	 { "POS_FREE_OR_VALIDS", 0, 0, &umr_bitfield_default },
+	 { "POS_INMUX_VALID", 20, 20, &umr_bitfield_default },
+	 { "POS_REQUESTER_BUSY", 1, 1, &umr_bitfield_default },
+	 { "POS_SCBD_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VDATA0_VALID", 29, 29, &umr_bitfield_default },
+	 { "VDATA1_VALID", 28, 28, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ1", 26, 26, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ2", 25, 25, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ3", 24, 24, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ1", 23, 23, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ2", 22, 22, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ3", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_2[] = {
+	 { "COL_BUFF3_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_DBIF0_FIFO_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_DBIF0_READ_VALID", 24, 24, &umr_bitfield_default },
+	 { "COL_DBIF0_SENDFREE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_DBIF1_FIFO_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_DBIF1_READ_VALID", 21, 21, &umr_bitfield_default },
+	 { "COL_DBIF1_SENDFREE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_DBIF2_FIFO_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_DBIF2_READ_VALID", 18, 18, &umr_bitfield_default },
+	 { "COL_DBIF2_SENDFREE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_DBIF3_FIFO_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_DBIF3_READ_VALID", 15, 15, &umr_bitfield_default },
+	 { "COL_DBIF3_SENDFREE_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_REQ0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_REQ0_FREECNT_NE0", 10, 10, &umr_bitfield_default },
+	 { "COL_REQ0_IDLE", 11, 11, &umr_bitfield_default },
+	 { "COL_REQ1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_REQ1_FREECNT_NE0", 7, 7, &umr_bitfield_default },
+	 { "COL_REQ1_IDLE", 8, 8, &umr_bitfield_default },
+	 { "COL_REQ2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_REQ2_FREECNT_NE0", 4, 4, &umr_bitfield_default },
+	 { "COL_REQ2_IDLE", 5, 5, &umr_bitfield_default },
+	 { "COL_REQ3_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_REQ3_FREECNT_NE0", 1, 1, &umr_bitfield_default },
+	 { "COL_REQ3_IDLE", 2, 2, &umr_bitfield_default },
+	 { "COL_SCBD_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_3[] = {
+	 { "COL_BUFF1_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_4[] = {
+	 { "COL_BUFF0_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_1[] = {
+	 { "DEBUG_DATA", 7, 31, &umr_bitfield_default },
+	 { "SX_DB_QUAD_CREDIT", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_PRIORITY[] = {
+	 { "PIPE_ORDER_TS0", 0, 2, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS1", 3, 5, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS2", 6, 8, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS3", 9, 11, &umr_bitfield_default },
+	 { "TS0_DUR_MULT", 12, 13, &umr_bitfield_default },
+	 { "TS1_DUR_MULT", 14, 15, &umr_bitfield_default },
+	 { "TS2_DUR_MULT", 16, 17, &umr_bitfield_default },
+	 { "TS3_DUR_MULT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_CYCLES_0[] = {
+	 { "TS0_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS1_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_CYCLES_1[] = {
+	 { "TS2_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS3_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER_BINS[] = {
+	 { "BIN0_MAX", 4, 7, &umr_bitfield_default },
+	 { "BIN0_MIN", 0, 3, &umr_bitfield_default },
+	 { "BIN1_MAX", 12, 15, &umr_bitfield_default },
+	 { "BIN1_MIN", 8, 11, &umr_bitfield_default },
+	 { "BIN2_MAX", 20, 23, &umr_bitfield_default },
+	 { "BIN2_MIN", 16, 19, &umr_bitfield_default },
+	 { "BIN3_MAX", 28, 31, &umr_bitfield_default },
+	 { "BIN3_MIN", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL[] = {
+	 { "ENABLE_SQG_BOP_EVENTS", 25, 25, &umr_bitfield_default },
+	 { "ENABLE_SQG_TOP_EVENTS", 24, 24, &umr_bitfield_default },
+	 { "EXP_PRIORITY_ORDER", 21, 23, &umr_bitfield_default },
+	 { "GPR_WRITE_PRIORITY", 0, 20, &umr_bitfield_default },
+	 { "RSRC_MGMT_RESET", 26, 26, &umr_bitfield_default },
+	 { "TTRACE_STALL_ALL", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_CNTL[] = {
+	 { "DEBUG_GRBM_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_GROUP_SEL", 5, 9, &umr_bitfield_default },
+	 { "DEBUG_PIPE_SEL", 25, 27, &umr_bitfield_default },
+	 { "DEBUG_REG_EN", 31, 31, &umr_bitfield_default },
+	 { "DEBUG_SH_SEL", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_SIMD_SEL", 10, 15, &umr_bitfield_default },
+	 { "DEBUG_THREAD_TYPE_SEL", 1, 4, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_0", 17, 17, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_1", 18, 18, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_2", 19, 19, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_3", 20, 20, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_4", 21, 21, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_5", 22, 22, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_6", 23, 23, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL_1[] = {
+	 { "CRC_SIMD_ID_WADDR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "INTERP_ONE_PRIM_PER_ROW", 4, 4, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_CNT", 10, 13, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_MODE", 9, 9, &umr_bitfield_default },
+	 { "PC_LIMIT_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "PC_LIMIT_SIZE", 16, 31, &umr_bitfield_default },
+	 { "PC_LIMIT_STRICT", 7, 7, &umr_bitfield_default },
+	 { "VTX_DONE_DELAY", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_BUSY[] = {
+	 { "CS0_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CS1_BUSY", 8, 8, &umr_bitfield_default },
+	 { "CS2_BUSY", 9, 9, &umr_bitfield_default },
+	 { "CS3_BUSY", 11, 11, &umr_bitfield_default },
+	 { "CS4_BUSY", 12, 12, &umr_bitfield_default },
+	 { "CS5_BUSY", 13, 13, &umr_bitfield_default },
+	 { "CS6_BUSY", 14, 14, &umr_bitfield_default },
+	 { "CS7_BUSY", 15, 15, &umr_bitfield_default },
+	 { "CSG_BUSY", 7, 7, &umr_bitfield_default },
+	 { "ES_BUSY", 2, 2, &umr_bitfield_default },
+	 { "EVENT_CLCTR_BUSY", 15, 15, &umr_bitfield_default },
+	 { "GRBM_BUSY", 16, 16, &umr_bitfield_default },
+	 { "GS_BUSY", 3, 3, &umr_bitfield_default },
+	 { "HS_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LDS_WR_CTL0_BUSY", 10, 10, &umr_bitfield_default },
+	 { "LDS_WR_CTL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "LS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "PC_DEALLOC_BUSY", 20, 20, &umr_bitfield_default },
+	 { "PS0_BUSY", 5, 5, &umr_bitfield_default },
+	 { "PS1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "RSRC_ALLOC0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "RSRC_ALLOC1_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SPIS_BUSY", 17, 17, &umr_bitfield_default },
+	 { "VS_BUSY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SPI_CLK_CTRL[] = {
+	 { "ALL_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "GRP0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "GRP1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "GRP2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "GRP3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_USER_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_SM_CTRL_REG[] = {
+	 { "BASE_MODE", 16, 16, &umr_bitfield_default },
+	 { "LS_OVERRIDE", 22, 22, &umr_bitfield_default },
+	 { "MGCG_ENABLED", 12, 12, &umr_bitfield_default },
+	 { "OFF_SEQ_DELAY", 4, 11, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD_EN", 23, 23, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD", 24, 31, &umr_bitfield_default },
+	 { "ON_SEQ_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OVERRIDE", 21, 21, &umr_bitfield_default },
+	 { "SM_MODE_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "SM_MODE", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_RD_CTRL_REG[] = {
+	 { "REG_MUX_SEL", 8, 12, &umr_bitfield_default },
+	 { "ROW_MUX_SEL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_RD_REG[] = {
+	 { "READ_DATA", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_PC_CLK_CTRL[] = {
+	 { "BACK_CLK_ON_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "FRONT_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_BCI_CLK_CTRL[] = {
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE4_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE5_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "CORE6_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SLAVE_DEBUG_BUSY[] = {
+	 { "ES_VTX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "EVENT_CNTL_BUSY", 21, 21, &umr_bitfield_default },
+	 { "GS_VTX_BUSY", 3, 3, &umr_bitfield_default },
+	 { "HS_VTX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LS_VTX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "SGPR_WC00_BUSY", 9, 9, &umr_bitfield_default },
+	 { "SGPR_WC01_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SGPR_WC02_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SGPR_WC03_BUSY", 12, 12, &umr_bitfield_default },
+	 { "SGPR_WC10_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SGPR_WC11_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SGPR_WC12_BUSY", 15, 15, &umr_bitfield_default },
+	 { "SGPR_WC13_BUSY", 16, 16, &umr_bitfield_default },
+	 { "VGPR_WC00_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGPR_WC01_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGPR_WC10_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGPR_WC11_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VS_VTX_BUSY", 4, 4, &umr_bitfield_default },
+	 { "WAVEBUFFER0_BUSY", 17, 17, &umr_bitfield_default },
+	 { "WAVEBUFFER1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "WAVE_WC0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "WAVE_WC1_BUSY", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_CTR_CTRL[] = {
+	 { "LOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_DATA_REG[] = {
+	 { "CNT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PG_ENABLE_STATIC_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDS_CREDITS[] = {
+	 { "DS_CMD_CREDITS", 8, 15, &umr_bitfield_default },
+	 { "DS_DATA_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SX_EXPORT_BUFFER_SIZES[] = {
+	 { "COLOR_BUFFER_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_BUFFER_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SX_SCOREBOARD_BUFFER_SIZES[] = {
+	 { "COLOR_SCOREBOARD_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_SCOREBOARD_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBCI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_CNTL[] = {
+	 { "DISABLE_POWER_THROTTLE", 20, 20, &umr_bitfield_default },
+	 { "EXTEND_LDS_STALL", 9, 10, &umr_bitfield_default },
+	 { "GATHER4_DX9_MODE", 19, 19, &umr_bitfield_default },
+	 { "GATHER4_FLOAT_MODE", 16, 16, &umr_bitfield_default },
+	 { "LD_FLOAT_MODE", 18, 18, &umr_bitfield_default },
+	 { "LDS_STALL_PHASE_ADJUST", 11, 12, &umr_bitfield_default },
+	 { "PAD_STALL_EN", 8, 8, &umr_bitfield_default },
+	 { "PRECISION_COMPATIBILITY", 15, 15, &umr_bitfield_default },
+	 { "SYNC_PHASE_SH", 0, 1, &umr_bitfield_default },
+	 { "SYNC_PHASE_VC_SMX", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_STATUS[] = {
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_CGTT_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DEBUG_DATA[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CNTL[] = {
+	 { "ALIGNER_CREDIT", 16, 20, &umr_bitfield_default },
+	 { "TC_DATA_CREDIT", 13, 15, &umr_bitfield_default },
+	 { "TD_FIFO_CREDIT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CNTL_AUX[] = {
+	 { "ANISO_WEIGHT_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CS_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CGTT_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_STATUS[] = {
+	 { "AL_BUSY", 30, 30, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+	 { "FA_BUSY", 29, 29, &umr_bitfield_default },
+	 { "FA_LFIFO_EMPTYB", 21, 21, &umr_bitfield_default },
+	 { "FA_PFIFO_EMPTYB", 20, 20, &umr_bitfield_default },
+	 { "FA_SFIFO_EMPTYB", 22, 22, &umr_bitfield_default },
+	 { "FG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "FG_LFIFO_EMPTYB", 13, 13, &umr_bitfield_default },
+	 { "FG_PFIFO_EMPTYB", 12, 12, &umr_bitfield_default },
+	 { "FG_SFIFO_EMPTYB", 14, 14, &umr_bitfield_default },
+	 { "FL_BUSY", 27, 27, &umr_bitfield_default },
+	 { "FL_LFIFO_EMPTYB", 17, 17, &umr_bitfield_default },
+	 { "FL_PFIFO_EMPTYB", 16, 16, &umr_bitfield_default },
+	 { "FL_SFIFO_EMPTYB", 18, 18, &umr_bitfield_default },
+	 { "IN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "LA_BUSY", 26, 26, &umr_bitfield_default },
+	 { "TA_BUSY", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CONFIG[] = {
+	 { "SH0_GPR_PHASE_SEL", 1, 2, &umr_bitfield_default },
+	 { "SH1_GPR_PHASE_SEL", 3, 4, &umr_bitfield_default },
+	 { "SH2_GPR_PHASE_SEL", 5, 6, &umr_bitfield_default },
+	 { "SH3_GPR_PHASE_SEL", 7, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CNTL_STATUS[] = {
+	 { "DS_ADDR_CONFLICT", 4, 4, &umr_bitfield_default },
+	 { "DS_BANK_CONFLICT", 3, 3, &umr_bitfield_default },
+	 { "DS_RD_CLAMP", 6, 6, &umr_bitfield_default },
+	 { "DS_WR_CLAMP", 5, 5, &umr_bitfield_default },
+	 { "GDS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GRBM_WBUF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ORD_APP_BUSY", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_ADDR[] = {
+	 { "READ_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_DATA[] = {
+	 { "READ_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_ADDR[] = {
+	 { "BURST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_COUNT[] = {
+	 { "BURST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_DATA[] = {
+	 { "BURST_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_BURST_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_BURST_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WRITE_COMPLETE[] = {
+	 { "WRITE_COMPLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_CNTL[] = {
+	 { "AINC", 0, 5, &umr_bitfield_default },
+	 { "DMODE", 8, 8, &umr_bitfield_default },
+	 { "UNUSED1", 6, 7, &umr_bitfield_default },
+	 { "UNUSED2", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_COMPLETE[] = {
+	 { "COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "UNUSED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OFFSET0[] = {
+	 { "OFFSET0", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OFFSET1[] = {
+	 { "OFFSET1", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_DST[] = {
+	 { "DST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OP[] = {
+	 { "OP", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ENHANCE[] = {
+	 { "AUTO_INC_INDEX", 16, 16, &umr_bitfield_default },
+	 { "MISC", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_GDS_CLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DEBUG_CNTL[] = {
+	 { "GDS_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+	 { "UNUSED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_CNTL[] = {
+	 { "INDEX", 0, 5, &umr_bitfield_default },
+	 { "UNUSED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE[] = {
+	 { "COUNTER", 1, 12, &umr_bitfield_default },
+	 { "DED", 14, 14, &umr_bitfield_default },
+	 { "FLAG", 0, 0, &umr_bitfield_default },
+	 { "HEAD_FLAG", 28, 28, &umr_bitfield_default },
+	 { "HEAD_QUEUE", 16, 26, &umr_bitfield_default },
+	 { "HEAD_VALID", 27, 27, &umr_bitfield_default },
+	 { "RELEASE_ALL", 15, 15, &umr_bitfield_default },
+	 { "TYPE", 13, 13, &umr_bitfield_default },
+	 { "UNUSED1", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_SECDED_CNT[] = {
+	 { "DED", 16, 31, &umr_bitfield_default },
+	 { "SEC", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GRBM_SECDED_CNT[] = {
+	 { "DED", 16, 31, &umr_bitfield_default },
+	 { "SEC", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_DED[] = {
+	 { "ME0_CS_DED", 2, 2, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_PIX_DED", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_DED", 1, 1, &umr_bitfield_default },
+	 { "ME1_PIPE0_DED", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_DED", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_DED", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_DED", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_DED", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_DED", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_DED", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_DED", 11, 11, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG[] = {
+	 { "DEBUG_DEPTH_COMPRESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_FAST_STENCIL_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_FAST_Z_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_FORCE_DEPTH_READ", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_FORCE_FULL_Z_RANGE", 19, 20, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE0", 10, 11, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE1", 12, 13, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIZ_ENABLE", 8, 9, &umr_bitfield_default },
+	 { "DEBUG_FORCE_STENCIL_READ", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_NOOP_CULL_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_STENCIL_COMPRESS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DECOMPRESS_AFTER_N_ZPLANES", 24, 27, &umr_bitfield_default },
+	 { "DEPTH_CACHE_FORCE_MISS", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_DEPTH_SURFACE_SYNC", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_HTILE_SURFACE_SYNC", 31, 31, &umr_bitfield_default },
+	 { "DISABLE_SUMM_SQUADS", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_VPORT_ZPLANE_OPTIMIZATION", 23, 23, &umr_bitfield_default },
+	 { "FETCH_FULL_STENCIL_TILE", 3, 3, &umr_bitfield_default },
+	 { "FETCH_FULL_Z_TILE", 2, 2, &umr_bitfield_default },
+	 { "FORCE_MISS_IF_NOT_INFLIGHT", 29, 29, &umr_bitfield_default },
+	 { "FORCE_Z_MODE", 4, 5, &umr_bitfield_default },
+	 { "NEVER_FREE_Z_ONLY", 21, 21, &umr_bitfield_default },
+	 { "ONE_FREE_IN_FLIGHT", 28, 28, &umr_bitfield_default },
+	 { "ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG2[] = {
+	 { "ALLOW_COMPZ_BYTE_MASKING", 0, 0, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 9, 13, &umr_bitfield_default },
+	 { "DISABLE_DTT_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_HTILE_PAIRED_PIPES", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_NULL_EOT_FORWARDING", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_PREZL_CB_STALL_REZ", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL_REZ", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_PREZL_VIEWPORT_STALL", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_QUAD_COHERENCY_STALL", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_SINGLE_STENCIL_QUAD_SUMM", 31, 31, &umr_bitfield_default },
+	 { "DISABLE_TC_MASK_L0_CACHE", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_TC_ZRANGE_L0_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_TILE_COVERED_FOR_PS_ITER", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_WRITE_STALL_ON_RDWR_CONFLICT", 31, 31, &umr_bitfield_default },
+	 { "DTR_PREZ_STALLS_FOR_ETF_ROOM", 4, 4, &umr_bitfield_default },
+	 { "DTR_ROUND_ROBIN_ARB", 3, 3, &umr_bitfield_default },
+	 { "ENABLE_PREZL_CB_STALL", 6, 6, &umr_bitfield_default },
+	 { "ENABLE_PREZ_OF_REZ_SUMM", 28, 28, &umr_bitfield_default },
+	 { "ENABLE_SUBTILE_GROUPING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG3[] = {
+	 { "ALLOW_RF2P_RW_COLLISION", 17, 17, &umr_bitfield_default },
+	 { "DB_EXTRA_DEBUG3", 26, 31, &umr_bitfield_default },
+	 { "DISABLE_DI_DT_STALL", 25, 25, &umr_bitfield_default },
+	 { "DISABLE_EQAA_A2M_PERF_OPT", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_HIZ_ON_VPORT_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_HZ_TC_WRITE_COMBINE", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_BYPASS", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_DIRECT_FEEDBACK", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_WRITE_COMBINE", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_OP_S_DATA_FORWARDING", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_OP_Z_DATA_FORWARDING", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_OVERRASTERIZATION_FIX", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_RAM_READ_SUPPRESION_ON_FWD", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_REDUNDANT_PLANE_FLUSHES_OPT", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_TCP_CAM_BYPASS", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_TC_UPDATE_WRITE_COMBINE", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_TL_SSO_NULL_SUPPRESSION", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_ZCMP_DIRTY_SUPPRESSION", 8, 8, &umr_bitfield_default },
+	 { "DONT_DELETE_CONTEXT_SUSPEND", 29, 29, &umr_bitfield_default },
+	 { "DONT_INSERT_CONTEXT_SUSPEND", 28, 28, &umr_bitfield_default },
+	 { "ENABLE_DB_PROCESS_RESET", 26, 26, &umr_bitfield_default },
+	 { "ENABLE_INCOHERENT_EQAA_READS", 12, 12, &umr_bitfield_default },
+	 { "ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_TC_MA_ROUND_ROBIN_ARB", 23, 23, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_COMP_Z", 5, 5, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_SRC_Z", 6, 6, &umr_bitfield_default },
+	 { "FORCE_DB_IS_GOOD", 2, 2, &umr_bitfield_default },
+	 { "SLOW_PREZ_TO_A2M_OMASK_RATE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG4[] = {
+	 { "DB_EXTRA_DEBUG4", 6, 31, &umr_bitfield_default },
+	 { "DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_QC_STENCIL_MASK_SUMMATION", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_QC_Z_MASK_SUMMATION", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_RESUMM_TO_SINGLE_STENCIL", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_CREDIT_LIMIT[] = {
+	 { "DB_CB_LQUAD_CREDITS", 10, 12, &umr_bitfield_default },
+	 { "DB_CB_TILE_CREDITS", 24, 30, &umr_bitfield_default },
+	 { "DB_SC_QUAD_CREDITS", 5, 9, &umr_bitfield_default },
+	 { "DB_SC_TILE_CREDITS", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_WATERMARKS[] = {
+	 { "AUTO_FLUSH_HTILE", 30, 30, &umr_bitfield_default },
+	 { "AUTO_FLUSH_QUAD", 31, 31, &umr_bitfield_default },
+	 { "DEPTH_CACHELINE_FREE", 20, 26, &umr_bitfield_default },
+	 { "DEPTH_FLUSH", 5, 10, &umr_bitfield_default },
+	 { "DEPTH_FREE", 0, 4, &umr_bitfield_default },
+	 { "DEPTH_PENDING_FREE", 15, 19, &umr_bitfield_default },
+	 { "EARLY_Z_PANIC_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "FORCE_SUMMARIZE", 11, 14, &umr_bitfield_default },
+	 { "LATE_Z_PANIC_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "RE_Z_PANIC_DISABLE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SUBTILE_CONTROL[] = {
+	 { "MSAA16_X", 16, 17, &umr_bitfield_default },
+	 { "MSAA16_Y", 18, 19, &umr_bitfield_default },
+	 { "MSAA1_X", 0, 1, &umr_bitfield_default },
+	 { "MSAA1_Y", 2, 3, &umr_bitfield_default },
+	 { "MSAA2_X", 4, 5, &umr_bitfield_default },
+	 { "MSAA2_Y", 6, 7, &umr_bitfield_default },
+	 { "MSAA4_X", 8, 9, &umr_bitfield_default },
+	 { "MSAA4_Y", 10, 11, &umr_bitfield_default },
+	 { "MSAA8_X", 12, 13, &umr_bitfield_default },
+	 { "MSAA8_Y", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FREE_CACHELINES[] = {
+	 { "FREE_DTILE_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "FREE_HTILE_DEPTH", 21, 24, &umr_bitfield_default },
+	 { "FREE_PLANE_DEPTH", 7, 13, &umr_bitfield_default },
+	 { "FREE_Z_DEPTH", 14, 20, &umr_bitfield_default },
+	 { "QUAD_READ_REQS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FIFO_DEPTH1[] = {
+	 { "LTILE_PROBE_FIFO_DEPTH", 21, 28, &umr_bitfield_default },
+	 { "MCC_DEPTH", 10, 15, &umr_bitfield_default },
+	 { "MI_RDREQ_FIFO_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "MI_WRREQ_FIFO_DEPTH", 5, 9, &umr_bitfield_default },
+	 { "QC_DEPTH", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FIFO_DEPTH2[] = {
+	 { "EQUAD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "ETILE_OP_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "LQUAD_FIFO_DEPTH", 15, 24, &umr_bitfield_default },
+	 { "LTILE_OP_FIFO_DEPTH", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_CGTT_CLK_CTRL_0[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ZPASS_COUNT_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ZPASS_COUNT_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_0[] = {
+	 { "BUSY_DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_1[] = {
+	 { "BUSY_DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_2[] = {
+	 { "BUSY_DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_3[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_4[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_5[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_6[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_7[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_8[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_9[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_A[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_B[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_C[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_D[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_E[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_F[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_REDUNDANCY[] = {
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_BACKEND_MAP[] = {
+	 { "BACKEND_MAP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_GPU_ID[] = {
+	 { "GPU_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_DAISY_CHAIN[] = {
+	 { "RB_0", 0, 3, &umr_bitfield_default },
+	 { "RB_1", 4, 7, &umr_bitfield_default },
+	 { "RB_2", 8, 11, &umr_bitfield_default },
+	 { "RB_3", 12, 15, &umr_bitfield_default },
+	 { "RB_4", 16, 19, &umr_bitfield_default },
+	 { "RB_5", 20, 23, &umr_bitfield_default },
+	 { "RB_6", 24, 27, &umr_bitfield_default },
+	 { "RB_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE0[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE1[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE2[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE3[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE4[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE5[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE6[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE7[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE8[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE9[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE10[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE11[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE12[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE13[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE14[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE15[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE16[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE17[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE18[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE19[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE20[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE21[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE22[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE23[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE24[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE25[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE26[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE27[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE28[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE29[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE30[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE31[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL[] = {
+	 { "ALLOW_MRT_WITH_DUAL_SOURCE", 16, 16, &umr_bitfield_default },
+	 { "CC_CACHE_EVICT_POINT", 12, 15, &umr_bitfield_default },
+	 { "CM_CACHE_EVICT_POINT", 0, 3, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_BYPASS", 25, 25, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DISCARD_PIXEL", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DONT_RD_DST", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_RESULT_EQ_DEST", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_CC_IB_SERIALIZER_STATE_OPT", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_FULL_WRITE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_INTNORM_LE11BPC_CLAMPING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE", 31, 31, &umr_bitfield_default },
+	 { "DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG", 23, 23, &umr_bitfield_default },
+	 { "FC_CACHE_EVICT_POINT", 6, 9, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_TOGGLE", 20, 20, &umr_bitfield_default },
+	 { "FORCE_NEEDS_DST", 19, 19, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT", 29, 29, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_1[] = {
+	 { "CC_CACHE_NUM_TAGS", 11, 16, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 26, 31, &umr_bitfield_default },
+	 { "CM_CACHE_NUM_TAGS", 0, 4, &umr_bitfield_default },
+	 { "CM_TILE_FIFO_DEPTH", 17, 25, &umr_bitfield_default },
+	 { "FC_CACHE_NUM_TAGS", 5, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_2[] = {
+	 { "CC_EVEN_ODD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 23, 31, &umr_bitfield_default },
+	 { "FC_RDLAT_QUAD_FIFO_DEPTH", 15, 22, &umr_bitfield_default },
+	 { "FC_RDLAT_TILE_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_SEL2", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_CGTT_SCLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_13[] = {
+	 { "AC_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CACHE_CTRL_BUSY", 5, 5, &umr_bitfield_default },
+	 { "CRW_BUSY", 4, 4, &umr_bitfield_default },
+	 { "EVICT_PENDING", 9, 9, &umr_bitfield_default },
+	 { "FC_RD_PENDING", 8, 8, &umr_bitfield_default },
+	 { "FC_WR_PENDING", 7, 7, &umr_bitfield_default },
+	 { "LAST_RD_ARB_WINNER", 10, 10, &umr_bitfield_default },
+	 { "MC_WR_PENDING", 6, 6, &umr_bitfield_default },
+	 { "MU_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MU_STATE", 11, 18, &umr_bitfield_default },
+	 { "TILE_INTFC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "TQ_BUSY", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_14[] = {
+	 { "ADDR_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CACHE_CTL_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CLEAR_BUSY", 8, 8, &umr_bitfield_default },
+	 { "FOP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LAT_BUSY", 2, 2, &umr_bitfield_default },
+	 { "MERGE_BUSY", 5, 5, &umr_bitfield_default },
+	 { "QUAD_BUSY", 6, 6, &umr_bitfield_default },
+	 { "TILE_BUSY", 7, 7, &umr_bitfield_default },
+	 { "TILE_RETIREMENT_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_15[] = {
+	 { "CS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "DS_BUSY", 6, 6, &umr_bitfield_default },
+	 { "IB_BUSY", 8, 8, &umr_bitfield_default },
+	 { "RB_BUSY", 5, 5, &umr_bitfield_default },
+	 { "SF_BUSY", 3, 3, &umr_bitfield_default },
+	 { "SURF_SYNC_START", 2, 2, &umr_bitfield_default },
+	 { "SURF_SYNC_STATE", 0, 1, &umr_bitfield_default },
+	 { "TB_BUSY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_16[] = {
+	 { "CC_WRREQ_FIFO_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "CM_WRREQ_FIFO_EMPTY", 22, 22, &umr_bitfield_default },
+	 { "FC_WRREQ_FIFO_EMPTY", 21, 21, &umr_bitfield_default },
+	 { "LAST_RD_GRANT_VEC", 6, 9, &umr_bitfield_default },
+	 { "LAST_WR_GRANT_VEC", 16, 19, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDITS", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_17[] = {
+	 { "BB_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CC_BUSY", 2, 2, &umr_bitfield_default },
+	 { "CM_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CORE_SCLK_VLD", 5, 5, &umr_bitfield_default },
+	 { "FC_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MA_BUSY", 4, 4, &umr_bitfield_default },
+	 { "REG_SCLK0_VLD", 7, 7, &umr_bitfield_default },
+	 { "REG_SCLK1_VLD", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_18[] = {
+	 { "NOT_USED", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_INVALIDATE[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_STATUS[] = {
+	 { "TCP_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CNTL[] = {
+	 { "DISABLE_Z_MAP", 28, 28, &umr_bitfield_default },
+	 { "FLAT_BUF_CACHE_SWIZZLE", 5, 5, &umr_bitfield_default },
+	 { "FLAT_BUF_HASH_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FORCE_EOW_TAGRAM_CNT", 22, 27, &umr_bitfield_default },
+	 { "FORCE_EOW_TOTAL_CNT", 15, 20, &umr_bitfield_default },
+	 { "FORCE_HIT", 0, 0, &umr_bitfield_default },
+	 { "FORCE_MISS", 1, 1, &umr_bitfield_default },
+	 { "INV_ALL_VMIDS", 29, 29, &umr_bitfield_default },
+	 { "L1_SIZE", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CHAN_STEER_LO[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "CHAN3", 12, 15, &umr_bitfield_default },
+	 { "CHAN4", 16, 19, &umr_bitfield_default },
+	 { "CHAN5", 20, 23, &umr_bitfield_default },
+	 { "CHAN6", 24, 27, &umr_bitfield_default },
+	 { "CHAN7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CHAN_STEER_HI[] = {
+	 { "CHAN8", 0, 3, &umr_bitfield_default },
+	 { "CHAN9", 4, 7, &umr_bitfield_default },
+	 { "CHANA", 8, 11, &umr_bitfield_default },
+	 { "CHANB", 12, 15, &umr_bitfield_default },
+	 { "CHANC", 16, 19, &umr_bitfield_default },
+	 { "CHAND", 20, 23, &umr_bitfield_default },
+	 { "CHANE", 24, 27, &umr_bitfield_default },
+	 { "CHANF", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_ADDR_CONFIG[] = {
+	 { "COLHI_WIDTH", 6, 8, &umr_bitfield_default },
+	 { "NUM_BANKS", 4, 5, &umr_bitfield_default },
+	 { "NUM_TCC_BANKS", 0, 3, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CREDIT[] = {
+	 { "LFIFO_CREDIT", 0, 9, &umr_bitfield_default },
+	 { "REQ_FIFO_CREDIT", 16, 22, &umr_bitfield_default },
+	 { "TD_CREDIT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_TCP_CLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_BUFFER_ADDR_HASH_CNTL[] = {
+	 { "BANK_BITS", 8, 10, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 24, 26, &umr_bitfield_default },
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_EDC_COUNTER[] = {
+	 { "DED_COUNT", 16, 19, &umr_bitfield_default },
+	 { "SEC_COUNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_TCI_CLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_STATUS[] = {
+	 { "TCI_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_CNTL_1[] = {
+	 { "REQ_FIFO_DEPTH", 16, 23, &umr_bitfield_default },
+	 { "WBINVL1_NUM_CYCLES", 0, 15, &umr_bitfield_default },
+	 { "WDATA_RAM_DEPTH", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_CNTL_2[] = {
+	 { "L1_INVAL_ON_WBINVL2", 0, 0, &umr_bitfield_default },
+	 { "TCA_MAX_CREDIT", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_CTRL[] = {
+	 { "CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "LATENCY_FIFO_SIZE", 16, 19, &umr_bitfield_default },
+	 { "RATE", 2, 3, &umr_bitfield_default },
+	 { "SRC_FIFO_SIZE", 12, 15, &umr_bitfield_default },
+	 { "WB_OR_INV_ALL_VMIDS", 20, 20, &umr_bitfield_default },
+	 { "WRITEBACK_MARGIN", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_CGTT_SCLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_EDC_COUNTER[] = {
+	 { "DED_COUNT", 16, 19, &umr_bitfield_default },
+	 { "SEC_COUNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_CTRL[] = {
+	 { "HOLE_TIMEOUT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_CGTT_SCLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_SELECT[] = {
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_PS[] = {
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+	 { "CU_GROUP_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_PS[] = {
+	 { "EXCP_EN", 16, 22, &umr_bitfield_default },
+	 { "EXTRA_LDS_SIZE", 8, 15, &umr_bitfield_default },
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "WAVE_CNT_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_VS[] = {
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_VS[] = {
+	 { "EXCP_EN", 13, 19, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "SO_BASE0_EN", 8, 8, &umr_bitfield_default },
+	 { "SO_BASE1_EN", 9, 9, &umr_bitfield_default },
+	 { "SO_BASE2_EN", 10, 10, &umr_bitfield_default },
+	 { "SO_BASE3_EN", 11, 11, &umr_bitfield_default },
+	 { "SO_EN", 12, 12, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_GS[] = {
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_GS[] = {
+	 { "EXCP_EN", 7, 13, &umr_bitfield_default },
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_ES[] = {
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES[] = {
+	 { "EXCP_EN", 8, 14, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_HS[] = {
+	 { "CACHE_CTL", 24, 26, &umr_bitfield_default },
+	 { "CDBG_USER", 27, 27, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_HS[] = {
+	 { "EXCP_EN", 9, 15, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 8, 8, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_LS[] = {
+	 { "CACHE_CTL", 26, 28, &umr_bitfield_default },
+	 { "CDBG_USER", 29, 29, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS[] = {
+	 { "EXCP_EN", 16, 22, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DISPATCH_INITIATOR[] = {
+	 { "COMPUTE_SHADER_EN", 0, 0, &umr_bitfield_default },
+	 { "DATA_ATC", 12, 12, &umr_bitfield_default },
+	 { "DISPATCH_CACHE_CNTL", 7, 9, &umr_bitfield_default },
+	 { "FORCE_START_AT_000", 2, 2, &umr_bitfield_default },
+	 { "ORDERED_APPEND_ENBL", 3, 3, &umr_bitfield_default },
+	 { "ORDERED_APPEND_MODE", 4, 4, &umr_bitfield_default },
+	 { "ORDER_MODE", 6, 6, &umr_bitfield_default },
+	 { "PARTIAL_TG_EN", 1, 1, &umr_bitfield_default },
+	 { "RESTORE", 14, 14, &umr_bitfield_default },
+	 { "SCALAR_L1_INV_VOL", 10, 10, &umr_bitfield_default },
+	 { "USE_THREAD_DIMENSIONS", 5, 5, &umr_bitfield_default },
+	 { "VECTOR_L1_INV_VOL", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_X[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_Y[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_Z[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_X[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_Y[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_Z[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_X[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Y[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Z[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+	 { "INST_ATC", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TBA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TBA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_RSRC1[] = {
+	 { "BULKY", 24, 24, &umr_bitfield_default },
+	 { "CDBG_USER", 25, 25, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_RSRC2[] = {
+	 { "EXCP_EN", 24, 30, &umr_bitfield_default },
+	 { "EXCP_EN_MSB", 13, 14, &umr_bitfield_default },
+	 { "LDS_SIZE", 15, 23, &umr_bitfield_default },
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "TGID_X_EN", 7, 7, &umr_bitfield_default },
+	 { "TGID_Y_EN", 8, 8, &umr_bitfield_default },
+	 { "TGID_Z_EN", 9, 9, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 10, 10, &umr_bitfield_default },
+	 { "TIDIG_COMP_CNT", 11, 12, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_VMID[] = {
+	 { "DATA", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESOURCE_LIMITS[] = {
+	 { "CU_GROUP_COUNT", 24, 26, &umr_bitfield_default },
+	 { "FORCE_SIMD_DIST", 23, 23, &umr_bitfield_default },
+	 { "LOCK_THRESHOLD", 16, 21, &umr_bitfield_default },
+	 { "SIMD_DEST_CNTL", 22, 22, &umr_bitfield_default },
+	 { "TG_PER_CU", 12, 15, &umr_bitfield_default },
+	 { "WAVES_PER_SH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE0[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE1[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMPRING_SIZE[] = {
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_CNTL[] = {
+	 { "BUF_SWAP", 16, 17, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_WR[] = {
+	 { "RB_RPTR_WR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR_ADDR[] = {
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "OBSOLETE", 2, 31, &umr_bitfield_default },
+	 { "RB_WPTR_POLL_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "OBSOLETE", 0, 7, &umr_bitfield_default },
+	 { "RB_WPTR_POLL_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL[] = {
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS[] = {
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_VMID[] = {
+	 { "RB0_VMID", 0, 3, &umr_bitfield_default },
+	 { "RB1_VMID", 8, 11, &umr_bitfield_default },
+	 { "RB2_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_RADDR[] = {
+	 { "ME_RAM_RADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_WADDR[] = {
+	 { "ME_RAM_WADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_DATA[] = {
+	 { "ME_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CP_CLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_CNTL[] = {
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR_ADDR[] = {
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_CNTL[] = {
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR_ADDR[] = {
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING0[] = {
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING1[] = {
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING2[] = {
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING0[] = {
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING1[] = {
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING2[] = {
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PWR_CNTL[] = {
+	 { "GFX_CLK_HALT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEM_SLP_CNTL[] = {
+	 { "CP_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "CP_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "CP_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "CP_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+	 { "RESERVED", 2, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING0[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING1[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING2[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_EDC_MODE[] = {
+	 { "BYPASS", 31, 31, &umr_bitfield_default },
+	 { "DED_MODE", 20, 21, &umr_bitfield_default },
+	 { "FORCE_SEC_ON_DED", 16, 16, &umr_bitfield_default },
+	 { "PROP_FED", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CNTL[] = {
+	 { "FORCE_RETRY", 1, 1, &umr_bitfield_default },
+	 { "READ_CACHE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+	 { "RLC_ENABLE_F32", 0, 0, &umr_bitfield_default },
+	 { "RLC_STEP_F32", 3, 3, &umr_bitfield_default },
+	 { "SOFT_RESET_DEBUG_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTL[] = {
+	 { "CU_MASK_USED_OFF_HYST", 4, 11, &umr_bitfield_default },
+	 { "LB_CNT_CP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LB_CNT_REG_INC", 3, 3, &umr_bitfield_default },
+	 { "LB_CNT_SPIM_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "LOAD_BALANCE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SAVE_AND_RESTORE_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTR_MAX[] = {
+	 { "LB_CNTR_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTR_INIT[] = {
+	 { "LB_CNTR_INIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DRIVER_CPDMA_STATUS[] = {
+	 { "DRIVER_ACK", 4, 4, &umr_bitfield_default },
+	 { "DRIVER_REQUEST", 0, 0, &umr_bitfield_default },
+	 { "RESERVED1", 1, 3, &umr_bitfield_default },
+	 { "RESERVED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DEBUG_SELECT[] = {
+	 { "RESERVED", 15, 31, &umr_bitfield_default },
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_LSB[] = {
+	 { "GPU_CLOCKS_LSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_MSB[] = {
+	 { "GPU_CLOCKS_MSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CAPTURE_GPU_CLOCK_COUNT[] = {
+	 { "CAPTURE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MC_CNTL[] = {
+	 { "RDNFO_STALL", 28, 28, &umr_bitfield_default },
+	 { "RDNFO_URG", 20, 23, &umr_bitfield_default },
+	 { "RDREQ_PRIV", 27, 27, &umr_bitfield_default },
+	 { "RDREQ_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RDREQ_TRAN", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_B", 13, 19, &umr_bitfield_default },
+	 { "RESERVED", 29, 31, &umr_bitfield_default },
+	 { "WRNFO_STALL", 4, 4, &umr_bitfield_default },
+	 { "WRNFO_URG", 5, 8, &umr_bitfield_default },
+	 { "WRREQ_DW_IMASK", 9, 12, &umr_bitfield_default },
+	 { "WRREQ_PRIV", 3, 3, &umr_bitfield_default },
+	 { "WRREQ_SWAP", 0, 1, &umr_bitfield_default },
+	 { "WRREQ_TRAN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_UCODE_CNTL[] = {
+	 { "RLC_UCODE_FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_STAT[] = {
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "RLC_GPM_BUSY", 1, 1, &umr_bitfield_default },
+	 { "RLC_SPM_BUSY", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_32_RES_SEL[] = {
+	 { "RESERVED", 6, 31, &umr_bitfield_default },
+	 { "RES_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_32[] = {
+	 { "GPU_CLOCK_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SOFT_RESET_GPU[] = {
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+	 { "SOFT_RESET_GPU", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_CNTL[] = {
+	 { "CHUB_HANDSHAKE_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "DYN_PER_CU_PG_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "GFX_POWER_GATING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_GATING_SRC", 1, 1, &umr_bitfield_default },
+	 { "PG_ERROR_STATUS", 24, 31, &umr_bitfield_default },
+	 { "RESERVED1", 19, 23, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PD_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PU_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "STATIC_PER_CU_PG_ENABLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MEM_SLP_CNTL[] = {
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+	 { "RESERVED", 2, 7, &umr_bitfield_default },
+	 { "RLC_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RLC_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "RLC_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RLC_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFMON_CNTL[] = {
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "PERFMON_STATE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_RLC_CLK_CTRL[] = {
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LOAD_BALANCE_CNTR[] = {
+	 { "RLC_LOAD_BALANCE_CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGTT_MGCG_OVERRIDE[] = {
+	 { "OVERRIDE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGCG_CGLS_CTRL[] = {
+	 { "CGCG_CONTROLLER", 27, 27, &umr_bitfield_default },
+	 { "CGCG_EN", 0, 0, &umr_bitfield_default },
+	 { "CGCG_GFX_IDLE_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "CGCG_REG_CTRL", 28, 28, &umr_bitfield_default },
+	 { "CGLS_EN", 1, 1, &umr_bitfield_default },
+	 { "CGLS_REP_COMPANSAT_DELAY", 2, 7, &umr_bitfield_default },
+	 { "SLEEP_MODE", 29, 30, &umr_bitfield_default },
+	 { "SPARE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGCG_RAMP_CTRL[] = {
+	 { "DOWN_DIV_START_UNIT", 0, 3, &umr_bitfield_default },
+	 { "DOWN_DIV_STEP_UNIT", 4, 7, &umr_bitfield_default },
+	 { "STEP_DELAY_CNT", 16, 27, &umr_bitfield_default },
+	 { "STEP_DELAY_UNIT", 28, 31, &umr_bitfield_default },
+	 { "UP_DIV_START_UNIT", 8, 11, &umr_bitfield_default },
+	 { "UP_DIV_STEP_UNIT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DYN_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DYN_PG_REQUEST[] = {
+	 { "PG_REQUEST_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CU_STATUS[] = {
+	 { "WORK_PENDING", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_INIT_CU_MASK[] = {
+	 { "INIT_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[] = {
+	 { "ALWAYS_ACTIVE_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_PARAMS[] = {
+	 { "FIFO_SAMPLES", 1, 7, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLES", 8, 15, &umr_bitfield_default },
+	 { "SKIP_L2_CHECK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_THREAD1_DELAY[] = {
+	 { "CU_IDEL_DELAY", 0, 7, &umr_bitfield_default },
+	 { "LBPW_INNER_LOOP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LBPW_OUTER_LOOP_DELAY", 16, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_ALWAYS_ON_CU_MASK[] = {
+	 { "AON_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MAX_PG_CU[] = {
+	 { "MAX_POWERED_UP_CU", 0, 7, &umr_bitfield_default },
+	 { "SPARE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_AUTO_PG_CTRL[] = {
+	 { "AUTO_GRBM_REG_SAVE_ON_IDLE_EN", 1, 1, &umr_bitfield_default },
+	 { "AUTO_PG_EN", 0, 0, &umr_bitfield_default },
+	 { "AUTO_WAKE_UP_EN", 2, 2, &umr_bitfield_default },
+	 { "GRBM_REG_SAVE_GFX_IDLE_THRESHOLD", 3, 18, &umr_bitfield_default },
+	 { "PG_AFTER_GRBM_REG_SAVE_THRESHOLD", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_GRBM_REG_SAVE_CTRL[] = {
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+	 { "START_GRBM_REG_SAVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_PG_CTRL[] = {
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+	 { "START_PG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_PG_WAKE_UP_CTRL[] = {
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+	 { "START_PG_WAKE_UP", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_MASTER_INDEX[] = {
+	 { "CU_ID", 0, 3, &umr_bitfield_default },
+	 { "DATA_REG_ID", 14, 15, &umr_bitfield_default },
+	 { "NON_SE", 11, 13, &umr_bitfield_default },
+	 { "SE_ID", 6, 8, &umr_bitfield_default },
+	 { "SE_NONCU_ID", 9, 9, &umr_bitfield_default },
+	 { "SE_NONCU", 10, 10, &umr_bitfield_default },
+	 { "SH_ID", 4, 5, &umr_bitfield_default },
+	 { "SPARE", 14, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_CTRL[] = {
+	 { "BPM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "CGCG_OVERRIDE_0", 20, 20, &umr_bitfield_default },
+	 { "CGCG_OVERRIDE_1", 21, 21, &umr_bitfield_default },
+	 { "CGLS_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "CGLS_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "CGLS_OFF", 19, 19, &umr_bitfield_default },
+	 { "CGLS_ON", 18, 18, &umr_bitfield_default },
+	 { "MGCG_OVERRIDE_0", 22, 22, &umr_bitfield_default },
+	 { "MGCG_OVERRIDE_1", 23, 23, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "READ_COMMAND", 13, 13, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+	 { "RESERVED_1", 14, 15, &umr_bitfield_default },
+	 { "RESERVED_2", 24, 27, &umr_bitfield_default },
+	 { "WRITE_COMMAND", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SIGNATURE_CONTROL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SIGNATURE_MASK[] = {
+	 { "INPUT_BUS_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_DB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_PA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_VGT_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SQ_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE4[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE5[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE6[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE7[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_IA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_IA_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SPI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SPI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TD_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_CB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_BCI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_BCI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_CONTROL[] = {
+	 { "COPY_CENTROID", 7, 7, &umr_bitfield_default },
+	 { "COPY_SAMPLE", 8, 11, &umr_bitfield_default },
+	 { "DEPTH_CLEAR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DEPTH_COMPRESS_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "DEPTH_COPY", 2, 2, &umr_bitfield_default },
+	 { "RESUMMARIZE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STENCIL_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STENCIL_COMPRESS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "STENCIL_COPY", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_COUNT_CONTROL[] = {
+	 { "DBFAIL_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "PERFECT_ZPASS_COUNTS", 1, 1, &umr_bitfield_default },
+	 { "SAMPLE_RATE", 4, 6, &umr_bitfield_default },
+	 { "SFAIL_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "SLICE_EVEN_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 28, 31, &umr_bitfield_default },
+	 { "ZFAIL_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "ZPASS_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "ZPASS_INCREMENT_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "STENCIL_READ_ONLY", 25, 25, &umr_bitfield_default },
+	 { "Z_READ_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_OVERRIDE[] = {
+	 { "DISABLE_FULLY_COVERED", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_TILE_RATE_TILES", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_VIEWPORT_CLAMP", 16, 16, &umr_bitfield_default },
+	 { "FAST_STENCIL_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "FAST_Z_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "FORCE_COLOR_KILL", 10, 10, &umr_bitfield_default },
+	 { "FORCE_FULL_Z_RANGE", 13, 14, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE0", 2, 3, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE1", 4, 5, &umr_bitfield_default },
+	 { "FORCE_HIZ_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "FORCE_QC_SMASK_CONFLICT", 15, 15, &umr_bitfield_default },
+	 { "FORCE_SHADER_Z_ORDER", 6, 6, &umr_bitfield_default },
+	 { "FORCE_STENCIL_DIRTY", 28, 28, &umr_bitfield_default },
+	 { "FORCE_STENCIL_READ", 12, 12, &umr_bitfield_default },
+	 { "FORCE_STENCIL_VALID", 30, 30, &umr_bitfield_default },
+	 { "FORCE_Z_DIRTY", 27, 27, &umr_bitfield_default },
+	 { "FORCE_Z_LIMIT_SUMM", 19, 20, &umr_bitfield_default },
+	 { "FORCE_Z_READ", 11, 11, &umr_bitfield_default },
+	 { "FORCE_Z_VALID", 29, 29, &umr_bitfield_default },
+	 { "IGNORE_SC_ZRANGE", 17, 17, &umr_bitfield_default },
+	 { "MAX_TILES_IN_DTT", 21, 25, &umr_bitfield_default },
+	 { "NOOP_CULL_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "PRESERVE_COMPRESSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_OVERRIDE2[] = {
+	 { "DECOMPRESS_Z_ON_FLUSH", 8, 8, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_HIER_DEPTH_DISABLE", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_COLOR_ON_VALIDATION", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_FAST_PASS", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_REG_SNOOP", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION", 5, 5, &umr_bitfield_default },
+	 { "HIS_SFUNC_BF", 18, 20, &umr_bitfield_default },
+	 { "HIS_SFUNC_FF", 15, 17, &umr_bitfield_default },
+	 { "HIZ_ZFUNC", 12, 14, &umr_bitfield_default },
+	 { "PARTIAL_SQUAD_LAUNCH_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "PARTIAL_SQUAD_LAUNCH_COUNTDOWN", 2, 4, &umr_bitfield_default },
+	 { "PRESERVE_SRESULTS", 22, 22, &umr_bitfield_default },
+	 { "PRESERVE_ZRANGE", 21, 21, &umr_bitfield_default },
+	 { "SEPARATE_HIZS_FUNC_ENABLE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_HTILE_DATA_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_BOUNDS_MIN[] = {
+	 { "MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_BOUNDS_MAX[] = {
+	 { "MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_CLEAR[] = {
+	 { "CLEAR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_CLEAR[] = {
+	 { "DEPTH_CLEAR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_TL[] = {
+	 { "TL_X", 0, 15, &umr_bitfield_default },
+	 { "TL_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_BR[] = {
+	 { "BR_X", 0, 15, &umr_bitfield_default },
+	 { "BR_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_INFO[] = {
+	 { "ADDR5_SWIZZLE_MASK", 0, 3, &umr_bitfield_default },
+	 { "ARRAY_MODE", 4, 7, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 15, 16, &umr_bitfield_default },
+	 { "BANK_WIDTH", 13, 14, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 17, 18, &umr_bitfield_default },
+	 { "NUM_BANKS", 19, 20, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_INFO[] = {
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "FORMAT", 0, 1, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 2, 3, &umr_bitfield_default },
+	 { "READ_SIZE", 28, 28, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_SURFACE_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "ZRANGE_PRECISION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_INFO[] = {
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "FORMAT", 0, 0, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_STENCIL_DISABLE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_SIZE[] = {
+	 { "HEIGHT_TILE_MAX", 11, 21, &umr_bitfield_default },
+	 { "PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_SLICE[] = {
+	 { "SLICE_TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_2[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_3[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_OFFSET[] = {
+	 { "WINDOW_X_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "WINDOW_Y_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_RULE[] = {
+	 { "CLIP_RULE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_EDGERULE[] = {
+	 { "ER_LINE_BT", 28, 31, &umr_bitfield_default },
+	 { "ER_LINE_LR", 12, 17, &umr_bitfield_default },
+	 { "ER_LINE_RL", 18, 23, &umr_bitfield_default },
+	 { "ER_LINE_TB", 24, 27, &umr_bitfield_default },
+	 { "ER_POINT", 4, 7, &umr_bitfield_default },
+	 { "ER_RECT", 8, 11, &umr_bitfield_default },
+	 { "ER_TRI", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_HARDWARE_SCREEN_OFFSET[] = {
+	 { "HW_SCREEN_OFFSET_X", 0, 8, &umr_bitfield_default },
+	 { "HW_SCREEN_OFFSET_Y", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_TARGET_MASK[] = {
+	 { "TARGET0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "TARGET1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "TARGET2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "TARGET3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "TARGET4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "TARGET5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "TARGET6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "TARGET7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_SHADER_MASK[] = {
+	 { "OUTPUT0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "OUTPUT1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "OUTPUT2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "OUTPUT3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "OUTPUT4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "OUTPUT5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "OUTPUT6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "OUTPUT7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_0[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_1[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_0[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_0[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_1[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_1[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_2[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_2[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_3[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_3[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_4[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_4[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_5[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_5[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_6[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_6[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_7[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_7[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_8[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_8[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_9[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_9[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_10[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_10[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_11[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_11[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_12[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_12[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_13[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_13[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_14[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_14[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_15[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_15[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_RASTER_CONFIG[] = {
+	 { "PKR_MAP", 8, 9, &umr_bitfield_default },
+	 { "PKR_XSEL2", 14, 15, &umr_bitfield_default },
+	 { "PKR_XSEL", 10, 11, &umr_bitfield_default },
+	 { "PKR_YSEL", 12, 13, &umr_bitfield_default },
+	 { "RB_MAP_PKR0", 0, 1, &umr_bitfield_default },
+	 { "RB_MAP_PKR1", 2, 3, &umr_bitfield_default },
+	 { "RB_XSEL2", 4, 5, &umr_bitfield_default },
+	 { "RB_XSEL", 6, 6, &umr_bitfield_default },
+	 { "RB_YSEL", 7, 7, &umr_bitfield_default },
+	 { "SC_MAP", 16, 17, &umr_bitfield_default },
+	 { "SC_XSEL", 18, 19, &umr_bitfield_default },
+	 { "SC_YSEL", 20, 21, &umr_bitfield_default },
+	 { "SE_MAP", 24, 25, &umr_bitfield_default },
+	 { "SE_XSEL", 26, 27, &umr_bitfield_default },
+	 { "SE_YSEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PERFMON_CNTX_CNTL[] = {
+	 { "PERFMON_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RINGID[] = {
+	 { "RINGID", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MAX_VTX_INDX[] = {
+	 { "MAX_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MIN_VTX_INDX[] = {
+	 { "MIN_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INDX_OFFSET[] = {
+	 { "INDX_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_INDX[] = {
+	 { "RESET_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_RED[] = {
+	 { "BLEND_RED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_GREEN[] = {
+	 { "BLEND_GREEN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_BLUE[] = {
+	 { "BLEND_BLUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_ALPHA[] = {
+	 { "BLEND_ALPHA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_CONTROL[] = {
+	 { "STENCILFAIL_BF", 12, 15, &umr_bitfield_default },
+	 { "STENCILFAIL", 0, 3, &umr_bitfield_default },
+	 { "STENCILZFAIL_BF", 20, 23, &umr_bitfield_default },
+	 { "STENCILZFAIL", 8, 11, &umr_bitfield_default },
+	 { "STENCILZPASS_BF", 16, 19, &umr_bitfield_default },
+	 { "STENCILZPASS", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCILREFMASK[] = {
+	 { "STENCILMASK", 8, 15, &umr_bitfield_default },
+	 { "STENCILOPVAL", 24, 31, &umr_bitfield_default },
+	 { "STENCILTESTVAL", 0, 7, &umr_bitfield_default },
+	 { "STENCILWRITEMASK", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCILREFMASK_BF[] = {
+	 { "STENCILMASK_BF", 8, 15, &umr_bitfield_default },
+	 { "STENCILOPVAL_BF", 24, 31, &umr_bitfield_default },
+	 { "STENCILTESTVAL_BF", 0, 7, &umr_bitfield_default },
+	 { "STENCILWRITEMASK_BF", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_1[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_1[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_1[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_1[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_1[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_1[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_2[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_2[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_2[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_2[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_2[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_2[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_3[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_3[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_3[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_3[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_3[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_3[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_4[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_4[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_4[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_4[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_4[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_4[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_5[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_5[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_5[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_5[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_5[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_5[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_6[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_6[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_6[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_6[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_6[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_6[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_7[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_7[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_7[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_7[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_7[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_7[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_8[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_8[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_8[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_8[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_8[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_8[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_9[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_9[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_9[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_9[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_9[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_9[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_10[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_10[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_10[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_10[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_10[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_10[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_11[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_11[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_11[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_11[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_11[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_11[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_12[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_12[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_12[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_12[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_12[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_12[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_13[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_13[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_13[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_13[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_13[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_13[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_14[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_14[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_14[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_14[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_14[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_14[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_15[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_15[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_15[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_15[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_15[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_15[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_0[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_1[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_2[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_3[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_4[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_5[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_6[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_7[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_8[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_9[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_10[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_11[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_12[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_13[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_14[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_15[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_16[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_17[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_18[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_19[] = {
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_20[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_21[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_22[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_23[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_24[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_25[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_26[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_27[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_28[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_29[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_30[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_31[] = {
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_VS_OUT_CONFIG[] = {
+	 { "VS_EXPORT_COUNT", 1, 5, &umr_bitfield_default },
+	 { "VS_HALF_PACK", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_ENA[] = {
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_ADDR[] = {
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_INTERP_CONTROL_0[] = {
+	 { "FLAT_SHADE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PNT_SPRITE_ENA", 1, 1, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_W", 11, 13, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_X", 2, 4, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Y", 5, 7, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Z", 8, 10, &umr_bitfield_default },
+	 { "PNT_SPRITE_TOP_1", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_IN_CONTROL[] = {
+	 { "BC_OPTIMIZE_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "NUM_INTERP", 0, 5, &umr_bitfield_default },
+	 { "PARAM_GEN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_BARYC_CNTL[] = {
+	 { "FRONT_FACE_ALL_BITS", 24, 24, &umr_bitfield_default },
+	 { "LINEAR_CENTER_CNTL", 8, 8, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_CNTL", 12, 12, &umr_bitfield_default },
+	 { "PERSP_CENTER_CNTL", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTROID_CNTL", 4, 4, &umr_bitfield_default },
+	 { "POS_FLOAT_LOCATION", 16, 17, &umr_bitfield_default },
+	 { "POS_FLOAT_ULC", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_TMPRING_SIZE[] = {
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_POS_FORMAT[] = {
+	 { "POS0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "POS1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "POS2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "POS3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_Z_FORMAT[] = {
+	 { "Z_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_COL_FORMAT[] = {
+	 { "COL0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "COL1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "COL2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "COL3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+	 { "COL4_EXPORT_FORMAT", 16, 19, &umr_bitfield_default },
+	 { "COL5_EXPORT_FORMAT", 20, 23, &umr_bitfield_default },
+	 { "COL6_EXPORT_FORMAT", 24, 27, &umr_bitfield_default },
+	 { "COL7_EXPORT_FORMAT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND0_CONTROL[] = {
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND1_CONTROL[] = {
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND2_CONTROL[] = {
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND3_CONTROL[] = {
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND4_CONTROL[] = {
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND5_CONTROL[] = {
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND6_CONTROL[] = {
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND7_CONTROL[] = {
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCS_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_X_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_Y_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_SIZE[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_CULL_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_BASE_HI[] = {
+	 { "BASE_ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_BASE[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DRAW_INITIATOR[] = {
+	 { "MAJOR_MODE", 2, 3, &umr_bitfield_default },
+	 { "NOT_EOP", 5, 5, &umr_bitfield_default },
+	 { "SOURCE_SELECT", 0, 1, &umr_bitfield_default },
+	 { "SPRITE_EN_R6XX", 4, 4, &umr_bitfield_default },
+	 { "USE_OPAQUE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_IMMED_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_EVENT_ADDRESS_REG[] = {
+	 { "ADDRESS_LOW", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_CONTROL[] = {
+	 { "BACKFACE_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_COLOR_WRITES_ON_DEPTH_PASS", 31, 31, &umr_bitfield_default },
+	 { "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL", 30, 30, &umr_bitfield_default },
+	 { "STENCIL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCILFUNC_BF", 20, 22, &umr_bitfield_default },
+	 { "STENCILFUNC", 8, 10, &umr_bitfield_default },
+	 { "Z_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "ZFUNC", 4, 6, &umr_bitfield_default },
+	 { "Z_WRITE_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_EQAA[] = {
+	 { "ALPHA_TO_MASK_EQAA_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "ENABLE_POSTZ_OVERRASTERIZATION", 27, 27, &umr_bitfield_default },
+	 { "HIGH_QUALITY_INTERSECTIONS", 16, 16, &umr_bitfield_default },
+	 { "INCOHERENT_EQAA_READS", 17, 17, &umr_bitfield_default },
+	 { "INTERPOLATE_COMP_Z", 18, 18, &umr_bitfield_default },
+	 { "INTERPOLATE_SRC_Z", 19, 19, &umr_bitfield_default },
+	 { "MASK_EXPORT_NUM_SAMPLES", 8, 10, &umr_bitfield_default },
+	 { "MAX_ANCHOR_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "OVERRASTERIZATION_AMOUNT", 24, 26, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLES", 4, 6, &umr_bitfield_default },
+	 { "STATIC_ANCHOR_ASSOCIATIONS", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR_CONTROL[] = {
+	 { "DEGAMMA_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "ROP3", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SHADER_CONTROL[] = {
+	 { "ALPHA_TO_MASK_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "CONSERVATIVE_Z_EXPORT", 13, 14, &umr_bitfield_default },
+	 { "COVERAGE_TO_MASK_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "DEPTH_BEFORE_SHADER", 12, 12, &umr_bitfield_default },
+	 { "EXEC_ON_HIER_FAIL", 9, 9, &umr_bitfield_default },
+	 { "EXEC_ON_NOOP", 10, 10, &umr_bitfield_default },
+	 { "KILL_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MASK_EXPORT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "STENCIL_OP_VAL_EXPORT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "STENCIL_TEST_VAL_EXPORT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "Z_EXPORT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "Z_ORDER", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_CLIP_CNTL[] = {
+	 { "BOUNDARY_EDGE_FLAG_ENA", 18, 18, &umr_bitfield_default },
+	 { "CLIP_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "DIS_CLIP_ERR_DETECT", 20, 20, &umr_bitfield_default },
+	 { "DX_CLIP_SPACE_DEF", 19, 19, &umr_bitfield_default },
+	 { "DX_LINEAR_ATTR_CLIP_ENA", 24, 24, &umr_bitfield_default },
+	 { "DX_RASTERIZATION_KILL", 22, 22, &umr_bitfield_default },
+	 { "PS_UCP_MODE", 14, 15, &umr_bitfield_default },
+	 { "PS_UCP_Y_SCALE_NEG", 13, 13, &umr_bitfield_default },
+	 { "UCP_CULL_ONLY_ENA", 17, 17, &umr_bitfield_default },
+	 { "UCP_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "UCP_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "UCP_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "UCP_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "UCP_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "UCP_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "VTE_VPORT_PROVOKE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "VTX_KILL_OR", 21, 21, &umr_bitfield_default },
+	 { "ZCLIP_FAR_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "ZCLIP_NEAR_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_SC_MODE_CNTL[] = {
+	 { "CULL_BACK", 1, 1, &umr_bitfield_default },
+	 { "CULL_FRONT", 0, 0, &umr_bitfield_default },
+	 { "FACE", 2, 2, &umr_bitfield_default },
+	 { "MULTI_PRIM_IB_ENA", 21, 21, &umr_bitfield_default },
+	 { "PERSP_CORR_DIS", 20, 20, &umr_bitfield_default },
+	 { "POLYMODE_BACK_PTYPE", 8, 10, &umr_bitfield_default },
+	 { "POLYMODE_FRONT_PTYPE", 5, 7, &umr_bitfield_default },
+	 { "POLY_MODE", 3, 4, &umr_bitfield_default },
+	 { "POLY_OFFSET_BACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "POLY_OFFSET_FRONT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "POLY_OFFSET_PARA_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "PROVOKING_VTX_LAST", 19, 19, &umr_bitfield_default },
+	 { "VTX_WINDOW_OFFSET_ENABLE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VTE_CNTL[] = {
+	 { "PERFCOUNTER_REF", 11, 11, &umr_bitfield_default },
+	 { "VPORT_X_OFFSET_ENA", 1, 1, &umr_bitfield_default },
+	 { "VPORT_X_SCALE_ENA", 0, 0, &umr_bitfield_default },
+	 { "VPORT_Y_OFFSET_ENA", 3, 3, &umr_bitfield_default },
+	 { "VPORT_Y_SCALE_ENA", 2, 2, &umr_bitfield_default },
+	 { "VPORT_Z_OFFSET_ENA", 5, 5, &umr_bitfield_default },
+	 { "VPORT_Z_SCALE_ENA", 4, 4, &umr_bitfield_default },
+	 { "VTX_W0_FMT", 10, 10, &umr_bitfield_default },
+	 { "VTX_XY_FMT", 8, 8, &umr_bitfield_default },
+	 { "VTX_Z_FMT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VS_OUT_CNTL[] = {
+	 { "CLIP_DIST_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_6", 6, 6, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_7", 7, 7, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_0", 8, 8, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_1", 9, 9, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_2", 10, 10, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_3", 11, 11, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_4", 12, 12, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_5", 13, 13, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_6", 14, 14, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_7", 15, 15, &umr_bitfield_default },
+	 { "USE_VTX_EDGE_FLAG", 17, 17, &umr_bitfield_default },
+	 { "USE_VTX_GS_CUT_FLAG", 25, 25, &umr_bitfield_default },
+	 { "USE_VTX_KILL_FLAG", 20, 20, &umr_bitfield_default },
+	 { "USE_VTX_POINT_SIZE", 16, 16, &umr_bitfield_default },
+	 { "USE_VTX_RENDER_TARGET_INDX", 18, 18, &umr_bitfield_default },
+	 { "USE_VTX_VIEWPORT_INDX", 19, 19, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST0_VEC_ENA", 22, 22, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST1_VEC_ENA", 23, 23, &umr_bitfield_default },
+	 { "VS_OUT_MISC_SIDE_BUS_ENA", 24, 24, &umr_bitfield_default },
+	 { "VS_OUT_MISC_VEC_ENA", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_NANINF_CNTL[] = {
+	 { "VS_CLIP_DIST_INF_DISCARD", 14, 14, &umr_bitfield_default },
+	 { "VS_W_INF_RETAIN", 13, 13, &umr_bitfield_default },
+	 { "VS_W_NAN_TO_INF", 12, 12, &umr_bitfield_default },
+	 { "VS_XY_INF_RETAIN", 9, 9, &umr_bitfield_default },
+	 { "VS_XY_NAN_TO_INF", 8, 8, &umr_bitfield_default },
+	 { "VS_Z_INF_RETAIN", 11, 11, &umr_bitfield_default },
+	 { "VS_Z_NAN_TO_INF", 10, 10, &umr_bitfield_default },
+	 { "VTE_0XNANINF_IS_0", 3, 3, &umr_bitfield_default },
+	 { "VTE_NO_OUTPUT_NEG_0", 20, 20, &umr_bitfield_default },
+	 { "VTE_W_INF_DISCARD", 2, 2, &umr_bitfield_default },
+	 { "VTE_W_NAN_RETAIN", 6, 6, &umr_bitfield_default },
+	 { "VTE_W_RECIP_NAN_IS_0", 7, 7, &umr_bitfield_default },
+	 { "VTE_XY_INF_DISCARD", 0, 0, &umr_bitfield_default },
+	 { "VTE_XY_NAN_RETAIN", 4, 4, &umr_bitfield_default },
+	 { "VTE_Z_INF_DISCARD", 1, 1, &umr_bitfield_default },
+	 { "VTE_Z_NAN_RETAIN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_CNTL[] = {
+	 { "DIAMOND_ADJUST", 4, 4, &umr_bitfield_default },
+	 { "EXPAND_FULL_LENGTH", 2, 2, &umr_bitfield_default },
+	 { "FRACTIONAL_ACCUM", 3, 3, &umr_bitfield_default },
+	 { "LINE_STIPPLE_RESET", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_SCALE[] = {
+	 { "LINE_STIPPLE_SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PRIM_FILTER_CNTL[] = {
+	 { "LINE_EXPAND_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINE_FILTER_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "POINT_EXPAND_ENA", 6, 6, &umr_bitfield_default },
+	 { "POINT_FILTER_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "PRIM_EXPAND_CONSTANT", 8, 15, &umr_bitfield_default },
+	 { "RECTANGLE_EXPAND_ENA", 7, 7, &umr_bitfield_default },
+	 { "RECTANGLE_FILTER_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "TRIANGLE_EXPAND_ENA", 4, 4, &umr_bitfield_default },
+	 { "TRIANGLE_FILTER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "XMAX_RIGHT_EXCLUSION", 30, 30, &umr_bitfield_default },
+	 { "YMAX_BOTTOM_EXCLUSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POINT_SIZE[] = {
+	 { "HEIGHT", 0, 15, &umr_bitfield_default },
+	 { "WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POINT_MINMAX[] = {
+	 { "MAX_SIZE", 16, 31, &umr_bitfield_default },
+	 { "MIN_SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_CNTL[] = {
+	 { "WIDTH", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_STIPPLE[] = {
+	 { "AUTO_RESET_CNTL", 29, 30, &umr_bitfield_default },
+	 { "LINE_PATTERN", 0, 15, &umr_bitfield_default },
+	 { "PATTERN_BIT_ORDER", 28, 28, &umr_bitfield_default },
+	 { "REPEAT_COUNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_OUTPUT_PATH_CNTL[] = {
+	 { "PATH_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_CNTL[] = {
+	 { "TESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_MAX_TESS_LEVEL[] = {
+	 { "MAX_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_MIN_TESS_LEVEL[] = {
+	 { "MIN_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_REUSE_DEPTH[] = {
+	 { "REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_PRIM_TYPE[] = {
+	 { "PRIM_ORDER", 16, 18, &umr_bitfield_default },
+	 { "PRIM_TYPE", 0, 4, &umr_bitfield_default },
+	 { "RETAIN_ORDER", 14, 14, &umr_bitfield_default },
+	 { "RETAIN_QUADS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_FIRST_DECR[] = {
+	 { "FIRST_DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_DECR[] = {
+	 { "DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_0_CNTL[] = {
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_1_CNTL[] = {
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_0_FMT_CNTL[] = {
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_1_FMT_CNTL[] = {
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_MODE[] = {
+	 { "COMPUTE_MODE", 14, 14, &umr_bitfield_default },
+	 { "CUT_MODE", 4, 5, &umr_bitfield_default },
+	 { "ELEMENT_INFO_EN", 16, 16, &umr_bitfield_default },
+	 { "ES_PASSTHRU", 13, 13, &umr_bitfield_default },
+	 { "ES_WRITE_OPTIMIZE", 19, 19, &umr_bitfield_default },
+	 { "FAST_COMPUTE_MODE", 15, 15, &umr_bitfield_default },
+	 { "GS_C_PACK_EN", 11, 11, &umr_bitfield_default },
+	 { "GS_WRITE_OPTIMIZE", 20, 20, &umr_bitfield_default },
+	 { "MODE", 0, 2, &umr_bitfield_default },
+	 { "ONCHIP", 21, 22, &umr_bitfield_default },
+	 { "PARTIAL_THD_AT_EOI", 17, 17, &umr_bitfield_default },
+	 { "RESERVED_0", 3, 3, &umr_bitfield_default },
+	 { "RESERVED_1", 6, 10, &umr_bitfield_default },
+	 { "RESERVED_2", 12, 12, &umr_bitfield_default },
+	 { "SUPPRESS_CUTS", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_MODE_CNTL_0[] = {
+	 { "LINE_STIPPLE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MSAA_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PKR", 3, 3, &umr_bitfield_default },
+	 { "VPORT_SCISSOR_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_MODE_CNTL_1[] = {
+	 { "FORCE_EOV_CNTDWN_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "FORCE_EOV_REZ_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE", 20, 23, &umr_bitfield_default },
+	 { "KILL_PIX_POST_DETAIL_MASK", 15, 15, &umr_bitfield_default },
+	 { "KILL_PIX_POST_HI_Z", 14, 14, &umr_bitfield_default },
+	 { "MULTI_GPU_PRIM_DISCARD_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "MULTI_GPU_SUPERTILE_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_PRIMITIVE_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_WATER_MARK", 28, 30, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLE", 16, 16, &umr_bitfield_default },
+	 { "SUPERTILE_WALK_ORDER_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "TILE_COVER_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "TILE_COVER_NO_SCISSOR", 10, 10, &umr_bitfield_default },
+	 { "TILE_WALK_ORDER_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "WALK_ALIGN8_PRIM_FITS_ST", 2, 2, &umr_bitfield_default },
+	 { "WALK_ALIGNMENT", 1, 1, &umr_bitfield_default },
+	 { "WALK_FENCE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "WALK_FENCE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "WALK_SIZE", 0, 0, &umr_bitfield_default },
+	 { "ZMM_LINE_EXTENT", 11, 11, &umr_bitfield_default },
+	 { "ZMM_LINE_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "ZMM_RECT_EXTENT", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_PER_ES[] = {
+	 { "GS_PER_ES", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ES_PER_GS[] = {
+	 { "ES_PER_GS", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_PER_VS[] = {
+	 { "GS_PER_VS", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_1[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_2[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_3[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_OUT_PRIM_TYPE[] = {
+	 { "OUTPRIM_TYPE_1", 8, 13, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_2", 16, 21, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_3", 22, 27, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE", 0, 5, &umr_bitfield_default },
+	 { "UNIQUE_TYPE_PER_STREAM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_SIZE[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_MAX_SIZE[] = {
+	 { "MAX_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_INDEX_TYPE[] = {
+	 { "ATC", 8, 8, &umr_bitfield_default },
+	 { "BUF_TYPE", 4, 5, &umr_bitfield_default },
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+	 { "NOT_EOP", 9, 9, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 6, 7, &umr_bitfield_default },
+	 { "REQ_PATH", 10, 10, &umr_bitfield_default },
+	 { "SWAP_MODE", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVEID_EN[] = {
+	 { "DISABLE_RESET_ON_EOI", 1, 1, &umr_bitfield_default },
+	 { "PRIMITIVEID_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVEID_RESET[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_EVENT_INITIATOR[] = {
+	 { "ADDRESS_HI", 18, 26, &umr_bitfield_default },
+	 { "EVENT_TYPE", 0, 5, &umr_bitfield_default },
+	 { "EXTENDED_EVENT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_EN[] = {
+	 { "RESET_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_0[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_1[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_MULTI_VGT_PARAM[] = {
+	 { "PARTIAL_ES_WAVE_ON", 18, 18, &umr_bitfield_default },
+	 { "PARTIAL_VS_WAVE_ON", 16, 16, &umr_bitfield_default },
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "SWITCH_ON_EOI", 19, 19, &umr_bitfield_default },
+	 { "SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ESGS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_REUSE_OFF[] = {
+	 { "REUSE_OFF", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VTX_CNT_EN[] = {
+	 { "VTX_CNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_HTILE_SURFACE[] = {
+	 { "DST_OUTSIDE_ZERO_TO_ONE", 16, 16, &umr_bitfield_default },
+	 { "FULL_CACHE", 1, 1, &umr_bitfield_default },
+	 { "HTILE_USES_PRELOAD_WIN", 2, 2, &umr_bitfield_default },
+	 { "LINEAR", 0, 0, &umr_bitfield_default },
+	 { "PREFETCH_HEIGHT", 10, 15, &umr_bitfield_default },
+	 { "PREFETCH_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PRELOAD", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE0[] = {
+	 { "COMPAREFUNC0", 0, 2, &umr_bitfield_default },
+	 { "COMPAREMASK0", 12, 19, &umr_bitfield_default },
+	 { "COMPAREVALUE0", 4, 11, &umr_bitfield_default },
+	 { "ENABLE0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE1[] = {
+	 { "COMPAREFUNC1", 0, 2, &umr_bitfield_default },
+	 { "COMPAREMASK1", 12, 19, &umr_bitfield_default },
+	 { "COMPAREVALUE1", 4, 11, &umr_bitfield_default },
+	 { "ENABLE1", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PRELOAD_CONTROL[] = {
+	 { "MAX_X", 16, 23, &umr_bitfield_default },
+	 { "MAX_Y", 24, 31, &umr_bitfield_default },
+	 { "START_X", 0, 7, &umr_bitfield_default },
+	 { "START_Y", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_0[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_0[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_1[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_1[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_2[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_2[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_3[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_3[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[] = {
+	 { "VERTEX_STRIDE", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_MAX_VERT_OUT[] = {
+	 { "MAX_VERT_OUT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_SHADER_STAGES_EN[] = {
+	 { "DYNAMIC_HS", 8, 8, &umr_bitfield_default },
+	 { "ES_EN", 3, 4, &umr_bitfield_default },
+	 { "GS_EN", 5, 5, &umr_bitfield_default },
+	 { "HS_EN", 2, 2, &umr_bitfield_default },
+	 { "LS_EN", 0, 1, &umr_bitfield_default },
+	 { "VS_EN", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_LS_HS_CONFIG[] = {
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+	 { "HS_NUM_OUTPUT_CP", 14, 19, &umr_bitfield_default },
+	 { "NUM_PATCHES", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_1[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_2[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_3[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_PARAM[] = {
+	 { "DEPRECATED", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_DONUTS", 14, 14, &umr_bitfield_default },
+	 { "NUM_DS_WAVES_PER_SIMD", 10, 13, &umr_bitfield_default },
+	 { "PARTITIONING", 2, 4, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 15, 16, &umr_bitfield_default },
+	 { "RESERVED_REDUC_AXIS", 8, 8, &umr_bitfield_default },
+	 { "TOPOLOGY", 5, 7, &umr_bitfield_default },
+	 { "TYPE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ALPHA_TO_MASK[] = {
+	 { "ALPHA_TO_MASK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET0", 8, 9, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET1", 10, 11, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET2", 12, 13, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET3", 14, 15, &umr_bitfield_default },
+	 { "OFFSET_ROUND", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[] = {
+	 { "POLY_OFFSET_DB_IS_FLOAT_FMT", 8, 8, &umr_bitfield_default },
+	 { "POLY_OFFSET_NEG_NUM_DB_BITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_CLAMP[] = {
+	 { "CLAMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_INSTANCE_CNT[] = {
+	 { "CNT", 2, 8, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_CONFIG[] = {
+	 { "RAST_STREAM", 4, 6, &umr_bitfield_default },
+	 { "RAST_STREAM_MASK", 8, 11, &umr_bitfield_default },
+	 { "STREAMOUT_0_EN", 0, 0, &umr_bitfield_default },
+	 { "STREAMOUT_1_EN", 1, 1, &umr_bitfield_default },
+	 { "STREAMOUT_2_EN", 2, 2, &umr_bitfield_default },
+	 { "STREAMOUT_3_EN", 3, 3, &umr_bitfield_default },
+	 { "USE_RAST_STREAM_MASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_CONFIG[] = {
+	 { "STREAM_0_BUFFER_EN", 0, 3, &umr_bitfield_default },
+	 { "STREAM_1_BUFFER_EN", 4, 7, &umr_bitfield_default },
+	 { "STREAM_2_BUFFER_EN", 8, 11, &umr_bitfield_default },
+	 { "STREAM_3_BUFFER_EN", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_0[] = {
+	 { "DISTANCE_0", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_1", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_2", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_3", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_4", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_5", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_6", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_1[] = {
+	 { "DISTANCE_10", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_11", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_12", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_13", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_14", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_15", 28, 31, &umr_bitfield_default },
+	 { "DISTANCE_8", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_9", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_CNTL[] = {
+	 { "DX10_DIAMOND_TEST_ENA", 12, 12, &umr_bitfield_default },
+	 { "EXPAND_LINE_WIDTH", 9, 9, &umr_bitfield_default },
+	 { "LAST_PIXEL", 10, 10, &umr_bitfield_default },
+	 { "PERPENDICULAR_ENDCAP_ENA", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_CONFIG[] = {
+	 { "AA_MASK_CENTROID_DTMN", 4, 4, &umr_bitfield_default },
+	 { "DETAIL_TO_EXPOSED_MODE", 24, 25, &umr_bitfield_default },
+	 { "MAX_SAMPLE_DIST", 13, 16, &umr_bitfield_default },
+	 { "MSAA_EXPOSED_SAMPLES", 20, 22, &umr_bitfield_default },
+	 { "MSAA_NUM_SAMPLES", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_VTX_CNTL[] = {
+	 { "PIX_CENTER", 0, 0, &umr_bitfield_default },
+	 { "QUANT_MODE", 3, 5, &umr_bitfield_default },
+	 { "ROUND_MODE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_VERT_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_VERT_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_HORZ_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_HORZ_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[] = {
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[] = {
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[] = {
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[] = {
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_MASK_X0Y0_X1Y0[] = {
+	 { "AA_MASK_X0Y0", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_MASK_X0Y1_X1Y1[] = {
+	 { "AA_MASK_X0Y1", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VERTEX_REUSE_BLOCK_CNTL[] = {
+	 { "VTX_REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_OUT_DEALLOC_CNTL[] = {
+	 { "DEALLOC_DIST", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_PITCH[] = {
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_INFO[] = {
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_ATTRIB[] = {
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_PITCH[] = {
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_INFO[] = {
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_ATTRIB[] = {
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_PITCH[] = {
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_INFO[] = {
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_ATTRIB[] = {
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_PITCH[] = {
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_INFO[] = {
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_ATTRIB[] = {
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_PITCH[] = {
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_INFO[] = {
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_ATTRIB[] = {
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_PITCH[] = {
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_INFO[] = {
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_ATTRIB[] = {
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_PITCH[] = {
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_INFO[] = {
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_ATTRIB[] = {
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_PITCH[] = {
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_VIEW[] = {
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_INFO[] = {
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_ATTRIB[] = {
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gfx60_regs.i b/src/lib/ip/gfx60_regs.i
new file mode 100644
index 0000000..20e7963
--- /dev/null
+++ b/src/lib/ip/gfx60_regs.i
@@ -0,0 +1,1645 @@
+	{ "ixCLIPPER_DEBUG_REG00", REG_SMC, 0x0000, &ixCLIPPER_DEBUG_REG00[0], sizeof(ixCLIPPER_DEBUG_REG00)/sizeof(ixCLIPPER_DEBUG_REG00[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG01", REG_SMC, 0x0001, &ixCLIPPER_DEBUG_REG01[0], sizeof(ixCLIPPER_DEBUG_REG01)/sizeof(ixCLIPPER_DEBUG_REG01[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG02", REG_SMC, 0x0002, &ixCLIPPER_DEBUG_REG02[0], sizeof(ixCLIPPER_DEBUG_REG02)/sizeof(ixCLIPPER_DEBUG_REG02[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG03", REG_SMC, 0x0003, &ixCLIPPER_DEBUG_REG03[0], sizeof(ixCLIPPER_DEBUG_REG03)/sizeof(ixCLIPPER_DEBUG_REG03[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG04", REG_SMC, 0x0004, &ixCLIPPER_DEBUG_REG04[0], sizeof(ixCLIPPER_DEBUG_REG04)/sizeof(ixCLIPPER_DEBUG_REG04[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG05", REG_SMC, 0x0005, &ixCLIPPER_DEBUG_REG05[0], sizeof(ixCLIPPER_DEBUG_REG05)/sizeof(ixCLIPPER_DEBUG_REG05[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG06", REG_SMC, 0x0006, &ixCLIPPER_DEBUG_REG06[0], sizeof(ixCLIPPER_DEBUG_REG06)/sizeof(ixCLIPPER_DEBUG_REG06[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG07", REG_SMC, 0x0007, &ixCLIPPER_DEBUG_REG07[0], sizeof(ixCLIPPER_DEBUG_REG07)/sizeof(ixCLIPPER_DEBUG_REG07[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG08", REG_SMC, 0x0008, &ixCLIPPER_DEBUG_REG08[0], sizeof(ixCLIPPER_DEBUG_REG08)/sizeof(ixCLIPPER_DEBUG_REG08[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG09", REG_SMC, 0x0009, &ixCLIPPER_DEBUG_REG09[0], sizeof(ixCLIPPER_DEBUG_REG09)/sizeof(ixCLIPPER_DEBUG_REG09[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG10", REG_SMC, 0x000A, &ixCLIPPER_DEBUG_REG10[0], sizeof(ixCLIPPER_DEBUG_REG10)/sizeof(ixCLIPPER_DEBUG_REG10[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG11", REG_SMC, 0x000B, &ixCLIPPER_DEBUG_REG11[0], sizeof(ixCLIPPER_DEBUG_REG11)/sizeof(ixCLIPPER_DEBUG_REG11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG12", REG_SMC, 0x000C, &ixCLIPPER_DEBUG_REG12[0], sizeof(ixCLIPPER_DEBUG_REG12)/sizeof(ixCLIPPER_DEBUG_REG12[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG13", REG_SMC, 0x000D, &ixCLIPPER_DEBUG_REG13[0], sizeof(ixCLIPPER_DEBUG_REG13)/sizeof(ixCLIPPER_DEBUG_REG13[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG14", REG_SMC, 0x000E, &ixCLIPPER_DEBUG_REG14[0], sizeof(ixCLIPPER_DEBUG_REG14)/sizeof(ixCLIPPER_DEBUG_REG14[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG15", REG_SMC, 0x000F, &ixCLIPPER_DEBUG_REG15[0], sizeof(ixCLIPPER_DEBUG_REG15)/sizeof(ixCLIPPER_DEBUG_REG15[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG16", REG_SMC, 0x0010, &ixCLIPPER_DEBUG_REG16[0], sizeof(ixCLIPPER_DEBUG_REG16)/sizeof(ixCLIPPER_DEBUG_REG16[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG17", REG_SMC, 0x0011, &ixCLIPPER_DEBUG_REG17[0], sizeof(ixCLIPPER_DEBUG_REG17)/sizeof(ixCLIPPER_DEBUG_REG17[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG18", REG_SMC, 0x0012, &ixCLIPPER_DEBUG_REG18[0], sizeof(ixCLIPPER_DEBUG_REG18)/sizeof(ixCLIPPER_DEBUG_REG18[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG19", REG_SMC, 0x0013, &ixCLIPPER_DEBUG_REG19[0], sizeof(ixCLIPPER_DEBUG_REG19)/sizeof(ixCLIPPER_DEBUG_REG19[0]), 0, 0 },
+	{ "ixSQ_WAVE_HW_ID", REG_SMC, 0x0014, &ixSQ_WAVE_HW_ID[0], sizeof(ixSQ_WAVE_HW_ID)/sizeof(ixSQ_WAVE_HW_ID[0]), 0, 0 },
+	{ "ixSQ_WAVE_GPR_ALLOC", REG_SMC, 0x0015, &ixSQ_WAVE_GPR_ALLOC[0], sizeof(ixSQ_WAVE_GPR_ALLOC)/sizeof(ixSQ_WAVE_GPR_ALLOC[0]), 0, 0 },
+	{ "ixSQ_WAVE_LDS_ALLOC", REG_SMC, 0x0016, &ixSQ_WAVE_LDS_ALLOC[0], sizeof(ixSQ_WAVE_LDS_ALLOC)/sizeof(ixSQ_WAVE_LDS_ALLOC[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_STS", REG_SMC, 0x0017, &ixSQ_WAVE_IB_STS[0], sizeof(ixSQ_WAVE_IB_STS)/sizeof(ixSQ_WAVE_IB_STS[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG0", REG_SMC, 0x0018, &ixSETUP_DEBUG_REG0[0], sizeof(ixSETUP_DEBUG_REG0)/sizeof(ixSETUP_DEBUG_REG0[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG1", REG_SMC, 0x0019, &ixSETUP_DEBUG_REG1[0], sizeof(ixSETUP_DEBUG_REG1)/sizeof(ixSETUP_DEBUG_REG1[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG2", REG_SMC, 0x001A, &ixSETUP_DEBUG_REG2[0], sizeof(ixSETUP_DEBUG_REG2)/sizeof(ixSETUP_DEBUG_REG2[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG3", REG_SMC, 0x001B, &ixSETUP_DEBUG_REG3[0], sizeof(ixSETUP_DEBUG_REG3)/sizeof(ixSETUP_DEBUG_REG3[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG4", REG_SMC, 0x001C, &ixSETUP_DEBUG_REG4[0], sizeof(ixSETUP_DEBUG_REG4)/sizeof(ixSETUP_DEBUG_REG4[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG5", REG_SMC, 0x001D, &ixSETUP_DEBUG_REG5[0], sizeof(ixSETUP_DEBUG_REG5)/sizeof(ixSETUP_DEBUG_REG5[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG30", REG_SMC, 0x001E, &ixVGT_DEBUG_REG30[0], sizeof(ixVGT_DEBUG_REG30)/sizeof(ixVGT_DEBUG_REG30[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG31", REG_SMC, 0x001F, &ixVGT_DEBUG_REG31[0], sizeof(ixVGT_DEBUG_REG31)/sizeof(ixVGT_DEBUG_REG31[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG32", REG_SMC, 0x0020, &ixVGT_DEBUG_REG32[0], sizeof(ixVGT_DEBUG_REG32)/sizeof(ixVGT_DEBUG_REG32[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG33", REG_SMC, 0x0021, &ixVGT_DEBUG_REG33[0], sizeof(ixVGT_DEBUG_REG33)/sizeof(ixVGT_DEBUG_REG33[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG34", REG_SMC, 0x0022, &ixVGT_DEBUG_REG34[0], sizeof(ixVGT_DEBUG_REG34)/sizeof(ixVGT_DEBUG_REG34[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG35", REG_SMC, 0x0023, &ixVGT_DEBUG_REG35[0], sizeof(ixVGT_DEBUG_REG35)/sizeof(ixVGT_DEBUG_REG35[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG36", REG_SMC, 0x0024, NULL, 0, 0, 0 },
+	{ "ixSQ_WAVE_TBA_LO", REG_SMC, 0x026C, &ixSQ_WAVE_TBA_LO[0], sizeof(ixSQ_WAVE_TBA_LO)/sizeof(ixSQ_WAVE_TBA_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_TBA_HI", REG_SMC, 0x026D, &ixSQ_WAVE_TBA_HI[0], sizeof(ixSQ_WAVE_TBA_HI)/sizeof(ixSQ_WAVE_TBA_HI[0]), 0, 0 },
+	{ "ixSQ_WAVE_TMA_LO", REG_SMC, 0x026E, &ixSQ_WAVE_TMA_LO[0], sizeof(ixSQ_WAVE_TMA_LO)/sizeof(ixSQ_WAVE_TMA_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_TMA_HI", REG_SMC, 0x026F, &ixSQ_WAVE_TMA_HI[0], sizeof(ixSQ_WAVE_TMA_HI)/sizeof(ixSQ_WAVE_TMA_HI[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP0", REG_SMC, 0x0270, &ixSQ_WAVE_TTMP0[0], sizeof(ixSQ_WAVE_TTMP0)/sizeof(ixSQ_WAVE_TTMP0[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP1", REG_SMC, 0x0271, &ixSQ_WAVE_TTMP1[0], sizeof(ixSQ_WAVE_TTMP1)/sizeof(ixSQ_WAVE_TTMP1[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP2", REG_SMC, 0x0272, &ixSQ_WAVE_TTMP2[0], sizeof(ixSQ_WAVE_TTMP2)/sizeof(ixSQ_WAVE_TTMP2[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP3", REG_SMC, 0x0273, &ixSQ_WAVE_TTMP3[0], sizeof(ixSQ_WAVE_TTMP3)/sizeof(ixSQ_WAVE_TTMP3[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP4", REG_SMC, 0x0274, &ixSQ_WAVE_TTMP4[0], sizeof(ixSQ_WAVE_TTMP4)/sizeof(ixSQ_WAVE_TTMP4[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP5", REG_SMC, 0x0275, &ixSQ_WAVE_TTMP5[0], sizeof(ixSQ_WAVE_TTMP5)/sizeof(ixSQ_WAVE_TTMP5[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP6", REG_SMC, 0x0276, &ixSQ_WAVE_TTMP6[0], sizeof(ixSQ_WAVE_TTMP6)/sizeof(ixSQ_WAVE_TTMP6[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP7", REG_SMC, 0x0277, &ixSQ_WAVE_TTMP7[0], sizeof(ixSQ_WAVE_TTMP7)/sizeof(ixSQ_WAVE_TTMP7[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP8", REG_SMC, 0x0278, &ixSQ_WAVE_TTMP8[0], sizeof(ixSQ_WAVE_TTMP8)/sizeof(ixSQ_WAVE_TTMP8[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP9", REG_SMC, 0x0279, &ixSQ_WAVE_TTMP9[0], sizeof(ixSQ_WAVE_TTMP9)/sizeof(ixSQ_WAVE_TTMP9[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP10", REG_SMC, 0x027A, &ixSQ_WAVE_TTMP10[0], sizeof(ixSQ_WAVE_TTMP10)/sizeof(ixSQ_WAVE_TTMP10[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP11", REG_SMC, 0x027B, &ixSQ_WAVE_TTMP11[0], sizeof(ixSQ_WAVE_TTMP11)/sizeof(ixSQ_WAVE_TTMP11[0]), 0, 0 },
+	{ "ixSQ_WAVE_M0", REG_SMC, 0x027C, &ixSQ_WAVE_M0[0], sizeof(ixSQ_WAVE_M0)/sizeof(ixSQ_WAVE_M0[0]), 0, 0 },
+	{ "ixSQ_WAVE_EXEC_LO", REG_SMC, 0x027E, &ixSQ_WAVE_EXEC_LO[0], sizeof(ixSQ_WAVE_EXEC_LO)/sizeof(ixSQ_WAVE_EXEC_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_EXEC_HI", REG_SMC, 0x027F, &ixSQ_WAVE_EXEC_HI[0], sizeof(ixSQ_WAVE_EXEC_HI)/sizeof(ixSQ_WAVE_EXEC_HI[0]), 0, 0 },
+	{ "mmGRBM_CNTL", REG_MMIO, 0x2000, &mmGRBM_CNTL[0], sizeof(mmGRBM_CNTL)/sizeof(mmGRBM_CNTL[0]), 0, 0 },
+	{ "mmGRBM_SKEW_CNTL", REG_MMIO, 0x2001, &mmGRBM_SKEW_CNTL[0], sizeof(mmGRBM_SKEW_CNTL)/sizeof(mmGRBM_SKEW_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS2", REG_MMIO, 0x2002, &mmGRBM_STATUS2[0], sizeof(mmGRBM_STATUS2)/sizeof(mmGRBM_STATUS2[0]), 0, 0 },
+	{ "mmGRBM_PWR_CNTL", REG_MMIO, 0x2003, &mmGRBM_PWR_CNTL[0], sizeof(mmGRBM_PWR_CNTL)/sizeof(mmGRBM_PWR_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS", REG_MMIO, 0x2004, &mmGRBM_STATUS[0], sizeof(mmGRBM_STATUS)/sizeof(mmGRBM_STATUS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE0", REG_MMIO, 0x2005, &mmGRBM_STATUS_SE0[0], sizeof(mmGRBM_STATUS_SE0)/sizeof(mmGRBM_STATUS_SE0[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE1", REG_MMIO, 0x2006, &mmGRBM_STATUS_SE1[0], sizeof(mmGRBM_STATUS_SE1)/sizeof(mmGRBM_STATUS_SE1[0]), 0, 0 },
+	{ "mmGRBM_SOFT_RESET", REG_MMIO, 0x2008, &mmGRBM_SOFT_RESET[0], sizeof(mmGRBM_SOFT_RESET)/sizeof(mmGRBM_SOFT_RESET[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_CNTL", REG_MMIO, 0x2009, &mmGRBM_DEBUG_CNTL[0], sizeof(mmGRBM_DEBUG_CNTL)/sizeof(mmGRBM_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_DATA", REG_MMIO, 0x200A, &mmGRBM_DEBUG_DATA[0], sizeof(mmGRBM_DEBUG_DATA)/sizeof(mmGRBM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_GFX_INDEX", REG_MMIO, 0x200B, &mmGRBM_GFX_INDEX[0], sizeof(mmGRBM_GFX_INDEX)/sizeof(mmGRBM_GFX_INDEX[0]), 0, 0 },
+	{ "mmGRBM_GFX_CLKEN_CNTL", REG_MMIO, 0x200C, &mmGRBM_GFX_CLKEN_CNTL[0], sizeof(mmGRBM_GFX_CLKEN_CNTL)/sizeof(mmGRBM_GFX_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmGRBM_WAIT_IDLE_CLOCKS", REG_MMIO, 0x200D, &mmGRBM_WAIT_IDLE_CLOCKS[0], sizeof(mmGRBM_WAIT_IDLE_CLOCKS)/sizeof(mmGRBM_WAIT_IDLE_CLOCKS[0]), 0, 0 },
+	{ "mmGRBM_DEBUG", REG_MMIO, 0x2014, &mmGRBM_DEBUG[0], sizeof(mmGRBM_DEBUG)/sizeof(mmGRBM_DEBUG[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x2015, &mmGRBM_DEBUG_SNAPSHOT[0], sizeof(mmGRBM_DEBUG_SNAPSHOT)/sizeof(mmGRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR", REG_MMIO, 0x2016, &mmGRBM_READ_ERROR[0], sizeof(mmGRBM_READ_ERROR)/sizeof(mmGRBM_READ_ERROR[0]), 0, 0 },
+	{ "mmGRBM_INT_CNTL", REG_MMIO, 0x2018, &mmGRBM_INT_CNTL[0], sizeof(mmGRBM_INT_CNTL)/sizeof(mmGRBM_INT_CNTL[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0x201C, &mmGRBM_PERFCOUNTER0_SELECT[0], sizeof(mmGRBM_PERFCOUNTER0_SELECT)/sizeof(mmGRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0x201D, &mmGRBM_PERFCOUNTER1_SELECT[0], sizeof(mmGRBM_PERFCOUNTER1_SELECT)/sizeof(mmGRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_LO", REG_MMIO, 0x201E, &mmGRBM_PERFCOUNTER0_LO[0], sizeof(mmGRBM_PERFCOUNTER0_LO)/sizeof(mmGRBM_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_HI", REG_MMIO, 0x201F, &mmGRBM_PERFCOUNTER0_HI[0], sizeof(mmGRBM_PERFCOUNTER0_HI)/sizeof(mmGRBM_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_LO", REG_MMIO, 0x2020, &mmGRBM_PERFCOUNTER1_LO[0], sizeof(mmGRBM_PERFCOUNTER1_LO)/sizeof(mmGRBM_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_HI", REG_MMIO, 0x2021, &mmGRBM_PERFCOUNTER1_HI[0], sizeof(mmGRBM_PERFCOUNTER1_HI)/sizeof(mmGRBM_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_SELECT", REG_MMIO, 0x2026, &mmGRBM_SE0_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_SELECT", REG_MMIO, 0x2027, &mmGRBM_SE1_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_LO", REG_MMIO, 0x202A, &mmGRBM_SE0_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE0_PERFCOUNTER_LO)/sizeof(mmGRBM_SE0_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_HI", REG_MMIO, 0x202B, &mmGRBM_SE0_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE0_PERFCOUNTER_HI)/sizeof(mmGRBM_SE0_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_LO", REG_MMIO, 0x202C, &mmGRBM_SE1_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE1_PERFCOUNTER_LO)/sizeof(mmGRBM_SE1_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_HI", REG_MMIO, 0x202D, &mmGRBM_SE1_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE1_PERFCOUNTER_HI)/sizeof(mmGRBM_SE1_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmDEBUG_INDEX", REG_MMIO, 0x203C, &mmDEBUG_INDEX[0], sizeof(mmDEBUG_INDEX)/sizeof(mmDEBUG_INDEX[0]), 0, 0 },
+	{ "mmDEBUG_DATA", REG_MMIO, 0x203D, &mmDEBUG_DATA[0], sizeof(mmDEBUG_DATA)/sizeof(mmDEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_NOWHERE", REG_MMIO, 0x203F, &mmGRBM_NOWHERE[0], sizeof(mmGRBM_NOWHERE)/sizeof(mmGRBM_NOWHERE[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG0", REG_MMIO, 0x2040, &mmGRBM_SCRATCH_REG0[0], sizeof(mmGRBM_SCRATCH_REG0)/sizeof(mmGRBM_SCRATCH_REG0[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG1", REG_MMIO, 0x2041, &mmGRBM_SCRATCH_REG1[0], sizeof(mmGRBM_SCRATCH_REG1)/sizeof(mmGRBM_SCRATCH_REG1[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG2", REG_MMIO, 0x2042, &mmGRBM_SCRATCH_REG2[0], sizeof(mmGRBM_SCRATCH_REG2)/sizeof(mmGRBM_SCRATCH_REG2[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG3", REG_MMIO, 0x2043, &mmGRBM_SCRATCH_REG3[0], sizeof(mmGRBM_SCRATCH_REG3)/sizeof(mmGRBM_SCRATCH_REG3[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG4", REG_MMIO, 0x2044, &mmGRBM_SCRATCH_REG4[0], sizeof(mmGRBM_SCRATCH_REG4)/sizeof(mmGRBM_SCRATCH_REG4[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG5", REG_MMIO, 0x2045, &mmGRBM_SCRATCH_REG5[0], sizeof(mmGRBM_SCRATCH_REG5)/sizeof(mmGRBM_SCRATCH_REG5[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG6", REG_MMIO, 0x2046, &mmGRBM_SCRATCH_REG6[0], sizeof(mmGRBM_SCRATCH_REG6)/sizeof(mmGRBM_SCRATCH_REG6[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG7", REG_MMIO, 0x2047, &mmGRBM_SCRATCH_REG7[0], sizeof(mmGRBM_SCRATCH_REG7)/sizeof(mmGRBM_SCRATCH_REG7[0]), 0, 0 },
+	{ "ixSQ_INTERRUPT_WORD_AUTO", REG_SMC, 0x20C0, &ixSQ_INTERRUPT_WORD_AUTO[0], sizeof(ixSQ_INTERRUPT_WORD_AUTO)/sizeof(ixSQ_INTERRUPT_WORD_AUTO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_LO", REG_MMIO, 0x2100, &mmCP_EOP_DONE_ADDR_LO[0], sizeof(mmCP_EOP_DONE_ADDR_LO)/sizeof(mmCP_EOP_DONE_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_HI", REG_MMIO, 0x2101, &mmCP_EOP_DONE_ADDR_HI[0], sizeof(mmCP_EOP_DONE_ADDR_HI)/sizeof(mmCP_EOP_DONE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_LO", REG_MMIO, 0x2102, &mmCP_EOP_DONE_DATA_LO[0], sizeof(mmCP_EOP_DONE_DATA_LO)/sizeof(mmCP_EOP_DONE_DATA_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_HI", REG_MMIO, 0x2103, &mmCP_EOP_DONE_DATA_HI[0], sizeof(mmCP_EOP_DONE_DATA_HI)/sizeof(mmCP_EOP_DONE_DATA_HI[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_LO", REG_MMIO, 0x2104, &mmCP_EOP_LAST_FENCE_LO[0], sizeof(mmCP_EOP_LAST_FENCE_LO)/sizeof(mmCP_EOP_LAST_FENCE_LO[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_HI", REG_MMIO, 0x2105, &mmCP_EOP_LAST_FENCE_HI[0], sizeof(mmCP_EOP_LAST_FENCE_HI)/sizeof(mmCP_EOP_LAST_FENCE_HI[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_LO", REG_MMIO, 0x2106, &mmCP_STREAM_OUT_ADDR_LO[0], sizeof(mmCP_STREAM_OUT_ADDR_LO)/sizeof(mmCP_STREAM_OUT_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_HI", REG_MMIO, 0x2107, &mmCP_STREAM_OUT_ADDR_HI[0], sizeof(mmCP_STREAM_OUT_ADDR_HI)/sizeof(mmCP_STREAM_OUT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_LO", REG_MMIO, 0x2108, &mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_HI", REG_MMIO, 0x2109, &mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_LO", REG_MMIO, 0x210A, &mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_HI", REG_MMIO, 0x210B, &mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_LO", REG_MMIO, 0x210C, &mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_HI", REG_MMIO, 0x210D, &mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_LO", REG_MMIO, 0x210E, &mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_HI", REG_MMIO, 0x210F, &mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_LO", REG_MMIO, 0x2110, &mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_HI", REG_MMIO, 0x2111, &mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_LO", REG_MMIO, 0x2112, &mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_HI", REG_MMIO, 0x2113, &mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_LO", REG_MMIO, 0x2114, &mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_HI", REG_MMIO, 0x2115, &mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_LO", REG_MMIO, 0x2116, &mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_HI", REG_MMIO, 0x2117, &mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_LO", REG_MMIO, 0x2118, &mmCP_PIPE_STATS_ADDR_LO[0], sizeof(mmCP_PIPE_STATS_ADDR_LO)/sizeof(mmCP_PIPE_STATS_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_HI", REG_MMIO, 0x2119, &mmCP_PIPE_STATS_ADDR_HI[0], sizeof(mmCP_PIPE_STATS_ADDR_HI)/sizeof(mmCP_PIPE_STATS_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_LO", REG_MMIO, 0x211A, &mmCP_VGT_IAVERT_COUNT_LO[0], sizeof(mmCP_VGT_IAVERT_COUNT_LO)/sizeof(mmCP_VGT_IAVERT_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_HI", REG_MMIO, 0x211B, &mmCP_VGT_IAVERT_COUNT_HI[0], sizeof(mmCP_VGT_IAVERT_COUNT_HI)/sizeof(mmCP_VGT_IAVERT_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_LO", REG_MMIO, 0x211C, &mmCP_VGT_IAPRIM_COUNT_LO[0], sizeof(mmCP_VGT_IAPRIM_COUNT_LO)/sizeof(mmCP_VGT_IAPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_HI", REG_MMIO, 0x211D, &mmCP_VGT_IAPRIM_COUNT_HI[0], sizeof(mmCP_VGT_IAPRIM_COUNT_HI)/sizeof(mmCP_VGT_IAPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_LO", REG_MMIO, 0x211E, &mmCP_VGT_GSPRIM_COUNT_LO[0], sizeof(mmCP_VGT_GSPRIM_COUNT_LO)/sizeof(mmCP_VGT_GSPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_HI", REG_MMIO, 0x211F, &mmCP_VGT_GSPRIM_COUNT_HI[0], sizeof(mmCP_VGT_GSPRIM_COUNT_HI)/sizeof(mmCP_VGT_GSPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_LO", REG_MMIO, 0x2120, &mmCP_VGT_VSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_VSINVOC_COUNT_LO)/sizeof(mmCP_VGT_VSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_HI", REG_MMIO, 0x2121, &mmCP_VGT_VSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_VSINVOC_COUNT_HI)/sizeof(mmCP_VGT_VSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_LO", REG_MMIO, 0x2122, &mmCP_VGT_GSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_GSINVOC_COUNT_LO)/sizeof(mmCP_VGT_GSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_HI", REG_MMIO, 0x2123, &mmCP_VGT_GSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_GSINVOC_COUNT_HI)/sizeof(mmCP_VGT_GSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_LO", REG_MMIO, 0x2124, &mmCP_VGT_HSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_HSINVOC_COUNT_LO)/sizeof(mmCP_VGT_HSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_HI", REG_MMIO, 0x2125, &mmCP_VGT_HSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_HSINVOC_COUNT_HI)/sizeof(mmCP_VGT_HSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_LO", REG_MMIO, 0x2126, &mmCP_VGT_DSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_DSINVOC_COUNT_LO)/sizeof(mmCP_VGT_DSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_HI", REG_MMIO, 0x2127, &mmCP_VGT_DSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_DSINVOC_COUNT_HI)/sizeof(mmCP_VGT_DSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_LO", REG_MMIO, 0x2128, &mmCP_PA_CINVOC_COUNT_LO[0], sizeof(mmCP_PA_CINVOC_COUNT_LO)/sizeof(mmCP_PA_CINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_HI", REG_MMIO, 0x2129, &mmCP_PA_CINVOC_COUNT_HI[0], sizeof(mmCP_PA_CINVOC_COUNT_HI)/sizeof(mmCP_PA_CINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_LO", REG_MMIO, 0x212A, &mmCP_PA_CPRIM_COUNT_LO[0], sizeof(mmCP_PA_CPRIM_COUNT_LO)/sizeof(mmCP_PA_CPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_HI", REG_MMIO, 0x212B, &mmCP_PA_CPRIM_COUNT_HI[0], sizeof(mmCP_PA_CPRIM_COUNT_HI)/sizeof(mmCP_PA_CPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_LO", REG_MMIO, 0x212C, &mmCP_SC_PSINVOC_COUNT0_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT0_LO)/sizeof(mmCP_SC_PSINVOC_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_HI", REG_MMIO, 0x212D, &mmCP_SC_PSINVOC_COUNT0_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT0_HI)/sizeof(mmCP_SC_PSINVOC_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_LO", REG_MMIO, 0x212E, &mmCP_SC_PSINVOC_COUNT1_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT1_LO)/sizeof(mmCP_SC_PSINVOC_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_HI", REG_MMIO, 0x212F, &mmCP_SC_PSINVOC_COUNT1_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT1_HI)/sizeof(mmCP_SC_PSINVOC_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_LO", REG_MMIO, 0x2130, &mmCP_VGT_CSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_CSINVOC_COUNT_LO)/sizeof(mmCP_VGT_CSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_HI", REG_MMIO, 0x2131, &mmCP_VGT_CSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_CSINVOC_COUNT_HI)/sizeof(mmCP_VGT_CSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_STRMOUT_CNTL", REG_MMIO, 0x213F, &mmCP_STRMOUT_CNTL[0], sizeof(mmCP_STRMOUT_CNTL)/sizeof(mmCP_STRMOUT_CNTL[0]), 0, 0 },
+	{ "mmSCRATCH_REG0", REG_MMIO, 0x2140, &mmSCRATCH_REG0[0], sizeof(mmSCRATCH_REG0)/sizeof(mmSCRATCH_REG0[0]), 0, 0 },
+	{ "mmSCRATCH_REG1", REG_MMIO, 0x2141, &mmSCRATCH_REG1[0], sizeof(mmSCRATCH_REG1)/sizeof(mmSCRATCH_REG1[0]), 0, 0 },
+	{ "mmSCRATCH_REG2", REG_MMIO, 0x2142, &mmSCRATCH_REG2[0], sizeof(mmSCRATCH_REG2)/sizeof(mmSCRATCH_REG2[0]), 0, 0 },
+	{ "mmSCRATCH_REG3", REG_MMIO, 0x2143, &mmSCRATCH_REG3[0], sizeof(mmSCRATCH_REG3)/sizeof(mmSCRATCH_REG3[0]), 0, 0 },
+	{ "mmSCRATCH_REG4", REG_MMIO, 0x2144, &mmSCRATCH_REG4[0], sizeof(mmSCRATCH_REG4)/sizeof(mmSCRATCH_REG4[0]), 0, 0 },
+	{ "mmSCRATCH_REG5", REG_MMIO, 0x2145, &mmSCRATCH_REG5[0], sizeof(mmSCRATCH_REG5)/sizeof(mmSCRATCH_REG5[0]), 0, 0 },
+	{ "mmSCRATCH_REG6", REG_MMIO, 0x2146, &mmSCRATCH_REG6[0], sizeof(mmSCRATCH_REG6)/sizeof(mmSCRATCH_REG6[0]), 0, 0 },
+	{ "mmSCRATCH_REG7", REG_MMIO, 0x2147, &mmSCRATCH_REG7[0], sizeof(mmSCRATCH_REG7)/sizeof(mmSCRATCH_REG7[0]), 0, 0 },
+	{ "mmSCRATCH_UMSK", REG_MMIO, 0x2150, &mmSCRATCH_UMSK[0], sizeof(mmSCRATCH_UMSK)/sizeof(mmSCRATCH_UMSK[0]), 0, 0 },
+	{ "mmSCRATCH_ADDR", REG_MMIO, 0x2151, &mmSCRATCH_ADDR[0], sizeof(mmSCRATCH_ADDR)/sizeof(mmSCRATCH_ADDR[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_LO", REG_MMIO, 0x2158, &mmCP_APPEND_ADDR_LO[0], sizeof(mmCP_APPEND_ADDR_LO)/sizeof(mmCP_APPEND_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_HI", REG_MMIO, 0x2159, &mmCP_APPEND_ADDR_HI[0], sizeof(mmCP_APPEND_ADDR_HI)/sizeof(mmCP_APPEND_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_DATA", REG_MMIO, 0x215A, &mmCP_APPEND_DATA[0], sizeof(mmCP_APPEND_DATA)/sizeof(mmCP_APPEND_DATA[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_CS_FENCE", REG_MMIO, 0x215B, &mmCP_APPEND_LAST_CS_FENCE[0], sizeof(mmCP_APPEND_LAST_CS_FENCE)/sizeof(mmCP_APPEND_LAST_CS_FENCE[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_PS_FENCE", REG_MMIO, 0x215C, &mmCP_APPEND_LAST_PS_FENCE[0], sizeof(mmCP_APPEND_LAST_PS_FENCE)/sizeof(mmCP_APPEND_LAST_PS_FENCE[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_LO", REG_MMIO, 0x215D, &mmCP_ATOMIC_PREOP_LO[0], sizeof(mmCP_ATOMIC_PREOP_LO)/sizeof(mmCP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_HI", REG_MMIO, 0x215E, &mmCP_ATOMIC_PREOP_HI[0], sizeof(mmCP_ATOMIC_PREOP_HI)/sizeof(mmCP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0x215F, &mmCP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0x2160, &mmCP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0x2161, &mmCP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0x2162, &mmCP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_LO", REG_MMIO, 0x2169, &mmCP_ME_MC_WADDR_LO[0], sizeof(mmCP_ME_MC_WADDR_LO)/sizeof(mmCP_ME_MC_WADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_HI", REG_MMIO, 0x216A, &mmCP_ME_MC_WADDR_HI[0], sizeof(mmCP_ME_MC_WADDR_HI)/sizeof(mmCP_ME_MC_WADDR_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_LO", REG_MMIO, 0x216B, &mmCP_ME_MC_WDATA_LO[0], sizeof(mmCP_ME_MC_WDATA_LO)/sizeof(mmCP_ME_MC_WDATA_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_HI", REG_MMIO, 0x216C, &mmCP_ME_MC_WDATA_HI[0], sizeof(mmCP_ME_MC_WDATA_HI)/sizeof(mmCP_ME_MC_WDATA_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_LO", REG_MMIO, 0x216D, &mmCP_ME_MC_RADDR_LO[0], sizeof(mmCP_ME_MC_RADDR_LO)/sizeof(mmCP_ME_MC_RADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_HI", REG_MMIO, 0x216E, &mmCP_ME_MC_RADDR_HI[0], sizeof(mmCP_ME_MC_RADDR_HI)/sizeof(mmCP_ME_MC_RADDR_HI[0]), 0, 0 },
+	{ "mmCP_SEM_WAIT_TIMER", REG_MMIO, 0x216F, &mmCP_SEM_WAIT_TIMER[0], sizeof(mmCP_SEM_WAIT_TIMER)/sizeof(mmCP_SEM_WAIT_TIMER[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_LO", REG_MMIO, 0x2170, &mmCP_SIG_SEM_ADDR_LO[0], sizeof(mmCP_SIG_SEM_ADDR_LO)/sizeof(mmCP_SIG_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_HI", REG_MMIO, 0x2171, &mmCP_SIG_SEM_ADDR_HI[0], sizeof(mmCP_SIG_SEM_ADDR_HI)/sizeof(mmCP_SIG_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_SEM_INCOMPLETE_TIMER_CNTL", REG_MMIO, 0x2172, NULL, 0, 0, 0 },
+	{ "mmCP_WAIT_REG_MEM_TIMEOUT", REG_MMIO, 0x2174, &mmCP_WAIT_REG_MEM_TIMEOUT[0], sizeof(mmCP_WAIT_REG_MEM_TIMEOUT)/sizeof(mmCP_WAIT_REG_MEM_TIMEOUT[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_LO", REG_MMIO, 0x2175, &mmCP_WAIT_SEM_ADDR_LO[0], sizeof(mmCP_WAIT_SEM_ADDR_LO)/sizeof(mmCP_WAIT_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_HI", REG_MMIO, 0x2176, &mmCP_WAIT_SEM_ADDR_HI[0], sizeof(mmCP_WAIT_SEM_ADDR_HI)/sizeof(mmCP_WAIT_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_COHER_CNTL2", REG_MMIO, 0x217A, NULL, 0, 0, 0 },
+	{ "mmCP_COHER_START_DELAY", REG_MMIO, 0x217B, &mmCP_COHER_START_DELAY[0], sizeof(mmCP_COHER_START_DELAY)/sizeof(mmCP_COHER_START_DELAY[0]), 0, 0 },
+	{ "mmCP_COHER_CNTL", REG_MMIO, 0x217C, &mmCP_COHER_CNTL[0], sizeof(mmCP_COHER_CNTL)/sizeof(mmCP_COHER_CNTL[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE", REG_MMIO, 0x217D, &mmCP_COHER_SIZE[0], sizeof(mmCP_COHER_SIZE)/sizeof(mmCP_COHER_SIZE[0]), 0, 0 },
+	{ "mmCP_COHER_BASE", REG_MMIO, 0x217E, &mmCP_COHER_BASE[0], sizeof(mmCP_COHER_BASE)/sizeof(mmCP_COHER_BASE[0]), 0, 0 },
+	{ "mmCP_COHER_STATUS", REG_MMIO, 0x217F, &mmCP_COHER_STATUS[0], sizeof(mmCP_COHER_STATUS)/sizeof(mmCP_COHER_STATUS[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR", REG_MMIO, 0x2180, &mmCP_DMA_ME_SRC_ADDR[0], sizeof(mmCP_DMA_ME_SRC_ADDR)/sizeof(mmCP_DMA_ME_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR_HI", REG_MMIO, 0x2181, &mmCP_DMA_ME_SRC_ADDR_HI[0], sizeof(mmCP_DMA_ME_SRC_ADDR_HI)/sizeof(mmCP_DMA_ME_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR", REG_MMIO, 0x2182, &mmCP_DMA_ME_DST_ADDR[0], sizeof(mmCP_DMA_ME_DST_ADDR)/sizeof(mmCP_DMA_ME_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR_HI", REG_MMIO, 0x2183, &mmCP_DMA_ME_DST_ADDR_HI[0], sizeof(mmCP_DMA_ME_DST_ADDR_HI)/sizeof(mmCP_DMA_ME_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_COMMAND", REG_MMIO, 0x2184, &mmCP_DMA_ME_COMMAND[0], sizeof(mmCP_DMA_ME_COMMAND)/sizeof(mmCP_DMA_ME_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR", REG_MMIO, 0x2185, &mmCP_DMA_PFP_SRC_ADDR[0], sizeof(mmCP_DMA_PFP_SRC_ADDR)/sizeof(mmCP_DMA_PFP_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR_HI", REG_MMIO, 0x2186, &mmCP_DMA_PFP_SRC_ADDR_HI[0], sizeof(mmCP_DMA_PFP_SRC_ADDR_HI)/sizeof(mmCP_DMA_PFP_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR", REG_MMIO, 0x2187, &mmCP_DMA_PFP_DST_ADDR[0], sizeof(mmCP_DMA_PFP_DST_ADDR)/sizeof(mmCP_DMA_PFP_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR_HI", REG_MMIO, 0x2188, &mmCP_DMA_PFP_DST_ADDR_HI[0], sizeof(mmCP_DMA_PFP_DST_ADDR_HI)/sizeof(mmCP_DMA_PFP_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_COMMAND", REG_MMIO, 0x2189, &mmCP_DMA_PFP_COMMAND[0], sizeof(mmCP_DMA_PFP_COMMAND)/sizeof(mmCP_DMA_PFP_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_CNTL", REG_MMIO, 0x218A, &mmCP_DMA_CNTL[0], sizeof(mmCP_DMA_CNTL)/sizeof(mmCP_DMA_CNTL[0]), 0, 0 },
+	{ "mmCP_DMA_READ_TAGS", REG_MMIO, 0x218B, &mmCP_DMA_READ_TAGS[0], sizeof(mmCP_DMA_READ_TAGS)/sizeof(mmCP_DMA_READ_TAGS[0]), 0, 0 },
+	{ "mmCP_PFP_IB_CONTROL", REG_MMIO, 0x218D, &mmCP_PFP_IB_CONTROL[0], sizeof(mmCP_PFP_IB_CONTROL)/sizeof(mmCP_PFP_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_PFP_LOAD_CONTROL", REG_MMIO, 0x218E, &mmCP_PFP_LOAD_CONTROL[0], sizeof(mmCP_PFP_LOAD_CONTROL)/sizeof(mmCP_PFP_LOAD_CONTROL[0]), 0, 0 },
+	{ "mmCP_SCRATCH_INDEX", REG_MMIO, 0x218F, &mmCP_SCRATCH_INDEX[0], sizeof(mmCP_SCRATCH_INDEX)/sizeof(mmCP_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_SCRATCH_DATA", REG_MMIO, 0x2190, &mmCP_SCRATCH_DATA[0], sizeof(mmCP_SCRATCH_DATA)/sizeof(mmCP_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_RB_OFFSET", REG_MMIO, 0x2191, &mmCP_RB_OFFSET[0], sizeof(mmCP_RB_OFFSET)/sizeof(mmCP_RB_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_OFFSET", REG_MMIO, 0x2192, &mmCP_IB1_OFFSET[0], sizeof(mmCP_IB1_OFFSET)/sizeof(mmCP_IB1_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB2_OFFSET", REG_MMIO, 0x2193, &mmCP_IB2_OFFSET[0], sizeof(mmCP_IB2_OFFSET)/sizeof(mmCP_IB2_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_BEGIN", REG_MMIO, 0x2194, &mmCP_IB1_PREAMBLE_BEGIN[0], sizeof(mmCP_IB1_PREAMBLE_BEGIN)/sizeof(mmCP_IB1_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_END", REG_MMIO, 0x2195, &mmCP_IB1_PREAMBLE_END[0], sizeof(mmCP_IB1_PREAMBLE_END)/sizeof(mmCP_IB1_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_BEGIN", REG_MMIO, 0x2196, &mmCP_IB2_PREAMBLE_BEGIN[0], sizeof(mmCP_IB2_PREAMBLE_BEGIN)/sizeof(mmCP_IB2_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_END", REG_MMIO, 0x2197, &mmCP_IB2_PREAMBLE_END[0], sizeof(mmCP_IB2_PREAMBLE_END)/sizeof(mmCP_IB2_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT3", REG_MMIO, 0x219C, &mmCP_STALLED_STAT3[0], sizeof(mmCP_STALLED_STAT3)/sizeof(mmCP_STALLED_STAT3[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT1", REG_MMIO, 0x219D, &mmCP_STALLED_STAT1[0], sizeof(mmCP_STALLED_STAT1)/sizeof(mmCP_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT2", REG_MMIO, 0x219E, &mmCP_STALLED_STAT2[0], sizeof(mmCP_STALLED_STAT2)/sizeof(mmCP_STALLED_STAT2[0]), 0, 0 },
+	{ "mmCP_BUSY_STAT", REG_MMIO, 0x219F, &mmCP_BUSY_STAT[0], sizeof(mmCP_BUSY_STAT)/sizeof(mmCP_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_STAT", REG_MMIO, 0x21A0, &mmCP_STAT[0], sizeof(mmCP_STAT)/sizeof(mmCP_STAT[0]), 0, 0 },
+	{ "mmCP_ME_HEADER_DUMP", REG_MMIO, 0x21A1, &mmCP_ME_HEADER_DUMP[0], sizeof(mmCP_ME_HEADER_DUMP)/sizeof(mmCP_ME_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_PFP_HEADER_DUMP", REG_MMIO, 0x21A2, &mmCP_PFP_HEADER_DUMP[0], sizeof(mmCP_PFP_HEADER_DUMP)/sizeof(mmCP_PFP_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_GRBM_FREE_COUNT", REG_MMIO, 0x21A3, &mmCP_GRBM_FREE_COUNT[0], sizeof(mmCP_GRBM_FREE_COUNT)/sizeof(mmCP_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_HEADER_DUMP", REG_MMIO, 0x21A4, &mmCP_CE_HEADER_DUMP[0], sizeof(mmCP_CE_HEADER_DUMP)/sizeof(mmCP_CE_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_MC_PACK_DELAY_CNT", REG_MMIO, 0x21A7, &mmCP_MC_PACK_DELAY_CNT[0], sizeof(mmCP_MC_PACK_DELAY_CNT)/sizeof(mmCP_MC_PACK_DELAY_CNT[0]), 0, 0 },
+	{ "mmCP_CSF_STAT", REG_MMIO, 0x21B4, &mmCP_CSF_STAT[0], sizeof(mmCP_CSF_STAT)/sizeof(mmCP_CSF_STAT[0]), 0, 0 },
+	{ "mmCP_CSF_CNTL", REG_MMIO, 0x21B5, &mmCP_CSF_CNTL[0], sizeof(mmCP_CSF_CNTL)/sizeof(mmCP_CSF_CNTL[0]), 0, 0 },
+	{ "mmCP_ME_CNTL", REG_MMIO, 0x21B6, &mmCP_ME_CNTL[0], sizeof(mmCP_ME_CNTL)/sizeof(mmCP_ME_CNTL[0]), 0, 0 },
+	{ "mmCP_CNTX_STAT", REG_MMIO, 0x21B8, &mmCP_CNTX_STAT[0], sizeof(mmCP_CNTX_STAT)/sizeof(mmCP_CNTX_STAT[0]), 0, 0 },
+	{ "mmCP_ME_PREEMPTION", REG_MMIO, 0x21B9, &mmCP_ME_PREEMPTION[0], sizeof(mmCP_ME_PREEMPTION)/sizeof(mmCP_ME_PREEMPTION[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR", REG_MMIO, 0x21BE, &mmCP_RB2_RPTR[0], sizeof(mmCP_RB2_RPTR)/sizeof(mmCP_RB2_RPTR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR", REG_MMIO, 0x21BF, &mmCP_RB1_RPTR[0], sizeof(mmCP_RB1_RPTR)/sizeof(mmCP_RB1_RPTR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR", REG_MMIO, 0x21C0, &mmCP_RB0_RPTR[0], sizeof(mmCP_RB0_RPTR)/sizeof(mmCP_RB0_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_DELAY", REG_MMIO, 0x21C1, &mmCP_RB_WPTR_DELAY[0], sizeof(mmCP_RB_WPTR_DELAY)/sizeof(mmCP_RB_WPTR_DELAY[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_CNTL", REG_MMIO, 0x21C2, &mmCP_RB_WPTR_POLL_CNTL[0], sizeof(mmCP_RB_WPTR_POLL_CNTL)/sizeof(mmCP_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_LO", REG_MMIO, 0x21C3, &mmCP_CE_INIT_BASE_LO[0], sizeof(mmCP_CE_INIT_BASE_LO)/sizeof(mmCP_CE_INIT_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_HI", REG_MMIO, 0x21C4, &mmCP_CE_INIT_BASE_HI[0], sizeof(mmCP_CE_INIT_BASE_HI)/sizeof(mmCP_CE_INIT_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BUFSZ", REG_MMIO, 0x21C5, &mmCP_CE_INIT_BUFSZ[0], sizeof(mmCP_CE_INIT_BUFSZ)/sizeof(mmCP_CE_INIT_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_LO", REG_MMIO, 0x21C6, &mmCP_CE_IB1_BASE_LO[0], sizeof(mmCP_CE_IB1_BASE_LO)/sizeof(mmCP_CE_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_HI", REG_MMIO, 0x21C7, &mmCP_CE_IB1_BASE_HI[0], sizeof(mmCP_CE_IB1_BASE_HI)/sizeof(mmCP_CE_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BUFSZ", REG_MMIO, 0x21C8, &mmCP_CE_IB1_BUFSZ[0], sizeof(mmCP_CE_IB1_BUFSZ)/sizeof(mmCP_CE_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_LO", REG_MMIO, 0x21C9, &mmCP_CE_IB2_BASE_LO[0], sizeof(mmCP_CE_IB2_BASE_LO)/sizeof(mmCP_CE_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_HI", REG_MMIO, 0x21CA, &mmCP_CE_IB2_BASE_HI[0], sizeof(mmCP_CE_IB2_BASE_HI)/sizeof(mmCP_CE_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BUFSZ", REG_MMIO, 0x21CB, &mmCP_CE_IB2_BUFSZ[0], sizeof(mmCP_CE_IB2_BUFSZ)/sizeof(mmCP_CE_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_LO", REG_MMIO, 0x21CC, &mmCP_IB1_BASE_LO[0], sizeof(mmCP_IB1_BASE_LO)/sizeof(mmCP_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_HI", REG_MMIO, 0x21CD, &mmCP_IB1_BASE_HI[0], sizeof(mmCP_IB1_BASE_HI)/sizeof(mmCP_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB1_BUFSZ", REG_MMIO, 0x21CE, &mmCP_IB1_BUFSZ[0], sizeof(mmCP_IB1_BUFSZ)/sizeof(mmCP_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_LO", REG_MMIO, 0x21CF, &mmCP_IB2_BASE_LO[0], sizeof(mmCP_IB2_BASE_LO)/sizeof(mmCP_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_HI", REG_MMIO, 0x21D0, &mmCP_IB2_BASE_HI[0], sizeof(mmCP_IB2_BASE_HI)/sizeof(mmCP_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB2_BUFSZ", REG_MMIO, 0x21D1, &mmCP_IB2_BUFSZ[0], sizeof(mmCP_IB2_BUFSZ)/sizeof(mmCP_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_ST_BASE_LO", REG_MMIO, 0x21D2, &mmCP_ST_BASE_LO[0], sizeof(mmCP_ST_BASE_LO)/sizeof(mmCP_ST_BASE_LO[0]), 0, 0 },
+	{ "mmCP_ST_BASE_HI", REG_MMIO, 0x21D3, &mmCP_ST_BASE_HI[0], sizeof(mmCP_ST_BASE_HI)/sizeof(mmCP_ST_BASE_HI[0]), 0, 0 },
+	{ "mmCP_ST_BUFSZ", REG_MMIO, 0x21D4, &mmCP_ST_BUFSZ[0], sizeof(mmCP_ST_BUFSZ)/sizeof(mmCP_ST_BUFSZ[0]), 0, 0 },
+	{ "mmCP_ROQ1_THRESHOLDS", REG_MMIO, 0x21D5, &mmCP_ROQ1_THRESHOLDS[0], sizeof(mmCP_ROQ1_THRESHOLDS)/sizeof(mmCP_ROQ1_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ2_THRESHOLDS", REG_MMIO, 0x21D6, &mmCP_ROQ2_THRESHOLDS[0], sizeof(mmCP_ROQ2_THRESHOLDS)/sizeof(mmCP_ROQ2_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_STQ_THRESHOLDS", REG_MMIO, 0x21D7, &mmCP_STQ_THRESHOLDS[0], sizeof(mmCP_STQ_THRESHOLDS)/sizeof(mmCP_STQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_QUEUE_THRESHOLDS", REG_MMIO, 0x21D8, &mmCP_QUEUE_THRESHOLDS[0], sizeof(mmCP_QUEUE_THRESHOLDS)/sizeof(mmCP_QUEUE_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_THRESHOLDS", REG_MMIO, 0x21D9, &mmCP_MEQ_THRESHOLDS[0], sizeof(mmCP_MEQ_THRESHOLDS)/sizeof(mmCP_MEQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ_AVAIL", REG_MMIO, 0x21DA, &mmCP_ROQ_AVAIL[0], sizeof(mmCP_ROQ_AVAIL)/sizeof(mmCP_ROQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_STQ_AVAIL", REG_MMIO, 0x21DB, &mmCP_STQ_AVAIL[0], sizeof(mmCP_STQ_AVAIL)/sizeof(mmCP_STQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_ROQ2_AVAIL", REG_MMIO, 0x21DC, &mmCP_ROQ2_AVAIL[0], sizeof(mmCP_ROQ2_AVAIL)/sizeof(mmCP_ROQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_MEQ_AVAIL", REG_MMIO, 0x21DD, &mmCP_MEQ_AVAIL[0], sizeof(mmCP_MEQ_AVAIL)/sizeof(mmCP_MEQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_CMD_INDEX", REG_MMIO, 0x21DE, &mmCP_CMD_INDEX[0], sizeof(mmCP_CMD_INDEX)/sizeof(mmCP_CMD_INDEX[0]), 0, 0 },
+	{ "mmCP_CMD_DATA", REG_MMIO, 0x21DF, &mmCP_CMD_DATA[0], sizeof(mmCP_CMD_DATA)/sizeof(mmCP_CMD_DATA[0]), 0, 0 },
+	{ "mmCP_ROQ_RB_STAT", REG_MMIO, 0x21E0, &mmCP_ROQ_RB_STAT[0], sizeof(mmCP_ROQ_RB_STAT)/sizeof(mmCP_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB1_STAT", REG_MMIO, 0x21E1, &mmCP_ROQ_IB1_STAT[0], sizeof(mmCP_ROQ_IB1_STAT)/sizeof(mmCP_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB2_STAT", REG_MMIO, 0x21E2, &mmCP_ROQ_IB2_STAT[0], sizeof(mmCP_ROQ_IB2_STAT)/sizeof(mmCP_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_STAT", REG_MMIO, 0x21E3, &mmCP_STQ_STAT[0], sizeof(mmCP_STQ_STAT)/sizeof(mmCP_STQ_STAT[0]), 0, 0 },
+	{ "mmCP_MEQ_STAT", REG_MMIO, 0x21E5, &mmCP_MEQ_STAT[0], sizeof(mmCP_MEQ_STAT)/sizeof(mmCP_MEQ_STAT[0]), 0, 0 },
+	{ "mmCP_CEQ1_AVAIL", REG_MMIO, 0x21E6, &mmCP_CEQ1_AVAIL[0], sizeof(mmCP_CEQ1_AVAIL)/sizeof(mmCP_CEQ1_AVAIL[0]), 0, 0 },
+	{ "mmCP_CEQ2_AVAIL", REG_MMIO, 0x21E7, &mmCP_CEQ2_AVAIL[0], sizeof(mmCP_CEQ2_AVAIL)/sizeof(mmCP_CEQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_RB_STAT", REG_MMIO, 0x21E8, &mmCP_CE_ROQ_RB_STAT[0], sizeof(mmCP_CE_ROQ_RB_STAT)/sizeof(mmCP_CE_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB1_STAT", REG_MMIO, 0x21E9, &mmCP_CE_ROQ_IB1_STAT[0], sizeof(mmCP_CE_ROQ_IB1_STAT)/sizeof(mmCP_CE_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB2_STAT", REG_MMIO, 0x21EA, &mmCP_CE_ROQ_IB2_STAT[0], sizeof(mmCP_CE_ROQ_IB2_STAT)/sizeof(mmCP_CE_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_INT_STAT_DEBUG", REG_MMIO, 0x21F7, &mmCP_INT_STAT_DEBUG[0], sizeof(mmCP_INT_STAT_DEBUG)/sizeof(mmCP_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTL", REG_MMIO, 0x21FF, &mmCP_PERFMON_CNTL[0], sizeof(mmCP_PERFMON_CNTL)/sizeof(mmCP_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT", REG_MMIO, 0x2220, &mmIA_PERFCOUNTER0_SELECT[0], sizeof(mmIA_PERFCOUNTER0_SELECT)/sizeof(mmIA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_SELECT", REG_MMIO, 0x2221, &mmIA_PERFCOUNTER1_SELECT[0], sizeof(mmIA_PERFCOUNTER1_SELECT)/sizeof(mmIA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_SELECT", REG_MMIO, 0x2222, &mmIA_PERFCOUNTER2_SELECT[0], sizeof(mmIA_PERFCOUNTER2_SELECT)/sizeof(mmIA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_SELECT", REG_MMIO, 0x2223, &mmIA_PERFCOUNTER3_SELECT[0], sizeof(mmIA_PERFCOUNTER3_SELECT)/sizeof(mmIA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_LO", REG_MMIO, 0x2224, &mmIA_PERFCOUNTER0_LO[0], sizeof(mmIA_PERFCOUNTER0_LO)/sizeof(mmIA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_HI", REG_MMIO, 0x2225, &mmIA_PERFCOUNTER0_HI[0], sizeof(mmIA_PERFCOUNTER0_HI)/sizeof(mmIA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_LO", REG_MMIO, 0x2226, &mmIA_PERFCOUNTER1_LO[0], sizeof(mmIA_PERFCOUNTER1_LO)/sizeof(mmIA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_HI", REG_MMIO, 0x2227, &mmIA_PERFCOUNTER1_HI[0], sizeof(mmIA_PERFCOUNTER1_HI)/sizeof(mmIA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_LO", REG_MMIO, 0x2228, &mmIA_PERFCOUNTER2_LO[0], sizeof(mmIA_PERFCOUNTER2_LO)/sizeof(mmIA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_HI", REG_MMIO, 0x2229, &mmIA_PERFCOUNTER2_HI[0], sizeof(mmIA_PERFCOUNTER2_HI)/sizeof(mmIA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_LO", REG_MMIO, 0x222A, &mmIA_PERFCOUNTER3_LO[0], sizeof(mmIA_PERFCOUNTER3_LO)/sizeof(mmIA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_HI", REG_MMIO, 0x222B, &mmIA_PERFCOUNTER3_HI[0], sizeof(mmIA_PERFCOUNTER3_HI)/sizeof(mmIA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmVGT_VTX_VECT_EJECT_REG", REG_MMIO, 0x222C, &mmVGT_VTX_VECT_EJECT_REG[0], sizeof(mmVGT_VTX_VECT_EJECT_REG)/sizeof(mmVGT_VTX_VECT_EJECT_REG[0]), 0, 0 },
+	{ "mmVGT_DMA_DATA_FIFO_DEPTH", REG_MMIO, 0x222D, &mmVGT_DMA_DATA_FIFO_DEPTH[0], sizeof(mmVGT_DMA_DATA_FIFO_DEPTH)/sizeof(mmVGT_DMA_DATA_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DMA_REQ_FIFO_DEPTH", REG_MMIO, 0x222E, &mmVGT_DMA_REQ_FIFO_DEPTH[0], sizeof(mmVGT_DMA_REQ_FIFO_DEPTH)/sizeof(mmVGT_DMA_REQ_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DRAW_INIT_FIFO_DEPTH", REG_MMIO, 0x222F, &mmVGT_DRAW_INIT_FIFO_DEPTH[0], sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH)/sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_LAST_COPY_STATE", REG_MMIO, 0x2230, &mmVGT_LAST_COPY_STATE[0], sizeof(mmVGT_LAST_COPY_STATE)/sizeof(mmVGT_LAST_COPY_STATE[0]), 0, 0 },
+	{ "mmVGT_CACHE_INVALIDATION", REG_MMIO, 0x2231, &mmVGT_CACHE_INVALIDATION[0], sizeof(mmVGT_CACHE_INVALIDATION)/sizeof(mmVGT_CACHE_INVALIDATION[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_SIZE", REG_MMIO, 0x2232, &mmVGT_ESGS_RING_SIZE[0], sizeof(mmVGT_ESGS_RING_SIZE)/sizeof(mmVGT_ESGS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_SIZE", REG_MMIO, 0x2233, &mmVGT_GSVS_RING_SIZE[0], sizeof(mmVGT_GSVS_RING_SIZE)/sizeof(mmVGT_GSVS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_FIFO_DEPTHS", REG_MMIO, 0x2234, &mmVGT_FIFO_DEPTHS[0], sizeof(mmVGT_FIFO_DEPTHS)/sizeof(mmVGT_FIFO_DEPTHS[0]), 0, 0 },
+	{ "mmVGT_GS_VERTEX_REUSE", REG_MMIO, 0x2235, &mmVGT_GS_VERTEX_REUSE[0], sizeof(mmVGT_GS_VERTEX_REUSE)/sizeof(mmVGT_GS_VERTEX_REUSE[0]), 0, 0 },
+	{ "mmVGT_MC_LAT_CNTL", REG_MMIO, 0x2236, &mmVGT_MC_LAT_CNTL[0], sizeof(mmVGT_MC_LAT_CNTL)/sizeof(mmVGT_MC_LAT_CNTL[0]), 0, 0 },
+	{ "mmIA_CNTL_STATUS", REG_MMIO, 0x2237, &mmIA_CNTL_STATUS[0], sizeof(mmIA_CNTL_STATUS)/sizeof(mmIA_CNTL_STATUS[0]), 0, 0 },
+	{ "mmVGT_DEBUG_CNTL", REG_MMIO, 0x2238, &mmVGT_DEBUG_CNTL[0], sizeof(mmVGT_DEBUG_CNTL)/sizeof(mmVGT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmVGT_DEBUG_DATA", REG_MMIO, 0x2239, &mmVGT_DEBUG_DATA[0], sizeof(mmVGT_DEBUG_DATA)/sizeof(mmVGT_DEBUG_DATA[0]), 0, 0 },
+	{ "mmIA_DEBUG_CNTL", REG_MMIO, 0x223A, &mmIA_DEBUG_CNTL[0], sizeof(mmIA_DEBUG_CNTL)/sizeof(mmIA_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmIA_DEBUG_DATA", REG_MMIO, 0x223B, &mmIA_DEBUG_DATA[0], sizeof(mmIA_DEBUG_DATA)/sizeof(mmIA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGT_CNTL_STATUS", REG_MMIO, 0x223C, &mmVGT_CNTL_STATUS[0], sizeof(mmVGT_CNTL_STATUS)/sizeof(mmVGT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER_SEID_MASK", REG_MMIO, 0x2247, &mmVGT_PERFCOUNTER_SEID_MASK[0], sizeof(mmVGT_PERFCOUNTER_SEID_MASK)/sizeof(mmVGT_PERFCOUNTER_SEID_MASK[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT", REG_MMIO, 0x2248, &mmVGT_PERFCOUNTER0_SELECT[0], sizeof(mmVGT_PERFCOUNTER0_SELECT)/sizeof(mmVGT_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT", REG_MMIO, 0x2249, &mmVGT_PERFCOUNTER1_SELECT[0], sizeof(mmVGT_PERFCOUNTER1_SELECT)/sizeof(mmVGT_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_SELECT", REG_MMIO, 0x224A, &mmVGT_PERFCOUNTER2_SELECT[0], sizeof(mmVGT_PERFCOUNTER2_SELECT)/sizeof(mmVGT_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_SELECT", REG_MMIO, 0x224B, &mmVGT_PERFCOUNTER3_SELECT[0], sizeof(mmVGT_PERFCOUNTER3_SELECT)/sizeof(mmVGT_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_LO", REG_MMIO, 0x224C, &mmVGT_PERFCOUNTER0_LO[0], sizeof(mmVGT_PERFCOUNTER0_LO)/sizeof(mmVGT_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_HI", REG_MMIO, 0x224D, &mmVGT_PERFCOUNTER0_HI[0], sizeof(mmVGT_PERFCOUNTER0_HI)/sizeof(mmVGT_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_LO", REG_MMIO, 0x224E, &mmVGT_PERFCOUNTER1_LO[0], sizeof(mmVGT_PERFCOUNTER1_LO)/sizeof(mmVGT_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_HI", REG_MMIO, 0x224F, &mmVGT_PERFCOUNTER1_HI[0], sizeof(mmVGT_PERFCOUNTER1_HI)/sizeof(mmVGT_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_LO", REG_MMIO, 0x2250, &mmVGT_PERFCOUNTER2_LO[0], sizeof(mmVGT_PERFCOUNTER2_LO)/sizeof(mmVGT_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_HI", REG_MMIO, 0x2251, &mmVGT_PERFCOUNTER2_HI[0], sizeof(mmVGT_PERFCOUNTER2_HI)/sizeof(mmVGT_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_LO", REG_MMIO, 0x2252, &mmVGT_PERFCOUNTER3_LO[0], sizeof(mmVGT_PERFCOUNTER3_LO)/sizeof(mmVGT_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_HI", REG_MMIO, 0x2253, &mmVGT_PERFCOUNTER3_HI[0], sizeof(mmVGT_PERFCOUNTER3_HI)/sizeof(mmVGT_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVE_TYPE", REG_MMIO, 0x2256, &mmVGT_PRIMITIVE_TYPE[0], sizeof(mmVGT_PRIMITIVE_TYPE)/sizeof(mmVGT_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_INDEX_TYPE", REG_MMIO, 0x2257, &mmVGT_INDEX_TYPE[0], sizeof(mmVGT_INDEX_TYPE)/sizeof(mmVGT_INDEX_TYPE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0", REG_MMIO, 0x2258, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1", REG_MMIO, 0x2259, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2", REG_MMIO, 0x225A, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3", REG_MMIO, 0x225B, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_NUM_INDICES", REG_MMIO, 0x225C, &mmVGT_NUM_INDICES[0], sizeof(mmVGT_NUM_INDICES)/sizeof(mmVGT_NUM_INDICES[0]), 0, 0 },
+	{ "mmVGT_NUM_INSTANCES", REG_MMIO, 0x225D, &mmVGT_NUM_INSTANCES[0], sizeof(mmVGT_NUM_INSTANCES)/sizeof(mmVGT_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmCGTT_VGT_CLK_CTRL", REG_MMIO, 0x225F, &mmCGTT_VGT_CLK_CTRL[0], sizeof(mmCGTT_VGT_CLK_CTRL)/sizeof(mmCGTT_VGT_CLK_CTRL[0]), 0, 0 },
+	{ "mmIA_VMID_OVERRIDE", REG_MMIO, 0x2260, &mmIA_VMID_OVERRIDE[0], sizeof(mmIA_VMID_OVERRIDE)/sizeof(mmIA_VMID_OVERRIDE[0]), 0, 0 },
+	{ "mmCGTT_IA_CLK_CTRL", REG_MMIO, 0x2261, &mmCGTT_IA_CLK_CTRL[0], sizeof(mmCGTT_IA_CLK_CTRL)/sizeof(mmCGTT_IA_CLK_CTRL[0]), 0, 0 },
+	{ "mmVGT_TF_RING_SIZE", REG_MMIO, 0x2262, &mmVGT_TF_RING_SIZE[0], sizeof(mmVGT_TF_RING_SIZE)/sizeof(mmVGT_TF_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_SYS_CONFIG", REG_MMIO, 0x2263, &mmVGT_SYS_CONFIG[0], sizeof(mmVGT_SYS_CONFIG)/sizeof(mmVGT_SYS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_HS_OFFCHIP_PARAM", REG_MMIO, 0x226C, &mmVGT_HS_OFFCHIP_PARAM[0], sizeof(mmVGT_HS_OFFCHIP_PARAM)/sizeof(mmVGT_HS_OFFCHIP_PARAM[0]), 0, 0 },
+	{ "mmVGT_TF_MEMORY_BASE", REG_MMIO, 0x226E, &mmVGT_TF_MEMORY_BASE[0], sizeof(mmVGT_TF_MEMORY_BASE)/sizeof(mmVGT_TF_MEMORY_BASE[0]), 0, 0 },
+	{ "mmCC_GC_SHADER_ARRAY_CONFIG", REG_MMIO, 0x226F, &mmCC_GC_SHADER_ARRAY_CONFIG[0], sizeof(mmCC_GC_SHADER_ARRAY_CONFIG)/sizeof(mmCC_GC_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_SHADER_ARRAY_CONFIG", REG_MMIO, 0x2270, &mmGC_USER_SHADER_ARRAY_CONFIG[0], sizeof(mmGC_USER_SHADER_ARRAY_CONFIG)/sizeof(mmGC_USER_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_CNTL", REG_MMIO, 0x2280, &mmPA_SU_DEBUG_CNTL[0], sizeof(mmPA_SU_DEBUG_CNTL)/sizeof(mmPA_SU_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_DATA", REG_MMIO, 0x2281, &mmPA_SU_DEBUG_DATA[0], sizeof(mmPA_SU_DEBUG_DATA)/sizeof(mmPA_SU_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_CL_CNTL_STATUS", REG_MMIO, 0x2284, &mmPA_CL_CNTL_STATUS[0], sizeof(mmPA_CL_CNTL_STATUS)/sizeof(mmPA_CL_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_CL_ENHANCE", REG_MMIO, 0x2285, &mmPA_CL_ENHANCE[0], sizeof(mmPA_CL_ENHANCE)/sizeof(mmPA_CL_ENHANCE[0]), 0, 0 },
+	{ "mmCGTT_PA_CLK_CTRL", REG_MMIO, 0x2286, &mmCGTT_PA_CLK_CTRL[0], sizeof(mmCGTT_PA_CLK_CTRL)/sizeof(mmCGTT_PA_CLK_CTRL[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT", REG_MMIO, 0x2288, &mmPA_SU_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT", REG_MMIO, 0x2289, &mmPA_SU_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_SELECT", REG_MMIO, 0x228A, &mmPA_SU_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER2_SELECT)/sizeof(mmPA_SU_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_SELECT", REG_MMIO, 0x228B, &mmPA_SU_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER3_SELECT)/sizeof(mmPA_SU_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_LO", REG_MMIO, 0x228C, &mmPA_SU_PERFCOUNTER0_LO[0], sizeof(mmPA_SU_PERFCOUNTER0_LO)/sizeof(mmPA_SU_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_HI", REG_MMIO, 0x228D, &mmPA_SU_PERFCOUNTER0_HI[0], sizeof(mmPA_SU_PERFCOUNTER0_HI)/sizeof(mmPA_SU_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_LO", REG_MMIO, 0x228E, &mmPA_SU_PERFCOUNTER1_LO[0], sizeof(mmPA_SU_PERFCOUNTER1_LO)/sizeof(mmPA_SU_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_HI", REG_MMIO, 0x228F, &mmPA_SU_PERFCOUNTER1_HI[0], sizeof(mmPA_SU_PERFCOUNTER1_HI)/sizeof(mmPA_SU_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_LO", REG_MMIO, 0x2290, &mmPA_SU_PERFCOUNTER2_LO[0], sizeof(mmPA_SU_PERFCOUNTER2_LO)/sizeof(mmPA_SU_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_HI", REG_MMIO, 0x2291, &mmPA_SU_PERFCOUNTER2_HI[0], sizeof(mmPA_SU_PERFCOUNTER2_HI)/sizeof(mmPA_SU_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_LO", REG_MMIO, 0x2292, &mmPA_SU_PERFCOUNTER3_LO[0], sizeof(mmPA_SU_PERFCOUNTER3_LO)/sizeof(mmPA_SU_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_HI", REG_MMIO, 0x2293, &mmPA_SU_PERFCOUNTER3_HI[0], sizeof(mmPA_SU_PERFCOUNTER3_HI)/sizeof(mmPA_SU_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SU_CNTL_STATUS", REG_MMIO, 0x2294, &mmPA_SU_CNTL_STATUS[0], sizeof(mmPA_SU_CNTL_STATUS)/sizeof(mmPA_SU_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_DEPTH_CNTL", REG_MMIO, 0x2295, &mmPA_SC_FIFO_DEPTH_CNTL[0], sizeof(mmPA_SC_FIFO_DEPTH_CNTL)/sizeof(mmPA_SC_FIFO_DEPTH_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_VALUE", REG_MMIO, 0x2298, &mmPA_SU_LINE_STIPPLE_VALUE[0], sizeof(mmPA_SU_LINE_STIPPLE_VALUE)/sizeof(mmPA_SU_LINE_STIPPLE_VALUE[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT", REG_MMIO, 0x22A0, &mmPA_SC_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_SELECT", REG_MMIO, 0x22A1, &mmPA_SC_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER1_SELECT)/sizeof(mmPA_SC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_SELECT", REG_MMIO, 0x22A2, &mmPA_SC_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER2_SELECT)/sizeof(mmPA_SC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_SELECT", REG_MMIO, 0x22A3, &mmPA_SC_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER3_SELECT)/sizeof(mmPA_SC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_SELECT", REG_MMIO, 0x22A4, &mmPA_SC_PERFCOUNTER4_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER4_SELECT)/sizeof(mmPA_SC_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_SELECT", REG_MMIO, 0x22A5, &mmPA_SC_PERFCOUNTER5_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER5_SELECT)/sizeof(mmPA_SC_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_SELECT", REG_MMIO, 0x22A6, &mmPA_SC_PERFCOUNTER6_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER6_SELECT)/sizeof(mmPA_SC_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_SELECT", REG_MMIO, 0x22A7, &mmPA_SC_PERFCOUNTER7_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER7_SELECT)/sizeof(mmPA_SC_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_LO", REG_MMIO, 0x22A8, &mmPA_SC_PERFCOUNTER0_LO[0], sizeof(mmPA_SC_PERFCOUNTER0_LO)/sizeof(mmPA_SC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_HI", REG_MMIO, 0x22A9, &mmPA_SC_PERFCOUNTER0_HI[0], sizeof(mmPA_SC_PERFCOUNTER0_HI)/sizeof(mmPA_SC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_LO", REG_MMIO, 0x22AA, &mmPA_SC_PERFCOUNTER1_LO[0], sizeof(mmPA_SC_PERFCOUNTER1_LO)/sizeof(mmPA_SC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_HI", REG_MMIO, 0x22AB, &mmPA_SC_PERFCOUNTER1_HI[0], sizeof(mmPA_SC_PERFCOUNTER1_HI)/sizeof(mmPA_SC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_LO", REG_MMIO, 0x22AC, &mmPA_SC_PERFCOUNTER2_LO[0], sizeof(mmPA_SC_PERFCOUNTER2_LO)/sizeof(mmPA_SC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_HI", REG_MMIO, 0x22AD, &mmPA_SC_PERFCOUNTER2_HI[0], sizeof(mmPA_SC_PERFCOUNTER2_HI)/sizeof(mmPA_SC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_LO", REG_MMIO, 0x22AE, &mmPA_SC_PERFCOUNTER3_LO[0], sizeof(mmPA_SC_PERFCOUNTER3_LO)/sizeof(mmPA_SC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_HI", REG_MMIO, 0x22AF, &mmPA_SC_PERFCOUNTER3_HI[0], sizeof(mmPA_SC_PERFCOUNTER3_HI)/sizeof(mmPA_SC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_LO", REG_MMIO, 0x22B0, &mmPA_SC_PERFCOUNTER4_LO[0], sizeof(mmPA_SC_PERFCOUNTER4_LO)/sizeof(mmPA_SC_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_HI", REG_MMIO, 0x22B1, &mmPA_SC_PERFCOUNTER4_HI[0], sizeof(mmPA_SC_PERFCOUNTER4_HI)/sizeof(mmPA_SC_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_LO", REG_MMIO, 0x22B2, &mmPA_SC_PERFCOUNTER5_LO[0], sizeof(mmPA_SC_PERFCOUNTER5_LO)/sizeof(mmPA_SC_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_HI", REG_MMIO, 0x22B3, &mmPA_SC_PERFCOUNTER5_HI[0], sizeof(mmPA_SC_PERFCOUNTER5_HI)/sizeof(mmPA_SC_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_LO", REG_MMIO, 0x22B4, &mmPA_SC_PERFCOUNTER6_LO[0], sizeof(mmPA_SC_PERFCOUNTER6_LO)/sizeof(mmPA_SC_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_HI", REG_MMIO, 0x22B5, &mmPA_SC_PERFCOUNTER6_HI[0], sizeof(mmPA_SC_PERFCOUNTER6_HI)/sizeof(mmPA_SC_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_LO", REG_MMIO, 0x22B6, &mmPA_SC_PERFCOUNTER7_LO[0], sizeof(mmPA_SC_PERFCOUNTER7_LO)/sizeof(mmPA_SC_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_HI", REG_MMIO, 0x22B7, &mmPA_SC_PERFCOUNTER7_HI[0], sizeof(mmPA_SC_PERFCOUNTER7_HI)/sizeof(mmPA_SC_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE_STATE", REG_MMIO, 0x22C4, &mmPA_SC_LINE_STIPPLE_STATE[0], sizeof(mmPA_SC_LINE_STIPPLE_STATE)/sizeof(mmPA_SC_LINE_STIPPLE_STATE[0]), 0, 0 },
+	{ "mmPA_SC_FORCE_EOV_MAX_CNTS", REG_MMIO, 0x22C9, &mmPA_SC_FORCE_EOV_MAX_CNTS[0], sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS)/sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS[0]), 0, 0 },
+	{ "mmCGTT_SC_CLK_CTRL", REG_MMIO, 0x22CA, &mmCGTT_SC_CLK_CTRL[0], sizeof(mmCGTT_SC_CLK_CTRL)/sizeof(mmCGTT_SC_CLK_CTRL[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_SIZE", REG_MMIO, 0x22F3, &mmPA_SC_FIFO_SIZE[0], sizeof(mmPA_SC_FIFO_SIZE)/sizeof(mmPA_SC_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_IF_FIFO_SIZE", REG_MMIO, 0x22F5, &mmPA_SC_IF_FIFO_SIZE[0], sizeof(mmPA_SC_IF_FIFO_SIZE)/sizeof(mmPA_SC_IF_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_CNTL", REG_MMIO, 0x22F6, &mmPA_SC_DEBUG_CNTL[0], sizeof(mmPA_SC_DEBUG_CNTL)/sizeof(mmPA_SC_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_DATA", REG_MMIO, 0x22F7, &mmPA_SC_DEBUG_DATA[0], sizeof(mmPA_SC_DEBUG_DATA)/sizeof(mmPA_SC_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_SC_ENHANCE", REG_MMIO, 0x22FC, &mmPA_SC_ENHANCE[0], sizeof(mmPA_SC_ENHANCE)/sizeof(mmPA_SC_ENHANCE[0]), 0, 0 },
+	{ "mmSQ_CONFIG", REG_MMIO, 0x2300, &mmSQ_CONFIG[0], sizeof(mmSQ_CONFIG)/sizeof(mmSQ_CONFIG[0]), 0, 0 },
+	{ "mmSQC_CONFIG", REG_MMIO, 0x2301, &mmSQC_CONFIG[0], sizeof(mmSQC_CONFIG)/sizeof(mmSQC_CONFIG[0]), 0, 0 },
+	{ "mmSQC_CACHES", REG_MMIO, 0x2302, &mmSQC_CACHES[0], sizeof(mmSQC_CACHES)/sizeof(mmSQC_CACHES[0]), 0, 0 },
+	{ "mmSQ_RANDOM_WAVE_PRI", REG_MMIO, 0x2303, &mmSQ_RANDOM_WAVE_PRI[0], sizeof(mmSQ_RANDOM_WAVE_PRI)/sizeof(mmSQ_RANDOM_WAVE_PRI[0]), 0, 0 },
+	{ "mmSQ_REG_CREDITS", REG_MMIO, 0x2304, &mmSQ_REG_CREDITS[0], sizeof(mmSQ_REG_CREDITS)/sizeof(mmSQ_REG_CREDITS[0]), 0, 0 },
+	{ "mmSQ_FIFO_SIZES", REG_MMIO, 0x2305, &mmSQ_FIFO_SIZES[0], sizeof(mmSQ_FIFO_SIZES)/sizeof(mmSQ_FIFO_SIZES[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL", REG_MMIO, 0x2306, &mmSQ_PERFCOUNTER_CTRL[0], sizeof(mmSQ_PERFCOUNTER_CTRL)/sizeof(mmSQ_PERFCOUNTER_CTRL[0]), 0, 0 },
+	{ "mmCC_SQC_BANK_DISABLE", REG_MMIO, 0x2307, &mmCC_SQC_BANK_DISABLE[0], sizeof(mmCC_SQC_BANK_DISABLE)/sizeof(mmCC_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmUSER_SQC_BANK_DISABLE", REG_MMIO, 0x2308, &mmUSER_SQC_BANK_DISABLE[0], sizeof(mmUSER_SQC_BANK_DISABLE)/sizeof(mmUSER_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL", REG_MMIO, 0x2309, &mmSQ_DEBUG_STS_GLOBAL[0], sizeof(mmSQ_DEBUG_STS_GLOBAL)/sizeof(mmSQ_DEBUG_STS_GLOBAL[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_LO", REG_MMIO, 0x2320, &mmSQ_PERFCOUNTER0_LO[0], sizeof(mmSQ_PERFCOUNTER0_LO)/sizeof(mmSQ_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_HI", REG_MMIO, 0x2321, &mmSQ_PERFCOUNTER0_HI[0], sizeof(mmSQ_PERFCOUNTER0_HI)/sizeof(mmSQ_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_LO", REG_MMIO, 0x2322, &mmSQ_PERFCOUNTER1_LO[0], sizeof(mmSQ_PERFCOUNTER1_LO)/sizeof(mmSQ_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_HI", REG_MMIO, 0x2323, &mmSQ_PERFCOUNTER1_HI[0], sizeof(mmSQ_PERFCOUNTER1_HI)/sizeof(mmSQ_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_LO", REG_MMIO, 0x2324, &mmSQ_PERFCOUNTER2_LO[0], sizeof(mmSQ_PERFCOUNTER2_LO)/sizeof(mmSQ_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_HI", REG_MMIO, 0x2325, &mmSQ_PERFCOUNTER2_HI[0], sizeof(mmSQ_PERFCOUNTER2_HI)/sizeof(mmSQ_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_LO", REG_MMIO, 0x2326, &mmSQ_PERFCOUNTER3_LO[0], sizeof(mmSQ_PERFCOUNTER3_LO)/sizeof(mmSQ_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_HI", REG_MMIO, 0x2327, &mmSQ_PERFCOUNTER3_HI[0], sizeof(mmSQ_PERFCOUNTER3_HI)/sizeof(mmSQ_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_LO", REG_MMIO, 0x2328, &mmSQ_PERFCOUNTER4_LO[0], sizeof(mmSQ_PERFCOUNTER4_LO)/sizeof(mmSQ_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_HI", REG_MMIO, 0x2329, &mmSQ_PERFCOUNTER4_HI[0], sizeof(mmSQ_PERFCOUNTER4_HI)/sizeof(mmSQ_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_LO", REG_MMIO, 0x232A, &mmSQ_PERFCOUNTER5_LO[0], sizeof(mmSQ_PERFCOUNTER5_LO)/sizeof(mmSQ_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_HI", REG_MMIO, 0x232B, &mmSQ_PERFCOUNTER5_HI[0], sizeof(mmSQ_PERFCOUNTER5_HI)/sizeof(mmSQ_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_LO", REG_MMIO, 0x232C, &mmSQ_PERFCOUNTER6_LO[0], sizeof(mmSQ_PERFCOUNTER6_LO)/sizeof(mmSQ_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_HI", REG_MMIO, 0x232D, &mmSQ_PERFCOUNTER6_HI[0], sizeof(mmSQ_PERFCOUNTER6_HI)/sizeof(mmSQ_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_LO", REG_MMIO, 0x232E, &mmSQ_PERFCOUNTER7_LO[0], sizeof(mmSQ_PERFCOUNTER7_LO)/sizeof(mmSQ_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_HI", REG_MMIO, 0x232F, &mmSQ_PERFCOUNTER7_HI[0], sizeof(mmSQ_PERFCOUNTER7_HI)/sizeof(mmSQ_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_LO", REG_MMIO, 0x2330, &mmSQ_PERFCOUNTER8_LO[0], sizeof(mmSQ_PERFCOUNTER8_LO)/sizeof(mmSQ_PERFCOUNTER8_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_HI", REG_MMIO, 0x2331, &mmSQ_PERFCOUNTER8_HI[0], sizeof(mmSQ_PERFCOUNTER8_HI)/sizeof(mmSQ_PERFCOUNTER8_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_LO", REG_MMIO, 0x2332, &mmSQ_PERFCOUNTER9_LO[0], sizeof(mmSQ_PERFCOUNTER9_LO)/sizeof(mmSQ_PERFCOUNTER9_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_HI", REG_MMIO, 0x2333, &mmSQ_PERFCOUNTER9_HI[0], sizeof(mmSQ_PERFCOUNTER9_HI)/sizeof(mmSQ_PERFCOUNTER9_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_LO", REG_MMIO, 0x2334, &mmSQ_PERFCOUNTER10_LO[0], sizeof(mmSQ_PERFCOUNTER10_LO)/sizeof(mmSQ_PERFCOUNTER10_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_HI", REG_MMIO, 0x2335, &mmSQ_PERFCOUNTER10_HI[0], sizeof(mmSQ_PERFCOUNTER10_HI)/sizeof(mmSQ_PERFCOUNTER10_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_LO", REG_MMIO, 0x2336, &mmSQ_PERFCOUNTER11_LO[0], sizeof(mmSQ_PERFCOUNTER11_LO)/sizeof(mmSQ_PERFCOUNTER11_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_HI", REG_MMIO, 0x2337, &mmSQ_PERFCOUNTER11_HI[0], sizeof(mmSQ_PERFCOUNTER11_HI)/sizeof(mmSQ_PERFCOUNTER11_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_LO", REG_MMIO, 0x2338, &mmSQ_PERFCOUNTER12_LO[0], sizeof(mmSQ_PERFCOUNTER12_LO)/sizeof(mmSQ_PERFCOUNTER12_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_HI", REG_MMIO, 0x2339, &mmSQ_PERFCOUNTER12_HI[0], sizeof(mmSQ_PERFCOUNTER12_HI)/sizeof(mmSQ_PERFCOUNTER12_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_LO", REG_MMIO, 0x233A, &mmSQ_PERFCOUNTER13_LO[0], sizeof(mmSQ_PERFCOUNTER13_LO)/sizeof(mmSQ_PERFCOUNTER13_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_HI", REG_MMIO, 0x233B, &mmSQ_PERFCOUNTER13_HI[0], sizeof(mmSQ_PERFCOUNTER13_HI)/sizeof(mmSQ_PERFCOUNTER13_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_LO", REG_MMIO, 0x233C, &mmSQ_PERFCOUNTER14_LO[0], sizeof(mmSQ_PERFCOUNTER14_LO)/sizeof(mmSQ_PERFCOUNTER14_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_HI", REG_MMIO, 0x233D, &mmSQ_PERFCOUNTER14_HI[0], sizeof(mmSQ_PERFCOUNTER14_HI)/sizeof(mmSQ_PERFCOUNTER14_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_LO", REG_MMIO, 0x233E, &mmSQ_PERFCOUNTER15_LO[0], sizeof(mmSQ_PERFCOUNTER15_LO)/sizeof(mmSQ_PERFCOUNTER15_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_HI", REG_MMIO, 0x233F, &mmSQ_PERFCOUNTER15_HI[0], sizeof(mmSQ_PERFCOUNTER15_HI)/sizeof(mmSQ_PERFCOUNTER15_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_SELECT", REG_MMIO, 0x2340, &mmSQ_PERFCOUNTER0_SELECT[0], sizeof(mmSQ_PERFCOUNTER0_SELECT)/sizeof(mmSQ_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_SELECT", REG_MMIO, 0x2341, &mmSQ_PERFCOUNTER1_SELECT[0], sizeof(mmSQ_PERFCOUNTER1_SELECT)/sizeof(mmSQ_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_SELECT", REG_MMIO, 0x2342, &mmSQ_PERFCOUNTER2_SELECT[0], sizeof(mmSQ_PERFCOUNTER2_SELECT)/sizeof(mmSQ_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_SELECT", REG_MMIO, 0x2343, &mmSQ_PERFCOUNTER3_SELECT[0], sizeof(mmSQ_PERFCOUNTER3_SELECT)/sizeof(mmSQ_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_SELECT", REG_MMIO, 0x2344, &mmSQ_PERFCOUNTER4_SELECT[0], sizeof(mmSQ_PERFCOUNTER4_SELECT)/sizeof(mmSQ_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_SELECT", REG_MMIO, 0x2345, &mmSQ_PERFCOUNTER5_SELECT[0], sizeof(mmSQ_PERFCOUNTER5_SELECT)/sizeof(mmSQ_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_SELECT", REG_MMIO, 0x2346, &mmSQ_PERFCOUNTER6_SELECT[0], sizeof(mmSQ_PERFCOUNTER6_SELECT)/sizeof(mmSQ_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_SELECT", REG_MMIO, 0x2347, &mmSQ_PERFCOUNTER7_SELECT[0], sizeof(mmSQ_PERFCOUNTER7_SELECT)/sizeof(mmSQ_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_SELECT", REG_MMIO, 0x2348, &mmSQ_PERFCOUNTER8_SELECT[0], sizeof(mmSQ_PERFCOUNTER8_SELECT)/sizeof(mmSQ_PERFCOUNTER8_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_SELECT", REG_MMIO, 0x2349, &mmSQ_PERFCOUNTER9_SELECT[0], sizeof(mmSQ_PERFCOUNTER9_SELECT)/sizeof(mmSQ_PERFCOUNTER9_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_SELECT", REG_MMIO, 0x234A, &mmSQ_PERFCOUNTER10_SELECT[0], sizeof(mmSQ_PERFCOUNTER10_SELECT)/sizeof(mmSQ_PERFCOUNTER10_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_SELECT", REG_MMIO, 0x234B, &mmSQ_PERFCOUNTER11_SELECT[0], sizeof(mmSQ_PERFCOUNTER11_SELECT)/sizeof(mmSQ_PERFCOUNTER11_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_SELECT", REG_MMIO, 0x234C, &mmSQ_PERFCOUNTER12_SELECT[0], sizeof(mmSQ_PERFCOUNTER12_SELECT)/sizeof(mmSQ_PERFCOUNTER12_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_SELECT", REG_MMIO, 0x234D, &mmSQ_PERFCOUNTER13_SELECT[0], sizeof(mmSQ_PERFCOUNTER13_SELECT)/sizeof(mmSQ_PERFCOUNTER13_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_SELECT", REG_MMIO, 0x234E, &mmSQ_PERFCOUNTER14_SELECT[0], sizeof(mmSQ_PERFCOUNTER14_SELECT)/sizeof(mmSQ_PERFCOUNTER14_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_SELECT", REG_MMIO, 0x234F, &mmSQ_PERFCOUNTER15_SELECT[0], sizeof(mmSQ_PERFCOUNTER15_SELECT)/sizeof(mmSQ_PERFCOUNTER15_SELECT[0]), 0, 0 },
+	{ "mmSQ_ALU_CLK_CTRL", REG_MMIO, 0x2360, &mmSQ_ALU_CLK_CTRL[0], sizeof(mmSQ_ALU_CLK_CTRL)/sizeof(mmSQ_ALU_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_TEX_CLK_CTRL", REG_MMIO, 0x2361, &mmSQ_TEX_CLK_CTRL[0], sizeof(mmSQ_TEX_CLK_CTRL)/sizeof(mmSQ_TEX_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQ_CLK_CTRL", REG_MMIO, 0x2362, &mmCGTT_SQ_CLK_CTRL[0], sizeof(mmCGTT_SQ_CLK_CTRL)/sizeof(mmCGTT_SQ_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQG_CLK_CTRL", REG_MMIO, 0x2363, &mmCGTT_SQG_CLK_CTRL[0], sizeof(mmCGTT_SQG_CLK_CTRL)/sizeof(mmCGTT_SQG_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_IND_INDEX", REG_MMIO, 0x2378, &mmSQ_IND_INDEX[0], sizeof(mmSQ_IND_INDEX)/sizeof(mmSQ_IND_INDEX[0]), 0, 0 },
+	{ "mmSQ_IND_DATA", REG_MMIO, 0x2379, &mmSQ_IND_DATA[0], sizeof(mmSQ_IND_DATA)/sizeof(mmSQ_IND_DATA[0]), 0, 0 },
+	{ "mmSQ_IND_CMD", REG_MMIO, 0x237A, NULL, 0, 0, 0 },
+	{ "mmSQ_TIME_HI", REG_MMIO, 0x237C, &mmSQ_TIME_HI[0], sizeof(mmSQ_TIME_HI)/sizeof(mmSQ_TIME_HI[0]), 0, 0 },
+	{ "mmSQ_TIME_LO", REG_MMIO, 0x237D, &mmSQ_TIME_LO[0], sizeof(mmSQ_TIME_LO)/sizeof(mmSQ_TIME_LO[0]), 0, 0 },
+	{ "mmSQ_DS_0", REG_MMIO, 0x237F, &mmSQ_DS_0[0], sizeof(mmSQ_DS_0)/sizeof(mmSQ_DS_0[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE", REG_MMIO, 0x2380, &mmSQ_THREAD_TRACE_BASE[0], sizeof(mmSQ_THREAD_TRACE_BASE)/sizeof(mmSQ_THREAD_TRACE_BASE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_SIZE", REG_MMIO, 0x2381, &mmSQ_THREAD_TRACE_SIZE[0], sizeof(mmSQ_THREAD_TRACE_SIZE)/sizeof(mmSQ_THREAD_TRACE_SIZE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MASK", REG_MMIO, 0x2382, &mmSQ_THREAD_TRACE_MASK[0], sizeof(mmSQ_THREAD_TRACE_MASK)/sizeof(mmSQ_THREAD_TRACE_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK", REG_MMIO, 0x2383, &mmSQ_THREAD_TRACE_TOKEN_MASK[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_PERF_MASK", REG_MMIO, 0x2384, &mmSQ_THREAD_TRACE_PERF_MASK[0], sizeof(mmSQ_THREAD_TRACE_PERF_MASK)/sizeof(mmSQ_THREAD_TRACE_PERF_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_0", REG_MMIO, 0x2388, &mmSQ_THREAD_TRACE_USERDATA_0[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_0)/sizeof(mmSQ_THREAD_TRACE_USERDATA_0[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_1", REG_MMIO, 0x2389, &mmSQ_THREAD_TRACE_USERDATA_1[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_1)/sizeof(mmSQ_THREAD_TRACE_USERDATA_1[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_2", REG_MMIO, 0x238A, &mmSQ_THREAD_TRACE_USERDATA_2[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_2)/sizeof(mmSQ_THREAD_TRACE_USERDATA_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_3", REG_MMIO, 0x238B, &mmSQ_THREAD_TRACE_USERDATA_3[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_3)/sizeof(mmSQ_THREAD_TRACE_USERDATA_3[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WPTR", REG_MMIO, 0x238C, &mmSQ_THREAD_TRACE_WPTR[0], sizeof(mmSQ_THREAD_TRACE_WPTR)/sizeof(mmSQ_THREAD_TRACE_WPTR[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_STATUS", REG_MMIO, 0x238D, &mmSQ_THREAD_TRACE_STATUS[0], sizeof(mmSQ_THREAD_TRACE_STATUS)/sizeof(mmSQ_THREAD_TRACE_STATUS[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MODE", REG_MMIO, 0x238E, &mmSQ_THREAD_TRACE_MODE[0], sizeof(mmSQ_THREAD_TRACE_MODE)/sizeof(mmSQ_THREAD_TRACE_MODE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CTRL", REG_MMIO, 0x238F, &mmSQ_THREAD_TRACE_CTRL[0], sizeof(mmSQ_THREAD_TRACE_CTRL)/sizeof(mmSQ_THREAD_TRACE_CTRL[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CNTR", REG_MMIO, 0x2390, &mmSQ_THREAD_TRACE_CNTR[0], sizeof(mmSQ_THREAD_TRACE_CNTR)/sizeof(mmSQ_THREAD_TRACE_CNTR[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_HIWATER", REG_MMIO, 0x2392, &mmSQ_THREAD_TRACE_HIWATER[0], sizeof(mmSQ_THREAD_TRACE_HIWATER)/sizeof(mmSQ_THREAD_TRACE_HIWATER[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE", REG_MMIO, 0x2396, &mmSQ_POWER_THROTTLE[0], sizeof(mmSQ_POWER_THROTTLE)/sizeof(mmSQ_POWER_THROTTLE[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE2", REG_MMIO, 0x2397, &mmSQ_POWER_THROTTLE2[0], sizeof(mmSQ_POWER_THROTTLE2)/sizeof(mmSQ_POWER_THROTTLE2[0]), 0, 0 },
+	{ "mmSQ_LB_CTR_CTRL", REG_MMIO, 0x2398, &mmSQ_LB_CTR_CTRL[0], sizeof(mmSQ_LB_CTR_CTRL)/sizeof(mmSQ_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_CYCLES", REG_MMIO, 0x2399, &mmSQ_LB_DATA_ALU_CYCLES[0], sizeof(mmSQ_LB_DATA_ALU_CYCLES)/sizeof(mmSQ_LB_DATA_ALU_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_CYCLES", REG_MMIO, 0x239A, &mmSQ_LB_DATA_TEX_CYCLES[0], sizeof(mmSQ_LB_DATA_TEX_CYCLES)/sizeof(mmSQ_LB_DATA_TEX_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_STALLS", REG_MMIO, 0x239B, &mmSQ_LB_DATA_ALU_STALLS[0], sizeof(mmSQ_LB_DATA_ALU_STALLS)/sizeof(mmSQ_LB_DATA_ALU_STALLS[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_STALLS", REG_MMIO, 0x239C, &mmSQ_LB_DATA_TEX_STALLS[0], sizeof(mmSQ_LB_DATA_TEX_STALLS)/sizeof(mmSQ_LB_DATA_TEX_STALLS[0]), 0, 0 },
+	{ "mmSQC_SECDED_CNT", REG_MMIO, 0x23A0, &mmSQC_SECDED_CNT[0], sizeof(mmSQC_SECDED_CNT)/sizeof(mmSQC_SECDED_CNT[0]), 0, 0 },
+	{ "mmSQ_SEC_CNT", REG_MMIO, 0x23A1, &mmSQ_SEC_CNT[0], sizeof(mmSQ_SEC_CNT)/sizeof(mmSQ_SEC_CNT[0]), 0, 0 },
+	{ "mmSQ_DED_CNT", REG_MMIO, 0x23A2, &mmSQ_DED_CNT[0], sizeof(mmSQ_DED_CNT)/sizeof(mmSQ_DED_CNT[0]), 0, 0 },
+	{ "mmSQ_DED_INFO", REG_MMIO, 0x23A3, &mmSQ_DED_INFO[0], sizeof(mmSQ_DED_INFO)/sizeof(mmSQ_DED_INFO[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_CMN", REG_MMIO, 0x23B0, &mmSQ_THREAD_TRACE_WORD_CMN[0], sizeof(mmSQ_THREAD_TRACE_WORD_CMN)/sizeof(mmSQ_THREAD_TRACE_WORD_CMN[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2", REG_MMIO, 0x23B1, &mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD0", REG_MMIO, 0x23C0, &mmSQ_BUF_RSRC_WORD0[0], sizeof(mmSQ_BUF_RSRC_WORD0)/sizeof(mmSQ_BUF_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD1", REG_MMIO, 0x23C1, &mmSQ_BUF_RSRC_WORD1[0], sizeof(mmSQ_BUF_RSRC_WORD1)/sizeof(mmSQ_BUF_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD2", REG_MMIO, 0x23C2, &mmSQ_BUF_RSRC_WORD2[0], sizeof(mmSQ_BUF_RSRC_WORD2)/sizeof(mmSQ_BUF_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD3", REG_MMIO, 0x23C3, &mmSQ_BUF_RSRC_WORD3[0], sizeof(mmSQ_BUF_RSRC_WORD3)/sizeof(mmSQ_BUF_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD0", REG_MMIO, 0x23C4, &mmSQ_IMG_RSRC_WORD0[0], sizeof(mmSQ_IMG_RSRC_WORD0)/sizeof(mmSQ_IMG_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD1", REG_MMIO, 0x23C5, &mmSQ_IMG_RSRC_WORD1[0], sizeof(mmSQ_IMG_RSRC_WORD1)/sizeof(mmSQ_IMG_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD2", REG_MMIO, 0x23C6, &mmSQ_IMG_RSRC_WORD2[0], sizeof(mmSQ_IMG_RSRC_WORD2)/sizeof(mmSQ_IMG_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD3", REG_MMIO, 0x23C7, &mmSQ_IMG_RSRC_WORD3[0], sizeof(mmSQ_IMG_RSRC_WORD3)/sizeof(mmSQ_IMG_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD4", REG_MMIO, 0x23C8, &mmSQ_IMG_RSRC_WORD4[0], sizeof(mmSQ_IMG_RSRC_WORD4)/sizeof(mmSQ_IMG_RSRC_WORD4[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD5", REG_MMIO, 0x23C9, &mmSQ_IMG_RSRC_WORD5[0], sizeof(mmSQ_IMG_RSRC_WORD5)/sizeof(mmSQ_IMG_RSRC_WORD5[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD6", REG_MMIO, 0x23CA, &mmSQ_IMG_RSRC_WORD6[0], sizeof(mmSQ_IMG_RSRC_WORD6)/sizeof(mmSQ_IMG_RSRC_WORD6[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD7", REG_MMIO, 0x23CB, &mmSQ_IMG_RSRC_WORD7[0], sizeof(mmSQ_IMG_RSRC_WORD7)/sizeof(mmSQ_IMG_RSRC_WORD7[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD0", REG_MMIO, 0x23CC, &mmSQ_IMG_SAMP_WORD0[0], sizeof(mmSQ_IMG_SAMP_WORD0)/sizeof(mmSQ_IMG_SAMP_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD1", REG_MMIO, 0x23CD, &mmSQ_IMG_SAMP_WORD1[0], sizeof(mmSQ_IMG_SAMP_WORD1)/sizeof(mmSQ_IMG_SAMP_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD2", REG_MMIO, 0x23CE, &mmSQ_IMG_SAMP_WORD2[0], sizeof(mmSQ_IMG_SAMP_WORD2)/sizeof(mmSQ_IMG_SAMP_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD3", REG_MMIO, 0x23CF, &mmSQ_IMG_SAMP_WORD3[0], sizeof(mmSQ_IMG_SAMP_WORD3)/sizeof(mmSQ_IMG_SAMP_WORD3[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL0", REG_MMIO, 0x240C, &mmCGTT_SX_CLK_CTRL0[0], sizeof(mmCGTT_SX_CLK_CTRL0)/sizeof(mmCGTT_SX_CLK_CTRL0[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL1", REG_MMIO, 0x240D, &mmCGTT_SX_CLK_CTRL1[0], sizeof(mmCGTT_SX_CLK_CTRL1)/sizeof(mmCGTT_SX_CLK_CTRL1[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL2", REG_MMIO, 0x240E, &mmCGTT_SX_CLK_CTRL2[0], sizeof(mmCGTT_SX_CLK_CTRL2)/sizeof(mmCGTT_SX_CLK_CTRL2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL3", REG_MMIO, 0x240F, &mmCGTT_SX_CLK_CTRL3[0], sizeof(mmCGTT_SX_CLK_CTRL3)/sizeof(mmCGTT_SX_CLK_CTRL3[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL4", REG_MMIO, 0x2410, &mmCGTT_SX_CLK_CTRL4[0], sizeof(mmCGTT_SX_CLK_CTRL4)/sizeof(mmCGTT_SX_CLK_CTRL4[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY", REG_MMIO, 0x2414, &mmSX_DEBUG_BUSY[0], sizeof(mmSX_DEBUG_BUSY)/sizeof(mmSX_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_2", REG_MMIO, 0x2415, &mmSX_DEBUG_BUSY_2[0], sizeof(mmSX_DEBUG_BUSY_2)/sizeof(mmSX_DEBUG_BUSY_2[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_3", REG_MMIO, 0x2416, &mmSX_DEBUG_BUSY_3[0], sizeof(mmSX_DEBUG_BUSY_3)/sizeof(mmSX_DEBUG_BUSY_3[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_4", REG_MMIO, 0x2417, &mmSX_DEBUG_BUSY_4[0], sizeof(mmSX_DEBUG_BUSY_4)/sizeof(mmSX_DEBUG_BUSY_4[0]), 0, 0 },
+	{ "mmSX_DEBUG_1", REG_MMIO, 0x2418, &mmSX_DEBUG_1[0], sizeof(mmSX_DEBUG_1)/sizeof(mmSX_DEBUG_1[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT", REG_MMIO, 0x241C, &mmSX_PERFCOUNTER0_SELECT[0], sizeof(mmSX_PERFCOUNTER0_SELECT)/sizeof(mmSX_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT", REG_MMIO, 0x241D, &mmSX_PERFCOUNTER1_SELECT[0], sizeof(mmSX_PERFCOUNTER1_SELECT)/sizeof(mmSX_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_SELECT", REG_MMIO, 0x241E, &mmSX_PERFCOUNTER2_SELECT[0], sizeof(mmSX_PERFCOUNTER2_SELECT)/sizeof(mmSX_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_SELECT", REG_MMIO, 0x241F, &mmSX_PERFCOUNTER3_SELECT[0], sizeof(mmSX_PERFCOUNTER3_SELECT)/sizeof(mmSX_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_LO", REG_MMIO, 0x2420, &mmSX_PERFCOUNTER0_LO[0], sizeof(mmSX_PERFCOUNTER0_LO)/sizeof(mmSX_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_HI", REG_MMIO, 0x2421, &mmSX_PERFCOUNTER0_HI[0], sizeof(mmSX_PERFCOUNTER0_HI)/sizeof(mmSX_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_LO", REG_MMIO, 0x2422, &mmSX_PERFCOUNTER1_LO[0], sizeof(mmSX_PERFCOUNTER1_LO)/sizeof(mmSX_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_HI", REG_MMIO, 0x2423, &mmSX_PERFCOUNTER1_HI[0], sizeof(mmSX_PERFCOUNTER1_HI)/sizeof(mmSX_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_LO", REG_MMIO, 0x2424, &mmSX_PERFCOUNTER2_LO[0], sizeof(mmSX_PERFCOUNTER2_LO)/sizeof(mmSX_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_HI", REG_MMIO, 0x2425, &mmSX_PERFCOUNTER2_HI[0], sizeof(mmSX_PERFCOUNTER2_HI)/sizeof(mmSX_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_LO", REG_MMIO, 0x2426, &mmSX_PERFCOUNTER3_LO[0], sizeof(mmSX_PERFCOUNTER3_LO)/sizeof(mmSX_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_HI", REG_MMIO, 0x2427, &mmSX_PERFCOUNTER3_HI[0], sizeof(mmSX_PERFCOUNTER3_HI)/sizeof(mmSX_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSPI_STATIC_THREAD_MGMT_3", REG_MMIO, 0x243A, NULL, 0, 0, 0 },
+	{ "mmSPI_PS_MAX_WAVE_ID", REG_MMIO, 0x243B, &mmSPI_PS_MAX_WAVE_ID[0], sizeof(mmSPI_PS_MAX_WAVE_ID)/sizeof(mmSPI_PS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmSPI_ARB_PRIORITY", REG_MMIO, 0x243C, &mmSPI_ARB_PRIORITY[0], sizeof(mmSPI_ARB_PRIORITY)/sizeof(mmSPI_ARB_PRIORITY[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_0", REG_MMIO, 0x243D, &mmSPI_ARB_CYCLES_0[0], sizeof(mmSPI_ARB_CYCLES_0)/sizeof(mmSPI_ARB_CYCLES_0[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_1", REG_MMIO, 0x243E, &mmSPI_ARB_CYCLES_1[0], sizeof(mmSPI_ARB_CYCLES_1)/sizeof(mmSPI_ARB_CYCLES_1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER_BINS", REG_MMIO, 0x243F, &mmSPI_PERFCOUNTER_BINS[0], sizeof(mmSPI_PERFCOUNTER_BINS)/sizeof(mmSPI_PERFCOUNTER_BINS[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL", REG_MMIO, 0x2440, &mmSPI_CONFIG_CNTL[0], sizeof(mmSPI_CONFIG_CNTL)/sizeof(mmSPI_CONFIG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_CNTL", REG_MMIO, 0x2441, &mmSPI_DEBUG_CNTL[0], sizeof(mmSPI_DEBUG_CNTL)/sizeof(mmSPI_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_READ", REG_MMIO, 0x2442, &mmSPI_DEBUG_READ[0], sizeof(mmSPI_DEBUG_READ)/sizeof(mmSPI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT", REG_MMIO, 0x2443, &mmSPI_PERFCOUNTER0_SELECT[0], sizeof(mmSPI_PERFCOUNTER0_SELECT)/sizeof(mmSPI_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT", REG_MMIO, 0x2444, &mmSPI_PERFCOUNTER1_SELECT[0], sizeof(mmSPI_PERFCOUNTER1_SELECT)/sizeof(mmSPI_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT", REG_MMIO, 0x2445, &mmSPI_PERFCOUNTER2_SELECT[0], sizeof(mmSPI_PERFCOUNTER2_SELECT)/sizeof(mmSPI_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT", REG_MMIO, 0x2446, &mmSPI_PERFCOUNTER3_SELECT[0], sizeof(mmSPI_PERFCOUNTER3_SELECT)/sizeof(mmSPI_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_HI", REG_MMIO, 0x2447, &mmSPI_PERFCOUNTER0_HI[0], sizeof(mmSPI_PERFCOUNTER0_HI)/sizeof(mmSPI_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_LO", REG_MMIO, 0x2448, &mmSPI_PERFCOUNTER0_LO[0], sizeof(mmSPI_PERFCOUNTER0_LO)/sizeof(mmSPI_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_HI", REG_MMIO, 0x2449, &mmSPI_PERFCOUNTER1_HI[0], sizeof(mmSPI_PERFCOUNTER1_HI)/sizeof(mmSPI_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_LO", REG_MMIO, 0x244A, &mmSPI_PERFCOUNTER1_LO[0], sizeof(mmSPI_PERFCOUNTER1_LO)/sizeof(mmSPI_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_HI", REG_MMIO, 0x244B, &mmSPI_PERFCOUNTER2_HI[0], sizeof(mmSPI_PERFCOUNTER2_HI)/sizeof(mmSPI_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_LO", REG_MMIO, 0x244C, &mmSPI_PERFCOUNTER2_LO[0], sizeof(mmSPI_PERFCOUNTER2_LO)/sizeof(mmSPI_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_HI", REG_MMIO, 0x244D, &mmSPI_PERFCOUNTER3_HI[0], sizeof(mmSPI_PERFCOUNTER3_HI)/sizeof(mmSPI_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_LO", REG_MMIO, 0x244E, &mmSPI_PERFCOUNTER3_LO[0], sizeof(mmSPI_PERFCOUNTER3_LO)/sizeof(mmSPI_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL_1", REG_MMIO, 0x244F, &mmSPI_CONFIG_CNTL_1[0], sizeof(mmSPI_CONFIG_CNTL_1)/sizeof(mmSPI_CONFIG_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_DEBUG_BUSY", REG_MMIO, 0x2450, &mmSPI_DEBUG_BUSY[0], sizeof(mmSPI_DEBUG_BUSY)/sizeof(mmSPI_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmCGTT_SPI_CLK_CTRL", REG_MMIO, 0x2451, &mmCGTT_SPI_CLK_CTRL[0], sizeof(mmCGTT_SPI_CLK_CTRL)/sizeof(mmCGTT_SPI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTS_TCC_DISABLE", REG_MMIO, 0x2452, &mmCGTS_TCC_DISABLE[0], sizeof(mmCGTS_TCC_DISABLE)/sizeof(mmCGTS_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_USER_TCC_DISABLE", REG_MMIO, 0x2453, &mmCGTS_USER_TCC_DISABLE[0], sizeof(mmCGTS_USER_TCC_DISABLE)/sizeof(mmCGTS_USER_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_SM_CTRL_REG", REG_MMIO, 0x2454, &mmCGTS_SM_CTRL_REG[0], sizeof(mmCGTS_SM_CTRL_REG)/sizeof(mmCGTS_SM_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_CTRL_REG", REG_MMIO, 0x2455, &mmCGTS_RD_CTRL_REG[0], sizeof(mmCGTS_RD_CTRL_REG)/sizeof(mmCGTS_RD_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_REG", REG_MMIO, 0x2456, &mmCGTS_RD_REG[0], sizeof(mmCGTS_RD_REG)/sizeof(mmCGTS_RD_REG[0]), 0, 0 },
+	{ "mmCGTT_PC_CLK_CTRL", REG_MMIO, 0x24A8, &mmCGTT_PC_CLK_CTRL[0], sizeof(mmCGTT_PC_CLK_CTRL)/sizeof(mmCGTT_PC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_BCI_CLK_CTRL", REG_MMIO, 0x24A9, &mmCGTT_BCI_CLK_CTRL[0], sizeof(mmCGTT_BCI_CLK_CTRL)/sizeof(mmCGTT_BCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmSPI_SLAVE_DEBUG_BUSY", REG_MMIO, 0x24D3, &mmSPI_SLAVE_DEBUG_BUSY[0], sizeof(mmSPI_SLAVE_DEBUG_BUSY)/sizeof(mmSPI_SLAVE_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_LB_CTR_CTRL", REG_MMIO, 0x24D4, &mmSPI_LB_CTR_CTRL[0], sizeof(mmSPI_LB_CTR_CTRL)/sizeof(mmSPI_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSPI_LB_CU_MASK", REG_MMIO, 0x24D5, &mmSPI_LB_CU_MASK[0], sizeof(mmSPI_LB_CU_MASK)/sizeof(mmSPI_LB_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_LB_DATA_REG", REG_MMIO, 0x24D6, &mmSPI_LB_DATA_REG[0], sizeof(mmSPI_LB_DATA_REG)/sizeof(mmSPI_LB_DATA_REG[0]), 0, 0 },
+	{ "mmSPI_PG_ENABLE_STATIC_CU_MASK", REG_MMIO, 0x24D7, &mmSPI_PG_ENABLE_STATIC_CU_MASK[0], sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK)/sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_GDS_CREDITS", REG_MMIO, 0x24D8, &mmSPI_GDS_CREDITS[0], sizeof(mmSPI_GDS_CREDITS)/sizeof(mmSPI_GDS_CREDITS[0]), 0, 0 },
+	{ "mmSPI_SX_EXPORT_BUFFER_SIZES", REG_MMIO, 0x24D9, &mmSPI_SX_EXPORT_BUFFER_SIZES[0], sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES)/sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_SX_SCOREBOARD_BUFFER_SIZES", REG_MMIO, 0x24DA, &mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0], sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES)/sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmBCI_DEBUG_READ", REG_MMIO, 0x24E3, &mmBCI_DEBUG_READ[0], sizeof(mmBCI_DEBUG_READ)/sizeof(mmBCI_DEBUG_READ[0]), 0, 0 },
+	{ "mmTD_CNTL", REG_MMIO, 0x2525, &mmTD_CNTL[0], sizeof(mmTD_CNTL)/sizeof(mmTD_CNTL[0]), 0, 0 },
+	{ "mmTD_STATUS", REG_MMIO, 0x2526, &mmTD_STATUS[0], sizeof(mmTD_STATUS)/sizeof(mmTD_STATUS[0]), 0, 0 },
+	{ "mmTD_CGTT_CTRL", REG_MMIO, 0x2527, &mmTD_CGTT_CTRL[0], sizeof(mmTD_CGTT_CTRL)/sizeof(mmTD_CGTT_CTRL[0]), 0, 0 },
+	{ "mmTD_DEBUG_INDEX", REG_MMIO, 0x2528, &mmTD_DEBUG_INDEX[0], sizeof(mmTD_DEBUG_INDEX)/sizeof(mmTD_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTD_DEBUG_DATA", REG_MMIO, 0x2529, &mmTD_DEBUG_DATA[0], sizeof(mmTD_DEBUG_DATA)/sizeof(mmTD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT", REG_MMIO, 0x252C, &mmTD_PERFCOUNTER0_SELECT[0], sizeof(mmTD_PERFCOUNTER0_SELECT)/sizeof(mmTD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_LO", REG_MMIO, 0x252D, &mmTD_PERFCOUNTER0_LO[0], sizeof(mmTD_PERFCOUNTER0_LO)/sizeof(mmTD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_HI", REG_MMIO, 0x252E, &mmTD_PERFCOUNTER0_HI[0], sizeof(mmTD_PERFCOUNTER0_HI)/sizeof(mmTD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTD_SCRATCH", REG_MMIO, 0x2530, &mmTD_SCRATCH[0], sizeof(mmTD_SCRATCH)/sizeof(mmTD_SCRATCH[0]), 0, 0 },
+	{ "mmTA_CNTL", REG_MMIO, 0x2541, &mmTA_CNTL[0], sizeof(mmTA_CNTL)/sizeof(mmTA_CNTL[0]), 0, 0 },
+	{ "mmTA_CNTL_AUX", REG_MMIO, 0x2542, &mmTA_CNTL_AUX[0], sizeof(mmTA_CNTL_AUX)/sizeof(mmTA_CNTL_AUX[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR", REG_MMIO, 0x2543, &mmTA_CS_BC_BASE_ADDR[0], sizeof(mmTA_CS_BC_BASE_ADDR)/sizeof(mmTA_CS_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_CGTT_CTRL", REG_MMIO, 0x2544, &mmTA_CGTT_CTRL[0], sizeof(mmTA_CGTT_CTRL)/sizeof(mmTA_CGTT_CTRL[0]), 0, 0 },
+	{ "mmTA_STATUS", REG_MMIO, 0x2548, &mmTA_STATUS[0], sizeof(mmTA_STATUS)/sizeof(mmTA_STATUS[0]), 0, 0 },
+	{ "mmTA_DEBUG_INDEX", REG_MMIO, 0x254C, &mmTA_DEBUG_INDEX[0], sizeof(mmTA_DEBUG_INDEX)/sizeof(mmTA_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTA_DEBUG_DATA", REG_MMIO, 0x254D, &mmTA_DEBUG_DATA[0], sizeof(mmTA_DEBUG_DATA)/sizeof(mmTA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT", REG_MMIO, 0x2554, &mmTA_PERFCOUNTER0_SELECT[0], sizeof(mmTA_PERFCOUNTER0_SELECT)/sizeof(mmTA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_LO", REG_MMIO, 0x2555, &mmTA_PERFCOUNTER0_LO[0], sizeof(mmTA_PERFCOUNTER0_LO)/sizeof(mmTA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_HI", REG_MMIO, 0x2556, &mmTA_PERFCOUNTER0_HI[0], sizeof(mmTA_PERFCOUNTER0_HI)/sizeof(mmTA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_SELECT", REG_MMIO, 0x2560, &mmTA_PERFCOUNTER1_SELECT[0], sizeof(mmTA_PERFCOUNTER1_SELECT)/sizeof(mmTA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_LO", REG_MMIO, 0x2561, &mmTA_PERFCOUNTER1_LO[0], sizeof(mmTA_PERFCOUNTER1_LO)/sizeof(mmTA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_HI", REG_MMIO, 0x2562, &mmTA_PERFCOUNTER1_HI[0], sizeof(mmTA_PERFCOUNTER1_HI)/sizeof(mmTA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTA_SCRATCH", REG_MMIO, 0x2564, &mmTA_SCRATCH[0], sizeof(mmTA_SCRATCH)/sizeof(mmTA_SCRATCH[0]), 0, 0 },
+	{ "mmGDS_CONFIG", REG_MMIO, 0x25C0, &mmGDS_CONFIG[0], sizeof(mmGDS_CONFIG)/sizeof(mmGDS_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CNTL_STATUS", REG_MMIO, 0x25C1, &mmGDS_CNTL_STATUS[0], sizeof(mmGDS_CNTL_STATUS)/sizeof(mmGDS_CNTL_STATUS[0]), 0, 0 },
+	{ "mmGDS_RD_ADDR", REG_MMIO, 0x25C2, &mmGDS_RD_ADDR[0], sizeof(mmGDS_RD_ADDR)/sizeof(mmGDS_RD_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_DATA", REG_MMIO, 0x25C3, &mmGDS_RD_DATA[0], sizeof(mmGDS_RD_DATA)/sizeof(mmGDS_RD_DATA[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_ADDR", REG_MMIO, 0x25C4, &mmGDS_RD_BURST_ADDR[0], sizeof(mmGDS_RD_BURST_ADDR)/sizeof(mmGDS_RD_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_COUNT", REG_MMIO, 0x25C5, &mmGDS_RD_BURST_COUNT[0], sizeof(mmGDS_RD_BURST_COUNT)/sizeof(mmGDS_RD_BURST_COUNT[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_DATA", REG_MMIO, 0x25C6, &mmGDS_RD_BURST_DATA[0], sizeof(mmGDS_RD_BURST_DATA)/sizeof(mmGDS_RD_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_ADDR", REG_MMIO, 0x25C7, &mmGDS_WR_ADDR[0], sizeof(mmGDS_WR_ADDR)/sizeof(mmGDS_WR_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_DATA", REG_MMIO, 0x25C8, &mmGDS_WR_DATA[0], sizeof(mmGDS_WR_DATA)/sizeof(mmGDS_WR_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_ADDR", REG_MMIO, 0x25C9, &mmGDS_WR_BURST_ADDR[0], sizeof(mmGDS_WR_BURST_ADDR)/sizeof(mmGDS_WR_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_DATA", REG_MMIO, 0x25CA, &mmGDS_WR_BURST_DATA[0], sizeof(mmGDS_WR_BURST_DATA)/sizeof(mmGDS_WR_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WRITE_COMPLETE", REG_MMIO, 0x25CB, &mmGDS_WRITE_COMPLETE[0], sizeof(mmGDS_WRITE_COMPLETE)/sizeof(mmGDS_WRITE_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_CNTL", REG_MMIO, 0x25CC, &mmGDS_ATOM_CNTL[0], sizeof(mmGDS_ATOM_CNTL)/sizeof(mmGDS_ATOM_CNTL[0]), 0, 0 },
+	{ "mmGDS_ATOM_COMPLETE", REG_MMIO, 0x25CD, &mmGDS_ATOM_COMPLETE[0], sizeof(mmGDS_ATOM_COMPLETE)/sizeof(mmGDS_ATOM_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_BASE", REG_MMIO, 0x25CE, &mmGDS_ATOM_BASE[0], sizeof(mmGDS_ATOM_BASE)/sizeof(mmGDS_ATOM_BASE[0]), 0, 0 },
+	{ "mmGDS_ATOM_SIZE", REG_MMIO, 0x25CF, &mmGDS_ATOM_SIZE[0], sizeof(mmGDS_ATOM_SIZE)/sizeof(mmGDS_ATOM_SIZE[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET0", REG_MMIO, 0x25D0, &mmGDS_ATOM_OFFSET0[0], sizeof(mmGDS_ATOM_OFFSET0)/sizeof(mmGDS_ATOM_OFFSET0[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET1", REG_MMIO, 0x25D1, &mmGDS_ATOM_OFFSET1[0], sizeof(mmGDS_ATOM_OFFSET1)/sizeof(mmGDS_ATOM_OFFSET1[0]), 0, 0 },
+	{ "mmGDS_ATOM_DST", REG_MMIO, 0x25D2, &mmGDS_ATOM_DST[0], sizeof(mmGDS_ATOM_DST)/sizeof(mmGDS_ATOM_DST[0]), 0, 0 },
+	{ "mmGDS_ATOM_OP", REG_MMIO, 0x25D3, &mmGDS_ATOM_OP[0], sizeof(mmGDS_ATOM_OP)/sizeof(mmGDS_ATOM_OP[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0", REG_MMIO, 0x25D4, &mmGDS_ATOM_SRC0[0], sizeof(mmGDS_ATOM_SRC0)/sizeof(mmGDS_ATOM_SRC0[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0_U", REG_MMIO, 0x25D5, &mmGDS_ATOM_SRC0_U[0], sizeof(mmGDS_ATOM_SRC0_U)/sizeof(mmGDS_ATOM_SRC0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1", REG_MMIO, 0x25D6, &mmGDS_ATOM_SRC1[0], sizeof(mmGDS_ATOM_SRC1)/sizeof(mmGDS_ATOM_SRC1[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1_U", REG_MMIO, 0x25D7, &mmGDS_ATOM_SRC1_U[0], sizeof(mmGDS_ATOM_SRC1_U)/sizeof(mmGDS_ATOM_SRC1_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0", REG_MMIO, 0x25D8, &mmGDS_ATOM_READ0[0], sizeof(mmGDS_ATOM_READ0)/sizeof(mmGDS_ATOM_READ0[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0_U", REG_MMIO, 0x25D9, &mmGDS_ATOM_READ0_U[0], sizeof(mmGDS_ATOM_READ0_U)/sizeof(mmGDS_ATOM_READ0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1", REG_MMIO, 0x25DA, &mmGDS_ATOM_READ1[0], sizeof(mmGDS_ATOM_READ1)/sizeof(mmGDS_ATOM_READ1[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1_U", REG_MMIO, 0x25DB, &mmGDS_ATOM_READ1_U[0], sizeof(mmGDS_ATOM_READ1_U)/sizeof(mmGDS_ATOM_READ1_U[0]), 0, 0 },
+	{ "mmGDS_ENHANCE", REG_MMIO, 0x25DC, &mmGDS_ENHANCE[0], sizeof(mmGDS_ENHANCE)/sizeof(mmGDS_ENHANCE[0]), 0, 0 },
+	{ "mmCGTT_GDS_CLK_CTRL", REG_MMIO, 0x25DD, &mmCGTT_GDS_CLK_CTRL[0], sizeof(mmCGTT_GDS_CLK_CTRL)/sizeof(mmCGTT_GDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmGDS_DEBUG_CNTL", REG_MMIO, 0x25DE, &mmGDS_DEBUG_CNTL[0], sizeof(mmGDS_DEBUG_CNTL)/sizeof(mmGDS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGDS_DEBUG_DATA", REG_MMIO, 0x25DF, &mmGDS_DEBUG_DATA[0], sizeof(mmGDS_DEBUG_DATA)/sizeof(mmGDS_DEBUG_DATA[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNTL", REG_MMIO, 0x25E0, &mmGDS_GWS_RESOURCE_CNTL[0], sizeof(mmGDS_GWS_RESOURCE_CNTL)/sizeof(mmGDS_GWS_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE", REG_MMIO, 0x25E1, &mmGDS_GWS_RESOURCE[0], sizeof(mmGDS_GWS_RESOURCE)/sizeof(mmGDS_GWS_RESOURCE[0]), 0, 0 },
+	{ "mmGDS_SECDED_CNT", REG_MMIO, 0x25E2, &mmGDS_SECDED_CNT[0], sizeof(mmGDS_SECDED_CNT)/sizeof(mmGDS_SECDED_CNT[0]), 0, 0 },
+	{ "mmGDS_GRBM_SECDED_CNT", REG_MMIO, 0x25E3, &mmGDS_GRBM_SECDED_CNT[0], sizeof(mmGDS_GRBM_SECDED_CNT)/sizeof(mmGDS_GRBM_SECDED_CNT[0]), 0, 0 },
+	{ "mmGDS_OA_DED", REG_MMIO, 0x25E4, &mmGDS_OA_DED[0], sizeof(mmGDS_OA_DED)/sizeof(mmGDS_OA_DED[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT", REG_MMIO, 0x25E5, &mmGDS_PERFCOUNTER0_SELECT[0], sizeof(mmGDS_PERFCOUNTER0_SELECT)/sizeof(mmGDS_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_LO", REG_MMIO, 0x25E6, &mmGDS_PERFCOUNTER0_LO[0], sizeof(mmGDS_PERFCOUNTER0_LO)/sizeof(mmGDS_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_HI", REG_MMIO, 0x25E7, &mmGDS_PERFCOUNTER0_HI[0], sizeof(mmGDS_PERFCOUNTER0_HI)/sizeof(mmGDS_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_SELECT", REG_MMIO, 0x25E8, &mmGDS_PERFCOUNTER1_SELECT[0], sizeof(mmGDS_PERFCOUNTER1_SELECT)/sizeof(mmGDS_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_LO", REG_MMIO, 0x25E9, &mmGDS_PERFCOUNTER1_LO[0], sizeof(mmGDS_PERFCOUNTER1_LO)/sizeof(mmGDS_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_HI", REG_MMIO, 0x25EA, &mmGDS_PERFCOUNTER1_HI[0], sizeof(mmGDS_PERFCOUNTER1_HI)/sizeof(mmGDS_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_SELECT", REG_MMIO, 0x25EB, &mmGDS_PERFCOUNTER2_SELECT[0], sizeof(mmGDS_PERFCOUNTER2_SELECT)/sizeof(mmGDS_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_LO", REG_MMIO, 0x25EC, &mmGDS_PERFCOUNTER2_LO[0], sizeof(mmGDS_PERFCOUNTER2_LO)/sizeof(mmGDS_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_HI", REG_MMIO, 0x25ED, &mmGDS_PERFCOUNTER2_HI[0], sizeof(mmGDS_PERFCOUNTER2_HI)/sizeof(mmGDS_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_SELECT", REG_MMIO, 0x25EE, &mmGDS_PERFCOUNTER3_SELECT[0], sizeof(mmGDS_PERFCOUNTER3_SELECT)/sizeof(mmGDS_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_LO", REG_MMIO, 0x25EF, &mmGDS_PERFCOUNTER3_LO[0], sizeof(mmGDS_PERFCOUNTER3_LO)/sizeof(mmGDS_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_HI", REG_MMIO, 0x25F0, &mmGDS_PERFCOUNTER3_HI[0], sizeof(mmGDS_PERFCOUNTER3_HI)/sizeof(mmGDS_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT", REG_MMIO, 0x2600, &mmDB_PERFCOUNTER0_SELECT[0], sizeof(mmDB_PERFCOUNTER0_SELECT)/sizeof(mmDB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_LO", REG_MMIO, 0x2601, &mmDB_PERFCOUNTER0_LO[0], sizeof(mmDB_PERFCOUNTER0_LO)/sizeof(mmDB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_HI", REG_MMIO, 0x2602, &mmDB_PERFCOUNTER0_HI[0], sizeof(mmDB_PERFCOUNTER0_HI)/sizeof(mmDB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT", REG_MMIO, 0x2603, &mmDB_PERFCOUNTER1_SELECT[0], sizeof(mmDB_PERFCOUNTER1_SELECT)/sizeof(mmDB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_LO", REG_MMIO, 0x2604, &mmDB_PERFCOUNTER1_LO[0], sizeof(mmDB_PERFCOUNTER1_LO)/sizeof(mmDB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_HI", REG_MMIO, 0x2605, &mmDB_PERFCOUNTER1_HI[0], sizeof(mmDB_PERFCOUNTER1_HI)/sizeof(mmDB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_SELECT", REG_MMIO, 0x2606, &mmDB_PERFCOUNTER2_SELECT[0], sizeof(mmDB_PERFCOUNTER2_SELECT)/sizeof(mmDB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_LO", REG_MMIO, 0x2607, &mmDB_PERFCOUNTER2_LO[0], sizeof(mmDB_PERFCOUNTER2_LO)/sizeof(mmDB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_HI", REG_MMIO, 0x2608, &mmDB_PERFCOUNTER2_HI[0], sizeof(mmDB_PERFCOUNTER2_HI)/sizeof(mmDB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_SELECT", REG_MMIO, 0x2609, &mmDB_PERFCOUNTER3_SELECT[0], sizeof(mmDB_PERFCOUNTER3_SELECT)/sizeof(mmDB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_LO", REG_MMIO, 0x260A, &mmDB_PERFCOUNTER3_LO[0], sizeof(mmDB_PERFCOUNTER3_LO)/sizeof(mmDB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_HI", REG_MMIO, 0x260B, &mmDB_PERFCOUNTER3_HI[0], sizeof(mmDB_PERFCOUNTER3_HI)/sizeof(mmDB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmDB_DEBUG", REG_MMIO, 0x260C, &mmDB_DEBUG[0], sizeof(mmDB_DEBUG)/sizeof(mmDB_DEBUG[0]), 0, 0 },
+	{ "mmDB_DEBUG2", REG_MMIO, 0x260D, &mmDB_DEBUG2[0], sizeof(mmDB_DEBUG2)/sizeof(mmDB_DEBUG2[0]), 0, 0 },
+	{ "mmDB_DEBUG3", REG_MMIO, 0x260E, &mmDB_DEBUG3[0], sizeof(mmDB_DEBUG3)/sizeof(mmDB_DEBUG3[0]), 0, 0 },
+	{ "mmDB_DEBUG4", REG_MMIO, 0x260F, &mmDB_DEBUG4[0], sizeof(mmDB_DEBUG4)/sizeof(mmDB_DEBUG4[0]), 0, 0 },
+	{ "mmDB_CREDIT_LIMIT", REG_MMIO, 0x2614, &mmDB_CREDIT_LIMIT[0], sizeof(mmDB_CREDIT_LIMIT)/sizeof(mmDB_CREDIT_LIMIT[0]), 0, 0 },
+	{ "mmDB_WATERMARKS", REG_MMIO, 0x2615, &mmDB_WATERMARKS[0], sizeof(mmDB_WATERMARKS)/sizeof(mmDB_WATERMARKS[0]), 0, 0 },
+	{ "mmDB_SUBTILE_CONTROL", REG_MMIO, 0x2616, &mmDB_SUBTILE_CONTROL[0], sizeof(mmDB_SUBTILE_CONTROL)/sizeof(mmDB_SUBTILE_CONTROL[0]), 0, 0 },
+	{ "mmDB_FREE_CACHELINES", REG_MMIO, 0x2617, &mmDB_FREE_CACHELINES[0], sizeof(mmDB_FREE_CACHELINES)/sizeof(mmDB_FREE_CACHELINES[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH1", REG_MMIO, 0x2618, &mmDB_FIFO_DEPTH1[0], sizeof(mmDB_FIFO_DEPTH1)/sizeof(mmDB_FIFO_DEPTH1[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH2", REG_MMIO, 0x2619, &mmDB_FIFO_DEPTH2[0], sizeof(mmDB_FIFO_DEPTH2)/sizeof(mmDB_FIFO_DEPTH2[0]), 0, 0 },
+	{ "mmDB_CGTT_CLK_CTRL_0", REG_MMIO, 0x261A, &mmDB_CGTT_CLK_CTRL_0[0], sizeof(mmDB_CGTT_CLK_CTRL_0)/sizeof(mmDB_CGTT_CLK_CTRL_0[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_LOW", REG_MMIO, 0x261C, &mmDB_ZPASS_COUNT_LOW[0], sizeof(mmDB_ZPASS_COUNT_LOW)/sizeof(mmDB_ZPASS_COUNT_LOW[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_HI", REG_MMIO, 0x261D, &mmDB_ZPASS_COUNT_HI[0], sizeof(mmDB_ZPASS_COUNT_HI)/sizeof(mmDB_ZPASS_COUNT_HI[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_0", REG_MMIO, 0x2620, &mmDB_READ_DEBUG_0[0], sizeof(mmDB_READ_DEBUG_0)/sizeof(mmDB_READ_DEBUG_0[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_1", REG_MMIO, 0x2621, &mmDB_READ_DEBUG_1[0], sizeof(mmDB_READ_DEBUG_1)/sizeof(mmDB_READ_DEBUG_1[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_2", REG_MMIO, 0x2622, &mmDB_READ_DEBUG_2[0], sizeof(mmDB_READ_DEBUG_2)/sizeof(mmDB_READ_DEBUG_2[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_3", REG_MMIO, 0x2623, &mmDB_READ_DEBUG_3[0], sizeof(mmDB_READ_DEBUG_3)/sizeof(mmDB_READ_DEBUG_3[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_4", REG_MMIO, 0x2624, &mmDB_READ_DEBUG_4[0], sizeof(mmDB_READ_DEBUG_4)/sizeof(mmDB_READ_DEBUG_4[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_5", REG_MMIO, 0x2625, &mmDB_READ_DEBUG_5[0], sizeof(mmDB_READ_DEBUG_5)/sizeof(mmDB_READ_DEBUG_5[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_6", REG_MMIO, 0x2626, &mmDB_READ_DEBUG_6[0], sizeof(mmDB_READ_DEBUG_6)/sizeof(mmDB_READ_DEBUG_6[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_7", REG_MMIO, 0x2627, &mmDB_READ_DEBUG_7[0], sizeof(mmDB_READ_DEBUG_7)/sizeof(mmDB_READ_DEBUG_7[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_8", REG_MMIO, 0x2628, &mmDB_READ_DEBUG_8[0], sizeof(mmDB_READ_DEBUG_8)/sizeof(mmDB_READ_DEBUG_8[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_9", REG_MMIO, 0x2629, &mmDB_READ_DEBUG_9[0], sizeof(mmDB_READ_DEBUG_9)/sizeof(mmDB_READ_DEBUG_9[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_A", REG_MMIO, 0x262A, &mmDB_READ_DEBUG_A[0], sizeof(mmDB_READ_DEBUG_A)/sizeof(mmDB_READ_DEBUG_A[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_B", REG_MMIO, 0x262B, &mmDB_READ_DEBUG_B[0], sizeof(mmDB_READ_DEBUG_B)/sizeof(mmDB_READ_DEBUG_B[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_C", REG_MMIO, 0x262C, &mmDB_READ_DEBUG_C[0], sizeof(mmDB_READ_DEBUG_C)/sizeof(mmDB_READ_DEBUG_C[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_D", REG_MMIO, 0x262D, &mmDB_READ_DEBUG_D[0], sizeof(mmDB_READ_DEBUG_D)/sizeof(mmDB_READ_DEBUG_D[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_E", REG_MMIO, 0x262E, &mmDB_READ_DEBUG_E[0], sizeof(mmDB_READ_DEBUG_E)/sizeof(mmDB_READ_DEBUG_E[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_F", REG_MMIO, 0x262F, &mmDB_READ_DEBUG_F[0], sizeof(mmDB_READ_DEBUG_F)/sizeof(mmDB_READ_DEBUG_F[0]), 0, 0 },
+	{ "mmCC_RB_REDUNDANCY", REG_MMIO, 0x263C, &mmCC_RB_REDUNDANCY[0], sizeof(mmCC_RB_REDUNDANCY)/sizeof(mmCC_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmCC_RB_BACKEND_DISABLE", REG_MMIO, 0x263D, &mmCC_RB_BACKEND_DISABLE[0], sizeof(mmCC_RB_BACKEND_DISABLE)/sizeof(mmCC_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmGB_ADDR_CONFIG", REG_MMIO, 0x263E, &mmGB_ADDR_CONFIG[0], sizeof(mmGB_ADDR_CONFIG)/sizeof(mmGB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmGB_BACKEND_MAP", REG_MMIO, 0x263F, &mmGB_BACKEND_MAP[0], sizeof(mmGB_BACKEND_MAP)/sizeof(mmGB_BACKEND_MAP[0]), 0, 0 },
+	{ "mmGB_GPU_ID", REG_MMIO, 0x2640, &mmGB_GPU_ID[0], sizeof(mmGB_GPU_ID)/sizeof(mmGB_GPU_ID[0]), 0, 0 },
+	{ "mmCC_RB_DAISY_CHAIN", REG_MMIO, 0x2641, &mmCC_RB_DAISY_CHAIN[0], sizeof(mmCC_RB_DAISY_CHAIN)/sizeof(mmCC_RB_DAISY_CHAIN[0]), 0, 0 },
+	{ "mmGB_TILE_MODE0", REG_MMIO, 0x2644, &mmGB_TILE_MODE0[0], sizeof(mmGB_TILE_MODE0)/sizeof(mmGB_TILE_MODE0[0]), 0, 0 },
+	{ "mmGB_TILE_MODE1", REG_MMIO, 0x2645, &mmGB_TILE_MODE1[0], sizeof(mmGB_TILE_MODE1)/sizeof(mmGB_TILE_MODE1[0]), 0, 0 },
+	{ "mmGB_TILE_MODE2", REG_MMIO, 0x2646, &mmGB_TILE_MODE2[0], sizeof(mmGB_TILE_MODE2)/sizeof(mmGB_TILE_MODE2[0]), 0, 0 },
+	{ "mmGB_TILE_MODE3", REG_MMIO, 0x2647, &mmGB_TILE_MODE3[0], sizeof(mmGB_TILE_MODE3)/sizeof(mmGB_TILE_MODE3[0]), 0, 0 },
+	{ "mmGB_TILE_MODE4", REG_MMIO, 0x2648, &mmGB_TILE_MODE4[0], sizeof(mmGB_TILE_MODE4)/sizeof(mmGB_TILE_MODE4[0]), 0, 0 },
+	{ "mmGB_TILE_MODE5", REG_MMIO, 0x2649, &mmGB_TILE_MODE5[0], sizeof(mmGB_TILE_MODE5)/sizeof(mmGB_TILE_MODE5[0]), 0, 0 },
+	{ "mmGB_TILE_MODE6", REG_MMIO, 0x264A, &mmGB_TILE_MODE6[0], sizeof(mmGB_TILE_MODE6)/sizeof(mmGB_TILE_MODE6[0]), 0, 0 },
+	{ "mmGB_TILE_MODE7", REG_MMIO, 0x264B, &mmGB_TILE_MODE7[0], sizeof(mmGB_TILE_MODE7)/sizeof(mmGB_TILE_MODE7[0]), 0, 0 },
+	{ "mmGB_TILE_MODE8", REG_MMIO, 0x264C, &mmGB_TILE_MODE8[0], sizeof(mmGB_TILE_MODE8)/sizeof(mmGB_TILE_MODE8[0]), 0, 0 },
+	{ "mmGB_TILE_MODE9", REG_MMIO, 0x264D, &mmGB_TILE_MODE9[0], sizeof(mmGB_TILE_MODE9)/sizeof(mmGB_TILE_MODE9[0]), 0, 0 },
+	{ "mmGB_TILE_MODE10", REG_MMIO, 0x264E, &mmGB_TILE_MODE10[0], sizeof(mmGB_TILE_MODE10)/sizeof(mmGB_TILE_MODE10[0]), 0, 0 },
+	{ "mmGB_TILE_MODE11", REG_MMIO, 0x264F, &mmGB_TILE_MODE11[0], sizeof(mmGB_TILE_MODE11)/sizeof(mmGB_TILE_MODE11[0]), 0, 0 },
+	{ "mmGB_TILE_MODE12", REG_MMIO, 0x2650, &mmGB_TILE_MODE12[0], sizeof(mmGB_TILE_MODE12)/sizeof(mmGB_TILE_MODE12[0]), 0, 0 },
+	{ "mmGB_TILE_MODE13", REG_MMIO, 0x2651, &mmGB_TILE_MODE13[0], sizeof(mmGB_TILE_MODE13)/sizeof(mmGB_TILE_MODE13[0]), 0, 0 },
+	{ "mmGB_TILE_MODE14", REG_MMIO, 0x2652, &mmGB_TILE_MODE14[0], sizeof(mmGB_TILE_MODE14)/sizeof(mmGB_TILE_MODE14[0]), 0, 0 },
+	{ "mmGB_TILE_MODE15", REG_MMIO, 0x2653, &mmGB_TILE_MODE15[0], sizeof(mmGB_TILE_MODE15)/sizeof(mmGB_TILE_MODE15[0]), 0, 0 },
+	{ "mmGB_TILE_MODE16", REG_MMIO, 0x2654, &mmGB_TILE_MODE16[0], sizeof(mmGB_TILE_MODE16)/sizeof(mmGB_TILE_MODE16[0]), 0, 0 },
+	{ "mmGB_TILE_MODE17", REG_MMIO, 0x2655, &mmGB_TILE_MODE17[0], sizeof(mmGB_TILE_MODE17)/sizeof(mmGB_TILE_MODE17[0]), 0, 0 },
+	{ "mmGB_TILE_MODE18", REG_MMIO, 0x2656, &mmGB_TILE_MODE18[0], sizeof(mmGB_TILE_MODE18)/sizeof(mmGB_TILE_MODE18[0]), 0, 0 },
+	{ "mmGB_TILE_MODE19", REG_MMIO, 0x2657, &mmGB_TILE_MODE19[0], sizeof(mmGB_TILE_MODE19)/sizeof(mmGB_TILE_MODE19[0]), 0, 0 },
+	{ "mmGB_TILE_MODE20", REG_MMIO, 0x2658, &mmGB_TILE_MODE20[0], sizeof(mmGB_TILE_MODE20)/sizeof(mmGB_TILE_MODE20[0]), 0, 0 },
+	{ "mmGB_TILE_MODE21", REG_MMIO, 0x2659, &mmGB_TILE_MODE21[0], sizeof(mmGB_TILE_MODE21)/sizeof(mmGB_TILE_MODE21[0]), 0, 0 },
+	{ "mmGB_TILE_MODE22", REG_MMIO, 0x265A, &mmGB_TILE_MODE22[0], sizeof(mmGB_TILE_MODE22)/sizeof(mmGB_TILE_MODE22[0]), 0, 0 },
+	{ "mmGB_TILE_MODE23", REG_MMIO, 0x265B, &mmGB_TILE_MODE23[0], sizeof(mmGB_TILE_MODE23)/sizeof(mmGB_TILE_MODE23[0]), 0, 0 },
+	{ "mmGB_TILE_MODE24", REG_MMIO, 0x265C, &mmGB_TILE_MODE24[0], sizeof(mmGB_TILE_MODE24)/sizeof(mmGB_TILE_MODE24[0]), 0, 0 },
+	{ "mmGB_TILE_MODE25", REG_MMIO, 0x265D, &mmGB_TILE_MODE25[0], sizeof(mmGB_TILE_MODE25)/sizeof(mmGB_TILE_MODE25[0]), 0, 0 },
+	{ "mmGB_TILE_MODE26", REG_MMIO, 0x265E, &mmGB_TILE_MODE26[0], sizeof(mmGB_TILE_MODE26)/sizeof(mmGB_TILE_MODE26[0]), 0, 0 },
+	{ "mmGB_TILE_MODE27", REG_MMIO, 0x265F, &mmGB_TILE_MODE27[0], sizeof(mmGB_TILE_MODE27)/sizeof(mmGB_TILE_MODE27[0]), 0, 0 },
+	{ "mmGB_TILE_MODE28", REG_MMIO, 0x2660, &mmGB_TILE_MODE28[0], sizeof(mmGB_TILE_MODE28)/sizeof(mmGB_TILE_MODE28[0]), 0, 0 },
+	{ "mmGB_TILE_MODE29", REG_MMIO, 0x2661, &mmGB_TILE_MODE29[0], sizeof(mmGB_TILE_MODE29)/sizeof(mmGB_TILE_MODE29[0]), 0, 0 },
+	{ "mmGB_TILE_MODE30", REG_MMIO, 0x2662, &mmGB_TILE_MODE30[0], sizeof(mmGB_TILE_MODE30)/sizeof(mmGB_TILE_MODE30[0]), 0, 0 },
+	{ "mmGB_TILE_MODE31", REG_MMIO, 0x2663, &mmGB_TILE_MODE31[0], sizeof(mmGB_TILE_MODE31)/sizeof(mmGB_TILE_MODE31[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL", REG_MMIO, 0x2684, &mmCB_HW_CONTROL[0], sizeof(mmCB_HW_CONTROL)/sizeof(mmCB_HW_CONTROL[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_1", REG_MMIO, 0x2685, &mmCB_HW_CONTROL_1[0], sizeof(mmCB_HW_CONTROL_1)/sizeof(mmCB_HW_CONTROL_1[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_2", REG_MMIO, 0x2686, &mmCB_HW_CONTROL_2[0], sizeof(mmCB_HW_CONTROL_2)/sizeof(mmCB_HW_CONTROL_2[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT0", REG_MMIO, 0x2688, NULL, 0, 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT1", REG_MMIO, 0x2689, &mmCB_PERFCOUNTER0_SELECT1[0], sizeof(mmCB_PERFCOUNTER0_SELECT1)/sizeof(mmCB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_SELECT0", REG_MMIO, 0x268A, NULL, 0, 0, 0 },
+	{ "mmCB_PERFCOUNTER1_SELECT1", REG_MMIO, 0x268B, NULL, 0, 0, 0 },
+	{ "mmCB_PERFCOUNTER2_SELECT0", REG_MMIO, 0x268C, NULL, 0, 0, 0 },
+	{ "mmCB_PERFCOUNTER2_SELECT1", REG_MMIO, 0x268D, NULL, 0, 0, 0 },
+	{ "mmCB_PERFCOUNTER3_SELECT0", REG_MMIO, 0x268E, NULL, 0, 0, 0 },
+	{ "mmCB_PERFCOUNTER3_SELECT1", REG_MMIO, 0x268F, NULL, 0, 0, 0 },
+	{ "mmCB_PERFCOUNTER0_LO", REG_MMIO, 0x2690, &mmCB_PERFCOUNTER0_LO[0], sizeof(mmCB_PERFCOUNTER0_LO)/sizeof(mmCB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_HI", REG_MMIO, 0x2691, &mmCB_PERFCOUNTER0_HI[0], sizeof(mmCB_PERFCOUNTER0_HI)/sizeof(mmCB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_LO", REG_MMIO, 0x2692, &mmCB_PERFCOUNTER1_LO[0], sizeof(mmCB_PERFCOUNTER1_LO)/sizeof(mmCB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_HI", REG_MMIO, 0x2693, &mmCB_PERFCOUNTER1_HI[0], sizeof(mmCB_PERFCOUNTER1_HI)/sizeof(mmCB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_LO", REG_MMIO, 0x2694, &mmCB_PERFCOUNTER2_LO[0], sizeof(mmCB_PERFCOUNTER2_LO)/sizeof(mmCB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_HI", REG_MMIO, 0x2695, &mmCB_PERFCOUNTER2_HI[0], sizeof(mmCB_PERFCOUNTER2_HI)/sizeof(mmCB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_LO", REG_MMIO, 0x2696, &mmCB_PERFCOUNTER3_LO[0], sizeof(mmCB_PERFCOUNTER3_LO)/sizeof(mmCB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_HI", REG_MMIO, 0x2697, &mmCB_PERFCOUNTER3_HI[0], sizeof(mmCB_PERFCOUNTER3_HI)/sizeof(mmCB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmCB_CGTT_SCLK_CTRL", REG_MMIO, 0x2698, &mmCB_CGTT_SCLK_CTRL[0], sizeof(mmCB_CGTT_SCLK_CTRL)/sizeof(mmCB_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_1", REG_MMIO, 0x2699, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_2", REG_MMIO, 0x269A, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_3", REG_MMIO, 0x269B, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_4", REG_MMIO, 0x269C, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_5", REG_MMIO, 0x269D, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_6", REG_MMIO, 0x269E, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_7", REG_MMIO, 0x269F, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_8", REG_MMIO, 0x26A0, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_9", REG_MMIO, 0x26A1, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_10", REG_MMIO, 0x26A2, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_11", REG_MMIO, 0x26A3, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_12", REG_MMIO, 0x26A4, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_13", REG_MMIO, 0x26A5, &mmCB_DEBUG_BUS_13[0], sizeof(mmCB_DEBUG_BUS_13)/sizeof(mmCB_DEBUG_BUS_13[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_14", REG_MMIO, 0x26A6, &mmCB_DEBUG_BUS_14[0], sizeof(mmCB_DEBUG_BUS_14)/sizeof(mmCB_DEBUG_BUS_14[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_15", REG_MMIO, 0x26A7, &mmCB_DEBUG_BUS_15[0], sizeof(mmCB_DEBUG_BUS_15)/sizeof(mmCB_DEBUG_BUS_15[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_16", REG_MMIO, 0x26A8, &mmCB_DEBUG_BUS_16[0], sizeof(mmCB_DEBUG_BUS_16)/sizeof(mmCB_DEBUG_BUS_16[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_17", REG_MMIO, 0x26A9, &mmCB_DEBUG_BUS_17[0], sizeof(mmCB_DEBUG_BUS_17)/sizeof(mmCB_DEBUG_BUS_17[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_18", REG_MMIO, 0x26AA, &mmCB_DEBUG_BUS_18[0], sizeof(mmCB_DEBUG_BUS_18)/sizeof(mmCB_DEBUG_BUS_18[0]), 0, 0 },
+	{ "mmGC_USER_RB_BACKEND_DISABLE", REG_MMIO, 0x26DF, &mmGC_USER_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmTCP_INVALIDATE", REG_MMIO, 0x2B00, &mmTCP_INVALIDATE[0], sizeof(mmTCP_INVALIDATE)/sizeof(mmTCP_INVALIDATE[0]), 0, 0 },
+	{ "mmTCP_STATUS", REG_MMIO, 0x2B01, &mmTCP_STATUS[0], sizeof(mmTCP_STATUS)/sizeof(mmTCP_STATUS[0]), 0, 0 },
+	{ "mmTCP_CNTL", REG_MMIO, 0x2B02, &mmTCP_CNTL[0], sizeof(mmTCP_CNTL)/sizeof(mmTCP_CNTL[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_LO", REG_MMIO, 0x2B03, &mmTCP_CHAN_STEER_LO[0], sizeof(mmTCP_CHAN_STEER_LO)/sizeof(mmTCP_CHAN_STEER_LO[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_HI", REG_MMIO, 0x2B04, &mmTCP_CHAN_STEER_HI[0], sizeof(mmTCP_CHAN_STEER_HI)/sizeof(mmTCP_CHAN_STEER_HI[0]), 0, 0 },
+	{ "mmTCP_ADDR_CONFIG", REG_MMIO, 0x2B05, &mmTCP_ADDR_CONFIG[0], sizeof(mmTCP_ADDR_CONFIG)/sizeof(mmTCP_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmTCP_CREDIT", REG_MMIO, 0x2B06, &mmTCP_CREDIT[0], sizeof(mmTCP_CREDIT)/sizeof(mmTCP_CREDIT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT", REG_MMIO, 0x2B09, &mmTCP_PERFCOUNTER0_SELECT[0], sizeof(mmTCP_PERFCOUNTER0_SELECT)/sizeof(mmTCP_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_HI", REG_MMIO, 0x2B0A, &mmTCP_PERFCOUNTER0_HI[0], sizeof(mmTCP_PERFCOUNTER0_HI)/sizeof(mmTCP_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_LO", REG_MMIO, 0x2B0B, &mmTCP_PERFCOUNTER0_LO[0], sizeof(mmTCP_PERFCOUNTER0_LO)/sizeof(mmTCP_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT", REG_MMIO, 0x2B0C, &mmTCP_PERFCOUNTER1_SELECT[0], sizeof(mmTCP_PERFCOUNTER1_SELECT)/sizeof(mmTCP_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_HI", REG_MMIO, 0x2B0D, &mmTCP_PERFCOUNTER1_HI[0], sizeof(mmTCP_PERFCOUNTER1_HI)/sizeof(mmTCP_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_LO", REG_MMIO, 0x2B0E, &mmTCP_PERFCOUNTER1_LO[0], sizeof(mmTCP_PERFCOUNTER1_LO)/sizeof(mmTCP_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_SELECT", REG_MMIO, 0x2B0F, &mmTCP_PERFCOUNTER2_SELECT[0], sizeof(mmTCP_PERFCOUNTER2_SELECT)/sizeof(mmTCP_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_HI", REG_MMIO, 0x2B10, &mmTCP_PERFCOUNTER2_HI[0], sizeof(mmTCP_PERFCOUNTER2_HI)/sizeof(mmTCP_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_LO", REG_MMIO, 0x2B11, &mmTCP_PERFCOUNTER2_LO[0], sizeof(mmTCP_PERFCOUNTER2_LO)/sizeof(mmTCP_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_SELECT", REG_MMIO, 0x2B12, &mmTCP_PERFCOUNTER3_SELECT[0], sizeof(mmTCP_PERFCOUNTER3_SELECT)/sizeof(mmTCP_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_HI", REG_MMIO, 0x2B13, &mmTCP_PERFCOUNTER3_HI[0], sizeof(mmTCP_PERFCOUNTER3_HI)/sizeof(mmTCP_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_LO", REG_MMIO, 0x2B14, &mmTCP_PERFCOUNTER3_LO[0], sizeof(mmTCP_PERFCOUNTER3_LO)/sizeof(mmTCP_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmCGTT_TCP_CLK_CTRL", REG_MMIO, 0x2B15, &mmCGTT_TCP_CLK_CTRL[0], sizeof(mmCGTT_TCP_CLK_CTRL)/sizeof(mmCGTT_TCP_CLK_CTRL[0]), 0, 0 },
+	{ "mmTCP_BUFFER_ADDR_HASH_CNTL", REG_MMIO, 0x2B16, &mmTCP_BUFFER_ADDR_HASH_CNTL[0], sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL)/sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL[0]), 0, 0 },
+	{ "mmTCP_EDC_COUNTER", REG_MMIO, 0x2B17, &mmTCP_EDC_COUNTER[0], sizeof(mmTCP_EDC_COUNTER)/sizeof(mmTCP_EDC_COUNTER[0]), 0, 0 },
+	{ "mmCGTT_TCI_CLK_CTRL", REG_MMIO, 0x2B60, &mmCGTT_TCI_CLK_CTRL[0], sizeof(mmCGTT_TCI_CLK_CTRL)/sizeof(mmCGTT_TCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmTCI_STATUS", REG_MMIO, 0x2B61, &mmTCI_STATUS[0], sizeof(mmTCI_STATUS)/sizeof(mmTCI_STATUS[0]), 0, 0 },
+	{ "mmTCI_CNTL_1", REG_MMIO, 0x2B62, &mmTCI_CNTL_1[0], sizeof(mmTCI_CNTL_1)/sizeof(mmTCI_CNTL_1[0]), 0, 0 },
+	{ "mmTCI_CNTL_2", REG_MMIO, 0x2B63, &mmTCI_CNTL_2[0], sizeof(mmTCI_CNTL_2)/sizeof(mmTCI_CNTL_2[0]), 0, 0 },
+	{ "mmTCC_CTRL", REG_MMIO, 0x2B80, &mmTCC_CTRL[0], sizeof(mmTCC_CTRL)/sizeof(mmTCC_CTRL[0]), 0, 0 },
+	{ "mmTCC_CGTT_SCLK_CTRL", REG_MMIO, 0x2B81, &mmTCC_CGTT_SCLK_CTRL[0], sizeof(mmTCC_CGTT_SCLK_CTRL)/sizeof(mmTCC_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCC_EDC_COUNTER", REG_MMIO, 0x2B82, &mmTCC_EDC_COUNTER[0], sizeof(mmTCC_EDC_COUNTER)/sizeof(mmTCC_EDC_COUNTER[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT", REG_MMIO, 0x2B90, &mmTCC_PERFCOUNTER0_SELECT[0], sizeof(mmTCC_PERFCOUNTER0_SELECT)/sizeof(mmTCC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_LO", REG_MMIO, 0x2B91, &mmTCC_PERFCOUNTER0_LO[0], sizeof(mmTCC_PERFCOUNTER0_LO)/sizeof(mmTCC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_HI", REG_MMIO, 0x2B92, &mmTCC_PERFCOUNTER0_HI[0], sizeof(mmTCC_PERFCOUNTER0_HI)/sizeof(mmTCC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT", REG_MMIO, 0x2B93, &mmTCC_PERFCOUNTER1_SELECT[0], sizeof(mmTCC_PERFCOUNTER1_SELECT)/sizeof(mmTCC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_LO", REG_MMIO, 0x2B94, &mmTCC_PERFCOUNTER1_LO[0], sizeof(mmTCC_PERFCOUNTER1_LO)/sizeof(mmTCC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_HI", REG_MMIO, 0x2B95, &mmTCC_PERFCOUNTER1_HI[0], sizeof(mmTCC_PERFCOUNTER1_HI)/sizeof(mmTCC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_SELECT", REG_MMIO, 0x2B96, &mmTCC_PERFCOUNTER2_SELECT[0], sizeof(mmTCC_PERFCOUNTER2_SELECT)/sizeof(mmTCC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_LO", REG_MMIO, 0x2B97, &mmTCC_PERFCOUNTER2_LO[0], sizeof(mmTCC_PERFCOUNTER2_LO)/sizeof(mmTCC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_HI", REG_MMIO, 0x2B98, &mmTCC_PERFCOUNTER2_HI[0], sizeof(mmTCC_PERFCOUNTER2_HI)/sizeof(mmTCC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_SELECT", REG_MMIO, 0x2B99, &mmTCC_PERFCOUNTER3_SELECT[0], sizeof(mmTCC_PERFCOUNTER3_SELECT)/sizeof(mmTCC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_LO", REG_MMIO, 0x2B9A, &mmTCC_PERFCOUNTER3_LO[0], sizeof(mmTCC_PERFCOUNTER3_LO)/sizeof(mmTCC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_HI", REG_MMIO, 0x2B9B, &mmTCC_PERFCOUNTER3_HI[0], sizeof(mmTCC_PERFCOUNTER3_HI)/sizeof(mmTCC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCA_CTRL", REG_MMIO, 0x2BC0, &mmTCA_CTRL[0], sizeof(mmTCA_CTRL)/sizeof(mmTCA_CTRL[0]), 0, 0 },
+	{ "mmTCA_CGTT_SCLK_CTRL", REG_MMIO, 0x2BC1, &mmTCA_CGTT_SCLK_CTRL[0], sizeof(mmTCA_CGTT_SCLK_CTRL)/sizeof(mmTCA_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT", REG_MMIO, 0x2BD0, &mmTCA_PERFCOUNTER0_SELECT[0], sizeof(mmTCA_PERFCOUNTER0_SELECT)/sizeof(mmTCA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_LO", REG_MMIO, 0x2BD1, &mmTCA_PERFCOUNTER0_LO[0], sizeof(mmTCA_PERFCOUNTER0_LO)/sizeof(mmTCA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_HI", REG_MMIO, 0x2BD2, &mmTCA_PERFCOUNTER0_HI[0], sizeof(mmTCA_PERFCOUNTER0_HI)/sizeof(mmTCA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT", REG_MMIO, 0x2BD3, &mmTCA_PERFCOUNTER1_SELECT[0], sizeof(mmTCA_PERFCOUNTER1_SELECT)/sizeof(mmTCA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_LO", REG_MMIO, 0x2BD4, &mmTCA_PERFCOUNTER1_LO[0], sizeof(mmTCA_PERFCOUNTER1_LO)/sizeof(mmTCA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_HI", REG_MMIO, 0x2BD5, &mmTCA_PERFCOUNTER1_HI[0], sizeof(mmTCA_PERFCOUNTER1_HI)/sizeof(mmTCA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_SELECT", REG_MMIO, 0x2BD6, &mmTCA_PERFCOUNTER2_SELECT[0], sizeof(mmTCA_PERFCOUNTER2_SELECT)/sizeof(mmTCA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_LO", REG_MMIO, 0x2BD7, &mmTCA_PERFCOUNTER2_LO[0], sizeof(mmTCA_PERFCOUNTER2_LO)/sizeof(mmTCA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_HI", REG_MMIO, 0x2BD8, &mmTCA_PERFCOUNTER2_HI[0], sizeof(mmTCA_PERFCOUNTER2_HI)/sizeof(mmTCA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_SELECT", REG_MMIO, 0x2BD9, &mmTCA_PERFCOUNTER3_SELECT[0], sizeof(mmTCA_PERFCOUNTER3_SELECT)/sizeof(mmTCA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_LO", REG_MMIO, 0x2BDA, &mmTCA_PERFCOUNTER3_LO[0], sizeof(mmTCA_PERFCOUNTER3_LO)/sizeof(mmTCA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_HI", REG_MMIO, 0x2BDB, &mmTCA_PERFCOUNTER3_HI[0], sizeof(mmTCA_PERFCOUNTER3_HI)/sizeof(mmTCA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_PS", REG_MMIO, 0x2C00, &mmSPI_SHADER_TBA_LO_PS[0], sizeof(mmSPI_SHADER_TBA_LO_PS)/sizeof(mmSPI_SHADER_TBA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_PS", REG_MMIO, 0x2C01, &mmSPI_SHADER_TBA_HI_PS[0], sizeof(mmSPI_SHADER_TBA_HI_PS)/sizeof(mmSPI_SHADER_TBA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_PS", REG_MMIO, 0x2C02, &mmSPI_SHADER_TMA_LO_PS[0], sizeof(mmSPI_SHADER_TMA_LO_PS)/sizeof(mmSPI_SHADER_TMA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_PS", REG_MMIO, 0x2C03, &mmSPI_SHADER_TMA_HI_PS[0], sizeof(mmSPI_SHADER_TMA_HI_PS)/sizeof(mmSPI_SHADER_TMA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_PS", REG_MMIO, 0x2C08, &mmSPI_SHADER_PGM_LO_PS[0], sizeof(mmSPI_SHADER_PGM_LO_PS)/sizeof(mmSPI_SHADER_PGM_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_PS", REG_MMIO, 0x2C09, &mmSPI_SHADER_PGM_HI_PS[0], sizeof(mmSPI_SHADER_PGM_HI_PS)/sizeof(mmSPI_SHADER_PGM_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_PS", REG_MMIO, 0x2C0A, &mmSPI_SHADER_PGM_RSRC1_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_PS)/sizeof(mmSPI_SHADER_PGM_RSRC1_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_PS", REG_MMIO, 0x2C0B, &mmSPI_SHADER_PGM_RSRC2_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_PS)/sizeof(mmSPI_SHADER_PGM_RSRC2_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_0", REG_MMIO, 0x2C0C, &mmSPI_SHADER_USER_DATA_PS_0[0], sizeof(mmSPI_SHADER_USER_DATA_PS_0)/sizeof(mmSPI_SHADER_USER_DATA_PS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_1", REG_MMIO, 0x2C0D, &mmSPI_SHADER_USER_DATA_PS_1[0], sizeof(mmSPI_SHADER_USER_DATA_PS_1)/sizeof(mmSPI_SHADER_USER_DATA_PS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_2", REG_MMIO, 0x2C0E, &mmSPI_SHADER_USER_DATA_PS_2[0], sizeof(mmSPI_SHADER_USER_DATA_PS_2)/sizeof(mmSPI_SHADER_USER_DATA_PS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_3", REG_MMIO, 0x2C0F, &mmSPI_SHADER_USER_DATA_PS_3[0], sizeof(mmSPI_SHADER_USER_DATA_PS_3)/sizeof(mmSPI_SHADER_USER_DATA_PS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_4", REG_MMIO, 0x2C10, &mmSPI_SHADER_USER_DATA_PS_4[0], sizeof(mmSPI_SHADER_USER_DATA_PS_4)/sizeof(mmSPI_SHADER_USER_DATA_PS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_5", REG_MMIO, 0x2C11, &mmSPI_SHADER_USER_DATA_PS_5[0], sizeof(mmSPI_SHADER_USER_DATA_PS_5)/sizeof(mmSPI_SHADER_USER_DATA_PS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_6", REG_MMIO, 0x2C12, &mmSPI_SHADER_USER_DATA_PS_6[0], sizeof(mmSPI_SHADER_USER_DATA_PS_6)/sizeof(mmSPI_SHADER_USER_DATA_PS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_7", REG_MMIO, 0x2C13, &mmSPI_SHADER_USER_DATA_PS_7[0], sizeof(mmSPI_SHADER_USER_DATA_PS_7)/sizeof(mmSPI_SHADER_USER_DATA_PS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_8", REG_MMIO, 0x2C14, &mmSPI_SHADER_USER_DATA_PS_8[0], sizeof(mmSPI_SHADER_USER_DATA_PS_8)/sizeof(mmSPI_SHADER_USER_DATA_PS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_9", REG_MMIO, 0x2C15, &mmSPI_SHADER_USER_DATA_PS_9[0], sizeof(mmSPI_SHADER_USER_DATA_PS_9)/sizeof(mmSPI_SHADER_USER_DATA_PS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_10", REG_MMIO, 0x2C16, &mmSPI_SHADER_USER_DATA_PS_10[0], sizeof(mmSPI_SHADER_USER_DATA_PS_10)/sizeof(mmSPI_SHADER_USER_DATA_PS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_11", REG_MMIO, 0x2C17, &mmSPI_SHADER_USER_DATA_PS_11[0], sizeof(mmSPI_SHADER_USER_DATA_PS_11)/sizeof(mmSPI_SHADER_USER_DATA_PS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_12", REG_MMIO, 0x2C18, &mmSPI_SHADER_USER_DATA_PS_12[0], sizeof(mmSPI_SHADER_USER_DATA_PS_12)/sizeof(mmSPI_SHADER_USER_DATA_PS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_13", REG_MMIO, 0x2C19, &mmSPI_SHADER_USER_DATA_PS_13[0], sizeof(mmSPI_SHADER_USER_DATA_PS_13)/sizeof(mmSPI_SHADER_USER_DATA_PS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_14", REG_MMIO, 0x2C1A, &mmSPI_SHADER_USER_DATA_PS_14[0], sizeof(mmSPI_SHADER_USER_DATA_PS_14)/sizeof(mmSPI_SHADER_USER_DATA_PS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_15", REG_MMIO, 0x2C1B, &mmSPI_SHADER_USER_DATA_PS_15[0], sizeof(mmSPI_SHADER_USER_DATA_PS_15)/sizeof(mmSPI_SHADER_USER_DATA_PS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_VS", REG_MMIO, 0x2C40, &mmSPI_SHADER_TBA_LO_VS[0], sizeof(mmSPI_SHADER_TBA_LO_VS)/sizeof(mmSPI_SHADER_TBA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_VS", REG_MMIO, 0x2C41, &mmSPI_SHADER_TBA_HI_VS[0], sizeof(mmSPI_SHADER_TBA_HI_VS)/sizeof(mmSPI_SHADER_TBA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_VS", REG_MMIO, 0x2C42, &mmSPI_SHADER_TMA_LO_VS[0], sizeof(mmSPI_SHADER_TMA_LO_VS)/sizeof(mmSPI_SHADER_TMA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_VS", REG_MMIO, 0x2C43, &mmSPI_SHADER_TMA_HI_VS[0], sizeof(mmSPI_SHADER_TMA_HI_VS)/sizeof(mmSPI_SHADER_TMA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_VS", REG_MMIO, 0x2C48, &mmSPI_SHADER_PGM_LO_VS[0], sizeof(mmSPI_SHADER_PGM_LO_VS)/sizeof(mmSPI_SHADER_PGM_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_VS", REG_MMIO, 0x2C49, &mmSPI_SHADER_PGM_HI_VS[0], sizeof(mmSPI_SHADER_PGM_HI_VS)/sizeof(mmSPI_SHADER_PGM_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_VS", REG_MMIO, 0x2C4A, &mmSPI_SHADER_PGM_RSRC1_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_VS)/sizeof(mmSPI_SHADER_PGM_RSRC1_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_VS", REG_MMIO, 0x2C4B, &mmSPI_SHADER_PGM_RSRC2_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_0", REG_MMIO, 0x2C4C, &mmSPI_SHADER_USER_DATA_VS_0[0], sizeof(mmSPI_SHADER_USER_DATA_VS_0)/sizeof(mmSPI_SHADER_USER_DATA_VS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_1", REG_MMIO, 0x2C4D, &mmSPI_SHADER_USER_DATA_VS_1[0], sizeof(mmSPI_SHADER_USER_DATA_VS_1)/sizeof(mmSPI_SHADER_USER_DATA_VS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_2", REG_MMIO, 0x2C4E, &mmSPI_SHADER_USER_DATA_VS_2[0], sizeof(mmSPI_SHADER_USER_DATA_VS_2)/sizeof(mmSPI_SHADER_USER_DATA_VS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_3", REG_MMIO, 0x2C4F, &mmSPI_SHADER_USER_DATA_VS_3[0], sizeof(mmSPI_SHADER_USER_DATA_VS_3)/sizeof(mmSPI_SHADER_USER_DATA_VS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_4", REG_MMIO, 0x2C50, &mmSPI_SHADER_USER_DATA_VS_4[0], sizeof(mmSPI_SHADER_USER_DATA_VS_4)/sizeof(mmSPI_SHADER_USER_DATA_VS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_5", REG_MMIO, 0x2C51, &mmSPI_SHADER_USER_DATA_VS_5[0], sizeof(mmSPI_SHADER_USER_DATA_VS_5)/sizeof(mmSPI_SHADER_USER_DATA_VS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_6", REG_MMIO, 0x2C52, &mmSPI_SHADER_USER_DATA_VS_6[0], sizeof(mmSPI_SHADER_USER_DATA_VS_6)/sizeof(mmSPI_SHADER_USER_DATA_VS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_7", REG_MMIO, 0x2C53, &mmSPI_SHADER_USER_DATA_VS_7[0], sizeof(mmSPI_SHADER_USER_DATA_VS_7)/sizeof(mmSPI_SHADER_USER_DATA_VS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_8", REG_MMIO, 0x2C54, &mmSPI_SHADER_USER_DATA_VS_8[0], sizeof(mmSPI_SHADER_USER_DATA_VS_8)/sizeof(mmSPI_SHADER_USER_DATA_VS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_9", REG_MMIO, 0x2C55, &mmSPI_SHADER_USER_DATA_VS_9[0], sizeof(mmSPI_SHADER_USER_DATA_VS_9)/sizeof(mmSPI_SHADER_USER_DATA_VS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_10", REG_MMIO, 0x2C56, &mmSPI_SHADER_USER_DATA_VS_10[0], sizeof(mmSPI_SHADER_USER_DATA_VS_10)/sizeof(mmSPI_SHADER_USER_DATA_VS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_11", REG_MMIO, 0x2C57, &mmSPI_SHADER_USER_DATA_VS_11[0], sizeof(mmSPI_SHADER_USER_DATA_VS_11)/sizeof(mmSPI_SHADER_USER_DATA_VS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_12", REG_MMIO, 0x2C58, &mmSPI_SHADER_USER_DATA_VS_12[0], sizeof(mmSPI_SHADER_USER_DATA_VS_12)/sizeof(mmSPI_SHADER_USER_DATA_VS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_13", REG_MMIO, 0x2C59, &mmSPI_SHADER_USER_DATA_VS_13[0], sizeof(mmSPI_SHADER_USER_DATA_VS_13)/sizeof(mmSPI_SHADER_USER_DATA_VS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_14", REG_MMIO, 0x2C5A, &mmSPI_SHADER_USER_DATA_VS_14[0], sizeof(mmSPI_SHADER_USER_DATA_VS_14)/sizeof(mmSPI_SHADER_USER_DATA_VS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_15", REG_MMIO, 0x2C5B, &mmSPI_SHADER_USER_DATA_VS_15[0], sizeof(mmSPI_SHADER_USER_DATA_VS_15)/sizeof(mmSPI_SHADER_USER_DATA_VS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_GS", REG_MMIO, 0x2C80, &mmSPI_SHADER_TBA_LO_GS[0], sizeof(mmSPI_SHADER_TBA_LO_GS)/sizeof(mmSPI_SHADER_TBA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_GS", REG_MMIO, 0x2C81, &mmSPI_SHADER_TBA_HI_GS[0], sizeof(mmSPI_SHADER_TBA_HI_GS)/sizeof(mmSPI_SHADER_TBA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_GS", REG_MMIO, 0x2C82, &mmSPI_SHADER_TMA_LO_GS[0], sizeof(mmSPI_SHADER_TMA_LO_GS)/sizeof(mmSPI_SHADER_TMA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_GS", REG_MMIO, 0x2C83, &mmSPI_SHADER_TMA_HI_GS[0], sizeof(mmSPI_SHADER_TMA_HI_GS)/sizeof(mmSPI_SHADER_TMA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_GS", REG_MMIO, 0x2C88, &mmSPI_SHADER_PGM_LO_GS[0], sizeof(mmSPI_SHADER_PGM_LO_GS)/sizeof(mmSPI_SHADER_PGM_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_GS", REG_MMIO, 0x2C89, &mmSPI_SHADER_PGM_HI_GS[0], sizeof(mmSPI_SHADER_PGM_HI_GS)/sizeof(mmSPI_SHADER_PGM_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_GS", REG_MMIO, 0x2C8A, &mmSPI_SHADER_PGM_RSRC1_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_GS)/sizeof(mmSPI_SHADER_PGM_RSRC1_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_GS", REG_MMIO, 0x2C8B, &mmSPI_SHADER_PGM_RSRC2_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_0", REG_MMIO, 0x2C8C, &mmSPI_SHADER_USER_DATA_GS_0[0], sizeof(mmSPI_SHADER_USER_DATA_GS_0)/sizeof(mmSPI_SHADER_USER_DATA_GS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_1", REG_MMIO, 0x2C8D, &mmSPI_SHADER_USER_DATA_GS_1[0], sizeof(mmSPI_SHADER_USER_DATA_GS_1)/sizeof(mmSPI_SHADER_USER_DATA_GS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_2", REG_MMIO, 0x2C8E, &mmSPI_SHADER_USER_DATA_GS_2[0], sizeof(mmSPI_SHADER_USER_DATA_GS_2)/sizeof(mmSPI_SHADER_USER_DATA_GS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_3", REG_MMIO, 0x2C8F, &mmSPI_SHADER_USER_DATA_GS_3[0], sizeof(mmSPI_SHADER_USER_DATA_GS_3)/sizeof(mmSPI_SHADER_USER_DATA_GS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_4", REG_MMIO, 0x2C90, &mmSPI_SHADER_USER_DATA_GS_4[0], sizeof(mmSPI_SHADER_USER_DATA_GS_4)/sizeof(mmSPI_SHADER_USER_DATA_GS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_5", REG_MMIO, 0x2C91, &mmSPI_SHADER_USER_DATA_GS_5[0], sizeof(mmSPI_SHADER_USER_DATA_GS_5)/sizeof(mmSPI_SHADER_USER_DATA_GS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_6", REG_MMIO, 0x2C92, &mmSPI_SHADER_USER_DATA_GS_6[0], sizeof(mmSPI_SHADER_USER_DATA_GS_6)/sizeof(mmSPI_SHADER_USER_DATA_GS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_7", REG_MMIO, 0x2C93, &mmSPI_SHADER_USER_DATA_GS_7[0], sizeof(mmSPI_SHADER_USER_DATA_GS_7)/sizeof(mmSPI_SHADER_USER_DATA_GS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_8", REG_MMIO, 0x2C94, &mmSPI_SHADER_USER_DATA_GS_8[0], sizeof(mmSPI_SHADER_USER_DATA_GS_8)/sizeof(mmSPI_SHADER_USER_DATA_GS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_9", REG_MMIO, 0x2C95, &mmSPI_SHADER_USER_DATA_GS_9[0], sizeof(mmSPI_SHADER_USER_DATA_GS_9)/sizeof(mmSPI_SHADER_USER_DATA_GS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_10", REG_MMIO, 0x2C96, &mmSPI_SHADER_USER_DATA_GS_10[0], sizeof(mmSPI_SHADER_USER_DATA_GS_10)/sizeof(mmSPI_SHADER_USER_DATA_GS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_11", REG_MMIO, 0x2C97, &mmSPI_SHADER_USER_DATA_GS_11[0], sizeof(mmSPI_SHADER_USER_DATA_GS_11)/sizeof(mmSPI_SHADER_USER_DATA_GS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_12", REG_MMIO, 0x2C98, &mmSPI_SHADER_USER_DATA_GS_12[0], sizeof(mmSPI_SHADER_USER_DATA_GS_12)/sizeof(mmSPI_SHADER_USER_DATA_GS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_13", REG_MMIO, 0x2C99, &mmSPI_SHADER_USER_DATA_GS_13[0], sizeof(mmSPI_SHADER_USER_DATA_GS_13)/sizeof(mmSPI_SHADER_USER_DATA_GS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_14", REG_MMIO, 0x2C9A, &mmSPI_SHADER_USER_DATA_GS_14[0], sizeof(mmSPI_SHADER_USER_DATA_GS_14)/sizeof(mmSPI_SHADER_USER_DATA_GS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_15", REG_MMIO, 0x2C9B, &mmSPI_SHADER_USER_DATA_GS_15[0], sizeof(mmSPI_SHADER_USER_DATA_GS_15)/sizeof(mmSPI_SHADER_USER_DATA_GS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_ES", REG_MMIO, 0x2CC0, &mmSPI_SHADER_TBA_LO_ES[0], sizeof(mmSPI_SHADER_TBA_LO_ES)/sizeof(mmSPI_SHADER_TBA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_ES", REG_MMIO, 0x2CC1, &mmSPI_SHADER_TBA_HI_ES[0], sizeof(mmSPI_SHADER_TBA_HI_ES)/sizeof(mmSPI_SHADER_TBA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_ES", REG_MMIO, 0x2CC2, &mmSPI_SHADER_TMA_LO_ES[0], sizeof(mmSPI_SHADER_TMA_LO_ES)/sizeof(mmSPI_SHADER_TMA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_ES", REG_MMIO, 0x2CC3, &mmSPI_SHADER_TMA_HI_ES[0], sizeof(mmSPI_SHADER_TMA_HI_ES)/sizeof(mmSPI_SHADER_TMA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_ES", REG_MMIO, 0x2CC8, &mmSPI_SHADER_PGM_LO_ES[0], sizeof(mmSPI_SHADER_PGM_LO_ES)/sizeof(mmSPI_SHADER_PGM_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_ES", REG_MMIO, 0x2CC9, &mmSPI_SHADER_PGM_HI_ES[0], sizeof(mmSPI_SHADER_PGM_HI_ES)/sizeof(mmSPI_SHADER_PGM_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_ES", REG_MMIO, 0x2CCA, &mmSPI_SHADER_PGM_RSRC1_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC1_ES)/sizeof(mmSPI_SHADER_PGM_RSRC1_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES", REG_MMIO, 0x2CCB, &mmSPI_SHADER_PGM_RSRC2_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_0", REG_MMIO, 0x2CCC, &mmSPI_SHADER_USER_DATA_ES_0[0], sizeof(mmSPI_SHADER_USER_DATA_ES_0)/sizeof(mmSPI_SHADER_USER_DATA_ES_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_1", REG_MMIO, 0x2CCD, &mmSPI_SHADER_USER_DATA_ES_1[0], sizeof(mmSPI_SHADER_USER_DATA_ES_1)/sizeof(mmSPI_SHADER_USER_DATA_ES_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_2", REG_MMIO, 0x2CCE, &mmSPI_SHADER_USER_DATA_ES_2[0], sizeof(mmSPI_SHADER_USER_DATA_ES_2)/sizeof(mmSPI_SHADER_USER_DATA_ES_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_3", REG_MMIO, 0x2CCF, &mmSPI_SHADER_USER_DATA_ES_3[0], sizeof(mmSPI_SHADER_USER_DATA_ES_3)/sizeof(mmSPI_SHADER_USER_DATA_ES_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_4", REG_MMIO, 0x2CD0, &mmSPI_SHADER_USER_DATA_ES_4[0], sizeof(mmSPI_SHADER_USER_DATA_ES_4)/sizeof(mmSPI_SHADER_USER_DATA_ES_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_5", REG_MMIO, 0x2CD1, &mmSPI_SHADER_USER_DATA_ES_5[0], sizeof(mmSPI_SHADER_USER_DATA_ES_5)/sizeof(mmSPI_SHADER_USER_DATA_ES_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_6", REG_MMIO, 0x2CD2, &mmSPI_SHADER_USER_DATA_ES_6[0], sizeof(mmSPI_SHADER_USER_DATA_ES_6)/sizeof(mmSPI_SHADER_USER_DATA_ES_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_7", REG_MMIO, 0x2CD3, &mmSPI_SHADER_USER_DATA_ES_7[0], sizeof(mmSPI_SHADER_USER_DATA_ES_7)/sizeof(mmSPI_SHADER_USER_DATA_ES_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_8", REG_MMIO, 0x2CD4, &mmSPI_SHADER_USER_DATA_ES_8[0], sizeof(mmSPI_SHADER_USER_DATA_ES_8)/sizeof(mmSPI_SHADER_USER_DATA_ES_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_9", REG_MMIO, 0x2CD5, &mmSPI_SHADER_USER_DATA_ES_9[0], sizeof(mmSPI_SHADER_USER_DATA_ES_9)/sizeof(mmSPI_SHADER_USER_DATA_ES_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_10", REG_MMIO, 0x2CD6, &mmSPI_SHADER_USER_DATA_ES_10[0], sizeof(mmSPI_SHADER_USER_DATA_ES_10)/sizeof(mmSPI_SHADER_USER_DATA_ES_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_11", REG_MMIO, 0x2CD7, &mmSPI_SHADER_USER_DATA_ES_11[0], sizeof(mmSPI_SHADER_USER_DATA_ES_11)/sizeof(mmSPI_SHADER_USER_DATA_ES_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_12", REG_MMIO, 0x2CD8, &mmSPI_SHADER_USER_DATA_ES_12[0], sizeof(mmSPI_SHADER_USER_DATA_ES_12)/sizeof(mmSPI_SHADER_USER_DATA_ES_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_13", REG_MMIO, 0x2CD9, &mmSPI_SHADER_USER_DATA_ES_13[0], sizeof(mmSPI_SHADER_USER_DATA_ES_13)/sizeof(mmSPI_SHADER_USER_DATA_ES_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_14", REG_MMIO, 0x2CDA, &mmSPI_SHADER_USER_DATA_ES_14[0], sizeof(mmSPI_SHADER_USER_DATA_ES_14)/sizeof(mmSPI_SHADER_USER_DATA_ES_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_15", REG_MMIO, 0x2CDB, &mmSPI_SHADER_USER_DATA_ES_15[0], sizeof(mmSPI_SHADER_USER_DATA_ES_15)/sizeof(mmSPI_SHADER_USER_DATA_ES_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_HS", REG_MMIO, 0x2D00, &mmSPI_SHADER_TBA_LO_HS[0], sizeof(mmSPI_SHADER_TBA_LO_HS)/sizeof(mmSPI_SHADER_TBA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_HS", REG_MMIO, 0x2D01, &mmSPI_SHADER_TBA_HI_HS[0], sizeof(mmSPI_SHADER_TBA_HI_HS)/sizeof(mmSPI_SHADER_TBA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_HS", REG_MMIO, 0x2D02, &mmSPI_SHADER_TMA_LO_HS[0], sizeof(mmSPI_SHADER_TMA_LO_HS)/sizeof(mmSPI_SHADER_TMA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_HS", REG_MMIO, 0x2D03, &mmSPI_SHADER_TMA_HI_HS[0], sizeof(mmSPI_SHADER_TMA_HI_HS)/sizeof(mmSPI_SHADER_TMA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_HS", REG_MMIO, 0x2D08, &mmSPI_SHADER_PGM_LO_HS[0], sizeof(mmSPI_SHADER_PGM_LO_HS)/sizeof(mmSPI_SHADER_PGM_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_HS", REG_MMIO, 0x2D09, &mmSPI_SHADER_PGM_HI_HS[0], sizeof(mmSPI_SHADER_PGM_HI_HS)/sizeof(mmSPI_SHADER_PGM_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_HS", REG_MMIO, 0x2D0A, &mmSPI_SHADER_PGM_RSRC1_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_HS)/sizeof(mmSPI_SHADER_PGM_RSRC1_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_HS", REG_MMIO, 0x2D0B, &mmSPI_SHADER_PGM_RSRC2_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_0", REG_MMIO, 0x2D0C, &mmSPI_SHADER_USER_DATA_HS_0[0], sizeof(mmSPI_SHADER_USER_DATA_HS_0)/sizeof(mmSPI_SHADER_USER_DATA_HS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_1", REG_MMIO, 0x2D0D, &mmSPI_SHADER_USER_DATA_HS_1[0], sizeof(mmSPI_SHADER_USER_DATA_HS_1)/sizeof(mmSPI_SHADER_USER_DATA_HS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_2", REG_MMIO, 0x2D0E, &mmSPI_SHADER_USER_DATA_HS_2[0], sizeof(mmSPI_SHADER_USER_DATA_HS_2)/sizeof(mmSPI_SHADER_USER_DATA_HS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_3", REG_MMIO, 0x2D0F, &mmSPI_SHADER_USER_DATA_HS_3[0], sizeof(mmSPI_SHADER_USER_DATA_HS_3)/sizeof(mmSPI_SHADER_USER_DATA_HS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_4", REG_MMIO, 0x2D10, &mmSPI_SHADER_USER_DATA_HS_4[0], sizeof(mmSPI_SHADER_USER_DATA_HS_4)/sizeof(mmSPI_SHADER_USER_DATA_HS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_5", REG_MMIO, 0x2D11, &mmSPI_SHADER_USER_DATA_HS_5[0], sizeof(mmSPI_SHADER_USER_DATA_HS_5)/sizeof(mmSPI_SHADER_USER_DATA_HS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_6", REG_MMIO, 0x2D12, &mmSPI_SHADER_USER_DATA_HS_6[0], sizeof(mmSPI_SHADER_USER_DATA_HS_6)/sizeof(mmSPI_SHADER_USER_DATA_HS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_7", REG_MMIO, 0x2D13, &mmSPI_SHADER_USER_DATA_HS_7[0], sizeof(mmSPI_SHADER_USER_DATA_HS_7)/sizeof(mmSPI_SHADER_USER_DATA_HS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_8", REG_MMIO, 0x2D14, &mmSPI_SHADER_USER_DATA_HS_8[0], sizeof(mmSPI_SHADER_USER_DATA_HS_8)/sizeof(mmSPI_SHADER_USER_DATA_HS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_9", REG_MMIO, 0x2D15, &mmSPI_SHADER_USER_DATA_HS_9[0], sizeof(mmSPI_SHADER_USER_DATA_HS_9)/sizeof(mmSPI_SHADER_USER_DATA_HS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_10", REG_MMIO, 0x2D16, &mmSPI_SHADER_USER_DATA_HS_10[0], sizeof(mmSPI_SHADER_USER_DATA_HS_10)/sizeof(mmSPI_SHADER_USER_DATA_HS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_11", REG_MMIO, 0x2D17, &mmSPI_SHADER_USER_DATA_HS_11[0], sizeof(mmSPI_SHADER_USER_DATA_HS_11)/sizeof(mmSPI_SHADER_USER_DATA_HS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_12", REG_MMIO, 0x2D18, &mmSPI_SHADER_USER_DATA_HS_12[0], sizeof(mmSPI_SHADER_USER_DATA_HS_12)/sizeof(mmSPI_SHADER_USER_DATA_HS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_13", REG_MMIO, 0x2D19, &mmSPI_SHADER_USER_DATA_HS_13[0], sizeof(mmSPI_SHADER_USER_DATA_HS_13)/sizeof(mmSPI_SHADER_USER_DATA_HS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_14", REG_MMIO, 0x2D1A, &mmSPI_SHADER_USER_DATA_HS_14[0], sizeof(mmSPI_SHADER_USER_DATA_HS_14)/sizeof(mmSPI_SHADER_USER_DATA_HS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_15", REG_MMIO, 0x2D1B, &mmSPI_SHADER_USER_DATA_HS_15[0], sizeof(mmSPI_SHADER_USER_DATA_HS_15)/sizeof(mmSPI_SHADER_USER_DATA_HS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_LS", REG_MMIO, 0x2D40, &mmSPI_SHADER_TBA_LO_LS[0], sizeof(mmSPI_SHADER_TBA_LO_LS)/sizeof(mmSPI_SHADER_TBA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_LS", REG_MMIO, 0x2D41, &mmSPI_SHADER_TBA_HI_LS[0], sizeof(mmSPI_SHADER_TBA_HI_LS)/sizeof(mmSPI_SHADER_TBA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_LS", REG_MMIO, 0x2D42, &mmSPI_SHADER_TMA_LO_LS[0], sizeof(mmSPI_SHADER_TMA_LO_LS)/sizeof(mmSPI_SHADER_TMA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_LS", REG_MMIO, 0x2D43, &mmSPI_SHADER_TMA_HI_LS[0], sizeof(mmSPI_SHADER_TMA_HI_LS)/sizeof(mmSPI_SHADER_TMA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_LS", REG_MMIO, 0x2D48, &mmSPI_SHADER_PGM_LO_LS[0], sizeof(mmSPI_SHADER_PGM_LO_LS)/sizeof(mmSPI_SHADER_PGM_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_LS", REG_MMIO, 0x2D49, &mmSPI_SHADER_PGM_HI_LS[0], sizeof(mmSPI_SHADER_PGM_HI_LS)/sizeof(mmSPI_SHADER_PGM_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_LS", REG_MMIO, 0x2D4A, &mmSPI_SHADER_PGM_RSRC1_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_LS)/sizeof(mmSPI_SHADER_PGM_RSRC1_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS", REG_MMIO, 0x2D4B, &mmSPI_SHADER_PGM_RSRC2_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_0", REG_MMIO, 0x2D4C, &mmSPI_SHADER_USER_DATA_LS_0[0], sizeof(mmSPI_SHADER_USER_DATA_LS_0)/sizeof(mmSPI_SHADER_USER_DATA_LS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_1", REG_MMIO, 0x2D4D, &mmSPI_SHADER_USER_DATA_LS_1[0], sizeof(mmSPI_SHADER_USER_DATA_LS_1)/sizeof(mmSPI_SHADER_USER_DATA_LS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_2", REG_MMIO, 0x2D4E, &mmSPI_SHADER_USER_DATA_LS_2[0], sizeof(mmSPI_SHADER_USER_DATA_LS_2)/sizeof(mmSPI_SHADER_USER_DATA_LS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_3", REG_MMIO, 0x2D4F, &mmSPI_SHADER_USER_DATA_LS_3[0], sizeof(mmSPI_SHADER_USER_DATA_LS_3)/sizeof(mmSPI_SHADER_USER_DATA_LS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_4", REG_MMIO, 0x2D50, &mmSPI_SHADER_USER_DATA_LS_4[0], sizeof(mmSPI_SHADER_USER_DATA_LS_4)/sizeof(mmSPI_SHADER_USER_DATA_LS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_5", REG_MMIO, 0x2D51, &mmSPI_SHADER_USER_DATA_LS_5[0], sizeof(mmSPI_SHADER_USER_DATA_LS_5)/sizeof(mmSPI_SHADER_USER_DATA_LS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_6", REG_MMIO, 0x2D52, &mmSPI_SHADER_USER_DATA_LS_6[0], sizeof(mmSPI_SHADER_USER_DATA_LS_6)/sizeof(mmSPI_SHADER_USER_DATA_LS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_7", REG_MMIO, 0x2D53, &mmSPI_SHADER_USER_DATA_LS_7[0], sizeof(mmSPI_SHADER_USER_DATA_LS_7)/sizeof(mmSPI_SHADER_USER_DATA_LS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_8", REG_MMIO, 0x2D54, &mmSPI_SHADER_USER_DATA_LS_8[0], sizeof(mmSPI_SHADER_USER_DATA_LS_8)/sizeof(mmSPI_SHADER_USER_DATA_LS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_9", REG_MMIO, 0x2D55, &mmSPI_SHADER_USER_DATA_LS_9[0], sizeof(mmSPI_SHADER_USER_DATA_LS_9)/sizeof(mmSPI_SHADER_USER_DATA_LS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_10", REG_MMIO, 0x2D56, &mmSPI_SHADER_USER_DATA_LS_10[0], sizeof(mmSPI_SHADER_USER_DATA_LS_10)/sizeof(mmSPI_SHADER_USER_DATA_LS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_11", REG_MMIO, 0x2D57, &mmSPI_SHADER_USER_DATA_LS_11[0], sizeof(mmSPI_SHADER_USER_DATA_LS_11)/sizeof(mmSPI_SHADER_USER_DATA_LS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_12", REG_MMIO, 0x2D58, &mmSPI_SHADER_USER_DATA_LS_12[0], sizeof(mmSPI_SHADER_USER_DATA_LS_12)/sizeof(mmSPI_SHADER_USER_DATA_LS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_13", REG_MMIO, 0x2D59, &mmSPI_SHADER_USER_DATA_LS_13[0], sizeof(mmSPI_SHADER_USER_DATA_LS_13)/sizeof(mmSPI_SHADER_USER_DATA_LS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_14", REG_MMIO, 0x2D5A, &mmSPI_SHADER_USER_DATA_LS_14[0], sizeof(mmSPI_SHADER_USER_DATA_LS_14)/sizeof(mmSPI_SHADER_USER_DATA_LS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_15", REG_MMIO, 0x2D5B, &mmSPI_SHADER_USER_DATA_LS_15[0], sizeof(mmSPI_SHADER_USER_DATA_LS_15)/sizeof(mmSPI_SHADER_USER_DATA_LS_15[0]), 0, 0 },
+	{ "mmCOMPUTE_DISPATCH_INITIATOR", REG_MMIO, 0x2E00, &mmCOMPUTE_DISPATCH_INITIATOR[0], sizeof(mmCOMPUTE_DISPATCH_INITIATOR)/sizeof(mmCOMPUTE_DISPATCH_INITIATOR[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_X", REG_MMIO, 0x2E01, &mmCOMPUTE_DIM_X[0], sizeof(mmCOMPUTE_DIM_X)/sizeof(mmCOMPUTE_DIM_X[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Y", REG_MMIO, 0x2E02, &mmCOMPUTE_DIM_Y[0], sizeof(mmCOMPUTE_DIM_Y)/sizeof(mmCOMPUTE_DIM_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Z", REG_MMIO, 0x2E03, &mmCOMPUTE_DIM_Z[0], sizeof(mmCOMPUTE_DIM_Z)/sizeof(mmCOMPUTE_DIM_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_START_X", REG_MMIO, 0x2E04, &mmCOMPUTE_START_X[0], sizeof(mmCOMPUTE_START_X)/sizeof(mmCOMPUTE_START_X[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Y", REG_MMIO, 0x2E05, &mmCOMPUTE_START_Y[0], sizeof(mmCOMPUTE_START_Y)/sizeof(mmCOMPUTE_START_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Z", REG_MMIO, 0x2E06, &mmCOMPUTE_START_Z[0], sizeof(mmCOMPUTE_START_Z)/sizeof(mmCOMPUTE_START_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_X", REG_MMIO, 0x2E07, &mmCOMPUTE_NUM_THREAD_X[0], sizeof(mmCOMPUTE_NUM_THREAD_X)/sizeof(mmCOMPUTE_NUM_THREAD_X[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Y", REG_MMIO, 0x2E08, &mmCOMPUTE_NUM_THREAD_Y[0], sizeof(mmCOMPUTE_NUM_THREAD_Y)/sizeof(mmCOMPUTE_NUM_THREAD_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Z", REG_MMIO, 0x2E09, &mmCOMPUTE_NUM_THREAD_Z[0], sizeof(mmCOMPUTE_NUM_THREAD_Z)/sizeof(mmCOMPUTE_NUM_THREAD_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_LO", REG_MMIO, 0x2E0C, &mmCOMPUTE_PGM_LO[0], sizeof(mmCOMPUTE_PGM_LO)/sizeof(mmCOMPUTE_PGM_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_HI", REG_MMIO, 0x2E0D, &mmCOMPUTE_PGM_HI[0], sizeof(mmCOMPUTE_PGM_HI)/sizeof(mmCOMPUTE_PGM_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_LO", REG_MMIO, 0x2E0E, &mmCOMPUTE_TBA_LO[0], sizeof(mmCOMPUTE_TBA_LO)/sizeof(mmCOMPUTE_TBA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_HI", REG_MMIO, 0x2E0F, &mmCOMPUTE_TBA_HI[0], sizeof(mmCOMPUTE_TBA_HI)/sizeof(mmCOMPUTE_TBA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_LO", REG_MMIO, 0x2E10, &mmCOMPUTE_TMA_LO[0], sizeof(mmCOMPUTE_TMA_LO)/sizeof(mmCOMPUTE_TMA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_HI", REG_MMIO, 0x2E11, &mmCOMPUTE_TMA_HI[0], sizeof(mmCOMPUTE_TMA_HI)/sizeof(mmCOMPUTE_TMA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC1", REG_MMIO, 0x2E12, &mmCOMPUTE_PGM_RSRC1[0], sizeof(mmCOMPUTE_PGM_RSRC1)/sizeof(mmCOMPUTE_PGM_RSRC1[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC2", REG_MMIO, 0x2E13, &mmCOMPUTE_PGM_RSRC2[0], sizeof(mmCOMPUTE_PGM_RSRC2)/sizeof(mmCOMPUTE_PGM_RSRC2[0]), 0, 0 },
+	{ "mmCOMPUTE_VMID", REG_MMIO, 0x2E14, &mmCOMPUTE_VMID[0], sizeof(mmCOMPUTE_VMID)/sizeof(mmCOMPUTE_VMID[0]), 0, 0 },
+	{ "mmCOMPUTE_RESOURCE_LIMITS", REG_MMIO, 0x2E15, &mmCOMPUTE_RESOURCE_LIMITS[0], sizeof(mmCOMPUTE_RESOURCE_LIMITS)/sizeof(mmCOMPUTE_RESOURCE_LIMITS[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE0", REG_MMIO, 0x2E16, &mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE1", REG_MMIO, 0x2E17, &mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0]), 0, 0 },
+	{ "mmCOMPUTE_TMPRING_SIZE", REG_MMIO, 0x2E18, &mmCOMPUTE_TMPRING_SIZE[0], sizeof(mmCOMPUTE_TMPRING_SIZE)/sizeof(mmCOMPUTE_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_0", REG_MMIO, 0x2E40, &mmCOMPUTE_USER_DATA_0[0], sizeof(mmCOMPUTE_USER_DATA_0)/sizeof(mmCOMPUTE_USER_DATA_0[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_1", REG_MMIO, 0x2E41, &mmCOMPUTE_USER_DATA_1[0], sizeof(mmCOMPUTE_USER_DATA_1)/sizeof(mmCOMPUTE_USER_DATA_1[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_2", REG_MMIO, 0x2E42, &mmCOMPUTE_USER_DATA_2[0], sizeof(mmCOMPUTE_USER_DATA_2)/sizeof(mmCOMPUTE_USER_DATA_2[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_3", REG_MMIO, 0x2E43, &mmCOMPUTE_USER_DATA_3[0], sizeof(mmCOMPUTE_USER_DATA_3)/sizeof(mmCOMPUTE_USER_DATA_3[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_4", REG_MMIO, 0x2E44, &mmCOMPUTE_USER_DATA_4[0], sizeof(mmCOMPUTE_USER_DATA_4)/sizeof(mmCOMPUTE_USER_DATA_4[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_5", REG_MMIO, 0x2E45, &mmCOMPUTE_USER_DATA_5[0], sizeof(mmCOMPUTE_USER_DATA_5)/sizeof(mmCOMPUTE_USER_DATA_5[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_6", REG_MMIO, 0x2E46, &mmCOMPUTE_USER_DATA_6[0], sizeof(mmCOMPUTE_USER_DATA_6)/sizeof(mmCOMPUTE_USER_DATA_6[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_7", REG_MMIO, 0x2E47, &mmCOMPUTE_USER_DATA_7[0], sizeof(mmCOMPUTE_USER_DATA_7)/sizeof(mmCOMPUTE_USER_DATA_7[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_8", REG_MMIO, 0x2E48, &mmCOMPUTE_USER_DATA_8[0], sizeof(mmCOMPUTE_USER_DATA_8)/sizeof(mmCOMPUTE_USER_DATA_8[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_9", REG_MMIO, 0x2E49, &mmCOMPUTE_USER_DATA_9[0], sizeof(mmCOMPUTE_USER_DATA_9)/sizeof(mmCOMPUTE_USER_DATA_9[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_10", REG_MMIO, 0x2E4A, &mmCOMPUTE_USER_DATA_10[0], sizeof(mmCOMPUTE_USER_DATA_10)/sizeof(mmCOMPUTE_USER_DATA_10[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_11", REG_MMIO, 0x2E4B, &mmCOMPUTE_USER_DATA_11[0], sizeof(mmCOMPUTE_USER_DATA_11)/sizeof(mmCOMPUTE_USER_DATA_11[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_12", REG_MMIO, 0x2E4C, &mmCOMPUTE_USER_DATA_12[0], sizeof(mmCOMPUTE_USER_DATA_12)/sizeof(mmCOMPUTE_USER_DATA_12[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_13", REG_MMIO, 0x2E4D, &mmCOMPUTE_USER_DATA_13[0], sizeof(mmCOMPUTE_USER_DATA_13)/sizeof(mmCOMPUTE_USER_DATA_13[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_14", REG_MMIO, 0x2E4E, &mmCOMPUTE_USER_DATA_14[0], sizeof(mmCOMPUTE_USER_DATA_14)/sizeof(mmCOMPUTE_USER_DATA_14[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_15", REG_MMIO, 0x2E4F, &mmCOMPUTE_USER_DATA_15[0], sizeof(mmCOMPUTE_USER_DATA_15)/sizeof(mmCOMPUTE_USER_DATA_15[0]), 0, 0 },
+	{ "mmGRBM_CAM_INDEX", REG_MMIO, 0x3000, &mmGRBM_CAM_INDEX[0], sizeof(mmGRBM_CAM_INDEX)/sizeof(mmGRBM_CAM_INDEX[0]), 0, 0 },
+	{ "mmGRBM_CAM_DATA", REG_MMIO, 0x3001, &mmGRBM_CAM_DATA[0], sizeof(mmGRBM_CAM_DATA)/sizeof(mmGRBM_CAM_DATA[0]), 0, 0 },
+	{ "mmCP_RB0_BASE", REG_MMIO, 0x3040, &mmCP_RB0_BASE[0], sizeof(mmCP_RB0_BASE)/sizeof(mmCP_RB0_BASE[0]), 0, 0 },
+	{ "mmCP_RB0_CNTL", REG_MMIO, 0x3041, &mmCP_RB0_CNTL[0], sizeof(mmCP_RB0_CNTL)/sizeof(mmCP_RB0_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_WR", REG_MMIO, 0x3042, &mmCP_RB_RPTR_WR[0], sizeof(mmCP_RB_RPTR_WR)/sizeof(mmCP_RB_RPTR_WR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB0_RPTR_ADDR[0], sizeof(mmCP_RB0_RPTR_ADDR)/sizeof(mmCP_RB0_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB0_RPTR_ADDR_HI[0], sizeof(mmCP_RB0_RPTR_ADDR_HI)/sizeof(mmCP_RB0_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB0_WPTR", REG_MMIO, 0x3045, &mmCP_RB0_WPTR[0], sizeof(mmCP_RB0_WPTR)/sizeof(mmCP_RB0_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3046, &mmCP_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_LO)/sizeof(mmCP_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3047, &mmCP_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_HI)/sizeof(mmCP_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmGC_PRIV_MODE", REG_MMIO, 0x3048, NULL, 0, 0, 0 },
+	{ "mmCP_INT_CNTL", REG_MMIO, 0x3049, &mmCP_INT_CNTL[0], sizeof(mmCP_INT_CNTL)/sizeof(mmCP_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_INT_STATUS", REG_MMIO, 0x304A, &mmCP_INT_STATUS[0], sizeof(mmCP_INT_STATUS)/sizeof(mmCP_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_RING_PRIORITY_CNTS", REG_MMIO, 0x304C, &mmCP_RING_PRIORITY_CNTS[0], sizeof(mmCP_RING_PRIORITY_CNTS)/sizeof(mmCP_RING_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_RING0_PRIORITY", REG_MMIO, 0x304D, &mmCP_RING0_PRIORITY[0], sizeof(mmCP_RING0_PRIORITY)/sizeof(mmCP_RING0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING1_PRIORITY", REG_MMIO, 0x304E, &mmCP_RING1_PRIORITY[0], sizeof(mmCP_RING1_PRIORITY)/sizeof(mmCP_RING1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING2_PRIORITY", REG_MMIO, 0x304F, &mmCP_RING2_PRIORITY[0], sizeof(mmCP_RING2_PRIORITY)/sizeof(mmCP_RING2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RB_VMID", REG_MMIO, 0x3051, &mmCP_RB_VMID[0], sizeof(mmCP_RB_VMID)/sizeof(mmCP_RB_VMID[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_ADDR", REG_MMIO, 0x3054, &mmCP_PFP_UCODE_ADDR[0], sizeof(mmCP_PFP_UCODE_ADDR)/sizeof(mmCP_PFP_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_DATA", REG_MMIO, 0x3055, &mmCP_PFP_UCODE_DATA[0], sizeof(mmCP_PFP_UCODE_DATA)/sizeof(mmCP_PFP_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_ME_RAM_RADDR", REG_MMIO, 0x3056, &mmCP_ME_RAM_RADDR[0], sizeof(mmCP_ME_RAM_RADDR)/sizeof(mmCP_ME_RAM_RADDR[0]), 0, 0 },
+	{ "mmCP_ME_RAM_WADDR", REG_MMIO, 0x3057, &mmCP_ME_RAM_WADDR[0], sizeof(mmCP_ME_RAM_WADDR)/sizeof(mmCP_ME_RAM_WADDR[0]), 0, 0 },
+	{ "mmCP_ME_RAM_DATA", REG_MMIO, 0x3058, &mmCP_ME_RAM_DATA[0], sizeof(mmCP_ME_RAM_DATA)/sizeof(mmCP_ME_RAM_DATA[0]), 0, 0 },
+	{ "mmCGTT_CP_CLK_CTRL", REG_MMIO, 0x3059, &mmCGTT_CP_CLK_CTRL[0], sizeof(mmCGTT_CP_CLK_CTRL)/sizeof(mmCGTT_CP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_ADDR", REG_MMIO, 0x305A, &mmCP_CE_UCODE_ADDR[0], sizeof(mmCP_CE_UCODE_ADDR)/sizeof(mmCP_CE_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_DATA", REG_MMIO, 0x305B, &mmCP_CE_UCODE_DATA[0], sizeof(mmCP_CE_UCODE_DATA)/sizeof(mmCP_CE_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_RB1_BASE", REG_MMIO, 0x3060, &mmCP_RB1_BASE[0], sizeof(mmCP_RB1_BASE)/sizeof(mmCP_RB1_BASE[0]), 0, 0 },
+	{ "mmCP_RB1_CNTL", REG_MMIO, 0x3061, &mmCP_RB1_CNTL[0], sizeof(mmCP_RB1_CNTL)/sizeof(mmCP_RB1_CNTL[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR", REG_MMIO, 0x3062, &mmCP_RB1_RPTR_ADDR[0], sizeof(mmCP_RB1_RPTR_ADDR)/sizeof(mmCP_RB1_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR_HI", REG_MMIO, 0x3063, &mmCP_RB1_RPTR_ADDR_HI[0], sizeof(mmCP_RB1_RPTR_ADDR_HI)/sizeof(mmCP_RB1_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB1_WPTR", REG_MMIO, 0x3064, &mmCP_RB1_WPTR[0], sizeof(mmCP_RB1_WPTR)/sizeof(mmCP_RB1_WPTR[0]), 0, 0 },
+	{ "mmCP_RB2_BASE", REG_MMIO, 0x3065, &mmCP_RB2_BASE[0], sizeof(mmCP_RB2_BASE)/sizeof(mmCP_RB2_BASE[0]), 0, 0 },
+	{ "mmCP_RB2_CNTL", REG_MMIO, 0x3066, &mmCP_RB2_CNTL[0], sizeof(mmCP_RB2_CNTL)/sizeof(mmCP_RB2_CNTL[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR", REG_MMIO, 0x3067, &mmCP_RB2_RPTR_ADDR[0], sizeof(mmCP_RB2_RPTR_ADDR)/sizeof(mmCP_RB2_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR_HI", REG_MMIO, 0x3068, &mmCP_RB2_RPTR_ADDR_HI[0], sizeof(mmCP_RB2_RPTR_ADDR_HI)/sizeof(mmCP_RB2_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB2_WPTR", REG_MMIO, 0x3069, &mmCP_RB2_WPTR[0], sizeof(mmCP_RB2_WPTR)/sizeof(mmCP_RB2_WPTR[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING0", REG_MMIO, 0x306A, &mmCP_INT_CNTL_RING0[0], sizeof(mmCP_INT_CNTL_RING0)/sizeof(mmCP_INT_CNTL_RING0[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING1", REG_MMIO, 0x306B, &mmCP_INT_CNTL_RING1[0], sizeof(mmCP_INT_CNTL_RING1)/sizeof(mmCP_INT_CNTL_RING1[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING2", REG_MMIO, 0x306C, &mmCP_INT_CNTL_RING2[0], sizeof(mmCP_INT_CNTL_RING2)/sizeof(mmCP_INT_CNTL_RING2[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING0", REG_MMIO, 0x306D, &mmCP_INT_STATUS_RING0[0], sizeof(mmCP_INT_STATUS_RING0)/sizeof(mmCP_INT_STATUS_RING0[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING1", REG_MMIO, 0x306E, &mmCP_INT_STATUS_RING1[0], sizeof(mmCP_INT_STATUS_RING1)/sizeof(mmCP_INT_STATUS_RING1[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING2", REG_MMIO, 0x306F, &mmCP_INT_STATUS_RING2[0], sizeof(mmCP_INT_STATUS_RING2)/sizeof(mmCP_INT_STATUS_RING2[0]), 0, 0 },
+	{ "mmCP_PWR_CNTL", REG_MMIO, 0x3078, &mmCP_PWR_CNTL[0], sizeof(mmCP_PWR_CNTL)/sizeof(mmCP_PWR_CNTL[0]), 0, 0 },
+	{ "mmCP_MEM_SLP_CNTL", REG_MMIO, 0x3079, &mmCP_MEM_SLP_CNTL[0], sizeof(mmCP_MEM_SLP_CNTL)/sizeof(mmCP_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE", REG_MMIO, 0x307A, &mmCP_ECC_FIRSTOCCURRENCE[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE)/sizeof(mmCP_ECC_FIRSTOCCURRENCE[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING0", REG_MMIO, 0x307B, &mmCP_ECC_FIRSTOCCURRENCE_RING0[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING1", REG_MMIO, 0x307C, &mmCP_ECC_FIRSTOCCURRENCE_RING1[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING2", REG_MMIO, 0x307D, &mmCP_ECC_FIRSTOCCURRENCE_RING2[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2[0]), 0, 0 },
+	{ "mmGB_EDC_MODE", REG_MMIO, 0x307E, &mmGB_EDC_MODE[0], sizeof(mmGB_EDC_MODE)/sizeof(mmGB_EDC_MODE[0]), 0, 0 },
+	{ "mmCP_DEBUG", REG_MMIO, 0x307F, NULL, 0, 0, 0 },
+	{ "mmRLC_CNTL", REG_MMIO, 0x30C0, &mmRLC_CNTL[0], sizeof(mmRLC_CNTL)/sizeof(mmRLC_CNTL[0]), 0, 0 },
+	{ "mmRLC_RL_BASE", REG_MMIO, 0x30C1, NULL, 0, 0, 0 },
+	{ "mmRLC_RL_SIZE", REG_MMIO, 0x30C2, NULL, 0, 0, 0 },
+	{ "mmRLC_LB_CNTL", REG_MMIO, 0x30C3, &mmRLC_LB_CNTL[0], sizeof(mmRLC_LB_CNTL)/sizeof(mmRLC_LB_CNTL[0]), 0, 0 },
+	{ "mmRLC_SAVE_AND_RESTORE_BASE", REG_MMIO, 0x30C4, &mmRLC_SAVE_AND_RESTORE_BASE[0], sizeof(mmRLC_SAVE_AND_RESTORE_BASE)/sizeof(mmRLC_SAVE_AND_RESTORE_BASE[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_MAX", REG_MMIO, 0x30C5, &mmRLC_LB_CNTR_MAX[0], sizeof(mmRLC_LB_CNTR_MAX)/sizeof(mmRLC_LB_CNTR_MAX[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_INIT", REG_MMIO, 0x30C6, &mmRLC_LB_CNTR_INIT[0], sizeof(mmRLC_LB_CNTR_INIT)/sizeof(mmRLC_LB_CNTR_INIT[0]), 0, 0 },
+	{ "mmRLC_DRIVER_CPDMA_STATUS", REG_MMIO, 0x30C7, &mmRLC_DRIVER_CPDMA_STATUS[0], sizeof(mmRLC_DRIVER_CPDMA_STATUS)/sizeof(mmRLC_DRIVER_CPDMA_STATUS[0]), 0, 0 },
+	{ "mmRLC_CLEAR_STATE_RESTORE_BASE", REG_MMIO, 0x30C8, NULL, 0, 0, 0 },
+	{ "mmRLC_DEBUG_SELECT", REG_MMIO, 0x30C9, &mmRLC_DEBUG_SELECT[0], sizeof(mmRLC_DEBUG_SELECT)/sizeof(mmRLC_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_DEBUG", REG_MMIO, 0x30CA, &mmRLC_DEBUG[0], sizeof(mmRLC_DEBUG)/sizeof(mmRLC_DEBUG[0]), 0, 0 },
+	{ "mmRLC_UCODE_ADDR", REG_MMIO, 0x30CB, NULL, 0, 0, 0 },
+	{ "mmRLC_UCODE_DATA", REG_MMIO, 0x30CC, NULL, 0, 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_LSB", REG_MMIO, 0x30CE, &mmRLC_GPU_CLOCK_COUNT_LSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_LSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_LSB[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_MSB", REG_MMIO, 0x30CF, &mmRLC_GPU_CLOCK_COUNT_MSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_MSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_MSB[0]), 0, 0 },
+	{ "mmRLC_CAPTURE_GPU_CLOCK_COUNT", REG_MMIO, 0x30D0, &mmRLC_CAPTURE_GPU_CLOCK_COUNT[0], sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT)/sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT[0]), 0, 0 },
+	{ "mmRLC_MC_CNTL", REG_MMIO, 0x30D1, &mmRLC_MC_CNTL[0], sizeof(mmRLC_MC_CNTL)/sizeof(mmRLC_MC_CNTL[0]), 0, 0 },
+	{ "mmRLC_UCODE_CNTL", REG_MMIO, 0x30D2, &mmRLC_UCODE_CNTL[0], sizeof(mmRLC_UCODE_CNTL)/sizeof(mmRLC_UCODE_CNTL[0]), 0, 0 },
+	{ "mmRLC_STAT", REG_MMIO, 0x30D3, &mmRLC_STAT[0], sizeof(mmRLC_STAT)/sizeof(mmRLC_STAT[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32_RES_SEL", REG_MMIO, 0x30D4, &mmRLC_GPU_CLOCK_32_RES_SEL[0], sizeof(mmRLC_GPU_CLOCK_32_RES_SEL)/sizeof(mmRLC_GPU_CLOCK_32_RES_SEL[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32", REG_MMIO, 0x30D5, &mmRLC_GPU_CLOCK_32[0], sizeof(mmRLC_GPU_CLOCK_32)/sizeof(mmRLC_GPU_CLOCK_32[0]), 0, 0 },
+	{ "mmRLC_SOFT_RESET_GPU", REG_MMIO, 0x30D6, &mmRLC_SOFT_RESET_GPU[0], sizeof(mmRLC_SOFT_RESET_GPU)/sizeof(mmRLC_SOFT_RESET_GPU[0]), 0, 0 },
+	{ "mmRLC_PG_CNTL", REG_MMIO, 0x30D7, &mmRLC_PG_CNTL[0], sizeof(mmRLC_PG_CNTL)/sizeof(mmRLC_PG_CNTL[0]), 0, 0 },
+	{ "mmRLC_MEM_SLP_CNTL", REG_MMIO, 0x30D8, &mmRLC_MEM_SLP_CNTL[0], sizeof(mmRLC_MEM_SLP_CNTL)/sizeof(mmRLC_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmRLC_PERFMON_CNTL", REG_MMIO, 0x30D9, &mmRLC_PERFMON_CNTL[0], sizeof(mmRLC_PERFMON_CNTL)/sizeof(mmRLC_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_SELECT", REG_MMIO, 0x30DA, &mmRLC_PERFCOUNTER0_SELECT[0], sizeof(mmRLC_PERFCOUNTER0_SELECT)/sizeof(mmRLC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_LO", REG_MMIO, 0x30DB, &mmRLC_PERFCOUNTER0_LO[0], sizeof(mmRLC_PERFCOUNTER0_LO)/sizeof(mmRLC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_HI", REG_MMIO, 0x30DC, &mmRLC_PERFCOUNTER0_HI[0], sizeof(mmRLC_PERFCOUNTER0_HI)/sizeof(mmRLC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_SELECT", REG_MMIO, 0x30DD, &mmRLC_PERFCOUNTER1_SELECT[0], sizeof(mmRLC_PERFCOUNTER1_SELECT)/sizeof(mmRLC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_LO", REG_MMIO, 0x30DE, &mmRLC_PERFCOUNTER1_LO[0], sizeof(mmRLC_PERFCOUNTER1_LO)/sizeof(mmRLC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_HI", REG_MMIO, 0x30DF, &mmRLC_PERFCOUNTER1_HI[0], sizeof(mmRLC_PERFCOUNTER1_HI)/sizeof(mmRLC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCGTT_RLC_CLK_CTRL", REG_MMIO, 0x30E0, &mmCGTT_RLC_CLK_CTRL[0], sizeof(mmCGTT_RLC_CLK_CTRL)/sizeof(mmCGTT_RLC_CLK_CTRL[0]), 0, 0 },
+	{ "mmRLC_LOAD_BALANCE_CNTR", REG_MMIO, 0x30F6, &mmRLC_LOAD_BALANCE_CNTR[0], sizeof(mmRLC_LOAD_BALANCE_CNTR)/sizeof(mmRLC_LOAD_BALANCE_CNTR[0]), 0, 0 },
+	{ "mmRLC_CGTT_MGCG_OVERRIDE", REG_MMIO, 0x3100, &mmRLC_CGTT_MGCG_OVERRIDE[0], sizeof(mmRLC_CGTT_MGCG_OVERRIDE)/sizeof(mmRLC_CGTT_MGCG_OVERRIDE[0]), 0, 0 },
+	{ "mmRLC_CGCG_CGLS_CTRL", REG_MMIO, 0x3101, &mmRLC_CGCG_CGLS_CTRL[0], sizeof(mmRLC_CGCG_CGLS_CTRL)/sizeof(mmRLC_CGCG_CGLS_CTRL[0]), 0, 0 },
+	{ "mmRLC_CGCG_RAMP_CTRL", REG_MMIO, 0x3102, &mmRLC_CGCG_RAMP_CTRL[0], sizeof(mmRLC_CGCG_RAMP_CTRL)/sizeof(mmRLC_CGCG_RAMP_CTRL[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_STATUS", REG_MMIO, 0x3103, &mmRLC_DYN_PG_STATUS[0], sizeof(mmRLC_DYN_PG_STATUS)/sizeof(mmRLC_DYN_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_REQUEST", REG_MMIO, 0x3104, &mmRLC_DYN_PG_REQUEST[0], sizeof(mmRLC_DYN_PG_REQUEST)/sizeof(mmRLC_DYN_PG_REQUEST[0]), 0, 0 },
+	{ "mmRLC_TTOP_D", REG_MMIO, 0x3105, NULL, 0, 0, 0 },
+	{ "mmRLC_CU_STATUS", REG_MMIO, 0x3106, &mmRLC_CU_STATUS[0], sizeof(mmRLC_CU_STATUS)/sizeof(mmRLC_CU_STATUS[0]), 0, 0 },
+	{ "mmRLC_LB_INIT_CU_MASK", REG_MMIO, 0x3107, &mmRLC_LB_INIT_CU_MASK[0], sizeof(mmRLC_LB_INIT_CU_MASK)/sizeof(mmRLC_LB_INIT_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_ALWAYS_ACTIVE_CU_MASK", REG_MMIO, 0x3108, &mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0], sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK)/sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_PARAMS", REG_MMIO, 0x3109, &mmRLC_LB_PARAMS[0], sizeof(mmRLC_LB_PARAMS)/sizeof(mmRLC_LB_PARAMS[0]), 0, 0 },
+	{ "mmRLC_THREAD1_DELAY", REG_MMIO, 0x310A, &mmRLC_THREAD1_DELAY[0], sizeof(mmRLC_THREAD1_DELAY)/sizeof(mmRLC_THREAD1_DELAY[0]), 0, 0 },
+	{ "mmRLC_PG_ALWAYS_ON_CU_MASK", REG_MMIO, 0x310B, &mmRLC_PG_ALWAYS_ON_CU_MASK[0], sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK)/sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_PG_AO_CU_MASK", REG_MMIO, 0x310B, NULL, 0, 0, 0 },
+	{ "mmRLC_MAX_PG_CU", REG_MMIO, 0x310C, &mmRLC_MAX_PG_CU[0], sizeof(mmRLC_MAX_PG_CU)/sizeof(mmRLC_MAX_PG_CU[0]), 0, 0 },
+	{ "mmRLC_AUTO_PG_CTRL", REG_MMIO, 0x310D, &mmRLC_AUTO_PG_CTRL[0], sizeof(mmRLC_AUTO_PG_CTRL)/sizeof(mmRLC_AUTO_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_GRBM_REG_SAVE_CTRL", REG_MMIO, 0x310E, &mmRLC_SMU_GRBM_REG_SAVE_CTRL[0], sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL)/sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_PG_CTRL", REG_MMIO, 0x310F, &mmRLC_SMU_PG_CTRL[0], sizeof(mmRLC_SMU_PG_CTRL)/sizeof(mmRLC_SMU_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_PG_WAKE_UP_CTRL", REG_MMIO, 0x3110, &mmRLC_SMU_PG_WAKE_UP_CTRL[0], sizeof(mmRLC_SMU_PG_WAKE_UP_CTRL)/sizeof(mmRLC_SMU_PG_WAKE_UP_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_MASTER_INDEX", REG_MMIO, 0x3111, &mmRLC_SERDES_RD_MASTER_INDEX[0], sizeof(mmRLC_SERDES_RD_MASTER_INDEX)/sizeof(mmRLC_SERDES_RD_MASTER_INDEX[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_0", REG_MMIO, 0x3112, &mmRLC_SERDES_RD_DATA_0[0], sizeof(mmRLC_SERDES_RD_DATA_0)/sizeof(mmRLC_SERDES_RD_DATA_0[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_1", REG_MMIO, 0x3113, &mmRLC_SERDES_RD_DATA_1[0], sizeof(mmRLC_SERDES_RD_DATA_1)/sizeof(mmRLC_SERDES_RD_DATA_1[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_2", REG_MMIO, 0x3114, &mmRLC_SERDES_RD_DATA_2[0], sizeof(mmRLC_SERDES_RD_DATA_2)/sizeof(mmRLC_SERDES_RD_DATA_2[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_MASTER_MASK_0", REG_MMIO, 0x3115, NULL, 0, 0, 0 },
+	{ "mmRLC_SERDES_WR_MASTER_MASK_1", REG_MMIO, 0x3116, NULL, 0, 0, 0 },
+	{ "mmRLC_SERDES_WR_CTRL", REG_MMIO, 0x3117, &mmRLC_SERDES_WR_CTRL[0], sizeof(mmRLC_SERDES_WR_CTRL)/sizeof(mmRLC_SERDES_WR_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_DATA", REG_MMIO, 0x3118, &mmRLC_SERDES_WR_DATA[0], sizeof(mmRLC_SERDES_WR_DATA)/sizeof(mmRLC_SERDES_WR_DATA[0]), 0, 0 },
+	{ "mmRLC_SERDES_MASTER_BUSY_0", REG_MMIO, 0x3119, NULL, 0, 0, 0 },
+	{ "mmRLC_SERDES_MASTER_BUSY_1", REG_MMIO, 0x311A, NULL, 0, 0, 0 },
+	{ "mmRLC_GCPM_GENERAL_3", REG_MMIO, 0x311E, NULL, 0, 0, 0 },
+	{ "mmRAS_SIGNATURE_CONTROL", REG_MMIO, 0x3380, &mmRAS_SIGNATURE_CONTROL[0], sizeof(mmRAS_SIGNATURE_CONTROL)/sizeof(mmRAS_SIGNATURE_CONTROL[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_MASK", REG_MMIO, 0x3381, &mmRAS_SIGNATURE_MASK[0], sizeof(mmRAS_SIGNATURE_MASK)/sizeof(mmRAS_SIGNATURE_MASK[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE0", REG_MMIO, 0x3382, &mmRAS_SX_SIGNATURE0[0], sizeof(mmRAS_SX_SIGNATURE0)/sizeof(mmRAS_SX_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE1", REG_MMIO, 0x3383, &mmRAS_SX_SIGNATURE1[0], sizeof(mmRAS_SX_SIGNATURE1)/sizeof(mmRAS_SX_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE2", REG_MMIO, 0x3384, &mmRAS_SX_SIGNATURE2[0], sizeof(mmRAS_SX_SIGNATURE2)/sizeof(mmRAS_SX_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE3", REG_MMIO, 0x3385, &mmRAS_SX_SIGNATURE3[0], sizeof(mmRAS_SX_SIGNATURE3)/sizeof(mmRAS_SX_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_DB_SIGNATURE0", REG_MMIO, 0x338B, &mmRAS_DB_SIGNATURE0[0], sizeof(mmRAS_DB_SIGNATURE0)/sizeof(mmRAS_DB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_PA_SIGNATURE0", REG_MMIO, 0x338C, &mmRAS_PA_SIGNATURE0[0], sizeof(mmRAS_PA_SIGNATURE0)/sizeof(mmRAS_PA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_VGT_SIGNATURE0", REG_MMIO, 0x338D, &mmRAS_VGT_SIGNATURE0[0], sizeof(mmRAS_VGT_SIGNATURE0)/sizeof(mmRAS_VGT_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SQ_SIGNATURE0", REG_MMIO, 0x338E, &mmRAS_SQ_SIGNATURE0[0], sizeof(mmRAS_SQ_SIGNATURE0)/sizeof(mmRAS_SQ_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE0", REG_MMIO, 0x338F, &mmRAS_SC_SIGNATURE0[0], sizeof(mmRAS_SC_SIGNATURE0)/sizeof(mmRAS_SC_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE1", REG_MMIO, 0x3390, &mmRAS_SC_SIGNATURE1[0], sizeof(mmRAS_SC_SIGNATURE1)/sizeof(mmRAS_SC_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE2", REG_MMIO, 0x3391, &mmRAS_SC_SIGNATURE2[0], sizeof(mmRAS_SC_SIGNATURE2)/sizeof(mmRAS_SC_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE3", REG_MMIO, 0x3392, &mmRAS_SC_SIGNATURE3[0], sizeof(mmRAS_SC_SIGNATURE3)/sizeof(mmRAS_SC_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE4", REG_MMIO, 0x3393, &mmRAS_SC_SIGNATURE4[0], sizeof(mmRAS_SC_SIGNATURE4)/sizeof(mmRAS_SC_SIGNATURE4[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE5", REG_MMIO, 0x3394, &mmRAS_SC_SIGNATURE5[0], sizeof(mmRAS_SC_SIGNATURE5)/sizeof(mmRAS_SC_SIGNATURE5[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE6", REG_MMIO, 0x3395, &mmRAS_SC_SIGNATURE6[0], sizeof(mmRAS_SC_SIGNATURE6)/sizeof(mmRAS_SC_SIGNATURE6[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE7", REG_MMIO, 0x3396, &mmRAS_SC_SIGNATURE7[0], sizeof(mmRAS_SC_SIGNATURE7)/sizeof(mmRAS_SC_SIGNATURE7[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE0", REG_MMIO, 0x3397, &mmRAS_IA_SIGNATURE0[0], sizeof(mmRAS_IA_SIGNATURE0)/sizeof(mmRAS_IA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE1", REG_MMIO, 0x3398, &mmRAS_IA_SIGNATURE1[0], sizeof(mmRAS_IA_SIGNATURE1)/sizeof(mmRAS_IA_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE0", REG_MMIO, 0x3399, &mmRAS_SPI_SIGNATURE0[0], sizeof(mmRAS_SPI_SIGNATURE0)/sizeof(mmRAS_SPI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE1", REG_MMIO, 0x339A, &mmRAS_SPI_SIGNATURE1[0], sizeof(mmRAS_SPI_SIGNATURE1)/sizeof(mmRAS_SPI_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_TA_SIGNATURE0", REG_MMIO, 0x339B, &mmRAS_TA_SIGNATURE0[0], sizeof(mmRAS_TA_SIGNATURE0)/sizeof(mmRAS_TA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_TD_SIGNATURE0", REG_MMIO, 0x339C, &mmRAS_TD_SIGNATURE0[0], sizeof(mmRAS_TD_SIGNATURE0)/sizeof(mmRAS_TD_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_CB_SIGNATURE0", REG_MMIO, 0x339D, &mmRAS_CB_SIGNATURE0[0], sizeof(mmRAS_CB_SIGNATURE0)/sizeof(mmRAS_CB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE0", REG_MMIO, 0x339E, &mmRAS_BCI_SIGNATURE0[0], sizeof(mmRAS_BCI_SIGNATURE0)/sizeof(mmRAS_BCI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE1", REG_MMIO, 0x339F, &mmRAS_BCI_SIGNATURE1[0], sizeof(mmRAS_BCI_SIGNATURE1)/sizeof(mmRAS_BCI_SIGNATURE1[0]), 0, 0 },
+	{ "mmDB_RENDER_CONTROL", REG_MMIO, 0xA000, &mmDB_RENDER_CONTROL[0], sizeof(mmDB_RENDER_CONTROL)/sizeof(mmDB_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmDB_COUNT_CONTROL", REG_MMIO, 0xA001, &mmDB_COUNT_CONTROL[0], sizeof(mmDB_COUNT_CONTROL)/sizeof(mmDB_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmDB_DEPTH_VIEW", REG_MMIO, 0xA002, &mmDB_DEPTH_VIEW[0], sizeof(mmDB_DEPTH_VIEW)/sizeof(mmDB_DEPTH_VIEW[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE", REG_MMIO, 0xA003, &mmDB_RENDER_OVERRIDE[0], sizeof(mmDB_RENDER_OVERRIDE)/sizeof(mmDB_RENDER_OVERRIDE[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE2", REG_MMIO, 0xA004, &mmDB_RENDER_OVERRIDE2[0], sizeof(mmDB_RENDER_OVERRIDE2)/sizeof(mmDB_RENDER_OVERRIDE2[0]), 0, 0 },
+	{ "mmDB_HTILE_DATA_BASE", REG_MMIO, 0xA005, &mmDB_HTILE_DATA_BASE[0], sizeof(mmDB_HTILE_DATA_BASE)/sizeof(mmDB_HTILE_DATA_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MIN", REG_MMIO, 0xA008, &mmDB_DEPTH_BOUNDS_MIN[0], sizeof(mmDB_DEPTH_BOUNDS_MIN)/sizeof(mmDB_DEPTH_BOUNDS_MIN[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MAX", REG_MMIO, 0xA009, &mmDB_DEPTH_BOUNDS_MAX[0], sizeof(mmDB_DEPTH_BOUNDS_MAX)/sizeof(mmDB_DEPTH_BOUNDS_MAX[0]), 0, 0 },
+	{ "mmDB_STENCIL_CLEAR", REG_MMIO, 0xA00A, &mmDB_STENCIL_CLEAR[0], sizeof(mmDB_STENCIL_CLEAR)/sizeof(mmDB_STENCIL_CLEAR[0]), 0, 0 },
+	{ "mmDB_DEPTH_CLEAR", REG_MMIO, 0xA00B, &mmDB_DEPTH_CLEAR[0], sizeof(mmDB_DEPTH_CLEAR)/sizeof(mmDB_DEPTH_CLEAR[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_TL", REG_MMIO, 0xA00C, &mmPA_SC_SCREEN_SCISSOR_TL[0], sizeof(mmPA_SC_SCREEN_SCISSOR_TL)/sizeof(mmPA_SC_SCREEN_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_BR", REG_MMIO, 0xA00D, &mmPA_SC_SCREEN_SCISSOR_BR[0], sizeof(mmPA_SC_SCREEN_SCISSOR_BR)/sizeof(mmPA_SC_SCREEN_SCISSOR_BR[0]), 0, 0 },
+	{ "mmDB_DEPTH_INFO", REG_MMIO, 0xA00F, &mmDB_DEPTH_INFO[0], sizeof(mmDB_DEPTH_INFO)/sizeof(mmDB_DEPTH_INFO[0]), 0, 0 },
+	{ "mmDB_Z_INFO", REG_MMIO, 0xA010, &mmDB_Z_INFO[0], sizeof(mmDB_Z_INFO)/sizeof(mmDB_Z_INFO[0]), 0, 0 },
+	{ "mmDB_STENCIL_INFO", REG_MMIO, 0xA011, &mmDB_STENCIL_INFO[0], sizeof(mmDB_STENCIL_INFO)/sizeof(mmDB_STENCIL_INFO[0]), 0, 0 },
+	{ "mmDB_Z_READ_BASE", REG_MMIO, 0xA012, &mmDB_Z_READ_BASE[0], sizeof(mmDB_Z_READ_BASE)/sizeof(mmDB_Z_READ_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_READ_BASE", REG_MMIO, 0xA013, &mmDB_STENCIL_READ_BASE[0], sizeof(mmDB_STENCIL_READ_BASE)/sizeof(mmDB_STENCIL_READ_BASE[0]), 0, 0 },
+	{ "mmDB_Z_WRITE_BASE", REG_MMIO, 0xA014, &mmDB_Z_WRITE_BASE[0], sizeof(mmDB_Z_WRITE_BASE)/sizeof(mmDB_Z_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_WRITE_BASE", REG_MMIO, 0xA015, &mmDB_STENCIL_WRITE_BASE[0], sizeof(mmDB_STENCIL_WRITE_BASE)/sizeof(mmDB_STENCIL_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SIZE", REG_MMIO, 0xA016, &mmDB_DEPTH_SIZE[0], sizeof(mmDB_DEPTH_SIZE)/sizeof(mmDB_DEPTH_SIZE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SLICE", REG_MMIO, 0xA017, &mmDB_DEPTH_SLICE[0], sizeof(mmDB_DEPTH_SLICE)/sizeof(mmDB_DEPTH_SLICE[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR", REG_MMIO, 0xA020, &mmTA_BC_BASE_ADDR[0], sizeof(mmTA_BC_BASE_ADDR)/sizeof(mmTA_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_2", REG_MMIO, 0xA07E, &mmCOHER_DEST_BASE_2[0], sizeof(mmCOHER_DEST_BASE_2)/sizeof(mmCOHER_DEST_BASE_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_3", REG_MMIO, 0xA07F, &mmCOHER_DEST_BASE_3[0], sizeof(mmCOHER_DEST_BASE_3)/sizeof(mmCOHER_DEST_BASE_3[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_OFFSET", REG_MMIO, 0xA080, &mmPA_SC_WINDOW_OFFSET[0], sizeof(mmPA_SC_WINDOW_OFFSET)/sizeof(mmPA_SC_WINDOW_OFFSET[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_TL", REG_MMIO, 0xA081, &mmPA_SC_WINDOW_SCISSOR_TL[0], sizeof(mmPA_SC_WINDOW_SCISSOR_TL)/sizeof(mmPA_SC_WINDOW_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_BR", REG_MMIO, 0xA082, &mmPA_SC_WINDOW_SCISSOR_BR[0], sizeof(mmPA_SC_WINDOW_SCISSOR_BR)/sizeof(mmPA_SC_WINDOW_SCISSOR_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_RULE", REG_MMIO, 0xA083, &mmPA_SC_CLIPRECT_RULE[0], sizeof(mmPA_SC_CLIPRECT_RULE)/sizeof(mmPA_SC_CLIPRECT_RULE[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_TL", REG_MMIO, 0xA084, &mmPA_SC_CLIPRECT_0_TL[0], sizeof(mmPA_SC_CLIPRECT_0_TL)/sizeof(mmPA_SC_CLIPRECT_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_BR", REG_MMIO, 0xA085, &mmPA_SC_CLIPRECT_0_BR[0], sizeof(mmPA_SC_CLIPRECT_0_BR)/sizeof(mmPA_SC_CLIPRECT_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_TL", REG_MMIO, 0xA086, &mmPA_SC_CLIPRECT_1_TL[0], sizeof(mmPA_SC_CLIPRECT_1_TL)/sizeof(mmPA_SC_CLIPRECT_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_BR", REG_MMIO, 0xA087, &mmPA_SC_CLIPRECT_1_BR[0], sizeof(mmPA_SC_CLIPRECT_1_BR)/sizeof(mmPA_SC_CLIPRECT_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_TL", REG_MMIO, 0xA088, &mmPA_SC_CLIPRECT_2_TL[0], sizeof(mmPA_SC_CLIPRECT_2_TL)/sizeof(mmPA_SC_CLIPRECT_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_BR", REG_MMIO, 0xA089, &mmPA_SC_CLIPRECT_2_BR[0], sizeof(mmPA_SC_CLIPRECT_2_BR)/sizeof(mmPA_SC_CLIPRECT_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_TL", REG_MMIO, 0xA08A, &mmPA_SC_CLIPRECT_3_TL[0], sizeof(mmPA_SC_CLIPRECT_3_TL)/sizeof(mmPA_SC_CLIPRECT_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_BR", REG_MMIO, 0xA08B, &mmPA_SC_CLIPRECT_3_BR[0], sizeof(mmPA_SC_CLIPRECT_3_BR)/sizeof(mmPA_SC_CLIPRECT_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_EDGERULE", REG_MMIO, 0xA08C, &mmPA_SC_EDGERULE[0], sizeof(mmPA_SC_EDGERULE)/sizeof(mmPA_SC_EDGERULE[0]), 0, 0 },
+	{ "mmPA_SU_HARDWARE_SCREEN_OFFSET", REG_MMIO, 0xA08D, &mmPA_SU_HARDWARE_SCREEN_OFFSET[0], sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET)/sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET[0]), 0, 0 },
+	{ "mmCB_TARGET_MASK", REG_MMIO, 0xA08E, &mmCB_TARGET_MASK[0], sizeof(mmCB_TARGET_MASK)/sizeof(mmCB_TARGET_MASK[0]), 0, 0 },
+	{ "mmCB_SHADER_MASK", REG_MMIO, 0xA08F, &mmCB_SHADER_MASK[0], sizeof(mmCB_SHADER_MASK)/sizeof(mmCB_SHADER_MASK[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_TL", REG_MMIO, 0xA090, &mmPA_SC_GENERIC_SCISSOR_TL[0], sizeof(mmPA_SC_GENERIC_SCISSOR_TL)/sizeof(mmPA_SC_GENERIC_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_BR", REG_MMIO, 0xA091, &mmPA_SC_GENERIC_SCISSOR_BR[0], sizeof(mmPA_SC_GENERIC_SCISSOR_BR)/sizeof(mmPA_SC_GENERIC_SCISSOR_BR[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_0", REG_MMIO, 0xA092, &mmCOHER_DEST_BASE_0[0], sizeof(mmCOHER_DEST_BASE_0)/sizeof(mmCOHER_DEST_BASE_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_1", REG_MMIO, 0xA093, &mmCOHER_DEST_BASE_1[0], sizeof(mmCOHER_DEST_BASE_1)/sizeof(mmCOHER_DEST_BASE_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_TL", REG_MMIO, 0xA094, &mmPA_SC_VPORT_SCISSOR_0_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_BR", REG_MMIO, 0xA095, &mmPA_SC_VPORT_SCISSOR_0_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_TL", REG_MMIO, 0xA096, &mmPA_SC_VPORT_SCISSOR_1_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_BR", REG_MMIO, 0xA097, &mmPA_SC_VPORT_SCISSOR_1_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_TL", REG_MMIO, 0xA098, &mmPA_SC_VPORT_SCISSOR_2_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_BR", REG_MMIO, 0xA099, &mmPA_SC_VPORT_SCISSOR_2_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_TL", REG_MMIO, 0xA09A, &mmPA_SC_VPORT_SCISSOR_3_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_BR", REG_MMIO, 0xA09B, &mmPA_SC_VPORT_SCISSOR_3_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_TL", REG_MMIO, 0xA09C, &mmPA_SC_VPORT_SCISSOR_4_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_4_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_BR", REG_MMIO, 0xA09D, &mmPA_SC_VPORT_SCISSOR_4_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_4_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_TL", REG_MMIO, 0xA09E, &mmPA_SC_VPORT_SCISSOR_5_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_5_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_BR", REG_MMIO, 0xA09F, &mmPA_SC_VPORT_SCISSOR_5_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_5_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_TL", REG_MMIO, 0xA0A0, &mmPA_SC_VPORT_SCISSOR_6_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_6_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_BR", REG_MMIO, 0xA0A1, &mmPA_SC_VPORT_SCISSOR_6_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_6_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_TL", REG_MMIO, 0xA0A2, &mmPA_SC_VPORT_SCISSOR_7_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_7_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_BR", REG_MMIO, 0xA0A3, &mmPA_SC_VPORT_SCISSOR_7_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_7_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_TL", REG_MMIO, 0xA0A4, &mmPA_SC_VPORT_SCISSOR_8_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_8_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_BR", REG_MMIO, 0xA0A5, &mmPA_SC_VPORT_SCISSOR_8_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_8_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_TL", REG_MMIO, 0xA0A6, &mmPA_SC_VPORT_SCISSOR_9_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_9_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_BR", REG_MMIO, 0xA0A7, &mmPA_SC_VPORT_SCISSOR_9_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_9_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_TL", REG_MMIO, 0xA0A8, &mmPA_SC_VPORT_SCISSOR_10_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_10_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_BR", REG_MMIO, 0xA0A9, &mmPA_SC_VPORT_SCISSOR_10_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_10_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_TL", REG_MMIO, 0xA0AA, &mmPA_SC_VPORT_SCISSOR_11_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_11_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_BR", REG_MMIO, 0xA0AB, &mmPA_SC_VPORT_SCISSOR_11_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_11_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_TL", REG_MMIO, 0xA0AC, &mmPA_SC_VPORT_SCISSOR_12_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_12_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_BR", REG_MMIO, 0xA0AD, &mmPA_SC_VPORT_SCISSOR_12_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_12_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_TL", REG_MMIO, 0xA0AE, &mmPA_SC_VPORT_SCISSOR_13_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_13_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_BR", REG_MMIO, 0xA0AF, &mmPA_SC_VPORT_SCISSOR_13_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_13_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_TL", REG_MMIO, 0xA0B0, &mmPA_SC_VPORT_SCISSOR_14_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_14_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_BR", REG_MMIO, 0xA0B1, &mmPA_SC_VPORT_SCISSOR_14_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_14_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_TL", REG_MMIO, 0xA0B2, &mmPA_SC_VPORT_SCISSOR_15_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_15_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_BR", REG_MMIO, 0xA0B3, &mmPA_SC_VPORT_SCISSOR_15_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_15_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_0", REG_MMIO, 0xA0B4, &mmPA_SC_VPORT_ZMIN_0[0], sizeof(mmPA_SC_VPORT_ZMIN_0)/sizeof(mmPA_SC_VPORT_ZMIN_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_0", REG_MMIO, 0xA0B5, &mmPA_SC_VPORT_ZMAX_0[0], sizeof(mmPA_SC_VPORT_ZMAX_0)/sizeof(mmPA_SC_VPORT_ZMAX_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_1", REG_MMIO, 0xA0B6, &mmPA_SC_VPORT_ZMIN_1[0], sizeof(mmPA_SC_VPORT_ZMIN_1)/sizeof(mmPA_SC_VPORT_ZMIN_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_1", REG_MMIO, 0xA0B7, &mmPA_SC_VPORT_ZMAX_1[0], sizeof(mmPA_SC_VPORT_ZMAX_1)/sizeof(mmPA_SC_VPORT_ZMAX_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_2", REG_MMIO, 0xA0B8, &mmPA_SC_VPORT_ZMIN_2[0], sizeof(mmPA_SC_VPORT_ZMIN_2)/sizeof(mmPA_SC_VPORT_ZMIN_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_2", REG_MMIO, 0xA0B9, &mmPA_SC_VPORT_ZMAX_2[0], sizeof(mmPA_SC_VPORT_ZMAX_2)/sizeof(mmPA_SC_VPORT_ZMAX_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_3", REG_MMIO, 0xA0BA, &mmPA_SC_VPORT_ZMIN_3[0], sizeof(mmPA_SC_VPORT_ZMIN_3)/sizeof(mmPA_SC_VPORT_ZMIN_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_3", REG_MMIO, 0xA0BB, &mmPA_SC_VPORT_ZMAX_3[0], sizeof(mmPA_SC_VPORT_ZMAX_3)/sizeof(mmPA_SC_VPORT_ZMAX_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_4", REG_MMIO, 0xA0BC, &mmPA_SC_VPORT_ZMIN_4[0], sizeof(mmPA_SC_VPORT_ZMIN_4)/sizeof(mmPA_SC_VPORT_ZMIN_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_4", REG_MMIO, 0xA0BD, &mmPA_SC_VPORT_ZMAX_4[0], sizeof(mmPA_SC_VPORT_ZMAX_4)/sizeof(mmPA_SC_VPORT_ZMAX_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_5", REG_MMIO, 0xA0BE, &mmPA_SC_VPORT_ZMIN_5[0], sizeof(mmPA_SC_VPORT_ZMIN_5)/sizeof(mmPA_SC_VPORT_ZMIN_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_5", REG_MMIO, 0xA0BF, &mmPA_SC_VPORT_ZMAX_5[0], sizeof(mmPA_SC_VPORT_ZMAX_5)/sizeof(mmPA_SC_VPORT_ZMAX_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_6", REG_MMIO, 0xA0C0, &mmPA_SC_VPORT_ZMIN_6[0], sizeof(mmPA_SC_VPORT_ZMIN_6)/sizeof(mmPA_SC_VPORT_ZMIN_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_6", REG_MMIO, 0xA0C1, &mmPA_SC_VPORT_ZMAX_6[0], sizeof(mmPA_SC_VPORT_ZMAX_6)/sizeof(mmPA_SC_VPORT_ZMAX_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_7", REG_MMIO, 0xA0C2, &mmPA_SC_VPORT_ZMIN_7[0], sizeof(mmPA_SC_VPORT_ZMIN_7)/sizeof(mmPA_SC_VPORT_ZMIN_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_7", REG_MMIO, 0xA0C3, &mmPA_SC_VPORT_ZMAX_7[0], sizeof(mmPA_SC_VPORT_ZMAX_7)/sizeof(mmPA_SC_VPORT_ZMAX_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_8", REG_MMIO, 0xA0C4, &mmPA_SC_VPORT_ZMIN_8[0], sizeof(mmPA_SC_VPORT_ZMIN_8)/sizeof(mmPA_SC_VPORT_ZMIN_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_8", REG_MMIO, 0xA0C5, &mmPA_SC_VPORT_ZMAX_8[0], sizeof(mmPA_SC_VPORT_ZMAX_8)/sizeof(mmPA_SC_VPORT_ZMAX_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_9", REG_MMIO, 0xA0C6, &mmPA_SC_VPORT_ZMIN_9[0], sizeof(mmPA_SC_VPORT_ZMIN_9)/sizeof(mmPA_SC_VPORT_ZMIN_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_9", REG_MMIO, 0xA0C7, &mmPA_SC_VPORT_ZMAX_9[0], sizeof(mmPA_SC_VPORT_ZMAX_9)/sizeof(mmPA_SC_VPORT_ZMAX_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_10", REG_MMIO, 0xA0C8, &mmPA_SC_VPORT_ZMIN_10[0], sizeof(mmPA_SC_VPORT_ZMIN_10)/sizeof(mmPA_SC_VPORT_ZMIN_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_10", REG_MMIO, 0xA0C9, &mmPA_SC_VPORT_ZMAX_10[0], sizeof(mmPA_SC_VPORT_ZMAX_10)/sizeof(mmPA_SC_VPORT_ZMAX_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_11", REG_MMIO, 0xA0CA, &mmPA_SC_VPORT_ZMIN_11[0], sizeof(mmPA_SC_VPORT_ZMIN_11)/sizeof(mmPA_SC_VPORT_ZMIN_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_11", REG_MMIO, 0xA0CB, &mmPA_SC_VPORT_ZMAX_11[0], sizeof(mmPA_SC_VPORT_ZMAX_11)/sizeof(mmPA_SC_VPORT_ZMAX_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_12", REG_MMIO, 0xA0CC, &mmPA_SC_VPORT_ZMIN_12[0], sizeof(mmPA_SC_VPORT_ZMIN_12)/sizeof(mmPA_SC_VPORT_ZMIN_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_12", REG_MMIO, 0xA0CD, &mmPA_SC_VPORT_ZMAX_12[0], sizeof(mmPA_SC_VPORT_ZMAX_12)/sizeof(mmPA_SC_VPORT_ZMAX_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_13", REG_MMIO, 0xA0CE, &mmPA_SC_VPORT_ZMIN_13[0], sizeof(mmPA_SC_VPORT_ZMIN_13)/sizeof(mmPA_SC_VPORT_ZMIN_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_13", REG_MMIO, 0xA0CF, &mmPA_SC_VPORT_ZMAX_13[0], sizeof(mmPA_SC_VPORT_ZMAX_13)/sizeof(mmPA_SC_VPORT_ZMAX_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_14", REG_MMIO, 0xA0D0, &mmPA_SC_VPORT_ZMIN_14[0], sizeof(mmPA_SC_VPORT_ZMIN_14)/sizeof(mmPA_SC_VPORT_ZMIN_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_14", REG_MMIO, 0xA0D1, &mmPA_SC_VPORT_ZMAX_14[0], sizeof(mmPA_SC_VPORT_ZMAX_14)/sizeof(mmPA_SC_VPORT_ZMAX_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_15", REG_MMIO, 0xA0D2, &mmPA_SC_VPORT_ZMIN_15[0], sizeof(mmPA_SC_VPORT_ZMIN_15)/sizeof(mmPA_SC_VPORT_ZMIN_15[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_15", REG_MMIO, 0xA0D3, &mmPA_SC_VPORT_ZMAX_15[0], sizeof(mmPA_SC_VPORT_ZMAX_15)/sizeof(mmPA_SC_VPORT_ZMAX_15[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG", REG_MMIO, 0xA0D4, &mmPA_SC_RASTER_CONFIG[0], sizeof(mmPA_SC_RASTER_CONFIG)/sizeof(mmPA_SC_RASTER_CONFIG[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTX_CNTL", REG_MMIO, 0xA0D8, &mmCP_PERFMON_CNTX_CNTL[0], sizeof(mmCP_PERFMON_CNTX_CNTL)/sizeof(mmCP_PERFMON_CNTX_CNTL[0]), 0, 0 },
+	{ "mmCP_RINGID", REG_MMIO, 0xA0D9, &mmCP_RINGID[0], sizeof(mmCP_RINGID)/sizeof(mmCP_RINGID[0]), 0, 0 },
+	{ "mmCP_VMID", REG_MMIO, 0xA0DA, &mmCP_VMID[0], sizeof(mmCP_VMID)/sizeof(mmCP_VMID[0]), 0, 0 },
+	{ "mmVGT_MAX_VTX_INDX", REG_MMIO, 0xA100, &mmVGT_MAX_VTX_INDX[0], sizeof(mmVGT_MAX_VTX_INDX)/sizeof(mmVGT_MAX_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_MIN_VTX_INDX", REG_MMIO, 0xA101, &mmVGT_MIN_VTX_INDX[0], sizeof(mmVGT_MIN_VTX_INDX)/sizeof(mmVGT_MIN_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_INDX_OFFSET", REG_MMIO, 0xA102, &mmVGT_INDX_OFFSET[0], sizeof(mmVGT_INDX_OFFSET)/sizeof(mmVGT_INDX_OFFSET[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_INDX", REG_MMIO, 0xA103, &mmVGT_MULTI_PRIM_IB_RESET_INDX[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX[0]), 0, 0 },
+	{ "mmCB_BLEND_RED", REG_MMIO, 0xA105, &mmCB_BLEND_RED[0], sizeof(mmCB_BLEND_RED)/sizeof(mmCB_BLEND_RED[0]), 0, 0 },
+	{ "mmCB_BLEND_GREEN", REG_MMIO, 0xA106, &mmCB_BLEND_GREEN[0], sizeof(mmCB_BLEND_GREEN)/sizeof(mmCB_BLEND_GREEN[0]), 0, 0 },
+	{ "mmCB_BLEND_BLUE", REG_MMIO, 0xA107, &mmCB_BLEND_BLUE[0], sizeof(mmCB_BLEND_BLUE)/sizeof(mmCB_BLEND_BLUE[0]), 0, 0 },
+	{ "mmCB_BLEND_ALPHA", REG_MMIO, 0xA108, &mmCB_BLEND_ALPHA[0], sizeof(mmCB_BLEND_ALPHA)/sizeof(mmCB_BLEND_ALPHA[0]), 0, 0 },
+	{ "mmDB_STENCIL_CONTROL", REG_MMIO, 0xA10B, &mmDB_STENCIL_CONTROL[0], sizeof(mmDB_STENCIL_CONTROL)/sizeof(mmDB_STENCIL_CONTROL[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK", REG_MMIO, 0xA10C, &mmDB_STENCILREFMASK[0], sizeof(mmDB_STENCILREFMASK)/sizeof(mmDB_STENCILREFMASK[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK_BF", REG_MMIO, 0xA10D, &mmDB_STENCILREFMASK_BF[0], sizeof(mmDB_STENCILREFMASK_BF)/sizeof(mmDB_STENCILREFMASK_BF[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE", REG_MMIO, 0xA10F, &mmPA_CL_VPORT_XSCALE[0], sizeof(mmPA_CL_VPORT_XSCALE)/sizeof(mmPA_CL_VPORT_XSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET", REG_MMIO, 0xA110, &mmPA_CL_VPORT_XOFFSET[0], sizeof(mmPA_CL_VPORT_XOFFSET)/sizeof(mmPA_CL_VPORT_XOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE", REG_MMIO, 0xA111, &mmPA_CL_VPORT_YSCALE[0], sizeof(mmPA_CL_VPORT_YSCALE)/sizeof(mmPA_CL_VPORT_YSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET", REG_MMIO, 0xA112, &mmPA_CL_VPORT_YOFFSET[0], sizeof(mmPA_CL_VPORT_YOFFSET)/sizeof(mmPA_CL_VPORT_YOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE", REG_MMIO, 0xA113, &mmPA_CL_VPORT_ZSCALE[0], sizeof(mmPA_CL_VPORT_ZSCALE)/sizeof(mmPA_CL_VPORT_ZSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET", REG_MMIO, 0xA114, &mmPA_CL_VPORT_ZOFFSET[0], sizeof(mmPA_CL_VPORT_ZOFFSET)/sizeof(mmPA_CL_VPORT_ZOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_1", REG_MMIO, 0xA115, &mmPA_CL_VPORT_XSCALE_1[0], sizeof(mmPA_CL_VPORT_XSCALE_1)/sizeof(mmPA_CL_VPORT_XSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_1", REG_MMIO, 0xA116, &mmPA_CL_VPORT_XOFFSET_1[0], sizeof(mmPA_CL_VPORT_XOFFSET_1)/sizeof(mmPA_CL_VPORT_XOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_1", REG_MMIO, 0xA117, &mmPA_CL_VPORT_YSCALE_1[0], sizeof(mmPA_CL_VPORT_YSCALE_1)/sizeof(mmPA_CL_VPORT_YSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_1", REG_MMIO, 0xA118, &mmPA_CL_VPORT_YOFFSET_1[0], sizeof(mmPA_CL_VPORT_YOFFSET_1)/sizeof(mmPA_CL_VPORT_YOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_1", REG_MMIO, 0xA119, &mmPA_CL_VPORT_ZSCALE_1[0], sizeof(mmPA_CL_VPORT_ZSCALE_1)/sizeof(mmPA_CL_VPORT_ZSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_1", REG_MMIO, 0xA11A, &mmPA_CL_VPORT_ZOFFSET_1[0], sizeof(mmPA_CL_VPORT_ZOFFSET_1)/sizeof(mmPA_CL_VPORT_ZOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_2", REG_MMIO, 0xA11B, &mmPA_CL_VPORT_XSCALE_2[0], sizeof(mmPA_CL_VPORT_XSCALE_2)/sizeof(mmPA_CL_VPORT_XSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_2", REG_MMIO, 0xA11C, &mmPA_CL_VPORT_XOFFSET_2[0], sizeof(mmPA_CL_VPORT_XOFFSET_2)/sizeof(mmPA_CL_VPORT_XOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_2", REG_MMIO, 0xA11D, &mmPA_CL_VPORT_YSCALE_2[0], sizeof(mmPA_CL_VPORT_YSCALE_2)/sizeof(mmPA_CL_VPORT_YSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_2", REG_MMIO, 0xA11E, &mmPA_CL_VPORT_YOFFSET_2[0], sizeof(mmPA_CL_VPORT_YOFFSET_2)/sizeof(mmPA_CL_VPORT_YOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_2", REG_MMIO, 0xA11F, &mmPA_CL_VPORT_ZSCALE_2[0], sizeof(mmPA_CL_VPORT_ZSCALE_2)/sizeof(mmPA_CL_VPORT_ZSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_2", REG_MMIO, 0xA120, &mmPA_CL_VPORT_ZOFFSET_2[0], sizeof(mmPA_CL_VPORT_ZOFFSET_2)/sizeof(mmPA_CL_VPORT_ZOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_3", REG_MMIO, 0xA121, &mmPA_CL_VPORT_XSCALE_3[0], sizeof(mmPA_CL_VPORT_XSCALE_3)/sizeof(mmPA_CL_VPORT_XSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_3", REG_MMIO, 0xA122, &mmPA_CL_VPORT_XOFFSET_3[0], sizeof(mmPA_CL_VPORT_XOFFSET_3)/sizeof(mmPA_CL_VPORT_XOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_3", REG_MMIO, 0xA123, &mmPA_CL_VPORT_YSCALE_3[0], sizeof(mmPA_CL_VPORT_YSCALE_3)/sizeof(mmPA_CL_VPORT_YSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_3", REG_MMIO, 0xA124, &mmPA_CL_VPORT_YOFFSET_3[0], sizeof(mmPA_CL_VPORT_YOFFSET_3)/sizeof(mmPA_CL_VPORT_YOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_3", REG_MMIO, 0xA125, &mmPA_CL_VPORT_ZSCALE_3[0], sizeof(mmPA_CL_VPORT_ZSCALE_3)/sizeof(mmPA_CL_VPORT_ZSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_3", REG_MMIO, 0xA126, &mmPA_CL_VPORT_ZOFFSET_3[0], sizeof(mmPA_CL_VPORT_ZOFFSET_3)/sizeof(mmPA_CL_VPORT_ZOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_4", REG_MMIO, 0xA127, &mmPA_CL_VPORT_XSCALE_4[0], sizeof(mmPA_CL_VPORT_XSCALE_4)/sizeof(mmPA_CL_VPORT_XSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_4", REG_MMIO, 0xA128, &mmPA_CL_VPORT_XOFFSET_4[0], sizeof(mmPA_CL_VPORT_XOFFSET_4)/sizeof(mmPA_CL_VPORT_XOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_4", REG_MMIO, 0xA129, &mmPA_CL_VPORT_YSCALE_4[0], sizeof(mmPA_CL_VPORT_YSCALE_4)/sizeof(mmPA_CL_VPORT_YSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_4", REG_MMIO, 0xA12A, &mmPA_CL_VPORT_YOFFSET_4[0], sizeof(mmPA_CL_VPORT_YOFFSET_4)/sizeof(mmPA_CL_VPORT_YOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_4", REG_MMIO, 0xA12B, &mmPA_CL_VPORT_ZSCALE_4[0], sizeof(mmPA_CL_VPORT_ZSCALE_4)/sizeof(mmPA_CL_VPORT_ZSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_4", REG_MMIO, 0xA12C, &mmPA_CL_VPORT_ZOFFSET_4[0], sizeof(mmPA_CL_VPORT_ZOFFSET_4)/sizeof(mmPA_CL_VPORT_ZOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_5", REG_MMIO, 0xA12D, &mmPA_CL_VPORT_XSCALE_5[0], sizeof(mmPA_CL_VPORT_XSCALE_5)/sizeof(mmPA_CL_VPORT_XSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_5", REG_MMIO, 0xA12E, &mmPA_CL_VPORT_XOFFSET_5[0], sizeof(mmPA_CL_VPORT_XOFFSET_5)/sizeof(mmPA_CL_VPORT_XOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_5", REG_MMIO, 0xA12F, &mmPA_CL_VPORT_YSCALE_5[0], sizeof(mmPA_CL_VPORT_YSCALE_5)/sizeof(mmPA_CL_VPORT_YSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_5", REG_MMIO, 0xA130, &mmPA_CL_VPORT_YOFFSET_5[0], sizeof(mmPA_CL_VPORT_YOFFSET_5)/sizeof(mmPA_CL_VPORT_YOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_5", REG_MMIO, 0xA131, &mmPA_CL_VPORT_ZSCALE_5[0], sizeof(mmPA_CL_VPORT_ZSCALE_5)/sizeof(mmPA_CL_VPORT_ZSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_5", REG_MMIO, 0xA132, &mmPA_CL_VPORT_ZOFFSET_5[0], sizeof(mmPA_CL_VPORT_ZOFFSET_5)/sizeof(mmPA_CL_VPORT_ZOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_6", REG_MMIO, 0xA133, &mmPA_CL_VPORT_XSCALE_6[0], sizeof(mmPA_CL_VPORT_XSCALE_6)/sizeof(mmPA_CL_VPORT_XSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_6", REG_MMIO, 0xA134, &mmPA_CL_VPORT_XOFFSET_6[0], sizeof(mmPA_CL_VPORT_XOFFSET_6)/sizeof(mmPA_CL_VPORT_XOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_6", REG_MMIO, 0xA135, &mmPA_CL_VPORT_YSCALE_6[0], sizeof(mmPA_CL_VPORT_YSCALE_6)/sizeof(mmPA_CL_VPORT_YSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_6", REG_MMIO, 0xA136, &mmPA_CL_VPORT_YOFFSET_6[0], sizeof(mmPA_CL_VPORT_YOFFSET_6)/sizeof(mmPA_CL_VPORT_YOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_6", REG_MMIO, 0xA137, &mmPA_CL_VPORT_ZSCALE_6[0], sizeof(mmPA_CL_VPORT_ZSCALE_6)/sizeof(mmPA_CL_VPORT_ZSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_6", REG_MMIO, 0xA138, &mmPA_CL_VPORT_ZOFFSET_6[0], sizeof(mmPA_CL_VPORT_ZOFFSET_6)/sizeof(mmPA_CL_VPORT_ZOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_7", REG_MMIO, 0xA139, &mmPA_CL_VPORT_XSCALE_7[0], sizeof(mmPA_CL_VPORT_XSCALE_7)/sizeof(mmPA_CL_VPORT_XSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_7", REG_MMIO, 0xA13A, &mmPA_CL_VPORT_XOFFSET_7[0], sizeof(mmPA_CL_VPORT_XOFFSET_7)/sizeof(mmPA_CL_VPORT_XOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_7", REG_MMIO, 0xA13B, &mmPA_CL_VPORT_YSCALE_7[0], sizeof(mmPA_CL_VPORT_YSCALE_7)/sizeof(mmPA_CL_VPORT_YSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_7", REG_MMIO, 0xA13C, &mmPA_CL_VPORT_YOFFSET_7[0], sizeof(mmPA_CL_VPORT_YOFFSET_7)/sizeof(mmPA_CL_VPORT_YOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_7", REG_MMIO, 0xA13D, &mmPA_CL_VPORT_ZSCALE_7[0], sizeof(mmPA_CL_VPORT_ZSCALE_7)/sizeof(mmPA_CL_VPORT_ZSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_7", REG_MMIO, 0xA13E, &mmPA_CL_VPORT_ZOFFSET_7[0], sizeof(mmPA_CL_VPORT_ZOFFSET_7)/sizeof(mmPA_CL_VPORT_ZOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_8", REG_MMIO, 0xA13F, &mmPA_CL_VPORT_XSCALE_8[0], sizeof(mmPA_CL_VPORT_XSCALE_8)/sizeof(mmPA_CL_VPORT_XSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_8", REG_MMIO, 0xA140, &mmPA_CL_VPORT_XOFFSET_8[0], sizeof(mmPA_CL_VPORT_XOFFSET_8)/sizeof(mmPA_CL_VPORT_XOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_8", REG_MMIO, 0xA141, &mmPA_CL_VPORT_YSCALE_8[0], sizeof(mmPA_CL_VPORT_YSCALE_8)/sizeof(mmPA_CL_VPORT_YSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_8", REG_MMIO, 0xA142, &mmPA_CL_VPORT_YOFFSET_8[0], sizeof(mmPA_CL_VPORT_YOFFSET_8)/sizeof(mmPA_CL_VPORT_YOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_8", REG_MMIO, 0xA143, &mmPA_CL_VPORT_ZSCALE_8[0], sizeof(mmPA_CL_VPORT_ZSCALE_8)/sizeof(mmPA_CL_VPORT_ZSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_8", REG_MMIO, 0xA144, &mmPA_CL_VPORT_ZOFFSET_8[0], sizeof(mmPA_CL_VPORT_ZOFFSET_8)/sizeof(mmPA_CL_VPORT_ZOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_9", REG_MMIO, 0xA145, &mmPA_CL_VPORT_XSCALE_9[0], sizeof(mmPA_CL_VPORT_XSCALE_9)/sizeof(mmPA_CL_VPORT_XSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_9", REG_MMIO, 0xA146, &mmPA_CL_VPORT_XOFFSET_9[0], sizeof(mmPA_CL_VPORT_XOFFSET_9)/sizeof(mmPA_CL_VPORT_XOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_9", REG_MMIO, 0xA147, &mmPA_CL_VPORT_YSCALE_9[0], sizeof(mmPA_CL_VPORT_YSCALE_9)/sizeof(mmPA_CL_VPORT_YSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_9", REG_MMIO, 0xA148, &mmPA_CL_VPORT_YOFFSET_9[0], sizeof(mmPA_CL_VPORT_YOFFSET_9)/sizeof(mmPA_CL_VPORT_YOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_9", REG_MMIO, 0xA149, &mmPA_CL_VPORT_ZSCALE_9[0], sizeof(mmPA_CL_VPORT_ZSCALE_9)/sizeof(mmPA_CL_VPORT_ZSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_9", REG_MMIO, 0xA14A, &mmPA_CL_VPORT_ZOFFSET_9[0], sizeof(mmPA_CL_VPORT_ZOFFSET_9)/sizeof(mmPA_CL_VPORT_ZOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_10", REG_MMIO, 0xA14B, &mmPA_CL_VPORT_XSCALE_10[0], sizeof(mmPA_CL_VPORT_XSCALE_10)/sizeof(mmPA_CL_VPORT_XSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_10", REG_MMIO, 0xA14C, &mmPA_CL_VPORT_XOFFSET_10[0], sizeof(mmPA_CL_VPORT_XOFFSET_10)/sizeof(mmPA_CL_VPORT_XOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_10", REG_MMIO, 0xA14D, &mmPA_CL_VPORT_YSCALE_10[0], sizeof(mmPA_CL_VPORT_YSCALE_10)/sizeof(mmPA_CL_VPORT_YSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_10", REG_MMIO, 0xA14E, &mmPA_CL_VPORT_YOFFSET_10[0], sizeof(mmPA_CL_VPORT_YOFFSET_10)/sizeof(mmPA_CL_VPORT_YOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_10", REG_MMIO, 0xA14F, &mmPA_CL_VPORT_ZSCALE_10[0], sizeof(mmPA_CL_VPORT_ZSCALE_10)/sizeof(mmPA_CL_VPORT_ZSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_10", REG_MMIO, 0xA150, &mmPA_CL_VPORT_ZOFFSET_10[0], sizeof(mmPA_CL_VPORT_ZOFFSET_10)/sizeof(mmPA_CL_VPORT_ZOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_11", REG_MMIO, 0xA151, &mmPA_CL_VPORT_XSCALE_11[0], sizeof(mmPA_CL_VPORT_XSCALE_11)/sizeof(mmPA_CL_VPORT_XSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_11", REG_MMIO, 0xA152, &mmPA_CL_VPORT_XOFFSET_11[0], sizeof(mmPA_CL_VPORT_XOFFSET_11)/sizeof(mmPA_CL_VPORT_XOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_11", REG_MMIO, 0xA153, &mmPA_CL_VPORT_YSCALE_11[0], sizeof(mmPA_CL_VPORT_YSCALE_11)/sizeof(mmPA_CL_VPORT_YSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_11", REG_MMIO, 0xA154, &mmPA_CL_VPORT_YOFFSET_11[0], sizeof(mmPA_CL_VPORT_YOFFSET_11)/sizeof(mmPA_CL_VPORT_YOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_11", REG_MMIO, 0xA155, &mmPA_CL_VPORT_ZSCALE_11[0], sizeof(mmPA_CL_VPORT_ZSCALE_11)/sizeof(mmPA_CL_VPORT_ZSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_11", REG_MMIO, 0xA156, &mmPA_CL_VPORT_ZOFFSET_11[0], sizeof(mmPA_CL_VPORT_ZOFFSET_11)/sizeof(mmPA_CL_VPORT_ZOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_12", REG_MMIO, 0xA157, &mmPA_CL_VPORT_XSCALE_12[0], sizeof(mmPA_CL_VPORT_XSCALE_12)/sizeof(mmPA_CL_VPORT_XSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_12", REG_MMIO, 0xA158, &mmPA_CL_VPORT_XOFFSET_12[0], sizeof(mmPA_CL_VPORT_XOFFSET_12)/sizeof(mmPA_CL_VPORT_XOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_12", REG_MMIO, 0xA159, &mmPA_CL_VPORT_YSCALE_12[0], sizeof(mmPA_CL_VPORT_YSCALE_12)/sizeof(mmPA_CL_VPORT_YSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_12", REG_MMIO, 0xA15A, &mmPA_CL_VPORT_YOFFSET_12[0], sizeof(mmPA_CL_VPORT_YOFFSET_12)/sizeof(mmPA_CL_VPORT_YOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_12", REG_MMIO, 0xA15B, &mmPA_CL_VPORT_ZSCALE_12[0], sizeof(mmPA_CL_VPORT_ZSCALE_12)/sizeof(mmPA_CL_VPORT_ZSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_12", REG_MMIO, 0xA15C, &mmPA_CL_VPORT_ZOFFSET_12[0], sizeof(mmPA_CL_VPORT_ZOFFSET_12)/sizeof(mmPA_CL_VPORT_ZOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_13", REG_MMIO, 0xA15D, &mmPA_CL_VPORT_XSCALE_13[0], sizeof(mmPA_CL_VPORT_XSCALE_13)/sizeof(mmPA_CL_VPORT_XSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_13", REG_MMIO, 0xA15E, &mmPA_CL_VPORT_XOFFSET_13[0], sizeof(mmPA_CL_VPORT_XOFFSET_13)/sizeof(mmPA_CL_VPORT_XOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_13", REG_MMIO, 0xA15F, &mmPA_CL_VPORT_YSCALE_13[0], sizeof(mmPA_CL_VPORT_YSCALE_13)/sizeof(mmPA_CL_VPORT_YSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_13", REG_MMIO, 0xA160, &mmPA_CL_VPORT_YOFFSET_13[0], sizeof(mmPA_CL_VPORT_YOFFSET_13)/sizeof(mmPA_CL_VPORT_YOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_13", REG_MMIO, 0xA161, &mmPA_CL_VPORT_ZSCALE_13[0], sizeof(mmPA_CL_VPORT_ZSCALE_13)/sizeof(mmPA_CL_VPORT_ZSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_13", REG_MMIO, 0xA162, &mmPA_CL_VPORT_ZOFFSET_13[0], sizeof(mmPA_CL_VPORT_ZOFFSET_13)/sizeof(mmPA_CL_VPORT_ZOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_14", REG_MMIO, 0xA163, &mmPA_CL_VPORT_XSCALE_14[0], sizeof(mmPA_CL_VPORT_XSCALE_14)/sizeof(mmPA_CL_VPORT_XSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_14", REG_MMIO, 0xA164, &mmPA_CL_VPORT_XOFFSET_14[0], sizeof(mmPA_CL_VPORT_XOFFSET_14)/sizeof(mmPA_CL_VPORT_XOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_14", REG_MMIO, 0xA165, &mmPA_CL_VPORT_YSCALE_14[0], sizeof(mmPA_CL_VPORT_YSCALE_14)/sizeof(mmPA_CL_VPORT_YSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_14", REG_MMIO, 0xA166, &mmPA_CL_VPORT_YOFFSET_14[0], sizeof(mmPA_CL_VPORT_YOFFSET_14)/sizeof(mmPA_CL_VPORT_YOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_14", REG_MMIO, 0xA167, &mmPA_CL_VPORT_ZSCALE_14[0], sizeof(mmPA_CL_VPORT_ZSCALE_14)/sizeof(mmPA_CL_VPORT_ZSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_14", REG_MMIO, 0xA168, &mmPA_CL_VPORT_ZOFFSET_14[0], sizeof(mmPA_CL_VPORT_ZOFFSET_14)/sizeof(mmPA_CL_VPORT_ZOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_15", REG_MMIO, 0xA169, &mmPA_CL_VPORT_XSCALE_15[0], sizeof(mmPA_CL_VPORT_XSCALE_15)/sizeof(mmPA_CL_VPORT_XSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_15", REG_MMIO, 0xA16A, &mmPA_CL_VPORT_XOFFSET_15[0], sizeof(mmPA_CL_VPORT_XOFFSET_15)/sizeof(mmPA_CL_VPORT_XOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_15", REG_MMIO, 0xA16B, &mmPA_CL_VPORT_YSCALE_15[0], sizeof(mmPA_CL_VPORT_YSCALE_15)/sizeof(mmPA_CL_VPORT_YSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_15", REG_MMIO, 0xA16C, &mmPA_CL_VPORT_YOFFSET_15[0], sizeof(mmPA_CL_VPORT_YOFFSET_15)/sizeof(mmPA_CL_VPORT_YOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_15", REG_MMIO, 0xA16D, &mmPA_CL_VPORT_ZSCALE_15[0], sizeof(mmPA_CL_VPORT_ZSCALE_15)/sizeof(mmPA_CL_VPORT_ZSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_15", REG_MMIO, 0xA16E, &mmPA_CL_VPORT_ZOFFSET_15[0], sizeof(mmPA_CL_VPORT_ZOFFSET_15)/sizeof(mmPA_CL_VPORT_ZOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_X", REG_MMIO, 0xA16F, &mmPA_CL_UCP_0_X[0], sizeof(mmPA_CL_UCP_0_X)/sizeof(mmPA_CL_UCP_0_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Y", REG_MMIO, 0xA170, &mmPA_CL_UCP_0_Y[0], sizeof(mmPA_CL_UCP_0_Y)/sizeof(mmPA_CL_UCP_0_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Z", REG_MMIO, 0xA171, &mmPA_CL_UCP_0_Z[0], sizeof(mmPA_CL_UCP_0_Z)/sizeof(mmPA_CL_UCP_0_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_W", REG_MMIO, 0xA172, &mmPA_CL_UCP_0_W[0], sizeof(mmPA_CL_UCP_0_W)/sizeof(mmPA_CL_UCP_0_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_X", REG_MMIO, 0xA173, &mmPA_CL_UCP_1_X[0], sizeof(mmPA_CL_UCP_1_X)/sizeof(mmPA_CL_UCP_1_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Y", REG_MMIO, 0xA174, &mmPA_CL_UCP_1_Y[0], sizeof(mmPA_CL_UCP_1_Y)/sizeof(mmPA_CL_UCP_1_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Z", REG_MMIO, 0xA175, &mmPA_CL_UCP_1_Z[0], sizeof(mmPA_CL_UCP_1_Z)/sizeof(mmPA_CL_UCP_1_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_W", REG_MMIO, 0xA176, &mmPA_CL_UCP_1_W[0], sizeof(mmPA_CL_UCP_1_W)/sizeof(mmPA_CL_UCP_1_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_X", REG_MMIO, 0xA177, &mmPA_CL_UCP_2_X[0], sizeof(mmPA_CL_UCP_2_X)/sizeof(mmPA_CL_UCP_2_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Y", REG_MMIO, 0xA178, &mmPA_CL_UCP_2_Y[0], sizeof(mmPA_CL_UCP_2_Y)/sizeof(mmPA_CL_UCP_2_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Z", REG_MMIO, 0xA179, &mmPA_CL_UCP_2_Z[0], sizeof(mmPA_CL_UCP_2_Z)/sizeof(mmPA_CL_UCP_2_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_W", REG_MMIO, 0xA17A, &mmPA_CL_UCP_2_W[0], sizeof(mmPA_CL_UCP_2_W)/sizeof(mmPA_CL_UCP_2_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_X", REG_MMIO, 0xA17B, &mmPA_CL_UCP_3_X[0], sizeof(mmPA_CL_UCP_3_X)/sizeof(mmPA_CL_UCP_3_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Y", REG_MMIO, 0xA17C, &mmPA_CL_UCP_3_Y[0], sizeof(mmPA_CL_UCP_3_Y)/sizeof(mmPA_CL_UCP_3_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Z", REG_MMIO, 0xA17D, &mmPA_CL_UCP_3_Z[0], sizeof(mmPA_CL_UCP_3_Z)/sizeof(mmPA_CL_UCP_3_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_W", REG_MMIO, 0xA17E, &mmPA_CL_UCP_3_W[0], sizeof(mmPA_CL_UCP_3_W)/sizeof(mmPA_CL_UCP_3_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_X", REG_MMIO, 0xA17F, &mmPA_CL_UCP_4_X[0], sizeof(mmPA_CL_UCP_4_X)/sizeof(mmPA_CL_UCP_4_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Y", REG_MMIO, 0xA180, &mmPA_CL_UCP_4_Y[0], sizeof(mmPA_CL_UCP_4_Y)/sizeof(mmPA_CL_UCP_4_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Z", REG_MMIO, 0xA181, &mmPA_CL_UCP_4_Z[0], sizeof(mmPA_CL_UCP_4_Z)/sizeof(mmPA_CL_UCP_4_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_W", REG_MMIO, 0xA182, &mmPA_CL_UCP_4_W[0], sizeof(mmPA_CL_UCP_4_W)/sizeof(mmPA_CL_UCP_4_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_X", REG_MMIO, 0xA183, &mmPA_CL_UCP_5_X[0], sizeof(mmPA_CL_UCP_5_X)/sizeof(mmPA_CL_UCP_5_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Y", REG_MMIO, 0xA184, &mmPA_CL_UCP_5_Y[0], sizeof(mmPA_CL_UCP_5_Y)/sizeof(mmPA_CL_UCP_5_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Z", REG_MMIO, 0xA185, &mmPA_CL_UCP_5_Z[0], sizeof(mmPA_CL_UCP_5_Z)/sizeof(mmPA_CL_UCP_5_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_W", REG_MMIO, 0xA186, &mmPA_CL_UCP_5_W[0], sizeof(mmPA_CL_UCP_5_W)/sizeof(mmPA_CL_UCP_5_W[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_0", REG_MMIO, 0xA191, &mmSPI_PS_INPUT_CNTL_0[0], sizeof(mmSPI_PS_INPUT_CNTL_0)/sizeof(mmSPI_PS_INPUT_CNTL_0[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_1", REG_MMIO, 0xA192, &mmSPI_PS_INPUT_CNTL_1[0], sizeof(mmSPI_PS_INPUT_CNTL_1)/sizeof(mmSPI_PS_INPUT_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_2", REG_MMIO, 0xA193, &mmSPI_PS_INPUT_CNTL_2[0], sizeof(mmSPI_PS_INPUT_CNTL_2)/sizeof(mmSPI_PS_INPUT_CNTL_2[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_3", REG_MMIO, 0xA194, &mmSPI_PS_INPUT_CNTL_3[0], sizeof(mmSPI_PS_INPUT_CNTL_3)/sizeof(mmSPI_PS_INPUT_CNTL_3[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_4", REG_MMIO, 0xA195, &mmSPI_PS_INPUT_CNTL_4[0], sizeof(mmSPI_PS_INPUT_CNTL_4)/sizeof(mmSPI_PS_INPUT_CNTL_4[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_5", REG_MMIO, 0xA196, &mmSPI_PS_INPUT_CNTL_5[0], sizeof(mmSPI_PS_INPUT_CNTL_5)/sizeof(mmSPI_PS_INPUT_CNTL_5[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_6", REG_MMIO, 0xA197, &mmSPI_PS_INPUT_CNTL_6[0], sizeof(mmSPI_PS_INPUT_CNTL_6)/sizeof(mmSPI_PS_INPUT_CNTL_6[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_7", REG_MMIO, 0xA198, &mmSPI_PS_INPUT_CNTL_7[0], sizeof(mmSPI_PS_INPUT_CNTL_7)/sizeof(mmSPI_PS_INPUT_CNTL_7[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_8", REG_MMIO, 0xA199, &mmSPI_PS_INPUT_CNTL_8[0], sizeof(mmSPI_PS_INPUT_CNTL_8)/sizeof(mmSPI_PS_INPUT_CNTL_8[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_9", REG_MMIO, 0xA19A, &mmSPI_PS_INPUT_CNTL_9[0], sizeof(mmSPI_PS_INPUT_CNTL_9)/sizeof(mmSPI_PS_INPUT_CNTL_9[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_10", REG_MMIO, 0xA19B, &mmSPI_PS_INPUT_CNTL_10[0], sizeof(mmSPI_PS_INPUT_CNTL_10)/sizeof(mmSPI_PS_INPUT_CNTL_10[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_11", REG_MMIO, 0xA19C, &mmSPI_PS_INPUT_CNTL_11[0], sizeof(mmSPI_PS_INPUT_CNTL_11)/sizeof(mmSPI_PS_INPUT_CNTL_11[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_12", REG_MMIO, 0xA19D, &mmSPI_PS_INPUT_CNTL_12[0], sizeof(mmSPI_PS_INPUT_CNTL_12)/sizeof(mmSPI_PS_INPUT_CNTL_12[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_13", REG_MMIO, 0xA19E, &mmSPI_PS_INPUT_CNTL_13[0], sizeof(mmSPI_PS_INPUT_CNTL_13)/sizeof(mmSPI_PS_INPUT_CNTL_13[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_14", REG_MMIO, 0xA19F, &mmSPI_PS_INPUT_CNTL_14[0], sizeof(mmSPI_PS_INPUT_CNTL_14)/sizeof(mmSPI_PS_INPUT_CNTL_14[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_15", REG_MMIO, 0xA1A0, &mmSPI_PS_INPUT_CNTL_15[0], sizeof(mmSPI_PS_INPUT_CNTL_15)/sizeof(mmSPI_PS_INPUT_CNTL_15[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_16", REG_MMIO, 0xA1A1, &mmSPI_PS_INPUT_CNTL_16[0], sizeof(mmSPI_PS_INPUT_CNTL_16)/sizeof(mmSPI_PS_INPUT_CNTL_16[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_17", REG_MMIO, 0xA1A2, &mmSPI_PS_INPUT_CNTL_17[0], sizeof(mmSPI_PS_INPUT_CNTL_17)/sizeof(mmSPI_PS_INPUT_CNTL_17[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_18", REG_MMIO, 0xA1A3, &mmSPI_PS_INPUT_CNTL_18[0], sizeof(mmSPI_PS_INPUT_CNTL_18)/sizeof(mmSPI_PS_INPUT_CNTL_18[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_19", REG_MMIO, 0xA1A4, &mmSPI_PS_INPUT_CNTL_19[0], sizeof(mmSPI_PS_INPUT_CNTL_19)/sizeof(mmSPI_PS_INPUT_CNTL_19[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_20", REG_MMIO, 0xA1A5, &mmSPI_PS_INPUT_CNTL_20[0], sizeof(mmSPI_PS_INPUT_CNTL_20)/sizeof(mmSPI_PS_INPUT_CNTL_20[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_21", REG_MMIO, 0xA1A6, &mmSPI_PS_INPUT_CNTL_21[0], sizeof(mmSPI_PS_INPUT_CNTL_21)/sizeof(mmSPI_PS_INPUT_CNTL_21[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_22", REG_MMIO, 0xA1A7, &mmSPI_PS_INPUT_CNTL_22[0], sizeof(mmSPI_PS_INPUT_CNTL_22)/sizeof(mmSPI_PS_INPUT_CNTL_22[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_23", REG_MMIO, 0xA1A8, &mmSPI_PS_INPUT_CNTL_23[0], sizeof(mmSPI_PS_INPUT_CNTL_23)/sizeof(mmSPI_PS_INPUT_CNTL_23[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_24", REG_MMIO, 0xA1A9, &mmSPI_PS_INPUT_CNTL_24[0], sizeof(mmSPI_PS_INPUT_CNTL_24)/sizeof(mmSPI_PS_INPUT_CNTL_24[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_25", REG_MMIO, 0xA1AA, &mmSPI_PS_INPUT_CNTL_25[0], sizeof(mmSPI_PS_INPUT_CNTL_25)/sizeof(mmSPI_PS_INPUT_CNTL_25[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_26", REG_MMIO, 0xA1AB, &mmSPI_PS_INPUT_CNTL_26[0], sizeof(mmSPI_PS_INPUT_CNTL_26)/sizeof(mmSPI_PS_INPUT_CNTL_26[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_27", REG_MMIO, 0xA1AC, &mmSPI_PS_INPUT_CNTL_27[0], sizeof(mmSPI_PS_INPUT_CNTL_27)/sizeof(mmSPI_PS_INPUT_CNTL_27[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_28", REG_MMIO, 0xA1AD, &mmSPI_PS_INPUT_CNTL_28[0], sizeof(mmSPI_PS_INPUT_CNTL_28)/sizeof(mmSPI_PS_INPUT_CNTL_28[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_29", REG_MMIO, 0xA1AE, &mmSPI_PS_INPUT_CNTL_29[0], sizeof(mmSPI_PS_INPUT_CNTL_29)/sizeof(mmSPI_PS_INPUT_CNTL_29[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_30", REG_MMIO, 0xA1AF, &mmSPI_PS_INPUT_CNTL_30[0], sizeof(mmSPI_PS_INPUT_CNTL_30)/sizeof(mmSPI_PS_INPUT_CNTL_30[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_31", REG_MMIO, 0xA1B0, &mmSPI_PS_INPUT_CNTL_31[0], sizeof(mmSPI_PS_INPUT_CNTL_31)/sizeof(mmSPI_PS_INPUT_CNTL_31[0]), 0, 0 },
+	{ "mmSPI_VS_OUT_CONFIG", REG_MMIO, 0xA1B1, &mmSPI_VS_OUT_CONFIG[0], sizeof(mmSPI_VS_OUT_CONFIG)/sizeof(mmSPI_VS_OUT_CONFIG[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ENA", REG_MMIO, 0xA1B3, &mmSPI_PS_INPUT_ENA[0], sizeof(mmSPI_PS_INPUT_ENA)/sizeof(mmSPI_PS_INPUT_ENA[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ADDR", REG_MMIO, 0xA1B4, &mmSPI_PS_INPUT_ADDR[0], sizeof(mmSPI_PS_INPUT_ADDR)/sizeof(mmSPI_PS_INPUT_ADDR[0]), 0, 0 },
+	{ "mmSPI_INTERP_CONTROL_0", REG_MMIO, 0xA1B5, &mmSPI_INTERP_CONTROL_0[0], sizeof(mmSPI_INTERP_CONTROL_0)/sizeof(mmSPI_INTERP_CONTROL_0[0]), 0, 0 },
+	{ "mmSPI_PS_IN_CONTROL", REG_MMIO, 0xA1B6, &mmSPI_PS_IN_CONTROL[0], sizeof(mmSPI_PS_IN_CONTROL)/sizeof(mmSPI_PS_IN_CONTROL[0]), 0, 0 },
+	{ "mmSPI_BARYC_CNTL", REG_MMIO, 0xA1B8, &mmSPI_BARYC_CNTL[0], sizeof(mmSPI_BARYC_CNTL)/sizeof(mmSPI_BARYC_CNTL[0]), 0, 0 },
+	{ "mmSPI_TMPRING_SIZE", REG_MMIO, 0xA1BA, &mmSPI_TMPRING_SIZE[0], sizeof(mmSPI_TMPRING_SIZE)/sizeof(mmSPI_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmSPI_SHADER_POS_FORMAT", REG_MMIO, 0xA1C3, &mmSPI_SHADER_POS_FORMAT[0], sizeof(mmSPI_SHADER_POS_FORMAT)/sizeof(mmSPI_SHADER_POS_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_Z_FORMAT", REG_MMIO, 0xA1C4, &mmSPI_SHADER_Z_FORMAT[0], sizeof(mmSPI_SHADER_Z_FORMAT)/sizeof(mmSPI_SHADER_Z_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_COL_FORMAT", REG_MMIO, 0xA1C5, &mmSPI_SHADER_COL_FORMAT[0], sizeof(mmSPI_SHADER_COL_FORMAT)/sizeof(mmSPI_SHADER_COL_FORMAT[0]), 0, 0 },
+	{ "mmCB_BLEND0_CONTROL", REG_MMIO, 0xA1E0, &mmCB_BLEND0_CONTROL[0], sizeof(mmCB_BLEND0_CONTROL)/sizeof(mmCB_BLEND0_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND1_CONTROL", REG_MMIO, 0xA1E1, &mmCB_BLEND1_CONTROL[0], sizeof(mmCB_BLEND1_CONTROL)/sizeof(mmCB_BLEND1_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND2_CONTROL", REG_MMIO, 0xA1E2, &mmCB_BLEND2_CONTROL[0], sizeof(mmCB_BLEND2_CONTROL)/sizeof(mmCB_BLEND2_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND3_CONTROL", REG_MMIO, 0xA1E3, &mmCB_BLEND3_CONTROL[0], sizeof(mmCB_BLEND3_CONTROL)/sizeof(mmCB_BLEND3_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND4_CONTROL", REG_MMIO, 0xA1E4, &mmCB_BLEND4_CONTROL[0], sizeof(mmCB_BLEND4_CONTROL)/sizeof(mmCB_BLEND4_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND5_CONTROL", REG_MMIO, 0xA1E5, &mmCB_BLEND5_CONTROL[0], sizeof(mmCB_BLEND5_CONTROL)/sizeof(mmCB_BLEND5_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND6_CONTROL", REG_MMIO, 0xA1E6, &mmCB_BLEND6_CONTROL[0], sizeof(mmCB_BLEND6_CONTROL)/sizeof(mmCB_BLEND6_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND7_CONTROL", REG_MMIO, 0xA1E7, &mmCB_BLEND7_CONTROL[0], sizeof(mmCB_BLEND7_CONTROL)/sizeof(mmCB_BLEND7_CONTROL[0]), 0, 0 },
+	{ "mmCS_COPY_STATE", REG_MMIO, 0xA1F3, &mmCS_COPY_STATE[0], sizeof(mmCS_COPY_STATE)/sizeof(mmCS_COPY_STATE[0]), 0, 0 },
+	{ "mmGFX_COPY_STATE", REG_MMIO, 0xA1F4, &mmGFX_COPY_STATE[0], sizeof(mmGFX_COPY_STATE)/sizeof(mmGFX_COPY_STATE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_X_RAD", REG_MMIO, 0xA1F5, &mmPA_CL_POINT_X_RAD[0], sizeof(mmPA_CL_POINT_X_RAD)/sizeof(mmPA_CL_POINT_X_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_Y_RAD", REG_MMIO, 0xA1F6, &mmPA_CL_POINT_Y_RAD[0], sizeof(mmPA_CL_POINT_Y_RAD)/sizeof(mmPA_CL_POINT_Y_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_SIZE", REG_MMIO, 0xA1F7, &mmPA_CL_POINT_SIZE[0], sizeof(mmPA_CL_POINT_SIZE)/sizeof(mmPA_CL_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_CULL_RAD", REG_MMIO, 0xA1F8, &mmPA_CL_POINT_CULL_RAD[0], sizeof(mmPA_CL_POINT_CULL_RAD)/sizeof(mmPA_CL_POINT_CULL_RAD[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE_HI", REG_MMIO, 0xA1F9, &mmVGT_DMA_BASE_HI[0], sizeof(mmVGT_DMA_BASE_HI)/sizeof(mmVGT_DMA_BASE_HI[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE", REG_MMIO, 0xA1FA, &mmVGT_DMA_BASE[0], sizeof(mmVGT_DMA_BASE)/sizeof(mmVGT_DMA_BASE[0]), 0, 0 },
+	{ "mmVGT_DRAW_INITIATOR", REG_MMIO, 0xA1FC, &mmVGT_DRAW_INITIATOR[0], sizeof(mmVGT_DRAW_INITIATOR)/sizeof(mmVGT_DRAW_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_IMMED_DATA", REG_MMIO, 0xA1FD, &mmVGT_IMMED_DATA[0], sizeof(mmVGT_IMMED_DATA)/sizeof(mmVGT_IMMED_DATA[0]), 0, 0 },
+	{ "mmVGT_EVENT_ADDRESS_REG", REG_MMIO, 0xA1FE, &mmVGT_EVENT_ADDRESS_REG[0], sizeof(mmVGT_EVENT_ADDRESS_REG)/sizeof(mmVGT_EVENT_ADDRESS_REG[0]), 0, 0 },
+	{ "mmDB_DEPTH_CONTROL", REG_MMIO, 0xA200, &mmDB_DEPTH_CONTROL[0], sizeof(mmDB_DEPTH_CONTROL)/sizeof(mmDB_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmDB_EQAA", REG_MMIO, 0xA201, &mmDB_EQAA[0], sizeof(mmDB_EQAA)/sizeof(mmDB_EQAA[0]), 0, 0 },
+	{ "mmCB_COLOR_CONTROL", REG_MMIO, 0xA202, &mmCB_COLOR_CONTROL[0], sizeof(mmCB_COLOR_CONTROL)/sizeof(mmCB_COLOR_CONTROL[0]), 0, 0 },
+	{ "mmDB_SHADER_CONTROL", REG_MMIO, 0xA203, &mmDB_SHADER_CONTROL[0], sizeof(mmDB_SHADER_CONTROL)/sizeof(mmDB_SHADER_CONTROL[0]), 0, 0 },
+	{ "mmPA_CL_CLIP_CNTL", REG_MMIO, 0xA204, &mmPA_CL_CLIP_CNTL[0], sizeof(mmPA_CL_CLIP_CNTL)/sizeof(mmPA_CL_CLIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_SC_MODE_CNTL", REG_MMIO, 0xA205, &mmPA_SU_SC_MODE_CNTL[0], sizeof(mmPA_SU_SC_MODE_CNTL)/sizeof(mmPA_SU_SC_MODE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VTE_CNTL", REG_MMIO, 0xA206, &mmPA_CL_VTE_CNTL[0], sizeof(mmPA_CL_VTE_CNTL)/sizeof(mmPA_CL_VTE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VS_OUT_CNTL", REG_MMIO, 0xA207, &mmPA_CL_VS_OUT_CNTL[0], sizeof(mmPA_CL_VS_OUT_CNTL)/sizeof(mmPA_CL_VS_OUT_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_NANINF_CNTL", REG_MMIO, 0xA208, &mmPA_CL_NANINF_CNTL[0], sizeof(mmPA_CL_NANINF_CNTL)/sizeof(mmPA_CL_NANINF_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_CNTL", REG_MMIO, 0xA209, &mmPA_SU_LINE_STIPPLE_CNTL[0], sizeof(mmPA_SU_LINE_STIPPLE_CNTL)/sizeof(mmPA_SU_LINE_STIPPLE_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_SCALE", REG_MMIO, 0xA20A, &mmPA_SU_LINE_STIPPLE_SCALE[0], sizeof(mmPA_SU_LINE_STIPPLE_SCALE)/sizeof(mmPA_SU_LINE_STIPPLE_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_PRIM_FILTER_CNTL", REG_MMIO, 0xA20B, &mmPA_SU_PRIM_FILTER_CNTL[0], sizeof(mmPA_SU_PRIM_FILTER_CNTL)/sizeof(mmPA_SU_PRIM_FILTER_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POINT_SIZE", REG_MMIO, 0xA280, &mmPA_SU_POINT_SIZE[0], sizeof(mmPA_SU_POINT_SIZE)/sizeof(mmPA_SU_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_SU_POINT_MINMAX", REG_MMIO, 0xA281, &mmPA_SU_POINT_MINMAX[0], sizeof(mmPA_SU_POINT_MINMAX)/sizeof(mmPA_SU_POINT_MINMAX[0]), 0, 0 },
+	{ "mmPA_SU_LINE_CNTL", REG_MMIO, 0xA282, &mmPA_SU_LINE_CNTL[0], sizeof(mmPA_SU_LINE_CNTL)/sizeof(mmPA_SU_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE", REG_MMIO, 0xA283, &mmPA_SC_LINE_STIPPLE[0], sizeof(mmPA_SC_LINE_STIPPLE)/sizeof(mmPA_SC_LINE_STIPPLE[0]), 0, 0 },
+	{ "mmVGT_OUTPUT_PATH_CNTL", REG_MMIO, 0xA284, &mmVGT_OUTPUT_PATH_CNTL[0], sizeof(mmVGT_OUTPUT_PATH_CNTL)/sizeof(mmVGT_OUTPUT_PATH_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_CNTL", REG_MMIO, 0xA285, &mmVGT_HOS_CNTL[0], sizeof(mmVGT_HOS_CNTL)/sizeof(mmVGT_HOS_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_MAX_TESS_LEVEL", REG_MMIO, 0xA286, &mmVGT_HOS_MAX_TESS_LEVEL[0], sizeof(mmVGT_HOS_MAX_TESS_LEVEL)/sizeof(mmVGT_HOS_MAX_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_MIN_TESS_LEVEL", REG_MMIO, 0xA287, &mmVGT_HOS_MIN_TESS_LEVEL[0], sizeof(mmVGT_HOS_MIN_TESS_LEVEL)/sizeof(mmVGT_HOS_MIN_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_REUSE_DEPTH", REG_MMIO, 0xA288, &mmVGT_HOS_REUSE_DEPTH[0], sizeof(mmVGT_HOS_REUSE_DEPTH)/sizeof(mmVGT_HOS_REUSE_DEPTH[0]), 0, 0 },
+	{ "mmVGT_GROUP_PRIM_TYPE", REG_MMIO, 0xA289, &mmVGT_GROUP_PRIM_TYPE[0], sizeof(mmVGT_GROUP_PRIM_TYPE)/sizeof(mmVGT_GROUP_PRIM_TYPE[0]), 0, 0 },
+	{ "mmVGT_GROUP_FIRST_DECR", REG_MMIO, 0xA28A, &mmVGT_GROUP_FIRST_DECR[0], sizeof(mmVGT_GROUP_FIRST_DECR)/sizeof(mmVGT_GROUP_FIRST_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_DECR", REG_MMIO, 0xA28B, &mmVGT_GROUP_DECR[0], sizeof(mmVGT_GROUP_DECR)/sizeof(mmVGT_GROUP_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_CNTL", REG_MMIO, 0xA28C, &mmVGT_GROUP_VECT_0_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_CNTL)/sizeof(mmVGT_GROUP_VECT_0_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_CNTL", REG_MMIO, 0xA28D, &mmVGT_GROUP_VECT_1_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_CNTL)/sizeof(mmVGT_GROUP_VECT_1_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_FMT_CNTL", REG_MMIO, 0xA28E, &mmVGT_GROUP_VECT_0_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_FMT_CNTL", REG_MMIO, 0xA28F, &mmVGT_GROUP_VECT_1_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GS_MODE", REG_MMIO, 0xA290, &mmVGT_GS_MODE[0], sizeof(mmVGT_GS_MODE)/sizeof(mmVGT_GS_MODE[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_0", REG_MMIO, 0xA292, &mmPA_SC_MODE_CNTL_0[0], sizeof(mmPA_SC_MODE_CNTL_0)/sizeof(mmPA_SC_MODE_CNTL_0[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_1", REG_MMIO, 0xA293, &mmPA_SC_MODE_CNTL_1[0], sizeof(mmPA_SC_MODE_CNTL_1)/sizeof(mmPA_SC_MODE_CNTL_1[0]), 0, 0 },
+	{ "mmVGT_ENHANCE", REG_MMIO, 0xA294, &mmVGT_ENHANCE[0], sizeof(mmVGT_ENHANCE)/sizeof(mmVGT_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_GS_PER_ES", REG_MMIO, 0xA295, &mmVGT_GS_PER_ES[0], sizeof(mmVGT_GS_PER_ES)/sizeof(mmVGT_GS_PER_ES[0]), 0, 0 },
+	{ "mmVGT_ES_PER_GS", REG_MMIO, 0xA296, &mmVGT_ES_PER_GS[0], sizeof(mmVGT_ES_PER_GS)/sizeof(mmVGT_ES_PER_GS[0]), 0, 0 },
+	{ "mmVGT_GS_PER_VS", REG_MMIO, 0xA297, &mmVGT_GS_PER_VS[0], sizeof(mmVGT_GS_PER_VS)/sizeof(mmVGT_GS_PER_VS[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_1", REG_MMIO, 0xA298, &mmVGT_GSVS_RING_OFFSET_1[0], sizeof(mmVGT_GSVS_RING_OFFSET_1)/sizeof(mmVGT_GSVS_RING_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_2", REG_MMIO, 0xA299, &mmVGT_GSVS_RING_OFFSET_2[0], sizeof(mmVGT_GSVS_RING_OFFSET_2)/sizeof(mmVGT_GSVS_RING_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_3", REG_MMIO, 0xA29A, &mmVGT_GSVS_RING_OFFSET_3[0], sizeof(mmVGT_GSVS_RING_OFFSET_3)/sizeof(mmVGT_GSVS_RING_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_GS_OUT_PRIM_TYPE", REG_MMIO, 0xA29B, &mmVGT_GS_OUT_PRIM_TYPE[0], sizeof(mmVGT_GS_OUT_PRIM_TYPE)/sizeof(mmVGT_GS_OUT_PRIM_TYPE[0]), 0, 0 },
+	{ "mmIA_ENHANCE", REG_MMIO, 0xA29C, &mmIA_ENHANCE[0], sizeof(mmIA_ENHANCE)/sizeof(mmIA_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_DMA_SIZE", REG_MMIO, 0xA29D, &mmVGT_DMA_SIZE[0], sizeof(mmVGT_DMA_SIZE)/sizeof(mmVGT_DMA_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_MAX_SIZE", REG_MMIO, 0xA29E, &mmVGT_DMA_MAX_SIZE[0], sizeof(mmVGT_DMA_MAX_SIZE)/sizeof(mmVGT_DMA_MAX_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_INDEX_TYPE", REG_MMIO, 0xA29F, &mmVGT_DMA_INDEX_TYPE[0], sizeof(mmVGT_DMA_INDEX_TYPE)/sizeof(mmVGT_DMA_INDEX_TYPE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_EN", REG_MMIO, 0xA2A1, &mmVGT_PRIMITIVEID_EN[0], sizeof(mmVGT_PRIMITIVEID_EN)/sizeof(mmVGT_PRIMITIVEID_EN[0]), 0, 0 },
+	{ "mmVGT_DMA_NUM_INSTANCES", REG_MMIO, 0xA2A2, &mmVGT_DMA_NUM_INSTANCES[0], sizeof(mmVGT_DMA_NUM_INSTANCES)/sizeof(mmVGT_DMA_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_RESET", REG_MMIO, 0xA2A3, &mmVGT_PRIMITIVEID_RESET[0], sizeof(mmVGT_PRIMITIVEID_RESET)/sizeof(mmVGT_PRIMITIVEID_RESET[0]), 0, 0 },
+	{ "mmVGT_EVENT_INITIATOR", REG_MMIO, 0xA2A4, &mmVGT_EVENT_INITIATOR[0], sizeof(mmVGT_EVENT_INITIATOR)/sizeof(mmVGT_EVENT_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_EN", REG_MMIO, 0xA2A5, &mmVGT_MULTI_PRIM_IB_RESET_EN[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_0", REG_MMIO, 0xA2A8, &mmVGT_INSTANCE_STEP_RATE_0[0], sizeof(mmVGT_INSTANCE_STEP_RATE_0)/sizeof(mmVGT_INSTANCE_STEP_RATE_0[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_1", REG_MMIO, 0xA2A9, &mmVGT_INSTANCE_STEP_RATE_1[0], sizeof(mmVGT_INSTANCE_STEP_RATE_1)/sizeof(mmVGT_INSTANCE_STEP_RATE_1[0]), 0, 0 },
+	{ "mmIA_MULTI_VGT_PARAM", REG_MMIO, 0xA2AA, &mmIA_MULTI_VGT_PARAM[0], sizeof(mmIA_MULTI_VGT_PARAM)/sizeof(mmIA_MULTI_VGT_PARAM[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_ITEMSIZE", REG_MMIO, 0xA2AB, &mmVGT_ESGS_RING_ITEMSIZE[0], sizeof(mmVGT_ESGS_RING_ITEMSIZE)/sizeof(mmVGT_ESGS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_ITEMSIZE", REG_MMIO, 0xA2AC, &mmVGT_GSVS_RING_ITEMSIZE[0], sizeof(mmVGT_GSVS_RING_ITEMSIZE)/sizeof(mmVGT_GSVS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_REUSE_OFF", REG_MMIO, 0xA2AD, &mmVGT_REUSE_OFF[0], sizeof(mmVGT_REUSE_OFF)/sizeof(mmVGT_REUSE_OFF[0]), 0, 0 },
+	{ "mmVGT_VTX_CNT_EN", REG_MMIO, 0xA2AE, &mmVGT_VTX_CNT_EN[0], sizeof(mmVGT_VTX_CNT_EN)/sizeof(mmVGT_VTX_CNT_EN[0]), 0, 0 },
+	{ "mmDB_HTILE_SURFACE", REG_MMIO, 0xA2AF, &mmDB_HTILE_SURFACE[0], sizeof(mmDB_HTILE_SURFACE)/sizeof(mmDB_HTILE_SURFACE[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE0", REG_MMIO, 0xA2B0, &mmDB_SRESULTS_COMPARE_STATE0[0], sizeof(mmDB_SRESULTS_COMPARE_STATE0)/sizeof(mmDB_SRESULTS_COMPARE_STATE0[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE1", REG_MMIO, 0xA2B1, &mmDB_SRESULTS_COMPARE_STATE1[0], sizeof(mmDB_SRESULTS_COMPARE_STATE1)/sizeof(mmDB_SRESULTS_COMPARE_STATE1[0]), 0, 0 },
+	{ "mmDB_PRELOAD_CONTROL", REG_MMIO, 0xA2B2, &mmDB_PRELOAD_CONTROL[0], sizeof(mmDB_PRELOAD_CONTROL)/sizeof(mmDB_PRELOAD_CONTROL[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_0", REG_MMIO, 0xA2B4, &mmVGT_STRMOUT_BUFFER_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_0", REG_MMIO, 0xA2B5, &mmVGT_STRMOUT_VTX_STRIDE_0[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_0)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_0", REG_MMIO, 0xA2B7, &mmVGT_STRMOUT_BUFFER_OFFSET_0[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_1", REG_MMIO, 0xA2B8, &mmVGT_STRMOUT_BUFFER_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_1", REG_MMIO, 0xA2B9, &mmVGT_STRMOUT_VTX_STRIDE_1[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_1)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_1", REG_MMIO, 0xA2BB, &mmVGT_STRMOUT_BUFFER_OFFSET_1[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_2", REG_MMIO, 0xA2BC, &mmVGT_STRMOUT_BUFFER_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_2", REG_MMIO, 0xA2BD, &mmVGT_STRMOUT_VTX_STRIDE_2[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_2)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_2", REG_MMIO, 0xA2BF, &mmVGT_STRMOUT_BUFFER_OFFSET_2[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_3", REG_MMIO, 0xA2C0, &mmVGT_STRMOUT_BUFFER_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_3", REG_MMIO, 0xA2C1, &mmVGT_STRMOUT_VTX_STRIDE_3[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_3)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_3", REG_MMIO, 0xA2C3, &mmVGT_STRMOUT_BUFFER_OFFSET_3[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET", REG_MMIO, 0xA2CA, &mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE", REG_MMIO, 0xA2CB, &mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", REG_MMIO, 0xA2CC, &mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0]), 0, 0 },
+	{ "mmVGT_GS_MAX_VERT_OUT", REG_MMIO, 0xA2CE, &mmVGT_GS_MAX_VERT_OUT[0], sizeof(mmVGT_GS_MAX_VERT_OUT)/sizeof(mmVGT_GS_MAX_VERT_OUT[0]), 0, 0 },
+	{ "mmVGT_SHADER_STAGES_EN", REG_MMIO, 0xA2D5, &mmVGT_SHADER_STAGES_EN[0], sizeof(mmVGT_SHADER_STAGES_EN)/sizeof(mmVGT_SHADER_STAGES_EN[0]), 0, 0 },
+	{ "mmVGT_LS_HS_CONFIG", REG_MMIO, 0xA2D6, &mmVGT_LS_HS_CONFIG[0], sizeof(mmVGT_LS_HS_CONFIG)/sizeof(mmVGT_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE", REG_MMIO, 0xA2D7, &mmVGT_GS_VERT_ITEMSIZE[0], sizeof(mmVGT_GS_VERT_ITEMSIZE)/sizeof(mmVGT_GS_VERT_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_1", REG_MMIO, 0xA2D8, &mmVGT_GS_VERT_ITEMSIZE_1[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_1)/sizeof(mmVGT_GS_VERT_ITEMSIZE_1[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_2", REG_MMIO, 0xA2D9, &mmVGT_GS_VERT_ITEMSIZE_2[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_2)/sizeof(mmVGT_GS_VERT_ITEMSIZE_2[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_3", REG_MMIO, 0xA2DA, &mmVGT_GS_VERT_ITEMSIZE_3[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_3)/sizeof(mmVGT_GS_VERT_ITEMSIZE_3[0]), 0, 0 },
+	{ "mmVGT_TF_PARAM", REG_MMIO, 0xA2DB, &mmVGT_TF_PARAM[0], sizeof(mmVGT_TF_PARAM)/sizeof(mmVGT_TF_PARAM[0]), 0, 0 },
+	{ "mmDB_ALPHA_TO_MASK", REG_MMIO, 0xA2DC, &mmDB_ALPHA_TO_MASK[0], sizeof(mmDB_ALPHA_TO_MASK)/sizeof(mmDB_ALPHA_TO_MASK[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_DB_FMT_CNTL", REG_MMIO, 0xA2DE, &mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0], sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL)/sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_CLAMP", REG_MMIO, 0xA2DF, &mmPA_SU_POLY_OFFSET_CLAMP[0], sizeof(mmPA_SU_POLY_OFFSET_CLAMP)/sizeof(mmPA_SU_POLY_OFFSET_CLAMP[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_SCALE", REG_MMIO, 0xA2E0, &mmPA_SU_POLY_OFFSET_FRONT_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_OFFSET", REG_MMIO, 0xA2E1, &mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_SCALE", REG_MMIO, 0xA2E2, &mmPA_SU_POLY_OFFSET_BACK_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_OFFSET", REG_MMIO, 0xA2E3, &mmPA_SU_POLY_OFFSET_BACK_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET[0]), 0, 0 },
+	{ "mmVGT_GS_INSTANCE_CNT", REG_MMIO, 0xA2E4, &mmVGT_GS_INSTANCE_CNT[0], sizeof(mmVGT_GS_INSTANCE_CNT)/sizeof(mmVGT_GS_INSTANCE_CNT[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_CONFIG", REG_MMIO, 0xA2E5, &mmVGT_STRMOUT_CONFIG[0], sizeof(mmVGT_STRMOUT_CONFIG)/sizeof(mmVGT_STRMOUT_CONFIG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_CONFIG", REG_MMIO, 0xA2E6, &mmVGT_STRMOUT_BUFFER_CONFIG[0], sizeof(mmVGT_STRMOUT_BUFFER_CONFIG)/sizeof(mmVGT_STRMOUT_BUFFER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_0", REG_MMIO, 0xA2F5, &mmPA_SC_CENTROID_PRIORITY_0[0], sizeof(mmPA_SC_CENTROID_PRIORITY_0)/sizeof(mmPA_SC_CENTROID_PRIORITY_0[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_1", REG_MMIO, 0xA2F6, &mmPA_SC_CENTROID_PRIORITY_1[0], sizeof(mmPA_SC_CENTROID_PRIORITY_1)/sizeof(mmPA_SC_CENTROID_PRIORITY_1[0]), 0, 0 },
+	{ "mmPA_SC_LINE_CNTL", REG_MMIO, 0xA2F7, &mmPA_SC_LINE_CNTL[0], sizeof(mmPA_SC_LINE_CNTL)/sizeof(mmPA_SC_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_AA_CONFIG", REG_MMIO, 0xA2F8, &mmPA_SC_AA_CONFIG[0], sizeof(mmPA_SC_AA_CONFIG)/sizeof(mmPA_SC_AA_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_VTX_CNTL", REG_MMIO, 0xA2F9, &mmPA_SU_VTX_CNTL[0], sizeof(mmPA_SU_VTX_CNTL)/sizeof(mmPA_SU_VTX_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_CLIP_ADJ", REG_MMIO, 0xA2FA, &mmPA_CL_GB_VERT_CLIP_ADJ[0], sizeof(mmPA_CL_GB_VERT_CLIP_ADJ)/sizeof(mmPA_CL_GB_VERT_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_DISC_ADJ", REG_MMIO, 0xA2FB, &mmPA_CL_GB_VERT_DISC_ADJ[0], sizeof(mmPA_CL_GB_VERT_DISC_ADJ)/sizeof(mmPA_CL_GB_VERT_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_CLIP_ADJ", REG_MMIO, 0xA2FC, &mmPA_CL_GB_HORZ_CLIP_ADJ[0], sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ)/sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_DISC_ADJ", REG_MMIO, 0xA2FD, &mmPA_CL_GB_HORZ_DISC_ADJ[0], sizeof(mmPA_CL_GB_HORZ_DISC_ADJ)/sizeof(mmPA_CL_GB_HORZ_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", REG_MMIO, 0xA2FE, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", REG_MMIO, 0xA2FF, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", REG_MMIO, 0xA300, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", REG_MMIO, 0xA301, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", REG_MMIO, 0xA302, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", REG_MMIO, 0xA303, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", REG_MMIO, 0xA304, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", REG_MMIO, 0xA305, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", REG_MMIO, 0xA306, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", REG_MMIO, 0xA307, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", REG_MMIO, 0xA308, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", REG_MMIO, 0xA309, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", REG_MMIO, 0xA30A, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", REG_MMIO, 0xA30B, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", REG_MMIO, 0xA30C, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", REG_MMIO, 0xA30D, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y0_X1Y0", REG_MMIO, 0xA30E, &mmPA_SC_AA_MASK_X0Y0_X1Y0[0], sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0)/sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y1_X1Y1", REG_MMIO, 0xA30F, &mmPA_SC_AA_MASK_X0Y1_X1Y1[0], sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1)/sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1[0]), 0, 0 },
+	{ "mmVGT_VERTEX_REUSE_BLOCK_CNTL", REG_MMIO, 0xA316, &mmVGT_VERTEX_REUSE_BLOCK_CNTL[0], sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL)/sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL[0]), 0, 0 },
+	{ "mmVGT_OUT_DEALLOC_CNTL", REG_MMIO, 0xA317, &mmVGT_OUT_DEALLOC_CNTL[0], sizeof(mmVGT_OUT_DEALLOC_CNTL)/sizeof(mmVGT_OUT_DEALLOC_CNTL[0]), 0, 0 },
+	{ "mmCB_COLOR0_BASE", REG_MMIO, 0xA318, &mmCB_COLOR0_BASE[0], sizeof(mmCB_COLOR0_BASE)/sizeof(mmCB_COLOR0_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR0_PITCH", REG_MMIO, 0xA319, &mmCB_COLOR0_PITCH[0], sizeof(mmCB_COLOR0_PITCH)/sizeof(mmCB_COLOR0_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR0_SLICE", REG_MMIO, 0xA31A, &mmCB_COLOR0_SLICE[0], sizeof(mmCB_COLOR0_SLICE)/sizeof(mmCB_COLOR0_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_VIEW", REG_MMIO, 0xA31B, &mmCB_COLOR0_VIEW[0], sizeof(mmCB_COLOR0_VIEW)/sizeof(mmCB_COLOR0_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR0_INFO", REG_MMIO, 0xA31C, &mmCB_COLOR0_INFO[0], sizeof(mmCB_COLOR0_INFO)/sizeof(mmCB_COLOR0_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR0_ATTRIB", REG_MMIO, 0xA31D, &mmCB_COLOR0_ATTRIB[0], sizeof(mmCB_COLOR0_ATTRIB)/sizeof(mmCB_COLOR0_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK", REG_MMIO, 0xA31F, &mmCB_COLOR0_CMASK[0], sizeof(mmCB_COLOR0_CMASK)/sizeof(mmCB_COLOR0_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK_SLICE", REG_MMIO, 0xA320, &mmCB_COLOR0_CMASK_SLICE[0], sizeof(mmCB_COLOR0_CMASK_SLICE)/sizeof(mmCB_COLOR0_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK", REG_MMIO, 0xA321, &mmCB_COLOR0_FMASK[0], sizeof(mmCB_COLOR0_FMASK)/sizeof(mmCB_COLOR0_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK_SLICE", REG_MMIO, 0xA322, &mmCB_COLOR0_FMASK_SLICE[0], sizeof(mmCB_COLOR0_FMASK_SLICE)/sizeof(mmCB_COLOR0_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD0", REG_MMIO, 0xA323, &mmCB_COLOR0_CLEAR_WORD0[0], sizeof(mmCB_COLOR0_CLEAR_WORD0)/sizeof(mmCB_COLOR0_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD1", REG_MMIO, 0xA324, &mmCB_COLOR0_CLEAR_WORD1[0], sizeof(mmCB_COLOR0_CLEAR_WORD1)/sizeof(mmCB_COLOR0_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR1_BASE", REG_MMIO, 0xA327, &mmCB_COLOR1_BASE[0], sizeof(mmCB_COLOR1_BASE)/sizeof(mmCB_COLOR1_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR1_PITCH", REG_MMIO, 0xA328, &mmCB_COLOR1_PITCH[0], sizeof(mmCB_COLOR1_PITCH)/sizeof(mmCB_COLOR1_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR1_SLICE", REG_MMIO, 0xA329, &mmCB_COLOR1_SLICE[0], sizeof(mmCB_COLOR1_SLICE)/sizeof(mmCB_COLOR1_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_VIEW", REG_MMIO, 0xA32A, &mmCB_COLOR1_VIEW[0], sizeof(mmCB_COLOR1_VIEW)/sizeof(mmCB_COLOR1_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR1_INFO", REG_MMIO, 0xA32B, &mmCB_COLOR1_INFO[0], sizeof(mmCB_COLOR1_INFO)/sizeof(mmCB_COLOR1_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR1_ATTRIB", REG_MMIO, 0xA32C, &mmCB_COLOR1_ATTRIB[0], sizeof(mmCB_COLOR1_ATTRIB)/sizeof(mmCB_COLOR1_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK", REG_MMIO, 0xA32E, &mmCB_COLOR1_CMASK[0], sizeof(mmCB_COLOR1_CMASK)/sizeof(mmCB_COLOR1_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK_SLICE", REG_MMIO, 0xA32F, &mmCB_COLOR1_CMASK_SLICE[0], sizeof(mmCB_COLOR1_CMASK_SLICE)/sizeof(mmCB_COLOR1_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK", REG_MMIO, 0xA330, &mmCB_COLOR1_FMASK[0], sizeof(mmCB_COLOR1_FMASK)/sizeof(mmCB_COLOR1_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK_SLICE", REG_MMIO, 0xA331, &mmCB_COLOR1_FMASK_SLICE[0], sizeof(mmCB_COLOR1_FMASK_SLICE)/sizeof(mmCB_COLOR1_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD0", REG_MMIO, 0xA332, &mmCB_COLOR1_CLEAR_WORD0[0], sizeof(mmCB_COLOR1_CLEAR_WORD0)/sizeof(mmCB_COLOR1_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD1", REG_MMIO, 0xA333, &mmCB_COLOR1_CLEAR_WORD1[0], sizeof(mmCB_COLOR1_CLEAR_WORD1)/sizeof(mmCB_COLOR1_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR2_BASE", REG_MMIO, 0xA336, &mmCB_COLOR2_BASE[0], sizeof(mmCB_COLOR2_BASE)/sizeof(mmCB_COLOR2_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR2_PITCH", REG_MMIO, 0xA337, &mmCB_COLOR2_PITCH[0], sizeof(mmCB_COLOR2_PITCH)/sizeof(mmCB_COLOR2_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR2_SLICE", REG_MMIO, 0xA338, &mmCB_COLOR2_SLICE[0], sizeof(mmCB_COLOR2_SLICE)/sizeof(mmCB_COLOR2_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_VIEW", REG_MMIO, 0xA339, &mmCB_COLOR2_VIEW[0], sizeof(mmCB_COLOR2_VIEW)/sizeof(mmCB_COLOR2_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR2_INFO", REG_MMIO, 0xA33A, &mmCB_COLOR2_INFO[0], sizeof(mmCB_COLOR2_INFO)/sizeof(mmCB_COLOR2_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR2_ATTRIB", REG_MMIO, 0xA33B, &mmCB_COLOR2_ATTRIB[0], sizeof(mmCB_COLOR2_ATTRIB)/sizeof(mmCB_COLOR2_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK", REG_MMIO, 0xA33D, &mmCB_COLOR2_CMASK[0], sizeof(mmCB_COLOR2_CMASK)/sizeof(mmCB_COLOR2_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK_SLICE", REG_MMIO, 0xA33E, &mmCB_COLOR2_CMASK_SLICE[0], sizeof(mmCB_COLOR2_CMASK_SLICE)/sizeof(mmCB_COLOR2_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK", REG_MMIO, 0xA33F, &mmCB_COLOR2_FMASK[0], sizeof(mmCB_COLOR2_FMASK)/sizeof(mmCB_COLOR2_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK_SLICE", REG_MMIO, 0xA340, &mmCB_COLOR2_FMASK_SLICE[0], sizeof(mmCB_COLOR2_FMASK_SLICE)/sizeof(mmCB_COLOR2_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD0", REG_MMIO, 0xA341, &mmCB_COLOR2_CLEAR_WORD0[0], sizeof(mmCB_COLOR2_CLEAR_WORD0)/sizeof(mmCB_COLOR2_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD1", REG_MMIO, 0xA342, &mmCB_COLOR2_CLEAR_WORD1[0], sizeof(mmCB_COLOR2_CLEAR_WORD1)/sizeof(mmCB_COLOR2_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR3_BASE", REG_MMIO, 0xA345, &mmCB_COLOR3_BASE[0], sizeof(mmCB_COLOR3_BASE)/sizeof(mmCB_COLOR3_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR3_PITCH", REG_MMIO, 0xA346, &mmCB_COLOR3_PITCH[0], sizeof(mmCB_COLOR3_PITCH)/sizeof(mmCB_COLOR3_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR3_SLICE", REG_MMIO, 0xA347, &mmCB_COLOR3_SLICE[0], sizeof(mmCB_COLOR3_SLICE)/sizeof(mmCB_COLOR3_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_VIEW", REG_MMIO, 0xA348, &mmCB_COLOR3_VIEW[0], sizeof(mmCB_COLOR3_VIEW)/sizeof(mmCB_COLOR3_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR3_INFO", REG_MMIO, 0xA349, &mmCB_COLOR3_INFO[0], sizeof(mmCB_COLOR3_INFO)/sizeof(mmCB_COLOR3_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR3_ATTRIB", REG_MMIO, 0xA34A, &mmCB_COLOR3_ATTRIB[0], sizeof(mmCB_COLOR3_ATTRIB)/sizeof(mmCB_COLOR3_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK", REG_MMIO, 0xA34C, &mmCB_COLOR3_CMASK[0], sizeof(mmCB_COLOR3_CMASK)/sizeof(mmCB_COLOR3_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK_SLICE", REG_MMIO, 0xA34D, &mmCB_COLOR3_CMASK_SLICE[0], sizeof(mmCB_COLOR3_CMASK_SLICE)/sizeof(mmCB_COLOR3_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK", REG_MMIO, 0xA34E, &mmCB_COLOR3_FMASK[0], sizeof(mmCB_COLOR3_FMASK)/sizeof(mmCB_COLOR3_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK_SLICE", REG_MMIO, 0xA34F, &mmCB_COLOR3_FMASK_SLICE[0], sizeof(mmCB_COLOR3_FMASK_SLICE)/sizeof(mmCB_COLOR3_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD0", REG_MMIO, 0xA350, &mmCB_COLOR3_CLEAR_WORD0[0], sizeof(mmCB_COLOR3_CLEAR_WORD0)/sizeof(mmCB_COLOR3_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD1", REG_MMIO, 0xA351, &mmCB_COLOR3_CLEAR_WORD1[0], sizeof(mmCB_COLOR3_CLEAR_WORD1)/sizeof(mmCB_COLOR3_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR4_BASE", REG_MMIO, 0xA354, &mmCB_COLOR4_BASE[0], sizeof(mmCB_COLOR4_BASE)/sizeof(mmCB_COLOR4_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR4_PITCH", REG_MMIO, 0xA355, &mmCB_COLOR4_PITCH[0], sizeof(mmCB_COLOR4_PITCH)/sizeof(mmCB_COLOR4_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR4_SLICE", REG_MMIO, 0xA356, &mmCB_COLOR4_SLICE[0], sizeof(mmCB_COLOR4_SLICE)/sizeof(mmCB_COLOR4_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_VIEW", REG_MMIO, 0xA357, &mmCB_COLOR4_VIEW[0], sizeof(mmCB_COLOR4_VIEW)/sizeof(mmCB_COLOR4_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR4_INFO", REG_MMIO, 0xA358, &mmCB_COLOR4_INFO[0], sizeof(mmCB_COLOR4_INFO)/sizeof(mmCB_COLOR4_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR4_ATTRIB", REG_MMIO, 0xA359, &mmCB_COLOR4_ATTRIB[0], sizeof(mmCB_COLOR4_ATTRIB)/sizeof(mmCB_COLOR4_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK", REG_MMIO, 0xA35B, &mmCB_COLOR4_CMASK[0], sizeof(mmCB_COLOR4_CMASK)/sizeof(mmCB_COLOR4_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK_SLICE", REG_MMIO, 0xA35C, &mmCB_COLOR4_CMASK_SLICE[0], sizeof(mmCB_COLOR4_CMASK_SLICE)/sizeof(mmCB_COLOR4_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK", REG_MMIO, 0xA35D, &mmCB_COLOR4_FMASK[0], sizeof(mmCB_COLOR4_FMASK)/sizeof(mmCB_COLOR4_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK_SLICE", REG_MMIO, 0xA35E, &mmCB_COLOR4_FMASK_SLICE[0], sizeof(mmCB_COLOR4_FMASK_SLICE)/sizeof(mmCB_COLOR4_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD0", REG_MMIO, 0xA35F, &mmCB_COLOR4_CLEAR_WORD0[0], sizeof(mmCB_COLOR4_CLEAR_WORD0)/sizeof(mmCB_COLOR4_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD1", REG_MMIO, 0xA360, &mmCB_COLOR4_CLEAR_WORD1[0], sizeof(mmCB_COLOR4_CLEAR_WORD1)/sizeof(mmCB_COLOR4_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR5_BASE", REG_MMIO, 0xA363, &mmCB_COLOR5_BASE[0], sizeof(mmCB_COLOR5_BASE)/sizeof(mmCB_COLOR5_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR5_PITCH", REG_MMIO, 0xA364, &mmCB_COLOR5_PITCH[0], sizeof(mmCB_COLOR5_PITCH)/sizeof(mmCB_COLOR5_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR5_SLICE", REG_MMIO, 0xA365, &mmCB_COLOR5_SLICE[0], sizeof(mmCB_COLOR5_SLICE)/sizeof(mmCB_COLOR5_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_VIEW", REG_MMIO, 0xA366, &mmCB_COLOR5_VIEW[0], sizeof(mmCB_COLOR5_VIEW)/sizeof(mmCB_COLOR5_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR5_INFO", REG_MMIO, 0xA367, &mmCB_COLOR5_INFO[0], sizeof(mmCB_COLOR5_INFO)/sizeof(mmCB_COLOR5_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR5_ATTRIB", REG_MMIO, 0xA368, &mmCB_COLOR5_ATTRIB[0], sizeof(mmCB_COLOR5_ATTRIB)/sizeof(mmCB_COLOR5_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK", REG_MMIO, 0xA36A, &mmCB_COLOR5_CMASK[0], sizeof(mmCB_COLOR5_CMASK)/sizeof(mmCB_COLOR5_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK_SLICE", REG_MMIO, 0xA36B, &mmCB_COLOR5_CMASK_SLICE[0], sizeof(mmCB_COLOR5_CMASK_SLICE)/sizeof(mmCB_COLOR5_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK", REG_MMIO, 0xA36C, &mmCB_COLOR5_FMASK[0], sizeof(mmCB_COLOR5_FMASK)/sizeof(mmCB_COLOR5_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK_SLICE", REG_MMIO, 0xA36D, &mmCB_COLOR5_FMASK_SLICE[0], sizeof(mmCB_COLOR5_FMASK_SLICE)/sizeof(mmCB_COLOR5_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD0", REG_MMIO, 0xA36E, &mmCB_COLOR5_CLEAR_WORD0[0], sizeof(mmCB_COLOR5_CLEAR_WORD0)/sizeof(mmCB_COLOR5_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD1", REG_MMIO, 0xA36F, &mmCB_COLOR5_CLEAR_WORD1[0], sizeof(mmCB_COLOR5_CLEAR_WORD1)/sizeof(mmCB_COLOR5_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR6_BASE", REG_MMIO, 0xA372, &mmCB_COLOR6_BASE[0], sizeof(mmCB_COLOR6_BASE)/sizeof(mmCB_COLOR6_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR6_PITCH", REG_MMIO, 0xA373, &mmCB_COLOR6_PITCH[0], sizeof(mmCB_COLOR6_PITCH)/sizeof(mmCB_COLOR6_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR6_SLICE", REG_MMIO, 0xA374, &mmCB_COLOR6_SLICE[0], sizeof(mmCB_COLOR6_SLICE)/sizeof(mmCB_COLOR6_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_VIEW", REG_MMIO, 0xA375, &mmCB_COLOR6_VIEW[0], sizeof(mmCB_COLOR6_VIEW)/sizeof(mmCB_COLOR6_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR6_INFO", REG_MMIO, 0xA376, &mmCB_COLOR6_INFO[0], sizeof(mmCB_COLOR6_INFO)/sizeof(mmCB_COLOR6_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR6_ATTRIB", REG_MMIO, 0xA377, &mmCB_COLOR6_ATTRIB[0], sizeof(mmCB_COLOR6_ATTRIB)/sizeof(mmCB_COLOR6_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK", REG_MMIO, 0xA379, &mmCB_COLOR6_CMASK[0], sizeof(mmCB_COLOR6_CMASK)/sizeof(mmCB_COLOR6_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK_SLICE", REG_MMIO, 0xA37A, &mmCB_COLOR6_CMASK_SLICE[0], sizeof(mmCB_COLOR6_CMASK_SLICE)/sizeof(mmCB_COLOR6_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK", REG_MMIO, 0xA37B, &mmCB_COLOR6_FMASK[0], sizeof(mmCB_COLOR6_FMASK)/sizeof(mmCB_COLOR6_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK_SLICE", REG_MMIO, 0xA37C, &mmCB_COLOR6_FMASK_SLICE[0], sizeof(mmCB_COLOR6_FMASK_SLICE)/sizeof(mmCB_COLOR6_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD0", REG_MMIO, 0xA37D, &mmCB_COLOR6_CLEAR_WORD0[0], sizeof(mmCB_COLOR6_CLEAR_WORD0)/sizeof(mmCB_COLOR6_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD1", REG_MMIO, 0xA37E, &mmCB_COLOR6_CLEAR_WORD1[0], sizeof(mmCB_COLOR6_CLEAR_WORD1)/sizeof(mmCB_COLOR6_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR7_BASE", REG_MMIO, 0xA381, &mmCB_COLOR7_BASE[0], sizeof(mmCB_COLOR7_BASE)/sizeof(mmCB_COLOR7_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR7_PITCH", REG_MMIO, 0xA382, &mmCB_COLOR7_PITCH[0], sizeof(mmCB_COLOR7_PITCH)/sizeof(mmCB_COLOR7_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR7_SLICE", REG_MMIO, 0xA383, &mmCB_COLOR7_SLICE[0], sizeof(mmCB_COLOR7_SLICE)/sizeof(mmCB_COLOR7_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_VIEW", REG_MMIO, 0xA384, &mmCB_COLOR7_VIEW[0], sizeof(mmCB_COLOR7_VIEW)/sizeof(mmCB_COLOR7_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR7_INFO", REG_MMIO, 0xA385, &mmCB_COLOR7_INFO[0], sizeof(mmCB_COLOR7_INFO)/sizeof(mmCB_COLOR7_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR7_ATTRIB", REG_MMIO, 0xA386, &mmCB_COLOR7_ATTRIB[0], sizeof(mmCB_COLOR7_ATTRIB)/sizeof(mmCB_COLOR7_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK", REG_MMIO, 0xA388, &mmCB_COLOR7_CMASK[0], sizeof(mmCB_COLOR7_CMASK)/sizeof(mmCB_COLOR7_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK_SLICE", REG_MMIO, 0xA389, &mmCB_COLOR7_CMASK_SLICE[0], sizeof(mmCB_COLOR7_CMASK_SLICE)/sizeof(mmCB_COLOR7_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK", REG_MMIO, 0xA38A, &mmCB_COLOR7_FMASK[0], sizeof(mmCB_COLOR7_FMASK)/sizeof(mmCB_COLOR7_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK_SLICE", REG_MMIO, 0xA38B, &mmCB_COLOR7_FMASK_SLICE[0], sizeof(mmCB_COLOR7_FMASK_SLICE)/sizeof(mmCB_COLOR7_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD0", REG_MMIO, 0xA38C, &mmCB_COLOR7_CLEAR_WORD0[0], sizeof(mmCB_COLOR7_CLEAR_WORD0)/sizeof(mmCB_COLOR7_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD1", REG_MMIO, 0xA38D, &mmCB_COLOR7_CLEAR_WORD1[0], sizeof(mmCB_COLOR7_CLEAR_WORD1)/sizeof(mmCB_COLOR7_CLEAR_WORD1[0]), 0, 0 },
diff --git a/src/lib/ip/gfx70.c b/src/lib/ip/gfx70.c
new file mode 100644
index 0000000..e9bfa4b
--- /dev/null
+++ b/src/lib/ip/gfx70.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gfx70_bits.i"
+static const struct umr_reg gfx70_registers[] = {
+#include "gfx70_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_gfx70(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gfx70";
+	ip->no_regs = sizeof(gfx70_registers)/sizeof(gfx70_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gfx70_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 1) ? grant : deny;
+	memcpy(ip->regs, gfx70_registers, sizeof(gfx70_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gfx70_bits.i b/src/lib/ip/gfx70_bits.i
new file mode 100644
index 0000000..b43c14d
--- /dev/null
+++ b/src/lib/ip/gfx70_bits.i
@@ -0,0 +1,11943 @@
+static struct umr_bitfield CSPRIV_CONNECT[] = {
+	 { "DOORBELL_OFFSET", 0, 20, &umr_bitfield_default },
+	 { "QUEUE_ID", 21, 23, &umr_bitfield_default },
+	 { "VMID", 26, 29, &umr_bitfield_default },
+	 { "UNORD_DISP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CSPRIV_THREAD_TRACE_TG0[] = {
+	 { "TGID_X", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CSPRIV_THREAD_TRACE_EVENT[] = {
+	 { "EVENT_ID", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_CNTL[] = {
+	 { "READ_TIMEOUT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SKEW_CNTL[] = {
+	 { "SKEW_TOP_THRESHOLD", 0, 5, &umr_bitfield_default },
+	 { "SKEW_COUNT", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_STATUS2[] = {
+	 { "ME0PIPE1_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "ME0PIPE1_CF_RQ_PENDING", 4, 4, &umr_bitfield_default },
+	 { "ME0PIPE1_PF_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME1PIPE0_RQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "ME1PIPE1_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME1PIPE2_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "ME1PIPE3_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "ME2PIPE0_RQ_PENDING", 10, 10, &umr_bitfield_default },
+	 { "ME2PIPE1_RQ_PENDING", 11, 11, &umr_bitfield_default },
+	 { "ME2PIPE2_RQ_PENDING", 12, 12, &umr_bitfield_default },
+	 { "ME2PIPE3_RQ_PENDING", 13, 13, &umr_bitfield_default },
+	 { "RLC_RQ_PENDING", 14, 14, &umr_bitfield_default },
+	 { "RLC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TC_BUSY", 25, 25, &umr_bitfield_default },
+	 { "CPF_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPG_BUSY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_PWR_CNTL[] = {
+	 { "REQ_TYPE", 0, 3, &umr_bitfield_default },
+	 { "RSP_TYPE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_STATUS[] = {
+	 { "ME0PIPE0_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "SRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME0PIPE0_CF_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME0PIPE0_PF_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "GDS_DMA_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "DB_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "CB_CLEAN", 13, 13, &umr_bitfield_default },
+	 { "TA_BUSY", 14, 14, &umr_bitfield_default },
+	 { "GDS_BUSY", 15, 15, &umr_bitfield_default },
+	 { "WD_BUSY_NO_DMA", 16, 16, &umr_bitfield_default },
+	 { "VGT_BUSY", 17, 17, &umr_bitfield_default },
+	 { "IA_BUSY_NO_DMA", 18, 18, &umr_bitfield_default },
+	 { "IA_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SX_BUSY", 20, 20, &umr_bitfield_default },
+	 { "WD_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SPI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "BCI_BUSY", 23, 23, &umr_bitfield_default },
+	 { "SC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "PA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "DB_BUSY", 26, 26, &umr_bitfield_default },
+	 { "CP_COHERENCY_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CP_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "GUI_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_STATUS_SE0[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_STATUS_SE1[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SOFT_RESET[] = {
+	 { "SOFT_RESET_CP", 0, 0, &umr_bitfield_default },
+	 { "SOFT_RESET_RLC", 2, 2, &umr_bitfield_default },
+	 { "SOFT_RESET_GFX", 16, 16, &umr_bitfield_default },
+	 { "SOFT_RESET_CPF", 17, 17, &umr_bitfield_default },
+	 { "SOFT_RESET_CPC", 18, 18, &umr_bitfield_default },
+	 { "SOFT_RESET_CPG", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_DEBUG_CNTL[] = {
+	 { "GRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_GFX_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_WAIT_IDLE_CLOCKS[] = {
+	 { "WAIT_IDLE_CLOCKS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_STATUS_SE2[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_STATUS_SE3[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_DEBUG[] = {
+	 { "IGNORE_RDY", 1, 1, &umr_bitfield_default },
+	 { "IGNORE_FAO", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_READ_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "SNAPSHOT_FREE_CNTRS", 7, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_GUI_ACTIVE", 8, 11, &umr_bitfield_default },
+	 { "GFX_CLOCK_DOMAIN_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_DEBUG_SNAPSHOT[] = {
+	 { "CPF_RDY", 0, 0, &umr_bitfield_default },
+	 { "CPG_RDY", 1, 1, &umr_bitfield_default },
+	 { "SRBM_RDY", 2, 2, &umr_bitfield_default },
+	 { "WD_ME0PIPE0_RDY", 3, 3, &umr_bitfield_default },
+	 { "WD_ME0PIPE1_RDY", 4, 4, &umr_bitfield_default },
+	 { "GDS_RDY", 5, 5, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY0", 6, 6, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY0", 7, 7, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY0", 8, 8, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY0", 9, 9, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY0", 10, 10, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY0", 11, 11, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY0", 12, 12, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY0", 13, 13, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY1", 14, 14, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY1", 15, 15, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY1", 16, 16, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY1", 17, 17, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY1", 18, 18, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY1", 19, 19, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY1", 20, 20, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY1", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_READ_ERROR[] = {
+	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "READ_PIPEID", 20, 21, &umr_bitfield_default },
+	 { "READ_MEID", 22, 23, &umr_bitfield_default },
+	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_READ_ERROR2[] = {
+	 { "READ_REQUESTER_SRBM", 17, 17, &umr_bitfield_default },
+	 { "READ_REQUESTER_RLC", 18, 18, &umr_bitfield_default },
+	 { "READ_REQUESTER_GDS_DMA", 19, 19, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE0_CF", 20, 20, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE0_PF", 21, 21, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE1_CF", 22, 22, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE1_PF", 23, 23, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE0", 24, 24, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE1", 25, 25, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE2", 26, 26, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE3", 27, 27, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE0", 28, 28, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE1", 29, 29, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE2", 30, 30, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_INT_CNTL[] = {
+	 { "RDERR_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GUI_IDLE_INT_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield DEBUG_INDEX[] = {
+	 { "DEBUG_INDEX", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield DEBUG_DATA[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_NOWHERE[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPC_STATUS[] = {
+	 { "MEC1_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MEC2_BUSY", 1, 1, &umr_bitfield_default },
+	 { "DC0_BUSY", 2, 2, &umr_bitfield_default },
+	 { "DC1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "RCIU1_BUSY", 4, 4, &umr_bitfield_default },
+	 { "RCIU2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "ROQ1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "ROQ2_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MIU_RDREQ_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MIU_WRREQ_BUSY", 9, 9, &umr_bitfield_default },
+	 { "TCIU_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 11, 11, &umr_bitfield_default },
+	 { "QU_BUSY", 12, 12, &umr_bitfield_default },
+	 { "CPG_CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPF_CPC_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CPC_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPC_BUSY_STAT[] = {
+	 { "MEC1_LOAD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MEC1_SEMAPOHRE_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MEC1_MUTEX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "MEC1_MESSAGE_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MEC1_EOP_QUEUE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "MEC1_IQ_QUEUE_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MEC1_IB_QUEUE_BUSY", 6, 6, &umr_bitfield_default },
+	 { "MEC1_TC_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MEC1_DMA_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MEC1_PARTIAL_FLUSH_BUSY", 9, 9, &umr_bitfield_default },
+	 { "MEC1_PIPE0_BUSY", 10, 10, &umr_bitfield_default },
+	 { "MEC1_PIPE1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "MEC1_PIPE2_BUSY", 12, 12, &umr_bitfield_default },
+	 { "MEC1_PIPE3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "MEC2_LOAD_BUSY", 16, 16, &umr_bitfield_default },
+	 { "MEC2_SEMAPOHRE_BUSY", 17, 17, &umr_bitfield_default },
+	 { "MEC2_MUTEX_BUSY", 18, 18, &umr_bitfield_default },
+	 { "MEC2_MESSAGE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "MEC2_EOP_QUEUE_BUSY", 20, 20, &umr_bitfield_default },
+	 { "MEC2_IQ_QUEUE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "MEC2_IB_QUEUE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "MEC2_TC_BUSY", 23, 23, &umr_bitfield_default },
+	 { "MEC2_DMA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "MEC2_PARTIAL_FLUSH_BUSY", 25, 25, &umr_bitfield_default },
+	 { "MEC2_PIPE0_BUSY", 26, 26, &umr_bitfield_default },
+	 { "MEC2_PIPE1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "MEC2_PIPE2_BUSY", 28, 28, &umr_bitfield_default },
+	 { "MEC2_PIPE3_BUSY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPC_STALLED_STAT1[] = {
+	 { "MIU_RDREQ_FREE_STALL", 0, 0, &umr_bitfield_default },
+	 { "MIU_WRREQ_FREE_STALL", 1, 1, &umr_bitfield_default },
+	 { "RCIU_TX_FREE_STALL", 3, 3, &umr_bitfield_default },
+	 { "RCIU_PRIV_VIOLATION", 4, 4, &umr_bitfield_default },
+	 { "TCIU_TX_FREE_STALL", 6, 6, &umr_bitfield_default },
+	 { "MEC1_DECODING_PACKET", 8, 8, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_RCIU", 9, 9, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_RCIU_READ", 10, 10, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_MC_READ", 11, 11, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_MC_WR_ACK", 12, 12, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_ROQ_DATA", 13, 13, &umr_bitfield_default },
+	 { "MEC2_DECODING_PACKET", 16, 16, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_RCIU", 17, 17, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_RCIU_READ", 18, 18, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_MC_READ", 19, 19, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_MC_WR_ACK", 20, 20, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_ROQ_DATA", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPF_STATUS[] = {
+	 { "POST_WPTR_GFX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CSF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MIU_RDREQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "MIU_WRREQ_BUSY", 3, 3, &umr_bitfield_default },
+	 { "ROQ_ALIGN_BUSY", 4, 4, &umr_bitfield_default },
+	 { "ROQ_RING_BUSY", 5, 5, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 7, 7, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 8, 8, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 13, 13, &umr_bitfield_default },
+	 { "TCIU_BUSY", 14, 14, &umr_bitfield_default },
+	 { "HQD_BUSY", 15, 15, &umr_bitfield_default },
+	 { "CPC_CPF_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CPF_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPF_BUSY_STAT[] = {
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CSF_RING_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CSF_INDIRECT1_BUSY", 2, 2, &umr_bitfield_default },
+	 { "CSF_INDIRECT2_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CSF_STATE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CSF_CE_INDR1_BUSY", 5, 5, &umr_bitfield_default },
+	 { "CSF_CE_INDR2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CSF_ARBITER_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CSF_INPUT_BUSY", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_READ_TAGS", 9, 9, &umr_bitfield_default },
+	 { "HPD_PROCESSING_EOP_BUSY", 11, 11, &umr_bitfield_default },
+	 { "HQD_DISPATCH_BUSY", 12, 12, &umr_bitfield_default },
+	 { "HQD_IQ_TIMER_BUSY", 13, 13, &umr_bitfield_default },
+	 { "HQD_DMA_OFFLOAD_BUSY", 14, 14, &umr_bitfield_default },
+	 { "HQD_WAIT_SEMAPHORE_BUSY", 15, 15, &umr_bitfield_default },
+	 { "HQD_SIGNAL_SEMAPHORE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "HQD_MESSAGE_BUSY", 17, 17, &umr_bitfield_default },
+	 { "HQD_PQ_FETCHER_BUSY", 18, 18, &umr_bitfield_default },
+	 { "HQD_IB_FETCHER_BUSY", 19, 19, &umr_bitfield_default },
+	 { "HQD_IQ_FETCHER_BUSY", 20, 20, &umr_bitfield_default },
+	 { "HQD_EOP_FETCHER_BUSY", 21, 21, &umr_bitfield_default },
+	 { "HQD_CONSUMED_RPTR_BUSY", 22, 22, &umr_bitfield_default },
+	 { "HQD_FETCHER_ARB_BUSY", 23, 23, &umr_bitfield_default },
+	 { "HQD_ROQ_ALIGN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "HQD_ROQ_EOP_BUSY", 25, 25, &umr_bitfield_default },
+	 { "HQD_ROQ_IQ_BUSY", 26, 26, &umr_bitfield_default },
+	 { "HQD_ROQ_PQ_BUSY", 27, 27, &umr_bitfield_default },
+	 { "HQD_ROQ_IB_BUSY", 28, 28, &umr_bitfield_default },
+	 { "HQD_WPTR_POLL_BUSY", 29, 29, &umr_bitfield_default },
+	 { "HQD_PQ_BUSY", 30, 30, &umr_bitfield_default },
+	 { "HQD_IB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPF_STALLED_STAT1[] = {
+	 { "RING_FETCHING_DATA", 0, 0, &umr_bitfield_default },
+	 { "INDR1_FETCHING_DATA", 1, 1, &umr_bitfield_default },
+	 { "INDR2_FETCHING_DATA", 2, 2, &umr_bitfield_default },
+	 { "STATE_FETCHING_DATA", 3, 3, &umr_bitfield_default },
+	 { "MIU_WAITING_ON_RDREQ_FREE", 4, 4, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 5, 5, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPC_MC_CNTL[] = {
+	 { "PACK_DELAY_CNT", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPC_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC_CNTL[] = {
+	 { "MEC_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "MEC_ME2_HALT", 28, 28, &umr_bitfield_default },
+	 { "MEC_ME2_STEP", 29, 29, &umr_bitfield_default },
+	 { "MEC_ME1_HALT", 30, 30, &umr_bitfield_default },
+	 { "MEC_ME1_STEP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC_ME1_HEADER_DUMP[] = {
+	 { "HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC_ME2_HEADER_DUMP[] = {
+	 { "HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPC_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPC_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CPC_HALT_HYST_COUNT[] = {
+	 { "COUNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_COMPARE_COUNT[] = {
+	 { "COMPARE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_DE_COUNT[] = {
+	 { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DE_CE_COUNT[] = {
+	 { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DE_LAST_INVAL_COUNT[] = {
+	 { "LAST_INVAL_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DE_DE_COUNT[] = {
+	 { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STALLED_STAT3[] = {
+	 { "CE_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER", 2, 2, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_NOT_RDY", 3, 3, &umr_bitfield_default },
+	 { "CE_TO_RAM_DUMP_NOT_RDY", 4, 4, &umr_bitfield_default },
+	 { "CE_TO_RAM_WRITE_NOT_RDY", 5, 5, &umr_bitfield_default },
+	 { "CE_TO_INC_FIFO_NOT_RDY_TO_RCV", 6, 6, &umr_bitfield_default },
+	 { "CE_TO_WR_FIFO_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default },
+	 { "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV", 8, 8, &umr_bitfield_default },
+	 { "CE_WAITING_ON_BUFFER_DATA", 10, 10, &umr_bitfield_default },
+	 { "CE_WAITING_ON_CE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER", 12, 12, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER_UNDERFLOW", 13, 13, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 14, 14, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STALLED_STAT1[] = {
+	 { "RBIU_TO_DMA_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "RBIU_TO_SEM_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "RBIU_TO_MEMWR_NOT_RDY_TO_RCV", 4, 4, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_CE_BUFFER_FLAG", 10, 10, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_DE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "ME_STALLED_ON_TC_WR_CONFIRM", 12, 12, &umr_bitfield_default },
+	 { "ME_STALLED_ON_ATOMIC_RTN_DATA", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_ON_MC_READ_DATA", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_REG_READ_DATA", 15, 15, &umr_bitfield_default },
+	 { "MIU_WAITING_ON_RDREQ_FREE", 16, 16, &umr_bitfield_default },
+	 { "MIU_WAITING_ON_WRREQ_FREE", 17, 17, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GDS_FREE", 23, 23, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GRBM_FREE", 24, 24, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_VGT_FREE", 25, 25, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_ME_READ", 26, 26, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_DMA_READ", 27, 27, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_APPEND_READ", 28, 28, &umr_bitfield_default },
+	 { "RCIU_HALTED_BY_REG_VIOLATION", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STALLED_STAT2[] = {
+	 { "PFP_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "PFP_TO_MEQ_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "PFP_TO_RCIU_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "PFP_TO_VGT_WRITES_PENDING", 4, 4, &umr_bitfield_default },
+	 { "PFP_RCIU_READ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "PFP_MIU_READ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default },
+	 { "PFP_WAITING_ON_BUFFER_DATA", 8, 8, &umr_bitfield_default },
+	 { "ME_WAIT_ON_CE_COUNTER", 9, 9, &umr_bitfield_default },
+	 { "ME_WAIT_ON_AVAIL_BUFFER", 10, 10, &umr_bitfield_default },
+	 { "GFX_CNTX_NOT_AVAIL_TO_ME", 11, 11, &umr_bitfield_default },
+	 { "ME_RCIU_NOT_RDY_TO_RCV", 12, 12, &umr_bitfield_default },
+	 { "ME_TO_CONST_NOT_RDY_TO_RCV", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_PFP", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_PARTIAL_FLUSH", 15, 15, &umr_bitfield_default },
+	 { "MEQ_TO_ME_NOT_RDY_TO_RCV", 16, 16, &umr_bitfield_default },
+	 { "STQ_TO_ME_NOT_RDY_TO_RCV", 17, 17, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_STQ", 18, 18, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_TC_WR_CONFIRM", 19, 19, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_ATOMIC_RTN_DATA", 20, 20, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_SC_EOP_DONE", 21, 21, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_WR_CONFIRM", 22, 22, &umr_bitfield_default },
+	 { "STRMO_WR_OF_PRIM_DATA_PENDING", 23, 23, &umr_bitfield_default },
+	 { "PIPE_STATS_WR_DATA_PENDING", 24, 24, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_CS_DONE", 25, 25, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_PS_DONE", 26, 26, &umr_bitfield_default },
+	 { "APPEND_WAIT_ON_WR_CONFIRM", 27, 27, &umr_bitfield_default },
+	 { "APPEND_ACTIVE_PARTITION", 28, 28, &umr_bitfield_default },
+	 { "APPEND_WAITING_TO_SEND_MEMWRITE", 29, 29, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_IDLE_CNTXS", 30, 30, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_ALL_CLEAN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_BUSY_STAT[] = {
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COHER_CNT_NEQ_ZERO", 6, 6, &umr_bitfield_default },
+	 { "PFP_PARSING_PACKETS", 7, 7, &umr_bitfield_default },
+	 { "ME_PARSING_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "RCIU_PFP_BUSY", 9, 9, &umr_bitfield_default },
+	 { "RCIU_ME_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SEM_CMDFIFO_NOT_EMPTY", 12, 12, &umr_bitfield_default },
+	 { "SEM_FAILED_AND_HOLDING", 13, 13, &umr_bitfield_default },
+	 { "SEM_POLLING_FOR_PASS", 14, 14, &umr_bitfield_default },
+	 { "GFX_CONTEXT_BUSY", 15, 15, &umr_bitfield_default },
+	 { "ME_PARSER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "EOP_DONE_BUSY", 18, 18, &umr_bitfield_default },
+	 { "STRM_OUT_BUSY", 19, 19, &umr_bitfield_default },
+	 { "PIPE_STATS_BUSY", 20, 20, &umr_bitfield_default },
+	 { "RCIU_CE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "CE_PARSING_PACKETS", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STAT[] = {
+	 { "MIU_RDREQ_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MIU_WRREQ_BUSY", 8, 8, &umr_bitfield_default },
+	 { "ROQ_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DC_BUSY", 13, 13, &umr_bitfield_default },
+	 { "PFP_BUSY", 15, 15, &umr_bitfield_default },
+	 { "MEQ_BUSY", 16, 16, &umr_bitfield_default },
+	 { "ME_BUSY", 17, 17, &umr_bitfield_default },
+	 { "QUERY_BUSY", 18, 18, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 20, 20, &umr_bitfield_default },
+	 { "SURFACE_SYNC_BUSY", 21, 21, &umr_bitfield_default },
+	 { "DMA_BUSY", 22, 22, &umr_bitfield_default },
+	 { "RCIU_BUSY", 23, 23, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 24, 24, &umr_bitfield_default },
+	 { "CPC_CPG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "CE_BUSY", 26, 26, &umr_bitfield_default },
+	 { "TCIU_BUSY", 27, 27, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 28, 28, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 29, 29, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CP_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_HEADER_DUMP[] = {
+	 { "ME_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_HEADER_DUMP[] = {
+	 { "PFP_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+	 { "FREE_COUNT_GDS", 8, 13, &umr_bitfield_default },
+	 { "FREE_COUNT_PFP", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_HEADER_DUMP[] = {
+	 { "CE_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MC_PACK_DELAY_CNT[] = {
+	 { "PACK_DELAY_CNT", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MC_TAG_CNTL[] = {
+	 { "TAG_RAM_INDEX", 0, 5, &umr_bitfield_default },
+	 { "TAG_RAM_SEL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MC_TAG_DATA[] = {
+	 { "TAG_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CSF_STAT[] = {
+	 { "BUFFER_SLOTS_ALLOCATED", 0, 3, &umr_bitfield_default },
+	 { "BUFFER_REQUEST_COUNT", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CSF_CNTL[] = {
+	 { "FETCH_BUFFER_DEPTH", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_CNTL[] = {
+	 { "CE_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "PFP_INVALIDATE_ICACHE", 6, 6, &umr_bitfield_default },
+	 { "ME_INVALIDATE_ICACHE", 8, 8, &umr_bitfield_default },
+	 { "CE_HALT", 24, 24, &umr_bitfield_default },
+	 { "CE_STEP", 25, 25, &umr_bitfield_default },
+	 { "PFP_HALT", 26, 26, &umr_bitfield_default },
+	 { "PFP_STEP", 27, 27, &umr_bitfield_default },
+	 { "ME_HALT", 28, 28, &umr_bitfield_default },
+	 { "ME_STEP", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CNTX_STAT[] = {
+	 { "ACTIVE_HP3D_CONTEXTS", 0, 7, &umr_bitfield_default },
+	 { "CURRENT_HP3D_CONTEXT", 8, 10, &umr_bitfield_default },
+	 { "ACTIVE_GFX_CONTEXTS", 20, 27, &umr_bitfield_default },
+	 { "CURRENT_GFX_CONTEXT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_PREEMPTION[] = {
+	 { "ME_CNTXSW_PREEMPTION", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ROQ_THRESHOLDS[] = {
+	 { "IB1_START", 0, 7, &umr_bitfield_default },
+	 { "IB2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEQ_STQ_THRESHOLD[] = {
+	 { "STQ_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB2_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB1_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB0_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_WPTR_DELAY[] = {
+	 { "PRE_WRITE_TIMER", 0, 27, &umr_bitfield_default },
+	 { "PRE_WRITE_LIMIT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_WPTR_POLL_CNTL[] = {
+	 { "POLL_FREQUENCY", 0, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ROQ1_THRESHOLDS[] = {
+	 { "RB1_START", 0, 7, &umr_bitfield_default },
+	 { "RB2_START", 8, 15, &umr_bitfield_default },
+	 { "R0_IB1_START", 16, 23, &umr_bitfield_default },
+	 { "R1_IB1_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ROQ2_THRESHOLDS[] = {
+	 { "R2_IB1_START", 0, 7, &umr_bitfield_default },
+	 { "R0_IB2_START", 8, 15, &umr_bitfield_default },
+	 { "R1_IB2_START", 16, 23, &umr_bitfield_default },
+	 { "R2_IB2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STQ_THRESHOLDS[] = {
+	 { "STQ0_START", 0, 7, &umr_bitfield_default },
+	 { "STQ1_START", 8, 15, &umr_bitfield_default },
+	 { "STQ2_START", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_QUEUE_THRESHOLDS[] = {
+	 { "ROQ_IB1_START", 0, 5, &umr_bitfield_default },
+	 { "ROQ_IB2_START", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEQ_THRESHOLDS[] = {
+	 { "MEQ1_START", 0, 7, &umr_bitfield_default },
+	 { "MEQ2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ROQ_AVAIL[] = {
+	 { "ROQ_CNT_RING", 0, 10, &umr_bitfield_default },
+	 { "ROQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STQ_AVAIL[] = {
+	 { "STQ_CNT", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ROQ2_AVAIL[] = {
+	 { "ROQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEQ_AVAIL[] = {
+	 { "MEQ_CNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CMD_INDEX[] = {
+	 { "CMD_INDEX", 0, 10, &umr_bitfield_default },
+	 { "CMD_ME_SEL", 12, 13, &umr_bitfield_default },
+	 { "CMD_QUEUE_SEL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CMD_DATA[] = {
+	 { "CMD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ROQ_RB_STAT[] = {
+	 { "ROQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ROQ_IB1_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ROQ_IB2_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STQ_STAT[] = {
+	 { "STQ_RPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STQ_WR_STAT[] = {
+	 { "STQ_WPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEQ_STAT[] = {
+	 { "MEQ_RPTR", 0, 9, &umr_bitfield_default },
+	 { "MEQ_WPTR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CEQ1_AVAIL[] = {
+	 { "CEQ_CNT_RING", 0, 10, &umr_bitfield_default },
+	 { "CEQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CEQ2_AVAIL[] = {
+	 { "CEQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_ROQ_RB_STAT[] = {
+	 { "CEQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_ROQ_IB1_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_ROQ_IB2_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_STAT_DEBUG[] = {
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ASSERTED", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ASSERTED", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ASSERTED", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_VTX_VECT_EJECT_REG[] = {
+	 { "PRIM_COUNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_DATA_FIFO_DEPTH[] = {
+	 { "DMA_DATA_FIFO_DEPTH", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_REQ_FIFO_DEPTH[] = {
+	 { "DMA_REQ_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DRAW_INIT_FIFO_DEPTH[] = {
+	 { "DRAW_INIT_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_LAST_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+	 { "DST_STATE_ID", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_CACHE_INVALIDATION[] = {
+	 { "CACHE_INVALIDATION", 0, 1, &umr_bitfield_default },
+	 { "VS_NO_EXTRA_BUFFER", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INVLD_EN", 6, 7, &umr_bitfield_default },
+	 { "USE_GS_DONE", 9, 9, &umr_bitfield_default },
+	 { "DIS_RANGE_FULL_INVLD", 11, 11, &umr_bitfield_default },
+	 { "GS_LATE_ALLOC_EN", 12, 12, &umr_bitfield_default },
+	 { "STREAMOUT_FULL_FLUSH", 13, 13, &umr_bitfield_default },
+	 { "ES_LIMIT", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_RESET_DEBUG[] = {
+	 { "GS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "TESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "WD_DISABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_DELAY[] = {
+	 { "SKIP_DELAY", 0, 7, &umr_bitfield_default },
+	 { "SE0_WD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "SE1_WD_DELAY", 11, 13, &umr_bitfield_default },
+	 { "SE2_WD_DELAY", 14, 16, &umr_bitfield_default },
+	 { "SE3_WD_DELAY", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_FIFO_DEPTHS[] = {
+	 { "VS_DEALLOC_TBL_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "RESERVED_0", 7, 7, &umr_bitfield_default },
+	 { "CLIPP_FIFO_DEPTH", 8, 21, &umr_bitfield_default },
+	 { "RESERVED_1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_VERTEX_REUSE[] = {
+	 { "VERT_REUSE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_MC_LAT_CNTL[] = {
+	 { "MC_TIME_STAMP_RES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_CNTL_STATUS[] = {
+	 { "IA_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IA_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "IA_DMA_REQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "IA_GRP_BUSY", 3, 3, &umr_bitfield_default },
+	 { "IA_ADC_BUSY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DEBUG_CNTL[] = {
+	 { "VGT_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "VGT_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_DEBUG_CNTL[] = {
+	 { "IA_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "IA_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_CNTL_STATUS[] = {
+	 { "VGT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VGT_OUT_INDX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "VGT_OUT_BUSY", 2, 2, &umr_bitfield_default },
+	 { "VGT_PT_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VGT_TE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGT_VR_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGT_PI_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGT_GS_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGT_HS_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VGT_TE11_BUSY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_DEBUG_CNTL[] = {
+	 { "WD_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "WD_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_CNTL_STATUS[] = {
+	 { "WD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "WD_SPL_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WD_SPL_DI_BUSY", 2, 2, &umr_bitfield_default },
+	 { "WD_ADC_BUSY", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield CC_GC_PRIM_CONFIG[] = {
+	 { "INACTIVE_IA", 16, 17, &umr_bitfield_default },
+	 { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield GC_USER_PRIM_CONFIG[] = {
+	 { "INACTIVE_IA", 16, 17, &umr_bitfield_default },
+	 { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_VMID_OVERRIDE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VMID", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_SYS_CONFIG[] = {
+	 { "DUAL_CORE_EN", 0, 0, &umr_bitfield_default },
+	 { "MAX_LS_HS_THDGRP", 1, 6, &umr_bitfield_default },
+	 { "ADC_EVENT_FILTER_DISABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_VS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield GFX_PIPE_CONTROL[] = {
+	 { "HYSTERESIS_CNT", 0, 12, &umr_bitfield_default },
+	 { "RESERVED", 13, 15, &umr_bitfield_default },
+	 { "CONTEXT_SUSPEND_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield CC_GC_SHADER_ARRAY_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GC_USER_SHADER_ARRAY_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_CONTROL[] = {
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "IA_SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_LS_HS_CONFIG[] = {
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_DEBUG_CNTL[] = {
+	 { "SU_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_CNTL_STATUS[] = {
+	 { "CL_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_ENHANCE[] = {
+	 { "CLIP_VTX_REORDER_ENA", 0, 0, &umr_bitfield_default },
+	 { "NUM_CLIP_SEQ", 1, 2, &umr_bitfield_default },
+	 { "CLIPPED_PRIM_SEQ_STALL", 3, 3, &umr_bitfield_default },
+	 { "VE_NAN_PROC_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "XTRA_DEBUG_REG_SEL", 5, 5, &umr_bitfield_default },
+	 { "ECO_SPARE3", 28, 28, &umr_bitfield_default },
+	 { "ECO_SPARE2", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_RESET_DEBUG[] = {
+	 { "CL_TRIV_DISC_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_CNTL_STATUS[] = {
+	 { "SU_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_FIFO_DEPTH_CNTL[] = {
+	 { "DEPTH", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_P3D_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_HP3D_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_FORCE_EOV_MAX_CNTS[] = {
+	 { "FORCE_EOV_MAX_CLK_CNT", 0, 15, &umr_bitfield_default },
+	 { "FORCE_EOV_MAX_REZ_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_FIFO_SIZE[] = {
+	 { "SC_FRONTEND_PRIM_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_BACKEND_PRIM_FIFO_SIZE", 6, 14, &umr_bitfield_default },
+	 { "SC_HIZ_TILE_FIFO_SIZE", 15, 20, &umr_bitfield_default },
+	 { "SC_EARLYZ_TILE_FIFO_SIZE", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_IF_FIFO_SIZE[] = {
+	 { "SC_DB_TILE_IF_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_DB_QUAD_IF_FIFO_SIZE", 6, 11, &umr_bitfield_default },
+	 { "SC_SPI_IF_FIFO_SIZE", 12, 17, &umr_bitfield_default },
+	 { "SC_BCI_IF_FIFO_SIZE", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_DEBUG_CNTL[] = {
+	 { "SC_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_ENHANCE[] = {
+	 { "ENABLE_PA_SC_OUT_OF_ORDER", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_SC_DB_TILE_FIX", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_AA_MASK_FULL_FIX", 2, 2, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOCATIONS", 3, 3, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_SCISSOR_FIX", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_PW_BUBBLE_COLLAPSE", 6, 7, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PACKER", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_DUALGRAD_PERF_OPTIMIZATION", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_PRIM", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_SUPERTILE", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_TILE", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_PA_SC_GUIDANCE", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_MULTICYCLE_BUBBLE_FREEZE", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_POLY_MODE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS", 23, 23, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO", 25, 25, &umr_bitfield_default },
+	 { "OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT", 26, 26, &umr_bitfield_default },
+	 { "OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_EOP_LINE_STIPPLE_RESET", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_VPZ_EOP_LINE_STIPPLE_RESET", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_CONFIG[] = {
+	 { "UNUSED", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_EN", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_SCA_BYPASS", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_IB_DEP_CHECK", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_SOFT_CLAUSE", 11, 11, &umr_bitfield_default },
+	 { "EARLY_TA_DONE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "DUA_FLAT_LOCK_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "DUA_LDS_BYPASS_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DUA_FLAT_LDS_PINGPONG_DISABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SQC_CONFIG[] = {
+	 { "INST_CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DATA_CACHE_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MISS_FIFO_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "HIT_FIFO_DEPTH", 6, 6, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_MISS", 7, 7, &umr_bitfield_default },
+	 { "FORCE_IN_ORDER", 8, 8, &umr_bitfield_default },
+	 { "IDENTITY_HASH_BANK", 9, 9, &umr_bitfield_default },
+	 { "IDENTITY_HASH_SET", 10, 10, &umr_bitfield_default },
+	 { "PER_VMID_INV_DISABLE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_RANDOM_WAVE_PRI[] = {
+	 { "RET", 0, 6, &umr_bitfield_default },
+	 { "RUI", 7, 9, &umr_bitfield_default },
+	 { "RNG", 10, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_REG_CREDITS[] = {
+	 { "SRBM_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "CMD_CREDITS", 8, 11, &umr_bitfield_default },
+	 { "REG_BUSY", 28, 28, &umr_bitfield_default },
+	 { "SRBM_OVERFLOW", 29, 29, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 30, 30, &umr_bitfield_default },
+	 { "CMD_OVERFLOW", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_FIFO_SIZES[] = {
+	 { "INTERRUPT_FIFO_SIZE", 0, 3, &umr_bitfield_default },
+	 { "TTRACE_FIFO_SIZE", 8, 11, &umr_bitfield_default },
+	 { "EXPORT_BUF_SIZE", 16, 17, &umr_bitfield_default },
+	 { "VMEM_DATA_FIFO_SIZE", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CC_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield USER_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_DEBUG_STS_GLOBAL[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "INTERRUPT_MSG_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH0", 4, 15, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH1", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield SH_MEM_BASES[] = {
+	 { "PRIVATE_BASE", 0, 15, &umr_bitfield_default },
+	 { "SHARED_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SH_MEM_APE1_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SH_MEM_APE1_LIMIT[] = {
+	 { "LIMIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SH_MEM_CONFIG[] = {
+	 { "PTR32", 0, 0, &umr_bitfield_default },
+	 { "PRIVATE_ATC", 1, 1, &umr_bitfield_default },
+	 { "ALIGNMENT_MODE", 2, 3, &umr_bitfield_default },
+	 { "DEFAULT_MTYPE", 4, 6, &umr_bitfield_default },
+	 { "APE1_MTYPE", 7, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield SQC_POLICY[] = {
+	 { "DATA_L1_POLICY_0", 0, 0, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_1", 1, 1, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_2", 2, 2, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_3", 3, 3, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_4", 4, 4, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_5", 5, 5, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_6", 6, 6, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_7", 7, 7, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_0", 8, 9, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_1", 10, 11, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_2", 12, 13, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_3", 14, 15, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_4", 16, 17, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_5", 18, 19, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_6", 20, 21, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_7", 22, 23, &umr_bitfield_default },
+	 { "INST_L2_POLICY", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield SQC_VOLATILE[] = {
+	 { "DATA_L1", 0, 3, &umr_bitfield_default },
+	 { "DATA_L2", 4, 7, &umr_bitfield_default },
+	 { "INST_L2", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_DEBUG_STS_GLOBAL2[] = {
+	 { "FIFO_LEVEL_GFX0", 0, 7, &umr_bitfield_default },
+	 { "FIFO_LEVEL_GFX1", 8, 15, &umr_bitfield_default },
+	 { "FIFO_LEVEL_IMMED", 16, 23, &umr_bitfield_default },
+	 { "FIFO_LEVEL_HOST", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_DEBUG_STS_GLOBAL3[] = {
+	 { "FIFO_LEVEL_HOST_CMD", 0, 3, &umr_bitfield_default },
+	 { "FIFO_LEVEL_HOST_REG", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_INTERRUPT_AUTO_MASK[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_INTERRUPT_MSG_CTRL[] = {
+	 { "STALL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_REG_TIMESTAMP[] = {
+	 { "TIMESTAMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_CMD_TIMESTAMP[] = {
+	 { "TIMESTAMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IND_INDEX[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "THREAD_ID", 6, 11, &umr_bitfield_default },
+	 { "AUTO_INCR", 12, 12, &umr_bitfield_default },
+	 { "FORCE_READ", 13, 13, &umr_bitfield_default },
+	 { "READ_TIMEOUT", 14, 14, &umr_bitfield_default },
+	 { "UNINDEXED", 15, 15, &umr_bitfield_default },
+	 { "INDEX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_CMD[] = {
+	 { "CMD", 0, 2, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "CHECK_VMID", 7, 7, &umr_bitfield_default },
+	 { "TRAP_ID", 8, 10, &umr_bitfield_default },
+	 { "WAVE_ID", 16, 19, &umr_bitfield_default },
+	 { "SIMD_ID", 20, 21, &umr_bitfield_default },
+	 { "QUEUE_ID", 24, 26, &umr_bitfield_default },
+	 { "VM_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_TIME_HI[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_TIME_LO[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_VOP3_0_SDST_ENC[] = {
+	 { "VDST", 0, 7, &umr_bitfield_default },
+	 { "SDST", 8, 14, &umr_bitfield_default },
+	 { "OP", 17, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_MTBUF_1[] = {
+	 { "VADDR", 0, 7, &umr_bitfield_default },
+	 { "VDATA", 8, 15, &umr_bitfield_default },
+	 { "SRSRC", 16, 20, &umr_bitfield_default },
+	 { "SLC", 22, 22, &umr_bitfield_default },
+	 { "TFE", 23, 23, &umr_bitfield_default },
+	 { "SOFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_VOP3_0[] = {
+	 { "VDST", 0, 7, &umr_bitfield_default },
+	 { "ABS", 8, 10, &umr_bitfield_default },
+	 { "CLAMP", 11, 11, &umr_bitfield_default },
+	 { "OP", 17, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_EXP_1[] = {
+	 { "VSRC0", 0, 7, &umr_bitfield_default },
+	 { "VSRC1", 8, 15, &umr_bitfield_default },
+	 { "VSRC2", 16, 23, &umr_bitfield_default },
+	 { "VSRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_SOP2[] = {
+	 { "SSRC0", 0, 7, &umr_bitfield_default },
+	 { "SSRC1", 8, 15, &umr_bitfield_default },
+	 { "SDST", 16, 22, &umr_bitfield_default },
+	 { "OP", 23, 29, &umr_bitfield_default },
+	 { "ENCODING", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_SIZE[] = {
+	 { "SIZE", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_MASK[] = {
+	 { "CU_SEL", 0, 4, &umr_bitfield_default },
+	 { "SH_SEL", 5, 5, &umr_bitfield_default },
+	 { "REG_STALL_EN", 7, 7, &umr_bitfield_default },
+	 { "SIMD_EN", 8, 11, &umr_bitfield_default },
+	 { "VM_ID_MASK", 12, 13, &umr_bitfield_default },
+	 { "SPI_STALL_EN", 14, 14, &umr_bitfield_default },
+	 { "SQ_STALL_EN", 15, 15, &umr_bitfield_default },
+	 { "RANDOM_SEED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_TOKEN_MASK[] = {
+	 { "TOKEN_MASK", 0, 15, &umr_bitfield_default },
+	 { "REG_MASK", 16, 23, &umr_bitfield_default },
+	 { "REG_DROP_ON_STALL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_PERF_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_BASE2[] = {
+	 { "ADDR_HI", 0, 3, &umr_bitfield_default },
+	 { "ATC", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_TOKEN_MASK2[] = {
+	 { "INST_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WPTR[] = {
+	 { "WPTR", 0, 29, &umr_bitfield_default },
+	 { "READ_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_STATUS[] = {
+	 { "FINISH_PENDING", 0, 9, &umr_bitfield_default },
+	 { "FINISH_DONE", 16, 25, &umr_bitfield_default },
+	 { "NEW_BUF", 29, 29, &umr_bitfield_default },
+	 { "BUSY", 30, 30, &umr_bitfield_default },
+	 { "FULL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_MODE[] = {
+	 { "MASK_PS", 0, 2, &umr_bitfield_default },
+	 { "MASK_VS", 3, 5, &umr_bitfield_default },
+	 { "MASK_GS", 6, 8, &umr_bitfield_default },
+	 { "MASK_ES", 9, 11, &umr_bitfield_default },
+	 { "MASK_HS", 12, 14, &umr_bitfield_default },
+	 { "MASK_LS", 15, 17, &umr_bitfield_default },
+	 { "MASK_CS", 18, 20, &umr_bitfield_default },
+	 { "MODE", 21, 22, &umr_bitfield_default },
+	 { "CAPTURE_MODE", 23, 24, &umr_bitfield_default },
+	 { "AUTOFLUSH_EN", 25, 25, &umr_bitfield_default },
+	 { "PRIV", 26, 26, &umr_bitfield_default },
+	 { "ISSUE_MASK", 27, 28, &umr_bitfield_default },
+	 { "TEST_MODE", 29, 29, &umr_bitfield_default },
+	 { "INTERRUPT_EN", 30, 30, &umr_bitfield_default },
+	 { "WRAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_CTRL[] = {
+	 { "RESET_BUFFER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_CNTR[] = {
+	 { "CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_HIWATER[] = {
+	 { "HIWATER", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_LB_CTR_CTRL[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "LOAD", 1, 1, &umr_bitfield_default },
+	 { "CLEAR", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_LB_DATA_ALU_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_LB_DATA_TEX_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_LB_DATA_ALU_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_LB_DATA_TEX_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQC_SECDED_CNT[] = {
+	 { "INST_SEC", 0, 7, &umr_bitfield_default },
+	 { "INST_DED", 8, 15, &umr_bitfield_default },
+	 { "DATA_SEC", 16, 23, &umr_bitfield_default },
+	 { "DATA_DED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_SEC_CNT[] = {
+	 { "LDS_SEC", 0, 5, &umr_bitfield_default },
+	 { "SGPR_SEC", 8, 12, &umr_bitfield_default },
+	 { "VGPR_SEC", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_DED_CNT[] = {
+	 { "LDS_DED", 0, 5, &umr_bitfield_default },
+	 { "SGPR_DED", 8, 12, &umr_bitfield_default },
+	 { "VGPR_DED", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_DED_INFO[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "SOURCE", 6, 8, &umr_bitfield_default },
+	 { "VM_ID", 9, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "WAVE_ID", 10, 13, &umr_bitfield_default },
+	 { "SIMD_ID", 14, 15, &umr_bitfield_default },
+	 { "DATA_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID", 5, 8, &umr_bitfield_default },
+	 { "SIMD_ID", 9, 10, &umr_bitfield_default },
+	 { "PC_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "PIPE_ID", 5, 6, &umr_bitfield_default },
+	 { "ME_ID", 7, 8, &umr_bitfield_default },
+	 { "REG_ADDR", 9, 15, &umr_bitfield_default },
+	 { "DATA_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_PERF_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "CNTR_BANK", 10, 11, &umr_bitfield_default },
+	 { "CNTR0", 12, 24, &umr_bitfield_default },
+	 { "CNTR1_LO", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_WAVE_START[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "WAVE_ID", 10, 13, &umr_bitfield_default },
+	 { "SIMD_ID", 14, 15, &umr_bitfield_default },
+	 { "DISPATCHER", 16, 20, &umr_bitfield_default },
+	 { "VS_NO_ALLOC_OR_GROUPED", 21, 21, &umr_bitfield_default },
+	 { "COUNT", 22, 28, &umr_bitfield_default },
+	 { "TG_ID", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_EVENT[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "STAGE", 6, 8, &umr_bitfield_default },
+	 { "EVENT_TYPE", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_INST[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID", 5, 8, &umr_bitfield_default },
+	 { "SIMD_ID", 9, 10, &umr_bitfield_default },
+	 { "SIZE", 11, 11, &umr_bitfield_default },
+	 { "INST_TYPE", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_CMN[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[] = {
+	 { "DATA_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[] = {
+	 { "TIME_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[] = {
+	 { "PC_HI", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_WORD_PERF_2_OF_2[] = {
+	 { "CNTR1_HI", 0, 5, &umr_bitfield_default },
+	 { "CNTR2", 6, 18, &umr_bitfield_default },
+	 { "CNTR3", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_BUF_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_BUF_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 15, &umr_bitfield_default },
+	 { "STRIDE", 16, 29, &umr_bitfield_default },
+	 { "CACHE_SWIZZLE", 30, 30, &umr_bitfield_default },
+	 { "SWIZZLE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_BUF_RSRC_WORD2[] = {
+	 { "NUM_RECORDS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_BUF_RSRC_WORD3[] = {
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "NUM_FORMAT", 12, 14, &umr_bitfield_default },
+	 { "DATA_FORMAT", 15, 18, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 19, 20, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 21, 22, &umr_bitfield_default },
+	 { "ADD_TID_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "ATC", 24, 24, &umr_bitfield_default },
+	 { "HASH_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "HEAP", 26, 26, &umr_bitfield_default },
+	 { "MTYPE", 27, 29, &umr_bitfield_default },
+	 { "TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 7, &umr_bitfield_default },
+	 { "MIN_LOD", 8, 19, &umr_bitfield_default },
+	 { "DATA_FORMAT", 20, 25, &umr_bitfield_default },
+	 { "NUM_FORMAT", 26, 29, &umr_bitfield_default },
+	 { "MTYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_RSRC_WORD2[] = {
+	 { "WIDTH", 0, 13, &umr_bitfield_default },
+	 { "HEIGHT", 14, 27, &umr_bitfield_default },
+	 { "PERF_MOD", 28, 30, &umr_bitfield_default },
+	 { "INTERLACED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_RSRC_WORD3[] = {
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "BASE_LEVEL", 12, 15, &umr_bitfield_default },
+	 { "LAST_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "TILING_INDEX", 20, 24, &umr_bitfield_default },
+	 { "POW2_PAD", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 26, 26, &umr_bitfield_default },
+	 { "ATC", 27, 27, &umr_bitfield_default },
+	 { "TYPE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_RSRC_WORD4[] = {
+	 { "DEPTH", 0, 12, &umr_bitfield_default },
+	 { "PITCH", 13, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_RSRC_WORD5[] = {
+	 { "BASE_ARRAY", 0, 12, &umr_bitfield_default },
+	 { "LAST_ARRAY", 13, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_RSRC_WORD6[] = {
+	 { "MIN_LOD_WARN", 0, 11, &umr_bitfield_default },
+	 { "COUNTER_BANK_ID", 12, 19, &umr_bitfield_default },
+	 { "LOD_HDW_CNT_EN", 20, 20, &umr_bitfield_default },
+	 { "UNUNSED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_RSRC_WORD7[] = {
+	 { "UNUNSED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_SAMP_WORD0[] = {
+	 { "CLAMP_X", 0, 2, &umr_bitfield_default },
+	 { "CLAMP_Y", 3, 5, &umr_bitfield_default },
+	 { "CLAMP_Z", 6, 8, &umr_bitfield_default },
+	 { "MAX_ANISO_RATIO", 9, 11, &umr_bitfield_default },
+	 { "DEPTH_COMPARE_FUNC", 12, 14, &umr_bitfield_default },
+	 { "FORCE_UNNORMALIZED", 15, 15, &umr_bitfield_default },
+	 { "ANISO_THRESHOLD", 16, 18, &umr_bitfield_default },
+	 { "MC_COORD_TRUNC", 19, 19, &umr_bitfield_default },
+	 { "FORCE_DEGAMMA", 20, 20, &umr_bitfield_default },
+	 { "ANISO_BIAS", 21, 26, &umr_bitfield_default },
+	 { "TRUNC_COORD", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_CUBE_WRAP", 28, 28, &umr_bitfield_default },
+	 { "FILTER_MODE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_SAMP_WORD1[] = {
+	 { "MIN_LOD", 0, 11, &umr_bitfield_default },
+	 { "MAX_LOD", 12, 23, &umr_bitfield_default },
+	 { "PERF_MIP", 24, 27, &umr_bitfield_default },
+	 { "PERF_Z", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_SAMP_WORD2[] = {
+	 { "LOD_BIAS", 0, 13, &umr_bitfield_default },
+	 { "LOD_BIAS_SEC", 14, 19, &umr_bitfield_default },
+	 { "XY_MAG_FILTER", 20, 21, &umr_bitfield_default },
+	 { "XY_MIN_FILTER", 22, 23, &umr_bitfield_default },
+	 { "Z_FILTER", 24, 25, &umr_bitfield_default },
+	 { "MIP_FILTER", 26, 27, &umr_bitfield_default },
+	 { "MIP_POINT_PRECLAMP", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_LSB_CEIL", 29, 29, &umr_bitfield_default },
+	 { "FILTER_PREC_FIX", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_IMG_SAMP_WORD3[] = {
+	 { "BORDER_COLOR_PTR", 0, 11, &umr_bitfield_default },
+	 { "BORDER_COLOR_TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_FLAT_SCRATCH_WORD0[] = {
+	 { "SIZE", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_FLAT_SCRATCH_WORD1[] = {
+	 { "OFFSET", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_DEBUG_BUSY[] = {
+	 { "POS_FREE_OR_VALIDS", 0, 0, &umr_bitfield_default },
+	 { "POS_REQUESTER_BUSY", 1, 1, &umr_bitfield_default },
+	 { "PA_SX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "POS_SCBD_BUSY", 3, 3, &umr_bitfield_default },
+	 { "POS_BANK3VAL3_BUSY", 4, 4, &umr_bitfield_default },
+	 { "POS_BANK3VAL2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "POS_BANK3VAL1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "POS_BANK3VAL0_BUSY", 7, 7, &umr_bitfield_default },
+	 { "POS_BANK2VAL3_BUSY", 8, 8, &umr_bitfield_default },
+	 { "POS_BANK2VAL2_BUSY", 9, 9, &umr_bitfield_default },
+	 { "POS_BANK2VAL1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "POS_BANK2VAL0_BUSY", 11, 11, &umr_bitfield_default },
+	 { "POS_BANK1VAL3_BUSY", 12, 12, &umr_bitfield_default },
+	 { "POS_BANK1VAL2_BUSY", 13, 13, &umr_bitfield_default },
+	 { "POS_BANK1VAL1_BUSY", 14, 14, &umr_bitfield_default },
+	 { "POS_BANK1VAL0_BUSY", 15, 15, &umr_bitfield_default },
+	 { "POS_BANK0VAL3_BUSY", 16, 16, &umr_bitfield_default },
+	 { "POS_BANK0VAL2_BUSY", 17, 17, &umr_bitfield_default },
+	 { "POS_BANK0VAL1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "POS_BANK0VAL0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "POS_INMUX_VALID", 20, 20, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ3", 21, 21, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ2", 22, 22, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ1", 23, 23, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ3", 24, 24, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ2", 25, 25, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ1", 26, 26, &umr_bitfield_default },
+	 { "PCCMD_VALID", 27, 27, &umr_bitfield_default },
+	 { "VDATA1_VALID", 28, 28, &umr_bitfield_default },
+	 { "VDATA0_VALID", 29, 29, &umr_bitfield_default },
+	 { "CMD_BUSYORVAL", 30, 30, &umr_bitfield_default },
+	 { "ADDR_BUSYORVAL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_DEBUG_BUSY_2[] = {
+	 { "COL_SCBD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_REQ3_FREECNT_NE0", 1, 1, &umr_bitfield_default },
+	 { "COL_REQ3_IDLE", 2, 2, &umr_bitfield_default },
+	 { "COL_REQ3_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_REQ2_FREECNT_NE0", 4, 4, &umr_bitfield_default },
+	 { "COL_REQ2_IDLE", 5, 5, &umr_bitfield_default },
+	 { "COL_REQ2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_REQ1_FREECNT_NE0", 7, 7, &umr_bitfield_default },
+	 { "COL_REQ1_IDLE", 8, 8, &umr_bitfield_default },
+	 { "COL_REQ1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_REQ0_FREECNT_NE0", 10, 10, &umr_bitfield_default },
+	 { "COL_REQ0_IDLE", 11, 11, &umr_bitfield_default },
+	 { "COL_REQ0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_DBIF3_SENDFREE_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_DBIF3_FIFO_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_DBIF3_READ_VALID", 15, 15, &umr_bitfield_default },
+	 { "COL_DBIF2_SENDFREE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_DBIF2_FIFO_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_DBIF2_READ_VALID", 18, 18, &umr_bitfield_default },
+	 { "COL_DBIF1_SENDFREE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_DBIF1_FIFO_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_DBIF1_READ_VALID", 21, 21, &umr_bitfield_default },
+	 { "COL_DBIF0_SENDFREE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_DBIF0_FIFO_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_DBIF0_READ_VALID", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_DEBUG_BUSY_3[] = {
+	 { "COL_BUFF3_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_DEBUG_BUSY_4[] = {
+	 { "COL_BUFF1_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "RESERVED", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_DEBUG_1[] = {
+	 { "SX_DB_QUAD_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "DEBUG_DATA", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CONFIG_CNTL[] = {
+	 { "GPR_WRITE_PRIORITY", 0, 20, &umr_bitfield_default },
+	 { "EXP_PRIORITY_ORDER", 21, 23, &umr_bitfield_default },
+	 { "ENABLE_SQG_TOP_EVENTS", 24, 24, &umr_bitfield_default },
+	 { "ENABLE_SQG_BOP_EVENTS", 25, 25, &umr_bitfield_default },
+	 { "RSRC_MGMT_RESET", 26, 26, &umr_bitfield_default },
+	 { "TTRACE_STALL_ALL", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_DEBUG_CNTL[] = {
+	 { "DEBUG_GRBM_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_THREAD_TYPE_SEL", 1, 3, &umr_bitfield_default },
+	 { "DEBUG_GROUP_SEL", 4, 9, &umr_bitfield_default },
+	 { "DEBUG_SIMD_SEL", 10, 15, &umr_bitfield_default },
+	 { "DEBUG_SH_SEL", 16, 16, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_0", 17, 17, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_1", 18, 18, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_2", 19, 19, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_3", 20, 20, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_4", 21, 21, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_5", 22, 22, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_6", 23, 23, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_7", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_PIPE_SEL", 25, 27, &umr_bitfield_default },
+	 { "DEBUG_REG_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CONFIG_CNTL_1[] = {
+	 { "VTX_DONE_DELAY", 0, 3, &umr_bitfield_default },
+	 { "INTERP_ONE_PRIM_PER_ROW", 4, 4, &umr_bitfield_default },
+	 { "PC_LIMIT_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "PC_LIMIT_STRICT", 7, 7, &umr_bitfield_default },
+	 { "CRC_SIMD_ID_WADDR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_MODE", 9, 9, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_CNT", 10, 13, &umr_bitfield_default },
+	 { "PC_LIMIT_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_DEBUG_BUSY[] = {
+	 { "LS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "HS_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ES_BUSY", 2, 2, &umr_bitfield_default },
+	 { "GS_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "PS0_BUSY", 5, 5, &umr_bitfield_default },
+	 { "PS1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CSG_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CS0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "CS1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "CS2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "CS3_BUSY", 11, 11, &umr_bitfield_default },
+	 { "CS4_BUSY", 12, 12, &umr_bitfield_default },
+	 { "CS5_BUSY", 13, 13, &umr_bitfield_default },
+	 { "CS6_BUSY", 14, 14, &umr_bitfield_default },
+	 { "CS7_BUSY", 15, 15, &umr_bitfield_default },
+	 { "LDS_WR_CTL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "LDS_WR_CTL1_BUSY", 17, 17, &umr_bitfield_default },
+	 { "RSRC_ALLOC0_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RSRC_ALLOC1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "PC_DEALLOC_BUSY", 20, 20, &umr_bitfield_default },
+	 { "EVENT_CLCTR_BUSY", 21, 21, &umr_bitfield_default },
+	 { "GRBM_BUSY", 22, 22, &umr_bitfield_default },
+	 { "SPIS_BUSY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_CNTL[] = {
+	 { "SAMPLE_PERIOD", 0, 3, &umr_bitfield_default },
+	 { "EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_0[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_1[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_2[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_3[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_4[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_5[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_6[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_7[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_8[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_LIMIT_9[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_0[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_1[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_2[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_3[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_4[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_5[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_6[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_7[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_8[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_9[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_10[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_11[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_12[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_13[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_14[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_15[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_16[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_17[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_18[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_19[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_STATUS_20[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WF_LIFETIME_DEBUG[] = {
+	 { "START_VALUE", 0, 30, &umr_bitfield_default },
+	 { "OVERRIDE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SLAVE_DEBUG_BUSY[] = {
+	 { "LS_VTX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "HS_VTX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ES_VTX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "GS_VTX_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VS_VTX_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGPR_WC00_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGPR_WC01_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGPR_WC10_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGPR_WC11_BUSY", 8, 8, &umr_bitfield_default },
+	 { "SGPR_WC00_BUSY", 9, 9, &umr_bitfield_default },
+	 { "SGPR_WC01_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SGPR_WC02_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SGPR_WC03_BUSY", 12, 12, &umr_bitfield_default },
+	 { "SGPR_WC10_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SGPR_WC11_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SGPR_WC12_BUSY", 15, 15, &umr_bitfield_default },
+	 { "SGPR_WC13_BUSY", 16, 16, &umr_bitfield_default },
+	 { "WAVEBUFFER0_BUSY", 17, 17, &umr_bitfield_default },
+	 { "WAVEBUFFER1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "WAVE_WC0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "WAVE_WC1_BUSY", 20, 20, &umr_bitfield_default },
+	 { "EVENT_CNTL_BUSY", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_LB_CTR_CTRL[] = {
+	 { "LOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_LB_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_LB_DATA_REG[] = {
+	 { "CNT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PG_ENABLE_STATIC_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDS_CREDITS[] = {
+	 { "DS_DATA_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "DS_CMD_CREDITS", 8, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SX_EXPORT_BUFFER_SIZES[] = {
+	 { "COLOR_BUFFER_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_BUFFER_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SX_SCOREBOARD_BUFFER_SIZES[] = {
+	 { "COLOR_SCOREBOARD_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_SCOREBOARD_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_STATUS[] = {
+	 { "ACTIVE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_COUNT_0[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_COUNT_1[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_COUNT_2[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_COUNT_3[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_COUNT_4[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_COUNT_5[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_COUNT_6[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CSQ_WF_ACTIVE_COUNT_7[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield BCI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P0_TRAP_SCREEN_PSBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P0_TRAP_SCREEN_PSBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P0_TRAP_SCREEN_PSMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P0_TRAP_SCREEN_PSMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P0_TRAP_SCREEN_GPR_MIN[] = {
+	 { "VGPR_MIN", 0, 5, &umr_bitfield_default },
+	 { "SGPR_MIN", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P1_TRAP_SCREEN_PSBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P1_TRAP_SCREEN_PSBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P1_TRAP_SCREEN_PSMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P1_TRAP_SCREEN_PSMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_P1_TRAP_SCREEN_GPR_MIN[] = {
+	 { "VGPR_MIN", 0, 5, &umr_bitfield_default },
+	 { "SGPR_MIN", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_CNTL[] = {
+	 { "SYNC_PHASE_SH", 0, 1, &umr_bitfield_default },
+	 { "SYNC_PHASE_VC_SMX", 4, 5, &umr_bitfield_default },
+	 { "PAD_STALL_EN", 8, 8, &umr_bitfield_default },
+	 { "EXTEND_LDS_STALL", 9, 10, &umr_bitfield_default },
+	 { "LDS_STALL_PHASE_ADJUST", 11, 12, &umr_bitfield_default },
+	 { "PRECISION_COMPATIBILITY", 15, 15, &umr_bitfield_default },
+	 { "GATHER4_FLOAT_MODE", 16, 16, &umr_bitfield_default },
+	 { "LD_FLOAT_MODE", 18, 18, &umr_bitfield_default },
+	 { "GATHER4_DX9_MODE", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_POWER_THROTTLE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_STATUS[] = {
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_CNTL[] = {
+	 { "TC_DATA_CREDIT", 13, 15, &umr_bitfield_default },
+	 { "ALIGNER_CREDIT", 16, 20, &umr_bitfield_default },
+	 { "TD_FIFO_CREDIT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_CNTL_AUX[] = {
+	 { "SCOAL_DSWIZZLE_N", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 3, &umr_bitfield_default },
+	 { "ANISO_WEIGHT_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_RESERVED_010C[] = {
+	 { "Unused", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_STATUS[] = {
+	 { "FG_PFIFO_EMPTYB", 12, 12, &umr_bitfield_default },
+	 { "FG_LFIFO_EMPTYB", 13, 13, &umr_bitfield_default },
+	 { "FG_SFIFO_EMPTYB", 14, 14, &umr_bitfield_default },
+	 { "FL_PFIFO_EMPTYB", 16, 16, &umr_bitfield_default },
+	 { "FL_LFIFO_EMPTYB", 17, 17, &umr_bitfield_default },
+	 { "FL_SFIFO_EMPTYB", 18, 18, &umr_bitfield_default },
+	 { "FA_PFIFO_EMPTYB", 20, 20, &umr_bitfield_default },
+	 { "FA_LFIFO_EMPTYB", 21, 21, &umr_bitfield_default },
+	 { "FA_SFIFO_EMPTYB", 22, 22, &umr_bitfield_default },
+	 { "IN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "FG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "LA_BUSY", 26, 26, &umr_bitfield_default },
+	 { "FL_BUSY", 27, 27, &umr_bitfield_default },
+	 { "TA_BUSY", 28, 28, &umr_bitfield_default },
+	 { "FA_BUSY", 29, 29, &umr_bitfield_default },
+	 { "AL_BUSY", 30, 30, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SH_HIDDEN_PRIVATE_BASE_VMID[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SH_STATIC_MEM_CONFIG[] = {
+	 { "SWIZZLE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 1, 2, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 3, 4, &umr_bitfield_default },
+	 { "PRIVATE_MTYPE", 5, 7, &umr_bitfield_default },
+	 { "READ_ONLY_CNTL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_CONFIG[] = {
+	 { "SH0_GPR_PHASE_SEL", 1, 2, &umr_bitfield_default },
+	 { "SH1_GPR_PHASE_SEL", 3, 4, &umr_bitfield_default },
+	 { "SH2_GPR_PHASE_SEL", 5, 6, &umr_bitfield_default },
+	 { "SH3_GPR_PHASE_SEL", 7, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_CNTL_STATUS[] = {
+	 { "GDS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GRBM_WBUF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ORD_APP_BUSY", 2, 2, &umr_bitfield_default },
+	 { "DS_BANK_CONFLICT", 3, 3, &umr_bitfield_default },
+	 { "DS_ADDR_CONFLICT", 4, 4, &umr_bitfield_default },
+	 { "DS_WR_CLAMP", 5, 5, &umr_bitfield_default },
+	 { "DS_RD_CLAMP", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ENHANCE[] = {
+	 { "MISC", 0, 15, &umr_bitfield_default },
+	 { "AUTO_INC_INDEX", 16, 16, &umr_bitfield_default },
+	 { "CGPG_RESTORE", 17, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PROTECTION_FAULT[] = {
+	 { "WRITE_DIS", 0, 0, &umr_bitfield_default },
+	 { "FAULT_DETECTED", 1, 1, &umr_bitfield_default },
+	 { "GRBM", 2, 2, &umr_bitfield_default },
+	 { "SH_ID", 3, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "SIMD_ID", 10, 11, &umr_bitfield_default },
+	 { "WAVE_ID", 12, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VM_PROTECTION_FAULT[] = {
+	 { "WRITE_DIS", 0, 0, &umr_bitfield_default },
+	 { "FAULT_DETECTED", 1, 1, &umr_bitfield_default },
+	 { "GWS", 2, 2, &umr_bitfield_default },
+	 { "OA", 3, 3, &umr_bitfield_default },
+	 { "GRBM", 4, 4, &umr_bitfield_default },
+	 { "VMID", 8, 11, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_SECDED_CNT[] = {
+	 { "DED", 0, 15, &umr_bitfield_default },
+	 { "SEC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GRBM_SECDED_CNT[] = {
+	 { "DED", 0, 15, &umr_bitfield_default },
+	 { "SEC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_DED[] = {
+	 { "ME0_GFXHP3D_PIX_DED", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_DED", 1, 1, &umr_bitfield_default },
+	 { "ME0_CS_DED", 2, 2, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "ME1_PIPE0_DED", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_DED", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_DED", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_DED", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_DED", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_DED", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_DED", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_DED", 11, 11, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_DEBUG_CNTL[] = {
+	 { "GDS_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+	 { "UNUSED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEBUG[] = {
+	 { "DEBUG_STENCIL_COMPRESS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_DEPTH_COMPRESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "FETCH_FULL_Z_TILE", 2, 2, &umr_bitfield_default },
+	 { "FETCH_FULL_STENCIL_TILE", 3, 3, &umr_bitfield_default },
+	 { "FORCE_Z_MODE", 4, 5, &umr_bitfield_default },
+	 { "DEBUG_FORCE_DEPTH_READ", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_FORCE_STENCIL_READ", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIZ_ENABLE", 8, 9, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE0", 10, 11, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE1", 12, 13, &umr_bitfield_default },
+	 { "DEBUG_FAST_Z_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_FAST_STENCIL_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_NOOP_CULL_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_SUMM_SQUADS", 17, 17, &umr_bitfield_default },
+	 { "DEPTH_CACHE_FORCE_MISS", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_FORCE_FULL_Z_RANGE", 19, 20, &umr_bitfield_default },
+	 { "NEVER_FREE_Z_ONLY", 21, 21, &umr_bitfield_default },
+	 { "ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_VPORT_ZPLANE_OPTIMIZATION", 23, 23, &umr_bitfield_default },
+	 { "DECOMPRESS_AFTER_N_ZPLANES", 24, 27, &umr_bitfield_default },
+	 { "ONE_FREE_IN_FLIGHT", 28, 28, &umr_bitfield_default },
+	 { "FORCE_MISS_IF_NOT_INFLIGHT", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_DEPTH_SURFACE_SYNC", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_HTILE_SURFACE_SYNC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEBUG2[] = {
+	 { "ALLOW_COMPZ_BYTE_MASKING", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_TC_ZRANGE_L0_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_TC_MASK_L0_CACHE", 2, 2, &umr_bitfield_default },
+	 { "DTR_ROUND_ROBIN_ARB", 3, 3, &umr_bitfield_default },
+	 { "DTR_PREZ_STALLS_FOR_ETF_ROOM", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_PREZL_CB_STALL", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL_REZ", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_PREZL_CB_STALL_REZ", 8, 8, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 9, 13, &umr_bitfield_default },
+	 { "DISABLE_TILE_COVERED_FOR_PS_ITER", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_SUBTILE_GROUPING", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_HTILE_PAIRED_PIPES", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_NULL_EOT_FORWARDING", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_DTT_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_QUAD_COHERENCY_STALL", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_PREZ_OF_REZ_SUMM", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_PREZL_VIEWPORT_STALL", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_SINGLE_STENCIL_QUAD_SUMM", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_WRITE_STALL_ON_RDWR_CONFLICT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEBUG3[] = {
+	 { "FORCE_DB_IS_GOOD", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_TL_SSO_NULL_SUPPRESSION", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_HIZ_ON_VPORT_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_COMP_Z", 5, 5, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_SRC_Z", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_TCP_CAM_BYPASS", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_ZCMP_DIRTY_SUPPRESSION", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_REDUNDANT_PLANE_FLUSHES_OPT", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_INCOHERENT_EQAA_READS", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_OP_Z_DATA_FORWARDING", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_BYPASS", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_WRITE_COMBINE", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_DIRECT_FEEDBACK", 15, 15, &umr_bitfield_default },
+	 { "ALLOW_RF2P_RW_COLLISION", 16, 16, &umr_bitfield_default },
+	 { "SLOW_PREZ_TO_A2M_OMASK_RATE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_OP_S_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_TC_UPDATE_WRITE_COMBINE", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_HZ_TC_WRITE_COMBINE", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_TC_MA_ROUND_ROBIN_ARB", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_RAM_READ_SUPPRESION_ON_FWD", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_EQAA_A2M_PERF_OPT", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_DI_DT_STALL", 25, 25, &umr_bitfield_default },
+	 { "ENABLE_DB_PROCESS_RESET", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_OVERRASTERIZATION_FIX", 27, 27, &umr_bitfield_default },
+	 { "DONT_INSERT_CONTEXT_SUSPEND", 28, 28, &umr_bitfield_default },
+	 { "DONT_DELETE_CONTEXT_SUSPEND", 29, 29, &umr_bitfield_default },
+	 { "DB_EXTRA_DEBUG3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEBUG4[] = {
+	 { "DISABLE_QC_Z_MASK_SUMMATION", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_QC_STENCIL_MASK_SUMMATION", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_RESUMM_TO_SINGLE_STENCIL", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL", 3, 3, &umr_bitfield_default },
+	 { "DB_EXTRA_DEBUG4", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_CREDIT_LIMIT[] = {
+	 { "DB_SC_TILE_CREDITS", 0, 4, &umr_bitfield_default },
+	 { "DB_SC_QUAD_CREDITS", 5, 9, &umr_bitfield_default },
+	 { "DB_CB_LQUAD_CREDITS", 10, 12, &umr_bitfield_default },
+	 { "DB_CB_TILE_CREDITS", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_WATERMARKS[] = {
+	 { "DEPTH_FREE", 0, 4, &umr_bitfield_default },
+	 { "DEPTH_FLUSH", 5, 10, &umr_bitfield_default },
+	 { "FORCE_SUMMARIZE", 11, 14, &umr_bitfield_default },
+	 { "DEPTH_PENDING_FREE", 15, 19, &umr_bitfield_default },
+	 { "DEPTH_CACHELINE_FREE", 20, 26, &umr_bitfield_default },
+	 { "EARLY_Z_PANIC_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "LATE_Z_PANIC_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "RE_Z_PANIC_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "AUTO_FLUSH_HTILE", 30, 30, &umr_bitfield_default },
+	 { "AUTO_FLUSH_QUAD", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_SUBTILE_CONTROL[] = {
+	 { "MSAA1_X", 0, 1, &umr_bitfield_default },
+	 { "MSAA1_Y", 2, 3, &umr_bitfield_default },
+	 { "MSAA2_X", 4, 5, &umr_bitfield_default },
+	 { "MSAA2_Y", 6, 7, &umr_bitfield_default },
+	 { "MSAA4_X", 8, 9, &umr_bitfield_default },
+	 { "MSAA4_Y", 10, 11, &umr_bitfield_default },
+	 { "MSAA8_X", 12, 13, &umr_bitfield_default },
+	 { "MSAA8_Y", 14, 15, &umr_bitfield_default },
+	 { "MSAA16_X", 16, 17, &umr_bitfield_default },
+	 { "MSAA16_Y", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_FREE_CACHELINES[] = {
+	 { "FREE_DTILE_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "FREE_PLANE_DEPTH", 7, 13, &umr_bitfield_default },
+	 { "FREE_Z_DEPTH", 14, 20, &umr_bitfield_default },
+	 { "FREE_HTILE_DEPTH", 21, 24, &umr_bitfield_default },
+	 { "QUAD_READ_REQS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_FIFO_DEPTH1[] = {
+	 { "MI_RDREQ_FIFO_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "MI_WRREQ_FIFO_DEPTH", 5, 9, &umr_bitfield_default },
+	 { "MCC_DEPTH", 10, 15, &umr_bitfield_default },
+	 { "QC_DEPTH", 16, 20, &umr_bitfield_default },
+	 { "LTILE_PROBE_FIFO_DEPTH", 21, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_FIFO_DEPTH2[] = {
+	 { "EQUAD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "ETILE_OP_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "LQUAD_FIFO_DEPTH", 15, 24, &umr_bitfield_default },
+	 { "LTILE_OP_FIFO_DEPTH", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_RING_CONTROL[] = {
+	 { "COUNTER_CONTROL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_0[] = {
+	 { "BUSY_DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_1[] = {
+	 { "BUSY_DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_2[] = {
+	 { "BUSY_DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_3[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_4[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_5[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_6[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_7[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_8[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_9[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_A[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_B[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_C[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_D[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_E[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_READ_DEBUG_F[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CC_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield CC_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_BACKEND_MAP[] = {
+	 { "BACKEND_MAP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_GPU_ID[] = {
+	 { "GPU_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield CC_RB_DAISY_CHAIN[] = {
+	 { "RB_0", 0, 3, &umr_bitfield_default },
+	 { "RB_1", 4, 7, &umr_bitfield_default },
+	 { "RB_2", 8, 11, &umr_bitfield_default },
+	 { "RB_3", 12, 15, &umr_bitfield_default },
+	 { "RB_4", 16, 19, &umr_bitfield_default },
+	 { "RB_5", 20, 23, &umr_bitfield_default },
+	 { "RB_6", 24, 27, &umr_bitfield_default },
+	 { "RB_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE0[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE1[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE2[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE3[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE4[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE5[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE6[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE7[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE8[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE9[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE10[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE11[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE12[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE13[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE14[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE15[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE16[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE17[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE18[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE19[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE20[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE21[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE22[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE23[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE24[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE25[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE26[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE27[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE28[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE29[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE30[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_TILE_MODE31[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE0[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE1[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE2[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE3[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE4[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE5[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE6[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE7[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE8[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE9[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE10[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE11[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE12[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE13[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE14[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_MACROTILE_MODE15[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_HW_CONTROL_3[] = {
+	 { "DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_HW_CONTROL[] = {
+	 { "CM_CACHE_EVICT_POINT", 0, 3, &umr_bitfield_default },
+	 { "FC_CACHE_EVICT_POINT", 6, 9, &umr_bitfield_default },
+	 { "CC_CACHE_EVICT_POINT", 12, 15, &umr_bitfield_default },
+	 { "ALLOW_MRT_WITH_DUAL_SOURCE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_INTNORM_LE11BPC_CLAMPING", 18, 18, &umr_bitfield_default },
+	 { "FORCE_NEEDS_DST", 19, 19, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_TOGGLE", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_RESULT_EQ_DEST", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_FULL_WRITE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DONT_RD_DST", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_BYPASS", 25, 25, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DISCARD_PIXEL", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED", 27, 27, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT", 28, 28, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_CC_IB_SERIALIZER_STATE_OPT", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_HW_CONTROL_1[] = {
+	 { "CM_CACHE_NUM_TAGS", 0, 4, &umr_bitfield_default },
+	 { "FC_CACHE_NUM_TAGS", 5, 10, &umr_bitfield_default },
+	 { "CC_CACHE_NUM_TAGS", 11, 16, &umr_bitfield_default },
+	 { "CM_TILE_FIFO_DEPTH", 17, 25, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_HW_CONTROL_2[] = {
+	 { "CC_EVEN_ODD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "FC_RDLAT_TILE_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "FC_RDLAT_QUAD_FIFO_DEPTH", 15, 22, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_DEBUG_BUS_13[] = {
+	 { "TILE_INTFC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MU_BUSY", 1, 1, &umr_bitfield_default },
+	 { "TQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "AC_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CRW_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CACHE_CTRL_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MC_WR_PENDING", 6, 6, &umr_bitfield_default },
+	 { "FC_WR_PENDING", 7, 7, &umr_bitfield_default },
+	 { "FC_RD_PENDING", 8, 8, &umr_bitfield_default },
+	 { "EVICT_PENDING", 9, 9, &umr_bitfield_default },
+	 { "LAST_RD_ARB_WINNER", 10, 10, &umr_bitfield_default },
+	 { "MU_STATE", 11, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_DEBUG_BUS_14[] = {
+	 { "TILE_RETIREMENT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "FOP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LAT_BUSY", 2, 2, &umr_bitfield_default },
+	 { "CACHE_CTL_BUSY", 3, 3, &umr_bitfield_default },
+	 { "ADDR_BUSY", 4, 4, &umr_bitfield_default },
+	 { "MERGE_BUSY", 5, 5, &umr_bitfield_default },
+	 { "QUAD_BUSY", 6, 6, &umr_bitfield_default },
+	 { "TILE_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CLEAR_BUSY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_DEBUG_BUS_15[] = {
+	 { "SURF_SYNC_STATE", 0, 1, &umr_bitfield_default },
+	 { "SURF_SYNC_START", 2, 2, &umr_bitfield_default },
+	 { "SF_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "RB_BUSY", 5, 5, &umr_bitfield_default },
+	 { "DS_BUSY", 6, 6, &umr_bitfield_default },
+	 { "TB_BUSY", 7, 7, &umr_bitfield_default },
+	 { "IB_BUSY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_DEBUG_BUS_16[] = {
+	 { "MC_RDREQ_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "LAST_RD_GRANT_VEC", 6, 9, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDITS", 10, 15, &umr_bitfield_default },
+	 { "LAST_WR_GRANT_VEC", 16, 19, &umr_bitfield_default },
+	 { "CC_WRREQ_FIFO_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "FC_WRREQ_FIFO_EMPTY", 21, 21, &umr_bitfield_default },
+	 { "CM_WRREQ_FIFO_EMPTY", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_DEBUG_BUS_17[] = {
+	 { "CM_BUSY", 0, 0, &umr_bitfield_default },
+	 { "FC_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CC_BUSY", 2, 2, &umr_bitfield_default },
+	 { "BB_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MA_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CORE_SCLK_VLD", 5, 5, &umr_bitfield_default },
+	 { "REG_SCLK1_VLD", 6, 6, &umr_bitfield_default },
+	 { "REG_SCLK0_VLD", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_DEBUG_BUS_18[] = {
+	 { "NOT_USED", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield GC_USER_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield GC_USER_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_INVALIDATE[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_STATUS[] = {
+	 { "TCP_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_CNTL[] = {
+	 { "FORCE_HIT", 0, 0, &umr_bitfield_default },
+	 { "FORCE_MISS", 1, 1, &umr_bitfield_default },
+	 { "L1_SIZE", 2, 3, &umr_bitfield_default },
+	 { "FLAT_BUF_HASH_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FLAT_BUF_CACHE_SWIZZLE", 5, 5, &umr_bitfield_default },
+	 { "FORCE_EOW_TOTAL_CNT", 15, 20, &umr_bitfield_default },
+	 { "FORCE_EOW_TAGRAM_CNT", 22, 27, &umr_bitfield_default },
+	 { "DISABLE_Z_MAP", 28, 28, &umr_bitfield_default },
+	 { "INV_ALL_VMIDS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_CHAN_STEER_LO[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "CHAN3", 12, 15, &umr_bitfield_default },
+	 { "CHAN4", 16, 19, &umr_bitfield_default },
+	 { "CHAN5", 20, 23, &umr_bitfield_default },
+	 { "CHAN6", 24, 27, &umr_bitfield_default },
+	 { "CHAN7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_CHAN_STEER_HI[] = {
+	 { "CHAN8", 0, 3, &umr_bitfield_default },
+	 { "CHAN9", 4, 7, &umr_bitfield_default },
+	 { "CHANA", 8, 11, &umr_bitfield_default },
+	 { "CHANB", 12, 15, &umr_bitfield_default },
+	 { "CHANC", 16, 19, &umr_bitfield_default },
+	 { "CHAND", 20, 23, &umr_bitfield_default },
+	 { "CHANE", 24, 27, &umr_bitfield_default },
+	 { "CHANF", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_ADDR_CONFIG[] = {
+	 { "NUM_TCC_BANKS", 0, 3, &umr_bitfield_default },
+	 { "NUM_BANKS", 4, 5, &umr_bitfield_default },
+	 { "COLHI_WIDTH", 6, 8, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_CREDIT[] = {
+	 { "LFIFO_CREDIT", 0, 9, &umr_bitfield_default },
+	 { "REQ_FIFO_CREDIT", 16, 22, &umr_bitfield_default },
+	 { "TD_CREDIT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_BUFFER_ADDR_HASH_CNTL[] = {
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "BANK_BITS", 8, 10, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 16, 18, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_EDC_COUNTER[] = {
+	 { "SEC_COUNT", 0, 3, &umr_bitfield_default },
+	 { "DED_COUNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L1_LOAD_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L1_LOAD_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L1_STORE_POLICY[] = {
+	 { "POLICY_0", 0, 0, &umr_bitfield_default },
+	 { "POLICY_1", 1, 1, &umr_bitfield_default },
+	 { "POLICY_2", 2, 2, &umr_bitfield_default },
+	 { "POLICY_3", 3, 3, &umr_bitfield_default },
+	 { "POLICY_4", 4, 4, &umr_bitfield_default },
+	 { "POLICY_5", 5, 5, &umr_bitfield_default },
+	 { "POLICY_6", 6, 6, &umr_bitfield_default },
+	 { "POLICY_7", 7, 7, &umr_bitfield_default },
+	 { "POLICY_8", 8, 8, &umr_bitfield_default },
+	 { "POLICY_9", 9, 9, &umr_bitfield_default },
+	 { "POLICY_10", 10, 10, &umr_bitfield_default },
+	 { "POLICY_11", 11, 11, &umr_bitfield_default },
+	 { "POLICY_12", 12, 12, &umr_bitfield_default },
+	 { "POLICY_13", 13, 13, &umr_bitfield_default },
+	 { "POLICY_14", 14, 14, &umr_bitfield_default },
+	 { "POLICY_15", 15, 15, &umr_bitfield_default },
+	 { "POLICY_16", 16, 16, &umr_bitfield_default },
+	 { "POLICY_17", 17, 17, &umr_bitfield_default },
+	 { "POLICY_18", 18, 18, &umr_bitfield_default },
+	 { "POLICY_19", 19, 19, &umr_bitfield_default },
+	 { "POLICY_20", 20, 20, &umr_bitfield_default },
+	 { "POLICY_21", 21, 21, &umr_bitfield_default },
+	 { "POLICY_22", 22, 22, &umr_bitfield_default },
+	 { "POLICY_23", 23, 23, &umr_bitfield_default },
+	 { "POLICY_24", 24, 24, &umr_bitfield_default },
+	 { "POLICY_25", 25, 25, &umr_bitfield_default },
+	 { "POLICY_26", 26, 26, &umr_bitfield_default },
+	 { "POLICY_27", 27, 27, &umr_bitfield_default },
+	 { "POLICY_28", 28, 28, &umr_bitfield_default },
+	 { "POLICY_29", 29, 29, &umr_bitfield_default },
+	 { "POLICY_30", 30, 30, &umr_bitfield_default },
+	 { "POLICY_31", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L2_LOAD_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L2_LOAD_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L2_STORE_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L2_STORE_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L2_ATOMIC_POLICY[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L1_VOLATILE[] = {
+	 { "VOL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield TC_CFG_L2_VOLATILE[] = {
+	 { "VOL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield TCI_STATUS[] = {
+	 { "TCI_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield TCI_CNTL_1[] = {
+	 { "WBINVL1_NUM_CYCLES", 0, 15, &umr_bitfield_default },
+	 { "REQ_FIFO_DEPTH", 16, 23, &umr_bitfield_default },
+	 { "WDATA_RAM_DEPTH", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCI_CNTL_2[] = {
+	 { "L1_INVAL_ON_WBINVL2", 0, 0, &umr_bitfield_default },
+	 { "TCA_MAX_CREDIT", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_CTRL[] = {
+	 { "CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "RATE", 2, 3, &umr_bitfield_default },
+	 { "WRITEBACK_MARGIN", 4, 7, &umr_bitfield_default },
+	 { "SRC_FIFO_SIZE", 12, 15, &umr_bitfield_default },
+	 { "LATENCY_FIFO_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WB_OR_INV_ALL_VMIDS", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_EDC_COUNTER[] = {
+	 { "SEC_COUNT", 0, 3, &umr_bitfield_default },
+	 { "DED_COUNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_REDUNDANCY[] = {
+	 { "MC_SEL0", 0, 0, &umr_bitfield_default },
+	 { "MC_SEL1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_CTRL[] = {
+	 { "HOLE_TIMEOUT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_CTRL[] = {
+	 { "RATE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC3_PS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC1_PS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_PS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "WAVE_CNT_EN", 7, 7, &umr_bitfield_default },
+	 { "EXTRA_LDS_SIZE", 8, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_PS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC3_VS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_LATE_ALLOC_VS[] = {
+	 { "LIMIT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC1_VS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "SO_BASE0_EN", 8, 8, &umr_bitfield_default },
+	 { "SO_BASE1_EN", 9, 9, &umr_bitfield_default },
+	 { "SO_BASE2_EN", 10, 10, &umr_bitfield_default },
+	 { "SO_BASE3_EN", 11, 11, &umr_bitfield_default },
+	 { "SO_EN", 12, 12, &umr_bitfield_default },
+	 { "EXCP_EN", 13, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_VS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_ES_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_LS_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC3_GS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC1_GS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_GS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "EXCP_EN", 7, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_GS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_ES_GS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC3_ES[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC1_ES[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_ES[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_ES_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_LS_ES[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC3_HS[] = {
+	 { "WAVE_LIMIT", 0, 5, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC1_HS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CACHE_CTL", 24, 26, &umr_bitfield_default },
+	 { "CDBG_USER", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_HS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 8, 8, &umr_bitfield_default },
+	 { "EXCP_EN", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_HS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_LS_HS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TBA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_TMA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC3_LS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC1_LS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CACHE_CTL", 26, 28, &umr_bitfield_default },
+	 { "CDBG_USER", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_PGM_RSRC2_LS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_USER_DATA_LS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_DISPATCH_INITIATOR[] = {
+	 { "COMPUTE_SHADER_EN", 0, 0, &umr_bitfield_default },
+	 { "PARTIAL_TG_EN", 1, 1, &umr_bitfield_default },
+	 { "FORCE_START_AT_000", 2, 2, &umr_bitfield_default },
+	 { "ORDERED_APPEND_ENBL", 3, 3, &umr_bitfield_default },
+	 { "ORDERED_APPEND_MODE", 4, 4, &umr_bitfield_default },
+	 { "USE_THREAD_DIMENSIONS", 5, 5, &umr_bitfield_default },
+	 { "ORDER_MODE", 6, 6, &umr_bitfield_default },
+	 { "DISPATCH_CACHE_CNTL", 7, 9, &umr_bitfield_default },
+	 { "SCALAR_L1_INV_VOL", 10, 10, &umr_bitfield_default },
+	 { "VECTOR_L1_INV_VOL", 11, 11, &umr_bitfield_default },
+	 { "DATA_ATC", 12, 12, &umr_bitfield_default },
+	 { "RESTORE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_DIM_X[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_DIM_Y[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_DIM_Z[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_START_X[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_START_Y[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_START_Z[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_NUM_THREAD_X[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_NUM_THREAD_Y[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_NUM_THREAD_Z[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_PIPELINESTAT_ENABLE[] = {
+	 { "PIPELINESTAT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_PERFCOUNT_ENABLE[] = {
+	 { "PERFCOUNT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_PGM_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_PGM_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+	 { "INST_ATC", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_TBA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_TBA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_TMA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_TMA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_PGM_RSRC1[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "BULKY", 24, 24, &umr_bitfield_default },
+	 { "CDBG_USER", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_PGM_RSRC2[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "TGID_X_EN", 7, 7, &umr_bitfield_default },
+	 { "TGID_Y_EN", 8, 8, &umr_bitfield_default },
+	 { "TGID_Z_EN", 9, 9, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 10, 10, &umr_bitfield_default },
+	 { "TIDIG_COMP_CNT", 11, 12, &umr_bitfield_default },
+	 { "EXCP_EN_MSB", 13, 14, &umr_bitfield_default },
+	 { "LDS_SIZE", 15, 23, &umr_bitfield_default },
+	 { "EXCP_EN", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_VMID[] = {
+	 { "DATA", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_RESOURCE_LIMITS[] = {
+	 { "WAVES_PER_SH", 0, 9, &umr_bitfield_default },
+	 { "TG_PER_CU", 12, 15, &umr_bitfield_default },
+	 { "LOCK_THRESHOLD", 16, 21, &umr_bitfield_default },
+	 { "SIMD_DEST_CNTL", 22, 22, &umr_bitfield_default },
+	 { "FORCE_SIMD_DIST", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_COUNT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_STATIC_THREAD_MGMT_SE0[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_STATIC_THREAD_MGMT_SE1[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_TMPRING_SIZE[] = {
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_STATIC_THREAD_MGMT_SE2[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_STATIC_THREAD_MGMT_SE3[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_RESTART_X[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_RESTART_Y[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_RESTART_Z[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_THREAD_TRACE_ENABLE[] = {
+	 { "THREAD_TRACE_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_MISC_RESERVED[] = {
+	 { "SEND_SEID", 0, 1, &umr_bitfield_default },
+	 { "RESERVED2", 2, 2, &umr_bitfield_default },
+	 { "RESERVED3", 3, 3, &umr_bitfield_default },
+	 { "RESERVED4", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COMPUTE_USER_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_CNTL[] = {
+	 { "POLICY", 8, 9, &umr_bitfield_default },
+	 { "VOL", 10, 10, &umr_bitfield_default },
+	 { "ATC", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_STAT[] = {
+	 { "BURST_COUNT", 0, 15, &umr_bitfield_default },
+	 { "TAGS_PENDING", 16, 23, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_ADDR_LO[] = {
+	 { "ADDR_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DFY_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB0_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB0_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "BUF_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "BUF_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_RPTR_WR[] = {
+	 { "RB_RPTR_WR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB0_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB0_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB0_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "OBSOLETE", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "OBSOLETE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_CNTL[] = {
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_STATUS[] = {
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DEVICE_ID[] = {
+	 { "DEVICE_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME0_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RING_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME0_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RING0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME0_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RING1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME0_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RING2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ENDIAN_SWAP[] = {
+	 { "ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_VMID[] = {
+	 { "RB0_VMID", 0, 3, &umr_bitfield_default },
+	 { "RB1_VMID", 8, 11, &umr_bitfield_default },
+	 { "RB2_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_RAM_RADDR[] = {
+	 { "ME_RAM_RADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_RAM_WADDR[] = {
+	 { "ME_RAM_WADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_RAM_DATA[] = {
+	 { "ME_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC_ME1_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC_ME1_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC_ME2_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC_ME2_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB1_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB1_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB1_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB1_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB1_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB2_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB2_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB2_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB2_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB2_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_CNTL_RING0[] = {
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_CNTL_RING1[] = {
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_CNTL_RING2[] = {
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_STATUS_RING0[] = {
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_STATUS_RING1[] = {
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_INT_STATUS_RING2[] = {
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PWR_CNTL[] = {
+	 { "GFX_CLK_HALT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEM_SLP_CNTL[] = {
+	 { "CP_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "CP_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 7, &umr_bitfield_default },
+	 { "CP_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CP_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ECC_FIRSTOCCURRENCE[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ECC_FIRSTOCCURRENCE_RING0[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ECC_FIRSTOCCURRENCE_RING1[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ECC_FIRSTOCCURRENCE_RING2[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield GB_EDC_MODE[] = {
+	 { "FORCE_SEC_ON_DED", 16, 16, &umr_bitfield_default },
+	 { "DED_MODE", 20, 21, &umr_bitfield_default },
+	 { "PROP_FED", 29, 29, &umr_bitfield_default },
+	 { "BYPASS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_FETCHER_SOURCE[] = {
+	 { "ME_SRC", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PQ_WPTR_POLL_CNTL[] = {
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+	 { "POLL_ACTIVE", 30, 30, &umr_bitfield_default },
+	 { "EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PQ_WPTR_POLL_CNTL1[] = {
+	 { "QUEUE_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE0_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE1_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE2_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE3_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE0_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE1_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE2_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE3_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE0_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE1_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE2_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE3_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE0_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE1_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE2_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE3_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_INT_STAT_DEBUG[] = {
+	 { "DEQUEUE_REQUEST_INT_ASSERTED", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_INT_STAT_DEBUG[] = {
+	 { "DEQUEUE_REQUEST_INT_ASSERTED", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CC_GC_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME1_PIPE3_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME2_PIPE3_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC1_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC2_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC1_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MEC2_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CONTEXT_CNTL[] = {
+	 { "ME0PIPE0_MAX_WD_CNTX", 0, 2, &umr_bitfield_default },
+	 { "ME0PIPE0_MAX_PIPE_CNTX", 4, 6, &umr_bitfield_default },
+	 { "ME0PIPE1_MAX_WD_CNTX", 16, 18, &umr_bitfield_default },
+	 { "ME0PIPE1_MAX_PIPE_CNTX", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MAX_CONTEXT[] = {
+	 { "MAX_CONTEXT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IQ_WAIT_TIME1[] = {
+	 { "IB_OFFLOAD", 0, 7, &umr_bitfield_default },
+	 { "ATOMIC_OFFLOAD", 8, 15, &umr_bitfield_default },
+	 { "WRM_OFFLOAD", 16, 23, &umr_bitfield_default },
+	 { "GWS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IQ_WAIT_TIME2[] = {
+	 { "QUE_SLEEP", 0, 7, &umr_bitfield_default },
+	 { "SCH_WAVE", 8, 15, &umr_bitfield_default },
+	 { "SEM_REARM", 16, 23, &umr_bitfield_default },
+	 { "DEQ_RETRY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB0_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB1_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VMID_RESET[] = {
+	 { "RESET_REQUEST", 0, 15, &umr_bitfield_default },
+	 { "RESET_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VMID_PREEMPT[] = {
+	 { "PREEMPT_REQUEST", 0, 15, &umr_bitfield_default },
+	 { "PREEMPT_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PQ_STATUS[] = {
+	 { "DOORBELL_UPDATED", 0, 0, &umr_bitfield_default },
+	 { "DOORBELL_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_CNTL[] = {
+	 { "RLC_ENABLE_F32", 0, 0, &umr_bitfield_default },
+	 { "FORCE_RETRY", 1, 1, &umr_bitfield_default },
+	 { "READ_CACHE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RLC_STEP_F32", 3, 3, &umr_bitfield_default },
+	 { "SOFT_RESET_DEBUG_MODE", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_MC_CNTL[] = {
+	 { "WRREQ_SWAP", 0, 1, &umr_bitfield_default },
+	 { "WRREQ_TRAN", 2, 2, &umr_bitfield_default },
+	 { "WRREQ_PRIV", 3, 3, &umr_bitfield_default },
+	 { "WRNFO_STALL", 4, 4, &umr_bitfield_default },
+	 { "WRNFO_URG", 5, 8, &umr_bitfield_default },
+	 { "WRREQ_DW_IMASK", 9, 12, &umr_bitfield_default },
+	 { "RESERVED_B", 13, 19, &umr_bitfield_default },
+	 { "RDNFO_URG", 20, 23, &umr_bitfield_default },
+	 { "RDREQ_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RDREQ_TRAN", 26, 26, &umr_bitfield_default },
+	 { "RDREQ_PRIV", 27, 27, &umr_bitfield_default },
+	 { "RDNFO_STALL", 28, 28, &umr_bitfield_default },
+	 { "RESERVED", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_STAT[] = {
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "RLC_GPM_BUSY", 1, 1, &umr_bitfield_default },
+	 { "RLC_SPM_BUSY", 2, 2, &umr_bitfield_default },
+	 { "RESERVED", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SOFT_RESET_GPU[] = {
+	 { "SOFT_RESET_GPU", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_MEM_SLP_CNTL[] = {
+	 { "RLC_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "RLC_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 7, &umr_bitfield_default },
+	 { "RLC_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "RLC_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_LB_CNTR_MAX[] = {
+	 { "LB_CNTR_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_LB_CNTL[] = {
+	 { "LOAD_BALANCE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LB_CNT_CP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LB_CNT_SPIM_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "LB_CNT_REG_INC", 3, 3, &umr_bitfield_default },
+	 { "CU_MASK_USED_OFF_HYST", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_LB_CNTR_INIT[] = {
+	 { "LB_CNTR_INIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_LOAD_BALANCE_CNTR[] = {
+	 { "RLC_LOAD_BALANCE_CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SAVE_AND_RESTORE_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_DRIVER_CPDMA_STATUS[] = {
+	 { "DRIVER_REQUEST", 0, 0, &umr_bitfield_default },
+	 { "RESERVED1", 1, 3, &umr_bitfield_default },
+	 { "DRIVER_ACK", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_JUMP_TABLE_RESTORE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PG_DELAY_2[] = {
+	 { "SERDES_TIMEOUT_VALUE", 0, 7, &umr_bitfield_default },
+	 { "SERDES_CMD_DELAY", 8, 15, &umr_bitfield_default },
+	 { "PERCU_TIMEOUT_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPU_CLOCK_COUNT_LSB[] = {
+	 { "GPU_CLOCKS_LSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPU_CLOCK_COUNT_MSB[] = {
+	 { "GPU_CLOCKS_MSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_CAPTURE_GPU_CLOCK_COUNT[] = {
+	 { "CAPTURE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_UCODE_CNTL[] = {
+	 { "RLC_UCODE_FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_STAT[] = {
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_STATUS", 1, 1, &umr_bitfield_default },
+	 { "GFX_CLOCK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "GFX_LS_STATUS", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPU_CLOCK_32_RES_SEL[] = {
+	 { "RES_SEL", 0, 5, &umr_bitfield_default },
+	 { "RESERVED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPU_CLOCK_32[] = {
+	 { "GPU_CLOCK_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PG_CNTL[] = {
+	 { "GFX_POWER_GATING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_GATING_SRC", 1, 1, &umr_bitfield_default },
+	 { "DYN_PER_CU_PG_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "STATIC_PER_CU_PG_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 15, &umr_bitfield_default },
+	 { "CHUB_HANDSHAKE_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PU_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PD_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "RESERVED1", 19, 23, &umr_bitfield_default },
+	 { "PG_ERROR_STATUS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_THREAD_PRIORITY[] = {
+	 { "THREAD0_PRIORITY", 0, 7, &umr_bitfield_default },
+	 { "THREAD1_PRIORITY", 8, 15, &umr_bitfield_default },
+	 { "THREAD2_PRIORITY", 16, 23, &umr_bitfield_default },
+	 { "THREAD3_PRIORITY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_THREAD_ENABLE[] = {
+	 { "THREAD0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "THREAD1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "THREAD2_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "THREAD3_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_VMID_THREAD0[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_VMID_THREAD1[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_CGTT_MGCG_OVERRIDE[] = {
+	 { "OVERRIDE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_CGCG_CGLS_CTRL[] = {
+	 { "CGCG_EN", 0, 0, &umr_bitfield_default },
+	 { "CGLS_EN", 1, 1, &umr_bitfield_default },
+	 { "CGLS_REP_COMPANSAT_DELAY", 2, 7, &umr_bitfield_default },
+	 { "CGCG_GFX_IDLE_THRESHOLD", 8, 26, &umr_bitfield_default },
+	 { "CGCG_CONTROLLER", 27, 27, &umr_bitfield_default },
+	 { "CGCG_REG_CTRL", 28, 28, &umr_bitfield_default },
+	 { "SLEEP_MODE", 29, 30, &umr_bitfield_default },
+	 { "SPARE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_CGCG_RAMP_CTRL[] = {
+	 { "DOWN_DIV_START_UNIT", 0, 3, &umr_bitfield_default },
+	 { "DOWN_DIV_STEP_UNIT", 4, 7, &umr_bitfield_default },
+	 { "UP_DIV_START_UNIT", 8, 11, &umr_bitfield_default },
+	 { "UP_DIV_STEP_UNIT", 12, 15, &umr_bitfield_default },
+	 { "STEP_DELAY_CNT", 16, 27, &umr_bitfield_default },
+	 { "STEP_DELAY_UNIT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_DYN_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_DYN_PG_REQUEST[] = {
+	 { "PG_REQUEST_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PG_DELAY[] = {
+	 { "POWER_UP_DELAY", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CMD_PROPAGATE_DELAY", 16, 23, &umr_bitfield_default },
+	 { "MEM_SLEEP_DELAY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_CU_STATUS[] = {
+	 { "WORK_PENDING", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_LB_INIT_CU_MASK[] = {
+	 { "INIT_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_LB_ALWAYS_ACTIVE_CU_MASK[] = {
+	 { "ALWAYS_ACTIVE_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_LB_PARAMS[] = {
+	 { "SKIP_L2_CHECK", 0, 0, &umr_bitfield_default },
+	 { "FIFO_SAMPLES", 1, 7, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLES", 8, 15, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_THREAD1_DELAY[] = {
+	 { "CU_IDEL_DELAY", 0, 7, &umr_bitfield_default },
+	 { "LBPW_INNER_LOOP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LBPW_OUTER_LOOP_DELAY", 16, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PG_ALWAYS_ON_CU_MASK[] = {
+	 { "AON_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_MAX_PG_CU[] = {
+	 { "MAX_POWERED_UP_CU", 0, 7, &umr_bitfield_default },
+	 { "SPARE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_AUTO_PG_CTRL[] = {
+	 { "AUTO_PG_EN", 0, 0, &umr_bitfield_default },
+	 { "AUTO_GRBM_REG_SAVE_ON_IDLE_EN", 1, 1, &umr_bitfield_default },
+	 { "AUTO_WAKE_UP_EN", 2, 2, &umr_bitfield_default },
+	 { "GRBM_REG_SAVE_GFX_IDLE_THRESHOLD", 3, 18, &umr_bitfield_default },
+	 { "PG_AFTER_GRBM_REG_SAVE_THRESHOLD", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SMU_GRBM_REG_SAVE_CTRL[] = {
+	 { "START_GRBM_REG_SAVE", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SMU_PG_CTRL[] = {
+	 { "START_PG", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SMU_PG_WAKE_UP_CTRL[] = {
+	 { "START_PG_WAKE_UP", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_RD_MASTER_INDEX[] = {
+	 { "CU_ID", 0, 3, &umr_bitfield_default },
+	 { "SH_ID", 4, 5, &umr_bitfield_default },
+	 { "SE_ID", 6, 8, &umr_bitfield_default },
+	 { "SE_NONCU_ID", 9, 9, &umr_bitfield_default },
+	 { "SE_NONCU", 10, 10, &umr_bitfield_default },
+	 { "NON_SE", 11, 13, &umr_bitfield_default },
+	 { "DATA_REG_ID", 14, 15, &umr_bitfield_default },
+	 { "SPARE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_RD_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_RD_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_RD_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_WR_CU_MASTER_MASK[] = {
+	 { "MASTER_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_WR_NONCU_MASTER_MASK[] = {
+	 { "SE_MASTER_MASK", 0, 15, &umr_bitfield_default },
+	 { "GC_MASTER_MASK", 16, 16, &umr_bitfield_default },
+	 { "TC0_MASTER_MASK", 17, 17, &umr_bitfield_default },
+	 { "TC1_MASTER_MASK", 18, 18, &umr_bitfield_default },
+	 { "SPARE0_MASTER_MASK", 19, 19, &umr_bitfield_default },
+	 { "SPARE1_MASTER_MASK", 20, 20, &umr_bitfield_default },
+	 { "SPARE2_MASTER_MASK", 21, 21, &umr_bitfield_default },
+	 { "SPARE3_MASTER_MASK", 22, 22, &umr_bitfield_default },
+	 { "RESERVED", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_WR_CTRL[] = {
+	 { "BPM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE_COMMAND", 12, 12, &umr_bitfield_default },
+	 { "READ_COMMAND", 13, 13, &umr_bitfield_default },
+	 { "RESERVED_1", 14, 15, &umr_bitfield_default },
+	 { "CGLS_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "CGLS_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "CGLS_ON", 18, 18, &umr_bitfield_default },
+	 { "CGLS_OFF", 19, 19, &umr_bitfield_default },
+	 { "CGCG_OVERRIDE_0", 20, 20, &umr_bitfield_default },
+	 { "CGCG_OVERRIDE_1", 21, 21, &umr_bitfield_default },
+	 { "MGCG_OVERRIDE_0", 22, 22, &umr_bitfield_default },
+	 { "MGCG_OVERRIDE_1", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_2", 24, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_WR_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_CU_MASTER_BUSY[] = {
+	 { "BUSY_BUSY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SERDES_NONCU_MASTER_BUSY[] = {
+	 { "SE_MASTER_BUSY", 0, 15, &umr_bitfield_default },
+	 { "GC_MASTER_BUSY", 16, 16, &umr_bitfield_default },
+	 { "TC0_MASTER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "TC1_MASTER_BUSY", 18, 18, &umr_bitfield_default },
+	 { "SPARE0_MASTER_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SPARE1_MASTER_BUSY", 20, 20, &umr_bitfield_default },
+	 { "SPARE2_MASTER_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SPARE3_MASTER_BUSY", 22, 22, &umr_bitfield_default },
+	 { "RESERVED", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_GENERAL_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_GENERAL_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_GENERAL_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_GENERAL_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_GENERAL_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_GENERAL_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_GENERAL_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_GENERAL_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_CU_PD_TIMEOUT[] = {
+	 { "TIMEOUT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_SCRATCH_ADDR[] = {
+	 { "ADDR", 0, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_SCRATCH_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_STATIC_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_PERF_COUNT_0[] = {
+	 { "FEATURE_SEL", 0, 3, &umr_bitfield_default },
+	 { "SE_INDEX", 4, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 11, &umr_bitfield_default },
+	 { "CU_INDEX", 12, 15, &umr_bitfield_default },
+	 { "EVENT_SEL", 16, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 19, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_PERF_COUNT_1[] = {
+	 { "FEATURE_SEL", 0, 3, &umr_bitfield_default },
+	 { "SE_INDEX", 4, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 11, &umr_bitfield_default },
+	 { "CU_INDEX", 12, 15, &umr_bitfield_default },
+	 { "EVENT_SEL", 16, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 19, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_VMID[] = {
+	 { "RLC_SPM_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_INT_CNTL[] = {
+	 { "RLC_SPM_INT_CNTL", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_INT_STATUS[] = {
+	 { "RLC_SPM_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 14, &umr_bitfield_default },
+	 { "RLC_SPM_DEBUG_MODE", 15, 15, &umr_bitfield_default },
+	 { "RLC_SPM_NUM_SAMPLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_LOG_ADDR[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_LOG_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPM_LOG_CONT[] = {
+	 { "CONT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPR_REG1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SAFE_MODE[] = {
+	 { "REQ", 0, 0, &umr_bitfield_default },
+	 { "MESSAGE", 1, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_GPR_REG2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_ARB_PRIORITY[] = {
+	 { "PIPE_ORDER_TS0", 0, 2, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS1", 3, 5, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS2", 6, 8, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS3", 9, 11, &umr_bitfield_default },
+	 { "TS0_DUR_MULT", 12, 13, &umr_bitfield_default },
+	 { "TS1_DUR_MULT", 14, 15, &umr_bitfield_default },
+	 { "TS2_DUR_MULT", 16, 17, &umr_bitfield_default },
+	 { "TS3_DUR_MULT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_ARB_CYCLES_0[] = {
+	 { "TS0_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS1_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_ARB_CYCLES_1[] = {
+	 { "TS2_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS3_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CDBG_SYS_GFX[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CDBG_SYS_HP3D[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CDBG_SYS_CS0[] = {
+	 { "PIPE0", 0, 7, &umr_bitfield_default },
+	 { "PIPE1", 8, 15, &umr_bitfield_default },
+	 { "PIPE2", 16, 23, &umr_bitfield_default },
+	 { "PIPE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_CDBG_SYS_CS1[] = {
+	 { "PIPE0", 0, 7, &umr_bitfield_default },
+	 { "PIPE1", 8, 15, &umr_bitfield_default },
+	 { "PIPE2", 16, 23, &umr_bitfield_default },
+	 { "PIPE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_GFX[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_HP3D[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_CS0[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_CS1[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_CS2[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_CS3[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_CS4[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_CS5[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_CS6[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_WCL_PIPE_PERCENT_CS7[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_WAVE_CNTL[] = {
+	 { "STALL_RA", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_TRAP_CONFIG[] = {
+	 { "ME_SEL", 0, 1, &umr_bitfield_default },
+	 { "PIPE_SEL", 2, 3, &umr_bitfield_default },
+	 { "QUEUE_SEL", 4, 6, &umr_bitfield_default },
+	 { "ME_MATCH", 7, 7, &umr_bitfield_default },
+	 { "PIPE_MATCH", 8, 8, &umr_bitfield_default },
+	 { "QUEUE_MATCH", 9, 9, &umr_bitfield_default },
+	 { "TRAP_EN", 15, 15, &umr_bitfield_default },
+	 { "VMID_SEL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_TRAP_MASK[] = {
+	 { "EXCP_EN", 0, 8, &umr_bitfield_default },
+	 { "REPLACE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_TBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_TBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_TMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_TMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_TRAP_DATA0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_GDBG_TRAP_DATA1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESET_DEBUG[] = {
+	 { "DISABLE_GFX_RESET", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_PER_VMID", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_ALL_VMID", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_RESOURCE", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_PRIORITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_COMPUTE_QUEUE_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_0[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_1[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_2[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_3[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_4[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_5[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_6[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_7[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_8[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_CU_9[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_0[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_1[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_2[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_3[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_4[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_5[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_6[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_7[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_8[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_RESOURCE_RESERVE_EN_CU_9[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HPD_ROQ_OFFSETS[] = {
+	 { "IQ_OFFSET", 0, 2, &umr_bitfield_default },
+	 { "PQ_OFFSET", 8, 13, &umr_bitfield_default },
+	 { "IB_OFFSET", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HPD_EOP_BASE_ADDR[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HPD_EOP_BASE_ADDR_HI[] = {
+	 { "BASE_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HPD_EOP_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HPD_EOP_CONTROL[] = {
+	 { "EOP_SIZE", 0, 5, &umr_bitfield_default },
+	 { "PROCESSING_EOP", 8, 8, &umr_bitfield_default },
+	 { "PROCESSING_QID", 9, 11, &umr_bitfield_default },
+	 { "PROCESS_EOP_EN", 12, 12, &umr_bitfield_default },
+	 { "PROCESSING_EOPIB", 13, 13, &umr_bitfield_default },
+	 { "PROCESS_EOPIB_EN", 14, 14, &umr_bitfield_default },
+	 { "EOP_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "EOP_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "PEND_Q_SEM", 28, 30, &umr_bitfield_default },
+	 { "PEND_SIG_SEM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MQD_BASE_ADDR[] = {
+	 { "BASE_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MQD_BASE_ADDR_HI[] = {
+	 { "BASE_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_ACTIVE[] = {
+	 { "ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "IB_VMID", 8, 11, &umr_bitfield_default },
+	 { "VQID", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PERSISTENT_STATE[] = {
+	 { "PRELOAD_REQ", 0, 0, &umr_bitfield_default },
+	 { "PRELOAD_SIZE", 8, 17, &umr_bitfield_default },
+	 { "DISP_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PIPE_PRIORITY[] = {
+	 { "PIPE_PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_QUEUE_PRIORITY[] = {
+	 { "PRIORITY_LEVEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_QUANTUM[] = {
+	 { "QUANTUM_EN", 0, 0, &umr_bitfield_default },
+	 { "QUANTUM_SCALE", 4, 4, &umr_bitfield_default },
+	 { "QUANTUM_DURATION", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_BASE_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_RPTR[] = {
+	 { "CONSUMED_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_RPTR_REPORT_ADDR[] = {
+	 { "RPTR_REPORT_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_RPTR_REPORT_ADDR_HI[] = {
+	 { "RPTR_REPORT_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_WPTR_POLL_ADDR[] = {
+	 { "WPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_WPTR_POLL_ADDR_HI[] = {
+	 { "WPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_DOORBELL_CONTROL[] = {
+	 { "DOORBELL_OFFSET", 2, 22, &umr_bitfield_default },
+	 { "DOORBELL_SOURCE", 28, 28, &umr_bitfield_default },
+	 { "DOORBELL_SCHD_HIT", 29, 29, &umr_bitfield_default },
+	 { "DOORBELL_EN", 30, 30, &umr_bitfield_default },
+	 { "DOORBELL_HIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_PQ_CONTROL[] = {
+	 { "QUEUE_SIZE", 0, 5, &umr_bitfield_default },
+	 { "RPTR_BLOCK_SIZE", 8, 13, &umr_bitfield_default },
+	 { "ENDIAN_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MIN_AVAIL_SIZE", 20, 21, &umr_bitfield_default },
+	 { "PQ_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "PQ_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "NO_UPDATE_RPTR", 27, 27, &umr_bitfield_default },
+	 { "UNORD_DISPATCH", 28, 28, &umr_bitfield_default },
+	 { "ROQ_PQ_IB_FLIP", 29, 29, &umr_bitfield_default },
+	 { "PRIV_STATE", 30, 30, &umr_bitfield_default },
+	 { "KMD_QUEUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_IB_BASE_ADDR[] = {
+	 { "IB_BASE_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_IB_BASE_ADDR_HI[] = {
+	 { "IB_BASE_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_IB_RPTR[] = {
+	 { "CONSUMED_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_IB_CONTROL[] = {
+	 { "IB_SIZE", 0, 19, &umr_bitfield_default },
+	 { "MIN_IB_AVAIL_SIZE", 20, 21, &umr_bitfield_default },
+	 { "IB_ATC", 23, 23, &umr_bitfield_default },
+	 { "IB_CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "IB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "PROCESSING_IB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_IQ_TIMER[] = {
+	 { "WAIT_TIME", 0, 7, &umr_bitfield_default },
+	 { "RETRY_TYPE", 8, 10, &umr_bitfield_default },
+	 { "INTERRUPT_TYPE", 12, 13, &umr_bitfield_default },
+	 { "INTERRUPT_SIZE", 16, 21, &umr_bitfield_default },
+	 { "IQ_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "IQ_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "PROCESS_IQ_EN", 29, 29, &umr_bitfield_default },
+	 { "PROCESSING_IQ", 30, 30, &umr_bitfield_default },
+	 { "ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_IQ_RPTR[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_DEQUEUE_REQUEST[] = {
+	 { "DEQUEUE_REQ", 0, 1, &umr_bitfield_default },
+	 { "IQ_REQ_PEND", 4, 4, &umr_bitfield_default },
+	 { "DEQUEUE_INT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_DMA_OFFLOAD[] = {
+	 { "DMA_OFFLOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_SEMA_CMD[] = {
+	 { "RETRY", 0, 0, &umr_bitfield_default },
+	 { "RESULT", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_MSG_TYPE[] = {
+	 { "ACTION", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_ATOMIC0_PREOP_LO[] = {
+	 { "ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_ATOMIC0_PREOP_HI[] = {
+	 { "ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_ATOMIC1_PREOP_LO[] = {
+	 { "ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_ATOMIC1_PREOP_HI[] = {
+	 { "ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_HQ_SCHEDULER0[] = {
+	 { "DEQUEUE_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DEQUEUE_RETRY_CNT", 2, 3, &umr_bitfield_default },
+	 { "RSV_5_4", 4, 5, &umr_bitfield_default },
+	 { "QUEUE_RUN_ONCE", 6, 6, &umr_bitfield_default },
+	 { "SCRATCH_RAM_INIT", 7, 7, &umr_bitfield_default },
+	 { "TCL2_DIRTY", 8, 8, &umr_bitfield_default },
+	 { "PG_ACTIVATED", 9, 9, &umr_bitfield_default },
+	 { "CG_ACTIVATED", 10, 10, &umr_bitfield_default },
+	 { "RSVR_31_11", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_HQD_HQ_SCHEDULER1[] = {
+	 { "SCHEDULER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_MQD_CONTROL[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "MQD_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "MQD_VOLATILE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield DIDT_IND_INDEX[] = {
+	 { "DIDT_IND_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DIDT_IND_DATA[] = {
+	 { "DIDT_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH0_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH0_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH0_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH1_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH1_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH1_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH2_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH2_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH2_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH3_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH3_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_WATCH3_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID0_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID0_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID1_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID1_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID2_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID2_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID3_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID3_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID4_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID4_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID5_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID5_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID6_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID6_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID7_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID7_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID8_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID8_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID9_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID9_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID10_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID10_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID11_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID11_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID12_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID12_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID13_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID13_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID14_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID14_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID15_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_VMID15_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID0[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID1[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID2[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID3[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID4[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID5[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID6[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID7[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID8[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID9[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID10[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID11[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID12[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID13[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID14[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_VMID15[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID0[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID1[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID2[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID3[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID4[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID5[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID6[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID7[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID8[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID9[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID10[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID11[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID12[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID13[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID14[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_VMID15[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_RESET0[] = {
+	 { "RESOURCE0_RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE1_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESOURCE2_RESET", 2, 2, &umr_bitfield_default },
+	 { "RESOURCE3_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESOURCE4_RESET", 4, 4, &umr_bitfield_default },
+	 { "RESOURCE5_RESET", 5, 5, &umr_bitfield_default },
+	 { "RESOURCE6_RESET", 6, 6, &umr_bitfield_default },
+	 { "RESOURCE7_RESET", 7, 7, &umr_bitfield_default },
+	 { "RESOURCE8_RESET", 8, 8, &umr_bitfield_default },
+	 { "RESOURCE9_RESET", 9, 9, &umr_bitfield_default },
+	 { "RESOURCE10_RESET", 10, 10, &umr_bitfield_default },
+	 { "RESOURCE11_RESET", 11, 11, &umr_bitfield_default },
+	 { "RESOURCE12_RESET", 12, 12, &umr_bitfield_default },
+	 { "RESOURCE13_RESET", 13, 13, &umr_bitfield_default },
+	 { "RESOURCE14_RESET", 14, 14, &umr_bitfield_default },
+	 { "RESOURCE15_RESET", 15, 15, &umr_bitfield_default },
+	 { "RESOURCE16_RESET", 16, 16, &umr_bitfield_default },
+	 { "RESOURCE17_RESET", 17, 17, &umr_bitfield_default },
+	 { "RESOURCE18_RESET", 18, 18, &umr_bitfield_default },
+	 { "RESOURCE19_RESET", 19, 19, &umr_bitfield_default },
+	 { "RESOURCE20_RESET", 20, 20, &umr_bitfield_default },
+	 { "RESOURCE21_RESET", 21, 21, &umr_bitfield_default },
+	 { "RESOURCE22_RESET", 22, 22, &umr_bitfield_default },
+	 { "RESOURCE23_RESET", 23, 23, &umr_bitfield_default },
+	 { "RESOURCE24_RESET", 24, 24, &umr_bitfield_default },
+	 { "RESOURCE25_RESET", 25, 25, &umr_bitfield_default },
+	 { "RESOURCE26_RESET", 26, 26, &umr_bitfield_default },
+	 { "RESOURCE27_RESET", 27, 27, &umr_bitfield_default },
+	 { "RESOURCE28_RESET", 28, 28, &umr_bitfield_default },
+	 { "RESOURCE29_RESET", 29, 29, &umr_bitfield_default },
+	 { "RESOURCE30_RESET", 30, 30, &umr_bitfield_default },
+	 { "RESOURCE31_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_RESET1[] = {
+	 { "RESOURCE32_RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE33_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESOURCE34_RESET", 2, 2, &umr_bitfield_default },
+	 { "RESOURCE35_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESOURCE36_RESET", 4, 4, &umr_bitfield_default },
+	 { "RESOURCE37_RESET", 5, 5, &umr_bitfield_default },
+	 { "RESOURCE38_RESET", 6, 6, &umr_bitfield_default },
+	 { "RESOURCE39_RESET", 7, 7, &umr_bitfield_default },
+	 { "RESOURCE40_RESET", 8, 8, &umr_bitfield_default },
+	 { "RESOURCE41_RESET", 9, 9, &umr_bitfield_default },
+	 { "RESOURCE42_RESET", 10, 10, &umr_bitfield_default },
+	 { "RESOURCE43_RESET", 11, 11, &umr_bitfield_default },
+	 { "RESOURCE44_RESET", 12, 12, &umr_bitfield_default },
+	 { "RESOURCE45_RESET", 13, 13, &umr_bitfield_default },
+	 { "RESOURCE46_RESET", 14, 14, &umr_bitfield_default },
+	 { "RESOURCE47_RESET", 15, 15, &umr_bitfield_default },
+	 { "RESOURCE48_RESET", 16, 16, &umr_bitfield_default },
+	 { "RESOURCE49_RESET", 17, 17, &umr_bitfield_default },
+	 { "RESOURCE50_RESET", 18, 18, &umr_bitfield_default },
+	 { "RESOURCE51_RESET", 19, 19, &umr_bitfield_default },
+	 { "RESOURCE52_RESET", 20, 20, &umr_bitfield_default },
+	 { "RESOURCE53_RESET", 21, 21, &umr_bitfield_default },
+	 { "RESOURCE54_RESET", 22, 22, &umr_bitfield_default },
+	 { "RESOURCE55_RESET", 23, 23, &umr_bitfield_default },
+	 { "RESOURCE56_RESET", 24, 24, &umr_bitfield_default },
+	 { "RESOURCE57_RESET", 25, 25, &umr_bitfield_default },
+	 { "RESOURCE58_RESET", 26, 26, &umr_bitfield_default },
+	 { "RESOURCE59_RESET", 27, 27, &umr_bitfield_default },
+	 { "RESOURCE60_RESET", 28, 28, &umr_bitfield_default },
+	 { "RESOURCE61_RESET", 29, 29, &umr_bitfield_default },
+	 { "RESOURCE62_RESET", 30, 30, &umr_bitfield_default },
+	 { "RESOURCE63_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_RESOURCE_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_COMPUTE_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_RESET_MASK[] = {
+	 { "ME0_GFXHP3D_PIX_RESET", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_RESET", 1, 1, &umr_bitfield_default },
+	 { "ME0_CS_RESET", 2, 2, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "ME1_PIPE0_RESET", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_RESET", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_RESET", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_RESET", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_RESET", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_RESET", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_RESET", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_RESET", 11, 11, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "PIPE_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SIGNATURE_CONTROL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SIGNATURE_MASK[] = {
+	 { "INPUT_BUS_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SX_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SX_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SX_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SX_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_DB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_PA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_VGT_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SQ_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SC_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SC_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SC_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SC_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SC_SIGNATURE4[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SC_SIGNATURE5[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SC_SIGNATURE6[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SC_SIGNATURE7[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_IA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_IA_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SPI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_SPI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_TA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_TD_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_CB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_BCI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RAS_BCI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_RENDER_CONTROL[] = {
+	 { "DEPTH_CLEAR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCIL_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DEPTH_COPY", 2, 2, &umr_bitfield_default },
+	 { "STENCIL_COPY", 3, 3, &umr_bitfield_default },
+	 { "RESUMMARIZE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STENCIL_COMPRESS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DEPTH_COMPRESS_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "COPY_CENTROID", 7, 7, &umr_bitfield_default },
+	 { "COPY_SAMPLE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_COUNT_CONTROL[] = {
+	 { "ZPASS_INCREMENT_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "PERFECT_ZPASS_COUNTS", 1, 1, &umr_bitfield_default },
+	 { "SAMPLE_RATE", 4, 6, &umr_bitfield_default },
+	 { "ZPASS_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "ZFAIL_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "SFAIL_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "DBFAIL_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "SLICE_EVEN_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEPTH_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "Z_READ_ONLY", 24, 24, &umr_bitfield_default },
+	 { "STENCIL_READ_ONLY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_RENDER_OVERRIDE[] = {
+	 { "FORCE_HIZ_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE0", 2, 3, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE1", 4, 5, &umr_bitfield_default },
+	 { "FORCE_SHADER_Z_ORDER", 6, 6, &umr_bitfield_default },
+	 { "FAST_Z_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "FAST_STENCIL_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "NOOP_CULL_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "FORCE_COLOR_KILL", 10, 10, &umr_bitfield_default },
+	 { "FORCE_Z_READ", 11, 11, &umr_bitfield_default },
+	 { "FORCE_STENCIL_READ", 12, 12, &umr_bitfield_default },
+	 { "FORCE_FULL_Z_RANGE", 13, 14, &umr_bitfield_default },
+	 { "FORCE_QC_SMASK_CONFLICT", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_VIEWPORT_CLAMP", 16, 16, &umr_bitfield_default },
+	 { "IGNORE_SC_ZRANGE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_FULLY_COVERED", 18, 18, &umr_bitfield_default },
+	 { "FORCE_Z_LIMIT_SUMM", 19, 20, &umr_bitfield_default },
+	 { "MAX_TILES_IN_DTT", 21, 25, &umr_bitfield_default },
+	 { "DISABLE_TILE_RATE_TILES", 26, 26, &umr_bitfield_default },
+	 { "FORCE_Z_DIRTY", 27, 27, &umr_bitfield_default },
+	 { "FORCE_STENCIL_DIRTY", 28, 28, &umr_bitfield_default },
+	 { "FORCE_Z_VALID", 29, 29, &umr_bitfield_default },
+	 { "FORCE_STENCIL_VALID", 30, 30, &umr_bitfield_default },
+	 { "PRESERVE_COMPRESSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_RENDER_OVERRIDE2[] = {
+	 { "PARTIAL_SQUAD_LAUNCH_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "PARTIAL_SQUAD_LAUNCH_COUNTDOWN", 2, 4, &umr_bitfield_default },
+	 { "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_COLOR_ON_VALIDATION", 7, 7, &umr_bitfield_default },
+	 { "DECOMPRESS_Z_ON_FLUSH", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_REG_SNOOP", 9, 9, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_HIER_DEPTH_DISABLE", 10, 10, &umr_bitfield_default },
+	 { "SEPARATE_HIZS_FUNC_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "HIZ_ZFUNC", 12, 14, &umr_bitfield_default },
+	 { "HIS_SFUNC_FF", 15, 17, &umr_bitfield_default },
+	 { "HIS_SFUNC_BF", 18, 20, &umr_bitfield_default },
+	 { "PRESERVE_ZRANGE", 21, 21, &umr_bitfield_default },
+	 { "PRESERVE_SRESULTS", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_FAST_PASS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_HTILE_DATA_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEPTH_BOUNDS_MIN[] = {
+	 { "MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEPTH_BOUNDS_MAX[] = {
+	 { "MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_STENCIL_CLEAR[] = {
+	 { "CLEAR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEPTH_CLEAR[] = {
+	 { "DEPTH_CLEAR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_SCREEN_SCISSOR_TL[] = {
+	 { "TL_X", 0, 15, &umr_bitfield_default },
+	 { "TL_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_SCREEN_SCISSOR_BR[] = {
+	 { "BR_X", 0, 15, &umr_bitfield_default },
+	 { "BR_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEPTH_INFO[] = {
+	 { "ADDR5_SWIZZLE_MASK", 0, 3, &umr_bitfield_default },
+	 { "ARRAY_MODE", 4, 7, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 8, 12, &umr_bitfield_default },
+	 { "BANK_WIDTH", 13, 14, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 15, 16, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 17, 18, &umr_bitfield_default },
+	 { "NUM_BANKS", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_Z_INFO[] = {
+	 { "FORMAT", 0, 1, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 2, 3, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "READ_SIZE", 28, 28, &umr_bitfield_default },
+	 { "TILE_SURFACE_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "ZRANGE_PRECISION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_STENCIL_INFO[] = {
+	 { "FORMAT", 0, 0, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "TILE_STENCIL_DISABLE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_Z_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_STENCIL_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_Z_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_STENCIL_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEPTH_SIZE[] = {
+	 { "PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "HEIGHT_TILE_MAX", 11, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEPTH_SLICE[] = {
+	 { "SLICE_TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_BC_BASE_ADDR_HI[] = {
+	 { "ADDRESS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield COHER_DEST_BASE_HI_0[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COHER_DEST_BASE_HI_1[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COHER_DEST_BASE_HI_2[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COHER_DEST_BASE_HI_3[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COHER_DEST_BASE_2[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COHER_DEST_BASE_3[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_WINDOW_OFFSET[] = {
+	 { "WINDOW_X_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "WINDOW_Y_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_WINDOW_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_WINDOW_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_RULE[] = {
+	 { "CLIP_RULE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CLIPRECT_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_EDGERULE[] = {
+	 { "ER_TRI", 0, 3, &umr_bitfield_default },
+	 { "ER_POINT", 4, 7, &umr_bitfield_default },
+	 { "ER_RECT", 8, 11, &umr_bitfield_default },
+	 { "ER_LINE_LR", 12, 17, &umr_bitfield_default },
+	 { "ER_LINE_RL", 18, 23, &umr_bitfield_default },
+	 { "ER_LINE_TB", 24, 27, &umr_bitfield_default },
+	 { "ER_LINE_BT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_HARDWARE_SCREEN_OFFSET[] = {
+	 { "HW_SCREEN_OFFSET_X", 0, 8, &umr_bitfield_default },
+	 { "HW_SCREEN_OFFSET_Y", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_TARGET_MASK[] = {
+	 { "TARGET0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "TARGET1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "TARGET2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "TARGET3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "TARGET4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "TARGET5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "TARGET6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "TARGET7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_SHADER_MASK[] = {
+	 { "OUTPUT0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "OUTPUT1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "OUTPUT2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "OUTPUT3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "OUTPUT4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "OUTPUT5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "OUTPUT6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "OUTPUT7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_GENERIC_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_GENERIC_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield COHER_DEST_BASE_0[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield COHER_DEST_BASE_1[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_4_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_4_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_5_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_5_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_6_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_6_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_7_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_7_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_8_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_8_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_9_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_9_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_10_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_10_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_11_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_11_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_12_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_12_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_13_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_13_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_14_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_14_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_15_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_SCISSOR_15_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_0[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_0[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_1[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_1[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_2[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_2[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_3[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_3[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_4[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_4[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_5[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_5[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_6[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_6[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_7[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_7[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_8[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_8[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_9[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_9[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_10[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_10[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_11[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_11[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_12[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_12[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_13[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_13[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_14[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_14[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMIN_15[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_VPORT_ZMAX_15[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_RASTER_CONFIG[] = {
+	 { "RB_MAP_PKR0", 0, 1, &umr_bitfield_default },
+	 { "RB_MAP_PKR1", 2, 3, &umr_bitfield_default },
+	 { "RB_XSEL2", 4, 5, &umr_bitfield_default },
+	 { "RB_XSEL", 6, 6, &umr_bitfield_default },
+	 { "RB_YSEL", 7, 7, &umr_bitfield_default },
+	 { "PKR_MAP", 8, 9, &umr_bitfield_default },
+	 { "PKR_XSEL", 10, 11, &umr_bitfield_default },
+	 { "PKR_YSEL", 12, 13, &umr_bitfield_default },
+	 { "PKR_XSEL2", 14, 15, &umr_bitfield_default },
+	 { "SC_MAP", 16, 17, &umr_bitfield_default },
+	 { "SC_XSEL", 18, 19, &umr_bitfield_default },
+	 { "SC_YSEL", 20, 21, &umr_bitfield_default },
+	 { "SE_MAP", 24, 25, &umr_bitfield_default },
+	 { "SE_XSEL", 26, 27, &umr_bitfield_default },
+	 { "SE_YSEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_RASTER_CONFIG_1[] = {
+	 { "SE_PAIR_MAP", 0, 1, &umr_bitfield_default },
+	 { "SE_PAIR_XSEL", 2, 3, &umr_bitfield_default },
+	 { "SE_PAIR_YSEL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_SCREEN_EXTENT_CONTROL[] = {
+	 { "SLICE_EVEN_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PERFMON_CNTX_CNTL[] = {
+	 { "PERFMON_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RINGID[] = {
+	 { "RINGID", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_MAX_VTX_INDX[] = {
+	 { "MAX_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_MIN_VTX_INDX[] = {
+	 { "MIN_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_INDX_OFFSET[] = {
+	 { "INDX_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_MULTI_PRIM_IB_RESET_INDX[] = {
+	 { "RESET_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND_RED[] = {
+	 { "BLEND_RED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND_GREEN[] = {
+	 { "BLEND_GREEN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND_BLUE[] = {
+	 { "BLEND_BLUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND_ALPHA[] = {
+	 { "BLEND_ALPHA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_STENCIL_CONTROL[] = {
+	 { "STENCILFAIL", 0, 3, &umr_bitfield_default },
+	 { "STENCILZPASS", 4, 7, &umr_bitfield_default },
+	 { "STENCILZFAIL", 8, 11, &umr_bitfield_default },
+	 { "STENCILFAIL_BF", 12, 15, &umr_bitfield_default },
+	 { "STENCILZPASS_BF", 16, 19, &umr_bitfield_default },
+	 { "STENCILZFAIL_BF", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_STENCILREFMASK[] = {
+	 { "STENCILTESTVAL", 0, 7, &umr_bitfield_default },
+	 { "STENCILMASK", 8, 15, &umr_bitfield_default },
+	 { "STENCILWRITEMASK", 16, 23, &umr_bitfield_default },
+	 { "STENCILOPVAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_STENCILREFMASK_BF[] = {
+	 { "STENCILTESTVAL_BF", 0, 7, &umr_bitfield_default },
+	 { "STENCILMASK_BF", 8, 15, &umr_bitfield_default },
+	 { "STENCILWRITEMASK_BF", 16, 23, &umr_bitfield_default },
+	 { "STENCILOPVAL_BF", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_1[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_1[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_1[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_1[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_1[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_1[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_2[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_2[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_2[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_2[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_2[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_2[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_3[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_3[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_3[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_3[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_3[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_3[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_4[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_4[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_4[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_4[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_4[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_4[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_5[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_5[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_5[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_5[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_5[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_5[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_6[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_6[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_6[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_6[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_6[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_6[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_7[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_7[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_7[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_7[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_7[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_7[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_8[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_8[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_8[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_8[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_8[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_8[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_9[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_9[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_9[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_9[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_9[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_9[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_10[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_10[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_10[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_10[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_10[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_10[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_11[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_11[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_11[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_11[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_11[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_11[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_12[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_12[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_12[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_12[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_12[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_12[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_13[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_13[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_13[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_13[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_13[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_13[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_14[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_14[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_14[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_14[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_14[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_14[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XSCALE_15[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_XOFFSET_15[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YSCALE_15[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_YOFFSET_15[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZSCALE_15[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VPORT_ZOFFSET_15[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_0_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_0_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_0_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_0_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_1_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_1_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_1_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_1_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_2_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_2_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_2_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_2_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_3_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_3_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_3_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_3_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_4_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_4_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_4_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_4_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_5_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_5_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_5_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_UCP_5_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_0[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_1[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_2[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_3[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_4[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_5[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_6[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_7[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_8[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_9[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_10[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_11[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_12[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_13[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_14[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_15[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_16[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_17[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_18[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_19[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_20[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_21[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_22[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_23[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_24[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_25[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_26[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_27[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_28[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_29[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_30[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_CNTL_31[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_VS_OUT_CONFIG[] = {
+	 { "VS_EXPORT_COUNT", 1, 5, &umr_bitfield_default },
+	 { "VS_HALF_PACK", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_ENA[] = {
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_INPUT_ADDR[] = {
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_INTERP_CONTROL_0[] = {
+	 { "FLAT_SHADE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PNT_SPRITE_ENA", 1, 1, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_X", 2, 4, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Y", 5, 7, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Z", 8, 10, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_W", 11, 13, &umr_bitfield_default },
+	 { "PNT_SPRITE_TOP_1", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PS_IN_CONTROL[] = {
+	 { "NUM_INTERP", 0, 5, &umr_bitfield_default },
+	 { "PARAM_GEN", 6, 6, &umr_bitfield_default },
+	 { "BC_OPTIMIZE_DISABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_BARYC_CNTL[] = {
+	 { "PERSP_CENTER_CNTL", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTROID_CNTL", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_CNTL", 8, 8, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_CNTL", 12, 12, &umr_bitfield_default },
+	 { "POS_FLOAT_LOCATION", 16, 17, &umr_bitfield_default },
+	 { "POS_FLOAT_ULC", 20, 20, &umr_bitfield_default },
+	 { "FRONT_FACE_ALL_BITS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_TMPRING_SIZE[] = {
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_POS_FORMAT[] = {
+	 { "POS0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "POS1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "POS2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "POS3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_Z_FORMAT[] = {
+	 { "Z_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_SHADER_COL_FORMAT[] = {
+	 { "COL0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "COL1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "COL2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "COL3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+	 { "COL4_EXPORT_FORMAT", 16, 19, &umr_bitfield_default },
+	 { "COL5_EXPORT_FORMAT", 20, 23, &umr_bitfield_default },
+	 { "COL6_EXPORT_FORMAT", 24, 27, &umr_bitfield_default },
+	 { "COL7_EXPORT_FORMAT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND0_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND1_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND2_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND3_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND4_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND5_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND6_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_BLEND7_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CS_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield GFX_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_POINT_X_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_POINT_Y_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_POINT_SIZE[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_POINT_CULL_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_BASE_HI[] = {
+	 { "BASE_ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_BASE[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DRAW_INITIATOR[] = {
+	 { "SOURCE_SELECT", 0, 1, &umr_bitfield_default },
+	 { "MAJOR_MODE", 2, 3, &umr_bitfield_default },
+	 { "SPRITE_EN_R6XX", 4, 4, &umr_bitfield_default },
+	 { "NOT_EOP", 5, 5, &umr_bitfield_default },
+	 { "USE_OPAQUE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_IMMED_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_EVENT_ADDRESS_REG[] = {
+	 { "ADDRESS_LOW", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_DEPTH_CONTROL[] = {
+	 { "STENCIL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "Z_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "Z_WRITE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "ZFUNC", 4, 6, &umr_bitfield_default },
+	 { "BACKFACE_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "STENCILFUNC", 8, 10, &umr_bitfield_default },
+	 { "STENCILFUNC_BF", 20, 22, &umr_bitfield_default },
+	 { "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_COLOR_WRITES_ON_DEPTH_PASS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_EQAA[] = {
+	 { "MAX_ANCHOR_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLES", 4, 6, &umr_bitfield_default },
+	 { "MASK_EXPORT_NUM_SAMPLES", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "HIGH_QUALITY_INTERSECTIONS", 16, 16, &umr_bitfield_default },
+	 { "INCOHERENT_EQAA_READS", 17, 17, &umr_bitfield_default },
+	 { "INTERPOLATE_COMP_Z", 18, 18, &umr_bitfield_default },
+	 { "INTERPOLATE_SRC_Z", 19, 19, &umr_bitfield_default },
+	 { "STATIC_ANCHOR_ASSOCIATIONS", 20, 20, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_EQAA_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "OVERRASTERIZATION_AMOUNT", 24, 26, &umr_bitfield_default },
+	 { "ENABLE_POSTZ_OVERRASTERIZATION", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR_CONTROL[] = {
+	 { "DEGAMMA_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "ROP3", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_SHADER_CONTROL[] = {
+	 { "Z_EXPORT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCIL_TEST_VAL_EXPORT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STENCIL_OP_VAL_EXPORT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "Z_ORDER", 4, 5, &umr_bitfield_default },
+	 { "KILL_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "COVERAGE_TO_MASK_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MASK_EXPORT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "EXEC_ON_HIER_FAIL", 9, 9, &umr_bitfield_default },
+	 { "EXEC_ON_NOOP", 10, 10, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "DEPTH_BEFORE_SHADER", 12, 12, &umr_bitfield_default },
+	 { "CONSERVATIVE_Z_EXPORT", 13, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_CLIP_CNTL[] = {
+	 { "UCP_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "UCP_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "UCP_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "UCP_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "UCP_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "UCP_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "PS_UCP_Y_SCALE_NEG", 13, 13, &umr_bitfield_default },
+	 { "PS_UCP_MODE", 14, 15, &umr_bitfield_default },
+	 { "CLIP_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "UCP_CULL_ONLY_ENA", 17, 17, &umr_bitfield_default },
+	 { "BOUNDARY_EDGE_FLAG_ENA", 18, 18, &umr_bitfield_default },
+	 { "DX_CLIP_SPACE_DEF", 19, 19, &umr_bitfield_default },
+	 { "DIS_CLIP_ERR_DETECT", 20, 20, &umr_bitfield_default },
+	 { "VTX_KILL_OR", 21, 21, &umr_bitfield_default },
+	 { "DX_RASTERIZATION_KILL", 22, 22, &umr_bitfield_default },
+	 { "DX_LINEAR_ATTR_CLIP_ENA", 24, 24, &umr_bitfield_default },
+	 { "VTE_VPORT_PROVOKE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "ZCLIP_NEAR_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "ZCLIP_FAR_DISABLE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_SC_MODE_CNTL[] = {
+	 { "CULL_FRONT", 0, 0, &umr_bitfield_default },
+	 { "CULL_BACK", 1, 1, &umr_bitfield_default },
+	 { "FACE", 2, 2, &umr_bitfield_default },
+	 { "POLY_MODE", 3, 4, &umr_bitfield_default },
+	 { "POLYMODE_FRONT_PTYPE", 5, 7, &umr_bitfield_default },
+	 { "POLYMODE_BACK_PTYPE", 8, 10, &umr_bitfield_default },
+	 { "POLY_OFFSET_FRONT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "POLY_OFFSET_BACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "POLY_OFFSET_PARA_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "VTX_WINDOW_OFFSET_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "PROVOKING_VTX_LAST", 19, 19, &umr_bitfield_default },
+	 { "PERSP_CORR_DIS", 20, 20, &umr_bitfield_default },
+	 { "MULTI_PRIM_IB_ENA", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VTE_CNTL[] = {
+	 { "VPORT_X_SCALE_ENA", 0, 0, &umr_bitfield_default },
+	 { "VPORT_X_OFFSET_ENA", 1, 1, &umr_bitfield_default },
+	 { "VPORT_Y_SCALE_ENA", 2, 2, &umr_bitfield_default },
+	 { "VPORT_Y_OFFSET_ENA", 3, 3, &umr_bitfield_default },
+	 { "VPORT_Z_SCALE_ENA", 4, 4, &umr_bitfield_default },
+	 { "VPORT_Z_OFFSET_ENA", 5, 5, &umr_bitfield_default },
+	 { "VTX_XY_FMT", 8, 8, &umr_bitfield_default },
+	 { "VTX_Z_FMT", 9, 9, &umr_bitfield_default },
+	 { "VTX_W0_FMT", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_REF", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_VS_OUT_CNTL[] = {
+	 { "CLIP_DIST_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_6", 6, 6, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_7", 7, 7, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_0", 8, 8, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_1", 9, 9, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_2", 10, 10, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_3", 11, 11, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_4", 12, 12, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_5", 13, 13, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_6", 14, 14, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_7", 15, 15, &umr_bitfield_default },
+	 { "USE_VTX_POINT_SIZE", 16, 16, &umr_bitfield_default },
+	 { "USE_VTX_EDGE_FLAG", 17, 17, &umr_bitfield_default },
+	 { "USE_VTX_RENDER_TARGET_INDX", 18, 18, &umr_bitfield_default },
+	 { "USE_VTX_VIEWPORT_INDX", 19, 19, &umr_bitfield_default },
+	 { "USE_VTX_KILL_FLAG", 20, 20, &umr_bitfield_default },
+	 { "VS_OUT_MISC_VEC_ENA", 21, 21, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST0_VEC_ENA", 22, 22, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST1_VEC_ENA", 23, 23, &umr_bitfield_default },
+	 { "VS_OUT_MISC_SIDE_BUS_ENA", 24, 24, &umr_bitfield_default },
+	 { "USE_VTX_GS_CUT_FLAG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_NANINF_CNTL[] = {
+	 { "VTE_XY_INF_DISCARD", 0, 0, &umr_bitfield_default },
+	 { "VTE_Z_INF_DISCARD", 1, 1, &umr_bitfield_default },
+	 { "VTE_W_INF_DISCARD", 2, 2, &umr_bitfield_default },
+	 { "VTE_0XNANINF_IS_0", 3, 3, &umr_bitfield_default },
+	 { "VTE_XY_NAN_RETAIN", 4, 4, &umr_bitfield_default },
+	 { "VTE_Z_NAN_RETAIN", 5, 5, &umr_bitfield_default },
+	 { "VTE_W_NAN_RETAIN", 6, 6, &umr_bitfield_default },
+	 { "VTE_W_RECIP_NAN_IS_0", 7, 7, &umr_bitfield_default },
+	 { "VS_XY_NAN_TO_INF", 8, 8, &umr_bitfield_default },
+	 { "VS_XY_INF_RETAIN", 9, 9, &umr_bitfield_default },
+	 { "VS_Z_NAN_TO_INF", 10, 10, &umr_bitfield_default },
+	 { "VS_Z_INF_RETAIN", 11, 11, &umr_bitfield_default },
+	 { "VS_W_NAN_TO_INF", 12, 12, &umr_bitfield_default },
+	 { "VS_W_INF_RETAIN", 13, 13, &umr_bitfield_default },
+	 { "VS_CLIP_DIST_INF_DISCARD", 14, 14, &umr_bitfield_default },
+	 { "VTE_NO_OUTPUT_NEG_0", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_LINE_STIPPLE_CNTL[] = {
+	 { "LINE_STIPPLE_RESET", 0, 1, &umr_bitfield_default },
+	 { "EXPAND_FULL_LENGTH", 2, 2, &umr_bitfield_default },
+	 { "FRACTIONAL_ACCUM", 3, 3, &umr_bitfield_default },
+	 { "DIAMOND_ADJUST", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_LINE_STIPPLE_SCALE[] = {
+	 { "LINE_STIPPLE_SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PRIM_FILTER_CNTL[] = {
+	 { "TRIANGLE_FILTER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "LINE_FILTER_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "POINT_FILTER_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RECTANGLE_FILTER_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "TRIANGLE_EXPAND_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINE_EXPAND_ENA", 5, 5, &umr_bitfield_default },
+	 { "POINT_EXPAND_ENA", 6, 6, &umr_bitfield_default },
+	 { "RECTANGLE_EXPAND_ENA", 7, 7, &umr_bitfield_default },
+	 { "PRIM_EXPAND_CONSTANT", 8, 15, &umr_bitfield_default },
+	 { "XMAX_RIGHT_EXCLUSION", 30, 30, &umr_bitfield_default },
+	 { "YMAX_BOTTOM_EXCLUSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_POINT_SIZE[] = {
+	 { "HEIGHT", 0, 15, &umr_bitfield_default },
+	 { "WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_POINT_MINMAX[] = {
+	 { "MIN_SIZE", 0, 15, &umr_bitfield_default },
+	 { "MAX_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_LINE_CNTL[] = {
+	 { "WIDTH", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_LINE_STIPPLE[] = {
+	 { "LINE_PATTERN", 0, 15, &umr_bitfield_default },
+	 { "REPEAT_COUNT", 16, 23, &umr_bitfield_default },
+	 { "PATTERN_BIT_ORDER", 28, 28, &umr_bitfield_default },
+	 { "AUTO_RESET_CNTL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_OUTPUT_PATH_CNTL[] = {
+	 { "PATH_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_HOS_CNTL[] = {
+	 { "TESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_HOS_MAX_TESS_LEVEL[] = {
+	 { "MAX_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_HOS_MIN_TESS_LEVEL[] = {
+	 { "MIN_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_HOS_REUSE_DEPTH[] = {
+	 { "REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GROUP_PRIM_TYPE[] = {
+	 { "PRIM_TYPE", 0, 4, &umr_bitfield_default },
+	 { "RETAIN_ORDER", 14, 14, &umr_bitfield_default },
+	 { "RETAIN_QUADS", 15, 15, &umr_bitfield_default },
+	 { "PRIM_ORDER", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GROUP_FIRST_DECR[] = {
+	 { "FIRST_DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GROUP_DECR[] = {
+	 { "DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GROUP_VECT_0_CNTL[] = {
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GROUP_VECT_1_CNTL[] = {
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GROUP_VECT_0_FMT_CNTL[] = {
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GROUP_VECT_1_FMT_CNTL[] = {
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_MODE[] = {
+	 { "MODE", 0, 2, &umr_bitfield_default },
+	 { "RESERVED_0", 3, 3, &umr_bitfield_default },
+	 { "CUT_MODE", 4, 5, &umr_bitfield_default },
+	 { "RESERVED_1", 6, 10, &umr_bitfield_default },
+	 { "GS_C_PACK_EN", 11, 11, &umr_bitfield_default },
+	 { "RESERVED_2", 12, 12, &umr_bitfield_default },
+	 { "ES_PASSTHRU", 13, 13, &umr_bitfield_default },
+	 { "COMPUTE_MODE", 14, 14, &umr_bitfield_default },
+	 { "FAST_COMPUTE_MODE", 15, 15, &umr_bitfield_default },
+	 { "ELEMENT_INFO_EN", 16, 16, &umr_bitfield_default },
+	 { "PARTIAL_THD_AT_EOI", 17, 17, &umr_bitfield_default },
+	 { "SUPPRESS_CUTS", 18, 18, &umr_bitfield_default },
+	 { "ES_WRITE_OPTIMIZE", 19, 19, &umr_bitfield_default },
+	 { "GS_WRITE_OPTIMIZE", 20, 20, &umr_bitfield_default },
+	 { "ONCHIP", 21, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_ONCHIP_CNTL[] = {
+	 { "ES_VERTS_PER_SUBGRP", 0, 10, &umr_bitfield_default },
+	 { "GS_PRIMS_PER_SUBGRP", 11, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_MODE_CNTL_0[] = {
+	 { "MSAA_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VPORT_SCISSOR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "LINE_STIPPLE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PKR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_MODE_CNTL_1[] = {
+	 { "WALK_SIZE", 0, 0, &umr_bitfield_default },
+	 { "WALK_ALIGNMENT", 1, 1, &umr_bitfield_default },
+	 { "WALK_ALIGN8_PRIM_FITS_ST", 2, 2, &umr_bitfield_default },
+	 { "WALK_FENCE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "WALK_FENCE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "SUPERTILE_WALK_ORDER_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "TILE_WALK_ORDER_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "TILE_COVER_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "TILE_COVER_NO_SCISSOR", 10, 10, &umr_bitfield_default },
+	 { "ZMM_LINE_EXTENT", 11, 11, &umr_bitfield_default },
+	 { "ZMM_LINE_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "ZMM_RECT_EXTENT", 13, 13, &umr_bitfield_default },
+	 { "KILL_PIX_POST_HI_Z", 14, 14, &umr_bitfield_default },
+	 { "KILL_PIX_POST_DETAIL_MASK", 15, 15, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLE", 16, 16, &umr_bitfield_default },
+	 { "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "MULTI_GPU_SUPERTILE_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE", 20, 23, &umr_bitfield_default },
+	 { "MULTI_GPU_PRIM_DISCARD_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "FORCE_EOV_CNTDWN_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "FORCE_EOV_REZ_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_PRIMITIVE_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_WATER_MARK", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_PER_ES[] = {
+	 { "GS_PER_ES", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_ES_PER_GS[] = {
+	 { "ES_PER_GS", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_PER_VS[] = {
+	 { "GS_PER_VS", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GSVS_RING_OFFSET_1[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GSVS_RING_OFFSET_2[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GSVS_RING_OFFSET_3[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_OUT_PRIM_TYPE[] = {
+	 { "OUTPRIM_TYPE", 0, 5, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_1", 8, 13, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_2", 16, 21, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_3", 22, 27, &umr_bitfield_default },
+	 { "UNIQUE_TYPE_PER_STREAM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_SIZE[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_MAX_SIZE[] = {
+	 { "MAX_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+	 { "SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "BUF_TYPE", 4, 5, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 6, 7, &umr_bitfield_default },
+	 { "ATC", 8, 8, &umr_bitfield_default },
+	 { "NOT_EOP", 9, 9, &umr_bitfield_default },
+	 { "REQ_PATH", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PRIMITIVEID_EN[] = {
+	 { "PRIMITIVEID_EN", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_RESET_ON_EOI", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_DMA_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PRIMITIVEID_RESET[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_EVENT_INITIATOR[] = {
+	 { "EVENT_TYPE", 0, 5, &umr_bitfield_default },
+	 { "ADDRESS_HI", 18, 26, &umr_bitfield_default },
+	 { "EXTENDED_EVENT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_MULTI_PRIM_IB_RESET_EN[] = {
+	 { "RESET_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_INSTANCE_STEP_RATE_0[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_INSTANCE_STEP_RATE_1[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_MULTI_VGT_PARAM[] = {
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "PARTIAL_VS_WAVE_ON", 16, 16, &umr_bitfield_default },
+	 { "SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "PARTIAL_ES_WAVE_ON", 18, 18, &umr_bitfield_default },
+	 { "SWITCH_ON_EOI", 19, 19, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_ESGS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GSVS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_REUSE_OFF[] = {
+	 { "REUSE_OFF", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_VTX_CNT_EN[] = {
+	 { "VTX_CNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_HTILE_SURFACE[] = {
+	 { "LINEAR", 0, 0, &umr_bitfield_default },
+	 { "FULL_CACHE", 1, 1, &umr_bitfield_default },
+	 { "HTILE_USES_PRELOAD_WIN", 2, 2, &umr_bitfield_default },
+	 { "PRELOAD", 3, 3, &umr_bitfield_default },
+	 { "PREFETCH_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PREFETCH_HEIGHT", 10, 15, &umr_bitfield_default },
+	 { "DST_OUTSIDE_ZERO_TO_ONE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_SRESULTS_COMPARE_STATE0[] = {
+	 { "COMPAREFUNC0", 0, 2, &umr_bitfield_default },
+	 { "COMPAREVALUE0", 4, 11, &umr_bitfield_default },
+	 { "COMPAREMASK0", 12, 19, &umr_bitfield_default },
+	 { "ENABLE0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_SRESULTS_COMPARE_STATE1[] = {
+	 { "COMPAREFUNC1", 0, 2, &umr_bitfield_default },
+	 { "COMPAREVALUE1", 4, 11, &umr_bitfield_default },
+	 { "COMPAREMASK1", 12, 19, &umr_bitfield_default },
+	 { "ENABLE1", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PRELOAD_CONTROL[] = {
+	 { "START_X", 0, 7, &umr_bitfield_default },
+	 { "START_Y", 8, 15, &umr_bitfield_default },
+	 { "MAX_X", 16, 23, &umr_bitfield_default },
+	 { "MAX_Y", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_VTX_STRIDE_0[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_OFFSET_0[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_VTX_STRIDE_1[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_OFFSET_1[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_VTX_STRIDE_2[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_OFFSET_2[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_VTX_STRIDE_3[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_OFFSET_3[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_DRAW_OPAQUE_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[] = {
+	 { "VERTEX_STRIDE", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_MAX_VERT_OUT[] = {
+	 { "MAX_VERT_OUT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_SHADER_STAGES_EN[] = {
+	 { "LS_EN", 0, 1, &umr_bitfield_default },
+	 { "HS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 4, &umr_bitfield_default },
+	 { "GS_EN", 5, 5, &umr_bitfield_default },
+	 { "VS_EN", 6, 7, &umr_bitfield_default },
+	 { "DYNAMIC_HS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_LS_HS_CONFIG[] = {
+	 { "NUM_PATCHES", 0, 7, &umr_bitfield_default },
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+	 { "HS_NUM_OUTPUT_CP", 14, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_VERT_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_VERT_ITEMSIZE_1[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_VERT_ITEMSIZE_2[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_VERT_ITEMSIZE_3[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_TF_PARAM[] = {
+	 { "TYPE", 0, 1, &umr_bitfield_default },
+	 { "PARTITIONING", 2, 4, &umr_bitfield_default },
+	 { "TOPOLOGY", 5, 7, &umr_bitfield_default },
+	 { "RESERVED_REDUC_AXIS", 8, 8, &umr_bitfield_default },
+	 { "DEPRECATED", 9, 9, &umr_bitfield_default },
+	 { "NUM_DS_WAVES_PER_SIMD", 10, 13, &umr_bitfield_default },
+	 { "DISABLE_DONUTS", 14, 14, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 15, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_ALPHA_TO_MASK[] = {
+	 { "ALPHA_TO_MASK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET0", 8, 9, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET1", 10, 11, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET2", 12, 13, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET3", 14, 15, &umr_bitfield_default },
+	 { "OFFSET_ROUND", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_POLY_OFFSET_DB_FMT_CNTL[] = {
+	 { "POLY_OFFSET_NEG_NUM_DB_BITS", 0, 7, &umr_bitfield_default },
+	 { "POLY_OFFSET_DB_IS_FLOAT_FMT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_POLY_OFFSET_CLAMP[] = {
+	 { "CLAMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_POLY_OFFSET_FRONT_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_POLY_OFFSET_FRONT_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_POLY_OFFSET_BACK_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_POLY_OFFSET_BACK_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GS_INSTANCE_CNT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CNT", 2, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_CONFIG[] = {
+	 { "STREAMOUT_0_EN", 0, 0, &umr_bitfield_default },
+	 { "STREAMOUT_1_EN", 1, 1, &umr_bitfield_default },
+	 { "STREAMOUT_2_EN", 2, 2, &umr_bitfield_default },
+	 { "STREAMOUT_3_EN", 3, 3, &umr_bitfield_default },
+	 { "RAST_STREAM", 4, 6, &umr_bitfield_default },
+	 { "RAST_STREAM_MASK", 8, 11, &umr_bitfield_default },
+	 { "USE_RAST_STREAM_MASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_CONFIG[] = {
+	 { "STREAM_0_BUFFER_EN", 0, 3, &umr_bitfield_default },
+	 { "STREAM_1_BUFFER_EN", 4, 7, &umr_bitfield_default },
+	 { "STREAM_2_BUFFER_EN", 8, 11, &umr_bitfield_default },
+	 { "STREAM_3_BUFFER_EN", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CENTROID_PRIORITY_0[] = {
+	 { "DISTANCE_0", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_1", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_2", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_3", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_4", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_5", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_6", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_CENTROID_PRIORITY_1[] = {
+	 { "DISTANCE_8", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_9", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_10", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_11", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_12", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_13", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_14", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_LINE_CNTL[] = {
+	 { "EXPAND_LINE_WIDTH", 9, 9, &umr_bitfield_default },
+	 { "LAST_PIXEL", 10, 10, &umr_bitfield_default },
+	 { "PERPENDICULAR_ENDCAP_ENA", 11, 11, &umr_bitfield_default },
+	 { "DX10_DIAMOND_TEST_ENA", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_CONFIG[] = {
+	 { "MSAA_NUM_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "AA_MASK_CENTROID_DTMN", 4, 4, &umr_bitfield_default },
+	 { "MAX_SAMPLE_DIST", 13, 16, &umr_bitfield_default },
+	 { "MSAA_EXPOSED_SAMPLES", 20, 22, &umr_bitfield_default },
+	 { "DETAIL_TO_EXPOSED_MODE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_VTX_CNTL[] = {
+	 { "PIX_CENTER", 0, 0, &umr_bitfield_default },
+	 { "ROUND_MODE", 1, 2, &umr_bitfield_default },
+	 { "QUANT_MODE", 3, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_GB_VERT_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_GB_VERT_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_GB_HORZ_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_CL_GB_HORZ_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_MASK_X0Y0_X1Y0[] = {
+	 { "AA_MASK_X0Y0", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_AA_MASK_X0Y1_X1Y1[] = {
+	 { "AA_MASK_X0Y1", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_VERTEX_REUSE_BLOCK_CNTL[] = {
+	 { "VTX_REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_OUT_DEALLOC_CNTL[] = {
+	 { "DEALLOC_DIST", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR0_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR1_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR2_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR3_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR4_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR5_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR6_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_COLOR7_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_EOP_DONE_ADDR_LO[] = {
+	 { "ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_EOP_DONE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_EOP_DONE_DATA_LO[] = {
+	 { "DATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_EOP_DONE_DATA_HI[] = {
+	 { "DATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_EOP_LAST_FENCE_LO[] = {
+	 { "LAST_FENCE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_EOP_LAST_FENCE_HI[] = {
+	 { "LAST_FENCE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STREAM_OUT_ADDR_LO[] = {
+	 { "STREAM_OUT_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "STREAM_OUT_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STREAM_OUT_ADDR_HI[] = {
+	 { "STREAM_OUT_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_WRITTEN_COUNT0_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_WRITTEN_COUNT0_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_NEEDED_COUNT0_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_NEEDED_COUNT0_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_WRITTEN_COUNT1_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_WRITTEN_COUNT1_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_NEEDED_COUNT1_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_NEEDED_COUNT1_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_WRITTEN_COUNT2_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_WRITTEN_COUNT2_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_NEEDED_COUNT2_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_NEEDED_COUNT2_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_WRITTEN_COUNT3_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_WRITTEN_COUNT3_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_NEEDED_COUNT3_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_NUM_PRIM_NEEDED_COUNT3_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PIPE_STATS_ADDR_LO[] = {
+	 { "PIPE_STATS_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "PIPE_STATS_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PIPE_STATS_ADDR_HI[] = {
+	 { "PIPE_STATS_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_IAVERT_COUNT_LO[] = {
+	 { "IAVERT_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_IAVERT_COUNT_HI[] = {
+	 { "IAVERT_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_IAPRIM_COUNT_LO[] = {
+	 { "IAPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_IAPRIM_COUNT_HI[] = {
+	 { "IAPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_GSPRIM_COUNT_LO[] = {
+	 { "GSPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_GSPRIM_COUNT_HI[] = {
+	 { "GSPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_VSINVOC_COUNT_LO[] = {
+	 { "VSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_VSINVOC_COUNT_HI[] = {
+	 { "VSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_GSINVOC_COUNT_LO[] = {
+	 { "GSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_GSINVOC_COUNT_HI[] = {
+	 { "GSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_HSINVOC_COUNT_LO[] = {
+	 { "HSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_HSINVOC_COUNT_HI[] = {
+	 { "HSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_DSINVOC_COUNT_LO[] = {
+	 { "DSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_DSINVOC_COUNT_HI[] = {
+	 { "DSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PA_CINVOC_COUNT_LO[] = {
+	 { "CINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PA_CINVOC_COUNT_HI[] = {
+	 { "CINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PA_CPRIM_COUNT_LO[] = {
+	 { "CPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PA_CPRIM_COUNT_HI[] = {
+	 { "CPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SC_PSINVOC_COUNT0_LO[] = {
+	 { "PSINVOC_COUNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SC_PSINVOC_COUNT0_HI[] = {
+	 { "PSINVOC_COUNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SC_PSINVOC_COUNT1_LO[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SC_PSINVOC_COUNT1_HI[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_CSINVOC_COUNT_LO[] = {
+	 { "CSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_VGT_CSINVOC_COUNT_HI[] = {
+	 { "CSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_STRMOUT_CNTL[] = {
+	 { "OFFSET_UPDATE_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_UMSK[] = {
+	 { "OBSOLETE_UMSK", 0, 7, &umr_bitfield_default },
+	 { "OBSOLETE_SWAP", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield SCRATCH_ADDR[] = {
+	 { "OBSOLETE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_APPEND_ADDR_LO[] = {
+	 { "MEM_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_APPEND_ADDR_HI[] = {
+	 { "MEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "CS_PS_SEL", 16, 16, &umr_bitfield_default },
+	 { "COMMAND", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_APPEND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_APPEND_LAST_CS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_APPEND_LAST_PS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_MC_WADDR_LO[] = {
+	 { "ME_MC_WADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ME_MC_WADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_MC_WADDR_HI[] = {
+	 { "ME_MC_WADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_MC_WDATA_LO[] = {
+	 { "ME_MC_WDATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_MC_WDATA_HI[] = {
+	 { "ME_MC_WDATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_MC_RADDR_LO[] = {
+	 { "ME_MC_RADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ME_MC_RADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ME_MC_RADDR_HI[] = {
+	 { "ME_MC_RADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SEM_WAIT_TIMER[] = {
+	 { "SEM_WAIT_TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SIG_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SIG_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_WAIT_REG_MEM_TIMEOUT[] = {
+	 { "WAIT_REG_MEM_TIMEOUT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_WAIT_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_WAIT_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_PFP_CONTROL[] = {
+	 { "SRC_ATC", 12, 12, &umr_bitfield_default },
+	 { "SRC_CACHE_POLICY", 13, 14, &umr_bitfield_default },
+	 { "SRC_VOLATILE", 15, 15, &umr_bitfield_default },
+	 { "DST_SELECT", 20, 21, &umr_bitfield_default },
+	 { "DST_ATC", 24, 24, &umr_bitfield_default },
+	 { "DST_CACHE_POLICY", 25, 26, &umr_bitfield_default },
+	 { "DST_VOLATILE", 27, 27, &umr_bitfield_default },
+	 { "SRC_SELECT", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_ME_CONTROL[] = {
+	 { "SRC_ATC", 12, 12, &umr_bitfield_default },
+	 { "SRC_CACHE_POLICY", 13, 14, &umr_bitfield_default },
+	 { "SRC_VOLATILE", 15, 15, &umr_bitfield_default },
+	 { "DST_SELECT", 20, 21, &umr_bitfield_default },
+	 { "DST_ATC", 24, 24, &umr_bitfield_default },
+	 { "DST_CACHE_POLICY", 25, 26, &umr_bitfield_default },
+	 { "DST_VOLATILE", 27, 27, &umr_bitfield_default },
+	 { "SRC_SELECT", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_COHER_BASE_HI[] = {
+	 { "COHER_BASE_HI_256B", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_COHER_START_DELAY[] = {
+	 { "START_DELAY_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_COHER_CNTL[] = {
+	 { "DEST_BASE_0_ENA", 0, 0, &umr_bitfield_default },
+	 { "DEST_BASE_1_ENA", 1, 1, &umr_bitfield_default },
+	 { "CB0_DEST_BASE_ENA", 6, 6, &umr_bitfield_default },
+	 { "CB1_DEST_BASE_ENA", 7, 7, &umr_bitfield_default },
+	 { "CB2_DEST_BASE_ENA", 8, 8, &umr_bitfield_default },
+	 { "CB3_DEST_BASE_ENA", 9, 9, &umr_bitfield_default },
+	 { "CB4_DEST_BASE_ENA", 10, 10, &umr_bitfield_default },
+	 { "CB5_DEST_BASE_ENA", 11, 11, &umr_bitfield_default },
+	 { "CB6_DEST_BASE_ENA", 12, 12, &umr_bitfield_default },
+	 { "CB7_DEST_BASE_ENA", 13, 13, &umr_bitfield_default },
+	 { "DB_DEST_BASE_ENA", 14, 14, &umr_bitfield_default },
+	 { "TCL1_VOL_ACTION_ENA", 15, 15, &umr_bitfield_default },
+	 { "TC_VOL_ACTION_ENA", 16, 16, &umr_bitfield_default },
+	 { "TC_WB_ACTION_ENA", 18, 18, &umr_bitfield_default },
+	 { "DEST_BASE_2_ENA", 19, 19, &umr_bitfield_default },
+	 { "DEST_BASE_3_ENA", 21, 21, &umr_bitfield_default },
+	 { "TCL1_ACTION_ENA", 22, 22, &umr_bitfield_default },
+	 { "TC_ACTION_ENA", 23, 23, &umr_bitfield_default },
+	 { "CB_ACTION_ENA", 25, 25, &umr_bitfield_default },
+	 { "DB_ACTION_ENA", 26, 26, &umr_bitfield_default },
+	 { "SH_KCACHE_ACTION_ENA", 27, 27, &umr_bitfield_default },
+	 { "SH_KCACHE_VOL_ACTION_ENA", 28, 28, &umr_bitfield_default },
+	 { "SH_ICACHE_ACTION_ENA", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_COHER_SIZE[] = {
+	 { "COHER_SIZE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_COHER_BASE[] = {
+	 { "COHER_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_COHER_STATUS[] = {
+	 { "MATCHING_GFX_CNTX", 0, 7, &umr_bitfield_default },
+	 { "MEID", 24, 25, &umr_bitfield_default },
+	 { "PHASE1_STATUS", 30, 30, &umr_bitfield_default },
+	 { "STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_ME_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_ME_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_ME_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_ME_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_ME_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_PFP_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_PFP_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_PFP_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_PFP_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_PFP_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_CNTL[] = {
+	 { "MIN_AVAILSZ", 4, 5, &umr_bitfield_default },
+	 { "BUFFER_DEPTH", 16, 19, &umr_bitfield_default },
+	 { "PIO_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
+	 { "PIO_FIFO_FULL", 29, 29, &umr_bitfield_default },
+	 { "PIO_COUNT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_DMA_READ_TAGS[] = {
+	 { "DMA_READ_TAG", 0, 25, &umr_bitfield_default },
+	 { "DMA_READ_TAG_VALID", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_COHER_SIZE_HI[] = {
+	 { "COHER_SIZE_HI_256B", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_IB_CONTROL[] = {
+	 { "IB_EN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PFP_LOAD_CONTROL[] = {
+	 { "CONFIG_REG_EN", 0, 0, &umr_bitfield_default },
+	 { "CNTX_REG_EN", 1, 1, &umr_bitfield_default },
+	 { "UCONFIG_REG_EN", 15, 15, &umr_bitfield_default },
+	 { "SH_GFX_REG_EN", 16, 16, &umr_bitfield_default },
+	 { "SH_CS_REG_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_RB_OFFSET[] = {
+	 { "RB_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB1_OFFSET[] = {
+	 { "IB1_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB2_OFFSET[] = {
+	 { "IB2_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB1_PREAMBLE_BEGIN[] = {
+	 { "IB1_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB1_PREAMBLE_END[] = {
+	 { "IB1_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB2_PREAMBLE_BEGIN[] = {
+	 { "IB2_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB2_PREAMBLE_END[] = {
+	 { "IB2_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_INIT_BASE_LO[] = {
+	 { "INIT_BASE_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_INIT_BASE_HI[] = {
+	 { "INIT_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_INIT_BUFSZ[] = {
+	 { "INIT_BUFSZ", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_CE_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ST_BASE_LO[] = {
+	 { "ST_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ST_BASE_HI[] = {
+	 { "ST_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_ST_BUFSZ[] = {
+	 { "ST_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_EOP_DONE_EVENT_CNTL[] = {
+	 { "WBINV_TC_OP", 0, 6, &umr_bitfield_default },
+	 { "WBINV_ACTION_ENA", 12, 17, &umr_bitfield_default },
+	 { "CACHE_CONTROL", 25, 26, &umr_bitfield_default },
+	 { "EOP_VOLATILE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_EOP_DONE_DATA_CNTL[] = {
+	 { "CNTX_ID", 0, 15, &umr_bitfield_default },
+	 { "DST_SEL", 16, 17, &umr_bitfield_default },
+	 { "INT_SEL", 24, 26, &umr_bitfield_default },
+	 { "DATA_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_GFX_INDEX[] = {
+	 { "INSTANCE_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 15, &umr_bitfield_default },
+	 { "SE_INDEX", 16, 23, &umr_bitfield_default },
+	 { "SH_BROADCAST_WRITES", 29, 29, &umr_bitfield_default },
+	 { "INSTANCE_BROADCAST_WRITES", 30, 30, &umr_bitfield_default },
+	 { "SE_BROADCAST_WRITES", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_ESGS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_GSVS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_FILLED_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_FILLED_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_FILLED_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_STRMOUT_BUFFER_FILLED_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_NUM_INDICES[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_TF_RING_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_HS_OFFCHIP_PARAM[] = {
+	 { "OFFCHIP_BUFFERING", 0, 8, &umr_bitfield_default },
+	 { "OFFCHIP_GRANULARITY", 9, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_TF_MEMORY_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_LINE_STIPPLE_VALUE[] = {
+	 { "LINE_STIPPLE_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_LINE_STIPPLE_STATE[] = {
+	 { "CURRENT_PTR", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_SCREEN_EXTENT_MIN_0[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_SCREEN_EXTENT_MAX_0[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_SCREEN_EXTENT_MIN_1[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_SCREEN_EXTENT_MAX_1[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_P3D_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_P3D_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_P3D_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_P3D_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_P3D_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_HP3D_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_HP3D_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_HP3D_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_HP3D_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_USERDATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_USERDATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_USERDATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_THREAD_TRACE_USERDATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQC_CACHES[] = {
+	 { "INST_INVALIDATE", 0, 0, &umr_bitfield_default },
+	 { "DATA_INVALIDATE", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE_VOLATILE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_CS_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_CS_BC_BASE_ADDR_HI[] = {
+	 { "ADDRESS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_OCCLUSION_COUNT0_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_OCCLUSION_COUNT0_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_OCCLUSION_COUNT1_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_OCCLUSION_COUNT1_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_OCCLUSION_COUNT2_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_OCCLUSION_COUNT2_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_OCCLUSION_COUNT3_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_OCCLUSION_COUNT3_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_ZPASS_COUNT_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_ZPASS_COUNT_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_RD_ADDR[] = {
+	 { "READ_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_RD_DATA[] = {
+	 { "READ_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_RD_BURST_ADDR[] = {
+	 { "BURST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_RD_BURST_COUNT[] = {
+	 { "BURST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_RD_BURST_DATA[] = {
+	 { "BURST_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_WR_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_WR_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_WR_BURST_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_WR_BURST_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_WRITE_COMPLETE[] = {
+	 { "WRITE_COMPLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_CNTL[] = {
+	 { "AINC", 0, 5, &umr_bitfield_default },
+	 { "UNUSED1", 6, 7, &umr_bitfield_default },
+	 { "DMODE", 8, 8, &umr_bitfield_default },
+	 { "UNUSED2", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_COMPLETE[] = {
+	 { "COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "UNUSED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_OFFSET0[] = {
+	 { "OFFSET0", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_OFFSET1[] = {
+	 { "OFFSET1", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_DST[] = {
+	 { "DST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_OP[] = {
+	 { "OP", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_SRC0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_SRC0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_SRC1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_SRC1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_READ0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_READ0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_READ1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_ATOM_READ1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_RESOURCE_CNTL[] = {
+	 { "INDEX", 0, 5, &umr_bitfield_default },
+	 { "UNUSED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_RESOURCE[] = {
+	 { "FLAG", 0, 0, &umr_bitfield_default },
+	 { "COUNTER", 1, 12, &umr_bitfield_default },
+	 { "TYPE", 13, 13, &umr_bitfield_default },
+	 { "DED", 14, 14, &umr_bitfield_default },
+	 { "RELEASE_ALL", 15, 15, &umr_bitfield_default },
+	 { "HEAD_QUEUE", 16, 26, &umr_bitfield_default },
+	 { "HEAD_VALID", 27, 27, &umr_bitfield_default },
+	 { "HEAD_FLAG", 28, 28, &umr_bitfield_default },
+	 { "UNUSED1", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_GWS_RESOURCE_CNT[] = {
+	 { "RESOURCE_CNT", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_CNTL[] = {
+	 { "INDEX", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_COUNTER[] = {
+	 { "SPACE_AVAILABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_ADDRESS[] = {
+	 { "DS_ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "CRAWLER_TYPE", 16, 19, &umr_bitfield_default },
+	 { "CRAWLER", 20, 23, &umr_bitfield_default },
+	 { "UNUSED", 24, 29, &umr_bitfield_default },
+	 { "NO_ALLOC", 30, 30, &umr_bitfield_default },
+	 { "ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_OA_INCDEC[] = {
+	 { "VALUE", 0, 30, &umr_bitfield_default },
+	 { "INCDEC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPG_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPG_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPG_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPG_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPF_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPF_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPF_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPF_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE0_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE0_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE1_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE1_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE2_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE2_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE3_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE3_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER8_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER8_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER9_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER9_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER10_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER10_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER11_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER11_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER12_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER12_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER13_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER13_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER14_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER14_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER15_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER15_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CPG_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield CPG_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CPG_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CPF_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield CPF_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield CPF_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CP_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
+	 { "SPM_PERFMON_STATE", 4, 7, &umr_bitfield_default },
+	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield CPC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE0_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE1_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE2_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield GRBM_SE3_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield WD_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield IA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield VGT_PERFCOUNTER_SEID_MASK[] = {
+	 { "PERF_SEID_IGNORE_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SU_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield PA_SC_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER2_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER3_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield SPI_PERFCOUNTER_BINS[] = {
+	 { "BIN0_MIN", 0, 3, &umr_bitfield_default },
+	 { "BIN0_MAX", 4, 7, &umr_bitfield_default },
+	 { "BIN1_MIN", 8, 11, &umr_bitfield_default },
+	 { "BIN1_MAX", 12, 15, &umr_bitfield_default },
+	 { "BIN2_MIN", 16, 19, &umr_bitfield_default },
+	 { "BIN2_MAX", 20, 23, &umr_bitfield_default },
+	 { "BIN3_MIN", 24, 27, &umr_bitfield_default },
+	 { "BIN3_MAX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER8_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER9_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER10_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER11_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER12_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER13_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER14_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER15_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER_CTRL[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+	 { "CNTR_RATE", 8, 12, &umr_bitfield_default },
+	 { "DISABLE_FLUSH", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_PERFCOUNTER_CTRL2[] = {
+	 { "FORCE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER2_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER3_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER0_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield SX_PERFCOUNTER1_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER2_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER3_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield GDS_PERFCOUNTER0_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 17, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 17, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCP_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER_FILTER[] = {
+	 { "OP_FILTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OP_FILTER_SEL", 1, 3, &umr_bitfield_default },
+	 { "FORMAT_FILTER_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FORMAT_FILTER_SEL", 5, 9, &umr_bitfield_default },
+	 { "CLEAR_FILTER_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "CLEAR_FILTER_SEL", 11, 11, &umr_bitfield_default },
+	 { "MRT_FILTER_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "MRT_FILTER_SEL", 13, 15, &umr_bitfield_default },
+	 { "NUM_SAMPLES_FILTER_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "NUM_SAMPLES_FILTER_SEL", 18, 20, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS_FILTER_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS_FILTER_SEL", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 18, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 18, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_PERFMON_CNTL[] = {
+	 { "RESERVED1", 0, 11, &umr_bitfield_default },
+	 { "PERFMON_RING_MODE", 12, 13, &umr_bitfield_default },
+	 { "RESERVED", 14, 15, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_PERFMON_RING_BASE_LO[] = {
+	 { "RING_BASE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_PERFMON_RING_BASE_HI[] = {
+	 { "RING_BASE_HI", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_PERFMON_RING_SIZE[] = {
+	 { "RING_BASE_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_PERFMON_SEGMENT_SIZE[] = {
+	 { "PERFMON_SEGMENT_SIZE", 0, 7, &umr_bitfield_default },
+	 { "RESERVED1", 8, 10, &umr_bitfield_default },
+	 { "GLOBAL_NUM_LINE", 11, 15, &umr_bitfield_default },
+	 { "SE0_NUM_LINE", 16, 20, &umr_bitfield_default },
+	 { "SE1_NUM_LINE", 21, 25, &umr_bitfield_default },
+	 { "SE2_NUM_LINE", 26, 30, &umr_bitfield_default },
+	 { "RESERVED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_SE_MUXSEL_ADDR[] = {
+	 { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_SE_MUXSEL_DATA[] = {
+	 { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_CPG_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_CPC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_CPF_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_CB_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_DB_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_PA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_GDS_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_IA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_SC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_TCC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_TCA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_TCP_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_TA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_TD_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_VGT_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_SPI_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_SQG_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_TCS_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_SX_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_GLOBAL_MUXSEL_ADDR[] = {
+	 { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_GLOBAL_MUXSEL_DATA[] = {
+	 { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_RING_RDPTR[] = {
+	 { "PERFMON_RING_RDPTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_SPM_SEGMENT_THRESHOLD[] = {
+	 { "NUM_SEGMENT_THRESHOLD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 2, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield RLC_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_SM_CTRL_REG[] = {
+	 { "ON_SEQ_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_SEQ_DELAY", 4, 11, &umr_bitfield_default },
+	 { "MGCG_ENABLED", 12, 12, &umr_bitfield_default },
+	 { "BASE_MODE", 16, 16, &umr_bitfield_default },
+	 { "SM_MODE", 17, 19, &umr_bitfield_default },
+	 { "SM_MODE_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "OVERRIDE", 21, 21, &umr_bitfield_default },
+	 { "LS_OVERRIDE", 22, 22, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD_EN", 23, 23, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_RD_CTRL_REG[] = {
+	 { "ROW_MUX_SEL", 0, 4, &umr_bitfield_default },
+	 { "REG_MUX_SEL", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_RD_REG[] = {
+	 { "READ_DATA", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_USER_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU0_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU0_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU0_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU0_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU0_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU1_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU1_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU1_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU1_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU1_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU2_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU2_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU2_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU2_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU2_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU3_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU3_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU3_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU3_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU3_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU4_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU4_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU4_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU4_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU4_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU5_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU5_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU5_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU5_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU5_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU6_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU6_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU6_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU6_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU6_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU7_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU7_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU7_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU7_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU7_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU8_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU8_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU8_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU8_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU8_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU9_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU9_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU9_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU9_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU9_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU10_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU10_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU10_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU10_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU10_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU11_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU11_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU11_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU11_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU11_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU12_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU12_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU12_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU12_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU12_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU13_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU13_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU13_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU13_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU13_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU14_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU14_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU14_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU14_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU14_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU15_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU15_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU15_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU15_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTS_CU15_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SPI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "ALL_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "GRP3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "GRP2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "GRP1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "GRP0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_PC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "BACK_CLK_ON_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "FRONT_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_BCI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "CORE6_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "CORE5_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "CORE4_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_VGT_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "GS_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_IA_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_WD_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "ADC_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "RBIU_INPUT_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_PA_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SU_CLK_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CL_CLK_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_CLK_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SQ_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SQG_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_ALU_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_TEX_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_LDS_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_POWER_THROTTLE[] = {
+	 { "MIN_POWER", 0, 13, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 29, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_POWER_THROTTLE2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SX_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SX_CLK_CTRL1[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SX_CLK_CTRL2[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SX_CLK_CTRL3[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_SX_CLK_CTRL4[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TD_CGTT_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TA_CGTT_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_TCP_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_TCI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_GDS_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield DB_CGTT_CLK_CTRL_0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CB_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCC_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCA_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield TCS_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_CP_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_CPF_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_CPC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield CGTT_RLC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield SQ_HV_VMID_CTRL[] = {
+	 { "DEFAULT_VMID", 0, 3, &umr_bitfield_default },
+	 { "ALLOWED_VMID_MASK", 4, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield GFX_PIPE_PRIORITY[] = {
+	 { "HP_PIPE_SELECT", 0, 0, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gfx70_regs.i b/src/lib/ip/gfx70_regs.i
new file mode 100644
index 0000000..8336d7e
--- /dev/null
+++ b/src/lib/ip/gfx70_regs.i
@@ -0,0 +1,2322 @@
+	{ "mmCSPRIV_CONNECT", REG_MMIO, 0x0, &CSPRIV_CONNECT[0], sizeof(CSPRIV_CONNECT)/sizeof(CSPRIV_CONNECT[0]), 0, 0 },
+	{ "mmCSPRIV_THREAD_TRACE_TG0", REG_MMIO, 0x1e, &CSPRIV_THREAD_TRACE_TG0[0], sizeof(CSPRIV_THREAD_TRACE_TG0)/sizeof(CSPRIV_THREAD_TRACE_TG0[0]), 0, 0 },
+	{ "mmCSPRIV_THREAD_TRACE_EVENT", REG_MMIO, 0x1f, &CSPRIV_THREAD_TRACE_EVENT[0], sizeof(CSPRIV_THREAD_TRACE_EVENT)/sizeof(CSPRIV_THREAD_TRACE_EVENT[0]), 0, 0 },
+	{ "mmGRBM_CNTL", REG_MMIO, 0x2000, &GRBM_CNTL[0], sizeof(GRBM_CNTL)/sizeof(GRBM_CNTL[0]), 0, 0 },
+	{ "mmGRBM_SKEW_CNTL", REG_MMIO, 0x2001, &GRBM_SKEW_CNTL[0], sizeof(GRBM_SKEW_CNTL)/sizeof(GRBM_SKEW_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS2", REG_MMIO, 0x2002, &GRBM_STATUS2[0], sizeof(GRBM_STATUS2)/sizeof(GRBM_STATUS2[0]), 0, 0 },
+	{ "mmGRBM_PWR_CNTL", REG_MMIO, 0x2003, &GRBM_PWR_CNTL[0], sizeof(GRBM_PWR_CNTL)/sizeof(GRBM_PWR_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS", REG_MMIO, 0x2004, &GRBM_STATUS[0], sizeof(GRBM_STATUS)/sizeof(GRBM_STATUS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE0", REG_MMIO, 0x2005, &GRBM_STATUS_SE0[0], sizeof(GRBM_STATUS_SE0)/sizeof(GRBM_STATUS_SE0[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE1", REG_MMIO, 0x2006, &GRBM_STATUS_SE1[0], sizeof(GRBM_STATUS_SE1)/sizeof(GRBM_STATUS_SE1[0]), 0, 0 },
+	{ "mmGRBM_SOFT_RESET", REG_MMIO, 0x2008, &GRBM_SOFT_RESET[0], sizeof(GRBM_SOFT_RESET)/sizeof(GRBM_SOFT_RESET[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_CNTL", REG_MMIO, 0x2009, &GRBM_DEBUG_CNTL[0], sizeof(GRBM_DEBUG_CNTL)/sizeof(GRBM_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_DATA", REG_MMIO, 0x200a, &GRBM_DEBUG_DATA[0], sizeof(GRBM_DEBUG_DATA)/sizeof(GRBM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_GFX_CLKEN_CNTL", REG_MMIO, 0x200c, &GRBM_GFX_CLKEN_CNTL[0], sizeof(GRBM_GFX_CLKEN_CNTL)/sizeof(GRBM_GFX_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmGRBM_WAIT_IDLE_CLOCKS", REG_MMIO, 0x200d, &GRBM_WAIT_IDLE_CLOCKS[0], sizeof(GRBM_WAIT_IDLE_CLOCKS)/sizeof(GRBM_WAIT_IDLE_CLOCKS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE2", REG_MMIO, 0x200e, &GRBM_STATUS_SE2[0], sizeof(GRBM_STATUS_SE2)/sizeof(GRBM_STATUS_SE2[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE3", REG_MMIO, 0x200f, &GRBM_STATUS_SE3[0], sizeof(GRBM_STATUS_SE3)/sizeof(GRBM_STATUS_SE3[0]), 0, 0 },
+	{ "mmGRBM_DEBUG", REG_MMIO, 0x2014, &GRBM_DEBUG[0], sizeof(GRBM_DEBUG)/sizeof(GRBM_DEBUG[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x2015, &GRBM_DEBUG_SNAPSHOT[0], sizeof(GRBM_DEBUG_SNAPSHOT)/sizeof(GRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR", REG_MMIO, 0x2016, &GRBM_READ_ERROR[0], sizeof(GRBM_READ_ERROR)/sizeof(GRBM_READ_ERROR[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR2", REG_MMIO, 0x2017, &GRBM_READ_ERROR2[0], sizeof(GRBM_READ_ERROR2)/sizeof(GRBM_READ_ERROR2[0]), 0, 0 },
+	{ "mmGRBM_INT_CNTL", REG_MMIO, 0x2018, &GRBM_INT_CNTL[0], sizeof(GRBM_INT_CNTL)/sizeof(GRBM_INT_CNTL[0]), 0, 0 },
+	{ "mmDEBUG_INDEX", REG_MMIO, 0x203c, &DEBUG_INDEX[0], sizeof(DEBUG_INDEX)/sizeof(DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDEBUG_DATA", REG_MMIO, 0x203d, &DEBUG_DATA[0], sizeof(DEBUG_DATA)/sizeof(DEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_NOWHERE", REG_MMIO, 0x203f, &GRBM_NOWHERE[0], sizeof(GRBM_NOWHERE)/sizeof(GRBM_NOWHERE[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG0", REG_MMIO, 0x2040, &GRBM_SCRATCH_REG0[0], sizeof(GRBM_SCRATCH_REG0)/sizeof(GRBM_SCRATCH_REG0[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG1", REG_MMIO, 0x2041, &GRBM_SCRATCH_REG1[0], sizeof(GRBM_SCRATCH_REG1)/sizeof(GRBM_SCRATCH_REG1[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG2", REG_MMIO, 0x2042, &GRBM_SCRATCH_REG2[0], sizeof(GRBM_SCRATCH_REG2)/sizeof(GRBM_SCRATCH_REG2[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG3", REG_MMIO, 0x2043, &GRBM_SCRATCH_REG3[0], sizeof(GRBM_SCRATCH_REG3)/sizeof(GRBM_SCRATCH_REG3[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG4", REG_MMIO, 0x2044, &GRBM_SCRATCH_REG4[0], sizeof(GRBM_SCRATCH_REG4)/sizeof(GRBM_SCRATCH_REG4[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG5", REG_MMIO, 0x2045, &GRBM_SCRATCH_REG5[0], sizeof(GRBM_SCRATCH_REG5)/sizeof(GRBM_SCRATCH_REG5[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG6", REG_MMIO, 0x2046, &GRBM_SCRATCH_REG6[0], sizeof(GRBM_SCRATCH_REG6)/sizeof(GRBM_SCRATCH_REG6[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG7", REG_MMIO, 0x2047, &GRBM_SCRATCH_REG7[0], sizeof(GRBM_SCRATCH_REG7)/sizeof(GRBM_SCRATCH_REG7[0]), 0, 0 },
+	{ "mmCP_CPC_STATUS", REG_MMIO, 0x2084, &CP_CPC_STATUS[0], sizeof(CP_CPC_STATUS)/sizeof(CP_CPC_STATUS[0]), 0, 0 },
+	{ "mmCP_CPC_BUSY_STAT", REG_MMIO, 0x2085, &CP_CPC_BUSY_STAT[0], sizeof(CP_CPC_BUSY_STAT)/sizeof(CP_CPC_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_CPC_STALLED_STAT1", REG_MMIO, 0x2086, &CP_CPC_STALLED_STAT1[0], sizeof(CP_CPC_STALLED_STAT1)/sizeof(CP_CPC_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_CPF_STATUS", REG_MMIO, 0x2087, &CP_CPF_STATUS[0], sizeof(CP_CPF_STATUS)/sizeof(CP_CPF_STATUS[0]), 0, 0 },
+	{ "mmCP_CPF_BUSY_STAT", REG_MMIO, 0x2088, &CP_CPF_BUSY_STAT[0], sizeof(CP_CPF_BUSY_STAT)/sizeof(CP_CPF_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_CPF_STALLED_STAT1", REG_MMIO, 0x2089, &CP_CPF_STALLED_STAT1[0], sizeof(CP_CPF_STALLED_STAT1)/sizeof(CP_CPF_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_CPC_MC_CNTL", REG_MMIO, 0x208a, &CP_CPC_MC_CNTL[0], sizeof(CP_CPC_MC_CNTL)/sizeof(CP_CPC_MC_CNTL[0]), 0, 0 },
+	{ "mmCP_CPC_GRBM_FREE_COUNT", REG_MMIO, 0x208b, &CP_CPC_GRBM_FREE_COUNT[0], sizeof(CP_CPC_GRBM_FREE_COUNT)/sizeof(CP_CPC_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_MEC_CNTL", REG_MMIO, 0x208d, &CP_MEC_CNTL[0], sizeof(CP_MEC_CNTL)/sizeof(CP_MEC_CNTL[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_HEADER_DUMP", REG_MMIO, 0x208e, &CP_MEC_ME1_HEADER_DUMP[0], sizeof(CP_MEC_ME1_HEADER_DUMP)/sizeof(CP_MEC_ME1_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_HEADER_DUMP", REG_MMIO, 0x208f, &CP_MEC_ME2_HEADER_DUMP[0], sizeof(CP_MEC_ME2_HEADER_DUMP)/sizeof(CP_MEC_ME2_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_CPC_SCRATCH_INDEX", REG_MMIO, 0x2090, &CP_CPC_SCRATCH_INDEX[0], sizeof(CP_CPC_SCRATCH_INDEX)/sizeof(CP_CPC_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_CPC_SCRATCH_DATA", REG_MMIO, 0x2091, &CP_CPC_SCRATCH_DATA[0], sizeof(CP_CPC_SCRATCH_DATA)/sizeof(CP_CPC_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_CPC_HALT_HYST_COUNT", REG_MMIO, 0x20a7, &CP_CPC_HALT_HYST_COUNT[0], sizeof(CP_CPC_HALT_HYST_COUNT)/sizeof(CP_CPC_HALT_HYST_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_COMPARE_COUNT", REG_MMIO, 0x20c0, &CP_CE_COMPARE_COUNT[0], sizeof(CP_CE_COMPARE_COUNT)/sizeof(CP_CE_COMPARE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_DE_COUNT", REG_MMIO, 0x20c1, &CP_CE_DE_COUNT[0], sizeof(CP_CE_DE_COUNT)/sizeof(CP_CE_DE_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_CE_COUNT", REG_MMIO, 0x20c2, &CP_DE_CE_COUNT[0], sizeof(CP_DE_CE_COUNT)/sizeof(CP_DE_CE_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_LAST_INVAL_COUNT", REG_MMIO, 0x20c3, &CP_DE_LAST_INVAL_COUNT[0], sizeof(CP_DE_LAST_INVAL_COUNT)/sizeof(CP_DE_LAST_INVAL_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_DE_COUNT", REG_MMIO, 0x20c4, &CP_DE_DE_COUNT[0], sizeof(CP_DE_DE_COUNT)/sizeof(CP_DE_DE_COUNT[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT3", REG_MMIO, 0x219c, &CP_STALLED_STAT3[0], sizeof(CP_STALLED_STAT3)/sizeof(CP_STALLED_STAT3[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT1", REG_MMIO, 0x219d, &CP_STALLED_STAT1[0], sizeof(CP_STALLED_STAT1)/sizeof(CP_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT2", REG_MMIO, 0x219e, &CP_STALLED_STAT2[0], sizeof(CP_STALLED_STAT2)/sizeof(CP_STALLED_STAT2[0]), 0, 0 },
+	{ "mmCP_BUSY_STAT", REG_MMIO, 0x219f, &CP_BUSY_STAT[0], sizeof(CP_BUSY_STAT)/sizeof(CP_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_STAT", REG_MMIO, 0x21a0, &CP_STAT[0], sizeof(CP_STAT)/sizeof(CP_STAT[0]), 0, 0 },
+	{ "mmCP_ME_HEADER_DUMP", REG_MMIO, 0x21a1, &CP_ME_HEADER_DUMP[0], sizeof(CP_ME_HEADER_DUMP)/sizeof(CP_ME_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_PFP_HEADER_DUMP", REG_MMIO, 0x21a2, &CP_PFP_HEADER_DUMP[0], sizeof(CP_PFP_HEADER_DUMP)/sizeof(CP_PFP_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_GRBM_FREE_COUNT", REG_MMIO, 0x21a3, &CP_GRBM_FREE_COUNT[0], sizeof(CP_GRBM_FREE_COUNT)/sizeof(CP_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_HEADER_DUMP", REG_MMIO, 0x21a4, &CP_CE_HEADER_DUMP[0], sizeof(CP_CE_HEADER_DUMP)/sizeof(CP_CE_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_MC_PACK_DELAY_CNT", REG_MMIO, 0x21a7, &CP_MC_PACK_DELAY_CNT[0], sizeof(CP_MC_PACK_DELAY_CNT)/sizeof(CP_MC_PACK_DELAY_CNT[0]), 0, 0 },
+	{ "mmCP_MC_TAG_CNTL", REG_MMIO, 0x21a8, &CP_MC_TAG_CNTL[0], sizeof(CP_MC_TAG_CNTL)/sizeof(CP_MC_TAG_CNTL[0]), 0, 0 },
+	{ "mmCP_MC_TAG_DATA", REG_MMIO, 0x21a9, &CP_MC_TAG_DATA[0], sizeof(CP_MC_TAG_DATA)/sizeof(CP_MC_TAG_DATA[0]), 0, 0 },
+	{ "mmCP_CSF_STAT", REG_MMIO, 0x21b4, &CP_CSF_STAT[0], sizeof(CP_CSF_STAT)/sizeof(CP_CSF_STAT[0]), 0, 0 },
+	{ "mmCP_CSF_CNTL", REG_MMIO, 0x21b5, &CP_CSF_CNTL[0], sizeof(CP_CSF_CNTL)/sizeof(CP_CSF_CNTL[0]), 0, 0 },
+	{ "mmCP_ME_CNTL", REG_MMIO, 0x21b6, &CP_ME_CNTL[0], sizeof(CP_ME_CNTL)/sizeof(CP_ME_CNTL[0]), 0, 0 },
+	{ "mmCP_CNTX_STAT", REG_MMIO, 0x21b8, &CP_CNTX_STAT[0], sizeof(CP_CNTX_STAT)/sizeof(CP_CNTX_STAT[0]), 0, 0 },
+	{ "mmCP_ME_PREEMPTION", REG_MMIO, 0x21b9, &CP_ME_PREEMPTION[0], sizeof(CP_ME_PREEMPTION)/sizeof(CP_ME_PREEMPTION[0]), 0, 0 },
+	{ "mmCP_ROQ_THRESHOLDS", REG_MMIO, 0x21bc, &CP_ROQ_THRESHOLDS[0], sizeof(CP_ROQ_THRESHOLDS)/sizeof(CP_ROQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_STQ_THRESHOLD", REG_MMIO, 0x21bd, &CP_MEQ_STQ_THRESHOLD[0], sizeof(CP_MEQ_STQ_THRESHOLD)/sizeof(CP_MEQ_STQ_THRESHOLD[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR", REG_MMIO, 0x21be, &CP_RB2_RPTR[0], sizeof(CP_RB2_RPTR)/sizeof(CP_RB2_RPTR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR", REG_MMIO, 0x21bf, &CP_RB1_RPTR[0], sizeof(CP_RB1_RPTR)/sizeof(CP_RB1_RPTR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR", REG_MMIO, 0x21c0, &CP_RB0_RPTR[0], sizeof(CP_RB0_RPTR)/sizeof(CP_RB0_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_RPTR", REG_MMIO, 0x21c0, &CP_RB_RPTR[0], sizeof(CP_RB_RPTR)/sizeof(CP_RB_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_DELAY", REG_MMIO, 0x21c1, &CP_RB_WPTR_DELAY[0], sizeof(CP_RB_WPTR_DELAY)/sizeof(CP_RB_WPTR_DELAY[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_CNTL", REG_MMIO, 0x21c2, &CP_RB_WPTR_POLL_CNTL[0], sizeof(CP_RB_WPTR_POLL_CNTL)/sizeof(CP_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_ROQ1_THRESHOLDS", REG_MMIO, 0x21d5, &CP_ROQ1_THRESHOLDS[0], sizeof(CP_ROQ1_THRESHOLDS)/sizeof(CP_ROQ1_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ2_THRESHOLDS", REG_MMIO, 0x21d6, &CP_ROQ2_THRESHOLDS[0], sizeof(CP_ROQ2_THRESHOLDS)/sizeof(CP_ROQ2_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_STQ_THRESHOLDS", REG_MMIO, 0x21d7, &CP_STQ_THRESHOLDS[0], sizeof(CP_STQ_THRESHOLDS)/sizeof(CP_STQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_QUEUE_THRESHOLDS", REG_MMIO, 0x21d8, &CP_QUEUE_THRESHOLDS[0], sizeof(CP_QUEUE_THRESHOLDS)/sizeof(CP_QUEUE_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_THRESHOLDS", REG_MMIO, 0x21d9, &CP_MEQ_THRESHOLDS[0], sizeof(CP_MEQ_THRESHOLDS)/sizeof(CP_MEQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ_AVAIL", REG_MMIO, 0x21da, &CP_ROQ_AVAIL[0], sizeof(CP_ROQ_AVAIL)/sizeof(CP_ROQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_STQ_AVAIL", REG_MMIO, 0x21db, &CP_STQ_AVAIL[0], sizeof(CP_STQ_AVAIL)/sizeof(CP_STQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_ROQ2_AVAIL", REG_MMIO, 0x21dc, &CP_ROQ2_AVAIL[0], sizeof(CP_ROQ2_AVAIL)/sizeof(CP_ROQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_MEQ_AVAIL", REG_MMIO, 0x21dd, &CP_MEQ_AVAIL[0], sizeof(CP_MEQ_AVAIL)/sizeof(CP_MEQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_CMD_INDEX", REG_MMIO, 0x21de, &CP_CMD_INDEX[0], sizeof(CP_CMD_INDEX)/sizeof(CP_CMD_INDEX[0]), 0, 0 },
+	{ "mmCP_CMD_DATA", REG_MMIO, 0x21df, &CP_CMD_DATA[0], sizeof(CP_CMD_DATA)/sizeof(CP_CMD_DATA[0]), 0, 0 },
+	{ "mmCP_ROQ_RB_STAT", REG_MMIO, 0x21e0, &CP_ROQ_RB_STAT[0], sizeof(CP_ROQ_RB_STAT)/sizeof(CP_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB1_STAT", REG_MMIO, 0x21e1, &CP_ROQ_IB1_STAT[0], sizeof(CP_ROQ_IB1_STAT)/sizeof(CP_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB2_STAT", REG_MMIO, 0x21e2, &CP_ROQ_IB2_STAT[0], sizeof(CP_ROQ_IB2_STAT)/sizeof(CP_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_STAT", REG_MMIO, 0x21e3, &CP_STQ_STAT[0], sizeof(CP_STQ_STAT)/sizeof(CP_STQ_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_WR_STAT", REG_MMIO, 0x21e4, &CP_STQ_WR_STAT[0], sizeof(CP_STQ_WR_STAT)/sizeof(CP_STQ_WR_STAT[0]), 0, 0 },
+	{ "mmCP_MEQ_STAT", REG_MMIO, 0x21e5, &CP_MEQ_STAT[0], sizeof(CP_MEQ_STAT)/sizeof(CP_MEQ_STAT[0]), 0, 0 },
+	{ "mmCP_CEQ1_AVAIL", REG_MMIO, 0x21e6, &CP_CEQ1_AVAIL[0], sizeof(CP_CEQ1_AVAIL)/sizeof(CP_CEQ1_AVAIL[0]), 0, 0 },
+	{ "mmCP_CEQ2_AVAIL", REG_MMIO, 0x21e7, &CP_CEQ2_AVAIL[0], sizeof(CP_CEQ2_AVAIL)/sizeof(CP_CEQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_RB_STAT", REG_MMIO, 0x21e8, &CP_CE_ROQ_RB_STAT[0], sizeof(CP_CE_ROQ_RB_STAT)/sizeof(CP_CE_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB1_STAT", REG_MMIO, 0x21e9, &CP_CE_ROQ_IB1_STAT[0], sizeof(CP_CE_ROQ_IB1_STAT)/sizeof(CP_CE_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB2_STAT", REG_MMIO, 0x21ea, &CP_CE_ROQ_IB2_STAT[0], sizeof(CP_CE_ROQ_IB2_STAT)/sizeof(CP_CE_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_INT_STAT_DEBUG", REG_MMIO, 0x21f7, &CP_INT_STAT_DEBUG[0], sizeof(CP_INT_STAT_DEBUG)/sizeof(CP_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmVGT_VTX_VECT_EJECT_REG", REG_MMIO, 0x222c, &VGT_VTX_VECT_EJECT_REG[0], sizeof(VGT_VTX_VECT_EJECT_REG)/sizeof(VGT_VTX_VECT_EJECT_REG[0]), 0, 0 },
+	{ "mmVGT_DMA_DATA_FIFO_DEPTH", REG_MMIO, 0x222d, &VGT_DMA_DATA_FIFO_DEPTH[0], sizeof(VGT_DMA_DATA_FIFO_DEPTH)/sizeof(VGT_DMA_DATA_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DMA_REQ_FIFO_DEPTH", REG_MMIO, 0x222e, &VGT_DMA_REQ_FIFO_DEPTH[0], sizeof(VGT_DMA_REQ_FIFO_DEPTH)/sizeof(VGT_DMA_REQ_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DRAW_INIT_FIFO_DEPTH", REG_MMIO, 0x222f, &VGT_DRAW_INIT_FIFO_DEPTH[0], sizeof(VGT_DRAW_INIT_FIFO_DEPTH)/sizeof(VGT_DRAW_INIT_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_LAST_COPY_STATE", REG_MMIO, 0x2230, &VGT_LAST_COPY_STATE[0], sizeof(VGT_LAST_COPY_STATE)/sizeof(VGT_LAST_COPY_STATE[0]), 0, 0 },
+	{ "mmVGT_CACHE_INVALIDATION", REG_MMIO, 0x2231, &VGT_CACHE_INVALIDATION[0], sizeof(VGT_CACHE_INVALIDATION)/sizeof(VGT_CACHE_INVALIDATION[0]), 0, 0 },
+	{ "mmVGT_RESET_DEBUG", REG_MMIO, 0x2232, &VGT_RESET_DEBUG[0], sizeof(VGT_RESET_DEBUG)/sizeof(VGT_RESET_DEBUG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DELAY", REG_MMIO, 0x2233, &VGT_STRMOUT_DELAY[0], sizeof(VGT_STRMOUT_DELAY)/sizeof(VGT_STRMOUT_DELAY[0]), 0, 0 },
+	{ "mmVGT_FIFO_DEPTHS", REG_MMIO, 0x2234, &VGT_FIFO_DEPTHS[0], sizeof(VGT_FIFO_DEPTHS)/sizeof(VGT_FIFO_DEPTHS[0]), 0, 0 },
+	{ "mmVGT_GS_VERTEX_REUSE", REG_MMIO, 0x2235, &VGT_GS_VERTEX_REUSE[0], sizeof(VGT_GS_VERTEX_REUSE)/sizeof(VGT_GS_VERTEX_REUSE[0]), 0, 0 },
+	{ "mmVGT_MC_LAT_CNTL", REG_MMIO, 0x2236, &VGT_MC_LAT_CNTL[0], sizeof(VGT_MC_LAT_CNTL)/sizeof(VGT_MC_LAT_CNTL[0]), 0, 0 },
+	{ "mmIA_CNTL_STATUS", REG_MMIO, 0x2237, &IA_CNTL_STATUS[0], sizeof(IA_CNTL_STATUS)/sizeof(IA_CNTL_STATUS[0]), 0, 0 },
+	{ "mmVGT_DEBUG_CNTL", REG_MMIO, 0x2238, &VGT_DEBUG_CNTL[0], sizeof(VGT_DEBUG_CNTL)/sizeof(VGT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmVGT_DEBUG_DATA", REG_MMIO, 0x2239, &VGT_DEBUG_DATA[0], sizeof(VGT_DEBUG_DATA)/sizeof(VGT_DEBUG_DATA[0]), 0, 0 },
+	{ "mmIA_DEBUG_CNTL", REG_MMIO, 0x223a, &IA_DEBUG_CNTL[0], sizeof(IA_DEBUG_CNTL)/sizeof(IA_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmIA_DEBUG_DATA", REG_MMIO, 0x223b, &IA_DEBUG_DATA[0], sizeof(IA_DEBUG_DATA)/sizeof(IA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGT_CNTL_STATUS", REG_MMIO, 0x223c, &VGT_CNTL_STATUS[0], sizeof(VGT_CNTL_STATUS)/sizeof(VGT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmWD_DEBUG_CNTL", REG_MMIO, 0x223d, &WD_DEBUG_CNTL[0], sizeof(WD_DEBUG_CNTL)/sizeof(WD_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmWD_DEBUG_DATA", REG_MMIO, 0x223e, &WD_DEBUG_DATA[0], sizeof(WD_DEBUG_DATA)/sizeof(WD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmWD_CNTL_STATUS", REG_MMIO, 0x223f, &WD_CNTL_STATUS[0], sizeof(WD_CNTL_STATUS)/sizeof(WD_CNTL_STATUS[0]), 0, 0 },
+	{ "mmCC_GC_PRIM_CONFIG", REG_MMIO, 0x2240, &CC_GC_PRIM_CONFIG[0], sizeof(CC_GC_PRIM_CONFIG)/sizeof(CC_GC_PRIM_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_PRIM_CONFIG", REG_MMIO, 0x2241, &GC_USER_PRIM_CONFIG[0], sizeof(GC_USER_PRIM_CONFIG)/sizeof(GC_USER_PRIM_CONFIG[0]), 0, 0 },
+	{ "mmIA_VMID_OVERRIDE", REG_MMIO, 0x2260, &IA_VMID_OVERRIDE[0], sizeof(IA_VMID_OVERRIDE)/sizeof(IA_VMID_OVERRIDE[0]), 0, 0 },
+	{ "mmVGT_SYS_CONFIG", REG_MMIO, 0x2263, &VGT_SYS_CONFIG[0], sizeof(VGT_SYS_CONFIG)/sizeof(VGT_SYS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_VS_MAX_WAVE_ID", REG_MMIO, 0x2268, &VGT_VS_MAX_WAVE_ID[0], sizeof(VGT_VS_MAX_WAVE_ID)/sizeof(VGT_VS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmGFX_PIPE_CONTROL", REG_MMIO, 0x226d, &GFX_PIPE_CONTROL[0], sizeof(GFX_PIPE_CONTROL)/sizeof(GFX_PIPE_CONTROL[0]), 0, 0 },
+	{ "mmCC_GC_SHADER_ARRAY_CONFIG", REG_MMIO, 0x226f, &CC_GC_SHADER_ARRAY_CONFIG[0], sizeof(CC_GC_SHADER_ARRAY_CONFIG)/sizeof(CC_GC_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_SHADER_ARRAY_CONFIG", REG_MMIO, 0x2270, &GC_USER_SHADER_ARRAY_CONFIG[0], sizeof(GC_USER_SHADER_ARRAY_CONFIG)/sizeof(GC_USER_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmVGT_DMA_PRIMITIVE_TYPE", REG_MMIO, 0x2271, &VGT_DMA_PRIMITIVE_TYPE[0], sizeof(VGT_DMA_PRIMITIVE_TYPE)/sizeof(VGT_DMA_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_DMA_CONTROL", REG_MMIO, 0x2272, &VGT_DMA_CONTROL[0], sizeof(VGT_DMA_CONTROL)/sizeof(VGT_DMA_CONTROL[0]), 0, 0 },
+	{ "mmVGT_DMA_LS_HS_CONFIG", REG_MMIO, 0x2273, &VGT_DMA_LS_HS_CONFIG[0], sizeof(VGT_DMA_LS_HS_CONFIG)/sizeof(VGT_DMA_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_CNTL", REG_MMIO, 0x2280, &PA_SU_DEBUG_CNTL[0], sizeof(PA_SU_DEBUG_CNTL)/sizeof(PA_SU_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_DATA", REG_MMIO, 0x2281, &PA_SU_DEBUG_DATA[0], sizeof(PA_SU_DEBUG_DATA)/sizeof(PA_SU_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_CL_CNTL_STATUS", REG_MMIO, 0x2284, &PA_CL_CNTL_STATUS[0], sizeof(PA_CL_CNTL_STATUS)/sizeof(PA_CL_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_CL_ENHANCE", REG_MMIO, 0x2285, &PA_CL_ENHANCE[0], sizeof(PA_CL_ENHANCE)/sizeof(PA_CL_ENHANCE[0]), 0, 0 },
+	{ "mmPA_CL_RESET_DEBUG", REG_MMIO, 0x2286, &PA_CL_RESET_DEBUG[0], sizeof(PA_CL_RESET_DEBUG)/sizeof(PA_CL_RESET_DEBUG[0]), 0, 0 },
+	{ "mmPA_SU_CNTL_STATUS", REG_MMIO, 0x2294, &PA_SU_CNTL_STATUS[0], sizeof(PA_SU_CNTL_STATUS)/sizeof(PA_SU_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_DEPTH_CNTL", REG_MMIO, 0x2295, &PA_SC_FIFO_DEPTH_CNTL[0], sizeof(PA_SC_FIFO_DEPTH_CNTL)/sizeof(PA_SC_FIFO_DEPTH_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c0, &PA_SC_P3D_TRAP_SCREEN_HV_LOCK[0], sizeof(PA_SC_P3D_TRAP_SCREEN_HV_LOCK)/sizeof(PA_SC_P3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c1, &PA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0], sizeof(PA_SC_HP3D_TRAP_SCREEN_HV_LOCK)/sizeof(PA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c2, &PA_SC_TRAP_SCREEN_HV_LOCK[0], sizeof(PA_SC_TRAP_SCREEN_HV_LOCK)/sizeof(PA_SC_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_FORCE_EOV_MAX_CNTS", REG_MMIO, 0x22c9, &PA_SC_FORCE_EOV_MAX_CNTS[0], sizeof(PA_SC_FORCE_EOV_MAX_CNTS)/sizeof(PA_SC_FORCE_EOV_MAX_CNTS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_SIZE", REG_MMIO, 0x22f3, &PA_SC_FIFO_SIZE[0], sizeof(PA_SC_FIFO_SIZE)/sizeof(PA_SC_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_IF_FIFO_SIZE", REG_MMIO, 0x22f5, &PA_SC_IF_FIFO_SIZE[0], sizeof(PA_SC_IF_FIFO_SIZE)/sizeof(PA_SC_IF_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_CNTL", REG_MMIO, 0x22f6, &PA_SC_DEBUG_CNTL[0], sizeof(PA_SC_DEBUG_CNTL)/sizeof(PA_SC_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_DATA", REG_MMIO, 0x22f7, &PA_SC_DEBUG_DATA[0], sizeof(PA_SC_DEBUG_DATA)/sizeof(PA_SC_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_SC_ENHANCE", REG_MMIO, 0x22fc, &PA_SC_ENHANCE[0], sizeof(PA_SC_ENHANCE)/sizeof(PA_SC_ENHANCE[0]), 0, 0 },
+	{ "mmSQ_CONFIG", REG_MMIO, 0x2300, &SQ_CONFIG[0], sizeof(SQ_CONFIG)/sizeof(SQ_CONFIG[0]), 0, 0 },
+	{ "mmSQC_CONFIG", REG_MMIO, 0x2301, &SQC_CONFIG[0], sizeof(SQC_CONFIG)/sizeof(SQC_CONFIG[0]), 0, 0 },
+	{ "mmSQ_RANDOM_WAVE_PRI", REG_MMIO, 0x2303, &SQ_RANDOM_WAVE_PRI[0], sizeof(SQ_RANDOM_WAVE_PRI)/sizeof(SQ_RANDOM_WAVE_PRI[0]), 0, 0 },
+	{ "mmSQ_REG_CREDITS", REG_MMIO, 0x2304, &SQ_REG_CREDITS[0], sizeof(SQ_REG_CREDITS)/sizeof(SQ_REG_CREDITS[0]), 0, 0 },
+	{ "mmSQ_FIFO_SIZES", REG_MMIO, 0x2305, &SQ_FIFO_SIZES[0], sizeof(SQ_FIFO_SIZES)/sizeof(SQ_FIFO_SIZES[0]), 0, 0 },
+	{ "mmCC_SQC_BANK_DISABLE", REG_MMIO, 0x2307, &CC_SQC_BANK_DISABLE[0], sizeof(CC_SQC_BANK_DISABLE)/sizeof(CC_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmUSER_SQC_BANK_DISABLE", REG_MMIO, 0x2308, &USER_SQC_BANK_DISABLE[0], sizeof(USER_SQC_BANK_DISABLE)/sizeof(USER_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL", REG_MMIO, 0x2309, &SQ_DEBUG_STS_GLOBAL[0], sizeof(SQ_DEBUG_STS_GLOBAL)/sizeof(SQ_DEBUG_STS_GLOBAL[0]), 0, 0 },
+	{ "mmSH_MEM_BASES", REG_MMIO, 0x230a, &SH_MEM_BASES[0], sizeof(SH_MEM_BASES)/sizeof(SH_MEM_BASES[0]), 0, 0 },
+	{ "mmSH_MEM_APE1_BASE", REG_MMIO, 0x230b, &SH_MEM_APE1_BASE[0], sizeof(SH_MEM_APE1_BASE)/sizeof(SH_MEM_APE1_BASE[0]), 0, 0 },
+	{ "mmSH_MEM_APE1_LIMIT", REG_MMIO, 0x230c, &SH_MEM_APE1_LIMIT[0], sizeof(SH_MEM_APE1_LIMIT)/sizeof(SH_MEM_APE1_LIMIT[0]), 0, 0 },
+	{ "mmSH_MEM_CONFIG", REG_MMIO, 0x230d, &SH_MEM_CONFIG[0], sizeof(SH_MEM_CONFIG)/sizeof(SH_MEM_CONFIG[0]), 0, 0 },
+	{ "mmSQC_POLICY", REG_MMIO, 0x230e, &SQC_POLICY[0], sizeof(SQC_POLICY)/sizeof(SQC_POLICY[0]), 0, 0 },
+	{ "mmSQC_VOLATILE", REG_MMIO, 0x230f, &SQC_VOLATILE[0], sizeof(SQC_VOLATILE)/sizeof(SQC_VOLATILE[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL2", REG_MMIO, 0x2310, &SQ_DEBUG_STS_GLOBAL2[0], sizeof(SQ_DEBUG_STS_GLOBAL2)/sizeof(SQ_DEBUG_STS_GLOBAL2[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL3", REG_MMIO, 0x2311, &SQ_DEBUG_STS_GLOBAL3[0], sizeof(SQ_DEBUG_STS_GLOBAL3)/sizeof(SQ_DEBUG_STS_GLOBAL3[0]), 0, 0 },
+	{ "mmSQ_INTERRUPT_AUTO_MASK", REG_MMIO, 0x2314, &SQ_INTERRUPT_AUTO_MASK[0], sizeof(SQ_INTERRUPT_AUTO_MASK)/sizeof(SQ_INTERRUPT_AUTO_MASK[0]), 0, 0 },
+	{ "mmSQ_INTERRUPT_MSG_CTRL", REG_MMIO, 0x2315, &SQ_INTERRUPT_MSG_CTRL[0], sizeof(SQ_INTERRUPT_MSG_CTRL)/sizeof(SQ_INTERRUPT_MSG_CTRL[0]), 0, 0 },
+	{ "mmSQ_REG_TIMESTAMP", REG_MMIO, 0x2374, &SQ_REG_TIMESTAMP[0], sizeof(SQ_REG_TIMESTAMP)/sizeof(SQ_REG_TIMESTAMP[0]), 0, 0 },
+	{ "mmSQ_CMD_TIMESTAMP", REG_MMIO, 0x2375, &SQ_CMD_TIMESTAMP[0], sizeof(SQ_CMD_TIMESTAMP)/sizeof(SQ_CMD_TIMESTAMP[0]), 0, 0 },
+	{ "mmSQ_IND_INDEX", REG_MMIO, 0x2378, &SQ_IND_INDEX[0], sizeof(SQ_IND_INDEX)/sizeof(SQ_IND_INDEX[0]), 0, 0 },
+	{ "mmSQ_IND_DATA", REG_MMIO, 0x2379, &SQ_IND_DATA[0], sizeof(SQ_IND_DATA)/sizeof(SQ_IND_DATA[0]), 0, 0 },
+	{ "mmSQ_IND_CMD", REG_MMIO, 0x237a, NULL, 0, 0, 0 },
+	{ "mmSQ_CMD", REG_MMIO, 0x237b, &SQ_CMD[0], sizeof(SQ_CMD)/sizeof(SQ_CMD[0]), 0, 0 },
+	{ "mmSQ_TIME_HI", REG_MMIO, 0x237c, &SQ_TIME_HI[0], sizeof(SQ_TIME_HI)/sizeof(SQ_TIME_HI[0]), 0, 0 },
+	{ "mmSQ_TIME_LO", REG_MMIO, 0x237d, &SQ_TIME_LO[0], sizeof(SQ_TIME_LO)/sizeof(SQ_TIME_LO[0]), 0, 0 },
+	{ "mmSQ_VOP3_0_SDST_ENC", REG_MMIO, 0x237f, &SQ_VOP3_0_SDST_ENC[0], sizeof(SQ_VOP3_0_SDST_ENC)/sizeof(SQ_VOP3_0_SDST_ENC[0]), 0, 0 },
+	{ "mmSQ_MTBUF_1", REG_MMIO, 0x237f, &SQ_MTBUF_1[0], sizeof(SQ_MTBUF_1)/sizeof(SQ_MTBUF_1[0]), 0, 0 },
+	{ "mmSQ_VOP3_0", REG_MMIO, 0x237f, &SQ_VOP3_0[0], sizeof(SQ_VOP3_0)/sizeof(SQ_VOP3_0[0]), 0, 0 },
+	{ "mmSQ_EXP_1", REG_MMIO, 0x237f, &SQ_EXP_1[0], sizeof(SQ_EXP_1)/sizeof(SQ_EXP_1[0]), 0, 0 },
+	{ "mmSQ_SOP2", REG_MMIO, 0x237f, &SQ_SOP2[0], sizeof(SQ_SOP2)/sizeof(SQ_SOP2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE", REG_MMIO, 0x2380, &SQ_THREAD_TRACE_BASE[0], sizeof(SQ_THREAD_TRACE_BASE)/sizeof(SQ_THREAD_TRACE_BASE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_SIZE", REG_MMIO, 0x2381, &SQ_THREAD_TRACE_SIZE[0], sizeof(SQ_THREAD_TRACE_SIZE)/sizeof(SQ_THREAD_TRACE_SIZE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MASK", REG_MMIO, 0x2382, &SQ_THREAD_TRACE_MASK[0], sizeof(SQ_THREAD_TRACE_MASK)/sizeof(SQ_THREAD_TRACE_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK", REG_MMIO, 0x2383, &SQ_THREAD_TRACE_TOKEN_MASK[0], sizeof(SQ_THREAD_TRACE_TOKEN_MASK)/sizeof(SQ_THREAD_TRACE_TOKEN_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_PERF_MASK", REG_MMIO, 0x2384, &SQ_THREAD_TRACE_PERF_MASK[0], sizeof(SQ_THREAD_TRACE_PERF_MASK)/sizeof(SQ_THREAD_TRACE_PERF_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE2", REG_MMIO, 0x2385, &SQ_THREAD_TRACE_BASE2[0], sizeof(SQ_THREAD_TRACE_BASE2)/sizeof(SQ_THREAD_TRACE_BASE2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK2", REG_MMIO, 0x2386, &SQ_THREAD_TRACE_TOKEN_MASK2[0], sizeof(SQ_THREAD_TRACE_TOKEN_MASK2)/sizeof(SQ_THREAD_TRACE_TOKEN_MASK2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WPTR", REG_MMIO, 0x238c, &SQ_THREAD_TRACE_WPTR[0], sizeof(SQ_THREAD_TRACE_WPTR)/sizeof(SQ_THREAD_TRACE_WPTR[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_STATUS", REG_MMIO, 0x238d, &SQ_THREAD_TRACE_STATUS[0], sizeof(SQ_THREAD_TRACE_STATUS)/sizeof(SQ_THREAD_TRACE_STATUS[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MODE", REG_MMIO, 0x238e, &SQ_THREAD_TRACE_MODE[0], sizeof(SQ_THREAD_TRACE_MODE)/sizeof(SQ_THREAD_TRACE_MODE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CTRL", REG_MMIO, 0x238f, &SQ_THREAD_TRACE_CTRL[0], sizeof(SQ_THREAD_TRACE_CTRL)/sizeof(SQ_THREAD_TRACE_CTRL[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CNTR", REG_MMIO, 0x2390, &SQ_THREAD_TRACE_CNTR[0], sizeof(SQ_THREAD_TRACE_CNTR)/sizeof(SQ_THREAD_TRACE_CNTR[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_HIWATER", REG_MMIO, 0x2392, &SQ_THREAD_TRACE_HIWATER[0], sizeof(SQ_THREAD_TRACE_HIWATER)/sizeof(SQ_THREAD_TRACE_HIWATER[0]), 0, 0 },
+	{ "mmSQ_LB_CTR_CTRL", REG_MMIO, 0x2398, &SQ_LB_CTR_CTRL[0], sizeof(SQ_LB_CTR_CTRL)/sizeof(SQ_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_CYCLES", REG_MMIO, 0x2399, &SQ_LB_DATA_ALU_CYCLES[0], sizeof(SQ_LB_DATA_ALU_CYCLES)/sizeof(SQ_LB_DATA_ALU_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_CYCLES", REG_MMIO, 0x239a, &SQ_LB_DATA_TEX_CYCLES[0], sizeof(SQ_LB_DATA_TEX_CYCLES)/sizeof(SQ_LB_DATA_TEX_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_STALLS", REG_MMIO, 0x239b, &SQ_LB_DATA_ALU_STALLS[0], sizeof(SQ_LB_DATA_ALU_STALLS)/sizeof(SQ_LB_DATA_ALU_STALLS[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_STALLS", REG_MMIO, 0x239c, &SQ_LB_DATA_TEX_STALLS[0], sizeof(SQ_LB_DATA_TEX_STALLS)/sizeof(SQ_LB_DATA_TEX_STALLS[0]), 0, 0 },
+	{ "mmSQC_SECDED_CNT", REG_MMIO, 0x23a0, &SQC_SECDED_CNT[0], sizeof(SQC_SECDED_CNT)/sizeof(SQC_SECDED_CNT[0]), 0, 0 },
+	{ "mmSQ_SEC_CNT", REG_MMIO, 0x23a1, &SQ_SEC_CNT[0], sizeof(SQ_SEC_CNT)/sizeof(SQ_SEC_CNT[0]), 0, 0 },
+	{ "mmSQ_DED_CNT", REG_MMIO, 0x23a2, &SQ_DED_CNT[0], sizeof(SQ_DED_CNT)/sizeof(SQ_DED_CNT[0]), 0, 0 },
+	{ "mmSQ_DED_INFO", REG_MMIO, 0x23a3, &SQ_DED_INFO[0], sizeof(SQ_DED_INFO)/sizeof(SQ_DED_INFO[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_PERF_1_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_PERF_1_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_PERF_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_WAVE_START", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_WAVE_START[0], sizeof(SQ_THREAD_TRACE_WORD_WAVE_START)/sizeof(SQ_THREAD_TRACE_WORD_WAVE_START[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_EVENT", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_EVENT[0], sizeof(SQ_THREAD_TRACE_WORD_EVENT)/sizeof(SQ_THREAD_TRACE_WORD_EVENT[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_INST[0], sizeof(SQ_THREAD_TRACE_WORD_INST)/sizeof(SQ_THREAD_TRACE_WORD_INST[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_CMN", REG_MMIO, 0x23b0, &SQ_THREAD_TRACE_WORD_CMN[0], sizeof(SQ_THREAD_TRACE_WORD_CMN)/sizeof(SQ_THREAD_TRACE_WORD_CMN[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2", REG_MMIO, 0x23b1, &SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2", REG_MMIO, 0x23b1, &SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2", REG_MMIO, 0x23b1, &SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2", REG_MMIO, 0x23b1, &SQ_THREAD_TRACE_WORD_PERF_2_OF_2[0], sizeof(SQ_THREAD_TRACE_WORD_PERF_2_OF_2)/sizeof(SQ_THREAD_TRACE_WORD_PERF_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD0", REG_MMIO, 0x23c0, &SQ_BUF_RSRC_WORD0[0], sizeof(SQ_BUF_RSRC_WORD0)/sizeof(SQ_BUF_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD1", REG_MMIO, 0x23c1, &SQ_BUF_RSRC_WORD1[0], sizeof(SQ_BUF_RSRC_WORD1)/sizeof(SQ_BUF_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD2", REG_MMIO, 0x23c2, &SQ_BUF_RSRC_WORD2[0], sizeof(SQ_BUF_RSRC_WORD2)/sizeof(SQ_BUF_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD3", REG_MMIO, 0x23c3, &SQ_BUF_RSRC_WORD3[0], sizeof(SQ_BUF_RSRC_WORD3)/sizeof(SQ_BUF_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD0", REG_MMIO, 0x23c4, &SQ_IMG_RSRC_WORD0[0], sizeof(SQ_IMG_RSRC_WORD0)/sizeof(SQ_IMG_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD1", REG_MMIO, 0x23c5, &SQ_IMG_RSRC_WORD1[0], sizeof(SQ_IMG_RSRC_WORD1)/sizeof(SQ_IMG_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD2", REG_MMIO, 0x23c6, &SQ_IMG_RSRC_WORD2[0], sizeof(SQ_IMG_RSRC_WORD2)/sizeof(SQ_IMG_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD3", REG_MMIO, 0x23c7, &SQ_IMG_RSRC_WORD3[0], sizeof(SQ_IMG_RSRC_WORD3)/sizeof(SQ_IMG_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD4", REG_MMIO, 0x23c8, &SQ_IMG_RSRC_WORD4[0], sizeof(SQ_IMG_RSRC_WORD4)/sizeof(SQ_IMG_RSRC_WORD4[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD5", REG_MMIO, 0x23c9, &SQ_IMG_RSRC_WORD5[0], sizeof(SQ_IMG_RSRC_WORD5)/sizeof(SQ_IMG_RSRC_WORD5[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD6", REG_MMIO, 0x23ca, &SQ_IMG_RSRC_WORD6[0], sizeof(SQ_IMG_RSRC_WORD6)/sizeof(SQ_IMG_RSRC_WORD6[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD7", REG_MMIO, 0x23cb, &SQ_IMG_RSRC_WORD7[0], sizeof(SQ_IMG_RSRC_WORD7)/sizeof(SQ_IMG_RSRC_WORD7[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD0", REG_MMIO, 0x23cc, &SQ_IMG_SAMP_WORD0[0], sizeof(SQ_IMG_SAMP_WORD0)/sizeof(SQ_IMG_SAMP_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD1", REG_MMIO, 0x23cd, &SQ_IMG_SAMP_WORD1[0], sizeof(SQ_IMG_SAMP_WORD1)/sizeof(SQ_IMG_SAMP_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD2", REG_MMIO, 0x23ce, &SQ_IMG_SAMP_WORD2[0], sizeof(SQ_IMG_SAMP_WORD2)/sizeof(SQ_IMG_SAMP_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD3", REG_MMIO, 0x23cf, &SQ_IMG_SAMP_WORD3[0], sizeof(SQ_IMG_SAMP_WORD3)/sizeof(SQ_IMG_SAMP_WORD3[0]), 0, 0 },
+	{ "mmSQ_FLAT_SCRATCH_WORD0", REG_MMIO, 0x23d0, &SQ_FLAT_SCRATCH_WORD0[0], sizeof(SQ_FLAT_SCRATCH_WORD0)/sizeof(SQ_FLAT_SCRATCH_WORD0[0]), 0, 0 },
+	{ "mmSQ_FLAT_SCRATCH_WORD1", REG_MMIO, 0x23d1, &SQ_FLAT_SCRATCH_WORD1[0], sizeof(SQ_FLAT_SCRATCH_WORD1)/sizeof(SQ_FLAT_SCRATCH_WORD1[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY", REG_MMIO, 0x2414, &SX_DEBUG_BUSY[0], sizeof(SX_DEBUG_BUSY)/sizeof(SX_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_2", REG_MMIO, 0x2415, &SX_DEBUG_BUSY_2[0], sizeof(SX_DEBUG_BUSY_2)/sizeof(SX_DEBUG_BUSY_2[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_3", REG_MMIO, 0x2416, &SX_DEBUG_BUSY_3[0], sizeof(SX_DEBUG_BUSY_3)/sizeof(SX_DEBUG_BUSY_3[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_4", REG_MMIO, 0x2417, &SX_DEBUG_BUSY_4[0], sizeof(SX_DEBUG_BUSY_4)/sizeof(SX_DEBUG_BUSY_4[0]), 0, 0 },
+	{ "mmSX_DEBUG_1", REG_MMIO, 0x2418, &SX_DEBUG_1[0], sizeof(SX_DEBUG_1)/sizeof(SX_DEBUG_1[0]), 0, 0 },
+	{ "mmSPI_PS_MAX_WAVE_ID", REG_MMIO, 0x243a, &SPI_PS_MAX_WAVE_ID[0], sizeof(SPI_PS_MAX_WAVE_ID)/sizeof(SPI_PS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL", REG_MMIO, 0x2440, &SPI_CONFIG_CNTL[0], sizeof(SPI_CONFIG_CNTL)/sizeof(SPI_CONFIG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_CNTL", REG_MMIO, 0x2441, &SPI_DEBUG_CNTL[0], sizeof(SPI_DEBUG_CNTL)/sizeof(SPI_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_READ", REG_MMIO, 0x2442, &SPI_DEBUG_READ[0], sizeof(SPI_DEBUG_READ)/sizeof(SPI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL_1", REG_MMIO, 0x244f, &SPI_CONFIG_CNTL_1[0], sizeof(SPI_CONFIG_CNTL_1)/sizeof(SPI_CONFIG_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_DEBUG_BUSY", REG_MMIO, 0x2450, &SPI_DEBUG_BUSY[0], sizeof(SPI_DEBUG_BUSY)/sizeof(SPI_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_CNTL", REG_MMIO, 0x24aa, &SPI_WF_LIFETIME_CNTL[0], sizeof(SPI_WF_LIFETIME_CNTL)/sizeof(SPI_WF_LIFETIME_CNTL[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_0", REG_MMIO, 0x24ab, &SPI_WF_LIFETIME_LIMIT_0[0], sizeof(SPI_WF_LIFETIME_LIMIT_0)/sizeof(SPI_WF_LIFETIME_LIMIT_0[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_1", REG_MMIO, 0x24ac, &SPI_WF_LIFETIME_LIMIT_1[0], sizeof(SPI_WF_LIFETIME_LIMIT_1)/sizeof(SPI_WF_LIFETIME_LIMIT_1[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_2", REG_MMIO, 0x24ad, &SPI_WF_LIFETIME_LIMIT_2[0], sizeof(SPI_WF_LIFETIME_LIMIT_2)/sizeof(SPI_WF_LIFETIME_LIMIT_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_3", REG_MMIO, 0x24ae, &SPI_WF_LIFETIME_LIMIT_3[0], sizeof(SPI_WF_LIFETIME_LIMIT_3)/sizeof(SPI_WF_LIFETIME_LIMIT_3[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_4", REG_MMIO, 0x24af, &SPI_WF_LIFETIME_LIMIT_4[0], sizeof(SPI_WF_LIFETIME_LIMIT_4)/sizeof(SPI_WF_LIFETIME_LIMIT_4[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_5", REG_MMIO, 0x24b0, &SPI_WF_LIFETIME_LIMIT_5[0], sizeof(SPI_WF_LIFETIME_LIMIT_5)/sizeof(SPI_WF_LIFETIME_LIMIT_5[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_6", REG_MMIO, 0x24b1, &SPI_WF_LIFETIME_LIMIT_6[0], sizeof(SPI_WF_LIFETIME_LIMIT_6)/sizeof(SPI_WF_LIFETIME_LIMIT_6[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_7", REG_MMIO, 0x24b2, &SPI_WF_LIFETIME_LIMIT_7[0], sizeof(SPI_WF_LIFETIME_LIMIT_7)/sizeof(SPI_WF_LIFETIME_LIMIT_7[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_8", REG_MMIO, 0x24b3, &SPI_WF_LIFETIME_LIMIT_8[0], sizeof(SPI_WF_LIFETIME_LIMIT_8)/sizeof(SPI_WF_LIFETIME_LIMIT_8[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_9", REG_MMIO, 0x24b4, &SPI_WF_LIFETIME_LIMIT_9[0], sizeof(SPI_WF_LIFETIME_LIMIT_9)/sizeof(SPI_WF_LIFETIME_LIMIT_9[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_0", REG_MMIO, 0x24b5, &SPI_WF_LIFETIME_STATUS_0[0], sizeof(SPI_WF_LIFETIME_STATUS_0)/sizeof(SPI_WF_LIFETIME_STATUS_0[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_1", REG_MMIO, 0x24b6, &SPI_WF_LIFETIME_STATUS_1[0], sizeof(SPI_WF_LIFETIME_STATUS_1)/sizeof(SPI_WF_LIFETIME_STATUS_1[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_2", REG_MMIO, 0x24b7, &SPI_WF_LIFETIME_STATUS_2[0], sizeof(SPI_WF_LIFETIME_STATUS_2)/sizeof(SPI_WF_LIFETIME_STATUS_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_3", REG_MMIO, 0x24b8, &SPI_WF_LIFETIME_STATUS_3[0], sizeof(SPI_WF_LIFETIME_STATUS_3)/sizeof(SPI_WF_LIFETIME_STATUS_3[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_4", REG_MMIO, 0x24b9, &SPI_WF_LIFETIME_STATUS_4[0], sizeof(SPI_WF_LIFETIME_STATUS_4)/sizeof(SPI_WF_LIFETIME_STATUS_4[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_5", REG_MMIO, 0x24ba, &SPI_WF_LIFETIME_STATUS_5[0], sizeof(SPI_WF_LIFETIME_STATUS_5)/sizeof(SPI_WF_LIFETIME_STATUS_5[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_6", REG_MMIO, 0x24bb, &SPI_WF_LIFETIME_STATUS_6[0], sizeof(SPI_WF_LIFETIME_STATUS_6)/sizeof(SPI_WF_LIFETIME_STATUS_6[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_7", REG_MMIO, 0x24bc, &SPI_WF_LIFETIME_STATUS_7[0], sizeof(SPI_WF_LIFETIME_STATUS_7)/sizeof(SPI_WF_LIFETIME_STATUS_7[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_8", REG_MMIO, 0x24bd, &SPI_WF_LIFETIME_STATUS_8[0], sizeof(SPI_WF_LIFETIME_STATUS_8)/sizeof(SPI_WF_LIFETIME_STATUS_8[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_9", REG_MMIO, 0x24be, &SPI_WF_LIFETIME_STATUS_9[0], sizeof(SPI_WF_LIFETIME_STATUS_9)/sizeof(SPI_WF_LIFETIME_STATUS_9[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_10", REG_MMIO, 0x24bf, &SPI_WF_LIFETIME_STATUS_10[0], sizeof(SPI_WF_LIFETIME_STATUS_10)/sizeof(SPI_WF_LIFETIME_STATUS_10[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_11", REG_MMIO, 0x24c0, &SPI_WF_LIFETIME_STATUS_11[0], sizeof(SPI_WF_LIFETIME_STATUS_11)/sizeof(SPI_WF_LIFETIME_STATUS_11[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_12", REG_MMIO, 0x24c1, &SPI_WF_LIFETIME_STATUS_12[0], sizeof(SPI_WF_LIFETIME_STATUS_12)/sizeof(SPI_WF_LIFETIME_STATUS_12[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_13", REG_MMIO, 0x24c2, &SPI_WF_LIFETIME_STATUS_13[0], sizeof(SPI_WF_LIFETIME_STATUS_13)/sizeof(SPI_WF_LIFETIME_STATUS_13[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_14", REG_MMIO, 0x24c3, &SPI_WF_LIFETIME_STATUS_14[0], sizeof(SPI_WF_LIFETIME_STATUS_14)/sizeof(SPI_WF_LIFETIME_STATUS_14[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_15", REG_MMIO, 0x24c4, &SPI_WF_LIFETIME_STATUS_15[0], sizeof(SPI_WF_LIFETIME_STATUS_15)/sizeof(SPI_WF_LIFETIME_STATUS_15[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_16", REG_MMIO, 0x24c5, &SPI_WF_LIFETIME_STATUS_16[0], sizeof(SPI_WF_LIFETIME_STATUS_16)/sizeof(SPI_WF_LIFETIME_STATUS_16[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_17", REG_MMIO, 0x24c6, &SPI_WF_LIFETIME_STATUS_17[0], sizeof(SPI_WF_LIFETIME_STATUS_17)/sizeof(SPI_WF_LIFETIME_STATUS_17[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_18", REG_MMIO, 0x24c7, &SPI_WF_LIFETIME_STATUS_18[0], sizeof(SPI_WF_LIFETIME_STATUS_18)/sizeof(SPI_WF_LIFETIME_STATUS_18[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_19", REG_MMIO, 0x24c8, &SPI_WF_LIFETIME_STATUS_19[0], sizeof(SPI_WF_LIFETIME_STATUS_19)/sizeof(SPI_WF_LIFETIME_STATUS_19[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_20", REG_MMIO, 0x24c9, &SPI_WF_LIFETIME_STATUS_20[0], sizeof(SPI_WF_LIFETIME_STATUS_20)/sizeof(SPI_WF_LIFETIME_STATUS_20[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_DEBUG", REG_MMIO, 0x24ca, &SPI_WF_LIFETIME_DEBUG[0], sizeof(SPI_WF_LIFETIME_DEBUG)/sizeof(SPI_WF_LIFETIME_DEBUG[0]), 0, 0 },
+	{ "mmSPI_SLAVE_DEBUG_BUSY", REG_MMIO, 0x24d3, &SPI_SLAVE_DEBUG_BUSY[0], sizeof(SPI_SLAVE_DEBUG_BUSY)/sizeof(SPI_SLAVE_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_LB_CTR_CTRL", REG_MMIO, 0x24d4, &SPI_LB_CTR_CTRL[0], sizeof(SPI_LB_CTR_CTRL)/sizeof(SPI_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSPI_LB_CU_MASK", REG_MMIO, 0x24d5, &SPI_LB_CU_MASK[0], sizeof(SPI_LB_CU_MASK)/sizeof(SPI_LB_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_LB_DATA_REG", REG_MMIO, 0x24d6, &SPI_LB_DATA_REG[0], sizeof(SPI_LB_DATA_REG)/sizeof(SPI_LB_DATA_REG[0]), 0, 0 },
+	{ "mmSPI_PG_ENABLE_STATIC_CU_MASK", REG_MMIO, 0x24d7, &SPI_PG_ENABLE_STATIC_CU_MASK[0], sizeof(SPI_PG_ENABLE_STATIC_CU_MASK)/sizeof(SPI_PG_ENABLE_STATIC_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_GDS_CREDITS", REG_MMIO, 0x24d8, &SPI_GDS_CREDITS[0], sizeof(SPI_GDS_CREDITS)/sizeof(SPI_GDS_CREDITS[0]), 0, 0 },
+	{ "mmSPI_SX_EXPORT_BUFFER_SIZES", REG_MMIO, 0x24d9, &SPI_SX_EXPORT_BUFFER_SIZES[0], sizeof(SPI_SX_EXPORT_BUFFER_SIZES)/sizeof(SPI_SX_EXPORT_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_SX_SCOREBOARD_BUFFER_SIZES", REG_MMIO, 0x24da, &SPI_SX_SCOREBOARD_BUFFER_SIZES[0], sizeof(SPI_SX_SCOREBOARD_BUFFER_SIZES)/sizeof(SPI_SX_SCOREBOARD_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_STATUS", REG_MMIO, 0x24db, &SPI_CSQ_WF_ACTIVE_STATUS[0], sizeof(SPI_CSQ_WF_ACTIVE_STATUS)/sizeof(SPI_CSQ_WF_ACTIVE_STATUS[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_0", REG_MMIO, 0x24dc, &SPI_CSQ_WF_ACTIVE_COUNT_0[0], sizeof(SPI_CSQ_WF_ACTIVE_COUNT_0)/sizeof(SPI_CSQ_WF_ACTIVE_COUNT_0[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_1", REG_MMIO, 0x24dd, &SPI_CSQ_WF_ACTIVE_COUNT_1[0], sizeof(SPI_CSQ_WF_ACTIVE_COUNT_1)/sizeof(SPI_CSQ_WF_ACTIVE_COUNT_1[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_2", REG_MMIO, 0x24de, &SPI_CSQ_WF_ACTIVE_COUNT_2[0], sizeof(SPI_CSQ_WF_ACTIVE_COUNT_2)/sizeof(SPI_CSQ_WF_ACTIVE_COUNT_2[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_3", REG_MMIO, 0x24df, &SPI_CSQ_WF_ACTIVE_COUNT_3[0], sizeof(SPI_CSQ_WF_ACTIVE_COUNT_3)/sizeof(SPI_CSQ_WF_ACTIVE_COUNT_3[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_4", REG_MMIO, 0x24e0, &SPI_CSQ_WF_ACTIVE_COUNT_4[0], sizeof(SPI_CSQ_WF_ACTIVE_COUNT_4)/sizeof(SPI_CSQ_WF_ACTIVE_COUNT_4[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_5", REG_MMIO, 0x24e1, &SPI_CSQ_WF_ACTIVE_COUNT_5[0], sizeof(SPI_CSQ_WF_ACTIVE_COUNT_5)/sizeof(SPI_CSQ_WF_ACTIVE_COUNT_5[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_6", REG_MMIO, 0x24e2, &SPI_CSQ_WF_ACTIVE_COUNT_6[0], sizeof(SPI_CSQ_WF_ACTIVE_COUNT_6)/sizeof(SPI_CSQ_WF_ACTIVE_COUNT_6[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_7", REG_MMIO, 0x24e3, &SPI_CSQ_WF_ACTIVE_COUNT_7[0], sizeof(SPI_CSQ_WF_ACTIVE_COUNT_7)/sizeof(SPI_CSQ_WF_ACTIVE_COUNT_7[0]), 0, 0 },
+	{ "mmBCI_DEBUG_READ", REG_MMIO, 0x24eb, &BCI_DEBUG_READ[0], sizeof(BCI_DEBUG_READ)/sizeof(BCI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24ec, &SPI_P0_TRAP_SCREEN_PSBA_LO[0], sizeof(SPI_P0_TRAP_SCREEN_PSBA_LO)/sizeof(SPI_P0_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24ed, &SPI_P0_TRAP_SCREEN_PSBA_HI[0], sizeof(SPI_P0_TRAP_SCREEN_PSBA_HI)/sizeof(SPI_P0_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24ee, &SPI_P0_TRAP_SCREEN_PSMA_LO[0], sizeof(SPI_P0_TRAP_SCREEN_PSMA_LO)/sizeof(SPI_P0_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24ef, &SPI_P0_TRAP_SCREEN_PSMA_HI[0], sizeof(SPI_P0_TRAP_SCREEN_PSMA_HI)/sizeof(SPI_P0_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f0, &SPI_P0_TRAP_SCREEN_GPR_MIN[0], sizeof(SPI_P0_TRAP_SCREEN_GPR_MIN)/sizeof(SPI_P0_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24f1, &SPI_P1_TRAP_SCREEN_PSBA_LO[0], sizeof(SPI_P1_TRAP_SCREEN_PSBA_LO)/sizeof(SPI_P1_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24f2, &SPI_P1_TRAP_SCREEN_PSBA_HI[0], sizeof(SPI_P1_TRAP_SCREEN_PSBA_HI)/sizeof(SPI_P1_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24f3, &SPI_P1_TRAP_SCREEN_PSMA_LO[0], sizeof(SPI_P1_TRAP_SCREEN_PSMA_LO)/sizeof(SPI_P1_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24f4, &SPI_P1_TRAP_SCREEN_PSMA_HI[0], sizeof(SPI_P1_TRAP_SCREEN_PSMA_HI)/sizeof(SPI_P1_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f5, &SPI_P1_TRAP_SCREEN_GPR_MIN[0], sizeof(SPI_P1_TRAP_SCREEN_GPR_MIN)/sizeof(SPI_P1_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
+	{ "mmTD_CNTL", REG_MMIO, 0x2525, &TD_CNTL[0], sizeof(TD_CNTL)/sizeof(TD_CNTL[0]), 0, 0 },
+	{ "mmTD_STATUS", REG_MMIO, 0x2526, &TD_STATUS[0], sizeof(TD_STATUS)/sizeof(TD_STATUS[0]), 0, 0 },
+	{ "mmTD_DEBUG_INDEX", REG_MMIO, 0x2528, &TD_DEBUG_INDEX[0], sizeof(TD_DEBUG_INDEX)/sizeof(TD_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTD_DEBUG_DATA", REG_MMIO, 0x2529, &TD_DEBUG_DATA[0], sizeof(TD_DEBUG_DATA)/sizeof(TD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTD_SCRATCH", REG_MMIO, 0x2533, &TD_SCRATCH[0], sizeof(TD_SCRATCH)/sizeof(TD_SCRATCH[0]), 0, 0 },
+	{ "mmTA_CNTL", REG_MMIO, 0x2541, &TA_CNTL[0], sizeof(TA_CNTL)/sizeof(TA_CNTL[0]), 0, 0 },
+	{ "mmTA_CNTL_AUX", REG_MMIO, 0x2542, &TA_CNTL_AUX[0], sizeof(TA_CNTL_AUX)/sizeof(TA_CNTL_AUX[0]), 0, 0 },
+	{ "mmTA_RESERVED_010C", REG_MMIO, 0x2543, &TA_RESERVED_010C[0], sizeof(TA_RESERVED_010C)/sizeof(TA_RESERVED_010C[0]), 0, 0 },
+	{ "mmTA_STATUS", REG_MMIO, 0x2548, &TA_STATUS[0], sizeof(TA_STATUS)/sizeof(TA_STATUS[0]), 0, 0 },
+	{ "mmTA_DEBUG_INDEX", REG_MMIO, 0x254c, &TA_DEBUG_INDEX[0], sizeof(TA_DEBUG_INDEX)/sizeof(TA_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTA_DEBUG_DATA", REG_MMIO, 0x254d, &TA_DEBUG_DATA[0], sizeof(TA_DEBUG_DATA)/sizeof(TA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTA_SCRATCH", REG_MMIO, 0x2564, &TA_SCRATCH[0], sizeof(TA_SCRATCH)/sizeof(TA_SCRATCH[0]), 0, 0 },
+	{ "mmSH_HIDDEN_PRIVATE_BASE_VMID", REG_MMIO, 0x2580, &SH_HIDDEN_PRIVATE_BASE_VMID[0], sizeof(SH_HIDDEN_PRIVATE_BASE_VMID)/sizeof(SH_HIDDEN_PRIVATE_BASE_VMID[0]), 0, 0 },
+	{ "mmSH_STATIC_MEM_CONFIG", REG_MMIO, 0x2581, &SH_STATIC_MEM_CONFIG[0], sizeof(SH_STATIC_MEM_CONFIG)/sizeof(SH_STATIC_MEM_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CONFIG", REG_MMIO, 0x25c0, &GDS_CONFIG[0], sizeof(GDS_CONFIG)/sizeof(GDS_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CNTL_STATUS", REG_MMIO, 0x25c1, &GDS_CNTL_STATUS[0], sizeof(GDS_CNTL_STATUS)/sizeof(GDS_CNTL_STATUS[0]), 0, 0 },
+	{ "mmGDS_ENHANCE", REG_MMIO, 0x25c2, &GDS_ENHANCE[0], sizeof(GDS_ENHANCE)/sizeof(GDS_ENHANCE[0]), 0, 0 },
+	{ "mmGDS_PROTECTION_FAULT", REG_MMIO, 0x25c3, &GDS_PROTECTION_FAULT[0], sizeof(GDS_PROTECTION_FAULT)/sizeof(GDS_PROTECTION_FAULT[0]), 0, 0 },
+	{ "mmGDS_VM_PROTECTION_FAULT", REG_MMIO, 0x25c4, &GDS_VM_PROTECTION_FAULT[0], sizeof(GDS_VM_PROTECTION_FAULT)/sizeof(GDS_VM_PROTECTION_FAULT[0]), 0, 0 },
+	{ "mmGDS_SECDED_CNT", REG_MMIO, 0x25c5, &GDS_SECDED_CNT[0], sizeof(GDS_SECDED_CNT)/sizeof(GDS_SECDED_CNT[0]), 0, 0 },
+	{ "mmGDS_GRBM_SECDED_CNT", REG_MMIO, 0x25c6, &GDS_GRBM_SECDED_CNT[0], sizeof(GDS_GRBM_SECDED_CNT)/sizeof(GDS_GRBM_SECDED_CNT[0]), 0, 0 },
+	{ "mmGDS_OA_DED", REG_MMIO, 0x25c7, &GDS_OA_DED[0], sizeof(GDS_OA_DED)/sizeof(GDS_OA_DED[0]), 0, 0 },
+	{ "mmGDS_DEBUG_CNTL", REG_MMIO, 0x25c8, &GDS_DEBUG_CNTL[0], sizeof(GDS_DEBUG_CNTL)/sizeof(GDS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGDS_DEBUG_DATA", REG_MMIO, 0x25c9, &GDS_DEBUG_DATA[0], sizeof(GDS_DEBUG_DATA)/sizeof(GDS_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDB_DEBUG", REG_MMIO, 0x260c, &DB_DEBUG[0], sizeof(DB_DEBUG)/sizeof(DB_DEBUG[0]), 0, 0 },
+	{ "mmDB_DEBUG2", REG_MMIO, 0x260d, &DB_DEBUG2[0], sizeof(DB_DEBUG2)/sizeof(DB_DEBUG2[0]), 0, 0 },
+	{ "mmDB_DEBUG3", REG_MMIO, 0x260e, &DB_DEBUG3[0], sizeof(DB_DEBUG3)/sizeof(DB_DEBUG3[0]), 0, 0 },
+	{ "mmDB_DEBUG4", REG_MMIO, 0x260f, &DB_DEBUG4[0], sizeof(DB_DEBUG4)/sizeof(DB_DEBUG4[0]), 0, 0 },
+	{ "mmDB_CREDIT_LIMIT", REG_MMIO, 0x2614, &DB_CREDIT_LIMIT[0], sizeof(DB_CREDIT_LIMIT)/sizeof(DB_CREDIT_LIMIT[0]), 0, 0 },
+	{ "mmDB_WATERMARKS", REG_MMIO, 0x2615, &DB_WATERMARKS[0], sizeof(DB_WATERMARKS)/sizeof(DB_WATERMARKS[0]), 0, 0 },
+	{ "mmDB_SUBTILE_CONTROL", REG_MMIO, 0x2616, &DB_SUBTILE_CONTROL[0], sizeof(DB_SUBTILE_CONTROL)/sizeof(DB_SUBTILE_CONTROL[0]), 0, 0 },
+	{ "mmDB_FREE_CACHELINES", REG_MMIO, 0x2617, &DB_FREE_CACHELINES[0], sizeof(DB_FREE_CACHELINES)/sizeof(DB_FREE_CACHELINES[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH1", REG_MMIO, 0x2618, &DB_FIFO_DEPTH1[0], sizeof(DB_FIFO_DEPTH1)/sizeof(DB_FIFO_DEPTH1[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH2", REG_MMIO, 0x2619, &DB_FIFO_DEPTH2[0], sizeof(DB_FIFO_DEPTH2)/sizeof(DB_FIFO_DEPTH2[0]), 0, 0 },
+	{ "mmDB_RING_CONTROL", REG_MMIO, 0x261b, &DB_RING_CONTROL[0], sizeof(DB_RING_CONTROL)/sizeof(DB_RING_CONTROL[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_0", REG_MMIO, 0x2620, &DB_READ_DEBUG_0[0], sizeof(DB_READ_DEBUG_0)/sizeof(DB_READ_DEBUG_0[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_1", REG_MMIO, 0x2621, &DB_READ_DEBUG_1[0], sizeof(DB_READ_DEBUG_1)/sizeof(DB_READ_DEBUG_1[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_2", REG_MMIO, 0x2622, &DB_READ_DEBUG_2[0], sizeof(DB_READ_DEBUG_2)/sizeof(DB_READ_DEBUG_2[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_3", REG_MMIO, 0x2623, &DB_READ_DEBUG_3[0], sizeof(DB_READ_DEBUG_3)/sizeof(DB_READ_DEBUG_3[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_4", REG_MMIO, 0x2624, &DB_READ_DEBUG_4[0], sizeof(DB_READ_DEBUG_4)/sizeof(DB_READ_DEBUG_4[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_5", REG_MMIO, 0x2625, &DB_READ_DEBUG_5[0], sizeof(DB_READ_DEBUG_5)/sizeof(DB_READ_DEBUG_5[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_6", REG_MMIO, 0x2626, &DB_READ_DEBUG_6[0], sizeof(DB_READ_DEBUG_6)/sizeof(DB_READ_DEBUG_6[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_7", REG_MMIO, 0x2627, &DB_READ_DEBUG_7[0], sizeof(DB_READ_DEBUG_7)/sizeof(DB_READ_DEBUG_7[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_8", REG_MMIO, 0x2628, &DB_READ_DEBUG_8[0], sizeof(DB_READ_DEBUG_8)/sizeof(DB_READ_DEBUG_8[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_9", REG_MMIO, 0x2629, &DB_READ_DEBUG_9[0], sizeof(DB_READ_DEBUG_9)/sizeof(DB_READ_DEBUG_9[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_A", REG_MMIO, 0x262a, &DB_READ_DEBUG_A[0], sizeof(DB_READ_DEBUG_A)/sizeof(DB_READ_DEBUG_A[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_B", REG_MMIO, 0x262b, &DB_READ_DEBUG_B[0], sizeof(DB_READ_DEBUG_B)/sizeof(DB_READ_DEBUG_B[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_C", REG_MMIO, 0x262c, &DB_READ_DEBUG_C[0], sizeof(DB_READ_DEBUG_C)/sizeof(DB_READ_DEBUG_C[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_D", REG_MMIO, 0x262d, &DB_READ_DEBUG_D[0], sizeof(DB_READ_DEBUG_D)/sizeof(DB_READ_DEBUG_D[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_E", REG_MMIO, 0x262e, &DB_READ_DEBUG_E[0], sizeof(DB_READ_DEBUG_E)/sizeof(DB_READ_DEBUG_E[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_F", REG_MMIO, 0x262f, &DB_READ_DEBUG_F[0], sizeof(DB_READ_DEBUG_F)/sizeof(DB_READ_DEBUG_F[0]), 0, 0 },
+	{ "mmCC_RB_REDUNDANCY", REG_MMIO, 0x263c, &CC_RB_REDUNDANCY[0], sizeof(CC_RB_REDUNDANCY)/sizeof(CC_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmCC_RB_BACKEND_DISABLE", REG_MMIO, 0x263d, &CC_RB_BACKEND_DISABLE[0], sizeof(CC_RB_BACKEND_DISABLE)/sizeof(CC_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmGB_ADDR_CONFIG", REG_MMIO, 0x263e, &GB_ADDR_CONFIG[0], sizeof(GB_ADDR_CONFIG)/sizeof(GB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmGB_BACKEND_MAP", REG_MMIO, 0x263f, &GB_BACKEND_MAP[0], sizeof(GB_BACKEND_MAP)/sizeof(GB_BACKEND_MAP[0]), 0, 0 },
+	{ "mmGB_GPU_ID", REG_MMIO, 0x2640, &GB_GPU_ID[0], sizeof(GB_GPU_ID)/sizeof(GB_GPU_ID[0]), 0, 0 },
+	{ "mmCC_RB_DAISY_CHAIN", REG_MMIO, 0x2641, &CC_RB_DAISY_CHAIN[0], sizeof(CC_RB_DAISY_CHAIN)/sizeof(CC_RB_DAISY_CHAIN[0]), 0, 0 },
+	{ "mmGB_TILE_MODE0", REG_MMIO, 0x2644, &GB_TILE_MODE0[0], sizeof(GB_TILE_MODE0)/sizeof(GB_TILE_MODE0[0]), 0, 0 },
+	{ "mmGB_TILE_MODE1", REG_MMIO, 0x2645, &GB_TILE_MODE1[0], sizeof(GB_TILE_MODE1)/sizeof(GB_TILE_MODE1[0]), 0, 0 },
+	{ "mmGB_TILE_MODE2", REG_MMIO, 0x2646, &GB_TILE_MODE2[0], sizeof(GB_TILE_MODE2)/sizeof(GB_TILE_MODE2[0]), 0, 0 },
+	{ "mmGB_TILE_MODE3", REG_MMIO, 0x2647, &GB_TILE_MODE3[0], sizeof(GB_TILE_MODE3)/sizeof(GB_TILE_MODE3[0]), 0, 0 },
+	{ "mmGB_TILE_MODE4", REG_MMIO, 0x2648, &GB_TILE_MODE4[0], sizeof(GB_TILE_MODE4)/sizeof(GB_TILE_MODE4[0]), 0, 0 },
+	{ "mmGB_TILE_MODE5", REG_MMIO, 0x2649, &GB_TILE_MODE5[0], sizeof(GB_TILE_MODE5)/sizeof(GB_TILE_MODE5[0]), 0, 0 },
+	{ "mmGB_TILE_MODE6", REG_MMIO, 0x264a, &GB_TILE_MODE6[0], sizeof(GB_TILE_MODE6)/sizeof(GB_TILE_MODE6[0]), 0, 0 },
+	{ "mmGB_TILE_MODE7", REG_MMIO, 0x264b, &GB_TILE_MODE7[0], sizeof(GB_TILE_MODE7)/sizeof(GB_TILE_MODE7[0]), 0, 0 },
+	{ "mmGB_TILE_MODE8", REG_MMIO, 0x264c, &GB_TILE_MODE8[0], sizeof(GB_TILE_MODE8)/sizeof(GB_TILE_MODE8[0]), 0, 0 },
+	{ "mmGB_TILE_MODE9", REG_MMIO, 0x264d, &GB_TILE_MODE9[0], sizeof(GB_TILE_MODE9)/sizeof(GB_TILE_MODE9[0]), 0, 0 },
+	{ "mmGB_TILE_MODE10", REG_MMIO, 0x264e, &GB_TILE_MODE10[0], sizeof(GB_TILE_MODE10)/sizeof(GB_TILE_MODE10[0]), 0, 0 },
+	{ "mmGB_TILE_MODE11", REG_MMIO, 0x264f, &GB_TILE_MODE11[0], sizeof(GB_TILE_MODE11)/sizeof(GB_TILE_MODE11[0]), 0, 0 },
+	{ "mmGB_TILE_MODE12", REG_MMIO, 0x2650, &GB_TILE_MODE12[0], sizeof(GB_TILE_MODE12)/sizeof(GB_TILE_MODE12[0]), 0, 0 },
+	{ "mmGB_TILE_MODE13", REG_MMIO, 0x2651, &GB_TILE_MODE13[0], sizeof(GB_TILE_MODE13)/sizeof(GB_TILE_MODE13[0]), 0, 0 },
+	{ "mmGB_TILE_MODE14", REG_MMIO, 0x2652, &GB_TILE_MODE14[0], sizeof(GB_TILE_MODE14)/sizeof(GB_TILE_MODE14[0]), 0, 0 },
+	{ "mmGB_TILE_MODE15", REG_MMIO, 0x2653, &GB_TILE_MODE15[0], sizeof(GB_TILE_MODE15)/sizeof(GB_TILE_MODE15[0]), 0, 0 },
+	{ "mmGB_TILE_MODE16", REG_MMIO, 0x2654, &GB_TILE_MODE16[0], sizeof(GB_TILE_MODE16)/sizeof(GB_TILE_MODE16[0]), 0, 0 },
+	{ "mmGB_TILE_MODE17", REG_MMIO, 0x2655, &GB_TILE_MODE17[0], sizeof(GB_TILE_MODE17)/sizeof(GB_TILE_MODE17[0]), 0, 0 },
+	{ "mmGB_TILE_MODE18", REG_MMIO, 0x2656, &GB_TILE_MODE18[0], sizeof(GB_TILE_MODE18)/sizeof(GB_TILE_MODE18[0]), 0, 0 },
+	{ "mmGB_TILE_MODE19", REG_MMIO, 0x2657, &GB_TILE_MODE19[0], sizeof(GB_TILE_MODE19)/sizeof(GB_TILE_MODE19[0]), 0, 0 },
+	{ "mmGB_TILE_MODE20", REG_MMIO, 0x2658, &GB_TILE_MODE20[0], sizeof(GB_TILE_MODE20)/sizeof(GB_TILE_MODE20[0]), 0, 0 },
+	{ "mmGB_TILE_MODE21", REG_MMIO, 0x2659, &GB_TILE_MODE21[0], sizeof(GB_TILE_MODE21)/sizeof(GB_TILE_MODE21[0]), 0, 0 },
+	{ "mmGB_TILE_MODE22", REG_MMIO, 0x265a, &GB_TILE_MODE22[0], sizeof(GB_TILE_MODE22)/sizeof(GB_TILE_MODE22[0]), 0, 0 },
+	{ "mmGB_TILE_MODE23", REG_MMIO, 0x265b, &GB_TILE_MODE23[0], sizeof(GB_TILE_MODE23)/sizeof(GB_TILE_MODE23[0]), 0, 0 },
+	{ "mmGB_TILE_MODE24", REG_MMIO, 0x265c, &GB_TILE_MODE24[0], sizeof(GB_TILE_MODE24)/sizeof(GB_TILE_MODE24[0]), 0, 0 },
+	{ "mmGB_TILE_MODE25", REG_MMIO, 0x265d, &GB_TILE_MODE25[0], sizeof(GB_TILE_MODE25)/sizeof(GB_TILE_MODE25[0]), 0, 0 },
+	{ "mmGB_TILE_MODE26", REG_MMIO, 0x265e, &GB_TILE_MODE26[0], sizeof(GB_TILE_MODE26)/sizeof(GB_TILE_MODE26[0]), 0, 0 },
+	{ "mmGB_TILE_MODE27", REG_MMIO, 0x265f, &GB_TILE_MODE27[0], sizeof(GB_TILE_MODE27)/sizeof(GB_TILE_MODE27[0]), 0, 0 },
+	{ "mmGB_TILE_MODE28", REG_MMIO, 0x2660, &GB_TILE_MODE28[0], sizeof(GB_TILE_MODE28)/sizeof(GB_TILE_MODE28[0]), 0, 0 },
+	{ "mmGB_TILE_MODE29", REG_MMIO, 0x2661, &GB_TILE_MODE29[0], sizeof(GB_TILE_MODE29)/sizeof(GB_TILE_MODE29[0]), 0, 0 },
+	{ "mmGB_TILE_MODE30", REG_MMIO, 0x2662, &GB_TILE_MODE30[0], sizeof(GB_TILE_MODE30)/sizeof(GB_TILE_MODE30[0]), 0, 0 },
+	{ "mmGB_TILE_MODE31", REG_MMIO, 0x2663, &GB_TILE_MODE31[0], sizeof(GB_TILE_MODE31)/sizeof(GB_TILE_MODE31[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE0", REG_MMIO, 0x2664, &GB_MACROTILE_MODE0[0], sizeof(GB_MACROTILE_MODE0)/sizeof(GB_MACROTILE_MODE0[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE1", REG_MMIO, 0x2665, &GB_MACROTILE_MODE1[0], sizeof(GB_MACROTILE_MODE1)/sizeof(GB_MACROTILE_MODE1[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE2", REG_MMIO, 0x2666, &GB_MACROTILE_MODE2[0], sizeof(GB_MACROTILE_MODE2)/sizeof(GB_MACROTILE_MODE2[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE3", REG_MMIO, 0x2667, &GB_MACROTILE_MODE3[0], sizeof(GB_MACROTILE_MODE3)/sizeof(GB_MACROTILE_MODE3[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE4", REG_MMIO, 0x2668, &GB_MACROTILE_MODE4[0], sizeof(GB_MACROTILE_MODE4)/sizeof(GB_MACROTILE_MODE4[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE5", REG_MMIO, 0x2669, &GB_MACROTILE_MODE5[0], sizeof(GB_MACROTILE_MODE5)/sizeof(GB_MACROTILE_MODE5[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE6", REG_MMIO, 0x266a, &GB_MACROTILE_MODE6[0], sizeof(GB_MACROTILE_MODE6)/sizeof(GB_MACROTILE_MODE6[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE7", REG_MMIO, 0x266b, &GB_MACROTILE_MODE7[0], sizeof(GB_MACROTILE_MODE7)/sizeof(GB_MACROTILE_MODE7[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE8", REG_MMIO, 0x266c, &GB_MACROTILE_MODE8[0], sizeof(GB_MACROTILE_MODE8)/sizeof(GB_MACROTILE_MODE8[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE9", REG_MMIO, 0x266d, &GB_MACROTILE_MODE9[0], sizeof(GB_MACROTILE_MODE9)/sizeof(GB_MACROTILE_MODE9[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE10", REG_MMIO, 0x266e, &GB_MACROTILE_MODE10[0], sizeof(GB_MACROTILE_MODE10)/sizeof(GB_MACROTILE_MODE10[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE11", REG_MMIO, 0x266f, &GB_MACROTILE_MODE11[0], sizeof(GB_MACROTILE_MODE11)/sizeof(GB_MACROTILE_MODE11[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE12", REG_MMIO, 0x2670, &GB_MACROTILE_MODE12[0], sizeof(GB_MACROTILE_MODE12)/sizeof(GB_MACROTILE_MODE12[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE13", REG_MMIO, 0x2671, &GB_MACROTILE_MODE13[0], sizeof(GB_MACROTILE_MODE13)/sizeof(GB_MACROTILE_MODE13[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE14", REG_MMIO, 0x2672, &GB_MACROTILE_MODE14[0], sizeof(GB_MACROTILE_MODE14)/sizeof(GB_MACROTILE_MODE14[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE15", REG_MMIO, 0x2673, &GB_MACROTILE_MODE15[0], sizeof(GB_MACROTILE_MODE15)/sizeof(GB_MACROTILE_MODE15[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_3", REG_MMIO, 0x2683, &CB_HW_CONTROL_3[0], sizeof(CB_HW_CONTROL_3)/sizeof(CB_HW_CONTROL_3[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL", REG_MMIO, 0x2684, &CB_HW_CONTROL[0], sizeof(CB_HW_CONTROL)/sizeof(CB_HW_CONTROL[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_1", REG_MMIO, 0x2685, &CB_HW_CONTROL_1[0], sizeof(CB_HW_CONTROL_1)/sizeof(CB_HW_CONTROL_1[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_2", REG_MMIO, 0x2686, &CB_HW_CONTROL_2[0], sizeof(CB_HW_CONTROL_2)/sizeof(CB_HW_CONTROL_2[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_1", REG_MMIO, 0x2699, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_2", REG_MMIO, 0x269a, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_3", REG_MMIO, 0x269b, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_4", REG_MMIO, 0x269c, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_5", REG_MMIO, 0x269d, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_6", REG_MMIO, 0x269e, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_7", REG_MMIO, 0x269f, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_8", REG_MMIO, 0x26a0, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_9", REG_MMIO, 0x26a1, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_10", REG_MMIO, 0x26a2, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_11", REG_MMIO, 0x26a3, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_12", REG_MMIO, 0x26a4, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_13", REG_MMIO, 0x26a5, &CB_DEBUG_BUS_13[0], sizeof(CB_DEBUG_BUS_13)/sizeof(CB_DEBUG_BUS_13[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_14", REG_MMIO, 0x26a6, &CB_DEBUG_BUS_14[0], sizeof(CB_DEBUG_BUS_14)/sizeof(CB_DEBUG_BUS_14[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_15", REG_MMIO, 0x26a7, &CB_DEBUG_BUS_15[0], sizeof(CB_DEBUG_BUS_15)/sizeof(CB_DEBUG_BUS_15[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_16", REG_MMIO, 0x26a8, &CB_DEBUG_BUS_16[0], sizeof(CB_DEBUG_BUS_16)/sizeof(CB_DEBUG_BUS_16[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_17", REG_MMIO, 0x26a9, &CB_DEBUG_BUS_17[0], sizeof(CB_DEBUG_BUS_17)/sizeof(CB_DEBUG_BUS_17[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_18", REG_MMIO, 0x26aa, &CB_DEBUG_BUS_18[0], sizeof(CB_DEBUG_BUS_18)/sizeof(CB_DEBUG_BUS_18[0]), 0, 0 },
+	{ "mmGC_USER_RB_REDUNDANCY", REG_MMIO, 0x26de, &GC_USER_RB_REDUNDANCY[0], sizeof(GC_USER_RB_REDUNDANCY)/sizeof(GC_USER_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmGC_USER_RB_BACKEND_DISABLE", REG_MMIO, 0x26df, &GC_USER_RB_BACKEND_DISABLE[0], sizeof(GC_USER_RB_BACKEND_DISABLE)/sizeof(GC_USER_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmTCP_INVALIDATE", REG_MMIO, 0x2b00, &TCP_INVALIDATE[0], sizeof(TCP_INVALIDATE)/sizeof(TCP_INVALIDATE[0]), 0, 0 },
+	{ "mmTCP_STATUS", REG_MMIO, 0x2b01, &TCP_STATUS[0], sizeof(TCP_STATUS)/sizeof(TCP_STATUS[0]), 0, 0 },
+	{ "mmTCP_CNTL", REG_MMIO, 0x2b02, &TCP_CNTL[0], sizeof(TCP_CNTL)/sizeof(TCP_CNTL[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_LO", REG_MMIO, 0x2b03, &TCP_CHAN_STEER_LO[0], sizeof(TCP_CHAN_STEER_LO)/sizeof(TCP_CHAN_STEER_LO[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_HI", REG_MMIO, 0x2b04, &TCP_CHAN_STEER_HI[0], sizeof(TCP_CHAN_STEER_HI)/sizeof(TCP_CHAN_STEER_HI[0]), 0, 0 },
+	{ "mmTCP_ADDR_CONFIG", REG_MMIO, 0x2b05, &TCP_ADDR_CONFIG[0], sizeof(TCP_ADDR_CONFIG)/sizeof(TCP_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmTCP_CREDIT", REG_MMIO, 0x2b06, &TCP_CREDIT[0], sizeof(TCP_CREDIT)/sizeof(TCP_CREDIT[0]), 0, 0 },
+	{ "mmTCP_BUFFER_ADDR_HASH_CNTL", REG_MMIO, 0x2b16, &TCP_BUFFER_ADDR_HASH_CNTL[0], sizeof(TCP_BUFFER_ADDR_HASH_CNTL)/sizeof(TCP_BUFFER_ADDR_HASH_CNTL[0]), 0, 0 },
+	{ "mmTCP_EDC_COUNTER", REG_MMIO, 0x2b17, &TCP_EDC_COUNTER[0], sizeof(TCP_EDC_COUNTER)/sizeof(TCP_EDC_COUNTER[0]), 0, 0 },
+	{ "mmTC_CFG_L1_LOAD_POLICY0", REG_MMIO, 0x2b1a, &TC_CFG_L1_LOAD_POLICY0[0], sizeof(TC_CFG_L1_LOAD_POLICY0)/sizeof(TC_CFG_L1_LOAD_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L1_LOAD_POLICY1", REG_MMIO, 0x2b1b, &TC_CFG_L1_LOAD_POLICY1[0], sizeof(TC_CFG_L1_LOAD_POLICY1)/sizeof(TC_CFG_L1_LOAD_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L1_STORE_POLICY", REG_MMIO, 0x2b1c, &TC_CFG_L1_STORE_POLICY[0], sizeof(TC_CFG_L1_STORE_POLICY)/sizeof(TC_CFG_L1_STORE_POLICY[0]), 0, 0 },
+	{ "mmTC_CFG_L2_LOAD_POLICY0", REG_MMIO, 0x2b1d, &TC_CFG_L2_LOAD_POLICY0[0], sizeof(TC_CFG_L2_LOAD_POLICY0)/sizeof(TC_CFG_L2_LOAD_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L2_LOAD_POLICY1", REG_MMIO, 0x2b1e, &TC_CFG_L2_LOAD_POLICY1[0], sizeof(TC_CFG_L2_LOAD_POLICY1)/sizeof(TC_CFG_L2_LOAD_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L2_STORE_POLICY0", REG_MMIO, 0x2b1f, &TC_CFG_L2_STORE_POLICY0[0], sizeof(TC_CFG_L2_STORE_POLICY0)/sizeof(TC_CFG_L2_STORE_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L2_STORE_POLICY1", REG_MMIO, 0x2b20, &TC_CFG_L2_STORE_POLICY1[0], sizeof(TC_CFG_L2_STORE_POLICY1)/sizeof(TC_CFG_L2_STORE_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L2_ATOMIC_POLICY", REG_MMIO, 0x2b21, &TC_CFG_L2_ATOMIC_POLICY[0], sizeof(TC_CFG_L2_ATOMIC_POLICY)/sizeof(TC_CFG_L2_ATOMIC_POLICY[0]), 0, 0 },
+	{ "mmTC_CFG_L1_VOLATILE", REG_MMIO, 0x2b22, &TC_CFG_L1_VOLATILE[0], sizeof(TC_CFG_L1_VOLATILE)/sizeof(TC_CFG_L1_VOLATILE[0]), 0, 0 },
+	{ "mmTC_CFG_L2_VOLATILE", REG_MMIO, 0x2b23, &TC_CFG_L2_VOLATILE[0], sizeof(TC_CFG_L2_VOLATILE)/sizeof(TC_CFG_L2_VOLATILE[0]), 0, 0 },
+	{ "mmTCI_STATUS", REG_MMIO, 0x2b61, &TCI_STATUS[0], sizeof(TCI_STATUS)/sizeof(TCI_STATUS[0]), 0, 0 },
+	{ "mmTCI_CNTL_1", REG_MMIO, 0x2b62, &TCI_CNTL_1[0], sizeof(TCI_CNTL_1)/sizeof(TCI_CNTL_1[0]), 0, 0 },
+	{ "mmTCI_CNTL_2", REG_MMIO, 0x2b63, &TCI_CNTL_2[0], sizeof(TCI_CNTL_2)/sizeof(TCI_CNTL_2[0]), 0, 0 },
+	{ "mmTCC_CTRL", REG_MMIO, 0x2b80, &TCC_CTRL[0], sizeof(TCC_CTRL)/sizeof(TCC_CTRL[0]), 0, 0 },
+	{ "mmTCC_EDC_COUNTER", REG_MMIO, 0x2b82, &TCC_EDC_COUNTER[0], sizeof(TCC_EDC_COUNTER)/sizeof(TCC_EDC_COUNTER[0]), 0, 0 },
+	{ "mmTCC_REDUNDANCY", REG_MMIO, 0x2b83, &TCC_REDUNDANCY[0], sizeof(TCC_REDUNDANCY)/sizeof(TCC_REDUNDANCY[0]), 0, 0 },
+	{ "mmTCA_CTRL", REG_MMIO, 0x2bc0, &TCA_CTRL[0], sizeof(TCA_CTRL)/sizeof(TCA_CTRL[0]), 0, 0 },
+	{ "mmTCS_CTRL", REG_MMIO, 0x2be0, &TCS_CTRL[0], sizeof(TCS_CTRL)/sizeof(TCS_CTRL[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_PS", REG_MMIO, 0x2c00, &SPI_SHADER_TBA_LO_PS[0], sizeof(SPI_SHADER_TBA_LO_PS)/sizeof(SPI_SHADER_TBA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_PS", REG_MMIO, 0x2c01, &SPI_SHADER_TBA_HI_PS[0], sizeof(SPI_SHADER_TBA_HI_PS)/sizeof(SPI_SHADER_TBA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_PS", REG_MMIO, 0x2c02, &SPI_SHADER_TMA_LO_PS[0], sizeof(SPI_SHADER_TMA_LO_PS)/sizeof(SPI_SHADER_TMA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_PS", REG_MMIO, 0x2c03, &SPI_SHADER_TMA_HI_PS[0], sizeof(SPI_SHADER_TMA_HI_PS)/sizeof(SPI_SHADER_TMA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_PS", REG_MMIO, 0x2c07, &SPI_SHADER_PGM_RSRC3_PS[0], sizeof(SPI_SHADER_PGM_RSRC3_PS)/sizeof(SPI_SHADER_PGM_RSRC3_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_PS", REG_MMIO, 0x2c08, &SPI_SHADER_PGM_LO_PS[0], sizeof(SPI_SHADER_PGM_LO_PS)/sizeof(SPI_SHADER_PGM_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_PS", REG_MMIO, 0x2c09, &SPI_SHADER_PGM_HI_PS[0], sizeof(SPI_SHADER_PGM_HI_PS)/sizeof(SPI_SHADER_PGM_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_PS", REG_MMIO, 0x2c0a, &SPI_SHADER_PGM_RSRC1_PS[0], sizeof(SPI_SHADER_PGM_RSRC1_PS)/sizeof(SPI_SHADER_PGM_RSRC1_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_PS", REG_MMIO, 0x2c0b, &SPI_SHADER_PGM_RSRC2_PS[0], sizeof(SPI_SHADER_PGM_RSRC2_PS)/sizeof(SPI_SHADER_PGM_RSRC2_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_0", REG_MMIO, 0x2c0c, &SPI_SHADER_USER_DATA_PS_0[0], sizeof(SPI_SHADER_USER_DATA_PS_0)/sizeof(SPI_SHADER_USER_DATA_PS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_1", REG_MMIO, 0x2c0d, &SPI_SHADER_USER_DATA_PS_1[0], sizeof(SPI_SHADER_USER_DATA_PS_1)/sizeof(SPI_SHADER_USER_DATA_PS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_2", REG_MMIO, 0x2c0e, &SPI_SHADER_USER_DATA_PS_2[0], sizeof(SPI_SHADER_USER_DATA_PS_2)/sizeof(SPI_SHADER_USER_DATA_PS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_3", REG_MMIO, 0x2c0f, &SPI_SHADER_USER_DATA_PS_3[0], sizeof(SPI_SHADER_USER_DATA_PS_3)/sizeof(SPI_SHADER_USER_DATA_PS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_4", REG_MMIO, 0x2c10, &SPI_SHADER_USER_DATA_PS_4[0], sizeof(SPI_SHADER_USER_DATA_PS_4)/sizeof(SPI_SHADER_USER_DATA_PS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_5", REG_MMIO, 0x2c11, &SPI_SHADER_USER_DATA_PS_5[0], sizeof(SPI_SHADER_USER_DATA_PS_5)/sizeof(SPI_SHADER_USER_DATA_PS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_6", REG_MMIO, 0x2c12, &SPI_SHADER_USER_DATA_PS_6[0], sizeof(SPI_SHADER_USER_DATA_PS_6)/sizeof(SPI_SHADER_USER_DATA_PS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_7", REG_MMIO, 0x2c13, &SPI_SHADER_USER_DATA_PS_7[0], sizeof(SPI_SHADER_USER_DATA_PS_7)/sizeof(SPI_SHADER_USER_DATA_PS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_8", REG_MMIO, 0x2c14, &SPI_SHADER_USER_DATA_PS_8[0], sizeof(SPI_SHADER_USER_DATA_PS_8)/sizeof(SPI_SHADER_USER_DATA_PS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_9", REG_MMIO, 0x2c15, &SPI_SHADER_USER_DATA_PS_9[0], sizeof(SPI_SHADER_USER_DATA_PS_9)/sizeof(SPI_SHADER_USER_DATA_PS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_10", REG_MMIO, 0x2c16, &SPI_SHADER_USER_DATA_PS_10[0], sizeof(SPI_SHADER_USER_DATA_PS_10)/sizeof(SPI_SHADER_USER_DATA_PS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_11", REG_MMIO, 0x2c17, &SPI_SHADER_USER_DATA_PS_11[0], sizeof(SPI_SHADER_USER_DATA_PS_11)/sizeof(SPI_SHADER_USER_DATA_PS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_12", REG_MMIO, 0x2c18, &SPI_SHADER_USER_DATA_PS_12[0], sizeof(SPI_SHADER_USER_DATA_PS_12)/sizeof(SPI_SHADER_USER_DATA_PS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_13", REG_MMIO, 0x2c19, &SPI_SHADER_USER_DATA_PS_13[0], sizeof(SPI_SHADER_USER_DATA_PS_13)/sizeof(SPI_SHADER_USER_DATA_PS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_14", REG_MMIO, 0x2c1a, &SPI_SHADER_USER_DATA_PS_14[0], sizeof(SPI_SHADER_USER_DATA_PS_14)/sizeof(SPI_SHADER_USER_DATA_PS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_15", REG_MMIO, 0x2c1b, &SPI_SHADER_USER_DATA_PS_15[0], sizeof(SPI_SHADER_USER_DATA_PS_15)/sizeof(SPI_SHADER_USER_DATA_PS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_VS", REG_MMIO, 0x2c40, &SPI_SHADER_TBA_LO_VS[0], sizeof(SPI_SHADER_TBA_LO_VS)/sizeof(SPI_SHADER_TBA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_VS", REG_MMIO, 0x2c41, &SPI_SHADER_TBA_HI_VS[0], sizeof(SPI_SHADER_TBA_HI_VS)/sizeof(SPI_SHADER_TBA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_VS", REG_MMIO, 0x2c42, &SPI_SHADER_TMA_LO_VS[0], sizeof(SPI_SHADER_TMA_LO_VS)/sizeof(SPI_SHADER_TMA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_VS", REG_MMIO, 0x2c43, &SPI_SHADER_TMA_HI_VS[0], sizeof(SPI_SHADER_TMA_HI_VS)/sizeof(SPI_SHADER_TMA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_VS", REG_MMIO, 0x2c46, &SPI_SHADER_PGM_RSRC3_VS[0], sizeof(SPI_SHADER_PGM_RSRC3_VS)/sizeof(SPI_SHADER_PGM_RSRC3_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_LATE_ALLOC_VS", REG_MMIO, 0x2c47, &SPI_SHADER_LATE_ALLOC_VS[0], sizeof(SPI_SHADER_LATE_ALLOC_VS)/sizeof(SPI_SHADER_LATE_ALLOC_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_VS", REG_MMIO, 0x2c48, &SPI_SHADER_PGM_LO_VS[0], sizeof(SPI_SHADER_PGM_LO_VS)/sizeof(SPI_SHADER_PGM_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_VS", REG_MMIO, 0x2c49, &SPI_SHADER_PGM_HI_VS[0], sizeof(SPI_SHADER_PGM_HI_VS)/sizeof(SPI_SHADER_PGM_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_VS", REG_MMIO, 0x2c4a, &SPI_SHADER_PGM_RSRC1_VS[0], sizeof(SPI_SHADER_PGM_RSRC1_VS)/sizeof(SPI_SHADER_PGM_RSRC1_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_VS", REG_MMIO, 0x2c4b, &SPI_SHADER_PGM_RSRC2_VS[0], sizeof(SPI_SHADER_PGM_RSRC2_VS)/sizeof(SPI_SHADER_PGM_RSRC2_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_0", REG_MMIO, 0x2c4c, &SPI_SHADER_USER_DATA_VS_0[0], sizeof(SPI_SHADER_USER_DATA_VS_0)/sizeof(SPI_SHADER_USER_DATA_VS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_1", REG_MMIO, 0x2c4d, &SPI_SHADER_USER_DATA_VS_1[0], sizeof(SPI_SHADER_USER_DATA_VS_1)/sizeof(SPI_SHADER_USER_DATA_VS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_2", REG_MMIO, 0x2c4e, &SPI_SHADER_USER_DATA_VS_2[0], sizeof(SPI_SHADER_USER_DATA_VS_2)/sizeof(SPI_SHADER_USER_DATA_VS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_3", REG_MMIO, 0x2c4f, &SPI_SHADER_USER_DATA_VS_3[0], sizeof(SPI_SHADER_USER_DATA_VS_3)/sizeof(SPI_SHADER_USER_DATA_VS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_4", REG_MMIO, 0x2c50, &SPI_SHADER_USER_DATA_VS_4[0], sizeof(SPI_SHADER_USER_DATA_VS_4)/sizeof(SPI_SHADER_USER_DATA_VS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_5", REG_MMIO, 0x2c51, &SPI_SHADER_USER_DATA_VS_5[0], sizeof(SPI_SHADER_USER_DATA_VS_5)/sizeof(SPI_SHADER_USER_DATA_VS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_6", REG_MMIO, 0x2c52, &SPI_SHADER_USER_DATA_VS_6[0], sizeof(SPI_SHADER_USER_DATA_VS_6)/sizeof(SPI_SHADER_USER_DATA_VS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_7", REG_MMIO, 0x2c53, &SPI_SHADER_USER_DATA_VS_7[0], sizeof(SPI_SHADER_USER_DATA_VS_7)/sizeof(SPI_SHADER_USER_DATA_VS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_8", REG_MMIO, 0x2c54, &SPI_SHADER_USER_DATA_VS_8[0], sizeof(SPI_SHADER_USER_DATA_VS_8)/sizeof(SPI_SHADER_USER_DATA_VS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_9", REG_MMIO, 0x2c55, &SPI_SHADER_USER_DATA_VS_9[0], sizeof(SPI_SHADER_USER_DATA_VS_9)/sizeof(SPI_SHADER_USER_DATA_VS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_10", REG_MMIO, 0x2c56, &SPI_SHADER_USER_DATA_VS_10[0], sizeof(SPI_SHADER_USER_DATA_VS_10)/sizeof(SPI_SHADER_USER_DATA_VS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_11", REG_MMIO, 0x2c57, &SPI_SHADER_USER_DATA_VS_11[0], sizeof(SPI_SHADER_USER_DATA_VS_11)/sizeof(SPI_SHADER_USER_DATA_VS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_12", REG_MMIO, 0x2c58, &SPI_SHADER_USER_DATA_VS_12[0], sizeof(SPI_SHADER_USER_DATA_VS_12)/sizeof(SPI_SHADER_USER_DATA_VS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_13", REG_MMIO, 0x2c59, &SPI_SHADER_USER_DATA_VS_13[0], sizeof(SPI_SHADER_USER_DATA_VS_13)/sizeof(SPI_SHADER_USER_DATA_VS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_14", REG_MMIO, 0x2c5a, &SPI_SHADER_USER_DATA_VS_14[0], sizeof(SPI_SHADER_USER_DATA_VS_14)/sizeof(SPI_SHADER_USER_DATA_VS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_15", REG_MMIO, 0x2c5b, &SPI_SHADER_USER_DATA_VS_15[0], sizeof(SPI_SHADER_USER_DATA_VS_15)/sizeof(SPI_SHADER_USER_DATA_VS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES_VS", REG_MMIO, 0x2c7c, &SPI_SHADER_PGM_RSRC2_ES_VS[0], sizeof(SPI_SHADER_PGM_RSRC2_ES_VS)/sizeof(SPI_SHADER_PGM_RSRC2_ES_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_VS", REG_MMIO, 0x2c7d, &SPI_SHADER_PGM_RSRC2_LS_VS[0], sizeof(SPI_SHADER_PGM_RSRC2_LS_VS)/sizeof(SPI_SHADER_PGM_RSRC2_LS_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_GS", REG_MMIO, 0x2c80, &SPI_SHADER_TBA_LO_GS[0], sizeof(SPI_SHADER_TBA_LO_GS)/sizeof(SPI_SHADER_TBA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_GS", REG_MMIO, 0x2c81, &SPI_SHADER_TBA_HI_GS[0], sizeof(SPI_SHADER_TBA_HI_GS)/sizeof(SPI_SHADER_TBA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_GS", REG_MMIO, 0x2c82, &SPI_SHADER_TMA_LO_GS[0], sizeof(SPI_SHADER_TMA_LO_GS)/sizeof(SPI_SHADER_TMA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_GS", REG_MMIO, 0x2c83, &SPI_SHADER_TMA_HI_GS[0], sizeof(SPI_SHADER_TMA_HI_GS)/sizeof(SPI_SHADER_TMA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_GS", REG_MMIO, 0x2c87, &SPI_SHADER_PGM_RSRC3_GS[0], sizeof(SPI_SHADER_PGM_RSRC3_GS)/sizeof(SPI_SHADER_PGM_RSRC3_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_GS", REG_MMIO, 0x2c88, &SPI_SHADER_PGM_LO_GS[0], sizeof(SPI_SHADER_PGM_LO_GS)/sizeof(SPI_SHADER_PGM_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_GS", REG_MMIO, 0x2c89, &SPI_SHADER_PGM_HI_GS[0], sizeof(SPI_SHADER_PGM_HI_GS)/sizeof(SPI_SHADER_PGM_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_GS", REG_MMIO, 0x2c8a, &SPI_SHADER_PGM_RSRC1_GS[0], sizeof(SPI_SHADER_PGM_RSRC1_GS)/sizeof(SPI_SHADER_PGM_RSRC1_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_GS", REG_MMIO, 0x2c8b, &SPI_SHADER_PGM_RSRC2_GS[0], sizeof(SPI_SHADER_PGM_RSRC2_GS)/sizeof(SPI_SHADER_PGM_RSRC2_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_0", REG_MMIO, 0x2c8c, &SPI_SHADER_USER_DATA_GS_0[0], sizeof(SPI_SHADER_USER_DATA_GS_0)/sizeof(SPI_SHADER_USER_DATA_GS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_1", REG_MMIO, 0x2c8d, &SPI_SHADER_USER_DATA_GS_1[0], sizeof(SPI_SHADER_USER_DATA_GS_1)/sizeof(SPI_SHADER_USER_DATA_GS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_2", REG_MMIO, 0x2c8e, &SPI_SHADER_USER_DATA_GS_2[0], sizeof(SPI_SHADER_USER_DATA_GS_2)/sizeof(SPI_SHADER_USER_DATA_GS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_3", REG_MMIO, 0x2c8f, &SPI_SHADER_USER_DATA_GS_3[0], sizeof(SPI_SHADER_USER_DATA_GS_3)/sizeof(SPI_SHADER_USER_DATA_GS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_4", REG_MMIO, 0x2c90, &SPI_SHADER_USER_DATA_GS_4[0], sizeof(SPI_SHADER_USER_DATA_GS_4)/sizeof(SPI_SHADER_USER_DATA_GS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_5", REG_MMIO, 0x2c91, &SPI_SHADER_USER_DATA_GS_5[0], sizeof(SPI_SHADER_USER_DATA_GS_5)/sizeof(SPI_SHADER_USER_DATA_GS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_6", REG_MMIO, 0x2c92, &SPI_SHADER_USER_DATA_GS_6[0], sizeof(SPI_SHADER_USER_DATA_GS_6)/sizeof(SPI_SHADER_USER_DATA_GS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_7", REG_MMIO, 0x2c93, &SPI_SHADER_USER_DATA_GS_7[0], sizeof(SPI_SHADER_USER_DATA_GS_7)/sizeof(SPI_SHADER_USER_DATA_GS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_8", REG_MMIO, 0x2c94, &SPI_SHADER_USER_DATA_GS_8[0], sizeof(SPI_SHADER_USER_DATA_GS_8)/sizeof(SPI_SHADER_USER_DATA_GS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_9", REG_MMIO, 0x2c95, &SPI_SHADER_USER_DATA_GS_9[0], sizeof(SPI_SHADER_USER_DATA_GS_9)/sizeof(SPI_SHADER_USER_DATA_GS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_10", REG_MMIO, 0x2c96, &SPI_SHADER_USER_DATA_GS_10[0], sizeof(SPI_SHADER_USER_DATA_GS_10)/sizeof(SPI_SHADER_USER_DATA_GS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_11", REG_MMIO, 0x2c97, &SPI_SHADER_USER_DATA_GS_11[0], sizeof(SPI_SHADER_USER_DATA_GS_11)/sizeof(SPI_SHADER_USER_DATA_GS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_12", REG_MMIO, 0x2c98, &SPI_SHADER_USER_DATA_GS_12[0], sizeof(SPI_SHADER_USER_DATA_GS_12)/sizeof(SPI_SHADER_USER_DATA_GS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_13", REG_MMIO, 0x2c99, &SPI_SHADER_USER_DATA_GS_13[0], sizeof(SPI_SHADER_USER_DATA_GS_13)/sizeof(SPI_SHADER_USER_DATA_GS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_14", REG_MMIO, 0x2c9a, &SPI_SHADER_USER_DATA_GS_14[0], sizeof(SPI_SHADER_USER_DATA_GS_14)/sizeof(SPI_SHADER_USER_DATA_GS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_15", REG_MMIO, 0x2c9b, &SPI_SHADER_USER_DATA_GS_15[0], sizeof(SPI_SHADER_USER_DATA_GS_15)/sizeof(SPI_SHADER_USER_DATA_GS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES_GS", REG_MMIO, 0x2cbc, &SPI_SHADER_PGM_RSRC2_ES_GS[0], sizeof(SPI_SHADER_PGM_RSRC2_ES_GS)/sizeof(SPI_SHADER_PGM_RSRC2_ES_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_ES", REG_MMIO, 0x2cc0, &SPI_SHADER_TBA_LO_ES[0], sizeof(SPI_SHADER_TBA_LO_ES)/sizeof(SPI_SHADER_TBA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_ES", REG_MMIO, 0x2cc1, &SPI_SHADER_TBA_HI_ES[0], sizeof(SPI_SHADER_TBA_HI_ES)/sizeof(SPI_SHADER_TBA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_ES", REG_MMIO, 0x2cc2, &SPI_SHADER_TMA_LO_ES[0], sizeof(SPI_SHADER_TMA_LO_ES)/sizeof(SPI_SHADER_TMA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_ES", REG_MMIO, 0x2cc3, &SPI_SHADER_TMA_HI_ES[0], sizeof(SPI_SHADER_TMA_HI_ES)/sizeof(SPI_SHADER_TMA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_ES", REG_MMIO, 0x2cc7, &SPI_SHADER_PGM_RSRC3_ES[0], sizeof(SPI_SHADER_PGM_RSRC3_ES)/sizeof(SPI_SHADER_PGM_RSRC3_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_ES", REG_MMIO, 0x2cc8, &SPI_SHADER_PGM_LO_ES[0], sizeof(SPI_SHADER_PGM_LO_ES)/sizeof(SPI_SHADER_PGM_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_ES", REG_MMIO, 0x2cc9, &SPI_SHADER_PGM_HI_ES[0], sizeof(SPI_SHADER_PGM_HI_ES)/sizeof(SPI_SHADER_PGM_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_ES", REG_MMIO, 0x2cca, &SPI_SHADER_PGM_RSRC1_ES[0], sizeof(SPI_SHADER_PGM_RSRC1_ES)/sizeof(SPI_SHADER_PGM_RSRC1_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES", REG_MMIO, 0x2ccb, &SPI_SHADER_PGM_RSRC2_ES[0], sizeof(SPI_SHADER_PGM_RSRC2_ES)/sizeof(SPI_SHADER_PGM_RSRC2_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_0", REG_MMIO, 0x2ccc, &SPI_SHADER_USER_DATA_ES_0[0], sizeof(SPI_SHADER_USER_DATA_ES_0)/sizeof(SPI_SHADER_USER_DATA_ES_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_1", REG_MMIO, 0x2ccd, &SPI_SHADER_USER_DATA_ES_1[0], sizeof(SPI_SHADER_USER_DATA_ES_1)/sizeof(SPI_SHADER_USER_DATA_ES_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_2", REG_MMIO, 0x2cce, &SPI_SHADER_USER_DATA_ES_2[0], sizeof(SPI_SHADER_USER_DATA_ES_2)/sizeof(SPI_SHADER_USER_DATA_ES_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_3", REG_MMIO, 0x2ccf, &SPI_SHADER_USER_DATA_ES_3[0], sizeof(SPI_SHADER_USER_DATA_ES_3)/sizeof(SPI_SHADER_USER_DATA_ES_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_4", REG_MMIO, 0x2cd0, &SPI_SHADER_USER_DATA_ES_4[0], sizeof(SPI_SHADER_USER_DATA_ES_4)/sizeof(SPI_SHADER_USER_DATA_ES_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_5", REG_MMIO, 0x2cd1, &SPI_SHADER_USER_DATA_ES_5[0], sizeof(SPI_SHADER_USER_DATA_ES_5)/sizeof(SPI_SHADER_USER_DATA_ES_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_6", REG_MMIO, 0x2cd2, &SPI_SHADER_USER_DATA_ES_6[0], sizeof(SPI_SHADER_USER_DATA_ES_6)/sizeof(SPI_SHADER_USER_DATA_ES_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_7", REG_MMIO, 0x2cd3, &SPI_SHADER_USER_DATA_ES_7[0], sizeof(SPI_SHADER_USER_DATA_ES_7)/sizeof(SPI_SHADER_USER_DATA_ES_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_8", REG_MMIO, 0x2cd4, &SPI_SHADER_USER_DATA_ES_8[0], sizeof(SPI_SHADER_USER_DATA_ES_8)/sizeof(SPI_SHADER_USER_DATA_ES_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_9", REG_MMIO, 0x2cd5, &SPI_SHADER_USER_DATA_ES_9[0], sizeof(SPI_SHADER_USER_DATA_ES_9)/sizeof(SPI_SHADER_USER_DATA_ES_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_10", REG_MMIO, 0x2cd6, &SPI_SHADER_USER_DATA_ES_10[0], sizeof(SPI_SHADER_USER_DATA_ES_10)/sizeof(SPI_SHADER_USER_DATA_ES_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_11", REG_MMIO, 0x2cd7, &SPI_SHADER_USER_DATA_ES_11[0], sizeof(SPI_SHADER_USER_DATA_ES_11)/sizeof(SPI_SHADER_USER_DATA_ES_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_12", REG_MMIO, 0x2cd8, &SPI_SHADER_USER_DATA_ES_12[0], sizeof(SPI_SHADER_USER_DATA_ES_12)/sizeof(SPI_SHADER_USER_DATA_ES_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_13", REG_MMIO, 0x2cd9, &SPI_SHADER_USER_DATA_ES_13[0], sizeof(SPI_SHADER_USER_DATA_ES_13)/sizeof(SPI_SHADER_USER_DATA_ES_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_14", REG_MMIO, 0x2cda, &SPI_SHADER_USER_DATA_ES_14[0], sizeof(SPI_SHADER_USER_DATA_ES_14)/sizeof(SPI_SHADER_USER_DATA_ES_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_15", REG_MMIO, 0x2cdb, &SPI_SHADER_USER_DATA_ES_15[0], sizeof(SPI_SHADER_USER_DATA_ES_15)/sizeof(SPI_SHADER_USER_DATA_ES_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_ES", REG_MMIO, 0x2cfd, &SPI_SHADER_PGM_RSRC2_LS_ES[0], sizeof(SPI_SHADER_PGM_RSRC2_LS_ES)/sizeof(SPI_SHADER_PGM_RSRC2_LS_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_HS", REG_MMIO, 0x2d00, &SPI_SHADER_TBA_LO_HS[0], sizeof(SPI_SHADER_TBA_LO_HS)/sizeof(SPI_SHADER_TBA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_HS", REG_MMIO, 0x2d01, &SPI_SHADER_TBA_HI_HS[0], sizeof(SPI_SHADER_TBA_HI_HS)/sizeof(SPI_SHADER_TBA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_HS", REG_MMIO, 0x2d02, &SPI_SHADER_TMA_LO_HS[0], sizeof(SPI_SHADER_TMA_LO_HS)/sizeof(SPI_SHADER_TMA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_HS", REG_MMIO, 0x2d03, &SPI_SHADER_TMA_HI_HS[0], sizeof(SPI_SHADER_TMA_HI_HS)/sizeof(SPI_SHADER_TMA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_HS", REG_MMIO, 0x2d07, &SPI_SHADER_PGM_RSRC3_HS[0], sizeof(SPI_SHADER_PGM_RSRC3_HS)/sizeof(SPI_SHADER_PGM_RSRC3_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_HS", REG_MMIO, 0x2d08, &SPI_SHADER_PGM_LO_HS[0], sizeof(SPI_SHADER_PGM_LO_HS)/sizeof(SPI_SHADER_PGM_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_HS", REG_MMIO, 0x2d09, &SPI_SHADER_PGM_HI_HS[0], sizeof(SPI_SHADER_PGM_HI_HS)/sizeof(SPI_SHADER_PGM_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_HS", REG_MMIO, 0x2d0a, &SPI_SHADER_PGM_RSRC1_HS[0], sizeof(SPI_SHADER_PGM_RSRC1_HS)/sizeof(SPI_SHADER_PGM_RSRC1_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_HS", REG_MMIO, 0x2d0b, &SPI_SHADER_PGM_RSRC2_HS[0], sizeof(SPI_SHADER_PGM_RSRC2_HS)/sizeof(SPI_SHADER_PGM_RSRC2_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_0", REG_MMIO, 0x2d0c, &SPI_SHADER_USER_DATA_HS_0[0], sizeof(SPI_SHADER_USER_DATA_HS_0)/sizeof(SPI_SHADER_USER_DATA_HS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_1", REG_MMIO, 0x2d0d, &SPI_SHADER_USER_DATA_HS_1[0], sizeof(SPI_SHADER_USER_DATA_HS_1)/sizeof(SPI_SHADER_USER_DATA_HS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_2", REG_MMIO, 0x2d0e, &SPI_SHADER_USER_DATA_HS_2[0], sizeof(SPI_SHADER_USER_DATA_HS_2)/sizeof(SPI_SHADER_USER_DATA_HS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_3", REG_MMIO, 0x2d0f, &SPI_SHADER_USER_DATA_HS_3[0], sizeof(SPI_SHADER_USER_DATA_HS_3)/sizeof(SPI_SHADER_USER_DATA_HS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_4", REG_MMIO, 0x2d10, &SPI_SHADER_USER_DATA_HS_4[0], sizeof(SPI_SHADER_USER_DATA_HS_4)/sizeof(SPI_SHADER_USER_DATA_HS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_5", REG_MMIO, 0x2d11, &SPI_SHADER_USER_DATA_HS_5[0], sizeof(SPI_SHADER_USER_DATA_HS_5)/sizeof(SPI_SHADER_USER_DATA_HS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_6", REG_MMIO, 0x2d12, &SPI_SHADER_USER_DATA_HS_6[0], sizeof(SPI_SHADER_USER_DATA_HS_6)/sizeof(SPI_SHADER_USER_DATA_HS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_7", REG_MMIO, 0x2d13, &SPI_SHADER_USER_DATA_HS_7[0], sizeof(SPI_SHADER_USER_DATA_HS_7)/sizeof(SPI_SHADER_USER_DATA_HS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_8", REG_MMIO, 0x2d14, &SPI_SHADER_USER_DATA_HS_8[0], sizeof(SPI_SHADER_USER_DATA_HS_8)/sizeof(SPI_SHADER_USER_DATA_HS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_9", REG_MMIO, 0x2d15, &SPI_SHADER_USER_DATA_HS_9[0], sizeof(SPI_SHADER_USER_DATA_HS_9)/sizeof(SPI_SHADER_USER_DATA_HS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_10", REG_MMIO, 0x2d16, &SPI_SHADER_USER_DATA_HS_10[0], sizeof(SPI_SHADER_USER_DATA_HS_10)/sizeof(SPI_SHADER_USER_DATA_HS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_11", REG_MMIO, 0x2d17, &SPI_SHADER_USER_DATA_HS_11[0], sizeof(SPI_SHADER_USER_DATA_HS_11)/sizeof(SPI_SHADER_USER_DATA_HS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_12", REG_MMIO, 0x2d18, &SPI_SHADER_USER_DATA_HS_12[0], sizeof(SPI_SHADER_USER_DATA_HS_12)/sizeof(SPI_SHADER_USER_DATA_HS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_13", REG_MMIO, 0x2d19, &SPI_SHADER_USER_DATA_HS_13[0], sizeof(SPI_SHADER_USER_DATA_HS_13)/sizeof(SPI_SHADER_USER_DATA_HS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_14", REG_MMIO, 0x2d1a, &SPI_SHADER_USER_DATA_HS_14[0], sizeof(SPI_SHADER_USER_DATA_HS_14)/sizeof(SPI_SHADER_USER_DATA_HS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_15", REG_MMIO, 0x2d1b, &SPI_SHADER_USER_DATA_HS_15[0], sizeof(SPI_SHADER_USER_DATA_HS_15)/sizeof(SPI_SHADER_USER_DATA_HS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_HS", REG_MMIO, 0x2d3d, &SPI_SHADER_PGM_RSRC2_LS_HS[0], sizeof(SPI_SHADER_PGM_RSRC2_LS_HS)/sizeof(SPI_SHADER_PGM_RSRC2_LS_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_LS", REG_MMIO, 0x2d40, &SPI_SHADER_TBA_LO_LS[0], sizeof(SPI_SHADER_TBA_LO_LS)/sizeof(SPI_SHADER_TBA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_LS", REG_MMIO, 0x2d41, &SPI_SHADER_TBA_HI_LS[0], sizeof(SPI_SHADER_TBA_HI_LS)/sizeof(SPI_SHADER_TBA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_LS", REG_MMIO, 0x2d42, &SPI_SHADER_TMA_LO_LS[0], sizeof(SPI_SHADER_TMA_LO_LS)/sizeof(SPI_SHADER_TMA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_LS", REG_MMIO, 0x2d43, &SPI_SHADER_TMA_HI_LS[0], sizeof(SPI_SHADER_TMA_HI_LS)/sizeof(SPI_SHADER_TMA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_LS", REG_MMIO, 0x2d47, &SPI_SHADER_PGM_RSRC3_LS[0], sizeof(SPI_SHADER_PGM_RSRC3_LS)/sizeof(SPI_SHADER_PGM_RSRC3_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_LS", REG_MMIO, 0x2d48, &SPI_SHADER_PGM_LO_LS[0], sizeof(SPI_SHADER_PGM_LO_LS)/sizeof(SPI_SHADER_PGM_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_LS", REG_MMIO, 0x2d49, &SPI_SHADER_PGM_HI_LS[0], sizeof(SPI_SHADER_PGM_HI_LS)/sizeof(SPI_SHADER_PGM_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_LS", REG_MMIO, 0x2d4a, &SPI_SHADER_PGM_RSRC1_LS[0], sizeof(SPI_SHADER_PGM_RSRC1_LS)/sizeof(SPI_SHADER_PGM_RSRC1_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS", REG_MMIO, 0x2d4b, &SPI_SHADER_PGM_RSRC2_LS[0], sizeof(SPI_SHADER_PGM_RSRC2_LS)/sizeof(SPI_SHADER_PGM_RSRC2_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_0", REG_MMIO, 0x2d4c, &SPI_SHADER_USER_DATA_LS_0[0], sizeof(SPI_SHADER_USER_DATA_LS_0)/sizeof(SPI_SHADER_USER_DATA_LS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_1", REG_MMIO, 0x2d4d, &SPI_SHADER_USER_DATA_LS_1[0], sizeof(SPI_SHADER_USER_DATA_LS_1)/sizeof(SPI_SHADER_USER_DATA_LS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_2", REG_MMIO, 0x2d4e, &SPI_SHADER_USER_DATA_LS_2[0], sizeof(SPI_SHADER_USER_DATA_LS_2)/sizeof(SPI_SHADER_USER_DATA_LS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_3", REG_MMIO, 0x2d4f, &SPI_SHADER_USER_DATA_LS_3[0], sizeof(SPI_SHADER_USER_DATA_LS_3)/sizeof(SPI_SHADER_USER_DATA_LS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_4", REG_MMIO, 0x2d50, &SPI_SHADER_USER_DATA_LS_4[0], sizeof(SPI_SHADER_USER_DATA_LS_4)/sizeof(SPI_SHADER_USER_DATA_LS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_5", REG_MMIO, 0x2d51, &SPI_SHADER_USER_DATA_LS_5[0], sizeof(SPI_SHADER_USER_DATA_LS_5)/sizeof(SPI_SHADER_USER_DATA_LS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_6", REG_MMIO, 0x2d52, &SPI_SHADER_USER_DATA_LS_6[0], sizeof(SPI_SHADER_USER_DATA_LS_6)/sizeof(SPI_SHADER_USER_DATA_LS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_7", REG_MMIO, 0x2d53, &SPI_SHADER_USER_DATA_LS_7[0], sizeof(SPI_SHADER_USER_DATA_LS_7)/sizeof(SPI_SHADER_USER_DATA_LS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_8", REG_MMIO, 0x2d54, &SPI_SHADER_USER_DATA_LS_8[0], sizeof(SPI_SHADER_USER_DATA_LS_8)/sizeof(SPI_SHADER_USER_DATA_LS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_9", REG_MMIO, 0x2d55, &SPI_SHADER_USER_DATA_LS_9[0], sizeof(SPI_SHADER_USER_DATA_LS_9)/sizeof(SPI_SHADER_USER_DATA_LS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_10", REG_MMIO, 0x2d56, &SPI_SHADER_USER_DATA_LS_10[0], sizeof(SPI_SHADER_USER_DATA_LS_10)/sizeof(SPI_SHADER_USER_DATA_LS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_11", REG_MMIO, 0x2d57, &SPI_SHADER_USER_DATA_LS_11[0], sizeof(SPI_SHADER_USER_DATA_LS_11)/sizeof(SPI_SHADER_USER_DATA_LS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_12", REG_MMIO, 0x2d58, &SPI_SHADER_USER_DATA_LS_12[0], sizeof(SPI_SHADER_USER_DATA_LS_12)/sizeof(SPI_SHADER_USER_DATA_LS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_13", REG_MMIO, 0x2d59, &SPI_SHADER_USER_DATA_LS_13[0], sizeof(SPI_SHADER_USER_DATA_LS_13)/sizeof(SPI_SHADER_USER_DATA_LS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_14", REG_MMIO, 0x2d5a, &SPI_SHADER_USER_DATA_LS_14[0], sizeof(SPI_SHADER_USER_DATA_LS_14)/sizeof(SPI_SHADER_USER_DATA_LS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_15", REG_MMIO, 0x2d5b, &SPI_SHADER_USER_DATA_LS_15[0], sizeof(SPI_SHADER_USER_DATA_LS_15)/sizeof(SPI_SHADER_USER_DATA_LS_15[0]), 0, 0 },
+	{ "mmCOMPUTE_DISPATCH_INITIATOR", REG_MMIO, 0x2e00, &COMPUTE_DISPATCH_INITIATOR[0], sizeof(COMPUTE_DISPATCH_INITIATOR)/sizeof(COMPUTE_DISPATCH_INITIATOR[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_X", REG_MMIO, 0x2e01, &COMPUTE_DIM_X[0], sizeof(COMPUTE_DIM_X)/sizeof(COMPUTE_DIM_X[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Y", REG_MMIO, 0x2e02, &COMPUTE_DIM_Y[0], sizeof(COMPUTE_DIM_Y)/sizeof(COMPUTE_DIM_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Z", REG_MMIO, 0x2e03, &COMPUTE_DIM_Z[0], sizeof(COMPUTE_DIM_Z)/sizeof(COMPUTE_DIM_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_START_X", REG_MMIO, 0x2e04, &COMPUTE_START_X[0], sizeof(COMPUTE_START_X)/sizeof(COMPUTE_START_X[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Y", REG_MMIO, 0x2e05, &COMPUTE_START_Y[0], sizeof(COMPUTE_START_Y)/sizeof(COMPUTE_START_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Z", REG_MMIO, 0x2e06, &COMPUTE_START_Z[0], sizeof(COMPUTE_START_Z)/sizeof(COMPUTE_START_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_X", REG_MMIO, 0x2e07, &COMPUTE_NUM_THREAD_X[0], sizeof(COMPUTE_NUM_THREAD_X)/sizeof(COMPUTE_NUM_THREAD_X[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Y", REG_MMIO, 0x2e08, &COMPUTE_NUM_THREAD_Y[0], sizeof(COMPUTE_NUM_THREAD_Y)/sizeof(COMPUTE_NUM_THREAD_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Z", REG_MMIO, 0x2e09, &COMPUTE_NUM_THREAD_Z[0], sizeof(COMPUTE_NUM_THREAD_Z)/sizeof(COMPUTE_NUM_THREAD_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_PIPELINESTAT_ENABLE", REG_MMIO, 0x2e0a, &COMPUTE_PIPELINESTAT_ENABLE[0], sizeof(COMPUTE_PIPELINESTAT_ENABLE)/sizeof(COMPUTE_PIPELINESTAT_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_PERFCOUNT_ENABLE", REG_MMIO, 0x2e0b, &COMPUTE_PERFCOUNT_ENABLE[0], sizeof(COMPUTE_PERFCOUNT_ENABLE)/sizeof(COMPUTE_PERFCOUNT_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_LO", REG_MMIO, 0x2e0c, &COMPUTE_PGM_LO[0], sizeof(COMPUTE_PGM_LO)/sizeof(COMPUTE_PGM_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_HI", REG_MMIO, 0x2e0d, &COMPUTE_PGM_HI[0], sizeof(COMPUTE_PGM_HI)/sizeof(COMPUTE_PGM_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_LO", REG_MMIO, 0x2e0e, &COMPUTE_TBA_LO[0], sizeof(COMPUTE_TBA_LO)/sizeof(COMPUTE_TBA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_HI", REG_MMIO, 0x2e0f, &COMPUTE_TBA_HI[0], sizeof(COMPUTE_TBA_HI)/sizeof(COMPUTE_TBA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_LO", REG_MMIO, 0x2e10, &COMPUTE_TMA_LO[0], sizeof(COMPUTE_TMA_LO)/sizeof(COMPUTE_TMA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_HI", REG_MMIO, 0x2e11, &COMPUTE_TMA_HI[0], sizeof(COMPUTE_TMA_HI)/sizeof(COMPUTE_TMA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC1", REG_MMIO, 0x2e12, &COMPUTE_PGM_RSRC1[0], sizeof(COMPUTE_PGM_RSRC1)/sizeof(COMPUTE_PGM_RSRC1[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC2", REG_MMIO, 0x2e13, &COMPUTE_PGM_RSRC2[0], sizeof(COMPUTE_PGM_RSRC2)/sizeof(COMPUTE_PGM_RSRC2[0]), 0, 0 },
+	{ "mmCOMPUTE_VMID", REG_MMIO, 0x2e14, &COMPUTE_VMID[0], sizeof(COMPUTE_VMID)/sizeof(COMPUTE_VMID[0]), 0, 0 },
+	{ "mmCOMPUTE_RESOURCE_LIMITS", REG_MMIO, 0x2e15, &COMPUTE_RESOURCE_LIMITS[0], sizeof(COMPUTE_RESOURCE_LIMITS)/sizeof(COMPUTE_RESOURCE_LIMITS[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE0", REG_MMIO, 0x2e16, &COMPUTE_STATIC_THREAD_MGMT_SE0[0], sizeof(COMPUTE_STATIC_THREAD_MGMT_SE0)/sizeof(COMPUTE_STATIC_THREAD_MGMT_SE0[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE1", REG_MMIO, 0x2e17, &COMPUTE_STATIC_THREAD_MGMT_SE1[0], sizeof(COMPUTE_STATIC_THREAD_MGMT_SE1)/sizeof(COMPUTE_STATIC_THREAD_MGMT_SE1[0]), 0, 0 },
+	{ "mmCOMPUTE_TMPRING_SIZE", REG_MMIO, 0x2e18, &COMPUTE_TMPRING_SIZE[0], sizeof(COMPUTE_TMPRING_SIZE)/sizeof(COMPUTE_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE2", REG_MMIO, 0x2e19, &COMPUTE_STATIC_THREAD_MGMT_SE2[0], sizeof(COMPUTE_STATIC_THREAD_MGMT_SE2)/sizeof(COMPUTE_STATIC_THREAD_MGMT_SE2[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE3", REG_MMIO, 0x2e1a, &COMPUTE_STATIC_THREAD_MGMT_SE3[0], sizeof(COMPUTE_STATIC_THREAD_MGMT_SE3)/sizeof(COMPUTE_STATIC_THREAD_MGMT_SE3[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_X", REG_MMIO, 0x2e1b, &COMPUTE_RESTART_X[0], sizeof(COMPUTE_RESTART_X)/sizeof(COMPUTE_RESTART_X[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_Y", REG_MMIO, 0x2e1c, &COMPUTE_RESTART_Y[0], sizeof(COMPUTE_RESTART_Y)/sizeof(COMPUTE_RESTART_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_Z", REG_MMIO, 0x2e1d, &COMPUTE_RESTART_Z[0], sizeof(COMPUTE_RESTART_Z)/sizeof(COMPUTE_RESTART_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_THREAD_TRACE_ENABLE", REG_MMIO, 0x2e1e, &COMPUTE_THREAD_TRACE_ENABLE[0], sizeof(COMPUTE_THREAD_TRACE_ENABLE)/sizeof(COMPUTE_THREAD_TRACE_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_MISC_RESERVED", REG_MMIO, 0x2e1f, &COMPUTE_MISC_RESERVED[0], sizeof(COMPUTE_MISC_RESERVED)/sizeof(COMPUTE_MISC_RESERVED[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_0", REG_MMIO, 0x2e40, &COMPUTE_USER_DATA_0[0], sizeof(COMPUTE_USER_DATA_0)/sizeof(COMPUTE_USER_DATA_0[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_1", REG_MMIO, 0x2e41, &COMPUTE_USER_DATA_1[0], sizeof(COMPUTE_USER_DATA_1)/sizeof(COMPUTE_USER_DATA_1[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_2", REG_MMIO, 0x2e42, &COMPUTE_USER_DATA_2[0], sizeof(COMPUTE_USER_DATA_2)/sizeof(COMPUTE_USER_DATA_2[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_3", REG_MMIO, 0x2e43, &COMPUTE_USER_DATA_3[0], sizeof(COMPUTE_USER_DATA_3)/sizeof(COMPUTE_USER_DATA_3[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_4", REG_MMIO, 0x2e44, &COMPUTE_USER_DATA_4[0], sizeof(COMPUTE_USER_DATA_4)/sizeof(COMPUTE_USER_DATA_4[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_5", REG_MMIO, 0x2e45, &COMPUTE_USER_DATA_5[0], sizeof(COMPUTE_USER_DATA_5)/sizeof(COMPUTE_USER_DATA_5[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_6", REG_MMIO, 0x2e46, &COMPUTE_USER_DATA_6[0], sizeof(COMPUTE_USER_DATA_6)/sizeof(COMPUTE_USER_DATA_6[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_7", REG_MMIO, 0x2e47, &COMPUTE_USER_DATA_7[0], sizeof(COMPUTE_USER_DATA_7)/sizeof(COMPUTE_USER_DATA_7[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_8", REG_MMIO, 0x2e48, &COMPUTE_USER_DATA_8[0], sizeof(COMPUTE_USER_DATA_8)/sizeof(COMPUTE_USER_DATA_8[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_9", REG_MMIO, 0x2e49, &COMPUTE_USER_DATA_9[0], sizeof(COMPUTE_USER_DATA_9)/sizeof(COMPUTE_USER_DATA_9[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_10", REG_MMIO, 0x2e4a, &COMPUTE_USER_DATA_10[0], sizeof(COMPUTE_USER_DATA_10)/sizeof(COMPUTE_USER_DATA_10[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_11", REG_MMIO, 0x2e4b, &COMPUTE_USER_DATA_11[0], sizeof(COMPUTE_USER_DATA_11)/sizeof(COMPUTE_USER_DATA_11[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_12", REG_MMIO, 0x2e4c, &COMPUTE_USER_DATA_12[0], sizeof(COMPUTE_USER_DATA_12)/sizeof(COMPUTE_USER_DATA_12[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_13", REG_MMIO, 0x2e4d, &COMPUTE_USER_DATA_13[0], sizeof(COMPUTE_USER_DATA_13)/sizeof(COMPUTE_USER_DATA_13[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_14", REG_MMIO, 0x2e4e, &COMPUTE_USER_DATA_14[0], sizeof(COMPUTE_USER_DATA_14)/sizeof(COMPUTE_USER_DATA_14[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_15", REG_MMIO, 0x2e4f, &COMPUTE_USER_DATA_15[0], sizeof(COMPUTE_USER_DATA_15)/sizeof(COMPUTE_USER_DATA_15[0]), 0, 0 },
+	{ "mmGRBM_CAM_INDEX", REG_MMIO, 0x3000, &GRBM_CAM_INDEX[0], sizeof(GRBM_CAM_INDEX)/sizeof(GRBM_CAM_INDEX[0]), 0, 0 },
+	{ "mmGRBM_CAM_DATA", REG_MMIO, 0x3001, &GRBM_CAM_DATA[0], sizeof(GRBM_CAM_DATA)/sizeof(GRBM_CAM_DATA[0]), 0, 0 },
+	{ "mmCP_DFY_CNTL", REG_MMIO, 0x3020, &CP_DFY_CNTL[0], sizeof(CP_DFY_CNTL)/sizeof(CP_DFY_CNTL[0]), 0, 0 },
+	{ "mmCP_DFY_STAT", REG_MMIO, 0x3021, &CP_DFY_STAT[0], sizeof(CP_DFY_STAT)/sizeof(CP_DFY_STAT[0]), 0, 0 },
+	{ "mmCP_DFY_ADDR_HI", REG_MMIO, 0x3022, &CP_DFY_ADDR_HI[0], sizeof(CP_DFY_ADDR_HI)/sizeof(CP_DFY_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DFY_ADDR_LO", REG_MMIO, 0x3023, &CP_DFY_ADDR_LO[0], sizeof(CP_DFY_ADDR_LO)/sizeof(CP_DFY_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_0", REG_MMIO, 0x3024, &CP_DFY_DATA_0[0], sizeof(CP_DFY_DATA_0)/sizeof(CP_DFY_DATA_0[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_1", REG_MMIO, 0x3025, &CP_DFY_DATA_1[0], sizeof(CP_DFY_DATA_1)/sizeof(CP_DFY_DATA_1[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_2", REG_MMIO, 0x3026, &CP_DFY_DATA_2[0], sizeof(CP_DFY_DATA_2)/sizeof(CP_DFY_DATA_2[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_3", REG_MMIO, 0x3027, &CP_DFY_DATA_3[0], sizeof(CP_DFY_DATA_3)/sizeof(CP_DFY_DATA_3[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_4", REG_MMIO, 0x3028, &CP_DFY_DATA_4[0], sizeof(CP_DFY_DATA_4)/sizeof(CP_DFY_DATA_4[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_5", REG_MMIO, 0x3029, &CP_DFY_DATA_5[0], sizeof(CP_DFY_DATA_5)/sizeof(CP_DFY_DATA_5[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_6", REG_MMIO, 0x302a, &CP_DFY_DATA_6[0], sizeof(CP_DFY_DATA_6)/sizeof(CP_DFY_DATA_6[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_7", REG_MMIO, 0x302b, &CP_DFY_DATA_7[0], sizeof(CP_DFY_DATA_7)/sizeof(CP_DFY_DATA_7[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_8", REG_MMIO, 0x302c, &CP_DFY_DATA_8[0], sizeof(CP_DFY_DATA_8)/sizeof(CP_DFY_DATA_8[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_9", REG_MMIO, 0x302d, &CP_DFY_DATA_9[0], sizeof(CP_DFY_DATA_9)/sizeof(CP_DFY_DATA_9[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_10", REG_MMIO, 0x302e, &CP_DFY_DATA_10[0], sizeof(CP_DFY_DATA_10)/sizeof(CP_DFY_DATA_10[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_11", REG_MMIO, 0x302f, &CP_DFY_DATA_11[0], sizeof(CP_DFY_DATA_11)/sizeof(CP_DFY_DATA_11[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_12", REG_MMIO, 0x3030, &CP_DFY_DATA_12[0], sizeof(CP_DFY_DATA_12)/sizeof(CP_DFY_DATA_12[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_13", REG_MMIO, 0x3031, &CP_DFY_DATA_13[0], sizeof(CP_DFY_DATA_13)/sizeof(CP_DFY_DATA_13[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_14", REG_MMIO, 0x3032, &CP_DFY_DATA_14[0], sizeof(CP_DFY_DATA_14)/sizeof(CP_DFY_DATA_14[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_15", REG_MMIO, 0x3033, &CP_DFY_DATA_15[0], sizeof(CP_DFY_DATA_15)/sizeof(CP_DFY_DATA_15[0]), 0, 0 },
+	{ "mmCP_RB0_BASE", REG_MMIO, 0x3040, &CP_RB0_BASE[0], sizeof(CP_RB0_BASE)/sizeof(CP_RB0_BASE[0]), 0, 0 },
+	{ "mmCP_RB_BASE", REG_MMIO, 0x3040, &CP_RB_BASE[0], sizeof(CP_RB_BASE)/sizeof(CP_RB_BASE[0]), 0, 0 },
+	{ "mmCP_RB0_CNTL", REG_MMIO, 0x3041, &CP_RB0_CNTL[0], sizeof(CP_RB0_CNTL)/sizeof(CP_RB0_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_CNTL", REG_MMIO, 0x3041, &CP_RB_CNTL[0], sizeof(CP_RB_CNTL)/sizeof(CP_RB_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_WR", REG_MMIO, 0x3042, &CP_RB_RPTR_WR[0], sizeof(CP_RB_RPTR_WR)/sizeof(CP_RB_RPTR_WR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR", REG_MMIO, 0x3043, &CP_RB0_RPTR_ADDR[0], sizeof(CP_RB0_RPTR_ADDR)/sizeof(CP_RB0_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_ADDR", REG_MMIO, 0x3043, &CP_RB_RPTR_ADDR[0], sizeof(CP_RB_RPTR_ADDR)/sizeof(CP_RB_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR_HI", REG_MMIO, 0x3044, &CP_RB0_RPTR_ADDR_HI[0], sizeof(CP_RB0_RPTR_ADDR_HI)/sizeof(CP_RB0_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_ADDR_HI", REG_MMIO, 0x3044, &CP_RB_RPTR_ADDR_HI[0], sizeof(CP_RB_RPTR_ADDR_HI)/sizeof(CP_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB0_WPTR", REG_MMIO, 0x3045, &CP_RB0_WPTR[0], sizeof(CP_RB0_WPTR)/sizeof(CP_RB0_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR", REG_MMIO, 0x3045, &CP_RB_WPTR[0], sizeof(CP_RB_WPTR)/sizeof(CP_RB_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3046, &CP_RB_WPTR_POLL_ADDR_LO[0], sizeof(CP_RB_WPTR_POLL_ADDR_LO)/sizeof(CP_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3047, &CP_RB_WPTR_POLL_ADDR_HI[0], sizeof(CP_RB_WPTR_POLL_ADDR_HI)/sizeof(CP_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmGC_PRIV_MODE", REG_MMIO, 0x3048, NULL, 0, 0, 0 },
+	{ "mmCP_INT_CNTL", REG_MMIO, 0x3049, &CP_INT_CNTL[0], sizeof(CP_INT_CNTL)/sizeof(CP_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_INT_STATUS", REG_MMIO, 0x304a, &CP_INT_STATUS[0], sizeof(CP_INT_STATUS)/sizeof(CP_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_DEVICE_ID", REG_MMIO, 0x304b, &CP_DEVICE_ID[0], sizeof(CP_DEVICE_ID)/sizeof(CP_DEVICE_ID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE_PRIORITY_CNTS", REG_MMIO, 0x304c, &CP_ME0_PIPE_PRIORITY_CNTS[0], sizeof(CP_ME0_PIPE_PRIORITY_CNTS)/sizeof(CP_ME0_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_RING_PRIORITY_CNTS", REG_MMIO, 0x304c, &CP_RING_PRIORITY_CNTS[0], sizeof(CP_RING_PRIORITY_CNTS)/sizeof(CP_RING_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE0_PRIORITY", REG_MMIO, 0x304d, &CP_ME0_PIPE0_PRIORITY[0], sizeof(CP_ME0_PIPE0_PRIORITY)/sizeof(CP_ME0_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING0_PRIORITY", REG_MMIO, 0x304d, &CP_RING0_PRIORITY[0], sizeof(CP_RING0_PRIORITY)/sizeof(CP_RING0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE1_PRIORITY", REG_MMIO, 0x304e, &CP_ME0_PIPE1_PRIORITY[0], sizeof(CP_ME0_PIPE1_PRIORITY)/sizeof(CP_ME0_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING1_PRIORITY", REG_MMIO, 0x304e, &CP_RING1_PRIORITY[0], sizeof(CP_RING1_PRIORITY)/sizeof(CP_RING1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE2_PRIORITY", REG_MMIO, 0x304f, &CP_ME0_PIPE2_PRIORITY[0], sizeof(CP_ME0_PIPE2_PRIORITY)/sizeof(CP_ME0_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING2_PRIORITY", REG_MMIO, 0x304f, &CP_RING2_PRIORITY[0], sizeof(CP_RING2_PRIORITY)/sizeof(CP_RING2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ENDIAN_SWAP", REG_MMIO, 0x3050, &CP_ENDIAN_SWAP[0], sizeof(CP_ENDIAN_SWAP)/sizeof(CP_ENDIAN_SWAP[0]), 0, 0 },
+	{ "mmCP_RB_VMID", REG_MMIO, 0x3051, &CP_RB_VMID[0], sizeof(CP_RB_VMID)/sizeof(CP_RB_VMID[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_ADDR", REG_MMIO, 0x3054, &CP_PFP_UCODE_ADDR[0], sizeof(CP_PFP_UCODE_ADDR)/sizeof(CP_PFP_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_DATA", REG_MMIO, 0x3055, &CP_PFP_UCODE_DATA[0], sizeof(CP_PFP_UCODE_DATA)/sizeof(CP_PFP_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_ME_RAM_RADDR", REG_MMIO, 0x3056, &CP_ME_RAM_RADDR[0], sizeof(CP_ME_RAM_RADDR)/sizeof(CP_ME_RAM_RADDR[0]), 0, 0 },
+	{ "mmCP_ME_RAM_WADDR", REG_MMIO, 0x3057, &CP_ME_RAM_WADDR[0], sizeof(CP_ME_RAM_WADDR)/sizeof(CP_ME_RAM_WADDR[0]), 0, 0 },
+	{ "mmCP_ME_RAM_DATA", REG_MMIO, 0x3058, &CP_ME_RAM_DATA[0], sizeof(CP_ME_RAM_DATA)/sizeof(CP_ME_RAM_DATA[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_ADDR", REG_MMIO, 0x305a, &CP_CE_UCODE_ADDR[0], sizeof(CP_CE_UCODE_ADDR)/sizeof(CP_CE_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_DATA", REG_MMIO, 0x305b, &CP_CE_UCODE_DATA[0], sizeof(CP_CE_UCODE_DATA)/sizeof(CP_CE_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_UCODE_ADDR", REG_MMIO, 0x305c, &CP_MEC_ME1_UCODE_ADDR[0], sizeof(CP_MEC_ME1_UCODE_ADDR)/sizeof(CP_MEC_ME1_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_UCODE_DATA", REG_MMIO, 0x305d, &CP_MEC_ME1_UCODE_DATA[0], sizeof(CP_MEC_ME1_UCODE_DATA)/sizeof(CP_MEC_ME1_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_UCODE_ADDR", REG_MMIO, 0x305e, &CP_MEC_ME2_UCODE_ADDR[0], sizeof(CP_MEC_ME2_UCODE_ADDR)/sizeof(CP_MEC_ME2_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_UCODE_DATA", REG_MMIO, 0x305f, &CP_MEC_ME2_UCODE_DATA[0], sizeof(CP_MEC_ME2_UCODE_DATA)/sizeof(CP_MEC_ME2_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_RB1_BASE", REG_MMIO, 0x3060, &CP_RB1_BASE[0], sizeof(CP_RB1_BASE)/sizeof(CP_RB1_BASE[0]), 0, 0 },
+	{ "mmCP_RB1_CNTL", REG_MMIO, 0x3061, &CP_RB1_CNTL[0], sizeof(CP_RB1_CNTL)/sizeof(CP_RB1_CNTL[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR", REG_MMIO, 0x3062, &CP_RB1_RPTR_ADDR[0], sizeof(CP_RB1_RPTR_ADDR)/sizeof(CP_RB1_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR_HI", REG_MMIO, 0x3063, &CP_RB1_RPTR_ADDR_HI[0], sizeof(CP_RB1_RPTR_ADDR_HI)/sizeof(CP_RB1_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB1_WPTR", REG_MMIO, 0x3064, &CP_RB1_WPTR[0], sizeof(CP_RB1_WPTR)/sizeof(CP_RB1_WPTR[0]), 0, 0 },
+	{ "mmCP_RB2_BASE", REG_MMIO, 0x3065, &CP_RB2_BASE[0], sizeof(CP_RB2_BASE)/sizeof(CP_RB2_BASE[0]), 0, 0 },
+	{ "mmCP_RB2_CNTL", REG_MMIO, 0x3066, &CP_RB2_CNTL[0], sizeof(CP_RB2_CNTL)/sizeof(CP_RB2_CNTL[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR", REG_MMIO, 0x3067, &CP_RB2_RPTR_ADDR[0], sizeof(CP_RB2_RPTR_ADDR)/sizeof(CP_RB2_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR_HI", REG_MMIO, 0x3068, &CP_RB2_RPTR_ADDR_HI[0], sizeof(CP_RB2_RPTR_ADDR_HI)/sizeof(CP_RB2_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB2_WPTR", REG_MMIO, 0x3069, &CP_RB2_WPTR[0], sizeof(CP_RB2_WPTR)/sizeof(CP_RB2_WPTR[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING0", REG_MMIO, 0x306a, &CP_INT_CNTL_RING0[0], sizeof(CP_INT_CNTL_RING0)/sizeof(CP_INT_CNTL_RING0[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING1", REG_MMIO, 0x306b, &CP_INT_CNTL_RING1[0], sizeof(CP_INT_CNTL_RING1)/sizeof(CP_INT_CNTL_RING1[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING2", REG_MMIO, 0x306c, &CP_INT_CNTL_RING2[0], sizeof(CP_INT_CNTL_RING2)/sizeof(CP_INT_CNTL_RING2[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING0", REG_MMIO, 0x306d, &CP_INT_STATUS_RING0[0], sizeof(CP_INT_STATUS_RING0)/sizeof(CP_INT_STATUS_RING0[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING1", REG_MMIO, 0x306e, &CP_INT_STATUS_RING1[0], sizeof(CP_INT_STATUS_RING1)/sizeof(CP_INT_STATUS_RING1[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING2", REG_MMIO, 0x306f, &CP_INT_STATUS_RING2[0], sizeof(CP_INT_STATUS_RING2)/sizeof(CP_INT_STATUS_RING2[0]), 0, 0 },
+	{ "mmCP_PWR_CNTL", REG_MMIO, 0x3078, &CP_PWR_CNTL[0], sizeof(CP_PWR_CNTL)/sizeof(CP_PWR_CNTL[0]), 0, 0 },
+	{ "mmCP_MEM_SLP_CNTL", REG_MMIO, 0x3079, &CP_MEM_SLP_CNTL[0], sizeof(CP_MEM_SLP_CNTL)/sizeof(CP_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE", REG_MMIO, 0x307a, &CP_ECC_FIRSTOCCURRENCE[0], sizeof(CP_ECC_FIRSTOCCURRENCE)/sizeof(CP_ECC_FIRSTOCCURRENCE[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING0", REG_MMIO, 0x307b, &CP_ECC_FIRSTOCCURRENCE_RING0[0], sizeof(CP_ECC_FIRSTOCCURRENCE_RING0)/sizeof(CP_ECC_FIRSTOCCURRENCE_RING0[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING1", REG_MMIO, 0x307c, &CP_ECC_FIRSTOCCURRENCE_RING1[0], sizeof(CP_ECC_FIRSTOCCURRENCE_RING1)/sizeof(CP_ECC_FIRSTOCCURRENCE_RING1[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING2", REG_MMIO, 0x307d, &CP_ECC_FIRSTOCCURRENCE_RING2[0], sizeof(CP_ECC_FIRSTOCCURRENCE_RING2)/sizeof(CP_ECC_FIRSTOCCURRENCE_RING2[0]), 0, 0 },
+	{ "mmGB_EDC_MODE", REG_MMIO, 0x307e, &GB_EDC_MODE[0], sizeof(GB_EDC_MODE)/sizeof(GB_EDC_MODE[0]), 0, 0 },
+	{ "mmCP_CPF_DEBUG", REG_MMIO, 0x3080, NULL, 0, 0, 0 },
+	{ "mmCP_FETCHER_SOURCE", REG_MMIO, 0x3082, &CP_FETCHER_SOURCE[0], sizeof(CP_FETCHER_SOURCE)/sizeof(CP_FETCHER_SOURCE[0]), 0, 0 },
+	{ "mmCP_PQ_WPTR_POLL_CNTL", REG_MMIO, 0x3083, &CP_PQ_WPTR_POLL_CNTL[0], sizeof(CP_PQ_WPTR_POLL_CNTL)/sizeof(CP_PQ_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_PQ_WPTR_POLL_CNTL1", REG_MMIO, 0x3084, &CP_PQ_WPTR_POLL_CNTL1[0], sizeof(CP_PQ_WPTR_POLL_CNTL1)/sizeof(CP_PQ_WPTR_POLL_CNTL1[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_INT_CNTL", REG_MMIO, 0x3085, &CP_ME1_PIPE0_INT_CNTL[0], sizeof(CP_ME1_PIPE0_INT_CNTL)/sizeof(CP_ME1_PIPE0_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_INT_CNTL", REG_MMIO, 0x3086, &CP_ME1_PIPE1_INT_CNTL[0], sizeof(CP_ME1_PIPE1_INT_CNTL)/sizeof(CP_ME1_PIPE1_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_INT_CNTL", REG_MMIO, 0x3087, &CP_ME1_PIPE2_INT_CNTL[0], sizeof(CP_ME1_PIPE2_INT_CNTL)/sizeof(CP_ME1_PIPE2_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_INT_CNTL", REG_MMIO, 0x3088, &CP_ME1_PIPE3_INT_CNTL[0], sizeof(CP_ME1_PIPE3_INT_CNTL)/sizeof(CP_ME1_PIPE3_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_INT_CNTL", REG_MMIO, 0x3089, &CP_ME2_PIPE0_INT_CNTL[0], sizeof(CP_ME2_PIPE0_INT_CNTL)/sizeof(CP_ME2_PIPE0_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_INT_CNTL", REG_MMIO, 0x308a, &CP_ME2_PIPE1_INT_CNTL[0], sizeof(CP_ME2_PIPE1_INT_CNTL)/sizeof(CP_ME2_PIPE1_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_INT_CNTL", REG_MMIO, 0x308b, &CP_ME2_PIPE2_INT_CNTL[0], sizeof(CP_ME2_PIPE2_INT_CNTL)/sizeof(CP_ME2_PIPE2_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_INT_CNTL", REG_MMIO, 0x308c, &CP_ME2_PIPE3_INT_CNTL[0], sizeof(CP_ME2_PIPE3_INT_CNTL)/sizeof(CP_ME2_PIPE3_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_INT_STATUS", REG_MMIO, 0x308d, &CP_ME1_PIPE0_INT_STATUS[0], sizeof(CP_ME1_PIPE0_INT_STATUS)/sizeof(CP_ME1_PIPE0_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_INT_STATUS", REG_MMIO, 0x308e, &CP_ME1_PIPE1_INT_STATUS[0], sizeof(CP_ME1_PIPE1_INT_STATUS)/sizeof(CP_ME1_PIPE1_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_INT_STATUS", REG_MMIO, 0x308f, &CP_ME1_PIPE2_INT_STATUS[0], sizeof(CP_ME1_PIPE2_INT_STATUS)/sizeof(CP_ME1_PIPE2_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_INT_STATUS", REG_MMIO, 0x3090, &CP_ME1_PIPE3_INT_STATUS[0], sizeof(CP_ME1_PIPE3_INT_STATUS)/sizeof(CP_ME1_PIPE3_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_INT_STATUS", REG_MMIO, 0x3091, &CP_ME2_PIPE0_INT_STATUS[0], sizeof(CP_ME2_PIPE0_INT_STATUS)/sizeof(CP_ME2_PIPE0_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_INT_STATUS", REG_MMIO, 0x3092, &CP_ME2_PIPE1_INT_STATUS[0], sizeof(CP_ME2_PIPE1_INT_STATUS)/sizeof(CP_ME2_PIPE1_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_INT_STATUS", REG_MMIO, 0x3093, &CP_ME2_PIPE2_INT_STATUS[0], sizeof(CP_ME2_PIPE2_INT_STATUS)/sizeof(CP_ME2_PIPE2_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_INT_STATUS", REG_MMIO, 0x3094, &CP_ME2_PIPE3_INT_STATUS[0], sizeof(CP_ME2_PIPE3_INT_STATUS)/sizeof(CP_ME2_PIPE3_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_INT_STAT_DEBUG", REG_MMIO, 0x3095, &CP_ME1_INT_STAT_DEBUG[0], sizeof(CP_ME1_INT_STAT_DEBUG)/sizeof(CP_ME1_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCP_ME2_INT_STAT_DEBUG", REG_MMIO, 0x3096, &CP_ME2_INT_STAT_DEBUG[0], sizeof(CP_ME2_INT_STAT_DEBUG)/sizeof(CP_ME2_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCC_GC_EDC_CONFIG", REG_MMIO, 0x3098, &CC_GC_EDC_CONFIG[0], sizeof(CC_GC_EDC_CONFIG)/sizeof(CC_GC_EDC_CONFIG[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE_PRIORITY_CNTS", REG_MMIO, 0x3099, &CP_ME1_PIPE_PRIORITY_CNTS[0], sizeof(CP_ME1_PIPE_PRIORITY_CNTS)/sizeof(CP_ME1_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_PRIORITY", REG_MMIO, 0x309a, &CP_ME1_PIPE0_PRIORITY[0], sizeof(CP_ME1_PIPE0_PRIORITY)/sizeof(CP_ME1_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_PRIORITY", REG_MMIO, 0x309b, &CP_ME1_PIPE1_PRIORITY[0], sizeof(CP_ME1_PIPE1_PRIORITY)/sizeof(CP_ME1_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_PRIORITY", REG_MMIO, 0x309c, &CP_ME1_PIPE2_PRIORITY[0], sizeof(CP_ME1_PIPE2_PRIORITY)/sizeof(CP_ME1_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_PRIORITY", REG_MMIO, 0x309d, &CP_ME1_PIPE3_PRIORITY[0], sizeof(CP_ME1_PIPE3_PRIORITY)/sizeof(CP_ME1_PIPE3_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE_PRIORITY_CNTS", REG_MMIO, 0x309e, &CP_ME2_PIPE_PRIORITY_CNTS[0], sizeof(CP_ME2_PIPE_PRIORITY_CNTS)/sizeof(CP_ME2_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_PRIORITY", REG_MMIO, 0x309f, &CP_ME2_PIPE0_PRIORITY[0], sizeof(CP_ME2_PIPE0_PRIORITY)/sizeof(CP_ME2_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_PRIORITY", REG_MMIO, 0x30a0, &CP_ME2_PIPE1_PRIORITY[0], sizeof(CP_ME2_PIPE1_PRIORITY)/sizeof(CP_ME2_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_PRIORITY", REG_MMIO, 0x30a1, &CP_ME2_PIPE2_PRIORITY[0], sizeof(CP_ME2_PIPE2_PRIORITY)/sizeof(CP_ME2_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_PRIORITY", REG_MMIO, 0x30a2, &CP_ME2_PIPE3_PRIORITY[0], sizeof(CP_ME2_PIPE3_PRIORITY)/sizeof(CP_ME2_PIPE3_PRIORITY[0]), 0, 0 },
+	{ "mmCP_CE_PRGRM_CNTR_START", REG_MMIO, 0x30a3, &CP_CE_PRGRM_CNTR_START[0], sizeof(CP_CE_PRGRM_CNTR_START)/sizeof(CP_CE_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_PFP_PRGRM_CNTR_START", REG_MMIO, 0x30a4, &CP_PFP_PRGRM_CNTR_START[0], sizeof(CP_PFP_PRGRM_CNTR_START)/sizeof(CP_PFP_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_ME_PRGRM_CNTR_START", REG_MMIO, 0x30a5, &CP_ME_PRGRM_CNTR_START[0], sizeof(CP_ME_PRGRM_CNTR_START)/sizeof(CP_ME_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_MEC1_PRGRM_CNTR_START", REG_MMIO, 0x30a6, &CP_MEC1_PRGRM_CNTR_START[0], sizeof(CP_MEC1_PRGRM_CNTR_START)/sizeof(CP_MEC1_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_MEC2_PRGRM_CNTR_START", REG_MMIO, 0x30a7, &CP_MEC2_PRGRM_CNTR_START[0], sizeof(CP_MEC2_PRGRM_CNTR_START)/sizeof(CP_MEC2_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_CE_INTR_ROUTINE_START", REG_MMIO, 0x30a8, &CP_CE_INTR_ROUTINE_START[0], sizeof(CP_CE_INTR_ROUTINE_START)/sizeof(CP_CE_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_PFP_INTR_ROUTINE_START", REG_MMIO, 0x30a9, &CP_PFP_INTR_ROUTINE_START[0], sizeof(CP_PFP_INTR_ROUTINE_START)/sizeof(CP_PFP_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_ME_INTR_ROUTINE_START", REG_MMIO, 0x30aa, &CP_ME_INTR_ROUTINE_START[0], sizeof(CP_ME_INTR_ROUTINE_START)/sizeof(CP_ME_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_MEC1_INTR_ROUTINE_START", REG_MMIO, 0x30ab, &CP_MEC1_INTR_ROUTINE_START[0], sizeof(CP_MEC1_INTR_ROUTINE_START)/sizeof(CP_MEC1_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_MEC2_INTR_ROUTINE_START", REG_MMIO, 0x30ac, &CP_MEC2_INTR_ROUTINE_START[0], sizeof(CP_MEC2_INTR_ROUTINE_START)/sizeof(CP_MEC2_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_CONTEXT_CNTL", REG_MMIO, 0x30ad, &CP_CONTEXT_CNTL[0], sizeof(CP_CONTEXT_CNTL)/sizeof(CP_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmCP_MAX_CONTEXT", REG_MMIO, 0x30ae, &CP_MAX_CONTEXT[0], sizeof(CP_MAX_CONTEXT)/sizeof(CP_MAX_CONTEXT[0]), 0, 0 },
+	{ "mmCP_IQ_WAIT_TIME1", REG_MMIO, 0x30af, &CP_IQ_WAIT_TIME1[0], sizeof(CP_IQ_WAIT_TIME1)/sizeof(CP_IQ_WAIT_TIME1[0]), 0, 0 },
+	{ "mmCP_IQ_WAIT_TIME2", REG_MMIO, 0x30b0, &CP_IQ_WAIT_TIME2[0], sizeof(CP_IQ_WAIT_TIME2)/sizeof(CP_IQ_WAIT_TIME2[0]), 0, 0 },
+	{ "mmCP_RB0_BASE_HI", REG_MMIO, 0x30b1, &CP_RB0_BASE_HI[0], sizeof(CP_RB0_BASE_HI)/sizeof(CP_RB0_BASE_HI[0]), 0, 0 },
+	{ "mmCP_RB1_BASE_HI", REG_MMIO, 0x30b2, &CP_RB1_BASE_HI[0], sizeof(CP_RB1_BASE_HI)/sizeof(CP_RB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_VMID_RESET", REG_MMIO, 0x30b3, &CP_VMID_RESET[0], sizeof(CP_VMID_RESET)/sizeof(CP_VMID_RESET[0]), 0, 0 },
+	{ "mmCPC_INT_CNTL", REG_MMIO, 0x30b4, &CPC_INT_CNTL[0], sizeof(CPC_INT_CNTL)/sizeof(CPC_INT_CNTL[0]), 0, 0 },
+	{ "mmCPC_INT_STATUS", REG_MMIO, 0x30b5, &CPC_INT_STATUS[0], sizeof(CPC_INT_STATUS)/sizeof(CPC_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_VMID_PREEMPT", REG_MMIO, 0x30b6, &CP_VMID_PREEMPT[0], sizeof(CP_VMID_PREEMPT)/sizeof(CP_VMID_PREEMPT[0]), 0, 0 },
+	{ "mmCP_PQ_STATUS", REG_MMIO, 0x30b8, &CP_PQ_STATUS[0], sizeof(CP_PQ_STATUS)/sizeof(CP_PQ_STATUS[0]), 0, 0 },
+	{ "mmRLC_CNTL", REG_MMIO, 0x30c0, &RLC_CNTL[0], sizeof(RLC_CNTL)/sizeof(RLC_CNTL[0]), 0, 0 },
+	{ "mmRLC_DEBUG_SELECT", REG_MMIO, 0x30c1, &RLC_DEBUG_SELECT[0], sizeof(RLC_DEBUG_SELECT)/sizeof(RLC_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_DEBUG", REG_MMIO, 0x30c2, &RLC_DEBUG[0], sizeof(RLC_DEBUG)/sizeof(RLC_DEBUG[0]), 0, 0 },
+	{ "mmRLC_MC_CNTL", REG_MMIO, 0x30c3, &RLC_MC_CNTL[0], sizeof(RLC_MC_CNTL)/sizeof(RLC_MC_CNTL[0]), 0, 0 },
+	{ "mmRLC_STAT", REG_MMIO, 0x30c4, &RLC_STAT[0], sizeof(RLC_STAT)/sizeof(RLC_STAT[0]), 0, 0 },
+	{ "mmRLC_SOFT_RESET_GPU", REG_MMIO, 0x30c5, &RLC_SOFT_RESET_GPU[0], sizeof(RLC_SOFT_RESET_GPU)/sizeof(RLC_SOFT_RESET_GPU[0]), 0, 0 },
+	{ "mmRLC_MEM_SLP_CNTL", REG_MMIO, 0x30c6, &RLC_MEM_SLP_CNTL[0], sizeof(RLC_MEM_SLP_CNTL)/sizeof(RLC_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_MAX", REG_MMIO, 0x30d2, &RLC_LB_CNTR_MAX[0], sizeof(RLC_LB_CNTR_MAX)/sizeof(RLC_LB_CNTR_MAX[0]), 0, 0 },
+	{ "mmRLC_LB_CNTL", REG_MMIO, 0x30d9, &RLC_LB_CNTL[0], sizeof(RLC_LB_CNTL)/sizeof(RLC_LB_CNTL[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_INIT", REG_MMIO, 0x30db, &RLC_LB_CNTR_INIT[0], sizeof(RLC_LB_CNTR_INIT)/sizeof(RLC_LB_CNTR_INIT[0]), 0, 0 },
+	{ "mmRLC_LOAD_BALANCE_CNTR", REG_MMIO, 0x30dc, &RLC_LOAD_BALANCE_CNTR[0], sizeof(RLC_LOAD_BALANCE_CNTR)/sizeof(RLC_LOAD_BALANCE_CNTR[0]), 0, 0 },
+	{ "mmRLC_SAVE_AND_RESTORE_BASE", REG_MMIO, 0x30dd, &RLC_SAVE_AND_RESTORE_BASE[0], sizeof(RLC_SAVE_AND_RESTORE_BASE)/sizeof(RLC_SAVE_AND_RESTORE_BASE[0]), 0, 0 },
+	{ "mmRLC_DRIVER_CPDMA_STATUS", REG_MMIO, 0x30de, &RLC_DRIVER_CPDMA_STATUS[0], sizeof(RLC_DRIVER_CPDMA_STATUS)/sizeof(RLC_DRIVER_CPDMA_STATUS[0]), 0, 0 },
+	{ "mmRLC_JUMP_TABLE_RESTORE", REG_MMIO, 0x30de, &RLC_JUMP_TABLE_RESTORE[0], sizeof(RLC_JUMP_TABLE_RESTORE)/sizeof(RLC_JUMP_TABLE_RESTORE[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY_2", REG_MMIO, 0x30df, &RLC_PG_DELAY_2[0], sizeof(RLC_PG_DELAY_2)/sizeof(RLC_PG_DELAY_2[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG_SELECT", REG_MMIO, 0x30e0, &RLC_GPM_DEBUG_SELECT[0], sizeof(RLC_GPM_DEBUG_SELECT)/sizeof(RLC_GPM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG", REG_MMIO, 0x30e1, &RLC_GPM_DEBUG[0], sizeof(RLC_GPM_DEBUG)/sizeof(RLC_GPM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_GPM_UCODE_ADDR", REG_MMIO, 0x30e2, &RLC_GPM_UCODE_ADDR[0], sizeof(RLC_GPM_UCODE_ADDR)/sizeof(RLC_GPM_UCODE_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_UCODE_DATA", REG_MMIO, 0x30e3, &RLC_GPM_UCODE_DATA[0], sizeof(RLC_GPM_UCODE_DATA)/sizeof(RLC_GPM_UCODE_DATA[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_LSB", REG_MMIO, 0x30e4, &RLC_GPU_CLOCK_COUNT_LSB[0], sizeof(RLC_GPU_CLOCK_COUNT_LSB)/sizeof(RLC_GPU_CLOCK_COUNT_LSB[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_MSB", REG_MMIO, 0x30e5, &RLC_GPU_CLOCK_COUNT_MSB[0], sizeof(RLC_GPU_CLOCK_COUNT_MSB)/sizeof(RLC_GPU_CLOCK_COUNT_MSB[0]), 0, 0 },
+	{ "mmRLC_CAPTURE_GPU_CLOCK_COUNT", REG_MMIO, 0x30e6, &RLC_CAPTURE_GPU_CLOCK_COUNT[0], sizeof(RLC_CAPTURE_GPU_CLOCK_COUNT)/sizeof(RLC_CAPTURE_GPU_CLOCK_COUNT[0]), 0, 0 },
+	{ "mmRLC_UCODE_CNTL", REG_MMIO, 0x30e7, &RLC_UCODE_CNTL[0], sizeof(RLC_UCODE_CNTL)/sizeof(RLC_UCODE_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPM_STAT", REG_MMIO, 0x3100, &RLC_GPM_STAT[0], sizeof(RLC_GPM_STAT)/sizeof(RLC_GPM_STAT[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32_RES_SEL", REG_MMIO, 0x3101, &RLC_GPU_CLOCK_32_RES_SEL[0], sizeof(RLC_GPU_CLOCK_32_RES_SEL)/sizeof(RLC_GPU_CLOCK_32_RES_SEL[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32", REG_MMIO, 0x3102, &RLC_GPU_CLOCK_32[0], sizeof(RLC_GPU_CLOCK_32)/sizeof(RLC_GPU_CLOCK_32[0]), 0, 0 },
+	{ "mmRLC_PG_CNTL", REG_MMIO, 0x3103, &RLC_PG_CNTL[0], sizeof(RLC_PG_CNTL)/sizeof(RLC_PG_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_PRIORITY", REG_MMIO, 0x3104, &RLC_GPM_THREAD_PRIORITY[0], sizeof(RLC_GPM_THREAD_PRIORITY)/sizeof(RLC_GPM_THREAD_PRIORITY[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_ENABLE", REG_MMIO, 0x3105, &RLC_GPM_THREAD_ENABLE[0], sizeof(RLC_GPM_THREAD_ENABLE)/sizeof(RLC_GPM_THREAD_ENABLE[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD0", REG_MMIO, 0x3106, &RLC_GPM_VMID_THREAD0[0], sizeof(RLC_GPM_VMID_THREAD0)/sizeof(RLC_GPM_VMID_THREAD0[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD1", REG_MMIO, 0x3107, &RLC_GPM_VMID_THREAD1[0], sizeof(RLC_GPM_VMID_THREAD1)/sizeof(RLC_GPM_VMID_THREAD1[0]), 0, 0 },
+	{ "mmRLC_CGTT_MGCG_OVERRIDE", REG_MMIO, 0x3108, &RLC_CGTT_MGCG_OVERRIDE[0], sizeof(RLC_CGTT_MGCG_OVERRIDE)/sizeof(RLC_CGTT_MGCG_OVERRIDE[0]), 0, 0 },
+	{ "mmRLC_CGCG_CGLS_CTRL", REG_MMIO, 0x3109, &RLC_CGCG_CGLS_CTRL[0], sizeof(RLC_CGCG_CGLS_CTRL)/sizeof(RLC_CGCG_CGLS_CTRL[0]), 0, 0 },
+	{ "mmRLC_CGCG_RAMP_CTRL", REG_MMIO, 0x310a, &RLC_CGCG_RAMP_CTRL[0], sizeof(RLC_CGCG_RAMP_CTRL)/sizeof(RLC_CGCG_RAMP_CTRL[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_STATUS", REG_MMIO, 0x310b, &RLC_DYN_PG_STATUS[0], sizeof(RLC_DYN_PG_STATUS)/sizeof(RLC_DYN_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_REQUEST", REG_MMIO, 0x310c, &RLC_DYN_PG_REQUEST[0], sizeof(RLC_DYN_PG_REQUEST)/sizeof(RLC_DYN_PG_REQUEST[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY", REG_MMIO, 0x310d, &RLC_PG_DELAY[0], sizeof(RLC_PG_DELAY)/sizeof(RLC_PG_DELAY[0]), 0, 0 },
+	{ "mmRLC_CU_STATUS", REG_MMIO, 0x310e, &RLC_CU_STATUS[0], sizeof(RLC_CU_STATUS)/sizeof(RLC_CU_STATUS[0]), 0, 0 },
+	{ "mmRLC_LB_INIT_CU_MASK", REG_MMIO, 0x310f, &RLC_LB_INIT_CU_MASK[0], sizeof(RLC_LB_INIT_CU_MASK)/sizeof(RLC_LB_INIT_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_ALWAYS_ACTIVE_CU_MASK", REG_MMIO, 0x3110, &RLC_LB_ALWAYS_ACTIVE_CU_MASK[0], sizeof(RLC_LB_ALWAYS_ACTIVE_CU_MASK)/sizeof(RLC_LB_ALWAYS_ACTIVE_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_PARAMS", REG_MMIO, 0x3111, &RLC_LB_PARAMS[0], sizeof(RLC_LB_PARAMS)/sizeof(RLC_LB_PARAMS[0]), 0, 0 },
+	{ "mmRLC_THREAD1_DELAY", REG_MMIO, 0x3112, &RLC_THREAD1_DELAY[0], sizeof(RLC_THREAD1_DELAY)/sizeof(RLC_THREAD1_DELAY[0]), 0, 0 },
+	{ "mmRLC_PG_ALWAYS_ON_CU_MASK", REG_MMIO, 0x3113, &RLC_PG_ALWAYS_ON_CU_MASK[0], sizeof(RLC_PG_ALWAYS_ON_CU_MASK)/sizeof(RLC_PG_ALWAYS_ON_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_MAX_PG_CU", REG_MMIO, 0x3114, &RLC_MAX_PG_CU[0], sizeof(RLC_MAX_PG_CU)/sizeof(RLC_MAX_PG_CU[0]), 0, 0 },
+	{ "mmRLC_AUTO_PG_CTRL", REG_MMIO, 0x3115, &RLC_AUTO_PG_CTRL[0], sizeof(RLC_AUTO_PG_CTRL)/sizeof(RLC_AUTO_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_GRBM_REG_SAVE_CTRL", REG_MMIO, 0x3116, &RLC_SMU_GRBM_REG_SAVE_CTRL[0], sizeof(RLC_SMU_GRBM_REG_SAVE_CTRL)/sizeof(RLC_SMU_GRBM_REG_SAVE_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_PG_CTRL", REG_MMIO, 0x3117, &RLC_SMU_PG_CTRL[0], sizeof(RLC_SMU_PG_CTRL)/sizeof(RLC_SMU_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_PG_WAKE_UP_CTRL", REG_MMIO, 0x3118, &RLC_SMU_PG_WAKE_UP_CTRL[0], sizeof(RLC_SMU_PG_WAKE_UP_CTRL)/sizeof(RLC_SMU_PG_WAKE_UP_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_MASTER_INDEX", REG_MMIO, 0x3119, &RLC_SERDES_RD_MASTER_INDEX[0], sizeof(RLC_SERDES_RD_MASTER_INDEX)/sizeof(RLC_SERDES_RD_MASTER_INDEX[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_0", REG_MMIO, 0x311a, &RLC_SERDES_RD_DATA_0[0], sizeof(RLC_SERDES_RD_DATA_0)/sizeof(RLC_SERDES_RD_DATA_0[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_1", REG_MMIO, 0x311b, &RLC_SERDES_RD_DATA_1[0], sizeof(RLC_SERDES_RD_DATA_1)/sizeof(RLC_SERDES_RD_DATA_1[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_2", REG_MMIO, 0x311c, &RLC_SERDES_RD_DATA_2[0], sizeof(RLC_SERDES_RD_DATA_2)/sizeof(RLC_SERDES_RD_DATA_2[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_CU_MASTER_MASK", REG_MMIO, 0x311d, &RLC_SERDES_WR_CU_MASTER_MASK[0], sizeof(RLC_SERDES_WR_CU_MASTER_MASK)/sizeof(RLC_SERDES_WR_CU_MASTER_MASK[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_NONCU_MASTER_MASK", REG_MMIO, 0x311e, &RLC_SERDES_WR_NONCU_MASTER_MASK[0], sizeof(RLC_SERDES_WR_NONCU_MASTER_MASK)/sizeof(RLC_SERDES_WR_NONCU_MASTER_MASK[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_CTRL", REG_MMIO, 0x311f, &RLC_SERDES_WR_CTRL[0], sizeof(RLC_SERDES_WR_CTRL)/sizeof(RLC_SERDES_WR_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_DATA", REG_MMIO, 0x3120, &RLC_SERDES_WR_DATA[0], sizeof(RLC_SERDES_WR_DATA)/sizeof(RLC_SERDES_WR_DATA[0]), 0, 0 },
+	{ "mmRLC_SERDES_CU_MASTER_BUSY", REG_MMIO, 0x3121, &RLC_SERDES_CU_MASTER_BUSY[0], sizeof(RLC_SERDES_CU_MASTER_BUSY)/sizeof(RLC_SERDES_CU_MASTER_BUSY[0]), 0, 0 },
+	{ "mmRLC_SERDES_NONCU_MASTER_BUSY", REG_MMIO, 0x3122, &RLC_SERDES_NONCU_MASTER_BUSY[0], sizeof(RLC_SERDES_NONCU_MASTER_BUSY)/sizeof(RLC_SERDES_NONCU_MASTER_BUSY[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_0", REG_MMIO, 0x3123, &RLC_GPM_GENERAL_0[0], sizeof(RLC_GPM_GENERAL_0)/sizeof(RLC_GPM_GENERAL_0[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_1", REG_MMIO, 0x3124, &RLC_GPM_GENERAL_1[0], sizeof(RLC_GPM_GENERAL_1)/sizeof(RLC_GPM_GENERAL_1[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_2", REG_MMIO, 0x3125, &RLC_GPM_GENERAL_2[0], sizeof(RLC_GPM_GENERAL_2)/sizeof(RLC_GPM_GENERAL_2[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_3", REG_MMIO, 0x3126, &RLC_GPM_GENERAL_3[0], sizeof(RLC_GPM_GENERAL_3)/sizeof(RLC_GPM_GENERAL_3[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_4", REG_MMIO, 0x3127, &RLC_GPM_GENERAL_4[0], sizeof(RLC_GPM_GENERAL_4)/sizeof(RLC_GPM_GENERAL_4[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_5", REG_MMIO, 0x3128, &RLC_GPM_GENERAL_5[0], sizeof(RLC_GPM_GENERAL_5)/sizeof(RLC_GPM_GENERAL_5[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_6", REG_MMIO, 0x3129, &RLC_GPM_GENERAL_6[0], sizeof(RLC_GPM_GENERAL_6)/sizeof(RLC_GPM_GENERAL_6[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_7", REG_MMIO, 0x312a, &RLC_GPM_GENERAL_7[0], sizeof(RLC_GPM_GENERAL_7)/sizeof(RLC_GPM_GENERAL_7[0]), 0, 0 },
+	{ "mmRLC_GPM_CU_PD_TIMEOUT", REG_MMIO, 0x312b, &RLC_GPM_CU_PD_TIMEOUT[0], sizeof(RLC_GPM_CU_PD_TIMEOUT)/sizeof(RLC_GPM_CU_PD_TIMEOUT[0]), 0, 0 },
+	{ "mmRLC_GPM_SCRATCH_ADDR", REG_MMIO, 0x312c, &RLC_GPM_SCRATCH_ADDR[0], sizeof(RLC_GPM_SCRATCH_ADDR)/sizeof(RLC_GPM_SCRATCH_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_SCRATCH_DATA", REG_MMIO, 0x312d, &RLC_GPM_SCRATCH_DATA[0], sizeof(RLC_GPM_SCRATCH_DATA)/sizeof(RLC_GPM_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmRLC_STATIC_PG_STATUS", REG_MMIO, 0x312e, &RLC_STATIC_PG_STATUS[0], sizeof(RLC_STATIC_PG_STATUS)/sizeof(RLC_STATIC_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_GPM_PERF_COUNT_0", REG_MMIO, 0x312f, &RLC_GPM_PERF_COUNT_0[0], sizeof(RLC_GPM_PERF_COUNT_0)/sizeof(RLC_GPM_PERF_COUNT_0[0]), 0, 0 },
+	{ "mmRLC_GPM_PERF_COUNT_1", REG_MMIO, 0x3130, &RLC_GPM_PERF_COUNT_1[0], sizeof(RLC_GPM_PERF_COUNT_1)/sizeof(RLC_GPM_PERF_COUNT_1[0]), 0, 0 },
+	{ "mmRLC_SPM_VMID", REG_MMIO, 0x3131, &RLC_SPM_VMID[0], sizeof(RLC_SPM_VMID)/sizeof(RLC_SPM_VMID[0]), 0, 0 },
+	{ "mmRLC_SPM_INT_CNTL", REG_MMIO, 0x3132, &RLC_SPM_INT_CNTL[0], sizeof(RLC_SPM_INT_CNTL)/sizeof(RLC_SPM_INT_CNTL[0]), 0, 0 },
+	{ "mmRLC_SPM_INT_STATUS", REG_MMIO, 0x3133, &RLC_SPM_INT_STATUS[0], sizeof(RLC_SPM_INT_STATUS)/sizeof(RLC_SPM_INT_STATUS[0]), 0, 0 },
+	{ "mmRLC_SPM_DEBUG_SELECT", REG_MMIO, 0x3134, &RLC_SPM_DEBUG_SELECT[0], sizeof(RLC_SPM_DEBUG_SELECT)/sizeof(RLC_SPM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_SPM_DEBUG", REG_MMIO, 0x3135, &RLC_SPM_DEBUG[0], sizeof(RLC_SPM_DEBUG)/sizeof(RLC_SPM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_ADDR", REG_MMIO, 0x3136, &RLC_GPM_LOG_ADDR[0], sizeof(RLC_GPM_LOG_ADDR)/sizeof(RLC_GPM_LOG_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_SIZE", REG_MMIO, 0x3137, &RLC_GPM_LOG_SIZE[0], sizeof(RLC_GPM_LOG_SIZE)/sizeof(RLC_GPM_LOG_SIZE[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_CONT", REG_MMIO, 0x3138, &RLC_GPM_LOG_CONT[0], sizeof(RLC_GPM_LOG_CONT)/sizeof(RLC_GPM_LOG_CONT[0]), 0, 0 },
+	{ "mmRLC_GPR_REG1", REG_MMIO, 0x3139, &RLC_GPR_REG1[0], sizeof(RLC_GPR_REG1)/sizeof(RLC_GPR_REG1[0]), 0, 0 },
+	{ "mmRLC_SAFE_MODE", REG_MMIO, 0x313a, &RLC_SAFE_MODE[0], sizeof(RLC_SAFE_MODE)/sizeof(RLC_SAFE_MODE[0]), 0, 0 },
+	{ "mmRLC_GPR_REG2", REG_MMIO, 0x313a, &RLC_GPR_REG2[0], sizeof(RLC_GPR_REG2)/sizeof(RLC_GPR_REG2[0]), 0, 0 },
+	{ "mmSPI_ARB_PRIORITY", REG_MMIO, 0x31c0, &SPI_ARB_PRIORITY[0], sizeof(SPI_ARB_PRIORITY)/sizeof(SPI_ARB_PRIORITY[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_0", REG_MMIO, 0x31c1, &SPI_ARB_CYCLES_0[0], sizeof(SPI_ARB_CYCLES_0)/sizeof(SPI_ARB_CYCLES_0[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_1", REG_MMIO, 0x31c2, &SPI_ARB_CYCLES_1[0], sizeof(SPI_ARB_CYCLES_1)/sizeof(SPI_ARB_CYCLES_1[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_GFX", REG_MMIO, 0x31c3, &SPI_CDBG_SYS_GFX[0], sizeof(SPI_CDBG_SYS_GFX)/sizeof(SPI_CDBG_SYS_GFX[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_HP3D", REG_MMIO, 0x31c4, &SPI_CDBG_SYS_HP3D[0], sizeof(SPI_CDBG_SYS_HP3D)/sizeof(SPI_CDBG_SYS_HP3D[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_CS0", REG_MMIO, 0x31c5, &SPI_CDBG_SYS_CS0[0], sizeof(SPI_CDBG_SYS_CS0)/sizeof(SPI_CDBG_SYS_CS0[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_CS1", REG_MMIO, 0x31c6, &SPI_CDBG_SYS_CS1[0], sizeof(SPI_CDBG_SYS_CS1)/sizeof(SPI_CDBG_SYS_CS1[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_GFX", REG_MMIO, 0x31c7, &SPI_WCL_PIPE_PERCENT_GFX[0], sizeof(SPI_WCL_PIPE_PERCENT_GFX)/sizeof(SPI_WCL_PIPE_PERCENT_GFX[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_HP3D", REG_MMIO, 0x31c8, &SPI_WCL_PIPE_PERCENT_HP3D[0], sizeof(SPI_WCL_PIPE_PERCENT_HP3D)/sizeof(SPI_WCL_PIPE_PERCENT_HP3D[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS0", REG_MMIO, 0x31c9, &SPI_WCL_PIPE_PERCENT_CS0[0], sizeof(SPI_WCL_PIPE_PERCENT_CS0)/sizeof(SPI_WCL_PIPE_PERCENT_CS0[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS1", REG_MMIO, 0x31ca, &SPI_WCL_PIPE_PERCENT_CS1[0], sizeof(SPI_WCL_PIPE_PERCENT_CS1)/sizeof(SPI_WCL_PIPE_PERCENT_CS1[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS2", REG_MMIO, 0x31cb, &SPI_WCL_PIPE_PERCENT_CS2[0], sizeof(SPI_WCL_PIPE_PERCENT_CS2)/sizeof(SPI_WCL_PIPE_PERCENT_CS2[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS3", REG_MMIO, 0x31cc, &SPI_WCL_PIPE_PERCENT_CS3[0], sizeof(SPI_WCL_PIPE_PERCENT_CS3)/sizeof(SPI_WCL_PIPE_PERCENT_CS3[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS4", REG_MMIO, 0x31cd, &SPI_WCL_PIPE_PERCENT_CS4[0], sizeof(SPI_WCL_PIPE_PERCENT_CS4)/sizeof(SPI_WCL_PIPE_PERCENT_CS4[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS5", REG_MMIO, 0x31ce, &SPI_WCL_PIPE_PERCENT_CS5[0], sizeof(SPI_WCL_PIPE_PERCENT_CS5)/sizeof(SPI_WCL_PIPE_PERCENT_CS5[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS6", REG_MMIO, 0x31cf, &SPI_WCL_PIPE_PERCENT_CS6[0], sizeof(SPI_WCL_PIPE_PERCENT_CS6)/sizeof(SPI_WCL_PIPE_PERCENT_CS6[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS7", REG_MMIO, 0x31d0, &SPI_WCL_PIPE_PERCENT_CS7[0], sizeof(SPI_WCL_PIPE_PERCENT_CS7)/sizeof(SPI_WCL_PIPE_PERCENT_CS7[0]), 0, 0 },
+	{ "mmSPI_GDBG_WAVE_CNTL", REG_MMIO, 0x31d1, &SPI_GDBG_WAVE_CNTL[0], sizeof(SPI_GDBG_WAVE_CNTL)/sizeof(SPI_GDBG_WAVE_CNTL[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_CONFIG", REG_MMIO, 0x31d2, &SPI_GDBG_TRAP_CONFIG[0], sizeof(SPI_GDBG_TRAP_CONFIG)/sizeof(SPI_GDBG_TRAP_CONFIG[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_MASK", REG_MMIO, 0x31d3, &SPI_GDBG_TRAP_MASK[0], sizeof(SPI_GDBG_TRAP_MASK)/sizeof(SPI_GDBG_TRAP_MASK[0]), 0, 0 },
+	{ "mmSPI_GDBG_TBA_LO", REG_MMIO, 0x31d4, &SPI_GDBG_TBA_LO[0], sizeof(SPI_GDBG_TBA_LO)/sizeof(SPI_GDBG_TBA_LO[0]), 0, 0 },
+	{ "mmSPI_GDBG_TBA_HI", REG_MMIO, 0x31d5, &SPI_GDBG_TBA_HI[0], sizeof(SPI_GDBG_TBA_HI)/sizeof(SPI_GDBG_TBA_HI[0]), 0, 0 },
+	{ "mmSPI_GDBG_TMA_LO", REG_MMIO, 0x31d6, &SPI_GDBG_TMA_LO[0], sizeof(SPI_GDBG_TMA_LO)/sizeof(SPI_GDBG_TMA_LO[0]), 0, 0 },
+	{ "mmSPI_GDBG_TMA_HI", REG_MMIO, 0x31d7, &SPI_GDBG_TMA_HI[0], sizeof(SPI_GDBG_TMA_HI)/sizeof(SPI_GDBG_TMA_HI[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_DATA0", REG_MMIO, 0x31d8, &SPI_GDBG_TRAP_DATA0[0], sizeof(SPI_GDBG_TRAP_DATA0)/sizeof(SPI_GDBG_TRAP_DATA0[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_DATA1", REG_MMIO, 0x31d9, &SPI_GDBG_TRAP_DATA1[0], sizeof(SPI_GDBG_TRAP_DATA1)/sizeof(SPI_GDBG_TRAP_DATA1[0]), 0, 0 },
+	{ "mmSPI_RESET_DEBUG", REG_MMIO, 0x31da, &SPI_RESET_DEBUG[0], sizeof(SPI_RESET_DEBUG)/sizeof(SPI_RESET_DEBUG[0]), 0, 0 },
+	{ "mmSPI_COMPUTE_QUEUE_RESET", REG_MMIO, 0x31db, &SPI_COMPUTE_QUEUE_RESET[0], sizeof(SPI_COMPUTE_QUEUE_RESET)/sizeof(SPI_COMPUTE_QUEUE_RESET[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_0", REG_MMIO, 0x31dc, &SPI_RESOURCE_RESERVE_CU_0[0], sizeof(SPI_RESOURCE_RESERVE_CU_0)/sizeof(SPI_RESOURCE_RESERVE_CU_0[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_1", REG_MMIO, 0x31dd, &SPI_RESOURCE_RESERVE_CU_1[0], sizeof(SPI_RESOURCE_RESERVE_CU_1)/sizeof(SPI_RESOURCE_RESERVE_CU_1[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_2", REG_MMIO, 0x31de, &SPI_RESOURCE_RESERVE_CU_2[0], sizeof(SPI_RESOURCE_RESERVE_CU_2)/sizeof(SPI_RESOURCE_RESERVE_CU_2[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_3", REG_MMIO, 0x31df, &SPI_RESOURCE_RESERVE_CU_3[0], sizeof(SPI_RESOURCE_RESERVE_CU_3)/sizeof(SPI_RESOURCE_RESERVE_CU_3[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_4", REG_MMIO, 0x31e0, &SPI_RESOURCE_RESERVE_CU_4[0], sizeof(SPI_RESOURCE_RESERVE_CU_4)/sizeof(SPI_RESOURCE_RESERVE_CU_4[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_5", REG_MMIO, 0x31e1, &SPI_RESOURCE_RESERVE_CU_5[0], sizeof(SPI_RESOURCE_RESERVE_CU_5)/sizeof(SPI_RESOURCE_RESERVE_CU_5[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_6", REG_MMIO, 0x31e2, &SPI_RESOURCE_RESERVE_CU_6[0], sizeof(SPI_RESOURCE_RESERVE_CU_6)/sizeof(SPI_RESOURCE_RESERVE_CU_6[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_7", REG_MMIO, 0x31e3, &SPI_RESOURCE_RESERVE_CU_7[0], sizeof(SPI_RESOURCE_RESERVE_CU_7)/sizeof(SPI_RESOURCE_RESERVE_CU_7[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_8", REG_MMIO, 0x31e4, &SPI_RESOURCE_RESERVE_CU_8[0], sizeof(SPI_RESOURCE_RESERVE_CU_8)/sizeof(SPI_RESOURCE_RESERVE_CU_8[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_9", REG_MMIO, 0x31e5, &SPI_RESOURCE_RESERVE_CU_9[0], sizeof(SPI_RESOURCE_RESERVE_CU_9)/sizeof(SPI_RESOURCE_RESERVE_CU_9[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_0", REG_MMIO, 0x31e6, &SPI_RESOURCE_RESERVE_EN_CU_0[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_0)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_0[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_1", REG_MMIO, 0x31e7, &SPI_RESOURCE_RESERVE_EN_CU_1[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_1)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_1[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_2", REG_MMIO, 0x31e8, &SPI_RESOURCE_RESERVE_EN_CU_2[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_2)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_2[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_3", REG_MMIO, 0x31e9, &SPI_RESOURCE_RESERVE_EN_CU_3[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_3)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_3[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_4", REG_MMIO, 0x31ea, &SPI_RESOURCE_RESERVE_EN_CU_4[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_4)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_4[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_5", REG_MMIO, 0x31eb, &SPI_RESOURCE_RESERVE_EN_CU_5[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_5)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_5[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_6", REG_MMIO, 0x31ec, &SPI_RESOURCE_RESERVE_EN_CU_6[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_6)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_6[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_7", REG_MMIO, 0x31ed, &SPI_RESOURCE_RESERVE_EN_CU_7[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_7)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_7[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_8", REG_MMIO, 0x31ee, &SPI_RESOURCE_RESERVE_EN_CU_8[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_8)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_8[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_9", REG_MMIO, 0x31ef, &SPI_RESOURCE_RESERVE_EN_CU_9[0], sizeof(SPI_RESOURCE_RESERVE_EN_CU_9)/sizeof(SPI_RESOURCE_RESERVE_EN_CU_9[0]), 0, 0 },
+	{ "mmCP_HPD_ROQ_OFFSETS", REG_MMIO, 0x3240, &CP_HPD_ROQ_OFFSETS[0], sizeof(CP_HPD_ROQ_OFFSETS)/sizeof(CP_HPD_ROQ_OFFSETS[0]), 0, 0 },
+	{ "mmCP_HPD_EOP_BASE_ADDR", REG_MMIO, 0x3241, &CP_HPD_EOP_BASE_ADDR[0], sizeof(CP_HPD_EOP_BASE_ADDR)/sizeof(CP_HPD_EOP_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_HPD_EOP_BASE_ADDR_HI", REG_MMIO, 0x3242, &CP_HPD_EOP_BASE_ADDR_HI[0], sizeof(CP_HPD_EOP_BASE_ADDR_HI)/sizeof(CP_HPD_EOP_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HPD_EOP_VMID", REG_MMIO, 0x3243, &CP_HPD_EOP_VMID[0], sizeof(CP_HPD_EOP_VMID)/sizeof(CP_HPD_EOP_VMID[0]), 0, 0 },
+	{ "mmCP_HPD_EOP_CONTROL", REG_MMIO, 0x3244, &CP_HPD_EOP_CONTROL[0], sizeof(CP_HPD_EOP_CONTROL)/sizeof(CP_HPD_EOP_CONTROL[0]), 0, 0 },
+	{ "mmCP_MQD_BASE_ADDR", REG_MMIO, 0x3245, &CP_MQD_BASE_ADDR[0], sizeof(CP_MQD_BASE_ADDR)/sizeof(CP_MQD_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_MQD_BASE_ADDR_HI", REG_MMIO, 0x3246, &CP_MQD_BASE_ADDR_HI[0], sizeof(CP_MQD_BASE_ADDR_HI)/sizeof(CP_MQD_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_ACTIVE", REG_MMIO, 0x3247, &CP_HQD_ACTIVE[0], sizeof(CP_HQD_ACTIVE)/sizeof(CP_HQD_ACTIVE[0]), 0, 0 },
+	{ "mmCP_HQD_VMID", REG_MMIO, 0x3248, &CP_HQD_VMID[0], sizeof(CP_HQD_VMID)/sizeof(CP_HQD_VMID[0]), 0, 0 },
+	{ "mmCP_HQD_PERSISTENT_STATE", REG_MMIO, 0x3249, &CP_HQD_PERSISTENT_STATE[0], sizeof(CP_HQD_PERSISTENT_STATE)/sizeof(CP_HQD_PERSISTENT_STATE[0]), 0, 0 },
+	{ "mmCP_HQD_PIPE_PRIORITY", REG_MMIO, 0x324a, &CP_HQD_PIPE_PRIORITY[0], sizeof(CP_HQD_PIPE_PRIORITY)/sizeof(CP_HQD_PIPE_PRIORITY[0]), 0, 0 },
+	{ "mmCP_HQD_QUEUE_PRIORITY", REG_MMIO, 0x324b, &CP_HQD_QUEUE_PRIORITY[0], sizeof(CP_HQD_QUEUE_PRIORITY)/sizeof(CP_HQD_QUEUE_PRIORITY[0]), 0, 0 },
+	{ "mmCP_HQD_QUANTUM", REG_MMIO, 0x324c, &CP_HQD_QUANTUM[0], sizeof(CP_HQD_QUANTUM)/sizeof(CP_HQD_QUANTUM[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_BASE", REG_MMIO, 0x324d, &CP_HQD_PQ_BASE[0], sizeof(CP_HQD_PQ_BASE)/sizeof(CP_HQD_PQ_BASE[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_BASE_HI", REG_MMIO, 0x324e, &CP_HQD_PQ_BASE_HI[0], sizeof(CP_HQD_PQ_BASE_HI)/sizeof(CP_HQD_PQ_BASE_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR", REG_MMIO, 0x324f, &CP_HQD_PQ_RPTR[0], sizeof(CP_HQD_PQ_RPTR)/sizeof(CP_HQD_PQ_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR", REG_MMIO, 0x3250, &CP_HQD_PQ_RPTR_REPORT_ADDR[0], sizeof(CP_HQD_PQ_RPTR_REPORT_ADDR)/sizeof(CP_HQD_PQ_RPTR_REPORT_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI", REG_MMIO, 0x3251, &CP_HQD_PQ_RPTR_REPORT_ADDR_HI[0], sizeof(CP_HQD_PQ_RPTR_REPORT_ADDR_HI)/sizeof(CP_HQD_PQ_RPTR_REPORT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR", REG_MMIO, 0x3252, &CP_HQD_PQ_WPTR_POLL_ADDR[0], sizeof(CP_HQD_PQ_WPTR_POLL_ADDR)/sizeof(CP_HQD_PQ_WPTR_POLL_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3253, &CP_HQD_PQ_WPTR_POLL_ADDR_HI[0], sizeof(CP_HQD_PQ_WPTR_POLL_ADDR_HI)/sizeof(CP_HQD_PQ_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_DOORBELL_CONTROL", REG_MMIO, 0x3254, &CP_HQD_PQ_DOORBELL_CONTROL[0], sizeof(CP_HQD_PQ_DOORBELL_CONTROL)/sizeof(CP_HQD_PQ_DOORBELL_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR", REG_MMIO, 0x3255, &CP_HQD_PQ_WPTR[0], sizeof(CP_HQD_PQ_WPTR)/sizeof(CP_HQD_PQ_WPTR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_CONTROL", REG_MMIO, 0x3256, &CP_HQD_PQ_CONTROL[0], sizeof(CP_HQD_PQ_CONTROL)/sizeof(CP_HQD_PQ_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_IB_BASE_ADDR", REG_MMIO, 0x3257, &CP_HQD_IB_BASE_ADDR[0], sizeof(CP_HQD_IB_BASE_ADDR)/sizeof(CP_HQD_IB_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_IB_BASE_ADDR_HI", REG_MMIO, 0x3258, &CP_HQD_IB_BASE_ADDR_HI[0], sizeof(CP_HQD_IB_BASE_ADDR_HI)/sizeof(CP_HQD_IB_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_IB_RPTR", REG_MMIO, 0x3259, &CP_HQD_IB_RPTR[0], sizeof(CP_HQD_IB_RPTR)/sizeof(CP_HQD_IB_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_IB_CONTROL", REG_MMIO, 0x325a, &CP_HQD_IB_CONTROL[0], sizeof(CP_HQD_IB_CONTROL)/sizeof(CP_HQD_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_IQ_TIMER", REG_MMIO, 0x325b, &CP_HQD_IQ_TIMER[0], sizeof(CP_HQD_IQ_TIMER)/sizeof(CP_HQD_IQ_TIMER[0]), 0, 0 },
+	{ "mmCP_HQD_IQ_RPTR", REG_MMIO, 0x325c, &CP_HQD_IQ_RPTR[0], sizeof(CP_HQD_IQ_RPTR)/sizeof(CP_HQD_IQ_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_DEQUEUE_REQUEST", REG_MMIO, 0x325d, &CP_HQD_DEQUEUE_REQUEST[0], sizeof(CP_HQD_DEQUEUE_REQUEST)/sizeof(CP_HQD_DEQUEUE_REQUEST[0]), 0, 0 },
+	{ "mmCP_HQD_DMA_OFFLOAD", REG_MMIO, 0x325e, &CP_HQD_DMA_OFFLOAD[0], sizeof(CP_HQD_DMA_OFFLOAD)/sizeof(CP_HQD_DMA_OFFLOAD[0]), 0, 0 },
+	{ "mmCP_HQD_SEMA_CMD", REG_MMIO, 0x325f, &CP_HQD_SEMA_CMD[0], sizeof(CP_HQD_SEMA_CMD)/sizeof(CP_HQD_SEMA_CMD[0]), 0, 0 },
+	{ "mmCP_HQD_MSG_TYPE", REG_MMIO, 0x3260, &CP_HQD_MSG_TYPE[0], sizeof(CP_HQD_MSG_TYPE)/sizeof(CP_HQD_MSG_TYPE[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC0_PREOP_LO", REG_MMIO, 0x3261, &CP_HQD_ATOMIC0_PREOP_LO[0], sizeof(CP_HQD_ATOMIC0_PREOP_LO)/sizeof(CP_HQD_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC0_PREOP_HI", REG_MMIO, 0x3262, &CP_HQD_ATOMIC0_PREOP_HI[0], sizeof(CP_HQD_ATOMIC0_PREOP_HI)/sizeof(CP_HQD_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC1_PREOP_LO", REG_MMIO, 0x3263, &CP_HQD_ATOMIC1_PREOP_LO[0], sizeof(CP_HQD_ATOMIC1_PREOP_LO)/sizeof(CP_HQD_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC1_PREOP_HI", REG_MMIO, 0x3264, &CP_HQD_ATOMIC1_PREOP_HI[0], sizeof(CP_HQD_ATOMIC1_PREOP_HI)/sizeof(CP_HQD_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_SCHEDULER0", REG_MMIO, 0x3265, &CP_HQD_HQ_SCHEDULER0[0], sizeof(CP_HQD_HQ_SCHEDULER0)/sizeof(CP_HQD_HQ_SCHEDULER0[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_SCHEDULER1", REG_MMIO, 0x3266, &CP_HQD_HQ_SCHEDULER1[0], sizeof(CP_HQD_HQ_SCHEDULER1)/sizeof(CP_HQD_HQ_SCHEDULER1[0]), 0, 0 },
+	{ "mmCP_MQD_CONTROL", REG_MMIO, 0x3267, &CP_MQD_CONTROL[0], sizeof(CP_MQD_CONTROL)/sizeof(CP_MQD_CONTROL[0]), 0, 0 },
+	{ "mmDIDT_IND_INDEX", REG_MMIO, 0x3280, &DIDT_IND_INDEX[0], sizeof(DIDT_IND_INDEX)/sizeof(DIDT_IND_INDEX[0]), 0, 0 },
+	{ "mmDIDT_IND_DATA", REG_MMIO, 0x3281, &DIDT_IND_DATA[0], sizeof(DIDT_IND_DATA)/sizeof(DIDT_IND_DATA[0]), 0, 0 },
+	{ "mmTCP_WATCH0_ADDR_H", REG_MMIO, 0x32a0, &TCP_WATCH0_ADDR_H[0], sizeof(TCP_WATCH0_ADDR_H)/sizeof(TCP_WATCH0_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH0_ADDR_L", REG_MMIO, 0x32a1, &TCP_WATCH0_ADDR_L[0], sizeof(TCP_WATCH0_ADDR_L)/sizeof(TCP_WATCH0_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH0_CNTL", REG_MMIO, 0x32a2, &TCP_WATCH0_CNTL[0], sizeof(TCP_WATCH0_CNTL)/sizeof(TCP_WATCH0_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH1_ADDR_H", REG_MMIO, 0x32a3, &TCP_WATCH1_ADDR_H[0], sizeof(TCP_WATCH1_ADDR_H)/sizeof(TCP_WATCH1_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH1_ADDR_L", REG_MMIO, 0x32a4, &TCP_WATCH1_ADDR_L[0], sizeof(TCP_WATCH1_ADDR_L)/sizeof(TCP_WATCH1_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH1_CNTL", REG_MMIO, 0x32a5, &TCP_WATCH1_CNTL[0], sizeof(TCP_WATCH1_CNTL)/sizeof(TCP_WATCH1_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH2_ADDR_H", REG_MMIO, 0x32a6, &TCP_WATCH2_ADDR_H[0], sizeof(TCP_WATCH2_ADDR_H)/sizeof(TCP_WATCH2_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH2_ADDR_L", REG_MMIO, 0x32a7, &TCP_WATCH2_ADDR_L[0], sizeof(TCP_WATCH2_ADDR_L)/sizeof(TCP_WATCH2_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH2_CNTL", REG_MMIO, 0x32a8, &TCP_WATCH2_CNTL[0], sizeof(TCP_WATCH2_CNTL)/sizeof(TCP_WATCH2_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH3_ADDR_H", REG_MMIO, 0x32a9, &TCP_WATCH3_ADDR_H[0], sizeof(TCP_WATCH3_ADDR_H)/sizeof(TCP_WATCH3_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH3_ADDR_L", REG_MMIO, 0x32aa, &TCP_WATCH3_ADDR_L[0], sizeof(TCP_WATCH3_ADDR_L)/sizeof(TCP_WATCH3_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH3_CNTL", REG_MMIO, 0x32ab, &TCP_WATCH3_CNTL[0], sizeof(TCP_WATCH3_CNTL)/sizeof(TCP_WATCH3_CNTL[0]), 0, 0 },
+	{ "mmGDS_VMID0_BASE", REG_MMIO, 0x3300, &GDS_VMID0_BASE[0], sizeof(GDS_VMID0_BASE)/sizeof(GDS_VMID0_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID0_SIZE", REG_MMIO, 0x3301, &GDS_VMID0_SIZE[0], sizeof(GDS_VMID0_SIZE)/sizeof(GDS_VMID0_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID1_BASE", REG_MMIO, 0x3302, &GDS_VMID1_BASE[0], sizeof(GDS_VMID1_BASE)/sizeof(GDS_VMID1_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID1_SIZE", REG_MMIO, 0x3303, &GDS_VMID1_SIZE[0], sizeof(GDS_VMID1_SIZE)/sizeof(GDS_VMID1_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID2_BASE", REG_MMIO, 0x3304, &GDS_VMID2_BASE[0], sizeof(GDS_VMID2_BASE)/sizeof(GDS_VMID2_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID2_SIZE", REG_MMIO, 0x3305, &GDS_VMID2_SIZE[0], sizeof(GDS_VMID2_SIZE)/sizeof(GDS_VMID2_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID3_BASE", REG_MMIO, 0x3306, &GDS_VMID3_BASE[0], sizeof(GDS_VMID3_BASE)/sizeof(GDS_VMID3_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID3_SIZE", REG_MMIO, 0x3307, &GDS_VMID3_SIZE[0], sizeof(GDS_VMID3_SIZE)/sizeof(GDS_VMID3_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID4_BASE", REG_MMIO, 0x3308, &GDS_VMID4_BASE[0], sizeof(GDS_VMID4_BASE)/sizeof(GDS_VMID4_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID4_SIZE", REG_MMIO, 0x3309, &GDS_VMID4_SIZE[0], sizeof(GDS_VMID4_SIZE)/sizeof(GDS_VMID4_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID5_BASE", REG_MMIO, 0x330a, &GDS_VMID5_BASE[0], sizeof(GDS_VMID5_BASE)/sizeof(GDS_VMID5_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID5_SIZE", REG_MMIO, 0x330b, &GDS_VMID5_SIZE[0], sizeof(GDS_VMID5_SIZE)/sizeof(GDS_VMID5_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID6_BASE", REG_MMIO, 0x330c, &GDS_VMID6_BASE[0], sizeof(GDS_VMID6_BASE)/sizeof(GDS_VMID6_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID6_SIZE", REG_MMIO, 0x330d, &GDS_VMID6_SIZE[0], sizeof(GDS_VMID6_SIZE)/sizeof(GDS_VMID6_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID7_BASE", REG_MMIO, 0x330e, &GDS_VMID7_BASE[0], sizeof(GDS_VMID7_BASE)/sizeof(GDS_VMID7_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID7_SIZE", REG_MMIO, 0x330f, &GDS_VMID7_SIZE[0], sizeof(GDS_VMID7_SIZE)/sizeof(GDS_VMID7_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID8_BASE", REG_MMIO, 0x3310, &GDS_VMID8_BASE[0], sizeof(GDS_VMID8_BASE)/sizeof(GDS_VMID8_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID8_SIZE", REG_MMIO, 0x3311, &GDS_VMID8_SIZE[0], sizeof(GDS_VMID8_SIZE)/sizeof(GDS_VMID8_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID9_BASE", REG_MMIO, 0x3312, &GDS_VMID9_BASE[0], sizeof(GDS_VMID9_BASE)/sizeof(GDS_VMID9_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID9_SIZE", REG_MMIO, 0x3313, &GDS_VMID9_SIZE[0], sizeof(GDS_VMID9_SIZE)/sizeof(GDS_VMID9_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID10_BASE", REG_MMIO, 0x3314, &GDS_VMID10_BASE[0], sizeof(GDS_VMID10_BASE)/sizeof(GDS_VMID10_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID10_SIZE", REG_MMIO, 0x3315, &GDS_VMID10_SIZE[0], sizeof(GDS_VMID10_SIZE)/sizeof(GDS_VMID10_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID11_BASE", REG_MMIO, 0x3316, &GDS_VMID11_BASE[0], sizeof(GDS_VMID11_BASE)/sizeof(GDS_VMID11_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID11_SIZE", REG_MMIO, 0x3317, &GDS_VMID11_SIZE[0], sizeof(GDS_VMID11_SIZE)/sizeof(GDS_VMID11_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID12_BASE", REG_MMIO, 0x3318, &GDS_VMID12_BASE[0], sizeof(GDS_VMID12_BASE)/sizeof(GDS_VMID12_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID12_SIZE", REG_MMIO, 0x3319, &GDS_VMID12_SIZE[0], sizeof(GDS_VMID12_SIZE)/sizeof(GDS_VMID12_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID13_BASE", REG_MMIO, 0x331a, &GDS_VMID13_BASE[0], sizeof(GDS_VMID13_BASE)/sizeof(GDS_VMID13_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID13_SIZE", REG_MMIO, 0x331b, &GDS_VMID13_SIZE[0], sizeof(GDS_VMID13_SIZE)/sizeof(GDS_VMID13_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID14_BASE", REG_MMIO, 0x331c, &GDS_VMID14_BASE[0], sizeof(GDS_VMID14_BASE)/sizeof(GDS_VMID14_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID14_SIZE", REG_MMIO, 0x331d, &GDS_VMID14_SIZE[0], sizeof(GDS_VMID14_SIZE)/sizeof(GDS_VMID14_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID15_BASE", REG_MMIO, 0x331e, &GDS_VMID15_BASE[0], sizeof(GDS_VMID15_BASE)/sizeof(GDS_VMID15_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID15_SIZE", REG_MMIO, 0x331f, &GDS_VMID15_SIZE[0], sizeof(GDS_VMID15_SIZE)/sizeof(GDS_VMID15_SIZE[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID0", REG_MMIO, 0x3320, &GDS_GWS_VMID0[0], sizeof(GDS_GWS_VMID0)/sizeof(GDS_GWS_VMID0[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID1", REG_MMIO, 0x3321, &GDS_GWS_VMID1[0], sizeof(GDS_GWS_VMID1)/sizeof(GDS_GWS_VMID1[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID2", REG_MMIO, 0x3322, &GDS_GWS_VMID2[0], sizeof(GDS_GWS_VMID2)/sizeof(GDS_GWS_VMID2[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID3", REG_MMIO, 0x3323, &GDS_GWS_VMID3[0], sizeof(GDS_GWS_VMID3)/sizeof(GDS_GWS_VMID3[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID4", REG_MMIO, 0x3324, &GDS_GWS_VMID4[0], sizeof(GDS_GWS_VMID4)/sizeof(GDS_GWS_VMID4[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID5", REG_MMIO, 0x3325, &GDS_GWS_VMID5[0], sizeof(GDS_GWS_VMID5)/sizeof(GDS_GWS_VMID5[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID6", REG_MMIO, 0x3326, &GDS_GWS_VMID6[0], sizeof(GDS_GWS_VMID6)/sizeof(GDS_GWS_VMID6[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID7", REG_MMIO, 0x3327, &GDS_GWS_VMID7[0], sizeof(GDS_GWS_VMID7)/sizeof(GDS_GWS_VMID7[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID8", REG_MMIO, 0x3328, &GDS_GWS_VMID8[0], sizeof(GDS_GWS_VMID8)/sizeof(GDS_GWS_VMID8[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID9", REG_MMIO, 0x3329, &GDS_GWS_VMID9[0], sizeof(GDS_GWS_VMID9)/sizeof(GDS_GWS_VMID9[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID10", REG_MMIO, 0x332a, &GDS_GWS_VMID10[0], sizeof(GDS_GWS_VMID10)/sizeof(GDS_GWS_VMID10[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID11", REG_MMIO, 0x332b, &GDS_GWS_VMID11[0], sizeof(GDS_GWS_VMID11)/sizeof(GDS_GWS_VMID11[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID12", REG_MMIO, 0x332c, &GDS_GWS_VMID12[0], sizeof(GDS_GWS_VMID12)/sizeof(GDS_GWS_VMID12[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID13", REG_MMIO, 0x332d, &GDS_GWS_VMID13[0], sizeof(GDS_GWS_VMID13)/sizeof(GDS_GWS_VMID13[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID14", REG_MMIO, 0x332e, &GDS_GWS_VMID14[0], sizeof(GDS_GWS_VMID14)/sizeof(GDS_GWS_VMID14[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID15", REG_MMIO, 0x332f, &GDS_GWS_VMID15[0], sizeof(GDS_GWS_VMID15)/sizeof(GDS_GWS_VMID15[0]), 0, 0 },
+	{ "mmGDS_OA_VMID0", REG_MMIO, 0x3330, &GDS_OA_VMID0[0], sizeof(GDS_OA_VMID0)/sizeof(GDS_OA_VMID0[0]), 0, 0 },
+	{ "mmGDS_OA_VMID1", REG_MMIO, 0x3331, &GDS_OA_VMID1[0], sizeof(GDS_OA_VMID1)/sizeof(GDS_OA_VMID1[0]), 0, 0 },
+	{ "mmGDS_OA_VMID2", REG_MMIO, 0x3332, &GDS_OA_VMID2[0], sizeof(GDS_OA_VMID2)/sizeof(GDS_OA_VMID2[0]), 0, 0 },
+	{ "mmGDS_OA_VMID3", REG_MMIO, 0x3333, &GDS_OA_VMID3[0], sizeof(GDS_OA_VMID3)/sizeof(GDS_OA_VMID3[0]), 0, 0 },
+	{ "mmGDS_OA_VMID4", REG_MMIO, 0x3334, &GDS_OA_VMID4[0], sizeof(GDS_OA_VMID4)/sizeof(GDS_OA_VMID4[0]), 0, 0 },
+	{ "mmGDS_OA_VMID5", REG_MMIO, 0x3335, &GDS_OA_VMID5[0], sizeof(GDS_OA_VMID5)/sizeof(GDS_OA_VMID5[0]), 0, 0 },
+	{ "mmGDS_OA_VMID6", REG_MMIO, 0x3336, &GDS_OA_VMID6[0], sizeof(GDS_OA_VMID6)/sizeof(GDS_OA_VMID6[0]), 0, 0 },
+	{ "mmGDS_OA_VMID7", REG_MMIO, 0x3337, &GDS_OA_VMID7[0], sizeof(GDS_OA_VMID7)/sizeof(GDS_OA_VMID7[0]), 0, 0 },
+	{ "mmGDS_OA_VMID8", REG_MMIO, 0x3338, &GDS_OA_VMID8[0], sizeof(GDS_OA_VMID8)/sizeof(GDS_OA_VMID8[0]), 0, 0 },
+	{ "mmGDS_OA_VMID9", REG_MMIO, 0x3339, &GDS_OA_VMID9[0], sizeof(GDS_OA_VMID9)/sizeof(GDS_OA_VMID9[0]), 0, 0 },
+	{ "mmGDS_OA_VMID10", REG_MMIO, 0x333a, &GDS_OA_VMID10[0], sizeof(GDS_OA_VMID10)/sizeof(GDS_OA_VMID10[0]), 0, 0 },
+	{ "mmGDS_OA_VMID11", REG_MMIO, 0x333b, &GDS_OA_VMID11[0], sizeof(GDS_OA_VMID11)/sizeof(GDS_OA_VMID11[0]), 0, 0 },
+	{ "mmGDS_OA_VMID12", REG_MMIO, 0x333c, &GDS_OA_VMID12[0], sizeof(GDS_OA_VMID12)/sizeof(GDS_OA_VMID12[0]), 0, 0 },
+	{ "mmGDS_OA_VMID13", REG_MMIO, 0x333d, &GDS_OA_VMID13[0], sizeof(GDS_OA_VMID13)/sizeof(GDS_OA_VMID13[0]), 0, 0 },
+	{ "mmGDS_OA_VMID14", REG_MMIO, 0x333e, &GDS_OA_VMID14[0], sizeof(GDS_OA_VMID14)/sizeof(GDS_OA_VMID14[0]), 0, 0 },
+	{ "mmGDS_OA_VMID15", REG_MMIO, 0x333f, &GDS_OA_VMID15[0], sizeof(GDS_OA_VMID15)/sizeof(GDS_OA_VMID15[0]), 0, 0 },
+	{ "mmGDS_GWS_RESET0", REG_MMIO, 0x3344, &GDS_GWS_RESET0[0], sizeof(GDS_GWS_RESET0)/sizeof(GDS_GWS_RESET0[0]), 0, 0 },
+	{ "mmGDS_GWS_RESET1", REG_MMIO, 0x3345, &GDS_GWS_RESET1[0], sizeof(GDS_GWS_RESET1)/sizeof(GDS_GWS_RESET1[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_RESET", REG_MMIO, 0x3346, &GDS_GWS_RESOURCE_RESET[0], sizeof(GDS_GWS_RESOURCE_RESET)/sizeof(GDS_GWS_RESOURCE_RESET[0]), 0, 0 },
+	{ "mmGDS_COMPUTE_MAX_WAVE_ID", REG_MMIO, 0x3348, &GDS_COMPUTE_MAX_WAVE_ID[0], sizeof(GDS_COMPUTE_MAX_WAVE_ID)/sizeof(GDS_COMPUTE_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmGDS_OA_RESET_MASK", REG_MMIO, 0x3349, &GDS_OA_RESET_MASK[0], sizeof(GDS_OA_RESET_MASK)/sizeof(GDS_OA_RESET_MASK[0]), 0, 0 },
+	{ "mmGDS_OA_RESET", REG_MMIO, 0x334a, &GDS_OA_RESET[0], sizeof(GDS_OA_RESET)/sizeof(GDS_OA_RESET[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_CONTROL", REG_MMIO, 0x3380, &RAS_SIGNATURE_CONTROL[0], sizeof(RAS_SIGNATURE_CONTROL)/sizeof(RAS_SIGNATURE_CONTROL[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_MASK", REG_MMIO, 0x3381, &RAS_SIGNATURE_MASK[0], sizeof(RAS_SIGNATURE_MASK)/sizeof(RAS_SIGNATURE_MASK[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE0", REG_MMIO, 0x3382, &RAS_SX_SIGNATURE0[0], sizeof(RAS_SX_SIGNATURE0)/sizeof(RAS_SX_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE1", REG_MMIO, 0x3383, &RAS_SX_SIGNATURE1[0], sizeof(RAS_SX_SIGNATURE1)/sizeof(RAS_SX_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE2", REG_MMIO, 0x3384, &RAS_SX_SIGNATURE2[0], sizeof(RAS_SX_SIGNATURE2)/sizeof(RAS_SX_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE3", REG_MMIO, 0x3385, &RAS_SX_SIGNATURE3[0], sizeof(RAS_SX_SIGNATURE3)/sizeof(RAS_SX_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_DB_SIGNATURE0", REG_MMIO, 0x338b, &RAS_DB_SIGNATURE0[0], sizeof(RAS_DB_SIGNATURE0)/sizeof(RAS_DB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_PA_SIGNATURE0", REG_MMIO, 0x338c, &RAS_PA_SIGNATURE0[0], sizeof(RAS_PA_SIGNATURE0)/sizeof(RAS_PA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_VGT_SIGNATURE0", REG_MMIO, 0x338d, &RAS_VGT_SIGNATURE0[0], sizeof(RAS_VGT_SIGNATURE0)/sizeof(RAS_VGT_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SQ_SIGNATURE0", REG_MMIO, 0x338e, &RAS_SQ_SIGNATURE0[0], sizeof(RAS_SQ_SIGNATURE0)/sizeof(RAS_SQ_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE0", REG_MMIO, 0x338f, &RAS_SC_SIGNATURE0[0], sizeof(RAS_SC_SIGNATURE0)/sizeof(RAS_SC_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE1", REG_MMIO, 0x3390, &RAS_SC_SIGNATURE1[0], sizeof(RAS_SC_SIGNATURE1)/sizeof(RAS_SC_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE2", REG_MMIO, 0x3391, &RAS_SC_SIGNATURE2[0], sizeof(RAS_SC_SIGNATURE2)/sizeof(RAS_SC_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE3", REG_MMIO, 0x3392, &RAS_SC_SIGNATURE3[0], sizeof(RAS_SC_SIGNATURE3)/sizeof(RAS_SC_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE4", REG_MMIO, 0x3393, &RAS_SC_SIGNATURE4[0], sizeof(RAS_SC_SIGNATURE4)/sizeof(RAS_SC_SIGNATURE4[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE5", REG_MMIO, 0x3394, &RAS_SC_SIGNATURE5[0], sizeof(RAS_SC_SIGNATURE5)/sizeof(RAS_SC_SIGNATURE5[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE6", REG_MMIO, 0x3395, &RAS_SC_SIGNATURE6[0], sizeof(RAS_SC_SIGNATURE6)/sizeof(RAS_SC_SIGNATURE6[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE7", REG_MMIO, 0x3396, &RAS_SC_SIGNATURE7[0], sizeof(RAS_SC_SIGNATURE7)/sizeof(RAS_SC_SIGNATURE7[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE0", REG_MMIO, 0x3397, &RAS_IA_SIGNATURE0[0], sizeof(RAS_IA_SIGNATURE0)/sizeof(RAS_IA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE1", REG_MMIO, 0x3398, &RAS_IA_SIGNATURE1[0], sizeof(RAS_IA_SIGNATURE1)/sizeof(RAS_IA_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE0", REG_MMIO, 0x3399, &RAS_SPI_SIGNATURE0[0], sizeof(RAS_SPI_SIGNATURE0)/sizeof(RAS_SPI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE1", REG_MMIO, 0x339a, &RAS_SPI_SIGNATURE1[0], sizeof(RAS_SPI_SIGNATURE1)/sizeof(RAS_SPI_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_TA_SIGNATURE0", REG_MMIO, 0x339b, &RAS_TA_SIGNATURE0[0], sizeof(RAS_TA_SIGNATURE0)/sizeof(RAS_TA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_TD_SIGNATURE0", REG_MMIO, 0x339c, &RAS_TD_SIGNATURE0[0], sizeof(RAS_TD_SIGNATURE0)/sizeof(RAS_TD_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_CB_SIGNATURE0", REG_MMIO, 0x339d, &RAS_CB_SIGNATURE0[0], sizeof(RAS_CB_SIGNATURE0)/sizeof(RAS_CB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE0", REG_MMIO, 0x339e, &RAS_BCI_SIGNATURE0[0], sizeof(RAS_BCI_SIGNATURE0)/sizeof(RAS_BCI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE1", REG_MMIO, 0x339f, &RAS_BCI_SIGNATURE1[0], sizeof(RAS_BCI_SIGNATURE1)/sizeof(RAS_BCI_SIGNATURE1[0]), 0, 0 },
+	{ "mmDB_RENDER_CONTROL", REG_MMIO, 0xa000, &DB_RENDER_CONTROL[0], sizeof(DB_RENDER_CONTROL)/sizeof(DB_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmDB_COUNT_CONTROL", REG_MMIO, 0xa001, &DB_COUNT_CONTROL[0], sizeof(DB_COUNT_CONTROL)/sizeof(DB_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmDB_DEPTH_VIEW", REG_MMIO, 0xa002, &DB_DEPTH_VIEW[0], sizeof(DB_DEPTH_VIEW)/sizeof(DB_DEPTH_VIEW[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE", REG_MMIO, 0xa003, &DB_RENDER_OVERRIDE[0], sizeof(DB_RENDER_OVERRIDE)/sizeof(DB_RENDER_OVERRIDE[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE2", REG_MMIO, 0xa004, &DB_RENDER_OVERRIDE2[0], sizeof(DB_RENDER_OVERRIDE2)/sizeof(DB_RENDER_OVERRIDE2[0]), 0, 0 },
+	{ "mmDB_HTILE_DATA_BASE", REG_MMIO, 0xa005, &DB_HTILE_DATA_BASE[0], sizeof(DB_HTILE_DATA_BASE)/sizeof(DB_HTILE_DATA_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MIN", REG_MMIO, 0xa008, &DB_DEPTH_BOUNDS_MIN[0], sizeof(DB_DEPTH_BOUNDS_MIN)/sizeof(DB_DEPTH_BOUNDS_MIN[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MAX", REG_MMIO, 0xa009, &DB_DEPTH_BOUNDS_MAX[0], sizeof(DB_DEPTH_BOUNDS_MAX)/sizeof(DB_DEPTH_BOUNDS_MAX[0]), 0, 0 },
+	{ "mmDB_STENCIL_CLEAR", REG_MMIO, 0xa00a, &DB_STENCIL_CLEAR[0], sizeof(DB_STENCIL_CLEAR)/sizeof(DB_STENCIL_CLEAR[0]), 0, 0 },
+	{ "mmDB_DEPTH_CLEAR", REG_MMIO, 0xa00b, &DB_DEPTH_CLEAR[0], sizeof(DB_DEPTH_CLEAR)/sizeof(DB_DEPTH_CLEAR[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_TL", REG_MMIO, 0xa00c, &PA_SC_SCREEN_SCISSOR_TL[0], sizeof(PA_SC_SCREEN_SCISSOR_TL)/sizeof(PA_SC_SCREEN_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_BR", REG_MMIO, 0xa00d, &PA_SC_SCREEN_SCISSOR_BR[0], sizeof(PA_SC_SCREEN_SCISSOR_BR)/sizeof(PA_SC_SCREEN_SCISSOR_BR[0]), 0, 0 },
+	{ "mmDB_DEPTH_INFO", REG_MMIO, 0xa00f, &DB_DEPTH_INFO[0], sizeof(DB_DEPTH_INFO)/sizeof(DB_DEPTH_INFO[0]), 0, 0 },
+	{ "mmDB_Z_INFO", REG_MMIO, 0xa010, &DB_Z_INFO[0], sizeof(DB_Z_INFO)/sizeof(DB_Z_INFO[0]), 0, 0 },
+	{ "mmDB_STENCIL_INFO", REG_MMIO, 0xa011, &DB_STENCIL_INFO[0], sizeof(DB_STENCIL_INFO)/sizeof(DB_STENCIL_INFO[0]), 0, 0 },
+	{ "mmDB_Z_READ_BASE", REG_MMIO, 0xa012, &DB_Z_READ_BASE[0], sizeof(DB_Z_READ_BASE)/sizeof(DB_Z_READ_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_READ_BASE", REG_MMIO, 0xa013, &DB_STENCIL_READ_BASE[0], sizeof(DB_STENCIL_READ_BASE)/sizeof(DB_STENCIL_READ_BASE[0]), 0, 0 },
+	{ "mmDB_Z_WRITE_BASE", REG_MMIO, 0xa014, &DB_Z_WRITE_BASE[0], sizeof(DB_Z_WRITE_BASE)/sizeof(DB_Z_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_WRITE_BASE", REG_MMIO, 0xa015, &DB_STENCIL_WRITE_BASE[0], sizeof(DB_STENCIL_WRITE_BASE)/sizeof(DB_STENCIL_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SIZE", REG_MMIO, 0xa016, &DB_DEPTH_SIZE[0], sizeof(DB_DEPTH_SIZE)/sizeof(DB_DEPTH_SIZE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SLICE", REG_MMIO, 0xa017, &DB_DEPTH_SLICE[0], sizeof(DB_DEPTH_SLICE)/sizeof(DB_DEPTH_SLICE[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR", REG_MMIO, 0xa020, &TA_BC_BASE_ADDR[0], sizeof(TA_BC_BASE_ADDR)/sizeof(TA_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR_HI", REG_MMIO, 0xa021, &TA_BC_BASE_ADDR_HI[0], sizeof(TA_BC_BASE_ADDR_HI)/sizeof(TA_BC_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_0", REG_MMIO, 0xa07a, &COHER_DEST_BASE_HI_0[0], sizeof(COHER_DEST_BASE_HI_0)/sizeof(COHER_DEST_BASE_HI_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_1", REG_MMIO, 0xa07b, &COHER_DEST_BASE_HI_1[0], sizeof(COHER_DEST_BASE_HI_1)/sizeof(COHER_DEST_BASE_HI_1[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_2", REG_MMIO, 0xa07c, &COHER_DEST_BASE_HI_2[0], sizeof(COHER_DEST_BASE_HI_2)/sizeof(COHER_DEST_BASE_HI_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_3", REG_MMIO, 0xa07d, &COHER_DEST_BASE_HI_3[0], sizeof(COHER_DEST_BASE_HI_3)/sizeof(COHER_DEST_BASE_HI_3[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_2", REG_MMIO, 0xa07e, &COHER_DEST_BASE_2[0], sizeof(COHER_DEST_BASE_2)/sizeof(COHER_DEST_BASE_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_3", REG_MMIO, 0xa07f, &COHER_DEST_BASE_3[0], sizeof(COHER_DEST_BASE_3)/sizeof(COHER_DEST_BASE_3[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_OFFSET", REG_MMIO, 0xa080, &PA_SC_WINDOW_OFFSET[0], sizeof(PA_SC_WINDOW_OFFSET)/sizeof(PA_SC_WINDOW_OFFSET[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_TL", REG_MMIO, 0xa081, &PA_SC_WINDOW_SCISSOR_TL[0], sizeof(PA_SC_WINDOW_SCISSOR_TL)/sizeof(PA_SC_WINDOW_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_BR", REG_MMIO, 0xa082, &PA_SC_WINDOW_SCISSOR_BR[0], sizeof(PA_SC_WINDOW_SCISSOR_BR)/sizeof(PA_SC_WINDOW_SCISSOR_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_RULE", REG_MMIO, 0xa083, &PA_SC_CLIPRECT_RULE[0], sizeof(PA_SC_CLIPRECT_RULE)/sizeof(PA_SC_CLIPRECT_RULE[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_TL", REG_MMIO, 0xa084, &PA_SC_CLIPRECT_0_TL[0], sizeof(PA_SC_CLIPRECT_0_TL)/sizeof(PA_SC_CLIPRECT_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_BR", REG_MMIO, 0xa085, &PA_SC_CLIPRECT_0_BR[0], sizeof(PA_SC_CLIPRECT_0_BR)/sizeof(PA_SC_CLIPRECT_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_TL", REG_MMIO, 0xa086, &PA_SC_CLIPRECT_1_TL[0], sizeof(PA_SC_CLIPRECT_1_TL)/sizeof(PA_SC_CLIPRECT_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_BR", REG_MMIO, 0xa087, &PA_SC_CLIPRECT_1_BR[0], sizeof(PA_SC_CLIPRECT_1_BR)/sizeof(PA_SC_CLIPRECT_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_TL", REG_MMIO, 0xa088, &PA_SC_CLIPRECT_2_TL[0], sizeof(PA_SC_CLIPRECT_2_TL)/sizeof(PA_SC_CLIPRECT_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_BR", REG_MMIO, 0xa089, &PA_SC_CLIPRECT_2_BR[0], sizeof(PA_SC_CLIPRECT_2_BR)/sizeof(PA_SC_CLIPRECT_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_TL", REG_MMIO, 0xa08a, &PA_SC_CLIPRECT_3_TL[0], sizeof(PA_SC_CLIPRECT_3_TL)/sizeof(PA_SC_CLIPRECT_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_BR", REG_MMIO, 0xa08b, &PA_SC_CLIPRECT_3_BR[0], sizeof(PA_SC_CLIPRECT_3_BR)/sizeof(PA_SC_CLIPRECT_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_EDGERULE", REG_MMIO, 0xa08c, &PA_SC_EDGERULE[0], sizeof(PA_SC_EDGERULE)/sizeof(PA_SC_EDGERULE[0]), 0, 0 },
+	{ "mmPA_SU_HARDWARE_SCREEN_OFFSET", REG_MMIO, 0xa08d, &PA_SU_HARDWARE_SCREEN_OFFSET[0], sizeof(PA_SU_HARDWARE_SCREEN_OFFSET)/sizeof(PA_SU_HARDWARE_SCREEN_OFFSET[0]), 0, 0 },
+	{ "mmCB_TARGET_MASK", REG_MMIO, 0xa08e, &CB_TARGET_MASK[0], sizeof(CB_TARGET_MASK)/sizeof(CB_TARGET_MASK[0]), 0, 0 },
+	{ "mmCB_SHADER_MASK", REG_MMIO, 0xa08f, &CB_SHADER_MASK[0], sizeof(CB_SHADER_MASK)/sizeof(CB_SHADER_MASK[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_TL", REG_MMIO, 0xa090, &PA_SC_GENERIC_SCISSOR_TL[0], sizeof(PA_SC_GENERIC_SCISSOR_TL)/sizeof(PA_SC_GENERIC_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_BR", REG_MMIO, 0xa091, &PA_SC_GENERIC_SCISSOR_BR[0], sizeof(PA_SC_GENERIC_SCISSOR_BR)/sizeof(PA_SC_GENERIC_SCISSOR_BR[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_0", REG_MMIO, 0xa092, &COHER_DEST_BASE_0[0], sizeof(COHER_DEST_BASE_0)/sizeof(COHER_DEST_BASE_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_1", REG_MMIO, 0xa093, &COHER_DEST_BASE_1[0], sizeof(COHER_DEST_BASE_1)/sizeof(COHER_DEST_BASE_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_TL", REG_MMIO, 0xa094, &PA_SC_VPORT_SCISSOR_0_TL[0], sizeof(PA_SC_VPORT_SCISSOR_0_TL)/sizeof(PA_SC_VPORT_SCISSOR_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_BR", REG_MMIO, 0xa095, &PA_SC_VPORT_SCISSOR_0_BR[0], sizeof(PA_SC_VPORT_SCISSOR_0_BR)/sizeof(PA_SC_VPORT_SCISSOR_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_TL", REG_MMIO, 0xa096, &PA_SC_VPORT_SCISSOR_1_TL[0], sizeof(PA_SC_VPORT_SCISSOR_1_TL)/sizeof(PA_SC_VPORT_SCISSOR_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_BR", REG_MMIO, 0xa097, &PA_SC_VPORT_SCISSOR_1_BR[0], sizeof(PA_SC_VPORT_SCISSOR_1_BR)/sizeof(PA_SC_VPORT_SCISSOR_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_TL", REG_MMIO, 0xa098, &PA_SC_VPORT_SCISSOR_2_TL[0], sizeof(PA_SC_VPORT_SCISSOR_2_TL)/sizeof(PA_SC_VPORT_SCISSOR_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_BR", REG_MMIO, 0xa099, &PA_SC_VPORT_SCISSOR_2_BR[0], sizeof(PA_SC_VPORT_SCISSOR_2_BR)/sizeof(PA_SC_VPORT_SCISSOR_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_TL", REG_MMIO, 0xa09a, &PA_SC_VPORT_SCISSOR_3_TL[0], sizeof(PA_SC_VPORT_SCISSOR_3_TL)/sizeof(PA_SC_VPORT_SCISSOR_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_BR", REG_MMIO, 0xa09b, &PA_SC_VPORT_SCISSOR_3_BR[0], sizeof(PA_SC_VPORT_SCISSOR_3_BR)/sizeof(PA_SC_VPORT_SCISSOR_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_TL", REG_MMIO, 0xa09c, &PA_SC_VPORT_SCISSOR_4_TL[0], sizeof(PA_SC_VPORT_SCISSOR_4_TL)/sizeof(PA_SC_VPORT_SCISSOR_4_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_BR", REG_MMIO, 0xa09d, &PA_SC_VPORT_SCISSOR_4_BR[0], sizeof(PA_SC_VPORT_SCISSOR_4_BR)/sizeof(PA_SC_VPORT_SCISSOR_4_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_TL", REG_MMIO, 0xa09e, &PA_SC_VPORT_SCISSOR_5_TL[0], sizeof(PA_SC_VPORT_SCISSOR_5_TL)/sizeof(PA_SC_VPORT_SCISSOR_5_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_BR", REG_MMIO, 0xa09f, &PA_SC_VPORT_SCISSOR_5_BR[0], sizeof(PA_SC_VPORT_SCISSOR_5_BR)/sizeof(PA_SC_VPORT_SCISSOR_5_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_TL", REG_MMIO, 0xa0a0, &PA_SC_VPORT_SCISSOR_6_TL[0], sizeof(PA_SC_VPORT_SCISSOR_6_TL)/sizeof(PA_SC_VPORT_SCISSOR_6_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_BR", REG_MMIO, 0xa0a1, &PA_SC_VPORT_SCISSOR_6_BR[0], sizeof(PA_SC_VPORT_SCISSOR_6_BR)/sizeof(PA_SC_VPORT_SCISSOR_6_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_TL", REG_MMIO, 0xa0a2, &PA_SC_VPORT_SCISSOR_7_TL[0], sizeof(PA_SC_VPORT_SCISSOR_7_TL)/sizeof(PA_SC_VPORT_SCISSOR_7_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_BR", REG_MMIO, 0xa0a3, &PA_SC_VPORT_SCISSOR_7_BR[0], sizeof(PA_SC_VPORT_SCISSOR_7_BR)/sizeof(PA_SC_VPORT_SCISSOR_7_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_TL", REG_MMIO, 0xa0a4, &PA_SC_VPORT_SCISSOR_8_TL[0], sizeof(PA_SC_VPORT_SCISSOR_8_TL)/sizeof(PA_SC_VPORT_SCISSOR_8_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_BR", REG_MMIO, 0xa0a5, &PA_SC_VPORT_SCISSOR_8_BR[0], sizeof(PA_SC_VPORT_SCISSOR_8_BR)/sizeof(PA_SC_VPORT_SCISSOR_8_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_TL", REG_MMIO, 0xa0a6, &PA_SC_VPORT_SCISSOR_9_TL[0], sizeof(PA_SC_VPORT_SCISSOR_9_TL)/sizeof(PA_SC_VPORT_SCISSOR_9_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_BR", REG_MMIO, 0xa0a7, &PA_SC_VPORT_SCISSOR_9_BR[0], sizeof(PA_SC_VPORT_SCISSOR_9_BR)/sizeof(PA_SC_VPORT_SCISSOR_9_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_TL", REG_MMIO, 0xa0a8, &PA_SC_VPORT_SCISSOR_10_TL[0], sizeof(PA_SC_VPORT_SCISSOR_10_TL)/sizeof(PA_SC_VPORT_SCISSOR_10_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_BR", REG_MMIO, 0xa0a9, &PA_SC_VPORT_SCISSOR_10_BR[0], sizeof(PA_SC_VPORT_SCISSOR_10_BR)/sizeof(PA_SC_VPORT_SCISSOR_10_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_TL", REG_MMIO, 0xa0aa, &PA_SC_VPORT_SCISSOR_11_TL[0], sizeof(PA_SC_VPORT_SCISSOR_11_TL)/sizeof(PA_SC_VPORT_SCISSOR_11_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_BR", REG_MMIO, 0xa0ab, &PA_SC_VPORT_SCISSOR_11_BR[0], sizeof(PA_SC_VPORT_SCISSOR_11_BR)/sizeof(PA_SC_VPORT_SCISSOR_11_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_TL", REG_MMIO, 0xa0ac, &PA_SC_VPORT_SCISSOR_12_TL[0], sizeof(PA_SC_VPORT_SCISSOR_12_TL)/sizeof(PA_SC_VPORT_SCISSOR_12_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_BR", REG_MMIO, 0xa0ad, &PA_SC_VPORT_SCISSOR_12_BR[0], sizeof(PA_SC_VPORT_SCISSOR_12_BR)/sizeof(PA_SC_VPORT_SCISSOR_12_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_TL", REG_MMIO, 0xa0ae, &PA_SC_VPORT_SCISSOR_13_TL[0], sizeof(PA_SC_VPORT_SCISSOR_13_TL)/sizeof(PA_SC_VPORT_SCISSOR_13_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_BR", REG_MMIO, 0xa0af, &PA_SC_VPORT_SCISSOR_13_BR[0], sizeof(PA_SC_VPORT_SCISSOR_13_BR)/sizeof(PA_SC_VPORT_SCISSOR_13_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_TL", REG_MMIO, 0xa0b0, &PA_SC_VPORT_SCISSOR_14_TL[0], sizeof(PA_SC_VPORT_SCISSOR_14_TL)/sizeof(PA_SC_VPORT_SCISSOR_14_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_BR", REG_MMIO, 0xa0b1, &PA_SC_VPORT_SCISSOR_14_BR[0], sizeof(PA_SC_VPORT_SCISSOR_14_BR)/sizeof(PA_SC_VPORT_SCISSOR_14_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_TL", REG_MMIO, 0xa0b2, &PA_SC_VPORT_SCISSOR_15_TL[0], sizeof(PA_SC_VPORT_SCISSOR_15_TL)/sizeof(PA_SC_VPORT_SCISSOR_15_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_BR", REG_MMIO, 0xa0b3, &PA_SC_VPORT_SCISSOR_15_BR[0], sizeof(PA_SC_VPORT_SCISSOR_15_BR)/sizeof(PA_SC_VPORT_SCISSOR_15_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_0", REG_MMIO, 0xa0b4, &PA_SC_VPORT_ZMIN_0[0], sizeof(PA_SC_VPORT_ZMIN_0)/sizeof(PA_SC_VPORT_ZMIN_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_0", REG_MMIO, 0xa0b5, &PA_SC_VPORT_ZMAX_0[0], sizeof(PA_SC_VPORT_ZMAX_0)/sizeof(PA_SC_VPORT_ZMAX_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_1", REG_MMIO, 0xa0b6, &PA_SC_VPORT_ZMIN_1[0], sizeof(PA_SC_VPORT_ZMIN_1)/sizeof(PA_SC_VPORT_ZMIN_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_1", REG_MMIO, 0xa0b7, &PA_SC_VPORT_ZMAX_1[0], sizeof(PA_SC_VPORT_ZMAX_1)/sizeof(PA_SC_VPORT_ZMAX_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_2", REG_MMIO, 0xa0b8, &PA_SC_VPORT_ZMIN_2[0], sizeof(PA_SC_VPORT_ZMIN_2)/sizeof(PA_SC_VPORT_ZMIN_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_2", REG_MMIO, 0xa0b9, &PA_SC_VPORT_ZMAX_2[0], sizeof(PA_SC_VPORT_ZMAX_2)/sizeof(PA_SC_VPORT_ZMAX_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_3", REG_MMIO, 0xa0ba, &PA_SC_VPORT_ZMIN_3[0], sizeof(PA_SC_VPORT_ZMIN_3)/sizeof(PA_SC_VPORT_ZMIN_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_3", REG_MMIO, 0xa0bb, &PA_SC_VPORT_ZMAX_3[0], sizeof(PA_SC_VPORT_ZMAX_3)/sizeof(PA_SC_VPORT_ZMAX_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_4", REG_MMIO, 0xa0bc, &PA_SC_VPORT_ZMIN_4[0], sizeof(PA_SC_VPORT_ZMIN_4)/sizeof(PA_SC_VPORT_ZMIN_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_4", REG_MMIO, 0xa0bd, &PA_SC_VPORT_ZMAX_4[0], sizeof(PA_SC_VPORT_ZMAX_4)/sizeof(PA_SC_VPORT_ZMAX_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_5", REG_MMIO, 0xa0be, &PA_SC_VPORT_ZMIN_5[0], sizeof(PA_SC_VPORT_ZMIN_5)/sizeof(PA_SC_VPORT_ZMIN_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_5", REG_MMIO, 0xa0bf, &PA_SC_VPORT_ZMAX_5[0], sizeof(PA_SC_VPORT_ZMAX_5)/sizeof(PA_SC_VPORT_ZMAX_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_6", REG_MMIO, 0xa0c0, &PA_SC_VPORT_ZMIN_6[0], sizeof(PA_SC_VPORT_ZMIN_6)/sizeof(PA_SC_VPORT_ZMIN_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_6", REG_MMIO, 0xa0c1, &PA_SC_VPORT_ZMAX_6[0], sizeof(PA_SC_VPORT_ZMAX_6)/sizeof(PA_SC_VPORT_ZMAX_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_7", REG_MMIO, 0xa0c2, &PA_SC_VPORT_ZMIN_7[0], sizeof(PA_SC_VPORT_ZMIN_7)/sizeof(PA_SC_VPORT_ZMIN_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_7", REG_MMIO, 0xa0c3, &PA_SC_VPORT_ZMAX_7[0], sizeof(PA_SC_VPORT_ZMAX_7)/sizeof(PA_SC_VPORT_ZMAX_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_8", REG_MMIO, 0xa0c4, &PA_SC_VPORT_ZMIN_8[0], sizeof(PA_SC_VPORT_ZMIN_8)/sizeof(PA_SC_VPORT_ZMIN_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_8", REG_MMIO, 0xa0c5, &PA_SC_VPORT_ZMAX_8[0], sizeof(PA_SC_VPORT_ZMAX_8)/sizeof(PA_SC_VPORT_ZMAX_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_9", REG_MMIO, 0xa0c6, &PA_SC_VPORT_ZMIN_9[0], sizeof(PA_SC_VPORT_ZMIN_9)/sizeof(PA_SC_VPORT_ZMIN_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_9", REG_MMIO, 0xa0c7, &PA_SC_VPORT_ZMAX_9[0], sizeof(PA_SC_VPORT_ZMAX_9)/sizeof(PA_SC_VPORT_ZMAX_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_10", REG_MMIO, 0xa0c8, &PA_SC_VPORT_ZMIN_10[0], sizeof(PA_SC_VPORT_ZMIN_10)/sizeof(PA_SC_VPORT_ZMIN_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_10", REG_MMIO, 0xa0c9, &PA_SC_VPORT_ZMAX_10[0], sizeof(PA_SC_VPORT_ZMAX_10)/sizeof(PA_SC_VPORT_ZMAX_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_11", REG_MMIO, 0xa0ca, &PA_SC_VPORT_ZMIN_11[0], sizeof(PA_SC_VPORT_ZMIN_11)/sizeof(PA_SC_VPORT_ZMIN_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_11", REG_MMIO, 0xa0cb, &PA_SC_VPORT_ZMAX_11[0], sizeof(PA_SC_VPORT_ZMAX_11)/sizeof(PA_SC_VPORT_ZMAX_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_12", REG_MMIO, 0xa0cc, &PA_SC_VPORT_ZMIN_12[0], sizeof(PA_SC_VPORT_ZMIN_12)/sizeof(PA_SC_VPORT_ZMIN_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_12", REG_MMIO, 0xa0cd, &PA_SC_VPORT_ZMAX_12[0], sizeof(PA_SC_VPORT_ZMAX_12)/sizeof(PA_SC_VPORT_ZMAX_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_13", REG_MMIO, 0xa0ce, &PA_SC_VPORT_ZMIN_13[0], sizeof(PA_SC_VPORT_ZMIN_13)/sizeof(PA_SC_VPORT_ZMIN_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_13", REG_MMIO, 0xa0cf, &PA_SC_VPORT_ZMAX_13[0], sizeof(PA_SC_VPORT_ZMAX_13)/sizeof(PA_SC_VPORT_ZMAX_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_14", REG_MMIO, 0xa0d0, &PA_SC_VPORT_ZMIN_14[0], sizeof(PA_SC_VPORT_ZMIN_14)/sizeof(PA_SC_VPORT_ZMIN_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_14", REG_MMIO, 0xa0d1, &PA_SC_VPORT_ZMAX_14[0], sizeof(PA_SC_VPORT_ZMAX_14)/sizeof(PA_SC_VPORT_ZMAX_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_15", REG_MMIO, 0xa0d2, &PA_SC_VPORT_ZMIN_15[0], sizeof(PA_SC_VPORT_ZMIN_15)/sizeof(PA_SC_VPORT_ZMIN_15[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_15", REG_MMIO, 0xa0d3, &PA_SC_VPORT_ZMAX_15[0], sizeof(PA_SC_VPORT_ZMAX_15)/sizeof(PA_SC_VPORT_ZMAX_15[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG", REG_MMIO, 0xa0d4, &PA_SC_RASTER_CONFIG[0], sizeof(PA_SC_RASTER_CONFIG)/sizeof(PA_SC_RASTER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG_1", REG_MMIO, 0xa0d5, &PA_SC_RASTER_CONFIG_1[0], sizeof(PA_SC_RASTER_CONFIG_1)/sizeof(PA_SC_RASTER_CONFIG_1[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_CONTROL", REG_MMIO, 0xa0d6, &PA_SC_SCREEN_EXTENT_CONTROL[0], sizeof(PA_SC_SCREEN_EXTENT_CONTROL)/sizeof(PA_SC_SCREEN_EXTENT_CONTROL[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTX_CNTL", REG_MMIO, 0xa0d8, &CP_PERFMON_CNTX_CNTL[0], sizeof(CP_PERFMON_CNTX_CNTL)/sizeof(CP_PERFMON_CNTX_CNTL[0]), 0, 0 },
+	{ "mmCP_RINGID", REG_MMIO, 0xa0d9, &CP_RINGID[0], sizeof(CP_RINGID)/sizeof(CP_RINGID[0]), 0, 0 },
+	{ "mmCP_VMID", REG_MMIO, 0xa0da, &CP_VMID[0], sizeof(CP_VMID)/sizeof(CP_VMID[0]), 0, 0 },
+	{ "mmVGT_MAX_VTX_INDX", REG_MMIO, 0xa100, &VGT_MAX_VTX_INDX[0], sizeof(VGT_MAX_VTX_INDX)/sizeof(VGT_MAX_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_MIN_VTX_INDX", REG_MMIO, 0xa101, &VGT_MIN_VTX_INDX[0], sizeof(VGT_MIN_VTX_INDX)/sizeof(VGT_MIN_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_INDX_OFFSET", REG_MMIO, 0xa102, &VGT_INDX_OFFSET[0], sizeof(VGT_INDX_OFFSET)/sizeof(VGT_INDX_OFFSET[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_INDX", REG_MMIO, 0xa103, &VGT_MULTI_PRIM_IB_RESET_INDX[0], sizeof(VGT_MULTI_PRIM_IB_RESET_INDX)/sizeof(VGT_MULTI_PRIM_IB_RESET_INDX[0]), 0, 0 },
+	{ "mmCB_BLEND_RED", REG_MMIO, 0xa105, &CB_BLEND_RED[0], sizeof(CB_BLEND_RED)/sizeof(CB_BLEND_RED[0]), 0, 0 },
+	{ "mmCB_BLEND_GREEN", REG_MMIO, 0xa106, &CB_BLEND_GREEN[0], sizeof(CB_BLEND_GREEN)/sizeof(CB_BLEND_GREEN[0]), 0, 0 },
+	{ "mmCB_BLEND_BLUE", REG_MMIO, 0xa107, &CB_BLEND_BLUE[0], sizeof(CB_BLEND_BLUE)/sizeof(CB_BLEND_BLUE[0]), 0, 0 },
+	{ "mmCB_BLEND_ALPHA", REG_MMIO, 0xa108, &CB_BLEND_ALPHA[0], sizeof(CB_BLEND_ALPHA)/sizeof(CB_BLEND_ALPHA[0]), 0, 0 },
+	{ "mmDB_STENCIL_CONTROL", REG_MMIO, 0xa10b, &DB_STENCIL_CONTROL[0], sizeof(DB_STENCIL_CONTROL)/sizeof(DB_STENCIL_CONTROL[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK", REG_MMIO, 0xa10c, &DB_STENCILREFMASK[0], sizeof(DB_STENCILREFMASK)/sizeof(DB_STENCILREFMASK[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK_BF", REG_MMIO, 0xa10d, &DB_STENCILREFMASK_BF[0], sizeof(DB_STENCILREFMASK_BF)/sizeof(DB_STENCILREFMASK_BF[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE", REG_MMIO, 0xa10f, &PA_CL_VPORT_XSCALE[0], sizeof(PA_CL_VPORT_XSCALE)/sizeof(PA_CL_VPORT_XSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET", REG_MMIO, 0xa110, &PA_CL_VPORT_XOFFSET[0], sizeof(PA_CL_VPORT_XOFFSET)/sizeof(PA_CL_VPORT_XOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE", REG_MMIO, 0xa111, &PA_CL_VPORT_YSCALE[0], sizeof(PA_CL_VPORT_YSCALE)/sizeof(PA_CL_VPORT_YSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET", REG_MMIO, 0xa112, &PA_CL_VPORT_YOFFSET[0], sizeof(PA_CL_VPORT_YOFFSET)/sizeof(PA_CL_VPORT_YOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE", REG_MMIO, 0xa113, &PA_CL_VPORT_ZSCALE[0], sizeof(PA_CL_VPORT_ZSCALE)/sizeof(PA_CL_VPORT_ZSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET", REG_MMIO, 0xa114, &PA_CL_VPORT_ZOFFSET[0], sizeof(PA_CL_VPORT_ZOFFSET)/sizeof(PA_CL_VPORT_ZOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_1", REG_MMIO, 0xa115, &PA_CL_VPORT_XSCALE_1[0], sizeof(PA_CL_VPORT_XSCALE_1)/sizeof(PA_CL_VPORT_XSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_1", REG_MMIO, 0xa116, &PA_CL_VPORT_XOFFSET_1[0], sizeof(PA_CL_VPORT_XOFFSET_1)/sizeof(PA_CL_VPORT_XOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_1", REG_MMIO, 0xa117, &PA_CL_VPORT_YSCALE_1[0], sizeof(PA_CL_VPORT_YSCALE_1)/sizeof(PA_CL_VPORT_YSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_1", REG_MMIO, 0xa118, &PA_CL_VPORT_YOFFSET_1[0], sizeof(PA_CL_VPORT_YOFFSET_1)/sizeof(PA_CL_VPORT_YOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_1", REG_MMIO, 0xa119, &PA_CL_VPORT_ZSCALE_1[0], sizeof(PA_CL_VPORT_ZSCALE_1)/sizeof(PA_CL_VPORT_ZSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_1", REG_MMIO, 0xa11a, &PA_CL_VPORT_ZOFFSET_1[0], sizeof(PA_CL_VPORT_ZOFFSET_1)/sizeof(PA_CL_VPORT_ZOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_2", REG_MMIO, 0xa11b, &PA_CL_VPORT_XSCALE_2[0], sizeof(PA_CL_VPORT_XSCALE_2)/sizeof(PA_CL_VPORT_XSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_2", REG_MMIO, 0xa11c, &PA_CL_VPORT_XOFFSET_2[0], sizeof(PA_CL_VPORT_XOFFSET_2)/sizeof(PA_CL_VPORT_XOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_2", REG_MMIO, 0xa11d, &PA_CL_VPORT_YSCALE_2[0], sizeof(PA_CL_VPORT_YSCALE_2)/sizeof(PA_CL_VPORT_YSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_2", REG_MMIO, 0xa11e, &PA_CL_VPORT_YOFFSET_2[0], sizeof(PA_CL_VPORT_YOFFSET_2)/sizeof(PA_CL_VPORT_YOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_2", REG_MMIO, 0xa11f, &PA_CL_VPORT_ZSCALE_2[0], sizeof(PA_CL_VPORT_ZSCALE_2)/sizeof(PA_CL_VPORT_ZSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_2", REG_MMIO, 0xa120, &PA_CL_VPORT_ZOFFSET_2[0], sizeof(PA_CL_VPORT_ZOFFSET_2)/sizeof(PA_CL_VPORT_ZOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_3", REG_MMIO, 0xa121, &PA_CL_VPORT_XSCALE_3[0], sizeof(PA_CL_VPORT_XSCALE_3)/sizeof(PA_CL_VPORT_XSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_3", REG_MMIO, 0xa122, &PA_CL_VPORT_XOFFSET_3[0], sizeof(PA_CL_VPORT_XOFFSET_3)/sizeof(PA_CL_VPORT_XOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_3", REG_MMIO, 0xa123, &PA_CL_VPORT_YSCALE_3[0], sizeof(PA_CL_VPORT_YSCALE_3)/sizeof(PA_CL_VPORT_YSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_3", REG_MMIO, 0xa124, &PA_CL_VPORT_YOFFSET_3[0], sizeof(PA_CL_VPORT_YOFFSET_3)/sizeof(PA_CL_VPORT_YOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_3", REG_MMIO, 0xa125, &PA_CL_VPORT_ZSCALE_3[0], sizeof(PA_CL_VPORT_ZSCALE_3)/sizeof(PA_CL_VPORT_ZSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_3", REG_MMIO, 0xa126, &PA_CL_VPORT_ZOFFSET_3[0], sizeof(PA_CL_VPORT_ZOFFSET_3)/sizeof(PA_CL_VPORT_ZOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_4", REG_MMIO, 0xa127, &PA_CL_VPORT_XSCALE_4[0], sizeof(PA_CL_VPORT_XSCALE_4)/sizeof(PA_CL_VPORT_XSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_4", REG_MMIO, 0xa128, &PA_CL_VPORT_XOFFSET_4[0], sizeof(PA_CL_VPORT_XOFFSET_4)/sizeof(PA_CL_VPORT_XOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_4", REG_MMIO, 0xa129, &PA_CL_VPORT_YSCALE_4[0], sizeof(PA_CL_VPORT_YSCALE_4)/sizeof(PA_CL_VPORT_YSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_4", REG_MMIO, 0xa12a, &PA_CL_VPORT_YOFFSET_4[0], sizeof(PA_CL_VPORT_YOFFSET_4)/sizeof(PA_CL_VPORT_YOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_4", REG_MMIO, 0xa12b, &PA_CL_VPORT_ZSCALE_4[0], sizeof(PA_CL_VPORT_ZSCALE_4)/sizeof(PA_CL_VPORT_ZSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_4", REG_MMIO, 0xa12c, &PA_CL_VPORT_ZOFFSET_4[0], sizeof(PA_CL_VPORT_ZOFFSET_4)/sizeof(PA_CL_VPORT_ZOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_5", REG_MMIO, 0xa12d, &PA_CL_VPORT_XSCALE_5[0], sizeof(PA_CL_VPORT_XSCALE_5)/sizeof(PA_CL_VPORT_XSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_5", REG_MMIO, 0xa12e, &PA_CL_VPORT_XOFFSET_5[0], sizeof(PA_CL_VPORT_XOFFSET_5)/sizeof(PA_CL_VPORT_XOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_5", REG_MMIO, 0xa12f, &PA_CL_VPORT_YSCALE_5[0], sizeof(PA_CL_VPORT_YSCALE_5)/sizeof(PA_CL_VPORT_YSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_5", REG_MMIO, 0xa130, &PA_CL_VPORT_YOFFSET_5[0], sizeof(PA_CL_VPORT_YOFFSET_5)/sizeof(PA_CL_VPORT_YOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_5", REG_MMIO, 0xa131, &PA_CL_VPORT_ZSCALE_5[0], sizeof(PA_CL_VPORT_ZSCALE_5)/sizeof(PA_CL_VPORT_ZSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_5", REG_MMIO, 0xa132, &PA_CL_VPORT_ZOFFSET_5[0], sizeof(PA_CL_VPORT_ZOFFSET_5)/sizeof(PA_CL_VPORT_ZOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_6", REG_MMIO, 0xa133, &PA_CL_VPORT_XSCALE_6[0], sizeof(PA_CL_VPORT_XSCALE_6)/sizeof(PA_CL_VPORT_XSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_6", REG_MMIO, 0xa134, &PA_CL_VPORT_XOFFSET_6[0], sizeof(PA_CL_VPORT_XOFFSET_6)/sizeof(PA_CL_VPORT_XOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_6", REG_MMIO, 0xa135, &PA_CL_VPORT_YSCALE_6[0], sizeof(PA_CL_VPORT_YSCALE_6)/sizeof(PA_CL_VPORT_YSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_6", REG_MMIO, 0xa136, &PA_CL_VPORT_YOFFSET_6[0], sizeof(PA_CL_VPORT_YOFFSET_6)/sizeof(PA_CL_VPORT_YOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_6", REG_MMIO, 0xa137, &PA_CL_VPORT_ZSCALE_6[0], sizeof(PA_CL_VPORT_ZSCALE_6)/sizeof(PA_CL_VPORT_ZSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_6", REG_MMIO, 0xa138, &PA_CL_VPORT_ZOFFSET_6[0], sizeof(PA_CL_VPORT_ZOFFSET_6)/sizeof(PA_CL_VPORT_ZOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_7", REG_MMIO, 0xa139, &PA_CL_VPORT_XSCALE_7[0], sizeof(PA_CL_VPORT_XSCALE_7)/sizeof(PA_CL_VPORT_XSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_7", REG_MMIO, 0xa13a, &PA_CL_VPORT_XOFFSET_7[0], sizeof(PA_CL_VPORT_XOFFSET_7)/sizeof(PA_CL_VPORT_XOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_7", REG_MMIO, 0xa13b, &PA_CL_VPORT_YSCALE_7[0], sizeof(PA_CL_VPORT_YSCALE_7)/sizeof(PA_CL_VPORT_YSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_7", REG_MMIO, 0xa13c, &PA_CL_VPORT_YOFFSET_7[0], sizeof(PA_CL_VPORT_YOFFSET_7)/sizeof(PA_CL_VPORT_YOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_7", REG_MMIO, 0xa13d, &PA_CL_VPORT_ZSCALE_7[0], sizeof(PA_CL_VPORT_ZSCALE_7)/sizeof(PA_CL_VPORT_ZSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_7", REG_MMIO, 0xa13e, &PA_CL_VPORT_ZOFFSET_7[0], sizeof(PA_CL_VPORT_ZOFFSET_7)/sizeof(PA_CL_VPORT_ZOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_8", REG_MMIO, 0xa13f, &PA_CL_VPORT_XSCALE_8[0], sizeof(PA_CL_VPORT_XSCALE_8)/sizeof(PA_CL_VPORT_XSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_8", REG_MMIO, 0xa140, &PA_CL_VPORT_XOFFSET_8[0], sizeof(PA_CL_VPORT_XOFFSET_8)/sizeof(PA_CL_VPORT_XOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_8", REG_MMIO, 0xa141, &PA_CL_VPORT_YSCALE_8[0], sizeof(PA_CL_VPORT_YSCALE_8)/sizeof(PA_CL_VPORT_YSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_8", REG_MMIO, 0xa142, &PA_CL_VPORT_YOFFSET_8[0], sizeof(PA_CL_VPORT_YOFFSET_8)/sizeof(PA_CL_VPORT_YOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_8", REG_MMIO, 0xa143, &PA_CL_VPORT_ZSCALE_8[0], sizeof(PA_CL_VPORT_ZSCALE_8)/sizeof(PA_CL_VPORT_ZSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_8", REG_MMIO, 0xa144, &PA_CL_VPORT_ZOFFSET_8[0], sizeof(PA_CL_VPORT_ZOFFSET_8)/sizeof(PA_CL_VPORT_ZOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_9", REG_MMIO, 0xa145, &PA_CL_VPORT_XSCALE_9[0], sizeof(PA_CL_VPORT_XSCALE_9)/sizeof(PA_CL_VPORT_XSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_9", REG_MMIO, 0xa146, &PA_CL_VPORT_XOFFSET_9[0], sizeof(PA_CL_VPORT_XOFFSET_9)/sizeof(PA_CL_VPORT_XOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_9", REG_MMIO, 0xa147, &PA_CL_VPORT_YSCALE_9[0], sizeof(PA_CL_VPORT_YSCALE_9)/sizeof(PA_CL_VPORT_YSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_9", REG_MMIO, 0xa148, &PA_CL_VPORT_YOFFSET_9[0], sizeof(PA_CL_VPORT_YOFFSET_9)/sizeof(PA_CL_VPORT_YOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_9", REG_MMIO, 0xa149, &PA_CL_VPORT_ZSCALE_9[0], sizeof(PA_CL_VPORT_ZSCALE_9)/sizeof(PA_CL_VPORT_ZSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_9", REG_MMIO, 0xa14a, &PA_CL_VPORT_ZOFFSET_9[0], sizeof(PA_CL_VPORT_ZOFFSET_9)/sizeof(PA_CL_VPORT_ZOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_10", REG_MMIO, 0xa14b, &PA_CL_VPORT_XSCALE_10[0], sizeof(PA_CL_VPORT_XSCALE_10)/sizeof(PA_CL_VPORT_XSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_10", REG_MMIO, 0xa14c, &PA_CL_VPORT_XOFFSET_10[0], sizeof(PA_CL_VPORT_XOFFSET_10)/sizeof(PA_CL_VPORT_XOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_10", REG_MMIO, 0xa14d, &PA_CL_VPORT_YSCALE_10[0], sizeof(PA_CL_VPORT_YSCALE_10)/sizeof(PA_CL_VPORT_YSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_10", REG_MMIO, 0xa14e, &PA_CL_VPORT_YOFFSET_10[0], sizeof(PA_CL_VPORT_YOFFSET_10)/sizeof(PA_CL_VPORT_YOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_10", REG_MMIO, 0xa14f, &PA_CL_VPORT_ZSCALE_10[0], sizeof(PA_CL_VPORT_ZSCALE_10)/sizeof(PA_CL_VPORT_ZSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_10", REG_MMIO, 0xa150, &PA_CL_VPORT_ZOFFSET_10[0], sizeof(PA_CL_VPORT_ZOFFSET_10)/sizeof(PA_CL_VPORT_ZOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_11", REG_MMIO, 0xa151, &PA_CL_VPORT_XSCALE_11[0], sizeof(PA_CL_VPORT_XSCALE_11)/sizeof(PA_CL_VPORT_XSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_11", REG_MMIO, 0xa152, &PA_CL_VPORT_XOFFSET_11[0], sizeof(PA_CL_VPORT_XOFFSET_11)/sizeof(PA_CL_VPORT_XOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_11", REG_MMIO, 0xa153, &PA_CL_VPORT_YSCALE_11[0], sizeof(PA_CL_VPORT_YSCALE_11)/sizeof(PA_CL_VPORT_YSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_11", REG_MMIO, 0xa154, &PA_CL_VPORT_YOFFSET_11[0], sizeof(PA_CL_VPORT_YOFFSET_11)/sizeof(PA_CL_VPORT_YOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_11", REG_MMIO, 0xa155, &PA_CL_VPORT_ZSCALE_11[0], sizeof(PA_CL_VPORT_ZSCALE_11)/sizeof(PA_CL_VPORT_ZSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_11", REG_MMIO, 0xa156, &PA_CL_VPORT_ZOFFSET_11[0], sizeof(PA_CL_VPORT_ZOFFSET_11)/sizeof(PA_CL_VPORT_ZOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_12", REG_MMIO, 0xa157, &PA_CL_VPORT_XSCALE_12[0], sizeof(PA_CL_VPORT_XSCALE_12)/sizeof(PA_CL_VPORT_XSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_12", REG_MMIO, 0xa158, &PA_CL_VPORT_XOFFSET_12[0], sizeof(PA_CL_VPORT_XOFFSET_12)/sizeof(PA_CL_VPORT_XOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_12", REG_MMIO, 0xa159, &PA_CL_VPORT_YSCALE_12[0], sizeof(PA_CL_VPORT_YSCALE_12)/sizeof(PA_CL_VPORT_YSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_12", REG_MMIO, 0xa15a, &PA_CL_VPORT_YOFFSET_12[0], sizeof(PA_CL_VPORT_YOFFSET_12)/sizeof(PA_CL_VPORT_YOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_12", REG_MMIO, 0xa15b, &PA_CL_VPORT_ZSCALE_12[0], sizeof(PA_CL_VPORT_ZSCALE_12)/sizeof(PA_CL_VPORT_ZSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_12", REG_MMIO, 0xa15c, &PA_CL_VPORT_ZOFFSET_12[0], sizeof(PA_CL_VPORT_ZOFFSET_12)/sizeof(PA_CL_VPORT_ZOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_13", REG_MMIO, 0xa15d, &PA_CL_VPORT_XSCALE_13[0], sizeof(PA_CL_VPORT_XSCALE_13)/sizeof(PA_CL_VPORT_XSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_13", REG_MMIO, 0xa15e, &PA_CL_VPORT_XOFFSET_13[0], sizeof(PA_CL_VPORT_XOFFSET_13)/sizeof(PA_CL_VPORT_XOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_13", REG_MMIO, 0xa15f, &PA_CL_VPORT_YSCALE_13[0], sizeof(PA_CL_VPORT_YSCALE_13)/sizeof(PA_CL_VPORT_YSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_13", REG_MMIO, 0xa160, &PA_CL_VPORT_YOFFSET_13[0], sizeof(PA_CL_VPORT_YOFFSET_13)/sizeof(PA_CL_VPORT_YOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_13", REG_MMIO, 0xa161, &PA_CL_VPORT_ZSCALE_13[0], sizeof(PA_CL_VPORT_ZSCALE_13)/sizeof(PA_CL_VPORT_ZSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_13", REG_MMIO, 0xa162, &PA_CL_VPORT_ZOFFSET_13[0], sizeof(PA_CL_VPORT_ZOFFSET_13)/sizeof(PA_CL_VPORT_ZOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_14", REG_MMIO, 0xa163, &PA_CL_VPORT_XSCALE_14[0], sizeof(PA_CL_VPORT_XSCALE_14)/sizeof(PA_CL_VPORT_XSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_14", REG_MMIO, 0xa164, &PA_CL_VPORT_XOFFSET_14[0], sizeof(PA_CL_VPORT_XOFFSET_14)/sizeof(PA_CL_VPORT_XOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_14", REG_MMIO, 0xa165, &PA_CL_VPORT_YSCALE_14[0], sizeof(PA_CL_VPORT_YSCALE_14)/sizeof(PA_CL_VPORT_YSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_14", REG_MMIO, 0xa166, &PA_CL_VPORT_YOFFSET_14[0], sizeof(PA_CL_VPORT_YOFFSET_14)/sizeof(PA_CL_VPORT_YOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_14", REG_MMIO, 0xa167, &PA_CL_VPORT_ZSCALE_14[0], sizeof(PA_CL_VPORT_ZSCALE_14)/sizeof(PA_CL_VPORT_ZSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_14", REG_MMIO, 0xa168, &PA_CL_VPORT_ZOFFSET_14[0], sizeof(PA_CL_VPORT_ZOFFSET_14)/sizeof(PA_CL_VPORT_ZOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_15", REG_MMIO, 0xa169, &PA_CL_VPORT_XSCALE_15[0], sizeof(PA_CL_VPORT_XSCALE_15)/sizeof(PA_CL_VPORT_XSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_15", REG_MMIO, 0xa16a, &PA_CL_VPORT_XOFFSET_15[0], sizeof(PA_CL_VPORT_XOFFSET_15)/sizeof(PA_CL_VPORT_XOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_15", REG_MMIO, 0xa16b, &PA_CL_VPORT_YSCALE_15[0], sizeof(PA_CL_VPORT_YSCALE_15)/sizeof(PA_CL_VPORT_YSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_15", REG_MMIO, 0xa16c, &PA_CL_VPORT_YOFFSET_15[0], sizeof(PA_CL_VPORT_YOFFSET_15)/sizeof(PA_CL_VPORT_YOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_15", REG_MMIO, 0xa16d, &PA_CL_VPORT_ZSCALE_15[0], sizeof(PA_CL_VPORT_ZSCALE_15)/sizeof(PA_CL_VPORT_ZSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_15", REG_MMIO, 0xa16e, &PA_CL_VPORT_ZOFFSET_15[0], sizeof(PA_CL_VPORT_ZOFFSET_15)/sizeof(PA_CL_VPORT_ZOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_X", REG_MMIO, 0xa16f, &PA_CL_UCP_0_X[0], sizeof(PA_CL_UCP_0_X)/sizeof(PA_CL_UCP_0_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Y", REG_MMIO, 0xa170, &PA_CL_UCP_0_Y[0], sizeof(PA_CL_UCP_0_Y)/sizeof(PA_CL_UCP_0_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Z", REG_MMIO, 0xa171, &PA_CL_UCP_0_Z[0], sizeof(PA_CL_UCP_0_Z)/sizeof(PA_CL_UCP_0_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_W", REG_MMIO, 0xa172, &PA_CL_UCP_0_W[0], sizeof(PA_CL_UCP_0_W)/sizeof(PA_CL_UCP_0_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_X", REG_MMIO, 0xa173, &PA_CL_UCP_1_X[0], sizeof(PA_CL_UCP_1_X)/sizeof(PA_CL_UCP_1_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Y", REG_MMIO, 0xa174, &PA_CL_UCP_1_Y[0], sizeof(PA_CL_UCP_1_Y)/sizeof(PA_CL_UCP_1_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Z", REG_MMIO, 0xa175, &PA_CL_UCP_1_Z[0], sizeof(PA_CL_UCP_1_Z)/sizeof(PA_CL_UCP_1_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_W", REG_MMIO, 0xa176, &PA_CL_UCP_1_W[0], sizeof(PA_CL_UCP_1_W)/sizeof(PA_CL_UCP_1_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_X", REG_MMIO, 0xa177, &PA_CL_UCP_2_X[0], sizeof(PA_CL_UCP_2_X)/sizeof(PA_CL_UCP_2_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Y", REG_MMIO, 0xa178, &PA_CL_UCP_2_Y[0], sizeof(PA_CL_UCP_2_Y)/sizeof(PA_CL_UCP_2_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Z", REG_MMIO, 0xa179, &PA_CL_UCP_2_Z[0], sizeof(PA_CL_UCP_2_Z)/sizeof(PA_CL_UCP_2_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_W", REG_MMIO, 0xa17a, &PA_CL_UCP_2_W[0], sizeof(PA_CL_UCP_2_W)/sizeof(PA_CL_UCP_2_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_X", REG_MMIO, 0xa17b, &PA_CL_UCP_3_X[0], sizeof(PA_CL_UCP_3_X)/sizeof(PA_CL_UCP_3_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Y", REG_MMIO, 0xa17c, &PA_CL_UCP_3_Y[0], sizeof(PA_CL_UCP_3_Y)/sizeof(PA_CL_UCP_3_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Z", REG_MMIO, 0xa17d, &PA_CL_UCP_3_Z[0], sizeof(PA_CL_UCP_3_Z)/sizeof(PA_CL_UCP_3_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_W", REG_MMIO, 0xa17e, &PA_CL_UCP_3_W[0], sizeof(PA_CL_UCP_3_W)/sizeof(PA_CL_UCP_3_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_X", REG_MMIO, 0xa17f, &PA_CL_UCP_4_X[0], sizeof(PA_CL_UCP_4_X)/sizeof(PA_CL_UCP_4_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Y", REG_MMIO, 0xa180, &PA_CL_UCP_4_Y[0], sizeof(PA_CL_UCP_4_Y)/sizeof(PA_CL_UCP_4_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Z", REG_MMIO, 0xa181, &PA_CL_UCP_4_Z[0], sizeof(PA_CL_UCP_4_Z)/sizeof(PA_CL_UCP_4_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_W", REG_MMIO, 0xa182, &PA_CL_UCP_4_W[0], sizeof(PA_CL_UCP_4_W)/sizeof(PA_CL_UCP_4_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_X", REG_MMIO, 0xa183, &PA_CL_UCP_5_X[0], sizeof(PA_CL_UCP_5_X)/sizeof(PA_CL_UCP_5_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Y", REG_MMIO, 0xa184, &PA_CL_UCP_5_Y[0], sizeof(PA_CL_UCP_5_Y)/sizeof(PA_CL_UCP_5_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Z", REG_MMIO, 0xa185, &PA_CL_UCP_5_Z[0], sizeof(PA_CL_UCP_5_Z)/sizeof(PA_CL_UCP_5_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_W", REG_MMIO, 0xa186, &PA_CL_UCP_5_W[0], sizeof(PA_CL_UCP_5_W)/sizeof(PA_CL_UCP_5_W[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_0", REG_MMIO, 0xa191, &SPI_PS_INPUT_CNTL_0[0], sizeof(SPI_PS_INPUT_CNTL_0)/sizeof(SPI_PS_INPUT_CNTL_0[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_1", REG_MMIO, 0xa192, &SPI_PS_INPUT_CNTL_1[0], sizeof(SPI_PS_INPUT_CNTL_1)/sizeof(SPI_PS_INPUT_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_2", REG_MMIO, 0xa193, &SPI_PS_INPUT_CNTL_2[0], sizeof(SPI_PS_INPUT_CNTL_2)/sizeof(SPI_PS_INPUT_CNTL_2[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_3", REG_MMIO, 0xa194, &SPI_PS_INPUT_CNTL_3[0], sizeof(SPI_PS_INPUT_CNTL_3)/sizeof(SPI_PS_INPUT_CNTL_3[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_4", REG_MMIO, 0xa195, &SPI_PS_INPUT_CNTL_4[0], sizeof(SPI_PS_INPUT_CNTL_4)/sizeof(SPI_PS_INPUT_CNTL_4[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_5", REG_MMIO, 0xa196, &SPI_PS_INPUT_CNTL_5[0], sizeof(SPI_PS_INPUT_CNTL_5)/sizeof(SPI_PS_INPUT_CNTL_5[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_6", REG_MMIO, 0xa197, &SPI_PS_INPUT_CNTL_6[0], sizeof(SPI_PS_INPUT_CNTL_6)/sizeof(SPI_PS_INPUT_CNTL_6[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_7", REG_MMIO, 0xa198, &SPI_PS_INPUT_CNTL_7[0], sizeof(SPI_PS_INPUT_CNTL_7)/sizeof(SPI_PS_INPUT_CNTL_7[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_8", REG_MMIO, 0xa199, &SPI_PS_INPUT_CNTL_8[0], sizeof(SPI_PS_INPUT_CNTL_8)/sizeof(SPI_PS_INPUT_CNTL_8[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_9", REG_MMIO, 0xa19a, &SPI_PS_INPUT_CNTL_9[0], sizeof(SPI_PS_INPUT_CNTL_9)/sizeof(SPI_PS_INPUT_CNTL_9[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_10", REG_MMIO, 0xa19b, &SPI_PS_INPUT_CNTL_10[0], sizeof(SPI_PS_INPUT_CNTL_10)/sizeof(SPI_PS_INPUT_CNTL_10[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_11", REG_MMIO, 0xa19c, &SPI_PS_INPUT_CNTL_11[0], sizeof(SPI_PS_INPUT_CNTL_11)/sizeof(SPI_PS_INPUT_CNTL_11[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_12", REG_MMIO, 0xa19d, &SPI_PS_INPUT_CNTL_12[0], sizeof(SPI_PS_INPUT_CNTL_12)/sizeof(SPI_PS_INPUT_CNTL_12[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_13", REG_MMIO, 0xa19e, &SPI_PS_INPUT_CNTL_13[0], sizeof(SPI_PS_INPUT_CNTL_13)/sizeof(SPI_PS_INPUT_CNTL_13[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_14", REG_MMIO, 0xa19f, &SPI_PS_INPUT_CNTL_14[0], sizeof(SPI_PS_INPUT_CNTL_14)/sizeof(SPI_PS_INPUT_CNTL_14[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_15", REG_MMIO, 0xa1a0, &SPI_PS_INPUT_CNTL_15[0], sizeof(SPI_PS_INPUT_CNTL_15)/sizeof(SPI_PS_INPUT_CNTL_15[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_16", REG_MMIO, 0xa1a1, &SPI_PS_INPUT_CNTL_16[0], sizeof(SPI_PS_INPUT_CNTL_16)/sizeof(SPI_PS_INPUT_CNTL_16[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_17", REG_MMIO, 0xa1a2, &SPI_PS_INPUT_CNTL_17[0], sizeof(SPI_PS_INPUT_CNTL_17)/sizeof(SPI_PS_INPUT_CNTL_17[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_18", REG_MMIO, 0xa1a3, &SPI_PS_INPUT_CNTL_18[0], sizeof(SPI_PS_INPUT_CNTL_18)/sizeof(SPI_PS_INPUT_CNTL_18[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_19", REG_MMIO, 0xa1a4, &SPI_PS_INPUT_CNTL_19[0], sizeof(SPI_PS_INPUT_CNTL_19)/sizeof(SPI_PS_INPUT_CNTL_19[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_20", REG_MMIO, 0xa1a5, &SPI_PS_INPUT_CNTL_20[0], sizeof(SPI_PS_INPUT_CNTL_20)/sizeof(SPI_PS_INPUT_CNTL_20[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_21", REG_MMIO, 0xa1a6, &SPI_PS_INPUT_CNTL_21[0], sizeof(SPI_PS_INPUT_CNTL_21)/sizeof(SPI_PS_INPUT_CNTL_21[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_22", REG_MMIO, 0xa1a7, &SPI_PS_INPUT_CNTL_22[0], sizeof(SPI_PS_INPUT_CNTL_22)/sizeof(SPI_PS_INPUT_CNTL_22[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_23", REG_MMIO, 0xa1a8, &SPI_PS_INPUT_CNTL_23[0], sizeof(SPI_PS_INPUT_CNTL_23)/sizeof(SPI_PS_INPUT_CNTL_23[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_24", REG_MMIO, 0xa1a9, &SPI_PS_INPUT_CNTL_24[0], sizeof(SPI_PS_INPUT_CNTL_24)/sizeof(SPI_PS_INPUT_CNTL_24[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_25", REG_MMIO, 0xa1aa, &SPI_PS_INPUT_CNTL_25[0], sizeof(SPI_PS_INPUT_CNTL_25)/sizeof(SPI_PS_INPUT_CNTL_25[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_26", REG_MMIO, 0xa1ab, &SPI_PS_INPUT_CNTL_26[0], sizeof(SPI_PS_INPUT_CNTL_26)/sizeof(SPI_PS_INPUT_CNTL_26[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_27", REG_MMIO, 0xa1ac, &SPI_PS_INPUT_CNTL_27[0], sizeof(SPI_PS_INPUT_CNTL_27)/sizeof(SPI_PS_INPUT_CNTL_27[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_28", REG_MMIO, 0xa1ad, &SPI_PS_INPUT_CNTL_28[0], sizeof(SPI_PS_INPUT_CNTL_28)/sizeof(SPI_PS_INPUT_CNTL_28[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_29", REG_MMIO, 0xa1ae, &SPI_PS_INPUT_CNTL_29[0], sizeof(SPI_PS_INPUT_CNTL_29)/sizeof(SPI_PS_INPUT_CNTL_29[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_30", REG_MMIO, 0xa1af, &SPI_PS_INPUT_CNTL_30[0], sizeof(SPI_PS_INPUT_CNTL_30)/sizeof(SPI_PS_INPUT_CNTL_30[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_31", REG_MMIO, 0xa1b0, &SPI_PS_INPUT_CNTL_31[0], sizeof(SPI_PS_INPUT_CNTL_31)/sizeof(SPI_PS_INPUT_CNTL_31[0]), 0, 0 },
+	{ "mmSPI_VS_OUT_CONFIG", REG_MMIO, 0xa1b1, &SPI_VS_OUT_CONFIG[0], sizeof(SPI_VS_OUT_CONFIG)/sizeof(SPI_VS_OUT_CONFIG[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ENA", REG_MMIO, 0xa1b3, &SPI_PS_INPUT_ENA[0], sizeof(SPI_PS_INPUT_ENA)/sizeof(SPI_PS_INPUT_ENA[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ADDR", REG_MMIO, 0xa1b4, &SPI_PS_INPUT_ADDR[0], sizeof(SPI_PS_INPUT_ADDR)/sizeof(SPI_PS_INPUT_ADDR[0]), 0, 0 },
+	{ "mmSPI_INTERP_CONTROL_0", REG_MMIO, 0xa1b5, &SPI_INTERP_CONTROL_0[0], sizeof(SPI_INTERP_CONTROL_0)/sizeof(SPI_INTERP_CONTROL_0[0]), 0, 0 },
+	{ "mmSPI_PS_IN_CONTROL", REG_MMIO, 0xa1b6, &SPI_PS_IN_CONTROL[0], sizeof(SPI_PS_IN_CONTROL)/sizeof(SPI_PS_IN_CONTROL[0]), 0, 0 },
+	{ "mmSPI_BARYC_CNTL", REG_MMIO, 0xa1b8, &SPI_BARYC_CNTL[0], sizeof(SPI_BARYC_CNTL)/sizeof(SPI_BARYC_CNTL[0]), 0, 0 },
+	{ "mmSPI_TMPRING_SIZE", REG_MMIO, 0xa1ba, &SPI_TMPRING_SIZE[0], sizeof(SPI_TMPRING_SIZE)/sizeof(SPI_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmSPI_SHADER_POS_FORMAT", REG_MMIO, 0xa1c3, &SPI_SHADER_POS_FORMAT[0], sizeof(SPI_SHADER_POS_FORMAT)/sizeof(SPI_SHADER_POS_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_Z_FORMAT", REG_MMIO, 0xa1c4, &SPI_SHADER_Z_FORMAT[0], sizeof(SPI_SHADER_Z_FORMAT)/sizeof(SPI_SHADER_Z_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_COL_FORMAT", REG_MMIO, 0xa1c5, &SPI_SHADER_COL_FORMAT[0], sizeof(SPI_SHADER_COL_FORMAT)/sizeof(SPI_SHADER_COL_FORMAT[0]), 0, 0 },
+	{ "mmCB_BLEND0_CONTROL", REG_MMIO, 0xa1e0, &CB_BLEND0_CONTROL[0], sizeof(CB_BLEND0_CONTROL)/sizeof(CB_BLEND0_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND1_CONTROL", REG_MMIO, 0xa1e1, &CB_BLEND1_CONTROL[0], sizeof(CB_BLEND1_CONTROL)/sizeof(CB_BLEND1_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND2_CONTROL", REG_MMIO, 0xa1e2, &CB_BLEND2_CONTROL[0], sizeof(CB_BLEND2_CONTROL)/sizeof(CB_BLEND2_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND3_CONTROL", REG_MMIO, 0xa1e3, &CB_BLEND3_CONTROL[0], sizeof(CB_BLEND3_CONTROL)/sizeof(CB_BLEND3_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND4_CONTROL", REG_MMIO, 0xa1e4, &CB_BLEND4_CONTROL[0], sizeof(CB_BLEND4_CONTROL)/sizeof(CB_BLEND4_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND5_CONTROL", REG_MMIO, 0xa1e5, &CB_BLEND5_CONTROL[0], sizeof(CB_BLEND5_CONTROL)/sizeof(CB_BLEND5_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND6_CONTROL", REG_MMIO, 0xa1e6, &CB_BLEND6_CONTROL[0], sizeof(CB_BLEND6_CONTROL)/sizeof(CB_BLEND6_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND7_CONTROL", REG_MMIO, 0xa1e7, &CB_BLEND7_CONTROL[0], sizeof(CB_BLEND7_CONTROL)/sizeof(CB_BLEND7_CONTROL[0]), 0, 0 },
+	{ "mmCS_COPY_STATE", REG_MMIO, 0xa1f3, &CS_COPY_STATE[0], sizeof(CS_COPY_STATE)/sizeof(CS_COPY_STATE[0]), 0, 0 },
+	{ "mmGFX_COPY_STATE", REG_MMIO, 0xa1f4, &GFX_COPY_STATE[0], sizeof(GFX_COPY_STATE)/sizeof(GFX_COPY_STATE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_X_RAD", REG_MMIO, 0xa1f5, &PA_CL_POINT_X_RAD[0], sizeof(PA_CL_POINT_X_RAD)/sizeof(PA_CL_POINT_X_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_Y_RAD", REG_MMIO, 0xa1f6, &PA_CL_POINT_Y_RAD[0], sizeof(PA_CL_POINT_Y_RAD)/sizeof(PA_CL_POINT_Y_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_SIZE", REG_MMIO, 0xa1f7, &PA_CL_POINT_SIZE[0], sizeof(PA_CL_POINT_SIZE)/sizeof(PA_CL_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_CULL_RAD", REG_MMIO, 0xa1f8, &PA_CL_POINT_CULL_RAD[0], sizeof(PA_CL_POINT_CULL_RAD)/sizeof(PA_CL_POINT_CULL_RAD[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE_HI", REG_MMIO, 0xa1f9, &VGT_DMA_BASE_HI[0], sizeof(VGT_DMA_BASE_HI)/sizeof(VGT_DMA_BASE_HI[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE", REG_MMIO, 0xa1fa, &VGT_DMA_BASE[0], sizeof(VGT_DMA_BASE)/sizeof(VGT_DMA_BASE[0]), 0, 0 },
+	{ "mmVGT_DRAW_INITIATOR", REG_MMIO, 0xa1fc, &VGT_DRAW_INITIATOR[0], sizeof(VGT_DRAW_INITIATOR)/sizeof(VGT_DRAW_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_IMMED_DATA", REG_MMIO, 0xa1fd, &VGT_IMMED_DATA[0], sizeof(VGT_IMMED_DATA)/sizeof(VGT_IMMED_DATA[0]), 0, 0 },
+	{ "mmVGT_EVENT_ADDRESS_REG", REG_MMIO, 0xa1fe, &VGT_EVENT_ADDRESS_REG[0], sizeof(VGT_EVENT_ADDRESS_REG)/sizeof(VGT_EVENT_ADDRESS_REG[0]), 0, 0 },
+	{ "mmDB_DEPTH_CONTROL", REG_MMIO, 0xa200, &DB_DEPTH_CONTROL[0], sizeof(DB_DEPTH_CONTROL)/sizeof(DB_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmDB_EQAA", REG_MMIO, 0xa201, &DB_EQAA[0], sizeof(DB_EQAA)/sizeof(DB_EQAA[0]), 0, 0 },
+	{ "mmCB_COLOR_CONTROL", REG_MMIO, 0xa202, &CB_COLOR_CONTROL[0], sizeof(CB_COLOR_CONTROL)/sizeof(CB_COLOR_CONTROL[0]), 0, 0 },
+	{ "mmDB_SHADER_CONTROL", REG_MMIO, 0xa203, &DB_SHADER_CONTROL[0], sizeof(DB_SHADER_CONTROL)/sizeof(DB_SHADER_CONTROL[0]), 0, 0 },
+	{ "mmPA_CL_CLIP_CNTL", REG_MMIO, 0xa204, &PA_CL_CLIP_CNTL[0], sizeof(PA_CL_CLIP_CNTL)/sizeof(PA_CL_CLIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_SC_MODE_CNTL", REG_MMIO, 0xa205, &PA_SU_SC_MODE_CNTL[0], sizeof(PA_SU_SC_MODE_CNTL)/sizeof(PA_SU_SC_MODE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VTE_CNTL", REG_MMIO, 0xa206, &PA_CL_VTE_CNTL[0], sizeof(PA_CL_VTE_CNTL)/sizeof(PA_CL_VTE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VS_OUT_CNTL", REG_MMIO, 0xa207, &PA_CL_VS_OUT_CNTL[0], sizeof(PA_CL_VS_OUT_CNTL)/sizeof(PA_CL_VS_OUT_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_NANINF_CNTL", REG_MMIO, 0xa208, &PA_CL_NANINF_CNTL[0], sizeof(PA_CL_NANINF_CNTL)/sizeof(PA_CL_NANINF_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_CNTL", REG_MMIO, 0xa209, &PA_SU_LINE_STIPPLE_CNTL[0], sizeof(PA_SU_LINE_STIPPLE_CNTL)/sizeof(PA_SU_LINE_STIPPLE_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_SCALE", REG_MMIO, 0xa20a, &PA_SU_LINE_STIPPLE_SCALE[0], sizeof(PA_SU_LINE_STIPPLE_SCALE)/sizeof(PA_SU_LINE_STIPPLE_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_PRIM_FILTER_CNTL", REG_MMIO, 0xa20b, &PA_SU_PRIM_FILTER_CNTL[0], sizeof(PA_SU_PRIM_FILTER_CNTL)/sizeof(PA_SU_PRIM_FILTER_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POINT_SIZE", REG_MMIO, 0xa280, &PA_SU_POINT_SIZE[0], sizeof(PA_SU_POINT_SIZE)/sizeof(PA_SU_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_SU_POINT_MINMAX", REG_MMIO, 0xa281, &PA_SU_POINT_MINMAX[0], sizeof(PA_SU_POINT_MINMAX)/sizeof(PA_SU_POINT_MINMAX[0]), 0, 0 },
+	{ "mmPA_SU_LINE_CNTL", REG_MMIO, 0xa282, &PA_SU_LINE_CNTL[0], sizeof(PA_SU_LINE_CNTL)/sizeof(PA_SU_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE", REG_MMIO, 0xa283, &PA_SC_LINE_STIPPLE[0], sizeof(PA_SC_LINE_STIPPLE)/sizeof(PA_SC_LINE_STIPPLE[0]), 0, 0 },
+	{ "mmVGT_OUTPUT_PATH_CNTL", REG_MMIO, 0xa284, &VGT_OUTPUT_PATH_CNTL[0], sizeof(VGT_OUTPUT_PATH_CNTL)/sizeof(VGT_OUTPUT_PATH_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_CNTL", REG_MMIO, 0xa285, &VGT_HOS_CNTL[0], sizeof(VGT_HOS_CNTL)/sizeof(VGT_HOS_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_MAX_TESS_LEVEL", REG_MMIO, 0xa286, &VGT_HOS_MAX_TESS_LEVEL[0], sizeof(VGT_HOS_MAX_TESS_LEVEL)/sizeof(VGT_HOS_MAX_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_MIN_TESS_LEVEL", REG_MMIO, 0xa287, &VGT_HOS_MIN_TESS_LEVEL[0], sizeof(VGT_HOS_MIN_TESS_LEVEL)/sizeof(VGT_HOS_MIN_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_REUSE_DEPTH", REG_MMIO, 0xa288, &VGT_HOS_REUSE_DEPTH[0], sizeof(VGT_HOS_REUSE_DEPTH)/sizeof(VGT_HOS_REUSE_DEPTH[0]), 0, 0 },
+	{ "mmVGT_GROUP_PRIM_TYPE", REG_MMIO, 0xa289, &VGT_GROUP_PRIM_TYPE[0], sizeof(VGT_GROUP_PRIM_TYPE)/sizeof(VGT_GROUP_PRIM_TYPE[0]), 0, 0 },
+	{ "mmVGT_GROUP_FIRST_DECR", REG_MMIO, 0xa28a, &VGT_GROUP_FIRST_DECR[0], sizeof(VGT_GROUP_FIRST_DECR)/sizeof(VGT_GROUP_FIRST_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_DECR", REG_MMIO, 0xa28b, &VGT_GROUP_DECR[0], sizeof(VGT_GROUP_DECR)/sizeof(VGT_GROUP_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_CNTL", REG_MMIO, 0xa28c, &VGT_GROUP_VECT_0_CNTL[0], sizeof(VGT_GROUP_VECT_0_CNTL)/sizeof(VGT_GROUP_VECT_0_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_CNTL", REG_MMIO, 0xa28d, &VGT_GROUP_VECT_1_CNTL[0], sizeof(VGT_GROUP_VECT_1_CNTL)/sizeof(VGT_GROUP_VECT_1_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_FMT_CNTL", REG_MMIO, 0xa28e, &VGT_GROUP_VECT_0_FMT_CNTL[0], sizeof(VGT_GROUP_VECT_0_FMT_CNTL)/sizeof(VGT_GROUP_VECT_0_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_FMT_CNTL", REG_MMIO, 0xa28f, &VGT_GROUP_VECT_1_FMT_CNTL[0], sizeof(VGT_GROUP_VECT_1_FMT_CNTL)/sizeof(VGT_GROUP_VECT_1_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GS_MODE", REG_MMIO, 0xa290, &VGT_GS_MODE[0], sizeof(VGT_GS_MODE)/sizeof(VGT_GS_MODE[0]), 0, 0 },
+	{ "mmVGT_GS_ONCHIP_CNTL", REG_MMIO, 0xa291, &VGT_GS_ONCHIP_CNTL[0], sizeof(VGT_GS_ONCHIP_CNTL)/sizeof(VGT_GS_ONCHIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_0", REG_MMIO, 0xa292, &PA_SC_MODE_CNTL_0[0], sizeof(PA_SC_MODE_CNTL_0)/sizeof(PA_SC_MODE_CNTL_0[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_1", REG_MMIO, 0xa293, &PA_SC_MODE_CNTL_1[0], sizeof(PA_SC_MODE_CNTL_1)/sizeof(PA_SC_MODE_CNTL_1[0]), 0, 0 },
+	{ "mmVGT_ENHANCE", REG_MMIO, 0xa294, &VGT_ENHANCE[0], sizeof(VGT_ENHANCE)/sizeof(VGT_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_GS_PER_ES", REG_MMIO, 0xa295, &VGT_GS_PER_ES[0], sizeof(VGT_GS_PER_ES)/sizeof(VGT_GS_PER_ES[0]), 0, 0 },
+	{ "mmVGT_ES_PER_GS", REG_MMIO, 0xa296, &VGT_ES_PER_GS[0], sizeof(VGT_ES_PER_GS)/sizeof(VGT_ES_PER_GS[0]), 0, 0 },
+	{ "mmVGT_GS_PER_VS", REG_MMIO, 0xa297, &VGT_GS_PER_VS[0], sizeof(VGT_GS_PER_VS)/sizeof(VGT_GS_PER_VS[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_1", REG_MMIO, 0xa298, &VGT_GSVS_RING_OFFSET_1[0], sizeof(VGT_GSVS_RING_OFFSET_1)/sizeof(VGT_GSVS_RING_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_2", REG_MMIO, 0xa299, &VGT_GSVS_RING_OFFSET_2[0], sizeof(VGT_GSVS_RING_OFFSET_2)/sizeof(VGT_GSVS_RING_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_3", REG_MMIO, 0xa29a, &VGT_GSVS_RING_OFFSET_3[0], sizeof(VGT_GSVS_RING_OFFSET_3)/sizeof(VGT_GSVS_RING_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_GS_OUT_PRIM_TYPE", REG_MMIO, 0xa29b, &VGT_GS_OUT_PRIM_TYPE[0], sizeof(VGT_GS_OUT_PRIM_TYPE)/sizeof(VGT_GS_OUT_PRIM_TYPE[0]), 0, 0 },
+	{ "mmIA_ENHANCE", REG_MMIO, 0xa29c, &IA_ENHANCE[0], sizeof(IA_ENHANCE)/sizeof(IA_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_DMA_SIZE", REG_MMIO, 0xa29d, &VGT_DMA_SIZE[0], sizeof(VGT_DMA_SIZE)/sizeof(VGT_DMA_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_MAX_SIZE", REG_MMIO, 0xa29e, &VGT_DMA_MAX_SIZE[0], sizeof(VGT_DMA_MAX_SIZE)/sizeof(VGT_DMA_MAX_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_INDEX_TYPE", REG_MMIO, 0xa29f, &VGT_DMA_INDEX_TYPE[0], sizeof(VGT_DMA_INDEX_TYPE)/sizeof(VGT_DMA_INDEX_TYPE[0]), 0, 0 },
+	{ "mmWD_ENHANCE", REG_MMIO, 0xa2a0, &WD_ENHANCE[0], sizeof(WD_ENHANCE)/sizeof(WD_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_EN", REG_MMIO, 0xa2a1, &VGT_PRIMITIVEID_EN[0], sizeof(VGT_PRIMITIVEID_EN)/sizeof(VGT_PRIMITIVEID_EN[0]), 0, 0 },
+	{ "mmVGT_DMA_NUM_INSTANCES", REG_MMIO, 0xa2a2, &VGT_DMA_NUM_INSTANCES[0], sizeof(VGT_DMA_NUM_INSTANCES)/sizeof(VGT_DMA_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_RESET", REG_MMIO, 0xa2a3, &VGT_PRIMITIVEID_RESET[0], sizeof(VGT_PRIMITIVEID_RESET)/sizeof(VGT_PRIMITIVEID_RESET[0]), 0, 0 },
+	{ "mmVGT_EVENT_INITIATOR", REG_MMIO, 0xa2a4, &VGT_EVENT_INITIATOR[0], sizeof(VGT_EVENT_INITIATOR)/sizeof(VGT_EVENT_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_EN", REG_MMIO, 0xa2a5, &VGT_MULTI_PRIM_IB_RESET_EN[0], sizeof(VGT_MULTI_PRIM_IB_RESET_EN)/sizeof(VGT_MULTI_PRIM_IB_RESET_EN[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_0", REG_MMIO, 0xa2a8, &VGT_INSTANCE_STEP_RATE_0[0], sizeof(VGT_INSTANCE_STEP_RATE_0)/sizeof(VGT_INSTANCE_STEP_RATE_0[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_1", REG_MMIO, 0xa2a9, &VGT_INSTANCE_STEP_RATE_1[0], sizeof(VGT_INSTANCE_STEP_RATE_1)/sizeof(VGT_INSTANCE_STEP_RATE_1[0]), 0, 0 },
+	{ "mmIA_MULTI_VGT_PARAM", REG_MMIO, 0xa2aa, &IA_MULTI_VGT_PARAM[0], sizeof(IA_MULTI_VGT_PARAM)/sizeof(IA_MULTI_VGT_PARAM[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_ITEMSIZE", REG_MMIO, 0xa2ab, &VGT_ESGS_RING_ITEMSIZE[0], sizeof(VGT_ESGS_RING_ITEMSIZE)/sizeof(VGT_ESGS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_ITEMSIZE", REG_MMIO, 0xa2ac, &VGT_GSVS_RING_ITEMSIZE[0], sizeof(VGT_GSVS_RING_ITEMSIZE)/sizeof(VGT_GSVS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_REUSE_OFF", REG_MMIO, 0xa2ad, &VGT_REUSE_OFF[0], sizeof(VGT_REUSE_OFF)/sizeof(VGT_REUSE_OFF[0]), 0, 0 },
+	{ "mmVGT_VTX_CNT_EN", REG_MMIO, 0xa2ae, &VGT_VTX_CNT_EN[0], sizeof(VGT_VTX_CNT_EN)/sizeof(VGT_VTX_CNT_EN[0]), 0, 0 },
+	{ "mmDB_HTILE_SURFACE", REG_MMIO, 0xa2af, &DB_HTILE_SURFACE[0], sizeof(DB_HTILE_SURFACE)/sizeof(DB_HTILE_SURFACE[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE0", REG_MMIO, 0xa2b0, &DB_SRESULTS_COMPARE_STATE0[0], sizeof(DB_SRESULTS_COMPARE_STATE0)/sizeof(DB_SRESULTS_COMPARE_STATE0[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE1", REG_MMIO, 0xa2b1, &DB_SRESULTS_COMPARE_STATE1[0], sizeof(DB_SRESULTS_COMPARE_STATE1)/sizeof(DB_SRESULTS_COMPARE_STATE1[0]), 0, 0 },
+	{ "mmDB_PRELOAD_CONTROL", REG_MMIO, 0xa2b2, &DB_PRELOAD_CONTROL[0], sizeof(DB_PRELOAD_CONTROL)/sizeof(DB_PRELOAD_CONTROL[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_0", REG_MMIO, 0xa2b4, &VGT_STRMOUT_BUFFER_SIZE_0[0], sizeof(VGT_STRMOUT_BUFFER_SIZE_0)/sizeof(VGT_STRMOUT_BUFFER_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_0", REG_MMIO, 0xa2b5, &VGT_STRMOUT_VTX_STRIDE_0[0], sizeof(VGT_STRMOUT_VTX_STRIDE_0)/sizeof(VGT_STRMOUT_VTX_STRIDE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_0", REG_MMIO, 0xa2b7, &VGT_STRMOUT_BUFFER_OFFSET_0[0], sizeof(VGT_STRMOUT_BUFFER_OFFSET_0)/sizeof(VGT_STRMOUT_BUFFER_OFFSET_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_1", REG_MMIO, 0xa2b8, &VGT_STRMOUT_BUFFER_SIZE_1[0], sizeof(VGT_STRMOUT_BUFFER_SIZE_1)/sizeof(VGT_STRMOUT_BUFFER_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_1", REG_MMIO, 0xa2b9, &VGT_STRMOUT_VTX_STRIDE_1[0], sizeof(VGT_STRMOUT_VTX_STRIDE_1)/sizeof(VGT_STRMOUT_VTX_STRIDE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_1", REG_MMIO, 0xa2bb, &VGT_STRMOUT_BUFFER_OFFSET_1[0], sizeof(VGT_STRMOUT_BUFFER_OFFSET_1)/sizeof(VGT_STRMOUT_BUFFER_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_2", REG_MMIO, 0xa2bc, &VGT_STRMOUT_BUFFER_SIZE_2[0], sizeof(VGT_STRMOUT_BUFFER_SIZE_2)/sizeof(VGT_STRMOUT_BUFFER_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_2", REG_MMIO, 0xa2bd, &VGT_STRMOUT_VTX_STRIDE_2[0], sizeof(VGT_STRMOUT_VTX_STRIDE_2)/sizeof(VGT_STRMOUT_VTX_STRIDE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_2", REG_MMIO, 0xa2bf, &VGT_STRMOUT_BUFFER_OFFSET_2[0], sizeof(VGT_STRMOUT_BUFFER_OFFSET_2)/sizeof(VGT_STRMOUT_BUFFER_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_3", REG_MMIO, 0xa2c0, &VGT_STRMOUT_BUFFER_SIZE_3[0], sizeof(VGT_STRMOUT_BUFFER_SIZE_3)/sizeof(VGT_STRMOUT_BUFFER_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_3", REG_MMIO, 0xa2c1, &VGT_STRMOUT_VTX_STRIDE_3[0], sizeof(VGT_STRMOUT_VTX_STRIDE_3)/sizeof(VGT_STRMOUT_VTX_STRIDE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_3", REG_MMIO, 0xa2c3, &VGT_STRMOUT_BUFFER_OFFSET_3[0], sizeof(VGT_STRMOUT_BUFFER_OFFSET_3)/sizeof(VGT_STRMOUT_BUFFER_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET", REG_MMIO, 0xa2ca, &VGT_STRMOUT_DRAW_OPAQUE_OFFSET[0], sizeof(VGT_STRMOUT_DRAW_OPAQUE_OFFSET)/sizeof(VGT_STRMOUT_DRAW_OPAQUE_OFFSET[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE", REG_MMIO, 0xa2cb, &VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0], sizeof(VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE)/sizeof(VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", REG_MMIO, 0xa2cc, &VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0], sizeof(VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE)/sizeof(VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0]), 0, 0 },
+	{ "mmVGT_GS_MAX_VERT_OUT", REG_MMIO, 0xa2ce, &VGT_GS_MAX_VERT_OUT[0], sizeof(VGT_GS_MAX_VERT_OUT)/sizeof(VGT_GS_MAX_VERT_OUT[0]), 0, 0 },
+	{ "mmVGT_SHADER_STAGES_EN", REG_MMIO, 0xa2d5, &VGT_SHADER_STAGES_EN[0], sizeof(VGT_SHADER_STAGES_EN)/sizeof(VGT_SHADER_STAGES_EN[0]), 0, 0 },
+	{ "mmVGT_LS_HS_CONFIG", REG_MMIO, 0xa2d6, &VGT_LS_HS_CONFIG[0], sizeof(VGT_LS_HS_CONFIG)/sizeof(VGT_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE", REG_MMIO, 0xa2d7, &VGT_GS_VERT_ITEMSIZE[0], sizeof(VGT_GS_VERT_ITEMSIZE)/sizeof(VGT_GS_VERT_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_1", REG_MMIO, 0xa2d8, &VGT_GS_VERT_ITEMSIZE_1[0], sizeof(VGT_GS_VERT_ITEMSIZE_1)/sizeof(VGT_GS_VERT_ITEMSIZE_1[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_2", REG_MMIO, 0xa2d9, &VGT_GS_VERT_ITEMSIZE_2[0], sizeof(VGT_GS_VERT_ITEMSIZE_2)/sizeof(VGT_GS_VERT_ITEMSIZE_2[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_3", REG_MMIO, 0xa2da, &VGT_GS_VERT_ITEMSIZE_3[0], sizeof(VGT_GS_VERT_ITEMSIZE_3)/sizeof(VGT_GS_VERT_ITEMSIZE_3[0]), 0, 0 },
+	{ "mmVGT_TF_PARAM", REG_MMIO, 0xa2db, &VGT_TF_PARAM[0], sizeof(VGT_TF_PARAM)/sizeof(VGT_TF_PARAM[0]), 0, 0 },
+	{ "mmDB_ALPHA_TO_MASK", REG_MMIO, 0xa2dc, &DB_ALPHA_TO_MASK[0], sizeof(DB_ALPHA_TO_MASK)/sizeof(DB_ALPHA_TO_MASK[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_DB_FMT_CNTL", REG_MMIO, 0xa2de, &PA_SU_POLY_OFFSET_DB_FMT_CNTL[0], sizeof(PA_SU_POLY_OFFSET_DB_FMT_CNTL)/sizeof(PA_SU_POLY_OFFSET_DB_FMT_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_CLAMP", REG_MMIO, 0xa2df, &PA_SU_POLY_OFFSET_CLAMP[0], sizeof(PA_SU_POLY_OFFSET_CLAMP)/sizeof(PA_SU_POLY_OFFSET_CLAMP[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_SCALE", REG_MMIO, 0xa2e0, &PA_SU_POLY_OFFSET_FRONT_SCALE[0], sizeof(PA_SU_POLY_OFFSET_FRONT_SCALE)/sizeof(PA_SU_POLY_OFFSET_FRONT_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_OFFSET", REG_MMIO, 0xa2e1, &PA_SU_POLY_OFFSET_FRONT_OFFSET[0], sizeof(PA_SU_POLY_OFFSET_FRONT_OFFSET)/sizeof(PA_SU_POLY_OFFSET_FRONT_OFFSET[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_SCALE", REG_MMIO, 0xa2e2, &PA_SU_POLY_OFFSET_BACK_SCALE[0], sizeof(PA_SU_POLY_OFFSET_BACK_SCALE)/sizeof(PA_SU_POLY_OFFSET_BACK_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_OFFSET", REG_MMIO, 0xa2e3, &PA_SU_POLY_OFFSET_BACK_OFFSET[0], sizeof(PA_SU_POLY_OFFSET_BACK_OFFSET)/sizeof(PA_SU_POLY_OFFSET_BACK_OFFSET[0]), 0, 0 },
+	{ "mmVGT_GS_INSTANCE_CNT", REG_MMIO, 0xa2e4, &VGT_GS_INSTANCE_CNT[0], sizeof(VGT_GS_INSTANCE_CNT)/sizeof(VGT_GS_INSTANCE_CNT[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_CONFIG", REG_MMIO, 0xa2e5, &VGT_STRMOUT_CONFIG[0], sizeof(VGT_STRMOUT_CONFIG)/sizeof(VGT_STRMOUT_CONFIG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_CONFIG", REG_MMIO, 0xa2e6, &VGT_STRMOUT_BUFFER_CONFIG[0], sizeof(VGT_STRMOUT_BUFFER_CONFIG)/sizeof(VGT_STRMOUT_BUFFER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_0", REG_MMIO, 0xa2f5, &PA_SC_CENTROID_PRIORITY_0[0], sizeof(PA_SC_CENTROID_PRIORITY_0)/sizeof(PA_SC_CENTROID_PRIORITY_0[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_1", REG_MMIO, 0xa2f6, &PA_SC_CENTROID_PRIORITY_1[0], sizeof(PA_SC_CENTROID_PRIORITY_1)/sizeof(PA_SC_CENTROID_PRIORITY_1[0]), 0, 0 },
+	{ "mmPA_SC_LINE_CNTL", REG_MMIO, 0xa2f7, &PA_SC_LINE_CNTL[0], sizeof(PA_SC_LINE_CNTL)/sizeof(PA_SC_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_AA_CONFIG", REG_MMIO, 0xa2f8, &PA_SC_AA_CONFIG[0], sizeof(PA_SC_AA_CONFIG)/sizeof(PA_SC_AA_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_VTX_CNTL", REG_MMIO, 0xa2f9, &PA_SU_VTX_CNTL[0], sizeof(PA_SU_VTX_CNTL)/sizeof(PA_SU_VTX_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_CLIP_ADJ", REG_MMIO, 0xa2fa, &PA_CL_GB_VERT_CLIP_ADJ[0], sizeof(PA_CL_GB_VERT_CLIP_ADJ)/sizeof(PA_CL_GB_VERT_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_DISC_ADJ", REG_MMIO, 0xa2fb, &PA_CL_GB_VERT_DISC_ADJ[0], sizeof(PA_CL_GB_VERT_DISC_ADJ)/sizeof(PA_CL_GB_VERT_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_CLIP_ADJ", REG_MMIO, 0xa2fc, &PA_CL_GB_HORZ_CLIP_ADJ[0], sizeof(PA_CL_GB_HORZ_CLIP_ADJ)/sizeof(PA_CL_GB_HORZ_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_DISC_ADJ", REG_MMIO, 0xa2fd, &PA_CL_GB_HORZ_DISC_ADJ[0], sizeof(PA_CL_GB_HORZ_DISC_ADJ)/sizeof(PA_CL_GB_HORZ_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", REG_MMIO, 0xa2fe, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", REG_MMIO, 0xa2ff, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", REG_MMIO, 0xa300, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", REG_MMIO, 0xa301, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", REG_MMIO, 0xa302, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", REG_MMIO, 0xa303, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", REG_MMIO, 0xa304, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", REG_MMIO, 0xa305, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", REG_MMIO, 0xa306, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", REG_MMIO, 0xa307, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", REG_MMIO, 0xa308, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", REG_MMIO, 0xa309, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", REG_MMIO, 0xa30a, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", REG_MMIO, 0xa30b, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", REG_MMIO, 0xa30c, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", REG_MMIO, 0xa30d, &PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0], sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3)/sizeof(PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y0_X1Y0", REG_MMIO, 0xa30e, &PA_SC_AA_MASK_X0Y0_X1Y0[0], sizeof(PA_SC_AA_MASK_X0Y0_X1Y0)/sizeof(PA_SC_AA_MASK_X0Y0_X1Y0[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y1_X1Y1", REG_MMIO, 0xa30f, &PA_SC_AA_MASK_X0Y1_X1Y1[0], sizeof(PA_SC_AA_MASK_X0Y1_X1Y1)/sizeof(PA_SC_AA_MASK_X0Y1_X1Y1[0]), 0, 0 },
+	{ "mmVGT_VERTEX_REUSE_BLOCK_CNTL", REG_MMIO, 0xa316, &VGT_VERTEX_REUSE_BLOCK_CNTL[0], sizeof(VGT_VERTEX_REUSE_BLOCK_CNTL)/sizeof(VGT_VERTEX_REUSE_BLOCK_CNTL[0]), 0, 0 },
+	{ "mmVGT_OUT_DEALLOC_CNTL", REG_MMIO, 0xa317, &VGT_OUT_DEALLOC_CNTL[0], sizeof(VGT_OUT_DEALLOC_CNTL)/sizeof(VGT_OUT_DEALLOC_CNTL[0]), 0, 0 },
+	{ "mmCB_COLOR0_BASE", REG_MMIO, 0xa318, &CB_COLOR0_BASE[0], sizeof(CB_COLOR0_BASE)/sizeof(CB_COLOR0_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR0_PITCH", REG_MMIO, 0xa319, &CB_COLOR0_PITCH[0], sizeof(CB_COLOR0_PITCH)/sizeof(CB_COLOR0_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR0_SLICE", REG_MMIO, 0xa31a, &CB_COLOR0_SLICE[0], sizeof(CB_COLOR0_SLICE)/sizeof(CB_COLOR0_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_VIEW", REG_MMIO, 0xa31b, &CB_COLOR0_VIEW[0], sizeof(CB_COLOR0_VIEW)/sizeof(CB_COLOR0_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR0_INFO", REG_MMIO, 0xa31c, &CB_COLOR0_INFO[0], sizeof(CB_COLOR0_INFO)/sizeof(CB_COLOR0_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR0_ATTRIB", REG_MMIO, 0xa31d, &CB_COLOR0_ATTRIB[0], sizeof(CB_COLOR0_ATTRIB)/sizeof(CB_COLOR0_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK", REG_MMIO, 0xa31f, &CB_COLOR0_CMASK[0], sizeof(CB_COLOR0_CMASK)/sizeof(CB_COLOR0_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK_SLICE", REG_MMIO, 0xa320, &CB_COLOR0_CMASK_SLICE[0], sizeof(CB_COLOR0_CMASK_SLICE)/sizeof(CB_COLOR0_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK", REG_MMIO, 0xa321, &CB_COLOR0_FMASK[0], sizeof(CB_COLOR0_FMASK)/sizeof(CB_COLOR0_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK_SLICE", REG_MMIO, 0xa322, &CB_COLOR0_FMASK_SLICE[0], sizeof(CB_COLOR0_FMASK_SLICE)/sizeof(CB_COLOR0_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD0", REG_MMIO, 0xa323, &CB_COLOR0_CLEAR_WORD0[0], sizeof(CB_COLOR0_CLEAR_WORD0)/sizeof(CB_COLOR0_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD1", REG_MMIO, 0xa324, &CB_COLOR0_CLEAR_WORD1[0], sizeof(CB_COLOR0_CLEAR_WORD1)/sizeof(CB_COLOR0_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR1_BASE", REG_MMIO, 0xa327, &CB_COLOR1_BASE[0], sizeof(CB_COLOR1_BASE)/sizeof(CB_COLOR1_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR1_PITCH", REG_MMIO, 0xa328, &CB_COLOR1_PITCH[0], sizeof(CB_COLOR1_PITCH)/sizeof(CB_COLOR1_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR1_SLICE", REG_MMIO, 0xa329, &CB_COLOR1_SLICE[0], sizeof(CB_COLOR1_SLICE)/sizeof(CB_COLOR1_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_VIEW", REG_MMIO, 0xa32a, &CB_COLOR1_VIEW[0], sizeof(CB_COLOR1_VIEW)/sizeof(CB_COLOR1_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR1_INFO", REG_MMIO, 0xa32b, &CB_COLOR1_INFO[0], sizeof(CB_COLOR1_INFO)/sizeof(CB_COLOR1_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR1_ATTRIB", REG_MMIO, 0xa32c, &CB_COLOR1_ATTRIB[0], sizeof(CB_COLOR1_ATTRIB)/sizeof(CB_COLOR1_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK", REG_MMIO, 0xa32e, &CB_COLOR1_CMASK[0], sizeof(CB_COLOR1_CMASK)/sizeof(CB_COLOR1_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK_SLICE", REG_MMIO, 0xa32f, &CB_COLOR1_CMASK_SLICE[0], sizeof(CB_COLOR1_CMASK_SLICE)/sizeof(CB_COLOR1_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK", REG_MMIO, 0xa330, &CB_COLOR1_FMASK[0], sizeof(CB_COLOR1_FMASK)/sizeof(CB_COLOR1_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK_SLICE", REG_MMIO, 0xa331, &CB_COLOR1_FMASK_SLICE[0], sizeof(CB_COLOR1_FMASK_SLICE)/sizeof(CB_COLOR1_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD0", REG_MMIO, 0xa332, &CB_COLOR1_CLEAR_WORD0[0], sizeof(CB_COLOR1_CLEAR_WORD0)/sizeof(CB_COLOR1_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD1", REG_MMIO, 0xa333, &CB_COLOR1_CLEAR_WORD1[0], sizeof(CB_COLOR1_CLEAR_WORD1)/sizeof(CB_COLOR1_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR2_BASE", REG_MMIO, 0xa336, &CB_COLOR2_BASE[0], sizeof(CB_COLOR2_BASE)/sizeof(CB_COLOR2_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR2_PITCH", REG_MMIO, 0xa337, &CB_COLOR2_PITCH[0], sizeof(CB_COLOR2_PITCH)/sizeof(CB_COLOR2_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR2_SLICE", REG_MMIO, 0xa338, &CB_COLOR2_SLICE[0], sizeof(CB_COLOR2_SLICE)/sizeof(CB_COLOR2_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_VIEW", REG_MMIO, 0xa339, &CB_COLOR2_VIEW[0], sizeof(CB_COLOR2_VIEW)/sizeof(CB_COLOR2_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR2_INFO", REG_MMIO, 0xa33a, &CB_COLOR2_INFO[0], sizeof(CB_COLOR2_INFO)/sizeof(CB_COLOR2_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR2_ATTRIB", REG_MMIO, 0xa33b, &CB_COLOR2_ATTRIB[0], sizeof(CB_COLOR2_ATTRIB)/sizeof(CB_COLOR2_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK", REG_MMIO, 0xa33d, &CB_COLOR2_CMASK[0], sizeof(CB_COLOR2_CMASK)/sizeof(CB_COLOR2_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK_SLICE", REG_MMIO, 0xa33e, &CB_COLOR2_CMASK_SLICE[0], sizeof(CB_COLOR2_CMASK_SLICE)/sizeof(CB_COLOR2_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK", REG_MMIO, 0xa33f, &CB_COLOR2_FMASK[0], sizeof(CB_COLOR2_FMASK)/sizeof(CB_COLOR2_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK_SLICE", REG_MMIO, 0xa340, &CB_COLOR2_FMASK_SLICE[0], sizeof(CB_COLOR2_FMASK_SLICE)/sizeof(CB_COLOR2_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD0", REG_MMIO, 0xa341, &CB_COLOR2_CLEAR_WORD0[0], sizeof(CB_COLOR2_CLEAR_WORD0)/sizeof(CB_COLOR2_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD1", REG_MMIO, 0xa342, &CB_COLOR2_CLEAR_WORD1[0], sizeof(CB_COLOR2_CLEAR_WORD1)/sizeof(CB_COLOR2_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR3_BASE", REG_MMIO, 0xa345, &CB_COLOR3_BASE[0], sizeof(CB_COLOR3_BASE)/sizeof(CB_COLOR3_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR3_PITCH", REG_MMIO, 0xa346, &CB_COLOR3_PITCH[0], sizeof(CB_COLOR3_PITCH)/sizeof(CB_COLOR3_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR3_SLICE", REG_MMIO, 0xa347, &CB_COLOR3_SLICE[0], sizeof(CB_COLOR3_SLICE)/sizeof(CB_COLOR3_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_VIEW", REG_MMIO, 0xa348, &CB_COLOR3_VIEW[0], sizeof(CB_COLOR3_VIEW)/sizeof(CB_COLOR3_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR3_INFO", REG_MMIO, 0xa349, &CB_COLOR3_INFO[0], sizeof(CB_COLOR3_INFO)/sizeof(CB_COLOR3_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR3_ATTRIB", REG_MMIO, 0xa34a, &CB_COLOR3_ATTRIB[0], sizeof(CB_COLOR3_ATTRIB)/sizeof(CB_COLOR3_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK", REG_MMIO, 0xa34c, &CB_COLOR3_CMASK[0], sizeof(CB_COLOR3_CMASK)/sizeof(CB_COLOR3_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK_SLICE", REG_MMIO, 0xa34d, &CB_COLOR3_CMASK_SLICE[0], sizeof(CB_COLOR3_CMASK_SLICE)/sizeof(CB_COLOR3_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK", REG_MMIO, 0xa34e, &CB_COLOR3_FMASK[0], sizeof(CB_COLOR3_FMASK)/sizeof(CB_COLOR3_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK_SLICE", REG_MMIO, 0xa34f, &CB_COLOR3_FMASK_SLICE[0], sizeof(CB_COLOR3_FMASK_SLICE)/sizeof(CB_COLOR3_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD0", REG_MMIO, 0xa350, &CB_COLOR3_CLEAR_WORD0[0], sizeof(CB_COLOR3_CLEAR_WORD0)/sizeof(CB_COLOR3_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD1", REG_MMIO, 0xa351, &CB_COLOR3_CLEAR_WORD1[0], sizeof(CB_COLOR3_CLEAR_WORD1)/sizeof(CB_COLOR3_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR4_BASE", REG_MMIO, 0xa354, &CB_COLOR4_BASE[0], sizeof(CB_COLOR4_BASE)/sizeof(CB_COLOR4_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR4_PITCH", REG_MMIO, 0xa355, &CB_COLOR4_PITCH[0], sizeof(CB_COLOR4_PITCH)/sizeof(CB_COLOR4_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR4_SLICE", REG_MMIO, 0xa356, &CB_COLOR4_SLICE[0], sizeof(CB_COLOR4_SLICE)/sizeof(CB_COLOR4_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_VIEW", REG_MMIO, 0xa357, &CB_COLOR4_VIEW[0], sizeof(CB_COLOR4_VIEW)/sizeof(CB_COLOR4_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR4_INFO", REG_MMIO, 0xa358, &CB_COLOR4_INFO[0], sizeof(CB_COLOR4_INFO)/sizeof(CB_COLOR4_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR4_ATTRIB", REG_MMIO, 0xa359, &CB_COLOR4_ATTRIB[0], sizeof(CB_COLOR4_ATTRIB)/sizeof(CB_COLOR4_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK", REG_MMIO, 0xa35b, &CB_COLOR4_CMASK[0], sizeof(CB_COLOR4_CMASK)/sizeof(CB_COLOR4_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK_SLICE", REG_MMIO, 0xa35c, &CB_COLOR4_CMASK_SLICE[0], sizeof(CB_COLOR4_CMASK_SLICE)/sizeof(CB_COLOR4_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK", REG_MMIO, 0xa35d, &CB_COLOR4_FMASK[0], sizeof(CB_COLOR4_FMASK)/sizeof(CB_COLOR4_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK_SLICE", REG_MMIO, 0xa35e, &CB_COLOR4_FMASK_SLICE[0], sizeof(CB_COLOR4_FMASK_SLICE)/sizeof(CB_COLOR4_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD0", REG_MMIO, 0xa35f, &CB_COLOR4_CLEAR_WORD0[0], sizeof(CB_COLOR4_CLEAR_WORD0)/sizeof(CB_COLOR4_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD1", REG_MMIO, 0xa360, &CB_COLOR4_CLEAR_WORD1[0], sizeof(CB_COLOR4_CLEAR_WORD1)/sizeof(CB_COLOR4_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR5_BASE", REG_MMIO, 0xa363, &CB_COLOR5_BASE[0], sizeof(CB_COLOR5_BASE)/sizeof(CB_COLOR5_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR5_PITCH", REG_MMIO, 0xa364, &CB_COLOR5_PITCH[0], sizeof(CB_COLOR5_PITCH)/sizeof(CB_COLOR5_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR5_SLICE", REG_MMIO, 0xa365, &CB_COLOR5_SLICE[0], sizeof(CB_COLOR5_SLICE)/sizeof(CB_COLOR5_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_VIEW", REG_MMIO, 0xa366, &CB_COLOR5_VIEW[0], sizeof(CB_COLOR5_VIEW)/sizeof(CB_COLOR5_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR5_INFO", REG_MMIO, 0xa367, &CB_COLOR5_INFO[0], sizeof(CB_COLOR5_INFO)/sizeof(CB_COLOR5_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR5_ATTRIB", REG_MMIO, 0xa368, &CB_COLOR5_ATTRIB[0], sizeof(CB_COLOR5_ATTRIB)/sizeof(CB_COLOR5_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK", REG_MMIO, 0xa36a, &CB_COLOR5_CMASK[0], sizeof(CB_COLOR5_CMASK)/sizeof(CB_COLOR5_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK_SLICE", REG_MMIO, 0xa36b, &CB_COLOR5_CMASK_SLICE[0], sizeof(CB_COLOR5_CMASK_SLICE)/sizeof(CB_COLOR5_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK", REG_MMIO, 0xa36c, &CB_COLOR5_FMASK[0], sizeof(CB_COLOR5_FMASK)/sizeof(CB_COLOR5_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK_SLICE", REG_MMIO, 0xa36d, &CB_COLOR5_FMASK_SLICE[0], sizeof(CB_COLOR5_FMASK_SLICE)/sizeof(CB_COLOR5_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD0", REG_MMIO, 0xa36e, &CB_COLOR5_CLEAR_WORD0[0], sizeof(CB_COLOR5_CLEAR_WORD0)/sizeof(CB_COLOR5_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD1", REG_MMIO, 0xa36f, &CB_COLOR5_CLEAR_WORD1[0], sizeof(CB_COLOR5_CLEAR_WORD1)/sizeof(CB_COLOR5_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR6_BASE", REG_MMIO, 0xa372, &CB_COLOR6_BASE[0], sizeof(CB_COLOR6_BASE)/sizeof(CB_COLOR6_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR6_PITCH", REG_MMIO, 0xa373, &CB_COLOR6_PITCH[0], sizeof(CB_COLOR6_PITCH)/sizeof(CB_COLOR6_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR6_SLICE", REG_MMIO, 0xa374, &CB_COLOR6_SLICE[0], sizeof(CB_COLOR6_SLICE)/sizeof(CB_COLOR6_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_VIEW", REG_MMIO, 0xa375, &CB_COLOR6_VIEW[0], sizeof(CB_COLOR6_VIEW)/sizeof(CB_COLOR6_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR6_INFO", REG_MMIO, 0xa376, &CB_COLOR6_INFO[0], sizeof(CB_COLOR6_INFO)/sizeof(CB_COLOR6_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR6_ATTRIB", REG_MMIO, 0xa377, &CB_COLOR6_ATTRIB[0], sizeof(CB_COLOR6_ATTRIB)/sizeof(CB_COLOR6_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK", REG_MMIO, 0xa379, &CB_COLOR6_CMASK[0], sizeof(CB_COLOR6_CMASK)/sizeof(CB_COLOR6_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK_SLICE", REG_MMIO, 0xa37a, &CB_COLOR6_CMASK_SLICE[0], sizeof(CB_COLOR6_CMASK_SLICE)/sizeof(CB_COLOR6_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK", REG_MMIO, 0xa37b, &CB_COLOR6_FMASK[0], sizeof(CB_COLOR6_FMASK)/sizeof(CB_COLOR6_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK_SLICE", REG_MMIO, 0xa37c, &CB_COLOR6_FMASK_SLICE[0], sizeof(CB_COLOR6_FMASK_SLICE)/sizeof(CB_COLOR6_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD0", REG_MMIO, 0xa37d, &CB_COLOR6_CLEAR_WORD0[0], sizeof(CB_COLOR6_CLEAR_WORD0)/sizeof(CB_COLOR6_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD1", REG_MMIO, 0xa37e, &CB_COLOR6_CLEAR_WORD1[0], sizeof(CB_COLOR6_CLEAR_WORD1)/sizeof(CB_COLOR6_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR7_BASE", REG_MMIO, 0xa381, &CB_COLOR7_BASE[0], sizeof(CB_COLOR7_BASE)/sizeof(CB_COLOR7_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR7_PITCH", REG_MMIO, 0xa382, &CB_COLOR7_PITCH[0], sizeof(CB_COLOR7_PITCH)/sizeof(CB_COLOR7_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR7_SLICE", REG_MMIO, 0xa383, &CB_COLOR7_SLICE[0], sizeof(CB_COLOR7_SLICE)/sizeof(CB_COLOR7_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_VIEW", REG_MMIO, 0xa384, &CB_COLOR7_VIEW[0], sizeof(CB_COLOR7_VIEW)/sizeof(CB_COLOR7_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR7_INFO", REG_MMIO, 0xa385, &CB_COLOR7_INFO[0], sizeof(CB_COLOR7_INFO)/sizeof(CB_COLOR7_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR7_ATTRIB", REG_MMIO, 0xa386, &CB_COLOR7_ATTRIB[0], sizeof(CB_COLOR7_ATTRIB)/sizeof(CB_COLOR7_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK", REG_MMIO, 0xa388, &CB_COLOR7_CMASK[0], sizeof(CB_COLOR7_CMASK)/sizeof(CB_COLOR7_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK_SLICE", REG_MMIO, 0xa389, &CB_COLOR7_CMASK_SLICE[0], sizeof(CB_COLOR7_CMASK_SLICE)/sizeof(CB_COLOR7_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK", REG_MMIO, 0xa38a, &CB_COLOR7_FMASK[0], sizeof(CB_COLOR7_FMASK)/sizeof(CB_COLOR7_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK_SLICE", REG_MMIO, 0xa38b, &CB_COLOR7_FMASK_SLICE[0], sizeof(CB_COLOR7_FMASK_SLICE)/sizeof(CB_COLOR7_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD0", REG_MMIO, 0xa38c, &CB_COLOR7_CLEAR_WORD0[0], sizeof(CB_COLOR7_CLEAR_WORD0)/sizeof(CB_COLOR7_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD1", REG_MMIO, 0xa38d, &CB_COLOR7_CLEAR_WORD1[0], sizeof(CB_COLOR7_CLEAR_WORD1)/sizeof(CB_COLOR7_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_LO", REG_MMIO, 0xc000, &CP_EOP_DONE_ADDR_LO[0], sizeof(CP_EOP_DONE_ADDR_LO)/sizeof(CP_EOP_DONE_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_HI", REG_MMIO, 0xc001, &CP_EOP_DONE_ADDR_HI[0], sizeof(CP_EOP_DONE_ADDR_HI)/sizeof(CP_EOP_DONE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_LO", REG_MMIO, 0xc002, &CP_EOP_DONE_DATA_LO[0], sizeof(CP_EOP_DONE_DATA_LO)/sizeof(CP_EOP_DONE_DATA_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_HI", REG_MMIO, 0xc003, &CP_EOP_DONE_DATA_HI[0], sizeof(CP_EOP_DONE_DATA_HI)/sizeof(CP_EOP_DONE_DATA_HI[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_LO", REG_MMIO, 0xc004, &CP_EOP_LAST_FENCE_LO[0], sizeof(CP_EOP_LAST_FENCE_LO)/sizeof(CP_EOP_LAST_FENCE_LO[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_HI", REG_MMIO, 0xc005, &CP_EOP_LAST_FENCE_HI[0], sizeof(CP_EOP_LAST_FENCE_HI)/sizeof(CP_EOP_LAST_FENCE_HI[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_LO", REG_MMIO, 0xc006, &CP_STREAM_OUT_ADDR_LO[0], sizeof(CP_STREAM_OUT_ADDR_LO)/sizeof(CP_STREAM_OUT_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_HI", REG_MMIO, 0xc007, &CP_STREAM_OUT_ADDR_HI[0], sizeof(CP_STREAM_OUT_ADDR_HI)/sizeof(CP_STREAM_OUT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_LO", REG_MMIO, 0xc008, &CP_NUM_PRIM_WRITTEN_COUNT0_LO[0], sizeof(CP_NUM_PRIM_WRITTEN_COUNT0_LO)/sizeof(CP_NUM_PRIM_WRITTEN_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_HI", REG_MMIO, 0xc009, &CP_NUM_PRIM_WRITTEN_COUNT0_HI[0], sizeof(CP_NUM_PRIM_WRITTEN_COUNT0_HI)/sizeof(CP_NUM_PRIM_WRITTEN_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_LO", REG_MMIO, 0xc00a, &CP_NUM_PRIM_NEEDED_COUNT0_LO[0], sizeof(CP_NUM_PRIM_NEEDED_COUNT0_LO)/sizeof(CP_NUM_PRIM_NEEDED_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_HI", REG_MMIO, 0xc00b, &CP_NUM_PRIM_NEEDED_COUNT0_HI[0], sizeof(CP_NUM_PRIM_NEEDED_COUNT0_HI)/sizeof(CP_NUM_PRIM_NEEDED_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_LO", REG_MMIO, 0xc00c, &CP_NUM_PRIM_WRITTEN_COUNT1_LO[0], sizeof(CP_NUM_PRIM_WRITTEN_COUNT1_LO)/sizeof(CP_NUM_PRIM_WRITTEN_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_HI", REG_MMIO, 0xc00d, &CP_NUM_PRIM_WRITTEN_COUNT1_HI[0], sizeof(CP_NUM_PRIM_WRITTEN_COUNT1_HI)/sizeof(CP_NUM_PRIM_WRITTEN_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_LO", REG_MMIO, 0xc00e, &CP_NUM_PRIM_NEEDED_COUNT1_LO[0], sizeof(CP_NUM_PRIM_NEEDED_COUNT1_LO)/sizeof(CP_NUM_PRIM_NEEDED_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_HI", REG_MMIO, 0xc00f, &CP_NUM_PRIM_NEEDED_COUNT1_HI[0], sizeof(CP_NUM_PRIM_NEEDED_COUNT1_HI)/sizeof(CP_NUM_PRIM_NEEDED_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_LO", REG_MMIO, 0xc010, &CP_NUM_PRIM_WRITTEN_COUNT2_LO[0], sizeof(CP_NUM_PRIM_WRITTEN_COUNT2_LO)/sizeof(CP_NUM_PRIM_WRITTEN_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_HI", REG_MMIO, 0xc011, &CP_NUM_PRIM_WRITTEN_COUNT2_HI[0], sizeof(CP_NUM_PRIM_WRITTEN_COUNT2_HI)/sizeof(CP_NUM_PRIM_WRITTEN_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_LO", REG_MMIO, 0xc012, &CP_NUM_PRIM_NEEDED_COUNT2_LO[0], sizeof(CP_NUM_PRIM_NEEDED_COUNT2_LO)/sizeof(CP_NUM_PRIM_NEEDED_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_HI", REG_MMIO, 0xc013, &CP_NUM_PRIM_NEEDED_COUNT2_HI[0], sizeof(CP_NUM_PRIM_NEEDED_COUNT2_HI)/sizeof(CP_NUM_PRIM_NEEDED_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_LO", REG_MMIO, 0xc014, &CP_NUM_PRIM_WRITTEN_COUNT3_LO[0], sizeof(CP_NUM_PRIM_WRITTEN_COUNT3_LO)/sizeof(CP_NUM_PRIM_WRITTEN_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_HI", REG_MMIO, 0xc015, &CP_NUM_PRIM_WRITTEN_COUNT3_HI[0], sizeof(CP_NUM_PRIM_WRITTEN_COUNT3_HI)/sizeof(CP_NUM_PRIM_WRITTEN_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_LO", REG_MMIO, 0xc016, &CP_NUM_PRIM_NEEDED_COUNT3_LO[0], sizeof(CP_NUM_PRIM_NEEDED_COUNT3_LO)/sizeof(CP_NUM_PRIM_NEEDED_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_HI", REG_MMIO, 0xc017, &CP_NUM_PRIM_NEEDED_COUNT3_HI[0], sizeof(CP_NUM_PRIM_NEEDED_COUNT3_HI)/sizeof(CP_NUM_PRIM_NEEDED_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_LO", REG_MMIO, 0xc018, &CP_PIPE_STATS_ADDR_LO[0], sizeof(CP_PIPE_STATS_ADDR_LO)/sizeof(CP_PIPE_STATS_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_HI", REG_MMIO, 0xc019, &CP_PIPE_STATS_ADDR_HI[0], sizeof(CP_PIPE_STATS_ADDR_HI)/sizeof(CP_PIPE_STATS_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_LO", REG_MMIO, 0xc01a, &CP_VGT_IAVERT_COUNT_LO[0], sizeof(CP_VGT_IAVERT_COUNT_LO)/sizeof(CP_VGT_IAVERT_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_HI", REG_MMIO, 0xc01b, &CP_VGT_IAVERT_COUNT_HI[0], sizeof(CP_VGT_IAVERT_COUNT_HI)/sizeof(CP_VGT_IAVERT_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_LO", REG_MMIO, 0xc01c, &CP_VGT_IAPRIM_COUNT_LO[0], sizeof(CP_VGT_IAPRIM_COUNT_LO)/sizeof(CP_VGT_IAPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_HI", REG_MMIO, 0xc01d, &CP_VGT_IAPRIM_COUNT_HI[0], sizeof(CP_VGT_IAPRIM_COUNT_HI)/sizeof(CP_VGT_IAPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_LO", REG_MMIO, 0xc01e, &CP_VGT_GSPRIM_COUNT_LO[0], sizeof(CP_VGT_GSPRIM_COUNT_LO)/sizeof(CP_VGT_GSPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_HI", REG_MMIO, 0xc01f, &CP_VGT_GSPRIM_COUNT_HI[0], sizeof(CP_VGT_GSPRIM_COUNT_HI)/sizeof(CP_VGT_GSPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_LO", REG_MMIO, 0xc020, &CP_VGT_VSINVOC_COUNT_LO[0], sizeof(CP_VGT_VSINVOC_COUNT_LO)/sizeof(CP_VGT_VSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_HI", REG_MMIO, 0xc021, &CP_VGT_VSINVOC_COUNT_HI[0], sizeof(CP_VGT_VSINVOC_COUNT_HI)/sizeof(CP_VGT_VSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_LO", REG_MMIO, 0xc022, &CP_VGT_GSINVOC_COUNT_LO[0], sizeof(CP_VGT_GSINVOC_COUNT_LO)/sizeof(CP_VGT_GSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_HI", REG_MMIO, 0xc023, &CP_VGT_GSINVOC_COUNT_HI[0], sizeof(CP_VGT_GSINVOC_COUNT_HI)/sizeof(CP_VGT_GSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_LO", REG_MMIO, 0xc024, &CP_VGT_HSINVOC_COUNT_LO[0], sizeof(CP_VGT_HSINVOC_COUNT_LO)/sizeof(CP_VGT_HSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_HI", REG_MMIO, 0xc025, &CP_VGT_HSINVOC_COUNT_HI[0], sizeof(CP_VGT_HSINVOC_COUNT_HI)/sizeof(CP_VGT_HSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_LO", REG_MMIO, 0xc026, &CP_VGT_DSINVOC_COUNT_LO[0], sizeof(CP_VGT_DSINVOC_COUNT_LO)/sizeof(CP_VGT_DSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_HI", REG_MMIO, 0xc027, &CP_VGT_DSINVOC_COUNT_HI[0], sizeof(CP_VGT_DSINVOC_COUNT_HI)/sizeof(CP_VGT_DSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_LO", REG_MMIO, 0xc028, &CP_PA_CINVOC_COUNT_LO[0], sizeof(CP_PA_CINVOC_COUNT_LO)/sizeof(CP_PA_CINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_HI", REG_MMIO, 0xc029, &CP_PA_CINVOC_COUNT_HI[0], sizeof(CP_PA_CINVOC_COUNT_HI)/sizeof(CP_PA_CINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_LO", REG_MMIO, 0xc02a, &CP_PA_CPRIM_COUNT_LO[0], sizeof(CP_PA_CPRIM_COUNT_LO)/sizeof(CP_PA_CPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_HI", REG_MMIO, 0xc02b, &CP_PA_CPRIM_COUNT_HI[0], sizeof(CP_PA_CPRIM_COUNT_HI)/sizeof(CP_PA_CPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_LO", REG_MMIO, 0xc02c, &CP_SC_PSINVOC_COUNT0_LO[0], sizeof(CP_SC_PSINVOC_COUNT0_LO)/sizeof(CP_SC_PSINVOC_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_HI", REG_MMIO, 0xc02d, &CP_SC_PSINVOC_COUNT0_HI[0], sizeof(CP_SC_PSINVOC_COUNT0_HI)/sizeof(CP_SC_PSINVOC_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_LO", REG_MMIO, 0xc02e, &CP_SC_PSINVOC_COUNT1_LO[0], sizeof(CP_SC_PSINVOC_COUNT1_LO)/sizeof(CP_SC_PSINVOC_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_HI", REG_MMIO, 0xc02f, &CP_SC_PSINVOC_COUNT1_HI[0], sizeof(CP_SC_PSINVOC_COUNT1_HI)/sizeof(CP_SC_PSINVOC_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_LO", REG_MMIO, 0xc030, &CP_VGT_CSINVOC_COUNT_LO[0], sizeof(CP_VGT_CSINVOC_COUNT_LO)/sizeof(CP_VGT_CSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_HI", REG_MMIO, 0xc031, &CP_VGT_CSINVOC_COUNT_HI[0], sizeof(CP_VGT_CSINVOC_COUNT_HI)/sizeof(CP_VGT_CSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_STRMOUT_CNTL", REG_MMIO, 0xc03f, &CP_STRMOUT_CNTL[0], sizeof(CP_STRMOUT_CNTL)/sizeof(CP_STRMOUT_CNTL[0]), 0, 0 },
+	{ "mmSCRATCH_REG0", REG_MMIO, 0xc040, &SCRATCH_REG0[0], sizeof(SCRATCH_REG0)/sizeof(SCRATCH_REG0[0]), 0, 0 },
+	{ "mmSCRATCH_REG1", REG_MMIO, 0xc041, &SCRATCH_REG1[0], sizeof(SCRATCH_REG1)/sizeof(SCRATCH_REG1[0]), 0, 0 },
+	{ "mmSCRATCH_REG2", REG_MMIO, 0xc042, &SCRATCH_REG2[0], sizeof(SCRATCH_REG2)/sizeof(SCRATCH_REG2[0]), 0, 0 },
+	{ "mmSCRATCH_REG3", REG_MMIO, 0xc043, &SCRATCH_REG3[0], sizeof(SCRATCH_REG3)/sizeof(SCRATCH_REG3[0]), 0, 0 },
+	{ "mmSCRATCH_REG4", REG_MMIO, 0xc044, &SCRATCH_REG4[0], sizeof(SCRATCH_REG4)/sizeof(SCRATCH_REG4[0]), 0, 0 },
+	{ "mmSCRATCH_REG5", REG_MMIO, 0xc045, &SCRATCH_REG5[0], sizeof(SCRATCH_REG5)/sizeof(SCRATCH_REG5[0]), 0, 0 },
+	{ "mmSCRATCH_REG6", REG_MMIO, 0xc046, &SCRATCH_REG6[0], sizeof(SCRATCH_REG6)/sizeof(SCRATCH_REG6[0]), 0, 0 },
+	{ "mmSCRATCH_REG7", REG_MMIO, 0xc047, &SCRATCH_REG7[0], sizeof(SCRATCH_REG7)/sizeof(SCRATCH_REG7[0]), 0, 0 },
+	{ "mmSCRATCH_UMSK", REG_MMIO, 0xc050, &SCRATCH_UMSK[0], sizeof(SCRATCH_UMSK)/sizeof(SCRATCH_UMSK[0]), 0, 0 },
+	{ "mmSCRATCH_ADDR", REG_MMIO, 0xc051, &SCRATCH_ADDR[0], sizeof(SCRATCH_ADDR)/sizeof(SCRATCH_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_ATOMIC_PREOP_LO", REG_MMIO, 0xc052, &CP_PFP_ATOMIC_PREOP_LO[0], sizeof(CP_PFP_ATOMIC_PREOP_LO)/sizeof(CP_PFP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_ATOMIC_PREOP_HI", REG_MMIO, 0xc053, &CP_PFP_ATOMIC_PREOP_HI[0], sizeof(CP_PFP_ATOMIC_PREOP_HI)/sizeof(CP_PFP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc054, &CP_PFP_GDS_ATOMIC0_PREOP_LO[0], sizeof(CP_PFP_GDS_ATOMIC0_PREOP_LO)/sizeof(CP_PFP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc055, &CP_PFP_GDS_ATOMIC0_PREOP_HI[0], sizeof(CP_PFP_GDS_ATOMIC0_PREOP_HI)/sizeof(CP_PFP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc056, &CP_PFP_GDS_ATOMIC1_PREOP_LO[0], sizeof(CP_PFP_GDS_ATOMIC1_PREOP_LO)/sizeof(CP_PFP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc057, &CP_PFP_GDS_ATOMIC1_PREOP_HI[0], sizeof(CP_PFP_GDS_ATOMIC1_PREOP_HI)/sizeof(CP_PFP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_LO", REG_MMIO, 0xc058, &CP_APPEND_ADDR_LO[0], sizeof(CP_APPEND_ADDR_LO)/sizeof(CP_APPEND_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_HI", REG_MMIO, 0xc059, &CP_APPEND_ADDR_HI[0], sizeof(CP_APPEND_ADDR_HI)/sizeof(CP_APPEND_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_DATA", REG_MMIO, 0xc05a, &CP_APPEND_DATA[0], sizeof(CP_APPEND_DATA)/sizeof(CP_APPEND_DATA[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_CS_FENCE", REG_MMIO, 0xc05b, &CP_APPEND_LAST_CS_FENCE[0], sizeof(CP_APPEND_LAST_CS_FENCE)/sizeof(CP_APPEND_LAST_CS_FENCE[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_PS_FENCE", REG_MMIO, 0xc05c, &CP_APPEND_LAST_PS_FENCE[0], sizeof(CP_APPEND_LAST_PS_FENCE)/sizeof(CP_APPEND_LAST_PS_FENCE[0]), 0, 0 },
+	{ "mmCP_ME_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &CP_ME_ATOMIC_PREOP_LO[0], sizeof(CP_ME_ATOMIC_PREOP_LO)/sizeof(CP_ME_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &CP_ATOMIC_PREOP_LO[0], sizeof(CP_ATOMIC_PREOP_LO)/sizeof(CP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &CP_ME_ATOMIC_PREOP_HI[0], sizeof(CP_ME_ATOMIC_PREOP_HI)/sizeof(CP_ME_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &CP_ATOMIC_PREOP_HI[0], sizeof(CP_ATOMIC_PREOP_HI)/sizeof(CP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &CP_ME_GDS_ATOMIC0_PREOP_LO[0], sizeof(CP_ME_GDS_ATOMIC0_PREOP_LO)/sizeof(CP_ME_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &CP_GDS_ATOMIC0_PREOP_LO[0], sizeof(CP_GDS_ATOMIC0_PREOP_LO)/sizeof(CP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &CP_ME_GDS_ATOMIC0_PREOP_HI[0], sizeof(CP_ME_GDS_ATOMIC0_PREOP_HI)/sizeof(CP_ME_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &CP_GDS_ATOMIC0_PREOP_HI[0], sizeof(CP_GDS_ATOMIC0_PREOP_HI)/sizeof(CP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &CP_ME_GDS_ATOMIC1_PREOP_LO[0], sizeof(CP_ME_GDS_ATOMIC1_PREOP_LO)/sizeof(CP_ME_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &CP_GDS_ATOMIC1_PREOP_LO[0], sizeof(CP_GDS_ATOMIC1_PREOP_LO)/sizeof(CP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &CP_ME_GDS_ATOMIC1_PREOP_HI[0], sizeof(CP_ME_GDS_ATOMIC1_PREOP_HI)/sizeof(CP_ME_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &CP_GDS_ATOMIC1_PREOP_HI[0], sizeof(CP_GDS_ATOMIC1_PREOP_HI)/sizeof(CP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_LO", REG_MMIO, 0xc069, &CP_ME_MC_WADDR_LO[0], sizeof(CP_ME_MC_WADDR_LO)/sizeof(CP_ME_MC_WADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_HI", REG_MMIO, 0xc06a, &CP_ME_MC_WADDR_HI[0], sizeof(CP_ME_MC_WADDR_HI)/sizeof(CP_ME_MC_WADDR_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_LO", REG_MMIO, 0xc06b, &CP_ME_MC_WDATA_LO[0], sizeof(CP_ME_MC_WDATA_LO)/sizeof(CP_ME_MC_WDATA_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_HI", REG_MMIO, 0xc06c, &CP_ME_MC_WDATA_HI[0], sizeof(CP_ME_MC_WDATA_HI)/sizeof(CP_ME_MC_WDATA_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_LO", REG_MMIO, 0xc06d, &CP_ME_MC_RADDR_LO[0], sizeof(CP_ME_MC_RADDR_LO)/sizeof(CP_ME_MC_RADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_HI", REG_MMIO, 0xc06e, &CP_ME_MC_RADDR_HI[0], sizeof(CP_ME_MC_RADDR_HI)/sizeof(CP_ME_MC_RADDR_HI[0]), 0, 0 },
+	{ "mmCP_SEM_WAIT_TIMER", REG_MMIO, 0xc06f, &CP_SEM_WAIT_TIMER[0], sizeof(CP_SEM_WAIT_TIMER)/sizeof(CP_SEM_WAIT_TIMER[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_LO", REG_MMIO, 0xc070, &CP_SIG_SEM_ADDR_LO[0], sizeof(CP_SIG_SEM_ADDR_LO)/sizeof(CP_SIG_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_HI", REG_MMIO, 0xc071, &CP_SIG_SEM_ADDR_HI[0], sizeof(CP_SIG_SEM_ADDR_HI)/sizeof(CP_SIG_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_SEM_INCOMPLETE_TIMER_CNTL", REG_MMIO, 0xc072, NULL, 0, 0, 0 },
+	{ "mmCP_WAIT_SEM_STATUS", REG_MMIO, 0xc073, NULL, 0, 0, 0 },
+	{ "mmCP_WAIT_REG_MEM_TIMEOUT", REG_MMIO, 0xc074, &CP_WAIT_REG_MEM_TIMEOUT[0], sizeof(CP_WAIT_REG_MEM_TIMEOUT)/sizeof(CP_WAIT_REG_MEM_TIMEOUT[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_LO", REG_MMIO, 0xc075, &CP_WAIT_SEM_ADDR_LO[0], sizeof(CP_WAIT_SEM_ADDR_LO)/sizeof(CP_WAIT_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_HI", REG_MMIO, 0xc076, &CP_WAIT_SEM_ADDR_HI[0], sizeof(CP_WAIT_SEM_ADDR_HI)/sizeof(CP_WAIT_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_CONTROL", REG_MMIO, 0xc077, &CP_DMA_PFP_CONTROL[0], sizeof(CP_DMA_PFP_CONTROL)/sizeof(CP_DMA_PFP_CONTROL[0]), 0, 0 },
+	{ "mmCP_DMA_ME_CONTROL", REG_MMIO, 0xc078, &CP_DMA_ME_CONTROL[0], sizeof(CP_DMA_ME_CONTROL)/sizeof(CP_DMA_ME_CONTROL[0]), 0, 0 },
+	{ "mmCP_COHER_BASE_HI", REG_MMIO, 0xc079, &CP_COHER_BASE_HI[0], sizeof(CP_COHER_BASE_HI)/sizeof(CP_COHER_BASE_HI[0]), 0, 0 },
+	{ "mmCP_COHER_START_DELAY", REG_MMIO, 0xc07b, &CP_COHER_START_DELAY[0], sizeof(CP_COHER_START_DELAY)/sizeof(CP_COHER_START_DELAY[0]), 0, 0 },
+	{ "mmCP_COHER_CNTL", REG_MMIO, 0xc07c, &CP_COHER_CNTL[0], sizeof(CP_COHER_CNTL)/sizeof(CP_COHER_CNTL[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE", REG_MMIO, 0xc07d, &CP_COHER_SIZE[0], sizeof(CP_COHER_SIZE)/sizeof(CP_COHER_SIZE[0]), 0, 0 },
+	{ "mmCP_COHER_BASE", REG_MMIO, 0xc07e, &CP_COHER_BASE[0], sizeof(CP_COHER_BASE)/sizeof(CP_COHER_BASE[0]), 0, 0 },
+	{ "mmCP_COHER_STATUS", REG_MMIO, 0xc07f, &CP_COHER_STATUS[0], sizeof(CP_COHER_STATUS)/sizeof(CP_COHER_STATUS[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR", REG_MMIO, 0xc080, &CP_DMA_ME_SRC_ADDR[0], sizeof(CP_DMA_ME_SRC_ADDR)/sizeof(CP_DMA_ME_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR_HI", REG_MMIO, 0xc081, &CP_DMA_ME_SRC_ADDR_HI[0], sizeof(CP_DMA_ME_SRC_ADDR_HI)/sizeof(CP_DMA_ME_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR", REG_MMIO, 0xc082, &CP_DMA_ME_DST_ADDR[0], sizeof(CP_DMA_ME_DST_ADDR)/sizeof(CP_DMA_ME_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR_HI", REG_MMIO, 0xc083, &CP_DMA_ME_DST_ADDR_HI[0], sizeof(CP_DMA_ME_DST_ADDR_HI)/sizeof(CP_DMA_ME_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_COMMAND", REG_MMIO, 0xc084, &CP_DMA_ME_COMMAND[0], sizeof(CP_DMA_ME_COMMAND)/sizeof(CP_DMA_ME_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR", REG_MMIO, 0xc085, &CP_DMA_PFP_SRC_ADDR[0], sizeof(CP_DMA_PFP_SRC_ADDR)/sizeof(CP_DMA_PFP_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR_HI", REG_MMIO, 0xc086, &CP_DMA_PFP_SRC_ADDR_HI[0], sizeof(CP_DMA_PFP_SRC_ADDR_HI)/sizeof(CP_DMA_PFP_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR", REG_MMIO, 0xc087, &CP_DMA_PFP_DST_ADDR[0], sizeof(CP_DMA_PFP_DST_ADDR)/sizeof(CP_DMA_PFP_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR_HI", REG_MMIO, 0xc088, &CP_DMA_PFP_DST_ADDR_HI[0], sizeof(CP_DMA_PFP_DST_ADDR_HI)/sizeof(CP_DMA_PFP_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_COMMAND", REG_MMIO, 0xc089, &CP_DMA_PFP_COMMAND[0], sizeof(CP_DMA_PFP_COMMAND)/sizeof(CP_DMA_PFP_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_CNTL", REG_MMIO, 0xc08a, &CP_DMA_CNTL[0], sizeof(CP_DMA_CNTL)/sizeof(CP_DMA_CNTL[0]), 0, 0 },
+	{ "mmCP_DMA_READ_TAGS", REG_MMIO, 0xc08b, &CP_DMA_READ_TAGS[0], sizeof(CP_DMA_READ_TAGS)/sizeof(CP_DMA_READ_TAGS[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE_HI", REG_MMIO, 0xc08c, &CP_COHER_SIZE_HI[0], sizeof(CP_COHER_SIZE_HI)/sizeof(CP_COHER_SIZE_HI[0]), 0, 0 },
+	{ "mmCP_PFP_IB_CONTROL", REG_MMIO, 0xc08d, &CP_PFP_IB_CONTROL[0], sizeof(CP_PFP_IB_CONTROL)/sizeof(CP_PFP_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_PFP_LOAD_CONTROL", REG_MMIO, 0xc08e, &CP_PFP_LOAD_CONTROL[0], sizeof(CP_PFP_LOAD_CONTROL)/sizeof(CP_PFP_LOAD_CONTROL[0]), 0, 0 },
+	{ "mmCP_SCRATCH_INDEX", REG_MMIO, 0xc08f, &CP_SCRATCH_INDEX[0], sizeof(CP_SCRATCH_INDEX)/sizeof(CP_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_SCRATCH_DATA", REG_MMIO, 0xc090, &CP_SCRATCH_DATA[0], sizeof(CP_SCRATCH_DATA)/sizeof(CP_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_RB_OFFSET", REG_MMIO, 0xc091, &CP_RB_OFFSET[0], sizeof(CP_RB_OFFSET)/sizeof(CP_RB_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_OFFSET", REG_MMIO, 0xc092, &CP_IB1_OFFSET[0], sizeof(CP_IB1_OFFSET)/sizeof(CP_IB1_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB2_OFFSET", REG_MMIO, 0xc093, &CP_IB2_OFFSET[0], sizeof(CP_IB2_OFFSET)/sizeof(CP_IB2_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_BEGIN", REG_MMIO, 0xc094, &CP_IB1_PREAMBLE_BEGIN[0], sizeof(CP_IB1_PREAMBLE_BEGIN)/sizeof(CP_IB1_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_END", REG_MMIO, 0xc095, &CP_IB1_PREAMBLE_END[0], sizeof(CP_IB1_PREAMBLE_END)/sizeof(CP_IB1_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_BEGIN", REG_MMIO, 0xc096, &CP_IB2_PREAMBLE_BEGIN[0], sizeof(CP_IB2_PREAMBLE_BEGIN)/sizeof(CP_IB2_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_END", REG_MMIO, 0xc097, &CP_IB2_PREAMBLE_END[0], sizeof(CP_IB2_PREAMBLE_END)/sizeof(CP_IB2_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_LO", REG_MMIO, 0xc0c3, &CP_CE_INIT_BASE_LO[0], sizeof(CP_CE_INIT_BASE_LO)/sizeof(CP_CE_INIT_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_HI", REG_MMIO, 0xc0c4, &CP_CE_INIT_BASE_HI[0], sizeof(CP_CE_INIT_BASE_HI)/sizeof(CP_CE_INIT_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BUFSZ", REG_MMIO, 0xc0c5, &CP_CE_INIT_BUFSZ[0], sizeof(CP_CE_INIT_BUFSZ)/sizeof(CP_CE_INIT_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_LO", REG_MMIO, 0xc0c6, &CP_CE_IB1_BASE_LO[0], sizeof(CP_CE_IB1_BASE_LO)/sizeof(CP_CE_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_HI", REG_MMIO, 0xc0c7, &CP_CE_IB1_BASE_HI[0], sizeof(CP_CE_IB1_BASE_HI)/sizeof(CP_CE_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BUFSZ", REG_MMIO, 0xc0c8, &CP_CE_IB1_BUFSZ[0], sizeof(CP_CE_IB1_BUFSZ)/sizeof(CP_CE_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_LO", REG_MMIO, 0xc0c9, &CP_CE_IB2_BASE_LO[0], sizeof(CP_CE_IB2_BASE_LO)/sizeof(CP_CE_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_HI", REG_MMIO, 0xc0ca, &CP_CE_IB2_BASE_HI[0], sizeof(CP_CE_IB2_BASE_HI)/sizeof(CP_CE_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BUFSZ", REG_MMIO, 0xc0cb, &CP_CE_IB2_BUFSZ[0], sizeof(CP_CE_IB2_BUFSZ)/sizeof(CP_CE_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_LO", REG_MMIO, 0xc0cc, &CP_IB1_BASE_LO[0], sizeof(CP_IB1_BASE_LO)/sizeof(CP_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_HI", REG_MMIO, 0xc0cd, &CP_IB1_BASE_HI[0], sizeof(CP_IB1_BASE_HI)/sizeof(CP_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB1_BUFSZ", REG_MMIO, 0xc0ce, &CP_IB1_BUFSZ[0], sizeof(CP_IB1_BUFSZ)/sizeof(CP_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_LO", REG_MMIO, 0xc0cf, &CP_IB2_BASE_LO[0], sizeof(CP_IB2_BASE_LO)/sizeof(CP_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_HI", REG_MMIO, 0xc0d0, &CP_IB2_BASE_HI[0], sizeof(CP_IB2_BASE_HI)/sizeof(CP_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB2_BUFSZ", REG_MMIO, 0xc0d1, &CP_IB2_BUFSZ[0], sizeof(CP_IB2_BUFSZ)/sizeof(CP_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_ST_BASE_LO", REG_MMIO, 0xc0d2, &CP_ST_BASE_LO[0], sizeof(CP_ST_BASE_LO)/sizeof(CP_ST_BASE_LO[0]), 0, 0 },
+	{ "mmCP_ST_BASE_HI", REG_MMIO, 0xc0d3, &CP_ST_BASE_HI[0], sizeof(CP_ST_BASE_HI)/sizeof(CP_ST_BASE_HI[0]), 0, 0 },
+	{ "mmCP_ST_BUFSZ", REG_MMIO, 0xc0d4, &CP_ST_BUFSZ[0], sizeof(CP_ST_BUFSZ)/sizeof(CP_ST_BUFSZ[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_EVENT_CNTL", REG_MMIO, 0xc0d5, &CP_EOP_DONE_EVENT_CNTL[0], sizeof(CP_EOP_DONE_EVENT_CNTL)/sizeof(CP_EOP_DONE_EVENT_CNTL[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_CNTL", REG_MMIO, 0xc0d6, &CP_EOP_DONE_DATA_CNTL[0], sizeof(CP_EOP_DONE_DATA_CNTL)/sizeof(CP_EOP_DONE_DATA_CNTL[0]), 0, 0 },
+	{ "mmGRBM_GFX_INDEX", REG_MMIO, 0xc200, &GRBM_GFX_INDEX[0], sizeof(GRBM_GFX_INDEX)/sizeof(GRBM_GFX_INDEX[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_SIZE", REG_MMIO, 0xc240, &VGT_ESGS_RING_SIZE[0], sizeof(VGT_ESGS_RING_SIZE)/sizeof(VGT_ESGS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_SIZE", REG_MMIO, 0xc241, &VGT_GSVS_RING_SIZE[0], sizeof(VGT_GSVS_RING_SIZE)/sizeof(VGT_GSVS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVE_TYPE", REG_MMIO, 0xc242, &VGT_PRIMITIVE_TYPE[0], sizeof(VGT_PRIMITIVE_TYPE)/sizeof(VGT_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_INDEX_TYPE", REG_MMIO, 0xc243, &VGT_INDEX_TYPE[0], sizeof(VGT_INDEX_TYPE)/sizeof(VGT_INDEX_TYPE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0", REG_MMIO, 0xc244, &VGT_STRMOUT_BUFFER_FILLED_SIZE_0[0], sizeof(VGT_STRMOUT_BUFFER_FILLED_SIZE_0)/sizeof(VGT_STRMOUT_BUFFER_FILLED_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1", REG_MMIO, 0xc245, &VGT_STRMOUT_BUFFER_FILLED_SIZE_1[0], sizeof(VGT_STRMOUT_BUFFER_FILLED_SIZE_1)/sizeof(VGT_STRMOUT_BUFFER_FILLED_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2", REG_MMIO, 0xc246, &VGT_STRMOUT_BUFFER_FILLED_SIZE_2[0], sizeof(VGT_STRMOUT_BUFFER_FILLED_SIZE_2)/sizeof(VGT_STRMOUT_BUFFER_FILLED_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3", REG_MMIO, 0xc247, &VGT_STRMOUT_BUFFER_FILLED_SIZE_3[0], sizeof(VGT_STRMOUT_BUFFER_FILLED_SIZE_3)/sizeof(VGT_STRMOUT_BUFFER_FILLED_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_NUM_INDICES", REG_MMIO, 0xc24c, &VGT_NUM_INDICES[0], sizeof(VGT_NUM_INDICES)/sizeof(VGT_NUM_INDICES[0]), 0, 0 },
+	{ "mmVGT_NUM_INSTANCES", REG_MMIO, 0xc24d, &VGT_NUM_INSTANCES[0], sizeof(VGT_NUM_INSTANCES)/sizeof(VGT_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_TF_RING_SIZE", REG_MMIO, 0xc24e, &VGT_TF_RING_SIZE[0], sizeof(VGT_TF_RING_SIZE)/sizeof(VGT_TF_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_HS_OFFCHIP_PARAM", REG_MMIO, 0xc24f, &VGT_HS_OFFCHIP_PARAM[0], sizeof(VGT_HS_OFFCHIP_PARAM)/sizeof(VGT_HS_OFFCHIP_PARAM[0]), 0, 0 },
+	{ "mmVGT_TF_MEMORY_BASE", REG_MMIO, 0xc250, &VGT_TF_MEMORY_BASE[0], sizeof(VGT_TF_MEMORY_BASE)/sizeof(VGT_TF_MEMORY_BASE[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_VALUE", REG_MMIO, 0xc280, &PA_SU_LINE_STIPPLE_VALUE[0], sizeof(PA_SU_LINE_STIPPLE_VALUE)/sizeof(PA_SU_LINE_STIPPLE_VALUE[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE_STATE", REG_MMIO, 0xc281, &PA_SC_LINE_STIPPLE_STATE[0], sizeof(PA_SC_LINE_STIPPLE_STATE)/sizeof(PA_SC_LINE_STIPPLE_STATE[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MIN_0", REG_MMIO, 0xc284, &PA_SC_SCREEN_EXTENT_MIN_0[0], sizeof(PA_SC_SCREEN_EXTENT_MIN_0)/sizeof(PA_SC_SCREEN_EXTENT_MIN_0[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MAX_0", REG_MMIO, 0xc285, &PA_SC_SCREEN_EXTENT_MAX_0[0], sizeof(PA_SC_SCREEN_EXTENT_MAX_0)/sizeof(PA_SC_SCREEN_EXTENT_MAX_0[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MIN_1", REG_MMIO, 0xc286, &PA_SC_SCREEN_EXTENT_MIN_1[0], sizeof(PA_SC_SCREEN_EXTENT_MIN_1)/sizeof(PA_SC_SCREEN_EXTENT_MIN_1[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MAX_1", REG_MMIO, 0xc28b, &PA_SC_SCREEN_EXTENT_MAX_1[0], sizeof(PA_SC_SCREEN_EXTENT_MAX_1)/sizeof(PA_SC_SCREEN_EXTENT_MAX_1[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a0, &PA_SC_P3D_TRAP_SCREEN_HV_EN[0], sizeof(PA_SC_P3D_TRAP_SCREEN_HV_EN)/sizeof(PA_SC_P3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a1, &PA_SC_P3D_TRAP_SCREEN_H[0], sizeof(PA_SC_P3D_TRAP_SCREEN_H)/sizeof(PA_SC_P3D_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_V", REG_MMIO, 0xc2a2, &PA_SC_P3D_TRAP_SCREEN_V[0], sizeof(PA_SC_P3D_TRAP_SCREEN_V)/sizeof(PA_SC_P3D_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2a3, &PA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(PA_SC_P3D_TRAP_SCREEN_OCCURRENCE)/sizeof(PA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2a4, &PA_SC_P3D_TRAP_SCREEN_COUNT[0], sizeof(PA_SC_P3D_TRAP_SCREEN_COUNT)/sizeof(PA_SC_P3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a8, &PA_SC_HP3D_TRAP_SCREEN_HV_EN[0], sizeof(PA_SC_HP3D_TRAP_SCREEN_HV_EN)/sizeof(PA_SC_HP3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a9, &PA_SC_HP3D_TRAP_SCREEN_H[0], sizeof(PA_SC_HP3D_TRAP_SCREEN_H)/sizeof(PA_SC_HP3D_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_V", REG_MMIO, 0xc2aa, &PA_SC_HP3D_TRAP_SCREEN_V[0], sizeof(PA_SC_HP3D_TRAP_SCREEN_V)/sizeof(PA_SC_HP3D_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2ab, &PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE)/sizeof(PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2ac, &PA_SC_HP3D_TRAP_SCREEN_COUNT[0], sizeof(PA_SC_HP3D_TRAP_SCREEN_COUNT)/sizeof(PA_SC_HP3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2b0, &PA_SC_TRAP_SCREEN_HV_EN[0], sizeof(PA_SC_TRAP_SCREEN_HV_EN)/sizeof(PA_SC_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_H", REG_MMIO, 0xc2b1, &PA_SC_TRAP_SCREEN_H[0], sizeof(PA_SC_TRAP_SCREEN_H)/sizeof(PA_SC_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_V", REG_MMIO, 0xc2b2, &PA_SC_TRAP_SCREEN_V[0], sizeof(PA_SC_TRAP_SCREEN_V)/sizeof(PA_SC_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2b3, &PA_SC_TRAP_SCREEN_OCCURRENCE[0], sizeof(PA_SC_TRAP_SCREEN_OCCURRENCE)/sizeof(PA_SC_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2b4, &PA_SC_TRAP_SCREEN_COUNT[0], sizeof(PA_SC_TRAP_SCREEN_COUNT)/sizeof(PA_SC_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_0", REG_MMIO, 0xc340, &SQ_THREAD_TRACE_USERDATA_0[0], sizeof(SQ_THREAD_TRACE_USERDATA_0)/sizeof(SQ_THREAD_TRACE_USERDATA_0[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_1", REG_MMIO, 0xc341, &SQ_THREAD_TRACE_USERDATA_1[0], sizeof(SQ_THREAD_TRACE_USERDATA_1)/sizeof(SQ_THREAD_TRACE_USERDATA_1[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_2", REG_MMIO, 0xc342, &SQ_THREAD_TRACE_USERDATA_2[0], sizeof(SQ_THREAD_TRACE_USERDATA_2)/sizeof(SQ_THREAD_TRACE_USERDATA_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_3", REG_MMIO, 0xc343, &SQ_THREAD_TRACE_USERDATA_3[0], sizeof(SQ_THREAD_TRACE_USERDATA_3)/sizeof(SQ_THREAD_TRACE_USERDATA_3[0]), 0, 0 },
+	{ "mmSQC_CACHES", REG_MMIO, 0xc348, &SQC_CACHES[0], sizeof(SQC_CACHES)/sizeof(SQC_CACHES[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR", REG_MMIO, 0xc380, &TA_CS_BC_BASE_ADDR[0], sizeof(TA_CS_BC_BASE_ADDR)/sizeof(TA_CS_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR_HI", REG_MMIO, 0xc381, &TA_CS_BC_BASE_ADDR_HI[0], sizeof(TA_CS_BC_BASE_ADDR_HI)/sizeof(TA_CS_BC_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT0_LOW", REG_MMIO, 0xc3c0, &DB_OCCLUSION_COUNT0_LOW[0], sizeof(DB_OCCLUSION_COUNT0_LOW)/sizeof(DB_OCCLUSION_COUNT0_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT0_HI", REG_MMIO, 0xc3c1, &DB_OCCLUSION_COUNT0_HI[0], sizeof(DB_OCCLUSION_COUNT0_HI)/sizeof(DB_OCCLUSION_COUNT0_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT1_LOW", REG_MMIO, 0xc3c2, &DB_OCCLUSION_COUNT1_LOW[0], sizeof(DB_OCCLUSION_COUNT1_LOW)/sizeof(DB_OCCLUSION_COUNT1_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT1_HI", REG_MMIO, 0xc3c3, &DB_OCCLUSION_COUNT1_HI[0], sizeof(DB_OCCLUSION_COUNT1_HI)/sizeof(DB_OCCLUSION_COUNT1_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT2_LOW", REG_MMIO, 0xc3c4, &DB_OCCLUSION_COUNT2_LOW[0], sizeof(DB_OCCLUSION_COUNT2_LOW)/sizeof(DB_OCCLUSION_COUNT2_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT2_HI", REG_MMIO, 0xc3c5, &DB_OCCLUSION_COUNT2_HI[0], sizeof(DB_OCCLUSION_COUNT2_HI)/sizeof(DB_OCCLUSION_COUNT2_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT3_LOW", REG_MMIO, 0xc3c6, &DB_OCCLUSION_COUNT3_LOW[0], sizeof(DB_OCCLUSION_COUNT3_LOW)/sizeof(DB_OCCLUSION_COUNT3_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT3_HI", REG_MMIO, 0xc3c7, &DB_OCCLUSION_COUNT3_HI[0], sizeof(DB_OCCLUSION_COUNT3_HI)/sizeof(DB_OCCLUSION_COUNT3_HI[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_LOW", REG_MMIO, 0xc3fe, &DB_ZPASS_COUNT_LOW[0], sizeof(DB_ZPASS_COUNT_LOW)/sizeof(DB_ZPASS_COUNT_LOW[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_HI", REG_MMIO, 0xc3ff, &DB_ZPASS_COUNT_HI[0], sizeof(DB_ZPASS_COUNT_HI)/sizeof(DB_ZPASS_COUNT_HI[0]), 0, 0 },
+	{ "mmGDS_RD_ADDR", REG_MMIO, 0xc400, &GDS_RD_ADDR[0], sizeof(GDS_RD_ADDR)/sizeof(GDS_RD_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_DATA", REG_MMIO, 0xc401, &GDS_RD_DATA[0], sizeof(GDS_RD_DATA)/sizeof(GDS_RD_DATA[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_ADDR", REG_MMIO, 0xc402, &GDS_RD_BURST_ADDR[0], sizeof(GDS_RD_BURST_ADDR)/sizeof(GDS_RD_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_COUNT", REG_MMIO, 0xc403, &GDS_RD_BURST_COUNT[0], sizeof(GDS_RD_BURST_COUNT)/sizeof(GDS_RD_BURST_COUNT[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_DATA", REG_MMIO, 0xc404, &GDS_RD_BURST_DATA[0], sizeof(GDS_RD_BURST_DATA)/sizeof(GDS_RD_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_ADDR", REG_MMIO, 0xc405, &GDS_WR_ADDR[0], sizeof(GDS_WR_ADDR)/sizeof(GDS_WR_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_DATA", REG_MMIO, 0xc406, &GDS_WR_DATA[0], sizeof(GDS_WR_DATA)/sizeof(GDS_WR_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_ADDR", REG_MMIO, 0xc407, &GDS_WR_BURST_ADDR[0], sizeof(GDS_WR_BURST_ADDR)/sizeof(GDS_WR_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_DATA", REG_MMIO, 0xc408, &GDS_WR_BURST_DATA[0], sizeof(GDS_WR_BURST_DATA)/sizeof(GDS_WR_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WRITE_COMPLETE", REG_MMIO, 0xc409, &GDS_WRITE_COMPLETE[0], sizeof(GDS_WRITE_COMPLETE)/sizeof(GDS_WRITE_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_CNTL", REG_MMIO, 0xc40a, &GDS_ATOM_CNTL[0], sizeof(GDS_ATOM_CNTL)/sizeof(GDS_ATOM_CNTL[0]), 0, 0 },
+	{ "mmGDS_ATOM_COMPLETE", REG_MMIO, 0xc40b, &GDS_ATOM_COMPLETE[0], sizeof(GDS_ATOM_COMPLETE)/sizeof(GDS_ATOM_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_BASE", REG_MMIO, 0xc40c, &GDS_ATOM_BASE[0], sizeof(GDS_ATOM_BASE)/sizeof(GDS_ATOM_BASE[0]), 0, 0 },
+	{ "mmGDS_ATOM_SIZE", REG_MMIO, 0xc40d, &GDS_ATOM_SIZE[0], sizeof(GDS_ATOM_SIZE)/sizeof(GDS_ATOM_SIZE[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET0", REG_MMIO, 0xc40e, &GDS_ATOM_OFFSET0[0], sizeof(GDS_ATOM_OFFSET0)/sizeof(GDS_ATOM_OFFSET0[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET1", REG_MMIO, 0xc40f, &GDS_ATOM_OFFSET1[0], sizeof(GDS_ATOM_OFFSET1)/sizeof(GDS_ATOM_OFFSET1[0]), 0, 0 },
+	{ "mmGDS_ATOM_DST", REG_MMIO, 0xc410, &GDS_ATOM_DST[0], sizeof(GDS_ATOM_DST)/sizeof(GDS_ATOM_DST[0]), 0, 0 },
+	{ "mmGDS_ATOM_OP", REG_MMIO, 0xc411, &GDS_ATOM_OP[0], sizeof(GDS_ATOM_OP)/sizeof(GDS_ATOM_OP[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0", REG_MMIO, 0xc412, &GDS_ATOM_SRC0[0], sizeof(GDS_ATOM_SRC0)/sizeof(GDS_ATOM_SRC0[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0_U", REG_MMIO, 0xc413, &GDS_ATOM_SRC0_U[0], sizeof(GDS_ATOM_SRC0_U)/sizeof(GDS_ATOM_SRC0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1", REG_MMIO, 0xc414, &GDS_ATOM_SRC1[0], sizeof(GDS_ATOM_SRC1)/sizeof(GDS_ATOM_SRC1[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1_U", REG_MMIO, 0xc415, &GDS_ATOM_SRC1_U[0], sizeof(GDS_ATOM_SRC1_U)/sizeof(GDS_ATOM_SRC1_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0", REG_MMIO, 0xc416, &GDS_ATOM_READ0[0], sizeof(GDS_ATOM_READ0)/sizeof(GDS_ATOM_READ0[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0_U", REG_MMIO, 0xc417, &GDS_ATOM_READ0_U[0], sizeof(GDS_ATOM_READ0_U)/sizeof(GDS_ATOM_READ0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1", REG_MMIO, 0xc418, &GDS_ATOM_READ1[0], sizeof(GDS_ATOM_READ1)/sizeof(GDS_ATOM_READ1[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1_U", REG_MMIO, 0xc419, &GDS_ATOM_READ1_U[0], sizeof(GDS_ATOM_READ1_U)/sizeof(GDS_ATOM_READ1_U[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNTL", REG_MMIO, 0xc41a, &GDS_GWS_RESOURCE_CNTL[0], sizeof(GDS_GWS_RESOURCE_CNTL)/sizeof(GDS_GWS_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE", REG_MMIO, 0xc41b, &GDS_GWS_RESOURCE[0], sizeof(GDS_GWS_RESOURCE)/sizeof(GDS_GWS_RESOURCE[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNT", REG_MMIO, 0xc41c, &GDS_GWS_RESOURCE_CNT[0], sizeof(GDS_GWS_RESOURCE_CNT)/sizeof(GDS_GWS_RESOURCE_CNT[0]), 0, 0 },
+	{ "mmGDS_OA_CNTL", REG_MMIO, 0xc41d, &GDS_OA_CNTL[0], sizeof(GDS_OA_CNTL)/sizeof(GDS_OA_CNTL[0]), 0, 0 },
+	{ "mmGDS_OA_COUNTER", REG_MMIO, 0xc41e, &GDS_OA_COUNTER[0], sizeof(GDS_OA_COUNTER)/sizeof(GDS_OA_COUNTER[0]), 0, 0 },
+	{ "mmGDS_OA_ADDRESS", REG_MMIO, 0xc41f, &GDS_OA_ADDRESS[0], sizeof(GDS_OA_ADDRESS)/sizeof(GDS_OA_ADDRESS[0]), 0, 0 },
+	{ "mmGDS_OA_INCDEC", REG_MMIO, 0xc420, &GDS_OA_INCDEC[0], sizeof(GDS_OA_INCDEC)/sizeof(GDS_OA_INCDEC[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_LO", REG_MMIO, 0xd000, &CPG_PERFCOUNTER1_LO[0], sizeof(CPG_PERFCOUNTER1_LO)/sizeof(CPG_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_HI", REG_MMIO, 0xd001, &CPG_PERFCOUNTER1_HI[0], sizeof(CPG_PERFCOUNTER1_HI)/sizeof(CPG_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_LO", REG_MMIO, 0xd002, &CPG_PERFCOUNTER0_LO[0], sizeof(CPG_PERFCOUNTER0_LO)/sizeof(CPG_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_HI", REG_MMIO, 0xd003, &CPG_PERFCOUNTER0_HI[0], sizeof(CPG_PERFCOUNTER0_HI)/sizeof(CPG_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_LO", REG_MMIO, 0xd004, &CPC_PERFCOUNTER1_LO[0], sizeof(CPC_PERFCOUNTER1_LO)/sizeof(CPC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_HI", REG_MMIO, 0xd005, &CPC_PERFCOUNTER1_HI[0], sizeof(CPC_PERFCOUNTER1_HI)/sizeof(CPC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_LO", REG_MMIO, 0xd006, &CPC_PERFCOUNTER0_LO[0], sizeof(CPC_PERFCOUNTER0_LO)/sizeof(CPC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_HI", REG_MMIO, 0xd007, &CPC_PERFCOUNTER0_HI[0], sizeof(CPC_PERFCOUNTER0_HI)/sizeof(CPC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_LO", REG_MMIO, 0xd008, &CPF_PERFCOUNTER1_LO[0], sizeof(CPF_PERFCOUNTER1_LO)/sizeof(CPF_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_HI", REG_MMIO, 0xd009, &CPF_PERFCOUNTER1_HI[0], sizeof(CPF_PERFCOUNTER1_HI)/sizeof(CPF_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_LO", REG_MMIO, 0xd00a, &CPF_PERFCOUNTER0_LO[0], sizeof(CPF_PERFCOUNTER0_LO)/sizeof(CPF_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_HI", REG_MMIO, 0xd00b, &CPF_PERFCOUNTER0_HI[0], sizeof(CPF_PERFCOUNTER0_HI)/sizeof(CPF_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_LO", REG_MMIO, 0xd040, &GRBM_PERFCOUNTER0_LO[0], sizeof(GRBM_PERFCOUNTER0_LO)/sizeof(GRBM_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_HI", REG_MMIO, 0xd041, &GRBM_PERFCOUNTER0_HI[0], sizeof(GRBM_PERFCOUNTER0_HI)/sizeof(GRBM_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_LO", REG_MMIO, 0xd043, &GRBM_PERFCOUNTER1_LO[0], sizeof(GRBM_PERFCOUNTER1_LO)/sizeof(GRBM_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_HI", REG_MMIO, 0xd044, &GRBM_PERFCOUNTER1_HI[0], sizeof(GRBM_PERFCOUNTER1_HI)/sizeof(GRBM_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_LO", REG_MMIO, 0xd045, &GRBM_SE0_PERFCOUNTER_LO[0], sizeof(GRBM_SE0_PERFCOUNTER_LO)/sizeof(GRBM_SE0_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_HI", REG_MMIO, 0xd046, &GRBM_SE0_PERFCOUNTER_HI[0], sizeof(GRBM_SE0_PERFCOUNTER_HI)/sizeof(GRBM_SE0_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_LO", REG_MMIO, 0xd047, &GRBM_SE1_PERFCOUNTER_LO[0], sizeof(GRBM_SE1_PERFCOUNTER_LO)/sizeof(GRBM_SE1_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_HI", REG_MMIO, 0xd048, &GRBM_SE1_PERFCOUNTER_HI[0], sizeof(GRBM_SE1_PERFCOUNTER_HI)/sizeof(GRBM_SE1_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_LO", REG_MMIO, 0xd049, &GRBM_SE2_PERFCOUNTER_LO[0], sizeof(GRBM_SE2_PERFCOUNTER_LO)/sizeof(GRBM_SE2_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_HI", REG_MMIO, 0xd04a, &GRBM_SE2_PERFCOUNTER_HI[0], sizeof(GRBM_SE2_PERFCOUNTER_HI)/sizeof(GRBM_SE2_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_LO", REG_MMIO, 0xd04b, &GRBM_SE3_PERFCOUNTER_LO[0], sizeof(GRBM_SE3_PERFCOUNTER_LO)/sizeof(GRBM_SE3_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_HI", REG_MMIO, 0xd04c, &GRBM_SE3_PERFCOUNTER_HI[0], sizeof(GRBM_SE3_PERFCOUNTER_HI)/sizeof(GRBM_SE3_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_LO", REG_MMIO, 0xd080, &WD_PERFCOUNTER0_LO[0], sizeof(WD_PERFCOUNTER0_LO)/sizeof(WD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_HI", REG_MMIO, 0xd081, &WD_PERFCOUNTER0_HI[0], sizeof(WD_PERFCOUNTER0_HI)/sizeof(WD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_LO", REG_MMIO, 0xd082, &WD_PERFCOUNTER1_LO[0], sizeof(WD_PERFCOUNTER1_LO)/sizeof(WD_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_HI", REG_MMIO, 0xd083, &WD_PERFCOUNTER1_HI[0], sizeof(WD_PERFCOUNTER1_HI)/sizeof(WD_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_LO", REG_MMIO, 0xd084, &WD_PERFCOUNTER2_LO[0], sizeof(WD_PERFCOUNTER2_LO)/sizeof(WD_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_HI", REG_MMIO, 0xd085, &WD_PERFCOUNTER2_HI[0], sizeof(WD_PERFCOUNTER2_HI)/sizeof(WD_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_LO", REG_MMIO, 0xd086, &WD_PERFCOUNTER3_LO[0], sizeof(WD_PERFCOUNTER3_LO)/sizeof(WD_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_HI", REG_MMIO, 0xd087, &WD_PERFCOUNTER3_HI[0], sizeof(WD_PERFCOUNTER3_HI)/sizeof(WD_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_LO", REG_MMIO, 0xd088, &IA_PERFCOUNTER0_LO[0], sizeof(IA_PERFCOUNTER0_LO)/sizeof(IA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_HI", REG_MMIO, 0xd089, &IA_PERFCOUNTER0_HI[0], sizeof(IA_PERFCOUNTER0_HI)/sizeof(IA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_LO", REG_MMIO, 0xd08a, &IA_PERFCOUNTER1_LO[0], sizeof(IA_PERFCOUNTER1_LO)/sizeof(IA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_HI", REG_MMIO, 0xd08b, &IA_PERFCOUNTER1_HI[0], sizeof(IA_PERFCOUNTER1_HI)/sizeof(IA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_LO", REG_MMIO, 0xd08c, &IA_PERFCOUNTER2_LO[0], sizeof(IA_PERFCOUNTER2_LO)/sizeof(IA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_HI", REG_MMIO, 0xd08d, &IA_PERFCOUNTER2_HI[0], sizeof(IA_PERFCOUNTER2_HI)/sizeof(IA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_LO", REG_MMIO, 0xd08e, &IA_PERFCOUNTER3_LO[0], sizeof(IA_PERFCOUNTER3_LO)/sizeof(IA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_HI", REG_MMIO, 0xd08f, &IA_PERFCOUNTER3_HI[0], sizeof(IA_PERFCOUNTER3_HI)/sizeof(IA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_LO", REG_MMIO, 0xd090, &VGT_PERFCOUNTER0_LO[0], sizeof(VGT_PERFCOUNTER0_LO)/sizeof(VGT_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_HI", REG_MMIO, 0xd091, &VGT_PERFCOUNTER0_HI[0], sizeof(VGT_PERFCOUNTER0_HI)/sizeof(VGT_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_LO", REG_MMIO, 0xd092, &VGT_PERFCOUNTER1_LO[0], sizeof(VGT_PERFCOUNTER1_LO)/sizeof(VGT_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_HI", REG_MMIO, 0xd093, &VGT_PERFCOUNTER1_HI[0], sizeof(VGT_PERFCOUNTER1_HI)/sizeof(VGT_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_LO", REG_MMIO, 0xd094, &VGT_PERFCOUNTER2_LO[0], sizeof(VGT_PERFCOUNTER2_LO)/sizeof(VGT_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_HI", REG_MMIO, 0xd095, &VGT_PERFCOUNTER2_HI[0], sizeof(VGT_PERFCOUNTER2_HI)/sizeof(VGT_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_LO", REG_MMIO, 0xd096, &VGT_PERFCOUNTER3_LO[0], sizeof(VGT_PERFCOUNTER3_LO)/sizeof(VGT_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_HI", REG_MMIO, 0xd097, &VGT_PERFCOUNTER3_HI[0], sizeof(VGT_PERFCOUNTER3_HI)/sizeof(VGT_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_LO", REG_MMIO, 0xd100, &PA_SU_PERFCOUNTER0_LO[0], sizeof(PA_SU_PERFCOUNTER0_LO)/sizeof(PA_SU_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_HI", REG_MMIO, 0xd101, &PA_SU_PERFCOUNTER0_HI[0], sizeof(PA_SU_PERFCOUNTER0_HI)/sizeof(PA_SU_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_LO", REG_MMIO, 0xd102, &PA_SU_PERFCOUNTER1_LO[0], sizeof(PA_SU_PERFCOUNTER1_LO)/sizeof(PA_SU_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_HI", REG_MMIO, 0xd103, &PA_SU_PERFCOUNTER1_HI[0], sizeof(PA_SU_PERFCOUNTER1_HI)/sizeof(PA_SU_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_LO", REG_MMIO, 0xd104, &PA_SU_PERFCOUNTER2_LO[0], sizeof(PA_SU_PERFCOUNTER2_LO)/sizeof(PA_SU_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_HI", REG_MMIO, 0xd105, &PA_SU_PERFCOUNTER2_HI[0], sizeof(PA_SU_PERFCOUNTER2_HI)/sizeof(PA_SU_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_LO", REG_MMIO, 0xd106, &PA_SU_PERFCOUNTER3_LO[0], sizeof(PA_SU_PERFCOUNTER3_LO)/sizeof(PA_SU_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_HI", REG_MMIO, 0xd107, &PA_SU_PERFCOUNTER3_HI[0], sizeof(PA_SU_PERFCOUNTER3_HI)/sizeof(PA_SU_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_LO", REG_MMIO, 0xd140, &PA_SC_PERFCOUNTER0_LO[0], sizeof(PA_SC_PERFCOUNTER0_LO)/sizeof(PA_SC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_HI", REG_MMIO, 0xd141, &PA_SC_PERFCOUNTER0_HI[0], sizeof(PA_SC_PERFCOUNTER0_HI)/sizeof(PA_SC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_LO", REG_MMIO, 0xd142, &PA_SC_PERFCOUNTER1_LO[0], sizeof(PA_SC_PERFCOUNTER1_LO)/sizeof(PA_SC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_HI", REG_MMIO, 0xd143, &PA_SC_PERFCOUNTER1_HI[0], sizeof(PA_SC_PERFCOUNTER1_HI)/sizeof(PA_SC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_LO", REG_MMIO, 0xd144, &PA_SC_PERFCOUNTER2_LO[0], sizeof(PA_SC_PERFCOUNTER2_LO)/sizeof(PA_SC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_HI", REG_MMIO, 0xd145, &PA_SC_PERFCOUNTER2_HI[0], sizeof(PA_SC_PERFCOUNTER2_HI)/sizeof(PA_SC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_LO", REG_MMIO, 0xd146, &PA_SC_PERFCOUNTER3_LO[0], sizeof(PA_SC_PERFCOUNTER3_LO)/sizeof(PA_SC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_HI", REG_MMIO, 0xd147, &PA_SC_PERFCOUNTER3_HI[0], sizeof(PA_SC_PERFCOUNTER3_HI)/sizeof(PA_SC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_LO", REG_MMIO, 0xd148, &PA_SC_PERFCOUNTER4_LO[0], sizeof(PA_SC_PERFCOUNTER4_LO)/sizeof(PA_SC_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_HI", REG_MMIO, 0xd149, &PA_SC_PERFCOUNTER4_HI[0], sizeof(PA_SC_PERFCOUNTER4_HI)/sizeof(PA_SC_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_LO", REG_MMIO, 0xd14a, &PA_SC_PERFCOUNTER5_LO[0], sizeof(PA_SC_PERFCOUNTER5_LO)/sizeof(PA_SC_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_HI", REG_MMIO, 0xd14b, &PA_SC_PERFCOUNTER5_HI[0], sizeof(PA_SC_PERFCOUNTER5_HI)/sizeof(PA_SC_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_LO", REG_MMIO, 0xd14c, &PA_SC_PERFCOUNTER6_LO[0], sizeof(PA_SC_PERFCOUNTER6_LO)/sizeof(PA_SC_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_HI", REG_MMIO, 0xd14d, &PA_SC_PERFCOUNTER6_HI[0], sizeof(PA_SC_PERFCOUNTER6_HI)/sizeof(PA_SC_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_LO", REG_MMIO, 0xd14e, &PA_SC_PERFCOUNTER7_LO[0], sizeof(PA_SC_PERFCOUNTER7_LO)/sizeof(PA_SC_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_HI", REG_MMIO, 0xd14f, &PA_SC_PERFCOUNTER7_HI[0], sizeof(PA_SC_PERFCOUNTER7_HI)/sizeof(PA_SC_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_HI", REG_MMIO, 0xd180, &SPI_PERFCOUNTER0_HI[0], sizeof(SPI_PERFCOUNTER0_HI)/sizeof(SPI_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_LO", REG_MMIO, 0xd181, &SPI_PERFCOUNTER0_LO[0], sizeof(SPI_PERFCOUNTER0_LO)/sizeof(SPI_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_HI", REG_MMIO, 0xd182, &SPI_PERFCOUNTER1_HI[0], sizeof(SPI_PERFCOUNTER1_HI)/sizeof(SPI_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_LO", REG_MMIO, 0xd183, &SPI_PERFCOUNTER1_LO[0], sizeof(SPI_PERFCOUNTER1_LO)/sizeof(SPI_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_HI", REG_MMIO, 0xd184, &SPI_PERFCOUNTER2_HI[0], sizeof(SPI_PERFCOUNTER2_HI)/sizeof(SPI_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_LO", REG_MMIO, 0xd185, &SPI_PERFCOUNTER2_LO[0], sizeof(SPI_PERFCOUNTER2_LO)/sizeof(SPI_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_HI", REG_MMIO, 0xd186, &SPI_PERFCOUNTER3_HI[0], sizeof(SPI_PERFCOUNTER3_HI)/sizeof(SPI_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_LO", REG_MMIO, 0xd187, &SPI_PERFCOUNTER3_LO[0], sizeof(SPI_PERFCOUNTER3_LO)/sizeof(SPI_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_HI", REG_MMIO, 0xd188, &SPI_PERFCOUNTER4_HI[0], sizeof(SPI_PERFCOUNTER4_HI)/sizeof(SPI_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_LO", REG_MMIO, 0xd189, &SPI_PERFCOUNTER4_LO[0], sizeof(SPI_PERFCOUNTER4_LO)/sizeof(SPI_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_HI", REG_MMIO, 0xd18a, &SPI_PERFCOUNTER5_HI[0], sizeof(SPI_PERFCOUNTER5_HI)/sizeof(SPI_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_LO", REG_MMIO, 0xd18b, &SPI_PERFCOUNTER5_LO[0], sizeof(SPI_PERFCOUNTER5_LO)/sizeof(SPI_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_LO", REG_MMIO, 0xd1c0, &SQ_PERFCOUNTER0_LO[0], sizeof(SQ_PERFCOUNTER0_LO)/sizeof(SQ_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_HI", REG_MMIO, 0xd1c1, &SQ_PERFCOUNTER0_HI[0], sizeof(SQ_PERFCOUNTER0_HI)/sizeof(SQ_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_LO", REG_MMIO, 0xd1c2, &SQ_PERFCOUNTER1_LO[0], sizeof(SQ_PERFCOUNTER1_LO)/sizeof(SQ_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_HI", REG_MMIO, 0xd1c3, &SQ_PERFCOUNTER1_HI[0], sizeof(SQ_PERFCOUNTER1_HI)/sizeof(SQ_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_LO", REG_MMIO, 0xd1c4, &SQ_PERFCOUNTER2_LO[0], sizeof(SQ_PERFCOUNTER2_LO)/sizeof(SQ_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_HI", REG_MMIO, 0xd1c5, &SQ_PERFCOUNTER2_HI[0], sizeof(SQ_PERFCOUNTER2_HI)/sizeof(SQ_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_LO", REG_MMIO, 0xd1c6, &SQ_PERFCOUNTER3_LO[0], sizeof(SQ_PERFCOUNTER3_LO)/sizeof(SQ_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_HI", REG_MMIO, 0xd1c7, &SQ_PERFCOUNTER3_HI[0], sizeof(SQ_PERFCOUNTER3_HI)/sizeof(SQ_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_LO", REG_MMIO, 0xd1c8, &SQ_PERFCOUNTER4_LO[0], sizeof(SQ_PERFCOUNTER4_LO)/sizeof(SQ_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_HI", REG_MMIO, 0xd1c9, &SQ_PERFCOUNTER4_HI[0], sizeof(SQ_PERFCOUNTER4_HI)/sizeof(SQ_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_LO", REG_MMIO, 0xd1ca, &SQ_PERFCOUNTER5_LO[0], sizeof(SQ_PERFCOUNTER5_LO)/sizeof(SQ_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_HI", REG_MMIO, 0xd1cb, &SQ_PERFCOUNTER5_HI[0], sizeof(SQ_PERFCOUNTER5_HI)/sizeof(SQ_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_LO", REG_MMIO, 0xd1cc, &SQ_PERFCOUNTER6_LO[0], sizeof(SQ_PERFCOUNTER6_LO)/sizeof(SQ_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_HI", REG_MMIO, 0xd1cd, &SQ_PERFCOUNTER6_HI[0], sizeof(SQ_PERFCOUNTER6_HI)/sizeof(SQ_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_LO", REG_MMIO, 0xd1ce, &SQ_PERFCOUNTER7_LO[0], sizeof(SQ_PERFCOUNTER7_LO)/sizeof(SQ_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_HI", REG_MMIO, 0xd1cf, &SQ_PERFCOUNTER7_HI[0], sizeof(SQ_PERFCOUNTER7_HI)/sizeof(SQ_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_LO", REG_MMIO, 0xd1d0, &SQ_PERFCOUNTER8_LO[0], sizeof(SQ_PERFCOUNTER8_LO)/sizeof(SQ_PERFCOUNTER8_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_HI", REG_MMIO, 0xd1d1, &SQ_PERFCOUNTER8_HI[0], sizeof(SQ_PERFCOUNTER8_HI)/sizeof(SQ_PERFCOUNTER8_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_LO", REG_MMIO, 0xd1d2, &SQ_PERFCOUNTER9_LO[0], sizeof(SQ_PERFCOUNTER9_LO)/sizeof(SQ_PERFCOUNTER9_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_HI", REG_MMIO, 0xd1d3, &SQ_PERFCOUNTER9_HI[0], sizeof(SQ_PERFCOUNTER9_HI)/sizeof(SQ_PERFCOUNTER9_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_LO", REG_MMIO, 0xd1d4, &SQ_PERFCOUNTER10_LO[0], sizeof(SQ_PERFCOUNTER10_LO)/sizeof(SQ_PERFCOUNTER10_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_HI", REG_MMIO, 0xd1d5, &SQ_PERFCOUNTER10_HI[0], sizeof(SQ_PERFCOUNTER10_HI)/sizeof(SQ_PERFCOUNTER10_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_LO", REG_MMIO, 0xd1d6, &SQ_PERFCOUNTER11_LO[0], sizeof(SQ_PERFCOUNTER11_LO)/sizeof(SQ_PERFCOUNTER11_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_HI", REG_MMIO, 0xd1d7, &SQ_PERFCOUNTER11_HI[0], sizeof(SQ_PERFCOUNTER11_HI)/sizeof(SQ_PERFCOUNTER11_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_LO", REG_MMIO, 0xd1d8, &SQ_PERFCOUNTER12_LO[0], sizeof(SQ_PERFCOUNTER12_LO)/sizeof(SQ_PERFCOUNTER12_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_HI", REG_MMIO, 0xd1d9, &SQ_PERFCOUNTER12_HI[0], sizeof(SQ_PERFCOUNTER12_HI)/sizeof(SQ_PERFCOUNTER12_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_LO", REG_MMIO, 0xd1da, &SQ_PERFCOUNTER13_LO[0], sizeof(SQ_PERFCOUNTER13_LO)/sizeof(SQ_PERFCOUNTER13_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_HI", REG_MMIO, 0xd1db, &SQ_PERFCOUNTER13_HI[0], sizeof(SQ_PERFCOUNTER13_HI)/sizeof(SQ_PERFCOUNTER13_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_LO", REG_MMIO, 0xd1dc, &SQ_PERFCOUNTER14_LO[0], sizeof(SQ_PERFCOUNTER14_LO)/sizeof(SQ_PERFCOUNTER14_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_HI", REG_MMIO, 0xd1dd, &SQ_PERFCOUNTER14_HI[0], sizeof(SQ_PERFCOUNTER14_HI)/sizeof(SQ_PERFCOUNTER14_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_LO", REG_MMIO, 0xd1de, &SQ_PERFCOUNTER15_LO[0], sizeof(SQ_PERFCOUNTER15_LO)/sizeof(SQ_PERFCOUNTER15_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_HI", REG_MMIO, 0xd1df, &SQ_PERFCOUNTER15_HI[0], sizeof(SQ_PERFCOUNTER15_HI)/sizeof(SQ_PERFCOUNTER15_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_LO", REG_MMIO, 0xd240, &SX_PERFCOUNTER0_LO[0], sizeof(SX_PERFCOUNTER0_LO)/sizeof(SX_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_HI", REG_MMIO, 0xd241, &SX_PERFCOUNTER0_HI[0], sizeof(SX_PERFCOUNTER0_HI)/sizeof(SX_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_LO", REG_MMIO, 0xd242, &SX_PERFCOUNTER1_LO[0], sizeof(SX_PERFCOUNTER1_LO)/sizeof(SX_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_HI", REG_MMIO, 0xd243, &SX_PERFCOUNTER1_HI[0], sizeof(SX_PERFCOUNTER1_HI)/sizeof(SX_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_LO", REG_MMIO, 0xd244, &SX_PERFCOUNTER2_LO[0], sizeof(SX_PERFCOUNTER2_LO)/sizeof(SX_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_HI", REG_MMIO, 0xd245, &SX_PERFCOUNTER2_HI[0], sizeof(SX_PERFCOUNTER2_HI)/sizeof(SX_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_LO", REG_MMIO, 0xd246, &SX_PERFCOUNTER3_LO[0], sizeof(SX_PERFCOUNTER3_LO)/sizeof(SX_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_HI", REG_MMIO, 0xd247, &SX_PERFCOUNTER3_HI[0], sizeof(SX_PERFCOUNTER3_HI)/sizeof(SX_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_LO", REG_MMIO, 0xd280, &GDS_PERFCOUNTER0_LO[0], sizeof(GDS_PERFCOUNTER0_LO)/sizeof(GDS_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_HI", REG_MMIO, 0xd281, &GDS_PERFCOUNTER0_HI[0], sizeof(GDS_PERFCOUNTER0_HI)/sizeof(GDS_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_LO", REG_MMIO, 0xd282, &GDS_PERFCOUNTER1_LO[0], sizeof(GDS_PERFCOUNTER1_LO)/sizeof(GDS_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_HI", REG_MMIO, 0xd283, &GDS_PERFCOUNTER1_HI[0], sizeof(GDS_PERFCOUNTER1_HI)/sizeof(GDS_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_LO", REG_MMIO, 0xd284, &GDS_PERFCOUNTER2_LO[0], sizeof(GDS_PERFCOUNTER2_LO)/sizeof(GDS_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_HI", REG_MMIO, 0xd285, &GDS_PERFCOUNTER2_HI[0], sizeof(GDS_PERFCOUNTER2_HI)/sizeof(GDS_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_LO", REG_MMIO, 0xd286, &GDS_PERFCOUNTER3_LO[0], sizeof(GDS_PERFCOUNTER3_LO)/sizeof(GDS_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_HI", REG_MMIO, 0xd287, &GDS_PERFCOUNTER3_HI[0], sizeof(GDS_PERFCOUNTER3_HI)/sizeof(GDS_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_LO", REG_MMIO, 0xd2c0, &TA_PERFCOUNTER0_LO[0], sizeof(TA_PERFCOUNTER0_LO)/sizeof(TA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_HI", REG_MMIO, 0xd2c1, &TA_PERFCOUNTER0_HI[0], sizeof(TA_PERFCOUNTER0_HI)/sizeof(TA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_LO", REG_MMIO, 0xd2c2, &TA_PERFCOUNTER1_LO[0], sizeof(TA_PERFCOUNTER1_LO)/sizeof(TA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_HI", REG_MMIO, 0xd2c3, &TA_PERFCOUNTER1_HI[0], sizeof(TA_PERFCOUNTER1_HI)/sizeof(TA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_LO", REG_MMIO, 0xd300, &TD_PERFCOUNTER0_LO[0], sizeof(TD_PERFCOUNTER0_LO)/sizeof(TD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_HI", REG_MMIO, 0xd301, &TD_PERFCOUNTER0_HI[0], sizeof(TD_PERFCOUNTER0_HI)/sizeof(TD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_LO", REG_MMIO, 0xd302, &TD_PERFCOUNTER1_LO[0], sizeof(TD_PERFCOUNTER1_LO)/sizeof(TD_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_HI", REG_MMIO, 0xd303, &TD_PERFCOUNTER1_HI[0], sizeof(TD_PERFCOUNTER1_HI)/sizeof(TD_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_LO", REG_MMIO, 0xd340, &TCP_PERFCOUNTER0_LO[0], sizeof(TCP_PERFCOUNTER0_LO)/sizeof(TCP_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_HI", REG_MMIO, 0xd341, &TCP_PERFCOUNTER0_HI[0], sizeof(TCP_PERFCOUNTER0_HI)/sizeof(TCP_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_LO", REG_MMIO, 0xd342, &TCP_PERFCOUNTER1_LO[0], sizeof(TCP_PERFCOUNTER1_LO)/sizeof(TCP_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_HI", REG_MMIO, 0xd343, &TCP_PERFCOUNTER1_HI[0], sizeof(TCP_PERFCOUNTER1_HI)/sizeof(TCP_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_LO", REG_MMIO, 0xd344, &TCP_PERFCOUNTER2_LO[0], sizeof(TCP_PERFCOUNTER2_LO)/sizeof(TCP_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_HI", REG_MMIO, 0xd345, &TCP_PERFCOUNTER2_HI[0], sizeof(TCP_PERFCOUNTER2_HI)/sizeof(TCP_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_LO", REG_MMIO, 0xd346, &TCP_PERFCOUNTER3_LO[0], sizeof(TCP_PERFCOUNTER3_LO)/sizeof(TCP_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_HI", REG_MMIO, 0xd347, &TCP_PERFCOUNTER3_HI[0], sizeof(TCP_PERFCOUNTER3_HI)/sizeof(TCP_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_LO", REG_MMIO, 0xd380, &TCC_PERFCOUNTER0_LO[0], sizeof(TCC_PERFCOUNTER0_LO)/sizeof(TCC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_HI", REG_MMIO, 0xd381, &TCC_PERFCOUNTER0_HI[0], sizeof(TCC_PERFCOUNTER0_HI)/sizeof(TCC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_LO", REG_MMIO, 0xd382, &TCC_PERFCOUNTER1_LO[0], sizeof(TCC_PERFCOUNTER1_LO)/sizeof(TCC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_HI", REG_MMIO, 0xd383, &TCC_PERFCOUNTER1_HI[0], sizeof(TCC_PERFCOUNTER1_HI)/sizeof(TCC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_LO", REG_MMIO, 0xd384, &TCC_PERFCOUNTER2_LO[0], sizeof(TCC_PERFCOUNTER2_LO)/sizeof(TCC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_HI", REG_MMIO, 0xd385, &TCC_PERFCOUNTER2_HI[0], sizeof(TCC_PERFCOUNTER2_HI)/sizeof(TCC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_LO", REG_MMIO, 0xd386, &TCC_PERFCOUNTER3_LO[0], sizeof(TCC_PERFCOUNTER3_LO)/sizeof(TCC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_HI", REG_MMIO, 0xd387, &TCC_PERFCOUNTER3_HI[0], sizeof(TCC_PERFCOUNTER3_HI)/sizeof(TCC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_LO", REG_MMIO, 0xd390, &TCA_PERFCOUNTER0_LO[0], sizeof(TCA_PERFCOUNTER0_LO)/sizeof(TCA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_HI", REG_MMIO, 0xd391, &TCA_PERFCOUNTER0_HI[0], sizeof(TCA_PERFCOUNTER0_HI)/sizeof(TCA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_LO", REG_MMIO, 0xd392, &TCA_PERFCOUNTER1_LO[0], sizeof(TCA_PERFCOUNTER1_LO)/sizeof(TCA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_HI", REG_MMIO, 0xd393, &TCA_PERFCOUNTER1_HI[0], sizeof(TCA_PERFCOUNTER1_HI)/sizeof(TCA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_LO", REG_MMIO, 0xd394, &TCA_PERFCOUNTER2_LO[0], sizeof(TCA_PERFCOUNTER2_LO)/sizeof(TCA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_HI", REG_MMIO, 0xd395, &TCA_PERFCOUNTER2_HI[0], sizeof(TCA_PERFCOUNTER2_HI)/sizeof(TCA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_LO", REG_MMIO, 0xd396, &TCA_PERFCOUNTER3_LO[0], sizeof(TCA_PERFCOUNTER3_LO)/sizeof(TCA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_HI", REG_MMIO, 0xd397, &TCA_PERFCOUNTER3_HI[0], sizeof(TCA_PERFCOUNTER3_HI)/sizeof(TCA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER0_LO", REG_MMIO, 0xd3a0, &TCS_PERFCOUNTER0_LO[0], sizeof(TCS_PERFCOUNTER0_LO)/sizeof(TCS_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER0_HI", REG_MMIO, 0xd3a1, &TCS_PERFCOUNTER0_HI[0], sizeof(TCS_PERFCOUNTER0_HI)/sizeof(TCS_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER1_LO", REG_MMIO, 0xd3a2, &TCS_PERFCOUNTER1_LO[0], sizeof(TCS_PERFCOUNTER1_LO)/sizeof(TCS_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER1_HI", REG_MMIO, 0xd3a3, &TCS_PERFCOUNTER1_HI[0], sizeof(TCS_PERFCOUNTER1_HI)/sizeof(TCS_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER2_LO", REG_MMIO, 0xd3a4, &TCS_PERFCOUNTER2_LO[0], sizeof(TCS_PERFCOUNTER2_LO)/sizeof(TCS_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER2_HI", REG_MMIO, 0xd3a5, &TCS_PERFCOUNTER2_HI[0], sizeof(TCS_PERFCOUNTER2_HI)/sizeof(TCS_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER3_LO", REG_MMIO, 0xd3a6, &TCS_PERFCOUNTER3_LO[0], sizeof(TCS_PERFCOUNTER3_LO)/sizeof(TCS_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER3_HI", REG_MMIO, 0xd3a7, &TCS_PERFCOUNTER3_HI[0], sizeof(TCS_PERFCOUNTER3_HI)/sizeof(TCS_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_LO", REG_MMIO, 0xd406, &CB_PERFCOUNTER0_LO[0], sizeof(CB_PERFCOUNTER0_LO)/sizeof(CB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_HI", REG_MMIO, 0xd407, &CB_PERFCOUNTER0_HI[0], sizeof(CB_PERFCOUNTER0_HI)/sizeof(CB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_LO", REG_MMIO, 0xd408, &CB_PERFCOUNTER1_LO[0], sizeof(CB_PERFCOUNTER1_LO)/sizeof(CB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_HI", REG_MMIO, 0xd409, &CB_PERFCOUNTER1_HI[0], sizeof(CB_PERFCOUNTER1_HI)/sizeof(CB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_LO", REG_MMIO, 0xd40a, &CB_PERFCOUNTER2_LO[0], sizeof(CB_PERFCOUNTER2_LO)/sizeof(CB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_HI", REG_MMIO, 0xd40b, &CB_PERFCOUNTER2_HI[0], sizeof(CB_PERFCOUNTER2_HI)/sizeof(CB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_LO", REG_MMIO, 0xd40c, &CB_PERFCOUNTER3_LO[0], sizeof(CB_PERFCOUNTER3_LO)/sizeof(CB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_HI", REG_MMIO, 0xd40d, &CB_PERFCOUNTER3_HI[0], sizeof(CB_PERFCOUNTER3_HI)/sizeof(CB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_LO", REG_MMIO, 0xd440, &DB_PERFCOUNTER0_LO[0], sizeof(DB_PERFCOUNTER0_LO)/sizeof(DB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_HI", REG_MMIO, 0xd441, &DB_PERFCOUNTER0_HI[0], sizeof(DB_PERFCOUNTER0_HI)/sizeof(DB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_LO", REG_MMIO, 0xd442, &DB_PERFCOUNTER1_LO[0], sizeof(DB_PERFCOUNTER1_LO)/sizeof(DB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_HI", REG_MMIO, 0xd443, &DB_PERFCOUNTER1_HI[0], sizeof(DB_PERFCOUNTER1_HI)/sizeof(DB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_LO", REG_MMIO, 0xd444, &DB_PERFCOUNTER2_LO[0], sizeof(DB_PERFCOUNTER2_LO)/sizeof(DB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_HI", REG_MMIO, 0xd445, &DB_PERFCOUNTER2_HI[0], sizeof(DB_PERFCOUNTER2_HI)/sizeof(DB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_LO", REG_MMIO, 0xd446, &DB_PERFCOUNTER3_LO[0], sizeof(DB_PERFCOUNTER3_LO)/sizeof(DB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_HI", REG_MMIO, 0xd447, &DB_PERFCOUNTER3_HI[0], sizeof(DB_PERFCOUNTER3_HI)/sizeof(DB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_LO", REG_MMIO, 0xd480, &RLC_PERFCOUNTER0_LO[0], sizeof(RLC_PERFCOUNTER0_LO)/sizeof(RLC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_HI", REG_MMIO, 0xd481, &RLC_PERFCOUNTER0_HI[0], sizeof(RLC_PERFCOUNTER0_HI)/sizeof(RLC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_LO", REG_MMIO, 0xd482, &RLC_PERFCOUNTER1_LO[0], sizeof(RLC_PERFCOUNTER1_LO)/sizeof(RLC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_HI", REG_MMIO, 0xd483, &RLC_PERFCOUNTER1_HI[0], sizeof(RLC_PERFCOUNTER1_HI)/sizeof(RLC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_SELECT", REG_MMIO, 0xd800, &CPG_PERFCOUNTER1_SELECT[0], sizeof(CPG_PERFCOUNTER1_SELECT)/sizeof(CPG_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd801, &CPG_PERFCOUNTER0_SELECT1[0], sizeof(CPG_PERFCOUNTER0_SELECT1)/sizeof(CPG_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_SELECT", REG_MMIO, 0xd802, &CPG_PERFCOUNTER0_SELECT[0], sizeof(CPG_PERFCOUNTER0_SELECT)/sizeof(CPG_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd803, &CPC_PERFCOUNTER1_SELECT[0], sizeof(CPC_PERFCOUNTER1_SELECT)/sizeof(CPC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd804, &CPC_PERFCOUNTER0_SELECT1[0], sizeof(CPC_PERFCOUNTER0_SELECT1)/sizeof(CPC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_SELECT", REG_MMIO, 0xd805, &CPF_PERFCOUNTER1_SELECT[0], sizeof(CPF_PERFCOUNTER1_SELECT)/sizeof(CPF_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd806, &CPF_PERFCOUNTER0_SELECT1[0], sizeof(CPF_PERFCOUNTER0_SELECT1)/sizeof(CPF_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_SELECT", REG_MMIO, 0xd807, &CPF_PERFCOUNTER0_SELECT[0], sizeof(CPF_PERFCOUNTER0_SELECT)/sizeof(CPF_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTL", REG_MMIO, 0xd808, &CP_PERFMON_CNTL[0], sizeof(CP_PERFMON_CNTL)/sizeof(CP_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd809, &CPC_PERFCOUNTER0_SELECT[0], sizeof(CPC_PERFCOUNTER0_SELECT)/sizeof(CPC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0xd840, &GRBM_PERFCOUNTER0_SELECT[0], sizeof(GRBM_PERFCOUNTER0_SELECT)/sizeof(GRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0xd841, &GRBM_PERFCOUNTER1_SELECT[0], sizeof(GRBM_PERFCOUNTER1_SELECT)/sizeof(GRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_SELECT", REG_MMIO, 0xd842, &GRBM_SE0_PERFCOUNTER_SELECT[0], sizeof(GRBM_SE0_PERFCOUNTER_SELECT)/sizeof(GRBM_SE0_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_SELECT", REG_MMIO, 0xd843, &GRBM_SE1_PERFCOUNTER_SELECT[0], sizeof(GRBM_SE1_PERFCOUNTER_SELECT)/sizeof(GRBM_SE1_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_SELECT", REG_MMIO, 0xd844, &GRBM_SE2_PERFCOUNTER_SELECT[0], sizeof(GRBM_SE2_PERFCOUNTER_SELECT)/sizeof(GRBM_SE2_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_SELECT", REG_MMIO, 0xd845, &GRBM_SE3_PERFCOUNTER_SELECT[0], sizeof(GRBM_SE3_PERFCOUNTER_SELECT)/sizeof(GRBM_SE3_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_SELECT", REG_MMIO, 0xd880, &WD_PERFCOUNTER0_SELECT[0], sizeof(WD_PERFCOUNTER0_SELECT)/sizeof(WD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_SELECT", REG_MMIO, 0xd881, &WD_PERFCOUNTER1_SELECT[0], sizeof(WD_PERFCOUNTER1_SELECT)/sizeof(WD_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_SELECT", REG_MMIO, 0xd882, &WD_PERFCOUNTER2_SELECT[0], sizeof(WD_PERFCOUNTER2_SELECT)/sizeof(WD_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_SELECT", REG_MMIO, 0xd883, &WD_PERFCOUNTER3_SELECT[0], sizeof(WD_PERFCOUNTER3_SELECT)/sizeof(WD_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT", REG_MMIO, 0xd884, &IA_PERFCOUNTER0_SELECT[0], sizeof(IA_PERFCOUNTER0_SELECT)/sizeof(IA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_SELECT", REG_MMIO, 0xd885, &IA_PERFCOUNTER1_SELECT[0], sizeof(IA_PERFCOUNTER1_SELECT)/sizeof(IA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_SELECT", REG_MMIO, 0xd886, &IA_PERFCOUNTER2_SELECT[0], sizeof(IA_PERFCOUNTER2_SELECT)/sizeof(IA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_SELECT", REG_MMIO, 0xd887, &IA_PERFCOUNTER3_SELECT[0], sizeof(IA_PERFCOUNTER3_SELECT)/sizeof(IA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd888, &IA_PERFCOUNTER0_SELECT1[0], sizeof(IA_PERFCOUNTER0_SELECT1)/sizeof(IA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT", REG_MMIO, 0xd88c, &VGT_PERFCOUNTER0_SELECT[0], sizeof(VGT_PERFCOUNTER0_SELECT)/sizeof(VGT_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT", REG_MMIO, 0xd88d, &VGT_PERFCOUNTER1_SELECT[0], sizeof(VGT_PERFCOUNTER1_SELECT)/sizeof(VGT_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_SELECT", REG_MMIO, 0xd88e, &VGT_PERFCOUNTER2_SELECT[0], sizeof(VGT_PERFCOUNTER2_SELECT)/sizeof(VGT_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_SELECT", REG_MMIO, 0xd88f, &VGT_PERFCOUNTER3_SELECT[0], sizeof(VGT_PERFCOUNTER3_SELECT)/sizeof(VGT_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd890, &VGT_PERFCOUNTER0_SELECT1[0], sizeof(VGT_PERFCOUNTER0_SELECT1)/sizeof(VGT_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd891, &VGT_PERFCOUNTER1_SELECT1[0], sizeof(VGT_PERFCOUNTER1_SELECT1)/sizeof(VGT_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER_SEID_MASK", REG_MMIO, 0xd894, &VGT_PERFCOUNTER_SEID_MASK[0], sizeof(VGT_PERFCOUNTER_SEID_MASK)/sizeof(VGT_PERFCOUNTER_SEID_MASK[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT", REG_MMIO, 0xd900, &PA_SU_PERFCOUNTER0_SELECT[0], sizeof(PA_SU_PERFCOUNTER0_SELECT)/sizeof(PA_SU_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd901, &PA_SU_PERFCOUNTER0_SELECT1[0], sizeof(PA_SU_PERFCOUNTER0_SELECT1)/sizeof(PA_SU_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT", REG_MMIO, 0xd902, &PA_SU_PERFCOUNTER1_SELECT[0], sizeof(PA_SU_PERFCOUNTER1_SELECT)/sizeof(PA_SU_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd903, &PA_SU_PERFCOUNTER1_SELECT1[0], sizeof(PA_SU_PERFCOUNTER1_SELECT1)/sizeof(PA_SU_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_SELECT", REG_MMIO, 0xd904, &PA_SU_PERFCOUNTER2_SELECT[0], sizeof(PA_SU_PERFCOUNTER2_SELECT)/sizeof(PA_SU_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_SELECT", REG_MMIO, 0xd905, &PA_SU_PERFCOUNTER3_SELECT[0], sizeof(PA_SU_PERFCOUNTER3_SELECT)/sizeof(PA_SU_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd940, &PA_SC_PERFCOUNTER0_SELECT[0], sizeof(PA_SC_PERFCOUNTER0_SELECT)/sizeof(PA_SC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd941, &PA_SC_PERFCOUNTER0_SELECT1[0], sizeof(PA_SC_PERFCOUNTER0_SELECT1)/sizeof(PA_SC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd942, &PA_SC_PERFCOUNTER1_SELECT[0], sizeof(PA_SC_PERFCOUNTER1_SELECT)/sizeof(PA_SC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_SELECT", REG_MMIO, 0xd943, &PA_SC_PERFCOUNTER2_SELECT[0], sizeof(PA_SC_PERFCOUNTER2_SELECT)/sizeof(PA_SC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_SELECT", REG_MMIO, 0xd944, &PA_SC_PERFCOUNTER3_SELECT[0], sizeof(PA_SC_PERFCOUNTER3_SELECT)/sizeof(PA_SC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_SELECT", REG_MMIO, 0xd945, &PA_SC_PERFCOUNTER4_SELECT[0], sizeof(PA_SC_PERFCOUNTER4_SELECT)/sizeof(PA_SC_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_SELECT", REG_MMIO, 0xd946, &PA_SC_PERFCOUNTER5_SELECT[0], sizeof(PA_SC_PERFCOUNTER5_SELECT)/sizeof(PA_SC_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_SELECT", REG_MMIO, 0xd947, &PA_SC_PERFCOUNTER6_SELECT[0], sizeof(PA_SC_PERFCOUNTER6_SELECT)/sizeof(PA_SC_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_SELECT", REG_MMIO, 0xd948, &PA_SC_PERFCOUNTER7_SELECT[0], sizeof(PA_SC_PERFCOUNTER7_SELECT)/sizeof(PA_SC_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT", REG_MMIO, 0xd980, &SPI_PERFCOUNTER0_SELECT[0], sizeof(SPI_PERFCOUNTER0_SELECT)/sizeof(SPI_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT", REG_MMIO, 0xd981, &SPI_PERFCOUNTER1_SELECT[0], sizeof(SPI_PERFCOUNTER1_SELECT)/sizeof(SPI_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT", REG_MMIO, 0xd982, &SPI_PERFCOUNTER2_SELECT[0], sizeof(SPI_PERFCOUNTER2_SELECT)/sizeof(SPI_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT", REG_MMIO, 0xd983, &SPI_PERFCOUNTER3_SELECT[0], sizeof(SPI_PERFCOUNTER3_SELECT)/sizeof(SPI_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd984, &SPI_PERFCOUNTER0_SELECT1[0], sizeof(SPI_PERFCOUNTER0_SELECT1)/sizeof(SPI_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd985, &SPI_PERFCOUNTER1_SELECT1[0], sizeof(SPI_PERFCOUNTER1_SELECT1)/sizeof(SPI_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT1", REG_MMIO, 0xd986, &SPI_PERFCOUNTER2_SELECT1[0], sizeof(SPI_PERFCOUNTER2_SELECT1)/sizeof(SPI_PERFCOUNTER2_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT1", REG_MMIO, 0xd987, &SPI_PERFCOUNTER3_SELECT1[0], sizeof(SPI_PERFCOUNTER3_SELECT1)/sizeof(SPI_PERFCOUNTER3_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_SELECT", REG_MMIO, 0xd988, &SPI_PERFCOUNTER4_SELECT[0], sizeof(SPI_PERFCOUNTER4_SELECT)/sizeof(SPI_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_SELECT", REG_MMIO, 0xd989, &SPI_PERFCOUNTER5_SELECT[0], sizeof(SPI_PERFCOUNTER5_SELECT)/sizeof(SPI_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER_BINS", REG_MMIO, 0xd98a, &SPI_PERFCOUNTER_BINS[0], sizeof(SPI_PERFCOUNTER_BINS)/sizeof(SPI_PERFCOUNTER_BINS[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_SELECT", REG_MMIO, 0xd9c0, &SQ_PERFCOUNTER0_SELECT[0], sizeof(SQ_PERFCOUNTER0_SELECT)/sizeof(SQ_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_SELECT", REG_MMIO, 0xd9c1, &SQ_PERFCOUNTER1_SELECT[0], sizeof(SQ_PERFCOUNTER1_SELECT)/sizeof(SQ_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_SELECT", REG_MMIO, 0xd9c2, &SQ_PERFCOUNTER2_SELECT[0], sizeof(SQ_PERFCOUNTER2_SELECT)/sizeof(SQ_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_SELECT", REG_MMIO, 0xd9c3, &SQ_PERFCOUNTER3_SELECT[0], sizeof(SQ_PERFCOUNTER3_SELECT)/sizeof(SQ_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_SELECT", REG_MMIO, 0xd9c4, &SQ_PERFCOUNTER4_SELECT[0], sizeof(SQ_PERFCOUNTER4_SELECT)/sizeof(SQ_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_SELECT", REG_MMIO, 0xd9c5, &SQ_PERFCOUNTER5_SELECT[0], sizeof(SQ_PERFCOUNTER5_SELECT)/sizeof(SQ_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_SELECT", REG_MMIO, 0xd9c6, &SQ_PERFCOUNTER6_SELECT[0], sizeof(SQ_PERFCOUNTER6_SELECT)/sizeof(SQ_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_SELECT", REG_MMIO, 0xd9c7, &SQ_PERFCOUNTER7_SELECT[0], sizeof(SQ_PERFCOUNTER7_SELECT)/sizeof(SQ_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_SELECT", REG_MMIO, 0xd9c8, &SQ_PERFCOUNTER8_SELECT[0], sizeof(SQ_PERFCOUNTER8_SELECT)/sizeof(SQ_PERFCOUNTER8_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_SELECT", REG_MMIO, 0xd9c9, &SQ_PERFCOUNTER9_SELECT[0], sizeof(SQ_PERFCOUNTER9_SELECT)/sizeof(SQ_PERFCOUNTER9_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_SELECT", REG_MMIO, 0xd9ca, &SQ_PERFCOUNTER10_SELECT[0], sizeof(SQ_PERFCOUNTER10_SELECT)/sizeof(SQ_PERFCOUNTER10_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_SELECT", REG_MMIO, 0xd9cb, &SQ_PERFCOUNTER11_SELECT[0], sizeof(SQ_PERFCOUNTER11_SELECT)/sizeof(SQ_PERFCOUNTER11_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_SELECT", REG_MMIO, 0xd9cc, &SQ_PERFCOUNTER12_SELECT[0], sizeof(SQ_PERFCOUNTER12_SELECT)/sizeof(SQ_PERFCOUNTER12_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_SELECT", REG_MMIO, 0xd9cd, &SQ_PERFCOUNTER13_SELECT[0], sizeof(SQ_PERFCOUNTER13_SELECT)/sizeof(SQ_PERFCOUNTER13_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_SELECT", REG_MMIO, 0xd9ce, &SQ_PERFCOUNTER14_SELECT[0], sizeof(SQ_PERFCOUNTER14_SELECT)/sizeof(SQ_PERFCOUNTER14_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_SELECT", REG_MMIO, 0xd9cf, &SQ_PERFCOUNTER15_SELECT[0], sizeof(SQ_PERFCOUNTER15_SELECT)/sizeof(SQ_PERFCOUNTER15_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL", REG_MMIO, 0xd9e0, &SQ_PERFCOUNTER_CTRL[0], sizeof(SQ_PERFCOUNTER_CTRL)/sizeof(SQ_PERFCOUNTER_CTRL[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_MASK", REG_MMIO, 0xd9e1, &SQ_PERFCOUNTER_MASK[0], sizeof(SQ_PERFCOUNTER_MASK)/sizeof(SQ_PERFCOUNTER_MASK[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL2", REG_MMIO, 0xd9e2, &SQ_PERFCOUNTER_CTRL2[0], sizeof(SQ_PERFCOUNTER_CTRL2)/sizeof(SQ_PERFCOUNTER_CTRL2[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT", REG_MMIO, 0xda40, &SX_PERFCOUNTER0_SELECT[0], sizeof(SX_PERFCOUNTER0_SELECT)/sizeof(SX_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT", REG_MMIO, 0xda41, &SX_PERFCOUNTER1_SELECT[0], sizeof(SX_PERFCOUNTER1_SELECT)/sizeof(SX_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_SELECT", REG_MMIO, 0xda42, &SX_PERFCOUNTER2_SELECT[0], sizeof(SX_PERFCOUNTER2_SELECT)/sizeof(SX_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_SELECT", REG_MMIO, 0xda43, &SX_PERFCOUNTER3_SELECT[0], sizeof(SX_PERFCOUNTER3_SELECT)/sizeof(SX_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda44, &SX_PERFCOUNTER0_SELECT1[0], sizeof(SX_PERFCOUNTER0_SELECT1)/sizeof(SX_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT1", REG_MMIO, 0xda45, &SX_PERFCOUNTER1_SELECT1[0], sizeof(SX_PERFCOUNTER1_SELECT1)/sizeof(SX_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT", REG_MMIO, 0xda80, &GDS_PERFCOUNTER0_SELECT[0], sizeof(GDS_PERFCOUNTER0_SELECT)/sizeof(GDS_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_SELECT", REG_MMIO, 0xda81, &GDS_PERFCOUNTER1_SELECT[0], sizeof(GDS_PERFCOUNTER1_SELECT)/sizeof(GDS_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_SELECT", REG_MMIO, 0xda82, &GDS_PERFCOUNTER2_SELECT[0], sizeof(GDS_PERFCOUNTER2_SELECT)/sizeof(GDS_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_SELECT", REG_MMIO, 0xda83, &GDS_PERFCOUNTER3_SELECT[0], sizeof(GDS_PERFCOUNTER3_SELECT)/sizeof(GDS_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda84, &GDS_PERFCOUNTER0_SELECT1[0], sizeof(GDS_PERFCOUNTER0_SELECT1)/sizeof(GDS_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdac0, &TA_PERFCOUNTER0_SELECT[0], sizeof(TA_PERFCOUNTER0_SELECT)/sizeof(TA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdac1, &TA_PERFCOUNTER0_SELECT1[0], sizeof(TA_PERFCOUNTER0_SELECT1)/sizeof(TA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdac2, &TA_PERFCOUNTER1_SELECT[0], sizeof(TA_PERFCOUNTER1_SELECT)/sizeof(TA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb00, &TD_PERFCOUNTER0_SELECT[0], sizeof(TD_PERFCOUNTER0_SELECT)/sizeof(TD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb01, &TD_PERFCOUNTER0_SELECT1[0], sizeof(TD_PERFCOUNTER0_SELECT1)/sizeof(TD_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb02, &TD_PERFCOUNTER1_SELECT[0], sizeof(TD_PERFCOUNTER1_SELECT)/sizeof(TD_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb40, &TCP_PERFCOUNTER0_SELECT[0], sizeof(TCP_PERFCOUNTER0_SELECT)/sizeof(TCP_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb41, &TCP_PERFCOUNTER0_SELECT1[0], sizeof(TCP_PERFCOUNTER0_SELECT1)/sizeof(TCP_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb42, &TCP_PERFCOUNTER1_SELECT[0], sizeof(TCP_PERFCOUNTER1_SELECT)/sizeof(TCP_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb43, &TCP_PERFCOUNTER1_SELECT1[0], sizeof(TCP_PERFCOUNTER1_SELECT1)/sizeof(TCP_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb44, &TCP_PERFCOUNTER2_SELECT[0], sizeof(TCP_PERFCOUNTER2_SELECT)/sizeof(TCP_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb45, &TCP_PERFCOUNTER3_SELECT[0], sizeof(TCP_PERFCOUNTER3_SELECT)/sizeof(TCP_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb80, &TCC_PERFCOUNTER0_SELECT[0], sizeof(TCC_PERFCOUNTER0_SELECT)/sizeof(TCC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb81, &TCC_PERFCOUNTER0_SELECT1[0], sizeof(TCC_PERFCOUNTER0_SELECT1)/sizeof(TCC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb82, &TCC_PERFCOUNTER1_SELECT[0], sizeof(TCC_PERFCOUNTER1_SELECT)/sizeof(TCC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb83, &TCC_PERFCOUNTER1_SELECT1[0], sizeof(TCC_PERFCOUNTER1_SELECT1)/sizeof(TCC_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb84, &TCC_PERFCOUNTER2_SELECT[0], sizeof(TCC_PERFCOUNTER2_SELECT)/sizeof(TCC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb85, &TCC_PERFCOUNTER3_SELECT[0], sizeof(TCC_PERFCOUNTER3_SELECT)/sizeof(TCC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb90, &TCA_PERFCOUNTER0_SELECT[0], sizeof(TCA_PERFCOUNTER0_SELECT)/sizeof(TCA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb91, &TCA_PERFCOUNTER0_SELECT1[0], sizeof(TCA_PERFCOUNTER0_SELECT1)/sizeof(TCA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb92, &TCA_PERFCOUNTER1_SELECT[0], sizeof(TCA_PERFCOUNTER1_SELECT)/sizeof(TCA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb93, &TCA_PERFCOUNTER1_SELECT1[0], sizeof(TCA_PERFCOUNTER1_SELECT1)/sizeof(TCA_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb94, &TCA_PERFCOUNTER2_SELECT[0], sizeof(TCA_PERFCOUNTER2_SELECT)/sizeof(TCA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb95, &TCA_PERFCOUNTER3_SELECT[0], sizeof(TCA_PERFCOUNTER3_SELECT)/sizeof(TCA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER0_SELECT", REG_MMIO, 0xdba0, &TCS_PERFCOUNTER0_SELECT[0], sizeof(TCS_PERFCOUNTER0_SELECT)/sizeof(TCS_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdba1, &TCS_PERFCOUNTER0_SELECT1[0], sizeof(TCS_PERFCOUNTER0_SELECT1)/sizeof(TCS_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER1_SELECT", REG_MMIO, 0xdba2, &TCS_PERFCOUNTER1_SELECT[0], sizeof(TCS_PERFCOUNTER1_SELECT)/sizeof(TCS_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER2_SELECT", REG_MMIO, 0xdba3, &TCS_PERFCOUNTER2_SELECT[0], sizeof(TCS_PERFCOUNTER2_SELECT)/sizeof(TCS_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER3_SELECT", REG_MMIO, 0xdba4, &TCS_PERFCOUNTER3_SELECT[0], sizeof(TCS_PERFCOUNTER3_SELECT)/sizeof(TCS_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER_FILTER", REG_MMIO, 0xdc00, &CB_PERFCOUNTER_FILTER[0], sizeof(CB_PERFCOUNTER_FILTER)/sizeof(CB_PERFCOUNTER_FILTER[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc01, &CB_PERFCOUNTER0_SELECT[0], sizeof(CB_PERFCOUNTER0_SELECT)/sizeof(CB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc02, &CB_PERFCOUNTER0_SELECT1[0], sizeof(CB_PERFCOUNTER0_SELECT1)/sizeof(CB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc03, &CB_PERFCOUNTER1_SELECT[0], sizeof(CB_PERFCOUNTER1_SELECT)/sizeof(CB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc04, &CB_PERFCOUNTER2_SELECT[0], sizeof(CB_PERFCOUNTER2_SELECT)/sizeof(CB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc05, &CB_PERFCOUNTER3_SELECT[0], sizeof(CB_PERFCOUNTER3_SELECT)/sizeof(CB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc40, &DB_PERFCOUNTER0_SELECT[0], sizeof(DB_PERFCOUNTER0_SELECT)/sizeof(DB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc41, &DB_PERFCOUNTER0_SELECT1[0], sizeof(DB_PERFCOUNTER0_SELECT1)/sizeof(DB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc42, &DB_PERFCOUNTER1_SELECT[0], sizeof(DB_PERFCOUNTER1_SELECT)/sizeof(DB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdc43, &DB_PERFCOUNTER1_SELECT1[0], sizeof(DB_PERFCOUNTER1_SELECT1)/sizeof(DB_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc44, &DB_PERFCOUNTER2_SELECT[0], sizeof(DB_PERFCOUNTER2_SELECT)/sizeof(DB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc46, &DB_PERFCOUNTER3_SELECT[0], sizeof(DB_PERFCOUNTER3_SELECT)/sizeof(DB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_CNTL", REG_MMIO, 0xdc80, &RLC_SPM_PERFMON_CNTL[0], sizeof(RLC_SPM_PERFMON_CNTL)/sizeof(RLC_SPM_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_BASE_LO", REG_MMIO, 0xdc81, &RLC_SPM_PERFMON_RING_BASE_LO[0], sizeof(RLC_SPM_PERFMON_RING_BASE_LO)/sizeof(RLC_SPM_PERFMON_RING_BASE_LO[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_BASE_HI", REG_MMIO, 0xdc82, &RLC_SPM_PERFMON_RING_BASE_HI[0], sizeof(RLC_SPM_PERFMON_RING_BASE_HI)/sizeof(RLC_SPM_PERFMON_RING_BASE_HI[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_SIZE", REG_MMIO, 0xdc83, &RLC_SPM_PERFMON_RING_SIZE[0], sizeof(RLC_SPM_PERFMON_RING_SIZE)/sizeof(RLC_SPM_PERFMON_RING_SIZE[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_SEGMENT_SIZE", REG_MMIO, 0xdc84, &RLC_SPM_PERFMON_SEGMENT_SIZE[0], sizeof(RLC_SPM_PERFMON_SEGMENT_SIZE)/sizeof(RLC_SPM_PERFMON_SEGMENT_SIZE[0]), 0, 0 },
+	{ "mmRLC_SPM_SE_MUXSEL_ADDR", REG_MMIO, 0xdc85, &RLC_SPM_SE_MUXSEL_ADDR[0], sizeof(RLC_SPM_SE_MUXSEL_ADDR)/sizeof(RLC_SPM_SE_MUXSEL_ADDR[0]), 0, 0 },
+	{ "mmRLC_SPM_SE_MUXSEL_DATA", REG_MMIO, 0xdc86, &RLC_SPM_SE_MUXSEL_DATA[0], sizeof(RLC_SPM_SE_MUXSEL_DATA)/sizeof(RLC_SPM_SE_MUXSEL_DATA[0]), 0, 0 },
+	{ "mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc87, &RLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_CPG_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc88, &RLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_CPC_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc89, &RLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_CPF_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8a, &RLC_SPM_CB_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_CB_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_CB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8b, &RLC_SPM_DB_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_DB_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_DB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8c, &RLC_SPM_PA_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_PA_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_PA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8d, &RLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_GDS_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8e, &RLC_SPM_IA_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_IA_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_IA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc90, &RLC_SPM_SC_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_SC_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_SC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc91, &RLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_TCC_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc92, &RLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_TCA_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc93, &RLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_TCP_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc94, &RLC_SPM_TA_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_TA_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_TA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc95, &RLC_SPM_TD_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_TD_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_TD_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc96, &RLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_VGT_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc97, &RLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_SPI_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc98, &RLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_SQG_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc99, &RLC_SPM_TCS_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_TCS_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_TCS_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc9a, &RLC_SPM_SX_PERFMON_SAMPLE_DELAY[0], sizeof(RLC_SPM_SX_PERFMON_SAMPLE_DELAY)/sizeof(RLC_SPM_SX_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_GLOBAL_MUXSEL_ADDR", REG_MMIO, 0xdc9b, &RLC_SPM_GLOBAL_MUXSEL_ADDR[0], sizeof(RLC_SPM_GLOBAL_MUXSEL_ADDR)/sizeof(RLC_SPM_GLOBAL_MUXSEL_ADDR[0]), 0, 0 },
+	{ "mmRLC_SPM_GLOBAL_MUXSEL_DATA", REG_MMIO, 0xdc9c, &RLC_SPM_GLOBAL_MUXSEL_DATA[0], sizeof(RLC_SPM_GLOBAL_MUXSEL_DATA)/sizeof(RLC_SPM_GLOBAL_MUXSEL_DATA[0]), 0, 0 },
+	{ "mmRLC_SPM_RING_RDPTR", REG_MMIO, 0xdc9d, &RLC_SPM_RING_RDPTR[0], sizeof(RLC_SPM_RING_RDPTR)/sizeof(RLC_SPM_RING_RDPTR[0]), 0, 0 },
+	{ "mmRLC_SPM_SEGMENT_THRESHOLD", REG_MMIO, 0xdc9e, &RLC_SPM_SEGMENT_THRESHOLD[0], sizeof(RLC_SPM_SEGMENT_THRESHOLD)/sizeof(RLC_SPM_SEGMENT_THRESHOLD[0]), 0, 0 },
+	{ "mmRLC_PERFMON_CNTL", REG_MMIO, 0xdcc0, &RLC_PERFMON_CNTL[0], sizeof(RLC_PERFMON_CNTL)/sizeof(RLC_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdcc1, &RLC_PERFCOUNTER0_SELECT[0], sizeof(RLC_PERFCOUNTER0_SELECT)/sizeof(RLC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdcc2, &RLC_PERFCOUNTER1_SELECT[0], sizeof(RLC_PERFCOUNTER1_SELECT)/sizeof(RLC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCGTS_SM_CTRL_REG", REG_MMIO, 0xf000, &CGTS_SM_CTRL_REG[0], sizeof(CGTS_SM_CTRL_REG)/sizeof(CGTS_SM_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_CTRL_REG", REG_MMIO, 0xf001, &CGTS_RD_CTRL_REG[0], sizeof(CGTS_RD_CTRL_REG)/sizeof(CGTS_RD_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_REG", REG_MMIO, 0xf002, &CGTS_RD_REG[0], sizeof(CGTS_RD_REG)/sizeof(CGTS_RD_REG[0]), 0, 0 },
+	{ "mmCGTS_TCC_DISABLE", REG_MMIO, 0xf003, &CGTS_TCC_DISABLE[0], sizeof(CGTS_TCC_DISABLE)/sizeof(CGTS_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_USER_TCC_DISABLE", REG_MMIO, 0xf004, &CGTS_USER_TCC_DISABLE[0], sizeof(CGTS_USER_TCC_DISABLE)/sizeof(CGTS_USER_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_CU0_SP0_CTRL_REG", REG_MMIO, 0xf008, &CGTS_CU0_SP0_CTRL_REG[0], sizeof(CGTS_CU0_SP0_CTRL_REG)/sizeof(CGTS_CU0_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_LDS_SQ_CTRL_REG", REG_MMIO, 0xf009, &CGTS_CU0_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU0_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU0_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_TA_SQC_CTRL_REG", REG_MMIO, 0xf00a, &CGTS_CU0_TA_SQC_CTRL_REG[0], sizeof(CGTS_CU0_TA_SQC_CTRL_REG)/sizeof(CGTS_CU0_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_SP1_CTRL_REG", REG_MMIO, 0xf00b, &CGTS_CU0_SP1_CTRL_REG[0], sizeof(CGTS_CU0_SP1_CTRL_REG)/sizeof(CGTS_CU0_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_TD_TCP_CTRL_REG", REG_MMIO, 0xf00c, &CGTS_CU0_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU0_TD_TCP_CTRL_REG)/sizeof(CGTS_CU0_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_SP0_CTRL_REG", REG_MMIO, 0xf00d, &CGTS_CU1_SP0_CTRL_REG[0], sizeof(CGTS_CU1_SP0_CTRL_REG)/sizeof(CGTS_CU1_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_LDS_SQ_CTRL_REG", REG_MMIO, 0xf00e, &CGTS_CU1_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU1_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU1_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_TA_CTRL_REG", REG_MMIO, 0xf00f, &CGTS_CU1_TA_CTRL_REG[0], sizeof(CGTS_CU1_TA_CTRL_REG)/sizeof(CGTS_CU1_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_SP1_CTRL_REG", REG_MMIO, 0xf010, &CGTS_CU1_SP1_CTRL_REG[0], sizeof(CGTS_CU1_SP1_CTRL_REG)/sizeof(CGTS_CU1_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_TD_TCP_CTRL_REG", REG_MMIO, 0xf011, &CGTS_CU1_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU1_TD_TCP_CTRL_REG)/sizeof(CGTS_CU1_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_SP0_CTRL_REG", REG_MMIO, 0xf012, &CGTS_CU2_SP0_CTRL_REG[0], sizeof(CGTS_CU2_SP0_CTRL_REG)/sizeof(CGTS_CU2_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_LDS_SQ_CTRL_REG", REG_MMIO, 0xf013, &CGTS_CU2_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU2_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU2_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_TA_CTRL_REG", REG_MMIO, 0xf014, &CGTS_CU2_TA_CTRL_REG[0], sizeof(CGTS_CU2_TA_CTRL_REG)/sizeof(CGTS_CU2_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_SP1_CTRL_REG", REG_MMIO, 0xf015, &CGTS_CU2_SP1_CTRL_REG[0], sizeof(CGTS_CU2_SP1_CTRL_REG)/sizeof(CGTS_CU2_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_TD_TCP_CTRL_REG", REG_MMIO, 0xf016, &CGTS_CU2_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU2_TD_TCP_CTRL_REG)/sizeof(CGTS_CU2_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_SP0_CTRL_REG", REG_MMIO, 0xf017, &CGTS_CU3_SP0_CTRL_REG[0], sizeof(CGTS_CU3_SP0_CTRL_REG)/sizeof(CGTS_CU3_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_LDS_SQ_CTRL_REG", REG_MMIO, 0xf018, &CGTS_CU3_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU3_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU3_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_TA_CTRL_REG", REG_MMIO, 0xf019, &CGTS_CU3_TA_CTRL_REG[0], sizeof(CGTS_CU3_TA_CTRL_REG)/sizeof(CGTS_CU3_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_SP1_CTRL_REG", REG_MMIO, 0xf01a, &CGTS_CU3_SP1_CTRL_REG[0], sizeof(CGTS_CU3_SP1_CTRL_REG)/sizeof(CGTS_CU3_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_TD_TCP_CTRL_REG", REG_MMIO, 0xf01b, &CGTS_CU3_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU3_TD_TCP_CTRL_REG)/sizeof(CGTS_CU3_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_SP0_CTRL_REG", REG_MMIO, 0xf01c, &CGTS_CU4_SP0_CTRL_REG[0], sizeof(CGTS_CU4_SP0_CTRL_REG)/sizeof(CGTS_CU4_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_LDS_SQ_CTRL_REG", REG_MMIO, 0xf01d, &CGTS_CU4_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU4_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU4_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_TA_SQC_CTRL_REG", REG_MMIO, 0xf01e, &CGTS_CU4_TA_SQC_CTRL_REG[0], sizeof(CGTS_CU4_TA_SQC_CTRL_REG)/sizeof(CGTS_CU4_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_SP1_CTRL_REG", REG_MMIO, 0xf01f, &CGTS_CU4_SP1_CTRL_REG[0], sizeof(CGTS_CU4_SP1_CTRL_REG)/sizeof(CGTS_CU4_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_TD_TCP_CTRL_REG", REG_MMIO, 0xf020, &CGTS_CU4_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU4_TD_TCP_CTRL_REG)/sizeof(CGTS_CU4_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_SP0_CTRL_REG", REG_MMIO, 0xf021, &CGTS_CU5_SP0_CTRL_REG[0], sizeof(CGTS_CU5_SP0_CTRL_REG)/sizeof(CGTS_CU5_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_LDS_SQ_CTRL_REG", REG_MMIO, 0xf022, &CGTS_CU5_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU5_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU5_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_TA_CTRL_REG", REG_MMIO, 0xf023, &CGTS_CU5_TA_CTRL_REG[0], sizeof(CGTS_CU5_TA_CTRL_REG)/sizeof(CGTS_CU5_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_SP1_CTRL_REG", REG_MMIO, 0xf024, &CGTS_CU5_SP1_CTRL_REG[0], sizeof(CGTS_CU5_SP1_CTRL_REG)/sizeof(CGTS_CU5_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_TD_TCP_CTRL_REG", REG_MMIO, 0xf025, &CGTS_CU5_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU5_TD_TCP_CTRL_REG)/sizeof(CGTS_CU5_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_SP0_CTRL_REG", REG_MMIO, 0xf026, &CGTS_CU6_SP0_CTRL_REG[0], sizeof(CGTS_CU6_SP0_CTRL_REG)/sizeof(CGTS_CU6_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_LDS_SQ_CTRL_REG", REG_MMIO, 0xf027, &CGTS_CU6_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU6_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU6_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_TA_CTRL_REG", REG_MMIO, 0xf028, &CGTS_CU6_TA_CTRL_REG[0], sizeof(CGTS_CU6_TA_CTRL_REG)/sizeof(CGTS_CU6_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_SP1_CTRL_REG", REG_MMIO, 0xf029, &CGTS_CU6_SP1_CTRL_REG[0], sizeof(CGTS_CU6_SP1_CTRL_REG)/sizeof(CGTS_CU6_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_TD_TCP_CTRL_REG", REG_MMIO, 0xf02a, &CGTS_CU6_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU6_TD_TCP_CTRL_REG)/sizeof(CGTS_CU6_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_SP0_CTRL_REG", REG_MMIO, 0xf02b, &CGTS_CU7_SP0_CTRL_REG[0], sizeof(CGTS_CU7_SP0_CTRL_REG)/sizeof(CGTS_CU7_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_LDS_SQ_CTRL_REG", REG_MMIO, 0xf02c, &CGTS_CU7_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU7_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU7_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_TA_CTRL_REG", REG_MMIO, 0xf02d, &CGTS_CU7_TA_CTRL_REG[0], sizeof(CGTS_CU7_TA_CTRL_REG)/sizeof(CGTS_CU7_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_SP1_CTRL_REG", REG_MMIO, 0xf02e, &CGTS_CU7_SP1_CTRL_REG[0], sizeof(CGTS_CU7_SP1_CTRL_REG)/sizeof(CGTS_CU7_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_TD_TCP_CTRL_REG", REG_MMIO, 0xf02f, &CGTS_CU7_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU7_TD_TCP_CTRL_REG)/sizeof(CGTS_CU7_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_SP0_CTRL_REG", REG_MMIO, 0xf030, &CGTS_CU8_SP0_CTRL_REG[0], sizeof(CGTS_CU8_SP0_CTRL_REG)/sizeof(CGTS_CU8_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_LDS_SQ_CTRL_REG", REG_MMIO, 0xf031, &CGTS_CU8_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU8_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU8_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_TA_SQC_CTRL_REG", REG_MMIO, 0xf032, &CGTS_CU8_TA_SQC_CTRL_REG[0], sizeof(CGTS_CU8_TA_SQC_CTRL_REG)/sizeof(CGTS_CU8_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_SP1_CTRL_REG", REG_MMIO, 0xf033, &CGTS_CU8_SP1_CTRL_REG[0], sizeof(CGTS_CU8_SP1_CTRL_REG)/sizeof(CGTS_CU8_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_TD_TCP_CTRL_REG", REG_MMIO, 0xf034, &CGTS_CU8_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU8_TD_TCP_CTRL_REG)/sizeof(CGTS_CU8_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_SP0_CTRL_REG", REG_MMIO, 0xf035, &CGTS_CU9_SP0_CTRL_REG[0], sizeof(CGTS_CU9_SP0_CTRL_REG)/sizeof(CGTS_CU9_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_LDS_SQ_CTRL_REG", REG_MMIO, 0xf036, &CGTS_CU9_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU9_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU9_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_TA_CTRL_REG", REG_MMIO, 0xf037, &CGTS_CU9_TA_CTRL_REG[0], sizeof(CGTS_CU9_TA_CTRL_REG)/sizeof(CGTS_CU9_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_SP1_CTRL_REG", REG_MMIO, 0xf038, &CGTS_CU9_SP1_CTRL_REG[0], sizeof(CGTS_CU9_SP1_CTRL_REG)/sizeof(CGTS_CU9_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_TD_TCP_CTRL_REG", REG_MMIO, 0xf039, &CGTS_CU9_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU9_TD_TCP_CTRL_REG)/sizeof(CGTS_CU9_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_SP0_CTRL_REG", REG_MMIO, 0xf03a, &CGTS_CU10_SP0_CTRL_REG[0], sizeof(CGTS_CU10_SP0_CTRL_REG)/sizeof(CGTS_CU10_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_LDS_SQ_CTRL_REG", REG_MMIO, 0xf03b, &CGTS_CU10_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU10_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU10_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_TA_CTRL_REG", REG_MMIO, 0xf03c, &CGTS_CU10_TA_CTRL_REG[0], sizeof(CGTS_CU10_TA_CTRL_REG)/sizeof(CGTS_CU10_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_SP1_CTRL_REG", REG_MMIO, 0xf03d, &CGTS_CU10_SP1_CTRL_REG[0], sizeof(CGTS_CU10_SP1_CTRL_REG)/sizeof(CGTS_CU10_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_TD_TCP_CTRL_REG", REG_MMIO, 0xf03e, &CGTS_CU10_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU10_TD_TCP_CTRL_REG)/sizeof(CGTS_CU10_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_SP0_CTRL_REG", REG_MMIO, 0xf03f, &CGTS_CU11_SP0_CTRL_REG[0], sizeof(CGTS_CU11_SP0_CTRL_REG)/sizeof(CGTS_CU11_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_LDS_SQ_CTRL_REG", REG_MMIO, 0xf040, &CGTS_CU11_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU11_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU11_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_TA_CTRL_REG", REG_MMIO, 0xf041, &CGTS_CU11_TA_CTRL_REG[0], sizeof(CGTS_CU11_TA_CTRL_REG)/sizeof(CGTS_CU11_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_SP1_CTRL_REG", REG_MMIO, 0xf042, &CGTS_CU11_SP1_CTRL_REG[0], sizeof(CGTS_CU11_SP1_CTRL_REG)/sizeof(CGTS_CU11_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_TD_TCP_CTRL_REG", REG_MMIO, 0xf043, &CGTS_CU11_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU11_TD_TCP_CTRL_REG)/sizeof(CGTS_CU11_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_SP0_CTRL_REG", REG_MMIO, 0xf044, &CGTS_CU12_SP0_CTRL_REG[0], sizeof(CGTS_CU12_SP0_CTRL_REG)/sizeof(CGTS_CU12_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_LDS_SQ_CTRL_REG", REG_MMIO, 0xf045, &CGTS_CU12_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU12_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU12_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_TA_SQC_CTRL_REG", REG_MMIO, 0xf046, &CGTS_CU12_TA_SQC_CTRL_REG[0], sizeof(CGTS_CU12_TA_SQC_CTRL_REG)/sizeof(CGTS_CU12_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_SP1_CTRL_REG", REG_MMIO, 0xf047, &CGTS_CU12_SP1_CTRL_REG[0], sizeof(CGTS_CU12_SP1_CTRL_REG)/sizeof(CGTS_CU12_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_TD_TCP_CTRL_REG", REG_MMIO, 0xf048, &CGTS_CU12_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU12_TD_TCP_CTRL_REG)/sizeof(CGTS_CU12_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_SP0_CTRL_REG", REG_MMIO, 0xf049, &CGTS_CU13_SP0_CTRL_REG[0], sizeof(CGTS_CU13_SP0_CTRL_REG)/sizeof(CGTS_CU13_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04a, &CGTS_CU13_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU13_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU13_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_TA_CTRL_REG", REG_MMIO, 0xf04b, &CGTS_CU13_TA_CTRL_REG[0], sizeof(CGTS_CU13_TA_CTRL_REG)/sizeof(CGTS_CU13_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_SP1_CTRL_REG", REG_MMIO, 0xf04c, &CGTS_CU13_SP1_CTRL_REG[0], sizeof(CGTS_CU13_SP1_CTRL_REG)/sizeof(CGTS_CU13_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_TD_TCP_CTRL_REG", REG_MMIO, 0xf04d, &CGTS_CU13_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU13_TD_TCP_CTRL_REG)/sizeof(CGTS_CU13_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_SP0_CTRL_REG", REG_MMIO, 0xf04e, &CGTS_CU14_SP0_CTRL_REG[0], sizeof(CGTS_CU14_SP0_CTRL_REG)/sizeof(CGTS_CU14_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04f, &CGTS_CU14_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU14_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU14_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_TA_CTRL_REG", REG_MMIO, 0xf050, &CGTS_CU14_TA_CTRL_REG[0], sizeof(CGTS_CU14_TA_CTRL_REG)/sizeof(CGTS_CU14_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_SP1_CTRL_REG", REG_MMIO, 0xf051, &CGTS_CU14_SP1_CTRL_REG[0], sizeof(CGTS_CU14_SP1_CTRL_REG)/sizeof(CGTS_CU14_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_TD_TCP_CTRL_REG", REG_MMIO, 0xf052, &CGTS_CU14_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU14_TD_TCP_CTRL_REG)/sizeof(CGTS_CU14_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_SP0_CTRL_REG", REG_MMIO, 0xf053, &CGTS_CU15_SP0_CTRL_REG[0], sizeof(CGTS_CU15_SP0_CTRL_REG)/sizeof(CGTS_CU15_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_LDS_SQ_CTRL_REG", REG_MMIO, 0xf054, &CGTS_CU15_LDS_SQ_CTRL_REG[0], sizeof(CGTS_CU15_LDS_SQ_CTRL_REG)/sizeof(CGTS_CU15_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_TA_CTRL_REG", REG_MMIO, 0xf055, &CGTS_CU15_TA_CTRL_REG[0], sizeof(CGTS_CU15_TA_CTRL_REG)/sizeof(CGTS_CU15_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_SP1_CTRL_REG", REG_MMIO, 0xf056, &CGTS_CU15_SP1_CTRL_REG[0], sizeof(CGTS_CU15_SP1_CTRL_REG)/sizeof(CGTS_CU15_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_TD_TCP_CTRL_REG", REG_MMIO, 0xf057, &CGTS_CU15_TD_TCP_CTRL_REG[0], sizeof(CGTS_CU15_TD_TCP_CTRL_REG)/sizeof(CGTS_CU15_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTT_SPI_CLK_CTRL", REG_MMIO, 0xf080, &CGTT_SPI_CLK_CTRL[0], sizeof(CGTT_SPI_CLK_CTRL)/sizeof(CGTT_SPI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_PC_CLK_CTRL", REG_MMIO, 0xf081, &CGTT_PC_CLK_CTRL[0], sizeof(CGTT_PC_CLK_CTRL)/sizeof(CGTT_PC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_BCI_CLK_CTRL", REG_MMIO, 0xf082, &CGTT_BCI_CLK_CTRL[0], sizeof(CGTT_BCI_CLK_CTRL)/sizeof(CGTT_BCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_VGT_CLK_CTRL", REG_MMIO, 0xf084, &CGTT_VGT_CLK_CTRL[0], sizeof(CGTT_VGT_CLK_CTRL)/sizeof(CGTT_VGT_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_IA_CLK_CTRL", REG_MMIO, 0xf085, &CGTT_IA_CLK_CTRL[0], sizeof(CGTT_IA_CLK_CTRL)/sizeof(CGTT_IA_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_WD_CLK_CTRL", REG_MMIO, 0xf086, &CGTT_WD_CLK_CTRL[0], sizeof(CGTT_WD_CLK_CTRL)/sizeof(CGTT_WD_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_PA_CLK_CTRL", REG_MMIO, 0xf088, &CGTT_PA_CLK_CTRL[0], sizeof(CGTT_PA_CLK_CTRL)/sizeof(CGTT_PA_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SC_CLK_CTRL", REG_MMIO, 0xf089, &CGTT_SC_CLK_CTRL[0], sizeof(CGTT_SC_CLK_CTRL)/sizeof(CGTT_SC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQ_CLK_CTRL", REG_MMIO, 0xf08c, &CGTT_SQ_CLK_CTRL[0], sizeof(CGTT_SQ_CLK_CTRL)/sizeof(CGTT_SQ_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQG_CLK_CTRL", REG_MMIO, 0xf08d, &CGTT_SQG_CLK_CTRL[0], sizeof(CGTT_SQG_CLK_CTRL)/sizeof(CGTT_SQG_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_ALU_CLK_CTRL", REG_MMIO, 0xf08e, &SQ_ALU_CLK_CTRL[0], sizeof(SQ_ALU_CLK_CTRL)/sizeof(SQ_ALU_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_TEX_CLK_CTRL", REG_MMIO, 0xf08f, &SQ_TEX_CLK_CTRL[0], sizeof(SQ_TEX_CLK_CTRL)/sizeof(SQ_TEX_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_LDS_CLK_CTRL", REG_MMIO, 0xf090, &SQ_LDS_CLK_CTRL[0], sizeof(SQ_LDS_CLK_CTRL)/sizeof(SQ_LDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE", REG_MMIO, 0xf091, &SQ_POWER_THROTTLE[0], sizeof(SQ_POWER_THROTTLE)/sizeof(SQ_POWER_THROTTLE[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE2", REG_MMIO, 0xf092, &SQ_POWER_THROTTLE2[0], sizeof(SQ_POWER_THROTTLE2)/sizeof(SQ_POWER_THROTTLE2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL0", REG_MMIO, 0xf094, &CGTT_SX_CLK_CTRL0[0], sizeof(CGTT_SX_CLK_CTRL0)/sizeof(CGTT_SX_CLK_CTRL0[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL1", REG_MMIO, 0xf095, &CGTT_SX_CLK_CTRL1[0], sizeof(CGTT_SX_CLK_CTRL1)/sizeof(CGTT_SX_CLK_CTRL1[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL2", REG_MMIO, 0xf096, &CGTT_SX_CLK_CTRL2[0], sizeof(CGTT_SX_CLK_CTRL2)/sizeof(CGTT_SX_CLK_CTRL2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL3", REG_MMIO, 0xf097, &CGTT_SX_CLK_CTRL3[0], sizeof(CGTT_SX_CLK_CTRL3)/sizeof(CGTT_SX_CLK_CTRL3[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL4", REG_MMIO, 0xf098, &CGTT_SX_CLK_CTRL4[0], sizeof(CGTT_SX_CLK_CTRL4)/sizeof(CGTT_SX_CLK_CTRL4[0]), 0, 0 },
+	{ "mmTD_CGTT_CTRL", REG_MMIO, 0xf09c, &TD_CGTT_CTRL[0], sizeof(TD_CGTT_CTRL)/sizeof(TD_CGTT_CTRL[0]), 0, 0 },
+	{ "mmTA_CGTT_CTRL", REG_MMIO, 0xf09d, &TA_CGTT_CTRL[0], sizeof(TA_CGTT_CTRL)/sizeof(TA_CGTT_CTRL[0]), 0, 0 },
+	{ "mmCGTT_TCP_CLK_CTRL", REG_MMIO, 0xf09e, &CGTT_TCP_CLK_CTRL[0], sizeof(CGTT_TCP_CLK_CTRL)/sizeof(CGTT_TCP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_TCI_CLK_CTRL", REG_MMIO, 0xf09f, &CGTT_TCI_CLK_CTRL[0], sizeof(CGTT_TCI_CLK_CTRL)/sizeof(CGTT_TCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_GDS_CLK_CTRL", REG_MMIO, 0xf0a0, &CGTT_GDS_CLK_CTRL[0], sizeof(CGTT_GDS_CLK_CTRL)/sizeof(CGTT_GDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmDB_CGTT_CLK_CTRL_0", REG_MMIO, 0xf0a4, &DB_CGTT_CLK_CTRL_0[0], sizeof(DB_CGTT_CLK_CTRL_0)/sizeof(DB_CGTT_CLK_CTRL_0[0]), 0, 0 },
+	{ "mmCB_CGTT_SCLK_CTRL", REG_MMIO, 0xf0a8, &CB_CGTT_SCLK_CTRL[0], sizeof(CB_CGTT_SCLK_CTRL)/sizeof(CB_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCC_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ac, &TCC_CGTT_SCLK_CTRL[0], sizeof(TCC_CGTT_SCLK_CTRL)/sizeof(TCC_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCA_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ad, &TCA_CGTT_SCLK_CTRL[0], sizeof(TCA_CGTT_SCLK_CTRL)/sizeof(TCA_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCS_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ae, &TCS_CGTT_SCLK_CTRL[0], sizeof(TCS_CGTT_SCLK_CTRL)/sizeof(TCS_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CP_CLK_CTRL", REG_MMIO, 0xf0b0, &CGTT_CP_CLK_CTRL[0], sizeof(CGTT_CP_CLK_CTRL)/sizeof(CGTT_CP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CPF_CLK_CTRL", REG_MMIO, 0xf0b1, &CGTT_CPF_CLK_CTRL[0], sizeof(CGTT_CPF_CLK_CTRL)/sizeof(CGTT_CPF_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CPC_CLK_CTRL", REG_MMIO, 0xf0b2, &CGTT_CPC_CLK_CTRL[0], sizeof(CGTT_CPC_CLK_CTRL)/sizeof(CGTT_CPC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_RLC_CLK_CTRL", REG_MMIO, 0xf0b8, &CGTT_RLC_CLK_CTRL[0], sizeof(CGTT_RLC_CLK_CTRL)/sizeof(CGTT_RLC_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_HV_VMID_CTRL", REG_MMIO, 0xf840, &SQ_HV_VMID_CTRL[0], sizeof(SQ_HV_VMID_CTRL)/sizeof(SQ_HV_VMID_CTRL[0]), 0, 0 },
+	{ "mmGFX_PIPE_PRIORITY", REG_MMIO, 0xf87f, &GFX_PIPE_PRIORITY[0], sizeof(GFX_PIPE_PRIORITY)/sizeof(GFX_PIPE_PRIORITY[0]), 0, 0 },
diff --git a/src/lib/ip/gfx72.c b/src/lib/ip/gfx72.c
new file mode 100644
index 0000000..cd04f8d
--- /dev/null
+++ b/src/lib/ip/gfx72.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gfx72_bits.i"
+
+static const struct umr_reg gfx72_registers[] = {
+#include "gfx72_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_gfx72(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gfx72";
+	ip->no_regs = sizeof(gfx72_registers)/sizeof(gfx72_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gfx72_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 1) ? grant : deny;
+	memcpy(ip->regs, gfx72_registers, sizeof(gfx72_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gfx72_bits.i b/src/lib/ip/gfx72_bits.i
new file mode 100644
index 0000000..dde5724
--- /dev/null
+++ b/src/lib/ip/gfx72_bits.i
@@ -0,0 +1,13686 @@
+static struct umr_bitfield ixCLIPPER_DEBUG_REG00[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 8, 8, &umr_bitfield_default },
+	 { "su_clip_baryc_free", 9, 10, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 11, 11, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_full", 12, 12, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_empty", 13, 13, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_full", 14, 14, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_full", 16, 16, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_empty", 17, 17, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_full", 18, 18, &umr_bitfield_default },
+	 { "vgt_to_clips_fifo_empty", 19, 19, &umr_bitfield_default },
+	 { "vgt_to_clips_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "clipcode_fifo_fifo_empty", 21, 21, &umr_bitfield_default },
+	 { "clipcode_fifo_full", 22, 22, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_empty", 23, 23, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_write", 30, 30, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPA_SC_DEBUG_REG0[] = {
+	 { "REG0_FIELD0", 0, 1, &umr_bitfield_default },
+	 { "REG0_FIELD1", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_CONNECT[] = {
+	 { "DOORBELL_OFFSET", 0, 20, &umr_bitfield_default },
+	 { "QUEUE_ID", 21, 23, &umr_bitfield_default },
+	 { "VMID", 26, 29, &umr_bitfield_default },
+	 { "UNORD_DISP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG0[] = {
+	 { "wd_busy_extended", 0, 0, &umr_bitfield_default },
+	 { "wd_nodma_busy_extended", 1, 1, &umr_bitfield_default },
+	 { "wd_busy", 2, 2, &umr_bitfield_default },
+	 { "wd_nodma_busy", 3, 3, &umr_bitfield_default },
+	 { "rbiu_busy", 4, 4, &umr_bitfield_default },
+	 { "spl_dma_busy", 5, 5, &umr_bitfield_default },
+	 { "spl_di_busy", 6, 6, &umr_bitfield_default },
+	 { "vgt0_active_q", 7, 7, &umr_bitfield_default },
+	 { "vgt1_active_q", 8, 8, &umr_bitfield_default },
+	 { "spl_dma_p1_busy", 9, 9, &umr_bitfield_default },
+	 { "rbiu_dr_p1_fifo_busy", 10, 10, &umr_bitfield_default },
+	 { "rbiu_di_p1_fifo_busy", 11, 11, &umr_bitfield_default },
+	 { "SPARE2", 12, 12, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_busy", 13, 13, &umr_bitfield_default },
+	 { "rbiu_spl_dr_valid", 14, 14, &umr_bitfield_default },
+	 { "spl_rbiu_dr_read", 15, 15, &umr_bitfield_default },
+	 { "SPARE3", 16, 16, &umr_bitfield_default },
+	 { "rbiu_di_fifo_busy", 17, 17, &umr_bitfield_default },
+	 { "rbiu_spl_di_valid", 18, 18, &umr_bitfield_default },
+	 { "spl_rbiu_di_read", 19, 19, &umr_bitfield_default },
+	 { "se0_synced_q", 20, 20, &umr_bitfield_default },
+	 { "se1_synced_q", 21, 21, &umr_bitfield_default },
+	 { "se2_synced_q", 22, 22, &umr_bitfield_default },
+	 { "se3_synced_q", 23, 23, &umr_bitfield_default },
+	 { "reg_clk_busy", 24, 24, &umr_bitfield_default },
+	 { "input_clk_busy", 25, 25, &umr_bitfield_default },
+	 { "core_clk_busy", 26, 26, &umr_bitfield_default },
+	 { "vgt2_active_q", 27, 27, &umr_bitfield_default },
+	 { "sclk_reg_vld", 28, 28, &umr_bitfield_default },
+	 { "sclk_input_vld", 29, 29, &umr_bitfield_default },
+	 { "sclk_core_vld", 30, 30, &umr_bitfield_default },
+	 { "vgt3_active_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG01[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_extra_bc_valid", 8, 10, &umr_bitfield_default },
+	 { "clip_vert_vte_valid", 11, 13, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_deallocate", 14, 16, &umr_bitfield_default },
+	 { "clip_to_outsm_deallocate_slot", 17, 19, &umr_bitfield_default },
+	 { "clip_to_outsm_null_primitive", 20, 20, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_2", 21, 21, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_1", 22, 22, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_0", 23, 23, &umr_bitfield_default },
+	 { "vte_out_clip_rd_extra_bc_valid", 24, 24, &umr_bitfield_default },
+	 { "vte_out_clip_rd_vte_naninf_kill", 25, 25, &umr_bitfield_default },
+	 { "vte_out_clip_rd_vertex_store_indx", 26, 27, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 28, 28, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_empty", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPA_SC_DEBUG_REG1[] = {
+	 { "REG1_FIELD0", 0, 1, &umr_bitfield_default },
+	 { "REG1_FIELD1", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG1[] = {
+	 { "tag_hit", 0, 0, &umr_bitfield_default },
+	 { "tag_miss", 1, 1, &umr_bitfield_default },
+	 { "pixel_addr", 2, 16, &umr_bitfield_default },
+	 { "pixel_vld", 17, 17, &umr_bitfield_default },
+	 { "data_ready", 18, 18, &umr_bitfield_default },
+	 { "awaiting_data", 19, 19, &umr_bitfield_default },
+	 { "addr_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "addr_fifo_empty", 21, 21, &umr_bitfield_default },
+	 { "buffer_loaded", 22, 22, &umr_bitfield_default },
+	 { "buffer_invalid", 23, 23, &umr_bitfield_default },
+	 { "spare", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG1[] = {
+	 { "grbm_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "grbm_fifo_full", 1, 1, &umr_bitfield_default },
+	 { "grbm_fifo_we", 2, 2, &umr_bitfield_default },
+	 { "grbm_fifo_re", 3, 3, &umr_bitfield_default },
+	 { "draw_initiator_valid_q", 4, 4, &umr_bitfield_default },
+	 { "event_initiator_valid_q", 5, 5, &umr_bitfield_default },
+	 { "event_addr_valid_q", 6, 6, &umr_bitfield_default },
+	 { "dma_request_valid_q", 7, 7, &umr_bitfield_default },
+	 { "SPARE0", 8, 8, &umr_bitfield_default },
+	 { "min_indx_valid_q", 9, 9, &umr_bitfield_default },
+	 { "max_indx_valid_q", 10, 10, &umr_bitfield_default },
+	 { "indx_offset_valid_q", 11, 11, &umr_bitfield_default },
+	 { "grbm_fifo_rdata_reg_id", 12, 16, &umr_bitfield_default },
+	 { "grbm_fifo_rdata_state", 17, 19, &umr_bitfield_default },
+	 { "free_cnt_q", 20, 25, &umr_bitfield_default },
+	 { "rbiu_di_fifo_we", 26, 26, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_we", 27, 27, &umr_bitfield_default },
+	 { "rbiu_di_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "rbiu_di_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG16[] = {
+	 { "sm0_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm0_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm0_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm0_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm0_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm0_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm0_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm0_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm0_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm0_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm0_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG16[] = {
+	 { "gog_busy", 0, 0, &umr_bitfield_default },
+	 { "gog_state_q", 1, 3, &umr_bitfield_default },
+	 { "r0_rtr", 4, 4, &umr_bitfield_default },
+	 { "r1_rtr", 5, 5, &umr_bitfield_default },
+	 { "r1_upstream_rtr", 6, 6, &umr_bitfield_default },
+	 { "r2_vs_tbl_rtr", 7, 7, &umr_bitfield_default },
+	 { "r2_prim_rtr", 8, 8, &umr_bitfield_default },
+	 { "r2_indx_rtr", 9, 9, &umr_bitfield_default },
+	 { "r2_rtr", 10, 10, &umr_bitfield_default },
+	 { "gog_tm_vs_event_rtr", 11, 11, &umr_bitfield_default },
+	 { "r3_force_vs_tbl_we_rtr", 12, 12, &umr_bitfield_default },
+	 { "indx_valid_r2_q", 13, 13, &umr_bitfield_default },
+	 { "prim_valid_r2_q", 14, 14, &umr_bitfield_default },
+	 { "valid_r2_q", 15, 15, &umr_bitfield_default },
+	 { "prim_valid_r1_q", 16, 16, &umr_bitfield_default },
+	 { "indx_valid_r1_q", 17, 17, &umr_bitfield_default },
+	 { "valid_r1_q", 18, 18, &umr_bitfield_default },
+	 { "indx_valid_r0_q", 19, 19, &umr_bitfield_default },
+	 { "prim_valid_r0_q", 20, 20, &umr_bitfield_default },
+	 { "valid_r0_q", 21, 21, &umr_bitfield_default },
+	 { "send_event_q", 22, 22, &umr_bitfield_default },
+	 { "SPARE24", 23, 23, &umr_bitfield_default },
+	 { "vert_seen_since_sopg_r2_q", 24, 24, &umr_bitfield_default },
+	 { "gog_out_prim_state_sel", 25, 27, &umr_bitfield_default },
+	 { "multiple_streams_en_r1_q", 28, 28, &umr_bitfield_default },
+	 { "vs_vert_count_r2_q_not_0", 29, 29, &umr_bitfield_default },
+	 { "num_gs_r2_q_not_0", 30, 30, &umr_bitfield_default },
+	 { "new_vs_thread_r2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG17[] = {
+	 { "sm1_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm1_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm1_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm1_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm1_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm1_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm1_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm1_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm1_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm1_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm1_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG17[] = {
+	 { "gog_out_prim_rel_indx2_5_0", 0, 5, &umr_bitfield_default },
+	 { "gog_out_prim_rel_indx1_5_0", 6, 11, &umr_bitfield_default },
+	 { "gog_out_prim_rel_indx0_5_0", 12, 17, &umr_bitfield_default },
+	 { "gog_out_indx_13_0", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_MODE[] = {
+	 { "FP_ROUND", 0, 3, &umr_bitfield_default },
+	 { "FP_DENORM", 4, 7, &umr_bitfield_default },
+	 { "DX10_CLAMP", 8, 8, &umr_bitfield_default },
+	 { "IEEE", 9, 9, &umr_bitfield_default },
+	 { "LOD_CLAMPED", 10, 10, &umr_bitfield_default },
+	 { "DEBUG_EN", 11, 11, &umr_bitfield_default },
+	 { "EXCP_EN", 12, 20, &umr_bitfield_default },
+	 { "VSKIP", 28, 28, &umr_bitfield_default },
+	 { "CSP", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG18[] = {
+	 { "sm2_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm2_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm2_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm2_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm2_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm2_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm2_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm2_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm2_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm2_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm2_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_STATUS[] = {
+	 { "SCC", 0, 0, &umr_bitfield_default },
+	 { "SPI_PRIO", 1, 2, &umr_bitfield_default },
+	 { "WAVE_PRIO", 3, 4, &umr_bitfield_default },
+	 { "PRIV", 5, 5, &umr_bitfield_default },
+	 { "TRAP_EN", 6, 6, &umr_bitfield_default },
+	 { "TTRACE_EN", 7, 7, &umr_bitfield_default },
+	 { "EXPORT_RDY", 8, 8, &umr_bitfield_default },
+	 { "EXECZ", 9, 9, &umr_bitfield_default },
+	 { "VCCZ", 10, 10, &umr_bitfield_default },
+	 { "IN_TG", 11, 11, &umr_bitfield_default },
+	 { "IN_BARRIER", 12, 12, &umr_bitfield_default },
+	 { "HALT", 13, 13, &umr_bitfield_default },
+	 { "TRAP", 14, 14, &umr_bitfield_default },
+	 { "TTRACE_CU_EN", 15, 15, &umr_bitfield_default },
+	 { "VALID", 16, 16, &umr_bitfield_default },
+	 { "ECC_ERR", 17, 17, &umr_bitfield_default },
+	 { "SKIP_EXPORT", 18, 18, &umr_bitfield_default },
+	 { "PERF_EN", 19, 19, &umr_bitfield_default },
+	 { "COND_DBG_USER", 20, 20, &umr_bitfield_default },
+	 { "COND_DBG_SYS", 21, 21, &umr_bitfield_default },
+	 { "DATA_ATC", 22, 22, &umr_bitfield_default },
+	 { "INST_ATC", 23, 23, &umr_bitfield_default },
+	 { "DISPATCH_CACHE_CTRL", 24, 26, &umr_bitfield_default },
+	 { "MUST_EXPORT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG19[] = {
+	 { "sm3_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm3_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm3_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm3_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm3_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm3_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm3_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm3_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm3_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm3_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm3_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TRAPSTS[] = {
+	 { "EXCP", 0, 8, &umr_bitfield_default },
+	 { "EXCP_CYCLE", 16, 21, &umr_bitfield_default },
+	 { "DP_RATE", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG0[] = {
+	 { "position_address", 0, 5, &umr_bitfield_default },
+	 { "point_address", 6, 8, &umr_bitfield_default },
+	 { "sx_pending_rd_state_var_indx", 9, 11, &umr_bitfield_default },
+	 { "sx_pending_rd_req_mask", 12, 15, &umr_bitfield_default },
+	 { "sx_pending_rd_pci", 16, 25, &umr_bitfield_default },
+	 { "sx_pending_rd_aux_sel", 26, 27, &umr_bitfield_default },
+	 { "sx_pending_rd_sp_id", 28, 29, &umr_bitfield_default },
+	 { "sx_pending_rd_aux_inc", 30, 30, &umr_bitfield_default },
+	 { "sx_pending_rd_advance", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG20[] = {
+	 { "dbg_VGT_SPI_vsthread_sovertexindex", 0, 15, &umr_bitfield_default },
+	 { "dbg_VGT_SPI_vsthread_sovertexcount_not_0", 16, 16, &umr_bitfield_default },
+	 { "SPARE17", 17, 17, &umr_bitfield_default },
+	 { "alloc_counter_q", 18, 21, &umr_bitfield_default },
+	 { "curr_dealloc_distance_q", 22, 28, &umr_bitfield_default },
+	 { "new_allocate_q", 29, 29, &umr_bitfield_default },
+	 { "curr_slot_in_vtx_vect_q_not_0", 30, 30, &umr_bitfield_default },
+	 { "int_vtx_counter_q_not_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_HW_ID[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "PIPE_ID", 6, 7, &umr_bitfield_default },
+	 { "CU_ID", 8, 11, &umr_bitfield_default },
+	 { "SH_ID", 12, 12, &umr_bitfield_default },
+	 { "SE_ID", 13, 14, &umr_bitfield_default },
+	 { "TG_ID", 16, 19, &umr_bitfield_default },
+	 { "VM_ID", 20, 23, &umr_bitfield_default },
+	 { "QUEUE_ID", 24, 26, &umr_bitfield_default },
+	 { "STATE_ID", 27, 29, &umr_bitfield_default },
+	 { "ME_ID", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG1[] = {
+	 { "available_positions", 0, 6, &umr_bitfield_default },
+	 { "sx_receive_indx", 7, 9, &umr_bitfield_default },
+	 { "sx_pending_fifo_contents", 10, 14, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_misc_vec_ena", 15, 15, &umr_bitfield_default },
+	 { "statevar_bits_disable_sp", 16, 19, &umr_bitfield_default },
+	 { "aux_sel", 20, 21, &umr_bitfield_default },
+	 { "sx_to_pa_empty_1", 22, 22, &umr_bitfield_default },
+	 { "sx_to_pa_empty_0", 23, 23, &umr_bitfield_default },
+	 { "pasx_req_cnt_1", 24, 27, &umr_bitfield_default },
+	 { "pasx_req_cnt_0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_GPR_ALLOC[] = {
+	 { "VGPR_BASE", 0, 5, &umr_bitfield_default },
+	 { "VGPR_SIZE", 8, 13, &umr_bitfield_default },
+	 { "SGPR_BASE", 16, 21, &umr_bitfield_default },
+	 { "SGPR_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG21[] = {
+	 { "out_indx_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "indx_side_fifo_empty", 1, 1, &umr_bitfield_default },
+	 { "pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe2_dr", 4, 4, &umr_bitfield_default },
+	 { "vsthread_buff_empty", 5, 5, &umr_bitfield_default },
+	 { "out_indx_fifo_full", 6, 6, &umr_bitfield_default },
+	 { "indx_side_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "pipe0_rtr", 8, 8, &umr_bitfield_default },
+	 { "pipe1_rtr", 9, 9, &umr_bitfield_default },
+	 { "pipe2_rtr", 10, 10, &umr_bitfield_default },
+	 { "vsthread_buff_full", 11, 11, &umr_bitfield_default },
+	 { "interfaces_rtr", 12, 12, &umr_bitfield_default },
+	 { "indx_count_q_not_0", 13, 13, &umr_bitfield_default },
+	 { "wait_for_external_eopg_q", 14, 14, &umr_bitfield_default },
+	 { "full_state_p1_q", 15, 15, &umr_bitfield_default },
+	 { "indx_side_indx_valid", 16, 16, &umr_bitfield_default },
+	 { "stateid_p0_q", 17, 19, &umr_bitfield_default },
+	 { "is_event_p0_q", 20, 20, &umr_bitfield_default },
+	 { "lshs_dealloc_p1", 21, 21, &umr_bitfield_default },
+	 { "stream_id_r2_q", 22, 22, &umr_bitfield_default },
+	 { "vtx_vect_counter_q_not_0", 23, 23, &umr_bitfield_default },
+	 { "buff_full_p1", 24, 24, &umr_bitfield_default },
+	 { "strmout_valid_p1", 25, 25, &umr_bitfield_default },
+	 { "eotg_r2_q", 26, 26, &umr_bitfield_default },
+	 { "null_r2_q", 27, 27, &umr_bitfield_default },
+	 { "p0_dr", 28, 28, &umr_bitfield_default },
+	 { "p0_rtr", 29, 29, &umr_bitfield_default },
+	 { "eopg_p0_q", 30, 30, &umr_bitfield_default },
+	 { "p0_nobp", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG2[] = {
+	 { "param_cache_base", 0, 6, &umr_bitfield_default },
+	 { "sx_aux", 7, 8, &umr_bitfield_default },
+	 { "sx_request_indx", 9, 14, &umr_bitfield_default },
+	 { "req_active_verts_loaded", 15, 15, &umr_bitfield_default },
+	 { "req_active_verts", 16, 22, &umr_bitfield_default },
+	 { "vgt_to_ccgen_state_var_indx", 23, 25, &umr_bitfield_default },
+	 { "vgt_to_ccgen_active_verts", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_LDS_ALLOC[] = {
+	 { "LDS_BASE", 0, 7, &umr_bitfield_default },
+	 { "LDS_SIZE", 12, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG22[] = {
+	 { "cm_state16", 0, 1, &umr_bitfield_default },
+	 { "cm_state17", 2, 3, &umr_bitfield_default },
+	 { "cm_state18", 4, 5, &umr_bitfield_default },
+	 { "cm_state19", 6, 7, &umr_bitfield_default },
+	 { "cm_state20", 8, 9, &umr_bitfield_default },
+	 { "cm_state21", 10, 11, &umr_bitfield_default },
+	 { "cm_state22", 12, 13, &umr_bitfield_default },
+	 { "cm_state23", 14, 15, &umr_bitfield_default },
+	 { "cm_state24", 16, 17, &umr_bitfield_default },
+	 { "cm_state25", 18, 19, &umr_bitfield_default },
+	 { "cm_state26", 20, 21, &umr_bitfield_default },
+	 { "cm_state27", 22, 23, &umr_bitfield_default },
+	 { "cm_state28", 24, 25, &umr_bitfield_default },
+	 { "cm_state29", 26, 27, &umr_bitfield_default },
+	 { "cm_state30", 28, 29, &umr_bitfield_default },
+	 { "cm_state31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG3[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "vertex_fifo_entriesavailable", 8, 11, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_ccdist1_vec_ena", 12, 12, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_ccdist0_vec_ena", 13, 13, &umr_bitfield_default },
+	 { "available_positions", 14, 20, &umr_bitfield_default },
+	 { "current_state", 21, 22, &umr_bitfield_default },
+	 { "vertex_fifo_empty", 23, 23, &umr_bitfield_default },
+	 { "vertex_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "sx0_receive_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "sx0_receive_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "vgt_to_ccgen_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "vgt_to_ccgen_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "sx0_receive_fifo_write", 30, 30, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG23[] = {
+	 { "frmt_busy", 0, 0, &umr_bitfield_default },
+	 { "rcm_frmt_vert_rtr", 1, 1, &umr_bitfield_default },
+	 { "rcm_frmt_prim_rtr", 2, 2, &umr_bitfield_default },
+	 { "prim_r3_rtr", 3, 3, &umr_bitfield_default },
+	 { "prim_r2_rtr", 4, 4, &umr_bitfield_default },
+	 { "vert_r3_rtr", 5, 5, &umr_bitfield_default },
+	 { "vert_r2_rtr", 6, 6, &umr_bitfield_default },
+	 { "vert_r1_rtr", 7, 7, &umr_bitfield_default },
+	 { "vert_r0_rtr", 8, 8, &umr_bitfield_default },
+	 { "prim_fifo_empty", 9, 9, &umr_bitfield_default },
+	 { "prim_fifo_full", 10, 10, &umr_bitfield_default },
+	 { "vert_dr_r2_q", 11, 11, &umr_bitfield_default },
+	 { "prim_dr_r2_q", 12, 12, &umr_bitfield_default },
+	 { "vert_dr_r1_q", 13, 13, &umr_bitfield_default },
+	 { "vert_dr_r0_q", 14, 14, &umr_bitfield_default },
+	 { "new_verts_r2_q", 15, 16, &umr_bitfield_default },
+	 { "verts_sent_r2_q", 17, 20, &umr_bitfield_default },
+	 { "prim_state_sel_r2_q", 21, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_STS[] = {
+	 { "VM_CNT", 0, 3, &umr_bitfield_default },
+	 { "EXP_CNT", 4, 6, &umr_bitfield_default },
+	 { "LGKM_CNT", 8, 11, &umr_bitfield_default },
+	 { "VALU_CNT", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG0[] = {
+	 { "su_baryc_cntl_state", 0, 1, &umr_bitfield_default },
+	 { "su_cntl_state", 2, 5, &umr_bitfield_default },
+	 { "pmode_state", 8, 13, &umr_bitfield_default },
+	 { "ge_stallb", 14, 14, &umr_bitfield_default },
+	 { "geom_enable", 15, 15, &umr_bitfield_default },
+	 { "su_clip_baryc_free", 16, 17, &umr_bitfield_default },
+	 { "su_clip_rtr", 18, 18, &umr_bitfield_default },
+	 { "pfifo_busy", 19, 19, &umr_bitfield_default },
+	 { "su_cntl_busy", 20, 20, &umr_bitfield_default },
+	 { "geom_busy", 21, 21, &umr_bitfield_default },
+	 { "event_id_gated", 22, 27, &umr_bitfield_default },
+	 { "event_gated", 28, 28, &umr_bitfield_default },
+	 { "pmode_prim_gated", 29, 29, &umr_bitfield_default },
+	 { "su_dyn_sclk_vld", 30, 30, &umr_bitfield_default },
+	 { "cl_dyn_sclk_vld", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG24[] = {
+	 { "avail_es_rb_space_r0_q_23_0", 0, 23, &umr_bitfield_default },
+	 { "dependent_st_cut_mode_q", 24, 25, &umr_bitfield_default },
+	 { "SPARE31", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_PC_LO[] = {
+	 { "PC_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG1[] = {
+	 { "y_sort0_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort0_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG25[] = {
+	 { "avail_gs_rb_space_r0_q_25_0", 0, 25, &umr_bitfield_default },
+	 { "active_sm_r0_q", 26, 29, &umr_bitfield_default },
+	 { "add_gs_rb_space_r1_q", 30, 30, &umr_bitfield_default },
+	 { "add_gs_rb_space_r0_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_PC_HI[] = {
+	 { "PC_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG2[] = {
+	 { "y_sort1_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort1_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG3[] = {
+	 { "y_sort2_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort2_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG27[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "gsc0_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "tm_pt_event_rtr", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "gsc0_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipe1_rtr", 6, 6, &umr_bitfield_default },
+	 { "last_indx_of_prim_p1_q", 7, 7, &umr_bitfield_default },
+	 { "indices_to_send_p0_q", 8, 9, &umr_bitfield_default },
+	 { "event_flag_p1_q", 10, 10, &umr_bitfield_default },
+	 { "eop_p1_q", 11, 11, &umr_bitfield_default },
+	 { "gs_out_prim_type_p0_q", 12, 13, &umr_bitfield_default },
+	 { "gsc_null_primitive_p0_q", 14, 14, &umr_bitfield_default },
+	 { "gsc_eop_p0_q", 15, 15, &umr_bitfield_default },
+	 { "gsc_2cycle_output", 16, 16, &umr_bitfield_default },
+	 { "gsc_2nd_cycle_p0_q", 17, 17, &umr_bitfield_default },
+	 { "last_indx_of_vsprim", 18, 18, &umr_bitfield_default },
+	 { "first_vsprim_of_gsprim_p0_q", 19, 19, &umr_bitfield_default },
+	 { "gsc_indx_count_p0_q", 20, 30, &umr_bitfield_default },
+	 { "last_vsprim_of_gsprim", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG4[] = {
+	 { "attr_indx_sort0_gated", 0, 13, &umr_bitfield_default },
+	 { "null_prim_gated", 14, 14, &umr_bitfield_default },
+	 { "backfacing_gated", 15, 15, &umr_bitfield_default },
+	 { "st_indx_gated", 16, 18, &umr_bitfield_default },
+	 { "clipped_gated", 19, 19, &umr_bitfield_default },
+	 { "dealloc_slot_gated", 20, 22, &umr_bitfield_default },
+	 { "xmajor_gated", 23, 23, &umr_bitfield_default },
+	 { "diamond_rule_gated", 24, 25, &umr_bitfield_default },
+	 { "type_gated", 26, 28, &umr_bitfield_default },
+	 { "fpov_gated", 29, 30, &umr_bitfield_default },
+	 { "eop_gated", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_DBG0[] = {
+	 { "IBUF_ST", 0, 2, &umr_bitfield_default },
+	 { "PC_INVALID", 3, 3, &umr_bitfield_default },
+	 { "NEED_NEXT_DW", 4, 4, &umr_bitfield_default },
+	 { "NO_PREFETCH_CNT", 5, 7, &umr_bitfield_default },
+	 { "IBUF_RPTR", 8, 9, &umr_bitfield_default },
+	 { "IBUF_WPTR", 10, 11, &umr_bitfield_default },
+	 { "INST_STR_ST", 16, 18, &umr_bitfield_default },
+	 { "MISC_CNT", 19, 21, &umr_bitfield_default },
+	 { "ECC_ST", 22, 23, &umr_bitfield_default },
+	 { "IS_HYB", 24, 24, &umr_bitfield_default },
+	 { "HYB_CNT", 25, 26, &umr_bitfield_default },
+	 { "KILL", 27, 27, &umr_bitfield_default },
+	 { "NEED_KILL_IFETCH", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG5[] = {
+	 { "attr_indx_sort2_gated", 0, 13, &umr_bitfield_default },
+	 { "attr_indx_sort1_gated", 14, 27, &umr_bitfield_default },
+	 { "provoking_vtx_gated", 28, 29, &umr_bitfield_default },
+	 { "valid_prim_gated", 30, 30, &umr_bitfield_default },
+	 { "pa_reg_sclk_vld", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG29[] = {
+	 { "con_state_q", 0, 3, &umr_bitfield_default },
+	 { "second_cycle_q", 4, 4, &umr_bitfield_default },
+	 { "process_tri_middle_p0_q", 5, 5, &umr_bitfield_default },
+	 { "process_tri_1st_2nd_half_p0_q", 6, 6, &umr_bitfield_default },
+	 { "process_tri_center_poly_p0_q", 7, 7, &umr_bitfield_default },
+	 { "pipe0_patch_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe0_edge_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe1_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 11, 11, &umr_bitfield_default },
+	 { "pipe0_edge_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe1_rtr", 13, 13, &umr_bitfield_default },
+	 { "outer_parity_p0_q", 14, 14, &umr_bitfield_default },
+	 { "parallel_parity_p0_q", 15, 15, &umr_bitfield_default },
+	 { "first_ring_of_patch_p0_q", 16, 16, &umr_bitfield_default },
+	 { "last_ring_of_patch_p0_q", 17, 17, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring_p0_q", 18, 18, &umr_bitfield_default },
+	 { "last_point_of_outer_ring_p1", 19, 19, &umr_bitfield_default },
+	 { "last_point_of_inner_ring_p1", 20, 20, &umr_bitfield_default },
+	 { "outer_edge_tf_eq_one_p0_q", 21, 21, &umr_bitfield_default },
+	 { "advance_outer_point_p1", 22, 22, &umr_bitfield_default },
+	 { "advance_inner_point_p1", 23, 23, &umr_bitfield_default },
+	 { "next_ring_is_rect_p0_q", 24, 24, &umr_bitfield_default },
+	 { "pipe1_outer1_rtr", 25, 25, &umr_bitfield_default },
+	 { "pipe1_outer2_rtr", 26, 26, &umr_bitfield_default },
+	 { "pipe1_inner1_rtr", 27, 27, &umr_bitfield_default },
+	 { "pipe1_inner2_rtr", 28, 28, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 29, 29, &umr_bitfield_default },
+	 { "pipe1_edge_rtr", 30, 30, &umr_bitfield_default },
+	 { "use_stored_inner_q_ring3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_THREAD_TRACE_TG0[] = {
+	 { "TGID_X", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG2[] = {
+	 { "hs_grp_busy", 0, 0, &umr_bitfield_default },
+	 { "hs_noif_busy", 1, 1, &umr_bitfield_default },
+	 { "tfmmIsBusy", 2, 2, &umr_bitfield_default },
+	 { "lsVertIfBusy_0", 3, 3, &umr_bitfield_default },
+	 { "te11_hs_tess_input_rtr", 4, 4, &umr_bitfield_default },
+	 { "lsWaveIfBusy_0", 5, 5, &umr_bitfield_default },
+	 { "hs_te11_tess_input_rts", 6, 6, &umr_bitfield_default },
+	 { "grpModBusy", 7, 7, &umr_bitfield_default },
+	 { "lsVertFifoEmpty", 8, 8, &umr_bitfield_default },
+	 { "lsWaveFifoEmpty", 9, 9, &umr_bitfield_default },
+	 { "hsVertFifoEmpty", 10, 10, &umr_bitfield_default },
+	 { "hsWaveFifoEmpty", 11, 11, &umr_bitfield_default },
+	 { "hsInputFifoEmpty", 12, 12, &umr_bitfield_default },
+	 { "hsTifFifoEmpty", 13, 13, &umr_bitfield_default },
+	 { "lsVertFifoFull", 14, 14, &umr_bitfield_default },
+	 { "lsWaveFifoFull", 15, 15, &umr_bitfield_default },
+	 { "hsVertFifoFull", 16, 16, &umr_bitfield_default },
+	 { "hsWaveFifoFull", 17, 17, &umr_bitfield_default },
+	 { "hsInputFifoFull", 18, 18, &umr_bitfield_default },
+	 { "hsTifFifoFull", 19, 19, &umr_bitfield_default },
+	 { "p0_rtr", 20, 20, &umr_bitfield_default },
+	 { "p1_rtr", 21, 21, &umr_bitfield_default },
+	 { "p0_dr", 22, 22, &umr_bitfield_default },
+	 { "p1_dr", 23, 23, &umr_bitfield_default },
+	 { "p0_rts", 24, 24, &umr_bitfield_default },
+	 { "p1_rts", 25, 25, &umr_bitfield_default },
+	 { "ls_sh_id", 26, 26, &umr_bitfield_default },
+	 { "lsFwaveFlag", 27, 27, &umr_bitfield_default },
+	 { "lsWaveSendFlush", 28, 28, &umr_bitfield_default },
+	 { "SPARE", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_THREAD_TRACE_EVENT[] = {
+	 { "EVENT_ID", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG3[] = {
+	 { "lsTgRelInd", 0, 11, &umr_bitfield_default },
+	 { "lsWaveRelInd", 12, 17, &umr_bitfield_default },
+	 { "lsPatchCnt", 18, 25, &umr_bitfield_default },
+	 { "hsWaveRelInd", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG02[] = {
+	 { "clip_extra_bc_valid", 0, 2, &umr_bitfield_default },
+	 { "clip_vert_vte_valid", 3, 5, &umr_bitfield_default },
+	 { "clip_to_outsm_clip_seq_indx", 6, 7, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_2", 8, 11, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_1", 12, 15, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_0", 16, 19, &umr_bitfield_default },
+	 { "clip_to_clipga_extra_bc_coords", 20, 20, &umr_bitfield_default },
+	 { "clip_to_clipga_vte_naninf_kill", 21, 21, &umr_bitfield_default },
+	 { "clip_to_outsm_end_of_packet", 22, 22, &umr_bitfield_default },
+	 { "clip_to_outsm_first_prim_of_slot", 23, 23, &umr_bitfield_default },
+	 { "clip_to_outsm_clipped_prim", 24, 24, &umr_bitfield_default },
+	 { "clip_to_outsm_null_primitive", 25, 25, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 28, 28, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_empty", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG2[] = {
+	 { "ds_full", 0, 0, &umr_bitfield_default },
+	 { "ds_credit_avail", 1, 1, &umr_bitfield_default },
+	 { "ord_idx_free", 2, 2, &umr_bitfield_default },
+	 { "cmd_write", 3, 3, &umr_bitfield_default },
+	 { "app_sel", 4, 7, &umr_bitfield_default },
+	 { "req", 8, 22, &umr_bitfield_default },
+	 { "spare", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG2[] = {
+	 { "p1_grbm_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "p1_grbm_fifo_full", 1, 1, &umr_bitfield_default },
+	 { "p1_grbm_fifo_we", 2, 2, &umr_bitfield_default },
+	 { "p1_grbm_fifo_re", 3, 3, &umr_bitfield_default },
+	 { "p1_draw_initiator_valid_q", 4, 4, &umr_bitfield_default },
+	 { "p1_event_initiator_valid_q", 5, 5, &umr_bitfield_default },
+	 { "p1_event_addr_valid_q", 6, 6, &umr_bitfield_default },
+	 { "p1_dma_request_valid_q", 7, 7, &umr_bitfield_default },
+	 { "SPARE0", 8, 8, &umr_bitfield_default },
+	 { "p1_min_indx_valid_q", 9, 9, &umr_bitfield_default },
+	 { "p1_max_indx_valid_q", 10, 10, &umr_bitfield_default },
+	 { "p1_indx_offset_valid_q", 11, 11, &umr_bitfield_default },
+	 { "p1_grbm_fifo_rdata_reg_id", 12, 16, &umr_bitfield_default },
+	 { "p1_grbm_fifo_rdata_state", 17, 19, &umr_bitfield_default },
+	 { "p1_free_cnt_q", 20, 25, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_we", 26, 26, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_we", 27, 27, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG4[] = {
+	 { "hsPatchCnt", 0, 7, &umr_bitfield_default },
+	 { "hsPrimId_15_0", 8, 23, &umr_bitfield_default },
+	 { "hsCpCnt", 24, 28, &umr_bitfield_default },
+	 { "hsWaveSendFlush", 29, 29, &umr_bitfield_default },
+	 { "hsFwaveFlag", 30, 30, &umr_bitfield_default },
+	 { "SPARE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CNTL[] = {
+	 { "READ_TIMEOUT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SKEW_CNTL[] = {
+	 { "SKEW_TOP_THRESHOLD", 0, 5, &umr_bitfield_default },
+	 { "SKEW_COUNT", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS2[] = {
+	 { "ME0PIPE1_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "ME0PIPE1_CF_RQ_PENDING", 4, 4, &umr_bitfield_default },
+	 { "ME0PIPE1_PF_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME1PIPE0_RQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "ME1PIPE1_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME1PIPE2_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "ME1PIPE3_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "ME2PIPE0_RQ_PENDING", 10, 10, &umr_bitfield_default },
+	 { "ME2PIPE1_RQ_PENDING", 11, 11, &umr_bitfield_default },
+	 { "ME2PIPE2_RQ_PENDING", 12, 12, &umr_bitfield_default },
+	 { "ME2PIPE3_RQ_PENDING", 13, 13, &umr_bitfield_default },
+	 { "RLC_RQ_PENDING", 14, 14, &umr_bitfield_default },
+	 { "RLC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TC_BUSY", 25, 25, &umr_bitfield_default },
+	 { "CPF_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPG_BUSY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PWR_CNTL[] = {
+	 { "REQ_TYPE", 0, 3, &umr_bitfield_default },
+	 { "RSP_TYPE", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS[] = {
+	 { "ME0PIPE0_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "SRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME0PIPE0_CF_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME0PIPE0_PF_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "GDS_DMA_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "DB_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "CB_CLEAN", 13, 13, &umr_bitfield_default },
+	 { "TA_BUSY", 14, 14, &umr_bitfield_default },
+	 { "GDS_BUSY", 15, 15, &umr_bitfield_default },
+	 { "WD_BUSY_NO_DMA", 16, 16, &umr_bitfield_default },
+	 { "VGT_BUSY", 17, 17, &umr_bitfield_default },
+	 { "IA_BUSY_NO_DMA", 18, 18, &umr_bitfield_default },
+	 { "IA_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SX_BUSY", 20, 20, &umr_bitfield_default },
+	 { "WD_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SPI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "BCI_BUSY", 23, 23, &umr_bitfield_default },
+	 { "SC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "PA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "DB_BUSY", 26, 26, &umr_bitfield_default },
+	 { "CP_COHERENCY_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CP_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "GUI_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE0[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE1[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SOFT_RESET[] = {
+	 { "SOFT_RESET_CP", 0, 0, &umr_bitfield_default },
+	 { "SOFT_RESET_RLC", 2, 2, &umr_bitfield_default },
+	 { "SOFT_RESET_GFX", 16, 16, &umr_bitfield_default },
+	 { "SOFT_RESET_CPF", 17, 17, &umr_bitfield_default },
+	 { "SOFT_RESET_CPC", 18, 18, &umr_bitfield_default },
+	 { "SOFT_RESET_CPG", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_CNTL[] = {
+	 { "GRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_GFX_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_WAIT_IDLE_CLOCKS[] = {
+	 { "WAIT_IDLE_CLOCKS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE2[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE3[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG[] = {
+	 { "IGNORE_RDY", 1, 1, &umr_bitfield_default },
+	 { "IGNORE_FAO", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_READ_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "SNAPSHOT_FREE_CNTRS", 7, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_GUI_ACTIVE", 8, 11, &umr_bitfield_default },
+	 { "GFX_CLOCK_DOMAIN_OVERRIDE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_SNAPSHOT[] = {
+	 { "CPF_RDY", 0, 0, &umr_bitfield_default },
+	 { "CPG_RDY", 1, 1, &umr_bitfield_default },
+	 { "SRBM_RDY", 2, 2, &umr_bitfield_default },
+	 { "WD_ME0PIPE0_RDY", 3, 3, &umr_bitfield_default },
+	 { "WD_ME0PIPE1_RDY", 4, 4, &umr_bitfield_default },
+	 { "GDS_RDY", 5, 5, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY0", 6, 6, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY0", 7, 7, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY0", 8, 8, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY0", 9, 9, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY0", 10, 10, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY0", 11, 11, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY0", 12, 12, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY0", 13, 13, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY1", 14, 14, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY1", 15, 15, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY1", 16, 16, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY1", 17, 17, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY1", 18, 18, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY1", 19, 19, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY1", 20, 20, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY1", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_READ_ERROR[] = {
+	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "READ_PIPEID", 20, 21, &umr_bitfield_default },
+	 { "READ_MEID", 22, 23, &umr_bitfield_default },
+	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_READ_ERROR2[] = {
+	 { "READ_REQUESTER_SRBM", 17, 17, &umr_bitfield_default },
+	 { "READ_REQUESTER_RLC", 18, 18, &umr_bitfield_default },
+	 { "READ_REQUESTER_GDS_DMA", 19, 19, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE0_CF", 20, 20, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE0_PF", 21, 21, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE1_CF", 22, 22, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE1_PF", 23, 23, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE0", 24, 24, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE1", 25, 25, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE2", 26, 26, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE3", 27, 27, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE0", 28, 28, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE1", 29, 29, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE2", 30, 30, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_INT_CNTL[] = {
+	 { "RDERR_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GUI_IDLE_INT_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEBUG_INDEX[] = {
+	 { "DEBUG_INDEX", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEBUG_DATA[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_NOWHERE[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_STATUS[] = {
+	 { "MEC1_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MEC2_BUSY", 1, 1, &umr_bitfield_default },
+	 { "DC0_BUSY", 2, 2, &umr_bitfield_default },
+	 { "DC1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "RCIU1_BUSY", 4, 4, &umr_bitfield_default },
+	 { "RCIU2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "ROQ1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "ROQ2_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MIU_RDREQ_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MIU_WRREQ_BUSY", 9, 9, &umr_bitfield_default },
+	 { "TCIU_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 11, 11, &umr_bitfield_default },
+	 { "QU_BUSY", 12, 12, &umr_bitfield_default },
+	 { "CPG_CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPF_CPC_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CPC_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_BUSY_STAT[] = {
+	 { "MEC1_LOAD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MEC1_SEMAPOHRE_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MEC1_MUTEX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "MEC1_MESSAGE_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MEC1_EOP_QUEUE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "MEC1_IQ_QUEUE_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MEC1_IB_QUEUE_BUSY", 6, 6, &umr_bitfield_default },
+	 { "MEC1_TC_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MEC1_DMA_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MEC1_PARTIAL_FLUSH_BUSY", 9, 9, &umr_bitfield_default },
+	 { "MEC1_PIPE0_BUSY", 10, 10, &umr_bitfield_default },
+	 { "MEC1_PIPE1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "MEC1_PIPE2_BUSY", 12, 12, &umr_bitfield_default },
+	 { "MEC1_PIPE3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "MEC2_LOAD_BUSY", 16, 16, &umr_bitfield_default },
+	 { "MEC2_SEMAPOHRE_BUSY", 17, 17, &umr_bitfield_default },
+	 { "MEC2_MUTEX_BUSY", 18, 18, &umr_bitfield_default },
+	 { "MEC2_MESSAGE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "MEC2_EOP_QUEUE_BUSY", 20, 20, &umr_bitfield_default },
+	 { "MEC2_IQ_QUEUE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "MEC2_IB_QUEUE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "MEC2_TC_BUSY", 23, 23, &umr_bitfield_default },
+	 { "MEC2_DMA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "MEC2_PARTIAL_FLUSH_BUSY", 25, 25, &umr_bitfield_default },
+	 { "MEC2_PIPE0_BUSY", 26, 26, &umr_bitfield_default },
+	 { "MEC2_PIPE1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "MEC2_PIPE2_BUSY", 28, 28, &umr_bitfield_default },
+	 { "MEC2_PIPE3_BUSY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_STALLED_STAT1[] = {
+	 { "MIU_RDREQ_FREE_STALL", 0, 0, &umr_bitfield_default },
+	 { "MIU_WRREQ_FREE_STALL", 1, 1, &umr_bitfield_default },
+	 { "RCIU_TX_FREE_STALL", 3, 3, &umr_bitfield_default },
+	 { "RCIU_PRIV_VIOLATION", 4, 4, &umr_bitfield_default },
+	 { "TCIU_TX_FREE_STALL", 6, 6, &umr_bitfield_default },
+	 { "MEC1_DECODING_PACKET", 8, 8, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_RCIU", 9, 9, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_RCIU_READ", 10, 10, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_MC_READ", 11, 11, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_MC_WR_ACK", 12, 12, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_ROQ_DATA", 13, 13, &umr_bitfield_default },
+	 { "MEC2_DECODING_PACKET", 16, 16, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_RCIU", 17, 17, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_RCIU_READ", 18, 18, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_MC_READ", 19, 19, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_MC_WR_ACK", 20, 20, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_ROQ_DATA", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_STATUS[] = {
+	 { "POST_WPTR_GFX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CSF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MIU_RDREQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "MIU_WRREQ_BUSY", 3, 3, &umr_bitfield_default },
+	 { "ROQ_ALIGN_BUSY", 4, 4, &umr_bitfield_default },
+	 { "ROQ_RING_BUSY", 5, 5, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 7, 7, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 8, 8, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 13, 13, &umr_bitfield_default },
+	 { "TCIU_BUSY", 14, 14, &umr_bitfield_default },
+	 { "HQD_BUSY", 15, 15, &umr_bitfield_default },
+	 { "CPC_CPF_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CPF_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_BUSY_STAT[] = {
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CSF_RING_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CSF_INDIRECT1_BUSY", 2, 2, &umr_bitfield_default },
+	 { "CSF_INDIRECT2_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CSF_STATE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CSF_CE_INDR1_BUSY", 5, 5, &umr_bitfield_default },
+	 { "CSF_CE_INDR2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CSF_ARBITER_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CSF_INPUT_BUSY", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_READ_TAGS", 9, 9, &umr_bitfield_default },
+	 { "HPD_PROCESSING_EOP_BUSY", 11, 11, &umr_bitfield_default },
+	 { "HQD_DISPATCH_BUSY", 12, 12, &umr_bitfield_default },
+	 { "HQD_IQ_TIMER_BUSY", 13, 13, &umr_bitfield_default },
+	 { "HQD_DMA_OFFLOAD_BUSY", 14, 14, &umr_bitfield_default },
+	 { "HQD_WAIT_SEMAPHORE_BUSY", 15, 15, &umr_bitfield_default },
+	 { "HQD_SIGNAL_SEMAPHORE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "HQD_MESSAGE_BUSY", 17, 17, &umr_bitfield_default },
+	 { "HQD_PQ_FETCHER_BUSY", 18, 18, &umr_bitfield_default },
+	 { "HQD_IB_FETCHER_BUSY", 19, 19, &umr_bitfield_default },
+	 { "HQD_IQ_FETCHER_BUSY", 20, 20, &umr_bitfield_default },
+	 { "HQD_EOP_FETCHER_BUSY", 21, 21, &umr_bitfield_default },
+	 { "HQD_CONSUMED_RPTR_BUSY", 22, 22, &umr_bitfield_default },
+	 { "HQD_FETCHER_ARB_BUSY", 23, 23, &umr_bitfield_default },
+	 { "HQD_ROQ_ALIGN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "HQD_ROQ_EOP_BUSY", 25, 25, &umr_bitfield_default },
+	 { "HQD_ROQ_IQ_BUSY", 26, 26, &umr_bitfield_default },
+	 { "HQD_ROQ_PQ_BUSY", 27, 27, &umr_bitfield_default },
+	 { "HQD_ROQ_IB_BUSY", 28, 28, &umr_bitfield_default },
+	 { "HQD_WPTR_POLL_BUSY", 29, 29, &umr_bitfield_default },
+	 { "HQD_PQ_BUSY", 30, 30, &umr_bitfield_default },
+	 { "HQD_IB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_STALLED_STAT1[] = {
+	 { "RING_FETCHING_DATA", 0, 0, &umr_bitfield_default },
+	 { "INDR1_FETCHING_DATA", 1, 1, &umr_bitfield_default },
+	 { "INDR2_FETCHING_DATA", 2, 2, &umr_bitfield_default },
+	 { "STATE_FETCHING_DATA", 3, 3, &umr_bitfield_default },
+	 { "MIU_WAITING_ON_RDREQ_FREE", 4, 4, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 5, 5, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_MC_CNTL[] = {
+	 { "PACK_DELAY_CNT", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_CNTL[] = {
+	 { "MEC_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "MEC_ME2_HALT", 28, 28, &umr_bitfield_default },
+	 { "MEC_ME2_STEP", 29, 29, &umr_bitfield_default },
+	 { "MEC_ME1_HALT", 30, 30, &umr_bitfield_default },
+	 { "MEC_ME1_STEP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_HEADER_DUMP[] = {
+	 { "HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_HEADER_DUMP[] = {
+	 { "HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_HALT_HYST_COUNT[] = {
+	 { "COUNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL0[] = {
+	 { "BU_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL1[] = {
+	 { "BASE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL2[] = {
+	 { "BASE_HI", 0, 1, &umr_bitfield_default },
+	 { "INTERVAL", 2, 9, &umr_bitfield_default },
+	 { "RESET_CNT", 10, 17, &umr_bitfield_default },
+	 { "RESET_FORCE", 18, 18, &umr_bitfield_default },
+	 { "REPORT_AND_RESET", 19, 19, &umr_bitfield_default },
+	 { "MC_ENDIAN_SWAP", 20, 21, &umr_bitfield_default },
+	 { "MC_VMID", 23, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_INTERRUPT_WORD_AUTO[] = {
+	 { "THREAD_TRACE", 0, 0, &umr_bitfield_default },
+	 { "WLT", 1, 1, &umr_bitfield_default },
+	 { "THREAD_TRACE_BUF_FULL", 2, 2, &umr_bitfield_default },
+	 { "REG_TIMESTAMP", 3, 3, &umr_bitfield_default },
+	 { "CMD_TIMESTAMP", 4, 4, &umr_bitfield_default },
+	 { "HOST_CMD_OVERFLOW", 5, 5, &umr_bitfield_default },
+	 { "HOST_REG_OVERFLOW", 6, 6, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "SE_ID", 24, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_INTERRUPT_WORD_CMN[] = {
+	 { "SE_ID", 24, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_COMPARE_COUNT[] = {
+	 { "COMPARE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_DE_COUNT[] = {
+	 { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_CE_COUNT[] = {
+	 { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_LAST_INVAL_COUNT[] = {
+	 { "LAST_INVAL_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_DE_COUNT[] = {
+	 { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG5[] = {
+	 { "SPARE4", 0, 2, &umr_bitfield_default },
+	 { "hsWaveCreditCnt_0", 3, 7, &umr_bitfield_default },
+	 { "SPARE3", 8, 10, &umr_bitfield_default },
+	 { "hsVertCreditCnt_0", 11, 15, &umr_bitfield_default },
+	 { "SPARE2", 16, 18, &umr_bitfield_default },
+	 { "lsWaveCreditCnt_0", 19, 23, &umr_bitfield_default },
+	 { "SPARE1", 24, 26, &umr_bitfield_default },
+	 { "lsVertCreditCnt_0", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT3[] = {
+	 { "CE_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER", 2, 2, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_NOT_RDY", 3, 3, &umr_bitfield_default },
+	 { "CE_TO_RAM_DUMP_NOT_RDY", 4, 4, &umr_bitfield_default },
+	 { "CE_TO_RAM_WRITE_NOT_RDY", 5, 5, &umr_bitfield_default },
+	 { "CE_TO_INC_FIFO_NOT_RDY_TO_RCV", 6, 6, &umr_bitfield_default },
+	 { "CE_TO_WR_FIFO_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default },
+	 { "CE_TO_MIU_WRITE_NOT_RDY_TO_RCV", 8, 8, &umr_bitfield_default },
+	 { "CE_WAITING_ON_BUFFER_DATA", 10, 10, &umr_bitfield_default },
+	 { "CE_WAITING_ON_CE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER", 12, 12, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER_UNDERFLOW", 13, 13, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 14, 14, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT1[] = {
+	 { "RBIU_TO_DMA_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "RBIU_TO_SEM_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "RBIU_TO_MEMWR_NOT_RDY_TO_RCV", 4, 4, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_CE_BUFFER_FLAG", 10, 10, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_DE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "ME_STALLED_ON_TC_WR_CONFIRM", 12, 12, &umr_bitfield_default },
+	 { "ME_STALLED_ON_ATOMIC_RTN_DATA", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_ON_MC_READ_DATA", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_REG_READ_DATA", 15, 15, &umr_bitfield_default },
+	 { "MIU_WAITING_ON_RDREQ_FREE", 16, 16, &umr_bitfield_default },
+	 { "MIU_WAITING_ON_WRREQ_FREE", 17, 17, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GDS_FREE", 23, 23, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GRBM_FREE", 24, 24, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_VGT_FREE", 25, 25, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_ME_READ", 26, 26, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_DMA_READ", 27, 27, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_APPEND_READ", 28, 28, &umr_bitfield_default },
+	 { "RCIU_HALTED_BY_REG_VIOLATION", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT2[] = {
+	 { "PFP_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "PFP_TO_MEQ_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "PFP_TO_RCIU_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "PFP_TO_VGT_WRITES_PENDING", 4, 4, &umr_bitfield_default },
+	 { "PFP_RCIU_READ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "PFP_MIU_READ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "PFP_TO_MIU_WRITE_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default },
+	 { "PFP_WAITING_ON_BUFFER_DATA", 8, 8, &umr_bitfield_default },
+	 { "ME_WAIT_ON_CE_COUNTER", 9, 9, &umr_bitfield_default },
+	 { "ME_WAIT_ON_AVAIL_BUFFER", 10, 10, &umr_bitfield_default },
+	 { "GFX_CNTX_NOT_AVAIL_TO_ME", 11, 11, &umr_bitfield_default },
+	 { "ME_RCIU_NOT_RDY_TO_RCV", 12, 12, &umr_bitfield_default },
+	 { "ME_TO_CONST_NOT_RDY_TO_RCV", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_PFP", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_PARTIAL_FLUSH", 15, 15, &umr_bitfield_default },
+	 { "MEQ_TO_ME_NOT_RDY_TO_RCV", 16, 16, &umr_bitfield_default },
+	 { "STQ_TO_ME_NOT_RDY_TO_RCV", 17, 17, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_STQ", 18, 18, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_TC_WR_CONFIRM", 19, 19, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_ATOMIC_RTN_DATA", 20, 20, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_SC_EOP_DONE", 21, 21, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_WR_CONFIRM", 22, 22, &umr_bitfield_default },
+	 { "STRMO_WR_OF_PRIM_DATA_PENDING", 23, 23, &umr_bitfield_default },
+	 { "PIPE_STATS_WR_DATA_PENDING", 24, 24, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_CS_DONE", 25, 25, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_PS_DONE", 26, 26, &umr_bitfield_default },
+	 { "APPEND_WAIT_ON_WR_CONFIRM", 27, 27, &umr_bitfield_default },
+	 { "APPEND_ACTIVE_PARTITION", 28, 28, &umr_bitfield_default },
+	 { "APPEND_WAITING_TO_SEND_MEMWRITE", 29, 29, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_IDLE_CNTXS", 30, 30, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_ALL_CLEAN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_BUSY_STAT[] = {
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COHER_CNT_NEQ_ZERO", 6, 6, &umr_bitfield_default },
+	 { "PFP_PARSING_PACKETS", 7, 7, &umr_bitfield_default },
+	 { "ME_PARSING_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "RCIU_PFP_BUSY", 9, 9, &umr_bitfield_default },
+	 { "RCIU_ME_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SEM_CMDFIFO_NOT_EMPTY", 12, 12, &umr_bitfield_default },
+	 { "SEM_FAILED_AND_HOLDING", 13, 13, &umr_bitfield_default },
+	 { "SEM_POLLING_FOR_PASS", 14, 14, &umr_bitfield_default },
+	 { "GFX_CONTEXT_BUSY", 15, 15, &umr_bitfield_default },
+	 { "ME_PARSER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "EOP_DONE_BUSY", 18, 18, &umr_bitfield_default },
+	 { "STRM_OUT_BUSY", 19, 19, &umr_bitfield_default },
+	 { "PIPE_STATS_BUSY", 20, 20, &umr_bitfield_default },
+	 { "RCIU_CE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "CE_PARSING_PACKETS", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STAT[] = {
+	 { "MIU_RDREQ_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MIU_WRREQ_BUSY", 8, 8, &umr_bitfield_default },
+	 { "ROQ_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DC_BUSY", 13, 13, &umr_bitfield_default },
+	 { "PFP_BUSY", 15, 15, &umr_bitfield_default },
+	 { "MEQ_BUSY", 16, 16, &umr_bitfield_default },
+	 { "ME_BUSY", 17, 17, &umr_bitfield_default },
+	 { "QUERY_BUSY", 18, 18, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 20, 20, &umr_bitfield_default },
+	 { "SURFACE_SYNC_BUSY", 21, 21, &umr_bitfield_default },
+	 { "DMA_BUSY", 22, 22, &umr_bitfield_default },
+	 { "RCIU_BUSY", 23, 23, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 24, 24, &umr_bitfield_default },
+	 { "CPC_CPG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "CE_BUSY", 26, 26, &umr_bitfield_default },
+	 { "TCIU_BUSY", 27, 27, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 28, 28, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 29, 29, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CP_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_HEADER_DUMP[] = {
+	 { "ME_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_HEADER_DUMP[] = {
+	 { "PFP_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+	 { "FREE_COUNT_GDS", 8, 13, &umr_bitfield_default },
+	 { "FREE_COUNT_PFP", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_HEADER_DUMP[] = {
+	 { "CE_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MC_PACK_DELAY_CNT[] = {
+	 { "PACK_DELAY_CNT", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MC_TAG_CNTL[] = {
+	 { "TAG_RAM_INDEX", 0, 5, &umr_bitfield_default },
+	 { "TAG_RAM_SEL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MC_TAG_DATA[] = {
+	 { "TAG_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CSF_STAT[] = {
+	 { "BUFFER_SLOTS_ALLOCATED", 0, 3, &umr_bitfield_default },
+	 { "BUFFER_REQUEST_COUNT", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CSF_CNTL[] = {
+	 { "FETCH_BUFFER_DEPTH", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_CNTL[] = {
+	 { "CE_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "PFP_INVALIDATE_ICACHE", 6, 6, &umr_bitfield_default },
+	 { "ME_INVALIDATE_ICACHE", 8, 8, &umr_bitfield_default },
+	 { "CE_HALT", 24, 24, &umr_bitfield_default },
+	 { "CE_STEP", 25, 25, &umr_bitfield_default },
+	 { "PFP_HALT", 26, 26, &umr_bitfield_default },
+	 { "PFP_STEP", 27, 27, &umr_bitfield_default },
+	 { "ME_HALT", 28, 28, &umr_bitfield_default },
+	 { "ME_STEP", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CNTX_STAT[] = {
+	 { "ACTIVE_HP3D_CONTEXTS", 0, 7, &umr_bitfield_default },
+	 { "CURRENT_HP3D_CONTEXT", 8, 10, &umr_bitfield_default },
+	 { "ACTIVE_GFX_CONTEXTS", 20, 27, &umr_bitfield_default },
+	 { "CURRENT_GFX_CONTEXT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_PREEMPTION[] = {
+	 { "ME_CNTXSW_PREEMPTION", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_THRESHOLDS[] = {
+	 { "IB1_START", 0, 7, &umr_bitfield_default },
+	 { "IB2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_STQ_THRESHOLD[] = {
+	 { "STQ_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_DELAY[] = {
+	 { "PRE_WRITE_TIMER", 0, 27, &umr_bitfield_default },
+	 { "PRE_WRITE_LIMIT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_CNTL[] = {
+	 { "POLL_FREQUENCY", 0, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ1_THRESHOLDS[] = {
+	 { "RB1_START", 0, 7, &umr_bitfield_default },
+	 { "RB2_START", 8, 15, &umr_bitfield_default },
+	 { "R0_IB1_START", 16, 23, &umr_bitfield_default },
+	 { "R1_IB1_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ2_THRESHOLDS[] = {
+	 { "R2_IB1_START", 0, 7, &umr_bitfield_default },
+	 { "R0_IB2_START", 8, 15, &umr_bitfield_default },
+	 { "R1_IB2_START", 16, 23, &umr_bitfield_default },
+	 { "R2_IB2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_THRESHOLDS[] = {
+	 { "STQ0_START", 0, 7, &umr_bitfield_default },
+	 { "STQ1_START", 8, 15, &umr_bitfield_default },
+	 { "STQ2_START", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_QUEUE_THRESHOLDS[] = {
+	 { "ROQ_IB1_START", 0, 5, &umr_bitfield_default },
+	 { "ROQ_IB2_START", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_THRESHOLDS[] = {
+	 { "MEQ1_START", 0, 7, &umr_bitfield_default },
+	 { "MEQ2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_AVAIL[] = {
+	 { "ROQ_CNT_RING", 0, 10, &umr_bitfield_default },
+	 { "ROQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_AVAIL[] = {
+	 { "STQ_CNT", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ2_AVAIL[] = {
+	 { "ROQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_AVAIL[] = {
+	 { "MEQ_CNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CMD_INDEX[] = {
+	 { "CMD_INDEX", 0, 10, &umr_bitfield_default },
+	 { "CMD_ME_SEL", 12, 13, &umr_bitfield_default },
+	 { "CMD_QUEUE_SEL", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CMD_DATA[] = {
+	 { "CMD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_RB_STAT[] = {
+	 { "ROQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_IB1_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_IB2_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_STAT[] = {
+	 { "STQ_RPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_WR_STAT[] = {
+	 { "STQ_WPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_STAT[] = {
+	 { "MEQ_RPTR", 0, 9, &umr_bitfield_default },
+	 { "MEQ_WPTR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CEQ1_AVAIL[] = {
+	 { "CEQ_CNT_RING", 0, 10, &umr_bitfield_default },
+	 { "CEQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CEQ2_AVAIL[] = {
+	 { "CEQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_RB_STAT[] = {
+	 { "CEQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_IB1_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_IB2_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STAT_DEBUG[] = {
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ASSERTED", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ASSERTED", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ASSERTED", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG6[] = {
+	 { "debug_BASE", 0, 15, &umr_bitfield_default },
+	 { "debug_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VTX_VECT_EJECT_REG[] = {
+	 { "PRIM_COUNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_DATA_FIFO_DEPTH[] = {
+	 { "DMA_DATA_FIFO_DEPTH", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_REQ_FIFO_DEPTH[] = {
+	 { "DMA_REQ_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DRAW_INIT_FIFO_DEPTH[] = {
+	 { "DRAW_INIT_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_LAST_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+	 { "DST_STATE_ID", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_CACHE_INVALIDATION[] = {
+	 { "CACHE_INVALIDATION", 0, 1, &umr_bitfield_default },
+	 { "VS_NO_EXTRA_BUFFER", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INVLD_EN", 6, 7, &umr_bitfield_default },
+	 { "USE_GS_DONE", 9, 9, &umr_bitfield_default },
+	 { "DIS_RANGE_FULL_INVLD", 11, 11, &umr_bitfield_default },
+	 { "GS_LATE_ALLOC_EN", 12, 12, &umr_bitfield_default },
+	 { "STREAMOUT_FULL_FLUSH", 13, 13, &umr_bitfield_default },
+	 { "ES_LIMIT", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_RESET_DEBUG[] = {
+	 { "GS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "TESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "WD_DISABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DELAY[] = {
+	 { "SKIP_DELAY", 0, 7, &umr_bitfield_default },
+	 { "SE0_WD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "SE1_WD_DELAY", 11, 13, &umr_bitfield_default },
+	 { "SE2_WD_DELAY", 14, 16, &umr_bitfield_default },
+	 { "SE3_WD_DELAY", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_FIFO_DEPTHS[] = {
+	 { "VS_DEALLOC_TBL_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "RESERVED_0", 7, 7, &umr_bitfield_default },
+	 { "CLIPP_FIFO_DEPTH", 8, 21, &umr_bitfield_default },
+	 { "RESERVED_1", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERTEX_REUSE[] = {
+	 { "VERT_REUSE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MC_LAT_CNTL[] = {
+	 { "MC_TIME_STAMP_RES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_CNTL_STATUS[] = {
+	 { "IA_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IA_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "IA_DMA_REQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "IA_GRP_BUSY", 3, 3, &umr_bitfield_default },
+	 { "IA_ADC_BUSY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DEBUG_CNTL[] = {
+	 { "VGT_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "VGT_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_DEBUG_CNTL[] = {
+	 { "IA_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "IA_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_CNTL_STATUS[] = {
+	 { "VGT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VGT_OUT_INDX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "VGT_OUT_BUSY", 2, 2, &umr_bitfield_default },
+	 { "VGT_PT_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VGT_TE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGT_VR_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGT_PI_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGT_GS_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGT_HS_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VGT_TE11_BUSY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_DEBUG_CNTL[] = {
+	 { "WD_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "WD_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_CNTL_STATUS[] = {
+	 { "WD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "WD_SPL_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WD_SPL_DI_BUSY", 2, 2, &umr_bitfield_default },
+	 { "WD_ADC_BUSY", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_PRIM_CONFIG[] = {
+	 { "INACTIVE_IA", 16, 17, &umr_bitfield_default },
+	 { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_PRIM_CONFIG[] = {
+	 { "INACTIVE_IA", 16, 17, &umr_bitfield_default },
+	 { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_VMID_OVERRIDE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VMID", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_SYS_CONFIG[] = {
+	 { "DUAL_CORE_EN", 0, 0, &umr_bitfield_default },
+	 { "MAX_LS_HS_THDGRP", 1, 6, &umr_bitfield_default },
+	 { "ADC_EVENT_FILTER_DISABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_PIPE_CONTROL[] = {
+	 { "HYSTERESIS_CNT", 0, 12, &umr_bitfield_default },
+	 { "RESERVED", 13, 15, &umr_bitfield_default },
+	 { "CONTEXT_SUSPEND_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_SHADER_ARRAY_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SHADER_ARRAY_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_CONTROL[] = {
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "IA_SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_LS_HS_CONFIG[] = {
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_DEBUG_CNTL[] = {
+	 { "SU_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_CNTL_STATUS[] = {
+	 { "CL_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_ENHANCE[] = {
+	 { "CLIP_VTX_REORDER_ENA", 0, 0, &umr_bitfield_default },
+	 { "NUM_CLIP_SEQ", 1, 2, &umr_bitfield_default },
+	 { "CLIPPED_PRIM_SEQ_STALL", 3, 3, &umr_bitfield_default },
+	 { "VE_NAN_PROC_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "XTRA_DEBUG_REG_SEL", 5, 5, &umr_bitfield_default },
+	 { "ECO_SPARE3", 28, 28, &umr_bitfield_default },
+	 { "ECO_SPARE2", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_RESET_DEBUG[] = {
+	 { "CL_TRIV_DISC_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_CNTL_STATUS[] = {
+	 { "SU_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FIFO_DEPTH_CNTL[] = {
+	 { "DEPTH", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FORCE_EOV_MAX_CNTS[] = {
+	 { "FORCE_EOV_MAX_CLK_CNT", 0, 15, &umr_bitfield_default },
+	 { "FORCE_EOV_MAX_REZ_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FIFO_SIZE[] = {
+	 { "SC_FRONTEND_PRIM_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_BACKEND_PRIM_FIFO_SIZE", 6, 14, &umr_bitfield_default },
+	 { "SC_HIZ_TILE_FIFO_SIZE", 15, 20, &umr_bitfield_default },
+	 { "SC_EARLYZ_TILE_FIFO_SIZE", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_IF_FIFO_SIZE[] = {
+	 { "SC_DB_TILE_IF_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_DB_QUAD_IF_FIFO_SIZE", 6, 11, &umr_bitfield_default },
+	 { "SC_SPI_IF_FIFO_SIZE", 12, 17, &umr_bitfield_default },
+	 { "SC_BCI_IF_FIFO_SIZE", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DEBUG_CNTL[] = {
+	 { "SC_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_ENHANCE[] = {
+	 { "ENABLE_PA_SC_OUT_OF_ORDER", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_SC_DB_TILE_FIX", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_AA_MASK_FULL_FIX", 2, 2, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOCATIONS", 3, 3, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_SCISSOR_FIX", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_PW_BUBBLE_COLLAPSE", 6, 7, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PACKER", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_DUALGRAD_PERF_OPTIMIZATION", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_PRIM", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_SUPERTILE", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_TILE", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_PA_SC_GUIDANCE", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_MULTICYCLE_BUBBLE_FREEZE", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_POLY_MODE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS", 23, 23, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO", 25, 25, &umr_bitfield_default },
+	 { "OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT", 26, 26, &umr_bitfield_default },
+	 { "OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_EOP_LINE_STIPPLE_RESET", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_VPZ_EOP_LINE_STIPPLE_RESET", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG7[] = {
+	 { "debug_tfmmFifoEmpty", 0, 0, &umr_bitfield_default },
+	 { "debug_tfmmFifoFull", 1, 1, &umr_bitfield_default },
+	 { "hs_pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "hs_pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "hs_pipe1_rtr", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 15, &umr_bitfield_default },
+	 { "TF_addr", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CONFIG[] = {
+	 { "UNUSED", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_EN", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_SCA_BYPASS", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_IB_DEP_CHECK", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_SOFT_CLAUSE", 11, 11, &umr_bitfield_default },
+	 { "EARLY_TA_DONE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "DUA_FLAT_LOCK_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "DUA_LDS_BYPASS_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DUA_FLAT_LDS_PINGPONG_DISABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_CONFIG[] = {
+	 { "INST_CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DATA_CACHE_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MISS_FIFO_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "HIT_FIFO_DEPTH", 6, 6, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_MISS", 7, 7, &umr_bitfield_default },
+	 { "FORCE_IN_ORDER", 8, 8, &umr_bitfield_default },
+	 { "IDENTITY_HASH_BANK", 9, 9, &umr_bitfield_default },
+	 { "IDENTITY_HASH_SET", 10, 10, &umr_bitfield_default },
+	 { "PER_VMID_INV_DISABLE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_RANDOM_WAVE_PRI[] = {
+	 { "RET", 0, 6, &umr_bitfield_default },
+	 { "RUI", 7, 9, &umr_bitfield_default },
+	 { "RNG", 10, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_REG_CREDITS[] = {
+	 { "SRBM_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "CMD_CREDITS", 8, 11, &umr_bitfield_default },
+	 { "REG_BUSY", 28, 28, &umr_bitfield_default },
+	 { "SRBM_OVERFLOW", 29, 29, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 30, 30, &umr_bitfield_default },
+	 { "CMD_OVERFLOW", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FIFO_SIZES[] = {
+	 { "INTERRUPT_FIFO_SIZE", 0, 3, &umr_bitfield_default },
+	 { "TTRACE_FIFO_SIZE", 8, 11, &umr_bitfield_default },
+	 { "EXPORT_BUF_SIZE", 16, 17, &umr_bitfield_default },
+	 { "VMEM_DATA_FIFO_SIZE", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUSER_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "INTERRUPT_MSG_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH0", 4, 15, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH1", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_BASES[] = {
+	 { "PRIVATE_BASE", 0, 15, &umr_bitfield_default },
+	 { "SHARED_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_APE1_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_APE1_LIMIT[] = {
+	 { "LIMIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_CONFIG[] = {
+	 { "PTR32", 0, 0, &umr_bitfield_default },
+	 { "PRIVATE_ATC", 1, 1, &umr_bitfield_default },
+	 { "ALIGNMENT_MODE", 2, 3, &umr_bitfield_default },
+	 { "DEFAULT_MTYPE", 4, 6, &umr_bitfield_default },
+	 { "APE1_MTYPE", 7, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_POLICY[] = {
+	 { "DATA_L1_POLICY_0", 0, 0, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_1", 1, 1, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_2", 2, 2, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_3", 3, 3, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_4", 4, 4, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_5", 5, 5, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_6", 6, 6, &umr_bitfield_default },
+	 { "DATA_L1_POLICY_7", 7, 7, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_0", 8, 9, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_1", 10, 11, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_2", 12, 13, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_3", 14, 15, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_4", 16, 17, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_5", 18, 19, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_6", 20, 21, &umr_bitfield_default },
+	 { "DATA_L2_POLICY_7", 22, 23, &umr_bitfield_default },
+	 { "INST_L2_POLICY", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_VOLATILE[] = {
+	 { "DATA_L1", 0, 3, &umr_bitfield_default },
+	 { "DATA_L2", 4, 7, &umr_bitfield_default },
+	 { "INST_L2", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL2[] = {
+	 { "FIFO_LEVEL_GFX0", 0, 7, &umr_bitfield_default },
+	 { "FIFO_LEVEL_GFX1", 8, 15, &umr_bitfield_default },
+	 { "FIFO_LEVEL_IMMED", 16, 23, &umr_bitfield_default },
+	 { "FIFO_LEVEL_HOST", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL3[] = {
+	 { "FIFO_LEVEL_HOST_CMD", 0, 3, &umr_bitfield_default },
+	 { "FIFO_LEVEL_HOST_REG", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_INTERRUPT_AUTO_MASK[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_INTERRUPT_MSG_CTRL[] = {
+	 { "STALL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_REG_TIMESTAMP[] = {
+	 { "TIMESTAMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CMD_TIMESTAMP[] = {
+	 { "TIMESTAMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IND_INDEX[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "THREAD_ID", 6, 11, &umr_bitfield_default },
+	 { "AUTO_INCR", 12, 12, &umr_bitfield_default },
+	 { "FORCE_READ", 13, 13, &umr_bitfield_default },
+	 { "READ_TIMEOUT", 14, 14, &umr_bitfield_default },
+	 { "UNINDEXED", 15, 15, &umr_bitfield_default },
+	 { "INDEX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CMD[] = {
+	 { "CMD", 0, 2, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "CHECK_VMID", 7, 7, &umr_bitfield_default },
+	 { "TRAP_ID", 8, 10, &umr_bitfield_default },
+	 { "WAVE_ID", 16, 19, &umr_bitfield_default },
+	 { "SIMD_ID", 20, 21, &umr_bitfield_default },
+	 { "QUEUE_ID", 24, 26, &umr_bitfield_default },
+	 { "VM_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TIME_HI[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TIME_LO[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_VOP3_0_SDST_ENC[] = {
+	 { "VDST", 0, 7, &umr_bitfield_default },
+	 { "SDST", 8, 14, &umr_bitfield_default },
+	 { "OP", 17, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_MTBUF_1[] = {
+	 { "VADDR", 0, 7, &umr_bitfield_default },
+	 { "VDATA", 8, 15, &umr_bitfield_default },
+	 { "SRSRC", 16, 20, &umr_bitfield_default },
+	 { "SLC", 22, 22, &umr_bitfield_default },
+	 { "TFE", 23, 23, &umr_bitfield_default },
+	 { "SOFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_VOP3_0[] = {
+	 { "VDST", 0, 7, &umr_bitfield_default },
+	 { "ABS", 8, 10, &umr_bitfield_default },
+	 { "CLAMP", 11, 11, &umr_bitfield_default },
+	 { "OP", 17, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EXP_1[] = {
+	 { "VSRC0", 0, 7, &umr_bitfield_default },
+	 { "VSRC1", 8, 15, &umr_bitfield_default },
+	 { "VSRC2", 16, 23, &umr_bitfield_default },
+	 { "VSRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_SOP2[] = {
+	 { "SSRC0", 0, 7, &umr_bitfield_default },
+	 { "SSRC1", 8, 15, &umr_bitfield_default },
+	 { "SDST", 16, 22, &umr_bitfield_default },
+	 { "OP", 23, 29, &umr_bitfield_default },
+	 { "ENCODING", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_SIZE[] = {
+	 { "SIZE", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_MASK[] = {
+	 { "CU_SEL", 0, 4, &umr_bitfield_default },
+	 { "SH_SEL", 5, 5, &umr_bitfield_default },
+	 { "REG_STALL_EN", 7, 7, &umr_bitfield_default },
+	 { "SIMD_EN", 8, 11, &umr_bitfield_default },
+	 { "VM_ID_MASK", 12, 13, &umr_bitfield_default },
+	 { "SPI_STALL_EN", 14, 14, &umr_bitfield_default },
+	 { "SQ_STALL_EN", 15, 15, &umr_bitfield_default },
+	 { "RANDOM_SEED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK[] = {
+	 { "TOKEN_MASK", 0, 15, &umr_bitfield_default },
+	 { "REG_MASK", 16, 23, &umr_bitfield_default },
+	 { "REG_DROP_ON_STALL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_PERF_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_BASE2[] = {
+	 { "ADDR_HI", 0, 3, &umr_bitfield_default },
+	 { "ATC", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK2[] = {
+	 { "INST_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WPTR[] = {
+	 { "WPTR", 0, 29, &umr_bitfield_default },
+	 { "READ_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_STATUS[] = {
+	 { "FINISH_PENDING", 0, 9, &umr_bitfield_default },
+	 { "FINISH_DONE", 16, 25, &umr_bitfield_default },
+	 { "NEW_BUF", 29, 29, &umr_bitfield_default },
+	 { "BUSY", 30, 30, &umr_bitfield_default },
+	 { "FULL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_MODE[] = {
+	 { "MASK_PS", 0, 2, &umr_bitfield_default },
+	 { "MASK_VS", 3, 5, &umr_bitfield_default },
+	 { "MASK_GS", 6, 8, &umr_bitfield_default },
+	 { "MASK_ES", 9, 11, &umr_bitfield_default },
+	 { "MASK_HS", 12, 14, &umr_bitfield_default },
+	 { "MASK_LS", 15, 17, &umr_bitfield_default },
+	 { "MASK_CS", 18, 20, &umr_bitfield_default },
+	 { "MODE", 21, 22, &umr_bitfield_default },
+	 { "CAPTURE_MODE", 23, 24, &umr_bitfield_default },
+	 { "AUTOFLUSH_EN", 25, 25, &umr_bitfield_default },
+	 { "PRIV", 26, 26, &umr_bitfield_default },
+	 { "ISSUE_MASK", 27, 28, &umr_bitfield_default },
+	 { "TEST_MODE", 29, 29, &umr_bitfield_default },
+	 { "INTERRUPT_EN", 30, 30, &umr_bitfield_default },
+	 { "WRAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_CTRL[] = {
+	 { "RESET_BUFFER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_CNTR[] = {
+	 { "CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_HIWATER[] = {
+	 { "HIWATER", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_CTR_CTRL[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "LOAD", 1, 1, &umr_bitfield_default },
+	 { "CLEAR", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_ALU_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_TEX_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_ALU_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_TEX_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_SECDED_CNT[] = {
+	 { "INST_SEC", 0, 7, &umr_bitfield_default },
+	 { "INST_DED", 8, 15, &umr_bitfield_default },
+	 { "DATA_SEC", 16, 23, &umr_bitfield_default },
+	 { "DATA_DED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_SEC_CNT[] = {
+	 { "LDS_SEC", 0, 5, &umr_bitfield_default },
+	 { "SGPR_SEC", 8, 12, &umr_bitfield_default },
+	 { "VGPR_SEC", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DED_CNT[] = {
+	 { "LDS_DED", 0, 5, &umr_bitfield_default },
+	 { "SGPR_DED", 8, 12, &umr_bitfield_default },
+	 { "VGPR_DED", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DED_INFO[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "SOURCE", 6, 8, &umr_bitfield_default },
+	 { "VM_ID", 9, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "WAVE_ID", 10, 13, &umr_bitfield_default },
+	 { "SIMD_ID", 14, 15, &umr_bitfield_default },
+	 { "DATA_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID", 5, 8, &umr_bitfield_default },
+	 { "SIMD_ID", 9, 10, &umr_bitfield_default },
+	 { "PC_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "PIPE_ID", 5, 6, &umr_bitfield_default },
+	 { "ME_ID", 7, 8, &umr_bitfield_default },
+	 { "REG_ADDR", 9, 15, &umr_bitfield_default },
+	 { "DATA_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "CNTR_BANK", 10, 11, &umr_bitfield_default },
+	 { "CNTR0", 12, 24, &umr_bitfield_default },
+	 { "CNTR1_LO", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_WAVE_START[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "WAVE_ID", 10, 13, &umr_bitfield_default },
+	 { "SIMD_ID", 14, 15, &umr_bitfield_default },
+	 { "DISPATCHER", 16, 20, &umr_bitfield_default },
+	 { "VS_NO_ALLOC_OR_GROUPED", 21, 21, &umr_bitfield_default },
+	 { "COUNT", 22, 28, &umr_bitfield_default },
+	 { "TG_ID", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_EVENT[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "STAGE", 6, 8, &umr_bitfield_default },
+	 { "EVENT_TYPE", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID", 5, 8, &umr_bitfield_default },
+	 { "SIMD_ID", 9, 10, &umr_bitfield_default },
+	 { "SIZE", 11, 11, &umr_bitfield_default },
+	 { "INST_TYPE", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_CMN[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[] = {
+	 { "DATA_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[] = {
+	 { "TIME_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[] = {
+	 { "PC_HI", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[] = {
+	 { "CNTR1_HI", 0, 5, &umr_bitfield_default },
+	 { "CNTR2", 6, 18, &umr_bitfield_default },
+	 { "CNTR3", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 15, &umr_bitfield_default },
+	 { "STRIDE", 16, 29, &umr_bitfield_default },
+	 { "CACHE_SWIZZLE", 30, 30, &umr_bitfield_default },
+	 { "SWIZZLE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD2[] = {
+	 { "NUM_RECORDS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD3[] = {
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "NUM_FORMAT", 12, 14, &umr_bitfield_default },
+	 { "DATA_FORMAT", 15, 18, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 19, 20, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 21, 22, &umr_bitfield_default },
+	 { "ADD_TID_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "ATC", 24, 24, &umr_bitfield_default },
+	 { "HASH_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "HEAP", 26, 26, &umr_bitfield_default },
+	 { "MTYPE", 27, 29, &umr_bitfield_default },
+	 { "TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 7, &umr_bitfield_default },
+	 { "MIN_LOD", 8, 19, &umr_bitfield_default },
+	 { "DATA_FORMAT", 20, 25, &umr_bitfield_default },
+	 { "NUM_FORMAT", 26, 29, &umr_bitfield_default },
+	 { "MTYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD2[] = {
+	 { "WIDTH", 0, 13, &umr_bitfield_default },
+	 { "HEIGHT", 14, 27, &umr_bitfield_default },
+	 { "PERF_MOD", 28, 30, &umr_bitfield_default },
+	 { "INTERLACED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD3[] = {
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "BASE_LEVEL", 12, 15, &umr_bitfield_default },
+	 { "LAST_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "TILING_INDEX", 20, 24, &umr_bitfield_default },
+	 { "POW2_PAD", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 26, 26, &umr_bitfield_default },
+	 { "ATC", 27, 27, &umr_bitfield_default },
+	 { "TYPE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD4[] = {
+	 { "DEPTH", 0, 12, &umr_bitfield_default },
+	 { "PITCH", 13, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD5[] = {
+	 { "BASE_ARRAY", 0, 12, &umr_bitfield_default },
+	 { "LAST_ARRAY", 13, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD6[] = {
+	 { "MIN_LOD_WARN", 0, 11, &umr_bitfield_default },
+	 { "COUNTER_BANK_ID", 12, 19, &umr_bitfield_default },
+	 { "LOD_HDW_CNT_EN", 20, 20, &umr_bitfield_default },
+	 { "UNUNSED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD7[] = {
+	 { "UNUNSED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD0[] = {
+	 { "CLAMP_X", 0, 2, &umr_bitfield_default },
+	 { "CLAMP_Y", 3, 5, &umr_bitfield_default },
+	 { "CLAMP_Z", 6, 8, &umr_bitfield_default },
+	 { "MAX_ANISO_RATIO", 9, 11, &umr_bitfield_default },
+	 { "DEPTH_COMPARE_FUNC", 12, 14, &umr_bitfield_default },
+	 { "FORCE_UNNORMALIZED", 15, 15, &umr_bitfield_default },
+	 { "ANISO_THRESHOLD", 16, 18, &umr_bitfield_default },
+	 { "MC_COORD_TRUNC", 19, 19, &umr_bitfield_default },
+	 { "FORCE_DEGAMMA", 20, 20, &umr_bitfield_default },
+	 { "ANISO_BIAS", 21, 26, &umr_bitfield_default },
+	 { "TRUNC_COORD", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_CUBE_WRAP", 28, 28, &umr_bitfield_default },
+	 { "FILTER_MODE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD1[] = {
+	 { "MIN_LOD", 0, 11, &umr_bitfield_default },
+	 { "MAX_LOD", 12, 23, &umr_bitfield_default },
+	 { "PERF_MIP", 24, 27, &umr_bitfield_default },
+	 { "PERF_Z", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD2[] = {
+	 { "LOD_BIAS", 0, 13, &umr_bitfield_default },
+	 { "LOD_BIAS_SEC", 14, 19, &umr_bitfield_default },
+	 { "XY_MAG_FILTER", 20, 21, &umr_bitfield_default },
+	 { "XY_MIN_FILTER", 22, 23, &umr_bitfield_default },
+	 { "Z_FILTER", 24, 25, &umr_bitfield_default },
+	 { "MIP_FILTER", 26, 27, &umr_bitfield_default },
+	 { "MIP_POINT_PRECLAMP", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_LSB_CEIL", 29, 29, &umr_bitfield_default },
+	 { "FILTER_PREC_FIX", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD3[] = {
+	 { "BORDER_COLOR_PTR", 0, 11, &umr_bitfield_default },
+	 { "BORDER_COLOR_TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FLAT_SCRATCH_WORD0[] = {
+	 { "SIZE", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FLAT_SCRATCH_WORD1[] = {
+	 { "OFFSET", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG26[] = {
+	 { "cm_state0", 0, 1, &umr_bitfield_default },
+	 { "cm_state1", 2, 3, &umr_bitfield_default },
+	 { "cm_state2", 4, 5, &umr_bitfield_default },
+	 { "cm_state3", 6, 7, &umr_bitfield_default },
+	 { "cm_state4", 8, 9, &umr_bitfield_default },
+	 { "cm_state5", 10, 11, &umr_bitfield_default },
+	 { "cm_state6", 12, 13, &umr_bitfield_default },
+	 { "cm_state7", 14, 15, &umr_bitfield_default },
+	 { "cm_state8", 16, 17, &umr_bitfield_default },
+	 { "cm_state9", 18, 19, &umr_bitfield_default },
+	 { "cm_state10", 20, 21, &umr_bitfield_default },
+	 { "cm_state11", 22, 23, &umr_bitfield_default },
+	 { "cm_state12", 24, 25, &umr_bitfield_default },
+	 { "cm_state13", 26, 27, &umr_bitfield_default },
+	 { "cm_state14", 28, 29, &umr_bitfield_default },
+	 { "cm_state15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY[] = {
+	 { "POS_FREE_OR_VALIDS", 0, 0, &umr_bitfield_default },
+	 { "POS_REQUESTER_BUSY", 1, 1, &umr_bitfield_default },
+	 { "PA_SX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "POS_SCBD_BUSY", 3, 3, &umr_bitfield_default },
+	 { "POS_BANK3VAL3_BUSY", 4, 4, &umr_bitfield_default },
+	 { "POS_BANK3VAL2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "POS_BANK3VAL1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "POS_BANK3VAL0_BUSY", 7, 7, &umr_bitfield_default },
+	 { "POS_BANK2VAL3_BUSY", 8, 8, &umr_bitfield_default },
+	 { "POS_BANK2VAL2_BUSY", 9, 9, &umr_bitfield_default },
+	 { "POS_BANK2VAL1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "POS_BANK2VAL0_BUSY", 11, 11, &umr_bitfield_default },
+	 { "POS_BANK1VAL3_BUSY", 12, 12, &umr_bitfield_default },
+	 { "POS_BANK1VAL2_BUSY", 13, 13, &umr_bitfield_default },
+	 { "POS_BANK1VAL1_BUSY", 14, 14, &umr_bitfield_default },
+	 { "POS_BANK1VAL0_BUSY", 15, 15, &umr_bitfield_default },
+	 { "POS_BANK0VAL3_BUSY", 16, 16, &umr_bitfield_default },
+	 { "POS_BANK0VAL2_BUSY", 17, 17, &umr_bitfield_default },
+	 { "POS_BANK0VAL1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "POS_BANK0VAL0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "POS_INMUX_VALID", 20, 20, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ3", 21, 21, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ2", 22, 22, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ1", 23, 23, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ3", 24, 24, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ2", 25, 25, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ1", 26, 26, &umr_bitfield_default },
+	 { "PCCMD_VALID", 27, 27, &umr_bitfield_default },
+	 { "VDATA1_VALID", 28, 28, &umr_bitfield_default },
+	 { "VDATA0_VALID", 29, 29, &umr_bitfield_default },
+	 { "CMD_BUSYORVAL", 30, 30, &umr_bitfield_default },
+	 { "ADDR_BUSYORVAL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_2[] = {
+	 { "COL_SCBD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_REQ3_FREECNT_NE0", 1, 1, &umr_bitfield_default },
+	 { "COL_REQ3_IDLE", 2, 2, &umr_bitfield_default },
+	 { "COL_REQ3_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_REQ2_FREECNT_NE0", 4, 4, &umr_bitfield_default },
+	 { "COL_REQ2_IDLE", 5, 5, &umr_bitfield_default },
+	 { "COL_REQ2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_REQ1_FREECNT_NE0", 7, 7, &umr_bitfield_default },
+	 { "COL_REQ1_IDLE", 8, 8, &umr_bitfield_default },
+	 { "COL_REQ1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_REQ0_FREECNT_NE0", 10, 10, &umr_bitfield_default },
+	 { "COL_REQ0_IDLE", 11, 11, &umr_bitfield_default },
+	 { "COL_REQ0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_DBIF3_SENDFREE_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_DBIF3_FIFO_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_DBIF3_READ_VALID", 15, 15, &umr_bitfield_default },
+	 { "COL_DBIF2_SENDFREE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_DBIF2_FIFO_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_DBIF2_READ_VALID", 18, 18, &umr_bitfield_default },
+	 { "COL_DBIF1_SENDFREE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_DBIF1_FIFO_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_DBIF1_READ_VALID", 21, 21, &umr_bitfield_default },
+	 { "COL_DBIF0_SENDFREE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_DBIF0_FIFO_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_DBIF0_READ_VALID", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_3[] = {
+	 { "COL_BUFF3_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_4[] = {
+	 { "COL_BUFF1_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "RESERVED", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_1[] = {
+	 { "SX_DB_QUAD_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "DEBUG_DATA", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL[] = {
+	 { "GPR_WRITE_PRIORITY", 0, 20, &umr_bitfield_default },
+	 { "EXP_PRIORITY_ORDER", 21, 23, &umr_bitfield_default },
+	 { "ENABLE_SQG_TOP_EVENTS", 24, 24, &umr_bitfield_default },
+	 { "ENABLE_SQG_BOP_EVENTS", 25, 25, &umr_bitfield_default },
+	 { "RSRC_MGMT_RESET", 26, 26, &umr_bitfield_default },
+	 { "TTRACE_STALL_ALL", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_CNTL[] = {
+	 { "DEBUG_GRBM_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_THREAD_TYPE_SEL", 1, 3, &umr_bitfield_default },
+	 { "DEBUG_GROUP_SEL", 4, 9, &umr_bitfield_default },
+	 { "DEBUG_SIMD_SEL", 10, 15, &umr_bitfield_default },
+	 { "DEBUG_SH_SEL", 16, 16, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_0", 17, 17, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_1", 18, 18, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_2", 19, 19, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_3", 20, 20, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_4", 21, 21, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_5", 22, 22, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_6", 23, 23, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_7", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_PIPE_SEL", 25, 27, &umr_bitfield_default },
+	 { "DEBUG_REG_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL_1[] = {
+	 { "VTX_DONE_DELAY", 0, 3, &umr_bitfield_default },
+	 { "INTERP_ONE_PRIM_PER_ROW", 4, 4, &umr_bitfield_default },
+	 { "PC_LIMIT_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "PC_LIMIT_STRICT", 7, 7, &umr_bitfield_default },
+	 { "CRC_SIMD_ID_WADDR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_MODE", 9, 9, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_CNT", 10, 13, &umr_bitfield_default },
+	 { "PC_LIMIT_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_BUSY[] = {
+	 { "LS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "HS_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ES_BUSY", 2, 2, &umr_bitfield_default },
+	 { "GS_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "PS0_BUSY", 5, 5, &umr_bitfield_default },
+	 { "PS1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CSG_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CS0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "CS1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "CS2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "CS3_BUSY", 11, 11, &umr_bitfield_default },
+	 { "CS4_BUSY", 12, 12, &umr_bitfield_default },
+	 { "CS5_BUSY", 13, 13, &umr_bitfield_default },
+	 { "CS6_BUSY", 14, 14, &umr_bitfield_default },
+	 { "CS7_BUSY", 15, 15, &umr_bitfield_default },
+	 { "LDS_WR_CTL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "LDS_WR_CTL1_BUSY", 17, 17, &umr_bitfield_default },
+	 { "RSRC_ALLOC0_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RSRC_ALLOC1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "PC_DEALLOC_BUSY", 20, 20, &umr_bitfield_default },
+	 { "EVENT_CLCTR_BUSY", 21, 21, &umr_bitfield_default },
+	 { "GRBM_BUSY", 22, 22, &umr_bitfield_default },
+	 { "SPIS_BUSY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_CNTL[] = {
+	 { "SAMPLE_PERIOD", 0, 3, &umr_bitfield_default },
+	 { "EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_0[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_1[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_2[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_3[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_4[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_5[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_6[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_7[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_8[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_9[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_0[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_1[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_2[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_3[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_4[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_5[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_6[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_7[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_8[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_9[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_10[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_11[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_12[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_13[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_14[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_15[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_16[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_17[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_18[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_19[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_20[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_DEBUG[] = {
+	 { "START_VALUE", 0, 30, &umr_bitfield_default },
+	 { "OVERRIDE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SLAVE_DEBUG_BUSY[] = {
+	 { "LS_VTX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "HS_VTX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ES_VTX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "GS_VTX_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VS_VTX_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGPR_WC00_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGPR_WC01_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGPR_WC10_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGPR_WC11_BUSY", 8, 8, &umr_bitfield_default },
+	 { "SGPR_WC00_BUSY", 9, 9, &umr_bitfield_default },
+	 { "SGPR_WC01_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SGPR_WC02_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SGPR_WC03_BUSY", 12, 12, &umr_bitfield_default },
+	 { "SGPR_WC10_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SGPR_WC11_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SGPR_WC12_BUSY", 15, 15, &umr_bitfield_default },
+	 { "SGPR_WC13_BUSY", 16, 16, &umr_bitfield_default },
+	 { "WAVEBUFFER0_BUSY", 17, 17, &umr_bitfield_default },
+	 { "WAVEBUFFER1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "WAVE_WC0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "WAVE_WC1_BUSY", 20, 20, &umr_bitfield_default },
+	 { "EVENT_CNTL_BUSY", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_CTR_CTRL[] = {
+	 { "LOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_DATA_REG[] = {
+	 { "CNT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PG_ENABLE_STATIC_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDS_CREDITS[] = {
+	 { "DS_DATA_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "DS_CMD_CREDITS", 8, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SX_EXPORT_BUFFER_SIZES[] = {
+	 { "COLOR_BUFFER_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_BUFFER_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SX_SCOREBOARD_BUFFER_SIZES[] = {
+	 { "COLOR_SCOREBOARD_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_SCOREBOARD_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_STATUS[] = {
+	 { "ACTIVE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_0[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_1[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_2[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_3[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_4[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_5[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_6[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_7[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBCI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_GPR_MIN[] = {
+	 { "VGPR_MIN", 0, 5, &umr_bitfield_default },
+	 { "SGPR_MIN", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_GPR_MIN[] = {
+	 { "VGPR_MIN", 0, 5, &umr_bitfield_default },
+	 { "SGPR_MIN", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG30[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe0_tf_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe2_dr", 2, 2, &umr_bitfield_default },
+	 { "event_or_null_p0_q", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipe1_tf_rtr", 6, 6, &umr_bitfield_default },
+	 { "pipe2_rtr", 7, 7, &umr_bitfield_default },
+	 { "ttp_patch_fifo_full", 8, 8, &umr_bitfield_default },
+	 { "ttp_patch_fifo_empty", 9, 9, &umr_bitfield_default },
+	 { "ttp_tf0_fifo_empty", 10, 10, &umr_bitfield_default },
+	 { "ttp_tf1_fifo_empty", 11, 11, &umr_bitfield_default },
+	 { "ttp_tf2_fifo_empty", 12, 12, &umr_bitfield_default },
+	 { "ttp_tf3_fifo_empty", 13, 13, &umr_bitfield_default },
+	 { "ttp_tf4_fifo_empty", 14, 14, &umr_bitfield_default },
+	 { "ttp_tf5_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "tf_fetch_state_q", 16, 18, &umr_bitfield_default },
+	 { "last_tf_of_tg", 19, 19, &umr_bitfield_default },
+	 { "tf_pointer_p0_q", 20, 23, &umr_bitfield_default },
+	 { "dynamic_hs_p0_q", 24, 24, &umr_bitfield_default },
+	 { "first_fetch_of_tg_p0_q", 25, 25, &umr_bitfield_default },
+	 { "first_data_ret_of_req_p0_q", 26, 26, &umr_bitfield_default },
+	 { "first_data_chunk_invalid_p0_q", 27, 27, &umr_bitfield_default },
+	 { "tf_xfer_count_p2_q", 28, 29, &umr_bitfield_default },
+	 { "pipe4_dr", 30, 30, &umr_bitfield_default },
+	 { "pipe4_rtr", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_CNTL[] = {
+	 { "SYNC_PHASE_SH", 0, 1, &umr_bitfield_default },
+	 { "SYNC_PHASE_VC_SMX", 4, 5, &umr_bitfield_default },
+	 { "PAD_STALL_EN", 8, 8, &umr_bitfield_default },
+	 { "EXTEND_LDS_STALL", 9, 10, &umr_bitfield_default },
+	 { "LDS_STALL_PHASE_ADJUST", 11, 12, &umr_bitfield_default },
+	 { "PRECISION_COMPATIBILITY", 15, 15, &umr_bitfield_default },
+	 { "GATHER4_FLOAT_MODE", 16, 16, &umr_bitfield_default },
+	 { "LD_FLOAT_MODE", 18, 18, &umr_bitfield_default },
+	 { "GATHER4_DX9_MODE", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_POWER_THROTTLE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_STATUS[] = {
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CNTL[] = {
+	 { "TC_DATA_CREDIT", 13, 15, &umr_bitfield_default },
+	 { "ALIGNER_CREDIT", 16, 20, &umr_bitfield_default },
+	 { "TD_FIFO_CREDIT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CNTL_AUX[] = {
+	 { "SCOAL_DSWIZZLE_N", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 3, &umr_bitfield_default },
+	 { "ANISO_WEIGHT_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_RESERVED_010C[] = {
+	 { "Unused", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_STATUS[] = {
+	 { "FG_PFIFO_EMPTYB", 12, 12, &umr_bitfield_default },
+	 { "FG_LFIFO_EMPTYB", 13, 13, &umr_bitfield_default },
+	 { "FG_SFIFO_EMPTYB", 14, 14, &umr_bitfield_default },
+	 { "FL_PFIFO_EMPTYB", 16, 16, &umr_bitfield_default },
+	 { "FL_LFIFO_EMPTYB", 17, 17, &umr_bitfield_default },
+	 { "FL_SFIFO_EMPTYB", 18, 18, &umr_bitfield_default },
+	 { "FA_PFIFO_EMPTYB", 20, 20, &umr_bitfield_default },
+	 { "FA_LFIFO_EMPTYB", 21, 21, &umr_bitfield_default },
+	 { "FA_SFIFO_EMPTYB", 22, 22, &umr_bitfield_default },
+	 { "IN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "FG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "LA_BUSY", 26, 26, &umr_bitfield_default },
+	 { "FL_BUSY", 27, 27, &umr_bitfield_default },
+	 { "TA_BUSY", 28, 28, &umr_bitfield_default },
+	 { "FA_BUSY", 29, 29, &umr_bitfield_default },
+	 { "AL_BUSY", 30, 30, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_HIDDEN_PRIVATE_BASE_VMID[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_STATIC_MEM_CONFIG[] = {
+	 { "SWIZZLE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 1, 2, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 3, 4, &umr_bitfield_default },
+	 { "PRIVATE_MTYPE", 5, 7, &umr_bitfield_default },
+	 { "READ_ONLY_CNTL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CONFIG[] = {
+	 { "SH0_GPR_PHASE_SEL", 1, 2, &umr_bitfield_default },
+	 { "SH1_GPR_PHASE_SEL", 3, 4, &umr_bitfield_default },
+	 { "SH2_GPR_PHASE_SEL", 5, 6, &umr_bitfield_default },
+	 { "SH3_GPR_PHASE_SEL", 7, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CNTL_STATUS[] = {
+	 { "GDS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GRBM_WBUF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ORD_APP_BUSY", 2, 2, &umr_bitfield_default },
+	 { "DS_BANK_CONFLICT", 3, 3, &umr_bitfield_default },
+	 { "DS_ADDR_CONFLICT", 4, 4, &umr_bitfield_default },
+	 { "DS_WR_CLAMP", 5, 5, &umr_bitfield_default },
+	 { "DS_RD_CLAMP", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ENHANCE2[] = {
+	 { "MISC", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PROTECTION_FAULT[] = {
+	 { "WRITE_DIS", 0, 0, &umr_bitfield_default },
+	 { "FAULT_DETECTED", 1, 1, &umr_bitfield_default },
+	 { "GRBM", 2, 2, &umr_bitfield_default },
+	 { "SH_ID", 3, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "SIMD_ID", 10, 11, &umr_bitfield_default },
+	 { "WAVE_ID", 12, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VM_PROTECTION_FAULT[] = {
+	 { "WRITE_DIS", 0, 0, &umr_bitfield_default },
+	 { "FAULT_DETECTED", 1, 1, &umr_bitfield_default },
+	 { "GWS", 2, 2, &umr_bitfield_default },
+	 { "OA", 3, 3, &umr_bitfield_default },
+	 { "GRBM", 4, 4, &umr_bitfield_default },
+	 { "VMID", 8, 11, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_SECDED_CNT[] = {
+	 { "DED", 0, 15, &umr_bitfield_default },
+	 { "SEC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GRBM_SECDED_CNT[] = {
+	 { "DED", 0, 15, &umr_bitfield_default },
+	 { "SEC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_DED[] = {
+	 { "ME0_GFXHP3D_PIX_DED", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_DED", 1, 1, &umr_bitfield_default },
+	 { "ME0_CS_DED", 2, 2, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "ME1_PIPE0_DED", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_DED", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_DED", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_DED", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_DED", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_DED", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_DED", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_DED", 11, 11, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DEBUG_CNTL[] = {
+	 { "GDS_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+	 { "UNUSED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG31[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe0_rtr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_outer_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_inner_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe2_outer_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe2_inner_dr", 5, 5, &umr_bitfield_default },
+	 { "pipe3_outer_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe3_inner_dr", 7, 7, &umr_bitfield_default },
+	 { "pipe4_outer_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe4_inner_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe5_outer_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe5_inner_dr", 11, 11, &umr_bitfield_default },
+	 { "pipe2_outer_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe2_inner_rtr", 13, 13, &umr_bitfield_default },
+	 { "pipe3_outer_rtr", 14, 14, &umr_bitfield_default },
+	 { "pipe3_inner_rtr", 15, 15, &umr_bitfield_default },
+	 { "pipe4_outer_rtr", 16, 16, &umr_bitfield_default },
+	 { "pipe4_inner_rtr", 17, 17, &umr_bitfield_default },
+	 { "pipe5_outer_rtr", 18, 18, &umr_bitfield_default },
+	 { "pipe5_inner_rtr", 19, 19, &umr_bitfield_default },
+	 { "pg_con_outer_point1_rts", 20, 20, &umr_bitfield_default },
+	 { "pg_con_outer_point2_rts", 21, 21, &umr_bitfield_default },
+	 { "pg_con_inner_point1_rts", 22, 22, &umr_bitfield_default },
+	 { "pg_con_inner_point2_rts", 23, 23, &umr_bitfield_default },
+	 { "pg_patch_fifo_empty", 24, 24, &umr_bitfield_default },
+	 { "pg_edge_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "pg_inner3_perp_fifo_empty", 26, 26, &umr_bitfield_default },
+	 { "pg_patch_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "pg_edge_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "pg_inner_perp_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "outer_ring_done_q", 30, 30, &umr_bitfield_default },
+	 { "inner_ring_done_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG[] = {
+	 { "DEBUG_STENCIL_COMPRESS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_DEPTH_COMPRESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "FETCH_FULL_Z_TILE", 2, 2, &umr_bitfield_default },
+	 { "FETCH_FULL_STENCIL_TILE", 3, 3, &umr_bitfield_default },
+	 { "FORCE_Z_MODE", 4, 5, &umr_bitfield_default },
+	 { "DEBUG_FORCE_DEPTH_READ", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_FORCE_STENCIL_READ", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIZ_ENABLE", 8, 9, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE0", 10, 11, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE1", 12, 13, &umr_bitfield_default },
+	 { "DEBUG_FAST_Z_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_FAST_STENCIL_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_NOOP_CULL_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_SUMM_SQUADS", 17, 17, &umr_bitfield_default },
+	 { "DEPTH_CACHE_FORCE_MISS", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_FORCE_FULL_Z_RANGE", 19, 20, &umr_bitfield_default },
+	 { "NEVER_FREE_Z_ONLY", 21, 21, &umr_bitfield_default },
+	 { "ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_VPORT_ZPLANE_OPTIMIZATION", 23, 23, &umr_bitfield_default },
+	 { "DECOMPRESS_AFTER_N_ZPLANES", 24, 27, &umr_bitfield_default },
+	 { "ONE_FREE_IN_FLIGHT", 28, 28, &umr_bitfield_default },
+	 { "FORCE_MISS_IF_NOT_INFLIGHT", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_DEPTH_SURFACE_SYNC", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_HTILE_SURFACE_SYNC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG2[] = {
+	 { "ALLOW_COMPZ_BYTE_MASKING", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_TC_ZRANGE_L0_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_TC_MASK_L0_CACHE", 2, 2, &umr_bitfield_default },
+	 { "DTR_ROUND_ROBIN_ARB", 3, 3, &umr_bitfield_default },
+	 { "DTR_PREZ_STALLS_FOR_ETF_ROOM", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_PREZL_CB_STALL", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL_REZ", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_PREZL_CB_STALL_REZ", 8, 8, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 9, 13, &umr_bitfield_default },
+	 { "DISABLE_TILE_COVERED_FOR_PS_ITER", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_SUBTILE_GROUPING", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_HTILE_PAIRED_PIPES", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_NULL_EOT_FORWARDING", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_DTT_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_QUAD_COHERENCY_STALL", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_PREZ_OF_REZ_SUMM", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_PREZL_VIEWPORT_STALL", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_SINGLE_STENCIL_QUAD_SUMM", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_WRITE_STALL_ON_RDWR_CONFLICT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG3[] = {
+	 { "FORCE_DB_IS_GOOD", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_TL_SSO_NULL_SUPPRESSION", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_HIZ_ON_VPORT_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_COMP_Z", 5, 5, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_SRC_Z", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_TCP_CAM_BYPASS", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_ZCMP_DIRTY_SUPPRESSION", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_REDUNDANT_PLANE_FLUSHES_OPT", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_INCOHERENT_EQAA_READS", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_OP_Z_DATA_FORWARDING", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_BYPASS", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_WRITE_COMBINE", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_DIRECT_FEEDBACK", 15, 15, &umr_bitfield_default },
+	 { "ALLOW_RF2P_RW_COLLISION", 16, 16, &umr_bitfield_default },
+	 { "SLOW_PREZ_TO_A2M_OMASK_RATE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_OP_S_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_TC_UPDATE_WRITE_COMBINE", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_HZ_TC_WRITE_COMBINE", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_TC_MA_ROUND_ROBIN_ARB", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_RAM_READ_SUPPRESION_ON_FWD", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_EQAA_A2M_PERF_OPT", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_DI_DT_STALL", 25, 25, &umr_bitfield_default },
+	 { "ENABLE_DB_PROCESS_RESET", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_OVERRASTERIZATION_FIX", 27, 27, &umr_bitfield_default },
+	 { "DONT_INSERT_CONTEXT_SUSPEND", 28, 28, &umr_bitfield_default },
+	 { "DONT_DELETE_CONTEXT_SUSPEND", 29, 29, &umr_bitfield_default },
+	 { "DB_EXTRA_DEBUG3", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG4[] = {
+	 { "DISABLE_QC_Z_MASK_SUMMATION", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_QC_STENCIL_MASK_SUMMATION", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_RESUMM_TO_SINGLE_STENCIL", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL", 3, 3, &umr_bitfield_default },
+	 { "DB_EXTRA_DEBUG4", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_CREDIT_LIMIT[] = {
+	 { "DB_SC_TILE_CREDITS", 0, 4, &umr_bitfield_default },
+	 { "DB_SC_QUAD_CREDITS", 5, 9, &umr_bitfield_default },
+	 { "DB_CB_LQUAD_CREDITS", 10, 12, &umr_bitfield_default },
+	 { "DB_CB_TILE_CREDITS", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_WATERMARKS[] = {
+	 { "DEPTH_FREE", 0, 4, &umr_bitfield_default },
+	 { "DEPTH_FLUSH", 5, 10, &umr_bitfield_default },
+	 { "FORCE_SUMMARIZE", 11, 14, &umr_bitfield_default },
+	 { "DEPTH_PENDING_FREE", 15, 19, &umr_bitfield_default },
+	 { "DEPTH_CACHELINE_FREE", 20, 26, &umr_bitfield_default },
+	 { "EARLY_Z_PANIC_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "LATE_Z_PANIC_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "RE_Z_PANIC_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "AUTO_FLUSH_HTILE", 30, 30, &umr_bitfield_default },
+	 { "AUTO_FLUSH_QUAD", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SUBTILE_CONTROL[] = {
+	 { "MSAA1_X", 0, 1, &umr_bitfield_default },
+	 { "MSAA1_Y", 2, 3, &umr_bitfield_default },
+	 { "MSAA2_X", 4, 5, &umr_bitfield_default },
+	 { "MSAA2_Y", 6, 7, &umr_bitfield_default },
+	 { "MSAA4_X", 8, 9, &umr_bitfield_default },
+	 { "MSAA4_Y", 10, 11, &umr_bitfield_default },
+	 { "MSAA8_X", 12, 13, &umr_bitfield_default },
+	 { "MSAA8_Y", 14, 15, &umr_bitfield_default },
+	 { "MSAA16_X", 16, 17, &umr_bitfield_default },
+	 { "MSAA16_Y", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FREE_CACHELINES[] = {
+	 { "FREE_DTILE_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "FREE_PLANE_DEPTH", 7, 13, &umr_bitfield_default },
+	 { "FREE_Z_DEPTH", 14, 20, &umr_bitfield_default },
+	 { "FREE_HTILE_DEPTH", 21, 24, &umr_bitfield_default },
+	 { "QUAD_READ_REQS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FIFO_DEPTH1[] = {
+	 { "MI_RDREQ_FIFO_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "MI_WRREQ_FIFO_DEPTH", 5, 9, &umr_bitfield_default },
+	 { "MCC_DEPTH", 10, 15, &umr_bitfield_default },
+	 { "QC_DEPTH", 16, 20, &umr_bitfield_default },
+	 { "LTILE_PROBE_FIFO_DEPTH", 21, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FIFO_DEPTH2[] = {
+	 { "EQUAD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "ETILE_OP_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "LQUAD_FIFO_DEPTH", 15, 24, &umr_bitfield_default },
+	 { "LTILE_OP_FIFO_DEPTH", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RING_CONTROL[] = {
+	 { "COUNTER_CONTROL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_0[] = {
+	 { "BUSY_DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_1[] = {
+	 { "BUSY_DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_2[] = {
+	 { "BUSY_DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_3[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_4[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_5[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_6[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_7[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_8[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_9[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_A[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_B[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_C[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_D[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_E[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_F[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_BACKEND_MAP[] = {
+	 { "BACKEND_MAP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_GPU_ID[] = {
+	 { "GPU_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_DAISY_CHAIN[] = {
+	 { "RB_0", 0, 3, &umr_bitfield_default },
+	 { "RB_1", 4, 7, &umr_bitfield_default },
+	 { "RB_2", 8, 11, &umr_bitfield_default },
+	 { "RB_3", 12, 15, &umr_bitfield_default },
+	 { "RB_4", 16, 19, &umr_bitfield_default },
+	 { "RB_5", 20, 23, &umr_bitfield_default },
+	 { "RB_6", 24, 27, &umr_bitfield_default },
+	 { "RB_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE0[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE1[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE2[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE3[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE4[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE5[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE6[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE7[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE8[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE9[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE10[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE11[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE12[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE13[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE14[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE15[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE16[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE17[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE18[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE19[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE20[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE21[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE22[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE23[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE24[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE25[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE26[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE27[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE28[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE29[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE30[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE31[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE0[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE1[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE2[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE3[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE4[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE5[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE6[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE7[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE8[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE9[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE10[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE11[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE12[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE13[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE14[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE15[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_3[] = {
+	 { "DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL[] = {
+	 { "CM_CACHE_EVICT_POINT", 0, 3, &umr_bitfield_default },
+	 { "FC_CACHE_EVICT_POINT", 6, 9, &umr_bitfield_default },
+	 { "CC_CACHE_EVICT_POINT", 12, 15, &umr_bitfield_default },
+	 { "ALLOW_MRT_WITH_DUAL_SOURCE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_INTNORM_LE11BPC_CLAMPING", 18, 18, &umr_bitfield_default },
+	 { "FORCE_NEEDS_DST", 19, 19, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_TOGGLE", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_RESULT_EQ_DEST", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_FULL_WRITE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DONT_RD_DST", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_BYPASS", 25, 25, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DISCARD_PIXEL", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED", 27, 27, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT", 28, 28, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_CC_IB_SERIALIZER_STATE_OPT", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_1[] = {
+	 { "CM_CACHE_NUM_TAGS", 0, 4, &umr_bitfield_default },
+	 { "FC_CACHE_NUM_TAGS", 5, 10, &umr_bitfield_default },
+	 { "CC_CACHE_NUM_TAGS", 11, 16, &umr_bitfield_default },
+	 { "CM_TILE_FIFO_DEPTH", 17, 25, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_2[] = {
+	 { "CC_EVEN_ODD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "FC_RDLAT_TILE_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "FC_RDLAT_QUAD_FIFO_DEPTH", 15, 22, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_13[] = {
+	 { "TILE_INTFC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MU_BUSY", 1, 1, &umr_bitfield_default },
+	 { "TQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "AC_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CRW_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CACHE_CTRL_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MC_WR_PENDING", 6, 6, &umr_bitfield_default },
+	 { "FC_WR_PENDING", 7, 7, &umr_bitfield_default },
+	 { "FC_RD_PENDING", 8, 8, &umr_bitfield_default },
+	 { "EVICT_PENDING", 9, 9, &umr_bitfield_default },
+	 { "LAST_RD_ARB_WINNER", 10, 10, &umr_bitfield_default },
+	 { "MU_STATE", 11, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_14[] = {
+	 { "TILE_RETIREMENT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "FOP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LAT_BUSY", 2, 2, &umr_bitfield_default },
+	 { "CACHE_CTL_BUSY", 3, 3, &umr_bitfield_default },
+	 { "ADDR_BUSY", 4, 4, &umr_bitfield_default },
+	 { "MERGE_BUSY", 5, 5, &umr_bitfield_default },
+	 { "QUAD_BUSY", 6, 6, &umr_bitfield_default },
+	 { "TILE_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CLEAR_BUSY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_15[] = {
+	 { "SURF_SYNC_STATE", 0, 1, &umr_bitfield_default },
+	 { "SURF_SYNC_START", 2, 2, &umr_bitfield_default },
+	 { "SF_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "RB_BUSY", 5, 5, &umr_bitfield_default },
+	 { "DS_BUSY", 6, 6, &umr_bitfield_default },
+	 { "TB_BUSY", 7, 7, &umr_bitfield_default },
+	 { "IB_BUSY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_16[] = {
+	 { "MC_RDREQ_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "LAST_RD_GRANT_VEC", 6, 9, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDITS", 10, 15, &umr_bitfield_default },
+	 { "LAST_WR_GRANT_VEC", 16, 19, &umr_bitfield_default },
+	 { "CC_WRREQ_FIFO_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "FC_WRREQ_FIFO_EMPTY", 21, 21, &umr_bitfield_default },
+	 { "CM_WRREQ_FIFO_EMPTY", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_17[] = {
+	 { "CM_BUSY", 0, 0, &umr_bitfield_default },
+	 { "FC_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CC_BUSY", 2, 2, &umr_bitfield_default },
+	 { "BB_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MA_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CORE_SCLK_VLD", 5, 5, &umr_bitfield_default },
+	 { "REG_SCLK1_VLD", 6, 6, &umr_bitfield_default },
+	 { "REG_SCLK0_VLD", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_18[] = {
+	 { "NOT_USED", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TBA_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TBA_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TMA_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TMA_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG32[] = {
+	 { "first_ring_of_patch", 0, 0, &umr_bitfield_default },
+	 { "last_ring_of_patch", 1, 1, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring", 2, 2, &umr_bitfield_default },
+	 { "last_point_of_outer_edge", 3, 3, &umr_bitfield_default },
+	 { "last_edge_of_inner_ring", 4, 4, &umr_bitfield_default },
+	 { "last_point_of_inner_edge", 5, 5, &umr_bitfield_default },
+	 { "last_patch_of_tg_p0_q", 6, 6, &umr_bitfield_default },
+	 { "event_null_special_p0_q", 7, 7, &umr_bitfield_default },
+	 { "event_flag_p5_q", 8, 8, &umr_bitfield_default },
+	 { "first_point_of_patch_p5_q", 9, 9, &umr_bitfield_default },
+	 { "first_point_of_edge_p5_q", 10, 10, &umr_bitfield_default },
+	 { "last_patch_of_tg_p5_q", 11, 11, &umr_bitfield_default },
+	 { "tess_topology_p5_q", 12, 13, &umr_bitfield_default },
+	 { "pipe5_inner3_rtr", 14, 14, &umr_bitfield_default },
+	 { "pipe5_inner2_rtr", 15, 15, &umr_bitfield_default },
+	 { "pg_edge_fifo3_full", 16, 16, &umr_bitfield_default },
+	 { "pg_edge_fifo2_full", 17, 17, &umr_bitfield_default },
+	 { "pg_inner3_point_fifo_full", 18, 18, &umr_bitfield_default },
+	 { "pg_outer3_point_fifo_full", 19, 19, &umr_bitfield_default },
+	 { "pg_inner2_point_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "pg_outer2_point_fifo_full", 21, 21, &umr_bitfield_default },
+	 { "pg_inner_point_fifo_full", 22, 22, &umr_bitfield_default },
+	 { "pg_outer_point_fifo_full", 23, 23, &umr_bitfield_default },
+	 { "inner2_fifos_rtr", 24, 24, &umr_bitfield_default },
+	 { "inner_fifos_rtr", 25, 25, &umr_bitfield_default },
+	 { "outer_fifos_rtr", 26, 26, &umr_bitfield_default },
+	 { "fifos_rtr", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_M0[] = {
+	 { "M0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_EXEC_LO[] = {
+	 { "EXEC_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_EXEC_HI[] = {
+	 { "EXEC_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG33[] = {
+	 { "pipe0_patch_dr", 0, 0, &umr_bitfield_default },
+	 { "ring3_pipe1_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe2_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 4, 4, &umr_bitfield_default },
+	 { "ring2_pipe1_dr", 5, 5, &umr_bitfield_default },
+	 { "ring1_pipe1_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe2_rtr", 7, 7, &umr_bitfield_default },
+	 { "pipe3_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe3_rtr", 9, 9, &umr_bitfield_default },
+	 { "ring2_in_sync_q", 10, 10, &umr_bitfield_default },
+	 { "ring1_in_sync_q", 11, 11, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 12, 12, &umr_bitfield_default },
+	 { "ring3_in_sync_q", 13, 13, &umr_bitfield_default },
+	 { "tm_te11_event_rtr", 14, 14, &umr_bitfield_default },
+	 { "first_prim_of_patch_q", 15, 15, &umr_bitfield_default },
+	 { "con_prim_fifo_full", 16, 16, &umr_bitfield_default },
+	 { "con_vert_fifo_full", 17, 17, &umr_bitfield_default },
+	 { "con_prim_fifo_empty", 18, 18, &umr_bitfield_default },
+	 { "con_vert_fifo_empty", 19, 19, &umr_bitfield_default },
+	 { "last_patch_of_tg_p0_q", 20, 20, &umr_bitfield_default },
+	 { "ring3_valid_p2", 21, 21, &umr_bitfield_default },
+	 { "ring2_valid_p2", 22, 22, &umr_bitfield_default },
+	 { "ring1_valid_p2", 23, 23, &umr_bitfield_default },
+	 { "tess_type_p0_q", 24, 25, &umr_bitfield_default },
+	 { "tess_topology_p0_q", 26, 27, &umr_bitfield_default },
+	 { "te11_out_vert_gs_en", 28, 28, &umr_bitfield_default },
+	 { "con_ring3_busy", 29, 29, &umr_bitfield_default },
+	 { "con_ring2_busy", 30, 30, &umr_bitfield_default },
+	 { "con_ring1_busy", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG34[] = {
+	 { "con_state_q", 0, 3, &umr_bitfield_default },
+	 { "second_cycle_q", 4, 4, &umr_bitfield_default },
+	 { "process_tri_middle_p0_q", 5, 5, &umr_bitfield_default },
+	 { "process_tri_1st_2nd_half_p0_q", 6, 6, &umr_bitfield_default },
+	 { "process_tri_center_poly_p0_q", 7, 7, &umr_bitfield_default },
+	 { "pipe0_patch_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe0_edge_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe1_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 11, 11, &umr_bitfield_default },
+	 { "pipe0_edge_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe1_rtr", 13, 13, &umr_bitfield_default },
+	 { "outer_parity_p0_q", 14, 14, &umr_bitfield_default },
+	 { "parallel_parity_p0_q", 15, 15, &umr_bitfield_default },
+	 { "first_ring_of_patch_p0_q", 16, 16, &umr_bitfield_default },
+	 { "last_ring_of_patch_p0_q", 17, 17, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring_p0_q", 18, 18, &umr_bitfield_default },
+	 { "last_point_of_outer_ring_p1", 19, 19, &umr_bitfield_default },
+	 { "last_point_of_inner_ring_p1", 20, 20, &umr_bitfield_default },
+	 { "outer_edge_tf_eq_one_p0_q", 21, 21, &umr_bitfield_default },
+	 { "advance_outer_point_p1", 22, 22, &umr_bitfield_default },
+	 { "advance_inner_point_p1", 23, 23, &umr_bitfield_default },
+	 { "next_ring_is_rect_p0_q", 24, 24, &umr_bitfield_default },
+	 { "pipe1_outer1_rtr", 25, 25, &umr_bitfield_default },
+	 { "pipe1_outer2_rtr", 26, 26, &umr_bitfield_default },
+	 { "pipe1_inner1_rtr", 27, 27, &umr_bitfield_default },
+	 { "pipe1_inner2_rtr", 28, 28, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 29, 29, &umr_bitfield_default },
+	 { "pipe1_edge_rtr", 30, 30, &umr_bitfield_default },
+	 { "use_stored_inner_q_ring1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG35[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe1_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe0_rtr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_rtr", 3, 3, &umr_bitfield_default },
+	 { "tfreq_tg_fifo_empty", 4, 4, &umr_bitfield_default },
+	 { "tfreq_tg_fifo_full", 5, 5, &umr_bitfield_default },
+	 { "tf_data_fifo_busy_q", 6, 6, &umr_bitfield_default },
+	 { "tf_data_fifo_rtr_q", 7, 7, &umr_bitfield_default },
+	 { "tf_skid_fifo_empty", 8, 8, &umr_bitfield_default },
+	 { "tf_skid_fifo_full", 9, 9, &umr_bitfield_default },
+	 { "vgt_tc_rdreq_rtr_q", 10, 10, &umr_bitfield_default },
+	 { "last_req_of_tg_p2", 11, 11, &umr_bitfield_default },
+	 { "spi_vgt_hs_done_cnt_q", 12, 17, &umr_bitfield_default },
+	 { "event_flag_p1_q", 18, 18, &umr_bitfield_default },
+	 { "null_flag_p1_q", 19, 19, &umr_bitfield_default },
+	 { "tf_data_fifo_cnt_q", 20, 26, &umr_bitfield_default },
+	 { "second_tf_ret_data_q", 27, 27, &umr_bitfield_default },
+	 { "first_req_of_tg_p1_q", 28, 28, &umr_bitfield_default },
+	 { "VGT_TC_rdreq_send_out", 29, 29, &umr_bitfield_default },
+	 { "VGT_TC_rdnfo_stall_out", 30, 30, &umr_bitfield_default },
+	 { "TC_VGT_rdret_data_in", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_INVALIDATE[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_STATUS[] = {
+	 { "TCP_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CNTL[] = {
+	 { "FORCE_HIT", 0, 0, &umr_bitfield_default },
+	 { "FORCE_MISS", 1, 1, &umr_bitfield_default },
+	 { "L1_SIZE", 2, 3, &umr_bitfield_default },
+	 { "FLAT_BUF_HASH_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FLAT_BUF_CACHE_SWIZZLE", 5, 5, &umr_bitfield_default },
+	 { "FORCE_EOW_TOTAL_CNT", 15, 20, &umr_bitfield_default },
+	 { "FORCE_EOW_TAGRAM_CNT", 22, 27, &umr_bitfield_default },
+	 { "DISABLE_Z_MAP", 28, 28, &umr_bitfield_default },
+	 { "INV_ALL_VMIDS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CHAN_STEER_LO[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "CHAN3", 12, 15, &umr_bitfield_default },
+	 { "CHAN4", 16, 19, &umr_bitfield_default },
+	 { "CHAN5", 20, 23, &umr_bitfield_default },
+	 { "CHAN6", 24, 27, &umr_bitfield_default },
+	 { "CHAN7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CHAN_STEER_HI[] = {
+	 { "CHAN8", 0, 3, &umr_bitfield_default },
+	 { "CHAN9", 4, 7, &umr_bitfield_default },
+	 { "CHANA", 8, 11, &umr_bitfield_default },
+	 { "CHANB", 12, 15, &umr_bitfield_default },
+	 { "CHANC", 16, 19, &umr_bitfield_default },
+	 { "CHAND", 20, 23, &umr_bitfield_default },
+	 { "CHANE", 24, 27, &umr_bitfield_default },
+	 { "CHANF", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_ADDR_CONFIG[] = {
+	 { "NUM_TCC_BANKS", 0, 3, &umr_bitfield_default },
+	 { "NUM_BANKS", 4, 5, &umr_bitfield_default },
+	 { "COLHI_WIDTH", 6, 8, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CREDIT[] = {
+	 { "LFIFO_CREDIT", 0, 9, &umr_bitfield_default },
+	 { "REQ_FIFO_CREDIT", 16, 22, &umr_bitfield_default },
+	 { "TD_CREDIT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_BUFFER_ADDR_HASH_CNTL[] = {
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "BANK_BITS", 8, 10, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 16, 18, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_EDC_COUNTER[] = {
+	 { "SEC_COUNT", 0, 3, &umr_bitfield_default },
+	 { "DED_COUNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_LOAD_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_LOAD_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_STORE_POLICY[] = {
+	 { "POLICY_0", 0, 0, &umr_bitfield_default },
+	 { "POLICY_1", 1, 1, &umr_bitfield_default },
+	 { "POLICY_2", 2, 2, &umr_bitfield_default },
+	 { "POLICY_3", 3, 3, &umr_bitfield_default },
+	 { "POLICY_4", 4, 4, &umr_bitfield_default },
+	 { "POLICY_5", 5, 5, &umr_bitfield_default },
+	 { "POLICY_6", 6, 6, &umr_bitfield_default },
+	 { "POLICY_7", 7, 7, &umr_bitfield_default },
+	 { "POLICY_8", 8, 8, &umr_bitfield_default },
+	 { "POLICY_9", 9, 9, &umr_bitfield_default },
+	 { "POLICY_10", 10, 10, &umr_bitfield_default },
+	 { "POLICY_11", 11, 11, &umr_bitfield_default },
+	 { "POLICY_12", 12, 12, &umr_bitfield_default },
+	 { "POLICY_13", 13, 13, &umr_bitfield_default },
+	 { "POLICY_14", 14, 14, &umr_bitfield_default },
+	 { "POLICY_15", 15, 15, &umr_bitfield_default },
+	 { "POLICY_16", 16, 16, &umr_bitfield_default },
+	 { "POLICY_17", 17, 17, &umr_bitfield_default },
+	 { "POLICY_18", 18, 18, &umr_bitfield_default },
+	 { "POLICY_19", 19, 19, &umr_bitfield_default },
+	 { "POLICY_20", 20, 20, &umr_bitfield_default },
+	 { "POLICY_21", 21, 21, &umr_bitfield_default },
+	 { "POLICY_22", 22, 22, &umr_bitfield_default },
+	 { "POLICY_23", 23, 23, &umr_bitfield_default },
+	 { "POLICY_24", 24, 24, &umr_bitfield_default },
+	 { "POLICY_25", 25, 25, &umr_bitfield_default },
+	 { "POLICY_26", 26, 26, &umr_bitfield_default },
+	 { "POLICY_27", 27, 27, &umr_bitfield_default },
+	 { "POLICY_28", 28, 28, &umr_bitfield_default },
+	 { "POLICY_29", 29, 29, &umr_bitfield_default },
+	 { "POLICY_30", 30, 30, &umr_bitfield_default },
+	 { "POLICY_31", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_LOAD_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_LOAD_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_STORE_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_STORE_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_ATOMIC_POLICY[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_VOLATILE[] = {
+	 { "VOL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_VOLATILE[] = {
+	 { "VOL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_STATUS[] = {
+	 { "TCI_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_CNTL_1[] = {
+	 { "WBINVL1_NUM_CYCLES", 0, 15, &umr_bitfield_default },
+	 { "REQ_FIFO_DEPTH", 16, 23, &umr_bitfield_default },
+	 { "WDATA_RAM_DEPTH", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_CNTL_2[] = {
+	 { "L1_INVAL_ON_WBINVL2", 0, 0, &umr_bitfield_default },
+	 { "TCA_MAX_CREDIT", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_CTRL[] = {
+	 { "CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "RATE", 2, 3, &umr_bitfield_default },
+	 { "WRITEBACK_MARGIN", 4, 7, &umr_bitfield_default },
+	 { "SRC_FIFO_SIZE", 12, 15, &umr_bitfield_default },
+	 { "LATENCY_FIFO_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WB_OR_INV_ALL_VMIDS", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_EDC_COUNTER[] = {
+	 { "SEC_COUNT", 0, 3, &umr_bitfield_default },
+	 { "DED_COUNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_REDUNDANCY[] = {
+	 { "MC_SEL0", 0, 0, &umr_bitfield_default },
+	 { "MC_SEL1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_CTRL[] = {
+	 { "HOLE_TIMEOUT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_CTRL[] = {
+	 { "RATE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_PS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_PS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_PS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "WAVE_CNT_EN", 7, 7, &umr_bitfield_default },
+	 { "EXTRA_LDS_SIZE", 8, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_VS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_LATE_ALLOC_VS[] = {
+	 { "LIMIT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_VS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "SO_BASE0_EN", 8, 8, &umr_bitfield_default },
+	 { "SO_BASE1_EN", 9, 9, &umr_bitfield_default },
+	 { "SO_BASE2_EN", 10, 10, &umr_bitfield_default },
+	 { "SO_BASE3_EN", 11, 11, &umr_bitfield_default },
+	 { "SO_EN", 12, 12, &umr_bitfield_default },
+	 { "EXCP_EN", 13, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_GS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_GS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_GS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "EXCP_EN", 7, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES_GS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_ES[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_ES[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_ES[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_HS[] = {
+	 { "WAVE_LIMIT", 0, 5, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_HS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CACHE_CTL", 24, 26, &umr_bitfield_default },
+	 { "CDBG_USER", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_HS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 8, 8, &umr_bitfield_default },
+	 { "EXCP_EN", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_HS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_LS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_LS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CACHE_CTL", 26, 28, &umr_bitfield_default },
+	 { "CDBG_USER", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DISPATCH_INITIATOR[] = {
+	 { "COMPUTE_SHADER_EN", 0, 0, &umr_bitfield_default },
+	 { "PARTIAL_TG_EN", 1, 1, &umr_bitfield_default },
+	 { "FORCE_START_AT_000", 2, 2, &umr_bitfield_default },
+	 { "ORDERED_APPEND_ENBL", 3, 3, &umr_bitfield_default },
+	 { "ORDERED_APPEND_MODE", 4, 4, &umr_bitfield_default },
+	 { "USE_THREAD_DIMENSIONS", 5, 5, &umr_bitfield_default },
+	 { "ORDER_MODE", 6, 6, &umr_bitfield_default },
+	 { "DISPATCH_CACHE_CNTL", 7, 9, &umr_bitfield_default },
+	 { "SCALAR_L1_INV_VOL", 10, 10, &umr_bitfield_default },
+	 { "VECTOR_L1_INV_VOL", 11, 11, &umr_bitfield_default },
+	 { "DATA_ATC", 12, 12, &umr_bitfield_default },
+	 { "RESTORE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_X[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_Y[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_Z[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_X[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_Y[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_Z[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_X[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Y[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Z[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PIPELINESTAT_ENABLE[] = {
+	 { "PIPELINESTAT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PERFCOUNT_ENABLE[] = {
+	 { "PERFCOUNT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+	 { "INST_ATC", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TBA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TBA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_RSRC1[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "BULKY", 24, 24, &umr_bitfield_default },
+	 { "CDBG_USER", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_RSRC2[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "TGID_X_EN", 7, 7, &umr_bitfield_default },
+	 { "TGID_Y_EN", 8, 8, &umr_bitfield_default },
+	 { "TGID_Z_EN", 9, 9, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 10, 10, &umr_bitfield_default },
+	 { "TIDIG_COMP_CNT", 11, 12, &umr_bitfield_default },
+	 { "EXCP_EN_MSB", 13, 14, &umr_bitfield_default },
+	 { "LDS_SIZE", 15, 23, &umr_bitfield_default },
+	 { "EXCP_EN", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_VMID[] = {
+	 { "DATA", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESOURCE_LIMITS[] = {
+	 { "WAVES_PER_SH", 0, 9, &umr_bitfield_default },
+	 { "TG_PER_CU", 12, 15, &umr_bitfield_default },
+	 { "LOCK_THRESHOLD", 16, 21, &umr_bitfield_default },
+	 { "SIMD_DEST_CNTL", 22, 22, &umr_bitfield_default },
+	 { "FORCE_SIMD_DIST", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_COUNT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE0[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE1[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMPRING_SIZE[] = {
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE2[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE3[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_X[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_Y[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_Z[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_THREAD_TRACE_ENABLE[] = {
+	 { "THREAD_TRACE_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_MISC_RESERVED[] = {
+	 { "SEND_SEID", 0, 1, &umr_bitfield_default },
+	 { "RESERVED2", 2, 2, &umr_bitfield_default },
+	 { "RESERVED3", 3, 3, &umr_bitfield_default },
+	 { "RESERVED4", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG03[] = {
+	 { "clipsm0_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG3[] = {
+	 { "pipe_num_busy", 0, 10, &umr_bitfield_default },
+	 { "pipe0_busy_num", 11, 14, &umr_bitfield_default },
+	 { "spare", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG3[] = {
+	 { "rbiu_spl_dr_valid", 0, 0, &umr_bitfield_default },
+	 { "SPARE0", 1, 1, &umr_bitfield_default },
+	 { "pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "pipe1_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "wd_subdma_fifo_empty", 6, 6, &umr_bitfield_default },
+	 { "wd_subdma_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "dma_buf_type_p0_q", 8, 9, &umr_bitfield_default },
+	 { "dma_zero_indices_p0_q", 10, 10, &umr_bitfield_default },
+	 { "dma_req_path_p3_q", 11, 11, &umr_bitfield_default },
+	 { "dma_not_eop_p1_q", 12, 12, &umr_bitfield_default },
+	 { "out_of_range_p4", 13, 13, &umr_bitfield_default },
+	 { "last_sub_dma_p3_q", 14, 14, &umr_bitfield_default },
+	 { "last_rdreq_of_sub_dma_p4", 15, 15, &umr_bitfield_default },
+	 { "WD_IA_dma_send_d", 16, 16, &umr_bitfield_default },
+	 { "WD_IA_dma_rtr", 17, 17, &umr_bitfield_default },
+	 { "WD_IA1_dma_send_d", 18, 18, &umr_bitfield_default },
+	 { "WD_IA1_dma_rtr", 19, 19, &umr_bitfield_default },
+	 { "last_inst_of_dma_p2", 20, 20, &umr_bitfield_default },
+	 { "last_sd_of_inst_p2", 21, 21, &umr_bitfield_default },
+	 { "last_sd_of_dma_p2", 22, 22, &umr_bitfield_default },
+	 { "SPARE1", 23, 23, &umr_bitfield_default },
+	 { "WD_IA_dma_busy", 24, 24, &umr_bitfield_default },
+	 { "WD_IA1_dma_busy", 25, 25, &umr_bitfield_default },
+	 { "send_to_ia1_p3_q", 26, 26, &umr_bitfield_default },
+	 { "dma_wd_switch_on_eop_p3_q", 27, 27, &umr_bitfield_default },
+	 { "pipe3_dr", 28, 28, &umr_bitfield_default },
+	 { "pipe3_rtr", 29, 29, &umr_bitfield_default },
+	 { "wd_dma2draw_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "wd_dma2draw_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_CNTL[] = {
+	 { "POLICY", 8, 9, &umr_bitfield_default },
+	 { "VOL", 10, 10, &umr_bitfield_default },
+	 { "ATC", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_STAT[] = {
+	 { "BURST_COUNT", 0, 15, &umr_bitfield_default },
+	 { "TAGS_PENDING", 16, 23, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_ADDR_LO[] = {
+	 { "ADDR_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "BUF_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "BUF_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_WR[] = {
+	 { "RB_RPTR_WR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "OBSOLETE", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "OBSOLETE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL[] = {
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS[] = {
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DEVICE_ID[] = {
+	 { "DEVICE_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ENDIAN_SWAP[] = {
+	 { "ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_VMID[] = {
+	 { "RB0_VMID", 0, 3, &umr_bitfield_default },
+	 { "RB1_VMID", 8, 11, &umr_bitfield_default },
+	 { "RB2_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE0_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE1_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_RADDR[] = {
+	 { "ME_RAM_RADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_WADDR[] = {
+	 { "ME_RAM_WADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_DATA[] = {
+	 { "ME_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "RB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING0[] = {
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING1[] = {
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING2[] = {
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING0[] = {
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING1[] = {
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING2[] = {
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PWR_CNTL[] = {
+	 { "GFX_CLK_HALT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEM_SLP_CNTL[] = {
+	 { "CP_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "CP_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 7, &umr_bitfield_default },
+	 { "CP_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CP_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING0[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING1[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING2[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "REQUEST_CLIENT", 4, 7, &umr_bitfield_default },
+	 { "RING_ID", 10, 13, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_EDC_MODE[] = {
+	 { "FORCE_SEC_ON_DED", 16, 16, &umr_bitfield_default },
+	 { "DED_MODE", 20, 21, &umr_bitfield_default },
+	 { "PROP_FED", 29, 29, &umr_bitfield_default },
+	 { "BYPASS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_FETCHER_SOURCE[] = {
+	 { "ME_SRC", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_WPTR_POLL_CNTL[] = {
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+	 { "POLL_ACTIVE", 30, 30, &umr_bitfield_default },
+	 { "EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_WPTR_POLL_CNTL1[] = {
+	 { "QUEUE_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_INT_STAT_DEBUG[] = {
+	 { "DEQUEUE_REQUEST_INT_ASSERTED", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_INT_STAT_DEBUG[] = {
+	 { "DEQUEUE_REQUEST_INT_ASSERTED", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC1_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC2_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC1_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC2_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CONTEXT_CNTL[] = {
+	 { "ME0PIPE0_MAX_WD_CNTX", 0, 2, &umr_bitfield_default },
+	 { "ME0PIPE0_MAX_PIPE_CNTX", 4, 6, &umr_bitfield_default },
+	 { "ME0PIPE1_MAX_WD_CNTX", 16, 18, &umr_bitfield_default },
+	 { "ME0PIPE1_MAX_PIPE_CNTX", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MAX_CONTEXT[] = {
+	 { "MAX_CONTEXT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IQ_WAIT_TIME1[] = {
+	 { "IB_OFFLOAD", 0, 7, &umr_bitfield_default },
+	 { "ATOMIC_OFFLOAD", 8, 15, &umr_bitfield_default },
+	 { "WRM_OFFLOAD", 16, 23, &umr_bitfield_default },
+	 { "GWS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IQ_WAIT_TIME2[] = {
+	 { "QUE_SLEEP", 0, 7, &umr_bitfield_default },
+	 { "SCH_WAVE", 8, 15, &umr_bitfield_default },
+	 { "SEM_REARM", 16, 23, &umr_bitfield_default },
+	 { "DEQ_RETRY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID_RESET[] = {
+	 { "RESET_REQUEST", 0, 15, &umr_bitfield_default },
+	 { "RESET_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_CNTL[] = {
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_STATUS[] = {
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID_PREEMPT[] = {
+	 { "PREEMPT_REQUEST", 0, 15, &umr_bitfield_default },
+	 { "PREEMPT_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_CNTX_ID[] = {
+	 { "CNTX_ID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_STATUS[] = {
+	 { "DOORBELL_UPDATED", 0, 0, &umr_bitfield_default },
+	 { "DOORBELL_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CNTL[] = {
+	 { "RLC_ENABLE_F32", 0, 0, &umr_bitfield_default },
+	 { "FORCE_RETRY", 1, 1, &umr_bitfield_default },
+	 { "READ_CACHE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RLC_STEP_F32", 3, 3, &umr_bitfield_default },
+	 { "SOFT_RESET_DEBUG_MODE", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MC_CNTL[] = {
+	 { "WRREQ_SWAP", 0, 1, &umr_bitfield_default },
+	 { "WRREQ_TRAN", 2, 2, &umr_bitfield_default },
+	 { "WRREQ_PRIV", 3, 3, &umr_bitfield_default },
+	 { "WRNFO_STALL", 4, 4, &umr_bitfield_default },
+	 { "WRNFO_URG", 5, 8, &umr_bitfield_default },
+	 { "WRREQ_DW_IMASK", 9, 12, &umr_bitfield_default },
+	 { "RESERVED_B", 13, 19, &umr_bitfield_default },
+	 { "RDNFO_URG", 20, 23, &umr_bitfield_default },
+	 { "RDREQ_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RDREQ_TRAN", 26, 26, &umr_bitfield_default },
+	 { "RDREQ_PRIV", 27, 27, &umr_bitfield_default },
+	 { "RDNFO_STALL", 28, 28, &umr_bitfield_default },
+	 { "RESERVED", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_STAT[] = {
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "RLC_GPM_BUSY", 1, 1, &umr_bitfield_default },
+	 { "RLC_SPM_BUSY", 2, 2, &umr_bitfield_default },
+	 { "RESERVED", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SOFT_RESET_GPU[] = {
+	 { "SOFT_RESET_GPU", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MEM_SLP_CNTL[] = {
+	 { "RLC_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "RLC_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 7, &umr_bitfield_default },
+	 { "RLC_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "RLC_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTR_MAX[] = {
+	 { "LB_CNTR_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTL[] = {
+	 { "LOAD_BALANCE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LB_CNT_CP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LB_CNT_SPIM_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "LB_CNT_REG_INC", 3, 3, &umr_bitfield_default },
+	 { "CU_MASK_USED_OFF_HYST", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTR_INIT[] = {
+	 { "LB_CNTR_INIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LOAD_BALANCE_CNTR[] = {
+	 { "RLC_LOAD_BALANCE_CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SAVE_AND_RESTORE_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DRIVER_CPDMA_STATUS[] = {
+	 { "DRIVER_REQUEST", 0, 0, &umr_bitfield_default },
+	 { "RESERVED1", 1, 3, &umr_bitfield_default },
+	 { "DRIVER_ACK", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_JUMP_TABLE_RESTORE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_DELAY_2[] = {
+	 { "SERDES_TIMEOUT_VALUE", 0, 7, &umr_bitfield_default },
+	 { "SERDES_CMD_DELAY", 8, 15, &umr_bitfield_default },
+	 { "PERCU_TIMEOUT_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_LSB[] = {
+	 { "GPU_CLOCKS_LSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_MSB[] = {
+	 { "GPU_CLOCKS_MSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CAPTURE_GPU_CLOCK_COUNT[] = {
+	 { "CAPTURE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_UCODE_CNTL[] = {
+	 { "RLC_UCODE_FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_STAT[] = {
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_STATUS", 1, 1, &umr_bitfield_default },
+	 { "GFX_CLOCK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "GFX_LS_STATUS", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_32_RES_SEL[] = {
+	 { "RES_SEL", 0, 5, &umr_bitfield_default },
+	 { "RESERVED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_32[] = {
+	 { "GPU_CLOCK_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_CNTL[] = {
+	 { "GFX_POWER_GATING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_GATING_SRC", 1, 1, &umr_bitfield_default },
+	 { "DYN_PER_CU_PG_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "STATIC_PER_CU_PG_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 15, &umr_bitfield_default },
+	 { "CHUB_HANDSHAKE_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PU_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PD_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "RESERVED1", 19, 23, &umr_bitfield_default },
+	 { "PG_ERROR_STATUS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_THREAD_PRIORITY[] = {
+	 { "THREAD0_PRIORITY", 0, 7, &umr_bitfield_default },
+	 { "THREAD1_PRIORITY", 8, 15, &umr_bitfield_default },
+	 { "THREAD2_PRIORITY", 16, 23, &umr_bitfield_default },
+	 { "THREAD3_PRIORITY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_THREAD_ENABLE[] = {
+	 { "THREAD0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "THREAD1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "THREAD2_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "THREAD3_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_VMID_THREAD0[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_VMID_THREAD1[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGTT_MGCG_OVERRIDE[] = {
+	 { "OVERRIDE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGCG_CGLS_CTRL[] = {
+	 { "CGCG_EN", 0, 0, &umr_bitfield_default },
+	 { "CGLS_EN", 1, 1, &umr_bitfield_default },
+	 { "CGLS_REP_COMPANSAT_DELAY", 2, 7, &umr_bitfield_default },
+	 { "CGCG_GFX_IDLE_THRESHOLD", 8, 26, &umr_bitfield_default },
+	 { "CGCG_CONTROLLER", 27, 27, &umr_bitfield_default },
+	 { "CGCG_REG_CTRL", 28, 28, &umr_bitfield_default },
+	 { "SLEEP_MODE", 29, 30, &umr_bitfield_default },
+	 { "SPARE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGCG_RAMP_CTRL[] = {
+	 { "DOWN_DIV_START_UNIT", 0, 3, &umr_bitfield_default },
+	 { "DOWN_DIV_STEP_UNIT", 4, 7, &umr_bitfield_default },
+	 { "UP_DIV_START_UNIT", 8, 11, &umr_bitfield_default },
+	 { "UP_DIV_STEP_UNIT", 12, 15, &umr_bitfield_default },
+	 { "STEP_DELAY_CNT", 16, 27, &umr_bitfield_default },
+	 { "STEP_DELAY_UNIT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DYN_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DYN_PG_REQUEST[] = {
+	 { "PG_REQUEST_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_DELAY[] = {
+	 { "POWER_UP_DELAY", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CMD_PROPAGATE_DELAY", 16, 23, &umr_bitfield_default },
+	 { "MEM_SLEEP_DELAY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CU_STATUS[] = {
+	 { "WORK_PENDING", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_INIT_CU_MASK[] = {
+	 { "INIT_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[] = {
+	 { "ALWAYS_ACTIVE_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_PARAMS[] = {
+	 { "SKIP_L2_CHECK", 0, 0, &umr_bitfield_default },
+	 { "FIFO_SAMPLES", 1, 7, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLES", 8, 15, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_THREAD1_DELAY[] = {
+	 { "CU_IDEL_DELAY", 0, 7, &umr_bitfield_default },
+	 { "LBPW_INNER_LOOP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LBPW_OUTER_LOOP_DELAY", 16, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_ALWAYS_ON_CU_MASK[] = {
+	 { "AON_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MAX_PG_CU[] = {
+	 { "MAX_POWERED_UP_CU", 0, 7, &umr_bitfield_default },
+	 { "SPARE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_AUTO_PG_CTRL[] = {
+	 { "AUTO_PG_EN", 0, 0, &umr_bitfield_default },
+	 { "AUTO_GRBM_REG_SAVE_ON_IDLE_EN", 1, 1, &umr_bitfield_default },
+	 { "AUTO_WAKE_UP_EN", 2, 2, &umr_bitfield_default },
+	 { "GRBM_REG_SAVE_GFX_IDLE_THRESHOLD", 3, 18, &umr_bitfield_default },
+	 { "PG_AFTER_GRBM_REG_SAVE_THRESHOLD", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_GRBM_REG_SAVE_CTRL[] = {
+	 { "START_GRBM_REG_SAVE", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_PG_CTRL[] = {
+	 { "START_PG", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_PG_WAKE_UP_CTRL[] = {
+	 { "START_PG_WAKE_UP", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_MASTER_INDEX[] = {
+	 { "CU_ID", 0, 3, &umr_bitfield_default },
+	 { "SH_ID", 4, 5, &umr_bitfield_default },
+	 { "SE_ID", 6, 8, &umr_bitfield_default },
+	 { "SE_NONCU_ID", 9, 9, &umr_bitfield_default },
+	 { "SE_NONCU", 10, 10, &umr_bitfield_default },
+	 { "NON_SE", 11, 13, &umr_bitfield_default },
+	 { "DATA_REG_ID", 14, 15, &umr_bitfield_default },
+	 { "SPARE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_CU_MASTER_MASK[] = {
+	 { "MASTER_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_NONCU_MASTER_MASK[] = {
+	 { "SE_MASTER_MASK", 0, 15, &umr_bitfield_default },
+	 { "GC_MASTER_MASK", 16, 16, &umr_bitfield_default },
+	 { "TC0_MASTER_MASK", 17, 17, &umr_bitfield_default },
+	 { "TC1_MASTER_MASK", 18, 18, &umr_bitfield_default },
+	 { "SPARE0_MASTER_MASK", 19, 19, &umr_bitfield_default },
+	 { "SPARE1_MASTER_MASK", 20, 20, &umr_bitfield_default },
+	 { "SPARE2_MASTER_MASK", 21, 21, &umr_bitfield_default },
+	 { "SPARE3_MASTER_MASK", 22, 22, &umr_bitfield_default },
+	 { "RESERVED", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_CTRL[] = {
+	 { "BPM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE_COMMAND", 12, 12, &umr_bitfield_default },
+	 { "READ_COMMAND", 13, 13, &umr_bitfield_default },
+	 { "RESERVED_1", 14, 15, &umr_bitfield_default },
+	 { "CGLS_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "CGLS_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "CGLS_ON", 18, 18, &umr_bitfield_default },
+	 { "CGLS_OFF", 19, 19, &umr_bitfield_default },
+	 { "CGCG_OVERRIDE_0", 20, 20, &umr_bitfield_default },
+	 { "CGCG_OVERRIDE_1", 21, 21, &umr_bitfield_default },
+	 { "MGCG_OVERRIDE_0", 22, 22, &umr_bitfield_default },
+	 { "MGCG_OVERRIDE_1", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_2", 24, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_CU_MASTER_BUSY[] = {
+	 { "BUSY_BUSY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_NONCU_MASTER_BUSY[] = {
+	 { "SE_MASTER_BUSY", 0, 15, &umr_bitfield_default },
+	 { "GC_MASTER_BUSY", 16, 16, &umr_bitfield_default },
+	 { "TC0_MASTER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "TC1_MASTER_BUSY", 18, 18, &umr_bitfield_default },
+	 { "SPARE0_MASTER_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SPARE1_MASTER_BUSY", 20, 20, &umr_bitfield_default },
+	 { "SPARE2_MASTER_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SPARE3_MASTER_BUSY", 22, 22, &umr_bitfield_default },
+	 { "RESERVED", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_CU_PD_TIMEOUT[] = {
+	 { "TIMEOUT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_SCRATCH_ADDR[] = {
+	 { "ADDR", 0, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_SCRATCH_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_STATIC_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_PERF_COUNT_0[] = {
+	 { "FEATURE_SEL", 0, 3, &umr_bitfield_default },
+	 { "SE_INDEX", 4, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 11, &umr_bitfield_default },
+	 { "CU_INDEX", 12, 15, &umr_bitfield_default },
+	 { "EVENT_SEL", 16, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 19, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_PERF_COUNT_1[] = {
+	 { "FEATURE_SEL", 0, 3, &umr_bitfield_default },
+	 { "SE_INDEX", 4, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 11, &umr_bitfield_default },
+	 { "CU_INDEX", 12, 15, &umr_bitfield_default },
+	 { "EVENT_SEL", 16, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 19, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_VMID[] = {
+	 { "RLC_SPM_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_INT_CNTL[] = {
+	 { "RLC_SPM_INT_CNTL", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_INT_STATUS[] = {
+	 { "RLC_SPM_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 14, &umr_bitfield_default },
+	 { "RLC_SPM_DEBUG_MODE", 15, 15, &umr_bitfield_default },
+	 { "RLC_SPM_NUM_SAMPLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_LOG_ADDR[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_LOG_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_LOG_CONT[] = {
+	 { "CONT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPR_REG1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SAFE_MODE[] = {
+	 { "REQ", 0, 0, &umr_bitfield_default },
+	 { "MESSAGE", 1, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPR_REG2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_PRIORITY[] = {
+	 { "PIPE_ORDER_TS0", 0, 2, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS1", 3, 5, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS2", 6, 8, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS3", 9, 11, &umr_bitfield_default },
+	 { "TS0_DUR_MULT", 12, 13, &umr_bitfield_default },
+	 { "TS1_DUR_MULT", 14, 15, &umr_bitfield_default },
+	 { "TS2_DUR_MULT", 16, 17, &umr_bitfield_default },
+	 { "TS3_DUR_MULT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_CYCLES_0[] = {
+	 { "TS0_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS1_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_CYCLES_1[] = {
+	 { "TS2_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS3_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_GFX[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_HP3D[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_CS0[] = {
+	 { "PIPE0", 0, 7, &umr_bitfield_default },
+	 { "PIPE1", 8, 15, &umr_bitfield_default },
+	 { "PIPE2", 16, 23, &umr_bitfield_default },
+	 { "PIPE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_CS1[] = {
+	 { "PIPE0", 0, 7, &umr_bitfield_default },
+	 { "PIPE1", 8, 15, &umr_bitfield_default },
+	 { "PIPE2", 16, 23, &umr_bitfield_default },
+	 { "PIPE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_GFX[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_HP3D[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS0[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS1[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS2[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS3[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS4[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS5[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS6[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS7[] = {
+	 { "VALUE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_WAVE_CNTL[] = {
+	 { "STALL_RA", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_CONFIG[] = {
+	 { "ME_SEL", 0, 1, &umr_bitfield_default },
+	 { "PIPE_SEL", 2, 3, &umr_bitfield_default },
+	 { "QUEUE_SEL", 4, 6, &umr_bitfield_default },
+	 { "ME_MATCH", 7, 7, &umr_bitfield_default },
+	 { "PIPE_MATCH", 8, 8, &umr_bitfield_default },
+	 { "QUEUE_MATCH", 9, 9, &umr_bitfield_default },
+	 { "TRAP_EN", 15, 15, &umr_bitfield_default },
+	 { "VMID_SEL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_MASK[] = {
+	 { "EXCP_EN", 0, 8, &umr_bitfield_default },
+	 { "REPLACE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_DATA0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_DATA1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESET_DEBUG[] = {
+	 { "DISABLE_GFX_RESET", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_PER_VMID", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_ALL_VMID", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_RESOURCE", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_PRIORITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_COMPUTE_QUEUE_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_0[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_1[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_2[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_3[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_4[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_5[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_6[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_7[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_8[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_9[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_0[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_1[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_2[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_3[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_4[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_5[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_6[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_7[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_8[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_9[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_10[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_11[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_10[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_11[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_ROQ_OFFSETS[] = {
+	 { "IQ_OFFSET", 0, 2, &umr_bitfield_default },
+	 { "PQ_OFFSET", 8, 13, &umr_bitfield_default },
+	 { "IB_OFFSET", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_EOP_BASE_ADDR[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_EOP_BASE_ADDR_HI[] = {
+	 { "BASE_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_EOP_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_EOP_CONTROL[] = {
+	 { "EOP_SIZE", 0, 5, &umr_bitfield_default },
+	 { "PROCESSING_EOP", 8, 8, &umr_bitfield_default },
+	 { "PROCESSING_QID", 9, 11, &umr_bitfield_default },
+	 { "PROCESS_EOP_EN", 12, 12, &umr_bitfield_default },
+	 { "PROCESSING_EOPIB", 13, 13, &umr_bitfield_default },
+	 { "PROCESS_EOPIB_EN", 14, 14, &umr_bitfield_default },
+	 { "EOP_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "EOP_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "PEND_Q_SEM", 28, 30, &umr_bitfield_default },
+	 { "PEND_SIG_SEM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_BASE_ADDR[] = {
+	 { "BASE_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_BASE_ADDR_HI[] = {
+	 { "BASE_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ACTIVE[] = {
+	 { "ACTIVE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "IB_VMID", 8, 11, &umr_bitfield_default },
+	 { "VQID", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PERSISTENT_STATE[] = {
+	 { "PRELOAD_REQ", 0, 0, &umr_bitfield_default },
+	 { "PRELOAD_SIZE", 8, 17, &umr_bitfield_default },
+	 { "DISP_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PIPE_PRIORITY[] = {
+	 { "PIPE_PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_QUEUE_PRIORITY[] = {
+	 { "PRIORITY_LEVEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_QUANTUM[] = {
+	 { "QUANTUM_EN", 0, 0, &umr_bitfield_default },
+	 { "QUANTUM_SCALE", 4, 4, &umr_bitfield_default },
+	 { "QUANTUM_DURATION", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_BASE_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR[] = {
+	 { "CONSUMED_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR_REPORT_ADDR[] = {
+	 { "RPTR_REPORT_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[] = {
+	 { "RPTR_REPORT_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR_POLL_ADDR[] = {
+	 { "WPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[] = {
+	 { "WPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_DOORBELL_CONTROL[] = {
+	 { "DOORBELL_OFFSET", 2, 22, &umr_bitfield_default },
+	 { "DOORBELL_SOURCE", 28, 28, &umr_bitfield_default },
+	 { "DOORBELL_SCHD_HIT", 29, 29, &umr_bitfield_default },
+	 { "DOORBELL_EN", 30, 30, &umr_bitfield_default },
+	 { "DOORBELL_HIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_CONTROL[] = {
+	 { "QUEUE_SIZE", 0, 5, &umr_bitfield_default },
+	 { "RPTR_BLOCK_SIZE", 8, 13, &umr_bitfield_default },
+	 { "ENDIAN_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MIN_AVAIL_SIZE", 20, 21, &umr_bitfield_default },
+	 { "PQ_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "PQ_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "NO_UPDATE_RPTR", 27, 27, &umr_bitfield_default },
+	 { "UNORD_DISPATCH", 28, 28, &umr_bitfield_default },
+	 { "ROQ_PQ_IB_FLIP", 29, 29, &umr_bitfield_default },
+	 { "PRIV_STATE", 30, 30, &umr_bitfield_default },
+	 { "KMD_QUEUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_BASE_ADDR[] = {
+	 { "IB_BASE_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_BASE_ADDR_HI[] = {
+	 { "IB_BASE_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_RPTR[] = {
+	 { "CONSUMED_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_CONTROL[] = {
+	 { "IB_SIZE", 0, 19, &umr_bitfield_default },
+	 { "MIN_IB_AVAIL_SIZE", 20, 21, &umr_bitfield_default },
+	 { "IB_ATC", 23, 23, &umr_bitfield_default },
+	 { "IB_CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "IB_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "PROCESSING_IB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IQ_TIMER[] = {
+	 { "WAIT_TIME", 0, 7, &umr_bitfield_default },
+	 { "RETRY_TYPE", 8, 10, &umr_bitfield_default },
+	 { "INTERRUPT_TYPE", 12, 13, &umr_bitfield_default },
+	 { "INTERRUPT_SIZE", 16, 21, &umr_bitfield_default },
+	 { "IQ_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "IQ_VOLATILE", 26, 26, &umr_bitfield_default },
+	 { "PROCESS_IQ_EN", 29, 29, &umr_bitfield_default },
+	 { "PROCESSING_IQ", 30, 30, &umr_bitfield_default },
+	 { "ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IQ_RPTR[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_DEQUEUE_REQUEST[] = {
+	 { "DEQUEUE_REQ", 0, 1, &umr_bitfield_default },
+	 { "IQ_REQ_PEND", 4, 4, &umr_bitfield_default },
+	 { "DEQUEUE_INT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_DMA_OFFLOAD[] = {
+	 { "DMA_OFFLOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_SEMA_CMD[] = {
+	 { "RETRY", 0, 0, &umr_bitfield_default },
+	 { "RESULT", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_MSG_TYPE[] = {
+	 { "ACTION", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC0_PREOP_LO[] = {
+	 { "ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC0_PREOP_HI[] = {
+	 { "ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC1_PREOP_LO[] = {
+	 { "ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC1_PREOP_HI[] = {
+	 { "ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_SCHEDULER0[] = {
+	 { "DEQUEUE_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DEQUEUE_RETRY_CNT", 2, 3, &umr_bitfield_default },
+	 { "RSV_5_4", 4, 5, &umr_bitfield_default },
+	 { "QUEUE_RUN_ONCE", 6, 6, &umr_bitfield_default },
+	 { "SCRATCH_RAM_INIT", 7, 7, &umr_bitfield_default },
+	 { "TCL2_DIRTY", 8, 8, &umr_bitfield_default },
+	 { "PG_ACTIVATED", 9, 9, &umr_bitfield_default },
+	 { "CG_ACTIVATED", 10, 10, &umr_bitfield_default },
+	 { "RSVR_31_11", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_SCHEDULER1[] = {
+	 { "SCHEDULER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_CONTROL[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "MQD_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 25, &umr_bitfield_default },
+	 { "MQD_VOLATILE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIDT_IND_INDEX[] = {
+	 { "DIDT_IND_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIDT_IND_DATA[] = {
+	 { "DIDT_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID0_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID0_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID1_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID1_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID2_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID2_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID3_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID3_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID4_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID4_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID5_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID5_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID6_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID6_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID7_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID7_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID8_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID8_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID9_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID9_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID10_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID10_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID11_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID11_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID12_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID12_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID13_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID13_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID14_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID14_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID15_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID15_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID0[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID1[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID2[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID3[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID4[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID5[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID6[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID7[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID8[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID9[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID10[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID11[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID12[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID13[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID14[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID15[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID0[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID1[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID2[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID3[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID4[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID5[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID6[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID7[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID8[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID9[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID10[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID11[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID12[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID13[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID14[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID15[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESET0[] = {
+	 { "RESOURCE0_RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE1_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESOURCE2_RESET", 2, 2, &umr_bitfield_default },
+	 { "RESOURCE3_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESOURCE4_RESET", 4, 4, &umr_bitfield_default },
+	 { "RESOURCE5_RESET", 5, 5, &umr_bitfield_default },
+	 { "RESOURCE6_RESET", 6, 6, &umr_bitfield_default },
+	 { "RESOURCE7_RESET", 7, 7, &umr_bitfield_default },
+	 { "RESOURCE8_RESET", 8, 8, &umr_bitfield_default },
+	 { "RESOURCE9_RESET", 9, 9, &umr_bitfield_default },
+	 { "RESOURCE10_RESET", 10, 10, &umr_bitfield_default },
+	 { "RESOURCE11_RESET", 11, 11, &umr_bitfield_default },
+	 { "RESOURCE12_RESET", 12, 12, &umr_bitfield_default },
+	 { "RESOURCE13_RESET", 13, 13, &umr_bitfield_default },
+	 { "RESOURCE14_RESET", 14, 14, &umr_bitfield_default },
+	 { "RESOURCE15_RESET", 15, 15, &umr_bitfield_default },
+	 { "RESOURCE16_RESET", 16, 16, &umr_bitfield_default },
+	 { "RESOURCE17_RESET", 17, 17, &umr_bitfield_default },
+	 { "RESOURCE18_RESET", 18, 18, &umr_bitfield_default },
+	 { "RESOURCE19_RESET", 19, 19, &umr_bitfield_default },
+	 { "RESOURCE20_RESET", 20, 20, &umr_bitfield_default },
+	 { "RESOURCE21_RESET", 21, 21, &umr_bitfield_default },
+	 { "RESOURCE22_RESET", 22, 22, &umr_bitfield_default },
+	 { "RESOURCE23_RESET", 23, 23, &umr_bitfield_default },
+	 { "RESOURCE24_RESET", 24, 24, &umr_bitfield_default },
+	 { "RESOURCE25_RESET", 25, 25, &umr_bitfield_default },
+	 { "RESOURCE26_RESET", 26, 26, &umr_bitfield_default },
+	 { "RESOURCE27_RESET", 27, 27, &umr_bitfield_default },
+	 { "RESOURCE28_RESET", 28, 28, &umr_bitfield_default },
+	 { "RESOURCE29_RESET", 29, 29, &umr_bitfield_default },
+	 { "RESOURCE30_RESET", 30, 30, &umr_bitfield_default },
+	 { "RESOURCE31_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESET1[] = {
+	 { "RESOURCE32_RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE33_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESOURCE34_RESET", 2, 2, &umr_bitfield_default },
+	 { "RESOURCE35_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESOURCE36_RESET", 4, 4, &umr_bitfield_default },
+	 { "RESOURCE37_RESET", 5, 5, &umr_bitfield_default },
+	 { "RESOURCE38_RESET", 6, 6, &umr_bitfield_default },
+	 { "RESOURCE39_RESET", 7, 7, &umr_bitfield_default },
+	 { "RESOURCE40_RESET", 8, 8, &umr_bitfield_default },
+	 { "RESOURCE41_RESET", 9, 9, &umr_bitfield_default },
+	 { "RESOURCE42_RESET", 10, 10, &umr_bitfield_default },
+	 { "RESOURCE43_RESET", 11, 11, &umr_bitfield_default },
+	 { "RESOURCE44_RESET", 12, 12, &umr_bitfield_default },
+	 { "RESOURCE45_RESET", 13, 13, &umr_bitfield_default },
+	 { "RESOURCE46_RESET", 14, 14, &umr_bitfield_default },
+	 { "RESOURCE47_RESET", 15, 15, &umr_bitfield_default },
+	 { "RESOURCE48_RESET", 16, 16, &umr_bitfield_default },
+	 { "RESOURCE49_RESET", 17, 17, &umr_bitfield_default },
+	 { "RESOURCE50_RESET", 18, 18, &umr_bitfield_default },
+	 { "RESOURCE51_RESET", 19, 19, &umr_bitfield_default },
+	 { "RESOURCE52_RESET", 20, 20, &umr_bitfield_default },
+	 { "RESOURCE53_RESET", 21, 21, &umr_bitfield_default },
+	 { "RESOURCE54_RESET", 22, 22, &umr_bitfield_default },
+	 { "RESOURCE55_RESET", 23, 23, &umr_bitfield_default },
+	 { "RESOURCE56_RESET", 24, 24, &umr_bitfield_default },
+	 { "RESOURCE57_RESET", 25, 25, &umr_bitfield_default },
+	 { "RESOURCE58_RESET", 26, 26, &umr_bitfield_default },
+	 { "RESOURCE59_RESET", 27, 27, &umr_bitfield_default },
+	 { "RESOURCE60_RESET", 28, 28, &umr_bitfield_default },
+	 { "RESOURCE61_RESET", 29, 29, &umr_bitfield_default },
+	 { "RESOURCE62_RESET", 30, 30, &umr_bitfield_default },
+	 { "RESOURCE63_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_COMPUTE_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RESET_MASK[] = {
+	 { "ME0_GFXHP3D_PIX_RESET", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_RESET", 1, 1, &umr_bitfield_default },
+	 { "ME0_CS_RESET", 2, 2, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "ME1_PIPE0_RESET", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_RESET", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_RESET", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_RESET", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_RESET", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_RESET", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_RESET", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_RESET", 11, 11, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "PIPE_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ENHANCE[] = {
+	 { "MISC", 0, 15, &umr_bitfield_default },
+	 { "AUTO_INC_INDEX", 16, 16, &umr_bitfield_default },
+	 { "CGPG_RESTORE", 17, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_CGPG_RESTORE[] = {
+	 { "VMID", 0, 7, &umr_bitfield_default },
+	 { "MEID", 8, 11, &umr_bitfield_default },
+	 { "PIPEID", 12, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SIGNATURE_CONTROL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SIGNATURE_MASK[] = {
+	 { "INPUT_BUS_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_DB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_PA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_VGT_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SQ_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE4[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE5[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE6[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE7[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_IA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_IA_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SPI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SPI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TD_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_CB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_BCI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_BCI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG04[] = {
+	 { "clipsm0_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG4[] = {
+	 { "gws_busy", 0, 0, &umr_bitfield_default },
+	 { "gws_req", 1, 1, &umr_bitfield_default },
+	 { "gws_out_stall", 2, 2, &umr_bitfield_default },
+	 { "cur_reso", 3, 8, &umr_bitfield_default },
+	 { "cur_reso_head_valid", 9, 9, &umr_bitfield_default },
+	 { "cur_reso_head_dirty", 10, 10, &umr_bitfield_default },
+	 { "cur_reso_head_flag", 11, 11, &umr_bitfield_default },
+	 { "cur_reso_fed", 12, 12, &umr_bitfield_default },
+	 { "cur_reso_barrier", 13, 13, &umr_bitfield_default },
+	 { "cur_reso_flag", 14, 14, &umr_bitfield_default },
+	 { "cur_reso_cnt_gt0", 15, 15, &umr_bitfield_default },
+	 { "credit_cnt_gt0", 16, 16, &umr_bitfield_default },
+	 { "cmd_write", 17, 17, &umr_bitfield_default },
+	 { "grbm_gws_reso_wr", 18, 18, &umr_bitfield_default },
+	 { "grbm_gws_reso_rd", 19, 19, &umr_bitfield_default },
+	 { "ram_read_busy", 20, 20, &umr_bitfield_default },
+	 { "gws_bulkfree", 21, 21, &umr_bitfield_default },
+	 { "ram_gws_re", 22, 22, &umr_bitfield_default },
+	 { "ram_gws_we", 23, 23, &umr_bitfield_default },
+	 { "spare", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG4[] = {
+	 { "rbiu_spl_di_valid", 0, 0, &umr_bitfield_default },
+	 { "spl_rbiu_di_read", 1, 1, &umr_bitfield_default },
+	 { "rbiu_spl_p1_di_valid", 2, 2, &umr_bitfield_default },
+	 { "spl_rbiu_p1_di_read", 3, 3, &umr_bitfield_default },
+	 { "pipe0_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe0_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipe1_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe1_rtr", 7, 7, &umr_bitfield_default },
+	 { "pipe2_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe2_rtr", 9, 9, &umr_bitfield_default },
+	 { "pipe3_ld", 10, 10, &umr_bitfield_default },
+	 { "pipe3_rtr", 11, 11, &umr_bitfield_default },
+	 { "WD_IA_draw_send_d", 12, 12, &umr_bitfield_default },
+	 { "WD_IA_draw_rtr", 13, 13, &umr_bitfield_default },
+	 { "di_type_p0", 14, 15, &umr_bitfield_default },
+	 { "di_state_sel_p1_q", 16, 18, &umr_bitfield_default },
+	 { "di_wd_switch_on_eop_p1_q", 19, 19, &umr_bitfield_default },
+	 { "rbiu_spl_pipe0_lockout", 20, 20, &umr_bitfield_default },
+	 { "last_inst_of_di_p2", 21, 21, &umr_bitfield_default },
+	 { "last_sd_of_inst_p2", 22, 22, &umr_bitfield_default },
+	 { "last_sd_of_di_p2", 23, 23, &umr_bitfield_default },
+	 { "not_eop_wait_p1_q", 24, 24, &umr_bitfield_default },
+	 { "not_eop_wait_q", 25, 25, &umr_bitfield_default },
+	 { "ext_event_wait_p1_q", 26, 26, &umr_bitfield_default },
+	 { "ext_event_wait_q", 27, 27, &umr_bitfield_default },
+	 { "WD_IA1_draw_send_d", 28, 28, &umr_bitfield_default },
+	 { "WD_IA1_draw_rtr", 29, 29, &umr_bitfield_default },
+	 { "send_to_ia1_q", 30, 30, &umr_bitfield_default },
+	 { "dual_ia_mode", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG05[] = {
+	 { "clipsm1_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG5[] = {
+	 { "write_dis", 0, 0, &umr_bitfield_default },
+	 { "dec_error", 1, 1, &umr_bitfield_default },
+	 { "alloc_opco_error", 2, 2, &umr_bitfield_default },
+	 { "dealloc_opco_error", 3, 3, &umr_bitfield_default },
+	 { "wrap_opco_error", 4, 4, &umr_bitfield_default },
+	 { "spare", 5, 7, &umr_bitfield_default },
+	 { "error_ds_address", 8, 21, &umr_bitfield_default },
+	 { "spare1", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG5[] = {
+	 { "p1_rbiu_spl_dr_valid", 0, 0, &umr_bitfield_default },
+	 { "SPARE0", 1, 1, &umr_bitfield_default },
+	 { "p1_pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "p1_pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "p1_pipe1_dr", 4, 4, &umr_bitfield_default },
+	 { "p1_pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "p1_wd_subdma_fifo_empty", 6, 6, &umr_bitfield_default },
+	 { "p1_wd_subdma_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "p1_dma_buf_type_p0_q", 8, 9, &umr_bitfield_default },
+	 { "p1_dma_zero_indices_p0_q", 10, 10, &umr_bitfield_default },
+	 { "p1_dma_req_path_p3_q", 11, 11, &umr_bitfield_default },
+	 { "p1_dma_not_eop_p1_q", 12, 12, &umr_bitfield_default },
+	 { "p1_out_of_range_p4", 13, 13, &umr_bitfield_default },
+	 { "p1_last_sub_dma_p3_q", 14, 14, &umr_bitfield_default },
+	 { "p1_last_rdreq_of_sub_dma_p4", 15, 15, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_send_d", 16, 16, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_rtr", 17, 17, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_send_d", 18, 18, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_rtr", 19, 19, &umr_bitfield_default },
+	 { "p1_last_inst_of_dma_p2", 20, 20, &umr_bitfield_default },
+	 { "p1_last_sd_of_inst_p2", 21, 21, &umr_bitfield_default },
+	 { "p1_last_sd_of_dma_p2", 22, 22, &umr_bitfield_default },
+	 { "SPARE1", 23, 23, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_busy", 24, 24, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_busy", 25, 25, &umr_bitfield_default },
+	 { "p1_send_to_ia1_p3_q", 26, 26, &umr_bitfield_default },
+	 { "p1_dma_wd_switch_on_eop_p3_q", 27, 27, &umr_bitfield_default },
+	 { "p1_pipe3_dr", 28, 28, &umr_bitfield_default },
+	 { "p1_pipe3_rtr", 29, 29, &umr_bitfield_default },
+	 { "p1_wd_dma2draw_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "p1_wd_dma2draw_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG06[] = {
+	 { "clipsm1_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG6[] = {
+	 { "oa_busy", 0, 0, &umr_bitfield_default },
+	 { "counters_enabled", 1, 4, &umr_bitfield_default },
+	 { "counters_busy", 5, 20, &umr_bitfield_default },
+	 { "spare", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIA_DEBUG_REG6[] = {
+	 { "current_shift_q", 0, 3, &umr_bitfield_default },
+	 { "current_stride_pre", 4, 7, &umr_bitfield_default },
+	 { "current_stride_q", 8, 12, &umr_bitfield_default },
+	 { "first_group_partial", 13, 13, &umr_bitfield_default },
+	 { "second_group_partial", 14, 14, &umr_bitfield_default },
+	 { "curr_prim_partial", 15, 15, &umr_bitfield_default },
+	 { "next_stride_q", 16, 20, &umr_bitfield_default },
+	 { "next_group_partial", 21, 21, &umr_bitfield_default },
+	 { "after_group_partial", 22, 22, &umr_bitfield_default },
+	 { "extract_group", 23, 23, &umr_bitfield_default },
+	 { "grp_shift_debug_data", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG07[] = {
+	 { "clipsm2_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG18[] = {
+	 { "grp_vr_valid", 0, 0, &umr_bitfield_default },
+	 { "pipe0_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "vr_grp_read", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "out_vr_indx_read", 6, 6, &umr_bitfield_default },
+	 { "out_vr_prim_read", 7, 7, &umr_bitfield_default },
+	 { "indices_to_send_q", 8, 10, &umr_bitfield_default },
+	 { "valid_indices", 11, 11, &umr_bitfield_default },
+	 { "last_indx_of_prim", 12, 12, &umr_bitfield_default },
+	 { "indx0_new_d", 13, 13, &umr_bitfield_default },
+	 { "indx1_new_d", 14, 14, &umr_bitfield_default },
+	 { "indx2_new_d", 15, 15, &umr_bitfield_default },
+	 { "indx2_hit_d", 16, 16, &umr_bitfield_default },
+	 { "indx1_hit_d", 17, 17, &umr_bitfield_default },
+	 { "indx0_hit_d", 18, 18, &umr_bitfield_default },
+	 { "st_vertex_reuse_off_r0_q", 19, 19, &umr_bitfield_default },
+	 { "last_group_of_instance_r0_q", 20, 20, &umr_bitfield_default },
+	 { "null_primitive_r0_q", 21, 21, &umr_bitfield_default },
+	 { "eop_r0_q", 22, 22, &umr_bitfield_default },
+	 { "eject_vtx_vect_r1_d", 23, 23, &umr_bitfield_default },
+	 { "sub_prim_type_r0_q", 24, 26, &umr_bitfield_default },
+	 { "gs_scenario_a_r0_q", 27, 27, &umr_bitfield_default },
+	 { "gs_scenario_b_r0_q", 28, 28, &umr_bitfield_default },
+	 { "components_valid_r0_q", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIA_DEBUG_REG7[] = {
+	 { "reset_indx_state_q", 0, 3, &umr_bitfield_default },
+	 { "shift_vect_valid_p2_q", 4, 7, &umr_bitfield_default },
+	 { "shift_vect1_valid_p2_q", 8, 11, &umr_bitfield_default },
+	 { "shift_vect0_reset_match_p2_q", 12, 15, &umr_bitfield_default },
+	 { "shift_vect1_reset_match_p2_q", 16, 19, &umr_bitfield_default },
+	 { "num_indx_in_group_p2_q", 20, 22, &umr_bitfield_default },
+	 { "last_group_of_draw_p2_q", 23, 23, &umr_bitfield_default },
+	 { "shift_event_flag_p2_q", 24, 24, &umr_bitfield_default },
+	 { "indx_shift_is_one_p2_q", 25, 25, &umr_bitfield_default },
+	 { "indx_shift_is_two_p2_q", 26, 26, &umr_bitfield_default },
+	 { "indx_stride_is_four_p2_q", 27, 27, &umr_bitfield_default },
+	 { "shift_prim1_reset_p3_q", 28, 28, &umr_bitfield_default },
+	 { "shift_prim1_partial_p3_q", 29, 29, &umr_bitfield_default },
+	 { "shift_prim0_reset_p3_q", 30, 30, &umr_bitfield_default },
+	 { "shift_prim0_partial_p3_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG08[] = {
+	 { "clipsm2_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_DEBUG_STS_LOCAL[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "WAVE_LEVEL", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG8[] = {
+	 { "rcm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "rcm_noif_busy_q", 1, 1, &umr_bitfield_default },
+	 { "r1_inst_rtr", 2, 2, &umr_bitfield_default },
+	 { "spi_gsprim_fifo_busy_q", 3, 3, &umr_bitfield_default },
+	 { "spi_esvert_fifo_busy_q", 4, 4, &umr_bitfield_default },
+	 { "gs_tbl_valid_r3_q", 5, 5, &umr_bitfield_default },
+	 { "valid_r0_q", 6, 6, &umr_bitfield_default },
+	 { "valid_r1_q", 7, 7, &umr_bitfield_default },
+	 { "valid_r2", 8, 8, &umr_bitfield_default },
+	 { "valid_r2_q", 9, 9, &umr_bitfield_default },
+	 { "r0_rtr", 10, 10, &umr_bitfield_default },
+	 { "r1_rtr", 11, 11, &umr_bitfield_default },
+	 { "r2_indx_rtr", 12, 12, &umr_bitfield_default },
+	 { "r2_rtr", 13, 13, &umr_bitfield_default },
+	 { "es_gs_rtr", 14, 14, &umr_bitfield_default },
+	 { "gs_event_fifo_rtr", 15, 15, &umr_bitfield_default },
+	 { "tm_rcm_gs_event_rtr", 16, 16, &umr_bitfield_default },
+	 { "gs_tbl_r3_rtr", 17, 17, &umr_bitfield_default },
+	 { "prim_skid_fifo_empty", 18, 18, &umr_bitfield_default },
+	 { "VGT_SPI_gsprim_rtr_q", 19, 19, &umr_bitfield_default },
+	 { "tm_rcm_gs_tbl_rtr", 20, 20, &umr_bitfield_default },
+	 { "tm_rcm_es_tbl_rtr", 21, 21, &umr_bitfield_default },
+	 { "VGT_SPI_esvert_rtr_q", 22, 22, &umr_bitfield_default },
+	 { "r2_no_bp_rtr", 23, 23, &umr_bitfield_default },
+	 { "hold_for_es_flush", 24, 24, &umr_bitfield_default },
+	 { "gs_event_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "gsprim_buff_empty_q", 26, 26, &umr_bitfield_default },
+	 { "gsprim_buff_full_q", 27, 27, &umr_bitfield_default },
+	 { "te_prim_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "te_prim_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "te_vert_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "te_vert_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIA_DEBUG_REG8[] = {
+	 { "di_prim_type_p1_q", 0, 4, &umr_bitfield_default },
+	 { "two_cycle_xfer_p1_q", 5, 5, &umr_bitfield_default },
+	 { "two_prim_input_p1_q", 6, 6, &umr_bitfield_default },
+	 { "shift_vect_end_of_packet_p5_q", 7, 7, &umr_bitfield_default },
+	 { "last_group_of_inst_p5_q", 8, 8, &umr_bitfield_default },
+	 { "shift_prim1_null_flag_p5_q", 9, 9, &umr_bitfield_default },
+	 { "shift_prim0_null_flag_p5_q", 10, 10, &umr_bitfield_default },
+	 { "grp_continued", 11, 11, &umr_bitfield_default },
+	 { "grp_state_sel", 12, 14, &umr_bitfield_default },
+	 { "grp_sub_prim_type", 15, 20, &umr_bitfield_default },
+	 { "grp_output_path", 21, 23, &umr_bitfield_default },
+	 { "grp_null_primitive", 24, 24, &umr_bitfield_default },
+	 { "grp_eop", 25, 25, &umr_bitfield_default },
+	 { "grp_eopg", 26, 26, &umr_bitfield_default },
+	 { "grp_event_flag", 27, 27, &umr_bitfield_default },
+	 { "grp_components_valid", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG09[] = {
+	 { "clipsm3_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG9[] = {
+	 { "indices_to_send_r2_q", 0, 1, &umr_bitfield_default },
+	 { "valid_indices_r3", 2, 2, &umr_bitfield_default },
+	 { "gs_eov_r3", 3, 3, &umr_bitfield_default },
+	 { "eop_indx_r3", 4, 4, &umr_bitfield_default },
+	 { "eop_prim_r3", 5, 5, &umr_bitfield_default },
+	 { "es_eov_r3", 6, 6, &umr_bitfield_default },
+	 { "es_tbl_state_r3_q_0", 7, 7, &umr_bitfield_default },
+	 { "pending_es_send_r3_q", 8, 8, &umr_bitfield_default },
+	 { "pending_es_flush_r3", 9, 9, &umr_bitfield_default },
+	 { "gs_tbl_num_es_per_gs_r3_q_not_0", 10, 10, &umr_bitfield_default },
+	 { "gs_tbl_prim_cnt_r3_q", 11, 17, &umr_bitfield_default },
+	 { "gs_tbl_eop_r3_q", 18, 18, &umr_bitfield_default },
+	 { "gs_tbl_state_r3_q", 19, 21, &umr_bitfield_default },
+	 { "gs_pending_state_r3_q", 22, 22, &umr_bitfield_default },
+	 { "invalidate_rb_roll_over_q", 23, 23, &umr_bitfield_default },
+	 { "gs_instancing_state_q", 24, 24, &umr_bitfield_default },
+	 { "es_per_gs_vert_cnt_r3_q_not_0", 25, 25, &umr_bitfield_default },
+	 { "gs_prim_per_es_ctr_r3_q_not_0", 26, 26, &umr_bitfield_default },
+	 { "pre_r0_rtr", 27, 27, &umr_bitfield_default },
+	 { "valid_r3_q", 28, 28, &umr_bitfield_default },
+	 { "valid_pre_r0_q", 29, 29, &umr_bitfield_default },
+	 { "SPARE0", 30, 30, &umr_bitfield_default },
+	 { "off_chip_hs_r2_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIA_DEBUG_REG9[] = {
+	 { "send_to_se1_p6", 0, 0, &umr_bitfield_default },
+	 { "gfx_se_switch_p6", 1, 1, &umr_bitfield_default },
+	 { "null_eoi_xfer_prim1_p6", 2, 2, &umr_bitfield_default },
+	 { "null_eoi_xfer_prim0_p6", 3, 3, &umr_bitfield_default },
+	 { "prim1_eoi_p6", 4, 4, &umr_bitfield_default },
+	 { "prim0_eoi_p6", 5, 5, &umr_bitfield_default },
+	 { "prim1_valid_eopg_p6", 6, 6, &umr_bitfield_default },
+	 { "prim0_valid_eopg_p6", 7, 7, &umr_bitfield_default },
+	 { "prim1_to_other_se_p6", 8, 8, &umr_bitfield_default },
+	 { "eopg_on_last_prim_p6", 9, 9, &umr_bitfield_default },
+	 { "eopg_between_prims_p6", 10, 10, &umr_bitfield_default },
+	 { "prim_count_eq_group_size_p6", 11, 11, &umr_bitfield_default },
+	 { "prim_count_gt_group_size_p6", 12, 12, &umr_bitfield_default },
+	 { "two_prim_output_p5_q", 13, 13, &umr_bitfield_default },
+	 { "SPARE0", 14, 14, &umr_bitfield_default },
+	 { "SPARE1", 15, 15, &umr_bitfield_default },
+	 { "shift_vect_end_of_packet_p5_q", 16, 16, &umr_bitfield_default },
+	 { "prim1_xfer_p6", 17, 17, &umr_bitfield_default },
+	 { "grp_se1_fifo_empty", 18, 18, &umr_bitfield_default },
+	 { "grp_se1_fifo_full", 19, 19, &umr_bitfield_default },
+	 { "prim_counter_q", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG10[] = {
+	 { "clipsm3_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG10[] = {
+	 { "index_buffer_depth_r1_q", 0, 4, &umr_bitfield_default },
+	 { "eopg_r2_q", 5, 5, &umr_bitfield_default },
+	 { "eotg_r2_q", 6, 6, &umr_bitfield_default },
+	 { "onchip_gs_en_r0_q", 7, 8, &umr_bitfield_default },
+	 { "SPARE2", 9, 10, &umr_bitfield_default },
+	 { "rcm_mem_gsprim_re_qq", 11, 11, &umr_bitfield_default },
+	 { "rcm_mem_gsprim_re_q", 12, 12, &umr_bitfield_default },
+	 { "gs_rb_space_avail_r3_q_9_0", 13, 22, &umr_bitfield_default },
+	 { "es_rb_space_avail_r2_q_8_0", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_CONTROL[] = {
+	 { "DEPTH_CLEAR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCIL_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DEPTH_COPY", 2, 2, &umr_bitfield_default },
+	 { "STENCIL_COPY", 3, 3, &umr_bitfield_default },
+	 { "RESUMMARIZE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STENCIL_COMPRESS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DEPTH_COMPRESS_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "COPY_CENTROID", 7, 7, &umr_bitfield_default },
+	 { "COPY_SAMPLE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_COUNT_CONTROL[] = {
+	 { "ZPASS_INCREMENT_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "PERFECT_ZPASS_COUNTS", 1, 1, &umr_bitfield_default },
+	 { "SAMPLE_RATE", 4, 6, &umr_bitfield_default },
+	 { "ZPASS_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "ZFAIL_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "SFAIL_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "DBFAIL_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "SLICE_EVEN_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "Z_READ_ONLY", 24, 24, &umr_bitfield_default },
+	 { "STENCIL_READ_ONLY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_OVERRIDE[] = {
+	 { "FORCE_HIZ_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE0", 2, 3, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE1", 4, 5, &umr_bitfield_default },
+	 { "FORCE_SHADER_Z_ORDER", 6, 6, &umr_bitfield_default },
+	 { "FAST_Z_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "FAST_STENCIL_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "NOOP_CULL_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "FORCE_COLOR_KILL", 10, 10, &umr_bitfield_default },
+	 { "FORCE_Z_READ", 11, 11, &umr_bitfield_default },
+	 { "FORCE_STENCIL_READ", 12, 12, &umr_bitfield_default },
+	 { "FORCE_FULL_Z_RANGE", 13, 14, &umr_bitfield_default },
+	 { "FORCE_QC_SMASK_CONFLICT", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_VIEWPORT_CLAMP", 16, 16, &umr_bitfield_default },
+	 { "IGNORE_SC_ZRANGE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_FULLY_COVERED", 18, 18, &umr_bitfield_default },
+	 { "FORCE_Z_LIMIT_SUMM", 19, 20, &umr_bitfield_default },
+	 { "MAX_TILES_IN_DTT", 21, 25, &umr_bitfield_default },
+	 { "DISABLE_TILE_RATE_TILES", 26, 26, &umr_bitfield_default },
+	 { "FORCE_Z_DIRTY", 27, 27, &umr_bitfield_default },
+	 { "FORCE_STENCIL_DIRTY", 28, 28, &umr_bitfield_default },
+	 { "FORCE_Z_VALID", 29, 29, &umr_bitfield_default },
+	 { "FORCE_STENCIL_VALID", 30, 30, &umr_bitfield_default },
+	 { "PRESERVE_COMPRESSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_OVERRIDE2[] = {
+	 { "PARTIAL_SQUAD_LAUNCH_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "PARTIAL_SQUAD_LAUNCH_COUNTDOWN", 2, 4, &umr_bitfield_default },
+	 { "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_COLOR_ON_VALIDATION", 7, 7, &umr_bitfield_default },
+	 { "DECOMPRESS_Z_ON_FLUSH", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_REG_SNOOP", 9, 9, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_HIER_DEPTH_DISABLE", 10, 10, &umr_bitfield_default },
+	 { "SEPARATE_HIZS_FUNC_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "HIZ_ZFUNC", 12, 14, &umr_bitfield_default },
+	 { "HIS_SFUNC_FF", 15, 17, &umr_bitfield_default },
+	 { "HIS_SFUNC_BF", 18, 20, &umr_bitfield_default },
+	 { "PRESERVE_ZRANGE", 21, 21, &umr_bitfield_default },
+	 { "PRESERVE_SRESULTS", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_FAST_PASS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_HTILE_DATA_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_BOUNDS_MIN[] = {
+	 { "MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_BOUNDS_MAX[] = {
+	 { "MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_CLEAR[] = {
+	 { "CLEAR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_CLEAR[] = {
+	 { "DEPTH_CLEAR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_TL[] = {
+	 { "TL_X", 0, 15, &umr_bitfield_default },
+	 { "TL_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_BR[] = {
+	 { "BR_X", 0, 15, &umr_bitfield_default },
+	 { "BR_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_INFO[] = {
+	 { "ADDR5_SWIZZLE_MASK", 0, 3, &umr_bitfield_default },
+	 { "ARRAY_MODE", 4, 7, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 8, 12, &umr_bitfield_default },
+	 { "BANK_WIDTH", 13, 14, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 15, 16, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 17, 18, &umr_bitfield_default },
+	 { "NUM_BANKS", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_INFO[] = {
+	 { "FORMAT", 0, 1, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 2, 3, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "READ_SIZE", 28, 28, &umr_bitfield_default },
+	 { "TILE_SURFACE_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "ZRANGE_PRECISION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_INFO[] = {
+	 { "FORMAT", 0, 0, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "TILE_STENCIL_DISABLE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_SIZE[] = {
+	 { "PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "HEIGHT_TILE_MAX", 11, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_SLICE[] = {
+	 { "SLICE_TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_BC_BASE_ADDR_HI[] = {
+	 { "ADDRESS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_0[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_1[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_2[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_3[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_2[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_3[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_OFFSET[] = {
+	 { "WINDOW_X_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "WINDOW_Y_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_RULE[] = {
+	 { "CLIP_RULE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_EDGERULE[] = {
+	 { "ER_TRI", 0, 3, &umr_bitfield_default },
+	 { "ER_POINT", 4, 7, &umr_bitfield_default },
+	 { "ER_RECT", 8, 11, &umr_bitfield_default },
+	 { "ER_LINE_LR", 12, 17, &umr_bitfield_default },
+	 { "ER_LINE_RL", 18, 23, &umr_bitfield_default },
+	 { "ER_LINE_TB", 24, 27, &umr_bitfield_default },
+	 { "ER_LINE_BT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_HARDWARE_SCREEN_OFFSET[] = {
+	 { "HW_SCREEN_OFFSET_X", 0, 8, &umr_bitfield_default },
+	 { "HW_SCREEN_OFFSET_Y", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_TARGET_MASK[] = {
+	 { "TARGET0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "TARGET1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "TARGET2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "TARGET3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "TARGET4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "TARGET5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "TARGET6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "TARGET7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_SHADER_MASK[] = {
+	 { "OUTPUT0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "OUTPUT1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "OUTPUT2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "OUTPUT3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "OUTPUT4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "OUTPUT5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "OUTPUT6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "OUTPUT7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_0[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_1[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_0[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_0[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_1[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_1[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_2[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_2[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_3[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_3[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_4[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_4[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_5[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_5[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_6[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_6[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_7[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_7[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_8[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_8[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_9[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_9[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_10[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_10[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_11[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_11[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_12[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_12[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_13[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_13[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_14[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_14[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_15[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_15[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_RASTER_CONFIG[] = {
+	 { "RB_MAP_PKR0", 0, 1, &umr_bitfield_default },
+	 { "RB_MAP_PKR1", 2, 3, &umr_bitfield_default },
+	 { "RB_XSEL2", 4, 5, &umr_bitfield_default },
+	 { "RB_XSEL", 6, 6, &umr_bitfield_default },
+	 { "RB_YSEL", 7, 7, &umr_bitfield_default },
+	 { "PKR_MAP", 8, 9, &umr_bitfield_default },
+	 { "PKR_XSEL", 10, 11, &umr_bitfield_default },
+	 { "PKR_YSEL", 12, 13, &umr_bitfield_default },
+	 { "PKR_XSEL2", 14, 15, &umr_bitfield_default },
+	 { "SC_MAP", 16, 17, &umr_bitfield_default },
+	 { "SC_XSEL", 18, 19, &umr_bitfield_default },
+	 { "SC_YSEL", 20, 21, &umr_bitfield_default },
+	 { "SE_MAP", 24, 25, &umr_bitfield_default },
+	 { "SE_XSEL", 26, 27, &umr_bitfield_default },
+	 { "SE_YSEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_RASTER_CONFIG_1[] = {
+	 { "SE_PAIR_MAP", 0, 1, &umr_bitfield_default },
+	 { "SE_PAIR_XSEL", 2, 3, &umr_bitfield_default },
+	 { "SE_PAIR_YSEL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_CONTROL[] = {
+	 { "SLICE_EVEN_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PERFMON_CNTX_CNTL[] = {
+	 { "PERFMON_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RINGID[] = {
+	 { "RINGID", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MAX_VTX_INDX[] = {
+	 { "MAX_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MIN_VTX_INDX[] = {
+	 { "MIN_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INDX_OFFSET[] = {
+	 { "INDX_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_INDX[] = {
+	 { "RESET_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_RED[] = {
+	 { "BLEND_RED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_GREEN[] = {
+	 { "BLEND_GREEN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_BLUE[] = {
+	 { "BLEND_BLUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_ALPHA[] = {
+	 { "BLEND_ALPHA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_CONTROL[] = {
+	 { "STENCILFAIL", 0, 3, &umr_bitfield_default },
+	 { "STENCILZPASS", 4, 7, &umr_bitfield_default },
+	 { "STENCILZFAIL", 8, 11, &umr_bitfield_default },
+	 { "STENCILFAIL_BF", 12, 15, &umr_bitfield_default },
+	 { "STENCILZPASS_BF", 16, 19, &umr_bitfield_default },
+	 { "STENCILZFAIL_BF", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCILREFMASK[] = {
+	 { "STENCILTESTVAL", 0, 7, &umr_bitfield_default },
+	 { "STENCILMASK", 8, 15, &umr_bitfield_default },
+	 { "STENCILWRITEMASK", 16, 23, &umr_bitfield_default },
+	 { "STENCILOPVAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCILREFMASK_BF[] = {
+	 { "STENCILTESTVAL_BF", 0, 7, &umr_bitfield_default },
+	 { "STENCILMASK_BF", 8, 15, &umr_bitfield_default },
+	 { "STENCILWRITEMASK_BF", 16, 23, &umr_bitfield_default },
+	 { "STENCILOPVAL_BF", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_1[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_1[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_1[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_1[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_1[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_1[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_2[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_2[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_2[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_2[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_2[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_2[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_3[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_3[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_3[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_3[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_3[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_3[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_4[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_4[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_4[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_4[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_4[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_4[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_5[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_5[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_5[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_5[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_5[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_5[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_6[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_6[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_6[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_6[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_6[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_6[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_7[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_7[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_7[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_7[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_7[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_7[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_8[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_8[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_8[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_8[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_8[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_8[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_9[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_9[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_9[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_9[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_9[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_9[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_10[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_10[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_10[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_10[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_10[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_10[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_11[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_11[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_11[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_11[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_11[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_11[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_12[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_12[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_12[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_12[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_12[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_12[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_13[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_13[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_13[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_13[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_13[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_13[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_14[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_14[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_14[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_14[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_14[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_14[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_15[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_15[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_15[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_15[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_15[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_15[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_0[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_1[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_2[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_3[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_4[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_5[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_6[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_7[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_8[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_9[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_10[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_11[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_12[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_13[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_14[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_15[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_16[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_17[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_18[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_19[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_20[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_21[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_22[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_23[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_24[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_25[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_26[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_27[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_28[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_29[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_30[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_31[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_VS_OUT_CONFIG[] = {
+	 { "VS_EXPORT_COUNT", 1, 5, &umr_bitfield_default },
+	 { "VS_HALF_PACK", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_ENA[] = {
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_ADDR[] = {
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_INTERP_CONTROL_0[] = {
+	 { "FLAT_SHADE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PNT_SPRITE_ENA", 1, 1, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_X", 2, 4, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Y", 5, 7, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Z", 8, 10, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_W", 11, 13, &umr_bitfield_default },
+	 { "PNT_SPRITE_TOP_1", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_IN_CONTROL[] = {
+	 { "NUM_INTERP", 0, 5, &umr_bitfield_default },
+	 { "PARAM_GEN", 6, 6, &umr_bitfield_default },
+	 { "BC_OPTIMIZE_DISABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_BARYC_CNTL[] = {
+	 { "PERSP_CENTER_CNTL", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTROID_CNTL", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_CNTL", 8, 8, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_CNTL", 12, 12, &umr_bitfield_default },
+	 { "POS_FLOAT_LOCATION", 16, 17, &umr_bitfield_default },
+	 { "POS_FLOAT_ULC", 20, 20, &umr_bitfield_default },
+	 { "FRONT_FACE_ALL_BITS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_TMPRING_SIZE[] = {
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_POS_FORMAT[] = {
+	 { "POS0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "POS1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "POS2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "POS3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_Z_FORMAT[] = {
+	 { "Z_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_COL_FORMAT[] = {
+	 { "COL0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "COL1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "COL2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "COL3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+	 { "COL4_EXPORT_FORMAT", 16, 19, &umr_bitfield_default },
+	 { "COL5_EXPORT_FORMAT", 20, 23, &umr_bitfield_default },
+	 { "COL6_EXPORT_FORMAT", 24, 27, &umr_bitfield_default },
+	 { "COL7_EXPORT_FORMAT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND0_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND1_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND2_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND3_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND4_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND5_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND6_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND7_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCS_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_X_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_Y_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_SIZE[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_CULL_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_BASE_HI[] = {
+	 { "BASE_ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_BASE[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DRAW_INITIATOR[] = {
+	 { "SOURCE_SELECT", 0, 1, &umr_bitfield_default },
+	 { "MAJOR_MODE", 2, 3, &umr_bitfield_default },
+	 { "SPRITE_EN_R6XX", 4, 4, &umr_bitfield_default },
+	 { "NOT_EOP", 5, 5, &umr_bitfield_default },
+	 { "USE_OPAQUE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_IMMED_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_EVENT_ADDRESS_REG[] = {
+	 { "ADDRESS_LOW", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_CONTROL[] = {
+	 { "STENCIL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "Z_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "Z_WRITE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "ZFUNC", 4, 6, &umr_bitfield_default },
+	 { "BACKFACE_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "STENCILFUNC", 8, 10, &umr_bitfield_default },
+	 { "STENCILFUNC_BF", 20, 22, &umr_bitfield_default },
+	 { "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_COLOR_WRITES_ON_DEPTH_PASS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_EQAA[] = {
+	 { "MAX_ANCHOR_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLES", 4, 6, &umr_bitfield_default },
+	 { "MASK_EXPORT_NUM_SAMPLES", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "HIGH_QUALITY_INTERSECTIONS", 16, 16, &umr_bitfield_default },
+	 { "INCOHERENT_EQAA_READS", 17, 17, &umr_bitfield_default },
+	 { "INTERPOLATE_COMP_Z", 18, 18, &umr_bitfield_default },
+	 { "INTERPOLATE_SRC_Z", 19, 19, &umr_bitfield_default },
+	 { "STATIC_ANCHOR_ASSOCIATIONS", 20, 20, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_EQAA_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "OVERRASTERIZATION_AMOUNT", 24, 26, &umr_bitfield_default },
+	 { "ENABLE_POSTZ_OVERRASTERIZATION", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR_CONTROL[] = {
+	 { "DEGAMMA_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "ROP3", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SHADER_CONTROL[] = {
+	 { "Z_EXPORT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCIL_TEST_VAL_EXPORT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STENCIL_OP_VAL_EXPORT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "Z_ORDER", 4, 5, &umr_bitfield_default },
+	 { "KILL_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "COVERAGE_TO_MASK_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MASK_EXPORT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "EXEC_ON_HIER_FAIL", 9, 9, &umr_bitfield_default },
+	 { "EXEC_ON_NOOP", 10, 10, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "DEPTH_BEFORE_SHADER", 12, 12, &umr_bitfield_default },
+	 { "CONSERVATIVE_Z_EXPORT", 13, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_CLIP_CNTL[] = {
+	 { "UCP_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "UCP_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "UCP_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "UCP_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "UCP_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "UCP_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "PS_UCP_Y_SCALE_NEG", 13, 13, &umr_bitfield_default },
+	 { "PS_UCP_MODE", 14, 15, &umr_bitfield_default },
+	 { "CLIP_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "UCP_CULL_ONLY_ENA", 17, 17, &umr_bitfield_default },
+	 { "BOUNDARY_EDGE_FLAG_ENA", 18, 18, &umr_bitfield_default },
+	 { "DX_CLIP_SPACE_DEF", 19, 19, &umr_bitfield_default },
+	 { "DIS_CLIP_ERR_DETECT", 20, 20, &umr_bitfield_default },
+	 { "VTX_KILL_OR", 21, 21, &umr_bitfield_default },
+	 { "DX_RASTERIZATION_KILL", 22, 22, &umr_bitfield_default },
+	 { "DX_LINEAR_ATTR_CLIP_ENA", 24, 24, &umr_bitfield_default },
+	 { "VTE_VPORT_PROVOKE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "ZCLIP_NEAR_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "ZCLIP_FAR_DISABLE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_SC_MODE_CNTL[] = {
+	 { "CULL_FRONT", 0, 0, &umr_bitfield_default },
+	 { "CULL_BACK", 1, 1, &umr_bitfield_default },
+	 { "FACE", 2, 2, &umr_bitfield_default },
+	 { "POLY_MODE", 3, 4, &umr_bitfield_default },
+	 { "POLYMODE_FRONT_PTYPE", 5, 7, &umr_bitfield_default },
+	 { "POLYMODE_BACK_PTYPE", 8, 10, &umr_bitfield_default },
+	 { "POLY_OFFSET_FRONT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "POLY_OFFSET_BACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "POLY_OFFSET_PARA_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "VTX_WINDOW_OFFSET_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "PROVOKING_VTX_LAST", 19, 19, &umr_bitfield_default },
+	 { "PERSP_CORR_DIS", 20, 20, &umr_bitfield_default },
+	 { "MULTI_PRIM_IB_ENA", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VTE_CNTL[] = {
+	 { "VPORT_X_SCALE_ENA", 0, 0, &umr_bitfield_default },
+	 { "VPORT_X_OFFSET_ENA", 1, 1, &umr_bitfield_default },
+	 { "VPORT_Y_SCALE_ENA", 2, 2, &umr_bitfield_default },
+	 { "VPORT_Y_OFFSET_ENA", 3, 3, &umr_bitfield_default },
+	 { "VPORT_Z_SCALE_ENA", 4, 4, &umr_bitfield_default },
+	 { "VPORT_Z_OFFSET_ENA", 5, 5, &umr_bitfield_default },
+	 { "VTX_XY_FMT", 8, 8, &umr_bitfield_default },
+	 { "VTX_Z_FMT", 9, 9, &umr_bitfield_default },
+	 { "VTX_W0_FMT", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_REF", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VS_OUT_CNTL[] = {
+	 { "CLIP_DIST_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_6", 6, 6, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_7", 7, 7, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_0", 8, 8, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_1", 9, 9, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_2", 10, 10, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_3", 11, 11, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_4", 12, 12, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_5", 13, 13, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_6", 14, 14, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_7", 15, 15, &umr_bitfield_default },
+	 { "USE_VTX_POINT_SIZE", 16, 16, &umr_bitfield_default },
+	 { "USE_VTX_EDGE_FLAG", 17, 17, &umr_bitfield_default },
+	 { "USE_VTX_RENDER_TARGET_INDX", 18, 18, &umr_bitfield_default },
+	 { "USE_VTX_VIEWPORT_INDX", 19, 19, &umr_bitfield_default },
+	 { "USE_VTX_KILL_FLAG", 20, 20, &umr_bitfield_default },
+	 { "VS_OUT_MISC_VEC_ENA", 21, 21, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST0_VEC_ENA", 22, 22, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST1_VEC_ENA", 23, 23, &umr_bitfield_default },
+	 { "VS_OUT_MISC_SIDE_BUS_ENA", 24, 24, &umr_bitfield_default },
+	 { "USE_VTX_GS_CUT_FLAG", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_NANINF_CNTL[] = {
+	 { "VTE_XY_INF_DISCARD", 0, 0, &umr_bitfield_default },
+	 { "VTE_Z_INF_DISCARD", 1, 1, &umr_bitfield_default },
+	 { "VTE_W_INF_DISCARD", 2, 2, &umr_bitfield_default },
+	 { "VTE_0XNANINF_IS_0", 3, 3, &umr_bitfield_default },
+	 { "VTE_XY_NAN_RETAIN", 4, 4, &umr_bitfield_default },
+	 { "VTE_Z_NAN_RETAIN", 5, 5, &umr_bitfield_default },
+	 { "VTE_W_NAN_RETAIN", 6, 6, &umr_bitfield_default },
+	 { "VTE_W_RECIP_NAN_IS_0", 7, 7, &umr_bitfield_default },
+	 { "VS_XY_NAN_TO_INF", 8, 8, &umr_bitfield_default },
+	 { "VS_XY_INF_RETAIN", 9, 9, &umr_bitfield_default },
+	 { "VS_Z_NAN_TO_INF", 10, 10, &umr_bitfield_default },
+	 { "VS_Z_INF_RETAIN", 11, 11, &umr_bitfield_default },
+	 { "VS_W_NAN_TO_INF", 12, 12, &umr_bitfield_default },
+	 { "VS_W_INF_RETAIN", 13, 13, &umr_bitfield_default },
+	 { "VS_CLIP_DIST_INF_DISCARD", 14, 14, &umr_bitfield_default },
+	 { "VTE_NO_OUTPUT_NEG_0", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_CNTL[] = {
+	 { "LINE_STIPPLE_RESET", 0, 1, &umr_bitfield_default },
+	 { "EXPAND_FULL_LENGTH", 2, 2, &umr_bitfield_default },
+	 { "FRACTIONAL_ACCUM", 3, 3, &umr_bitfield_default },
+	 { "DIAMOND_ADJUST", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_SCALE[] = {
+	 { "LINE_STIPPLE_SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PRIM_FILTER_CNTL[] = {
+	 { "TRIANGLE_FILTER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "LINE_FILTER_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "POINT_FILTER_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RECTANGLE_FILTER_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "TRIANGLE_EXPAND_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINE_EXPAND_ENA", 5, 5, &umr_bitfield_default },
+	 { "POINT_EXPAND_ENA", 6, 6, &umr_bitfield_default },
+	 { "RECTANGLE_EXPAND_ENA", 7, 7, &umr_bitfield_default },
+	 { "PRIM_EXPAND_CONSTANT", 8, 15, &umr_bitfield_default },
+	 { "XMAX_RIGHT_EXCLUSION", 30, 30, &umr_bitfield_default },
+	 { "YMAX_BOTTOM_EXCLUSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POINT_SIZE[] = {
+	 { "HEIGHT", 0, 15, &umr_bitfield_default },
+	 { "WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POINT_MINMAX[] = {
+	 { "MIN_SIZE", 0, 15, &umr_bitfield_default },
+	 { "MAX_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_CNTL[] = {
+	 { "WIDTH", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_STIPPLE[] = {
+	 { "LINE_PATTERN", 0, 15, &umr_bitfield_default },
+	 { "REPEAT_COUNT", 16, 23, &umr_bitfield_default },
+	 { "PATTERN_BIT_ORDER", 28, 28, &umr_bitfield_default },
+	 { "AUTO_RESET_CNTL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_OUTPUT_PATH_CNTL[] = {
+	 { "PATH_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_CNTL[] = {
+	 { "TESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_MAX_TESS_LEVEL[] = {
+	 { "MAX_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_MIN_TESS_LEVEL[] = {
+	 { "MIN_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_REUSE_DEPTH[] = {
+	 { "REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_PRIM_TYPE[] = {
+	 { "PRIM_TYPE", 0, 4, &umr_bitfield_default },
+	 { "RETAIN_ORDER", 14, 14, &umr_bitfield_default },
+	 { "RETAIN_QUADS", 15, 15, &umr_bitfield_default },
+	 { "PRIM_ORDER", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_FIRST_DECR[] = {
+	 { "FIRST_DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_DECR[] = {
+	 { "DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_0_CNTL[] = {
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_1_CNTL[] = {
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_0_FMT_CNTL[] = {
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_1_FMT_CNTL[] = {
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_MODE[] = {
+	 { "MODE", 0, 2, &umr_bitfield_default },
+	 { "RESERVED_0", 3, 3, &umr_bitfield_default },
+	 { "CUT_MODE", 4, 5, &umr_bitfield_default },
+	 { "RESERVED_1", 6, 10, &umr_bitfield_default },
+	 { "GS_C_PACK_EN", 11, 11, &umr_bitfield_default },
+	 { "RESERVED_2", 12, 12, &umr_bitfield_default },
+	 { "ES_PASSTHRU", 13, 13, &umr_bitfield_default },
+	 { "COMPUTE_MODE", 14, 14, &umr_bitfield_default },
+	 { "FAST_COMPUTE_MODE", 15, 15, &umr_bitfield_default },
+	 { "ELEMENT_INFO_EN", 16, 16, &umr_bitfield_default },
+	 { "PARTIAL_THD_AT_EOI", 17, 17, &umr_bitfield_default },
+	 { "SUPPRESS_CUTS", 18, 18, &umr_bitfield_default },
+	 { "ES_WRITE_OPTIMIZE", 19, 19, &umr_bitfield_default },
+	 { "GS_WRITE_OPTIMIZE", 20, 20, &umr_bitfield_default },
+	 { "ONCHIP", 21, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_ONCHIP_CNTL[] = {
+	 { "ES_VERTS_PER_SUBGRP", 0, 10, &umr_bitfield_default },
+	 { "GS_PRIMS_PER_SUBGRP", 11, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_MODE_CNTL_0[] = {
+	 { "MSAA_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VPORT_SCISSOR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "LINE_STIPPLE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PKR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_MODE_CNTL_1[] = {
+	 { "WALK_SIZE", 0, 0, &umr_bitfield_default },
+	 { "WALK_ALIGNMENT", 1, 1, &umr_bitfield_default },
+	 { "WALK_ALIGN8_PRIM_FITS_ST", 2, 2, &umr_bitfield_default },
+	 { "WALK_FENCE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "WALK_FENCE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "SUPERTILE_WALK_ORDER_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "TILE_WALK_ORDER_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "TILE_COVER_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "TILE_COVER_NO_SCISSOR", 10, 10, &umr_bitfield_default },
+	 { "ZMM_LINE_EXTENT", 11, 11, &umr_bitfield_default },
+	 { "ZMM_LINE_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "ZMM_RECT_EXTENT", 13, 13, &umr_bitfield_default },
+	 { "KILL_PIX_POST_HI_Z", 14, 14, &umr_bitfield_default },
+	 { "KILL_PIX_POST_DETAIL_MASK", 15, 15, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLE", 16, 16, &umr_bitfield_default },
+	 { "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "MULTI_GPU_SUPERTILE_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE", 20, 23, &umr_bitfield_default },
+	 { "MULTI_GPU_PRIM_DISCARD_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "FORCE_EOV_CNTDWN_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "FORCE_EOV_REZ_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_PRIMITIVE_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_WATER_MARK", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_PER_ES[] = {
+	 { "GS_PER_ES", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ES_PER_GS[] = {
+	 { "ES_PER_GS", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_PER_VS[] = {
+	 { "GS_PER_VS", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_1[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_2[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_3[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_OUT_PRIM_TYPE[] = {
+	 { "OUTPRIM_TYPE", 0, 5, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_1", 8, 13, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_2", 16, 21, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_3", 22, 27, &umr_bitfield_default },
+	 { "UNIQUE_TYPE_PER_STREAM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_SIZE[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_MAX_SIZE[] = {
+	 { "MAX_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+	 { "SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "BUF_TYPE", 4, 5, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 6, 7, &umr_bitfield_default },
+	 { "ATC", 8, 8, &umr_bitfield_default },
+	 { "NOT_EOP", 9, 9, &umr_bitfield_default },
+	 { "REQ_PATH", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVEID_EN[] = {
+	 { "PRIMITIVEID_EN", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_RESET_ON_EOI", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVEID_RESET[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_EVENT_INITIATOR[] = {
+	 { "EVENT_TYPE", 0, 5, &umr_bitfield_default },
+	 { "ADDRESS_HI", 18, 26, &umr_bitfield_default },
+	 { "EXTENDED_EVENT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_EN[] = {
+	 { "RESET_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_0[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_1[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_MULTI_VGT_PARAM[] = {
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "PARTIAL_VS_WAVE_ON", 16, 16, &umr_bitfield_default },
+	 { "SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "PARTIAL_ES_WAVE_ON", 18, 18, &umr_bitfield_default },
+	 { "SWITCH_ON_EOI", 19, 19, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ESGS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_REUSE_OFF[] = {
+	 { "REUSE_OFF", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VTX_CNT_EN[] = {
+	 { "VTX_CNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_HTILE_SURFACE[] = {
+	 { "LINEAR", 0, 0, &umr_bitfield_default },
+	 { "FULL_CACHE", 1, 1, &umr_bitfield_default },
+	 { "HTILE_USES_PRELOAD_WIN", 2, 2, &umr_bitfield_default },
+	 { "PRELOAD", 3, 3, &umr_bitfield_default },
+	 { "PREFETCH_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PREFETCH_HEIGHT", 10, 15, &umr_bitfield_default },
+	 { "DST_OUTSIDE_ZERO_TO_ONE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE0[] = {
+	 { "COMPAREFUNC0", 0, 2, &umr_bitfield_default },
+	 { "COMPAREVALUE0", 4, 11, &umr_bitfield_default },
+	 { "COMPAREMASK0", 12, 19, &umr_bitfield_default },
+	 { "ENABLE0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE1[] = {
+	 { "COMPAREFUNC1", 0, 2, &umr_bitfield_default },
+	 { "COMPAREVALUE1", 4, 11, &umr_bitfield_default },
+	 { "COMPAREMASK1", 12, 19, &umr_bitfield_default },
+	 { "ENABLE1", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PRELOAD_CONTROL[] = {
+	 { "START_X", 0, 7, &umr_bitfield_default },
+	 { "START_Y", 8, 15, &umr_bitfield_default },
+	 { "MAX_X", 16, 23, &umr_bitfield_default },
+	 { "MAX_Y", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_0[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_0[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_1[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_1[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_2[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_2[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_3[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_3[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[] = {
+	 { "VERTEX_STRIDE", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_MAX_VERT_OUT[] = {
+	 { "MAX_VERT_OUT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_SHADER_STAGES_EN[] = {
+	 { "LS_EN", 0, 1, &umr_bitfield_default },
+	 { "HS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 4, &umr_bitfield_default },
+	 { "GS_EN", 5, 5, &umr_bitfield_default },
+	 { "VS_EN", 6, 7, &umr_bitfield_default },
+	 { "DYNAMIC_HS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_LS_HS_CONFIG[] = {
+	 { "NUM_PATCHES", 0, 7, &umr_bitfield_default },
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+	 { "HS_NUM_OUTPUT_CP", 14, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_1[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_2[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_3[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_PARAM[] = {
+	 { "TYPE", 0, 1, &umr_bitfield_default },
+	 { "PARTITIONING", 2, 4, &umr_bitfield_default },
+	 { "TOPOLOGY", 5, 7, &umr_bitfield_default },
+	 { "RESERVED_REDUC_AXIS", 8, 8, &umr_bitfield_default },
+	 { "DEPRECATED", 9, 9, &umr_bitfield_default },
+	 { "NUM_DS_WAVES_PER_SIMD", 10, 13, &umr_bitfield_default },
+	 { "DISABLE_DONUTS", 14, 14, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 15, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ALPHA_TO_MASK[] = {
+	 { "ALPHA_TO_MASK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET0", 8, 9, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET1", 10, 11, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET2", 12, 13, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET3", 14, 15, &umr_bitfield_default },
+	 { "OFFSET_ROUND", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DISPATCH_DRAW_INDEX[] = {
+	 { "MATCH_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[] = {
+	 { "POLY_OFFSET_NEG_NUM_DB_BITS", 0, 7, &umr_bitfield_default },
+	 { "POLY_OFFSET_DB_IS_FLOAT_FMT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_CLAMP[] = {
+	 { "CLAMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_INSTANCE_CNT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CNT", 2, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_CONFIG[] = {
+	 { "STREAMOUT_0_EN", 0, 0, &umr_bitfield_default },
+	 { "STREAMOUT_1_EN", 1, 1, &umr_bitfield_default },
+	 { "STREAMOUT_2_EN", 2, 2, &umr_bitfield_default },
+	 { "STREAMOUT_3_EN", 3, 3, &umr_bitfield_default },
+	 { "RAST_STREAM", 4, 6, &umr_bitfield_default },
+	 { "RAST_STREAM_MASK", 8, 11, &umr_bitfield_default },
+	 { "USE_RAST_STREAM_MASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_CONFIG[] = {
+	 { "STREAM_0_BUFFER_EN", 0, 3, &umr_bitfield_default },
+	 { "STREAM_1_BUFFER_EN", 4, 7, &umr_bitfield_default },
+	 { "STREAM_2_BUFFER_EN", 8, 11, &umr_bitfield_default },
+	 { "STREAM_3_BUFFER_EN", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_0[] = {
+	 { "DISTANCE_0", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_1", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_2", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_3", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_4", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_5", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_6", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_1[] = {
+	 { "DISTANCE_8", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_9", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_10", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_11", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_12", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_13", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_14", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_CNTL[] = {
+	 { "EXPAND_LINE_WIDTH", 9, 9, &umr_bitfield_default },
+	 { "LAST_PIXEL", 10, 10, &umr_bitfield_default },
+	 { "PERPENDICULAR_ENDCAP_ENA", 11, 11, &umr_bitfield_default },
+	 { "DX10_DIAMOND_TEST_ENA", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_CONFIG[] = {
+	 { "MSAA_NUM_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "AA_MASK_CENTROID_DTMN", 4, 4, &umr_bitfield_default },
+	 { "MAX_SAMPLE_DIST", 13, 16, &umr_bitfield_default },
+	 { "MSAA_EXPOSED_SAMPLES", 20, 22, &umr_bitfield_default },
+	 { "DETAIL_TO_EXPOSED_MODE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_VTX_CNTL[] = {
+	 { "PIX_CENTER", 0, 0, &umr_bitfield_default },
+	 { "ROUND_MODE", 1, 2, &umr_bitfield_default },
+	 { "QUANT_MODE", 3, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_VERT_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_VERT_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_HORZ_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_HORZ_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_MASK_X0Y0_X1Y0[] = {
+	 { "AA_MASK_X0Y0", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_MASK_X0Y1_X1Y1[] = {
+	 { "AA_MASK_X0Y1", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VERTEX_REUSE_BLOCK_CNTL[] = {
+	 { "VTX_REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_OUT_DEALLOC_CNTL[] = {
+	 { "DEALLOC_DIST", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG11[] = {
+	 { "clipsm3_clip_to_clipga_event", 0, 0, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_event", 1, 1, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_event", 2, 2, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_event", 3, 3, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_clip_primitive", 4, 4, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_clip_primitive", 5, 5, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_clip_primitive", 6, 6, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_clip_primitive", 7, 7, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_clip_to_outsm_cnt", 8, 11, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_clip_to_outsm_cnt", 12, 15, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_clip_to_outsm_cnt", 16, 19, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_clip_to_outsm_cnt", 20, 23, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_prim_valid", 24, 24, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_prim_valid", 25, 25, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_prim_valid", 26, 26, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_prim_valid", 27, 27, &umr_bitfield_default },
+	 { "clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt", 28, 28, &umr_bitfield_default },
+	 { "clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG11[] = {
+	 { "tm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "tm_noif_busy_q", 1, 1, &umr_bitfield_default },
+	 { "tm_out_busy_q", 2, 2, &umr_bitfield_default },
+	 { "es_rb_dealloc_fifo_busy", 3, 3, &umr_bitfield_default },
+	 { "vs_dealloc_tbl_busy", 4, 4, &umr_bitfield_default },
+	 { "SPARE1", 5, 5, &umr_bitfield_default },
+	 { "spi_gsthread_fifo_busy", 6, 6, &umr_bitfield_default },
+	 { "spi_esthread_fifo_busy", 7, 7, &umr_bitfield_default },
+	 { "hold_eswave", 8, 8, &umr_bitfield_default },
+	 { "es_rb_roll_over_r3", 9, 9, &umr_bitfield_default },
+	 { "counters_busy_r0", 10, 10, &umr_bitfield_default },
+	 { "counters_avail_r0", 11, 11, &umr_bitfield_default },
+	 { "counters_available_r0", 12, 12, &umr_bitfield_default },
+	 { "vs_event_fifo_rtr", 13, 13, &umr_bitfield_default },
+	 { "VGT_SPI_gsthread_rtr_q", 14, 14, &umr_bitfield_default },
+	 { "VGT_SPI_esthread_rtr_q", 15, 15, &umr_bitfield_default },
+	 { "gs_issue_rtr", 16, 16, &umr_bitfield_default },
+	 { "tm_pt_event_rtr", 17, 17, &umr_bitfield_default },
+	 { "SPARE0", 18, 18, &umr_bitfield_default },
+	 { "gs_r0_rtr", 19, 19, &umr_bitfield_default },
+	 { "es_r0_rtr", 20, 20, &umr_bitfield_default },
+	 { "gog_tm_vs_event_rtr", 21, 21, &umr_bitfield_default },
+	 { "tm_rcm_gs_event_rtr", 22, 22, &umr_bitfield_default },
+	 { "tm_rcm_gs_tbl_rtr", 23, 23, &umr_bitfield_default },
+	 { "tm_rcm_es_tbl_rtr", 24, 24, &umr_bitfield_default },
+	 { "vs_event_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "vs_event_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "es_rb_dealloc_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "vs_dealloc_tbl_full", 28, 28, &umr_bitfield_default },
+	 { "send_event_q", 29, 29, &umr_bitfield_default },
+	 { "es_tbl_empty", 30, 30, &umr_bitfield_default },
+	 { "no_active_states_r0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG12[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_priority_available_vte_out_clip", 8, 12, &umr_bitfield_default },
+	 { "clip_priority_available_clip_verts", 13, 17, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_out", 18, 19, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_vert", 20, 21, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_load", 22, 23, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_clip_primitive", 24, 24, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 25, 25, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_clip_primitive", 26, 26, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 27, 27, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_clip_primitive", 28, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_clip_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG12[] = {
+	 { "gs_state0_r0_q", 0, 2, &umr_bitfield_default },
+	 { "gs_state1_r0_q", 3, 5, &umr_bitfield_default },
+	 { "gs_state2_r0_q", 6, 8, &umr_bitfield_default },
+	 { "gs_state3_r0_q", 9, 11, &umr_bitfield_default },
+	 { "gs_state4_r0_q", 12, 14, &umr_bitfield_default },
+	 { "gs_state5_r0_q", 15, 17, &umr_bitfield_default },
+	 { "gs_state6_r0_q", 18, 20, &umr_bitfield_default },
+	 { "gs_state7_r0_q", 21, 23, &umr_bitfield_default },
+	 { "gs_state8_r0_q", 24, 26, &umr_bitfield_default },
+	 { "gs_state9_r0_q", 27, 29, &umr_bitfield_default },
+	 { "hold_eswave_eop", 30, 30, &umr_bitfield_default },
+	 { "SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_ADDR_LO[] = {
+	 { "ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_LO[] = {
+	 { "DATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_HI[] = {
+	 { "DATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_LAST_FENCE_LO[] = {
+	 { "LAST_FENCE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_LAST_FENCE_HI[] = {
+	 { "LAST_FENCE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_ADDR_LO[] = {
+	 { "STREAM_OUT_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "STREAM_OUT_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_ADDR_HI[] = {
+	 { "STREAM_OUT_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_ADDR_LO[] = {
+	 { "PIPE_STATS_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "PIPE_STATS_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_ADDR_HI[] = {
+	 { "PIPE_STATS_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_LO[] = {
+	 { "IAVERT_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_HI[] = {
+	 { "IAVERT_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_LO[] = {
+	 { "IAPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_HI[] = {
+	 { "IAPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_LO[] = {
+	 { "GSPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_HI[] = {
+	 { "GSPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_LO[] = {
+	 { "VSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_HI[] = {
+	 { "VSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_LO[] = {
+	 { "GSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_HI[] = {
+	 { "GSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_LO[] = {
+	 { "HSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_HI[] = {
+	 { "HSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_LO[] = {
+	 { "DSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_HI[] = {
+	 { "DSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CINVOC_COUNT_LO[] = {
+	 { "CINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CINVOC_COUNT_HI[] = {
+	 { "CINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CPRIM_COUNT_LO[] = {
+	 { "CPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CPRIM_COUNT_HI[] = {
+	 { "CPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_LO[] = {
+	 { "PSINVOC_COUNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_HI[] = {
+	 { "PSINVOC_COUNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_LO[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_HI[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_LO[] = {
+	 { "CSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_HI[] = {
+	 { "CSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STRMOUT_CNTL[] = {
+	 { "OFFSET_UPDATE_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_UMSK[] = {
+	 { "OBSOLETE_UMSK", 0, 7, &umr_bitfield_default },
+	 { "OBSOLETE_SWAP", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_ADDR[] = {
+	 { "OBSOLETE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_ADDR_LO[] = {
+	 { "MEM_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_ADDR_HI[] = {
+	 { "MEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "CS_PS_SEL", 16, 16, &umr_bitfield_default },
+	 { "COMMAND", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_LAST_CS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_LAST_PS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WADDR_LO[] = {
+	 { "ME_MC_WADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ME_MC_WADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WADDR_HI[] = {
+	 { "ME_MC_WADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WDATA_LO[] = {
+	 { "ME_MC_WDATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WDATA_HI[] = {
+	 { "ME_MC_WDATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_RADDR_LO[] = {
+	 { "ME_MC_RADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ME_MC_RADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_RADDR_HI[] = {
+	 { "ME_MC_RADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SEM_WAIT_TIMER[] = {
+	 { "SEM_WAIT_TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SIG_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SIG_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_REG_MEM_TIMEOUT[] = {
+	 { "WAIT_REG_MEM_TIMEOUT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_CONTROL[] = {
+	 { "SRC_ATC", 12, 12, &umr_bitfield_default },
+	 { "SRC_CACHE_POLICY", 13, 14, &umr_bitfield_default },
+	 { "SRC_VOLATILE", 15, 15, &umr_bitfield_default },
+	 { "DST_SELECT", 20, 21, &umr_bitfield_default },
+	 { "DST_ATC", 24, 24, &umr_bitfield_default },
+	 { "DST_CACHE_POLICY", 25, 26, &umr_bitfield_default },
+	 { "DST_VOLATILE", 27, 27, &umr_bitfield_default },
+	 { "SRC_SELECT", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_CONTROL[] = {
+	 { "SRC_ATC", 12, 12, &umr_bitfield_default },
+	 { "SRC_CACHE_POLICY", 13, 14, &umr_bitfield_default },
+	 { "SRC_VOLATILE", 15, 15, &umr_bitfield_default },
+	 { "DST_SELECT", 20, 21, &umr_bitfield_default },
+	 { "DST_ATC", 24, 24, &umr_bitfield_default },
+	 { "DST_CACHE_POLICY", 25, 26, &umr_bitfield_default },
+	 { "DST_VOLATILE", 27, 27, &umr_bitfield_default },
+	 { "SRC_SELECT", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_BASE_HI[] = {
+	 { "COHER_BASE_HI_256B", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_START_DELAY[] = {
+	 { "START_DELAY_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_CNTL[] = {
+	 { "DEST_BASE_0_ENA", 0, 0, &umr_bitfield_default },
+	 { "DEST_BASE_1_ENA", 1, 1, &umr_bitfield_default },
+	 { "CB0_DEST_BASE_ENA", 6, 6, &umr_bitfield_default },
+	 { "CB1_DEST_BASE_ENA", 7, 7, &umr_bitfield_default },
+	 { "CB2_DEST_BASE_ENA", 8, 8, &umr_bitfield_default },
+	 { "CB3_DEST_BASE_ENA", 9, 9, &umr_bitfield_default },
+	 { "CB4_DEST_BASE_ENA", 10, 10, &umr_bitfield_default },
+	 { "CB5_DEST_BASE_ENA", 11, 11, &umr_bitfield_default },
+	 { "CB6_DEST_BASE_ENA", 12, 12, &umr_bitfield_default },
+	 { "CB7_DEST_BASE_ENA", 13, 13, &umr_bitfield_default },
+	 { "DB_DEST_BASE_ENA", 14, 14, &umr_bitfield_default },
+	 { "TCL1_VOL_ACTION_ENA", 15, 15, &umr_bitfield_default },
+	 { "TC_VOL_ACTION_ENA", 16, 16, &umr_bitfield_default },
+	 { "TC_WB_ACTION_ENA", 18, 18, &umr_bitfield_default },
+	 { "DEST_BASE_2_ENA", 19, 19, &umr_bitfield_default },
+	 { "DEST_BASE_3_ENA", 21, 21, &umr_bitfield_default },
+	 { "TCL1_ACTION_ENA", 22, 22, &umr_bitfield_default },
+	 { "TC_ACTION_ENA", 23, 23, &umr_bitfield_default },
+	 { "CB_ACTION_ENA", 25, 25, &umr_bitfield_default },
+	 { "DB_ACTION_ENA", 26, 26, &umr_bitfield_default },
+	 { "SH_KCACHE_ACTION_ENA", 27, 27, &umr_bitfield_default },
+	 { "SH_KCACHE_VOL_ACTION_ENA", 28, 28, &umr_bitfield_default },
+	 { "SH_ICACHE_ACTION_ENA", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_SIZE[] = {
+	 { "COHER_SIZE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_BASE[] = {
+	 { "COHER_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_STATUS[] = {
+	 { "MATCHING_GFX_CNTX", 0, 7, &umr_bitfield_default },
+	 { "MEID", 24, 25, &umr_bitfield_default },
+	 { "PHASE1_STATUS", 30, 30, &umr_bitfield_default },
+	 { "STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_CNTL[] = {
+	 { "MIN_AVAILSZ", 4, 5, &umr_bitfield_default },
+	 { "BUFFER_DEPTH", 16, 19, &umr_bitfield_default },
+	 { "PIO_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
+	 { "PIO_FIFO_FULL", 29, 29, &umr_bitfield_default },
+	 { "PIO_COUNT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_READ_TAGS[] = {
+	 { "DMA_READ_TAG", 0, 25, &umr_bitfield_default },
+	 { "DMA_READ_TAG_VALID", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_SIZE_HI[] = {
+	 { "COHER_SIZE_HI_256B", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_IB_CONTROL[] = {
+	 { "IB_EN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_LOAD_CONTROL[] = {
+	 { "CONFIG_REG_EN", 0, 0, &umr_bitfield_default },
+	 { "CNTX_REG_EN", 1, 1, &umr_bitfield_default },
+	 { "UCONFIG_REG_EN", 15, 15, &umr_bitfield_default },
+	 { "SH_GFX_REG_EN", 16, 16, &umr_bitfield_default },
+	 { "SH_CS_REG_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_OFFSET[] = {
+	 { "RB_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_OFFSET[] = {
+	 { "IB1_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_OFFSET[] = {
+	 { "IB2_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_PREAMBLE_BEGIN[] = {
+	 { "IB1_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_PREAMBLE_END[] = {
+	 { "IB1_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_PREAMBLE_BEGIN[] = {
+	 { "IB2_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_PREAMBLE_END[] = {
+	 { "IB2_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_OFFSET[] = {
+	 { "IB1_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_OFFSET[] = {
+	 { "IB2_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_COUNTER[] = {
+	 { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BASE_LO[] = {
+	 { "INIT_BASE_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BASE_HI[] = {
+	 { "INIT_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BUFSZ[] = {
+	 { "INIT_BUFSZ", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BASE_LO[] = {
+	 { "ST_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BASE_HI[] = {
+	 { "ST_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BUFSZ[] = {
+	 { "ST_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_EVENT_CNTL[] = {
+	 { "WBINV_TC_OP", 0, 6, &umr_bitfield_default },
+	 { "WBINV_ACTION_ENA", 12, 17, &umr_bitfield_default },
+	 { "CACHE_CONTROL", 25, 26, &umr_bitfield_default },
+	 { "EOP_VOLATILE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_CNTL[] = {
+	 { "CNTX_ID", 0, 15, &umr_bitfield_default },
+	 { "DST_SEL", 16, 17, &umr_bitfield_default },
+	 { "INT_SEL", 24, 26, &umr_bitfield_default },
+	 { "DATA_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_GFX_INDEX[] = {
+	 { "INSTANCE_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 15, &umr_bitfield_default },
+	 { "SE_INDEX", 16, 23, &umr_bitfield_default },
+	 { "SH_BROADCAST_WRITES", 29, 29, &umr_bitfield_default },
+	 { "INSTANCE_BROADCAST_WRITES", 30, 30, &umr_bitfield_default },
+	 { "SE_BROADCAST_WRITES", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ESGS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_NUM_INDICES[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_RING_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HS_OFFCHIP_PARAM[] = {
+	 { "OFFCHIP_BUFFERING", 0, 8, &umr_bitfield_default },
+	 { "OFFCHIP_GRANULARITY", 9, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_MEMORY_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_VALUE[] = {
+	 { "LINE_STIPPLE_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_STIPPLE_STATE[] = {
+	 { "CURRENT_PTR", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MIN_0[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MAX_0[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MIN_1[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MAX_1[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_CACHES[] = {
+	 { "INST_INVALIDATE", 0, 0, &umr_bitfield_default },
+	 { "DATA_INVALIDATE", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE_VOLATILE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CS_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CS_BC_BASE_ADDR_HI[] = {
+	 { "ADDRESS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT0_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT0_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT1_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT1_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT2_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT2_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT3_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT3_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ZPASS_COUNT_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ZPASS_COUNT_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_ADDR[] = {
+	 { "READ_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_DATA[] = {
+	 { "READ_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_ADDR[] = {
+	 { "BURST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_COUNT[] = {
+	 { "BURST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_DATA[] = {
+	 { "BURST_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_BURST_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_BURST_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WRITE_COMPLETE[] = {
+	 { "WRITE_COMPLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_CNTL[] = {
+	 { "AINC", 0, 5, &umr_bitfield_default },
+	 { "UNUSED1", 6, 7, &umr_bitfield_default },
+	 { "DMODE", 8, 8, &umr_bitfield_default },
+	 { "UNUSED2", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_COMPLETE[] = {
+	 { "COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "UNUSED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OFFSET0[] = {
+	 { "OFFSET0", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OFFSET1[] = {
+	 { "OFFSET1", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_DST[] = {
+	 { "DST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OP[] = {
+	 { "OP", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_CNTL[] = {
+	 { "INDEX", 0, 5, &umr_bitfield_default },
+	 { "UNUSED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE[] = {
+	 { "FLAG", 0, 0, &umr_bitfield_default },
+	 { "COUNTER", 1, 12, &umr_bitfield_default },
+	 { "TYPE", 13, 13, &umr_bitfield_default },
+	 { "DED", 14, 14, &umr_bitfield_default },
+	 { "RELEASE_ALL", 15, 15, &umr_bitfield_default },
+	 { "HEAD_QUEUE", 16, 26, &umr_bitfield_default },
+	 { "HEAD_VALID", 27, 27, &umr_bitfield_default },
+	 { "HEAD_FLAG", 28, 28, &umr_bitfield_default },
+	 { "UNUSED1", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_CNT[] = {
+	 { "RESOURCE_CNT", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_CNTL[] = {
+	 { "INDEX", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_COUNTER[] = {
+	 { "SPACE_AVAILABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_ADDRESS[] = {
+	 { "DS_ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "CRAWLER_TYPE", 16, 19, &umr_bitfield_default },
+	 { "CRAWLER", 20, 23, &umr_bitfield_default },
+	 { "UNUSED", 24, 29, &umr_bitfield_default },
+	 { "NO_ALLOC", 30, 30, &umr_bitfield_default },
+	 { "ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_INCDEC[] = {
+	 { "VALUE", 0, 30, &umr_bitfield_default },
+	 { "INCDEC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RING_SIZE[] = {
+	 { "RING_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG13[] = {
+	 { "clprim_in_back_state_var_indx", 0, 2, &umr_bitfield_default },
+	 { "point_clip_candidate", 3, 3, &umr_bitfield_default },
+	 { "prim_nan_kill", 4, 4, &umr_bitfield_default },
+	 { "clprim_clip_primitive", 5, 5, &umr_bitfield_default },
+	 { "clprim_cull_primitive", 6, 6, &umr_bitfield_default },
+	 { "prim_back_valid", 7, 7, &umr_bitfield_default },
+	 { "vertval_bits_vertex_cc_next_valid", 8, 11, &umr_bitfield_default },
+	 { "clipcc_vertex_store_indx", 12, 13, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_empty", 14, 14, &umr_bitfield_default },
+	 { "clipcode_fifo_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_empty", 16, 16, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_out_cnt", 17, 20, &umr_bitfield_default },
+	 { "outsm_clr_rd_orig_vertices", 21, 22, &umr_bitfield_default },
+	 { "outsm_clr_rd_clipsm_wait", 23, 23, &umr_bitfield_default },
+	 { "outsm_clr_fifo_contents", 24, 28, &umr_bitfield_default },
+	 { "outsm_clr_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "outsm_clr_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "outsm_clr_fifo_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG13[] = {
+	 { "gs_state10_r0_q", 0, 2, &umr_bitfield_default },
+	 { "gs_state11_r0_q", 3, 5, &umr_bitfield_default },
+	 { "gs_state12_r0_q", 6, 8, &umr_bitfield_default },
+	 { "gs_state13_r0_q", 9, 11, &umr_bitfield_default },
+	 { "gs_state14_r0_q", 12, 14, &umr_bitfield_default },
+	 { "gs_state15_r0_q", 15, 17, &umr_bitfield_default },
+	 { "gs_tbl_wrptr_r0_q_3_0", 18, 21, &umr_bitfield_default },
+	 { "gsfetch_done_fifo_cnt_q_not_0", 22, 22, &umr_bitfield_default },
+	 { "gsfetch_done_cnt_q_not_0", 23, 23, &umr_bitfield_default },
+	 { "es_tbl_full", 24, 24, &umr_bitfield_default },
+	 { "SPARE1", 25, 25, &umr_bitfield_default },
+	 { "SPARE0", 26, 26, &umr_bitfield_default },
+	 { "active_cm_sm_r0_q", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
+	 { "SPM_PERFMON_STATE", 4, 7, &umr_bitfield_default },
+	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_OBJECT[] = {
+	 { "OBJECT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_OBJECT_COUNTER[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_MASK_HI[] = {
+	 { "WINDOW_MASK_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_HI[] = {
+	 { "WINDOW_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_LO[] = {
+	 { "MIN", 0, 15, &umr_bitfield_default },
+	 { "MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_CNTL[] = {
+	 { "DISABLE_DRAW_WINDOW_LO_MAX", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_DRAW_WINDOW_LO_MIN", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_DRAW_WINDOW_HI", 2, 2, &umr_bitfield_default },
+	 { "MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER_SEID_MASK[] = {
+	 { "PERF_SEID_IGNORE_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER_BINS[] = {
+	 { "BIN0_MIN", 0, 3, &umr_bitfield_default },
+	 { "BIN0_MAX", 4, 7, &umr_bitfield_default },
+	 { "BIN1_MIN", 8, 11, &umr_bitfield_default },
+	 { "BIN1_MAX", 12, 15, &umr_bitfield_default },
+	 { "BIN2_MIN", 16, 19, &umr_bitfield_default },
+	 { "BIN2_MAX", 20, 23, &umr_bitfield_default },
+	 { "BIN3_MIN", 24, 27, &umr_bitfield_default },
+	 { "BIN3_MAX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+	 { "CNTR_RATE", 8, 12, &umr_bitfield_default },
+	 { "DISABLE_FLUSH", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL2[] = {
+	 { "FORCE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 17, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 17, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER_FILTER[] = {
+	 { "OP_FILTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OP_FILTER_SEL", 1, 3, &umr_bitfield_default },
+	 { "FORMAT_FILTER_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FORMAT_FILTER_SEL", 5, 9, &umr_bitfield_default },
+	 { "CLEAR_FILTER_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "CLEAR_FILTER_SEL", 11, 11, &umr_bitfield_default },
+	 { "MRT_FILTER_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "MRT_FILTER_SEL", 13, 15, &umr_bitfield_default },
+	 { "NUM_SAMPLES_FILTER_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "NUM_SAMPLES_FILTER_SEL", 18, 20, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS_FILTER_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS_FILTER_SEL", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 18, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 18, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_CNTL[] = {
+	 { "RESERVED1", 0, 11, &umr_bitfield_default },
+	 { "PERFMON_RING_MODE", 12, 13, &umr_bitfield_default },
+	 { "RESERVED", 14, 15, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_BASE_LO[] = {
+	 { "RING_BASE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_BASE_HI[] = {
+	 { "RING_BASE_HI", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_SIZE[] = {
+	 { "RING_BASE_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_SEGMENT_SIZE[] = {
+	 { "PERFMON_SEGMENT_SIZE", 0, 7, &umr_bitfield_default },
+	 { "RESERVED1", 8, 10, &umr_bitfield_default },
+	 { "GLOBAL_NUM_LINE", 11, 15, &umr_bitfield_default },
+	 { "SE0_NUM_LINE", 16, 20, &umr_bitfield_default },
+	 { "SE1_NUM_LINE", 21, 25, &umr_bitfield_default },
+	 { "SE2_NUM_LINE", 26, 30, &umr_bitfield_default },
+	 { "RESERVED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SE_MUXSEL_ADDR[] = {
+	 { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SE_MUXSEL_DATA[] = {
+	 { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GLOBAL_MUXSEL_ADDR[] = {
+	 { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GLOBAL_MUXSEL_DATA[] = {
+	 { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_RING_RDPTR[] = {
+	 { "PERFMON_RING_RDPTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SEGMENT_THRESHOLD[] = {
+	 { "NUM_SEGMENT_THRESHOLD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 2, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG14[] = {
+	 { "clprim_in_back_vertex_store_indx_2", 0, 5, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_1", 6, 11, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_0", 12, 17, &umr_bitfield_default },
+	 { "outputclprimtoclip_null_primitive", 18, 18, &umr_bitfield_default },
+	 { "clprim_in_back_end_of_packet", 19, 19, &umr_bitfield_default },
+	 { "clprim_in_back_first_prim_of_slot", 20, 20, &umr_bitfield_default },
+	 { "clprim_in_back_deallocate_slot", 21, 23, &umr_bitfield_default },
+	 { "clprim_in_back_event_id", 24, 29, &umr_bitfield_default },
+	 { "clprim_in_back_event", 30, 30, &umr_bitfield_default },
+	 { "prim_back_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG14[] = {
+	 { "SPARE3", 0, 3, &umr_bitfield_default },
+	 { "gsfetch_done_fifo_full", 4, 4, &umr_bitfield_default },
+	 { "gs_rb_space_avail_r0", 5, 5, &umr_bitfield_default },
+	 { "smx_es_done_cnt_r0_q_not_0", 6, 6, &umr_bitfield_default },
+	 { "SPARE8", 7, 8, &umr_bitfield_default },
+	 { "vs_done_cnt_q_not_0", 9, 9, &umr_bitfield_default },
+	 { "es_flush_cnt_busy_q", 10, 10, &umr_bitfield_default },
+	 { "gs_tbl_full_r0", 11, 11, &umr_bitfield_default },
+	 { "SPARE2", 12, 20, &umr_bitfield_default },
+	 { "se1spi_gsthread_fifo_busy", 21, 21, &umr_bitfield_default },
+	 { "SPARE", 22, 24, &umr_bitfield_default },
+	 { "VGT_SE1SPI_gsthread_rtr_q", 25, 25, &umr_bitfield_default },
+	 { "smx1_es_done_cnt_r0_q_not_0", 26, 26, &umr_bitfield_default },
+	 { "se1spi_esthread_fifo_busy", 27, 27, &umr_bitfield_default },
+	 { "SPARE1", 28, 28, &umr_bitfield_default },
+	 { "gsfetch_done_se1_cnt_q_not_0", 29, 29, &umr_bitfield_default },
+	 { "SPARE0", 30, 30, &umr_bitfield_default },
+	 { "VGT_SE1SPI_esthread_rtr_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG15[] = {
+	 { "vertval_bits_vertex_vertex_store_msb", 0, 15, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_2", 16, 20, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_1", 21, 25, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_0", 26, 30, &umr_bitfield_default },
+	 { "primic_to_clprim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG15[] = {
+	 { "cm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "counters_busy_q", 1, 1, &umr_bitfield_default },
+	 { "output_fifo_empty", 2, 2, &umr_bitfield_default },
+	 { "output_fifo_full", 3, 3, &umr_bitfield_default },
+	 { "counters_full", 4, 4, &umr_bitfield_default },
+	 { "active_sm_q", 5, 9, &umr_bitfield_default },
+	 { "entry_rdptr_q", 10, 14, &umr_bitfield_default },
+	 { "cntr_tbl_wrptr_q", 15, 19, &umr_bitfield_default },
+	 { "SPARE25", 20, 25, &umr_bitfield_default },
+	 { "st_cut_mode_q", 26, 27, &umr_bitfield_default },
+	 { "gs_done_array_q_not_0", 28, 28, &umr_bitfield_default },
+	 { "SPARE31", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_SM_CTRL_REG[] = {
+	 { "ON_SEQ_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_SEQ_DELAY", 4, 11, &umr_bitfield_default },
+	 { "MGCG_ENABLED", 12, 12, &umr_bitfield_default },
+	 { "BASE_MODE", 16, 16, &umr_bitfield_default },
+	 { "SM_MODE", 17, 19, &umr_bitfield_default },
+	 { "SM_MODE_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "OVERRIDE", 21, 21, &umr_bitfield_default },
+	 { "LS_OVERRIDE", 22, 22, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD_EN", 23, 23, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_RD_CTRL_REG[] = {
+	 { "ROW_MUX_SEL", 0, 4, &umr_bitfield_default },
+	 { "REG_MUX_SEL", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_RD_REG[] = {
+	 { "READ_DATA", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_USER_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SPI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "ALL_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "GRP3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "GRP2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "GRP1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "GRP0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_PC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "BACK_CLK_ON_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "FRONT_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_BCI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "CORE6_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "CORE5_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "CORE4_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_VGT_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "GS_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_IA_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_WD_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "ADC_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "RBIU_INPUT_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_PA_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SU_CLK_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CL_CLK_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_CLK_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SQ_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SQG_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_ALU_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TEX_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LDS_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_POWER_THROTTLE[] = {
+	 { "MIN_POWER", 0, 13, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 29, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_POWER_THROTTLE2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL1[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL2[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL3[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL4[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_CGTT_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CGTT_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_TCP_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_TCI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_GDS_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_CGTT_CLK_CTRL_0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCS_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CP_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CPF_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CPC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_RLC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_HV_VMID_CTRL[] = {
+	 { "DEFAULT_VMID", 0, 3, &umr_bitfield_default },
+	 { "ALLOWED_VMID_MASK", 4, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_PIPE_PRIORITY[] = {
+	 { "HP_PIPE_SELECT", 0, 0, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gfx72_regs.i b/src/lib/ip/gfx72_regs.i
new file mode 100644
index 0000000..0b19bf7
--- /dev/null
+++ b/src/lib/ip/gfx72_regs.i
@@ -0,0 +1,2480 @@
+	{ "ixCLIPPER_DEBUG_REG00", REG_SMC, 0x0, &ixCLIPPER_DEBUG_REG00[0], sizeof(ixCLIPPER_DEBUG_REG00)/sizeof(ixCLIPPER_DEBUG_REG00[0]), 0, 0 },
+	{ "ixPA_SC_DEBUG_REG0", REG_SMC, 0x0, &ixPA_SC_DEBUG_REG0[0], sizeof(ixPA_SC_DEBUG_REG0)/sizeof(ixPA_SC_DEBUG_REG0[0]), 0, 0 },
+	{ "mmCSPRIV_CONNECT", REG_MMIO, 0x0, &mmCSPRIV_CONNECT[0], sizeof(mmCSPRIV_CONNECT)/sizeof(mmCSPRIV_CONNECT[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG0", REG_SMC, 0x0, &ixWD_DEBUG_REG0[0], sizeof(ixWD_DEBUG_REG0)/sizeof(ixWD_DEBUG_REG0[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG01", REG_SMC, 0x1, &ixCLIPPER_DEBUG_REG01[0], sizeof(ixCLIPPER_DEBUG_REG01)/sizeof(ixCLIPPER_DEBUG_REG01[0]), 0, 0 },
+	{ "ixPA_SC_DEBUG_REG1", REG_SMC, 0x1, &ixPA_SC_DEBUG_REG1[0], sizeof(ixPA_SC_DEBUG_REG1)/sizeof(ixPA_SC_DEBUG_REG1[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG1", REG_SMC, 0x1, &ixGDS_DEBUG_REG1[0], sizeof(ixGDS_DEBUG_REG1)/sizeof(ixGDS_DEBUG_REG1[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG1", REG_SMC, 0x1, &ixWD_DEBUG_REG1[0], sizeof(ixWD_DEBUG_REG1)/sizeof(ixWD_DEBUG_REG1[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG16", REG_SMC, 0x10, &ixCLIPPER_DEBUG_REG16[0], sizeof(ixCLIPPER_DEBUG_REG16)/sizeof(ixCLIPPER_DEBUG_REG16[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT0_3", REG_SMC, 0x10, &ixDIDT_SQ_WEIGHT0_3[0], sizeof(ixDIDT_SQ_WEIGHT0_3)/sizeof(ixDIDT_SQ_WEIGHT0_3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG16", REG_SMC, 0x10, &ixVGT_DEBUG_REG16[0], sizeof(ixVGT_DEBUG_REG16)/sizeof(ixVGT_DEBUG_REG16[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG17", REG_SMC, 0x11, &ixCLIPPER_DEBUG_REG17[0], sizeof(ixCLIPPER_DEBUG_REG17)/sizeof(ixCLIPPER_DEBUG_REG17[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT4_7", REG_SMC, 0x11, &ixDIDT_SQ_WEIGHT4_7[0], sizeof(ixDIDT_SQ_WEIGHT4_7)/sizeof(ixDIDT_SQ_WEIGHT4_7[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG17", REG_SMC, 0x11, &ixVGT_DEBUG_REG17[0], sizeof(ixVGT_DEBUG_REG17)/sizeof(ixVGT_DEBUG_REG17[0]), 0, 0 },
+	{ "ixSQ_WAVE_MODE", REG_SMC, 0x11, &ixSQ_WAVE_MODE[0], sizeof(ixSQ_WAVE_MODE)/sizeof(ixSQ_WAVE_MODE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG18", REG_SMC, 0x12, &ixCLIPPER_DEBUG_REG18[0], sizeof(ixCLIPPER_DEBUG_REG18)/sizeof(ixCLIPPER_DEBUG_REG18[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT8_11", REG_SMC, 0x12, &ixDIDT_SQ_WEIGHT8_11[0], sizeof(ixDIDT_SQ_WEIGHT8_11)/sizeof(ixDIDT_SQ_WEIGHT8_11[0]), 0, 0 },
+	{ "ixSQ_WAVE_STATUS", REG_SMC, 0x12, &ixSQ_WAVE_STATUS[0], sizeof(ixSQ_WAVE_STATUS)/sizeof(ixSQ_WAVE_STATUS[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG19", REG_SMC, 0x13, &ixCLIPPER_DEBUG_REG19[0], sizeof(ixCLIPPER_DEBUG_REG19)/sizeof(ixCLIPPER_DEBUG_REG19[0]), 0, 0 },
+	{ "ixSQ_WAVE_TRAPSTS", REG_SMC, 0x13, &ixSQ_WAVE_TRAPSTS[0], sizeof(ixSQ_WAVE_TRAPSTS)/sizeof(ixSQ_WAVE_TRAPSTS[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG0", REG_SMC, 0x14, &ixSXIFCCG_DEBUG_REG0[0], sizeof(ixSXIFCCG_DEBUG_REG0)/sizeof(ixSXIFCCG_DEBUG_REG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG20", REG_SMC, 0x14, &ixVGT_DEBUG_REG20[0], sizeof(ixVGT_DEBUG_REG20)/sizeof(ixVGT_DEBUG_REG20[0]), 0, 0 },
+	{ "ixSQ_WAVE_HW_ID", REG_SMC, 0x14, &ixSQ_WAVE_HW_ID[0], sizeof(ixSQ_WAVE_HW_ID)/sizeof(ixSQ_WAVE_HW_ID[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG1", REG_SMC, 0x15, &ixSXIFCCG_DEBUG_REG1[0], sizeof(ixSXIFCCG_DEBUG_REG1)/sizeof(ixSXIFCCG_DEBUG_REG1[0]), 0, 0 },
+	{ "ixSQ_WAVE_GPR_ALLOC", REG_SMC, 0x15, &ixSQ_WAVE_GPR_ALLOC[0], sizeof(ixSQ_WAVE_GPR_ALLOC)/sizeof(ixSQ_WAVE_GPR_ALLOC[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG21", REG_SMC, 0x15, &ixVGT_DEBUG_REG21[0], sizeof(ixVGT_DEBUG_REG21)/sizeof(ixVGT_DEBUG_REG21[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG2", REG_SMC, 0x16, &ixSXIFCCG_DEBUG_REG2[0], sizeof(ixSXIFCCG_DEBUG_REG2)/sizeof(ixSXIFCCG_DEBUG_REG2[0]), 0, 0 },
+	{ "ixSQ_WAVE_LDS_ALLOC", REG_SMC, 0x16, &ixSQ_WAVE_LDS_ALLOC[0], sizeof(ixSQ_WAVE_LDS_ALLOC)/sizeof(ixSQ_WAVE_LDS_ALLOC[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG22", REG_SMC, 0x16, &ixVGT_DEBUG_REG22[0], sizeof(ixVGT_DEBUG_REG22)/sizeof(ixVGT_DEBUG_REG22[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG3", REG_SMC, 0x17, &ixSXIFCCG_DEBUG_REG3[0], sizeof(ixSXIFCCG_DEBUG_REG3)/sizeof(ixSXIFCCG_DEBUG_REG3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG23", REG_SMC, 0x17, &ixVGT_DEBUG_REG23[0], sizeof(ixVGT_DEBUG_REG23)/sizeof(ixVGT_DEBUG_REG23[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_STS", REG_SMC, 0x17, &ixSQ_WAVE_IB_STS[0], sizeof(ixSQ_WAVE_IB_STS)/sizeof(ixSQ_WAVE_IB_STS[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG0", REG_SMC, 0x18, &ixSETUP_DEBUG_REG0[0], sizeof(ixSETUP_DEBUG_REG0)/sizeof(ixSETUP_DEBUG_REG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG24", REG_SMC, 0x18, &ixVGT_DEBUG_REG24[0], sizeof(ixVGT_DEBUG_REG24)/sizeof(ixVGT_DEBUG_REG24[0]), 0, 0 },
+	{ "ixSQ_WAVE_PC_LO", REG_SMC, 0x18, &ixSQ_WAVE_PC_LO[0], sizeof(ixSQ_WAVE_PC_LO)/sizeof(ixSQ_WAVE_PC_LO[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG1", REG_SMC, 0x19, &ixSETUP_DEBUG_REG1[0], sizeof(ixSETUP_DEBUG_REG1)/sizeof(ixSETUP_DEBUG_REG1[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG25", REG_SMC, 0x19, &ixVGT_DEBUG_REG25[0], sizeof(ixVGT_DEBUG_REG25)/sizeof(ixVGT_DEBUG_REG25[0]), 0, 0 },
+	{ "ixSQ_WAVE_PC_HI", REG_SMC, 0x19, &ixSQ_WAVE_PC_HI[0], sizeof(ixSQ_WAVE_PC_HI)/sizeof(ixSQ_WAVE_PC_HI[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG2", REG_SMC, 0x1a, &ixSETUP_DEBUG_REG2[0], sizeof(ixSETUP_DEBUG_REG2)/sizeof(ixSETUP_DEBUG_REG2[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG3", REG_SMC, 0x1b, &ixSETUP_DEBUG_REG3[0], sizeof(ixSETUP_DEBUG_REG3)/sizeof(ixSETUP_DEBUG_REG3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG27", REG_SMC, 0x1b, &ixVGT_DEBUG_REG27[0], sizeof(ixVGT_DEBUG_REG27)/sizeof(ixVGT_DEBUG_REG27[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG4", REG_SMC, 0x1c, &ixSETUP_DEBUG_REG4[0], sizeof(ixSETUP_DEBUG_REG4)/sizeof(ixSETUP_DEBUG_REG4[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_DBG0", REG_SMC, 0x1c, &ixSQ_WAVE_IB_DBG0[0], sizeof(ixSQ_WAVE_IB_DBG0)/sizeof(ixSQ_WAVE_IB_DBG0[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG5", REG_SMC, 0x1d, &ixSETUP_DEBUG_REG5[0], sizeof(ixSETUP_DEBUG_REG5)/sizeof(ixSETUP_DEBUG_REG5[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG29", REG_SMC, 0x1d, &ixVGT_DEBUG_REG29[0], sizeof(ixVGT_DEBUG_REG29)/sizeof(ixVGT_DEBUG_REG29[0]), 0, 0 },
+	{ "mmCSPRIV_THREAD_TRACE_TG0", REG_MMIO, 0x1e, &mmCSPRIV_THREAD_TRACE_TG0[0], sizeof(mmCSPRIV_THREAD_TRACE_TG0)/sizeof(mmCSPRIV_THREAD_TRACE_TG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG2", REG_SMC, 0x1e, &ixVGT_DEBUG_REG2[0], sizeof(ixVGT_DEBUG_REG2)/sizeof(ixVGT_DEBUG_REG2[0]), 0, 0 },
+	{ "mmCSPRIV_THREAD_TRACE_EVENT", REG_MMIO, 0x1f, &mmCSPRIV_THREAD_TRACE_EVENT[0], sizeof(mmCSPRIV_THREAD_TRACE_EVENT)/sizeof(mmCSPRIV_THREAD_TRACE_EVENT[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG3", REG_SMC, 0x1f, &ixVGT_DEBUG_REG3[0], sizeof(ixVGT_DEBUG_REG3)/sizeof(ixVGT_DEBUG_REG3[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG02", REG_SMC, 0x2, &ixCLIPPER_DEBUG_REG02[0], sizeof(ixCLIPPER_DEBUG_REG02)/sizeof(ixCLIPPER_DEBUG_REG02[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG2", REG_SMC, 0x2, &ixGDS_DEBUG_REG2[0], sizeof(ixGDS_DEBUG_REG2)/sizeof(ixGDS_DEBUG_REG2[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG2", REG_SMC, 0x2, &ixWD_DEBUG_REG2[0], sizeof(ixWD_DEBUG_REG2)/sizeof(ixWD_DEBUG_REG2[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG4", REG_SMC, 0x20, &ixVGT_DEBUG_REG4[0], sizeof(ixVGT_DEBUG_REG4)/sizeof(ixVGT_DEBUG_REG4[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL0", REG_SMC, 0x20, &ixDIDT_DB_CTRL0[0], sizeof(ixDIDT_DB_CTRL0)/sizeof(ixDIDT_DB_CTRL0[0]), 0, 0 },
+	{ "mmGRBM_CNTL", REG_MMIO, 0x2000, &mmGRBM_CNTL[0], sizeof(mmGRBM_CNTL)/sizeof(mmGRBM_CNTL[0]), 0, 0 },
+	{ "mmGRBM_SKEW_CNTL", REG_MMIO, 0x2001, &mmGRBM_SKEW_CNTL[0], sizeof(mmGRBM_SKEW_CNTL)/sizeof(mmGRBM_SKEW_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS2", REG_MMIO, 0x2002, &mmGRBM_STATUS2[0], sizeof(mmGRBM_STATUS2)/sizeof(mmGRBM_STATUS2[0]), 0, 0 },
+	{ "mmGRBM_PWR_CNTL", REG_MMIO, 0x2003, &mmGRBM_PWR_CNTL[0], sizeof(mmGRBM_PWR_CNTL)/sizeof(mmGRBM_PWR_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS", REG_MMIO, 0x2004, &mmGRBM_STATUS[0], sizeof(mmGRBM_STATUS)/sizeof(mmGRBM_STATUS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE0", REG_MMIO, 0x2005, &mmGRBM_STATUS_SE0[0], sizeof(mmGRBM_STATUS_SE0)/sizeof(mmGRBM_STATUS_SE0[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE1", REG_MMIO, 0x2006, &mmGRBM_STATUS_SE1[0], sizeof(mmGRBM_STATUS_SE1)/sizeof(mmGRBM_STATUS_SE1[0]), 0, 0 },
+	{ "mmGRBM_SOFT_RESET", REG_MMIO, 0x2008, &mmGRBM_SOFT_RESET[0], sizeof(mmGRBM_SOFT_RESET)/sizeof(mmGRBM_SOFT_RESET[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_CNTL", REG_MMIO, 0x2009, &mmGRBM_DEBUG_CNTL[0], sizeof(mmGRBM_DEBUG_CNTL)/sizeof(mmGRBM_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_DATA", REG_MMIO, 0x200a, &mmGRBM_DEBUG_DATA[0], sizeof(mmGRBM_DEBUG_DATA)/sizeof(mmGRBM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_GFX_CLKEN_CNTL", REG_MMIO, 0x200c, &mmGRBM_GFX_CLKEN_CNTL[0], sizeof(mmGRBM_GFX_CLKEN_CNTL)/sizeof(mmGRBM_GFX_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmGRBM_WAIT_IDLE_CLOCKS", REG_MMIO, 0x200d, &mmGRBM_WAIT_IDLE_CLOCKS[0], sizeof(mmGRBM_WAIT_IDLE_CLOCKS)/sizeof(mmGRBM_WAIT_IDLE_CLOCKS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE2", REG_MMIO, 0x200e, &mmGRBM_STATUS_SE2[0], sizeof(mmGRBM_STATUS_SE2)/sizeof(mmGRBM_STATUS_SE2[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE3", REG_MMIO, 0x200f, &mmGRBM_STATUS_SE3[0], sizeof(mmGRBM_STATUS_SE3)/sizeof(mmGRBM_STATUS_SE3[0]), 0, 0 },
+	{ "mmGRBM_DEBUG", REG_MMIO, 0x2014, &mmGRBM_DEBUG[0], sizeof(mmGRBM_DEBUG)/sizeof(mmGRBM_DEBUG[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x2015, &mmGRBM_DEBUG_SNAPSHOT[0], sizeof(mmGRBM_DEBUG_SNAPSHOT)/sizeof(mmGRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR", REG_MMIO, 0x2016, &mmGRBM_READ_ERROR[0], sizeof(mmGRBM_READ_ERROR)/sizeof(mmGRBM_READ_ERROR[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR2", REG_MMIO, 0x2017, &mmGRBM_READ_ERROR2[0], sizeof(mmGRBM_READ_ERROR2)/sizeof(mmGRBM_READ_ERROR2[0]), 0, 0 },
+	{ "mmGRBM_INT_CNTL", REG_MMIO, 0x2018, &mmGRBM_INT_CNTL[0], sizeof(mmGRBM_INT_CNTL)/sizeof(mmGRBM_INT_CNTL[0]), 0, 0 },
+	{ "mmDEBUG_INDEX", REG_MMIO, 0x203c, &mmDEBUG_INDEX[0], sizeof(mmDEBUG_INDEX)/sizeof(mmDEBUG_INDEX[0]), 0, 0 },
+	{ "mmDEBUG_DATA", REG_MMIO, 0x203d, &mmDEBUG_DATA[0], sizeof(mmDEBUG_DATA)/sizeof(mmDEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_NOWHERE", REG_MMIO, 0x203f, &mmGRBM_NOWHERE[0], sizeof(mmGRBM_NOWHERE)/sizeof(mmGRBM_NOWHERE[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG0", REG_MMIO, 0x2040, &mmGRBM_SCRATCH_REG0[0], sizeof(mmGRBM_SCRATCH_REG0)/sizeof(mmGRBM_SCRATCH_REG0[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG1", REG_MMIO, 0x2041, &mmGRBM_SCRATCH_REG1[0], sizeof(mmGRBM_SCRATCH_REG1)/sizeof(mmGRBM_SCRATCH_REG1[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG2", REG_MMIO, 0x2042, &mmGRBM_SCRATCH_REG2[0], sizeof(mmGRBM_SCRATCH_REG2)/sizeof(mmGRBM_SCRATCH_REG2[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG3", REG_MMIO, 0x2043, &mmGRBM_SCRATCH_REG3[0], sizeof(mmGRBM_SCRATCH_REG3)/sizeof(mmGRBM_SCRATCH_REG3[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG4", REG_MMIO, 0x2044, &mmGRBM_SCRATCH_REG4[0], sizeof(mmGRBM_SCRATCH_REG4)/sizeof(mmGRBM_SCRATCH_REG4[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG5", REG_MMIO, 0x2045, &mmGRBM_SCRATCH_REG5[0], sizeof(mmGRBM_SCRATCH_REG5)/sizeof(mmGRBM_SCRATCH_REG5[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG6", REG_MMIO, 0x2046, &mmGRBM_SCRATCH_REG6[0], sizeof(mmGRBM_SCRATCH_REG6)/sizeof(mmGRBM_SCRATCH_REG6[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG7", REG_MMIO, 0x2047, &mmGRBM_SCRATCH_REG7[0], sizeof(mmGRBM_SCRATCH_REG7)/sizeof(mmGRBM_SCRATCH_REG7[0]), 0, 0 },
+	{ "mmCP_CPC_STATUS", REG_MMIO, 0x2084, &mmCP_CPC_STATUS[0], sizeof(mmCP_CPC_STATUS)/sizeof(mmCP_CPC_STATUS[0]), 0, 0 },
+	{ "mmCP_CPC_BUSY_STAT", REG_MMIO, 0x2085, &mmCP_CPC_BUSY_STAT[0], sizeof(mmCP_CPC_BUSY_STAT)/sizeof(mmCP_CPC_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_CPC_STALLED_STAT1", REG_MMIO, 0x2086, &mmCP_CPC_STALLED_STAT1[0], sizeof(mmCP_CPC_STALLED_STAT1)/sizeof(mmCP_CPC_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_CPF_STATUS", REG_MMIO, 0x2087, &mmCP_CPF_STATUS[0], sizeof(mmCP_CPF_STATUS)/sizeof(mmCP_CPF_STATUS[0]), 0, 0 },
+	{ "mmCP_CPF_BUSY_STAT", REG_MMIO, 0x2088, &mmCP_CPF_BUSY_STAT[0], sizeof(mmCP_CPF_BUSY_STAT)/sizeof(mmCP_CPF_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_CPF_STALLED_STAT1", REG_MMIO, 0x2089, &mmCP_CPF_STALLED_STAT1[0], sizeof(mmCP_CPF_STALLED_STAT1)/sizeof(mmCP_CPF_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_CPC_MC_CNTL", REG_MMIO, 0x208a, &mmCP_CPC_MC_CNTL[0], sizeof(mmCP_CPC_MC_CNTL)/sizeof(mmCP_CPC_MC_CNTL[0]), 0, 0 },
+	{ "mmCP_CPC_GRBM_FREE_COUNT", REG_MMIO, 0x208b, &mmCP_CPC_GRBM_FREE_COUNT[0], sizeof(mmCP_CPC_GRBM_FREE_COUNT)/sizeof(mmCP_CPC_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_MEC_CNTL", REG_MMIO, 0x208d, &mmCP_MEC_CNTL[0], sizeof(mmCP_MEC_CNTL)/sizeof(mmCP_MEC_CNTL[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_HEADER_DUMP", REG_MMIO, 0x208e, &mmCP_MEC_ME1_HEADER_DUMP[0], sizeof(mmCP_MEC_ME1_HEADER_DUMP)/sizeof(mmCP_MEC_ME1_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_HEADER_DUMP", REG_MMIO, 0x208f, &mmCP_MEC_ME2_HEADER_DUMP[0], sizeof(mmCP_MEC_ME2_HEADER_DUMP)/sizeof(mmCP_MEC_ME2_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_CPC_SCRATCH_INDEX", REG_MMIO, 0x2090, &mmCP_CPC_SCRATCH_INDEX[0], sizeof(mmCP_CPC_SCRATCH_INDEX)/sizeof(mmCP_CPC_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_CPC_SCRATCH_DATA", REG_MMIO, 0x2091, &mmCP_CPC_SCRATCH_DATA[0], sizeof(mmCP_CPC_SCRATCH_DATA)/sizeof(mmCP_CPC_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_CPC_HALT_HYST_COUNT", REG_MMIO, 0x20a7, &mmCP_CPC_HALT_HYST_COUNT[0], sizeof(mmCP_CPC_HALT_HYST_COUNT)/sizeof(mmCP_CPC_HALT_HYST_COUNT[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL0", REG_MMIO, 0x20ad, &mmCP_PRT_LOD_STATS_CNTL0[0], sizeof(mmCP_PRT_LOD_STATS_CNTL0)/sizeof(mmCP_PRT_LOD_STATS_CNTL0[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL1", REG_MMIO, 0x20ae, &mmCP_PRT_LOD_STATS_CNTL1[0], sizeof(mmCP_PRT_LOD_STATS_CNTL1)/sizeof(mmCP_PRT_LOD_STATS_CNTL1[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL2", REG_MMIO, 0x20af, &mmCP_PRT_LOD_STATS_CNTL2[0], sizeof(mmCP_PRT_LOD_STATS_CNTL2)/sizeof(mmCP_PRT_LOD_STATS_CNTL2[0]), 0, 0 },
+	{ "ixSQ_INTERRUPT_WORD_AUTO", REG_SMC, 0x20c0, &ixSQ_INTERRUPT_WORD_AUTO[0], sizeof(ixSQ_INTERRUPT_WORD_AUTO)/sizeof(ixSQ_INTERRUPT_WORD_AUTO[0]), 0, 0 },
+	{ "ixSQ_INTERRUPT_WORD_CMN", REG_SMC, 0x20c0, &ixSQ_INTERRUPT_WORD_CMN[0], sizeof(ixSQ_INTERRUPT_WORD_CMN)/sizeof(ixSQ_INTERRUPT_WORD_CMN[0]), 0, 0 },
+	{ "mmCP_CE_COMPARE_COUNT", REG_MMIO, 0x20c0, &mmCP_CE_COMPARE_COUNT[0], sizeof(mmCP_CE_COMPARE_COUNT)/sizeof(mmCP_CE_COMPARE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_DE_COUNT", REG_MMIO, 0x20c1, &mmCP_CE_DE_COUNT[0], sizeof(mmCP_CE_DE_COUNT)/sizeof(mmCP_CE_DE_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_CE_COUNT", REG_MMIO, 0x20c2, &mmCP_DE_CE_COUNT[0], sizeof(mmCP_DE_CE_COUNT)/sizeof(mmCP_DE_CE_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_LAST_INVAL_COUNT", REG_MMIO, 0x20c3, &mmCP_DE_LAST_INVAL_COUNT[0], sizeof(mmCP_DE_LAST_INVAL_COUNT)/sizeof(mmCP_DE_LAST_INVAL_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_DE_COUNT", REG_MMIO, 0x20c4, &mmCP_DE_DE_COUNT[0], sizeof(mmCP_DE_DE_COUNT)/sizeof(mmCP_DE_DE_COUNT[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG5", REG_SMC, 0x21, &ixVGT_DEBUG_REG5[0], sizeof(ixVGT_DEBUG_REG5)/sizeof(ixVGT_DEBUG_REG5[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL1", REG_SMC, 0x21, &ixDIDT_DB_CTRL1[0], sizeof(ixDIDT_DB_CTRL1)/sizeof(ixDIDT_DB_CTRL1[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT3", REG_MMIO, 0x219c, &mmCP_STALLED_STAT3[0], sizeof(mmCP_STALLED_STAT3)/sizeof(mmCP_STALLED_STAT3[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT1", REG_MMIO, 0x219d, &mmCP_STALLED_STAT1[0], sizeof(mmCP_STALLED_STAT1)/sizeof(mmCP_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT2", REG_MMIO, 0x219e, &mmCP_STALLED_STAT2[0], sizeof(mmCP_STALLED_STAT2)/sizeof(mmCP_STALLED_STAT2[0]), 0, 0 },
+	{ "mmCP_BUSY_STAT", REG_MMIO, 0x219f, &mmCP_BUSY_STAT[0], sizeof(mmCP_BUSY_STAT)/sizeof(mmCP_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_STAT", REG_MMIO, 0x21a0, &mmCP_STAT[0], sizeof(mmCP_STAT)/sizeof(mmCP_STAT[0]), 0, 0 },
+	{ "mmCP_ME_HEADER_DUMP", REG_MMIO, 0x21a1, &mmCP_ME_HEADER_DUMP[0], sizeof(mmCP_ME_HEADER_DUMP)/sizeof(mmCP_ME_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_PFP_HEADER_DUMP", REG_MMIO, 0x21a2, &mmCP_PFP_HEADER_DUMP[0], sizeof(mmCP_PFP_HEADER_DUMP)/sizeof(mmCP_PFP_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_GRBM_FREE_COUNT", REG_MMIO, 0x21a3, &mmCP_GRBM_FREE_COUNT[0], sizeof(mmCP_GRBM_FREE_COUNT)/sizeof(mmCP_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_HEADER_DUMP", REG_MMIO, 0x21a4, &mmCP_CE_HEADER_DUMP[0], sizeof(mmCP_CE_HEADER_DUMP)/sizeof(mmCP_CE_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_MC_PACK_DELAY_CNT", REG_MMIO, 0x21a7, &mmCP_MC_PACK_DELAY_CNT[0], sizeof(mmCP_MC_PACK_DELAY_CNT)/sizeof(mmCP_MC_PACK_DELAY_CNT[0]), 0, 0 },
+	{ "mmCP_MC_TAG_CNTL", REG_MMIO, 0x21a8, &mmCP_MC_TAG_CNTL[0], sizeof(mmCP_MC_TAG_CNTL)/sizeof(mmCP_MC_TAG_CNTL[0]), 0, 0 },
+	{ "mmCP_MC_TAG_DATA", REG_MMIO, 0x21a9, &mmCP_MC_TAG_DATA[0], sizeof(mmCP_MC_TAG_DATA)/sizeof(mmCP_MC_TAG_DATA[0]), 0, 0 },
+	{ "mmCP_CSF_STAT", REG_MMIO, 0x21b4, &mmCP_CSF_STAT[0], sizeof(mmCP_CSF_STAT)/sizeof(mmCP_CSF_STAT[0]), 0, 0 },
+	{ "mmCP_CSF_CNTL", REG_MMIO, 0x21b5, &mmCP_CSF_CNTL[0], sizeof(mmCP_CSF_CNTL)/sizeof(mmCP_CSF_CNTL[0]), 0, 0 },
+	{ "mmCP_ME_CNTL", REG_MMIO, 0x21b6, &mmCP_ME_CNTL[0], sizeof(mmCP_ME_CNTL)/sizeof(mmCP_ME_CNTL[0]), 0, 0 },
+	{ "mmCP_CNTX_STAT", REG_MMIO, 0x21b8, &mmCP_CNTX_STAT[0], sizeof(mmCP_CNTX_STAT)/sizeof(mmCP_CNTX_STAT[0]), 0, 0 },
+	{ "mmCP_ME_PREEMPTION", REG_MMIO, 0x21b9, &mmCP_ME_PREEMPTION[0], sizeof(mmCP_ME_PREEMPTION)/sizeof(mmCP_ME_PREEMPTION[0]), 0, 0 },
+	{ "mmCP_ROQ_THRESHOLDS", REG_MMIO, 0x21bc, &mmCP_ROQ_THRESHOLDS[0], sizeof(mmCP_ROQ_THRESHOLDS)/sizeof(mmCP_ROQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_STQ_THRESHOLD", REG_MMIO, 0x21bd, &mmCP_MEQ_STQ_THRESHOLD[0], sizeof(mmCP_MEQ_STQ_THRESHOLD)/sizeof(mmCP_MEQ_STQ_THRESHOLD[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR", REG_MMIO, 0x21be, &mmCP_RB2_RPTR[0], sizeof(mmCP_RB2_RPTR)/sizeof(mmCP_RB2_RPTR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR", REG_MMIO, 0x21bf, &mmCP_RB1_RPTR[0], sizeof(mmCP_RB1_RPTR)/sizeof(mmCP_RB1_RPTR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR", REG_MMIO, 0x21c0, &mmCP_RB0_RPTR[0], sizeof(mmCP_RB0_RPTR)/sizeof(mmCP_RB0_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_RPTR", REG_MMIO, 0x21c0, &mmCP_RB_RPTR[0], sizeof(mmCP_RB_RPTR)/sizeof(mmCP_RB_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_DELAY", REG_MMIO, 0x21c1, &mmCP_RB_WPTR_DELAY[0], sizeof(mmCP_RB_WPTR_DELAY)/sizeof(mmCP_RB_WPTR_DELAY[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_CNTL", REG_MMIO, 0x21c2, &mmCP_RB_WPTR_POLL_CNTL[0], sizeof(mmCP_RB_WPTR_POLL_CNTL)/sizeof(mmCP_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_ROQ1_THRESHOLDS", REG_MMIO, 0x21d5, &mmCP_ROQ1_THRESHOLDS[0], sizeof(mmCP_ROQ1_THRESHOLDS)/sizeof(mmCP_ROQ1_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ2_THRESHOLDS", REG_MMIO, 0x21d6, &mmCP_ROQ2_THRESHOLDS[0], sizeof(mmCP_ROQ2_THRESHOLDS)/sizeof(mmCP_ROQ2_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_STQ_THRESHOLDS", REG_MMIO, 0x21d7, &mmCP_STQ_THRESHOLDS[0], sizeof(mmCP_STQ_THRESHOLDS)/sizeof(mmCP_STQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_QUEUE_THRESHOLDS", REG_MMIO, 0x21d8, &mmCP_QUEUE_THRESHOLDS[0], sizeof(mmCP_QUEUE_THRESHOLDS)/sizeof(mmCP_QUEUE_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_THRESHOLDS", REG_MMIO, 0x21d9, &mmCP_MEQ_THRESHOLDS[0], sizeof(mmCP_MEQ_THRESHOLDS)/sizeof(mmCP_MEQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ_AVAIL", REG_MMIO, 0x21da, &mmCP_ROQ_AVAIL[0], sizeof(mmCP_ROQ_AVAIL)/sizeof(mmCP_ROQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_STQ_AVAIL", REG_MMIO, 0x21db, &mmCP_STQ_AVAIL[0], sizeof(mmCP_STQ_AVAIL)/sizeof(mmCP_STQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_ROQ2_AVAIL", REG_MMIO, 0x21dc, &mmCP_ROQ2_AVAIL[0], sizeof(mmCP_ROQ2_AVAIL)/sizeof(mmCP_ROQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_MEQ_AVAIL", REG_MMIO, 0x21dd, &mmCP_MEQ_AVAIL[0], sizeof(mmCP_MEQ_AVAIL)/sizeof(mmCP_MEQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_CMD_INDEX", REG_MMIO, 0x21de, &mmCP_CMD_INDEX[0], sizeof(mmCP_CMD_INDEX)/sizeof(mmCP_CMD_INDEX[0]), 0, 0 },
+	{ "mmCP_CMD_DATA", REG_MMIO, 0x21df, &mmCP_CMD_DATA[0], sizeof(mmCP_CMD_DATA)/sizeof(mmCP_CMD_DATA[0]), 0, 0 },
+	{ "mmCP_ROQ_RB_STAT", REG_MMIO, 0x21e0, &mmCP_ROQ_RB_STAT[0], sizeof(mmCP_ROQ_RB_STAT)/sizeof(mmCP_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB1_STAT", REG_MMIO, 0x21e1, &mmCP_ROQ_IB1_STAT[0], sizeof(mmCP_ROQ_IB1_STAT)/sizeof(mmCP_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB2_STAT", REG_MMIO, 0x21e2, &mmCP_ROQ_IB2_STAT[0], sizeof(mmCP_ROQ_IB2_STAT)/sizeof(mmCP_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_STAT", REG_MMIO, 0x21e3, &mmCP_STQ_STAT[0], sizeof(mmCP_STQ_STAT)/sizeof(mmCP_STQ_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_WR_STAT", REG_MMIO, 0x21e4, &mmCP_STQ_WR_STAT[0], sizeof(mmCP_STQ_WR_STAT)/sizeof(mmCP_STQ_WR_STAT[0]), 0, 0 },
+	{ "mmCP_MEQ_STAT", REG_MMIO, 0x21e5, &mmCP_MEQ_STAT[0], sizeof(mmCP_MEQ_STAT)/sizeof(mmCP_MEQ_STAT[0]), 0, 0 },
+	{ "mmCP_CEQ1_AVAIL", REG_MMIO, 0x21e6, &mmCP_CEQ1_AVAIL[0], sizeof(mmCP_CEQ1_AVAIL)/sizeof(mmCP_CEQ1_AVAIL[0]), 0, 0 },
+	{ "mmCP_CEQ2_AVAIL", REG_MMIO, 0x21e7, &mmCP_CEQ2_AVAIL[0], sizeof(mmCP_CEQ2_AVAIL)/sizeof(mmCP_CEQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_RB_STAT", REG_MMIO, 0x21e8, &mmCP_CE_ROQ_RB_STAT[0], sizeof(mmCP_CE_ROQ_RB_STAT)/sizeof(mmCP_CE_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB1_STAT", REG_MMIO, 0x21e9, &mmCP_CE_ROQ_IB1_STAT[0], sizeof(mmCP_CE_ROQ_IB1_STAT)/sizeof(mmCP_CE_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB2_STAT", REG_MMIO, 0x21ea, &mmCP_CE_ROQ_IB2_STAT[0], sizeof(mmCP_CE_ROQ_IB2_STAT)/sizeof(mmCP_CE_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_INT_STAT_DEBUG", REG_MMIO, 0x21f7, &mmCP_INT_STAT_DEBUG[0], sizeof(mmCP_INT_STAT_DEBUG)/sizeof(mmCP_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG6", REG_SMC, 0x22, &ixVGT_DEBUG_REG6[0], sizeof(ixVGT_DEBUG_REG6)/sizeof(ixVGT_DEBUG_REG6[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL2", REG_SMC, 0x22, &ixDIDT_DB_CTRL2[0], sizeof(ixDIDT_DB_CTRL2)/sizeof(ixDIDT_DB_CTRL2[0]), 0, 0 },
+	{ "mmVGT_VTX_VECT_EJECT_REG", REG_MMIO, 0x222c, &mmVGT_VTX_VECT_EJECT_REG[0], sizeof(mmVGT_VTX_VECT_EJECT_REG)/sizeof(mmVGT_VTX_VECT_EJECT_REG[0]), 0, 0 },
+	{ "mmVGT_DMA_DATA_FIFO_DEPTH", REG_MMIO, 0x222d, &mmVGT_DMA_DATA_FIFO_DEPTH[0], sizeof(mmVGT_DMA_DATA_FIFO_DEPTH)/sizeof(mmVGT_DMA_DATA_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DMA_REQ_FIFO_DEPTH", REG_MMIO, 0x222e, &mmVGT_DMA_REQ_FIFO_DEPTH[0], sizeof(mmVGT_DMA_REQ_FIFO_DEPTH)/sizeof(mmVGT_DMA_REQ_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DRAW_INIT_FIFO_DEPTH", REG_MMIO, 0x222f, &mmVGT_DRAW_INIT_FIFO_DEPTH[0], sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH)/sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_LAST_COPY_STATE", REG_MMIO, 0x2230, &mmVGT_LAST_COPY_STATE[0], sizeof(mmVGT_LAST_COPY_STATE)/sizeof(mmVGT_LAST_COPY_STATE[0]), 0, 0 },
+	{ "mmVGT_CACHE_INVALIDATION", REG_MMIO, 0x2231, &mmVGT_CACHE_INVALIDATION[0], sizeof(mmVGT_CACHE_INVALIDATION)/sizeof(mmVGT_CACHE_INVALIDATION[0]), 0, 0 },
+	{ "mmVGT_RESET_DEBUG", REG_MMIO, 0x2232, &mmVGT_RESET_DEBUG[0], sizeof(mmVGT_RESET_DEBUG)/sizeof(mmVGT_RESET_DEBUG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DELAY", REG_MMIO, 0x2233, &mmVGT_STRMOUT_DELAY[0], sizeof(mmVGT_STRMOUT_DELAY)/sizeof(mmVGT_STRMOUT_DELAY[0]), 0, 0 },
+	{ "mmVGT_FIFO_DEPTHS", REG_MMIO, 0x2234, &mmVGT_FIFO_DEPTHS[0], sizeof(mmVGT_FIFO_DEPTHS)/sizeof(mmVGT_FIFO_DEPTHS[0]), 0, 0 },
+	{ "mmVGT_GS_VERTEX_REUSE", REG_MMIO, 0x2235, &mmVGT_GS_VERTEX_REUSE[0], sizeof(mmVGT_GS_VERTEX_REUSE)/sizeof(mmVGT_GS_VERTEX_REUSE[0]), 0, 0 },
+	{ "mmVGT_MC_LAT_CNTL", REG_MMIO, 0x2236, &mmVGT_MC_LAT_CNTL[0], sizeof(mmVGT_MC_LAT_CNTL)/sizeof(mmVGT_MC_LAT_CNTL[0]), 0, 0 },
+	{ "mmIA_CNTL_STATUS", REG_MMIO, 0x2237, &mmIA_CNTL_STATUS[0], sizeof(mmIA_CNTL_STATUS)/sizeof(mmIA_CNTL_STATUS[0]), 0, 0 },
+	{ "mmVGT_DEBUG_CNTL", REG_MMIO, 0x2238, &mmVGT_DEBUG_CNTL[0], sizeof(mmVGT_DEBUG_CNTL)/sizeof(mmVGT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmVGT_DEBUG_DATA", REG_MMIO, 0x2239, &mmVGT_DEBUG_DATA[0], sizeof(mmVGT_DEBUG_DATA)/sizeof(mmVGT_DEBUG_DATA[0]), 0, 0 },
+	{ "mmIA_DEBUG_CNTL", REG_MMIO, 0x223a, &mmIA_DEBUG_CNTL[0], sizeof(mmIA_DEBUG_CNTL)/sizeof(mmIA_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmIA_DEBUG_DATA", REG_MMIO, 0x223b, &mmIA_DEBUG_DATA[0], sizeof(mmIA_DEBUG_DATA)/sizeof(mmIA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGT_CNTL_STATUS", REG_MMIO, 0x223c, &mmVGT_CNTL_STATUS[0], sizeof(mmVGT_CNTL_STATUS)/sizeof(mmVGT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmWD_DEBUG_CNTL", REG_MMIO, 0x223d, &mmWD_DEBUG_CNTL[0], sizeof(mmWD_DEBUG_CNTL)/sizeof(mmWD_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmWD_DEBUG_DATA", REG_MMIO, 0x223e, &mmWD_DEBUG_DATA[0], sizeof(mmWD_DEBUG_DATA)/sizeof(mmWD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmWD_CNTL_STATUS", REG_MMIO, 0x223f, &mmWD_CNTL_STATUS[0], sizeof(mmWD_CNTL_STATUS)/sizeof(mmWD_CNTL_STATUS[0]), 0, 0 },
+	{ "mmCC_GC_PRIM_CONFIG", REG_MMIO, 0x2240, &mmCC_GC_PRIM_CONFIG[0], sizeof(mmCC_GC_PRIM_CONFIG)/sizeof(mmCC_GC_PRIM_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_PRIM_CONFIG", REG_MMIO, 0x2241, &mmGC_USER_PRIM_CONFIG[0], sizeof(mmGC_USER_PRIM_CONFIG)/sizeof(mmGC_USER_PRIM_CONFIG[0]), 0, 0 },
+	{ "mmIA_VMID_OVERRIDE", REG_MMIO, 0x2260, &mmIA_VMID_OVERRIDE[0], sizeof(mmIA_VMID_OVERRIDE)/sizeof(mmIA_VMID_OVERRIDE[0]), 0, 0 },
+	{ "mmVGT_SYS_CONFIG", REG_MMIO, 0x2263, &mmVGT_SYS_CONFIG[0], sizeof(mmVGT_SYS_CONFIG)/sizeof(mmVGT_SYS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_VS_MAX_WAVE_ID", REG_MMIO, 0x2268, &mmVGT_VS_MAX_WAVE_ID[0], sizeof(mmVGT_VS_MAX_WAVE_ID)/sizeof(mmVGT_VS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmGFX_PIPE_CONTROL", REG_MMIO, 0x226d, &mmGFX_PIPE_CONTROL[0], sizeof(mmGFX_PIPE_CONTROL)/sizeof(mmGFX_PIPE_CONTROL[0]), 0, 0 },
+	{ "mmCC_GC_SHADER_ARRAY_CONFIG", REG_MMIO, 0x226f, &mmCC_GC_SHADER_ARRAY_CONFIG[0], sizeof(mmCC_GC_SHADER_ARRAY_CONFIG)/sizeof(mmCC_GC_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_SHADER_ARRAY_CONFIG", REG_MMIO, 0x2270, &mmGC_USER_SHADER_ARRAY_CONFIG[0], sizeof(mmGC_USER_SHADER_ARRAY_CONFIG)/sizeof(mmGC_USER_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmVGT_DMA_PRIMITIVE_TYPE", REG_MMIO, 0x2271, &mmVGT_DMA_PRIMITIVE_TYPE[0], sizeof(mmVGT_DMA_PRIMITIVE_TYPE)/sizeof(mmVGT_DMA_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_DMA_CONTROL", REG_MMIO, 0x2272, &mmVGT_DMA_CONTROL[0], sizeof(mmVGT_DMA_CONTROL)/sizeof(mmVGT_DMA_CONTROL[0]), 0, 0 },
+	{ "mmVGT_DMA_LS_HS_CONFIG", REG_MMIO, 0x2273, &mmVGT_DMA_LS_HS_CONFIG[0], sizeof(mmVGT_DMA_LS_HS_CONFIG)/sizeof(mmVGT_DMA_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_CNTL", REG_MMIO, 0x2280, &mmPA_SU_DEBUG_CNTL[0], sizeof(mmPA_SU_DEBUG_CNTL)/sizeof(mmPA_SU_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_DATA", REG_MMIO, 0x2281, &mmPA_SU_DEBUG_DATA[0], sizeof(mmPA_SU_DEBUG_DATA)/sizeof(mmPA_SU_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_CL_CNTL_STATUS", REG_MMIO, 0x2284, &mmPA_CL_CNTL_STATUS[0], sizeof(mmPA_CL_CNTL_STATUS)/sizeof(mmPA_CL_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_CL_ENHANCE", REG_MMIO, 0x2285, &mmPA_CL_ENHANCE[0], sizeof(mmPA_CL_ENHANCE)/sizeof(mmPA_CL_ENHANCE[0]), 0, 0 },
+	{ "mmPA_CL_RESET_DEBUG", REG_MMIO, 0x2286, &mmPA_CL_RESET_DEBUG[0], sizeof(mmPA_CL_RESET_DEBUG)/sizeof(mmPA_CL_RESET_DEBUG[0]), 0, 0 },
+	{ "mmPA_SU_CNTL_STATUS", REG_MMIO, 0x2294, &mmPA_SU_CNTL_STATUS[0], sizeof(mmPA_SU_CNTL_STATUS)/sizeof(mmPA_SU_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_DEPTH_CNTL", REG_MMIO, 0x2295, &mmPA_SC_FIFO_DEPTH_CNTL[0], sizeof(mmPA_SC_FIFO_DEPTH_CNTL)/sizeof(mmPA_SC_FIFO_DEPTH_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c0, &mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c1, &mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c2, &mmPA_SC_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_FORCE_EOV_MAX_CNTS", REG_MMIO, 0x22c9, &mmPA_SC_FORCE_EOV_MAX_CNTS[0], sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS)/sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_SIZE", REG_MMIO, 0x22f3, &mmPA_SC_FIFO_SIZE[0], sizeof(mmPA_SC_FIFO_SIZE)/sizeof(mmPA_SC_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_IF_FIFO_SIZE", REG_MMIO, 0x22f5, &mmPA_SC_IF_FIFO_SIZE[0], sizeof(mmPA_SC_IF_FIFO_SIZE)/sizeof(mmPA_SC_IF_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_CNTL", REG_MMIO, 0x22f6, &mmPA_SC_DEBUG_CNTL[0], sizeof(mmPA_SC_DEBUG_CNTL)/sizeof(mmPA_SC_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_DATA", REG_MMIO, 0x22f7, &mmPA_SC_DEBUG_DATA[0], sizeof(mmPA_SC_DEBUG_DATA)/sizeof(mmPA_SC_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_SC_ENHANCE", REG_MMIO, 0x22fc, &mmPA_SC_ENHANCE[0], sizeof(mmPA_SC_ENHANCE)/sizeof(mmPA_SC_ENHANCE[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG7", REG_SMC, 0x23, &ixVGT_DEBUG_REG7[0], sizeof(ixVGT_DEBUG_REG7)/sizeof(ixVGT_DEBUG_REG7[0]), 0, 0 },
+	{ "mmSQ_CONFIG", REG_MMIO, 0x2300, &mmSQ_CONFIG[0], sizeof(mmSQ_CONFIG)/sizeof(mmSQ_CONFIG[0]), 0, 0 },
+	{ "mmSQC_CONFIG", REG_MMIO, 0x2301, &mmSQC_CONFIG[0], sizeof(mmSQC_CONFIG)/sizeof(mmSQC_CONFIG[0]), 0, 0 },
+	{ "mmSQ_RANDOM_WAVE_PRI", REG_MMIO, 0x2303, &mmSQ_RANDOM_WAVE_PRI[0], sizeof(mmSQ_RANDOM_WAVE_PRI)/sizeof(mmSQ_RANDOM_WAVE_PRI[0]), 0, 0 },
+	{ "mmSQ_REG_CREDITS", REG_MMIO, 0x2304, &mmSQ_REG_CREDITS[0], sizeof(mmSQ_REG_CREDITS)/sizeof(mmSQ_REG_CREDITS[0]), 0, 0 },
+	{ "mmSQ_FIFO_SIZES", REG_MMIO, 0x2305, &mmSQ_FIFO_SIZES[0], sizeof(mmSQ_FIFO_SIZES)/sizeof(mmSQ_FIFO_SIZES[0]), 0, 0 },
+	{ "mmCC_SQC_BANK_DISABLE", REG_MMIO, 0x2307, &mmCC_SQC_BANK_DISABLE[0], sizeof(mmCC_SQC_BANK_DISABLE)/sizeof(mmCC_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmUSER_SQC_BANK_DISABLE", REG_MMIO, 0x2308, &mmUSER_SQC_BANK_DISABLE[0], sizeof(mmUSER_SQC_BANK_DISABLE)/sizeof(mmUSER_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL", REG_MMIO, 0x2309, &mmSQ_DEBUG_STS_GLOBAL[0], sizeof(mmSQ_DEBUG_STS_GLOBAL)/sizeof(mmSQ_DEBUG_STS_GLOBAL[0]), 0, 0 },
+	{ "mmSH_MEM_BASES", REG_MMIO, 0x230a, &mmSH_MEM_BASES[0], sizeof(mmSH_MEM_BASES)/sizeof(mmSH_MEM_BASES[0]), 0, 0 },
+	{ "mmSH_MEM_APE1_BASE", REG_MMIO, 0x230b, &mmSH_MEM_APE1_BASE[0], sizeof(mmSH_MEM_APE1_BASE)/sizeof(mmSH_MEM_APE1_BASE[0]), 0, 0 },
+	{ "mmSH_MEM_APE1_LIMIT", REG_MMIO, 0x230c, &mmSH_MEM_APE1_LIMIT[0], sizeof(mmSH_MEM_APE1_LIMIT)/sizeof(mmSH_MEM_APE1_LIMIT[0]), 0, 0 },
+	{ "mmSH_MEM_CONFIG", REG_MMIO, 0x230d, &mmSH_MEM_CONFIG[0], sizeof(mmSH_MEM_CONFIG)/sizeof(mmSH_MEM_CONFIG[0]), 0, 0 },
+	{ "mmSQC_POLICY", REG_MMIO, 0x230e, &mmSQC_POLICY[0], sizeof(mmSQC_POLICY)/sizeof(mmSQC_POLICY[0]), 0, 0 },
+	{ "mmSQC_VOLATILE", REG_MMIO, 0x230f, &mmSQC_VOLATILE[0], sizeof(mmSQC_VOLATILE)/sizeof(mmSQC_VOLATILE[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL2", REG_MMIO, 0x2310, &mmSQ_DEBUG_STS_GLOBAL2[0], sizeof(mmSQ_DEBUG_STS_GLOBAL2)/sizeof(mmSQ_DEBUG_STS_GLOBAL2[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL3", REG_MMIO, 0x2311, &mmSQ_DEBUG_STS_GLOBAL3[0], sizeof(mmSQ_DEBUG_STS_GLOBAL3)/sizeof(mmSQ_DEBUG_STS_GLOBAL3[0]), 0, 0 },
+	{ "mmSQ_INTERRUPT_AUTO_MASK", REG_MMIO, 0x2314, &mmSQ_INTERRUPT_AUTO_MASK[0], sizeof(mmSQ_INTERRUPT_AUTO_MASK)/sizeof(mmSQ_INTERRUPT_AUTO_MASK[0]), 0, 0 },
+	{ "mmSQ_INTERRUPT_MSG_CTRL", REG_MMIO, 0x2315, &mmSQ_INTERRUPT_MSG_CTRL[0], sizeof(mmSQ_INTERRUPT_MSG_CTRL)/sizeof(mmSQ_INTERRUPT_MSG_CTRL[0]), 0, 0 },
+	{ "mmSQ_REG_TIMESTAMP", REG_MMIO, 0x2374, &mmSQ_REG_TIMESTAMP[0], sizeof(mmSQ_REG_TIMESTAMP)/sizeof(mmSQ_REG_TIMESTAMP[0]), 0, 0 },
+	{ "mmSQ_CMD_TIMESTAMP", REG_MMIO, 0x2375, &mmSQ_CMD_TIMESTAMP[0], sizeof(mmSQ_CMD_TIMESTAMP)/sizeof(mmSQ_CMD_TIMESTAMP[0]), 0, 0 },
+	{ "mmSQ_IND_INDEX", REG_MMIO, 0x2378, &mmSQ_IND_INDEX[0], sizeof(mmSQ_IND_INDEX)/sizeof(mmSQ_IND_INDEX[0]), 0, 0 },
+	{ "mmSQ_IND_DATA", REG_MMIO, 0x2379, &mmSQ_IND_DATA[0], sizeof(mmSQ_IND_DATA)/sizeof(mmSQ_IND_DATA[0]), 0, 0 },
+	{ "mmSQ_IND_CMD", REG_MMIO, 0x237a, NULL, 0, 0, 0 },
+	{ "mmSQ_CMD", REG_MMIO, 0x237b, &mmSQ_CMD[0], sizeof(mmSQ_CMD)/sizeof(mmSQ_CMD[0]), 0, 0 },
+	{ "mmSQ_TIME_HI", REG_MMIO, 0x237c, &mmSQ_TIME_HI[0], sizeof(mmSQ_TIME_HI)/sizeof(mmSQ_TIME_HI[0]), 0, 0 },
+	{ "mmSQ_TIME_LO", REG_MMIO, 0x237d, &mmSQ_TIME_LO[0], sizeof(mmSQ_TIME_LO)/sizeof(mmSQ_TIME_LO[0]), 0, 0 },
+	{ "mmSQ_VOP3_0_SDST_ENC", REG_MMIO, 0x237f, &mmSQ_VOP3_0_SDST_ENC[0], sizeof(mmSQ_VOP3_0_SDST_ENC)/sizeof(mmSQ_VOP3_0_SDST_ENC[0]), 0, 0 },
+	{ "mmSQ_MTBUF_1", REG_MMIO, 0x237f, &mmSQ_MTBUF_1[0], sizeof(mmSQ_MTBUF_1)/sizeof(mmSQ_MTBUF_1[0]), 0, 0 },
+	{ "mmSQ_VOP3_0", REG_MMIO, 0x237f, &mmSQ_VOP3_0[0], sizeof(mmSQ_VOP3_0)/sizeof(mmSQ_VOP3_0[0]), 0, 0 },
+	{ "mmSQ_EXP_1", REG_MMIO, 0x237f, &mmSQ_EXP_1[0], sizeof(mmSQ_EXP_1)/sizeof(mmSQ_EXP_1[0]), 0, 0 },
+	{ "mmSQ_SOP2", REG_MMIO, 0x237f, &mmSQ_SOP2[0], sizeof(mmSQ_SOP2)/sizeof(mmSQ_SOP2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE", REG_MMIO, 0x2380, &mmSQ_THREAD_TRACE_BASE[0], sizeof(mmSQ_THREAD_TRACE_BASE)/sizeof(mmSQ_THREAD_TRACE_BASE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_SIZE", REG_MMIO, 0x2381, &mmSQ_THREAD_TRACE_SIZE[0], sizeof(mmSQ_THREAD_TRACE_SIZE)/sizeof(mmSQ_THREAD_TRACE_SIZE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MASK", REG_MMIO, 0x2382, &mmSQ_THREAD_TRACE_MASK[0], sizeof(mmSQ_THREAD_TRACE_MASK)/sizeof(mmSQ_THREAD_TRACE_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK", REG_MMIO, 0x2383, &mmSQ_THREAD_TRACE_TOKEN_MASK[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_PERF_MASK", REG_MMIO, 0x2384, &mmSQ_THREAD_TRACE_PERF_MASK[0], sizeof(mmSQ_THREAD_TRACE_PERF_MASK)/sizeof(mmSQ_THREAD_TRACE_PERF_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE2", REG_MMIO, 0x2385, &mmSQ_THREAD_TRACE_BASE2[0], sizeof(mmSQ_THREAD_TRACE_BASE2)/sizeof(mmSQ_THREAD_TRACE_BASE2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK2", REG_MMIO, 0x2386, &mmSQ_THREAD_TRACE_TOKEN_MASK2[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WPTR", REG_MMIO, 0x238c, &mmSQ_THREAD_TRACE_WPTR[0], sizeof(mmSQ_THREAD_TRACE_WPTR)/sizeof(mmSQ_THREAD_TRACE_WPTR[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_STATUS", REG_MMIO, 0x238d, &mmSQ_THREAD_TRACE_STATUS[0], sizeof(mmSQ_THREAD_TRACE_STATUS)/sizeof(mmSQ_THREAD_TRACE_STATUS[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MODE", REG_MMIO, 0x238e, &mmSQ_THREAD_TRACE_MODE[0], sizeof(mmSQ_THREAD_TRACE_MODE)/sizeof(mmSQ_THREAD_TRACE_MODE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CTRL", REG_MMIO, 0x238f, &mmSQ_THREAD_TRACE_CTRL[0], sizeof(mmSQ_THREAD_TRACE_CTRL)/sizeof(mmSQ_THREAD_TRACE_CTRL[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CNTR", REG_MMIO, 0x2390, &mmSQ_THREAD_TRACE_CNTR[0], sizeof(mmSQ_THREAD_TRACE_CNTR)/sizeof(mmSQ_THREAD_TRACE_CNTR[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_HIWATER", REG_MMIO, 0x2392, &mmSQ_THREAD_TRACE_HIWATER[0], sizeof(mmSQ_THREAD_TRACE_HIWATER)/sizeof(mmSQ_THREAD_TRACE_HIWATER[0]), 0, 0 },
+	{ "mmSQ_LB_CTR_CTRL", REG_MMIO, 0x2398, &mmSQ_LB_CTR_CTRL[0], sizeof(mmSQ_LB_CTR_CTRL)/sizeof(mmSQ_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_CYCLES", REG_MMIO, 0x2399, &mmSQ_LB_DATA_ALU_CYCLES[0], sizeof(mmSQ_LB_DATA_ALU_CYCLES)/sizeof(mmSQ_LB_DATA_ALU_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_CYCLES", REG_MMIO, 0x239a, &mmSQ_LB_DATA_TEX_CYCLES[0], sizeof(mmSQ_LB_DATA_TEX_CYCLES)/sizeof(mmSQ_LB_DATA_TEX_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_STALLS", REG_MMIO, 0x239b, &mmSQ_LB_DATA_ALU_STALLS[0], sizeof(mmSQ_LB_DATA_ALU_STALLS)/sizeof(mmSQ_LB_DATA_ALU_STALLS[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_STALLS", REG_MMIO, 0x239c, &mmSQ_LB_DATA_TEX_STALLS[0], sizeof(mmSQ_LB_DATA_TEX_STALLS)/sizeof(mmSQ_LB_DATA_TEX_STALLS[0]), 0, 0 },
+	{ "mmSQC_SECDED_CNT", REG_MMIO, 0x23a0, &mmSQC_SECDED_CNT[0], sizeof(mmSQC_SECDED_CNT)/sizeof(mmSQC_SECDED_CNT[0]), 0, 0 },
+	{ "mmSQ_SEC_CNT", REG_MMIO, 0x23a1, &mmSQ_SEC_CNT[0], sizeof(mmSQ_SEC_CNT)/sizeof(mmSQ_SEC_CNT[0]), 0, 0 },
+	{ "mmSQ_DED_CNT", REG_MMIO, 0x23a2, &mmSQ_DED_CNT[0], sizeof(mmSQ_DED_CNT)/sizeof(mmSQ_DED_CNT[0]), 0, 0 },
+	{ "mmSQ_DED_INFO", REG_MMIO, 0x23a3, &mmSQ_DED_INFO[0], sizeof(mmSQ_DED_INFO)/sizeof(mmSQ_DED_INFO[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_WAVE_START", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_WAVE_START[0], sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START)/sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_EVENT", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_EVENT[0], sizeof(mmSQ_THREAD_TRACE_WORD_EVENT)/sizeof(mmSQ_THREAD_TRACE_WORD_EVENT[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST)/sizeof(mmSQ_THREAD_TRACE_WORD_INST[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_CMN", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_CMN[0], sizeof(mmSQ_THREAD_TRACE_WORD_CMN)/sizeof(mmSQ_THREAD_TRACE_WORD_CMN[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD0", REG_MMIO, 0x23c0, &mmSQ_BUF_RSRC_WORD0[0], sizeof(mmSQ_BUF_RSRC_WORD0)/sizeof(mmSQ_BUF_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD1", REG_MMIO, 0x23c1, &mmSQ_BUF_RSRC_WORD1[0], sizeof(mmSQ_BUF_RSRC_WORD1)/sizeof(mmSQ_BUF_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD2", REG_MMIO, 0x23c2, &mmSQ_BUF_RSRC_WORD2[0], sizeof(mmSQ_BUF_RSRC_WORD2)/sizeof(mmSQ_BUF_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD3", REG_MMIO, 0x23c3, &mmSQ_BUF_RSRC_WORD3[0], sizeof(mmSQ_BUF_RSRC_WORD3)/sizeof(mmSQ_BUF_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD0", REG_MMIO, 0x23c4, &mmSQ_IMG_RSRC_WORD0[0], sizeof(mmSQ_IMG_RSRC_WORD0)/sizeof(mmSQ_IMG_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD1", REG_MMIO, 0x23c5, &mmSQ_IMG_RSRC_WORD1[0], sizeof(mmSQ_IMG_RSRC_WORD1)/sizeof(mmSQ_IMG_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD2", REG_MMIO, 0x23c6, &mmSQ_IMG_RSRC_WORD2[0], sizeof(mmSQ_IMG_RSRC_WORD2)/sizeof(mmSQ_IMG_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD3", REG_MMIO, 0x23c7, &mmSQ_IMG_RSRC_WORD3[0], sizeof(mmSQ_IMG_RSRC_WORD3)/sizeof(mmSQ_IMG_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD4", REG_MMIO, 0x23c8, &mmSQ_IMG_RSRC_WORD4[0], sizeof(mmSQ_IMG_RSRC_WORD4)/sizeof(mmSQ_IMG_RSRC_WORD4[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD5", REG_MMIO, 0x23c9, &mmSQ_IMG_RSRC_WORD5[0], sizeof(mmSQ_IMG_RSRC_WORD5)/sizeof(mmSQ_IMG_RSRC_WORD5[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD6", REG_MMIO, 0x23ca, &mmSQ_IMG_RSRC_WORD6[0], sizeof(mmSQ_IMG_RSRC_WORD6)/sizeof(mmSQ_IMG_RSRC_WORD6[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD7", REG_MMIO, 0x23cb, &mmSQ_IMG_RSRC_WORD7[0], sizeof(mmSQ_IMG_RSRC_WORD7)/sizeof(mmSQ_IMG_RSRC_WORD7[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD0", REG_MMIO, 0x23cc, &mmSQ_IMG_SAMP_WORD0[0], sizeof(mmSQ_IMG_SAMP_WORD0)/sizeof(mmSQ_IMG_SAMP_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD1", REG_MMIO, 0x23cd, &mmSQ_IMG_SAMP_WORD1[0], sizeof(mmSQ_IMG_SAMP_WORD1)/sizeof(mmSQ_IMG_SAMP_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD2", REG_MMIO, 0x23ce, &mmSQ_IMG_SAMP_WORD2[0], sizeof(mmSQ_IMG_SAMP_WORD2)/sizeof(mmSQ_IMG_SAMP_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD3", REG_MMIO, 0x23cf, &mmSQ_IMG_SAMP_WORD3[0], sizeof(mmSQ_IMG_SAMP_WORD3)/sizeof(mmSQ_IMG_SAMP_WORD3[0]), 0, 0 },
+	{ "mmSQ_FLAT_SCRATCH_WORD0", REG_MMIO, 0x23d0, &mmSQ_FLAT_SCRATCH_WORD0[0], sizeof(mmSQ_FLAT_SCRATCH_WORD0)/sizeof(mmSQ_FLAT_SCRATCH_WORD0[0]), 0, 0 },
+	{ "mmSQ_FLAT_SCRATCH_WORD1", REG_MMIO, 0x23d1, &mmSQ_FLAT_SCRATCH_WORD1[0], sizeof(mmSQ_FLAT_SCRATCH_WORD1)/sizeof(mmSQ_FLAT_SCRATCH_WORD1[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG26", REG_SMC, 0x24, &ixVGT_DEBUG_REG26[0], sizeof(ixVGT_DEBUG_REG26)/sizeof(ixVGT_DEBUG_REG26[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY", REG_MMIO, 0x2414, &mmSX_DEBUG_BUSY[0], sizeof(mmSX_DEBUG_BUSY)/sizeof(mmSX_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_2", REG_MMIO, 0x2415, &mmSX_DEBUG_BUSY_2[0], sizeof(mmSX_DEBUG_BUSY_2)/sizeof(mmSX_DEBUG_BUSY_2[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_3", REG_MMIO, 0x2416, &mmSX_DEBUG_BUSY_3[0], sizeof(mmSX_DEBUG_BUSY_3)/sizeof(mmSX_DEBUG_BUSY_3[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_4", REG_MMIO, 0x2417, &mmSX_DEBUG_BUSY_4[0], sizeof(mmSX_DEBUG_BUSY_4)/sizeof(mmSX_DEBUG_BUSY_4[0]), 0, 0 },
+	{ "mmSX_DEBUG_1", REG_MMIO, 0x2418, &mmSX_DEBUG_1[0], sizeof(mmSX_DEBUG_1)/sizeof(mmSX_DEBUG_1[0]), 0, 0 },
+	{ "mmSPI_PS_MAX_WAVE_ID", REG_MMIO, 0x243a, &mmSPI_PS_MAX_WAVE_ID[0], sizeof(mmSPI_PS_MAX_WAVE_ID)/sizeof(mmSPI_PS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL", REG_MMIO, 0x2440, &mmSPI_CONFIG_CNTL[0], sizeof(mmSPI_CONFIG_CNTL)/sizeof(mmSPI_CONFIG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_CNTL", REG_MMIO, 0x2441, &mmSPI_DEBUG_CNTL[0], sizeof(mmSPI_DEBUG_CNTL)/sizeof(mmSPI_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_READ", REG_MMIO, 0x2442, &mmSPI_DEBUG_READ[0], sizeof(mmSPI_DEBUG_READ)/sizeof(mmSPI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL_1", REG_MMIO, 0x244f, &mmSPI_CONFIG_CNTL_1[0], sizeof(mmSPI_CONFIG_CNTL_1)/sizeof(mmSPI_CONFIG_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_DEBUG_BUSY", REG_MMIO, 0x2450, &mmSPI_DEBUG_BUSY[0], sizeof(mmSPI_DEBUG_BUSY)/sizeof(mmSPI_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_CNTL", REG_MMIO, 0x24aa, &mmSPI_WF_LIFETIME_CNTL[0], sizeof(mmSPI_WF_LIFETIME_CNTL)/sizeof(mmSPI_WF_LIFETIME_CNTL[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_0", REG_MMIO, 0x24ab, &mmSPI_WF_LIFETIME_LIMIT_0[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_0)/sizeof(mmSPI_WF_LIFETIME_LIMIT_0[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_1", REG_MMIO, 0x24ac, &mmSPI_WF_LIFETIME_LIMIT_1[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_1)/sizeof(mmSPI_WF_LIFETIME_LIMIT_1[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_2", REG_MMIO, 0x24ad, &mmSPI_WF_LIFETIME_LIMIT_2[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_2)/sizeof(mmSPI_WF_LIFETIME_LIMIT_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_3", REG_MMIO, 0x24ae, &mmSPI_WF_LIFETIME_LIMIT_3[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_3)/sizeof(mmSPI_WF_LIFETIME_LIMIT_3[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_4", REG_MMIO, 0x24af, &mmSPI_WF_LIFETIME_LIMIT_4[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_4)/sizeof(mmSPI_WF_LIFETIME_LIMIT_4[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_5", REG_MMIO, 0x24b0, &mmSPI_WF_LIFETIME_LIMIT_5[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_5)/sizeof(mmSPI_WF_LIFETIME_LIMIT_5[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_6", REG_MMIO, 0x24b1, &mmSPI_WF_LIFETIME_LIMIT_6[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_6)/sizeof(mmSPI_WF_LIFETIME_LIMIT_6[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_7", REG_MMIO, 0x24b2, &mmSPI_WF_LIFETIME_LIMIT_7[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_7)/sizeof(mmSPI_WF_LIFETIME_LIMIT_7[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_8", REG_MMIO, 0x24b3, &mmSPI_WF_LIFETIME_LIMIT_8[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_8)/sizeof(mmSPI_WF_LIFETIME_LIMIT_8[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_9", REG_MMIO, 0x24b4, &mmSPI_WF_LIFETIME_LIMIT_9[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_9)/sizeof(mmSPI_WF_LIFETIME_LIMIT_9[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_0", REG_MMIO, 0x24b5, &mmSPI_WF_LIFETIME_STATUS_0[0], sizeof(mmSPI_WF_LIFETIME_STATUS_0)/sizeof(mmSPI_WF_LIFETIME_STATUS_0[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_1", REG_MMIO, 0x24b6, &mmSPI_WF_LIFETIME_STATUS_1[0], sizeof(mmSPI_WF_LIFETIME_STATUS_1)/sizeof(mmSPI_WF_LIFETIME_STATUS_1[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_2", REG_MMIO, 0x24b7, &mmSPI_WF_LIFETIME_STATUS_2[0], sizeof(mmSPI_WF_LIFETIME_STATUS_2)/sizeof(mmSPI_WF_LIFETIME_STATUS_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_3", REG_MMIO, 0x24b8, &mmSPI_WF_LIFETIME_STATUS_3[0], sizeof(mmSPI_WF_LIFETIME_STATUS_3)/sizeof(mmSPI_WF_LIFETIME_STATUS_3[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_4", REG_MMIO, 0x24b9, &mmSPI_WF_LIFETIME_STATUS_4[0], sizeof(mmSPI_WF_LIFETIME_STATUS_4)/sizeof(mmSPI_WF_LIFETIME_STATUS_4[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_5", REG_MMIO, 0x24ba, &mmSPI_WF_LIFETIME_STATUS_5[0], sizeof(mmSPI_WF_LIFETIME_STATUS_5)/sizeof(mmSPI_WF_LIFETIME_STATUS_5[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_6", REG_MMIO, 0x24bb, &mmSPI_WF_LIFETIME_STATUS_6[0], sizeof(mmSPI_WF_LIFETIME_STATUS_6)/sizeof(mmSPI_WF_LIFETIME_STATUS_6[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_7", REG_MMIO, 0x24bc, &mmSPI_WF_LIFETIME_STATUS_7[0], sizeof(mmSPI_WF_LIFETIME_STATUS_7)/sizeof(mmSPI_WF_LIFETIME_STATUS_7[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_8", REG_MMIO, 0x24bd, &mmSPI_WF_LIFETIME_STATUS_8[0], sizeof(mmSPI_WF_LIFETIME_STATUS_8)/sizeof(mmSPI_WF_LIFETIME_STATUS_8[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_9", REG_MMIO, 0x24be, &mmSPI_WF_LIFETIME_STATUS_9[0], sizeof(mmSPI_WF_LIFETIME_STATUS_9)/sizeof(mmSPI_WF_LIFETIME_STATUS_9[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_10", REG_MMIO, 0x24bf, &mmSPI_WF_LIFETIME_STATUS_10[0], sizeof(mmSPI_WF_LIFETIME_STATUS_10)/sizeof(mmSPI_WF_LIFETIME_STATUS_10[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_11", REG_MMIO, 0x24c0, &mmSPI_WF_LIFETIME_STATUS_11[0], sizeof(mmSPI_WF_LIFETIME_STATUS_11)/sizeof(mmSPI_WF_LIFETIME_STATUS_11[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_12", REG_MMIO, 0x24c1, &mmSPI_WF_LIFETIME_STATUS_12[0], sizeof(mmSPI_WF_LIFETIME_STATUS_12)/sizeof(mmSPI_WF_LIFETIME_STATUS_12[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_13", REG_MMIO, 0x24c2, &mmSPI_WF_LIFETIME_STATUS_13[0], sizeof(mmSPI_WF_LIFETIME_STATUS_13)/sizeof(mmSPI_WF_LIFETIME_STATUS_13[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_14", REG_MMIO, 0x24c3, &mmSPI_WF_LIFETIME_STATUS_14[0], sizeof(mmSPI_WF_LIFETIME_STATUS_14)/sizeof(mmSPI_WF_LIFETIME_STATUS_14[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_15", REG_MMIO, 0x24c4, &mmSPI_WF_LIFETIME_STATUS_15[0], sizeof(mmSPI_WF_LIFETIME_STATUS_15)/sizeof(mmSPI_WF_LIFETIME_STATUS_15[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_16", REG_MMIO, 0x24c5, &mmSPI_WF_LIFETIME_STATUS_16[0], sizeof(mmSPI_WF_LIFETIME_STATUS_16)/sizeof(mmSPI_WF_LIFETIME_STATUS_16[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_17", REG_MMIO, 0x24c6, &mmSPI_WF_LIFETIME_STATUS_17[0], sizeof(mmSPI_WF_LIFETIME_STATUS_17)/sizeof(mmSPI_WF_LIFETIME_STATUS_17[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_18", REG_MMIO, 0x24c7, &mmSPI_WF_LIFETIME_STATUS_18[0], sizeof(mmSPI_WF_LIFETIME_STATUS_18)/sizeof(mmSPI_WF_LIFETIME_STATUS_18[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_19", REG_MMIO, 0x24c8, &mmSPI_WF_LIFETIME_STATUS_19[0], sizeof(mmSPI_WF_LIFETIME_STATUS_19)/sizeof(mmSPI_WF_LIFETIME_STATUS_19[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_20", REG_MMIO, 0x24c9, &mmSPI_WF_LIFETIME_STATUS_20[0], sizeof(mmSPI_WF_LIFETIME_STATUS_20)/sizeof(mmSPI_WF_LIFETIME_STATUS_20[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_DEBUG", REG_MMIO, 0x24ca, &mmSPI_WF_LIFETIME_DEBUG[0], sizeof(mmSPI_WF_LIFETIME_DEBUG)/sizeof(mmSPI_WF_LIFETIME_DEBUG[0]), 0, 0 },
+	{ "mmSPI_SLAVE_DEBUG_BUSY", REG_MMIO, 0x24d3, &mmSPI_SLAVE_DEBUG_BUSY[0], sizeof(mmSPI_SLAVE_DEBUG_BUSY)/sizeof(mmSPI_SLAVE_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_LB_CTR_CTRL", REG_MMIO, 0x24d4, &mmSPI_LB_CTR_CTRL[0], sizeof(mmSPI_LB_CTR_CTRL)/sizeof(mmSPI_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSPI_LB_CU_MASK", REG_MMIO, 0x24d5, &mmSPI_LB_CU_MASK[0], sizeof(mmSPI_LB_CU_MASK)/sizeof(mmSPI_LB_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_LB_DATA_REG", REG_MMIO, 0x24d6, &mmSPI_LB_DATA_REG[0], sizeof(mmSPI_LB_DATA_REG)/sizeof(mmSPI_LB_DATA_REG[0]), 0, 0 },
+	{ "mmSPI_PG_ENABLE_STATIC_CU_MASK", REG_MMIO, 0x24d7, &mmSPI_PG_ENABLE_STATIC_CU_MASK[0], sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK)/sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_GDS_CREDITS", REG_MMIO, 0x24d8, &mmSPI_GDS_CREDITS[0], sizeof(mmSPI_GDS_CREDITS)/sizeof(mmSPI_GDS_CREDITS[0]), 0, 0 },
+	{ "mmSPI_SX_EXPORT_BUFFER_SIZES", REG_MMIO, 0x24d9, &mmSPI_SX_EXPORT_BUFFER_SIZES[0], sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES)/sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_SX_SCOREBOARD_BUFFER_SIZES", REG_MMIO, 0x24da, &mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0], sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES)/sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_STATUS", REG_MMIO, 0x24db, &mmSPI_CSQ_WF_ACTIVE_STATUS[0], sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS)/sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_0", REG_MMIO, 0x24dc, &mmSPI_CSQ_WF_ACTIVE_COUNT_0[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_1", REG_MMIO, 0x24dd, &mmSPI_CSQ_WF_ACTIVE_COUNT_1[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_2", REG_MMIO, 0x24de, &mmSPI_CSQ_WF_ACTIVE_COUNT_2[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_3", REG_MMIO, 0x24df, &mmSPI_CSQ_WF_ACTIVE_COUNT_3[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_4", REG_MMIO, 0x24e0, &mmSPI_CSQ_WF_ACTIVE_COUNT_4[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_5", REG_MMIO, 0x24e1, &mmSPI_CSQ_WF_ACTIVE_COUNT_5[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_6", REG_MMIO, 0x24e2, &mmSPI_CSQ_WF_ACTIVE_COUNT_6[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_7", REG_MMIO, 0x24e3, &mmSPI_CSQ_WF_ACTIVE_COUNT_7[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7[0]), 0, 0 },
+	{ "mmBCI_DEBUG_READ", REG_MMIO, 0x24eb, &mmBCI_DEBUG_READ[0], sizeof(mmBCI_DEBUG_READ)/sizeof(mmBCI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24ec, &mmSPI_P0_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24ed, &mmSPI_P0_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24ee, &mmSPI_P0_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24ef, &mmSPI_P0_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f0, &mmSPI_P0_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24f1, &mmSPI_P1_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24f2, &mmSPI_P1_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24f3, &mmSPI_P1_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24f4, &mmSPI_P1_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f5, &mmSPI_P1_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG30", REG_SMC, 0x25, &ixVGT_DEBUG_REG30[0], sizeof(ixVGT_DEBUG_REG30)/sizeof(ixVGT_DEBUG_REG30[0]), 0, 0 },
+	{ "mmTD_CNTL", REG_MMIO, 0x2525, &mmTD_CNTL[0], sizeof(mmTD_CNTL)/sizeof(mmTD_CNTL[0]), 0, 0 },
+	{ "mmTD_STATUS", REG_MMIO, 0x2526, &mmTD_STATUS[0], sizeof(mmTD_STATUS)/sizeof(mmTD_STATUS[0]), 0, 0 },
+	{ "mmTD_DEBUG_INDEX", REG_MMIO, 0x2528, &mmTD_DEBUG_INDEX[0], sizeof(mmTD_DEBUG_INDEX)/sizeof(mmTD_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTD_DEBUG_DATA", REG_MMIO, 0x2529, &mmTD_DEBUG_DATA[0], sizeof(mmTD_DEBUG_DATA)/sizeof(mmTD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTD_SCRATCH", REG_MMIO, 0x2533, &mmTD_SCRATCH[0], sizeof(mmTD_SCRATCH)/sizeof(mmTD_SCRATCH[0]), 0, 0 },
+	{ "mmTA_CNTL", REG_MMIO, 0x2541, &mmTA_CNTL[0], sizeof(mmTA_CNTL)/sizeof(mmTA_CNTL[0]), 0, 0 },
+	{ "mmTA_CNTL_AUX", REG_MMIO, 0x2542, &mmTA_CNTL_AUX[0], sizeof(mmTA_CNTL_AUX)/sizeof(mmTA_CNTL_AUX[0]), 0, 0 },
+	{ "mmTA_RESERVED_010C", REG_MMIO, 0x2543, &mmTA_RESERVED_010C[0], sizeof(mmTA_RESERVED_010C)/sizeof(mmTA_RESERVED_010C[0]), 0, 0 },
+	{ "mmTA_STATUS", REG_MMIO, 0x2548, &mmTA_STATUS[0], sizeof(mmTA_STATUS)/sizeof(mmTA_STATUS[0]), 0, 0 },
+	{ "mmTA_DEBUG_INDEX", REG_MMIO, 0x254c, &mmTA_DEBUG_INDEX[0], sizeof(mmTA_DEBUG_INDEX)/sizeof(mmTA_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTA_DEBUG_DATA", REG_MMIO, 0x254d, &mmTA_DEBUG_DATA[0], sizeof(mmTA_DEBUG_DATA)/sizeof(mmTA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTA_SCRATCH", REG_MMIO, 0x2564, &mmTA_SCRATCH[0], sizeof(mmTA_SCRATCH)/sizeof(mmTA_SCRATCH[0]), 0, 0 },
+	{ "mmSH_HIDDEN_PRIVATE_BASE_VMID", REG_MMIO, 0x2580, &mmSH_HIDDEN_PRIVATE_BASE_VMID[0], sizeof(mmSH_HIDDEN_PRIVATE_BASE_VMID)/sizeof(mmSH_HIDDEN_PRIVATE_BASE_VMID[0]), 0, 0 },
+	{ "mmSH_STATIC_MEM_CONFIG", REG_MMIO, 0x2581, &mmSH_STATIC_MEM_CONFIG[0], sizeof(mmSH_STATIC_MEM_CONFIG)/sizeof(mmSH_STATIC_MEM_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CONFIG", REG_MMIO, 0x25c0, &mmGDS_CONFIG[0], sizeof(mmGDS_CONFIG)/sizeof(mmGDS_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CNTL_STATUS", REG_MMIO, 0x25c1, &mmGDS_CNTL_STATUS[0], sizeof(mmGDS_CNTL_STATUS)/sizeof(mmGDS_CNTL_STATUS[0]), 0, 0 },
+	{ "mmGDS_ENHANCE2", REG_MMIO, 0x25c2, &mmGDS_ENHANCE2[0], sizeof(mmGDS_ENHANCE2)/sizeof(mmGDS_ENHANCE2[0]), 0, 0 },
+	{ "mmGDS_PROTECTION_FAULT", REG_MMIO, 0x25c3, &mmGDS_PROTECTION_FAULT[0], sizeof(mmGDS_PROTECTION_FAULT)/sizeof(mmGDS_PROTECTION_FAULT[0]), 0, 0 },
+	{ "mmGDS_VM_PROTECTION_FAULT", REG_MMIO, 0x25c4, &mmGDS_VM_PROTECTION_FAULT[0], sizeof(mmGDS_VM_PROTECTION_FAULT)/sizeof(mmGDS_VM_PROTECTION_FAULT[0]), 0, 0 },
+	{ "mmGDS_SECDED_CNT", REG_MMIO, 0x25c5, &mmGDS_SECDED_CNT[0], sizeof(mmGDS_SECDED_CNT)/sizeof(mmGDS_SECDED_CNT[0]), 0, 0 },
+	{ "mmGDS_GRBM_SECDED_CNT", REG_MMIO, 0x25c6, &mmGDS_GRBM_SECDED_CNT[0], sizeof(mmGDS_GRBM_SECDED_CNT)/sizeof(mmGDS_GRBM_SECDED_CNT[0]), 0, 0 },
+	{ "mmGDS_OA_DED", REG_MMIO, 0x25c7, &mmGDS_OA_DED[0], sizeof(mmGDS_OA_DED)/sizeof(mmGDS_OA_DED[0]), 0, 0 },
+	{ "mmGDS_DEBUG_CNTL", REG_MMIO, 0x25c8, &mmGDS_DEBUG_CNTL[0], sizeof(mmGDS_DEBUG_CNTL)/sizeof(mmGDS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGDS_DEBUG_DATA", REG_MMIO, 0x25c9, &mmGDS_DEBUG_DATA[0], sizeof(mmGDS_DEBUG_DATA)/sizeof(mmGDS_DEBUG_DATA[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG31", REG_SMC, 0x26, &ixVGT_DEBUG_REG31[0], sizeof(ixVGT_DEBUG_REG31)/sizeof(ixVGT_DEBUG_REG31[0]), 0, 0 },
+	{ "mmDB_DEBUG", REG_MMIO, 0x260c, &mmDB_DEBUG[0], sizeof(mmDB_DEBUG)/sizeof(mmDB_DEBUG[0]), 0, 0 },
+	{ "mmDB_DEBUG2", REG_MMIO, 0x260d, &mmDB_DEBUG2[0], sizeof(mmDB_DEBUG2)/sizeof(mmDB_DEBUG2[0]), 0, 0 },
+	{ "mmDB_DEBUG3", REG_MMIO, 0x260e, &mmDB_DEBUG3[0], sizeof(mmDB_DEBUG3)/sizeof(mmDB_DEBUG3[0]), 0, 0 },
+	{ "mmDB_DEBUG4", REG_MMIO, 0x260f, &mmDB_DEBUG4[0], sizeof(mmDB_DEBUG4)/sizeof(mmDB_DEBUG4[0]), 0, 0 },
+	{ "mmDB_CREDIT_LIMIT", REG_MMIO, 0x2614, &mmDB_CREDIT_LIMIT[0], sizeof(mmDB_CREDIT_LIMIT)/sizeof(mmDB_CREDIT_LIMIT[0]), 0, 0 },
+	{ "mmDB_WATERMARKS", REG_MMIO, 0x2615, &mmDB_WATERMARKS[0], sizeof(mmDB_WATERMARKS)/sizeof(mmDB_WATERMARKS[0]), 0, 0 },
+	{ "mmDB_SUBTILE_CONTROL", REG_MMIO, 0x2616, &mmDB_SUBTILE_CONTROL[0], sizeof(mmDB_SUBTILE_CONTROL)/sizeof(mmDB_SUBTILE_CONTROL[0]), 0, 0 },
+	{ "mmDB_FREE_CACHELINES", REG_MMIO, 0x2617, &mmDB_FREE_CACHELINES[0], sizeof(mmDB_FREE_CACHELINES)/sizeof(mmDB_FREE_CACHELINES[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH1", REG_MMIO, 0x2618, &mmDB_FIFO_DEPTH1[0], sizeof(mmDB_FIFO_DEPTH1)/sizeof(mmDB_FIFO_DEPTH1[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH2", REG_MMIO, 0x2619, &mmDB_FIFO_DEPTH2[0], sizeof(mmDB_FIFO_DEPTH2)/sizeof(mmDB_FIFO_DEPTH2[0]), 0, 0 },
+	{ "mmDB_RING_CONTROL", REG_MMIO, 0x261b, &mmDB_RING_CONTROL[0], sizeof(mmDB_RING_CONTROL)/sizeof(mmDB_RING_CONTROL[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_0", REG_MMIO, 0x2620, &mmDB_READ_DEBUG_0[0], sizeof(mmDB_READ_DEBUG_0)/sizeof(mmDB_READ_DEBUG_0[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_1", REG_MMIO, 0x2621, &mmDB_READ_DEBUG_1[0], sizeof(mmDB_READ_DEBUG_1)/sizeof(mmDB_READ_DEBUG_1[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_2", REG_MMIO, 0x2622, &mmDB_READ_DEBUG_2[0], sizeof(mmDB_READ_DEBUG_2)/sizeof(mmDB_READ_DEBUG_2[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_3", REG_MMIO, 0x2623, &mmDB_READ_DEBUG_3[0], sizeof(mmDB_READ_DEBUG_3)/sizeof(mmDB_READ_DEBUG_3[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_4", REG_MMIO, 0x2624, &mmDB_READ_DEBUG_4[0], sizeof(mmDB_READ_DEBUG_4)/sizeof(mmDB_READ_DEBUG_4[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_5", REG_MMIO, 0x2625, &mmDB_READ_DEBUG_5[0], sizeof(mmDB_READ_DEBUG_5)/sizeof(mmDB_READ_DEBUG_5[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_6", REG_MMIO, 0x2626, &mmDB_READ_DEBUG_6[0], sizeof(mmDB_READ_DEBUG_6)/sizeof(mmDB_READ_DEBUG_6[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_7", REG_MMIO, 0x2627, &mmDB_READ_DEBUG_7[0], sizeof(mmDB_READ_DEBUG_7)/sizeof(mmDB_READ_DEBUG_7[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_8", REG_MMIO, 0x2628, &mmDB_READ_DEBUG_8[0], sizeof(mmDB_READ_DEBUG_8)/sizeof(mmDB_READ_DEBUG_8[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_9", REG_MMIO, 0x2629, &mmDB_READ_DEBUG_9[0], sizeof(mmDB_READ_DEBUG_9)/sizeof(mmDB_READ_DEBUG_9[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_A", REG_MMIO, 0x262a, &mmDB_READ_DEBUG_A[0], sizeof(mmDB_READ_DEBUG_A)/sizeof(mmDB_READ_DEBUG_A[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_B", REG_MMIO, 0x262b, &mmDB_READ_DEBUG_B[0], sizeof(mmDB_READ_DEBUG_B)/sizeof(mmDB_READ_DEBUG_B[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_C", REG_MMIO, 0x262c, &mmDB_READ_DEBUG_C[0], sizeof(mmDB_READ_DEBUG_C)/sizeof(mmDB_READ_DEBUG_C[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_D", REG_MMIO, 0x262d, &mmDB_READ_DEBUG_D[0], sizeof(mmDB_READ_DEBUG_D)/sizeof(mmDB_READ_DEBUG_D[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_E", REG_MMIO, 0x262e, &mmDB_READ_DEBUG_E[0], sizeof(mmDB_READ_DEBUG_E)/sizeof(mmDB_READ_DEBUG_E[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_F", REG_MMIO, 0x262f, &mmDB_READ_DEBUG_F[0], sizeof(mmDB_READ_DEBUG_F)/sizeof(mmDB_READ_DEBUG_F[0]), 0, 0 },
+	{ "mmCC_RB_REDUNDANCY", REG_MMIO, 0x263c, &mmCC_RB_REDUNDANCY[0], sizeof(mmCC_RB_REDUNDANCY)/sizeof(mmCC_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmCC_RB_BACKEND_DISABLE", REG_MMIO, 0x263d, &mmCC_RB_BACKEND_DISABLE[0], sizeof(mmCC_RB_BACKEND_DISABLE)/sizeof(mmCC_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmGB_ADDR_CONFIG", REG_MMIO, 0x263e, &mmGB_ADDR_CONFIG[0], sizeof(mmGB_ADDR_CONFIG)/sizeof(mmGB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmGB_BACKEND_MAP", REG_MMIO, 0x263f, &mmGB_BACKEND_MAP[0], sizeof(mmGB_BACKEND_MAP)/sizeof(mmGB_BACKEND_MAP[0]), 0, 0 },
+	{ "mmGB_GPU_ID", REG_MMIO, 0x2640, &mmGB_GPU_ID[0], sizeof(mmGB_GPU_ID)/sizeof(mmGB_GPU_ID[0]), 0, 0 },
+	{ "mmCC_RB_DAISY_CHAIN", REG_MMIO, 0x2641, &mmCC_RB_DAISY_CHAIN[0], sizeof(mmCC_RB_DAISY_CHAIN)/sizeof(mmCC_RB_DAISY_CHAIN[0]), 0, 0 },
+	{ "mmGB_TILE_MODE0", REG_MMIO, 0x2644, &mmGB_TILE_MODE0[0], sizeof(mmGB_TILE_MODE0)/sizeof(mmGB_TILE_MODE0[0]), 0, 0 },
+	{ "mmGB_TILE_MODE1", REG_MMIO, 0x2645, &mmGB_TILE_MODE1[0], sizeof(mmGB_TILE_MODE1)/sizeof(mmGB_TILE_MODE1[0]), 0, 0 },
+	{ "mmGB_TILE_MODE2", REG_MMIO, 0x2646, &mmGB_TILE_MODE2[0], sizeof(mmGB_TILE_MODE2)/sizeof(mmGB_TILE_MODE2[0]), 0, 0 },
+	{ "mmGB_TILE_MODE3", REG_MMIO, 0x2647, &mmGB_TILE_MODE3[0], sizeof(mmGB_TILE_MODE3)/sizeof(mmGB_TILE_MODE3[0]), 0, 0 },
+	{ "mmGB_TILE_MODE4", REG_MMIO, 0x2648, &mmGB_TILE_MODE4[0], sizeof(mmGB_TILE_MODE4)/sizeof(mmGB_TILE_MODE4[0]), 0, 0 },
+	{ "mmGB_TILE_MODE5", REG_MMIO, 0x2649, &mmGB_TILE_MODE5[0], sizeof(mmGB_TILE_MODE5)/sizeof(mmGB_TILE_MODE5[0]), 0, 0 },
+	{ "mmGB_TILE_MODE6", REG_MMIO, 0x264a, &mmGB_TILE_MODE6[0], sizeof(mmGB_TILE_MODE6)/sizeof(mmGB_TILE_MODE6[0]), 0, 0 },
+	{ "mmGB_TILE_MODE7", REG_MMIO, 0x264b, &mmGB_TILE_MODE7[0], sizeof(mmGB_TILE_MODE7)/sizeof(mmGB_TILE_MODE7[0]), 0, 0 },
+	{ "mmGB_TILE_MODE8", REG_MMIO, 0x264c, &mmGB_TILE_MODE8[0], sizeof(mmGB_TILE_MODE8)/sizeof(mmGB_TILE_MODE8[0]), 0, 0 },
+	{ "mmGB_TILE_MODE9", REG_MMIO, 0x264d, &mmGB_TILE_MODE9[0], sizeof(mmGB_TILE_MODE9)/sizeof(mmGB_TILE_MODE9[0]), 0, 0 },
+	{ "mmGB_TILE_MODE10", REG_MMIO, 0x264e, &mmGB_TILE_MODE10[0], sizeof(mmGB_TILE_MODE10)/sizeof(mmGB_TILE_MODE10[0]), 0, 0 },
+	{ "mmGB_TILE_MODE11", REG_MMIO, 0x264f, &mmGB_TILE_MODE11[0], sizeof(mmGB_TILE_MODE11)/sizeof(mmGB_TILE_MODE11[0]), 0, 0 },
+	{ "mmGB_TILE_MODE12", REG_MMIO, 0x2650, &mmGB_TILE_MODE12[0], sizeof(mmGB_TILE_MODE12)/sizeof(mmGB_TILE_MODE12[0]), 0, 0 },
+	{ "mmGB_TILE_MODE13", REG_MMIO, 0x2651, &mmGB_TILE_MODE13[0], sizeof(mmGB_TILE_MODE13)/sizeof(mmGB_TILE_MODE13[0]), 0, 0 },
+	{ "mmGB_TILE_MODE14", REG_MMIO, 0x2652, &mmGB_TILE_MODE14[0], sizeof(mmGB_TILE_MODE14)/sizeof(mmGB_TILE_MODE14[0]), 0, 0 },
+	{ "mmGB_TILE_MODE15", REG_MMIO, 0x2653, &mmGB_TILE_MODE15[0], sizeof(mmGB_TILE_MODE15)/sizeof(mmGB_TILE_MODE15[0]), 0, 0 },
+	{ "mmGB_TILE_MODE16", REG_MMIO, 0x2654, &mmGB_TILE_MODE16[0], sizeof(mmGB_TILE_MODE16)/sizeof(mmGB_TILE_MODE16[0]), 0, 0 },
+	{ "mmGB_TILE_MODE17", REG_MMIO, 0x2655, &mmGB_TILE_MODE17[0], sizeof(mmGB_TILE_MODE17)/sizeof(mmGB_TILE_MODE17[0]), 0, 0 },
+	{ "mmGB_TILE_MODE18", REG_MMIO, 0x2656, &mmGB_TILE_MODE18[0], sizeof(mmGB_TILE_MODE18)/sizeof(mmGB_TILE_MODE18[0]), 0, 0 },
+	{ "mmGB_TILE_MODE19", REG_MMIO, 0x2657, &mmGB_TILE_MODE19[0], sizeof(mmGB_TILE_MODE19)/sizeof(mmGB_TILE_MODE19[0]), 0, 0 },
+	{ "mmGB_TILE_MODE20", REG_MMIO, 0x2658, &mmGB_TILE_MODE20[0], sizeof(mmGB_TILE_MODE20)/sizeof(mmGB_TILE_MODE20[0]), 0, 0 },
+	{ "mmGB_TILE_MODE21", REG_MMIO, 0x2659, &mmGB_TILE_MODE21[0], sizeof(mmGB_TILE_MODE21)/sizeof(mmGB_TILE_MODE21[0]), 0, 0 },
+	{ "mmGB_TILE_MODE22", REG_MMIO, 0x265a, &mmGB_TILE_MODE22[0], sizeof(mmGB_TILE_MODE22)/sizeof(mmGB_TILE_MODE22[0]), 0, 0 },
+	{ "mmGB_TILE_MODE23", REG_MMIO, 0x265b, &mmGB_TILE_MODE23[0], sizeof(mmGB_TILE_MODE23)/sizeof(mmGB_TILE_MODE23[0]), 0, 0 },
+	{ "mmGB_TILE_MODE24", REG_MMIO, 0x265c, &mmGB_TILE_MODE24[0], sizeof(mmGB_TILE_MODE24)/sizeof(mmGB_TILE_MODE24[0]), 0, 0 },
+	{ "mmGB_TILE_MODE25", REG_MMIO, 0x265d, &mmGB_TILE_MODE25[0], sizeof(mmGB_TILE_MODE25)/sizeof(mmGB_TILE_MODE25[0]), 0, 0 },
+	{ "mmGB_TILE_MODE26", REG_MMIO, 0x265e, &mmGB_TILE_MODE26[0], sizeof(mmGB_TILE_MODE26)/sizeof(mmGB_TILE_MODE26[0]), 0, 0 },
+	{ "mmGB_TILE_MODE27", REG_MMIO, 0x265f, &mmGB_TILE_MODE27[0], sizeof(mmGB_TILE_MODE27)/sizeof(mmGB_TILE_MODE27[0]), 0, 0 },
+	{ "mmGB_TILE_MODE28", REG_MMIO, 0x2660, &mmGB_TILE_MODE28[0], sizeof(mmGB_TILE_MODE28)/sizeof(mmGB_TILE_MODE28[0]), 0, 0 },
+	{ "mmGB_TILE_MODE29", REG_MMIO, 0x2661, &mmGB_TILE_MODE29[0], sizeof(mmGB_TILE_MODE29)/sizeof(mmGB_TILE_MODE29[0]), 0, 0 },
+	{ "mmGB_TILE_MODE30", REG_MMIO, 0x2662, &mmGB_TILE_MODE30[0], sizeof(mmGB_TILE_MODE30)/sizeof(mmGB_TILE_MODE30[0]), 0, 0 },
+	{ "mmGB_TILE_MODE31", REG_MMIO, 0x2663, &mmGB_TILE_MODE31[0], sizeof(mmGB_TILE_MODE31)/sizeof(mmGB_TILE_MODE31[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE0", REG_MMIO, 0x2664, &mmGB_MACROTILE_MODE0[0], sizeof(mmGB_MACROTILE_MODE0)/sizeof(mmGB_MACROTILE_MODE0[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE1", REG_MMIO, 0x2665, &mmGB_MACROTILE_MODE1[0], sizeof(mmGB_MACROTILE_MODE1)/sizeof(mmGB_MACROTILE_MODE1[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE2", REG_MMIO, 0x2666, &mmGB_MACROTILE_MODE2[0], sizeof(mmGB_MACROTILE_MODE2)/sizeof(mmGB_MACROTILE_MODE2[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE3", REG_MMIO, 0x2667, &mmGB_MACROTILE_MODE3[0], sizeof(mmGB_MACROTILE_MODE3)/sizeof(mmGB_MACROTILE_MODE3[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE4", REG_MMIO, 0x2668, &mmGB_MACROTILE_MODE4[0], sizeof(mmGB_MACROTILE_MODE4)/sizeof(mmGB_MACROTILE_MODE4[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE5", REG_MMIO, 0x2669, &mmGB_MACROTILE_MODE5[0], sizeof(mmGB_MACROTILE_MODE5)/sizeof(mmGB_MACROTILE_MODE5[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE6", REG_MMIO, 0x266a, &mmGB_MACROTILE_MODE6[0], sizeof(mmGB_MACROTILE_MODE6)/sizeof(mmGB_MACROTILE_MODE6[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE7", REG_MMIO, 0x266b, &mmGB_MACROTILE_MODE7[0], sizeof(mmGB_MACROTILE_MODE7)/sizeof(mmGB_MACROTILE_MODE7[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE8", REG_MMIO, 0x266c, &mmGB_MACROTILE_MODE8[0], sizeof(mmGB_MACROTILE_MODE8)/sizeof(mmGB_MACROTILE_MODE8[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE9", REG_MMIO, 0x266d, &mmGB_MACROTILE_MODE9[0], sizeof(mmGB_MACROTILE_MODE9)/sizeof(mmGB_MACROTILE_MODE9[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE10", REG_MMIO, 0x266e, &mmGB_MACROTILE_MODE10[0], sizeof(mmGB_MACROTILE_MODE10)/sizeof(mmGB_MACROTILE_MODE10[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE11", REG_MMIO, 0x266f, &mmGB_MACROTILE_MODE11[0], sizeof(mmGB_MACROTILE_MODE11)/sizeof(mmGB_MACROTILE_MODE11[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE12", REG_MMIO, 0x2670, &mmGB_MACROTILE_MODE12[0], sizeof(mmGB_MACROTILE_MODE12)/sizeof(mmGB_MACROTILE_MODE12[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE13", REG_MMIO, 0x2671, &mmGB_MACROTILE_MODE13[0], sizeof(mmGB_MACROTILE_MODE13)/sizeof(mmGB_MACROTILE_MODE13[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE14", REG_MMIO, 0x2672, &mmGB_MACROTILE_MODE14[0], sizeof(mmGB_MACROTILE_MODE14)/sizeof(mmGB_MACROTILE_MODE14[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE15", REG_MMIO, 0x2673, &mmGB_MACROTILE_MODE15[0], sizeof(mmGB_MACROTILE_MODE15)/sizeof(mmGB_MACROTILE_MODE15[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_3", REG_MMIO, 0x2683, &mmCB_HW_CONTROL_3[0], sizeof(mmCB_HW_CONTROL_3)/sizeof(mmCB_HW_CONTROL_3[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL", REG_MMIO, 0x2684, &mmCB_HW_CONTROL[0], sizeof(mmCB_HW_CONTROL)/sizeof(mmCB_HW_CONTROL[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_1", REG_MMIO, 0x2685, &mmCB_HW_CONTROL_1[0], sizeof(mmCB_HW_CONTROL_1)/sizeof(mmCB_HW_CONTROL_1[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_2", REG_MMIO, 0x2686, &mmCB_HW_CONTROL_2[0], sizeof(mmCB_HW_CONTROL_2)/sizeof(mmCB_HW_CONTROL_2[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_1", REG_MMIO, 0x2699, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_2", REG_MMIO, 0x269a, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_3", REG_MMIO, 0x269b, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_4", REG_MMIO, 0x269c, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_5", REG_MMIO, 0x269d, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_6", REG_MMIO, 0x269e, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_7", REG_MMIO, 0x269f, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_8", REG_MMIO, 0x26a0, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_9", REG_MMIO, 0x26a1, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_10", REG_MMIO, 0x26a2, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_11", REG_MMIO, 0x26a3, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_12", REG_MMIO, 0x26a4, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_13", REG_MMIO, 0x26a5, &mmCB_DEBUG_BUS_13[0], sizeof(mmCB_DEBUG_BUS_13)/sizeof(mmCB_DEBUG_BUS_13[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_14", REG_MMIO, 0x26a6, &mmCB_DEBUG_BUS_14[0], sizeof(mmCB_DEBUG_BUS_14)/sizeof(mmCB_DEBUG_BUS_14[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_15", REG_MMIO, 0x26a7, &mmCB_DEBUG_BUS_15[0], sizeof(mmCB_DEBUG_BUS_15)/sizeof(mmCB_DEBUG_BUS_15[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_16", REG_MMIO, 0x26a8, &mmCB_DEBUG_BUS_16[0], sizeof(mmCB_DEBUG_BUS_16)/sizeof(mmCB_DEBUG_BUS_16[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_17", REG_MMIO, 0x26a9, &mmCB_DEBUG_BUS_17[0], sizeof(mmCB_DEBUG_BUS_17)/sizeof(mmCB_DEBUG_BUS_17[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_18", REG_MMIO, 0x26aa, &mmCB_DEBUG_BUS_18[0], sizeof(mmCB_DEBUG_BUS_18)/sizeof(mmCB_DEBUG_BUS_18[0]), 0, 0 },
+	{ "ixSQ_WAVE_TBA_LO", REG_SMC, 0x26c, &ixSQ_WAVE_TBA_LO[0], sizeof(ixSQ_WAVE_TBA_LO)/sizeof(ixSQ_WAVE_TBA_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_TBA_HI", REG_SMC, 0x26d, &ixSQ_WAVE_TBA_HI[0], sizeof(ixSQ_WAVE_TBA_HI)/sizeof(ixSQ_WAVE_TBA_HI[0]), 0, 0 },
+	{ "mmGC_USER_RB_REDUNDANCY", REG_MMIO, 0x26de, &mmGC_USER_RB_REDUNDANCY[0], sizeof(mmGC_USER_RB_REDUNDANCY)/sizeof(mmGC_USER_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmGC_USER_RB_BACKEND_DISABLE", REG_MMIO, 0x26df, &mmGC_USER_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "ixSQ_WAVE_TMA_LO", REG_SMC, 0x26e, &ixSQ_WAVE_TMA_LO[0], sizeof(ixSQ_WAVE_TMA_LO)/sizeof(ixSQ_WAVE_TMA_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_TMA_HI", REG_SMC, 0x26f, &ixSQ_WAVE_TMA_HI[0], sizeof(ixSQ_WAVE_TMA_HI)/sizeof(ixSQ_WAVE_TMA_HI[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG32", REG_SMC, 0x27, &ixVGT_DEBUG_REG32[0], sizeof(ixVGT_DEBUG_REG32)/sizeof(ixVGT_DEBUG_REG32[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP0", REG_SMC, 0x270, &ixSQ_WAVE_TTMP0[0], sizeof(ixSQ_WAVE_TTMP0)/sizeof(ixSQ_WAVE_TTMP0[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP1", REG_SMC, 0x271, &ixSQ_WAVE_TTMP1[0], sizeof(ixSQ_WAVE_TTMP1)/sizeof(ixSQ_WAVE_TTMP1[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP2", REG_SMC, 0x272, &ixSQ_WAVE_TTMP2[0], sizeof(ixSQ_WAVE_TTMP2)/sizeof(ixSQ_WAVE_TTMP2[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP3", REG_SMC, 0x273, &ixSQ_WAVE_TTMP3[0], sizeof(ixSQ_WAVE_TTMP3)/sizeof(ixSQ_WAVE_TTMP3[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP4", REG_SMC, 0x274, &ixSQ_WAVE_TTMP4[0], sizeof(ixSQ_WAVE_TTMP4)/sizeof(ixSQ_WAVE_TTMP4[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP5", REG_SMC, 0x275, &ixSQ_WAVE_TTMP5[0], sizeof(ixSQ_WAVE_TTMP5)/sizeof(ixSQ_WAVE_TTMP5[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP6", REG_SMC, 0x276, &ixSQ_WAVE_TTMP6[0], sizeof(ixSQ_WAVE_TTMP6)/sizeof(ixSQ_WAVE_TTMP6[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP7", REG_SMC, 0x277, &ixSQ_WAVE_TTMP7[0], sizeof(ixSQ_WAVE_TTMP7)/sizeof(ixSQ_WAVE_TTMP7[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP8", REG_SMC, 0x278, &ixSQ_WAVE_TTMP8[0], sizeof(ixSQ_WAVE_TTMP8)/sizeof(ixSQ_WAVE_TTMP8[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP9", REG_SMC, 0x279, &ixSQ_WAVE_TTMP9[0], sizeof(ixSQ_WAVE_TTMP9)/sizeof(ixSQ_WAVE_TTMP9[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP10", REG_SMC, 0x27a, &ixSQ_WAVE_TTMP10[0], sizeof(ixSQ_WAVE_TTMP10)/sizeof(ixSQ_WAVE_TTMP10[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP11", REG_SMC, 0x27b, &ixSQ_WAVE_TTMP11[0], sizeof(ixSQ_WAVE_TTMP11)/sizeof(ixSQ_WAVE_TTMP11[0]), 0, 0 },
+	{ "ixSQ_WAVE_M0", REG_SMC, 0x27c, &ixSQ_WAVE_M0[0], sizeof(ixSQ_WAVE_M0)/sizeof(ixSQ_WAVE_M0[0]), 0, 0 },
+	{ "ixSQ_WAVE_EXEC_LO", REG_SMC, 0x27e, &ixSQ_WAVE_EXEC_LO[0], sizeof(ixSQ_WAVE_EXEC_LO)/sizeof(ixSQ_WAVE_EXEC_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_EXEC_HI", REG_SMC, 0x27f, &ixSQ_WAVE_EXEC_HI[0], sizeof(ixSQ_WAVE_EXEC_HI)/sizeof(ixSQ_WAVE_EXEC_HI[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG33", REG_SMC, 0x28, &ixVGT_DEBUG_REG33[0], sizeof(ixVGT_DEBUG_REG33)/sizeof(ixVGT_DEBUG_REG33[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG34", REG_SMC, 0x29, &ixVGT_DEBUG_REG34[0], sizeof(ixVGT_DEBUG_REG34)/sizeof(ixVGT_DEBUG_REG34[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG35", REG_SMC, 0x2a, &ixVGT_DEBUG_REG35[0], sizeof(ixVGT_DEBUG_REG35)/sizeof(ixVGT_DEBUG_REG35[0]), 0, 0 },
+	{ "mmTCP_INVALIDATE", REG_MMIO, 0x2b00, &mmTCP_INVALIDATE[0], sizeof(mmTCP_INVALIDATE)/sizeof(mmTCP_INVALIDATE[0]), 0, 0 },
+	{ "mmTCP_STATUS", REG_MMIO, 0x2b01, &mmTCP_STATUS[0], sizeof(mmTCP_STATUS)/sizeof(mmTCP_STATUS[0]), 0, 0 },
+	{ "mmTCP_CNTL", REG_MMIO, 0x2b02, &mmTCP_CNTL[0], sizeof(mmTCP_CNTL)/sizeof(mmTCP_CNTL[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_LO", REG_MMIO, 0x2b03, &mmTCP_CHAN_STEER_LO[0], sizeof(mmTCP_CHAN_STEER_LO)/sizeof(mmTCP_CHAN_STEER_LO[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_HI", REG_MMIO, 0x2b04, &mmTCP_CHAN_STEER_HI[0], sizeof(mmTCP_CHAN_STEER_HI)/sizeof(mmTCP_CHAN_STEER_HI[0]), 0, 0 },
+	{ "mmTCP_ADDR_CONFIG", REG_MMIO, 0x2b05, &mmTCP_ADDR_CONFIG[0], sizeof(mmTCP_ADDR_CONFIG)/sizeof(mmTCP_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmTCP_CREDIT", REG_MMIO, 0x2b06, &mmTCP_CREDIT[0], sizeof(mmTCP_CREDIT)/sizeof(mmTCP_CREDIT[0]), 0, 0 },
+	{ "mmTCP_BUFFER_ADDR_HASH_CNTL", REG_MMIO, 0x2b16, &mmTCP_BUFFER_ADDR_HASH_CNTL[0], sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL)/sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL[0]), 0, 0 },
+	{ "mmTCP_EDC_COUNTER", REG_MMIO, 0x2b17, &mmTCP_EDC_COUNTER[0], sizeof(mmTCP_EDC_COUNTER)/sizeof(mmTCP_EDC_COUNTER[0]), 0, 0 },
+	{ "mmTC_CFG_L1_LOAD_POLICY0", REG_MMIO, 0x2b1a, &mmTC_CFG_L1_LOAD_POLICY0[0], sizeof(mmTC_CFG_L1_LOAD_POLICY0)/sizeof(mmTC_CFG_L1_LOAD_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L1_LOAD_POLICY1", REG_MMIO, 0x2b1b, &mmTC_CFG_L1_LOAD_POLICY1[0], sizeof(mmTC_CFG_L1_LOAD_POLICY1)/sizeof(mmTC_CFG_L1_LOAD_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L1_STORE_POLICY", REG_MMIO, 0x2b1c, &mmTC_CFG_L1_STORE_POLICY[0], sizeof(mmTC_CFG_L1_STORE_POLICY)/sizeof(mmTC_CFG_L1_STORE_POLICY[0]), 0, 0 },
+	{ "mmTC_CFG_L2_LOAD_POLICY0", REG_MMIO, 0x2b1d, &mmTC_CFG_L2_LOAD_POLICY0[0], sizeof(mmTC_CFG_L2_LOAD_POLICY0)/sizeof(mmTC_CFG_L2_LOAD_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L2_LOAD_POLICY1", REG_MMIO, 0x2b1e, &mmTC_CFG_L2_LOAD_POLICY1[0], sizeof(mmTC_CFG_L2_LOAD_POLICY1)/sizeof(mmTC_CFG_L2_LOAD_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L2_STORE_POLICY0", REG_MMIO, 0x2b1f, &mmTC_CFG_L2_STORE_POLICY0[0], sizeof(mmTC_CFG_L2_STORE_POLICY0)/sizeof(mmTC_CFG_L2_STORE_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L2_STORE_POLICY1", REG_MMIO, 0x2b20, &mmTC_CFG_L2_STORE_POLICY1[0], sizeof(mmTC_CFG_L2_STORE_POLICY1)/sizeof(mmTC_CFG_L2_STORE_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L2_ATOMIC_POLICY", REG_MMIO, 0x2b21, &mmTC_CFG_L2_ATOMIC_POLICY[0], sizeof(mmTC_CFG_L2_ATOMIC_POLICY)/sizeof(mmTC_CFG_L2_ATOMIC_POLICY[0]), 0, 0 },
+	{ "mmTC_CFG_L1_VOLATILE", REG_MMIO, 0x2b22, &mmTC_CFG_L1_VOLATILE[0], sizeof(mmTC_CFG_L1_VOLATILE)/sizeof(mmTC_CFG_L1_VOLATILE[0]), 0, 0 },
+	{ "mmTC_CFG_L2_VOLATILE", REG_MMIO, 0x2b23, &mmTC_CFG_L2_VOLATILE[0], sizeof(mmTC_CFG_L2_VOLATILE)/sizeof(mmTC_CFG_L2_VOLATILE[0]), 0, 0 },
+	{ "mmTCI_STATUS", REG_MMIO, 0x2b61, &mmTCI_STATUS[0], sizeof(mmTCI_STATUS)/sizeof(mmTCI_STATUS[0]), 0, 0 },
+	{ "mmTCI_CNTL_1", REG_MMIO, 0x2b62, &mmTCI_CNTL_1[0], sizeof(mmTCI_CNTL_1)/sizeof(mmTCI_CNTL_1[0]), 0, 0 },
+	{ "mmTCI_CNTL_2", REG_MMIO, 0x2b63, &mmTCI_CNTL_2[0], sizeof(mmTCI_CNTL_2)/sizeof(mmTCI_CNTL_2[0]), 0, 0 },
+	{ "mmTCC_CTRL", REG_MMIO, 0x2b80, &mmTCC_CTRL[0], sizeof(mmTCC_CTRL)/sizeof(mmTCC_CTRL[0]), 0, 0 },
+	{ "mmTCC_EDC_COUNTER", REG_MMIO, 0x2b82, &mmTCC_EDC_COUNTER[0], sizeof(mmTCC_EDC_COUNTER)/sizeof(mmTCC_EDC_COUNTER[0]), 0, 0 },
+	{ "mmTCC_REDUNDANCY", REG_MMIO, 0x2b83, &mmTCC_REDUNDANCY[0], sizeof(mmTCC_REDUNDANCY)/sizeof(mmTCC_REDUNDANCY[0]), 0, 0 },
+	{ "mmTCA_CTRL", REG_MMIO, 0x2bc0, &mmTCA_CTRL[0], sizeof(mmTCA_CTRL)/sizeof(mmTCA_CTRL[0]), 0, 0 },
+	{ "mmTCS_CTRL", REG_MMIO, 0x2be0, &mmTCS_CTRL[0], sizeof(mmTCS_CTRL)/sizeof(mmTCS_CTRL[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_PS", REG_MMIO, 0x2c00, &mmSPI_SHADER_TBA_LO_PS[0], sizeof(mmSPI_SHADER_TBA_LO_PS)/sizeof(mmSPI_SHADER_TBA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_PS", REG_MMIO, 0x2c01, &mmSPI_SHADER_TBA_HI_PS[0], sizeof(mmSPI_SHADER_TBA_HI_PS)/sizeof(mmSPI_SHADER_TBA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_PS", REG_MMIO, 0x2c02, &mmSPI_SHADER_TMA_LO_PS[0], sizeof(mmSPI_SHADER_TMA_LO_PS)/sizeof(mmSPI_SHADER_TMA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_PS", REG_MMIO, 0x2c03, &mmSPI_SHADER_TMA_HI_PS[0], sizeof(mmSPI_SHADER_TMA_HI_PS)/sizeof(mmSPI_SHADER_TMA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_PS", REG_MMIO, 0x2c07, &mmSPI_SHADER_PGM_RSRC3_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_PS)/sizeof(mmSPI_SHADER_PGM_RSRC3_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_PS", REG_MMIO, 0x2c08, &mmSPI_SHADER_PGM_LO_PS[0], sizeof(mmSPI_SHADER_PGM_LO_PS)/sizeof(mmSPI_SHADER_PGM_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_PS", REG_MMIO, 0x2c09, &mmSPI_SHADER_PGM_HI_PS[0], sizeof(mmSPI_SHADER_PGM_HI_PS)/sizeof(mmSPI_SHADER_PGM_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_PS", REG_MMIO, 0x2c0a, &mmSPI_SHADER_PGM_RSRC1_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_PS)/sizeof(mmSPI_SHADER_PGM_RSRC1_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_PS", REG_MMIO, 0x2c0b, &mmSPI_SHADER_PGM_RSRC2_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_PS)/sizeof(mmSPI_SHADER_PGM_RSRC2_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_0", REG_MMIO, 0x2c0c, &mmSPI_SHADER_USER_DATA_PS_0[0], sizeof(mmSPI_SHADER_USER_DATA_PS_0)/sizeof(mmSPI_SHADER_USER_DATA_PS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_1", REG_MMIO, 0x2c0d, &mmSPI_SHADER_USER_DATA_PS_1[0], sizeof(mmSPI_SHADER_USER_DATA_PS_1)/sizeof(mmSPI_SHADER_USER_DATA_PS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_2", REG_MMIO, 0x2c0e, &mmSPI_SHADER_USER_DATA_PS_2[0], sizeof(mmSPI_SHADER_USER_DATA_PS_2)/sizeof(mmSPI_SHADER_USER_DATA_PS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_3", REG_MMIO, 0x2c0f, &mmSPI_SHADER_USER_DATA_PS_3[0], sizeof(mmSPI_SHADER_USER_DATA_PS_3)/sizeof(mmSPI_SHADER_USER_DATA_PS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_4", REG_MMIO, 0x2c10, &mmSPI_SHADER_USER_DATA_PS_4[0], sizeof(mmSPI_SHADER_USER_DATA_PS_4)/sizeof(mmSPI_SHADER_USER_DATA_PS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_5", REG_MMIO, 0x2c11, &mmSPI_SHADER_USER_DATA_PS_5[0], sizeof(mmSPI_SHADER_USER_DATA_PS_5)/sizeof(mmSPI_SHADER_USER_DATA_PS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_6", REG_MMIO, 0x2c12, &mmSPI_SHADER_USER_DATA_PS_6[0], sizeof(mmSPI_SHADER_USER_DATA_PS_6)/sizeof(mmSPI_SHADER_USER_DATA_PS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_7", REG_MMIO, 0x2c13, &mmSPI_SHADER_USER_DATA_PS_7[0], sizeof(mmSPI_SHADER_USER_DATA_PS_7)/sizeof(mmSPI_SHADER_USER_DATA_PS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_8", REG_MMIO, 0x2c14, &mmSPI_SHADER_USER_DATA_PS_8[0], sizeof(mmSPI_SHADER_USER_DATA_PS_8)/sizeof(mmSPI_SHADER_USER_DATA_PS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_9", REG_MMIO, 0x2c15, &mmSPI_SHADER_USER_DATA_PS_9[0], sizeof(mmSPI_SHADER_USER_DATA_PS_9)/sizeof(mmSPI_SHADER_USER_DATA_PS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_10", REG_MMIO, 0x2c16, &mmSPI_SHADER_USER_DATA_PS_10[0], sizeof(mmSPI_SHADER_USER_DATA_PS_10)/sizeof(mmSPI_SHADER_USER_DATA_PS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_11", REG_MMIO, 0x2c17, &mmSPI_SHADER_USER_DATA_PS_11[0], sizeof(mmSPI_SHADER_USER_DATA_PS_11)/sizeof(mmSPI_SHADER_USER_DATA_PS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_12", REG_MMIO, 0x2c18, &mmSPI_SHADER_USER_DATA_PS_12[0], sizeof(mmSPI_SHADER_USER_DATA_PS_12)/sizeof(mmSPI_SHADER_USER_DATA_PS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_13", REG_MMIO, 0x2c19, &mmSPI_SHADER_USER_DATA_PS_13[0], sizeof(mmSPI_SHADER_USER_DATA_PS_13)/sizeof(mmSPI_SHADER_USER_DATA_PS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_14", REG_MMIO, 0x2c1a, &mmSPI_SHADER_USER_DATA_PS_14[0], sizeof(mmSPI_SHADER_USER_DATA_PS_14)/sizeof(mmSPI_SHADER_USER_DATA_PS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_15", REG_MMIO, 0x2c1b, &mmSPI_SHADER_USER_DATA_PS_15[0], sizeof(mmSPI_SHADER_USER_DATA_PS_15)/sizeof(mmSPI_SHADER_USER_DATA_PS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_VS", REG_MMIO, 0x2c40, &mmSPI_SHADER_TBA_LO_VS[0], sizeof(mmSPI_SHADER_TBA_LO_VS)/sizeof(mmSPI_SHADER_TBA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_VS", REG_MMIO, 0x2c41, &mmSPI_SHADER_TBA_HI_VS[0], sizeof(mmSPI_SHADER_TBA_HI_VS)/sizeof(mmSPI_SHADER_TBA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_VS", REG_MMIO, 0x2c42, &mmSPI_SHADER_TMA_LO_VS[0], sizeof(mmSPI_SHADER_TMA_LO_VS)/sizeof(mmSPI_SHADER_TMA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_VS", REG_MMIO, 0x2c43, &mmSPI_SHADER_TMA_HI_VS[0], sizeof(mmSPI_SHADER_TMA_HI_VS)/sizeof(mmSPI_SHADER_TMA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_VS", REG_MMIO, 0x2c46, &mmSPI_SHADER_PGM_RSRC3_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_VS)/sizeof(mmSPI_SHADER_PGM_RSRC3_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_LATE_ALLOC_VS", REG_MMIO, 0x2c47, &mmSPI_SHADER_LATE_ALLOC_VS[0], sizeof(mmSPI_SHADER_LATE_ALLOC_VS)/sizeof(mmSPI_SHADER_LATE_ALLOC_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_VS", REG_MMIO, 0x2c48, &mmSPI_SHADER_PGM_LO_VS[0], sizeof(mmSPI_SHADER_PGM_LO_VS)/sizeof(mmSPI_SHADER_PGM_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_VS", REG_MMIO, 0x2c49, &mmSPI_SHADER_PGM_HI_VS[0], sizeof(mmSPI_SHADER_PGM_HI_VS)/sizeof(mmSPI_SHADER_PGM_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_VS", REG_MMIO, 0x2c4a, &mmSPI_SHADER_PGM_RSRC1_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_VS)/sizeof(mmSPI_SHADER_PGM_RSRC1_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_VS", REG_MMIO, 0x2c4b, &mmSPI_SHADER_PGM_RSRC2_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_0", REG_MMIO, 0x2c4c, &mmSPI_SHADER_USER_DATA_VS_0[0], sizeof(mmSPI_SHADER_USER_DATA_VS_0)/sizeof(mmSPI_SHADER_USER_DATA_VS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_1", REG_MMIO, 0x2c4d, &mmSPI_SHADER_USER_DATA_VS_1[0], sizeof(mmSPI_SHADER_USER_DATA_VS_1)/sizeof(mmSPI_SHADER_USER_DATA_VS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_2", REG_MMIO, 0x2c4e, &mmSPI_SHADER_USER_DATA_VS_2[0], sizeof(mmSPI_SHADER_USER_DATA_VS_2)/sizeof(mmSPI_SHADER_USER_DATA_VS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_3", REG_MMIO, 0x2c4f, &mmSPI_SHADER_USER_DATA_VS_3[0], sizeof(mmSPI_SHADER_USER_DATA_VS_3)/sizeof(mmSPI_SHADER_USER_DATA_VS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_4", REG_MMIO, 0x2c50, &mmSPI_SHADER_USER_DATA_VS_4[0], sizeof(mmSPI_SHADER_USER_DATA_VS_4)/sizeof(mmSPI_SHADER_USER_DATA_VS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_5", REG_MMIO, 0x2c51, &mmSPI_SHADER_USER_DATA_VS_5[0], sizeof(mmSPI_SHADER_USER_DATA_VS_5)/sizeof(mmSPI_SHADER_USER_DATA_VS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_6", REG_MMIO, 0x2c52, &mmSPI_SHADER_USER_DATA_VS_6[0], sizeof(mmSPI_SHADER_USER_DATA_VS_6)/sizeof(mmSPI_SHADER_USER_DATA_VS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_7", REG_MMIO, 0x2c53, &mmSPI_SHADER_USER_DATA_VS_7[0], sizeof(mmSPI_SHADER_USER_DATA_VS_7)/sizeof(mmSPI_SHADER_USER_DATA_VS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_8", REG_MMIO, 0x2c54, &mmSPI_SHADER_USER_DATA_VS_8[0], sizeof(mmSPI_SHADER_USER_DATA_VS_8)/sizeof(mmSPI_SHADER_USER_DATA_VS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_9", REG_MMIO, 0x2c55, &mmSPI_SHADER_USER_DATA_VS_9[0], sizeof(mmSPI_SHADER_USER_DATA_VS_9)/sizeof(mmSPI_SHADER_USER_DATA_VS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_10", REG_MMIO, 0x2c56, &mmSPI_SHADER_USER_DATA_VS_10[0], sizeof(mmSPI_SHADER_USER_DATA_VS_10)/sizeof(mmSPI_SHADER_USER_DATA_VS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_11", REG_MMIO, 0x2c57, &mmSPI_SHADER_USER_DATA_VS_11[0], sizeof(mmSPI_SHADER_USER_DATA_VS_11)/sizeof(mmSPI_SHADER_USER_DATA_VS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_12", REG_MMIO, 0x2c58, &mmSPI_SHADER_USER_DATA_VS_12[0], sizeof(mmSPI_SHADER_USER_DATA_VS_12)/sizeof(mmSPI_SHADER_USER_DATA_VS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_13", REG_MMIO, 0x2c59, &mmSPI_SHADER_USER_DATA_VS_13[0], sizeof(mmSPI_SHADER_USER_DATA_VS_13)/sizeof(mmSPI_SHADER_USER_DATA_VS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_14", REG_MMIO, 0x2c5a, &mmSPI_SHADER_USER_DATA_VS_14[0], sizeof(mmSPI_SHADER_USER_DATA_VS_14)/sizeof(mmSPI_SHADER_USER_DATA_VS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_15", REG_MMIO, 0x2c5b, &mmSPI_SHADER_USER_DATA_VS_15[0], sizeof(mmSPI_SHADER_USER_DATA_VS_15)/sizeof(mmSPI_SHADER_USER_DATA_VS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES_VS", REG_MMIO, 0x2c7c, &mmSPI_SHADER_PGM_RSRC2_ES_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_VS", REG_MMIO, 0x2c7d, &mmSPI_SHADER_PGM_RSRC2_LS_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_GS", REG_MMIO, 0x2c80, &mmSPI_SHADER_TBA_LO_GS[0], sizeof(mmSPI_SHADER_TBA_LO_GS)/sizeof(mmSPI_SHADER_TBA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_GS", REG_MMIO, 0x2c81, &mmSPI_SHADER_TBA_HI_GS[0], sizeof(mmSPI_SHADER_TBA_HI_GS)/sizeof(mmSPI_SHADER_TBA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_GS", REG_MMIO, 0x2c82, &mmSPI_SHADER_TMA_LO_GS[0], sizeof(mmSPI_SHADER_TMA_LO_GS)/sizeof(mmSPI_SHADER_TMA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_GS", REG_MMIO, 0x2c83, &mmSPI_SHADER_TMA_HI_GS[0], sizeof(mmSPI_SHADER_TMA_HI_GS)/sizeof(mmSPI_SHADER_TMA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_GS", REG_MMIO, 0x2c87, &mmSPI_SHADER_PGM_RSRC3_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_GS)/sizeof(mmSPI_SHADER_PGM_RSRC3_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_GS", REG_MMIO, 0x2c88, &mmSPI_SHADER_PGM_LO_GS[0], sizeof(mmSPI_SHADER_PGM_LO_GS)/sizeof(mmSPI_SHADER_PGM_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_GS", REG_MMIO, 0x2c89, &mmSPI_SHADER_PGM_HI_GS[0], sizeof(mmSPI_SHADER_PGM_HI_GS)/sizeof(mmSPI_SHADER_PGM_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_GS", REG_MMIO, 0x2c8a, &mmSPI_SHADER_PGM_RSRC1_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_GS)/sizeof(mmSPI_SHADER_PGM_RSRC1_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_GS", REG_MMIO, 0x2c8b, &mmSPI_SHADER_PGM_RSRC2_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_0", REG_MMIO, 0x2c8c, &mmSPI_SHADER_USER_DATA_GS_0[0], sizeof(mmSPI_SHADER_USER_DATA_GS_0)/sizeof(mmSPI_SHADER_USER_DATA_GS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_1", REG_MMIO, 0x2c8d, &mmSPI_SHADER_USER_DATA_GS_1[0], sizeof(mmSPI_SHADER_USER_DATA_GS_1)/sizeof(mmSPI_SHADER_USER_DATA_GS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_2", REG_MMIO, 0x2c8e, &mmSPI_SHADER_USER_DATA_GS_2[0], sizeof(mmSPI_SHADER_USER_DATA_GS_2)/sizeof(mmSPI_SHADER_USER_DATA_GS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_3", REG_MMIO, 0x2c8f, &mmSPI_SHADER_USER_DATA_GS_3[0], sizeof(mmSPI_SHADER_USER_DATA_GS_3)/sizeof(mmSPI_SHADER_USER_DATA_GS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_4", REG_MMIO, 0x2c90, &mmSPI_SHADER_USER_DATA_GS_4[0], sizeof(mmSPI_SHADER_USER_DATA_GS_4)/sizeof(mmSPI_SHADER_USER_DATA_GS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_5", REG_MMIO, 0x2c91, &mmSPI_SHADER_USER_DATA_GS_5[0], sizeof(mmSPI_SHADER_USER_DATA_GS_5)/sizeof(mmSPI_SHADER_USER_DATA_GS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_6", REG_MMIO, 0x2c92, &mmSPI_SHADER_USER_DATA_GS_6[0], sizeof(mmSPI_SHADER_USER_DATA_GS_6)/sizeof(mmSPI_SHADER_USER_DATA_GS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_7", REG_MMIO, 0x2c93, &mmSPI_SHADER_USER_DATA_GS_7[0], sizeof(mmSPI_SHADER_USER_DATA_GS_7)/sizeof(mmSPI_SHADER_USER_DATA_GS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_8", REG_MMIO, 0x2c94, &mmSPI_SHADER_USER_DATA_GS_8[0], sizeof(mmSPI_SHADER_USER_DATA_GS_8)/sizeof(mmSPI_SHADER_USER_DATA_GS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_9", REG_MMIO, 0x2c95, &mmSPI_SHADER_USER_DATA_GS_9[0], sizeof(mmSPI_SHADER_USER_DATA_GS_9)/sizeof(mmSPI_SHADER_USER_DATA_GS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_10", REG_MMIO, 0x2c96, &mmSPI_SHADER_USER_DATA_GS_10[0], sizeof(mmSPI_SHADER_USER_DATA_GS_10)/sizeof(mmSPI_SHADER_USER_DATA_GS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_11", REG_MMIO, 0x2c97, &mmSPI_SHADER_USER_DATA_GS_11[0], sizeof(mmSPI_SHADER_USER_DATA_GS_11)/sizeof(mmSPI_SHADER_USER_DATA_GS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_12", REG_MMIO, 0x2c98, &mmSPI_SHADER_USER_DATA_GS_12[0], sizeof(mmSPI_SHADER_USER_DATA_GS_12)/sizeof(mmSPI_SHADER_USER_DATA_GS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_13", REG_MMIO, 0x2c99, &mmSPI_SHADER_USER_DATA_GS_13[0], sizeof(mmSPI_SHADER_USER_DATA_GS_13)/sizeof(mmSPI_SHADER_USER_DATA_GS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_14", REG_MMIO, 0x2c9a, &mmSPI_SHADER_USER_DATA_GS_14[0], sizeof(mmSPI_SHADER_USER_DATA_GS_14)/sizeof(mmSPI_SHADER_USER_DATA_GS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_15", REG_MMIO, 0x2c9b, &mmSPI_SHADER_USER_DATA_GS_15[0], sizeof(mmSPI_SHADER_USER_DATA_GS_15)/sizeof(mmSPI_SHADER_USER_DATA_GS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES_GS", REG_MMIO, 0x2cbc, &mmSPI_SHADER_PGM_RSRC2_ES_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_ES", REG_MMIO, 0x2cc0, &mmSPI_SHADER_TBA_LO_ES[0], sizeof(mmSPI_SHADER_TBA_LO_ES)/sizeof(mmSPI_SHADER_TBA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_ES", REG_MMIO, 0x2cc1, &mmSPI_SHADER_TBA_HI_ES[0], sizeof(mmSPI_SHADER_TBA_HI_ES)/sizeof(mmSPI_SHADER_TBA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_ES", REG_MMIO, 0x2cc2, &mmSPI_SHADER_TMA_LO_ES[0], sizeof(mmSPI_SHADER_TMA_LO_ES)/sizeof(mmSPI_SHADER_TMA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_ES", REG_MMIO, 0x2cc3, &mmSPI_SHADER_TMA_HI_ES[0], sizeof(mmSPI_SHADER_TMA_HI_ES)/sizeof(mmSPI_SHADER_TMA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_ES", REG_MMIO, 0x2cc7, &mmSPI_SHADER_PGM_RSRC3_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC3_ES)/sizeof(mmSPI_SHADER_PGM_RSRC3_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_ES", REG_MMIO, 0x2cc8, &mmSPI_SHADER_PGM_LO_ES[0], sizeof(mmSPI_SHADER_PGM_LO_ES)/sizeof(mmSPI_SHADER_PGM_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_ES", REG_MMIO, 0x2cc9, &mmSPI_SHADER_PGM_HI_ES[0], sizeof(mmSPI_SHADER_PGM_HI_ES)/sizeof(mmSPI_SHADER_PGM_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_ES", REG_MMIO, 0x2cca, &mmSPI_SHADER_PGM_RSRC1_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC1_ES)/sizeof(mmSPI_SHADER_PGM_RSRC1_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES", REG_MMIO, 0x2ccb, &mmSPI_SHADER_PGM_RSRC2_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_0", REG_MMIO, 0x2ccc, &mmSPI_SHADER_USER_DATA_ES_0[0], sizeof(mmSPI_SHADER_USER_DATA_ES_0)/sizeof(mmSPI_SHADER_USER_DATA_ES_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_1", REG_MMIO, 0x2ccd, &mmSPI_SHADER_USER_DATA_ES_1[0], sizeof(mmSPI_SHADER_USER_DATA_ES_1)/sizeof(mmSPI_SHADER_USER_DATA_ES_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_2", REG_MMIO, 0x2cce, &mmSPI_SHADER_USER_DATA_ES_2[0], sizeof(mmSPI_SHADER_USER_DATA_ES_2)/sizeof(mmSPI_SHADER_USER_DATA_ES_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_3", REG_MMIO, 0x2ccf, &mmSPI_SHADER_USER_DATA_ES_3[0], sizeof(mmSPI_SHADER_USER_DATA_ES_3)/sizeof(mmSPI_SHADER_USER_DATA_ES_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_4", REG_MMIO, 0x2cd0, &mmSPI_SHADER_USER_DATA_ES_4[0], sizeof(mmSPI_SHADER_USER_DATA_ES_4)/sizeof(mmSPI_SHADER_USER_DATA_ES_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_5", REG_MMIO, 0x2cd1, &mmSPI_SHADER_USER_DATA_ES_5[0], sizeof(mmSPI_SHADER_USER_DATA_ES_5)/sizeof(mmSPI_SHADER_USER_DATA_ES_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_6", REG_MMIO, 0x2cd2, &mmSPI_SHADER_USER_DATA_ES_6[0], sizeof(mmSPI_SHADER_USER_DATA_ES_6)/sizeof(mmSPI_SHADER_USER_DATA_ES_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_7", REG_MMIO, 0x2cd3, &mmSPI_SHADER_USER_DATA_ES_7[0], sizeof(mmSPI_SHADER_USER_DATA_ES_7)/sizeof(mmSPI_SHADER_USER_DATA_ES_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_8", REG_MMIO, 0x2cd4, &mmSPI_SHADER_USER_DATA_ES_8[0], sizeof(mmSPI_SHADER_USER_DATA_ES_8)/sizeof(mmSPI_SHADER_USER_DATA_ES_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_9", REG_MMIO, 0x2cd5, &mmSPI_SHADER_USER_DATA_ES_9[0], sizeof(mmSPI_SHADER_USER_DATA_ES_9)/sizeof(mmSPI_SHADER_USER_DATA_ES_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_10", REG_MMIO, 0x2cd6, &mmSPI_SHADER_USER_DATA_ES_10[0], sizeof(mmSPI_SHADER_USER_DATA_ES_10)/sizeof(mmSPI_SHADER_USER_DATA_ES_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_11", REG_MMIO, 0x2cd7, &mmSPI_SHADER_USER_DATA_ES_11[0], sizeof(mmSPI_SHADER_USER_DATA_ES_11)/sizeof(mmSPI_SHADER_USER_DATA_ES_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_12", REG_MMIO, 0x2cd8, &mmSPI_SHADER_USER_DATA_ES_12[0], sizeof(mmSPI_SHADER_USER_DATA_ES_12)/sizeof(mmSPI_SHADER_USER_DATA_ES_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_13", REG_MMIO, 0x2cd9, &mmSPI_SHADER_USER_DATA_ES_13[0], sizeof(mmSPI_SHADER_USER_DATA_ES_13)/sizeof(mmSPI_SHADER_USER_DATA_ES_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_14", REG_MMIO, 0x2cda, &mmSPI_SHADER_USER_DATA_ES_14[0], sizeof(mmSPI_SHADER_USER_DATA_ES_14)/sizeof(mmSPI_SHADER_USER_DATA_ES_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_15", REG_MMIO, 0x2cdb, &mmSPI_SHADER_USER_DATA_ES_15[0], sizeof(mmSPI_SHADER_USER_DATA_ES_15)/sizeof(mmSPI_SHADER_USER_DATA_ES_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_ES", REG_MMIO, 0x2cfd, &mmSPI_SHADER_PGM_RSRC2_LS_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_HS", REG_MMIO, 0x2d00, &mmSPI_SHADER_TBA_LO_HS[0], sizeof(mmSPI_SHADER_TBA_LO_HS)/sizeof(mmSPI_SHADER_TBA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_HS", REG_MMIO, 0x2d01, &mmSPI_SHADER_TBA_HI_HS[0], sizeof(mmSPI_SHADER_TBA_HI_HS)/sizeof(mmSPI_SHADER_TBA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_HS", REG_MMIO, 0x2d02, &mmSPI_SHADER_TMA_LO_HS[0], sizeof(mmSPI_SHADER_TMA_LO_HS)/sizeof(mmSPI_SHADER_TMA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_HS", REG_MMIO, 0x2d03, &mmSPI_SHADER_TMA_HI_HS[0], sizeof(mmSPI_SHADER_TMA_HI_HS)/sizeof(mmSPI_SHADER_TMA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_HS", REG_MMIO, 0x2d07, &mmSPI_SHADER_PGM_RSRC3_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_HS)/sizeof(mmSPI_SHADER_PGM_RSRC3_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_HS", REG_MMIO, 0x2d08, &mmSPI_SHADER_PGM_LO_HS[0], sizeof(mmSPI_SHADER_PGM_LO_HS)/sizeof(mmSPI_SHADER_PGM_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_HS", REG_MMIO, 0x2d09, &mmSPI_SHADER_PGM_HI_HS[0], sizeof(mmSPI_SHADER_PGM_HI_HS)/sizeof(mmSPI_SHADER_PGM_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_HS", REG_MMIO, 0x2d0a, &mmSPI_SHADER_PGM_RSRC1_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_HS)/sizeof(mmSPI_SHADER_PGM_RSRC1_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_HS", REG_MMIO, 0x2d0b, &mmSPI_SHADER_PGM_RSRC2_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_0", REG_MMIO, 0x2d0c, &mmSPI_SHADER_USER_DATA_HS_0[0], sizeof(mmSPI_SHADER_USER_DATA_HS_0)/sizeof(mmSPI_SHADER_USER_DATA_HS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_1", REG_MMIO, 0x2d0d, &mmSPI_SHADER_USER_DATA_HS_1[0], sizeof(mmSPI_SHADER_USER_DATA_HS_1)/sizeof(mmSPI_SHADER_USER_DATA_HS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_2", REG_MMIO, 0x2d0e, &mmSPI_SHADER_USER_DATA_HS_2[0], sizeof(mmSPI_SHADER_USER_DATA_HS_2)/sizeof(mmSPI_SHADER_USER_DATA_HS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_3", REG_MMIO, 0x2d0f, &mmSPI_SHADER_USER_DATA_HS_3[0], sizeof(mmSPI_SHADER_USER_DATA_HS_3)/sizeof(mmSPI_SHADER_USER_DATA_HS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_4", REG_MMIO, 0x2d10, &mmSPI_SHADER_USER_DATA_HS_4[0], sizeof(mmSPI_SHADER_USER_DATA_HS_4)/sizeof(mmSPI_SHADER_USER_DATA_HS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_5", REG_MMIO, 0x2d11, &mmSPI_SHADER_USER_DATA_HS_5[0], sizeof(mmSPI_SHADER_USER_DATA_HS_5)/sizeof(mmSPI_SHADER_USER_DATA_HS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_6", REG_MMIO, 0x2d12, &mmSPI_SHADER_USER_DATA_HS_6[0], sizeof(mmSPI_SHADER_USER_DATA_HS_6)/sizeof(mmSPI_SHADER_USER_DATA_HS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_7", REG_MMIO, 0x2d13, &mmSPI_SHADER_USER_DATA_HS_7[0], sizeof(mmSPI_SHADER_USER_DATA_HS_7)/sizeof(mmSPI_SHADER_USER_DATA_HS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_8", REG_MMIO, 0x2d14, &mmSPI_SHADER_USER_DATA_HS_8[0], sizeof(mmSPI_SHADER_USER_DATA_HS_8)/sizeof(mmSPI_SHADER_USER_DATA_HS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_9", REG_MMIO, 0x2d15, &mmSPI_SHADER_USER_DATA_HS_9[0], sizeof(mmSPI_SHADER_USER_DATA_HS_9)/sizeof(mmSPI_SHADER_USER_DATA_HS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_10", REG_MMIO, 0x2d16, &mmSPI_SHADER_USER_DATA_HS_10[0], sizeof(mmSPI_SHADER_USER_DATA_HS_10)/sizeof(mmSPI_SHADER_USER_DATA_HS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_11", REG_MMIO, 0x2d17, &mmSPI_SHADER_USER_DATA_HS_11[0], sizeof(mmSPI_SHADER_USER_DATA_HS_11)/sizeof(mmSPI_SHADER_USER_DATA_HS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_12", REG_MMIO, 0x2d18, &mmSPI_SHADER_USER_DATA_HS_12[0], sizeof(mmSPI_SHADER_USER_DATA_HS_12)/sizeof(mmSPI_SHADER_USER_DATA_HS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_13", REG_MMIO, 0x2d19, &mmSPI_SHADER_USER_DATA_HS_13[0], sizeof(mmSPI_SHADER_USER_DATA_HS_13)/sizeof(mmSPI_SHADER_USER_DATA_HS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_14", REG_MMIO, 0x2d1a, &mmSPI_SHADER_USER_DATA_HS_14[0], sizeof(mmSPI_SHADER_USER_DATA_HS_14)/sizeof(mmSPI_SHADER_USER_DATA_HS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_15", REG_MMIO, 0x2d1b, &mmSPI_SHADER_USER_DATA_HS_15[0], sizeof(mmSPI_SHADER_USER_DATA_HS_15)/sizeof(mmSPI_SHADER_USER_DATA_HS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_HS", REG_MMIO, 0x2d3d, &mmSPI_SHADER_PGM_RSRC2_LS_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_LS", REG_MMIO, 0x2d40, &mmSPI_SHADER_TBA_LO_LS[0], sizeof(mmSPI_SHADER_TBA_LO_LS)/sizeof(mmSPI_SHADER_TBA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_LS", REG_MMIO, 0x2d41, &mmSPI_SHADER_TBA_HI_LS[0], sizeof(mmSPI_SHADER_TBA_HI_LS)/sizeof(mmSPI_SHADER_TBA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_LS", REG_MMIO, 0x2d42, &mmSPI_SHADER_TMA_LO_LS[0], sizeof(mmSPI_SHADER_TMA_LO_LS)/sizeof(mmSPI_SHADER_TMA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_LS", REG_MMIO, 0x2d43, &mmSPI_SHADER_TMA_HI_LS[0], sizeof(mmSPI_SHADER_TMA_HI_LS)/sizeof(mmSPI_SHADER_TMA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_LS", REG_MMIO, 0x2d47, &mmSPI_SHADER_PGM_RSRC3_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_LS)/sizeof(mmSPI_SHADER_PGM_RSRC3_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_LS", REG_MMIO, 0x2d48, &mmSPI_SHADER_PGM_LO_LS[0], sizeof(mmSPI_SHADER_PGM_LO_LS)/sizeof(mmSPI_SHADER_PGM_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_LS", REG_MMIO, 0x2d49, &mmSPI_SHADER_PGM_HI_LS[0], sizeof(mmSPI_SHADER_PGM_HI_LS)/sizeof(mmSPI_SHADER_PGM_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_LS", REG_MMIO, 0x2d4a, &mmSPI_SHADER_PGM_RSRC1_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_LS)/sizeof(mmSPI_SHADER_PGM_RSRC1_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS", REG_MMIO, 0x2d4b, &mmSPI_SHADER_PGM_RSRC2_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_0", REG_MMIO, 0x2d4c, &mmSPI_SHADER_USER_DATA_LS_0[0], sizeof(mmSPI_SHADER_USER_DATA_LS_0)/sizeof(mmSPI_SHADER_USER_DATA_LS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_1", REG_MMIO, 0x2d4d, &mmSPI_SHADER_USER_DATA_LS_1[0], sizeof(mmSPI_SHADER_USER_DATA_LS_1)/sizeof(mmSPI_SHADER_USER_DATA_LS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_2", REG_MMIO, 0x2d4e, &mmSPI_SHADER_USER_DATA_LS_2[0], sizeof(mmSPI_SHADER_USER_DATA_LS_2)/sizeof(mmSPI_SHADER_USER_DATA_LS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_3", REG_MMIO, 0x2d4f, &mmSPI_SHADER_USER_DATA_LS_3[0], sizeof(mmSPI_SHADER_USER_DATA_LS_3)/sizeof(mmSPI_SHADER_USER_DATA_LS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_4", REG_MMIO, 0x2d50, &mmSPI_SHADER_USER_DATA_LS_4[0], sizeof(mmSPI_SHADER_USER_DATA_LS_4)/sizeof(mmSPI_SHADER_USER_DATA_LS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_5", REG_MMIO, 0x2d51, &mmSPI_SHADER_USER_DATA_LS_5[0], sizeof(mmSPI_SHADER_USER_DATA_LS_5)/sizeof(mmSPI_SHADER_USER_DATA_LS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_6", REG_MMIO, 0x2d52, &mmSPI_SHADER_USER_DATA_LS_6[0], sizeof(mmSPI_SHADER_USER_DATA_LS_6)/sizeof(mmSPI_SHADER_USER_DATA_LS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_7", REG_MMIO, 0x2d53, &mmSPI_SHADER_USER_DATA_LS_7[0], sizeof(mmSPI_SHADER_USER_DATA_LS_7)/sizeof(mmSPI_SHADER_USER_DATA_LS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_8", REG_MMIO, 0x2d54, &mmSPI_SHADER_USER_DATA_LS_8[0], sizeof(mmSPI_SHADER_USER_DATA_LS_8)/sizeof(mmSPI_SHADER_USER_DATA_LS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_9", REG_MMIO, 0x2d55, &mmSPI_SHADER_USER_DATA_LS_9[0], sizeof(mmSPI_SHADER_USER_DATA_LS_9)/sizeof(mmSPI_SHADER_USER_DATA_LS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_10", REG_MMIO, 0x2d56, &mmSPI_SHADER_USER_DATA_LS_10[0], sizeof(mmSPI_SHADER_USER_DATA_LS_10)/sizeof(mmSPI_SHADER_USER_DATA_LS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_11", REG_MMIO, 0x2d57, &mmSPI_SHADER_USER_DATA_LS_11[0], sizeof(mmSPI_SHADER_USER_DATA_LS_11)/sizeof(mmSPI_SHADER_USER_DATA_LS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_12", REG_MMIO, 0x2d58, &mmSPI_SHADER_USER_DATA_LS_12[0], sizeof(mmSPI_SHADER_USER_DATA_LS_12)/sizeof(mmSPI_SHADER_USER_DATA_LS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_13", REG_MMIO, 0x2d59, &mmSPI_SHADER_USER_DATA_LS_13[0], sizeof(mmSPI_SHADER_USER_DATA_LS_13)/sizeof(mmSPI_SHADER_USER_DATA_LS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_14", REG_MMIO, 0x2d5a, &mmSPI_SHADER_USER_DATA_LS_14[0], sizeof(mmSPI_SHADER_USER_DATA_LS_14)/sizeof(mmSPI_SHADER_USER_DATA_LS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_15", REG_MMIO, 0x2d5b, &mmSPI_SHADER_USER_DATA_LS_15[0], sizeof(mmSPI_SHADER_USER_DATA_LS_15)/sizeof(mmSPI_SHADER_USER_DATA_LS_15[0]), 0, 0 },
+	{ "mmCOMPUTE_DISPATCH_INITIATOR", REG_MMIO, 0x2e00, &mmCOMPUTE_DISPATCH_INITIATOR[0], sizeof(mmCOMPUTE_DISPATCH_INITIATOR)/sizeof(mmCOMPUTE_DISPATCH_INITIATOR[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_X", REG_MMIO, 0x2e01, &mmCOMPUTE_DIM_X[0], sizeof(mmCOMPUTE_DIM_X)/sizeof(mmCOMPUTE_DIM_X[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Y", REG_MMIO, 0x2e02, &mmCOMPUTE_DIM_Y[0], sizeof(mmCOMPUTE_DIM_Y)/sizeof(mmCOMPUTE_DIM_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Z", REG_MMIO, 0x2e03, &mmCOMPUTE_DIM_Z[0], sizeof(mmCOMPUTE_DIM_Z)/sizeof(mmCOMPUTE_DIM_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_START_X", REG_MMIO, 0x2e04, &mmCOMPUTE_START_X[0], sizeof(mmCOMPUTE_START_X)/sizeof(mmCOMPUTE_START_X[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Y", REG_MMIO, 0x2e05, &mmCOMPUTE_START_Y[0], sizeof(mmCOMPUTE_START_Y)/sizeof(mmCOMPUTE_START_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Z", REG_MMIO, 0x2e06, &mmCOMPUTE_START_Z[0], sizeof(mmCOMPUTE_START_Z)/sizeof(mmCOMPUTE_START_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_X", REG_MMIO, 0x2e07, &mmCOMPUTE_NUM_THREAD_X[0], sizeof(mmCOMPUTE_NUM_THREAD_X)/sizeof(mmCOMPUTE_NUM_THREAD_X[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Y", REG_MMIO, 0x2e08, &mmCOMPUTE_NUM_THREAD_Y[0], sizeof(mmCOMPUTE_NUM_THREAD_Y)/sizeof(mmCOMPUTE_NUM_THREAD_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Z", REG_MMIO, 0x2e09, &mmCOMPUTE_NUM_THREAD_Z[0], sizeof(mmCOMPUTE_NUM_THREAD_Z)/sizeof(mmCOMPUTE_NUM_THREAD_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_PIPELINESTAT_ENABLE", REG_MMIO, 0x2e0a, &mmCOMPUTE_PIPELINESTAT_ENABLE[0], sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE)/sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_PERFCOUNT_ENABLE", REG_MMIO, 0x2e0b, &mmCOMPUTE_PERFCOUNT_ENABLE[0], sizeof(mmCOMPUTE_PERFCOUNT_ENABLE)/sizeof(mmCOMPUTE_PERFCOUNT_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_LO", REG_MMIO, 0x2e0c, &mmCOMPUTE_PGM_LO[0], sizeof(mmCOMPUTE_PGM_LO)/sizeof(mmCOMPUTE_PGM_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_HI", REG_MMIO, 0x2e0d, &mmCOMPUTE_PGM_HI[0], sizeof(mmCOMPUTE_PGM_HI)/sizeof(mmCOMPUTE_PGM_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_LO", REG_MMIO, 0x2e0e, &mmCOMPUTE_TBA_LO[0], sizeof(mmCOMPUTE_TBA_LO)/sizeof(mmCOMPUTE_TBA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_HI", REG_MMIO, 0x2e0f, &mmCOMPUTE_TBA_HI[0], sizeof(mmCOMPUTE_TBA_HI)/sizeof(mmCOMPUTE_TBA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_LO", REG_MMIO, 0x2e10, &mmCOMPUTE_TMA_LO[0], sizeof(mmCOMPUTE_TMA_LO)/sizeof(mmCOMPUTE_TMA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_HI", REG_MMIO, 0x2e11, &mmCOMPUTE_TMA_HI[0], sizeof(mmCOMPUTE_TMA_HI)/sizeof(mmCOMPUTE_TMA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC1", REG_MMIO, 0x2e12, &mmCOMPUTE_PGM_RSRC1[0], sizeof(mmCOMPUTE_PGM_RSRC1)/sizeof(mmCOMPUTE_PGM_RSRC1[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC2", REG_MMIO, 0x2e13, &mmCOMPUTE_PGM_RSRC2[0], sizeof(mmCOMPUTE_PGM_RSRC2)/sizeof(mmCOMPUTE_PGM_RSRC2[0]), 0, 0 },
+	{ "mmCOMPUTE_VMID", REG_MMIO, 0x2e14, &mmCOMPUTE_VMID[0], sizeof(mmCOMPUTE_VMID)/sizeof(mmCOMPUTE_VMID[0]), 0, 0 },
+	{ "mmCOMPUTE_RESOURCE_LIMITS", REG_MMIO, 0x2e15, &mmCOMPUTE_RESOURCE_LIMITS[0], sizeof(mmCOMPUTE_RESOURCE_LIMITS)/sizeof(mmCOMPUTE_RESOURCE_LIMITS[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE0", REG_MMIO, 0x2e16, &mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE1", REG_MMIO, 0x2e17, &mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0]), 0, 0 },
+	{ "mmCOMPUTE_TMPRING_SIZE", REG_MMIO, 0x2e18, &mmCOMPUTE_TMPRING_SIZE[0], sizeof(mmCOMPUTE_TMPRING_SIZE)/sizeof(mmCOMPUTE_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE2", REG_MMIO, 0x2e19, &mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE3", REG_MMIO, 0x2e1a, &mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_X", REG_MMIO, 0x2e1b, &mmCOMPUTE_RESTART_X[0], sizeof(mmCOMPUTE_RESTART_X)/sizeof(mmCOMPUTE_RESTART_X[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_Y", REG_MMIO, 0x2e1c, &mmCOMPUTE_RESTART_Y[0], sizeof(mmCOMPUTE_RESTART_Y)/sizeof(mmCOMPUTE_RESTART_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_Z", REG_MMIO, 0x2e1d, &mmCOMPUTE_RESTART_Z[0], sizeof(mmCOMPUTE_RESTART_Z)/sizeof(mmCOMPUTE_RESTART_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_THREAD_TRACE_ENABLE", REG_MMIO, 0x2e1e, &mmCOMPUTE_THREAD_TRACE_ENABLE[0], sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE)/sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_MISC_RESERVED", REG_MMIO, 0x2e1f, &mmCOMPUTE_MISC_RESERVED[0], sizeof(mmCOMPUTE_MISC_RESERVED)/sizeof(mmCOMPUTE_MISC_RESERVED[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_0", REG_MMIO, 0x2e40, &mmCOMPUTE_USER_DATA_0[0], sizeof(mmCOMPUTE_USER_DATA_0)/sizeof(mmCOMPUTE_USER_DATA_0[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_1", REG_MMIO, 0x2e41, &mmCOMPUTE_USER_DATA_1[0], sizeof(mmCOMPUTE_USER_DATA_1)/sizeof(mmCOMPUTE_USER_DATA_1[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_2", REG_MMIO, 0x2e42, &mmCOMPUTE_USER_DATA_2[0], sizeof(mmCOMPUTE_USER_DATA_2)/sizeof(mmCOMPUTE_USER_DATA_2[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_3", REG_MMIO, 0x2e43, &mmCOMPUTE_USER_DATA_3[0], sizeof(mmCOMPUTE_USER_DATA_3)/sizeof(mmCOMPUTE_USER_DATA_3[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_4", REG_MMIO, 0x2e44, &mmCOMPUTE_USER_DATA_4[0], sizeof(mmCOMPUTE_USER_DATA_4)/sizeof(mmCOMPUTE_USER_DATA_4[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_5", REG_MMIO, 0x2e45, &mmCOMPUTE_USER_DATA_5[0], sizeof(mmCOMPUTE_USER_DATA_5)/sizeof(mmCOMPUTE_USER_DATA_5[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_6", REG_MMIO, 0x2e46, &mmCOMPUTE_USER_DATA_6[0], sizeof(mmCOMPUTE_USER_DATA_6)/sizeof(mmCOMPUTE_USER_DATA_6[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_7", REG_MMIO, 0x2e47, &mmCOMPUTE_USER_DATA_7[0], sizeof(mmCOMPUTE_USER_DATA_7)/sizeof(mmCOMPUTE_USER_DATA_7[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_8", REG_MMIO, 0x2e48, &mmCOMPUTE_USER_DATA_8[0], sizeof(mmCOMPUTE_USER_DATA_8)/sizeof(mmCOMPUTE_USER_DATA_8[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_9", REG_MMIO, 0x2e49, &mmCOMPUTE_USER_DATA_9[0], sizeof(mmCOMPUTE_USER_DATA_9)/sizeof(mmCOMPUTE_USER_DATA_9[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_10", REG_MMIO, 0x2e4a, &mmCOMPUTE_USER_DATA_10[0], sizeof(mmCOMPUTE_USER_DATA_10)/sizeof(mmCOMPUTE_USER_DATA_10[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_11", REG_MMIO, 0x2e4b, &mmCOMPUTE_USER_DATA_11[0], sizeof(mmCOMPUTE_USER_DATA_11)/sizeof(mmCOMPUTE_USER_DATA_11[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_12", REG_MMIO, 0x2e4c, &mmCOMPUTE_USER_DATA_12[0], sizeof(mmCOMPUTE_USER_DATA_12)/sizeof(mmCOMPUTE_USER_DATA_12[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_13", REG_MMIO, 0x2e4d, &mmCOMPUTE_USER_DATA_13[0], sizeof(mmCOMPUTE_USER_DATA_13)/sizeof(mmCOMPUTE_USER_DATA_13[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_14", REG_MMIO, 0x2e4e, &mmCOMPUTE_USER_DATA_14[0], sizeof(mmCOMPUTE_USER_DATA_14)/sizeof(mmCOMPUTE_USER_DATA_14[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_15", REG_MMIO, 0x2e4f, &mmCOMPUTE_USER_DATA_15[0], sizeof(mmCOMPUTE_USER_DATA_15)/sizeof(mmCOMPUTE_USER_DATA_15[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG03", REG_SMC, 0x3, &ixCLIPPER_DEBUG_REG03[0], sizeof(ixCLIPPER_DEBUG_REG03)/sizeof(ixCLIPPER_DEBUG_REG03[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG3", REG_SMC, 0x3, &ixGDS_DEBUG_REG3[0], sizeof(ixGDS_DEBUG_REG3)/sizeof(ixGDS_DEBUG_REG3[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG3", REG_SMC, 0x3, &ixWD_DEBUG_REG3[0], sizeof(ixWD_DEBUG_REG3)/sizeof(ixWD_DEBUG_REG3[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT0_3", REG_SMC, 0x30, &ixDIDT_DB_WEIGHT0_3[0], sizeof(ixDIDT_DB_WEIGHT0_3)/sizeof(ixDIDT_DB_WEIGHT0_3[0]), 0, 0 },
+	{ "mmGRBM_CAM_INDEX", REG_MMIO, 0x3000, &mmGRBM_CAM_INDEX[0], sizeof(mmGRBM_CAM_INDEX)/sizeof(mmGRBM_CAM_INDEX[0]), 0, 0 },
+	{ "mmGRBM_CAM_DATA", REG_MMIO, 0x3001, &mmGRBM_CAM_DATA[0], sizeof(mmGRBM_CAM_DATA)/sizeof(mmGRBM_CAM_DATA[0]), 0, 0 },
+	{ "mmCP_DFY_CNTL", REG_MMIO, 0x3020, &mmCP_DFY_CNTL[0], sizeof(mmCP_DFY_CNTL)/sizeof(mmCP_DFY_CNTL[0]), 0, 0 },
+	{ "mmCP_DFY_STAT", REG_MMIO, 0x3021, &mmCP_DFY_STAT[0], sizeof(mmCP_DFY_STAT)/sizeof(mmCP_DFY_STAT[0]), 0, 0 },
+	{ "mmCP_DFY_ADDR_HI", REG_MMIO, 0x3022, &mmCP_DFY_ADDR_HI[0], sizeof(mmCP_DFY_ADDR_HI)/sizeof(mmCP_DFY_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DFY_ADDR_LO", REG_MMIO, 0x3023, &mmCP_DFY_ADDR_LO[0], sizeof(mmCP_DFY_ADDR_LO)/sizeof(mmCP_DFY_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_0", REG_MMIO, 0x3024, &mmCP_DFY_DATA_0[0], sizeof(mmCP_DFY_DATA_0)/sizeof(mmCP_DFY_DATA_0[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_1", REG_MMIO, 0x3025, &mmCP_DFY_DATA_1[0], sizeof(mmCP_DFY_DATA_1)/sizeof(mmCP_DFY_DATA_1[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_2", REG_MMIO, 0x3026, &mmCP_DFY_DATA_2[0], sizeof(mmCP_DFY_DATA_2)/sizeof(mmCP_DFY_DATA_2[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_3", REG_MMIO, 0x3027, &mmCP_DFY_DATA_3[0], sizeof(mmCP_DFY_DATA_3)/sizeof(mmCP_DFY_DATA_3[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_4", REG_MMIO, 0x3028, &mmCP_DFY_DATA_4[0], sizeof(mmCP_DFY_DATA_4)/sizeof(mmCP_DFY_DATA_4[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_5", REG_MMIO, 0x3029, &mmCP_DFY_DATA_5[0], sizeof(mmCP_DFY_DATA_5)/sizeof(mmCP_DFY_DATA_5[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_6", REG_MMIO, 0x302a, &mmCP_DFY_DATA_6[0], sizeof(mmCP_DFY_DATA_6)/sizeof(mmCP_DFY_DATA_6[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_7", REG_MMIO, 0x302b, &mmCP_DFY_DATA_7[0], sizeof(mmCP_DFY_DATA_7)/sizeof(mmCP_DFY_DATA_7[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_8", REG_MMIO, 0x302c, &mmCP_DFY_DATA_8[0], sizeof(mmCP_DFY_DATA_8)/sizeof(mmCP_DFY_DATA_8[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_9", REG_MMIO, 0x302d, &mmCP_DFY_DATA_9[0], sizeof(mmCP_DFY_DATA_9)/sizeof(mmCP_DFY_DATA_9[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_10", REG_MMIO, 0x302e, &mmCP_DFY_DATA_10[0], sizeof(mmCP_DFY_DATA_10)/sizeof(mmCP_DFY_DATA_10[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_11", REG_MMIO, 0x302f, &mmCP_DFY_DATA_11[0], sizeof(mmCP_DFY_DATA_11)/sizeof(mmCP_DFY_DATA_11[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_12", REG_MMIO, 0x3030, &mmCP_DFY_DATA_12[0], sizeof(mmCP_DFY_DATA_12)/sizeof(mmCP_DFY_DATA_12[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_13", REG_MMIO, 0x3031, &mmCP_DFY_DATA_13[0], sizeof(mmCP_DFY_DATA_13)/sizeof(mmCP_DFY_DATA_13[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_14", REG_MMIO, 0x3032, &mmCP_DFY_DATA_14[0], sizeof(mmCP_DFY_DATA_14)/sizeof(mmCP_DFY_DATA_14[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_15", REG_MMIO, 0x3033, &mmCP_DFY_DATA_15[0], sizeof(mmCP_DFY_DATA_15)/sizeof(mmCP_DFY_DATA_15[0]), 0, 0 },
+	{ "mmCP_RB0_BASE", REG_MMIO, 0x3040, &mmCP_RB0_BASE[0], sizeof(mmCP_RB0_BASE)/sizeof(mmCP_RB0_BASE[0]), 0, 0 },
+	{ "mmCP_RB_BASE", REG_MMIO, 0x3040, &mmCP_RB_BASE[0], sizeof(mmCP_RB_BASE)/sizeof(mmCP_RB_BASE[0]), 0, 0 },
+	{ "mmCP_RB0_CNTL", REG_MMIO, 0x3041, &mmCP_RB0_CNTL[0], sizeof(mmCP_RB0_CNTL)/sizeof(mmCP_RB0_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_CNTL", REG_MMIO, 0x3041, &mmCP_RB_CNTL[0], sizeof(mmCP_RB_CNTL)/sizeof(mmCP_RB_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_WR", REG_MMIO, 0x3042, &mmCP_RB_RPTR_WR[0], sizeof(mmCP_RB_RPTR_WR)/sizeof(mmCP_RB_RPTR_WR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB0_RPTR_ADDR[0], sizeof(mmCP_RB0_RPTR_ADDR)/sizeof(mmCP_RB0_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB_RPTR_ADDR[0], sizeof(mmCP_RB_RPTR_ADDR)/sizeof(mmCP_RB_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB0_RPTR_ADDR_HI[0], sizeof(mmCP_RB0_RPTR_ADDR_HI)/sizeof(mmCP_RB0_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB_RPTR_ADDR_HI[0], sizeof(mmCP_RB_RPTR_ADDR_HI)/sizeof(mmCP_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB0_WPTR", REG_MMIO, 0x3045, &mmCP_RB0_WPTR[0], sizeof(mmCP_RB0_WPTR)/sizeof(mmCP_RB0_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR", REG_MMIO, 0x3045, &mmCP_RB_WPTR[0], sizeof(mmCP_RB_WPTR)/sizeof(mmCP_RB_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3046, &mmCP_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_LO)/sizeof(mmCP_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3047, &mmCP_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_HI)/sizeof(mmCP_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmGC_PRIV_MODE", REG_MMIO, 0x3048, NULL, 0, 0, 0 },
+	{ "mmCP_INT_CNTL", REG_MMIO, 0x3049, &mmCP_INT_CNTL[0], sizeof(mmCP_INT_CNTL)/sizeof(mmCP_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_INT_STATUS", REG_MMIO, 0x304a, &mmCP_INT_STATUS[0], sizeof(mmCP_INT_STATUS)/sizeof(mmCP_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_DEVICE_ID", REG_MMIO, 0x304b, &mmCP_DEVICE_ID[0], sizeof(mmCP_DEVICE_ID)/sizeof(mmCP_DEVICE_ID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE_PRIORITY_CNTS", REG_MMIO, 0x304c, &mmCP_ME0_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_RING_PRIORITY_CNTS", REG_MMIO, 0x304c, &mmCP_RING_PRIORITY_CNTS[0], sizeof(mmCP_RING_PRIORITY_CNTS)/sizeof(mmCP_RING_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE0_PRIORITY", REG_MMIO, 0x304d, &mmCP_ME0_PIPE0_PRIORITY[0], sizeof(mmCP_ME0_PIPE0_PRIORITY)/sizeof(mmCP_ME0_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING0_PRIORITY", REG_MMIO, 0x304d, &mmCP_RING0_PRIORITY[0], sizeof(mmCP_RING0_PRIORITY)/sizeof(mmCP_RING0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE1_PRIORITY", REG_MMIO, 0x304e, &mmCP_ME0_PIPE1_PRIORITY[0], sizeof(mmCP_ME0_PIPE1_PRIORITY)/sizeof(mmCP_ME0_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING1_PRIORITY", REG_MMIO, 0x304e, &mmCP_RING1_PRIORITY[0], sizeof(mmCP_RING1_PRIORITY)/sizeof(mmCP_RING1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE2_PRIORITY", REG_MMIO, 0x304f, &mmCP_ME0_PIPE2_PRIORITY[0], sizeof(mmCP_ME0_PIPE2_PRIORITY)/sizeof(mmCP_ME0_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING2_PRIORITY", REG_MMIO, 0x304f, &mmCP_RING2_PRIORITY[0], sizeof(mmCP_RING2_PRIORITY)/sizeof(mmCP_RING2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ENDIAN_SWAP", REG_MMIO, 0x3050, &mmCP_ENDIAN_SWAP[0], sizeof(mmCP_ENDIAN_SWAP)/sizeof(mmCP_ENDIAN_SWAP[0]), 0, 0 },
+	{ "mmCP_RB_VMID", REG_MMIO, 0x3051, &mmCP_RB_VMID[0], sizeof(mmCP_RB_VMID)/sizeof(mmCP_RB_VMID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE0_VMID", REG_MMIO, 0x3052, &mmCP_ME0_PIPE0_VMID[0], sizeof(mmCP_ME0_PIPE0_VMID)/sizeof(mmCP_ME0_PIPE0_VMID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE1_VMID", REG_MMIO, 0x3053, &mmCP_ME0_PIPE1_VMID[0], sizeof(mmCP_ME0_PIPE1_VMID)/sizeof(mmCP_ME0_PIPE1_VMID[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_ADDR", REG_MMIO, 0x3054, &mmCP_PFP_UCODE_ADDR[0], sizeof(mmCP_PFP_UCODE_ADDR)/sizeof(mmCP_PFP_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_DATA", REG_MMIO, 0x3055, &mmCP_PFP_UCODE_DATA[0], sizeof(mmCP_PFP_UCODE_DATA)/sizeof(mmCP_PFP_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_ME_RAM_RADDR", REG_MMIO, 0x3056, &mmCP_ME_RAM_RADDR[0], sizeof(mmCP_ME_RAM_RADDR)/sizeof(mmCP_ME_RAM_RADDR[0]), 0, 0 },
+	{ "mmCP_ME_RAM_WADDR", REG_MMIO, 0x3057, &mmCP_ME_RAM_WADDR[0], sizeof(mmCP_ME_RAM_WADDR)/sizeof(mmCP_ME_RAM_WADDR[0]), 0, 0 },
+	{ "mmCP_ME_RAM_DATA", REG_MMIO, 0x3058, &mmCP_ME_RAM_DATA[0], sizeof(mmCP_ME_RAM_DATA)/sizeof(mmCP_ME_RAM_DATA[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_ADDR", REG_MMIO, 0x305a, &mmCP_CE_UCODE_ADDR[0], sizeof(mmCP_CE_UCODE_ADDR)/sizeof(mmCP_CE_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_DATA", REG_MMIO, 0x305b, &mmCP_CE_UCODE_DATA[0], sizeof(mmCP_CE_UCODE_DATA)/sizeof(mmCP_CE_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_UCODE_ADDR", REG_MMIO, 0x305c, &mmCP_MEC_ME1_UCODE_ADDR[0], sizeof(mmCP_MEC_ME1_UCODE_ADDR)/sizeof(mmCP_MEC_ME1_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_UCODE_DATA", REG_MMIO, 0x305d, &mmCP_MEC_ME1_UCODE_DATA[0], sizeof(mmCP_MEC_ME1_UCODE_DATA)/sizeof(mmCP_MEC_ME1_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_UCODE_ADDR", REG_MMIO, 0x305e, &mmCP_MEC_ME2_UCODE_ADDR[0], sizeof(mmCP_MEC_ME2_UCODE_ADDR)/sizeof(mmCP_MEC_ME2_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_UCODE_DATA", REG_MMIO, 0x305f, &mmCP_MEC_ME2_UCODE_DATA[0], sizeof(mmCP_MEC_ME2_UCODE_DATA)/sizeof(mmCP_MEC_ME2_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_RB1_BASE", REG_MMIO, 0x3060, &mmCP_RB1_BASE[0], sizeof(mmCP_RB1_BASE)/sizeof(mmCP_RB1_BASE[0]), 0, 0 },
+	{ "mmCP_RB1_CNTL", REG_MMIO, 0x3061, &mmCP_RB1_CNTL[0], sizeof(mmCP_RB1_CNTL)/sizeof(mmCP_RB1_CNTL[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR", REG_MMIO, 0x3062, &mmCP_RB1_RPTR_ADDR[0], sizeof(mmCP_RB1_RPTR_ADDR)/sizeof(mmCP_RB1_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR_HI", REG_MMIO, 0x3063, &mmCP_RB1_RPTR_ADDR_HI[0], sizeof(mmCP_RB1_RPTR_ADDR_HI)/sizeof(mmCP_RB1_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB1_WPTR", REG_MMIO, 0x3064, &mmCP_RB1_WPTR[0], sizeof(mmCP_RB1_WPTR)/sizeof(mmCP_RB1_WPTR[0]), 0, 0 },
+	{ "mmCP_RB2_BASE", REG_MMIO, 0x3065, &mmCP_RB2_BASE[0], sizeof(mmCP_RB2_BASE)/sizeof(mmCP_RB2_BASE[0]), 0, 0 },
+	{ "mmCP_RB2_CNTL", REG_MMIO, 0x3066, &mmCP_RB2_CNTL[0], sizeof(mmCP_RB2_CNTL)/sizeof(mmCP_RB2_CNTL[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR", REG_MMIO, 0x3067, &mmCP_RB2_RPTR_ADDR[0], sizeof(mmCP_RB2_RPTR_ADDR)/sizeof(mmCP_RB2_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR_HI", REG_MMIO, 0x3068, &mmCP_RB2_RPTR_ADDR_HI[0], sizeof(mmCP_RB2_RPTR_ADDR_HI)/sizeof(mmCP_RB2_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB2_WPTR", REG_MMIO, 0x3069, &mmCP_RB2_WPTR[0], sizeof(mmCP_RB2_WPTR)/sizeof(mmCP_RB2_WPTR[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING0", REG_MMIO, 0x306a, &mmCP_INT_CNTL_RING0[0], sizeof(mmCP_INT_CNTL_RING0)/sizeof(mmCP_INT_CNTL_RING0[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING1", REG_MMIO, 0x306b, &mmCP_INT_CNTL_RING1[0], sizeof(mmCP_INT_CNTL_RING1)/sizeof(mmCP_INT_CNTL_RING1[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING2", REG_MMIO, 0x306c, &mmCP_INT_CNTL_RING2[0], sizeof(mmCP_INT_CNTL_RING2)/sizeof(mmCP_INT_CNTL_RING2[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING0", REG_MMIO, 0x306d, &mmCP_INT_STATUS_RING0[0], sizeof(mmCP_INT_STATUS_RING0)/sizeof(mmCP_INT_STATUS_RING0[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING1", REG_MMIO, 0x306e, &mmCP_INT_STATUS_RING1[0], sizeof(mmCP_INT_STATUS_RING1)/sizeof(mmCP_INT_STATUS_RING1[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING2", REG_MMIO, 0x306f, &mmCP_INT_STATUS_RING2[0], sizeof(mmCP_INT_STATUS_RING2)/sizeof(mmCP_INT_STATUS_RING2[0]), 0, 0 },
+	{ "mmCP_PWR_CNTL", REG_MMIO, 0x3078, &mmCP_PWR_CNTL[0], sizeof(mmCP_PWR_CNTL)/sizeof(mmCP_PWR_CNTL[0]), 0, 0 },
+	{ "mmCP_MEM_SLP_CNTL", REG_MMIO, 0x3079, &mmCP_MEM_SLP_CNTL[0], sizeof(mmCP_MEM_SLP_CNTL)/sizeof(mmCP_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE", REG_MMIO, 0x307a, &mmCP_ECC_FIRSTOCCURRENCE[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE)/sizeof(mmCP_ECC_FIRSTOCCURRENCE[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING0", REG_MMIO, 0x307b, &mmCP_ECC_FIRSTOCCURRENCE_RING0[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING1", REG_MMIO, 0x307c, &mmCP_ECC_FIRSTOCCURRENCE_RING1[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING2", REG_MMIO, 0x307d, &mmCP_ECC_FIRSTOCCURRENCE_RING2[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2[0]), 0, 0 },
+	{ "mmGB_EDC_MODE", REG_MMIO, 0x307e, &mmGB_EDC_MODE[0], sizeof(mmGB_EDC_MODE)/sizeof(mmGB_EDC_MODE[0]), 0, 0 },
+	{ "mmCP_CPF_DEBUG", REG_MMIO, 0x3080, NULL, 0, 0, 0 },
+	{ "mmCP_FETCHER_SOURCE", REG_MMIO, 0x3082, &mmCP_FETCHER_SOURCE[0], sizeof(mmCP_FETCHER_SOURCE)/sizeof(mmCP_FETCHER_SOURCE[0]), 0, 0 },
+	{ "mmCP_PQ_WPTR_POLL_CNTL", REG_MMIO, 0x3083, &mmCP_PQ_WPTR_POLL_CNTL[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL)/sizeof(mmCP_PQ_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_PQ_WPTR_POLL_CNTL1", REG_MMIO, 0x3084, &mmCP_PQ_WPTR_POLL_CNTL1[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL1)/sizeof(mmCP_PQ_WPTR_POLL_CNTL1[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_INT_CNTL", REG_MMIO, 0x3085, &mmCP_ME1_PIPE0_INT_CNTL[0], sizeof(mmCP_ME1_PIPE0_INT_CNTL)/sizeof(mmCP_ME1_PIPE0_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_INT_CNTL", REG_MMIO, 0x3086, &mmCP_ME1_PIPE1_INT_CNTL[0], sizeof(mmCP_ME1_PIPE1_INT_CNTL)/sizeof(mmCP_ME1_PIPE1_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_INT_CNTL", REG_MMIO, 0x3087, &mmCP_ME1_PIPE2_INT_CNTL[0], sizeof(mmCP_ME1_PIPE2_INT_CNTL)/sizeof(mmCP_ME1_PIPE2_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_INT_CNTL", REG_MMIO, 0x3088, &mmCP_ME1_PIPE3_INT_CNTL[0], sizeof(mmCP_ME1_PIPE3_INT_CNTL)/sizeof(mmCP_ME1_PIPE3_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_INT_CNTL", REG_MMIO, 0x3089, &mmCP_ME2_PIPE0_INT_CNTL[0], sizeof(mmCP_ME2_PIPE0_INT_CNTL)/sizeof(mmCP_ME2_PIPE0_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_INT_CNTL", REG_MMIO, 0x308a, &mmCP_ME2_PIPE1_INT_CNTL[0], sizeof(mmCP_ME2_PIPE1_INT_CNTL)/sizeof(mmCP_ME2_PIPE1_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_INT_CNTL", REG_MMIO, 0x308b, &mmCP_ME2_PIPE2_INT_CNTL[0], sizeof(mmCP_ME2_PIPE2_INT_CNTL)/sizeof(mmCP_ME2_PIPE2_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_INT_CNTL", REG_MMIO, 0x308c, &mmCP_ME2_PIPE3_INT_CNTL[0], sizeof(mmCP_ME2_PIPE3_INT_CNTL)/sizeof(mmCP_ME2_PIPE3_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_INT_STATUS", REG_MMIO, 0x308d, &mmCP_ME1_PIPE0_INT_STATUS[0], sizeof(mmCP_ME1_PIPE0_INT_STATUS)/sizeof(mmCP_ME1_PIPE0_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_INT_STATUS", REG_MMIO, 0x308e, &mmCP_ME1_PIPE1_INT_STATUS[0], sizeof(mmCP_ME1_PIPE1_INT_STATUS)/sizeof(mmCP_ME1_PIPE1_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_INT_STATUS", REG_MMIO, 0x308f, &mmCP_ME1_PIPE2_INT_STATUS[0], sizeof(mmCP_ME1_PIPE2_INT_STATUS)/sizeof(mmCP_ME1_PIPE2_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_INT_STATUS", REG_MMIO, 0x3090, &mmCP_ME1_PIPE3_INT_STATUS[0], sizeof(mmCP_ME1_PIPE3_INT_STATUS)/sizeof(mmCP_ME1_PIPE3_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_INT_STATUS", REG_MMIO, 0x3091, &mmCP_ME2_PIPE0_INT_STATUS[0], sizeof(mmCP_ME2_PIPE0_INT_STATUS)/sizeof(mmCP_ME2_PIPE0_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_INT_STATUS", REG_MMIO, 0x3092, &mmCP_ME2_PIPE1_INT_STATUS[0], sizeof(mmCP_ME2_PIPE1_INT_STATUS)/sizeof(mmCP_ME2_PIPE1_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_INT_STATUS", REG_MMIO, 0x3093, &mmCP_ME2_PIPE2_INT_STATUS[0], sizeof(mmCP_ME2_PIPE2_INT_STATUS)/sizeof(mmCP_ME2_PIPE2_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_INT_STATUS", REG_MMIO, 0x3094, &mmCP_ME2_PIPE3_INT_STATUS[0], sizeof(mmCP_ME2_PIPE3_INT_STATUS)/sizeof(mmCP_ME2_PIPE3_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_INT_STAT_DEBUG", REG_MMIO, 0x3095, &mmCP_ME1_INT_STAT_DEBUG[0], sizeof(mmCP_ME1_INT_STAT_DEBUG)/sizeof(mmCP_ME1_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCP_ME2_INT_STAT_DEBUG", REG_MMIO, 0x3096, &mmCP_ME2_INT_STAT_DEBUG[0], sizeof(mmCP_ME2_INT_STAT_DEBUG)/sizeof(mmCP_ME2_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCC_GC_EDC_CONFIG", REG_MMIO, 0x3098, &mmCC_GC_EDC_CONFIG[0], sizeof(mmCC_GC_EDC_CONFIG)/sizeof(mmCC_GC_EDC_CONFIG[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE_PRIORITY_CNTS", REG_MMIO, 0x3099, &mmCP_ME1_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_PRIORITY", REG_MMIO, 0x309a, &mmCP_ME1_PIPE0_PRIORITY[0], sizeof(mmCP_ME1_PIPE0_PRIORITY)/sizeof(mmCP_ME1_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_PRIORITY", REG_MMIO, 0x309b, &mmCP_ME1_PIPE1_PRIORITY[0], sizeof(mmCP_ME1_PIPE1_PRIORITY)/sizeof(mmCP_ME1_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_PRIORITY", REG_MMIO, 0x309c, &mmCP_ME1_PIPE2_PRIORITY[0], sizeof(mmCP_ME1_PIPE2_PRIORITY)/sizeof(mmCP_ME1_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_PRIORITY", REG_MMIO, 0x309d, &mmCP_ME1_PIPE3_PRIORITY[0], sizeof(mmCP_ME1_PIPE3_PRIORITY)/sizeof(mmCP_ME1_PIPE3_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE_PRIORITY_CNTS", REG_MMIO, 0x309e, &mmCP_ME2_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_PRIORITY", REG_MMIO, 0x309f, &mmCP_ME2_PIPE0_PRIORITY[0], sizeof(mmCP_ME2_PIPE0_PRIORITY)/sizeof(mmCP_ME2_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_PRIORITY", REG_MMIO, 0x30a0, &mmCP_ME2_PIPE1_PRIORITY[0], sizeof(mmCP_ME2_PIPE1_PRIORITY)/sizeof(mmCP_ME2_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_PRIORITY", REG_MMIO, 0x30a1, &mmCP_ME2_PIPE2_PRIORITY[0], sizeof(mmCP_ME2_PIPE2_PRIORITY)/sizeof(mmCP_ME2_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_PRIORITY", REG_MMIO, 0x30a2, &mmCP_ME2_PIPE3_PRIORITY[0], sizeof(mmCP_ME2_PIPE3_PRIORITY)/sizeof(mmCP_ME2_PIPE3_PRIORITY[0]), 0, 0 },
+	{ "mmCP_CE_PRGRM_CNTR_START", REG_MMIO, 0x30a3, &mmCP_CE_PRGRM_CNTR_START[0], sizeof(mmCP_CE_PRGRM_CNTR_START)/sizeof(mmCP_CE_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_PFP_PRGRM_CNTR_START", REG_MMIO, 0x30a4, &mmCP_PFP_PRGRM_CNTR_START[0], sizeof(mmCP_PFP_PRGRM_CNTR_START)/sizeof(mmCP_PFP_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_ME_PRGRM_CNTR_START", REG_MMIO, 0x30a5, &mmCP_ME_PRGRM_CNTR_START[0], sizeof(mmCP_ME_PRGRM_CNTR_START)/sizeof(mmCP_ME_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_MEC1_PRGRM_CNTR_START", REG_MMIO, 0x30a6, &mmCP_MEC1_PRGRM_CNTR_START[0], sizeof(mmCP_MEC1_PRGRM_CNTR_START)/sizeof(mmCP_MEC1_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_MEC2_PRGRM_CNTR_START", REG_MMIO, 0x30a7, &mmCP_MEC2_PRGRM_CNTR_START[0], sizeof(mmCP_MEC2_PRGRM_CNTR_START)/sizeof(mmCP_MEC2_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_CE_INTR_ROUTINE_START", REG_MMIO, 0x30a8, &mmCP_CE_INTR_ROUTINE_START[0], sizeof(mmCP_CE_INTR_ROUTINE_START)/sizeof(mmCP_CE_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_PFP_INTR_ROUTINE_START", REG_MMIO, 0x30a9, &mmCP_PFP_INTR_ROUTINE_START[0], sizeof(mmCP_PFP_INTR_ROUTINE_START)/sizeof(mmCP_PFP_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_ME_INTR_ROUTINE_START", REG_MMIO, 0x30aa, &mmCP_ME_INTR_ROUTINE_START[0], sizeof(mmCP_ME_INTR_ROUTINE_START)/sizeof(mmCP_ME_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_MEC1_INTR_ROUTINE_START", REG_MMIO, 0x30ab, &mmCP_MEC1_INTR_ROUTINE_START[0], sizeof(mmCP_MEC1_INTR_ROUTINE_START)/sizeof(mmCP_MEC1_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_MEC2_INTR_ROUTINE_START", REG_MMIO, 0x30ac, &mmCP_MEC2_INTR_ROUTINE_START[0], sizeof(mmCP_MEC2_INTR_ROUTINE_START)/sizeof(mmCP_MEC2_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_CONTEXT_CNTL", REG_MMIO, 0x30ad, &mmCP_CONTEXT_CNTL[0], sizeof(mmCP_CONTEXT_CNTL)/sizeof(mmCP_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmCP_MAX_CONTEXT", REG_MMIO, 0x30ae, &mmCP_MAX_CONTEXT[0], sizeof(mmCP_MAX_CONTEXT)/sizeof(mmCP_MAX_CONTEXT[0]), 0, 0 },
+	{ "mmCP_IQ_WAIT_TIME1", REG_MMIO, 0x30af, &mmCP_IQ_WAIT_TIME1[0], sizeof(mmCP_IQ_WAIT_TIME1)/sizeof(mmCP_IQ_WAIT_TIME1[0]), 0, 0 },
+	{ "mmCP_IQ_WAIT_TIME2", REG_MMIO, 0x30b0, &mmCP_IQ_WAIT_TIME2[0], sizeof(mmCP_IQ_WAIT_TIME2)/sizeof(mmCP_IQ_WAIT_TIME2[0]), 0, 0 },
+	{ "mmCP_RB0_BASE_HI", REG_MMIO, 0x30b1, &mmCP_RB0_BASE_HI[0], sizeof(mmCP_RB0_BASE_HI)/sizeof(mmCP_RB0_BASE_HI[0]), 0, 0 },
+	{ "mmCP_RB1_BASE_HI", REG_MMIO, 0x30b2, &mmCP_RB1_BASE_HI[0], sizeof(mmCP_RB1_BASE_HI)/sizeof(mmCP_RB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_VMID_RESET", REG_MMIO, 0x30b3, &mmCP_VMID_RESET[0], sizeof(mmCP_VMID_RESET)/sizeof(mmCP_VMID_RESET[0]), 0, 0 },
+	{ "mmCPC_INT_CNTL", REG_MMIO, 0x30b4, &mmCPC_INT_CNTL[0], sizeof(mmCPC_INT_CNTL)/sizeof(mmCPC_INT_CNTL[0]), 0, 0 },
+	{ "mmCPC_INT_STATUS", REG_MMIO, 0x30b5, &mmCPC_INT_STATUS[0], sizeof(mmCPC_INT_STATUS)/sizeof(mmCPC_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_VMID_PREEMPT", REG_MMIO, 0x30b6, &mmCP_VMID_PREEMPT[0], sizeof(mmCP_VMID_PREEMPT)/sizeof(mmCP_VMID_PREEMPT[0]), 0, 0 },
+	{ "mmCPC_INT_CNTX_ID", REG_MMIO, 0x30b7, &mmCPC_INT_CNTX_ID[0], sizeof(mmCPC_INT_CNTX_ID)/sizeof(mmCPC_INT_CNTX_ID[0]), 0, 0 },
+	{ "mmCP_PQ_STATUS", REG_MMIO, 0x30b8, &mmCP_PQ_STATUS[0], sizeof(mmCP_PQ_STATUS)/sizeof(mmCP_PQ_STATUS[0]), 0, 0 },
+	{ "mmRLC_CNTL", REG_MMIO, 0x30c0, &mmRLC_CNTL[0], sizeof(mmRLC_CNTL)/sizeof(mmRLC_CNTL[0]), 0, 0 },
+	{ "mmRLC_DEBUG_SELECT", REG_MMIO, 0x30c1, &mmRLC_DEBUG_SELECT[0], sizeof(mmRLC_DEBUG_SELECT)/sizeof(mmRLC_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_DEBUG", REG_MMIO, 0x30c2, &mmRLC_DEBUG[0], sizeof(mmRLC_DEBUG)/sizeof(mmRLC_DEBUG[0]), 0, 0 },
+	{ "mmRLC_MC_CNTL", REG_MMIO, 0x30c3, &mmRLC_MC_CNTL[0], sizeof(mmRLC_MC_CNTL)/sizeof(mmRLC_MC_CNTL[0]), 0, 0 },
+	{ "mmRLC_STAT", REG_MMIO, 0x30c4, &mmRLC_STAT[0], sizeof(mmRLC_STAT)/sizeof(mmRLC_STAT[0]), 0, 0 },
+	{ "mmRLC_SOFT_RESET_GPU", REG_MMIO, 0x30c5, &mmRLC_SOFT_RESET_GPU[0], sizeof(mmRLC_SOFT_RESET_GPU)/sizeof(mmRLC_SOFT_RESET_GPU[0]), 0, 0 },
+	{ "mmRLC_MEM_SLP_CNTL", REG_MMIO, 0x30c6, &mmRLC_MEM_SLP_CNTL[0], sizeof(mmRLC_MEM_SLP_CNTL)/sizeof(mmRLC_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_MAX", REG_MMIO, 0x30d2, &mmRLC_LB_CNTR_MAX[0], sizeof(mmRLC_LB_CNTR_MAX)/sizeof(mmRLC_LB_CNTR_MAX[0]), 0, 0 },
+	{ "mmRLC_LB_CNTL", REG_MMIO, 0x30d9, &mmRLC_LB_CNTL[0], sizeof(mmRLC_LB_CNTL)/sizeof(mmRLC_LB_CNTL[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_INIT", REG_MMIO, 0x30db, &mmRLC_LB_CNTR_INIT[0], sizeof(mmRLC_LB_CNTR_INIT)/sizeof(mmRLC_LB_CNTR_INIT[0]), 0, 0 },
+	{ "mmRLC_LOAD_BALANCE_CNTR", REG_MMIO, 0x30dc, &mmRLC_LOAD_BALANCE_CNTR[0], sizeof(mmRLC_LOAD_BALANCE_CNTR)/sizeof(mmRLC_LOAD_BALANCE_CNTR[0]), 0, 0 },
+	{ "mmRLC_SAVE_AND_RESTORE_BASE", REG_MMIO, 0x30dd, &mmRLC_SAVE_AND_RESTORE_BASE[0], sizeof(mmRLC_SAVE_AND_RESTORE_BASE)/sizeof(mmRLC_SAVE_AND_RESTORE_BASE[0]), 0, 0 },
+	{ "mmRLC_DRIVER_CPDMA_STATUS", REG_MMIO, 0x30de, &mmRLC_DRIVER_CPDMA_STATUS[0], sizeof(mmRLC_DRIVER_CPDMA_STATUS)/sizeof(mmRLC_DRIVER_CPDMA_STATUS[0]), 0, 0 },
+	{ "mmRLC_JUMP_TABLE_RESTORE", REG_MMIO, 0x30de, &mmRLC_JUMP_TABLE_RESTORE[0], sizeof(mmRLC_JUMP_TABLE_RESTORE)/sizeof(mmRLC_JUMP_TABLE_RESTORE[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY_2", REG_MMIO, 0x30df, &mmRLC_PG_DELAY_2[0], sizeof(mmRLC_PG_DELAY_2)/sizeof(mmRLC_PG_DELAY_2[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG_SELECT", REG_MMIO, 0x30e0, &mmRLC_GPM_DEBUG_SELECT[0], sizeof(mmRLC_GPM_DEBUG_SELECT)/sizeof(mmRLC_GPM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG", REG_MMIO, 0x30e1, &mmRLC_GPM_DEBUG[0], sizeof(mmRLC_GPM_DEBUG)/sizeof(mmRLC_GPM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_GPM_UCODE_ADDR", REG_MMIO, 0x30e2, &mmRLC_GPM_UCODE_ADDR[0], sizeof(mmRLC_GPM_UCODE_ADDR)/sizeof(mmRLC_GPM_UCODE_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_UCODE_DATA", REG_MMIO, 0x30e3, &mmRLC_GPM_UCODE_DATA[0], sizeof(mmRLC_GPM_UCODE_DATA)/sizeof(mmRLC_GPM_UCODE_DATA[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_LSB", REG_MMIO, 0x30e4, &mmRLC_GPU_CLOCK_COUNT_LSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_LSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_LSB[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_MSB", REG_MMIO, 0x30e5, &mmRLC_GPU_CLOCK_COUNT_MSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_MSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_MSB[0]), 0, 0 },
+	{ "mmRLC_CAPTURE_GPU_CLOCK_COUNT", REG_MMIO, 0x30e6, &mmRLC_CAPTURE_GPU_CLOCK_COUNT[0], sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT)/sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT[0]), 0, 0 },
+	{ "mmRLC_UCODE_CNTL", REG_MMIO, 0x30e7, &mmRLC_UCODE_CNTL[0], sizeof(mmRLC_UCODE_CNTL)/sizeof(mmRLC_UCODE_CNTL[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT4_7", REG_SMC, 0x31, &ixDIDT_DB_WEIGHT4_7[0], sizeof(ixDIDT_DB_WEIGHT4_7)/sizeof(ixDIDT_DB_WEIGHT4_7[0]), 0, 0 },
+	{ "mmRLC_GPM_STAT", REG_MMIO, 0x3100, &mmRLC_GPM_STAT[0], sizeof(mmRLC_GPM_STAT)/sizeof(mmRLC_GPM_STAT[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32_RES_SEL", REG_MMIO, 0x3101, &mmRLC_GPU_CLOCK_32_RES_SEL[0], sizeof(mmRLC_GPU_CLOCK_32_RES_SEL)/sizeof(mmRLC_GPU_CLOCK_32_RES_SEL[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32", REG_MMIO, 0x3102, &mmRLC_GPU_CLOCK_32[0], sizeof(mmRLC_GPU_CLOCK_32)/sizeof(mmRLC_GPU_CLOCK_32[0]), 0, 0 },
+	{ "mmRLC_PG_CNTL", REG_MMIO, 0x3103, &mmRLC_PG_CNTL[0], sizeof(mmRLC_PG_CNTL)/sizeof(mmRLC_PG_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_PRIORITY", REG_MMIO, 0x3104, &mmRLC_GPM_THREAD_PRIORITY[0], sizeof(mmRLC_GPM_THREAD_PRIORITY)/sizeof(mmRLC_GPM_THREAD_PRIORITY[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_ENABLE", REG_MMIO, 0x3105, &mmRLC_GPM_THREAD_ENABLE[0], sizeof(mmRLC_GPM_THREAD_ENABLE)/sizeof(mmRLC_GPM_THREAD_ENABLE[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD0", REG_MMIO, 0x3106, &mmRLC_GPM_VMID_THREAD0[0], sizeof(mmRLC_GPM_VMID_THREAD0)/sizeof(mmRLC_GPM_VMID_THREAD0[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD1", REG_MMIO, 0x3107, &mmRLC_GPM_VMID_THREAD1[0], sizeof(mmRLC_GPM_VMID_THREAD1)/sizeof(mmRLC_GPM_VMID_THREAD1[0]), 0, 0 },
+	{ "mmRLC_CGTT_MGCG_OVERRIDE", REG_MMIO, 0x3108, &mmRLC_CGTT_MGCG_OVERRIDE[0], sizeof(mmRLC_CGTT_MGCG_OVERRIDE)/sizeof(mmRLC_CGTT_MGCG_OVERRIDE[0]), 0, 0 },
+	{ "mmRLC_CGCG_CGLS_CTRL", REG_MMIO, 0x3109, &mmRLC_CGCG_CGLS_CTRL[0], sizeof(mmRLC_CGCG_CGLS_CTRL)/sizeof(mmRLC_CGCG_CGLS_CTRL[0]), 0, 0 },
+	{ "mmRLC_CGCG_RAMP_CTRL", REG_MMIO, 0x310a, &mmRLC_CGCG_RAMP_CTRL[0], sizeof(mmRLC_CGCG_RAMP_CTRL)/sizeof(mmRLC_CGCG_RAMP_CTRL[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_STATUS", REG_MMIO, 0x310b, &mmRLC_DYN_PG_STATUS[0], sizeof(mmRLC_DYN_PG_STATUS)/sizeof(mmRLC_DYN_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_REQUEST", REG_MMIO, 0x310c, &mmRLC_DYN_PG_REQUEST[0], sizeof(mmRLC_DYN_PG_REQUEST)/sizeof(mmRLC_DYN_PG_REQUEST[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY", REG_MMIO, 0x310d, &mmRLC_PG_DELAY[0], sizeof(mmRLC_PG_DELAY)/sizeof(mmRLC_PG_DELAY[0]), 0, 0 },
+	{ "mmRLC_CU_STATUS", REG_MMIO, 0x310e, &mmRLC_CU_STATUS[0], sizeof(mmRLC_CU_STATUS)/sizeof(mmRLC_CU_STATUS[0]), 0, 0 },
+	{ "mmRLC_LB_INIT_CU_MASK", REG_MMIO, 0x310f, &mmRLC_LB_INIT_CU_MASK[0], sizeof(mmRLC_LB_INIT_CU_MASK)/sizeof(mmRLC_LB_INIT_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_ALWAYS_ACTIVE_CU_MASK", REG_MMIO, 0x3110, &mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0], sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK)/sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_PARAMS", REG_MMIO, 0x3111, &mmRLC_LB_PARAMS[0], sizeof(mmRLC_LB_PARAMS)/sizeof(mmRLC_LB_PARAMS[0]), 0, 0 },
+	{ "mmRLC_THREAD1_DELAY", REG_MMIO, 0x3112, &mmRLC_THREAD1_DELAY[0], sizeof(mmRLC_THREAD1_DELAY)/sizeof(mmRLC_THREAD1_DELAY[0]), 0, 0 },
+	{ "mmRLC_PG_ALWAYS_ON_CU_MASK", REG_MMIO, 0x3113, &mmRLC_PG_ALWAYS_ON_CU_MASK[0], sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK)/sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_MAX_PG_CU", REG_MMIO, 0x3114, &mmRLC_MAX_PG_CU[0], sizeof(mmRLC_MAX_PG_CU)/sizeof(mmRLC_MAX_PG_CU[0]), 0, 0 },
+	{ "mmRLC_AUTO_PG_CTRL", REG_MMIO, 0x3115, &mmRLC_AUTO_PG_CTRL[0], sizeof(mmRLC_AUTO_PG_CTRL)/sizeof(mmRLC_AUTO_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_GRBM_REG_SAVE_CTRL", REG_MMIO, 0x3116, &mmRLC_SMU_GRBM_REG_SAVE_CTRL[0], sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL)/sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_PG_CTRL", REG_MMIO, 0x3117, &mmRLC_SMU_PG_CTRL[0], sizeof(mmRLC_SMU_PG_CTRL)/sizeof(mmRLC_SMU_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_PG_WAKE_UP_CTRL", REG_MMIO, 0x3118, &mmRLC_SMU_PG_WAKE_UP_CTRL[0], sizeof(mmRLC_SMU_PG_WAKE_UP_CTRL)/sizeof(mmRLC_SMU_PG_WAKE_UP_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_MASTER_INDEX", REG_MMIO, 0x3119, &mmRLC_SERDES_RD_MASTER_INDEX[0], sizeof(mmRLC_SERDES_RD_MASTER_INDEX)/sizeof(mmRLC_SERDES_RD_MASTER_INDEX[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_0", REG_MMIO, 0x311a, &mmRLC_SERDES_RD_DATA_0[0], sizeof(mmRLC_SERDES_RD_DATA_0)/sizeof(mmRLC_SERDES_RD_DATA_0[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_1", REG_MMIO, 0x311b, &mmRLC_SERDES_RD_DATA_1[0], sizeof(mmRLC_SERDES_RD_DATA_1)/sizeof(mmRLC_SERDES_RD_DATA_1[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_2", REG_MMIO, 0x311c, &mmRLC_SERDES_RD_DATA_2[0], sizeof(mmRLC_SERDES_RD_DATA_2)/sizeof(mmRLC_SERDES_RD_DATA_2[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_CU_MASTER_MASK", REG_MMIO, 0x311d, &mmRLC_SERDES_WR_CU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_NONCU_MASTER_MASK", REG_MMIO, 0x311e, &mmRLC_SERDES_WR_NONCU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_CTRL", REG_MMIO, 0x311f, &mmRLC_SERDES_WR_CTRL[0], sizeof(mmRLC_SERDES_WR_CTRL)/sizeof(mmRLC_SERDES_WR_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_DATA", REG_MMIO, 0x3120, &mmRLC_SERDES_WR_DATA[0], sizeof(mmRLC_SERDES_WR_DATA)/sizeof(mmRLC_SERDES_WR_DATA[0]), 0, 0 },
+	{ "mmRLC_SERDES_CU_MASTER_BUSY", REG_MMIO, 0x3121, &mmRLC_SERDES_CU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_CU_MASTER_BUSY)/sizeof(mmRLC_SERDES_CU_MASTER_BUSY[0]), 0, 0 },
+	{ "mmRLC_SERDES_NONCU_MASTER_BUSY", REG_MMIO, 0x3122, &mmRLC_SERDES_NONCU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY)/sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_0", REG_MMIO, 0x3123, &mmRLC_GPM_GENERAL_0[0], sizeof(mmRLC_GPM_GENERAL_0)/sizeof(mmRLC_GPM_GENERAL_0[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_1", REG_MMIO, 0x3124, &mmRLC_GPM_GENERAL_1[0], sizeof(mmRLC_GPM_GENERAL_1)/sizeof(mmRLC_GPM_GENERAL_1[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_2", REG_MMIO, 0x3125, &mmRLC_GPM_GENERAL_2[0], sizeof(mmRLC_GPM_GENERAL_2)/sizeof(mmRLC_GPM_GENERAL_2[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_3", REG_MMIO, 0x3126, &mmRLC_GPM_GENERAL_3[0], sizeof(mmRLC_GPM_GENERAL_3)/sizeof(mmRLC_GPM_GENERAL_3[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_4", REG_MMIO, 0x3127, &mmRLC_GPM_GENERAL_4[0], sizeof(mmRLC_GPM_GENERAL_4)/sizeof(mmRLC_GPM_GENERAL_4[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_5", REG_MMIO, 0x3128, &mmRLC_GPM_GENERAL_5[0], sizeof(mmRLC_GPM_GENERAL_5)/sizeof(mmRLC_GPM_GENERAL_5[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_6", REG_MMIO, 0x3129, &mmRLC_GPM_GENERAL_6[0], sizeof(mmRLC_GPM_GENERAL_6)/sizeof(mmRLC_GPM_GENERAL_6[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_7", REG_MMIO, 0x312a, &mmRLC_GPM_GENERAL_7[0], sizeof(mmRLC_GPM_GENERAL_7)/sizeof(mmRLC_GPM_GENERAL_7[0]), 0, 0 },
+	{ "mmRLC_GPM_CU_PD_TIMEOUT", REG_MMIO, 0x312b, &mmRLC_GPM_CU_PD_TIMEOUT[0], sizeof(mmRLC_GPM_CU_PD_TIMEOUT)/sizeof(mmRLC_GPM_CU_PD_TIMEOUT[0]), 0, 0 },
+	{ "mmRLC_GPM_SCRATCH_ADDR", REG_MMIO, 0x312c, &mmRLC_GPM_SCRATCH_ADDR[0], sizeof(mmRLC_GPM_SCRATCH_ADDR)/sizeof(mmRLC_GPM_SCRATCH_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_SCRATCH_DATA", REG_MMIO, 0x312d, &mmRLC_GPM_SCRATCH_DATA[0], sizeof(mmRLC_GPM_SCRATCH_DATA)/sizeof(mmRLC_GPM_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmRLC_STATIC_PG_STATUS", REG_MMIO, 0x312e, &mmRLC_STATIC_PG_STATUS[0], sizeof(mmRLC_STATIC_PG_STATUS)/sizeof(mmRLC_STATIC_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_GPM_PERF_COUNT_0", REG_MMIO, 0x312f, &mmRLC_GPM_PERF_COUNT_0[0], sizeof(mmRLC_GPM_PERF_COUNT_0)/sizeof(mmRLC_GPM_PERF_COUNT_0[0]), 0, 0 },
+	{ "mmRLC_GPM_PERF_COUNT_1", REG_MMIO, 0x3130, &mmRLC_GPM_PERF_COUNT_1[0], sizeof(mmRLC_GPM_PERF_COUNT_1)/sizeof(mmRLC_GPM_PERF_COUNT_1[0]), 0, 0 },
+	{ "mmRLC_SPM_VMID", REG_MMIO, 0x3131, &mmRLC_SPM_VMID[0], sizeof(mmRLC_SPM_VMID)/sizeof(mmRLC_SPM_VMID[0]), 0, 0 },
+	{ "mmRLC_SPM_INT_CNTL", REG_MMIO, 0x3132, &mmRLC_SPM_INT_CNTL[0], sizeof(mmRLC_SPM_INT_CNTL)/sizeof(mmRLC_SPM_INT_CNTL[0]), 0, 0 },
+	{ "mmRLC_SPM_INT_STATUS", REG_MMIO, 0x3133, &mmRLC_SPM_INT_STATUS[0], sizeof(mmRLC_SPM_INT_STATUS)/sizeof(mmRLC_SPM_INT_STATUS[0]), 0, 0 },
+	{ "mmRLC_SPM_DEBUG_SELECT", REG_MMIO, 0x3134, &mmRLC_SPM_DEBUG_SELECT[0], sizeof(mmRLC_SPM_DEBUG_SELECT)/sizeof(mmRLC_SPM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_SPM_DEBUG", REG_MMIO, 0x3135, &mmRLC_SPM_DEBUG[0], sizeof(mmRLC_SPM_DEBUG)/sizeof(mmRLC_SPM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_ADDR", REG_MMIO, 0x3136, &mmRLC_GPM_LOG_ADDR[0], sizeof(mmRLC_GPM_LOG_ADDR)/sizeof(mmRLC_GPM_LOG_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_SIZE", REG_MMIO, 0x3137, &mmRLC_GPM_LOG_SIZE[0], sizeof(mmRLC_GPM_LOG_SIZE)/sizeof(mmRLC_GPM_LOG_SIZE[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_CONT", REG_MMIO, 0x3138, &mmRLC_GPM_LOG_CONT[0], sizeof(mmRLC_GPM_LOG_CONT)/sizeof(mmRLC_GPM_LOG_CONT[0]), 0, 0 },
+	{ "mmRLC_GPR_REG1", REG_MMIO, 0x3139, &mmRLC_GPR_REG1[0], sizeof(mmRLC_GPR_REG1)/sizeof(mmRLC_GPR_REG1[0]), 0, 0 },
+	{ "mmRLC_SAFE_MODE", REG_MMIO, 0x313a, &mmRLC_SAFE_MODE[0], sizeof(mmRLC_SAFE_MODE)/sizeof(mmRLC_SAFE_MODE[0]), 0, 0 },
+	{ "mmRLC_GPR_REG2", REG_MMIO, 0x313a, &mmRLC_GPR_REG2[0], sizeof(mmRLC_GPR_REG2)/sizeof(mmRLC_GPR_REG2[0]), 0, 0 },
+	{ "mmSPI_ARB_PRIORITY", REG_MMIO, 0x31c0, &mmSPI_ARB_PRIORITY[0], sizeof(mmSPI_ARB_PRIORITY)/sizeof(mmSPI_ARB_PRIORITY[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_0", REG_MMIO, 0x31c1, &mmSPI_ARB_CYCLES_0[0], sizeof(mmSPI_ARB_CYCLES_0)/sizeof(mmSPI_ARB_CYCLES_0[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_1", REG_MMIO, 0x31c2, &mmSPI_ARB_CYCLES_1[0], sizeof(mmSPI_ARB_CYCLES_1)/sizeof(mmSPI_ARB_CYCLES_1[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_GFX", REG_MMIO, 0x31c3, &mmSPI_CDBG_SYS_GFX[0], sizeof(mmSPI_CDBG_SYS_GFX)/sizeof(mmSPI_CDBG_SYS_GFX[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_HP3D", REG_MMIO, 0x31c4, &mmSPI_CDBG_SYS_HP3D[0], sizeof(mmSPI_CDBG_SYS_HP3D)/sizeof(mmSPI_CDBG_SYS_HP3D[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_CS0", REG_MMIO, 0x31c5, &mmSPI_CDBG_SYS_CS0[0], sizeof(mmSPI_CDBG_SYS_CS0)/sizeof(mmSPI_CDBG_SYS_CS0[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_CS1", REG_MMIO, 0x31c6, &mmSPI_CDBG_SYS_CS1[0], sizeof(mmSPI_CDBG_SYS_CS1)/sizeof(mmSPI_CDBG_SYS_CS1[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_GFX", REG_MMIO, 0x31c7, &mmSPI_WCL_PIPE_PERCENT_GFX[0], sizeof(mmSPI_WCL_PIPE_PERCENT_GFX)/sizeof(mmSPI_WCL_PIPE_PERCENT_GFX[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_HP3D", REG_MMIO, 0x31c8, &mmSPI_WCL_PIPE_PERCENT_HP3D[0], sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D)/sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS0", REG_MMIO, 0x31c9, &mmSPI_WCL_PIPE_PERCENT_CS0[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS0)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS0[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS1", REG_MMIO, 0x31ca, &mmSPI_WCL_PIPE_PERCENT_CS1[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS1)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS1[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS2", REG_MMIO, 0x31cb, &mmSPI_WCL_PIPE_PERCENT_CS2[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS2)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS2[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS3", REG_MMIO, 0x31cc, &mmSPI_WCL_PIPE_PERCENT_CS3[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS3)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS3[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS4", REG_MMIO, 0x31cd, &mmSPI_WCL_PIPE_PERCENT_CS4[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS4)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS4[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS5", REG_MMIO, 0x31ce, &mmSPI_WCL_PIPE_PERCENT_CS5[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS5)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS5[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS6", REG_MMIO, 0x31cf, &mmSPI_WCL_PIPE_PERCENT_CS6[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS6)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS6[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS7", REG_MMIO, 0x31d0, &mmSPI_WCL_PIPE_PERCENT_CS7[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS7)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS7[0]), 0, 0 },
+	{ "mmSPI_GDBG_WAVE_CNTL", REG_MMIO, 0x31d1, &mmSPI_GDBG_WAVE_CNTL[0], sizeof(mmSPI_GDBG_WAVE_CNTL)/sizeof(mmSPI_GDBG_WAVE_CNTL[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_CONFIG", REG_MMIO, 0x31d2, &mmSPI_GDBG_TRAP_CONFIG[0], sizeof(mmSPI_GDBG_TRAP_CONFIG)/sizeof(mmSPI_GDBG_TRAP_CONFIG[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_MASK", REG_MMIO, 0x31d3, &mmSPI_GDBG_TRAP_MASK[0], sizeof(mmSPI_GDBG_TRAP_MASK)/sizeof(mmSPI_GDBG_TRAP_MASK[0]), 0, 0 },
+	{ "mmSPI_GDBG_TBA_LO", REG_MMIO, 0x31d4, &mmSPI_GDBG_TBA_LO[0], sizeof(mmSPI_GDBG_TBA_LO)/sizeof(mmSPI_GDBG_TBA_LO[0]), 0, 0 },
+	{ "mmSPI_GDBG_TBA_HI", REG_MMIO, 0x31d5, &mmSPI_GDBG_TBA_HI[0], sizeof(mmSPI_GDBG_TBA_HI)/sizeof(mmSPI_GDBG_TBA_HI[0]), 0, 0 },
+	{ "mmSPI_GDBG_TMA_LO", REG_MMIO, 0x31d6, &mmSPI_GDBG_TMA_LO[0], sizeof(mmSPI_GDBG_TMA_LO)/sizeof(mmSPI_GDBG_TMA_LO[0]), 0, 0 },
+	{ "mmSPI_GDBG_TMA_HI", REG_MMIO, 0x31d7, &mmSPI_GDBG_TMA_HI[0], sizeof(mmSPI_GDBG_TMA_HI)/sizeof(mmSPI_GDBG_TMA_HI[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_DATA0", REG_MMIO, 0x31d8, &mmSPI_GDBG_TRAP_DATA0[0], sizeof(mmSPI_GDBG_TRAP_DATA0)/sizeof(mmSPI_GDBG_TRAP_DATA0[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_DATA1", REG_MMIO, 0x31d9, &mmSPI_GDBG_TRAP_DATA1[0], sizeof(mmSPI_GDBG_TRAP_DATA1)/sizeof(mmSPI_GDBG_TRAP_DATA1[0]), 0, 0 },
+	{ "mmSPI_RESET_DEBUG", REG_MMIO, 0x31da, &mmSPI_RESET_DEBUG[0], sizeof(mmSPI_RESET_DEBUG)/sizeof(mmSPI_RESET_DEBUG[0]), 0, 0 },
+	{ "mmSPI_COMPUTE_QUEUE_RESET", REG_MMIO, 0x31db, &mmSPI_COMPUTE_QUEUE_RESET[0], sizeof(mmSPI_COMPUTE_QUEUE_RESET)/sizeof(mmSPI_COMPUTE_QUEUE_RESET[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_0", REG_MMIO, 0x31dc, &mmSPI_RESOURCE_RESERVE_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_CU_0[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_1", REG_MMIO, 0x31dd, &mmSPI_RESOURCE_RESERVE_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_CU_1[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_2", REG_MMIO, 0x31de, &mmSPI_RESOURCE_RESERVE_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_CU_2[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_3", REG_MMIO, 0x31df, &mmSPI_RESOURCE_RESERVE_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_CU_3[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_4", REG_MMIO, 0x31e0, &mmSPI_RESOURCE_RESERVE_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_CU_4[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_5", REG_MMIO, 0x31e1, &mmSPI_RESOURCE_RESERVE_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_CU_5[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_6", REG_MMIO, 0x31e2, &mmSPI_RESOURCE_RESERVE_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_CU_6[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_7", REG_MMIO, 0x31e3, &mmSPI_RESOURCE_RESERVE_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_CU_7[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_8", REG_MMIO, 0x31e4, &mmSPI_RESOURCE_RESERVE_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_CU_8[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_9", REG_MMIO, 0x31e5, &mmSPI_RESOURCE_RESERVE_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_CU_9[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_0", REG_MMIO, 0x31e6, &mmSPI_RESOURCE_RESERVE_EN_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_1", REG_MMIO, 0x31e7, &mmSPI_RESOURCE_RESERVE_EN_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_2", REG_MMIO, 0x31e8, &mmSPI_RESOURCE_RESERVE_EN_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_3", REG_MMIO, 0x31e9, &mmSPI_RESOURCE_RESERVE_EN_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_4", REG_MMIO, 0x31ea, &mmSPI_RESOURCE_RESERVE_EN_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_5", REG_MMIO, 0x31eb, &mmSPI_RESOURCE_RESERVE_EN_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_6", REG_MMIO, 0x31ec, &mmSPI_RESOURCE_RESERVE_EN_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_7", REG_MMIO, 0x31ed, &mmSPI_RESOURCE_RESERVE_EN_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_8", REG_MMIO, 0x31ee, &mmSPI_RESOURCE_RESERVE_EN_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_9", REG_MMIO, 0x31ef, &mmSPI_RESOURCE_RESERVE_EN_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_10", REG_MMIO, 0x31f0, &mmSPI_RESOURCE_RESERVE_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_CU_10[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_11", REG_MMIO, 0x31f1, &mmSPI_RESOURCE_RESERVE_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_CU_11[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_10", REG_MMIO, 0x31f2, &mmSPI_RESOURCE_RESERVE_EN_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_11", REG_MMIO, 0x31f3, &mmSPI_RESOURCE_RESERVE_EN_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT8_11", REG_SMC, 0x32, &ixDIDT_DB_WEIGHT8_11[0], sizeof(ixDIDT_DB_WEIGHT8_11)/sizeof(ixDIDT_DB_WEIGHT8_11[0]), 0, 0 },
+	{ "mmCP_HPD_ROQ_OFFSETS", REG_MMIO, 0x3240, &mmCP_HPD_ROQ_OFFSETS[0], sizeof(mmCP_HPD_ROQ_OFFSETS)/sizeof(mmCP_HPD_ROQ_OFFSETS[0]), 0, 0 },
+	{ "mmCP_HPD_EOP_BASE_ADDR", REG_MMIO, 0x3241, &mmCP_HPD_EOP_BASE_ADDR[0], sizeof(mmCP_HPD_EOP_BASE_ADDR)/sizeof(mmCP_HPD_EOP_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_HPD_EOP_BASE_ADDR_HI", REG_MMIO, 0x3242, &mmCP_HPD_EOP_BASE_ADDR_HI[0], sizeof(mmCP_HPD_EOP_BASE_ADDR_HI)/sizeof(mmCP_HPD_EOP_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HPD_EOP_VMID", REG_MMIO, 0x3243, &mmCP_HPD_EOP_VMID[0], sizeof(mmCP_HPD_EOP_VMID)/sizeof(mmCP_HPD_EOP_VMID[0]), 0, 0 },
+	{ "mmCP_HPD_EOP_CONTROL", REG_MMIO, 0x3244, &mmCP_HPD_EOP_CONTROL[0], sizeof(mmCP_HPD_EOP_CONTROL)/sizeof(mmCP_HPD_EOP_CONTROL[0]), 0, 0 },
+	{ "mmCP_MQD_BASE_ADDR", REG_MMIO, 0x3245, &mmCP_MQD_BASE_ADDR[0], sizeof(mmCP_MQD_BASE_ADDR)/sizeof(mmCP_MQD_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_MQD_BASE_ADDR_HI", REG_MMIO, 0x3246, &mmCP_MQD_BASE_ADDR_HI[0], sizeof(mmCP_MQD_BASE_ADDR_HI)/sizeof(mmCP_MQD_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_ACTIVE", REG_MMIO, 0x3247, &mmCP_HQD_ACTIVE[0], sizeof(mmCP_HQD_ACTIVE)/sizeof(mmCP_HQD_ACTIVE[0]), 0, 0 },
+	{ "mmCP_HQD_VMID", REG_MMIO, 0x3248, &mmCP_HQD_VMID[0], sizeof(mmCP_HQD_VMID)/sizeof(mmCP_HQD_VMID[0]), 0, 0 },
+	{ "mmCP_HQD_PERSISTENT_STATE", REG_MMIO, 0x3249, &mmCP_HQD_PERSISTENT_STATE[0], sizeof(mmCP_HQD_PERSISTENT_STATE)/sizeof(mmCP_HQD_PERSISTENT_STATE[0]), 0, 0 },
+	{ "mmCP_HQD_PIPE_PRIORITY", REG_MMIO, 0x324a, &mmCP_HQD_PIPE_PRIORITY[0], sizeof(mmCP_HQD_PIPE_PRIORITY)/sizeof(mmCP_HQD_PIPE_PRIORITY[0]), 0, 0 },
+	{ "mmCP_HQD_QUEUE_PRIORITY", REG_MMIO, 0x324b, &mmCP_HQD_QUEUE_PRIORITY[0], sizeof(mmCP_HQD_QUEUE_PRIORITY)/sizeof(mmCP_HQD_QUEUE_PRIORITY[0]), 0, 0 },
+	{ "mmCP_HQD_QUANTUM", REG_MMIO, 0x324c, &mmCP_HQD_QUANTUM[0], sizeof(mmCP_HQD_QUANTUM)/sizeof(mmCP_HQD_QUANTUM[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_BASE", REG_MMIO, 0x324d, &mmCP_HQD_PQ_BASE[0], sizeof(mmCP_HQD_PQ_BASE)/sizeof(mmCP_HQD_PQ_BASE[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_BASE_HI", REG_MMIO, 0x324e, &mmCP_HQD_PQ_BASE_HI[0], sizeof(mmCP_HQD_PQ_BASE_HI)/sizeof(mmCP_HQD_PQ_BASE_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR", REG_MMIO, 0x324f, &mmCP_HQD_PQ_RPTR[0], sizeof(mmCP_HQD_PQ_RPTR)/sizeof(mmCP_HQD_PQ_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR", REG_MMIO, 0x3250, &mmCP_HQD_PQ_RPTR_REPORT_ADDR[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI", REG_MMIO, 0x3251, &mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR", REG_MMIO, 0x3252, &mmCP_HQD_PQ_WPTR_POLL_ADDR[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3253, &mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_DOORBELL_CONTROL", REG_MMIO, 0x3254, &mmCP_HQD_PQ_DOORBELL_CONTROL[0], sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL)/sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR", REG_MMIO, 0x3255, &mmCP_HQD_PQ_WPTR[0], sizeof(mmCP_HQD_PQ_WPTR)/sizeof(mmCP_HQD_PQ_WPTR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_CONTROL", REG_MMIO, 0x3256, &mmCP_HQD_PQ_CONTROL[0], sizeof(mmCP_HQD_PQ_CONTROL)/sizeof(mmCP_HQD_PQ_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_IB_BASE_ADDR", REG_MMIO, 0x3257, &mmCP_HQD_IB_BASE_ADDR[0], sizeof(mmCP_HQD_IB_BASE_ADDR)/sizeof(mmCP_HQD_IB_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_IB_BASE_ADDR_HI", REG_MMIO, 0x3258, &mmCP_HQD_IB_BASE_ADDR_HI[0], sizeof(mmCP_HQD_IB_BASE_ADDR_HI)/sizeof(mmCP_HQD_IB_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_IB_RPTR", REG_MMIO, 0x3259, &mmCP_HQD_IB_RPTR[0], sizeof(mmCP_HQD_IB_RPTR)/sizeof(mmCP_HQD_IB_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_IB_CONTROL", REG_MMIO, 0x325a, &mmCP_HQD_IB_CONTROL[0], sizeof(mmCP_HQD_IB_CONTROL)/sizeof(mmCP_HQD_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_IQ_TIMER", REG_MMIO, 0x325b, &mmCP_HQD_IQ_TIMER[0], sizeof(mmCP_HQD_IQ_TIMER)/sizeof(mmCP_HQD_IQ_TIMER[0]), 0, 0 },
+	{ "mmCP_HQD_IQ_RPTR", REG_MMIO, 0x325c, &mmCP_HQD_IQ_RPTR[0], sizeof(mmCP_HQD_IQ_RPTR)/sizeof(mmCP_HQD_IQ_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_DEQUEUE_REQUEST", REG_MMIO, 0x325d, &mmCP_HQD_DEQUEUE_REQUEST[0], sizeof(mmCP_HQD_DEQUEUE_REQUEST)/sizeof(mmCP_HQD_DEQUEUE_REQUEST[0]), 0, 0 },
+	{ "mmCP_HQD_DMA_OFFLOAD", REG_MMIO, 0x325e, &mmCP_HQD_DMA_OFFLOAD[0], sizeof(mmCP_HQD_DMA_OFFLOAD)/sizeof(mmCP_HQD_DMA_OFFLOAD[0]), 0, 0 },
+	{ "mmCP_HQD_SEMA_CMD", REG_MMIO, 0x325f, &mmCP_HQD_SEMA_CMD[0], sizeof(mmCP_HQD_SEMA_CMD)/sizeof(mmCP_HQD_SEMA_CMD[0]), 0, 0 },
+	{ "mmCP_HQD_MSG_TYPE", REG_MMIO, 0x3260, &mmCP_HQD_MSG_TYPE[0], sizeof(mmCP_HQD_MSG_TYPE)/sizeof(mmCP_HQD_MSG_TYPE[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC0_PREOP_LO", REG_MMIO, 0x3261, &mmCP_HQD_ATOMIC0_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC0_PREOP_HI", REG_MMIO, 0x3262, &mmCP_HQD_ATOMIC0_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC1_PREOP_LO", REG_MMIO, 0x3263, &mmCP_HQD_ATOMIC1_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC1_PREOP_HI", REG_MMIO, 0x3264, &mmCP_HQD_ATOMIC1_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_SCHEDULER0", REG_MMIO, 0x3265, &mmCP_HQD_HQ_SCHEDULER0[0], sizeof(mmCP_HQD_HQ_SCHEDULER0)/sizeof(mmCP_HQD_HQ_SCHEDULER0[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_SCHEDULER1", REG_MMIO, 0x3266, &mmCP_HQD_HQ_SCHEDULER1[0], sizeof(mmCP_HQD_HQ_SCHEDULER1)/sizeof(mmCP_HQD_HQ_SCHEDULER1[0]), 0, 0 },
+	{ "mmCP_MQD_CONTROL", REG_MMIO, 0x3267, &mmCP_MQD_CONTROL[0], sizeof(mmCP_MQD_CONTROL)/sizeof(mmCP_MQD_CONTROL[0]), 0, 0 },
+	{ "mmDIDT_IND_INDEX", REG_MMIO, 0x3280, &mmDIDT_IND_INDEX[0], sizeof(mmDIDT_IND_INDEX)/sizeof(mmDIDT_IND_INDEX[0]), 0, 0 },
+	{ "mmDIDT_IND_DATA", REG_MMIO, 0x3281, &mmDIDT_IND_DATA[0], sizeof(mmDIDT_IND_DATA)/sizeof(mmDIDT_IND_DATA[0]), 0, 0 },
+	{ "mmTCP_WATCH0_ADDR_H", REG_MMIO, 0x32a0, &mmTCP_WATCH0_ADDR_H[0], sizeof(mmTCP_WATCH0_ADDR_H)/sizeof(mmTCP_WATCH0_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH0_ADDR_L", REG_MMIO, 0x32a1, &mmTCP_WATCH0_ADDR_L[0], sizeof(mmTCP_WATCH0_ADDR_L)/sizeof(mmTCP_WATCH0_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH0_CNTL", REG_MMIO, 0x32a2, &mmTCP_WATCH0_CNTL[0], sizeof(mmTCP_WATCH0_CNTL)/sizeof(mmTCP_WATCH0_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH1_ADDR_H", REG_MMIO, 0x32a3, &mmTCP_WATCH1_ADDR_H[0], sizeof(mmTCP_WATCH1_ADDR_H)/sizeof(mmTCP_WATCH1_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH1_ADDR_L", REG_MMIO, 0x32a4, &mmTCP_WATCH1_ADDR_L[0], sizeof(mmTCP_WATCH1_ADDR_L)/sizeof(mmTCP_WATCH1_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH1_CNTL", REG_MMIO, 0x32a5, &mmTCP_WATCH1_CNTL[0], sizeof(mmTCP_WATCH1_CNTL)/sizeof(mmTCP_WATCH1_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH2_ADDR_H", REG_MMIO, 0x32a6, &mmTCP_WATCH2_ADDR_H[0], sizeof(mmTCP_WATCH2_ADDR_H)/sizeof(mmTCP_WATCH2_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH2_ADDR_L", REG_MMIO, 0x32a7, &mmTCP_WATCH2_ADDR_L[0], sizeof(mmTCP_WATCH2_ADDR_L)/sizeof(mmTCP_WATCH2_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH2_CNTL", REG_MMIO, 0x32a8, &mmTCP_WATCH2_CNTL[0], sizeof(mmTCP_WATCH2_CNTL)/sizeof(mmTCP_WATCH2_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH3_ADDR_H", REG_MMIO, 0x32a9, &mmTCP_WATCH3_ADDR_H[0], sizeof(mmTCP_WATCH3_ADDR_H)/sizeof(mmTCP_WATCH3_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH3_ADDR_L", REG_MMIO, 0x32aa, &mmTCP_WATCH3_ADDR_L[0], sizeof(mmTCP_WATCH3_ADDR_L)/sizeof(mmTCP_WATCH3_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH3_CNTL", REG_MMIO, 0x32ab, &mmTCP_WATCH3_CNTL[0], sizeof(mmTCP_WATCH3_CNTL)/sizeof(mmTCP_WATCH3_CNTL[0]), 0, 0 },
+	{ "mmGDS_VMID0_BASE", REG_MMIO, 0x3300, &mmGDS_VMID0_BASE[0], sizeof(mmGDS_VMID0_BASE)/sizeof(mmGDS_VMID0_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID0_SIZE", REG_MMIO, 0x3301, &mmGDS_VMID0_SIZE[0], sizeof(mmGDS_VMID0_SIZE)/sizeof(mmGDS_VMID0_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID1_BASE", REG_MMIO, 0x3302, &mmGDS_VMID1_BASE[0], sizeof(mmGDS_VMID1_BASE)/sizeof(mmGDS_VMID1_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID1_SIZE", REG_MMIO, 0x3303, &mmGDS_VMID1_SIZE[0], sizeof(mmGDS_VMID1_SIZE)/sizeof(mmGDS_VMID1_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID2_BASE", REG_MMIO, 0x3304, &mmGDS_VMID2_BASE[0], sizeof(mmGDS_VMID2_BASE)/sizeof(mmGDS_VMID2_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID2_SIZE", REG_MMIO, 0x3305, &mmGDS_VMID2_SIZE[0], sizeof(mmGDS_VMID2_SIZE)/sizeof(mmGDS_VMID2_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID3_BASE", REG_MMIO, 0x3306, &mmGDS_VMID3_BASE[0], sizeof(mmGDS_VMID3_BASE)/sizeof(mmGDS_VMID3_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID3_SIZE", REG_MMIO, 0x3307, &mmGDS_VMID3_SIZE[0], sizeof(mmGDS_VMID3_SIZE)/sizeof(mmGDS_VMID3_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID4_BASE", REG_MMIO, 0x3308, &mmGDS_VMID4_BASE[0], sizeof(mmGDS_VMID4_BASE)/sizeof(mmGDS_VMID4_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID4_SIZE", REG_MMIO, 0x3309, &mmGDS_VMID4_SIZE[0], sizeof(mmGDS_VMID4_SIZE)/sizeof(mmGDS_VMID4_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID5_BASE", REG_MMIO, 0x330a, &mmGDS_VMID5_BASE[0], sizeof(mmGDS_VMID5_BASE)/sizeof(mmGDS_VMID5_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID5_SIZE", REG_MMIO, 0x330b, &mmGDS_VMID5_SIZE[0], sizeof(mmGDS_VMID5_SIZE)/sizeof(mmGDS_VMID5_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID6_BASE", REG_MMIO, 0x330c, &mmGDS_VMID6_BASE[0], sizeof(mmGDS_VMID6_BASE)/sizeof(mmGDS_VMID6_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID6_SIZE", REG_MMIO, 0x330d, &mmGDS_VMID6_SIZE[0], sizeof(mmGDS_VMID6_SIZE)/sizeof(mmGDS_VMID6_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID7_BASE", REG_MMIO, 0x330e, &mmGDS_VMID7_BASE[0], sizeof(mmGDS_VMID7_BASE)/sizeof(mmGDS_VMID7_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID7_SIZE", REG_MMIO, 0x330f, &mmGDS_VMID7_SIZE[0], sizeof(mmGDS_VMID7_SIZE)/sizeof(mmGDS_VMID7_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID8_BASE", REG_MMIO, 0x3310, &mmGDS_VMID8_BASE[0], sizeof(mmGDS_VMID8_BASE)/sizeof(mmGDS_VMID8_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID8_SIZE", REG_MMIO, 0x3311, &mmGDS_VMID8_SIZE[0], sizeof(mmGDS_VMID8_SIZE)/sizeof(mmGDS_VMID8_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID9_BASE", REG_MMIO, 0x3312, &mmGDS_VMID9_BASE[0], sizeof(mmGDS_VMID9_BASE)/sizeof(mmGDS_VMID9_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID9_SIZE", REG_MMIO, 0x3313, &mmGDS_VMID9_SIZE[0], sizeof(mmGDS_VMID9_SIZE)/sizeof(mmGDS_VMID9_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID10_BASE", REG_MMIO, 0x3314, &mmGDS_VMID10_BASE[0], sizeof(mmGDS_VMID10_BASE)/sizeof(mmGDS_VMID10_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID10_SIZE", REG_MMIO, 0x3315, &mmGDS_VMID10_SIZE[0], sizeof(mmGDS_VMID10_SIZE)/sizeof(mmGDS_VMID10_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID11_BASE", REG_MMIO, 0x3316, &mmGDS_VMID11_BASE[0], sizeof(mmGDS_VMID11_BASE)/sizeof(mmGDS_VMID11_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID11_SIZE", REG_MMIO, 0x3317, &mmGDS_VMID11_SIZE[0], sizeof(mmGDS_VMID11_SIZE)/sizeof(mmGDS_VMID11_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID12_BASE", REG_MMIO, 0x3318, &mmGDS_VMID12_BASE[0], sizeof(mmGDS_VMID12_BASE)/sizeof(mmGDS_VMID12_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID12_SIZE", REG_MMIO, 0x3319, &mmGDS_VMID12_SIZE[0], sizeof(mmGDS_VMID12_SIZE)/sizeof(mmGDS_VMID12_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID13_BASE", REG_MMIO, 0x331a, &mmGDS_VMID13_BASE[0], sizeof(mmGDS_VMID13_BASE)/sizeof(mmGDS_VMID13_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID13_SIZE", REG_MMIO, 0x331b, &mmGDS_VMID13_SIZE[0], sizeof(mmGDS_VMID13_SIZE)/sizeof(mmGDS_VMID13_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID14_BASE", REG_MMIO, 0x331c, &mmGDS_VMID14_BASE[0], sizeof(mmGDS_VMID14_BASE)/sizeof(mmGDS_VMID14_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID14_SIZE", REG_MMIO, 0x331d, &mmGDS_VMID14_SIZE[0], sizeof(mmGDS_VMID14_SIZE)/sizeof(mmGDS_VMID14_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID15_BASE", REG_MMIO, 0x331e, &mmGDS_VMID15_BASE[0], sizeof(mmGDS_VMID15_BASE)/sizeof(mmGDS_VMID15_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID15_SIZE", REG_MMIO, 0x331f, &mmGDS_VMID15_SIZE[0], sizeof(mmGDS_VMID15_SIZE)/sizeof(mmGDS_VMID15_SIZE[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID0", REG_MMIO, 0x3320, &mmGDS_GWS_VMID0[0], sizeof(mmGDS_GWS_VMID0)/sizeof(mmGDS_GWS_VMID0[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID1", REG_MMIO, 0x3321, &mmGDS_GWS_VMID1[0], sizeof(mmGDS_GWS_VMID1)/sizeof(mmGDS_GWS_VMID1[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID2", REG_MMIO, 0x3322, &mmGDS_GWS_VMID2[0], sizeof(mmGDS_GWS_VMID2)/sizeof(mmGDS_GWS_VMID2[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID3", REG_MMIO, 0x3323, &mmGDS_GWS_VMID3[0], sizeof(mmGDS_GWS_VMID3)/sizeof(mmGDS_GWS_VMID3[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID4", REG_MMIO, 0x3324, &mmGDS_GWS_VMID4[0], sizeof(mmGDS_GWS_VMID4)/sizeof(mmGDS_GWS_VMID4[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID5", REG_MMIO, 0x3325, &mmGDS_GWS_VMID5[0], sizeof(mmGDS_GWS_VMID5)/sizeof(mmGDS_GWS_VMID5[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID6", REG_MMIO, 0x3326, &mmGDS_GWS_VMID6[0], sizeof(mmGDS_GWS_VMID6)/sizeof(mmGDS_GWS_VMID6[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID7", REG_MMIO, 0x3327, &mmGDS_GWS_VMID7[0], sizeof(mmGDS_GWS_VMID7)/sizeof(mmGDS_GWS_VMID7[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID8", REG_MMIO, 0x3328, &mmGDS_GWS_VMID8[0], sizeof(mmGDS_GWS_VMID8)/sizeof(mmGDS_GWS_VMID8[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID9", REG_MMIO, 0x3329, &mmGDS_GWS_VMID9[0], sizeof(mmGDS_GWS_VMID9)/sizeof(mmGDS_GWS_VMID9[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID10", REG_MMIO, 0x332a, &mmGDS_GWS_VMID10[0], sizeof(mmGDS_GWS_VMID10)/sizeof(mmGDS_GWS_VMID10[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID11", REG_MMIO, 0x332b, &mmGDS_GWS_VMID11[0], sizeof(mmGDS_GWS_VMID11)/sizeof(mmGDS_GWS_VMID11[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID12", REG_MMIO, 0x332c, &mmGDS_GWS_VMID12[0], sizeof(mmGDS_GWS_VMID12)/sizeof(mmGDS_GWS_VMID12[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID13", REG_MMIO, 0x332d, &mmGDS_GWS_VMID13[0], sizeof(mmGDS_GWS_VMID13)/sizeof(mmGDS_GWS_VMID13[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID14", REG_MMIO, 0x332e, &mmGDS_GWS_VMID14[0], sizeof(mmGDS_GWS_VMID14)/sizeof(mmGDS_GWS_VMID14[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID15", REG_MMIO, 0x332f, &mmGDS_GWS_VMID15[0], sizeof(mmGDS_GWS_VMID15)/sizeof(mmGDS_GWS_VMID15[0]), 0, 0 },
+	{ "mmGDS_OA_VMID0", REG_MMIO, 0x3330, &mmGDS_OA_VMID0[0], sizeof(mmGDS_OA_VMID0)/sizeof(mmGDS_OA_VMID0[0]), 0, 0 },
+	{ "mmGDS_OA_VMID1", REG_MMIO, 0x3331, &mmGDS_OA_VMID1[0], sizeof(mmGDS_OA_VMID1)/sizeof(mmGDS_OA_VMID1[0]), 0, 0 },
+	{ "mmGDS_OA_VMID2", REG_MMIO, 0x3332, &mmGDS_OA_VMID2[0], sizeof(mmGDS_OA_VMID2)/sizeof(mmGDS_OA_VMID2[0]), 0, 0 },
+	{ "mmGDS_OA_VMID3", REG_MMIO, 0x3333, &mmGDS_OA_VMID3[0], sizeof(mmGDS_OA_VMID3)/sizeof(mmGDS_OA_VMID3[0]), 0, 0 },
+	{ "mmGDS_OA_VMID4", REG_MMIO, 0x3334, &mmGDS_OA_VMID4[0], sizeof(mmGDS_OA_VMID4)/sizeof(mmGDS_OA_VMID4[0]), 0, 0 },
+	{ "mmGDS_OA_VMID5", REG_MMIO, 0x3335, &mmGDS_OA_VMID5[0], sizeof(mmGDS_OA_VMID5)/sizeof(mmGDS_OA_VMID5[0]), 0, 0 },
+	{ "mmGDS_OA_VMID6", REG_MMIO, 0x3336, &mmGDS_OA_VMID6[0], sizeof(mmGDS_OA_VMID6)/sizeof(mmGDS_OA_VMID6[0]), 0, 0 },
+	{ "mmGDS_OA_VMID7", REG_MMIO, 0x3337, &mmGDS_OA_VMID7[0], sizeof(mmGDS_OA_VMID7)/sizeof(mmGDS_OA_VMID7[0]), 0, 0 },
+	{ "mmGDS_OA_VMID8", REG_MMIO, 0x3338, &mmGDS_OA_VMID8[0], sizeof(mmGDS_OA_VMID8)/sizeof(mmGDS_OA_VMID8[0]), 0, 0 },
+	{ "mmGDS_OA_VMID9", REG_MMIO, 0x3339, &mmGDS_OA_VMID9[0], sizeof(mmGDS_OA_VMID9)/sizeof(mmGDS_OA_VMID9[0]), 0, 0 },
+	{ "mmGDS_OA_VMID10", REG_MMIO, 0x333a, &mmGDS_OA_VMID10[0], sizeof(mmGDS_OA_VMID10)/sizeof(mmGDS_OA_VMID10[0]), 0, 0 },
+	{ "mmGDS_OA_VMID11", REG_MMIO, 0x333b, &mmGDS_OA_VMID11[0], sizeof(mmGDS_OA_VMID11)/sizeof(mmGDS_OA_VMID11[0]), 0, 0 },
+	{ "mmGDS_OA_VMID12", REG_MMIO, 0x333c, &mmGDS_OA_VMID12[0], sizeof(mmGDS_OA_VMID12)/sizeof(mmGDS_OA_VMID12[0]), 0, 0 },
+	{ "mmGDS_OA_VMID13", REG_MMIO, 0x333d, &mmGDS_OA_VMID13[0], sizeof(mmGDS_OA_VMID13)/sizeof(mmGDS_OA_VMID13[0]), 0, 0 },
+	{ "mmGDS_OA_VMID14", REG_MMIO, 0x333e, &mmGDS_OA_VMID14[0], sizeof(mmGDS_OA_VMID14)/sizeof(mmGDS_OA_VMID14[0]), 0, 0 },
+	{ "mmGDS_OA_VMID15", REG_MMIO, 0x333f, &mmGDS_OA_VMID15[0], sizeof(mmGDS_OA_VMID15)/sizeof(mmGDS_OA_VMID15[0]), 0, 0 },
+	{ "mmGDS_GWS_RESET0", REG_MMIO, 0x3344, &mmGDS_GWS_RESET0[0], sizeof(mmGDS_GWS_RESET0)/sizeof(mmGDS_GWS_RESET0[0]), 0, 0 },
+	{ "mmGDS_GWS_RESET1", REG_MMIO, 0x3345, &mmGDS_GWS_RESET1[0], sizeof(mmGDS_GWS_RESET1)/sizeof(mmGDS_GWS_RESET1[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_RESET", REG_MMIO, 0x3346, &mmGDS_GWS_RESOURCE_RESET[0], sizeof(mmGDS_GWS_RESOURCE_RESET)/sizeof(mmGDS_GWS_RESOURCE_RESET[0]), 0, 0 },
+	{ "mmGDS_COMPUTE_MAX_WAVE_ID", REG_MMIO, 0x3348, &mmGDS_COMPUTE_MAX_WAVE_ID[0], sizeof(mmGDS_COMPUTE_MAX_WAVE_ID)/sizeof(mmGDS_COMPUTE_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmGDS_OA_RESET_MASK", REG_MMIO, 0x3349, &mmGDS_OA_RESET_MASK[0], sizeof(mmGDS_OA_RESET_MASK)/sizeof(mmGDS_OA_RESET_MASK[0]), 0, 0 },
+	{ "mmGDS_OA_RESET", REG_MMIO, 0x334a, &mmGDS_OA_RESET[0], sizeof(mmGDS_OA_RESET)/sizeof(mmGDS_OA_RESET[0]), 0, 0 },
+	{ "mmGDS_ENHANCE", REG_MMIO, 0x334b, &mmGDS_ENHANCE[0], sizeof(mmGDS_ENHANCE)/sizeof(mmGDS_ENHANCE[0]), 0, 0 },
+	{ "mmGDS_OA_CGPG_RESTORE", REG_MMIO, 0x334c, &mmGDS_OA_CGPG_RESTORE[0], sizeof(mmGDS_OA_CGPG_RESTORE)/sizeof(mmGDS_OA_CGPG_RESTORE[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_CONTROL", REG_MMIO, 0x3380, &mmRAS_SIGNATURE_CONTROL[0], sizeof(mmRAS_SIGNATURE_CONTROL)/sizeof(mmRAS_SIGNATURE_CONTROL[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_MASK", REG_MMIO, 0x3381, &mmRAS_SIGNATURE_MASK[0], sizeof(mmRAS_SIGNATURE_MASK)/sizeof(mmRAS_SIGNATURE_MASK[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE0", REG_MMIO, 0x3382, &mmRAS_SX_SIGNATURE0[0], sizeof(mmRAS_SX_SIGNATURE0)/sizeof(mmRAS_SX_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE1", REG_MMIO, 0x3383, &mmRAS_SX_SIGNATURE1[0], sizeof(mmRAS_SX_SIGNATURE1)/sizeof(mmRAS_SX_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE2", REG_MMIO, 0x3384, &mmRAS_SX_SIGNATURE2[0], sizeof(mmRAS_SX_SIGNATURE2)/sizeof(mmRAS_SX_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE3", REG_MMIO, 0x3385, &mmRAS_SX_SIGNATURE3[0], sizeof(mmRAS_SX_SIGNATURE3)/sizeof(mmRAS_SX_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_DB_SIGNATURE0", REG_MMIO, 0x338b, &mmRAS_DB_SIGNATURE0[0], sizeof(mmRAS_DB_SIGNATURE0)/sizeof(mmRAS_DB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_PA_SIGNATURE0", REG_MMIO, 0x338c, &mmRAS_PA_SIGNATURE0[0], sizeof(mmRAS_PA_SIGNATURE0)/sizeof(mmRAS_PA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_VGT_SIGNATURE0", REG_MMIO, 0x338d, &mmRAS_VGT_SIGNATURE0[0], sizeof(mmRAS_VGT_SIGNATURE0)/sizeof(mmRAS_VGT_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SQ_SIGNATURE0", REG_MMIO, 0x338e, &mmRAS_SQ_SIGNATURE0[0], sizeof(mmRAS_SQ_SIGNATURE0)/sizeof(mmRAS_SQ_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE0", REG_MMIO, 0x338f, &mmRAS_SC_SIGNATURE0[0], sizeof(mmRAS_SC_SIGNATURE0)/sizeof(mmRAS_SC_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE1", REG_MMIO, 0x3390, &mmRAS_SC_SIGNATURE1[0], sizeof(mmRAS_SC_SIGNATURE1)/sizeof(mmRAS_SC_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE2", REG_MMIO, 0x3391, &mmRAS_SC_SIGNATURE2[0], sizeof(mmRAS_SC_SIGNATURE2)/sizeof(mmRAS_SC_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE3", REG_MMIO, 0x3392, &mmRAS_SC_SIGNATURE3[0], sizeof(mmRAS_SC_SIGNATURE3)/sizeof(mmRAS_SC_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE4", REG_MMIO, 0x3393, &mmRAS_SC_SIGNATURE4[0], sizeof(mmRAS_SC_SIGNATURE4)/sizeof(mmRAS_SC_SIGNATURE4[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE5", REG_MMIO, 0x3394, &mmRAS_SC_SIGNATURE5[0], sizeof(mmRAS_SC_SIGNATURE5)/sizeof(mmRAS_SC_SIGNATURE5[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE6", REG_MMIO, 0x3395, &mmRAS_SC_SIGNATURE6[0], sizeof(mmRAS_SC_SIGNATURE6)/sizeof(mmRAS_SC_SIGNATURE6[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE7", REG_MMIO, 0x3396, &mmRAS_SC_SIGNATURE7[0], sizeof(mmRAS_SC_SIGNATURE7)/sizeof(mmRAS_SC_SIGNATURE7[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE0", REG_MMIO, 0x3397, &mmRAS_IA_SIGNATURE0[0], sizeof(mmRAS_IA_SIGNATURE0)/sizeof(mmRAS_IA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE1", REG_MMIO, 0x3398, &mmRAS_IA_SIGNATURE1[0], sizeof(mmRAS_IA_SIGNATURE1)/sizeof(mmRAS_IA_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE0", REG_MMIO, 0x3399, &mmRAS_SPI_SIGNATURE0[0], sizeof(mmRAS_SPI_SIGNATURE0)/sizeof(mmRAS_SPI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE1", REG_MMIO, 0x339a, &mmRAS_SPI_SIGNATURE1[0], sizeof(mmRAS_SPI_SIGNATURE1)/sizeof(mmRAS_SPI_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_TA_SIGNATURE0", REG_MMIO, 0x339b, &mmRAS_TA_SIGNATURE0[0], sizeof(mmRAS_TA_SIGNATURE0)/sizeof(mmRAS_TA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_TD_SIGNATURE0", REG_MMIO, 0x339c, &mmRAS_TD_SIGNATURE0[0], sizeof(mmRAS_TD_SIGNATURE0)/sizeof(mmRAS_TD_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_CB_SIGNATURE0", REG_MMIO, 0x339d, &mmRAS_CB_SIGNATURE0[0], sizeof(mmRAS_CB_SIGNATURE0)/sizeof(mmRAS_CB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE0", REG_MMIO, 0x339e, &mmRAS_BCI_SIGNATURE0[0], sizeof(mmRAS_BCI_SIGNATURE0)/sizeof(mmRAS_BCI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE1", REG_MMIO, 0x339f, &mmRAS_BCI_SIGNATURE1[0], sizeof(mmRAS_BCI_SIGNATURE1)/sizeof(mmRAS_BCI_SIGNATURE1[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG04", REG_SMC, 0x4, &ixCLIPPER_DEBUG_REG04[0], sizeof(ixCLIPPER_DEBUG_REG04)/sizeof(ixCLIPPER_DEBUG_REG04[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG4", REG_SMC, 0x4, &ixGDS_DEBUG_REG4[0], sizeof(ixGDS_DEBUG_REG4)/sizeof(ixGDS_DEBUG_REG4[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG4", REG_SMC, 0x4, &ixWD_DEBUG_REG4[0], sizeof(ixWD_DEBUG_REG4)/sizeof(ixWD_DEBUG_REG4[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL0", REG_SMC, 0x40, &ixDIDT_TD_CTRL0[0], sizeof(ixDIDT_TD_CTRL0)/sizeof(ixDIDT_TD_CTRL0[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL1", REG_SMC, 0x41, &ixDIDT_TD_CTRL1[0], sizeof(ixDIDT_TD_CTRL1)/sizeof(ixDIDT_TD_CTRL1[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL2", REG_SMC, 0x42, &ixDIDT_TD_CTRL2[0], sizeof(ixDIDT_TD_CTRL2)/sizeof(ixDIDT_TD_CTRL2[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG05", REG_SMC, 0x5, &ixCLIPPER_DEBUG_REG05[0], sizeof(ixCLIPPER_DEBUG_REG05)/sizeof(ixCLIPPER_DEBUG_REG05[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG5", REG_SMC, 0x5, &ixGDS_DEBUG_REG5[0], sizeof(ixGDS_DEBUG_REG5)/sizeof(ixGDS_DEBUG_REG5[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG5", REG_SMC, 0x5, &ixWD_DEBUG_REG5[0], sizeof(ixWD_DEBUG_REG5)/sizeof(ixWD_DEBUG_REG5[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT0_3", REG_SMC, 0x50, &ixDIDT_TD_WEIGHT0_3[0], sizeof(ixDIDT_TD_WEIGHT0_3)/sizeof(ixDIDT_TD_WEIGHT0_3[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT4_7", REG_SMC, 0x51, &ixDIDT_TD_WEIGHT4_7[0], sizeof(ixDIDT_TD_WEIGHT4_7)/sizeof(ixDIDT_TD_WEIGHT4_7[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT8_11", REG_SMC, 0x52, &ixDIDT_TD_WEIGHT8_11[0], sizeof(ixDIDT_TD_WEIGHT8_11)/sizeof(ixDIDT_TD_WEIGHT8_11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG06", REG_SMC, 0x6, &ixCLIPPER_DEBUG_REG06[0], sizeof(ixCLIPPER_DEBUG_REG06)/sizeof(ixCLIPPER_DEBUG_REG06[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG6", REG_SMC, 0x6, &ixGDS_DEBUG_REG6[0], sizeof(ixGDS_DEBUG_REG6)/sizeof(ixGDS_DEBUG_REG6[0]), 0, 0 },
+	{ "ixIA_DEBUG_REG6", REG_SMC, 0x6, &ixIA_DEBUG_REG6[0], sizeof(ixIA_DEBUG_REG6)/sizeof(ixIA_DEBUG_REG6[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL0", REG_SMC, 0x60, &ixDIDT_TCP_CTRL0[0], sizeof(ixDIDT_TCP_CTRL0)/sizeof(ixDIDT_TCP_CTRL0[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL1", REG_SMC, 0x61, &ixDIDT_TCP_CTRL1[0], sizeof(ixDIDT_TCP_CTRL1)/sizeof(ixDIDT_TCP_CTRL1[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL2", REG_SMC, 0x62, &ixDIDT_TCP_CTRL2[0], sizeof(ixDIDT_TCP_CTRL2)/sizeof(ixDIDT_TCP_CTRL2[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG07", REG_SMC, 0x7, &ixCLIPPER_DEBUG_REG07[0], sizeof(ixCLIPPER_DEBUG_REG07)/sizeof(ixCLIPPER_DEBUG_REG07[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG18", REG_SMC, 0x7, &ixVGT_DEBUG_REG18[0], sizeof(ixVGT_DEBUG_REG18)/sizeof(ixVGT_DEBUG_REG18[0]), 0, 0 },
+	{ "ixIA_DEBUG_REG7", REG_SMC, 0x7, &ixIA_DEBUG_REG7[0], sizeof(ixIA_DEBUG_REG7)/sizeof(ixIA_DEBUG_REG7[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT0_3", REG_SMC, 0x70, &ixDIDT_TCP_WEIGHT0_3[0], sizeof(ixDIDT_TCP_WEIGHT0_3)/sizeof(ixDIDT_TCP_WEIGHT0_3[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT4_7", REG_SMC, 0x71, &ixDIDT_TCP_WEIGHT4_7[0], sizeof(ixDIDT_TCP_WEIGHT4_7)/sizeof(ixDIDT_TCP_WEIGHT4_7[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT8_11", REG_SMC, 0x72, &ixDIDT_TCP_WEIGHT8_11[0], sizeof(ixDIDT_TCP_WEIGHT8_11)/sizeof(ixDIDT_TCP_WEIGHT8_11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG08", REG_SMC, 0x8, &ixCLIPPER_DEBUG_REG08[0], sizeof(ixCLIPPER_DEBUG_REG08)/sizeof(ixCLIPPER_DEBUG_REG08[0]), 0, 0 },
+	{ "ixSQ_DEBUG_STS_LOCAL", REG_SMC, 0x8, &ixSQ_DEBUG_STS_LOCAL[0], sizeof(ixSQ_DEBUG_STS_LOCAL)/sizeof(ixSQ_DEBUG_STS_LOCAL[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG8", REG_SMC, 0x8, &ixVGT_DEBUG_REG8[0], sizeof(ixVGT_DEBUG_REG8)/sizeof(ixVGT_DEBUG_REG8[0]), 0, 0 },
+	{ "ixIA_DEBUG_REG8", REG_SMC, 0x8, &ixIA_DEBUG_REG8[0], sizeof(ixIA_DEBUG_REG8)/sizeof(ixIA_DEBUG_REG8[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG09", REG_SMC, 0x9, &ixCLIPPER_DEBUG_REG09[0], sizeof(ixCLIPPER_DEBUG_REG09)/sizeof(ixCLIPPER_DEBUG_REG09[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG9", REG_SMC, 0x9, &ixVGT_DEBUG_REG9[0], sizeof(ixVGT_DEBUG_REG9)/sizeof(ixVGT_DEBUG_REG9[0]), 0, 0 },
+	{ "ixIA_DEBUG_REG9", REG_SMC, 0x9, &ixIA_DEBUG_REG9[0], sizeof(ixIA_DEBUG_REG9)/sizeof(ixIA_DEBUG_REG9[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG10", REG_SMC, 0xa, &ixCLIPPER_DEBUG_REG10[0], sizeof(ixCLIPPER_DEBUG_REG10)/sizeof(ixCLIPPER_DEBUG_REG10[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG10", REG_SMC, 0xa, &ixVGT_DEBUG_REG10[0], sizeof(ixVGT_DEBUG_REG10)/sizeof(ixVGT_DEBUG_REG10[0]), 0, 0 },
+	{ "mmDB_RENDER_CONTROL", REG_MMIO, 0xa000, &mmDB_RENDER_CONTROL[0], sizeof(mmDB_RENDER_CONTROL)/sizeof(mmDB_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmDB_COUNT_CONTROL", REG_MMIO, 0xa001, &mmDB_COUNT_CONTROL[0], sizeof(mmDB_COUNT_CONTROL)/sizeof(mmDB_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmDB_DEPTH_VIEW", REG_MMIO, 0xa002, &mmDB_DEPTH_VIEW[0], sizeof(mmDB_DEPTH_VIEW)/sizeof(mmDB_DEPTH_VIEW[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE", REG_MMIO, 0xa003, &mmDB_RENDER_OVERRIDE[0], sizeof(mmDB_RENDER_OVERRIDE)/sizeof(mmDB_RENDER_OVERRIDE[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE2", REG_MMIO, 0xa004, &mmDB_RENDER_OVERRIDE2[0], sizeof(mmDB_RENDER_OVERRIDE2)/sizeof(mmDB_RENDER_OVERRIDE2[0]), 0, 0 },
+	{ "mmDB_HTILE_DATA_BASE", REG_MMIO, 0xa005, &mmDB_HTILE_DATA_BASE[0], sizeof(mmDB_HTILE_DATA_BASE)/sizeof(mmDB_HTILE_DATA_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MIN", REG_MMIO, 0xa008, &mmDB_DEPTH_BOUNDS_MIN[0], sizeof(mmDB_DEPTH_BOUNDS_MIN)/sizeof(mmDB_DEPTH_BOUNDS_MIN[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MAX", REG_MMIO, 0xa009, &mmDB_DEPTH_BOUNDS_MAX[0], sizeof(mmDB_DEPTH_BOUNDS_MAX)/sizeof(mmDB_DEPTH_BOUNDS_MAX[0]), 0, 0 },
+	{ "mmDB_STENCIL_CLEAR", REG_MMIO, 0xa00a, &mmDB_STENCIL_CLEAR[0], sizeof(mmDB_STENCIL_CLEAR)/sizeof(mmDB_STENCIL_CLEAR[0]), 0, 0 },
+	{ "mmDB_DEPTH_CLEAR", REG_MMIO, 0xa00b, &mmDB_DEPTH_CLEAR[0], sizeof(mmDB_DEPTH_CLEAR)/sizeof(mmDB_DEPTH_CLEAR[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_TL", REG_MMIO, 0xa00c, &mmPA_SC_SCREEN_SCISSOR_TL[0], sizeof(mmPA_SC_SCREEN_SCISSOR_TL)/sizeof(mmPA_SC_SCREEN_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_BR", REG_MMIO, 0xa00d, &mmPA_SC_SCREEN_SCISSOR_BR[0], sizeof(mmPA_SC_SCREEN_SCISSOR_BR)/sizeof(mmPA_SC_SCREEN_SCISSOR_BR[0]), 0, 0 },
+	{ "mmDB_DEPTH_INFO", REG_MMIO, 0xa00f, &mmDB_DEPTH_INFO[0], sizeof(mmDB_DEPTH_INFO)/sizeof(mmDB_DEPTH_INFO[0]), 0, 0 },
+	{ "mmDB_Z_INFO", REG_MMIO, 0xa010, &mmDB_Z_INFO[0], sizeof(mmDB_Z_INFO)/sizeof(mmDB_Z_INFO[0]), 0, 0 },
+	{ "mmDB_STENCIL_INFO", REG_MMIO, 0xa011, &mmDB_STENCIL_INFO[0], sizeof(mmDB_STENCIL_INFO)/sizeof(mmDB_STENCIL_INFO[0]), 0, 0 },
+	{ "mmDB_Z_READ_BASE", REG_MMIO, 0xa012, &mmDB_Z_READ_BASE[0], sizeof(mmDB_Z_READ_BASE)/sizeof(mmDB_Z_READ_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_READ_BASE", REG_MMIO, 0xa013, &mmDB_STENCIL_READ_BASE[0], sizeof(mmDB_STENCIL_READ_BASE)/sizeof(mmDB_STENCIL_READ_BASE[0]), 0, 0 },
+	{ "mmDB_Z_WRITE_BASE", REG_MMIO, 0xa014, &mmDB_Z_WRITE_BASE[0], sizeof(mmDB_Z_WRITE_BASE)/sizeof(mmDB_Z_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_WRITE_BASE", REG_MMIO, 0xa015, &mmDB_STENCIL_WRITE_BASE[0], sizeof(mmDB_STENCIL_WRITE_BASE)/sizeof(mmDB_STENCIL_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SIZE", REG_MMIO, 0xa016, &mmDB_DEPTH_SIZE[0], sizeof(mmDB_DEPTH_SIZE)/sizeof(mmDB_DEPTH_SIZE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SLICE", REG_MMIO, 0xa017, &mmDB_DEPTH_SLICE[0], sizeof(mmDB_DEPTH_SLICE)/sizeof(mmDB_DEPTH_SLICE[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR", REG_MMIO, 0xa020, &mmTA_BC_BASE_ADDR[0], sizeof(mmTA_BC_BASE_ADDR)/sizeof(mmTA_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR_HI", REG_MMIO, 0xa021, &mmTA_BC_BASE_ADDR_HI[0], sizeof(mmTA_BC_BASE_ADDR_HI)/sizeof(mmTA_BC_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_0", REG_MMIO, 0xa07a, &mmCOHER_DEST_BASE_HI_0[0], sizeof(mmCOHER_DEST_BASE_HI_0)/sizeof(mmCOHER_DEST_BASE_HI_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_1", REG_MMIO, 0xa07b, &mmCOHER_DEST_BASE_HI_1[0], sizeof(mmCOHER_DEST_BASE_HI_1)/sizeof(mmCOHER_DEST_BASE_HI_1[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_2", REG_MMIO, 0xa07c, &mmCOHER_DEST_BASE_HI_2[0], sizeof(mmCOHER_DEST_BASE_HI_2)/sizeof(mmCOHER_DEST_BASE_HI_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_3", REG_MMIO, 0xa07d, &mmCOHER_DEST_BASE_HI_3[0], sizeof(mmCOHER_DEST_BASE_HI_3)/sizeof(mmCOHER_DEST_BASE_HI_3[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_2", REG_MMIO, 0xa07e, &mmCOHER_DEST_BASE_2[0], sizeof(mmCOHER_DEST_BASE_2)/sizeof(mmCOHER_DEST_BASE_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_3", REG_MMIO, 0xa07f, &mmCOHER_DEST_BASE_3[0], sizeof(mmCOHER_DEST_BASE_3)/sizeof(mmCOHER_DEST_BASE_3[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_OFFSET", REG_MMIO, 0xa080, &mmPA_SC_WINDOW_OFFSET[0], sizeof(mmPA_SC_WINDOW_OFFSET)/sizeof(mmPA_SC_WINDOW_OFFSET[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_TL", REG_MMIO, 0xa081, &mmPA_SC_WINDOW_SCISSOR_TL[0], sizeof(mmPA_SC_WINDOW_SCISSOR_TL)/sizeof(mmPA_SC_WINDOW_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_BR", REG_MMIO, 0xa082, &mmPA_SC_WINDOW_SCISSOR_BR[0], sizeof(mmPA_SC_WINDOW_SCISSOR_BR)/sizeof(mmPA_SC_WINDOW_SCISSOR_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_RULE", REG_MMIO, 0xa083, &mmPA_SC_CLIPRECT_RULE[0], sizeof(mmPA_SC_CLIPRECT_RULE)/sizeof(mmPA_SC_CLIPRECT_RULE[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_TL", REG_MMIO, 0xa084, &mmPA_SC_CLIPRECT_0_TL[0], sizeof(mmPA_SC_CLIPRECT_0_TL)/sizeof(mmPA_SC_CLIPRECT_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_BR", REG_MMIO, 0xa085, &mmPA_SC_CLIPRECT_0_BR[0], sizeof(mmPA_SC_CLIPRECT_0_BR)/sizeof(mmPA_SC_CLIPRECT_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_TL", REG_MMIO, 0xa086, &mmPA_SC_CLIPRECT_1_TL[0], sizeof(mmPA_SC_CLIPRECT_1_TL)/sizeof(mmPA_SC_CLIPRECT_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_BR", REG_MMIO, 0xa087, &mmPA_SC_CLIPRECT_1_BR[0], sizeof(mmPA_SC_CLIPRECT_1_BR)/sizeof(mmPA_SC_CLIPRECT_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_TL", REG_MMIO, 0xa088, &mmPA_SC_CLIPRECT_2_TL[0], sizeof(mmPA_SC_CLIPRECT_2_TL)/sizeof(mmPA_SC_CLIPRECT_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_BR", REG_MMIO, 0xa089, &mmPA_SC_CLIPRECT_2_BR[0], sizeof(mmPA_SC_CLIPRECT_2_BR)/sizeof(mmPA_SC_CLIPRECT_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_TL", REG_MMIO, 0xa08a, &mmPA_SC_CLIPRECT_3_TL[0], sizeof(mmPA_SC_CLIPRECT_3_TL)/sizeof(mmPA_SC_CLIPRECT_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_BR", REG_MMIO, 0xa08b, &mmPA_SC_CLIPRECT_3_BR[0], sizeof(mmPA_SC_CLIPRECT_3_BR)/sizeof(mmPA_SC_CLIPRECT_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_EDGERULE", REG_MMIO, 0xa08c, &mmPA_SC_EDGERULE[0], sizeof(mmPA_SC_EDGERULE)/sizeof(mmPA_SC_EDGERULE[0]), 0, 0 },
+	{ "mmPA_SU_HARDWARE_SCREEN_OFFSET", REG_MMIO, 0xa08d, &mmPA_SU_HARDWARE_SCREEN_OFFSET[0], sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET)/sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET[0]), 0, 0 },
+	{ "mmCB_TARGET_MASK", REG_MMIO, 0xa08e, &mmCB_TARGET_MASK[0], sizeof(mmCB_TARGET_MASK)/sizeof(mmCB_TARGET_MASK[0]), 0, 0 },
+	{ "mmCB_SHADER_MASK", REG_MMIO, 0xa08f, &mmCB_SHADER_MASK[0], sizeof(mmCB_SHADER_MASK)/sizeof(mmCB_SHADER_MASK[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_TL", REG_MMIO, 0xa090, &mmPA_SC_GENERIC_SCISSOR_TL[0], sizeof(mmPA_SC_GENERIC_SCISSOR_TL)/sizeof(mmPA_SC_GENERIC_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_BR", REG_MMIO, 0xa091, &mmPA_SC_GENERIC_SCISSOR_BR[0], sizeof(mmPA_SC_GENERIC_SCISSOR_BR)/sizeof(mmPA_SC_GENERIC_SCISSOR_BR[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_0", REG_MMIO, 0xa092, &mmCOHER_DEST_BASE_0[0], sizeof(mmCOHER_DEST_BASE_0)/sizeof(mmCOHER_DEST_BASE_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_1", REG_MMIO, 0xa093, &mmCOHER_DEST_BASE_1[0], sizeof(mmCOHER_DEST_BASE_1)/sizeof(mmCOHER_DEST_BASE_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_TL", REG_MMIO, 0xa094, &mmPA_SC_VPORT_SCISSOR_0_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_BR", REG_MMIO, 0xa095, &mmPA_SC_VPORT_SCISSOR_0_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_TL", REG_MMIO, 0xa096, &mmPA_SC_VPORT_SCISSOR_1_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_BR", REG_MMIO, 0xa097, &mmPA_SC_VPORT_SCISSOR_1_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_TL", REG_MMIO, 0xa098, &mmPA_SC_VPORT_SCISSOR_2_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_BR", REG_MMIO, 0xa099, &mmPA_SC_VPORT_SCISSOR_2_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_TL", REG_MMIO, 0xa09a, &mmPA_SC_VPORT_SCISSOR_3_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_BR", REG_MMIO, 0xa09b, &mmPA_SC_VPORT_SCISSOR_3_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_TL", REG_MMIO, 0xa09c, &mmPA_SC_VPORT_SCISSOR_4_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_4_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_BR", REG_MMIO, 0xa09d, &mmPA_SC_VPORT_SCISSOR_4_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_4_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_TL", REG_MMIO, 0xa09e, &mmPA_SC_VPORT_SCISSOR_5_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_5_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_BR", REG_MMIO, 0xa09f, &mmPA_SC_VPORT_SCISSOR_5_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_5_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_TL", REG_MMIO, 0xa0a0, &mmPA_SC_VPORT_SCISSOR_6_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_6_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_BR", REG_MMIO, 0xa0a1, &mmPA_SC_VPORT_SCISSOR_6_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_6_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_TL", REG_MMIO, 0xa0a2, &mmPA_SC_VPORT_SCISSOR_7_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_7_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_BR", REG_MMIO, 0xa0a3, &mmPA_SC_VPORT_SCISSOR_7_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_7_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_TL", REG_MMIO, 0xa0a4, &mmPA_SC_VPORT_SCISSOR_8_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_8_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_BR", REG_MMIO, 0xa0a5, &mmPA_SC_VPORT_SCISSOR_8_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_8_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_TL", REG_MMIO, 0xa0a6, &mmPA_SC_VPORT_SCISSOR_9_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_9_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_BR", REG_MMIO, 0xa0a7, &mmPA_SC_VPORT_SCISSOR_9_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_9_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_TL", REG_MMIO, 0xa0a8, &mmPA_SC_VPORT_SCISSOR_10_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_10_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_BR", REG_MMIO, 0xa0a9, &mmPA_SC_VPORT_SCISSOR_10_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_10_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_TL", REG_MMIO, 0xa0aa, &mmPA_SC_VPORT_SCISSOR_11_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_11_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_BR", REG_MMIO, 0xa0ab, &mmPA_SC_VPORT_SCISSOR_11_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_11_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_TL", REG_MMIO, 0xa0ac, &mmPA_SC_VPORT_SCISSOR_12_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_12_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_BR", REG_MMIO, 0xa0ad, &mmPA_SC_VPORT_SCISSOR_12_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_12_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_TL", REG_MMIO, 0xa0ae, &mmPA_SC_VPORT_SCISSOR_13_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_13_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_BR", REG_MMIO, 0xa0af, &mmPA_SC_VPORT_SCISSOR_13_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_13_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_TL", REG_MMIO, 0xa0b0, &mmPA_SC_VPORT_SCISSOR_14_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_14_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_BR", REG_MMIO, 0xa0b1, &mmPA_SC_VPORT_SCISSOR_14_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_14_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_TL", REG_MMIO, 0xa0b2, &mmPA_SC_VPORT_SCISSOR_15_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_15_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_BR", REG_MMIO, 0xa0b3, &mmPA_SC_VPORT_SCISSOR_15_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_15_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_0", REG_MMIO, 0xa0b4, &mmPA_SC_VPORT_ZMIN_0[0], sizeof(mmPA_SC_VPORT_ZMIN_0)/sizeof(mmPA_SC_VPORT_ZMIN_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_0", REG_MMIO, 0xa0b5, &mmPA_SC_VPORT_ZMAX_0[0], sizeof(mmPA_SC_VPORT_ZMAX_0)/sizeof(mmPA_SC_VPORT_ZMAX_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_1", REG_MMIO, 0xa0b6, &mmPA_SC_VPORT_ZMIN_1[0], sizeof(mmPA_SC_VPORT_ZMIN_1)/sizeof(mmPA_SC_VPORT_ZMIN_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_1", REG_MMIO, 0xa0b7, &mmPA_SC_VPORT_ZMAX_1[0], sizeof(mmPA_SC_VPORT_ZMAX_1)/sizeof(mmPA_SC_VPORT_ZMAX_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_2", REG_MMIO, 0xa0b8, &mmPA_SC_VPORT_ZMIN_2[0], sizeof(mmPA_SC_VPORT_ZMIN_2)/sizeof(mmPA_SC_VPORT_ZMIN_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_2", REG_MMIO, 0xa0b9, &mmPA_SC_VPORT_ZMAX_2[0], sizeof(mmPA_SC_VPORT_ZMAX_2)/sizeof(mmPA_SC_VPORT_ZMAX_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_3", REG_MMIO, 0xa0ba, &mmPA_SC_VPORT_ZMIN_3[0], sizeof(mmPA_SC_VPORT_ZMIN_3)/sizeof(mmPA_SC_VPORT_ZMIN_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_3", REG_MMIO, 0xa0bb, &mmPA_SC_VPORT_ZMAX_3[0], sizeof(mmPA_SC_VPORT_ZMAX_3)/sizeof(mmPA_SC_VPORT_ZMAX_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_4", REG_MMIO, 0xa0bc, &mmPA_SC_VPORT_ZMIN_4[0], sizeof(mmPA_SC_VPORT_ZMIN_4)/sizeof(mmPA_SC_VPORT_ZMIN_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_4", REG_MMIO, 0xa0bd, &mmPA_SC_VPORT_ZMAX_4[0], sizeof(mmPA_SC_VPORT_ZMAX_4)/sizeof(mmPA_SC_VPORT_ZMAX_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_5", REG_MMIO, 0xa0be, &mmPA_SC_VPORT_ZMIN_5[0], sizeof(mmPA_SC_VPORT_ZMIN_5)/sizeof(mmPA_SC_VPORT_ZMIN_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_5", REG_MMIO, 0xa0bf, &mmPA_SC_VPORT_ZMAX_5[0], sizeof(mmPA_SC_VPORT_ZMAX_5)/sizeof(mmPA_SC_VPORT_ZMAX_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_6", REG_MMIO, 0xa0c0, &mmPA_SC_VPORT_ZMIN_6[0], sizeof(mmPA_SC_VPORT_ZMIN_6)/sizeof(mmPA_SC_VPORT_ZMIN_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_6", REG_MMIO, 0xa0c1, &mmPA_SC_VPORT_ZMAX_6[0], sizeof(mmPA_SC_VPORT_ZMAX_6)/sizeof(mmPA_SC_VPORT_ZMAX_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_7", REG_MMIO, 0xa0c2, &mmPA_SC_VPORT_ZMIN_7[0], sizeof(mmPA_SC_VPORT_ZMIN_7)/sizeof(mmPA_SC_VPORT_ZMIN_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_7", REG_MMIO, 0xa0c3, &mmPA_SC_VPORT_ZMAX_7[0], sizeof(mmPA_SC_VPORT_ZMAX_7)/sizeof(mmPA_SC_VPORT_ZMAX_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_8", REG_MMIO, 0xa0c4, &mmPA_SC_VPORT_ZMIN_8[0], sizeof(mmPA_SC_VPORT_ZMIN_8)/sizeof(mmPA_SC_VPORT_ZMIN_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_8", REG_MMIO, 0xa0c5, &mmPA_SC_VPORT_ZMAX_8[0], sizeof(mmPA_SC_VPORT_ZMAX_8)/sizeof(mmPA_SC_VPORT_ZMAX_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_9", REG_MMIO, 0xa0c6, &mmPA_SC_VPORT_ZMIN_9[0], sizeof(mmPA_SC_VPORT_ZMIN_9)/sizeof(mmPA_SC_VPORT_ZMIN_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_9", REG_MMIO, 0xa0c7, &mmPA_SC_VPORT_ZMAX_9[0], sizeof(mmPA_SC_VPORT_ZMAX_9)/sizeof(mmPA_SC_VPORT_ZMAX_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_10", REG_MMIO, 0xa0c8, &mmPA_SC_VPORT_ZMIN_10[0], sizeof(mmPA_SC_VPORT_ZMIN_10)/sizeof(mmPA_SC_VPORT_ZMIN_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_10", REG_MMIO, 0xa0c9, &mmPA_SC_VPORT_ZMAX_10[0], sizeof(mmPA_SC_VPORT_ZMAX_10)/sizeof(mmPA_SC_VPORT_ZMAX_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_11", REG_MMIO, 0xa0ca, &mmPA_SC_VPORT_ZMIN_11[0], sizeof(mmPA_SC_VPORT_ZMIN_11)/sizeof(mmPA_SC_VPORT_ZMIN_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_11", REG_MMIO, 0xa0cb, &mmPA_SC_VPORT_ZMAX_11[0], sizeof(mmPA_SC_VPORT_ZMAX_11)/sizeof(mmPA_SC_VPORT_ZMAX_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_12", REG_MMIO, 0xa0cc, &mmPA_SC_VPORT_ZMIN_12[0], sizeof(mmPA_SC_VPORT_ZMIN_12)/sizeof(mmPA_SC_VPORT_ZMIN_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_12", REG_MMIO, 0xa0cd, &mmPA_SC_VPORT_ZMAX_12[0], sizeof(mmPA_SC_VPORT_ZMAX_12)/sizeof(mmPA_SC_VPORT_ZMAX_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_13", REG_MMIO, 0xa0ce, &mmPA_SC_VPORT_ZMIN_13[0], sizeof(mmPA_SC_VPORT_ZMIN_13)/sizeof(mmPA_SC_VPORT_ZMIN_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_13", REG_MMIO, 0xa0cf, &mmPA_SC_VPORT_ZMAX_13[0], sizeof(mmPA_SC_VPORT_ZMAX_13)/sizeof(mmPA_SC_VPORT_ZMAX_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_14", REG_MMIO, 0xa0d0, &mmPA_SC_VPORT_ZMIN_14[0], sizeof(mmPA_SC_VPORT_ZMIN_14)/sizeof(mmPA_SC_VPORT_ZMIN_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_14", REG_MMIO, 0xa0d1, &mmPA_SC_VPORT_ZMAX_14[0], sizeof(mmPA_SC_VPORT_ZMAX_14)/sizeof(mmPA_SC_VPORT_ZMAX_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_15", REG_MMIO, 0xa0d2, &mmPA_SC_VPORT_ZMIN_15[0], sizeof(mmPA_SC_VPORT_ZMIN_15)/sizeof(mmPA_SC_VPORT_ZMIN_15[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_15", REG_MMIO, 0xa0d3, &mmPA_SC_VPORT_ZMAX_15[0], sizeof(mmPA_SC_VPORT_ZMAX_15)/sizeof(mmPA_SC_VPORT_ZMAX_15[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG", REG_MMIO, 0xa0d4, &mmPA_SC_RASTER_CONFIG[0], sizeof(mmPA_SC_RASTER_CONFIG)/sizeof(mmPA_SC_RASTER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG_1", REG_MMIO, 0xa0d5, &mmPA_SC_RASTER_CONFIG_1[0], sizeof(mmPA_SC_RASTER_CONFIG_1)/sizeof(mmPA_SC_RASTER_CONFIG_1[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_CONTROL", REG_MMIO, 0xa0d6, &mmPA_SC_SCREEN_EXTENT_CONTROL[0], sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL)/sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTX_CNTL", REG_MMIO, 0xa0d8, &mmCP_PERFMON_CNTX_CNTL[0], sizeof(mmCP_PERFMON_CNTX_CNTL)/sizeof(mmCP_PERFMON_CNTX_CNTL[0]), 0, 0 },
+	{ "mmCP_RINGID", REG_MMIO, 0xa0d9, &mmCP_RINGID[0], sizeof(mmCP_RINGID)/sizeof(mmCP_RINGID[0]), 0, 0 },
+	{ "mmCP_VMID", REG_MMIO, 0xa0da, &mmCP_VMID[0], sizeof(mmCP_VMID)/sizeof(mmCP_VMID[0]), 0, 0 },
+	{ "mmVGT_MAX_VTX_INDX", REG_MMIO, 0xa100, &mmVGT_MAX_VTX_INDX[0], sizeof(mmVGT_MAX_VTX_INDX)/sizeof(mmVGT_MAX_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_MIN_VTX_INDX", REG_MMIO, 0xa101, &mmVGT_MIN_VTX_INDX[0], sizeof(mmVGT_MIN_VTX_INDX)/sizeof(mmVGT_MIN_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_INDX_OFFSET", REG_MMIO, 0xa102, &mmVGT_INDX_OFFSET[0], sizeof(mmVGT_INDX_OFFSET)/sizeof(mmVGT_INDX_OFFSET[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_INDX", REG_MMIO, 0xa103, &mmVGT_MULTI_PRIM_IB_RESET_INDX[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX[0]), 0, 0 },
+	{ "mmCB_BLEND_RED", REG_MMIO, 0xa105, &mmCB_BLEND_RED[0], sizeof(mmCB_BLEND_RED)/sizeof(mmCB_BLEND_RED[0]), 0, 0 },
+	{ "mmCB_BLEND_GREEN", REG_MMIO, 0xa106, &mmCB_BLEND_GREEN[0], sizeof(mmCB_BLEND_GREEN)/sizeof(mmCB_BLEND_GREEN[0]), 0, 0 },
+	{ "mmCB_BLEND_BLUE", REG_MMIO, 0xa107, &mmCB_BLEND_BLUE[0], sizeof(mmCB_BLEND_BLUE)/sizeof(mmCB_BLEND_BLUE[0]), 0, 0 },
+	{ "mmCB_BLEND_ALPHA", REG_MMIO, 0xa108, &mmCB_BLEND_ALPHA[0], sizeof(mmCB_BLEND_ALPHA)/sizeof(mmCB_BLEND_ALPHA[0]), 0, 0 },
+	{ "mmDB_STENCIL_CONTROL", REG_MMIO, 0xa10b, &mmDB_STENCIL_CONTROL[0], sizeof(mmDB_STENCIL_CONTROL)/sizeof(mmDB_STENCIL_CONTROL[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK", REG_MMIO, 0xa10c, &mmDB_STENCILREFMASK[0], sizeof(mmDB_STENCILREFMASK)/sizeof(mmDB_STENCILREFMASK[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK_BF", REG_MMIO, 0xa10d, &mmDB_STENCILREFMASK_BF[0], sizeof(mmDB_STENCILREFMASK_BF)/sizeof(mmDB_STENCILREFMASK_BF[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE", REG_MMIO, 0xa10f, &mmPA_CL_VPORT_XSCALE[0], sizeof(mmPA_CL_VPORT_XSCALE)/sizeof(mmPA_CL_VPORT_XSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET", REG_MMIO, 0xa110, &mmPA_CL_VPORT_XOFFSET[0], sizeof(mmPA_CL_VPORT_XOFFSET)/sizeof(mmPA_CL_VPORT_XOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE", REG_MMIO, 0xa111, &mmPA_CL_VPORT_YSCALE[0], sizeof(mmPA_CL_VPORT_YSCALE)/sizeof(mmPA_CL_VPORT_YSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET", REG_MMIO, 0xa112, &mmPA_CL_VPORT_YOFFSET[0], sizeof(mmPA_CL_VPORT_YOFFSET)/sizeof(mmPA_CL_VPORT_YOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE", REG_MMIO, 0xa113, &mmPA_CL_VPORT_ZSCALE[0], sizeof(mmPA_CL_VPORT_ZSCALE)/sizeof(mmPA_CL_VPORT_ZSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET", REG_MMIO, 0xa114, &mmPA_CL_VPORT_ZOFFSET[0], sizeof(mmPA_CL_VPORT_ZOFFSET)/sizeof(mmPA_CL_VPORT_ZOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_1", REG_MMIO, 0xa115, &mmPA_CL_VPORT_XSCALE_1[0], sizeof(mmPA_CL_VPORT_XSCALE_1)/sizeof(mmPA_CL_VPORT_XSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_1", REG_MMIO, 0xa116, &mmPA_CL_VPORT_XOFFSET_1[0], sizeof(mmPA_CL_VPORT_XOFFSET_1)/sizeof(mmPA_CL_VPORT_XOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_1", REG_MMIO, 0xa117, &mmPA_CL_VPORT_YSCALE_1[0], sizeof(mmPA_CL_VPORT_YSCALE_1)/sizeof(mmPA_CL_VPORT_YSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_1", REG_MMIO, 0xa118, &mmPA_CL_VPORT_YOFFSET_1[0], sizeof(mmPA_CL_VPORT_YOFFSET_1)/sizeof(mmPA_CL_VPORT_YOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_1", REG_MMIO, 0xa119, &mmPA_CL_VPORT_ZSCALE_1[0], sizeof(mmPA_CL_VPORT_ZSCALE_1)/sizeof(mmPA_CL_VPORT_ZSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_1", REG_MMIO, 0xa11a, &mmPA_CL_VPORT_ZOFFSET_1[0], sizeof(mmPA_CL_VPORT_ZOFFSET_1)/sizeof(mmPA_CL_VPORT_ZOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_2", REG_MMIO, 0xa11b, &mmPA_CL_VPORT_XSCALE_2[0], sizeof(mmPA_CL_VPORT_XSCALE_2)/sizeof(mmPA_CL_VPORT_XSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_2", REG_MMIO, 0xa11c, &mmPA_CL_VPORT_XOFFSET_2[0], sizeof(mmPA_CL_VPORT_XOFFSET_2)/sizeof(mmPA_CL_VPORT_XOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_2", REG_MMIO, 0xa11d, &mmPA_CL_VPORT_YSCALE_2[0], sizeof(mmPA_CL_VPORT_YSCALE_2)/sizeof(mmPA_CL_VPORT_YSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_2", REG_MMIO, 0xa11e, &mmPA_CL_VPORT_YOFFSET_2[0], sizeof(mmPA_CL_VPORT_YOFFSET_2)/sizeof(mmPA_CL_VPORT_YOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_2", REG_MMIO, 0xa11f, &mmPA_CL_VPORT_ZSCALE_2[0], sizeof(mmPA_CL_VPORT_ZSCALE_2)/sizeof(mmPA_CL_VPORT_ZSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_2", REG_MMIO, 0xa120, &mmPA_CL_VPORT_ZOFFSET_2[0], sizeof(mmPA_CL_VPORT_ZOFFSET_2)/sizeof(mmPA_CL_VPORT_ZOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_3", REG_MMIO, 0xa121, &mmPA_CL_VPORT_XSCALE_3[0], sizeof(mmPA_CL_VPORT_XSCALE_3)/sizeof(mmPA_CL_VPORT_XSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_3", REG_MMIO, 0xa122, &mmPA_CL_VPORT_XOFFSET_3[0], sizeof(mmPA_CL_VPORT_XOFFSET_3)/sizeof(mmPA_CL_VPORT_XOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_3", REG_MMIO, 0xa123, &mmPA_CL_VPORT_YSCALE_3[0], sizeof(mmPA_CL_VPORT_YSCALE_3)/sizeof(mmPA_CL_VPORT_YSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_3", REG_MMIO, 0xa124, &mmPA_CL_VPORT_YOFFSET_3[0], sizeof(mmPA_CL_VPORT_YOFFSET_3)/sizeof(mmPA_CL_VPORT_YOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_3", REG_MMIO, 0xa125, &mmPA_CL_VPORT_ZSCALE_3[0], sizeof(mmPA_CL_VPORT_ZSCALE_3)/sizeof(mmPA_CL_VPORT_ZSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_3", REG_MMIO, 0xa126, &mmPA_CL_VPORT_ZOFFSET_3[0], sizeof(mmPA_CL_VPORT_ZOFFSET_3)/sizeof(mmPA_CL_VPORT_ZOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_4", REG_MMIO, 0xa127, &mmPA_CL_VPORT_XSCALE_4[0], sizeof(mmPA_CL_VPORT_XSCALE_4)/sizeof(mmPA_CL_VPORT_XSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_4", REG_MMIO, 0xa128, &mmPA_CL_VPORT_XOFFSET_4[0], sizeof(mmPA_CL_VPORT_XOFFSET_4)/sizeof(mmPA_CL_VPORT_XOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_4", REG_MMIO, 0xa129, &mmPA_CL_VPORT_YSCALE_4[0], sizeof(mmPA_CL_VPORT_YSCALE_4)/sizeof(mmPA_CL_VPORT_YSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_4", REG_MMIO, 0xa12a, &mmPA_CL_VPORT_YOFFSET_4[0], sizeof(mmPA_CL_VPORT_YOFFSET_4)/sizeof(mmPA_CL_VPORT_YOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_4", REG_MMIO, 0xa12b, &mmPA_CL_VPORT_ZSCALE_4[0], sizeof(mmPA_CL_VPORT_ZSCALE_4)/sizeof(mmPA_CL_VPORT_ZSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_4", REG_MMIO, 0xa12c, &mmPA_CL_VPORT_ZOFFSET_4[0], sizeof(mmPA_CL_VPORT_ZOFFSET_4)/sizeof(mmPA_CL_VPORT_ZOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_5", REG_MMIO, 0xa12d, &mmPA_CL_VPORT_XSCALE_5[0], sizeof(mmPA_CL_VPORT_XSCALE_5)/sizeof(mmPA_CL_VPORT_XSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_5", REG_MMIO, 0xa12e, &mmPA_CL_VPORT_XOFFSET_5[0], sizeof(mmPA_CL_VPORT_XOFFSET_5)/sizeof(mmPA_CL_VPORT_XOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_5", REG_MMIO, 0xa12f, &mmPA_CL_VPORT_YSCALE_5[0], sizeof(mmPA_CL_VPORT_YSCALE_5)/sizeof(mmPA_CL_VPORT_YSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_5", REG_MMIO, 0xa130, &mmPA_CL_VPORT_YOFFSET_5[0], sizeof(mmPA_CL_VPORT_YOFFSET_5)/sizeof(mmPA_CL_VPORT_YOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_5", REG_MMIO, 0xa131, &mmPA_CL_VPORT_ZSCALE_5[0], sizeof(mmPA_CL_VPORT_ZSCALE_5)/sizeof(mmPA_CL_VPORT_ZSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_5", REG_MMIO, 0xa132, &mmPA_CL_VPORT_ZOFFSET_5[0], sizeof(mmPA_CL_VPORT_ZOFFSET_5)/sizeof(mmPA_CL_VPORT_ZOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_6", REG_MMIO, 0xa133, &mmPA_CL_VPORT_XSCALE_6[0], sizeof(mmPA_CL_VPORT_XSCALE_6)/sizeof(mmPA_CL_VPORT_XSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_6", REG_MMIO, 0xa134, &mmPA_CL_VPORT_XOFFSET_6[0], sizeof(mmPA_CL_VPORT_XOFFSET_6)/sizeof(mmPA_CL_VPORT_XOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_6", REG_MMIO, 0xa135, &mmPA_CL_VPORT_YSCALE_6[0], sizeof(mmPA_CL_VPORT_YSCALE_6)/sizeof(mmPA_CL_VPORT_YSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_6", REG_MMIO, 0xa136, &mmPA_CL_VPORT_YOFFSET_6[0], sizeof(mmPA_CL_VPORT_YOFFSET_6)/sizeof(mmPA_CL_VPORT_YOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_6", REG_MMIO, 0xa137, &mmPA_CL_VPORT_ZSCALE_6[0], sizeof(mmPA_CL_VPORT_ZSCALE_6)/sizeof(mmPA_CL_VPORT_ZSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_6", REG_MMIO, 0xa138, &mmPA_CL_VPORT_ZOFFSET_6[0], sizeof(mmPA_CL_VPORT_ZOFFSET_6)/sizeof(mmPA_CL_VPORT_ZOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_7", REG_MMIO, 0xa139, &mmPA_CL_VPORT_XSCALE_7[0], sizeof(mmPA_CL_VPORT_XSCALE_7)/sizeof(mmPA_CL_VPORT_XSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_7", REG_MMIO, 0xa13a, &mmPA_CL_VPORT_XOFFSET_7[0], sizeof(mmPA_CL_VPORT_XOFFSET_7)/sizeof(mmPA_CL_VPORT_XOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_7", REG_MMIO, 0xa13b, &mmPA_CL_VPORT_YSCALE_7[0], sizeof(mmPA_CL_VPORT_YSCALE_7)/sizeof(mmPA_CL_VPORT_YSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_7", REG_MMIO, 0xa13c, &mmPA_CL_VPORT_YOFFSET_7[0], sizeof(mmPA_CL_VPORT_YOFFSET_7)/sizeof(mmPA_CL_VPORT_YOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_7", REG_MMIO, 0xa13d, &mmPA_CL_VPORT_ZSCALE_7[0], sizeof(mmPA_CL_VPORT_ZSCALE_7)/sizeof(mmPA_CL_VPORT_ZSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_7", REG_MMIO, 0xa13e, &mmPA_CL_VPORT_ZOFFSET_7[0], sizeof(mmPA_CL_VPORT_ZOFFSET_7)/sizeof(mmPA_CL_VPORT_ZOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_8", REG_MMIO, 0xa13f, &mmPA_CL_VPORT_XSCALE_8[0], sizeof(mmPA_CL_VPORT_XSCALE_8)/sizeof(mmPA_CL_VPORT_XSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_8", REG_MMIO, 0xa140, &mmPA_CL_VPORT_XOFFSET_8[0], sizeof(mmPA_CL_VPORT_XOFFSET_8)/sizeof(mmPA_CL_VPORT_XOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_8", REG_MMIO, 0xa141, &mmPA_CL_VPORT_YSCALE_8[0], sizeof(mmPA_CL_VPORT_YSCALE_8)/sizeof(mmPA_CL_VPORT_YSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_8", REG_MMIO, 0xa142, &mmPA_CL_VPORT_YOFFSET_8[0], sizeof(mmPA_CL_VPORT_YOFFSET_8)/sizeof(mmPA_CL_VPORT_YOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_8", REG_MMIO, 0xa143, &mmPA_CL_VPORT_ZSCALE_8[0], sizeof(mmPA_CL_VPORT_ZSCALE_8)/sizeof(mmPA_CL_VPORT_ZSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_8", REG_MMIO, 0xa144, &mmPA_CL_VPORT_ZOFFSET_8[0], sizeof(mmPA_CL_VPORT_ZOFFSET_8)/sizeof(mmPA_CL_VPORT_ZOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_9", REG_MMIO, 0xa145, &mmPA_CL_VPORT_XSCALE_9[0], sizeof(mmPA_CL_VPORT_XSCALE_9)/sizeof(mmPA_CL_VPORT_XSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_9", REG_MMIO, 0xa146, &mmPA_CL_VPORT_XOFFSET_9[0], sizeof(mmPA_CL_VPORT_XOFFSET_9)/sizeof(mmPA_CL_VPORT_XOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_9", REG_MMIO, 0xa147, &mmPA_CL_VPORT_YSCALE_9[0], sizeof(mmPA_CL_VPORT_YSCALE_9)/sizeof(mmPA_CL_VPORT_YSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_9", REG_MMIO, 0xa148, &mmPA_CL_VPORT_YOFFSET_9[0], sizeof(mmPA_CL_VPORT_YOFFSET_9)/sizeof(mmPA_CL_VPORT_YOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_9", REG_MMIO, 0xa149, &mmPA_CL_VPORT_ZSCALE_9[0], sizeof(mmPA_CL_VPORT_ZSCALE_9)/sizeof(mmPA_CL_VPORT_ZSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_9", REG_MMIO, 0xa14a, &mmPA_CL_VPORT_ZOFFSET_9[0], sizeof(mmPA_CL_VPORT_ZOFFSET_9)/sizeof(mmPA_CL_VPORT_ZOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_10", REG_MMIO, 0xa14b, &mmPA_CL_VPORT_XSCALE_10[0], sizeof(mmPA_CL_VPORT_XSCALE_10)/sizeof(mmPA_CL_VPORT_XSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_10", REG_MMIO, 0xa14c, &mmPA_CL_VPORT_XOFFSET_10[0], sizeof(mmPA_CL_VPORT_XOFFSET_10)/sizeof(mmPA_CL_VPORT_XOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_10", REG_MMIO, 0xa14d, &mmPA_CL_VPORT_YSCALE_10[0], sizeof(mmPA_CL_VPORT_YSCALE_10)/sizeof(mmPA_CL_VPORT_YSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_10", REG_MMIO, 0xa14e, &mmPA_CL_VPORT_YOFFSET_10[0], sizeof(mmPA_CL_VPORT_YOFFSET_10)/sizeof(mmPA_CL_VPORT_YOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_10", REG_MMIO, 0xa14f, &mmPA_CL_VPORT_ZSCALE_10[0], sizeof(mmPA_CL_VPORT_ZSCALE_10)/sizeof(mmPA_CL_VPORT_ZSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_10", REG_MMIO, 0xa150, &mmPA_CL_VPORT_ZOFFSET_10[0], sizeof(mmPA_CL_VPORT_ZOFFSET_10)/sizeof(mmPA_CL_VPORT_ZOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_11", REG_MMIO, 0xa151, &mmPA_CL_VPORT_XSCALE_11[0], sizeof(mmPA_CL_VPORT_XSCALE_11)/sizeof(mmPA_CL_VPORT_XSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_11", REG_MMIO, 0xa152, &mmPA_CL_VPORT_XOFFSET_11[0], sizeof(mmPA_CL_VPORT_XOFFSET_11)/sizeof(mmPA_CL_VPORT_XOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_11", REG_MMIO, 0xa153, &mmPA_CL_VPORT_YSCALE_11[0], sizeof(mmPA_CL_VPORT_YSCALE_11)/sizeof(mmPA_CL_VPORT_YSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_11", REG_MMIO, 0xa154, &mmPA_CL_VPORT_YOFFSET_11[0], sizeof(mmPA_CL_VPORT_YOFFSET_11)/sizeof(mmPA_CL_VPORT_YOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_11", REG_MMIO, 0xa155, &mmPA_CL_VPORT_ZSCALE_11[0], sizeof(mmPA_CL_VPORT_ZSCALE_11)/sizeof(mmPA_CL_VPORT_ZSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_11", REG_MMIO, 0xa156, &mmPA_CL_VPORT_ZOFFSET_11[0], sizeof(mmPA_CL_VPORT_ZOFFSET_11)/sizeof(mmPA_CL_VPORT_ZOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_12", REG_MMIO, 0xa157, &mmPA_CL_VPORT_XSCALE_12[0], sizeof(mmPA_CL_VPORT_XSCALE_12)/sizeof(mmPA_CL_VPORT_XSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_12", REG_MMIO, 0xa158, &mmPA_CL_VPORT_XOFFSET_12[0], sizeof(mmPA_CL_VPORT_XOFFSET_12)/sizeof(mmPA_CL_VPORT_XOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_12", REG_MMIO, 0xa159, &mmPA_CL_VPORT_YSCALE_12[0], sizeof(mmPA_CL_VPORT_YSCALE_12)/sizeof(mmPA_CL_VPORT_YSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_12", REG_MMIO, 0xa15a, &mmPA_CL_VPORT_YOFFSET_12[0], sizeof(mmPA_CL_VPORT_YOFFSET_12)/sizeof(mmPA_CL_VPORT_YOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_12", REG_MMIO, 0xa15b, &mmPA_CL_VPORT_ZSCALE_12[0], sizeof(mmPA_CL_VPORT_ZSCALE_12)/sizeof(mmPA_CL_VPORT_ZSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_12", REG_MMIO, 0xa15c, &mmPA_CL_VPORT_ZOFFSET_12[0], sizeof(mmPA_CL_VPORT_ZOFFSET_12)/sizeof(mmPA_CL_VPORT_ZOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_13", REG_MMIO, 0xa15d, &mmPA_CL_VPORT_XSCALE_13[0], sizeof(mmPA_CL_VPORT_XSCALE_13)/sizeof(mmPA_CL_VPORT_XSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_13", REG_MMIO, 0xa15e, &mmPA_CL_VPORT_XOFFSET_13[0], sizeof(mmPA_CL_VPORT_XOFFSET_13)/sizeof(mmPA_CL_VPORT_XOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_13", REG_MMIO, 0xa15f, &mmPA_CL_VPORT_YSCALE_13[0], sizeof(mmPA_CL_VPORT_YSCALE_13)/sizeof(mmPA_CL_VPORT_YSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_13", REG_MMIO, 0xa160, &mmPA_CL_VPORT_YOFFSET_13[0], sizeof(mmPA_CL_VPORT_YOFFSET_13)/sizeof(mmPA_CL_VPORT_YOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_13", REG_MMIO, 0xa161, &mmPA_CL_VPORT_ZSCALE_13[0], sizeof(mmPA_CL_VPORT_ZSCALE_13)/sizeof(mmPA_CL_VPORT_ZSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_13", REG_MMIO, 0xa162, &mmPA_CL_VPORT_ZOFFSET_13[0], sizeof(mmPA_CL_VPORT_ZOFFSET_13)/sizeof(mmPA_CL_VPORT_ZOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_14", REG_MMIO, 0xa163, &mmPA_CL_VPORT_XSCALE_14[0], sizeof(mmPA_CL_VPORT_XSCALE_14)/sizeof(mmPA_CL_VPORT_XSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_14", REG_MMIO, 0xa164, &mmPA_CL_VPORT_XOFFSET_14[0], sizeof(mmPA_CL_VPORT_XOFFSET_14)/sizeof(mmPA_CL_VPORT_XOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_14", REG_MMIO, 0xa165, &mmPA_CL_VPORT_YSCALE_14[0], sizeof(mmPA_CL_VPORT_YSCALE_14)/sizeof(mmPA_CL_VPORT_YSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_14", REG_MMIO, 0xa166, &mmPA_CL_VPORT_YOFFSET_14[0], sizeof(mmPA_CL_VPORT_YOFFSET_14)/sizeof(mmPA_CL_VPORT_YOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_14", REG_MMIO, 0xa167, &mmPA_CL_VPORT_ZSCALE_14[0], sizeof(mmPA_CL_VPORT_ZSCALE_14)/sizeof(mmPA_CL_VPORT_ZSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_14", REG_MMIO, 0xa168, &mmPA_CL_VPORT_ZOFFSET_14[0], sizeof(mmPA_CL_VPORT_ZOFFSET_14)/sizeof(mmPA_CL_VPORT_ZOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_15", REG_MMIO, 0xa169, &mmPA_CL_VPORT_XSCALE_15[0], sizeof(mmPA_CL_VPORT_XSCALE_15)/sizeof(mmPA_CL_VPORT_XSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_15", REG_MMIO, 0xa16a, &mmPA_CL_VPORT_XOFFSET_15[0], sizeof(mmPA_CL_VPORT_XOFFSET_15)/sizeof(mmPA_CL_VPORT_XOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_15", REG_MMIO, 0xa16b, &mmPA_CL_VPORT_YSCALE_15[0], sizeof(mmPA_CL_VPORT_YSCALE_15)/sizeof(mmPA_CL_VPORT_YSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_15", REG_MMIO, 0xa16c, &mmPA_CL_VPORT_YOFFSET_15[0], sizeof(mmPA_CL_VPORT_YOFFSET_15)/sizeof(mmPA_CL_VPORT_YOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_15", REG_MMIO, 0xa16d, &mmPA_CL_VPORT_ZSCALE_15[0], sizeof(mmPA_CL_VPORT_ZSCALE_15)/sizeof(mmPA_CL_VPORT_ZSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_15", REG_MMIO, 0xa16e, &mmPA_CL_VPORT_ZOFFSET_15[0], sizeof(mmPA_CL_VPORT_ZOFFSET_15)/sizeof(mmPA_CL_VPORT_ZOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_X", REG_MMIO, 0xa16f, &mmPA_CL_UCP_0_X[0], sizeof(mmPA_CL_UCP_0_X)/sizeof(mmPA_CL_UCP_0_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Y", REG_MMIO, 0xa170, &mmPA_CL_UCP_0_Y[0], sizeof(mmPA_CL_UCP_0_Y)/sizeof(mmPA_CL_UCP_0_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Z", REG_MMIO, 0xa171, &mmPA_CL_UCP_0_Z[0], sizeof(mmPA_CL_UCP_0_Z)/sizeof(mmPA_CL_UCP_0_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_W", REG_MMIO, 0xa172, &mmPA_CL_UCP_0_W[0], sizeof(mmPA_CL_UCP_0_W)/sizeof(mmPA_CL_UCP_0_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_X", REG_MMIO, 0xa173, &mmPA_CL_UCP_1_X[0], sizeof(mmPA_CL_UCP_1_X)/sizeof(mmPA_CL_UCP_1_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Y", REG_MMIO, 0xa174, &mmPA_CL_UCP_1_Y[0], sizeof(mmPA_CL_UCP_1_Y)/sizeof(mmPA_CL_UCP_1_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Z", REG_MMIO, 0xa175, &mmPA_CL_UCP_1_Z[0], sizeof(mmPA_CL_UCP_1_Z)/sizeof(mmPA_CL_UCP_1_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_W", REG_MMIO, 0xa176, &mmPA_CL_UCP_1_W[0], sizeof(mmPA_CL_UCP_1_W)/sizeof(mmPA_CL_UCP_1_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_X", REG_MMIO, 0xa177, &mmPA_CL_UCP_2_X[0], sizeof(mmPA_CL_UCP_2_X)/sizeof(mmPA_CL_UCP_2_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Y", REG_MMIO, 0xa178, &mmPA_CL_UCP_2_Y[0], sizeof(mmPA_CL_UCP_2_Y)/sizeof(mmPA_CL_UCP_2_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Z", REG_MMIO, 0xa179, &mmPA_CL_UCP_2_Z[0], sizeof(mmPA_CL_UCP_2_Z)/sizeof(mmPA_CL_UCP_2_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_W", REG_MMIO, 0xa17a, &mmPA_CL_UCP_2_W[0], sizeof(mmPA_CL_UCP_2_W)/sizeof(mmPA_CL_UCP_2_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_X", REG_MMIO, 0xa17b, &mmPA_CL_UCP_3_X[0], sizeof(mmPA_CL_UCP_3_X)/sizeof(mmPA_CL_UCP_3_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Y", REG_MMIO, 0xa17c, &mmPA_CL_UCP_3_Y[0], sizeof(mmPA_CL_UCP_3_Y)/sizeof(mmPA_CL_UCP_3_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Z", REG_MMIO, 0xa17d, &mmPA_CL_UCP_3_Z[0], sizeof(mmPA_CL_UCP_3_Z)/sizeof(mmPA_CL_UCP_3_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_W", REG_MMIO, 0xa17e, &mmPA_CL_UCP_3_W[0], sizeof(mmPA_CL_UCP_3_W)/sizeof(mmPA_CL_UCP_3_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_X", REG_MMIO, 0xa17f, &mmPA_CL_UCP_4_X[0], sizeof(mmPA_CL_UCP_4_X)/sizeof(mmPA_CL_UCP_4_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Y", REG_MMIO, 0xa180, &mmPA_CL_UCP_4_Y[0], sizeof(mmPA_CL_UCP_4_Y)/sizeof(mmPA_CL_UCP_4_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Z", REG_MMIO, 0xa181, &mmPA_CL_UCP_4_Z[0], sizeof(mmPA_CL_UCP_4_Z)/sizeof(mmPA_CL_UCP_4_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_W", REG_MMIO, 0xa182, &mmPA_CL_UCP_4_W[0], sizeof(mmPA_CL_UCP_4_W)/sizeof(mmPA_CL_UCP_4_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_X", REG_MMIO, 0xa183, &mmPA_CL_UCP_5_X[0], sizeof(mmPA_CL_UCP_5_X)/sizeof(mmPA_CL_UCP_5_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Y", REG_MMIO, 0xa184, &mmPA_CL_UCP_5_Y[0], sizeof(mmPA_CL_UCP_5_Y)/sizeof(mmPA_CL_UCP_5_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Z", REG_MMIO, 0xa185, &mmPA_CL_UCP_5_Z[0], sizeof(mmPA_CL_UCP_5_Z)/sizeof(mmPA_CL_UCP_5_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_W", REG_MMIO, 0xa186, &mmPA_CL_UCP_5_W[0], sizeof(mmPA_CL_UCP_5_W)/sizeof(mmPA_CL_UCP_5_W[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_0", REG_MMIO, 0xa191, &mmSPI_PS_INPUT_CNTL_0[0], sizeof(mmSPI_PS_INPUT_CNTL_0)/sizeof(mmSPI_PS_INPUT_CNTL_0[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_1", REG_MMIO, 0xa192, &mmSPI_PS_INPUT_CNTL_1[0], sizeof(mmSPI_PS_INPUT_CNTL_1)/sizeof(mmSPI_PS_INPUT_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_2", REG_MMIO, 0xa193, &mmSPI_PS_INPUT_CNTL_2[0], sizeof(mmSPI_PS_INPUT_CNTL_2)/sizeof(mmSPI_PS_INPUT_CNTL_2[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_3", REG_MMIO, 0xa194, &mmSPI_PS_INPUT_CNTL_3[0], sizeof(mmSPI_PS_INPUT_CNTL_3)/sizeof(mmSPI_PS_INPUT_CNTL_3[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_4", REG_MMIO, 0xa195, &mmSPI_PS_INPUT_CNTL_4[0], sizeof(mmSPI_PS_INPUT_CNTL_4)/sizeof(mmSPI_PS_INPUT_CNTL_4[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_5", REG_MMIO, 0xa196, &mmSPI_PS_INPUT_CNTL_5[0], sizeof(mmSPI_PS_INPUT_CNTL_5)/sizeof(mmSPI_PS_INPUT_CNTL_5[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_6", REG_MMIO, 0xa197, &mmSPI_PS_INPUT_CNTL_6[0], sizeof(mmSPI_PS_INPUT_CNTL_6)/sizeof(mmSPI_PS_INPUT_CNTL_6[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_7", REG_MMIO, 0xa198, &mmSPI_PS_INPUT_CNTL_7[0], sizeof(mmSPI_PS_INPUT_CNTL_7)/sizeof(mmSPI_PS_INPUT_CNTL_7[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_8", REG_MMIO, 0xa199, &mmSPI_PS_INPUT_CNTL_8[0], sizeof(mmSPI_PS_INPUT_CNTL_8)/sizeof(mmSPI_PS_INPUT_CNTL_8[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_9", REG_MMIO, 0xa19a, &mmSPI_PS_INPUT_CNTL_9[0], sizeof(mmSPI_PS_INPUT_CNTL_9)/sizeof(mmSPI_PS_INPUT_CNTL_9[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_10", REG_MMIO, 0xa19b, &mmSPI_PS_INPUT_CNTL_10[0], sizeof(mmSPI_PS_INPUT_CNTL_10)/sizeof(mmSPI_PS_INPUT_CNTL_10[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_11", REG_MMIO, 0xa19c, &mmSPI_PS_INPUT_CNTL_11[0], sizeof(mmSPI_PS_INPUT_CNTL_11)/sizeof(mmSPI_PS_INPUT_CNTL_11[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_12", REG_MMIO, 0xa19d, &mmSPI_PS_INPUT_CNTL_12[0], sizeof(mmSPI_PS_INPUT_CNTL_12)/sizeof(mmSPI_PS_INPUT_CNTL_12[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_13", REG_MMIO, 0xa19e, &mmSPI_PS_INPUT_CNTL_13[0], sizeof(mmSPI_PS_INPUT_CNTL_13)/sizeof(mmSPI_PS_INPUT_CNTL_13[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_14", REG_MMIO, 0xa19f, &mmSPI_PS_INPUT_CNTL_14[0], sizeof(mmSPI_PS_INPUT_CNTL_14)/sizeof(mmSPI_PS_INPUT_CNTL_14[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_15", REG_MMIO, 0xa1a0, &mmSPI_PS_INPUT_CNTL_15[0], sizeof(mmSPI_PS_INPUT_CNTL_15)/sizeof(mmSPI_PS_INPUT_CNTL_15[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_16", REG_MMIO, 0xa1a1, &mmSPI_PS_INPUT_CNTL_16[0], sizeof(mmSPI_PS_INPUT_CNTL_16)/sizeof(mmSPI_PS_INPUT_CNTL_16[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_17", REG_MMIO, 0xa1a2, &mmSPI_PS_INPUT_CNTL_17[0], sizeof(mmSPI_PS_INPUT_CNTL_17)/sizeof(mmSPI_PS_INPUT_CNTL_17[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_18", REG_MMIO, 0xa1a3, &mmSPI_PS_INPUT_CNTL_18[0], sizeof(mmSPI_PS_INPUT_CNTL_18)/sizeof(mmSPI_PS_INPUT_CNTL_18[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_19", REG_MMIO, 0xa1a4, &mmSPI_PS_INPUT_CNTL_19[0], sizeof(mmSPI_PS_INPUT_CNTL_19)/sizeof(mmSPI_PS_INPUT_CNTL_19[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_20", REG_MMIO, 0xa1a5, &mmSPI_PS_INPUT_CNTL_20[0], sizeof(mmSPI_PS_INPUT_CNTL_20)/sizeof(mmSPI_PS_INPUT_CNTL_20[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_21", REG_MMIO, 0xa1a6, &mmSPI_PS_INPUT_CNTL_21[0], sizeof(mmSPI_PS_INPUT_CNTL_21)/sizeof(mmSPI_PS_INPUT_CNTL_21[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_22", REG_MMIO, 0xa1a7, &mmSPI_PS_INPUT_CNTL_22[0], sizeof(mmSPI_PS_INPUT_CNTL_22)/sizeof(mmSPI_PS_INPUT_CNTL_22[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_23", REG_MMIO, 0xa1a8, &mmSPI_PS_INPUT_CNTL_23[0], sizeof(mmSPI_PS_INPUT_CNTL_23)/sizeof(mmSPI_PS_INPUT_CNTL_23[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_24", REG_MMIO, 0xa1a9, &mmSPI_PS_INPUT_CNTL_24[0], sizeof(mmSPI_PS_INPUT_CNTL_24)/sizeof(mmSPI_PS_INPUT_CNTL_24[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_25", REG_MMIO, 0xa1aa, &mmSPI_PS_INPUT_CNTL_25[0], sizeof(mmSPI_PS_INPUT_CNTL_25)/sizeof(mmSPI_PS_INPUT_CNTL_25[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_26", REG_MMIO, 0xa1ab, &mmSPI_PS_INPUT_CNTL_26[0], sizeof(mmSPI_PS_INPUT_CNTL_26)/sizeof(mmSPI_PS_INPUT_CNTL_26[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_27", REG_MMIO, 0xa1ac, &mmSPI_PS_INPUT_CNTL_27[0], sizeof(mmSPI_PS_INPUT_CNTL_27)/sizeof(mmSPI_PS_INPUT_CNTL_27[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_28", REG_MMIO, 0xa1ad, &mmSPI_PS_INPUT_CNTL_28[0], sizeof(mmSPI_PS_INPUT_CNTL_28)/sizeof(mmSPI_PS_INPUT_CNTL_28[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_29", REG_MMIO, 0xa1ae, &mmSPI_PS_INPUT_CNTL_29[0], sizeof(mmSPI_PS_INPUT_CNTL_29)/sizeof(mmSPI_PS_INPUT_CNTL_29[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_30", REG_MMIO, 0xa1af, &mmSPI_PS_INPUT_CNTL_30[0], sizeof(mmSPI_PS_INPUT_CNTL_30)/sizeof(mmSPI_PS_INPUT_CNTL_30[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_31", REG_MMIO, 0xa1b0, &mmSPI_PS_INPUT_CNTL_31[0], sizeof(mmSPI_PS_INPUT_CNTL_31)/sizeof(mmSPI_PS_INPUT_CNTL_31[0]), 0, 0 },
+	{ "mmSPI_VS_OUT_CONFIG", REG_MMIO, 0xa1b1, &mmSPI_VS_OUT_CONFIG[0], sizeof(mmSPI_VS_OUT_CONFIG)/sizeof(mmSPI_VS_OUT_CONFIG[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ENA", REG_MMIO, 0xa1b3, &mmSPI_PS_INPUT_ENA[0], sizeof(mmSPI_PS_INPUT_ENA)/sizeof(mmSPI_PS_INPUT_ENA[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ADDR", REG_MMIO, 0xa1b4, &mmSPI_PS_INPUT_ADDR[0], sizeof(mmSPI_PS_INPUT_ADDR)/sizeof(mmSPI_PS_INPUT_ADDR[0]), 0, 0 },
+	{ "mmSPI_INTERP_CONTROL_0", REG_MMIO, 0xa1b5, &mmSPI_INTERP_CONTROL_0[0], sizeof(mmSPI_INTERP_CONTROL_0)/sizeof(mmSPI_INTERP_CONTROL_0[0]), 0, 0 },
+	{ "mmSPI_PS_IN_CONTROL", REG_MMIO, 0xa1b6, &mmSPI_PS_IN_CONTROL[0], sizeof(mmSPI_PS_IN_CONTROL)/sizeof(mmSPI_PS_IN_CONTROL[0]), 0, 0 },
+	{ "mmSPI_BARYC_CNTL", REG_MMIO, 0xa1b8, &mmSPI_BARYC_CNTL[0], sizeof(mmSPI_BARYC_CNTL)/sizeof(mmSPI_BARYC_CNTL[0]), 0, 0 },
+	{ "mmSPI_TMPRING_SIZE", REG_MMIO, 0xa1ba, &mmSPI_TMPRING_SIZE[0], sizeof(mmSPI_TMPRING_SIZE)/sizeof(mmSPI_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmSPI_SHADER_POS_FORMAT", REG_MMIO, 0xa1c3, &mmSPI_SHADER_POS_FORMAT[0], sizeof(mmSPI_SHADER_POS_FORMAT)/sizeof(mmSPI_SHADER_POS_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_Z_FORMAT", REG_MMIO, 0xa1c4, &mmSPI_SHADER_Z_FORMAT[0], sizeof(mmSPI_SHADER_Z_FORMAT)/sizeof(mmSPI_SHADER_Z_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_COL_FORMAT", REG_MMIO, 0xa1c5, &mmSPI_SHADER_COL_FORMAT[0], sizeof(mmSPI_SHADER_COL_FORMAT)/sizeof(mmSPI_SHADER_COL_FORMAT[0]), 0, 0 },
+	{ "mmCB_BLEND0_CONTROL", REG_MMIO, 0xa1e0, &mmCB_BLEND0_CONTROL[0], sizeof(mmCB_BLEND0_CONTROL)/sizeof(mmCB_BLEND0_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND1_CONTROL", REG_MMIO, 0xa1e1, &mmCB_BLEND1_CONTROL[0], sizeof(mmCB_BLEND1_CONTROL)/sizeof(mmCB_BLEND1_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND2_CONTROL", REG_MMIO, 0xa1e2, &mmCB_BLEND2_CONTROL[0], sizeof(mmCB_BLEND2_CONTROL)/sizeof(mmCB_BLEND2_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND3_CONTROL", REG_MMIO, 0xa1e3, &mmCB_BLEND3_CONTROL[0], sizeof(mmCB_BLEND3_CONTROL)/sizeof(mmCB_BLEND3_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND4_CONTROL", REG_MMIO, 0xa1e4, &mmCB_BLEND4_CONTROL[0], sizeof(mmCB_BLEND4_CONTROL)/sizeof(mmCB_BLEND4_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND5_CONTROL", REG_MMIO, 0xa1e5, &mmCB_BLEND5_CONTROL[0], sizeof(mmCB_BLEND5_CONTROL)/sizeof(mmCB_BLEND5_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND6_CONTROL", REG_MMIO, 0xa1e6, &mmCB_BLEND6_CONTROL[0], sizeof(mmCB_BLEND6_CONTROL)/sizeof(mmCB_BLEND6_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND7_CONTROL", REG_MMIO, 0xa1e7, &mmCB_BLEND7_CONTROL[0], sizeof(mmCB_BLEND7_CONTROL)/sizeof(mmCB_BLEND7_CONTROL[0]), 0, 0 },
+	{ "mmCS_COPY_STATE", REG_MMIO, 0xa1f3, &mmCS_COPY_STATE[0], sizeof(mmCS_COPY_STATE)/sizeof(mmCS_COPY_STATE[0]), 0, 0 },
+	{ "mmGFX_COPY_STATE", REG_MMIO, 0xa1f4, &mmGFX_COPY_STATE[0], sizeof(mmGFX_COPY_STATE)/sizeof(mmGFX_COPY_STATE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_X_RAD", REG_MMIO, 0xa1f5, &mmPA_CL_POINT_X_RAD[0], sizeof(mmPA_CL_POINT_X_RAD)/sizeof(mmPA_CL_POINT_X_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_Y_RAD", REG_MMIO, 0xa1f6, &mmPA_CL_POINT_Y_RAD[0], sizeof(mmPA_CL_POINT_Y_RAD)/sizeof(mmPA_CL_POINT_Y_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_SIZE", REG_MMIO, 0xa1f7, &mmPA_CL_POINT_SIZE[0], sizeof(mmPA_CL_POINT_SIZE)/sizeof(mmPA_CL_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_CULL_RAD", REG_MMIO, 0xa1f8, &mmPA_CL_POINT_CULL_RAD[0], sizeof(mmPA_CL_POINT_CULL_RAD)/sizeof(mmPA_CL_POINT_CULL_RAD[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE_HI", REG_MMIO, 0xa1f9, &mmVGT_DMA_BASE_HI[0], sizeof(mmVGT_DMA_BASE_HI)/sizeof(mmVGT_DMA_BASE_HI[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE", REG_MMIO, 0xa1fa, &mmVGT_DMA_BASE[0], sizeof(mmVGT_DMA_BASE)/sizeof(mmVGT_DMA_BASE[0]), 0, 0 },
+	{ "mmVGT_DRAW_INITIATOR", REG_MMIO, 0xa1fc, &mmVGT_DRAW_INITIATOR[0], sizeof(mmVGT_DRAW_INITIATOR)/sizeof(mmVGT_DRAW_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_IMMED_DATA", REG_MMIO, 0xa1fd, &mmVGT_IMMED_DATA[0], sizeof(mmVGT_IMMED_DATA)/sizeof(mmVGT_IMMED_DATA[0]), 0, 0 },
+	{ "mmVGT_EVENT_ADDRESS_REG", REG_MMIO, 0xa1fe, &mmVGT_EVENT_ADDRESS_REG[0], sizeof(mmVGT_EVENT_ADDRESS_REG)/sizeof(mmVGT_EVENT_ADDRESS_REG[0]), 0, 0 },
+	{ "mmDB_DEPTH_CONTROL", REG_MMIO, 0xa200, &mmDB_DEPTH_CONTROL[0], sizeof(mmDB_DEPTH_CONTROL)/sizeof(mmDB_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmDB_EQAA", REG_MMIO, 0xa201, &mmDB_EQAA[0], sizeof(mmDB_EQAA)/sizeof(mmDB_EQAA[0]), 0, 0 },
+	{ "mmCB_COLOR_CONTROL", REG_MMIO, 0xa202, &mmCB_COLOR_CONTROL[0], sizeof(mmCB_COLOR_CONTROL)/sizeof(mmCB_COLOR_CONTROL[0]), 0, 0 },
+	{ "mmDB_SHADER_CONTROL", REG_MMIO, 0xa203, &mmDB_SHADER_CONTROL[0], sizeof(mmDB_SHADER_CONTROL)/sizeof(mmDB_SHADER_CONTROL[0]), 0, 0 },
+	{ "mmPA_CL_CLIP_CNTL", REG_MMIO, 0xa204, &mmPA_CL_CLIP_CNTL[0], sizeof(mmPA_CL_CLIP_CNTL)/sizeof(mmPA_CL_CLIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_SC_MODE_CNTL", REG_MMIO, 0xa205, &mmPA_SU_SC_MODE_CNTL[0], sizeof(mmPA_SU_SC_MODE_CNTL)/sizeof(mmPA_SU_SC_MODE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VTE_CNTL", REG_MMIO, 0xa206, &mmPA_CL_VTE_CNTL[0], sizeof(mmPA_CL_VTE_CNTL)/sizeof(mmPA_CL_VTE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VS_OUT_CNTL", REG_MMIO, 0xa207, &mmPA_CL_VS_OUT_CNTL[0], sizeof(mmPA_CL_VS_OUT_CNTL)/sizeof(mmPA_CL_VS_OUT_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_NANINF_CNTL", REG_MMIO, 0xa208, &mmPA_CL_NANINF_CNTL[0], sizeof(mmPA_CL_NANINF_CNTL)/sizeof(mmPA_CL_NANINF_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_CNTL", REG_MMIO, 0xa209, &mmPA_SU_LINE_STIPPLE_CNTL[0], sizeof(mmPA_SU_LINE_STIPPLE_CNTL)/sizeof(mmPA_SU_LINE_STIPPLE_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_SCALE", REG_MMIO, 0xa20a, &mmPA_SU_LINE_STIPPLE_SCALE[0], sizeof(mmPA_SU_LINE_STIPPLE_SCALE)/sizeof(mmPA_SU_LINE_STIPPLE_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_PRIM_FILTER_CNTL", REG_MMIO, 0xa20b, &mmPA_SU_PRIM_FILTER_CNTL[0], sizeof(mmPA_SU_PRIM_FILTER_CNTL)/sizeof(mmPA_SU_PRIM_FILTER_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POINT_SIZE", REG_MMIO, 0xa280, &mmPA_SU_POINT_SIZE[0], sizeof(mmPA_SU_POINT_SIZE)/sizeof(mmPA_SU_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_SU_POINT_MINMAX", REG_MMIO, 0xa281, &mmPA_SU_POINT_MINMAX[0], sizeof(mmPA_SU_POINT_MINMAX)/sizeof(mmPA_SU_POINT_MINMAX[0]), 0, 0 },
+	{ "mmPA_SU_LINE_CNTL", REG_MMIO, 0xa282, &mmPA_SU_LINE_CNTL[0], sizeof(mmPA_SU_LINE_CNTL)/sizeof(mmPA_SU_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE", REG_MMIO, 0xa283, &mmPA_SC_LINE_STIPPLE[0], sizeof(mmPA_SC_LINE_STIPPLE)/sizeof(mmPA_SC_LINE_STIPPLE[0]), 0, 0 },
+	{ "mmVGT_OUTPUT_PATH_CNTL", REG_MMIO, 0xa284, &mmVGT_OUTPUT_PATH_CNTL[0], sizeof(mmVGT_OUTPUT_PATH_CNTL)/sizeof(mmVGT_OUTPUT_PATH_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_CNTL", REG_MMIO, 0xa285, &mmVGT_HOS_CNTL[0], sizeof(mmVGT_HOS_CNTL)/sizeof(mmVGT_HOS_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_MAX_TESS_LEVEL", REG_MMIO, 0xa286, &mmVGT_HOS_MAX_TESS_LEVEL[0], sizeof(mmVGT_HOS_MAX_TESS_LEVEL)/sizeof(mmVGT_HOS_MAX_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_MIN_TESS_LEVEL", REG_MMIO, 0xa287, &mmVGT_HOS_MIN_TESS_LEVEL[0], sizeof(mmVGT_HOS_MIN_TESS_LEVEL)/sizeof(mmVGT_HOS_MIN_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_REUSE_DEPTH", REG_MMIO, 0xa288, &mmVGT_HOS_REUSE_DEPTH[0], sizeof(mmVGT_HOS_REUSE_DEPTH)/sizeof(mmVGT_HOS_REUSE_DEPTH[0]), 0, 0 },
+	{ "mmVGT_GROUP_PRIM_TYPE", REG_MMIO, 0xa289, &mmVGT_GROUP_PRIM_TYPE[0], sizeof(mmVGT_GROUP_PRIM_TYPE)/sizeof(mmVGT_GROUP_PRIM_TYPE[0]), 0, 0 },
+	{ "mmVGT_GROUP_FIRST_DECR", REG_MMIO, 0xa28a, &mmVGT_GROUP_FIRST_DECR[0], sizeof(mmVGT_GROUP_FIRST_DECR)/sizeof(mmVGT_GROUP_FIRST_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_DECR", REG_MMIO, 0xa28b, &mmVGT_GROUP_DECR[0], sizeof(mmVGT_GROUP_DECR)/sizeof(mmVGT_GROUP_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_CNTL", REG_MMIO, 0xa28c, &mmVGT_GROUP_VECT_0_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_CNTL)/sizeof(mmVGT_GROUP_VECT_0_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_CNTL", REG_MMIO, 0xa28d, &mmVGT_GROUP_VECT_1_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_CNTL)/sizeof(mmVGT_GROUP_VECT_1_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_FMT_CNTL", REG_MMIO, 0xa28e, &mmVGT_GROUP_VECT_0_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_FMT_CNTL", REG_MMIO, 0xa28f, &mmVGT_GROUP_VECT_1_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GS_MODE", REG_MMIO, 0xa290, &mmVGT_GS_MODE[0], sizeof(mmVGT_GS_MODE)/sizeof(mmVGT_GS_MODE[0]), 0, 0 },
+	{ "mmVGT_GS_ONCHIP_CNTL", REG_MMIO, 0xa291, &mmVGT_GS_ONCHIP_CNTL[0], sizeof(mmVGT_GS_ONCHIP_CNTL)/sizeof(mmVGT_GS_ONCHIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_0", REG_MMIO, 0xa292, &mmPA_SC_MODE_CNTL_0[0], sizeof(mmPA_SC_MODE_CNTL_0)/sizeof(mmPA_SC_MODE_CNTL_0[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_1", REG_MMIO, 0xa293, &mmPA_SC_MODE_CNTL_1[0], sizeof(mmPA_SC_MODE_CNTL_1)/sizeof(mmPA_SC_MODE_CNTL_1[0]), 0, 0 },
+	{ "mmVGT_ENHANCE", REG_MMIO, 0xa294, &mmVGT_ENHANCE[0], sizeof(mmVGT_ENHANCE)/sizeof(mmVGT_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_GS_PER_ES", REG_MMIO, 0xa295, &mmVGT_GS_PER_ES[0], sizeof(mmVGT_GS_PER_ES)/sizeof(mmVGT_GS_PER_ES[0]), 0, 0 },
+	{ "mmVGT_ES_PER_GS", REG_MMIO, 0xa296, &mmVGT_ES_PER_GS[0], sizeof(mmVGT_ES_PER_GS)/sizeof(mmVGT_ES_PER_GS[0]), 0, 0 },
+	{ "mmVGT_GS_PER_VS", REG_MMIO, 0xa297, &mmVGT_GS_PER_VS[0], sizeof(mmVGT_GS_PER_VS)/sizeof(mmVGT_GS_PER_VS[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_1", REG_MMIO, 0xa298, &mmVGT_GSVS_RING_OFFSET_1[0], sizeof(mmVGT_GSVS_RING_OFFSET_1)/sizeof(mmVGT_GSVS_RING_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_2", REG_MMIO, 0xa299, &mmVGT_GSVS_RING_OFFSET_2[0], sizeof(mmVGT_GSVS_RING_OFFSET_2)/sizeof(mmVGT_GSVS_RING_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_3", REG_MMIO, 0xa29a, &mmVGT_GSVS_RING_OFFSET_3[0], sizeof(mmVGT_GSVS_RING_OFFSET_3)/sizeof(mmVGT_GSVS_RING_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_GS_OUT_PRIM_TYPE", REG_MMIO, 0xa29b, &mmVGT_GS_OUT_PRIM_TYPE[0], sizeof(mmVGT_GS_OUT_PRIM_TYPE)/sizeof(mmVGT_GS_OUT_PRIM_TYPE[0]), 0, 0 },
+	{ "mmIA_ENHANCE", REG_MMIO, 0xa29c, &mmIA_ENHANCE[0], sizeof(mmIA_ENHANCE)/sizeof(mmIA_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_DMA_SIZE", REG_MMIO, 0xa29d, &mmVGT_DMA_SIZE[0], sizeof(mmVGT_DMA_SIZE)/sizeof(mmVGT_DMA_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_MAX_SIZE", REG_MMIO, 0xa29e, &mmVGT_DMA_MAX_SIZE[0], sizeof(mmVGT_DMA_MAX_SIZE)/sizeof(mmVGT_DMA_MAX_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_INDEX_TYPE", REG_MMIO, 0xa29f, &mmVGT_DMA_INDEX_TYPE[0], sizeof(mmVGT_DMA_INDEX_TYPE)/sizeof(mmVGT_DMA_INDEX_TYPE[0]), 0, 0 },
+	{ "mmWD_ENHANCE", REG_MMIO, 0xa2a0, &mmWD_ENHANCE[0], sizeof(mmWD_ENHANCE)/sizeof(mmWD_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_EN", REG_MMIO, 0xa2a1, &mmVGT_PRIMITIVEID_EN[0], sizeof(mmVGT_PRIMITIVEID_EN)/sizeof(mmVGT_PRIMITIVEID_EN[0]), 0, 0 },
+	{ "mmVGT_DMA_NUM_INSTANCES", REG_MMIO, 0xa2a2, &mmVGT_DMA_NUM_INSTANCES[0], sizeof(mmVGT_DMA_NUM_INSTANCES)/sizeof(mmVGT_DMA_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_RESET", REG_MMIO, 0xa2a3, &mmVGT_PRIMITIVEID_RESET[0], sizeof(mmVGT_PRIMITIVEID_RESET)/sizeof(mmVGT_PRIMITIVEID_RESET[0]), 0, 0 },
+	{ "mmVGT_EVENT_INITIATOR", REG_MMIO, 0xa2a4, &mmVGT_EVENT_INITIATOR[0], sizeof(mmVGT_EVENT_INITIATOR)/sizeof(mmVGT_EVENT_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_EN", REG_MMIO, 0xa2a5, &mmVGT_MULTI_PRIM_IB_RESET_EN[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_0", REG_MMIO, 0xa2a8, &mmVGT_INSTANCE_STEP_RATE_0[0], sizeof(mmVGT_INSTANCE_STEP_RATE_0)/sizeof(mmVGT_INSTANCE_STEP_RATE_0[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_1", REG_MMIO, 0xa2a9, &mmVGT_INSTANCE_STEP_RATE_1[0], sizeof(mmVGT_INSTANCE_STEP_RATE_1)/sizeof(mmVGT_INSTANCE_STEP_RATE_1[0]), 0, 0 },
+	{ "mmIA_MULTI_VGT_PARAM", REG_MMIO, 0xa2aa, &mmIA_MULTI_VGT_PARAM[0], sizeof(mmIA_MULTI_VGT_PARAM)/sizeof(mmIA_MULTI_VGT_PARAM[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_ITEMSIZE", REG_MMIO, 0xa2ab, &mmVGT_ESGS_RING_ITEMSIZE[0], sizeof(mmVGT_ESGS_RING_ITEMSIZE)/sizeof(mmVGT_ESGS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_ITEMSIZE", REG_MMIO, 0xa2ac, &mmVGT_GSVS_RING_ITEMSIZE[0], sizeof(mmVGT_GSVS_RING_ITEMSIZE)/sizeof(mmVGT_GSVS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_REUSE_OFF", REG_MMIO, 0xa2ad, &mmVGT_REUSE_OFF[0], sizeof(mmVGT_REUSE_OFF)/sizeof(mmVGT_REUSE_OFF[0]), 0, 0 },
+	{ "mmVGT_VTX_CNT_EN", REG_MMIO, 0xa2ae, &mmVGT_VTX_CNT_EN[0], sizeof(mmVGT_VTX_CNT_EN)/sizeof(mmVGT_VTX_CNT_EN[0]), 0, 0 },
+	{ "mmDB_HTILE_SURFACE", REG_MMIO, 0xa2af, &mmDB_HTILE_SURFACE[0], sizeof(mmDB_HTILE_SURFACE)/sizeof(mmDB_HTILE_SURFACE[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE0", REG_MMIO, 0xa2b0, &mmDB_SRESULTS_COMPARE_STATE0[0], sizeof(mmDB_SRESULTS_COMPARE_STATE0)/sizeof(mmDB_SRESULTS_COMPARE_STATE0[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE1", REG_MMIO, 0xa2b1, &mmDB_SRESULTS_COMPARE_STATE1[0], sizeof(mmDB_SRESULTS_COMPARE_STATE1)/sizeof(mmDB_SRESULTS_COMPARE_STATE1[0]), 0, 0 },
+	{ "mmDB_PRELOAD_CONTROL", REG_MMIO, 0xa2b2, &mmDB_PRELOAD_CONTROL[0], sizeof(mmDB_PRELOAD_CONTROL)/sizeof(mmDB_PRELOAD_CONTROL[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_0", REG_MMIO, 0xa2b4, &mmVGT_STRMOUT_BUFFER_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_0", REG_MMIO, 0xa2b5, &mmVGT_STRMOUT_VTX_STRIDE_0[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_0)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_0", REG_MMIO, 0xa2b7, &mmVGT_STRMOUT_BUFFER_OFFSET_0[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_1", REG_MMIO, 0xa2b8, &mmVGT_STRMOUT_BUFFER_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_1", REG_MMIO, 0xa2b9, &mmVGT_STRMOUT_VTX_STRIDE_1[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_1)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_1", REG_MMIO, 0xa2bb, &mmVGT_STRMOUT_BUFFER_OFFSET_1[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_2", REG_MMIO, 0xa2bc, &mmVGT_STRMOUT_BUFFER_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_2", REG_MMIO, 0xa2bd, &mmVGT_STRMOUT_VTX_STRIDE_2[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_2)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_2", REG_MMIO, 0xa2bf, &mmVGT_STRMOUT_BUFFER_OFFSET_2[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_3", REG_MMIO, 0xa2c0, &mmVGT_STRMOUT_BUFFER_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_3", REG_MMIO, 0xa2c1, &mmVGT_STRMOUT_VTX_STRIDE_3[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_3)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_3", REG_MMIO, 0xa2c3, &mmVGT_STRMOUT_BUFFER_OFFSET_3[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET", REG_MMIO, 0xa2ca, &mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE", REG_MMIO, 0xa2cb, &mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", REG_MMIO, 0xa2cc, &mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0]), 0, 0 },
+	{ "mmVGT_GS_MAX_VERT_OUT", REG_MMIO, 0xa2ce, &mmVGT_GS_MAX_VERT_OUT[0], sizeof(mmVGT_GS_MAX_VERT_OUT)/sizeof(mmVGT_GS_MAX_VERT_OUT[0]), 0, 0 },
+	{ "mmVGT_SHADER_STAGES_EN", REG_MMIO, 0xa2d5, &mmVGT_SHADER_STAGES_EN[0], sizeof(mmVGT_SHADER_STAGES_EN)/sizeof(mmVGT_SHADER_STAGES_EN[0]), 0, 0 },
+	{ "mmVGT_LS_HS_CONFIG", REG_MMIO, 0xa2d6, &mmVGT_LS_HS_CONFIG[0], sizeof(mmVGT_LS_HS_CONFIG)/sizeof(mmVGT_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE", REG_MMIO, 0xa2d7, &mmVGT_GS_VERT_ITEMSIZE[0], sizeof(mmVGT_GS_VERT_ITEMSIZE)/sizeof(mmVGT_GS_VERT_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_1", REG_MMIO, 0xa2d8, &mmVGT_GS_VERT_ITEMSIZE_1[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_1)/sizeof(mmVGT_GS_VERT_ITEMSIZE_1[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_2", REG_MMIO, 0xa2d9, &mmVGT_GS_VERT_ITEMSIZE_2[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_2)/sizeof(mmVGT_GS_VERT_ITEMSIZE_2[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_3", REG_MMIO, 0xa2da, &mmVGT_GS_VERT_ITEMSIZE_3[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_3)/sizeof(mmVGT_GS_VERT_ITEMSIZE_3[0]), 0, 0 },
+	{ "mmVGT_TF_PARAM", REG_MMIO, 0xa2db, &mmVGT_TF_PARAM[0], sizeof(mmVGT_TF_PARAM)/sizeof(mmVGT_TF_PARAM[0]), 0, 0 },
+	{ "mmDB_ALPHA_TO_MASK", REG_MMIO, 0xa2dc, &mmDB_ALPHA_TO_MASK[0], sizeof(mmDB_ALPHA_TO_MASK)/sizeof(mmDB_ALPHA_TO_MASK[0]), 0, 0 },
+	{ "mmVGT_DISPATCH_DRAW_INDEX", REG_MMIO, 0xa2dd, &mmVGT_DISPATCH_DRAW_INDEX[0], sizeof(mmVGT_DISPATCH_DRAW_INDEX)/sizeof(mmVGT_DISPATCH_DRAW_INDEX[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_DB_FMT_CNTL", REG_MMIO, 0xa2de, &mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0], sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL)/sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_CLAMP", REG_MMIO, 0xa2df, &mmPA_SU_POLY_OFFSET_CLAMP[0], sizeof(mmPA_SU_POLY_OFFSET_CLAMP)/sizeof(mmPA_SU_POLY_OFFSET_CLAMP[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_SCALE", REG_MMIO, 0xa2e0, &mmPA_SU_POLY_OFFSET_FRONT_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_OFFSET", REG_MMIO, 0xa2e1, &mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_SCALE", REG_MMIO, 0xa2e2, &mmPA_SU_POLY_OFFSET_BACK_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_OFFSET", REG_MMIO, 0xa2e3, &mmPA_SU_POLY_OFFSET_BACK_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET[0]), 0, 0 },
+	{ "mmVGT_GS_INSTANCE_CNT", REG_MMIO, 0xa2e4, &mmVGT_GS_INSTANCE_CNT[0], sizeof(mmVGT_GS_INSTANCE_CNT)/sizeof(mmVGT_GS_INSTANCE_CNT[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_CONFIG", REG_MMIO, 0xa2e5, &mmVGT_STRMOUT_CONFIG[0], sizeof(mmVGT_STRMOUT_CONFIG)/sizeof(mmVGT_STRMOUT_CONFIG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_CONFIG", REG_MMIO, 0xa2e6, &mmVGT_STRMOUT_BUFFER_CONFIG[0], sizeof(mmVGT_STRMOUT_BUFFER_CONFIG)/sizeof(mmVGT_STRMOUT_BUFFER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_0", REG_MMIO, 0xa2f5, &mmPA_SC_CENTROID_PRIORITY_0[0], sizeof(mmPA_SC_CENTROID_PRIORITY_0)/sizeof(mmPA_SC_CENTROID_PRIORITY_0[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_1", REG_MMIO, 0xa2f6, &mmPA_SC_CENTROID_PRIORITY_1[0], sizeof(mmPA_SC_CENTROID_PRIORITY_1)/sizeof(mmPA_SC_CENTROID_PRIORITY_1[0]), 0, 0 },
+	{ "mmPA_SC_LINE_CNTL", REG_MMIO, 0xa2f7, &mmPA_SC_LINE_CNTL[0], sizeof(mmPA_SC_LINE_CNTL)/sizeof(mmPA_SC_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_AA_CONFIG", REG_MMIO, 0xa2f8, &mmPA_SC_AA_CONFIG[0], sizeof(mmPA_SC_AA_CONFIG)/sizeof(mmPA_SC_AA_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_VTX_CNTL", REG_MMIO, 0xa2f9, &mmPA_SU_VTX_CNTL[0], sizeof(mmPA_SU_VTX_CNTL)/sizeof(mmPA_SU_VTX_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_CLIP_ADJ", REG_MMIO, 0xa2fa, &mmPA_CL_GB_VERT_CLIP_ADJ[0], sizeof(mmPA_CL_GB_VERT_CLIP_ADJ)/sizeof(mmPA_CL_GB_VERT_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_DISC_ADJ", REG_MMIO, 0xa2fb, &mmPA_CL_GB_VERT_DISC_ADJ[0], sizeof(mmPA_CL_GB_VERT_DISC_ADJ)/sizeof(mmPA_CL_GB_VERT_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_CLIP_ADJ", REG_MMIO, 0xa2fc, &mmPA_CL_GB_HORZ_CLIP_ADJ[0], sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ)/sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_DISC_ADJ", REG_MMIO, 0xa2fd, &mmPA_CL_GB_HORZ_DISC_ADJ[0], sizeof(mmPA_CL_GB_HORZ_DISC_ADJ)/sizeof(mmPA_CL_GB_HORZ_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", REG_MMIO, 0xa2fe, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", REG_MMIO, 0xa2ff, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", REG_MMIO, 0xa300, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", REG_MMIO, 0xa301, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", REG_MMIO, 0xa302, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", REG_MMIO, 0xa303, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", REG_MMIO, 0xa304, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", REG_MMIO, 0xa305, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", REG_MMIO, 0xa306, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", REG_MMIO, 0xa307, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", REG_MMIO, 0xa308, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", REG_MMIO, 0xa309, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", REG_MMIO, 0xa30a, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", REG_MMIO, 0xa30b, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", REG_MMIO, 0xa30c, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", REG_MMIO, 0xa30d, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y0_X1Y0", REG_MMIO, 0xa30e, &mmPA_SC_AA_MASK_X0Y0_X1Y0[0], sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0)/sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y1_X1Y1", REG_MMIO, 0xa30f, &mmPA_SC_AA_MASK_X0Y1_X1Y1[0], sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1)/sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1[0]), 0, 0 },
+	{ "mmVGT_VERTEX_REUSE_BLOCK_CNTL", REG_MMIO, 0xa316, &mmVGT_VERTEX_REUSE_BLOCK_CNTL[0], sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL)/sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL[0]), 0, 0 },
+	{ "mmVGT_OUT_DEALLOC_CNTL", REG_MMIO, 0xa317, &mmVGT_OUT_DEALLOC_CNTL[0], sizeof(mmVGT_OUT_DEALLOC_CNTL)/sizeof(mmVGT_OUT_DEALLOC_CNTL[0]), 0, 0 },
+	{ "mmCB_COLOR0_BASE", REG_MMIO, 0xa318, &mmCB_COLOR0_BASE[0], sizeof(mmCB_COLOR0_BASE)/sizeof(mmCB_COLOR0_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR0_PITCH", REG_MMIO, 0xa319, &mmCB_COLOR0_PITCH[0], sizeof(mmCB_COLOR0_PITCH)/sizeof(mmCB_COLOR0_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR0_SLICE", REG_MMIO, 0xa31a, &mmCB_COLOR0_SLICE[0], sizeof(mmCB_COLOR0_SLICE)/sizeof(mmCB_COLOR0_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_VIEW", REG_MMIO, 0xa31b, &mmCB_COLOR0_VIEW[0], sizeof(mmCB_COLOR0_VIEW)/sizeof(mmCB_COLOR0_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR0_INFO", REG_MMIO, 0xa31c, &mmCB_COLOR0_INFO[0], sizeof(mmCB_COLOR0_INFO)/sizeof(mmCB_COLOR0_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR0_ATTRIB", REG_MMIO, 0xa31d, &mmCB_COLOR0_ATTRIB[0], sizeof(mmCB_COLOR0_ATTRIB)/sizeof(mmCB_COLOR0_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK", REG_MMIO, 0xa31f, &mmCB_COLOR0_CMASK[0], sizeof(mmCB_COLOR0_CMASK)/sizeof(mmCB_COLOR0_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK_SLICE", REG_MMIO, 0xa320, &mmCB_COLOR0_CMASK_SLICE[0], sizeof(mmCB_COLOR0_CMASK_SLICE)/sizeof(mmCB_COLOR0_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK", REG_MMIO, 0xa321, &mmCB_COLOR0_FMASK[0], sizeof(mmCB_COLOR0_FMASK)/sizeof(mmCB_COLOR0_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK_SLICE", REG_MMIO, 0xa322, &mmCB_COLOR0_FMASK_SLICE[0], sizeof(mmCB_COLOR0_FMASK_SLICE)/sizeof(mmCB_COLOR0_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD0", REG_MMIO, 0xa323, &mmCB_COLOR0_CLEAR_WORD0[0], sizeof(mmCB_COLOR0_CLEAR_WORD0)/sizeof(mmCB_COLOR0_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD1", REG_MMIO, 0xa324, &mmCB_COLOR0_CLEAR_WORD1[0], sizeof(mmCB_COLOR0_CLEAR_WORD1)/sizeof(mmCB_COLOR0_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR1_BASE", REG_MMIO, 0xa327, &mmCB_COLOR1_BASE[0], sizeof(mmCB_COLOR1_BASE)/sizeof(mmCB_COLOR1_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR1_PITCH", REG_MMIO, 0xa328, &mmCB_COLOR1_PITCH[0], sizeof(mmCB_COLOR1_PITCH)/sizeof(mmCB_COLOR1_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR1_SLICE", REG_MMIO, 0xa329, &mmCB_COLOR1_SLICE[0], sizeof(mmCB_COLOR1_SLICE)/sizeof(mmCB_COLOR1_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_VIEW", REG_MMIO, 0xa32a, &mmCB_COLOR1_VIEW[0], sizeof(mmCB_COLOR1_VIEW)/sizeof(mmCB_COLOR1_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR1_INFO", REG_MMIO, 0xa32b, &mmCB_COLOR1_INFO[0], sizeof(mmCB_COLOR1_INFO)/sizeof(mmCB_COLOR1_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR1_ATTRIB", REG_MMIO, 0xa32c, &mmCB_COLOR1_ATTRIB[0], sizeof(mmCB_COLOR1_ATTRIB)/sizeof(mmCB_COLOR1_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK", REG_MMIO, 0xa32e, &mmCB_COLOR1_CMASK[0], sizeof(mmCB_COLOR1_CMASK)/sizeof(mmCB_COLOR1_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK_SLICE", REG_MMIO, 0xa32f, &mmCB_COLOR1_CMASK_SLICE[0], sizeof(mmCB_COLOR1_CMASK_SLICE)/sizeof(mmCB_COLOR1_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK", REG_MMIO, 0xa330, &mmCB_COLOR1_FMASK[0], sizeof(mmCB_COLOR1_FMASK)/sizeof(mmCB_COLOR1_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK_SLICE", REG_MMIO, 0xa331, &mmCB_COLOR1_FMASK_SLICE[0], sizeof(mmCB_COLOR1_FMASK_SLICE)/sizeof(mmCB_COLOR1_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD0", REG_MMIO, 0xa332, &mmCB_COLOR1_CLEAR_WORD0[0], sizeof(mmCB_COLOR1_CLEAR_WORD0)/sizeof(mmCB_COLOR1_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD1", REG_MMIO, 0xa333, &mmCB_COLOR1_CLEAR_WORD1[0], sizeof(mmCB_COLOR1_CLEAR_WORD1)/sizeof(mmCB_COLOR1_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR2_BASE", REG_MMIO, 0xa336, &mmCB_COLOR2_BASE[0], sizeof(mmCB_COLOR2_BASE)/sizeof(mmCB_COLOR2_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR2_PITCH", REG_MMIO, 0xa337, &mmCB_COLOR2_PITCH[0], sizeof(mmCB_COLOR2_PITCH)/sizeof(mmCB_COLOR2_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR2_SLICE", REG_MMIO, 0xa338, &mmCB_COLOR2_SLICE[0], sizeof(mmCB_COLOR2_SLICE)/sizeof(mmCB_COLOR2_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_VIEW", REG_MMIO, 0xa339, &mmCB_COLOR2_VIEW[0], sizeof(mmCB_COLOR2_VIEW)/sizeof(mmCB_COLOR2_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR2_INFO", REG_MMIO, 0xa33a, &mmCB_COLOR2_INFO[0], sizeof(mmCB_COLOR2_INFO)/sizeof(mmCB_COLOR2_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR2_ATTRIB", REG_MMIO, 0xa33b, &mmCB_COLOR2_ATTRIB[0], sizeof(mmCB_COLOR2_ATTRIB)/sizeof(mmCB_COLOR2_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK", REG_MMIO, 0xa33d, &mmCB_COLOR2_CMASK[0], sizeof(mmCB_COLOR2_CMASK)/sizeof(mmCB_COLOR2_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK_SLICE", REG_MMIO, 0xa33e, &mmCB_COLOR2_CMASK_SLICE[0], sizeof(mmCB_COLOR2_CMASK_SLICE)/sizeof(mmCB_COLOR2_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK", REG_MMIO, 0xa33f, &mmCB_COLOR2_FMASK[0], sizeof(mmCB_COLOR2_FMASK)/sizeof(mmCB_COLOR2_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK_SLICE", REG_MMIO, 0xa340, &mmCB_COLOR2_FMASK_SLICE[0], sizeof(mmCB_COLOR2_FMASK_SLICE)/sizeof(mmCB_COLOR2_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD0", REG_MMIO, 0xa341, &mmCB_COLOR2_CLEAR_WORD0[0], sizeof(mmCB_COLOR2_CLEAR_WORD0)/sizeof(mmCB_COLOR2_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD1", REG_MMIO, 0xa342, &mmCB_COLOR2_CLEAR_WORD1[0], sizeof(mmCB_COLOR2_CLEAR_WORD1)/sizeof(mmCB_COLOR2_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR3_BASE", REG_MMIO, 0xa345, &mmCB_COLOR3_BASE[0], sizeof(mmCB_COLOR3_BASE)/sizeof(mmCB_COLOR3_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR3_PITCH", REG_MMIO, 0xa346, &mmCB_COLOR3_PITCH[0], sizeof(mmCB_COLOR3_PITCH)/sizeof(mmCB_COLOR3_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR3_SLICE", REG_MMIO, 0xa347, &mmCB_COLOR3_SLICE[0], sizeof(mmCB_COLOR3_SLICE)/sizeof(mmCB_COLOR3_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_VIEW", REG_MMIO, 0xa348, &mmCB_COLOR3_VIEW[0], sizeof(mmCB_COLOR3_VIEW)/sizeof(mmCB_COLOR3_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR3_INFO", REG_MMIO, 0xa349, &mmCB_COLOR3_INFO[0], sizeof(mmCB_COLOR3_INFO)/sizeof(mmCB_COLOR3_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR3_ATTRIB", REG_MMIO, 0xa34a, &mmCB_COLOR3_ATTRIB[0], sizeof(mmCB_COLOR3_ATTRIB)/sizeof(mmCB_COLOR3_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK", REG_MMIO, 0xa34c, &mmCB_COLOR3_CMASK[0], sizeof(mmCB_COLOR3_CMASK)/sizeof(mmCB_COLOR3_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK_SLICE", REG_MMIO, 0xa34d, &mmCB_COLOR3_CMASK_SLICE[0], sizeof(mmCB_COLOR3_CMASK_SLICE)/sizeof(mmCB_COLOR3_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK", REG_MMIO, 0xa34e, &mmCB_COLOR3_FMASK[0], sizeof(mmCB_COLOR3_FMASK)/sizeof(mmCB_COLOR3_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK_SLICE", REG_MMIO, 0xa34f, &mmCB_COLOR3_FMASK_SLICE[0], sizeof(mmCB_COLOR3_FMASK_SLICE)/sizeof(mmCB_COLOR3_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD0", REG_MMIO, 0xa350, &mmCB_COLOR3_CLEAR_WORD0[0], sizeof(mmCB_COLOR3_CLEAR_WORD0)/sizeof(mmCB_COLOR3_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD1", REG_MMIO, 0xa351, &mmCB_COLOR3_CLEAR_WORD1[0], sizeof(mmCB_COLOR3_CLEAR_WORD1)/sizeof(mmCB_COLOR3_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR4_BASE", REG_MMIO, 0xa354, &mmCB_COLOR4_BASE[0], sizeof(mmCB_COLOR4_BASE)/sizeof(mmCB_COLOR4_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR4_PITCH", REG_MMIO, 0xa355, &mmCB_COLOR4_PITCH[0], sizeof(mmCB_COLOR4_PITCH)/sizeof(mmCB_COLOR4_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR4_SLICE", REG_MMIO, 0xa356, &mmCB_COLOR4_SLICE[0], sizeof(mmCB_COLOR4_SLICE)/sizeof(mmCB_COLOR4_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_VIEW", REG_MMIO, 0xa357, &mmCB_COLOR4_VIEW[0], sizeof(mmCB_COLOR4_VIEW)/sizeof(mmCB_COLOR4_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR4_INFO", REG_MMIO, 0xa358, &mmCB_COLOR4_INFO[0], sizeof(mmCB_COLOR4_INFO)/sizeof(mmCB_COLOR4_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR4_ATTRIB", REG_MMIO, 0xa359, &mmCB_COLOR4_ATTRIB[0], sizeof(mmCB_COLOR4_ATTRIB)/sizeof(mmCB_COLOR4_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK", REG_MMIO, 0xa35b, &mmCB_COLOR4_CMASK[0], sizeof(mmCB_COLOR4_CMASK)/sizeof(mmCB_COLOR4_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK_SLICE", REG_MMIO, 0xa35c, &mmCB_COLOR4_CMASK_SLICE[0], sizeof(mmCB_COLOR4_CMASK_SLICE)/sizeof(mmCB_COLOR4_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK", REG_MMIO, 0xa35d, &mmCB_COLOR4_FMASK[0], sizeof(mmCB_COLOR4_FMASK)/sizeof(mmCB_COLOR4_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK_SLICE", REG_MMIO, 0xa35e, &mmCB_COLOR4_FMASK_SLICE[0], sizeof(mmCB_COLOR4_FMASK_SLICE)/sizeof(mmCB_COLOR4_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD0", REG_MMIO, 0xa35f, &mmCB_COLOR4_CLEAR_WORD0[0], sizeof(mmCB_COLOR4_CLEAR_WORD0)/sizeof(mmCB_COLOR4_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD1", REG_MMIO, 0xa360, &mmCB_COLOR4_CLEAR_WORD1[0], sizeof(mmCB_COLOR4_CLEAR_WORD1)/sizeof(mmCB_COLOR4_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR5_BASE", REG_MMIO, 0xa363, &mmCB_COLOR5_BASE[0], sizeof(mmCB_COLOR5_BASE)/sizeof(mmCB_COLOR5_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR5_PITCH", REG_MMIO, 0xa364, &mmCB_COLOR5_PITCH[0], sizeof(mmCB_COLOR5_PITCH)/sizeof(mmCB_COLOR5_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR5_SLICE", REG_MMIO, 0xa365, &mmCB_COLOR5_SLICE[0], sizeof(mmCB_COLOR5_SLICE)/sizeof(mmCB_COLOR5_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_VIEW", REG_MMIO, 0xa366, &mmCB_COLOR5_VIEW[0], sizeof(mmCB_COLOR5_VIEW)/sizeof(mmCB_COLOR5_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR5_INFO", REG_MMIO, 0xa367, &mmCB_COLOR5_INFO[0], sizeof(mmCB_COLOR5_INFO)/sizeof(mmCB_COLOR5_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR5_ATTRIB", REG_MMIO, 0xa368, &mmCB_COLOR5_ATTRIB[0], sizeof(mmCB_COLOR5_ATTRIB)/sizeof(mmCB_COLOR5_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK", REG_MMIO, 0xa36a, &mmCB_COLOR5_CMASK[0], sizeof(mmCB_COLOR5_CMASK)/sizeof(mmCB_COLOR5_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK_SLICE", REG_MMIO, 0xa36b, &mmCB_COLOR5_CMASK_SLICE[0], sizeof(mmCB_COLOR5_CMASK_SLICE)/sizeof(mmCB_COLOR5_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK", REG_MMIO, 0xa36c, &mmCB_COLOR5_FMASK[0], sizeof(mmCB_COLOR5_FMASK)/sizeof(mmCB_COLOR5_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK_SLICE", REG_MMIO, 0xa36d, &mmCB_COLOR5_FMASK_SLICE[0], sizeof(mmCB_COLOR5_FMASK_SLICE)/sizeof(mmCB_COLOR5_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD0", REG_MMIO, 0xa36e, &mmCB_COLOR5_CLEAR_WORD0[0], sizeof(mmCB_COLOR5_CLEAR_WORD0)/sizeof(mmCB_COLOR5_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD1", REG_MMIO, 0xa36f, &mmCB_COLOR5_CLEAR_WORD1[0], sizeof(mmCB_COLOR5_CLEAR_WORD1)/sizeof(mmCB_COLOR5_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR6_BASE", REG_MMIO, 0xa372, &mmCB_COLOR6_BASE[0], sizeof(mmCB_COLOR6_BASE)/sizeof(mmCB_COLOR6_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR6_PITCH", REG_MMIO, 0xa373, &mmCB_COLOR6_PITCH[0], sizeof(mmCB_COLOR6_PITCH)/sizeof(mmCB_COLOR6_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR6_SLICE", REG_MMIO, 0xa374, &mmCB_COLOR6_SLICE[0], sizeof(mmCB_COLOR6_SLICE)/sizeof(mmCB_COLOR6_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_VIEW", REG_MMIO, 0xa375, &mmCB_COLOR6_VIEW[0], sizeof(mmCB_COLOR6_VIEW)/sizeof(mmCB_COLOR6_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR6_INFO", REG_MMIO, 0xa376, &mmCB_COLOR6_INFO[0], sizeof(mmCB_COLOR6_INFO)/sizeof(mmCB_COLOR6_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR6_ATTRIB", REG_MMIO, 0xa377, &mmCB_COLOR6_ATTRIB[0], sizeof(mmCB_COLOR6_ATTRIB)/sizeof(mmCB_COLOR6_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK", REG_MMIO, 0xa379, &mmCB_COLOR6_CMASK[0], sizeof(mmCB_COLOR6_CMASK)/sizeof(mmCB_COLOR6_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK_SLICE", REG_MMIO, 0xa37a, &mmCB_COLOR6_CMASK_SLICE[0], sizeof(mmCB_COLOR6_CMASK_SLICE)/sizeof(mmCB_COLOR6_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK", REG_MMIO, 0xa37b, &mmCB_COLOR6_FMASK[0], sizeof(mmCB_COLOR6_FMASK)/sizeof(mmCB_COLOR6_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK_SLICE", REG_MMIO, 0xa37c, &mmCB_COLOR6_FMASK_SLICE[0], sizeof(mmCB_COLOR6_FMASK_SLICE)/sizeof(mmCB_COLOR6_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD0", REG_MMIO, 0xa37d, &mmCB_COLOR6_CLEAR_WORD0[0], sizeof(mmCB_COLOR6_CLEAR_WORD0)/sizeof(mmCB_COLOR6_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD1", REG_MMIO, 0xa37e, &mmCB_COLOR6_CLEAR_WORD1[0], sizeof(mmCB_COLOR6_CLEAR_WORD1)/sizeof(mmCB_COLOR6_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR7_BASE", REG_MMIO, 0xa381, &mmCB_COLOR7_BASE[0], sizeof(mmCB_COLOR7_BASE)/sizeof(mmCB_COLOR7_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR7_PITCH", REG_MMIO, 0xa382, &mmCB_COLOR7_PITCH[0], sizeof(mmCB_COLOR7_PITCH)/sizeof(mmCB_COLOR7_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR7_SLICE", REG_MMIO, 0xa383, &mmCB_COLOR7_SLICE[0], sizeof(mmCB_COLOR7_SLICE)/sizeof(mmCB_COLOR7_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_VIEW", REG_MMIO, 0xa384, &mmCB_COLOR7_VIEW[0], sizeof(mmCB_COLOR7_VIEW)/sizeof(mmCB_COLOR7_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR7_INFO", REG_MMIO, 0xa385, &mmCB_COLOR7_INFO[0], sizeof(mmCB_COLOR7_INFO)/sizeof(mmCB_COLOR7_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR7_ATTRIB", REG_MMIO, 0xa386, &mmCB_COLOR7_ATTRIB[0], sizeof(mmCB_COLOR7_ATTRIB)/sizeof(mmCB_COLOR7_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK", REG_MMIO, 0xa388, &mmCB_COLOR7_CMASK[0], sizeof(mmCB_COLOR7_CMASK)/sizeof(mmCB_COLOR7_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK_SLICE", REG_MMIO, 0xa389, &mmCB_COLOR7_CMASK_SLICE[0], sizeof(mmCB_COLOR7_CMASK_SLICE)/sizeof(mmCB_COLOR7_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK", REG_MMIO, 0xa38a, &mmCB_COLOR7_FMASK[0], sizeof(mmCB_COLOR7_FMASK)/sizeof(mmCB_COLOR7_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK_SLICE", REG_MMIO, 0xa38b, &mmCB_COLOR7_FMASK_SLICE[0], sizeof(mmCB_COLOR7_FMASK_SLICE)/sizeof(mmCB_COLOR7_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD0", REG_MMIO, 0xa38c, &mmCB_COLOR7_CLEAR_WORD0[0], sizeof(mmCB_COLOR7_CLEAR_WORD0)/sizeof(mmCB_COLOR7_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD1", REG_MMIO, 0xa38d, &mmCB_COLOR7_CLEAR_WORD1[0], sizeof(mmCB_COLOR7_CLEAR_WORD1)/sizeof(mmCB_COLOR7_CLEAR_WORD1[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG11", REG_SMC, 0xb, &ixCLIPPER_DEBUG_REG11[0], sizeof(ixCLIPPER_DEBUG_REG11)/sizeof(ixCLIPPER_DEBUG_REG11[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG11", REG_SMC, 0xb, &ixVGT_DEBUG_REG11[0], sizeof(ixVGT_DEBUG_REG11)/sizeof(ixVGT_DEBUG_REG11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG12", REG_SMC, 0xc, &ixCLIPPER_DEBUG_REG12[0], sizeof(ixCLIPPER_DEBUG_REG12)/sizeof(ixCLIPPER_DEBUG_REG12[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG12", REG_SMC, 0xc, &ixVGT_DEBUG_REG12[0], sizeof(ixVGT_DEBUG_REG12)/sizeof(ixVGT_DEBUG_REG12[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_LO", REG_MMIO, 0xc000, &mmCP_EOP_DONE_ADDR_LO[0], sizeof(mmCP_EOP_DONE_ADDR_LO)/sizeof(mmCP_EOP_DONE_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_HI", REG_MMIO, 0xc001, &mmCP_EOP_DONE_ADDR_HI[0], sizeof(mmCP_EOP_DONE_ADDR_HI)/sizeof(mmCP_EOP_DONE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_LO", REG_MMIO, 0xc002, &mmCP_EOP_DONE_DATA_LO[0], sizeof(mmCP_EOP_DONE_DATA_LO)/sizeof(mmCP_EOP_DONE_DATA_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_HI", REG_MMIO, 0xc003, &mmCP_EOP_DONE_DATA_HI[0], sizeof(mmCP_EOP_DONE_DATA_HI)/sizeof(mmCP_EOP_DONE_DATA_HI[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_LO", REG_MMIO, 0xc004, &mmCP_EOP_LAST_FENCE_LO[0], sizeof(mmCP_EOP_LAST_FENCE_LO)/sizeof(mmCP_EOP_LAST_FENCE_LO[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_HI", REG_MMIO, 0xc005, &mmCP_EOP_LAST_FENCE_HI[0], sizeof(mmCP_EOP_LAST_FENCE_HI)/sizeof(mmCP_EOP_LAST_FENCE_HI[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_LO", REG_MMIO, 0xc006, &mmCP_STREAM_OUT_ADDR_LO[0], sizeof(mmCP_STREAM_OUT_ADDR_LO)/sizeof(mmCP_STREAM_OUT_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_HI", REG_MMIO, 0xc007, &mmCP_STREAM_OUT_ADDR_HI[0], sizeof(mmCP_STREAM_OUT_ADDR_HI)/sizeof(mmCP_STREAM_OUT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_LO", REG_MMIO, 0xc008, &mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_HI", REG_MMIO, 0xc009, &mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_LO", REG_MMIO, 0xc00a, &mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_HI", REG_MMIO, 0xc00b, &mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_LO", REG_MMIO, 0xc00c, &mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_HI", REG_MMIO, 0xc00d, &mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_LO", REG_MMIO, 0xc00e, &mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_HI", REG_MMIO, 0xc00f, &mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_LO", REG_MMIO, 0xc010, &mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_HI", REG_MMIO, 0xc011, &mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_LO", REG_MMIO, 0xc012, &mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_HI", REG_MMIO, 0xc013, &mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_LO", REG_MMIO, 0xc014, &mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_HI", REG_MMIO, 0xc015, &mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_LO", REG_MMIO, 0xc016, &mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_HI", REG_MMIO, 0xc017, &mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_LO", REG_MMIO, 0xc018, &mmCP_PIPE_STATS_ADDR_LO[0], sizeof(mmCP_PIPE_STATS_ADDR_LO)/sizeof(mmCP_PIPE_STATS_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_HI", REG_MMIO, 0xc019, &mmCP_PIPE_STATS_ADDR_HI[0], sizeof(mmCP_PIPE_STATS_ADDR_HI)/sizeof(mmCP_PIPE_STATS_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_LO", REG_MMIO, 0xc01a, &mmCP_VGT_IAVERT_COUNT_LO[0], sizeof(mmCP_VGT_IAVERT_COUNT_LO)/sizeof(mmCP_VGT_IAVERT_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_HI", REG_MMIO, 0xc01b, &mmCP_VGT_IAVERT_COUNT_HI[0], sizeof(mmCP_VGT_IAVERT_COUNT_HI)/sizeof(mmCP_VGT_IAVERT_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_LO", REG_MMIO, 0xc01c, &mmCP_VGT_IAPRIM_COUNT_LO[0], sizeof(mmCP_VGT_IAPRIM_COUNT_LO)/sizeof(mmCP_VGT_IAPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_HI", REG_MMIO, 0xc01d, &mmCP_VGT_IAPRIM_COUNT_HI[0], sizeof(mmCP_VGT_IAPRIM_COUNT_HI)/sizeof(mmCP_VGT_IAPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_LO", REG_MMIO, 0xc01e, &mmCP_VGT_GSPRIM_COUNT_LO[0], sizeof(mmCP_VGT_GSPRIM_COUNT_LO)/sizeof(mmCP_VGT_GSPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_HI", REG_MMIO, 0xc01f, &mmCP_VGT_GSPRIM_COUNT_HI[0], sizeof(mmCP_VGT_GSPRIM_COUNT_HI)/sizeof(mmCP_VGT_GSPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_LO", REG_MMIO, 0xc020, &mmCP_VGT_VSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_VSINVOC_COUNT_LO)/sizeof(mmCP_VGT_VSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_HI", REG_MMIO, 0xc021, &mmCP_VGT_VSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_VSINVOC_COUNT_HI)/sizeof(mmCP_VGT_VSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_LO", REG_MMIO, 0xc022, &mmCP_VGT_GSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_GSINVOC_COUNT_LO)/sizeof(mmCP_VGT_GSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_HI", REG_MMIO, 0xc023, &mmCP_VGT_GSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_GSINVOC_COUNT_HI)/sizeof(mmCP_VGT_GSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_LO", REG_MMIO, 0xc024, &mmCP_VGT_HSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_HSINVOC_COUNT_LO)/sizeof(mmCP_VGT_HSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_HI", REG_MMIO, 0xc025, &mmCP_VGT_HSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_HSINVOC_COUNT_HI)/sizeof(mmCP_VGT_HSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_LO", REG_MMIO, 0xc026, &mmCP_VGT_DSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_DSINVOC_COUNT_LO)/sizeof(mmCP_VGT_DSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_HI", REG_MMIO, 0xc027, &mmCP_VGT_DSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_DSINVOC_COUNT_HI)/sizeof(mmCP_VGT_DSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_LO", REG_MMIO, 0xc028, &mmCP_PA_CINVOC_COUNT_LO[0], sizeof(mmCP_PA_CINVOC_COUNT_LO)/sizeof(mmCP_PA_CINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_HI", REG_MMIO, 0xc029, &mmCP_PA_CINVOC_COUNT_HI[0], sizeof(mmCP_PA_CINVOC_COUNT_HI)/sizeof(mmCP_PA_CINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_LO", REG_MMIO, 0xc02a, &mmCP_PA_CPRIM_COUNT_LO[0], sizeof(mmCP_PA_CPRIM_COUNT_LO)/sizeof(mmCP_PA_CPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_HI", REG_MMIO, 0xc02b, &mmCP_PA_CPRIM_COUNT_HI[0], sizeof(mmCP_PA_CPRIM_COUNT_HI)/sizeof(mmCP_PA_CPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_LO", REG_MMIO, 0xc02c, &mmCP_SC_PSINVOC_COUNT0_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT0_LO)/sizeof(mmCP_SC_PSINVOC_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_HI", REG_MMIO, 0xc02d, &mmCP_SC_PSINVOC_COUNT0_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT0_HI)/sizeof(mmCP_SC_PSINVOC_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_LO", REG_MMIO, 0xc02e, &mmCP_SC_PSINVOC_COUNT1_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT1_LO)/sizeof(mmCP_SC_PSINVOC_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_HI", REG_MMIO, 0xc02f, &mmCP_SC_PSINVOC_COUNT1_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT1_HI)/sizeof(mmCP_SC_PSINVOC_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_LO", REG_MMIO, 0xc030, &mmCP_VGT_CSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_CSINVOC_COUNT_LO)/sizeof(mmCP_VGT_CSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_HI", REG_MMIO, 0xc031, &mmCP_VGT_CSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_CSINVOC_COUNT_HI)/sizeof(mmCP_VGT_CSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_STRMOUT_CNTL", REG_MMIO, 0xc03f, &mmCP_STRMOUT_CNTL[0], sizeof(mmCP_STRMOUT_CNTL)/sizeof(mmCP_STRMOUT_CNTL[0]), 0, 0 },
+	{ "mmSCRATCH_REG0", REG_MMIO, 0xc040, &mmSCRATCH_REG0[0], sizeof(mmSCRATCH_REG0)/sizeof(mmSCRATCH_REG0[0]), 0, 0 },
+	{ "mmSCRATCH_REG1", REG_MMIO, 0xc041, &mmSCRATCH_REG1[0], sizeof(mmSCRATCH_REG1)/sizeof(mmSCRATCH_REG1[0]), 0, 0 },
+	{ "mmSCRATCH_REG2", REG_MMIO, 0xc042, &mmSCRATCH_REG2[0], sizeof(mmSCRATCH_REG2)/sizeof(mmSCRATCH_REG2[0]), 0, 0 },
+	{ "mmSCRATCH_REG3", REG_MMIO, 0xc043, &mmSCRATCH_REG3[0], sizeof(mmSCRATCH_REG3)/sizeof(mmSCRATCH_REG3[0]), 0, 0 },
+	{ "mmSCRATCH_REG4", REG_MMIO, 0xc044, &mmSCRATCH_REG4[0], sizeof(mmSCRATCH_REG4)/sizeof(mmSCRATCH_REG4[0]), 0, 0 },
+	{ "mmSCRATCH_REG5", REG_MMIO, 0xc045, &mmSCRATCH_REG5[0], sizeof(mmSCRATCH_REG5)/sizeof(mmSCRATCH_REG5[0]), 0, 0 },
+	{ "mmSCRATCH_REG6", REG_MMIO, 0xc046, &mmSCRATCH_REG6[0], sizeof(mmSCRATCH_REG6)/sizeof(mmSCRATCH_REG6[0]), 0, 0 },
+	{ "mmSCRATCH_REG7", REG_MMIO, 0xc047, &mmSCRATCH_REG7[0], sizeof(mmSCRATCH_REG7)/sizeof(mmSCRATCH_REG7[0]), 0, 0 },
+	{ "mmSCRATCH_UMSK", REG_MMIO, 0xc050, &mmSCRATCH_UMSK[0], sizeof(mmSCRATCH_UMSK)/sizeof(mmSCRATCH_UMSK[0]), 0, 0 },
+	{ "mmSCRATCH_ADDR", REG_MMIO, 0xc051, &mmSCRATCH_ADDR[0], sizeof(mmSCRATCH_ADDR)/sizeof(mmSCRATCH_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_ATOMIC_PREOP_LO", REG_MMIO, 0xc052, &mmCP_PFP_ATOMIC_PREOP_LO[0], sizeof(mmCP_PFP_ATOMIC_PREOP_LO)/sizeof(mmCP_PFP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_ATOMIC_PREOP_HI", REG_MMIO, 0xc053, &mmCP_PFP_ATOMIC_PREOP_HI[0], sizeof(mmCP_PFP_ATOMIC_PREOP_HI)/sizeof(mmCP_PFP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc054, &mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc055, &mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc056, &mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc057, &mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_LO", REG_MMIO, 0xc058, &mmCP_APPEND_ADDR_LO[0], sizeof(mmCP_APPEND_ADDR_LO)/sizeof(mmCP_APPEND_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_HI", REG_MMIO, 0xc059, &mmCP_APPEND_ADDR_HI[0], sizeof(mmCP_APPEND_ADDR_HI)/sizeof(mmCP_APPEND_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_DATA", REG_MMIO, 0xc05a, &mmCP_APPEND_DATA[0], sizeof(mmCP_APPEND_DATA)/sizeof(mmCP_APPEND_DATA[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_CS_FENCE", REG_MMIO, 0xc05b, &mmCP_APPEND_LAST_CS_FENCE[0], sizeof(mmCP_APPEND_LAST_CS_FENCE)/sizeof(mmCP_APPEND_LAST_CS_FENCE[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_PS_FENCE", REG_MMIO, 0xc05c, &mmCP_APPEND_LAST_PS_FENCE[0], sizeof(mmCP_APPEND_LAST_PS_FENCE)/sizeof(mmCP_APPEND_LAST_PS_FENCE[0]), 0, 0 },
+	{ "mmCP_ME_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &mmCP_ME_ATOMIC_PREOP_LO[0], sizeof(mmCP_ME_ATOMIC_PREOP_LO)/sizeof(mmCP_ME_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &mmCP_ATOMIC_PREOP_LO[0], sizeof(mmCP_ATOMIC_PREOP_LO)/sizeof(mmCP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &mmCP_ME_ATOMIC_PREOP_HI[0], sizeof(mmCP_ME_ATOMIC_PREOP_HI)/sizeof(mmCP_ME_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &mmCP_ATOMIC_PREOP_HI[0], sizeof(mmCP_ATOMIC_PREOP_HI)/sizeof(mmCP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &mmCP_ME_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &mmCP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &mmCP_ME_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &mmCP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &mmCP_ME_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &mmCP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &mmCP_ME_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &mmCP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_LO", REG_MMIO, 0xc069, &mmCP_ME_MC_WADDR_LO[0], sizeof(mmCP_ME_MC_WADDR_LO)/sizeof(mmCP_ME_MC_WADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_HI", REG_MMIO, 0xc06a, &mmCP_ME_MC_WADDR_HI[0], sizeof(mmCP_ME_MC_WADDR_HI)/sizeof(mmCP_ME_MC_WADDR_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_LO", REG_MMIO, 0xc06b, &mmCP_ME_MC_WDATA_LO[0], sizeof(mmCP_ME_MC_WDATA_LO)/sizeof(mmCP_ME_MC_WDATA_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_HI", REG_MMIO, 0xc06c, &mmCP_ME_MC_WDATA_HI[0], sizeof(mmCP_ME_MC_WDATA_HI)/sizeof(mmCP_ME_MC_WDATA_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_LO", REG_MMIO, 0xc06d, &mmCP_ME_MC_RADDR_LO[0], sizeof(mmCP_ME_MC_RADDR_LO)/sizeof(mmCP_ME_MC_RADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_HI", REG_MMIO, 0xc06e, &mmCP_ME_MC_RADDR_HI[0], sizeof(mmCP_ME_MC_RADDR_HI)/sizeof(mmCP_ME_MC_RADDR_HI[0]), 0, 0 },
+	{ "mmCP_SEM_WAIT_TIMER", REG_MMIO, 0xc06f, &mmCP_SEM_WAIT_TIMER[0], sizeof(mmCP_SEM_WAIT_TIMER)/sizeof(mmCP_SEM_WAIT_TIMER[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_LO", REG_MMIO, 0xc070, &mmCP_SIG_SEM_ADDR_LO[0], sizeof(mmCP_SIG_SEM_ADDR_LO)/sizeof(mmCP_SIG_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_HI", REG_MMIO, 0xc071, &mmCP_SIG_SEM_ADDR_HI[0], sizeof(mmCP_SIG_SEM_ADDR_HI)/sizeof(mmCP_SIG_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_WAIT_REG_MEM_TIMEOUT", REG_MMIO, 0xc074, &mmCP_WAIT_REG_MEM_TIMEOUT[0], sizeof(mmCP_WAIT_REG_MEM_TIMEOUT)/sizeof(mmCP_WAIT_REG_MEM_TIMEOUT[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_LO", REG_MMIO, 0xc075, &mmCP_WAIT_SEM_ADDR_LO[0], sizeof(mmCP_WAIT_SEM_ADDR_LO)/sizeof(mmCP_WAIT_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_HI", REG_MMIO, 0xc076, &mmCP_WAIT_SEM_ADDR_HI[0], sizeof(mmCP_WAIT_SEM_ADDR_HI)/sizeof(mmCP_WAIT_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_CONTROL", REG_MMIO, 0xc077, &mmCP_DMA_PFP_CONTROL[0], sizeof(mmCP_DMA_PFP_CONTROL)/sizeof(mmCP_DMA_PFP_CONTROL[0]), 0, 0 },
+	{ "mmCP_DMA_ME_CONTROL", REG_MMIO, 0xc078, &mmCP_DMA_ME_CONTROL[0], sizeof(mmCP_DMA_ME_CONTROL)/sizeof(mmCP_DMA_ME_CONTROL[0]), 0, 0 },
+	{ "mmCP_COHER_BASE_HI", REG_MMIO, 0xc079, &mmCP_COHER_BASE_HI[0], sizeof(mmCP_COHER_BASE_HI)/sizeof(mmCP_COHER_BASE_HI[0]), 0, 0 },
+	{ "mmCP_COHER_START_DELAY", REG_MMIO, 0xc07b, &mmCP_COHER_START_DELAY[0], sizeof(mmCP_COHER_START_DELAY)/sizeof(mmCP_COHER_START_DELAY[0]), 0, 0 },
+	{ "mmCP_COHER_CNTL", REG_MMIO, 0xc07c, &mmCP_COHER_CNTL[0], sizeof(mmCP_COHER_CNTL)/sizeof(mmCP_COHER_CNTL[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE", REG_MMIO, 0xc07d, &mmCP_COHER_SIZE[0], sizeof(mmCP_COHER_SIZE)/sizeof(mmCP_COHER_SIZE[0]), 0, 0 },
+	{ "mmCP_COHER_BASE", REG_MMIO, 0xc07e, &mmCP_COHER_BASE[0], sizeof(mmCP_COHER_BASE)/sizeof(mmCP_COHER_BASE[0]), 0, 0 },
+	{ "mmCP_COHER_STATUS", REG_MMIO, 0xc07f, &mmCP_COHER_STATUS[0], sizeof(mmCP_COHER_STATUS)/sizeof(mmCP_COHER_STATUS[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR", REG_MMIO, 0xc080, &mmCP_DMA_ME_SRC_ADDR[0], sizeof(mmCP_DMA_ME_SRC_ADDR)/sizeof(mmCP_DMA_ME_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR_HI", REG_MMIO, 0xc081, &mmCP_DMA_ME_SRC_ADDR_HI[0], sizeof(mmCP_DMA_ME_SRC_ADDR_HI)/sizeof(mmCP_DMA_ME_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR", REG_MMIO, 0xc082, &mmCP_DMA_ME_DST_ADDR[0], sizeof(mmCP_DMA_ME_DST_ADDR)/sizeof(mmCP_DMA_ME_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR_HI", REG_MMIO, 0xc083, &mmCP_DMA_ME_DST_ADDR_HI[0], sizeof(mmCP_DMA_ME_DST_ADDR_HI)/sizeof(mmCP_DMA_ME_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_COMMAND", REG_MMIO, 0xc084, &mmCP_DMA_ME_COMMAND[0], sizeof(mmCP_DMA_ME_COMMAND)/sizeof(mmCP_DMA_ME_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR", REG_MMIO, 0xc085, &mmCP_DMA_PFP_SRC_ADDR[0], sizeof(mmCP_DMA_PFP_SRC_ADDR)/sizeof(mmCP_DMA_PFP_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR_HI", REG_MMIO, 0xc086, &mmCP_DMA_PFP_SRC_ADDR_HI[0], sizeof(mmCP_DMA_PFP_SRC_ADDR_HI)/sizeof(mmCP_DMA_PFP_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR", REG_MMIO, 0xc087, &mmCP_DMA_PFP_DST_ADDR[0], sizeof(mmCP_DMA_PFP_DST_ADDR)/sizeof(mmCP_DMA_PFP_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR_HI", REG_MMIO, 0xc088, &mmCP_DMA_PFP_DST_ADDR_HI[0], sizeof(mmCP_DMA_PFP_DST_ADDR_HI)/sizeof(mmCP_DMA_PFP_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_COMMAND", REG_MMIO, 0xc089, &mmCP_DMA_PFP_COMMAND[0], sizeof(mmCP_DMA_PFP_COMMAND)/sizeof(mmCP_DMA_PFP_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_CNTL", REG_MMIO, 0xc08a, &mmCP_DMA_CNTL[0], sizeof(mmCP_DMA_CNTL)/sizeof(mmCP_DMA_CNTL[0]), 0, 0 },
+	{ "mmCP_DMA_READ_TAGS", REG_MMIO, 0xc08b, &mmCP_DMA_READ_TAGS[0], sizeof(mmCP_DMA_READ_TAGS)/sizeof(mmCP_DMA_READ_TAGS[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE_HI", REG_MMIO, 0xc08c, &mmCP_COHER_SIZE_HI[0], sizeof(mmCP_COHER_SIZE_HI)/sizeof(mmCP_COHER_SIZE_HI[0]), 0, 0 },
+	{ "mmCP_PFP_IB_CONTROL", REG_MMIO, 0xc08d, &mmCP_PFP_IB_CONTROL[0], sizeof(mmCP_PFP_IB_CONTROL)/sizeof(mmCP_PFP_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_PFP_LOAD_CONTROL", REG_MMIO, 0xc08e, &mmCP_PFP_LOAD_CONTROL[0], sizeof(mmCP_PFP_LOAD_CONTROL)/sizeof(mmCP_PFP_LOAD_CONTROL[0]), 0, 0 },
+	{ "mmCP_SCRATCH_INDEX", REG_MMIO, 0xc08f, &mmCP_SCRATCH_INDEX[0], sizeof(mmCP_SCRATCH_INDEX)/sizeof(mmCP_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_SCRATCH_DATA", REG_MMIO, 0xc090, &mmCP_SCRATCH_DATA[0], sizeof(mmCP_SCRATCH_DATA)/sizeof(mmCP_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_RB_OFFSET", REG_MMIO, 0xc091, &mmCP_RB_OFFSET[0], sizeof(mmCP_RB_OFFSET)/sizeof(mmCP_RB_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_OFFSET", REG_MMIO, 0xc092, &mmCP_IB1_OFFSET[0], sizeof(mmCP_IB1_OFFSET)/sizeof(mmCP_IB1_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB2_OFFSET", REG_MMIO, 0xc093, &mmCP_IB2_OFFSET[0], sizeof(mmCP_IB2_OFFSET)/sizeof(mmCP_IB2_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_BEGIN", REG_MMIO, 0xc094, &mmCP_IB1_PREAMBLE_BEGIN[0], sizeof(mmCP_IB1_PREAMBLE_BEGIN)/sizeof(mmCP_IB1_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_END", REG_MMIO, 0xc095, &mmCP_IB1_PREAMBLE_END[0], sizeof(mmCP_IB1_PREAMBLE_END)/sizeof(mmCP_IB1_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_BEGIN", REG_MMIO, 0xc096, &mmCP_IB2_PREAMBLE_BEGIN[0], sizeof(mmCP_IB2_PREAMBLE_BEGIN)/sizeof(mmCP_IB2_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_END", REG_MMIO, 0xc097, &mmCP_IB2_PREAMBLE_END[0], sizeof(mmCP_IB2_PREAMBLE_END)/sizeof(mmCP_IB2_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_CE_IB1_OFFSET", REG_MMIO, 0xc098, &mmCP_CE_IB1_OFFSET[0], sizeof(mmCP_CE_IB1_OFFSET)/sizeof(mmCP_CE_IB1_OFFSET[0]), 0, 0 },
+	{ "mmCP_CE_IB2_OFFSET", REG_MMIO, 0xc099, &mmCP_CE_IB2_OFFSET[0], sizeof(mmCP_CE_IB2_OFFSET)/sizeof(mmCP_CE_IB2_OFFSET[0]), 0, 0 },
+	{ "mmCP_CE_COUNTER", REG_MMIO, 0xc09a, &mmCP_CE_COUNTER[0], sizeof(mmCP_CE_COUNTER)/sizeof(mmCP_CE_COUNTER[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_LO", REG_MMIO, 0xc0c3, &mmCP_CE_INIT_BASE_LO[0], sizeof(mmCP_CE_INIT_BASE_LO)/sizeof(mmCP_CE_INIT_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_HI", REG_MMIO, 0xc0c4, &mmCP_CE_INIT_BASE_HI[0], sizeof(mmCP_CE_INIT_BASE_HI)/sizeof(mmCP_CE_INIT_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BUFSZ", REG_MMIO, 0xc0c5, &mmCP_CE_INIT_BUFSZ[0], sizeof(mmCP_CE_INIT_BUFSZ)/sizeof(mmCP_CE_INIT_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_LO", REG_MMIO, 0xc0c6, &mmCP_CE_IB1_BASE_LO[0], sizeof(mmCP_CE_IB1_BASE_LO)/sizeof(mmCP_CE_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_HI", REG_MMIO, 0xc0c7, &mmCP_CE_IB1_BASE_HI[0], sizeof(mmCP_CE_IB1_BASE_HI)/sizeof(mmCP_CE_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BUFSZ", REG_MMIO, 0xc0c8, &mmCP_CE_IB1_BUFSZ[0], sizeof(mmCP_CE_IB1_BUFSZ)/sizeof(mmCP_CE_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_LO", REG_MMIO, 0xc0c9, &mmCP_CE_IB2_BASE_LO[0], sizeof(mmCP_CE_IB2_BASE_LO)/sizeof(mmCP_CE_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_HI", REG_MMIO, 0xc0ca, &mmCP_CE_IB2_BASE_HI[0], sizeof(mmCP_CE_IB2_BASE_HI)/sizeof(mmCP_CE_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BUFSZ", REG_MMIO, 0xc0cb, &mmCP_CE_IB2_BUFSZ[0], sizeof(mmCP_CE_IB2_BUFSZ)/sizeof(mmCP_CE_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_LO", REG_MMIO, 0xc0cc, &mmCP_IB1_BASE_LO[0], sizeof(mmCP_IB1_BASE_LO)/sizeof(mmCP_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_HI", REG_MMIO, 0xc0cd, &mmCP_IB1_BASE_HI[0], sizeof(mmCP_IB1_BASE_HI)/sizeof(mmCP_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB1_BUFSZ", REG_MMIO, 0xc0ce, &mmCP_IB1_BUFSZ[0], sizeof(mmCP_IB1_BUFSZ)/sizeof(mmCP_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_LO", REG_MMIO, 0xc0cf, &mmCP_IB2_BASE_LO[0], sizeof(mmCP_IB2_BASE_LO)/sizeof(mmCP_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_HI", REG_MMIO, 0xc0d0, &mmCP_IB2_BASE_HI[0], sizeof(mmCP_IB2_BASE_HI)/sizeof(mmCP_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB2_BUFSZ", REG_MMIO, 0xc0d1, &mmCP_IB2_BUFSZ[0], sizeof(mmCP_IB2_BUFSZ)/sizeof(mmCP_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_ST_BASE_LO", REG_MMIO, 0xc0d2, &mmCP_ST_BASE_LO[0], sizeof(mmCP_ST_BASE_LO)/sizeof(mmCP_ST_BASE_LO[0]), 0, 0 },
+	{ "mmCP_ST_BASE_HI", REG_MMIO, 0xc0d3, &mmCP_ST_BASE_HI[0], sizeof(mmCP_ST_BASE_HI)/sizeof(mmCP_ST_BASE_HI[0]), 0, 0 },
+	{ "mmCP_ST_BUFSZ", REG_MMIO, 0xc0d4, &mmCP_ST_BUFSZ[0], sizeof(mmCP_ST_BUFSZ)/sizeof(mmCP_ST_BUFSZ[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_EVENT_CNTL", REG_MMIO, 0xc0d5, &mmCP_EOP_DONE_EVENT_CNTL[0], sizeof(mmCP_EOP_DONE_EVENT_CNTL)/sizeof(mmCP_EOP_DONE_EVENT_CNTL[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_CNTL", REG_MMIO, 0xc0d6, &mmCP_EOP_DONE_DATA_CNTL[0], sizeof(mmCP_EOP_DONE_DATA_CNTL)/sizeof(mmCP_EOP_DONE_DATA_CNTL[0]), 0, 0 },
+	{ "mmGRBM_GFX_INDEX", REG_MMIO, 0xc200, &mmGRBM_GFX_INDEX[0], sizeof(mmGRBM_GFX_INDEX)/sizeof(mmGRBM_GFX_INDEX[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_SIZE", REG_MMIO, 0xc240, &mmVGT_ESGS_RING_SIZE[0], sizeof(mmVGT_ESGS_RING_SIZE)/sizeof(mmVGT_ESGS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_SIZE", REG_MMIO, 0xc241, &mmVGT_GSVS_RING_SIZE[0], sizeof(mmVGT_GSVS_RING_SIZE)/sizeof(mmVGT_GSVS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVE_TYPE", REG_MMIO, 0xc242, &mmVGT_PRIMITIVE_TYPE[0], sizeof(mmVGT_PRIMITIVE_TYPE)/sizeof(mmVGT_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_INDEX_TYPE", REG_MMIO, 0xc243, &mmVGT_INDEX_TYPE[0], sizeof(mmVGT_INDEX_TYPE)/sizeof(mmVGT_INDEX_TYPE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0", REG_MMIO, 0xc244, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1", REG_MMIO, 0xc245, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2", REG_MMIO, 0xc246, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3", REG_MMIO, 0xc247, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_NUM_INDICES", REG_MMIO, 0xc24c, &mmVGT_NUM_INDICES[0], sizeof(mmVGT_NUM_INDICES)/sizeof(mmVGT_NUM_INDICES[0]), 0, 0 },
+	{ "mmVGT_NUM_INSTANCES", REG_MMIO, 0xc24d, &mmVGT_NUM_INSTANCES[0], sizeof(mmVGT_NUM_INSTANCES)/sizeof(mmVGT_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_TF_RING_SIZE", REG_MMIO, 0xc24e, &mmVGT_TF_RING_SIZE[0], sizeof(mmVGT_TF_RING_SIZE)/sizeof(mmVGT_TF_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_HS_OFFCHIP_PARAM", REG_MMIO, 0xc24f, &mmVGT_HS_OFFCHIP_PARAM[0], sizeof(mmVGT_HS_OFFCHIP_PARAM)/sizeof(mmVGT_HS_OFFCHIP_PARAM[0]), 0, 0 },
+	{ "mmVGT_TF_MEMORY_BASE", REG_MMIO, 0xc250, &mmVGT_TF_MEMORY_BASE[0], sizeof(mmVGT_TF_MEMORY_BASE)/sizeof(mmVGT_TF_MEMORY_BASE[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_VALUE", REG_MMIO, 0xc280, &mmPA_SU_LINE_STIPPLE_VALUE[0], sizeof(mmPA_SU_LINE_STIPPLE_VALUE)/sizeof(mmPA_SU_LINE_STIPPLE_VALUE[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE_STATE", REG_MMIO, 0xc281, &mmPA_SC_LINE_STIPPLE_STATE[0], sizeof(mmPA_SC_LINE_STIPPLE_STATE)/sizeof(mmPA_SC_LINE_STIPPLE_STATE[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MIN_0", REG_MMIO, 0xc284, &mmPA_SC_SCREEN_EXTENT_MIN_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MAX_0", REG_MMIO, 0xc285, &mmPA_SC_SCREEN_EXTENT_MAX_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MIN_1", REG_MMIO, 0xc286, &mmPA_SC_SCREEN_EXTENT_MIN_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MAX_1", REG_MMIO, 0xc28b, &mmPA_SC_SCREEN_EXTENT_MAX_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a0, &mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a1, &mmPA_SC_P3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_V", REG_MMIO, 0xc2a2, &mmPA_SC_P3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2a3, &mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2a4, &mmPA_SC_P3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a8, &mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a9, &mmPA_SC_HP3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_V", REG_MMIO, 0xc2aa, &mmPA_SC_HP3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2ab, &mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2ac, &mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2b0, &mmPA_SC_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_H", REG_MMIO, 0xc2b1, &mmPA_SC_TRAP_SCREEN_H[0], sizeof(mmPA_SC_TRAP_SCREEN_H)/sizeof(mmPA_SC_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_V", REG_MMIO, 0xc2b2, &mmPA_SC_TRAP_SCREEN_V[0], sizeof(mmPA_SC_TRAP_SCREEN_V)/sizeof(mmPA_SC_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2b3, &mmPA_SC_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2b4, &mmPA_SC_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_0", REG_MMIO, 0xc340, &mmSQ_THREAD_TRACE_USERDATA_0[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_0)/sizeof(mmSQ_THREAD_TRACE_USERDATA_0[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_1", REG_MMIO, 0xc341, &mmSQ_THREAD_TRACE_USERDATA_1[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_1)/sizeof(mmSQ_THREAD_TRACE_USERDATA_1[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_2", REG_MMIO, 0xc342, &mmSQ_THREAD_TRACE_USERDATA_2[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_2)/sizeof(mmSQ_THREAD_TRACE_USERDATA_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_3", REG_MMIO, 0xc343, &mmSQ_THREAD_TRACE_USERDATA_3[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_3)/sizeof(mmSQ_THREAD_TRACE_USERDATA_3[0]), 0, 0 },
+	{ "mmSQC_CACHES", REG_MMIO, 0xc348, &mmSQC_CACHES[0], sizeof(mmSQC_CACHES)/sizeof(mmSQC_CACHES[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR", REG_MMIO, 0xc380, &mmTA_CS_BC_BASE_ADDR[0], sizeof(mmTA_CS_BC_BASE_ADDR)/sizeof(mmTA_CS_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR_HI", REG_MMIO, 0xc381, &mmTA_CS_BC_BASE_ADDR_HI[0], sizeof(mmTA_CS_BC_BASE_ADDR_HI)/sizeof(mmTA_CS_BC_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT0_LOW", REG_MMIO, 0xc3c0, &mmDB_OCCLUSION_COUNT0_LOW[0], sizeof(mmDB_OCCLUSION_COUNT0_LOW)/sizeof(mmDB_OCCLUSION_COUNT0_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT0_HI", REG_MMIO, 0xc3c1, &mmDB_OCCLUSION_COUNT0_HI[0], sizeof(mmDB_OCCLUSION_COUNT0_HI)/sizeof(mmDB_OCCLUSION_COUNT0_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT1_LOW", REG_MMIO, 0xc3c2, &mmDB_OCCLUSION_COUNT1_LOW[0], sizeof(mmDB_OCCLUSION_COUNT1_LOW)/sizeof(mmDB_OCCLUSION_COUNT1_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT1_HI", REG_MMIO, 0xc3c3, &mmDB_OCCLUSION_COUNT1_HI[0], sizeof(mmDB_OCCLUSION_COUNT1_HI)/sizeof(mmDB_OCCLUSION_COUNT1_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT2_LOW", REG_MMIO, 0xc3c4, &mmDB_OCCLUSION_COUNT2_LOW[0], sizeof(mmDB_OCCLUSION_COUNT2_LOW)/sizeof(mmDB_OCCLUSION_COUNT2_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT2_HI", REG_MMIO, 0xc3c5, &mmDB_OCCLUSION_COUNT2_HI[0], sizeof(mmDB_OCCLUSION_COUNT2_HI)/sizeof(mmDB_OCCLUSION_COUNT2_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT3_LOW", REG_MMIO, 0xc3c6, &mmDB_OCCLUSION_COUNT3_LOW[0], sizeof(mmDB_OCCLUSION_COUNT3_LOW)/sizeof(mmDB_OCCLUSION_COUNT3_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT3_HI", REG_MMIO, 0xc3c7, &mmDB_OCCLUSION_COUNT3_HI[0], sizeof(mmDB_OCCLUSION_COUNT3_HI)/sizeof(mmDB_OCCLUSION_COUNT3_HI[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_LOW", REG_MMIO, 0xc3fe, &mmDB_ZPASS_COUNT_LOW[0], sizeof(mmDB_ZPASS_COUNT_LOW)/sizeof(mmDB_ZPASS_COUNT_LOW[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_HI", REG_MMIO, 0xc3ff, &mmDB_ZPASS_COUNT_HI[0], sizeof(mmDB_ZPASS_COUNT_HI)/sizeof(mmDB_ZPASS_COUNT_HI[0]), 0, 0 },
+	{ "mmGDS_RD_ADDR", REG_MMIO, 0xc400, &mmGDS_RD_ADDR[0], sizeof(mmGDS_RD_ADDR)/sizeof(mmGDS_RD_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_DATA", REG_MMIO, 0xc401, &mmGDS_RD_DATA[0], sizeof(mmGDS_RD_DATA)/sizeof(mmGDS_RD_DATA[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_ADDR", REG_MMIO, 0xc402, &mmGDS_RD_BURST_ADDR[0], sizeof(mmGDS_RD_BURST_ADDR)/sizeof(mmGDS_RD_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_COUNT", REG_MMIO, 0xc403, &mmGDS_RD_BURST_COUNT[0], sizeof(mmGDS_RD_BURST_COUNT)/sizeof(mmGDS_RD_BURST_COUNT[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_DATA", REG_MMIO, 0xc404, &mmGDS_RD_BURST_DATA[0], sizeof(mmGDS_RD_BURST_DATA)/sizeof(mmGDS_RD_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_ADDR", REG_MMIO, 0xc405, &mmGDS_WR_ADDR[0], sizeof(mmGDS_WR_ADDR)/sizeof(mmGDS_WR_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_DATA", REG_MMIO, 0xc406, &mmGDS_WR_DATA[0], sizeof(mmGDS_WR_DATA)/sizeof(mmGDS_WR_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_ADDR", REG_MMIO, 0xc407, &mmGDS_WR_BURST_ADDR[0], sizeof(mmGDS_WR_BURST_ADDR)/sizeof(mmGDS_WR_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_DATA", REG_MMIO, 0xc408, &mmGDS_WR_BURST_DATA[0], sizeof(mmGDS_WR_BURST_DATA)/sizeof(mmGDS_WR_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WRITE_COMPLETE", REG_MMIO, 0xc409, &mmGDS_WRITE_COMPLETE[0], sizeof(mmGDS_WRITE_COMPLETE)/sizeof(mmGDS_WRITE_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_CNTL", REG_MMIO, 0xc40a, &mmGDS_ATOM_CNTL[0], sizeof(mmGDS_ATOM_CNTL)/sizeof(mmGDS_ATOM_CNTL[0]), 0, 0 },
+	{ "mmGDS_ATOM_COMPLETE", REG_MMIO, 0xc40b, &mmGDS_ATOM_COMPLETE[0], sizeof(mmGDS_ATOM_COMPLETE)/sizeof(mmGDS_ATOM_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_BASE", REG_MMIO, 0xc40c, &mmGDS_ATOM_BASE[0], sizeof(mmGDS_ATOM_BASE)/sizeof(mmGDS_ATOM_BASE[0]), 0, 0 },
+	{ "mmGDS_ATOM_SIZE", REG_MMIO, 0xc40d, &mmGDS_ATOM_SIZE[0], sizeof(mmGDS_ATOM_SIZE)/sizeof(mmGDS_ATOM_SIZE[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET0", REG_MMIO, 0xc40e, &mmGDS_ATOM_OFFSET0[0], sizeof(mmGDS_ATOM_OFFSET0)/sizeof(mmGDS_ATOM_OFFSET0[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET1", REG_MMIO, 0xc40f, &mmGDS_ATOM_OFFSET1[0], sizeof(mmGDS_ATOM_OFFSET1)/sizeof(mmGDS_ATOM_OFFSET1[0]), 0, 0 },
+	{ "mmGDS_ATOM_DST", REG_MMIO, 0xc410, &mmGDS_ATOM_DST[0], sizeof(mmGDS_ATOM_DST)/sizeof(mmGDS_ATOM_DST[0]), 0, 0 },
+	{ "mmGDS_ATOM_OP", REG_MMIO, 0xc411, &mmGDS_ATOM_OP[0], sizeof(mmGDS_ATOM_OP)/sizeof(mmGDS_ATOM_OP[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0", REG_MMIO, 0xc412, &mmGDS_ATOM_SRC0[0], sizeof(mmGDS_ATOM_SRC0)/sizeof(mmGDS_ATOM_SRC0[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0_U", REG_MMIO, 0xc413, &mmGDS_ATOM_SRC0_U[0], sizeof(mmGDS_ATOM_SRC0_U)/sizeof(mmGDS_ATOM_SRC0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1", REG_MMIO, 0xc414, &mmGDS_ATOM_SRC1[0], sizeof(mmGDS_ATOM_SRC1)/sizeof(mmGDS_ATOM_SRC1[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1_U", REG_MMIO, 0xc415, &mmGDS_ATOM_SRC1_U[0], sizeof(mmGDS_ATOM_SRC1_U)/sizeof(mmGDS_ATOM_SRC1_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0", REG_MMIO, 0xc416, &mmGDS_ATOM_READ0[0], sizeof(mmGDS_ATOM_READ0)/sizeof(mmGDS_ATOM_READ0[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0_U", REG_MMIO, 0xc417, &mmGDS_ATOM_READ0_U[0], sizeof(mmGDS_ATOM_READ0_U)/sizeof(mmGDS_ATOM_READ0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1", REG_MMIO, 0xc418, &mmGDS_ATOM_READ1[0], sizeof(mmGDS_ATOM_READ1)/sizeof(mmGDS_ATOM_READ1[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1_U", REG_MMIO, 0xc419, &mmGDS_ATOM_READ1_U[0], sizeof(mmGDS_ATOM_READ1_U)/sizeof(mmGDS_ATOM_READ1_U[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNTL", REG_MMIO, 0xc41a, &mmGDS_GWS_RESOURCE_CNTL[0], sizeof(mmGDS_GWS_RESOURCE_CNTL)/sizeof(mmGDS_GWS_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE", REG_MMIO, 0xc41b, &mmGDS_GWS_RESOURCE[0], sizeof(mmGDS_GWS_RESOURCE)/sizeof(mmGDS_GWS_RESOURCE[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNT", REG_MMIO, 0xc41c, &mmGDS_GWS_RESOURCE_CNT[0], sizeof(mmGDS_GWS_RESOURCE_CNT)/sizeof(mmGDS_GWS_RESOURCE_CNT[0]), 0, 0 },
+	{ "mmGDS_OA_CNTL", REG_MMIO, 0xc41d, &mmGDS_OA_CNTL[0], sizeof(mmGDS_OA_CNTL)/sizeof(mmGDS_OA_CNTL[0]), 0, 0 },
+	{ "mmGDS_OA_COUNTER", REG_MMIO, 0xc41e, &mmGDS_OA_COUNTER[0], sizeof(mmGDS_OA_COUNTER)/sizeof(mmGDS_OA_COUNTER[0]), 0, 0 },
+	{ "mmGDS_OA_ADDRESS", REG_MMIO, 0xc41f, &mmGDS_OA_ADDRESS[0], sizeof(mmGDS_OA_ADDRESS)/sizeof(mmGDS_OA_ADDRESS[0]), 0, 0 },
+	{ "mmGDS_OA_INCDEC", REG_MMIO, 0xc420, &mmGDS_OA_INCDEC[0], sizeof(mmGDS_OA_INCDEC)/sizeof(mmGDS_OA_INCDEC[0]), 0, 0 },
+	{ "mmGDS_OA_RING_SIZE", REG_MMIO, 0xc421, &mmGDS_OA_RING_SIZE[0], sizeof(mmGDS_OA_RING_SIZE)/sizeof(mmGDS_OA_RING_SIZE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG13", REG_SMC, 0xd, &ixCLIPPER_DEBUG_REG13[0], sizeof(ixCLIPPER_DEBUG_REG13)/sizeof(ixCLIPPER_DEBUG_REG13[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG13", REG_SMC, 0xd, &ixVGT_DEBUG_REG13[0], sizeof(ixVGT_DEBUG_REG13)/sizeof(ixVGT_DEBUG_REG13[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_LO", REG_MMIO, 0xd000, &mmCPG_PERFCOUNTER1_LO[0], sizeof(mmCPG_PERFCOUNTER1_LO)/sizeof(mmCPG_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_HI", REG_MMIO, 0xd001, &mmCPG_PERFCOUNTER1_HI[0], sizeof(mmCPG_PERFCOUNTER1_HI)/sizeof(mmCPG_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_LO", REG_MMIO, 0xd002, &mmCPG_PERFCOUNTER0_LO[0], sizeof(mmCPG_PERFCOUNTER0_LO)/sizeof(mmCPG_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_HI", REG_MMIO, 0xd003, &mmCPG_PERFCOUNTER0_HI[0], sizeof(mmCPG_PERFCOUNTER0_HI)/sizeof(mmCPG_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_LO", REG_MMIO, 0xd004, &mmCPC_PERFCOUNTER1_LO[0], sizeof(mmCPC_PERFCOUNTER1_LO)/sizeof(mmCPC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_HI", REG_MMIO, 0xd005, &mmCPC_PERFCOUNTER1_HI[0], sizeof(mmCPC_PERFCOUNTER1_HI)/sizeof(mmCPC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_LO", REG_MMIO, 0xd006, &mmCPC_PERFCOUNTER0_LO[0], sizeof(mmCPC_PERFCOUNTER0_LO)/sizeof(mmCPC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_HI", REG_MMIO, 0xd007, &mmCPC_PERFCOUNTER0_HI[0], sizeof(mmCPC_PERFCOUNTER0_HI)/sizeof(mmCPC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_LO", REG_MMIO, 0xd008, &mmCPF_PERFCOUNTER1_LO[0], sizeof(mmCPF_PERFCOUNTER1_LO)/sizeof(mmCPF_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_HI", REG_MMIO, 0xd009, &mmCPF_PERFCOUNTER1_HI[0], sizeof(mmCPF_PERFCOUNTER1_HI)/sizeof(mmCPF_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_LO", REG_MMIO, 0xd00a, &mmCPF_PERFCOUNTER0_LO[0], sizeof(mmCPF_PERFCOUNTER0_LO)/sizeof(mmCPF_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_HI", REG_MMIO, 0xd00b, &mmCPF_PERFCOUNTER0_HI[0], sizeof(mmCPF_PERFCOUNTER0_HI)/sizeof(mmCPF_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_LO", REG_MMIO, 0xd040, &mmGRBM_PERFCOUNTER0_LO[0], sizeof(mmGRBM_PERFCOUNTER0_LO)/sizeof(mmGRBM_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_HI", REG_MMIO, 0xd041, &mmGRBM_PERFCOUNTER0_HI[0], sizeof(mmGRBM_PERFCOUNTER0_HI)/sizeof(mmGRBM_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_LO", REG_MMIO, 0xd043, &mmGRBM_PERFCOUNTER1_LO[0], sizeof(mmGRBM_PERFCOUNTER1_LO)/sizeof(mmGRBM_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_HI", REG_MMIO, 0xd044, &mmGRBM_PERFCOUNTER1_HI[0], sizeof(mmGRBM_PERFCOUNTER1_HI)/sizeof(mmGRBM_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_LO", REG_MMIO, 0xd045, &mmGRBM_SE0_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE0_PERFCOUNTER_LO)/sizeof(mmGRBM_SE0_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_HI", REG_MMIO, 0xd046, &mmGRBM_SE0_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE0_PERFCOUNTER_HI)/sizeof(mmGRBM_SE0_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_LO", REG_MMIO, 0xd047, &mmGRBM_SE1_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE1_PERFCOUNTER_LO)/sizeof(mmGRBM_SE1_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_HI", REG_MMIO, 0xd048, &mmGRBM_SE1_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE1_PERFCOUNTER_HI)/sizeof(mmGRBM_SE1_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_LO", REG_MMIO, 0xd049, &mmGRBM_SE2_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE2_PERFCOUNTER_LO)/sizeof(mmGRBM_SE2_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_HI", REG_MMIO, 0xd04a, &mmGRBM_SE2_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE2_PERFCOUNTER_HI)/sizeof(mmGRBM_SE2_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_LO", REG_MMIO, 0xd04b, &mmGRBM_SE3_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE3_PERFCOUNTER_LO)/sizeof(mmGRBM_SE3_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_HI", REG_MMIO, 0xd04c, &mmGRBM_SE3_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE3_PERFCOUNTER_HI)/sizeof(mmGRBM_SE3_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_LO", REG_MMIO, 0xd080, &mmWD_PERFCOUNTER0_LO[0], sizeof(mmWD_PERFCOUNTER0_LO)/sizeof(mmWD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_HI", REG_MMIO, 0xd081, &mmWD_PERFCOUNTER0_HI[0], sizeof(mmWD_PERFCOUNTER0_HI)/sizeof(mmWD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_LO", REG_MMIO, 0xd082, &mmWD_PERFCOUNTER1_LO[0], sizeof(mmWD_PERFCOUNTER1_LO)/sizeof(mmWD_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_HI", REG_MMIO, 0xd083, &mmWD_PERFCOUNTER1_HI[0], sizeof(mmWD_PERFCOUNTER1_HI)/sizeof(mmWD_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_LO", REG_MMIO, 0xd084, &mmWD_PERFCOUNTER2_LO[0], sizeof(mmWD_PERFCOUNTER2_LO)/sizeof(mmWD_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_HI", REG_MMIO, 0xd085, &mmWD_PERFCOUNTER2_HI[0], sizeof(mmWD_PERFCOUNTER2_HI)/sizeof(mmWD_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_LO", REG_MMIO, 0xd086, &mmWD_PERFCOUNTER3_LO[0], sizeof(mmWD_PERFCOUNTER3_LO)/sizeof(mmWD_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_HI", REG_MMIO, 0xd087, &mmWD_PERFCOUNTER3_HI[0], sizeof(mmWD_PERFCOUNTER3_HI)/sizeof(mmWD_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_LO", REG_MMIO, 0xd088, &mmIA_PERFCOUNTER0_LO[0], sizeof(mmIA_PERFCOUNTER0_LO)/sizeof(mmIA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_HI", REG_MMIO, 0xd089, &mmIA_PERFCOUNTER0_HI[0], sizeof(mmIA_PERFCOUNTER0_HI)/sizeof(mmIA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_LO", REG_MMIO, 0xd08a, &mmIA_PERFCOUNTER1_LO[0], sizeof(mmIA_PERFCOUNTER1_LO)/sizeof(mmIA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_HI", REG_MMIO, 0xd08b, &mmIA_PERFCOUNTER1_HI[0], sizeof(mmIA_PERFCOUNTER1_HI)/sizeof(mmIA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_LO", REG_MMIO, 0xd08c, &mmIA_PERFCOUNTER2_LO[0], sizeof(mmIA_PERFCOUNTER2_LO)/sizeof(mmIA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_HI", REG_MMIO, 0xd08d, &mmIA_PERFCOUNTER2_HI[0], sizeof(mmIA_PERFCOUNTER2_HI)/sizeof(mmIA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_LO", REG_MMIO, 0xd08e, &mmIA_PERFCOUNTER3_LO[0], sizeof(mmIA_PERFCOUNTER3_LO)/sizeof(mmIA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_HI", REG_MMIO, 0xd08f, &mmIA_PERFCOUNTER3_HI[0], sizeof(mmIA_PERFCOUNTER3_HI)/sizeof(mmIA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_LO", REG_MMIO, 0xd090, &mmVGT_PERFCOUNTER0_LO[0], sizeof(mmVGT_PERFCOUNTER0_LO)/sizeof(mmVGT_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_HI", REG_MMIO, 0xd091, &mmVGT_PERFCOUNTER0_HI[0], sizeof(mmVGT_PERFCOUNTER0_HI)/sizeof(mmVGT_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_LO", REG_MMIO, 0xd092, &mmVGT_PERFCOUNTER1_LO[0], sizeof(mmVGT_PERFCOUNTER1_LO)/sizeof(mmVGT_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_HI", REG_MMIO, 0xd093, &mmVGT_PERFCOUNTER1_HI[0], sizeof(mmVGT_PERFCOUNTER1_HI)/sizeof(mmVGT_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_LO", REG_MMIO, 0xd094, &mmVGT_PERFCOUNTER2_LO[0], sizeof(mmVGT_PERFCOUNTER2_LO)/sizeof(mmVGT_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_HI", REG_MMIO, 0xd095, &mmVGT_PERFCOUNTER2_HI[0], sizeof(mmVGT_PERFCOUNTER2_HI)/sizeof(mmVGT_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_LO", REG_MMIO, 0xd096, &mmVGT_PERFCOUNTER3_LO[0], sizeof(mmVGT_PERFCOUNTER3_LO)/sizeof(mmVGT_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_HI", REG_MMIO, 0xd097, &mmVGT_PERFCOUNTER3_HI[0], sizeof(mmVGT_PERFCOUNTER3_HI)/sizeof(mmVGT_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_LO", REG_MMIO, 0xd100, &mmPA_SU_PERFCOUNTER0_LO[0], sizeof(mmPA_SU_PERFCOUNTER0_LO)/sizeof(mmPA_SU_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_HI", REG_MMIO, 0xd101, &mmPA_SU_PERFCOUNTER0_HI[0], sizeof(mmPA_SU_PERFCOUNTER0_HI)/sizeof(mmPA_SU_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_LO", REG_MMIO, 0xd102, &mmPA_SU_PERFCOUNTER1_LO[0], sizeof(mmPA_SU_PERFCOUNTER1_LO)/sizeof(mmPA_SU_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_HI", REG_MMIO, 0xd103, &mmPA_SU_PERFCOUNTER1_HI[0], sizeof(mmPA_SU_PERFCOUNTER1_HI)/sizeof(mmPA_SU_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_LO", REG_MMIO, 0xd104, &mmPA_SU_PERFCOUNTER2_LO[0], sizeof(mmPA_SU_PERFCOUNTER2_LO)/sizeof(mmPA_SU_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_HI", REG_MMIO, 0xd105, &mmPA_SU_PERFCOUNTER2_HI[0], sizeof(mmPA_SU_PERFCOUNTER2_HI)/sizeof(mmPA_SU_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_LO", REG_MMIO, 0xd106, &mmPA_SU_PERFCOUNTER3_LO[0], sizeof(mmPA_SU_PERFCOUNTER3_LO)/sizeof(mmPA_SU_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_HI", REG_MMIO, 0xd107, &mmPA_SU_PERFCOUNTER3_HI[0], sizeof(mmPA_SU_PERFCOUNTER3_HI)/sizeof(mmPA_SU_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_LO", REG_MMIO, 0xd140, &mmPA_SC_PERFCOUNTER0_LO[0], sizeof(mmPA_SC_PERFCOUNTER0_LO)/sizeof(mmPA_SC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_HI", REG_MMIO, 0xd141, &mmPA_SC_PERFCOUNTER0_HI[0], sizeof(mmPA_SC_PERFCOUNTER0_HI)/sizeof(mmPA_SC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_LO", REG_MMIO, 0xd142, &mmPA_SC_PERFCOUNTER1_LO[0], sizeof(mmPA_SC_PERFCOUNTER1_LO)/sizeof(mmPA_SC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_HI", REG_MMIO, 0xd143, &mmPA_SC_PERFCOUNTER1_HI[0], sizeof(mmPA_SC_PERFCOUNTER1_HI)/sizeof(mmPA_SC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_LO", REG_MMIO, 0xd144, &mmPA_SC_PERFCOUNTER2_LO[0], sizeof(mmPA_SC_PERFCOUNTER2_LO)/sizeof(mmPA_SC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_HI", REG_MMIO, 0xd145, &mmPA_SC_PERFCOUNTER2_HI[0], sizeof(mmPA_SC_PERFCOUNTER2_HI)/sizeof(mmPA_SC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_LO", REG_MMIO, 0xd146, &mmPA_SC_PERFCOUNTER3_LO[0], sizeof(mmPA_SC_PERFCOUNTER3_LO)/sizeof(mmPA_SC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_HI", REG_MMIO, 0xd147, &mmPA_SC_PERFCOUNTER3_HI[0], sizeof(mmPA_SC_PERFCOUNTER3_HI)/sizeof(mmPA_SC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_LO", REG_MMIO, 0xd148, &mmPA_SC_PERFCOUNTER4_LO[0], sizeof(mmPA_SC_PERFCOUNTER4_LO)/sizeof(mmPA_SC_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_HI", REG_MMIO, 0xd149, &mmPA_SC_PERFCOUNTER4_HI[0], sizeof(mmPA_SC_PERFCOUNTER4_HI)/sizeof(mmPA_SC_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_LO", REG_MMIO, 0xd14a, &mmPA_SC_PERFCOUNTER5_LO[0], sizeof(mmPA_SC_PERFCOUNTER5_LO)/sizeof(mmPA_SC_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_HI", REG_MMIO, 0xd14b, &mmPA_SC_PERFCOUNTER5_HI[0], sizeof(mmPA_SC_PERFCOUNTER5_HI)/sizeof(mmPA_SC_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_LO", REG_MMIO, 0xd14c, &mmPA_SC_PERFCOUNTER6_LO[0], sizeof(mmPA_SC_PERFCOUNTER6_LO)/sizeof(mmPA_SC_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_HI", REG_MMIO, 0xd14d, &mmPA_SC_PERFCOUNTER6_HI[0], sizeof(mmPA_SC_PERFCOUNTER6_HI)/sizeof(mmPA_SC_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_LO", REG_MMIO, 0xd14e, &mmPA_SC_PERFCOUNTER7_LO[0], sizeof(mmPA_SC_PERFCOUNTER7_LO)/sizeof(mmPA_SC_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_HI", REG_MMIO, 0xd14f, &mmPA_SC_PERFCOUNTER7_HI[0], sizeof(mmPA_SC_PERFCOUNTER7_HI)/sizeof(mmPA_SC_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_HI", REG_MMIO, 0xd180, &mmSPI_PERFCOUNTER0_HI[0], sizeof(mmSPI_PERFCOUNTER0_HI)/sizeof(mmSPI_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_LO", REG_MMIO, 0xd181, &mmSPI_PERFCOUNTER0_LO[0], sizeof(mmSPI_PERFCOUNTER0_LO)/sizeof(mmSPI_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_HI", REG_MMIO, 0xd182, &mmSPI_PERFCOUNTER1_HI[0], sizeof(mmSPI_PERFCOUNTER1_HI)/sizeof(mmSPI_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_LO", REG_MMIO, 0xd183, &mmSPI_PERFCOUNTER1_LO[0], sizeof(mmSPI_PERFCOUNTER1_LO)/sizeof(mmSPI_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_HI", REG_MMIO, 0xd184, &mmSPI_PERFCOUNTER2_HI[0], sizeof(mmSPI_PERFCOUNTER2_HI)/sizeof(mmSPI_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_LO", REG_MMIO, 0xd185, &mmSPI_PERFCOUNTER2_LO[0], sizeof(mmSPI_PERFCOUNTER2_LO)/sizeof(mmSPI_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_HI", REG_MMIO, 0xd186, &mmSPI_PERFCOUNTER3_HI[0], sizeof(mmSPI_PERFCOUNTER3_HI)/sizeof(mmSPI_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_LO", REG_MMIO, 0xd187, &mmSPI_PERFCOUNTER3_LO[0], sizeof(mmSPI_PERFCOUNTER3_LO)/sizeof(mmSPI_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_HI", REG_MMIO, 0xd188, &mmSPI_PERFCOUNTER4_HI[0], sizeof(mmSPI_PERFCOUNTER4_HI)/sizeof(mmSPI_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_LO", REG_MMIO, 0xd189, &mmSPI_PERFCOUNTER4_LO[0], sizeof(mmSPI_PERFCOUNTER4_LO)/sizeof(mmSPI_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_HI", REG_MMIO, 0xd18a, &mmSPI_PERFCOUNTER5_HI[0], sizeof(mmSPI_PERFCOUNTER5_HI)/sizeof(mmSPI_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_LO", REG_MMIO, 0xd18b, &mmSPI_PERFCOUNTER5_LO[0], sizeof(mmSPI_PERFCOUNTER5_LO)/sizeof(mmSPI_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_LO", REG_MMIO, 0xd1c0, &mmSQ_PERFCOUNTER0_LO[0], sizeof(mmSQ_PERFCOUNTER0_LO)/sizeof(mmSQ_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_HI", REG_MMIO, 0xd1c1, &mmSQ_PERFCOUNTER0_HI[0], sizeof(mmSQ_PERFCOUNTER0_HI)/sizeof(mmSQ_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_LO", REG_MMIO, 0xd1c2, &mmSQ_PERFCOUNTER1_LO[0], sizeof(mmSQ_PERFCOUNTER1_LO)/sizeof(mmSQ_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_HI", REG_MMIO, 0xd1c3, &mmSQ_PERFCOUNTER1_HI[0], sizeof(mmSQ_PERFCOUNTER1_HI)/sizeof(mmSQ_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_LO", REG_MMIO, 0xd1c4, &mmSQ_PERFCOUNTER2_LO[0], sizeof(mmSQ_PERFCOUNTER2_LO)/sizeof(mmSQ_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_HI", REG_MMIO, 0xd1c5, &mmSQ_PERFCOUNTER2_HI[0], sizeof(mmSQ_PERFCOUNTER2_HI)/sizeof(mmSQ_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_LO", REG_MMIO, 0xd1c6, &mmSQ_PERFCOUNTER3_LO[0], sizeof(mmSQ_PERFCOUNTER3_LO)/sizeof(mmSQ_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_HI", REG_MMIO, 0xd1c7, &mmSQ_PERFCOUNTER3_HI[0], sizeof(mmSQ_PERFCOUNTER3_HI)/sizeof(mmSQ_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_LO", REG_MMIO, 0xd1c8, &mmSQ_PERFCOUNTER4_LO[0], sizeof(mmSQ_PERFCOUNTER4_LO)/sizeof(mmSQ_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_HI", REG_MMIO, 0xd1c9, &mmSQ_PERFCOUNTER4_HI[0], sizeof(mmSQ_PERFCOUNTER4_HI)/sizeof(mmSQ_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_LO", REG_MMIO, 0xd1ca, &mmSQ_PERFCOUNTER5_LO[0], sizeof(mmSQ_PERFCOUNTER5_LO)/sizeof(mmSQ_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_HI", REG_MMIO, 0xd1cb, &mmSQ_PERFCOUNTER5_HI[0], sizeof(mmSQ_PERFCOUNTER5_HI)/sizeof(mmSQ_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_LO", REG_MMIO, 0xd1cc, &mmSQ_PERFCOUNTER6_LO[0], sizeof(mmSQ_PERFCOUNTER6_LO)/sizeof(mmSQ_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_HI", REG_MMIO, 0xd1cd, &mmSQ_PERFCOUNTER6_HI[0], sizeof(mmSQ_PERFCOUNTER6_HI)/sizeof(mmSQ_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_LO", REG_MMIO, 0xd1ce, &mmSQ_PERFCOUNTER7_LO[0], sizeof(mmSQ_PERFCOUNTER7_LO)/sizeof(mmSQ_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_HI", REG_MMIO, 0xd1cf, &mmSQ_PERFCOUNTER7_HI[0], sizeof(mmSQ_PERFCOUNTER7_HI)/sizeof(mmSQ_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_LO", REG_MMIO, 0xd1d0, &mmSQ_PERFCOUNTER8_LO[0], sizeof(mmSQ_PERFCOUNTER8_LO)/sizeof(mmSQ_PERFCOUNTER8_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_HI", REG_MMIO, 0xd1d1, &mmSQ_PERFCOUNTER8_HI[0], sizeof(mmSQ_PERFCOUNTER8_HI)/sizeof(mmSQ_PERFCOUNTER8_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_LO", REG_MMIO, 0xd1d2, &mmSQ_PERFCOUNTER9_LO[0], sizeof(mmSQ_PERFCOUNTER9_LO)/sizeof(mmSQ_PERFCOUNTER9_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_HI", REG_MMIO, 0xd1d3, &mmSQ_PERFCOUNTER9_HI[0], sizeof(mmSQ_PERFCOUNTER9_HI)/sizeof(mmSQ_PERFCOUNTER9_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_LO", REG_MMIO, 0xd1d4, &mmSQ_PERFCOUNTER10_LO[0], sizeof(mmSQ_PERFCOUNTER10_LO)/sizeof(mmSQ_PERFCOUNTER10_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_HI", REG_MMIO, 0xd1d5, &mmSQ_PERFCOUNTER10_HI[0], sizeof(mmSQ_PERFCOUNTER10_HI)/sizeof(mmSQ_PERFCOUNTER10_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_LO", REG_MMIO, 0xd1d6, &mmSQ_PERFCOUNTER11_LO[0], sizeof(mmSQ_PERFCOUNTER11_LO)/sizeof(mmSQ_PERFCOUNTER11_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_HI", REG_MMIO, 0xd1d7, &mmSQ_PERFCOUNTER11_HI[0], sizeof(mmSQ_PERFCOUNTER11_HI)/sizeof(mmSQ_PERFCOUNTER11_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_LO", REG_MMIO, 0xd1d8, &mmSQ_PERFCOUNTER12_LO[0], sizeof(mmSQ_PERFCOUNTER12_LO)/sizeof(mmSQ_PERFCOUNTER12_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_HI", REG_MMIO, 0xd1d9, &mmSQ_PERFCOUNTER12_HI[0], sizeof(mmSQ_PERFCOUNTER12_HI)/sizeof(mmSQ_PERFCOUNTER12_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_LO", REG_MMIO, 0xd1da, &mmSQ_PERFCOUNTER13_LO[0], sizeof(mmSQ_PERFCOUNTER13_LO)/sizeof(mmSQ_PERFCOUNTER13_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_HI", REG_MMIO, 0xd1db, &mmSQ_PERFCOUNTER13_HI[0], sizeof(mmSQ_PERFCOUNTER13_HI)/sizeof(mmSQ_PERFCOUNTER13_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_LO", REG_MMIO, 0xd1dc, &mmSQ_PERFCOUNTER14_LO[0], sizeof(mmSQ_PERFCOUNTER14_LO)/sizeof(mmSQ_PERFCOUNTER14_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_HI", REG_MMIO, 0xd1dd, &mmSQ_PERFCOUNTER14_HI[0], sizeof(mmSQ_PERFCOUNTER14_HI)/sizeof(mmSQ_PERFCOUNTER14_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_LO", REG_MMIO, 0xd1de, &mmSQ_PERFCOUNTER15_LO[0], sizeof(mmSQ_PERFCOUNTER15_LO)/sizeof(mmSQ_PERFCOUNTER15_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_HI", REG_MMIO, 0xd1df, &mmSQ_PERFCOUNTER15_HI[0], sizeof(mmSQ_PERFCOUNTER15_HI)/sizeof(mmSQ_PERFCOUNTER15_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_LO", REG_MMIO, 0xd240, &mmSX_PERFCOUNTER0_LO[0], sizeof(mmSX_PERFCOUNTER0_LO)/sizeof(mmSX_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_HI", REG_MMIO, 0xd241, &mmSX_PERFCOUNTER0_HI[0], sizeof(mmSX_PERFCOUNTER0_HI)/sizeof(mmSX_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_LO", REG_MMIO, 0xd242, &mmSX_PERFCOUNTER1_LO[0], sizeof(mmSX_PERFCOUNTER1_LO)/sizeof(mmSX_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_HI", REG_MMIO, 0xd243, &mmSX_PERFCOUNTER1_HI[0], sizeof(mmSX_PERFCOUNTER1_HI)/sizeof(mmSX_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_LO", REG_MMIO, 0xd244, &mmSX_PERFCOUNTER2_LO[0], sizeof(mmSX_PERFCOUNTER2_LO)/sizeof(mmSX_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_HI", REG_MMIO, 0xd245, &mmSX_PERFCOUNTER2_HI[0], sizeof(mmSX_PERFCOUNTER2_HI)/sizeof(mmSX_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_LO", REG_MMIO, 0xd246, &mmSX_PERFCOUNTER3_LO[0], sizeof(mmSX_PERFCOUNTER3_LO)/sizeof(mmSX_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_HI", REG_MMIO, 0xd247, &mmSX_PERFCOUNTER3_HI[0], sizeof(mmSX_PERFCOUNTER3_HI)/sizeof(mmSX_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_LO", REG_MMIO, 0xd280, &mmGDS_PERFCOUNTER0_LO[0], sizeof(mmGDS_PERFCOUNTER0_LO)/sizeof(mmGDS_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_HI", REG_MMIO, 0xd281, &mmGDS_PERFCOUNTER0_HI[0], sizeof(mmGDS_PERFCOUNTER0_HI)/sizeof(mmGDS_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_LO", REG_MMIO, 0xd282, &mmGDS_PERFCOUNTER1_LO[0], sizeof(mmGDS_PERFCOUNTER1_LO)/sizeof(mmGDS_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_HI", REG_MMIO, 0xd283, &mmGDS_PERFCOUNTER1_HI[0], sizeof(mmGDS_PERFCOUNTER1_HI)/sizeof(mmGDS_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_LO", REG_MMIO, 0xd284, &mmGDS_PERFCOUNTER2_LO[0], sizeof(mmGDS_PERFCOUNTER2_LO)/sizeof(mmGDS_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_HI", REG_MMIO, 0xd285, &mmGDS_PERFCOUNTER2_HI[0], sizeof(mmGDS_PERFCOUNTER2_HI)/sizeof(mmGDS_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_LO", REG_MMIO, 0xd286, &mmGDS_PERFCOUNTER3_LO[0], sizeof(mmGDS_PERFCOUNTER3_LO)/sizeof(mmGDS_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_HI", REG_MMIO, 0xd287, &mmGDS_PERFCOUNTER3_HI[0], sizeof(mmGDS_PERFCOUNTER3_HI)/sizeof(mmGDS_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_LO", REG_MMIO, 0xd2c0, &mmTA_PERFCOUNTER0_LO[0], sizeof(mmTA_PERFCOUNTER0_LO)/sizeof(mmTA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_HI", REG_MMIO, 0xd2c1, &mmTA_PERFCOUNTER0_HI[0], sizeof(mmTA_PERFCOUNTER0_HI)/sizeof(mmTA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_LO", REG_MMIO, 0xd2c2, &mmTA_PERFCOUNTER1_LO[0], sizeof(mmTA_PERFCOUNTER1_LO)/sizeof(mmTA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_HI", REG_MMIO, 0xd2c3, &mmTA_PERFCOUNTER1_HI[0], sizeof(mmTA_PERFCOUNTER1_HI)/sizeof(mmTA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_LO", REG_MMIO, 0xd300, &mmTD_PERFCOUNTER0_LO[0], sizeof(mmTD_PERFCOUNTER0_LO)/sizeof(mmTD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_HI", REG_MMIO, 0xd301, &mmTD_PERFCOUNTER0_HI[0], sizeof(mmTD_PERFCOUNTER0_HI)/sizeof(mmTD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_LO", REG_MMIO, 0xd302, &mmTD_PERFCOUNTER1_LO[0], sizeof(mmTD_PERFCOUNTER1_LO)/sizeof(mmTD_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_HI", REG_MMIO, 0xd303, &mmTD_PERFCOUNTER1_HI[0], sizeof(mmTD_PERFCOUNTER1_HI)/sizeof(mmTD_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_LO", REG_MMIO, 0xd340, &mmTCP_PERFCOUNTER0_LO[0], sizeof(mmTCP_PERFCOUNTER0_LO)/sizeof(mmTCP_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_HI", REG_MMIO, 0xd341, &mmTCP_PERFCOUNTER0_HI[0], sizeof(mmTCP_PERFCOUNTER0_HI)/sizeof(mmTCP_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_LO", REG_MMIO, 0xd342, &mmTCP_PERFCOUNTER1_LO[0], sizeof(mmTCP_PERFCOUNTER1_LO)/sizeof(mmTCP_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_HI", REG_MMIO, 0xd343, &mmTCP_PERFCOUNTER1_HI[0], sizeof(mmTCP_PERFCOUNTER1_HI)/sizeof(mmTCP_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_LO", REG_MMIO, 0xd344, &mmTCP_PERFCOUNTER2_LO[0], sizeof(mmTCP_PERFCOUNTER2_LO)/sizeof(mmTCP_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_HI", REG_MMIO, 0xd345, &mmTCP_PERFCOUNTER2_HI[0], sizeof(mmTCP_PERFCOUNTER2_HI)/sizeof(mmTCP_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_LO", REG_MMIO, 0xd346, &mmTCP_PERFCOUNTER3_LO[0], sizeof(mmTCP_PERFCOUNTER3_LO)/sizeof(mmTCP_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_HI", REG_MMIO, 0xd347, &mmTCP_PERFCOUNTER3_HI[0], sizeof(mmTCP_PERFCOUNTER3_HI)/sizeof(mmTCP_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_LO", REG_MMIO, 0xd380, &mmTCC_PERFCOUNTER0_LO[0], sizeof(mmTCC_PERFCOUNTER0_LO)/sizeof(mmTCC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_HI", REG_MMIO, 0xd381, &mmTCC_PERFCOUNTER0_HI[0], sizeof(mmTCC_PERFCOUNTER0_HI)/sizeof(mmTCC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_LO", REG_MMIO, 0xd382, &mmTCC_PERFCOUNTER1_LO[0], sizeof(mmTCC_PERFCOUNTER1_LO)/sizeof(mmTCC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_HI", REG_MMIO, 0xd383, &mmTCC_PERFCOUNTER1_HI[0], sizeof(mmTCC_PERFCOUNTER1_HI)/sizeof(mmTCC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_LO", REG_MMIO, 0xd384, &mmTCC_PERFCOUNTER2_LO[0], sizeof(mmTCC_PERFCOUNTER2_LO)/sizeof(mmTCC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_HI", REG_MMIO, 0xd385, &mmTCC_PERFCOUNTER2_HI[0], sizeof(mmTCC_PERFCOUNTER2_HI)/sizeof(mmTCC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_LO", REG_MMIO, 0xd386, &mmTCC_PERFCOUNTER3_LO[0], sizeof(mmTCC_PERFCOUNTER3_LO)/sizeof(mmTCC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_HI", REG_MMIO, 0xd387, &mmTCC_PERFCOUNTER3_HI[0], sizeof(mmTCC_PERFCOUNTER3_HI)/sizeof(mmTCC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_LO", REG_MMIO, 0xd390, &mmTCA_PERFCOUNTER0_LO[0], sizeof(mmTCA_PERFCOUNTER0_LO)/sizeof(mmTCA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_HI", REG_MMIO, 0xd391, &mmTCA_PERFCOUNTER0_HI[0], sizeof(mmTCA_PERFCOUNTER0_HI)/sizeof(mmTCA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_LO", REG_MMIO, 0xd392, &mmTCA_PERFCOUNTER1_LO[0], sizeof(mmTCA_PERFCOUNTER1_LO)/sizeof(mmTCA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_HI", REG_MMIO, 0xd393, &mmTCA_PERFCOUNTER1_HI[0], sizeof(mmTCA_PERFCOUNTER1_HI)/sizeof(mmTCA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_LO", REG_MMIO, 0xd394, &mmTCA_PERFCOUNTER2_LO[0], sizeof(mmTCA_PERFCOUNTER2_LO)/sizeof(mmTCA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_HI", REG_MMIO, 0xd395, &mmTCA_PERFCOUNTER2_HI[0], sizeof(mmTCA_PERFCOUNTER2_HI)/sizeof(mmTCA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_LO", REG_MMIO, 0xd396, &mmTCA_PERFCOUNTER3_LO[0], sizeof(mmTCA_PERFCOUNTER3_LO)/sizeof(mmTCA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_HI", REG_MMIO, 0xd397, &mmTCA_PERFCOUNTER3_HI[0], sizeof(mmTCA_PERFCOUNTER3_HI)/sizeof(mmTCA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER0_LO", REG_MMIO, 0xd3a0, &mmTCS_PERFCOUNTER0_LO[0], sizeof(mmTCS_PERFCOUNTER0_LO)/sizeof(mmTCS_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER0_HI", REG_MMIO, 0xd3a1, &mmTCS_PERFCOUNTER0_HI[0], sizeof(mmTCS_PERFCOUNTER0_HI)/sizeof(mmTCS_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER1_LO", REG_MMIO, 0xd3a2, &mmTCS_PERFCOUNTER1_LO[0], sizeof(mmTCS_PERFCOUNTER1_LO)/sizeof(mmTCS_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER1_HI", REG_MMIO, 0xd3a3, &mmTCS_PERFCOUNTER1_HI[0], sizeof(mmTCS_PERFCOUNTER1_HI)/sizeof(mmTCS_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER2_LO", REG_MMIO, 0xd3a4, &mmTCS_PERFCOUNTER2_LO[0], sizeof(mmTCS_PERFCOUNTER2_LO)/sizeof(mmTCS_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER2_HI", REG_MMIO, 0xd3a5, &mmTCS_PERFCOUNTER2_HI[0], sizeof(mmTCS_PERFCOUNTER2_HI)/sizeof(mmTCS_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER3_LO", REG_MMIO, 0xd3a6, &mmTCS_PERFCOUNTER3_LO[0], sizeof(mmTCS_PERFCOUNTER3_LO)/sizeof(mmTCS_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER3_HI", REG_MMIO, 0xd3a7, &mmTCS_PERFCOUNTER3_HI[0], sizeof(mmTCS_PERFCOUNTER3_HI)/sizeof(mmTCS_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_LO", REG_MMIO, 0xd406, &mmCB_PERFCOUNTER0_LO[0], sizeof(mmCB_PERFCOUNTER0_LO)/sizeof(mmCB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_HI", REG_MMIO, 0xd407, &mmCB_PERFCOUNTER0_HI[0], sizeof(mmCB_PERFCOUNTER0_HI)/sizeof(mmCB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_LO", REG_MMIO, 0xd408, &mmCB_PERFCOUNTER1_LO[0], sizeof(mmCB_PERFCOUNTER1_LO)/sizeof(mmCB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_HI", REG_MMIO, 0xd409, &mmCB_PERFCOUNTER1_HI[0], sizeof(mmCB_PERFCOUNTER1_HI)/sizeof(mmCB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_LO", REG_MMIO, 0xd40a, &mmCB_PERFCOUNTER2_LO[0], sizeof(mmCB_PERFCOUNTER2_LO)/sizeof(mmCB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_HI", REG_MMIO, 0xd40b, &mmCB_PERFCOUNTER2_HI[0], sizeof(mmCB_PERFCOUNTER2_HI)/sizeof(mmCB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_LO", REG_MMIO, 0xd40c, &mmCB_PERFCOUNTER3_LO[0], sizeof(mmCB_PERFCOUNTER3_LO)/sizeof(mmCB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_HI", REG_MMIO, 0xd40d, &mmCB_PERFCOUNTER3_HI[0], sizeof(mmCB_PERFCOUNTER3_HI)/sizeof(mmCB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_LO", REG_MMIO, 0xd440, &mmDB_PERFCOUNTER0_LO[0], sizeof(mmDB_PERFCOUNTER0_LO)/sizeof(mmDB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_HI", REG_MMIO, 0xd441, &mmDB_PERFCOUNTER0_HI[0], sizeof(mmDB_PERFCOUNTER0_HI)/sizeof(mmDB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_LO", REG_MMIO, 0xd442, &mmDB_PERFCOUNTER1_LO[0], sizeof(mmDB_PERFCOUNTER1_LO)/sizeof(mmDB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_HI", REG_MMIO, 0xd443, &mmDB_PERFCOUNTER1_HI[0], sizeof(mmDB_PERFCOUNTER1_HI)/sizeof(mmDB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_LO", REG_MMIO, 0xd444, &mmDB_PERFCOUNTER2_LO[0], sizeof(mmDB_PERFCOUNTER2_LO)/sizeof(mmDB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_HI", REG_MMIO, 0xd445, &mmDB_PERFCOUNTER2_HI[0], sizeof(mmDB_PERFCOUNTER2_HI)/sizeof(mmDB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_LO", REG_MMIO, 0xd446, &mmDB_PERFCOUNTER3_LO[0], sizeof(mmDB_PERFCOUNTER3_LO)/sizeof(mmDB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_HI", REG_MMIO, 0xd447, &mmDB_PERFCOUNTER3_HI[0], sizeof(mmDB_PERFCOUNTER3_HI)/sizeof(mmDB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_LO", REG_MMIO, 0xd480, &mmRLC_PERFCOUNTER0_LO[0], sizeof(mmRLC_PERFCOUNTER0_LO)/sizeof(mmRLC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_HI", REG_MMIO, 0xd481, &mmRLC_PERFCOUNTER0_HI[0], sizeof(mmRLC_PERFCOUNTER0_HI)/sizeof(mmRLC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_LO", REG_MMIO, 0xd482, &mmRLC_PERFCOUNTER1_LO[0], sizeof(mmRLC_PERFCOUNTER1_LO)/sizeof(mmRLC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_HI", REG_MMIO, 0xd483, &mmRLC_PERFCOUNTER1_HI[0], sizeof(mmRLC_PERFCOUNTER1_HI)/sizeof(mmRLC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_SELECT", REG_MMIO, 0xd800, &mmCPG_PERFCOUNTER1_SELECT[0], sizeof(mmCPG_PERFCOUNTER1_SELECT)/sizeof(mmCPG_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd801, &mmCPG_PERFCOUNTER0_SELECT1[0], sizeof(mmCPG_PERFCOUNTER0_SELECT1)/sizeof(mmCPG_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_SELECT", REG_MMIO, 0xd802, &mmCPG_PERFCOUNTER0_SELECT[0], sizeof(mmCPG_PERFCOUNTER0_SELECT)/sizeof(mmCPG_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd803, &mmCPC_PERFCOUNTER1_SELECT[0], sizeof(mmCPC_PERFCOUNTER1_SELECT)/sizeof(mmCPC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd804, &mmCPC_PERFCOUNTER0_SELECT1[0], sizeof(mmCPC_PERFCOUNTER0_SELECT1)/sizeof(mmCPC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_SELECT", REG_MMIO, 0xd805, &mmCPF_PERFCOUNTER1_SELECT[0], sizeof(mmCPF_PERFCOUNTER1_SELECT)/sizeof(mmCPF_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd806, &mmCPF_PERFCOUNTER0_SELECT1[0], sizeof(mmCPF_PERFCOUNTER0_SELECT1)/sizeof(mmCPF_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_SELECT", REG_MMIO, 0xd807, &mmCPF_PERFCOUNTER0_SELECT[0], sizeof(mmCPF_PERFCOUNTER0_SELECT)/sizeof(mmCPF_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTL", REG_MMIO, 0xd808, &mmCP_PERFMON_CNTL[0], sizeof(mmCP_PERFMON_CNTL)/sizeof(mmCP_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd809, &mmCPC_PERFCOUNTER0_SELECT[0], sizeof(mmCPC_PERFCOUNTER0_SELECT)/sizeof(mmCPC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCP_DRAW_OBJECT", REG_MMIO, 0xd810, &mmCP_DRAW_OBJECT[0], sizeof(mmCP_DRAW_OBJECT)/sizeof(mmCP_DRAW_OBJECT[0]), 0, 0 },
+	{ "mmCP_DRAW_OBJECT_COUNTER", REG_MMIO, 0xd811, &mmCP_DRAW_OBJECT_COUNTER[0], sizeof(mmCP_DRAW_OBJECT_COUNTER)/sizeof(mmCP_DRAW_OBJECT_COUNTER[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_MASK_HI", REG_MMIO, 0xd812, &mmCP_DRAW_WINDOW_MASK_HI[0], sizeof(mmCP_DRAW_WINDOW_MASK_HI)/sizeof(mmCP_DRAW_WINDOW_MASK_HI[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_HI", REG_MMIO, 0xd813, &mmCP_DRAW_WINDOW_HI[0], sizeof(mmCP_DRAW_WINDOW_HI)/sizeof(mmCP_DRAW_WINDOW_HI[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_LO", REG_MMIO, 0xd814, &mmCP_DRAW_WINDOW_LO[0], sizeof(mmCP_DRAW_WINDOW_LO)/sizeof(mmCP_DRAW_WINDOW_LO[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_CNTL", REG_MMIO, 0xd815, &mmCP_DRAW_WINDOW_CNTL[0], sizeof(mmCP_DRAW_WINDOW_CNTL)/sizeof(mmCP_DRAW_WINDOW_CNTL[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0xd840, &mmGRBM_PERFCOUNTER0_SELECT[0], sizeof(mmGRBM_PERFCOUNTER0_SELECT)/sizeof(mmGRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0xd841, &mmGRBM_PERFCOUNTER1_SELECT[0], sizeof(mmGRBM_PERFCOUNTER1_SELECT)/sizeof(mmGRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_SELECT", REG_MMIO, 0xd842, &mmGRBM_SE0_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_SELECT", REG_MMIO, 0xd843, &mmGRBM_SE1_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_SELECT", REG_MMIO, 0xd844, &mmGRBM_SE2_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_SELECT", REG_MMIO, 0xd845, &mmGRBM_SE3_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_SELECT", REG_MMIO, 0xd880, &mmWD_PERFCOUNTER0_SELECT[0], sizeof(mmWD_PERFCOUNTER0_SELECT)/sizeof(mmWD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_SELECT", REG_MMIO, 0xd881, &mmWD_PERFCOUNTER1_SELECT[0], sizeof(mmWD_PERFCOUNTER1_SELECT)/sizeof(mmWD_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_SELECT", REG_MMIO, 0xd882, &mmWD_PERFCOUNTER2_SELECT[0], sizeof(mmWD_PERFCOUNTER2_SELECT)/sizeof(mmWD_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_SELECT", REG_MMIO, 0xd883, &mmWD_PERFCOUNTER3_SELECT[0], sizeof(mmWD_PERFCOUNTER3_SELECT)/sizeof(mmWD_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT", REG_MMIO, 0xd884, &mmIA_PERFCOUNTER0_SELECT[0], sizeof(mmIA_PERFCOUNTER0_SELECT)/sizeof(mmIA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_SELECT", REG_MMIO, 0xd885, &mmIA_PERFCOUNTER1_SELECT[0], sizeof(mmIA_PERFCOUNTER1_SELECT)/sizeof(mmIA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_SELECT", REG_MMIO, 0xd886, &mmIA_PERFCOUNTER2_SELECT[0], sizeof(mmIA_PERFCOUNTER2_SELECT)/sizeof(mmIA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_SELECT", REG_MMIO, 0xd887, &mmIA_PERFCOUNTER3_SELECT[0], sizeof(mmIA_PERFCOUNTER3_SELECT)/sizeof(mmIA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd888, &mmIA_PERFCOUNTER0_SELECT1[0], sizeof(mmIA_PERFCOUNTER0_SELECT1)/sizeof(mmIA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT", REG_MMIO, 0xd88c, &mmVGT_PERFCOUNTER0_SELECT[0], sizeof(mmVGT_PERFCOUNTER0_SELECT)/sizeof(mmVGT_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT", REG_MMIO, 0xd88d, &mmVGT_PERFCOUNTER1_SELECT[0], sizeof(mmVGT_PERFCOUNTER1_SELECT)/sizeof(mmVGT_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_SELECT", REG_MMIO, 0xd88e, &mmVGT_PERFCOUNTER2_SELECT[0], sizeof(mmVGT_PERFCOUNTER2_SELECT)/sizeof(mmVGT_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_SELECT", REG_MMIO, 0xd88f, &mmVGT_PERFCOUNTER3_SELECT[0], sizeof(mmVGT_PERFCOUNTER3_SELECT)/sizeof(mmVGT_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd890, &mmVGT_PERFCOUNTER0_SELECT1[0], sizeof(mmVGT_PERFCOUNTER0_SELECT1)/sizeof(mmVGT_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd891, &mmVGT_PERFCOUNTER1_SELECT1[0], sizeof(mmVGT_PERFCOUNTER1_SELECT1)/sizeof(mmVGT_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER_SEID_MASK", REG_MMIO, 0xd894, &mmVGT_PERFCOUNTER_SEID_MASK[0], sizeof(mmVGT_PERFCOUNTER_SEID_MASK)/sizeof(mmVGT_PERFCOUNTER_SEID_MASK[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT", REG_MMIO, 0xd900, &mmPA_SU_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd901, &mmPA_SU_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT", REG_MMIO, 0xd902, &mmPA_SU_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd903, &mmPA_SU_PERFCOUNTER1_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_SELECT", REG_MMIO, 0xd904, &mmPA_SU_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER2_SELECT)/sizeof(mmPA_SU_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_SELECT", REG_MMIO, 0xd905, &mmPA_SU_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER3_SELECT)/sizeof(mmPA_SU_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd940, &mmPA_SC_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd941, &mmPA_SC_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd942, &mmPA_SC_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER1_SELECT)/sizeof(mmPA_SC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_SELECT", REG_MMIO, 0xd943, &mmPA_SC_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER2_SELECT)/sizeof(mmPA_SC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_SELECT", REG_MMIO, 0xd944, &mmPA_SC_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER3_SELECT)/sizeof(mmPA_SC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_SELECT", REG_MMIO, 0xd945, &mmPA_SC_PERFCOUNTER4_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER4_SELECT)/sizeof(mmPA_SC_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_SELECT", REG_MMIO, 0xd946, &mmPA_SC_PERFCOUNTER5_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER5_SELECT)/sizeof(mmPA_SC_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_SELECT", REG_MMIO, 0xd947, &mmPA_SC_PERFCOUNTER6_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER6_SELECT)/sizeof(mmPA_SC_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_SELECT", REG_MMIO, 0xd948, &mmPA_SC_PERFCOUNTER7_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER7_SELECT)/sizeof(mmPA_SC_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT", REG_MMIO, 0xd980, &mmSPI_PERFCOUNTER0_SELECT[0], sizeof(mmSPI_PERFCOUNTER0_SELECT)/sizeof(mmSPI_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT", REG_MMIO, 0xd981, &mmSPI_PERFCOUNTER1_SELECT[0], sizeof(mmSPI_PERFCOUNTER1_SELECT)/sizeof(mmSPI_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT", REG_MMIO, 0xd982, &mmSPI_PERFCOUNTER2_SELECT[0], sizeof(mmSPI_PERFCOUNTER2_SELECT)/sizeof(mmSPI_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT", REG_MMIO, 0xd983, &mmSPI_PERFCOUNTER3_SELECT[0], sizeof(mmSPI_PERFCOUNTER3_SELECT)/sizeof(mmSPI_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd984, &mmSPI_PERFCOUNTER0_SELECT1[0], sizeof(mmSPI_PERFCOUNTER0_SELECT1)/sizeof(mmSPI_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd985, &mmSPI_PERFCOUNTER1_SELECT1[0], sizeof(mmSPI_PERFCOUNTER1_SELECT1)/sizeof(mmSPI_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT1", REG_MMIO, 0xd986, &mmSPI_PERFCOUNTER2_SELECT1[0], sizeof(mmSPI_PERFCOUNTER2_SELECT1)/sizeof(mmSPI_PERFCOUNTER2_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT1", REG_MMIO, 0xd987, &mmSPI_PERFCOUNTER3_SELECT1[0], sizeof(mmSPI_PERFCOUNTER3_SELECT1)/sizeof(mmSPI_PERFCOUNTER3_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_SELECT", REG_MMIO, 0xd988, &mmSPI_PERFCOUNTER4_SELECT[0], sizeof(mmSPI_PERFCOUNTER4_SELECT)/sizeof(mmSPI_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_SELECT", REG_MMIO, 0xd989, &mmSPI_PERFCOUNTER5_SELECT[0], sizeof(mmSPI_PERFCOUNTER5_SELECT)/sizeof(mmSPI_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER_BINS", REG_MMIO, 0xd98a, &mmSPI_PERFCOUNTER_BINS[0], sizeof(mmSPI_PERFCOUNTER_BINS)/sizeof(mmSPI_PERFCOUNTER_BINS[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_SELECT", REG_MMIO, 0xd9c0, &mmSQ_PERFCOUNTER0_SELECT[0], sizeof(mmSQ_PERFCOUNTER0_SELECT)/sizeof(mmSQ_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_SELECT", REG_MMIO, 0xd9c1, &mmSQ_PERFCOUNTER1_SELECT[0], sizeof(mmSQ_PERFCOUNTER1_SELECT)/sizeof(mmSQ_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_SELECT", REG_MMIO, 0xd9c2, &mmSQ_PERFCOUNTER2_SELECT[0], sizeof(mmSQ_PERFCOUNTER2_SELECT)/sizeof(mmSQ_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_SELECT", REG_MMIO, 0xd9c3, &mmSQ_PERFCOUNTER3_SELECT[0], sizeof(mmSQ_PERFCOUNTER3_SELECT)/sizeof(mmSQ_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_SELECT", REG_MMIO, 0xd9c4, &mmSQ_PERFCOUNTER4_SELECT[0], sizeof(mmSQ_PERFCOUNTER4_SELECT)/sizeof(mmSQ_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_SELECT", REG_MMIO, 0xd9c5, &mmSQ_PERFCOUNTER5_SELECT[0], sizeof(mmSQ_PERFCOUNTER5_SELECT)/sizeof(mmSQ_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_SELECT", REG_MMIO, 0xd9c6, &mmSQ_PERFCOUNTER6_SELECT[0], sizeof(mmSQ_PERFCOUNTER6_SELECT)/sizeof(mmSQ_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_SELECT", REG_MMIO, 0xd9c7, &mmSQ_PERFCOUNTER7_SELECT[0], sizeof(mmSQ_PERFCOUNTER7_SELECT)/sizeof(mmSQ_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_SELECT", REG_MMIO, 0xd9c8, &mmSQ_PERFCOUNTER8_SELECT[0], sizeof(mmSQ_PERFCOUNTER8_SELECT)/sizeof(mmSQ_PERFCOUNTER8_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_SELECT", REG_MMIO, 0xd9c9, &mmSQ_PERFCOUNTER9_SELECT[0], sizeof(mmSQ_PERFCOUNTER9_SELECT)/sizeof(mmSQ_PERFCOUNTER9_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_SELECT", REG_MMIO, 0xd9ca, &mmSQ_PERFCOUNTER10_SELECT[0], sizeof(mmSQ_PERFCOUNTER10_SELECT)/sizeof(mmSQ_PERFCOUNTER10_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_SELECT", REG_MMIO, 0xd9cb, &mmSQ_PERFCOUNTER11_SELECT[0], sizeof(mmSQ_PERFCOUNTER11_SELECT)/sizeof(mmSQ_PERFCOUNTER11_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_SELECT", REG_MMIO, 0xd9cc, &mmSQ_PERFCOUNTER12_SELECT[0], sizeof(mmSQ_PERFCOUNTER12_SELECT)/sizeof(mmSQ_PERFCOUNTER12_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_SELECT", REG_MMIO, 0xd9cd, &mmSQ_PERFCOUNTER13_SELECT[0], sizeof(mmSQ_PERFCOUNTER13_SELECT)/sizeof(mmSQ_PERFCOUNTER13_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_SELECT", REG_MMIO, 0xd9ce, &mmSQ_PERFCOUNTER14_SELECT[0], sizeof(mmSQ_PERFCOUNTER14_SELECT)/sizeof(mmSQ_PERFCOUNTER14_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_SELECT", REG_MMIO, 0xd9cf, &mmSQ_PERFCOUNTER15_SELECT[0], sizeof(mmSQ_PERFCOUNTER15_SELECT)/sizeof(mmSQ_PERFCOUNTER15_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL", REG_MMIO, 0xd9e0, &mmSQ_PERFCOUNTER_CTRL[0], sizeof(mmSQ_PERFCOUNTER_CTRL)/sizeof(mmSQ_PERFCOUNTER_CTRL[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_MASK", REG_MMIO, 0xd9e1, &mmSQ_PERFCOUNTER_MASK[0], sizeof(mmSQ_PERFCOUNTER_MASK)/sizeof(mmSQ_PERFCOUNTER_MASK[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL2", REG_MMIO, 0xd9e2, &mmSQ_PERFCOUNTER_CTRL2[0], sizeof(mmSQ_PERFCOUNTER_CTRL2)/sizeof(mmSQ_PERFCOUNTER_CTRL2[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT", REG_MMIO, 0xda40, &mmSX_PERFCOUNTER0_SELECT[0], sizeof(mmSX_PERFCOUNTER0_SELECT)/sizeof(mmSX_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT", REG_MMIO, 0xda41, &mmSX_PERFCOUNTER1_SELECT[0], sizeof(mmSX_PERFCOUNTER1_SELECT)/sizeof(mmSX_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_SELECT", REG_MMIO, 0xda42, &mmSX_PERFCOUNTER2_SELECT[0], sizeof(mmSX_PERFCOUNTER2_SELECT)/sizeof(mmSX_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_SELECT", REG_MMIO, 0xda43, &mmSX_PERFCOUNTER3_SELECT[0], sizeof(mmSX_PERFCOUNTER3_SELECT)/sizeof(mmSX_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda44, &mmSX_PERFCOUNTER0_SELECT1[0], sizeof(mmSX_PERFCOUNTER0_SELECT1)/sizeof(mmSX_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT1", REG_MMIO, 0xda45, &mmSX_PERFCOUNTER1_SELECT1[0], sizeof(mmSX_PERFCOUNTER1_SELECT1)/sizeof(mmSX_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT", REG_MMIO, 0xda80, &mmGDS_PERFCOUNTER0_SELECT[0], sizeof(mmGDS_PERFCOUNTER0_SELECT)/sizeof(mmGDS_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_SELECT", REG_MMIO, 0xda81, &mmGDS_PERFCOUNTER1_SELECT[0], sizeof(mmGDS_PERFCOUNTER1_SELECT)/sizeof(mmGDS_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_SELECT", REG_MMIO, 0xda82, &mmGDS_PERFCOUNTER2_SELECT[0], sizeof(mmGDS_PERFCOUNTER2_SELECT)/sizeof(mmGDS_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_SELECT", REG_MMIO, 0xda83, &mmGDS_PERFCOUNTER3_SELECT[0], sizeof(mmGDS_PERFCOUNTER3_SELECT)/sizeof(mmGDS_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda84, &mmGDS_PERFCOUNTER0_SELECT1[0], sizeof(mmGDS_PERFCOUNTER0_SELECT1)/sizeof(mmGDS_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdac0, &mmTA_PERFCOUNTER0_SELECT[0], sizeof(mmTA_PERFCOUNTER0_SELECT)/sizeof(mmTA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdac1, &mmTA_PERFCOUNTER0_SELECT1[0], sizeof(mmTA_PERFCOUNTER0_SELECT1)/sizeof(mmTA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdac2, &mmTA_PERFCOUNTER1_SELECT[0], sizeof(mmTA_PERFCOUNTER1_SELECT)/sizeof(mmTA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb00, &mmTD_PERFCOUNTER0_SELECT[0], sizeof(mmTD_PERFCOUNTER0_SELECT)/sizeof(mmTD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb01, &mmTD_PERFCOUNTER0_SELECT1[0], sizeof(mmTD_PERFCOUNTER0_SELECT1)/sizeof(mmTD_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb02, &mmTD_PERFCOUNTER1_SELECT[0], sizeof(mmTD_PERFCOUNTER1_SELECT)/sizeof(mmTD_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb40, &mmTCP_PERFCOUNTER0_SELECT[0], sizeof(mmTCP_PERFCOUNTER0_SELECT)/sizeof(mmTCP_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb41, &mmTCP_PERFCOUNTER0_SELECT1[0], sizeof(mmTCP_PERFCOUNTER0_SELECT1)/sizeof(mmTCP_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb42, &mmTCP_PERFCOUNTER1_SELECT[0], sizeof(mmTCP_PERFCOUNTER1_SELECT)/sizeof(mmTCP_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb43, &mmTCP_PERFCOUNTER1_SELECT1[0], sizeof(mmTCP_PERFCOUNTER1_SELECT1)/sizeof(mmTCP_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb44, &mmTCP_PERFCOUNTER2_SELECT[0], sizeof(mmTCP_PERFCOUNTER2_SELECT)/sizeof(mmTCP_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb45, &mmTCP_PERFCOUNTER3_SELECT[0], sizeof(mmTCP_PERFCOUNTER3_SELECT)/sizeof(mmTCP_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb80, &mmTCC_PERFCOUNTER0_SELECT[0], sizeof(mmTCC_PERFCOUNTER0_SELECT)/sizeof(mmTCC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb81, &mmTCC_PERFCOUNTER0_SELECT1[0], sizeof(mmTCC_PERFCOUNTER0_SELECT1)/sizeof(mmTCC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb82, &mmTCC_PERFCOUNTER1_SELECT[0], sizeof(mmTCC_PERFCOUNTER1_SELECT)/sizeof(mmTCC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb83, &mmTCC_PERFCOUNTER1_SELECT1[0], sizeof(mmTCC_PERFCOUNTER1_SELECT1)/sizeof(mmTCC_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb84, &mmTCC_PERFCOUNTER2_SELECT[0], sizeof(mmTCC_PERFCOUNTER2_SELECT)/sizeof(mmTCC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb85, &mmTCC_PERFCOUNTER3_SELECT[0], sizeof(mmTCC_PERFCOUNTER3_SELECT)/sizeof(mmTCC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb90, &mmTCA_PERFCOUNTER0_SELECT[0], sizeof(mmTCA_PERFCOUNTER0_SELECT)/sizeof(mmTCA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb91, &mmTCA_PERFCOUNTER0_SELECT1[0], sizeof(mmTCA_PERFCOUNTER0_SELECT1)/sizeof(mmTCA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb92, &mmTCA_PERFCOUNTER1_SELECT[0], sizeof(mmTCA_PERFCOUNTER1_SELECT)/sizeof(mmTCA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb93, &mmTCA_PERFCOUNTER1_SELECT1[0], sizeof(mmTCA_PERFCOUNTER1_SELECT1)/sizeof(mmTCA_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb94, &mmTCA_PERFCOUNTER2_SELECT[0], sizeof(mmTCA_PERFCOUNTER2_SELECT)/sizeof(mmTCA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb95, &mmTCA_PERFCOUNTER3_SELECT[0], sizeof(mmTCA_PERFCOUNTER3_SELECT)/sizeof(mmTCA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER0_SELECT", REG_MMIO, 0xdba0, &mmTCS_PERFCOUNTER0_SELECT[0], sizeof(mmTCS_PERFCOUNTER0_SELECT)/sizeof(mmTCS_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdba1, &mmTCS_PERFCOUNTER0_SELECT1[0], sizeof(mmTCS_PERFCOUNTER0_SELECT1)/sizeof(mmTCS_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER1_SELECT", REG_MMIO, 0xdba2, &mmTCS_PERFCOUNTER1_SELECT[0], sizeof(mmTCS_PERFCOUNTER1_SELECT)/sizeof(mmTCS_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER2_SELECT", REG_MMIO, 0xdba3, &mmTCS_PERFCOUNTER2_SELECT[0], sizeof(mmTCS_PERFCOUNTER2_SELECT)/sizeof(mmTCS_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCS_PERFCOUNTER3_SELECT", REG_MMIO, 0xdba4, &mmTCS_PERFCOUNTER3_SELECT[0], sizeof(mmTCS_PERFCOUNTER3_SELECT)/sizeof(mmTCS_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER_FILTER", REG_MMIO, 0xdc00, &mmCB_PERFCOUNTER_FILTER[0], sizeof(mmCB_PERFCOUNTER_FILTER)/sizeof(mmCB_PERFCOUNTER_FILTER[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc01, &mmCB_PERFCOUNTER0_SELECT[0], sizeof(mmCB_PERFCOUNTER0_SELECT)/sizeof(mmCB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc02, &mmCB_PERFCOUNTER0_SELECT1[0], sizeof(mmCB_PERFCOUNTER0_SELECT1)/sizeof(mmCB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc03, &mmCB_PERFCOUNTER1_SELECT[0], sizeof(mmCB_PERFCOUNTER1_SELECT)/sizeof(mmCB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc04, &mmCB_PERFCOUNTER2_SELECT[0], sizeof(mmCB_PERFCOUNTER2_SELECT)/sizeof(mmCB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc05, &mmCB_PERFCOUNTER3_SELECT[0], sizeof(mmCB_PERFCOUNTER3_SELECT)/sizeof(mmCB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc40, &mmDB_PERFCOUNTER0_SELECT[0], sizeof(mmDB_PERFCOUNTER0_SELECT)/sizeof(mmDB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc41, &mmDB_PERFCOUNTER0_SELECT1[0], sizeof(mmDB_PERFCOUNTER0_SELECT1)/sizeof(mmDB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc42, &mmDB_PERFCOUNTER1_SELECT[0], sizeof(mmDB_PERFCOUNTER1_SELECT)/sizeof(mmDB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdc43, &mmDB_PERFCOUNTER1_SELECT1[0], sizeof(mmDB_PERFCOUNTER1_SELECT1)/sizeof(mmDB_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc44, &mmDB_PERFCOUNTER2_SELECT[0], sizeof(mmDB_PERFCOUNTER2_SELECT)/sizeof(mmDB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc46, &mmDB_PERFCOUNTER3_SELECT[0], sizeof(mmDB_PERFCOUNTER3_SELECT)/sizeof(mmDB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_CNTL", REG_MMIO, 0xdc80, &mmRLC_SPM_PERFMON_CNTL[0], sizeof(mmRLC_SPM_PERFMON_CNTL)/sizeof(mmRLC_SPM_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_BASE_LO", REG_MMIO, 0xdc81, &mmRLC_SPM_PERFMON_RING_BASE_LO[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_BASE_HI", REG_MMIO, 0xdc82, &mmRLC_SPM_PERFMON_RING_BASE_HI[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_SIZE", REG_MMIO, 0xdc83, &mmRLC_SPM_PERFMON_RING_SIZE[0], sizeof(mmRLC_SPM_PERFMON_RING_SIZE)/sizeof(mmRLC_SPM_PERFMON_RING_SIZE[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_SEGMENT_SIZE", REG_MMIO, 0xdc84, &mmRLC_SPM_PERFMON_SEGMENT_SIZE[0], sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE)/sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE[0]), 0, 0 },
+	{ "mmRLC_SPM_SE_MUXSEL_ADDR", REG_MMIO, 0xdc85, &mmRLC_SPM_SE_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_SE_MUXSEL_ADDR)/sizeof(mmRLC_SPM_SE_MUXSEL_ADDR[0]), 0, 0 },
+	{ "mmRLC_SPM_SE_MUXSEL_DATA", REG_MMIO, 0xdc86, &mmRLC_SPM_SE_MUXSEL_DATA[0], sizeof(mmRLC_SPM_SE_MUXSEL_DATA)/sizeof(mmRLC_SPM_SE_MUXSEL_DATA[0]), 0, 0 },
+	{ "mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc87, &mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc88, &mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc89, &mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8a, &mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8b, &mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8c, &mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8d, &mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8e, &mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc90, &mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc91, &mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc92, &mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc93, &mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc94, &mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc95, &mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc96, &mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc97, &mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc98, &mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc99, &mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc9a, &mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_GLOBAL_MUXSEL_ADDR", REG_MMIO, 0xdc9b, &mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0]), 0, 0 },
+	{ "mmRLC_SPM_GLOBAL_MUXSEL_DATA", REG_MMIO, 0xdc9c, &mmRLC_SPM_GLOBAL_MUXSEL_DATA[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA[0]), 0, 0 },
+	{ "mmRLC_SPM_RING_RDPTR", REG_MMIO, 0xdc9d, &mmRLC_SPM_RING_RDPTR[0], sizeof(mmRLC_SPM_RING_RDPTR)/sizeof(mmRLC_SPM_RING_RDPTR[0]), 0, 0 },
+	{ "mmRLC_SPM_SEGMENT_THRESHOLD", REG_MMIO, 0xdc9e, &mmRLC_SPM_SEGMENT_THRESHOLD[0], sizeof(mmRLC_SPM_SEGMENT_THRESHOLD)/sizeof(mmRLC_SPM_SEGMENT_THRESHOLD[0]), 0, 0 },
+	{ "mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc9f, &mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca0, &mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca1, &mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca2, &mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_PERFMON_CNTL", REG_MMIO, 0xdcc0, &mmRLC_PERFMON_CNTL[0], sizeof(mmRLC_PERFMON_CNTL)/sizeof(mmRLC_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdcc1, &mmRLC_PERFCOUNTER0_SELECT[0], sizeof(mmRLC_PERFCOUNTER0_SELECT)/sizeof(mmRLC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdcc2, &mmRLC_PERFCOUNTER1_SELECT[0], sizeof(mmRLC_PERFCOUNTER1_SELECT)/sizeof(mmRLC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG14", REG_SMC, 0xe, &ixCLIPPER_DEBUG_REG14[0], sizeof(ixCLIPPER_DEBUG_REG14)/sizeof(ixCLIPPER_DEBUG_REG14[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG14", REG_SMC, 0xe, &ixVGT_DEBUG_REG14[0], sizeof(ixVGT_DEBUG_REG14)/sizeof(ixVGT_DEBUG_REG14[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG15", REG_SMC, 0xf, &ixCLIPPER_DEBUG_REG15[0], sizeof(ixCLIPPER_DEBUG_REG15)/sizeof(ixCLIPPER_DEBUG_REG15[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG15", REG_SMC, 0xf, &ixVGT_DEBUG_REG15[0], sizeof(ixVGT_DEBUG_REG15)/sizeof(ixVGT_DEBUG_REG15[0]), 0, 0 },
+	{ "mmCGTS_SM_CTRL_REG", REG_MMIO, 0xf000, &mmCGTS_SM_CTRL_REG[0], sizeof(mmCGTS_SM_CTRL_REG)/sizeof(mmCGTS_SM_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_CTRL_REG", REG_MMIO, 0xf001, &mmCGTS_RD_CTRL_REG[0], sizeof(mmCGTS_RD_CTRL_REG)/sizeof(mmCGTS_RD_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_REG", REG_MMIO, 0xf002, &mmCGTS_RD_REG[0], sizeof(mmCGTS_RD_REG)/sizeof(mmCGTS_RD_REG[0]), 0, 0 },
+	{ "mmCGTS_TCC_DISABLE", REG_MMIO, 0xf003, &mmCGTS_TCC_DISABLE[0], sizeof(mmCGTS_TCC_DISABLE)/sizeof(mmCGTS_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_USER_TCC_DISABLE", REG_MMIO, 0xf004, &mmCGTS_USER_TCC_DISABLE[0], sizeof(mmCGTS_USER_TCC_DISABLE)/sizeof(mmCGTS_USER_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_CU0_SP0_CTRL_REG", REG_MMIO, 0xf008, &mmCGTS_CU0_SP0_CTRL_REG[0], sizeof(mmCGTS_CU0_SP0_CTRL_REG)/sizeof(mmCGTS_CU0_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_LDS_SQ_CTRL_REG", REG_MMIO, 0xf009, &mmCGTS_CU0_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_TA_SQC_CTRL_REG", REG_MMIO, 0xf00a, &mmCGTS_CU0_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_SP1_CTRL_REG", REG_MMIO, 0xf00b, &mmCGTS_CU0_SP1_CTRL_REG[0], sizeof(mmCGTS_CU0_SP1_CTRL_REG)/sizeof(mmCGTS_CU0_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_TD_TCP_CTRL_REG", REG_MMIO, 0xf00c, &mmCGTS_CU0_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_SP0_CTRL_REG", REG_MMIO, 0xf00d, &mmCGTS_CU1_SP0_CTRL_REG[0], sizeof(mmCGTS_CU1_SP0_CTRL_REG)/sizeof(mmCGTS_CU1_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_LDS_SQ_CTRL_REG", REG_MMIO, 0xf00e, &mmCGTS_CU1_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_TA_CTRL_REG", REG_MMIO, 0xf00f, &mmCGTS_CU1_TA_CTRL_REG[0], sizeof(mmCGTS_CU1_TA_CTRL_REG)/sizeof(mmCGTS_CU1_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_SP1_CTRL_REG", REG_MMIO, 0xf010, &mmCGTS_CU1_SP1_CTRL_REG[0], sizeof(mmCGTS_CU1_SP1_CTRL_REG)/sizeof(mmCGTS_CU1_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_TD_TCP_CTRL_REG", REG_MMIO, 0xf011, &mmCGTS_CU1_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_SP0_CTRL_REG", REG_MMIO, 0xf012, &mmCGTS_CU2_SP0_CTRL_REG[0], sizeof(mmCGTS_CU2_SP0_CTRL_REG)/sizeof(mmCGTS_CU2_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_LDS_SQ_CTRL_REG", REG_MMIO, 0xf013, &mmCGTS_CU2_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_TA_CTRL_REG", REG_MMIO, 0xf014, &mmCGTS_CU2_TA_CTRL_REG[0], sizeof(mmCGTS_CU2_TA_CTRL_REG)/sizeof(mmCGTS_CU2_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_SP1_CTRL_REG", REG_MMIO, 0xf015, &mmCGTS_CU2_SP1_CTRL_REG[0], sizeof(mmCGTS_CU2_SP1_CTRL_REG)/sizeof(mmCGTS_CU2_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_TD_TCP_CTRL_REG", REG_MMIO, 0xf016, &mmCGTS_CU2_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_SP0_CTRL_REG", REG_MMIO, 0xf017, &mmCGTS_CU3_SP0_CTRL_REG[0], sizeof(mmCGTS_CU3_SP0_CTRL_REG)/sizeof(mmCGTS_CU3_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_LDS_SQ_CTRL_REG", REG_MMIO, 0xf018, &mmCGTS_CU3_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_TA_CTRL_REG", REG_MMIO, 0xf019, &mmCGTS_CU3_TA_CTRL_REG[0], sizeof(mmCGTS_CU3_TA_CTRL_REG)/sizeof(mmCGTS_CU3_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_SP1_CTRL_REG", REG_MMIO, 0xf01a, &mmCGTS_CU3_SP1_CTRL_REG[0], sizeof(mmCGTS_CU3_SP1_CTRL_REG)/sizeof(mmCGTS_CU3_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_TD_TCP_CTRL_REG", REG_MMIO, 0xf01b, &mmCGTS_CU3_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_SP0_CTRL_REG", REG_MMIO, 0xf01c, &mmCGTS_CU4_SP0_CTRL_REG[0], sizeof(mmCGTS_CU4_SP0_CTRL_REG)/sizeof(mmCGTS_CU4_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_LDS_SQ_CTRL_REG", REG_MMIO, 0xf01d, &mmCGTS_CU4_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_TA_SQC_CTRL_REG", REG_MMIO, 0xf01e, &mmCGTS_CU4_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_SP1_CTRL_REG", REG_MMIO, 0xf01f, &mmCGTS_CU4_SP1_CTRL_REG[0], sizeof(mmCGTS_CU4_SP1_CTRL_REG)/sizeof(mmCGTS_CU4_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_TD_TCP_CTRL_REG", REG_MMIO, 0xf020, &mmCGTS_CU4_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_SP0_CTRL_REG", REG_MMIO, 0xf021, &mmCGTS_CU5_SP0_CTRL_REG[0], sizeof(mmCGTS_CU5_SP0_CTRL_REG)/sizeof(mmCGTS_CU5_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_LDS_SQ_CTRL_REG", REG_MMIO, 0xf022, &mmCGTS_CU5_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_TA_CTRL_REG", REG_MMIO, 0xf023, &mmCGTS_CU5_TA_CTRL_REG[0], sizeof(mmCGTS_CU5_TA_CTRL_REG)/sizeof(mmCGTS_CU5_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_SP1_CTRL_REG", REG_MMIO, 0xf024, &mmCGTS_CU5_SP1_CTRL_REG[0], sizeof(mmCGTS_CU5_SP1_CTRL_REG)/sizeof(mmCGTS_CU5_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_TD_TCP_CTRL_REG", REG_MMIO, 0xf025, &mmCGTS_CU5_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_SP0_CTRL_REG", REG_MMIO, 0xf026, &mmCGTS_CU6_SP0_CTRL_REG[0], sizeof(mmCGTS_CU6_SP0_CTRL_REG)/sizeof(mmCGTS_CU6_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_LDS_SQ_CTRL_REG", REG_MMIO, 0xf027, &mmCGTS_CU6_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_TA_CTRL_REG", REG_MMIO, 0xf028, &mmCGTS_CU6_TA_CTRL_REG[0], sizeof(mmCGTS_CU6_TA_CTRL_REG)/sizeof(mmCGTS_CU6_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_SP1_CTRL_REG", REG_MMIO, 0xf029, &mmCGTS_CU6_SP1_CTRL_REG[0], sizeof(mmCGTS_CU6_SP1_CTRL_REG)/sizeof(mmCGTS_CU6_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_TD_TCP_CTRL_REG", REG_MMIO, 0xf02a, &mmCGTS_CU6_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_SP0_CTRL_REG", REG_MMIO, 0xf02b, &mmCGTS_CU7_SP0_CTRL_REG[0], sizeof(mmCGTS_CU7_SP0_CTRL_REG)/sizeof(mmCGTS_CU7_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_LDS_SQ_CTRL_REG", REG_MMIO, 0xf02c, &mmCGTS_CU7_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_TA_CTRL_REG", REG_MMIO, 0xf02d, &mmCGTS_CU7_TA_CTRL_REG[0], sizeof(mmCGTS_CU7_TA_CTRL_REG)/sizeof(mmCGTS_CU7_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_SP1_CTRL_REG", REG_MMIO, 0xf02e, &mmCGTS_CU7_SP1_CTRL_REG[0], sizeof(mmCGTS_CU7_SP1_CTRL_REG)/sizeof(mmCGTS_CU7_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_TD_TCP_CTRL_REG", REG_MMIO, 0xf02f, &mmCGTS_CU7_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_SP0_CTRL_REG", REG_MMIO, 0xf030, &mmCGTS_CU8_SP0_CTRL_REG[0], sizeof(mmCGTS_CU8_SP0_CTRL_REG)/sizeof(mmCGTS_CU8_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_LDS_SQ_CTRL_REG", REG_MMIO, 0xf031, &mmCGTS_CU8_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_TA_SQC_CTRL_REG", REG_MMIO, 0xf032, &mmCGTS_CU8_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_SP1_CTRL_REG", REG_MMIO, 0xf033, &mmCGTS_CU8_SP1_CTRL_REG[0], sizeof(mmCGTS_CU8_SP1_CTRL_REG)/sizeof(mmCGTS_CU8_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_TD_TCP_CTRL_REG", REG_MMIO, 0xf034, &mmCGTS_CU8_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_SP0_CTRL_REG", REG_MMIO, 0xf035, &mmCGTS_CU9_SP0_CTRL_REG[0], sizeof(mmCGTS_CU9_SP0_CTRL_REG)/sizeof(mmCGTS_CU9_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_LDS_SQ_CTRL_REG", REG_MMIO, 0xf036, &mmCGTS_CU9_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_TA_CTRL_REG", REG_MMIO, 0xf037, &mmCGTS_CU9_TA_CTRL_REG[0], sizeof(mmCGTS_CU9_TA_CTRL_REG)/sizeof(mmCGTS_CU9_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_SP1_CTRL_REG", REG_MMIO, 0xf038, &mmCGTS_CU9_SP1_CTRL_REG[0], sizeof(mmCGTS_CU9_SP1_CTRL_REG)/sizeof(mmCGTS_CU9_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_TD_TCP_CTRL_REG", REG_MMIO, 0xf039, &mmCGTS_CU9_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_SP0_CTRL_REG", REG_MMIO, 0xf03a, &mmCGTS_CU10_SP0_CTRL_REG[0], sizeof(mmCGTS_CU10_SP0_CTRL_REG)/sizeof(mmCGTS_CU10_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_LDS_SQ_CTRL_REG", REG_MMIO, 0xf03b, &mmCGTS_CU10_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_TA_CTRL_REG", REG_MMIO, 0xf03c, &mmCGTS_CU10_TA_CTRL_REG[0], sizeof(mmCGTS_CU10_TA_CTRL_REG)/sizeof(mmCGTS_CU10_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_SP1_CTRL_REG", REG_MMIO, 0xf03d, &mmCGTS_CU10_SP1_CTRL_REG[0], sizeof(mmCGTS_CU10_SP1_CTRL_REG)/sizeof(mmCGTS_CU10_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_TD_TCP_CTRL_REG", REG_MMIO, 0xf03e, &mmCGTS_CU10_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_SP0_CTRL_REG", REG_MMIO, 0xf03f, &mmCGTS_CU11_SP0_CTRL_REG[0], sizeof(mmCGTS_CU11_SP0_CTRL_REG)/sizeof(mmCGTS_CU11_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_LDS_SQ_CTRL_REG", REG_MMIO, 0xf040, &mmCGTS_CU11_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_TA_CTRL_REG", REG_MMIO, 0xf041, &mmCGTS_CU11_TA_CTRL_REG[0], sizeof(mmCGTS_CU11_TA_CTRL_REG)/sizeof(mmCGTS_CU11_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_SP1_CTRL_REG", REG_MMIO, 0xf042, &mmCGTS_CU11_SP1_CTRL_REG[0], sizeof(mmCGTS_CU11_SP1_CTRL_REG)/sizeof(mmCGTS_CU11_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_TD_TCP_CTRL_REG", REG_MMIO, 0xf043, &mmCGTS_CU11_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_SP0_CTRL_REG", REG_MMIO, 0xf044, &mmCGTS_CU12_SP0_CTRL_REG[0], sizeof(mmCGTS_CU12_SP0_CTRL_REG)/sizeof(mmCGTS_CU12_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_LDS_SQ_CTRL_REG", REG_MMIO, 0xf045, &mmCGTS_CU12_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_TA_SQC_CTRL_REG", REG_MMIO, 0xf046, &mmCGTS_CU12_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_SP1_CTRL_REG", REG_MMIO, 0xf047, &mmCGTS_CU12_SP1_CTRL_REG[0], sizeof(mmCGTS_CU12_SP1_CTRL_REG)/sizeof(mmCGTS_CU12_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_TD_TCP_CTRL_REG", REG_MMIO, 0xf048, &mmCGTS_CU12_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_SP0_CTRL_REG", REG_MMIO, 0xf049, &mmCGTS_CU13_SP0_CTRL_REG[0], sizeof(mmCGTS_CU13_SP0_CTRL_REG)/sizeof(mmCGTS_CU13_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04a, &mmCGTS_CU13_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_TA_CTRL_REG", REG_MMIO, 0xf04b, &mmCGTS_CU13_TA_CTRL_REG[0], sizeof(mmCGTS_CU13_TA_CTRL_REG)/sizeof(mmCGTS_CU13_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_SP1_CTRL_REG", REG_MMIO, 0xf04c, &mmCGTS_CU13_SP1_CTRL_REG[0], sizeof(mmCGTS_CU13_SP1_CTRL_REG)/sizeof(mmCGTS_CU13_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_TD_TCP_CTRL_REG", REG_MMIO, 0xf04d, &mmCGTS_CU13_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_SP0_CTRL_REG", REG_MMIO, 0xf04e, &mmCGTS_CU14_SP0_CTRL_REG[0], sizeof(mmCGTS_CU14_SP0_CTRL_REG)/sizeof(mmCGTS_CU14_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04f, &mmCGTS_CU14_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_TA_CTRL_REG", REG_MMIO, 0xf050, &mmCGTS_CU14_TA_CTRL_REG[0], sizeof(mmCGTS_CU14_TA_CTRL_REG)/sizeof(mmCGTS_CU14_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_SP1_CTRL_REG", REG_MMIO, 0xf051, &mmCGTS_CU14_SP1_CTRL_REG[0], sizeof(mmCGTS_CU14_SP1_CTRL_REG)/sizeof(mmCGTS_CU14_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_TD_TCP_CTRL_REG", REG_MMIO, 0xf052, &mmCGTS_CU14_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_SP0_CTRL_REG", REG_MMIO, 0xf053, &mmCGTS_CU15_SP0_CTRL_REG[0], sizeof(mmCGTS_CU15_SP0_CTRL_REG)/sizeof(mmCGTS_CU15_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_LDS_SQ_CTRL_REG", REG_MMIO, 0xf054, &mmCGTS_CU15_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_TA_CTRL_REG", REG_MMIO, 0xf055, &mmCGTS_CU15_TA_CTRL_REG[0], sizeof(mmCGTS_CU15_TA_CTRL_REG)/sizeof(mmCGTS_CU15_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_SP1_CTRL_REG", REG_MMIO, 0xf056, &mmCGTS_CU15_SP1_CTRL_REG[0], sizeof(mmCGTS_CU15_SP1_CTRL_REG)/sizeof(mmCGTS_CU15_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_TD_TCP_CTRL_REG", REG_MMIO, 0xf057, &mmCGTS_CU15_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTT_SPI_CLK_CTRL", REG_MMIO, 0xf080, &mmCGTT_SPI_CLK_CTRL[0], sizeof(mmCGTT_SPI_CLK_CTRL)/sizeof(mmCGTT_SPI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_PC_CLK_CTRL", REG_MMIO, 0xf081, &mmCGTT_PC_CLK_CTRL[0], sizeof(mmCGTT_PC_CLK_CTRL)/sizeof(mmCGTT_PC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_BCI_CLK_CTRL", REG_MMIO, 0xf082, &mmCGTT_BCI_CLK_CTRL[0], sizeof(mmCGTT_BCI_CLK_CTRL)/sizeof(mmCGTT_BCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_VGT_CLK_CTRL", REG_MMIO, 0xf084, &mmCGTT_VGT_CLK_CTRL[0], sizeof(mmCGTT_VGT_CLK_CTRL)/sizeof(mmCGTT_VGT_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_IA_CLK_CTRL", REG_MMIO, 0xf085, &mmCGTT_IA_CLK_CTRL[0], sizeof(mmCGTT_IA_CLK_CTRL)/sizeof(mmCGTT_IA_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_WD_CLK_CTRL", REG_MMIO, 0xf086, &mmCGTT_WD_CLK_CTRL[0], sizeof(mmCGTT_WD_CLK_CTRL)/sizeof(mmCGTT_WD_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_PA_CLK_CTRL", REG_MMIO, 0xf088, &mmCGTT_PA_CLK_CTRL[0], sizeof(mmCGTT_PA_CLK_CTRL)/sizeof(mmCGTT_PA_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SC_CLK_CTRL", REG_MMIO, 0xf089, &mmCGTT_SC_CLK_CTRL[0], sizeof(mmCGTT_SC_CLK_CTRL)/sizeof(mmCGTT_SC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQ_CLK_CTRL", REG_MMIO, 0xf08c, &mmCGTT_SQ_CLK_CTRL[0], sizeof(mmCGTT_SQ_CLK_CTRL)/sizeof(mmCGTT_SQ_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQG_CLK_CTRL", REG_MMIO, 0xf08d, &mmCGTT_SQG_CLK_CTRL[0], sizeof(mmCGTT_SQG_CLK_CTRL)/sizeof(mmCGTT_SQG_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_ALU_CLK_CTRL", REG_MMIO, 0xf08e, &mmSQ_ALU_CLK_CTRL[0], sizeof(mmSQ_ALU_CLK_CTRL)/sizeof(mmSQ_ALU_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_TEX_CLK_CTRL", REG_MMIO, 0xf08f, &mmSQ_TEX_CLK_CTRL[0], sizeof(mmSQ_TEX_CLK_CTRL)/sizeof(mmSQ_TEX_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_LDS_CLK_CTRL", REG_MMIO, 0xf090, &mmSQ_LDS_CLK_CTRL[0], sizeof(mmSQ_LDS_CLK_CTRL)/sizeof(mmSQ_LDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE", REG_MMIO, 0xf091, &mmSQ_POWER_THROTTLE[0], sizeof(mmSQ_POWER_THROTTLE)/sizeof(mmSQ_POWER_THROTTLE[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE2", REG_MMIO, 0xf092, &mmSQ_POWER_THROTTLE2[0], sizeof(mmSQ_POWER_THROTTLE2)/sizeof(mmSQ_POWER_THROTTLE2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL0", REG_MMIO, 0xf094, &mmCGTT_SX_CLK_CTRL0[0], sizeof(mmCGTT_SX_CLK_CTRL0)/sizeof(mmCGTT_SX_CLK_CTRL0[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL1", REG_MMIO, 0xf095, &mmCGTT_SX_CLK_CTRL1[0], sizeof(mmCGTT_SX_CLK_CTRL1)/sizeof(mmCGTT_SX_CLK_CTRL1[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL2", REG_MMIO, 0xf096, &mmCGTT_SX_CLK_CTRL2[0], sizeof(mmCGTT_SX_CLK_CTRL2)/sizeof(mmCGTT_SX_CLK_CTRL2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL3", REG_MMIO, 0xf097, &mmCGTT_SX_CLK_CTRL3[0], sizeof(mmCGTT_SX_CLK_CTRL3)/sizeof(mmCGTT_SX_CLK_CTRL3[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL4", REG_MMIO, 0xf098, &mmCGTT_SX_CLK_CTRL4[0], sizeof(mmCGTT_SX_CLK_CTRL4)/sizeof(mmCGTT_SX_CLK_CTRL4[0]), 0, 0 },
+	{ "mmTD_CGTT_CTRL", REG_MMIO, 0xf09c, &mmTD_CGTT_CTRL[0], sizeof(mmTD_CGTT_CTRL)/sizeof(mmTD_CGTT_CTRL[0]), 0, 0 },
+	{ "mmTA_CGTT_CTRL", REG_MMIO, 0xf09d, &mmTA_CGTT_CTRL[0], sizeof(mmTA_CGTT_CTRL)/sizeof(mmTA_CGTT_CTRL[0]), 0, 0 },
+	{ "mmCGTT_TCP_CLK_CTRL", REG_MMIO, 0xf09e, &mmCGTT_TCP_CLK_CTRL[0], sizeof(mmCGTT_TCP_CLK_CTRL)/sizeof(mmCGTT_TCP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_TCI_CLK_CTRL", REG_MMIO, 0xf09f, &mmCGTT_TCI_CLK_CTRL[0], sizeof(mmCGTT_TCI_CLK_CTRL)/sizeof(mmCGTT_TCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_GDS_CLK_CTRL", REG_MMIO, 0xf0a0, &mmCGTT_GDS_CLK_CTRL[0], sizeof(mmCGTT_GDS_CLK_CTRL)/sizeof(mmCGTT_GDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmDB_CGTT_CLK_CTRL_0", REG_MMIO, 0xf0a4, &mmDB_CGTT_CLK_CTRL_0[0], sizeof(mmDB_CGTT_CLK_CTRL_0)/sizeof(mmDB_CGTT_CLK_CTRL_0[0]), 0, 0 },
+	{ "mmCB_CGTT_SCLK_CTRL", REG_MMIO, 0xf0a8, &mmCB_CGTT_SCLK_CTRL[0], sizeof(mmCB_CGTT_SCLK_CTRL)/sizeof(mmCB_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCC_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ac, &mmTCC_CGTT_SCLK_CTRL[0], sizeof(mmTCC_CGTT_SCLK_CTRL)/sizeof(mmTCC_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCA_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ad, &mmTCA_CGTT_SCLK_CTRL[0], sizeof(mmTCA_CGTT_SCLK_CTRL)/sizeof(mmTCA_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCS_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ae, &mmTCS_CGTT_SCLK_CTRL[0], sizeof(mmTCS_CGTT_SCLK_CTRL)/sizeof(mmTCS_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CP_CLK_CTRL", REG_MMIO, 0xf0b0, &mmCGTT_CP_CLK_CTRL[0], sizeof(mmCGTT_CP_CLK_CTRL)/sizeof(mmCGTT_CP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CPF_CLK_CTRL", REG_MMIO, 0xf0b1, &mmCGTT_CPF_CLK_CTRL[0], sizeof(mmCGTT_CPF_CLK_CTRL)/sizeof(mmCGTT_CPF_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CPC_CLK_CTRL", REG_MMIO, 0xf0b2, &mmCGTT_CPC_CLK_CTRL[0], sizeof(mmCGTT_CPC_CLK_CTRL)/sizeof(mmCGTT_CPC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_RLC_CLK_CTRL", REG_MMIO, 0xf0b8, &mmCGTT_RLC_CLK_CTRL[0], sizeof(mmCGTT_RLC_CLK_CTRL)/sizeof(mmCGTT_RLC_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_HV_VMID_CTRL", REG_MMIO, 0xf840, &mmSQ_HV_VMID_CTRL[0], sizeof(mmSQ_HV_VMID_CTRL)/sizeof(mmSQ_HV_VMID_CTRL[0]), 0, 0 },
+	{ "mmGFX_PIPE_PRIORITY", REG_MMIO, 0xf87f, &mmGFX_PIPE_PRIORITY[0], sizeof(mmGFX_PIPE_PRIORITY)/sizeof(mmGFX_PIPE_PRIORITY[0]), 0, 0 },
diff --git a/src/lib/ip/gfx80.c b/src/lib/ip/gfx80.c
new file mode 100644
index 0000000..211c925
--- /dev/null
+++ b/src/lib/ip/gfx80.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gfx80_bits.i"
+
+static const struct umr_reg gfx80_registers[] = {
+#include "gfx80_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_gfx80(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gfx80";
+	ip->no_regs = sizeof(gfx80_registers)/sizeof(gfx80_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gfx80_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 1) ? grant : deny;
+	memcpy(ip->regs, gfx80_registers, sizeof(gfx80_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gfx80_bits.i b/src/lib/ip/gfx80_bits.i
new file mode 100644
index 0000000..ddb36f7
--- /dev/null
+++ b/src/lib/ip/gfx80_bits.i
@@ -0,0 +1,15214 @@
+static struct umr_bitfield ixCLIPPER_DEBUG_REG00[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 8, 8, &umr_bitfield_default },
+	 { "su_clip_baryc_free", 9, 10, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 11, 11, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_full", 12, 12, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_empty", 13, 13, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_full", 14, 14, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_full", 16, 16, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_empty", 17, 17, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_full", 18, 18, &umr_bitfield_default },
+	 { "vgt_to_clips_fifo_empty", 19, 19, &umr_bitfield_default },
+	 { "vgt_to_clips_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "clipcode_fifo_fifo_empty", 21, 21, &umr_bitfield_default },
+	 { "clipcode_fifo_full", 22, 22, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_empty", 23, 23, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_write", 30, 30, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPA_SC_DEBUG_REG0[] = {
+	 { "REG0_FIELD0", 0, 1, &umr_bitfield_default },
+	 { "REG0_FIELD1", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_CONNECT[] = {
+	 { "DOORBELL_OFFSET", 0, 20, &umr_bitfield_default },
+	 { "QUEUE_ID", 21, 23, &umr_bitfield_default },
+	 { "VMID", 26, 29, &umr_bitfield_default },
+	 { "UNORD_DISP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG0[] = {
+	 { "wd_busy_extended", 0, 0, &umr_bitfield_default },
+	 { "wd_nodma_busy_extended", 1, 1, &umr_bitfield_default },
+	 { "wd_busy", 2, 2, &umr_bitfield_default },
+	 { "wd_nodma_busy", 3, 3, &umr_bitfield_default },
+	 { "rbiu_busy", 4, 4, &umr_bitfield_default },
+	 { "spl_dma_busy", 5, 5, &umr_bitfield_default },
+	 { "spl_di_busy", 6, 6, &umr_bitfield_default },
+	 { "vgt0_active_q", 7, 7, &umr_bitfield_default },
+	 { "vgt1_active_q", 8, 8, &umr_bitfield_default },
+	 { "spl_dma_p1_busy", 9, 9, &umr_bitfield_default },
+	 { "rbiu_dr_p1_fifo_busy", 10, 10, &umr_bitfield_default },
+	 { "rbiu_di_p1_fifo_busy", 11, 11, &umr_bitfield_default },
+	 { "SPARE2", 12, 12, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_busy", 13, 13, &umr_bitfield_default },
+	 { "rbiu_spl_dr_valid", 14, 14, &umr_bitfield_default },
+	 { "spl_rbiu_dr_read", 15, 15, &umr_bitfield_default },
+	 { "SPARE3", 16, 16, &umr_bitfield_default },
+	 { "rbiu_di_fifo_busy", 17, 17, &umr_bitfield_default },
+	 { "rbiu_spl_di_valid", 18, 18, &umr_bitfield_default },
+	 { "spl_rbiu_di_read", 19, 19, &umr_bitfield_default },
+	 { "se0_synced_q", 20, 20, &umr_bitfield_default },
+	 { "se1_synced_q", 21, 21, &umr_bitfield_default },
+	 { "se2_synced_q", 22, 22, &umr_bitfield_default },
+	 { "se3_synced_q", 23, 23, &umr_bitfield_default },
+	 { "reg_clk_busy", 24, 24, &umr_bitfield_default },
+	 { "input_clk_busy", 25, 25, &umr_bitfield_default },
+	 { "core_clk_busy", 26, 26, &umr_bitfield_default },
+	 { "vgt2_active_q", 27, 27, &umr_bitfield_default },
+	 { "sclk_reg_vld", 28, 28, &umr_bitfield_default },
+	 { "sclk_input_vld", 29, 29, &umr_bitfield_default },
+	 { "sclk_core_vld", 30, 30, &umr_bitfield_default },
+	 { "vgt3_active_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG01[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_extra_bc_valid", 8, 10, &umr_bitfield_default },
+	 { "clip_vert_vte_valid", 11, 13, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_deallocate", 14, 16, &umr_bitfield_default },
+	 { "clip_to_outsm_deallocate_slot", 17, 19, &umr_bitfield_default },
+	 { "clip_to_outsm_null_primitive", 20, 20, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_2", 21, 21, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_1", 22, 22, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_0", 23, 23, &umr_bitfield_default },
+	 { "vte_out_clip_rd_extra_bc_valid", 24, 24, &umr_bitfield_default },
+	 { "vte_out_clip_rd_vte_naninf_kill", 25, 25, &umr_bitfield_default },
+	 { "vte_out_clip_rd_vertex_store_indx", 26, 27, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 28, 28, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_empty", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPA_SC_DEBUG_REG1[] = {
+	 { "REG1_FIELD0", 0, 1, &umr_bitfield_default },
+	 { "REG1_FIELD1", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG1[] = {
+	 { "tag_hit", 0, 0, &umr_bitfield_default },
+	 { "tag_miss", 1, 1, &umr_bitfield_default },
+	 { "pixel_addr", 2, 16, &umr_bitfield_default },
+	 { "pixel_vld", 17, 17, &umr_bitfield_default },
+	 { "data_ready", 18, 18, &umr_bitfield_default },
+	 { "awaiting_data", 19, 19, &umr_bitfield_default },
+	 { "addr_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "addr_fifo_empty", 21, 21, &umr_bitfield_default },
+	 { "buffer_loaded", 22, 22, &umr_bitfield_default },
+	 { "buffer_invalid", 23, 23, &umr_bitfield_default },
+	 { "spare", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG1[] = {
+	 { "grbm_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "grbm_fifo_full", 1, 1, &umr_bitfield_default },
+	 { "grbm_fifo_we", 2, 2, &umr_bitfield_default },
+	 { "grbm_fifo_re", 3, 3, &umr_bitfield_default },
+	 { "draw_initiator_valid_q", 4, 4, &umr_bitfield_default },
+	 { "event_initiator_valid_q", 5, 5, &umr_bitfield_default },
+	 { "event_addr_valid_q", 6, 6, &umr_bitfield_default },
+	 { "dma_request_valid_q", 7, 7, &umr_bitfield_default },
+	 { "SPARE0", 8, 8, &umr_bitfield_default },
+	 { "min_indx_valid_q", 9, 9, &umr_bitfield_default },
+	 { "max_indx_valid_q", 10, 10, &umr_bitfield_default },
+	 { "indx_offset_valid_q", 11, 11, &umr_bitfield_default },
+	 { "grbm_fifo_rdata_reg_id", 12, 16, &umr_bitfield_default },
+	 { "grbm_fifo_rdata_state", 17, 19, &umr_bitfield_default },
+	 { "free_cnt_q", 20, 25, &umr_bitfield_default },
+	 { "rbiu_di_fifo_we", 26, 26, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_we", 27, 27, &umr_bitfield_default },
+	 { "rbiu_di_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "rbiu_di_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG16[] = {
+	 { "sm0_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm0_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm0_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm0_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm0_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm0_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm0_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm0_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm0_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm0_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm0_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG16[] = {
+	 { "gog_busy", 0, 0, &umr_bitfield_default },
+	 { "gog_state_q", 1, 3, &umr_bitfield_default },
+	 { "r0_rtr", 4, 4, &umr_bitfield_default },
+	 { "r1_rtr", 5, 5, &umr_bitfield_default },
+	 { "r1_upstream_rtr", 6, 6, &umr_bitfield_default },
+	 { "r2_vs_tbl_rtr", 7, 7, &umr_bitfield_default },
+	 { "r2_prim_rtr", 8, 8, &umr_bitfield_default },
+	 { "r2_indx_rtr", 9, 9, &umr_bitfield_default },
+	 { "r2_rtr", 10, 10, &umr_bitfield_default },
+	 { "gog_tm_vs_event_rtr", 11, 11, &umr_bitfield_default },
+	 { "r3_force_vs_tbl_we_rtr", 12, 12, &umr_bitfield_default },
+	 { "indx_valid_r2_q", 13, 13, &umr_bitfield_default },
+	 { "prim_valid_r2_q", 14, 14, &umr_bitfield_default },
+	 { "valid_r2_q", 15, 15, &umr_bitfield_default },
+	 { "prim_valid_r1_q", 16, 16, &umr_bitfield_default },
+	 { "indx_valid_r1_q", 17, 17, &umr_bitfield_default },
+	 { "valid_r1_q", 18, 18, &umr_bitfield_default },
+	 { "indx_valid_r0_q", 19, 19, &umr_bitfield_default },
+	 { "prim_valid_r0_q", 20, 20, &umr_bitfield_default },
+	 { "valid_r0_q", 21, 21, &umr_bitfield_default },
+	 { "send_event_q", 22, 22, &umr_bitfield_default },
+	 { "SPARE24", 23, 23, &umr_bitfield_default },
+	 { "vert_seen_since_sopg_r2_q", 24, 24, &umr_bitfield_default },
+	 { "gog_out_prim_state_sel", 25, 27, &umr_bitfield_default },
+	 { "multiple_streams_en_r1_q", 28, 28, &umr_bitfield_default },
+	 { "vs_vert_count_r2_q_not_0", 29, 29, &umr_bitfield_default },
+	 { "num_gs_r2_q_not_0", 30, 30, &umr_bitfield_default },
+	 { "new_vs_thread_r2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG17[] = {
+	 { "sm1_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm1_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm1_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm1_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm1_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm1_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm1_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm1_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm1_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm1_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm1_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG17[] = {
+	 { "gog_out_prim_rel_indx2_5_0", 0, 5, &umr_bitfield_default },
+	 { "gog_out_prim_rel_indx1_5_0", 6, 11, &umr_bitfield_default },
+	 { "gog_out_prim_rel_indx0_5_0", 12, 17, &umr_bitfield_default },
+	 { "gog_out_indx_13_0", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_MODE[] = {
+	 { "FP_ROUND", 0, 3, &umr_bitfield_default },
+	 { "FP_DENORM", 4, 7, &umr_bitfield_default },
+	 { "DX10_CLAMP", 8, 8, &umr_bitfield_default },
+	 { "IEEE", 9, 9, &umr_bitfield_default },
+	 { "LOD_CLAMPED", 10, 10, &umr_bitfield_default },
+	 { "DEBUG_EN", 11, 11, &umr_bitfield_default },
+	 { "EXCP_EN", 12, 20, &umr_bitfield_default },
+	 { "GPR_IDX_EN", 27, 27, &umr_bitfield_default },
+	 { "VSKIP", 28, 28, &umr_bitfield_default },
+	 { "CSP", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG18[] = {
+	 { "sm2_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm2_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm2_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm2_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm2_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm2_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm2_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm2_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm2_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm2_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm2_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_STATUS[] = {
+	 { "SCC", 0, 0, &umr_bitfield_default },
+	 { "SPI_PRIO", 1, 2, &umr_bitfield_default },
+	 { "USER_PRIO", 3, 4, &umr_bitfield_default },
+	 { "PRIV", 5, 5, &umr_bitfield_default },
+	 { "TRAP_EN", 6, 6, &umr_bitfield_default },
+	 { "TTRACE_EN", 7, 7, &umr_bitfield_default },
+	 { "EXPORT_RDY", 8, 8, &umr_bitfield_default },
+	 { "EXECZ", 9, 9, &umr_bitfield_default },
+	 { "VCCZ", 10, 10, &umr_bitfield_default },
+	 { "IN_TG", 11, 11, &umr_bitfield_default },
+	 { "IN_BARRIER", 12, 12, &umr_bitfield_default },
+	 { "HALT", 13, 13, &umr_bitfield_default },
+	 { "TRAP", 14, 14, &umr_bitfield_default },
+	 { "TTRACE_CU_EN", 15, 15, &umr_bitfield_default },
+	 { "VALID", 16, 16, &umr_bitfield_default },
+	 { "ECC_ERR", 17, 17, &umr_bitfield_default },
+	 { "SKIP_EXPORT", 18, 18, &umr_bitfield_default },
+	 { "PERF_EN", 19, 19, &umr_bitfield_default },
+	 { "COND_DBG_USER", 20, 20, &umr_bitfield_default },
+	 { "COND_DBG_SYS", 21, 21, &umr_bitfield_default },
+	 { "ALLOW_REPLAY", 22, 22, &umr_bitfield_default },
+	 { "INST_ATC", 23, 23, &umr_bitfield_default },
+	 { "MUST_EXPORT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG19[] = {
+	 { "sm3_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm3_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm3_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm3_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm3_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm3_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm3_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm3_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm3_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm3_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm3_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TRAPSTS[] = {
+	 { "EXCP", 0, 8, &umr_bitfield_default },
+	 { "SAVECTX", 10, 10, &umr_bitfield_default },
+	 { "EXCP_CYCLE", 16, 21, &umr_bitfield_default },
+	 { "DP_RATE", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG0[] = {
+	 { "position_address", 0, 5, &umr_bitfield_default },
+	 { "point_address", 6, 8, &umr_bitfield_default },
+	 { "sx_pending_rd_state_var_indx", 9, 11, &umr_bitfield_default },
+	 { "sx_pending_rd_req_mask", 12, 15, &umr_bitfield_default },
+	 { "sx_pending_rd_pci", 16, 25, &umr_bitfield_default },
+	 { "sx_pending_rd_aux_sel", 26, 27, &umr_bitfield_default },
+	 { "sx_pending_rd_sp_id", 28, 29, &umr_bitfield_default },
+	 { "sx_pending_rd_aux_inc", 30, 30, &umr_bitfield_default },
+	 { "sx_pending_rd_advance", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG20[] = {
+	 { "dbg_VGT_SPI_vsthread_sovertexindex", 0, 15, &umr_bitfield_default },
+	 { "dbg_VGT_SPI_vsthread_sovertexcount_not_0", 16, 16, &umr_bitfield_default },
+	 { "SPARE17", 17, 17, &umr_bitfield_default },
+	 { "alloc_counter_q", 18, 21, &umr_bitfield_default },
+	 { "curr_dealloc_distance_q", 22, 28, &umr_bitfield_default },
+	 { "new_allocate_q", 29, 29, &umr_bitfield_default },
+	 { "curr_slot_in_vtx_vect_q_not_0", 30, 30, &umr_bitfield_default },
+	 { "int_vtx_counter_q_not_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_HW_ID[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "PIPE_ID", 6, 7, &umr_bitfield_default },
+	 { "CU_ID", 8, 11, &umr_bitfield_default },
+	 { "SH_ID", 12, 12, &umr_bitfield_default },
+	 { "SE_ID", 13, 14, &umr_bitfield_default },
+	 { "TG_ID", 16, 19, &umr_bitfield_default },
+	 { "VM_ID", 20, 23, &umr_bitfield_default },
+	 { "QUEUE_ID", 24, 26, &umr_bitfield_default },
+	 { "STATE_ID", 27, 29, &umr_bitfield_default },
+	 { "ME_ID", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG1[] = {
+	 { "available_positions", 0, 6, &umr_bitfield_default },
+	 { "sx_receive_indx", 7, 9, &umr_bitfield_default },
+	 { "sx_pending_fifo_contents", 10, 14, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_misc_vec_ena", 15, 15, &umr_bitfield_default },
+	 { "statevar_bits_disable_sp", 16, 19, &umr_bitfield_default },
+	 { "aux_sel", 20, 21, &umr_bitfield_default },
+	 { "sx_to_pa_empty_1", 22, 22, &umr_bitfield_default },
+	 { "sx_to_pa_empty_0", 23, 23, &umr_bitfield_default },
+	 { "pasx_req_cnt_1", 24, 27, &umr_bitfield_default },
+	 { "pasx_req_cnt_0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_GPR_ALLOC[] = {
+	 { "VGPR_BASE", 0, 5, &umr_bitfield_default },
+	 { "VGPR_SIZE", 8, 13, &umr_bitfield_default },
+	 { "SGPR_BASE", 16, 21, &umr_bitfield_default },
+	 { "SGPR_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG21[] = {
+	 { "out_indx_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "indx_side_fifo_empty", 1, 1, &umr_bitfield_default },
+	 { "pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe2_dr", 4, 4, &umr_bitfield_default },
+	 { "vsthread_buff_empty", 5, 5, &umr_bitfield_default },
+	 { "out_indx_fifo_full", 6, 6, &umr_bitfield_default },
+	 { "indx_side_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "pipe0_rtr", 8, 8, &umr_bitfield_default },
+	 { "pipe1_rtr", 9, 9, &umr_bitfield_default },
+	 { "pipe2_rtr", 10, 10, &umr_bitfield_default },
+	 { "vsthread_buff_full", 11, 11, &umr_bitfield_default },
+	 { "interfaces_rtr", 12, 12, &umr_bitfield_default },
+	 { "indx_count_q_not_0", 13, 13, &umr_bitfield_default },
+	 { "wait_for_external_eopg_q", 14, 14, &umr_bitfield_default },
+	 { "full_state_p1_q", 15, 15, &umr_bitfield_default },
+	 { "indx_side_indx_valid", 16, 16, &umr_bitfield_default },
+	 { "stateid_p0_q", 17, 19, &umr_bitfield_default },
+	 { "is_event_p0_q", 20, 20, &umr_bitfield_default },
+	 { "lshs_dealloc_p1", 21, 21, &umr_bitfield_default },
+	 { "stream_id_r2_q", 22, 22, &umr_bitfield_default },
+	 { "vtx_vect_counter_q_not_0", 23, 23, &umr_bitfield_default },
+	 { "buff_full_p1", 24, 24, &umr_bitfield_default },
+	 { "strmout_valid_p1", 25, 25, &umr_bitfield_default },
+	 { "eotg_r2_q", 26, 26, &umr_bitfield_default },
+	 { "null_r2_q", 27, 27, &umr_bitfield_default },
+	 { "p0_dr", 28, 28, &umr_bitfield_default },
+	 { "p0_rtr", 29, 29, &umr_bitfield_default },
+	 { "eopg_p0_q", 30, 30, &umr_bitfield_default },
+	 { "p0_nobp", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG2[] = {
+	 { "param_cache_base", 0, 6, &umr_bitfield_default },
+	 { "sx_aux", 7, 8, &umr_bitfield_default },
+	 { "sx_request_indx", 9, 14, &umr_bitfield_default },
+	 { "req_active_verts_loaded", 15, 15, &umr_bitfield_default },
+	 { "req_active_verts", 16, 22, &umr_bitfield_default },
+	 { "vgt_to_ccgen_state_var_indx", 23, 25, &umr_bitfield_default },
+	 { "vgt_to_ccgen_active_verts", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_LDS_ALLOC[] = {
+	 { "LDS_BASE", 0, 7, &umr_bitfield_default },
+	 { "LDS_SIZE", 12, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG22[] = {
+	 { "cm_state16", 0, 1, &umr_bitfield_default },
+	 { "cm_state17", 2, 3, &umr_bitfield_default },
+	 { "cm_state18", 4, 5, &umr_bitfield_default },
+	 { "cm_state19", 6, 7, &umr_bitfield_default },
+	 { "cm_state20", 8, 9, &umr_bitfield_default },
+	 { "cm_state21", 10, 11, &umr_bitfield_default },
+	 { "cm_state22", 12, 13, &umr_bitfield_default },
+	 { "cm_state23", 14, 15, &umr_bitfield_default },
+	 { "cm_state24", 16, 17, &umr_bitfield_default },
+	 { "cm_state25", 18, 19, &umr_bitfield_default },
+	 { "cm_state26", 20, 21, &umr_bitfield_default },
+	 { "cm_state27", 22, 23, &umr_bitfield_default },
+	 { "cm_state28", 24, 25, &umr_bitfield_default },
+	 { "cm_state29", 26, 27, &umr_bitfield_default },
+	 { "cm_state30", 28, 29, &umr_bitfield_default },
+	 { "cm_state31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG3[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "vertex_fifo_entriesavailable", 8, 11, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_ccdist1_vec_ena", 12, 12, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_ccdist0_vec_ena", 13, 13, &umr_bitfield_default },
+	 { "available_positions", 14, 20, &umr_bitfield_default },
+	 { "current_state", 21, 22, &umr_bitfield_default },
+	 { "vertex_fifo_empty", 23, 23, &umr_bitfield_default },
+	 { "vertex_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "sx0_receive_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "sx0_receive_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "vgt_to_ccgen_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "vgt_to_ccgen_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "sx0_receive_fifo_write", 30, 30, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG23[] = {
+	 { "frmt_busy", 0, 0, &umr_bitfield_default },
+	 { "rcm_frmt_vert_rtr", 1, 1, &umr_bitfield_default },
+	 { "rcm_frmt_prim_rtr", 2, 2, &umr_bitfield_default },
+	 { "prim_r3_rtr", 3, 3, &umr_bitfield_default },
+	 { "prim_r2_rtr", 4, 4, &umr_bitfield_default },
+	 { "vert_r3_rtr", 5, 5, &umr_bitfield_default },
+	 { "vert_r2_rtr", 6, 6, &umr_bitfield_default },
+	 { "vert_r1_rtr", 7, 7, &umr_bitfield_default },
+	 { "vert_r0_rtr", 8, 8, &umr_bitfield_default },
+	 { "prim_fifo_empty", 9, 9, &umr_bitfield_default },
+	 { "prim_fifo_full", 10, 10, &umr_bitfield_default },
+	 { "vert_dr_r2_q", 11, 11, &umr_bitfield_default },
+	 { "prim_dr_r2_q", 12, 12, &umr_bitfield_default },
+	 { "vert_dr_r1_q", 13, 13, &umr_bitfield_default },
+	 { "vert_dr_r0_q", 14, 14, &umr_bitfield_default },
+	 { "new_verts_r2_q", 15, 16, &umr_bitfield_default },
+	 { "verts_sent_r2_q", 17, 20, &umr_bitfield_default },
+	 { "prim_state_sel_r2_q", 21, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_STS[] = {
+	 { "VM_CNT", 0, 3, &umr_bitfield_default },
+	 { "EXP_CNT", 4, 6, &umr_bitfield_default },
+	 { "LGKM_CNT", 8, 11, &umr_bitfield_default },
+	 { "VALU_CNT", 12, 14, &umr_bitfield_default },
+	 { "FIRST_REPLAY", 15, 15, &umr_bitfield_default },
+	 { "RCNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG0[] = {
+	 { "su_baryc_cntl_state", 0, 1, &umr_bitfield_default },
+	 { "su_cntl_state", 2, 5, &umr_bitfield_default },
+	 { "pmode_state", 8, 13, &umr_bitfield_default },
+	 { "ge_stallb", 14, 14, &umr_bitfield_default },
+	 { "geom_enable", 15, 15, &umr_bitfield_default },
+	 { "su_clip_baryc_free", 16, 17, &umr_bitfield_default },
+	 { "su_clip_rtr", 18, 18, &umr_bitfield_default },
+	 { "pfifo_busy", 19, 19, &umr_bitfield_default },
+	 { "su_cntl_busy", 20, 20, &umr_bitfield_default },
+	 { "geom_busy", 21, 21, &umr_bitfield_default },
+	 { "event_id_gated", 22, 27, &umr_bitfield_default },
+	 { "event_gated", 28, 28, &umr_bitfield_default },
+	 { "pmode_prim_gated", 29, 29, &umr_bitfield_default },
+	 { "su_dyn_sclk_vld", 30, 30, &umr_bitfield_default },
+	 { "cl_dyn_sclk_vld", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG24[] = {
+	 { "avail_es_rb_space_r0_q_23_0", 0, 23, &umr_bitfield_default },
+	 { "dependent_st_cut_mode_q", 24, 25, &umr_bitfield_default },
+	 { "SPARE31", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_PC_LO[] = {
+	 { "PC_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG1[] = {
+	 { "y_sort0_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort0_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG25[] = {
+	 { "avail_gs_rb_space_r0_q_25_0", 0, 25, &umr_bitfield_default },
+	 { "active_sm_r0_q", 26, 29, &umr_bitfield_default },
+	 { "add_gs_rb_space_r1_q", 30, 30, &umr_bitfield_default },
+	 { "add_gs_rb_space_r0_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_PC_HI[] = {
+	 { "PC_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG2[] = {
+	 { "y_sort1_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort1_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG3[] = {
+	 { "y_sort2_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort2_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG27[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "gsc0_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "tm_pt_event_rtr", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "gsc0_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipe1_rtr", 6, 6, &umr_bitfield_default },
+	 { "last_indx_of_prim_p1_q", 7, 7, &umr_bitfield_default },
+	 { "indices_to_send_p0_q", 8, 9, &umr_bitfield_default },
+	 { "event_flag_p1_q", 10, 10, &umr_bitfield_default },
+	 { "eop_p1_q", 11, 11, &umr_bitfield_default },
+	 { "gs_out_prim_type_p0_q", 12, 13, &umr_bitfield_default },
+	 { "gsc_null_primitive_p0_q", 14, 14, &umr_bitfield_default },
+	 { "gsc_eop_p0_q", 15, 15, &umr_bitfield_default },
+	 { "gsc_2cycle_output", 16, 16, &umr_bitfield_default },
+	 { "gsc_2nd_cycle_p0_q", 17, 17, &umr_bitfield_default },
+	 { "last_indx_of_vsprim", 18, 18, &umr_bitfield_default },
+	 { "first_vsprim_of_gsprim_p0_q", 19, 19, &umr_bitfield_default },
+	 { "gsc_indx_count_p0_q", 20, 30, &umr_bitfield_default },
+	 { "last_vsprim_of_gsprim", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG4[] = {
+	 { "attr_indx_sort0_gated", 0, 13, &umr_bitfield_default },
+	 { "null_prim_gated", 14, 14, &umr_bitfield_default },
+	 { "backfacing_gated", 15, 15, &umr_bitfield_default },
+	 { "st_indx_gated", 16, 18, &umr_bitfield_default },
+	 { "clipped_gated", 19, 19, &umr_bitfield_default },
+	 { "dealloc_slot_gated", 20, 22, &umr_bitfield_default },
+	 { "xmajor_gated", 23, 23, &umr_bitfield_default },
+	 { "diamond_rule_gated", 24, 25, &umr_bitfield_default },
+	 { "type_gated", 26, 28, &umr_bitfield_default },
+	 { "fpov_gated", 29, 30, &umr_bitfield_default },
+	 { "eop_gated", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_DBG0[] = {
+	 { "IBUF_ST", 0, 2, &umr_bitfield_default },
+	 { "PC_INVALID", 3, 3, &umr_bitfield_default },
+	 { "NEED_NEXT_DW", 4, 4, &umr_bitfield_default },
+	 { "NO_PREFETCH_CNT", 5, 7, &umr_bitfield_default },
+	 { "IBUF_RPTR", 8, 9, &umr_bitfield_default },
+	 { "IBUF_WPTR", 10, 11, &umr_bitfield_default },
+	 { "INST_STR_ST", 16, 19, &umr_bitfield_default },
+	 { "MISC_CNT", 20, 23, &umr_bitfield_default },
+	 { "ECC_ST", 24, 25, &umr_bitfield_default },
+	 { "IS_HYB", 26, 26, &umr_bitfield_default },
+	 { "HYB_CNT", 27, 28, &umr_bitfield_default },
+	 { "KILL", 29, 29, &umr_bitfield_default },
+	 { "NEED_KILL_IFETCH", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG5[] = {
+	 { "attr_indx_sort2_gated", 0, 13, &umr_bitfield_default },
+	 { "attr_indx_sort1_gated", 14, 27, &umr_bitfield_default },
+	 { "provoking_vtx_gated", 28, 29, &umr_bitfield_default },
+	 { "valid_prim_gated", 30, 30, &umr_bitfield_default },
+	 { "pa_reg_sclk_vld", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_DBG1[] = {
+	 { "IXNACK", 0, 0, &umr_bitfield_default },
+	 { "XNACK", 1, 1, &umr_bitfield_default },
+	 { "TA_NEED_RESET", 2, 2, &umr_bitfield_default },
+	 { "XCNT", 4, 7, &umr_bitfield_default },
+	 { "QCNT", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_THREAD_TRACE_TG0[] = {
+	 { "TGID_X", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG2[] = {
+	 { "hs_grp_busy", 0, 0, &umr_bitfield_default },
+	 { "hs_noif_busy", 1, 1, &umr_bitfield_default },
+	 { "tfmmIsBusy", 2, 2, &umr_bitfield_default },
+	 { "lsVertIfBusy_0", 3, 3, &umr_bitfield_default },
+	 { "te11_hs_tess_input_rtr", 4, 4, &umr_bitfield_default },
+	 { "lsWaveIfBusy_0", 5, 5, &umr_bitfield_default },
+	 { "hs_te11_tess_input_rts", 6, 6, &umr_bitfield_default },
+	 { "grpModBusy", 7, 7, &umr_bitfield_default },
+	 { "lsVertFifoEmpty", 8, 8, &umr_bitfield_default },
+	 { "lsWaveFifoEmpty", 9, 9, &umr_bitfield_default },
+	 { "hsVertFifoEmpty", 10, 10, &umr_bitfield_default },
+	 { "hsWaveFifoEmpty", 11, 11, &umr_bitfield_default },
+	 { "hsInputFifoEmpty", 12, 12, &umr_bitfield_default },
+	 { "hsTifFifoEmpty", 13, 13, &umr_bitfield_default },
+	 { "lsVertFifoFull", 14, 14, &umr_bitfield_default },
+	 { "lsWaveFifoFull", 15, 15, &umr_bitfield_default },
+	 { "hsVertFifoFull", 16, 16, &umr_bitfield_default },
+	 { "hsWaveFifoFull", 17, 17, &umr_bitfield_default },
+	 { "hsInputFifoFull", 18, 18, &umr_bitfield_default },
+	 { "hsTifFifoFull", 19, 19, &umr_bitfield_default },
+	 { "p0_rtr", 20, 20, &umr_bitfield_default },
+	 { "p1_rtr", 21, 21, &umr_bitfield_default },
+	 { "p0_dr", 22, 22, &umr_bitfield_default },
+	 { "p1_dr", 23, 23, &umr_bitfield_default },
+	 { "p0_rts", 24, 24, &umr_bitfield_default },
+	 { "p1_rts", 25, 25, &umr_bitfield_default },
+	 { "ls_sh_id", 26, 26, &umr_bitfield_default },
+	 { "lsFwaveFlag", 27, 27, &umr_bitfield_default },
+	 { "lsWaveSendFlush", 28, 28, &umr_bitfield_default },
+	 { "SPARE", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_THREAD_TRACE_EVENT[] = {
+	 { "EVENT_ID", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG3[] = {
+	 { "lsTgRelInd", 0, 11, &umr_bitfield_default },
+	 { "lsWaveRelInd", 12, 17, &umr_bitfield_default },
+	 { "lsPatchCnt", 18, 25, &umr_bitfield_default },
+	 { "hsWaveRelInd", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG02[] = {
+	 { "clip_extra_bc_valid", 0, 2, &umr_bitfield_default },
+	 { "clip_vert_vte_valid", 3, 5, &umr_bitfield_default },
+	 { "clip_to_outsm_clip_seq_indx", 6, 7, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_2", 8, 11, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_1", 12, 15, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_0", 16, 19, &umr_bitfield_default },
+	 { "clip_to_clipga_extra_bc_coords", 20, 20, &umr_bitfield_default },
+	 { "clip_to_clipga_vte_naninf_kill", 21, 21, &umr_bitfield_default },
+	 { "clip_to_outsm_end_of_packet", 22, 22, &umr_bitfield_default },
+	 { "clip_to_outsm_first_prim_of_slot", 23, 23, &umr_bitfield_default },
+	 { "clip_to_outsm_clipped_prim", 24, 24, &umr_bitfield_default },
+	 { "clip_to_outsm_null_primitive", 25, 25, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 28, 28, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_empty", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG2[] = {
+	 { "ds_full", 0, 0, &umr_bitfield_default },
+	 { "ds_credit_avail", 1, 1, &umr_bitfield_default },
+	 { "ord_idx_free", 2, 2, &umr_bitfield_default },
+	 { "cmd_write", 3, 3, &umr_bitfield_default },
+	 { "app_sel", 4, 7, &umr_bitfield_default },
+	 { "req", 8, 22, &umr_bitfield_default },
+	 { "spare", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG2[] = {
+	 { "p1_grbm_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "p1_grbm_fifo_full", 1, 1, &umr_bitfield_default },
+	 { "p1_grbm_fifo_we", 2, 2, &umr_bitfield_default },
+	 { "p1_grbm_fifo_re", 3, 3, &umr_bitfield_default },
+	 { "p1_draw_initiator_valid_q", 4, 4, &umr_bitfield_default },
+	 { "p1_event_initiator_valid_q", 5, 5, &umr_bitfield_default },
+	 { "p1_event_addr_valid_q", 6, 6, &umr_bitfield_default },
+	 { "p1_dma_request_valid_q", 7, 7, &umr_bitfield_default },
+	 { "SPARE0", 8, 8, &umr_bitfield_default },
+	 { "p1_min_indx_valid_q", 9, 9, &umr_bitfield_default },
+	 { "p1_max_indx_valid_q", 10, 10, &umr_bitfield_default },
+	 { "p1_indx_offset_valid_q", 11, 11, &umr_bitfield_default },
+	 { "p1_grbm_fifo_rdata_reg_id", 12, 16, &umr_bitfield_default },
+	 { "p1_grbm_fifo_rdata_state", 17, 19, &umr_bitfield_default },
+	 { "p1_free_cnt_q", 20, 25, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_we", 26, 26, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_we", 27, 27, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG4[] = {
+	 { "hsPatchCnt", 0, 7, &umr_bitfield_default },
+	 { "hsPrimId_15_0", 8, 23, &umr_bitfield_default },
+	 { "hsCpCnt", 24, 28, &umr_bitfield_default },
+	 { "hsWaveSendFlush", 29, 29, &umr_bitfield_default },
+	 { "hsFwaveFlag", 30, 30, &umr_bitfield_default },
+	 { "SPARE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CNTL[] = {
+	 { "READ_TIMEOUT", 0, 7, &umr_bitfield_default },
+	 { "REPORT_LAST_RDERR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SKEW_CNTL[] = {
+	 { "SKEW_TOP_THRESHOLD", 0, 5, &umr_bitfield_default },
+	 { "SKEW_COUNT", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS2[] = {
+	 { "ME0PIPE1_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "ME0PIPE1_CF_RQ_PENDING", 4, 4, &umr_bitfield_default },
+	 { "ME0PIPE1_PF_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME1PIPE0_RQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "ME1PIPE1_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME1PIPE2_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "ME1PIPE3_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "ME2PIPE0_RQ_PENDING", 10, 10, &umr_bitfield_default },
+	 { "ME2PIPE1_RQ_PENDING", 11, 11, &umr_bitfield_default },
+	 { "ME2PIPE2_RQ_PENDING", 12, 12, &umr_bitfield_default },
+	 { "ME2PIPE3_RQ_PENDING", 13, 13, &umr_bitfield_default },
+	 { "RLC_RQ_PENDING", 14, 14, &umr_bitfield_default },
+	 { "RLC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TC_BUSY", 25, 25, &umr_bitfield_default },
+	 { "TCC_CC_RESIDENT", 26, 26, &umr_bitfield_default },
+	 { "CPF_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPG_BUSY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PWR_CNTL[] = {
+	 { "ALL_REQ_TYPE", 0, 1, &umr_bitfield_default },
+	 { "GFX_REQ_TYPE", 2, 3, &umr_bitfield_default },
+	 { "ALL_RSP_TYPE", 4, 5, &umr_bitfield_default },
+	 { "GFX_RSP_TYPE", 6, 7, &umr_bitfield_default },
+	 { "GFX_REQ_EN", 14, 14, &umr_bitfield_default },
+	 { "ALL_REQ_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS[] = {
+	 { "ME0PIPE0_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "SRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME0PIPE0_CF_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME0PIPE0_PF_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "GDS_DMA_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "DB_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "CB_CLEAN", 13, 13, &umr_bitfield_default },
+	 { "TA_BUSY", 14, 14, &umr_bitfield_default },
+	 { "GDS_BUSY", 15, 15, &umr_bitfield_default },
+	 { "WD_BUSY_NO_DMA", 16, 16, &umr_bitfield_default },
+	 { "VGT_BUSY", 17, 17, &umr_bitfield_default },
+	 { "IA_BUSY_NO_DMA", 18, 18, &umr_bitfield_default },
+	 { "IA_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SX_BUSY", 20, 20, &umr_bitfield_default },
+	 { "WD_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SPI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "BCI_BUSY", 23, 23, &umr_bitfield_default },
+	 { "SC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "PA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "DB_BUSY", 26, 26, &umr_bitfield_default },
+	 { "CP_COHERENCY_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CP_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "GUI_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE0[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE1[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SOFT_RESET[] = {
+	 { "SOFT_RESET_CP", 0, 0, &umr_bitfield_default },
+	 { "SOFT_RESET_RLC", 2, 2, &umr_bitfield_default },
+	 { "SOFT_RESET_GFX", 16, 16, &umr_bitfield_default },
+	 { "SOFT_RESET_CPF", 17, 17, &umr_bitfield_default },
+	 { "SOFT_RESET_CPC", 18, 18, &umr_bitfield_default },
+	 { "SOFT_RESET_CPG", 19, 19, &umr_bitfield_default },
+	 { "SOFT_RESET_CAC", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_CNTL[] = {
+	 { "GRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_GFX_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_WAIT_IDLE_CLOCKS[] = {
+	 { "WAIT_IDLE_CLOCKS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE2[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE3[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG[] = {
+	 { "IGNORE_RDY", 1, 1, &umr_bitfield_default },
+	 { "IGNORE_FAO", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_READ_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "SNAPSHOT_FREE_CNTRS", 7, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_GUI_ACTIVE", 8, 11, &umr_bitfield_default },
+	 { "GFX_CLOCK_DOMAIN_OVERRIDE", 12, 12, &umr_bitfield_default },
+	 { "GRBM_TRAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_BUS_FGCG_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_SNAPSHOT[] = {
+	 { "CPF_RDY", 0, 0, &umr_bitfield_default },
+	 { "CPG_RDY", 1, 1, &umr_bitfield_default },
+	 { "SRBM_RDY", 2, 2, &umr_bitfield_default },
+	 { "WD_ME0PIPE0_RDY", 3, 3, &umr_bitfield_default },
+	 { "WD_ME0PIPE1_RDY", 4, 4, &umr_bitfield_default },
+	 { "GDS_RDY", 5, 5, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY0", 6, 6, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY0", 7, 7, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY0", 8, 8, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY0", 9, 9, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY0", 10, 10, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY0", 11, 11, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY0", 12, 12, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY0", 13, 13, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY1", 14, 14, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY1", 15, 15, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY1", 16, 16, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY1", 17, 17, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY1", 18, 18, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY1", 19, 19, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY1", 20, 20, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY1", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_READ_ERROR[] = {
+	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "READ_PIPEID", 20, 21, &umr_bitfield_default },
+	 { "READ_MEID", 22, 23, &umr_bitfield_default },
+	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_READ_ERROR2[] = {
+	 { "READ_REQUESTER_SRBM", 17, 17, &umr_bitfield_default },
+	 { "READ_REQUESTER_RLC", 18, 18, &umr_bitfield_default },
+	 { "READ_REQUESTER_GDS_DMA", 19, 19, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE0_CF", 20, 20, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE0_PF", 21, 21, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE1_CF", 22, 22, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE1_PF", 23, 23, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE0", 24, 24, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE1", 25, 25, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE2", 26, 26, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE3", 27, 27, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE0", 28, 28, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE1", 29, 29, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE2", 30, 30, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_INT_CNTL[] = {
+	 { "RDERR_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GUI_IDLE_INT_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_OP[] = {
+	 { "RW", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_ADDR[] = {
+	 { "DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_ADDR_MSK[] = {
+	 { "DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_WD[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_WD_MSK[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DSM_BYPASS[] = {
+	 { "BYPASS_BITS", 0, 1, &umr_bitfield_default },
+	 { "BYPASS_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_WRITE_ERROR[] = {
+	 { "WRITE_REQUESTER_RLC", 0, 0, &umr_bitfield_default },
+	 { "WRITE_REQUESTER_SRBM", 1, 1, &umr_bitfield_default },
+	 { "WRITE_SSRCID", 2, 4, &umr_bitfield_default },
+	 { "WRITE_VFID", 5, 8, &umr_bitfield_default },
+	 { "WRITE_VF", 12, 12, &umr_bitfield_default },
+	 { "WRITE_VMID", 13, 16, &umr_bitfield_default },
+	 { "WRITE_PIPEID", 20, 21, &umr_bitfield_default },
+	 { "WRITE_MEID", 22, 23, &umr_bitfield_default },
+	 { "WRITE_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEBUG_INDEX[] = {
+	 { "DEBUG_INDEX", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEBUG_DATA[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_NOWHERE[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_STATUS[] = {
+	 { "MEC1_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MEC2_BUSY", 1, 1, &umr_bitfield_default },
+	 { "DC0_BUSY", 2, 2, &umr_bitfield_default },
+	 { "DC1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "RCIU1_BUSY", 4, 4, &umr_bitfield_default },
+	 { "RCIU2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "ROQ1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "ROQ2_BUSY", 7, 7, &umr_bitfield_default },
+	 { "TCIU_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 11, 11, &umr_bitfield_default },
+	 { "QU_BUSY", 12, 12, &umr_bitfield_default },
+	 { "ATCL2IU_BUSY", 13, 13, &umr_bitfield_default },
+	 { "CPG_CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPF_CPC_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CPC_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_BUSY_STAT[] = {
+	 { "MEC1_LOAD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MEC1_SEMAPOHRE_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MEC1_MUTEX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "MEC1_MESSAGE_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MEC1_EOP_QUEUE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "MEC1_IQ_QUEUE_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MEC1_IB_QUEUE_BUSY", 6, 6, &umr_bitfield_default },
+	 { "MEC1_TC_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MEC1_DMA_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MEC1_PARTIAL_FLUSH_BUSY", 9, 9, &umr_bitfield_default },
+	 { "MEC1_PIPE0_BUSY", 10, 10, &umr_bitfield_default },
+	 { "MEC1_PIPE1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "MEC1_PIPE2_BUSY", 12, 12, &umr_bitfield_default },
+	 { "MEC1_PIPE3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "MEC2_LOAD_BUSY", 16, 16, &umr_bitfield_default },
+	 { "MEC2_SEMAPOHRE_BUSY", 17, 17, &umr_bitfield_default },
+	 { "MEC2_MUTEX_BUSY", 18, 18, &umr_bitfield_default },
+	 { "MEC2_MESSAGE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "MEC2_EOP_QUEUE_BUSY", 20, 20, &umr_bitfield_default },
+	 { "MEC2_IQ_QUEUE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "MEC2_IB_QUEUE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "MEC2_TC_BUSY", 23, 23, &umr_bitfield_default },
+	 { "MEC2_DMA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "MEC2_PARTIAL_FLUSH_BUSY", 25, 25, &umr_bitfield_default },
+	 { "MEC2_PIPE0_BUSY", 26, 26, &umr_bitfield_default },
+	 { "MEC2_PIPE1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "MEC2_PIPE2_BUSY", 28, 28, &umr_bitfield_default },
+	 { "MEC2_PIPE3_BUSY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_STALLED_STAT1[] = {
+	 { "RCIU_TX_FREE_STALL", 3, 3, &umr_bitfield_default },
+	 { "RCIU_PRIV_VIOLATION", 4, 4, &umr_bitfield_default },
+	 { "TCIU_TX_FREE_STALL", 6, 6, &umr_bitfield_default },
+	 { "MEC1_DECODING_PACKET", 8, 8, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_RCIU", 9, 9, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_RCIU_READ", 10, 10, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_ROQ_DATA", 13, 13, &umr_bitfield_default },
+	 { "MEC2_DECODING_PACKET", 16, 16, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_RCIU", 17, 17, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_RCIU_READ", 18, 18, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_ROQ_DATA", 21, 21, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_FREE", 22, 22, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_TAGS", 23, 23, &umr_bitfield_default },
+	 { "ATCL1_WAITING_ON_TRANS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_STATUS[] = {
+	 { "POST_WPTR_GFX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CSF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ROQ_ALIGN_BUSY", 4, 4, &umr_bitfield_default },
+	 { "ROQ_RING_BUSY", 5, 5, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 7, 7, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 8, 8, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 13, 13, &umr_bitfield_default },
+	 { "TCIU_BUSY", 14, 14, &umr_bitfield_default },
+	 { "HQD_BUSY", 15, 15, &umr_bitfield_default },
+	 { "PRT_BUSY", 16, 16, &umr_bitfield_default },
+	 { "ATCL2IU_BUSY", 17, 17, &umr_bitfield_default },
+	 { "CPF_GFX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "CPF_CMP_BUSY", 27, 27, &umr_bitfield_default },
+	 { "GRBM_CPF_STAT_BUSY", 28, 29, &umr_bitfield_default },
+	 { "CPC_CPF_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CPF_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_BUSY_STAT[] = {
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CSF_RING_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CSF_INDIRECT1_BUSY", 2, 2, &umr_bitfield_default },
+	 { "CSF_INDIRECT2_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CSF_STATE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CSF_CE_INDR1_BUSY", 5, 5, &umr_bitfield_default },
+	 { "CSF_CE_INDR2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CSF_ARBITER_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CSF_INPUT_BUSY", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_READ_TAGS", 9, 9, &umr_bitfield_default },
+	 { "HPD_PROCESSING_EOP_BUSY", 11, 11, &umr_bitfield_default },
+	 { "HQD_DISPATCH_BUSY", 12, 12, &umr_bitfield_default },
+	 { "HQD_IQ_TIMER_BUSY", 13, 13, &umr_bitfield_default },
+	 { "HQD_DMA_OFFLOAD_BUSY", 14, 14, &umr_bitfield_default },
+	 { "HQD_WAIT_SEMAPHORE_BUSY", 15, 15, &umr_bitfield_default },
+	 { "HQD_SIGNAL_SEMAPHORE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "HQD_MESSAGE_BUSY", 17, 17, &umr_bitfield_default },
+	 { "HQD_PQ_FETCHER_BUSY", 18, 18, &umr_bitfield_default },
+	 { "HQD_IB_FETCHER_BUSY", 19, 19, &umr_bitfield_default },
+	 { "HQD_IQ_FETCHER_BUSY", 20, 20, &umr_bitfield_default },
+	 { "HQD_EOP_FETCHER_BUSY", 21, 21, &umr_bitfield_default },
+	 { "HQD_CONSUMED_RPTR_BUSY", 22, 22, &umr_bitfield_default },
+	 { "HQD_FETCHER_ARB_BUSY", 23, 23, &umr_bitfield_default },
+	 { "HQD_ROQ_ALIGN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "HQD_ROQ_EOP_BUSY", 25, 25, &umr_bitfield_default },
+	 { "HQD_ROQ_IQ_BUSY", 26, 26, &umr_bitfield_default },
+	 { "HQD_ROQ_PQ_BUSY", 27, 27, &umr_bitfield_default },
+	 { "HQD_ROQ_IB_BUSY", 28, 28, &umr_bitfield_default },
+	 { "HQD_WPTR_POLL_BUSY", 29, 29, &umr_bitfield_default },
+	 { "HQD_PQ_BUSY", 30, 30, &umr_bitfield_default },
+	 { "HQD_IB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_STALLED_STAT1[] = {
+	 { "RING_FETCHING_DATA", 0, 0, &umr_bitfield_default },
+	 { "INDR1_FETCHING_DATA", 1, 1, &umr_bitfield_default },
+	 { "INDR2_FETCHING_DATA", 2, 2, &umr_bitfield_default },
+	 { "STATE_FETCHING_DATA", 3, 3, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 5, 5, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 6, 6, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_FREE", 7, 7, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_TAGS", 8, 8, &umr_bitfield_default },
+	 { "ATCL1_WAITING_ON_TRANS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_CNTL[] = {
+	 { "MEC_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "MEC_ME1_PIPE0_RESET", 16, 16, &umr_bitfield_default },
+	 { "MEC_ME1_PIPE1_RESET", 17, 17, &umr_bitfield_default },
+	 { "MEC_ME1_PIPE2_RESET", 18, 18, &umr_bitfield_default },
+	 { "MEC_ME1_PIPE3_RESET", 19, 19, &umr_bitfield_default },
+	 { "MEC_ME2_PIPE0_RESET", 20, 20, &umr_bitfield_default },
+	 { "MEC_ME2_PIPE1_RESET", 21, 21, &umr_bitfield_default },
+	 { "MEC_ME2_HALT", 28, 28, &umr_bitfield_default },
+	 { "MEC_ME2_STEP", 29, 29, &umr_bitfield_default },
+	 { "MEC_ME1_HALT", 30, 30, &umr_bitfield_default },
+	 { "MEC_ME1_STEP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_HEADER_DUMP[] = {
+	 { "HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_HEADER_DUMP[] = {
+	 { "HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_HALT_HYST_COUNT[] = {
+	 { "COUNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL0[] = {
+	 { "BU_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL1[] = {
+	 { "BASE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL2[] = {
+	 { "BASE_HI", 0, 1, &umr_bitfield_default },
+	 { "INTERVAL", 2, 9, &umr_bitfield_default },
+	 { "RESET_CNT", 10, 17, &umr_bitfield_default },
+	 { "RESET_FORCE", 18, 18, &umr_bitfield_default },
+	 { "REPORT_AND_RESET", 19, 19, &umr_bitfield_default },
+	 { "MC_VMID", 23, 26, &umr_bitfield_default },
+	 { "CACHE_POLICY", 28, 28, &umr_bitfield_default },
+	 { "MTYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_INTERRUPT_WORD_AUTO[] = {
+	 { "THREAD_TRACE", 0, 0, &umr_bitfield_default },
+	 { "WLT", 1, 1, &umr_bitfield_default },
+	 { "THREAD_TRACE_BUF_FULL", 2, 2, &umr_bitfield_default },
+	 { "REG_TIMESTAMP", 3, 3, &umr_bitfield_default },
+	 { "CMD_TIMESTAMP", 4, 4, &umr_bitfield_default },
+	 { "HOST_CMD_OVERFLOW", 5, 5, &umr_bitfield_default },
+	 { "HOST_REG_OVERFLOW", 6, 6, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "SE_ID", 24, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_INTERRUPT_WORD_CMN[] = {
+	 { "SE_ID", 24, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_COMPARE_COUNT[] = {
+	 { "COMPARE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_DE_COUNT[] = {
+	 { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_CE_COUNT[] = {
+	 { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_LAST_INVAL_COUNT[] = {
+	 { "LAST_INVAL_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_DE_COUNT[] = {
+	 { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG5[] = {
+	 { "SPARE4", 0, 2, &umr_bitfield_default },
+	 { "hsWaveCreditCnt_0", 3, 7, &umr_bitfield_default },
+	 { "SPARE3", 8, 10, &umr_bitfield_default },
+	 { "hsVertCreditCnt_0", 11, 15, &umr_bitfield_default },
+	 { "SPARE2", 16, 18, &umr_bitfield_default },
+	 { "lsWaveCreditCnt_0", 19, 23, &umr_bitfield_default },
+	 { "SPARE1", 24, 26, &umr_bitfield_default },
+	 { "lsVertCreditCnt_0", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT3[] = {
+	 { "CE_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER", 2, 2, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_NOT_RDY", 3, 3, &umr_bitfield_default },
+	 { "CE_TO_RAM_DUMP_NOT_RDY", 4, 4, &umr_bitfield_default },
+	 { "CE_TO_RAM_WRITE_NOT_RDY", 5, 5, &umr_bitfield_default },
+	 { "CE_TO_INC_FIFO_NOT_RDY_TO_RCV", 6, 6, &umr_bitfield_default },
+	 { "CE_TO_WR_FIFO_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default },
+	 { "CE_WAITING_ON_BUFFER_DATA", 10, 10, &umr_bitfield_default },
+	 { "CE_WAITING_ON_CE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER", 12, 12, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER_UNDERFLOW", 13, 13, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 14, 14, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 15, 15, &umr_bitfield_default },
+	 { "CE_STALLED_ON_TC_WR_CONFIRM", 16, 16, &umr_bitfield_default },
+	 { "CE_STALLED_ON_ATOMIC_RTN_DATA", 17, 17, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_FREE", 18, 18, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_TAGS", 19, 19, &umr_bitfield_default },
+	 { "ATCL1_WAITING_ON_TRANS", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT1[] = {
+	 { "RBIU_TO_DMA_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "RBIU_TO_SEM_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "RBIU_TO_MEMWR_NOT_RDY_TO_RCV", 4, 4, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_CE_BUFFER_FLAG", 10, 10, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_DE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "ME_STALLED_ON_TC_WR_CONFIRM", 12, 12, &umr_bitfield_default },
+	 { "ME_STALLED_ON_ATOMIC_RTN_DATA", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_ON_TC_READ_DATA", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_REG_READ_DATA", 15, 15, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GDS_FREE", 23, 23, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GRBM_FREE", 24, 24, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_VGT_FREE", 25, 25, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_ME_READ", 26, 26, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_DMA_READ", 27, 27, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_APPEND_READ", 28, 28, &umr_bitfield_default },
+	 { "RCIU_HALTED_BY_REG_VIOLATION", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT2[] = {
+	 { "PFP_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "PFP_TO_MEQ_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "PFP_TO_RCIU_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "PFP_TO_VGT_WRITES_PENDING", 4, 4, &umr_bitfield_default },
+	 { "PFP_RCIU_READ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "PFP_WAITING_ON_BUFFER_DATA", 8, 8, &umr_bitfield_default },
+	 { "ME_WAIT_ON_CE_COUNTER", 9, 9, &umr_bitfield_default },
+	 { "ME_WAIT_ON_AVAIL_BUFFER", 10, 10, &umr_bitfield_default },
+	 { "GFX_CNTX_NOT_AVAIL_TO_ME", 11, 11, &umr_bitfield_default },
+	 { "ME_RCIU_NOT_RDY_TO_RCV", 12, 12, &umr_bitfield_default },
+	 { "ME_TO_CONST_NOT_RDY_TO_RCV", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_PFP", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_PARTIAL_FLUSH", 15, 15, &umr_bitfield_default },
+	 { "MEQ_TO_ME_NOT_RDY_TO_RCV", 16, 16, &umr_bitfield_default },
+	 { "STQ_TO_ME_NOT_RDY_TO_RCV", 17, 17, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_STQ", 18, 18, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_TC_WR_CONFIRM", 19, 19, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_ATOMIC_RTN_DATA", 20, 20, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_SC_EOP_DONE", 21, 21, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_WR_CONFIRM", 22, 22, &umr_bitfield_default },
+	 { "STRMO_WR_OF_PRIM_DATA_PENDING", 23, 23, &umr_bitfield_default },
+	 { "PIPE_STATS_WR_DATA_PENDING", 24, 24, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_CS_DONE", 25, 25, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_PS_DONE", 26, 26, &umr_bitfield_default },
+	 { "APPEND_WAIT_ON_WR_CONFIRM", 27, 27, &umr_bitfield_default },
+	 { "APPEND_ACTIVE_PARTITION", 28, 28, &umr_bitfield_default },
+	 { "APPEND_WAITING_TO_SEND_MEMWRITE", 29, 29, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_IDLE_CNTXS", 30, 30, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_ALL_CLEAN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_BUSY_STAT[] = {
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COHER_CNT_NEQ_ZERO", 6, 6, &umr_bitfield_default },
+	 { "PFP_PARSING_PACKETS", 7, 7, &umr_bitfield_default },
+	 { "ME_PARSING_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "RCIU_PFP_BUSY", 9, 9, &umr_bitfield_default },
+	 { "RCIU_ME_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SEM_CMDFIFO_NOT_EMPTY", 12, 12, &umr_bitfield_default },
+	 { "SEM_FAILED_AND_HOLDING", 13, 13, &umr_bitfield_default },
+	 { "SEM_POLLING_FOR_PASS", 14, 14, &umr_bitfield_default },
+	 { "GFX_CONTEXT_BUSY", 15, 15, &umr_bitfield_default },
+	 { "ME_PARSER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "EOP_DONE_BUSY", 18, 18, &umr_bitfield_default },
+	 { "STRM_OUT_BUSY", 19, 19, &umr_bitfield_default },
+	 { "PIPE_STATS_BUSY", 20, 20, &umr_bitfield_default },
+	 { "RCIU_CE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "CE_PARSING_PACKETS", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STAT[] = {
+	 { "ROQ_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DC_BUSY", 13, 13, &umr_bitfield_default },
+	 { "ATCL2IU_BUSY", 14, 14, &umr_bitfield_default },
+	 { "PFP_BUSY", 15, 15, &umr_bitfield_default },
+	 { "MEQ_BUSY", 16, 16, &umr_bitfield_default },
+	 { "ME_BUSY", 17, 17, &umr_bitfield_default },
+	 { "QUERY_BUSY", 18, 18, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 20, 20, &umr_bitfield_default },
+	 { "SURFACE_SYNC_BUSY", 21, 21, &umr_bitfield_default },
+	 { "DMA_BUSY", 22, 22, &umr_bitfield_default },
+	 { "RCIU_BUSY", 23, 23, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 24, 24, &umr_bitfield_default },
+	 { "CPC_CPG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "CE_BUSY", 26, 26, &umr_bitfield_default },
+	 { "TCIU_BUSY", 27, 27, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 28, 28, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 29, 29, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CP_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_HEADER_DUMP[] = {
+	 { "ME_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_HEADER_DUMP[] = {
+	 { "PFP_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+	 { "FREE_COUNT_GDS", 8, 13, &umr_bitfield_default },
+	 { "FREE_COUNT_PFP", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_HEADER_DUMP[] = {
+	 { "CE_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CSF_STAT[] = {
+	 { "BUFFER_SLOTS_ALLOCATED", 0, 3, &umr_bitfield_default },
+	 { "BUFFER_REQUEST_COUNT", 8, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CSF_CNTL[] = {
+	 { "FETCH_BUFFER_DEPTH", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_CNTL[] = {
+	 { "CE_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "PFP_INVALIDATE_ICACHE", 6, 6, &umr_bitfield_default },
+	 { "ME_INVALIDATE_ICACHE", 8, 8, &umr_bitfield_default },
+	 { "CE_PIPE0_RESET", 16, 16, &umr_bitfield_default },
+	 { "PFP_PIPE0_RESET", 18, 18, &umr_bitfield_default },
+	 { "ME_PIPE0_RESET", 20, 20, &umr_bitfield_default },
+	 { "CE_HALT", 24, 24, &umr_bitfield_default },
+	 { "CE_STEP", 25, 25, &umr_bitfield_default },
+	 { "PFP_HALT", 26, 26, &umr_bitfield_default },
+	 { "PFP_STEP", 27, 27, &umr_bitfield_default },
+	 { "ME_HALT", 28, 28, &umr_bitfield_default },
+	 { "ME_STEP", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CNTX_STAT[] = {
+	 { "ACTIVE_HP3D_CONTEXTS", 0, 7, &umr_bitfield_default },
+	 { "CURRENT_HP3D_CONTEXT", 8, 10, &umr_bitfield_default },
+	 { "ACTIVE_GFX_CONTEXTS", 20, 27, &umr_bitfield_default },
+	 { "CURRENT_GFX_CONTEXT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_PREEMPTION[] = {
+	 { "OBSOLETE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_THRESHOLDS[] = {
+	 { "IB1_START", 0, 7, &umr_bitfield_default },
+	 { "IB2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_STQ_THRESHOLD[] = {
+	 { "STQ_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_DELAY[] = {
+	 { "PRE_WRITE_TIMER", 0, 27, &umr_bitfield_default },
+	 { "PRE_WRITE_LIMIT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_CNTL[] = {
+	 { "POLL_FREQUENCY", 0, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ1_THRESHOLDS[] = {
+	 { "RB1_START", 0, 7, &umr_bitfield_default },
+	 { "RB2_START", 8, 15, &umr_bitfield_default },
+	 { "R0_IB1_START", 16, 23, &umr_bitfield_default },
+	 { "R1_IB1_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ2_THRESHOLDS[] = {
+	 { "R2_IB1_START", 0, 7, &umr_bitfield_default },
+	 { "R0_IB2_START", 8, 15, &umr_bitfield_default },
+	 { "R1_IB2_START", 16, 23, &umr_bitfield_default },
+	 { "R2_IB2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_THRESHOLDS[] = {
+	 { "STQ0_START", 0, 7, &umr_bitfield_default },
+	 { "STQ1_START", 8, 15, &umr_bitfield_default },
+	 { "STQ2_START", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_QUEUE_THRESHOLDS[] = {
+	 { "ROQ_IB1_START", 0, 5, &umr_bitfield_default },
+	 { "ROQ_IB2_START", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_THRESHOLDS[] = {
+	 { "MEQ1_START", 0, 7, &umr_bitfield_default },
+	 { "MEQ2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_AVAIL[] = {
+	 { "ROQ_CNT_RING", 0, 10, &umr_bitfield_default },
+	 { "ROQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_AVAIL[] = {
+	 { "STQ_CNT", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ2_AVAIL[] = {
+	 { "ROQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_AVAIL[] = {
+	 { "MEQ_CNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CMD_INDEX[] = {
+	 { "CMD_INDEX", 0, 10, &umr_bitfield_default },
+	 { "CMD_ME_SEL", 12, 13, &umr_bitfield_default },
+	 { "CMD_QUEUE_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CMD_DATA[] = {
+	 { "CMD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_RB_STAT[] = {
+	 { "ROQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_IB1_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_IB2_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_STAT[] = {
+	 { "STQ_RPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_WR_STAT[] = {
+	 { "STQ_WPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_STAT[] = {
+	 { "MEQ_RPTR", 0, 9, &umr_bitfield_default },
+	 { "MEQ_WPTR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CEQ1_AVAIL[] = {
+	 { "CEQ_CNT_RING", 0, 10, &umr_bitfield_default },
+	 { "CEQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CEQ2_AVAIL[] = {
+	 { "CEQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_RB_STAT[] = {
+	 { "CEQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_IB1_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_IB2_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STAT_DEBUG[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ASSERTED", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ASSERTED", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ASSERTED", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ASSERTED", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ASSERTED", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ASSERTED", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG6[] = {
+	 { "debug_BASE", 0, 15, &umr_bitfield_default },
+	 { "debug_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "UNUSED_0", 14, 15, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "UNUSED_1", 26, 26, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "UNUSED_2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VTX_VECT_EJECT_REG[] = {
+	 { "PRIM_COUNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_DATA_FIFO_DEPTH[] = {
+	 { "DMA_DATA_FIFO_DEPTH", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_REQ_FIFO_DEPTH[] = {
+	 { "DMA_REQ_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DRAW_INIT_FIFO_DEPTH[] = {
+	 { "DRAW_INIT_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_LAST_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+	 { "DST_STATE_ID", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_CACHE_INVALIDATION[] = {
+	 { "CACHE_INVALIDATION", 0, 1, &umr_bitfield_default },
+	 { "DIS_INSTANCING_OPT", 4, 4, &umr_bitfield_default },
+	 { "VS_NO_EXTRA_BUFFER", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INVLD_EN", 6, 7, &umr_bitfield_default },
+	 { "USE_GS_DONE", 9, 9, &umr_bitfield_default },
+	 { "DIS_RANGE_FULL_INVLD", 11, 11, &umr_bitfield_default },
+	 { "GS_LATE_ALLOC_EN", 12, 12, &umr_bitfield_default },
+	 { "STREAMOUT_FULL_FLUSH", 13, 13, &umr_bitfield_default },
+	 { "ES_LIMIT", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_RESET_DEBUG[] = {
+	 { "GS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "TESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "WD_DISABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DELAY[] = {
+	 { "SKIP_DELAY", 0, 7, &umr_bitfield_default },
+	 { "SE0_WD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "SE1_WD_DELAY", 11, 13, &umr_bitfield_default },
+	 { "SE2_WD_DELAY", 14, 16, &umr_bitfield_default },
+	 { "SE3_WD_DELAY", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_FIFO_DEPTHS[] = {
+	 { "VS_DEALLOC_TBL_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "RESERVED_0", 7, 7, &umr_bitfield_default },
+	 { "CLIPP_FIFO_DEPTH", 8, 21, &umr_bitfield_default },
+	 { "HSINPUT_FIFO_DEPTH", 22, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERTEX_REUSE[] = {
+	 { "VERT_REUSE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MC_LAT_CNTL[] = {
+	 { "MC_TIME_STAMP_RES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_CNTL_STATUS[] = {
+	 { "IA_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IA_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "IA_DMA_REQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "IA_GRP_BUSY", 3, 3, &umr_bitfield_default },
+	 { "IA_ADC_BUSY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DEBUG_CNTL[] = {
+	 { "VGT_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "VGT_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_DEBUG_CNTL[] = {
+	 { "IA_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "IA_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_CNTL_STATUS[] = {
+	 { "VGT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VGT_OUT_INDX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "VGT_OUT_BUSY", 2, 2, &umr_bitfield_default },
+	 { "VGT_PT_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VGT_TE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGT_VR_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGT_PI_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGT_GS_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGT_HS_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VGT_TE11_BUSY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_DEBUG_CNTL[] = {
+	 { "WD_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "WD_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_CNTL_STATUS[] = {
+	 { "WD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "WD_SPL_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WD_SPL_DI_BUSY", 2, 2, &umr_bitfield_default },
+	 { "WD_ADC_BUSY", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_PRIM_CONFIG[] = {
+	 { "INACTIVE_IA", 16, 17, &umr_bitfield_default },
+	 { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_PRIM_CONFIG[] = {
+	 { "INACTIVE_IA", 16, 17, &umr_bitfield_default },
+	 { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_QOS[] = {
+	 { "DRAW_STALL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_SYS_CONFIG[] = {
+	 { "DUAL_CORE_EN", 0, 0, &umr_bitfield_default },
+	 { "MAX_LS_HS_THDGRP", 1, 6, &umr_bitfield_default },
+	 { "ADC_EVENT_FILTER_DISABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_PIPE_CONTROL[] = {
+	 { "HYSTERESIS_CNT", 0, 12, &umr_bitfield_default },
+	 { "RESERVED", 13, 15, &umr_bitfield_default },
+	 { "CONTEXT_SUSPEND_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_SHADER_ARRAY_CONFIG[] = {
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SHADER_ARRAY_CONFIG[] = {
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_CONTROL[] = {
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "IA_SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_LS_HS_CONFIG[] = {
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_DEBUG_CNTL[] = {
+	 { "SU_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_CNTL_STATUS[] = {
+	 { "CL_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_ENHANCE[] = {
+	 { "CLIP_VTX_REORDER_ENA", 0, 0, &umr_bitfield_default },
+	 { "NUM_CLIP_SEQ", 1, 2, &umr_bitfield_default },
+	 { "CLIPPED_PRIM_SEQ_STALL", 3, 3, &umr_bitfield_default },
+	 { "VE_NAN_PROC_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "XTRA_DEBUG_REG_SEL", 5, 5, &umr_bitfield_default },
+	 { "ECO_SPARE3", 28, 28, &umr_bitfield_default },
+	 { "ECO_SPARE2", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_RESET_DEBUG[] = {
+	 { "CL_TRIV_DISC_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_CNTL_STATUS[] = {
+	 { "SU_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FIFO_DEPTH_CNTL[] = {
+	 { "DEPTH", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FORCE_EOV_MAX_CNTS[] = {
+	 { "FORCE_EOV_MAX_CLK_CNT", 0, 15, &umr_bitfield_default },
+	 { "FORCE_EOV_MAX_REZ_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FIFO_SIZE[] = {
+	 { "SC_FRONTEND_PRIM_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_BACKEND_PRIM_FIFO_SIZE", 6, 14, &umr_bitfield_default },
+	 { "SC_HIZ_TILE_FIFO_SIZE", 15, 20, &umr_bitfield_default },
+	 { "SC_EARLYZ_TILE_FIFO_SIZE", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_IF_FIFO_SIZE[] = {
+	 { "SC_DB_TILE_IF_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_DB_QUAD_IF_FIFO_SIZE", 6, 11, &umr_bitfield_default },
+	 { "SC_SPI_IF_FIFO_SIZE", 12, 17, &umr_bitfield_default },
+	 { "SC_BCI_IF_FIFO_SIZE", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DEBUG_CNTL[] = {
+	 { "SC_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_ENHANCE[] = {
+	 { "ENABLE_PA_SC_OUT_OF_ORDER", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_SC_DB_TILE_FIX", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_AA_MASK_FULL_FIX", 2, 2, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOCATIONS", 3, 3, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_SCISSOR_FIX", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_PW_BUBBLE_COLLAPSE", 6, 7, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PACKER", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_DUALGRAD_PERF_OPTIMIZATION", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_PRIM", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_SUPERTILE", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_TILE", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_PA_SC_GUIDANCE", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_MULTICYCLE_BUBBLE_FREEZE", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_POLY_MODE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS", 23, 23, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO", 25, 25, &umr_bitfield_default },
+	 { "OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT", 26, 26, &umr_bitfield_default },
+	 { "OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_EOP_LINE_STIPPLE_RESET", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_VPZ_EOP_LINE_STIPPLE_RESET", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG7[] = {
+	 { "debug_tfmmFifoEmpty", 0, 0, &umr_bitfield_default },
+	 { "debug_tfmmFifoFull", 1, 1, &umr_bitfield_default },
+	 { "hs_pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "hs_pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "hs_pipe1_rtr", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 15, &umr_bitfield_default },
+	 { "TF_addr", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CONFIG[] = {
+	 { "UNUSED", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_EN", 8, 8, &umr_bitfield_default },
+	 { "DEBUG_SINGLE_MEMOP", 9, 9, &umr_bitfield_default },
+	 { "DEBUG_ONE_INST_CLAUSE", 10, 10, &umr_bitfield_default },
+	 { "EARLY_TA_DONE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "DUA_FLAT_LOCK_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "DUA_LDS_BYPASS_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DUA_FLAT_LDS_PINGPONG_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_VMEM_SOFT_CLAUSE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_SMEM_SOFT_CLAUSE", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_HIPRIO_ON_EXP_RDY_VS", 18, 18, &umr_bitfield_default },
+	 { "PRIO_VAL_ON_EXP_RDY_VS", 19, 20, &umr_bitfield_default },
+	 { "REPLAY_SLEEP_CNT", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_CONFIG[] = {
+	 { "INST_CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DATA_CACHE_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MISS_FIFO_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "HIT_FIFO_DEPTH", 6, 6, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_MISS", 7, 7, &umr_bitfield_default },
+	 { "FORCE_IN_ORDER", 8, 8, &umr_bitfield_default },
+	 { "IDENTITY_HASH_BANK", 9, 9, &umr_bitfield_default },
+	 { "IDENTITY_HASH_SET", 10, 10, &umr_bitfield_default },
+	 { "PER_VMID_INV_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "EVICT_LRU", 12, 13, &umr_bitfield_default },
+	 { "FORCE_2_BANK", 14, 14, &umr_bitfield_default },
+	 { "FORCE_1_BANK", 15, 15, &umr_bitfield_default },
+	 { "LS_DISABLE_CLOCKS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_RANDOM_WAVE_PRI[] = {
+	 { "RET", 0, 6, &umr_bitfield_default },
+	 { "RUI", 7, 9, &umr_bitfield_default },
+	 { "RNG", 10, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_REG_CREDITS[] = {
+	 { "SRBM_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "CMD_CREDITS", 8, 11, &umr_bitfield_default },
+	 { "REG_BUSY", 28, 28, &umr_bitfield_default },
+	 { "SRBM_OVERFLOW", 29, 29, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 30, 30, &umr_bitfield_default },
+	 { "CMD_OVERFLOW", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FIFO_SIZES[] = {
+	 { "INTERRUPT_FIFO_SIZE", 0, 3, &umr_bitfield_default },
+	 { "TTRACE_FIFO_SIZE", 8, 11, &umr_bitfield_default },
+	 { "EXPORT_BUF_SIZE", 16, 17, &umr_bitfield_default },
+	 { "VMEM_DATA_FIFO_SIZE", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DSM_CNTL[] = {
+	 { "WAVEFRONT_STALL_0", 0, 0, &umr_bitfield_default },
+	 { "WAVEFRONT_STALL_1", 1, 1, &umr_bitfield_default },
+	 { "SPI_BACKPRESSURE_0", 2, 2, &umr_bitfield_default },
+	 { "SPI_BACKPRESSURE_1", 3, 3, &umr_bitfield_default },
+	 { "SEL_DSM_SGPR_IRRITATOR_DATA0", 8, 8, &umr_bitfield_default },
+	 { "SEL_DSM_SGPR_IRRITATOR_DATA1", 9, 9, &umr_bitfield_default },
+	 { "SGPR_ENABLE_SINGLE_WRITE", 10, 10, &umr_bitfield_default },
+	 { "SEL_DSM_LDS_IRRITATOR_DATA0", 16, 16, &umr_bitfield_default },
+	 { "SEL_DSM_LDS_IRRITATOR_DATA1", 17, 17, &umr_bitfield_default },
+	 { "LDS_ENABLE_SINGLE_WRITE01", 18, 18, &umr_bitfield_default },
+	 { "SEL_DSM_LDS_IRRITATOR_DATA2", 19, 19, &umr_bitfield_default },
+	 { "SEL_DSM_LDS_IRRITATOR_DATA3", 20, 20, &umr_bitfield_default },
+	 { "LDS_ENABLE_SINGLE_WRITE23", 21, 21, &umr_bitfield_default },
+	 { "SEL_DSM_SP_IRRITATOR_DATA0", 24, 24, &umr_bitfield_default },
+	 { "SEL_DSM_SP_IRRITATOR_DATA1", 25, 25, &umr_bitfield_default },
+	 { "SP_ENABLE_SINGLE_WRITE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUSER_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "INTERRUPT_MSG_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH0", 4, 15, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH1", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_BASES[] = {
+	 { "PRIVATE_BASE", 0, 15, &umr_bitfield_default },
+	 { "SHARED_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_APE1_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_APE1_LIMIT[] = {
+	 { "LIMIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_CONFIG[] = {
+	 { "ADDRESS_MODE", 0, 1, &umr_bitfield_default },
+	 { "PRIVATE_ATC", 2, 2, &umr_bitfield_default },
+	 { "ALIGNMENT_MODE", 3, 4, &umr_bitfield_default },
+	 { "DEFAULT_MTYPE", 5, 7, &umr_bitfield_default },
+	 { "APE1_MTYPE", 8, 10, &umr_bitfield_default },
+	 { "APE1_ATC", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_DSM_CNTL[] = {
+	 { "SEL_DATA_ICACHE_BANKA", 0, 1, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_BANKA", 2, 2, &umr_bitfield_default },
+	 { "SEL_DATA_ICACHE_BANKB", 3, 4, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_BANKB", 5, 5, &umr_bitfield_default },
+	 { "SEL_DATA_ICACHE_BANKC", 6, 7, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_BANKC", 8, 8, &umr_bitfield_default },
+	 { "SEL_DATA_ICACHE_BANKD", 9, 10, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_BANKD", 11, 11, &umr_bitfield_default },
+	 { "SEL_DATA_ICACHE_GATCL1", 12, 13, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_GATCL1", 14, 14, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_BANKA", 15, 16, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_BANKA", 17, 17, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_BANKB", 18, 19, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_BANKB", 20, 20, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_BANKC", 21, 22, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_BANKC", 23, 23, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_BANKD", 24, 25, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_BANKD", 26, 26, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_GATCL1", 27, 28, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_GATCL1", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL2[] = {
+	 { "FIFO_LEVEL_GFX0", 0, 7, &umr_bitfield_default },
+	 { "FIFO_LEVEL_GFX1", 8, 15, &umr_bitfield_default },
+	 { "FIFO_LEVEL_IMMED", 16, 23, &umr_bitfield_default },
+	 { "FIFO_LEVEL_HOST", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL3[] = {
+	 { "FIFO_LEVEL_HOST_CMD", 0, 3, &umr_bitfield_default },
+	 { "FIFO_LEVEL_HOST_REG", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_SHADER_RATE_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SHADER_RATE_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_INTERRUPT_AUTO_MASK[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_INTERRUPT_MSG_CTRL[] = {
+	 { "STALL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_REG_TIMESTAMP[] = {
+	 { "TIMESTAMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CMD_TIMESTAMP[] = {
+	 { "TIMESTAMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IND_INDEX[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "THREAD_ID", 6, 11, &umr_bitfield_default },
+	 { "AUTO_INCR", 12, 12, &umr_bitfield_default },
+	 { "FORCE_READ", 13, 13, &umr_bitfield_default },
+	 { "READ_TIMEOUT", 14, 14, &umr_bitfield_default },
+	 { "UNINDEXED", 15, 15, &umr_bitfield_default },
+	 { "INDEX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CMD[] = {
+	 { "CMD", 0, 2, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "CHECK_VMID", 7, 7, &umr_bitfield_default },
+	 { "DATA", 8, 10, &umr_bitfield_default },
+	 { "WAVE_ID", 16, 19, &umr_bitfield_default },
+	 { "SIMD_ID", 20, 21, &umr_bitfield_default },
+	 { "QUEUE_ID", 24, 26, &umr_bitfield_default },
+	 { "VM_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TIME_HI[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TIME_LO[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_VOP3_0_SDST_ENC[] = {
+	 { "VDST", 0, 7, &umr_bitfield_default },
+	 { "SDST", 8, 14, &umr_bitfield_default },
+	 { "CLAMP", 15, 15, &umr_bitfield_default },
+	 { "OP", 16, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_VOP_SDWA[] = {
+	 { "SRC0", 0, 7, &umr_bitfield_default },
+	 { "DST_SEL", 8, 10, &umr_bitfield_default },
+	 { "DST_UNUSED", 11, 12, &umr_bitfield_default },
+	 { "CLAMP", 13, 13, &umr_bitfield_default },
+	 { "SRC0_SEL", 16, 18, &umr_bitfield_default },
+	 { "SRC0_SEXT", 19, 19, &umr_bitfield_default },
+	 { "SRC0_NEG", 20, 20, &umr_bitfield_default },
+	 { "SRC0_ABS", 21, 21, &umr_bitfield_default },
+	 { "SRC1_SEL", 24, 26, &umr_bitfield_default },
+	 { "SRC1_SEXT", 27, 27, &umr_bitfield_default },
+	 { "SRC1_NEG", 28, 28, &umr_bitfield_default },
+	 { "SRC1_ABS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_MTBUF_1[] = {
+	 { "VADDR", 0, 7, &umr_bitfield_default },
+	 { "VDATA", 8, 15, &umr_bitfield_default },
+	 { "SRSRC", 16, 20, &umr_bitfield_default },
+	 { "SLC", 22, 22, &umr_bitfield_default },
+	 { "TFE", 23, 23, &umr_bitfield_default },
+	 { "SOFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_SMEM_1[] = {
+	 { "OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EXP_1[] = {
+	 { "VSRC0", 0, 7, &umr_bitfield_default },
+	 { "VSRC1", 8, 15, &umr_bitfield_default },
+	 { "VSRC2", 16, 23, &umr_bitfield_default },
+	 { "VSRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_SOP2[] = {
+	 { "SSRC0", 0, 7, &umr_bitfield_default },
+	 { "SSRC1", 8, 15, &umr_bitfield_default },
+	 { "SDST", 16, 22, &umr_bitfield_default },
+	 { "OP", 23, 29, &umr_bitfield_default },
+	 { "ENCODING", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_CNTR[] = {
+	 { "CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_CTR_CTRL[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "LOAD", 1, 1, &umr_bitfield_default },
+	 { "CLEAR", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_ALU_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_TEX_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_ALU_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_TEX_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_EDC_CNT[] = {
+	 { "INST_SEC", 0, 7, &umr_bitfield_default },
+	 { "INST_DED", 8, 15, &umr_bitfield_default },
+	 { "DATA_SEC", 16, 23, &umr_bitfield_default },
+	 { "DATA_DED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EDC_SEC_CNT[] = {
+	 { "LDS_SEC", 0, 7, &umr_bitfield_default },
+	 { "SGPR_SEC", 8, 15, &umr_bitfield_default },
+	 { "VGPR_SEC", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EDC_DED_CNT[] = {
+	 { "LDS_DED", 0, 7, &umr_bitfield_default },
+	 { "SGPR_DED", 8, 15, &umr_bitfield_default },
+	 { "VGPR_DED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EDC_INFO[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "SOURCE", 6, 8, &umr_bitfield_default },
+	 { "VM_ID", 9, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "WAVE_ID", 10, 13, &umr_bitfield_default },
+	 { "SIMD_ID", 14, 15, &umr_bitfield_default },
+	 { "DATA_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID", 5, 8, &umr_bitfield_default },
+	 { "SIMD_ID", 9, 10, &umr_bitfield_default },
+	 { "PC_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "PIPE_ID", 5, 6, &umr_bitfield_default },
+	 { "ME_ID", 7, 8, &umr_bitfield_default },
+	 { "REG_ADDR", 9, 15, &umr_bitfield_default },
+	 { "DATA_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "CNTR_BANK", 10, 11, &umr_bitfield_default },
+	 { "CNTR0", 12, 24, &umr_bitfield_default },
+	 { "CNTR1_LO", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_WAVE_START[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "WAVE_ID", 10, 13, &umr_bitfield_default },
+	 { "SIMD_ID", 14, 15, &umr_bitfield_default },
+	 { "DISPATCHER", 16, 20, &umr_bitfield_default },
+	 { "VS_NO_ALLOC_OR_GROUPED", 21, 21, &umr_bitfield_default },
+	 { "COUNT", 22, 28, &umr_bitfield_default },
+	 { "TG_ID", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_EVENT[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "STAGE", 6, 8, &umr_bitfield_default },
+	 { "EVENT_TYPE", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID", 5, 8, &umr_bitfield_default },
+	 { "SIMD_ID", 9, 10, &umr_bitfield_default },
+	 { "INST_TYPE", 11, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_CMN[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[] = {
+	 { "DATA_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[] = {
+	 { "TIME_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[] = {
+	 { "PC_HI", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[] = {
+	 { "CNTR1_HI", 0, 5, &umr_bitfield_default },
+	 { "CNTR2", 6, 18, &umr_bitfield_default },
+	 { "CNTR3", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_WREXEC_EXEC_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_GATCL1_CNTL[] = {
+	 { "RESERVED", 0, 17, &umr_bitfield_default },
+	 { "DCACHE_INVALIDATE_ALL_VMID", 18, 18, &umr_bitfield_default },
+	 { "DCACHE_FORCE_MISS", 19, 19, &umr_bitfield_default },
+	 { "DCACHE_FORCE_IN_ORDER", 20, 20, &umr_bitfield_default },
+	 { "DCACHE_REDUCE_FIFO_DEPTH_BY_2", 21, 22, &umr_bitfield_default },
+	 { "DCACHE_REDUCE_CACHE_SIZE_BY_2", 23, 24, &umr_bitfield_default },
+	 { "ICACHE_INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default },
+	 { "ICACHE_FORCE_MISS", 26, 26, &umr_bitfield_default },
+	 { "ICACHE_FORCE_IN_ORDER", 27, 27, &umr_bitfield_default },
+	 { "ICACHE_REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default },
+	 { "ICACHE_REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_ATC_EDC_GATCL1_CNT[] = {
+	 { "ICACHE_DATA_SEC", 0, 7, &umr_bitfield_default },
+	 { "DCACHE_DATA_SEC", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 15, &umr_bitfield_default },
+	 { "STRIDE", 16, 29, &umr_bitfield_default },
+	 { "CACHE_SWIZZLE", 30, 30, &umr_bitfield_default },
+	 { "SWIZZLE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD2[] = {
+	 { "NUM_RECORDS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD3[] = {
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "NUM_FORMAT", 12, 14, &umr_bitfield_default },
+	 { "DATA_FORMAT", 15, 18, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 19, 20, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 21, 22, &umr_bitfield_default },
+	 { "ADD_TID_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "ATC", 24, 24, &umr_bitfield_default },
+	 { "HASH_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "HEAP", 26, 26, &umr_bitfield_default },
+	 { "MTYPE", 27, 29, &umr_bitfield_default },
+	 { "TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 7, &umr_bitfield_default },
+	 { "MIN_LOD", 8, 19, &umr_bitfield_default },
+	 { "DATA_FORMAT", 20, 25, &umr_bitfield_default },
+	 { "NUM_FORMAT", 26, 29, &umr_bitfield_default },
+	 { "MTYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD2[] = {
+	 { "WIDTH", 0, 13, &umr_bitfield_default },
+	 { "HEIGHT", 14, 27, &umr_bitfield_default },
+	 { "PERF_MOD", 28, 30, &umr_bitfield_default },
+	 { "INTERLACED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD3[] = {
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "BASE_LEVEL", 12, 15, &umr_bitfield_default },
+	 { "LAST_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "TILING_INDEX", 20, 24, &umr_bitfield_default },
+	 { "POW2_PAD", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 26, 26, &umr_bitfield_default },
+	 { "ATC", 27, 27, &umr_bitfield_default },
+	 { "TYPE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD4[] = {
+	 { "DEPTH", 0, 12, &umr_bitfield_default },
+	 { "PITCH", 13, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD5[] = {
+	 { "BASE_ARRAY", 0, 12, &umr_bitfield_default },
+	 { "LAST_ARRAY", 13, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD6[] = {
+	 { "MIN_LOD_WARN", 0, 11, &umr_bitfield_default },
+	 { "COUNTER_BANK_ID", 12, 19, &umr_bitfield_default },
+	 { "LOD_HDW_CNT_EN", 20, 20, &umr_bitfield_default },
+	 { "COMPRESSION_EN", 21, 21, &umr_bitfield_default },
+	 { "ALPHA_IS_ON_MSB", 22, 22, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 23, 23, &umr_bitfield_default },
+	 { "LOST_ALPHA_BITS", 24, 27, &umr_bitfield_default },
+	 { "LOST_COLOR_BITS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD7[] = {
+	 { "META_DATA_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD0[] = {
+	 { "CLAMP_X", 0, 2, &umr_bitfield_default },
+	 { "CLAMP_Y", 3, 5, &umr_bitfield_default },
+	 { "CLAMP_Z", 6, 8, &umr_bitfield_default },
+	 { "MAX_ANISO_RATIO", 9, 11, &umr_bitfield_default },
+	 { "DEPTH_COMPARE_FUNC", 12, 14, &umr_bitfield_default },
+	 { "FORCE_UNNORMALIZED", 15, 15, &umr_bitfield_default },
+	 { "ANISO_THRESHOLD", 16, 18, &umr_bitfield_default },
+	 { "MC_COORD_TRUNC", 19, 19, &umr_bitfield_default },
+	 { "FORCE_DEGAMMA", 20, 20, &umr_bitfield_default },
+	 { "ANISO_BIAS", 21, 26, &umr_bitfield_default },
+	 { "TRUNC_COORD", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_CUBE_WRAP", 28, 28, &umr_bitfield_default },
+	 { "FILTER_MODE", 29, 30, &umr_bitfield_default },
+	 { "COMPAT_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD1[] = {
+	 { "MIN_LOD", 0, 11, &umr_bitfield_default },
+	 { "MAX_LOD", 12, 23, &umr_bitfield_default },
+	 { "PERF_MIP", 24, 27, &umr_bitfield_default },
+	 { "PERF_Z", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD2[] = {
+	 { "LOD_BIAS", 0, 13, &umr_bitfield_default },
+	 { "LOD_BIAS_SEC", 14, 19, &umr_bitfield_default },
+	 { "XY_MAG_FILTER", 20, 21, &umr_bitfield_default },
+	 { "XY_MIN_FILTER", 22, 23, &umr_bitfield_default },
+	 { "Z_FILTER", 24, 25, &umr_bitfield_default },
+	 { "MIP_FILTER", 26, 27, &umr_bitfield_default },
+	 { "MIP_POINT_PRECLAMP", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_LSB_CEIL", 29, 29, &umr_bitfield_default },
+	 { "FILTER_PREC_FIX", 30, 30, &umr_bitfield_default },
+	 { "ANISO_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD3[] = {
+	 { "BORDER_COLOR_PTR", 0, 11, &umr_bitfield_default },
+	 { "BORDER_COLOR_TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FLAT_SCRATCH_WORD0[] = {
+	 { "SIZE", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FLAT_SCRATCH_WORD1[] = {
+	 { "OFFSET", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_M0_GPR_IDX_WORD[] = {
+	 { "INDEX", 0, 7, &umr_bitfield_default },
+	 { "VSRC0_REL", 12, 12, &umr_bitfield_default },
+	 { "VSRC1_REL", 13, 13, &umr_bitfield_default },
+	 { "VSRC2_REL", 14, 14, &umr_bitfield_default },
+	 { "VDST_REL", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG26[] = {
+	 { "cm_state0", 0, 1, &umr_bitfield_default },
+	 { "cm_state1", 2, 3, &umr_bitfield_default },
+	 { "cm_state2", 4, 5, &umr_bitfield_default },
+	 { "cm_state3", 6, 7, &umr_bitfield_default },
+	 { "cm_state4", 8, 9, &umr_bitfield_default },
+	 { "cm_state5", 10, 11, &umr_bitfield_default },
+	 { "cm_state6", 12, 13, &umr_bitfield_default },
+	 { "cm_state7", 14, 15, &umr_bitfield_default },
+	 { "cm_state8", 16, 17, &umr_bitfield_default },
+	 { "cm_state9", 18, 19, &umr_bitfield_default },
+	 { "cm_state10", 20, 21, &umr_bitfield_default },
+	 { "cm_state11", 22, 23, &umr_bitfield_default },
+	 { "cm_state12", 24, 25, &umr_bitfield_default },
+	 { "cm_state13", 26, 27, &umr_bitfield_default },
+	 { "cm_state14", 28, 29, &umr_bitfield_default },
+	 { "cm_state15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY[] = {
+	 { "POS_FREE_OR_VALIDS", 0, 0, &umr_bitfield_default },
+	 { "POS_REQUESTER_BUSY", 1, 1, &umr_bitfield_default },
+	 { "PA_SX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "POS_SCBD_BUSY", 3, 3, &umr_bitfield_default },
+	 { "POS_BANK3VAL3_BUSY", 4, 4, &umr_bitfield_default },
+	 { "POS_BANK3VAL2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "POS_BANK3VAL1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "POS_BANK3VAL0_BUSY", 7, 7, &umr_bitfield_default },
+	 { "POS_BANK2VAL3_BUSY", 8, 8, &umr_bitfield_default },
+	 { "POS_BANK2VAL2_BUSY", 9, 9, &umr_bitfield_default },
+	 { "POS_BANK2VAL1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "POS_BANK2VAL0_BUSY", 11, 11, &umr_bitfield_default },
+	 { "POS_BANK1VAL3_BUSY", 12, 12, &umr_bitfield_default },
+	 { "POS_BANK1VAL2_BUSY", 13, 13, &umr_bitfield_default },
+	 { "POS_BANK1VAL1_BUSY", 14, 14, &umr_bitfield_default },
+	 { "POS_BANK1VAL0_BUSY", 15, 15, &umr_bitfield_default },
+	 { "POS_BANK0VAL3_BUSY", 16, 16, &umr_bitfield_default },
+	 { "POS_BANK0VAL2_BUSY", 17, 17, &umr_bitfield_default },
+	 { "POS_BANK0VAL1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "POS_BANK0VAL0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "POS_INMUX_VALID", 20, 20, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ3", 21, 21, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ2", 22, 22, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ1", 23, 23, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ3", 24, 24, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ2", 25, 25, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ1", 26, 26, &umr_bitfield_default },
+	 { "PCCMD_VALID", 27, 27, &umr_bitfield_default },
+	 { "VDATA1_VALID", 28, 28, &umr_bitfield_default },
+	 { "VDATA0_VALID", 29, 29, &umr_bitfield_default },
+	 { "CMD_BUSYORVAL", 30, 30, &umr_bitfield_default },
+	 { "ADDR_BUSYORVAL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_2[] = {
+	 { "COL_SCBD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_REQ3_FREECNT_NE0", 1, 1, &umr_bitfield_default },
+	 { "COL_REQ3_IDLE", 2, 2, &umr_bitfield_default },
+	 { "COL_REQ3_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_REQ2_FREECNT_NE0", 4, 4, &umr_bitfield_default },
+	 { "COL_REQ2_IDLE", 5, 5, &umr_bitfield_default },
+	 { "COL_REQ2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_REQ1_FREECNT_NE0", 7, 7, &umr_bitfield_default },
+	 { "COL_REQ1_IDLE", 8, 8, &umr_bitfield_default },
+	 { "COL_REQ1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_REQ0_FREECNT_NE0", 10, 10, &umr_bitfield_default },
+	 { "COL_REQ0_IDLE", 11, 11, &umr_bitfield_default },
+	 { "COL_REQ0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_DBIF3_SENDFREE_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_DBIF3_FIFO_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_DBIF3_READ_VALID", 15, 15, &umr_bitfield_default },
+	 { "COL_DBIF2_SENDFREE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_DBIF2_FIFO_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_DBIF2_READ_VALID", 18, 18, &umr_bitfield_default },
+	 { "COL_DBIF1_SENDFREE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_DBIF1_FIFO_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_DBIF1_READ_VALID", 21, 21, &umr_bitfield_default },
+	 { "COL_DBIF0_SENDFREE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_DBIF0_FIFO_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_DBIF0_READ_VALID", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_3[] = {
+	 { "COL_BUFF3_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_4[] = {
+	 { "COL_BUFF1_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "RESERVED", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_1[] = {
+	 { "SX_DB_QUAD_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "DEBUG_DATA", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_START_PHASE[] = {
+	 { "VGPR_START_PHASE", 0, 1, &umr_bitfield_default },
+	 { "SGPR_START_PHASE", 2, 3, &umr_bitfield_default },
+	 { "WAVE_START_PHASE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GFX_CNTL[] = {
+	 { "RESET_COUNTS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL[] = {
+	 { "GPR_WRITE_PRIORITY", 0, 20, &umr_bitfield_default },
+	 { "EXP_PRIORITY_ORDER", 21, 23, &umr_bitfield_default },
+	 { "ENABLE_SQG_TOP_EVENTS", 24, 24, &umr_bitfield_default },
+	 { "ENABLE_SQG_BOP_EVENTS", 25, 25, &umr_bitfield_default },
+	 { "RSRC_MGMT_RESET", 26, 26, &umr_bitfield_default },
+	 { "TTRACE_STALL_ALL", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_CNTL[] = {
+	 { "DEBUG_GRBM_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_THREAD_TYPE_SEL", 1, 3, &umr_bitfield_default },
+	 { "DEBUG_GROUP_SEL", 4, 9, &umr_bitfield_default },
+	 { "DEBUG_SIMD_SEL", 10, 15, &umr_bitfield_default },
+	 { "DEBUG_SH_SEL", 16, 16, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_0", 17, 17, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_1", 18, 18, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_2", 19, 19, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_3", 20, 20, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_4", 21, 21, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_5", 22, 22, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_6", 23, 23, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_7", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_PIPE_SEL", 25, 27, &umr_bitfield_default },
+	 { "DEBUG_REG_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DSM_CNTL[] = {
+	 { "Sel_DSM_SPI_Irritator_data0", 0, 0, &umr_bitfield_default },
+	 { "Sel_DSM_SPI_Irritator_data1", 1, 1, &umr_bitfield_default },
+	 { "SPI_Enable_Single_Write", 2, 2, &umr_bitfield_default },
+	 { "UNUSED", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_EDC_CNT[] = {
+	 { "SED", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL_1[] = {
+	 { "VTX_DONE_DELAY", 0, 3, &umr_bitfield_default },
+	 { "INTERP_ONE_PRIM_PER_ROW", 4, 4, &umr_bitfield_default },
+	 { "PC_LIMIT_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "PC_LIMIT_STRICT", 7, 7, &umr_bitfield_default },
+	 { "CRC_SIMD_ID_WADDR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_MODE", 9, 9, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_CNT", 10, 13, &umr_bitfield_default },
+	 { "PC_LIMIT_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_BUSY[] = {
+	 { "LS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "HS_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ES_BUSY", 2, 2, &umr_bitfield_default },
+	 { "GS_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "PS0_BUSY", 5, 5, &umr_bitfield_default },
+	 { "PS1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CSG_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CS0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "CS1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "CS2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "CS3_BUSY", 11, 11, &umr_bitfield_default },
+	 { "CS4_BUSY", 12, 12, &umr_bitfield_default },
+	 { "CS5_BUSY", 13, 13, &umr_bitfield_default },
+	 { "CS6_BUSY", 14, 14, &umr_bitfield_default },
+	 { "CS7_BUSY", 15, 15, &umr_bitfield_default },
+	 { "LDS_WR_CTL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "LDS_WR_CTL1_BUSY", 17, 17, &umr_bitfield_default },
+	 { "RSRC_ALLOC0_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RSRC_ALLOC1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "PC_DEALLOC_BUSY", 20, 20, &umr_bitfield_default },
+	 { "EVENT_CLCTR_BUSY", 21, 21, &umr_bitfield_default },
+	 { "GRBM_BUSY", 22, 22, &umr_bitfield_default },
+	 { "SPIS_BUSY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL_2[] = {
+	 { "CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD", 0, 3, &umr_bitfield_default },
+	 { "CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_CNTL[] = {
+	 { "SAMPLE_PERIOD", 0, 3, &umr_bitfield_default },
+	 { "EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_0[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_1[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_2[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_3[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_4[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_5[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_6[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_7[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_8[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_9[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_0[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_1[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_2[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_3[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_4[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_5[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_6[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_7[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_8[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_9[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_10[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_11[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_12[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_13[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_14[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_15[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_16[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_17[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_18[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_19[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_20[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_DEBUG[] = {
+	 { "START_VALUE", 0, 30, &umr_bitfield_default },
+	 { "OVERRIDE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SLAVE_DEBUG_BUSY[] = {
+	 { "LS_VTX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "HS_VTX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ES_VTX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "GS_VTX_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VS_VTX_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGPR_WC00_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGPR_WC01_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGPR_WC10_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGPR_WC11_BUSY", 8, 8, &umr_bitfield_default },
+	 { "SGPR_WC00_BUSY", 9, 9, &umr_bitfield_default },
+	 { "SGPR_WC01_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SGPR_WC02_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SGPR_WC03_BUSY", 12, 12, &umr_bitfield_default },
+	 { "SGPR_WC10_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SGPR_WC11_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SGPR_WC12_BUSY", 15, 15, &umr_bitfield_default },
+	 { "SGPR_WC13_BUSY", 16, 16, &umr_bitfield_default },
+	 { "WAVEBUFFER0_BUSY", 17, 17, &umr_bitfield_default },
+	 { "WAVEBUFFER1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "WAVE_WC0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "WAVE_WC1_BUSY", 20, 20, &umr_bitfield_default },
+	 { "EVENT_CNTL_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SAVE_CTX_BUSY", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_CTR_CTRL[] = {
+	 { "LOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_DATA_REG[] = {
+	 { "CNT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PG_ENABLE_STATIC_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDS_CREDITS[] = {
+	 { "DS_DATA_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "DS_CMD_CREDITS", 8, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SX_EXPORT_BUFFER_SIZES[] = {
+	 { "COLOR_BUFFER_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_BUFFER_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SX_SCOREBOARD_BUFFER_SIZES[] = {
+	 { "COLOR_SCOREBOARD_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_SCOREBOARD_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_STATUS[] = {
+	 { "ACTIVE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_0[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_1[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_2[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_3[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_4[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_5[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_6[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_7[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBCI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_GPR_MIN[] = {
+	 { "VGPR_MIN", 0, 5, &umr_bitfield_default },
+	 { "SGPR_MIN", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_GPR_MIN[] = {
+	 { "VGPR_MIN", 0, 5, &umr_bitfield_default },
+	 { "SGPR_MIN", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_CNTL[] = {
+	 { "SYNC_PHASE_SH", 0, 1, &umr_bitfield_default },
+	 { "SYNC_PHASE_VC_SMX", 4, 5, &umr_bitfield_default },
+	 { "PAD_STALL_EN", 8, 8, &umr_bitfield_default },
+	 { "EXTEND_LDS_STALL", 9, 10, &umr_bitfield_default },
+	 { "LDS_STALL_PHASE_ADJUST", 11, 12, &umr_bitfield_default },
+	 { "PRECISION_COMPATIBILITY", 15, 15, &umr_bitfield_default },
+	 { "GATHER4_FLOAT_MODE", 16, 16, &umr_bitfield_default },
+	 { "LD_FLOAT_MODE", 18, 18, &umr_bitfield_default },
+	 { "GATHER4_DX9_MODE", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_POWER_THROTTLE", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_ROUND_TO_ZERO", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_STATUS[] = {
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DSM_CNTL[] = {
+	 { "FORCE_SEDB_0", 0, 0, &umr_bitfield_default },
+	 { "FORCE_SEDB_1", 1, 1, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_SEDB", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CNTL[] = {
+	 { "TC_DATA_CREDIT", 13, 15, &umr_bitfield_default },
+	 { "ALIGNER_CREDIT", 16, 20, &umr_bitfield_default },
+	 { "TD_FIFO_CREDIT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CNTL_AUX[] = {
+	 { "SCOAL_DSWIZZLE_N", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 3, &umr_bitfield_default },
+	 { "ANISO_WEIGHT_MODE", 16, 16, &umr_bitfield_default },
+	 { "ANISO_RATIO_LUT", 17, 17, &umr_bitfield_default },
+	 { "ANISO_TAP", 18, 18, &umr_bitfield_default },
+	 { "ANISO_MIP_ADJ_MODE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_RESERVED_010C[] = {
+	 { "Unused", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_STATUS[] = {
+	 { "FG_PFIFO_EMPTYB", 12, 12, &umr_bitfield_default },
+	 { "FG_LFIFO_EMPTYB", 13, 13, &umr_bitfield_default },
+	 { "FG_SFIFO_EMPTYB", 14, 14, &umr_bitfield_default },
+	 { "FL_PFIFO_EMPTYB", 16, 16, &umr_bitfield_default },
+	 { "FL_LFIFO_EMPTYB", 17, 17, &umr_bitfield_default },
+	 { "FL_SFIFO_EMPTYB", 18, 18, &umr_bitfield_default },
+	 { "FA_PFIFO_EMPTYB", 20, 20, &umr_bitfield_default },
+	 { "FA_LFIFO_EMPTYB", 21, 21, &umr_bitfield_default },
+	 { "FA_SFIFO_EMPTYB", 22, 22, &umr_bitfield_default },
+	 { "IN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "FG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "LA_BUSY", 26, 26, &umr_bitfield_default },
+	 { "FL_BUSY", 27, 27, &umr_bitfield_default },
+	 { "TA_BUSY", 28, 28, &umr_bitfield_default },
+	 { "FA_BUSY", 29, 29, &umr_bitfield_default },
+	 { "AL_BUSY", 30, 30, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_HIDDEN_PRIVATE_BASE_VMID[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_STATIC_MEM_CONFIG[] = {
+	 { "SWIZZLE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 1, 2, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 3, 4, &umr_bitfield_default },
+	 { "PRIVATE_MTYPE", 5, 7, &umr_bitfield_default },
+	 { "READ_ONLY_CNTL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CONFIG[] = {
+	 { "SH0_GPR_PHASE_SEL", 1, 2, &umr_bitfield_default },
+	 { "SH1_GPR_PHASE_SEL", 3, 4, &umr_bitfield_default },
+	 { "SH2_GPR_PHASE_SEL", 5, 6, &umr_bitfield_default },
+	 { "SH3_GPR_PHASE_SEL", 7, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CNTL_STATUS[] = {
+	 { "GDS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GRBM_WBUF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ORD_APP_BUSY", 2, 2, &umr_bitfield_default },
+	 { "DS_BANK_CONFLICT", 3, 3, &umr_bitfield_default },
+	 { "DS_ADDR_CONFLICT", 4, 4, &umr_bitfield_default },
+	 { "DS_WR_CLAMP", 5, 5, &umr_bitfield_default },
+	 { "DS_RD_CLAMP", 6, 6, &umr_bitfield_default },
+	 { "GRBM_RBUF_BUSY", 7, 7, &umr_bitfield_default },
+	 { "DS_BUSY", 8, 8, &umr_bitfield_default },
+	 { "GWS_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ORD_FIFO_BUSY", 10, 10, &umr_bitfield_default },
+	 { "CREDIT_BUSY0", 11, 11, &umr_bitfield_default },
+	 { "CREDIT_BUSY1", 12, 12, &umr_bitfield_default },
+	 { "CREDIT_BUSY2", 13, 13, &umr_bitfield_default },
+	 { "CREDIT_BUSY3", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ENHANCE2[] = {
+	 { "MISC", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PROTECTION_FAULT[] = {
+	 { "WRITE_DIS", 0, 0, &umr_bitfield_default },
+	 { "FAULT_DETECTED", 1, 1, &umr_bitfield_default },
+	 { "GRBM", 2, 2, &umr_bitfield_default },
+	 { "SH_ID", 3, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "SIMD_ID", 10, 11, &umr_bitfield_default },
+	 { "WAVE_ID", 12, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VM_PROTECTION_FAULT[] = {
+	 { "WRITE_DIS", 0, 0, &umr_bitfield_default },
+	 { "FAULT_DETECTED", 1, 1, &umr_bitfield_default },
+	 { "GWS", 2, 2, &umr_bitfield_default },
+	 { "OA", 3, 3, &umr_bitfield_default },
+	 { "GRBM", 4, 4, &umr_bitfield_default },
+	 { "VMID", 8, 11, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_EDC_CNT[] = {
+	 { "DED", 0, 7, &umr_bitfield_default },
+	 { "SED", 8, 15, &umr_bitfield_default },
+	 { "SEC", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_EDC_GRBM_CNT[] = {
+	 { "DED", 0, 7, &umr_bitfield_default },
+	 { "SEC", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_EDC_OA_DED[] = {
+	 { "ME0_GFXHP3D_PIX_DED", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_DED", 1, 1, &umr_bitfield_default },
+	 { "ME0_CS_DED", 2, 2, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "ME1_PIPE0_DED", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_DED", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_DED", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_DED", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_DED", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_DED", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_DED", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_DED", 11, 11, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DEBUG_CNTL[] = {
+	 { "GDS_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+	 { "UNUSED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DSM_CNTL[] = {
+	 { "SEL_DSM_GDS_IRRITATOR_DATA_A_0", 0, 0, &umr_bitfield_default },
+	 { "SEL_DSM_GDS_IRRITATOR_DATA_A_1", 1, 1, &umr_bitfield_default },
+	 { "GDS_ENABLE_SINGLE_WRITE_A", 2, 2, &umr_bitfield_default },
+	 { "SEL_DSM_GDS_IRRITATOR_DATA_B_0", 3, 3, &umr_bitfield_default },
+	 { "SEL_DSM_GDS_IRRITATOR_DATA_B_1", 4, 4, &umr_bitfield_default },
+	 { "GDS_ENABLE_SINGLE_WRITE_B", 5, 5, &umr_bitfield_default },
+	 { "UNUSED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG31[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe0_rtr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_outer_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_inner_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe2_outer_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe2_inner_dr", 5, 5, &umr_bitfield_default },
+	 { "pipe3_outer_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe3_inner_dr", 7, 7, &umr_bitfield_default },
+	 { "pipe4_outer_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe4_inner_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe5_outer_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe5_inner_dr", 11, 11, &umr_bitfield_default },
+	 { "pipe2_outer_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe2_inner_rtr", 13, 13, &umr_bitfield_default },
+	 { "pipe3_outer_rtr", 14, 14, &umr_bitfield_default },
+	 { "pipe3_inner_rtr", 15, 15, &umr_bitfield_default },
+	 { "pipe4_outer_rtr", 16, 16, &umr_bitfield_default },
+	 { "pipe4_inner_rtr", 17, 17, &umr_bitfield_default },
+	 { "pipe5_outer_rtr", 18, 18, &umr_bitfield_default },
+	 { "pipe5_inner_rtr", 19, 19, &umr_bitfield_default },
+	 { "pg_con_outer_point1_rts", 20, 20, &umr_bitfield_default },
+	 { "pg_con_outer_point2_rts", 21, 21, &umr_bitfield_default },
+	 { "pg_con_inner_point1_rts", 22, 22, &umr_bitfield_default },
+	 { "pg_con_inner_point2_rts", 23, 23, &umr_bitfield_default },
+	 { "pg_patch_fifo_empty", 24, 24, &umr_bitfield_default },
+	 { "pg_edge_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "pg_inner3_perp_fifo_empty", 26, 26, &umr_bitfield_default },
+	 { "pg_patch_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "pg_edge_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "pg_inner_perp_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "outer_ring_done_q", 30, 30, &umr_bitfield_default },
+	 { "inner_ring_done_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG[] = {
+	 { "DEBUG_STENCIL_COMPRESS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_DEPTH_COMPRESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "FETCH_FULL_Z_TILE", 2, 2, &umr_bitfield_default },
+	 { "FETCH_FULL_STENCIL_TILE", 3, 3, &umr_bitfield_default },
+	 { "FORCE_Z_MODE", 4, 5, &umr_bitfield_default },
+	 { "DEBUG_FORCE_DEPTH_READ", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_FORCE_STENCIL_READ", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIZ_ENABLE", 8, 9, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE0", 10, 11, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE1", 12, 13, &umr_bitfield_default },
+	 { "DEBUG_FAST_Z_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_FAST_STENCIL_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_NOOP_CULL_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_SUMM_SQUADS", 17, 17, &umr_bitfield_default },
+	 { "DEPTH_CACHE_FORCE_MISS", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_FORCE_FULL_Z_RANGE", 19, 20, &umr_bitfield_default },
+	 { "NEVER_FREE_Z_ONLY", 21, 21, &umr_bitfield_default },
+	 { "ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_VPORT_ZPLANE_OPTIMIZATION", 23, 23, &umr_bitfield_default },
+	 { "DECOMPRESS_AFTER_N_ZPLANES", 24, 27, &umr_bitfield_default },
+	 { "ONE_FREE_IN_FLIGHT", 28, 28, &umr_bitfield_default },
+	 { "FORCE_MISS_IF_NOT_INFLIGHT", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_DEPTH_SURFACE_SYNC", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_HTILE_SURFACE_SYNC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG2[] = {
+	 { "ALLOW_COMPZ_BYTE_MASKING", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_TC_ZRANGE_L0_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_TC_MASK_L0_CACHE", 2, 2, &umr_bitfield_default },
+	 { "DTR_ROUND_ROBIN_ARB", 3, 3, &umr_bitfield_default },
+	 { "DTR_PREZ_STALLS_FOR_ETF_ROOM", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_PREZL_CB_STALL", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL_REZ", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_PREZL_CB_STALL_REZ", 8, 8, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 9, 13, &umr_bitfield_default },
+	 { "DISABLE_TILE_COVERED_FOR_PS_ITER", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_SUBTILE_GROUPING", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_HTILE_PAIRED_PIPES", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_NULL_EOT_FORWARDING", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_DTT_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_QUAD_COHERENCY_STALL", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_PREZ_OF_REZ_SUMM", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_PREZL_VIEWPORT_STALL", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_SINGLE_STENCIL_QUAD_SUMM", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_WRITE_STALL_ON_RDWR_CONFLICT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG3[] = {
+	 { "FORCE_DB_IS_GOOD", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_TL_SSO_NULL_SUPPRESSION", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_HIZ_ON_VPORT_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_COMP_Z", 5, 5, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_SRC_Z", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_TCP_CAM_BYPASS", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_ZCMP_DIRTY_SUPPRESSION", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_REDUNDANT_PLANE_FLUSHES_OPT", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_INCOHERENT_EQAA_READS", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_OP_Z_DATA_FORWARDING", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_BYPASS", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_WRITE_COMBINE", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_DIRECT_FEEDBACK", 15, 15, &umr_bitfield_default },
+	 { "ALLOW_RF2P_RW_COLLISION", 16, 16, &umr_bitfield_default },
+	 { "SLOW_PREZ_TO_A2M_OMASK_RATE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_OP_S_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_TC_UPDATE_WRITE_COMBINE", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_HZ_TC_WRITE_COMBINE", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_TC_MA_ROUND_ROBIN_ARB", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_RAM_READ_SUPPRESION_ON_FWD", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_EQAA_A2M_PERF_OPT", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_DI_DT_STALL", 25, 25, &umr_bitfield_default },
+	 { "ENABLE_DB_PROCESS_RESET", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_OVERRASTERIZATION_FIX", 27, 27, &umr_bitfield_default },
+	 { "DONT_INSERT_CONTEXT_SUSPEND", 28, 28, &umr_bitfield_default },
+	 { "DONT_DELETE_CONTEXT_SUSPEND", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_4XAA_2P_DELAYED_WRITE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_4XAA_2P_INTERLEAVED_PMASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG4[] = {
+	 { "DISABLE_QC_Z_MASK_SUMMATION", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_QC_STENCIL_MASK_SUMMATION", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_RESUMM_TO_SINGLE_STENCIL", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL", 3, 3, &umr_bitfield_default },
+	 { "DB_EXTRA_DEBUG4", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_CREDIT_LIMIT[] = {
+	 { "DB_SC_TILE_CREDITS", 0, 4, &umr_bitfield_default },
+	 { "DB_SC_QUAD_CREDITS", 5, 9, &umr_bitfield_default },
+	 { "DB_CB_LQUAD_CREDITS", 10, 12, &umr_bitfield_default },
+	 { "DB_CB_TILE_CREDITS", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_WATERMARKS[] = {
+	 { "DEPTH_FREE", 0, 4, &umr_bitfield_default },
+	 { "DEPTH_FLUSH", 5, 10, &umr_bitfield_default },
+	 { "FORCE_SUMMARIZE", 11, 14, &umr_bitfield_default },
+	 { "DEPTH_PENDING_FREE", 15, 19, &umr_bitfield_default },
+	 { "DEPTH_CACHELINE_FREE", 20, 26, &umr_bitfield_default },
+	 { "EARLY_Z_PANIC_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "LATE_Z_PANIC_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "RE_Z_PANIC_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "AUTO_FLUSH_HTILE", 30, 30, &umr_bitfield_default },
+	 { "AUTO_FLUSH_QUAD", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SUBTILE_CONTROL[] = {
+	 { "MSAA1_X", 0, 1, &umr_bitfield_default },
+	 { "MSAA1_Y", 2, 3, &umr_bitfield_default },
+	 { "MSAA2_X", 4, 5, &umr_bitfield_default },
+	 { "MSAA2_Y", 6, 7, &umr_bitfield_default },
+	 { "MSAA4_X", 8, 9, &umr_bitfield_default },
+	 { "MSAA4_Y", 10, 11, &umr_bitfield_default },
+	 { "MSAA8_X", 12, 13, &umr_bitfield_default },
+	 { "MSAA8_Y", 14, 15, &umr_bitfield_default },
+	 { "MSAA16_X", 16, 17, &umr_bitfield_default },
+	 { "MSAA16_Y", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FREE_CACHELINES[] = {
+	 { "FREE_DTILE_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "FREE_PLANE_DEPTH", 7, 13, &umr_bitfield_default },
+	 { "FREE_Z_DEPTH", 14, 20, &umr_bitfield_default },
+	 { "FREE_HTILE_DEPTH", 21, 24, &umr_bitfield_default },
+	 { "QUAD_READ_REQS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FIFO_DEPTH1[] = {
+	 { "MI_RDREQ_FIFO_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "MI_WRREQ_FIFO_DEPTH", 5, 9, &umr_bitfield_default },
+	 { "MCC_DEPTH", 10, 15, &umr_bitfield_default },
+	 { "QC_DEPTH", 16, 20, &umr_bitfield_default },
+	 { "LTILE_PROBE_FIFO_DEPTH", 21, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FIFO_DEPTH2[] = {
+	 { "EQUAD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "ETILE_OP_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "LQUAD_FIFO_DEPTH", 15, 24, &umr_bitfield_default },
+	 { "LTILE_OP_FIFO_DEPTH", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RING_CONTROL[] = {
+	 { "COUNTER_CONTROL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_0[] = {
+	 { "BUSY_DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_1[] = {
+	 { "BUSY_DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_2[] = {
+	 { "BUSY_DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_3[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_4[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_5[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_6[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_7[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_8[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_9[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_A[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_B[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_C[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_D[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_E[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_F[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_BACKEND_MAP[] = {
+	 { "BACKEND_MAP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_GPU_ID[] = {
+	 { "GPU_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_DAISY_CHAIN[] = {
+	 { "RB_0", 0, 3, &umr_bitfield_default },
+	 { "RB_1", 4, 7, &umr_bitfield_default },
+	 { "RB_2", 8, 11, &umr_bitfield_default },
+	 { "RB_3", 12, 15, &umr_bitfield_default },
+	 { "RB_4", 16, 19, &umr_bitfield_default },
+	 { "RB_5", 20, 23, &umr_bitfield_default },
+	 { "RB_6", 24, 27, &umr_bitfield_default },
+	 { "RB_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE0[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE1[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE2[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE3[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE4[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE5[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE6[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE7[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE8[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE9[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE10[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE11[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE12[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE13[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE14[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE15[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE16[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE17[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE18[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE19[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE20[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE21[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE22[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE23[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE24[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE25[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE26[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE27[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE28[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE29[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE30[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE31[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE0[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE1[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE2[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE3[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE4[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE5[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE6[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE7[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE8[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE9[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE10[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE11[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE12[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE13[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE14[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE15[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_3[] = {
+	 { "DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL", 0, 0, &umr_bitfield_default },
+	 { "RAM_ADDRESS_CONFLICTS_DISALLOWED", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_FAST_CLEAR_FETCH_OPT", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_QUAD_MARKER_DROP_STOP", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_OVERWRITE_COMBINER_CAM_CLR", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_CC_CACHE_OVWR_STATUS_ACCUM", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_CC_CACHE_OVWR_KEY_MOD", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_CC_CACHE_PANIC_GATING", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL[] = {
+	 { "CM_CACHE_EVICT_POINT", 0, 3, &umr_bitfield_default },
+	 { "FC_CACHE_EVICT_POINT", 6, 9, &umr_bitfield_default },
+	 { "CC_CACHE_EVICT_POINT", 12, 15, &umr_bitfield_default },
+	 { "ALLOW_MRT_WITH_DUAL_SOURCE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_INTNORM_LE11BPC_CLAMPING", 18, 18, &umr_bitfield_default },
+	 { "FORCE_NEEDS_DST", 19, 19, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_TOGGLE", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_RESULT_EQ_DEST", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_FULL_WRITE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DONT_RD_DST", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_BYPASS", 25, 25, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DISCARD_PIXEL", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED", 27, 27, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT", 28, 28, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_CC_IB_SERIALIZER_STATE_OPT", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_1[] = {
+	 { "CM_CACHE_NUM_TAGS", 0, 4, &umr_bitfield_default },
+	 { "FC_CACHE_NUM_TAGS", 5, 10, &umr_bitfield_default },
+	 { "CC_CACHE_NUM_TAGS", 11, 16, &umr_bitfield_default },
+	 { "CM_TILE_FIFO_DEPTH", 17, 25, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_2[] = {
+	 { "CC_EVEN_ODD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "FC_RDLAT_TILE_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "FC_RDLAT_QUAD_FIFO_DEPTH", 15, 22, &umr_bitfield_default },
+	 { "DRR_ASSUMED_FIFO_DEPTH_DIV8", 24, 27, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DCC_CONFIG[] = {
+	 { "OVERWRITE_COMBINER_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "OVERWRITE_COMBINER_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "OVERWRITE_COMBINER_CC_POP_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "FC_RDLAT_KEYID_FIFO_DEPTH", 8, 15, &umr_bitfield_default },
+	 { "READ_RETURN_SKID_FIFO_DEPTH", 16, 22, &umr_bitfield_default },
+	 { "DCC_CACHE_EVICT_POINT", 24, 27, &umr_bitfield_default },
+	 { "DCC_CACHE_NUM_TAGS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_17[] = {
+	 { "TILE_INTFC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MU_BUSY", 1, 1, &umr_bitfield_default },
+	 { "TQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "AC_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CRW_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CACHE_CTRL_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MC_WR_PENDING", 6, 6, &umr_bitfield_default },
+	 { "FC_WR_PENDING", 7, 7, &umr_bitfield_default },
+	 { "FC_RD_PENDING", 8, 8, &umr_bitfield_default },
+	 { "EVICT_PENDING", 9, 9, &umr_bitfield_default },
+	 { "LAST_RD_ARB_WINNER", 10, 10, &umr_bitfield_default },
+	 { "MU_STATE", 11, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_18[] = {
+	 { "TILE_RETIREMENT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "FOP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_BUSY", 2, 2, &umr_bitfield_default },
+	 { "LAT_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CACHE_CTL_BUSY", 4, 4, &umr_bitfield_default },
+	 { "ADDR_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MERGE_BUSY", 6, 6, &umr_bitfield_default },
+	 { "QUAD_BUSY", 7, 7, &umr_bitfield_default },
+	 { "TILE_BUSY", 8, 8, &umr_bitfield_default },
+	 { "DCC_BUSY", 9, 9, &umr_bitfield_default },
+	 { "DOC_BUSY", 10, 10, &umr_bitfield_default },
+	 { "DAG_BUSY", 11, 11, &umr_bitfield_default },
+	 { "DOC_STALL", 12, 12, &umr_bitfield_default },
+	 { "DOC_QT_CAM_FULL", 13, 13, &umr_bitfield_default },
+	 { "DOC_CL_CAM_FULL", 14, 14, &umr_bitfield_default },
+	 { "DOC_QUAD_PTR_FIFO_FULL", 15, 15, &umr_bitfield_default },
+	 { "DOC_SECTOR_MASK_FIFO_FULL", 16, 16, &umr_bitfield_default },
+	 { "DCS_READ_WINNER_LAST", 17, 17, &umr_bitfield_default },
+	 { "DCS_READ_EV_PENDING", 18, 18, &umr_bitfield_default },
+	 { "DCS_WRITE_CC_PENDING", 19, 19, &umr_bitfield_default },
+	 { "DCS_READ_CC_PENDING", 20, 20, &umr_bitfield_default },
+	 { "DCS_WRITE_MC_PENDING", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_19[] = {
+	 { "SURF_SYNC_STATE", 0, 1, &umr_bitfield_default },
+	 { "SURF_SYNC_START", 2, 2, &umr_bitfield_default },
+	 { "SF_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "RB_BUSY", 5, 5, &umr_bitfield_default },
+	 { "DS_BUSY", 6, 6, &umr_bitfield_default },
+	 { "TB_BUSY", 7, 7, &umr_bitfield_default },
+	 { "IB_BUSY", 8, 8, &umr_bitfield_default },
+	 { "DRR_BUSY", 9, 9, &umr_bitfield_default },
+	 { "DF_BUSY", 10, 10, &umr_bitfield_default },
+	 { "DD_BUSY", 11, 11, &umr_bitfield_default },
+	 { "DC_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DK_BUSY", 13, 13, &umr_bitfield_default },
+	 { "DF_SKID_FIFO_EMPTY", 14, 14, &umr_bitfield_default },
+	 { "DF_CLEAR_FIFO_EMPTY", 15, 15, &umr_bitfield_default },
+	 { "DD_READY", 16, 16, &umr_bitfield_default },
+	 { "DC_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "DC_READY", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_20[] = {
+	 { "MC_RDREQ_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDITS", 6, 11, &umr_bitfield_default },
+	 { "CC_RDREQ_HAD_ITS_TURN", 12, 12, &umr_bitfield_default },
+	 { "FC_RDREQ_HAD_ITS_TURN", 13, 13, &umr_bitfield_default },
+	 { "CM_RDREQ_HAD_ITS_TURN", 14, 14, &umr_bitfield_default },
+	 { "CC_WRREQ_HAD_ITS_TURN", 16, 16, &umr_bitfield_default },
+	 { "FC_WRREQ_HAD_ITS_TURN", 17, 17, &umr_bitfield_default },
+	 { "CM_WRREQ_HAD_ITS_TURN", 18, 18, &umr_bitfield_default },
+	 { "CC_WRREQ_FIFO_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "FC_WRREQ_FIFO_EMPTY", 21, 21, &umr_bitfield_default },
+	 { "CM_WRREQ_FIFO_EMPTY", 22, 22, &umr_bitfield_default },
+	 { "DCC_WRREQ_FIFO_EMPTY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_21[] = {
+	 { "CM_BUSY", 0, 0, &umr_bitfield_default },
+	 { "FC_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CC_BUSY", 2, 2, &umr_bitfield_default },
+	 { "BB_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MA_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CORE_SCLK_VLD", 5, 5, &umr_bitfield_default },
+	 { "REG_SCLK1_VLD", 6, 6, &umr_bitfield_default },
+	 { "REG_SCLK0_VLD", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_22[] = {
+	 { "OUTSTANDING_MC_READS", 0, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_MC_WRITES", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TBA_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TBA_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TMA_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TMA_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG32[] = {
+	 { "first_ring_of_patch", 0, 0, &umr_bitfield_default },
+	 { "last_ring_of_patch", 1, 1, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring", 2, 2, &umr_bitfield_default },
+	 { "last_point_of_outer_edge", 3, 3, &umr_bitfield_default },
+	 { "last_edge_of_inner_ring", 4, 4, &umr_bitfield_default },
+	 { "last_point_of_inner_edge", 5, 5, &umr_bitfield_default },
+	 { "last_patch_of_tg_p0_q", 6, 6, &umr_bitfield_default },
+	 { "event_null_special_p0_q", 7, 7, &umr_bitfield_default },
+	 { "event_flag_p5_q", 8, 8, &umr_bitfield_default },
+	 { "first_point_of_patch_p5_q", 9, 9, &umr_bitfield_default },
+	 { "first_point_of_edge_p5_q", 10, 10, &umr_bitfield_default },
+	 { "last_patch_of_tg_p5_q", 11, 11, &umr_bitfield_default },
+	 { "tess_topology_p5_q", 12, 13, &umr_bitfield_default },
+	 { "pipe5_inner3_rtr", 14, 14, &umr_bitfield_default },
+	 { "pipe5_inner2_rtr", 15, 15, &umr_bitfield_default },
+	 { "pg_edge_fifo3_full", 16, 16, &umr_bitfield_default },
+	 { "pg_edge_fifo2_full", 17, 17, &umr_bitfield_default },
+	 { "pg_inner3_point_fifo_full", 18, 18, &umr_bitfield_default },
+	 { "pg_outer3_point_fifo_full", 19, 19, &umr_bitfield_default },
+	 { "pg_inner2_point_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "pg_outer2_point_fifo_full", 21, 21, &umr_bitfield_default },
+	 { "pg_inner_point_fifo_full", 22, 22, &umr_bitfield_default },
+	 { "pg_outer_point_fifo_full", 23, 23, &umr_bitfield_default },
+	 { "inner2_fifos_rtr", 24, 24, &umr_bitfield_default },
+	 { "inner_fifos_rtr", 25, 25, &umr_bitfield_default },
+	 { "outer_fifos_rtr", 26, 26, &umr_bitfield_default },
+	 { "fifos_rtr", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_M0[] = {
+	 { "M0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_EXEC_LO[] = {
+	 { "EXEC_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_EXEC_HI[] = {
+	 { "EXEC_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG33[] = {
+	 { "pipe0_patch_dr", 0, 0, &umr_bitfield_default },
+	 { "ring3_pipe1_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe2_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 4, 4, &umr_bitfield_default },
+	 { "ring2_pipe1_dr", 5, 5, &umr_bitfield_default },
+	 { "ring1_pipe1_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe2_rtr", 7, 7, &umr_bitfield_default },
+	 { "pipe3_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe3_rtr", 9, 9, &umr_bitfield_default },
+	 { "ring2_in_sync_q", 10, 10, &umr_bitfield_default },
+	 { "ring1_in_sync_q", 11, 11, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 12, 12, &umr_bitfield_default },
+	 { "ring3_in_sync_q", 13, 13, &umr_bitfield_default },
+	 { "tm_te11_event_rtr", 14, 14, &umr_bitfield_default },
+	 { "first_prim_of_patch_q", 15, 15, &umr_bitfield_default },
+	 { "con_prim_fifo_full", 16, 16, &umr_bitfield_default },
+	 { "con_vert_fifo_full", 17, 17, &umr_bitfield_default },
+	 { "con_prim_fifo_empty", 18, 18, &umr_bitfield_default },
+	 { "con_vert_fifo_empty", 19, 19, &umr_bitfield_default },
+	 { "last_patch_of_tg_p0_q", 20, 20, &umr_bitfield_default },
+	 { "ring3_valid_p2", 21, 21, &umr_bitfield_default },
+	 { "ring2_valid_p2", 22, 22, &umr_bitfield_default },
+	 { "ring1_valid_p2", 23, 23, &umr_bitfield_default },
+	 { "tess_type_p0_q", 24, 25, &umr_bitfield_default },
+	 { "tess_topology_p0_q", 26, 27, &umr_bitfield_default },
+	 { "te11_out_vert_gs_en", 28, 28, &umr_bitfield_default },
+	 { "con_ring3_busy", 29, 29, &umr_bitfield_default },
+	 { "con_ring2_busy", 30, 30, &umr_bitfield_default },
+	 { "con_ring1_busy", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG34[] = {
+	 { "con_state_q", 0, 3, &umr_bitfield_default },
+	 { "second_cycle_q", 4, 4, &umr_bitfield_default },
+	 { "process_tri_middle_p0_q", 5, 5, &umr_bitfield_default },
+	 { "process_tri_1st_2nd_half_p0_q", 6, 6, &umr_bitfield_default },
+	 { "process_tri_center_poly_p0_q", 7, 7, &umr_bitfield_default },
+	 { "pipe0_patch_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe0_edge_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe1_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 11, 11, &umr_bitfield_default },
+	 { "pipe0_edge_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe1_rtr", 13, 13, &umr_bitfield_default },
+	 { "outer_parity_p0_q", 14, 14, &umr_bitfield_default },
+	 { "parallel_parity_p0_q", 15, 15, &umr_bitfield_default },
+	 { "first_ring_of_patch_p0_q", 16, 16, &umr_bitfield_default },
+	 { "last_ring_of_patch_p0_q", 17, 17, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring_p0_q", 18, 18, &umr_bitfield_default },
+	 { "last_point_of_outer_ring_p1", 19, 19, &umr_bitfield_default },
+	 { "last_point_of_inner_ring_p1", 20, 20, &umr_bitfield_default },
+	 { "outer_edge_tf_eq_one_p0_q", 21, 21, &umr_bitfield_default },
+	 { "advance_outer_point_p1", 22, 22, &umr_bitfield_default },
+	 { "advance_inner_point_p1", 23, 23, &umr_bitfield_default },
+	 { "next_ring_is_rect_p0_q", 24, 24, &umr_bitfield_default },
+	 { "pipe1_outer1_rtr", 25, 25, &umr_bitfield_default },
+	 { "pipe1_outer2_rtr", 26, 26, &umr_bitfield_default },
+	 { "pipe1_inner1_rtr", 27, 27, &umr_bitfield_default },
+	 { "pipe1_inner2_rtr", 28, 28, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 29, 29, &umr_bitfield_default },
+	 { "pipe1_edge_rtr", 30, 30, &umr_bitfield_default },
+	 { "use_stored_inner_q_ring1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG36[] = {
+	 { "VGT_PA_clipp_eop", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_INVALIDATE[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_STATUS[] = {
+	 { "TCP_BUSY", 0, 0, &umr_bitfield_default },
+	 { "INPUT_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ADRS_BUSY", 2, 2, &umr_bitfield_default },
+	 { "TAGRAMS_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CNTRL_BUSY", 4, 4, &umr_bitfield_default },
+	 { "LFIFO_BUSY", 5, 5, &umr_bitfield_default },
+	 { "READ_BUSY", 6, 6, &umr_bitfield_default },
+	 { "FORMAT_BUSY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CNTL[] = {
+	 { "FORCE_HIT", 0, 0, &umr_bitfield_default },
+	 { "FORCE_MISS", 1, 1, &umr_bitfield_default },
+	 { "L1_SIZE", 2, 3, &umr_bitfield_default },
+	 { "FLAT_BUF_HASH_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FLAT_BUF_CACHE_SWIZZLE", 5, 5, &umr_bitfield_default },
+	 { "FORCE_EOW_TOTAL_CNT", 15, 20, &umr_bitfield_default },
+	 { "FORCE_EOW_TAGRAM_CNT", 22, 27, &umr_bitfield_default },
+	 { "DISABLE_Z_MAP", 28, 28, &umr_bitfield_default },
+	 { "INV_ALL_VMIDS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CHAN_STEER_LO[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "CHAN3", 12, 15, &umr_bitfield_default },
+	 { "CHAN4", 16, 19, &umr_bitfield_default },
+	 { "CHAN5", 20, 23, &umr_bitfield_default },
+	 { "CHAN6", 24, 27, &umr_bitfield_default },
+	 { "CHAN7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CHAN_STEER_HI[] = {
+	 { "CHAN8", 0, 3, &umr_bitfield_default },
+	 { "CHAN9", 4, 7, &umr_bitfield_default },
+	 { "CHANA", 8, 11, &umr_bitfield_default },
+	 { "CHANB", 12, 15, &umr_bitfield_default },
+	 { "CHANC", 16, 19, &umr_bitfield_default },
+	 { "CHAND", 20, 23, &umr_bitfield_default },
+	 { "CHANE", 24, 27, &umr_bitfield_default },
+	 { "CHANF", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_ADDR_CONFIG[] = {
+	 { "NUM_TCC_BANKS", 0, 3, &umr_bitfield_default },
+	 { "NUM_BANKS", 4, 5, &umr_bitfield_default },
+	 { "COLHI_WIDTH", 6, 8, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CREDIT[] = {
+	 { "LFIFO_CREDIT", 0, 9, &umr_bitfield_default },
+	 { "REQ_FIFO_CREDIT", 16, 22, &umr_bitfield_default },
+	 { "TD_CREDIT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_BUFFER_ADDR_HASH_CNTL[] = {
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "BANK_BITS", 8, 10, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 16, 18, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_EDC_CNT[] = {
+	 { "SEC_COUNT", 0, 7, &umr_bitfield_default },
+	 { "LFIFO_SED_COUNT", 8, 15, &umr_bitfield_default },
+	 { "DED_COUNT", 16, 23, &umr_bitfield_default },
+	 { "UNUSED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_LOAD_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_LOAD_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_STORE_POLICY[] = {
+	 { "POLICY_0", 0, 0, &umr_bitfield_default },
+	 { "POLICY_1", 1, 1, &umr_bitfield_default },
+	 { "POLICY_2", 2, 2, &umr_bitfield_default },
+	 { "POLICY_3", 3, 3, &umr_bitfield_default },
+	 { "POLICY_4", 4, 4, &umr_bitfield_default },
+	 { "POLICY_5", 5, 5, &umr_bitfield_default },
+	 { "POLICY_6", 6, 6, &umr_bitfield_default },
+	 { "POLICY_7", 7, 7, &umr_bitfield_default },
+	 { "POLICY_8", 8, 8, &umr_bitfield_default },
+	 { "POLICY_9", 9, 9, &umr_bitfield_default },
+	 { "POLICY_10", 10, 10, &umr_bitfield_default },
+	 { "POLICY_11", 11, 11, &umr_bitfield_default },
+	 { "POLICY_12", 12, 12, &umr_bitfield_default },
+	 { "POLICY_13", 13, 13, &umr_bitfield_default },
+	 { "POLICY_14", 14, 14, &umr_bitfield_default },
+	 { "POLICY_15", 15, 15, &umr_bitfield_default },
+	 { "POLICY_16", 16, 16, &umr_bitfield_default },
+	 { "POLICY_17", 17, 17, &umr_bitfield_default },
+	 { "POLICY_18", 18, 18, &umr_bitfield_default },
+	 { "POLICY_19", 19, 19, &umr_bitfield_default },
+	 { "POLICY_20", 20, 20, &umr_bitfield_default },
+	 { "POLICY_21", 21, 21, &umr_bitfield_default },
+	 { "POLICY_22", 22, 22, &umr_bitfield_default },
+	 { "POLICY_23", 23, 23, &umr_bitfield_default },
+	 { "POLICY_24", 24, 24, &umr_bitfield_default },
+	 { "POLICY_25", 25, 25, &umr_bitfield_default },
+	 { "POLICY_26", 26, 26, &umr_bitfield_default },
+	 { "POLICY_27", 27, 27, &umr_bitfield_default },
+	 { "POLICY_28", 28, 28, &umr_bitfield_default },
+	 { "POLICY_29", 29, 29, &umr_bitfield_default },
+	 { "POLICY_30", 30, 30, &umr_bitfield_default },
+	 { "POLICY_31", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_LOAD_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_LOAD_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_STORE_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_STORE_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_ATOMIC_POLICY[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_VOLATILE[] = {
+	 { "VOL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_VOLATILE[] = {
+	 { "VOL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_STATUS[] = {
+	 { "TCI_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_CNTL_1[] = {
+	 { "WBINVL1_NUM_CYCLES", 0, 15, &umr_bitfield_default },
+	 { "REQ_FIFO_DEPTH", 16, 23, &umr_bitfield_default },
+	 { "WDATA_RAM_DEPTH", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_CNTL_2[] = {
+	 { "L1_INVAL_ON_WBINVL2", 0, 0, &umr_bitfield_default },
+	 { "TCA_MAX_CREDIT", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_CTRL[] = {
+	 { "CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "RATE", 2, 3, &umr_bitfield_default },
+	 { "WRITEBACK_MARGIN", 4, 7, &umr_bitfield_default },
+	 { "METADATA_LATENCY_FIFO_SIZE", 8, 11, &umr_bitfield_default },
+	 { "SRC_FIFO_SIZE", 12, 15, &umr_bitfield_default },
+	 { "LATENCY_FIFO_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WB_OR_INV_ALL_VMIDS", 20, 20, &umr_bitfield_default },
+	 { "MDC_SIZE", 24, 25, &umr_bitfield_default },
+	 { "MDC_SECTOR_SIZE", 26, 27, &umr_bitfield_default },
+	 { "MDC_SIDEBAND_FIFO_SIZE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_EDC_CNT[] = {
+	 { "SEC_COUNT", 0, 7, &umr_bitfield_default },
+	 { "DED_COUNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_REDUNDANCY[] = {
+	 { "MC_SEL0", 0, 0, &umr_bitfield_default },
+	 { "MC_SEL1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_EXE_DISABLE[] = {
+	 { "EXE_DISABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_DSM_CNTL[] = {
+	 { "CACHE_RAM_IRRITATOR_DATA_SEL", 0, 1, &umr_bitfield_default },
+	 { "CACHE_RAM_IRRITATOR_SINGLE_WRITE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_CTRL[] = {
+	 { "HOLE_TIMEOUT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_PS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_PS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_PS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "WAVE_CNT_EN", 7, 7, &umr_bitfield_default },
+	 { "EXTRA_LDS_SIZE", 8, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_VS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_LATE_ALLOC_VS[] = {
+	 { "LIMIT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_VS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "SO_BASE0_EN", 8, 8, &umr_bitfield_default },
+	 { "SO_BASE1_EN", 9, 9, &umr_bitfield_default },
+	 { "SO_BASE2_EN", 10, 10, &umr_bitfield_default },
+	 { "SO_BASE3_EN", 11, 11, &umr_bitfield_default },
+	 { "SO_EN", 12, 12, &umr_bitfield_default },
+	 { "EXCP_EN", 13, 21, &umr_bitfield_default },
+	 { "DISPATCH_DRAW_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_GS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+	 { "GROUP_FIFO_DEPTH", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_GS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_GS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "EXCP_EN", 7, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES_GS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_ES[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+	 { "GROUP_FIFO_DEPTH", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_ES[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_ES[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_HS[] = {
+	 { "WAVE_LIMIT", 0, 5, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 6, 9, &umr_bitfield_default },
+	 { "GROUP_FIFO_DEPTH", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_HS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CACHE_CTL", 24, 26, &umr_bitfield_default },
+	 { "CDBG_USER", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_HS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 8, 8, &umr_bitfield_default },
+	 { "EXCP_EN", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_HS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_LS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+	 { "GROUP_FIFO_DEPTH", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_LS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CACHE_CTL", 26, 28, &umr_bitfield_default },
+	 { "CDBG_USER", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DISPATCH_INITIATOR[] = {
+	 { "COMPUTE_SHADER_EN", 0, 0, &umr_bitfield_default },
+	 { "PARTIAL_TG_EN", 1, 1, &umr_bitfield_default },
+	 { "FORCE_START_AT_000", 2, 2, &umr_bitfield_default },
+	 { "ORDERED_APPEND_ENBL", 3, 3, &umr_bitfield_default },
+	 { "ORDERED_APPEND_MODE", 4, 4, &umr_bitfield_default },
+	 { "USE_THREAD_DIMENSIONS", 5, 5, &umr_bitfield_default },
+	 { "ORDER_MODE", 6, 6, &umr_bitfield_default },
+	 { "DISPATCH_CACHE_CNTL", 7, 9, &umr_bitfield_default },
+	 { "SCALAR_L1_INV_VOL", 10, 10, &umr_bitfield_default },
+	 { "VECTOR_L1_INV_VOL", 11, 11, &umr_bitfield_default },
+	 { "DATA_ATC", 12, 12, &umr_bitfield_default },
+	 { "RESTORE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_X[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_Y[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_Z[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_X[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_Y[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_Z[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_X[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Y[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Z[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PIPELINESTAT_ENABLE[] = {
+	 { "PIPELINESTAT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PERFCOUNT_ENABLE[] = {
+	 { "PERFCOUNT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+	 { "INST_ATC", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TBA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TBA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_RSRC1[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "BULKY", 24, 24, &umr_bitfield_default },
+	 { "CDBG_USER", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_RSRC2[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "TGID_X_EN", 7, 7, &umr_bitfield_default },
+	 { "TGID_Y_EN", 8, 8, &umr_bitfield_default },
+	 { "TGID_Z_EN", 9, 9, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 10, 10, &umr_bitfield_default },
+	 { "TIDIG_COMP_CNT", 11, 12, &umr_bitfield_default },
+	 { "EXCP_EN_MSB", 13, 14, &umr_bitfield_default },
+	 { "LDS_SIZE", 15, 23, &umr_bitfield_default },
+	 { "EXCP_EN", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_VMID[] = {
+	 { "DATA", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESOURCE_LIMITS[] = {
+	 { "WAVES_PER_SH", 0, 9, &umr_bitfield_default },
+	 { "TG_PER_CU", 12, 15, &umr_bitfield_default },
+	 { "LOCK_THRESHOLD", 16, 21, &umr_bitfield_default },
+	 { "SIMD_DEST_CNTL", 22, 22, &umr_bitfield_default },
+	 { "FORCE_SIMD_DIST", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_COUNT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE0[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE1[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMPRING_SIZE[] = {
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE2[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE3[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_X[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_Y[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_Z[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_THREAD_TRACE_ENABLE[] = {
+	 { "THREAD_TRACE_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_MISC_RESERVED[] = {
+	 { "SEND_SEID", 0, 1, &umr_bitfield_default },
+	 { "RESERVED2", 2, 2, &umr_bitfield_default },
+	 { "RESERVED3", 3, 3, &umr_bitfield_default },
+	 { "RESERVED4", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID_BASE", 5, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DISPATCH_ID[] = {
+	 { "DISPATCH_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_THREADGROUP_ID[] = {
+	 { "THREADGROUP_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RELAUNCH[] = {
+	 { "PAYLOAD", 0, 29, &umr_bitfield_default },
+	 { "IS_EVENT", 30, 30, &umr_bitfield_default },
+	 { "IS_STATE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_WAVE_RESTORE_ADDR_LO[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_WAVE_RESTORE_ADDR_HI[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_WAVE_RESTORE_CONTROL[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "MTYPE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NOWHERE[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG03[] = {
+	 { "clipsm0_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG3[] = {
+	 { "pipe_num_busy", 0, 10, &umr_bitfield_default },
+	 { "pipe0_busy_num", 11, 14, &umr_bitfield_default },
+	 { "spare", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG3[] = {
+	 { "rbiu_spl_dr_valid", 0, 0, &umr_bitfield_default },
+	 { "SPARE0", 1, 1, &umr_bitfield_default },
+	 { "pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "pipe1_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "wd_subdma_fifo_empty", 6, 6, &umr_bitfield_default },
+	 { "wd_subdma_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "dma_buf_type_p0_q", 8, 9, &umr_bitfield_default },
+	 { "dma_zero_indices_p0_q", 10, 10, &umr_bitfield_default },
+	 { "dma_req_path_p3_q", 11, 11, &umr_bitfield_default },
+	 { "dma_not_eop_p1_q", 12, 12, &umr_bitfield_default },
+	 { "out_of_range_p4", 13, 13, &umr_bitfield_default },
+	 { "last_sub_dma_p3_q", 14, 14, &umr_bitfield_default },
+	 { "last_rdreq_of_sub_dma_p4", 15, 15, &umr_bitfield_default },
+	 { "WD_IA_dma_send_d", 16, 16, &umr_bitfield_default },
+	 { "WD_IA_dma_rtr", 17, 17, &umr_bitfield_default },
+	 { "WD_IA1_dma_send_d", 18, 18, &umr_bitfield_default },
+	 { "WD_IA1_dma_rtr", 19, 19, &umr_bitfield_default },
+	 { "last_inst_of_dma_p2", 20, 20, &umr_bitfield_default },
+	 { "last_sd_of_inst_p2", 21, 21, &umr_bitfield_default },
+	 { "last_sd_of_dma_p2", 22, 22, &umr_bitfield_default },
+	 { "SPARE1", 23, 23, &umr_bitfield_default },
+	 { "WD_IA_dma_busy", 24, 24, &umr_bitfield_default },
+	 { "WD_IA1_dma_busy", 25, 25, &umr_bitfield_default },
+	 { "send_to_ia1_p3_q", 26, 26, &umr_bitfield_default },
+	 { "dma_wd_switch_on_eop_p3_q", 27, 27, &umr_bitfield_default },
+	 { "pipe3_dr", 28, 28, &umr_bitfield_default },
+	 { "pipe3_rtr", 29, 29, &umr_bitfield_default },
+	 { "wd_dma2draw_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "wd_dma2draw_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_CNTL[] = {
+	 { "POLICY", 0, 0, &umr_bitfield_default },
+	 { "MTYPE", 2, 3, &umr_bitfield_default },
+	 { "LFSR_RESET", 28, 28, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_STAT[] = {
+	 { "BURST_COUNT", 0, 15, &umr_bitfield_default },
+	 { "TAGS_PENDING", 16, 24, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_ADDR_LO[] = {
+	 { "ADDR_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_CMD[] = {
+	 { "OFFSET", 0, 8, &umr_bitfield_default },
+	 { "SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_MGCG_SYNC_CNTL[] = {
+	 { "COOLDOWN_PERIOD", 0, 7, &umr_bitfield_default },
+	 { "WARMUP_PERIOD", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VIRT_STATUS[] = {
+	 { "VIRT_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "BUF_SWAP", 17, 18, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "BUF_SWAP", 17, 18, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_WR[] = {
+	 { "RB_RPTR_WR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "RB_WPTR_POLL_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "RB_WPTR_POLL_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS[] = {
+	 { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DEVICE_ID[] = {
+	 { "DEVICE_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ENDIAN_SWAP[] = {
+	 { "ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_VMID[] = {
+	 { "RB0_VMID", 0, 3, &umr_bitfield_default },
+	 { "RB1_VMID", 8, 11, &umr_bitfield_default },
+	 { "RB2_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE0_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE1_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL[] = {
+	 { "DOORBELL_OFFSET", 2, 22, &umr_bitfield_default },
+	 { "DOORBELL_EN", 30, 30, &umr_bitfield_default },
+	 { "DOORBELL_HIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_DOORBELL_RANGE_LOWER[] = {
+	 { "DOORBELL_RANGE_LOWER", 2, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_DOORBELL_RANGE_UPPER[] = {
+	 { "DOORBELL_RANGE_UPPER", 2, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_DOORBELL_RANGE_LOWER[] = {
+	 { "DOORBELL_RANGE_LOWER", 2, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_DOORBELL_RANGE_UPPER[] = {
+	 { "DOORBELL_RANGE_UPPER", 2, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING0[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING1[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING2[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING0[] = {
+	 { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default },
+	 { "GCNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING1[] = {
+	 { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING2[] = {
+	 { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PWR_CNTL[] = {
+	 { "GFX_CLK_HALT_ME0_PIPE0", 0, 0, &umr_bitfield_default },
+	 { "GFX_CLK_HALT_ME0_PIPE1", 1, 1, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME1_PIPE0", 8, 8, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME1_PIPE1", 9, 9, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME1_PIPE2", 10, 10, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME1_PIPE3", 11, 11, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME2_PIPE0", 16, 16, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME2_PIPE1", 17, 17, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME2_PIPE2", 18, 18, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME2_PIPE3", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEM_SLP_CNTL[] = {
+	 { "CP_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "CP_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 6, &umr_bitfield_default },
+	 { "CP_LS_DS_BUSY_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "CP_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CP_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "CLIENT", 4, 7, &umr_bitfield_default },
+	 { "ME", 8, 9, &umr_bitfield_default },
+	 { "PIPE", 10, 11, &umr_bitfield_default },
+	 { "QUEUE", 12, 14, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING0[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING1[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING2[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_EDC_MODE[] = {
+	 { "FORCE_SEC_ON_DED", 16, 16, &umr_bitfield_default },
+	 { "DED_MODE", 20, 21, &umr_bitfield_default },
+	 { "PROP_FED", 29, 29, &umr_bitfield_default },
+	 { "BYPASS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_WPTR_POLL_CNTL[] = {
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+	 { "POLL_ACTIVE", 30, 30, &umr_bitfield_default },
+	 { "EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_WPTR_POLL_CNTL1[] = {
+	 { "QUEUE_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_INT_STAT_DEBUG[] = {
+	 { "CMP_QUERY_STATUS_INT_ASSERTED", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ASSERTED", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_INT_STAT_DEBUG[] = {
+	 { "CMP_QUERY_STATUS_INT_ASSERTED", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ASSERTED", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC1_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC2_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC1_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC2_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CONTEXT_CNTL[] = {
+	 { "ME0PIPE0_MAX_WD_CNTX", 0, 2, &umr_bitfield_default },
+	 { "ME0PIPE0_MAX_PIPE_CNTX", 4, 6, &umr_bitfield_default },
+	 { "ME0PIPE1_MAX_WD_CNTX", 16, 18, &umr_bitfield_default },
+	 { "ME0PIPE1_MAX_PIPE_CNTX", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MAX_CONTEXT[] = {
+	 { "MAX_CONTEXT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IQ_WAIT_TIME1[] = {
+	 { "IB_OFFLOAD", 0, 7, &umr_bitfield_default },
+	 { "ATOMIC_OFFLOAD", 8, 15, &umr_bitfield_default },
+	 { "WRM_OFFLOAD", 16, 23, &umr_bitfield_default },
+	 { "GWS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IQ_WAIT_TIME2[] = {
+	 { "QUE_SLEEP", 0, 7, &umr_bitfield_default },
+	 { "SCH_WAVE", 8, 15, &umr_bitfield_default },
+	 { "SEM_REARM", 16, 23, &umr_bitfield_default },
+	 { "DEQ_RETRY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID_RESET[] = {
+	 { "RESET_REQUEST", 0, 15, &umr_bitfield_default },
+	 { "RESET_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID_PREEMPT[] = {
+	 { "PREEMPT_REQUEST", 0, 15, &umr_bitfield_default },
+	 { "VIRT_COMMAND", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_CNTX_ID[] = {
+	 { "CNTX_ID", 0, 27, &umr_bitfield_default },
+	 { "QUEUE_ID", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_STATUS[] = {
+	 { "DOORBELL_UPDATED", 0, 0, &umr_bitfield_default },
+	 { "DOORBELL_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_IC_BASE_LO[] = {
+	 { "IC_BASE_LO", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_IC_BASE_HI[] = {
+	 { "IC_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_IC_BASE_CNTL[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_IC_OP_CNTL[] = {
+	 { "INVALIDATE_CACHE", 0, 0, &umr_bitfield_default },
+	 { "PRIME_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "ICACHE_PRIMED", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC1_F32_INT_DIS[] = {
+	 { "EDC_ROQ_FED_INT", 0, 0, &umr_bitfield_default },
+	 { "PRIV_REG_INT", 1, 1, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERR_INT", 2, 2, &umr_bitfield_default },
+	 { "EDC_TC_FED_INT", 3, 3, &umr_bitfield_default },
+	 { "EDC_GDS_FED_INT", 4, 4, &umr_bitfield_default },
+	 { "EDC_SCRATCH_FED_INT", 5, 5, &umr_bitfield_default },
+	 { "WAVE_RESTORE_INT", 6, 6, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT", 7, 7, &umr_bitfield_default },
+	 { "EDC_DMA_FED_INT", 8, 8, &umr_bitfield_default },
+	 { "IQ_TIMER_INT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC2_F32_INT_DIS[] = {
+	 { "EDC_ROQ_FED_INT", 0, 0, &umr_bitfield_default },
+	 { "PRIV_REG_INT", 1, 1, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERR_INT", 2, 2, &umr_bitfield_default },
+	 { "EDC_TC_FED_INT", 3, 3, &umr_bitfield_default },
+	 { "EDC_GDS_FED_INT", 4, 4, &umr_bitfield_default },
+	 { "EDC_SCRATCH_FED_INT", 5, 5, &umr_bitfield_default },
+	 { "WAVE_RESTORE_INT", 6, 6, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT", 7, 7, &umr_bitfield_default },
+	 { "EDC_DMA_FED_INT", 8, 8, &umr_bitfield_default },
+	 { "IQ_TIMER_INT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID_STATUS[] = {
+	 { "PREEMPT_DE_STATUS", 0, 15, &umr_bitfield_default },
+	 { "PREEMPT_CE_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_PRIORITY[] = {
+	 { "PIPE_ORDER_TS0", 0, 2, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS1", 3, 5, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS2", 6, 8, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS3", 9, 11, &umr_bitfield_default },
+	 { "TS0_DUR_MULT", 12, 13, &umr_bitfield_default },
+	 { "TS1_DUR_MULT", 14, 15, &umr_bitfield_default },
+	 { "TS2_DUR_MULT", 16, 17, &umr_bitfield_default },
+	 { "TS3_DUR_MULT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_CYCLES_0[] = {
+	 { "TS0_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS1_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_CYCLES_1[] = {
+	 { "TS2_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS3_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_GFX[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_HP3D[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_CS0[] = {
+	 { "PIPE0", 0, 7, &umr_bitfield_default },
+	 { "PIPE1", 8, 15, &umr_bitfield_default },
+	 { "PIPE2", 16, 23, &umr_bitfield_default },
+	 { "PIPE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_CS1[] = {
+	 { "PIPE0", 0, 7, &umr_bitfield_default },
+	 { "PIPE1", 8, 15, &umr_bitfield_default },
+	 { "PIPE2", 16, 23, &umr_bitfield_default },
+	 { "PIPE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_GFX[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+	 { "LS_GRP_VALUE", 7, 11, &umr_bitfield_default },
+	 { "HS_GRP_VALUE", 12, 16, &umr_bitfield_default },
+	 { "ES_GRP_VALUE", 17, 21, &umr_bitfield_default },
+	 { "GS_GRP_VALUE", 22, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_HP3D[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+	 { "LS_GRP_VALUE", 7, 11, &umr_bitfield_default },
+	 { "HS_GRP_VALUE", 12, 16, &umr_bitfield_default },
+	 { "ES_GRP_VALUE", 17, 21, &umr_bitfield_default },
+	 { "GS_GRP_VALUE", 22, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS0[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS1[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS2[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS3[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS4[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS5[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS6[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS7[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_WAVE_CNTL[] = {
+	 { "STALL_RA", 0, 0, &umr_bitfield_default },
+	 { "STALL_VMID", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_CONFIG[] = {
+	 { "ME_SEL", 0, 1, &umr_bitfield_default },
+	 { "PIPE_SEL", 2, 3, &umr_bitfield_default },
+	 { "QUEUE_SEL", 4, 6, &umr_bitfield_default },
+	 { "ME_MATCH", 7, 7, &umr_bitfield_default },
+	 { "PIPE_MATCH", 8, 8, &umr_bitfield_default },
+	 { "QUEUE_MATCH", 9, 9, &umr_bitfield_default },
+	 { "TRAP_EN", 15, 15, &umr_bitfield_default },
+	 { "VMID_SEL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_MASK[] = {
+	 { "EXCP_EN", 0, 8, &umr_bitfield_default },
+	 { "REPLACE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_DATA0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_DATA1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESET_DEBUG[] = {
+	 { "DISABLE_GFX_RESET", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_PER_VMID", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_ALL_VMID", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_RESOURCE", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_PRIORITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_COMPUTE_QUEUE_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_0[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_1[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_2[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_3[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_4[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_5[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_6[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_7[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_8[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_9[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_0[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_1[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_2[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_3[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_4[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_5[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_6[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_7[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_8[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_9[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_10[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_11[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_10[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_11[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_12[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_13[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_14[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_15[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_12[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_13[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_14[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_15[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_COMPUTE_WF_CTX_SAVE[] = {
+	 { "INITIATE", 0, 0, &umr_bitfield_default },
+	 { "GDS_INTERRUPT_EN", 1, 1, &umr_bitfield_default },
+	 { "DONE_INTERRUPT_EN", 2, 2, &umr_bitfield_default },
+	 { "GDS_REQ_BUSY", 30, 30, &umr_bitfield_default },
+	 { "SAVE_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_ROQ_OFFSETS[] = {
+	 { "IQ_OFFSET", 0, 2, &umr_bitfield_default },
+	 { "PQ_OFFSET", 8, 13, &umr_bitfield_default },
+	 { "IB_OFFSET", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_STATUS0[] = {
+	 { "QUEUE_STATE", 0, 4, &umr_bitfield_default },
+	 { "MAPPED_QUEUE", 5, 7, &umr_bitfield_default },
+	 { "QUEUE_AVAILABLE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_BASE_ADDR[] = {
+	 { "BASE_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_BASE_ADDR_HI[] = {
+	 { "BASE_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ACTIVE[] = {
+	 { "ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "BUSY_GATE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "IB_VMID", 8, 11, &umr_bitfield_default },
+	 { "VQID", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PERSISTENT_STATE[] = {
+	 { "PRELOAD_REQ", 0, 0, &umr_bitfield_default },
+	 { "PRELOAD_SIZE", 8, 17, &umr_bitfield_default },
+	 { "RESTORE_ACTIVE", 28, 28, &umr_bitfield_default },
+	 { "RELAUNCH_WAVES", 29, 29, &umr_bitfield_default },
+	 { "QSWITCH_MODE", 30, 30, &umr_bitfield_default },
+	 { "DISP_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PIPE_PRIORITY[] = {
+	 { "PIPE_PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_QUEUE_PRIORITY[] = {
+	 { "PRIORITY_LEVEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_QUANTUM[] = {
+	 { "QUANTUM_EN", 0, 0, &umr_bitfield_default },
+	 { "QUANTUM_SCALE", 4, 4, &umr_bitfield_default },
+	 { "QUANTUM_DURATION", 8, 13, &umr_bitfield_default },
+	 { "QUANTUM_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_BASE_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR[] = {
+	 { "CONSUMED_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR_REPORT_ADDR[] = {
+	 { "RPTR_REPORT_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[] = {
+	 { "RPTR_REPORT_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR_POLL_ADDR[] = {
+	 { "WPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[] = {
+	 { "WPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_DOORBELL_CONTROL[] = {
+	 { "DOORBELL_MODE", 0, 0, &umr_bitfield_default },
+	 { "DOORBELL_BIF_DROP", 1, 1, &umr_bitfield_default },
+	 { "DOORBELL_OFFSET", 2, 22, &umr_bitfield_default },
+	 { "DOORBELL_CARRY_BITS", 23, 25, &umr_bitfield_default },
+	 { "DOORBELL_SOURCE", 28, 28, &umr_bitfield_default },
+	 { "DOORBELL_SCHD_HIT", 29, 29, &umr_bitfield_default },
+	 { "DOORBELL_EN", 30, 30, &umr_bitfield_default },
+	 { "DOORBELL_HIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_CONTROL[] = {
+	 { "QUEUE_SIZE", 0, 5, &umr_bitfield_default },
+	 { "RPTR_BLOCK_SIZE", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "ENDIAN_SWAP", 17, 18, &umr_bitfield_default },
+	 { "MIN_AVAIL_SIZE", 20, 21, &umr_bitfield_default },
+	 { "PQ_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "SLOT_BASED_WPTR", 25, 26, &umr_bitfield_default },
+	 { "NO_UPDATE_RPTR", 27, 27, &umr_bitfield_default },
+	 { "UNORD_DISPATCH", 28, 28, &umr_bitfield_default },
+	 { "ROQ_PQ_IB_FLIP", 29, 29, &umr_bitfield_default },
+	 { "PRIV_STATE", 30, 30, &umr_bitfield_default },
+	 { "KMD_QUEUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_BASE_ADDR[] = {
+	 { "IB_BASE_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_BASE_ADDR_HI[] = {
+	 { "IB_BASE_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_RPTR[] = {
+	 { "CONSUMED_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_CONTROL[] = {
+	 { "IB_SIZE", 0, 19, &umr_bitfield_default },
+	 { "MIN_IB_AVAIL_SIZE", 20, 21, &umr_bitfield_default },
+	 { "IB_ATC", 23, 23, &umr_bitfield_default },
+	 { "IB_CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+	 { "PROCESSING_IB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IQ_TIMER[] = {
+	 { "WAIT_TIME", 0, 7, &umr_bitfield_default },
+	 { "RETRY_TYPE", 8, 10, &umr_bitfield_default },
+	 { "IMMEDIATE_EXPIRE", 11, 11, &umr_bitfield_default },
+	 { "INTERRUPT_TYPE", 12, 13, &umr_bitfield_default },
+	 { "CLOCK_COUNT", 14, 15, &umr_bitfield_default },
+	 { "INTERRUPT_SIZE", 16, 21, &umr_bitfield_default },
+	 { "QUANTUM_TIMER", 22, 22, &umr_bitfield_default },
+	 { "IQ_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+	 { "PROCESS_IQ_EN", 29, 29, &umr_bitfield_default },
+	 { "PROCESSING_IQ", 30, 30, &umr_bitfield_default },
+	 { "ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IQ_RPTR[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_DEQUEUE_REQUEST[] = {
+	 { "DEQUEUE_REQ", 0, 2, &umr_bitfield_default },
+	 { "IQ_REQ_PEND", 4, 4, &umr_bitfield_default },
+	 { "DEQUEUE_INT", 8, 8, &umr_bitfield_default },
+	 { "IQ_REQ_PEND_EN", 9, 9, &umr_bitfield_default },
+	 { "DEQUEUE_REQ_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_DMA_OFFLOAD[] = {
+	 { "DMA_OFFLOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_OFFLOAD[] = {
+	 { "DMA_OFFLOAD", 0, 0, &umr_bitfield_default },
+	 { "DMA_OFFLOAD_EN", 1, 1, &umr_bitfield_default },
+	 { "EOP_OFFLOAD", 4, 4, &umr_bitfield_default },
+	 { "EOP_OFFLOAD_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_SEMA_CMD[] = {
+	 { "RETRY", 0, 0, &umr_bitfield_default },
+	 { "RESULT", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_MSG_TYPE[] = {
+	 { "ACTION", 0, 2, &umr_bitfield_default },
+	 { "SAVE_STATE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC0_PREOP_LO[] = {
+	 { "ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC0_PREOP_HI[] = {
+	 { "ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC1_PREOP_LO[] = {
+	 { "ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC1_PREOP_HI[] = {
+	 { "ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_SCHEDULER0[] = {
+	 { "SCHEDULER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_STATUS0[] = {
+	 { "DEQUEUE_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DEQUEUE_RETRY_CNT", 2, 3, &umr_bitfield_default },
+	 { "RSV_6_4", 4, 6, &umr_bitfield_default },
+	 { "SCRATCH_RAM_INIT", 7, 7, &umr_bitfield_default },
+	 { "TCL2_DIRTY", 8, 8, &umr_bitfield_default },
+	 { "PG_ACTIVATED", 9, 9, &umr_bitfield_default },
+	 { "RSVR_31_10", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_SCHEDULER1[] = {
+	 { "SCHEDULER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_CONTROL0[] = {
+	 { "CONTROL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_CONTROL[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "PROCESSING_MQD", 12, 12, &umr_bitfield_default },
+	 { "PROCESSING_MQD_EN", 13, 13, &umr_bitfield_default },
+	 { "MQD_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_STATUS1[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_CONTROL1[] = {
+	 { "CONTROL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_BASE_ADDR[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_BASE_ADDR_HI[] = {
+	 { "BASE_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_CONTROL[] = {
+	 { "EOP_SIZE", 0, 5, &umr_bitfield_default },
+	 { "PROCESSING_EOP", 8, 8, &umr_bitfield_default },
+	 { "PROCESS_EOP_EN", 12, 12, &umr_bitfield_default },
+	 { "PROCESSING_EOPIB", 13, 13, &umr_bitfield_default },
+	 { "PROCESS_EOPIB_EN", 14, 14, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "EOP_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "SIG_SEM_RESULT", 29, 30, &umr_bitfield_default },
+	 { "PEND_SIG_SEM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_RPTR[] = {
+	 { "RPTR", 0, 12, &umr_bitfield_default },
+	 { "RPTR_EQ_CSMD_WPTR", 30, 30, &umr_bitfield_default },
+	 { "INIT_FETCHER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_WPTR[] = {
+	 { "WPTR", 0, 12, &umr_bitfield_default },
+	 { "EOP_AVAIL", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_EVENTS[] = {
+	 { "EVENT_COUNT", 0, 11, &umr_bitfield_default },
+	 { "CS_PARTIAL_FLUSH_PEND", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[] = {
+	 { "ADDR", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CTX_SAVE_CONTROL[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "MTYPE", 1, 2, &umr_bitfield_default },
+	 { "POLICY", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CNTL_STACK_OFFSET[] = {
+	 { "OFFSET", 2, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CNTL_STACK_SIZE[] = {
+	 { "SIZE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_WG_STATE_OFFSET[] = {
+	 { "OFFSET", 2, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CTX_SAVE_SIZE[] = {
+	 { "SIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_GDS_RESOURCE_STATE[] = {
+	 { "OA_REQUIRED", 0, 0, &umr_bitfield_default },
+	 { "OA_ACQUIRED", 1, 1, &umr_bitfield_default },
+	 { "GWS_SIZE", 4, 9, &umr_bitfield_default },
+	 { "GWS_PNTR", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ERROR[] = {
+	 { "EDC_ERROR_ID", 0, 3, &umr_bitfield_default },
+	 { "SUA_ERROR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_WPTR_MEM[] = {
+	 { "WPTR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_DONES[] = {
+	 { "DONE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIDT_IND_INDEX[] = {
+	 { "DIDT_IND_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIDT_IND_DATA[] = {
+	 { "DIDT_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_GATCL1_CNTL[] = {
+	 { "INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default },
+	 { "FORCE_MISS", 26, 26, &umr_bitfield_default },
+	 { "FORCE_IN_ORDER", 27, 27, &umr_bitfield_default },
+	 { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default },
+	 { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_ATC_EDC_GATCL1_CNT[] = {
+	 { "DATA_SEC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_GATCL1_DSM_CNTL[] = {
+	 { "SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0", 0, 0, &umr_bitfield_default },
+	 { "SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1", 1, 1, &umr_bitfield_default },
+	 { "TCP_GATCL1_ENABLE_SINGLE_WRITE_A", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_DSM_CNTL[] = {
+	 { "CACHE_RAM_IRRITATOR_DATA_SEL", 0, 1, &umr_bitfield_default },
+	 { "CACHE_RAM_IRRITATOR_SINGLE_WRITE", 2, 2, &umr_bitfield_default },
+	 { "LFIFO_RAM_IRRITATOR_DATA_SEL", 3, 4, &umr_bitfield_default },
+	 { "LFIFO_RAM_IRRITATOR_SINGLE_WRITE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CNTL2[] = {
+	 { "LS_DISABLE_CLOCKS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID0_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID0_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID1_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID1_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID2_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID2_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID3_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID3_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID4_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID4_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID5_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID5_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID6_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID6_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID7_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID7_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID8_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID8_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID9_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID9_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID10_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID10_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID11_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID11_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID12_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID12_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID13_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID13_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID14_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID14_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID15_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID15_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID0[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID1[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID2[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID3[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID4[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID5[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID6[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID7[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID8[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID9[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID10[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID11[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID12[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID13[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID14[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID15[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID0[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID1[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID2[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID3[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID4[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID5[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID6[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID7[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID8[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID9[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID10[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID11[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID12[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID13[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID14[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID15[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESET0[] = {
+	 { "RESOURCE0_RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE1_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESOURCE2_RESET", 2, 2, &umr_bitfield_default },
+	 { "RESOURCE3_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESOURCE4_RESET", 4, 4, &umr_bitfield_default },
+	 { "RESOURCE5_RESET", 5, 5, &umr_bitfield_default },
+	 { "RESOURCE6_RESET", 6, 6, &umr_bitfield_default },
+	 { "RESOURCE7_RESET", 7, 7, &umr_bitfield_default },
+	 { "RESOURCE8_RESET", 8, 8, &umr_bitfield_default },
+	 { "RESOURCE9_RESET", 9, 9, &umr_bitfield_default },
+	 { "RESOURCE10_RESET", 10, 10, &umr_bitfield_default },
+	 { "RESOURCE11_RESET", 11, 11, &umr_bitfield_default },
+	 { "RESOURCE12_RESET", 12, 12, &umr_bitfield_default },
+	 { "RESOURCE13_RESET", 13, 13, &umr_bitfield_default },
+	 { "RESOURCE14_RESET", 14, 14, &umr_bitfield_default },
+	 { "RESOURCE15_RESET", 15, 15, &umr_bitfield_default },
+	 { "RESOURCE16_RESET", 16, 16, &umr_bitfield_default },
+	 { "RESOURCE17_RESET", 17, 17, &umr_bitfield_default },
+	 { "RESOURCE18_RESET", 18, 18, &umr_bitfield_default },
+	 { "RESOURCE19_RESET", 19, 19, &umr_bitfield_default },
+	 { "RESOURCE20_RESET", 20, 20, &umr_bitfield_default },
+	 { "RESOURCE21_RESET", 21, 21, &umr_bitfield_default },
+	 { "RESOURCE22_RESET", 22, 22, &umr_bitfield_default },
+	 { "RESOURCE23_RESET", 23, 23, &umr_bitfield_default },
+	 { "RESOURCE24_RESET", 24, 24, &umr_bitfield_default },
+	 { "RESOURCE25_RESET", 25, 25, &umr_bitfield_default },
+	 { "RESOURCE26_RESET", 26, 26, &umr_bitfield_default },
+	 { "RESOURCE27_RESET", 27, 27, &umr_bitfield_default },
+	 { "RESOURCE28_RESET", 28, 28, &umr_bitfield_default },
+	 { "RESOURCE29_RESET", 29, 29, &umr_bitfield_default },
+	 { "RESOURCE30_RESET", 30, 30, &umr_bitfield_default },
+	 { "RESOURCE31_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESET1[] = {
+	 { "RESOURCE32_RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE33_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESOURCE34_RESET", 2, 2, &umr_bitfield_default },
+	 { "RESOURCE35_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESOURCE36_RESET", 4, 4, &umr_bitfield_default },
+	 { "RESOURCE37_RESET", 5, 5, &umr_bitfield_default },
+	 { "RESOURCE38_RESET", 6, 6, &umr_bitfield_default },
+	 { "RESOURCE39_RESET", 7, 7, &umr_bitfield_default },
+	 { "RESOURCE40_RESET", 8, 8, &umr_bitfield_default },
+	 { "RESOURCE41_RESET", 9, 9, &umr_bitfield_default },
+	 { "RESOURCE42_RESET", 10, 10, &umr_bitfield_default },
+	 { "RESOURCE43_RESET", 11, 11, &umr_bitfield_default },
+	 { "RESOURCE44_RESET", 12, 12, &umr_bitfield_default },
+	 { "RESOURCE45_RESET", 13, 13, &umr_bitfield_default },
+	 { "RESOURCE46_RESET", 14, 14, &umr_bitfield_default },
+	 { "RESOURCE47_RESET", 15, 15, &umr_bitfield_default },
+	 { "RESOURCE48_RESET", 16, 16, &umr_bitfield_default },
+	 { "RESOURCE49_RESET", 17, 17, &umr_bitfield_default },
+	 { "RESOURCE50_RESET", 18, 18, &umr_bitfield_default },
+	 { "RESOURCE51_RESET", 19, 19, &umr_bitfield_default },
+	 { "RESOURCE52_RESET", 20, 20, &umr_bitfield_default },
+	 { "RESOURCE53_RESET", 21, 21, &umr_bitfield_default },
+	 { "RESOURCE54_RESET", 22, 22, &umr_bitfield_default },
+	 { "RESOURCE55_RESET", 23, 23, &umr_bitfield_default },
+	 { "RESOURCE56_RESET", 24, 24, &umr_bitfield_default },
+	 { "RESOURCE57_RESET", 25, 25, &umr_bitfield_default },
+	 { "RESOURCE58_RESET", 26, 26, &umr_bitfield_default },
+	 { "RESOURCE59_RESET", 27, 27, &umr_bitfield_default },
+	 { "RESOURCE60_RESET", 28, 28, &umr_bitfield_default },
+	 { "RESOURCE61_RESET", 29, 29, &umr_bitfield_default },
+	 { "RESOURCE62_RESET", 30, 30, &umr_bitfield_default },
+	 { "RESOURCE63_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_COMPUTE_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RESET_MASK[] = {
+	 { "ME0_GFXHP3D_PIX_RESET", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_RESET", 1, 1, &umr_bitfield_default },
+	 { "ME0_CS_RESET", 2, 2, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "ME1_PIPE0_RESET", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_RESET", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_RESET", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_RESET", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_RESET", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_RESET", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_RESET", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_RESET", 11, 11, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "PIPE_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ENHANCE[] = {
+	 { "MISC", 0, 15, &umr_bitfield_default },
+	 { "AUTO_INC_INDEX", 16, 16, &umr_bitfield_default },
+	 { "CGPG_RESTORE", 17, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_CGPG_RESTORE[] = {
+	 { "VMID", 0, 7, &umr_bitfield_default },
+	 { "MEID", 8, 11, &umr_bitfield_default },
+	 { "PIPEID", 12, 15, &umr_bitfield_default },
+	 { "QUEUEID", 16, 19, &umr_bitfield_default },
+	 { "UNUSED", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_STATUS[] = {
+	 { "R", 0, 0, &umr_bitfield_default },
+	 { "W", 1, 1, &umr_bitfield_default },
+	 { "UNUSED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GFX_CTXSW_STATUS[] = {
+	 { "R", 0, 0, &umr_bitfield_default },
+	 { "W", 1, 1, &umr_bitfield_default },
+	 { "UNUSED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VS_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VS_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VS_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VS_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS0_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS0_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS0_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS0_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS1_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS1_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS1_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS1_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS2_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS2_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS2_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS2_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS3_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS3_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS3_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS3_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS4_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS4_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS4_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS4_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS5_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS5_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS5_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS5_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS6_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS6_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS6_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS6_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS7_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS7_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS7_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS7_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SIGNATURE_CONTROL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SIGNATURE_MASK[] = {
+	 { "INPUT_BUS_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_DB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_PA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_VGT_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SQ_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE4[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE5[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE6[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE7[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_IA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_IA_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SPI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SPI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TD_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_CB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_BCI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_BCI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TA_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG04[] = {
+	 { "clipsm0_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG4[] = {
+	 { "gws_busy", 0, 0, &umr_bitfield_default },
+	 { "gws_req", 1, 1, &umr_bitfield_default },
+	 { "gws_out_stall", 2, 2, &umr_bitfield_default },
+	 { "cur_reso", 3, 8, &umr_bitfield_default },
+	 { "cur_reso_head_valid", 9, 9, &umr_bitfield_default },
+	 { "cur_reso_head_dirty", 10, 10, &umr_bitfield_default },
+	 { "cur_reso_head_flag", 11, 11, &umr_bitfield_default },
+	 { "cur_reso_fed", 12, 12, &umr_bitfield_default },
+	 { "cur_reso_barrier", 13, 13, &umr_bitfield_default },
+	 { "cur_reso_flag", 14, 14, &umr_bitfield_default },
+	 { "cur_reso_cnt_gt0", 15, 15, &umr_bitfield_default },
+	 { "credit_cnt_gt0", 16, 16, &umr_bitfield_default },
+	 { "cmd_write", 17, 17, &umr_bitfield_default },
+	 { "grbm_gws_reso_wr", 18, 18, &umr_bitfield_default },
+	 { "grbm_gws_reso_rd", 19, 19, &umr_bitfield_default },
+	 { "ram_read_busy", 20, 20, &umr_bitfield_default },
+	 { "gws_bulkfree", 21, 21, &umr_bitfield_default },
+	 { "ram_gws_re", 22, 22, &umr_bitfield_default },
+	 { "ram_gws_we", 23, 23, &umr_bitfield_default },
+	 { "spare", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG4[] = {
+	 { "rbiu_spl_di_valid", 0, 0, &umr_bitfield_default },
+	 { "spl_rbiu_di_read", 1, 1, &umr_bitfield_default },
+	 { "rbiu_spl_p1_di_valid", 2, 2, &umr_bitfield_default },
+	 { "spl_rbiu_p1_di_read", 3, 3, &umr_bitfield_default },
+	 { "pipe0_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe0_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipe1_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe1_rtr", 7, 7, &umr_bitfield_default },
+	 { "pipe2_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe2_rtr", 9, 9, &umr_bitfield_default },
+	 { "pipe3_ld", 10, 10, &umr_bitfield_default },
+	 { "pipe3_rtr", 11, 11, &umr_bitfield_default },
+	 { "WD_IA_draw_send_d", 12, 12, &umr_bitfield_default },
+	 { "WD_IA_draw_rtr", 13, 13, &umr_bitfield_default },
+	 { "di_type_p0", 14, 15, &umr_bitfield_default },
+	 { "di_state_sel_p1_q", 16, 18, &umr_bitfield_default },
+	 { "di_wd_switch_on_eop_p1_q", 19, 19, &umr_bitfield_default },
+	 { "rbiu_spl_pipe0_lockout", 20, 20, &umr_bitfield_default },
+	 { "last_inst_of_di_p2", 21, 21, &umr_bitfield_default },
+	 { "last_sd_of_inst_p2", 22, 22, &umr_bitfield_default },
+	 { "last_sd_of_di_p2", 23, 23, &umr_bitfield_default },
+	 { "not_eop_wait_p1_q", 24, 24, &umr_bitfield_default },
+	 { "not_eop_wait_q", 25, 25, &umr_bitfield_default },
+	 { "ext_event_wait_p1_q", 26, 26, &umr_bitfield_default },
+	 { "ext_event_wait_q", 27, 27, &umr_bitfield_default },
+	 { "WD_IA1_draw_send_d", 28, 28, &umr_bitfield_default },
+	 { "WD_IA1_draw_rtr", 29, 29, &umr_bitfield_default },
+	 { "send_to_ia1_q", 30, 30, &umr_bitfield_default },
+	 { "dual_ia_mode", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "DIDT_MAX_STALLS_ALLOWED_HI", 6, 11, &umr_bitfield_default },
+	 { "DIDT_MAX_STALLS_ALLOWED_LO", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "UNUSED_0", 14, 15, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "UNUSED_1", 26, 26, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "UNUSED_2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG05[] = {
+	 { "clipsm1_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG5[] = {
+	 { "write_dis", 0, 0, &umr_bitfield_default },
+	 { "dec_error", 1, 1, &umr_bitfield_default },
+	 { "alloc_opco_error", 2, 2, &umr_bitfield_default },
+	 { "dealloc_opco_error", 3, 3, &umr_bitfield_default },
+	 { "wrap_opco_error", 4, 4, &umr_bitfield_default },
+	 { "spare", 5, 7, &umr_bitfield_default },
+	 { "error_ds_address", 8, 21, &umr_bitfield_default },
+	 { "spare1", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG5[] = {
+	 { "p1_rbiu_spl_dr_valid", 0, 0, &umr_bitfield_default },
+	 { "SPARE0", 1, 1, &umr_bitfield_default },
+	 { "p1_pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "p1_pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "p1_pipe1_dr", 4, 4, &umr_bitfield_default },
+	 { "p1_pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "p1_wd_subdma_fifo_empty", 6, 6, &umr_bitfield_default },
+	 { "p1_wd_subdma_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "p1_dma_buf_type_p0_q", 8, 9, &umr_bitfield_default },
+	 { "p1_dma_zero_indices_p0_q", 10, 10, &umr_bitfield_default },
+	 { "p1_dma_req_path_p3_q", 11, 11, &umr_bitfield_default },
+	 { "p1_dma_not_eop_p1_q", 12, 12, &umr_bitfield_default },
+	 { "p1_out_of_range_p4", 13, 13, &umr_bitfield_default },
+	 { "p1_last_sub_dma_p3_q", 14, 14, &umr_bitfield_default },
+	 { "p1_last_rdreq_of_sub_dma_p4", 15, 15, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_send_d", 16, 16, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_rtr", 17, 17, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_send_d", 18, 18, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_rtr", 19, 19, &umr_bitfield_default },
+	 { "p1_last_inst_of_dma_p2", 20, 20, &umr_bitfield_default },
+	 { "p1_last_sd_of_inst_p2", 21, 21, &umr_bitfield_default },
+	 { "p1_last_sd_of_dma_p2", 22, 22, &umr_bitfield_default },
+	 { "SPARE1", 23, 23, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_busy", 24, 24, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_busy", 25, 25, &umr_bitfield_default },
+	 { "p1_send_to_ia1_p3_q", 26, 26, &umr_bitfield_default },
+	 { "p1_dma_wd_switch_on_eop_p3_q", 27, 27, &umr_bitfield_default },
+	 { "p1_pipe3_dr", 28, 28, &umr_bitfield_default },
+	 { "p1_pipe3_rtr", 29, 29, &umr_bitfield_default },
+	 { "p1_wd_dma2draw_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "p1_wd_dma2draw_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG06[] = {
+	 { "clipsm1_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG6[] = {
+	 { "oa_busy", 0, 0, &umr_bitfield_default },
+	 { "counters_enabled", 1, 4, &umr_bitfield_default },
+	 { "counters_busy", 5, 20, &umr_bitfield_default },
+	 { "spare", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG6[] = {
+	 { "WD_IA_draw_eop", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "DIDT_MAX_STALLS_ALLOWED_HI", 6, 11, &umr_bitfield_default },
+	 { "DIDT_MAX_STALLS_ALLOWED_LO", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "UNUSED_0", 14, 15, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "UNUSED_1", 26, 26, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "UNUSED_2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG07[] = {
+	 { "clipsm2_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG18[] = {
+	 { "grp_vr_valid", 0, 0, &umr_bitfield_default },
+	 { "pipe0_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "vr_grp_read", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "out_vr_indx_read", 6, 6, &umr_bitfield_default },
+	 { "out_vr_prim_read", 7, 7, &umr_bitfield_default },
+	 { "indices_to_send_q", 8, 10, &umr_bitfield_default },
+	 { "valid_indices", 11, 11, &umr_bitfield_default },
+	 { "last_indx_of_prim", 12, 12, &umr_bitfield_default },
+	 { "indx0_new_d", 13, 13, &umr_bitfield_default },
+	 { "indx1_new_d", 14, 14, &umr_bitfield_default },
+	 { "indx2_new_d", 15, 15, &umr_bitfield_default },
+	 { "indx2_hit_d", 16, 16, &umr_bitfield_default },
+	 { "indx1_hit_d", 17, 17, &umr_bitfield_default },
+	 { "indx0_hit_d", 18, 18, &umr_bitfield_default },
+	 { "st_vertex_reuse_off_r0_q", 19, 19, &umr_bitfield_default },
+	 { "last_group_of_instance_r0_q", 20, 20, &umr_bitfield_default },
+	 { "null_primitive_r0_q", 21, 21, &umr_bitfield_default },
+	 { "eop_r0_q", 22, 22, &umr_bitfield_default },
+	 { "eject_vtx_vect_r1_d", 23, 23, &umr_bitfield_default },
+	 { "sub_prim_type_r0_q", 24, 26, &umr_bitfield_default },
+	 { "gs_scenario_a_r0_q", 27, 27, &umr_bitfield_default },
+	 { "gs_scenario_b_r0_q", 28, 28, &umr_bitfield_default },
+	 { "components_valid_r0_q", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG7[] = {
+	 { "SE0VGT_WD_thdgrp_send_in", 0, 0, &umr_bitfield_default },
+	 { "wd_arb_se0_input_fifo_re", 1, 1, &umr_bitfield_default },
+	 { "wd_arb_se0_input_fifo_empty", 2, 2, &umr_bitfield_default },
+	 { "wd_arb_se0_input_fifo_full", 3, 3, &umr_bitfield_default },
+	 { "SPARE0", 4, 7, &umr_bitfield_default },
+	 { "SPARE1", 8, 11, &umr_bitfield_default },
+	 { "SPARE2", 12, 15, &umr_bitfield_default },
+	 { "SPARE3", 16, 19, &umr_bitfield_default },
+	 { "se0_thdgrp_is_event", 20, 20, &umr_bitfield_default },
+	 { "se0_thdgrp_eop", 21, 21, &umr_bitfield_default },
+	 { "SPARE4", 22, 27, &umr_bitfield_default },
+	 { "tfreq_arb_tgroup_rtr", 28, 28, &umr_bitfield_default },
+	 { "arb_tfreq_tgroup_rts", 29, 29, &umr_bitfield_default },
+	 { "arb_tfreq_tgroup_event", 30, 30, &umr_bitfield_default },
+	 { "te11_arb_busy", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG08[] = {
+	 { "clipsm2_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_DEBUG_STS_LOCAL[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "WAVE_LEVEL", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG8[] = {
+	 { "rcm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "rcm_noif_busy_q", 1, 1, &umr_bitfield_default },
+	 { "r1_inst_rtr", 2, 2, &umr_bitfield_default },
+	 { "spi_gsprim_fifo_busy_q", 3, 3, &umr_bitfield_default },
+	 { "spi_esvert_fifo_busy_q", 4, 4, &umr_bitfield_default },
+	 { "gs_tbl_valid_r3_q", 5, 5, &umr_bitfield_default },
+	 { "valid_r0_q", 6, 6, &umr_bitfield_default },
+	 { "valid_r1_q", 7, 7, &umr_bitfield_default },
+	 { "valid_r2", 8, 8, &umr_bitfield_default },
+	 { "valid_r2_q", 9, 9, &umr_bitfield_default },
+	 { "r0_rtr", 10, 10, &umr_bitfield_default },
+	 { "r1_rtr", 11, 11, &umr_bitfield_default },
+	 { "r2_indx_rtr", 12, 12, &umr_bitfield_default },
+	 { "r2_rtr", 13, 13, &umr_bitfield_default },
+	 { "es_gs_rtr", 14, 14, &umr_bitfield_default },
+	 { "gs_event_fifo_rtr", 15, 15, &umr_bitfield_default },
+	 { "tm_rcm_gs_event_rtr", 16, 16, &umr_bitfield_default },
+	 { "gs_tbl_r3_rtr", 17, 17, &umr_bitfield_default },
+	 { "prim_skid_fifo_empty", 18, 18, &umr_bitfield_default },
+	 { "VGT_SPI_gsprim_rtr_q", 19, 19, &umr_bitfield_default },
+	 { "tm_rcm_gs_tbl_rtr", 20, 20, &umr_bitfield_default },
+	 { "tm_rcm_es_tbl_rtr", 21, 21, &umr_bitfield_default },
+	 { "VGT_SPI_esvert_rtr_q", 22, 22, &umr_bitfield_default },
+	 { "r2_no_bp_rtr", 23, 23, &umr_bitfield_default },
+	 { "hold_for_es_flush", 24, 24, &umr_bitfield_default },
+	 { "gs_event_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "gsprim_buff_empty_q", 26, 26, &umr_bitfield_default },
+	 { "gsprim_buff_full_q", 27, 27, &umr_bitfield_default },
+	 { "te_prim_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "te_prim_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "te_vert_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "te_vert_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG8[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe1_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe0_rtr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_rtr", 3, 3, &umr_bitfield_default },
+	 { "tfreq_tg_fifo_empty", 4, 4, &umr_bitfield_default },
+	 { "tfreq_tg_fifo_full", 5, 5, &umr_bitfield_default },
+	 { "tf_data_fifo_busy_q", 6, 6, &umr_bitfield_default },
+	 { "tf_data_fifo_rtr_q", 7, 7, &umr_bitfield_default },
+	 { "tf_skid_fifo_empty", 8, 8, &umr_bitfield_default },
+	 { "tf_skid_fifo_full", 9, 9, &umr_bitfield_default },
+	 { "wd_tc_rdreq_rtr_q", 10, 10, &umr_bitfield_default },
+	 { "last_req_of_tg_p2", 11, 11, &umr_bitfield_default },
+	 { "se0spi_wd_hs_done_cnt_q", 12, 17, &umr_bitfield_default },
+	 { "event_flag_p1_q", 18, 18, &umr_bitfield_default },
+	 { "null_flag_p1_q", 19, 19, &umr_bitfield_default },
+	 { "tf_data_fifo_cnt_q", 20, 26, &umr_bitfield_default },
+	 { "second_tf_ret_data_q", 27, 27, &umr_bitfield_default },
+	 { "first_req_of_tg_p1_q", 28, 28, &umr_bitfield_default },
+	 { "WD_TC_rdreq_send_out", 29, 29, &umr_bitfield_default },
+	 { "WD_TC_rdnfo_stall_out", 30, 30, &umr_bitfield_default },
+	 { "TC_WD_rdret_valid_in", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "UNUSED_0", 14, 15, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "UNUSED_1", 26, 26, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "UNUSED_2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG09[] = {
+	 { "clipsm3_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG9[] = {
+	 { "indices_to_send_r2_q", 0, 1, &umr_bitfield_default },
+	 { "valid_indices_r3", 2, 2, &umr_bitfield_default },
+	 { "gs_eov_r3", 3, 3, &umr_bitfield_default },
+	 { "eop_indx_r3", 4, 4, &umr_bitfield_default },
+	 { "eop_prim_r3", 5, 5, &umr_bitfield_default },
+	 { "es_eov_r3", 6, 6, &umr_bitfield_default },
+	 { "es_tbl_state_r3_q_0", 7, 7, &umr_bitfield_default },
+	 { "pending_es_send_r3_q", 8, 8, &umr_bitfield_default },
+	 { "pending_es_flush_r3", 9, 9, &umr_bitfield_default },
+	 { "gs_tbl_num_es_per_gs_r3_q_not_0", 10, 10, &umr_bitfield_default },
+	 { "gs_tbl_prim_cnt_r3_q", 11, 17, &umr_bitfield_default },
+	 { "gs_tbl_eop_r3_q", 18, 18, &umr_bitfield_default },
+	 { "gs_tbl_state_r3_q", 19, 21, &umr_bitfield_default },
+	 { "gs_pending_state_r3_q", 22, 22, &umr_bitfield_default },
+	 { "invalidate_rb_roll_over_q", 23, 23, &umr_bitfield_default },
+	 { "gs_instancing_state_q", 24, 24, &umr_bitfield_default },
+	 { "es_per_gs_vert_cnt_r3_q_not_0", 25, 25, &umr_bitfield_default },
+	 { "gs_prim_per_es_ctr_r3_q_not_0", 26, 26, &umr_bitfield_default },
+	 { "pre_r0_rtr", 27, 27, &umr_bitfield_default },
+	 { "valid_r3_q", 28, 28, &umr_bitfield_default },
+	 { "valid_pre_r0_q", 29, 29, &umr_bitfield_default },
+	 { "SPARE0", 30, 30, &umr_bitfield_default },
+	 { "off_chip_hs_r2_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG9[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipec_tf_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe2_dr", 2, 2, &umr_bitfield_default },
+	 { "event_or_null_flags_p0_q", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipec_tf_rtr", 6, 6, &umr_bitfield_default },
+	 { "pipe2_rtr", 7, 7, &umr_bitfield_default },
+	 { "ttp_patch_fifo_full", 8, 8, &umr_bitfield_default },
+	 { "ttp_patch_fifo_empty", 9, 9, &umr_bitfield_default },
+	 { "ttp_tf_fifo_empty", 10, 10, &umr_bitfield_default },
+	 { "SPARE0", 11, 15, &umr_bitfield_default },
+	 { "tf_fetch_state_q", 16, 18, &umr_bitfield_default },
+	 { "last_patch_of_tg", 19, 19, &umr_bitfield_default },
+	 { "tf_pointer_p0_q", 20, 23, &umr_bitfield_default },
+	 { "dynamic_hs_p0_q", 24, 24, &umr_bitfield_default },
+	 { "first_fetch_of_tg_p0_q", 25, 25, &umr_bitfield_default },
+	 { "mem_is_even", 26, 26, &umr_bitfield_default },
+	 { "SPARE1", 27, 27, &umr_bitfield_default },
+	 { "SPARE2", 28, 29, &umr_bitfield_default },
+	 { "pipe4_dr", 30, 30, &umr_bitfield_default },
+	 { "pipe4_rtr", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG10[] = {
+	 { "clipsm3_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG10[] = {
+	 { "index_buffer_depth_r1_q", 0, 4, &umr_bitfield_default },
+	 { "eopg_r2_q", 5, 5, &umr_bitfield_default },
+	 { "eotg_r2_q", 6, 6, &umr_bitfield_default },
+	 { "onchip_gs_en_r0_q", 7, 8, &umr_bitfield_default },
+	 { "SPARE2", 9, 10, &umr_bitfield_default },
+	 { "rcm_mem_gsprim_re_qq", 11, 11, &umr_bitfield_default },
+	 { "rcm_mem_gsprim_re_q", 12, 12, &umr_bitfield_default },
+	 { "gs_rb_space_avail_r3_q_9_0", 13, 22, &umr_bitfield_default },
+	 { "es_rb_space_avail_r2_q_8_0", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG10[] = {
+	 { "ttp_pd_patch_rts", 0, 0, &umr_bitfield_default },
+	 { "ttp_pd_is_event", 1, 1, &umr_bitfield_default },
+	 { "ttp_pd_eopg", 2, 2, &umr_bitfield_default },
+	 { "ttp_pd_eop", 3, 3, &umr_bitfield_default },
+	 { "pipe0_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_dr", 5, 5, &umr_bitfield_default },
+	 { "pipe0_rtr", 6, 6, &umr_bitfield_default },
+	 { "pipe1_rtr", 7, 7, &umr_bitfield_default },
+	 { "donut_en_p1_q", 8, 8, &umr_bitfield_default },
+	 { "donut_se_switch_p2", 9, 9, &umr_bitfield_default },
+	 { "patch_se_switch_p2", 10, 10, &umr_bitfield_default },
+	 { "last_donut_switch_p2", 11, 11, &umr_bitfield_default },
+	 { "last_donut_of_patch_p2", 12, 12, &umr_bitfield_default },
+	 { "is_event_p1_q", 13, 13, &umr_bitfield_default },
+	 { "eopg_p1_q", 14, 14, &umr_bitfield_default },
+	 { "eop_p1_q", 15, 15, &umr_bitfield_default },
+	 { "patch_accum_q", 16, 23, &umr_bitfield_default },
+	 { "wd_te11_out_se0_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "wd_te11_out_se0_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "wd_te11_out_se1_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "wd_te11_out_se1_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "wd_te11_out_se2_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "wd_te11_out_se2_fifo_empty", 29, 29, &umr_bitfield_default },
+	 { "wd_te11_out_se3_fifo_full", 30, 30, &umr_bitfield_default },
+	 { "wd_te11_out_se3_fifo_empty", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_CONTROL[] = {
+	 { "DEPTH_CLEAR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCIL_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DEPTH_COPY", 2, 2, &umr_bitfield_default },
+	 { "STENCIL_COPY", 3, 3, &umr_bitfield_default },
+	 { "RESUMMARIZE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STENCIL_COMPRESS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DEPTH_COMPRESS_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "COPY_CENTROID", 7, 7, &umr_bitfield_default },
+	 { "COPY_SAMPLE", 8, 11, &umr_bitfield_default },
+	 { "DECOMPRESS_ENABLE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_COUNT_CONTROL[] = {
+	 { "ZPASS_INCREMENT_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "PERFECT_ZPASS_COUNTS", 1, 1, &umr_bitfield_default },
+	 { "SAMPLE_RATE", 4, 6, &umr_bitfield_default },
+	 { "ZPASS_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "ZFAIL_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "SFAIL_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "DBFAIL_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "SLICE_EVEN_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "Z_READ_ONLY", 24, 24, &umr_bitfield_default },
+	 { "STENCIL_READ_ONLY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_OVERRIDE[] = {
+	 { "FORCE_HIZ_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE0", 2, 3, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE1", 4, 5, &umr_bitfield_default },
+	 { "FORCE_SHADER_Z_ORDER", 6, 6, &umr_bitfield_default },
+	 { "FAST_Z_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "FAST_STENCIL_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "NOOP_CULL_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "FORCE_COLOR_KILL", 10, 10, &umr_bitfield_default },
+	 { "FORCE_Z_READ", 11, 11, &umr_bitfield_default },
+	 { "FORCE_STENCIL_READ", 12, 12, &umr_bitfield_default },
+	 { "FORCE_FULL_Z_RANGE", 13, 14, &umr_bitfield_default },
+	 { "FORCE_QC_SMASK_CONFLICT", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_VIEWPORT_CLAMP", 16, 16, &umr_bitfield_default },
+	 { "IGNORE_SC_ZRANGE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_FULLY_COVERED", 18, 18, &umr_bitfield_default },
+	 { "FORCE_Z_LIMIT_SUMM", 19, 20, &umr_bitfield_default },
+	 { "MAX_TILES_IN_DTT", 21, 25, &umr_bitfield_default },
+	 { "DISABLE_TILE_RATE_TILES", 26, 26, &umr_bitfield_default },
+	 { "FORCE_Z_DIRTY", 27, 27, &umr_bitfield_default },
+	 { "FORCE_STENCIL_DIRTY", 28, 28, &umr_bitfield_default },
+	 { "FORCE_Z_VALID", 29, 29, &umr_bitfield_default },
+	 { "FORCE_STENCIL_VALID", 30, 30, &umr_bitfield_default },
+	 { "PRESERVE_COMPRESSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_OVERRIDE2[] = {
+	 { "PARTIAL_SQUAD_LAUNCH_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "PARTIAL_SQUAD_LAUNCH_COUNTDOWN", 2, 4, &umr_bitfield_default },
+	 { "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_COLOR_ON_VALIDATION", 7, 7, &umr_bitfield_default },
+	 { "DECOMPRESS_Z_ON_FLUSH", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_REG_SNOOP", 9, 9, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_HIER_DEPTH_DISABLE", 10, 10, &umr_bitfield_default },
+	 { "SEPARATE_HIZS_FUNC_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "HIZ_ZFUNC", 12, 14, &umr_bitfield_default },
+	 { "HIS_SFUNC_FF", 15, 17, &umr_bitfield_default },
+	 { "HIS_SFUNC_BF", 18, 20, &umr_bitfield_default },
+	 { "PRESERVE_ZRANGE", 21, 21, &umr_bitfield_default },
+	 { "PRESERVE_SRESULTS", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_FAST_PASS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_HTILE_DATA_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_BOUNDS_MIN[] = {
+	 { "MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_BOUNDS_MAX[] = {
+	 { "MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_CLEAR[] = {
+	 { "CLEAR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_CLEAR[] = {
+	 { "DEPTH_CLEAR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_TL[] = {
+	 { "TL_X", 0, 15, &umr_bitfield_default },
+	 { "TL_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_BR[] = {
+	 { "BR_X", 0, 15, &umr_bitfield_default },
+	 { "BR_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_INFO[] = {
+	 { "ADDR5_SWIZZLE_MASK", 0, 3, &umr_bitfield_default },
+	 { "ARRAY_MODE", 4, 7, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 8, 12, &umr_bitfield_default },
+	 { "BANK_WIDTH", 13, 14, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 15, 16, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 17, 18, &umr_bitfield_default },
+	 { "NUM_BANKS", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_INFO[] = {
+	 { "FORMAT", 0, 1, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 2, 3, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "DECOMPRESS_ON_N_ZPLANES", 23, 26, &umr_bitfield_default },
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "READ_SIZE", 28, 28, &umr_bitfield_default },
+	 { "TILE_SURFACE_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "CLEAR_DISALLOWED", 30, 30, &umr_bitfield_default },
+	 { "ZRANGE_PRECISION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_INFO[] = {
+	 { "FORMAT", 0, 0, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "TILE_STENCIL_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "CLEAR_DISALLOWED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_SIZE[] = {
+	 { "PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "HEIGHT_TILE_MAX", 11, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_SLICE[] = {
+	 { "SLICE_TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_BC_BASE_ADDR_HI[] = {
+	 { "ADDRESS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_0[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_1[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_2[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_3[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_2[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_3[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_OFFSET[] = {
+	 { "WINDOW_X_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "WINDOW_Y_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_RULE[] = {
+	 { "CLIP_RULE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_EDGERULE[] = {
+	 { "ER_TRI", 0, 3, &umr_bitfield_default },
+	 { "ER_POINT", 4, 7, &umr_bitfield_default },
+	 { "ER_RECT", 8, 11, &umr_bitfield_default },
+	 { "ER_LINE_LR", 12, 17, &umr_bitfield_default },
+	 { "ER_LINE_RL", 18, 23, &umr_bitfield_default },
+	 { "ER_LINE_TB", 24, 27, &umr_bitfield_default },
+	 { "ER_LINE_BT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_HARDWARE_SCREEN_OFFSET[] = {
+	 { "HW_SCREEN_OFFSET_X", 0, 8, &umr_bitfield_default },
+	 { "HW_SCREEN_OFFSET_Y", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_TARGET_MASK[] = {
+	 { "TARGET0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "TARGET1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "TARGET2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "TARGET3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "TARGET4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "TARGET5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "TARGET6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "TARGET7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_SHADER_MASK[] = {
+	 { "OUTPUT0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "OUTPUT1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "OUTPUT2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "OUTPUT3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "OUTPUT4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "OUTPUT5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "OUTPUT6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "OUTPUT7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_0[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_1[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_0[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_0[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_1[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_1[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_2[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_2[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_3[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_3[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_4[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_4[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_5[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_5[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_6[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_6[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_7[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_7[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_8[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_8[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_9[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_9[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_10[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_10[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_11[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_11[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_12[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_12[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_13[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_13[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_14[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_14[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_15[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_15[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_RASTER_CONFIG[] = {
+	 { "RB_MAP_PKR0", 0, 1, &umr_bitfield_default },
+	 { "RB_MAP_PKR1", 2, 3, &umr_bitfield_default },
+	 { "RB_XSEL2", 4, 5, &umr_bitfield_default },
+	 { "RB_XSEL", 6, 6, &umr_bitfield_default },
+	 { "RB_YSEL", 7, 7, &umr_bitfield_default },
+	 { "PKR_MAP", 8, 9, &umr_bitfield_default },
+	 { "PKR_XSEL", 10, 11, &umr_bitfield_default },
+	 { "PKR_YSEL", 12, 13, &umr_bitfield_default },
+	 { "PKR_XSEL2", 14, 15, &umr_bitfield_default },
+	 { "SC_MAP", 16, 17, &umr_bitfield_default },
+	 { "SC_XSEL", 18, 19, &umr_bitfield_default },
+	 { "SC_YSEL", 20, 21, &umr_bitfield_default },
+	 { "SE_MAP", 24, 25, &umr_bitfield_default },
+	 { "SE_XSEL", 26, 27, &umr_bitfield_default },
+	 { "SE_YSEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_RASTER_CONFIG_1[] = {
+	 { "SE_PAIR_MAP", 0, 1, &umr_bitfield_default },
+	 { "SE_PAIR_XSEL", 2, 3, &umr_bitfield_default },
+	 { "SE_PAIR_YSEL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_CONTROL[] = {
+	 { "SLICE_EVEN_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PERFMON_CNTX_CNTL[] = {
+	 { "PERFMON_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RINGID[] = {
+	 { "RINGID", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MAX_VTX_INDX[] = {
+	 { "MAX_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MIN_VTX_INDX[] = {
+	 { "MIN_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INDX_OFFSET[] = {
+	 { "INDX_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_INDX[] = {
+	 { "RESET_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_RED[] = {
+	 { "BLEND_RED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_GREEN[] = {
+	 { "BLEND_GREEN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_BLUE[] = {
+	 { "BLEND_BLUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_ALPHA[] = {
+	 { "BLEND_ALPHA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "OVERWRITE_COMBINER_MRT_SHARING_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "OVERWRITE_COMBINER_WATERMARK", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_CONTROL[] = {
+	 { "STENCILFAIL", 0, 3, &umr_bitfield_default },
+	 { "STENCILZPASS", 4, 7, &umr_bitfield_default },
+	 { "STENCILZFAIL", 8, 11, &umr_bitfield_default },
+	 { "STENCILFAIL_BF", 12, 15, &umr_bitfield_default },
+	 { "STENCILZPASS_BF", 16, 19, &umr_bitfield_default },
+	 { "STENCILZFAIL_BF", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCILREFMASK[] = {
+	 { "STENCILTESTVAL", 0, 7, &umr_bitfield_default },
+	 { "STENCILMASK", 8, 15, &umr_bitfield_default },
+	 { "STENCILWRITEMASK", 16, 23, &umr_bitfield_default },
+	 { "STENCILOPVAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCILREFMASK_BF[] = {
+	 { "STENCILTESTVAL_BF", 0, 7, &umr_bitfield_default },
+	 { "STENCILMASK_BF", 8, 15, &umr_bitfield_default },
+	 { "STENCILWRITEMASK_BF", 16, 23, &umr_bitfield_default },
+	 { "STENCILOPVAL_BF", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_1[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_1[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_1[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_1[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_1[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_1[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_2[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_2[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_2[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_2[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_2[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_2[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_3[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_3[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_3[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_3[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_3[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_3[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_4[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_4[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_4[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_4[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_4[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_4[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_5[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_5[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_5[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_5[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_5[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_5[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_6[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_6[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_6[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_6[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_6[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_6[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_7[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_7[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_7[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_7[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_7[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_7[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_8[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_8[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_8[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_8[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_8[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_8[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_9[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_9[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_9[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_9[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_9[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_9[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_10[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_10[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_10[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_10[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_10[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_10[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_11[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_11[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_11[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_11[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_11[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_11[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_12[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_12[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_12[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_12[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_12[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_12[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_13[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_13[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_13[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_13[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_13[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_13[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_14[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_14[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_14[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_14[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_14[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_14[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_15[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_15[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_15[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_15[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_15[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_15[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_0[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_1[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_2[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_3[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_4[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_5[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_6[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_7[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_8[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_9[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_10[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_11[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_12[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_13[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_14[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_15[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_16[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_17[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_18[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_19[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_20[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_21[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_22[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_23[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_24[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_25[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_26[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_27[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_28[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_29[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_30[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_31[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_VS_OUT_CONFIG[] = {
+	 { "VS_EXPORT_COUNT", 1, 5, &umr_bitfield_default },
+	 { "VS_HALF_PACK", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_ENA[] = {
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_ADDR[] = {
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_INTERP_CONTROL_0[] = {
+	 { "FLAT_SHADE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PNT_SPRITE_ENA", 1, 1, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_X", 2, 4, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Y", 5, 7, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Z", 8, 10, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_W", 11, 13, &umr_bitfield_default },
+	 { "PNT_SPRITE_TOP_1", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_IN_CONTROL[] = {
+	 { "NUM_INTERP", 0, 5, &umr_bitfield_default },
+	 { "PARAM_GEN", 6, 6, &umr_bitfield_default },
+	 { "BC_OPTIMIZE_DISABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_BARYC_CNTL[] = {
+	 { "PERSP_CENTER_CNTL", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTROID_CNTL", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_CNTL", 8, 8, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_CNTL", 12, 12, &umr_bitfield_default },
+	 { "POS_FLOAT_LOCATION", 16, 17, &umr_bitfield_default },
+	 { "POS_FLOAT_ULC", 20, 20, &umr_bitfield_default },
+	 { "FRONT_FACE_ALL_BITS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_TMPRING_SIZE[] = {
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_POS_FORMAT[] = {
+	 { "POS0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "POS1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "POS2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "POS3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_Z_FORMAT[] = {
+	 { "Z_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_COL_FORMAT[] = {
+	 { "COL0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "COL1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "COL2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "COL3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+	 { "COL4_EXPORT_FORMAT", 16, 19, &umr_bitfield_default },
+	 { "COL5_EXPORT_FORMAT", 20, 23, &umr_bitfield_default },
+	 { "COL6_EXPORT_FORMAT", 24, 27, &umr_bitfield_default },
+	 { "COL7_EXPORT_FORMAT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND0_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND1_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND2_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND3_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND4_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND5_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND6_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND7_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCS_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_X_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_Y_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_SIZE[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_CULL_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_BASE_HI[] = {
+	 { "BASE_ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_BASE[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DRAW_INITIATOR[] = {
+	 { "SOURCE_SELECT", 0, 1, &umr_bitfield_default },
+	 { "MAJOR_MODE", 2, 3, &umr_bitfield_default },
+	 { "SPRITE_EN_R6XX", 4, 4, &umr_bitfield_default },
+	 { "NOT_EOP", 5, 5, &umr_bitfield_default },
+	 { "USE_OPAQUE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_IMMED_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_EVENT_ADDRESS_REG[] = {
+	 { "ADDRESS_LOW", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_CONTROL[] = {
+	 { "STENCIL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "Z_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "Z_WRITE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "ZFUNC", 4, 6, &umr_bitfield_default },
+	 { "BACKFACE_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "STENCILFUNC", 8, 10, &umr_bitfield_default },
+	 { "STENCILFUNC_BF", 20, 22, &umr_bitfield_default },
+	 { "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_COLOR_WRITES_ON_DEPTH_PASS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_EQAA[] = {
+	 { "MAX_ANCHOR_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLES", 4, 6, &umr_bitfield_default },
+	 { "MASK_EXPORT_NUM_SAMPLES", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "HIGH_QUALITY_INTERSECTIONS", 16, 16, &umr_bitfield_default },
+	 { "INCOHERENT_EQAA_READS", 17, 17, &umr_bitfield_default },
+	 { "INTERPOLATE_COMP_Z", 18, 18, &umr_bitfield_default },
+	 { "INTERPOLATE_SRC_Z", 19, 19, &umr_bitfield_default },
+	 { "STATIC_ANCHOR_ASSOCIATIONS", 20, 20, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_EQAA_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "OVERRASTERIZATION_AMOUNT", 24, 26, &umr_bitfield_default },
+	 { "ENABLE_POSTZ_OVERRASTERIZATION", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR_CONTROL[] = {
+	 { "DEGAMMA_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "ROP3", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SHADER_CONTROL[] = {
+	 { "Z_EXPORT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCIL_TEST_VAL_EXPORT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STENCIL_OP_VAL_EXPORT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "Z_ORDER", 4, 5, &umr_bitfield_default },
+	 { "KILL_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "COVERAGE_TO_MASK_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MASK_EXPORT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "EXEC_ON_HIER_FAIL", 9, 9, &umr_bitfield_default },
+	 { "EXEC_ON_NOOP", 10, 10, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "DEPTH_BEFORE_SHADER", 12, 12, &umr_bitfield_default },
+	 { "CONSERVATIVE_Z_EXPORT", 13, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_CLIP_CNTL[] = {
+	 { "UCP_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "UCP_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "UCP_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "UCP_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "UCP_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "UCP_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "PS_UCP_Y_SCALE_NEG", 13, 13, &umr_bitfield_default },
+	 { "PS_UCP_MODE", 14, 15, &umr_bitfield_default },
+	 { "CLIP_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "UCP_CULL_ONLY_ENA", 17, 17, &umr_bitfield_default },
+	 { "BOUNDARY_EDGE_FLAG_ENA", 18, 18, &umr_bitfield_default },
+	 { "DX_CLIP_SPACE_DEF", 19, 19, &umr_bitfield_default },
+	 { "DIS_CLIP_ERR_DETECT", 20, 20, &umr_bitfield_default },
+	 { "VTX_KILL_OR", 21, 21, &umr_bitfield_default },
+	 { "DX_RASTERIZATION_KILL", 22, 22, &umr_bitfield_default },
+	 { "DX_LINEAR_ATTR_CLIP_ENA", 24, 24, &umr_bitfield_default },
+	 { "VTE_VPORT_PROVOKE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "ZCLIP_NEAR_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "ZCLIP_FAR_DISABLE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_SC_MODE_CNTL[] = {
+	 { "CULL_FRONT", 0, 0, &umr_bitfield_default },
+	 { "CULL_BACK", 1, 1, &umr_bitfield_default },
+	 { "FACE", 2, 2, &umr_bitfield_default },
+	 { "POLY_MODE", 3, 4, &umr_bitfield_default },
+	 { "POLYMODE_FRONT_PTYPE", 5, 7, &umr_bitfield_default },
+	 { "POLYMODE_BACK_PTYPE", 8, 10, &umr_bitfield_default },
+	 { "POLY_OFFSET_FRONT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "POLY_OFFSET_BACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "POLY_OFFSET_PARA_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "VTX_WINDOW_OFFSET_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "PROVOKING_VTX_LAST", 19, 19, &umr_bitfield_default },
+	 { "PERSP_CORR_DIS", 20, 20, &umr_bitfield_default },
+	 { "MULTI_PRIM_IB_ENA", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VTE_CNTL[] = {
+	 { "VPORT_X_SCALE_ENA", 0, 0, &umr_bitfield_default },
+	 { "VPORT_X_OFFSET_ENA", 1, 1, &umr_bitfield_default },
+	 { "VPORT_Y_SCALE_ENA", 2, 2, &umr_bitfield_default },
+	 { "VPORT_Y_OFFSET_ENA", 3, 3, &umr_bitfield_default },
+	 { "VPORT_Z_SCALE_ENA", 4, 4, &umr_bitfield_default },
+	 { "VPORT_Z_OFFSET_ENA", 5, 5, &umr_bitfield_default },
+	 { "VTX_XY_FMT", 8, 8, &umr_bitfield_default },
+	 { "VTX_Z_FMT", 9, 9, &umr_bitfield_default },
+	 { "VTX_W0_FMT", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_REF", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VS_OUT_CNTL[] = {
+	 { "CLIP_DIST_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_6", 6, 6, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_7", 7, 7, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_0", 8, 8, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_1", 9, 9, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_2", 10, 10, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_3", 11, 11, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_4", 12, 12, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_5", 13, 13, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_6", 14, 14, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_7", 15, 15, &umr_bitfield_default },
+	 { "USE_VTX_POINT_SIZE", 16, 16, &umr_bitfield_default },
+	 { "USE_VTX_EDGE_FLAG", 17, 17, &umr_bitfield_default },
+	 { "USE_VTX_RENDER_TARGET_INDX", 18, 18, &umr_bitfield_default },
+	 { "USE_VTX_VIEWPORT_INDX", 19, 19, &umr_bitfield_default },
+	 { "USE_VTX_KILL_FLAG", 20, 20, &umr_bitfield_default },
+	 { "VS_OUT_MISC_VEC_ENA", 21, 21, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST0_VEC_ENA", 22, 22, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST1_VEC_ENA", 23, 23, &umr_bitfield_default },
+	 { "VS_OUT_MISC_SIDE_BUS_ENA", 24, 24, &umr_bitfield_default },
+	 { "USE_VTX_GS_CUT_FLAG", 25, 25, &umr_bitfield_default },
+	 { "USE_VTX_LINE_WIDTH", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_NANINF_CNTL[] = {
+	 { "VTE_XY_INF_DISCARD", 0, 0, &umr_bitfield_default },
+	 { "VTE_Z_INF_DISCARD", 1, 1, &umr_bitfield_default },
+	 { "VTE_W_INF_DISCARD", 2, 2, &umr_bitfield_default },
+	 { "VTE_0XNANINF_IS_0", 3, 3, &umr_bitfield_default },
+	 { "VTE_XY_NAN_RETAIN", 4, 4, &umr_bitfield_default },
+	 { "VTE_Z_NAN_RETAIN", 5, 5, &umr_bitfield_default },
+	 { "VTE_W_NAN_RETAIN", 6, 6, &umr_bitfield_default },
+	 { "VTE_W_RECIP_NAN_IS_0", 7, 7, &umr_bitfield_default },
+	 { "VS_XY_NAN_TO_INF", 8, 8, &umr_bitfield_default },
+	 { "VS_XY_INF_RETAIN", 9, 9, &umr_bitfield_default },
+	 { "VS_Z_NAN_TO_INF", 10, 10, &umr_bitfield_default },
+	 { "VS_Z_INF_RETAIN", 11, 11, &umr_bitfield_default },
+	 { "VS_W_NAN_TO_INF", 12, 12, &umr_bitfield_default },
+	 { "VS_W_INF_RETAIN", 13, 13, &umr_bitfield_default },
+	 { "VS_CLIP_DIST_INF_DISCARD", 14, 14, &umr_bitfield_default },
+	 { "VTE_NO_OUTPUT_NEG_0", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_CNTL[] = {
+	 { "LINE_STIPPLE_RESET", 0, 1, &umr_bitfield_default },
+	 { "EXPAND_FULL_LENGTH", 2, 2, &umr_bitfield_default },
+	 { "FRACTIONAL_ACCUM", 3, 3, &umr_bitfield_default },
+	 { "DIAMOND_ADJUST", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_SCALE[] = {
+	 { "LINE_STIPPLE_SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PRIM_FILTER_CNTL[] = {
+	 { "TRIANGLE_FILTER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "LINE_FILTER_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "POINT_FILTER_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RECTANGLE_FILTER_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "TRIANGLE_EXPAND_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINE_EXPAND_ENA", 5, 5, &umr_bitfield_default },
+	 { "POINT_EXPAND_ENA", 6, 6, &umr_bitfield_default },
+	 { "RECTANGLE_EXPAND_ENA", 7, 7, &umr_bitfield_default },
+	 { "PRIM_EXPAND_CONSTANT", 8, 15, &umr_bitfield_default },
+	 { "XMAX_RIGHT_EXCLUSION", 30, 30, &umr_bitfield_default },
+	 { "YMAX_BOTTOM_EXCLUSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POINT_SIZE[] = {
+	 { "HEIGHT", 0, 15, &umr_bitfield_default },
+	 { "WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POINT_MINMAX[] = {
+	 { "MIN_SIZE", 0, 15, &umr_bitfield_default },
+	 { "MAX_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_CNTL[] = {
+	 { "WIDTH", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_STIPPLE[] = {
+	 { "LINE_PATTERN", 0, 15, &umr_bitfield_default },
+	 { "REPEAT_COUNT", 16, 23, &umr_bitfield_default },
+	 { "PATTERN_BIT_ORDER", 28, 28, &umr_bitfield_default },
+	 { "AUTO_RESET_CNTL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_OUTPUT_PATH_CNTL[] = {
+	 { "PATH_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_CNTL[] = {
+	 { "TESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_MAX_TESS_LEVEL[] = {
+	 { "MAX_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_MIN_TESS_LEVEL[] = {
+	 { "MIN_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_REUSE_DEPTH[] = {
+	 { "REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_PRIM_TYPE[] = {
+	 { "PRIM_TYPE", 0, 4, &umr_bitfield_default },
+	 { "RETAIN_ORDER", 14, 14, &umr_bitfield_default },
+	 { "RETAIN_QUADS", 15, 15, &umr_bitfield_default },
+	 { "PRIM_ORDER", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_FIRST_DECR[] = {
+	 { "FIRST_DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_DECR[] = {
+	 { "DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_0_CNTL[] = {
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_1_CNTL[] = {
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_0_FMT_CNTL[] = {
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_1_FMT_CNTL[] = {
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_MODE[] = {
+	 { "MODE", 0, 2, &umr_bitfield_default },
+	 { "RESERVED_0", 3, 3, &umr_bitfield_default },
+	 { "CUT_MODE", 4, 5, &umr_bitfield_default },
+	 { "RESERVED_1", 6, 10, &umr_bitfield_default },
+	 { "GS_C_PACK_EN", 11, 11, &umr_bitfield_default },
+	 { "RESERVED_2", 12, 12, &umr_bitfield_default },
+	 { "ES_PASSTHRU", 13, 13, &umr_bitfield_default },
+	 { "RESERVED_3", 14, 14, &umr_bitfield_default },
+	 { "RESERVED_4", 15, 15, &umr_bitfield_default },
+	 { "RESERVED_5", 16, 16, &umr_bitfield_default },
+	 { "PARTIAL_THD_AT_EOI", 17, 17, &umr_bitfield_default },
+	 { "SUPPRESS_CUTS", 18, 18, &umr_bitfield_default },
+	 { "ES_WRITE_OPTIMIZE", 19, 19, &umr_bitfield_default },
+	 { "GS_WRITE_OPTIMIZE", 20, 20, &umr_bitfield_default },
+	 { "ONCHIP", 21, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_ONCHIP_CNTL[] = {
+	 { "ES_VERTS_PER_SUBGRP", 0, 10, &umr_bitfield_default },
+	 { "GS_PRIMS_PER_SUBGRP", 11, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_MODE_CNTL_0[] = {
+	 { "MSAA_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VPORT_SCISSOR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "LINE_STIPPLE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PKR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_MODE_CNTL_1[] = {
+	 { "WALK_SIZE", 0, 0, &umr_bitfield_default },
+	 { "WALK_ALIGNMENT", 1, 1, &umr_bitfield_default },
+	 { "WALK_ALIGN8_PRIM_FITS_ST", 2, 2, &umr_bitfield_default },
+	 { "WALK_FENCE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "WALK_FENCE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "SUPERTILE_WALK_ORDER_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "TILE_WALK_ORDER_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "TILE_COVER_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "TILE_COVER_NO_SCISSOR", 10, 10, &umr_bitfield_default },
+	 { "ZMM_LINE_EXTENT", 11, 11, &umr_bitfield_default },
+	 { "ZMM_LINE_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "ZMM_RECT_EXTENT", 13, 13, &umr_bitfield_default },
+	 { "KILL_PIX_POST_HI_Z", 14, 14, &umr_bitfield_default },
+	 { "KILL_PIX_POST_DETAIL_MASK", 15, 15, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLE", 16, 16, &umr_bitfield_default },
+	 { "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "MULTI_GPU_SUPERTILE_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE", 20, 23, &umr_bitfield_default },
+	 { "MULTI_GPU_PRIM_DISCARD_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "FORCE_EOV_CNTDWN_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "FORCE_EOV_REZ_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_PRIMITIVE_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_WATER_MARK", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_PER_ES[] = {
+	 { "GS_PER_ES", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ES_PER_GS[] = {
+	 { "ES_PER_GS", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_PER_VS[] = {
+	 { "GS_PER_VS", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_1[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_2[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_3[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_OUT_PRIM_TYPE[] = {
+	 { "OUTPRIM_TYPE", 0, 5, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_1", 8, 13, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_2", 16, 21, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_3", 22, 27, &umr_bitfield_default },
+	 { "UNIQUE_TYPE_PER_STREAM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_SIZE[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_MAX_SIZE[] = {
+	 { "MAX_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+	 { "SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "BUF_TYPE", 4, 5, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 6, 6, &umr_bitfield_default },
+	 { "NOT_EOP", 9, 9, &umr_bitfield_default },
+	 { "REQ_PATH", 10, 10, &umr_bitfield_default },
+	 { "MTYPE", 11, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVEID_EN[] = {
+	 { "PRIMITIVEID_EN", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_RESET_ON_EOI", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVEID_RESET[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_EVENT_INITIATOR[] = {
+	 { "EVENT_TYPE", 0, 5, &umr_bitfield_default },
+	 { "ADDRESS_HI", 18, 26, &umr_bitfield_default },
+	 { "EXTENDED_EVENT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_EN[] = {
+	 { "RESET_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_0[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_1[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_MULTI_VGT_PARAM[] = {
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "PARTIAL_VS_WAVE_ON", 16, 16, &umr_bitfield_default },
+	 { "SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "PARTIAL_ES_WAVE_ON", 18, 18, &umr_bitfield_default },
+	 { "SWITCH_ON_EOI", 19, 19, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+	 { "MAX_PRIMGRP_IN_WAVE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ESGS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_REUSE_OFF[] = {
+	 { "REUSE_OFF", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VTX_CNT_EN[] = {
+	 { "VTX_CNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_HTILE_SURFACE[] = {
+	 { "LINEAR", 0, 0, &umr_bitfield_default },
+	 { "FULL_CACHE", 1, 1, &umr_bitfield_default },
+	 { "HTILE_USES_PRELOAD_WIN", 2, 2, &umr_bitfield_default },
+	 { "PRELOAD", 3, 3, &umr_bitfield_default },
+	 { "PREFETCH_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PREFETCH_HEIGHT", 10, 15, &umr_bitfield_default },
+	 { "DST_OUTSIDE_ZERO_TO_ONE", 16, 16, &umr_bitfield_default },
+	 { "TC_COMPATIBLE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE0[] = {
+	 { "COMPAREFUNC0", 0, 2, &umr_bitfield_default },
+	 { "COMPAREVALUE0", 4, 11, &umr_bitfield_default },
+	 { "COMPAREMASK0", 12, 19, &umr_bitfield_default },
+	 { "ENABLE0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE1[] = {
+	 { "COMPAREFUNC1", 0, 2, &umr_bitfield_default },
+	 { "COMPAREVALUE1", 4, 11, &umr_bitfield_default },
+	 { "COMPAREMASK1", 12, 19, &umr_bitfield_default },
+	 { "ENABLE1", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PRELOAD_CONTROL[] = {
+	 { "START_X", 0, 7, &umr_bitfield_default },
+	 { "START_Y", 8, 15, &umr_bitfield_default },
+	 { "MAX_X", 16, 23, &umr_bitfield_default },
+	 { "MAX_Y", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_0[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_0[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_1[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_1[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_2[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_2[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_3[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_3[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[] = {
+	 { "VERTEX_STRIDE", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_MAX_VERT_OUT[] = {
+	 { "MAX_VERT_OUT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TESS_DISTRIBUTION[] = {
+	 { "ACCUM_ISOLINE", 0, 7, &umr_bitfield_default },
+	 { "ACCUM_TRI", 8, 15, &umr_bitfield_default },
+	 { "ACCUM_QUAD", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_SHADER_STAGES_EN[] = {
+	 { "LS_EN", 0, 1, &umr_bitfield_default },
+	 { "HS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 4, &umr_bitfield_default },
+	 { "GS_EN", 5, 5, &umr_bitfield_default },
+	 { "VS_EN", 6, 7, &umr_bitfield_default },
+	 { "DYNAMIC_HS", 8, 8, &umr_bitfield_default },
+	 { "DISPATCH_DRAW_EN", 9, 9, &umr_bitfield_default },
+	 { "DIS_DEALLOC_ACCUM_0", 10, 10, &umr_bitfield_default },
+	 { "DIS_DEALLOC_ACCUM_1", 11, 11, &umr_bitfield_default },
+	 { "VS_WAVE_ID_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_LS_HS_CONFIG[] = {
+	 { "NUM_PATCHES", 0, 7, &umr_bitfield_default },
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+	 { "HS_NUM_OUTPUT_CP", 14, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_1[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_2[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_3[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_PARAM[] = {
+	 { "TYPE", 0, 1, &umr_bitfield_default },
+	 { "PARTITIONING", 2, 4, &umr_bitfield_default },
+	 { "TOPOLOGY", 5, 7, &umr_bitfield_default },
+	 { "RESERVED_REDUC_AXIS", 8, 8, &umr_bitfield_default },
+	 { "DEPRECATED", 9, 9, &umr_bitfield_default },
+	 { "NUM_DS_WAVES_PER_SIMD", 10, 13, &umr_bitfield_default },
+	 { "DISABLE_DONUTS", 14, 14, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 15, 15, &umr_bitfield_default },
+	 { "DISTRIBUTION_MODE", 17, 18, &umr_bitfield_default },
+	 { "MTYPE", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ALPHA_TO_MASK[] = {
+	 { "ALPHA_TO_MASK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET0", 8, 9, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET1", 10, 11, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET2", 12, 13, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET3", 14, 15, &umr_bitfield_default },
+	 { "OFFSET_ROUND", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DISPATCH_DRAW_INDEX[] = {
+	 { "MATCH_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[] = {
+	 { "POLY_OFFSET_NEG_NUM_DB_BITS", 0, 7, &umr_bitfield_default },
+	 { "POLY_OFFSET_DB_IS_FLOAT_FMT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_CLAMP[] = {
+	 { "CLAMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_INSTANCE_CNT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CNT", 2, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_CONFIG[] = {
+	 { "STREAMOUT_0_EN", 0, 0, &umr_bitfield_default },
+	 { "STREAMOUT_1_EN", 1, 1, &umr_bitfield_default },
+	 { "STREAMOUT_2_EN", 2, 2, &umr_bitfield_default },
+	 { "STREAMOUT_3_EN", 3, 3, &umr_bitfield_default },
+	 { "RAST_STREAM", 4, 6, &umr_bitfield_default },
+	 { "RAST_STREAM_MASK", 8, 11, &umr_bitfield_default },
+	 { "USE_RAST_STREAM_MASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_CONFIG[] = {
+	 { "STREAM_0_BUFFER_EN", 0, 3, &umr_bitfield_default },
+	 { "STREAM_1_BUFFER_EN", 4, 7, &umr_bitfield_default },
+	 { "STREAM_2_BUFFER_EN", 8, 11, &umr_bitfield_default },
+	 { "STREAM_3_BUFFER_EN", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_0[] = {
+	 { "DISTANCE_0", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_1", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_2", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_3", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_4", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_5", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_6", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_1[] = {
+	 { "DISTANCE_8", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_9", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_10", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_11", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_12", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_13", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_14", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_CNTL[] = {
+	 { "EXPAND_LINE_WIDTH", 9, 9, &umr_bitfield_default },
+	 { "LAST_PIXEL", 10, 10, &umr_bitfield_default },
+	 { "PERPENDICULAR_ENDCAP_ENA", 11, 11, &umr_bitfield_default },
+	 { "DX10_DIAMOND_TEST_ENA", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_CONFIG[] = {
+	 { "MSAA_NUM_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "AA_MASK_CENTROID_DTMN", 4, 4, &umr_bitfield_default },
+	 { "MAX_SAMPLE_DIST", 13, 16, &umr_bitfield_default },
+	 { "MSAA_EXPOSED_SAMPLES", 20, 22, &umr_bitfield_default },
+	 { "DETAIL_TO_EXPOSED_MODE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_VTX_CNTL[] = {
+	 { "PIX_CENTER", 0, 0, &umr_bitfield_default },
+	 { "ROUND_MODE", 1, 2, &umr_bitfield_default },
+	 { "QUANT_MODE", 3, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_VERT_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_VERT_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_HORZ_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_HORZ_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_MASK_X0Y0_X1Y0[] = {
+	 { "AA_MASK_X0Y0", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_MASK_X0Y1_X1Y1[] = {
+	 { "AA_MASK_X0Y1", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VERTEX_REUSE_BLOCK_CNTL[] = {
+	 { "VTX_REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_OUT_DEALLOC_CNTL[] = {
+	 { "DEALLOC_DIST", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG11[] = {
+	 { "clipsm3_clip_to_clipga_event", 0, 0, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_event", 1, 1, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_event", 2, 2, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_event", 3, 3, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_clip_primitive", 4, 4, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_clip_primitive", 5, 5, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_clip_primitive", 6, 6, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_clip_primitive", 7, 7, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_clip_to_outsm_cnt", 8, 11, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_clip_to_outsm_cnt", 12, 15, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_clip_to_outsm_cnt", 16, 19, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_clip_to_outsm_cnt", 20, 23, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_prim_valid", 24, 24, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_prim_valid", 25, 25, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_prim_valid", 26, 26, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_prim_valid", 27, 27, &umr_bitfield_default },
+	 { "clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt", 28, 28, &umr_bitfield_default },
+	 { "clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG11[] = {
+	 { "tm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "tm_noif_busy_q", 1, 1, &umr_bitfield_default },
+	 { "tm_out_busy_q", 2, 2, &umr_bitfield_default },
+	 { "es_rb_dealloc_fifo_busy", 3, 3, &umr_bitfield_default },
+	 { "vs_dealloc_tbl_busy", 4, 4, &umr_bitfield_default },
+	 { "SPARE1", 5, 5, &umr_bitfield_default },
+	 { "spi_gsthread_fifo_busy", 6, 6, &umr_bitfield_default },
+	 { "spi_esthread_fifo_busy", 7, 7, &umr_bitfield_default },
+	 { "hold_eswave", 8, 8, &umr_bitfield_default },
+	 { "es_rb_roll_over_r3", 9, 9, &umr_bitfield_default },
+	 { "counters_busy_r0", 10, 10, &umr_bitfield_default },
+	 { "counters_avail_r0", 11, 11, &umr_bitfield_default },
+	 { "counters_available_r0", 12, 12, &umr_bitfield_default },
+	 { "vs_event_fifo_rtr", 13, 13, &umr_bitfield_default },
+	 { "VGT_SPI_gsthread_rtr_q", 14, 14, &umr_bitfield_default },
+	 { "VGT_SPI_esthread_rtr_q", 15, 15, &umr_bitfield_default },
+	 { "gs_issue_rtr", 16, 16, &umr_bitfield_default },
+	 { "tm_pt_event_rtr", 17, 17, &umr_bitfield_default },
+	 { "SPARE0", 18, 18, &umr_bitfield_default },
+	 { "gs_r0_rtr", 19, 19, &umr_bitfield_default },
+	 { "es_r0_rtr", 20, 20, &umr_bitfield_default },
+	 { "gog_tm_vs_event_rtr", 21, 21, &umr_bitfield_default },
+	 { "tm_rcm_gs_event_rtr", 22, 22, &umr_bitfield_default },
+	 { "tm_rcm_gs_tbl_rtr", 23, 23, &umr_bitfield_default },
+	 { "tm_rcm_es_tbl_rtr", 24, 24, &umr_bitfield_default },
+	 { "vs_event_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "vs_event_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "es_rb_dealloc_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "vs_dealloc_tbl_full", 28, 28, &umr_bitfield_default },
+	 { "send_event_q", 29, 29, &umr_bitfield_default },
+	 { "es_tbl_empty", 30, 30, &umr_bitfield_default },
+	 { "no_active_states_r0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG12[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_priority_available_vte_out_clip", 8, 12, &umr_bitfield_default },
+	 { "clip_priority_available_clip_verts", 13, 17, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_out", 18, 19, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_vert", 20, 21, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_load", 22, 23, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_clip_primitive", 24, 24, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 25, 25, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_clip_primitive", 26, 26, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 27, 27, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_clip_primitive", 28, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_clip_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG12[] = {
+	 { "gs_state0_r0_q", 0, 2, &umr_bitfield_default },
+	 { "gs_state1_r0_q", 3, 5, &umr_bitfield_default },
+	 { "gs_state2_r0_q", 6, 8, &umr_bitfield_default },
+	 { "gs_state3_r0_q", 9, 11, &umr_bitfield_default },
+	 { "gs_state4_r0_q", 12, 14, &umr_bitfield_default },
+	 { "gs_state5_r0_q", 15, 17, &umr_bitfield_default },
+	 { "gs_state6_r0_q", 18, 20, &umr_bitfield_default },
+	 { "gs_state7_r0_q", 21, 23, &umr_bitfield_default },
+	 { "gs_state8_r0_q", 24, 26, &umr_bitfield_default },
+	 { "gs_state9_r0_q", 27, 29, &umr_bitfield_default },
+	 { "hold_eswave_eop", 30, 30, &umr_bitfield_default },
+	 { "SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_ADDR_LO[] = {
+	 { "ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_LO[] = {
+	 { "DATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_HI[] = {
+	 { "DATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_LAST_FENCE_LO[] = {
+	 { "LAST_FENCE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_LAST_FENCE_HI[] = {
+	 { "LAST_FENCE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_ADDR_LO[] = {
+	 { "STREAM_OUT_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_ADDR_HI[] = {
+	 { "STREAM_OUT_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_ADDR_LO[] = {
+	 { "PIPE_STATS_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_ADDR_HI[] = {
+	 { "PIPE_STATS_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_LO[] = {
+	 { "IAVERT_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_HI[] = {
+	 { "IAVERT_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_LO[] = {
+	 { "IAPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_HI[] = {
+	 { "IAPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_LO[] = {
+	 { "GSPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_HI[] = {
+	 { "GSPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_LO[] = {
+	 { "VSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_HI[] = {
+	 { "VSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_LO[] = {
+	 { "GSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_HI[] = {
+	 { "GSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_LO[] = {
+	 { "HSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_HI[] = {
+	 { "HSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_LO[] = {
+	 { "DSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_HI[] = {
+	 { "DSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CINVOC_COUNT_LO[] = {
+	 { "CINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CINVOC_COUNT_HI[] = {
+	 { "CINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CPRIM_COUNT_LO[] = {
+	 { "CPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CPRIM_COUNT_HI[] = {
+	 { "CPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_LO[] = {
+	 { "PSINVOC_COUNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_HI[] = {
+	 { "PSINVOC_COUNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_LO[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_HI[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_LO[] = {
+	 { "CSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_HI[] = {
+	 { "CSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_CONTROL[] = {
+	 { "CACHE_CONTROL", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_CONTROL[] = {
+	 { "CACHE_CONTROL", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STRMOUT_CNTL[] = {
+	 { "OFFSET_UPDATE_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_UMSK[] = {
+	 { "OBSOLETE_UMSK", 0, 7, &umr_bitfield_default },
+	 { "OBSOLETE_SWAP", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_ADDR[] = {
+	 { "OBSOLETE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_ADDR_LO[] = {
+	 { "MEM_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_ADDR_HI[] = {
+	 { "MEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "CS_PS_SEL", 16, 16, &umr_bitfield_default },
+	 { "CACHE_POLICY", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+	 { "COMMAND", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_LAST_CS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_LAST_PS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WADDR_LO[] = {
+	 { "ME_MC_WADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ME_MC_WADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WADDR_HI[] = {
+	 { "ME_MC_WADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "MTYPE", 20, 21, &umr_bitfield_default },
+	 { "CACHE_POLICY", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WDATA_LO[] = {
+	 { "ME_MC_WDATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WDATA_HI[] = {
+	 { "ME_MC_WDATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_RADDR_LO[] = {
+	 { "ME_MC_RADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ME_MC_RADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_RADDR_HI[] = {
+	 { "ME_MC_RADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "MTYPE", 20, 21, &umr_bitfield_default },
+	 { "CACHE_POLICY", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SEM_WAIT_TIMER[] = {
+	 { "SEM_WAIT_TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SIG_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SIG_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_REG_MEM_TIMEOUT[] = {
+	 { "WAIT_REG_MEM_TIMEOUT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_CONTROL[] = {
+	 { "SRC_MTYPE", 10, 11, &umr_bitfield_default },
+	 { "SRC_ATC", 12, 12, &umr_bitfield_default },
+	 { "SRC_CACHE_POLICY", 13, 13, &umr_bitfield_default },
+	 { "DST_SELECT", 20, 21, &umr_bitfield_default },
+	 { "DST_MTYPE", 22, 23, &umr_bitfield_default },
+	 { "DST_ATC", 24, 24, &umr_bitfield_default },
+	 { "DST_CACHE_POLICY", 25, 25, &umr_bitfield_default },
+	 { "SRC_SELECT", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_CONTROL[] = {
+	 { "SRC_MTYPE", 10, 11, &umr_bitfield_default },
+	 { "SRC_ATC", 12, 12, &umr_bitfield_default },
+	 { "SRC_CACHE_POLICY", 13, 13, &umr_bitfield_default },
+	 { "DST_SELECT", 20, 21, &umr_bitfield_default },
+	 { "DST_MTYPE", 22, 23, &umr_bitfield_default },
+	 { "DST_ATC", 24, 24, &umr_bitfield_default },
+	 { "DST_CACHE_POLICY", 25, 25, &umr_bitfield_default },
+	 { "SRC_SELECT", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_BASE_HI[] = {
+	 { "COHER_BASE_HI_256B", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_START_DELAY[] = {
+	 { "START_DELAY_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_CNTL[] = {
+	 { "DEST_BASE_0_ENA", 0, 0, &umr_bitfield_default },
+	 { "DEST_BASE_1_ENA", 1, 1, &umr_bitfield_default },
+	 { "TC_SD_ACTION_ENA", 2, 2, &umr_bitfield_default },
+	 { "TC_NC_ACTION_ENA", 3, 3, &umr_bitfield_default },
+	 { "CB0_DEST_BASE_ENA", 6, 6, &umr_bitfield_default },
+	 { "CB1_DEST_BASE_ENA", 7, 7, &umr_bitfield_default },
+	 { "CB2_DEST_BASE_ENA", 8, 8, &umr_bitfield_default },
+	 { "CB3_DEST_BASE_ENA", 9, 9, &umr_bitfield_default },
+	 { "CB4_DEST_BASE_ENA", 10, 10, &umr_bitfield_default },
+	 { "CB5_DEST_BASE_ENA", 11, 11, &umr_bitfield_default },
+	 { "CB6_DEST_BASE_ENA", 12, 12, &umr_bitfield_default },
+	 { "CB7_DEST_BASE_ENA", 13, 13, &umr_bitfield_default },
+	 { "DB_DEST_BASE_ENA", 14, 14, &umr_bitfield_default },
+	 { "TCL1_VOL_ACTION_ENA", 15, 15, &umr_bitfield_default },
+	 { "TC_WB_ACTION_ENA", 18, 18, &umr_bitfield_default },
+	 { "DEST_BASE_2_ENA", 19, 19, &umr_bitfield_default },
+	 { "DEST_BASE_3_ENA", 21, 21, &umr_bitfield_default },
+	 { "TCL1_ACTION_ENA", 22, 22, &umr_bitfield_default },
+	 { "TC_ACTION_ENA", 23, 23, &umr_bitfield_default },
+	 { "CB_ACTION_ENA", 25, 25, &umr_bitfield_default },
+	 { "DB_ACTION_ENA", 26, 26, &umr_bitfield_default },
+	 { "SH_KCACHE_ACTION_ENA", 27, 27, &umr_bitfield_default },
+	 { "SH_KCACHE_VOL_ACTION_ENA", 28, 28, &umr_bitfield_default },
+	 { "SH_ICACHE_ACTION_ENA", 29, 29, &umr_bitfield_default },
+	 { "SH_KCACHE_WB_ACTION_ENA", 30, 30, &umr_bitfield_default },
+	 { "SH_SD_ACTION_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_SIZE[] = {
+	 { "COHER_SIZE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_BASE[] = {
+	 { "COHER_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_STATUS[] = {
+	 { "MATCHING_GFX_CNTX", 0, 7, &umr_bitfield_default },
+	 { "MEID", 24, 25, &umr_bitfield_default },
+	 { "PHASE1_STATUS", 30, 30, &umr_bitfield_default },
+	 { "STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_CNTL[] = {
+	 { "MIN_AVAILSZ", 4, 5, &umr_bitfield_default },
+	 { "BUFFER_DEPTH", 16, 19, &umr_bitfield_default },
+	 { "PIO_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
+	 { "PIO_FIFO_FULL", 29, 29, &umr_bitfield_default },
+	 { "PIO_COUNT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_READ_TAGS[] = {
+	 { "DMA_READ_TAG", 0, 25, &umr_bitfield_default },
+	 { "DMA_READ_TAG_VALID", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_SIZE_HI[] = {
+	 { "COHER_SIZE_HI_256B", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_IB_CONTROL[] = {
+	 { "IB_EN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_LOAD_CONTROL[] = {
+	 { "CONFIG_REG_EN", 0, 0, &umr_bitfield_default },
+	 { "CNTX_REG_EN", 1, 1, &umr_bitfield_default },
+	 { "SH_GFX_REG_EN", 16, 16, &umr_bitfield_default },
+	 { "SH_CS_REG_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_OFFSET[] = {
+	 { "RB_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_OFFSET[] = {
+	 { "IB1_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_OFFSET[] = {
+	 { "IB2_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_PREAMBLE_BEGIN[] = {
+	 { "IB1_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_PREAMBLE_END[] = {
+	 { "IB1_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_PREAMBLE_BEGIN[] = {
+	 { "IB2_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_PREAMBLE_END[] = {
+	 { "IB2_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_OFFSET[] = {
+	 { "IB1_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_OFFSET[] = {
+	 { "IB2_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_COUNTER[] = {
+	 { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_RB_OFFSET[] = {
+	 { "RB_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BASE_LO[] = {
+	 { "INIT_BASE_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BASE_HI[] = {
+	 { "INIT_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BUFSZ[] = {
+	 { "INIT_BUFSZ", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BASE_LO[] = {
+	 { "ST_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BASE_HI[] = {
+	 { "ST_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BUFSZ[] = {
+	 { "ST_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_EVENT_CNTL[] = {
+	 { "WBINV_TC_OP", 0, 6, &umr_bitfield_default },
+	 { "WBINV_ACTION_ENA", 12, 17, &umr_bitfield_default },
+	 { "CACHE_CONTROL", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_CNTL[] = {
+	 { "CNTX_ID", 0, 15, &umr_bitfield_default },
+	 { "DST_SEL", 16, 17, &umr_bitfield_default },
+	 { "INT_SEL", 24, 26, &umr_bitfield_default },
+	 { "DATA_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_CNTX_ID[] = {
+	 { "CNTX_ID", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_COMPLETION_STATUS[] = {
+	 { "STATUS", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_COMPLETION_STATUS[] = {
+	 { "STATUS", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRED_NOT_VISIBLE[] = {
+	 { "NOT_VISIBLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_METADATA_BASE_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_METADATA_BASE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_METADATA_BASE_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_METADATA_BASE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_INDX_INDR_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_INDX_INDR_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DISPATCH_INDR_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DISPATCH_INDR_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INDEX_BASE_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INDEX_BASE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_BKUP_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_BKUP_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SAMPLE_STATUS[] = {
+	 { "Z_PASS_ACITVE", 0, 0, &umr_bitfield_default },
+	 { "STREAMOUT_ACTIVE", 1, 1, &umr_bitfield_default },
+	 { "PIPELINE_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "STIPPLE_ACTIVE", 3, 3, &umr_bitfield_default },
+	 { "VGT_BUFFERS_ACTIVE", 4, 4, &umr_bitfield_default },
+	 { "SCREEN_EXT_ACTIVE", 5, 5, &umr_bitfield_default },
+	 { "DRAW_INDIRECT_ACTIVE", 6, 6, &umr_bitfield_default },
+	 { "DISP_INDIRECT_ACTIVE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_GFX_INDEX[] = {
+	 { "INSTANCE_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 15, &umr_bitfield_default },
+	 { "SE_INDEX", 16, 23, &umr_bitfield_default },
+	 { "SH_BROADCAST_WRITES", 29, 29, &umr_bitfield_default },
+	 { "INSTANCE_BROADCAST_WRITES", 30, 30, &umr_bitfield_default },
+	 { "SE_BROADCAST_WRITES", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ESGS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_NUM_INDICES[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_RING_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HS_OFFCHIP_PARAM[] = {
+	 { "OFFCHIP_BUFFERING", 0, 8, &umr_bitfield_default },
+	 { "OFFCHIP_GRANULARITY", 9, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_MEMORY_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_VALUE[] = {
+	 { "LINE_STIPPLE_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_STIPPLE_STATE[] = {
+	 { "CURRENT_PTR", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MIN_0[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MAX_0[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MIN_1[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MAX_1[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_SIZE[] = {
+	 { "SIZE", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_MASK[] = {
+	 { "CU_SEL", 0, 4, &umr_bitfield_default },
+	 { "SH_SEL", 5, 5, &umr_bitfield_default },
+	 { "REG_STALL_EN", 7, 7, &umr_bitfield_default },
+	 { "SIMD_EN", 8, 11, &umr_bitfield_default },
+	 { "VM_ID_MASK", 12, 13, &umr_bitfield_default },
+	 { "SPI_STALL_EN", 14, 14, &umr_bitfield_default },
+	 { "SQ_STALL_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK[] = {
+	 { "TOKEN_MASK", 0, 15, &umr_bitfield_default },
+	 { "REG_MASK", 16, 23, &umr_bitfield_default },
+	 { "REG_DROP_ON_STALL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_PERF_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_CTRL[] = {
+	 { "RESET_BUFFER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_MODE[] = {
+	 { "MASK_PS", 0, 2, &umr_bitfield_default },
+	 { "MASK_VS", 3, 5, &umr_bitfield_default },
+	 { "MASK_GS", 6, 8, &umr_bitfield_default },
+	 { "MASK_ES", 9, 11, &umr_bitfield_default },
+	 { "MASK_HS", 12, 14, &umr_bitfield_default },
+	 { "MASK_LS", 15, 17, &umr_bitfield_default },
+	 { "MASK_CS", 18, 20, &umr_bitfield_default },
+	 { "MODE", 21, 22, &umr_bitfield_default },
+	 { "CAPTURE_MODE", 23, 24, &umr_bitfield_default },
+	 { "AUTOFLUSH_EN", 25, 25, &umr_bitfield_default },
+	 { "PRIV", 26, 26, &umr_bitfield_default },
+	 { "ISSUE_MASK", 27, 28, &umr_bitfield_default },
+	 { "TEST_MODE", 29, 29, &umr_bitfield_default },
+	 { "INTERRUPT_EN", 30, 30, &umr_bitfield_default },
+	 { "WRAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_BASE2[] = {
+	 { "ADDR_HI", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK2[] = {
+	 { "INST_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WPTR[] = {
+	 { "WPTR", 0, 29, &umr_bitfield_default },
+	 { "READ_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_STATUS[] = {
+	 { "FINISH_PENDING", 0, 9, &umr_bitfield_default },
+	 { "FINISH_DONE", 16, 25, &umr_bitfield_default },
+	 { "NEW_BUF", 29, 29, &umr_bitfield_default },
+	 { "BUSY", 30, 30, &umr_bitfield_default },
+	 { "FULL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_HIWATER[] = {
+	 { "HIWATER", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_CACHES[] = {
+	 { "TARGET_INST", 0, 0, &umr_bitfield_default },
+	 { "TARGET_DATA", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE", 2, 2, &umr_bitfield_default },
+	 { "WRITEBACK", 3, 3, &umr_bitfield_default },
+	 { "VOL", 4, 4, &umr_bitfield_default },
+	 { "COMPLETE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_WRITEBACK[] = {
+	 { "DWB", 0, 0, &umr_bitfield_default },
+	 { "DIRTY", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CS_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CS_BC_BASE_ADDR_HI[] = {
+	 { "ADDRESS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT0_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT0_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT1_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT1_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT2_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT2_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT3_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT3_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ZPASS_COUNT_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ZPASS_COUNT_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_ADDR[] = {
+	 { "READ_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_DATA[] = {
+	 { "READ_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_ADDR[] = {
+	 { "BURST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_COUNT[] = {
+	 { "BURST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_DATA[] = {
+	 { "BURST_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_BURST_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_BURST_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WRITE_COMPLETE[] = {
+	 { "WRITE_COMPLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_CNTL[] = {
+	 { "AINC", 0, 5, &umr_bitfield_default },
+	 { "UNUSED1", 6, 7, &umr_bitfield_default },
+	 { "DMODE", 8, 9, &umr_bitfield_default },
+	 { "UNUSED2", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_COMPLETE[] = {
+	 { "COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "UNUSED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OFFSET0[] = {
+	 { "OFFSET0", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OFFSET1[] = {
+	 { "OFFSET1", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_DST[] = {
+	 { "DST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OP[] = {
+	 { "OP", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_CNTL[] = {
+	 { "INDEX", 0, 5, &umr_bitfield_default },
+	 { "UNUSED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE[] = {
+	 { "FLAG", 0, 0, &umr_bitfield_default },
+	 { "COUNTER", 1, 12, &umr_bitfield_default },
+	 { "TYPE", 13, 13, &umr_bitfield_default },
+	 { "DED", 14, 14, &umr_bitfield_default },
+	 { "RELEASE_ALL", 15, 15, &umr_bitfield_default },
+	 { "HEAD_QUEUE", 16, 26, &umr_bitfield_default },
+	 { "HEAD_VALID", 27, 27, &umr_bitfield_default },
+	 { "HEAD_FLAG", 28, 28, &umr_bitfield_default },
+	 { "UNUSED1", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_CNT[] = {
+	 { "RESOURCE_CNT", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_CNTL[] = {
+	 { "INDEX", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_COUNTER[] = {
+	 { "SPACE_AVAILABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_ADDRESS[] = {
+	 { "DS_ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "CRAWLER", 16, 19, &umr_bitfield_default },
+	 { "CRAWLER_TYPE", 20, 21, &umr_bitfield_default },
+	 { "UNUSED", 22, 29, &umr_bitfield_default },
+	 { "NO_ALLOC", 30, 30, &umr_bitfield_default },
+	 { "ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_INCDEC[] = {
+	 { "VALUE", 0, 30, &umr_bitfield_default },
+	 { "INCDEC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RING_SIZE[] = {
+	 { "RING_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG13[] = {
+	 { "clprim_in_back_state_var_indx", 0, 2, &umr_bitfield_default },
+	 { "point_clip_candidate", 3, 3, &umr_bitfield_default },
+	 { "prim_nan_kill", 4, 4, &umr_bitfield_default },
+	 { "clprim_clip_primitive", 5, 5, &umr_bitfield_default },
+	 { "clprim_cull_primitive", 6, 6, &umr_bitfield_default },
+	 { "prim_back_valid", 7, 7, &umr_bitfield_default },
+	 { "vertval_bits_vertex_cc_next_valid", 8, 11, &umr_bitfield_default },
+	 { "clipcc_vertex_store_indx", 12, 13, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_empty", 14, 14, &umr_bitfield_default },
+	 { "clipcode_fifo_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_empty", 16, 16, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_out_cnt", 17, 20, &umr_bitfield_default },
+	 { "outsm_clr_rd_orig_vertices", 21, 22, &umr_bitfield_default },
+	 { "outsm_clr_rd_clipsm_wait", 23, 23, &umr_bitfield_default },
+	 { "outsm_clr_fifo_contents", 24, 28, &umr_bitfield_default },
+	 { "outsm_clr_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "outsm_clr_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "outsm_clr_fifo_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG13[] = {
+	 { "gs_state10_r0_q", 0, 2, &umr_bitfield_default },
+	 { "gs_state11_r0_q", 3, 5, &umr_bitfield_default },
+	 { "gs_state12_r0_q", 6, 8, &umr_bitfield_default },
+	 { "gs_state13_r0_q", 9, 11, &umr_bitfield_default },
+	 { "gs_state14_r0_q", 12, 14, &umr_bitfield_default },
+	 { "gs_state15_r0_q", 15, 17, &umr_bitfield_default },
+	 { "gs_tbl_wrptr_r0_q_3_0", 18, 21, &umr_bitfield_default },
+	 { "gsfetch_done_fifo_cnt_q_not_0", 22, 22, &umr_bitfield_default },
+	 { "gsfetch_done_cnt_q_not_0", 23, 23, &umr_bitfield_default },
+	 { "es_tbl_full", 24, 24, &umr_bitfield_default },
+	 { "SPARE1", 25, 25, &umr_bitfield_default },
+	 { "SPARE0", 26, 26, &umr_bitfield_default },
+	 { "active_cm_sm_r0_q", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
+	 { "SPM_PERFMON_STATE", 4, 7, &umr_bitfield_default },
+	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_OBJECT[] = {
+	 { "OBJECT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_OBJECT_COUNTER[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_MASK_HI[] = {
+	 { "WINDOW_MASK_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_HI[] = {
+	 { "WINDOW_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_LO[] = {
+	 { "MIN", 0, 15, &umr_bitfield_default },
+	 { "MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_CNTL[] = {
+	 { "DISABLE_DRAW_WINDOW_LO_MAX", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_DRAW_WINDOW_LO_MIN", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_DRAW_WINDOW_HI", 2, 2, &umr_bitfield_default },
+	 { "MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER_SEID_MASK[] = {
+	 { "PERF_SEID_IGNORE_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER_BINS[] = {
+	 { "BIN0_MIN", 0, 3, &umr_bitfield_default },
+	 { "BIN0_MAX", 4, 7, &umr_bitfield_default },
+	 { "BIN1_MIN", 8, 11, &umr_bitfield_default },
+	 { "BIN1_MAX", 12, 15, &umr_bitfield_default },
+	 { "BIN2_MIN", 16, 19, &umr_bitfield_default },
+	 { "BIN2_MAX", 20, 23, &umr_bitfield_default },
+	 { "BIN3_MIN", 24, 27, &umr_bitfield_default },
+	 { "BIN3_MAX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+	 { "CNTR_RATE", 8, 12, &umr_bitfield_default },
+	 { "DISABLE_FLUSH", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL2[] = {
+	 { "FORCE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 17, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 17, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER_FILTER[] = {
+	 { "OP_FILTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OP_FILTER_SEL", 1, 3, &umr_bitfield_default },
+	 { "FORMAT_FILTER_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FORMAT_FILTER_SEL", 5, 9, &umr_bitfield_default },
+	 { "CLEAR_FILTER_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "CLEAR_FILTER_SEL", 11, 11, &umr_bitfield_default },
+	 { "MRT_FILTER_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "MRT_FILTER_SEL", 13, 15, &umr_bitfield_default },
+	 { "NUM_SAMPLES_FILTER_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "NUM_SAMPLES_FILTER_SEL", 18, 20, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS_FILTER_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS_FILTER_SEL", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 18, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 18, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_CNTL[] = {
+	 { "RESERVED1", 0, 11, &umr_bitfield_default },
+	 { "PERFMON_RING_MODE", 12, 13, &umr_bitfield_default },
+	 { "RESERVED", 14, 15, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_BASE_LO[] = {
+	 { "RING_BASE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_BASE_HI[] = {
+	 { "RING_BASE_HI", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_SIZE[] = {
+	 { "RING_BASE_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_SEGMENT_SIZE[] = {
+	 { "PERFMON_SEGMENT_SIZE", 0, 7, &umr_bitfield_default },
+	 { "RESERVED1", 8, 10, &umr_bitfield_default },
+	 { "GLOBAL_NUM_LINE", 11, 15, &umr_bitfield_default },
+	 { "SE0_NUM_LINE", 16, 20, &umr_bitfield_default },
+	 { "SE1_NUM_LINE", 21, 25, &umr_bitfield_default },
+	 { "SE2_NUM_LINE", 26, 30, &umr_bitfield_default },
+	 { "RESERVED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SE_MUXSEL_ADDR[] = {
+	 { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SE_MUXSEL_DATA[] = {
+	 { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GLOBAL_MUXSEL_ADDR[] = {
+	 { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GLOBAL_MUXSEL_DATA[] = {
+	 { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_RING_RDPTR[] = {
+	 { "PERFMON_RING_RDPTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SEGMENT_THRESHOLD[] = {
+	 { "NUM_SEGMENT_THRESHOLD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFMON_CLK_CNTL[] = {
+	 { "PERFMON_CLOCK_STATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 2, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG14[] = {
+	 { "clprim_in_back_vertex_store_indx_2", 0, 5, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_1", 6, 11, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_0", 12, 17, &umr_bitfield_default },
+	 { "outputclprimtoclip_null_primitive", 18, 18, &umr_bitfield_default },
+	 { "clprim_in_back_end_of_packet", 19, 19, &umr_bitfield_default },
+	 { "clprim_in_back_first_prim_of_slot", 20, 20, &umr_bitfield_default },
+	 { "clprim_in_back_deallocate_slot", 21, 23, &umr_bitfield_default },
+	 { "clprim_in_back_event_id", 24, 29, &umr_bitfield_default },
+	 { "clprim_in_back_event", 30, 30, &umr_bitfield_default },
+	 { "prim_back_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG14[] = {
+	 { "SPARE3", 0, 3, &umr_bitfield_default },
+	 { "gsfetch_done_fifo_full", 4, 4, &umr_bitfield_default },
+	 { "gs_rb_space_avail_r0", 5, 5, &umr_bitfield_default },
+	 { "smx_es_done_cnt_r0_q_not_0", 6, 6, &umr_bitfield_default },
+	 { "SPARE8", 7, 8, &umr_bitfield_default },
+	 { "vs_done_cnt_q_not_0", 9, 9, &umr_bitfield_default },
+	 { "es_flush_cnt_busy_q", 10, 10, &umr_bitfield_default },
+	 { "gs_tbl_full_r0", 11, 11, &umr_bitfield_default },
+	 { "SPARE2", 12, 20, &umr_bitfield_default },
+	 { "se1spi_gsthread_fifo_busy", 21, 21, &umr_bitfield_default },
+	 { "SPARE", 22, 24, &umr_bitfield_default },
+	 { "VGT_SE1SPI_gsthread_rtr_q", 25, 25, &umr_bitfield_default },
+	 { "smx1_es_done_cnt_r0_q_not_0", 26, 26, &umr_bitfield_default },
+	 { "se1spi_esthread_fifo_busy", 27, 27, &umr_bitfield_default },
+	 { "SPARE1", 28, 28, &umr_bitfield_default },
+	 { "gsfetch_done_se1_cnt_q_not_0", 29, 29, &umr_bitfield_default },
+	 { "SPARE0", 30, 30, &umr_bitfield_default },
+	 { "VGT_SE1SPI_esthread_rtr_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CNTL[] = {
+	 { "RLC_ENABLE_F32", 0, 0, &umr_bitfield_default },
+	 { "FORCE_RETRY", 1, 1, &umr_bitfield_default },
+	 { "READ_CACHE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RLC_STEP_F32", 3, 3, &umr_bitfield_default },
+	 { "SOFT_RESET_DEBUG_MODE", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MC_CNTL[] = {
+	 { "WRREQ_SWAP", 0, 1, &umr_bitfield_default },
+	 { "WRREQ_TRAN", 2, 2, &umr_bitfield_default },
+	 { "WRREQ_PRIV", 3, 3, &umr_bitfield_default },
+	 { "WRNFO_STALL", 4, 4, &umr_bitfield_default },
+	 { "WRNFO_URG", 5, 8, &umr_bitfield_default },
+	 { "WRREQ_DW_IMASK", 9, 12, &umr_bitfield_default },
+	 { "RESERVED_B", 13, 19, &umr_bitfield_default },
+	 { "RDNFO_URG", 20, 23, &umr_bitfield_default },
+	 { "RDREQ_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RDREQ_TRAN", 26, 26, &umr_bitfield_default },
+	 { "RDREQ_PRIV", 27, 27, &umr_bitfield_default },
+	 { "RDNFO_STALL", 28, 28, &umr_bitfield_default },
+	 { "RESERVED", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_STAT[] = {
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "RLC_GPM_BUSY", 1, 1, &umr_bitfield_default },
+	 { "RLC_SPM_BUSY", 2, 2, &umr_bitfield_default },
+	 { "RESERVED", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SOFT_RESET_GPU[] = {
+	 { "SOFT_RESET_GPU", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SAFE_MODE[] = {
+	 { "CMD", 0, 0, &umr_bitfield_default },
+	 { "MESSAGE", 1, 4, &umr_bitfield_default },
+	 { "RESERVED1", 5, 7, &umr_bitfield_default },
+	 { "RESPONSE", 8, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MEM_SLP_CNTL[] = {
+	 { "RLC_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "RLC_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 6, &umr_bitfield_default },
+	 { "RLC_LS_DS_BUSY_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "RLC_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "RLC_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_RLC_RESPONSE[] = {
+	 { "RESP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_RLCV_SAFE_MODE[] = {
+	 { "CMD", 0, 0, &umr_bitfield_default },
+	 { "MESSAGE", 1, 4, &umr_bitfield_default },
+	 { "RESERVED1", 5, 7, &umr_bitfield_default },
+	 { "RESPONSE", 8, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_SAFE_MODE[] = {
+	 { "CMD", 0, 0, &umr_bitfield_default },
+	 { "MESSAGE", 1, 4, &umr_bitfield_default },
+	 { "RESERVED1", 5, 7, &umr_bitfield_default },
+	 { "RESPONSE", 8, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_RLCV_COMMAND[] = {
+	 { "CMD", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTR_MAX[] = {
+	 { "LB_CNTR_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTL[] = {
+	 { "LOAD_BALANCE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LB_CNT_CP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LB_CNT_SPIM_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "LB_CNT_REG_INC", 3, 3, &umr_bitfield_default },
+	 { "CU_MASK_USED_OFF_HYST", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MGCG_CTRL[] = {
+	 { "MGCG_EN", 0, 0, &umr_bitfield_default },
+	 { "SILICON_EN", 1, 1, &umr_bitfield_default },
+	 { "SIMULATION_EN", 2, 2, &umr_bitfield_default },
+	 { "ON_DELAY", 3, 6, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 7, 14, &umr_bitfield_default },
+	 { "SPARE", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTR_INIT[] = {
+	 { "LB_CNTR_INIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LOAD_BALANCE_CNTR[] = {
+	 { "RLC_LOAD_BALANCE_CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SAVE_AND_RESTORE_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DRIVER_CPDMA_STATUS[] = {
+	 { "DRIVER_REQUEST", 0, 0, &umr_bitfield_default },
+	 { "RESERVED1", 1, 3, &umr_bitfield_default },
+	 { "DRIVER_ACK", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_JUMP_TABLE_RESTORE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_DELAY_2[] = {
+	 { "SERDES_TIMEOUT_VALUE", 0, 7, &umr_bitfield_default },
+	 { "SERDES_CMD_DELAY", 8, 15, &umr_bitfield_default },
+	 { "PERCU_TIMEOUT_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "F32_DEBUG_SELECT", 8, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_LSB[] = {
+	 { "GPU_CLOCKS_LSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_MSB[] = {
+	 { "GPU_CLOCKS_MSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CAPTURE_GPU_CLOCK_COUNT[] = {
+	 { "CAPTURE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_UCODE_CNTL[] = {
+	 { "RLC_UCODE_FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_THREAD_RESET[] = {
+	 { "THREAD0_RESET", 0, 0, &umr_bitfield_default },
+	 { "THREAD1_RESET", 1, 1, &umr_bitfield_default },
+	 { "THREAD2_RESET", 2, 2, &umr_bitfield_default },
+	 { "THREAD3_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_STAT[] = {
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_STATUS", 1, 1, &umr_bitfield_default },
+	 { "GFX_CLOCK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "GFX_LS_STATUS", 3, 3, &umr_bitfield_default },
+	 { "GFX_PIPELINE_POWER_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CNTX_IDLE_BEING_PROCESSED", 5, 5, &umr_bitfield_default },
+	 { "CNTX_BUSY_BEING_PROCESSED", 6, 6, &umr_bitfield_default },
+	 { "GFX_IDLE_BEING_PROCESSED", 7, 7, &umr_bitfield_default },
+	 { "CMP_BUSY_BEING_PROCESSED", 8, 8, &umr_bitfield_default },
+	 { "SAVING_REGISTERS", 9, 9, &umr_bitfield_default },
+	 { "RESTORING_REGISTERS", 10, 10, &umr_bitfield_default },
+	 { "GFX3D_BLOCKS_CHANGING_POWER_STATE", 11, 11, &umr_bitfield_default },
+	 { "CMP_BLOCKS_CHANGING_POWER_STATE", 12, 12, &umr_bitfield_default },
+	 { "STATIC_CU_POWERING_UP", 13, 13, &umr_bitfield_default },
+	 { "STATIC_CU_POWERING_DOWN", 14, 14, &umr_bitfield_default },
+	 { "DYN_CU_POWERING_UP", 15, 15, &umr_bitfield_default },
+	 { "DYN_CU_POWERING_DOWN", 16, 16, &umr_bitfield_default },
+	 { "ABORTED_PD_SEQUENCE", 17, 17, &umr_bitfield_default },
+	 { "PG_ERROR_STATUS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_32_RES_SEL[] = {
+	 { "RES_SEL", 0, 5, &umr_bitfield_default },
+	 { "RESERVED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_32[] = {
+	 { "GPU_CLOCK_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_CNTL[] = {
+	 { "GFX_POWER_GATING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_GATING_SRC", 1, 1, &umr_bitfield_default },
+	 { "DYN_PER_CU_PG_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "STATIC_PER_CU_PG_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "GFX_PIPELINE_PG_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 13, &umr_bitfield_default },
+	 { "PG_OVERRIDE", 14, 14, &umr_bitfield_default },
+	 { "CP_PG_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "CHUB_HANDSHAKE_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PU_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PD_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "SMU_HANDSHAKE_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "QUICK_PG_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED1", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_THREAD_PRIORITY[] = {
+	 { "THREAD0_PRIORITY", 0, 7, &umr_bitfield_default },
+	 { "THREAD1_PRIORITY", 8, 15, &umr_bitfield_default },
+	 { "THREAD2_PRIORITY", 16, 23, &umr_bitfield_default },
+	 { "THREAD3_PRIORITY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_THREAD_ENABLE[] = {
+	 { "THREAD0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "THREAD1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "THREAD2_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "THREAD3_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_VMID_THREAD0[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED0", 4, 7, &umr_bitfield_default },
+	 { "RLC_QUEUEID", 8, 10, &umr_bitfield_default },
+	 { "RESERVED1", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_VMID_THREAD1[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED0", 4, 7, &umr_bitfield_default },
+	 { "RLC_QUEUEID", 8, 10, &umr_bitfield_default },
+	 { "RESERVED1", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGTT_MGCG_OVERRIDE[] = {
+	 { "OVERRIDE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGCG_CGLS_CTRL[] = {
+	 { "CGCG_EN", 0, 0, &umr_bitfield_default },
+	 { "CGLS_EN", 1, 1, &umr_bitfield_default },
+	 { "CGLS_REP_COMPANSAT_DELAY", 2, 7, &umr_bitfield_default },
+	 { "CGCG_GFX_IDLE_THRESHOLD", 8, 26, &umr_bitfield_default },
+	 { "CGCG_CONTROLLER", 27, 27, &umr_bitfield_default },
+	 { "CGCG_REG_CTRL", 28, 28, &umr_bitfield_default },
+	 { "SLEEP_MODE", 29, 30, &umr_bitfield_default },
+	 { "SIM_SILICON_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGCG_RAMP_CTRL[] = {
+	 { "DOWN_DIV_START_UNIT", 0, 3, &umr_bitfield_default },
+	 { "DOWN_DIV_STEP_UNIT", 4, 7, &umr_bitfield_default },
+	 { "UP_DIV_START_UNIT", 8, 11, &umr_bitfield_default },
+	 { "UP_DIV_STEP_UNIT", 12, 15, &umr_bitfield_default },
+	 { "STEP_DELAY_CNT", 16, 27, &umr_bitfield_default },
+	 { "STEP_DELAY_UNIT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DYN_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DYN_PG_REQUEST[] = {
+	 { "PG_REQUEST_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_DELAY[] = {
+	 { "POWER_UP_DELAY", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CMD_PROPAGATE_DELAY", 16, 23, &umr_bitfield_default },
+	 { "MEM_SLEEP_DELAY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CU_STATUS[] = {
+	 { "WORK_PENDING", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_INIT_CU_MASK[] = {
+	 { "INIT_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[] = {
+	 { "ALWAYS_ACTIVE_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_PARAMS[] = {
+	 { "SKIP_L2_CHECK", 0, 0, &umr_bitfield_default },
+	 { "FIFO_SAMPLES", 1, 7, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLES", 8, 15, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_THREAD1_DELAY[] = {
+	 { "CU_IDEL_DELAY", 0, 7, &umr_bitfield_default },
+	 { "LBPW_INNER_LOOP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LBPW_OUTER_LOOP_DELAY", 16, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_ALWAYS_ON_CU_MASK[] = {
+	 { "AON_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MAX_PG_CU[] = {
+	 { "MAX_POWERED_UP_CU", 0, 7, &umr_bitfield_default },
+	 { "SPARE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_AUTO_PG_CTRL[] = {
+	 { "AUTO_PG_EN", 0, 0, &umr_bitfield_default },
+	 { "AUTO_GRBM_REG_SAVE_ON_IDLE_EN", 1, 1, &umr_bitfield_default },
+	 { "AUTO_WAKE_UP_EN", 2, 2, &umr_bitfield_default },
+	 { "GRBM_REG_SAVE_GFX_IDLE_THRESHOLD", 3, 18, &umr_bitfield_default },
+	 { "PG_AFTER_GRBM_REG_SAVE_THRESHOLD", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_GRBM_REG_SAVE_CTRL[] = {
+	 { "START_GRBM_REG_SAVE", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_PG_CTRL[] = {
+	 { "START_PG", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_PG_WAKE_UP_CTRL[] = {
+	 { "START_PG_WAKE_UP", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_MASTER_INDEX[] = {
+	 { "CU_ID", 0, 3, &umr_bitfield_default },
+	 { "SH_ID", 4, 5, &umr_bitfield_default },
+	 { "SE_ID", 6, 8, &umr_bitfield_default },
+	 { "SE_NONCU_ID", 9, 9, &umr_bitfield_default },
+	 { "SE_NONCU", 10, 10, &umr_bitfield_default },
+	 { "NON_SE", 11, 14, &umr_bitfield_default },
+	 { "DATA_REG_ID", 15, 16, &umr_bitfield_default },
+	 { "SPARE", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_CU_MASTER_MASK[] = {
+	 { "MASTER_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_NONCU_MASTER_MASK[] = {
+	 { "SE_MASTER_MASK", 0, 15, &umr_bitfield_default },
+	 { "GC_MASTER_MASK", 16, 16, &umr_bitfield_default },
+	 { "GC_GFX_MASTER_MASK", 17, 17, &umr_bitfield_default },
+	 { "TC0_MASTER_MASK", 18, 18, &umr_bitfield_default },
+	 { "TC1_MASTER_MASK", 19, 19, &umr_bitfield_default },
+	 { "SPARE0_MASTER_MASK", 20, 20, &umr_bitfield_default },
+	 { "SPARE1_MASTER_MASK", 21, 21, &umr_bitfield_default },
+	 { "SPARE2_MASTER_MASK", 22, 22, &umr_bitfield_default },
+	 { "SPARE3_MASTER_MASK", 23, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_CTRL[] = {
+	 { "BPM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE_COMMAND", 12, 12, &umr_bitfield_default },
+	 { "READ_COMMAND", 13, 13, &umr_bitfield_default },
+	 { "RDDATA_RESET", 14, 14, &umr_bitfield_default },
+	 { "SHORT_FORMAT", 15, 15, &umr_bitfield_default },
+	 { "BPM_DATA", 16, 25, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "RSVD_BPM_ADDR", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_CU_MASTER_BUSY[] = {
+	 { "BUSY_BUSY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_NONCU_MASTER_BUSY[] = {
+	 { "SE_MASTER_BUSY", 0, 15, &umr_bitfield_default },
+	 { "GC_MASTER_BUSY", 16, 16, &umr_bitfield_default },
+	 { "GC_GFX_MASTER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "TC0_MASTER_BUSY", 18, 18, &umr_bitfield_default },
+	 { "TC1_MASTER_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SPARE0_MASTER_BUSY", 20, 20, &umr_bitfield_default },
+	 { "SPARE1_MASTER_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SPARE2_MASTER_BUSY", 22, 22, &umr_bitfield_default },
+	 { "SPARE3_MASTER_BUSY", 23, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_CU_PD_TIMEOUT[] = {
+	 { "TIMEOUT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_SCRATCH_ADDR[] = {
+	 { "ADDR", 0, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_SCRATCH_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_STATIC_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_PERF_COUNT_0[] = {
+	 { "FEATURE_SEL", 0, 3, &umr_bitfield_default },
+	 { "SE_INDEX", 4, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 11, &umr_bitfield_default },
+	 { "CU_INDEX", 12, 15, &umr_bitfield_default },
+	 { "EVENT_SEL", 16, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 19, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_PERF_COUNT_1[] = {
+	 { "FEATURE_SEL", 0, 3, &umr_bitfield_default },
+	 { "SE_INDEX", 4, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 11, &umr_bitfield_default },
+	 { "CU_INDEX", 12, 15, &umr_bitfield_default },
+	 { "EVENT_SEL", 16, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 19, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_VMID[] = {
+	 { "RLC_SPM_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_INT_CNTL[] = {
+	 { "RLC_SPM_INT_CNTL", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_INT_STATUS[] = {
+	 { "RLC_SPM_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 14, &umr_bitfield_default },
+	 { "RLC_SPM_DEBUG_MODE", 15, 15, &umr_bitfield_default },
+	 { "RLC_SPM_NUM_SAMPLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_LOG_ADDR[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_MESSAGE[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_LOG_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_DELAY_3[] = {
+	 { "CGCG_ACTIVE_BEFORE_CGPG", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPR_REG1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPR_REG2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_LOG_CONT[] = {
+	 { "CONT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_INT_DISABLE_TH0[] = {
+	 { "DISABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_INT_DISABLE_TH1[] = {
+	 { "DISABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_INT_FORCE_TH0[] = {
+	 { "FORCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_INT_FORCE_TH1[] = {
+	 { "FORCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_CNTL[] = {
+	 { "SRM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCR_ADDR", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_ARAM_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_DRAM_ADDR[] = {
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_DRAM_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_GPM_COMMAND[] = {
+	 { "OP", 0, 0, &umr_bitfield_default },
+	 { "INDEX_CNTL", 1, 1, &umr_bitfield_default },
+	 { "INDEX_CNTL_NUM", 2, 4, &umr_bitfield_default },
+	 { "SIZE", 5, 16, &umr_bitfield_default },
+	 { "START_OFFSET", 17, 28, &umr_bitfield_default },
+	 { "RESERVED1", 29, 30, &umr_bitfield_default },
+	 { "DEST_MEMORY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_GPM_COMMAND_STATUS[] = {
+	 { "FIFO_EMPTY", 0, 0, &umr_bitfield_default },
+	 { "FIFO_FULL", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_RLCV_COMMAND[] = {
+	 { "OP", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 3, &umr_bitfield_default },
+	 { "SIZE", 4, 15, &umr_bitfield_default },
+	 { "START_OFFSET", 16, 27, &umr_bitfield_default },
+	 { "RESERVED1", 28, 30, &umr_bitfield_default },
+	 { "DEST_MEMORY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_RLCV_COMMAND_STATUS[] = {
+	 { "FIFO_EMPTY", 0, 0, &umr_bitfield_default },
+	 { "FIFO_FULL", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_0[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_1[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_2[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_3[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_4[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_5[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_6[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_7[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_STAT[] = {
+	 { "SRM_STATUS", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_GPM_ABORT[] = {
+	 { "ABORT", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CSIB_ADDR_LO[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CSIB_ADDR_HI[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CSIB_LENGTH[] = {
+	 { "LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_RESPONSE0[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_RESPONSE1[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_RESPONSE2[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_RESPONSE3[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_COMMAND[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_SCHEDULERS[] = {
+	 { "scheduler0", 0, 7, &umr_bitfield_default },
+	 { "scheduler1", 8, 15, &umr_bitfield_default },
+	 { "scheduler2", 16, 23, &umr_bitfield_default },
+	 { "scheduler3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG15[] = {
+	 { "vertval_bits_vertex_vertex_store_msb", 0, 15, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_2", 16, 20, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_1", 21, 25, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_0", 26, 30, &umr_bitfield_default },
+	 { "primic_to_clprim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG15[] = {
+	 { "cm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "counters_busy_q", 1, 1, &umr_bitfield_default },
+	 { "output_fifo_empty", 2, 2, &umr_bitfield_default },
+	 { "output_fifo_full", 3, 3, &umr_bitfield_default },
+	 { "counters_full", 4, 4, &umr_bitfield_default },
+	 { "active_sm_q", 5, 9, &umr_bitfield_default },
+	 { "entry_rdptr_q", 10, 14, &umr_bitfield_default },
+	 { "cntr_tbl_wrptr_q", 15, 19, &umr_bitfield_default },
+	 { "SPARE25", 20, 25, &umr_bitfield_default },
+	 { "st_cut_mode_q", 26, 27, &umr_bitfield_default },
+	 { "gs_done_array_q_not_0", 28, 28, &umr_bitfield_default },
+	 { "SPARE31", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_SM_CTRL_REG[] = {
+	 { "ON_SEQ_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_SEQ_DELAY", 4, 11, &umr_bitfield_default },
+	 { "MGCG_ENABLED", 12, 12, &umr_bitfield_default },
+	 { "BASE_MODE", 16, 16, &umr_bitfield_default },
+	 { "SM_MODE", 17, 19, &umr_bitfield_default },
+	 { "SM_MODE_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "OVERRIDE", 21, 21, &umr_bitfield_default },
+	 { "LS_OVERRIDE", 22, 22, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD_EN", 23, 23, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_RD_CTRL_REG[] = {
+	 { "ROW_MUX_SEL", 0, 4, &umr_bitfield_default },
+	 { "REG_MUX_SEL", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_RD_REG[] = {
+	 { "READ_DATA", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_USER_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SPI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "ALL_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "GRP3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "GRP2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "GRP1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "GRP0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_PC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "BACK_CLK_ON_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "FRONT_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_BCI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "CORE6_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "CORE5_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "CORE4_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_VGT_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "GS_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_IA_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_WD_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "ADC_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "RBIU_INPUT_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_PA_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SU_CLK_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CL_CLK_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_CLK_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SQ_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "PERFMON_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SQG_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "TTRACE_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "PERFMON_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_ALU_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TEX_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LDS_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_POWER_THROTTLE[] = {
+	 { "MIN_POWER", 0, 13, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 29, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_POWER_THROTTLE2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL1[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL2[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL3[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL4[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_CGTT_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CGTT_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_TCP_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_TCI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_GDS_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_CGTT_CLK_CTRL_0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CP_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CPF_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CPC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_RLC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_RADDR[] = {
+	 { "ME_RAM_RADDR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_DATA[] = {
+	 { "ME_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_BIST_CONTROL[] = {
+	 { "STOP_ON_FAIL_HW", 0, 0, &umr_bitfield_default },
+	 { "STOP_ON_FAIL_CU_HARV", 1, 1, &umr_bitfield_default },
+	 { "CU_HARV_LOOP_COUNT", 2, 5, &umr_bitfield_default },
+	 { "RESERVED", 7, 23, &umr_bitfield_default },
+	 { "GLOBAL_LOOP_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_ROM_CNTL[] = {
+	 { "USE_ROM", 0, 0, &umr_bitfield_default },
+	 { "SLP_MODE_EN", 1, 1, &umr_bitfield_default },
+	 { "EFUSE_DISTRIB_EN", 2, 2, &umr_bitfield_default },
+	 { "HELLOWORLD_EN", 3, 3, &umr_bitfield_default },
+	 { "CU_HARVEST_EN", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_HYP_GPM_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_HYP_GPM_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_HYP_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_HYP_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_HV_VMID_CTRL[] = {
+	 { "DEFAULT_VMID", 0, 3, &umr_bitfield_default },
+	 { "ALLOWED_VMID_MASK", 4, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_PIPE_PRIORITY[] = {
+	 { "HP_PIPE_SELECT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 15, &umr_bitfield_default },
+	 { "VF_NUM", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG1[] = {
+	 { "CMD_TYPE", 0, 3, &umr_bitfield_default },
+	 { "CMD_EXECUTE", 4, 4, &umr_bitfield_default },
+	 { "CMD_EXECUTE_INTR_EN", 5, 5, &umr_bitfield_default },
+	 { "RESERVED", 6, 7, &umr_bitfield_default },
+	 { "FCN_ID", 8, 15, &umr_bitfield_default },
+	 { "NEXT_FCN_ID", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG2[] = {
+	 { "CMD_STATUS", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG6[] = {
+	 { "CNTXT_SIZE", 0, 6, &umr_bitfield_default },
+	 { "CNTXT_LOCATION", 7, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 9, &umr_bitfield_default },
+	 { "CNTXT_OFFSET", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG8[] = {
+	 { "VM_BUSY_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG9[] = {
+	 { "ACTIVE_FCN_ID", 0, 7, &umr_bitfield_default },
+	 { "ACTIVE_FCN_ID_STATUS", 8, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG10[] = {
+	 { "TIME_QUANTA_PF", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG11[] = {
+	 { "YIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG12[] = {
+	 { "TIME_QUANTA_VF0", 0, 7, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF1", 8, 15, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF2", 16, 23, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG13[] = {
+	 { "TIME_QUANTA_VF4", 0, 7, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF5", 8, 15, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF6", 16, 23, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG14[] = {
+	 { "TIME_QUANTA_VF8", 0, 7, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF9", 8, 15, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF10", 16, 23, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_CFG_REG15[] = {
+	 { "TIME_QUANTA_VF12", 0, 7, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF13", 8, 15, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF14", 16, 23, &umr_bitfield_default },
+	 { "TIME_QUANTA_VF15", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_ACTIVE_FCN_ID[] = {
+	 { "VF_ID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 30, &umr_bitfield_default },
+	 { "PF_VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_VMID_THREAD2[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED0", 4, 7, &umr_bitfield_default },
+	 { "RLC_QUEUEID", 8, 10, &umr_bitfield_default },
+	 { "RESERVED1", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SCRATCH_ADDR[] = {
+	 { "ADDR", 0, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SCRATCH_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_F32_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_F32_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SDMA0_STATUS[] = {
+	 { "PREEMPTED", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 7, &umr_bitfield_default },
+	 { "SAVED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED1", 9, 11, &umr_bitfield_default },
+	 { "RESTORED", 12, 12, &umr_bitfield_default },
+	 { "RESERVED2", 13, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SDMA1_STATUS[] = {
+	 { "PREEMPTED", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 7, &umr_bitfield_default },
+	 { "SAVED", 8, 8, &umr_bitfield_default },
+	 { "RESERVED1", 9, 11, &umr_bitfield_default },
+	 { "RESTORED", 12, 12, &umr_bitfield_default },
+	 { "RESERVED2", 13, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SMU_RESPONSE[] = {
+	 { "RESP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_VIRT_RESET_REQ[] = {
+	 { "VF_FLR", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 30, &umr_bitfield_default },
+	 { "SOFT_PF_FLR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_RLC_RESPONSE[] = {
+	 { "RESP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_INT_DISABLE[] = {
+	 { "DISABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_INT_FORCE[] = {
+	 { "FORCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SDMA0_BUSY_STATUS[] = {
+	 { "VM_BUSY_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SDMA1_BUSY_STATUS[] = {
+	 { "VM_BUSY_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SCH_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SCH_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SCH_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SCH_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_SCH_INT[] = {
+	 { "interrupt", 0, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gfx80_regs.i b/src/lib/ip/gfx80_regs.i
new file mode 100644
index 0000000..2dfaf80
--- /dev/null
+++ b/src/lib/ip/gfx80_regs.i
@@ -0,0 +1,2742 @@
+	{ "ixCLIPPER_DEBUG_REG00", REG_SMC, 0x0, &ixCLIPPER_DEBUG_REG00[0], sizeof(ixCLIPPER_DEBUG_REG00)/sizeof(ixCLIPPER_DEBUG_REG00[0]), 0, 0 },
+	{ "ixPA_SC_DEBUG_REG0", REG_SMC, 0x0, &ixPA_SC_DEBUG_REG0[0], sizeof(ixPA_SC_DEBUG_REG0)/sizeof(ixPA_SC_DEBUG_REG0[0]), 0, 0 },
+	{ "mmCSPRIV_CONNECT", REG_MMIO, 0x0, &mmCSPRIV_CONNECT[0], sizeof(mmCSPRIV_CONNECT)/sizeof(mmCSPRIV_CONNECT[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG0", REG_SMC, 0x0, &ixWD_DEBUG_REG0[0], sizeof(ixWD_DEBUG_REG0)/sizeof(ixWD_DEBUG_REG0[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG01", REG_SMC, 0x1, &ixCLIPPER_DEBUG_REG01[0], sizeof(ixCLIPPER_DEBUG_REG01)/sizeof(ixCLIPPER_DEBUG_REG01[0]), 0, 0 },
+	{ "ixPA_SC_DEBUG_REG1", REG_SMC, 0x1, &ixPA_SC_DEBUG_REG1[0], sizeof(ixPA_SC_DEBUG_REG1)/sizeof(ixPA_SC_DEBUG_REG1[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG1", REG_SMC, 0x1, &ixGDS_DEBUG_REG1[0], sizeof(ixGDS_DEBUG_REG1)/sizeof(ixGDS_DEBUG_REG1[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG1", REG_SMC, 0x1, &ixWD_DEBUG_REG1[0], sizeof(ixWD_DEBUG_REG1)/sizeof(ixWD_DEBUG_REG1[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG16", REG_SMC, 0x10, &ixCLIPPER_DEBUG_REG16[0], sizeof(ixCLIPPER_DEBUG_REG16)/sizeof(ixCLIPPER_DEBUG_REG16[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT0_3", REG_SMC, 0x10, &ixDIDT_SQ_WEIGHT0_3[0], sizeof(ixDIDT_SQ_WEIGHT0_3)/sizeof(ixDIDT_SQ_WEIGHT0_3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG16", REG_SMC, 0x10, &ixVGT_DEBUG_REG16[0], sizeof(ixVGT_DEBUG_REG16)/sizeof(ixVGT_DEBUG_REG16[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG17", REG_SMC, 0x11, &ixCLIPPER_DEBUG_REG17[0], sizeof(ixCLIPPER_DEBUG_REG17)/sizeof(ixCLIPPER_DEBUG_REG17[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT4_7", REG_SMC, 0x11, &ixDIDT_SQ_WEIGHT4_7[0], sizeof(ixDIDT_SQ_WEIGHT4_7)/sizeof(ixDIDT_SQ_WEIGHT4_7[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG17", REG_SMC, 0x11, &ixVGT_DEBUG_REG17[0], sizeof(ixVGT_DEBUG_REG17)/sizeof(ixVGT_DEBUG_REG17[0]), 0, 0 },
+	{ "ixSQ_WAVE_MODE", REG_SMC, 0x11, &ixSQ_WAVE_MODE[0], sizeof(ixSQ_WAVE_MODE)/sizeof(ixSQ_WAVE_MODE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG18", REG_SMC, 0x12, &ixCLIPPER_DEBUG_REG18[0], sizeof(ixCLIPPER_DEBUG_REG18)/sizeof(ixCLIPPER_DEBUG_REG18[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT8_11", REG_SMC, 0x12, &ixDIDT_SQ_WEIGHT8_11[0], sizeof(ixDIDT_SQ_WEIGHT8_11)/sizeof(ixDIDT_SQ_WEIGHT8_11[0]), 0, 0 },
+	{ "ixSQ_WAVE_STATUS", REG_SMC, 0x12, &ixSQ_WAVE_STATUS[0], sizeof(ixSQ_WAVE_STATUS)/sizeof(ixSQ_WAVE_STATUS[0]), 0, 0 },
+	{ "mmGC_CAC_IND_INDEX", REG_MMIO, 0x129a, NULL, 0, 0, 0 },
+	{ "mmGC_CAC_IND_DATA", REG_MMIO, 0x129b, NULL, 0, 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG19", REG_SMC, 0x13, &ixCLIPPER_DEBUG_REG19[0], sizeof(ixCLIPPER_DEBUG_REG19)/sizeof(ixCLIPPER_DEBUG_REG19[0]), 0, 0 },
+	{ "ixSQ_WAVE_TRAPSTS", REG_SMC, 0x13, &ixSQ_WAVE_TRAPSTS[0], sizeof(ixSQ_WAVE_TRAPSTS)/sizeof(ixSQ_WAVE_TRAPSTS[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG0", REG_SMC, 0x14, &ixSXIFCCG_DEBUG_REG0[0], sizeof(ixSXIFCCG_DEBUG_REG0)/sizeof(ixSXIFCCG_DEBUG_REG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG20", REG_SMC, 0x14, &ixVGT_DEBUG_REG20[0], sizeof(ixVGT_DEBUG_REG20)/sizeof(ixVGT_DEBUG_REG20[0]), 0, 0 },
+	{ "ixSQ_WAVE_HW_ID", REG_SMC, 0x14, &ixSQ_WAVE_HW_ID[0], sizeof(ixSQ_WAVE_HW_ID)/sizeof(ixSQ_WAVE_HW_ID[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG1", REG_SMC, 0x15, &ixSXIFCCG_DEBUG_REG1[0], sizeof(ixSXIFCCG_DEBUG_REG1)/sizeof(ixSXIFCCG_DEBUG_REG1[0]), 0, 0 },
+	{ "ixSQ_WAVE_GPR_ALLOC", REG_SMC, 0x15, &ixSQ_WAVE_GPR_ALLOC[0], sizeof(ixSQ_WAVE_GPR_ALLOC)/sizeof(ixSQ_WAVE_GPR_ALLOC[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG21", REG_SMC, 0x15, &ixVGT_DEBUG_REG21[0], sizeof(ixVGT_DEBUG_REG21)/sizeof(ixVGT_DEBUG_REG21[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG2", REG_SMC, 0x16, &ixSXIFCCG_DEBUG_REG2[0], sizeof(ixSXIFCCG_DEBUG_REG2)/sizeof(ixSXIFCCG_DEBUG_REG2[0]), 0, 0 },
+	{ "ixSQ_WAVE_LDS_ALLOC", REG_SMC, 0x16, &ixSQ_WAVE_LDS_ALLOC[0], sizeof(ixSQ_WAVE_LDS_ALLOC)/sizeof(ixSQ_WAVE_LDS_ALLOC[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG22", REG_SMC, 0x16, &ixVGT_DEBUG_REG22[0], sizeof(ixVGT_DEBUG_REG22)/sizeof(ixVGT_DEBUG_REG22[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG3", REG_SMC, 0x17, &ixSXIFCCG_DEBUG_REG3[0], sizeof(ixSXIFCCG_DEBUG_REG3)/sizeof(ixSXIFCCG_DEBUG_REG3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG23", REG_SMC, 0x17, &ixVGT_DEBUG_REG23[0], sizeof(ixVGT_DEBUG_REG23)/sizeof(ixVGT_DEBUG_REG23[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_STS", REG_SMC, 0x17, &ixSQ_WAVE_IB_STS[0], sizeof(ixSQ_WAVE_IB_STS)/sizeof(ixSQ_WAVE_IB_STS[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG0", REG_SMC, 0x18, &ixSETUP_DEBUG_REG0[0], sizeof(ixSETUP_DEBUG_REG0)/sizeof(ixSETUP_DEBUG_REG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG24", REG_SMC, 0x18, &ixVGT_DEBUG_REG24[0], sizeof(ixVGT_DEBUG_REG24)/sizeof(ixVGT_DEBUG_REG24[0]), 0, 0 },
+	{ "ixSQ_WAVE_PC_LO", REG_SMC, 0x18, &ixSQ_WAVE_PC_LO[0], sizeof(ixSQ_WAVE_PC_LO)/sizeof(ixSQ_WAVE_PC_LO[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG1", REG_SMC, 0x19, &ixSETUP_DEBUG_REG1[0], sizeof(ixSETUP_DEBUG_REG1)/sizeof(ixSETUP_DEBUG_REG1[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG25", REG_SMC, 0x19, &ixVGT_DEBUG_REG25[0], sizeof(ixVGT_DEBUG_REG25)/sizeof(ixVGT_DEBUG_REG25[0]), 0, 0 },
+	{ "ixSQ_WAVE_PC_HI", REG_SMC, 0x19, &ixSQ_WAVE_PC_HI[0], sizeof(ixSQ_WAVE_PC_HI)/sizeof(ixSQ_WAVE_PC_HI[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG2", REG_SMC, 0x1a, &ixSETUP_DEBUG_REG2[0], sizeof(ixSETUP_DEBUG_REG2)/sizeof(ixSETUP_DEBUG_REG2[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG3", REG_SMC, 0x1b, &ixSETUP_DEBUG_REG3[0], sizeof(ixSETUP_DEBUG_REG3)/sizeof(ixSETUP_DEBUG_REG3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG27", REG_SMC, 0x1b, &ixVGT_DEBUG_REG27[0], sizeof(ixVGT_DEBUG_REG27)/sizeof(ixVGT_DEBUG_REG27[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG4", REG_SMC, 0x1c, &ixSETUP_DEBUG_REG4[0], sizeof(ixSETUP_DEBUG_REG4)/sizeof(ixSETUP_DEBUG_REG4[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_DBG0", REG_SMC, 0x1c, &ixSQ_WAVE_IB_DBG0[0], sizeof(ixSQ_WAVE_IB_DBG0)/sizeof(ixSQ_WAVE_IB_DBG0[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG5", REG_SMC, 0x1d, &ixSETUP_DEBUG_REG5[0], sizeof(ixSETUP_DEBUG_REG5)/sizeof(ixSETUP_DEBUG_REG5[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_DBG1", REG_SMC, 0x1d, &ixSQ_WAVE_IB_DBG1[0], sizeof(ixSQ_WAVE_IB_DBG1)/sizeof(ixSQ_WAVE_IB_DBG1[0]), 0, 0 },
+	{ "mmCSPRIV_THREAD_TRACE_TG0", REG_MMIO, 0x1e, &mmCSPRIV_THREAD_TRACE_TG0[0], sizeof(mmCSPRIV_THREAD_TRACE_TG0)/sizeof(mmCSPRIV_THREAD_TRACE_TG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG2", REG_SMC, 0x1e, &ixVGT_DEBUG_REG2[0], sizeof(ixVGT_DEBUG_REG2)/sizeof(ixVGT_DEBUG_REG2[0]), 0, 0 },
+	{ "mmCSPRIV_THREAD_TRACE_EVENT", REG_MMIO, 0x1f, &mmCSPRIV_THREAD_TRACE_EVENT[0], sizeof(mmCSPRIV_THREAD_TRACE_EVENT)/sizeof(mmCSPRIV_THREAD_TRACE_EVENT[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG3", REG_SMC, 0x1f, &ixVGT_DEBUG_REG3[0], sizeof(ixVGT_DEBUG_REG3)/sizeof(ixVGT_DEBUG_REG3[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG02", REG_SMC, 0x2, &ixCLIPPER_DEBUG_REG02[0], sizeof(ixCLIPPER_DEBUG_REG02)/sizeof(ixCLIPPER_DEBUG_REG02[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG2", REG_SMC, 0x2, &ixGDS_DEBUG_REG2[0], sizeof(ixGDS_DEBUG_REG2)/sizeof(ixGDS_DEBUG_REG2[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG2", REG_SMC, 0x2, &ixWD_DEBUG_REG2[0], sizeof(ixWD_DEBUG_REG2)/sizeof(ixWD_DEBUG_REG2[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG4", REG_SMC, 0x20, &ixVGT_DEBUG_REG4[0], sizeof(ixVGT_DEBUG_REG4)/sizeof(ixVGT_DEBUG_REG4[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL0", REG_SMC, 0x20, &ixDIDT_DB_CTRL0[0], sizeof(ixDIDT_DB_CTRL0)/sizeof(ixDIDT_DB_CTRL0[0]), 0, 0 },
+	{ "mmGRBM_CNTL", REG_MMIO, 0x2000, &mmGRBM_CNTL[0], sizeof(mmGRBM_CNTL)/sizeof(mmGRBM_CNTL[0]), 0, 0 },
+	{ "mmGRBM_SKEW_CNTL", REG_MMIO, 0x2001, &mmGRBM_SKEW_CNTL[0], sizeof(mmGRBM_SKEW_CNTL)/sizeof(mmGRBM_SKEW_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS2", REG_MMIO, 0x2002, &mmGRBM_STATUS2[0], sizeof(mmGRBM_STATUS2)/sizeof(mmGRBM_STATUS2[0]), 0, 0 },
+	{ "mmGRBM_PWR_CNTL", REG_MMIO, 0x2003, &mmGRBM_PWR_CNTL[0], sizeof(mmGRBM_PWR_CNTL)/sizeof(mmGRBM_PWR_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS", REG_MMIO, 0x2004, &mmGRBM_STATUS[0], sizeof(mmGRBM_STATUS)/sizeof(mmGRBM_STATUS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE0", REG_MMIO, 0x2005, &mmGRBM_STATUS_SE0[0], sizeof(mmGRBM_STATUS_SE0)/sizeof(mmGRBM_STATUS_SE0[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE1", REG_MMIO, 0x2006, &mmGRBM_STATUS_SE1[0], sizeof(mmGRBM_STATUS_SE1)/sizeof(mmGRBM_STATUS_SE1[0]), 0, 0 },
+	{ "mmGRBM_SOFT_RESET", REG_MMIO, 0x2008, &mmGRBM_SOFT_RESET[0], sizeof(mmGRBM_SOFT_RESET)/sizeof(mmGRBM_SOFT_RESET[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_CNTL", REG_MMIO, 0x2009, &mmGRBM_DEBUG_CNTL[0], sizeof(mmGRBM_DEBUG_CNTL)/sizeof(mmGRBM_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_DATA", REG_MMIO, 0x200a, &mmGRBM_DEBUG_DATA[0], sizeof(mmGRBM_DEBUG_DATA)/sizeof(mmGRBM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_GFX_CLKEN_CNTL", REG_MMIO, 0x200c, &mmGRBM_GFX_CLKEN_CNTL[0], sizeof(mmGRBM_GFX_CLKEN_CNTL)/sizeof(mmGRBM_GFX_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmGRBM_WAIT_IDLE_CLOCKS", REG_MMIO, 0x200d, &mmGRBM_WAIT_IDLE_CLOCKS[0], sizeof(mmGRBM_WAIT_IDLE_CLOCKS)/sizeof(mmGRBM_WAIT_IDLE_CLOCKS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE2", REG_MMIO, 0x200e, &mmGRBM_STATUS_SE2[0], sizeof(mmGRBM_STATUS_SE2)/sizeof(mmGRBM_STATUS_SE2[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE3", REG_MMIO, 0x200f, &mmGRBM_STATUS_SE3[0], sizeof(mmGRBM_STATUS_SE3)/sizeof(mmGRBM_STATUS_SE3[0]), 0, 0 },
+	{ "mmGRBM_DEBUG", REG_MMIO, 0x2014, &mmGRBM_DEBUG[0], sizeof(mmGRBM_DEBUG)/sizeof(mmGRBM_DEBUG[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x2015, &mmGRBM_DEBUG_SNAPSHOT[0], sizeof(mmGRBM_DEBUG_SNAPSHOT)/sizeof(mmGRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR", REG_MMIO, 0x2016, &mmGRBM_READ_ERROR[0], sizeof(mmGRBM_READ_ERROR)/sizeof(mmGRBM_READ_ERROR[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR2", REG_MMIO, 0x2017, &mmGRBM_READ_ERROR2[0], sizeof(mmGRBM_READ_ERROR2)/sizeof(mmGRBM_READ_ERROR2[0]), 0, 0 },
+	{ "mmGRBM_INT_CNTL", REG_MMIO, 0x2018, &mmGRBM_INT_CNTL[0], sizeof(mmGRBM_INT_CNTL)/sizeof(mmGRBM_INT_CNTL[0]), 0, 0 },
+	{ "mmGRBM_TRAP_OP", REG_MMIO, 0x2019, &mmGRBM_TRAP_OP[0], sizeof(mmGRBM_TRAP_OP)/sizeof(mmGRBM_TRAP_OP[0]), 0, 0 },
+	{ "mmGRBM_TRAP_ADDR", REG_MMIO, 0x201a, &mmGRBM_TRAP_ADDR[0], sizeof(mmGRBM_TRAP_ADDR)/sizeof(mmGRBM_TRAP_ADDR[0]), 0, 0 },
+	{ "mmGRBM_TRAP_ADDR_MSK", REG_MMIO, 0x201b, &mmGRBM_TRAP_ADDR_MSK[0], sizeof(mmGRBM_TRAP_ADDR_MSK)/sizeof(mmGRBM_TRAP_ADDR_MSK[0]), 0, 0 },
+	{ "mmGRBM_TRAP_WD", REG_MMIO, 0x201c, &mmGRBM_TRAP_WD[0], sizeof(mmGRBM_TRAP_WD)/sizeof(mmGRBM_TRAP_WD[0]), 0, 0 },
+	{ "mmGRBM_TRAP_WD_MSK", REG_MMIO, 0x201d, &mmGRBM_TRAP_WD_MSK[0], sizeof(mmGRBM_TRAP_WD_MSK)/sizeof(mmGRBM_TRAP_WD_MSK[0]), 0, 0 },
+	{ "mmGRBM_DSM_BYPASS", REG_MMIO, 0x201e, &mmGRBM_DSM_BYPASS[0], sizeof(mmGRBM_DSM_BYPASS)/sizeof(mmGRBM_DSM_BYPASS[0]), 0, 0 },
+	{ "mmGRBM_WRITE_ERROR", REG_MMIO, 0x201f, &mmGRBM_WRITE_ERROR[0], sizeof(mmGRBM_WRITE_ERROR)/sizeof(mmGRBM_WRITE_ERROR[0]), 0, 0 },
+	{ "mmDEBUG_INDEX", REG_MMIO, 0x203c, &mmDEBUG_INDEX[0], sizeof(mmDEBUG_INDEX)/sizeof(mmDEBUG_INDEX[0]), 0, 0 },
+	{ "mmDEBUG_DATA", REG_MMIO, 0x203d, &mmDEBUG_DATA[0], sizeof(mmDEBUG_DATA)/sizeof(mmDEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_NOWHERE", REG_MMIO, 0x203f, &mmGRBM_NOWHERE[0], sizeof(mmGRBM_NOWHERE)/sizeof(mmGRBM_NOWHERE[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG0", REG_MMIO, 0x2040, &mmGRBM_SCRATCH_REG0[0], sizeof(mmGRBM_SCRATCH_REG0)/sizeof(mmGRBM_SCRATCH_REG0[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG1", REG_MMIO, 0x2041, &mmGRBM_SCRATCH_REG1[0], sizeof(mmGRBM_SCRATCH_REG1)/sizeof(mmGRBM_SCRATCH_REG1[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG2", REG_MMIO, 0x2042, &mmGRBM_SCRATCH_REG2[0], sizeof(mmGRBM_SCRATCH_REG2)/sizeof(mmGRBM_SCRATCH_REG2[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG3", REG_MMIO, 0x2043, &mmGRBM_SCRATCH_REG3[0], sizeof(mmGRBM_SCRATCH_REG3)/sizeof(mmGRBM_SCRATCH_REG3[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG4", REG_MMIO, 0x2044, &mmGRBM_SCRATCH_REG4[0], sizeof(mmGRBM_SCRATCH_REG4)/sizeof(mmGRBM_SCRATCH_REG4[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG5", REG_MMIO, 0x2045, &mmGRBM_SCRATCH_REG5[0], sizeof(mmGRBM_SCRATCH_REG5)/sizeof(mmGRBM_SCRATCH_REG5[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG6", REG_MMIO, 0x2046, &mmGRBM_SCRATCH_REG6[0], sizeof(mmGRBM_SCRATCH_REG6)/sizeof(mmGRBM_SCRATCH_REG6[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG7", REG_MMIO, 0x2047, &mmGRBM_SCRATCH_REG7[0], sizeof(mmGRBM_SCRATCH_REG7)/sizeof(mmGRBM_SCRATCH_REG7[0]), 0, 0 },
+	{ "mmCP_CPC_STATUS", REG_MMIO, 0x2084, &mmCP_CPC_STATUS[0], sizeof(mmCP_CPC_STATUS)/sizeof(mmCP_CPC_STATUS[0]), 0, 0 },
+	{ "mmCP_CPC_BUSY_STAT", REG_MMIO, 0x2085, &mmCP_CPC_BUSY_STAT[0], sizeof(mmCP_CPC_BUSY_STAT)/sizeof(mmCP_CPC_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_CPC_STALLED_STAT1", REG_MMIO, 0x2086, &mmCP_CPC_STALLED_STAT1[0], sizeof(mmCP_CPC_STALLED_STAT1)/sizeof(mmCP_CPC_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_CPF_STATUS", REG_MMIO, 0x2087, &mmCP_CPF_STATUS[0], sizeof(mmCP_CPF_STATUS)/sizeof(mmCP_CPF_STATUS[0]), 0, 0 },
+	{ "mmCP_CPF_BUSY_STAT", REG_MMIO, 0x2088, &mmCP_CPF_BUSY_STAT[0], sizeof(mmCP_CPF_BUSY_STAT)/sizeof(mmCP_CPF_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_CPF_STALLED_STAT1", REG_MMIO, 0x2089, &mmCP_CPF_STALLED_STAT1[0], sizeof(mmCP_CPF_STALLED_STAT1)/sizeof(mmCP_CPF_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_CPC_GRBM_FREE_COUNT", REG_MMIO, 0x208b, &mmCP_CPC_GRBM_FREE_COUNT[0], sizeof(mmCP_CPC_GRBM_FREE_COUNT)/sizeof(mmCP_CPC_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_MEC_CNTL", REG_MMIO, 0x208d, &mmCP_MEC_CNTL[0], sizeof(mmCP_MEC_CNTL)/sizeof(mmCP_MEC_CNTL[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_HEADER_DUMP", REG_MMIO, 0x208e, &mmCP_MEC_ME1_HEADER_DUMP[0], sizeof(mmCP_MEC_ME1_HEADER_DUMP)/sizeof(mmCP_MEC_ME1_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_HEADER_DUMP", REG_MMIO, 0x208f, &mmCP_MEC_ME2_HEADER_DUMP[0], sizeof(mmCP_MEC_ME2_HEADER_DUMP)/sizeof(mmCP_MEC_ME2_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_CPC_SCRATCH_INDEX", REG_MMIO, 0x2090, &mmCP_CPC_SCRATCH_INDEX[0], sizeof(mmCP_CPC_SCRATCH_INDEX)/sizeof(mmCP_CPC_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_CPC_SCRATCH_DATA", REG_MMIO, 0x2091, &mmCP_CPC_SCRATCH_DATA[0], sizeof(mmCP_CPC_SCRATCH_DATA)/sizeof(mmCP_CPC_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_CPC_HALT_HYST_COUNT", REG_MMIO, 0x20a7, &mmCP_CPC_HALT_HYST_COUNT[0], sizeof(mmCP_CPC_HALT_HYST_COUNT)/sizeof(mmCP_CPC_HALT_HYST_COUNT[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL0", REG_MMIO, 0x20ad, &mmCP_PRT_LOD_STATS_CNTL0[0], sizeof(mmCP_PRT_LOD_STATS_CNTL0)/sizeof(mmCP_PRT_LOD_STATS_CNTL0[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL1", REG_MMIO, 0x20ae, &mmCP_PRT_LOD_STATS_CNTL1[0], sizeof(mmCP_PRT_LOD_STATS_CNTL1)/sizeof(mmCP_PRT_LOD_STATS_CNTL1[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL2", REG_MMIO, 0x20af, &mmCP_PRT_LOD_STATS_CNTL2[0], sizeof(mmCP_PRT_LOD_STATS_CNTL2)/sizeof(mmCP_PRT_LOD_STATS_CNTL2[0]), 0, 0 },
+	{ "ixSQ_INTERRUPT_WORD_AUTO", REG_SMC, 0x20c0, &ixSQ_INTERRUPT_WORD_AUTO[0], sizeof(ixSQ_INTERRUPT_WORD_AUTO)/sizeof(ixSQ_INTERRUPT_WORD_AUTO[0]), 0, 0 },
+	{ "ixSQ_INTERRUPT_WORD_CMN", REG_SMC, 0x20c0, &ixSQ_INTERRUPT_WORD_CMN[0], sizeof(ixSQ_INTERRUPT_WORD_CMN)/sizeof(ixSQ_INTERRUPT_WORD_CMN[0]), 0, 0 },
+	{ "mmCP_CE_COMPARE_COUNT", REG_MMIO, 0x20c0, &mmCP_CE_COMPARE_COUNT[0], sizeof(mmCP_CE_COMPARE_COUNT)/sizeof(mmCP_CE_COMPARE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_DE_COUNT", REG_MMIO, 0x20c1, &mmCP_CE_DE_COUNT[0], sizeof(mmCP_CE_DE_COUNT)/sizeof(mmCP_CE_DE_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_CE_COUNT", REG_MMIO, 0x20c2, &mmCP_DE_CE_COUNT[0], sizeof(mmCP_DE_CE_COUNT)/sizeof(mmCP_DE_CE_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_LAST_INVAL_COUNT", REG_MMIO, 0x20c3, &mmCP_DE_LAST_INVAL_COUNT[0], sizeof(mmCP_DE_LAST_INVAL_COUNT)/sizeof(mmCP_DE_LAST_INVAL_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_DE_COUNT", REG_MMIO, 0x20c4, &mmCP_DE_DE_COUNT[0], sizeof(mmCP_DE_DE_COUNT)/sizeof(mmCP_DE_DE_COUNT[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG5", REG_SMC, 0x21, &ixVGT_DEBUG_REG5[0], sizeof(ixVGT_DEBUG_REG5)/sizeof(ixVGT_DEBUG_REG5[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL1", REG_SMC, 0x21, &ixDIDT_DB_CTRL1[0], sizeof(ixDIDT_DB_CTRL1)/sizeof(ixDIDT_DB_CTRL1[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT3", REG_MMIO, 0x219c, &mmCP_STALLED_STAT3[0], sizeof(mmCP_STALLED_STAT3)/sizeof(mmCP_STALLED_STAT3[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT1", REG_MMIO, 0x219d, &mmCP_STALLED_STAT1[0], sizeof(mmCP_STALLED_STAT1)/sizeof(mmCP_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT2", REG_MMIO, 0x219e, &mmCP_STALLED_STAT2[0], sizeof(mmCP_STALLED_STAT2)/sizeof(mmCP_STALLED_STAT2[0]), 0, 0 },
+	{ "mmCP_BUSY_STAT", REG_MMIO, 0x219f, &mmCP_BUSY_STAT[0], sizeof(mmCP_BUSY_STAT)/sizeof(mmCP_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_STAT", REG_MMIO, 0x21a0, &mmCP_STAT[0], sizeof(mmCP_STAT)/sizeof(mmCP_STAT[0]), 0, 0 },
+	{ "mmCP_ME_HEADER_DUMP", REG_MMIO, 0x21a1, &mmCP_ME_HEADER_DUMP[0], sizeof(mmCP_ME_HEADER_DUMP)/sizeof(mmCP_ME_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_PFP_HEADER_DUMP", REG_MMIO, 0x21a2, &mmCP_PFP_HEADER_DUMP[0], sizeof(mmCP_PFP_HEADER_DUMP)/sizeof(mmCP_PFP_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_GRBM_FREE_COUNT", REG_MMIO, 0x21a3, &mmCP_GRBM_FREE_COUNT[0], sizeof(mmCP_GRBM_FREE_COUNT)/sizeof(mmCP_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_HEADER_DUMP", REG_MMIO, 0x21a4, &mmCP_CE_HEADER_DUMP[0], sizeof(mmCP_CE_HEADER_DUMP)/sizeof(mmCP_CE_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_CSF_STAT", REG_MMIO, 0x21b4, &mmCP_CSF_STAT[0], sizeof(mmCP_CSF_STAT)/sizeof(mmCP_CSF_STAT[0]), 0, 0 },
+	{ "mmCP_CSF_CNTL", REG_MMIO, 0x21b5, &mmCP_CSF_CNTL[0], sizeof(mmCP_CSF_CNTL)/sizeof(mmCP_CSF_CNTL[0]), 0, 0 },
+	{ "mmCP_ME_CNTL", REG_MMIO, 0x21b6, &mmCP_ME_CNTL[0], sizeof(mmCP_ME_CNTL)/sizeof(mmCP_ME_CNTL[0]), 0, 0 },
+	{ "mmCP_CNTX_STAT", REG_MMIO, 0x21b8, &mmCP_CNTX_STAT[0], sizeof(mmCP_CNTX_STAT)/sizeof(mmCP_CNTX_STAT[0]), 0, 0 },
+	{ "mmCP_ME_PREEMPTION", REG_MMIO, 0x21b9, &mmCP_ME_PREEMPTION[0], sizeof(mmCP_ME_PREEMPTION)/sizeof(mmCP_ME_PREEMPTION[0]), 0, 0 },
+	{ "mmCP_ROQ_THRESHOLDS", REG_MMIO, 0x21bc, &mmCP_ROQ_THRESHOLDS[0], sizeof(mmCP_ROQ_THRESHOLDS)/sizeof(mmCP_ROQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_STQ_THRESHOLD", REG_MMIO, 0x21bd, &mmCP_MEQ_STQ_THRESHOLD[0], sizeof(mmCP_MEQ_STQ_THRESHOLD)/sizeof(mmCP_MEQ_STQ_THRESHOLD[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR", REG_MMIO, 0x21be, &mmCP_RB2_RPTR[0], sizeof(mmCP_RB2_RPTR)/sizeof(mmCP_RB2_RPTR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR", REG_MMIO, 0x21bf, &mmCP_RB1_RPTR[0], sizeof(mmCP_RB1_RPTR)/sizeof(mmCP_RB1_RPTR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR", REG_MMIO, 0x21c0, &mmCP_RB0_RPTR[0], sizeof(mmCP_RB0_RPTR)/sizeof(mmCP_RB0_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_RPTR", REG_MMIO, 0x21c0, &mmCP_RB_RPTR[0], sizeof(mmCP_RB_RPTR)/sizeof(mmCP_RB_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_DELAY", REG_MMIO, 0x21c1, &mmCP_RB_WPTR_DELAY[0], sizeof(mmCP_RB_WPTR_DELAY)/sizeof(mmCP_RB_WPTR_DELAY[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_CNTL", REG_MMIO, 0x21c2, &mmCP_RB_WPTR_POLL_CNTL[0], sizeof(mmCP_RB_WPTR_POLL_CNTL)/sizeof(mmCP_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_ROQ1_THRESHOLDS", REG_MMIO, 0x21d5, &mmCP_ROQ1_THRESHOLDS[0], sizeof(mmCP_ROQ1_THRESHOLDS)/sizeof(mmCP_ROQ1_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ2_THRESHOLDS", REG_MMIO, 0x21d6, &mmCP_ROQ2_THRESHOLDS[0], sizeof(mmCP_ROQ2_THRESHOLDS)/sizeof(mmCP_ROQ2_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_STQ_THRESHOLDS", REG_MMIO, 0x21d7, &mmCP_STQ_THRESHOLDS[0], sizeof(mmCP_STQ_THRESHOLDS)/sizeof(mmCP_STQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_QUEUE_THRESHOLDS", REG_MMIO, 0x21d8, &mmCP_QUEUE_THRESHOLDS[0], sizeof(mmCP_QUEUE_THRESHOLDS)/sizeof(mmCP_QUEUE_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_THRESHOLDS", REG_MMIO, 0x21d9, &mmCP_MEQ_THRESHOLDS[0], sizeof(mmCP_MEQ_THRESHOLDS)/sizeof(mmCP_MEQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ_AVAIL", REG_MMIO, 0x21da, &mmCP_ROQ_AVAIL[0], sizeof(mmCP_ROQ_AVAIL)/sizeof(mmCP_ROQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_STQ_AVAIL", REG_MMIO, 0x21db, &mmCP_STQ_AVAIL[0], sizeof(mmCP_STQ_AVAIL)/sizeof(mmCP_STQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_ROQ2_AVAIL", REG_MMIO, 0x21dc, &mmCP_ROQ2_AVAIL[0], sizeof(mmCP_ROQ2_AVAIL)/sizeof(mmCP_ROQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_MEQ_AVAIL", REG_MMIO, 0x21dd, &mmCP_MEQ_AVAIL[0], sizeof(mmCP_MEQ_AVAIL)/sizeof(mmCP_MEQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_CMD_INDEX", REG_MMIO, 0x21de, &mmCP_CMD_INDEX[0], sizeof(mmCP_CMD_INDEX)/sizeof(mmCP_CMD_INDEX[0]), 0, 0 },
+	{ "mmCP_CMD_DATA", REG_MMIO, 0x21df, &mmCP_CMD_DATA[0], sizeof(mmCP_CMD_DATA)/sizeof(mmCP_CMD_DATA[0]), 0, 0 },
+	{ "mmCP_ROQ_RB_STAT", REG_MMIO, 0x21e0, &mmCP_ROQ_RB_STAT[0], sizeof(mmCP_ROQ_RB_STAT)/sizeof(mmCP_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB1_STAT", REG_MMIO, 0x21e1, &mmCP_ROQ_IB1_STAT[0], sizeof(mmCP_ROQ_IB1_STAT)/sizeof(mmCP_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB2_STAT", REG_MMIO, 0x21e2, &mmCP_ROQ_IB2_STAT[0], sizeof(mmCP_ROQ_IB2_STAT)/sizeof(mmCP_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_STAT", REG_MMIO, 0x21e3, &mmCP_STQ_STAT[0], sizeof(mmCP_STQ_STAT)/sizeof(mmCP_STQ_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_WR_STAT", REG_MMIO, 0x21e4, &mmCP_STQ_WR_STAT[0], sizeof(mmCP_STQ_WR_STAT)/sizeof(mmCP_STQ_WR_STAT[0]), 0, 0 },
+	{ "mmCP_MEQ_STAT", REG_MMIO, 0x21e5, &mmCP_MEQ_STAT[0], sizeof(mmCP_MEQ_STAT)/sizeof(mmCP_MEQ_STAT[0]), 0, 0 },
+	{ "mmCP_CEQ1_AVAIL", REG_MMIO, 0x21e6, &mmCP_CEQ1_AVAIL[0], sizeof(mmCP_CEQ1_AVAIL)/sizeof(mmCP_CEQ1_AVAIL[0]), 0, 0 },
+	{ "mmCP_CEQ2_AVAIL", REG_MMIO, 0x21e7, &mmCP_CEQ2_AVAIL[0], sizeof(mmCP_CEQ2_AVAIL)/sizeof(mmCP_CEQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_RB_STAT", REG_MMIO, 0x21e8, &mmCP_CE_ROQ_RB_STAT[0], sizeof(mmCP_CE_ROQ_RB_STAT)/sizeof(mmCP_CE_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB1_STAT", REG_MMIO, 0x21e9, &mmCP_CE_ROQ_IB1_STAT[0], sizeof(mmCP_CE_ROQ_IB1_STAT)/sizeof(mmCP_CE_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB2_STAT", REG_MMIO, 0x21ea, &mmCP_CE_ROQ_IB2_STAT[0], sizeof(mmCP_CE_ROQ_IB2_STAT)/sizeof(mmCP_CE_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_INT_STAT_DEBUG", REG_MMIO, 0x21f7, &mmCP_INT_STAT_DEBUG[0], sizeof(mmCP_INT_STAT_DEBUG)/sizeof(mmCP_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG6", REG_SMC, 0x22, &ixVGT_DEBUG_REG6[0], sizeof(ixVGT_DEBUG_REG6)/sizeof(ixVGT_DEBUG_REG6[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL2", REG_SMC, 0x22, &ixDIDT_DB_CTRL2[0], sizeof(ixDIDT_DB_CTRL2)/sizeof(ixDIDT_DB_CTRL2[0]), 0, 0 },
+	{ "mmVGT_VTX_VECT_EJECT_REG", REG_MMIO, 0x222c, &mmVGT_VTX_VECT_EJECT_REG[0], sizeof(mmVGT_VTX_VECT_EJECT_REG)/sizeof(mmVGT_VTX_VECT_EJECT_REG[0]), 0, 0 },
+	{ "mmVGT_DMA_DATA_FIFO_DEPTH", REG_MMIO, 0x222d, &mmVGT_DMA_DATA_FIFO_DEPTH[0], sizeof(mmVGT_DMA_DATA_FIFO_DEPTH)/sizeof(mmVGT_DMA_DATA_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DMA_REQ_FIFO_DEPTH", REG_MMIO, 0x222e, &mmVGT_DMA_REQ_FIFO_DEPTH[0], sizeof(mmVGT_DMA_REQ_FIFO_DEPTH)/sizeof(mmVGT_DMA_REQ_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DRAW_INIT_FIFO_DEPTH", REG_MMIO, 0x222f, &mmVGT_DRAW_INIT_FIFO_DEPTH[0], sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH)/sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_LAST_COPY_STATE", REG_MMIO, 0x2230, &mmVGT_LAST_COPY_STATE[0], sizeof(mmVGT_LAST_COPY_STATE)/sizeof(mmVGT_LAST_COPY_STATE[0]), 0, 0 },
+	{ "mmVGT_CACHE_INVALIDATION", REG_MMIO, 0x2231, &mmVGT_CACHE_INVALIDATION[0], sizeof(mmVGT_CACHE_INVALIDATION)/sizeof(mmVGT_CACHE_INVALIDATION[0]), 0, 0 },
+	{ "mmVGT_RESET_DEBUG", REG_MMIO, 0x2232, &mmVGT_RESET_DEBUG[0], sizeof(mmVGT_RESET_DEBUG)/sizeof(mmVGT_RESET_DEBUG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DELAY", REG_MMIO, 0x2233, &mmVGT_STRMOUT_DELAY[0], sizeof(mmVGT_STRMOUT_DELAY)/sizeof(mmVGT_STRMOUT_DELAY[0]), 0, 0 },
+	{ "mmVGT_FIFO_DEPTHS", REG_MMIO, 0x2234, &mmVGT_FIFO_DEPTHS[0], sizeof(mmVGT_FIFO_DEPTHS)/sizeof(mmVGT_FIFO_DEPTHS[0]), 0, 0 },
+	{ "mmVGT_GS_VERTEX_REUSE", REG_MMIO, 0x2235, &mmVGT_GS_VERTEX_REUSE[0], sizeof(mmVGT_GS_VERTEX_REUSE)/sizeof(mmVGT_GS_VERTEX_REUSE[0]), 0, 0 },
+	{ "mmVGT_MC_LAT_CNTL", REG_MMIO, 0x2236, &mmVGT_MC_LAT_CNTL[0], sizeof(mmVGT_MC_LAT_CNTL)/sizeof(mmVGT_MC_LAT_CNTL[0]), 0, 0 },
+	{ "mmIA_CNTL_STATUS", REG_MMIO, 0x2237, &mmIA_CNTL_STATUS[0], sizeof(mmIA_CNTL_STATUS)/sizeof(mmIA_CNTL_STATUS[0]), 0, 0 },
+	{ "mmVGT_DEBUG_CNTL", REG_MMIO, 0x2238, &mmVGT_DEBUG_CNTL[0], sizeof(mmVGT_DEBUG_CNTL)/sizeof(mmVGT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmVGT_DEBUG_DATA", REG_MMIO, 0x2239, &mmVGT_DEBUG_DATA[0], sizeof(mmVGT_DEBUG_DATA)/sizeof(mmVGT_DEBUG_DATA[0]), 0, 0 },
+	{ "mmIA_DEBUG_CNTL", REG_MMIO, 0x223a, &mmIA_DEBUG_CNTL[0], sizeof(mmIA_DEBUG_CNTL)/sizeof(mmIA_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmIA_DEBUG_DATA", REG_MMIO, 0x223b, &mmIA_DEBUG_DATA[0], sizeof(mmIA_DEBUG_DATA)/sizeof(mmIA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGT_CNTL_STATUS", REG_MMIO, 0x223c, &mmVGT_CNTL_STATUS[0], sizeof(mmVGT_CNTL_STATUS)/sizeof(mmVGT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmWD_DEBUG_CNTL", REG_MMIO, 0x223d, &mmWD_DEBUG_CNTL[0], sizeof(mmWD_DEBUG_CNTL)/sizeof(mmWD_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmWD_DEBUG_DATA", REG_MMIO, 0x223e, &mmWD_DEBUG_DATA[0], sizeof(mmWD_DEBUG_DATA)/sizeof(mmWD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmWD_CNTL_STATUS", REG_MMIO, 0x223f, &mmWD_CNTL_STATUS[0], sizeof(mmWD_CNTL_STATUS)/sizeof(mmWD_CNTL_STATUS[0]), 0, 0 },
+	{ "mmCC_GC_PRIM_CONFIG", REG_MMIO, 0x2240, &mmCC_GC_PRIM_CONFIG[0], sizeof(mmCC_GC_PRIM_CONFIG)/sizeof(mmCC_GC_PRIM_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_PRIM_CONFIG", REG_MMIO, 0x2241, &mmGC_USER_PRIM_CONFIG[0], sizeof(mmGC_USER_PRIM_CONFIG)/sizeof(mmGC_USER_PRIM_CONFIG[0]), 0, 0 },
+	{ "mmWD_QOS", REG_MMIO, 0x2242, &mmWD_QOS[0], sizeof(mmWD_QOS)/sizeof(mmWD_QOS[0]), 0, 0 },
+	{ "mmVGT_SYS_CONFIG", REG_MMIO, 0x2263, &mmVGT_SYS_CONFIG[0], sizeof(mmVGT_SYS_CONFIG)/sizeof(mmVGT_SYS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_VS_MAX_WAVE_ID", REG_MMIO, 0x2268, &mmVGT_VS_MAX_WAVE_ID[0], sizeof(mmVGT_VS_MAX_WAVE_ID)/sizeof(mmVGT_VS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmGFX_PIPE_CONTROL", REG_MMIO, 0x226d, &mmGFX_PIPE_CONTROL[0], sizeof(mmGFX_PIPE_CONTROL)/sizeof(mmGFX_PIPE_CONTROL[0]), 0, 0 },
+	{ "mmCC_GC_SHADER_ARRAY_CONFIG", REG_MMIO, 0x226f, &mmCC_GC_SHADER_ARRAY_CONFIG[0], sizeof(mmCC_GC_SHADER_ARRAY_CONFIG)/sizeof(mmCC_GC_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_SHADER_ARRAY_CONFIG", REG_MMIO, 0x2270, &mmGC_USER_SHADER_ARRAY_CONFIG[0], sizeof(mmGC_USER_SHADER_ARRAY_CONFIG)/sizeof(mmGC_USER_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmVGT_DMA_PRIMITIVE_TYPE", REG_MMIO, 0x2271, &mmVGT_DMA_PRIMITIVE_TYPE[0], sizeof(mmVGT_DMA_PRIMITIVE_TYPE)/sizeof(mmVGT_DMA_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_DMA_CONTROL", REG_MMIO, 0x2272, &mmVGT_DMA_CONTROL[0], sizeof(mmVGT_DMA_CONTROL)/sizeof(mmVGT_DMA_CONTROL[0]), 0, 0 },
+	{ "mmVGT_DMA_LS_HS_CONFIG", REG_MMIO, 0x2273, &mmVGT_DMA_LS_HS_CONFIG[0], sizeof(mmVGT_DMA_LS_HS_CONFIG)/sizeof(mmVGT_DMA_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_CNTL", REG_MMIO, 0x2280, &mmPA_SU_DEBUG_CNTL[0], sizeof(mmPA_SU_DEBUG_CNTL)/sizeof(mmPA_SU_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_DATA", REG_MMIO, 0x2281, &mmPA_SU_DEBUG_DATA[0], sizeof(mmPA_SU_DEBUG_DATA)/sizeof(mmPA_SU_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_CL_CNTL_STATUS", REG_MMIO, 0x2284, &mmPA_CL_CNTL_STATUS[0], sizeof(mmPA_CL_CNTL_STATUS)/sizeof(mmPA_CL_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_CL_ENHANCE", REG_MMIO, 0x2285, &mmPA_CL_ENHANCE[0], sizeof(mmPA_CL_ENHANCE)/sizeof(mmPA_CL_ENHANCE[0]), 0, 0 },
+	{ "mmPA_CL_RESET_DEBUG", REG_MMIO, 0x2286, &mmPA_CL_RESET_DEBUG[0], sizeof(mmPA_CL_RESET_DEBUG)/sizeof(mmPA_CL_RESET_DEBUG[0]), 0, 0 },
+	{ "mmPA_SU_CNTL_STATUS", REG_MMIO, 0x2294, &mmPA_SU_CNTL_STATUS[0], sizeof(mmPA_SU_CNTL_STATUS)/sizeof(mmPA_SU_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_DEPTH_CNTL", REG_MMIO, 0x2295, &mmPA_SC_FIFO_DEPTH_CNTL[0], sizeof(mmPA_SC_FIFO_DEPTH_CNTL)/sizeof(mmPA_SC_FIFO_DEPTH_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c0, &mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c1, &mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c2, &mmPA_SC_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_FORCE_EOV_MAX_CNTS", REG_MMIO, 0x22c9, &mmPA_SC_FORCE_EOV_MAX_CNTS[0], sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS)/sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_SIZE", REG_MMIO, 0x22f3, &mmPA_SC_FIFO_SIZE[0], sizeof(mmPA_SC_FIFO_SIZE)/sizeof(mmPA_SC_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_IF_FIFO_SIZE", REG_MMIO, 0x22f5, &mmPA_SC_IF_FIFO_SIZE[0], sizeof(mmPA_SC_IF_FIFO_SIZE)/sizeof(mmPA_SC_IF_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_CNTL", REG_MMIO, 0x22f6, &mmPA_SC_DEBUG_CNTL[0], sizeof(mmPA_SC_DEBUG_CNTL)/sizeof(mmPA_SC_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_DATA", REG_MMIO, 0x22f7, &mmPA_SC_DEBUG_DATA[0], sizeof(mmPA_SC_DEBUG_DATA)/sizeof(mmPA_SC_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_SC_ENHANCE", REG_MMIO, 0x22fc, &mmPA_SC_ENHANCE[0], sizeof(mmPA_SC_ENHANCE)/sizeof(mmPA_SC_ENHANCE[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL_OCP", REG_SMC, 0x23, &ixDIDT_DB_CTRL_OCP[0], sizeof(ixDIDT_DB_CTRL_OCP)/sizeof(ixDIDT_DB_CTRL_OCP[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG7", REG_SMC, 0x23, &ixVGT_DEBUG_REG7[0], sizeof(ixVGT_DEBUG_REG7)/sizeof(ixVGT_DEBUG_REG7[0]), 0, 0 },
+	{ "mmSQ_CONFIG", REG_MMIO, 0x2300, &mmSQ_CONFIG[0], sizeof(mmSQ_CONFIG)/sizeof(mmSQ_CONFIG[0]), 0, 0 },
+	{ "mmSQC_CONFIG", REG_MMIO, 0x2301, &mmSQC_CONFIG[0], sizeof(mmSQC_CONFIG)/sizeof(mmSQC_CONFIG[0]), 0, 0 },
+	{ "mmSQ_RANDOM_WAVE_PRI", REG_MMIO, 0x2303, &mmSQ_RANDOM_WAVE_PRI[0], sizeof(mmSQ_RANDOM_WAVE_PRI)/sizeof(mmSQ_RANDOM_WAVE_PRI[0]), 0, 0 },
+	{ "mmSQ_REG_CREDITS", REG_MMIO, 0x2304, &mmSQ_REG_CREDITS[0], sizeof(mmSQ_REG_CREDITS)/sizeof(mmSQ_REG_CREDITS[0]), 0, 0 },
+	{ "mmSQ_FIFO_SIZES", REG_MMIO, 0x2305, &mmSQ_FIFO_SIZES[0], sizeof(mmSQ_FIFO_SIZES)/sizeof(mmSQ_FIFO_SIZES[0]), 0, 0 },
+	{ "mmSQ_DSM_CNTL", REG_MMIO, 0x2306, &mmSQ_DSM_CNTL[0], sizeof(mmSQ_DSM_CNTL)/sizeof(mmSQ_DSM_CNTL[0]), 0, 0 },
+	{ "mmCC_SQC_BANK_DISABLE", REG_MMIO, 0x2307, &mmCC_SQC_BANK_DISABLE[0], sizeof(mmCC_SQC_BANK_DISABLE)/sizeof(mmCC_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmUSER_SQC_BANK_DISABLE", REG_MMIO, 0x2308, &mmUSER_SQC_BANK_DISABLE[0], sizeof(mmUSER_SQC_BANK_DISABLE)/sizeof(mmUSER_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL", REG_MMIO, 0x2309, &mmSQ_DEBUG_STS_GLOBAL[0], sizeof(mmSQ_DEBUG_STS_GLOBAL)/sizeof(mmSQ_DEBUG_STS_GLOBAL[0]), 0, 0 },
+	{ "mmSH_MEM_BASES", REG_MMIO, 0x230a, &mmSH_MEM_BASES[0], sizeof(mmSH_MEM_BASES)/sizeof(mmSH_MEM_BASES[0]), 0, 0 },
+	{ "mmSH_MEM_APE1_BASE", REG_MMIO, 0x230b, &mmSH_MEM_APE1_BASE[0], sizeof(mmSH_MEM_APE1_BASE)/sizeof(mmSH_MEM_APE1_BASE[0]), 0, 0 },
+	{ "mmSH_MEM_APE1_LIMIT", REG_MMIO, 0x230c, &mmSH_MEM_APE1_LIMIT[0], sizeof(mmSH_MEM_APE1_LIMIT)/sizeof(mmSH_MEM_APE1_LIMIT[0]), 0, 0 },
+	{ "mmSH_MEM_CONFIG", REG_MMIO, 0x230d, &mmSH_MEM_CONFIG[0], sizeof(mmSH_MEM_CONFIG)/sizeof(mmSH_MEM_CONFIG[0]), 0, 0 },
+	{ "mmSQC_DSM_CNTL", REG_MMIO, 0x230f, &mmSQC_DSM_CNTL[0], sizeof(mmSQC_DSM_CNTL)/sizeof(mmSQC_DSM_CNTL[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL2", REG_MMIO, 0x2310, &mmSQ_DEBUG_STS_GLOBAL2[0], sizeof(mmSQ_DEBUG_STS_GLOBAL2)/sizeof(mmSQ_DEBUG_STS_GLOBAL2[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL3", REG_MMIO, 0x2311, &mmSQ_DEBUG_STS_GLOBAL3[0], sizeof(mmSQ_DEBUG_STS_GLOBAL3)/sizeof(mmSQ_DEBUG_STS_GLOBAL3[0]), 0, 0 },
+	{ "mmCC_GC_SHADER_RATE_CONFIG", REG_MMIO, 0x2312, &mmCC_GC_SHADER_RATE_CONFIG[0], sizeof(mmCC_GC_SHADER_RATE_CONFIG)/sizeof(mmCC_GC_SHADER_RATE_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_SHADER_RATE_CONFIG", REG_MMIO, 0x2313, &mmGC_USER_SHADER_RATE_CONFIG[0], sizeof(mmGC_USER_SHADER_RATE_CONFIG)/sizeof(mmGC_USER_SHADER_RATE_CONFIG[0]), 0, 0 },
+	{ "mmSQ_INTERRUPT_AUTO_MASK", REG_MMIO, 0x2314, &mmSQ_INTERRUPT_AUTO_MASK[0], sizeof(mmSQ_INTERRUPT_AUTO_MASK)/sizeof(mmSQ_INTERRUPT_AUTO_MASK[0]), 0, 0 },
+	{ "mmSQ_INTERRUPT_MSG_CTRL", REG_MMIO, 0x2315, &mmSQ_INTERRUPT_MSG_CTRL[0], sizeof(mmSQ_INTERRUPT_MSG_CTRL)/sizeof(mmSQ_INTERRUPT_MSG_CTRL[0]), 0, 0 },
+	{ "mmSQ_REG_TIMESTAMP", REG_MMIO, 0x2374, &mmSQ_REG_TIMESTAMP[0], sizeof(mmSQ_REG_TIMESTAMP)/sizeof(mmSQ_REG_TIMESTAMP[0]), 0, 0 },
+	{ "mmSQ_CMD_TIMESTAMP", REG_MMIO, 0x2375, &mmSQ_CMD_TIMESTAMP[0], sizeof(mmSQ_CMD_TIMESTAMP)/sizeof(mmSQ_CMD_TIMESTAMP[0]), 0, 0 },
+	{ "mmSQ_IND_INDEX", REG_MMIO, 0x2378, &mmSQ_IND_INDEX[0], sizeof(mmSQ_IND_INDEX)/sizeof(mmSQ_IND_INDEX[0]), 0, 0 },
+	{ "mmSQ_IND_DATA", REG_MMIO, 0x2379, &mmSQ_IND_DATA[0], sizeof(mmSQ_IND_DATA)/sizeof(mmSQ_IND_DATA[0]), 0, 0 },
+	{ "mmSQ_CMD", REG_MMIO, 0x237b, &mmSQ_CMD[0], sizeof(mmSQ_CMD)/sizeof(mmSQ_CMD[0]), 0, 0 },
+	{ "mmSQ_TIME_HI", REG_MMIO, 0x237c, &mmSQ_TIME_HI[0], sizeof(mmSQ_TIME_HI)/sizeof(mmSQ_TIME_HI[0]), 0, 0 },
+	{ "mmSQ_TIME_LO", REG_MMIO, 0x237d, &mmSQ_TIME_LO[0], sizeof(mmSQ_TIME_LO)/sizeof(mmSQ_TIME_LO[0]), 0, 0 },
+	{ "mmSQ_VOP3_0_SDST_ENC", REG_MMIO, 0x237f, &mmSQ_VOP3_0_SDST_ENC[0], sizeof(mmSQ_VOP3_0_SDST_ENC)/sizeof(mmSQ_VOP3_0_SDST_ENC[0]), 0, 0 },
+	{ "mmSQ_VOP_SDWA", REG_MMIO, 0x237f, &mmSQ_VOP_SDWA[0], sizeof(mmSQ_VOP_SDWA)/sizeof(mmSQ_VOP_SDWA[0]), 0, 0 },
+	{ "mmSQ_MTBUF_1", REG_MMIO, 0x237f, &mmSQ_MTBUF_1[0], sizeof(mmSQ_MTBUF_1)/sizeof(mmSQ_MTBUF_1[0]), 0, 0 },
+	{ "mmSQ_SMEM_1", REG_MMIO, 0x237f, &mmSQ_SMEM_1[0], sizeof(mmSQ_SMEM_1)/sizeof(mmSQ_SMEM_1[0]), 0, 0 },
+	{ "mmSQ_EXP_1", REG_MMIO, 0x237f, &mmSQ_EXP_1[0], sizeof(mmSQ_EXP_1)/sizeof(mmSQ_EXP_1[0]), 0, 0 },
+	{ "mmSQ_SOP2", REG_MMIO, 0x237f, &mmSQ_SOP2[0], sizeof(mmSQ_SOP2)/sizeof(mmSQ_SOP2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CNTR", REG_MMIO, 0x2390, &mmSQ_THREAD_TRACE_CNTR[0], sizeof(mmSQ_THREAD_TRACE_CNTR)/sizeof(mmSQ_THREAD_TRACE_CNTR[0]), 0, 0 },
+	{ "mmSQ_LB_CTR_CTRL", REG_MMIO, 0x2398, &mmSQ_LB_CTR_CTRL[0], sizeof(mmSQ_LB_CTR_CTRL)/sizeof(mmSQ_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_CYCLES", REG_MMIO, 0x2399, &mmSQ_LB_DATA_ALU_CYCLES[0], sizeof(mmSQ_LB_DATA_ALU_CYCLES)/sizeof(mmSQ_LB_DATA_ALU_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_CYCLES", REG_MMIO, 0x239a, &mmSQ_LB_DATA_TEX_CYCLES[0], sizeof(mmSQ_LB_DATA_TEX_CYCLES)/sizeof(mmSQ_LB_DATA_TEX_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_STALLS", REG_MMIO, 0x239b, &mmSQ_LB_DATA_ALU_STALLS[0], sizeof(mmSQ_LB_DATA_ALU_STALLS)/sizeof(mmSQ_LB_DATA_ALU_STALLS[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_STALLS", REG_MMIO, 0x239c, &mmSQ_LB_DATA_TEX_STALLS[0], sizeof(mmSQ_LB_DATA_TEX_STALLS)/sizeof(mmSQ_LB_DATA_TEX_STALLS[0]), 0, 0 },
+	{ "mmSQC_EDC_CNT", REG_MMIO, 0x23a0, &mmSQC_EDC_CNT[0], sizeof(mmSQC_EDC_CNT)/sizeof(mmSQC_EDC_CNT[0]), 0, 0 },
+	{ "mmSQ_EDC_SEC_CNT", REG_MMIO, 0x23a1, &mmSQ_EDC_SEC_CNT[0], sizeof(mmSQ_EDC_SEC_CNT)/sizeof(mmSQ_EDC_SEC_CNT[0]), 0, 0 },
+	{ "mmSQ_EDC_DED_CNT", REG_MMIO, 0x23a2, &mmSQ_EDC_DED_CNT[0], sizeof(mmSQ_EDC_DED_CNT)/sizeof(mmSQ_EDC_DED_CNT[0]), 0, 0 },
+	{ "mmSQ_EDC_INFO", REG_MMIO, 0x23a3, &mmSQ_EDC_INFO[0], sizeof(mmSQ_EDC_INFO)/sizeof(mmSQ_EDC_INFO[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_WAVE_START", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_WAVE_START[0], sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START)/sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_EVENT", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_EVENT[0], sizeof(mmSQ_THREAD_TRACE_WORD_EVENT)/sizeof(mmSQ_THREAD_TRACE_WORD_EVENT[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST)/sizeof(mmSQ_THREAD_TRACE_WORD_INST[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_CMN", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_CMN[0], sizeof(mmSQ_THREAD_TRACE_WORD_CMN)/sizeof(mmSQ_THREAD_TRACE_WORD_CMN[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_WREXEC_EXEC_LO", REG_MMIO, 0x23b1, &mmSQ_WREXEC_EXEC_LO[0], sizeof(mmSQ_WREXEC_EXEC_LO)/sizeof(mmSQ_WREXEC_EXEC_LO[0]), 0, 0 },
+	{ "mmSQC_GATCL1_CNTL", REG_MMIO, 0x23b2, &mmSQC_GATCL1_CNTL[0], sizeof(mmSQC_GATCL1_CNTL)/sizeof(mmSQC_GATCL1_CNTL[0]), 0, 0 },
+	{ "mmSQC_ATC_EDC_GATCL1_CNT", REG_MMIO, 0x23b3, &mmSQC_ATC_EDC_GATCL1_CNT[0], sizeof(mmSQC_ATC_EDC_GATCL1_CNT)/sizeof(mmSQC_ATC_EDC_GATCL1_CNT[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD0", REG_MMIO, 0x23c0, &mmSQ_BUF_RSRC_WORD0[0], sizeof(mmSQ_BUF_RSRC_WORD0)/sizeof(mmSQ_BUF_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD1", REG_MMIO, 0x23c1, &mmSQ_BUF_RSRC_WORD1[0], sizeof(mmSQ_BUF_RSRC_WORD1)/sizeof(mmSQ_BUF_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD2", REG_MMIO, 0x23c2, &mmSQ_BUF_RSRC_WORD2[0], sizeof(mmSQ_BUF_RSRC_WORD2)/sizeof(mmSQ_BUF_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD3", REG_MMIO, 0x23c3, &mmSQ_BUF_RSRC_WORD3[0], sizeof(mmSQ_BUF_RSRC_WORD3)/sizeof(mmSQ_BUF_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD0", REG_MMIO, 0x23c4, &mmSQ_IMG_RSRC_WORD0[0], sizeof(mmSQ_IMG_RSRC_WORD0)/sizeof(mmSQ_IMG_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD1", REG_MMIO, 0x23c5, &mmSQ_IMG_RSRC_WORD1[0], sizeof(mmSQ_IMG_RSRC_WORD1)/sizeof(mmSQ_IMG_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD2", REG_MMIO, 0x23c6, &mmSQ_IMG_RSRC_WORD2[0], sizeof(mmSQ_IMG_RSRC_WORD2)/sizeof(mmSQ_IMG_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD3", REG_MMIO, 0x23c7, &mmSQ_IMG_RSRC_WORD3[0], sizeof(mmSQ_IMG_RSRC_WORD3)/sizeof(mmSQ_IMG_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD4", REG_MMIO, 0x23c8, &mmSQ_IMG_RSRC_WORD4[0], sizeof(mmSQ_IMG_RSRC_WORD4)/sizeof(mmSQ_IMG_RSRC_WORD4[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD5", REG_MMIO, 0x23c9, &mmSQ_IMG_RSRC_WORD5[0], sizeof(mmSQ_IMG_RSRC_WORD5)/sizeof(mmSQ_IMG_RSRC_WORD5[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD6", REG_MMIO, 0x23ca, &mmSQ_IMG_RSRC_WORD6[0], sizeof(mmSQ_IMG_RSRC_WORD6)/sizeof(mmSQ_IMG_RSRC_WORD6[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD7", REG_MMIO, 0x23cb, &mmSQ_IMG_RSRC_WORD7[0], sizeof(mmSQ_IMG_RSRC_WORD7)/sizeof(mmSQ_IMG_RSRC_WORD7[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD0", REG_MMIO, 0x23cc, &mmSQ_IMG_SAMP_WORD0[0], sizeof(mmSQ_IMG_SAMP_WORD0)/sizeof(mmSQ_IMG_SAMP_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD1", REG_MMIO, 0x23cd, &mmSQ_IMG_SAMP_WORD1[0], sizeof(mmSQ_IMG_SAMP_WORD1)/sizeof(mmSQ_IMG_SAMP_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD2", REG_MMIO, 0x23ce, &mmSQ_IMG_SAMP_WORD2[0], sizeof(mmSQ_IMG_SAMP_WORD2)/sizeof(mmSQ_IMG_SAMP_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD3", REG_MMIO, 0x23cf, &mmSQ_IMG_SAMP_WORD3[0], sizeof(mmSQ_IMG_SAMP_WORD3)/sizeof(mmSQ_IMG_SAMP_WORD3[0]), 0, 0 },
+	{ "mmSQ_FLAT_SCRATCH_WORD0", REG_MMIO, 0x23d0, &mmSQ_FLAT_SCRATCH_WORD0[0], sizeof(mmSQ_FLAT_SCRATCH_WORD0)/sizeof(mmSQ_FLAT_SCRATCH_WORD0[0]), 0, 0 },
+	{ "mmSQ_FLAT_SCRATCH_WORD1", REG_MMIO, 0x23d1, &mmSQ_FLAT_SCRATCH_WORD1[0], sizeof(mmSQ_FLAT_SCRATCH_WORD1)/sizeof(mmSQ_FLAT_SCRATCH_WORD1[0]), 0, 0 },
+	{ "mmSQ_M0_GPR_IDX_WORD", REG_MMIO, 0x23d2, &mmSQ_M0_GPR_IDX_WORD[0], sizeof(mmSQ_M0_GPR_IDX_WORD)/sizeof(mmSQ_M0_GPR_IDX_WORD[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG26", REG_SMC, 0x24, &ixVGT_DEBUG_REG26[0], sizeof(ixVGT_DEBUG_REG26)/sizeof(ixVGT_DEBUG_REG26[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY", REG_MMIO, 0x2414, &mmSX_DEBUG_BUSY[0], sizeof(mmSX_DEBUG_BUSY)/sizeof(mmSX_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_2", REG_MMIO, 0x2415, &mmSX_DEBUG_BUSY_2[0], sizeof(mmSX_DEBUG_BUSY_2)/sizeof(mmSX_DEBUG_BUSY_2[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_3", REG_MMIO, 0x2416, &mmSX_DEBUG_BUSY_3[0], sizeof(mmSX_DEBUG_BUSY_3)/sizeof(mmSX_DEBUG_BUSY_3[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_4", REG_MMIO, 0x2417, &mmSX_DEBUG_BUSY_4[0], sizeof(mmSX_DEBUG_BUSY_4)/sizeof(mmSX_DEBUG_BUSY_4[0]), 0, 0 },
+	{ "mmSX_DEBUG_1", REG_MMIO, 0x2418, &mmSX_DEBUG_1[0], sizeof(mmSX_DEBUG_1)/sizeof(mmSX_DEBUG_1[0]), 0, 0 },
+	{ "mmSPI_PS_MAX_WAVE_ID", REG_MMIO, 0x243a, &mmSPI_PS_MAX_WAVE_ID[0], sizeof(mmSPI_PS_MAX_WAVE_ID)/sizeof(mmSPI_PS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmSPI_START_PHASE", REG_MMIO, 0x243b, &mmSPI_START_PHASE[0], sizeof(mmSPI_START_PHASE)/sizeof(mmSPI_START_PHASE[0]), 0, 0 },
+	{ "mmSPI_GFX_CNTL", REG_MMIO, 0x243c, &mmSPI_GFX_CNTL[0], sizeof(mmSPI_GFX_CNTL)/sizeof(mmSPI_GFX_CNTL[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL", REG_MMIO, 0x2440, &mmSPI_CONFIG_CNTL[0], sizeof(mmSPI_CONFIG_CNTL)/sizeof(mmSPI_CONFIG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_CNTL", REG_MMIO, 0x2441, &mmSPI_DEBUG_CNTL[0], sizeof(mmSPI_DEBUG_CNTL)/sizeof(mmSPI_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_READ", REG_MMIO, 0x2442, &mmSPI_DEBUG_READ[0], sizeof(mmSPI_DEBUG_READ)/sizeof(mmSPI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_DSM_CNTL", REG_MMIO, 0x2443, &mmSPI_DSM_CNTL[0], sizeof(mmSPI_DSM_CNTL)/sizeof(mmSPI_DSM_CNTL[0]), 0, 0 },
+	{ "mmSPI_EDC_CNT", REG_MMIO, 0x2444, &mmSPI_EDC_CNT[0], sizeof(mmSPI_EDC_CNT)/sizeof(mmSPI_EDC_CNT[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL_1", REG_MMIO, 0x244f, &mmSPI_CONFIG_CNTL_1[0], sizeof(mmSPI_CONFIG_CNTL_1)/sizeof(mmSPI_CONFIG_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_DEBUG_BUSY", REG_MMIO, 0x2450, &mmSPI_DEBUG_BUSY[0], sizeof(mmSPI_DEBUG_BUSY)/sizeof(mmSPI_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL_2", REG_MMIO, 0x2451, &mmSPI_CONFIG_CNTL_2[0], sizeof(mmSPI_CONFIG_CNTL_2)/sizeof(mmSPI_CONFIG_CNTL_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_CNTL", REG_MMIO, 0x24aa, &mmSPI_WF_LIFETIME_CNTL[0], sizeof(mmSPI_WF_LIFETIME_CNTL)/sizeof(mmSPI_WF_LIFETIME_CNTL[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_0", REG_MMIO, 0x24ab, &mmSPI_WF_LIFETIME_LIMIT_0[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_0)/sizeof(mmSPI_WF_LIFETIME_LIMIT_0[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_1", REG_MMIO, 0x24ac, &mmSPI_WF_LIFETIME_LIMIT_1[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_1)/sizeof(mmSPI_WF_LIFETIME_LIMIT_1[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_2", REG_MMIO, 0x24ad, &mmSPI_WF_LIFETIME_LIMIT_2[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_2)/sizeof(mmSPI_WF_LIFETIME_LIMIT_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_3", REG_MMIO, 0x24ae, &mmSPI_WF_LIFETIME_LIMIT_3[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_3)/sizeof(mmSPI_WF_LIFETIME_LIMIT_3[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_4", REG_MMIO, 0x24af, &mmSPI_WF_LIFETIME_LIMIT_4[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_4)/sizeof(mmSPI_WF_LIFETIME_LIMIT_4[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_5", REG_MMIO, 0x24b0, &mmSPI_WF_LIFETIME_LIMIT_5[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_5)/sizeof(mmSPI_WF_LIFETIME_LIMIT_5[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_6", REG_MMIO, 0x24b1, &mmSPI_WF_LIFETIME_LIMIT_6[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_6)/sizeof(mmSPI_WF_LIFETIME_LIMIT_6[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_7", REG_MMIO, 0x24b2, &mmSPI_WF_LIFETIME_LIMIT_7[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_7)/sizeof(mmSPI_WF_LIFETIME_LIMIT_7[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_8", REG_MMIO, 0x24b3, &mmSPI_WF_LIFETIME_LIMIT_8[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_8)/sizeof(mmSPI_WF_LIFETIME_LIMIT_8[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_9", REG_MMIO, 0x24b4, &mmSPI_WF_LIFETIME_LIMIT_9[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_9)/sizeof(mmSPI_WF_LIFETIME_LIMIT_9[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_0", REG_MMIO, 0x24b5, &mmSPI_WF_LIFETIME_STATUS_0[0], sizeof(mmSPI_WF_LIFETIME_STATUS_0)/sizeof(mmSPI_WF_LIFETIME_STATUS_0[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_1", REG_MMIO, 0x24b6, &mmSPI_WF_LIFETIME_STATUS_1[0], sizeof(mmSPI_WF_LIFETIME_STATUS_1)/sizeof(mmSPI_WF_LIFETIME_STATUS_1[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_2", REG_MMIO, 0x24b7, &mmSPI_WF_LIFETIME_STATUS_2[0], sizeof(mmSPI_WF_LIFETIME_STATUS_2)/sizeof(mmSPI_WF_LIFETIME_STATUS_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_3", REG_MMIO, 0x24b8, &mmSPI_WF_LIFETIME_STATUS_3[0], sizeof(mmSPI_WF_LIFETIME_STATUS_3)/sizeof(mmSPI_WF_LIFETIME_STATUS_3[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_4", REG_MMIO, 0x24b9, &mmSPI_WF_LIFETIME_STATUS_4[0], sizeof(mmSPI_WF_LIFETIME_STATUS_4)/sizeof(mmSPI_WF_LIFETIME_STATUS_4[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_5", REG_MMIO, 0x24ba, &mmSPI_WF_LIFETIME_STATUS_5[0], sizeof(mmSPI_WF_LIFETIME_STATUS_5)/sizeof(mmSPI_WF_LIFETIME_STATUS_5[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_6", REG_MMIO, 0x24bb, &mmSPI_WF_LIFETIME_STATUS_6[0], sizeof(mmSPI_WF_LIFETIME_STATUS_6)/sizeof(mmSPI_WF_LIFETIME_STATUS_6[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_7", REG_MMIO, 0x24bc, &mmSPI_WF_LIFETIME_STATUS_7[0], sizeof(mmSPI_WF_LIFETIME_STATUS_7)/sizeof(mmSPI_WF_LIFETIME_STATUS_7[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_8", REG_MMIO, 0x24bd, &mmSPI_WF_LIFETIME_STATUS_8[0], sizeof(mmSPI_WF_LIFETIME_STATUS_8)/sizeof(mmSPI_WF_LIFETIME_STATUS_8[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_9", REG_MMIO, 0x24be, &mmSPI_WF_LIFETIME_STATUS_9[0], sizeof(mmSPI_WF_LIFETIME_STATUS_9)/sizeof(mmSPI_WF_LIFETIME_STATUS_9[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_10", REG_MMIO, 0x24bf, &mmSPI_WF_LIFETIME_STATUS_10[0], sizeof(mmSPI_WF_LIFETIME_STATUS_10)/sizeof(mmSPI_WF_LIFETIME_STATUS_10[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_11", REG_MMIO, 0x24c0, &mmSPI_WF_LIFETIME_STATUS_11[0], sizeof(mmSPI_WF_LIFETIME_STATUS_11)/sizeof(mmSPI_WF_LIFETIME_STATUS_11[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_12", REG_MMIO, 0x24c1, &mmSPI_WF_LIFETIME_STATUS_12[0], sizeof(mmSPI_WF_LIFETIME_STATUS_12)/sizeof(mmSPI_WF_LIFETIME_STATUS_12[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_13", REG_MMIO, 0x24c2, &mmSPI_WF_LIFETIME_STATUS_13[0], sizeof(mmSPI_WF_LIFETIME_STATUS_13)/sizeof(mmSPI_WF_LIFETIME_STATUS_13[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_14", REG_MMIO, 0x24c3, &mmSPI_WF_LIFETIME_STATUS_14[0], sizeof(mmSPI_WF_LIFETIME_STATUS_14)/sizeof(mmSPI_WF_LIFETIME_STATUS_14[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_15", REG_MMIO, 0x24c4, &mmSPI_WF_LIFETIME_STATUS_15[0], sizeof(mmSPI_WF_LIFETIME_STATUS_15)/sizeof(mmSPI_WF_LIFETIME_STATUS_15[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_16", REG_MMIO, 0x24c5, &mmSPI_WF_LIFETIME_STATUS_16[0], sizeof(mmSPI_WF_LIFETIME_STATUS_16)/sizeof(mmSPI_WF_LIFETIME_STATUS_16[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_17", REG_MMIO, 0x24c6, &mmSPI_WF_LIFETIME_STATUS_17[0], sizeof(mmSPI_WF_LIFETIME_STATUS_17)/sizeof(mmSPI_WF_LIFETIME_STATUS_17[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_18", REG_MMIO, 0x24c7, &mmSPI_WF_LIFETIME_STATUS_18[0], sizeof(mmSPI_WF_LIFETIME_STATUS_18)/sizeof(mmSPI_WF_LIFETIME_STATUS_18[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_19", REG_MMIO, 0x24c8, &mmSPI_WF_LIFETIME_STATUS_19[0], sizeof(mmSPI_WF_LIFETIME_STATUS_19)/sizeof(mmSPI_WF_LIFETIME_STATUS_19[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_20", REG_MMIO, 0x24c9, &mmSPI_WF_LIFETIME_STATUS_20[0], sizeof(mmSPI_WF_LIFETIME_STATUS_20)/sizeof(mmSPI_WF_LIFETIME_STATUS_20[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_DEBUG", REG_MMIO, 0x24ca, &mmSPI_WF_LIFETIME_DEBUG[0], sizeof(mmSPI_WF_LIFETIME_DEBUG)/sizeof(mmSPI_WF_LIFETIME_DEBUG[0]), 0, 0 },
+	{ "mmSPI_SLAVE_DEBUG_BUSY", REG_MMIO, 0x24d3, &mmSPI_SLAVE_DEBUG_BUSY[0], sizeof(mmSPI_SLAVE_DEBUG_BUSY)/sizeof(mmSPI_SLAVE_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_LB_CTR_CTRL", REG_MMIO, 0x24d4, &mmSPI_LB_CTR_CTRL[0], sizeof(mmSPI_LB_CTR_CTRL)/sizeof(mmSPI_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSPI_LB_CU_MASK", REG_MMIO, 0x24d5, &mmSPI_LB_CU_MASK[0], sizeof(mmSPI_LB_CU_MASK)/sizeof(mmSPI_LB_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_LB_DATA_REG", REG_MMIO, 0x24d6, &mmSPI_LB_DATA_REG[0], sizeof(mmSPI_LB_DATA_REG)/sizeof(mmSPI_LB_DATA_REG[0]), 0, 0 },
+	{ "mmSPI_PG_ENABLE_STATIC_CU_MASK", REG_MMIO, 0x24d7, &mmSPI_PG_ENABLE_STATIC_CU_MASK[0], sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK)/sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_GDS_CREDITS", REG_MMIO, 0x24d8, &mmSPI_GDS_CREDITS[0], sizeof(mmSPI_GDS_CREDITS)/sizeof(mmSPI_GDS_CREDITS[0]), 0, 0 },
+	{ "mmSPI_SX_EXPORT_BUFFER_SIZES", REG_MMIO, 0x24d9, &mmSPI_SX_EXPORT_BUFFER_SIZES[0], sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES)/sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_SX_SCOREBOARD_BUFFER_SIZES", REG_MMIO, 0x24da, &mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0], sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES)/sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_STATUS", REG_MMIO, 0x24db, &mmSPI_CSQ_WF_ACTIVE_STATUS[0], sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS)/sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_0", REG_MMIO, 0x24dc, &mmSPI_CSQ_WF_ACTIVE_COUNT_0[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_1", REG_MMIO, 0x24dd, &mmSPI_CSQ_WF_ACTIVE_COUNT_1[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_2", REG_MMIO, 0x24de, &mmSPI_CSQ_WF_ACTIVE_COUNT_2[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_3", REG_MMIO, 0x24df, &mmSPI_CSQ_WF_ACTIVE_COUNT_3[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_4", REG_MMIO, 0x24e0, &mmSPI_CSQ_WF_ACTIVE_COUNT_4[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_5", REG_MMIO, 0x24e1, &mmSPI_CSQ_WF_ACTIVE_COUNT_5[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_6", REG_MMIO, 0x24e2, &mmSPI_CSQ_WF_ACTIVE_COUNT_6[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_7", REG_MMIO, 0x24e3, &mmSPI_CSQ_WF_ACTIVE_COUNT_7[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7[0]), 0, 0 },
+	{ "mmBCI_DEBUG_READ", REG_MMIO, 0x24eb, &mmBCI_DEBUG_READ[0], sizeof(mmBCI_DEBUG_READ)/sizeof(mmBCI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24ec, &mmSPI_P0_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24ed, &mmSPI_P0_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24ee, &mmSPI_P0_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24ef, &mmSPI_P0_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f0, &mmSPI_P0_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24f1, &mmSPI_P1_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24f2, &mmSPI_P1_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24f3, &mmSPI_P1_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24f4, &mmSPI_P1_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f5, &mmSPI_P1_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
+	{ "mmTD_CNTL", REG_MMIO, 0x2525, &mmTD_CNTL[0], sizeof(mmTD_CNTL)/sizeof(mmTD_CNTL[0]), 0, 0 },
+	{ "mmTD_STATUS", REG_MMIO, 0x2526, &mmTD_STATUS[0], sizeof(mmTD_STATUS)/sizeof(mmTD_STATUS[0]), 0, 0 },
+	{ "mmTD_DEBUG_INDEX", REG_MMIO, 0x2528, &mmTD_DEBUG_INDEX[0], sizeof(mmTD_DEBUG_INDEX)/sizeof(mmTD_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTD_DEBUG_DATA", REG_MMIO, 0x2529, &mmTD_DEBUG_DATA[0], sizeof(mmTD_DEBUG_DATA)/sizeof(mmTD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTD_EDC_CNT", REG_MMIO, 0x252e, NULL, 0, 0, 0 },
+	{ "mmTD_DSM_CNTL", REG_MMIO, 0x252f, &mmTD_DSM_CNTL[0], sizeof(mmTD_DSM_CNTL)/sizeof(mmTD_DSM_CNTL[0]), 0, 0 },
+	{ "mmTD_SCRATCH", REG_MMIO, 0x2533, &mmTD_SCRATCH[0], sizeof(mmTD_SCRATCH)/sizeof(mmTD_SCRATCH[0]), 0, 0 },
+	{ "mmTA_CNTL", REG_MMIO, 0x2541, &mmTA_CNTL[0], sizeof(mmTA_CNTL)/sizeof(mmTA_CNTL[0]), 0, 0 },
+	{ "mmTA_CNTL_AUX", REG_MMIO, 0x2542, &mmTA_CNTL_AUX[0], sizeof(mmTA_CNTL_AUX)/sizeof(mmTA_CNTL_AUX[0]), 0, 0 },
+	{ "mmTA_RESERVED_010C", REG_MMIO, 0x2543, &mmTA_RESERVED_010C[0], sizeof(mmTA_RESERVED_010C)/sizeof(mmTA_RESERVED_010C[0]), 0, 0 },
+	{ "mmTA_STATUS", REG_MMIO, 0x2548, &mmTA_STATUS[0], sizeof(mmTA_STATUS)/sizeof(mmTA_STATUS[0]), 0, 0 },
+	{ "mmTA_DEBUG_INDEX", REG_MMIO, 0x254c, &mmTA_DEBUG_INDEX[0], sizeof(mmTA_DEBUG_INDEX)/sizeof(mmTA_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTA_DEBUG_DATA", REG_MMIO, 0x254d, &mmTA_DEBUG_DATA[0], sizeof(mmTA_DEBUG_DATA)/sizeof(mmTA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTA_SCRATCH", REG_MMIO, 0x2564, &mmTA_SCRATCH[0], sizeof(mmTA_SCRATCH)/sizeof(mmTA_SCRATCH[0]), 0, 0 },
+	{ "mmSH_HIDDEN_PRIVATE_BASE_VMID", REG_MMIO, 0x2580, &mmSH_HIDDEN_PRIVATE_BASE_VMID[0], sizeof(mmSH_HIDDEN_PRIVATE_BASE_VMID)/sizeof(mmSH_HIDDEN_PRIVATE_BASE_VMID[0]), 0, 0 },
+	{ "mmSH_STATIC_MEM_CONFIG", REG_MMIO, 0x2581, &mmSH_STATIC_MEM_CONFIG[0], sizeof(mmSH_STATIC_MEM_CONFIG)/sizeof(mmSH_STATIC_MEM_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CONFIG", REG_MMIO, 0x25c0, &mmGDS_CONFIG[0], sizeof(mmGDS_CONFIG)/sizeof(mmGDS_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CNTL_STATUS", REG_MMIO, 0x25c1, &mmGDS_CNTL_STATUS[0], sizeof(mmGDS_CNTL_STATUS)/sizeof(mmGDS_CNTL_STATUS[0]), 0, 0 },
+	{ "mmGDS_ENHANCE2", REG_MMIO, 0x25c2, &mmGDS_ENHANCE2[0], sizeof(mmGDS_ENHANCE2)/sizeof(mmGDS_ENHANCE2[0]), 0, 0 },
+	{ "mmGDS_PROTECTION_FAULT", REG_MMIO, 0x25c3, &mmGDS_PROTECTION_FAULT[0], sizeof(mmGDS_PROTECTION_FAULT)/sizeof(mmGDS_PROTECTION_FAULT[0]), 0, 0 },
+	{ "mmGDS_VM_PROTECTION_FAULT", REG_MMIO, 0x25c4, &mmGDS_VM_PROTECTION_FAULT[0], sizeof(mmGDS_VM_PROTECTION_FAULT)/sizeof(mmGDS_VM_PROTECTION_FAULT[0]), 0, 0 },
+	{ "mmGDS_EDC_CNT", REG_MMIO, 0x25c5, &mmGDS_EDC_CNT[0], sizeof(mmGDS_EDC_CNT)/sizeof(mmGDS_EDC_CNT[0]), 0, 0 },
+	{ "mmGDS_EDC_GRBM_CNT", REG_MMIO, 0x25c6, &mmGDS_EDC_GRBM_CNT[0], sizeof(mmGDS_EDC_GRBM_CNT)/sizeof(mmGDS_EDC_GRBM_CNT[0]), 0, 0 },
+	{ "mmGDS_EDC_OA_DED", REG_MMIO, 0x25c7, &mmGDS_EDC_OA_DED[0], sizeof(mmGDS_EDC_OA_DED)/sizeof(mmGDS_EDC_OA_DED[0]), 0, 0 },
+	{ "mmGDS_DEBUG_CNTL", REG_MMIO, 0x25c8, &mmGDS_DEBUG_CNTL[0], sizeof(mmGDS_DEBUG_CNTL)/sizeof(mmGDS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGDS_DEBUG_DATA", REG_MMIO, 0x25c9, &mmGDS_DEBUG_DATA[0], sizeof(mmGDS_DEBUG_DATA)/sizeof(mmGDS_DEBUG_DATA[0]), 0, 0 },
+	{ "mmGDS_DSM_CNTL", REG_MMIO, 0x25ca, &mmGDS_DSM_CNTL[0], sizeof(mmGDS_DSM_CNTL)/sizeof(mmGDS_DSM_CNTL[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG31", REG_SMC, 0x26, &ixVGT_DEBUG_REG31[0], sizeof(ixVGT_DEBUG_REG31)/sizeof(ixVGT_DEBUG_REG31[0]), 0, 0 },
+	{ "mmDB_DEBUG", REG_MMIO, 0x260c, &mmDB_DEBUG[0], sizeof(mmDB_DEBUG)/sizeof(mmDB_DEBUG[0]), 0, 0 },
+	{ "mmDB_DEBUG2", REG_MMIO, 0x260d, &mmDB_DEBUG2[0], sizeof(mmDB_DEBUG2)/sizeof(mmDB_DEBUG2[0]), 0, 0 },
+	{ "mmDB_DEBUG3", REG_MMIO, 0x260e, &mmDB_DEBUG3[0], sizeof(mmDB_DEBUG3)/sizeof(mmDB_DEBUG3[0]), 0, 0 },
+	{ "mmDB_DEBUG4", REG_MMIO, 0x260f, &mmDB_DEBUG4[0], sizeof(mmDB_DEBUG4)/sizeof(mmDB_DEBUG4[0]), 0, 0 },
+	{ "mmDB_CREDIT_LIMIT", REG_MMIO, 0x2614, &mmDB_CREDIT_LIMIT[0], sizeof(mmDB_CREDIT_LIMIT)/sizeof(mmDB_CREDIT_LIMIT[0]), 0, 0 },
+	{ "mmDB_WATERMARKS", REG_MMIO, 0x2615, &mmDB_WATERMARKS[0], sizeof(mmDB_WATERMARKS)/sizeof(mmDB_WATERMARKS[0]), 0, 0 },
+	{ "mmDB_SUBTILE_CONTROL", REG_MMIO, 0x2616, &mmDB_SUBTILE_CONTROL[0], sizeof(mmDB_SUBTILE_CONTROL)/sizeof(mmDB_SUBTILE_CONTROL[0]), 0, 0 },
+	{ "mmDB_FREE_CACHELINES", REG_MMIO, 0x2617, &mmDB_FREE_CACHELINES[0], sizeof(mmDB_FREE_CACHELINES)/sizeof(mmDB_FREE_CACHELINES[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH1", REG_MMIO, 0x2618, &mmDB_FIFO_DEPTH1[0], sizeof(mmDB_FIFO_DEPTH1)/sizeof(mmDB_FIFO_DEPTH1[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH2", REG_MMIO, 0x2619, &mmDB_FIFO_DEPTH2[0], sizeof(mmDB_FIFO_DEPTH2)/sizeof(mmDB_FIFO_DEPTH2[0]), 0, 0 },
+	{ "mmDB_RING_CONTROL", REG_MMIO, 0x261b, &mmDB_RING_CONTROL[0], sizeof(mmDB_RING_CONTROL)/sizeof(mmDB_RING_CONTROL[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_0", REG_MMIO, 0x2620, &mmDB_READ_DEBUG_0[0], sizeof(mmDB_READ_DEBUG_0)/sizeof(mmDB_READ_DEBUG_0[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_1", REG_MMIO, 0x2621, &mmDB_READ_DEBUG_1[0], sizeof(mmDB_READ_DEBUG_1)/sizeof(mmDB_READ_DEBUG_1[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_2", REG_MMIO, 0x2622, &mmDB_READ_DEBUG_2[0], sizeof(mmDB_READ_DEBUG_2)/sizeof(mmDB_READ_DEBUG_2[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_3", REG_MMIO, 0x2623, &mmDB_READ_DEBUG_3[0], sizeof(mmDB_READ_DEBUG_3)/sizeof(mmDB_READ_DEBUG_3[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_4", REG_MMIO, 0x2624, &mmDB_READ_DEBUG_4[0], sizeof(mmDB_READ_DEBUG_4)/sizeof(mmDB_READ_DEBUG_4[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_5", REG_MMIO, 0x2625, &mmDB_READ_DEBUG_5[0], sizeof(mmDB_READ_DEBUG_5)/sizeof(mmDB_READ_DEBUG_5[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_6", REG_MMIO, 0x2626, &mmDB_READ_DEBUG_6[0], sizeof(mmDB_READ_DEBUG_6)/sizeof(mmDB_READ_DEBUG_6[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_7", REG_MMIO, 0x2627, &mmDB_READ_DEBUG_7[0], sizeof(mmDB_READ_DEBUG_7)/sizeof(mmDB_READ_DEBUG_7[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_8", REG_MMIO, 0x2628, &mmDB_READ_DEBUG_8[0], sizeof(mmDB_READ_DEBUG_8)/sizeof(mmDB_READ_DEBUG_8[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_9", REG_MMIO, 0x2629, &mmDB_READ_DEBUG_9[0], sizeof(mmDB_READ_DEBUG_9)/sizeof(mmDB_READ_DEBUG_9[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_A", REG_MMIO, 0x262a, &mmDB_READ_DEBUG_A[0], sizeof(mmDB_READ_DEBUG_A)/sizeof(mmDB_READ_DEBUG_A[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_B", REG_MMIO, 0x262b, &mmDB_READ_DEBUG_B[0], sizeof(mmDB_READ_DEBUG_B)/sizeof(mmDB_READ_DEBUG_B[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_C", REG_MMIO, 0x262c, &mmDB_READ_DEBUG_C[0], sizeof(mmDB_READ_DEBUG_C)/sizeof(mmDB_READ_DEBUG_C[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_D", REG_MMIO, 0x262d, &mmDB_READ_DEBUG_D[0], sizeof(mmDB_READ_DEBUG_D)/sizeof(mmDB_READ_DEBUG_D[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_E", REG_MMIO, 0x262e, &mmDB_READ_DEBUG_E[0], sizeof(mmDB_READ_DEBUG_E)/sizeof(mmDB_READ_DEBUG_E[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_F", REG_MMIO, 0x262f, &mmDB_READ_DEBUG_F[0], sizeof(mmDB_READ_DEBUG_F)/sizeof(mmDB_READ_DEBUG_F[0]), 0, 0 },
+	{ "mmCC_RB_REDUNDANCY", REG_MMIO, 0x263c, &mmCC_RB_REDUNDANCY[0], sizeof(mmCC_RB_REDUNDANCY)/sizeof(mmCC_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmCC_RB_BACKEND_DISABLE", REG_MMIO, 0x263d, &mmCC_RB_BACKEND_DISABLE[0], sizeof(mmCC_RB_BACKEND_DISABLE)/sizeof(mmCC_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmGB_ADDR_CONFIG", REG_MMIO, 0x263e, &mmGB_ADDR_CONFIG[0], sizeof(mmGB_ADDR_CONFIG)/sizeof(mmGB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmGB_BACKEND_MAP", REG_MMIO, 0x263f, &mmGB_BACKEND_MAP[0], sizeof(mmGB_BACKEND_MAP)/sizeof(mmGB_BACKEND_MAP[0]), 0, 0 },
+	{ "mmGB_GPU_ID", REG_MMIO, 0x2640, &mmGB_GPU_ID[0], sizeof(mmGB_GPU_ID)/sizeof(mmGB_GPU_ID[0]), 0, 0 },
+	{ "mmCC_RB_DAISY_CHAIN", REG_MMIO, 0x2641, &mmCC_RB_DAISY_CHAIN[0], sizeof(mmCC_RB_DAISY_CHAIN)/sizeof(mmCC_RB_DAISY_CHAIN[0]), 0, 0 },
+	{ "mmGB_TILE_MODE0", REG_MMIO, 0x2644, &mmGB_TILE_MODE0[0], sizeof(mmGB_TILE_MODE0)/sizeof(mmGB_TILE_MODE0[0]), 0, 0 },
+	{ "mmGB_TILE_MODE1", REG_MMIO, 0x2645, &mmGB_TILE_MODE1[0], sizeof(mmGB_TILE_MODE1)/sizeof(mmGB_TILE_MODE1[0]), 0, 0 },
+	{ "mmGB_TILE_MODE2", REG_MMIO, 0x2646, &mmGB_TILE_MODE2[0], sizeof(mmGB_TILE_MODE2)/sizeof(mmGB_TILE_MODE2[0]), 0, 0 },
+	{ "mmGB_TILE_MODE3", REG_MMIO, 0x2647, &mmGB_TILE_MODE3[0], sizeof(mmGB_TILE_MODE3)/sizeof(mmGB_TILE_MODE3[0]), 0, 0 },
+	{ "mmGB_TILE_MODE4", REG_MMIO, 0x2648, &mmGB_TILE_MODE4[0], sizeof(mmGB_TILE_MODE4)/sizeof(mmGB_TILE_MODE4[0]), 0, 0 },
+	{ "mmGB_TILE_MODE5", REG_MMIO, 0x2649, &mmGB_TILE_MODE5[0], sizeof(mmGB_TILE_MODE5)/sizeof(mmGB_TILE_MODE5[0]), 0, 0 },
+	{ "mmGB_TILE_MODE6", REG_MMIO, 0x264a, &mmGB_TILE_MODE6[0], sizeof(mmGB_TILE_MODE6)/sizeof(mmGB_TILE_MODE6[0]), 0, 0 },
+	{ "mmGB_TILE_MODE7", REG_MMIO, 0x264b, &mmGB_TILE_MODE7[0], sizeof(mmGB_TILE_MODE7)/sizeof(mmGB_TILE_MODE7[0]), 0, 0 },
+	{ "mmGB_TILE_MODE8", REG_MMIO, 0x264c, &mmGB_TILE_MODE8[0], sizeof(mmGB_TILE_MODE8)/sizeof(mmGB_TILE_MODE8[0]), 0, 0 },
+	{ "mmGB_TILE_MODE9", REG_MMIO, 0x264d, &mmGB_TILE_MODE9[0], sizeof(mmGB_TILE_MODE9)/sizeof(mmGB_TILE_MODE9[0]), 0, 0 },
+	{ "mmGB_TILE_MODE10", REG_MMIO, 0x264e, &mmGB_TILE_MODE10[0], sizeof(mmGB_TILE_MODE10)/sizeof(mmGB_TILE_MODE10[0]), 0, 0 },
+	{ "mmGB_TILE_MODE11", REG_MMIO, 0x264f, &mmGB_TILE_MODE11[0], sizeof(mmGB_TILE_MODE11)/sizeof(mmGB_TILE_MODE11[0]), 0, 0 },
+	{ "mmGB_TILE_MODE12", REG_MMIO, 0x2650, &mmGB_TILE_MODE12[0], sizeof(mmGB_TILE_MODE12)/sizeof(mmGB_TILE_MODE12[0]), 0, 0 },
+	{ "mmGB_TILE_MODE13", REG_MMIO, 0x2651, &mmGB_TILE_MODE13[0], sizeof(mmGB_TILE_MODE13)/sizeof(mmGB_TILE_MODE13[0]), 0, 0 },
+	{ "mmGB_TILE_MODE14", REG_MMIO, 0x2652, &mmGB_TILE_MODE14[0], sizeof(mmGB_TILE_MODE14)/sizeof(mmGB_TILE_MODE14[0]), 0, 0 },
+	{ "mmGB_TILE_MODE15", REG_MMIO, 0x2653, &mmGB_TILE_MODE15[0], sizeof(mmGB_TILE_MODE15)/sizeof(mmGB_TILE_MODE15[0]), 0, 0 },
+	{ "mmGB_TILE_MODE16", REG_MMIO, 0x2654, &mmGB_TILE_MODE16[0], sizeof(mmGB_TILE_MODE16)/sizeof(mmGB_TILE_MODE16[0]), 0, 0 },
+	{ "mmGB_TILE_MODE17", REG_MMIO, 0x2655, &mmGB_TILE_MODE17[0], sizeof(mmGB_TILE_MODE17)/sizeof(mmGB_TILE_MODE17[0]), 0, 0 },
+	{ "mmGB_TILE_MODE18", REG_MMIO, 0x2656, &mmGB_TILE_MODE18[0], sizeof(mmGB_TILE_MODE18)/sizeof(mmGB_TILE_MODE18[0]), 0, 0 },
+	{ "mmGB_TILE_MODE19", REG_MMIO, 0x2657, &mmGB_TILE_MODE19[0], sizeof(mmGB_TILE_MODE19)/sizeof(mmGB_TILE_MODE19[0]), 0, 0 },
+	{ "mmGB_TILE_MODE20", REG_MMIO, 0x2658, &mmGB_TILE_MODE20[0], sizeof(mmGB_TILE_MODE20)/sizeof(mmGB_TILE_MODE20[0]), 0, 0 },
+	{ "mmGB_TILE_MODE21", REG_MMIO, 0x2659, &mmGB_TILE_MODE21[0], sizeof(mmGB_TILE_MODE21)/sizeof(mmGB_TILE_MODE21[0]), 0, 0 },
+	{ "mmGB_TILE_MODE22", REG_MMIO, 0x265a, &mmGB_TILE_MODE22[0], sizeof(mmGB_TILE_MODE22)/sizeof(mmGB_TILE_MODE22[0]), 0, 0 },
+	{ "mmGB_TILE_MODE23", REG_MMIO, 0x265b, &mmGB_TILE_MODE23[0], sizeof(mmGB_TILE_MODE23)/sizeof(mmGB_TILE_MODE23[0]), 0, 0 },
+	{ "mmGB_TILE_MODE24", REG_MMIO, 0x265c, &mmGB_TILE_MODE24[0], sizeof(mmGB_TILE_MODE24)/sizeof(mmGB_TILE_MODE24[0]), 0, 0 },
+	{ "mmGB_TILE_MODE25", REG_MMIO, 0x265d, &mmGB_TILE_MODE25[0], sizeof(mmGB_TILE_MODE25)/sizeof(mmGB_TILE_MODE25[0]), 0, 0 },
+	{ "mmGB_TILE_MODE26", REG_MMIO, 0x265e, &mmGB_TILE_MODE26[0], sizeof(mmGB_TILE_MODE26)/sizeof(mmGB_TILE_MODE26[0]), 0, 0 },
+	{ "mmGB_TILE_MODE27", REG_MMIO, 0x265f, &mmGB_TILE_MODE27[0], sizeof(mmGB_TILE_MODE27)/sizeof(mmGB_TILE_MODE27[0]), 0, 0 },
+	{ "mmGB_TILE_MODE28", REG_MMIO, 0x2660, &mmGB_TILE_MODE28[0], sizeof(mmGB_TILE_MODE28)/sizeof(mmGB_TILE_MODE28[0]), 0, 0 },
+	{ "mmGB_TILE_MODE29", REG_MMIO, 0x2661, &mmGB_TILE_MODE29[0], sizeof(mmGB_TILE_MODE29)/sizeof(mmGB_TILE_MODE29[0]), 0, 0 },
+	{ "mmGB_TILE_MODE30", REG_MMIO, 0x2662, &mmGB_TILE_MODE30[0], sizeof(mmGB_TILE_MODE30)/sizeof(mmGB_TILE_MODE30[0]), 0, 0 },
+	{ "mmGB_TILE_MODE31", REG_MMIO, 0x2663, &mmGB_TILE_MODE31[0], sizeof(mmGB_TILE_MODE31)/sizeof(mmGB_TILE_MODE31[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE0", REG_MMIO, 0x2664, &mmGB_MACROTILE_MODE0[0], sizeof(mmGB_MACROTILE_MODE0)/sizeof(mmGB_MACROTILE_MODE0[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE1", REG_MMIO, 0x2665, &mmGB_MACROTILE_MODE1[0], sizeof(mmGB_MACROTILE_MODE1)/sizeof(mmGB_MACROTILE_MODE1[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE2", REG_MMIO, 0x2666, &mmGB_MACROTILE_MODE2[0], sizeof(mmGB_MACROTILE_MODE2)/sizeof(mmGB_MACROTILE_MODE2[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE3", REG_MMIO, 0x2667, &mmGB_MACROTILE_MODE3[0], sizeof(mmGB_MACROTILE_MODE3)/sizeof(mmGB_MACROTILE_MODE3[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE4", REG_MMIO, 0x2668, &mmGB_MACROTILE_MODE4[0], sizeof(mmGB_MACROTILE_MODE4)/sizeof(mmGB_MACROTILE_MODE4[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE5", REG_MMIO, 0x2669, &mmGB_MACROTILE_MODE5[0], sizeof(mmGB_MACROTILE_MODE5)/sizeof(mmGB_MACROTILE_MODE5[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE6", REG_MMIO, 0x266a, &mmGB_MACROTILE_MODE6[0], sizeof(mmGB_MACROTILE_MODE6)/sizeof(mmGB_MACROTILE_MODE6[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE7", REG_MMIO, 0x266b, &mmGB_MACROTILE_MODE7[0], sizeof(mmGB_MACROTILE_MODE7)/sizeof(mmGB_MACROTILE_MODE7[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE8", REG_MMIO, 0x266c, &mmGB_MACROTILE_MODE8[0], sizeof(mmGB_MACROTILE_MODE8)/sizeof(mmGB_MACROTILE_MODE8[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE9", REG_MMIO, 0x266d, &mmGB_MACROTILE_MODE9[0], sizeof(mmGB_MACROTILE_MODE9)/sizeof(mmGB_MACROTILE_MODE9[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE10", REG_MMIO, 0x266e, &mmGB_MACROTILE_MODE10[0], sizeof(mmGB_MACROTILE_MODE10)/sizeof(mmGB_MACROTILE_MODE10[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE11", REG_MMIO, 0x266f, &mmGB_MACROTILE_MODE11[0], sizeof(mmGB_MACROTILE_MODE11)/sizeof(mmGB_MACROTILE_MODE11[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE12", REG_MMIO, 0x2670, &mmGB_MACROTILE_MODE12[0], sizeof(mmGB_MACROTILE_MODE12)/sizeof(mmGB_MACROTILE_MODE12[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE13", REG_MMIO, 0x2671, &mmGB_MACROTILE_MODE13[0], sizeof(mmGB_MACROTILE_MODE13)/sizeof(mmGB_MACROTILE_MODE13[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE14", REG_MMIO, 0x2672, &mmGB_MACROTILE_MODE14[0], sizeof(mmGB_MACROTILE_MODE14)/sizeof(mmGB_MACROTILE_MODE14[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE15", REG_MMIO, 0x2673, &mmGB_MACROTILE_MODE15[0], sizeof(mmGB_MACROTILE_MODE15)/sizeof(mmGB_MACROTILE_MODE15[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_3", REG_MMIO, 0x2683, &mmCB_HW_CONTROL_3[0], sizeof(mmCB_HW_CONTROL_3)/sizeof(mmCB_HW_CONTROL_3[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL", REG_MMIO, 0x2684, &mmCB_HW_CONTROL[0], sizeof(mmCB_HW_CONTROL)/sizeof(mmCB_HW_CONTROL[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_1", REG_MMIO, 0x2685, &mmCB_HW_CONTROL_1[0], sizeof(mmCB_HW_CONTROL_1)/sizeof(mmCB_HW_CONTROL_1[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_2", REG_MMIO, 0x2686, &mmCB_HW_CONTROL_2[0], sizeof(mmCB_HW_CONTROL_2)/sizeof(mmCB_HW_CONTROL_2[0]), 0, 0 },
+	{ "mmCB_DCC_CONFIG", REG_MMIO, 0x2687, &mmCB_DCC_CONFIG[0], sizeof(mmCB_DCC_CONFIG)/sizeof(mmCB_DCC_CONFIG[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_1", REG_MMIO, 0x2699, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_2", REG_MMIO, 0x269a, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_3", REG_MMIO, 0x269b, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_4", REG_MMIO, 0x269c, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_5", REG_MMIO, 0x269d, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_6", REG_MMIO, 0x269e, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_7", REG_MMIO, 0x269f, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_8", REG_MMIO, 0x26a0, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_9", REG_MMIO, 0x26a1, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_10", REG_MMIO, 0x26a2, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_11", REG_MMIO, 0x26a3, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_12", REG_MMIO, 0x26a4, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_13", REG_MMIO, 0x26a5, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_14", REG_MMIO, 0x26a6, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_15", REG_MMIO, 0x26a7, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_16", REG_MMIO, 0x26a8, NULL, 0, 0, 0 },
+	{ "mmCB_DEBUG_BUS_17", REG_MMIO, 0x26a9, &mmCB_DEBUG_BUS_17[0], sizeof(mmCB_DEBUG_BUS_17)/sizeof(mmCB_DEBUG_BUS_17[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_18", REG_MMIO, 0x26aa, &mmCB_DEBUG_BUS_18[0], sizeof(mmCB_DEBUG_BUS_18)/sizeof(mmCB_DEBUG_BUS_18[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_19", REG_MMIO, 0x26ab, &mmCB_DEBUG_BUS_19[0], sizeof(mmCB_DEBUG_BUS_19)/sizeof(mmCB_DEBUG_BUS_19[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_20", REG_MMIO, 0x26ac, &mmCB_DEBUG_BUS_20[0], sizeof(mmCB_DEBUG_BUS_20)/sizeof(mmCB_DEBUG_BUS_20[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_21", REG_MMIO, 0x26ad, &mmCB_DEBUG_BUS_21[0], sizeof(mmCB_DEBUG_BUS_21)/sizeof(mmCB_DEBUG_BUS_21[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_22", REG_MMIO, 0x26ae, &mmCB_DEBUG_BUS_22[0], sizeof(mmCB_DEBUG_BUS_22)/sizeof(mmCB_DEBUG_BUS_22[0]), 0, 0 },
+	{ "ixSQ_WAVE_TBA_LO", REG_SMC, 0x26c, &ixSQ_WAVE_TBA_LO[0], sizeof(ixSQ_WAVE_TBA_LO)/sizeof(ixSQ_WAVE_TBA_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_TBA_HI", REG_SMC, 0x26d, &ixSQ_WAVE_TBA_HI[0], sizeof(ixSQ_WAVE_TBA_HI)/sizeof(ixSQ_WAVE_TBA_HI[0]), 0, 0 },
+	{ "mmGC_USER_RB_REDUNDANCY", REG_MMIO, 0x26de, &mmGC_USER_RB_REDUNDANCY[0], sizeof(mmGC_USER_RB_REDUNDANCY)/sizeof(mmGC_USER_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmGC_USER_RB_BACKEND_DISABLE", REG_MMIO, 0x26df, &mmGC_USER_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "ixSQ_WAVE_TMA_LO", REG_SMC, 0x26e, &ixSQ_WAVE_TMA_LO[0], sizeof(ixSQ_WAVE_TMA_LO)/sizeof(ixSQ_WAVE_TMA_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_TMA_HI", REG_SMC, 0x26f, &ixSQ_WAVE_TMA_HI[0], sizeof(ixSQ_WAVE_TMA_HI)/sizeof(ixSQ_WAVE_TMA_HI[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG32", REG_SMC, 0x27, &ixVGT_DEBUG_REG32[0], sizeof(ixVGT_DEBUG_REG32)/sizeof(ixVGT_DEBUG_REG32[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP0", REG_SMC, 0x270, &ixSQ_WAVE_TTMP0[0], sizeof(ixSQ_WAVE_TTMP0)/sizeof(ixSQ_WAVE_TTMP0[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP1", REG_SMC, 0x271, &ixSQ_WAVE_TTMP1[0], sizeof(ixSQ_WAVE_TTMP1)/sizeof(ixSQ_WAVE_TTMP1[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP2", REG_SMC, 0x272, &ixSQ_WAVE_TTMP2[0], sizeof(ixSQ_WAVE_TTMP2)/sizeof(ixSQ_WAVE_TTMP2[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP3", REG_SMC, 0x273, &ixSQ_WAVE_TTMP3[0], sizeof(ixSQ_WAVE_TTMP3)/sizeof(ixSQ_WAVE_TTMP3[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP4", REG_SMC, 0x274, &ixSQ_WAVE_TTMP4[0], sizeof(ixSQ_WAVE_TTMP4)/sizeof(ixSQ_WAVE_TTMP4[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP5", REG_SMC, 0x275, &ixSQ_WAVE_TTMP5[0], sizeof(ixSQ_WAVE_TTMP5)/sizeof(ixSQ_WAVE_TTMP5[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP6", REG_SMC, 0x276, &ixSQ_WAVE_TTMP6[0], sizeof(ixSQ_WAVE_TTMP6)/sizeof(ixSQ_WAVE_TTMP6[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP7", REG_SMC, 0x277, &ixSQ_WAVE_TTMP7[0], sizeof(ixSQ_WAVE_TTMP7)/sizeof(ixSQ_WAVE_TTMP7[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP8", REG_SMC, 0x278, &ixSQ_WAVE_TTMP8[0], sizeof(ixSQ_WAVE_TTMP8)/sizeof(ixSQ_WAVE_TTMP8[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP9", REG_SMC, 0x279, &ixSQ_WAVE_TTMP9[0], sizeof(ixSQ_WAVE_TTMP9)/sizeof(ixSQ_WAVE_TTMP9[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP10", REG_SMC, 0x27a, &ixSQ_WAVE_TTMP10[0], sizeof(ixSQ_WAVE_TTMP10)/sizeof(ixSQ_WAVE_TTMP10[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP11", REG_SMC, 0x27b, &ixSQ_WAVE_TTMP11[0], sizeof(ixSQ_WAVE_TTMP11)/sizeof(ixSQ_WAVE_TTMP11[0]), 0, 0 },
+	{ "ixSQ_WAVE_M0", REG_SMC, 0x27c, &ixSQ_WAVE_M0[0], sizeof(ixSQ_WAVE_M0)/sizeof(ixSQ_WAVE_M0[0]), 0, 0 },
+	{ "ixSQ_WAVE_EXEC_LO", REG_SMC, 0x27e, &ixSQ_WAVE_EXEC_LO[0], sizeof(ixSQ_WAVE_EXEC_LO)/sizeof(ixSQ_WAVE_EXEC_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_EXEC_HI", REG_SMC, 0x27f, &ixSQ_WAVE_EXEC_HI[0], sizeof(ixSQ_WAVE_EXEC_HI)/sizeof(ixSQ_WAVE_EXEC_HI[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG33", REG_SMC, 0x28, &ixVGT_DEBUG_REG33[0], sizeof(ixVGT_DEBUG_REG33)/sizeof(ixVGT_DEBUG_REG33[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG34", REG_SMC, 0x29, &ixVGT_DEBUG_REG34[0], sizeof(ixVGT_DEBUG_REG34)/sizeof(ixVGT_DEBUG_REG34[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG36", REG_SMC, 0x2b, &ixVGT_DEBUG_REG36[0], sizeof(ixVGT_DEBUG_REG36)/sizeof(ixVGT_DEBUG_REG36[0]), 0, 0 },
+	{ "mmTCP_INVALIDATE", REG_MMIO, 0x2b00, &mmTCP_INVALIDATE[0], sizeof(mmTCP_INVALIDATE)/sizeof(mmTCP_INVALIDATE[0]), 0, 0 },
+	{ "mmTCP_STATUS", REG_MMIO, 0x2b01, &mmTCP_STATUS[0], sizeof(mmTCP_STATUS)/sizeof(mmTCP_STATUS[0]), 0, 0 },
+	{ "mmTCP_CNTL", REG_MMIO, 0x2b02, &mmTCP_CNTL[0], sizeof(mmTCP_CNTL)/sizeof(mmTCP_CNTL[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_LO", REG_MMIO, 0x2b03, &mmTCP_CHAN_STEER_LO[0], sizeof(mmTCP_CHAN_STEER_LO)/sizeof(mmTCP_CHAN_STEER_LO[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_HI", REG_MMIO, 0x2b04, &mmTCP_CHAN_STEER_HI[0], sizeof(mmTCP_CHAN_STEER_HI)/sizeof(mmTCP_CHAN_STEER_HI[0]), 0, 0 },
+	{ "mmTCP_ADDR_CONFIG", REG_MMIO, 0x2b05, &mmTCP_ADDR_CONFIG[0], sizeof(mmTCP_ADDR_CONFIG)/sizeof(mmTCP_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmTCP_CREDIT", REG_MMIO, 0x2b06, &mmTCP_CREDIT[0], sizeof(mmTCP_CREDIT)/sizeof(mmTCP_CREDIT[0]), 0, 0 },
+	{ "mmTCP_BUFFER_ADDR_HASH_CNTL", REG_MMIO, 0x2b16, &mmTCP_BUFFER_ADDR_HASH_CNTL[0], sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL)/sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL[0]), 0, 0 },
+	{ "mmTCP_EDC_CNT", REG_MMIO, 0x2b17, &mmTCP_EDC_CNT[0], sizeof(mmTCP_EDC_CNT)/sizeof(mmTCP_EDC_CNT[0]), 0, 0 },
+	{ "mmTC_CFG_L1_LOAD_POLICY0", REG_MMIO, 0x2b1a, &mmTC_CFG_L1_LOAD_POLICY0[0], sizeof(mmTC_CFG_L1_LOAD_POLICY0)/sizeof(mmTC_CFG_L1_LOAD_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L1_LOAD_POLICY1", REG_MMIO, 0x2b1b, &mmTC_CFG_L1_LOAD_POLICY1[0], sizeof(mmTC_CFG_L1_LOAD_POLICY1)/sizeof(mmTC_CFG_L1_LOAD_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L1_STORE_POLICY", REG_MMIO, 0x2b1c, &mmTC_CFG_L1_STORE_POLICY[0], sizeof(mmTC_CFG_L1_STORE_POLICY)/sizeof(mmTC_CFG_L1_STORE_POLICY[0]), 0, 0 },
+	{ "mmTC_CFG_L2_LOAD_POLICY0", REG_MMIO, 0x2b1d, &mmTC_CFG_L2_LOAD_POLICY0[0], sizeof(mmTC_CFG_L2_LOAD_POLICY0)/sizeof(mmTC_CFG_L2_LOAD_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L2_LOAD_POLICY1", REG_MMIO, 0x2b1e, &mmTC_CFG_L2_LOAD_POLICY1[0], sizeof(mmTC_CFG_L2_LOAD_POLICY1)/sizeof(mmTC_CFG_L2_LOAD_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L2_STORE_POLICY0", REG_MMIO, 0x2b1f, &mmTC_CFG_L2_STORE_POLICY0[0], sizeof(mmTC_CFG_L2_STORE_POLICY0)/sizeof(mmTC_CFG_L2_STORE_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L2_STORE_POLICY1", REG_MMIO, 0x2b20, &mmTC_CFG_L2_STORE_POLICY1[0], sizeof(mmTC_CFG_L2_STORE_POLICY1)/sizeof(mmTC_CFG_L2_STORE_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L2_ATOMIC_POLICY", REG_MMIO, 0x2b21, &mmTC_CFG_L2_ATOMIC_POLICY[0], sizeof(mmTC_CFG_L2_ATOMIC_POLICY)/sizeof(mmTC_CFG_L2_ATOMIC_POLICY[0]), 0, 0 },
+	{ "mmTC_CFG_L1_VOLATILE", REG_MMIO, 0x2b22, &mmTC_CFG_L1_VOLATILE[0], sizeof(mmTC_CFG_L1_VOLATILE)/sizeof(mmTC_CFG_L1_VOLATILE[0]), 0, 0 },
+	{ "mmTC_CFG_L2_VOLATILE", REG_MMIO, 0x2b23, &mmTC_CFG_L2_VOLATILE[0], sizeof(mmTC_CFG_L2_VOLATILE)/sizeof(mmTC_CFG_L2_VOLATILE[0]), 0, 0 },
+	{ "mmTCI_STATUS", REG_MMIO, 0x2b61, &mmTCI_STATUS[0], sizeof(mmTCI_STATUS)/sizeof(mmTCI_STATUS[0]), 0, 0 },
+	{ "mmTCI_CNTL_1", REG_MMIO, 0x2b62, &mmTCI_CNTL_1[0], sizeof(mmTCI_CNTL_1)/sizeof(mmTCI_CNTL_1[0]), 0, 0 },
+	{ "mmTCI_CNTL_2", REG_MMIO, 0x2b63, &mmTCI_CNTL_2[0], sizeof(mmTCI_CNTL_2)/sizeof(mmTCI_CNTL_2[0]), 0, 0 },
+	{ "mmTCC_CTRL", REG_MMIO, 0x2b80, &mmTCC_CTRL[0], sizeof(mmTCC_CTRL)/sizeof(mmTCC_CTRL[0]), 0, 0 },
+	{ "mmTCC_EDC_CNT", REG_MMIO, 0x2b82, &mmTCC_EDC_CNT[0], sizeof(mmTCC_EDC_CNT)/sizeof(mmTCC_EDC_CNT[0]), 0, 0 },
+	{ "mmTCC_REDUNDANCY", REG_MMIO, 0x2b83, &mmTCC_REDUNDANCY[0], sizeof(mmTCC_REDUNDANCY)/sizeof(mmTCC_REDUNDANCY[0]), 0, 0 },
+	{ "mmTCC_EXE_DISABLE", REG_MMIO, 0x2b84, &mmTCC_EXE_DISABLE[0], sizeof(mmTCC_EXE_DISABLE)/sizeof(mmTCC_EXE_DISABLE[0]), 0, 0 },
+	{ "mmTCC_DSM_CNTL", REG_MMIO, 0x2b85, &mmTCC_DSM_CNTL[0], sizeof(mmTCC_DSM_CNTL)/sizeof(mmTCC_DSM_CNTL[0]), 0, 0 },
+	{ "mmTCA_CTRL", REG_MMIO, 0x2bc0, &mmTCA_CTRL[0], sizeof(mmTCA_CTRL)/sizeof(mmTCA_CTRL[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_PS", REG_MMIO, 0x2c00, &mmSPI_SHADER_TBA_LO_PS[0], sizeof(mmSPI_SHADER_TBA_LO_PS)/sizeof(mmSPI_SHADER_TBA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_PS", REG_MMIO, 0x2c01, &mmSPI_SHADER_TBA_HI_PS[0], sizeof(mmSPI_SHADER_TBA_HI_PS)/sizeof(mmSPI_SHADER_TBA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_PS", REG_MMIO, 0x2c02, &mmSPI_SHADER_TMA_LO_PS[0], sizeof(mmSPI_SHADER_TMA_LO_PS)/sizeof(mmSPI_SHADER_TMA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_PS", REG_MMIO, 0x2c03, &mmSPI_SHADER_TMA_HI_PS[0], sizeof(mmSPI_SHADER_TMA_HI_PS)/sizeof(mmSPI_SHADER_TMA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_PS", REG_MMIO, 0x2c07, &mmSPI_SHADER_PGM_RSRC3_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_PS)/sizeof(mmSPI_SHADER_PGM_RSRC3_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_PS", REG_MMIO, 0x2c08, &mmSPI_SHADER_PGM_LO_PS[0], sizeof(mmSPI_SHADER_PGM_LO_PS)/sizeof(mmSPI_SHADER_PGM_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_PS", REG_MMIO, 0x2c09, &mmSPI_SHADER_PGM_HI_PS[0], sizeof(mmSPI_SHADER_PGM_HI_PS)/sizeof(mmSPI_SHADER_PGM_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_PS", REG_MMIO, 0x2c0a, &mmSPI_SHADER_PGM_RSRC1_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_PS)/sizeof(mmSPI_SHADER_PGM_RSRC1_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_PS", REG_MMIO, 0x2c0b, &mmSPI_SHADER_PGM_RSRC2_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_PS)/sizeof(mmSPI_SHADER_PGM_RSRC2_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_0", REG_MMIO, 0x2c0c, &mmSPI_SHADER_USER_DATA_PS_0[0], sizeof(mmSPI_SHADER_USER_DATA_PS_0)/sizeof(mmSPI_SHADER_USER_DATA_PS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_1", REG_MMIO, 0x2c0d, &mmSPI_SHADER_USER_DATA_PS_1[0], sizeof(mmSPI_SHADER_USER_DATA_PS_1)/sizeof(mmSPI_SHADER_USER_DATA_PS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_2", REG_MMIO, 0x2c0e, &mmSPI_SHADER_USER_DATA_PS_2[0], sizeof(mmSPI_SHADER_USER_DATA_PS_2)/sizeof(mmSPI_SHADER_USER_DATA_PS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_3", REG_MMIO, 0x2c0f, &mmSPI_SHADER_USER_DATA_PS_3[0], sizeof(mmSPI_SHADER_USER_DATA_PS_3)/sizeof(mmSPI_SHADER_USER_DATA_PS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_4", REG_MMIO, 0x2c10, &mmSPI_SHADER_USER_DATA_PS_4[0], sizeof(mmSPI_SHADER_USER_DATA_PS_4)/sizeof(mmSPI_SHADER_USER_DATA_PS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_5", REG_MMIO, 0x2c11, &mmSPI_SHADER_USER_DATA_PS_5[0], sizeof(mmSPI_SHADER_USER_DATA_PS_5)/sizeof(mmSPI_SHADER_USER_DATA_PS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_6", REG_MMIO, 0x2c12, &mmSPI_SHADER_USER_DATA_PS_6[0], sizeof(mmSPI_SHADER_USER_DATA_PS_6)/sizeof(mmSPI_SHADER_USER_DATA_PS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_7", REG_MMIO, 0x2c13, &mmSPI_SHADER_USER_DATA_PS_7[0], sizeof(mmSPI_SHADER_USER_DATA_PS_7)/sizeof(mmSPI_SHADER_USER_DATA_PS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_8", REG_MMIO, 0x2c14, &mmSPI_SHADER_USER_DATA_PS_8[0], sizeof(mmSPI_SHADER_USER_DATA_PS_8)/sizeof(mmSPI_SHADER_USER_DATA_PS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_9", REG_MMIO, 0x2c15, &mmSPI_SHADER_USER_DATA_PS_9[0], sizeof(mmSPI_SHADER_USER_DATA_PS_9)/sizeof(mmSPI_SHADER_USER_DATA_PS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_10", REG_MMIO, 0x2c16, &mmSPI_SHADER_USER_DATA_PS_10[0], sizeof(mmSPI_SHADER_USER_DATA_PS_10)/sizeof(mmSPI_SHADER_USER_DATA_PS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_11", REG_MMIO, 0x2c17, &mmSPI_SHADER_USER_DATA_PS_11[0], sizeof(mmSPI_SHADER_USER_DATA_PS_11)/sizeof(mmSPI_SHADER_USER_DATA_PS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_12", REG_MMIO, 0x2c18, &mmSPI_SHADER_USER_DATA_PS_12[0], sizeof(mmSPI_SHADER_USER_DATA_PS_12)/sizeof(mmSPI_SHADER_USER_DATA_PS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_13", REG_MMIO, 0x2c19, &mmSPI_SHADER_USER_DATA_PS_13[0], sizeof(mmSPI_SHADER_USER_DATA_PS_13)/sizeof(mmSPI_SHADER_USER_DATA_PS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_14", REG_MMIO, 0x2c1a, &mmSPI_SHADER_USER_DATA_PS_14[0], sizeof(mmSPI_SHADER_USER_DATA_PS_14)/sizeof(mmSPI_SHADER_USER_DATA_PS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_15", REG_MMIO, 0x2c1b, &mmSPI_SHADER_USER_DATA_PS_15[0], sizeof(mmSPI_SHADER_USER_DATA_PS_15)/sizeof(mmSPI_SHADER_USER_DATA_PS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_VS", REG_MMIO, 0x2c40, &mmSPI_SHADER_TBA_LO_VS[0], sizeof(mmSPI_SHADER_TBA_LO_VS)/sizeof(mmSPI_SHADER_TBA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_VS", REG_MMIO, 0x2c41, &mmSPI_SHADER_TBA_HI_VS[0], sizeof(mmSPI_SHADER_TBA_HI_VS)/sizeof(mmSPI_SHADER_TBA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_VS", REG_MMIO, 0x2c42, &mmSPI_SHADER_TMA_LO_VS[0], sizeof(mmSPI_SHADER_TMA_LO_VS)/sizeof(mmSPI_SHADER_TMA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_VS", REG_MMIO, 0x2c43, &mmSPI_SHADER_TMA_HI_VS[0], sizeof(mmSPI_SHADER_TMA_HI_VS)/sizeof(mmSPI_SHADER_TMA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_VS", REG_MMIO, 0x2c46, &mmSPI_SHADER_PGM_RSRC3_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_VS)/sizeof(mmSPI_SHADER_PGM_RSRC3_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_LATE_ALLOC_VS", REG_MMIO, 0x2c47, &mmSPI_SHADER_LATE_ALLOC_VS[0], sizeof(mmSPI_SHADER_LATE_ALLOC_VS)/sizeof(mmSPI_SHADER_LATE_ALLOC_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_VS", REG_MMIO, 0x2c48, &mmSPI_SHADER_PGM_LO_VS[0], sizeof(mmSPI_SHADER_PGM_LO_VS)/sizeof(mmSPI_SHADER_PGM_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_VS", REG_MMIO, 0x2c49, &mmSPI_SHADER_PGM_HI_VS[0], sizeof(mmSPI_SHADER_PGM_HI_VS)/sizeof(mmSPI_SHADER_PGM_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_VS", REG_MMIO, 0x2c4a, &mmSPI_SHADER_PGM_RSRC1_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_VS)/sizeof(mmSPI_SHADER_PGM_RSRC1_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_VS", REG_MMIO, 0x2c4b, &mmSPI_SHADER_PGM_RSRC2_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_0", REG_MMIO, 0x2c4c, &mmSPI_SHADER_USER_DATA_VS_0[0], sizeof(mmSPI_SHADER_USER_DATA_VS_0)/sizeof(mmSPI_SHADER_USER_DATA_VS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_1", REG_MMIO, 0x2c4d, &mmSPI_SHADER_USER_DATA_VS_1[0], sizeof(mmSPI_SHADER_USER_DATA_VS_1)/sizeof(mmSPI_SHADER_USER_DATA_VS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_2", REG_MMIO, 0x2c4e, &mmSPI_SHADER_USER_DATA_VS_2[0], sizeof(mmSPI_SHADER_USER_DATA_VS_2)/sizeof(mmSPI_SHADER_USER_DATA_VS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_3", REG_MMIO, 0x2c4f, &mmSPI_SHADER_USER_DATA_VS_3[0], sizeof(mmSPI_SHADER_USER_DATA_VS_3)/sizeof(mmSPI_SHADER_USER_DATA_VS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_4", REG_MMIO, 0x2c50, &mmSPI_SHADER_USER_DATA_VS_4[0], sizeof(mmSPI_SHADER_USER_DATA_VS_4)/sizeof(mmSPI_SHADER_USER_DATA_VS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_5", REG_MMIO, 0x2c51, &mmSPI_SHADER_USER_DATA_VS_5[0], sizeof(mmSPI_SHADER_USER_DATA_VS_5)/sizeof(mmSPI_SHADER_USER_DATA_VS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_6", REG_MMIO, 0x2c52, &mmSPI_SHADER_USER_DATA_VS_6[0], sizeof(mmSPI_SHADER_USER_DATA_VS_6)/sizeof(mmSPI_SHADER_USER_DATA_VS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_7", REG_MMIO, 0x2c53, &mmSPI_SHADER_USER_DATA_VS_7[0], sizeof(mmSPI_SHADER_USER_DATA_VS_7)/sizeof(mmSPI_SHADER_USER_DATA_VS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_8", REG_MMIO, 0x2c54, &mmSPI_SHADER_USER_DATA_VS_8[0], sizeof(mmSPI_SHADER_USER_DATA_VS_8)/sizeof(mmSPI_SHADER_USER_DATA_VS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_9", REG_MMIO, 0x2c55, &mmSPI_SHADER_USER_DATA_VS_9[0], sizeof(mmSPI_SHADER_USER_DATA_VS_9)/sizeof(mmSPI_SHADER_USER_DATA_VS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_10", REG_MMIO, 0x2c56, &mmSPI_SHADER_USER_DATA_VS_10[0], sizeof(mmSPI_SHADER_USER_DATA_VS_10)/sizeof(mmSPI_SHADER_USER_DATA_VS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_11", REG_MMIO, 0x2c57, &mmSPI_SHADER_USER_DATA_VS_11[0], sizeof(mmSPI_SHADER_USER_DATA_VS_11)/sizeof(mmSPI_SHADER_USER_DATA_VS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_12", REG_MMIO, 0x2c58, &mmSPI_SHADER_USER_DATA_VS_12[0], sizeof(mmSPI_SHADER_USER_DATA_VS_12)/sizeof(mmSPI_SHADER_USER_DATA_VS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_13", REG_MMIO, 0x2c59, &mmSPI_SHADER_USER_DATA_VS_13[0], sizeof(mmSPI_SHADER_USER_DATA_VS_13)/sizeof(mmSPI_SHADER_USER_DATA_VS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_14", REG_MMIO, 0x2c5a, &mmSPI_SHADER_USER_DATA_VS_14[0], sizeof(mmSPI_SHADER_USER_DATA_VS_14)/sizeof(mmSPI_SHADER_USER_DATA_VS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_15", REG_MMIO, 0x2c5b, &mmSPI_SHADER_USER_DATA_VS_15[0], sizeof(mmSPI_SHADER_USER_DATA_VS_15)/sizeof(mmSPI_SHADER_USER_DATA_VS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES_VS", REG_MMIO, 0x2c7c, &mmSPI_SHADER_PGM_RSRC2_ES_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_VS", REG_MMIO, 0x2c7d, &mmSPI_SHADER_PGM_RSRC2_LS_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_GS", REG_MMIO, 0x2c80, &mmSPI_SHADER_TBA_LO_GS[0], sizeof(mmSPI_SHADER_TBA_LO_GS)/sizeof(mmSPI_SHADER_TBA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_GS", REG_MMIO, 0x2c81, &mmSPI_SHADER_TBA_HI_GS[0], sizeof(mmSPI_SHADER_TBA_HI_GS)/sizeof(mmSPI_SHADER_TBA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_GS", REG_MMIO, 0x2c82, &mmSPI_SHADER_TMA_LO_GS[0], sizeof(mmSPI_SHADER_TMA_LO_GS)/sizeof(mmSPI_SHADER_TMA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_GS", REG_MMIO, 0x2c83, &mmSPI_SHADER_TMA_HI_GS[0], sizeof(mmSPI_SHADER_TMA_HI_GS)/sizeof(mmSPI_SHADER_TMA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_GS", REG_MMIO, 0x2c87, &mmSPI_SHADER_PGM_RSRC3_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_GS)/sizeof(mmSPI_SHADER_PGM_RSRC3_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_GS", REG_MMIO, 0x2c88, &mmSPI_SHADER_PGM_LO_GS[0], sizeof(mmSPI_SHADER_PGM_LO_GS)/sizeof(mmSPI_SHADER_PGM_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_GS", REG_MMIO, 0x2c89, &mmSPI_SHADER_PGM_HI_GS[0], sizeof(mmSPI_SHADER_PGM_HI_GS)/sizeof(mmSPI_SHADER_PGM_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_GS", REG_MMIO, 0x2c8a, &mmSPI_SHADER_PGM_RSRC1_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_GS)/sizeof(mmSPI_SHADER_PGM_RSRC1_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_GS", REG_MMIO, 0x2c8b, &mmSPI_SHADER_PGM_RSRC2_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_0", REG_MMIO, 0x2c8c, &mmSPI_SHADER_USER_DATA_GS_0[0], sizeof(mmSPI_SHADER_USER_DATA_GS_0)/sizeof(mmSPI_SHADER_USER_DATA_GS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_1", REG_MMIO, 0x2c8d, &mmSPI_SHADER_USER_DATA_GS_1[0], sizeof(mmSPI_SHADER_USER_DATA_GS_1)/sizeof(mmSPI_SHADER_USER_DATA_GS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_2", REG_MMIO, 0x2c8e, &mmSPI_SHADER_USER_DATA_GS_2[0], sizeof(mmSPI_SHADER_USER_DATA_GS_2)/sizeof(mmSPI_SHADER_USER_DATA_GS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_3", REG_MMIO, 0x2c8f, &mmSPI_SHADER_USER_DATA_GS_3[0], sizeof(mmSPI_SHADER_USER_DATA_GS_3)/sizeof(mmSPI_SHADER_USER_DATA_GS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_4", REG_MMIO, 0x2c90, &mmSPI_SHADER_USER_DATA_GS_4[0], sizeof(mmSPI_SHADER_USER_DATA_GS_4)/sizeof(mmSPI_SHADER_USER_DATA_GS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_5", REG_MMIO, 0x2c91, &mmSPI_SHADER_USER_DATA_GS_5[0], sizeof(mmSPI_SHADER_USER_DATA_GS_5)/sizeof(mmSPI_SHADER_USER_DATA_GS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_6", REG_MMIO, 0x2c92, &mmSPI_SHADER_USER_DATA_GS_6[0], sizeof(mmSPI_SHADER_USER_DATA_GS_6)/sizeof(mmSPI_SHADER_USER_DATA_GS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_7", REG_MMIO, 0x2c93, &mmSPI_SHADER_USER_DATA_GS_7[0], sizeof(mmSPI_SHADER_USER_DATA_GS_7)/sizeof(mmSPI_SHADER_USER_DATA_GS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_8", REG_MMIO, 0x2c94, &mmSPI_SHADER_USER_DATA_GS_8[0], sizeof(mmSPI_SHADER_USER_DATA_GS_8)/sizeof(mmSPI_SHADER_USER_DATA_GS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_9", REG_MMIO, 0x2c95, &mmSPI_SHADER_USER_DATA_GS_9[0], sizeof(mmSPI_SHADER_USER_DATA_GS_9)/sizeof(mmSPI_SHADER_USER_DATA_GS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_10", REG_MMIO, 0x2c96, &mmSPI_SHADER_USER_DATA_GS_10[0], sizeof(mmSPI_SHADER_USER_DATA_GS_10)/sizeof(mmSPI_SHADER_USER_DATA_GS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_11", REG_MMIO, 0x2c97, &mmSPI_SHADER_USER_DATA_GS_11[0], sizeof(mmSPI_SHADER_USER_DATA_GS_11)/sizeof(mmSPI_SHADER_USER_DATA_GS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_12", REG_MMIO, 0x2c98, &mmSPI_SHADER_USER_DATA_GS_12[0], sizeof(mmSPI_SHADER_USER_DATA_GS_12)/sizeof(mmSPI_SHADER_USER_DATA_GS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_13", REG_MMIO, 0x2c99, &mmSPI_SHADER_USER_DATA_GS_13[0], sizeof(mmSPI_SHADER_USER_DATA_GS_13)/sizeof(mmSPI_SHADER_USER_DATA_GS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_14", REG_MMIO, 0x2c9a, &mmSPI_SHADER_USER_DATA_GS_14[0], sizeof(mmSPI_SHADER_USER_DATA_GS_14)/sizeof(mmSPI_SHADER_USER_DATA_GS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_15", REG_MMIO, 0x2c9b, &mmSPI_SHADER_USER_DATA_GS_15[0], sizeof(mmSPI_SHADER_USER_DATA_GS_15)/sizeof(mmSPI_SHADER_USER_DATA_GS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES_GS", REG_MMIO, 0x2cbc, &mmSPI_SHADER_PGM_RSRC2_ES_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_ES", REG_MMIO, 0x2cc0, &mmSPI_SHADER_TBA_LO_ES[0], sizeof(mmSPI_SHADER_TBA_LO_ES)/sizeof(mmSPI_SHADER_TBA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_ES", REG_MMIO, 0x2cc1, &mmSPI_SHADER_TBA_HI_ES[0], sizeof(mmSPI_SHADER_TBA_HI_ES)/sizeof(mmSPI_SHADER_TBA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_ES", REG_MMIO, 0x2cc2, &mmSPI_SHADER_TMA_LO_ES[0], sizeof(mmSPI_SHADER_TMA_LO_ES)/sizeof(mmSPI_SHADER_TMA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_ES", REG_MMIO, 0x2cc3, &mmSPI_SHADER_TMA_HI_ES[0], sizeof(mmSPI_SHADER_TMA_HI_ES)/sizeof(mmSPI_SHADER_TMA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_ES", REG_MMIO, 0x2cc7, &mmSPI_SHADER_PGM_RSRC3_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC3_ES)/sizeof(mmSPI_SHADER_PGM_RSRC3_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_ES", REG_MMIO, 0x2cc8, &mmSPI_SHADER_PGM_LO_ES[0], sizeof(mmSPI_SHADER_PGM_LO_ES)/sizeof(mmSPI_SHADER_PGM_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_ES", REG_MMIO, 0x2cc9, &mmSPI_SHADER_PGM_HI_ES[0], sizeof(mmSPI_SHADER_PGM_HI_ES)/sizeof(mmSPI_SHADER_PGM_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_ES", REG_MMIO, 0x2cca, &mmSPI_SHADER_PGM_RSRC1_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC1_ES)/sizeof(mmSPI_SHADER_PGM_RSRC1_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES", REG_MMIO, 0x2ccb, &mmSPI_SHADER_PGM_RSRC2_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_0", REG_MMIO, 0x2ccc, &mmSPI_SHADER_USER_DATA_ES_0[0], sizeof(mmSPI_SHADER_USER_DATA_ES_0)/sizeof(mmSPI_SHADER_USER_DATA_ES_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_1", REG_MMIO, 0x2ccd, &mmSPI_SHADER_USER_DATA_ES_1[0], sizeof(mmSPI_SHADER_USER_DATA_ES_1)/sizeof(mmSPI_SHADER_USER_DATA_ES_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_2", REG_MMIO, 0x2cce, &mmSPI_SHADER_USER_DATA_ES_2[0], sizeof(mmSPI_SHADER_USER_DATA_ES_2)/sizeof(mmSPI_SHADER_USER_DATA_ES_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_3", REG_MMIO, 0x2ccf, &mmSPI_SHADER_USER_DATA_ES_3[0], sizeof(mmSPI_SHADER_USER_DATA_ES_3)/sizeof(mmSPI_SHADER_USER_DATA_ES_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_4", REG_MMIO, 0x2cd0, &mmSPI_SHADER_USER_DATA_ES_4[0], sizeof(mmSPI_SHADER_USER_DATA_ES_4)/sizeof(mmSPI_SHADER_USER_DATA_ES_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_5", REG_MMIO, 0x2cd1, &mmSPI_SHADER_USER_DATA_ES_5[0], sizeof(mmSPI_SHADER_USER_DATA_ES_5)/sizeof(mmSPI_SHADER_USER_DATA_ES_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_6", REG_MMIO, 0x2cd2, &mmSPI_SHADER_USER_DATA_ES_6[0], sizeof(mmSPI_SHADER_USER_DATA_ES_6)/sizeof(mmSPI_SHADER_USER_DATA_ES_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_7", REG_MMIO, 0x2cd3, &mmSPI_SHADER_USER_DATA_ES_7[0], sizeof(mmSPI_SHADER_USER_DATA_ES_7)/sizeof(mmSPI_SHADER_USER_DATA_ES_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_8", REG_MMIO, 0x2cd4, &mmSPI_SHADER_USER_DATA_ES_8[0], sizeof(mmSPI_SHADER_USER_DATA_ES_8)/sizeof(mmSPI_SHADER_USER_DATA_ES_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_9", REG_MMIO, 0x2cd5, &mmSPI_SHADER_USER_DATA_ES_9[0], sizeof(mmSPI_SHADER_USER_DATA_ES_9)/sizeof(mmSPI_SHADER_USER_DATA_ES_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_10", REG_MMIO, 0x2cd6, &mmSPI_SHADER_USER_DATA_ES_10[0], sizeof(mmSPI_SHADER_USER_DATA_ES_10)/sizeof(mmSPI_SHADER_USER_DATA_ES_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_11", REG_MMIO, 0x2cd7, &mmSPI_SHADER_USER_DATA_ES_11[0], sizeof(mmSPI_SHADER_USER_DATA_ES_11)/sizeof(mmSPI_SHADER_USER_DATA_ES_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_12", REG_MMIO, 0x2cd8, &mmSPI_SHADER_USER_DATA_ES_12[0], sizeof(mmSPI_SHADER_USER_DATA_ES_12)/sizeof(mmSPI_SHADER_USER_DATA_ES_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_13", REG_MMIO, 0x2cd9, &mmSPI_SHADER_USER_DATA_ES_13[0], sizeof(mmSPI_SHADER_USER_DATA_ES_13)/sizeof(mmSPI_SHADER_USER_DATA_ES_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_14", REG_MMIO, 0x2cda, &mmSPI_SHADER_USER_DATA_ES_14[0], sizeof(mmSPI_SHADER_USER_DATA_ES_14)/sizeof(mmSPI_SHADER_USER_DATA_ES_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_15", REG_MMIO, 0x2cdb, &mmSPI_SHADER_USER_DATA_ES_15[0], sizeof(mmSPI_SHADER_USER_DATA_ES_15)/sizeof(mmSPI_SHADER_USER_DATA_ES_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_ES", REG_MMIO, 0x2cfd, &mmSPI_SHADER_PGM_RSRC2_LS_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_HS", REG_MMIO, 0x2d00, &mmSPI_SHADER_TBA_LO_HS[0], sizeof(mmSPI_SHADER_TBA_LO_HS)/sizeof(mmSPI_SHADER_TBA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_HS", REG_MMIO, 0x2d01, &mmSPI_SHADER_TBA_HI_HS[0], sizeof(mmSPI_SHADER_TBA_HI_HS)/sizeof(mmSPI_SHADER_TBA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_HS", REG_MMIO, 0x2d02, &mmSPI_SHADER_TMA_LO_HS[0], sizeof(mmSPI_SHADER_TMA_LO_HS)/sizeof(mmSPI_SHADER_TMA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_HS", REG_MMIO, 0x2d03, &mmSPI_SHADER_TMA_HI_HS[0], sizeof(mmSPI_SHADER_TMA_HI_HS)/sizeof(mmSPI_SHADER_TMA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_HS", REG_MMIO, 0x2d07, &mmSPI_SHADER_PGM_RSRC3_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_HS)/sizeof(mmSPI_SHADER_PGM_RSRC3_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_HS", REG_MMIO, 0x2d08, &mmSPI_SHADER_PGM_LO_HS[0], sizeof(mmSPI_SHADER_PGM_LO_HS)/sizeof(mmSPI_SHADER_PGM_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_HS", REG_MMIO, 0x2d09, &mmSPI_SHADER_PGM_HI_HS[0], sizeof(mmSPI_SHADER_PGM_HI_HS)/sizeof(mmSPI_SHADER_PGM_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_HS", REG_MMIO, 0x2d0a, &mmSPI_SHADER_PGM_RSRC1_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_HS)/sizeof(mmSPI_SHADER_PGM_RSRC1_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_HS", REG_MMIO, 0x2d0b, &mmSPI_SHADER_PGM_RSRC2_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_0", REG_MMIO, 0x2d0c, &mmSPI_SHADER_USER_DATA_HS_0[0], sizeof(mmSPI_SHADER_USER_DATA_HS_0)/sizeof(mmSPI_SHADER_USER_DATA_HS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_1", REG_MMIO, 0x2d0d, &mmSPI_SHADER_USER_DATA_HS_1[0], sizeof(mmSPI_SHADER_USER_DATA_HS_1)/sizeof(mmSPI_SHADER_USER_DATA_HS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_2", REG_MMIO, 0x2d0e, &mmSPI_SHADER_USER_DATA_HS_2[0], sizeof(mmSPI_SHADER_USER_DATA_HS_2)/sizeof(mmSPI_SHADER_USER_DATA_HS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_3", REG_MMIO, 0x2d0f, &mmSPI_SHADER_USER_DATA_HS_3[0], sizeof(mmSPI_SHADER_USER_DATA_HS_3)/sizeof(mmSPI_SHADER_USER_DATA_HS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_4", REG_MMIO, 0x2d10, &mmSPI_SHADER_USER_DATA_HS_4[0], sizeof(mmSPI_SHADER_USER_DATA_HS_4)/sizeof(mmSPI_SHADER_USER_DATA_HS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_5", REG_MMIO, 0x2d11, &mmSPI_SHADER_USER_DATA_HS_5[0], sizeof(mmSPI_SHADER_USER_DATA_HS_5)/sizeof(mmSPI_SHADER_USER_DATA_HS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_6", REG_MMIO, 0x2d12, &mmSPI_SHADER_USER_DATA_HS_6[0], sizeof(mmSPI_SHADER_USER_DATA_HS_6)/sizeof(mmSPI_SHADER_USER_DATA_HS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_7", REG_MMIO, 0x2d13, &mmSPI_SHADER_USER_DATA_HS_7[0], sizeof(mmSPI_SHADER_USER_DATA_HS_7)/sizeof(mmSPI_SHADER_USER_DATA_HS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_8", REG_MMIO, 0x2d14, &mmSPI_SHADER_USER_DATA_HS_8[0], sizeof(mmSPI_SHADER_USER_DATA_HS_8)/sizeof(mmSPI_SHADER_USER_DATA_HS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_9", REG_MMIO, 0x2d15, &mmSPI_SHADER_USER_DATA_HS_9[0], sizeof(mmSPI_SHADER_USER_DATA_HS_9)/sizeof(mmSPI_SHADER_USER_DATA_HS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_10", REG_MMIO, 0x2d16, &mmSPI_SHADER_USER_DATA_HS_10[0], sizeof(mmSPI_SHADER_USER_DATA_HS_10)/sizeof(mmSPI_SHADER_USER_DATA_HS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_11", REG_MMIO, 0x2d17, &mmSPI_SHADER_USER_DATA_HS_11[0], sizeof(mmSPI_SHADER_USER_DATA_HS_11)/sizeof(mmSPI_SHADER_USER_DATA_HS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_12", REG_MMIO, 0x2d18, &mmSPI_SHADER_USER_DATA_HS_12[0], sizeof(mmSPI_SHADER_USER_DATA_HS_12)/sizeof(mmSPI_SHADER_USER_DATA_HS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_13", REG_MMIO, 0x2d19, &mmSPI_SHADER_USER_DATA_HS_13[0], sizeof(mmSPI_SHADER_USER_DATA_HS_13)/sizeof(mmSPI_SHADER_USER_DATA_HS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_14", REG_MMIO, 0x2d1a, &mmSPI_SHADER_USER_DATA_HS_14[0], sizeof(mmSPI_SHADER_USER_DATA_HS_14)/sizeof(mmSPI_SHADER_USER_DATA_HS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_15", REG_MMIO, 0x2d1b, &mmSPI_SHADER_USER_DATA_HS_15[0], sizeof(mmSPI_SHADER_USER_DATA_HS_15)/sizeof(mmSPI_SHADER_USER_DATA_HS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_HS", REG_MMIO, 0x2d3d, &mmSPI_SHADER_PGM_RSRC2_LS_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_LS", REG_MMIO, 0x2d40, &mmSPI_SHADER_TBA_LO_LS[0], sizeof(mmSPI_SHADER_TBA_LO_LS)/sizeof(mmSPI_SHADER_TBA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_LS", REG_MMIO, 0x2d41, &mmSPI_SHADER_TBA_HI_LS[0], sizeof(mmSPI_SHADER_TBA_HI_LS)/sizeof(mmSPI_SHADER_TBA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_LS", REG_MMIO, 0x2d42, &mmSPI_SHADER_TMA_LO_LS[0], sizeof(mmSPI_SHADER_TMA_LO_LS)/sizeof(mmSPI_SHADER_TMA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_LS", REG_MMIO, 0x2d43, &mmSPI_SHADER_TMA_HI_LS[0], sizeof(mmSPI_SHADER_TMA_HI_LS)/sizeof(mmSPI_SHADER_TMA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_LS", REG_MMIO, 0x2d47, &mmSPI_SHADER_PGM_RSRC3_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_LS)/sizeof(mmSPI_SHADER_PGM_RSRC3_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_LS", REG_MMIO, 0x2d48, &mmSPI_SHADER_PGM_LO_LS[0], sizeof(mmSPI_SHADER_PGM_LO_LS)/sizeof(mmSPI_SHADER_PGM_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_LS", REG_MMIO, 0x2d49, &mmSPI_SHADER_PGM_HI_LS[0], sizeof(mmSPI_SHADER_PGM_HI_LS)/sizeof(mmSPI_SHADER_PGM_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_LS", REG_MMIO, 0x2d4a, &mmSPI_SHADER_PGM_RSRC1_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_LS)/sizeof(mmSPI_SHADER_PGM_RSRC1_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS", REG_MMIO, 0x2d4b, &mmSPI_SHADER_PGM_RSRC2_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_0", REG_MMIO, 0x2d4c, &mmSPI_SHADER_USER_DATA_LS_0[0], sizeof(mmSPI_SHADER_USER_DATA_LS_0)/sizeof(mmSPI_SHADER_USER_DATA_LS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_1", REG_MMIO, 0x2d4d, &mmSPI_SHADER_USER_DATA_LS_1[0], sizeof(mmSPI_SHADER_USER_DATA_LS_1)/sizeof(mmSPI_SHADER_USER_DATA_LS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_2", REG_MMIO, 0x2d4e, &mmSPI_SHADER_USER_DATA_LS_2[0], sizeof(mmSPI_SHADER_USER_DATA_LS_2)/sizeof(mmSPI_SHADER_USER_DATA_LS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_3", REG_MMIO, 0x2d4f, &mmSPI_SHADER_USER_DATA_LS_3[0], sizeof(mmSPI_SHADER_USER_DATA_LS_3)/sizeof(mmSPI_SHADER_USER_DATA_LS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_4", REG_MMIO, 0x2d50, &mmSPI_SHADER_USER_DATA_LS_4[0], sizeof(mmSPI_SHADER_USER_DATA_LS_4)/sizeof(mmSPI_SHADER_USER_DATA_LS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_5", REG_MMIO, 0x2d51, &mmSPI_SHADER_USER_DATA_LS_5[0], sizeof(mmSPI_SHADER_USER_DATA_LS_5)/sizeof(mmSPI_SHADER_USER_DATA_LS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_6", REG_MMIO, 0x2d52, &mmSPI_SHADER_USER_DATA_LS_6[0], sizeof(mmSPI_SHADER_USER_DATA_LS_6)/sizeof(mmSPI_SHADER_USER_DATA_LS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_7", REG_MMIO, 0x2d53, &mmSPI_SHADER_USER_DATA_LS_7[0], sizeof(mmSPI_SHADER_USER_DATA_LS_7)/sizeof(mmSPI_SHADER_USER_DATA_LS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_8", REG_MMIO, 0x2d54, &mmSPI_SHADER_USER_DATA_LS_8[0], sizeof(mmSPI_SHADER_USER_DATA_LS_8)/sizeof(mmSPI_SHADER_USER_DATA_LS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_9", REG_MMIO, 0x2d55, &mmSPI_SHADER_USER_DATA_LS_9[0], sizeof(mmSPI_SHADER_USER_DATA_LS_9)/sizeof(mmSPI_SHADER_USER_DATA_LS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_10", REG_MMIO, 0x2d56, &mmSPI_SHADER_USER_DATA_LS_10[0], sizeof(mmSPI_SHADER_USER_DATA_LS_10)/sizeof(mmSPI_SHADER_USER_DATA_LS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_11", REG_MMIO, 0x2d57, &mmSPI_SHADER_USER_DATA_LS_11[0], sizeof(mmSPI_SHADER_USER_DATA_LS_11)/sizeof(mmSPI_SHADER_USER_DATA_LS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_12", REG_MMIO, 0x2d58, &mmSPI_SHADER_USER_DATA_LS_12[0], sizeof(mmSPI_SHADER_USER_DATA_LS_12)/sizeof(mmSPI_SHADER_USER_DATA_LS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_13", REG_MMIO, 0x2d59, &mmSPI_SHADER_USER_DATA_LS_13[0], sizeof(mmSPI_SHADER_USER_DATA_LS_13)/sizeof(mmSPI_SHADER_USER_DATA_LS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_14", REG_MMIO, 0x2d5a, &mmSPI_SHADER_USER_DATA_LS_14[0], sizeof(mmSPI_SHADER_USER_DATA_LS_14)/sizeof(mmSPI_SHADER_USER_DATA_LS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_15", REG_MMIO, 0x2d5b, &mmSPI_SHADER_USER_DATA_LS_15[0], sizeof(mmSPI_SHADER_USER_DATA_LS_15)/sizeof(mmSPI_SHADER_USER_DATA_LS_15[0]), 0, 0 },
+	{ "mmCOMPUTE_DISPATCH_INITIATOR", REG_MMIO, 0x2e00, &mmCOMPUTE_DISPATCH_INITIATOR[0], sizeof(mmCOMPUTE_DISPATCH_INITIATOR)/sizeof(mmCOMPUTE_DISPATCH_INITIATOR[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_X", REG_MMIO, 0x2e01, &mmCOMPUTE_DIM_X[0], sizeof(mmCOMPUTE_DIM_X)/sizeof(mmCOMPUTE_DIM_X[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Y", REG_MMIO, 0x2e02, &mmCOMPUTE_DIM_Y[0], sizeof(mmCOMPUTE_DIM_Y)/sizeof(mmCOMPUTE_DIM_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Z", REG_MMIO, 0x2e03, &mmCOMPUTE_DIM_Z[0], sizeof(mmCOMPUTE_DIM_Z)/sizeof(mmCOMPUTE_DIM_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_START_X", REG_MMIO, 0x2e04, &mmCOMPUTE_START_X[0], sizeof(mmCOMPUTE_START_X)/sizeof(mmCOMPUTE_START_X[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Y", REG_MMIO, 0x2e05, &mmCOMPUTE_START_Y[0], sizeof(mmCOMPUTE_START_Y)/sizeof(mmCOMPUTE_START_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Z", REG_MMIO, 0x2e06, &mmCOMPUTE_START_Z[0], sizeof(mmCOMPUTE_START_Z)/sizeof(mmCOMPUTE_START_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_X", REG_MMIO, 0x2e07, &mmCOMPUTE_NUM_THREAD_X[0], sizeof(mmCOMPUTE_NUM_THREAD_X)/sizeof(mmCOMPUTE_NUM_THREAD_X[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Y", REG_MMIO, 0x2e08, &mmCOMPUTE_NUM_THREAD_Y[0], sizeof(mmCOMPUTE_NUM_THREAD_Y)/sizeof(mmCOMPUTE_NUM_THREAD_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Z", REG_MMIO, 0x2e09, &mmCOMPUTE_NUM_THREAD_Z[0], sizeof(mmCOMPUTE_NUM_THREAD_Z)/sizeof(mmCOMPUTE_NUM_THREAD_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_PIPELINESTAT_ENABLE", REG_MMIO, 0x2e0a, &mmCOMPUTE_PIPELINESTAT_ENABLE[0], sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE)/sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_PERFCOUNT_ENABLE", REG_MMIO, 0x2e0b, &mmCOMPUTE_PERFCOUNT_ENABLE[0], sizeof(mmCOMPUTE_PERFCOUNT_ENABLE)/sizeof(mmCOMPUTE_PERFCOUNT_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_LO", REG_MMIO, 0x2e0c, &mmCOMPUTE_PGM_LO[0], sizeof(mmCOMPUTE_PGM_LO)/sizeof(mmCOMPUTE_PGM_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_HI", REG_MMIO, 0x2e0d, &mmCOMPUTE_PGM_HI[0], sizeof(mmCOMPUTE_PGM_HI)/sizeof(mmCOMPUTE_PGM_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_LO", REG_MMIO, 0x2e0e, &mmCOMPUTE_TBA_LO[0], sizeof(mmCOMPUTE_TBA_LO)/sizeof(mmCOMPUTE_TBA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_HI", REG_MMIO, 0x2e0f, &mmCOMPUTE_TBA_HI[0], sizeof(mmCOMPUTE_TBA_HI)/sizeof(mmCOMPUTE_TBA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_LO", REG_MMIO, 0x2e10, &mmCOMPUTE_TMA_LO[0], sizeof(mmCOMPUTE_TMA_LO)/sizeof(mmCOMPUTE_TMA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_HI", REG_MMIO, 0x2e11, &mmCOMPUTE_TMA_HI[0], sizeof(mmCOMPUTE_TMA_HI)/sizeof(mmCOMPUTE_TMA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC1", REG_MMIO, 0x2e12, &mmCOMPUTE_PGM_RSRC1[0], sizeof(mmCOMPUTE_PGM_RSRC1)/sizeof(mmCOMPUTE_PGM_RSRC1[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC2", REG_MMIO, 0x2e13, &mmCOMPUTE_PGM_RSRC2[0], sizeof(mmCOMPUTE_PGM_RSRC2)/sizeof(mmCOMPUTE_PGM_RSRC2[0]), 0, 0 },
+	{ "mmCOMPUTE_VMID", REG_MMIO, 0x2e14, &mmCOMPUTE_VMID[0], sizeof(mmCOMPUTE_VMID)/sizeof(mmCOMPUTE_VMID[0]), 0, 0 },
+	{ "mmCOMPUTE_RESOURCE_LIMITS", REG_MMIO, 0x2e15, &mmCOMPUTE_RESOURCE_LIMITS[0], sizeof(mmCOMPUTE_RESOURCE_LIMITS)/sizeof(mmCOMPUTE_RESOURCE_LIMITS[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE0", REG_MMIO, 0x2e16, &mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE1", REG_MMIO, 0x2e17, &mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0]), 0, 0 },
+	{ "mmCOMPUTE_TMPRING_SIZE", REG_MMIO, 0x2e18, &mmCOMPUTE_TMPRING_SIZE[0], sizeof(mmCOMPUTE_TMPRING_SIZE)/sizeof(mmCOMPUTE_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE2", REG_MMIO, 0x2e19, &mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE3", REG_MMIO, 0x2e1a, &mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_X", REG_MMIO, 0x2e1b, &mmCOMPUTE_RESTART_X[0], sizeof(mmCOMPUTE_RESTART_X)/sizeof(mmCOMPUTE_RESTART_X[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_Y", REG_MMIO, 0x2e1c, &mmCOMPUTE_RESTART_Y[0], sizeof(mmCOMPUTE_RESTART_Y)/sizeof(mmCOMPUTE_RESTART_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_Z", REG_MMIO, 0x2e1d, &mmCOMPUTE_RESTART_Z[0], sizeof(mmCOMPUTE_RESTART_Z)/sizeof(mmCOMPUTE_RESTART_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_THREAD_TRACE_ENABLE", REG_MMIO, 0x2e1e, &mmCOMPUTE_THREAD_TRACE_ENABLE[0], sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE)/sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_MISC_RESERVED", REG_MMIO, 0x2e1f, &mmCOMPUTE_MISC_RESERVED[0], sizeof(mmCOMPUTE_MISC_RESERVED)/sizeof(mmCOMPUTE_MISC_RESERVED[0]), 0, 0 },
+	{ "mmCOMPUTE_DISPATCH_ID", REG_MMIO, 0x2e20, &mmCOMPUTE_DISPATCH_ID[0], sizeof(mmCOMPUTE_DISPATCH_ID)/sizeof(mmCOMPUTE_DISPATCH_ID[0]), 0, 0 },
+	{ "mmCOMPUTE_THREADGROUP_ID", REG_MMIO, 0x2e21, &mmCOMPUTE_THREADGROUP_ID[0], sizeof(mmCOMPUTE_THREADGROUP_ID)/sizeof(mmCOMPUTE_THREADGROUP_ID[0]), 0, 0 },
+	{ "mmCOMPUTE_RELAUNCH", REG_MMIO, 0x2e22, &mmCOMPUTE_RELAUNCH[0], sizeof(mmCOMPUTE_RELAUNCH)/sizeof(mmCOMPUTE_RELAUNCH[0]), 0, 0 },
+	{ "mmCOMPUTE_WAVE_RESTORE_ADDR_LO", REG_MMIO, 0x2e23, &mmCOMPUTE_WAVE_RESTORE_ADDR_LO[0], sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_LO)/sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_WAVE_RESTORE_ADDR_HI", REG_MMIO, 0x2e24, &mmCOMPUTE_WAVE_RESTORE_ADDR_HI[0], sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_HI)/sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_WAVE_RESTORE_CONTROL", REG_MMIO, 0x2e25, &mmCOMPUTE_WAVE_RESTORE_CONTROL[0], sizeof(mmCOMPUTE_WAVE_RESTORE_CONTROL)/sizeof(mmCOMPUTE_WAVE_RESTORE_CONTROL[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_0", REG_MMIO, 0x2e40, &mmCOMPUTE_USER_DATA_0[0], sizeof(mmCOMPUTE_USER_DATA_0)/sizeof(mmCOMPUTE_USER_DATA_0[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_1", REG_MMIO, 0x2e41, &mmCOMPUTE_USER_DATA_1[0], sizeof(mmCOMPUTE_USER_DATA_1)/sizeof(mmCOMPUTE_USER_DATA_1[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_2", REG_MMIO, 0x2e42, &mmCOMPUTE_USER_DATA_2[0], sizeof(mmCOMPUTE_USER_DATA_2)/sizeof(mmCOMPUTE_USER_DATA_2[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_3", REG_MMIO, 0x2e43, &mmCOMPUTE_USER_DATA_3[0], sizeof(mmCOMPUTE_USER_DATA_3)/sizeof(mmCOMPUTE_USER_DATA_3[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_4", REG_MMIO, 0x2e44, &mmCOMPUTE_USER_DATA_4[0], sizeof(mmCOMPUTE_USER_DATA_4)/sizeof(mmCOMPUTE_USER_DATA_4[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_5", REG_MMIO, 0x2e45, &mmCOMPUTE_USER_DATA_5[0], sizeof(mmCOMPUTE_USER_DATA_5)/sizeof(mmCOMPUTE_USER_DATA_5[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_6", REG_MMIO, 0x2e46, &mmCOMPUTE_USER_DATA_6[0], sizeof(mmCOMPUTE_USER_DATA_6)/sizeof(mmCOMPUTE_USER_DATA_6[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_7", REG_MMIO, 0x2e47, &mmCOMPUTE_USER_DATA_7[0], sizeof(mmCOMPUTE_USER_DATA_7)/sizeof(mmCOMPUTE_USER_DATA_7[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_8", REG_MMIO, 0x2e48, &mmCOMPUTE_USER_DATA_8[0], sizeof(mmCOMPUTE_USER_DATA_8)/sizeof(mmCOMPUTE_USER_DATA_8[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_9", REG_MMIO, 0x2e49, &mmCOMPUTE_USER_DATA_9[0], sizeof(mmCOMPUTE_USER_DATA_9)/sizeof(mmCOMPUTE_USER_DATA_9[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_10", REG_MMIO, 0x2e4a, &mmCOMPUTE_USER_DATA_10[0], sizeof(mmCOMPUTE_USER_DATA_10)/sizeof(mmCOMPUTE_USER_DATA_10[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_11", REG_MMIO, 0x2e4b, &mmCOMPUTE_USER_DATA_11[0], sizeof(mmCOMPUTE_USER_DATA_11)/sizeof(mmCOMPUTE_USER_DATA_11[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_12", REG_MMIO, 0x2e4c, &mmCOMPUTE_USER_DATA_12[0], sizeof(mmCOMPUTE_USER_DATA_12)/sizeof(mmCOMPUTE_USER_DATA_12[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_13", REG_MMIO, 0x2e4d, &mmCOMPUTE_USER_DATA_13[0], sizeof(mmCOMPUTE_USER_DATA_13)/sizeof(mmCOMPUTE_USER_DATA_13[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_14", REG_MMIO, 0x2e4e, &mmCOMPUTE_USER_DATA_14[0], sizeof(mmCOMPUTE_USER_DATA_14)/sizeof(mmCOMPUTE_USER_DATA_14[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_15", REG_MMIO, 0x2e4f, &mmCOMPUTE_USER_DATA_15[0], sizeof(mmCOMPUTE_USER_DATA_15)/sizeof(mmCOMPUTE_USER_DATA_15[0]), 0, 0 },
+	{ "mmCOMPUTE_NOWHERE", REG_MMIO, 0x2e7f, &mmCOMPUTE_NOWHERE[0], sizeof(mmCOMPUTE_NOWHERE)/sizeof(mmCOMPUTE_NOWHERE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG03", REG_SMC, 0x3, &ixCLIPPER_DEBUG_REG03[0], sizeof(ixCLIPPER_DEBUG_REG03)/sizeof(ixCLIPPER_DEBUG_REG03[0]), 0, 0 },
+	{ "ixDIDT_SQ_CTRL_OCP", REG_SMC, 0x3, &ixDIDT_SQ_CTRL_OCP[0], sizeof(ixDIDT_SQ_CTRL_OCP)/sizeof(ixDIDT_SQ_CTRL_OCP[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG3", REG_SMC, 0x3, &ixGDS_DEBUG_REG3[0], sizeof(ixGDS_DEBUG_REG3)/sizeof(ixGDS_DEBUG_REG3[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG3", REG_SMC, 0x3, &ixWD_DEBUG_REG3[0], sizeof(ixWD_DEBUG_REG3)/sizeof(ixWD_DEBUG_REG3[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT0_3", REG_SMC, 0x30, &ixDIDT_DB_WEIGHT0_3[0], sizeof(ixDIDT_DB_WEIGHT0_3)/sizeof(ixDIDT_DB_WEIGHT0_3[0]), 0, 0 },
+	{ "mmCP_DFY_CNTL", REG_MMIO, 0x3020, &mmCP_DFY_CNTL[0], sizeof(mmCP_DFY_CNTL)/sizeof(mmCP_DFY_CNTL[0]), 0, 0 },
+	{ "mmCP_DFY_STAT", REG_MMIO, 0x3021, &mmCP_DFY_STAT[0], sizeof(mmCP_DFY_STAT)/sizeof(mmCP_DFY_STAT[0]), 0, 0 },
+	{ "mmCP_DFY_ADDR_HI", REG_MMIO, 0x3022, &mmCP_DFY_ADDR_HI[0], sizeof(mmCP_DFY_ADDR_HI)/sizeof(mmCP_DFY_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DFY_ADDR_LO", REG_MMIO, 0x3023, &mmCP_DFY_ADDR_LO[0], sizeof(mmCP_DFY_ADDR_LO)/sizeof(mmCP_DFY_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_0", REG_MMIO, 0x3024, &mmCP_DFY_DATA_0[0], sizeof(mmCP_DFY_DATA_0)/sizeof(mmCP_DFY_DATA_0[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_1", REG_MMIO, 0x3025, &mmCP_DFY_DATA_1[0], sizeof(mmCP_DFY_DATA_1)/sizeof(mmCP_DFY_DATA_1[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_2", REG_MMIO, 0x3026, &mmCP_DFY_DATA_2[0], sizeof(mmCP_DFY_DATA_2)/sizeof(mmCP_DFY_DATA_2[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_3", REG_MMIO, 0x3027, &mmCP_DFY_DATA_3[0], sizeof(mmCP_DFY_DATA_3)/sizeof(mmCP_DFY_DATA_3[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_4", REG_MMIO, 0x3028, &mmCP_DFY_DATA_4[0], sizeof(mmCP_DFY_DATA_4)/sizeof(mmCP_DFY_DATA_4[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_5", REG_MMIO, 0x3029, &mmCP_DFY_DATA_5[0], sizeof(mmCP_DFY_DATA_5)/sizeof(mmCP_DFY_DATA_5[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_6", REG_MMIO, 0x302a, &mmCP_DFY_DATA_6[0], sizeof(mmCP_DFY_DATA_6)/sizeof(mmCP_DFY_DATA_6[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_7", REG_MMIO, 0x302b, &mmCP_DFY_DATA_7[0], sizeof(mmCP_DFY_DATA_7)/sizeof(mmCP_DFY_DATA_7[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_8", REG_MMIO, 0x302c, &mmCP_DFY_DATA_8[0], sizeof(mmCP_DFY_DATA_8)/sizeof(mmCP_DFY_DATA_8[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_9", REG_MMIO, 0x302d, &mmCP_DFY_DATA_9[0], sizeof(mmCP_DFY_DATA_9)/sizeof(mmCP_DFY_DATA_9[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_10", REG_MMIO, 0x302e, &mmCP_DFY_DATA_10[0], sizeof(mmCP_DFY_DATA_10)/sizeof(mmCP_DFY_DATA_10[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_11", REG_MMIO, 0x302f, &mmCP_DFY_DATA_11[0], sizeof(mmCP_DFY_DATA_11)/sizeof(mmCP_DFY_DATA_11[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_12", REG_MMIO, 0x3030, &mmCP_DFY_DATA_12[0], sizeof(mmCP_DFY_DATA_12)/sizeof(mmCP_DFY_DATA_12[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_13", REG_MMIO, 0x3031, &mmCP_DFY_DATA_13[0], sizeof(mmCP_DFY_DATA_13)/sizeof(mmCP_DFY_DATA_13[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_14", REG_MMIO, 0x3032, &mmCP_DFY_DATA_14[0], sizeof(mmCP_DFY_DATA_14)/sizeof(mmCP_DFY_DATA_14[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_15", REG_MMIO, 0x3033, &mmCP_DFY_DATA_15[0], sizeof(mmCP_DFY_DATA_15)/sizeof(mmCP_DFY_DATA_15[0]), 0, 0 },
+	{ "mmCP_DFY_CMD", REG_MMIO, 0x3034, &mmCP_DFY_CMD[0], sizeof(mmCP_DFY_CMD)/sizeof(mmCP_DFY_CMD[0]), 0, 0 },
+	{ "mmCP_CPC_MGCG_SYNC_CNTL", REG_MMIO, 0x3036, &mmCP_CPC_MGCG_SYNC_CNTL[0], sizeof(mmCP_CPC_MGCG_SYNC_CNTL)/sizeof(mmCP_CPC_MGCG_SYNC_CNTL[0]), 0, 0 },
+	{ "mmCP_VIRT_STATUS", REG_MMIO, 0x3038, &mmCP_VIRT_STATUS[0], sizeof(mmCP_VIRT_STATUS)/sizeof(mmCP_VIRT_STATUS[0]), 0, 0 },
+	{ "mmCP_RB0_BASE", REG_MMIO, 0x3040, &mmCP_RB0_BASE[0], sizeof(mmCP_RB0_BASE)/sizeof(mmCP_RB0_BASE[0]), 0, 0 },
+	{ "mmCP_RB_BASE", REG_MMIO, 0x3040, &mmCP_RB_BASE[0], sizeof(mmCP_RB_BASE)/sizeof(mmCP_RB_BASE[0]), 0, 0 },
+	{ "mmCP_RB0_CNTL", REG_MMIO, 0x3041, &mmCP_RB0_CNTL[0], sizeof(mmCP_RB0_CNTL)/sizeof(mmCP_RB0_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_CNTL", REG_MMIO, 0x3041, &mmCP_RB_CNTL[0], sizeof(mmCP_RB_CNTL)/sizeof(mmCP_RB_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_WR", REG_MMIO, 0x3042, &mmCP_RB_RPTR_WR[0], sizeof(mmCP_RB_RPTR_WR)/sizeof(mmCP_RB_RPTR_WR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB0_RPTR_ADDR[0], sizeof(mmCP_RB0_RPTR_ADDR)/sizeof(mmCP_RB0_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB_RPTR_ADDR[0], sizeof(mmCP_RB_RPTR_ADDR)/sizeof(mmCP_RB_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB0_RPTR_ADDR_HI[0], sizeof(mmCP_RB0_RPTR_ADDR_HI)/sizeof(mmCP_RB0_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB_RPTR_ADDR_HI[0], sizeof(mmCP_RB_RPTR_ADDR_HI)/sizeof(mmCP_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB0_WPTR", REG_MMIO, 0x3045, &mmCP_RB0_WPTR[0], sizeof(mmCP_RB0_WPTR)/sizeof(mmCP_RB0_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR", REG_MMIO, 0x3045, &mmCP_RB_WPTR[0], sizeof(mmCP_RB_WPTR)/sizeof(mmCP_RB_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3046, &mmCP_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_LO)/sizeof(mmCP_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3047, &mmCP_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_HI)/sizeof(mmCP_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmGC_PRIV_MODE", REG_MMIO, 0x3048, NULL, 0, 0, 0 },
+	{ "mmCP_INT_CNTL", REG_MMIO, 0x3049, &mmCP_INT_CNTL[0], sizeof(mmCP_INT_CNTL)/sizeof(mmCP_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_INT_STATUS", REG_MMIO, 0x304a, &mmCP_INT_STATUS[0], sizeof(mmCP_INT_STATUS)/sizeof(mmCP_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_DEVICE_ID", REG_MMIO, 0x304b, &mmCP_DEVICE_ID[0], sizeof(mmCP_DEVICE_ID)/sizeof(mmCP_DEVICE_ID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE_PRIORITY_CNTS", REG_MMIO, 0x304c, &mmCP_ME0_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_RING_PRIORITY_CNTS", REG_MMIO, 0x304c, &mmCP_RING_PRIORITY_CNTS[0], sizeof(mmCP_RING_PRIORITY_CNTS)/sizeof(mmCP_RING_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE0_PRIORITY", REG_MMIO, 0x304d, &mmCP_ME0_PIPE0_PRIORITY[0], sizeof(mmCP_ME0_PIPE0_PRIORITY)/sizeof(mmCP_ME0_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING0_PRIORITY", REG_MMIO, 0x304d, &mmCP_RING0_PRIORITY[0], sizeof(mmCP_RING0_PRIORITY)/sizeof(mmCP_RING0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE1_PRIORITY", REG_MMIO, 0x304e, &mmCP_ME0_PIPE1_PRIORITY[0], sizeof(mmCP_ME0_PIPE1_PRIORITY)/sizeof(mmCP_ME0_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING1_PRIORITY", REG_MMIO, 0x304e, &mmCP_RING1_PRIORITY[0], sizeof(mmCP_RING1_PRIORITY)/sizeof(mmCP_RING1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE2_PRIORITY", REG_MMIO, 0x304f, &mmCP_ME0_PIPE2_PRIORITY[0], sizeof(mmCP_ME0_PIPE2_PRIORITY)/sizeof(mmCP_ME0_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING2_PRIORITY", REG_MMIO, 0x304f, &mmCP_RING2_PRIORITY[0], sizeof(mmCP_RING2_PRIORITY)/sizeof(mmCP_RING2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ENDIAN_SWAP", REG_MMIO, 0x3050, &mmCP_ENDIAN_SWAP[0], sizeof(mmCP_ENDIAN_SWAP)/sizeof(mmCP_ENDIAN_SWAP[0]), 0, 0 },
+	{ "mmCP_RB_VMID", REG_MMIO, 0x3051, &mmCP_RB_VMID[0], sizeof(mmCP_RB_VMID)/sizeof(mmCP_RB_VMID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE0_VMID", REG_MMIO, 0x3052, &mmCP_ME0_PIPE0_VMID[0], sizeof(mmCP_ME0_PIPE0_VMID)/sizeof(mmCP_ME0_PIPE0_VMID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE1_VMID", REG_MMIO, 0x3053, &mmCP_ME0_PIPE1_VMID[0], sizeof(mmCP_ME0_PIPE1_VMID)/sizeof(mmCP_ME0_PIPE1_VMID[0]), 0, 0 },
+	{ "mmCP_RB_DOORBELL_CONTROL", REG_MMIO, 0x3059, &mmCP_RB_DOORBELL_CONTROL[0], sizeof(mmCP_RB_DOORBELL_CONTROL)/sizeof(mmCP_RB_DOORBELL_CONTROL[0]), 0, 0 },
+	{ "mmCP_RB_DOORBELL_RANGE_LOWER", REG_MMIO, 0x305a, &mmCP_RB_DOORBELL_RANGE_LOWER[0], sizeof(mmCP_RB_DOORBELL_RANGE_LOWER)/sizeof(mmCP_RB_DOORBELL_RANGE_LOWER[0]), 0, 0 },
+	{ "mmCP_RB_DOORBELL_RANGE_UPPER", REG_MMIO, 0x305b, &mmCP_RB_DOORBELL_RANGE_UPPER[0], sizeof(mmCP_RB_DOORBELL_RANGE_UPPER)/sizeof(mmCP_RB_DOORBELL_RANGE_UPPER[0]), 0, 0 },
+	{ "mmCP_MEC_DOORBELL_RANGE_LOWER", REG_MMIO, 0x305c, &mmCP_MEC_DOORBELL_RANGE_LOWER[0], sizeof(mmCP_MEC_DOORBELL_RANGE_LOWER)/sizeof(mmCP_MEC_DOORBELL_RANGE_LOWER[0]), 0, 0 },
+	{ "mmCP_MEC_DOORBELL_RANGE_UPPER", REG_MMIO, 0x305d, &mmCP_MEC_DOORBELL_RANGE_UPPER[0], sizeof(mmCP_MEC_DOORBELL_RANGE_UPPER)/sizeof(mmCP_MEC_DOORBELL_RANGE_UPPER[0]), 0, 0 },
+	{ "mmCP_RB1_BASE", REG_MMIO, 0x3060, &mmCP_RB1_BASE[0], sizeof(mmCP_RB1_BASE)/sizeof(mmCP_RB1_BASE[0]), 0, 0 },
+	{ "mmCP_RB1_CNTL", REG_MMIO, 0x3061, &mmCP_RB1_CNTL[0], sizeof(mmCP_RB1_CNTL)/sizeof(mmCP_RB1_CNTL[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR", REG_MMIO, 0x3062, &mmCP_RB1_RPTR_ADDR[0], sizeof(mmCP_RB1_RPTR_ADDR)/sizeof(mmCP_RB1_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR_HI", REG_MMIO, 0x3063, &mmCP_RB1_RPTR_ADDR_HI[0], sizeof(mmCP_RB1_RPTR_ADDR_HI)/sizeof(mmCP_RB1_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB1_WPTR", REG_MMIO, 0x3064, &mmCP_RB1_WPTR[0], sizeof(mmCP_RB1_WPTR)/sizeof(mmCP_RB1_WPTR[0]), 0, 0 },
+	{ "mmCP_RB2_BASE", REG_MMIO, 0x3065, &mmCP_RB2_BASE[0], sizeof(mmCP_RB2_BASE)/sizeof(mmCP_RB2_BASE[0]), 0, 0 },
+	{ "mmCP_RB2_CNTL", REG_MMIO, 0x3066, &mmCP_RB2_CNTL[0], sizeof(mmCP_RB2_CNTL)/sizeof(mmCP_RB2_CNTL[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR", REG_MMIO, 0x3067, &mmCP_RB2_RPTR_ADDR[0], sizeof(mmCP_RB2_RPTR_ADDR)/sizeof(mmCP_RB2_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR_HI", REG_MMIO, 0x3068, &mmCP_RB2_RPTR_ADDR_HI[0], sizeof(mmCP_RB2_RPTR_ADDR_HI)/sizeof(mmCP_RB2_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB2_WPTR", REG_MMIO, 0x3069, &mmCP_RB2_WPTR[0], sizeof(mmCP_RB2_WPTR)/sizeof(mmCP_RB2_WPTR[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING0", REG_MMIO, 0x306a, &mmCP_INT_CNTL_RING0[0], sizeof(mmCP_INT_CNTL_RING0)/sizeof(mmCP_INT_CNTL_RING0[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING1", REG_MMIO, 0x306b, &mmCP_INT_CNTL_RING1[0], sizeof(mmCP_INT_CNTL_RING1)/sizeof(mmCP_INT_CNTL_RING1[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING2", REG_MMIO, 0x306c, &mmCP_INT_CNTL_RING2[0], sizeof(mmCP_INT_CNTL_RING2)/sizeof(mmCP_INT_CNTL_RING2[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING0", REG_MMIO, 0x306d, &mmCP_INT_STATUS_RING0[0], sizeof(mmCP_INT_STATUS_RING0)/sizeof(mmCP_INT_STATUS_RING0[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING1", REG_MMIO, 0x306e, &mmCP_INT_STATUS_RING1[0], sizeof(mmCP_INT_STATUS_RING1)/sizeof(mmCP_INT_STATUS_RING1[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING2", REG_MMIO, 0x306f, &mmCP_INT_STATUS_RING2[0], sizeof(mmCP_INT_STATUS_RING2)/sizeof(mmCP_INT_STATUS_RING2[0]), 0, 0 },
+	{ "mmCP_PWR_CNTL", REG_MMIO, 0x3078, &mmCP_PWR_CNTL[0], sizeof(mmCP_PWR_CNTL)/sizeof(mmCP_PWR_CNTL[0]), 0, 0 },
+	{ "mmCP_MEM_SLP_CNTL", REG_MMIO, 0x3079, &mmCP_MEM_SLP_CNTL[0], sizeof(mmCP_MEM_SLP_CNTL)/sizeof(mmCP_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE", REG_MMIO, 0x307a, &mmCP_ECC_FIRSTOCCURRENCE[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE)/sizeof(mmCP_ECC_FIRSTOCCURRENCE[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING0", REG_MMIO, 0x307b, &mmCP_ECC_FIRSTOCCURRENCE_RING0[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING1", REG_MMIO, 0x307c, &mmCP_ECC_FIRSTOCCURRENCE_RING1[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING2", REG_MMIO, 0x307d, &mmCP_ECC_FIRSTOCCURRENCE_RING2[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2[0]), 0, 0 },
+	{ "mmGB_EDC_MODE", REG_MMIO, 0x307e, &mmGB_EDC_MODE[0], sizeof(mmGB_EDC_MODE)/sizeof(mmGB_EDC_MODE[0]), 0, 0 },
+	{ "mmCP_CPF_DEBUG", REG_MMIO, 0x3080, NULL, 0, 0, 0 },
+	{ "mmCP_PQ_WPTR_POLL_CNTL", REG_MMIO, 0x3083, &mmCP_PQ_WPTR_POLL_CNTL[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL)/sizeof(mmCP_PQ_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_PQ_WPTR_POLL_CNTL1", REG_MMIO, 0x3084, &mmCP_PQ_WPTR_POLL_CNTL1[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL1)/sizeof(mmCP_PQ_WPTR_POLL_CNTL1[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_INT_CNTL", REG_MMIO, 0x3085, &mmCP_ME1_PIPE0_INT_CNTL[0], sizeof(mmCP_ME1_PIPE0_INT_CNTL)/sizeof(mmCP_ME1_PIPE0_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_INT_CNTL", REG_MMIO, 0x3086, &mmCP_ME1_PIPE1_INT_CNTL[0], sizeof(mmCP_ME1_PIPE1_INT_CNTL)/sizeof(mmCP_ME1_PIPE1_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_INT_CNTL", REG_MMIO, 0x3087, &mmCP_ME1_PIPE2_INT_CNTL[0], sizeof(mmCP_ME1_PIPE2_INT_CNTL)/sizeof(mmCP_ME1_PIPE2_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_INT_CNTL", REG_MMIO, 0x3088, &mmCP_ME1_PIPE3_INT_CNTL[0], sizeof(mmCP_ME1_PIPE3_INT_CNTL)/sizeof(mmCP_ME1_PIPE3_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_INT_CNTL", REG_MMIO, 0x3089, &mmCP_ME2_PIPE0_INT_CNTL[0], sizeof(mmCP_ME2_PIPE0_INT_CNTL)/sizeof(mmCP_ME2_PIPE0_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_INT_CNTL", REG_MMIO, 0x308a, &mmCP_ME2_PIPE1_INT_CNTL[0], sizeof(mmCP_ME2_PIPE1_INT_CNTL)/sizeof(mmCP_ME2_PIPE1_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_INT_CNTL", REG_MMIO, 0x308b, &mmCP_ME2_PIPE2_INT_CNTL[0], sizeof(mmCP_ME2_PIPE2_INT_CNTL)/sizeof(mmCP_ME2_PIPE2_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_INT_CNTL", REG_MMIO, 0x308c, &mmCP_ME2_PIPE3_INT_CNTL[0], sizeof(mmCP_ME2_PIPE3_INT_CNTL)/sizeof(mmCP_ME2_PIPE3_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_INT_STATUS", REG_MMIO, 0x308d, &mmCP_ME1_PIPE0_INT_STATUS[0], sizeof(mmCP_ME1_PIPE0_INT_STATUS)/sizeof(mmCP_ME1_PIPE0_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_INT_STATUS", REG_MMIO, 0x308e, &mmCP_ME1_PIPE1_INT_STATUS[0], sizeof(mmCP_ME1_PIPE1_INT_STATUS)/sizeof(mmCP_ME1_PIPE1_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_INT_STATUS", REG_MMIO, 0x308f, &mmCP_ME1_PIPE2_INT_STATUS[0], sizeof(mmCP_ME1_PIPE2_INT_STATUS)/sizeof(mmCP_ME1_PIPE2_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_INT_STATUS", REG_MMIO, 0x3090, &mmCP_ME1_PIPE3_INT_STATUS[0], sizeof(mmCP_ME1_PIPE3_INT_STATUS)/sizeof(mmCP_ME1_PIPE3_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_INT_STATUS", REG_MMIO, 0x3091, &mmCP_ME2_PIPE0_INT_STATUS[0], sizeof(mmCP_ME2_PIPE0_INT_STATUS)/sizeof(mmCP_ME2_PIPE0_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_INT_STATUS", REG_MMIO, 0x3092, &mmCP_ME2_PIPE1_INT_STATUS[0], sizeof(mmCP_ME2_PIPE1_INT_STATUS)/sizeof(mmCP_ME2_PIPE1_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_INT_STATUS", REG_MMIO, 0x3093, &mmCP_ME2_PIPE2_INT_STATUS[0], sizeof(mmCP_ME2_PIPE2_INT_STATUS)/sizeof(mmCP_ME2_PIPE2_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_INT_STATUS", REG_MMIO, 0x3094, &mmCP_ME2_PIPE3_INT_STATUS[0], sizeof(mmCP_ME2_PIPE3_INT_STATUS)/sizeof(mmCP_ME2_PIPE3_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_INT_STAT_DEBUG", REG_MMIO, 0x3095, &mmCP_ME1_INT_STAT_DEBUG[0], sizeof(mmCP_ME1_INT_STAT_DEBUG)/sizeof(mmCP_ME1_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCP_ME2_INT_STAT_DEBUG", REG_MMIO, 0x3096, &mmCP_ME2_INT_STAT_DEBUG[0], sizeof(mmCP_ME2_INT_STAT_DEBUG)/sizeof(mmCP_ME2_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCC_GC_EDC_CONFIG", REG_MMIO, 0x3098, &mmCC_GC_EDC_CONFIG[0], sizeof(mmCC_GC_EDC_CONFIG)/sizeof(mmCC_GC_EDC_CONFIG[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE_PRIORITY_CNTS", REG_MMIO, 0x3099, &mmCP_ME1_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_PRIORITY", REG_MMIO, 0x309a, &mmCP_ME1_PIPE0_PRIORITY[0], sizeof(mmCP_ME1_PIPE0_PRIORITY)/sizeof(mmCP_ME1_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_PRIORITY", REG_MMIO, 0x309b, &mmCP_ME1_PIPE1_PRIORITY[0], sizeof(mmCP_ME1_PIPE1_PRIORITY)/sizeof(mmCP_ME1_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_PRIORITY", REG_MMIO, 0x309c, &mmCP_ME1_PIPE2_PRIORITY[0], sizeof(mmCP_ME1_PIPE2_PRIORITY)/sizeof(mmCP_ME1_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_PRIORITY", REG_MMIO, 0x309d, &mmCP_ME1_PIPE3_PRIORITY[0], sizeof(mmCP_ME1_PIPE3_PRIORITY)/sizeof(mmCP_ME1_PIPE3_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE_PRIORITY_CNTS", REG_MMIO, 0x309e, &mmCP_ME2_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_PRIORITY", REG_MMIO, 0x309f, &mmCP_ME2_PIPE0_PRIORITY[0], sizeof(mmCP_ME2_PIPE0_PRIORITY)/sizeof(mmCP_ME2_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_PRIORITY", REG_MMIO, 0x30a0, &mmCP_ME2_PIPE1_PRIORITY[0], sizeof(mmCP_ME2_PIPE1_PRIORITY)/sizeof(mmCP_ME2_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_PRIORITY", REG_MMIO, 0x30a1, &mmCP_ME2_PIPE2_PRIORITY[0], sizeof(mmCP_ME2_PIPE2_PRIORITY)/sizeof(mmCP_ME2_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_PRIORITY", REG_MMIO, 0x30a2, &mmCP_ME2_PIPE3_PRIORITY[0], sizeof(mmCP_ME2_PIPE3_PRIORITY)/sizeof(mmCP_ME2_PIPE3_PRIORITY[0]), 0, 0 },
+	{ "mmCP_CE_PRGRM_CNTR_START", REG_MMIO, 0x30a3, &mmCP_CE_PRGRM_CNTR_START[0], sizeof(mmCP_CE_PRGRM_CNTR_START)/sizeof(mmCP_CE_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_PFP_PRGRM_CNTR_START", REG_MMIO, 0x30a4, &mmCP_PFP_PRGRM_CNTR_START[0], sizeof(mmCP_PFP_PRGRM_CNTR_START)/sizeof(mmCP_PFP_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_ME_PRGRM_CNTR_START", REG_MMIO, 0x30a5, &mmCP_ME_PRGRM_CNTR_START[0], sizeof(mmCP_ME_PRGRM_CNTR_START)/sizeof(mmCP_ME_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_MEC1_PRGRM_CNTR_START", REG_MMIO, 0x30a6, &mmCP_MEC1_PRGRM_CNTR_START[0], sizeof(mmCP_MEC1_PRGRM_CNTR_START)/sizeof(mmCP_MEC1_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_MEC2_PRGRM_CNTR_START", REG_MMIO, 0x30a7, &mmCP_MEC2_PRGRM_CNTR_START[0], sizeof(mmCP_MEC2_PRGRM_CNTR_START)/sizeof(mmCP_MEC2_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_CE_INTR_ROUTINE_START", REG_MMIO, 0x30a8, &mmCP_CE_INTR_ROUTINE_START[0], sizeof(mmCP_CE_INTR_ROUTINE_START)/sizeof(mmCP_CE_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_PFP_INTR_ROUTINE_START", REG_MMIO, 0x30a9, &mmCP_PFP_INTR_ROUTINE_START[0], sizeof(mmCP_PFP_INTR_ROUTINE_START)/sizeof(mmCP_PFP_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_ME_INTR_ROUTINE_START", REG_MMIO, 0x30aa, &mmCP_ME_INTR_ROUTINE_START[0], sizeof(mmCP_ME_INTR_ROUTINE_START)/sizeof(mmCP_ME_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_MEC1_INTR_ROUTINE_START", REG_MMIO, 0x30ab, &mmCP_MEC1_INTR_ROUTINE_START[0], sizeof(mmCP_MEC1_INTR_ROUTINE_START)/sizeof(mmCP_MEC1_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_MEC2_INTR_ROUTINE_START", REG_MMIO, 0x30ac, &mmCP_MEC2_INTR_ROUTINE_START[0], sizeof(mmCP_MEC2_INTR_ROUTINE_START)/sizeof(mmCP_MEC2_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_CONTEXT_CNTL", REG_MMIO, 0x30ad, &mmCP_CONTEXT_CNTL[0], sizeof(mmCP_CONTEXT_CNTL)/sizeof(mmCP_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmCP_MAX_CONTEXT", REG_MMIO, 0x30ae, &mmCP_MAX_CONTEXT[0], sizeof(mmCP_MAX_CONTEXT)/sizeof(mmCP_MAX_CONTEXT[0]), 0, 0 },
+	{ "mmCP_IQ_WAIT_TIME1", REG_MMIO, 0x30af, &mmCP_IQ_WAIT_TIME1[0], sizeof(mmCP_IQ_WAIT_TIME1)/sizeof(mmCP_IQ_WAIT_TIME1[0]), 0, 0 },
+	{ "mmCP_IQ_WAIT_TIME2", REG_MMIO, 0x30b0, &mmCP_IQ_WAIT_TIME2[0], sizeof(mmCP_IQ_WAIT_TIME2)/sizeof(mmCP_IQ_WAIT_TIME2[0]), 0, 0 },
+	{ "mmCP_RB0_BASE_HI", REG_MMIO, 0x30b1, &mmCP_RB0_BASE_HI[0], sizeof(mmCP_RB0_BASE_HI)/sizeof(mmCP_RB0_BASE_HI[0]), 0, 0 },
+	{ "mmCP_RB1_BASE_HI", REG_MMIO, 0x30b2, &mmCP_RB1_BASE_HI[0], sizeof(mmCP_RB1_BASE_HI)/sizeof(mmCP_RB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_VMID_RESET", REG_MMIO, 0x30b3, &mmCP_VMID_RESET[0], sizeof(mmCP_VMID_RESET)/sizeof(mmCP_VMID_RESET[0]), 0, 0 },
+	{ "mmCPC_INT_CNTL", REG_MMIO, 0x30b4, &mmCPC_INT_CNTL[0], sizeof(mmCPC_INT_CNTL)/sizeof(mmCPC_INT_CNTL[0]), 0, 0 },
+	{ "mmCPC_INT_STATUS", REG_MMIO, 0x30b5, &mmCPC_INT_STATUS[0], sizeof(mmCPC_INT_STATUS)/sizeof(mmCPC_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_VMID_PREEMPT", REG_MMIO, 0x30b6, &mmCP_VMID_PREEMPT[0], sizeof(mmCP_VMID_PREEMPT)/sizeof(mmCP_VMID_PREEMPT[0]), 0, 0 },
+	{ "mmCPC_INT_CNTX_ID", REG_MMIO, 0x30b7, &mmCPC_INT_CNTX_ID[0], sizeof(mmCPC_INT_CNTX_ID)/sizeof(mmCPC_INT_CNTX_ID[0]), 0, 0 },
+	{ "mmCP_PQ_STATUS", REG_MMIO, 0x30b8, &mmCP_PQ_STATUS[0], sizeof(mmCP_PQ_STATUS)/sizeof(mmCP_PQ_STATUS[0]), 0, 0 },
+	{ "mmCP_CPC_IC_BASE_LO", REG_MMIO, 0x30b9, &mmCP_CPC_IC_BASE_LO[0], sizeof(mmCP_CPC_IC_BASE_LO)/sizeof(mmCP_CPC_IC_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CPC_IC_BASE_HI", REG_MMIO, 0x30ba, &mmCP_CPC_IC_BASE_HI[0], sizeof(mmCP_CPC_IC_BASE_HI)/sizeof(mmCP_CPC_IC_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CPC_IC_BASE_CNTL", REG_MMIO, 0x30bb, &mmCP_CPC_IC_BASE_CNTL[0], sizeof(mmCP_CPC_IC_BASE_CNTL)/sizeof(mmCP_CPC_IC_BASE_CNTL[0]), 0, 0 },
+	{ "mmCP_CPC_IC_OP_CNTL", REG_MMIO, 0x30bc, &mmCP_CPC_IC_OP_CNTL[0], sizeof(mmCP_CPC_IC_OP_CNTL)/sizeof(mmCP_CPC_IC_OP_CNTL[0]), 0, 0 },
+	{ "mmCP_MEC1_F32_INT_DIS", REG_MMIO, 0x30bd, &mmCP_MEC1_F32_INT_DIS[0], sizeof(mmCP_MEC1_F32_INT_DIS)/sizeof(mmCP_MEC1_F32_INT_DIS[0]), 0, 0 },
+	{ "mmCP_MEC2_F32_INT_DIS", REG_MMIO, 0x30be, &mmCP_MEC2_F32_INT_DIS[0], sizeof(mmCP_MEC2_F32_INT_DIS)/sizeof(mmCP_MEC2_F32_INT_DIS[0]), 0, 0 },
+	{ "mmCP_VMID_STATUS", REG_MMIO, 0x30bf, &mmCP_VMID_STATUS[0], sizeof(mmCP_VMID_STATUS)/sizeof(mmCP_VMID_STATUS[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT4_7", REG_SMC, 0x31, &ixDIDT_DB_WEIGHT4_7[0], sizeof(ixDIDT_DB_WEIGHT4_7)/sizeof(ixDIDT_DB_WEIGHT4_7[0]), 0, 0 },
+	{ "mmCPF_EDC_TAG_CNT", REG_MMIO, 0x3188, NULL, 0, 0, 0 },
+	{ "mmCPF_EDC_ROQ_CNT", REG_MMIO, 0x3189, NULL, 0, 0, 0 },
+	{ "mmCPF_EDC_ATC_CNT", REG_MMIO, 0x318a, NULL, 0, 0, 0 },
+	{ "mmCPG_EDC_TAG_CNT", REG_MMIO, 0x318b, NULL, 0, 0, 0 },
+	{ "mmCPG_EDC_ATC_CNT", REG_MMIO, 0x318c, NULL, 0, 0, 0 },
+	{ "mmCPG_EDC_DMA_CNT", REG_MMIO, 0x318d, NULL, 0, 0, 0 },
+	{ "mmCPC_EDC_SCRATCH_CNT", REG_MMIO, 0x318e, NULL, 0, 0, 0 },
+	{ "mmCPC_EDC_UCODE_CNT", REG_MMIO, 0x318f, NULL, 0, 0, 0 },
+	{ "mmCPC_EDC_ATC_CNT", REG_MMIO, 0x3190, NULL, 0, 0, 0 },
+	{ "mmDC_EDC_STATE_CNT", REG_MMIO, 0x3191, NULL, 0, 0, 0 },
+	{ "mmDC_EDC_CSINVOC_CNT", REG_MMIO, 0x3192, NULL, 0, 0, 0 },
+	{ "mmDC_EDC_RESTORE_CNT", REG_MMIO, 0x3193, NULL, 0, 0, 0 },
+	{ "mmSPI_ARB_PRIORITY", REG_MMIO, 0x31c0, &mmSPI_ARB_PRIORITY[0], sizeof(mmSPI_ARB_PRIORITY)/sizeof(mmSPI_ARB_PRIORITY[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_0", REG_MMIO, 0x31c1, &mmSPI_ARB_CYCLES_0[0], sizeof(mmSPI_ARB_CYCLES_0)/sizeof(mmSPI_ARB_CYCLES_0[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_1", REG_MMIO, 0x31c2, &mmSPI_ARB_CYCLES_1[0], sizeof(mmSPI_ARB_CYCLES_1)/sizeof(mmSPI_ARB_CYCLES_1[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_GFX", REG_MMIO, 0x31c3, &mmSPI_CDBG_SYS_GFX[0], sizeof(mmSPI_CDBG_SYS_GFX)/sizeof(mmSPI_CDBG_SYS_GFX[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_HP3D", REG_MMIO, 0x31c4, &mmSPI_CDBG_SYS_HP3D[0], sizeof(mmSPI_CDBG_SYS_HP3D)/sizeof(mmSPI_CDBG_SYS_HP3D[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_CS0", REG_MMIO, 0x31c5, &mmSPI_CDBG_SYS_CS0[0], sizeof(mmSPI_CDBG_SYS_CS0)/sizeof(mmSPI_CDBG_SYS_CS0[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_CS1", REG_MMIO, 0x31c6, &mmSPI_CDBG_SYS_CS1[0], sizeof(mmSPI_CDBG_SYS_CS1)/sizeof(mmSPI_CDBG_SYS_CS1[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_GFX", REG_MMIO, 0x31c7, &mmSPI_WCL_PIPE_PERCENT_GFX[0], sizeof(mmSPI_WCL_PIPE_PERCENT_GFX)/sizeof(mmSPI_WCL_PIPE_PERCENT_GFX[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_HP3D", REG_MMIO, 0x31c8, &mmSPI_WCL_PIPE_PERCENT_HP3D[0], sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D)/sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS0", REG_MMIO, 0x31c9, &mmSPI_WCL_PIPE_PERCENT_CS0[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS0)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS0[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS1", REG_MMIO, 0x31ca, &mmSPI_WCL_PIPE_PERCENT_CS1[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS1)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS1[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS2", REG_MMIO, 0x31cb, &mmSPI_WCL_PIPE_PERCENT_CS2[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS2)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS2[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS3", REG_MMIO, 0x31cc, &mmSPI_WCL_PIPE_PERCENT_CS3[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS3)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS3[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS4", REG_MMIO, 0x31cd, &mmSPI_WCL_PIPE_PERCENT_CS4[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS4)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS4[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS5", REG_MMIO, 0x31ce, &mmSPI_WCL_PIPE_PERCENT_CS5[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS5)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS5[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS6", REG_MMIO, 0x31cf, &mmSPI_WCL_PIPE_PERCENT_CS6[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS6)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS6[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS7", REG_MMIO, 0x31d0, &mmSPI_WCL_PIPE_PERCENT_CS7[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS7)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS7[0]), 0, 0 },
+	{ "mmSPI_GDBG_WAVE_CNTL", REG_MMIO, 0x31d1, &mmSPI_GDBG_WAVE_CNTL[0], sizeof(mmSPI_GDBG_WAVE_CNTL)/sizeof(mmSPI_GDBG_WAVE_CNTL[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_CONFIG", REG_MMIO, 0x31d2, &mmSPI_GDBG_TRAP_CONFIG[0], sizeof(mmSPI_GDBG_TRAP_CONFIG)/sizeof(mmSPI_GDBG_TRAP_CONFIG[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_MASK", REG_MMIO, 0x31d3, &mmSPI_GDBG_TRAP_MASK[0], sizeof(mmSPI_GDBG_TRAP_MASK)/sizeof(mmSPI_GDBG_TRAP_MASK[0]), 0, 0 },
+	{ "mmSPI_GDBG_TBA_LO", REG_MMIO, 0x31d4, &mmSPI_GDBG_TBA_LO[0], sizeof(mmSPI_GDBG_TBA_LO)/sizeof(mmSPI_GDBG_TBA_LO[0]), 0, 0 },
+	{ "mmSPI_GDBG_TBA_HI", REG_MMIO, 0x31d5, &mmSPI_GDBG_TBA_HI[0], sizeof(mmSPI_GDBG_TBA_HI)/sizeof(mmSPI_GDBG_TBA_HI[0]), 0, 0 },
+	{ "mmSPI_GDBG_TMA_LO", REG_MMIO, 0x31d6, &mmSPI_GDBG_TMA_LO[0], sizeof(mmSPI_GDBG_TMA_LO)/sizeof(mmSPI_GDBG_TMA_LO[0]), 0, 0 },
+	{ "mmSPI_GDBG_TMA_HI", REG_MMIO, 0x31d7, &mmSPI_GDBG_TMA_HI[0], sizeof(mmSPI_GDBG_TMA_HI)/sizeof(mmSPI_GDBG_TMA_HI[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_DATA0", REG_MMIO, 0x31d8, &mmSPI_GDBG_TRAP_DATA0[0], sizeof(mmSPI_GDBG_TRAP_DATA0)/sizeof(mmSPI_GDBG_TRAP_DATA0[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_DATA1", REG_MMIO, 0x31d9, &mmSPI_GDBG_TRAP_DATA1[0], sizeof(mmSPI_GDBG_TRAP_DATA1)/sizeof(mmSPI_GDBG_TRAP_DATA1[0]), 0, 0 },
+	{ "mmSPI_RESET_DEBUG", REG_MMIO, 0x31da, &mmSPI_RESET_DEBUG[0], sizeof(mmSPI_RESET_DEBUG)/sizeof(mmSPI_RESET_DEBUG[0]), 0, 0 },
+	{ "mmSPI_COMPUTE_QUEUE_RESET", REG_MMIO, 0x31db, &mmSPI_COMPUTE_QUEUE_RESET[0], sizeof(mmSPI_COMPUTE_QUEUE_RESET)/sizeof(mmSPI_COMPUTE_QUEUE_RESET[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_0", REG_MMIO, 0x31dc, &mmSPI_RESOURCE_RESERVE_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_CU_0[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_1", REG_MMIO, 0x31dd, &mmSPI_RESOURCE_RESERVE_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_CU_1[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_2", REG_MMIO, 0x31de, &mmSPI_RESOURCE_RESERVE_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_CU_2[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_3", REG_MMIO, 0x31df, &mmSPI_RESOURCE_RESERVE_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_CU_3[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_4", REG_MMIO, 0x31e0, &mmSPI_RESOURCE_RESERVE_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_CU_4[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_5", REG_MMIO, 0x31e1, &mmSPI_RESOURCE_RESERVE_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_CU_5[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_6", REG_MMIO, 0x31e2, &mmSPI_RESOURCE_RESERVE_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_CU_6[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_7", REG_MMIO, 0x31e3, &mmSPI_RESOURCE_RESERVE_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_CU_7[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_8", REG_MMIO, 0x31e4, &mmSPI_RESOURCE_RESERVE_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_CU_8[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_9", REG_MMIO, 0x31e5, &mmSPI_RESOURCE_RESERVE_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_CU_9[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_0", REG_MMIO, 0x31e6, &mmSPI_RESOURCE_RESERVE_EN_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_1", REG_MMIO, 0x31e7, &mmSPI_RESOURCE_RESERVE_EN_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_2", REG_MMIO, 0x31e8, &mmSPI_RESOURCE_RESERVE_EN_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_3", REG_MMIO, 0x31e9, &mmSPI_RESOURCE_RESERVE_EN_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_4", REG_MMIO, 0x31ea, &mmSPI_RESOURCE_RESERVE_EN_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_5", REG_MMIO, 0x31eb, &mmSPI_RESOURCE_RESERVE_EN_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_6", REG_MMIO, 0x31ec, &mmSPI_RESOURCE_RESERVE_EN_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_7", REG_MMIO, 0x31ed, &mmSPI_RESOURCE_RESERVE_EN_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_8", REG_MMIO, 0x31ee, &mmSPI_RESOURCE_RESERVE_EN_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_9", REG_MMIO, 0x31ef, &mmSPI_RESOURCE_RESERVE_EN_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_10", REG_MMIO, 0x31f0, &mmSPI_RESOURCE_RESERVE_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_CU_10[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_11", REG_MMIO, 0x31f1, &mmSPI_RESOURCE_RESERVE_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_CU_11[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_10", REG_MMIO, 0x31f2, &mmSPI_RESOURCE_RESERVE_EN_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_11", REG_MMIO, 0x31f3, &mmSPI_RESOURCE_RESERVE_EN_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_12", REG_MMIO, 0x31f4, &mmSPI_RESOURCE_RESERVE_CU_12[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_12)/sizeof(mmSPI_RESOURCE_RESERVE_CU_12[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_13", REG_MMIO, 0x31f5, &mmSPI_RESOURCE_RESERVE_CU_13[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_13)/sizeof(mmSPI_RESOURCE_RESERVE_CU_13[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_14", REG_MMIO, 0x31f6, &mmSPI_RESOURCE_RESERVE_CU_14[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_14)/sizeof(mmSPI_RESOURCE_RESERVE_CU_14[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_15", REG_MMIO, 0x31f7, &mmSPI_RESOURCE_RESERVE_CU_15[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_15)/sizeof(mmSPI_RESOURCE_RESERVE_CU_15[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_12", REG_MMIO, 0x31f8, &mmSPI_RESOURCE_RESERVE_EN_CU_12[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_12)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_12[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_13", REG_MMIO, 0x31f9, &mmSPI_RESOURCE_RESERVE_EN_CU_13[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_13)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_13[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_14", REG_MMIO, 0x31fa, &mmSPI_RESOURCE_RESERVE_EN_CU_14[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_14)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_14[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_15", REG_MMIO, 0x31fb, &mmSPI_RESOURCE_RESERVE_EN_CU_15[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_15)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_15[0]), 0, 0 },
+	{ "mmSPI_COMPUTE_WF_CTX_SAVE", REG_MMIO, 0x31fc, &mmSPI_COMPUTE_WF_CTX_SAVE[0], sizeof(mmSPI_COMPUTE_WF_CTX_SAVE)/sizeof(mmSPI_COMPUTE_WF_CTX_SAVE[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT8_11", REG_SMC, 0x32, &ixDIDT_DB_WEIGHT8_11[0], sizeof(ixDIDT_DB_WEIGHT8_11)/sizeof(ixDIDT_DB_WEIGHT8_11[0]), 0, 0 },
+	{ "mmCP_HPD_ROQ_OFFSETS", REG_MMIO, 0x3240, &mmCP_HPD_ROQ_OFFSETS[0], sizeof(mmCP_HPD_ROQ_OFFSETS)/sizeof(mmCP_HPD_ROQ_OFFSETS[0]), 0, 0 },
+	{ "mmCP_HPD_STATUS0", REG_MMIO, 0x3241, &mmCP_HPD_STATUS0[0], sizeof(mmCP_HPD_STATUS0)/sizeof(mmCP_HPD_STATUS0[0]), 0, 0 },
+	{ "mmCP_MQD_BASE_ADDR", REG_MMIO, 0x3245, &mmCP_MQD_BASE_ADDR[0], sizeof(mmCP_MQD_BASE_ADDR)/sizeof(mmCP_MQD_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_MQD_BASE_ADDR_HI", REG_MMIO, 0x3246, &mmCP_MQD_BASE_ADDR_HI[0], sizeof(mmCP_MQD_BASE_ADDR_HI)/sizeof(mmCP_MQD_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_ACTIVE", REG_MMIO, 0x3247, &mmCP_HQD_ACTIVE[0], sizeof(mmCP_HQD_ACTIVE)/sizeof(mmCP_HQD_ACTIVE[0]), 0, 0 },
+	{ "mmCP_HQD_VMID", REG_MMIO, 0x3248, &mmCP_HQD_VMID[0], sizeof(mmCP_HQD_VMID)/sizeof(mmCP_HQD_VMID[0]), 0, 0 },
+	{ "mmCP_HQD_PERSISTENT_STATE", REG_MMIO, 0x3249, &mmCP_HQD_PERSISTENT_STATE[0], sizeof(mmCP_HQD_PERSISTENT_STATE)/sizeof(mmCP_HQD_PERSISTENT_STATE[0]), 0, 0 },
+	{ "mmCP_HQD_PIPE_PRIORITY", REG_MMIO, 0x324a, &mmCP_HQD_PIPE_PRIORITY[0], sizeof(mmCP_HQD_PIPE_PRIORITY)/sizeof(mmCP_HQD_PIPE_PRIORITY[0]), 0, 0 },
+	{ "mmCP_HQD_QUEUE_PRIORITY", REG_MMIO, 0x324b, &mmCP_HQD_QUEUE_PRIORITY[0], sizeof(mmCP_HQD_QUEUE_PRIORITY)/sizeof(mmCP_HQD_QUEUE_PRIORITY[0]), 0, 0 },
+	{ "mmCP_HQD_QUANTUM", REG_MMIO, 0x324c, &mmCP_HQD_QUANTUM[0], sizeof(mmCP_HQD_QUANTUM)/sizeof(mmCP_HQD_QUANTUM[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_BASE", REG_MMIO, 0x324d, &mmCP_HQD_PQ_BASE[0], sizeof(mmCP_HQD_PQ_BASE)/sizeof(mmCP_HQD_PQ_BASE[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_BASE_HI", REG_MMIO, 0x324e, &mmCP_HQD_PQ_BASE_HI[0], sizeof(mmCP_HQD_PQ_BASE_HI)/sizeof(mmCP_HQD_PQ_BASE_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR", REG_MMIO, 0x324f, &mmCP_HQD_PQ_RPTR[0], sizeof(mmCP_HQD_PQ_RPTR)/sizeof(mmCP_HQD_PQ_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR", REG_MMIO, 0x3250, &mmCP_HQD_PQ_RPTR_REPORT_ADDR[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI", REG_MMIO, 0x3251, &mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR", REG_MMIO, 0x3252, &mmCP_HQD_PQ_WPTR_POLL_ADDR[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3253, &mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_DOORBELL_CONTROL", REG_MMIO, 0x3254, &mmCP_HQD_PQ_DOORBELL_CONTROL[0], sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL)/sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR", REG_MMIO, 0x3255, &mmCP_HQD_PQ_WPTR[0], sizeof(mmCP_HQD_PQ_WPTR)/sizeof(mmCP_HQD_PQ_WPTR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_CONTROL", REG_MMIO, 0x3256, &mmCP_HQD_PQ_CONTROL[0], sizeof(mmCP_HQD_PQ_CONTROL)/sizeof(mmCP_HQD_PQ_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_IB_BASE_ADDR", REG_MMIO, 0x3257, &mmCP_HQD_IB_BASE_ADDR[0], sizeof(mmCP_HQD_IB_BASE_ADDR)/sizeof(mmCP_HQD_IB_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_IB_BASE_ADDR_HI", REG_MMIO, 0x3258, &mmCP_HQD_IB_BASE_ADDR_HI[0], sizeof(mmCP_HQD_IB_BASE_ADDR_HI)/sizeof(mmCP_HQD_IB_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_IB_RPTR", REG_MMIO, 0x3259, &mmCP_HQD_IB_RPTR[0], sizeof(mmCP_HQD_IB_RPTR)/sizeof(mmCP_HQD_IB_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_IB_CONTROL", REG_MMIO, 0x325a, &mmCP_HQD_IB_CONTROL[0], sizeof(mmCP_HQD_IB_CONTROL)/sizeof(mmCP_HQD_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_IQ_TIMER", REG_MMIO, 0x325b, &mmCP_HQD_IQ_TIMER[0], sizeof(mmCP_HQD_IQ_TIMER)/sizeof(mmCP_HQD_IQ_TIMER[0]), 0, 0 },
+	{ "mmCP_HQD_IQ_RPTR", REG_MMIO, 0x325c, &mmCP_HQD_IQ_RPTR[0], sizeof(mmCP_HQD_IQ_RPTR)/sizeof(mmCP_HQD_IQ_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_DEQUEUE_REQUEST", REG_MMIO, 0x325d, &mmCP_HQD_DEQUEUE_REQUEST[0], sizeof(mmCP_HQD_DEQUEUE_REQUEST)/sizeof(mmCP_HQD_DEQUEUE_REQUEST[0]), 0, 0 },
+	{ "mmCP_HQD_DMA_OFFLOAD", REG_MMIO, 0x325e, &mmCP_HQD_DMA_OFFLOAD[0], sizeof(mmCP_HQD_DMA_OFFLOAD)/sizeof(mmCP_HQD_DMA_OFFLOAD[0]), 0, 0 },
+	{ "mmCP_HQD_OFFLOAD", REG_MMIO, 0x325e, &mmCP_HQD_OFFLOAD[0], sizeof(mmCP_HQD_OFFLOAD)/sizeof(mmCP_HQD_OFFLOAD[0]), 0, 0 },
+	{ "mmCP_HQD_SEMA_CMD", REG_MMIO, 0x325f, &mmCP_HQD_SEMA_CMD[0], sizeof(mmCP_HQD_SEMA_CMD)/sizeof(mmCP_HQD_SEMA_CMD[0]), 0, 0 },
+	{ "mmCP_HQD_MSG_TYPE", REG_MMIO, 0x3260, &mmCP_HQD_MSG_TYPE[0], sizeof(mmCP_HQD_MSG_TYPE)/sizeof(mmCP_HQD_MSG_TYPE[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC0_PREOP_LO", REG_MMIO, 0x3261, &mmCP_HQD_ATOMIC0_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC0_PREOP_HI", REG_MMIO, 0x3262, &mmCP_HQD_ATOMIC0_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC1_PREOP_LO", REG_MMIO, 0x3263, &mmCP_HQD_ATOMIC1_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC1_PREOP_HI", REG_MMIO, 0x3264, &mmCP_HQD_ATOMIC1_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_SCHEDULER0", REG_MMIO, 0x3265, &mmCP_HQD_HQ_SCHEDULER0[0], sizeof(mmCP_HQD_HQ_SCHEDULER0)/sizeof(mmCP_HQD_HQ_SCHEDULER0[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_STATUS0", REG_MMIO, 0x3265, &mmCP_HQD_HQ_STATUS0[0], sizeof(mmCP_HQD_HQ_STATUS0)/sizeof(mmCP_HQD_HQ_STATUS0[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_SCHEDULER1", REG_MMIO, 0x3266, &mmCP_HQD_HQ_SCHEDULER1[0], sizeof(mmCP_HQD_HQ_SCHEDULER1)/sizeof(mmCP_HQD_HQ_SCHEDULER1[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_CONTROL0", REG_MMIO, 0x3266, &mmCP_HQD_HQ_CONTROL0[0], sizeof(mmCP_HQD_HQ_CONTROL0)/sizeof(mmCP_HQD_HQ_CONTROL0[0]), 0, 0 },
+	{ "mmCP_MQD_CONTROL", REG_MMIO, 0x3267, &mmCP_MQD_CONTROL[0], sizeof(mmCP_MQD_CONTROL)/sizeof(mmCP_MQD_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_STATUS1", REG_MMIO, 0x3268, &mmCP_HQD_HQ_STATUS1[0], sizeof(mmCP_HQD_HQ_STATUS1)/sizeof(mmCP_HQD_HQ_STATUS1[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_CONTROL1", REG_MMIO, 0x3269, &mmCP_HQD_HQ_CONTROL1[0], sizeof(mmCP_HQD_HQ_CONTROL1)/sizeof(mmCP_HQD_HQ_CONTROL1[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_BASE_ADDR", REG_MMIO, 0x326a, &mmCP_HQD_EOP_BASE_ADDR[0], sizeof(mmCP_HQD_EOP_BASE_ADDR)/sizeof(mmCP_HQD_EOP_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_BASE_ADDR_HI", REG_MMIO, 0x326b, &mmCP_HQD_EOP_BASE_ADDR_HI[0], sizeof(mmCP_HQD_EOP_BASE_ADDR_HI)/sizeof(mmCP_HQD_EOP_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_CONTROL", REG_MMIO, 0x326c, &mmCP_HQD_EOP_CONTROL[0], sizeof(mmCP_HQD_EOP_CONTROL)/sizeof(mmCP_HQD_EOP_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_RPTR", REG_MMIO, 0x326d, &mmCP_HQD_EOP_RPTR[0], sizeof(mmCP_HQD_EOP_RPTR)/sizeof(mmCP_HQD_EOP_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_WPTR", REG_MMIO, 0x326e, &mmCP_HQD_EOP_WPTR[0], sizeof(mmCP_HQD_EOP_WPTR)/sizeof(mmCP_HQD_EOP_WPTR[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_EVENTS", REG_MMIO, 0x326f, &mmCP_HQD_EOP_EVENTS[0], sizeof(mmCP_HQD_EOP_EVENTS)/sizeof(mmCP_HQD_EOP_EVENTS[0]), 0, 0 },
+	{ "mmCP_HQD_CTX_SAVE_BASE_ADDR_LO", REG_MMIO, 0x3270, &mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[0], sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO)/sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_HQD_CTX_SAVE_BASE_ADDR_HI", REG_MMIO, 0x3271, &mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[0], sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI)/sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_CTX_SAVE_CONTROL", REG_MMIO, 0x3272, &mmCP_HQD_CTX_SAVE_CONTROL[0], sizeof(mmCP_HQD_CTX_SAVE_CONTROL)/sizeof(mmCP_HQD_CTX_SAVE_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_CNTL_STACK_OFFSET", REG_MMIO, 0x3273, &mmCP_HQD_CNTL_STACK_OFFSET[0], sizeof(mmCP_HQD_CNTL_STACK_OFFSET)/sizeof(mmCP_HQD_CNTL_STACK_OFFSET[0]), 0, 0 },
+	{ "mmCP_HQD_CNTL_STACK_SIZE", REG_MMIO, 0x3274, &mmCP_HQD_CNTL_STACK_SIZE[0], sizeof(mmCP_HQD_CNTL_STACK_SIZE)/sizeof(mmCP_HQD_CNTL_STACK_SIZE[0]), 0, 0 },
+	{ "mmCP_HQD_WG_STATE_OFFSET", REG_MMIO, 0x3275, &mmCP_HQD_WG_STATE_OFFSET[0], sizeof(mmCP_HQD_WG_STATE_OFFSET)/sizeof(mmCP_HQD_WG_STATE_OFFSET[0]), 0, 0 },
+	{ "mmCP_HQD_CTX_SAVE_SIZE", REG_MMIO, 0x3276, &mmCP_HQD_CTX_SAVE_SIZE[0], sizeof(mmCP_HQD_CTX_SAVE_SIZE)/sizeof(mmCP_HQD_CTX_SAVE_SIZE[0]), 0, 0 },
+	{ "mmCP_HQD_GDS_RESOURCE_STATE", REG_MMIO, 0x3277, &mmCP_HQD_GDS_RESOURCE_STATE[0], sizeof(mmCP_HQD_GDS_RESOURCE_STATE)/sizeof(mmCP_HQD_GDS_RESOURCE_STATE[0]), 0, 0 },
+	{ "mmCP_HQD_ERROR", REG_MMIO, 0x3278, &mmCP_HQD_ERROR[0], sizeof(mmCP_HQD_ERROR)/sizeof(mmCP_HQD_ERROR[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_WPTR_MEM", REG_MMIO, 0x3279, &mmCP_HQD_EOP_WPTR_MEM[0], sizeof(mmCP_HQD_EOP_WPTR_MEM)/sizeof(mmCP_HQD_EOP_WPTR_MEM[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_DONES", REG_MMIO, 0x327a, &mmCP_HQD_EOP_DONES[0], sizeof(mmCP_HQD_EOP_DONES)/sizeof(mmCP_HQD_EOP_DONES[0]), 0, 0 },
+	{ "mmDIDT_IND_INDEX", REG_MMIO, 0x3280, &mmDIDT_IND_INDEX[0], sizeof(mmDIDT_IND_INDEX)/sizeof(mmDIDT_IND_INDEX[0]), 0, 0 },
+	{ "mmDIDT_IND_DATA", REG_MMIO, 0x3281, &mmDIDT_IND_DATA[0], sizeof(mmDIDT_IND_DATA)/sizeof(mmDIDT_IND_DATA[0]), 0, 0 },
+	{ "mmTCP_WATCH0_ADDR_H", REG_MMIO, 0x32a0, &mmTCP_WATCH0_ADDR_H[0], sizeof(mmTCP_WATCH0_ADDR_H)/sizeof(mmTCP_WATCH0_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH0_ADDR_L", REG_MMIO, 0x32a1, &mmTCP_WATCH0_ADDR_L[0], sizeof(mmTCP_WATCH0_ADDR_L)/sizeof(mmTCP_WATCH0_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH0_CNTL", REG_MMIO, 0x32a2, &mmTCP_WATCH0_CNTL[0], sizeof(mmTCP_WATCH0_CNTL)/sizeof(mmTCP_WATCH0_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH1_ADDR_H", REG_MMIO, 0x32a3, &mmTCP_WATCH1_ADDR_H[0], sizeof(mmTCP_WATCH1_ADDR_H)/sizeof(mmTCP_WATCH1_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH1_ADDR_L", REG_MMIO, 0x32a4, &mmTCP_WATCH1_ADDR_L[0], sizeof(mmTCP_WATCH1_ADDR_L)/sizeof(mmTCP_WATCH1_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH1_CNTL", REG_MMIO, 0x32a5, &mmTCP_WATCH1_CNTL[0], sizeof(mmTCP_WATCH1_CNTL)/sizeof(mmTCP_WATCH1_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH2_ADDR_H", REG_MMIO, 0x32a6, &mmTCP_WATCH2_ADDR_H[0], sizeof(mmTCP_WATCH2_ADDR_H)/sizeof(mmTCP_WATCH2_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH2_ADDR_L", REG_MMIO, 0x32a7, &mmTCP_WATCH2_ADDR_L[0], sizeof(mmTCP_WATCH2_ADDR_L)/sizeof(mmTCP_WATCH2_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH2_CNTL", REG_MMIO, 0x32a8, &mmTCP_WATCH2_CNTL[0], sizeof(mmTCP_WATCH2_CNTL)/sizeof(mmTCP_WATCH2_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH3_ADDR_H", REG_MMIO, 0x32a9, &mmTCP_WATCH3_ADDR_H[0], sizeof(mmTCP_WATCH3_ADDR_H)/sizeof(mmTCP_WATCH3_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH3_ADDR_L", REG_MMIO, 0x32aa, &mmTCP_WATCH3_ADDR_L[0], sizeof(mmTCP_WATCH3_ADDR_L)/sizeof(mmTCP_WATCH3_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH3_CNTL", REG_MMIO, 0x32ab, &mmTCP_WATCH3_CNTL[0], sizeof(mmTCP_WATCH3_CNTL)/sizeof(mmTCP_WATCH3_CNTL[0]), 0, 0 },
+	{ "mmTCP_GATCL1_CNTL", REG_MMIO, 0x32b0, &mmTCP_GATCL1_CNTL[0], sizeof(mmTCP_GATCL1_CNTL)/sizeof(mmTCP_GATCL1_CNTL[0]), 0, 0 },
+	{ "mmTCP_ATC_EDC_GATCL1_CNT", REG_MMIO, 0x32b1, &mmTCP_ATC_EDC_GATCL1_CNT[0], sizeof(mmTCP_ATC_EDC_GATCL1_CNT)/sizeof(mmTCP_ATC_EDC_GATCL1_CNT[0]), 0, 0 },
+	{ "mmTCP_GATCL1_DSM_CNTL", REG_MMIO, 0x32b2, &mmTCP_GATCL1_DSM_CNTL[0], sizeof(mmTCP_GATCL1_DSM_CNTL)/sizeof(mmTCP_GATCL1_DSM_CNTL[0]), 0, 0 },
+	{ "mmTCP_DSM_CNTL", REG_MMIO, 0x32b3, &mmTCP_DSM_CNTL[0], sizeof(mmTCP_DSM_CNTL)/sizeof(mmTCP_DSM_CNTL[0]), 0, 0 },
+	{ "mmTCP_CNTL2", REG_MMIO, 0x32b4, &mmTCP_CNTL2[0], sizeof(mmTCP_CNTL2)/sizeof(mmTCP_CNTL2[0]), 0, 0 },
+	{ "mmGDS_VMID0_BASE", REG_MMIO, 0x3300, &mmGDS_VMID0_BASE[0], sizeof(mmGDS_VMID0_BASE)/sizeof(mmGDS_VMID0_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID0_SIZE", REG_MMIO, 0x3301, &mmGDS_VMID0_SIZE[0], sizeof(mmGDS_VMID0_SIZE)/sizeof(mmGDS_VMID0_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID1_BASE", REG_MMIO, 0x3302, &mmGDS_VMID1_BASE[0], sizeof(mmGDS_VMID1_BASE)/sizeof(mmGDS_VMID1_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID1_SIZE", REG_MMIO, 0x3303, &mmGDS_VMID1_SIZE[0], sizeof(mmGDS_VMID1_SIZE)/sizeof(mmGDS_VMID1_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID2_BASE", REG_MMIO, 0x3304, &mmGDS_VMID2_BASE[0], sizeof(mmGDS_VMID2_BASE)/sizeof(mmGDS_VMID2_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID2_SIZE", REG_MMIO, 0x3305, &mmGDS_VMID2_SIZE[0], sizeof(mmGDS_VMID2_SIZE)/sizeof(mmGDS_VMID2_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID3_BASE", REG_MMIO, 0x3306, &mmGDS_VMID3_BASE[0], sizeof(mmGDS_VMID3_BASE)/sizeof(mmGDS_VMID3_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID3_SIZE", REG_MMIO, 0x3307, &mmGDS_VMID3_SIZE[0], sizeof(mmGDS_VMID3_SIZE)/sizeof(mmGDS_VMID3_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID4_BASE", REG_MMIO, 0x3308, &mmGDS_VMID4_BASE[0], sizeof(mmGDS_VMID4_BASE)/sizeof(mmGDS_VMID4_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID4_SIZE", REG_MMIO, 0x3309, &mmGDS_VMID4_SIZE[0], sizeof(mmGDS_VMID4_SIZE)/sizeof(mmGDS_VMID4_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID5_BASE", REG_MMIO, 0x330a, &mmGDS_VMID5_BASE[0], sizeof(mmGDS_VMID5_BASE)/sizeof(mmGDS_VMID5_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID5_SIZE", REG_MMIO, 0x330b, &mmGDS_VMID5_SIZE[0], sizeof(mmGDS_VMID5_SIZE)/sizeof(mmGDS_VMID5_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID6_BASE", REG_MMIO, 0x330c, &mmGDS_VMID6_BASE[0], sizeof(mmGDS_VMID6_BASE)/sizeof(mmGDS_VMID6_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID6_SIZE", REG_MMIO, 0x330d, &mmGDS_VMID6_SIZE[0], sizeof(mmGDS_VMID6_SIZE)/sizeof(mmGDS_VMID6_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID7_BASE", REG_MMIO, 0x330e, &mmGDS_VMID7_BASE[0], sizeof(mmGDS_VMID7_BASE)/sizeof(mmGDS_VMID7_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID7_SIZE", REG_MMIO, 0x330f, &mmGDS_VMID7_SIZE[0], sizeof(mmGDS_VMID7_SIZE)/sizeof(mmGDS_VMID7_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID8_BASE", REG_MMIO, 0x3310, &mmGDS_VMID8_BASE[0], sizeof(mmGDS_VMID8_BASE)/sizeof(mmGDS_VMID8_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID8_SIZE", REG_MMIO, 0x3311, &mmGDS_VMID8_SIZE[0], sizeof(mmGDS_VMID8_SIZE)/sizeof(mmGDS_VMID8_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID9_BASE", REG_MMIO, 0x3312, &mmGDS_VMID9_BASE[0], sizeof(mmGDS_VMID9_BASE)/sizeof(mmGDS_VMID9_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID9_SIZE", REG_MMIO, 0x3313, &mmGDS_VMID9_SIZE[0], sizeof(mmGDS_VMID9_SIZE)/sizeof(mmGDS_VMID9_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID10_BASE", REG_MMIO, 0x3314, &mmGDS_VMID10_BASE[0], sizeof(mmGDS_VMID10_BASE)/sizeof(mmGDS_VMID10_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID10_SIZE", REG_MMIO, 0x3315, &mmGDS_VMID10_SIZE[0], sizeof(mmGDS_VMID10_SIZE)/sizeof(mmGDS_VMID10_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID11_BASE", REG_MMIO, 0x3316, &mmGDS_VMID11_BASE[0], sizeof(mmGDS_VMID11_BASE)/sizeof(mmGDS_VMID11_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID11_SIZE", REG_MMIO, 0x3317, &mmGDS_VMID11_SIZE[0], sizeof(mmGDS_VMID11_SIZE)/sizeof(mmGDS_VMID11_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID12_BASE", REG_MMIO, 0x3318, &mmGDS_VMID12_BASE[0], sizeof(mmGDS_VMID12_BASE)/sizeof(mmGDS_VMID12_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID12_SIZE", REG_MMIO, 0x3319, &mmGDS_VMID12_SIZE[0], sizeof(mmGDS_VMID12_SIZE)/sizeof(mmGDS_VMID12_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID13_BASE", REG_MMIO, 0x331a, &mmGDS_VMID13_BASE[0], sizeof(mmGDS_VMID13_BASE)/sizeof(mmGDS_VMID13_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID13_SIZE", REG_MMIO, 0x331b, &mmGDS_VMID13_SIZE[0], sizeof(mmGDS_VMID13_SIZE)/sizeof(mmGDS_VMID13_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID14_BASE", REG_MMIO, 0x331c, &mmGDS_VMID14_BASE[0], sizeof(mmGDS_VMID14_BASE)/sizeof(mmGDS_VMID14_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID14_SIZE", REG_MMIO, 0x331d, &mmGDS_VMID14_SIZE[0], sizeof(mmGDS_VMID14_SIZE)/sizeof(mmGDS_VMID14_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID15_BASE", REG_MMIO, 0x331e, &mmGDS_VMID15_BASE[0], sizeof(mmGDS_VMID15_BASE)/sizeof(mmGDS_VMID15_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID15_SIZE", REG_MMIO, 0x331f, &mmGDS_VMID15_SIZE[0], sizeof(mmGDS_VMID15_SIZE)/sizeof(mmGDS_VMID15_SIZE[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID0", REG_MMIO, 0x3320, &mmGDS_GWS_VMID0[0], sizeof(mmGDS_GWS_VMID0)/sizeof(mmGDS_GWS_VMID0[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID1", REG_MMIO, 0x3321, &mmGDS_GWS_VMID1[0], sizeof(mmGDS_GWS_VMID1)/sizeof(mmGDS_GWS_VMID1[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID2", REG_MMIO, 0x3322, &mmGDS_GWS_VMID2[0], sizeof(mmGDS_GWS_VMID2)/sizeof(mmGDS_GWS_VMID2[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID3", REG_MMIO, 0x3323, &mmGDS_GWS_VMID3[0], sizeof(mmGDS_GWS_VMID3)/sizeof(mmGDS_GWS_VMID3[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID4", REG_MMIO, 0x3324, &mmGDS_GWS_VMID4[0], sizeof(mmGDS_GWS_VMID4)/sizeof(mmGDS_GWS_VMID4[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID5", REG_MMIO, 0x3325, &mmGDS_GWS_VMID5[0], sizeof(mmGDS_GWS_VMID5)/sizeof(mmGDS_GWS_VMID5[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID6", REG_MMIO, 0x3326, &mmGDS_GWS_VMID6[0], sizeof(mmGDS_GWS_VMID6)/sizeof(mmGDS_GWS_VMID6[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID7", REG_MMIO, 0x3327, &mmGDS_GWS_VMID7[0], sizeof(mmGDS_GWS_VMID7)/sizeof(mmGDS_GWS_VMID7[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID8", REG_MMIO, 0x3328, &mmGDS_GWS_VMID8[0], sizeof(mmGDS_GWS_VMID8)/sizeof(mmGDS_GWS_VMID8[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID9", REG_MMIO, 0x3329, &mmGDS_GWS_VMID9[0], sizeof(mmGDS_GWS_VMID9)/sizeof(mmGDS_GWS_VMID9[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID10", REG_MMIO, 0x332a, &mmGDS_GWS_VMID10[0], sizeof(mmGDS_GWS_VMID10)/sizeof(mmGDS_GWS_VMID10[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID11", REG_MMIO, 0x332b, &mmGDS_GWS_VMID11[0], sizeof(mmGDS_GWS_VMID11)/sizeof(mmGDS_GWS_VMID11[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID12", REG_MMIO, 0x332c, &mmGDS_GWS_VMID12[0], sizeof(mmGDS_GWS_VMID12)/sizeof(mmGDS_GWS_VMID12[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID13", REG_MMIO, 0x332d, &mmGDS_GWS_VMID13[0], sizeof(mmGDS_GWS_VMID13)/sizeof(mmGDS_GWS_VMID13[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID14", REG_MMIO, 0x332e, &mmGDS_GWS_VMID14[0], sizeof(mmGDS_GWS_VMID14)/sizeof(mmGDS_GWS_VMID14[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID15", REG_MMIO, 0x332f, &mmGDS_GWS_VMID15[0], sizeof(mmGDS_GWS_VMID15)/sizeof(mmGDS_GWS_VMID15[0]), 0, 0 },
+	{ "mmGDS_OA_VMID0", REG_MMIO, 0x3330, &mmGDS_OA_VMID0[0], sizeof(mmGDS_OA_VMID0)/sizeof(mmGDS_OA_VMID0[0]), 0, 0 },
+	{ "mmGDS_OA_VMID1", REG_MMIO, 0x3331, &mmGDS_OA_VMID1[0], sizeof(mmGDS_OA_VMID1)/sizeof(mmGDS_OA_VMID1[0]), 0, 0 },
+	{ "mmGDS_OA_VMID2", REG_MMIO, 0x3332, &mmGDS_OA_VMID2[0], sizeof(mmGDS_OA_VMID2)/sizeof(mmGDS_OA_VMID2[0]), 0, 0 },
+	{ "mmGDS_OA_VMID3", REG_MMIO, 0x3333, &mmGDS_OA_VMID3[0], sizeof(mmGDS_OA_VMID3)/sizeof(mmGDS_OA_VMID3[0]), 0, 0 },
+	{ "mmGDS_OA_VMID4", REG_MMIO, 0x3334, &mmGDS_OA_VMID4[0], sizeof(mmGDS_OA_VMID4)/sizeof(mmGDS_OA_VMID4[0]), 0, 0 },
+	{ "mmGDS_OA_VMID5", REG_MMIO, 0x3335, &mmGDS_OA_VMID5[0], sizeof(mmGDS_OA_VMID5)/sizeof(mmGDS_OA_VMID5[0]), 0, 0 },
+	{ "mmGDS_OA_VMID6", REG_MMIO, 0x3336, &mmGDS_OA_VMID6[0], sizeof(mmGDS_OA_VMID6)/sizeof(mmGDS_OA_VMID6[0]), 0, 0 },
+	{ "mmGDS_OA_VMID7", REG_MMIO, 0x3337, &mmGDS_OA_VMID7[0], sizeof(mmGDS_OA_VMID7)/sizeof(mmGDS_OA_VMID7[0]), 0, 0 },
+	{ "mmGDS_OA_VMID8", REG_MMIO, 0x3338, &mmGDS_OA_VMID8[0], sizeof(mmGDS_OA_VMID8)/sizeof(mmGDS_OA_VMID8[0]), 0, 0 },
+	{ "mmGDS_OA_VMID9", REG_MMIO, 0x3339, &mmGDS_OA_VMID9[0], sizeof(mmGDS_OA_VMID9)/sizeof(mmGDS_OA_VMID9[0]), 0, 0 },
+	{ "mmGDS_OA_VMID10", REG_MMIO, 0x333a, &mmGDS_OA_VMID10[0], sizeof(mmGDS_OA_VMID10)/sizeof(mmGDS_OA_VMID10[0]), 0, 0 },
+	{ "mmGDS_OA_VMID11", REG_MMIO, 0x333b, &mmGDS_OA_VMID11[0], sizeof(mmGDS_OA_VMID11)/sizeof(mmGDS_OA_VMID11[0]), 0, 0 },
+	{ "mmGDS_OA_VMID12", REG_MMIO, 0x333c, &mmGDS_OA_VMID12[0], sizeof(mmGDS_OA_VMID12)/sizeof(mmGDS_OA_VMID12[0]), 0, 0 },
+	{ "mmGDS_OA_VMID13", REG_MMIO, 0x333d, &mmGDS_OA_VMID13[0], sizeof(mmGDS_OA_VMID13)/sizeof(mmGDS_OA_VMID13[0]), 0, 0 },
+	{ "mmGDS_OA_VMID14", REG_MMIO, 0x333e, &mmGDS_OA_VMID14[0], sizeof(mmGDS_OA_VMID14)/sizeof(mmGDS_OA_VMID14[0]), 0, 0 },
+	{ "mmGDS_OA_VMID15", REG_MMIO, 0x333f, &mmGDS_OA_VMID15[0], sizeof(mmGDS_OA_VMID15)/sizeof(mmGDS_OA_VMID15[0]), 0, 0 },
+	{ "mmGDS_GWS_RESET0", REG_MMIO, 0x3344, &mmGDS_GWS_RESET0[0], sizeof(mmGDS_GWS_RESET0)/sizeof(mmGDS_GWS_RESET0[0]), 0, 0 },
+	{ "mmGDS_GWS_RESET1", REG_MMIO, 0x3345, &mmGDS_GWS_RESET1[0], sizeof(mmGDS_GWS_RESET1)/sizeof(mmGDS_GWS_RESET1[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_RESET", REG_MMIO, 0x3346, &mmGDS_GWS_RESOURCE_RESET[0], sizeof(mmGDS_GWS_RESOURCE_RESET)/sizeof(mmGDS_GWS_RESOURCE_RESET[0]), 0, 0 },
+	{ "mmGDS_COMPUTE_MAX_WAVE_ID", REG_MMIO, 0x3348, &mmGDS_COMPUTE_MAX_WAVE_ID[0], sizeof(mmGDS_COMPUTE_MAX_WAVE_ID)/sizeof(mmGDS_COMPUTE_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmGDS_OA_RESET_MASK", REG_MMIO, 0x3349, &mmGDS_OA_RESET_MASK[0], sizeof(mmGDS_OA_RESET_MASK)/sizeof(mmGDS_OA_RESET_MASK[0]), 0, 0 },
+	{ "mmGDS_OA_RESET", REG_MMIO, 0x334a, &mmGDS_OA_RESET[0], sizeof(mmGDS_OA_RESET)/sizeof(mmGDS_OA_RESET[0]), 0, 0 },
+	{ "mmGDS_ENHANCE", REG_MMIO, 0x334b, &mmGDS_ENHANCE[0], sizeof(mmGDS_ENHANCE)/sizeof(mmGDS_ENHANCE[0]), 0, 0 },
+	{ "mmGDS_OA_CGPG_RESTORE", REG_MMIO, 0x334c, &mmGDS_OA_CGPG_RESTORE[0], sizeof(mmGDS_OA_CGPG_RESTORE)/sizeof(mmGDS_OA_CGPG_RESTORE[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_STATUS", REG_MMIO, 0x334d, &mmGDS_CS_CTXSW_STATUS[0], sizeof(mmGDS_CS_CTXSW_STATUS)/sizeof(mmGDS_CS_CTXSW_STATUS[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_CNT0", REG_MMIO, 0x334e, &mmGDS_CS_CTXSW_CNT0[0], sizeof(mmGDS_CS_CTXSW_CNT0)/sizeof(mmGDS_CS_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_CNT1", REG_MMIO, 0x334f, &mmGDS_CS_CTXSW_CNT1[0], sizeof(mmGDS_CS_CTXSW_CNT1)/sizeof(mmGDS_CS_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_CNT2", REG_MMIO, 0x3350, &mmGDS_CS_CTXSW_CNT2[0], sizeof(mmGDS_CS_CTXSW_CNT2)/sizeof(mmGDS_CS_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_CNT3", REG_MMIO, 0x3351, &mmGDS_CS_CTXSW_CNT3[0], sizeof(mmGDS_CS_CTXSW_CNT3)/sizeof(mmGDS_CS_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_GFX_CTXSW_STATUS", REG_MMIO, 0x3352, &mmGDS_GFX_CTXSW_STATUS[0], sizeof(mmGDS_GFX_CTXSW_STATUS)/sizeof(mmGDS_GFX_CTXSW_STATUS[0]), 0, 0 },
+	{ "mmGDS_VS_CTXSW_CNT0", REG_MMIO, 0x3353, &mmGDS_VS_CTXSW_CNT0[0], sizeof(mmGDS_VS_CTXSW_CNT0)/sizeof(mmGDS_VS_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_VS_CTXSW_CNT1", REG_MMIO, 0x3354, &mmGDS_VS_CTXSW_CNT1[0], sizeof(mmGDS_VS_CTXSW_CNT1)/sizeof(mmGDS_VS_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_VS_CTXSW_CNT2", REG_MMIO, 0x3355, &mmGDS_VS_CTXSW_CNT2[0], sizeof(mmGDS_VS_CTXSW_CNT2)/sizeof(mmGDS_VS_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_VS_CTXSW_CNT3", REG_MMIO, 0x3356, &mmGDS_VS_CTXSW_CNT3[0], sizeof(mmGDS_VS_CTXSW_CNT3)/sizeof(mmGDS_VS_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS0_CTXSW_CNT0", REG_MMIO, 0x3357, &mmGDS_PS0_CTXSW_CNT0[0], sizeof(mmGDS_PS0_CTXSW_CNT0)/sizeof(mmGDS_PS0_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS0_CTXSW_CNT1", REG_MMIO, 0x3358, &mmGDS_PS0_CTXSW_CNT1[0], sizeof(mmGDS_PS0_CTXSW_CNT1)/sizeof(mmGDS_PS0_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS0_CTXSW_CNT2", REG_MMIO, 0x3359, &mmGDS_PS0_CTXSW_CNT2[0], sizeof(mmGDS_PS0_CTXSW_CNT2)/sizeof(mmGDS_PS0_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS0_CTXSW_CNT3", REG_MMIO, 0x335a, &mmGDS_PS0_CTXSW_CNT3[0], sizeof(mmGDS_PS0_CTXSW_CNT3)/sizeof(mmGDS_PS0_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS1_CTXSW_CNT0", REG_MMIO, 0x335b, &mmGDS_PS1_CTXSW_CNT0[0], sizeof(mmGDS_PS1_CTXSW_CNT0)/sizeof(mmGDS_PS1_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS1_CTXSW_CNT1", REG_MMIO, 0x335c, &mmGDS_PS1_CTXSW_CNT1[0], sizeof(mmGDS_PS1_CTXSW_CNT1)/sizeof(mmGDS_PS1_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS1_CTXSW_CNT2", REG_MMIO, 0x335d, &mmGDS_PS1_CTXSW_CNT2[0], sizeof(mmGDS_PS1_CTXSW_CNT2)/sizeof(mmGDS_PS1_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS1_CTXSW_CNT3", REG_MMIO, 0x335e, &mmGDS_PS1_CTXSW_CNT3[0], sizeof(mmGDS_PS1_CTXSW_CNT3)/sizeof(mmGDS_PS1_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS2_CTXSW_CNT0", REG_MMIO, 0x335f, &mmGDS_PS2_CTXSW_CNT0[0], sizeof(mmGDS_PS2_CTXSW_CNT0)/sizeof(mmGDS_PS2_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS2_CTXSW_CNT1", REG_MMIO, 0x3360, &mmGDS_PS2_CTXSW_CNT1[0], sizeof(mmGDS_PS2_CTXSW_CNT1)/sizeof(mmGDS_PS2_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS2_CTXSW_CNT2", REG_MMIO, 0x3361, &mmGDS_PS2_CTXSW_CNT2[0], sizeof(mmGDS_PS2_CTXSW_CNT2)/sizeof(mmGDS_PS2_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS2_CTXSW_CNT3", REG_MMIO, 0x3362, &mmGDS_PS2_CTXSW_CNT3[0], sizeof(mmGDS_PS2_CTXSW_CNT3)/sizeof(mmGDS_PS2_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS3_CTXSW_CNT0", REG_MMIO, 0x3363, &mmGDS_PS3_CTXSW_CNT0[0], sizeof(mmGDS_PS3_CTXSW_CNT0)/sizeof(mmGDS_PS3_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS3_CTXSW_CNT1", REG_MMIO, 0x3364, &mmGDS_PS3_CTXSW_CNT1[0], sizeof(mmGDS_PS3_CTXSW_CNT1)/sizeof(mmGDS_PS3_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS3_CTXSW_CNT2", REG_MMIO, 0x3365, &mmGDS_PS3_CTXSW_CNT2[0], sizeof(mmGDS_PS3_CTXSW_CNT2)/sizeof(mmGDS_PS3_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS3_CTXSW_CNT3", REG_MMIO, 0x3366, &mmGDS_PS3_CTXSW_CNT3[0], sizeof(mmGDS_PS3_CTXSW_CNT3)/sizeof(mmGDS_PS3_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS4_CTXSW_CNT0", REG_MMIO, 0x3367, &mmGDS_PS4_CTXSW_CNT0[0], sizeof(mmGDS_PS4_CTXSW_CNT0)/sizeof(mmGDS_PS4_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS4_CTXSW_CNT1", REG_MMIO, 0x3368, &mmGDS_PS4_CTXSW_CNT1[0], sizeof(mmGDS_PS4_CTXSW_CNT1)/sizeof(mmGDS_PS4_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS4_CTXSW_CNT2", REG_MMIO, 0x3369, &mmGDS_PS4_CTXSW_CNT2[0], sizeof(mmGDS_PS4_CTXSW_CNT2)/sizeof(mmGDS_PS4_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS4_CTXSW_CNT3", REG_MMIO, 0x336a, &mmGDS_PS4_CTXSW_CNT3[0], sizeof(mmGDS_PS4_CTXSW_CNT3)/sizeof(mmGDS_PS4_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS5_CTXSW_CNT0", REG_MMIO, 0x336b, &mmGDS_PS5_CTXSW_CNT0[0], sizeof(mmGDS_PS5_CTXSW_CNT0)/sizeof(mmGDS_PS5_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS5_CTXSW_CNT1", REG_MMIO, 0x336c, &mmGDS_PS5_CTXSW_CNT1[0], sizeof(mmGDS_PS5_CTXSW_CNT1)/sizeof(mmGDS_PS5_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS5_CTXSW_CNT2", REG_MMIO, 0x336d, &mmGDS_PS5_CTXSW_CNT2[0], sizeof(mmGDS_PS5_CTXSW_CNT2)/sizeof(mmGDS_PS5_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS5_CTXSW_CNT3", REG_MMIO, 0x336e, &mmGDS_PS5_CTXSW_CNT3[0], sizeof(mmGDS_PS5_CTXSW_CNT3)/sizeof(mmGDS_PS5_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS6_CTXSW_CNT0", REG_MMIO, 0x336f, &mmGDS_PS6_CTXSW_CNT0[0], sizeof(mmGDS_PS6_CTXSW_CNT0)/sizeof(mmGDS_PS6_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS6_CTXSW_CNT1", REG_MMIO, 0x3370, &mmGDS_PS6_CTXSW_CNT1[0], sizeof(mmGDS_PS6_CTXSW_CNT1)/sizeof(mmGDS_PS6_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS6_CTXSW_CNT2", REG_MMIO, 0x3371, &mmGDS_PS6_CTXSW_CNT2[0], sizeof(mmGDS_PS6_CTXSW_CNT2)/sizeof(mmGDS_PS6_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS6_CTXSW_CNT3", REG_MMIO, 0x3372, &mmGDS_PS6_CTXSW_CNT3[0], sizeof(mmGDS_PS6_CTXSW_CNT3)/sizeof(mmGDS_PS6_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS7_CTXSW_CNT0", REG_MMIO, 0x3373, &mmGDS_PS7_CTXSW_CNT0[0], sizeof(mmGDS_PS7_CTXSW_CNT0)/sizeof(mmGDS_PS7_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS7_CTXSW_CNT1", REG_MMIO, 0x3374, &mmGDS_PS7_CTXSW_CNT1[0], sizeof(mmGDS_PS7_CTXSW_CNT1)/sizeof(mmGDS_PS7_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS7_CTXSW_CNT2", REG_MMIO, 0x3375, &mmGDS_PS7_CTXSW_CNT2[0], sizeof(mmGDS_PS7_CTXSW_CNT2)/sizeof(mmGDS_PS7_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS7_CTXSW_CNT3", REG_MMIO, 0x3376, &mmGDS_PS7_CTXSW_CNT3[0], sizeof(mmGDS_PS7_CTXSW_CNT3)/sizeof(mmGDS_PS7_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_CONTROL", REG_MMIO, 0x3380, &mmRAS_SIGNATURE_CONTROL[0], sizeof(mmRAS_SIGNATURE_CONTROL)/sizeof(mmRAS_SIGNATURE_CONTROL[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_MASK", REG_MMIO, 0x3381, &mmRAS_SIGNATURE_MASK[0], sizeof(mmRAS_SIGNATURE_MASK)/sizeof(mmRAS_SIGNATURE_MASK[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE0", REG_MMIO, 0x3382, &mmRAS_SX_SIGNATURE0[0], sizeof(mmRAS_SX_SIGNATURE0)/sizeof(mmRAS_SX_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE1", REG_MMIO, 0x3383, &mmRAS_SX_SIGNATURE1[0], sizeof(mmRAS_SX_SIGNATURE1)/sizeof(mmRAS_SX_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE2", REG_MMIO, 0x3384, &mmRAS_SX_SIGNATURE2[0], sizeof(mmRAS_SX_SIGNATURE2)/sizeof(mmRAS_SX_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE3", REG_MMIO, 0x3385, &mmRAS_SX_SIGNATURE3[0], sizeof(mmRAS_SX_SIGNATURE3)/sizeof(mmRAS_SX_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_DB_SIGNATURE0", REG_MMIO, 0x338b, &mmRAS_DB_SIGNATURE0[0], sizeof(mmRAS_DB_SIGNATURE0)/sizeof(mmRAS_DB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_PA_SIGNATURE0", REG_MMIO, 0x338c, &mmRAS_PA_SIGNATURE0[0], sizeof(mmRAS_PA_SIGNATURE0)/sizeof(mmRAS_PA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_VGT_SIGNATURE0", REG_MMIO, 0x338d, &mmRAS_VGT_SIGNATURE0[0], sizeof(mmRAS_VGT_SIGNATURE0)/sizeof(mmRAS_VGT_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SQ_SIGNATURE0", REG_MMIO, 0x338e, &mmRAS_SQ_SIGNATURE0[0], sizeof(mmRAS_SQ_SIGNATURE0)/sizeof(mmRAS_SQ_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE0", REG_MMIO, 0x338f, &mmRAS_SC_SIGNATURE0[0], sizeof(mmRAS_SC_SIGNATURE0)/sizeof(mmRAS_SC_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE1", REG_MMIO, 0x3390, &mmRAS_SC_SIGNATURE1[0], sizeof(mmRAS_SC_SIGNATURE1)/sizeof(mmRAS_SC_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE2", REG_MMIO, 0x3391, &mmRAS_SC_SIGNATURE2[0], sizeof(mmRAS_SC_SIGNATURE2)/sizeof(mmRAS_SC_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE3", REG_MMIO, 0x3392, &mmRAS_SC_SIGNATURE3[0], sizeof(mmRAS_SC_SIGNATURE3)/sizeof(mmRAS_SC_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE4", REG_MMIO, 0x3393, &mmRAS_SC_SIGNATURE4[0], sizeof(mmRAS_SC_SIGNATURE4)/sizeof(mmRAS_SC_SIGNATURE4[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE5", REG_MMIO, 0x3394, &mmRAS_SC_SIGNATURE5[0], sizeof(mmRAS_SC_SIGNATURE5)/sizeof(mmRAS_SC_SIGNATURE5[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE6", REG_MMIO, 0x3395, &mmRAS_SC_SIGNATURE6[0], sizeof(mmRAS_SC_SIGNATURE6)/sizeof(mmRAS_SC_SIGNATURE6[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE7", REG_MMIO, 0x3396, &mmRAS_SC_SIGNATURE7[0], sizeof(mmRAS_SC_SIGNATURE7)/sizeof(mmRAS_SC_SIGNATURE7[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE0", REG_MMIO, 0x3397, &mmRAS_IA_SIGNATURE0[0], sizeof(mmRAS_IA_SIGNATURE0)/sizeof(mmRAS_IA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE1", REG_MMIO, 0x3398, &mmRAS_IA_SIGNATURE1[0], sizeof(mmRAS_IA_SIGNATURE1)/sizeof(mmRAS_IA_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE0", REG_MMIO, 0x3399, &mmRAS_SPI_SIGNATURE0[0], sizeof(mmRAS_SPI_SIGNATURE0)/sizeof(mmRAS_SPI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE1", REG_MMIO, 0x339a, &mmRAS_SPI_SIGNATURE1[0], sizeof(mmRAS_SPI_SIGNATURE1)/sizeof(mmRAS_SPI_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_TA_SIGNATURE0", REG_MMIO, 0x339b, &mmRAS_TA_SIGNATURE0[0], sizeof(mmRAS_TA_SIGNATURE0)/sizeof(mmRAS_TA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_TD_SIGNATURE0", REG_MMIO, 0x339c, &mmRAS_TD_SIGNATURE0[0], sizeof(mmRAS_TD_SIGNATURE0)/sizeof(mmRAS_TD_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_CB_SIGNATURE0", REG_MMIO, 0x339d, &mmRAS_CB_SIGNATURE0[0], sizeof(mmRAS_CB_SIGNATURE0)/sizeof(mmRAS_CB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE0", REG_MMIO, 0x339e, &mmRAS_BCI_SIGNATURE0[0], sizeof(mmRAS_BCI_SIGNATURE0)/sizeof(mmRAS_BCI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE1", REG_MMIO, 0x339f, &mmRAS_BCI_SIGNATURE1[0], sizeof(mmRAS_BCI_SIGNATURE1)/sizeof(mmRAS_BCI_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_TA_SIGNATURE1", REG_MMIO, 0x33a0, &mmRAS_TA_SIGNATURE1[0], sizeof(mmRAS_TA_SIGNATURE1)/sizeof(mmRAS_TA_SIGNATURE1[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG04", REG_SMC, 0x4, &ixCLIPPER_DEBUG_REG04[0], sizeof(ixCLIPPER_DEBUG_REG04)/sizeof(ixCLIPPER_DEBUG_REG04[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG4", REG_SMC, 0x4, &ixGDS_DEBUG_REG4[0], sizeof(ixGDS_DEBUG_REG4)/sizeof(ixGDS_DEBUG_REG4[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG4", REG_SMC, 0x4, &ixWD_DEBUG_REG4[0], sizeof(ixWD_DEBUG_REG4)/sizeof(ixWD_DEBUG_REG4[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL0", REG_SMC, 0x40, &ixDIDT_TD_CTRL0[0], sizeof(ixDIDT_TD_CTRL0)/sizeof(ixDIDT_TD_CTRL0[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL1", REG_SMC, 0x41, &ixDIDT_TD_CTRL1[0], sizeof(ixDIDT_TD_CTRL1)/sizeof(ixDIDT_TD_CTRL1[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL2", REG_SMC, 0x42, &ixDIDT_TD_CTRL2[0], sizeof(ixDIDT_TD_CTRL2)/sizeof(ixDIDT_TD_CTRL2[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL_OCP", REG_SMC, 0x43, &ixDIDT_TD_CTRL_OCP[0], sizeof(ixDIDT_TD_CTRL_OCP)/sizeof(ixDIDT_TD_CTRL_OCP[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG05", REG_SMC, 0x5, &ixCLIPPER_DEBUG_REG05[0], sizeof(ixCLIPPER_DEBUG_REG05)/sizeof(ixCLIPPER_DEBUG_REG05[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG5", REG_SMC, 0x5, &ixGDS_DEBUG_REG5[0], sizeof(ixGDS_DEBUG_REG5)/sizeof(ixGDS_DEBUG_REG5[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG5", REG_SMC, 0x5, &ixWD_DEBUG_REG5[0], sizeof(ixWD_DEBUG_REG5)/sizeof(ixWD_DEBUG_REG5[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT0_3", REG_SMC, 0x50, &ixDIDT_TD_WEIGHT0_3[0], sizeof(ixDIDT_TD_WEIGHT0_3)/sizeof(ixDIDT_TD_WEIGHT0_3[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT4_7", REG_SMC, 0x51, &ixDIDT_TD_WEIGHT4_7[0], sizeof(ixDIDT_TD_WEIGHT4_7)/sizeof(ixDIDT_TD_WEIGHT4_7[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT8_11", REG_SMC, 0x52, &ixDIDT_TD_WEIGHT8_11[0], sizeof(ixDIDT_TD_WEIGHT8_11)/sizeof(ixDIDT_TD_WEIGHT8_11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG06", REG_SMC, 0x6, &ixCLIPPER_DEBUG_REG06[0], sizeof(ixCLIPPER_DEBUG_REG06)/sizeof(ixCLIPPER_DEBUG_REG06[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG6", REG_SMC, 0x6, &ixGDS_DEBUG_REG6[0], sizeof(ixGDS_DEBUG_REG6)/sizeof(ixGDS_DEBUG_REG6[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG6", REG_SMC, 0x6, &ixWD_DEBUG_REG6[0], sizeof(ixWD_DEBUG_REG6)/sizeof(ixWD_DEBUG_REG6[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL0", REG_SMC, 0x60, &ixDIDT_TCP_CTRL0[0], sizeof(ixDIDT_TCP_CTRL0)/sizeof(ixDIDT_TCP_CTRL0[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL1", REG_SMC, 0x61, &ixDIDT_TCP_CTRL1[0], sizeof(ixDIDT_TCP_CTRL1)/sizeof(ixDIDT_TCP_CTRL1[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL2", REG_SMC, 0x62, &ixDIDT_TCP_CTRL2[0], sizeof(ixDIDT_TCP_CTRL2)/sizeof(ixDIDT_TCP_CTRL2[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL_OCP", REG_SMC, 0x63, &ixDIDT_TCP_CTRL_OCP[0], sizeof(ixDIDT_TCP_CTRL_OCP)/sizeof(ixDIDT_TCP_CTRL_OCP[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG07", REG_SMC, 0x7, &ixCLIPPER_DEBUG_REG07[0], sizeof(ixCLIPPER_DEBUG_REG07)/sizeof(ixCLIPPER_DEBUG_REG07[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG18", REG_SMC, 0x7, &ixVGT_DEBUG_REG18[0], sizeof(ixVGT_DEBUG_REG18)/sizeof(ixVGT_DEBUG_REG18[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG7", REG_SMC, 0x7, &ixWD_DEBUG_REG7[0], sizeof(ixWD_DEBUG_REG7)/sizeof(ixWD_DEBUG_REG7[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT0_3", REG_SMC, 0x70, &ixDIDT_TCP_WEIGHT0_3[0], sizeof(ixDIDT_TCP_WEIGHT0_3)/sizeof(ixDIDT_TCP_WEIGHT0_3[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT4_7", REG_SMC, 0x71, &ixDIDT_TCP_WEIGHT4_7[0], sizeof(ixDIDT_TCP_WEIGHT4_7)/sizeof(ixDIDT_TCP_WEIGHT4_7[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT8_11", REG_SMC, 0x72, &ixDIDT_TCP_WEIGHT8_11[0], sizeof(ixDIDT_TCP_WEIGHT8_11)/sizeof(ixDIDT_TCP_WEIGHT8_11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG08", REG_SMC, 0x8, &ixCLIPPER_DEBUG_REG08[0], sizeof(ixCLIPPER_DEBUG_REG08)/sizeof(ixCLIPPER_DEBUG_REG08[0]), 0, 0 },
+	{ "ixSQ_DEBUG_STS_LOCAL", REG_SMC, 0x8, &ixSQ_DEBUG_STS_LOCAL[0], sizeof(ixSQ_DEBUG_STS_LOCAL)/sizeof(ixSQ_DEBUG_STS_LOCAL[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG8", REG_SMC, 0x8, &ixVGT_DEBUG_REG8[0], sizeof(ixVGT_DEBUG_REG8)/sizeof(ixVGT_DEBUG_REG8[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG8", REG_SMC, 0x8, &ixWD_DEBUG_REG8[0], sizeof(ixWD_DEBUG_REG8)/sizeof(ixWD_DEBUG_REG8[0]), 0, 0 },
+	{ "ixDIDT_DBR_CTRL0", REG_SMC, 0x80, &ixDIDT_DBR_CTRL0[0], sizeof(ixDIDT_DBR_CTRL0)/sizeof(ixDIDT_DBR_CTRL0[0]), 0, 0 },
+	{ "ixDIDT_DBR_CTRL1", REG_SMC, 0x81, &ixDIDT_DBR_CTRL1[0], sizeof(ixDIDT_DBR_CTRL1)/sizeof(ixDIDT_DBR_CTRL1[0]), 0, 0 },
+	{ "ixDIDT_DBR_CTRL2", REG_SMC, 0x82, &ixDIDT_DBR_CTRL2[0], sizeof(ixDIDT_DBR_CTRL2)/sizeof(ixDIDT_DBR_CTRL2[0]), 0, 0 },
+	{ "ixDIDT_DBR_CTRL_OCP", REG_SMC, 0x83, &ixDIDT_DBR_CTRL_OCP[0], sizeof(ixDIDT_DBR_CTRL_OCP)/sizeof(ixDIDT_DBR_CTRL_OCP[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG09", REG_SMC, 0x9, &ixCLIPPER_DEBUG_REG09[0], sizeof(ixCLIPPER_DEBUG_REG09)/sizeof(ixCLIPPER_DEBUG_REG09[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG9", REG_SMC, 0x9, &ixVGT_DEBUG_REG9[0], sizeof(ixVGT_DEBUG_REG9)/sizeof(ixVGT_DEBUG_REG9[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG9", REG_SMC, 0x9, &ixWD_DEBUG_REG9[0], sizeof(ixWD_DEBUG_REG9)/sizeof(ixWD_DEBUG_REG9[0]), 0, 0 },
+	{ "ixDIDT_DBR_WEIGHT0_3", REG_SMC, 0x90, &ixDIDT_DBR_WEIGHT0_3[0], sizeof(ixDIDT_DBR_WEIGHT0_3)/sizeof(ixDIDT_DBR_WEIGHT0_3[0]), 0, 0 },
+	{ "ixDIDT_DBR_WEIGHT4_7", REG_SMC, 0x91, &ixDIDT_DBR_WEIGHT4_7[0], sizeof(ixDIDT_DBR_WEIGHT4_7)/sizeof(ixDIDT_DBR_WEIGHT4_7[0]), 0, 0 },
+	{ "ixDIDT_DBR_WEIGHT8_11", REG_SMC, 0x92, &ixDIDT_DBR_WEIGHT8_11[0], sizeof(ixDIDT_DBR_WEIGHT8_11)/sizeof(ixDIDT_DBR_WEIGHT8_11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG10", REG_SMC, 0xa, &ixCLIPPER_DEBUG_REG10[0], sizeof(ixCLIPPER_DEBUG_REG10)/sizeof(ixCLIPPER_DEBUG_REG10[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG10", REG_SMC, 0xa, &ixVGT_DEBUG_REG10[0], sizeof(ixVGT_DEBUG_REG10)/sizeof(ixVGT_DEBUG_REG10[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG10", REG_SMC, 0xa, &ixWD_DEBUG_REG10[0], sizeof(ixWD_DEBUG_REG10)/sizeof(ixWD_DEBUG_REG10[0]), 0, 0 },
+	{ "mmDB_RENDER_CONTROL", REG_MMIO, 0xa000, &mmDB_RENDER_CONTROL[0], sizeof(mmDB_RENDER_CONTROL)/sizeof(mmDB_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmDB_COUNT_CONTROL", REG_MMIO, 0xa001, &mmDB_COUNT_CONTROL[0], sizeof(mmDB_COUNT_CONTROL)/sizeof(mmDB_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmDB_DEPTH_VIEW", REG_MMIO, 0xa002, &mmDB_DEPTH_VIEW[0], sizeof(mmDB_DEPTH_VIEW)/sizeof(mmDB_DEPTH_VIEW[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE", REG_MMIO, 0xa003, &mmDB_RENDER_OVERRIDE[0], sizeof(mmDB_RENDER_OVERRIDE)/sizeof(mmDB_RENDER_OVERRIDE[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE2", REG_MMIO, 0xa004, &mmDB_RENDER_OVERRIDE2[0], sizeof(mmDB_RENDER_OVERRIDE2)/sizeof(mmDB_RENDER_OVERRIDE2[0]), 0, 0 },
+	{ "mmDB_HTILE_DATA_BASE", REG_MMIO, 0xa005, &mmDB_HTILE_DATA_BASE[0], sizeof(mmDB_HTILE_DATA_BASE)/sizeof(mmDB_HTILE_DATA_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MIN", REG_MMIO, 0xa008, &mmDB_DEPTH_BOUNDS_MIN[0], sizeof(mmDB_DEPTH_BOUNDS_MIN)/sizeof(mmDB_DEPTH_BOUNDS_MIN[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MAX", REG_MMIO, 0xa009, &mmDB_DEPTH_BOUNDS_MAX[0], sizeof(mmDB_DEPTH_BOUNDS_MAX)/sizeof(mmDB_DEPTH_BOUNDS_MAX[0]), 0, 0 },
+	{ "mmDB_STENCIL_CLEAR", REG_MMIO, 0xa00a, &mmDB_STENCIL_CLEAR[0], sizeof(mmDB_STENCIL_CLEAR)/sizeof(mmDB_STENCIL_CLEAR[0]), 0, 0 },
+	{ "mmDB_DEPTH_CLEAR", REG_MMIO, 0xa00b, &mmDB_DEPTH_CLEAR[0], sizeof(mmDB_DEPTH_CLEAR)/sizeof(mmDB_DEPTH_CLEAR[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_TL", REG_MMIO, 0xa00c, &mmPA_SC_SCREEN_SCISSOR_TL[0], sizeof(mmPA_SC_SCREEN_SCISSOR_TL)/sizeof(mmPA_SC_SCREEN_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_BR", REG_MMIO, 0xa00d, &mmPA_SC_SCREEN_SCISSOR_BR[0], sizeof(mmPA_SC_SCREEN_SCISSOR_BR)/sizeof(mmPA_SC_SCREEN_SCISSOR_BR[0]), 0, 0 },
+	{ "mmDB_DEPTH_INFO", REG_MMIO, 0xa00f, &mmDB_DEPTH_INFO[0], sizeof(mmDB_DEPTH_INFO)/sizeof(mmDB_DEPTH_INFO[0]), 0, 0 },
+	{ "mmDB_Z_INFO", REG_MMIO, 0xa010, &mmDB_Z_INFO[0], sizeof(mmDB_Z_INFO)/sizeof(mmDB_Z_INFO[0]), 0, 0 },
+	{ "mmDB_STENCIL_INFO", REG_MMIO, 0xa011, &mmDB_STENCIL_INFO[0], sizeof(mmDB_STENCIL_INFO)/sizeof(mmDB_STENCIL_INFO[0]), 0, 0 },
+	{ "mmDB_Z_READ_BASE", REG_MMIO, 0xa012, &mmDB_Z_READ_BASE[0], sizeof(mmDB_Z_READ_BASE)/sizeof(mmDB_Z_READ_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_READ_BASE", REG_MMIO, 0xa013, &mmDB_STENCIL_READ_BASE[0], sizeof(mmDB_STENCIL_READ_BASE)/sizeof(mmDB_STENCIL_READ_BASE[0]), 0, 0 },
+	{ "mmDB_Z_WRITE_BASE", REG_MMIO, 0xa014, &mmDB_Z_WRITE_BASE[0], sizeof(mmDB_Z_WRITE_BASE)/sizeof(mmDB_Z_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_WRITE_BASE", REG_MMIO, 0xa015, &mmDB_STENCIL_WRITE_BASE[0], sizeof(mmDB_STENCIL_WRITE_BASE)/sizeof(mmDB_STENCIL_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SIZE", REG_MMIO, 0xa016, &mmDB_DEPTH_SIZE[0], sizeof(mmDB_DEPTH_SIZE)/sizeof(mmDB_DEPTH_SIZE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SLICE", REG_MMIO, 0xa017, &mmDB_DEPTH_SLICE[0], sizeof(mmDB_DEPTH_SLICE)/sizeof(mmDB_DEPTH_SLICE[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR", REG_MMIO, 0xa020, &mmTA_BC_BASE_ADDR[0], sizeof(mmTA_BC_BASE_ADDR)/sizeof(mmTA_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR_HI", REG_MMIO, 0xa021, &mmTA_BC_BASE_ADDR_HI[0], sizeof(mmTA_BC_BASE_ADDR_HI)/sizeof(mmTA_BC_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_0", REG_MMIO, 0xa07a, &mmCOHER_DEST_BASE_HI_0[0], sizeof(mmCOHER_DEST_BASE_HI_0)/sizeof(mmCOHER_DEST_BASE_HI_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_1", REG_MMIO, 0xa07b, &mmCOHER_DEST_BASE_HI_1[0], sizeof(mmCOHER_DEST_BASE_HI_1)/sizeof(mmCOHER_DEST_BASE_HI_1[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_2", REG_MMIO, 0xa07c, &mmCOHER_DEST_BASE_HI_2[0], sizeof(mmCOHER_DEST_BASE_HI_2)/sizeof(mmCOHER_DEST_BASE_HI_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_3", REG_MMIO, 0xa07d, &mmCOHER_DEST_BASE_HI_3[0], sizeof(mmCOHER_DEST_BASE_HI_3)/sizeof(mmCOHER_DEST_BASE_HI_3[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_2", REG_MMIO, 0xa07e, &mmCOHER_DEST_BASE_2[0], sizeof(mmCOHER_DEST_BASE_2)/sizeof(mmCOHER_DEST_BASE_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_3", REG_MMIO, 0xa07f, &mmCOHER_DEST_BASE_3[0], sizeof(mmCOHER_DEST_BASE_3)/sizeof(mmCOHER_DEST_BASE_3[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_OFFSET", REG_MMIO, 0xa080, &mmPA_SC_WINDOW_OFFSET[0], sizeof(mmPA_SC_WINDOW_OFFSET)/sizeof(mmPA_SC_WINDOW_OFFSET[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_TL", REG_MMIO, 0xa081, &mmPA_SC_WINDOW_SCISSOR_TL[0], sizeof(mmPA_SC_WINDOW_SCISSOR_TL)/sizeof(mmPA_SC_WINDOW_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_BR", REG_MMIO, 0xa082, &mmPA_SC_WINDOW_SCISSOR_BR[0], sizeof(mmPA_SC_WINDOW_SCISSOR_BR)/sizeof(mmPA_SC_WINDOW_SCISSOR_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_RULE", REG_MMIO, 0xa083, &mmPA_SC_CLIPRECT_RULE[0], sizeof(mmPA_SC_CLIPRECT_RULE)/sizeof(mmPA_SC_CLIPRECT_RULE[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_TL", REG_MMIO, 0xa084, &mmPA_SC_CLIPRECT_0_TL[0], sizeof(mmPA_SC_CLIPRECT_0_TL)/sizeof(mmPA_SC_CLIPRECT_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_BR", REG_MMIO, 0xa085, &mmPA_SC_CLIPRECT_0_BR[0], sizeof(mmPA_SC_CLIPRECT_0_BR)/sizeof(mmPA_SC_CLIPRECT_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_TL", REG_MMIO, 0xa086, &mmPA_SC_CLIPRECT_1_TL[0], sizeof(mmPA_SC_CLIPRECT_1_TL)/sizeof(mmPA_SC_CLIPRECT_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_BR", REG_MMIO, 0xa087, &mmPA_SC_CLIPRECT_1_BR[0], sizeof(mmPA_SC_CLIPRECT_1_BR)/sizeof(mmPA_SC_CLIPRECT_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_TL", REG_MMIO, 0xa088, &mmPA_SC_CLIPRECT_2_TL[0], sizeof(mmPA_SC_CLIPRECT_2_TL)/sizeof(mmPA_SC_CLIPRECT_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_BR", REG_MMIO, 0xa089, &mmPA_SC_CLIPRECT_2_BR[0], sizeof(mmPA_SC_CLIPRECT_2_BR)/sizeof(mmPA_SC_CLIPRECT_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_TL", REG_MMIO, 0xa08a, &mmPA_SC_CLIPRECT_3_TL[0], sizeof(mmPA_SC_CLIPRECT_3_TL)/sizeof(mmPA_SC_CLIPRECT_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_BR", REG_MMIO, 0xa08b, &mmPA_SC_CLIPRECT_3_BR[0], sizeof(mmPA_SC_CLIPRECT_3_BR)/sizeof(mmPA_SC_CLIPRECT_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_EDGERULE", REG_MMIO, 0xa08c, &mmPA_SC_EDGERULE[0], sizeof(mmPA_SC_EDGERULE)/sizeof(mmPA_SC_EDGERULE[0]), 0, 0 },
+	{ "mmPA_SU_HARDWARE_SCREEN_OFFSET", REG_MMIO, 0xa08d, &mmPA_SU_HARDWARE_SCREEN_OFFSET[0], sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET)/sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET[0]), 0, 0 },
+	{ "mmCB_TARGET_MASK", REG_MMIO, 0xa08e, &mmCB_TARGET_MASK[0], sizeof(mmCB_TARGET_MASK)/sizeof(mmCB_TARGET_MASK[0]), 0, 0 },
+	{ "mmCB_SHADER_MASK", REG_MMIO, 0xa08f, &mmCB_SHADER_MASK[0], sizeof(mmCB_SHADER_MASK)/sizeof(mmCB_SHADER_MASK[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_TL", REG_MMIO, 0xa090, &mmPA_SC_GENERIC_SCISSOR_TL[0], sizeof(mmPA_SC_GENERIC_SCISSOR_TL)/sizeof(mmPA_SC_GENERIC_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_BR", REG_MMIO, 0xa091, &mmPA_SC_GENERIC_SCISSOR_BR[0], sizeof(mmPA_SC_GENERIC_SCISSOR_BR)/sizeof(mmPA_SC_GENERIC_SCISSOR_BR[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_0", REG_MMIO, 0xa092, &mmCOHER_DEST_BASE_0[0], sizeof(mmCOHER_DEST_BASE_0)/sizeof(mmCOHER_DEST_BASE_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_1", REG_MMIO, 0xa093, &mmCOHER_DEST_BASE_1[0], sizeof(mmCOHER_DEST_BASE_1)/sizeof(mmCOHER_DEST_BASE_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_TL", REG_MMIO, 0xa094, &mmPA_SC_VPORT_SCISSOR_0_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_BR", REG_MMIO, 0xa095, &mmPA_SC_VPORT_SCISSOR_0_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_TL", REG_MMIO, 0xa096, &mmPA_SC_VPORT_SCISSOR_1_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_BR", REG_MMIO, 0xa097, &mmPA_SC_VPORT_SCISSOR_1_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_TL", REG_MMIO, 0xa098, &mmPA_SC_VPORT_SCISSOR_2_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_BR", REG_MMIO, 0xa099, &mmPA_SC_VPORT_SCISSOR_2_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_TL", REG_MMIO, 0xa09a, &mmPA_SC_VPORT_SCISSOR_3_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_BR", REG_MMIO, 0xa09b, &mmPA_SC_VPORT_SCISSOR_3_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_TL", REG_MMIO, 0xa09c, &mmPA_SC_VPORT_SCISSOR_4_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_4_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_BR", REG_MMIO, 0xa09d, &mmPA_SC_VPORT_SCISSOR_4_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_4_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_TL", REG_MMIO, 0xa09e, &mmPA_SC_VPORT_SCISSOR_5_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_5_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_BR", REG_MMIO, 0xa09f, &mmPA_SC_VPORT_SCISSOR_5_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_5_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_TL", REG_MMIO, 0xa0a0, &mmPA_SC_VPORT_SCISSOR_6_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_6_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_BR", REG_MMIO, 0xa0a1, &mmPA_SC_VPORT_SCISSOR_6_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_6_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_TL", REG_MMIO, 0xa0a2, &mmPA_SC_VPORT_SCISSOR_7_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_7_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_BR", REG_MMIO, 0xa0a3, &mmPA_SC_VPORT_SCISSOR_7_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_7_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_TL", REG_MMIO, 0xa0a4, &mmPA_SC_VPORT_SCISSOR_8_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_8_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_BR", REG_MMIO, 0xa0a5, &mmPA_SC_VPORT_SCISSOR_8_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_8_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_TL", REG_MMIO, 0xa0a6, &mmPA_SC_VPORT_SCISSOR_9_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_9_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_BR", REG_MMIO, 0xa0a7, &mmPA_SC_VPORT_SCISSOR_9_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_9_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_TL", REG_MMIO, 0xa0a8, &mmPA_SC_VPORT_SCISSOR_10_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_10_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_BR", REG_MMIO, 0xa0a9, &mmPA_SC_VPORT_SCISSOR_10_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_10_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_TL", REG_MMIO, 0xa0aa, &mmPA_SC_VPORT_SCISSOR_11_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_11_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_BR", REG_MMIO, 0xa0ab, &mmPA_SC_VPORT_SCISSOR_11_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_11_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_TL", REG_MMIO, 0xa0ac, &mmPA_SC_VPORT_SCISSOR_12_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_12_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_BR", REG_MMIO, 0xa0ad, &mmPA_SC_VPORT_SCISSOR_12_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_12_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_TL", REG_MMIO, 0xa0ae, &mmPA_SC_VPORT_SCISSOR_13_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_13_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_BR", REG_MMIO, 0xa0af, &mmPA_SC_VPORT_SCISSOR_13_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_13_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_TL", REG_MMIO, 0xa0b0, &mmPA_SC_VPORT_SCISSOR_14_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_14_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_BR", REG_MMIO, 0xa0b1, &mmPA_SC_VPORT_SCISSOR_14_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_14_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_TL", REG_MMIO, 0xa0b2, &mmPA_SC_VPORT_SCISSOR_15_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_15_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_BR", REG_MMIO, 0xa0b3, &mmPA_SC_VPORT_SCISSOR_15_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_15_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_0", REG_MMIO, 0xa0b4, &mmPA_SC_VPORT_ZMIN_0[0], sizeof(mmPA_SC_VPORT_ZMIN_0)/sizeof(mmPA_SC_VPORT_ZMIN_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_0", REG_MMIO, 0xa0b5, &mmPA_SC_VPORT_ZMAX_0[0], sizeof(mmPA_SC_VPORT_ZMAX_0)/sizeof(mmPA_SC_VPORT_ZMAX_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_1", REG_MMIO, 0xa0b6, &mmPA_SC_VPORT_ZMIN_1[0], sizeof(mmPA_SC_VPORT_ZMIN_1)/sizeof(mmPA_SC_VPORT_ZMIN_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_1", REG_MMIO, 0xa0b7, &mmPA_SC_VPORT_ZMAX_1[0], sizeof(mmPA_SC_VPORT_ZMAX_1)/sizeof(mmPA_SC_VPORT_ZMAX_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_2", REG_MMIO, 0xa0b8, &mmPA_SC_VPORT_ZMIN_2[0], sizeof(mmPA_SC_VPORT_ZMIN_2)/sizeof(mmPA_SC_VPORT_ZMIN_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_2", REG_MMIO, 0xa0b9, &mmPA_SC_VPORT_ZMAX_2[0], sizeof(mmPA_SC_VPORT_ZMAX_2)/sizeof(mmPA_SC_VPORT_ZMAX_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_3", REG_MMIO, 0xa0ba, &mmPA_SC_VPORT_ZMIN_3[0], sizeof(mmPA_SC_VPORT_ZMIN_3)/sizeof(mmPA_SC_VPORT_ZMIN_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_3", REG_MMIO, 0xa0bb, &mmPA_SC_VPORT_ZMAX_3[0], sizeof(mmPA_SC_VPORT_ZMAX_3)/sizeof(mmPA_SC_VPORT_ZMAX_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_4", REG_MMIO, 0xa0bc, &mmPA_SC_VPORT_ZMIN_4[0], sizeof(mmPA_SC_VPORT_ZMIN_4)/sizeof(mmPA_SC_VPORT_ZMIN_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_4", REG_MMIO, 0xa0bd, &mmPA_SC_VPORT_ZMAX_4[0], sizeof(mmPA_SC_VPORT_ZMAX_4)/sizeof(mmPA_SC_VPORT_ZMAX_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_5", REG_MMIO, 0xa0be, &mmPA_SC_VPORT_ZMIN_5[0], sizeof(mmPA_SC_VPORT_ZMIN_5)/sizeof(mmPA_SC_VPORT_ZMIN_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_5", REG_MMIO, 0xa0bf, &mmPA_SC_VPORT_ZMAX_5[0], sizeof(mmPA_SC_VPORT_ZMAX_5)/sizeof(mmPA_SC_VPORT_ZMAX_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_6", REG_MMIO, 0xa0c0, &mmPA_SC_VPORT_ZMIN_6[0], sizeof(mmPA_SC_VPORT_ZMIN_6)/sizeof(mmPA_SC_VPORT_ZMIN_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_6", REG_MMIO, 0xa0c1, &mmPA_SC_VPORT_ZMAX_6[0], sizeof(mmPA_SC_VPORT_ZMAX_6)/sizeof(mmPA_SC_VPORT_ZMAX_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_7", REG_MMIO, 0xa0c2, &mmPA_SC_VPORT_ZMIN_7[0], sizeof(mmPA_SC_VPORT_ZMIN_7)/sizeof(mmPA_SC_VPORT_ZMIN_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_7", REG_MMIO, 0xa0c3, &mmPA_SC_VPORT_ZMAX_7[0], sizeof(mmPA_SC_VPORT_ZMAX_7)/sizeof(mmPA_SC_VPORT_ZMAX_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_8", REG_MMIO, 0xa0c4, &mmPA_SC_VPORT_ZMIN_8[0], sizeof(mmPA_SC_VPORT_ZMIN_8)/sizeof(mmPA_SC_VPORT_ZMIN_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_8", REG_MMIO, 0xa0c5, &mmPA_SC_VPORT_ZMAX_8[0], sizeof(mmPA_SC_VPORT_ZMAX_8)/sizeof(mmPA_SC_VPORT_ZMAX_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_9", REG_MMIO, 0xa0c6, &mmPA_SC_VPORT_ZMIN_9[0], sizeof(mmPA_SC_VPORT_ZMIN_9)/sizeof(mmPA_SC_VPORT_ZMIN_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_9", REG_MMIO, 0xa0c7, &mmPA_SC_VPORT_ZMAX_9[0], sizeof(mmPA_SC_VPORT_ZMAX_9)/sizeof(mmPA_SC_VPORT_ZMAX_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_10", REG_MMIO, 0xa0c8, &mmPA_SC_VPORT_ZMIN_10[0], sizeof(mmPA_SC_VPORT_ZMIN_10)/sizeof(mmPA_SC_VPORT_ZMIN_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_10", REG_MMIO, 0xa0c9, &mmPA_SC_VPORT_ZMAX_10[0], sizeof(mmPA_SC_VPORT_ZMAX_10)/sizeof(mmPA_SC_VPORT_ZMAX_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_11", REG_MMIO, 0xa0ca, &mmPA_SC_VPORT_ZMIN_11[0], sizeof(mmPA_SC_VPORT_ZMIN_11)/sizeof(mmPA_SC_VPORT_ZMIN_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_11", REG_MMIO, 0xa0cb, &mmPA_SC_VPORT_ZMAX_11[0], sizeof(mmPA_SC_VPORT_ZMAX_11)/sizeof(mmPA_SC_VPORT_ZMAX_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_12", REG_MMIO, 0xa0cc, &mmPA_SC_VPORT_ZMIN_12[0], sizeof(mmPA_SC_VPORT_ZMIN_12)/sizeof(mmPA_SC_VPORT_ZMIN_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_12", REG_MMIO, 0xa0cd, &mmPA_SC_VPORT_ZMAX_12[0], sizeof(mmPA_SC_VPORT_ZMAX_12)/sizeof(mmPA_SC_VPORT_ZMAX_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_13", REG_MMIO, 0xa0ce, &mmPA_SC_VPORT_ZMIN_13[0], sizeof(mmPA_SC_VPORT_ZMIN_13)/sizeof(mmPA_SC_VPORT_ZMIN_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_13", REG_MMIO, 0xa0cf, &mmPA_SC_VPORT_ZMAX_13[0], sizeof(mmPA_SC_VPORT_ZMAX_13)/sizeof(mmPA_SC_VPORT_ZMAX_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_14", REG_MMIO, 0xa0d0, &mmPA_SC_VPORT_ZMIN_14[0], sizeof(mmPA_SC_VPORT_ZMIN_14)/sizeof(mmPA_SC_VPORT_ZMIN_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_14", REG_MMIO, 0xa0d1, &mmPA_SC_VPORT_ZMAX_14[0], sizeof(mmPA_SC_VPORT_ZMAX_14)/sizeof(mmPA_SC_VPORT_ZMAX_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_15", REG_MMIO, 0xa0d2, &mmPA_SC_VPORT_ZMIN_15[0], sizeof(mmPA_SC_VPORT_ZMIN_15)/sizeof(mmPA_SC_VPORT_ZMIN_15[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_15", REG_MMIO, 0xa0d3, &mmPA_SC_VPORT_ZMAX_15[0], sizeof(mmPA_SC_VPORT_ZMAX_15)/sizeof(mmPA_SC_VPORT_ZMAX_15[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG", REG_MMIO, 0xa0d4, &mmPA_SC_RASTER_CONFIG[0], sizeof(mmPA_SC_RASTER_CONFIG)/sizeof(mmPA_SC_RASTER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG_1", REG_MMIO, 0xa0d5, &mmPA_SC_RASTER_CONFIG_1[0], sizeof(mmPA_SC_RASTER_CONFIG_1)/sizeof(mmPA_SC_RASTER_CONFIG_1[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_CONTROL", REG_MMIO, 0xa0d6, &mmPA_SC_SCREEN_EXTENT_CONTROL[0], sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL)/sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTX_CNTL", REG_MMIO, 0xa0d8, &mmCP_PERFMON_CNTX_CNTL[0], sizeof(mmCP_PERFMON_CNTX_CNTL)/sizeof(mmCP_PERFMON_CNTX_CNTL[0]), 0, 0 },
+	{ "mmCP_RINGID", REG_MMIO, 0xa0d9, &mmCP_RINGID[0], sizeof(mmCP_RINGID)/sizeof(mmCP_RINGID[0]), 0, 0 },
+	{ "mmCP_VMID", REG_MMIO, 0xa0da, &mmCP_VMID[0], sizeof(mmCP_VMID)/sizeof(mmCP_VMID[0]), 0, 0 },
+	{ "mmVGT_MAX_VTX_INDX", REG_MMIO, 0xa100, &mmVGT_MAX_VTX_INDX[0], sizeof(mmVGT_MAX_VTX_INDX)/sizeof(mmVGT_MAX_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_MIN_VTX_INDX", REG_MMIO, 0xa101, &mmVGT_MIN_VTX_INDX[0], sizeof(mmVGT_MIN_VTX_INDX)/sizeof(mmVGT_MIN_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_INDX_OFFSET", REG_MMIO, 0xa102, &mmVGT_INDX_OFFSET[0], sizeof(mmVGT_INDX_OFFSET)/sizeof(mmVGT_INDX_OFFSET[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_INDX", REG_MMIO, 0xa103, &mmVGT_MULTI_PRIM_IB_RESET_INDX[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX[0]), 0, 0 },
+	{ "mmCB_BLEND_RED", REG_MMIO, 0xa105, &mmCB_BLEND_RED[0], sizeof(mmCB_BLEND_RED)/sizeof(mmCB_BLEND_RED[0]), 0, 0 },
+	{ "mmCB_BLEND_GREEN", REG_MMIO, 0xa106, &mmCB_BLEND_GREEN[0], sizeof(mmCB_BLEND_GREEN)/sizeof(mmCB_BLEND_GREEN[0]), 0, 0 },
+	{ "mmCB_BLEND_BLUE", REG_MMIO, 0xa107, &mmCB_BLEND_BLUE[0], sizeof(mmCB_BLEND_BLUE)/sizeof(mmCB_BLEND_BLUE[0]), 0, 0 },
+	{ "mmCB_BLEND_ALPHA", REG_MMIO, 0xa108, &mmCB_BLEND_ALPHA[0], sizeof(mmCB_BLEND_ALPHA)/sizeof(mmCB_BLEND_ALPHA[0]), 0, 0 },
+	{ "mmCB_DCC_CONTROL", REG_MMIO, 0xa109, &mmCB_DCC_CONTROL[0], sizeof(mmCB_DCC_CONTROL)/sizeof(mmCB_DCC_CONTROL[0]), 0, 0 },
+	{ "mmDB_STENCIL_CONTROL", REG_MMIO, 0xa10b, &mmDB_STENCIL_CONTROL[0], sizeof(mmDB_STENCIL_CONTROL)/sizeof(mmDB_STENCIL_CONTROL[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK", REG_MMIO, 0xa10c, &mmDB_STENCILREFMASK[0], sizeof(mmDB_STENCILREFMASK)/sizeof(mmDB_STENCILREFMASK[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK_BF", REG_MMIO, 0xa10d, &mmDB_STENCILREFMASK_BF[0], sizeof(mmDB_STENCILREFMASK_BF)/sizeof(mmDB_STENCILREFMASK_BF[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE", REG_MMIO, 0xa10f, &mmPA_CL_VPORT_XSCALE[0], sizeof(mmPA_CL_VPORT_XSCALE)/sizeof(mmPA_CL_VPORT_XSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET", REG_MMIO, 0xa110, &mmPA_CL_VPORT_XOFFSET[0], sizeof(mmPA_CL_VPORT_XOFFSET)/sizeof(mmPA_CL_VPORT_XOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE", REG_MMIO, 0xa111, &mmPA_CL_VPORT_YSCALE[0], sizeof(mmPA_CL_VPORT_YSCALE)/sizeof(mmPA_CL_VPORT_YSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET", REG_MMIO, 0xa112, &mmPA_CL_VPORT_YOFFSET[0], sizeof(mmPA_CL_VPORT_YOFFSET)/sizeof(mmPA_CL_VPORT_YOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE", REG_MMIO, 0xa113, &mmPA_CL_VPORT_ZSCALE[0], sizeof(mmPA_CL_VPORT_ZSCALE)/sizeof(mmPA_CL_VPORT_ZSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET", REG_MMIO, 0xa114, &mmPA_CL_VPORT_ZOFFSET[0], sizeof(mmPA_CL_VPORT_ZOFFSET)/sizeof(mmPA_CL_VPORT_ZOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_1", REG_MMIO, 0xa115, &mmPA_CL_VPORT_XSCALE_1[0], sizeof(mmPA_CL_VPORT_XSCALE_1)/sizeof(mmPA_CL_VPORT_XSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_1", REG_MMIO, 0xa116, &mmPA_CL_VPORT_XOFFSET_1[0], sizeof(mmPA_CL_VPORT_XOFFSET_1)/sizeof(mmPA_CL_VPORT_XOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_1", REG_MMIO, 0xa117, &mmPA_CL_VPORT_YSCALE_1[0], sizeof(mmPA_CL_VPORT_YSCALE_1)/sizeof(mmPA_CL_VPORT_YSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_1", REG_MMIO, 0xa118, &mmPA_CL_VPORT_YOFFSET_1[0], sizeof(mmPA_CL_VPORT_YOFFSET_1)/sizeof(mmPA_CL_VPORT_YOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_1", REG_MMIO, 0xa119, &mmPA_CL_VPORT_ZSCALE_1[0], sizeof(mmPA_CL_VPORT_ZSCALE_1)/sizeof(mmPA_CL_VPORT_ZSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_1", REG_MMIO, 0xa11a, &mmPA_CL_VPORT_ZOFFSET_1[0], sizeof(mmPA_CL_VPORT_ZOFFSET_1)/sizeof(mmPA_CL_VPORT_ZOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_2", REG_MMIO, 0xa11b, &mmPA_CL_VPORT_XSCALE_2[0], sizeof(mmPA_CL_VPORT_XSCALE_2)/sizeof(mmPA_CL_VPORT_XSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_2", REG_MMIO, 0xa11c, &mmPA_CL_VPORT_XOFFSET_2[0], sizeof(mmPA_CL_VPORT_XOFFSET_2)/sizeof(mmPA_CL_VPORT_XOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_2", REG_MMIO, 0xa11d, &mmPA_CL_VPORT_YSCALE_2[0], sizeof(mmPA_CL_VPORT_YSCALE_2)/sizeof(mmPA_CL_VPORT_YSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_2", REG_MMIO, 0xa11e, &mmPA_CL_VPORT_YOFFSET_2[0], sizeof(mmPA_CL_VPORT_YOFFSET_2)/sizeof(mmPA_CL_VPORT_YOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_2", REG_MMIO, 0xa11f, &mmPA_CL_VPORT_ZSCALE_2[0], sizeof(mmPA_CL_VPORT_ZSCALE_2)/sizeof(mmPA_CL_VPORT_ZSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_2", REG_MMIO, 0xa120, &mmPA_CL_VPORT_ZOFFSET_2[0], sizeof(mmPA_CL_VPORT_ZOFFSET_2)/sizeof(mmPA_CL_VPORT_ZOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_3", REG_MMIO, 0xa121, &mmPA_CL_VPORT_XSCALE_3[0], sizeof(mmPA_CL_VPORT_XSCALE_3)/sizeof(mmPA_CL_VPORT_XSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_3", REG_MMIO, 0xa122, &mmPA_CL_VPORT_XOFFSET_3[0], sizeof(mmPA_CL_VPORT_XOFFSET_3)/sizeof(mmPA_CL_VPORT_XOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_3", REG_MMIO, 0xa123, &mmPA_CL_VPORT_YSCALE_3[0], sizeof(mmPA_CL_VPORT_YSCALE_3)/sizeof(mmPA_CL_VPORT_YSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_3", REG_MMIO, 0xa124, &mmPA_CL_VPORT_YOFFSET_3[0], sizeof(mmPA_CL_VPORT_YOFFSET_3)/sizeof(mmPA_CL_VPORT_YOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_3", REG_MMIO, 0xa125, &mmPA_CL_VPORT_ZSCALE_3[0], sizeof(mmPA_CL_VPORT_ZSCALE_3)/sizeof(mmPA_CL_VPORT_ZSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_3", REG_MMIO, 0xa126, &mmPA_CL_VPORT_ZOFFSET_3[0], sizeof(mmPA_CL_VPORT_ZOFFSET_3)/sizeof(mmPA_CL_VPORT_ZOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_4", REG_MMIO, 0xa127, &mmPA_CL_VPORT_XSCALE_4[0], sizeof(mmPA_CL_VPORT_XSCALE_4)/sizeof(mmPA_CL_VPORT_XSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_4", REG_MMIO, 0xa128, &mmPA_CL_VPORT_XOFFSET_4[0], sizeof(mmPA_CL_VPORT_XOFFSET_4)/sizeof(mmPA_CL_VPORT_XOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_4", REG_MMIO, 0xa129, &mmPA_CL_VPORT_YSCALE_4[0], sizeof(mmPA_CL_VPORT_YSCALE_4)/sizeof(mmPA_CL_VPORT_YSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_4", REG_MMIO, 0xa12a, &mmPA_CL_VPORT_YOFFSET_4[0], sizeof(mmPA_CL_VPORT_YOFFSET_4)/sizeof(mmPA_CL_VPORT_YOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_4", REG_MMIO, 0xa12b, &mmPA_CL_VPORT_ZSCALE_4[0], sizeof(mmPA_CL_VPORT_ZSCALE_4)/sizeof(mmPA_CL_VPORT_ZSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_4", REG_MMIO, 0xa12c, &mmPA_CL_VPORT_ZOFFSET_4[0], sizeof(mmPA_CL_VPORT_ZOFFSET_4)/sizeof(mmPA_CL_VPORT_ZOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_5", REG_MMIO, 0xa12d, &mmPA_CL_VPORT_XSCALE_5[0], sizeof(mmPA_CL_VPORT_XSCALE_5)/sizeof(mmPA_CL_VPORT_XSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_5", REG_MMIO, 0xa12e, &mmPA_CL_VPORT_XOFFSET_5[0], sizeof(mmPA_CL_VPORT_XOFFSET_5)/sizeof(mmPA_CL_VPORT_XOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_5", REG_MMIO, 0xa12f, &mmPA_CL_VPORT_YSCALE_5[0], sizeof(mmPA_CL_VPORT_YSCALE_5)/sizeof(mmPA_CL_VPORT_YSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_5", REG_MMIO, 0xa130, &mmPA_CL_VPORT_YOFFSET_5[0], sizeof(mmPA_CL_VPORT_YOFFSET_5)/sizeof(mmPA_CL_VPORT_YOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_5", REG_MMIO, 0xa131, &mmPA_CL_VPORT_ZSCALE_5[0], sizeof(mmPA_CL_VPORT_ZSCALE_5)/sizeof(mmPA_CL_VPORT_ZSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_5", REG_MMIO, 0xa132, &mmPA_CL_VPORT_ZOFFSET_5[0], sizeof(mmPA_CL_VPORT_ZOFFSET_5)/sizeof(mmPA_CL_VPORT_ZOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_6", REG_MMIO, 0xa133, &mmPA_CL_VPORT_XSCALE_6[0], sizeof(mmPA_CL_VPORT_XSCALE_6)/sizeof(mmPA_CL_VPORT_XSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_6", REG_MMIO, 0xa134, &mmPA_CL_VPORT_XOFFSET_6[0], sizeof(mmPA_CL_VPORT_XOFFSET_6)/sizeof(mmPA_CL_VPORT_XOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_6", REG_MMIO, 0xa135, &mmPA_CL_VPORT_YSCALE_6[0], sizeof(mmPA_CL_VPORT_YSCALE_6)/sizeof(mmPA_CL_VPORT_YSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_6", REG_MMIO, 0xa136, &mmPA_CL_VPORT_YOFFSET_6[0], sizeof(mmPA_CL_VPORT_YOFFSET_6)/sizeof(mmPA_CL_VPORT_YOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_6", REG_MMIO, 0xa137, &mmPA_CL_VPORT_ZSCALE_6[0], sizeof(mmPA_CL_VPORT_ZSCALE_6)/sizeof(mmPA_CL_VPORT_ZSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_6", REG_MMIO, 0xa138, &mmPA_CL_VPORT_ZOFFSET_6[0], sizeof(mmPA_CL_VPORT_ZOFFSET_6)/sizeof(mmPA_CL_VPORT_ZOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_7", REG_MMIO, 0xa139, &mmPA_CL_VPORT_XSCALE_7[0], sizeof(mmPA_CL_VPORT_XSCALE_7)/sizeof(mmPA_CL_VPORT_XSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_7", REG_MMIO, 0xa13a, &mmPA_CL_VPORT_XOFFSET_7[0], sizeof(mmPA_CL_VPORT_XOFFSET_7)/sizeof(mmPA_CL_VPORT_XOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_7", REG_MMIO, 0xa13b, &mmPA_CL_VPORT_YSCALE_7[0], sizeof(mmPA_CL_VPORT_YSCALE_7)/sizeof(mmPA_CL_VPORT_YSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_7", REG_MMIO, 0xa13c, &mmPA_CL_VPORT_YOFFSET_7[0], sizeof(mmPA_CL_VPORT_YOFFSET_7)/sizeof(mmPA_CL_VPORT_YOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_7", REG_MMIO, 0xa13d, &mmPA_CL_VPORT_ZSCALE_7[0], sizeof(mmPA_CL_VPORT_ZSCALE_7)/sizeof(mmPA_CL_VPORT_ZSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_7", REG_MMIO, 0xa13e, &mmPA_CL_VPORT_ZOFFSET_7[0], sizeof(mmPA_CL_VPORT_ZOFFSET_7)/sizeof(mmPA_CL_VPORT_ZOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_8", REG_MMIO, 0xa13f, &mmPA_CL_VPORT_XSCALE_8[0], sizeof(mmPA_CL_VPORT_XSCALE_8)/sizeof(mmPA_CL_VPORT_XSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_8", REG_MMIO, 0xa140, &mmPA_CL_VPORT_XOFFSET_8[0], sizeof(mmPA_CL_VPORT_XOFFSET_8)/sizeof(mmPA_CL_VPORT_XOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_8", REG_MMIO, 0xa141, &mmPA_CL_VPORT_YSCALE_8[0], sizeof(mmPA_CL_VPORT_YSCALE_8)/sizeof(mmPA_CL_VPORT_YSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_8", REG_MMIO, 0xa142, &mmPA_CL_VPORT_YOFFSET_8[0], sizeof(mmPA_CL_VPORT_YOFFSET_8)/sizeof(mmPA_CL_VPORT_YOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_8", REG_MMIO, 0xa143, &mmPA_CL_VPORT_ZSCALE_8[0], sizeof(mmPA_CL_VPORT_ZSCALE_8)/sizeof(mmPA_CL_VPORT_ZSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_8", REG_MMIO, 0xa144, &mmPA_CL_VPORT_ZOFFSET_8[0], sizeof(mmPA_CL_VPORT_ZOFFSET_8)/sizeof(mmPA_CL_VPORT_ZOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_9", REG_MMIO, 0xa145, &mmPA_CL_VPORT_XSCALE_9[0], sizeof(mmPA_CL_VPORT_XSCALE_9)/sizeof(mmPA_CL_VPORT_XSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_9", REG_MMIO, 0xa146, &mmPA_CL_VPORT_XOFFSET_9[0], sizeof(mmPA_CL_VPORT_XOFFSET_9)/sizeof(mmPA_CL_VPORT_XOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_9", REG_MMIO, 0xa147, &mmPA_CL_VPORT_YSCALE_9[0], sizeof(mmPA_CL_VPORT_YSCALE_9)/sizeof(mmPA_CL_VPORT_YSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_9", REG_MMIO, 0xa148, &mmPA_CL_VPORT_YOFFSET_9[0], sizeof(mmPA_CL_VPORT_YOFFSET_9)/sizeof(mmPA_CL_VPORT_YOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_9", REG_MMIO, 0xa149, &mmPA_CL_VPORT_ZSCALE_9[0], sizeof(mmPA_CL_VPORT_ZSCALE_9)/sizeof(mmPA_CL_VPORT_ZSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_9", REG_MMIO, 0xa14a, &mmPA_CL_VPORT_ZOFFSET_9[0], sizeof(mmPA_CL_VPORT_ZOFFSET_9)/sizeof(mmPA_CL_VPORT_ZOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_10", REG_MMIO, 0xa14b, &mmPA_CL_VPORT_XSCALE_10[0], sizeof(mmPA_CL_VPORT_XSCALE_10)/sizeof(mmPA_CL_VPORT_XSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_10", REG_MMIO, 0xa14c, &mmPA_CL_VPORT_XOFFSET_10[0], sizeof(mmPA_CL_VPORT_XOFFSET_10)/sizeof(mmPA_CL_VPORT_XOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_10", REG_MMIO, 0xa14d, &mmPA_CL_VPORT_YSCALE_10[0], sizeof(mmPA_CL_VPORT_YSCALE_10)/sizeof(mmPA_CL_VPORT_YSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_10", REG_MMIO, 0xa14e, &mmPA_CL_VPORT_YOFFSET_10[0], sizeof(mmPA_CL_VPORT_YOFFSET_10)/sizeof(mmPA_CL_VPORT_YOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_10", REG_MMIO, 0xa14f, &mmPA_CL_VPORT_ZSCALE_10[0], sizeof(mmPA_CL_VPORT_ZSCALE_10)/sizeof(mmPA_CL_VPORT_ZSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_10", REG_MMIO, 0xa150, &mmPA_CL_VPORT_ZOFFSET_10[0], sizeof(mmPA_CL_VPORT_ZOFFSET_10)/sizeof(mmPA_CL_VPORT_ZOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_11", REG_MMIO, 0xa151, &mmPA_CL_VPORT_XSCALE_11[0], sizeof(mmPA_CL_VPORT_XSCALE_11)/sizeof(mmPA_CL_VPORT_XSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_11", REG_MMIO, 0xa152, &mmPA_CL_VPORT_XOFFSET_11[0], sizeof(mmPA_CL_VPORT_XOFFSET_11)/sizeof(mmPA_CL_VPORT_XOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_11", REG_MMIO, 0xa153, &mmPA_CL_VPORT_YSCALE_11[0], sizeof(mmPA_CL_VPORT_YSCALE_11)/sizeof(mmPA_CL_VPORT_YSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_11", REG_MMIO, 0xa154, &mmPA_CL_VPORT_YOFFSET_11[0], sizeof(mmPA_CL_VPORT_YOFFSET_11)/sizeof(mmPA_CL_VPORT_YOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_11", REG_MMIO, 0xa155, &mmPA_CL_VPORT_ZSCALE_11[0], sizeof(mmPA_CL_VPORT_ZSCALE_11)/sizeof(mmPA_CL_VPORT_ZSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_11", REG_MMIO, 0xa156, &mmPA_CL_VPORT_ZOFFSET_11[0], sizeof(mmPA_CL_VPORT_ZOFFSET_11)/sizeof(mmPA_CL_VPORT_ZOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_12", REG_MMIO, 0xa157, &mmPA_CL_VPORT_XSCALE_12[0], sizeof(mmPA_CL_VPORT_XSCALE_12)/sizeof(mmPA_CL_VPORT_XSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_12", REG_MMIO, 0xa158, &mmPA_CL_VPORT_XOFFSET_12[0], sizeof(mmPA_CL_VPORT_XOFFSET_12)/sizeof(mmPA_CL_VPORT_XOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_12", REG_MMIO, 0xa159, &mmPA_CL_VPORT_YSCALE_12[0], sizeof(mmPA_CL_VPORT_YSCALE_12)/sizeof(mmPA_CL_VPORT_YSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_12", REG_MMIO, 0xa15a, &mmPA_CL_VPORT_YOFFSET_12[0], sizeof(mmPA_CL_VPORT_YOFFSET_12)/sizeof(mmPA_CL_VPORT_YOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_12", REG_MMIO, 0xa15b, &mmPA_CL_VPORT_ZSCALE_12[0], sizeof(mmPA_CL_VPORT_ZSCALE_12)/sizeof(mmPA_CL_VPORT_ZSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_12", REG_MMIO, 0xa15c, &mmPA_CL_VPORT_ZOFFSET_12[0], sizeof(mmPA_CL_VPORT_ZOFFSET_12)/sizeof(mmPA_CL_VPORT_ZOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_13", REG_MMIO, 0xa15d, &mmPA_CL_VPORT_XSCALE_13[0], sizeof(mmPA_CL_VPORT_XSCALE_13)/sizeof(mmPA_CL_VPORT_XSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_13", REG_MMIO, 0xa15e, &mmPA_CL_VPORT_XOFFSET_13[0], sizeof(mmPA_CL_VPORT_XOFFSET_13)/sizeof(mmPA_CL_VPORT_XOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_13", REG_MMIO, 0xa15f, &mmPA_CL_VPORT_YSCALE_13[0], sizeof(mmPA_CL_VPORT_YSCALE_13)/sizeof(mmPA_CL_VPORT_YSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_13", REG_MMIO, 0xa160, &mmPA_CL_VPORT_YOFFSET_13[0], sizeof(mmPA_CL_VPORT_YOFFSET_13)/sizeof(mmPA_CL_VPORT_YOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_13", REG_MMIO, 0xa161, &mmPA_CL_VPORT_ZSCALE_13[0], sizeof(mmPA_CL_VPORT_ZSCALE_13)/sizeof(mmPA_CL_VPORT_ZSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_13", REG_MMIO, 0xa162, &mmPA_CL_VPORT_ZOFFSET_13[0], sizeof(mmPA_CL_VPORT_ZOFFSET_13)/sizeof(mmPA_CL_VPORT_ZOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_14", REG_MMIO, 0xa163, &mmPA_CL_VPORT_XSCALE_14[0], sizeof(mmPA_CL_VPORT_XSCALE_14)/sizeof(mmPA_CL_VPORT_XSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_14", REG_MMIO, 0xa164, &mmPA_CL_VPORT_XOFFSET_14[0], sizeof(mmPA_CL_VPORT_XOFFSET_14)/sizeof(mmPA_CL_VPORT_XOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_14", REG_MMIO, 0xa165, &mmPA_CL_VPORT_YSCALE_14[0], sizeof(mmPA_CL_VPORT_YSCALE_14)/sizeof(mmPA_CL_VPORT_YSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_14", REG_MMIO, 0xa166, &mmPA_CL_VPORT_YOFFSET_14[0], sizeof(mmPA_CL_VPORT_YOFFSET_14)/sizeof(mmPA_CL_VPORT_YOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_14", REG_MMIO, 0xa167, &mmPA_CL_VPORT_ZSCALE_14[0], sizeof(mmPA_CL_VPORT_ZSCALE_14)/sizeof(mmPA_CL_VPORT_ZSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_14", REG_MMIO, 0xa168, &mmPA_CL_VPORT_ZOFFSET_14[0], sizeof(mmPA_CL_VPORT_ZOFFSET_14)/sizeof(mmPA_CL_VPORT_ZOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_15", REG_MMIO, 0xa169, &mmPA_CL_VPORT_XSCALE_15[0], sizeof(mmPA_CL_VPORT_XSCALE_15)/sizeof(mmPA_CL_VPORT_XSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_15", REG_MMIO, 0xa16a, &mmPA_CL_VPORT_XOFFSET_15[0], sizeof(mmPA_CL_VPORT_XOFFSET_15)/sizeof(mmPA_CL_VPORT_XOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_15", REG_MMIO, 0xa16b, &mmPA_CL_VPORT_YSCALE_15[0], sizeof(mmPA_CL_VPORT_YSCALE_15)/sizeof(mmPA_CL_VPORT_YSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_15", REG_MMIO, 0xa16c, &mmPA_CL_VPORT_YOFFSET_15[0], sizeof(mmPA_CL_VPORT_YOFFSET_15)/sizeof(mmPA_CL_VPORT_YOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_15", REG_MMIO, 0xa16d, &mmPA_CL_VPORT_ZSCALE_15[0], sizeof(mmPA_CL_VPORT_ZSCALE_15)/sizeof(mmPA_CL_VPORT_ZSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_15", REG_MMIO, 0xa16e, &mmPA_CL_VPORT_ZOFFSET_15[0], sizeof(mmPA_CL_VPORT_ZOFFSET_15)/sizeof(mmPA_CL_VPORT_ZOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_X", REG_MMIO, 0xa16f, &mmPA_CL_UCP_0_X[0], sizeof(mmPA_CL_UCP_0_X)/sizeof(mmPA_CL_UCP_0_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Y", REG_MMIO, 0xa170, &mmPA_CL_UCP_0_Y[0], sizeof(mmPA_CL_UCP_0_Y)/sizeof(mmPA_CL_UCP_0_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Z", REG_MMIO, 0xa171, &mmPA_CL_UCP_0_Z[0], sizeof(mmPA_CL_UCP_0_Z)/sizeof(mmPA_CL_UCP_0_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_W", REG_MMIO, 0xa172, &mmPA_CL_UCP_0_W[0], sizeof(mmPA_CL_UCP_0_W)/sizeof(mmPA_CL_UCP_0_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_X", REG_MMIO, 0xa173, &mmPA_CL_UCP_1_X[0], sizeof(mmPA_CL_UCP_1_X)/sizeof(mmPA_CL_UCP_1_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Y", REG_MMIO, 0xa174, &mmPA_CL_UCP_1_Y[0], sizeof(mmPA_CL_UCP_1_Y)/sizeof(mmPA_CL_UCP_1_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Z", REG_MMIO, 0xa175, &mmPA_CL_UCP_1_Z[0], sizeof(mmPA_CL_UCP_1_Z)/sizeof(mmPA_CL_UCP_1_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_W", REG_MMIO, 0xa176, &mmPA_CL_UCP_1_W[0], sizeof(mmPA_CL_UCP_1_W)/sizeof(mmPA_CL_UCP_1_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_X", REG_MMIO, 0xa177, &mmPA_CL_UCP_2_X[0], sizeof(mmPA_CL_UCP_2_X)/sizeof(mmPA_CL_UCP_2_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Y", REG_MMIO, 0xa178, &mmPA_CL_UCP_2_Y[0], sizeof(mmPA_CL_UCP_2_Y)/sizeof(mmPA_CL_UCP_2_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Z", REG_MMIO, 0xa179, &mmPA_CL_UCP_2_Z[0], sizeof(mmPA_CL_UCP_2_Z)/sizeof(mmPA_CL_UCP_2_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_W", REG_MMIO, 0xa17a, &mmPA_CL_UCP_2_W[0], sizeof(mmPA_CL_UCP_2_W)/sizeof(mmPA_CL_UCP_2_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_X", REG_MMIO, 0xa17b, &mmPA_CL_UCP_3_X[0], sizeof(mmPA_CL_UCP_3_X)/sizeof(mmPA_CL_UCP_3_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Y", REG_MMIO, 0xa17c, &mmPA_CL_UCP_3_Y[0], sizeof(mmPA_CL_UCP_3_Y)/sizeof(mmPA_CL_UCP_3_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Z", REG_MMIO, 0xa17d, &mmPA_CL_UCP_3_Z[0], sizeof(mmPA_CL_UCP_3_Z)/sizeof(mmPA_CL_UCP_3_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_W", REG_MMIO, 0xa17e, &mmPA_CL_UCP_3_W[0], sizeof(mmPA_CL_UCP_3_W)/sizeof(mmPA_CL_UCP_3_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_X", REG_MMIO, 0xa17f, &mmPA_CL_UCP_4_X[0], sizeof(mmPA_CL_UCP_4_X)/sizeof(mmPA_CL_UCP_4_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Y", REG_MMIO, 0xa180, &mmPA_CL_UCP_4_Y[0], sizeof(mmPA_CL_UCP_4_Y)/sizeof(mmPA_CL_UCP_4_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Z", REG_MMIO, 0xa181, &mmPA_CL_UCP_4_Z[0], sizeof(mmPA_CL_UCP_4_Z)/sizeof(mmPA_CL_UCP_4_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_W", REG_MMIO, 0xa182, &mmPA_CL_UCP_4_W[0], sizeof(mmPA_CL_UCP_4_W)/sizeof(mmPA_CL_UCP_4_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_X", REG_MMIO, 0xa183, &mmPA_CL_UCP_5_X[0], sizeof(mmPA_CL_UCP_5_X)/sizeof(mmPA_CL_UCP_5_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Y", REG_MMIO, 0xa184, &mmPA_CL_UCP_5_Y[0], sizeof(mmPA_CL_UCP_5_Y)/sizeof(mmPA_CL_UCP_5_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Z", REG_MMIO, 0xa185, &mmPA_CL_UCP_5_Z[0], sizeof(mmPA_CL_UCP_5_Z)/sizeof(mmPA_CL_UCP_5_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_W", REG_MMIO, 0xa186, &mmPA_CL_UCP_5_W[0], sizeof(mmPA_CL_UCP_5_W)/sizeof(mmPA_CL_UCP_5_W[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_0", REG_MMIO, 0xa191, &mmSPI_PS_INPUT_CNTL_0[0], sizeof(mmSPI_PS_INPUT_CNTL_0)/sizeof(mmSPI_PS_INPUT_CNTL_0[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_1", REG_MMIO, 0xa192, &mmSPI_PS_INPUT_CNTL_1[0], sizeof(mmSPI_PS_INPUT_CNTL_1)/sizeof(mmSPI_PS_INPUT_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_2", REG_MMIO, 0xa193, &mmSPI_PS_INPUT_CNTL_2[0], sizeof(mmSPI_PS_INPUT_CNTL_2)/sizeof(mmSPI_PS_INPUT_CNTL_2[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_3", REG_MMIO, 0xa194, &mmSPI_PS_INPUT_CNTL_3[0], sizeof(mmSPI_PS_INPUT_CNTL_3)/sizeof(mmSPI_PS_INPUT_CNTL_3[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_4", REG_MMIO, 0xa195, &mmSPI_PS_INPUT_CNTL_4[0], sizeof(mmSPI_PS_INPUT_CNTL_4)/sizeof(mmSPI_PS_INPUT_CNTL_4[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_5", REG_MMIO, 0xa196, &mmSPI_PS_INPUT_CNTL_5[0], sizeof(mmSPI_PS_INPUT_CNTL_5)/sizeof(mmSPI_PS_INPUT_CNTL_5[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_6", REG_MMIO, 0xa197, &mmSPI_PS_INPUT_CNTL_6[0], sizeof(mmSPI_PS_INPUT_CNTL_6)/sizeof(mmSPI_PS_INPUT_CNTL_6[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_7", REG_MMIO, 0xa198, &mmSPI_PS_INPUT_CNTL_7[0], sizeof(mmSPI_PS_INPUT_CNTL_7)/sizeof(mmSPI_PS_INPUT_CNTL_7[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_8", REG_MMIO, 0xa199, &mmSPI_PS_INPUT_CNTL_8[0], sizeof(mmSPI_PS_INPUT_CNTL_8)/sizeof(mmSPI_PS_INPUT_CNTL_8[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_9", REG_MMIO, 0xa19a, &mmSPI_PS_INPUT_CNTL_9[0], sizeof(mmSPI_PS_INPUT_CNTL_9)/sizeof(mmSPI_PS_INPUT_CNTL_9[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_10", REG_MMIO, 0xa19b, &mmSPI_PS_INPUT_CNTL_10[0], sizeof(mmSPI_PS_INPUT_CNTL_10)/sizeof(mmSPI_PS_INPUT_CNTL_10[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_11", REG_MMIO, 0xa19c, &mmSPI_PS_INPUT_CNTL_11[0], sizeof(mmSPI_PS_INPUT_CNTL_11)/sizeof(mmSPI_PS_INPUT_CNTL_11[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_12", REG_MMIO, 0xa19d, &mmSPI_PS_INPUT_CNTL_12[0], sizeof(mmSPI_PS_INPUT_CNTL_12)/sizeof(mmSPI_PS_INPUT_CNTL_12[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_13", REG_MMIO, 0xa19e, &mmSPI_PS_INPUT_CNTL_13[0], sizeof(mmSPI_PS_INPUT_CNTL_13)/sizeof(mmSPI_PS_INPUT_CNTL_13[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_14", REG_MMIO, 0xa19f, &mmSPI_PS_INPUT_CNTL_14[0], sizeof(mmSPI_PS_INPUT_CNTL_14)/sizeof(mmSPI_PS_INPUT_CNTL_14[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_15", REG_MMIO, 0xa1a0, &mmSPI_PS_INPUT_CNTL_15[0], sizeof(mmSPI_PS_INPUT_CNTL_15)/sizeof(mmSPI_PS_INPUT_CNTL_15[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_16", REG_MMIO, 0xa1a1, &mmSPI_PS_INPUT_CNTL_16[0], sizeof(mmSPI_PS_INPUT_CNTL_16)/sizeof(mmSPI_PS_INPUT_CNTL_16[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_17", REG_MMIO, 0xa1a2, &mmSPI_PS_INPUT_CNTL_17[0], sizeof(mmSPI_PS_INPUT_CNTL_17)/sizeof(mmSPI_PS_INPUT_CNTL_17[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_18", REG_MMIO, 0xa1a3, &mmSPI_PS_INPUT_CNTL_18[0], sizeof(mmSPI_PS_INPUT_CNTL_18)/sizeof(mmSPI_PS_INPUT_CNTL_18[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_19", REG_MMIO, 0xa1a4, &mmSPI_PS_INPUT_CNTL_19[0], sizeof(mmSPI_PS_INPUT_CNTL_19)/sizeof(mmSPI_PS_INPUT_CNTL_19[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_20", REG_MMIO, 0xa1a5, &mmSPI_PS_INPUT_CNTL_20[0], sizeof(mmSPI_PS_INPUT_CNTL_20)/sizeof(mmSPI_PS_INPUT_CNTL_20[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_21", REG_MMIO, 0xa1a6, &mmSPI_PS_INPUT_CNTL_21[0], sizeof(mmSPI_PS_INPUT_CNTL_21)/sizeof(mmSPI_PS_INPUT_CNTL_21[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_22", REG_MMIO, 0xa1a7, &mmSPI_PS_INPUT_CNTL_22[0], sizeof(mmSPI_PS_INPUT_CNTL_22)/sizeof(mmSPI_PS_INPUT_CNTL_22[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_23", REG_MMIO, 0xa1a8, &mmSPI_PS_INPUT_CNTL_23[0], sizeof(mmSPI_PS_INPUT_CNTL_23)/sizeof(mmSPI_PS_INPUT_CNTL_23[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_24", REG_MMIO, 0xa1a9, &mmSPI_PS_INPUT_CNTL_24[0], sizeof(mmSPI_PS_INPUT_CNTL_24)/sizeof(mmSPI_PS_INPUT_CNTL_24[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_25", REG_MMIO, 0xa1aa, &mmSPI_PS_INPUT_CNTL_25[0], sizeof(mmSPI_PS_INPUT_CNTL_25)/sizeof(mmSPI_PS_INPUT_CNTL_25[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_26", REG_MMIO, 0xa1ab, &mmSPI_PS_INPUT_CNTL_26[0], sizeof(mmSPI_PS_INPUT_CNTL_26)/sizeof(mmSPI_PS_INPUT_CNTL_26[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_27", REG_MMIO, 0xa1ac, &mmSPI_PS_INPUT_CNTL_27[0], sizeof(mmSPI_PS_INPUT_CNTL_27)/sizeof(mmSPI_PS_INPUT_CNTL_27[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_28", REG_MMIO, 0xa1ad, &mmSPI_PS_INPUT_CNTL_28[0], sizeof(mmSPI_PS_INPUT_CNTL_28)/sizeof(mmSPI_PS_INPUT_CNTL_28[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_29", REG_MMIO, 0xa1ae, &mmSPI_PS_INPUT_CNTL_29[0], sizeof(mmSPI_PS_INPUT_CNTL_29)/sizeof(mmSPI_PS_INPUT_CNTL_29[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_30", REG_MMIO, 0xa1af, &mmSPI_PS_INPUT_CNTL_30[0], sizeof(mmSPI_PS_INPUT_CNTL_30)/sizeof(mmSPI_PS_INPUT_CNTL_30[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_31", REG_MMIO, 0xa1b0, &mmSPI_PS_INPUT_CNTL_31[0], sizeof(mmSPI_PS_INPUT_CNTL_31)/sizeof(mmSPI_PS_INPUT_CNTL_31[0]), 0, 0 },
+	{ "mmSPI_VS_OUT_CONFIG", REG_MMIO, 0xa1b1, &mmSPI_VS_OUT_CONFIG[0], sizeof(mmSPI_VS_OUT_CONFIG)/sizeof(mmSPI_VS_OUT_CONFIG[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ENA", REG_MMIO, 0xa1b3, &mmSPI_PS_INPUT_ENA[0], sizeof(mmSPI_PS_INPUT_ENA)/sizeof(mmSPI_PS_INPUT_ENA[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ADDR", REG_MMIO, 0xa1b4, &mmSPI_PS_INPUT_ADDR[0], sizeof(mmSPI_PS_INPUT_ADDR)/sizeof(mmSPI_PS_INPUT_ADDR[0]), 0, 0 },
+	{ "mmSPI_INTERP_CONTROL_0", REG_MMIO, 0xa1b5, &mmSPI_INTERP_CONTROL_0[0], sizeof(mmSPI_INTERP_CONTROL_0)/sizeof(mmSPI_INTERP_CONTROL_0[0]), 0, 0 },
+	{ "mmSPI_PS_IN_CONTROL", REG_MMIO, 0xa1b6, &mmSPI_PS_IN_CONTROL[0], sizeof(mmSPI_PS_IN_CONTROL)/sizeof(mmSPI_PS_IN_CONTROL[0]), 0, 0 },
+	{ "mmSPI_BARYC_CNTL", REG_MMIO, 0xa1b8, &mmSPI_BARYC_CNTL[0], sizeof(mmSPI_BARYC_CNTL)/sizeof(mmSPI_BARYC_CNTL[0]), 0, 0 },
+	{ "mmSPI_TMPRING_SIZE", REG_MMIO, 0xa1ba, &mmSPI_TMPRING_SIZE[0], sizeof(mmSPI_TMPRING_SIZE)/sizeof(mmSPI_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmSPI_SHADER_POS_FORMAT", REG_MMIO, 0xa1c3, &mmSPI_SHADER_POS_FORMAT[0], sizeof(mmSPI_SHADER_POS_FORMAT)/sizeof(mmSPI_SHADER_POS_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_Z_FORMAT", REG_MMIO, 0xa1c4, &mmSPI_SHADER_Z_FORMAT[0], sizeof(mmSPI_SHADER_Z_FORMAT)/sizeof(mmSPI_SHADER_Z_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_COL_FORMAT", REG_MMIO, 0xa1c5, &mmSPI_SHADER_COL_FORMAT[0], sizeof(mmSPI_SHADER_COL_FORMAT)/sizeof(mmSPI_SHADER_COL_FORMAT[0]), 0, 0 },
+	{ "mmCB_BLEND0_CONTROL", REG_MMIO, 0xa1e0, &mmCB_BLEND0_CONTROL[0], sizeof(mmCB_BLEND0_CONTROL)/sizeof(mmCB_BLEND0_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND1_CONTROL", REG_MMIO, 0xa1e1, &mmCB_BLEND1_CONTROL[0], sizeof(mmCB_BLEND1_CONTROL)/sizeof(mmCB_BLEND1_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND2_CONTROL", REG_MMIO, 0xa1e2, &mmCB_BLEND2_CONTROL[0], sizeof(mmCB_BLEND2_CONTROL)/sizeof(mmCB_BLEND2_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND3_CONTROL", REG_MMIO, 0xa1e3, &mmCB_BLEND3_CONTROL[0], sizeof(mmCB_BLEND3_CONTROL)/sizeof(mmCB_BLEND3_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND4_CONTROL", REG_MMIO, 0xa1e4, &mmCB_BLEND4_CONTROL[0], sizeof(mmCB_BLEND4_CONTROL)/sizeof(mmCB_BLEND4_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND5_CONTROL", REG_MMIO, 0xa1e5, &mmCB_BLEND5_CONTROL[0], sizeof(mmCB_BLEND5_CONTROL)/sizeof(mmCB_BLEND5_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND6_CONTROL", REG_MMIO, 0xa1e6, &mmCB_BLEND6_CONTROL[0], sizeof(mmCB_BLEND6_CONTROL)/sizeof(mmCB_BLEND6_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND7_CONTROL", REG_MMIO, 0xa1e7, &mmCB_BLEND7_CONTROL[0], sizeof(mmCB_BLEND7_CONTROL)/sizeof(mmCB_BLEND7_CONTROL[0]), 0, 0 },
+	{ "mmCS_COPY_STATE", REG_MMIO, 0xa1f3, &mmCS_COPY_STATE[0], sizeof(mmCS_COPY_STATE)/sizeof(mmCS_COPY_STATE[0]), 0, 0 },
+	{ "mmGFX_COPY_STATE", REG_MMIO, 0xa1f4, &mmGFX_COPY_STATE[0], sizeof(mmGFX_COPY_STATE)/sizeof(mmGFX_COPY_STATE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_X_RAD", REG_MMIO, 0xa1f5, &mmPA_CL_POINT_X_RAD[0], sizeof(mmPA_CL_POINT_X_RAD)/sizeof(mmPA_CL_POINT_X_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_Y_RAD", REG_MMIO, 0xa1f6, &mmPA_CL_POINT_Y_RAD[0], sizeof(mmPA_CL_POINT_Y_RAD)/sizeof(mmPA_CL_POINT_Y_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_SIZE", REG_MMIO, 0xa1f7, &mmPA_CL_POINT_SIZE[0], sizeof(mmPA_CL_POINT_SIZE)/sizeof(mmPA_CL_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_CULL_RAD", REG_MMIO, 0xa1f8, &mmPA_CL_POINT_CULL_RAD[0], sizeof(mmPA_CL_POINT_CULL_RAD)/sizeof(mmPA_CL_POINT_CULL_RAD[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE_HI", REG_MMIO, 0xa1f9, &mmVGT_DMA_BASE_HI[0], sizeof(mmVGT_DMA_BASE_HI)/sizeof(mmVGT_DMA_BASE_HI[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE", REG_MMIO, 0xa1fa, &mmVGT_DMA_BASE[0], sizeof(mmVGT_DMA_BASE)/sizeof(mmVGT_DMA_BASE[0]), 0, 0 },
+	{ "mmVGT_DRAW_INITIATOR", REG_MMIO, 0xa1fc, &mmVGT_DRAW_INITIATOR[0], sizeof(mmVGT_DRAW_INITIATOR)/sizeof(mmVGT_DRAW_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_IMMED_DATA", REG_MMIO, 0xa1fd, &mmVGT_IMMED_DATA[0], sizeof(mmVGT_IMMED_DATA)/sizeof(mmVGT_IMMED_DATA[0]), 0, 0 },
+	{ "mmVGT_EVENT_ADDRESS_REG", REG_MMIO, 0xa1fe, &mmVGT_EVENT_ADDRESS_REG[0], sizeof(mmVGT_EVENT_ADDRESS_REG)/sizeof(mmVGT_EVENT_ADDRESS_REG[0]), 0, 0 },
+	{ "mmDB_DEPTH_CONTROL", REG_MMIO, 0xa200, &mmDB_DEPTH_CONTROL[0], sizeof(mmDB_DEPTH_CONTROL)/sizeof(mmDB_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmDB_EQAA", REG_MMIO, 0xa201, &mmDB_EQAA[0], sizeof(mmDB_EQAA)/sizeof(mmDB_EQAA[0]), 0, 0 },
+	{ "mmCB_COLOR_CONTROL", REG_MMIO, 0xa202, &mmCB_COLOR_CONTROL[0], sizeof(mmCB_COLOR_CONTROL)/sizeof(mmCB_COLOR_CONTROL[0]), 0, 0 },
+	{ "mmDB_SHADER_CONTROL", REG_MMIO, 0xa203, &mmDB_SHADER_CONTROL[0], sizeof(mmDB_SHADER_CONTROL)/sizeof(mmDB_SHADER_CONTROL[0]), 0, 0 },
+	{ "mmPA_CL_CLIP_CNTL", REG_MMIO, 0xa204, &mmPA_CL_CLIP_CNTL[0], sizeof(mmPA_CL_CLIP_CNTL)/sizeof(mmPA_CL_CLIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_SC_MODE_CNTL", REG_MMIO, 0xa205, &mmPA_SU_SC_MODE_CNTL[0], sizeof(mmPA_SU_SC_MODE_CNTL)/sizeof(mmPA_SU_SC_MODE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VTE_CNTL", REG_MMIO, 0xa206, &mmPA_CL_VTE_CNTL[0], sizeof(mmPA_CL_VTE_CNTL)/sizeof(mmPA_CL_VTE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VS_OUT_CNTL", REG_MMIO, 0xa207, &mmPA_CL_VS_OUT_CNTL[0], sizeof(mmPA_CL_VS_OUT_CNTL)/sizeof(mmPA_CL_VS_OUT_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_NANINF_CNTL", REG_MMIO, 0xa208, &mmPA_CL_NANINF_CNTL[0], sizeof(mmPA_CL_NANINF_CNTL)/sizeof(mmPA_CL_NANINF_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_CNTL", REG_MMIO, 0xa209, &mmPA_SU_LINE_STIPPLE_CNTL[0], sizeof(mmPA_SU_LINE_STIPPLE_CNTL)/sizeof(mmPA_SU_LINE_STIPPLE_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_SCALE", REG_MMIO, 0xa20a, &mmPA_SU_LINE_STIPPLE_SCALE[0], sizeof(mmPA_SU_LINE_STIPPLE_SCALE)/sizeof(mmPA_SU_LINE_STIPPLE_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_PRIM_FILTER_CNTL", REG_MMIO, 0xa20b, &mmPA_SU_PRIM_FILTER_CNTL[0], sizeof(mmPA_SU_PRIM_FILTER_CNTL)/sizeof(mmPA_SU_PRIM_FILTER_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POINT_SIZE", REG_MMIO, 0xa280, &mmPA_SU_POINT_SIZE[0], sizeof(mmPA_SU_POINT_SIZE)/sizeof(mmPA_SU_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_SU_POINT_MINMAX", REG_MMIO, 0xa281, &mmPA_SU_POINT_MINMAX[0], sizeof(mmPA_SU_POINT_MINMAX)/sizeof(mmPA_SU_POINT_MINMAX[0]), 0, 0 },
+	{ "mmPA_SU_LINE_CNTL", REG_MMIO, 0xa282, &mmPA_SU_LINE_CNTL[0], sizeof(mmPA_SU_LINE_CNTL)/sizeof(mmPA_SU_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE", REG_MMIO, 0xa283, &mmPA_SC_LINE_STIPPLE[0], sizeof(mmPA_SC_LINE_STIPPLE)/sizeof(mmPA_SC_LINE_STIPPLE[0]), 0, 0 },
+	{ "mmVGT_OUTPUT_PATH_CNTL", REG_MMIO, 0xa284, &mmVGT_OUTPUT_PATH_CNTL[0], sizeof(mmVGT_OUTPUT_PATH_CNTL)/sizeof(mmVGT_OUTPUT_PATH_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_CNTL", REG_MMIO, 0xa285, &mmVGT_HOS_CNTL[0], sizeof(mmVGT_HOS_CNTL)/sizeof(mmVGT_HOS_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_MAX_TESS_LEVEL", REG_MMIO, 0xa286, &mmVGT_HOS_MAX_TESS_LEVEL[0], sizeof(mmVGT_HOS_MAX_TESS_LEVEL)/sizeof(mmVGT_HOS_MAX_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_MIN_TESS_LEVEL", REG_MMIO, 0xa287, &mmVGT_HOS_MIN_TESS_LEVEL[0], sizeof(mmVGT_HOS_MIN_TESS_LEVEL)/sizeof(mmVGT_HOS_MIN_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_REUSE_DEPTH", REG_MMIO, 0xa288, &mmVGT_HOS_REUSE_DEPTH[0], sizeof(mmVGT_HOS_REUSE_DEPTH)/sizeof(mmVGT_HOS_REUSE_DEPTH[0]), 0, 0 },
+	{ "mmVGT_GROUP_PRIM_TYPE", REG_MMIO, 0xa289, &mmVGT_GROUP_PRIM_TYPE[0], sizeof(mmVGT_GROUP_PRIM_TYPE)/sizeof(mmVGT_GROUP_PRIM_TYPE[0]), 0, 0 },
+	{ "mmVGT_GROUP_FIRST_DECR", REG_MMIO, 0xa28a, &mmVGT_GROUP_FIRST_DECR[0], sizeof(mmVGT_GROUP_FIRST_DECR)/sizeof(mmVGT_GROUP_FIRST_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_DECR", REG_MMIO, 0xa28b, &mmVGT_GROUP_DECR[0], sizeof(mmVGT_GROUP_DECR)/sizeof(mmVGT_GROUP_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_CNTL", REG_MMIO, 0xa28c, &mmVGT_GROUP_VECT_0_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_CNTL)/sizeof(mmVGT_GROUP_VECT_0_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_CNTL", REG_MMIO, 0xa28d, &mmVGT_GROUP_VECT_1_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_CNTL)/sizeof(mmVGT_GROUP_VECT_1_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_FMT_CNTL", REG_MMIO, 0xa28e, &mmVGT_GROUP_VECT_0_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_FMT_CNTL", REG_MMIO, 0xa28f, &mmVGT_GROUP_VECT_1_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GS_MODE", REG_MMIO, 0xa290, &mmVGT_GS_MODE[0], sizeof(mmVGT_GS_MODE)/sizeof(mmVGT_GS_MODE[0]), 0, 0 },
+	{ "mmVGT_GS_ONCHIP_CNTL", REG_MMIO, 0xa291, &mmVGT_GS_ONCHIP_CNTL[0], sizeof(mmVGT_GS_ONCHIP_CNTL)/sizeof(mmVGT_GS_ONCHIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_0", REG_MMIO, 0xa292, &mmPA_SC_MODE_CNTL_0[0], sizeof(mmPA_SC_MODE_CNTL_0)/sizeof(mmPA_SC_MODE_CNTL_0[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_1", REG_MMIO, 0xa293, &mmPA_SC_MODE_CNTL_1[0], sizeof(mmPA_SC_MODE_CNTL_1)/sizeof(mmPA_SC_MODE_CNTL_1[0]), 0, 0 },
+	{ "mmVGT_ENHANCE", REG_MMIO, 0xa294, &mmVGT_ENHANCE[0], sizeof(mmVGT_ENHANCE)/sizeof(mmVGT_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_GS_PER_ES", REG_MMIO, 0xa295, &mmVGT_GS_PER_ES[0], sizeof(mmVGT_GS_PER_ES)/sizeof(mmVGT_GS_PER_ES[0]), 0, 0 },
+	{ "mmVGT_ES_PER_GS", REG_MMIO, 0xa296, &mmVGT_ES_PER_GS[0], sizeof(mmVGT_ES_PER_GS)/sizeof(mmVGT_ES_PER_GS[0]), 0, 0 },
+	{ "mmVGT_GS_PER_VS", REG_MMIO, 0xa297, &mmVGT_GS_PER_VS[0], sizeof(mmVGT_GS_PER_VS)/sizeof(mmVGT_GS_PER_VS[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_1", REG_MMIO, 0xa298, &mmVGT_GSVS_RING_OFFSET_1[0], sizeof(mmVGT_GSVS_RING_OFFSET_1)/sizeof(mmVGT_GSVS_RING_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_2", REG_MMIO, 0xa299, &mmVGT_GSVS_RING_OFFSET_2[0], sizeof(mmVGT_GSVS_RING_OFFSET_2)/sizeof(mmVGT_GSVS_RING_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_3", REG_MMIO, 0xa29a, &mmVGT_GSVS_RING_OFFSET_3[0], sizeof(mmVGT_GSVS_RING_OFFSET_3)/sizeof(mmVGT_GSVS_RING_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_GS_OUT_PRIM_TYPE", REG_MMIO, 0xa29b, &mmVGT_GS_OUT_PRIM_TYPE[0], sizeof(mmVGT_GS_OUT_PRIM_TYPE)/sizeof(mmVGT_GS_OUT_PRIM_TYPE[0]), 0, 0 },
+	{ "mmIA_ENHANCE", REG_MMIO, 0xa29c, &mmIA_ENHANCE[0], sizeof(mmIA_ENHANCE)/sizeof(mmIA_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_DMA_SIZE", REG_MMIO, 0xa29d, &mmVGT_DMA_SIZE[0], sizeof(mmVGT_DMA_SIZE)/sizeof(mmVGT_DMA_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_MAX_SIZE", REG_MMIO, 0xa29e, &mmVGT_DMA_MAX_SIZE[0], sizeof(mmVGT_DMA_MAX_SIZE)/sizeof(mmVGT_DMA_MAX_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_INDEX_TYPE", REG_MMIO, 0xa29f, &mmVGT_DMA_INDEX_TYPE[0], sizeof(mmVGT_DMA_INDEX_TYPE)/sizeof(mmVGT_DMA_INDEX_TYPE[0]), 0, 0 },
+	{ "mmWD_ENHANCE", REG_MMIO, 0xa2a0, &mmWD_ENHANCE[0], sizeof(mmWD_ENHANCE)/sizeof(mmWD_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_EN", REG_MMIO, 0xa2a1, &mmVGT_PRIMITIVEID_EN[0], sizeof(mmVGT_PRIMITIVEID_EN)/sizeof(mmVGT_PRIMITIVEID_EN[0]), 0, 0 },
+	{ "mmVGT_DMA_NUM_INSTANCES", REG_MMIO, 0xa2a2, &mmVGT_DMA_NUM_INSTANCES[0], sizeof(mmVGT_DMA_NUM_INSTANCES)/sizeof(mmVGT_DMA_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_RESET", REG_MMIO, 0xa2a3, &mmVGT_PRIMITIVEID_RESET[0], sizeof(mmVGT_PRIMITIVEID_RESET)/sizeof(mmVGT_PRIMITIVEID_RESET[0]), 0, 0 },
+	{ "mmVGT_EVENT_INITIATOR", REG_MMIO, 0xa2a4, &mmVGT_EVENT_INITIATOR[0], sizeof(mmVGT_EVENT_INITIATOR)/sizeof(mmVGT_EVENT_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_EN", REG_MMIO, 0xa2a5, &mmVGT_MULTI_PRIM_IB_RESET_EN[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_0", REG_MMIO, 0xa2a8, &mmVGT_INSTANCE_STEP_RATE_0[0], sizeof(mmVGT_INSTANCE_STEP_RATE_0)/sizeof(mmVGT_INSTANCE_STEP_RATE_0[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_1", REG_MMIO, 0xa2a9, &mmVGT_INSTANCE_STEP_RATE_1[0], sizeof(mmVGT_INSTANCE_STEP_RATE_1)/sizeof(mmVGT_INSTANCE_STEP_RATE_1[0]), 0, 0 },
+	{ "mmIA_MULTI_VGT_PARAM", REG_MMIO, 0xa2aa, &mmIA_MULTI_VGT_PARAM[0], sizeof(mmIA_MULTI_VGT_PARAM)/sizeof(mmIA_MULTI_VGT_PARAM[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_ITEMSIZE", REG_MMIO, 0xa2ab, &mmVGT_ESGS_RING_ITEMSIZE[0], sizeof(mmVGT_ESGS_RING_ITEMSIZE)/sizeof(mmVGT_ESGS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_ITEMSIZE", REG_MMIO, 0xa2ac, &mmVGT_GSVS_RING_ITEMSIZE[0], sizeof(mmVGT_GSVS_RING_ITEMSIZE)/sizeof(mmVGT_GSVS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_REUSE_OFF", REG_MMIO, 0xa2ad, &mmVGT_REUSE_OFF[0], sizeof(mmVGT_REUSE_OFF)/sizeof(mmVGT_REUSE_OFF[0]), 0, 0 },
+	{ "mmVGT_VTX_CNT_EN", REG_MMIO, 0xa2ae, &mmVGT_VTX_CNT_EN[0], sizeof(mmVGT_VTX_CNT_EN)/sizeof(mmVGT_VTX_CNT_EN[0]), 0, 0 },
+	{ "mmDB_HTILE_SURFACE", REG_MMIO, 0xa2af, &mmDB_HTILE_SURFACE[0], sizeof(mmDB_HTILE_SURFACE)/sizeof(mmDB_HTILE_SURFACE[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE0", REG_MMIO, 0xa2b0, &mmDB_SRESULTS_COMPARE_STATE0[0], sizeof(mmDB_SRESULTS_COMPARE_STATE0)/sizeof(mmDB_SRESULTS_COMPARE_STATE0[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE1", REG_MMIO, 0xa2b1, &mmDB_SRESULTS_COMPARE_STATE1[0], sizeof(mmDB_SRESULTS_COMPARE_STATE1)/sizeof(mmDB_SRESULTS_COMPARE_STATE1[0]), 0, 0 },
+	{ "mmDB_PRELOAD_CONTROL", REG_MMIO, 0xa2b2, &mmDB_PRELOAD_CONTROL[0], sizeof(mmDB_PRELOAD_CONTROL)/sizeof(mmDB_PRELOAD_CONTROL[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_0", REG_MMIO, 0xa2b4, &mmVGT_STRMOUT_BUFFER_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_0", REG_MMIO, 0xa2b5, &mmVGT_STRMOUT_VTX_STRIDE_0[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_0)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_0", REG_MMIO, 0xa2b7, &mmVGT_STRMOUT_BUFFER_OFFSET_0[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_1", REG_MMIO, 0xa2b8, &mmVGT_STRMOUT_BUFFER_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_1", REG_MMIO, 0xa2b9, &mmVGT_STRMOUT_VTX_STRIDE_1[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_1)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_1", REG_MMIO, 0xa2bb, &mmVGT_STRMOUT_BUFFER_OFFSET_1[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_2", REG_MMIO, 0xa2bc, &mmVGT_STRMOUT_BUFFER_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_2", REG_MMIO, 0xa2bd, &mmVGT_STRMOUT_VTX_STRIDE_2[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_2)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_2", REG_MMIO, 0xa2bf, &mmVGT_STRMOUT_BUFFER_OFFSET_2[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_3", REG_MMIO, 0xa2c0, &mmVGT_STRMOUT_BUFFER_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_3", REG_MMIO, 0xa2c1, &mmVGT_STRMOUT_VTX_STRIDE_3[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_3)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_3", REG_MMIO, 0xa2c3, &mmVGT_STRMOUT_BUFFER_OFFSET_3[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET", REG_MMIO, 0xa2ca, &mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE", REG_MMIO, 0xa2cb, &mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", REG_MMIO, 0xa2cc, &mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0]), 0, 0 },
+	{ "mmVGT_GS_MAX_VERT_OUT", REG_MMIO, 0xa2ce, &mmVGT_GS_MAX_VERT_OUT[0], sizeof(mmVGT_GS_MAX_VERT_OUT)/sizeof(mmVGT_GS_MAX_VERT_OUT[0]), 0, 0 },
+	{ "mmVGT_TESS_DISTRIBUTION", REG_MMIO, 0xa2d4, &mmVGT_TESS_DISTRIBUTION[0], sizeof(mmVGT_TESS_DISTRIBUTION)/sizeof(mmVGT_TESS_DISTRIBUTION[0]), 0, 0 },
+	{ "mmVGT_SHADER_STAGES_EN", REG_MMIO, 0xa2d5, &mmVGT_SHADER_STAGES_EN[0], sizeof(mmVGT_SHADER_STAGES_EN)/sizeof(mmVGT_SHADER_STAGES_EN[0]), 0, 0 },
+	{ "mmVGT_LS_HS_CONFIG", REG_MMIO, 0xa2d6, &mmVGT_LS_HS_CONFIG[0], sizeof(mmVGT_LS_HS_CONFIG)/sizeof(mmVGT_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE", REG_MMIO, 0xa2d7, &mmVGT_GS_VERT_ITEMSIZE[0], sizeof(mmVGT_GS_VERT_ITEMSIZE)/sizeof(mmVGT_GS_VERT_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_1", REG_MMIO, 0xa2d8, &mmVGT_GS_VERT_ITEMSIZE_1[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_1)/sizeof(mmVGT_GS_VERT_ITEMSIZE_1[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_2", REG_MMIO, 0xa2d9, &mmVGT_GS_VERT_ITEMSIZE_2[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_2)/sizeof(mmVGT_GS_VERT_ITEMSIZE_2[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_3", REG_MMIO, 0xa2da, &mmVGT_GS_VERT_ITEMSIZE_3[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_3)/sizeof(mmVGT_GS_VERT_ITEMSIZE_3[0]), 0, 0 },
+	{ "mmVGT_TF_PARAM", REG_MMIO, 0xa2db, &mmVGT_TF_PARAM[0], sizeof(mmVGT_TF_PARAM)/sizeof(mmVGT_TF_PARAM[0]), 0, 0 },
+	{ "mmDB_ALPHA_TO_MASK", REG_MMIO, 0xa2dc, &mmDB_ALPHA_TO_MASK[0], sizeof(mmDB_ALPHA_TO_MASK)/sizeof(mmDB_ALPHA_TO_MASK[0]), 0, 0 },
+	{ "mmVGT_DISPATCH_DRAW_INDEX", REG_MMIO, 0xa2dd, &mmVGT_DISPATCH_DRAW_INDEX[0], sizeof(mmVGT_DISPATCH_DRAW_INDEX)/sizeof(mmVGT_DISPATCH_DRAW_INDEX[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_DB_FMT_CNTL", REG_MMIO, 0xa2de, &mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0], sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL)/sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_CLAMP", REG_MMIO, 0xa2df, &mmPA_SU_POLY_OFFSET_CLAMP[0], sizeof(mmPA_SU_POLY_OFFSET_CLAMP)/sizeof(mmPA_SU_POLY_OFFSET_CLAMP[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_SCALE", REG_MMIO, 0xa2e0, &mmPA_SU_POLY_OFFSET_FRONT_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_OFFSET", REG_MMIO, 0xa2e1, &mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_SCALE", REG_MMIO, 0xa2e2, &mmPA_SU_POLY_OFFSET_BACK_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_OFFSET", REG_MMIO, 0xa2e3, &mmPA_SU_POLY_OFFSET_BACK_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET[0]), 0, 0 },
+	{ "mmVGT_GS_INSTANCE_CNT", REG_MMIO, 0xa2e4, &mmVGT_GS_INSTANCE_CNT[0], sizeof(mmVGT_GS_INSTANCE_CNT)/sizeof(mmVGT_GS_INSTANCE_CNT[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_CONFIG", REG_MMIO, 0xa2e5, &mmVGT_STRMOUT_CONFIG[0], sizeof(mmVGT_STRMOUT_CONFIG)/sizeof(mmVGT_STRMOUT_CONFIG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_CONFIG", REG_MMIO, 0xa2e6, &mmVGT_STRMOUT_BUFFER_CONFIG[0], sizeof(mmVGT_STRMOUT_BUFFER_CONFIG)/sizeof(mmVGT_STRMOUT_BUFFER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_0", REG_MMIO, 0xa2f5, &mmPA_SC_CENTROID_PRIORITY_0[0], sizeof(mmPA_SC_CENTROID_PRIORITY_0)/sizeof(mmPA_SC_CENTROID_PRIORITY_0[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_1", REG_MMIO, 0xa2f6, &mmPA_SC_CENTROID_PRIORITY_1[0], sizeof(mmPA_SC_CENTROID_PRIORITY_1)/sizeof(mmPA_SC_CENTROID_PRIORITY_1[0]), 0, 0 },
+	{ "mmPA_SC_LINE_CNTL", REG_MMIO, 0xa2f7, &mmPA_SC_LINE_CNTL[0], sizeof(mmPA_SC_LINE_CNTL)/sizeof(mmPA_SC_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_AA_CONFIG", REG_MMIO, 0xa2f8, &mmPA_SC_AA_CONFIG[0], sizeof(mmPA_SC_AA_CONFIG)/sizeof(mmPA_SC_AA_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_VTX_CNTL", REG_MMIO, 0xa2f9, &mmPA_SU_VTX_CNTL[0], sizeof(mmPA_SU_VTX_CNTL)/sizeof(mmPA_SU_VTX_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_CLIP_ADJ", REG_MMIO, 0xa2fa, &mmPA_CL_GB_VERT_CLIP_ADJ[0], sizeof(mmPA_CL_GB_VERT_CLIP_ADJ)/sizeof(mmPA_CL_GB_VERT_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_DISC_ADJ", REG_MMIO, 0xa2fb, &mmPA_CL_GB_VERT_DISC_ADJ[0], sizeof(mmPA_CL_GB_VERT_DISC_ADJ)/sizeof(mmPA_CL_GB_VERT_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_CLIP_ADJ", REG_MMIO, 0xa2fc, &mmPA_CL_GB_HORZ_CLIP_ADJ[0], sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ)/sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_DISC_ADJ", REG_MMIO, 0xa2fd, &mmPA_CL_GB_HORZ_DISC_ADJ[0], sizeof(mmPA_CL_GB_HORZ_DISC_ADJ)/sizeof(mmPA_CL_GB_HORZ_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", REG_MMIO, 0xa2fe, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", REG_MMIO, 0xa2ff, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", REG_MMIO, 0xa300, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", REG_MMIO, 0xa301, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", REG_MMIO, 0xa302, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", REG_MMIO, 0xa303, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", REG_MMIO, 0xa304, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", REG_MMIO, 0xa305, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", REG_MMIO, 0xa306, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", REG_MMIO, 0xa307, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", REG_MMIO, 0xa308, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", REG_MMIO, 0xa309, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", REG_MMIO, 0xa30a, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", REG_MMIO, 0xa30b, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", REG_MMIO, 0xa30c, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", REG_MMIO, 0xa30d, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y0_X1Y0", REG_MMIO, 0xa30e, &mmPA_SC_AA_MASK_X0Y0_X1Y0[0], sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0)/sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y1_X1Y1", REG_MMIO, 0xa30f, &mmPA_SC_AA_MASK_X0Y1_X1Y1[0], sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1)/sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1[0]), 0, 0 },
+	{ "mmVGT_VERTEX_REUSE_BLOCK_CNTL", REG_MMIO, 0xa316, &mmVGT_VERTEX_REUSE_BLOCK_CNTL[0], sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL)/sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL[0]), 0, 0 },
+	{ "mmVGT_OUT_DEALLOC_CNTL", REG_MMIO, 0xa317, &mmVGT_OUT_DEALLOC_CNTL[0], sizeof(mmVGT_OUT_DEALLOC_CNTL)/sizeof(mmVGT_OUT_DEALLOC_CNTL[0]), 0, 0 },
+	{ "mmCB_COLOR0_BASE", REG_MMIO, 0xa318, &mmCB_COLOR0_BASE[0], sizeof(mmCB_COLOR0_BASE)/sizeof(mmCB_COLOR0_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR0_PITCH", REG_MMIO, 0xa319, &mmCB_COLOR0_PITCH[0], sizeof(mmCB_COLOR0_PITCH)/sizeof(mmCB_COLOR0_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR0_SLICE", REG_MMIO, 0xa31a, &mmCB_COLOR0_SLICE[0], sizeof(mmCB_COLOR0_SLICE)/sizeof(mmCB_COLOR0_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_VIEW", REG_MMIO, 0xa31b, &mmCB_COLOR0_VIEW[0], sizeof(mmCB_COLOR0_VIEW)/sizeof(mmCB_COLOR0_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR0_INFO", REG_MMIO, 0xa31c, &mmCB_COLOR0_INFO[0], sizeof(mmCB_COLOR0_INFO)/sizeof(mmCB_COLOR0_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR0_ATTRIB", REG_MMIO, 0xa31d, &mmCB_COLOR0_ATTRIB[0], sizeof(mmCB_COLOR0_ATTRIB)/sizeof(mmCB_COLOR0_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR0_DCC_CONTROL", REG_MMIO, 0xa31e, &mmCB_COLOR0_DCC_CONTROL[0], sizeof(mmCB_COLOR0_DCC_CONTROL)/sizeof(mmCB_COLOR0_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK", REG_MMIO, 0xa31f, &mmCB_COLOR0_CMASK[0], sizeof(mmCB_COLOR0_CMASK)/sizeof(mmCB_COLOR0_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK_SLICE", REG_MMIO, 0xa320, &mmCB_COLOR0_CMASK_SLICE[0], sizeof(mmCB_COLOR0_CMASK_SLICE)/sizeof(mmCB_COLOR0_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK", REG_MMIO, 0xa321, &mmCB_COLOR0_FMASK[0], sizeof(mmCB_COLOR0_FMASK)/sizeof(mmCB_COLOR0_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK_SLICE", REG_MMIO, 0xa322, &mmCB_COLOR0_FMASK_SLICE[0], sizeof(mmCB_COLOR0_FMASK_SLICE)/sizeof(mmCB_COLOR0_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD0", REG_MMIO, 0xa323, &mmCB_COLOR0_CLEAR_WORD0[0], sizeof(mmCB_COLOR0_CLEAR_WORD0)/sizeof(mmCB_COLOR0_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD1", REG_MMIO, 0xa324, &mmCB_COLOR0_CLEAR_WORD1[0], sizeof(mmCB_COLOR0_CLEAR_WORD1)/sizeof(mmCB_COLOR0_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR0_DCC_BASE", REG_MMIO, 0xa325, &mmCB_COLOR0_DCC_BASE[0], sizeof(mmCB_COLOR0_DCC_BASE)/sizeof(mmCB_COLOR0_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR1_BASE", REG_MMIO, 0xa327, &mmCB_COLOR1_BASE[0], sizeof(mmCB_COLOR1_BASE)/sizeof(mmCB_COLOR1_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR1_PITCH", REG_MMIO, 0xa328, &mmCB_COLOR1_PITCH[0], sizeof(mmCB_COLOR1_PITCH)/sizeof(mmCB_COLOR1_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR1_SLICE", REG_MMIO, 0xa329, &mmCB_COLOR1_SLICE[0], sizeof(mmCB_COLOR1_SLICE)/sizeof(mmCB_COLOR1_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_VIEW", REG_MMIO, 0xa32a, &mmCB_COLOR1_VIEW[0], sizeof(mmCB_COLOR1_VIEW)/sizeof(mmCB_COLOR1_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR1_INFO", REG_MMIO, 0xa32b, &mmCB_COLOR1_INFO[0], sizeof(mmCB_COLOR1_INFO)/sizeof(mmCB_COLOR1_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR1_ATTRIB", REG_MMIO, 0xa32c, &mmCB_COLOR1_ATTRIB[0], sizeof(mmCB_COLOR1_ATTRIB)/sizeof(mmCB_COLOR1_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR1_DCC_CONTROL", REG_MMIO, 0xa32d, &mmCB_COLOR1_DCC_CONTROL[0], sizeof(mmCB_COLOR1_DCC_CONTROL)/sizeof(mmCB_COLOR1_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK", REG_MMIO, 0xa32e, &mmCB_COLOR1_CMASK[0], sizeof(mmCB_COLOR1_CMASK)/sizeof(mmCB_COLOR1_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK_SLICE", REG_MMIO, 0xa32f, &mmCB_COLOR1_CMASK_SLICE[0], sizeof(mmCB_COLOR1_CMASK_SLICE)/sizeof(mmCB_COLOR1_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK", REG_MMIO, 0xa330, &mmCB_COLOR1_FMASK[0], sizeof(mmCB_COLOR1_FMASK)/sizeof(mmCB_COLOR1_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK_SLICE", REG_MMIO, 0xa331, &mmCB_COLOR1_FMASK_SLICE[0], sizeof(mmCB_COLOR1_FMASK_SLICE)/sizeof(mmCB_COLOR1_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD0", REG_MMIO, 0xa332, &mmCB_COLOR1_CLEAR_WORD0[0], sizeof(mmCB_COLOR1_CLEAR_WORD0)/sizeof(mmCB_COLOR1_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD1", REG_MMIO, 0xa333, &mmCB_COLOR1_CLEAR_WORD1[0], sizeof(mmCB_COLOR1_CLEAR_WORD1)/sizeof(mmCB_COLOR1_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR1_DCC_BASE", REG_MMIO, 0xa334, &mmCB_COLOR1_DCC_BASE[0], sizeof(mmCB_COLOR1_DCC_BASE)/sizeof(mmCB_COLOR1_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR2_BASE", REG_MMIO, 0xa336, &mmCB_COLOR2_BASE[0], sizeof(mmCB_COLOR2_BASE)/sizeof(mmCB_COLOR2_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR2_PITCH", REG_MMIO, 0xa337, &mmCB_COLOR2_PITCH[0], sizeof(mmCB_COLOR2_PITCH)/sizeof(mmCB_COLOR2_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR2_SLICE", REG_MMIO, 0xa338, &mmCB_COLOR2_SLICE[0], sizeof(mmCB_COLOR2_SLICE)/sizeof(mmCB_COLOR2_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_VIEW", REG_MMIO, 0xa339, &mmCB_COLOR2_VIEW[0], sizeof(mmCB_COLOR2_VIEW)/sizeof(mmCB_COLOR2_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR2_INFO", REG_MMIO, 0xa33a, &mmCB_COLOR2_INFO[0], sizeof(mmCB_COLOR2_INFO)/sizeof(mmCB_COLOR2_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR2_ATTRIB", REG_MMIO, 0xa33b, &mmCB_COLOR2_ATTRIB[0], sizeof(mmCB_COLOR2_ATTRIB)/sizeof(mmCB_COLOR2_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR2_DCC_CONTROL", REG_MMIO, 0xa33c, &mmCB_COLOR2_DCC_CONTROL[0], sizeof(mmCB_COLOR2_DCC_CONTROL)/sizeof(mmCB_COLOR2_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK", REG_MMIO, 0xa33d, &mmCB_COLOR2_CMASK[0], sizeof(mmCB_COLOR2_CMASK)/sizeof(mmCB_COLOR2_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK_SLICE", REG_MMIO, 0xa33e, &mmCB_COLOR2_CMASK_SLICE[0], sizeof(mmCB_COLOR2_CMASK_SLICE)/sizeof(mmCB_COLOR2_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK", REG_MMIO, 0xa33f, &mmCB_COLOR2_FMASK[0], sizeof(mmCB_COLOR2_FMASK)/sizeof(mmCB_COLOR2_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK_SLICE", REG_MMIO, 0xa340, &mmCB_COLOR2_FMASK_SLICE[0], sizeof(mmCB_COLOR2_FMASK_SLICE)/sizeof(mmCB_COLOR2_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD0", REG_MMIO, 0xa341, &mmCB_COLOR2_CLEAR_WORD0[0], sizeof(mmCB_COLOR2_CLEAR_WORD0)/sizeof(mmCB_COLOR2_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD1", REG_MMIO, 0xa342, &mmCB_COLOR2_CLEAR_WORD1[0], sizeof(mmCB_COLOR2_CLEAR_WORD1)/sizeof(mmCB_COLOR2_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR2_DCC_BASE", REG_MMIO, 0xa343, &mmCB_COLOR2_DCC_BASE[0], sizeof(mmCB_COLOR2_DCC_BASE)/sizeof(mmCB_COLOR2_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR3_BASE", REG_MMIO, 0xa345, &mmCB_COLOR3_BASE[0], sizeof(mmCB_COLOR3_BASE)/sizeof(mmCB_COLOR3_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR3_PITCH", REG_MMIO, 0xa346, &mmCB_COLOR3_PITCH[0], sizeof(mmCB_COLOR3_PITCH)/sizeof(mmCB_COLOR3_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR3_SLICE", REG_MMIO, 0xa347, &mmCB_COLOR3_SLICE[0], sizeof(mmCB_COLOR3_SLICE)/sizeof(mmCB_COLOR3_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_VIEW", REG_MMIO, 0xa348, &mmCB_COLOR3_VIEW[0], sizeof(mmCB_COLOR3_VIEW)/sizeof(mmCB_COLOR3_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR3_INFO", REG_MMIO, 0xa349, &mmCB_COLOR3_INFO[0], sizeof(mmCB_COLOR3_INFO)/sizeof(mmCB_COLOR3_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR3_ATTRIB", REG_MMIO, 0xa34a, &mmCB_COLOR3_ATTRIB[0], sizeof(mmCB_COLOR3_ATTRIB)/sizeof(mmCB_COLOR3_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR3_DCC_CONTROL", REG_MMIO, 0xa34b, &mmCB_COLOR3_DCC_CONTROL[0], sizeof(mmCB_COLOR3_DCC_CONTROL)/sizeof(mmCB_COLOR3_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK", REG_MMIO, 0xa34c, &mmCB_COLOR3_CMASK[0], sizeof(mmCB_COLOR3_CMASK)/sizeof(mmCB_COLOR3_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK_SLICE", REG_MMIO, 0xa34d, &mmCB_COLOR3_CMASK_SLICE[0], sizeof(mmCB_COLOR3_CMASK_SLICE)/sizeof(mmCB_COLOR3_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK", REG_MMIO, 0xa34e, &mmCB_COLOR3_FMASK[0], sizeof(mmCB_COLOR3_FMASK)/sizeof(mmCB_COLOR3_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK_SLICE", REG_MMIO, 0xa34f, &mmCB_COLOR3_FMASK_SLICE[0], sizeof(mmCB_COLOR3_FMASK_SLICE)/sizeof(mmCB_COLOR3_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD0", REG_MMIO, 0xa350, &mmCB_COLOR3_CLEAR_WORD0[0], sizeof(mmCB_COLOR3_CLEAR_WORD0)/sizeof(mmCB_COLOR3_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD1", REG_MMIO, 0xa351, &mmCB_COLOR3_CLEAR_WORD1[0], sizeof(mmCB_COLOR3_CLEAR_WORD1)/sizeof(mmCB_COLOR3_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR3_DCC_BASE", REG_MMIO, 0xa352, &mmCB_COLOR3_DCC_BASE[0], sizeof(mmCB_COLOR3_DCC_BASE)/sizeof(mmCB_COLOR3_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR4_BASE", REG_MMIO, 0xa354, &mmCB_COLOR4_BASE[0], sizeof(mmCB_COLOR4_BASE)/sizeof(mmCB_COLOR4_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR4_PITCH", REG_MMIO, 0xa355, &mmCB_COLOR4_PITCH[0], sizeof(mmCB_COLOR4_PITCH)/sizeof(mmCB_COLOR4_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR4_SLICE", REG_MMIO, 0xa356, &mmCB_COLOR4_SLICE[0], sizeof(mmCB_COLOR4_SLICE)/sizeof(mmCB_COLOR4_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_VIEW", REG_MMIO, 0xa357, &mmCB_COLOR4_VIEW[0], sizeof(mmCB_COLOR4_VIEW)/sizeof(mmCB_COLOR4_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR4_INFO", REG_MMIO, 0xa358, &mmCB_COLOR4_INFO[0], sizeof(mmCB_COLOR4_INFO)/sizeof(mmCB_COLOR4_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR4_ATTRIB", REG_MMIO, 0xa359, &mmCB_COLOR4_ATTRIB[0], sizeof(mmCB_COLOR4_ATTRIB)/sizeof(mmCB_COLOR4_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR4_DCC_CONTROL", REG_MMIO, 0xa35a, &mmCB_COLOR4_DCC_CONTROL[0], sizeof(mmCB_COLOR4_DCC_CONTROL)/sizeof(mmCB_COLOR4_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK", REG_MMIO, 0xa35b, &mmCB_COLOR4_CMASK[0], sizeof(mmCB_COLOR4_CMASK)/sizeof(mmCB_COLOR4_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK_SLICE", REG_MMIO, 0xa35c, &mmCB_COLOR4_CMASK_SLICE[0], sizeof(mmCB_COLOR4_CMASK_SLICE)/sizeof(mmCB_COLOR4_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK", REG_MMIO, 0xa35d, &mmCB_COLOR4_FMASK[0], sizeof(mmCB_COLOR4_FMASK)/sizeof(mmCB_COLOR4_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK_SLICE", REG_MMIO, 0xa35e, &mmCB_COLOR4_FMASK_SLICE[0], sizeof(mmCB_COLOR4_FMASK_SLICE)/sizeof(mmCB_COLOR4_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD0", REG_MMIO, 0xa35f, &mmCB_COLOR4_CLEAR_WORD0[0], sizeof(mmCB_COLOR4_CLEAR_WORD0)/sizeof(mmCB_COLOR4_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD1", REG_MMIO, 0xa360, &mmCB_COLOR4_CLEAR_WORD1[0], sizeof(mmCB_COLOR4_CLEAR_WORD1)/sizeof(mmCB_COLOR4_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR4_DCC_BASE", REG_MMIO, 0xa361, &mmCB_COLOR4_DCC_BASE[0], sizeof(mmCB_COLOR4_DCC_BASE)/sizeof(mmCB_COLOR4_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR5_BASE", REG_MMIO, 0xa363, &mmCB_COLOR5_BASE[0], sizeof(mmCB_COLOR5_BASE)/sizeof(mmCB_COLOR5_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR5_PITCH", REG_MMIO, 0xa364, &mmCB_COLOR5_PITCH[0], sizeof(mmCB_COLOR5_PITCH)/sizeof(mmCB_COLOR5_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR5_SLICE", REG_MMIO, 0xa365, &mmCB_COLOR5_SLICE[0], sizeof(mmCB_COLOR5_SLICE)/sizeof(mmCB_COLOR5_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_VIEW", REG_MMIO, 0xa366, &mmCB_COLOR5_VIEW[0], sizeof(mmCB_COLOR5_VIEW)/sizeof(mmCB_COLOR5_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR5_INFO", REG_MMIO, 0xa367, &mmCB_COLOR5_INFO[0], sizeof(mmCB_COLOR5_INFO)/sizeof(mmCB_COLOR5_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR5_ATTRIB", REG_MMIO, 0xa368, &mmCB_COLOR5_ATTRIB[0], sizeof(mmCB_COLOR5_ATTRIB)/sizeof(mmCB_COLOR5_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR5_DCC_CONTROL", REG_MMIO, 0xa369, &mmCB_COLOR5_DCC_CONTROL[0], sizeof(mmCB_COLOR5_DCC_CONTROL)/sizeof(mmCB_COLOR5_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK", REG_MMIO, 0xa36a, &mmCB_COLOR5_CMASK[0], sizeof(mmCB_COLOR5_CMASK)/sizeof(mmCB_COLOR5_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK_SLICE", REG_MMIO, 0xa36b, &mmCB_COLOR5_CMASK_SLICE[0], sizeof(mmCB_COLOR5_CMASK_SLICE)/sizeof(mmCB_COLOR5_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK", REG_MMIO, 0xa36c, &mmCB_COLOR5_FMASK[0], sizeof(mmCB_COLOR5_FMASK)/sizeof(mmCB_COLOR5_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK_SLICE", REG_MMIO, 0xa36d, &mmCB_COLOR5_FMASK_SLICE[0], sizeof(mmCB_COLOR5_FMASK_SLICE)/sizeof(mmCB_COLOR5_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD0", REG_MMIO, 0xa36e, &mmCB_COLOR5_CLEAR_WORD0[0], sizeof(mmCB_COLOR5_CLEAR_WORD0)/sizeof(mmCB_COLOR5_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD1", REG_MMIO, 0xa36f, &mmCB_COLOR5_CLEAR_WORD1[0], sizeof(mmCB_COLOR5_CLEAR_WORD1)/sizeof(mmCB_COLOR5_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR5_DCC_BASE", REG_MMIO, 0xa370, &mmCB_COLOR5_DCC_BASE[0], sizeof(mmCB_COLOR5_DCC_BASE)/sizeof(mmCB_COLOR5_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR6_BASE", REG_MMIO, 0xa372, &mmCB_COLOR6_BASE[0], sizeof(mmCB_COLOR6_BASE)/sizeof(mmCB_COLOR6_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR6_PITCH", REG_MMIO, 0xa373, &mmCB_COLOR6_PITCH[0], sizeof(mmCB_COLOR6_PITCH)/sizeof(mmCB_COLOR6_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR6_SLICE", REG_MMIO, 0xa374, &mmCB_COLOR6_SLICE[0], sizeof(mmCB_COLOR6_SLICE)/sizeof(mmCB_COLOR6_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_VIEW", REG_MMIO, 0xa375, &mmCB_COLOR6_VIEW[0], sizeof(mmCB_COLOR6_VIEW)/sizeof(mmCB_COLOR6_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR6_INFO", REG_MMIO, 0xa376, &mmCB_COLOR6_INFO[0], sizeof(mmCB_COLOR6_INFO)/sizeof(mmCB_COLOR6_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR6_ATTRIB", REG_MMIO, 0xa377, &mmCB_COLOR6_ATTRIB[0], sizeof(mmCB_COLOR6_ATTRIB)/sizeof(mmCB_COLOR6_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR6_DCC_CONTROL", REG_MMIO, 0xa378, &mmCB_COLOR6_DCC_CONTROL[0], sizeof(mmCB_COLOR6_DCC_CONTROL)/sizeof(mmCB_COLOR6_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK", REG_MMIO, 0xa379, &mmCB_COLOR6_CMASK[0], sizeof(mmCB_COLOR6_CMASK)/sizeof(mmCB_COLOR6_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK_SLICE", REG_MMIO, 0xa37a, &mmCB_COLOR6_CMASK_SLICE[0], sizeof(mmCB_COLOR6_CMASK_SLICE)/sizeof(mmCB_COLOR6_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK", REG_MMIO, 0xa37b, &mmCB_COLOR6_FMASK[0], sizeof(mmCB_COLOR6_FMASK)/sizeof(mmCB_COLOR6_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK_SLICE", REG_MMIO, 0xa37c, &mmCB_COLOR6_FMASK_SLICE[0], sizeof(mmCB_COLOR6_FMASK_SLICE)/sizeof(mmCB_COLOR6_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD0", REG_MMIO, 0xa37d, &mmCB_COLOR6_CLEAR_WORD0[0], sizeof(mmCB_COLOR6_CLEAR_WORD0)/sizeof(mmCB_COLOR6_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD1", REG_MMIO, 0xa37e, &mmCB_COLOR6_CLEAR_WORD1[0], sizeof(mmCB_COLOR6_CLEAR_WORD1)/sizeof(mmCB_COLOR6_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR6_DCC_BASE", REG_MMIO, 0xa37f, &mmCB_COLOR6_DCC_BASE[0], sizeof(mmCB_COLOR6_DCC_BASE)/sizeof(mmCB_COLOR6_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR7_BASE", REG_MMIO, 0xa381, &mmCB_COLOR7_BASE[0], sizeof(mmCB_COLOR7_BASE)/sizeof(mmCB_COLOR7_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR7_PITCH", REG_MMIO, 0xa382, &mmCB_COLOR7_PITCH[0], sizeof(mmCB_COLOR7_PITCH)/sizeof(mmCB_COLOR7_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR7_SLICE", REG_MMIO, 0xa383, &mmCB_COLOR7_SLICE[0], sizeof(mmCB_COLOR7_SLICE)/sizeof(mmCB_COLOR7_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_VIEW", REG_MMIO, 0xa384, &mmCB_COLOR7_VIEW[0], sizeof(mmCB_COLOR7_VIEW)/sizeof(mmCB_COLOR7_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR7_INFO", REG_MMIO, 0xa385, &mmCB_COLOR7_INFO[0], sizeof(mmCB_COLOR7_INFO)/sizeof(mmCB_COLOR7_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR7_ATTRIB", REG_MMIO, 0xa386, &mmCB_COLOR7_ATTRIB[0], sizeof(mmCB_COLOR7_ATTRIB)/sizeof(mmCB_COLOR7_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR7_DCC_CONTROL", REG_MMIO, 0xa387, &mmCB_COLOR7_DCC_CONTROL[0], sizeof(mmCB_COLOR7_DCC_CONTROL)/sizeof(mmCB_COLOR7_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK", REG_MMIO, 0xa388, &mmCB_COLOR7_CMASK[0], sizeof(mmCB_COLOR7_CMASK)/sizeof(mmCB_COLOR7_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK_SLICE", REG_MMIO, 0xa389, &mmCB_COLOR7_CMASK_SLICE[0], sizeof(mmCB_COLOR7_CMASK_SLICE)/sizeof(mmCB_COLOR7_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK", REG_MMIO, 0xa38a, &mmCB_COLOR7_FMASK[0], sizeof(mmCB_COLOR7_FMASK)/sizeof(mmCB_COLOR7_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK_SLICE", REG_MMIO, 0xa38b, &mmCB_COLOR7_FMASK_SLICE[0], sizeof(mmCB_COLOR7_FMASK_SLICE)/sizeof(mmCB_COLOR7_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD0", REG_MMIO, 0xa38c, &mmCB_COLOR7_CLEAR_WORD0[0], sizeof(mmCB_COLOR7_CLEAR_WORD0)/sizeof(mmCB_COLOR7_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD1", REG_MMIO, 0xa38d, &mmCB_COLOR7_CLEAR_WORD1[0], sizeof(mmCB_COLOR7_CLEAR_WORD1)/sizeof(mmCB_COLOR7_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR7_DCC_BASE", REG_MMIO, 0xa38e, &mmCB_COLOR7_DCC_BASE[0], sizeof(mmCB_COLOR7_DCC_BASE)/sizeof(mmCB_COLOR7_DCC_BASE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG11", REG_SMC, 0xb, &ixCLIPPER_DEBUG_REG11[0], sizeof(ixCLIPPER_DEBUG_REG11)/sizeof(ixCLIPPER_DEBUG_REG11[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG11", REG_SMC, 0xb, &ixVGT_DEBUG_REG11[0], sizeof(ixVGT_DEBUG_REG11)/sizeof(ixVGT_DEBUG_REG11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG12", REG_SMC, 0xc, &ixCLIPPER_DEBUG_REG12[0], sizeof(ixCLIPPER_DEBUG_REG12)/sizeof(ixCLIPPER_DEBUG_REG12[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG12", REG_SMC, 0xc, &ixVGT_DEBUG_REG12[0], sizeof(ixVGT_DEBUG_REG12)/sizeof(ixVGT_DEBUG_REG12[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_LO", REG_MMIO, 0xc000, &mmCP_EOP_DONE_ADDR_LO[0], sizeof(mmCP_EOP_DONE_ADDR_LO)/sizeof(mmCP_EOP_DONE_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_HI", REG_MMIO, 0xc001, &mmCP_EOP_DONE_ADDR_HI[0], sizeof(mmCP_EOP_DONE_ADDR_HI)/sizeof(mmCP_EOP_DONE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_LO", REG_MMIO, 0xc002, &mmCP_EOP_DONE_DATA_LO[0], sizeof(mmCP_EOP_DONE_DATA_LO)/sizeof(mmCP_EOP_DONE_DATA_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_HI", REG_MMIO, 0xc003, &mmCP_EOP_DONE_DATA_HI[0], sizeof(mmCP_EOP_DONE_DATA_HI)/sizeof(mmCP_EOP_DONE_DATA_HI[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_LO", REG_MMIO, 0xc004, &mmCP_EOP_LAST_FENCE_LO[0], sizeof(mmCP_EOP_LAST_FENCE_LO)/sizeof(mmCP_EOP_LAST_FENCE_LO[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_HI", REG_MMIO, 0xc005, &mmCP_EOP_LAST_FENCE_HI[0], sizeof(mmCP_EOP_LAST_FENCE_HI)/sizeof(mmCP_EOP_LAST_FENCE_HI[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_LO", REG_MMIO, 0xc006, &mmCP_STREAM_OUT_ADDR_LO[0], sizeof(mmCP_STREAM_OUT_ADDR_LO)/sizeof(mmCP_STREAM_OUT_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_HI", REG_MMIO, 0xc007, &mmCP_STREAM_OUT_ADDR_HI[0], sizeof(mmCP_STREAM_OUT_ADDR_HI)/sizeof(mmCP_STREAM_OUT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_LO", REG_MMIO, 0xc008, &mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_HI", REG_MMIO, 0xc009, &mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_LO", REG_MMIO, 0xc00a, &mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_HI", REG_MMIO, 0xc00b, &mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_LO", REG_MMIO, 0xc00c, &mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_HI", REG_MMIO, 0xc00d, &mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_LO", REG_MMIO, 0xc00e, &mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_HI", REG_MMIO, 0xc00f, &mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_LO", REG_MMIO, 0xc010, &mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_HI", REG_MMIO, 0xc011, &mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_LO", REG_MMIO, 0xc012, &mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_HI", REG_MMIO, 0xc013, &mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_LO", REG_MMIO, 0xc014, &mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_HI", REG_MMIO, 0xc015, &mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_LO", REG_MMIO, 0xc016, &mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_HI", REG_MMIO, 0xc017, &mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_LO", REG_MMIO, 0xc018, &mmCP_PIPE_STATS_ADDR_LO[0], sizeof(mmCP_PIPE_STATS_ADDR_LO)/sizeof(mmCP_PIPE_STATS_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_HI", REG_MMIO, 0xc019, &mmCP_PIPE_STATS_ADDR_HI[0], sizeof(mmCP_PIPE_STATS_ADDR_HI)/sizeof(mmCP_PIPE_STATS_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_LO", REG_MMIO, 0xc01a, &mmCP_VGT_IAVERT_COUNT_LO[0], sizeof(mmCP_VGT_IAVERT_COUNT_LO)/sizeof(mmCP_VGT_IAVERT_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_HI", REG_MMIO, 0xc01b, &mmCP_VGT_IAVERT_COUNT_HI[0], sizeof(mmCP_VGT_IAVERT_COUNT_HI)/sizeof(mmCP_VGT_IAVERT_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_LO", REG_MMIO, 0xc01c, &mmCP_VGT_IAPRIM_COUNT_LO[0], sizeof(mmCP_VGT_IAPRIM_COUNT_LO)/sizeof(mmCP_VGT_IAPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_HI", REG_MMIO, 0xc01d, &mmCP_VGT_IAPRIM_COUNT_HI[0], sizeof(mmCP_VGT_IAPRIM_COUNT_HI)/sizeof(mmCP_VGT_IAPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_LO", REG_MMIO, 0xc01e, &mmCP_VGT_GSPRIM_COUNT_LO[0], sizeof(mmCP_VGT_GSPRIM_COUNT_LO)/sizeof(mmCP_VGT_GSPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_HI", REG_MMIO, 0xc01f, &mmCP_VGT_GSPRIM_COUNT_HI[0], sizeof(mmCP_VGT_GSPRIM_COUNT_HI)/sizeof(mmCP_VGT_GSPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_LO", REG_MMIO, 0xc020, &mmCP_VGT_VSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_VSINVOC_COUNT_LO)/sizeof(mmCP_VGT_VSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_HI", REG_MMIO, 0xc021, &mmCP_VGT_VSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_VSINVOC_COUNT_HI)/sizeof(mmCP_VGT_VSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_LO", REG_MMIO, 0xc022, &mmCP_VGT_GSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_GSINVOC_COUNT_LO)/sizeof(mmCP_VGT_GSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_HI", REG_MMIO, 0xc023, &mmCP_VGT_GSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_GSINVOC_COUNT_HI)/sizeof(mmCP_VGT_GSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_LO", REG_MMIO, 0xc024, &mmCP_VGT_HSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_HSINVOC_COUNT_LO)/sizeof(mmCP_VGT_HSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_HI", REG_MMIO, 0xc025, &mmCP_VGT_HSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_HSINVOC_COUNT_HI)/sizeof(mmCP_VGT_HSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_LO", REG_MMIO, 0xc026, &mmCP_VGT_DSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_DSINVOC_COUNT_LO)/sizeof(mmCP_VGT_DSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_HI", REG_MMIO, 0xc027, &mmCP_VGT_DSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_DSINVOC_COUNT_HI)/sizeof(mmCP_VGT_DSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_LO", REG_MMIO, 0xc028, &mmCP_PA_CINVOC_COUNT_LO[0], sizeof(mmCP_PA_CINVOC_COUNT_LO)/sizeof(mmCP_PA_CINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_HI", REG_MMIO, 0xc029, &mmCP_PA_CINVOC_COUNT_HI[0], sizeof(mmCP_PA_CINVOC_COUNT_HI)/sizeof(mmCP_PA_CINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_LO", REG_MMIO, 0xc02a, &mmCP_PA_CPRIM_COUNT_LO[0], sizeof(mmCP_PA_CPRIM_COUNT_LO)/sizeof(mmCP_PA_CPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_HI", REG_MMIO, 0xc02b, &mmCP_PA_CPRIM_COUNT_HI[0], sizeof(mmCP_PA_CPRIM_COUNT_HI)/sizeof(mmCP_PA_CPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_LO", REG_MMIO, 0xc02c, &mmCP_SC_PSINVOC_COUNT0_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT0_LO)/sizeof(mmCP_SC_PSINVOC_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_HI", REG_MMIO, 0xc02d, &mmCP_SC_PSINVOC_COUNT0_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT0_HI)/sizeof(mmCP_SC_PSINVOC_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_LO", REG_MMIO, 0xc02e, &mmCP_SC_PSINVOC_COUNT1_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT1_LO)/sizeof(mmCP_SC_PSINVOC_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_HI", REG_MMIO, 0xc02f, &mmCP_SC_PSINVOC_COUNT1_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT1_HI)/sizeof(mmCP_SC_PSINVOC_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_LO", REG_MMIO, 0xc030, &mmCP_VGT_CSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_CSINVOC_COUNT_LO)/sizeof(mmCP_VGT_CSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_HI", REG_MMIO, 0xc031, &mmCP_VGT_CSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_CSINVOC_COUNT_HI)/sizeof(mmCP_VGT_CSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_CONTROL", REG_MMIO, 0xc03d, &mmCP_PIPE_STATS_CONTROL[0], sizeof(mmCP_PIPE_STATS_CONTROL)/sizeof(mmCP_PIPE_STATS_CONTROL[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_CONTROL", REG_MMIO, 0xc03e, &mmCP_STREAM_OUT_CONTROL[0], sizeof(mmCP_STREAM_OUT_CONTROL)/sizeof(mmCP_STREAM_OUT_CONTROL[0]), 0, 0 },
+	{ "mmCP_STRMOUT_CNTL", REG_MMIO, 0xc03f, &mmCP_STRMOUT_CNTL[0], sizeof(mmCP_STRMOUT_CNTL)/sizeof(mmCP_STRMOUT_CNTL[0]), 0, 0 },
+	{ "mmSCRATCH_REG0", REG_MMIO, 0xc040, &mmSCRATCH_REG0[0], sizeof(mmSCRATCH_REG0)/sizeof(mmSCRATCH_REG0[0]), 0, 0 },
+	{ "mmSCRATCH_REG1", REG_MMIO, 0xc041, &mmSCRATCH_REG1[0], sizeof(mmSCRATCH_REG1)/sizeof(mmSCRATCH_REG1[0]), 0, 0 },
+	{ "mmSCRATCH_REG2", REG_MMIO, 0xc042, &mmSCRATCH_REG2[0], sizeof(mmSCRATCH_REG2)/sizeof(mmSCRATCH_REG2[0]), 0, 0 },
+	{ "mmSCRATCH_REG3", REG_MMIO, 0xc043, &mmSCRATCH_REG3[0], sizeof(mmSCRATCH_REG3)/sizeof(mmSCRATCH_REG3[0]), 0, 0 },
+	{ "mmSCRATCH_REG4", REG_MMIO, 0xc044, &mmSCRATCH_REG4[0], sizeof(mmSCRATCH_REG4)/sizeof(mmSCRATCH_REG4[0]), 0, 0 },
+	{ "mmSCRATCH_REG5", REG_MMIO, 0xc045, &mmSCRATCH_REG5[0], sizeof(mmSCRATCH_REG5)/sizeof(mmSCRATCH_REG5[0]), 0, 0 },
+	{ "mmSCRATCH_REG6", REG_MMIO, 0xc046, &mmSCRATCH_REG6[0], sizeof(mmSCRATCH_REG6)/sizeof(mmSCRATCH_REG6[0]), 0, 0 },
+	{ "mmSCRATCH_REG7", REG_MMIO, 0xc047, &mmSCRATCH_REG7[0], sizeof(mmSCRATCH_REG7)/sizeof(mmSCRATCH_REG7[0]), 0, 0 },
+	{ "mmSCRATCH_UMSK", REG_MMIO, 0xc050, &mmSCRATCH_UMSK[0], sizeof(mmSCRATCH_UMSK)/sizeof(mmSCRATCH_UMSK[0]), 0, 0 },
+	{ "mmSCRATCH_ADDR", REG_MMIO, 0xc051, &mmSCRATCH_ADDR[0], sizeof(mmSCRATCH_ADDR)/sizeof(mmSCRATCH_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_ATOMIC_PREOP_LO", REG_MMIO, 0xc052, &mmCP_PFP_ATOMIC_PREOP_LO[0], sizeof(mmCP_PFP_ATOMIC_PREOP_LO)/sizeof(mmCP_PFP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_ATOMIC_PREOP_HI", REG_MMIO, 0xc053, &mmCP_PFP_ATOMIC_PREOP_HI[0], sizeof(mmCP_PFP_ATOMIC_PREOP_HI)/sizeof(mmCP_PFP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc054, &mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc055, &mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc056, &mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc057, &mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_LO", REG_MMIO, 0xc058, &mmCP_APPEND_ADDR_LO[0], sizeof(mmCP_APPEND_ADDR_LO)/sizeof(mmCP_APPEND_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_HI", REG_MMIO, 0xc059, &mmCP_APPEND_ADDR_HI[0], sizeof(mmCP_APPEND_ADDR_HI)/sizeof(mmCP_APPEND_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_DATA", REG_MMIO, 0xc05a, &mmCP_APPEND_DATA[0], sizeof(mmCP_APPEND_DATA)/sizeof(mmCP_APPEND_DATA[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_CS_FENCE", REG_MMIO, 0xc05b, &mmCP_APPEND_LAST_CS_FENCE[0], sizeof(mmCP_APPEND_LAST_CS_FENCE)/sizeof(mmCP_APPEND_LAST_CS_FENCE[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_PS_FENCE", REG_MMIO, 0xc05c, &mmCP_APPEND_LAST_PS_FENCE[0], sizeof(mmCP_APPEND_LAST_PS_FENCE)/sizeof(mmCP_APPEND_LAST_PS_FENCE[0]), 0, 0 },
+	{ "mmCP_ME_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &mmCP_ME_ATOMIC_PREOP_LO[0], sizeof(mmCP_ME_ATOMIC_PREOP_LO)/sizeof(mmCP_ME_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &mmCP_ATOMIC_PREOP_LO[0], sizeof(mmCP_ATOMIC_PREOP_LO)/sizeof(mmCP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &mmCP_ME_ATOMIC_PREOP_HI[0], sizeof(mmCP_ME_ATOMIC_PREOP_HI)/sizeof(mmCP_ME_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &mmCP_ATOMIC_PREOP_HI[0], sizeof(mmCP_ATOMIC_PREOP_HI)/sizeof(mmCP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &mmCP_ME_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &mmCP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &mmCP_ME_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &mmCP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &mmCP_ME_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &mmCP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &mmCP_ME_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &mmCP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_LO", REG_MMIO, 0xc069, &mmCP_ME_MC_WADDR_LO[0], sizeof(mmCP_ME_MC_WADDR_LO)/sizeof(mmCP_ME_MC_WADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_HI", REG_MMIO, 0xc06a, &mmCP_ME_MC_WADDR_HI[0], sizeof(mmCP_ME_MC_WADDR_HI)/sizeof(mmCP_ME_MC_WADDR_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_LO", REG_MMIO, 0xc06b, &mmCP_ME_MC_WDATA_LO[0], sizeof(mmCP_ME_MC_WDATA_LO)/sizeof(mmCP_ME_MC_WDATA_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_HI", REG_MMIO, 0xc06c, &mmCP_ME_MC_WDATA_HI[0], sizeof(mmCP_ME_MC_WDATA_HI)/sizeof(mmCP_ME_MC_WDATA_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_LO", REG_MMIO, 0xc06d, &mmCP_ME_MC_RADDR_LO[0], sizeof(mmCP_ME_MC_RADDR_LO)/sizeof(mmCP_ME_MC_RADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_HI", REG_MMIO, 0xc06e, &mmCP_ME_MC_RADDR_HI[0], sizeof(mmCP_ME_MC_RADDR_HI)/sizeof(mmCP_ME_MC_RADDR_HI[0]), 0, 0 },
+	{ "mmCP_SEM_WAIT_TIMER", REG_MMIO, 0xc06f, &mmCP_SEM_WAIT_TIMER[0], sizeof(mmCP_SEM_WAIT_TIMER)/sizeof(mmCP_SEM_WAIT_TIMER[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_LO", REG_MMIO, 0xc070, &mmCP_SIG_SEM_ADDR_LO[0], sizeof(mmCP_SIG_SEM_ADDR_LO)/sizeof(mmCP_SIG_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_HI", REG_MMIO, 0xc071, &mmCP_SIG_SEM_ADDR_HI[0], sizeof(mmCP_SIG_SEM_ADDR_HI)/sizeof(mmCP_SIG_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_WAIT_REG_MEM_TIMEOUT", REG_MMIO, 0xc074, &mmCP_WAIT_REG_MEM_TIMEOUT[0], sizeof(mmCP_WAIT_REG_MEM_TIMEOUT)/sizeof(mmCP_WAIT_REG_MEM_TIMEOUT[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_LO", REG_MMIO, 0xc075, &mmCP_WAIT_SEM_ADDR_LO[0], sizeof(mmCP_WAIT_SEM_ADDR_LO)/sizeof(mmCP_WAIT_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_HI", REG_MMIO, 0xc076, &mmCP_WAIT_SEM_ADDR_HI[0], sizeof(mmCP_WAIT_SEM_ADDR_HI)/sizeof(mmCP_WAIT_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_CONTROL", REG_MMIO, 0xc077, &mmCP_DMA_PFP_CONTROL[0], sizeof(mmCP_DMA_PFP_CONTROL)/sizeof(mmCP_DMA_PFP_CONTROL[0]), 0, 0 },
+	{ "mmCP_DMA_ME_CONTROL", REG_MMIO, 0xc078, &mmCP_DMA_ME_CONTROL[0], sizeof(mmCP_DMA_ME_CONTROL)/sizeof(mmCP_DMA_ME_CONTROL[0]), 0, 0 },
+	{ "mmCP_COHER_BASE_HI", REG_MMIO, 0xc079, &mmCP_COHER_BASE_HI[0], sizeof(mmCP_COHER_BASE_HI)/sizeof(mmCP_COHER_BASE_HI[0]), 0, 0 },
+	{ "mmCP_COHER_START_DELAY", REG_MMIO, 0xc07b, &mmCP_COHER_START_DELAY[0], sizeof(mmCP_COHER_START_DELAY)/sizeof(mmCP_COHER_START_DELAY[0]), 0, 0 },
+	{ "mmCP_COHER_CNTL", REG_MMIO, 0xc07c, &mmCP_COHER_CNTL[0], sizeof(mmCP_COHER_CNTL)/sizeof(mmCP_COHER_CNTL[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE", REG_MMIO, 0xc07d, &mmCP_COHER_SIZE[0], sizeof(mmCP_COHER_SIZE)/sizeof(mmCP_COHER_SIZE[0]), 0, 0 },
+	{ "mmCP_COHER_BASE", REG_MMIO, 0xc07e, &mmCP_COHER_BASE[0], sizeof(mmCP_COHER_BASE)/sizeof(mmCP_COHER_BASE[0]), 0, 0 },
+	{ "mmCP_COHER_STATUS", REG_MMIO, 0xc07f, &mmCP_COHER_STATUS[0], sizeof(mmCP_COHER_STATUS)/sizeof(mmCP_COHER_STATUS[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR", REG_MMIO, 0xc080, &mmCP_DMA_ME_SRC_ADDR[0], sizeof(mmCP_DMA_ME_SRC_ADDR)/sizeof(mmCP_DMA_ME_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR_HI", REG_MMIO, 0xc081, &mmCP_DMA_ME_SRC_ADDR_HI[0], sizeof(mmCP_DMA_ME_SRC_ADDR_HI)/sizeof(mmCP_DMA_ME_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR", REG_MMIO, 0xc082, &mmCP_DMA_ME_DST_ADDR[0], sizeof(mmCP_DMA_ME_DST_ADDR)/sizeof(mmCP_DMA_ME_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR_HI", REG_MMIO, 0xc083, &mmCP_DMA_ME_DST_ADDR_HI[0], sizeof(mmCP_DMA_ME_DST_ADDR_HI)/sizeof(mmCP_DMA_ME_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_COMMAND", REG_MMIO, 0xc084, &mmCP_DMA_ME_COMMAND[0], sizeof(mmCP_DMA_ME_COMMAND)/sizeof(mmCP_DMA_ME_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR", REG_MMIO, 0xc085, &mmCP_DMA_PFP_SRC_ADDR[0], sizeof(mmCP_DMA_PFP_SRC_ADDR)/sizeof(mmCP_DMA_PFP_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR_HI", REG_MMIO, 0xc086, &mmCP_DMA_PFP_SRC_ADDR_HI[0], sizeof(mmCP_DMA_PFP_SRC_ADDR_HI)/sizeof(mmCP_DMA_PFP_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR", REG_MMIO, 0xc087, &mmCP_DMA_PFP_DST_ADDR[0], sizeof(mmCP_DMA_PFP_DST_ADDR)/sizeof(mmCP_DMA_PFP_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR_HI", REG_MMIO, 0xc088, &mmCP_DMA_PFP_DST_ADDR_HI[0], sizeof(mmCP_DMA_PFP_DST_ADDR_HI)/sizeof(mmCP_DMA_PFP_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_COMMAND", REG_MMIO, 0xc089, &mmCP_DMA_PFP_COMMAND[0], sizeof(mmCP_DMA_PFP_COMMAND)/sizeof(mmCP_DMA_PFP_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_CNTL", REG_MMIO, 0xc08a, &mmCP_DMA_CNTL[0], sizeof(mmCP_DMA_CNTL)/sizeof(mmCP_DMA_CNTL[0]), 0, 0 },
+	{ "mmCP_DMA_READ_TAGS", REG_MMIO, 0xc08b, &mmCP_DMA_READ_TAGS[0], sizeof(mmCP_DMA_READ_TAGS)/sizeof(mmCP_DMA_READ_TAGS[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE_HI", REG_MMIO, 0xc08c, &mmCP_COHER_SIZE_HI[0], sizeof(mmCP_COHER_SIZE_HI)/sizeof(mmCP_COHER_SIZE_HI[0]), 0, 0 },
+	{ "mmCP_PFP_IB_CONTROL", REG_MMIO, 0xc08d, &mmCP_PFP_IB_CONTROL[0], sizeof(mmCP_PFP_IB_CONTROL)/sizeof(mmCP_PFP_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_PFP_LOAD_CONTROL", REG_MMIO, 0xc08e, &mmCP_PFP_LOAD_CONTROL[0], sizeof(mmCP_PFP_LOAD_CONTROL)/sizeof(mmCP_PFP_LOAD_CONTROL[0]), 0, 0 },
+	{ "mmCP_SCRATCH_INDEX", REG_MMIO, 0xc08f, &mmCP_SCRATCH_INDEX[0], sizeof(mmCP_SCRATCH_INDEX)/sizeof(mmCP_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_SCRATCH_DATA", REG_MMIO, 0xc090, &mmCP_SCRATCH_DATA[0], sizeof(mmCP_SCRATCH_DATA)/sizeof(mmCP_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_RB_OFFSET", REG_MMIO, 0xc091, &mmCP_RB_OFFSET[0], sizeof(mmCP_RB_OFFSET)/sizeof(mmCP_RB_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_OFFSET", REG_MMIO, 0xc092, &mmCP_IB1_OFFSET[0], sizeof(mmCP_IB1_OFFSET)/sizeof(mmCP_IB1_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB2_OFFSET", REG_MMIO, 0xc093, &mmCP_IB2_OFFSET[0], sizeof(mmCP_IB2_OFFSET)/sizeof(mmCP_IB2_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_BEGIN", REG_MMIO, 0xc094, &mmCP_IB1_PREAMBLE_BEGIN[0], sizeof(mmCP_IB1_PREAMBLE_BEGIN)/sizeof(mmCP_IB1_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_END", REG_MMIO, 0xc095, &mmCP_IB1_PREAMBLE_END[0], sizeof(mmCP_IB1_PREAMBLE_END)/sizeof(mmCP_IB1_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_BEGIN", REG_MMIO, 0xc096, &mmCP_IB2_PREAMBLE_BEGIN[0], sizeof(mmCP_IB2_PREAMBLE_BEGIN)/sizeof(mmCP_IB2_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_END", REG_MMIO, 0xc097, &mmCP_IB2_PREAMBLE_END[0], sizeof(mmCP_IB2_PREAMBLE_END)/sizeof(mmCP_IB2_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_CE_IB1_OFFSET", REG_MMIO, 0xc098, &mmCP_CE_IB1_OFFSET[0], sizeof(mmCP_CE_IB1_OFFSET)/sizeof(mmCP_CE_IB1_OFFSET[0]), 0, 0 },
+	{ "mmCP_CE_IB2_OFFSET", REG_MMIO, 0xc099, &mmCP_CE_IB2_OFFSET[0], sizeof(mmCP_CE_IB2_OFFSET)/sizeof(mmCP_CE_IB2_OFFSET[0]), 0, 0 },
+	{ "mmCP_CE_COUNTER", REG_MMIO, 0xc09a, &mmCP_CE_COUNTER[0], sizeof(mmCP_CE_COUNTER)/sizeof(mmCP_CE_COUNTER[0]), 0, 0 },
+	{ "mmCP_CE_RB_OFFSET", REG_MMIO, 0xc09b, &mmCP_CE_RB_OFFSET[0], sizeof(mmCP_CE_RB_OFFSET)/sizeof(mmCP_CE_RB_OFFSET[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_LO", REG_MMIO, 0xc0c3, &mmCP_CE_INIT_BASE_LO[0], sizeof(mmCP_CE_INIT_BASE_LO)/sizeof(mmCP_CE_INIT_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_HI", REG_MMIO, 0xc0c4, &mmCP_CE_INIT_BASE_HI[0], sizeof(mmCP_CE_INIT_BASE_HI)/sizeof(mmCP_CE_INIT_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BUFSZ", REG_MMIO, 0xc0c5, &mmCP_CE_INIT_BUFSZ[0], sizeof(mmCP_CE_INIT_BUFSZ)/sizeof(mmCP_CE_INIT_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_LO", REG_MMIO, 0xc0c6, &mmCP_CE_IB1_BASE_LO[0], sizeof(mmCP_CE_IB1_BASE_LO)/sizeof(mmCP_CE_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_HI", REG_MMIO, 0xc0c7, &mmCP_CE_IB1_BASE_HI[0], sizeof(mmCP_CE_IB1_BASE_HI)/sizeof(mmCP_CE_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BUFSZ", REG_MMIO, 0xc0c8, &mmCP_CE_IB1_BUFSZ[0], sizeof(mmCP_CE_IB1_BUFSZ)/sizeof(mmCP_CE_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_LO", REG_MMIO, 0xc0c9, &mmCP_CE_IB2_BASE_LO[0], sizeof(mmCP_CE_IB2_BASE_LO)/sizeof(mmCP_CE_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_HI", REG_MMIO, 0xc0ca, &mmCP_CE_IB2_BASE_HI[0], sizeof(mmCP_CE_IB2_BASE_HI)/sizeof(mmCP_CE_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BUFSZ", REG_MMIO, 0xc0cb, &mmCP_CE_IB2_BUFSZ[0], sizeof(mmCP_CE_IB2_BUFSZ)/sizeof(mmCP_CE_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_LO", REG_MMIO, 0xc0cc, &mmCP_IB1_BASE_LO[0], sizeof(mmCP_IB1_BASE_LO)/sizeof(mmCP_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_HI", REG_MMIO, 0xc0cd, &mmCP_IB1_BASE_HI[0], sizeof(mmCP_IB1_BASE_HI)/sizeof(mmCP_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB1_BUFSZ", REG_MMIO, 0xc0ce, &mmCP_IB1_BUFSZ[0], sizeof(mmCP_IB1_BUFSZ)/sizeof(mmCP_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_LO", REG_MMIO, 0xc0cf, &mmCP_IB2_BASE_LO[0], sizeof(mmCP_IB2_BASE_LO)/sizeof(mmCP_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_HI", REG_MMIO, 0xc0d0, &mmCP_IB2_BASE_HI[0], sizeof(mmCP_IB2_BASE_HI)/sizeof(mmCP_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB2_BUFSZ", REG_MMIO, 0xc0d1, &mmCP_IB2_BUFSZ[0], sizeof(mmCP_IB2_BUFSZ)/sizeof(mmCP_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_ST_BASE_LO", REG_MMIO, 0xc0d2, &mmCP_ST_BASE_LO[0], sizeof(mmCP_ST_BASE_LO)/sizeof(mmCP_ST_BASE_LO[0]), 0, 0 },
+	{ "mmCP_ST_BASE_HI", REG_MMIO, 0xc0d3, &mmCP_ST_BASE_HI[0], sizeof(mmCP_ST_BASE_HI)/sizeof(mmCP_ST_BASE_HI[0]), 0, 0 },
+	{ "mmCP_ST_BUFSZ", REG_MMIO, 0xc0d4, &mmCP_ST_BUFSZ[0], sizeof(mmCP_ST_BUFSZ)/sizeof(mmCP_ST_BUFSZ[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_EVENT_CNTL", REG_MMIO, 0xc0d5, &mmCP_EOP_DONE_EVENT_CNTL[0], sizeof(mmCP_EOP_DONE_EVENT_CNTL)/sizeof(mmCP_EOP_DONE_EVENT_CNTL[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_CNTL", REG_MMIO, 0xc0d6, &mmCP_EOP_DONE_DATA_CNTL[0], sizeof(mmCP_EOP_DONE_DATA_CNTL)/sizeof(mmCP_EOP_DONE_DATA_CNTL[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_CNTX_ID", REG_MMIO, 0xc0d7, &mmCP_EOP_DONE_CNTX_ID[0], sizeof(mmCP_EOP_DONE_CNTX_ID)/sizeof(mmCP_EOP_DONE_CNTX_ID[0]), 0, 0 },
+	{ "mmCP_PFP_COMPLETION_STATUS", REG_MMIO, 0xc0ec, &mmCP_PFP_COMPLETION_STATUS[0], sizeof(mmCP_PFP_COMPLETION_STATUS)/sizeof(mmCP_PFP_COMPLETION_STATUS[0]), 0, 0 },
+	{ "mmCP_CE_COMPLETION_STATUS", REG_MMIO, 0xc0ed, &mmCP_CE_COMPLETION_STATUS[0], sizeof(mmCP_CE_COMPLETION_STATUS)/sizeof(mmCP_CE_COMPLETION_STATUS[0]), 0, 0 },
+	{ "mmCP_PRED_NOT_VISIBLE", REG_MMIO, 0xc0ee, &mmCP_PRED_NOT_VISIBLE[0], sizeof(mmCP_PRED_NOT_VISIBLE)/sizeof(mmCP_PRED_NOT_VISIBLE[0]), 0, 0 },
+	{ "mmCP_PFP_METADATA_BASE_ADDR", REG_MMIO, 0xc0f0, &mmCP_PFP_METADATA_BASE_ADDR[0], sizeof(mmCP_PFP_METADATA_BASE_ADDR)/sizeof(mmCP_PFP_METADATA_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_METADATA_BASE_ADDR_HI", REG_MMIO, 0xc0f1, &mmCP_PFP_METADATA_BASE_ADDR_HI[0], sizeof(mmCP_PFP_METADATA_BASE_ADDR_HI)/sizeof(mmCP_PFP_METADATA_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_CE_METADATA_BASE_ADDR", REG_MMIO, 0xc0f2, &mmCP_CE_METADATA_BASE_ADDR[0], sizeof(mmCP_CE_METADATA_BASE_ADDR)/sizeof(mmCP_CE_METADATA_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_CE_METADATA_BASE_ADDR_HI", REG_MMIO, 0xc0f3, &mmCP_CE_METADATA_BASE_ADDR_HI[0], sizeof(mmCP_CE_METADATA_BASE_ADDR_HI)/sizeof(mmCP_CE_METADATA_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DRAW_INDX_INDR_ADDR", REG_MMIO, 0xc0f4, &mmCP_DRAW_INDX_INDR_ADDR[0], sizeof(mmCP_DRAW_INDX_INDR_ADDR)/sizeof(mmCP_DRAW_INDX_INDR_ADDR[0]), 0, 0 },
+	{ "mmCP_DRAW_INDX_INDR_ADDR_HI", REG_MMIO, 0xc0f5, &mmCP_DRAW_INDX_INDR_ADDR_HI[0], sizeof(mmCP_DRAW_INDX_INDR_ADDR_HI)/sizeof(mmCP_DRAW_INDX_INDR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DISPATCH_INDR_ADDR", REG_MMIO, 0xc0f6, &mmCP_DISPATCH_INDR_ADDR[0], sizeof(mmCP_DISPATCH_INDR_ADDR)/sizeof(mmCP_DISPATCH_INDR_ADDR[0]), 0, 0 },
+	{ "mmCP_DISPATCH_INDR_ADDR_HI", REG_MMIO, 0xc0f7, &mmCP_DISPATCH_INDR_ADDR_HI[0], sizeof(mmCP_DISPATCH_INDR_ADDR_HI)/sizeof(mmCP_DISPATCH_INDR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_INDEX_BASE_ADDR", REG_MMIO, 0xc0f8, &mmCP_INDEX_BASE_ADDR[0], sizeof(mmCP_INDEX_BASE_ADDR)/sizeof(mmCP_INDEX_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_INDEX_BASE_ADDR_HI", REG_MMIO, 0xc0f9, &mmCP_INDEX_BASE_ADDR_HI[0], sizeof(mmCP_INDEX_BASE_ADDR_HI)/sizeof(mmCP_INDEX_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_INDEX_TYPE", REG_MMIO, 0xc0fa, &mmCP_INDEX_TYPE[0], sizeof(mmCP_INDEX_TYPE)/sizeof(mmCP_INDEX_TYPE[0]), 0, 0 },
+	{ "mmCP_GDS_BKUP_ADDR", REG_MMIO, 0xc0fb, &mmCP_GDS_BKUP_ADDR[0], sizeof(mmCP_GDS_BKUP_ADDR)/sizeof(mmCP_GDS_BKUP_ADDR[0]), 0, 0 },
+	{ "mmCP_GDS_BKUP_ADDR_HI", REG_MMIO, 0xc0fc, &mmCP_GDS_BKUP_ADDR_HI[0], sizeof(mmCP_GDS_BKUP_ADDR_HI)/sizeof(mmCP_GDS_BKUP_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_SAMPLE_STATUS", REG_MMIO, 0xc0fd, &mmCP_SAMPLE_STATUS[0], sizeof(mmCP_SAMPLE_STATUS)/sizeof(mmCP_SAMPLE_STATUS[0]), 0, 0 },
+	{ "mmGRBM_GFX_INDEX", REG_MMIO, 0xc200, &mmGRBM_GFX_INDEX[0], sizeof(mmGRBM_GFX_INDEX)/sizeof(mmGRBM_GFX_INDEX[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_SIZE", REG_MMIO, 0xc240, &mmVGT_ESGS_RING_SIZE[0], sizeof(mmVGT_ESGS_RING_SIZE)/sizeof(mmVGT_ESGS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_SIZE", REG_MMIO, 0xc241, &mmVGT_GSVS_RING_SIZE[0], sizeof(mmVGT_GSVS_RING_SIZE)/sizeof(mmVGT_GSVS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVE_TYPE", REG_MMIO, 0xc242, &mmVGT_PRIMITIVE_TYPE[0], sizeof(mmVGT_PRIMITIVE_TYPE)/sizeof(mmVGT_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_INDEX_TYPE", REG_MMIO, 0xc243, &mmVGT_INDEX_TYPE[0], sizeof(mmVGT_INDEX_TYPE)/sizeof(mmVGT_INDEX_TYPE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0", REG_MMIO, 0xc244, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1", REG_MMIO, 0xc245, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2", REG_MMIO, 0xc246, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3", REG_MMIO, 0xc247, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_NUM_INDICES", REG_MMIO, 0xc24c, &mmVGT_NUM_INDICES[0], sizeof(mmVGT_NUM_INDICES)/sizeof(mmVGT_NUM_INDICES[0]), 0, 0 },
+	{ "mmVGT_NUM_INSTANCES", REG_MMIO, 0xc24d, &mmVGT_NUM_INSTANCES[0], sizeof(mmVGT_NUM_INSTANCES)/sizeof(mmVGT_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_TF_RING_SIZE", REG_MMIO, 0xc24e, &mmVGT_TF_RING_SIZE[0], sizeof(mmVGT_TF_RING_SIZE)/sizeof(mmVGT_TF_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_HS_OFFCHIP_PARAM", REG_MMIO, 0xc24f, &mmVGT_HS_OFFCHIP_PARAM[0], sizeof(mmVGT_HS_OFFCHIP_PARAM)/sizeof(mmVGT_HS_OFFCHIP_PARAM[0]), 0, 0 },
+	{ "mmVGT_TF_MEMORY_BASE", REG_MMIO, 0xc250, &mmVGT_TF_MEMORY_BASE[0], sizeof(mmVGT_TF_MEMORY_BASE)/sizeof(mmVGT_TF_MEMORY_BASE[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_VALUE", REG_MMIO, 0xc280, &mmPA_SU_LINE_STIPPLE_VALUE[0], sizeof(mmPA_SU_LINE_STIPPLE_VALUE)/sizeof(mmPA_SU_LINE_STIPPLE_VALUE[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE_STATE", REG_MMIO, 0xc281, &mmPA_SC_LINE_STIPPLE_STATE[0], sizeof(mmPA_SC_LINE_STIPPLE_STATE)/sizeof(mmPA_SC_LINE_STIPPLE_STATE[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MIN_0", REG_MMIO, 0xc284, &mmPA_SC_SCREEN_EXTENT_MIN_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MAX_0", REG_MMIO, 0xc285, &mmPA_SC_SCREEN_EXTENT_MAX_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MIN_1", REG_MMIO, 0xc286, &mmPA_SC_SCREEN_EXTENT_MIN_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MAX_1", REG_MMIO, 0xc28b, &mmPA_SC_SCREEN_EXTENT_MAX_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a0, &mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a1, &mmPA_SC_P3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_V", REG_MMIO, 0xc2a2, &mmPA_SC_P3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2a3, &mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2a4, &mmPA_SC_P3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a8, &mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a9, &mmPA_SC_HP3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_V", REG_MMIO, 0xc2aa, &mmPA_SC_HP3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2ab, &mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2ac, &mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2b0, &mmPA_SC_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_H", REG_MMIO, 0xc2b1, &mmPA_SC_TRAP_SCREEN_H[0], sizeof(mmPA_SC_TRAP_SCREEN_H)/sizeof(mmPA_SC_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_V", REG_MMIO, 0xc2b2, &mmPA_SC_TRAP_SCREEN_V[0], sizeof(mmPA_SC_TRAP_SCREEN_V)/sizeof(mmPA_SC_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2b3, &mmPA_SC_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2b4, &mmPA_SC_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE", REG_MMIO, 0xc330, &mmSQ_THREAD_TRACE_BASE[0], sizeof(mmSQ_THREAD_TRACE_BASE)/sizeof(mmSQ_THREAD_TRACE_BASE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_SIZE", REG_MMIO, 0xc331, &mmSQ_THREAD_TRACE_SIZE[0], sizeof(mmSQ_THREAD_TRACE_SIZE)/sizeof(mmSQ_THREAD_TRACE_SIZE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MASK", REG_MMIO, 0xc332, &mmSQ_THREAD_TRACE_MASK[0], sizeof(mmSQ_THREAD_TRACE_MASK)/sizeof(mmSQ_THREAD_TRACE_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK", REG_MMIO, 0xc333, &mmSQ_THREAD_TRACE_TOKEN_MASK[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_PERF_MASK", REG_MMIO, 0xc334, &mmSQ_THREAD_TRACE_PERF_MASK[0], sizeof(mmSQ_THREAD_TRACE_PERF_MASK)/sizeof(mmSQ_THREAD_TRACE_PERF_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CTRL", REG_MMIO, 0xc335, &mmSQ_THREAD_TRACE_CTRL[0], sizeof(mmSQ_THREAD_TRACE_CTRL)/sizeof(mmSQ_THREAD_TRACE_CTRL[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MODE", REG_MMIO, 0xc336, &mmSQ_THREAD_TRACE_MODE[0], sizeof(mmSQ_THREAD_TRACE_MODE)/sizeof(mmSQ_THREAD_TRACE_MODE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE2", REG_MMIO, 0xc337, &mmSQ_THREAD_TRACE_BASE2[0], sizeof(mmSQ_THREAD_TRACE_BASE2)/sizeof(mmSQ_THREAD_TRACE_BASE2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK2", REG_MMIO, 0xc338, &mmSQ_THREAD_TRACE_TOKEN_MASK2[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WPTR", REG_MMIO, 0xc339, &mmSQ_THREAD_TRACE_WPTR[0], sizeof(mmSQ_THREAD_TRACE_WPTR)/sizeof(mmSQ_THREAD_TRACE_WPTR[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_STATUS", REG_MMIO, 0xc33a, &mmSQ_THREAD_TRACE_STATUS[0], sizeof(mmSQ_THREAD_TRACE_STATUS)/sizeof(mmSQ_THREAD_TRACE_STATUS[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_HIWATER", REG_MMIO, 0xc33b, &mmSQ_THREAD_TRACE_HIWATER[0], sizeof(mmSQ_THREAD_TRACE_HIWATER)/sizeof(mmSQ_THREAD_TRACE_HIWATER[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_0", REG_MMIO, 0xc340, &mmSQ_THREAD_TRACE_USERDATA_0[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_0)/sizeof(mmSQ_THREAD_TRACE_USERDATA_0[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_1", REG_MMIO, 0xc341, &mmSQ_THREAD_TRACE_USERDATA_1[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_1)/sizeof(mmSQ_THREAD_TRACE_USERDATA_1[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_2", REG_MMIO, 0xc342, &mmSQ_THREAD_TRACE_USERDATA_2[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_2)/sizeof(mmSQ_THREAD_TRACE_USERDATA_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_3", REG_MMIO, 0xc343, &mmSQ_THREAD_TRACE_USERDATA_3[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_3)/sizeof(mmSQ_THREAD_TRACE_USERDATA_3[0]), 0, 0 },
+	{ "mmSQC_CACHES", REG_MMIO, 0xc348, &mmSQC_CACHES[0], sizeof(mmSQC_CACHES)/sizeof(mmSQC_CACHES[0]), 0, 0 },
+	{ "mmSQC_WRITEBACK", REG_MMIO, 0xc349, &mmSQC_WRITEBACK[0], sizeof(mmSQC_WRITEBACK)/sizeof(mmSQC_WRITEBACK[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR", REG_MMIO, 0xc380, &mmTA_CS_BC_BASE_ADDR[0], sizeof(mmTA_CS_BC_BASE_ADDR)/sizeof(mmTA_CS_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR_HI", REG_MMIO, 0xc381, &mmTA_CS_BC_BASE_ADDR_HI[0], sizeof(mmTA_CS_BC_BASE_ADDR_HI)/sizeof(mmTA_CS_BC_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT0_LOW", REG_MMIO, 0xc3c0, &mmDB_OCCLUSION_COUNT0_LOW[0], sizeof(mmDB_OCCLUSION_COUNT0_LOW)/sizeof(mmDB_OCCLUSION_COUNT0_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT0_HI", REG_MMIO, 0xc3c1, &mmDB_OCCLUSION_COUNT0_HI[0], sizeof(mmDB_OCCLUSION_COUNT0_HI)/sizeof(mmDB_OCCLUSION_COUNT0_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT1_LOW", REG_MMIO, 0xc3c2, &mmDB_OCCLUSION_COUNT1_LOW[0], sizeof(mmDB_OCCLUSION_COUNT1_LOW)/sizeof(mmDB_OCCLUSION_COUNT1_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT1_HI", REG_MMIO, 0xc3c3, &mmDB_OCCLUSION_COUNT1_HI[0], sizeof(mmDB_OCCLUSION_COUNT1_HI)/sizeof(mmDB_OCCLUSION_COUNT1_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT2_LOW", REG_MMIO, 0xc3c4, &mmDB_OCCLUSION_COUNT2_LOW[0], sizeof(mmDB_OCCLUSION_COUNT2_LOW)/sizeof(mmDB_OCCLUSION_COUNT2_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT2_HI", REG_MMIO, 0xc3c5, &mmDB_OCCLUSION_COUNT2_HI[0], sizeof(mmDB_OCCLUSION_COUNT2_HI)/sizeof(mmDB_OCCLUSION_COUNT2_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT3_LOW", REG_MMIO, 0xc3c6, &mmDB_OCCLUSION_COUNT3_LOW[0], sizeof(mmDB_OCCLUSION_COUNT3_LOW)/sizeof(mmDB_OCCLUSION_COUNT3_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT3_HI", REG_MMIO, 0xc3c7, &mmDB_OCCLUSION_COUNT3_HI[0], sizeof(mmDB_OCCLUSION_COUNT3_HI)/sizeof(mmDB_OCCLUSION_COUNT3_HI[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_LOW", REG_MMIO, 0xc3fe, &mmDB_ZPASS_COUNT_LOW[0], sizeof(mmDB_ZPASS_COUNT_LOW)/sizeof(mmDB_ZPASS_COUNT_LOW[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_HI", REG_MMIO, 0xc3ff, &mmDB_ZPASS_COUNT_HI[0], sizeof(mmDB_ZPASS_COUNT_HI)/sizeof(mmDB_ZPASS_COUNT_HI[0]), 0, 0 },
+	{ "mmGDS_RD_ADDR", REG_MMIO, 0xc400, &mmGDS_RD_ADDR[0], sizeof(mmGDS_RD_ADDR)/sizeof(mmGDS_RD_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_DATA", REG_MMIO, 0xc401, &mmGDS_RD_DATA[0], sizeof(mmGDS_RD_DATA)/sizeof(mmGDS_RD_DATA[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_ADDR", REG_MMIO, 0xc402, &mmGDS_RD_BURST_ADDR[0], sizeof(mmGDS_RD_BURST_ADDR)/sizeof(mmGDS_RD_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_COUNT", REG_MMIO, 0xc403, &mmGDS_RD_BURST_COUNT[0], sizeof(mmGDS_RD_BURST_COUNT)/sizeof(mmGDS_RD_BURST_COUNT[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_DATA", REG_MMIO, 0xc404, &mmGDS_RD_BURST_DATA[0], sizeof(mmGDS_RD_BURST_DATA)/sizeof(mmGDS_RD_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_ADDR", REG_MMIO, 0xc405, &mmGDS_WR_ADDR[0], sizeof(mmGDS_WR_ADDR)/sizeof(mmGDS_WR_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_DATA", REG_MMIO, 0xc406, &mmGDS_WR_DATA[0], sizeof(mmGDS_WR_DATA)/sizeof(mmGDS_WR_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_ADDR", REG_MMIO, 0xc407, &mmGDS_WR_BURST_ADDR[0], sizeof(mmGDS_WR_BURST_ADDR)/sizeof(mmGDS_WR_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_DATA", REG_MMIO, 0xc408, &mmGDS_WR_BURST_DATA[0], sizeof(mmGDS_WR_BURST_DATA)/sizeof(mmGDS_WR_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WRITE_COMPLETE", REG_MMIO, 0xc409, &mmGDS_WRITE_COMPLETE[0], sizeof(mmGDS_WRITE_COMPLETE)/sizeof(mmGDS_WRITE_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_CNTL", REG_MMIO, 0xc40a, &mmGDS_ATOM_CNTL[0], sizeof(mmGDS_ATOM_CNTL)/sizeof(mmGDS_ATOM_CNTL[0]), 0, 0 },
+	{ "mmGDS_ATOM_COMPLETE", REG_MMIO, 0xc40b, &mmGDS_ATOM_COMPLETE[0], sizeof(mmGDS_ATOM_COMPLETE)/sizeof(mmGDS_ATOM_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_BASE", REG_MMIO, 0xc40c, &mmGDS_ATOM_BASE[0], sizeof(mmGDS_ATOM_BASE)/sizeof(mmGDS_ATOM_BASE[0]), 0, 0 },
+	{ "mmGDS_ATOM_SIZE", REG_MMIO, 0xc40d, &mmGDS_ATOM_SIZE[0], sizeof(mmGDS_ATOM_SIZE)/sizeof(mmGDS_ATOM_SIZE[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET0", REG_MMIO, 0xc40e, &mmGDS_ATOM_OFFSET0[0], sizeof(mmGDS_ATOM_OFFSET0)/sizeof(mmGDS_ATOM_OFFSET0[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET1", REG_MMIO, 0xc40f, &mmGDS_ATOM_OFFSET1[0], sizeof(mmGDS_ATOM_OFFSET1)/sizeof(mmGDS_ATOM_OFFSET1[0]), 0, 0 },
+	{ "mmGDS_ATOM_DST", REG_MMIO, 0xc410, &mmGDS_ATOM_DST[0], sizeof(mmGDS_ATOM_DST)/sizeof(mmGDS_ATOM_DST[0]), 0, 0 },
+	{ "mmGDS_ATOM_OP", REG_MMIO, 0xc411, &mmGDS_ATOM_OP[0], sizeof(mmGDS_ATOM_OP)/sizeof(mmGDS_ATOM_OP[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0", REG_MMIO, 0xc412, &mmGDS_ATOM_SRC0[0], sizeof(mmGDS_ATOM_SRC0)/sizeof(mmGDS_ATOM_SRC0[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0_U", REG_MMIO, 0xc413, &mmGDS_ATOM_SRC0_U[0], sizeof(mmGDS_ATOM_SRC0_U)/sizeof(mmGDS_ATOM_SRC0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1", REG_MMIO, 0xc414, &mmGDS_ATOM_SRC1[0], sizeof(mmGDS_ATOM_SRC1)/sizeof(mmGDS_ATOM_SRC1[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1_U", REG_MMIO, 0xc415, &mmGDS_ATOM_SRC1_U[0], sizeof(mmGDS_ATOM_SRC1_U)/sizeof(mmGDS_ATOM_SRC1_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0", REG_MMIO, 0xc416, &mmGDS_ATOM_READ0[0], sizeof(mmGDS_ATOM_READ0)/sizeof(mmGDS_ATOM_READ0[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0_U", REG_MMIO, 0xc417, &mmGDS_ATOM_READ0_U[0], sizeof(mmGDS_ATOM_READ0_U)/sizeof(mmGDS_ATOM_READ0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1", REG_MMIO, 0xc418, &mmGDS_ATOM_READ1[0], sizeof(mmGDS_ATOM_READ1)/sizeof(mmGDS_ATOM_READ1[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1_U", REG_MMIO, 0xc419, &mmGDS_ATOM_READ1_U[0], sizeof(mmGDS_ATOM_READ1_U)/sizeof(mmGDS_ATOM_READ1_U[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNTL", REG_MMIO, 0xc41a, &mmGDS_GWS_RESOURCE_CNTL[0], sizeof(mmGDS_GWS_RESOURCE_CNTL)/sizeof(mmGDS_GWS_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE", REG_MMIO, 0xc41b, &mmGDS_GWS_RESOURCE[0], sizeof(mmGDS_GWS_RESOURCE)/sizeof(mmGDS_GWS_RESOURCE[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNT", REG_MMIO, 0xc41c, &mmGDS_GWS_RESOURCE_CNT[0], sizeof(mmGDS_GWS_RESOURCE_CNT)/sizeof(mmGDS_GWS_RESOURCE_CNT[0]), 0, 0 },
+	{ "mmGDS_OA_CNTL", REG_MMIO, 0xc41d, &mmGDS_OA_CNTL[0], sizeof(mmGDS_OA_CNTL)/sizeof(mmGDS_OA_CNTL[0]), 0, 0 },
+	{ "mmGDS_OA_COUNTER", REG_MMIO, 0xc41e, &mmGDS_OA_COUNTER[0], sizeof(mmGDS_OA_COUNTER)/sizeof(mmGDS_OA_COUNTER[0]), 0, 0 },
+	{ "mmGDS_OA_ADDRESS", REG_MMIO, 0xc41f, &mmGDS_OA_ADDRESS[0], sizeof(mmGDS_OA_ADDRESS)/sizeof(mmGDS_OA_ADDRESS[0]), 0, 0 },
+	{ "mmGDS_OA_INCDEC", REG_MMIO, 0xc420, &mmGDS_OA_INCDEC[0], sizeof(mmGDS_OA_INCDEC)/sizeof(mmGDS_OA_INCDEC[0]), 0, 0 },
+	{ "mmGDS_OA_RING_SIZE", REG_MMIO, 0xc421, &mmGDS_OA_RING_SIZE[0], sizeof(mmGDS_OA_RING_SIZE)/sizeof(mmGDS_OA_RING_SIZE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG13", REG_SMC, 0xd, &ixCLIPPER_DEBUG_REG13[0], sizeof(ixCLIPPER_DEBUG_REG13)/sizeof(ixCLIPPER_DEBUG_REG13[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG13", REG_SMC, 0xd, &ixVGT_DEBUG_REG13[0], sizeof(ixVGT_DEBUG_REG13)/sizeof(ixVGT_DEBUG_REG13[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_LO", REG_MMIO, 0xd000, &mmCPG_PERFCOUNTER1_LO[0], sizeof(mmCPG_PERFCOUNTER1_LO)/sizeof(mmCPG_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_HI", REG_MMIO, 0xd001, &mmCPG_PERFCOUNTER1_HI[0], sizeof(mmCPG_PERFCOUNTER1_HI)/sizeof(mmCPG_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_LO", REG_MMIO, 0xd002, &mmCPG_PERFCOUNTER0_LO[0], sizeof(mmCPG_PERFCOUNTER0_LO)/sizeof(mmCPG_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_HI", REG_MMIO, 0xd003, &mmCPG_PERFCOUNTER0_HI[0], sizeof(mmCPG_PERFCOUNTER0_HI)/sizeof(mmCPG_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_LO", REG_MMIO, 0xd004, &mmCPC_PERFCOUNTER1_LO[0], sizeof(mmCPC_PERFCOUNTER1_LO)/sizeof(mmCPC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_HI", REG_MMIO, 0xd005, &mmCPC_PERFCOUNTER1_HI[0], sizeof(mmCPC_PERFCOUNTER1_HI)/sizeof(mmCPC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_LO", REG_MMIO, 0xd006, &mmCPC_PERFCOUNTER0_LO[0], sizeof(mmCPC_PERFCOUNTER0_LO)/sizeof(mmCPC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_HI", REG_MMIO, 0xd007, &mmCPC_PERFCOUNTER0_HI[0], sizeof(mmCPC_PERFCOUNTER0_HI)/sizeof(mmCPC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_LO", REG_MMIO, 0xd008, &mmCPF_PERFCOUNTER1_LO[0], sizeof(mmCPF_PERFCOUNTER1_LO)/sizeof(mmCPF_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_HI", REG_MMIO, 0xd009, &mmCPF_PERFCOUNTER1_HI[0], sizeof(mmCPF_PERFCOUNTER1_HI)/sizeof(mmCPF_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_LO", REG_MMIO, 0xd00a, &mmCPF_PERFCOUNTER0_LO[0], sizeof(mmCPF_PERFCOUNTER0_LO)/sizeof(mmCPF_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_HI", REG_MMIO, 0xd00b, &mmCPF_PERFCOUNTER0_HI[0], sizeof(mmCPF_PERFCOUNTER0_HI)/sizeof(mmCPF_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_LO", REG_MMIO, 0xd040, &mmGRBM_PERFCOUNTER0_LO[0], sizeof(mmGRBM_PERFCOUNTER0_LO)/sizeof(mmGRBM_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_HI", REG_MMIO, 0xd041, &mmGRBM_PERFCOUNTER0_HI[0], sizeof(mmGRBM_PERFCOUNTER0_HI)/sizeof(mmGRBM_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_LO", REG_MMIO, 0xd043, &mmGRBM_PERFCOUNTER1_LO[0], sizeof(mmGRBM_PERFCOUNTER1_LO)/sizeof(mmGRBM_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_HI", REG_MMIO, 0xd044, &mmGRBM_PERFCOUNTER1_HI[0], sizeof(mmGRBM_PERFCOUNTER1_HI)/sizeof(mmGRBM_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_LO", REG_MMIO, 0xd045, &mmGRBM_SE0_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE0_PERFCOUNTER_LO)/sizeof(mmGRBM_SE0_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_HI", REG_MMIO, 0xd046, &mmGRBM_SE0_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE0_PERFCOUNTER_HI)/sizeof(mmGRBM_SE0_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_LO", REG_MMIO, 0xd047, &mmGRBM_SE1_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE1_PERFCOUNTER_LO)/sizeof(mmGRBM_SE1_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_HI", REG_MMIO, 0xd048, &mmGRBM_SE1_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE1_PERFCOUNTER_HI)/sizeof(mmGRBM_SE1_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_LO", REG_MMIO, 0xd049, &mmGRBM_SE2_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE2_PERFCOUNTER_LO)/sizeof(mmGRBM_SE2_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_HI", REG_MMIO, 0xd04a, &mmGRBM_SE2_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE2_PERFCOUNTER_HI)/sizeof(mmGRBM_SE2_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_LO", REG_MMIO, 0xd04b, &mmGRBM_SE3_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE3_PERFCOUNTER_LO)/sizeof(mmGRBM_SE3_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_HI", REG_MMIO, 0xd04c, &mmGRBM_SE3_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE3_PERFCOUNTER_HI)/sizeof(mmGRBM_SE3_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_LO", REG_MMIO, 0xd080, &mmWD_PERFCOUNTER0_LO[0], sizeof(mmWD_PERFCOUNTER0_LO)/sizeof(mmWD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_HI", REG_MMIO, 0xd081, &mmWD_PERFCOUNTER0_HI[0], sizeof(mmWD_PERFCOUNTER0_HI)/sizeof(mmWD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_LO", REG_MMIO, 0xd082, &mmWD_PERFCOUNTER1_LO[0], sizeof(mmWD_PERFCOUNTER1_LO)/sizeof(mmWD_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_HI", REG_MMIO, 0xd083, &mmWD_PERFCOUNTER1_HI[0], sizeof(mmWD_PERFCOUNTER1_HI)/sizeof(mmWD_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_LO", REG_MMIO, 0xd084, &mmWD_PERFCOUNTER2_LO[0], sizeof(mmWD_PERFCOUNTER2_LO)/sizeof(mmWD_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_HI", REG_MMIO, 0xd085, &mmWD_PERFCOUNTER2_HI[0], sizeof(mmWD_PERFCOUNTER2_HI)/sizeof(mmWD_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_LO", REG_MMIO, 0xd086, &mmWD_PERFCOUNTER3_LO[0], sizeof(mmWD_PERFCOUNTER3_LO)/sizeof(mmWD_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_HI", REG_MMIO, 0xd087, &mmWD_PERFCOUNTER3_HI[0], sizeof(mmWD_PERFCOUNTER3_HI)/sizeof(mmWD_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_LO", REG_MMIO, 0xd088, &mmIA_PERFCOUNTER0_LO[0], sizeof(mmIA_PERFCOUNTER0_LO)/sizeof(mmIA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_HI", REG_MMIO, 0xd089, &mmIA_PERFCOUNTER0_HI[0], sizeof(mmIA_PERFCOUNTER0_HI)/sizeof(mmIA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_LO", REG_MMIO, 0xd08a, &mmIA_PERFCOUNTER1_LO[0], sizeof(mmIA_PERFCOUNTER1_LO)/sizeof(mmIA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_HI", REG_MMIO, 0xd08b, &mmIA_PERFCOUNTER1_HI[0], sizeof(mmIA_PERFCOUNTER1_HI)/sizeof(mmIA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_LO", REG_MMIO, 0xd08c, &mmIA_PERFCOUNTER2_LO[0], sizeof(mmIA_PERFCOUNTER2_LO)/sizeof(mmIA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_HI", REG_MMIO, 0xd08d, &mmIA_PERFCOUNTER2_HI[0], sizeof(mmIA_PERFCOUNTER2_HI)/sizeof(mmIA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_LO", REG_MMIO, 0xd08e, &mmIA_PERFCOUNTER3_LO[0], sizeof(mmIA_PERFCOUNTER3_LO)/sizeof(mmIA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_HI", REG_MMIO, 0xd08f, &mmIA_PERFCOUNTER3_HI[0], sizeof(mmIA_PERFCOUNTER3_HI)/sizeof(mmIA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_LO", REG_MMIO, 0xd090, &mmVGT_PERFCOUNTER0_LO[0], sizeof(mmVGT_PERFCOUNTER0_LO)/sizeof(mmVGT_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_HI", REG_MMIO, 0xd091, &mmVGT_PERFCOUNTER0_HI[0], sizeof(mmVGT_PERFCOUNTER0_HI)/sizeof(mmVGT_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_LO", REG_MMIO, 0xd092, &mmVGT_PERFCOUNTER1_LO[0], sizeof(mmVGT_PERFCOUNTER1_LO)/sizeof(mmVGT_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_HI", REG_MMIO, 0xd093, &mmVGT_PERFCOUNTER1_HI[0], sizeof(mmVGT_PERFCOUNTER1_HI)/sizeof(mmVGT_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_LO", REG_MMIO, 0xd094, &mmVGT_PERFCOUNTER2_LO[0], sizeof(mmVGT_PERFCOUNTER2_LO)/sizeof(mmVGT_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_HI", REG_MMIO, 0xd095, &mmVGT_PERFCOUNTER2_HI[0], sizeof(mmVGT_PERFCOUNTER2_HI)/sizeof(mmVGT_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_LO", REG_MMIO, 0xd096, &mmVGT_PERFCOUNTER3_LO[0], sizeof(mmVGT_PERFCOUNTER3_LO)/sizeof(mmVGT_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_HI", REG_MMIO, 0xd097, &mmVGT_PERFCOUNTER3_HI[0], sizeof(mmVGT_PERFCOUNTER3_HI)/sizeof(mmVGT_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_LO", REG_MMIO, 0xd100, &mmPA_SU_PERFCOUNTER0_LO[0], sizeof(mmPA_SU_PERFCOUNTER0_LO)/sizeof(mmPA_SU_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_HI", REG_MMIO, 0xd101, &mmPA_SU_PERFCOUNTER0_HI[0], sizeof(mmPA_SU_PERFCOUNTER0_HI)/sizeof(mmPA_SU_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_LO", REG_MMIO, 0xd102, &mmPA_SU_PERFCOUNTER1_LO[0], sizeof(mmPA_SU_PERFCOUNTER1_LO)/sizeof(mmPA_SU_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_HI", REG_MMIO, 0xd103, &mmPA_SU_PERFCOUNTER1_HI[0], sizeof(mmPA_SU_PERFCOUNTER1_HI)/sizeof(mmPA_SU_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_LO", REG_MMIO, 0xd104, &mmPA_SU_PERFCOUNTER2_LO[0], sizeof(mmPA_SU_PERFCOUNTER2_LO)/sizeof(mmPA_SU_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_HI", REG_MMIO, 0xd105, &mmPA_SU_PERFCOUNTER2_HI[0], sizeof(mmPA_SU_PERFCOUNTER2_HI)/sizeof(mmPA_SU_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_LO", REG_MMIO, 0xd106, &mmPA_SU_PERFCOUNTER3_LO[0], sizeof(mmPA_SU_PERFCOUNTER3_LO)/sizeof(mmPA_SU_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_HI", REG_MMIO, 0xd107, &mmPA_SU_PERFCOUNTER3_HI[0], sizeof(mmPA_SU_PERFCOUNTER3_HI)/sizeof(mmPA_SU_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_LO", REG_MMIO, 0xd140, &mmPA_SC_PERFCOUNTER0_LO[0], sizeof(mmPA_SC_PERFCOUNTER0_LO)/sizeof(mmPA_SC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_HI", REG_MMIO, 0xd141, &mmPA_SC_PERFCOUNTER0_HI[0], sizeof(mmPA_SC_PERFCOUNTER0_HI)/sizeof(mmPA_SC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_LO", REG_MMIO, 0xd142, &mmPA_SC_PERFCOUNTER1_LO[0], sizeof(mmPA_SC_PERFCOUNTER1_LO)/sizeof(mmPA_SC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_HI", REG_MMIO, 0xd143, &mmPA_SC_PERFCOUNTER1_HI[0], sizeof(mmPA_SC_PERFCOUNTER1_HI)/sizeof(mmPA_SC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_LO", REG_MMIO, 0xd144, &mmPA_SC_PERFCOUNTER2_LO[0], sizeof(mmPA_SC_PERFCOUNTER2_LO)/sizeof(mmPA_SC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_HI", REG_MMIO, 0xd145, &mmPA_SC_PERFCOUNTER2_HI[0], sizeof(mmPA_SC_PERFCOUNTER2_HI)/sizeof(mmPA_SC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_LO", REG_MMIO, 0xd146, &mmPA_SC_PERFCOUNTER3_LO[0], sizeof(mmPA_SC_PERFCOUNTER3_LO)/sizeof(mmPA_SC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_HI", REG_MMIO, 0xd147, &mmPA_SC_PERFCOUNTER3_HI[0], sizeof(mmPA_SC_PERFCOUNTER3_HI)/sizeof(mmPA_SC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_LO", REG_MMIO, 0xd148, &mmPA_SC_PERFCOUNTER4_LO[0], sizeof(mmPA_SC_PERFCOUNTER4_LO)/sizeof(mmPA_SC_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_HI", REG_MMIO, 0xd149, &mmPA_SC_PERFCOUNTER4_HI[0], sizeof(mmPA_SC_PERFCOUNTER4_HI)/sizeof(mmPA_SC_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_LO", REG_MMIO, 0xd14a, &mmPA_SC_PERFCOUNTER5_LO[0], sizeof(mmPA_SC_PERFCOUNTER5_LO)/sizeof(mmPA_SC_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_HI", REG_MMIO, 0xd14b, &mmPA_SC_PERFCOUNTER5_HI[0], sizeof(mmPA_SC_PERFCOUNTER5_HI)/sizeof(mmPA_SC_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_LO", REG_MMIO, 0xd14c, &mmPA_SC_PERFCOUNTER6_LO[0], sizeof(mmPA_SC_PERFCOUNTER6_LO)/sizeof(mmPA_SC_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_HI", REG_MMIO, 0xd14d, &mmPA_SC_PERFCOUNTER6_HI[0], sizeof(mmPA_SC_PERFCOUNTER6_HI)/sizeof(mmPA_SC_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_LO", REG_MMIO, 0xd14e, &mmPA_SC_PERFCOUNTER7_LO[0], sizeof(mmPA_SC_PERFCOUNTER7_LO)/sizeof(mmPA_SC_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_HI", REG_MMIO, 0xd14f, &mmPA_SC_PERFCOUNTER7_HI[0], sizeof(mmPA_SC_PERFCOUNTER7_HI)/sizeof(mmPA_SC_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_HI", REG_MMIO, 0xd180, &mmSPI_PERFCOUNTER0_HI[0], sizeof(mmSPI_PERFCOUNTER0_HI)/sizeof(mmSPI_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_LO", REG_MMIO, 0xd181, &mmSPI_PERFCOUNTER0_LO[0], sizeof(mmSPI_PERFCOUNTER0_LO)/sizeof(mmSPI_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_HI", REG_MMIO, 0xd182, &mmSPI_PERFCOUNTER1_HI[0], sizeof(mmSPI_PERFCOUNTER1_HI)/sizeof(mmSPI_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_LO", REG_MMIO, 0xd183, &mmSPI_PERFCOUNTER1_LO[0], sizeof(mmSPI_PERFCOUNTER1_LO)/sizeof(mmSPI_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_HI", REG_MMIO, 0xd184, &mmSPI_PERFCOUNTER2_HI[0], sizeof(mmSPI_PERFCOUNTER2_HI)/sizeof(mmSPI_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_LO", REG_MMIO, 0xd185, &mmSPI_PERFCOUNTER2_LO[0], sizeof(mmSPI_PERFCOUNTER2_LO)/sizeof(mmSPI_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_HI", REG_MMIO, 0xd186, &mmSPI_PERFCOUNTER3_HI[0], sizeof(mmSPI_PERFCOUNTER3_HI)/sizeof(mmSPI_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_LO", REG_MMIO, 0xd187, &mmSPI_PERFCOUNTER3_LO[0], sizeof(mmSPI_PERFCOUNTER3_LO)/sizeof(mmSPI_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_HI", REG_MMIO, 0xd188, &mmSPI_PERFCOUNTER4_HI[0], sizeof(mmSPI_PERFCOUNTER4_HI)/sizeof(mmSPI_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_LO", REG_MMIO, 0xd189, &mmSPI_PERFCOUNTER4_LO[0], sizeof(mmSPI_PERFCOUNTER4_LO)/sizeof(mmSPI_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_HI", REG_MMIO, 0xd18a, &mmSPI_PERFCOUNTER5_HI[0], sizeof(mmSPI_PERFCOUNTER5_HI)/sizeof(mmSPI_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_LO", REG_MMIO, 0xd18b, &mmSPI_PERFCOUNTER5_LO[0], sizeof(mmSPI_PERFCOUNTER5_LO)/sizeof(mmSPI_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_LO", REG_MMIO, 0xd1c0, &mmSQ_PERFCOUNTER0_LO[0], sizeof(mmSQ_PERFCOUNTER0_LO)/sizeof(mmSQ_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_HI", REG_MMIO, 0xd1c1, &mmSQ_PERFCOUNTER0_HI[0], sizeof(mmSQ_PERFCOUNTER0_HI)/sizeof(mmSQ_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_LO", REG_MMIO, 0xd1c2, &mmSQ_PERFCOUNTER1_LO[0], sizeof(mmSQ_PERFCOUNTER1_LO)/sizeof(mmSQ_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_HI", REG_MMIO, 0xd1c3, &mmSQ_PERFCOUNTER1_HI[0], sizeof(mmSQ_PERFCOUNTER1_HI)/sizeof(mmSQ_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_LO", REG_MMIO, 0xd1c4, &mmSQ_PERFCOUNTER2_LO[0], sizeof(mmSQ_PERFCOUNTER2_LO)/sizeof(mmSQ_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_HI", REG_MMIO, 0xd1c5, &mmSQ_PERFCOUNTER2_HI[0], sizeof(mmSQ_PERFCOUNTER2_HI)/sizeof(mmSQ_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_LO", REG_MMIO, 0xd1c6, &mmSQ_PERFCOUNTER3_LO[0], sizeof(mmSQ_PERFCOUNTER3_LO)/sizeof(mmSQ_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_HI", REG_MMIO, 0xd1c7, &mmSQ_PERFCOUNTER3_HI[0], sizeof(mmSQ_PERFCOUNTER3_HI)/sizeof(mmSQ_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_LO", REG_MMIO, 0xd1c8, &mmSQ_PERFCOUNTER4_LO[0], sizeof(mmSQ_PERFCOUNTER4_LO)/sizeof(mmSQ_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_HI", REG_MMIO, 0xd1c9, &mmSQ_PERFCOUNTER4_HI[0], sizeof(mmSQ_PERFCOUNTER4_HI)/sizeof(mmSQ_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_LO", REG_MMIO, 0xd1ca, &mmSQ_PERFCOUNTER5_LO[0], sizeof(mmSQ_PERFCOUNTER5_LO)/sizeof(mmSQ_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_HI", REG_MMIO, 0xd1cb, &mmSQ_PERFCOUNTER5_HI[0], sizeof(mmSQ_PERFCOUNTER5_HI)/sizeof(mmSQ_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_LO", REG_MMIO, 0xd1cc, &mmSQ_PERFCOUNTER6_LO[0], sizeof(mmSQ_PERFCOUNTER6_LO)/sizeof(mmSQ_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_HI", REG_MMIO, 0xd1cd, &mmSQ_PERFCOUNTER6_HI[0], sizeof(mmSQ_PERFCOUNTER6_HI)/sizeof(mmSQ_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_LO", REG_MMIO, 0xd1ce, &mmSQ_PERFCOUNTER7_LO[0], sizeof(mmSQ_PERFCOUNTER7_LO)/sizeof(mmSQ_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_HI", REG_MMIO, 0xd1cf, &mmSQ_PERFCOUNTER7_HI[0], sizeof(mmSQ_PERFCOUNTER7_HI)/sizeof(mmSQ_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_LO", REG_MMIO, 0xd1d0, &mmSQ_PERFCOUNTER8_LO[0], sizeof(mmSQ_PERFCOUNTER8_LO)/sizeof(mmSQ_PERFCOUNTER8_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_HI", REG_MMIO, 0xd1d1, &mmSQ_PERFCOUNTER8_HI[0], sizeof(mmSQ_PERFCOUNTER8_HI)/sizeof(mmSQ_PERFCOUNTER8_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_LO", REG_MMIO, 0xd1d2, &mmSQ_PERFCOUNTER9_LO[0], sizeof(mmSQ_PERFCOUNTER9_LO)/sizeof(mmSQ_PERFCOUNTER9_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_HI", REG_MMIO, 0xd1d3, &mmSQ_PERFCOUNTER9_HI[0], sizeof(mmSQ_PERFCOUNTER9_HI)/sizeof(mmSQ_PERFCOUNTER9_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_LO", REG_MMIO, 0xd1d4, &mmSQ_PERFCOUNTER10_LO[0], sizeof(mmSQ_PERFCOUNTER10_LO)/sizeof(mmSQ_PERFCOUNTER10_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_HI", REG_MMIO, 0xd1d5, &mmSQ_PERFCOUNTER10_HI[0], sizeof(mmSQ_PERFCOUNTER10_HI)/sizeof(mmSQ_PERFCOUNTER10_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_LO", REG_MMIO, 0xd1d6, &mmSQ_PERFCOUNTER11_LO[0], sizeof(mmSQ_PERFCOUNTER11_LO)/sizeof(mmSQ_PERFCOUNTER11_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_HI", REG_MMIO, 0xd1d7, &mmSQ_PERFCOUNTER11_HI[0], sizeof(mmSQ_PERFCOUNTER11_HI)/sizeof(mmSQ_PERFCOUNTER11_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_LO", REG_MMIO, 0xd1d8, &mmSQ_PERFCOUNTER12_LO[0], sizeof(mmSQ_PERFCOUNTER12_LO)/sizeof(mmSQ_PERFCOUNTER12_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_HI", REG_MMIO, 0xd1d9, &mmSQ_PERFCOUNTER12_HI[0], sizeof(mmSQ_PERFCOUNTER12_HI)/sizeof(mmSQ_PERFCOUNTER12_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_LO", REG_MMIO, 0xd1da, &mmSQ_PERFCOUNTER13_LO[0], sizeof(mmSQ_PERFCOUNTER13_LO)/sizeof(mmSQ_PERFCOUNTER13_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_HI", REG_MMIO, 0xd1db, &mmSQ_PERFCOUNTER13_HI[0], sizeof(mmSQ_PERFCOUNTER13_HI)/sizeof(mmSQ_PERFCOUNTER13_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_LO", REG_MMIO, 0xd1dc, &mmSQ_PERFCOUNTER14_LO[0], sizeof(mmSQ_PERFCOUNTER14_LO)/sizeof(mmSQ_PERFCOUNTER14_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_HI", REG_MMIO, 0xd1dd, &mmSQ_PERFCOUNTER14_HI[0], sizeof(mmSQ_PERFCOUNTER14_HI)/sizeof(mmSQ_PERFCOUNTER14_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_LO", REG_MMIO, 0xd1de, &mmSQ_PERFCOUNTER15_LO[0], sizeof(mmSQ_PERFCOUNTER15_LO)/sizeof(mmSQ_PERFCOUNTER15_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_HI", REG_MMIO, 0xd1df, &mmSQ_PERFCOUNTER15_HI[0], sizeof(mmSQ_PERFCOUNTER15_HI)/sizeof(mmSQ_PERFCOUNTER15_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_LO", REG_MMIO, 0xd240, &mmSX_PERFCOUNTER0_LO[0], sizeof(mmSX_PERFCOUNTER0_LO)/sizeof(mmSX_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_HI", REG_MMIO, 0xd241, &mmSX_PERFCOUNTER0_HI[0], sizeof(mmSX_PERFCOUNTER0_HI)/sizeof(mmSX_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_LO", REG_MMIO, 0xd242, &mmSX_PERFCOUNTER1_LO[0], sizeof(mmSX_PERFCOUNTER1_LO)/sizeof(mmSX_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_HI", REG_MMIO, 0xd243, &mmSX_PERFCOUNTER1_HI[0], sizeof(mmSX_PERFCOUNTER1_HI)/sizeof(mmSX_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_LO", REG_MMIO, 0xd244, &mmSX_PERFCOUNTER2_LO[0], sizeof(mmSX_PERFCOUNTER2_LO)/sizeof(mmSX_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_HI", REG_MMIO, 0xd245, &mmSX_PERFCOUNTER2_HI[0], sizeof(mmSX_PERFCOUNTER2_HI)/sizeof(mmSX_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_LO", REG_MMIO, 0xd246, &mmSX_PERFCOUNTER3_LO[0], sizeof(mmSX_PERFCOUNTER3_LO)/sizeof(mmSX_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_HI", REG_MMIO, 0xd247, &mmSX_PERFCOUNTER3_HI[0], sizeof(mmSX_PERFCOUNTER3_HI)/sizeof(mmSX_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_LO", REG_MMIO, 0xd280, &mmGDS_PERFCOUNTER0_LO[0], sizeof(mmGDS_PERFCOUNTER0_LO)/sizeof(mmGDS_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_HI", REG_MMIO, 0xd281, &mmGDS_PERFCOUNTER0_HI[0], sizeof(mmGDS_PERFCOUNTER0_HI)/sizeof(mmGDS_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_LO", REG_MMIO, 0xd282, &mmGDS_PERFCOUNTER1_LO[0], sizeof(mmGDS_PERFCOUNTER1_LO)/sizeof(mmGDS_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_HI", REG_MMIO, 0xd283, &mmGDS_PERFCOUNTER1_HI[0], sizeof(mmGDS_PERFCOUNTER1_HI)/sizeof(mmGDS_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_LO", REG_MMIO, 0xd284, &mmGDS_PERFCOUNTER2_LO[0], sizeof(mmGDS_PERFCOUNTER2_LO)/sizeof(mmGDS_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_HI", REG_MMIO, 0xd285, &mmGDS_PERFCOUNTER2_HI[0], sizeof(mmGDS_PERFCOUNTER2_HI)/sizeof(mmGDS_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_LO", REG_MMIO, 0xd286, &mmGDS_PERFCOUNTER3_LO[0], sizeof(mmGDS_PERFCOUNTER3_LO)/sizeof(mmGDS_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_HI", REG_MMIO, 0xd287, &mmGDS_PERFCOUNTER3_HI[0], sizeof(mmGDS_PERFCOUNTER3_HI)/sizeof(mmGDS_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_LO", REG_MMIO, 0xd2c0, &mmTA_PERFCOUNTER0_LO[0], sizeof(mmTA_PERFCOUNTER0_LO)/sizeof(mmTA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_HI", REG_MMIO, 0xd2c1, &mmTA_PERFCOUNTER0_HI[0], sizeof(mmTA_PERFCOUNTER0_HI)/sizeof(mmTA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_LO", REG_MMIO, 0xd2c2, &mmTA_PERFCOUNTER1_LO[0], sizeof(mmTA_PERFCOUNTER1_LO)/sizeof(mmTA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_HI", REG_MMIO, 0xd2c3, &mmTA_PERFCOUNTER1_HI[0], sizeof(mmTA_PERFCOUNTER1_HI)/sizeof(mmTA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_LO", REG_MMIO, 0xd300, &mmTD_PERFCOUNTER0_LO[0], sizeof(mmTD_PERFCOUNTER0_LO)/sizeof(mmTD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_HI", REG_MMIO, 0xd301, &mmTD_PERFCOUNTER0_HI[0], sizeof(mmTD_PERFCOUNTER0_HI)/sizeof(mmTD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_LO", REG_MMIO, 0xd302, &mmTD_PERFCOUNTER1_LO[0], sizeof(mmTD_PERFCOUNTER1_LO)/sizeof(mmTD_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_HI", REG_MMIO, 0xd303, &mmTD_PERFCOUNTER1_HI[0], sizeof(mmTD_PERFCOUNTER1_HI)/sizeof(mmTD_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_LO", REG_MMIO, 0xd340, &mmTCP_PERFCOUNTER0_LO[0], sizeof(mmTCP_PERFCOUNTER0_LO)/sizeof(mmTCP_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_HI", REG_MMIO, 0xd341, &mmTCP_PERFCOUNTER0_HI[0], sizeof(mmTCP_PERFCOUNTER0_HI)/sizeof(mmTCP_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_LO", REG_MMIO, 0xd342, &mmTCP_PERFCOUNTER1_LO[0], sizeof(mmTCP_PERFCOUNTER1_LO)/sizeof(mmTCP_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_HI", REG_MMIO, 0xd343, &mmTCP_PERFCOUNTER1_HI[0], sizeof(mmTCP_PERFCOUNTER1_HI)/sizeof(mmTCP_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_LO", REG_MMIO, 0xd344, &mmTCP_PERFCOUNTER2_LO[0], sizeof(mmTCP_PERFCOUNTER2_LO)/sizeof(mmTCP_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_HI", REG_MMIO, 0xd345, &mmTCP_PERFCOUNTER2_HI[0], sizeof(mmTCP_PERFCOUNTER2_HI)/sizeof(mmTCP_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_LO", REG_MMIO, 0xd346, &mmTCP_PERFCOUNTER3_LO[0], sizeof(mmTCP_PERFCOUNTER3_LO)/sizeof(mmTCP_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_HI", REG_MMIO, 0xd347, &mmTCP_PERFCOUNTER3_HI[0], sizeof(mmTCP_PERFCOUNTER3_HI)/sizeof(mmTCP_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_LO", REG_MMIO, 0xd380, &mmTCC_PERFCOUNTER0_LO[0], sizeof(mmTCC_PERFCOUNTER0_LO)/sizeof(mmTCC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_HI", REG_MMIO, 0xd381, &mmTCC_PERFCOUNTER0_HI[0], sizeof(mmTCC_PERFCOUNTER0_HI)/sizeof(mmTCC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_LO", REG_MMIO, 0xd382, &mmTCC_PERFCOUNTER1_LO[0], sizeof(mmTCC_PERFCOUNTER1_LO)/sizeof(mmTCC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_HI", REG_MMIO, 0xd383, &mmTCC_PERFCOUNTER1_HI[0], sizeof(mmTCC_PERFCOUNTER1_HI)/sizeof(mmTCC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_LO", REG_MMIO, 0xd384, &mmTCC_PERFCOUNTER2_LO[0], sizeof(mmTCC_PERFCOUNTER2_LO)/sizeof(mmTCC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_HI", REG_MMIO, 0xd385, &mmTCC_PERFCOUNTER2_HI[0], sizeof(mmTCC_PERFCOUNTER2_HI)/sizeof(mmTCC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_LO", REG_MMIO, 0xd386, &mmTCC_PERFCOUNTER3_LO[0], sizeof(mmTCC_PERFCOUNTER3_LO)/sizeof(mmTCC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_HI", REG_MMIO, 0xd387, &mmTCC_PERFCOUNTER3_HI[0], sizeof(mmTCC_PERFCOUNTER3_HI)/sizeof(mmTCC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_LO", REG_MMIO, 0xd390, &mmTCA_PERFCOUNTER0_LO[0], sizeof(mmTCA_PERFCOUNTER0_LO)/sizeof(mmTCA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_HI", REG_MMIO, 0xd391, &mmTCA_PERFCOUNTER0_HI[0], sizeof(mmTCA_PERFCOUNTER0_HI)/sizeof(mmTCA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_LO", REG_MMIO, 0xd392, &mmTCA_PERFCOUNTER1_LO[0], sizeof(mmTCA_PERFCOUNTER1_LO)/sizeof(mmTCA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_HI", REG_MMIO, 0xd393, &mmTCA_PERFCOUNTER1_HI[0], sizeof(mmTCA_PERFCOUNTER1_HI)/sizeof(mmTCA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_LO", REG_MMIO, 0xd394, &mmTCA_PERFCOUNTER2_LO[0], sizeof(mmTCA_PERFCOUNTER2_LO)/sizeof(mmTCA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_HI", REG_MMIO, 0xd395, &mmTCA_PERFCOUNTER2_HI[0], sizeof(mmTCA_PERFCOUNTER2_HI)/sizeof(mmTCA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_LO", REG_MMIO, 0xd396, &mmTCA_PERFCOUNTER3_LO[0], sizeof(mmTCA_PERFCOUNTER3_LO)/sizeof(mmTCA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_HI", REG_MMIO, 0xd397, &mmTCA_PERFCOUNTER3_HI[0], sizeof(mmTCA_PERFCOUNTER3_HI)/sizeof(mmTCA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_LO", REG_MMIO, 0xd406, &mmCB_PERFCOUNTER0_LO[0], sizeof(mmCB_PERFCOUNTER0_LO)/sizeof(mmCB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_HI", REG_MMIO, 0xd407, &mmCB_PERFCOUNTER0_HI[0], sizeof(mmCB_PERFCOUNTER0_HI)/sizeof(mmCB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_LO", REG_MMIO, 0xd408, &mmCB_PERFCOUNTER1_LO[0], sizeof(mmCB_PERFCOUNTER1_LO)/sizeof(mmCB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_HI", REG_MMIO, 0xd409, &mmCB_PERFCOUNTER1_HI[0], sizeof(mmCB_PERFCOUNTER1_HI)/sizeof(mmCB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_LO", REG_MMIO, 0xd40a, &mmCB_PERFCOUNTER2_LO[0], sizeof(mmCB_PERFCOUNTER2_LO)/sizeof(mmCB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_HI", REG_MMIO, 0xd40b, &mmCB_PERFCOUNTER2_HI[0], sizeof(mmCB_PERFCOUNTER2_HI)/sizeof(mmCB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_LO", REG_MMIO, 0xd40c, &mmCB_PERFCOUNTER3_LO[0], sizeof(mmCB_PERFCOUNTER3_LO)/sizeof(mmCB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_HI", REG_MMIO, 0xd40d, &mmCB_PERFCOUNTER3_HI[0], sizeof(mmCB_PERFCOUNTER3_HI)/sizeof(mmCB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_LO", REG_MMIO, 0xd440, &mmDB_PERFCOUNTER0_LO[0], sizeof(mmDB_PERFCOUNTER0_LO)/sizeof(mmDB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_HI", REG_MMIO, 0xd441, &mmDB_PERFCOUNTER0_HI[0], sizeof(mmDB_PERFCOUNTER0_HI)/sizeof(mmDB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_LO", REG_MMIO, 0xd442, &mmDB_PERFCOUNTER1_LO[0], sizeof(mmDB_PERFCOUNTER1_LO)/sizeof(mmDB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_HI", REG_MMIO, 0xd443, &mmDB_PERFCOUNTER1_HI[0], sizeof(mmDB_PERFCOUNTER1_HI)/sizeof(mmDB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_LO", REG_MMIO, 0xd444, &mmDB_PERFCOUNTER2_LO[0], sizeof(mmDB_PERFCOUNTER2_LO)/sizeof(mmDB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_HI", REG_MMIO, 0xd445, &mmDB_PERFCOUNTER2_HI[0], sizeof(mmDB_PERFCOUNTER2_HI)/sizeof(mmDB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_LO", REG_MMIO, 0xd446, &mmDB_PERFCOUNTER3_LO[0], sizeof(mmDB_PERFCOUNTER3_LO)/sizeof(mmDB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_HI", REG_MMIO, 0xd447, &mmDB_PERFCOUNTER3_HI[0], sizeof(mmDB_PERFCOUNTER3_HI)/sizeof(mmDB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_LO", REG_MMIO, 0xd480, &mmRLC_PERFCOUNTER0_LO[0], sizeof(mmRLC_PERFCOUNTER0_LO)/sizeof(mmRLC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_HI", REG_MMIO, 0xd481, &mmRLC_PERFCOUNTER0_HI[0], sizeof(mmRLC_PERFCOUNTER0_HI)/sizeof(mmRLC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_LO", REG_MMIO, 0xd482, &mmRLC_PERFCOUNTER1_LO[0], sizeof(mmRLC_PERFCOUNTER1_LO)/sizeof(mmRLC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_HI", REG_MMIO, 0xd483, &mmRLC_PERFCOUNTER1_HI[0], sizeof(mmRLC_PERFCOUNTER1_HI)/sizeof(mmRLC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_SELECT", REG_MMIO, 0xd800, &mmCPG_PERFCOUNTER1_SELECT[0], sizeof(mmCPG_PERFCOUNTER1_SELECT)/sizeof(mmCPG_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd801, &mmCPG_PERFCOUNTER0_SELECT1[0], sizeof(mmCPG_PERFCOUNTER0_SELECT1)/sizeof(mmCPG_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_SELECT", REG_MMIO, 0xd802, &mmCPG_PERFCOUNTER0_SELECT[0], sizeof(mmCPG_PERFCOUNTER0_SELECT)/sizeof(mmCPG_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd803, &mmCPC_PERFCOUNTER1_SELECT[0], sizeof(mmCPC_PERFCOUNTER1_SELECT)/sizeof(mmCPC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd804, &mmCPC_PERFCOUNTER0_SELECT1[0], sizeof(mmCPC_PERFCOUNTER0_SELECT1)/sizeof(mmCPC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_SELECT", REG_MMIO, 0xd805, &mmCPF_PERFCOUNTER1_SELECT[0], sizeof(mmCPF_PERFCOUNTER1_SELECT)/sizeof(mmCPF_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd806, &mmCPF_PERFCOUNTER0_SELECT1[0], sizeof(mmCPF_PERFCOUNTER0_SELECT1)/sizeof(mmCPF_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_SELECT", REG_MMIO, 0xd807, &mmCPF_PERFCOUNTER0_SELECT[0], sizeof(mmCPF_PERFCOUNTER0_SELECT)/sizeof(mmCPF_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTL", REG_MMIO, 0xd808, &mmCP_PERFMON_CNTL[0], sizeof(mmCP_PERFMON_CNTL)/sizeof(mmCP_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd809, &mmCPC_PERFCOUNTER0_SELECT[0], sizeof(mmCPC_PERFCOUNTER0_SELECT)/sizeof(mmCPC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCP_DRAW_OBJECT", REG_MMIO, 0xd810, &mmCP_DRAW_OBJECT[0], sizeof(mmCP_DRAW_OBJECT)/sizeof(mmCP_DRAW_OBJECT[0]), 0, 0 },
+	{ "mmCP_DRAW_OBJECT_COUNTER", REG_MMIO, 0xd811, &mmCP_DRAW_OBJECT_COUNTER[0], sizeof(mmCP_DRAW_OBJECT_COUNTER)/sizeof(mmCP_DRAW_OBJECT_COUNTER[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_MASK_HI", REG_MMIO, 0xd812, &mmCP_DRAW_WINDOW_MASK_HI[0], sizeof(mmCP_DRAW_WINDOW_MASK_HI)/sizeof(mmCP_DRAW_WINDOW_MASK_HI[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_HI", REG_MMIO, 0xd813, &mmCP_DRAW_WINDOW_HI[0], sizeof(mmCP_DRAW_WINDOW_HI)/sizeof(mmCP_DRAW_WINDOW_HI[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_LO", REG_MMIO, 0xd814, &mmCP_DRAW_WINDOW_LO[0], sizeof(mmCP_DRAW_WINDOW_LO)/sizeof(mmCP_DRAW_WINDOW_LO[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_CNTL", REG_MMIO, 0xd815, &mmCP_DRAW_WINDOW_CNTL[0], sizeof(mmCP_DRAW_WINDOW_CNTL)/sizeof(mmCP_DRAW_WINDOW_CNTL[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0xd840, &mmGRBM_PERFCOUNTER0_SELECT[0], sizeof(mmGRBM_PERFCOUNTER0_SELECT)/sizeof(mmGRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0xd841, &mmGRBM_PERFCOUNTER1_SELECT[0], sizeof(mmGRBM_PERFCOUNTER1_SELECT)/sizeof(mmGRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_SELECT", REG_MMIO, 0xd842, &mmGRBM_SE0_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_SELECT", REG_MMIO, 0xd843, &mmGRBM_SE1_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_SELECT", REG_MMIO, 0xd844, &mmGRBM_SE2_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_SELECT", REG_MMIO, 0xd845, &mmGRBM_SE3_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_SELECT", REG_MMIO, 0xd880, &mmWD_PERFCOUNTER0_SELECT[0], sizeof(mmWD_PERFCOUNTER0_SELECT)/sizeof(mmWD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_SELECT", REG_MMIO, 0xd881, &mmWD_PERFCOUNTER1_SELECT[0], sizeof(mmWD_PERFCOUNTER1_SELECT)/sizeof(mmWD_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_SELECT", REG_MMIO, 0xd882, &mmWD_PERFCOUNTER2_SELECT[0], sizeof(mmWD_PERFCOUNTER2_SELECT)/sizeof(mmWD_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_SELECT", REG_MMIO, 0xd883, &mmWD_PERFCOUNTER3_SELECT[0], sizeof(mmWD_PERFCOUNTER3_SELECT)/sizeof(mmWD_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT", REG_MMIO, 0xd884, &mmIA_PERFCOUNTER0_SELECT[0], sizeof(mmIA_PERFCOUNTER0_SELECT)/sizeof(mmIA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_SELECT", REG_MMIO, 0xd885, &mmIA_PERFCOUNTER1_SELECT[0], sizeof(mmIA_PERFCOUNTER1_SELECT)/sizeof(mmIA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_SELECT", REG_MMIO, 0xd886, &mmIA_PERFCOUNTER2_SELECT[0], sizeof(mmIA_PERFCOUNTER2_SELECT)/sizeof(mmIA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_SELECT", REG_MMIO, 0xd887, &mmIA_PERFCOUNTER3_SELECT[0], sizeof(mmIA_PERFCOUNTER3_SELECT)/sizeof(mmIA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd888, &mmIA_PERFCOUNTER0_SELECT1[0], sizeof(mmIA_PERFCOUNTER0_SELECT1)/sizeof(mmIA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT", REG_MMIO, 0xd88c, &mmVGT_PERFCOUNTER0_SELECT[0], sizeof(mmVGT_PERFCOUNTER0_SELECT)/sizeof(mmVGT_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT", REG_MMIO, 0xd88d, &mmVGT_PERFCOUNTER1_SELECT[0], sizeof(mmVGT_PERFCOUNTER1_SELECT)/sizeof(mmVGT_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_SELECT", REG_MMIO, 0xd88e, &mmVGT_PERFCOUNTER2_SELECT[0], sizeof(mmVGT_PERFCOUNTER2_SELECT)/sizeof(mmVGT_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_SELECT", REG_MMIO, 0xd88f, &mmVGT_PERFCOUNTER3_SELECT[0], sizeof(mmVGT_PERFCOUNTER3_SELECT)/sizeof(mmVGT_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd890, &mmVGT_PERFCOUNTER0_SELECT1[0], sizeof(mmVGT_PERFCOUNTER0_SELECT1)/sizeof(mmVGT_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd891, &mmVGT_PERFCOUNTER1_SELECT1[0], sizeof(mmVGT_PERFCOUNTER1_SELECT1)/sizeof(mmVGT_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER_SEID_MASK", REG_MMIO, 0xd894, &mmVGT_PERFCOUNTER_SEID_MASK[0], sizeof(mmVGT_PERFCOUNTER_SEID_MASK)/sizeof(mmVGT_PERFCOUNTER_SEID_MASK[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT", REG_MMIO, 0xd900, &mmPA_SU_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd901, &mmPA_SU_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT", REG_MMIO, 0xd902, &mmPA_SU_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd903, &mmPA_SU_PERFCOUNTER1_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_SELECT", REG_MMIO, 0xd904, &mmPA_SU_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER2_SELECT)/sizeof(mmPA_SU_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_SELECT", REG_MMIO, 0xd905, &mmPA_SU_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER3_SELECT)/sizeof(mmPA_SU_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd940, &mmPA_SC_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd941, &mmPA_SC_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd942, &mmPA_SC_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER1_SELECT)/sizeof(mmPA_SC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_SELECT", REG_MMIO, 0xd943, &mmPA_SC_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER2_SELECT)/sizeof(mmPA_SC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_SELECT", REG_MMIO, 0xd944, &mmPA_SC_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER3_SELECT)/sizeof(mmPA_SC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_SELECT", REG_MMIO, 0xd945, &mmPA_SC_PERFCOUNTER4_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER4_SELECT)/sizeof(mmPA_SC_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_SELECT", REG_MMIO, 0xd946, &mmPA_SC_PERFCOUNTER5_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER5_SELECT)/sizeof(mmPA_SC_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_SELECT", REG_MMIO, 0xd947, &mmPA_SC_PERFCOUNTER6_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER6_SELECT)/sizeof(mmPA_SC_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_SELECT", REG_MMIO, 0xd948, &mmPA_SC_PERFCOUNTER7_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER7_SELECT)/sizeof(mmPA_SC_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT", REG_MMIO, 0xd980, &mmSPI_PERFCOUNTER0_SELECT[0], sizeof(mmSPI_PERFCOUNTER0_SELECT)/sizeof(mmSPI_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT", REG_MMIO, 0xd981, &mmSPI_PERFCOUNTER1_SELECT[0], sizeof(mmSPI_PERFCOUNTER1_SELECT)/sizeof(mmSPI_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT", REG_MMIO, 0xd982, &mmSPI_PERFCOUNTER2_SELECT[0], sizeof(mmSPI_PERFCOUNTER2_SELECT)/sizeof(mmSPI_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT", REG_MMIO, 0xd983, &mmSPI_PERFCOUNTER3_SELECT[0], sizeof(mmSPI_PERFCOUNTER3_SELECT)/sizeof(mmSPI_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd984, &mmSPI_PERFCOUNTER0_SELECT1[0], sizeof(mmSPI_PERFCOUNTER0_SELECT1)/sizeof(mmSPI_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd985, &mmSPI_PERFCOUNTER1_SELECT1[0], sizeof(mmSPI_PERFCOUNTER1_SELECT1)/sizeof(mmSPI_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT1", REG_MMIO, 0xd986, &mmSPI_PERFCOUNTER2_SELECT1[0], sizeof(mmSPI_PERFCOUNTER2_SELECT1)/sizeof(mmSPI_PERFCOUNTER2_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT1", REG_MMIO, 0xd987, &mmSPI_PERFCOUNTER3_SELECT1[0], sizeof(mmSPI_PERFCOUNTER3_SELECT1)/sizeof(mmSPI_PERFCOUNTER3_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_SELECT", REG_MMIO, 0xd988, &mmSPI_PERFCOUNTER4_SELECT[0], sizeof(mmSPI_PERFCOUNTER4_SELECT)/sizeof(mmSPI_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_SELECT", REG_MMIO, 0xd989, &mmSPI_PERFCOUNTER5_SELECT[0], sizeof(mmSPI_PERFCOUNTER5_SELECT)/sizeof(mmSPI_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER_BINS", REG_MMIO, 0xd98a, &mmSPI_PERFCOUNTER_BINS[0], sizeof(mmSPI_PERFCOUNTER_BINS)/sizeof(mmSPI_PERFCOUNTER_BINS[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_SELECT", REG_MMIO, 0xd9c0, &mmSQ_PERFCOUNTER0_SELECT[0], sizeof(mmSQ_PERFCOUNTER0_SELECT)/sizeof(mmSQ_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_SELECT", REG_MMIO, 0xd9c1, &mmSQ_PERFCOUNTER1_SELECT[0], sizeof(mmSQ_PERFCOUNTER1_SELECT)/sizeof(mmSQ_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_SELECT", REG_MMIO, 0xd9c2, &mmSQ_PERFCOUNTER2_SELECT[0], sizeof(mmSQ_PERFCOUNTER2_SELECT)/sizeof(mmSQ_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_SELECT", REG_MMIO, 0xd9c3, &mmSQ_PERFCOUNTER3_SELECT[0], sizeof(mmSQ_PERFCOUNTER3_SELECT)/sizeof(mmSQ_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_SELECT", REG_MMIO, 0xd9c4, &mmSQ_PERFCOUNTER4_SELECT[0], sizeof(mmSQ_PERFCOUNTER4_SELECT)/sizeof(mmSQ_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_SELECT", REG_MMIO, 0xd9c5, &mmSQ_PERFCOUNTER5_SELECT[0], sizeof(mmSQ_PERFCOUNTER5_SELECT)/sizeof(mmSQ_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_SELECT", REG_MMIO, 0xd9c6, &mmSQ_PERFCOUNTER6_SELECT[0], sizeof(mmSQ_PERFCOUNTER6_SELECT)/sizeof(mmSQ_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_SELECT", REG_MMIO, 0xd9c7, &mmSQ_PERFCOUNTER7_SELECT[0], sizeof(mmSQ_PERFCOUNTER7_SELECT)/sizeof(mmSQ_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_SELECT", REG_MMIO, 0xd9c8, &mmSQ_PERFCOUNTER8_SELECT[0], sizeof(mmSQ_PERFCOUNTER8_SELECT)/sizeof(mmSQ_PERFCOUNTER8_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_SELECT", REG_MMIO, 0xd9c9, &mmSQ_PERFCOUNTER9_SELECT[0], sizeof(mmSQ_PERFCOUNTER9_SELECT)/sizeof(mmSQ_PERFCOUNTER9_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_SELECT", REG_MMIO, 0xd9ca, &mmSQ_PERFCOUNTER10_SELECT[0], sizeof(mmSQ_PERFCOUNTER10_SELECT)/sizeof(mmSQ_PERFCOUNTER10_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_SELECT", REG_MMIO, 0xd9cb, &mmSQ_PERFCOUNTER11_SELECT[0], sizeof(mmSQ_PERFCOUNTER11_SELECT)/sizeof(mmSQ_PERFCOUNTER11_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_SELECT", REG_MMIO, 0xd9cc, &mmSQ_PERFCOUNTER12_SELECT[0], sizeof(mmSQ_PERFCOUNTER12_SELECT)/sizeof(mmSQ_PERFCOUNTER12_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_SELECT", REG_MMIO, 0xd9cd, &mmSQ_PERFCOUNTER13_SELECT[0], sizeof(mmSQ_PERFCOUNTER13_SELECT)/sizeof(mmSQ_PERFCOUNTER13_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_SELECT", REG_MMIO, 0xd9ce, &mmSQ_PERFCOUNTER14_SELECT[0], sizeof(mmSQ_PERFCOUNTER14_SELECT)/sizeof(mmSQ_PERFCOUNTER14_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_SELECT", REG_MMIO, 0xd9cf, &mmSQ_PERFCOUNTER15_SELECT[0], sizeof(mmSQ_PERFCOUNTER15_SELECT)/sizeof(mmSQ_PERFCOUNTER15_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL", REG_MMIO, 0xd9e0, &mmSQ_PERFCOUNTER_CTRL[0], sizeof(mmSQ_PERFCOUNTER_CTRL)/sizeof(mmSQ_PERFCOUNTER_CTRL[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_MASK", REG_MMIO, 0xd9e1, &mmSQ_PERFCOUNTER_MASK[0], sizeof(mmSQ_PERFCOUNTER_MASK)/sizeof(mmSQ_PERFCOUNTER_MASK[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL2", REG_MMIO, 0xd9e2, &mmSQ_PERFCOUNTER_CTRL2[0], sizeof(mmSQ_PERFCOUNTER_CTRL2)/sizeof(mmSQ_PERFCOUNTER_CTRL2[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT", REG_MMIO, 0xda40, &mmSX_PERFCOUNTER0_SELECT[0], sizeof(mmSX_PERFCOUNTER0_SELECT)/sizeof(mmSX_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT", REG_MMIO, 0xda41, &mmSX_PERFCOUNTER1_SELECT[0], sizeof(mmSX_PERFCOUNTER1_SELECT)/sizeof(mmSX_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_SELECT", REG_MMIO, 0xda42, &mmSX_PERFCOUNTER2_SELECT[0], sizeof(mmSX_PERFCOUNTER2_SELECT)/sizeof(mmSX_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_SELECT", REG_MMIO, 0xda43, &mmSX_PERFCOUNTER3_SELECT[0], sizeof(mmSX_PERFCOUNTER3_SELECT)/sizeof(mmSX_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda44, &mmSX_PERFCOUNTER0_SELECT1[0], sizeof(mmSX_PERFCOUNTER0_SELECT1)/sizeof(mmSX_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT1", REG_MMIO, 0xda45, &mmSX_PERFCOUNTER1_SELECT1[0], sizeof(mmSX_PERFCOUNTER1_SELECT1)/sizeof(mmSX_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT", REG_MMIO, 0xda80, &mmGDS_PERFCOUNTER0_SELECT[0], sizeof(mmGDS_PERFCOUNTER0_SELECT)/sizeof(mmGDS_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_SELECT", REG_MMIO, 0xda81, &mmGDS_PERFCOUNTER1_SELECT[0], sizeof(mmGDS_PERFCOUNTER1_SELECT)/sizeof(mmGDS_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_SELECT", REG_MMIO, 0xda82, &mmGDS_PERFCOUNTER2_SELECT[0], sizeof(mmGDS_PERFCOUNTER2_SELECT)/sizeof(mmGDS_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_SELECT", REG_MMIO, 0xda83, &mmGDS_PERFCOUNTER3_SELECT[0], sizeof(mmGDS_PERFCOUNTER3_SELECT)/sizeof(mmGDS_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda84, &mmGDS_PERFCOUNTER0_SELECT1[0], sizeof(mmGDS_PERFCOUNTER0_SELECT1)/sizeof(mmGDS_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdac0, &mmTA_PERFCOUNTER0_SELECT[0], sizeof(mmTA_PERFCOUNTER0_SELECT)/sizeof(mmTA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdac1, &mmTA_PERFCOUNTER0_SELECT1[0], sizeof(mmTA_PERFCOUNTER0_SELECT1)/sizeof(mmTA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdac2, &mmTA_PERFCOUNTER1_SELECT[0], sizeof(mmTA_PERFCOUNTER1_SELECT)/sizeof(mmTA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb00, &mmTD_PERFCOUNTER0_SELECT[0], sizeof(mmTD_PERFCOUNTER0_SELECT)/sizeof(mmTD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb01, &mmTD_PERFCOUNTER0_SELECT1[0], sizeof(mmTD_PERFCOUNTER0_SELECT1)/sizeof(mmTD_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb02, &mmTD_PERFCOUNTER1_SELECT[0], sizeof(mmTD_PERFCOUNTER1_SELECT)/sizeof(mmTD_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb40, &mmTCP_PERFCOUNTER0_SELECT[0], sizeof(mmTCP_PERFCOUNTER0_SELECT)/sizeof(mmTCP_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb41, &mmTCP_PERFCOUNTER0_SELECT1[0], sizeof(mmTCP_PERFCOUNTER0_SELECT1)/sizeof(mmTCP_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb42, &mmTCP_PERFCOUNTER1_SELECT[0], sizeof(mmTCP_PERFCOUNTER1_SELECT)/sizeof(mmTCP_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb43, &mmTCP_PERFCOUNTER1_SELECT1[0], sizeof(mmTCP_PERFCOUNTER1_SELECT1)/sizeof(mmTCP_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb44, &mmTCP_PERFCOUNTER2_SELECT[0], sizeof(mmTCP_PERFCOUNTER2_SELECT)/sizeof(mmTCP_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb45, &mmTCP_PERFCOUNTER3_SELECT[0], sizeof(mmTCP_PERFCOUNTER3_SELECT)/sizeof(mmTCP_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb80, &mmTCC_PERFCOUNTER0_SELECT[0], sizeof(mmTCC_PERFCOUNTER0_SELECT)/sizeof(mmTCC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb81, &mmTCC_PERFCOUNTER0_SELECT1[0], sizeof(mmTCC_PERFCOUNTER0_SELECT1)/sizeof(mmTCC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb82, &mmTCC_PERFCOUNTER1_SELECT[0], sizeof(mmTCC_PERFCOUNTER1_SELECT)/sizeof(mmTCC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb83, &mmTCC_PERFCOUNTER1_SELECT1[0], sizeof(mmTCC_PERFCOUNTER1_SELECT1)/sizeof(mmTCC_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb84, &mmTCC_PERFCOUNTER2_SELECT[0], sizeof(mmTCC_PERFCOUNTER2_SELECT)/sizeof(mmTCC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb85, &mmTCC_PERFCOUNTER3_SELECT[0], sizeof(mmTCC_PERFCOUNTER3_SELECT)/sizeof(mmTCC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb90, &mmTCA_PERFCOUNTER0_SELECT[0], sizeof(mmTCA_PERFCOUNTER0_SELECT)/sizeof(mmTCA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb91, &mmTCA_PERFCOUNTER0_SELECT1[0], sizeof(mmTCA_PERFCOUNTER0_SELECT1)/sizeof(mmTCA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb92, &mmTCA_PERFCOUNTER1_SELECT[0], sizeof(mmTCA_PERFCOUNTER1_SELECT)/sizeof(mmTCA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb93, &mmTCA_PERFCOUNTER1_SELECT1[0], sizeof(mmTCA_PERFCOUNTER1_SELECT1)/sizeof(mmTCA_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb94, &mmTCA_PERFCOUNTER2_SELECT[0], sizeof(mmTCA_PERFCOUNTER2_SELECT)/sizeof(mmTCA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb95, &mmTCA_PERFCOUNTER3_SELECT[0], sizeof(mmTCA_PERFCOUNTER3_SELECT)/sizeof(mmTCA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER_FILTER", REG_MMIO, 0xdc00, &mmCB_PERFCOUNTER_FILTER[0], sizeof(mmCB_PERFCOUNTER_FILTER)/sizeof(mmCB_PERFCOUNTER_FILTER[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc01, &mmCB_PERFCOUNTER0_SELECT[0], sizeof(mmCB_PERFCOUNTER0_SELECT)/sizeof(mmCB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc02, &mmCB_PERFCOUNTER0_SELECT1[0], sizeof(mmCB_PERFCOUNTER0_SELECT1)/sizeof(mmCB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc03, &mmCB_PERFCOUNTER1_SELECT[0], sizeof(mmCB_PERFCOUNTER1_SELECT)/sizeof(mmCB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc04, &mmCB_PERFCOUNTER2_SELECT[0], sizeof(mmCB_PERFCOUNTER2_SELECT)/sizeof(mmCB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc05, &mmCB_PERFCOUNTER3_SELECT[0], sizeof(mmCB_PERFCOUNTER3_SELECT)/sizeof(mmCB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc40, &mmDB_PERFCOUNTER0_SELECT[0], sizeof(mmDB_PERFCOUNTER0_SELECT)/sizeof(mmDB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc41, &mmDB_PERFCOUNTER0_SELECT1[0], sizeof(mmDB_PERFCOUNTER0_SELECT1)/sizeof(mmDB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc42, &mmDB_PERFCOUNTER1_SELECT[0], sizeof(mmDB_PERFCOUNTER1_SELECT)/sizeof(mmDB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdc43, &mmDB_PERFCOUNTER1_SELECT1[0], sizeof(mmDB_PERFCOUNTER1_SELECT1)/sizeof(mmDB_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc44, &mmDB_PERFCOUNTER2_SELECT[0], sizeof(mmDB_PERFCOUNTER2_SELECT)/sizeof(mmDB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc46, &mmDB_PERFCOUNTER3_SELECT[0], sizeof(mmDB_PERFCOUNTER3_SELECT)/sizeof(mmDB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_CNTL", REG_MMIO, 0xdc80, &mmRLC_SPM_PERFMON_CNTL[0], sizeof(mmRLC_SPM_PERFMON_CNTL)/sizeof(mmRLC_SPM_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_BASE_LO", REG_MMIO, 0xdc81, &mmRLC_SPM_PERFMON_RING_BASE_LO[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_BASE_HI", REG_MMIO, 0xdc82, &mmRLC_SPM_PERFMON_RING_BASE_HI[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_SIZE", REG_MMIO, 0xdc83, &mmRLC_SPM_PERFMON_RING_SIZE[0], sizeof(mmRLC_SPM_PERFMON_RING_SIZE)/sizeof(mmRLC_SPM_PERFMON_RING_SIZE[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_SEGMENT_SIZE", REG_MMIO, 0xdc84, &mmRLC_SPM_PERFMON_SEGMENT_SIZE[0], sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE)/sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE[0]), 0, 0 },
+	{ "mmRLC_SPM_SE_MUXSEL_ADDR", REG_MMIO, 0xdc85, &mmRLC_SPM_SE_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_SE_MUXSEL_ADDR)/sizeof(mmRLC_SPM_SE_MUXSEL_ADDR[0]), 0, 0 },
+	{ "mmRLC_SPM_SE_MUXSEL_DATA", REG_MMIO, 0xdc86, &mmRLC_SPM_SE_MUXSEL_DATA[0], sizeof(mmRLC_SPM_SE_MUXSEL_DATA)/sizeof(mmRLC_SPM_SE_MUXSEL_DATA[0]), 0, 0 },
+	{ "mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc87, &mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc88, &mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc89, &mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8a, &mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8b, &mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8c, &mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8d, &mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8e, &mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc90, &mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc91, &mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc92, &mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc93, &mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc94, &mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc95, &mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc96, &mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc97, &mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc98, &mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc9a, &mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_GLOBAL_MUXSEL_ADDR", REG_MMIO, 0xdc9b, &mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0]), 0, 0 },
+	{ "mmRLC_SPM_GLOBAL_MUXSEL_DATA", REG_MMIO, 0xdc9c, &mmRLC_SPM_GLOBAL_MUXSEL_DATA[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA[0]), 0, 0 },
+	{ "mmRLC_SPM_RING_RDPTR", REG_MMIO, 0xdc9d, &mmRLC_SPM_RING_RDPTR[0], sizeof(mmRLC_SPM_RING_RDPTR)/sizeof(mmRLC_SPM_RING_RDPTR[0]), 0, 0 },
+	{ "mmRLC_SPM_SEGMENT_THRESHOLD", REG_MMIO, 0xdc9e, &mmRLC_SPM_SEGMENT_THRESHOLD[0], sizeof(mmRLC_SPM_SEGMENT_THRESHOLD)/sizeof(mmRLC_SPM_SEGMENT_THRESHOLD[0]), 0, 0 },
+	{ "mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc9f, &mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca0, &mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca1, &mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdca2, &mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_PERFMON_CLK_CNTL", REG_MMIO, 0xdcbf, &mmRLC_PERFMON_CLK_CNTL[0], sizeof(mmRLC_PERFMON_CLK_CNTL)/sizeof(mmRLC_PERFMON_CLK_CNTL[0]), 0, 0 },
+	{ "mmRLC_PERFMON_CNTL", REG_MMIO, 0xdcc0, &mmRLC_PERFMON_CNTL[0], sizeof(mmRLC_PERFMON_CNTL)/sizeof(mmRLC_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdcc1, &mmRLC_PERFCOUNTER0_SELECT[0], sizeof(mmRLC_PERFCOUNTER0_SELECT)/sizeof(mmRLC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdcc2, &mmRLC_PERFCOUNTER1_SELECT[0], sizeof(mmRLC_PERFCOUNTER1_SELECT)/sizeof(mmRLC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG14", REG_SMC, 0xe, &ixCLIPPER_DEBUG_REG14[0], sizeof(ixCLIPPER_DEBUG_REG14)/sizeof(ixCLIPPER_DEBUG_REG14[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG14", REG_SMC, 0xe, &ixVGT_DEBUG_REG14[0], sizeof(ixVGT_DEBUG_REG14)/sizeof(ixVGT_DEBUG_REG14[0]), 0, 0 },
+	{ "mmRLC_CNTL", REG_MMIO, 0xec00, &mmRLC_CNTL[0], sizeof(mmRLC_CNTL)/sizeof(mmRLC_CNTL[0]), 0, 0 },
+	{ "mmRLC_DEBUG_SELECT", REG_MMIO, 0xec01, &mmRLC_DEBUG_SELECT[0], sizeof(mmRLC_DEBUG_SELECT)/sizeof(mmRLC_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_DEBUG", REG_MMIO, 0xec02, &mmRLC_DEBUG[0], sizeof(mmRLC_DEBUG)/sizeof(mmRLC_DEBUG[0]), 0, 0 },
+	{ "mmRLC_MC_CNTL", REG_MMIO, 0xec03, &mmRLC_MC_CNTL[0], sizeof(mmRLC_MC_CNTL)/sizeof(mmRLC_MC_CNTL[0]), 0, 0 },
+	{ "mmRLC_STAT", REG_MMIO, 0xec04, &mmRLC_STAT[0], sizeof(mmRLC_STAT)/sizeof(mmRLC_STAT[0]), 0, 0 },
+	{ "mmRLC_SOFT_RESET_GPU", REG_MMIO, 0xec05, &mmRLC_SOFT_RESET_GPU[0], sizeof(mmRLC_SOFT_RESET_GPU)/sizeof(mmRLC_SOFT_RESET_GPU[0]), 0, 0 },
+	{ "mmRLC_SAFE_MODE", REG_MMIO, 0xec05, &mmRLC_SAFE_MODE[0], sizeof(mmRLC_SAFE_MODE)/sizeof(mmRLC_SAFE_MODE[0]), 0, 0 },
+	{ "mmRLC_MEM_SLP_CNTL", REG_MMIO, 0xec06, &mmRLC_MEM_SLP_CNTL[0], sizeof(mmRLC_MEM_SLP_CNTL)/sizeof(mmRLC_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmSMU_RLC_RESPONSE", REG_MMIO, 0xec07, &mmSMU_RLC_RESPONSE[0], sizeof(mmSMU_RLC_RESPONSE)/sizeof(mmSMU_RLC_RESPONSE[0]), 0, 0 },
+	{ "mmRLC_RLCV_SAFE_MODE", REG_MMIO, 0xec08, &mmRLC_RLCV_SAFE_MODE[0], sizeof(mmRLC_RLCV_SAFE_MODE)/sizeof(mmRLC_RLCV_SAFE_MODE[0]), 0, 0 },
+	{ "mmRLC_SMU_SAFE_MODE", REG_MMIO, 0xec09, &mmRLC_SMU_SAFE_MODE[0], sizeof(mmRLC_SMU_SAFE_MODE)/sizeof(mmRLC_SMU_SAFE_MODE[0]), 0, 0 },
+	{ "mmRLC_RLCV_COMMAND", REG_MMIO, 0xec0a, &mmRLC_RLCV_COMMAND[0], sizeof(mmRLC_RLCV_COMMAND)/sizeof(mmRLC_RLCV_COMMAND[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_MAX", REG_MMIO, 0xec12, &mmRLC_LB_CNTR_MAX[0], sizeof(mmRLC_LB_CNTR_MAX)/sizeof(mmRLC_LB_CNTR_MAX[0]), 0, 0 },
+	{ "mmRLC_LB_CNTL", REG_MMIO, 0xec19, &mmRLC_LB_CNTL[0], sizeof(mmRLC_LB_CNTL)/sizeof(mmRLC_LB_CNTL[0]), 0, 0 },
+	{ "mmRLC_MGCG_CTRL", REG_MMIO, 0xec1a, &mmRLC_MGCG_CTRL[0], sizeof(mmRLC_MGCG_CTRL)/sizeof(mmRLC_MGCG_CTRL[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_INIT", REG_MMIO, 0xec1b, &mmRLC_LB_CNTR_INIT[0], sizeof(mmRLC_LB_CNTR_INIT)/sizeof(mmRLC_LB_CNTR_INIT[0]), 0, 0 },
+	{ "mmRLC_LOAD_BALANCE_CNTR", REG_MMIO, 0xec1c, &mmRLC_LOAD_BALANCE_CNTR[0], sizeof(mmRLC_LOAD_BALANCE_CNTR)/sizeof(mmRLC_LOAD_BALANCE_CNTR[0]), 0, 0 },
+	{ "mmRLC_SAVE_AND_RESTORE_BASE", REG_MMIO, 0xec1d, &mmRLC_SAVE_AND_RESTORE_BASE[0], sizeof(mmRLC_SAVE_AND_RESTORE_BASE)/sizeof(mmRLC_SAVE_AND_RESTORE_BASE[0]), 0, 0 },
+	{ "mmRLC_DRIVER_CPDMA_STATUS", REG_MMIO, 0xec1e, &mmRLC_DRIVER_CPDMA_STATUS[0], sizeof(mmRLC_DRIVER_CPDMA_STATUS)/sizeof(mmRLC_DRIVER_CPDMA_STATUS[0]), 0, 0 },
+	{ "mmRLC_JUMP_TABLE_RESTORE", REG_MMIO, 0xec1e, &mmRLC_JUMP_TABLE_RESTORE[0], sizeof(mmRLC_JUMP_TABLE_RESTORE)/sizeof(mmRLC_JUMP_TABLE_RESTORE[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY_2", REG_MMIO, 0xec1f, &mmRLC_PG_DELAY_2[0], sizeof(mmRLC_PG_DELAY_2)/sizeof(mmRLC_PG_DELAY_2[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG_SELECT", REG_MMIO, 0xec20, &mmRLC_GPM_DEBUG_SELECT[0], sizeof(mmRLC_GPM_DEBUG_SELECT)/sizeof(mmRLC_GPM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG", REG_MMIO, 0xec21, &mmRLC_GPM_DEBUG[0], sizeof(mmRLC_GPM_DEBUG)/sizeof(mmRLC_GPM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_LSB", REG_MMIO, 0xec24, &mmRLC_GPU_CLOCK_COUNT_LSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_LSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_LSB[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_MSB", REG_MMIO, 0xec25, &mmRLC_GPU_CLOCK_COUNT_MSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_MSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_MSB[0]), 0, 0 },
+	{ "mmRLC_CAPTURE_GPU_CLOCK_COUNT", REG_MMIO, 0xec26, &mmRLC_CAPTURE_GPU_CLOCK_COUNT[0], sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT)/sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT[0]), 0, 0 },
+	{ "mmRLC_UCODE_CNTL", REG_MMIO, 0xec27, &mmRLC_UCODE_CNTL[0], sizeof(mmRLC_UCODE_CNTL)/sizeof(mmRLC_UCODE_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_RESET", REG_MMIO, 0xec28, &mmRLC_GPM_THREAD_RESET[0], sizeof(mmRLC_GPM_THREAD_RESET)/sizeof(mmRLC_GPM_THREAD_RESET[0]), 0, 0 },
+	{ "mmRLC_GPM_STAT", REG_MMIO, 0xec40, &mmRLC_GPM_STAT[0], sizeof(mmRLC_GPM_STAT)/sizeof(mmRLC_GPM_STAT[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32_RES_SEL", REG_MMIO, 0xec41, &mmRLC_GPU_CLOCK_32_RES_SEL[0], sizeof(mmRLC_GPU_CLOCK_32_RES_SEL)/sizeof(mmRLC_GPU_CLOCK_32_RES_SEL[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32", REG_MMIO, 0xec42, &mmRLC_GPU_CLOCK_32[0], sizeof(mmRLC_GPU_CLOCK_32)/sizeof(mmRLC_GPU_CLOCK_32[0]), 0, 0 },
+	{ "mmRLC_PG_CNTL", REG_MMIO, 0xec43, &mmRLC_PG_CNTL[0], sizeof(mmRLC_PG_CNTL)/sizeof(mmRLC_PG_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_PRIORITY", REG_MMIO, 0xec44, &mmRLC_GPM_THREAD_PRIORITY[0], sizeof(mmRLC_GPM_THREAD_PRIORITY)/sizeof(mmRLC_GPM_THREAD_PRIORITY[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_ENABLE", REG_MMIO, 0xec45, &mmRLC_GPM_THREAD_ENABLE[0], sizeof(mmRLC_GPM_THREAD_ENABLE)/sizeof(mmRLC_GPM_THREAD_ENABLE[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD0", REG_MMIO, 0xec46, &mmRLC_GPM_VMID_THREAD0[0], sizeof(mmRLC_GPM_VMID_THREAD0)/sizeof(mmRLC_GPM_VMID_THREAD0[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD1", REG_MMIO, 0xec47, &mmRLC_GPM_VMID_THREAD1[0], sizeof(mmRLC_GPM_VMID_THREAD1)/sizeof(mmRLC_GPM_VMID_THREAD1[0]), 0, 0 },
+	{ "mmRLC_CGTT_MGCG_OVERRIDE", REG_MMIO, 0xec48, &mmRLC_CGTT_MGCG_OVERRIDE[0], sizeof(mmRLC_CGTT_MGCG_OVERRIDE)/sizeof(mmRLC_CGTT_MGCG_OVERRIDE[0]), 0, 0 },
+	{ "mmRLC_CGCG_CGLS_CTRL", REG_MMIO, 0xec49, &mmRLC_CGCG_CGLS_CTRL[0], sizeof(mmRLC_CGCG_CGLS_CTRL)/sizeof(mmRLC_CGCG_CGLS_CTRL[0]), 0, 0 },
+	{ "mmRLC_CGCG_RAMP_CTRL", REG_MMIO, 0xec4a, &mmRLC_CGCG_RAMP_CTRL[0], sizeof(mmRLC_CGCG_RAMP_CTRL)/sizeof(mmRLC_CGCG_RAMP_CTRL[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_STATUS", REG_MMIO, 0xec4b, &mmRLC_DYN_PG_STATUS[0], sizeof(mmRLC_DYN_PG_STATUS)/sizeof(mmRLC_DYN_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_REQUEST", REG_MMIO, 0xec4c, &mmRLC_DYN_PG_REQUEST[0], sizeof(mmRLC_DYN_PG_REQUEST)/sizeof(mmRLC_DYN_PG_REQUEST[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY", REG_MMIO, 0xec4d, &mmRLC_PG_DELAY[0], sizeof(mmRLC_PG_DELAY)/sizeof(mmRLC_PG_DELAY[0]), 0, 0 },
+	{ "mmRLC_CU_STATUS", REG_MMIO, 0xec4e, &mmRLC_CU_STATUS[0], sizeof(mmRLC_CU_STATUS)/sizeof(mmRLC_CU_STATUS[0]), 0, 0 },
+	{ "mmRLC_LB_INIT_CU_MASK", REG_MMIO, 0xec4f, &mmRLC_LB_INIT_CU_MASK[0], sizeof(mmRLC_LB_INIT_CU_MASK)/sizeof(mmRLC_LB_INIT_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_ALWAYS_ACTIVE_CU_MASK", REG_MMIO, 0xec50, &mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0], sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK)/sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_PARAMS", REG_MMIO, 0xec51, &mmRLC_LB_PARAMS[0], sizeof(mmRLC_LB_PARAMS)/sizeof(mmRLC_LB_PARAMS[0]), 0, 0 },
+	{ "mmRLC_THREAD1_DELAY", REG_MMIO, 0xec52, &mmRLC_THREAD1_DELAY[0], sizeof(mmRLC_THREAD1_DELAY)/sizeof(mmRLC_THREAD1_DELAY[0]), 0, 0 },
+	{ "mmRLC_PG_ALWAYS_ON_CU_MASK", REG_MMIO, 0xec53, &mmRLC_PG_ALWAYS_ON_CU_MASK[0], sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK)/sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_MAX_PG_CU", REG_MMIO, 0xec54, &mmRLC_MAX_PG_CU[0], sizeof(mmRLC_MAX_PG_CU)/sizeof(mmRLC_MAX_PG_CU[0]), 0, 0 },
+	{ "mmRLC_AUTO_PG_CTRL", REG_MMIO, 0xec55, &mmRLC_AUTO_PG_CTRL[0], sizeof(mmRLC_AUTO_PG_CTRL)/sizeof(mmRLC_AUTO_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_GRBM_REG_SAVE_CTRL", REG_MMIO, 0xec56, &mmRLC_SMU_GRBM_REG_SAVE_CTRL[0], sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL)/sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_PG_CTRL", REG_MMIO, 0xec57, &mmRLC_SMU_PG_CTRL[0], sizeof(mmRLC_SMU_PG_CTRL)/sizeof(mmRLC_SMU_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_PG_WAKE_UP_CTRL", REG_MMIO, 0xec58, &mmRLC_SMU_PG_WAKE_UP_CTRL[0], sizeof(mmRLC_SMU_PG_WAKE_UP_CTRL)/sizeof(mmRLC_SMU_PG_WAKE_UP_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_MASTER_INDEX", REG_MMIO, 0xec59, &mmRLC_SERDES_RD_MASTER_INDEX[0], sizeof(mmRLC_SERDES_RD_MASTER_INDEX)/sizeof(mmRLC_SERDES_RD_MASTER_INDEX[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_0", REG_MMIO, 0xec5a, &mmRLC_SERDES_RD_DATA_0[0], sizeof(mmRLC_SERDES_RD_DATA_0)/sizeof(mmRLC_SERDES_RD_DATA_0[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_1", REG_MMIO, 0xec5b, &mmRLC_SERDES_RD_DATA_1[0], sizeof(mmRLC_SERDES_RD_DATA_1)/sizeof(mmRLC_SERDES_RD_DATA_1[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_2", REG_MMIO, 0xec5c, &mmRLC_SERDES_RD_DATA_2[0], sizeof(mmRLC_SERDES_RD_DATA_2)/sizeof(mmRLC_SERDES_RD_DATA_2[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_CU_MASTER_MASK", REG_MMIO, 0xec5d, &mmRLC_SERDES_WR_CU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_NONCU_MASTER_MASK", REG_MMIO, 0xec5e, &mmRLC_SERDES_WR_NONCU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_CTRL", REG_MMIO, 0xec5f, &mmRLC_SERDES_WR_CTRL[0], sizeof(mmRLC_SERDES_WR_CTRL)/sizeof(mmRLC_SERDES_WR_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_DATA", REG_MMIO, 0xec60, &mmRLC_SERDES_WR_DATA[0], sizeof(mmRLC_SERDES_WR_DATA)/sizeof(mmRLC_SERDES_WR_DATA[0]), 0, 0 },
+	{ "mmRLC_SERDES_CU_MASTER_BUSY", REG_MMIO, 0xec61, &mmRLC_SERDES_CU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_CU_MASTER_BUSY)/sizeof(mmRLC_SERDES_CU_MASTER_BUSY[0]), 0, 0 },
+	{ "mmRLC_SERDES_NONCU_MASTER_BUSY", REG_MMIO, 0xec62, &mmRLC_SERDES_NONCU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY)/sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_0", REG_MMIO, 0xec63, &mmRLC_GPM_GENERAL_0[0], sizeof(mmRLC_GPM_GENERAL_0)/sizeof(mmRLC_GPM_GENERAL_0[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_1", REG_MMIO, 0xec64, &mmRLC_GPM_GENERAL_1[0], sizeof(mmRLC_GPM_GENERAL_1)/sizeof(mmRLC_GPM_GENERAL_1[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_2", REG_MMIO, 0xec65, &mmRLC_GPM_GENERAL_2[0], sizeof(mmRLC_GPM_GENERAL_2)/sizeof(mmRLC_GPM_GENERAL_2[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_3", REG_MMIO, 0xec66, &mmRLC_GPM_GENERAL_3[0], sizeof(mmRLC_GPM_GENERAL_3)/sizeof(mmRLC_GPM_GENERAL_3[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_4", REG_MMIO, 0xec67, &mmRLC_GPM_GENERAL_4[0], sizeof(mmRLC_GPM_GENERAL_4)/sizeof(mmRLC_GPM_GENERAL_4[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_5", REG_MMIO, 0xec68, &mmRLC_GPM_GENERAL_5[0], sizeof(mmRLC_GPM_GENERAL_5)/sizeof(mmRLC_GPM_GENERAL_5[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_6", REG_MMIO, 0xec69, &mmRLC_GPM_GENERAL_6[0], sizeof(mmRLC_GPM_GENERAL_6)/sizeof(mmRLC_GPM_GENERAL_6[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_7", REG_MMIO, 0xec6a, &mmRLC_GPM_GENERAL_7[0], sizeof(mmRLC_GPM_GENERAL_7)/sizeof(mmRLC_GPM_GENERAL_7[0]), 0, 0 },
+	{ "mmRLC_GPM_CU_PD_TIMEOUT", REG_MMIO, 0xec6b, &mmRLC_GPM_CU_PD_TIMEOUT[0], sizeof(mmRLC_GPM_CU_PD_TIMEOUT)/sizeof(mmRLC_GPM_CU_PD_TIMEOUT[0]), 0, 0 },
+	{ "mmRLC_GPM_SCRATCH_ADDR", REG_MMIO, 0xec6c, &mmRLC_GPM_SCRATCH_ADDR[0], sizeof(mmRLC_GPM_SCRATCH_ADDR)/sizeof(mmRLC_GPM_SCRATCH_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_SCRATCH_DATA", REG_MMIO, 0xec6d, &mmRLC_GPM_SCRATCH_DATA[0], sizeof(mmRLC_GPM_SCRATCH_DATA)/sizeof(mmRLC_GPM_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmRLC_STATIC_PG_STATUS", REG_MMIO, 0xec6e, &mmRLC_STATIC_PG_STATUS[0], sizeof(mmRLC_STATIC_PG_STATUS)/sizeof(mmRLC_STATIC_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_GPM_PERF_COUNT_0", REG_MMIO, 0xec6f, &mmRLC_GPM_PERF_COUNT_0[0], sizeof(mmRLC_GPM_PERF_COUNT_0)/sizeof(mmRLC_GPM_PERF_COUNT_0[0]), 0, 0 },
+	{ "mmRLC_GPM_PERF_COUNT_1", REG_MMIO, 0xec70, &mmRLC_GPM_PERF_COUNT_1[0], sizeof(mmRLC_GPM_PERF_COUNT_1)/sizeof(mmRLC_GPM_PERF_COUNT_1[0]), 0, 0 },
+	{ "mmRLC_SPM_VMID", REG_MMIO, 0xec71, &mmRLC_SPM_VMID[0], sizeof(mmRLC_SPM_VMID)/sizeof(mmRLC_SPM_VMID[0]), 0, 0 },
+	{ "mmRLC_SPM_INT_CNTL", REG_MMIO, 0xec72, &mmRLC_SPM_INT_CNTL[0], sizeof(mmRLC_SPM_INT_CNTL)/sizeof(mmRLC_SPM_INT_CNTL[0]), 0, 0 },
+	{ "mmRLC_SPM_INT_STATUS", REG_MMIO, 0xec73, &mmRLC_SPM_INT_STATUS[0], sizeof(mmRLC_SPM_INT_STATUS)/sizeof(mmRLC_SPM_INT_STATUS[0]), 0, 0 },
+	{ "mmRLC_SPM_DEBUG_SELECT", REG_MMIO, 0xec74, &mmRLC_SPM_DEBUG_SELECT[0], sizeof(mmRLC_SPM_DEBUG_SELECT)/sizeof(mmRLC_SPM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_SPM_DEBUG", REG_MMIO, 0xec75, &mmRLC_SPM_DEBUG[0], sizeof(mmRLC_SPM_DEBUG)/sizeof(mmRLC_SPM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_ADDR", REG_MMIO, 0xec76, &mmRLC_GPM_LOG_ADDR[0], sizeof(mmRLC_GPM_LOG_ADDR)/sizeof(mmRLC_GPM_LOG_ADDR[0]), 0, 0 },
+	{ "mmRLC_SMU_MESSAGE", REG_MMIO, 0xec76, &mmRLC_SMU_MESSAGE[0], sizeof(mmRLC_SMU_MESSAGE)/sizeof(mmRLC_SMU_MESSAGE[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_SIZE", REG_MMIO, 0xec77, &mmRLC_GPM_LOG_SIZE[0], sizeof(mmRLC_GPM_LOG_SIZE)/sizeof(mmRLC_GPM_LOG_SIZE[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY_3", REG_MMIO, 0xec78, &mmRLC_PG_DELAY_3[0], sizeof(mmRLC_PG_DELAY_3)/sizeof(mmRLC_PG_DELAY_3[0]), 0, 0 },
+	{ "mmRLC_GPR_REG1", REG_MMIO, 0xec79, &mmRLC_GPR_REG1[0], sizeof(mmRLC_GPR_REG1)/sizeof(mmRLC_GPR_REG1[0]), 0, 0 },
+	{ "mmRLC_GPR_REG2", REG_MMIO, 0xec7a, &mmRLC_GPR_REG2[0], sizeof(mmRLC_GPR_REG2)/sizeof(mmRLC_GPR_REG2[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_CONT", REG_MMIO, 0xec7b, &mmRLC_GPM_LOG_CONT[0], sizeof(mmRLC_GPM_LOG_CONT)/sizeof(mmRLC_GPM_LOG_CONT[0]), 0, 0 },
+	{ "mmRLC_GPM_INT_DISABLE_TH0", REG_MMIO, 0xec7c, &mmRLC_GPM_INT_DISABLE_TH0[0], sizeof(mmRLC_GPM_INT_DISABLE_TH0)/sizeof(mmRLC_GPM_INT_DISABLE_TH0[0]), 0, 0 },
+	{ "mmRLC_GPM_INT_DISABLE_TH1", REG_MMIO, 0xec7d, &mmRLC_GPM_INT_DISABLE_TH1[0], sizeof(mmRLC_GPM_INT_DISABLE_TH1)/sizeof(mmRLC_GPM_INT_DISABLE_TH1[0]), 0, 0 },
+	{ "mmRLC_GPM_INT_FORCE_TH0", REG_MMIO, 0xec7e, &mmRLC_GPM_INT_FORCE_TH0[0], sizeof(mmRLC_GPM_INT_FORCE_TH0)/sizeof(mmRLC_GPM_INT_FORCE_TH0[0]), 0, 0 },
+	{ "mmRLC_GPM_INT_FORCE_TH1", REG_MMIO, 0xec7f, &mmRLC_GPM_INT_FORCE_TH1[0], sizeof(mmRLC_GPM_INT_FORCE_TH1)/sizeof(mmRLC_GPM_INT_FORCE_TH1[0]), 0, 0 },
+	{ "mmRLC_SRM_CNTL", REG_MMIO, 0xec80, &mmRLC_SRM_CNTL[0], sizeof(mmRLC_SRM_CNTL)/sizeof(mmRLC_SRM_CNTL[0]), 0, 0 },
+	{ "mmRLC_SRM_DEBUG_SELECT", REG_MMIO, 0xec81, &mmRLC_SRM_DEBUG_SELECT[0], sizeof(mmRLC_SRM_DEBUG_SELECT)/sizeof(mmRLC_SRM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_SRM_DEBUG", REG_MMIO, 0xec82, &mmRLC_SRM_DEBUG[0], sizeof(mmRLC_SRM_DEBUG)/sizeof(mmRLC_SRM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_SRM_ARAM_ADDR", REG_MMIO, 0xec83, NULL, 0, 0, 0 },
+	{ "mmRLC_SRM_ARAM_DATA", REG_MMIO, 0xec84, &mmRLC_SRM_ARAM_DATA[0], sizeof(mmRLC_SRM_ARAM_DATA)/sizeof(mmRLC_SRM_ARAM_DATA[0]), 0, 0 },
+	{ "mmRLC_SRM_DRAM_ADDR", REG_MMIO, 0xec85, &mmRLC_SRM_DRAM_ADDR[0], sizeof(mmRLC_SRM_DRAM_ADDR)/sizeof(mmRLC_SRM_DRAM_ADDR[0]), 0, 0 },
+	{ "mmRLC_SRM_DRAM_DATA", REG_MMIO, 0xec86, &mmRLC_SRM_DRAM_DATA[0], sizeof(mmRLC_SRM_DRAM_DATA)/sizeof(mmRLC_SRM_DRAM_DATA[0]), 0, 0 },
+	{ "mmRLC_SRM_GPM_COMMAND", REG_MMIO, 0xec87, &mmRLC_SRM_GPM_COMMAND[0], sizeof(mmRLC_SRM_GPM_COMMAND)/sizeof(mmRLC_SRM_GPM_COMMAND[0]), 0, 0 },
+	{ "mmRLC_SRM_GPM_COMMAND_STATUS", REG_MMIO, 0xec88, &mmRLC_SRM_GPM_COMMAND_STATUS[0], sizeof(mmRLC_SRM_GPM_COMMAND_STATUS)/sizeof(mmRLC_SRM_GPM_COMMAND_STATUS[0]), 0, 0 },
+	{ "mmRLC_SRM_RLCV_COMMAND", REG_MMIO, 0xec89, &mmRLC_SRM_RLCV_COMMAND[0], sizeof(mmRLC_SRM_RLCV_COMMAND)/sizeof(mmRLC_SRM_RLCV_COMMAND[0]), 0, 0 },
+	{ "mmRLC_SRM_RLCV_COMMAND_STATUS", REG_MMIO, 0xec8a, &mmRLC_SRM_RLCV_COMMAND_STATUS[0], sizeof(mmRLC_SRM_RLCV_COMMAND_STATUS)/sizeof(mmRLC_SRM_RLCV_COMMAND_STATUS[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_0", REG_MMIO, 0xec8b, &mmRLC_SRM_INDEX_CNTL_ADDR_0[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_0)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_0[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_1", REG_MMIO, 0xec8c, &mmRLC_SRM_INDEX_CNTL_ADDR_1[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_1)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_1[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_2", REG_MMIO, 0xec8d, &mmRLC_SRM_INDEX_CNTL_ADDR_2[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_2)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_2[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_3", REG_MMIO, 0xec8e, &mmRLC_SRM_INDEX_CNTL_ADDR_3[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_3)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_3[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_4", REG_MMIO, 0xec8f, &mmRLC_SRM_INDEX_CNTL_ADDR_4[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_4)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_4[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_5", REG_MMIO, 0xec90, &mmRLC_SRM_INDEX_CNTL_ADDR_5[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_5)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_5[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_6", REG_MMIO, 0xec91, &mmRLC_SRM_INDEX_CNTL_ADDR_6[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_6)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_6[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_7", REG_MMIO, 0xec92, &mmRLC_SRM_INDEX_CNTL_ADDR_7[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_7)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_7[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_0", REG_MMIO, 0xec93, &mmRLC_SRM_INDEX_CNTL_DATA_0[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_0)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_0[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_1", REG_MMIO, 0xec94, &mmRLC_SRM_INDEX_CNTL_DATA_1[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_1)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_1[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_2", REG_MMIO, 0xec95, &mmRLC_SRM_INDEX_CNTL_DATA_2[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_2)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_2[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_3", REG_MMIO, 0xec96, &mmRLC_SRM_INDEX_CNTL_DATA_3[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_3)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_3[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_4", REG_MMIO, 0xec97, &mmRLC_SRM_INDEX_CNTL_DATA_4[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_4)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_4[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_5", REG_MMIO, 0xec98, &mmRLC_SRM_INDEX_CNTL_DATA_5[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_5)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_5[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_6", REG_MMIO, 0xec99, &mmRLC_SRM_INDEX_CNTL_DATA_6[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_6)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_6[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_7", REG_MMIO, 0xec9a, &mmRLC_SRM_INDEX_CNTL_DATA_7[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_7)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_7[0]), 0, 0 },
+	{ "mmRLC_SRM_STAT", REG_MMIO, 0xec9b, &mmRLC_SRM_STAT[0], sizeof(mmRLC_SRM_STAT)/sizeof(mmRLC_SRM_STAT[0]), 0, 0 },
+	{ "mmRLC_SRM_GPM_ABORT", REG_MMIO, 0xec9c, &mmRLC_SRM_GPM_ABORT[0], sizeof(mmRLC_SRM_GPM_ABORT)/sizeof(mmRLC_SRM_GPM_ABORT[0]), 0, 0 },
+	{ "mmRLC_CGCG_CGLS_CTRL_3D", REG_MMIO, 0xec9d, NULL, 0, 0, 0 },
+	{ "mmRLC_CGCG_RAMP_CTRL_3D", REG_MMIO, 0xec9e, NULL, 0, 0, 0 },
+	{ "mmRLC_CSIB_ADDR_LO", REG_MMIO, 0xeca2, &mmRLC_CSIB_ADDR_LO[0], sizeof(mmRLC_CSIB_ADDR_LO)/sizeof(mmRLC_CSIB_ADDR_LO[0]), 0, 0 },
+	{ "mmRLC_CSIB_ADDR_HI", REG_MMIO, 0xeca3, &mmRLC_CSIB_ADDR_HI[0], sizeof(mmRLC_CSIB_ADDR_HI)/sizeof(mmRLC_CSIB_ADDR_HI[0]), 0, 0 },
+	{ "mmRLC_CSIB_LENGTH", REG_MMIO, 0xeca4, &mmRLC_CSIB_LENGTH[0], sizeof(mmRLC_CSIB_LENGTH)/sizeof(mmRLC_CSIB_LENGTH[0]), 0, 0 },
+	{ "mmRLC_CP_RESPONSE0", REG_MMIO, 0xeca5, &mmRLC_CP_RESPONSE0[0], sizeof(mmRLC_CP_RESPONSE0)/sizeof(mmRLC_CP_RESPONSE0[0]), 0, 0 },
+	{ "mmRLC_CP_RESPONSE1", REG_MMIO, 0xeca6, &mmRLC_CP_RESPONSE1[0], sizeof(mmRLC_CP_RESPONSE1)/sizeof(mmRLC_CP_RESPONSE1[0]), 0, 0 },
+	{ "mmRLC_CP_RESPONSE2", REG_MMIO, 0xeca7, &mmRLC_CP_RESPONSE2[0], sizeof(mmRLC_CP_RESPONSE2)/sizeof(mmRLC_CP_RESPONSE2[0]), 0, 0 },
+	{ "mmRLC_CP_RESPONSE3", REG_MMIO, 0xeca8, &mmRLC_CP_RESPONSE3[0], sizeof(mmRLC_CP_RESPONSE3)/sizeof(mmRLC_CP_RESPONSE3[0]), 0, 0 },
+	{ "mmRLC_SMU_COMMAND", REG_MMIO, 0xeca9, &mmRLC_SMU_COMMAND[0], sizeof(mmRLC_SMU_COMMAND)/sizeof(mmRLC_SMU_COMMAND[0]), 0, 0 },
+	{ "mmRLC_CP_SCHEDULERS", REG_MMIO, 0xecaa, &mmRLC_CP_SCHEDULERS[0], sizeof(mmRLC_CP_SCHEDULERS)/sizeof(mmRLC_CP_SCHEDULERS[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG15", REG_SMC, 0xf, &ixCLIPPER_DEBUG_REG15[0], sizeof(ixCLIPPER_DEBUG_REG15)/sizeof(ixCLIPPER_DEBUG_REG15[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG15", REG_SMC, 0xf, &ixVGT_DEBUG_REG15[0], sizeof(ixVGT_DEBUG_REG15)/sizeof(ixVGT_DEBUG_REG15[0]), 0, 0 },
+	{ "mmCGTS_SM_CTRL_REG", REG_MMIO, 0xf000, &mmCGTS_SM_CTRL_REG[0], sizeof(mmCGTS_SM_CTRL_REG)/sizeof(mmCGTS_SM_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_CTRL_REG", REG_MMIO, 0xf001, &mmCGTS_RD_CTRL_REG[0], sizeof(mmCGTS_RD_CTRL_REG)/sizeof(mmCGTS_RD_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_REG", REG_MMIO, 0xf002, &mmCGTS_RD_REG[0], sizeof(mmCGTS_RD_REG)/sizeof(mmCGTS_RD_REG[0]), 0, 0 },
+	{ "mmCGTS_TCC_DISABLE", REG_MMIO, 0xf003, &mmCGTS_TCC_DISABLE[0], sizeof(mmCGTS_TCC_DISABLE)/sizeof(mmCGTS_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_USER_TCC_DISABLE", REG_MMIO, 0xf004, &mmCGTS_USER_TCC_DISABLE[0], sizeof(mmCGTS_USER_TCC_DISABLE)/sizeof(mmCGTS_USER_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_CU0_SP0_CTRL_REG", REG_MMIO, 0xf008, &mmCGTS_CU0_SP0_CTRL_REG[0], sizeof(mmCGTS_CU0_SP0_CTRL_REG)/sizeof(mmCGTS_CU0_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_LDS_SQ_CTRL_REG", REG_MMIO, 0xf009, &mmCGTS_CU0_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_TA_SQC_CTRL_REG", REG_MMIO, 0xf00a, &mmCGTS_CU0_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_SP1_CTRL_REG", REG_MMIO, 0xf00b, &mmCGTS_CU0_SP1_CTRL_REG[0], sizeof(mmCGTS_CU0_SP1_CTRL_REG)/sizeof(mmCGTS_CU0_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_TD_TCP_CTRL_REG", REG_MMIO, 0xf00c, &mmCGTS_CU0_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_SP0_CTRL_REG", REG_MMIO, 0xf00d, &mmCGTS_CU1_SP0_CTRL_REG[0], sizeof(mmCGTS_CU1_SP0_CTRL_REG)/sizeof(mmCGTS_CU1_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_LDS_SQ_CTRL_REG", REG_MMIO, 0xf00e, &mmCGTS_CU1_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_TA_CTRL_REG", REG_MMIO, 0xf00f, &mmCGTS_CU1_TA_CTRL_REG[0], sizeof(mmCGTS_CU1_TA_CTRL_REG)/sizeof(mmCGTS_CU1_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_SP1_CTRL_REG", REG_MMIO, 0xf010, &mmCGTS_CU1_SP1_CTRL_REG[0], sizeof(mmCGTS_CU1_SP1_CTRL_REG)/sizeof(mmCGTS_CU1_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_TD_TCP_CTRL_REG", REG_MMIO, 0xf011, &mmCGTS_CU1_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_SP0_CTRL_REG", REG_MMIO, 0xf012, &mmCGTS_CU2_SP0_CTRL_REG[0], sizeof(mmCGTS_CU2_SP0_CTRL_REG)/sizeof(mmCGTS_CU2_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_LDS_SQ_CTRL_REG", REG_MMIO, 0xf013, &mmCGTS_CU2_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_TA_CTRL_REG", REG_MMIO, 0xf014, &mmCGTS_CU2_TA_CTRL_REG[0], sizeof(mmCGTS_CU2_TA_CTRL_REG)/sizeof(mmCGTS_CU2_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_SP1_CTRL_REG", REG_MMIO, 0xf015, &mmCGTS_CU2_SP1_CTRL_REG[0], sizeof(mmCGTS_CU2_SP1_CTRL_REG)/sizeof(mmCGTS_CU2_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_TD_TCP_CTRL_REG", REG_MMIO, 0xf016, &mmCGTS_CU2_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_SP0_CTRL_REG", REG_MMIO, 0xf017, &mmCGTS_CU3_SP0_CTRL_REG[0], sizeof(mmCGTS_CU3_SP0_CTRL_REG)/sizeof(mmCGTS_CU3_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_LDS_SQ_CTRL_REG", REG_MMIO, 0xf018, &mmCGTS_CU3_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_TA_CTRL_REG", REG_MMIO, 0xf019, &mmCGTS_CU3_TA_CTRL_REG[0], sizeof(mmCGTS_CU3_TA_CTRL_REG)/sizeof(mmCGTS_CU3_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_SP1_CTRL_REG", REG_MMIO, 0xf01a, &mmCGTS_CU3_SP1_CTRL_REG[0], sizeof(mmCGTS_CU3_SP1_CTRL_REG)/sizeof(mmCGTS_CU3_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_TD_TCP_CTRL_REG", REG_MMIO, 0xf01b, &mmCGTS_CU3_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_SP0_CTRL_REG", REG_MMIO, 0xf01c, &mmCGTS_CU4_SP0_CTRL_REG[0], sizeof(mmCGTS_CU4_SP0_CTRL_REG)/sizeof(mmCGTS_CU4_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_LDS_SQ_CTRL_REG", REG_MMIO, 0xf01d, &mmCGTS_CU4_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_TA_SQC_CTRL_REG", REG_MMIO, 0xf01e, &mmCGTS_CU4_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_SP1_CTRL_REG", REG_MMIO, 0xf01f, &mmCGTS_CU4_SP1_CTRL_REG[0], sizeof(mmCGTS_CU4_SP1_CTRL_REG)/sizeof(mmCGTS_CU4_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_TD_TCP_CTRL_REG", REG_MMIO, 0xf020, &mmCGTS_CU4_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_SP0_CTRL_REG", REG_MMIO, 0xf021, &mmCGTS_CU5_SP0_CTRL_REG[0], sizeof(mmCGTS_CU5_SP0_CTRL_REG)/sizeof(mmCGTS_CU5_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_LDS_SQ_CTRL_REG", REG_MMIO, 0xf022, &mmCGTS_CU5_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_TA_CTRL_REG", REG_MMIO, 0xf023, &mmCGTS_CU5_TA_CTRL_REG[0], sizeof(mmCGTS_CU5_TA_CTRL_REG)/sizeof(mmCGTS_CU5_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_SP1_CTRL_REG", REG_MMIO, 0xf024, &mmCGTS_CU5_SP1_CTRL_REG[0], sizeof(mmCGTS_CU5_SP1_CTRL_REG)/sizeof(mmCGTS_CU5_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_TD_TCP_CTRL_REG", REG_MMIO, 0xf025, &mmCGTS_CU5_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_SP0_CTRL_REG", REG_MMIO, 0xf026, &mmCGTS_CU6_SP0_CTRL_REG[0], sizeof(mmCGTS_CU6_SP0_CTRL_REG)/sizeof(mmCGTS_CU6_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_LDS_SQ_CTRL_REG", REG_MMIO, 0xf027, &mmCGTS_CU6_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_TA_CTRL_REG", REG_MMIO, 0xf028, &mmCGTS_CU6_TA_CTRL_REG[0], sizeof(mmCGTS_CU6_TA_CTRL_REG)/sizeof(mmCGTS_CU6_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_SP1_CTRL_REG", REG_MMIO, 0xf029, &mmCGTS_CU6_SP1_CTRL_REG[0], sizeof(mmCGTS_CU6_SP1_CTRL_REG)/sizeof(mmCGTS_CU6_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_TD_TCP_CTRL_REG", REG_MMIO, 0xf02a, &mmCGTS_CU6_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_SP0_CTRL_REG", REG_MMIO, 0xf02b, &mmCGTS_CU7_SP0_CTRL_REG[0], sizeof(mmCGTS_CU7_SP0_CTRL_REG)/sizeof(mmCGTS_CU7_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_LDS_SQ_CTRL_REG", REG_MMIO, 0xf02c, &mmCGTS_CU7_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_TA_CTRL_REG", REG_MMIO, 0xf02d, &mmCGTS_CU7_TA_CTRL_REG[0], sizeof(mmCGTS_CU7_TA_CTRL_REG)/sizeof(mmCGTS_CU7_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_SP1_CTRL_REG", REG_MMIO, 0xf02e, &mmCGTS_CU7_SP1_CTRL_REG[0], sizeof(mmCGTS_CU7_SP1_CTRL_REG)/sizeof(mmCGTS_CU7_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_TD_TCP_CTRL_REG", REG_MMIO, 0xf02f, &mmCGTS_CU7_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_SP0_CTRL_REG", REG_MMIO, 0xf030, &mmCGTS_CU8_SP0_CTRL_REG[0], sizeof(mmCGTS_CU8_SP0_CTRL_REG)/sizeof(mmCGTS_CU8_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_LDS_SQ_CTRL_REG", REG_MMIO, 0xf031, &mmCGTS_CU8_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_TA_SQC_CTRL_REG", REG_MMIO, 0xf032, &mmCGTS_CU8_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_SP1_CTRL_REG", REG_MMIO, 0xf033, &mmCGTS_CU8_SP1_CTRL_REG[0], sizeof(mmCGTS_CU8_SP1_CTRL_REG)/sizeof(mmCGTS_CU8_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_TD_TCP_CTRL_REG", REG_MMIO, 0xf034, &mmCGTS_CU8_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_SP0_CTRL_REG", REG_MMIO, 0xf035, &mmCGTS_CU9_SP0_CTRL_REG[0], sizeof(mmCGTS_CU9_SP0_CTRL_REG)/sizeof(mmCGTS_CU9_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_LDS_SQ_CTRL_REG", REG_MMIO, 0xf036, &mmCGTS_CU9_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_TA_CTRL_REG", REG_MMIO, 0xf037, &mmCGTS_CU9_TA_CTRL_REG[0], sizeof(mmCGTS_CU9_TA_CTRL_REG)/sizeof(mmCGTS_CU9_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_SP1_CTRL_REG", REG_MMIO, 0xf038, &mmCGTS_CU9_SP1_CTRL_REG[0], sizeof(mmCGTS_CU9_SP1_CTRL_REG)/sizeof(mmCGTS_CU9_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_TD_TCP_CTRL_REG", REG_MMIO, 0xf039, &mmCGTS_CU9_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_SP0_CTRL_REG", REG_MMIO, 0xf03a, &mmCGTS_CU10_SP0_CTRL_REG[0], sizeof(mmCGTS_CU10_SP0_CTRL_REG)/sizeof(mmCGTS_CU10_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_LDS_SQ_CTRL_REG", REG_MMIO, 0xf03b, &mmCGTS_CU10_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_TA_CTRL_REG", REG_MMIO, 0xf03c, &mmCGTS_CU10_TA_CTRL_REG[0], sizeof(mmCGTS_CU10_TA_CTRL_REG)/sizeof(mmCGTS_CU10_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_SP1_CTRL_REG", REG_MMIO, 0xf03d, &mmCGTS_CU10_SP1_CTRL_REG[0], sizeof(mmCGTS_CU10_SP1_CTRL_REG)/sizeof(mmCGTS_CU10_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_TD_TCP_CTRL_REG", REG_MMIO, 0xf03e, &mmCGTS_CU10_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_SP0_CTRL_REG", REG_MMIO, 0xf03f, &mmCGTS_CU11_SP0_CTRL_REG[0], sizeof(mmCGTS_CU11_SP0_CTRL_REG)/sizeof(mmCGTS_CU11_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_LDS_SQ_CTRL_REG", REG_MMIO, 0xf040, &mmCGTS_CU11_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_TA_CTRL_REG", REG_MMIO, 0xf041, &mmCGTS_CU11_TA_CTRL_REG[0], sizeof(mmCGTS_CU11_TA_CTRL_REG)/sizeof(mmCGTS_CU11_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_SP1_CTRL_REG", REG_MMIO, 0xf042, &mmCGTS_CU11_SP1_CTRL_REG[0], sizeof(mmCGTS_CU11_SP1_CTRL_REG)/sizeof(mmCGTS_CU11_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_TD_TCP_CTRL_REG", REG_MMIO, 0xf043, &mmCGTS_CU11_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_SP0_CTRL_REG", REG_MMIO, 0xf044, &mmCGTS_CU12_SP0_CTRL_REG[0], sizeof(mmCGTS_CU12_SP0_CTRL_REG)/sizeof(mmCGTS_CU12_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_LDS_SQ_CTRL_REG", REG_MMIO, 0xf045, &mmCGTS_CU12_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_TA_SQC_CTRL_REG", REG_MMIO, 0xf046, &mmCGTS_CU12_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_SP1_CTRL_REG", REG_MMIO, 0xf047, &mmCGTS_CU12_SP1_CTRL_REG[0], sizeof(mmCGTS_CU12_SP1_CTRL_REG)/sizeof(mmCGTS_CU12_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_TD_TCP_CTRL_REG", REG_MMIO, 0xf048, &mmCGTS_CU12_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_SP0_CTRL_REG", REG_MMIO, 0xf049, &mmCGTS_CU13_SP0_CTRL_REG[0], sizeof(mmCGTS_CU13_SP0_CTRL_REG)/sizeof(mmCGTS_CU13_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04a, &mmCGTS_CU13_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_TA_CTRL_REG", REG_MMIO, 0xf04b, &mmCGTS_CU13_TA_CTRL_REG[0], sizeof(mmCGTS_CU13_TA_CTRL_REG)/sizeof(mmCGTS_CU13_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_SP1_CTRL_REG", REG_MMIO, 0xf04c, &mmCGTS_CU13_SP1_CTRL_REG[0], sizeof(mmCGTS_CU13_SP1_CTRL_REG)/sizeof(mmCGTS_CU13_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_TD_TCP_CTRL_REG", REG_MMIO, 0xf04d, &mmCGTS_CU13_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_SP0_CTRL_REG", REG_MMIO, 0xf04e, &mmCGTS_CU14_SP0_CTRL_REG[0], sizeof(mmCGTS_CU14_SP0_CTRL_REG)/sizeof(mmCGTS_CU14_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04f, &mmCGTS_CU14_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_TA_CTRL_REG", REG_MMIO, 0xf050, &mmCGTS_CU14_TA_CTRL_REG[0], sizeof(mmCGTS_CU14_TA_CTRL_REG)/sizeof(mmCGTS_CU14_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_SP1_CTRL_REG", REG_MMIO, 0xf051, &mmCGTS_CU14_SP1_CTRL_REG[0], sizeof(mmCGTS_CU14_SP1_CTRL_REG)/sizeof(mmCGTS_CU14_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_TD_TCP_CTRL_REG", REG_MMIO, 0xf052, &mmCGTS_CU14_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_SP0_CTRL_REG", REG_MMIO, 0xf053, &mmCGTS_CU15_SP0_CTRL_REG[0], sizeof(mmCGTS_CU15_SP0_CTRL_REG)/sizeof(mmCGTS_CU15_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_LDS_SQ_CTRL_REG", REG_MMIO, 0xf054, &mmCGTS_CU15_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_TA_CTRL_REG", REG_MMIO, 0xf055, &mmCGTS_CU15_TA_CTRL_REG[0], sizeof(mmCGTS_CU15_TA_CTRL_REG)/sizeof(mmCGTS_CU15_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_SP1_CTRL_REG", REG_MMIO, 0xf056, &mmCGTS_CU15_SP1_CTRL_REG[0], sizeof(mmCGTS_CU15_SP1_CTRL_REG)/sizeof(mmCGTS_CU15_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_TD_TCP_CTRL_REG", REG_MMIO, 0xf057, &mmCGTS_CU15_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTT_SPI_CLK_CTRL", REG_MMIO, 0xf080, &mmCGTT_SPI_CLK_CTRL[0], sizeof(mmCGTT_SPI_CLK_CTRL)/sizeof(mmCGTT_SPI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_PC_CLK_CTRL", REG_MMIO, 0xf081, &mmCGTT_PC_CLK_CTRL[0], sizeof(mmCGTT_PC_CLK_CTRL)/sizeof(mmCGTT_PC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_BCI_CLK_CTRL", REG_MMIO, 0xf082, &mmCGTT_BCI_CLK_CTRL[0], sizeof(mmCGTT_BCI_CLK_CTRL)/sizeof(mmCGTT_BCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_VGT_CLK_CTRL", REG_MMIO, 0xf084, &mmCGTT_VGT_CLK_CTRL[0], sizeof(mmCGTT_VGT_CLK_CTRL)/sizeof(mmCGTT_VGT_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_IA_CLK_CTRL", REG_MMIO, 0xf085, &mmCGTT_IA_CLK_CTRL[0], sizeof(mmCGTT_IA_CLK_CTRL)/sizeof(mmCGTT_IA_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_WD_CLK_CTRL", REG_MMIO, 0xf086, &mmCGTT_WD_CLK_CTRL[0], sizeof(mmCGTT_WD_CLK_CTRL)/sizeof(mmCGTT_WD_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_PA_CLK_CTRL", REG_MMIO, 0xf088, &mmCGTT_PA_CLK_CTRL[0], sizeof(mmCGTT_PA_CLK_CTRL)/sizeof(mmCGTT_PA_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SC_CLK_CTRL", REG_MMIO, 0xf089, &mmCGTT_SC_CLK_CTRL[0], sizeof(mmCGTT_SC_CLK_CTRL)/sizeof(mmCGTT_SC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQ_CLK_CTRL", REG_MMIO, 0xf08c, &mmCGTT_SQ_CLK_CTRL[0], sizeof(mmCGTT_SQ_CLK_CTRL)/sizeof(mmCGTT_SQ_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQG_CLK_CTRL", REG_MMIO, 0xf08d, &mmCGTT_SQG_CLK_CTRL[0], sizeof(mmCGTT_SQG_CLK_CTRL)/sizeof(mmCGTT_SQG_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_ALU_CLK_CTRL", REG_MMIO, 0xf08e, &mmSQ_ALU_CLK_CTRL[0], sizeof(mmSQ_ALU_CLK_CTRL)/sizeof(mmSQ_ALU_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_TEX_CLK_CTRL", REG_MMIO, 0xf08f, &mmSQ_TEX_CLK_CTRL[0], sizeof(mmSQ_TEX_CLK_CTRL)/sizeof(mmSQ_TEX_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_LDS_CLK_CTRL", REG_MMIO, 0xf090, &mmSQ_LDS_CLK_CTRL[0], sizeof(mmSQ_LDS_CLK_CTRL)/sizeof(mmSQ_LDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE", REG_MMIO, 0xf091, &mmSQ_POWER_THROTTLE[0], sizeof(mmSQ_POWER_THROTTLE)/sizeof(mmSQ_POWER_THROTTLE[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE2", REG_MMIO, 0xf092, &mmSQ_POWER_THROTTLE2[0], sizeof(mmSQ_POWER_THROTTLE2)/sizeof(mmSQ_POWER_THROTTLE2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL0", REG_MMIO, 0xf094, &mmCGTT_SX_CLK_CTRL0[0], sizeof(mmCGTT_SX_CLK_CTRL0)/sizeof(mmCGTT_SX_CLK_CTRL0[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL1", REG_MMIO, 0xf095, &mmCGTT_SX_CLK_CTRL1[0], sizeof(mmCGTT_SX_CLK_CTRL1)/sizeof(mmCGTT_SX_CLK_CTRL1[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL2", REG_MMIO, 0xf096, &mmCGTT_SX_CLK_CTRL2[0], sizeof(mmCGTT_SX_CLK_CTRL2)/sizeof(mmCGTT_SX_CLK_CTRL2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL3", REG_MMIO, 0xf097, &mmCGTT_SX_CLK_CTRL3[0], sizeof(mmCGTT_SX_CLK_CTRL3)/sizeof(mmCGTT_SX_CLK_CTRL3[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL4", REG_MMIO, 0xf098, &mmCGTT_SX_CLK_CTRL4[0], sizeof(mmCGTT_SX_CLK_CTRL4)/sizeof(mmCGTT_SX_CLK_CTRL4[0]), 0, 0 },
+	{ "mmTD_CGTT_CTRL", REG_MMIO, 0xf09c, &mmTD_CGTT_CTRL[0], sizeof(mmTD_CGTT_CTRL)/sizeof(mmTD_CGTT_CTRL[0]), 0, 0 },
+	{ "mmTA_CGTT_CTRL", REG_MMIO, 0xf09d, &mmTA_CGTT_CTRL[0], sizeof(mmTA_CGTT_CTRL)/sizeof(mmTA_CGTT_CTRL[0]), 0, 0 },
+	{ "mmCGTT_TCP_CLK_CTRL", REG_MMIO, 0xf09e, &mmCGTT_TCP_CLK_CTRL[0], sizeof(mmCGTT_TCP_CLK_CTRL)/sizeof(mmCGTT_TCP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_TCI_CLK_CTRL", REG_MMIO, 0xf09f, &mmCGTT_TCI_CLK_CTRL[0], sizeof(mmCGTT_TCI_CLK_CTRL)/sizeof(mmCGTT_TCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_GDS_CLK_CTRL", REG_MMIO, 0xf0a0, &mmCGTT_GDS_CLK_CTRL[0], sizeof(mmCGTT_GDS_CLK_CTRL)/sizeof(mmCGTT_GDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmDB_CGTT_CLK_CTRL_0", REG_MMIO, 0xf0a4, &mmDB_CGTT_CLK_CTRL_0[0], sizeof(mmDB_CGTT_CLK_CTRL_0)/sizeof(mmDB_CGTT_CLK_CTRL_0[0]), 0, 0 },
+	{ "mmCB_CGTT_SCLK_CTRL", REG_MMIO, 0xf0a8, &mmCB_CGTT_SCLK_CTRL[0], sizeof(mmCB_CGTT_SCLK_CTRL)/sizeof(mmCB_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCC_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ac, &mmTCC_CGTT_SCLK_CTRL[0], sizeof(mmTCC_CGTT_SCLK_CTRL)/sizeof(mmTCC_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCA_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ad, &mmTCA_CGTT_SCLK_CTRL[0], sizeof(mmTCA_CGTT_SCLK_CTRL)/sizeof(mmTCA_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CP_CLK_CTRL", REG_MMIO, 0xf0b0, &mmCGTT_CP_CLK_CTRL[0], sizeof(mmCGTT_CP_CLK_CTRL)/sizeof(mmCGTT_CP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CPF_CLK_CTRL", REG_MMIO, 0xf0b1, &mmCGTT_CPF_CLK_CTRL[0], sizeof(mmCGTT_CPF_CLK_CTRL)/sizeof(mmCGTT_CPF_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CPC_CLK_CTRL", REG_MMIO, 0xf0b2, &mmCGTT_CPC_CLK_CTRL[0], sizeof(mmCGTT_CPC_CLK_CTRL)/sizeof(mmCGTT_CPC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_RLC_CLK_CTRL", REG_MMIO, 0xf0b8, &mmCGTT_RLC_CLK_CTRL[0], sizeof(mmCGTT_RLC_CLK_CTRL)/sizeof(mmCGTT_RLC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_ADDR", REG_MMIO, 0xf814, &mmCP_PFP_UCODE_ADDR[0], sizeof(mmCP_PFP_UCODE_ADDR)/sizeof(mmCP_PFP_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_DATA", REG_MMIO, 0xf815, &mmCP_PFP_UCODE_DATA[0], sizeof(mmCP_PFP_UCODE_DATA)/sizeof(mmCP_PFP_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_ME_RAM_RADDR", REG_MMIO, 0xf816, &mmCP_ME_RAM_RADDR[0], sizeof(mmCP_ME_RAM_RADDR)/sizeof(mmCP_ME_RAM_RADDR[0]), 0, 0 },
+	{ "mmCP_ME_RAM_DATA", REG_MMIO, 0xf817, &mmCP_ME_RAM_DATA[0], sizeof(mmCP_ME_RAM_DATA)/sizeof(mmCP_ME_RAM_DATA[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_ADDR", REG_MMIO, 0xf818, &mmCP_CE_UCODE_ADDR[0], sizeof(mmCP_CE_UCODE_ADDR)/sizeof(mmCP_CE_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_DATA", REG_MMIO, 0xf819, &mmCP_CE_UCODE_DATA[0], sizeof(mmCP_CE_UCODE_DATA)/sizeof(mmCP_CE_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_UCODE_ADDR", REG_MMIO, 0xf81a, &mmCP_MEC_ME1_UCODE_ADDR[0], sizeof(mmCP_MEC_ME1_UCODE_ADDR)/sizeof(mmCP_MEC_ME1_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_UCODE_DATA", REG_MMIO, 0xf81b, &mmCP_MEC_ME1_UCODE_DATA[0], sizeof(mmCP_MEC_ME1_UCODE_DATA)/sizeof(mmCP_MEC_ME1_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_UCODE_ADDR", REG_MMIO, 0xf81c, &mmCP_MEC_ME2_UCODE_ADDR[0], sizeof(mmCP_MEC_ME2_UCODE_ADDR)/sizeof(mmCP_MEC_ME2_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_UCODE_DATA", REG_MMIO, 0xf81d, &mmCP_MEC_ME2_UCODE_DATA[0], sizeof(mmCP_MEC_ME2_UCODE_DATA)/sizeof(mmCP_MEC_ME2_UCODE_DATA[0]), 0, 0 },
+	{ "mmGPU_BIST_CONTROL", REG_MMIO, 0xf835, &mmGPU_BIST_CONTROL[0], sizeof(mmGPU_BIST_CONTROL)/sizeof(mmGPU_BIST_CONTROL[0]), 0, 0 },
+	{ "mmRLC_ROM_CNTL", REG_MMIO, 0xf836, &mmRLC_ROM_CNTL[0], sizeof(mmRLC_ROM_CNTL)/sizeof(mmRLC_ROM_CNTL[0]), 0, 0 },
+	{ "mmRLC_HYP_GPM_UCODE_ADDR", REG_MMIO, 0xf83c, &mmRLC_HYP_GPM_UCODE_ADDR[0], sizeof(mmRLC_HYP_GPM_UCODE_ADDR)/sizeof(mmRLC_HYP_GPM_UCODE_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_UCODE_ADDR", REG_MMIO, 0xf83c, &mmRLC_GPM_UCODE_ADDR[0], sizeof(mmRLC_GPM_UCODE_ADDR)/sizeof(mmRLC_GPM_UCODE_ADDR[0]), 0, 0 },
+	{ "mmRLC_HYP_GPM_UCODE_DATA", REG_MMIO, 0xf83d, &mmRLC_HYP_GPM_UCODE_DATA[0], sizeof(mmRLC_HYP_GPM_UCODE_DATA)/sizeof(mmRLC_HYP_GPM_UCODE_DATA[0]), 0, 0 },
+	{ "mmRLC_GPM_UCODE_DATA", REG_MMIO, 0xf83d, &mmRLC_GPM_UCODE_DATA[0], sizeof(mmRLC_GPM_UCODE_DATA)/sizeof(mmRLC_GPM_UCODE_DATA[0]), 0, 0 },
+	{ "mmGRBM_HYP_CAM_INDEX", REG_MMIO, 0xf83e, &mmGRBM_HYP_CAM_INDEX[0], sizeof(mmGRBM_HYP_CAM_INDEX)/sizeof(mmGRBM_HYP_CAM_INDEX[0]), 0, 0 },
+	{ "mmGRBM_CAM_INDEX", REG_MMIO, 0xf83e, &mmGRBM_CAM_INDEX[0], sizeof(mmGRBM_CAM_INDEX)/sizeof(mmGRBM_CAM_INDEX[0]), 0, 0 },
+	{ "mmGRBM_HYP_CAM_DATA", REG_MMIO, 0xf83f, &mmGRBM_HYP_CAM_DATA[0], sizeof(mmGRBM_HYP_CAM_DATA)/sizeof(mmGRBM_HYP_CAM_DATA[0]), 0, 0 },
+	{ "mmGRBM_CAM_DATA", REG_MMIO, 0xf83f, &mmGRBM_CAM_DATA[0], sizeof(mmGRBM_CAM_DATA)/sizeof(mmGRBM_CAM_DATA[0]), 0, 0 },
+	{ "mmSQ_HV_VMID_CTRL", REG_MMIO, 0xf840, &mmSQ_HV_VMID_CTRL[0], sizeof(mmSQ_HV_VMID_CTRL)/sizeof(mmSQ_HV_VMID_CTRL[0]), 0, 0 },
+	{ "mmGFX_PIPE_PRIORITY", REG_MMIO, 0xf87f, &mmGFX_PIPE_PRIORITY[0], sizeof(mmGFX_PIPE_PRIORITY)/sizeof(mmGFX_PIPE_PRIORITY[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_VF_ENABLE", REG_MMIO, 0xfb00, &mmRLC_GPU_IOV_VF_ENABLE[0], sizeof(mmRLC_GPU_IOV_VF_ENABLE)/sizeof(mmRLC_GPU_IOV_VF_ENABLE[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG1", REG_MMIO, 0xfb01, &mmRLC_GPU_IOV_CFG_REG1[0], sizeof(mmRLC_GPU_IOV_CFG_REG1)/sizeof(mmRLC_GPU_IOV_CFG_REG1[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG2", REG_MMIO, 0xfb02, &mmRLC_GPU_IOV_CFG_REG2[0], sizeof(mmRLC_GPU_IOV_CFG_REG2)/sizeof(mmRLC_GPU_IOV_CFG_REG2[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG6", REG_MMIO, 0xfb06, &mmRLC_GPU_IOV_CFG_REG6[0], sizeof(mmRLC_GPU_IOV_CFG_REG6)/sizeof(mmRLC_GPU_IOV_CFG_REG6[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG8", REG_MMIO, 0xfb08, &mmRLC_GPU_IOV_CFG_REG8[0], sizeof(mmRLC_GPU_IOV_CFG_REG8)/sizeof(mmRLC_GPU_IOV_CFG_REG8[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG9", REG_MMIO, 0xfb21, &mmRLC_GPU_IOV_CFG_REG9[0], sizeof(mmRLC_GPU_IOV_CFG_REG9)/sizeof(mmRLC_GPU_IOV_CFG_REG9[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG10", REG_MMIO, 0xfb22, &mmRLC_GPU_IOV_CFG_REG10[0], sizeof(mmRLC_GPU_IOV_CFG_REG10)/sizeof(mmRLC_GPU_IOV_CFG_REG10[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG11", REG_MMIO, 0xfb23, &mmRLC_GPU_IOV_CFG_REG11[0], sizeof(mmRLC_GPU_IOV_CFG_REG11)/sizeof(mmRLC_GPU_IOV_CFG_REG11[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG12", REG_MMIO, 0xfb24, &mmRLC_GPU_IOV_CFG_REG12[0], sizeof(mmRLC_GPU_IOV_CFG_REG12)/sizeof(mmRLC_GPU_IOV_CFG_REG12[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG13", REG_MMIO, 0xfb25, &mmRLC_GPU_IOV_CFG_REG13[0], sizeof(mmRLC_GPU_IOV_CFG_REG13)/sizeof(mmRLC_GPU_IOV_CFG_REG13[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG14", REG_MMIO, 0xfb26, &mmRLC_GPU_IOV_CFG_REG14[0], sizeof(mmRLC_GPU_IOV_CFG_REG14)/sizeof(mmRLC_GPU_IOV_CFG_REG14[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_CFG_REG15", REG_MMIO, 0xfb27, &mmRLC_GPU_IOV_CFG_REG15[0], sizeof(mmRLC_GPU_IOV_CFG_REG15)/sizeof(mmRLC_GPU_IOV_CFG_REG15[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_ACTIVE_FCN_ID", REG_MMIO, 0xfb40, &mmRLC_GPU_IOV_ACTIVE_FCN_ID[0], sizeof(mmRLC_GPU_IOV_ACTIVE_FCN_ID)/sizeof(mmRLC_GPU_IOV_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD2", REG_MMIO, 0xfb41, &mmRLC_GPM_VMID_THREAD2[0], sizeof(mmRLC_GPM_VMID_THREAD2)/sizeof(mmRLC_GPM_VMID_THREAD2[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_UCODE_ADDR", REG_MMIO, 0xfb42, &mmRLC_GPU_IOV_UCODE_ADDR[0], sizeof(mmRLC_GPU_IOV_UCODE_ADDR)/sizeof(mmRLC_GPU_IOV_UCODE_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_UCODE_DATA", REG_MMIO, 0xfb43, &mmRLC_GPU_IOV_UCODE_DATA[0], sizeof(mmRLC_GPU_IOV_UCODE_DATA)/sizeof(mmRLC_GPU_IOV_UCODE_DATA[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SCRATCH_ADDR", REG_MMIO, 0xfb44, &mmRLC_GPU_IOV_SCRATCH_ADDR[0], sizeof(mmRLC_GPU_IOV_SCRATCH_ADDR)/sizeof(mmRLC_GPU_IOV_SCRATCH_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SCRATCH_DATA", REG_MMIO, 0xfb45, &mmRLC_GPU_IOV_SCRATCH_DATA[0], sizeof(mmRLC_GPU_IOV_SCRATCH_DATA)/sizeof(mmRLC_GPU_IOV_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_F32_CNTL", REG_MMIO, 0xfb46, &mmRLC_GPU_IOV_F32_CNTL[0], sizeof(mmRLC_GPU_IOV_F32_CNTL)/sizeof(mmRLC_GPU_IOV_F32_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_F32_RESET", REG_MMIO, 0xfb47, &mmRLC_GPU_IOV_F32_RESET[0], sizeof(mmRLC_GPU_IOV_F32_RESET)/sizeof(mmRLC_GPU_IOV_F32_RESET[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SDMA0_STATUS", REG_MMIO, 0xfb48, &mmRLC_GPU_IOV_SDMA0_STATUS[0], sizeof(mmRLC_GPU_IOV_SDMA0_STATUS)/sizeof(mmRLC_GPU_IOV_SDMA0_STATUS[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SDMA1_STATUS", REG_MMIO, 0xfb49, &mmRLC_GPU_IOV_SDMA1_STATUS[0], sizeof(mmRLC_GPU_IOV_SDMA1_STATUS)/sizeof(mmRLC_GPU_IOV_SDMA1_STATUS[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SMU_RESPONSE", REG_MMIO, 0xfb4a, &mmRLC_GPU_IOV_SMU_RESPONSE[0], sizeof(mmRLC_GPU_IOV_SMU_RESPONSE)/sizeof(mmRLC_GPU_IOV_SMU_RESPONSE[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_VIRT_RESET_REQ", REG_MMIO, 0xfb4c, &mmRLC_GPU_IOV_VIRT_RESET_REQ[0], sizeof(mmRLC_GPU_IOV_VIRT_RESET_REQ)/sizeof(mmRLC_GPU_IOV_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_RLC_RESPONSE", REG_MMIO, 0xfb4d, &mmRLC_GPU_IOV_RLC_RESPONSE[0], sizeof(mmRLC_GPU_IOV_RLC_RESPONSE)/sizeof(mmRLC_GPU_IOV_RLC_RESPONSE[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_INT_DISABLE", REG_MMIO, 0xfb4e, &mmRLC_GPU_IOV_INT_DISABLE[0], sizeof(mmRLC_GPU_IOV_INT_DISABLE)/sizeof(mmRLC_GPU_IOV_INT_DISABLE[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_INT_FORCE", REG_MMIO, 0xfb4f, &mmRLC_GPU_IOV_INT_FORCE[0], sizeof(mmRLC_GPU_IOV_INT_FORCE)/sizeof(mmRLC_GPU_IOV_INT_FORCE[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SDMA0_BUSY_STATUS", REG_MMIO, 0xfb50, &mmRLC_GPU_IOV_SDMA0_BUSY_STATUS[0], sizeof(mmRLC_GPU_IOV_SDMA0_BUSY_STATUS)/sizeof(mmRLC_GPU_IOV_SDMA0_BUSY_STATUS[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SDMA1_BUSY_STATUS", REG_MMIO, 0xfb51, &mmRLC_GPU_IOV_SDMA1_BUSY_STATUS[0], sizeof(mmRLC_GPU_IOV_SDMA1_BUSY_STATUS)/sizeof(mmRLC_GPU_IOV_SDMA1_BUSY_STATUS[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SCH_0", REG_MMIO, 0xfb52, &mmRLC_GPU_IOV_SCH_0[0], sizeof(mmRLC_GPU_IOV_SCH_0)/sizeof(mmRLC_GPU_IOV_SCH_0[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SCH_1", REG_MMIO, 0xfb53, &mmRLC_GPU_IOV_SCH_1[0], sizeof(mmRLC_GPU_IOV_SCH_1)/sizeof(mmRLC_GPU_IOV_SCH_1[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SCH_2", REG_MMIO, 0xfb54, &mmRLC_GPU_IOV_SCH_2[0], sizeof(mmRLC_GPU_IOV_SCH_2)/sizeof(mmRLC_GPU_IOV_SCH_2[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SCH_3", REG_MMIO, 0xfb55, &mmRLC_GPU_IOV_SCH_3[0], sizeof(mmRLC_GPU_IOV_SCH_3)/sizeof(mmRLC_GPU_IOV_SCH_3[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_SCH_INT", REG_MMIO, 0xfb56, &mmRLC_GPU_IOV_SCH_INT[0], sizeof(mmRLC_GPU_IOV_SCH_INT)/sizeof(mmRLC_GPU_IOV_SCH_INT[0]), 0, 0 },
diff --git a/src/lib/ip/gfx81.c b/src/lib/ip/gfx81.c
new file mode 100644
index 0000000..ef19203
--- /dev/null
+++ b/src/lib/ip/gfx81.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gfx81_bits.i"
+
+static const struct umr_reg gfx81_registers[] = {
+#include "gfx81_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_gfx81(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gfx81";
+	ip->no_regs = sizeof(gfx81_registers)/sizeof(gfx81_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gfx81_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 1) ? grant : deny;
+	memcpy(ip->regs, gfx81_registers, sizeof(gfx81_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gfx81_bits.i b/src/lib/ip/gfx81_bits.i
new file mode 100644
index 0000000..f6c7e3f
--- /dev/null
+++ b/src/lib/ip/gfx81_bits.i
@@ -0,0 +1,15509 @@
+static struct umr_bitfield ixCLIPPER_DEBUG_REG00[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 8, 8, &umr_bitfield_default },
+	 { "su_clip_baryc_free", 9, 10, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 11, 11, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_full", 12, 12, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_empty", 13, 13, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_full", 14, 14, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_full", 16, 16, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_empty", 17, 17, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_full", 18, 18, &umr_bitfield_default },
+	 { "vgt_to_clips_fifo_empty", 19, 19, &umr_bitfield_default },
+	 { "vgt_to_clips_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "clipcode_fifo_fifo_empty", 21, 21, &umr_bitfield_default },
+	 { "clipcode_fifo_full", 22, 22, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_empty", 23, 23, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_write", 30, 30, &umr_bitfield_default },
+	 { "vgt_to_clipp_fifo_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPA_SC_DEBUG_REG0[] = {
+	 { "REG0_FIELD0", 0, 1, &umr_bitfield_default },
+	 { "REG0_FIELD1", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_CONNECT[] = {
+	 { "DOORBELL_OFFSET", 0, 20, &umr_bitfield_default },
+	 { "QUEUE_ID", 21, 23, &umr_bitfield_default },
+	 { "VMID", 26, 29, &umr_bitfield_default },
+	 { "UNORD_DISP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG0[] = {
+	 { "wd_busy_extended", 0, 0, &umr_bitfield_default },
+	 { "wd_nodma_busy_extended", 1, 1, &umr_bitfield_default },
+	 { "wd_busy", 2, 2, &umr_bitfield_default },
+	 { "wd_nodma_busy", 3, 3, &umr_bitfield_default },
+	 { "rbiu_busy", 4, 4, &umr_bitfield_default },
+	 { "spl_dma_busy", 5, 5, &umr_bitfield_default },
+	 { "spl_di_busy", 6, 6, &umr_bitfield_default },
+	 { "vgt0_active_q", 7, 7, &umr_bitfield_default },
+	 { "vgt1_active_q", 8, 8, &umr_bitfield_default },
+	 { "spl_dma_p1_busy", 9, 9, &umr_bitfield_default },
+	 { "rbiu_dr_p1_fifo_busy", 10, 10, &umr_bitfield_default },
+	 { "rbiu_di_p1_fifo_busy", 11, 11, &umr_bitfield_default },
+	 { "SPARE2", 12, 12, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_busy", 13, 13, &umr_bitfield_default },
+	 { "rbiu_spl_dr_valid", 14, 14, &umr_bitfield_default },
+	 { "spl_rbiu_dr_read", 15, 15, &umr_bitfield_default },
+	 { "SPARE3", 16, 16, &umr_bitfield_default },
+	 { "rbiu_di_fifo_busy", 17, 17, &umr_bitfield_default },
+	 { "rbiu_spl_di_valid", 18, 18, &umr_bitfield_default },
+	 { "spl_rbiu_di_read", 19, 19, &umr_bitfield_default },
+	 { "se0_synced_q", 20, 20, &umr_bitfield_default },
+	 { "se1_synced_q", 21, 21, &umr_bitfield_default },
+	 { "se2_synced_q", 22, 22, &umr_bitfield_default },
+	 { "se3_synced_q", 23, 23, &umr_bitfield_default },
+	 { "reg_clk_busy", 24, 24, &umr_bitfield_default },
+	 { "input_clk_busy", 25, 25, &umr_bitfield_default },
+	 { "core_clk_busy", 26, 26, &umr_bitfield_default },
+	 { "vgt2_active_q", 27, 27, &umr_bitfield_default },
+	 { "sclk_reg_vld", 28, 28, &umr_bitfield_default },
+	 { "sclk_input_vld", 29, 29, &umr_bitfield_default },
+	 { "sclk_core_vld", 30, 30, &umr_bitfield_default },
+	 { "vgt3_active_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG01[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_extra_bc_valid", 8, 10, &umr_bitfield_default },
+	 { "clip_vert_vte_valid", 11, 13, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_deallocate", 14, 16, &umr_bitfield_default },
+	 { "clip_to_outsm_deallocate_slot", 17, 19, &umr_bitfield_default },
+	 { "clip_to_outsm_null_primitive", 20, 20, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_2", 21, 21, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_1", 22, 22, &umr_bitfield_default },
+	 { "vte_positions_vte_clip_vte_naninf_kill_0", 23, 23, &umr_bitfield_default },
+	 { "vte_out_clip_rd_extra_bc_valid", 24, 24, &umr_bitfield_default },
+	 { "vte_out_clip_rd_vte_naninf_kill", 25, 25, &umr_bitfield_default },
+	 { "vte_out_clip_rd_vertex_store_indx", 26, 27, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 28, 28, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "vte_out_clip_fifo_fifo_empty", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPA_SC_DEBUG_REG1[] = {
+	 { "REG1_FIELD0", 0, 1, &umr_bitfield_default },
+	 { "REG1_FIELD1", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG1[] = {
+	 { "tag_hit", 0, 0, &umr_bitfield_default },
+	 { "tag_miss", 1, 1, &umr_bitfield_default },
+	 { "pixel_addr", 2, 16, &umr_bitfield_default },
+	 { "pixel_vld", 17, 17, &umr_bitfield_default },
+	 { "data_ready", 18, 18, &umr_bitfield_default },
+	 { "awaiting_data", 19, 19, &umr_bitfield_default },
+	 { "addr_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "addr_fifo_empty", 21, 21, &umr_bitfield_default },
+	 { "buffer_loaded", 22, 22, &umr_bitfield_default },
+	 { "buffer_invalid", 23, 23, &umr_bitfield_default },
+	 { "spare", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG1[] = {
+	 { "grbm_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "grbm_fifo_full", 1, 1, &umr_bitfield_default },
+	 { "grbm_fifo_we", 2, 2, &umr_bitfield_default },
+	 { "grbm_fifo_re", 3, 3, &umr_bitfield_default },
+	 { "draw_initiator_valid_q", 4, 4, &umr_bitfield_default },
+	 { "event_initiator_valid_q", 5, 5, &umr_bitfield_default },
+	 { "event_addr_valid_q", 6, 6, &umr_bitfield_default },
+	 { "dma_request_valid_q", 7, 7, &umr_bitfield_default },
+	 { "SPARE0", 8, 8, &umr_bitfield_default },
+	 { "min_indx_valid_q", 9, 9, &umr_bitfield_default },
+	 { "max_indx_valid_q", 10, 10, &umr_bitfield_default },
+	 { "indx_offset_valid_q", 11, 11, &umr_bitfield_default },
+	 { "grbm_fifo_rdata_reg_id", 12, 16, &umr_bitfield_default },
+	 { "grbm_fifo_rdata_state", 17, 19, &umr_bitfield_default },
+	 { "free_cnt_q", 20, 25, &umr_bitfield_default },
+	 { "rbiu_di_fifo_we", 26, 26, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_we", 27, 27, &umr_bitfield_default },
+	 { "rbiu_di_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "rbiu_di_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "rbiu_dr_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG16[] = {
+	 { "sm0_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm0_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm0_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm0_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm0_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm0_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm0_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm0_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm0_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm0_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm0_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG16[] = {
+	 { "gog_busy", 0, 0, &umr_bitfield_default },
+	 { "gog_state_q", 1, 3, &umr_bitfield_default },
+	 { "r0_rtr", 4, 4, &umr_bitfield_default },
+	 { "r1_rtr", 5, 5, &umr_bitfield_default },
+	 { "r1_upstream_rtr", 6, 6, &umr_bitfield_default },
+	 { "r2_vs_tbl_rtr", 7, 7, &umr_bitfield_default },
+	 { "r2_prim_rtr", 8, 8, &umr_bitfield_default },
+	 { "r2_indx_rtr", 9, 9, &umr_bitfield_default },
+	 { "r2_rtr", 10, 10, &umr_bitfield_default },
+	 { "gog_tm_vs_event_rtr", 11, 11, &umr_bitfield_default },
+	 { "r3_force_vs_tbl_we_rtr", 12, 12, &umr_bitfield_default },
+	 { "indx_valid_r2_q", 13, 13, &umr_bitfield_default },
+	 { "prim_valid_r2_q", 14, 14, &umr_bitfield_default },
+	 { "valid_r2_q", 15, 15, &umr_bitfield_default },
+	 { "prim_valid_r1_q", 16, 16, &umr_bitfield_default },
+	 { "indx_valid_r1_q", 17, 17, &umr_bitfield_default },
+	 { "valid_r1_q", 18, 18, &umr_bitfield_default },
+	 { "indx_valid_r0_q", 19, 19, &umr_bitfield_default },
+	 { "prim_valid_r0_q", 20, 20, &umr_bitfield_default },
+	 { "valid_r0_q", 21, 21, &umr_bitfield_default },
+	 { "send_event_q", 22, 22, &umr_bitfield_default },
+	 { "SPARE24", 23, 23, &umr_bitfield_default },
+	 { "vert_seen_since_sopg_r2_q", 24, 24, &umr_bitfield_default },
+	 { "gog_out_prim_state_sel", 25, 27, &umr_bitfield_default },
+	 { "multiple_streams_en_r1_q", 28, 28, &umr_bitfield_default },
+	 { "vs_vert_count_r2_q_not_0", 29, 29, &umr_bitfield_default },
+	 { "num_gs_r2_q_not_0", 30, 30, &umr_bitfield_default },
+	 { "new_vs_thread_r2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG17[] = {
+	 { "sm1_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm1_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm1_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm1_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm1_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm1_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm1_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm1_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm1_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm1_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm1_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG17[] = {
+	 { "gog_out_prim_rel_indx2_5_0", 0, 5, &umr_bitfield_default },
+	 { "gog_out_prim_rel_indx1_5_0", 6, 11, &umr_bitfield_default },
+	 { "gog_out_prim_rel_indx0_5_0", 12, 17, &umr_bitfield_default },
+	 { "gog_out_indx_13_0", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_MODE[] = {
+	 { "FP_ROUND", 0, 3, &umr_bitfield_default },
+	 { "FP_DENORM", 4, 7, &umr_bitfield_default },
+	 { "DX10_CLAMP", 8, 8, &umr_bitfield_default },
+	 { "IEEE", 9, 9, &umr_bitfield_default },
+	 { "LOD_CLAMPED", 10, 10, &umr_bitfield_default },
+	 { "DEBUG_EN", 11, 11, &umr_bitfield_default },
+	 { "EXCP_EN", 12, 20, &umr_bitfield_default },
+	 { "GPR_IDX_EN", 27, 27, &umr_bitfield_default },
+	 { "VSKIP", 28, 28, &umr_bitfield_default },
+	 { "CSP", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG18[] = {
+	 { "sm2_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm2_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm2_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm2_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm2_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm2_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm2_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm2_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm2_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm2_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm2_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_STATUS[] = {
+	 { "SCC", 0, 0, &umr_bitfield_default },
+	 { "SPI_PRIO", 1, 2, &umr_bitfield_default },
+	 { "USER_PRIO", 3, 4, &umr_bitfield_default },
+	 { "PRIV", 5, 5, &umr_bitfield_default },
+	 { "TRAP_EN", 6, 6, &umr_bitfield_default },
+	 { "TTRACE_EN", 7, 7, &umr_bitfield_default },
+	 { "EXPORT_RDY", 8, 8, &umr_bitfield_default },
+	 { "EXECZ", 9, 9, &umr_bitfield_default },
+	 { "VCCZ", 10, 10, &umr_bitfield_default },
+	 { "IN_TG", 11, 11, &umr_bitfield_default },
+	 { "IN_BARRIER", 12, 12, &umr_bitfield_default },
+	 { "HALT", 13, 13, &umr_bitfield_default },
+	 { "TRAP", 14, 14, &umr_bitfield_default },
+	 { "TTRACE_CU_EN", 15, 15, &umr_bitfield_default },
+	 { "VALID", 16, 16, &umr_bitfield_default },
+	 { "ECC_ERR", 17, 17, &umr_bitfield_default },
+	 { "SKIP_EXPORT", 18, 18, &umr_bitfield_default },
+	 { "PERF_EN", 19, 19, &umr_bitfield_default },
+	 { "COND_DBG_USER", 20, 20, &umr_bitfield_default },
+	 { "COND_DBG_SYS", 21, 21, &umr_bitfield_default },
+	 { "ALLOW_REPLAY", 22, 22, &umr_bitfield_default },
+	 { "INST_ATC", 23, 23, &umr_bitfield_default },
+	 { "MUST_EXPORT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG19[] = {
+	 { "sm3_prim_end_state", 0, 6, &umr_bitfield_default },
+	 { "sm3_ps_expand", 7, 7, &umr_bitfield_default },
+	 { "sm3_clip_vert_cnt", 8, 12, &umr_bitfield_default },
+	 { "sm3_vertex_clip_cnt", 13, 17, &umr_bitfield_default },
+	 { "sm3_inv_to_clip_data_valid_1", 18, 18, &umr_bitfield_default },
+	 { "sm3_inv_to_clip_data_valid_0", 19, 19, &umr_bitfield_default },
+	 { "sm3_current_state", 20, 26, &umr_bitfield_default },
+	 { "sm3_clip_to_clipga_clip_to_outsm_cnt_eq0", 27, 27, &umr_bitfield_default },
+	 { "sm3_clip_to_outsm_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "sm3_highest_priority_seq", 29, 29, &umr_bitfield_default },
+	 { "sm3_outputcliptoclipga_0", 30, 30, &umr_bitfield_default },
+	 { "sm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TRAPSTS[] = {
+	 { "EXCP", 0, 8, &umr_bitfield_default },
+	 { "SAVECTX", 10, 10, &umr_bitfield_default },
+	 { "EXCP_CYCLE", 16, 21, &umr_bitfield_default },
+	 { "DP_RATE", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG0[] = {
+	 { "position_address", 0, 5, &umr_bitfield_default },
+	 { "point_address", 6, 8, &umr_bitfield_default },
+	 { "sx_pending_rd_state_var_indx", 9, 11, &umr_bitfield_default },
+	 { "sx_pending_rd_req_mask", 12, 15, &umr_bitfield_default },
+	 { "sx_pending_rd_pci", 16, 25, &umr_bitfield_default },
+	 { "sx_pending_rd_aux_sel", 26, 27, &umr_bitfield_default },
+	 { "sx_pending_rd_sp_id", 28, 29, &umr_bitfield_default },
+	 { "sx_pending_rd_aux_inc", 30, 30, &umr_bitfield_default },
+	 { "sx_pending_rd_advance", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG20[] = {
+	 { "dbg_VGT_SPI_vsthread_sovertexindex", 0, 15, &umr_bitfield_default },
+	 { "dbg_VGT_SPI_vsthread_sovertexcount_not_0", 16, 16, &umr_bitfield_default },
+	 { "SPARE17", 17, 17, &umr_bitfield_default },
+	 { "alloc_counter_q", 18, 21, &umr_bitfield_default },
+	 { "curr_dealloc_distance_q", 22, 28, &umr_bitfield_default },
+	 { "new_allocate_q", 29, 29, &umr_bitfield_default },
+	 { "curr_slot_in_vtx_vect_q_not_0", 30, 30, &umr_bitfield_default },
+	 { "int_vtx_counter_q_not_0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_HW_ID[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "PIPE_ID", 6, 7, &umr_bitfield_default },
+	 { "CU_ID", 8, 11, &umr_bitfield_default },
+	 { "SH_ID", 12, 12, &umr_bitfield_default },
+	 { "SE_ID", 13, 14, &umr_bitfield_default },
+	 { "TG_ID", 16, 19, &umr_bitfield_default },
+	 { "VM_ID", 20, 23, &umr_bitfield_default },
+	 { "QUEUE_ID", 24, 26, &umr_bitfield_default },
+	 { "STATE_ID", 27, 29, &umr_bitfield_default },
+	 { "ME_ID", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG1[] = {
+	 { "available_positions", 0, 6, &umr_bitfield_default },
+	 { "sx_receive_indx", 7, 9, &umr_bitfield_default },
+	 { "sx_pending_fifo_contents", 10, 14, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_misc_vec_ena", 15, 15, &umr_bitfield_default },
+	 { "statevar_bits_disable_sp", 16, 19, &umr_bitfield_default },
+	 { "aux_sel", 20, 21, &umr_bitfield_default },
+	 { "sx_to_pa_empty_1", 22, 22, &umr_bitfield_default },
+	 { "sx_to_pa_empty_0", 23, 23, &umr_bitfield_default },
+	 { "pasx_req_cnt_1", 24, 27, &umr_bitfield_default },
+	 { "pasx_req_cnt_0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_GPR_ALLOC[] = {
+	 { "VGPR_BASE", 0, 5, &umr_bitfield_default },
+	 { "VGPR_SIZE", 8, 13, &umr_bitfield_default },
+	 { "SGPR_BASE", 16, 21, &umr_bitfield_default },
+	 { "SGPR_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG21[] = {
+	 { "out_indx_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "indx_side_fifo_empty", 1, 1, &umr_bitfield_default },
+	 { "pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe2_dr", 4, 4, &umr_bitfield_default },
+	 { "vsthread_buff_empty", 5, 5, &umr_bitfield_default },
+	 { "out_indx_fifo_full", 6, 6, &umr_bitfield_default },
+	 { "indx_side_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "pipe0_rtr", 8, 8, &umr_bitfield_default },
+	 { "pipe1_rtr", 9, 9, &umr_bitfield_default },
+	 { "pipe2_rtr", 10, 10, &umr_bitfield_default },
+	 { "vsthread_buff_full", 11, 11, &umr_bitfield_default },
+	 { "interfaces_rtr", 12, 12, &umr_bitfield_default },
+	 { "indx_count_q_not_0", 13, 13, &umr_bitfield_default },
+	 { "wait_for_external_eopg_q", 14, 14, &umr_bitfield_default },
+	 { "full_state_p1_q", 15, 15, &umr_bitfield_default },
+	 { "indx_side_indx_valid", 16, 16, &umr_bitfield_default },
+	 { "stateid_p0_q", 17, 19, &umr_bitfield_default },
+	 { "is_event_p0_q", 20, 20, &umr_bitfield_default },
+	 { "lshs_dealloc_p1", 21, 21, &umr_bitfield_default },
+	 { "stream_id_r2_q", 22, 22, &umr_bitfield_default },
+	 { "vtx_vect_counter_q_not_0", 23, 23, &umr_bitfield_default },
+	 { "buff_full_p1", 24, 24, &umr_bitfield_default },
+	 { "strmout_valid_p1", 25, 25, &umr_bitfield_default },
+	 { "eotg_r2_q", 26, 26, &umr_bitfield_default },
+	 { "null_r2_q", 27, 27, &umr_bitfield_default },
+	 { "p0_dr", 28, 28, &umr_bitfield_default },
+	 { "p0_rtr", 29, 29, &umr_bitfield_default },
+	 { "eopg_p0_q", 30, 30, &umr_bitfield_default },
+	 { "p0_nobp", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG2[] = {
+	 { "param_cache_base", 0, 6, &umr_bitfield_default },
+	 { "sx_aux", 7, 8, &umr_bitfield_default },
+	 { "sx_request_indx", 9, 14, &umr_bitfield_default },
+	 { "req_active_verts_loaded", 15, 15, &umr_bitfield_default },
+	 { "req_active_verts", 16, 22, &umr_bitfield_default },
+	 { "vgt_to_ccgen_state_var_indx", 23, 25, &umr_bitfield_default },
+	 { "vgt_to_ccgen_active_verts", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_LDS_ALLOC[] = {
+	 { "LDS_BASE", 0, 7, &umr_bitfield_default },
+	 { "LDS_SIZE", 12, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG22[] = {
+	 { "cm_state16", 0, 1, &umr_bitfield_default },
+	 { "cm_state17", 2, 3, &umr_bitfield_default },
+	 { "cm_state18", 4, 5, &umr_bitfield_default },
+	 { "cm_state19", 6, 7, &umr_bitfield_default },
+	 { "cm_state20", 8, 9, &umr_bitfield_default },
+	 { "cm_state21", 10, 11, &umr_bitfield_default },
+	 { "cm_state22", 12, 13, &umr_bitfield_default },
+	 { "cm_state23", 14, 15, &umr_bitfield_default },
+	 { "cm_state24", 16, 17, &umr_bitfield_default },
+	 { "cm_state25", 18, 19, &umr_bitfield_default },
+	 { "cm_state26", 20, 21, &umr_bitfield_default },
+	 { "cm_state27", 22, 23, &umr_bitfield_default },
+	 { "cm_state28", 24, 25, &umr_bitfield_default },
+	 { "cm_state29", 26, 27, &umr_bitfield_default },
+	 { "cm_state30", 28, 29, &umr_bitfield_default },
+	 { "cm_state31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSXIFCCG_DEBUG_REG3[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "vertex_fifo_entriesavailable", 8, 11, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_ccdist1_vec_ena", 12, 12, &umr_bitfield_default },
+	 { "statevar_bits_vs_out_ccdist0_vec_ena", 13, 13, &umr_bitfield_default },
+	 { "available_positions", 14, 20, &umr_bitfield_default },
+	 { "current_state", 21, 22, &umr_bitfield_default },
+	 { "vertex_fifo_empty", 23, 23, &umr_bitfield_default },
+	 { "vertex_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "sx0_receive_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "sx0_receive_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "vgt_to_ccgen_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "vgt_to_ccgen_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "sx0_receive_fifo_write", 30, 30, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG23[] = {
+	 { "frmt_busy", 0, 0, &umr_bitfield_default },
+	 { "rcm_frmt_vert_rtr", 1, 1, &umr_bitfield_default },
+	 { "rcm_frmt_prim_rtr", 2, 2, &umr_bitfield_default },
+	 { "prim_r3_rtr", 3, 3, &umr_bitfield_default },
+	 { "prim_r2_rtr", 4, 4, &umr_bitfield_default },
+	 { "vert_r3_rtr", 5, 5, &umr_bitfield_default },
+	 { "vert_r2_rtr", 6, 6, &umr_bitfield_default },
+	 { "vert_r1_rtr", 7, 7, &umr_bitfield_default },
+	 { "vert_r0_rtr", 8, 8, &umr_bitfield_default },
+	 { "prim_fifo_empty", 9, 9, &umr_bitfield_default },
+	 { "prim_fifo_full", 10, 10, &umr_bitfield_default },
+	 { "vert_dr_r2_q", 11, 11, &umr_bitfield_default },
+	 { "prim_dr_r2_q", 12, 12, &umr_bitfield_default },
+	 { "vert_dr_r1_q", 13, 13, &umr_bitfield_default },
+	 { "vert_dr_r0_q", 14, 14, &umr_bitfield_default },
+	 { "new_verts_r2_q", 15, 16, &umr_bitfield_default },
+	 { "verts_sent_r2_q", 17, 20, &umr_bitfield_default },
+	 { "prim_state_sel_r2_q", 21, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_STS[] = {
+	 { "VM_CNT", 0, 3, &umr_bitfield_default },
+	 { "EXP_CNT", 4, 6, &umr_bitfield_default },
+	 { "LGKM_CNT", 8, 11, &umr_bitfield_default },
+	 { "VALU_CNT", 12, 14, &umr_bitfield_default },
+	 { "FIRST_REPLAY", 15, 15, &umr_bitfield_default },
+	 { "RCNT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG0[] = {
+	 { "su_baryc_cntl_state", 0, 1, &umr_bitfield_default },
+	 { "su_cntl_state", 2, 5, &umr_bitfield_default },
+	 { "pmode_state", 8, 13, &umr_bitfield_default },
+	 { "ge_stallb", 14, 14, &umr_bitfield_default },
+	 { "geom_enable", 15, 15, &umr_bitfield_default },
+	 { "su_clip_baryc_free", 16, 17, &umr_bitfield_default },
+	 { "su_clip_rtr", 18, 18, &umr_bitfield_default },
+	 { "pfifo_busy", 19, 19, &umr_bitfield_default },
+	 { "su_cntl_busy", 20, 20, &umr_bitfield_default },
+	 { "geom_busy", 21, 21, &umr_bitfield_default },
+	 { "event_id_gated", 22, 27, &umr_bitfield_default },
+	 { "event_gated", 28, 28, &umr_bitfield_default },
+	 { "pmode_prim_gated", 29, 29, &umr_bitfield_default },
+	 { "su_dyn_sclk_vld", 30, 30, &umr_bitfield_default },
+	 { "cl_dyn_sclk_vld", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG24[] = {
+	 { "avail_es_rb_space_r0_q_23_0", 0, 23, &umr_bitfield_default },
+	 { "dependent_st_cut_mode_q", 24, 25, &umr_bitfield_default },
+	 { "SPARE31", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_PC_LO[] = {
+	 { "PC_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG1[] = {
+	 { "y_sort0_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort0_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG25[] = {
+	 { "avail_gs_rb_space_r0_q_25_0", 0, 25, &umr_bitfield_default },
+	 { "active_sm_r0_q", 26, 29, &umr_bitfield_default },
+	 { "add_gs_rb_space_r1_q", 30, 30, &umr_bitfield_default },
+	 { "add_gs_rb_space_r0_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_PC_HI[] = {
+	 { "PC_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG2[] = {
+	 { "y_sort1_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort1_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG3[] = {
+	 { "y_sort2_gated_23_8", 0, 15, &umr_bitfield_default },
+	 { "x_sort2_gated_23_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG27[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "gsc0_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "tm_pt_event_rtr", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "gsc0_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipe1_rtr", 6, 6, &umr_bitfield_default },
+	 { "last_indx_of_prim_p1_q", 7, 7, &umr_bitfield_default },
+	 { "indices_to_send_p0_q", 8, 9, &umr_bitfield_default },
+	 { "event_flag_p1_q", 10, 10, &umr_bitfield_default },
+	 { "eop_p1_q", 11, 11, &umr_bitfield_default },
+	 { "gs_out_prim_type_p0_q", 12, 13, &umr_bitfield_default },
+	 { "gsc_null_primitive_p0_q", 14, 14, &umr_bitfield_default },
+	 { "gsc_eop_p0_q", 15, 15, &umr_bitfield_default },
+	 { "gsc_2cycle_output", 16, 16, &umr_bitfield_default },
+	 { "gsc_2nd_cycle_p0_q", 17, 17, &umr_bitfield_default },
+	 { "last_indx_of_vsprim", 18, 18, &umr_bitfield_default },
+	 { "first_vsprim_of_gsprim_p0_q", 19, 19, &umr_bitfield_default },
+	 { "gsc_indx_count_p0_q", 20, 30, &umr_bitfield_default },
+	 { "last_vsprim_of_gsprim", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG4[] = {
+	 { "attr_indx_sort0_gated", 0, 13, &umr_bitfield_default },
+	 { "null_prim_gated", 14, 14, &umr_bitfield_default },
+	 { "backfacing_gated", 15, 15, &umr_bitfield_default },
+	 { "st_indx_gated", 16, 18, &umr_bitfield_default },
+	 { "clipped_gated", 19, 19, &umr_bitfield_default },
+	 { "dealloc_slot_gated", 20, 22, &umr_bitfield_default },
+	 { "xmajor_gated", 23, 23, &umr_bitfield_default },
+	 { "diamond_rule_gated", 24, 25, &umr_bitfield_default },
+	 { "type_gated", 26, 28, &umr_bitfield_default },
+	 { "fpov_gated", 29, 30, &umr_bitfield_default },
+	 { "eop_gated", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_DBG0[] = {
+	 { "IBUF_ST", 0, 2, &umr_bitfield_default },
+	 { "PC_INVALID", 3, 3, &umr_bitfield_default },
+	 { "NEED_NEXT_DW", 4, 4, &umr_bitfield_default },
+	 { "NO_PREFETCH_CNT", 5, 7, &umr_bitfield_default },
+	 { "IBUF_RPTR", 8, 9, &umr_bitfield_default },
+	 { "IBUF_WPTR", 10, 11, &umr_bitfield_default },
+	 { "INST_STR_ST", 16, 19, &umr_bitfield_default },
+	 { "MISC_CNT", 20, 23, &umr_bitfield_default },
+	 { "ECC_ST", 24, 25, &umr_bitfield_default },
+	 { "IS_HYB", 26, 26, &umr_bitfield_default },
+	 { "HYB_CNT", 27, 28, &umr_bitfield_default },
+	 { "KILL", 29, 29, &umr_bitfield_default },
+	 { "NEED_KILL_IFETCH", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSETUP_DEBUG_REG5[] = {
+	 { "attr_indx_sort2_gated", 0, 13, &umr_bitfield_default },
+	 { "attr_indx_sort1_gated", 14, 27, &umr_bitfield_default },
+	 { "provoking_vtx_gated", 28, 29, &umr_bitfield_default },
+	 { "valid_prim_gated", 30, 30, &umr_bitfield_default },
+	 { "pa_reg_sclk_vld", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_IB_DBG1[] = {
+	 { "IXNACK", 0, 0, &umr_bitfield_default },
+	 { "XNACK", 1, 1, &umr_bitfield_default },
+	 { "TA_NEED_RESET", 2, 2, &umr_bitfield_default },
+	 { "XCNT", 4, 7, &umr_bitfield_default },
+	 { "QCNT", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_THREAD_TRACE_TG0[] = {
+	 { "TGID_X", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG2[] = {
+	 { "hs_grp_busy", 0, 0, &umr_bitfield_default },
+	 { "hs_noif_busy", 1, 1, &umr_bitfield_default },
+	 { "tfmmIsBusy", 2, 2, &umr_bitfield_default },
+	 { "lsVertIfBusy_0", 3, 3, &umr_bitfield_default },
+	 { "te11_hs_tess_input_rtr", 4, 4, &umr_bitfield_default },
+	 { "lsWaveIfBusy_0", 5, 5, &umr_bitfield_default },
+	 { "hs_te11_tess_input_rts", 6, 6, &umr_bitfield_default },
+	 { "grpModBusy", 7, 7, &umr_bitfield_default },
+	 { "lsVertFifoEmpty", 8, 8, &umr_bitfield_default },
+	 { "lsWaveFifoEmpty", 9, 9, &umr_bitfield_default },
+	 { "hsVertFifoEmpty", 10, 10, &umr_bitfield_default },
+	 { "hsWaveFifoEmpty", 11, 11, &umr_bitfield_default },
+	 { "hsInputFifoEmpty", 12, 12, &umr_bitfield_default },
+	 { "hsTifFifoEmpty", 13, 13, &umr_bitfield_default },
+	 { "lsVertFifoFull", 14, 14, &umr_bitfield_default },
+	 { "lsWaveFifoFull", 15, 15, &umr_bitfield_default },
+	 { "hsVertFifoFull", 16, 16, &umr_bitfield_default },
+	 { "hsWaveFifoFull", 17, 17, &umr_bitfield_default },
+	 { "hsInputFifoFull", 18, 18, &umr_bitfield_default },
+	 { "hsTifFifoFull", 19, 19, &umr_bitfield_default },
+	 { "p0_rtr", 20, 20, &umr_bitfield_default },
+	 { "p1_rtr", 21, 21, &umr_bitfield_default },
+	 { "p0_dr", 22, 22, &umr_bitfield_default },
+	 { "p1_dr", 23, 23, &umr_bitfield_default },
+	 { "p0_rts", 24, 24, &umr_bitfield_default },
+	 { "p1_rts", 25, 25, &umr_bitfield_default },
+	 { "ls_sh_id", 26, 26, &umr_bitfield_default },
+	 { "lsFwaveFlag", 27, 27, &umr_bitfield_default },
+	 { "lsWaveSendFlush", 28, 28, &umr_bitfield_default },
+	 { "SPARE", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCSPRIV_THREAD_TRACE_EVENT[] = {
+	 { "EVENT_ID", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG3[] = {
+	 { "lsTgRelInd", 0, 11, &umr_bitfield_default },
+	 { "lsWaveRelInd", 12, 17, &umr_bitfield_default },
+	 { "lsPatchCnt", 18, 25, &umr_bitfield_default },
+	 { "hsWaveRelInd", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG02[] = {
+	 { "clip_extra_bc_valid", 0, 2, &umr_bitfield_default },
+	 { "clip_vert_vte_valid", 3, 5, &umr_bitfield_default },
+	 { "clip_to_outsm_clip_seq_indx", 6, 7, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_2", 8, 11, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_1", 12, 15, &umr_bitfield_default },
+	 { "clip_to_outsm_vertex_store_indx_0", 16, 19, &umr_bitfield_default },
+	 { "clip_to_clipga_extra_bc_coords", 20, 20, &umr_bitfield_default },
+	 { "clip_to_clipga_vte_naninf_kill", 21, 21, &umr_bitfield_default },
+	 { "clip_to_outsm_end_of_packet", 22, 22, &umr_bitfield_default },
+	 { "clip_to_outsm_first_prim_of_slot", 23, 23, &umr_bitfield_default },
+	 { "clip_to_outsm_clipped_prim", 24, 24, &umr_bitfield_default },
+	 { "clip_to_outsm_null_primitive", 25, 25, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "clip_ga_bc_fifo_write", 28, 28, &umr_bitfield_default },
+	 { "clip_to_ga_fifo_write", 29, 29, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "clip_to_outsm_fifo_empty", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG2[] = {
+	 { "ds_full", 0, 0, &umr_bitfield_default },
+	 { "ds_credit_avail", 1, 1, &umr_bitfield_default },
+	 { "ord_idx_free", 2, 2, &umr_bitfield_default },
+	 { "cmd_write", 3, 3, &umr_bitfield_default },
+	 { "app_sel", 4, 7, &umr_bitfield_default },
+	 { "req", 8, 22, &umr_bitfield_default },
+	 { "spare", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG2[] = {
+	 { "p1_grbm_fifo_empty", 0, 0, &umr_bitfield_default },
+	 { "p1_grbm_fifo_full", 1, 1, &umr_bitfield_default },
+	 { "p1_grbm_fifo_we", 2, 2, &umr_bitfield_default },
+	 { "p1_grbm_fifo_re", 3, 3, &umr_bitfield_default },
+	 { "p1_draw_initiator_valid_q", 4, 4, &umr_bitfield_default },
+	 { "p1_event_initiator_valid_q", 5, 5, &umr_bitfield_default },
+	 { "p1_event_addr_valid_q", 6, 6, &umr_bitfield_default },
+	 { "p1_dma_request_valid_q", 7, 7, &umr_bitfield_default },
+	 { "SPARE0", 8, 8, &umr_bitfield_default },
+	 { "p1_min_indx_valid_q", 9, 9, &umr_bitfield_default },
+	 { "p1_max_indx_valid_q", 10, 10, &umr_bitfield_default },
+	 { "p1_indx_offset_valid_q", 11, 11, &umr_bitfield_default },
+	 { "p1_grbm_fifo_rdata_reg_id", 12, 16, &umr_bitfield_default },
+	 { "p1_grbm_fifo_rdata_state", 17, 19, &umr_bitfield_default },
+	 { "p1_free_cnt_q", 20, 25, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_we", 26, 26, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_we", 27, 27, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "p1_rbiu_di_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "p1_rbiu_dr_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG4[] = {
+	 { "hsPatchCnt", 0, 7, &umr_bitfield_default },
+	 { "hsPrimId_15_0", 8, 23, &umr_bitfield_default },
+	 { "hsCpCnt", 24, 28, &umr_bitfield_default },
+	 { "hsWaveSendFlush", 29, 29, &umr_bitfield_default },
+	 { "hsFwaveFlag", 30, 30, &umr_bitfield_default },
+	 { "SPARE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "UNUSED_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CNTL[] = {
+	 { "READ_TIMEOUT", 0, 7, &umr_bitfield_default },
+	 { "REPORT_LAST_RDERR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SKEW_CNTL[] = {
+	 { "SKEW_TOP_THRESHOLD", 0, 5, &umr_bitfield_default },
+	 { "SKEW_COUNT", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS2[] = {
+	 { "ME0PIPE1_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "ME0PIPE1_CF_RQ_PENDING", 4, 4, &umr_bitfield_default },
+	 { "ME0PIPE1_PF_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME1PIPE0_RQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "ME1PIPE1_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME1PIPE2_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "ME1PIPE3_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "ME2PIPE0_RQ_PENDING", 10, 10, &umr_bitfield_default },
+	 { "ME2PIPE1_RQ_PENDING", 11, 11, &umr_bitfield_default },
+	 { "ME2PIPE2_RQ_PENDING", 12, 12, &umr_bitfield_default },
+	 { "ME2PIPE3_RQ_PENDING", 13, 13, &umr_bitfield_default },
+	 { "RLC_RQ_PENDING", 14, 14, &umr_bitfield_default },
+	 { "RLC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TC_BUSY", 25, 25, &umr_bitfield_default },
+	 { "TCC_CC_RESIDENT", 26, 26, &umr_bitfield_default },
+	 { "CPF_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPG_BUSY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PWR_CNTL[] = {
+	 { "ALL_REQ_TYPE", 0, 1, &umr_bitfield_default },
+	 { "GFX_REQ_TYPE", 2, 3, &umr_bitfield_default },
+	 { "ALL_RSP_TYPE", 4, 5, &umr_bitfield_default },
+	 { "GFX_RSP_TYPE", 6, 7, &umr_bitfield_default },
+	 { "GFX_REQ_EN", 14, 14, &umr_bitfield_default },
+	 { "ALL_REQ_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS[] = {
+	 { "ME0PIPE0_CMDFIFO_AVAIL", 0, 3, &umr_bitfield_default },
+	 { "SRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "ME0PIPE0_CF_RQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "ME0PIPE0_PF_RQ_PENDING", 8, 8, &umr_bitfield_default },
+	 { "GDS_DMA_RQ_PENDING", 9, 9, &umr_bitfield_default },
+	 { "DB_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "CB_CLEAN", 13, 13, &umr_bitfield_default },
+	 { "TA_BUSY", 14, 14, &umr_bitfield_default },
+	 { "GDS_BUSY", 15, 15, &umr_bitfield_default },
+	 { "WD_BUSY_NO_DMA", 16, 16, &umr_bitfield_default },
+	 { "VGT_BUSY", 17, 17, &umr_bitfield_default },
+	 { "IA_BUSY_NO_DMA", 18, 18, &umr_bitfield_default },
+	 { "IA_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SX_BUSY", 20, 20, &umr_bitfield_default },
+	 { "WD_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SPI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "BCI_BUSY", 23, 23, &umr_bitfield_default },
+	 { "SC_BUSY", 24, 24, &umr_bitfield_default },
+	 { "PA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "DB_BUSY", 26, 26, &umr_bitfield_default },
+	 { "CP_COHERENCY_BUSY", 28, 28, &umr_bitfield_default },
+	 { "CP_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "GUI_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE0[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE1[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SOFT_RESET[] = {
+	 { "SOFT_RESET_CP", 0, 0, &umr_bitfield_default },
+	 { "SOFT_RESET_RLC", 2, 2, &umr_bitfield_default },
+	 { "SOFT_RESET_GFX", 16, 16, &umr_bitfield_default },
+	 { "SOFT_RESET_CPF", 17, 17, &umr_bitfield_default },
+	 { "SOFT_RESET_CPC", 18, 18, &umr_bitfield_default },
+	 { "SOFT_RESET_CPG", 19, 19, &umr_bitfield_default },
+	 { "SOFT_RESET_CAC", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_CNTL[] = {
+	 { "GRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CGTT_CLK_CNTL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_GFX_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_WAIT_IDLE_CLOCKS[] = {
+	 { "WAIT_IDLE_CLOCKS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE2[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_STATUS_SE3[] = {
+	 { "DB_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "CB_CLEAN", 2, 2, &umr_bitfield_default },
+	 { "BCI_BUSY", 22, 22, &umr_bitfield_default },
+	 { "VGT_BUSY", 23, 23, &umr_bitfield_default },
+	 { "PA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "TA_BUSY", 25, 25, &umr_bitfield_default },
+	 { "SX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "SPI_BUSY", 27, 27, &umr_bitfield_default },
+	 { "SC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "DB_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG[] = {
+	 { "IGNORE_RDY", 1, 1, &umr_bitfield_default },
+	 { "IGNORE_FAO", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_READ_TIMEOUT", 6, 6, &umr_bitfield_default },
+	 { "SNAPSHOT_FREE_CNTRS", 7, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_GUI_ACTIVE", 8, 11, &umr_bitfield_default },
+	 { "GFX_CLOCK_DOMAIN_OVERRIDE", 12, 12, &umr_bitfield_default },
+	 { "GRBM_TRAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_BUS_FGCG_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DEBUG_SNAPSHOT[] = {
+	 { "CPF_RDY", 0, 0, &umr_bitfield_default },
+	 { "CPG_RDY", 1, 1, &umr_bitfield_default },
+	 { "SRBM_RDY", 2, 2, &umr_bitfield_default },
+	 { "WD_ME0PIPE0_RDY", 3, 3, &umr_bitfield_default },
+	 { "WD_ME0PIPE1_RDY", 4, 4, &umr_bitfield_default },
+	 { "GDS_RDY", 5, 5, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY0", 6, 6, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY0", 7, 7, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY0", 8, 8, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY0", 9, 9, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY0", 10, 10, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY0", 11, 11, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY0", 12, 12, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY0", 13, 13, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE0_RDY1", 14, 14, &umr_bitfield_default },
+	 { "SE0SPI_ME0PIPE1_RDY1", 15, 15, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE0_RDY1", 16, 16, &umr_bitfield_default },
+	 { "SE1SPI_ME0PIPE1_RDY1", 17, 17, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE0_RDY1", 18, 18, &umr_bitfield_default },
+	 { "SE2SPI_ME0PIPE1_RDY1", 19, 19, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE0_RDY1", 20, 20, &umr_bitfield_default },
+	 { "SE3SPI_ME0PIPE1_RDY1", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_READ_ERROR[] = {
+	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "READ_PIPEID", 20, 21, &umr_bitfield_default },
+	 { "READ_MEID", 22, 23, &umr_bitfield_default },
+	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_READ_ERROR2[] = {
+	 { "READ_REQUESTER_SRBM", 17, 17, &umr_bitfield_default },
+	 { "READ_REQUESTER_RLC", 18, 18, &umr_bitfield_default },
+	 { "READ_REQUESTER_GDS_DMA", 19, 19, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE0_CF", 20, 20, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE0_PF", 21, 21, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE1_CF", 22, 22, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME0PIPE1_PF", 23, 23, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE0", 24, 24, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE1", 25, 25, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE2", 26, 26, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME1PIPE3", 27, 27, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE0", 28, 28, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE1", 29, 29, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE2", 30, 30, &umr_bitfield_default },
+	 { "READ_REQUESTER_ME2PIPE3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_INT_CNTL[] = {
+	 { "RDERR_INT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GUI_IDLE_INT_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_OP[] = {
+	 { "RW", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_ADDR[] = {
+	 { "DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_ADDR_MSK[] = {
+	 { "DATA", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_WD[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_TRAP_WD_MSK[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_DSM_BYPASS[] = {
+	 { "BYPASS_BITS", 0, 1, &umr_bitfield_default },
+	 { "BYPASS_EN", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_WRITE_ERROR[] = {
+	 { "WRITE_REQUESTER_RLC", 0, 0, &umr_bitfield_default },
+	 { "WRITE_REQUESTER_SRBM", 1, 1, &umr_bitfield_default },
+	 { "WRITE_SSRCID", 2, 4, &umr_bitfield_default },
+	 { "WRITE_VFID", 5, 8, &umr_bitfield_default },
+	 { "WRITE_VF", 12, 12, &umr_bitfield_default },
+	 { "WRITE_VMID", 13, 16, &umr_bitfield_default },
+	 { "WRITE_PIPEID", 20, 21, &umr_bitfield_default },
+	 { "WRITE_MEID", 22, 23, &umr_bitfield_default },
+	 { "WRITE_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEBUG_INDEX[] = {
+	 { "DEBUG_INDEX", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDEBUG_DATA[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_NOWHERE[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_STATUS[] = {
+	 { "MEC1_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MEC2_BUSY", 1, 1, &umr_bitfield_default },
+	 { "DC0_BUSY", 2, 2, &umr_bitfield_default },
+	 { "DC1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "RCIU1_BUSY", 4, 4, &umr_bitfield_default },
+	 { "RCIU2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "ROQ1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "ROQ2_BUSY", 7, 7, &umr_bitfield_default },
+	 { "TCIU_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 11, 11, &umr_bitfield_default },
+	 { "QU_BUSY", 12, 12, &umr_bitfield_default },
+	 { "ATCL2IU_BUSY", 13, 13, &umr_bitfield_default },
+	 { "CPG_CPC_BUSY", 29, 29, &umr_bitfield_default },
+	 { "CPF_CPC_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CPC_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_BUSY_STAT[] = {
+	 { "MEC1_LOAD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MEC1_SEMAPOHRE_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MEC1_MUTEX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "MEC1_MESSAGE_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MEC1_EOP_QUEUE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "MEC1_IQ_QUEUE_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MEC1_IB_QUEUE_BUSY", 6, 6, &umr_bitfield_default },
+	 { "MEC1_TC_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MEC1_DMA_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MEC1_PARTIAL_FLUSH_BUSY", 9, 9, &umr_bitfield_default },
+	 { "MEC1_PIPE0_BUSY", 10, 10, &umr_bitfield_default },
+	 { "MEC1_PIPE1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "MEC1_PIPE2_BUSY", 12, 12, &umr_bitfield_default },
+	 { "MEC1_PIPE3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "MEC2_LOAD_BUSY", 16, 16, &umr_bitfield_default },
+	 { "MEC2_SEMAPOHRE_BUSY", 17, 17, &umr_bitfield_default },
+	 { "MEC2_MUTEX_BUSY", 18, 18, &umr_bitfield_default },
+	 { "MEC2_MESSAGE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "MEC2_EOP_QUEUE_BUSY", 20, 20, &umr_bitfield_default },
+	 { "MEC2_IQ_QUEUE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "MEC2_IB_QUEUE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "MEC2_TC_BUSY", 23, 23, &umr_bitfield_default },
+	 { "MEC2_DMA_BUSY", 24, 24, &umr_bitfield_default },
+	 { "MEC2_PARTIAL_FLUSH_BUSY", 25, 25, &umr_bitfield_default },
+	 { "MEC2_PIPE0_BUSY", 26, 26, &umr_bitfield_default },
+	 { "MEC2_PIPE1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "MEC2_PIPE2_BUSY", 28, 28, &umr_bitfield_default },
+	 { "MEC2_PIPE3_BUSY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_STALLED_STAT1[] = {
+	 { "RCIU_TX_FREE_STALL", 3, 3, &umr_bitfield_default },
+	 { "RCIU_PRIV_VIOLATION", 4, 4, &umr_bitfield_default },
+	 { "TCIU_TX_FREE_STALL", 6, 6, &umr_bitfield_default },
+	 { "MEC1_DECODING_PACKET", 8, 8, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_RCIU", 9, 9, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_RCIU_READ", 10, 10, &umr_bitfield_default },
+	 { "MEC1_WAIT_ON_ROQ_DATA", 13, 13, &umr_bitfield_default },
+	 { "MEC2_DECODING_PACKET", 16, 16, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_RCIU", 17, 17, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_RCIU_READ", 18, 18, &umr_bitfield_default },
+	 { "MEC2_WAIT_ON_ROQ_DATA", 21, 21, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_FREE", 22, 22, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_TAGS", 23, 23, &umr_bitfield_default },
+	 { "ATCL1_WAITING_ON_TRANS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_STATUS[] = {
+	 { "POST_WPTR_GFX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CSF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ROQ_ALIGN_BUSY", 4, 4, &umr_bitfield_default },
+	 { "ROQ_RING_BUSY", 5, 5, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 7, 7, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 8, 8, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 13, 13, &umr_bitfield_default },
+	 { "TCIU_BUSY", 14, 14, &umr_bitfield_default },
+	 { "HQD_BUSY", 15, 15, &umr_bitfield_default },
+	 { "PRT_BUSY", 16, 16, &umr_bitfield_default },
+	 { "ATCL2IU_BUSY", 17, 17, &umr_bitfield_default },
+	 { "CPF_GFX_BUSY", 26, 26, &umr_bitfield_default },
+	 { "CPF_CMP_BUSY", 27, 27, &umr_bitfield_default },
+	 { "GRBM_CPF_STAT_BUSY", 28, 29, &umr_bitfield_default },
+	 { "CPC_CPF_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CPF_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_BUSY_STAT[] = {
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CSF_RING_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CSF_INDIRECT1_BUSY", 2, 2, &umr_bitfield_default },
+	 { "CSF_INDIRECT2_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CSF_STATE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CSF_CE_INDR1_BUSY", 5, 5, &umr_bitfield_default },
+	 { "CSF_CE_INDR2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CSF_ARBITER_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CSF_INPUT_BUSY", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_READ_TAGS", 9, 9, &umr_bitfield_default },
+	 { "HPD_PROCESSING_EOP_BUSY", 11, 11, &umr_bitfield_default },
+	 { "HQD_DISPATCH_BUSY", 12, 12, &umr_bitfield_default },
+	 { "HQD_IQ_TIMER_BUSY", 13, 13, &umr_bitfield_default },
+	 { "HQD_DMA_OFFLOAD_BUSY", 14, 14, &umr_bitfield_default },
+	 { "HQD_WAIT_SEMAPHORE_BUSY", 15, 15, &umr_bitfield_default },
+	 { "HQD_SIGNAL_SEMAPHORE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "HQD_MESSAGE_BUSY", 17, 17, &umr_bitfield_default },
+	 { "HQD_PQ_FETCHER_BUSY", 18, 18, &umr_bitfield_default },
+	 { "HQD_IB_FETCHER_BUSY", 19, 19, &umr_bitfield_default },
+	 { "HQD_IQ_FETCHER_BUSY", 20, 20, &umr_bitfield_default },
+	 { "HQD_EOP_FETCHER_BUSY", 21, 21, &umr_bitfield_default },
+	 { "HQD_CONSUMED_RPTR_BUSY", 22, 22, &umr_bitfield_default },
+	 { "HQD_FETCHER_ARB_BUSY", 23, 23, &umr_bitfield_default },
+	 { "HQD_ROQ_ALIGN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "HQD_ROQ_EOP_BUSY", 25, 25, &umr_bitfield_default },
+	 { "HQD_ROQ_IQ_BUSY", 26, 26, &umr_bitfield_default },
+	 { "HQD_ROQ_PQ_BUSY", 27, 27, &umr_bitfield_default },
+	 { "HQD_ROQ_IB_BUSY", 28, 28, &umr_bitfield_default },
+	 { "HQD_WPTR_POLL_BUSY", 29, 29, &umr_bitfield_default },
+	 { "HQD_PQ_BUSY", 30, 30, &umr_bitfield_default },
+	 { "HQD_IB_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPF_STALLED_STAT1[] = {
+	 { "RING_FETCHING_DATA", 0, 0, &umr_bitfield_default },
+	 { "INDR1_FETCHING_DATA", 1, 1, &umr_bitfield_default },
+	 { "INDR2_FETCHING_DATA", 2, 2, &umr_bitfield_default },
+	 { "STATE_FETCHING_DATA", 3, 3, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 5, 5, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 6, 6, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_FREE", 7, 7, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_TAGS", 8, 8, &umr_bitfield_default },
+	 { "ATCL1_WAITING_ON_TRANS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_CNTL[] = {
+	 { "MEC_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "MEC_ME1_PIPE0_RESET", 16, 16, &umr_bitfield_default },
+	 { "MEC_ME1_PIPE1_RESET", 17, 17, &umr_bitfield_default },
+	 { "MEC_ME1_PIPE2_RESET", 18, 18, &umr_bitfield_default },
+	 { "MEC_ME1_PIPE3_RESET", 19, 19, &umr_bitfield_default },
+	 { "MEC_ME2_PIPE0_RESET", 20, 20, &umr_bitfield_default },
+	 { "MEC_ME2_PIPE1_RESET", 21, 21, &umr_bitfield_default },
+	 { "MEC_ME2_HALT", 28, 28, &umr_bitfield_default },
+	 { "MEC_ME2_STEP", 29, 29, &umr_bitfield_default },
+	 { "MEC_ME1_HALT", 30, 30, &umr_bitfield_default },
+	 { "MEC_ME1_STEP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_HEADER_DUMP[] = {
+	 { "HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_HEADER_DUMP[] = {
+	 { "HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_HALT_HYST_COUNT[] = {
+	 { "COUNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL0[] = {
+	 { "BU_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL1[] = {
+	 { "BASE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRT_LOD_STATS_CNTL2[] = {
+	 { "BASE_HI", 0, 1, &umr_bitfield_default },
+	 { "INTERVAL", 2, 9, &umr_bitfield_default },
+	 { "RESET_CNT", 10, 17, &umr_bitfield_default },
+	 { "RESET_FORCE", 18, 18, &umr_bitfield_default },
+	 { "REPORT_AND_RESET", 19, 19, &umr_bitfield_default },
+	 { "MC_VMID", 23, 26, &umr_bitfield_default },
+	 { "CACHE_POLICY", 28, 28, &umr_bitfield_default },
+	 { "MTYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_INTERRUPT_WORD_AUTO[] = {
+	 { "THREAD_TRACE", 0, 0, &umr_bitfield_default },
+	 { "WLT", 1, 1, &umr_bitfield_default },
+	 { "THREAD_TRACE_BUF_FULL", 2, 2, &umr_bitfield_default },
+	 { "REG_TIMESTAMP", 3, 3, &umr_bitfield_default },
+	 { "CMD_TIMESTAMP", 4, 4, &umr_bitfield_default },
+	 { "HOST_CMD_OVERFLOW", 5, 5, &umr_bitfield_default },
+	 { "HOST_REG_OVERFLOW", 6, 6, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 7, 7, &umr_bitfield_default },
+	 { "SE_ID", 24, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_INTERRUPT_WORD_CMN[] = {
+	 { "SE_ID", 24, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_COMPARE_COUNT[] = {
+	 { "COMPARE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_DE_COUNT[] = {
+	 { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_CE_COUNT[] = {
+	 { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_LAST_INVAL_COUNT[] = {
+	 { "LAST_INVAL_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DE_DE_COUNT[] = {
+	 { "DRAW_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG5[] = {
+	 { "SPARE4", 0, 2, &umr_bitfield_default },
+	 { "hsWaveCreditCnt_0", 3, 7, &umr_bitfield_default },
+	 { "SPARE3", 8, 10, &umr_bitfield_default },
+	 { "hsVertCreditCnt_0", 11, 15, &umr_bitfield_default },
+	 { "SPARE2", 16, 18, &umr_bitfield_default },
+	 { "lsWaveCreditCnt_0", 19, 23, &umr_bitfield_default },
+	 { "SPARE1", 24, 26, &umr_bitfield_default },
+	 { "lsVertCreditCnt_0", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT3[] = {
+	 { "CE_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER", 2, 2, &umr_bitfield_default },
+	 { "CE_TO_RAM_INIT_NOT_RDY", 3, 3, &umr_bitfield_default },
+	 { "CE_TO_RAM_DUMP_NOT_RDY", 4, 4, &umr_bitfield_default },
+	 { "CE_TO_RAM_WRITE_NOT_RDY", 5, 5, &umr_bitfield_default },
+	 { "CE_TO_INC_FIFO_NOT_RDY_TO_RCV", 6, 6, &umr_bitfield_default },
+	 { "CE_TO_WR_FIFO_NOT_RDY_TO_RCV", 7, 7, &umr_bitfield_default },
+	 { "CE_WAITING_ON_BUFFER_DATA", 10, 10, &umr_bitfield_default },
+	 { "CE_WAITING_ON_CE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER", 12, 12, &umr_bitfield_default },
+	 { "CE_WAITING_ON_DE_COUNTER_UNDERFLOW", 13, 13, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_FREE", 14, 14, &umr_bitfield_default },
+	 { "TCIU_WAITING_ON_TAGS", 15, 15, &umr_bitfield_default },
+	 { "CE_STALLED_ON_TC_WR_CONFIRM", 16, 16, &umr_bitfield_default },
+	 { "CE_STALLED_ON_ATOMIC_RTN_DATA", 17, 17, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_FREE", 18, 18, &umr_bitfield_default },
+	 { "ATCL2IU_WAITING_ON_TAGS", 19, 19, &umr_bitfield_default },
+	 { "ATCL1_WAITING_ON_TRANS", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT1[] = {
+	 { "RBIU_TO_DMA_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "RBIU_TO_SEM_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "RBIU_TO_MEMWR_NOT_RDY_TO_RCV", 4, 4, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_CE_BUFFER_FLAG", 10, 10, &umr_bitfield_default },
+	 { "ME_HAS_ACTIVE_DE_BUFFER_FLAG", 11, 11, &umr_bitfield_default },
+	 { "ME_STALLED_ON_TC_WR_CONFIRM", 12, 12, &umr_bitfield_default },
+	 { "ME_STALLED_ON_ATOMIC_RTN_DATA", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_ON_TC_READ_DATA", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_REG_READ_DATA", 15, 15, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GDS_FREE", 23, 23, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_GRBM_FREE", 24, 24, &umr_bitfield_default },
+	 { "RCIU_WAITING_ON_VGT_FREE", 25, 25, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_ME_READ", 26, 26, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_DMA_READ", 27, 27, &umr_bitfield_default },
+	 { "RCIU_STALLED_ON_APPEND_READ", 28, 28, &umr_bitfield_default },
+	 { "RCIU_HALTED_BY_REG_VIOLATION", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STALLED_STAT2[] = {
+	 { "PFP_TO_CSF_NOT_RDY_TO_RCV", 0, 0, &umr_bitfield_default },
+	 { "PFP_TO_MEQ_NOT_RDY_TO_RCV", 1, 1, &umr_bitfield_default },
+	 { "PFP_TO_RCIU_NOT_RDY_TO_RCV", 2, 2, &umr_bitfield_default },
+	 { "PFP_TO_VGT_WRITES_PENDING", 4, 4, &umr_bitfield_default },
+	 { "PFP_RCIU_READ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "PFP_WAITING_ON_BUFFER_DATA", 8, 8, &umr_bitfield_default },
+	 { "ME_WAIT_ON_CE_COUNTER", 9, 9, &umr_bitfield_default },
+	 { "ME_WAIT_ON_AVAIL_BUFFER", 10, 10, &umr_bitfield_default },
+	 { "GFX_CNTX_NOT_AVAIL_TO_ME", 11, 11, &umr_bitfield_default },
+	 { "ME_RCIU_NOT_RDY_TO_RCV", 12, 12, &umr_bitfield_default },
+	 { "ME_TO_CONST_NOT_RDY_TO_RCV", 13, 13, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_PFP", 14, 14, &umr_bitfield_default },
+	 { "ME_WAITING_ON_PARTIAL_FLUSH", 15, 15, &umr_bitfield_default },
+	 { "MEQ_TO_ME_NOT_RDY_TO_RCV", 16, 16, &umr_bitfield_default },
+	 { "STQ_TO_ME_NOT_RDY_TO_RCV", 17, 17, &umr_bitfield_default },
+	 { "ME_WAITING_DATA_FROM_STQ", 18, 18, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_TC_WR_CONFIRM", 19, 19, &umr_bitfield_default },
+	 { "PFP_STALLED_ON_ATOMIC_RTN_DATA", 20, 20, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_SC_EOP_DONE", 21, 21, &umr_bitfield_default },
+	 { "EOPD_FIFO_NEEDS_WR_CONFIRM", 22, 22, &umr_bitfield_default },
+	 { "STRMO_WR_OF_PRIM_DATA_PENDING", 23, 23, &umr_bitfield_default },
+	 { "PIPE_STATS_WR_DATA_PENDING", 24, 24, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_CS_DONE", 25, 25, &umr_bitfield_default },
+	 { "APPEND_RDY_WAIT_ON_PS_DONE", 26, 26, &umr_bitfield_default },
+	 { "APPEND_WAIT_ON_WR_CONFIRM", 27, 27, &umr_bitfield_default },
+	 { "APPEND_ACTIVE_PARTITION", 28, 28, &umr_bitfield_default },
+	 { "APPEND_WAITING_TO_SEND_MEMWRITE", 29, 29, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_IDLE_CNTXS", 30, 30, &umr_bitfield_default },
+	 { "SURF_SYNC_NEEDS_ALL_CLEAN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_BUSY_STAT[] = {
+	 { "REG_BUS_FIFO_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COHER_CNT_NEQ_ZERO", 6, 6, &umr_bitfield_default },
+	 { "PFP_PARSING_PACKETS", 7, 7, &umr_bitfield_default },
+	 { "ME_PARSING_PACKETS", 8, 8, &umr_bitfield_default },
+	 { "RCIU_PFP_BUSY", 9, 9, &umr_bitfield_default },
+	 { "RCIU_ME_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SEM_CMDFIFO_NOT_EMPTY", 12, 12, &umr_bitfield_default },
+	 { "SEM_FAILED_AND_HOLDING", 13, 13, &umr_bitfield_default },
+	 { "SEM_POLLING_FOR_PASS", 14, 14, &umr_bitfield_default },
+	 { "GFX_CONTEXT_BUSY", 15, 15, &umr_bitfield_default },
+	 { "ME_PARSER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "EOP_DONE_BUSY", 18, 18, &umr_bitfield_default },
+	 { "STRM_OUT_BUSY", 19, 19, &umr_bitfield_default },
+	 { "PIPE_STATS_BUSY", 20, 20, &umr_bitfield_default },
+	 { "RCIU_CE_BUSY", 21, 21, &umr_bitfield_default },
+	 { "CE_PARSING_PACKETS", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STAT[] = {
+	 { "ROQ_RING_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ROQ_INDIRECT1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "ROQ_INDIRECT2_BUSY", 11, 11, &umr_bitfield_default },
+	 { "ROQ_STATE_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DC_BUSY", 13, 13, &umr_bitfield_default },
+	 { "ATCL2IU_BUSY", 14, 14, &umr_bitfield_default },
+	 { "PFP_BUSY", 15, 15, &umr_bitfield_default },
+	 { "MEQ_BUSY", 16, 16, &umr_bitfield_default },
+	 { "ME_BUSY", 17, 17, &umr_bitfield_default },
+	 { "QUERY_BUSY", 18, 18, &umr_bitfield_default },
+	 { "SEMAPHORE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "INTERRUPT_BUSY", 20, 20, &umr_bitfield_default },
+	 { "SURFACE_SYNC_BUSY", 21, 21, &umr_bitfield_default },
+	 { "DMA_BUSY", 22, 22, &umr_bitfield_default },
+	 { "RCIU_BUSY", 23, 23, &umr_bitfield_default },
+	 { "SCRATCH_RAM_BUSY", 24, 24, &umr_bitfield_default },
+	 { "CPC_CPG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "CE_BUSY", 26, 26, &umr_bitfield_default },
+	 { "TCIU_BUSY", 27, 27, &umr_bitfield_default },
+	 { "ROQ_CE_RING_BUSY", 28, 28, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT1_BUSY", 29, 29, &umr_bitfield_default },
+	 { "ROQ_CE_INDIRECT2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "CP_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_HEADER_DUMP[] = {
+	 { "ME_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_HEADER_DUMP[] = {
+	 { "PFP_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GRBM_FREE_COUNT[] = {
+	 { "FREE_COUNT", 0, 5, &umr_bitfield_default },
+	 { "FREE_COUNT_GDS", 8, 13, &umr_bitfield_default },
+	 { "FREE_COUNT_PFP", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_HEADER_DUMP[] = {
+	 { "CE_HEADER_DUMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CSF_STAT[] = {
+	 { "BUFFER_SLOTS_ALLOCATED", 0, 3, &umr_bitfield_default },
+	 { "BUFFER_REQUEST_COUNT", 8, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CSF_CNTL[] = {
+	 { "FETCH_BUFFER_DEPTH", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_CNTL[] = {
+	 { "CE_INVALIDATE_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "PFP_INVALIDATE_ICACHE", 6, 6, &umr_bitfield_default },
+	 { "ME_INVALIDATE_ICACHE", 8, 8, &umr_bitfield_default },
+	 { "CE_PIPE0_RESET", 16, 16, &umr_bitfield_default },
+	 { "PFP_PIPE0_RESET", 18, 18, &umr_bitfield_default },
+	 { "ME_PIPE0_RESET", 20, 20, &umr_bitfield_default },
+	 { "CE_HALT", 24, 24, &umr_bitfield_default },
+	 { "CE_STEP", 25, 25, &umr_bitfield_default },
+	 { "PFP_HALT", 26, 26, &umr_bitfield_default },
+	 { "PFP_STEP", 27, 27, &umr_bitfield_default },
+	 { "ME_HALT", 28, 28, &umr_bitfield_default },
+	 { "ME_STEP", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CNTX_STAT[] = {
+	 { "ACTIVE_HP3D_CONTEXTS", 0, 7, &umr_bitfield_default },
+	 { "CURRENT_HP3D_CONTEXT", 8, 10, &umr_bitfield_default },
+	 { "ACTIVE_GFX_CONTEXTS", 20, 27, &umr_bitfield_default },
+	 { "CURRENT_GFX_CONTEXT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_PREEMPTION[] = {
+	 { "OBSOLETE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_THRESHOLDS[] = {
+	 { "IB1_START", 0, 7, &umr_bitfield_default },
+	 { "IB2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_STQ_THRESHOLD[] = {
+	 { "STQ_START", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR[] = {
+	 { "RB_RPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_DELAY[] = {
+	 { "PRE_WRITE_TIMER", 0, 27, &umr_bitfield_default },
+	 { "PRE_WRITE_LIMIT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_CNTL[] = {
+	 { "POLL_FREQUENCY", 0, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ1_THRESHOLDS[] = {
+	 { "RB1_START", 0, 7, &umr_bitfield_default },
+	 { "RB2_START", 8, 15, &umr_bitfield_default },
+	 { "R0_IB1_START", 16, 23, &umr_bitfield_default },
+	 { "R1_IB1_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ2_THRESHOLDS[] = {
+	 { "R2_IB1_START", 0, 7, &umr_bitfield_default },
+	 { "R0_IB2_START", 8, 15, &umr_bitfield_default },
+	 { "R1_IB2_START", 16, 23, &umr_bitfield_default },
+	 { "R2_IB2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_THRESHOLDS[] = {
+	 { "STQ0_START", 0, 7, &umr_bitfield_default },
+	 { "STQ1_START", 8, 15, &umr_bitfield_default },
+	 { "STQ2_START", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_QUEUE_THRESHOLDS[] = {
+	 { "ROQ_IB1_START", 0, 5, &umr_bitfield_default },
+	 { "ROQ_IB2_START", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_THRESHOLDS[] = {
+	 { "MEQ1_START", 0, 7, &umr_bitfield_default },
+	 { "MEQ2_START", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_AVAIL[] = {
+	 { "ROQ_CNT_RING", 0, 10, &umr_bitfield_default },
+	 { "ROQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_AVAIL[] = {
+	 { "STQ_CNT", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ2_AVAIL[] = {
+	 { "ROQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_AVAIL[] = {
+	 { "MEQ_CNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CMD_INDEX[] = {
+	 { "CMD_INDEX", 0, 10, &umr_bitfield_default },
+	 { "CMD_ME_SEL", 12, 13, &umr_bitfield_default },
+	 { "CMD_QUEUE_SEL", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CMD_DATA[] = {
+	 { "CMD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_RB_STAT[] = {
+	 { "ROQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_IB1_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ROQ_IB2_STAT[] = {
+	 { "ROQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "ROQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_STAT[] = {
+	 { "STQ_RPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STQ_WR_STAT[] = {
+	 { "STQ_WPTR", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEQ_STAT[] = {
+	 { "MEQ_RPTR", 0, 9, &umr_bitfield_default },
+	 { "MEQ_WPTR", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CEQ1_AVAIL[] = {
+	 { "CEQ_CNT_RING", 0, 10, &umr_bitfield_default },
+	 { "CEQ_CNT_IB1", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CEQ2_AVAIL[] = {
+	 { "CEQ_CNT_IB2", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_RB_STAT[] = {
+	 { "CEQ_RPTR_PRIMARY", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_PRIMARY", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_IB1_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT1", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT1", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_ROQ_IB2_STAT[] = {
+	 { "CEQ_RPTR_INDIRECT2", 0, 9, &umr_bitfield_default },
+	 { "CEQ_WPTR_INDIRECT2", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STAT_DEBUG[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ASSERTED", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ASSERTED", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ASSERTED", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ASSERTED", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ASSERTED", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ASSERTED", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG6[] = {
+	 { "debug_BASE", 0, 15, &umr_bitfield_default },
+	 { "debug_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "UNUSED_0", 14, 15, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "UNUSED_1", 26, 26, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "UNUSED_2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VTX_VECT_EJECT_REG[] = {
+	 { "PRIM_COUNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_DATA_FIFO_DEPTH[] = {
+	 { "DMA_DATA_FIFO_DEPTH", 0, 8, &umr_bitfield_default },
+	 { "DMA2DRAW_FIFO_DEPTH", 9, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_REQ_FIFO_DEPTH[] = {
+	 { "DMA_REQ_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DRAW_INIT_FIFO_DEPTH[] = {
+	 { "DRAW_INIT_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_LAST_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+	 { "DST_STATE_ID", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_CACHE_INVALIDATION[] = {
+	 { "CACHE_INVALIDATION", 0, 1, &umr_bitfield_default },
+	 { "DIS_INSTANCING_OPT", 4, 4, &umr_bitfield_default },
+	 { "VS_NO_EXTRA_BUFFER", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INVLD_EN", 6, 7, &umr_bitfield_default },
+	 { "USE_GS_DONE", 9, 9, &umr_bitfield_default },
+	 { "DIS_RANGE_FULL_INVLD", 11, 11, &umr_bitfield_default },
+	 { "GS_LATE_ALLOC_EN", 12, 12, &umr_bitfield_default },
+	 { "STREAMOUT_FULL_FLUSH", 13, 13, &umr_bitfield_default },
+	 { "ES_LIMIT", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_RESET_DEBUG[] = {
+	 { "GS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "TESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "WD_DISABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DELAY[] = {
+	 { "SKIP_DELAY", 0, 7, &umr_bitfield_default },
+	 { "SE0_WD_DELAY", 8, 10, &umr_bitfield_default },
+	 { "SE1_WD_DELAY", 11, 13, &umr_bitfield_default },
+	 { "SE2_WD_DELAY", 14, 16, &umr_bitfield_default },
+	 { "SE3_WD_DELAY", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_FIFO_DEPTHS[] = {
+	 { "VS_DEALLOC_TBL_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "RESERVED_0", 7, 7, &umr_bitfield_default },
+	 { "CLIPP_FIFO_DEPTH", 8, 21, &umr_bitfield_default },
+	 { "HSINPUT_FIFO_DEPTH", 22, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERTEX_REUSE[] = {
+	 { "VERT_REUSE", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MC_LAT_CNTL[] = {
+	 { "MC_TIME_STAMP_RES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_CNTL_STATUS[] = {
+	 { "IA_BUSY", 0, 0, &umr_bitfield_default },
+	 { "IA_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "IA_DMA_REQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "IA_GRP_BUSY", 3, 3, &umr_bitfield_default },
+	 { "IA_ADC_BUSY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DEBUG_CNTL[] = {
+	 { "VGT_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "VGT_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_DEBUG_CNTL[] = {
+	 { "IA_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "IA_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_CNTL_STATUS[] = {
+	 { "VGT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VGT_OUT_INDX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "VGT_OUT_BUSY", 2, 2, &umr_bitfield_default },
+	 { "VGT_PT_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VGT_TE_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGT_VR_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGT_PI_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGT_GS_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGT_HS_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VGT_TE11_BUSY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_DEBUG_CNTL[] = {
+	 { "WD_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+	 { "WD_DEBUG_SEL_BUS_B", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_CNTL_STATUS[] = {
+	 { "WD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "WD_SPL_DMA_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WD_SPL_DI_BUSY", 2, 2, &umr_bitfield_default },
+	 { "WD_ADC_BUSY", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_PRIM_CONFIG[] = {
+	 { "INACTIVE_IA", 16, 17, &umr_bitfield_default },
+	 { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_PRIM_CONFIG[] = {
+	 { "INACTIVE_IA", 16, 17, &umr_bitfield_default },
+	 { "INACTIVE_VGT_PA", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_QOS[] = {
+	 { "DRAW_STALL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_SYS_CONFIG[] = {
+	 { "DUAL_CORE_EN", 0, 0, &umr_bitfield_default },
+	 { "MAX_LS_HS_THDGRP", 1, 6, &umr_bitfield_default },
+	 { "ADC_EVENT_FILTER_DISABLE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_PIPE_CONTROL[] = {
+	 { "HYSTERESIS_CNT", 0, 12, &umr_bitfield_default },
+	 { "RESERVED", 13, 15, &umr_bitfield_default },
+	 { "CONTEXT_SUSPEND_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_SHADER_ARRAY_CONFIG[] = {
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SHADER_ARRAY_CONFIG[] = {
+	 { "INACTIVE_CUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_CONTROL[] = {
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "IA_SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_LS_HS_CONFIG[] = {
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_DEBUG_CNTL[] = {
+	 { "SU_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_CNTL_STATUS[] = {
+	 { "CL_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_ENHANCE[] = {
+	 { "CLIP_VTX_REORDER_ENA", 0, 0, &umr_bitfield_default },
+	 { "NUM_CLIP_SEQ", 1, 2, &umr_bitfield_default },
+	 { "CLIPPED_PRIM_SEQ_STALL", 3, 3, &umr_bitfield_default },
+	 { "VE_NAN_PROC_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "XTRA_DEBUG_REG_SEL", 5, 5, &umr_bitfield_default },
+	 { "ECO_SPARE3", 28, 28, &umr_bitfield_default },
+	 { "ECO_SPARE2", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_RESET_DEBUG[] = {
+	 { "CL_TRIV_DISC_DISABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_CNTL_STATUS[] = {
+	 { "SU_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FIFO_DEPTH_CNTL[] = {
+	 { "DEPTH", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_HV_LOCK[] = {
+	 { "DISABLE_NON_PRIV_WRITES", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FORCE_EOV_MAX_CNTS[] = {
+	 { "FORCE_EOV_MAX_CLK_CNT", 0, 15, &umr_bitfield_default },
+	 { "FORCE_EOV_MAX_REZ_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_FIFO_SIZE[] = {
+	 { "SC_FRONTEND_PRIM_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_BACKEND_PRIM_FIFO_SIZE", 6, 14, &umr_bitfield_default },
+	 { "SC_HIZ_TILE_FIFO_SIZE", 15, 20, &umr_bitfield_default },
+	 { "SC_EARLYZ_TILE_FIFO_SIZE", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_IF_FIFO_SIZE[] = {
+	 { "SC_DB_TILE_IF_FIFO_SIZE", 0, 5, &umr_bitfield_default },
+	 { "SC_DB_QUAD_IF_FIFO_SIZE", 6, 11, &umr_bitfield_default },
+	 { "SC_SPI_IF_FIFO_SIZE", 12, 17, &umr_bitfield_default },
+	 { "SC_BCI_IF_FIFO_SIZE", 18, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DEBUG_CNTL[] = {
+	 { "SC_DEBUG_INDX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_ENHANCE[] = {
+	 { "ENABLE_PA_SC_OUT_OF_ORDER", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_SC_DB_TILE_FIX", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_AA_MASK_FULL_FIX", 2, 2, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOCATIONS", 3, 3, &umr_bitfield_default },
+	 { "ENABLE_1XMSAA_SAMPLE_LOC_CENTROID", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_SCISSOR_FIX", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_PW_BUBBLE_COLLAPSE", 6, 7, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PACKER", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_DUALGRAD_PERF_OPTIMIZATION", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_PRIM", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_SUPERTILE", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_SC_PROCESS_RESET_TILE", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_PA_SC_GUIDANCE", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_MULTICYCLE_BUBBLE_FREEZE", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_POLY_MODE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS", 23, 23, &umr_bitfield_default },
+	 { "ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO", 25, 25, &umr_bitfield_default },
+	 { "OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT", 26, 26, &umr_bitfield_default },
+	 { "OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_EOP_LINE_STIPPLE_RESET", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_VPZ_EOP_LINE_STIPPLE_RESET", 29, 29, &umr_bitfield_default },
+	 { "ECO_SPARE1", 30, 30, &umr_bitfield_default },
+	 { "ECO_SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_ENHANCE_1[] = {
+	 { "REALIGN_DQUADS_OVERRIDE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "REALIGN_DQUADS_OVERRIDE", 1, 2, &umr_bitfield_default },
+	 { "ENABLE_SC_BINNING", 3, 3, &umr_bitfield_default },
+	 { "ECO_SPARE0", 4, 4, &umr_bitfield_default },
+	 { "ECO_SPARE1", 5, 5, &umr_bitfield_default },
+	 { "ECO_SPARE2", 6, 6, &umr_bitfield_default },
+	 { "ECO_SPARE3", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_DSM_CNTL[] = {
+	 { "FORCE_EOV_REZ_0", 0, 0, &umr_bitfield_default },
+	 { "FORCE_EOV_REZ_1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG7[] = {
+	 { "debug_tfmmFifoEmpty", 0, 0, &umr_bitfield_default },
+	 { "debug_tfmmFifoFull", 1, 1, &umr_bitfield_default },
+	 { "hs_pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "hs_pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "hs_pipe1_rtr", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 15, &umr_bitfield_default },
+	 { "TF_addr", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CONFIG[] = {
+	 { "UNUSED", 0, 7, &umr_bitfield_default },
+	 { "DEBUG_EN", 8, 8, &umr_bitfield_default },
+	 { "DEBUG_SINGLE_MEMOP", 9, 9, &umr_bitfield_default },
+	 { "DEBUG_ONE_INST_CLAUSE", 10, 10, &umr_bitfield_default },
+	 { "EARLY_TA_DONE_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "DUA_FLAT_LOCK_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "DUA_LDS_BYPASS_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DUA_FLAT_LDS_PINGPONG_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_VMEM_SOFT_CLAUSE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_SMEM_SOFT_CLAUSE", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_HIPRIO_ON_EXP_RDY_VS", 18, 18, &umr_bitfield_default },
+	 { "PRIO_VAL_ON_EXP_RDY_VS", 19, 20, &umr_bitfield_default },
+	 { "REPLAY_SLEEP_CNT", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_CONFIG[] = {
+	 { "INST_CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "DATA_CACHE_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MISS_FIFO_DEPTH", 4, 5, &umr_bitfield_default },
+	 { "HIT_FIFO_DEPTH", 6, 6, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_MISS", 7, 7, &umr_bitfield_default },
+	 { "FORCE_IN_ORDER", 8, 8, &umr_bitfield_default },
+	 { "IDENTITY_HASH_BANK", 9, 9, &umr_bitfield_default },
+	 { "IDENTITY_HASH_SET", 10, 10, &umr_bitfield_default },
+	 { "PER_VMID_INV_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "EVICT_LRU", 12, 13, &umr_bitfield_default },
+	 { "FORCE_2_BANK", 14, 14, &umr_bitfield_default },
+	 { "FORCE_1_BANK", 15, 15, &umr_bitfield_default },
+	 { "LS_DISABLE_CLOCKS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_RANDOM_WAVE_PRI[] = {
+	 { "RET", 0, 6, &umr_bitfield_default },
+	 { "RUI", 7, 9, &umr_bitfield_default },
+	 { "RNG", 10, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_REG_CREDITS[] = {
+	 { "SRBM_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "CMD_CREDITS", 8, 11, &umr_bitfield_default },
+	 { "REG_BUSY", 28, 28, &umr_bitfield_default },
+	 { "SRBM_OVERFLOW", 29, 29, &umr_bitfield_default },
+	 { "IMMED_OVERFLOW", 30, 30, &umr_bitfield_default },
+	 { "CMD_OVERFLOW", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FIFO_SIZES[] = {
+	 { "INTERRUPT_FIFO_SIZE", 0, 3, &umr_bitfield_default },
+	 { "TTRACE_FIFO_SIZE", 8, 11, &umr_bitfield_default },
+	 { "EXPORT_BUF_SIZE", 16, 17, &umr_bitfield_default },
+	 { "VMEM_DATA_FIFO_SIZE", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DSM_CNTL[] = {
+	 { "WAVEFRONT_STALL_0", 0, 0, &umr_bitfield_default },
+	 { "WAVEFRONT_STALL_1", 1, 1, &umr_bitfield_default },
+	 { "SPI_BACKPRESSURE_0", 2, 2, &umr_bitfield_default },
+	 { "SPI_BACKPRESSURE_1", 3, 3, &umr_bitfield_default },
+	 { "SEL_DSM_SGPR_IRRITATOR_DATA0", 8, 8, &umr_bitfield_default },
+	 { "SEL_DSM_SGPR_IRRITATOR_DATA1", 9, 9, &umr_bitfield_default },
+	 { "SGPR_ENABLE_SINGLE_WRITE", 10, 10, &umr_bitfield_default },
+	 { "SEL_DSM_LDS_IRRITATOR_DATA0", 16, 16, &umr_bitfield_default },
+	 { "SEL_DSM_LDS_IRRITATOR_DATA1", 17, 17, &umr_bitfield_default },
+	 { "LDS_ENABLE_SINGLE_WRITE01", 18, 18, &umr_bitfield_default },
+	 { "SEL_DSM_LDS_IRRITATOR_DATA2", 19, 19, &umr_bitfield_default },
+	 { "SEL_DSM_LDS_IRRITATOR_DATA3", 20, 20, &umr_bitfield_default },
+	 { "LDS_ENABLE_SINGLE_WRITE23", 21, 21, &umr_bitfield_default },
+	 { "SEL_DSM_SP_IRRITATOR_DATA0", 24, 24, &umr_bitfield_default },
+	 { "SEL_DSM_SP_IRRITATOR_DATA1", 25, 25, &umr_bitfield_default },
+	 { "SP_ENABLE_SINGLE_WRITE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUSER_SQC_BANK_DISABLE[] = {
+	 { "SQC0_BANK_DISABLE", 16, 19, &umr_bitfield_default },
+	 { "SQC1_BANK_DISABLE", 20, 23, &umr_bitfield_default },
+	 { "SQC2_BANK_DISABLE", 24, 27, &umr_bitfield_default },
+	 { "SQC3_BANK_DISABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "INTERRUPT_MSG_BUSY", 1, 1, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH0", 4, 15, &umr_bitfield_default },
+	 { "WAVE_LEVEL_SH1", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_BASES[] = {
+	 { "PRIVATE_BASE", 0, 15, &umr_bitfield_default },
+	 { "SHARED_BASE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_APE1_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_APE1_LIMIT[] = {
+	 { "LIMIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_MEM_CONFIG[] = {
+	 { "ADDRESS_MODE", 0, 1, &umr_bitfield_default },
+	 { "PRIVATE_ATC", 2, 2, &umr_bitfield_default },
+	 { "ALIGNMENT_MODE", 3, 4, &umr_bitfield_default },
+	 { "DEFAULT_MTYPE", 5, 7, &umr_bitfield_default },
+	 { "APE1_MTYPE", 8, 10, &umr_bitfield_default },
+	 { "APE1_ATC", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_DSM_CNTL[] = {
+	 { "SEL_DATA_ICACHE_BANKA", 0, 1, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_BANKA", 2, 2, &umr_bitfield_default },
+	 { "SEL_DATA_ICACHE_BANKB", 3, 4, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_BANKB", 5, 5, &umr_bitfield_default },
+	 { "SEL_DATA_ICACHE_BANKC", 6, 7, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_BANKC", 8, 8, &umr_bitfield_default },
+	 { "SEL_DATA_ICACHE_BANKD", 9, 10, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_BANKD", 11, 11, &umr_bitfield_default },
+	 { "SEL_DATA_ICACHE_GATCL1", 12, 13, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_ICACHE_GATCL1", 14, 14, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_BANKA", 15, 16, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_BANKA", 17, 17, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_BANKB", 18, 19, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_BANKB", 20, 20, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_BANKC", 21, 22, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_BANKC", 23, 23, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_BANKD", 24, 25, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_BANKD", 26, 26, &umr_bitfield_default },
+	 { "SEL_DATA_DCACHE_GATCL1", 27, 28, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_DCACHE_GATCL1", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL2[] = {
+	 { "FIFO_LEVEL_GFX0", 0, 7, &umr_bitfield_default },
+	 { "FIFO_LEVEL_GFX1", 8, 15, &umr_bitfield_default },
+	 { "FIFO_LEVEL_IMMED", 16, 23, &umr_bitfield_default },
+	 { "FIFO_LEVEL_HOST", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_DEBUG_STS_GLOBAL3[] = {
+	 { "FIFO_LEVEL_HOST_CMD", 0, 3, &umr_bitfield_default },
+	 { "FIFO_LEVEL_HOST_REG", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_SHADER_RATE_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SHADER_RATE_CONFIG[] = {
+	 { "DPFP_RATE", 1, 2, &umr_bitfield_default },
+	 { "SQC_BALANCE_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "HALF_LDS", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_INTERRUPT_AUTO_MASK[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_INTERRUPT_MSG_CTRL[] = {
+	 { "STALL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_REG_TIMESTAMP[] = {
+	 { "TIMESTAMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CMD_TIMESTAMP[] = {
+	 { "TIMESTAMP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IND_INDEX[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "THREAD_ID", 6, 11, &umr_bitfield_default },
+	 { "AUTO_INCR", 12, 12, &umr_bitfield_default },
+	 { "FORCE_READ", 13, 13, &umr_bitfield_default },
+	 { "READ_TIMEOUT", 14, 14, &umr_bitfield_default },
+	 { "UNINDEXED", 15, 15, &umr_bitfield_default },
+	 { "INDEX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_CMD[] = {
+	 { "CMD", 0, 2, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "CHECK_VMID", 7, 7, &umr_bitfield_default },
+	 { "DATA", 8, 10, &umr_bitfield_default },
+	 { "WAVE_ID", 16, 19, &umr_bitfield_default },
+	 { "SIMD_ID", 20, 21, &umr_bitfield_default },
+	 { "QUEUE_ID", 24, 26, &umr_bitfield_default },
+	 { "VM_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TIME_HI[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TIME_LO[] = {
+	 { "TIME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_VOP3_0_SDST_ENC[] = {
+	 { "VDST", 0, 7, &umr_bitfield_default },
+	 { "SDST", 8, 14, &umr_bitfield_default },
+	 { "CLAMP", 15, 15, &umr_bitfield_default },
+	 { "OP", 16, 25, &umr_bitfield_default },
+	 { "ENCODING", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_VOP_SDWA[] = {
+	 { "SRC0", 0, 7, &umr_bitfield_default },
+	 { "DST_SEL", 8, 10, &umr_bitfield_default },
+	 { "DST_UNUSED", 11, 12, &umr_bitfield_default },
+	 { "CLAMP", 13, 13, &umr_bitfield_default },
+	 { "SRC0_SEL", 16, 18, &umr_bitfield_default },
+	 { "SRC0_SEXT", 19, 19, &umr_bitfield_default },
+	 { "SRC0_NEG", 20, 20, &umr_bitfield_default },
+	 { "SRC0_ABS", 21, 21, &umr_bitfield_default },
+	 { "SRC1_SEL", 24, 26, &umr_bitfield_default },
+	 { "SRC1_SEXT", 27, 27, &umr_bitfield_default },
+	 { "SRC1_NEG", 28, 28, &umr_bitfield_default },
+	 { "SRC1_ABS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_MTBUF_1[] = {
+	 { "VADDR", 0, 7, &umr_bitfield_default },
+	 { "VDATA", 8, 15, &umr_bitfield_default },
+	 { "SRSRC", 16, 20, &umr_bitfield_default },
+	 { "SLC", 22, 22, &umr_bitfield_default },
+	 { "TFE", 23, 23, &umr_bitfield_default },
+	 { "SOFFSET", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_SMEM_1[] = {
+	 { "OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EXP_1[] = {
+	 { "VSRC0", 0, 7, &umr_bitfield_default },
+	 { "VSRC1", 8, 15, &umr_bitfield_default },
+	 { "VSRC2", 16, 23, &umr_bitfield_default },
+	 { "VSRC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_SOP2[] = {
+	 { "SSRC0", 0, 7, &umr_bitfield_default },
+	 { "SSRC1", 8, 15, &umr_bitfield_default },
+	 { "SDST", 16, 22, &umr_bitfield_default },
+	 { "OP", 23, 29, &umr_bitfield_default },
+	 { "ENCODING", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_CNTR[] = {
+	 { "CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_CTR_CTRL[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "LOAD", 1, 1, &umr_bitfield_default },
+	 { "CLEAR", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_ALU_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_TEX_CYCLES[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_ALU_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LB_DATA_TEX_STALLS[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_EDC_CNT[] = {
+	 { "INST_SEC", 0, 7, &umr_bitfield_default },
+	 { "INST_DED", 8, 15, &umr_bitfield_default },
+	 { "DATA_SEC", 16, 23, &umr_bitfield_default },
+	 { "DATA_DED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EDC_SEC_CNT[] = {
+	 { "LDS_SEC", 0, 7, &umr_bitfield_default },
+	 { "SGPR_SEC", 8, 15, &umr_bitfield_default },
+	 { "VGPR_SEC", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EDC_DED_CNT[] = {
+	 { "LDS_DED", 0, 7, &umr_bitfield_default },
+	 { "SGPR_DED", 8, 15, &umr_bitfield_default },
+	 { "VGPR_DED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_EDC_INFO[] = {
+	 { "WAVE_ID", 0, 3, &umr_bitfield_default },
+	 { "SIMD_ID", 4, 5, &umr_bitfield_default },
+	 { "SOURCE", 6, 8, &umr_bitfield_default },
+	 { "VM_ID", 9, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "WAVE_ID", 10, 13, &umr_bitfield_default },
+	 { "SIMD_ID", 14, 15, &umr_bitfield_default },
+	 { "DATA_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID", 5, 8, &umr_bitfield_default },
+	 { "SIMD_ID", 9, 10, &umr_bitfield_default },
+	 { "PC_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "PIPE_ID", 5, 6, &umr_bitfield_default },
+	 { "ME_ID", 7, 8, &umr_bitfield_default },
+	 { "REG_ADDR", 9, 15, &umr_bitfield_default },
+	 { "DATA_LO", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "CNTR_BANK", 10, 11, &umr_bitfield_default },
+	 { "CNTR0", 12, 24, &umr_bitfield_default },
+	 { "CNTR1_LO", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_WAVE_START[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "WAVE_ID", 10, 13, &umr_bitfield_default },
+	 { "SIMD_ID", 14, 15, &umr_bitfield_default },
+	 { "DISPATCHER", 16, 20, &umr_bitfield_default },
+	 { "VS_NO_ALLOC_OR_GROUPED", 21, 21, &umr_bitfield_default },
+	 { "COUNT", 22, 28, &umr_bitfield_default },
+	 { "TG_ID", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_EVENT[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "SH_ID", 5, 5, &umr_bitfield_default },
+	 { "STAGE", 6, 8, &umr_bitfield_default },
+	 { "EVENT_TYPE", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID", 5, 8, &umr_bitfield_default },
+	 { "SIMD_ID", 9, 10, &umr_bitfield_default },
+	 { "INST_TYPE", 11, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_CMN[] = {
+	 { "TOKEN_TYPE", 0, 3, &umr_bitfield_default },
+	 { "TIME_DELTA", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[] = {
+	 { "DATA_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[] = {
+	 { "TIME_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[] = {
+	 { "PC_HI", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[] = {
+	 { "CNTR1_HI", 0, 5, &umr_bitfield_default },
+	 { "CNTR2", 6, 18, &umr_bitfield_default },
+	 { "CNTR3", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_WREXEC_EXEC_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_GATCL1_CNTL[] = {
+	 { "RESERVED", 0, 17, &umr_bitfield_default },
+	 { "DCACHE_INVALIDATE_ALL_VMID", 18, 18, &umr_bitfield_default },
+	 { "DCACHE_FORCE_MISS", 19, 19, &umr_bitfield_default },
+	 { "DCACHE_FORCE_IN_ORDER", 20, 20, &umr_bitfield_default },
+	 { "DCACHE_REDUCE_FIFO_DEPTH_BY_2", 21, 22, &umr_bitfield_default },
+	 { "DCACHE_REDUCE_CACHE_SIZE_BY_2", 23, 24, &umr_bitfield_default },
+	 { "ICACHE_INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default },
+	 { "ICACHE_FORCE_MISS", 26, 26, &umr_bitfield_default },
+	 { "ICACHE_FORCE_IN_ORDER", 27, 27, &umr_bitfield_default },
+	 { "ICACHE_REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default },
+	 { "ICACHE_REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_ATC_EDC_GATCL1_CNT[] = {
+	 { "ICACHE_DATA_SEC", 0, 7, &umr_bitfield_default },
+	 { "DCACHE_DATA_SEC", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 15, &umr_bitfield_default },
+	 { "STRIDE", 16, 29, &umr_bitfield_default },
+	 { "CACHE_SWIZZLE", 30, 30, &umr_bitfield_default },
+	 { "SWIZZLE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD2[] = {
+	 { "NUM_RECORDS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_BUF_RSRC_WORD3[] = {
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "NUM_FORMAT", 12, 14, &umr_bitfield_default },
+	 { "DATA_FORMAT", 15, 18, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 19, 20, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 21, 22, &umr_bitfield_default },
+	 { "ADD_TID_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "ATC", 24, 24, &umr_bitfield_default },
+	 { "HASH_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "HEAP", 26, 26, &umr_bitfield_default },
+	 { "MTYPE", 27, 29, &umr_bitfield_default },
+	 { "TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD0[] = {
+	 { "BASE_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD1[] = {
+	 { "BASE_ADDRESS_HI", 0, 7, &umr_bitfield_default },
+	 { "MIN_LOD", 8, 19, &umr_bitfield_default },
+	 { "DATA_FORMAT", 20, 25, &umr_bitfield_default },
+	 { "NUM_FORMAT", 26, 29, &umr_bitfield_default },
+	 { "MTYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD2[] = {
+	 { "WIDTH", 0, 13, &umr_bitfield_default },
+	 { "HEIGHT", 14, 27, &umr_bitfield_default },
+	 { "PERF_MOD", 28, 30, &umr_bitfield_default },
+	 { "INTERLACED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD3[] = {
+	 { "DST_SEL_X", 0, 2, &umr_bitfield_default },
+	 { "DST_SEL_Y", 3, 5, &umr_bitfield_default },
+	 { "DST_SEL_Z", 6, 8, &umr_bitfield_default },
+	 { "DST_SEL_W", 9, 11, &umr_bitfield_default },
+	 { "BASE_LEVEL", 12, 15, &umr_bitfield_default },
+	 { "LAST_LEVEL", 16, 19, &umr_bitfield_default },
+	 { "TILING_INDEX", 20, 24, &umr_bitfield_default },
+	 { "POW2_PAD", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 26, 26, &umr_bitfield_default },
+	 { "ATC", 27, 27, &umr_bitfield_default },
+	 { "TYPE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD4[] = {
+	 { "DEPTH", 0, 12, &umr_bitfield_default },
+	 { "PITCH", 13, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD5[] = {
+	 { "BASE_ARRAY", 0, 12, &umr_bitfield_default },
+	 { "LAST_ARRAY", 13, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD6[] = {
+	 { "MIN_LOD_WARN", 0, 11, &umr_bitfield_default },
+	 { "COUNTER_BANK_ID", 12, 19, &umr_bitfield_default },
+	 { "LOD_HDW_CNT_EN", 20, 20, &umr_bitfield_default },
+	 { "COMPRESSION_EN", 21, 21, &umr_bitfield_default },
+	 { "ALPHA_IS_ON_MSB", 22, 22, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 23, 23, &umr_bitfield_default },
+	 { "LOST_ALPHA_BITS", 24, 27, &umr_bitfield_default },
+	 { "LOST_COLOR_BITS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_RSRC_WORD7[] = {
+	 { "META_DATA_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD0[] = {
+	 { "CLAMP_X", 0, 2, &umr_bitfield_default },
+	 { "CLAMP_Y", 3, 5, &umr_bitfield_default },
+	 { "CLAMP_Z", 6, 8, &umr_bitfield_default },
+	 { "MAX_ANISO_RATIO", 9, 11, &umr_bitfield_default },
+	 { "DEPTH_COMPARE_FUNC", 12, 14, &umr_bitfield_default },
+	 { "FORCE_UNNORMALIZED", 15, 15, &umr_bitfield_default },
+	 { "ANISO_THRESHOLD", 16, 18, &umr_bitfield_default },
+	 { "MC_COORD_TRUNC", 19, 19, &umr_bitfield_default },
+	 { "FORCE_DEGAMMA", 20, 20, &umr_bitfield_default },
+	 { "ANISO_BIAS", 21, 26, &umr_bitfield_default },
+	 { "TRUNC_COORD", 27, 27, &umr_bitfield_default },
+	 { "DISABLE_CUBE_WRAP", 28, 28, &umr_bitfield_default },
+	 { "FILTER_MODE", 29, 30, &umr_bitfield_default },
+	 { "COMPAT_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD1[] = {
+	 { "MIN_LOD", 0, 11, &umr_bitfield_default },
+	 { "MAX_LOD", 12, 23, &umr_bitfield_default },
+	 { "PERF_MIP", 24, 27, &umr_bitfield_default },
+	 { "PERF_Z", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD2[] = {
+	 { "LOD_BIAS", 0, 13, &umr_bitfield_default },
+	 { "LOD_BIAS_SEC", 14, 19, &umr_bitfield_default },
+	 { "XY_MAG_FILTER", 20, 21, &umr_bitfield_default },
+	 { "XY_MIN_FILTER", 22, 23, &umr_bitfield_default },
+	 { "Z_FILTER", 24, 25, &umr_bitfield_default },
+	 { "MIP_FILTER", 26, 27, &umr_bitfield_default },
+	 { "MIP_POINT_PRECLAMP", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_LSB_CEIL", 29, 29, &umr_bitfield_default },
+	 { "FILTER_PREC_FIX", 30, 30, &umr_bitfield_default },
+	 { "ANISO_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_IMG_SAMP_WORD3[] = {
+	 { "BORDER_COLOR_PTR", 0, 11, &umr_bitfield_default },
+	 { "BORDER_COLOR_TYPE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FLAT_SCRATCH_WORD0[] = {
+	 { "SIZE", 0, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_FLAT_SCRATCH_WORD1[] = {
+	 { "OFFSET", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_M0_GPR_IDX_WORD[] = {
+	 { "INDEX", 0, 7, &umr_bitfield_default },
+	 { "VSRC0_REL", 12, 12, &umr_bitfield_default },
+	 { "VSRC1_REL", 13, 13, &umr_bitfield_default },
+	 { "VSRC2_REL", 14, 14, &umr_bitfield_default },
+	 { "VDST_REL", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG26[] = {
+	 { "cm_state0", 0, 1, &umr_bitfield_default },
+	 { "cm_state1", 2, 3, &umr_bitfield_default },
+	 { "cm_state2", 4, 5, &umr_bitfield_default },
+	 { "cm_state3", 6, 7, &umr_bitfield_default },
+	 { "cm_state4", 8, 9, &umr_bitfield_default },
+	 { "cm_state5", 10, 11, &umr_bitfield_default },
+	 { "cm_state6", 12, 13, &umr_bitfield_default },
+	 { "cm_state7", 14, 15, &umr_bitfield_default },
+	 { "cm_state8", 16, 17, &umr_bitfield_default },
+	 { "cm_state9", 18, 19, &umr_bitfield_default },
+	 { "cm_state10", 20, 21, &umr_bitfield_default },
+	 { "cm_state11", 22, 23, &umr_bitfield_default },
+	 { "cm_state12", 24, 25, &umr_bitfield_default },
+	 { "cm_state13", 26, 27, &umr_bitfield_default },
+	 { "cm_state14", 28, 29, &umr_bitfield_default },
+	 { "cm_state15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY[] = {
+	 { "POS_FREE_OR_VALIDS", 0, 0, &umr_bitfield_default },
+	 { "POS_REQUESTER_BUSY", 1, 1, &umr_bitfield_default },
+	 { "PA_SX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "POS_SCBD_BUSY", 3, 3, &umr_bitfield_default },
+	 { "POS_BANK3VAL3_BUSY", 4, 4, &umr_bitfield_default },
+	 { "POS_BANK3VAL2_BUSY", 5, 5, &umr_bitfield_default },
+	 { "POS_BANK3VAL1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "POS_BANK3VAL0_BUSY", 7, 7, &umr_bitfield_default },
+	 { "POS_BANK2VAL3_BUSY", 8, 8, &umr_bitfield_default },
+	 { "POS_BANK2VAL2_BUSY", 9, 9, &umr_bitfield_default },
+	 { "POS_BANK2VAL1_BUSY", 10, 10, &umr_bitfield_default },
+	 { "POS_BANK2VAL0_BUSY", 11, 11, &umr_bitfield_default },
+	 { "POS_BANK1VAL3_BUSY", 12, 12, &umr_bitfield_default },
+	 { "POS_BANK1VAL2_BUSY", 13, 13, &umr_bitfield_default },
+	 { "POS_BANK1VAL1_BUSY", 14, 14, &umr_bitfield_default },
+	 { "POS_BANK1VAL0_BUSY", 15, 15, &umr_bitfield_default },
+	 { "POS_BANK0VAL3_BUSY", 16, 16, &umr_bitfield_default },
+	 { "POS_BANK0VAL2_BUSY", 17, 17, &umr_bitfield_default },
+	 { "POS_BANK0VAL1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "POS_BANK0VAL0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "POS_INMUX_VALID", 20, 20, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ3", 21, 21, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ2", 22, 22, &umr_bitfield_default },
+	 { "WRCTRL1_VALIDQ1", 23, 23, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ3", 24, 24, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ2", 25, 25, &umr_bitfield_default },
+	 { "WRCTRL0_VALIDQ1", 26, 26, &umr_bitfield_default },
+	 { "PCCMD_VALID", 27, 27, &umr_bitfield_default },
+	 { "VDATA1_VALID", 28, 28, &umr_bitfield_default },
+	 { "VDATA0_VALID", 29, 29, &umr_bitfield_default },
+	 { "CMD_BUSYORVAL", 30, 30, &umr_bitfield_default },
+	 { "ADDR_BUSYORVAL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_2[] = {
+	 { "COL_SCBD_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_REQ3_FREECNT_NE0", 1, 1, &umr_bitfield_default },
+	 { "COL_REQ3_IDLE", 2, 2, &umr_bitfield_default },
+	 { "COL_REQ3_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_REQ2_FREECNT_NE0", 4, 4, &umr_bitfield_default },
+	 { "COL_REQ2_IDLE", 5, 5, &umr_bitfield_default },
+	 { "COL_REQ2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_REQ1_FREECNT_NE0", 7, 7, &umr_bitfield_default },
+	 { "COL_REQ1_IDLE", 8, 8, &umr_bitfield_default },
+	 { "COL_REQ1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_REQ0_FREECNT_NE0", 10, 10, &umr_bitfield_default },
+	 { "COL_REQ0_IDLE", 11, 11, &umr_bitfield_default },
+	 { "COL_REQ0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_DBIF3_SENDFREE_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_DBIF3_FIFO_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_DBIF3_READ_VALID", 15, 15, &umr_bitfield_default },
+	 { "COL_DBIF2_SENDFREE_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_DBIF2_FIFO_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_DBIF2_READ_VALID", 18, 18, &umr_bitfield_default },
+	 { "COL_DBIF1_SENDFREE_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_DBIF1_FIFO_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_DBIF1_READ_VALID", 21, 21, &umr_bitfield_default },
+	 { "COL_DBIF0_SENDFREE_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_DBIF0_FIFO_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_DBIF0_READ_VALID", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_3[] = {
+	 { "COL_BUFF3_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF3_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF2_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL3_BUSY", 25, 25, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL2_BUSY", 26, 26, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL1_BUSY", 27, 27, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK3_VAL0_BUSY", 28, 28, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL3_BUSY", 29, 29, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL2_BUSY", 30, 30, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK2_VAL1_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_BUSY_4[] = {
+	 { "COL_BUFF1_BANK2_VAL0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL3_BUSY", 1, 1, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL1_BUSY", 3, 3, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK1_VAL0_BUSY", 4, 4, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL3_BUSY", 5, 5, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL2_BUSY", 6, 6, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL1_BUSY", 7, 7, &umr_bitfield_default },
+	 { "COL_BUFF1_BANK0_VAL0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL3_BUSY", 9, 9, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL1_BUSY", 11, 11, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK3_VAL0_BUSY", 12, 12, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL3_BUSY", 13, 13, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL2_BUSY", 14, 14, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK2_VAL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL3_BUSY", 17, 17, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL2_BUSY", 18, 18, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK1_VAL0_BUSY", 20, 20, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL3_BUSY", 21, 21, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL1_BUSY", 23, 23, &umr_bitfield_default },
+	 { "COL_BUFF0_BANK0_VAL0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "RESERVED", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_DEBUG_1[] = {
+	 { "SX_DB_QUAD_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DONT_RD_DST", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_BYPASS", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DISCARD_PIXEL", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_QUAD_PAIR_OPT", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_PIX_EN_ZERO_OPT", 12, 12, &umr_bitfield_default },
+	 { "DEBUG_DATA", 13, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_START_PHASE[] = {
+	 { "VGPR_START_PHASE", 0, 1, &umr_bitfield_default },
+	 { "SGPR_START_PHASE", 2, 3, &umr_bitfield_default },
+	 { "WAVE_START_PHASE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GFX_CNTL[] = {
+	 { "RESET_COUNTS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL[] = {
+	 { "GPR_WRITE_PRIORITY", 0, 20, &umr_bitfield_default },
+	 { "EXP_PRIORITY_ORDER", 21, 23, &umr_bitfield_default },
+	 { "ENABLE_SQG_TOP_EVENTS", 24, 24, &umr_bitfield_default },
+	 { "ENABLE_SQG_BOP_EVENTS", 25, 25, &umr_bitfield_default },
+	 { "RSRC_MGMT_RESET", 26, 26, &umr_bitfield_default },
+	 { "TTRACE_STALL_ALL", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_CNTL[] = {
+	 { "DEBUG_GRBM_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_THREAD_TYPE_SEL", 1, 3, &umr_bitfield_default },
+	 { "DEBUG_GROUP_SEL", 4, 9, &umr_bitfield_default },
+	 { "DEBUG_SIMD_SEL", 10, 15, &umr_bitfield_default },
+	 { "DEBUG_SH_SEL", 16, 16, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_0", 17, 17, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_1", 18, 18, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_2", 19, 19, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_3", 20, 20, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_4", 21, 21, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_5", 22, 22, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_6", 23, 23, &umr_bitfield_default },
+	 { "SPI_ECO_SPARE_7", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_PIPE_SEL", 25, 27, &umr_bitfield_default },
+	 { "DEBUG_REG_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DSM_CNTL[] = {
+	 { "Sel_DSM_SPI_Irritator_data0", 0, 0, &umr_bitfield_default },
+	 { "Sel_DSM_SPI_Irritator_data1", 1, 1, &umr_bitfield_default },
+	 { "SPI_Enable_Single_Write", 2, 2, &umr_bitfield_default },
+	 { "UNUSED", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_EDC_CNT[] = {
+	 { "SED", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL_1[] = {
+	 { "VTX_DONE_DELAY", 0, 3, &umr_bitfield_default },
+	 { "INTERP_ONE_PRIM_PER_ROW", 4, 4, &umr_bitfield_default },
+	 { "PC_LIMIT_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "PC_LIMIT_STRICT", 7, 7, &umr_bitfield_default },
+	 { "CRC_SIMD_ID_WADDR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_MODE", 9, 9, &umr_bitfield_default },
+	 { "LBPW_CU_CHK_CNT", 10, 13, &umr_bitfield_default },
+	 { "PC_LIMIT_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_DEBUG_BUSY[] = {
+	 { "LS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "HS_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ES_BUSY", 2, 2, &umr_bitfield_default },
+	 { "GS_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "PS0_BUSY", 5, 5, &umr_bitfield_default },
+	 { "PS1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CSG_BUSY", 7, 7, &umr_bitfield_default },
+	 { "CS0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "CS1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "CS2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "CS3_BUSY", 11, 11, &umr_bitfield_default },
+	 { "CS4_BUSY", 12, 12, &umr_bitfield_default },
+	 { "CS5_BUSY", 13, 13, &umr_bitfield_default },
+	 { "CS6_BUSY", 14, 14, &umr_bitfield_default },
+	 { "CS7_BUSY", 15, 15, &umr_bitfield_default },
+	 { "LDS_WR_CTL0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "LDS_WR_CTL1_BUSY", 17, 17, &umr_bitfield_default },
+	 { "RSRC_ALLOC0_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RSRC_ALLOC1_BUSY", 19, 19, &umr_bitfield_default },
+	 { "PC_DEALLOC_BUSY", 20, 20, &umr_bitfield_default },
+	 { "EVENT_CLCTR_BUSY", 21, 21, &umr_bitfield_default },
+	 { "GRBM_BUSY", 22, 22, &umr_bitfield_default },
+	 { "SPIS_BUSY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CONFIG_CNTL_2[] = {
+	 { "CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD", 0, 3, &umr_bitfield_default },
+	 { "CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_CNTL[] = {
+	 { "SAMPLE_PERIOD", 0, 3, &umr_bitfield_default },
+	 { "EN", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_0[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_1[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_2[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_3[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_4[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_5[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_6[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_7[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_8[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_LIMIT_9[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "EN_WARN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_0[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_1[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_2[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_3[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_4[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_5[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_6[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_7[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_8[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_9[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_10[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_11[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_12[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_13[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_14[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_15[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_16[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_17[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_18[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_19[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_STATUS_20[] = {
+	 { "MAX_CNT", 0, 30, &umr_bitfield_default },
+	 { "INT_SENT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WF_LIFETIME_DEBUG[] = {
+	 { "START_VALUE", 0, 30, &umr_bitfield_default },
+	 { "OVERRIDE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SLAVE_DEBUG_BUSY[] = {
+	 { "LS_VTX_BUSY", 0, 0, &umr_bitfield_default },
+	 { "HS_VTX_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ES_VTX_BUSY", 2, 2, &umr_bitfield_default },
+	 { "GS_VTX_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VS_VTX_BUSY", 4, 4, &umr_bitfield_default },
+	 { "VGPR_WC00_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VGPR_WC01_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VGPR_WC10_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VGPR_WC11_BUSY", 8, 8, &umr_bitfield_default },
+	 { "SGPR_WC00_BUSY", 9, 9, &umr_bitfield_default },
+	 { "SGPR_WC01_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SGPR_WC02_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SGPR_WC03_BUSY", 12, 12, &umr_bitfield_default },
+	 { "SGPR_WC10_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SGPR_WC11_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SGPR_WC12_BUSY", 15, 15, &umr_bitfield_default },
+	 { "SGPR_WC13_BUSY", 16, 16, &umr_bitfield_default },
+	 { "WAVEBUFFER0_BUSY", 17, 17, &umr_bitfield_default },
+	 { "WAVEBUFFER1_BUSY", 18, 18, &umr_bitfield_default },
+	 { "WAVE_WC0_BUSY", 19, 19, &umr_bitfield_default },
+	 { "WAVE_WC1_BUSY", 20, 20, &umr_bitfield_default },
+	 { "EVENT_CNTL_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SAVE_CTX_BUSY", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_CTR_CTRL[] = {
+	 { "LOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_LB_DATA_REG[] = {
+	 { "CNT_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PG_ENABLE_STATIC_CU_MASK[] = {
+	 { "CU_MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDS_CREDITS[] = {
+	 { "DS_DATA_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "DS_CMD_CREDITS", 8, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SX_EXPORT_BUFFER_SIZES[] = {
+	 { "COLOR_BUFFER_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_BUFFER_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SX_SCOREBOARD_BUFFER_SIZES[] = {
+	 { "COLOR_SCOREBOARD_SIZE", 0, 15, &umr_bitfield_default },
+	 { "POSITION_SCOREBOARD_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_STATUS[] = {
+	 { "ACTIVE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_0[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_1[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_2[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_3[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_4[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_5[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_6[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CSQ_WF_ACTIVE_COUNT_7[] = {
+	 { "COUNT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmBCI_DEBUG_READ[] = {
+	 { "DATA", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_PSMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P0_TRAP_SCREEN_GPR_MIN[] = {
+	 { "VGPR_MIN", 0, 5, &umr_bitfield_default },
+	 { "SGPR_MIN", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_PSMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_P1_TRAP_SCREEN_GPR_MIN[] = {
+	 { "VGPR_MIN", 0, 5, &umr_bitfield_default },
+	 { "SGPR_MIN", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_CNTL[] = {
+	 { "SYNC_PHASE_SH", 0, 1, &umr_bitfield_default },
+	 { "SYNC_PHASE_VC_SMX", 4, 5, &umr_bitfield_default },
+	 { "PAD_STALL_EN", 8, 8, &umr_bitfield_default },
+	 { "EXTEND_LDS_STALL", 9, 10, &umr_bitfield_default },
+	 { "LDS_STALL_PHASE_ADJUST", 11, 12, &umr_bitfield_default },
+	 { "PRECISION_COMPATIBILITY", 15, 15, &umr_bitfield_default },
+	 { "GATHER4_FLOAT_MODE", 16, 16, &umr_bitfield_default },
+	 { "LD_FLOAT_MODE", 18, 18, &umr_bitfield_default },
+	 { "GATHER4_DX9_MODE", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_POWER_THROTTLE", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_ROUND_TO_ZERO", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_D16_PACKING", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_2BIT_SIGNED_FORMAT", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_STATUS[] = {
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_DSM_CNTL[] = {
+	 { "FORCE_SEDB_0", 0, 0, &umr_bitfield_default },
+	 { "FORCE_SEDB_1", 1, 1, &umr_bitfield_default },
+	 { "EN_SINGLE_WR_SEDB", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CNTL[] = {
+	 { "FX_XNACK_CREDIT", 0, 6, &umr_bitfield_default },
+	 { "SQ_XNACK_CREDIT", 9, 12, &umr_bitfield_default },
+	 { "TC_DATA_CREDIT", 13, 15, &umr_bitfield_default },
+	 { "ALIGNER_CREDIT", 16, 20, &umr_bitfield_default },
+	 { "TD_FIFO_CREDIT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CNTL_AUX[] = {
+	 { "SCOAL_DSWIZZLE_N", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 3, &umr_bitfield_default },
+	 { "D16_PACK_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "ANISO_WEIGHT_MODE", 16, 16, &umr_bitfield_default },
+	 { "ANISO_RATIO_LUT", 17, 17, &umr_bitfield_default },
+	 { "ANISO_TAP", 18, 18, &umr_bitfield_default },
+	 { "ANISO_MIP_ADJ_MODE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_RESERVED_010C[] = {
+	 { "Unused", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_STATUS[] = {
+	 { "FG_PFIFO_EMPTYB", 12, 12, &umr_bitfield_default },
+	 { "FG_LFIFO_EMPTYB", 13, 13, &umr_bitfield_default },
+	 { "FG_SFIFO_EMPTYB", 14, 14, &umr_bitfield_default },
+	 { "FL_PFIFO_EMPTYB", 16, 16, &umr_bitfield_default },
+	 { "FL_LFIFO_EMPTYB", 17, 17, &umr_bitfield_default },
+	 { "FL_SFIFO_EMPTYB", 18, 18, &umr_bitfield_default },
+	 { "FA_PFIFO_EMPTYB", 20, 20, &umr_bitfield_default },
+	 { "FA_LFIFO_EMPTYB", 21, 21, &umr_bitfield_default },
+	 { "FA_SFIFO_EMPTYB", 22, 22, &umr_bitfield_default },
+	 { "IN_BUSY", 24, 24, &umr_bitfield_default },
+	 { "FG_BUSY", 25, 25, &umr_bitfield_default },
+	 { "LA_BUSY", 26, 26, &umr_bitfield_default },
+	 { "FL_BUSY", 27, 27, &umr_bitfield_default },
+	 { "TA_BUSY", 28, 28, &umr_bitfield_default },
+	 { "FA_BUSY", 29, 29, &umr_bitfield_default },
+	 { "AL_BUSY", 30, 30, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_DEBUG_INDEX[] = {
+	 { "INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_SCRATCH[] = {
+	 { "SCRATCH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_HIDDEN_PRIVATE_BASE_VMID[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSH_STATIC_MEM_CONFIG[] = {
+	 { "SWIZZLE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ELEMENT_SIZE", 1, 2, &umr_bitfield_default },
+	 { "INDEX_STRIDE", 3, 4, &umr_bitfield_default },
+	 { "PRIVATE_MTYPE", 5, 7, &umr_bitfield_default },
+	 { "READ_ONLY_CNTL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CONFIG[] = {
+	 { "SH0_GPR_PHASE_SEL", 1, 2, &umr_bitfield_default },
+	 { "SH1_GPR_PHASE_SEL", 3, 4, &umr_bitfield_default },
+	 { "SH2_GPR_PHASE_SEL", 5, 6, &umr_bitfield_default },
+	 { "SH3_GPR_PHASE_SEL", 7, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CNTL_STATUS[] = {
+	 { "GDS_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GRBM_WBUF_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ORD_APP_BUSY", 2, 2, &umr_bitfield_default },
+	 { "DS_BANK_CONFLICT", 3, 3, &umr_bitfield_default },
+	 { "DS_ADDR_CONFLICT", 4, 4, &umr_bitfield_default },
+	 { "DS_WR_CLAMP", 5, 5, &umr_bitfield_default },
+	 { "DS_RD_CLAMP", 6, 6, &umr_bitfield_default },
+	 { "GRBM_RBUF_BUSY", 7, 7, &umr_bitfield_default },
+	 { "DS_BUSY", 8, 8, &umr_bitfield_default },
+	 { "GWS_BUSY", 9, 9, &umr_bitfield_default },
+	 { "ORD_FIFO_BUSY", 10, 10, &umr_bitfield_default },
+	 { "CREDIT_BUSY0", 11, 11, &umr_bitfield_default },
+	 { "CREDIT_BUSY1", 12, 12, &umr_bitfield_default },
+	 { "CREDIT_BUSY2", 13, 13, &umr_bitfield_default },
+	 { "CREDIT_BUSY3", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ENHANCE2[] = {
+	 { "MISC", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PROTECTION_FAULT[] = {
+	 { "WRITE_DIS", 0, 0, &umr_bitfield_default },
+	 { "FAULT_DETECTED", 1, 1, &umr_bitfield_default },
+	 { "GRBM", 2, 2, &umr_bitfield_default },
+	 { "SH_ID", 3, 5, &umr_bitfield_default },
+	 { "CU_ID", 6, 9, &umr_bitfield_default },
+	 { "SIMD_ID", 10, 11, &umr_bitfield_default },
+	 { "WAVE_ID", 12, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VM_PROTECTION_FAULT[] = {
+	 { "WRITE_DIS", 0, 0, &umr_bitfield_default },
+	 { "FAULT_DETECTED", 1, 1, &umr_bitfield_default },
+	 { "GWS", 2, 2, &umr_bitfield_default },
+	 { "OA", 3, 3, &umr_bitfield_default },
+	 { "GRBM", 4, 4, &umr_bitfield_default },
+	 { "VMID", 8, 11, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_EDC_CNT[] = {
+	 { "DED", 0, 7, &umr_bitfield_default },
+	 { "SED", 8, 15, &umr_bitfield_default },
+	 { "SEC", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_EDC_GRBM_CNT[] = {
+	 { "DED", 0, 7, &umr_bitfield_default },
+	 { "SEC", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_EDC_OA_DED[] = {
+	 { "ME0_GFXHP3D_PIX_DED", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_DED", 1, 1, &umr_bitfield_default },
+	 { "ME0_CS_DED", 2, 2, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "ME1_PIPE0_DED", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_DED", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_DED", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_DED", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_DED", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_DED", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_DED", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_DED", 11, 11, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DEBUG_CNTL[] = {
+	 { "GDS_DEBUG_INDX", 0, 4, &umr_bitfield_default },
+	 { "UNUSED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_DSM_CNTL[] = {
+	 { "SEL_DSM_GDS_IRRITATOR_DATA_A_0", 0, 0, &umr_bitfield_default },
+	 { "SEL_DSM_GDS_IRRITATOR_DATA_A_1", 1, 1, &umr_bitfield_default },
+	 { "GDS_ENABLE_SINGLE_WRITE_A", 2, 2, &umr_bitfield_default },
+	 { "SEL_DSM_GDS_IRRITATOR_DATA_B_0", 3, 3, &umr_bitfield_default },
+	 { "SEL_DSM_GDS_IRRITATOR_DATA_B_1", 4, 4, &umr_bitfield_default },
+	 { "GDS_ENABLE_SINGLE_WRITE_B", 5, 5, &umr_bitfield_default },
+	 { "UNUSED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG31[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe0_rtr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_outer_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_inner_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe2_outer_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe2_inner_dr", 5, 5, &umr_bitfield_default },
+	 { "pipe3_outer_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe3_inner_dr", 7, 7, &umr_bitfield_default },
+	 { "pipe4_outer_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe4_inner_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe5_outer_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe5_inner_dr", 11, 11, &umr_bitfield_default },
+	 { "pipe2_outer_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe2_inner_rtr", 13, 13, &umr_bitfield_default },
+	 { "pipe3_outer_rtr", 14, 14, &umr_bitfield_default },
+	 { "pipe3_inner_rtr", 15, 15, &umr_bitfield_default },
+	 { "pipe4_outer_rtr", 16, 16, &umr_bitfield_default },
+	 { "pipe4_inner_rtr", 17, 17, &umr_bitfield_default },
+	 { "pipe5_outer_rtr", 18, 18, &umr_bitfield_default },
+	 { "pipe5_inner_rtr", 19, 19, &umr_bitfield_default },
+	 { "pg_con_outer_point1_rts", 20, 20, &umr_bitfield_default },
+	 { "pg_con_outer_point2_rts", 21, 21, &umr_bitfield_default },
+	 { "pg_con_inner_point1_rts", 22, 22, &umr_bitfield_default },
+	 { "pg_con_inner_point2_rts", 23, 23, &umr_bitfield_default },
+	 { "pg_patch_fifo_empty", 24, 24, &umr_bitfield_default },
+	 { "pg_edge_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "pg_inner3_perp_fifo_empty", 26, 26, &umr_bitfield_default },
+	 { "pg_patch_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "pg_edge_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "pg_inner_perp_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "outer_ring_done_q", 30, 30, &umr_bitfield_default },
+	 { "inner_ring_done_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG[] = {
+	 { "DEBUG_STENCIL_COMPRESS_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_DEPTH_COMPRESS_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "FETCH_FULL_Z_TILE", 2, 2, &umr_bitfield_default },
+	 { "FETCH_FULL_STENCIL_TILE", 3, 3, &umr_bitfield_default },
+	 { "FORCE_Z_MODE", 4, 5, &umr_bitfield_default },
+	 { "DEBUG_FORCE_DEPTH_READ", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_FORCE_STENCIL_READ", 7, 7, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIZ_ENABLE", 8, 9, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE0", 10, 11, &umr_bitfield_default },
+	 { "DEBUG_FORCE_HIS_ENABLE1", 12, 13, &umr_bitfield_default },
+	 { "DEBUG_FAST_Z_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_FAST_STENCIL_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_NOOP_CULL_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_SUMM_SQUADS", 17, 17, &umr_bitfield_default },
+	 { "DEPTH_CACHE_FORCE_MISS", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_FORCE_FULL_Z_RANGE", 19, 20, &umr_bitfield_default },
+	 { "NEVER_FREE_Z_ONLY", 21, 21, &umr_bitfield_default },
+	 { "ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_VPORT_ZPLANE_OPTIMIZATION", 23, 23, &umr_bitfield_default },
+	 { "DECOMPRESS_AFTER_N_ZPLANES", 24, 27, &umr_bitfield_default },
+	 { "ONE_FREE_IN_FLIGHT", 28, 28, &umr_bitfield_default },
+	 { "FORCE_MISS_IF_NOT_INFLIGHT", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_DEPTH_SURFACE_SYNC", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_HTILE_SURFACE_SYNC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG2[] = {
+	 { "ALLOW_COMPZ_BYTE_MASKING", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_TC_ZRANGE_L0_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_TC_MASK_L0_CACHE", 2, 2, &umr_bitfield_default },
+	 { "DTR_ROUND_ROBIN_ARB", 3, 3, &umr_bitfield_default },
+	 { "DTR_PREZ_STALLS_FOR_ETF_ROOM", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_PREZL_CB_STALL", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_PREZL_LPF_STALL_REZ", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_PREZL_CB_STALL_REZ", 8, 8, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 9, 13, &umr_bitfield_default },
+	 { "DISABLE_TILE_COVERED_FOR_PS_ITER", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_SUBTILE_GROUPING", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_HTILE_PAIRED_PIPES", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_NULL_EOT_FORWARDING", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_DTT_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_QUAD_COHERENCY_STALL", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_PREZ_OF_REZ_SUMM", 28, 28, &umr_bitfield_default },
+	 { "DISABLE_PREZL_VIEWPORT_STALL", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_SINGLE_STENCIL_QUAD_SUMM", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_WRITE_STALL_ON_RDWR_CONFLICT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG3[] = {
+	 { "FORCE_DB_IS_GOOD", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_TL_SSO_NULL_SUPPRESSION", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_HIZ_ON_VPORT_CLAMP", 4, 4, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_COMP_Z", 5, 5, &umr_bitfield_default },
+	 { "EQAA_INTERPOLATE_SRC_Z", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_TCP_CAM_BYPASS", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_ZCMP_DIRTY_SUPPRESSION", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_REDUNDANT_PLANE_FLUSHES_OPT", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_INCOHERENT_EQAA_READS", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_OP_Z_DATA_FORWARDING", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_BYPASS", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_WRITE_COMBINE", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_OP_DF_DIRECT_FEEDBACK", 15, 15, &umr_bitfield_default },
+	 { "ALLOW_RF2P_RW_COLLISION", 16, 16, &umr_bitfield_default },
+	 { "SLOW_PREZ_TO_A2M_OMASK_RATE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_OP_S_DATA_FORWARDING", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_TC_UPDATE_WRITE_COMBINE", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_HZ_TC_WRITE_COMBINE", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_TC_MA_ROUND_ROBIN_ARB", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_RAM_READ_SUPPRESION_ON_FWD", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_EQAA_A2M_PERF_OPT", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_DI_DT_STALL", 25, 25, &umr_bitfield_default },
+	 { "ENABLE_DB_PROCESS_RESET", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_OVERRASTERIZATION_FIX", 27, 27, &umr_bitfield_default },
+	 { "DONT_INSERT_CONTEXT_SUSPEND", 28, 28, &umr_bitfield_default },
+	 { "DONT_DELETE_CONTEXT_SUSPEND", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_4XAA_2P_DELAYED_WRITE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_4XAA_2P_INTERLEAVED_PMASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEBUG4[] = {
+	 { "DISABLE_QC_Z_MASK_SUMMATION", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_QC_STENCIL_MASK_SUMMATION", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_RESUMM_TO_SINGLE_STENCIL", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_4XAA_2P_ZD_HOLDOFF", 4, 4, &umr_bitfield_default },
+	 { "ENABLE_A2M_DQUAD_OPTIMIZATION", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_DBCB_SLOW_FORMAT_COLLAPSE", 6, 6, &umr_bitfield_default },
+	 { "DB_EXTRA_DEBUG4", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_CREDIT_LIMIT[] = {
+	 { "DB_SC_TILE_CREDITS", 0, 4, &umr_bitfield_default },
+	 { "DB_SC_QUAD_CREDITS", 5, 9, &umr_bitfield_default },
+	 { "DB_CB_LQUAD_CREDITS", 10, 12, &umr_bitfield_default },
+	 { "DB_CB_TILE_CREDITS", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_WATERMARKS[] = {
+	 { "DEPTH_FREE", 0, 4, &umr_bitfield_default },
+	 { "DEPTH_FLUSH", 5, 10, &umr_bitfield_default },
+	 { "FORCE_SUMMARIZE", 11, 14, &umr_bitfield_default },
+	 { "DEPTH_PENDING_FREE", 15, 19, &umr_bitfield_default },
+	 { "DEPTH_CACHELINE_FREE", 20, 26, &umr_bitfield_default },
+	 { "EARLY_Z_PANIC_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "LATE_Z_PANIC_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "RE_Z_PANIC_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "AUTO_FLUSH_HTILE", 30, 30, &umr_bitfield_default },
+	 { "AUTO_FLUSH_QUAD", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SUBTILE_CONTROL[] = {
+	 { "MSAA1_X", 0, 1, &umr_bitfield_default },
+	 { "MSAA1_Y", 2, 3, &umr_bitfield_default },
+	 { "MSAA2_X", 4, 5, &umr_bitfield_default },
+	 { "MSAA2_Y", 6, 7, &umr_bitfield_default },
+	 { "MSAA4_X", 8, 9, &umr_bitfield_default },
+	 { "MSAA4_Y", 10, 11, &umr_bitfield_default },
+	 { "MSAA8_X", 12, 13, &umr_bitfield_default },
+	 { "MSAA8_Y", 14, 15, &umr_bitfield_default },
+	 { "MSAA16_X", 16, 17, &umr_bitfield_default },
+	 { "MSAA16_Y", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FREE_CACHELINES[] = {
+	 { "FREE_DTILE_DEPTH", 0, 6, &umr_bitfield_default },
+	 { "FREE_PLANE_DEPTH", 7, 13, &umr_bitfield_default },
+	 { "FREE_Z_DEPTH", 14, 20, &umr_bitfield_default },
+	 { "FREE_HTILE_DEPTH", 21, 24, &umr_bitfield_default },
+	 { "QUAD_READ_REQS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FIFO_DEPTH1[] = {
+	 { "MI_RDREQ_FIFO_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "MI_WRREQ_FIFO_DEPTH", 5, 9, &umr_bitfield_default },
+	 { "MCC_DEPTH", 10, 15, &umr_bitfield_default },
+	 { "QC_DEPTH", 16, 20, &umr_bitfield_default },
+	 { "LTILE_PROBE_FIFO_DEPTH", 21, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_FIFO_DEPTH2[] = {
+	 { "EQUAD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "ETILE_OP_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "LQUAD_FIFO_DEPTH", 15, 24, &umr_bitfield_default },
+	 { "LTILE_OP_FIFO_DEPTH", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RING_CONTROL[] = {
+	 { "COUNTER_CONTROL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_0[] = {
+	 { "BUSY_DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_1[] = {
+	 { "BUSY_DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_2[] = {
+	 { "BUSY_DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_3[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_4[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_5[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_6[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_7[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_8[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_9[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_A[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_B[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_C[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_D[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_E[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_READ_DEBUG_F[] = {
+	 { "DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_BACKEND_MAP[] = {
+	 { "BACKEND_MAP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_GPU_ID[] = {
+	 { "GPU_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_RB_DAISY_CHAIN[] = {
+	 { "RB_0", 0, 3, &umr_bitfield_default },
+	 { "RB_1", 4, 7, &umr_bitfield_default },
+	 { "RB_2", 8, 11, &umr_bitfield_default },
+	 { "RB_3", 12, 15, &umr_bitfield_default },
+	 { "RB_4", 16, 19, &umr_bitfield_default },
+	 { "RB_5", 20, 23, &umr_bitfield_default },
+	 { "RB_6", 24, 27, &umr_bitfield_default },
+	 { "RB_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE0[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE1[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE2[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE3[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE4[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE5[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE6[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE7[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE8[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE9[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE10[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE11[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE12[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE13[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE14[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE15[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE16[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE17[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE18[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE19[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE20[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE21[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE22[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE23[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE24[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE25[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE26[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE27[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE28[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE29[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE30[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_TILE_MODE31[] = {
+	 { "ARRAY_MODE", 2, 5, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 6, 10, &umr_bitfield_default },
+	 { "TILE_SPLIT", 11, 13, &umr_bitfield_default },
+	 { "MICRO_TILE_MODE_NEW", 22, 24, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 25, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE0[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE1[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE2[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE3[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE4[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE5[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE6[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE7[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE8[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE9[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE10[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE11[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE12[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE13[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE14[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_MACROTILE_MODE15[] = {
+	 { "BANK_WIDTH", 0, 1, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 2, 3, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 4, 5, &umr_bitfield_default },
+	 { "NUM_BANKS", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_3[] = {
+	 { "DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL", 0, 0, &umr_bitfield_default },
+	 { "RAM_ADDRESS_CONFLICTS_DISALLOWED", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_FAST_CLEAR_FETCH_OPT", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_QUAD_MARKER_DROP_STOP", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_OVERWRITE_COMBINER_CAM_CLR", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_CC_CACHE_OVWR_STATUS_ACCUM", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_CC_CACHE_PANIC_GATING", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION", 8, 8, &umr_bitfield_default },
+	 { "SPLIT_ALL_FAST_MODE_TRANSFERS", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_SHADER_BLEND_OPTS", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CMASK_LAST_QUAD_INSERTION", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_ROP3_FIXES_OF_BUG_511967", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_ROP3_FIXES_OF_BUG_520657", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL[] = {
+	 { "CM_CACHE_EVICT_POINT", 0, 3, &umr_bitfield_default },
+	 { "FC_CACHE_EVICT_POINT", 6, 9, &umr_bitfield_default },
+	 { "CC_CACHE_EVICT_POINT", 12, 15, &umr_bitfield_default },
+	 { "ALLOW_MRT_WITH_DUAL_SOURCE", 16, 16, &umr_bitfield_default },
+	 { "DISABLE_INTNORM_LE11BPC_CLAMPING", 18, 18, &umr_bitfield_default },
+	 { "FORCE_NEEDS_DST", 19, 19, &umr_bitfield_default },
+	 { "FORCE_ALWAYS_TOGGLE", 20, 20, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_RESULT_EQ_DEST", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_FULL_WRITE_MASK", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG", 23, 23, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DONT_RD_DST", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_BYPASS", 25, 25, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_DISCARD_PIXEL", 26, 26, &umr_bitfield_default },
+	 { "DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED", 27, 27, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT", 28, 28, &umr_bitfield_default },
+	 { "PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_CC_IB_SERIALIZER_STATE_OPT", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_1[] = {
+	 { "CM_CACHE_NUM_TAGS", 0, 4, &umr_bitfield_default },
+	 { "FC_CACHE_NUM_TAGS", 5, 10, &umr_bitfield_default },
+	 { "CC_CACHE_NUM_TAGS", 11, 16, &umr_bitfield_default },
+	 { "CM_TILE_FIFO_DEPTH", 17, 25, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_HW_CONTROL_2[] = {
+	 { "CC_EVEN_ODD_FIFO_DEPTH", 0, 7, &umr_bitfield_default },
+	 { "FC_RDLAT_TILE_FIFO_DEPTH", 8, 14, &umr_bitfield_default },
+	 { "FC_RDLAT_QUAD_FIFO_DEPTH", 15, 22, &umr_bitfield_default },
+	 { "DRR_ASSUMED_FIFO_DEPTH_DIV8", 24, 27, &umr_bitfield_default },
+	 { "CHICKEN_BITS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DCC_CONFIG[] = {
+	 { "OVERWRITE_COMBINER_DEPTH", 0, 4, &umr_bitfield_default },
+	 { "OVERWRITE_COMBINER_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "OVERWRITE_COMBINER_CC_POP_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "FC_RDLAT_KEYID_FIFO_DEPTH", 8, 15, &umr_bitfield_default },
+	 { "READ_RETURN_SKID_FIFO_DEPTH", 16, 22, &umr_bitfield_default },
+	 { "DCC_CACHE_EVICT_POINT", 24, 27, &umr_bitfield_default },
+	 { "DCC_CACHE_NUM_TAGS", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_1[] = {
+	 { "CB_BUSY", 0, 0, &umr_bitfield_default },
+	 { "DB_CB_TILE_VALID_READY", 1, 1, &umr_bitfield_default },
+	 { "DB_CB_TILE_VALID_READYB", 2, 2, &umr_bitfield_default },
+	 { "DB_CB_TILE_VALIDB_READY", 3, 3, &umr_bitfield_default },
+	 { "DB_CB_TILE_VALIDB_READYB", 4, 4, &umr_bitfield_default },
+	 { "DB_CB_LQUAD_VALID_READY", 5, 5, &umr_bitfield_default },
+	 { "DB_CB_LQUAD_VALID_READYB", 6, 6, &umr_bitfield_default },
+	 { "DB_CB_LQUAD_VALIDB_READY", 7, 7, &umr_bitfield_default },
+	 { "DB_CB_LQUAD_VALIDB_READYB", 8, 8, &umr_bitfield_default },
+	 { "CB_TAP_WRREQ_VALID_READY", 9, 9, &umr_bitfield_default },
+	 { "CB_TAP_WRREQ_VALID_READYB", 10, 10, &umr_bitfield_default },
+	 { "CB_TAP_WRREQ_VALIDB_READY", 11, 11, &umr_bitfield_default },
+	 { "CB_TAP_WRREQ_VALIDB_READYB", 12, 12, &umr_bitfield_default },
+	 { "CB_TAP_RDREQ_VALID_READY", 13, 13, &umr_bitfield_default },
+	 { "CB_TAP_RDREQ_VALID_READYB", 14, 14, &umr_bitfield_default },
+	 { "CB_TAP_RDREQ_VALIDB_READY", 15, 15, &umr_bitfield_default },
+	 { "CB_TAP_RDREQ_VALIDB_READYB", 16, 16, &umr_bitfield_default },
+	 { "CM_FC_TILE_VALID_READY", 17, 17, &umr_bitfield_default },
+	 { "CM_FC_TILE_VALID_READYB", 18, 18, &umr_bitfield_default },
+	 { "CM_FC_TILE_VALIDB_READY", 19, 19, &umr_bitfield_default },
+	 { "CM_FC_TILE_VALIDB_READYB", 20, 20, &umr_bitfield_default },
+	 { "FC_CLEAR_QUAD_VALID_READY", 21, 21, &umr_bitfield_default },
+	 { "FC_CLEAR_QUAD_VALID_READYB", 22, 22, &umr_bitfield_default },
+	 { "FC_CLEAR_QUAD_VALIDB_READY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_2[] = {
+	 { "FC_CLEAR_QUAD_VALIDB_READYB", 0, 0, &umr_bitfield_default },
+	 { "FC_QUAD_RESIDENCY_STALL", 1, 1, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_VALID_READY", 2, 2, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_VALID_READYB", 3, 3, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_VALIDB_READY", 4, 4, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_VALIDB_READYB", 5, 5, &umr_bitfield_default },
+	 { "FOP_IN_VALID_READY", 6, 6, &umr_bitfield_default },
+	 { "FOP_IN_VALID_READYB", 7, 7, &umr_bitfield_default },
+	 { "FOP_IN_VALIDB_READY", 8, 8, &umr_bitfield_default },
+	 { "FOP_IN_VALIDB_READYB", 9, 9, &umr_bitfield_default },
+	 { "FOP_FMASK_RAW_STALL", 10, 10, &umr_bitfield_default },
+	 { "FOP_FMASK_BYPASS_STALL", 11, 11, &umr_bitfield_default },
+	 { "CC_IB_TB_FRAG_VALID_READY", 12, 12, &umr_bitfield_default },
+	 { "CC_IB_TB_FRAG_VALID_READYB", 13, 13, &umr_bitfield_default },
+	 { "CC_IB_TB_FRAG_VALIDB_READY", 14, 14, &umr_bitfield_default },
+	 { "CC_IB_TB_FRAG_VALIDB_READYB", 15, 15, &umr_bitfield_default },
+	 { "CC_IB_SR_FRAG_VALID_READY", 16, 16, &umr_bitfield_default },
+	 { "CC_IB_SR_FRAG_VALID_READYB", 17, 17, &umr_bitfield_default },
+	 { "CC_IB_SR_FRAG_VALIDB_READY", 18, 18, &umr_bitfield_default },
+	 { "CC_IB_SR_FRAG_VALIDB_READYB", 19, 19, &umr_bitfield_default },
+	 { "CC_RB_BC_EVENFRAG_VALID_READY", 20, 20, &umr_bitfield_default },
+	 { "CC_RB_BC_EVENFRAG_VALID_READYB", 21, 21, &umr_bitfield_default },
+	 { "CC_RB_BC_EVENFRAG_VALIDB_READY", 22, 22, &umr_bitfield_default },
+	 { "CC_RB_BC_EVENFRAG_VALIDB_READYB", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_3[] = {
+	 { "CC_RB_BC_ODDFRAG_VALID_READY", 0, 0, &umr_bitfield_default },
+	 { "CC_RB_BC_ODDFRAG_VALID_READYB", 1, 1, &umr_bitfield_default },
+	 { "CC_RB_BC_ODDFRAG_VALIDB_READY", 2, 2, &umr_bitfield_default },
+	 { "CC_RB_BC_ODDFRAG_VALIDB_READYB", 3, 3, &umr_bitfield_default },
+	 { "CC_BC_CS_FRAG_VALID", 4, 4, &umr_bitfield_default },
+	 { "CC_SF_FULL", 5, 5, &umr_bitfield_default },
+	 { "CC_RB_FULL", 6, 6, &umr_bitfield_default },
+	 { "CC_EVENFIFO_QUAD_RESIDENCY_STALL", 7, 7, &umr_bitfield_default },
+	 { "CC_ODDFIFO_QUAD_RESIDENCY_STALL", 8, 8, &umr_bitfield_default },
+	 { "CM_TQ_FULL", 9, 9, &umr_bitfield_default },
+	 { "CM_TILE_RESIDENCY_STALL", 10, 10, &umr_bitfield_default },
+	 { "LQUAD_NO_TILE", 11, 11, &umr_bitfield_default },
+	 { "LQUAD_FORMAT_IS_EXPORT_32_R", 12, 12, &umr_bitfield_default },
+	 { "LQUAD_FORMAT_IS_EXPORT_32_AR", 13, 13, &umr_bitfield_default },
+	 { "LQUAD_FORMAT_IS_EXPORT_32_GR", 14, 14, &umr_bitfield_default },
+	 { "LQUAD_FORMAT_IS_EXPORT_32_ABGR", 15, 15, &umr_bitfield_default },
+	 { "LQUAD_FORMAT_IS_EXPORT_FP16_ABGR", 16, 16, &umr_bitfield_default },
+	 { "LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR", 17, 17, &umr_bitfield_default },
+	 { "LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR", 18, 18, &umr_bitfield_default },
+	 { "CM_CACHE_HIT", 19, 19, &umr_bitfield_default },
+	 { "CM_CACHE_TAG_MISS", 20, 20, &umr_bitfield_default },
+	 { "CM_CACHE_SECTOR_MISS", 21, 21, &umr_bitfield_default },
+	 { "CM_CACHE_REEVICTION_STALL", 22, 22, &umr_bitfield_default },
+	 { "CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_4[] = {
+	 { "CM_CACHE_REPLACE_PENDING_EVICT_STALL", 0, 0, &umr_bitfield_default },
+	 { "CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL", 1, 1, &umr_bitfield_default },
+	 { "CM_CACHE_READ_OUTPUT_STALL", 2, 2, &umr_bitfield_default },
+	 { "CM_CACHE_WRITE_OUTPUT_STALL", 3, 3, &umr_bitfield_default },
+	 { "CM_CACHE_ACK_OUTPUT_STALL", 4, 4, &umr_bitfield_default },
+	 { "CM_CACHE_STALL", 5, 5, &umr_bitfield_default },
+	 { "FC_CACHE_HIT", 6, 6, &umr_bitfield_default },
+	 { "FC_CACHE_TAG_MISS", 7, 7, &umr_bitfield_default },
+	 { "FC_CACHE_SECTOR_MISS", 8, 8, &umr_bitfield_default },
+	 { "FC_CACHE_REEVICTION_STALL", 9, 9, &umr_bitfield_default },
+	 { "FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL", 10, 10, &umr_bitfield_default },
+	 { "FC_CACHE_REPLACE_PENDING_EVICT_STALL", 11, 11, &umr_bitfield_default },
+	 { "FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL", 12, 12, &umr_bitfield_default },
+	 { "FC_CACHE_READ_OUTPUT_STALL", 13, 13, &umr_bitfield_default },
+	 { "FC_CACHE_WRITE_OUTPUT_STALL", 14, 14, &umr_bitfield_default },
+	 { "FC_CACHE_ACK_OUTPUT_STALL", 15, 15, &umr_bitfield_default },
+	 { "FC_CACHE_STALL", 16, 16, &umr_bitfield_default },
+	 { "CC_CACHE_HIT", 17, 17, &umr_bitfield_default },
+	 { "CC_CACHE_TAG_MISS", 18, 18, &umr_bitfield_default },
+	 { "CC_CACHE_SECTOR_MISS", 19, 19, &umr_bitfield_default },
+	 { "CC_CACHE_REEVICTION_STALL", 20, 20, &umr_bitfield_default },
+	 { "CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL", 21, 21, &umr_bitfield_default },
+	 { "CC_CACHE_REPLACE_PENDING_EVICT_STALL", 22, 22, &umr_bitfield_default },
+	 { "CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_5[] = {
+	 { "CC_CACHE_READ_OUTPUT_STALL", 0, 0, &umr_bitfield_default },
+	 { "CC_CACHE_WRITE_OUTPUT_STALL", 1, 1, &umr_bitfield_default },
+	 { "CC_CACHE_ACK_OUTPUT_STALL", 2, 2, &umr_bitfield_default },
+	 { "CC_CACHE_STALL", 3, 3, &umr_bitfield_default },
+	 { "CC_CACHE_WA_TO_RMW_CONVERSION", 4, 4, &umr_bitfield_default },
+	 { "CM_CACHE_FLUSH", 5, 5, &umr_bitfield_default },
+	 { "CM_CACHE_TAGS_FLUSHED", 6, 6, &umr_bitfield_default },
+	 { "CM_CACHE_SECTORS_FLUSHED", 7, 7, &umr_bitfield_default },
+	 { "CM_CACHE_DIRTY_SECTORS_FLUSHED", 8, 8, &umr_bitfield_default },
+	 { "FC_CACHE_FLUSH", 9, 9, &umr_bitfield_default },
+	 { "FC_CACHE_TAGS_FLUSHED", 10, 10, &umr_bitfield_default },
+	 { "FC_CACHE_SECTORS_FLUSHED", 11, 13, &umr_bitfield_default },
+	 { "FC_CACHE_DIRTY_SECTORS_FLUSHED", 14, 16, &umr_bitfield_default },
+	 { "CC_CACHE_FLUSH", 17, 17, &umr_bitfield_default },
+	 { "CC_CACHE_TAGS_FLUSHED", 18, 18, &umr_bitfield_default },
+	 { "CC_CACHE_SECTORS_FLUSHED", 19, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_6[] = {
+	 { "CC_CACHE_DIRTY_SECTORS_FLUSHED", 0, 2, &umr_bitfield_default },
+	 { "CM_MC_READ_REQUEST", 3, 3, &umr_bitfield_default },
+	 { "FC_MC_READ_REQUEST", 4, 4, &umr_bitfield_default },
+	 { "CC_MC_READ_REQUEST", 5, 5, &umr_bitfield_default },
+	 { "CM_MC_WRITE_REQUEST", 6, 6, &umr_bitfield_default },
+	 { "FC_MC_WRITE_REQUEST", 7, 7, &umr_bitfield_default },
+	 { "CC_MC_WRITE_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "CM_MC_READ_REQUESTS_IN_FLIGHT", 9, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_7[] = {
+	 { "FC_MC_READ_REQUESTS_IN_FLIGHT", 0, 10, &umr_bitfield_default },
+	 { "CC_MC_READ_REQUESTS_IN_FLIGHT", 11, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_8[] = {
+	 { "CM_MC_WRITE_REQUESTS_IN_FLIGHT", 0, 7, &umr_bitfield_default },
+	 { "FC_MC_WRITE_REQUESTS_IN_FLIGHT", 8, 18, &umr_bitfield_default },
+	 { "FC_SEQUENCER_FMASK_COMPRESSION_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "FC_SEQUENCER_FMASK_DECOMPRESS", 20, 20, &umr_bitfield_default },
+	 { "FC_SEQUENCER_ELIMINATE_FAST_CLEAR", 21, 21, &umr_bitfield_default },
+	 { "FC_SEQUENCER_CLEAR", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_9[] = {
+	 { "CC_MC_WRITE_REQUESTS_IN_FLIGHT", 0, 9, &umr_bitfield_default },
+	 { "CC_SURFACE_SYNC", 10, 10, &umr_bitfield_default },
+	 { "TWO_PROBE_QUAD_FRAGMENT", 11, 11, &umr_bitfield_default },
+	 { "EXPORT_32_ABGR_QUAD_FRAGMENT", 12, 12, &umr_bitfield_default },
+	 { "DUAL_SOURCE_COLOR_QUAD_FRAGMENT", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_BUS_DRAWN_QUAD", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_BUS_DRAWN_PIXEL", 15, 18, &umr_bitfield_default },
+	 { "DEBUG_BUS_DRAWN_QUAD_FRAGMENT", 19, 19, &umr_bitfield_default },
+	 { "DEBUG_BUS_DRAWN_TILE", 20, 20, &umr_bitfield_default },
+	 { "EVENT_ALL", 21, 21, &umr_bitfield_default },
+	 { "EVENT_CACHE_FLUSH_TS", 22, 22, &umr_bitfield_default },
+	 { "EVENT_CONTEXT_DONE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_10[] = {
+	 { "EVENT_CACHE_FLUSH", 0, 0, &umr_bitfield_default },
+	 { "EVENT_CACHE_FLUSH_AND_INV_TS_EVENT", 1, 1, &umr_bitfield_default },
+	 { "EVENT_CACHE_FLUSH_AND_INV_EVENT", 2, 2, &umr_bitfield_default },
+	 { "EVENT_FLUSH_AND_INV_CB_DATA_TS", 3, 3, &umr_bitfield_default },
+	 { "EVENT_FLUSH_AND_INV_CB_META", 4, 4, &umr_bitfield_default },
+	 { "CMASK_READ_DATA_0XC", 5, 5, &umr_bitfield_default },
+	 { "CMASK_READ_DATA_0XD", 6, 6, &umr_bitfield_default },
+	 { "CMASK_READ_DATA_0XE", 7, 7, &umr_bitfield_default },
+	 { "CMASK_READ_DATA_0XF", 8, 8, &umr_bitfield_default },
+	 { "CMASK_WRITE_DATA_0XC", 9, 9, &umr_bitfield_default },
+	 { "CMASK_WRITE_DATA_0XD", 10, 10, &umr_bitfield_default },
+	 { "CMASK_WRITE_DATA_0XE", 11, 11, &umr_bitfield_default },
+	 { "CMASK_WRITE_DATA_0XF", 12, 12, &umr_bitfield_default },
+	 { "CORE_SCLK_VLD", 13, 13, &umr_bitfield_default },
+	 { "REG_SCLK0_VLD", 14, 14, &umr_bitfield_default },
+	 { "REG_SCLK1_VLD", 15, 15, &umr_bitfield_default },
+	 { "MERGE_TILE_ONLY_VALID_READY", 16, 16, &umr_bitfield_default },
+	 { "MERGE_TILE_ONLY_VALID_READYB", 17, 17, &umr_bitfield_default },
+	 { "FC_QUAD_RDLAT_FIFO_FULL", 18, 18, &umr_bitfield_default },
+	 { "FC_TILE_RDLAT_FIFO_FULL", 19, 19, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE", 20, 20, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE", 21, 21, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE", 22, 22, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_11[] = {
+	 { "FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE", 0, 0, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE", 1, 1, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE", 2, 2, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE", 3, 3, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE", 4, 4, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE", 5, 5, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE", 6, 6, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE", 7, 7, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE", 8, 8, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE", 9, 9, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE", 10, 10, &umr_bitfield_default },
+	 { "FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "FOP_QUAD_ADDED_1_FRAGMENT", 12, 12, &umr_bitfield_default },
+	 { "FOP_QUAD_ADDED_2_FRAGMENTS", 13, 13, &umr_bitfield_default },
+	 { "FOP_QUAD_ADDED_3_FRAGMENTS", 14, 14, &umr_bitfield_default },
+	 { "FOP_QUAD_ADDED_4_FRAGMENTS", 15, 15, &umr_bitfield_default },
+	 { "FOP_QUAD_ADDED_5_FRAGMENTS", 16, 16, &umr_bitfield_default },
+	 { "FOP_QUAD_ADDED_6_FRAGMENTS", 17, 17, &umr_bitfield_default },
+	 { "FOP_QUAD_ADDED_7_FRAGMENTS", 18, 18, &umr_bitfield_default },
+	 { "FOP_QUAD_REMOVED_1_FRAGMENT", 19, 19, &umr_bitfield_default },
+	 { "FOP_QUAD_REMOVED_2_FRAGMENTS", 20, 20, &umr_bitfield_default },
+	 { "FOP_QUAD_REMOVED_3_FRAGMENTS", 21, 21, &umr_bitfield_default },
+	 { "FOP_QUAD_REMOVED_4_FRAGMENTS", 22, 22, &umr_bitfield_default },
+	 { "FOP_QUAD_REMOVED_5_FRAGMENTS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_12[] = {
+	 { "FOP_QUAD_REMOVED_6_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "FOP_QUAD_REMOVED_7_FRAGMENTS", 1, 1, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_READS_FRAGMENT_0", 2, 2, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_READS_FRAGMENT_1", 3, 3, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_READS_FRAGMENT_2", 4, 4, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_READS_FRAGMENT_3", 5, 5, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_READS_FRAGMENT_4", 6, 6, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_READS_FRAGMENT_5", 7, 7, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_READS_FRAGMENT_6", 8, 8, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_READS_FRAGMENT_7", 9, 9, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_WRITES_FRAGMENT_0", 10, 10, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_WRITES_FRAGMENT_1", 11, 11, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_WRITES_FRAGMENT_2", 12, 12, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_WRITES_FRAGMENT_3", 13, 13, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_WRITES_FRAGMENT_4", 14, 14, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_WRITES_FRAGMENT_5", 15, 15, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_WRITES_FRAGMENT_6", 16, 16, &umr_bitfield_default },
+	 { "FC_CC_QUADFRAG_WRITES_FRAGMENT_7", 17, 17, &umr_bitfield_default },
+	 { "FC_QUAD_BLEND_OPT_DONT_READ_DST", 18, 18, &umr_bitfield_default },
+	 { "FC_QUAD_BLEND_OPT_BLEND_BYPASS", 19, 19, &umr_bitfield_default },
+	 { "FC_QUAD_BLEND_OPT_DISCARD_PIXELS", 20, 20, &umr_bitfield_default },
+	 { "FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT", 21, 21, &umr_bitfield_default },
+	 { "FC_QUAD_KILLED_BY_COLOR_INVALID", 22, 22, &umr_bitfield_default },
+	 { "FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_13[] = {
+	 { "FC_PF_FC_KEYID_RDLAT_FIFO_FULL", 0, 0, &umr_bitfield_default },
+	 { "FC_DOC_QTILE_CAM_MISS", 1, 1, &umr_bitfield_default },
+	 { "FC_DOC_QTILE_CAM_HIT", 2, 2, &umr_bitfield_default },
+	 { "FC_DOC_CLINE_CAM_MISS", 3, 3, &umr_bitfield_default },
+	 { "FC_DOC_CLINE_CAM_HIT", 4, 4, &umr_bitfield_default },
+	 { "FC_DOC_OVERWROTE_1_SECTOR", 5, 5, &umr_bitfield_default },
+	 { "FC_DOC_OVERWROTE_2_SECTORS", 6, 6, &umr_bitfield_default },
+	 { "FC_DOC_OVERWROTE_3_SECTORS", 7, 7, &umr_bitfield_default },
+	 { "FC_DOC_OVERWROTE_4_SECTORS", 8, 8, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_HIT", 9, 9, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_TAG_MISS", 10, 10, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_SECTOR_MISS", 11, 11, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_REEVICTION_STALL", 12, 12, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL", 13, 13, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL", 14, 14, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL", 15, 15, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_READ_OUTPUT_STALL", 16, 16, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL", 17, 17, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_ACK_OUTPUT_STALL", 18, 18, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_STALL", 19, 19, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_FLUSH", 20, 20, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_SECTORS_FLUSHED", 21, 21, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED", 22, 22, &umr_bitfield_default },
+	 { "FC_PF_DCC_CACHE_TAGS_FLUSHED", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_14[] = {
+	 { "FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT", 0, 10, &umr_bitfield_default },
+	 { "FC_MC_DCC_READ_REQUESTS_IN_FLIGHT", 11, 21, &umr_bitfield_default },
+	 { "CC_PF_DCC_BEYOND_TILE_SPLIT", 22, 22, &umr_bitfield_default },
+	 { "CC_PF_DCC_RDREQ_STALL", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_15[] = {
+	 { "CC_PF_DCC_COMPRESS_RATIO_2TO1", 0, 2, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_4TO1", 3, 4, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_4TO2", 5, 6, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_4TO3", 7, 8, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_6TO1", 9, 10, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_6TO2", 11, 12, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_6TO3", 13, 14, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_6TO4", 15, 16, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_6TO5", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_16[] = {
+	 { "CC_PF_DCC_COMPRESS_RATIO_8TO1", 0, 0, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_8TO2", 1, 1, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_8TO3", 2, 2, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_8TO4", 3, 3, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_8TO5", 4, 4, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_8TO6", 5, 5, &umr_bitfield_default },
+	 { "CC_PF_DCC_COMPRESS_RATIO_8TO7", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_17[] = {
+	 { "TILE_INTFC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MU_BUSY", 1, 1, &umr_bitfield_default },
+	 { "TQ_BUSY", 2, 2, &umr_bitfield_default },
+	 { "AC_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CRW_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CACHE_CTRL_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MC_WR_PENDING", 6, 6, &umr_bitfield_default },
+	 { "FC_WR_PENDING", 7, 7, &umr_bitfield_default },
+	 { "FC_RD_PENDING", 8, 8, &umr_bitfield_default },
+	 { "EVICT_PENDING", 9, 9, &umr_bitfield_default },
+	 { "LAST_RD_ARB_WINNER", 10, 10, &umr_bitfield_default },
+	 { "MU_STATE", 11, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_18[] = {
+	 { "TILE_RETIREMENT_BUSY", 0, 0, &umr_bitfield_default },
+	 { "FOP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_BUSY", 2, 2, &umr_bitfield_default },
+	 { "LAT_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CACHE_CTL_BUSY", 4, 4, &umr_bitfield_default },
+	 { "ADDR_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MERGE_BUSY", 6, 6, &umr_bitfield_default },
+	 { "QUAD_BUSY", 7, 7, &umr_bitfield_default },
+	 { "TILE_BUSY", 8, 8, &umr_bitfield_default },
+	 { "DCC_BUSY", 9, 9, &umr_bitfield_default },
+	 { "DOC_BUSY", 10, 10, &umr_bitfield_default },
+	 { "DAG_BUSY", 11, 11, &umr_bitfield_default },
+	 { "DOC_STALL", 12, 12, &umr_bitfield_default },
+	 { "DOC_QT_CAM_FULL", 13, 13, &umr_bitfield_default },
+	 { "DOC_CL_CAM_FULL", 14, 14, &umr_bitfield_default },
+	 { "DOC_QUAD_PTR_FIFO_FULL", 15, 15, &umr_bitfield_default },
+	 { "DOC_SECTOR_MASK_FIFO_FULL", 16, 16, &umr_bitfield_default },
+	 { "DCS_READ_WINNER_LAST", 17, 17, &umr_bitfield_default },
+	 { "DCS_READ_EV_PENDING", 18, 18, &umr_bitfield_default },
+	 { "DCS_WRITE_CC_PENDING", 19, 19, &umr_bitfield_default },
+	 { "DCS_READ_CC_PENDING", 20, 20, &umr_bitfield_default },
+	 { "DCS_WRITE_MC_PENDING", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_19[] = {
+	 { "SURF_SYNC_STATE", 0, 1, &umr_bitfield_default },
+	 { "SURF_SYNC_START", 2, 2, &umr_bitfield_default },
+	 { "SF_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CS_BUSY", 4, 4, &umr_bitfield_default },
+	 { "RB_BUSY", 5, 5, &umr_bitfield_default },
+	 { "DS_BUSY", 6, 6, &umr_bitfield_default },
+	 { "TB_BUSY", 7, 7, &umr_bitfield_default },
+	 { "IB_BUSY", 8, 8, &umr_bitfield_default },
+	 { "DRR_BUSY", 9, 9, &umr_bitfield_default },
+	 { "DF_BUSY", 10, 10, &umr_bitfield_default },
+	 { "DD_BUSY", 11, 11, &umr_bitfield_default },
+	 { "DC_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DK_BUSY", 13, 13, &umr_bitfield_default },
+	 { "DF_SKID_FIFO_EMPTY", 14, 14, &umr_bitfield_default },
+	 { "DF_CLEAR_FIFO_EMPTY", 15, 15, &umr_bitfield_default },
+	 { "DD_READY", 16, 16, &umr_bitfield_default },
+	 { "DC_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "DC_READY", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_20[] = {
+	 { "MC_RDREQ_CREDITS", 0, 5, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDITS", 6, 11, &umr_bitfield_default },
+	 { "CC_RDREQ_HAD_ITS_TURN", 12, 12, &umr_bitfield_default },
+	 { "FC_RDREQ_HAD_ITS_TURN", 13, 13, &umr_bitfield_default },
+	 { "CM_RDREQ_HAD_ITS_TURN", 14, 14, &umr_bitfield_default },
+	 { "CC_WRREQ_HAD_ITS_TURN", 16, 16, &umr_bitfield_default },
+	 { "FC_WRREQ_HAD_ITS_TURN", 17, 17, &umr_bitfield_default },
+	 { "CM_WRREQ_HAD_ITS_TURN", 18, 18, &umr_bitfield_default },
+	 { "CC_WRREQ_FIFO_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "FC_WRREQ_FIFO_EMPTY", 21, 21, &umr_bitfield_default },
+	 { "CM_WRREQ_FIFO_EMPTY", 22, 22, &umr_bitfield_default },
+	 { "DCC_WRREQ_FIFO_EMPTY", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_21[] = {
+	 { "CM_BUSY", 0, 0, &umr_bitfield_default },
+	 { "FC_BUSY", 1, 1, &umr_bitfield_default },
+	 { "CC_BUSY", 2, 2, &umr_bitfield_default },
+	 { "BB_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MA_BUSY", 4, 4, &umr_bitfield_default },
+	 { "CORE_SCLK_VLD", 5, 5, &umr_bitfield_default },
+	 { "REG_SCLK1_VLD", 6, 6, &umr_bitfield_default },
+	 { "REG_SCLK0_VLD", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DEBUG_BUS_22[] = {
+	 { "OUTSTANDING_MC_READS", 0, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_MC_WRITES", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TBA_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TBA_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TMA_LO[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TMA_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG32[] = {
+	 { "first_ring_of_patch", 0, 0, &umr_bitfield_default },
+	 { "last_ring_of_patch", 1, 1, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring", 2, 2, &umr_bitfield_default },
+	 { "last_point_of_outer_edge", 3, 3, &umr_bitfield_default },
+	 { "last_edge_of_inner_ring", 4, 4, &umr_bitfield_default },
+	 { "last_point_of_inner_edge", 5, 5, &umr_bitfield_default },
+	 { "last_patch_of_tg_p0_q", 6, 6, &umr_bitfield_default },
+	 { "event_null_special_p0_q", 7, 7, &umr_bitfield_default },
+	 { "event_flag_p5_q", 8, 8, &umr_bitfield_default },
+	 { "first_point_of_patch_p5_q", 9, 9, &umr_bitfield_default },
+	 { "first_point_of_edge_p5_q", 10, 10, &umr_bitfield_default },
+	 { "last_patch_of_tg_p5_q", 11, 11, &umr_bitfield_default },
+	 { "tess_topology_p5_q", 12, 13, &umr_bitfield_default },
+	 { "pipe5_inner3_rtr", 14, 14, &umr_bitfield_default },
+	 { "pipe5_inner2_rtr", 15, 15, &umr_bitfield_default },
+	 { "pg_edge_fifo3_full", 16, 16, &umr_bitfield_default },
+	 { "pg_edge_fifo2_full", 17, 17, &umr_bitfield_default },
+	 { "pg_inner3_point_fifo_full", 18, 18, &umr_bitfield_default },
+	 { "pg_outer3_point_fifo_full", 19, 19, &umr_bitfield_default },
+	 { "pg_inner2_point_fifo_full", 20, 20, &umr_bitfield_default },
+	 { "pg_outer2_point_fifo_full", 21, 21, &umr_bitfield_default },
+	 { "pg_inner_point_fifo_full", 22, 22, &umr_bitfield_default },
+	 { "pg_outer_point_fifo_full", 23, 23, &umr_bitfield_default },
+	 { "inner2_fifos_rtr", 24, 24, &umr_bitfield_default },
+	 { "inner_fifos_rtr", 25, 25, &umr_bitfield_default },
+	 { "outer_fifos_rtr", 26, 26, &umr_bitfield_default },
+	 { "fifos_rtr", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_TTMP11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_M0[] = {
+	 { "M0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_EXEC_LO[] = {
+	 { "EXEC_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_WAVE_EXEC_HI[] = {
+	 { "EXEC_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG33[] = {
+	 { "pipe0_patch_dr", 0, 0, &umr_bitfield_default },
+	 { "ring3_pipe1_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe2_dr", 3, 3, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 4, 4, &umr_bitfield_default },
+	 { "ring2_pipe1_dr", 5, 5, &umr_bitfield_default },
+	 { "ring1_pipe1_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe2_rtr", 7, 7, &umr_bitfield_default },
+	 { "pipe3_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe3_rtr", 9, 9, &umr_bitfield_default },
+	 { "ring2_in_sync_q", 10, 10, &umr_bitfield_default },
+	 { "ring1_in_sync_q", 11, 11, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 12, 12, &umr_bitfield_default },
+	 { "ring3_in_sync_q", 13, 13, &umr_bitfield_default },
+	 { "tm_te11_event_rtr", 14, 14, &umr_bitfield_default },
+	 { "first_prim_of_patch_q", 15, 15, &umr_bitfield_default },
+	 { "con_prim_fifo_full", 16, 16, &umr_bitfield_default },
+	 { "con_vert_fifo_full", 17, 17, &umr_bitfield_default },
+	 { "con_prim_fifo_empty", 18, 18, &umr_bitfield_default },
+	 { "con_vert_fifo_empty", 19, 19, &umr_bitfield_default },
+	 { "last_patch_of_tg_p0_q", 20, 20, &umr_bitfield_default },
+	 { "ring3_valid_p2", 21, 21, &umr_bitfield_default },
+	 { "ring2_valid_p2", 22, 22, &umr_bitfield_default },
+	 { "ring1_valid_p2", 23, 23, &umr_bitfield_default },
+	 { "tess_type_p0_q", 24, 25, &umr_bitfield_default },
+	 { "tess_topology_p0_q", 26, 27, &umr_bitfield_default },
+	 { "te11_out_vert_gs_en", 28, 28, &umr_bitfield_default },
+	 { "con_ring3_busy", 29, 29, &umr_bitfield_default },
+	 { "con_ring2_busy", 30, 30, &umr_bitfield_default },
+	 { "con_ring1_busy", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG34[] = {
+	 { "con_state_q", 0, 3, &umr_bitfield_default },
+	 { "second_cycle_q", 4, 4, &umr_bitfield_default },
+	 { "process_tri_middle_p0_q", 5, 5, &umr_bitfield_default },
+	 { "process_tri_1st_2nd_half_p0_q", 6, 6, &umr_bitfield_default },
+	 { "process_tri_center_poly_p0_q", 7, 7, &umr_bitfield_default },
+	 { "pipe0_patch_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe0_edge_dr", 9, 9, &umr_bitfield_default },
+	 { "pipe1_dr", 10, 10, &umr_bitfield_default },
+	 { "pipe0_patch_rtr", 11, 11, &umr_bitfield_default },
+	 { "pipe0_edge_rtr", 12, 12, &umr_bitfield_default },
+	 { "pipe1_rtr", 13, 13, &umr_bitfield_default },
+	 { "outer_parity_p0_q", 14, 14, &umr_bitfield_default },
+	 { "parallel_parity_p0_q", 15, 15, &umr_bitfield_default },
+	 { "first_ring_of_patch_p0_q", 16, 16, &umr_bitfield_default },
+	 { "last_ring_of_patch_p0_q", 17, 17, &umr_bitfield_default },
+	 { "last_edge_of_outer_ring_p0_q", 18, 18, &umr_bitfield_default },
+	 { "last_point_of_outer_ring_p1", 19, 19, &umr_bitfield_default },
+	 { "last_point_of_inner_ring_p1", 20, 20, &umr_bitfield_default },
+	 { "outer_edge_tf_eq_one_p0_q", 21, 21, &umr_bitfield_default },
+	 { "advance_outer_point_p1", 22, 22, &umr_bitfield_default },
+	 { "advance_inner_point_p1", 23, 23, &umr_bitfield_default },
+	 { "next_ring_is_rect_p0_q", 24, 24, &umr_bitfield_default },
+	 { "pipe1_outer1_rtr", 25, 25, &umr_bitfield_default },
+	 { "pipe1_outer2_rtr", 26, 26, &umr_bitfield_default },
+	 { "pipe1_inner1_rtr", 27, 27, &umr_bitfield_default },
+	 { "pipe1_inner2_rtr", 28, 28, &umr_bitfield_default },
+	 { "pipe1_patch_rtr", 29, 29, &umr_bitfield_default },
+	 { "pipe1_edge_rtr", 30, 30, &umr_bitfield_default },
+	 { "use_stored_inner_q_ring1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG36[] = {
+	 { "VGT_PA_clipp_eop", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_INVALIDATE[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_STATUS[] = {
+	 { "TCP_BUSY", 0, 0, &umr_bitfield_default },
+	 { "INPUT_BUSY", 1, 1, &umr_bitfield_default },
+	 { "ADRS_BUSY", 2, 2, &umr_bitfield_default },
+	 { "TAGRAMS_BUSY", 3, 3, &umr_bitfield_default },
+	 { "CNTRL_BUSY", 4, 4, &umr_bitfield_default },
+	 { "LFIFO_BUSY", 5, 5, &umr_bitfield_default },
+	 { "READ_BUSY", 6, 6, &umr_bitfield_default },
+	 { "FORMAT_BUSY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CNTL[] = {
+	 { "FORCE_HIT", 0, 0, &umr_bitfield_default },
+	 { "FORCE_MISS", 1, 1, &umr_bitfield_default },
+	 { "L1_SIZE", 2, 3, &umr_bitfield_default },
+	 { "FLAT_BUF_HASH_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FLAT_BUF_CACHE_SWIZZLE", 5, 5, &umr_bitfield_default },
+	 { "FORCE_EOW_TOTAL_CNT", 15, 20, &umr_bitfield_default },
+	 { "FORCE_EOW_TAGRAM_CNT", 22, 27, &umr_bitfield_default },
+	 { "DISABLE_Z_MAP", 28, 28, &umr_bitfield_default },
+	 { "INV_ALL_VMIDS", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CHAN_STEER_LO[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "CHAN3", 12, 15, &umr_bitfield_default },
+	 { "CHAN4", 16, 19, &umr_bitfield_default },
+	 { "CHAN5", 20, 23, &umr_bitfield_default },
+	 { "CHAN6", 24, 27, &umr_bitfield_default },
+	 { "CHAN7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CHAN_STEER_HI[] = {
+	 { "CHAN8", 0, 3, &umr_bitfield_default },
+	 { "CHAN9", 4, 7, &umr_bitfield_default },
+	 { "CHANA", 8, 11, &umr_bitfield_default },
+	 { "CHANB", 12, 15, &umr_bitfield_default },
+	 { "CHANC", 16, 19, &umr_bitfield_default },
+	 { "CHAND", 20, 23, &umr_bitfield_default },
+	 { "CHANE", 24, 27, &umr_bitfield_default },
+	 { "CHANF", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_ADDR_CONFIG[] = {
+	 { "NUM_TCC_BANKS", 0, 3, &umr_bitfield_default },
+	 { "NUM_BANKS", 4, 5, &umr_bitfield_default },
+	 { "COLHI_WIDTH", 6, 8, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CREDIT[] = {
+	 { "LFIFO_CREDIT", 0, 9, &umr_bitfield_default },
+	 { "REQ_FIFO_CREDIT", 16, 22, &umr_bitfield_default },
+	 { "TD_CREDIT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_BUFFER_ADDR_HASH_CNTL[] = {
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "BANK_BITS", 8, 10, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 16, 18, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_EDC_CNT[] = {
+	 { "SEC_COUNT", 0, 7, &umr_bitfield_default },
+	 { "LFIFO_SED_COUNT", 8, 15, &umr_bitfield_default },
+	 { "DED_COUNT", 16, 23, &umr_bitfield_default },
+	 { "UNUSED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_LOAD_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_LOAD_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_STORE_POLICY[] = {
+	 { "POLICY_0", 0, 0, &umr_bitfield_default },
+	 { "POLICY_1", 1, 1, &umr_bitfield_default },
+	 { "POLICY_2", 2, 2, &umr_bitfield_default },
+	 { "POLICY_3", 3, 3, &umr_bitfield_default },
+	 { "POLICY_4", 4, 4, &umr_bitfield_default },
+	 { "POLICY_5", 5, 5, &umr_bitfield_default },
+	 { "POLICY_6", 6, 6, &umr_bitfield_default },
+	 { "POLICY_7", 7, 7, &umr_bitfield_default },
+	 { "POLICY_8", 8, 8, &umr_bitfield_default },
+	 { "POLICY_9", 9, 9, &umr_bitfield_default },
+	 { "POLICY_10", 10, 10, &umr_bitfield_default },
+	 { "POLICY_11", 11, 11, &umr_bitfield_default },
+	 { "POLICY_12", 12, 12, &umr_bitfield_default },
+	 { "POLICY_13", 13, 13, &umr_bitfield_default },
+	 { "POLICY_14", 14, 14, &umr_bitfield_default },
+	 { "POLICY_15", 15, 15, &umr_bitfield_default },
+	 { "POLICY_16", 16, 16, &umr_bitfield_default },
+	 { "POLICY_17", 17, 17, &umr_bitfield_default },
+	 { "POLICY_18", 18, 18, &umr_bitfield_default },
+	 { "POLICY_19", 19, 19, &umr_bitfield_default },
+	 { "POLICY_20", 20, 20, &umr_bitfield_default },
+	 { "POLICY_21", 21, 21, &umr_bitfield_default },
+	 { "POLICY_22", 22, 22, &umr_bitfield_default },
+	 { "POLICY_23", 23, 23, &umr_bitfield_default },
+	 { "POLICY_24", 24, 24, &umr_bitfield_default },
+	 { "POLICY_25", 25, 25, &umr_bitfield_default },
+	 { "POLICY_26", 26, 26, &umr_bitfield_default },
+	 { "POLICY_27", 27, 27, &umr_bitfield_default },
+	 { "POLICY_28", 28, 28, &umr_bitfield_default },
+	 { "POLICY_29", 29, 29, &umr_bitfield_default },
+	 { "POLICY_30", 30, 30, &umr_bitfield_default },
+	 { "POLICY_31", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_LOAD_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_LOAD_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_STORE_POLICY0[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_STORE_POLICY1[] = {
+	 { "POLICY_16", 0, 1, &umr_bitfield_default },
+	 { "POLICY_17", 2, 3, &umr_bitfield_default },
+	 { "POLICY_18", 4, 5, &umr_bitfield_default },
+	 { "POLICY_19", 6, 7, &umr_bitfield_default },
+	 { "POLICY_20", 8, 9, &umr_bitfield_default },
+	 { "POLICY_21", 10, 11, &umr_bitfield_default },
+	 { "POLICY_22", 12, 13, &umr_bitfield_default },
+	 { "POLICY_23", 14, 15, &umr_bitfield_default },
+	 { "POLICY_24", 16, 17, &umr_bitfield_default },
+	 { "POLICY_25", 18, 19, &umr_bitfield_default },
+	 { "POLICY_26", 20, 21, &umr_bitfield_default },
+	 { "POLICY_27", 22, 23, &umr_bitfield_default },
+	 { "POLICY_28", 24, 25, &umr_bitfield_default },
+	 { "POLICY_29", 26, 27, &umr_bitfield_default },
+	 { "POLICY_30", 28, 29, &umr_bitfield_default },
+	 { "POLICY_31", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_ATOMIC_POLICY[] = {
+	 { "POLICY_0", 0, 1, &umr_bitfield_default },
+	 { "POLICY_1", 2, 3, &umr_bitfield_default },
+	 { "POLICY_2", 4, 5, &umr_bitfield_default },
+	 { "POLICY_3", 6, 7, &umr_bitfield_default },
+	 { "POLICY_4", 8, 9, &umr_bitfield_default },
+	 { "POLICY_5", 10, 11, &umr_bitfield_default },
+	 { "POLICY_6", 12, 13, &umr_bitfield_default },
+	 { "POLICY_7", 14, 15, &umr_bitfield_default },
+	 { "POLICY_8", 16, 17, &umr_bitfield_default },
+	 { "POLICY_9", 18, 19, &umr_bitfield_default },
+	 { "POLICY_10", 20, 21, &umr_bitfield_default },
+	 { "POLICY_11", 22, 23, &umr_bitfield_default },
+	 { "POLICY_12", 24, 25, &umr_bitfield_default },
+	 { "POLICY_13", 26, 27, &umr_bitfield_default },
+	 { "POLICY_14", 28, 29, &umr_bitfield_default },
+	 { "POLICY_15", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L1_VOLATILE[] = {
+	 { "VOL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTC_CFG_L2_VOLATILE[] = {
+	 { "VOL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_STATUS[] = {
+	 { "TCI_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_CNTL_1[] = {
+	 { "WBINVL1_NUM_CYCLES", 0, 15, &umr_bitfield_default },
+	 { "REQ_FIFO_DEPTH", 16, 23, &umr_bitfield_default },
+	 { "WDATA_RAM_DEPTH", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCI_CNTL_2[] = {
+	 { "L1_INVAL_ON_WBINVL2", 0, 0, &umr_bitfield_default },
+	 { "TCA_MAX_CREDIT", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_CTRL[] = {
+	 { "CACHE_SIZE", 0, 1, &umr_bitfield_default },
+	 { "RATE", 2, 3, &umr_bitfield_default },
+	 { "WRITEBACK_MARGIN", 4, 7, &umr_bitfield_default },
+	 { "METADATA_LATENCY_FIFO_SIZE", 8, 11, &umr_bitfield_default },
+	 { "SRC_FIFO_SIZE", 12, 15, &umr_bitfield_default },
+	 { "LATENCY_FIFO_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WB_OR_INV_ALL_VMIDS", 20, 20, &umr_bitfield_default },
+	 { "MDC_SIZE", 24, 25, &umr_bitfield_default },
+	 { "MDC_SECTOR_SIZE", 26, 27, &umr_bitfield_default },
+	 { "MDC_SIDEBAND_FIFO_SIZE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_EDC_CNT[] = {
+	 { "SEC_COUNT", 0, 7, &umr_bitfield_default },
+	 { "DED_COUNT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_REDUNDANCY[] = {
+	 { "MC_SEL0", 0, 0, &umr_bitfield_default },
+	 { "MC_SEL1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_EXE_DISABLE[] = {
+	 { "EXE_DISABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_DSM_CNTL[] = {
+	 { "CACHE_RAM_IRRITATOR_DATA_SEL", 0, 1, &umr_bitfield_default },
+	 { "CACHE_RAM_IRRITATOR_SINGLE_WRITE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_CTRL[] = {
+	 { "HOLE_TIMEOUT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_PS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_PS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_PS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_PS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_PS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "WAVE_CNT_EN", 7, 7, &umr_bitfield_default },
+	 { "EXTRA_LDS_SIZE", 8, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_PS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_VS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_LATE_ALLOC_VS[] = {
+	 { "LIMIT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_VS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_VS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_VS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "SO_BASE0_EN", 8, 8, &umr_bitfield_default },
+	 { "SO_BASE1_EN", 9, 9, &umr_bitfield_default },
+	 { "SO_BASE2_EN", 10, 10, &umr_bitfield_default },
+	 { "SO_BASE3_EN", 11, 11, &umr_bitfield_default },
+	 { "SO_EN", 12, 12, &umr_bitfield_default },
+	 { "EXCP_EN", 13, 21, &umr_bitfield_default },
+	 { "DISPATCH_DRAW_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_VS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_VS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_GS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+	 { "GROUP_FIFO_DEPTH", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_GS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_GS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_GS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "CACHE_CTL", 25, 27, &umr_bitfield_default },
+	 { "CDBG_USER", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_GS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "EXCP_EN", 7, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_GS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES_GS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_ES[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+	 { "GROUP_FIFO_DEPTH", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_ES[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_ES[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_ES[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CU_GROUP_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CACHE_CTL", 27, 29, &umr_bitfield_default },
+	 { "CDBG_USER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_ES[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "EXCP_EN", 8, 16, &umr_bitfield_default },
+	 { "LDS_SIZE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_ES_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_ES[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_HS[] = {
+	 { "WAVE_LIMIT", 0, 5, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 6, 9, &umr_bitfield_default },
+	 { "GROUP_FIFO_DEPTH", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_HS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_HS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_HS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "CACHE_CTL", 24, 26, &umr_bitfield_default },
+	 { "CDBG_USER", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_HS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "OC_LDS_EN", 7, 7, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 8, 8, &umr_bitfield_default },
+	 { "EXCP_EN", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_HS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS_HS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TBA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_TMA_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC3_LS[] = {
+	 { "CU_EN", 0, 15, &umr_bitfield_default },
+	 { "WAVE_LIMIT", 16, 21, &umr_bitfield_default },
+	 { "LOCK_LOW_THRESHOLD", 22, 25, &umr_bitfield_default },
+	 { "GROUP_FIFO_DEPTH", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_LO_LS[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_HI_LS[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC1_LS[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "VGPR_COMP_CNT", 24, 25, &umr_bitfield_default },
+	 { "CACHE_CTL", 26, 28, &umr_bitfield_default },
+	 { "CDBG_USER", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_PGM_RSRC2_LS[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "LDS_SIZE", 7, 15, &umr_bitfield_default },
+	 { "EXCP_EN", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_USER_DATA_LS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DISPATCH_INITIATOR[] = {
+	 { "COMPUTE_SHADER_EN", 0, 0, &umr_bitfield_default },
+	 { "PARTIAL_TG_EN", 1, 1, &umr_bitfield_default },
+	 { "FORCE_START_AT_000", 2, 2, &umr_bitfield_default },
+	 { "ORDERED_APPEND_ENBL", 3, 3, &umr_bitfield_default },
+	 { "ORDERED_APPEND_MODE", 4, 4, &umr_bitfield_default },
+	 { "USE_THREAD_DIMENSIONS", 5, 5, &umr_bitfield_default },
+	 { "ORDER_MODE", 6, 6, &umr_bitfield_default },
+	 { "DISPATCH_CACHE_CNTL", 7, 9, &umr_bitfield_default },
+	 { "SCALAR_L1_INV_VOL", 10, 10, &umr_bitfield_default },
+	 { "VECTOR_L1_INV_VOL", 11, 11, &umr_bitfield_default },
+	 { "DATA_ATC", 12, 12, &umr_bitfield_default },
+	 { "RESTORE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_X[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_Y[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DIM_Z[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_X[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_Y[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_START_Z[] = {
+	 { "START", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_X[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Y[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NUM_THREAD_Z[] = {
+	 { "NUM_THREAD_FULL", 0, 15, &umr_bitfield_default },
+	 { "NUM_THREAD_PARTIAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PIPELINESTAT_ENABLE[] = {
+	 { "PIPELINESTAT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PERFCOUNT_ENABLE[] = {
+	 { "PERFCOUNT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+	 { "INST_ATC", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TBA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TBA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMA_HI[] = {
+	 { "DATA", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_RSRC1[] = {
+	 { "VGPRS", 0, 5, &umr_bitfield_default },
+	 { "SGPRS", 6, 9, &umr_bitfield_default },
+	 { "PRIORITY", 10, 11, &umr_bitfield_default },
+	 { "FLOAT_MODE", 12, 19, &umr_bitfield_default },
+	 { "PRIV", 20, 20, &umr_bitfield_default },
+	 { "DX10_CLAMP", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_MODE", 22, 22, &umr_bitfield_default },
+	 { "IEEE_MODE", 23, 23, &umr_bitfield_default },
+	 { "BULKY", 24, 24, &umr_bitfield_default },
+	 { "CDBG_USER", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_PGM_RSRC2[] = {
+	 { "SCRATCH_EN", 0, 0, &umr_bitfield_default },
+	 { "USER_SGPR", 1, 5, &umr_bitfield_default },
+	 { "TRAP_PRESENT", 6, 6, &umr_bitfield_default },
+	 { "TGID_X_EN", 7, 7, &umr_bitfield_default },
+	 { "TGID_Y_EN", 8, 8, &umr_bitfield_default },
+	 { "TGID_Z_EN", 9, 9, &umr_bitfield_default },
+	 { "TG_SIZE_EN", 10, 10, &umr_bitfield_default },
+	 { "TIDIG_COMP_CNT", 11, 12, &umr_bitfield_default },
+	 { "EXCP_EN_MSB", 13, 14, &umr_bitfield_default },
+	 { "LDS_SIZE", 15, 23, &umr_bitfield_default },
+	 { "EXCP_EN", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_VMID[] = {
+	 { "DATA", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESOURCE_LIMITS[] = {
+	 { "WAVES_PER_SH", 0, 9, &umr_bitfield_default },
+	 { "TG_PER_CU", 12, 15, &umr_bitfield_default },
+	 { "LOCK_THRESHOLD", 16, 21, &umr_bitfield_default },
+	 { "SIMD_DEST_CNTL", 22, 22, &umr_bitfield_default },
+	 { "FORCE_SIMD_DIST", 23, 23, &umr_bitfield_default },
+	 { "CU_GROUP_COUNT", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE0[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE1[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_TMPRING_SIZE[] = {
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE2[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_STATIC_THREAD_MGMT_SE3[] = {
+	 { "SH0_CU_EN", 0, 15, &umr_bitfield_default },
+	 { "SH1_CU_EN", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_X[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_Y[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RESTART_Z[] = {
+	 { "RESTART", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_THREAD_TRACE_ENABLE[] = {
+	 { "THREAD_TRACE_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_MISC_RESERVED[] = {
+	 { "SEND_SEID", 0, 1, &umr_bitfield_default },
+	 { "RESERVED2", 2, 2, &umr_bitfield_default },
+	 { "RESERVED3", 3, 3, &umr_bitfield_default },
+	 { "RESERVED4", 4, 4, &umr_bitfield_default },
+	 { "WAVE_ID_BASE", 5, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_DISPATCH_ID[] = {
+	 { "DISPATCH_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_THREADGROUP_ID[] = {
+	 { "THREADGROUP_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_RELAUNCH[] = {
+	 { "PAYLOAD", 0, 29, &umr_bitfield_default },
+	 { "IS_EVENT", 30, 30, &umr_bitfield_default },
+	 { "IS_STATE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_WAVE_RESTORE_ADDR_LO[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_WAVE_RESTORE_ADDR_HI[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_WAVE_RESTORE_CONTROL[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "MTYPE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_USER_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOMPUTE_NOWHERE[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG03[] = {
+	 { "clipsm0_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_SQ_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG3[] = {
+	 { "pipe_num_busy", 0, 10, &umr_bitfield_default },
+	 { "pipe0_busy_num", 11, 14, &umr_bitfield_default },
+	 { "spare", 15, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG3[] = {
+	 { "rbiu_spl_dr_valid", 0, 0, &umr_bitfield_default },
+	 { "SPARE0", 1, 1, &umr_bitfield_default },
+	 { "pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "pipe1_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "wd_subdma_fifo_empty", 6, 6, &umr_bitfield_default },
+	 { "wd_subdma_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "dma_buf_type_p0_q", 8, 9, &umr_bitfield_default },
+	 { "dma_zero_indices_p0_q", 10, 10, &umr_bitfield_default },
+	 { "dma_req_path_p3_q", 11, 11, &umr_bitfield_default },
+	 { "dma_not_eop_p1_q", 12, 12, &umr_bitfield_default },
+	 { "out_of_range_p4", 13, 13, &umr_bitfield_default },
+	 { "last_sub_dma_p3_q", 14, 14, &umr_bitfield_default },
+	 { "last_rdreq_of_sub_dma_p4", 15, 15, &umr_bitfield_default },
+	 { "WD_IA_dma_send_d", 16, 16, &umr_bitfield_default },
+	 { "WD_IA_dma_rtr", 17, 17, &umr_bitfield_default },
+	 { "WD_IA1_dma_send_d", 18, 18, &umr_bitfield_default },
+	 { "WD_IA1_dma_rtr", 19, 19, &umr_bitfield_default },
+	 { "last_inst_of_dma_p2", 20, 20, &umr_bitfield_default },
+	 { "last_sd_of_inst_p2", 21, 21, &umr_bitfield_default },
+	 { "last_sd_of_dma_p2", 22, 22, &umr_bitfield_default },
+	 { "SPARE1", 23, 23, &umr_bitfield_default },
+	 { "WD_IA_dma_busy", 24, 24, &umr_bitfield_default },
+	 { "WD_IA1_dma_busy", 25, 25, &umr_bitfield_default },
+	 { "send_to_ia1_p3_q", 26, 26, &umr_bitfield_default },
+	 { "dma_wd_switch_on_eop_p3_q", 27, 27, &umr_bitfield_default },
+	 { "pipe3_dr", 28, 28, &umr_bitfield_default },
+	 { "pipe3_rtr", 29, 29, &umr_bitfield_default },
+	 { "wd_dma2draw_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "wd_dma2draw_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_CNTL[] = {
+	 { "POLICY", 0, 0, &umr_bitfield_default },
+	 { "MTYPE", 2, 3, &umr_bitfield_default },
+	 { "LFSR_RESET", 28, 28, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_STAT[] = {
+	 { "BURST_COUNT", 0, 15, &umr_bitfield_default },
+	 { "TAGS_PENDING", 16, 24, &umr_bitfield_default },
+	 { "BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_ADDR_LO[] = {
+	 { "ADDR_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DFY_CMD[] = {
+	 { "OFFSET", 0, 8, &umr_bitfield_default },
+	 { "SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_MGCG_SYNC_CNTL[] = {
+	 { "COOLDOWN_PERIOD", 0, 7, &umr_bitfield_default },
+	 { "WARMUP_PERIOD", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATCL1_CNTL[] = {
+	 { "XNACK_REDO_TIMER_CNT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "BUF_SWAP", 17, 18, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "BUF_SWAP", 17, 18, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_WR[] = {
+	 { "RB_RPTR_WR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "RB_WPTR_POLL_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "RB_WPTR_POLL_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS[] = {
+	 { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DEVICE_ID[] = {
+	 { "DEVICE_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RING2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ENDIAN_SWAP[] = {
+	 { "ENDIAN_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_VMID[] = {
+	 { "RB0_VMID", 0, 3, &umr_bitfield_default },
+	 { "RB1_VMID", 8, 11, &umr_bitfield_default },
+	 { "RB2_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE0_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME0_PIPE1_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_DOORBELL_CONTROL[] = {
+	 { "DOORBELL_OFFSET", 2, 22, &umr_bitfield_default },
+	 { "DOORBELL_EN", 30, 30, &umr_bitfield_default },
+	 { "DOORBELL_HIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_DOORBELL_RANGE_LOWER[] = {
+	 { "DOORBELL_RANGE_LOWER", 2, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_DOORBELL_RANGE_UPPER[] = {
+	 { "DOORBELL_RANGE_UPPER", 2, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_DOORBELL_RANGE_LOWER[] = {
+	 { "DOORBELL_RANGE_LOWER", 2, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_DOORBELL_RANGE_UPPER[] = {
+	 { "DOORBELL_RANGE_UPPER", 2, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_BASE[] = {
+	 { "RB_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_CNTL[] = {
+	 { "RB_BUFSZ", 0, 5, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "MIN_AVAILSZ", 20, 21, &umr_bitfield_default },
+	 { "MIN_IB_AVAILSZ", 22, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 27, 27, &umr_bitfield_default },
+	 { "RB_RPTR_WR_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR_ADDR[] = {
+	 { "RB_RPTR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_RPTR_ADDR_HI[] = {
+	 { "RB_RPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB2_WPTR[] = {
+	 { "RB_WPTR", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING0[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING1[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_CNTL_RING2[] = {
+	 { "CP_VM_DOORBELL_WR_INT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING0[] = {
+	 { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default },
+	 { "GCNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING1[] = {
+	 { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INT_STATUS_RING2[] = {
+	 { "CP_VM_DOORBELL_WR_INT_STAT", 11, 11, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STAT", 14, 14, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STAT", 17, 17, &umr_bitfield_default },
+	 { "CMP_BUSY_INT_STAT", 18, 18, &umr_bitfield_default },
+	 { "CNTX_BUSY_INT_STAT", 19, 19, &umr_bitfield_default },
+	 { "CNTX_EMPTY_INT_STAT", 20, 20, &umr_bitfield_default },
+	 { "GFX_IDLE_INT_STAT", 21, 21, &umr_bitfield_default },
+	 { "PRIV_INSTR_INT_STAT", 22, 22, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STAT", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STAT", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STAT", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STAT", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STAT", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STAT", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PWR_CNTL[] = {
+	 { "GFX_CLK_HALT_ME0_PIPE0", 0, 0, &umr_bitfield_default },
+	 { "GFX_CLK_HALT_ME0_PIPE1", 1, 1, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME1_PIPE0", 8, 8, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME1_PIPE1", 9, 9, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME1_PIPE2", 10, 10, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME1_PIPE3", 11, 11, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME2_PIPE0", 16, 16, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME2_PIPE1", 17, 17, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME2_PIPE2", 18, 18, &umr_bitfield_default },
+	 { "CMP_CLK_HALT_ME2_PIPE3", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEM_SLP_CNTL[] = {
+	 { "CP_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "CP_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 6, &umr_bitfield_default },
+	 { "CP_LS_DS_BUSY_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "CP_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CP_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE[] = {
+	 { "INTERFACE", 0, 1, &umr_bitfield_default },
+	 { "CLIENT", 4, 7, &umr_bitfield_default },
+	 { "ME", 8, 9, &umr_bitfield_default },
+	 { "PIPE", 10, 11, &umr_bitfield_default },
+	 { "QUEUE", 12, 14, &umr_bitfield_default },
+	 { "VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING0[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING1[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ECC_FIRSTOCCURRENCE_RING2[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGB_EDC_MODE[] = {
+	 { "FORCE_SEC_ON_DED", 16, 16, &umr_bitfield_default },
+	 { "DED_MODE", 20, 21, &umr_bitfield_default },
+	 { "PROP_FED", 29, 29, &umr_bitfield_default },
+	 { "BYPASS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_WPTR_POLL_CNTL[] = {
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+	 { "POLL_ACTIVE", 30, 30, &umr_bitfield_default },
+	 { "EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_WPTR_POLL_CNTL1[] = {
+	 { "QUEUE_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_INT_STAT_DEBUG[] = {
+	 { "CMP_QUERY_STATUS_INT_ASSERTED", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ASSERTED", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_INT_STAT_DEBUG[] = {
+	 { "CMP_QUERY_STATUS_INT_ASSERTED", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ASSERTED", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ASSERTED", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ASSERTED", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ASSERTED", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ASSERTED", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ASSERTED", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ASSERTED", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ASSERTED", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ASSERTED", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ASSERTED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_GC_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME1_PIPE3_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE_PRIORITY_CNTS[] = {
+	 { "PRIORITY1_CNT", 0, 7, &umr_bitfield_default },
+	 { "PRIORITY2A_CNT", 8, 15, &umr_bitfield_default },
+	 { "PRIORITY2B_CNT", 16, 23, &umr_bitfield_default },
+	 { "PRIORITY3_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE0_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE1_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE2_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME2_PIPE3_PRIORITY[] = {
+	 { "PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC1_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC2_PRGRM_CNTR_START[] = {
+	 { "IP_START", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC1_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC2_INTR_ROUTINE_START[] = {
+	 { "IR_START", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CONTEXT_CNTL[] = {
+	 { "ME0PIPE0_MAX_WD_CNTX", 0, 2, &umr_bitfield_default },
+	 { "ME0PIPE0_MAX_PIPE_CNTX", 4, 6, &umr_bitfield_default },
+	 { "ME0PIPE1_MAX_WD_CNTX", 16, 18, &umr_bitfield_default },
+	 { "ME0PIPE1_MAX_PIPE_CNTX", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MAX_CONTEXT[] = {
+	 { "MAX_CONTEXT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IQ_WAIT_TIME1[] = {
+	 { "IB_OFFLOAD", 0, 7, &umr_bitfield_default },
+	 { "ATOMIC_OFFLOAD", 8, 15, &umr_bitfield_default },
+	 { "WRM_OFFLOAD", 16, 23, &umr_bitfield_default },
+	 { "GWS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IQ_WAIT_TIME2[] = {
+	 { "QUE_SLEEP", 0, 7, &umr_bitfield_default },
+	 { "SCH_WAVE", 8, 15, &umr_bitfield_default },
+	 { "SEM_REARM", 16, 23, &umr_bitfield_default },
+	 { "DEQ_RETRY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB0_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB1_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID_RESET[] = {
+	 { "RESET_REQUEST", 0, 15, &umr_bitfield_default },
+	 { "RESET_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_CNTL[] = {
+	 { "CMP_QUERY_STATUS_INT_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_STATUS[] = {
+	 { "CMP_QUERY_STATUS_INT_STATUS", 12, 12, &umr_bitfield_default },
+	 { "DEQUEUE_REQUEST_INT_STATUS", 13, 13, &umr_bitfield_default },
+	 { "CP_ECC_ERROR_INT_STATUS", 14, 14, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT_STATUS", 15, 15, &umr_bitfield_default },
+	 { "WRM_POLL_TIMEOUT_INT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "PRIV_REG_INT_STATUS", 23, 23, &umr_bitfield_default },
+	 { "OPCODE_ERROR_INT_STATUS", 24, 24, &umr_bitfield_default },
+	 { "TIME_STAMP_INT_STATUS", 26, 26, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERROR_INT_STATUS", 27, 27, &umr_bitfield_default },
+	 { "GENERIC2_INT_STATUS", 29, 29, &umr_bitfield_default },
+	 { "GENERIC1_INT_STATUS", 30, 30, &umr_bitfield_default },
+	 { "GENERIC0_INT_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID_PREEMPT[] = {
+	 { "PREEMPT_REQUEST", 0, 15, &umr_bitfield_default },
+	 { "VIRT_COMMAND", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_INT_CNTX_ID[] = {
+	 { "CNTX_ID", 0, 27, &umr_bitfield_default },
+	 { "QUEUE_ID", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PQ_STATUS[] = {
+	 { "DOORBELL_UPDATED", 0, 0, &umr_bitfield_default },
+	 { "DOORBELL_ENABLE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_IC_BASE_LO[] = {
+	 { "IC_BASE_LO", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_IC_BASE_HI[] = {
+	 { "IC_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_IC_BASE_CNTL[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CPC_IC_OP_CNTL[] = {
+	 { "INVALIDATE_CACHE", 0, 0, &umr_bitfield_default },
+	 { "PRIME_ICACHE", 4, 4, &umr_bitfield_default },
+	 { "ICACHE_PRIMED", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC1_F32_INT_DIS[] = {
+	 { "EDC_ROQ_FED_INT", 0, 0, &umr_bitfield_default },
+	 { "PRIV_REG_INT", 1, 1, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERR_INT", 2, 2, &umr_bitfield_default },
+	 { "EDC_TC_FED_INT", 3, 3, &umr_bitfield_default },
+	 { "EDC_GDS_FED_INT", 4, 4, &umr_bitfield_default },
+	 { "EDC_SCRATCH_FED_INT", 5, 5, &umr_bitfield_default },
+	 { "WAVE_RESTORE_INT", 6, 6, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT", 7, 7, &umr_bitfield_default },
+	 { "EDC_DMA_FED_INT", 8, 8, &umr_bitfield_default },
+	 { "IQ_TIMER_INT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC2_F32_INT_DIS[] = {
+	 { "EDC_ROQ_FED_INT", 0, 0, &umr_bitfield_default },
+	 { "PRIV_REG_INT", 1, 1, &umr_bitfield_default },
+	 { "RESERVED_BIT_ERR_INT", 2, 2, &umr_bitfield_default },
+	 { "EDC_TC_FED_INT", 3, 3, &umr_bitfield_default },
+	 { "EDC_GDS_FED_INT", 4, 4, &umr_bitfield_default },
+	 { "EDC_SCRATCH_FED_INT", 5, 5, &umr_bitfield_default },
+	 { "WAVE_RESTORE_INT", 6, 6, &umr_bitfield_default },
+	 { "SUA_VIOLATION_INT", 7, 7, &umr_bitfield_default },
+	 { "EDC_DMA_FED_INT", 8, 8, &umr_bitfield_default },
+	 { "IQ_TIMER_INT", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID_STATUS[] = {
+	 { "PREEMPT_DE_STATUS", 0, 15, &umr_bitfield_default },
+	 { "PREEMPT_CE_STATUS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_PRIORITY[] = {
+	 { "PIPE_ORDER_TS0", 0, 2, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS1", 3, 5, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS2", 6, 8, &umr_bitfield_default },
+	 { "PIPE_ORDER_TS3", 9, 11, &umr_bitfield_default },
+	 { "TS0_DUR_MULT", 12, 13, &umr_bitfield_default },
+	 { "TS1_DUR_MULT", 14, 15, &umr_bitfield_default },
+	 { "TS2_DUR_MULT", 16, 17, &umr_bitfield_default },
+	 { "TS3_DUR_MULT", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_CYCLES_0[] = {
+	 { "TS0_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS1_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_ARB_CYCLES_1[] = {
+	 { "TS2_DURATION", 0, 15, &umr_bitfield_default },
+	 { "TS3_DURATION", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_GFX[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_HP3D[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_CS0[] = {
+	 { "PIPE0", 0, 7, &umr_bitfield_default },
+	 { "PIPE1", 8, 15, &umr_bitfield_default },
+	 { "PIPE2", 16, 23, &umr_bitfield_default },
+	 { "PIPE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_CDBG_SYS_CS1[] = {
+	 { "PIPE0", 0, 7, &umr_bitfield_default },
+	 { "PIPE1", 8, 15, &umr_bitfield_default },
+	 { "PIPE2", 16, 23, &umr_bitfield_default },
+	 { "PIPE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_GFX[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+	 { "LS_GRP_VALUE", 7, 11, &umr_bitfield_default },
+	 { "HS_GRP_VALUE", 12, 16, &umr_bitfield_default },
+	 { "ES_GRP_VALUE", 17, 21, &umr_bitfield_default },
+	 { "GS_GRP_VALUE", 22, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_HP3D[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+	 { "LS_GRP_VALUE", 7, 11, &umr_bitfield_default },
+	 { "HS_GRP_VALUE", 12, 16, &umr_bitfield_default },
+	 { "ES_GRP_VALUE", 17, 21, &umr_bitfield_default },
+	 { "GS_GRP_VALUE", 22, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS0[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS1[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS2[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS3[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS4[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS5[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS6[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_WCL_PIPE_PERCENT_CS7[] = {
+	 { "VALUE", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_WAVE_CNTL[] = {
+	 { "STALL_RA", 0, 0, &umr_bitfield_default },
+	 { "STALL_VMID", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_CONFIG[] = {
+	 { "ME_SEL", 0, 1, &umr_bitfield_default },
+	 { "PIPE_SEL", 2, 3, &umr_bitfield_default },
+	 { "QUEUE_SEL", 4, 6, &umr_bitfield_default },
+	 { "ME_MATCH", 7, 7, &umr_bitfield_default },
+	 { "PIPE_MATCH", 8, 8, &umr_bitfield_default },
+	 { "QUEUE_MATCH", 9, 9, &umr_bitfield_default },
+	 { "TRAP_EN", 15, 15, &umr_bitfield_default },
+	 { "VMID_SEL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_MASK[] = {
+	 { "EXCP_EN", 0, 8, &umr_bitfield_default },
+	 { "REPLACE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TBA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TBA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TMA_LO[] = {
+	 { "MEM_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TMA_HI[] = {
+	 { "MEM_BASE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_DATA0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_GDBG_TRAP_DATA1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESET_DEBUG[] = {
+	 { "DISABLE_GFX_RESET", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_PER_VMID", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_ALL_VMID", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_RESOURCE", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_GFX_RESET_PRIORITY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_COMPUTE_QUEUE_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_0[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_1[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_2[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_3[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_4[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_5[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_6[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_7[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_8[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_9[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_0[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_1[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_2[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_3[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_4[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_5[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_6[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_7[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_8[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_9[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_10[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_11[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_10[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_11[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_12[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_13[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_14[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_CU_15[] = {
+	 { "VGPR", 0, 3, &umr_bitfield_default },
+	 { "SGPR", 4, 7, &umr_bitfield_default },
+	 { "LDS", 8, 11, &umr_bitfield_default },
+	 { "WAVES", 12, 14, &umr_bitfield_default },
+	 { "BARRIERS", 15, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_12[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_13[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_14[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_RESOURCE_RESERVE_EN_CU_15[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "TYPE_MASK", 1, 15, &umr_bitfield_default },
+	 { "QUEUE_MASK", 16, 23, &umr_bitfield_default },
+	 { "RESERVE_SPACE_ONLY", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_COMPUTE_WF_CTX_SAVE[] = {
+	 { "INITIATE", 0, 0, &umr_bitfield_default },
+	 { "GDS_INTERRUPT_EN", 1, 1, &umr_bitfield_default },
+	 { "DONE_INTERRUPT_EN", 2, 2, &umr_bitfield_default },
+	 { "GDS_REQ_BUSY", 30, 30, &umr_bitfield_default },
+	 { "SAVE_BUSY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DB_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_ROQ_OFFSETS[] = {
+	 { "IQ_OFFSET", 0, 2, &umr_bitfield_default },
+	 { "PQ_OFFSET", 8, 13, &umr_bitfield_default },
+	 { "IB_OFFSET", 16, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HPD_STATUS0[] = {
+	 { "QUEUE_STATE", 0, 4, &umr_bitfield_default },
+	 { "MAPPED_QUEUE", 5, 7, &umr_bitfield_default },
+	 { "QUEUE_AVAILABLE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_BASE_ADDR[] = {
+	 { "BASE_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_BASE_ADDR_HI[] = {
+	 { "BASE_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ACTIVE[] = {
+	 { "ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "BUSY_GATE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "IB_VMID", 8, 11, &umr_bitfield_default },
+	 { "VQID", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PERSISTENT_STATE[] = {
+	 { "PRELOAD_REQ", 0, 0, &umr_bitfield_default },
+	 { "PRELOAD_SIZE", 8, 17, &umr_bitfield_default },
+	 { "RESTORE_ACTIVE", 28, 28, &umr_bitfield_default },
+	 { "RELAUNCH_WAVES", 29, 29, &umr_bitfield_default },
+	 { "QSWITCH_MODE", 30, 30, &umr_bitfield_default },
+	 { "DISP_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PIPE_PRIORITY[] = {
+	 { "PIPE_PRIORITY", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_QUEUE_PRIORITY[] = {
+	 { "PRIORITY_LEVEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_QUANTUM[] = {
+	 { "QUANTUM_EN", 0, 0, &umr_bitfield_default },
+	 { "QUANTUM_SCALE", 4, 4, &umr_bitfield_default },
+	 { "QUANTUM_DURATION", 8, 13, &umr_bitfield_default },
+	 { "QUANTUM_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_BASE_HI[] = {
+	 { "ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR[] = {
+	 { "CONSUMED_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR_REPORT_ADDR[] = {
+	 { "RPTR_REPORT_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[] = {
+	 { "RPTR_REPORT_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR_POLL_ADDR[] = {
+	 { "WPTR_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[] = {
+	 { "WPTR_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_DOORBELL_CONTROL[] = {
+	 { "DOORBELL_MODE", 0, 0, &umr_bitfield_default },
+	 { "DOORBELL_BIF_DROP", 1, 1, &umr_bitfield_default },
+	 { "DOORBELL_OFFSET", 2, 22, &umr_bitfield_default },
+	 { "DOORBELL_CARRY_BITS", 23, 25, &umr_bitfield_default },
+	 { "DOORBELL_SOURCE", 28, 28, &umr_bitfield_default },
+	 { "DOORBELL_SCHD_HIT", 29, 29, &umr_bitfield_default },
+	 { "DOORBELL_EN", 30, 30, &umr_bitfield_default },
+	 { "DOORBELL_HIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_WPTR[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_PQ_CONTROL[] = {
+	 { "QUEUE_SIZE", 0, 5, &umr_bitfield_default },
+	 { "RPTR_BLOCK_SIZE", 8, 13, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "ENDIAN_SWAP", 17, 18, &umr_bitfield_default },
+	 { "MIN_AVAIL_SIZE", 20, 21, &umr_bitfield_default },
+	 { "PQ_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "SLOT_BASED_WPTR", 25, 26, &umr_bitfield_default },
+	 { "NO_UPDATE_RPTR", 27, 27, &umr_bitfield_default },
+	 { "UNORD_DISPATCH", 28, 28, &umr_bitfield_default },
+	 { "ROQ_PQ_IB_FLIP", 29, 29, &umr_bitfield_default },
+	 { "PRIV_STATE", 30, 30, &umr_bitfield_default },
+	 { "KMD_QUEUE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_BASE_ADDR[] = {
+	 { "IB_BASE_ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_BASE_ADDR_HI[] = {
+	 { "IB_BASE_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_RPTR[] = {
+	 { "CONSUMED_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IB_CONTROL[] = {
+	 { "IB_SIZE", 0, 19, &umr_bitfield_default },
+	 { "MIN_IB_AVAIL_SIZE", 20, 21, &umr_bitfield_default },
+	 { "IB_ATC", 23, 23, &umr_bitfield_default },
+	 { "IB_CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+	 { "PROCESSING_IB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IQ_TIMER[] = {
+	 { "WAIT_TIME", 0, 7, &umr_bitfield_default },
+	 { "RETRY_TYPE", 8, 10, &umr_bitfield_default },
+	 { "IMMEDIATE_EXPIRE", 11, 11, &umr_bitfield_default },
+	 { "INTERRUPT_TYPE", 12, 13, &umr_bitfield_default },
+	 { "CLOCK_COUNT", 14, 15, &umr_bitfield_default },
+	 { "INTERRUPT_SIZE", 16, 21, &umr_bitfield_default },
+	 { "QUANTUM_TIMER", 22, 22, &umr_bitfield_default },
+	 { "IQ_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+	 { "PROCESS_IQ_EN", 29, 29, &umr_bitfield_default },
+	 { "PROCESSING_IQ", 30, 30, &umr_bitfield_default },
+	 { "ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_IQ_RPTR[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_DEQUEUE_REQUEST[] = {
+	 { "DEQUEUE_REQ", 0, 2, &umr_bitfield_default },
+	 { "IQ_REQ_PEND", 4, 4, &umr_bitfield_default },
+	 { "DEQUEUE_INT", 8, 8, &umr_bitfield_default },
+	 { "IQ_REQ_PEND_EN", 9, 9, &umr_bitfield_default },
+	 { "DEQUEUE_REQ_EN", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_DMA_OFFLOAD[] = {
+	 { "DMA_OFFLOAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_OFFLOAD[] = {
+	 { "DMA_OFFLOAD", 0, 0, &umr_bitfield_default },
+	 { "DMA_OFFLOAD_EN", 1, 1, &umr_bitfield_default },
+	 { "EOP_OFFLOAD", 4, 4, &umr_bitfield_default },
+	 { "EOP_OFFLOAD_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_SEMA_CMD[] = {
+	 { "RETRY", 0, 0, &umr_bitfield_default },
+	 { "RESULT", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_MSG_TYPE[] = {
+	 { "ACTION", 0, 2, &umr_bitfield_default },
+	 { "SAVE_STATE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC0_PREOP_LO[] = {
+	 { "ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC0_PREOP_HI[] = {
+	 { "ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC1_PREOP_LO[] = {
+	 { "ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ATOMIC1_PREOP_HI[] = {
+	 { "ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_SCHEDULER0[] = {
+	 { "SCHEDULER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_STATUS0[] = {
+	 { "DEQUEUE_STATUS", 0, 1, &umr_bitfield_default },
+	 { "DEQUEUE_RETRY_CNT", 2, 3, &umr_bitfield_default },
+	 { "RSV_6_4", 4, 6, &umr_bitfield_default },
+	 { "SCRATCH_RAM_INIT", 7, 7, &umr_bitfield_default },
+	 { "TCL2_DIRTY", 8, 8, &umr_bitfield_default },
+	 { "PG_ACTIVATED", 9, 9, &umr_bitfield_default },
+	 { "RSVR_31_10", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_SCHEDULER1[] = {
+	 { "SCHEDULER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_CONTROL0[] = {
+	 { "CONTROL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MQD_CONTROL[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+	 { "PROCESSING_MQD", 12, 12, &umr_bitfield_default },
+	 { "PROCESSING_MQD_EN", 13, 13, &umr_bitfield_default },
+	 { "MQD_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_STATUS1[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_HQ_CONTROL1[] = {
+	 { "CONTROL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_BASE_ADDR[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_BASE_ADDR_HI[] = {
+	 { "BASE_ADDR_HI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_CONTROL[] = {
+	 { "EOP_SIZE", 0, 5, &umr_bitfield_default },
+	 { "PROCESSING_EOP", 8, 8, &umr_bitfield_default },
+	 { "PROCESS_EOP_EN", 12, 12, &umr_bitfield_default },
+	 { "PROCESSING_EOPIB", 13, 13, &umr_bitfield_default },
+	 { "PROCESS_EOPIB_EN", 14, 14, &umr_bitfield_default },
+	 { "MTYPE", 15, 16, &umr_bitfield_default },
+	 { "EOP_ATC", 23, 23, &umr_bitfield_default },
+	 { "CACHE_POLICY", 24, 24, &umr_bitfield_default },
+	 { "SIG_SEM_RESULT", 29, 30, &umr_bitfield_default },
+	 { "PEND_SIG_SEM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_RPTR[] = {
+	 { "RPTR", 0, 12, &umr_bitfield_default },
+	 { "RPTR_EQ_CSMD_WPTR", 30, 30, &umr_bitfield_default },
+	 { "INIT_FETCHER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_WPTR[] = {
+	 { "WPTR", 0, 12, &umr_bitfield_default },
+	 { "EOP_AVAIL", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_EVENTS[] = {
+	 { "EVENT_COUNT", 0, 11, &umr_bitfield_default },
+	 { "CS_PARTIAL_FLUSH_PEND", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[] = {
+	 { "ADDR", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CTX_SAVE_CONTROL[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "MTYPE", 1, 2, &umr_bitfield_default },
+	 { "POLICY", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CNTL_STACK_OFFSET[] = {
+	 { "OFFSET", 2, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CNTL_STACK_SIZE[] = {
+	 { "SIZE", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_WG_STATE_OFFSET[] = {
+	 { "OFFSET", 2, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_CTX_SAVE_SIZE[] = {
+	 { "SIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_GDS_RESOURCE_STATE[] = {
+	 { "OA_REQUIRED", 0, 0, &umr_bitfield_default },
+	 { "OA_ACQUIRED", 1, 1, &umr_bitfield_default },
+	 { "GWS_SIZE", 4, 9, &umr_bitfield_default },
+	 { "GWS_PNTR", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_ERROR[] = {
+	 { "EDC_ERROR_ID", 0, 3, &umr_bitfield_default },
+	 { "SUA_ERROR", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_WPTR_MEM[] = {
+	 { "WPTR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_HQD_EOP_DONES[] = {
+	 { "DONE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIDT_IND_INDEX[] = {
+	 { "DIDT_IND_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDIDT_IND_DATA[] = {
+	 { "DIDT_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH0_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "ATC", 28, 28, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH1_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "ATC", 28, 28, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH2_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "ATC", 28, 28, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_ADDR_H[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_ADDR_L[] = {
+	 { "ADDR", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_WATCH3_CNTL[] = {
+	 { "MASK", 0, 23, &umr_bitfield_default },
+	 { "VMID", 24, 27, &umr_bitfield_default },
+	 { "ATC", 28, 28, &umr_bitfield_default },
+	 { "MODE", 29, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_GATCL1_CNTL[] = {
+	 { "INVALIDATE_ALL_VMID", 25, 25, &umr_bitfield_default },
+	 { "FORCE_MISS", 26, 26, &umr_bitfield_default },
+	 { "FORCE_IN_ORDER", 27, 27, &umr_bitfield_default },
+	 { "REDUCE_FIFO_DEPTH_BY_2", 28, 29, &umr_bitfield_default },
+	 { "REDUCE_CACHE_SIZE_BY_2", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_ATC_EDC_GATCL1_CNT[] = {
+	 { "DATA_SEC", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_GATCL1_DSM_CNTL[] = {
+	 { "SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0", 0, 0, &umr_bitfield_default },
+	 { "SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1", 1, 1, &umr_bitfield_default },
+	 { "TCP_GATCL1_ENABLE_SINGLE_WRITE_A", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_DSM_CNTL[] = {
+	 { "CACHE_RAM_IRRITATOR_DATA_SEL", 0, 1, &umr_bitfield_default },
+	 { "CACHE_RAM_IRRITATOR_SINGLE_WRITE", 2, 2, &umr_bitfield_default },
+	 { "LFIFO_RAM_IRRITATOR_DATA_SEL", 3, 4, &umr_bitfield_default },
+	 { "LFIFO_RAM_IRRITATOR_SINGLE_WRITE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_CNTL2[] = {
+	 { "LS_DISABLE_CLOCKS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID0_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID0_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID1_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID1_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID2_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID2_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID3_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID3_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID4_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID4_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID5_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID5_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID6_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID6_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID7_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID7_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID8_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID8_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID9_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID9_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID10_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID10_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID11_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID11_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID12_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID12_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID13_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID13_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID14_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID14_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID15_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VMID15_SIZE[] = {
+	 { "SIZE", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID0[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID1[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID2[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID3[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID4[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID5[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID6[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID7[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID8[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID9[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID10[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID11[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID12[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID13[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID14[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_VMID15[] = {
+	 { "BASE", 0, 5, &umr_bitfield_default },
+	 { "SIZE", 16, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID0[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID1[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID2[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID3[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID4[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID5[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID6[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID7[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID8[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID9[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID10[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID11[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID12[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID13[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID14[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_VMID15[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESET0[] = {
+	 { "RESOURCE0_RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE1_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESOURCE2_RESET", 2, 2, &umr_bitfield_default },
+	 { "RESOURCE3_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESOURCE4_RESET", 4, 4, &umr_bitfield_default },
+	 { "RESOURCE5_RESET", 5, 5, &umr_bitfield_default },
+	 { "RESOURCE6_RESET", 6, 6, &umr_bitfield_default },
+	 { "RESOURCE7_RESET", 7, 7, &umr_bitfield_default },
+	 { "RESOURCE8_RESET", 8, 8, &umr_bitfield_default },
+	 { "RESOURCE9_RESET", 9, 9, &umr_bitfield_default },
+	 { "RESOURCE10_RESET", 10, 10, &umr_bitfield_default },
+	 { "RESOURCE11_RESET", 11, 11, &umr_bitfield_default },
+	 { "RESOURCE12_RESET", 12, 12, &umr_bitfield_default },
+	 { "RESOURCE13_RESET", 13, 13, &umr_bitfield_default },
+	 { "RESOURCE14_RESET", 14, 14, &umr_bitfield_default },
+	 { "RESOURCE15_RESET", 15, 15, &umr_bitfield_default },
+	 { "RESOURCE16_RESET", 16, 16, &umr_bitfield_default },
+	 { "RESOURCE17_RESET", 17, 17, &umr_bitfield_default },
+	 { "RESOURCE18_RESET", 18, 18, &umr_bitfield_default },
+	 { "RESOURCE19_RESET", 19, 19, &umr_bitfield_default },
+	 { "RESOURCE20_RESET", 20, 20, &umr_bitfield_default },
+	 { "RESOURCE21_RESET", 21, 21, &umr_bitfield_default },
+	 { "RESOURCE22_RESET", 22, 22, &umr_bitfield_default },
+	 { "RESOURCE23_RESET", 23, 23, &umr_bitfield_default },
+	 { "RESOURCE24_RESET", 24, 24, &umr_bitfield_default },
+	 { "RESOURCE25_RESET", 25, 25, &umr_bitfield_default },
+	 { "RESOURCE26_RESET", 26, 26, &umr_bitfield_default },
+	 { "RESOURCE27_RESET", 27, 27, &umr_bitfield_default },
+	 { "RESOURCE28_RESET", 28, 28, &umr_bitfield_default },
+	 { "RESOURCE29_RESET", 29, 29, &umr_bitfield_default },
+	 { "RESOURCE30_RESET", 30, 30, &umr_bitfield_default },
+	 { "RESOURCE31_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESET1[] = {
+	 { "RESOURCE32_RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE33_RESET", 1, 1, &umr_bitfield_default },
+	 { "RESOURCE34_RESET", 2, 2, &umr_bitfield_default },
+	 { "RESOURCE35_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESOURCE36_RESET", 4, 4, &umr_bitfield_default },
+	 { "RESOURCE37_RESET", 5, 5, &umr_bitfield_default },
+	 { "RESOURCE38_RESET", 6, 6, &umr_bitfield_default },
+	 { "RESOURCE39_RESET", 7, 7, &umr_bitfield_default },
+	 { "RESOURCE40_RESET", 8, 8, &umr_bitfield_default },
+	 { "RESOURCE41_RESET", 9, 9, &umr_bitfield_default },
+	 { "RESOURCE42_RESET", 10, 10, &umr_bitfield_default },
+	 { "RESOURCE43_RESET", 11, 11, &umr_bitfield_default },
+	 { "RESOURCE44_RESET", 12, 12, &umr_bitfield_default },
+	 { "RESOURCE45_RESET", 13, 13, &umr_bitfield_default },
+	 { "RESOURCE46_RESET", 14, 14, &umr_bitfield_default },
+	 { "RESOURCE47_RESET", 15, 15, &umr_bitfield_default },
+	 { "RESOURCE48_RESET", 16, 16, &umr_bitfield_default },
+	 { "RESOURCE49_RESET", 17, 17, &umr_bitfield_default },
+	 { "RESOURCE50_RESET", 18, 18, &umr_bitfield_default },
+	 { "RESOURCE51_RESET", 19, 19, &umr_bitfield_default },
+	 { "RESOURCE52_RESET", 20, 20, &umr_bitfield_default },
+	 { "RESOURCE53_RESET", 21, 21, &umr_bitfield_default },
+	 { "RESOURCE54_RESET", 22, 22, &umr_bitfield_default },
+	 { "RESOURCE55_RESET", 23, 23, &umr_bitfield_default },
+	 { "RESOURCE56_RESET", 24, 24, &umr_bitfield_default },
+	 { "RESOURCE57_RESET", 25, 25, &umr_bitfield_default },
+	 { "RESOURCE58_RESET", 26, 26, &umr_bitfield_default },
+	 { "RESOURCE59_RESET", 27, 27, &umr_bitfield_default },
+	 { "RESOURCE60_RESET", 28, 28, &umr_bitfield_default },
+	 { "RESOURCE61_RESET", 29, 29, &umr_bitfield_default },
+	 { "RESOURCE62_RESET", 30, 30, &umr_bitfield_default },
+	 { "RESOURCE63_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "RESOURCE_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_COMPUTE_MAX_WAVE_ID[] = {
+	 { "MAX_WAVE_ID", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RESET_MASK[] = {
+	 { "ME0_GFXHP3D_PIX_RESET", 0, 0, &umr_bitfield_default },
+	 { "ME0_GFXHP3D_VTX_RESET", 1, 1, &umr_bitfield_default },
+	 { "ME0_CS_RESET", 2, 2, &umr_bitfield_default },
+	 { "UNUSED0", 3, 3, &umr_bitfield_default },
+	 { "ME1_PIPE0_RESET", 4, 4, &umr_bitfield_default },
+	 { "ME1_PIPE1_RESET", 5, 5, &umr_bitfield_default },
+	 { "ME1_PIPE2_RESET", 6, 6, &umr_bitfield_default },
+	 { "ME1_PIPE3_RESET", 7, 7, &umr_bitfield_default },
+	 { "ME2_PIPE0_RESET", 8, 8, &umr_bitfield_default },
+	 { "ME2_PIPE1_RESET", 9, 9, &umr_bitfield_default },
+	 { "ME2_PIPE2_RESET", 10, 10, &umr_bitfield_default },
+	 { "ME2_PIPE3_RESET", 11, 11, &umr_bitfield_default },
+	 { "UNUSED1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RESET[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "PIPE_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ENHANCE[] = {
+	 { "MISC", 0, 15, &umr_bitfield_default },
+	 { "AUTO_INC_INDEX", 16, 16, &umr_bitfield_default },
+	 { "CGPG_RESTORE", 17, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_CGPG_RESTORE[] = {
+	 { "VMID", 0, 7, &umr_bitfield_default },
+	 { "MEID", 8, 11, &umr_bitfield_default },
+	 { "PIPEID", 12, 15, &umr_bitfield_default },
+	 { "QUEUEID", 16, 19, &umr_bitfield_default },
+	 { "UNUSED", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_STATUS[] = {
+	 { "R", 0, 0, &umr_bitfield_default },
+	 { "W", 1, 1, &umr_bitfield_default },
+	 { "UNUSED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_CS_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GFX_CTXSW_STATUS[] = {
+	 { "R", 0, 0, &umr_bitfield_default },
+	 { "W", 1, 1, &umr_bitfield_default },
+	 { "UNUSED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VS_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VS_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VS_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_VS_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS0_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS0_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS0_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS0_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS1_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS1_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS1_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS1_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS2_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS2_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS2_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS2_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS3_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS3_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS3_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS3_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS4_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS4_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS4_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS4_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS5_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS5_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS5_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS5_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS6_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS6_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS6_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS6_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS7_CTXSW_CNT0[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS7_CTXSW_CNT1[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS7_CTXSW_CNT2[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PS7_CTXSW_CNT3[] = {
+	 { "UPDN", 0, 15, &umr_bitfield_default },
+	 { "PTR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SIGNATURE_CONTROL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SIGNATURE_MASK[] = {
+	 { "INPUT_BUS_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SX_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_DB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_PA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_VGT_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE2[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE3[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE4[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE5[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE6[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SC_SIGNATURE7[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_IA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_IA_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SPI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_SPI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TA_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TD_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_CB_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_BCI_SIGNATURE0[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_BCI_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRAS_TA_SIGNATURE1[] = {
+	 { "SIGNATURE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG04[] = {
+	 { "clipsm0_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG4[] = {
+	 { "gws_busy", 0, 0, &umr_bitfield_default },
+	 { "gws_req", 1, 1, &umr_bitfield_default },
+	 { "gws_out_stall", 2, 2, &umr_bitfield_default },
+	 { "cur_reso", 3, 8, &umr_bitfield_default },
+	 { "cur_reso_head_valid", 9, 9, &umr_bitfield_default },
+	 { "cur_reso_head_dirty", 10, 10, &umr_bitfield_default },
+	 { "cur_reso_head_flag", 11, 11, &umr_bitfield_default },
+	 { "cur_reso_fed", 12, 12, &umr_bitfield_default },
+	 { "cur_reso_barrier", 13, 13, &umr_bitfield_default },
+	 { "cur_reso_flag", 14, 14, &umr_bitfield_default },
+	 { "cur_reso_cnt_gt0", 15, 15, &umr_bitfield_default },
+	 { "credit_cnt_gt0", 16, 16, &umr_bitfield_default },
+	 { "cmd_write", 17, 17, &umr_bitfield_default },
+	 { "grbm_gws_reso_wr", 18, 18, &umr_bitfield_default },
+	 { "grbm_gws_reso_rd", 19, 19, &umr_bitfield_default },
+	 { "ram_read_busy", 20, 20, &umr_bitfield_default },
+	 { "gws_bulkfree", 21, 21, &umr_bitfield_default },
+	 { "ram_gws_re", 22, 22, &umr_bitfield_default },
+	 { "ram_gws_we", 23, 23, &umr_bitfield_default },
+	 { "spare", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG4[] = {
+	 { "rbiu_spl_di_valid", 0, 0, &umr_bitfield_default },
+	 { "spl_rbiu_di_read", 1, 1, &umr_bitfield_default },
+	 { "rbiu_spl_p1_di_valid", 2, 2, &umr_bitfield_default },
+	 { "spl_rbiu_p1_di_read", 3, 3, &umr_bitfield_default },
+	 { "pipe0_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe0_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipe1_dr", 6, 6, &umr_bitfield_default },
+	 { "pipe1_rtr", 7, 7, &umr_bitfield_default },
+	 { "pipe2_dr", 8, 8, &umr_bitfield_default },
+	 { "pipe2_rtr", 9, 9, &umr_bitfield_default },
+	 { "pipe3_ld", 10, 10, &umr_bitfield_default },
+	 { "pipe3_rtr", 11, 11, &umr_bitfield_default },
+	 { "WD_IA_draw_send_d", 12, 12, &umr_bitfield_default },
+	 { "WD_IA_draw_rtr", 13, 13, &umr_bitfield_default },
+	 { "di_type_p0", 14, 15, &umr_bitfield_default },
+	 { "di_state_sel_p1_q", 16, 18, &umr_bitfield_default },
+	 { "di_wd_switch_on_eop_p1_q", 19, 19, &umr_bitfield_default },
+	 { "rbiu_spl_pipe0_lockout", 20, 20, &umr_bitfield_default },
+	 { "last_inst_of_di_p2", 21, 21, &umr_bitfield_default },
+	 { "last_sd_of_inst_p2", 22, 22, &umr_bitfield_default },
+	 { "last_sd_of_di_p2", 23, 23, &umr_bitfield_default },
+	 { "not_eop_wait_p1_q", 24, 24, &umr_bitfield_default },
+	 { "not_eop_wait_q", 25, 25, &umr_bitfield_default },
+	 { "ext_event_wait_p1_q", 26, 26, &umr_bitfield_default },
+	 { "ext_event_wait_q", 27, 27, &umr_bitfield_default },
+	 { "WD_IA1_draw_send_d", 28, 28, &umr_bitfield_default },
+	 { "WD_IA1_draw_rtr", 29, 29, &umr_bitfield_default },
+	 { "send_to_ia1_q", 30, 30, &umr_bitfield_default },
+	 { "dual_ia_mode", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "UNUSED_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "UNUSED_0", 14, 15, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "UNUSED_1", 26, 26, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "UNUSED_2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG05[] = {
+	 { "clipsm1_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG5[] = {
+	 { "write_dis", 0, 0, &umr_bitfield_default },
+	 { "dec_error", 1, 1, &umr_bitfield_default },
+	 { "alloc_opco_error", 2, 2, &umr_bitfield_default },
+	 { "dealloc_opco_error", 3, 3, &umr_bitfield_default },
+	 { "wrap_opco_error", 4, 4, &umr_bitfield_default },
+	 { "spare", 5, 7, &umr_bitfield_default },
+	 { "error_ds_address", 8, 21, &umr_bitfield_default },
+	 { "spare1", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG5[] = {
+	 { "p1_rbiu_spl_dr_valid", 0, 0, &umr_bitfield_default },
+	 { "SPARE0", 1, 1, &umr_bitfield_default },
+	 { "p1_pipe0_dr", 2, 2, &umr_bitfield_default },
+	 { "p1_pipe0_rtr", 3, 3, &umr_bitfield_default },
+	 { "p1_pipe1_dr", 4, 4, &umr_bitfield_default },
+	 { "p1_pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "p1_wd_subdma_fifo_empty", 6, 6, &umr_bitfield_default },
+	 { "p1_wd_subdma_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "p1_dma_buf_type_p0_q", 8, 9, &umr_bitfield_default },
+	 { "p1_dma_zero_indices_p0_q", 10, 10, &umr_bitfield_default },
+	 { "p1_dma_req_path_p3_q", 11, 11, &umr_bitfield_default },
+	 { "p1_dma_not_eop_p1_q", 12, 12, &umr_bitfield_default },
+	 { "p1_out_of_range_p4", 13, 13, &umr_bitfield_default },
+	 { "p1_last_sub_dma_p3_q", 14, 14, &umr_bitfield_default },
+	 { "p1_last_rdreq_of_sub_dma_p4", 15, 15, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_send_d", 16, 16, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_rtr", 17, 17, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_send_d", 18, 18, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_rtr", 19, 19, &umr_bitfield_default },
+	 { "p1_last_inst_of_dma_p2", 20, 20, &umr_bitfield_default },
+	 { "p1_last_sd_of_inst_p2", 21, 21, &umr_bitfield_default },
+	 { "p1_last_sd_of_dma_p2", 22, 22, &umr_bitfield_default },
+	 { "SPARE1", 23, 23, &umr_bitfield_default },
+	 { "p1_WD_IA_dma_busy", 24, 24, &umr_bitfield_default },
+	 { "p1_WD_IA1_dma_busy", 25, 25, &umr_bitfield_default },
+	 { "p1_send_to_ia1_p3_q", 26, 26, &umr_bitfield_default },
+	 { "p1_dma_wd_switch_on_eop_p3_q", 27, 27, &umr_bitfield_default },
+	 { "p1_pipe3_dr", 28, 28, &umr_bitfield_default },
+	 { "p1_pipe3_rtr", 29, 29, &umr_bitfield_default },
+	 { "p1_wd_dma2draw_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "p1_wd_dma2draw_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TD_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG06[] = {
+	 { "clipsm1_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGDS_DEBUG_REG6[] = {
+	 { "oa_busy", 0, 0, &umr_bitfield_default },
+	 { "counters_enabled", 1, 4, &umr_bitfield_default },
+	 { "counters_busy", 5, 20, &umr_bitfield_default },
+	 { "spare", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG6[] = {
+	 { "WD_IA_draw_eop", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "UNUSED_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "UNUSED_0", 14, 15, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "UNUSED_1", 26, 26, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "UNUSED_2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG07[] = {
+	 { "clipsm2_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG18[] = {
+	 { "grp_vr_valid", 0, 0, &umr_bitfield_default },
+	 { "pipe0_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe1_dr", 2, 2, &umr_bitfield_default },
+	 { "vr_grp_read", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "out_vr_indx_read", 6, 6, &umr_bitfield_default },
+	 { "out_vr_prim_read", 7, 7, &umr_bitfield_default },
+	 { "indices_to_send_q", 8, 10, &umr_bitfield_default },
+	 { "valid_indices", 11, 11, &umr_bitfield_default },
+	 { "last_indx_of_prim", 12, 12, &umr_bitfield_default },
+	 { "indx0_new_d", 13, 13, &umr_bitfield_default },
+	 { "indx1_new_d", 14, 14, &umr_bitfield_default },
+	 { "indx2_new_d", 15, 15, &umr_bitfield_default },
+	 { "indx2_hit_d", 16, 16, &umr_bitfield_default },
+	 { "indx1_hit_d", 17, 17, &umr_bitfield_default },
+	 { "indx0_hit_d", 18, 18, &umr_bitfield_default },
+	 { "st_vertex_reuse_off_r0_q", 19, 19, &umr_bitfield_default },
+	 { "last_group_of_instance_r0_q", 20, 20, &umr_bitfield_default },
+	 { "null_primitive_r0_q", 21, 21, &umr_bitfield_default },
+	 { "eop_r0_q", 22, 22, &umr_bitfield_default },
+	 { "eject_vtx_vect_r1_d", 23, 23, &umr_bitfield_default },
+	 { "sub_prim_type_r0_q", 24, 26, &umr_bitfield_default },
+	 { "gs_scenario_a_r0_q", 27, 27, &umr_bitfield_default },
+	 { "gs_scenario_b_r0_q", 28, 28, &umr_bitfield_default },
+	 { "components_valid_r0_q", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG7[] = {
+	 { "SE0VGT_WD_thdgrp_send_in", 0, 0, &umr_bitfield_default },
+	 { "wd_arb_se0_input_fifo_re", 1, 1, &umr_bitfield_default },
+	 { "wd_arb_se0_input_fifo_empty", 2, 2, &umr_bitfield_default },
+	 { "wd_arb_se0_input_fifo_full", 3, 3, &umr_bitfield_default },
+	 { "SE1VGT_WD_thdgrp_send_in", 4, 4, &umr_bitfield_default },
+	 { "wd_arb_se1_input_fifo_re", 5, 5, &umr_bitfield_default },
+	 { "wd_arb_se1_input_fifo_empty", 6, 6, &umr_bitfield_default },
+	 { "wd_arb_se1_input_fifo_full", 7, 7, &umr_bitfield_default },
+	 { "SPARE1", 8, 11, &umr_bitfield_default },
+	 { "SPARE2", 12, 15, &umr_bitfield_default },
+	 { "te11_arb_state_q", 16, 18, &umr_bitfield_default },
+	 { "SPARE5", 19, 19, &umr_bitfield_default },
+	 { "se0_thdgrp_is_event", 20, 20, &umr_bitfield_default },
+	 { "se0_thdgrp_eop", 21, 21, &umr_bitfield_default },
+	 { "se1_thdgrp_is_event", 22, 22, &umr_bitfield_default },
+	 { "se1_thdgrp_eop", 23, 23, &umr_bitfield_default },
+	 { "SPARE6", 24, 27, &umr_bitfield_default },
+	 { "tfreq_arb_tgroup_rtr", 28, 28, &umr_bitfield_default },
+	 { "arb_tfreq_tgroup_rts", 29, 29, &umr_bitfield_default },
+	 { "arb_tfreq_tgroup_event", 30, 30, &umr_bitfield_default },
+	 { "te11_arb_busy", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_TCP_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG08[] = {
+	 { "clipsm2_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSQ_DEBUG_STS_LOCAL[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "WAVE_LEVEL", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG8[] = {
+	 { "rcm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "rcm_noif_busy_q", 1, 1, &umr_bitfield_default },
+	 { "r1_inst_rtr", 2, 2, &umr_bitfield_default },
+	 { "spi_gsprim_fifo_busy_q", 3, 3, &umr_bitfield_default },
+	 { "spi_esvert_fifo_busy_q", 4, 4, &umr_bitfield_default },
+	 { "gs_tbl_valid_r3_q", 5, 5, &umr_bitfield_default },
+	 { "valid_r0_q", 6, 6, &umr_bitfield_default },
+	 { "valid_r1_q", 7, 7, &umr_bitfield_default },
+	 { "valid_r2", 8, 8, &umr_bitfield_default },
+	 { "valid_r2_q", 9, 9, &umr_bitfield_default },
+	 { "r0_rtr", 10, 10, &umr_bitfield_default },
+	 { "r1_rtr", 11, 11, &umr_bitfield_default },
+	 { "r2_indx_rtr", 12, 12, &umr_bitfield_default },
+	 { "r2_rtr", 13, 13, &umr_bitfield_default },
+	 { "es_gs_rtr", 14, 14, &umr_bitfield_default },
+	 { "gs_event_fifo_rtr", 15, 15, &umr_bitfield_default },
+	 { "tm_rcm_gs_event_rtr", 16, 16, &umr_bitfield_default },
+	 { "gs_tbl_r3_rtr", 17, 17, &umr_bitfield_default },
+	 { "prim_skid_fifo_empty", 18, 18, &umr_bitfield_default },
+	 { "VGT_SPI_gsprim_rtr_q", 19, 19, &umr_bitfield_default },
+	 { "tm_rcm_gs_tbl_rtr", 20, 20, &umr_bitfield_default },
+	 { "tm_rcm_es_tbl_rtr", 21, 21, &umr_bitfield_default },
+	 { "VGT_SPI_esvert_rtr_q", 22, 22, &umr_bitfield_default },
+	 { "r2_no_bp_rtr", 23, 23, &umr_bitfield_default },
+	 { "hold_for_es_flush", 24, 24, &umr_bitfield_default },
+	 { "gs_event_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "gsprim_buff_empty_q", 26, 26, &umr_bitfield_default },
+	 { "gsprim_buff_full_q", 27, 27, &umr_bitfield_default },
+	 { "te_prim_fifo_empty", 28, 28, &umr_bitfield_default },
+	 { "te_prim_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "te_vert_fifo_empty", 30, 30, &umr_bitfield_default },
+	 { "te_vert_fifo_full", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG8[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipe1_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe0_rtr", 2, 2, &umr_bitfield_default },
+	 { "pipe1_rtr", 3, 3, &umr_bitfield_default },
+	 { "tfreq_tg_fifo_empty", 4, 4, &umr_bitfield_default },
+	 { "tfreq_tg_fifo_full", 5, 5, &umr_bitfield_default },
+	 { "tf_data_fifo_busy_q", 6, 6, &umr_bitfield_default },
+	 { "tf_data_fifo_rtr_q", 7, 7, &umr_bitfield_default },
+	 { "tf_skid_fifo_empty", 8, 8, &umr_bitfield_default },
+	 { "tf_skid_fifo_full", 9, 9, &umr_bitfield_default },
+	 { "wd_tc_rdreq_rtr_q", 10, 10, &umr_bitfield_default },
+	 { "last_req_of_tg_p2", 11, 11, &umr_bitfield_default },
+	 { "se0spi_wd_hs_done_cnt_q", 12, 17, &umr_bitfield_default },
+	 { "event_flag_p1_q", 18, 18, &umr_bitfield_default },
+	 { "null_flag_p1_q", 19, 19, &umr_bitfield_default },
+	 { "tf_data_fifo_cnt_q", 20, 26, &umr_bitfield_default },
+	 { "second_tf_ret_data_q", 27, 27, &umr_bitfield_default },
+	 { "first_req_of_tg_p1_q", 28, 28, &umr_bitfield_default },
+	 { "WD_TC_rdreq_send_out", 29, 29, &umr_bitfield_default },
+	 { "WD_TC_rdnfo_stall_out", 30, 30, &umr_bitfield_default },
+	 { "TC_WD_rdret_valid_in", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_CTRL0[] = {
+	 { "DIDT_CTRL_EN", 0, 0, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 1, 1, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 2, 3, &umr_bitfield_default },
+	 { "DIDT_CTRL_RST", 4, 4, &umr_bitfield_default },
+	 { "DIDT_CLK_EN_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "UNUSED_0", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_CTRL1[] = {
+	 { "MIN_POWER", 0, 15, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_CTRL2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "UNUSED_0", 14, 15, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "UNUSED_1", 26, 26, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "UNUSED_2", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_CTRL_OCP[] = {
+	 { "UNUSED_0", 0, 15, &umr_bitfield_default },
+	 { "OCP_MAX_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG09[] = {
+	 { "clipsm3_clprim_to_clip_clip_code_or", 0, 13, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event_id", 14, 19, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_state_var_indx", 20, 22, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_clip_primitive", 23, 23, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_deallocate_slot", 24, 26, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_first_prim_of_slot", 27, 27, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_end_of_packet", 28, 28, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG9[] = {
+	 { "indices_to_send_r2_q", 0, 1, &umr_bitfield_default },
+	 { "valid_indices_r3", 2, 2, &umr_bitfield_default },
+	 { "gs_eov_r3", 3, 3, &umr_bitfield_default },
+	 { "eop_indx_r3", 4, 4, &umr_bitfield_default },
+	 { "eop_prim_r3", 5, 5, &umr_bitfield_default },
+	 { "es_eov_r3", 6, 6, &umr_bitfield_default },
+	 { "es_tbl_state_r3_q_0", 7, 7, &umr_bitfield_default },
+	 { "pending_es_send_r3_q", 8, 8, &umr_bitfield_default },
+	 { "pending_es_flush_r3", 9, 9, &umr_bitfield_default },
+	 { "gs_tbl_num_es_per_gs_r3_q_not_0", 10, 10, &umr_bitfield_default },
+	 { "gs_tbl_prim_cnt_r3_q", 11, 17, &umr_bitfield_default },
+	 { "gs_tbl_eop_r3_q", 18, 18, &umr_bitfield_default },
+	 { "gs_tbl_state_r3_q", 19, 21, &umr_bitfield_default },
+	 { "gs_pending_state_r3_q", 22, 22, &umr_bitfield_default },
+	 { "invalidate_rb_roll_over_q", 23, 23, &umr_bitfield_default },
+	 { "gs_instancing_state_q", 24, 24, &umr_bitfield_default },
+	 { "es_per_gs_vert_cnt_r3_q_not_0", 25, 25, &umr_bitfield_default },
+	 { "gs_prim_per_es_ctr_r3_q_not_0", 26, 26, &umr_bitfield_default },
+	 { "pre_r0_rtr", 27, 27, &umr_bitfield_default },
+	 { "valid_r3_q", 28, 28, &umr_bitfield_default },
+	 { "valid_pre_r0_q", 29, 29, &umr_bitfield_default },
+	 { "SPARE0", 30, 30, &umr_bitfield_default },
+	 { "off_chip_hs_r2_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG9[] = {
+	 { "pipe0_dr", 0, 0, &umr_bitfield_default },
+	 { "pipec_tf_dr", 1, 1, &umr_bitfield_default },
+	 { "pipe2_dr", 2, 2, &umr_bitfield_default },
+	 { "event_or_null_flags_p0_q", 3, 3, &umr_bitfield_default },
+	 { "pipe0_rtr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_rtr", 5, 5, &umr_bitfield_default },
+	 { "pipec_tf_rtr", 6, 6, &umr_bitfield_default },
+	 { "pipe2_rtr", 7, 7, &umr_bitfield_default },
+	 { "ttp_patch_fifo_full", 8, 8, &umr_bitfield_default },
+	 { "ttp_patch_fifo_empty", 9, 9, &umr_bitfield_default },
+	 { "ttp_tf_fifo_empty", 10, 10, &umr_bitfield_default },
+	 { "SPARE0", 11, 15, &umr_bitfield_default },
+	 { "tf_fetch_state_q", 16, 18, &umr_bitfield_default },
+	 { "last_patch_of_tg", 19, 19, &umr_bitfield_default },
+	 { "tf_pointer_p0_q", 20, 23, &umr_bitfield_default },
+	 { "dynamic_hs_p0_q", 24, 24, &umr_bitfield_default },
+	 { "first_fetch_of_tg_p0_q", 25, 25, &umr_bitfield_default },
+	 { "mem_is_even", 26, 26, &umr_bitfield_default },
+	 { "SPARE1", 27, 27, &umr_bitfield_default },
+	 { "SPARE2", 28, 29, &umr_bitfield_default },
+	 { "pipe4_dr", 30, 30, &umr_bitfield_default },
+	 { "pipe4_rtr", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_WEIGHT0_3[] = {
+	 { "WEIGHT0", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT1", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT2", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_WEIGHT4_7[] = {
+	 { "WEIGHT4", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT5", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT6", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDIDT_DBR_WEIGHT8_11[] = {
+	 { "WEIGHT8", 0, 7, &umr_bitfield_default },
+	 { "WEIGHT9", 8, 15, &umr_bitfield_default },
+	 { "WEIGHT10", 16, 23, &umr_bitfield_default },
+	 { "WEIGHT11", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG10[] = {
+	 { "clipsm3_clprim_to_clip_param_cache_indx_0", 1, 10, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_2", 11, 16, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_1", 17, 22, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_vertex_store_indx_0", 23, 28, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_event", 29, 29, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_null_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG10[] = {
+	 { "index_buffer_depth_r1_q", 0, 4, &umr_bitfield_default },
+	 { "eopg_r2_q", 5, 5, &umr_bitfield_default },
+	 { "eotg_r2_q", 6, 6, &umr_bitfield_default },
+	 { "onchip_gs_en_r0_q", 7, 8, &umr_bitfield_default },
+	 { "SPARE2", 9, 10, &umr_bitfield_default },
+	 { "rcm_mem_gsprim_re_qq", 11, 11, &umr_bitfield_default },
+	 { "rcm_mem_gsprim_re_q", 12, 12, &umr_bitfield_default },
+	 { "gs_rb_space_avail_r3_q_9_0", 13, 22, &umr_bitfield_default },
+	 { "es_rb_space_avail_r2_q_8_0", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWD_DEBUG_REG10[] = {
+	 { "ttp_pd_patch_rts", 0, 0, &umr_bitfield_default },
+	 { "ttp_pd_is_event", 1, 1, &umr_bitfield_default },
+	 { "ttp_pd_eopg", 2, 2, &umr_bitfield_default },
+	 { "ttp_pd_eop", 3, 3, &umr_bitfield_default },
+	 { "pipe0_dr", 4, 4, &umr_bitfield_default },
+	 { "pipe1_dr", 5, 5, &umr_bitfield_default },
+	 { "pipe0_rtr", 6, 6, &umr_bitfield_default },
+	 { "pipe1_rtr", 7, 7, &umr_bitfield_default },
+	 { "donut_en_p1_q", 8, 8, &umr_bitfield_default },
+	 { "donut_se_switch_p2", 9, 9, &umr_bitfield_default },
+	 { "patch_se_switch_p2", 10, 10, &umr_bitfield_default },
+	 { "last_donut_switch_p2", 11, 11, &umr_bitfield_default },
+	 { "last_donut_of_patch_p2", 12, 12, &umr_bitfield_default },
+	 { "is_event_p1_q", 13, 13, &umr_bitfield_default },
+	 { "eopg_p1_q", 14, 14, &umr_bitfield_default },
+	 { "eop_p1_q", 15, 15, &umr_bitfield_default },
+	 { "patch_accum_q", 16, 23, &umr_bitfield_default },
+	 { "wd_te11_out_se0_fifo_full", 24, 24, &umr_bitfield_default },
+	 { "wd_te11_out_se0_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "wd_te11_out_se1_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "wd_te11_out_se1_fifo_empty", 27, 27, &umr_bitfield_default },
+	 { "wd_te11_out_se2_fifo_full", 28, 28, &umr_bitfield_default },
+	 { "wd_te11_out_se2_fifo_empty", 29, 29, &umr_bitfield_default },
+	 { "wd_te11_out_se3_fifo_full", 30, 30, &umr_bitfield_default },
+	 { "wd_te11_out_se3_fifo_empty", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_CONTROL[] = {
+	 { "DEPTH_CLEAR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCIL_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "DEPTH_COPY", 2, 2, &umr_bitfield_default },
+	 { "STENCIL_COPY", 3, 3, &umr_bitfield_default },
+	 { "RESUMMARIZE_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "STENCIL_COMPRESS_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "DEPTH_COMPRESS_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "COPY_CENTROID", 7, 7, &umr_bitfield_default },
+	 { "COPY_SAMPLE", 8, 11, &umr_bitfield_default },
+	 { "DECOMPRESS_ENABLE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_COUNT_CONTROL[] = {
+	 { "ZPASS_INCREMENT_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "PERFECT_ZPASS_COUNTS", 1, 1, &umr_bitfield_default },
+	 { "SAMPLE_RATE", 4, 6, &umr_bitfield_default },
+	 { "ZPASS_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "ZFAIL_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "SFAIL_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "DBFAIL_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "SLICE_EVEN_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+	 { "Z_READ_ONLY", 24, 24, &umr_bitfield_default },
+	 { "STENCIL_READ_ONLY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_OVERRIDE[] = {
+	 { "FORCE_HIZ_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE0", 2, 3, &umr_bitfield_default },
+	 { "FORCE_HIS_ENABLE1", 4, 5, &umr_bitfield_default },
+	 { "FORCE_SHADER_Z_ORDER", 6, 6, &umr_bitfield_default },
+	 { "FAST_Z_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "FAST_STENCIL_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "NOOP_CULL_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "FORCE_COLOR_KILL", 10, 10, &umr_bitfield_default },
+	 { "FORCE_Z_READ", 11, 11, &umr_bitfield_default },
+	 { "FORCE_STENCIL_READ", 12, 12, &umr_bitfield_default },
+	 { "FORCE_FULL_Z_RANGE", 13, 14, &umr_bitfield_default },
+	 { "FORCE_QC_SMASK_CONFLICT", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_VIEWPORT_CLAMP", 16, 16, &umr_bitfield_default },
+	 { "IGNORE_SC_ZRANGE", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_FULLY_COVERED", 18, 18, &umr_bitfield_default },
+	 { "FORCE_Z_LIMIT_SUMM", 19, 20, &umr_bitfield_default },
+	 { "MAX_TILES_IN_DTT", 21, 25, &umr_bitfield_default },
+	 { "DISABLE_TILE_RATE_TILES", 26, 26, &umr_bitfield_default },
+	 { "FORCE_Z_DIRTY", 27, 27, &umr_bitfield_default },
+	 { "FORCE_STENCIL_DIRTY", 28, 28, &umr_bitfield_default },
+	 { "FORCE_Z_VALID", 29, 29, &umr_bitfield_default },
+	 { "FORCE_STENCIL_VALID", 30, 30, &umr_bitfield_default },
+	 { "PRESERVE_COMPRESSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_RENDER_OVERRIDE2[] = {
+	 { "PARTIAL_SQUAD_LAUNCH_CONTROL", 0, 1, &umr_bitfield_default },
+	 { "PARTIAL_SQUAD_LAUNCH_COUNTDOWN", 2, 4, &umr_bitfield_default },
+	 { "DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_SMEM_EXPCLEAR_OPTIMIZATION", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_COLOR_ON_VALIDATION", 7, 7, &umr_bitfield_default },
+	 { "DECOMPRESS_Z_ON_FLUSH", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_REG_SNOOP", 9, 9, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_HIER_DEPTH_DISABLE", 10, 10, &umr_bitfield_default },
+	 { "SEPARATE_HIZS_FUNC_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "HIZ_ZFUNC", 12, 14, &umr_bitfield_default },
+	 { "HIS_SFUNC_FF", 15, 17, &umr_bitfield_default },
+	 { "HIS_SFUNC_BF", 18, 20, &umr_bitfield_default },
+	 { "PRESERVE_ZRANGE", 21, 21, &umr_bitfield_default },
+	 { "PRESERVE_SRESULTS", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_FAST_PASS", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_HTILE_DATA_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_BOUNDS_MIN[] = {
+	 { "MIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_BOUNDS_MAX[] = {
+	 { "MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_CLEAR[] = {
+	 { "CLEAR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_CLEAR[] = {
+	 { "DEPTH_CLEAR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_TL[] = {
+	 { "TL_X", 0, 15, &umr_bitfield_default },
+	 { "TL_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_SCISSOR_BR[] = {
+	 { "BR_X", 0, 15, &umr_bitfield_default },
+	 { "BR_Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_INFO[] = {
+	 { "ADDR5_SWIZZLE_MASK", 0, 3, &umr_bitfield_default },
+	 { "ARRAY_MODE", 4, 7, &umr_bitfield_default },
+	 { "PIPE_CONFIG", 8, 12, &umr_bitfield_default },
+	 { "BANK_WIDTH", 13, 14, &umr_bitfield_default },
+	 { "BANK_HEIGHT", 15, 16, &umr_bitfield_default },
+	 { "MACRO_TILE_ASPECT", 17, 18, &umr_bitfield_default },
+	 { "NUM_BANKS", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_INFO[] = {
+	 { "FORMAT", 0, 1, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 2, 3, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "DECOMPRESS_ON_N_ZPLANES", 23, 26, &umr_bitfield_default },
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "READ_SIZE", 28, 28, &umr_bitfield_default },
+	 { "TILE_SURFACE_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "CLEAR_DISALLOWED", 30, 30, &umr_bitfield_default },
+	 { "ZRANGE_PRECISION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_INFO[] = {
+	 { "FORMAT", 0, 0, &umr_bitfield_default },
+	 { "TILE_SPLIT", 13, 15, &umr_bitfield_default },
+	 { "TILE_MODE_INDEX", 20, 22, &umr_bitfield_default },
+	 { "ALLOW_EXPCLEAR", 27, 27, &umr_bitfield_default },
+	 { "TILE_STENCIL_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "CLEAR_DISALLOWED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_READ_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_Z_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_WRITE_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_SIZE[] = {
+	 { "PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "HEIGHT_TILE_MAX", 11, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_SLICE[] = {
+	 { "SLICE_TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_BC_BASE_ADDR_HI[] = {
+	 { "ADDRESS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_0[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_1[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_2[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_HI_3[] = {
+	 { "DEST_BASE_HI_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_2[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_3[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_OFFSET[] = {
+	 { "WINDOW_X_OFFSET", 0, 15, &umr_bitfield_default },
+	 { "WINDOW_Y_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_WINDOW_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_RULE[] = {
+	 { "CLIP_RULE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CLIPRECT_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_EDGERULE[] = {
+	 { "ER_TRI", 0, 3, &umr_bitfield_default },
+	 { "ER_POINT", 4, 7, &umr_bitfield_default },
+	 { "ER_RECT", 8, 11, &umr_bitfield_default },
+	 { "ER_LINE_LR", 12, 17, &umr_bitfield_default },
+	 { "ER_LINE_RL", 18, 23, &umr_bitfield_default },
+	 { "ER_LINE_TB", 24, 27, &umr_bitfield_default },
+	 { "ER_LINE_BT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_HARDWARE_SCREEN_OFFSET[] = {
+	 { "HW_SCREEN_OFFSET_X", 0, 8, &umr_bitfield_default },
+	 { "HW_SCREEN_OFFSET_Y", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_TARGET_MASK[] = {
+	 { "TARGET0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "TARGET1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "TARGET2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "TARGET3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "TARGET4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "TARGET5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "TARGET6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "TARGET7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_SHADER_MASK[] = {
+	 { "OUTPUT0_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "OUTPUT1_ENABLE", 4, 7, &umr_bitfield_default },
+	 { "OUTPUT2_ENABLE", 8, 11, &umr_bitfield_default },
+	 { "OUTPUT3_ENABLE", 12, 15, &umr_bitfield_default },
+	 { "OUTPUT4_ENABLE", 16, 19, &umr_bitfield_default },
+	 { "OUTPUT5_ENABLE", 20, 23, &umr_bitfield_default },
+	 { "OUTPUT6_ENABLE", 24, 27, &umr_bitfield_default },
+	 { "OUTPUT7_ENABLE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_GENERIC_SCISSOR_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_0[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCOHER_DEST_BASE_1[] = {
+	 { "DEST_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_0_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_1_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_2_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_3_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_4_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_5_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_6_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_7_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_8_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_9_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_10_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_11_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_12_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_13_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_14_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_TL[] = {
+	 { "TL_X", 0, 14, &umr_bitfield_default },
+	 { "TL_Y", 16, 30, &umr_bitfield_default },
+	 { "WINDOW_OFFSET_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_SCISSOR_15_BR[] = {
+	 { "BR_X", 0, 14, &umr_bitfield_default },
+	 { "BR_Y", 16, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_0[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_0[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_1[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_1[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_2[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_2[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_3[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_3[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_4[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_4[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_5[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_5[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_6[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_6[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_7[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_7[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_8[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_8[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_9[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_9[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_10[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_10[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_11[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_11[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_12[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_12[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_13[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_13[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_14[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_14[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMIN_15[] = {
+	 { "VPORT_ZMIN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_VPORT_ZMAX_15[] = {
+	 { "VPORT_ZMAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_RASTER_CONFIG[] = {
+	 { "RB_MAP_PKR0", 0, 1, &umr_bitfield_default },
+	 { "RB_MAP_PKR1", 2, 3, &umr_bitfield_default },
+	 { "RB_XSEL2", 4, 5, &umr_bitfield_default },
+	 { "RB_XSEL", 6, 6, &umr_bitfield_default },
+	 { "RB_YSEL", 7, 7, &umr_bitfield_default },
+	 { "PKR_MAP", 8, 9, &umr_bitfield_default },
+	 { "PKR_XSEL", 10, 11, &umr_bitfield_default },
+	 { "PKR_YSEL", 12, 13, &umr_bitfield_default },
+	 { "PKR_XSEL2", 14, 15, &umr_bitfield_default },
+	 { "SC_MAP", 16, 17, &umr_bitfield_default },
+	 { "SC_XSEL", 18, 19, &umr_bitfield_default },
+	 { "SC_YSEL", 20, 21, &umr_bitfield_default },
+	 { "SE_MAP", 24, 25, &umr_bitfield_default },
+	 { "SE_XSEL", 26, 27, &umr_bitfield_default },
+	 { "SE_YSEL", 28, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_RASTER_CONFIG_1[] = {
+	 { "SE_PAIR_MAP", 0, 1, &umr_bitfield_default },
+	 { "SE_PAIR_XSEL", 2, 3, &umr_bitfield_default },
+	 { "SE_PAIR_YSEL", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_CONTROL[] = {
+	 { "SLICE_EVEN_ENABLE", 0, 1, &umr_bitfield_default },
+	 { "SLICE_ODD_ENABLE", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PERFMON_CNTX_CNTL[] = {
+	 { "PERFMON_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RINGID[] = {
+	 { "RINGID", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VMID[] = {
+	 { "VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MAX_VTX_INDX[] = {
+	 { "MAX_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MIN_VTX_INDX[] = {
+	 { "MIN_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INDX_OFFSET[] = {
+	 { "INDX_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_INDX[] = {
+	 { "RESET_INDX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_RED[] = {
+	 { "BLEND_RED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_GREEN[] = {
+	 { "BLEND_GREEN", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_BLUE[] = {
+	 { "BLEND_BLUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND_ALPHA[] = {
+	 { "BLEND_ALPHA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "OVERWRITE_COMBINER_MRT_SHARING_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "OVERWRITE_COMBINER_WATERMARK", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCIL_CONTROL[] = {
+	 { "STENCILFAIL", 0, 3, &umr_bitfield_default },
+	 { "STENCILZPASS", 4, 7, &umr_bitfield_default },
+	 { "STENCILZFAIL", 8, 11, &umr_bitfield_default },
+	 { "STENCILFAIL_BF", 12, 15, &umr_bitfield_default },
+	 { "STENCILZPASS_BF", 16, 19, &umr_bitfield_default },
+	 { "STENCILZFAIL_BF", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCILREFMASK[] = {
+	 { "STENCILTESTVAL", 0, 7, &umr_bitfield_default },
+	 { "STENCILMASK", 8, 15, &umr_bitfield_default },
+	 { "STENCILWRITEMASK", 16, 23, &umr_bitfield_default },
+	 { "STENCILOPVAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_STENCILREFMASK_BF[] = {
+	 { "STENCILTESTVAL_BF", 0, 7, &umr_bitfield_default },
+	 { "STENCILMASK_BF", 8, 15, &umr_bitfield_default },
+	 { "STENCILWRITEMASK_BF", 16, 23, &umr_bitfield_default },
+	 { "STENCILOPVAL_BF", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_1[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_1[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_1[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_1[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_1[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_1[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_2[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_2[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_2[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_2[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_2[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_2[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_3[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_3[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_3[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_3[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_3[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_3[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_4[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_4[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_4[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_4[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_4[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_4[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_5[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_5[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_5[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_5[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_5[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_5[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_6[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_6[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_6[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_6[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_6[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_6[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_7[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_7[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_7[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_7[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_7[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_7[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_8[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_8[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_8[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_8[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_8[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_8[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_9[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_9[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_9[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_9[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_9[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_9[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_10[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_10[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_10[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_10[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_10[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_10[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_11[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_11[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_11[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_11[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_11[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_11[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_12[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_12[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_12[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_12[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_12[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_12[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_13[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_13[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_13[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_13[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_13[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_13[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_14[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_14[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_14[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_14[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_14[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_14[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XSCALE_15[] = {
+	 { "VPORT_XSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_XOFFSET_15[] = {
+	 { "VPORT_XOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YSCALE_15[] = {
+	 { "VPORT_YSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_YOFFSET_15[] = {
+	 { "VPORT_YOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZSCALE_15[] = {
+	 { "VPORT_ZSCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VPORT_ZOFFSET_15[] = {
+	 { "VPORT_ZOFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_0_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_1_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_2_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_3_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_4_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_X[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_Y[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_Z[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_UCP_5_W[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_0[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_1[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_2[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_3[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_4[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_5[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_6[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_7[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_8[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_9[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_10[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_11[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_12[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_13[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_14[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_15[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_16[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_17[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_18[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_19[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "CYL_WRAP", 13, 16, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX", 17, 17, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "PT_SPRITE_TEX_ATTR1", 23, 23, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_20[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_21[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_22[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_23[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_24[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_25[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_26[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_27[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_28[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_29[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_30[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_CNTL_31[] = {
+	 { "OFFSET", 0, 5, &umr_bitfield_default },
+	 { "DEFAULT_VAL", 8, 9, &umr_bitfield_default },
+	 { "FLAT_SHADE", 10, 10, &umr_bitfield_default },
+	 { "DUP", 18, 18, &umr_bitfield_default },
+	 { "FP16_INTERP_MODE", 19, 19, &umr_bitfield_default },
+	 { "USE_DEFAULT_ATTR1", 20, 20, &umr_bitfield_default },
+	 { "DEFAULT_VAL_ATTR1", 21, 22, &umr_bitfield_default },
+	 { "ATTR0_VALID", 24, 24, &umr_bitfield_default },
+	 { "ATTR1_VALID", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_VS_OUT_CONFIG[] = {
+	 { "VS_EXPORT_COUNT", 1, 5, &umr_bitfield_default },
+	 { "VS_HALF_PACK", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_ENA[] = {
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_INPUT_ADDR[] = {
+	 { "PERSP_SAMPLE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTER_ENA", 1, 1, &umr_bitfield_default },
+	 { "PERSP_CENTROID_ENA", 2, 2, &umr_bitfield_default },
+	 { "PERSP_PULL_MODEL_ENA", 3, 3, &umr_bitfield_default },
+	 { "LINEAR_SAMPLE_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_ENA", 5, 5, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_ENA", 6, 6, &umr_bitfield_default },
+	 { "LINE_STIPPLE_TEX_ENA", 7, 7, &umr_bitfield_default },
+	 { "POS_X_FLOAT_ENA", 8, 8, &umr_bitfield_default },
+	 { "POS_Y_FLOAT_ENA", 9, 9, &umr_bitfield_default },
+	 { "POS_Z_FLOAT_ENA", 10, 10, &umr_bitfield_default },
+	 { "POS_W_FLOAT_ENA", 11, 11, &umr_bitfield_default },
+	 { "FRONT_FACE_ENA", 12, 12, &umr_bitfield_default },
+	 { "ANCILLARY_ENA", 13, 13, &umr_bitfield_default },
+	 { "SAMPLE_COVERAGE_ENA", 14, 14, &umr_bitfield_default },
+	 { "POS_FIXED_PT_ENA", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_INTERP_CONTROL_0[] = {
+	 { "FLAT_SHADE_ENA", 0, 0, &umr_bitfield_default },
+	 { "PNT_SPRITE_ENA", 1, 1, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_X", 2, 4, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Y", 5, 7, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_Z", 8, 10, &umr_bitfield_default },
+	 { "PNT_SPRITE_OVRD_W", 11, 13, &umr_bitfield_default },
+	 { "PNT_SPRITE_TOP_1", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PS_IN_CONTROL[] = {
+	 { "NUM_INTERP", 0, 5, &umr_bitfield_default },
+	 { "PARAM_GEN", 6, 6, &umr_bitfield_default },
+	 { "BC_OPTIMIZE_DISABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_BARYC_CNTL[] = {
+	 { "PERSP_CENTER_CNTL", 0, 0, &umr_bitfield_default },
+	 { "PERSP_CENTROID_CNTL", 4, 4, &umr_bitfield_default },
+	 { "LINEAR_CENTER_CNTL", 8, 8, &umr_bitfield_default },
+	 { "LINEAR_CENTROID_CNTL", 12, 12, &umr_bitfield_default },
+	 { "POS_FLOAT_LOCATION", 16, 17, &umr_bitfield_default },
+	 { "POS_FLOAT_ULC", 20, 20, &umr_bitfield_default },
+	 { "FRONT_FACE_ALL_BITS", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_TMPRING_SIZE[] = {
+	 { "WAVES", 0, 11, &umr_bitfield_default },
+	 { "WAVESIZE", 12, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_POS_FORMAT[] = {
+	 { "POS0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "POS1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "POS2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "POS3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_Z_FORMAT[] = {
+	 { "Z_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_SHADER_COL_FORMAT[] = {
+	 { "COL0_EXPORT_FORMAT", 0, 3, &umr_bitfield_default },
+	 { "COL1_EXPORT_FORMAT", 4, 7, &umr_bitfield_default },
+	 { "COL2_EXPORT_FORMAT", 8, 11, &umr_bitfield_default },
+	 { "COL3_EXPORT_FORMAT", 12, 15, &umr_bitfield_default },
+	 { "COL4_EXPORT_FORMAT", 16, 19, &umr_bitfield_default },
+	 { "COL5_EXPORT_FORMAT", 20, 23, &umr_bitfield_default },
+	 { "COL6_EXPORT_FORMAT", 24, 27, &umr_bitfield_default },
+	 { "COL7_EXPORT_FORMAT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PS_DOWNCONVERT[] = {
+	 { "MRT0", 0, 3, &umr_bitfield_default },
+	 { "MRT1", 4, 7, &umr_bitfield_default },
+	 { "MRT2", 8, 11, &umr_bitfield_default },
+	 { "MRT3", 12, 15, &umr_bitfield_default },
+	 { "MRT4", 16, 19, &umr_bitfield_default },
+	 { "MRT5", 20, 23, &umr_bitfield_default },
+	 { "MRT6", 24, 27, &umr_bitfield_default },
+	 { "MRT7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_BLEND_OPT_EPSILON[] = {
+	 { "MRT0_EPSILON", 0, 3, &umr_bitfield_default },
+	 { "MRT1_EPSILON", 4, 7, &umr_bitfield_default },
+	 { "MRT2_EPSILON", 8, 11, &umr_bitfield_default },
+	 { "MRT3_EPSILON", 12, 15, &umr_bitfield_default },
+	 { "MRT4_EPSILON", 16, 19, &umr_bitfield_default },
+	 { "MRT5_EPSILON", 20, 23, &umr_bitfield_default },
+	 { "MRT6_EPSILON", 24, 27, &umr_bitfield_default },
+	 { "MRT7_EPSILON", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_BLEND_OPT_CONTROL[] = {
+	 { "MRT0_COLOR_OPT_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "MRT0_ALPHA_OPT_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "MRT1_COLOR_OPT_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MRT1_ALPHA_OPT_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "MRT2_COLOR_OPT_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "MRT2_ALPHA_OPT_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "MRT3_COLOR_OPT_DISABLE", 12, 12, &umr_bitfield_default },
+	 { "MRT3_ALPHA_OPT_DISABLE", 13, 13, &umr_bitfield_default },
+	 { "MRT4_COLOR_OPT_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "MRT4_ALPHA_OPT_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "MRT5_COLOR_OPT_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "MRT5_ALPHA_OPT_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "MRT6_COLOR_OPT_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "MRT6_ALPHA_OPT_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "MRT7_COLOR_OPT_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "MRT7_ALPHA_OPT_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "PIXEN_ZERO_OPT_DISABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_MRT0_BLEND_OPT[] = {
+	 { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default },
+	 { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default },
+	 { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_MRT1_BLEND_OPT[] = {
+	 { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default },
+	 { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default },
+	 { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_MRT2_BLEND_OPT[] = {
+	 { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default },
+	 { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default },
+	 { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_MRT3_BLEND_OPT[] = {
+	 { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default },
+	 { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default },
+	 { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_MRT4_BLEND_OPT[] = {
+	 { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default },
+	 { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default },
+	 { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_MRT5_BLEND_OPT[] = {
+	 { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default },
+	 { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default },
+	 { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_MRT6_BLEND_OPT[] = {
+	 { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default },
+	 { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default },
+	 { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_MRT7_BLEND_OPT[] = {
+	 { "COLOR_SRC_OPT", 0, 2, &umr_bitfield_default },
+	 { "COLOR_DST_OPT", 4, 6, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_SRC_OPT", 16, 18, &umr_bitfield_default },
+	 { "ALPHA_DST_OPT", 20, 22, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND0_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND1_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND2_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND3_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND4_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND5_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND6_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_BLEND7_CONTROL[] = {
+	 { "COLOR_SRCBLEND", 0, 4, &umr_bitfield_default },
+	 { "COLOR_COMB_FCN", 5, 7, &umr_bitfield_default },
+	 { "COLOR_DESTBLEND", 8, 12, &umr_bitfield_default },
+	 { "ALPHA_SRCBLEND", 16, 20, &umr_bitfield_default },
+	 { "ALPHA_COMB_FCN", 21, 23, &umr_bitfield_default },
+	 { "ALPHA_DESTBLEND", 24, 28, &umr_bitfield_default },
+	 { "SEPARATE_ALPHA_BLEND", 29, 29, &umr_bitfield_default },
+	 { "ENABLE", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_ROP3", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCS_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGFX_COPY_STATE[] = {
+	 { "SRC_STATE_ID", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_X_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_Y_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_SIZE[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_POINT_CULL_RAD[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_BASE_HI[] = {
+	 { "BASE_ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_BASE[] = {
+	 { "BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DRAW_INITIATOR[] = {
+	 { "SOURCE_SELECT", 0, 1, &umr_bitfield_default },
+	 { "MAJOR_MODE", 2, 3, &umr_bitfield_default },
+	 { "SPRITE_EN_R6XX", 4, 4, &umr_bitfield_default },
+	 { "NOT_EOP", 5, 5, &umr_bitfield_default },
+	 { "USE_OPAQUE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_IMMED_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_EVENT_ADDRESS_REG[] = {
+	 { "ADDRESS_LOW", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_DEPTH_CONTROL[] = {
+	 { "STENCIL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "Z_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "Z_WRITE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DEPTH_BOUNDS_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "ZFUNC", 4, 6, &umr_bitfield_default },
+	 { "BACKFACE_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "STENCILFUNC", 8, 10, &umr_bitfield_default },
+	 { "STENCILFUNC_BF", 20, 22, &umr_bitfield_default },
+	 { "ENABLE_COLOR_WRITES_ON_DEPTH_FAIL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_COLOR_WRITES_ON_DEPTH_PASS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_EQAA[] = {
+	 { "MAX_ANCHOR_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLES", 4, 6, &umr_bitfield_default },
+	 { "MASK_EXPORT_NUM_SAMPLES", 8, 10, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "HIGH_QUALITY_INTERSECTIONS", 16, 16, &umr_bitfield_default },
+	 { "INCOHERENT_EQAA_READS", 17, 17, &umr_bitfield_default },
+	 { "INTERPOLATE_COMP_Z", 18, 18, &umr_bitfield_default },
+	 { "INTERPOLATE_SRC_Z", 19, 19, &umr_bitfield_default },
+	 { "STATIC_ANCHOR_ASSOCIATIONS", 20, 20, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_EQAA_DISABLE", 21, 21, &umr_bitfield_default },
+	 { "OVERRASTERIZATION_AMOUNT", 24, 26, &umr_bitfield_default },
+	 { "ENABLE_POSTZ_OVERRASTERIZATION", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR_CONTROL[] = {
+	 { "DISABLE_DUAL_QUAD", 0, 0, &umr_bitfield_default },
+	 { "DEGAMMA_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MODE", 4, 6, &umr_bitfield_default },
+	 { "ROP3", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SHADER_CONTROL[] = {
+	 { "Z_EXPORT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STENCIL_TEST_VAL_EXPORT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STENCIL_OP_VAL_EXPORT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "Z_ORDER", 4, 5, &umr_bitfield_default },
+	 { "KILL_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "COVERAGE_TO_MASK_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MASK_EXPORT_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "EXEC_ON_HIER_FAIL", 9, 9, &umr_bitfield_default },
+	 { "EXEC_ON_NOOP", 10, 10, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "DEPTH_BEFORE_SHADER", 12, 12, &umr_bitfield_default },
+	 { "CONSERVATIVE_Z_EXPORT", 13, 14, &umr_bitfield_default },
+	 { "DUAL_QUAD_DISABLE", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_CLIP_CNTL[] = {
+	 { "UCP_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "UCP_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "UCP_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "UCP_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "UCP_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "UCP_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "PS_UCP_Y_SCALE_NEG", 13, 13, &umr_bitfield_default },
+	 { "PS_UCP_MODE", 14, 15, &umr_bitfield_default },
+	 { "CLIP_DISABLE", 16, 16, &umr_bitfield_default },
+	 { "UCP_CULL_ONLY_ENA", 17, 17, &umr_bitfield_default },
+	 { "BOUNDARY_EDGE_FLAG_ENA", 18, 18, &umr_bitfield_default },
+	 { "DX_CLIP_SPACE_DEF", 19, 19, &umr_bitfield_default },
+	 { "DIS_CLIP_ERR_DETECT", 20, 20, &umr_bitfield_default },
+	 { "VTX_KILL_OR", 21, 21, &umr_bitfield_default },
+	 { "DX_RASTERIZATION_KILL", 22, 22, &umr_bitfield_default },
+	 { "DX_LINEAR_ATTR_CLIP_ENA", 24, 24, &umr_bitfield_default },
+	 { "VTE_VPORT_PROVOKE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "ZCLIP_NEAR_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "ZCLIP_FAR_DISABLE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_SC_MODE_CNTL[] = {
+	 { "CULL_FRONT", 0, 0, &umr_bitfield_default },
+	 { "CULL_BACK", 1, 1, &umr_bitfield_default },
+	 { "FACE", 2, 2, &umr_bitfield_default },
+	 { "POLY_MODE", 3, 4, &umr_bitfield_default },
+	 { "POLYMODE_FRONT_PTYPE", 5, 7, &umr_bitfield_default },
+	 { "POLYMODE_BACK_PTYPE", 8, 10, &umr_bitfield_default },
+	 { "POLY_OFFSET_FRONT_ENABLE", 11, 11, &umr_bitfield_default },
+	 { "POLY_OFFSET_BACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "POLY_OFFSET_PARA_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "VTX_WINDOW_OFFSET_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "PROVOKING_VTX_LAST", 19, 19, &umr_bitfield_default },
+	 { "PERSP_CORR_DIS", 20, 20, &umr_bitfield_default },
+	 { "MULTI_PRIM_IB_ENA", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VTE_CNTL[] = {
+	 { "VPORT_X_SCALE_ENA", 0, 0, &umr_bitfield_default },
+	 { "VPORT_X_OFFSET_ENA", 1, 1, &umr_bitfield_default },
+	 { "VPORT_Y_SCALE_ENA", 2, 2, &umr_bitfield_default },
+	 { "VPORT_Y_OFFSET_ENA", 3, 3, &umr_bitfield_default },
+	 { "VPORT_Z_SCALE_ENA", 4, 4, &umr_bitfield_default },
+	 { "VPORT_Z_OFFSET_ENA", 5, 5, &umr_bitfield_default },
+	 { "VTX_XY_FMT", 8, 8, &umr_bitfield_default },
+	 { "VTX_Z_FMT", 9, 9, &umr_bitfield_default },
+	 { "VTX_W0_FMT", 10, 10, &umr_bitfield_default },
+	 { "PERFCOUNTER_REF", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_VS_OUT_CNTL[] = {
+	 { "CLIP_DIST_ENA_0", 0, 0, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_1", 1, 1, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_2", 2, 2, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_3", 3, 3, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_4", 4, 4, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_5", 5, 5, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_6", 6, 6, &umr_bitfield_default },
+	 { "CLIP_DIST_ENA_7", 7, 7, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_0", 8, 8, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_1", 9, 9, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_2", 10, 10, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_3", 11, 11, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_4", 12, 12, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_5", 13, 13, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_6", 14, 14, &umr_bitfield_default },
+	 { "CULL_DIST_ENA_7", 15, 15, &umr_bitfield_default },
+	 { "USE_VTX_POINT_SIZE", 16, 16, &umr_bitfield_default },
+	 { "USE_VTX_EDGE_FLAG", 17, 17, &umr_bitfield_default },
+	 { "USE_VTX_RENDER_TARGET_INDX", 18, 18, &umr_bitfield_default },
+	 { "USE_VTX_VIEWPORT_INDX", 19, 19, &umr_bitfield_default },
+	 { "USE_VTX_KILL_FLAG", 20, 20, &umr_bitfield_default },
+	 { "VS_OUT_MISC_VEC_ENA", 21, 21, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST0_VEC_ENA", 22, 22, &umr_bitfield_default },
+	 { "VS_OUT_CCDIST1_VEC_ENA", 23, 23, &umr_bitfield_default },
+	 { "VS_OUT_MISC_SIDE_BUS_ENA", 24, 24, &umr_bitfield_default },
+	 { "USE_VTX_GS_CUT_FLAG", 25, 25, &umr_bitfield_default },
+	 { "USE_VTX_LINE_WIDTH", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_NANINF_CNTL[] = {
+	 { "VTE_XY_INF_DISCARD", 0, 0, &umr_bitfield_default },
+	 { "VTE_Z_INF_DISCARD", 1, 1, &umr_bitfield_default },
+	 { "VTE_W_INF_DISCARD", 2, 2, &umr_bitfield_default },
+	 { "VTE_0XNANINF_IS_0", 3, 3, &umr_bitfield_default },
+	 { "VTE_XY_NAN_RETAIN", 4, 4, &umr_bitfield_default },
+	 { "VTE_Z_NAN_RETAIN", 5, 5, &umr_bitfield_default },
+	 { "VTE_W_NAN_RETAIN", 6, 6, &umr_bitfield_default },
+	 { "VTE_W_RECIP_NAN_IS_0", 7, 7, &umr_bitfield_default },
+	 { "VS_XY_NAN_TO_INF", 8, 8, &umr_bitfield_default },
+	 { "VS_XY_INF_RETAIN", 9, 9, &umr_bitfield_default },
+	 { "VS_Z_NAN_TO_INF", 10, 10, &umr_bitfield_default },
+	 { "VS_Z_INF_RETAIN", 11, 11, &umr_bitfield_default },
+	 { "VS_W_NAN_TO_INF", 12, 12, &umr_bitfield_default },
+	 { "VS_W_INF_RETAIN", 13, 13, &umr_bitfield_default },
+	 { "VS_CLIP_DIST_INF_DISCARD", 14, 14, &umr_bitfield_default },
+	 { "VTE_NO_OUTPUT_NEG_0", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_CNTL[] = {
+	 { "LINE_STIPPLE_RESET", 0, 1, &umr_bitfield_default },
+	 { "EXPAND_FULL_LENGTH", 2, 2, &umr_bitfield_default },
+	 { "FRACTIONAL_ACCUM", 3, 3, &umr_bitfield_default },
+	 { "DIAMOND_ADJUST", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_SCALE[] = {
+	 { "LINE_STIPPLE_SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PRIM_FILTER_CNTL[] = {
+	 { "TRIANGLE_FILTER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "LINE_FILTER_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "POINT_FILTER_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RECTANGLE_FILTER_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "TRIANGLE_EXPAND_ENA", 4, 4, &umr_bitfield_default },
+	 { "LINE_EXPAND_ENA", 5, 5, &umr_bitfield_default },
+	 { "POINT_EXPAND_ENA", 6, 6, &umr_bitfield_default },
+	 { "RECTANGLE_EXPAND_ENA", 7, 7, &umr_bitfield_default },
+	 { "PRIM_EXPAND_CONSTANT", 8, 15, &umr_bitfield_default },
+	 { "XMAX_RIGHT_EXCLUSION", 30, 30, &umr_bitfield_default },
+	 { "YMAX_BOTTOM_EXCLUSION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POINT_SIZE[] = {
+	 { "HEIGHT", 0, 15, &umr_bitfield_default },
+	 { "WIDTH", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POINT_MINMAX[] = {
+	 { "MIN_SIZE", 0, 15, &umr_bitfield_default },
+	 { "MAX_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_CNTL[] = {
+	 { "WIDTH", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_STIPPLE[] = {
+	 { "LINE_PATTERN", 0, 15, &umr_bitfield_default },
+	 { "REPEAT_COUNT", 16, 23, &umr_bitfield_default },
+	 { "PATTERN_BIT_ORDER", 28, 28, &umr_bitfield_default },
+	 { "AUTO_RESET_CNTL", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_OUTPUT_PATH_CNTL[] = {
+	 { "PATH_SELECT", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_CNTL[] = {
+	 { "TESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_MAX_TESS_LEVEL[] = {
+	 { "MAX_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_MIN_TESS_LEVEL[] = {
+	 { "MIN_TESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HOS_REUSE_DEPTH[] = {
+	 { "REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_PRIM_TYPE[] = {
+	 { "PRIM_TYPE", 0, 4, &umr_bitfield_default },
+	 { "RETAIN_ORDER", 14, 14, &umr_bitfield_default },
+	 { "RETAIN_QUADS", 15, 15, &umr_bitfield_default },
+	 { "PRIM_ORDER", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_FIRST_DECR[] = {
+	 { "FIRST_DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_DECR[] = {
+	 { "DECR", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_0_CNTL[] = {
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_1_CNTL[] = {
+	 { "COMP_X_EN", 0, 0, &umr_bitfield_default },
+	 { "COMP_Y_EN", 1, 1, &umr_bitfield_default },
+	 { "COMP_Z_EN", 2, 2, &umr_bitfield_default },
+	 { "COMP_W_EN", 3, 3, &umr_bitfield_default },
+	 { "STRIDE", 8, 15, &umr_bitfield_default },
+	 { "SHIFT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_0_FMT_CNTL[] = {
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GROUP_VECT_1_FMT_CNTL[] = {
+	 { "X_CONV", 0, 3, &umr_bitfield_default },
+	 { "X_OFFSET", 4, 7, &umr_bitfield_default },
+	 { "Y_CONV", 8, 11, &umr_bitfield_default },
+	 { "Y_OFFSET", 12, 15, &umr_bitfield_default },
+	 { "Z_CONV", 16, 19, &umr_bitfield_default },
+	 { "Z_OFFSET", 20, 23, &umr_bitfield_default },
+	 { "W_CONV", 24, 27, &umr_bitfield_default },
+	 { "W_OFFSET", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_MODE[] = {
+	 { "MODE", 0, 2, &umr_bitfield_default },
+	 { "RESERVED_0", 3, 3, &umr_bitfield_default },
+	 { "CUT_MODE", 4, 5, &umr_bitfield_default },
+	 { "RESERVED_1", 6, 10, &umr_bitfield_default },
+	 { "GS_C_PACK_EN", 11, 11, &umr_bitfield_default },
+	 { "RESERVED_2", 12, 12, &umr_bitfield_default },
+	 { "ES_PASSTHRU", 13, 13, &umr_bitfield_default },
+	 { "RESERVED_3", 14, 14, &umr_bitfield_default },
+	 { "RESERVED_4", 15, 15, &umr_bitfield_default },
+	 { "RESERVED_5", 16, 16, &umr_bitfield_default },
+	 { "PARTIAL_THD_AT_EOI", 17, 17, &umr_bitfield_default },
+	 { "SUPPRESS_CUTS", 18, 18, &umr_bitfield_default },
+	 { "ES_WRITE_OPTIMIZE", 19, 19, &umr_bitfield_default },
+	 { "GS_WRITE_OPTIMIZE", 20, 20, &umr_bitfield_default },
+	 { "ONCHIP", 21, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_ONCHIP_CNTL[] = {
+	 { "ES_VERTS_PER_SUBGRP", 0, 10, &umr_bitfield_default },
+	 { "GS_PRIMS_PER_SUBGRP", 11, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_MODE_CNTL_0[] = {
+	 { "MSAA_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "VPORT_SCISSOR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "LINE_STIPPLE_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "SEND_UNLIT_STILES_TO_PKR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_MODE_CNTL_1[] = {
+	 { "WALK_SIZE", 0, 0, &umr_bitfield_default },
+	 { "WALK_ALIGNMENT", 1, 1, &umr_bitfield_default },
+	 { "WALK_ALIGN8_PRIM_FITS_ST", 2, 2, &umr_bitfield_default },
+	 { "WALK_FENCE_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "WALK_FENCE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "SUPERTILE_WALK_ORDER_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "TILE_WALK_ORDER_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "TILE_COVER_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "TILE_COVER_NO_SCISSOR", 10, 10, &umr_bitfield_default },
+	 { "ZMM_LINE_EXTENT", 11, 11, &umr_bitfield_default },
+	 { "ZMM_LINE_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "ZMM_RECT_EXTENT", 13, 13, &umr_bitfield_default },
+	 { "KILL_PIX_POST_HI_Z", 14, 14, &umr_bitfield_default },
+	 { "KILL_PIX_POST_DETAIL_MASK", 15, 15, &umr_bitfield_default },
+	 { "PS_ITER_SAMPLE", 16, 16, &umr_bitfield_default },
+	 { "MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "MULTI_GPU_SUPERTILE_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "GPU_ID_OVERRIDE", 20, 23, &umr_bitfield_default },
+	 { "MULTI_GPU_PRIM_DISCARD_ENABLE", 24, 24, &umr_bitfield_default },
+	 { "FORCE_EOV_CNTDWN_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "FORCE_EOV_REZ_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_PRIMITIVE_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "OUT_OF_ORDER_WATER_MARK", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_PER_ES[] = {
+	 { "GS_PER_ES", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ES_PER_GS[] = {
+	 { "ES_PER_GS", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_PER_VS[] = {
+	 { "GS_PER_VS", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_1[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_2[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_OFFSET_3[] = {
+	 { "OFFSET", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_OUT_PRIM_TYPE[] = {
+	 { "OUTPRIM_TYPE", 0, 5, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_1", 8, 13, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_2", 16, 21, &umr_bitfield_default },
+	 { "OUTPRIM_TYPE_3", 22, 27, &umr_bitfield_default },
+	 { "UNIQUE_TYPE_PER_STREAM", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_SIZE[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_MAX_SIZE[] = {
+	 { "MAX_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+	 { "SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "BUF_TYPE", 4, 5, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 6, 6, &umr_bitfield_default },
+	 { "NOT_EOP", 9, 9, &umr_bitfield_default },
+	 { "REQ_PATH", 10, 10, &umr_bitfield_default },
+	 { "MTYPE", 11, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_ENHANCE[] = {
+	 { "MISC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVEID_EN[] = {
+	 { "PRIMITIVEID_EN", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_RESET_ON_EOI", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DMA_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVEID_RESET[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_EVENT_INITIATOR[] = {
+	 { "EVENT_TYPE", 0, 5, &umr_bitfield_default },
+	 { "ADDRESS_HI", 18, 26, &umr_bitfield_default },
+	 { "EXTENDED_EVENT", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_MULTI_PRIM_IB_RESET_EN[] = {
+	 { "RESET_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_0[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INSTANCE_STEP_RATE_1[] = {
+	 { "STEP_RATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_MULTI_VGT_PARAM[] = {
+	 { "PRIMGROUP_SIZE", 0, 15, &umr_bitfield_default },
+	 { "PARTIAL_VS_WAVE_ON", 16, 16, &umr_bitfield_default },
+	 { "SWITCH_ON_EOP", 17, 17, &umr_bitfield_default },
+	 { "PARTIAL_ES_WAVE_ON", 18, 18, &umr_bitfield_default },
+	 { "SWITCH_ON_EOI", 19, 19, &umr_bitfield_default },
+	 { "WD_SWITCH_ON_EOP", 20, 20, &umr_bitfield_default },
+	 { "MAX_PRIMGRP_IN_WAVE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ESGS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_REUSE_OFF[] = {
+	 { "REUSE_OFF", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VTX_CNT_EN[] = {
+	 { "VTX_CNT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_HTILE_SURFACE[] = {
+	 { "LINEAR", 0, 0, &umr_bitfield_default },
+	 { "FULL_CACHE", 1, 1, &umr_bitfield_default },
+	 { "HTILE_USES_PRELOAD_WIN", 2, 2, &umr_bitfield_default },
+	 { "PRELOAD", 3, 3, &umr_bitfield_default },
+	 { "PREFETCH_WIDTH", 4, 9, &umr_bitfield_default },
+	 { "PREFETCH_HEIGHT", 10, 15, &umr_bitfield_default },
+	 { "DST_OUTSIDE_ZERO_TO_ONE", 16, 16, &umr_bitfield_default },
+	 { "TC_COMPATIBLE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE0[] = {
+	 { "COMPAREFUNC0", 0, 2, &umr_bitfield_default },
+	 { "COMPAREVALUE0", 4, 11, &umr_bitfield_default },
+	 { "COMPAREMASK0", 12, 19, &umr_bitfield_default },
+	 { "ENABLE0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_SRESULTS_COMPARE_STATE1[] = {
+	 { "COMPAREFUNC1", 0, 2, &umr_bitfield_default },
+	 { "COMPAREVALUE1", 4, 11, &umr_bitfield_default },
+	 { "COMPAREMASK1", 12, 19, &umr_bitfield_default },
+	 { "ENABLE1", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PRELOAD_CONTROL[] = {
+	 { "START_X", 0, 7, &umr_bitfield_default },
+	 { "START_Y", 8, 15, &umr_bitfield_default },
+	 { "MAX_X", 16, 23, &umr_bitfield_default },
+	 { "MAX_Y", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_0[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_0[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_1[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_1[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_2[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_2[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_VTX_STRIDE_3[] = {
+	 { "STRIDE", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_OFFSET_3[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[] = {
+	 { "VERTEX_STRIDE", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_MAX_VERT_OUT[] = {
+	 { "MAX_VERT_OUT", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TESS_DISTRIBUTION[] = {
+	 { "ACCUM_ISOLINE", 0, 7, &umr_bitfield_default },
+	 { "ACCUM_TRI", 8, 15, &umr_bitfield_default },
+	 { "ACCUM_QUAD", 16, 23, &umr_bitfield_default },
+	 { "DONUT_SPLIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_SHADER_STAGES_EN[] = {
+	 { "LS_EN", 0, 1, &umr_bitfield_default },
+	 { "HS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 4, &umr_bitfield_default },
+	 { "GS_EN", 5, 5, &umr_bitfield_default },
+	 { "VS_EN", 6, 7, &umr_bitfield_default },
+	 { "DYNAMIC_HS", 8, 8, &umr_bitfield_default },
+	 { "DISPATCH_DRAW_EN", 9, 9, &umr_bitfield_default },
+	 { "DIS_DEALLOC_ACCUM_0", 10, 10, &umr_bitfield_default },
+	 { "DIS_DEALLOC_ACCUM_1", 11, 11, &umr_bitfield_default },
+	 { "VS_WAVE_ID_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_LS_HS_CONFIG[] = {
+	 { "NUM_PATCHES", 0, 7, &umr_bitfield_default },
+	 { "HS_NUM_INPUT_CP", 8, 13, &umr_bitfield_default },
+	 { "HS_NUM_OUTPUT_CP", 14, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_1[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_2[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_VERT_ITEMSIZE_3[] = {
+	 { "ITEMSIZE", 0, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_PARAM[] = {
+	 { "TYPE", 0, 1, &umr_bitfield_default },
+	 { "PARTITIONING", 2, 4, &umr_bitfield_default },
+	 { "TOPOLOGY", 5, 7, &umr_bitfield_default },
+	 { "RESERVED_REDUC_AXIS", 8, 8, &umr_bitfield_default },
+	 { "DEPRECATED", 9, 9, &umr_bitfield_default },
+	 { "NUM_DS_WAVES_PER_SIMD", 10, 13, &umr_bitfield_default },
+	 { "DISABLE_DONUTS", 14, 14, &umr_bitfield_default },
+	 { "RDREQ_POLICY", 15, 15, &umr_bitfield_default },
+	 { "DISTRIBUTION_MODE", 17, 18, &umr_bitfield_default },
+	 { "MTYPE", 19, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ALPHA_TO_MASK[] = {
+	 { "ALPHA_TO_MASK_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET0", 8, 9, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET1", 10, 11, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET2", 12, 13, &umr_bitfield_default },
+	 { "ALPHA_TO_MASK_OFFSET3", 14, 15, &umr_bitfield_default },
+	 { "OFFSET_ROUND", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_DISPATCH_DRAW_INDEX[] = {
+	 { "MATCH_INDEX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[] = {
+	 { "POLY_OFFSET_NEG_NUM_DB_BITS", 0, 7, &umr_bitfield_default },
+	 { "POLY_OFFSET_DB_IS_FLOAT_FMT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_CLAMP[] = {
+	 { "CLAMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_FRONT_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_SCALE[] = {
+	 { "SCALE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_POLY_OFFSET_BACK_OFFSET[] = {
+	 { "OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GS_INSTANCE_CNT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CNT", 2, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_CONFIG[] = {
+	 { "STREAMOUT_0_EN", 0, 0, &umr_bitfield_default },
+	 { "STREAMOUT_1_EN", 1, 1, &umr_bitfield_default },
+	 { "STREAMOUT_2_EN", 2, 2, &umr_bitfield_default },
+	 { "STREAMOUT_3_EN", 3, 3, &umr_bitfield_default },
+	 { "RAST_STREAM", 4, 6, &umr_bitfield_default },
+	 { "RAST_STREAM_MASK", 8, 11, &umr_bitfield_default },
+	 { "USE_RAST_STREAM_MASK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_CONFIG[] = {
+	 { "STREAM_0_BUFFER_EN", 0, 3, &umr_bitfield_default },
+	 { "STREAM_1_BUFFER_EN", 4, 7, &umr_bitfield_default },
+	 { "STREAM_2_BUFFER_EN", 8, 11, &umr_bitfield_default },
+	 { "STREAM_3_BUFFER_EN", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_0[] = {
+	 { "DISTANCE_0", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_1", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_2", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_3", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_4", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_5", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_6", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_CENTROID_PRIORITY_1[] = {
+	 { "DISTANCE_8", 0, 3, &umr_bitfield_default },
+	 { "DISTANCE_9", 4, 7, &umr_bitfield_default },
+	 { "DISTANCE_10", 8, 11, &umr_bitfield_default },
+	 { "DISTANCE_11", 12, 15, &umr_bitfield_default },
+	 { "DISTANCE_12", 16, 19, &umr_bitfield_default },
+	 { "DISTANCE_13", 20, 23, &umr_bitfield_default },
+	 { "DISTANCE_14", 24, 27, &umr_bitfield_default },
+	 { "DISTANCE_15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_CNTL[] = {
+	 { "EXPAND_LINE_WIDTH", 9, 9, &umr_bitfield_default },
+	 { "LAST_PIXEL", 10, 10, &umr_bitfield_default },
+	 { "PERPENDICULAR_ENDCAP_ENA", 11, 11, &umr_bitfield_default },
+	 { "DX10_DIAMOND_TEST_ENA", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_CONFIG[] = {
+	 { "MSAA_NUM_SAMPLES", 0, 2, &umr_bitfield_default },
+	 { "AA_MASK_CENTROID_DTMN", 4, 4, &umr_bitfield_default },
+	 { "MAX_SAMPLE_DIST", 13, 16, &umr_bitfield_default },
+	 { "MSAA_EXPOSED_SAMPLES", 20, 22, &umr_bitfield_default },
+	 { "DETAIL_TO_EXPOSED_MODE", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_VTX_CNTL[] = {
+	 { "PIX_CENTER", 0, 0, &umr_bitfield_default },
+	 { "ROUND_MODE", 1, 2, &umr_bitfield_default },
+	 { "QUANT_MODE", 3, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_VERT_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_VERT_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_HORZ_CLIP_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_CL_GB_HORZ_DISC_ADJ[] = {
+	 { "DATA_REGISTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[] = {
+	 { "S0_X", 0, 3, &umr_bitfield_default },
+	 { "S0_Y", 4, 7, &umr_bitfield_default },
+	 { "S1_X", 8, 11, &umr_bitfield_default },
+	 { "S1_Y", 12, 15, &umr_bitfield_default },
+	 { "S2_X", 16, 19, &umr_bitfield_default },
+	 { "S2_Y", 20, 23, &umr_bitfield_default },
+	 { "S3_X", 24, 27, &umr_bitfield_default },
+	 { "S3_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[] = {
+	 { "S4_X", 0, 3, &umr_bitfield_default },
+	 { "S4_Y", 4, 7, &umr_bitfield_default },
+	 { "S5_X", 8, 11, &umr_bitfield_default },
+	 { "S5_Y", 12, 15, &umr_bitfield_default },
+	 { "S6_X", 16, 19, &umr_bitfield_default },
+	 { "S6_Y", 20, 23, &umr_bitfield_default },
+	 { "S7_X", 24, 27, &umr_bitfield_default },
+	 { "S7_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[] = {
+	 { "S8_X", 0, 3, &umr_bitfield_default },
+	 { "S8_Y", 4, 7, &umr_bitfield_default },
+	 { "S9_X", 8, 11, &umr_bitfield_default },
+	 { "S9_Y", 12, 15, &umr_bitfield_default },
+	 { "S10_X", 16, 19, &umr_bitfield_default },
+	 { "S10_Y", 20, 23, &umr_bitfield_default },
+	 { "S11_X", 24, 27, &umr_bitfield_default },
+	 { "S11_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[] = {
+	 { "S12_X", 0, 3, &umr_bitfield_default },
+	 { "S12_Y", 4, 7, &umr_bitfield_default },
+	 { "S13_X", 8, 11, &umr_bitfield_default },
+	 { "S13_Y", 12, 15, &umr_bitfield_default },
+	 { "S14_X", 16, 19, &umr_bitfield_default },
+	 { "S14_Y", 20, 23, &umr_bitfield_default },
+	 { "S15_X", 24, 27, &umr_bitfield_default },
+	 { "S15_Y", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_MASK_X0Y0_X1Y0[] = {
+	 { "AA_MASK_X0Y0", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_AA_MASK_X0Y1_X1Y1[] = {
+	 { "AA_MASK_X0Y1", 0, 15, &umr_bitfield_default },
+	 { "AA_MASK_X1Y1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SHADER_CONTROL[] = {
+	 { "REALIGN_DQUADS_AFTER_N_WAVES", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_VERTEX_REUSE_BLOCK_CNTL[] = {
+	 { "VTX_REUSE_DEPTH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_OUT_DEALLOC_CNTL[] = {
+	 { "DEALLOC_DIST", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR0_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR1_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR2_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR3_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR4_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR5_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR6_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_PITCH[] = {
+	 { "TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "FMASK_TILE_MAX", 20, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_VIEW[] = {
+	 { "SLICE_START", 0, 10, &umr_bitfield_default },
+	 { "SLICE_MAX", 13, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_INFO[] = {
+	 { "ENDIAN", 0, 1, &umr_bitfield_default },
+	 { "FORMAT", 2, 6, &umr_bitfield_default },
+	 { "LINEAR_GENERAL", 7, 7, &umr_bitfield_default },
+	 { "NUMBER_TYPE", 8, 10, &umr_bitfield_default },
+	 { "COMP_SWAP", 11, 12, &umr_bitfield_default },
+	 { "FAST_CLEAR", 13, 13, &umr_bitfield_default },
+	 { "COMPRESSION", 14, 14, &umr_bitfield_default },
+	 { "BLEND_CLAMP", 15, 15, &umr_bitfield_default },
+	 { "BLEND_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "SIMPLE_FLOAT", 17, 17, &umr_bitfield_default },
+	 { "ROUND_MODE", 18, 18, &umr_bitfield_default },
+	 { "CMASK_IS_LINEAR", 19, 19, &umr_bitfield_default },
+	 { "BLEND_OPT_DONT_RD_DST", 20, 22, &umr_bitfield_default },
+	 { "BLEND_OPT_DISCARD_PIXEL", 23, 25, &umr_bitfield_default },
+	 { "FMASK_COMPRESSION_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "FMASK_COMPRESS_1FRAG_ONLY", 27, 27, &umr_bitfield_default },
+	 { "DCC_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CMASK_ADDR_TYPE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_ATTRIB[] = {
+	 { "TILE_MODE_INDEX", 0, 4, &umr_bitfield_default },
+	 { "FMASK_TILE_MODE_INDEX", 5, 9, &umr_bitfield_default },
+	 { "FMASK_BANK_HEIGHT", 10, 11, &umr_bitfield_default },
+	 { "NUM_SAMPLES", 12, 14, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS", 15, 16, &umr_bitfield_default },
+	 { "FORCE_DST_ALPHA_1", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_DCC_CONTROL[] = {
+	 { "OVERWRITE_COMBINER_DISABLE", 0, 0, &umr_bitfield_default },
+	 { "KEY_CLEAR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MAX_UNCOMPRESSED_BLOCK_SIZE", 2, 3, &umr_bitfield_default },
+	 { "MIN_COMPRESSED_BLOCK_SIZE", 4, 4, &umr_bitfield_default },
+	 { "MAX_COMPRESSED_BLOCK_SIZE", 5, 6, &umr_bitfield_default },
+	 { "COLOR_TRANSFORM", 7, 8, &umr_bitfield_default },
+	 { "INDEPENDENT_64B_BLOCKS", 9, 9, &umr_bitfield_default },
+	 { "LOSSY_RGB_PRECISION", 10, 13, &umr_bitfield_default },
+	 { "LOSSY_ALPHA_PRECISION", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_FMASK[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_FMASK_SLICE[] = {
+	 { "TILE_MAX", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD0[] = {
+	 { "CLEAR_WORD0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_CLEAR_WORD1[] = {
+	 { "CLEAR_WORD1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_COLOR7_DCC_BASE[] = {
+	 { "BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG11[] = {
+	 { "clipsm3_clip_to_clipga_event", 0, 0, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_event", 1, 1, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_event", 2, 2, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_event", 3, 3, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_clip_primitive", 4, 4, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_clip_primitive", 5, 5, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_clip_primitive", 6, 6, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_clip_primitive", 7, 7, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_clip_to_outsm_cnt", 8, 11, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_clip_to_outsm_cnt", 12, 15, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_clip_to_outsm_cnt", 16, 19, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_clip_to_outsm_cnt", 20, 23, &umr_bitfield_default },
+	 { "clipsm3_clip_to_clipga_prim_valid", 24, 24, &umr_bitfield_default },
+	 { "clipsm2_clip_to_clipga_prim_valid", 25, 25, &umr_bitfield_default },
+	 { "clipsm1_clip_to_clipga_prim_valid", 26, 26, &umr_bitfield_default },
+	 { "clipsm0_clip_to_clipga_prim_valid", 27, 27, &umr_bitfield_default },
+	 { "clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt", 28, 28, &umr_bitfield_default },
+	 { "clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt", 29, 29, &umr_bitfield_default },
+	 { "clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG11[] = {
+	 { "tm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "tm_noif_busy_q", 1, 1, &umr_bitfield_default },
+	 { "tm_out_busy_q", 2, 2, &umr_bitfield_default },
+	 { "es_rb_dealloc_fifo_busy", 3, 3, &umr_bitfield_default },
+	 { "vs_dealloc_tbl_busy", 4, 4, &umr_bitfield_default },
+	 { "SPARE1", 5, 5, &umr_bitfield_default },
+	 { "spi_gsthread_fifo_busy", 6, 6, &umr_bitfield_default },
+	 { "spi_esthread_fifo_busy", 7, 7, &umr_bitfield_default },
+	 { "hold_eswave", 8, 8, &umr_bitfield_default },
+	 { "es_rb_roll_over_r3", 9, 9, &umr_bitfield_default },
+	 { "counters_busy_r0", 10, 10, &umr_bitfield_default },
+	 { "counters_avail_r0", 11, 11, &umr_bitfield_default },
+	 { "counters_available_r0", 12, 12, &umr_bitfield_default },
+	 { "vs_event_fifo_rtr", 13, 13, &umr_bitfield_default },
+	 { "VGT_SPI_gsthread_rtr_q", 14, 14, &umr_bitfield_default },
+	 { "VGT_SPI_esthread_rtr_q", 15, 15, &umr_bitfield_default },
+	 { "gs_issue_rtr", 16, 16, &umr_bitfield_default },
+	 { "tm_pt_event_rtr", 17, 17, &umr_bitfield_default },
+	 { "SPARE0", 18, 18, &umr_bitfield_default },
+	 { "gs_r0_rtr", 19, 19, &umr_bitfield_default },
+	 { "es_r0_rtr", 20, 20, &umr_bitfield_default },
+	 { "gog_tm_vs_event_rtr", 21, 21, &umr_bitfield_default },
+	 { "tm_rcm_gs_event_rtr", 22, 22, &umr_bitfield_default },
+	 { "tm_rcm_gs_tbl_rtr", 23, 23, &umr_bitfield_default },
+	 { "tm_rcm_es_tbl_rtr", 24, 24, &umr_bitfield_default },
+	 { "vs_event_fifo_empty", 25, 25, &umr_bitfield_default },
+	 { "vs_event_fifo_full", 26, 26, &umr_bitfield_default },
+	 { "es_rb_dealloc_fifo_full", 27, 27, &umr_bitfield_default },
+	 { "vs_dealloc_tbl_full", 28, 28, &umr_bitfield_default },
+	 { "send_event_q", 29, 29, &umr_bitfield_default },
+	 { "es_tbl_empty", 30, 30, &umr_bitfield_default },
+	 { "no_active_states_r0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG12[] = {
+	 { "ALWAYS_ZERO", 0, 7, &umr_bitfield_default },
+	 { "clip_priority_available_vte_out_clip", 8, 12, &umr_bitfield_default },
+	 { "clip_priority_available_clip_verts", 13, 17, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_out", 18, 19, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_vert", 20, 21, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_load", 22, 23, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_clip_primitive", 24, 24, &umr_bitfield_default },
+	 { "clipsm3_clprim_to_clip_prim_valid", 25, 25, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_clip_primitive", 26, 26, &umr_bitfield_default },
+	 { "clipsm2_clprim_to_clip_prim_valid", 27, 27, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_clip_primitive", 28, 28, &umr_bitfield_default },
+	 { "clipsm1_clprim_to_clip_prim_valid", 29, 29, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_clip_primitive", 30, 30, &umr_bitfield_default },
+	 { "clipsm0_clprim_to_clip_prim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG12[] = {
+	 { "gs_state0_r0_q", 0, 2, &umr_bitfield_default },
+	 { "gs_state1_r0_q", 3, 5, &umr_bitfield_default },
+	 { "gs_state2_r0_q", 6, 8, &umr_bitfield_default },
+	 { "gs_state3_r0_q", 9, 11, &umr_bitfield_default },
+	 { "gs_state4_r0_q", 12, 14, &umr_bitfield_default },
+	 { "gs_state5_r0_q", 15, 17, &umr_bitfield_default },
+	 { "gs_state6_r0_q", 18, 20, &umr_bitfield_default },
+	 { "gs_state7_r0_q", 21, 23, &umr_bitfield_default },
+	 { "gs_state8_r0_q", 24, 26, &umr_bitfield_default },
+	 { "gs_state9_r0_q", 27, 29, &umr_bitfield_default },
+	 { "hold_eswave_eop", 30, 30, &umr_bitfield_default },
+	 { "SPARE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_ADDR_LO[] = {
+	 { "ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_LO[] = {
+	 { "DATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_HI[] = {
+	 { "DATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_LAST_FENCE_LO[] = {
+	 { "LAST_FENCE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_LAST_FENCE_HI[] = {
+	 { "LAST_FENCE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_ADDR_LO[] = {
+	 { "STREAM_OUT_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_ADDR_HI[] = {
+	 { "STREAM_OUT_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT0_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT1_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT2_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT2_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[] = {
+	 { "NUM_PRIM_WRITTEN_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_LO[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_NUM_PRIM_NEEDED_COUNT3_HI[] = {
+	 { "NUM_PRIM_NEEDED_CNT3_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_ADDR_LO[] = {
+	 { "PIPE_STATS_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_ADDR_HI[] = {
+	 { "PIPE_STATS_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_LO[] = {
+	 { "IAVERT_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAVERT_COUNT_HI[] = {
+	 { "IAVERT_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_LO[] = {
+	 { "IAPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_IAPRIM_COUNT_HI[] = {
+	 { "IAPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_LO[] = {
+	 { "GSPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSPRIM_COUNT_HI[] = {
+	 { "GSPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_LO[] = {
+	 { "VSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_VSINVOC_COUNT_HI[] = {
+	 { "VSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_LO[] = {
+	 { "GSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_GSINVOC_COUNT_HI[] = {
+	 { "GSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_LO[] = {
+	 { "HSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_HSINVOC_COUNT_HI[] = {
+	 { "HSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_LO[] = {
+	 { "DSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_DSINVOC_COUNT_HI[] = {
+	 { "DSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CINVOC_COUNT_LO[] = {
+	 { "CINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CINVOC_COUNT_HI[] = {
+	 { "CINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CPRIM_COUNT_LO[] = {
+	 { "CPRIM_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PA_CPRIM_COUNT_HI[] = {
+	 { "CPRIM_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_LO[] = {
+	 { "PSINVOC_COUNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT0_HI[] = {
+	 { "PSINVOC_COUNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_LO[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SC_PSINVOC_COUNT1_HI[] = {
+	 { "OBSOLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_LO[] = {
+	 { "CSINVOC_COUNT_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_VGT_CSINVOC_COUNT_HI[] = {
+	 { "CSINVOC_COUNT_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PIPE_STATS_CONTROL[] = {
+	 { "CACHE_CONTROL", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STREAM_OUT_CONTROL[] = {
+	 { "CACHE_CONTROL", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_STRMOUT_CNTL[] = {
+	 { "OFFSET_UPDATE_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG0[] = {
+	 { "SCRATCH_REG0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG1[] = {
+	 { "SCRATCH_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG2[] = {
+	 { "SCRATCH_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG3[] = {
+	 { "SCRATCH_REG3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG4[] = {
+	 { "SCRATCH_REG4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG5[] = {
+	 { "SCRATCH_REG5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG6[] = {
+	 { "SCRATCH_REG6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_REG7[] = {
+	 { "SCRATCH_REG7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_UMSK[] = {
+	 { "OBSOLETE_UMSK", 0, 7, &umr_bitfield_default },
+	 { "OBSOLETE_SWAP", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSCRATCH_ADDR[] = {
+	 { "OBSOLETE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_ADDR_LO[] = {
+	 { "MEM_ADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_ADDR_HI[] = {
+	 { "MEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "CS_PS_SEL", 16, 16, &umr_bitfield_default },
+	 { "CACHE_POLICY", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+	 { "COMMAND", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_LAST_CS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_APPEND_LAST_PS_FENCE[] = {
+	 { "LAST_FENCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATOMIC_PREOP_LO[] = {
+	 { "ATOMIC_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ATOMIC_PREOP_HI[] = {
+	 { "ATOMIC_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_LO[] = {
+	 { "GDS_ATOMIC0_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC0_PREOP_HI[] = {
+	 { "GDS_ATOMIC0_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_LO[] = {
+	 { "GDS_ATOMIC1_PREOP_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_ATOMIC1_PREOP_HI[] = {
+	 { "GDS_ATOMIC1_PREOP_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WADDR_LO[] = {
+	 { "ME_MC_WADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ME_MC_WADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WADDR_HI[] = {
+	 { "ME_MC_WADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "MTYPE", 20, 21, &umr_bitfield_default },
+	 { "CACHE_POLICY", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WDATA_LO[] = {
+	 { "ME_MC_WDATA_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_WDATA_HI[] = {
+	 { "ME_MC_WDATA_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_RADDR_LO[] = {
+	 { "ME_MC_RADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "ME_MC_RADDR_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_MC_RADDR_HI[] = {
+	 { "ME_MC_RADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "MTYPE", 20, 21, &umr_bitfield_default },
+	 { "CACHE_POLICY", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SEM_WAIT_TIMER[] = {
+	 { "SEM_WAIT_TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SIG_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SIG_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_REG_MEM_TIMEOUT[] = {
+	 { "WAIT_REG_MEM_TIMEOUT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_SEM_ADDR_LO[] = {
+	 { "SEM_ADDR_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SEM_ADDR_LO", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_WAIT_SEM_ADDR_HI[] = {
+	 { "SEM_ADDR_HI", 0, 15, &umr_bitfield_default },
+	 { "SEM_USE_MAILBOX", 16, 16, &umr_bitfield_default },
+	 { "SEM_SIGNAL_TYPE", 20, 20, &umr_bitfield_default },
+	 { "SEM_CLIENT_CODE", 24, 25, &umr_bitfield_default },
+	 { "SEM_SELECT", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_CONTROL[] = {
+	 { "SRC_MTYPE", 10, 11, &umr_bitfield_default },
+	 { "SRC_ATC", 12, 12, &umr_bitfield_default },
+	 { "SRC_CACHE_POLICY", 13, 13, &umr_bitfield_default },
+	 { "DST_SELECT", 20, 21, &umr_bitfield_default },
+	 { "DST_MTYPE", 22, 23, &umr_bitfield_default },
+	 { "DST_ATC", 24, 24, &umr_bitfield_default },
+	 { "DST_CACHE_POLICY", 25, 25, &umr_bitfield_default },
+	 { "SRC_SELECT", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_CONTROL[] = {
+	 { "SRC_MTYPE", 10, 11, &umr_bitfield_default },
+	 { "SRC_ATC", 12, 12, &umr_bitfield_default },
+	 { "SRC_CACHE_POLICY", 13, 13, &umr_bitfield_default },
+	 { "DST_SELECT", 20, 21, &umr_bitfield_default },
+	 { "DST_MTYPE", 22, 23, &umr_bitfield_default },
+	 { "DST_ATC", 24, 24, &umr_bitfield_default },
+	 { "DST_CACHE_POLICY", 25, 25, &umr_bitfield_default },
+	 { "SRC_SELECT", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_BASE_HI[] = {
+	 { "COHER_BASE_HI_256B", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_START_DELAY[] = {
+	 { "START_DELAY_COUNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_CNTL[] = {
+	 { "DEST_BASE_0_ENA", 0, 0, &umr_bitfield_default },
+	 { "DEST_BASE_1_ENA", 1, 1, &umr_bitfield_default },
+	 { "TC_SD_ACTION_ENA", 2, 2, &umr_bitfield_default },
+	 { "TC_NC_ACTION_ENA", 3, 3, &umr_bitfield_default },
+	 { "CB0_DEST_BASE_ENA", 6, 6, &umr_bitfield_default },
+	 { "CB1_DEST_BASE_ENA", 7, 7, &umr_bitfield_default },
+	 { "CB2_DEST_BASE_ENA", 8, 8, &umr_bitfield_default },
+	 { "CB3_DEST_BASE_ENA", 9, 9, &umr_bitfield_default },
+	 { "CB4_DEST_BASE_ENA", 10, 10, &umr_bitfield_default },
+	 { "CB5_DEST_BASE_ENA", 11, 11, &umr_bitfield_default },
+	 { "CB6_DEST_BASE_ENA", 12, 12, &umr_bitfield_default },
+	 { "CB7_DEST_BASE_ENA", 13, 13, &umr_bitfield_default },
+	 { "DB_DEST_BASE_ENA", 14, 14, &umr_bitfield_default },
+	 { "TCL1_VOL_ACTION_ENA", 15, 15, &umr_bitfield_default },
+	 { "TC_WB_ACTION_ENA", 18, 18, &umr_bitfield_default },
+	 { "DEST_BASE_2_ENA", 19, 19, &umr_bitfield_default },
+	 { "DEST_BASE_3_ENA", 21, 21, &umr_bitfield_default },
+	 { "TCL1_ACTION_ENA", 22, 22, &umr_bitfield_default },
+	 { "TC_ACTION_ENA", 23, 23, &umr_bitfield_default },
+	 { "CB_ACTION_ENA", 25, 25, &umr_bitfield_default },
+	 { "DB_ACTION_ENA", 26, 26, &umr_bitfield_default },
+	 { "SH_KCACHE_ACTION_ENA", 27, 27, &umr_bitfield_default },
+	 { "SH_KCACHE_VOL_ACTION_ENA", 28, 28, &umr_bitfield_default },
+	 { "SH_ICACHE_ACTION_ENA", 29, 29, &umr_bitfield_default },
+	 { "SH_KCACHE_WB_ACTION_ENA", 30, 30, &umr_bitfield_default },
+	 { "SH_SD_ACTION_ENA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_SIZE[] = {
+	 { "COHER_SIZE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_BASE[] = {
+	 { "COHER_BASE_256B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_STATUS[] = {
+	 { "MATCHING_GFX_CNTX", 0, 7, &umr_bitfield_default },
+	 { "MEID", 24, 25, &umr_bitfield_default },
+	 { "PHASE1_STATUS", 30, 30, &umr_bitfield_default },
+	 { "STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_ME_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR[] = {
+	 { "SRC_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_SRC_ADDR_HI[] = {
+	 { "SRC_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR[] = {
+	 { "DST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_DST_ADDR_HI[] = {
+	 { "DST_ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_PFP_COMMAND[] = {
+	 { "BYTE_COUNT", 0, 20, &umr_bitfield_default },
+	 { "DIS_WC", 21, 21, &umr_bitfield_default },
+	 { "SRC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DST_SWAP", 24, 25, &umr_bitfield_default },
+	 { "SAS", 26, 26, &umr_bitfield_default },
+	 { "DAS", 27, 27, &umr_bitfield_default },
+	 { "SAIC", 28, 28, &umr_bitfield_default },
+	 { "DAIC", 29, 29, &umr_bitfield_default },
+	 { "RAW_WAIT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_CNTL[] = {
+	 { "MIN_AVAILSZ", 4, 5, &umr_bitfield_default },
+	 { "BUFFER_DEPTH", 16, 19, &umr_bitfield_default },
+	 { "PIO_FIFO_EMPTY", 28, 28, &umr_bitfield_default },
+	 { "PIO_FIFO_FULL", 29, 29, &umr_bitfield_default },
+	 { "PIO_COUNT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DMA_READ_TAGS[] = {
+	 { "DMA_READ_TAG", 0, 25, &umr_bitfield_default },
+	 { "DMA_READ_TAG_VALID", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_COHER_SIZE_HI[] = {
+	 { "COHER_SIZE_HI_256B", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_IB_CONTROL[] = {
+	 { "IB_EN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_LOAD_CONTROL[] = {
+	 { "CONFIG_REG_EN", 0, 0, &umr_bitfield_default },
+	 { "CNTX_REG_EN", 1, 1, &umr_bitfield_default },
+	 { "SH_GFX_REG_EN", 16, 16, &umr_bitfield_default },
+	 { "SH_CS_REG_EN", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SCRATCH_INDEX[] = {
+	 { "SCRATCH_INDEX", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SCRATCH_DATA[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_RB_OFFSET[] = {
+	 { "RB_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_OFFSET[] = {
+	 { "IB1_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_OFFSET[] = {
+	 { "IB2_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_PREAMBLE_BEGIN[] = {
+	 { "IB1_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_PREAMBLE_END[] = {
+	 { "IB1_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_PREAMBLE_BEGIN[] = {
+	 { "IB2_PREAMBLE_BEGIN", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_PREAMBLE_END[] = {
+	 { "IB2_PREAMBLE_END", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_OFFSET[] = {
+	 { "IB1_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_OFFSET[] = {
+	 { "IB2_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_COUNTER[] = {
+	 { "CONST_ENGINE_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_RB_OFFSET[] = {
+	 { "RB_OFFSET", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BASE_LO[] = {
+	 { "INIT_BASE_LO", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BASE_HI[] = {
+	 { "INIT_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_INIT_BUFSZ[] = {
+	 { "INIT_BUFSZ", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BASE_LO[] = {
+	 { "IB1_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BASE_HI[] = {
+	 { "IB1_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB1_BUFSZ[] = {
+	 { "IB1_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BASE_LO[] = {
+	 { "IB2_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BASE_HI[] = {
+	 { "IB2_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_IB2_BUFSZ[] = {
+	 { "IB2_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BASE_LO[] = {
+	 { "ST_BASE_LO", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BASE_HI[] = {
+	 { "ST_BASE_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ST_BUFSZ[] = {
+	 { "ST_BUFSZ", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_EVENT_CNTL[] = {
+	 { "WBINV_TC_OP", 0, 6, &umr_bitfield_default },
+	 { "WBINV_ACTION_ENA", 12, 17, &umr_bitfield_default },
+	 { "CACHE_CONTROL", 25, 25, &umr_bitfield_default },
+	 { "MTYPE", 27, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_DATA_CNTL[] = {
+	 { "CNTX_ID", 0, 15, &umr_bitfield_default },
+	 { "DST_SEL", 16, 17, &umr_bitfield_default },
+	 { "INT_SEL", 24, 26, &umr_bitfield_default },
+	 { "DATA_SEL", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_EOP_DONE_CNTX_ID[] = {
+	 { "CNTX_ID", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_COMPLETION_STATUS[] = {
+	 { "STATUS", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_COMPLETION_STATUS[] = {
+	 { "STATUS", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PRED_NOT_VISIBLE[] = {
+	 { "NOT_VISIBLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_METADATA_BASE_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_METADATA_BASE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_METADATA_BASE_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_METADATA_BASE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_INDX_INDR_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_INDX_INDR_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DISPATCH_INDR_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DISPATCH_INDR_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INDEX_BASE_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INDEX_BASE_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_BKUP_ADDR[] = {
+	 { "ADDR_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_GDS_BKUP_ADDR_HI[] = {
+	 { "ADDR_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_SAMPLE_STATUS[] = {
+	 { "Z_PASS_ACITVE", 0, 0, &umr_bitfield_default },
+	 { "STREAMOUT_ACTIVE", 1, 1, &umr_bitfield_default },
+	 { "PIPELINE_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "STIPPLE_ACTIVE", 3, 3, &umr_bitfield_default },
+	 { "VGT_BUFFERS_ACTIVE", 4, 4, &umr_bitfield_default },
+	 { "SCREEN_EXT_ACTIVE", 5, 5, &umr_bitfield_default },
+	 { "DRAW_INDIRECT_ACTIVE", 6, 6, &umr_bitfield_default },
+	 { "DISP_INDIRECT_ACTIVE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_GFX_INDEX[] = {
+	 { "INSTANCE_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 15, &umr_bitfield_default },
+	 { "SE_INDEX", 16, 23, &umr_bitfield_default },
+	 { "SH_BROADCAST_WRITES", 29, 29, &umr_bitfield_default },
+	 { "INSTANCE_BROADCAST_WRITES", 30, 30, &umr_bitfield_default },
+	 { "SE_BROADCAST_WRITES", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_ESGS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_GSVS_RING_SIZE[] = {
+	 { "MEM_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PRIMITIVE_TYPE[] = {
+	 { "PRIM_TYPE", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_INDEX_TYPE[] = {
+	 { "INDEX_TYPE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_NUM_INDICES[] = {
+	 { "NUM_INDICES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_NUM_INSTANCES[] = {
+	 { "NUM_INSTANCES", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_RING_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_HS_OFFCHIP_PARAM[] = {
+	 { "OFFCHIP_BUFFERING", 0, 8, &umr_bitfield_default },
+	 { "OFFCHIP_GRANULARITY", 9, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_TF_MEMORY_BASE[] = {
+	 { "BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_LINE_STIPPLE_VALUE[] = {
+	 { "LINE_STIPPLE_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_LINE_STIPPLE_STATE[] = {
+	 { "CURRENT_PTR", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_COUNT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MIN_0[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MAX_0[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MIN_1[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_SCREEN_EXTENT_MAX_1[] = {
+	 { "X", 0, 15, &umr_bitfield_default },
+	 { "Y", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_P3D_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_HP3D_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_HV_EN[] = {
+	 { "ENABLE_HV_PRE_SHADER", 0, 0, &umr_bitfield_default },
+	 { "FORCE_PRE_SHADER_ALL_PIXELS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_H[] = {
+	 { "X_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_V[] = {
+	 { "Y_COORD", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_OCCURRENCE[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_TRAP_SCREEN_COUNT[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_SIZE[] = {
+	 { "SIZE", 0, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_MASK[] = {
+	 { "CU_SEL", 0, 4, &umr_bitfield_default },
+	 { "SH_SEL", 5, 5, &umr_bitfield_default },
+	 { "REG_STALL_EN", 7, 7, &umr_bitfield_default },
+	 { "SIMD_EN", 8, 11, &umr_bitfield_default },
+	 { "VM_ID_MASK", 12, 13, &umr_bitfield_default },
+	 { "SPI_STALL_EN", 14, 14, &umr_bitfield_default },
+	 { "SQ_STALL_EN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK[] = {
+	 { "TOKEN_MASK", 0, 15, &umr_bitfield_default },
+	 { "REG_MASK", 16, 23, &umr_bitfield_default },
+	 { "REG_DROP_ON_STALL", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_PERF_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_CTRL[] = {
+	 { "RESET_BUFFER", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_MODE[] = {
+	 { "MASK_PS", 0, 2, &umr_bitfield_default },
+	 { "MASK_VS", 3, 5, &umr_bitfield_default },
+	 { "MASK_GS", 6, 8, &umr_bitfield_default },
+	 { "MASK_ES", 9, 11, &umr_bitfield_default },
+	 { "MASK_HS", 12, 14, &umr_bitfield_default },
+	 { "MASK_LS", 15, 17, &umr_bitfield_default },
+	 { "MASK_CS", 18, 20, &umr_bitfield_default },
+	 { "MODE", 21, 22, &umr_bitfield_default },
+	 { "CAPTURE_MODE", 23, 24, &umr_bitfield_default },
+	 { "AUTOFLUSH_EN", 25, 25, &umr_bitfield_default },
+	 { "PRIV", 26, 26, &umr_bitfield_default },
+	 { "ISSUE_MASK", 27, 28, &umr_bitfield_default },
+	 { "TEST_MODE", 29, 29, &umr_bitfield_default },
+	 { "INTERRUPT_EN", 30, 30, &umr_bitfield_default },
+	 { "WRAP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_BASE2[] = {
+	 { "ADDR_HI", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_TOKEN_MASK2[] = {
+	 { "INST_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_WPTR[] = {
+	 { "WPTR", 0, 29, &umr_bitfield_default },
+	 { "READ_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_STATUS[] = {
+	 { "FINISH_PENDING", 0, 9, &umr_bitfield_default },
+	 { "FINISH_DONE", 16, 25, &umr_bitfield_default },
+	 { "NEW_BUF", 29, 29, &umr_bitfield_default },
+	 { "BUSY", 30, 30, &umr_bitfield_default },
+	 { "FULL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_HIWATER[] = {
+	 { "HIWATER", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_THREAD_TRACE_USERDATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_CACHES[] = {
+	 { "TARGET_INST", 0, 0, &umr_bitfield_default },
+	 { "TARGET_DATA", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE", 2, 2, &umr_bitfield_default },
+	 { "WRITEBACK", 3, 3, &umr_bitfield_default },
+	 { "VOL", 4, 4, &umr_bitfield_default },
+	 { "COMPLETE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQC_WRITEBACK[] = {
+	 { "DWB", 0, 0, &umr_bitfield_default },
+	 { "DIRTY", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CS_BC_BASE_ADDR[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CS_BC_BASE_ADDR_HI[] = {
+	 { "ADDRESS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT0_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT0_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT1_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT1_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT2_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT2_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT3_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_OCCLUSION_COUNT3_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ZPASS_COUNT_LOW[] = {
+	 { "COUNT_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_ZPASS_COUNT_HI[] = {
+	 { "COUNT_HI", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_ADDR[] = {
+	 { "READ_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_DATA[] = {
+	 { "READ_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_ADDR[] = {
+	 { "BURST_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_COUNT[] = {
+	 { "BURST_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_RD_BURST_DATA[] = {
+	 { "BURST_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_BURST_ADDR[] = {
+	 { "WRITE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WR_BURST_DATA[] = {
+	 { "WRITE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_WRITE_COMPLETE[] = {
+	 { "WRITE_COMPLETE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_CNTL[] = {
+	 { "AINC", 0, 5, &umr_bitfield_default },
+	 { "UNUSED1", 6, 7, &umr_bitfield_default },
+	 { "DMODE", 8, 9, &umr_bitfield_default },
+	 { "UNUSED2", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_COMPLETE[] = {
+	 { "COMPLETE", 0, 0, &umr_bitfield_default },
+	 { "UNUSED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_BASE[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SIZE[] = {
+	 { "SIZE", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OFFSET0[] = {
+	 { "OFFSET0", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OFFSET1[] = {
+	 { "OFFSET1", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_DST[] = {
+	 { "DST", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_OP[] = {
+	 { "OP", 0, 7, &umr_bitfield_default },
+	 { "UNUSED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_SRC1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ0_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_ATOM_READ1_U[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_CNTL[] = {
+	 { "INDEX", 0, 5, &umr_bitfield_default },
+	 { "UNUSED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE[] = {
+	 { "FLAG", 0, 0, &umr_bitfield_default },
+	 { "COUNTER", 1, 12, &umr_bitfield_default },
+	 { "TYPE", 13, 13, &umr_bitfield_default },
+	 { "DED", 14, 14, &umr_bitfield_default },
+	 { "RELEASE_ALL", 15, 15, &umr_bitfield_default },
+	 { "HEAD_QUEUE", 16, 27, &umr_bitfield_default },
+	 { "HEAD_VALID", 28, 28, &umr_bitfield_default },
+	 { "HEAD_FLAG", 29, 29, &umr_bitfield_default },
+	 { "UNUSED1", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_GWS_RESOURCE_CNT[] = {
+	 { "RESOURCE_CNT", 0, 15, &umr_bitfield_default },
+	 { "UNUSED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_CNTL[] = {
+	 { "INDEX", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_COUNTER[] = {
+	 { "SPACE_AVAILABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_ADDRESS[] = {
+	 { "DS_ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "CRAWLER", 16, 19, &umr_bitfield_default },
+	 { "CRAWLER_TYPE", 20, 21, &umr_bitfield_default },
+	 { "UNUSED", 22, 29, &umr_bitfield_default },
+	 { "NO_ALLOC", 30, 30, &umr_bitfield_default },
+	 { "ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_INCDEC[] = {
+	 { "VALUE", 0, 30, &umr_bitfield_default },
+	 { "INCDEC", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_OA_RING_SIZE[] = {
+	 { "RING_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG13[] = {
+	 { "clprim_in_back_state_var_indx", 0, 2, &umr_bitfield_default },
+	 { "point_clip_candidate", 3, 3, &umr_bitfield_default },
+	 { "prim_nan_kill", 4, 4, &umr_bitfield_default },
+	 { "clprim_clip_primitive", 5, 5, &umr_bitfield_default },
+	 { "clprim_cull_primitive", 6, 6, &umr_bitfield_default },
+	 { "prim_back_valid", 7, 7, &umr_bitfield_default },
+	 { "vertval_bits_vertex_cc_next_valid", 8, 11, &umr_bitfield_default },
+	 { "clipcc_vertex_store_indx", 12, 13, &umr_bitfield_default },
+	 { "vte_out_orig_fifo_fifo_empty", 14, 14, &umr_bitfield_default },
+	 { "clipcode_fifo_fifo_empty", 15, 15, &umr_bitfield_default },
+	 { "ccgen_to_clipcc_fifo_empty", 16, 16, &umr_bitfield_default },
+	 { "clip_priority_seq_indx_out_cnt", 17, 20, &umr_bitfield_default },
+	 { "outsm_clr_rd_orig_vertices", 21, 22, &umr_bitfield_default },
+	 { "outsm_clr_rd_clipsm_wait", 23, 23, &umr_bitfield_default },
+	 { "outsm_clr_fifo_contents", 24, 28, &umr_bitfield_default },
+	 { "outsm_clr_fifo_full", 29, 29, &umr_bitfield_default },
+	 { "outsm_clr_fifo_advanceread", 30, 30, &umr_bitfield_default },
+	 { "outsm_clr_fifo_write", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG13[] = {
+	 { "gs_state10_r0_q", 0, 2, &umr_bitfield_default },
+	 { "gs_state11_r0_q", 3, 5, &umr_bitfield_default },
+	 { "gs_state12_r0_q", 6, 8, &umr_bitfield_default },
+	 { "gs_state13_r0_q", 9, 11, &umr_bitfield_default },
+	 { "gs_state14_r0_q", 12, 14, &umr_bitfield_default },
+	 { "gs_state15_r0_q", 15, 17, &umr_bitfield_default },
+	 { "gs_tbl_wrptr_r0_q_3_0", 18, 21, &umr_bitfield_default },
+	 { "gsfetch_done_fifo_cnt_q_not_0", 22, 22, &umr_bitfield_default },
+	 { "gsfetch_done_cnt_q_not_0", 23, 23, &umr_bitfield_default },
+	 { "es_tbl_full", 24, 24, &umr_bitfield_default },
+	 { "SPARE1", 25, 25, &umr_bitfield_default },
+	 { "SPARE0", 26, 26, &umr_bitfield_default },
+	 { "active_cm_sm_r0_q", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_LO[] = {
+	 { "PERFCOUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_HI[] = {
+	 { "PERFCOUNTER_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPF_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
+	 { "SPM_PERFMON_STATE", 4, 7, &umr_bitfield_default },
+	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_OBJECT[] = {
+	 { "OBJECT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_OBJECT_COUNTER[] = {
+	 { "COUNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_MASK_HI[] = {
+	 { "WINDOW_MASK_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_HI[] = {
+	 { "WINDOW_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_LO[] = {
+	 { "MIN", 0, 15, &umr_bitfield_default },
+	 { "MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_DRAW_WINDOW_CNTL[] = {
+	 { "DISABLE_DRAW_WINDOW_LO_MAX", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_DRAW_WINDOW_LO_MIN", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_DRAW_WINDOW_HI", 2, 2, &umr_bitfield_default },
+	 { "MODE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 14, 14, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "GRBM_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+	 { "CP_BUSY_USER_DEFINED_MASK", 22, 22, &umr_bitfield_default },
+	 { "IA_BUSY_USER_DEFINED_MASK", 23, 23, &umr_bitfield_default },
+	 { "GDS_BUSY_USER_DEFINED_MASK", 24, 24, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 25, 25, &umr_bitfield_default },
+	 { "RLC_BUSY_USER_DEFINED_MASK", 26, 26, &umr_bitfield_default },
+	 { "TC_BUSY_USER_DEFINED_MASK", 27, 27, &umr_bitfield_default },
+	 { "WD_BUSY_USER_DEFINED_MASK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE0_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE1_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE2_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_SE3_PERFCOUNTER_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+	 { "DB_CLEAN_USER_DEFINED_MASK", 10, 10, &umr_bitfield_default },
+	 { "CB_CLEAN_USER_DEFINED_MASK", 11, 11, &umr_bitfield_default },
+	 { "TA_BUSY_USER_DEFINED_MASK", 12, 12, &umr_bitfield_default },
+	 { "SX_BUSY_USER_DEFINED_MASK", 13, 13, &umr_bitfield_default },
+	 { "SPI_BUSY_USER_DEFINED_MASK", 15, 15, &umr_bitfield_default },
+	 { "SC_BUSY_USER_DEFINED_MASK", 16, 16, &umr_bitfield_default },
+	 { "DB_BUSY_USER_DEFINED_MASK", 17, 17, &umr_bitfield_default },
+	 { "CB_BUSY_USER_DEFINED_MASK", 18, 18, &umr_bitfield_default },
+	 { "VGT_BUSY_USER_DEFINED_MASK", 19, 19, &umr_bitfield_default },
+	 { "PA_BUSY_USER_DEFINED_MASK", 20, 20, &umr_bitfield_default },
+	 { "BCI_BUSY_USER_DEFINED_MASK", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmWD_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVGT_PERFCOUNTER_SEID_MASK[] = {
+	 { "PERF_SEID_IGNORE_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SU_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPA_SC_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER2_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER3_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSPI_PERFCOUNTER_BINS[] = {
+	 { "BIN0_MIN", 0, 3, &umr_bitfield_default },
+	 { "BIN0_MAX", 4, 7, &umr_bitfield_default },
+	 { "BIN1_MIN", 8, 11, &umr_bitfield_default },
+	 { "BIN1_MAX", 12, 15, &umr_bitfield_default },
+	 { "BIN2_MIN", 16, 19, &umr_bitfield_default },
+	 { "BIN2_MAX", 20, 23, &umr_bitfield_default },
+	 { "BIN3_MIN", 24, 27, &umr_bitfield_default },
+	 { "BIN3_MAX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER4_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER5_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER6_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER7_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER8_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER9_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER10_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER11_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER12_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER13_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER14_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER15_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "SQC_BANK_MASK", 12, 15, &umr_bitfield_default },
+	 { "SQC_CLIENT_MASK", 16, 19, &umr_bitfield_default },
+	 { "SPM_MODE", 20, 23, &umr_bitfield_default },
+	 { "SIMD_MASK", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL[] = {
+	 { "PS_EN", 0, 0, &umr_bitfield_default },
+	 { "VS_EN", 1, 1, &umr_bitfield_default },
+	 { "GS_EN", 2, 2, &umr_bitfield_default },
+	 { "ES_EN", 3, 3, &umr_bitfield_default },
+	 { "HS_EN", 4, 4, &umr_bitfield_default },
+	 { "LS_EN", 5, 5, &umr_bitfield_default },
+	 { "CS_EN", 6, 6, &umr_bitfield_default },
+	 { "CNTR_RATE", 8, 12, &umr_bitfield_default },
+	 { "DISABLE_FLUSH", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_MASK[] = {
+	 { "SH0_MASK", 0, 15, &umr_bitfield_default },
+	 { "SH1_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_PERFCOUNTER_CTRL2[] = {
+	 { "FORCE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER2_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER3_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER0_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSX_PERFCOUNTER1_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER2_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER3_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGDS_PERFCOUNTER0_SELECT1[] = {
+	 { "PERFCOUNTER_SELECT2", 0, 9, &umr_bitfield_default },
+	 { "PERFCOUNTER_SELECT3", 10, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 17, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 17, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 17, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCP_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE2", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER_FILTER[] = {
+	 { "OP_FILTER_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "OP_FILTER_SEL", 1, 3, &umr_bitfield_default },
+	 { "FORMAT_FILTER_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "FORMAT_FILTER_SEL", 5, 9, &umr_bitfield_default },
+	 { "CLEAR_FILTER_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "CLEAR_FILTER_SEL", 11, 11, &umr_bitfield_default },
+	 { "MRT_FILTER_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "MRT_FILTER_SEL", 13, 15, &umr_bitfield_default },
+	 { "NUM_SAMPLES_FILTER_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "NUM_SAMPLES_FILTER_SEL", 18, 20, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS_FILTER_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "NUM_FRAGMENTS_FILTER_SEL", 22, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 18, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 8, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 18, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 8, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER0_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER1_SELECT1[] = {
+	 { "PERF_SEL2", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL3", 10, 19, &umr_bitfield_default },
+	 { "PERF_MODE3", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE2", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER2_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_PERFCOUNTER3_SELECT[] = {
+	 { "PERF_SEL", 0, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 19, &umr_bitfield_default },
+	 { "CNTR_MODE", 20, 23, &umr_bitfield_default },
+	 { "PERF_MODE1", 24, 27, &umr_bitfield_default },
+	 { "PERF_MODE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_CNTL[] = {
+	 { "RESERVED1", 0, 11, &umr_bitfield_default },
+	 { "PERFMON_RING_MODE", 12, 13, &umr_bitfield_default },
+	 { "RESERVED", 14, 15, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_BASE_LO[] = {
+	 { "RING_BASE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_BASE_HI[] = {
+	 { "RING_BASE_HI", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_RING_SIZE[] = {
+	 { "RING_BASE_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PERFMON_SEGMENT_SIZE[] = {
+	 { "PERFMON_SEGMENT_SIZE", 0, 7, &umr_bitfield_default },
+	 { "RESERVED1", 8, 10, &umr_bitfield_default },
+	 { "GLOBAL_NUM_LINE", 11, 15, &umr_bitfield_default },
+	 { "SE0_NUM_LINE", 16, 20, &umr_bitfield_default },
+	 { "SE1_NUM_LINE", 21, 25, &umr_bitfield_default },
+	 { "SE2_NUM_LINE", 26, 30, &umr_bitfield_default },
+	 { "RESERVED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SE_MUXSEL_ADDR[] = {
+	 { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SE_MUXSEL_DATA[] = {
+	 { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[] = {
+	 { "PERFMON_SAMPLE_DELAY", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GLOBAL_MUXSEL_ADDR[] = {
+	 { "PERFMON_SEL_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_GLOBAL_MUXSEL_DATA[] = {
+	 { "PERFMON_SEL_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_RING_RDPTR[] = {
+	 { "PERFMON_RING_RDPTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_SEGMENT_THRESHOLD[] = {
+	 { "NUM_SEGMENT_THRESHOLD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFMON_CLK_CNTL[] = {
+	 { "PERFMON_CLOCK_STATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 2, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER0_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PERFCOUNTER1_SELECT[] = {
+	 { "PERFCOUNTER_SELECT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG14[] = {
+	 { "clprim_in_back_vertex_store_indx_2", 0, 5, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_1", 6, 11, &umr_bitfield_default },
+	 { "clprim_in_back_vertex_store_indx_0", 12, 17, &umr_bitfield_default },
+	 { "outputclprimtoclip_null_primitive", 18, 18, &umr_bitfield_default },
+	 { "clprim_in_back_end_of_packet", 19, 19, &umr_bitfield_default },
+	 { "clprim_in_back_first_prim_of_slot", 20, 20, &umr_bitfield_default },
+	 { "clprim_in_back_deallocate_slot", 21, 23, &umr_bitfield_default },
+	 { "clprim_in_back_event_id", 24, 29, &umr_bitfield_default },
+	 { "clprim_in_back_event", 30, 30, &umr_bitfield_default },
+	 { "prim_back_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG14[] = {
+	 { "SPARE3", 0, 3, &umr_bitfield_default },
+	 { "gsfetch_done_fifo_full", 4, 4, &umr_bitfield_default },
+	 { "gs_rb_space_avail_r0", 5, 5, &umr_bitfield_default },
+	 { "smx_es_done_cnt_r0_q_not_0", 6, 6, &umr_bitfield_default },
+	 { "SPARE8", 7, 8, &umr_bitfield_default },
+	 { "vs_done_cnt_q_not_0", 9, 9, &umr_bitfield_default },
+	 { "es_flush_cnt_busy_q", 10, 10, &umr_bitfield_default },
+	 { "gs_tbl_full_r0", 11, 11, &umr_bitfield_default },
+	 { "SPARE2", 12, 20, &umr_bitfield_default },
+	 { "se1spi_gsthread_fifo_busy", 21, 21, &umr_bitfield_default },
+	 { "SPARE", 22, 24, &umr_bitfield_default },
+	 { "VGT_SE1SPI_gsthread_rtr_q", 25, 25, &umr_bitfield_default },
+	 { "smx1_es_done_cnt_r0_q_not_0", 26, 26, &umr_bitfield_default },
+	 { "se1spi_esthread_fifo_busy", 27, 27, &umr_bitfield_default },
+	 { "SPARE1", 28, 28, &umr_bitfield_default },
+	 { "gsfetch_done_se1_cnt_q_not_0", 29, 29, &umr_bitfield_default },
+	 { "SPARE0", 30, 30, &umr_bitfield_default },
+	 { "VGT_SE1SPI_esthread_rtr_q", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CNTL[] = {
+	 { "RLC_ENABLE_F32", 0, 0, &umr_bitfield_default },
+	 { "FORCE_RETRY", 1, 1, &umr_bitfield_default },
+	 { "READ_CACHE_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "RLC_STEP_F32", 3, 3, &umr_bitfield_default },
+	 { "SOFT_RESET_DEBUG_MODE", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MC_CNTL[] = {
+	 { "WRREQ_SWAP", 0, 1, &umr_bitfield_default },
+	 { "WRREQ_TRAN", 2, 2, &umr_bitfield_default },
+	 { "WRREQ_PRIV", 3, 3, &umr_bitfield_default },
+	 { "WRNFO_STALL", 4, 4, &umr_bitfield_default },
+	 { "WRNFO_URG", 5, 8, &umr_bitfield_default },
+	 { "WRREQ_DW_IMASK", 9, 12, &umr_bitfield_default },
+	 { "RESERVED_B", 13, 19, &umr_bitfield_default },
+	 { "RDNFO_URG", 20, 23, &umr_bitfield_default },
+	 { "RDREQ_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RDREQ_TRAN", 26, 26, &umr_bitfield_default },
+	 { "RDREQ_PRIV", 27, 27, &umr_bitfield_default },
+	 { "RDNFO_STALL", 28, 28, &umr_bitfield_default },
+	 { "RESERVED", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_STAT[] = {
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "RLC_GPM_BUSY", 1, 1, &umr_bitfield_default },
+	 { "RLC_SPM_BUSY", 2, 2, &umr_bitfield_default },
+	 { "RLC_SRM_BUSY", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SAFE_MODE[] = {
+	 { "CMD", 0, 0, &umr_bitfield_default },
+	 { "MESSAGE", 1, 4, &umr_bitfield_default },
+	 { "RESERVED1", 5, 7, &umr_bitfield_default },
+	 { "RESPONSE", 8, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MEM_SLP_CNTL[] = {
+	 { "RLC_MEM_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "RLC_MEM_DS_EN", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 6, &umr_bitfield_default },
+	 { "RLC_LS_DS_BUSY_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "RLC_MEM_LS_ON_DELAY", 8, 15, &umr_bitfield_default },
+	 { "RLC_MEM_LS_OFF_DELAY", 16, 23, &umr_bitfield_default },
+	 { "RESERVED1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_RLC_RESPONSE[] = {
+	 { "RESP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_RLCV_SAFE_MODE[] = {
+	 { "CMD", 0, 0, &umr_bitfield_default },
+	 { "MESSAGE", 1, 4, &umr_bitfield_default },
+	 { "RESERVED1", 5, 7, &umr_bitfield_default },
+	 { "RESPONSE", 8, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_SAFE_MODE[] = {
+	 { "CMD", 0, 0, &umr_bitfield_default },
+	 { "MESSAGE", 1, 4, &umr_bitfield_default },
+	 { "RESERVED1", 5, 7, &umr_bitfield_default },
+	 { "RESPONSE", 8, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_RLCV_COMMAND[] = {
+	 { "CMD", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CLK_CNTL[] = {
+	 { "RLC_SRM_CLK_CNTL", 0, 0, &umr_bitfield_default },
+	 { "RLC_SPM_CLK_CNTL", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTR_MAX[] = {
+	 { "LB_CNTR_MAX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTL[] = {
+	 { "LOAD_BALANCE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LB_CNT_CP_BUSY", 1, 1, &umr_bitfield_default },
+	 { "LB_CNT_SPIM_ACTIVE", 2, 2, &umr_bitfield_default },
+	 { "LB_CNT_REG_INC", 3, 3, &umr_bitfield_default },
+	 { "CU_MASK_USED_OFF_HYST", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MGCG_CTRL[] = {
+	 { "MGCG_EN", 0, 0, &umr_bitfield_default },
+	 { "SILICON_EN", 1, 1, &umr_bitfield_default },
+	 { "SIMULATION_EN", 2, 2, &umr_bitfield_default },
+	 { "ON_DELAY", 3, 6, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 7, 14, &umr_bitfield_default },
+	 { "GC_CAC_MGCG_CLK_CNTL", 15, 15, &umr_bitfield_default },
+	 { "SE_CAC_MGCG_CLK_CNTL", 16, 16, &umr_bitfield_default },
+	 { "SPARE", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_CNTR_INIT[] = {
+	 { "LB_CNTR_INIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LOAD_BALANCE_CNTR[] = {
+	 { "RLC_LOAD_BALANCE_CNTR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG_INST_ADDR[] = {
+	 { "ADRR_A", 0, 15, &umr_bitfield_default },
+	 { "ADDR_B", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_JUMP_TABLE_RESTORE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_DELAY_2[] = {
+	 { "SERDES_TIMEOUT_VALUE", 0, 7, &umr_bitfield_default },
+	 { "SERDES_CMD_DELAY", 8, 15, &umr_bitfield_default },
+	 { "PERCU_TIMEOUT_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "F32_DEBUG_SELECT", 8, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG_INST_A[] = {
+	 { "INST_A", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_DEBUG_INST_B[] = {
+	 { "INST_B", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_LSB[] = {
+	 { "GPU_CLOCKS_LSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_COUNT_MSB[] = {
+	 { "GPU_CLOCKS_MSB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CAPTURE_GPU_CLOCK_COUNT[] = {
+	 { "CAPTURE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_UCODE_CNTL[] = {
+	 { "RLC_UCODE_FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_THREAD_RESET[] = {
+	 { "THREAD0_RESET", 0, 0, &umr_bitfield_default },
+	 { "THREAD1_RESET", 1, 1, &umr_bitfield_default },
+	 { "THREAD2_RESET", 2, 2, &umr_bitfield_default },
+	 { "THREAD3_RESET", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_STAT[] = {
+	 { "RLC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_STATUS", 1, 1, &umr_bitfield_default },
+	 { "GFX_CLOCK_STATUS", 2, 2, &umr_bitfield_default },
+	 { "GFX_LS_STATUS", 3, 3, &umr_bitfield_default },
+	 { "GFX_PIPELINE_POWER_STATUS", 4, 4, &umr_bitfield_default },
+	 { "CNTX_IDLE_BEING_PROCESSED", 5, 5, &umr_bitfield_default },
+	 { "CNTX_BUSY_BEING_PROCESSED", 6, 6, &umr_bitfield_default },
+	 { "GFX_IDLE_BEING_PROCESSED", 7, 7, &umr_bitfield_default },
+	 { "CMP_BUSY_BEING_PROCESSED", 8, 8, &umr_bitfield_default },
+	 { "SAVING_REGISTERS", 9, 9, &umr_bitfield_default },
+	 { "RESTORING_REGISTERS", 10, 10, &umr_bitfield_default },
+	 { "GFX3D_BLOCKS_CHANGING_POWER_STATE", 11, 11, &umr_bitfield_default },
+	 { "CMP_BLOCKS_CHANGING_POWER_STATE", 12, 12, &umr_bitfield_default },
+	 { "STATIC_CU_POWERING_UP", 13, 13, &umr_bitfield_default },
+	 { "STATIC_CU_POWERING_DOWN", 14, 14, &umr_bitfield_default },
+	 { "DYN_CU_POWERING_UP", 15, 15, &umr_bitfield_default },
+	 { "DYN_CU_POWERING_DOWN", 16, 16, &umr_bitfield_default },
+	 { "ABORTED_PD_SEQUENCE", 17, 17, &umr_bitfield_default },
+	 { "RESERVED", 18, 23, &umr_bitfield_default },
+	 { "PG_ERROR_STATUS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_32_RES_SEL[] = {
+	 { "RES_SEL", 0, 5, &umr_bitfield_default },
+	 { "RESERVED", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_CLOCK_32[] = {
+	 { "GPU_CLOCK_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_CNTL[] = {
+	 { "GFX_POWER_GATING_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "GFX_POWER_GATING_SRC", 1, 1, &umr_bitfield_default },
+	 { "DYN_PER_CU_PG_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "STATIC_PER_CU_PG_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "GFX_PIPELINE_PG_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 13, &umr_bitfield_default },
+	 { "PG_OVERRIDE", 14, 14, &umr_bitfield_default },
+	 { "CP_PG_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "CHUB_HANDSHAKE_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PU_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "SMU_CLK_SLOWDOWN_ON_PD_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "SMU_HANDSHAKE_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "RESERVED1", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_THREAD_PRIORITY[] = {
+	 { "THREAD0_PRIORITY", 0, 7, &umr_bitfield_default },
+	 { "THREAD1_PRIORITY", 8, 15, &umr_bitfield_default },
+	 { "THREAD2_PRIORITY", 16, 23, &umr_bitfield_default },
+	 { "THREAD3_PRIORITY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_THREAD_ENABLE[] = {
+	 { "THREAD0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "THREAD1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "THREAD2_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "THREAD3_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_VMID_THREAD0[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED0", 4, 7, &umr_bitfield_default },
+	 { "RLC_QUEUEID", 8, 10, &umr_bitfield_default },
+	 { "RESERVED1", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_VMID_THREAD1[] = {
+	 { "RLC_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED0", 4, 7, &umr_bitfield_default },
+	 { "RLC_QUEUEID", 8, 10, &umr_bitfield_default },
+	 { "RESERVED1", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGTT_MGCG_OVERRIDE[] = {
+	 { "OVERRIDE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGCG_CGLS_CTRL[] = {
+	 { "CGCG_EN", 0, 0, &umr_bitfield_default },
+	 { "CGLS_EN", 1, 1, &umr_bitfield_default },
+	 { "CGLS_REP_COMPANSAT_DELAY", 2, 7, &umr_bitfield_default },
+	 { "CGCG_GFX_IDLE_THRESHOLD", 8, 26, &umr_bitfield_default },
+	 { "CGCG_CONTROLLER", 27, 27, &umr_bitfield_default },
+	 { "CGCG_REG_CTRL", 28, 28, &umr_bitfield_default },
+	 { "SLEEP_MODE", 29, 30, &umr_bitfield_default },
+	 { "SIM_SILICON_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CGCG_RAMP_CTRL[] = {
+	 { "DOWN_DIV_START_UNIT", 0, 3, &umr_bitfield_default },
+	 { "DOWN_DIV_STEP_UNIT", 4, 7, &umr_bitfield_default },
+	 { "UP_DIV_START_UNIT", 8, 11, &umr_bitfield_default },
+	 { "UP_DIV_STEP_UNIT", 12, 15, &umr_bitfield_default },
+	 { "STEP_DELAY_CNT", 16, 27, &umr_bitfield_default },
+	 { "STEP_DELAY_UNIT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DYN_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_DYN_PG_REQUEST[] = {
+	 { "PG_REQUEST_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_DELAY[] = {
+	 { "POWER_UP_DELAY", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN_DELAY", 8, 15, &umr_bitfield_default },
+	 { "CMD_PROPAGATE_DELAY", 16, 23, &umr_bitfield_default },
+	 { "MEM_SLEEP_DELAY", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CU_STATUS[] = {
+	 { "WORK_PENDING", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_INIT_CU_MASK[] = {
+	 { "INIT_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[] = {
+	 { "ALWAYS_ACTIVE_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_LB_PARAMS[] = {
+	 { "SKIP_L2_CHECK", 0, 0, &umr_bitfield_default },
+	 { "FIFO_SAMPLES", 1, 7, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLES", 8, 15, &umr_bitfield_default },
+	 { "PG_IDLE_SAMPLE_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_THREAD1_DELAY[] = {
+	 { "CU_IDEL_DELAY", 0, 7, &umr_bitfield_default },
+	 { "LBPW_INNER_LOOP_DELAY", 8, 15, &umr_bitfield_default },
+	 { "LBPW_OUTER_LOOP_DELAY", 16, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_ALWAYS_ON_CU_MASK[] = {
+	 { "AON_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_MAX_PG_CU[] = {
+	 { "MAX_POWERED_UP_CU", 0, 7, &umr_bitfield_default },
+	 { "SPARE", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_AUTO_PG_CTRL[] = {
+	 { "AUTO_PG_EN", 0, 0, &umr_bitfield_default },
+	 { "AUTO_GRBM_REG_SAVE_ON_IDLE_EN", 1, 1, &umr_bitfield_default },
+	 { "AUTO_WAKE_UP_EN", 2, 2, &umr_bitfield_default },
+	 { "GRBM_REG_SAVE_GFX_IDLE_THRESHOLD", 3, 18, &umr_bitfield_default },
+	 { "PG_AFTER_GRBM_REG_SAVE_THRESHOLD", 19, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_GRBM_REG_SAVE_CTRL[] = {
+	 { "START_GRBM_REG_SAVE", 0, 0, &umr_bitfield_default },
+	 { "SPARE", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_MASTER_INDEX[] = {
+	 { "CU_ID", 0, 3, &umr_bitfield_default },
+	 { "SH_ID", 4, 5, &umr_bitfield_default },
+	 { "SE_ID", 6, 8, &umr_bitfield_default },
+	 { "SE_NONCU_ID", 9, 9, &umr_bitfield_default },
+	 { "SE_NONCU", 10, 10, &umr_bitfield_default },
+	 { "NON_SE", 11, 14, &umr_bitfield_default },
+	 { "DATA_REG_ID", 15, 16, &umr_bitfield_default },
+	 { "SPARE", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_RD_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_CU_MASTER_MASK[] = {
+	 { "MASTER_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_NONCU_MASTER_MASK[] = {
+	 { "SE_MASTER_MASK", 0, 15, &umr_bitfield_default },
+	 { "GC_MASTER_MASK", 16, 16, &umr_bitfield_default },
+	 { "GC_GFX_MASTER_MASK", 17, 17, &umr_bitfield_default },
+	 { "TC0_MASTER_MASK", 18, 18, &umr_bitfield_default },
+	 { "TC1_MASTER_MASK", 19, 19, &umr_bitfield_default },
+	 { "SPARE0_MASTER_MASK", 20, 20, &umr_bitfield_default },
+	 { "SPARE1_MASTER_MASK", 21, 21, &umr_bitfield_default },
+	 { "SPARE2_MASTER_MASK", 22, 22, &umr_bitfield_default },
+	 { "SPARE3_MASTER_MASK", 23, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_CTRL[] = {
+	 { "BPM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE_COMMAND", 12, 12, &umr_bitfield_default },
+	 { "READ_COMMAND", 13, 13, &umr_bitfield_default },
+	 { "RDDATA_RESET", 14, 14, &umr_bitfield_default },
+	 { "SHORT_FORMAT", 15, 15, &umr_bitfield_default },
+	 { "BPM_DATA", 16, 25, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "RSVD_BPM_ADDR", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_WR_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_CU_MASTER_BUSY[] = {
+	 { "BUSY_BUSY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SERDES_NONCU_MASTER_BUSY[] = {
+	 { "SE_MASTER_BUSY", 0, 15, &umr_bitfield_default },
+	 { "GC_MASTER_BUSY", 16, 16, &umr_bitfield_default },
+	 { "GC_GFX_MASTER_BUSY", 17, 17, &umr_bitfield_default },
+	 { "TC0_MASTER_BUSY", 18, 18, &umr_bitfield_default },
+	 { "TC1_MASTER_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SPARE0_MASTER_BUSY", 20, 20, &umr_bitfield_default },
+	 { "SPARE1_MASTER_BUSY", 21, 21, &umr_bitfield_default },
+	 { "SPARE2_MASTER_BUSY", 22, 22, &umr_bitfield_default },
+	 { "SPARE3_MASTER_BUSY", 23, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_SCRATCH_ADDR[] = {
+	 { "ADDR", 0, 8, &umr_bitfield_default },
+	 { "RESERVED", 9, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_SCRATCH_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_STATIC_PG_STATUS[] = {
+	 { "PG_STATUS_CU_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_PERF_COUNT_0[] = {
+	 { "FEATURE_SEL", 0, 3, &umr_bitfield_default },
+	 { "SE_INDEX", 4, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 11, &umr_bitfield_default },
+	 { "CU_INDEX", 12, 15, &umr_bitfield_default },
+	 { "EVENT_SEL", 16, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 19, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_PERF_COUNT_1[] = {
+	 { "FEATURE_SEL", 0, 3, &umr_bitfield_default },
+	 { "SE_INDEX", 4, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 11, &umr_bitfield_default },
+	 { "CU_INDEX", 12, 15, &umr_bitfield_default },
+	 { "EVENT_SEL", 16, 17, &umr_bitfield_default },
+	 { "UNUSED", 18, 19, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_VMID[] = {
+	 { "RLC_SPM_VMID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_INT_CNTL[] = {
+	 { "RLC_SPM_INT_CNTL", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_INT_STATUS[] = {
+	 { "RLC_SPM_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 14, &umr_bitfield_default },
+	 { "RLC_SPM_DEBUG_MODE", 15, 15, &umr_bitfield_default },
+	 { "RLC_SPM_NUM_SAMPLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SPM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_MESSAGE[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_LOG_SIZE[] = {
+	 { "SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_PG_DELAY_3[] = {
+	 { "CGCG_ACTIVE_BEFORE_CGPG", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPR_REG1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPR_REG2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_LOG_CONT[] = {
+	 { "CONT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_INT_DISABLE_TH0[] = {
+	 { "DISABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_INT_DISABLE_TH1[] = {
+	 { "DISABLE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_INT_FORCE_TH0[] = {
+	 { "FORCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_INT_FORCE_TH1[] = {
+	 { "FORCE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_CNTL[] = {
+	 { "SRM_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCR_ADDR", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_DEBUG_SELECT[] = {
+	 { "SELECT", 0, 7, &umr_bitfield_default },
+	 { "RESERVED", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_DEBUG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_ARAM_ADDR[] = {
+	 { "ADDR", 0, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_ARAM_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_DRAM_ADDR[] = {
+	 { "ADDR", 0, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_DRAM_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_GPM_COMMAND[] = {
+	 { "OP", 0, 0, &umr_bitfield_default },
+	 { "INDEX_CNTL", 1, 1, &umr_bitfield_default },
+	 { "INDEX_CNTL_NUM", 2, 4, &umr_bitfield_default },
+	 { "SIZE", 5, 16, &umr_bitfield_default },
+	 { "START_OFFSET", 17, 28, &umr_bitfield_default },
+	 { "RESERVED1", 29, 30, &umr_bitfield_default },
+	 { "DEST_MEMORY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_GPM_COMMAND_STATUS[] = {
+	 { "FIFO_EMPTY", 0, 0, &umr_bitfield_default },
+	 { "FIFO_FULL", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_RLCV_COMMAND[] = {
+	 { "OP", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 3, &umr_bitfield_default },
+	 { "SIZE", 4, 15, &umr_bitfield_default },
+	 { "START_OFFSET", 16, 27, &umr_bitfield_default },
+	 { "RESERVED1", 28, 30, &umr_bitfield_default },
+	 { "DEST_MEMORY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_RLCV_COMMAND_STATUS[] = {
+	 { "FIFO_EMPTY", 0, 0, &umr_bitfield_default },
+	 { "FIFO_FULL", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_0[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_1[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_2[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_3[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_4[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_5[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_6[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_ADDR_7[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_INDEX_CNTL_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_STAT[] = {
+	 { "SRM_STATUS", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SRM_GPM_ABORT[] = {
+	 { "ABORT", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CSIB_ADDR_LO[] = {
+	 { "ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CSIB_ADDR_HI[] = {
+	 { "ADDRESS", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CSIB_LENGTH[] = {
+	 { "LENGTH", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_RESPONSE0[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_RESPONSE1[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_RESPONSE2[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_RESPONSE3[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_COMMAND[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_CP_SCHEDULERS[] = {
+	 { "scheduler0", 0, 7, &umr_bitfield_default },
+	 { "scheduler1", 8, 15, &umr_bitfield_default },
+	 { "scheduler2", 16, 23, &umr_bitfield_default },
+	 { "scheduler3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_ARGUMENT_1[] = {
+	 { "ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_SMU_ARGUMENT_2[] = {
+	 { "ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_GENERAL_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIPPER_DEBUG_REG15[] = {
+	 { "vertval_bits_vertex_vertex_store_msb", 0, 15, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_2", 16, 20, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_1", 21, 25, &umr_bitfield_default },
+	 { "primic_to_clprim_fifo_vertex_store_indx_0", 26, 30, &umr_bitfield_default },
+	 { "primic_to_clprim_valid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVGT_DEBUG_REG15[] = {
+	 { "cm_busy_q", 0, 0, &umr_bitfield_default },
+	 { "counters_busy_q", 1, 1, &umr_bitfield_default },
+	 { "output_fifo_empty", 2, 2, &umr_bitfield_default },
+	 { "output_fifo_full", 3, 3, &umr_bitfield_default },
+	 { "counters_full", 4, 4, &umr_bitfield_default },
+	 { "active_sm_q", 5, 9, &umr_bitfield_default },
+	 { "entry_rdptr_q", 10, 14, &umr_bitfield_default },
+	 { "cntr_tbl_wrptr_q", 15, 19, &umr_bitfield_default },
+	 { "SPARE25", 20, 25, &umr_bitfield_default },
+	 { "st_cut_mode_q", 26, 27, &umr_bitfield_default },
+	 { "gs_done_array_q_not_0", 28, 28, &umr_bitfield_default },
+	 { "SPARE31", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_SM_CTRL_REG[] = {
+	 { "ON_SEQ_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_SEQ_DELAY", 4, 11, &umr_bitfield_default },
+	 { "MGCG_ENABLED", 12, 12, &umr_bitfield_default },
+	 { "BASE_MODE", 16, 16, &umr_bitfield_default },
+	 { "SM_MODE", 17, 19, &umr_bitfield_default },
+	 { "SM_MODE_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "OVERRIDE", 21, 21, &umr_bitfield_default },
+	 { "LS_OVERRIDE", 22, 22, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD_EN", 23, 23, &umr_bitfield_default },
+	 { "ON_MONITOR_ADD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_RD_CTRL_REG[] = {
+	 { "ROW_MUX_SEL", 0, 4, &umr_bitfield_default },
+	 { "REG_MUX_SEL", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_RD_REG[] = {
+	 { "READ_DATA", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_USER_TCC_DISABLE[] = {
+	 { "TCC_DISABLE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU0_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU1_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU2_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU3_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU4_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU5_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU6_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU7_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU8_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU9_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU10_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU11_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_TA_SQC_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQC", 16, 22, &umr_bitfield_default },
+	 { "SQC_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQC_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQC_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQC_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU12_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU13_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU14_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_SP0_CTRL_REG[] = {
+	 { "SP00", 0, 6, &umr_bitfield_default },
+	 { "SP00_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP00_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP00_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP00_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP01", 16, 22, &umr_bitfield_default },
+	 { "SP01_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP01_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP01_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP01_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_LDS_SQ_CTRL_REG[] = {
+	 { "LDS", 0, 6, &umr_bitfield_default },
+	 { "LDS_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "LDS_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "LDS_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "LDS_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SQ", 16, 22, &umr_bitfield_default },
+	 { "SQ_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SQ_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SQ_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SQ_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_TA_CTRL_REG[] = {
+	 { "TA", 0, 6, &umr_bitfield_default },
+	 { "TA_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TA_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TA_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TA_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_SP1_CTRL_REG[] = {
+	 { "SP10", 0, 6, &umr_bitfield_default },
+	 { "SP10_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "SP10_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "SP10_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "SP10_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "SP11", 16, 22, &umr_bitfield_default },
+	 { "SP11_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "SP11_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "SP11_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "SP11_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTS_CU15_TD_TCP_CTRL_REG[] = {
+	 { "TD", 0, 6, &umr_bitfield_default },
+	 { "TD_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "TD_BUSY_OVERRIDE", 8, 9, &umr_bitfield_default },
+	 { "TD_LS_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "TD_SIMDBUSY_OVERRIDE", 11, 11, &umr_bitfield_default },
+	 { "TCP", 16, 22, &umr_bitfield_default },
+	 { "TCP_OVERRIDE", 23, 23, &umr_bitfield_default },
+	 { "TCP_BUSY_OVERRIDE", 24, 25, &umr_bitfield_default },
+	 { "TCP_LS_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "TCP_SIMDBUSY_OVERRIDE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SPI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "ALL_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "GRP3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "GRP2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "GRP1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "GRP0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_PC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "GRP5_CG_OFF_HYST", 18, 23, &umr_bitfield_default },
+	 { "GRP5_CG_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "BACK_CLK_ON_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "FRONT_CLK_ON_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_BCI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "CORE6_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "CORE5_OVERRIDE", 25, 25, &umr_bitfield_default },
+	 { "CORE4_OVERRIDE", 26, 26, &umr_bitfield_default },
+	 { "CORE3_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "CORE2_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE1_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE0_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_VGT_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "TESS_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "GS_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_IA_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_WD_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "PERF_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DBG_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "TESS_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "RBIU_INPUT_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_PA_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SU_CLK_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CL_CLK_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_CLK_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SQ_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "PERFMON_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SQG_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "TTRACE_OVERRIDE", 28, 28, &umr_bitfield_default },
+	 { "PERFMON_OVERRIDE", 29, 29, &umr_bitfield_default },
+	 { "CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_ALU_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_TEX_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_LDS_CLK_CTRL[] = {
+	 { "FORCE_CU_ON_SH0", 0, 15, &umr_bitfield_default },
+	 { "FORCE_CU_ON_SH1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_POWER_THROTTLE[] = {
+	 { "MIN_POWER", 0, 13, &umr_bitfield_default },
+	 { "MAX_POWER", 16, 29, &umr_bitfield_default },
+	 { "PHASE_OFFSET", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_POWER_THROTTLE2[] = {
+	 { "MAX_POWER_DELTA", 0, 13, &umr_bitfield_default },
+	 { "SHORT_TERM_INTERVAL_SIZE", 16, 25, &umr_bitfield_default },
+	 { "LONG_TERM_INTERVAL_RATIO", 27, 30, &umr_bitfield_default },
+	 { "USE_REF_CLOCK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL1[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "DBG_EN", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL2[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "DBG_EN", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL3[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "DBG_EN", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_SX_CLK_CTRL4[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "DBG_EN", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTD_CGTT_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTA_CGTT_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_TCP_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_TCI_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_GDS_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDB_CGTT_CLK_CTRL_0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 23, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCB_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCC_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmTCA_CGTT_SCLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CP_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CPF_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_CPC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_PERFMON", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCGTT_RLC_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_PFP_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_RADDR[] = {
+	 { "ME_RAM_RADDR", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_ME_RAM_DATA[] = {
+	 { "ME_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CE_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME1_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_MEC_ME2_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPU_BIST_CONTROL[] = {
+	 { "STOP_ON_FAIL_HW", 0, 0, &umr_bitfield_default },
+	 { "STOP_ON_FAIL_CU_HARV", 1, 1, &umr_bitfield_default },
+	 { "CU_HARV_LOOP_COUNT", 2, 5, &umr_bitfield_default },
+	 { "RESERVED", 7, 23, &umr_bitfield_default },
+	 { "GLOBAL_LOOP_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_ROM_CNTL[] = {
+	 { "USE_ROM", 0, 0, &umr_bitfield_default },
+	 { "SLP_MODE_EN", 1, 1, &umr_bitfield_default },
+	 { "EFUSE_DISTRIB_EN", 2, 2, &umr_bitfield_default },
+	 { "HELLOWORLD_EN", 3, 3, &umr_bitfield_default },
+	 { "CU_HARVEST_EN", 4, 4, &umr_bitfield_default },
+	 { "RESERVED", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_UCODE_ADDR[] = {
+	 { "UCODE_ADDR", 0, 11, &umr_bitfield_default },
+	 { "RESERVED", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPM_UCODE_DATA[] = {
+	 { "UCODE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_HYP_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_HYP_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGRBM_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSQ_HV_VMID_CTRL[] = {
+	 { "DEFAULT_VMID", 0, 3, &umr_bitfield_default },
+	 { "ALLOWED_VMID_MASK", 4, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 15, &umr_bitfield_default },
+	 { "VF_NUM", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_ACTIVE_FCN_ID[] = {
+	 { "VF_ID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 30, &umr_bitfield_default },
+	 { "PF_VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmRLC_GPU_IOV_RLC_RESPONSE[] = {
+	 { "RESP", 0, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gfx81_regs.i b/src/lib/ip/gfx81_regs.i
new file mode 100644
index 0000000..1b4ff78
--- /dev/null
+++ b/src/lib/ip/gfx81_regs.i
@@ -0,0 +1,2705 @@
+	{ "ixCLIPPER_DEBUG_REG00", REG_SMC, 0x0, &ixCLIPPER_DEBUG_REG00[0], sizeof(ixCLIPPER_DEBUG_REG00)/sizeof(ixCLIPPER_DEBUG_REG00[0]), 0, 0 },
+	{ "ixPA_SC_DEBUG_REG0", REG_SMC, 0x0, &ixPA_SC_DEBUG_REG0[0], sizeof(ixPA_SC_DEBUG_REG0)/sizeof(ixPA_SC_DEBUG_REG0[0]), 0, 0 },
+	{ "mmCSPRIV_CONNECT", REG_MMIO, 0x0, &mmCSPRIV_CONNECT[0], sizeof(mmCSPRIV_CONNECT)/sizeof(mmCSPRIV_CONNECT[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG0", REG_SMC, 0x0, &ixWD_DEBUG_REG0[0], sizeof(ixWD_DEBUG_REG0)/sizeof(ixWD_DEBUG_REG0[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG01", REG_SMC, 0x1, &ixCLIPPER_DEBUG_REG01[0], sizeof(ixCLIPPER_DEBUG_REG01)/sizeof(ixCLIPPER_DEBUG_REG01[0]), 0, 0 },
+	{ "ixPA_SC_DEBUG_REG1", REG_SMC, 0x1, &ixPA_SC_DEBUG_REG1[0], sizeof(ixPA_SC_DEBUG_REG1)/sizeof(ixPA_SC_DEBUG_REG1[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG1", REG_SMC, 0x1, &ixGDS_DEBUG_REG1[0], sizeof(ixGDS_DEBUG_REG1)/sizeof(ixGDS_DEBUG_REG1[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG1", REG_SMC, 0x1, &ixWD_DEBUG_REG1[0], sizeof(ixWD_DEBUG_REG1)/sizeof(ixWD_DEBUG_REG1[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG16", REG_SMC, 0x10, &ixCLIPPER_DEBUG_REG16[0], sizeof(ixCLIPPER_DEBUG_REG16)/sizeof(ixCLIPPER_DEBUG_REG16[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT0_3", REG_SMC, 0x10, &ixDIDT_SQ_WEIGHT0_3[0], sizeof(ixDIDT_SQ_WEIGHT0_3)/sizeof(ixDIDT_SQ_WEIGHT0_3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG16", REG_SMC, 0x10, &ixVGT_DEBUG_REG16[0], sizeof(ixVGT_DEBUG_REG16)/sizeof(ixVGT_DEBUG_REG16[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG17", REG_SMC, 0x11, &ixCLIPPER_DEBUG_REG17[0], sizeof(ixCLIPPER_DEBUG_REG17)/sizeof(ixCLIPPER_DEBUG_REG17[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT4_7", REG_SMC, 0x11, &ixDIDT_SQ_WEIGHT4_7[0], sizeof(ixDIDT_SQ_WEIGHT4_7)/sizeof(ixDIDT_SQ_WEIGHT4_7[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG17", REG_SMC, 0x11, &ixVGT_DEBUG_REG17[0], sizeof(ixVGT_DEBUG_REG17)/sizeof(ixVGT_DEBUG_REG17[0]), 0, 0 },
+	{ "ixSQ_WAVE_MODE", REG_SMC, 0x11, &ixSQ_WAVE_MODE[0], sizeof(ixSQ_WAVE_MODE)/sizeof(ixSQ_WAVE_MODE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG18", REG_SMC, 0x12, &ixCLIPPER_DEBUG_REG18[0], sizeof(ixCLIPPER_DEBUG_REG18)/sizeof(ixCLIPPER_DEBUG_REG18[0]), 0, 0 },
+	{ "ixDIDT_SQ_WEIGHT8_11", REG_SMC, 0x12, &ixDIDT_SQ_WEIGHT8_11[0], sizeof(ixDIDT_SQ_WEIGHT8_11)/sizeof(ixDIDT_SQ_WEIGHT8_11[0]), 0, 0 },
+	{ "ixSQ_WAVE_STATUS", REG_SMC, 0x12, &ixSQ_WAVE_STATUS[0], sizeof(ixSQ_WAVE_STATUS)/sizeof(ixSQ_WAVE_STATUS[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG19", REG_SMC, 0x13, &ixCLIPPER_DEBUG_REG19[0], sizeof(ixCLIPPER_DEBUG_REG19)/sizeof(ixCLIPPER_DEBUG_REG19[0]), 0, 0 },
+	{ "ixSQ_WAVE_TRAPSTS", REG_SMC, 0x13, &ixSQ_WAVE_TRAPSTS[0], sizeof(ixSQ_WAVE_TRAPSTS)/sizeof(ixSQ_WAVE_TRAPSTS[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG0", REG_SMC, 0x14, &ixSXIFCCG_DEBUG_REG0[0], sizeof(ixSXIFCCG_DEBUG_REG0)/sizeof(ixSXIFCCG_DEBUG_REG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG20", REG_SMC, 0x14, &ixVGT_DEBUG_REG20[0], sizeof(ixVGT_DEBUG_REG20)/sizeof(ixVGT_DEBUG_REG20[0]), 0, 0 },
+	{ "ixSQ_WAVE_HW_ID", REG_SMC, 0x14, &ixSQ_WAVE_HW_ID[0], sizeof(ixSQ_WAVE_HW_ID)/sizeof(ixSQ_WAVE_HW_ID[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG1", REG_SMC, 0x15, &ixSXIFCCG_DEBUG_REG1[0], sizeof(ixSXIFCCG_DEBUG_REG1)/sizeof(ixSXIFCCG_DEBUG_REG1[0]), 0, 0 },
+	{ "ixSQ_WAVE_GPR_ALLOC", REG_SMC, 0x15, &ixSQ_WAVE_GPR_ALLOC[0], sizeof(ixSQ_WAVE_GPR_ALLOC)/sizeof(ixSQ_WAVE_GPR_ALLOC[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG21", REG_SMC, 0x15, &ixVGT_DEBUG_REG21[0], sizeof(ixVGT_DEBUG_REG21)/sizeof(ixVGT_DEBUG_REG21[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG2", REG_SMC, 0x16, &ixSXIFCCG_DEBUG_REG2[0], sizeof(ixSXIFCCG_DEBUG_REG2)/sizeof(ixSXIFCCG_DEBUG_REG2[0]), 0, 0 },
+	{ "ixSQ_WAVE_LDS_ALLOC", REG_SMC, 0x16, &ixSQ_WAVE_LDS_ALLOC[0], sizeof(ixSQ_WAVE_LDS_ALLOC)/sizeof(ixSQ_WAVE_LDS_ALLOC[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG22", REG_SMC, 0x16, &ixVGT_DEBUG_REG22[0], sizeof(ixVGT_DEBUG_REG22)/sizeof(ixVGT_DEBUG_REG22[0]), 0, 0 },
+	{ "ixSXIFCCG_DEBUG_REG3", REG_SMC, 0x17, &ixSXIFCCG_DEBUG_REG3[0], sizeof(ixSXIFCCG_DEBUG_REG3)/sizeof(ixSXIFCCG_DEBUG_REG3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG23", REG_SMC, 0x17, &ixVGT_DEBUG_REG23[0], sizeof(ixVGT_DEBUG_REG23)/sizeof(ixVGT_DEBUG_REG23[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_STS", REG_SMC, 0x17, &ixSQ_WAVE_IB_STS[0], sizeof(ixSQ_WAVE_IB_STS)/sizeof(ixSQ_WAVE_IB_STS[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG0", REG_SMC, 0x18, &ixSETUP_DEBUG_REG0[0], sizeof(ixSETUP_DEBUG_REG0)/sizeof(ixSETUP_DEBUG_REG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG24", REG_SMC, 0x18, &ixVGT_DEBUG_REG24[0], sizeof(ixVGT_DEBUG_REG24)/sizeof(ixVGT_DEBUG_REG24[0]), 0, 0 },
+	{ "ixSQ_WAVE_PC_LO", REG_SMC, 0x18, &ixSQ_WAVE_PC_LO[0], sizeof(ixSQ_WAVE_PC_LO)/sizeof(ixSQ_WAVE_PC_LO[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG1", REG_SMC, 0x19, &ixSETUP_DEBUG_REG1[0], sizeof(ixSETUP_DEBUG_REG1)/sizeof(ixSETUP_DEBUG_REG1[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG25", REG_SMC, 0x19, &ixVGT_DEBUG_REG25[0], sizeof(ixVGT_DEBUG_REG25)/sizeof(ixVGT_DEBUG_REG25[0]), 0, 0 },
+	{ "ixSQ_WAVE_PC_HI", REG_SMC, 0x19, &ixSQ_WAVE_PC_HI[0], sizeof(ixSQ_WAVE_PC_HI)/sizeof(ixSQ_WAVE_PC_HI[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG2", REG_SMC, 0x1a, &ixSETUP_DEBUG_REG2[0], sizeof(ixSETUP_DEBUG_REG2)/sizeof(ixSETUP_DEBUG_REG2[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG3", REG_SMC, 0x1b, &ixSETUP_DEBUG_REG3[0], sizeof(ixSETUP_DEBUG_REG3)/sizeof(ixSETUP_DEBUG_REG3[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG27", REG_SMC, 0x1b, &ixVGT_DEBUG_REG27[0], sizeof(ixVGT_DEBUG_REG27)/sizeof(ixVGT_DEBUG_REG27[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG4", REG_SMC, 0x1c, &ixSETUP_DEBUG_REG4[0], sizeof(ixSETUP_DEBUG_REG4)/sizeof(ixSETUP_DEBUG_REG4[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_DBG0", REG_SMC, 0x1c, &ixSQ_WAVE_IB_DBG0[0], sizeof(ixSQ_WAVE_IB_DBG0)/sizeof(ixSQ_WAVE_IB_DBG0[0]), 0, 0 },
+	{ "ixSETUP_DEBUG_REG5", REG_SMC, 0x1d, &ixSETUP_DEBUG_REG5[0], sizeof(ixSETUP_DEBUG_REG5)/sizeof(ixSETUP_DEBUG_REG5[0]), 0, 0 },
+	{ "ixSQ_WAVE_IB_DBG1", REG_SMC, 0x1d, &ixSQ_WAVE_IB_DBG1[0], sizeof(ixSQ_WAVE_IB_DBG1)/sizeof(ixSQ_WAVE_IB_DBG1[0]), 0, 0 },
+	{ "mmCSPRIV_THREAD_TRACE_TG0", REG_MMIO, 0x1e, &mmCSPRIV_THREAD_TRACE_TG0[0], sizeof(mmCSPRIV_THREAD_TRACE_TG0)/sizeof(mmCSPRIV_THREAD_TRACE_TG0[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG2", REG_SMC, 0x1e, &ixVGT_DEBUG_REG2[0], sizeof(ixVGT_DEBUG_REG2)/sizeof(ixVGT_DEBUG_REG2[0]), 0, 0 },
+	{ "mmCSPRIV_THREAD_TRACE_EVENT", REG_MMIO, 0x1f, &mmCSPRIV_THREAD_TRACE_EVENT[0], sizeof(mmCSPRIV_THREAD_TRACE_EVENT)/sizeof(mmCSPRIV_THREAD_TRACE_EVENT[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG3", REG_SMC, 0x1f, &ixVGT_DEBUG_REG3[0], sizeof(ixVGT_DEBUG_REG3)/sizeof(ixVGT_DEBUG_REG3[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG02", REG_SMC, 0x2, &ixCLIPPER_DEBUG_REG02[0], sizeof(ixCLIPPER_DEBUG_REG02)/sizeof(ixCLIPPER_DEBUG_REG02[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG2", REG_SMC, 0x2, &ixGDS_DEBUG_REG2[0], sizeof(ixGDS_DEBUG_REG2)/sizeof(ixGDS_DEBUG_REG2[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG2", REG_SMC, 0x2, &ixWD_DEBUG_REG2[0], sizeof(ixWD_DEBUG_REG2)/sizeof(ixWD_DEBUG_REG2[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG4", REG_SMC, 0x20, &ixVGT_DEBUG_REG4[0], sizeof(ixVGT_DEBUG_REG4)/sizeof(ixVGT_DEBUG_REG4[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL0", REG_SMC, 0x20, &ixDIDT_DB_CTRL0[0], sizeof(ixDIDT_DB_CTRL0)/sizeof(ixDIDT_DB_CTRL0[0]), 0, 0 },
+	{ "mmGRBM_CNTL", REG_MMIO, 0x2000, &mmGRBM_CNTL[0], sizeof(mmGRBM_CNTL)/sizeof(mmGRBM_CNTL[0]), 0, 0 },
+	{ "mmGRBM_SKEW_CNTL", REG_MMIO, 0x2001, &mmGRBM_SKEW_CNTL[0], sizeof(mmGRBM_SKEW_CNTL)/sizeof(mmGRBM_SKEW_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS2", REG_MMIO, 0x2002, &mmGRBM_STATUS2[0], sizeof(mmGRBM_STATUS2)/sizeof(mmGRBM_STATUS2[0]), 0, 0 },
+	{ "mmGRBM_PWR_CNTL", REG_MMIO, 0x2003, &mmGRBM_PWR_CNTL[0], sizeof(mmGRBM_PWR_CNTL)/sizeof(mmGRBM_PWR_CNTL[0]), 0, 0 },
+	{ "mmGRBM_STATUS", REG_MMIO, 0x2004, &mmGRBM_STATUS[0], sizeof(mmGRBM_STATUS)/sizeof(mmGRBM_STATUS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE0", REG_MMIO, 0x2005, &mmGRBM_STATUS_SE0[0], sizeof(mmGRBM_STATUS_SE0)/sizeof(mmGRBM_STATUS_SE0[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE1", REG_MMIO, 0x2006, &mmGRBM_STATUS_SE1[0], sizeof(mmGRBM_STATUS_SE1)/sizeof(mmGRBM_STATUS_SE1[0]), 0, 0 },
+	{ "mmGRBM_SOFT_RESET", REG_MMIO, 0x2008, &mmGRBM_SOFT_RESET[0], sizeof(mmGRBM_SOFT_RESET)/sizeof(mmGRBM_SOFT_RESET[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_CNTL", REG_MMIO, 0x2009, &mmGRBM_DEBUG_CNTL[0], sizeof(mmGRBM_DEBUG_CNTL)/sizeof(mmGRBM_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_DATA", REG_MMIO, 0x200a, &mmGRBM_DEBUG_DATA[0], sizeof(mmGRBM_DEBUG_DATA)/sizeof(mmGRBM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_CGTT_CLK_CNTL", REG_MMIO, 0x200b, &mmGRBM_CGTT_CLK_CNTL[0], sizeof(mmGRBM_CGTT_CLK_CNTL)/sizeof(mmGRBM_CGTT_CLK_CNTL[0]), 0, 0 },
+	{ "mmGRBM_GFX_CLKEN_CNTL", REG_MMIO, 0x200c, &mmGRBM_GFX_CLKEN_CNTL[0], sizeof(mmGRBM_GFX_CLKEN_CNTL)/sizeof(mmGRBM_GFX_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmGRBM_WAIT_IDLE_CLOCKS", REG_MMIO, 0x200d, &mmGRBM_WAIT_IDLE_CLOCKS[0], sizeof(mmGRBM_WAIT_IDLE_CLOCKS)/sizeof(mmGRBM_WAIT_IDLE_CLOCKS[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE2", REG_MMIO, 0x200e, &mmGRBM_STATUS_SE2[0], sizeof(mmGRBM_STATUS_SE2)/sizeof(mmGRBM_STATUS_SE2[0]), 0, 0 },
+	{ "mmGRBM_STATUS_SE3", REG_MMIO, 0x200f, &mmGRBM_STATUS_SE3[0], sizeof(mmGRBM_STATUS_SE3)/sizeof(mmGRBM_STATUS_SE3[0]), 0, 0 },
+	{ "mmGRBM_DEBUG", REG_MMIO, 0x2014, &mmGRBM_DEBUG[0], sizeof(mmGRBM_DEBUG)/sizeof(mmGRBM_DEBUG[0]), 0, 0 },
+	{ "mmGRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x2015, &mmGRBM_DEBUG_SNAPSHOT[0], sizeof(mmGRBM_DEBUG_SNAPSHOT)/sizeof(mmGRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR", REG_MMIO, 0x2016, &mmGRBM_READ_ERROR[0], sizeof(mmGRBM_READ_ERROR)/sizeof(mmGRBM_READ_ERROR[0]), 0, 0 },
+	{ "mmGRBM_READ_ERROR2", REG_MMIO, 0x2017, &mmGRBM_READ_ERROR2[0], sizeof(mmGRBM_READ_ERROR2)/sizeof(mmGRBM_READ_ERROR2[0]), 0, 0 },
+	{ "mmGRBM_INT_CNTL", REG_MMIO, 0x2018, &mmGRBM_INT_CNTL[0], sizeof(mmGRBM_INT_CNTL)/sizeof(mmGRBM_INT_CNTL[0]), 0, 0 },
+	{ "mmGRBM_TRAP_OP", REG_MMIO, 0x2019, &mmGRBM_TRAP_OP[0], sizeof(mmGRBM_TRAP_OP)/sizeof(mmGRBM_TRAP_OP[0]), 0, 0 },
+	{ "mmGRBM_TRAP_ADDR", REG_MMIO, 0x201a, &mmGRBM_TRAP_ADDR[0], sizeof(mmGRBM_TRAP_ADDR)/sizeof(mmGRBM_TRAP_ADDR[0]), 0, 0 },
+	{ "mmGRBM_TRAP_ADDR_MSK", REG_MMIO, 0x201b, &mmGRBM_TRAP_ADDR_MSK[0], sizeof(mmGRBM_TRAP_ADDR_MSK)/sizeof(mmGRBM_TRAP_ADDR_MSK[0]), 0, 0 },
+	{ "mmGRBM_TRAP_WD", REG_MMIO, 0x201c, &mmGRBM_TRAP_WD[0], sizeof(mmGRBM_TRAP_WD)/sizeof(mmGRBM_TRAP_WD[0]), 0, 0 },
+	{ "mmGRBM_TRAP_WD_MSK", REG_MMIO, 0x201d, &mmGRBM_TRAP_WD_MSK[0], sizeof(mmGRBM_TRAP_WD_MSK)/sizeof(mmGRBM_TRAP_WD_MSK[0]), 0, 0 },
+	{ "mmGRBM_DSM_BYPASS", REG_MMIO, 0x201e, &mmGRBM_DSM_BYPASS[0], sizeof(mmGRBM_DSM_BYPASS)/sizeof(mmGRBM_DSM_BYPASS[0]), 0, 0 },
+	{ "mmGRBM_WRITE_ERROR", REG_MMIO, 0x201f, &mmGRBM_WRITE_ERROR[0], sizeof(mmGRBM_WRITE_ERROR)/sizeof(mmGRBM_WRITE_ERROR[0]), 0, 0 },
+	{ "mmDEBUG_INDEX", REG_MMIO, 0x203c, &mmDEBUG_INDEX[0], sizeof(mmDEBUG_INDEX)/sizeof(mmDEBUG_INDEX[0]), 0, 0 },
+	{ "mmDEBUG_DATA", REG_MMIO, 0x203d, &mmDEBUG_DATA[0], sizeof(mmDEBUG_DATA)/sizeof(mmDEBUG_DATA[0]), 0, 0 },
+	{ "mmGRBM_NOWHERE", REG_MMIO, 0x203f, &mmGRBM_NOWHERE[0], sizeof(mmGRBM_NOWHERE)/sizeof(mmGRBM_NOWHERE[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG0", REG_MMIO, 0x2040, &mmGRBM_SCRATCH_REG0[0], sizeof(mmGRBM_SCRATCH_REG0)/sizeof(mmGRBM_SCRATCH_REG0[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG1", REG_MMIO, 0x2041, &mmGRBM_SCRATCH_REG1[0], sizeof(mmGRBM_SCRATCH_REG1)/sizeof(mmGRBM_SCRATCH_REG1[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG2", REG_MMIO, 0x2042, &mmGRBM_SCRATCH_REG2[0], sizeof(mmGRBM_SCRATCH_REG2)/sizeof(mmGRBM_SCRATCH_REG2[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG3", REG_MMIO, 0x2043, &mmGRBM_SCRATCH_REG3[0], sizeof(mmGRBM_SCRATCH_REG3)/sizeof(mmGRBM_SCRATCH_REG3[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG4", REG_MMIO, 0x2044, &mmGRBM_SCRATCH_REG4[0], sizeof(mmGRBM_SCRATCH_REG4)/sizeof(mmGRBM_SCRATCH_REG4[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG5", REG_MMIO, 0x2045, &mmGRBM_SCRATCH_REG5[0], sizeof(mmGRBM_SCRATCH_REG5)/sizeof(mmGRBM_SCRATCH_REG5[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG6", REG_MMIO, 0x2046, &mmGRBM_SCRATCH_REG6[0], sizeof(mmGRBM_SCRATCH_REG6)/sizeof(mmGRBM_SCRATCH_REG6[0]), 0, 0 },
+	{ "mmGRBM_SCRATCH_REG7", REG_MMIO, 0x2047, &mmGRBM_SCRATCH_REG7[0], sizeof(mmGRBM_SCRATCH_REG7)/sizeof(mmGRBM_SCRATCH_REG7[0]), 0, 0 },
+	{ "mmCP_CPC_STATUS", REG_MMIO, 0x2084, &mmCP_CPC_STATUS[0], sizeof(mmCP_CPC_STATUS)/sizeof(mmCP_CPC_STATUS[0]), 0, 0 },
+	{ "mmCP_CPC_BUSY_STAT", REG_MMIO, 0x2085, &mmCP_CPC_BUSY_STAT[0], sizeof(mmCP_CPC_BUSY_STAT)/sizeof(mmCP_CPC_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_CPC_STALLED_STAT1", REG_MMIO, 0x2086, &mmCP_CPC_STALLED_STAT1[0], sizeof(mmCP_CPC_STALLED_STAT1)/sizeof(mmCP_CPC_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_CPF_STATUS", REG_MMIO, 0x2087, &mmCP_CPF_STATUS[0], sizeof(mmCP_CPF_STATUS)/sizeof(mmCP_CPF_STATUS[0]), 0, 0 },
+	{ "mmCP_CPF_BUSY_STAT", REG_MMIO, 0x2088, &mmCP_CPF_BUSY_STAT[0], sizeof(mmCP_CPF_BUSY_STAT)/sizeof(mmCP_CPF_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_CPF_STALLED_STAT1", REG_MMIO, 0x2089, &mmCP_CPF_STALLED_STAT1[0], sizeof(mmCP_CPF_STALLED_STAT1)/sizeof(mmCP_CPF_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_CPC_GRBM_FREE_COUNT", REG_MMIO, 0x208b, &mmCP_CPC_GRBM_FREE_COUNT[0], sizeof(mmCP_CPC_GRBM_FREE_COUNT)/sizeof(mmCP_CPC_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_MEC_CNTL", REG_MMIO, 0x208d, &mmCP_MEC_CNTL[0], sizeof(mmCP_MEC_CNTL)/sizeof(mmCP_MEC_CNTL[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_HEADER_DUMP", REG_MMIO, 0x208e, &mmCP_MEC_ME1_HEADER_DUMP[0], sizeof(mmCP_MEC_ME1_HEADER_DUMP)/sizeof(mmCP_MEC_ME1_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_HEADER_DUMP", REG_MMIO, 0x208f, &mmCP_MEC_ME2_HEADER_DUMP[0], sizeof(mmCP_MEC_ME2_HEADER_DUMP)/sizeof(mmCP_MEC_ME2_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_CPC_SCRATCH_INDEX", REG_MMIO, 0x2090, &mmCP_CPC_SCRATCH_INDEX[0], sizeof(mmCP_CPC_SCRATCH_INDEX)/sizeof(mmCP_CPC_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_CPC_SCRATCH_DATA", REG_MMIO, 0x2091, &mmCP_CPC_SCRATCH_DATA[0], sizeof(mmCP_CPC_SCRATCH_DATA)/sizeof(mmCP_CPC_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_CPC_HALT_HYST_COUNT", REG_MMIO, 0x20a7, &mmCP_CPC_HALT_HYST_COUNT[0], sizeof(mmCP_CPC_HALT_HYST_COUNT)/sizeof(mmCP_CPC_HALT_HYST_COUNT[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL0", REG_MMIO, 0x20ad, &mmCP_PRT_LOD_STATS_CNTL0[0], sizeof(mmCP_PRT_LOD_STATS_CNTL0)/sizeof(mmCP_PRT_LOD_STATS_CNTL0[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL1", REG_MMIO, 0x20ae, &mmCP_PRT_LOD_STATS_CNTL1[0], sizeof(mmCP_PRT_LOD_STATS_CNTL1)/sizeof(mmCP_PRT_LOD_STATS_CNTL1[0]), 0, 0 },
+	{ "mmCP_PRT_LOD_STATS_CNTL2", REG_MMIO, 0x20af, &mmCP_PRT_LOD_STATS_CNTL2[0], sizeof(mmCP_PRT_LOD_STATS_CNTL2)/sizeof(mmCP_PRT_LOD_STATS_CNTL2[0]), 0, 0 },
+	{ "ixSQ_INTERRUPT_WORD_AUTO", REG_SMC, 0x20c0, &ixSQ_INTERRUPT_WORD_AUTO[0], sizeof(ixSQ_INTERRUPT_WORD_AUTO)/sizeof(ixSQ_INTERRUPT_WORD_AUTO[0]), 0, 0 },
+	{ "ixSQ_INTERRUPT_WORD_CMN", REG_SMC, 0x20c0, &ixSQ_INTERRUPT_WORD_CMN[0], sizeof(ixSQ_INTERRUPT_WORD_CMN)/sizeof(ixSQ_INTERRUPT_WORD_CMN[0]), 0, 0 },
+	{ "mmCP_CE_COMPARE_COUNT", REG_MMIO, 0x20c0, &mmCP_CE_COMPARE_COUNT[0], sizeof(mmCP_CE_COMPARE_COUNT)/sizeof(mmCP_CE_COMPARE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_DE_COUNT", REG_MMIO, 0x20c1, &mmCP_CE_DE_COUNT[0], sizeof(mmCP_CE_DE_COUNT)/sizeof(mmCP_CE_DE_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_CE_COUNT", REG_MMIO, 0x20c2, &mmCP_DE_CE_COUNT[0], sizeof(mmCP_DE_CE_COUNT)/sizeof(mmCP_DE_CE_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_LAST_INVAL_COUNT", REG_MMIO, 0x20c3, &mmCP_DE_LAST_INVAL_COUNT[0], sizeof(mmCP_DE_LAST_INVAL_COUNT)/sizeof(mmCP_DE_LAST_INVAL_COUNT[0]), 0, 0 },
+	{ "mmCP_DE_DE_COUNT", REG_MMIO, 0x20c4, &mmCP_DE_DE_COUNT[0], sizeof(mmCP_DE_DE_COUNT)/sizeof(mmCP_DE_DE_COUNT[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG5", REG_SMC, 0x21, &ixVGT_DEBUG_REG5[0], sizeof(ixVGT_DEBUG_REG5)/sizeof(ixVGT_DEBUG_REG5[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL1", REG_SMC, 0x21, &ixDIDT_DB_CTRL1[0], sizeof(ixDIDT_DB_CTRL1)/sizeof(ixDIDT_DB_CTRL1[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT3", REG_MMIO, 0x219c, &mmCP_STALLED_STAT3[0], sizeof(mmCP_STALLED_STAT3)/sizeof(mmCP_STALLED_STAT3[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT1", REG_MMIO, 0x219d, &mmCP_STALLED_STAT1[0], sizeof(mmCP_STALLED_STAT1)/sizeof(mmCP_STALLED_STAT1[0]), 0, 0 },
+	{ "mmCP_STALLED_STAT2", REG_MMIO, 0x219e, &mmCP_STALLED_STAT2[0], sizeof(mmCP_STALLED_STAT2)/sizeof(mmCP_STALLED_STAT2[0]), 0, 0 },
+	{ "mmCP_BUSY_STAT", REG_MMIO, 0x219f, &mmCP_BUSY_STAT[0], sizeof(mmCP_BUSY_STAT)/sizeof(mmCP_BUSY_STAT[0]), 0, 0 },
+	{ "mmCP_STAT", REG_MMIO, 0x21a0, &mmCP_STAT[0], sizeof(mmCP_STAT)/sizeof(mmCP_STAT[0]), 0, 0 },
+	{ "mmCP_ME_HEADER_DUMP", REG_MMIO, 0x21a1, &mmCP_ME_HEADER_DUMP[0], sizeof(mmCP_ME_HEADER_DUMP)/sizeof(mmCP_ME_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_PFP_HEADER_DUMP", REG_MMIO, 0x21a2, &mmCP_PFP_HEADER_DUMP[0], sizeof(mmCP_PFP_HEADER_DUMP)/sizeof(mmCP_PFP_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_GRBM_FREE_COUNT", REG_MMIO, 0x21a3, &mmCP_GRBM_FREE_COUNT[0], sizeof(mmCP_GRBM_FREE_COUNT)/sizeof(mmCP_GRBM_FREE_COUNT[0]), 0, 0 },
+	{ "mmCP_CE_HEADER_DUMP", REG_MMIO, 0x21a4, &mmCP_CE_HEADER_DUMP[0], sizeof(mmCP_CE_HEADER_DUMP)/sizeof(mmCP_CE_HEADER_DUMP[0]), 0, 0 },
+	{ "mmCP_CSF_STAT", REG_MMIO, 0x21b4, &mmCP_CSF_STAT[0], sizeof(mmCP_CSF_STAT)/sizeof(mmCP_CSF_STAT[0]), 0, 0 },
+	{ "mmCP_CSF_CNTL", REG_MMIO, 0x21b5, &mmCP_CSF_CNTL[0], sizeof(mmCP_CSF_CNTL)/sizeof(mmCP_CSF_CNTL[0]), 0, 0 },
+	{ "mmCP_ME_CNTL", REG_MMIO, 0x21b6, &mmCP_ME_CNTL[0], sizeof(mmCP_ME_CNTL)/sizeof(mmCP_ME_CNTL[0]), 0, 0 },
+	{ "mmCP_CNTX_STAT", REG_MMIO, 0x21b8, &mmCP_CNTX_STAT[0], sizeof(mmCP_CNTX_STAT)/sizeof(mmCP_CNTX_STAT[0]), 0, 0 },
+	{ "mmCP_ME_PREEMPTION", REG_MMIO, 0x21b9, &mmCP_ME_PREEMPTION[0], sizeof(mmCP_ME_PREEMPTION)/sizeof(mmCP_ME_PREEMPTION[0]), 0, 0 },
+	{ "mmCP_ROQ_THRESHOLDS", REG_MMIO, 0x21bc, &mmCP_ROQ_THRESHOLDS[0], sizeof(mmCP_ROQ_THRESHOLDS)/sizeof(mmCP_ROQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_STQ_THRESHOLD", REG_MMIO, 0x21bd, &mmCP_MEQ_STQ_THRESHOLD[0], sizeof(mmCP_MEQ_STQ_THRESHOLD)/sizeof(mmCP_MEQ_STQ_THRESHOLD[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR", REG_MMIO, 0x21be, &mmCP_RB2_RPTR[0], sizeof(mmCP_RB2_RPTR)/sizeof(mmCP_RB2_RPTR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR", REG_MMIO, 0x21bf, &mmCP_RB1_RPTR[0], sizeof(mmCP_RB1_RPTR)/sizeof(mmCP_RB1_RPTR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR", REG_MMIO, 0x21c0, &mmCP_RB0_RPTR[0], sizeof(mmCP_RB0_RPTR)/sizeof(mmCP_RB0_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_RPTR", REG_MMIO, 0x21c0, &mmCP_RB_RPTR[0], sizeof(mmCP_RB_RPTR)/sizeof(mmCP_RB_RPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_DELAY", REG_MMIO, 0x21c1, &mmCP_RB_WPTR_DELAY[0], sizeof(mmCP_RB_WPTR_DELAY)/sizeof(mmCP_RB_WPTR_DELAY[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_CNTL", REG_MMIO, 0x21c2, &mmCP_RB_WPTR_POLL_CNTL[0], sizeof(mmCP_RB_WPTR_POLL_CNTL)/sizeof(mmCP_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_ROQ1_THRESHOLDS", REG_MMIO, 0x21d5, &mmCP_ROQ1_THRESHOLDS[0], sizeof(mmCP_ROQ1_THRESHOLDS)/sizeof(mmCP_ROQ1_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ2_THRESHOLDS", REG_MMIO, 0x21d6, &mmCP_ROQ2_THRESHOLDS[0], sizeof(mmCP_ROQ2_THRESHOLDS)/sizeof(mmCP_ROQ2_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_STQ_THRESHOLDS", REG_MMIO, 0x21d7, &mmCP_STQ_THRESHOLDS[0], sizeof(mmCP_STQ_THRESHOLDS)/sizeof(mmCP_STQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_QUEUE_THRESHOLDS", REG_MMIO, 0x21d8, &mmCP_QUEUE_THRESHOLDS[0], sizeof(mmCP_QUEUE_THRESHOLDS)/sizeof(mmCP_QUEUE_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_MEQ_THRESHOLDS", REG_MMIO, 0x21d9, &mmCP_MEQ_THRESHOLDS[0], sizeof(mmCP_MEQ_THRESHOLDS)/sizeof(mmCP_MEQ_THRESHOLDS[0]), 0, 0 },
+	{ "mmCP_ROQ_AVAIL", REG_MMIO, 0x21da, &mmCP_ROQ_AVAIL[0], sizeof(mmCP_ROQ_AVAIL)/sizeof(mmCP_ROQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_STQ_AVAIL", REG_MMIO, 0x21db, &mmCP_STQ_AVAIL[0], sizeof(mmCP_STQ_AVAIL)/sizeof(mmCP_STQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_ROQ2_AVAIL", REG_MMIO, 0x21dc, &mmCP_ROQ2_AVAIL[0], sizeof(mmCP_ROQ2_AVAIL)/sizeof(mmCP_ROQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_MEQ_AVAIL", REG_MMIO, 0x21dd, &mmCP_MEQ_AVAIL[0], sizeof(mmCP_MEQ_AVAIL)/sizeof(mmCP_MEQ_AVAIL[0]), 0, 0 },
+	{ "mmCP_CMD_INDEX", REG_MMIO, 0x21de, &mmCP_CMD_INDEX[0], sizeof(mmCP_CMD_INDEX)/sizeof(mmCP_CMD_INDEX[0]), 0, 0 },
+	{ "mmCP_CMD_DATA", REG_MMIO, 0x21df, &mmCP_CMD_DATA[0], sizeof(mmCP_CMD_DATA)/sizeof(mmCP_CMD_DATA[0]), 0, 0 },
+	{ "mmCP_ROQ_RB_STAT", REG_MMIO, 0x21e0, &mmCP_ROQ_RB_STAT[0], sizeof(mmCP_ROQ_RB_STAT)/sizeof(mmCP_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB1_STAT", REG_MMIO, 0x21e1, &mmCP_ROQ_IB1_STAT[0], sizeof(mmCP_ROQ_IB1_STAT)/sizeof(mmCP_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_ROQ_IB2_STAT", REG_MMIO, 0x21e2, &mmCP_ROQ_IB2_STAT[0], sizeof(mmCP_ROQ_IB2_STAT)/sizeof(mmCP_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_STAT", REG_MMIO, 0x21e3, &mmCP_STQ_STAT[0], sizeof(mmCP_STQ_STAT)/sizeof(mmCP_STQ_STAT[0]), 0, 0 },
+	{ "mmCP_STQ_WR_STAT", REG_MMIO, 0x21e4, &mmCP_STQ_WR_STAT[0], sizeof(mmCP_STQ_WR_STAT)/sizeof(mmCP_STQ_WR_STAT[0]), 0, 0 },
+	{ "mmCP_MEQ_STAT", REG_MMIO, 0x21e5, &mmCP_MEQ_STAT[0], sizeof(mmCP_MEQ_STAT)/sizeof(mmCP_MEQ_STAT[0]), 0, 0 },
+	{ "mmCP_CEQ1_AVAIL", REG_MMIO, 0x21e6, &mmCP_CEQ1_AVAIL[0], sizeof(mmCP_CEQ1_AVAIL)/sizeof(mmCP_CEQ1_AVAIL[0]), 0, 0 },
+	{ "mmCP_CEQ2_AVAIL", REG_MMIO, 0x21e7, &mmCP_CEQ2_AVAIL[0], sizeof(mmCP_CEQ2_AVAIL)/sizeof(mmCP_CEQ2_AVAIL[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_RB_STAT", REG_MMIO, 0x21e8, &mmCP_CE_ROQ_RB_STAT[0], sizeof(mmCP_CE_ROQ_RB_STAT)/sizeof(mmCP_CE_ROQ_RB_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB1_STAT", REG_MMIO, 0x21e9, &mmCP_CE_ROQ_IB1_STAT[0], sizeof(mmCP_CE_ROQ_IB1_STAT)/sizeof(mmCP_CE_ROQ_IB1_STAT[0]), 0, 0 },
+	{ "mmCP_CE_ROQ_IB2_STAT", REG_MMIO, 0x21ea, &mmCP_CE_ROQ_IB2_STAT[0], sizeof(mmCP_CE_ROQ_IB2_STAT)/sizeof(mmCP_CE_ROQ_IB2_STAT[0]), 0, 0 },
+	{ "mmCP_INT_STAT_DEBUG", REG_MMIO, 0x21f7, &mmCP_INT_STAT_DEBUG[0], sizeof(mmCP_INT_STAT_DEBUG)/sizeof(mmCP_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG6", REG_SMC, 0x22, &ixVGT_DEBUG_REG6[0], sizeof(ixVGT_DEBUG_REG6)/sizeof(ixVGT_DEBUG_REG6[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL2", REG_SMC, 0x22, &ixDIDT_DB_CTRL2[0], sizeof(ixDIDT_DB_CTRL2)/sizeof(ixDIDT_DB_CTRL2[0]), 0, 0 },
+	{ "mmVGT_VTX_VECT_EJECT_REG", REG_MMIO, 0x222c, &mmVGT_VTX_VECT_EJECT_REG[0], sizeof(mmVGT_VTX_VECT_EJECT_REG)/sizeof(mmVGT_VTX_VECT_EJECT_REG[0]), 0, 0 },
+	{ "mmVGT_DMA_DATA_FIFO_DEPTH", REG_MMIO, 0x222d, &mmVGT_DMA_DATA_FIFO_DEPTH[0], sizeof(mmVGT_DMA_DATA_FIFO_DEPTH)/sizeof(mmVGT_DMA_DATA_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DMA_REQ_FIFO_DEPTH", REG_MMIO, 0x222e, &mmVGT_DMA_REQ_FIFO_DEPTH[0], sizeof(mmVGT_DMA_REQ_FIFO_DEPTH)/sizeof(mmVGT_DMA_REQ_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_DRAW_INIT_FIFO_DEPTH", REG_MMIO, 0x222f, &mmVGT_DRAW_INIT_FIFO_DEPTH[0], sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH)/sizeof(mmVGT_DRAW_INIT_FIFO_DEPTH[0]), 0, 0 },
+	{ "mmVGT_LAST_COPY_STATE", REG_MMIO, 0x2230, &mmVGT_LAST_COPY_STATE[0], sizeof(mmVGT_LAST_COPY_STATE)/sizeof(mmVGT_LAST_COPY_STATE[0]), 0, 0 },
+	{ "mmVGT_CACHE_INVALIDATION", REG_MMIO, 0x2231, &mmVGT_CACHE_INVALIDATION[0], sizeof(mmVGT_CACHE_INVALIDATION)/sizeof(mmVGT_CACHE_INVALIDATION[0]), 0, 0 },
+	{ "mmVGT_RESET_DEBUG", REG_MMIO, 0x2232, &mmVGT_RESET_DEBUG[0], sizeof(mmVGT_RESET_DEBUG)/sizeof(mmVGT_RESET_DEBUG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DELAY", REG_MMIO, 0x2233, &mmVGT_STRMOUT_DELAY[0], sizeof(mmVGT_STRMOUT_DELAY)/sizeof(mmVGT_STRMOUT_DELAY[0]), 0, 0 },
+	{ "mmVGT_FIFO_DEPTHS", REG_MMIO, 0x2234, &mmVGT_FIFO_DEPTHS[0], sizeof(mmVGT_FIFO_DEPTHS)/sizeof(mmVGT_FIFO_DEPTHS[0]), 0, 0 },
+	{ "mmVGT_GS_VERTEX_REUSE", REG_MMIO, 0x2235, &mmVGT_GS_VERTEX_REUSE[0], sizeof(mmVGT_GS_VERTEX_REUSE)/sizeof(mmVGT_GS_VERTEX_REUSE[0]), 0, 0 },
+	{ "mmVGT_MC_LAT_CNTL", REG_MMIO, 0x2236, &mmVGT_MC_LAT_CNTL[0], sizeof(mmVGT_MC_LAT_CNTL)/sizeof(mmVGT_MC_LAT_CNTL[0]), 0, 0 },
+	{ "mmIA_CNTL_STATUS", REG_MMIO, 0x2237, &mmIA_CNTL_STATUS[0], sizeof(mmIA_CNTL_STATUS)/sizeof(mmIA_CNTL_STATUS[0]), 0, 0 },
+	{ "mmVGT_DEBUG_CNTL", REG_MMIO, 0x2238, &mmVGT_DEBUG_CNTL[0], sizeof(mmVGT_DEBUG_CNTL)/sizeof(mmVGT_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmVGT_DEBUG_DATA", REG_MMIO, 0x2239, &mmVGT_DEBUG_DATA[0], sizeof(mmVGT_DEBUG_DATA)/sizeof(mmVGT_DEBUG_DATA[0]), 0, 0 },
+	{ "mmIA_DEBUG_CNTL", REG_MMIO, 0x223a, &mmIA_DEBUG_CNTL[0], sizeof(mmIA_DEBUG_CNTL)/sizeof(mmIA_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmIA_DEBUG_DATA", REG_MMIO, 0x223b, &mmIA_DEBUG_DATA[0], sizeof(mmIA_DEBUG_DATA)/sizeof(mmIA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmVGT_CNTL_STATUS", REG_MMIO, 0x223c, &mmVGT_CNTL_STATUS[0], sizeof(mmVGT_CNTL_STATUS)/sizeof(mmVGT_CNTL_STATUS[0]), 0, 0 },
+	{ "mmWD_DEBUG_CNTL", REG_MMIO, 0x223d, &mmWD_DEBUG_CNTL[0], sizeof(mmWD_DEBUG_CNTL)/sizeof(mmWD_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmWD_DEBUG_DATA", REG_MMIO, 0x223e, &mmWD_DEBUG_DATA[0], sizeof(mmWD_DEBUG_DATA)/sizeof(mmWD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmWD_CNTL_STATUS", REG_MMIO, 0x223f, &mmWD_CNTL_STATUS[0], sizeof(mmWD_CNTL_STATUS)/sizeof(mmWD_CNTL_STATUS[0]), 0, 0 },
+	{ "mmCC_GC_PRIM_CONFIG", REG_MMIO, 0x2240, &mmCC_GC_PRIM_CONFIG[0], sizeof(mmCC_GC_PRIM_CONFIG)/sizeof(mmCC_GC_PRIM_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_PRIM_CONFIG", REG_MMIO, 0x2241, &mmGC_USER_PRIM_CONFIG[0], sizeof(mmGC_USER_PRIM_CONFIG)/sizeof(mmGC_USER_PRIM_CONFIG[0]), 0, 0 },
+	{ "mmWD_QOS", REG_MMIO, 0x2242, &mmWD_QOS[0], sizeof(mmWD_QOS)/sizeof(mmWD_QOS[0]), 0, 0 },
+	{ "mmVGT_SYS_CONFIG", REG_MMIO, 0x2263, &mmVGT_SYS_CONFIG[0], sizeof(mmVGT_SYS_CONFIG)/sizeof(mmVGT_SYS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_VS_MAX_WAVE_ID", REG_MMIO, 0x2268, &mmVGT_VS_MAX_WAVE_ID[0], sizeof(mmVGT_VS_MAX_WAVE_ID)/sizeof(mmVGT_VS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmGFX_PIPE_CONTROL", REG_MMIO, 0x226d, &mmGFX_PIPE_CONTROL[0], sizeof(mmGFX_PIPE_CONTROL)/sizeof(mmGFX_PIPE_CONTROL[0]), 0, 0 },
+	{ "mmCC_GC_SHADER_ARRAY_CONFIG", REG_MMIO, 0x226f, &mmCC_GC_SHADER_ARRAY_CONFIG[0], sizeof(mmCC_GC_SHADER_ARRAY_CONFIG)/sizeof(mmCC_GC_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_SHADER_ARRAY_CONFIG", REG_MMIO, 0x2270, &mmGC_USER_SHADER_ARRAY_CONFIG[0], sizeof(mmGC_USER_SHADER_ARRAY_CONFIG)/sizeof(mmGC_USER_SHADER_ARRAY_CONFIG[0]), 0, 0 },
+	{ "mmVGT_DMA_PRIMITIVE_TYPE", REG_MMIO, 0x2271, &mmVGT_DMA_PRIMITIVE_TYPE[0], sizeof(mmVGT_DMA_PRIMITIVE_TYPE)/sizeof(mmVGT_DMA_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_DMA_CONTROL", REG_MMIO, 0x2272, &mmVGT_DMA_CONTROL[0], sizeof(mmVGT_DMA_CONTROL)/sizeof(mmVGT_DMA_CONTROL[0]), 0, 0 },
+	{ "mmVGT_DMA_LS_HS_CONFIG", REG_MMIO, 0x2273, &mmVGT_DMA_LS_HS_CONFIG[0], sizeof(mmVGT_DMA_LS_HS_CONFIG)/sizeof(mmVGT_DMA_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_CNTL", REG_MMIO, 0x2280, &mmPA_SU_DEBUG_CNTL[0], sizeof(mmPA_SU_DEBUG_CNTL)/sizeof(mmPA_SU_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_DEBUG_DATA", REG_MMIO, 0x2281, &mmPA_SU_DEBUG_DATA[0], sizeof(mmPA_SU_DEBUG_DATA)/sizeof(mmPA_SU_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_CL_CNTL_STATUS", REG_MMIO, 0x2284, &mmPA_CL_CNTL_STATUS[0], sizeof(mmPA_CL_CNTL_STATUS)/sizeof(mmPA_CL_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_CL_ENHANCE", REG_MMIO, 0x2285, &mmPA_CL_ENHANCE[0], sizeof(mmPA_CL_ENHANCE)/sizeof(mmPA_CL_ENHANCE[0]), 0, 0 },
+	{ "mmPA_CL_RESET_DEBUG", REG_MMIO, 0x2286, &mmPA_CL_RESET_DEBUG[0], sizeof(mmPA_CL_RESET_DEBUG)/sizeof(mmPA_CL_RESET_DEBUG[0]), 0, 0 },
+	{ "mmPA_SU_CNTL_STATUS", REG_MMIO, 0x2294, &mmPA_SU_CNTL_STATUS[0], sizeof(mmPA_SU_CNTL_STATUS)/sizeof(mmPA_SU_CNTL_STATUS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_DEPTH_CNTL", REG_MMIO, 0x2295, &mmPA_SC_FIFO_DEPTH_CNTL[0], sizeof(mmPA_SC_FIFO_DEPTH_CNTL)/sizeof(mmPA_SC_FIFO_DEPTH_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c0, &mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c1, &mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_HV_LOCK", REG_MMIO, 0x22c2, &mmPA_SC_TRAP_SCREEN_HV_LOCK[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK)/sizeof(mmPA_SC_TRAP_SCREEN_HV_LOCK[0]), 0, 0 },
+	{ "mmPA_SC_FORCE_EOV_MAX_CNTS", REG_MMIO, 0x22c9, &mmPA_SC_FORCE_EOV_MAX_CNTS[0], sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS)/sizeof(mmPA_SC_FORCE_EOV_MAX_CNTS[0]), 0, 0 },
+	{ "mmPA_SC_FIFO_SIZE", REG_MMIO, 0x22f3, &mmPA_SC_FIFO_SIZE[0], sizeof(mmPA_SC_FIFO_SIZE)/sizeof(mmPA_SC_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_IF_FIFO_SIZE", REG_MMIO, 0x22f5, &mmPA_SC_IF_FIFO_SIZE[0], sizeof(mmPA_SC_IF_FIFO_SIZE)/sizeof(mmPA_SC_IF_FIFO_SIZE[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_CNTL", REG_MMIO, 0x22f6, &mmPA_SC_DEBUG_CNTL[0], sizeof(mmPA_SC_DEBUG_CNTL)/sizeof(mmPA_SC_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_DEBUG_DATA", REG_MMIO, 0x22f7, &mmPA_SC_DEBUG_DATA[0], sizeof(mmPA_SC_DEBUG_DATA)/sizeof(mmPA_SC_DEBUG_DATA[0]), 0, 0 },
+	{ "mmPA_SC_ENHANCE", REG_MMIO, 0x22fc, &mmPA_SC_ENHANCE[0], sizeof(mmPA_SC_ENHANCE)/sizeof(mmPA_SC_ENHANCE[0]), 0, 0 },
+	{ "mmPA_SC_ENHANCE_1", REG_MMIO, 0x22fd, &mmPA_SC_ENHANCE_1[0], sizeof(mmPA_SC_ENHANCE_1)/sizeof(mmPA_SC_ENHANCE_1[0]), 0, 0 },
+	{ "mmPA_SC_DSM_CNTL", REG_MMIO, 0x22fe, &mmPA_SC_DSM_CNTL[0], sizeof(mmPA_SC_DSM_CNTL)/sizeof(mmPA_SC_DSM_CNTL[0]), 0, 0 },
+	{ "ixDIDT_DB_CTRL_OCP", REG_SMC, 0x23, &ixDIDT_DB_CTRL_OCP[0], sizeof(ixDIDT_DB_CTRL_OCP)/sizeof(ixDIDT_DB_CTRL_OCP[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG7", REG_SMC, 0x23, &ixVGT_DEBUG_REG7[0], sizeof(ixVGT_DEBUG_REG7)/sizeof(ixVGT_DEBUG_REG7[0]), 0, 0 },
+	{ "mmSQ_CONFIG", REG_MMIO, 0x2300, &mmSQ_CONFIG[0], sizeof(mmSQ_CONFIG)/sizeof(mmSQ_CONFIG[0]), 0, 0 },
+	{ "mmSQC_CONFIG", REG_MMIO, 0x2301, &mmSQC_CONFIG[0], sizeof(mmSQC_CONFIG)/sizeof(mmSQC_CONFIG[0]), 0, 0 },
+	{ "mmSQ_RANDOM_WAVE_PRI", REG_MMIO, 0x2303, &mmSQ_RANDOM_WAVE_PRI[0], sizeof(mmSQ_RANDOM_WAVE_PRI)/sizeof(mmSQ_RANDOM_WAVE_PRI[0]), 0, 0 },
+	{ "mmSQ_REG_CREDITS", REG_MMIO, 0x2304, &mmSQ_REG_CREDITS[0], sizeof(mmSQ_REG_CREDITS)/sizeof(mmSQ_REG_CREDITS[0]), 0, 0 },
+	{ "mmSQ_FIFO_SIZES", REG_MMIO, 0x2305, &mmSQ_FIFO_SIZES[0], sizeof(mmSQ_FIFO_SIZES)/sizeof(mmSQ_FIFO_SIZES[0]), 0, 0 },
+	{ "mmSQ_DSM_CNTL", REG_MMIO, 0x2306, &mmSQ_DSM_CNTL[0], sizeof(mmSQ_DSM_CNTL)/sizeof(mmSQ_DSM_CNTL[0]), 0, 0 },
+	{ "mmCC_SQC_BANK_DISABLE", REG_MMIO, 0x2307, &mmCC_SQC_BANK_DISABLE[0], sizeof(mmCC_SQC_BANK_DISABLE)/sizeof(mmCC_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmUSER_SQC_BANK_DISABLE", REG_MMIO, 0x2308, &mmUSER_SQC_BANK_DISABLE[0], sizeof(mmUSER_SQC_BANK_DISABLE)/sizeof(mmUSER_SQC_BANK_DISABLE[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL", REG_MMIO, 0x2309, &mmSQ_DEBUG_STS_GLOBAL[0], sizeof(mmSQ_DEBUG_STS_GLOBAL)/sizeof(mmSQ_DEBUG_STS_GLOBAL[0]), 0, 0 },
+	{ "mmSH_MEM_BASES", REG_MMIO, 0x230a, &mmSH_MEM_BASES[0], sizeof(mmSH_MEM_BASES)/sizeof(mmSH_MEM_BASES[0]), 0, 0 },
+	{ "mmSH_MEM_APE1_BASE", REG_MMIO, 0x230b, &mmSH_MEM_APE1_BASE[0], sizeof(mmSH_MEM_APE1_BASE)/sizeof(mmSH_MEM_APE1_BASE[0]), 0, 0 },
+	{ "mmSH_MEM_APE1_LIMIT", REG_MMIO, 0x230c, &mmSH_MEM_APE1_LIMIT[0], sizeof(mmSH_MEM_APE1_LIMIT)/sizeof(mmSH_MEM_APE1_LIMIT[0]), 0, 0 },
+	{ "mmSH_MEM_CONFIG", REG_MMIO, 0x230d, &mmSH_MEM_CONFIG[0], sizeof(mmSH_MEM_CONFIG)/sizeof(mmSH_MEM_CONFIG[0]), 0, 0 },
+	{ "mmSQC_DSM_CNTL", REG_MMIO, 0x230f, &mmSQC_DSM_CNTL[0], sizeof(mmSQC_DSM_CNTL)/sizeof(mmSQC_DSM_CNTL[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL2", REG_MMIO, 0x2310, &mmSQ_DEBUG_STS_GLOBAL2[0], sizeof(mmSQ_DEBUG_STS_GLOBAL2)/sizeof(mmSQ_DEBUG_STS_GLOBAL2[0]), 0, 0 },
+	{ "mmSQ_DEBUG_STS_GLOBAL3", REG_MMIO, 0x2311, &mmSQ_DEBUG_STS_GLOBAL3[0], sizeof(mmSQ_DEBUG_STS_GLOBAL3)/sizeof(mmSQ_DEBUG_STS_GLOBAL3[0]), 0, 0 },
+	{ "mmCC_GC_SHADER_RATE_CONFIG", REG_MMIO, 0x2312, &mmCC_GC_SHADER_RATE_CONFIG[0], sizeof(mmCC_GC_SHADER_RATE_CONFIG)/sizeof(mmCC_GC_SHADER_RATE_CONFIG[0]), 0, 0 },
+	{ "mmGC_USER_SHADER_RATE_CONFIG", REG_MMIO, 0x2313, &mmGC_USER_SHADER_RATE_CONFIG[0], sizeof(mmGC_USER_SHADER_RATE_CONFIG)/sizeof(mmGC_USER_SHADER_RATE_CONFIG[0]), 0, 0 },
+	{ "mmSQ_INTERRUPT_AUTO_MASK", REG_MMIO, 0x2314, &mmSQ_INTERRUPT_AUTO_MASK[0], sizeof(mmSQ_INTERRUPT_AUTO_MASK)/sizeof(mmSQ_INTERRUPT_AUTO_MASK[0]), 0, 0 },
+	{ "mmSQ_INTERRUPT_MSG_CTRL", REG_MMIO, 0x2315, &mmSQ_INTERRUPT_MSG_CTRL[0], sizeof(mmSQ_INTERRUPT_MSG_CTRL)/sizeof(mmSQ_INTERRUPT_MSG_CTRL[0]), 0, 0 },
+	{ "mmSQ_REG_TIMESTAMP", REG_MMIO, 0x2374, &mmSQ_REG_TIMESTAMP[0], sizeof(mmSQ_REG_TIMESTAMP)/sizeof(mmSQ_REG_TIMESTAMP[0]), 0, 0 },
+	{ "mmSQ_CMD_TIMESTAMP", REG_MMIO, 0x2375, &mmSQ_CMD_TIMESTAMP[0], sizeof(mmSQ_CMD_TIMESTAMP)/sizeof(mmSQ_CMD_TIMESTAMP[0]), 0, 0 },
+	{ "mmSQ_IND_INDEX", REG_MMIO, 0x2378, &mmSQ_IND_INDEX[0], sizeof(mmSQ_IND_INDEX)/sizeof(mmSQ_IND_INDEX[0]), 0, 0 },
+	{ "mmSQ_IND_DATA", REG_MMIO, 0x2379, &mmSQ_IND_DATA[0], sizeof(mmSQ_IND_DATA)/sizeof(mmSQ_IND_DATA[0]), 0, 0 },
+	{ "mmSQ_CMD", REG_MMIO, 0x237b, &mmSQ_CMD[0], sizeof(mmSQ_CMD)/sizeof(mmSQ_CMD[0]), 0, 0 },
+	{ "mmSQ_TIME_HI", REG_MMIO, 0x237c, &mmSQ_TIME_HI[0], sizeof(mmSQ_TIME_HI)/sizeof(mmSQ_TIME_HI[0]), 0, 0 },
+	{ "mmSQ_TIME_LO", REG_MMIO, 0x237d, &mmSQ_TIME_LO[0], sizeof(mmSQ_TIME_LO)/sizeof(mmSQ_TIME_LO[0]), 0, 0 },
+	{ "mmSQ_VOP3_0_SDST_ENC", REG_MMIO, 0x237f, &mmSQ_VOP3_0_SDST_ENC[0], sizeof(mmSQ_VOP3_0_SDST_ENC)/sizeof(mmSQ_VOP3_0_SDST_ENC[0]), 0, 0 },
+	{ "mmSQ_VOP_SDWA", REG_MMIO, 0x237f, &mmSQ_VOP_SDWA[0], sizeof(mmSQ_VOP_SDWA)/sizeof(mmSQ_VOP_SDWA[0]), 0, 0 },
+	{ "mmSQ_MTBUF_1", REG_MMIO, 0x237f, &mmSQ_MTBUF_1[0], sizeof(mmSQ_MTBUF_1)/sizeof(mmSQ_MTBUF_1[0]), 0, 0 },
+	{ "mmSQ_SMEM_1", REG_MMIO, 0x237f, &mmSQ_SMEM_1[0], sizeof(mmSQ_SMEM_1)/sizeof(mmSQ_SMEM_1[0]), 0, 0 },
+	{ "mmSQ_EXP_1", REG_MMIO, 0x237f, &mmSQ_EXP_1[0], sizeof(mmSQ_EXP_1)/sizeof(mmSQ_EXP_1[0]), 0, 0 },
+	{ "mmSQ_SOP2", REG_MMIO, 0x237f, &mmSQ_SOP2[0], sizeof(mmSQ_SOP2)/sizeof(mmSQ_SOP2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CNTR", REG_MMIO, 0x2390, &mmSQ_THREAD_TRACE_CNTR[0], sizeof(mmSQ_THREAD_TRACE_CNTR)/sizeof(mmSQ_THREAD_TRACE_CNTR[0]), 0, 0 },
+	{ "mmSQ_LB_CTR_CTRL", REG_MMIO, 0x2398, &mmSQ_LB_CTR_CTRL[0], sizeof(mmSQ_LB_CTR_CTRL)/sizeof(mmSQ_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_CYCLES", REG_MMIO, 0x2399, &mmSQ_LB_DATA_ALU_CYCLES[0], sizeof(mmSQ_LB_DATA_ALU_CYCLES)/sizeof(mmSQ_LB_DATA_ALU_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_CYCLES", REG_MMIO, 0x239a, &mmSQ_LB_DATA_TEX_CYCLES[0], sizeof(mmSQ_LB_DATA_TEX_CYCLES)/sizeof(mmSQ_LB_DATA_TEX_CYCLES[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_ALU_STALLS", REG_MMIO, 0x239b, &mmSQ_LB_DATA_ALU_STALLS[0], sizeof(mmSQ_LB_DATA_ALU_STALLS)/sizeof(mmSQ_LB_DATA_ALU_STALLS[0]), 0, 0 },
+	{ "mmSQ_LB_DATA_TEX_STALLS", REG_MMIO, 0x239c, &mmSQ_LB_DATA_TEX_STALLS[0], sizeof(mmSQ_LB_DATA_TEX_STALLS)/sizeof(mmSQ_LB_DATA_TEX_STALLS[0]), 0, 0 },
+	{ "mmSQC_EDC_CNT", REG_MMIO, 0x23a0, &mmSQC_EDC_CNT[0], sizeof(mmSQC_EDC_CNT)/sizeof(mmSQC_EDC_CNT[0]), 0, 0 },
+	{ "mmSQ_EDC_SEC_CNT", REG_MMIO, 0x23a1, &mmSQ_EDC_SEC_CNT[0], sizeof(mmSQ_EDC_SEC_CNT)/sizeof(mmSQ_EDC_SEC_CNT[0]), 0, 0 },
+	{ "mmSQ_EDC_DED_CNT", REG_MMIO, 0x23a2, &mmSQ_EDC_DED_CNT[0], sizeof(mmSQ_EDC_DED_CNT)/sizeof(mmSQ_EDC_DED_CNT[0]), 0, 0 },
+	{ "mmSQ_EDC_INFO", REG_MMIO, 0x23a3, &mmSQ_EDC_INFO[0], sizeof(mmSQ_EDC_INFO)/sizeof(mmSQ_EDC_INFO[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_WAVE_START", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_WAVE_START[0], sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START)/sizeof(mmSQ_THREAD_TRACE_WORD_WAVE_START[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_EVENT", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_EVENT[0], sizeof(mmSQ_THREAD_TRACE_WORD_EVENT)/sizeof(mmSQ_THREAD_TRACE_WORD_EVENT[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_INST[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST)/sizeof(mmSQ_THREAD_TRACE_WORD_INST[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_CMN", REG_MMIO, 0x23b0, &mmSQ_THREAD_TRACE_WORD_CMN[0], sizeof(mmSQ_THREAD_TRACE_WORD_CMN)/sizeof(mmSQ_THREAD_TRACE_WORD_CMN[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2", REG_MMIO, 0x23b1, &mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0], sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2)/sizeof(mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2[0]), 0, 0 },
+	{ "mmSQ_WREXEC_EXEC_LO", REG_MMIO, 0x23b1, &mmSQ_WREXEC_EXEC_LO[0], sizeof(mmSQ_WREXEC_EXEC_LO)/sizeof(mmSQ_WREXEC_EXEC_LO[0]), 0, 0 },
+	{ "mmSQC_GATCL1_CNTL", REG_MMIO, 0x23b2, &mmSQC_GATCL1_CNTL[0], sizeof(mmSQC_GATCL1_CNTL)/sizeof(mmSQC_GATCL1_CNTL[0]), 0, 0 },
+	{ "mmSQC_ATC_EDC_GATCL1_CNT", REG_MMIO, 0x23b3, &mmSQC_ATC_EDC_GATCL1_CNT[0], sizeof(mmSQC_ATC_EDC_GATCL1_CNT)/sizeof(mmSQC_ATC_EDC_GATCL1_CNT[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD0", REG_MMIO, 0x23c0, &mmSQ_BUF_RSRC_WORD0[0], sizeof(mmSQ_BUF_RSRC_WORD0)/sizeof(mmSQ_BUF_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD1", REG_MMIO, 0x23c1, &mmSQ_BUF_RSRC_WORD1[0], sizeof(mmSQ_BUF_RSRC_WORD1)/sizeof(mmSQ_BUF_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD2", REG_MMIO, 0x23c2, &mmSQ_BUF_RSRC_WORD2[0], sizeof(mmSQ_BUF_RSRC_WORD2)/sizeof(mmSQ_BUF_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_BUF_RSRC_WORD3", REG_MMIO, 0x23c3, &mmSQ_BUF_RSRC_WORD3[0], sizeof(mmSQ_BUF_RSRC_WORD3)/sizeof(mmSQ_BUF_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD0", REG_MMIO, 0x23c4, &mmSQ_IMG_RSRC_WORD0[0], sizeof(mmSQ_IMG_RSRC_WORD0)/sizeof(mmSQ_IMG_RSRC_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD1", REG_MMIO, 0x23c5, &mmSQ_IMG_RSRC_WORD1[0], sizeof(mmSQ_IMG_RSRC_WORD1)/sizeof(mmSQ_IMG_RSRC_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD2", REG_MMIO, 0x23c6, &mmSQ_IMG_RSRC_WORD2[0], sizeof(mmSQ_IMG_RSRC_WORD2)/sizeof(mmSQ_IMG_RSRC_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD3", REG_MMIO, 0x23c7, &mmSQ_IMG_RSRC_WORD3[0], sizeof(mmSQ_IMG_RSRC_WORD3)/sizeof(mmSQ_IMG_RSRC_WORD3[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD4", REG_MMIO, 0x23c8, &mmSQ_IMG_RSRC_WORD4[0], sizeof(mmSQ_IMG_RSRC_WORD4)/sizeof(mmSQ_IMG_RSRC_WORD4[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD5", REG_MMIO, 0x23c9, &mmSQ_IMG_RSRC_WORD5[0], sizeof(mmSQ_IMG_RSRC_WORD5)/sizeof(mmSQ_IMG_RSRC_WORD5[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD6", REG_MMIO, 0x23ca, &mmSQ_IMG_RSRC_WORD6[0], sizeof(mmSQ_IMG_RSRC_WORD6)/sizeof(mmSQ_IMG_RSRC_WORD6[0]), 0, 0 },
+	{ "mmSQ_IMG_RSRC_WORD7", REG_MMIO, 0x23cb, &mmSQ_IMG_RSRC_WORD7[0], sizeof(mmSQ_IMG_RSRC_WORD7)/sizeof(mmSQ_IMG_RSRC_WORD7[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD0", REG_MMIO, 0x23cc, &mmSQ_IMG_SAMP_WORD0[0], sizeof(mmSQ_IMG_SAMP_WORD0)/sizeof(mmSQ_IMG_SAMP_WORD0[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD1", REG_MMIO, 0x23cd, &mmSQ_IMG_SAMP_WORD1[0], sizeof(mmSQ_IMG_SAMP_WORD1)/sizeof(mmSQ_IMG_SAMP_WORD1[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD2", REG_MMIO, 0x23ce, &mmSQ_IMG_SAMP_WORD2[0], sizeof(mmSQ_IMG_SAMP_WORD2)/sizeof(mmSQ_IMG_SAMP_WORD2[0]), 0, 0 },
+	{ "mmSQ_IMG_SAMP_WORD3", REG_MMIO, 0x23cf, &mmSQ_IMG_SAMP_WORD3[0], sizeof(mmSQ_IMG_SAMP_WORD3)/sizeof(mmSQ_IMG_SAMP_WORD3[0]), 0, 0 },
+	{ "mmSQ_FLAT_SCRATCH_WORD0", REG_MMIO, 0x23d0, &mmSQ_FLAT_SCRATCH_WORD0[0], sizeof(mmSQ_FLAT_SCRATCH_WORD0)/sizeof(mmSQ_FLAT_SCRATCH_WORD0[0]), 0, 0 },
+	{ "mmSQ_FLAT_SCRATCH_WORD1", REG_MMIO, 0x23d1, &mmSQ_FLAT_SCRATCH_WORD1[0], sizeof(mmSQ_FLAT_SCRATCH_WORD1)/sizeof(mmSQ_FLAT_SCRATCH_WORD1[0]), 0, 0 },
+	{ "mmSQ_M0_GPR_IDX_WORD", REG_MMIO, 0x23d2, &mmSQ_M0_GPR_IDX_WORD[0], sizeof(mmSQ_M0_GPR_IDX_WORD)/sizeof(mmSQ_M0_GPR_IDX_WORD[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG26", REG_SMC, 0x24, &ixVGT_DEBUG_REG26[0], sizeof(ixVGT_DEBUG_REG26)/sizeof(ixVGT_DEBUG_REG26[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY", REG_MMIO, 0x2414, &mmSX_DEBUG_BUSY[0], sizeof(mmSX_DEBUG_BUSY)/sizeof(mmSX_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_2", REG_MMIO, 0x2415, &mmSX_DEBUG_BUSY_2[0], sizeof(mmSX_DEBUG_BUSY_2)/sizeof(mmSX_DEBUG_BUSY_2[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_3", REG_MMIO, 0x2416, &mmSX_DEBUG_BUSY_3[0], sizeof(mmSX_DEBUG_BUSY_3)/sizeof(mmSX_DEBUG_BUSY_3[0]), 0, 0 },
+	{ "mmSX_DEBUG_BUSY_4", REG_MMIO, 0x2417, &mmSX_DEBUG_BUSY_4[0], sizeof(mmSX_DEBUG_BUSY_4)/sizeof(mmSX_DEBUG_BUSY_4[0]), 0, 0 },
+	{ "mmSX_DEBUG_1", REG_MMIO, 0x2418, &mmSX_DEBUG_1[0], sizeof(mmSX_DEBUG_1)/sizeof(mmSX_DEBUG_1[0]), 0, 0 },
+	{ "mmSPI_PS_MAX_WAVE_ID", REG_MMIO, 0x243a, &mmSPI_PS_MAX_WAVE_ID[0], sizeof(mmSPI_PS_MAX_WAVE_ID)/sizeof(mmSPI_PS_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmSPI_START_PHASE", REG_MMIO, 0x243b, &mmSPI_START_PHASE[0], sizeof(mmSPI_START_PHASE)/sizeof(mmSPI_START_PHASE[0]), 0, 0 },
+	{ "mmSPI_GFX_CNTL", REG_MMIO, 0x243c, &mmSPI_GFX_CNTL[0], sizeof(mmSPI_GFX_CNTL)/sizeof(mmSPI_GFX_CNTL[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL", REG_MMIO, 0x2440, &mmSPI_CONFIG_CNTL[0], sizeof(mmSPI_CONFIG_CNTL)/sizeof(mmSPI_CONFIG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_CNTL", REG_MMIO, 0x2441, &mmSPI_DEBUG_CNTL[0], sizeof(mmSPI_DEBUG_CNTL)/sizeof(mmSPI_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmSPI_DEBUG_READ", REG_MMIO, 0x2442, &mmSPI_DEBUG_READ[0], sizeof(mmSPI_DEBUG_READ)/sizeof(mmSPI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_DSM_CNTL", REG_MMIO, 0x2443, &mmSPI_DSM_CNTL[0], sizeof(mmSPI_DSM_CNTL)/sizeof(mmSPI_DSM_CNTL[0]), 0, 0 },
+	{ "mmSPI_EDC_CNT", REG_MMIO, 0x2444, &mmSPI_EDC_CNT[0], sizeof(mmSPI_EDC_CNT)/sizeof(mmSPI_EDC_CNT[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL_1", REG_MMIO, 0x244f, &mmSPI_CONFIG_CNTL_1[0], sizeof(mmSPI_CONFIG_CNTL_1)/sizeof(mmSPI_CONFIG_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_DEBUG_BUSY", REG_MMIO, 0x2450, &mmSPI_DEBUG_BUSY[0], sizeof(mmSPI_DEBUG_BUSY)/sizeof(mmSPI_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_CONFIG_CNTL_2", REG_MMIO, 0x2451, &mmSPI_CONFIG_CNTL_2[0], sizeof(mmSPI_CONFIG_CNTL_2)/sizeof(mmSPI_CONFIG_CNTL_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_CNTL", REG_MMIO, 0x24aa, &mmSPI_WF_LIFETIME_CNTL[0], sizeof(mmSPI_WF_LIFETIME_CNTL)/sizeof(mmSPI_WF_LIFETIME_CNTL[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_0", REG_MMIO, 0x24ab, &mmSPI_WF_LIFETIME_LIMIT_0[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_0)/sizeof(mmSPI_WF_LIFETIME_LIMIT_0[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_1", REG_MMIO, 0x24ac, &mmSPI_WF_LIFETIME_LIMIT_1[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_1)/sizeof(mmSPI_WF_LIFETIME_LIMIT_1[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_2", REG_MMIO, 0x24ad, &mmSPI_WF_LIFETIME_LIMIT_2[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_2)/sizeof(mmSPI_WF_LIFETIME_LIMIT_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_3", REG_MMIO, 0x24ae, &mmSPI_WF_LIFETIME_LIMIT_3[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_3)/sizeof(mmSPI_WF_LIFETIME_LIMIT_3[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_4", REG_MMIO, 0x24af, &mmSPI_WF_LIFETIME_LIMIT_4[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_4)/sizeof(mmSPI_WF_LIFETIME_LIMIT_4[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_5", REG_MMIO, 0x24b0, &mmSPI_WF_LIFETIME_LIMIT_5[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_5)/sizeof(mmSPI_WF_LIFETIME_LIMIT_5[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_6", REG_MMIO, 0x24b1, &mmSPI_WF_LIFETIME_LIMIT_6[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_6)/sizeof(mmSPI_WF_LIFETIME_LIMIT_6[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_7", REG_MMIO, 0x24b2, &mmSPI_WF_LIFETIME_LIMIT_7[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_7)/sizeof(mmSPI_WF_LIFETIME_LIMIT_7[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_8", REG_MMIO, 0x24b3, &mmSPI_WF_LIFETIME_LIMIT_8[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_8)/sizeof(mmSPI_WF_LIFETIME_LIMIT_8[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_LIMIT_9", REG_MMIO, 0x24b4, &mmSPI_WF_LIFETIME_LIMIT_9[0], sizeof(mmSPI_WF_LIFETIME_LIMIT_9)/sizeof(mmSPI_WF_LIFETIME_LIMIT_9[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_0", REG_MMIO, 0x24b5, &mmSPI_WF_LIFETIME_STATUS_0[0], sizeof(mmSPI_WF_LIFETIME_STATUS_0)/sizeof(mmSPI_WF_LIFETIME_STATUS_0[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_1", REG_MMIO, 0x24b6, &mmSPI_WF_LIFETIME_STATUS_1[0], sizeof(mmSPI_WF_LIFETIME_STATUS_1)/sizeof(mmSPI_WF_LIFETIME_STATUS_1[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_2", REG_MMIO, 0x24b7, &mmSPI_WF_LIFETIME_STATUS_2[0], sizeof(mmSPI_WF_LIFETIME_STATUS_2)/sizeof(mmSPI_WF_LIFETIME_STATUS_2[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_3", REG_MMIO, 0x24b8, &mmSPI_WF_LIFETIME_STATUS_3[0], sizeof(mmSPI_WF_LIFETIME_STATUS_3)/sizeof(mmSPI_WF_LIFETIME_STATUS_3[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_4", REG_MMIO, 0x24b9, &mmSPI_WF_LIFETIME_STATUS_4[0], sizeof(mmSPI_WF_LIFETIME_STATUS_4)/sizeof(mmSPI_WF_LIFETIME_STATUS_4[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_5", REG_MMIO, 0x24ba, &mmSPI_WF_LIFETIME_STATUS_5[0], sizeof(mmSPI_WF_LIFETIME_STATUS_5)/sizeof(mmSPI_WF_LIFETIME_STATUS_5[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_6", REG_MMIO, 0x24bb, &mmSPI_WF_LIFETIME_STATUS_6[0], sizeof(mmSPI_WF_LIFETIME_STATUS_6)/sizeof(mmSPI_WF_LIFETIME_STATUS_6[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_7", REG_MMIO, 0x24bc, &mmSPI_WF_LIFETIME_STATUS_7[0], sizeof(mmSPI_WF_LIFETIME_STATUS_7)/sizeof(mmSPI_WF_LIFETIME_STATUS_7[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_8", REG_MMIO, 0x24bd, &mmSPI_WF_LIFETIME_STATUS_8[0], sizeof(mmSPI_WF_LIFETIME_STATUS_8)/sizeof(mmSPI_WF_LIFETIME_STATUS_8[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_9", REG_MMIO, 0x24be, &mmSPI_WF_LIFETIME_STATUS_9[0], sizeof(mmSPI_WF_LIFETIME_STATUS_9)/sizeof(mmSPI_WF_LIFETIME_STATUS_9[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_10", REG_MMIO, 0x24bf, &mmSPI_WF_LIFETIME_STATUS_10[0], sizeof(mmSPI_WF_LIFETIME_STATUS_10)/sizeof(mmSPI_WF_LIFETIME_STATUS_10[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_11", REG_MMIO, 0x24c0, &mmSPI_WF_LIFETIME_STATUS_11[0], sizeof(mmSPI_WF_LIFETIME_STATUS_11)/sizeof(mmSPI_WF_LIFETIME_STATUS_11[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_12", REG_MMIO, 0x24c1, &mmSPI_WF_LIFETIME_STATUS_12[0], sizeof(mmSPI_WF_LIFETIME_STATUS_12)/sizeof(mmSPI_WF_LIFETIME_STATUS_12[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_13", REG_MMIO, 0x24c2, &mmSPI_WF_LIFETIME_STATUS_13[0], sizeof(mmSPI_WF_LIFETIME_STATUS_13)/sizeof(mmSPI_WF_LIFETIME_STATUS_13[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_14", REG_MMIO, 0x24c3, &mmSPI_WF_LIFETIME_STATUS_14[0], sizeof(mmSPI_WF_LIFETIME_STATUS_14)/sizeof(mmSPI_WF_LIFETIME_STATUS_14[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_15", REG_MMIO, 0x24c4, &mmSPI_WF_LIFETIME_STATUS_15[0], sizeof(mmSPI_WF_LIFETIME_STATUS_15)/sizeof(mmSPI_WF_LIFETIME_STATUS_15[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_16", REG_MMIO, 0x24c5, &mmSPI_WF_LIFETIME_STATUS_16[0], sizeof(mmSPI_WF_LIFETIME_STATUS_16)/sizeof(mmSPI_WF_LIFETIME_STATUS_16[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_17", REG_MMIO, 0x24c6, &mmSPI_WF_LIFETIME_STATUS_17[0], sizeof(mmSPI_WF_LIFETIME_STATUS_17)/sizeof(mmSPI_WF_LIFETIME_STATUS_17[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_18", REG_MMIO, 0x24c7, &mmSPI_WF_LIFETIME_STATUS_18[0], sizeof(mmSPI_WF_LIFETIME_STATUS_18)/sizeof(mmSPI_WF_LIFETIME_STATUS_18[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_19", REG_MMIO, 0x24c8, &mmSPI_WF_LIFETIME_STATUS_19[0], sizeof(mmSPI_WF_LIFETIME_STATUS_19)/sizeof(mmSPI_WF_LIFETIME_STATUS_19[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_STATUS_20", REG_MMIO, 0x24c9, &mmSPI_WF_LIFETIME_STATUS_20[0], sizeof(mmSPI_WF_LIFETIME_STATUS_20)/sizeof(mmSPI_WF_LIFETIME_STATUS_20[0]), 0, 0 },
+	{ "mmSPI_WF_LIFETIME_DEBUG", REG_MMIO, 0x24ca, &mmSPI_WF_LIFETIME_DEBUG[0], sizeof(mmSPI_WF_LIFETIME_DEBUG)/sizeof(mmSPI_WF_LIFETIME_DEBUG[0]), 0, 0 },
+	{ "mmSPI_SLAVE_DEBUG_BUSY", REG_MMIO, 0x24d3, &mmSPI_SLAVE_DEBUG_BUSY[0], sizeof(mmSPI_SLAVE_DEBUG_BUSY)/sizeof(mmSPI_SLAVE_DEBUG_BUSY[0]), 0, 0 },
+	{ "mmSPI_LB_CTR_CTRL", REG_MMIO, 0x24d4, &mmSPI_LB_CTR_CTRL[0], sizeof(mmSPI_LB_CTR_CTRL)/sizeof(mmSPI_LB_CTR_CTRL[0]), 0, 0 },
+	{ "mmSPI_LB_CU_MASK", REG_MMIO, 0x24d5, &mmSPI_LB_CU_MASK[0], sizeof(mmSPI_LB_CU_MASK)/sizeof(mmSPI_LB_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_LB_DATA_REG", REG_MMIO, 0x24d6, &mmSPI_LB_DATA_REG[0], sizeof(mmSPI_LB_DATA_REG)/sizeof(mmSPI_LB_DATA_REG[0]), 0, 0 },
+	{ "mmSPI_PG_ENABLE_STATIC_CU_MASK", REG_MMIO, 0x24d7, &mmSPI_PG_ENABLE_STATIC_CU_MASK[0], sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK)/sizeof(mmSPI_PG_ENABLE_STATIC_CU_MASK[0]), 0, 0 },
+	{ "mmSPI_GDS_CREDITS", REG_MMIO, 0x24d8, &mmSPI_GDS_CREDITS[0], sizeof(mmSPI_GDS_CREDITS)/sizeof(mmSPI_GDS_CREDITS[0]), 0, 0 },
+	{ "mmSPI_SX_EXPORT_BUFFER_SIZES", REG_MMIO, 0x24d9, &mmSPI_SX_EXPORT_BUFFER_SIZES[0], sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES)/sizeof(mmSPI_SX_EXPORT_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_SX_SCOREBOARD_BUFFER_SIZES", REG_MMIO, 0x24da, &mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0], sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES)/sizeof(mmSPI_SX_SCOREBOARD_BUFFER_SIZES[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_STATUS", REG_MMIO, 0x24db, &mmSPI_CSQ_WF_ACTIVE_STATUS[0], sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS)/sizeof(mmSPI_CSQ_WF_ACTIVE_STATUS[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_0", REG_MMIO, 0x24dc, &mmSPI_CSQ_WF_ACTIVE_COUNT_0[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_0[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_1", REG_MMIO, 0x24dd, &mmSPI_CSQ_WF_ACTIVE_COUNT_1[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_1[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_2", REG_MMIO, 0x24de, &mmSPI_CSQ_WF_ACTIVE_COUNT_2[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_2[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_3", REG_MMIO, 0x24df, &mmSPI_CSQ_WF_ACTIVE_COUNT_3[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_3[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_4", REG_MMIO, 0x24e0, &mmSPI_CSQ_WF_ACTIVE_COUNT_4[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_4[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_5", REG_MMIO, 0x24e1, &mmSPI_CSQ_WF_ACTIVE_COUNT_5[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_5[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_6", REG_MMIO, 0x24e2, &mmSPI_CSQ_WF_ACTIVE_COUNT_6[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_6[0]), 0, 0 },
+	{ "mmSPI_CSQ_WF_ACTIVE_COUNT_7", REG_MMIO, 0x24e3, &mmSPI_CSQ_WF_ACTIVE_COUNT_7[0], sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7)/sizeof(mmSPI_CSQ_WF_ACTIVE_COUNT_7[0]), 0, 0 },
+	{ "mmBCI_DEBUG_READ", REG_MMIO, 0x24eb, &mmBCI_DEBUG_READ[0], sizeof(mmBCI_DEBUG_READ)/sizeof(mmBCI_DEBUG_READ[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24ec, &mmSPI_P0_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24ed, &mmSPI_P0_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24ee, &mmSPI_P0_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24ef, &mmSPI_P0_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P0_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
+	{ "mmSPI_P0_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f0, &mmSPI_P0_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P0_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSBA_LO", REG_MMIO, 0x24f1, &mmSPI_P1_TRAP_SCREEN_PSBA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_LO[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSBA_HI", REG_MMIO, 0x24f2, &mmSPI_P1_TRAP_SCREEN_PSBA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSBA_HI[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSMA_LO", REG_MMIO, 0x24f3, &mmSPI_P1_TRAP_SCREEN_PSMA_LO[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_LO[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_PSMA_HI", REG_MMIO, 0x24f4, &mmSPI_P1_TRAP_SCREEN_PSMA_HI[0], sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI)/sizeof(mmSPI_P1_TRAP_SCREEN_PSMA_HI[0]), 0, 0 },
+	{ "mmSPI_P1_TRAP_SCREEN_GPR_MIN", REG_MMIO, 0x24f5, &mmSPI_P1_TRAP_SCREEN_GPR_MIN[0], sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN)/sizeof(mmSPI_P1_TRAP_SCREEN_GPR_MIN[0]), 0, 0 },
+	{ "mmTD_CNTL", REG_MMIO, 0x2525, &mmTD_CNTL[0], sizeof(mmTD_CNTL)/sizeof(mmTD_CNTL[0]), 0, 0 },
+	{ "mmTD_STATUS", REG_MMIO, 0x2526, &mmTD_STATUS[0], sizeof(mmTD_STATUS)/sizeof(mmTD_STATUS[0]), 0, 0 },
+	{ "mmTD_DEBUG_INDEX", REG_MMIO, 0x2528, &mmTD_DEBUG_INDEX[0], sizeof(mmTD_DEBUG_INDEX)/sizeof(mmTD_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTD_DEBUG_DATA", REG_MMIO, 0x2529, &mmTD_DEBUG_DATA[0], sizeof(mmTD_DEBUG_DATA)/sizeof(mmTD_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTD_DSM_CNTL", REG_MMIO, 0x252f, &mmTD_DSM_CNTL[0], sizeof(mmTD_DSM_CNTL)/sizeof(mmTD_DSM_CNTL[0]), 0, 0 },
+	{ "mmTD_SCRATCH", REG_MMIO, 0x2533, &mmTD_SCRATCH[0], sizeof(mmTD_SCRATCH)/sizeof(mmTD_SCRATCH[0]), 0, 0 },
+	{ "mmTA_CNTL", REG_MMIO, 0x2541, &mmTA_CNTL[0], sizeof(mmTA_CNTL)/sizeof(mmTA_CNTL[0]), 0, 0 },
+	{ "mmTA_CNTL_AUX", REG_MMIO, 0x2542, &mmTA_CNTL_AUX[0], sizeof(mmTA_CNTL_AUX)/sizeof(mmTA_CNTL_AUX[0]), 0, 0 },
+	{ "mmTA_RESERVED_010C", REG_MMIO, 0x2543, &mmTA_RESERVED_010C[0], sizeof(mmTA_RESERVED_010C)/sizeof(mmTA_RESERVED_010C[0]), 0, 0 },
+	{ "mmTA_STATUS", REG_MMIO, 0x2548, &mmTA_STATUS[0], sizeof(mmTA_STATUS)/sizeof(mmTA_STATUS[0]), 0, 0 },
+	{ "mmTA_DEBUG_INDEX", REG_MMIO, 0x254c, &mmTA_DEBUG_INDEX[0], sizeof(mmTA_DEBUG_INDEX)/sizeof(mmTA_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmTA_DEBUG_DATA", REG_MMIO, 0x254d, &mmTA_DEBUG_DATA[0], sizeof(mmTA_DEBUG_DATA)/sizeof(mmTA_DEBUG_DATA[0]), 0, 0 },
+	{ "mmTA_SCRATCH", REG_MMIO, 0x2564, &mmTA_SCRATCH[0], sizeof(mmTA_SCRATCH)/sizeof(mmTA_SCRATCH[0]), 0, 0 },
+	{ "mmSH_HIDDEN_PRIVATE_BASE_VMID", REG_MMIO, 0x2580, &mmSH_HIDDEN_PRIVATE_BASE_VMID[0], sizeof(mmSH_HIDDEN_PRIVATE_BASE_VMID)/sizeof(mmSH_HIDDEN_PRIVATE_BASE_VMID[0]), 0, 0 },
+	{ "mmSH_STATIC_MEM_CONFIG", REG_MMIO, 0x2581, &mmSH_STATIC_MEM_CONFIG[0], sizeof(mmSH_STATIC_MEM_CONFIG)/sizeof(mmSH_STATIC_MEM_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CONFIG", REG_MMIO, 0x25c0, &mmGDS_CONFIG[0], sizeof(mmGDS_CONFIG)/sizeof(mmGDS_CONFIG[0]), 0, 0 },
+	{ "mmGDS_CNTL_STATUS", REG_MMIO, 0x25c1, &mmGDS_CNTL_STATUS[0], sizeof(mmGDS_CNTL_STATUS)/sizeof(mmGDS_CNTL_STATUS[0]), 0, 0 },
+	{ "mmGDS_ENHANCE2", REG_MMIO, 0x25c2, &mmGDS_ENHANCE2[0], sizeof(mmGDS_ENHANCE2)/sizeof(mmGDS_ENHANCE2[0]), 0, 0 },
+	{ "mmGDS_PROTECTION_FAULT", REG_MMIO, 0x25c3, &mmGDS_PROTECTION_FAULT[0], sizeof(mmGDS_PROTECTION_FAULT)/sizeof(mmGDS_PROTECTION_FAULT[0]), 0, 0 },
+	{ "mmGDS_VM_PROTECTION_FAULT", REG_MMIO, 0x25c4, &mmGDS_VM_PROTECTION_FAULT[0], sizeof(mmGDS_VM_PROTECTION_FAULT)/sizeof(mmGDS_VM_PROTECTION_FAULT[0]), 0, 0 },
+	{ "mmGDS_EDC_CNT", REG_MMIO, 0x25c5, &mmGDS_EDC_CNT[0], sizeof(mmGDS_EDC_CNT)/sizeof(mmGDS_EDC_CNT[0]), 0, 0 },
+	{ "mmGDS_EDC_GRBM_CNT", REG_MMIO, 0x25c6, &mmGDS_EDC_GRBM_CNT[0], sizeof(mmGDS_EDC_GRBM_CNT)/sizeof(mmGDS_EDC_GRBM_CNT[0]), 0, 0 },
+	{ "mmGDS_EDC_OA_DED", REG_MMIO, 0x25c7, &mmGDS_EDC_OA_DED[0], sizeof(mmGDS_EDC_OA_DED)/sizeof(mmGDS_EDC_OA_DED[0]), 0, 0 },
+	{ "mmGDS_DEBUG_CNTL", REG_MMIO, 0x25c8, &mmGDS_DEBUG_CNTL[0], sizeof(mmGDS_DEBUG_CNTL)/sizeof(mmGDS_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmGDS_DEBUG_DATA", REG_MMIO, 0x25c9, &mmGDS_DEBUG_DATA[0], sizeof(mmGDS_DEBUG_DATA)/sizeof(mmGDS_DEBUG_DATA[0]), 0, 0 },
+	{ "mmGDS_DSM_CNTL", REG_MMIO, 0x25ca, &mmGDS_DSM_CNTL[0], sizeof(mmGDS_DSM_CNTL)/sizeof(mmGDS_DSM_CNTL[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG31", REG_SMC, 0x26, &ixVGT_DEBUG_REG31[0], sizeof(ixVGT_DEBUG_REG31)/sizeof(ixVGT_DEBUG_REG31[0]), 0, 0 },
+	{ "mmDB_DEBUG", REG_MMIO, 0x260c, &mmDB_DEBUG[0], sizeof(mmDB_DEBUG)/sizeof(mmDB_DEBUG[0]), 0, 0 },
+	{ "mmDB_DEBUG2", REG_MMIO, 0x260d, &mmDB_DEBUG2[0], sizeof(mmDB_DEBUG2)/sizeof(mmDB_DEBUG2[0]), 0, 0 },
+	{ "mmDB_DEBUG3", REG_MMIO, 0x260e, &mmDB_DEBUG3[0], sizeof(mmDB_DEBUG3)/sizeof(mmDB_DEBUG3[0]), 0, 0 },
+	{ "mmDB_DEBUG4", REG_MMIO, 0x260f, &mmDB_DEBUG4[0], sizeof(mmDB_DEBUG4)/sizeof(mmDB_DEBUG4[0]), 0, 0 },
+	{ "mmDB_CREDIT_LIMIT", REG_MMIO, 0x2614, &mmDB_CREDIT_LIMIT[0], sizeof(mmDB_CREDIT_LIMIT)/sizeof(mmDB_CREDIT_LIMIT[0]), 0, 0 },
+	{ "mmDB_WATERMARKS", REG_MMIO, 0x2615, &mmDB_WATERMARKS[0], sizeof(mmDB_WATERMARKS)/sizeof(mmDB_WATERMARKS[0]), 0, 0 },
+	{ "mmDB_SUBTILE_CONTROL", REG_MMIO, 0x2616, &mmDB_SUBTILE_CONTROL[0], sizeof(mmDB_SUBTILE_CONTROL)/sizeof(mmDB_SUBTILE_CONTROL[0]), 0, 0 },
+	{ "mmDB_FREE_CACHELINES", REG_MMIO, 0x2617, &mmDB_FREE_CACHELINES[0], sizeof(mmDB_FREE_CACHELINES)/sizeof(mmDB_FREE_CACHELINES[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH1", REG_MMIO, 0x2618, &mmDB_FIFO_DEPTH1[0], sizeof(mmDB_FIFO_DEPTH1)/sizeof(mmDB_FIFO_DEPTH1[0]), 0, 0 },
+	{ "mmDB_FIFO_DEPTH2", REG_MMIO, 0x2619, &mmDB_FIFO_DEPTH2[0], sizeof(mmDB_FIFO_DEPTH2)/sizeof(mmDB_FIFO_DEPTH2[0]), 0, 0 },
+	{ "mmDB_RING_CONTROL", REG_MMIO, 0x261b, &mmDB_RING_CONTROL[0], sizeof(mmDB_RING_CONTROL)/sizeof(mmDB_RING_CONTROL[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_0", REG_MMIO, 0x2620, &mmDB_READ_DEBUG_0[0], sizeof(mmDB_READ_DEBUG_0)/sizeof(mmDB_READ_DEBUG_0[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_1", REG_MMIO, 0x2621, &mmDB_READ_DEBUG_1[0], sizeof(mmDB_READ_DEBUG_1)/sizeof(mmDB_READ_DEBUG_1[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_2", REG_MMIO, 0x2622, &mmDB_READ_DEBUG_2[0], sizeof(mmDB_READ_DEBUG_2)/sizeof(mmDB_READ_DEBUG_2[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_3", REG_MMIO, 0x2623, &mmDB_READ_DEBUG_3[0], sizeof(mmDB_READ_DEBUG_3)/sizeof(mmDB_READ_DEBUG_3[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_4", REG_MMIO, 0x2624, &mmDB_READ_DEBUG_4[0], sizeof(mmDB_READ_DEBUG_4)/sizeof(mmDB_READ_DEBUG_4[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_5", REG_MMIO, 0x2625, &mmDB_READ_DEBUG_5[0], sizeof(mmDB_READ_DEBUG_5)/sizeof(mmDB_READ_DEBUG_5[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_6", REG_MMIO, 0x2626, &mmDB_READ_DEBUG_6[0], sizeof(mmDB_READ_DEBUG_6)/sizeof(mmDB_READ_DEBUG_6[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_7", REG_MMIO, 0x2627, &mmDB_READ_DEBUG_7[0], sizeof(mmDB_READ_DEBUG_7)/sizeof(mmDB_READ_DEBUG_7[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_8", REG_MMIO, 0x2628, &mmDB_READ_DEBUG_8[0], sizeof(mmDB_READ_DEBUG_8)/sizeof(mmDB_READ_DEBUG_8[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_9", REG_MMIO, 0x2629, &mmDB_READ_DEBUG_9[0], sizeof(mmDB_READ_DEBUG_9)/sizeof(mmDB_READ_DEBUG_9[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_A", REG_MMIO, 0x262a, &mmDB_READ_DEBUG_A[0], sizeof(mmDB_READ_DEBUG_A)/sizeof(mmDB_READ_DEBUG_A[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_B", REG_MMIO, 0x262b, &mmDB_READ_DEBUG_B[0], sizeof(mmDB_READ_DEBUG_B)/sizeof(mmDB_READ_DEBUG_B[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_C", REG_MMIO, 0x262c, &mmDB_READ_DEBUG_C[0], sizeof(mmDB_READ_DEBUG_C)/sizeof(mmDB_READ_DEBUG_C[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_D", REG_MMIO, 0x262d, &mmDB_READ_DEBUG_D[0], sizeof(mmDB_READ_DEBUG_D)/sizeof(mmDB_READ_DEBUG_D[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_E", REG_MMIO, 0x262e, &mmDB_READ_DEBUG_E[0], sizeof(mmDB_READ_DEBUG_E)/sizeof(mmDB_READ_DEBUG_E[0]), 0, 0 },
+	{ "mmDB_READ_DEBUG_F", REG_MMIO, 0x262f, &mmDB_READ_DEBUG_F[0], sizeof(mmDB_READ_DEBUG_F)/sizeof(mmDB_READ_DEBUG_F[0]), 0, 0 },
+	{ "mmCC_RB_REDUNDANCY", REG_MMIO, 0x263c, &mmCC_RB_REDUNDANCY[0], sizeof(mmCC_RB_REDUNDANCY)/sizeof(mmCC_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmCC_RB_BACKEND_DISABLE", REG_MMIO, 0x263d, &mmCC_RB_BACKEND_DISABLE[0], sizeof(mmCC_RB_BACKEND_DISABLE)/sizeof(mmCC_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmGB_ADDR_CONFIG", REG_MMIO, 0x263e, &mmGB_ADDR_CONFIG[0], sizeof(mmGB_ADDR_CONFIG)/sizeof(mmGB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmGB_BACKEND_MAP", REG_MMIO, 0x263f, &mmGB_BACKEND_MAP[0], sizeof(mmGB_BACKEND_MAP)/sizeof(mmGB_BACKEND_MAP[0]), 0, 0 },
+	{ "mmGB_GPU_ID", REG_MMIO, 0x2640, &mmGB_GPU_ID[0], sizeof(mmGB_GPU_ID)/sizeof(mmGB_GPU_ID[0]), 0, 0 },
+	{ "mmCC_RB_DAISY_CHAIN", REG_MMIO, 0x2641, &mmCC_RB_DAISY_CHAIN[0], sizeof(mmCC_RB_DAISY_CHAIN)/sizeof(mmCC_RB_DAISY_CHAIN[0]), 0, 0 },
+	{ "mmGB_TILE_MODE0", REG_MMIO, 0x2644, &mmGB_TILE_MODE0[0], sizeof(mmGB_TILE_MODE0)/sizeof(mmGB_TILE_MODE0[0]), 0, 0 },
+	{ "mmGB_TILE_MODE1", REG_MMIO, 0x2645, &mmGB_TILE_MODE1[0], sizeof(mmGB_TILE_MODE1)/sizeof(mmGB_TILE_MODE1[0]), 0, 0 },
+	{ "mmGB_TILE_MODE2", REG_MMIO, 0x2646, &mmGB_TILE_MODE2[0], sizeof(mmGB_TILE_MODE2)/sizeof(mmGB_TILE_MODE2[0]), 0, 0 },
+	{ "mmGB_TILE_MODE3", REG_MMIO, 0x2647, &mmGB_TILE_MODE3[0], sizeof(mmGB_TILE_MODE3)/sizeof(mmGB_TILE_MODE3[0]), 0, 0 },
+	{ "mmGB_TILE_MODE4", REG_MMIO, 0x2648, &mmGB_TILE_MODE4[0], sizeof(mmGB_TILE_MODE4)/sizeof(mmGB_TILE_MODE4[0]), 0, 0 },
+	{ "mmGB_TILE_MODE5", REG_MMIO, 0x2649, &mmGB_TILE_MODE5[0], sizeof(mmGB_TILE_MODE5)/sizeof(mmGB_TILE_MODE5[0]), 0, 0 },
+	{ "mmGB_TILE_MODE6", REG_MMIO, 0x264a, &mmGB_TILE_MODE6[0], sizeof(mmGB_TILE_MODE6)/sizeof(mmGB_TILE_MODE6[0]), 0, 0 },
+	{ "mmGB_TILE_MODE7", REG_MMIO, 0x264b, &mmGB_TILE_MODE7[0], sizeof(mmGB_TILE_MODE7)/sizeof(mmGB_TILE_MODE7[0]), 0, 0 },
+	{ "mmGB_TILE_MODE8", REG_MMIO, 0x264c, &mmGB_TILE_MODE8[0], sizeof(mmGB_TILE_MODE8)/sizeof(mmGB_TILE_MODE8[0]), 0, 0 },
+	{ "mmGB_TILE_MODE9", REG_MMIO, 0x264d, &mmGB_TILE_MODE9[0], sizeof(mmGB_TILE_MODE9)/sizeof(mmGB_TILE_MODE9[0]), 0, 0 },
+	{ "mmGB_TILE_MODE10", REG_MMIO, 0x264e, &mmGB_TILE_MODE10[0], sizeof(mmGB_TILE_MODE10)/sizeof(mmGB_TILE_MODE10[0]), 0, 0 },
+	{ "mmGB_TILE_MODE11", REG_MMIO, 0x264f, &mmGB_TILE_MODE11[0], sizeof(mmGB_TILE_MODE11)/sizeof(mmGB_TILE_MODE11[0]), 0, 0 },
+	{ "mmGB_TILE_MODE12", REG_MMIO, 0x2650, &mmGB_TILE_MODE12[0], sizeof(mmGB_TILE_MODE12)/sizeof(mmGB_TILE_MODE12[0]), 0, 0 },
+	{ "mmGB_TILE_MODE13", REG_MMIO, 0x2651, &mmGB_TILE_MODE13[0], sizeof(mmGB_TILE_MODE13)/sizeof(mmGB_TILE_MODE13[0]), 0, 0 },
+	{ "mmGB_TILE_MODE14", REG_MMIO, 0x2652, &mmGB_TILE_MODE14[0], sizeof(mmGB_TILE_MODE14)/sizeof(mmGB_TILE_MODE14[0]), 0, 0 },
+	{ "mmGB_TILE_MODE15", REG_MMIO, 0x2653, &mmGB_TILE_MODE15[0], sizeof(mmGB_TILE_MODE15)/sizeof(mmGB_TILE_MODE15[0]), 0, 0 },
+	{ "mmGB_TILE_MODE16", REG_MMIO, 0x2654, &mmGB_TILE_MODE16[0], sizeof(mmGB_TILE_MODE16)/sizeof(mmGB_TILE_MODE16[0]), 0, 0 },
+	{ "mmGB_TILE_MODE17", REG_MMIO, 0x2655, &mmGB_TILE_MODE17[0], sizeof(mmGB_TILE_MODE17)/sizeof(mmGB_TILE_MODE17[0]), 0, 0 },
+	{ "mmGB_TILE_MODE18", REG_MMIO, 0x2656, &mmGB_TILE_MODE18[0], sizeof(mmGB_TILE_MODE18)/sizeof(mmGB_TILE_MODE18[0]), 0, 0 },
+	{ "mmGB_TILE_MODE19", REG_MMIO, 0x2657, &mmGB_TILE_MODE19[0], sizeof(mmGB_TILE_MODE19)/sizeof(mmGB_TILE_MODE19[0]), 0, 0 },
+	{ "mmGB_TILE_MODE20", REG_MMIO, 0x2658, &mmGB_TILE_MODE20[0], sizeof(mmGB_TILE_MODE20)/sizeof(mmGB_TILE_MODE20[0]), 0, 0 },
+	{ "mmGB_TILE_MODE21", REG_MMIO, 0x2659, &mmGB_TILE_MODE21[0], sizeof(mmGB_TILE_MODE21)/sizeof(mmGB_TILE_MODE21[0]), 0, 0 },
+	{ "mmGB_TILE_MODE22", REG_MMIO, 0x265a, &mmGB_TILE_MODE22[0], sizeof(mmGB_TILE_MODE22)/sizeof(mmGB_TILE_MODE22[0]), 0, 0 },
+	{ "mmGB_TILE_MODE23", REG_MMIO, 0x265b, &mmGB_TILE_MODE23[0], sizeof(mmGB_TILE_MODE23)/sizeof(mmGB_TILE_MODE23[0]), 0, 0 },
+	{ "mmGB_TILE_MODE24", REG_MMIO, 0x265c, &mmGB_TILE_MODE24[0], sizeof(mmGB_TILE_MODE24)/sizeof(mmGB_TILE_MODE24[0]), 0, 0 },
+	{ "mmGB_TILE_MODE25", REG_MMIO, 0x265d, &mmGB_TILE_MODE25[0], sizeof(mmGB_TILE_MODE25)/sizeof(mmGB_TILE_MODE25[0]), 0, 0 },
+	{ "mmGB_TILE_MODE26", REG_MMIO, 0x265e, &mmGB_TILE_MODE26[0], sizeof(mmGB_TILE_MODE26)/sizeof(mmGB_TILE_MODE26[0]), 0, 0 },
+	{ "mmGB_TILE_MODE27", REG_MMIO, 0x265f, &mmGB_TILE_MODE27[0], sizeof(mmGB_TILE_MODE27)/sizeof(mmGB_TILE_MODE27[0]), 0, 0 },
+	{ "mmGB_TILE_MODE28", REG_MMIO, 0x2660, &mmGB_TILE_MODE28[0], sizeof(mmGB_TILE_MODE28)/sizeof(mmGB_TILE_MODE28[0]), 0, 0 },
+	{ "mmGB_TILE_MODE29", REG_MMIO, 0x2661, &mmGB_TILE_MODE29[0], sizeof(mmGB_TILE_MODE29)/sizeof(mmGB_TILE_MODE29[0]), 0, 0 },
+	{ "mmGB_TILE_MODE30", REG_MMIO, 0x2662, &mmGB_TILE_MODE30[0], sizeof(mmGB_TILE_MODE30)/sizeof(mmGB_TILE_MODE30[0]), 0, 0 },
+	{ "mmGB_TILE_MODE31", REG_MMIO, 0x2663, &mmGB_TILE_MODE31[0], sizeof(mmGB_TILE_MODE31)/sizeof(mmGB_TILE_MODE31[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE0", REG_MMIO, 0x2664, &mmGB_MACROTILE_MODE0[0], sizeof(mmGB_MACROTILE_MODE0)/sizeof(mmGB_MACROTILE_MODE0[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE1", REG_MMIO, 0x2665, &mmGB_MACROTILE_MODE1[0], sizeof(mmGB_MACROTILE_MODE1)/sizeof(mmGB_MACROTILE_MODE1[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE2", REG_MMIO, 0x2666, &mmGB_MACROTILE_MODE2[0], sizeof(mmGB_MACROTILE_MODE2)/sizeof(mmGB_MACROTILE_MODE2[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE3", REG_MMIO, 0x2667, &mmGB_MACROTILE_MODE3[0], sizeof(mmGB_MACROTILE_MODE3)/sizeof(mmGB_MACROTILE_MODE3[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE4", REG_MMIO, 0x2668, &mmGB_MACROTILE_MODE4[0], sizeof(mmGB_MACROTILE_MODE4)/sizeof(mmGB_MACROTILE_MODE4[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE5", REG_MMIO, 0x2669, &mmGB_MACROTILE_MODE5[0], sizeof(mmGB_MACROTILE_MODE5)/sizeof(mmGB_MACROTILE_MODE5[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE6", REG_MMIO, 0x266a, &mmGB_MACROTILE_MODE6[0], sizeof(mmGB_MACROTILE_MODE6)/sizeof(mmGB_MACROTILE_MODE6[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE7", REG_MMIO, 0x266b, &mmGB_MACROTILE_MODE7[0], sizeof(mmGB_MACROTILE_MODE7)/sizeof(mmGB_MACROTILE_MODE7[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE8", REG_MMIO, 0x266c, &mmGB_MACROTILE_MODE8[0], sizeof(mmGB_MACROTILE_MODE8)/sizeof(mmGB_MACROTILE_MODE8[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE9", REG_MMIO, 0x266d, &mmGB_MACROTILE_MODE9[0], sizeof(mmGB_MACROTILE_MODE9)/sizeof(mmGB_MACROTILE_MODE9[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE10", REG_MMIO, 0x266e, &mmGB_MACROTILE_MODE10[0], sizeof(mmGB_MACROTILE_MODE10)/sizeof(mmGB_MACROTILE_MODE10[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE11", REG_MMIO, 0x266f, &mmGB_MACROTILE_MODE11[0], sizeof(mmGB_MACROTILE_MODE11)/sizeof(mmGB_MACROTILE_MODE11[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE12", REG_MMIO, 0x2670, &mmGB_MACROTILE_MODE12[0], sizeof(mmGB_MACROTILE_MODE12)/sizeof(mmGB_MACROTILE_MODE12[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE13", REG_MMIO, 0x2671, &mmGB_MACROTILE_MODE13[0], sizeof(mmGB_MACROTILE_MODE13)/sizeof(mmGB_MACROTILE_MODE13[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE14", REG_MMIO, 0x2672, &mmGB_MACROTILE_MODE14[0], sizeof(mmGB_MACROTILE_MODE14)/sizeof(mmGB_MACROTILE_MODE14[0]), 0, 0 },
+	{ "mmGB_MACROTILE_MODE15", REG_MMIO, 0x2673, &mmGB_MACROTILE_MODE15[0], sizeof(mmGB_MACROTILE_MODE15)/sizeof(mmGB_MACROTILE_MODE15[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_3", REG_MMIO, 0x2683, &mmCB_HW_CONTROL_3[0], sizeof(mmCB_HW_CONTROL_3)/sizeof(mmCB_HW_CONTROL_3[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL", REG_MMIO, 0x2684, &mmCB_HW_CONTROL[0], sizeof(mmCB_HW_CONTROL)/sizeof(mmCB_HW_CONTROL[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_1", REG_MMIO, 0x2685, &mmCB_HW_CONTROL_1[0], sizeof(mmCB_HW_CONTROL_1)/sizeof(mmCB_HW_CONTROL_1[0]), 0, 0 },
+	{ "mmCB_HW_CONTROL_2", REG_MMIO, 0x2686, &mmCB_HW_CONTROL_2[0], sizeof(mmCB_HW_CONTROL_2)/sizeof(mmCB_HW_CONTROL_2[0]), 0, 0 },
+	{ "mmCB_DCC_CONFIG", REG_MMIO, 0x2687, &mmCB_DCC_CONFIG[0], sizeof(mmCB_DCC_CONFIG)/sizeof(mmCB_DCC_CONFIG[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_1", REG_MMIO, 0x2699, &mmCB_DEBUG_BUS_1[0], sizeof(mmCB_DEBUG_BUS_1)/sizeof(mmCB_DEBUG_BUS_1[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_2", REG_MMIO, 0x269a, &mmCB_DEBUG_BUS_2[0], sizeof(mmCB_DEBUG_BUS_2)/sizeof(mmCB_DEBUG_BUS_2[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_3", REG_MMIO, 0x269b, &mmCB_DEBUG_BUS_3[0], sizeof(mmCB_DEBUG_BUS_3)/sizeof(mmCB_DEBUG_BUS_3[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_4", REG_MMIO, 0x269c, &mmCB_DEBUG_BUS_4[0], sizeof(mmCB_DEBUG_BUS_4)/sizeof(mmCB_DEBUG_BUS_4[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_5", REG_MMIO, 0x269d, &mmCB_DEBUG_BUS_5[0], sizeof(mmCB_DEBUG_BUS_5)/sizeof(mmCB_DEBUG_BUS_5[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_6", REG_MMIO, 0x269e, &mmCB_DEBUG_BUS_6[0], sizeof(mmCB_DEBUG_BUS_6)/sizeof(mmCB_DEBUG_BUS_6[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_7", REG_MMIO, 0x269f, &mmCB_DEBUG_BUS_7[0], sizeof(mmCB_DEBUG_BUS_7)/sizeof(mmCB_DEBUG_BUS_7[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_8", REG_MMIO, 0x26a0, &mmCB_DEBUG_BUS_8[0], sizeof(mmCB_DEBUG_BUS_8)/sizeof(mmCB_DEBUG_BUS_8[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_9", REG_MMIO, 0x26a1, &mmCB_DEBUG_BUS_9[0], sizeof(mmCB_DEBUG_BUS_9)/sizeof(mmCB_DEBUG_BUS_9[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_10", REG_MMIO, 0x26a2, &mmCB_DEBUG_BUS_10[0], sizeof(mmCB_DEBUG_BUS_10)/sizeof(mmCB_DEBUG_BUS_10[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_11", REG_MMIO, 0x26a3, &mmCB_DEBUG_BUS_11[0], sizeof(mmCB_DEBUG_BUS_11)/sizeof(mmCB_DEBUG_BUS_11[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_12", REG_MMIO, 0x26a4, &mmCB_DEBUG_BUS_12[0], sizeof(mmCB_DEBUG_BUS_12)/sizeof(mmCB_DEBUG_BUS_12[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_13", REG_MMIO, 0x26a5, &mmCB_DEBUG_BUS_13[0], sizeof(mmCB_DEBUG_BUS_13)/sizeof(mmCB_DEBUG_BUS_13[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_14", REG_MMIO, 0x26a6, &mmCB_DEBUG_BUS_14[0], sizeof(mmCB_DEBUG_BUS_14)/sizeof(mmCB_DEBUG_BUS_14[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_15", REG_MMIO, 0x26a7, &mmCB_DEBUG_BUS_15[0], sizeof(mmCB_DEBUG_BUS_15)/sizeof(mmCB_DEBUG_BUS_15[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_16", REG_MMIO, 0x26a8, &mmCB_DEBUG_BUS_16[0], sizeof(mmCB_DEBUG_BUS_16)/sizeof(mmCB_DEBUG_BUS_16[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_17", REG_MMIO, 0x26a9, &mmCB_DEBUG_BUS_17[0], sizeof(mmCB_DEBUG_BUS_17)/sizeof(mmCB_DEBUG_BUS_17[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_18", REG_MMIO, 0x26aa, &mmCB_DEBUG_BUS_18[0], sizeof(mmCB_DEBUG_BUS_18)/sizeof(mmCB_DEBUG_BUS_18[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_19", REG_MMIO, 0x26ab, &mmCB_DEBUG_BUS_19[0], sizeof(mmCB_DEBUG_BUS_19)/sizeof(mmCB_DEBUG_BUS_19[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_20", REG_MMIO, 0x26ac, &mmCB_DEBUG_BUS_20[0], sizeof(mmCB_DEBUG_BUS_20)/sizeof(mmCB_DEBUG_BUS_20[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_21", REG_MMIO, 0x26ad, &mmCB_DEBUG_BUS_21[0], sizeof(mmCB_DEBUG_BUS_21)/sizeof(mmCB_DEBUG_BUS_21[0]), 0, 0 },
+	{ "mmCB_DEBUG_BUS_22", REG_MMIO, 0x26ae, &mmCB_DEBUG_BUS_22[0], sizeof(mmCB_DEBUG_BUS_22)/sizeof(mmCB_DEBUG_BUS_22[0]), 0, 0 },
+	{ "ixSQ_WAVE_TBA_LO", REG_SMC, 0x26c, &ixSQ_WAVE_TBA_LO[0], sizeof(ixSQ_WAVE_TBA_LO)/sizeof(ixSQ_WAVE_TBA_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_TBA_HI", REG_SMC, 0x26d, &ixSQ_WAVE_TBA_HI[0], sizeof(ixSQ_WAVE_TBA_HI)/sizeof(ixSQ_WAVE_TBA_HI[0]), 0, 0 },
+	{ "mmGC_USER_RB_REDUNDANCY", REG_MMIO, 0x26de, &mmGC_USER_RB_REDUNDANCY[0], sizeof(mmGC_USER_RB_REDUNDANCY)/sizeof(mmGC_USER_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmGC_USER_RB_BACKEND_DISABLE", REG_MMIO, 0x26df, &mmGC_USER_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "ixSQ_WAVE_TMA_LO", REG_SMC, 0x26e, &ixSQ_WAVE_TMA_LO[0], sizeof(ixSQ_WAVE_TMA_LO)/sizeof(ixSQ_WAVE_TMA_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_TMA_HI", REG_SMC, 0x26f, &ixSQ_WAVE_TMA_HI[0], sizeof(ixSQ_WAVE_TMA_HI)/sizeof(ixSQ_WAVE_TMA_HI[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG32", REG_SMC, 0x27, &ixVGT_DEBUG_REG32[0], sizeof(ixVGT_DEBUG_REG32)/sizeof(ixVGT_DEBUG_REG32[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP0", REG_SMC, 0x270, &ixSQ_WAVE_TTMP0[0], sizeof(ixSQ_WAVE_TTMP0)/sizeof(ixSQ_WAVE_TTMP0[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP1", REG_SMC, 0x271, &ixSQ_WAVE_TTMP1[0], sizeof(ixSQ_WAVE_TTMP1)/sizeof(ixSQ_WAVE_TTMP1[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP2", REG_SMC, 0x272, &ixSQ_WAVE_TTMP2[0], sizeof(ixSQ_WAVE_TTMP2)/sizeof(ixSQ_WAVE_TTMP2[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP3", REG_SMC, 0x273, &ixSQ_WAVE_TTMP3[0], sizeof(ixSQ_WAVE_TTMP3)/sizeof(ixSQ_WAVE_TTMP3[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP4", REG_SMC, 0x274, &ixSQ_WAVE_TTMP4[0], sizeof(ixSQ_WAVE_TTMP4)/sizeof(ixSQ_WAVE_TTMP4[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP5", REG_SMC, 0x275, &ixSQ_WAVE_TTMP5[0], sizeof(ixSQ_WAVE_TTMP5)/sizeof(ixSQ_WAVE_TTMP5[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP6", REG_SMC, 0x276, &ixSQ_WAVE_TTMP6[0], sizeof(ixSQ_WAVE_TTMP6)/sizeof(ixSQ_WAVE_TTMP6[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP7", REG_SMC, 0x277, &ixSQ_WAVE_TTMP7[0], sizeof(ixSQ_WAVE_TTMP7)/sizeof(ixSQ_WAVE_TTMP7[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP8", REG_SMC, 0x278, &ixSQ_WAVE_TTMP8[0], sizeof(ixSQ_WAVE_TTMP8)/sizeof(ixSQ_WAVE_TTMP8[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP9", REG_SMC, 0x279, &ixSQ_WAVE_TTMP9[0], sizeof(ixSQ_WAVE_TTMP9)/sizeof(ixSQ_WAVE_TTMP9[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP10", REG_SMC, 0x27a, &ixSQ_WAVE_TTMP10[0], sizeof(ixSQ_WAVE_TTMP10)/sizeof(ixSQ_WAVE_TTMP10[0]), 0, 0 },
+	{ "ixSQ_WAVE_TTMP11", REG_SMC, 0x27b, &ixSQ_WAVE_TTMP11[0], sizeof(ixSQ_WAVE_TTMP11)/sizeof(ixSQ_WAVE_TTMP11[0]), 0, 0 },
+	{ "ixSQ_WAVE_M0", REG_SMC, 0x27c, &ixSQ_WAVE_M0[0], sizeof(ixSQ_WAVE_M0)/sizeof(ixSQ_WAVE_M0[0]), 0, 0 },
+	{ "ixSQ_WAVE_EXEC_LO", REG_SMC, 0x27e, &ixSQ_WAVE_EXEC_LO[0], sizeof(ixSQ_WAVE_EXEC_LO)/sizeof(ixSQ_WAVE_EXEC_LO[0]), 0, 0 },
+	{ "ixSQ_WAVE_EXEC_HI", REG_SMC, 0x27f, &ixSQ_WAVE_EXEC_HI[0], sizeof(ixSQ_WAVE_EXEC_HI)/sizeof(ixSQ_WAVE_EXEC_HI[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG33", REG_SMC, 0x28, &ixVGT_DEBUG_REG33[0], sizeof(ixVGT_DEBUG_REG33)/sizeof(ixVGT_DEBUG_REG33[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG34", REG_SMC, 0x29, &ixVGT_DEBUG_REG34[0], sizeof(ixVGT_DEBUG_REG34)/sizeof(ixVGT_DEBUG_REG34[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG36", REG_SMC, 0x2b, &ixVGT_DEBUG_REG36[0], sizeof(ixVGT_DEBUG_REG36)/sizeof(ixVGT_DEBUG_REG36[0]), 0, 0 },
+	{ "mmTCP_INVALIDATE", REG_MMIO, 0x2b00, &mmTCP_INVALIDATE[0], sizeof(mmTCP_INVALIDATE)/sizeof(mmTCP_INVALIDATE[0]), 0, 0 },
+	{ "mmTCP_STATUS", REG_MMIO, 0x2b01, &mmTCP_STATUS[0], sizeof(mmTCP_STATUS)/sizeof(mmTCP_STATUS[0]), 0, 0 },
+	{ "mmTCP_CNTL", REG_MMIO, 0x2b02, &mmTCP_CNTL[0], sizeof(mmTCP_CNTL)/sizeof(mmTCP_CNTL[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_LO", REG_MMIO, 0x2b03, &mmTCP_CHAN_STEER_LO[0], sizeof(mmTCP_CHAN_STEER_LO)/sizeof(mmTCP_CHAN_STEER_LO[0]), 0, 0 },
+	{ "mmTCP_CHAN_STEER_HI", REG_MMIO, 0x2b04, &mmTCP_CHAN_STEER_HI[0], sizeof(mmTCP_CHAN_STEER_HI)/sizeof(mmTCP_CHAN_STEER_HI[0]), 0, 0 },
+	{ "mmTCP_ADDR_CONFIG", REG_MMIO, 0x2b05, &mmTCP_ADDR_CONFIG[0], sizeof(mmTCP_ADDR_CONFIG)/sizeof(mmTCP_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmTCP_CREDIT", REG_MMIO, 0x2b06, &mmTCP_CREDIT[0], sizeof(mmTCP_CREDIT)/sizeof(mmTCP_CREDIT[0]), 0, 0 },
+	{ "mmTCP_BUFFER_ADDR_HASH_CNTL", REG_MMIO, 0x2b16, &mmTCP_BUFFER_ADDR_HASH_CNTL[0], sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL)/sizeof(mmTCP_BUFFER_ADDR_HASH_CNTL[0]), 0, 0 },
+	{ "mmTCP_EDC_CNT", REG_MMIO, 0x2b17, &mmTCP_EDC_CNT[0], sizeof(mmTCP_EDC_CNT)/sizeof(mmTCP_EDC_CNT[0]), 0, 0 },
+	{ "mmTC_CFG_L1_LOAD_POLICY0", REG_MMIO, 0x2b1a, &mmTC_CFG_L1_LOAD_POLICY0[0], sizeof(mmTC_CFG_L1_LOAD_POLICY0)/sizeof(mmTC_CFG_L1_LOAD_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L1_LOAD_POLICY1", REG_MMIO, 0x2b1b, &mmTC_CFG_L1_LOAD_POLICY1[0], sizeof(mmTC_CFG_L1_LOAD_POLICY1)/sizeof(mmTC_CFG_L1_LOAD_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L1_STORE_POLICY", REG_MMIO, 0x2b1c, &mmTC_CFG_L1_STORE_POLICY[0], sizeof(mmTC_CFG_L1_STORE_POLICY)/sizeof(mmTC_CFG_L1_STORE_POLICY[0]), 0, 0 },
+	{ "mmTC_CFG_L2_LOAD_POLICY0", REG_MMIO, 0x2b1d, &mmTC_CFG_L2_LOAD_POLICY0[0], sizeof(mmTC_CFG_L2_LOAD_POLICY0)/sizeof(mmTC_CFG_L2_LOAD_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L2_LOAD_POLICY1", REG_MMIO, 0x2b1e, &mmTC_CFG_L2_LOAD_POLICY1[0], sizeof(mmTC_CFG_L2_LOAD_POLICY1)/sizeof(mmTC_CFG_L2_LOAD_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L2_STORE_POLICY0", REG_MMIO, 0x2b1f, &mmTC_CFG_L2_STORE_POLICY0[0], sizeof(mmTC_CFG_L2_STORE_POLICY0)/sizeof(mmTC_CFG_L2_STORE_POLICY0[0]), 0, 0 },
+	{ "mmTC_CFG_L2_STORE_POLICY1", REG_MMIO, 0x2b20, &mmTC_CFG_L2_STORE_POLICY1[0], sizeof(mmTC_CFG_L2_STORE_POLICY1)/sizeof(mmTC_CFG_L2_STORE_POLICY1[0]), 0, 0 },
+	{ "mmTC_CFG_L2_ATOMIC_POLICY", REG_MMIO, 0x2b21, &mmTC_CFG_L2_ATOMIC_POLICY[0], sizeof(mmTC_CFG_L2_ATOMIC_POLICY)/sizeof(mmTC_CFG_L2_ATOMIC_POLICY[0]), 0, 0 },
+	{ "mmTC_CFG_L1_VOLATILE", REG_MMIO, 0x2b22, &mmTC_CFG_L1_VOLATILE[0], sizeof(mmTC_CFG_L1_VOLATILE)/sizeof(mmTC_CFG_L1_VOLATILE[0]), 0, 0 },
+	{ "mmTC_CFG_L2_VOLATILE", REG_MMIO, 0x2b23, &mmTC_CFG_L2_VOLATILE[0], sizeof(mmTC_CFG_L2_VOLATILE)/sizeof(mmTC_CFG_L2_VOLATILE[0]), 0, 0 },
+	{ "mmTCI_STATUS", REG_MMIO, 0x2b61, &mmTCI_STATUS[0], sizeof(mmTCI_STATUS)/sizeof(mmTCI_STATUS[0]), 0, 0 },
+	{ "mmTCI_CNTL_1", REG_MMIO, 0x2b62, &mmTCI_CNTL_1[0], sizeof(mmTCI_CNTL_1)/sizeof(mmTCI_CNTL_1[0]), 0, 0 },
+	{ "mmTCI_CNTL_2", REG_MMIO, 0x2b63, &mmTCI_CNTL_2[0], sizeof(mmTCI_CNTL_2)/sizeof(mmTCI_CNTL_2[0]), 0, 0 },
+	{ "mmTCC_CTRL", REG_MMIO, 0x2b80, &mmTCC_CTRL[0], sizeof(mmTCC_CTRL)/sizeof(mmTCC_CTRL[0]), 0, 0 },
+	{ "mmTCC_EDC_CNT", REG_MMIO, 0x2b82, &mmTCC_EDC_CNT[0], sizeof(mmTCC_EDC_CNT)/sizeof(mmTCC_EDC_CNT[0]), 0, 0 },
+	{ "mmTCC_REDUNDANCY", REG_MMIO, 0x2b83, &mmTCC_REDUNDANCY[0], sizeof(mmTCC_REDUNDANCY)/sizeof(mmTCC_REDUNDANCY[0]), 0, 0 },
+	{ "mmTCC_EXE_DISABLE", REG_MMIO, 0x2b84, &mmTCC_EXE_DISABLE[0], sizeof(mmTCC_EXE_DISABLE)/sizeof(mmTCC_EXE_DISABLE[0]), 0, 0 },
+	{ "mmTCC_DSM_CNTL", REG_MMIO, 0x2b85, &mmTCC_DSM_CNTL[0], sizeof(mmTCC_DSM_CNTL)/sizeof(mmTCC_DSM_CNTL[0]), 0, 0 },
+	{ "mmTCA_CTRL", REG_MMIO, 0x2bc0, &mmTCA_CTRL[0], sizeof(mmTCA_CTRL)/sizeof(mmTCA_CTRL[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_PS", REG_MMIO, 0x2c00, &mmSPI_SHADER_TBA_LO_PS[0], sizeof(mmSPI_SHADER_TBA_LO_PS)/sizeof(mmSPI_SHADER_TBA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_PS", REG_MMIO, 0x2c01, &mmSPI_SHADER_TBA_HI_PS[0], sizeof(mmSPI_SHADER_TBA_HI_PS)/sizeof(mmSPI_SHADER_TBA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_PS", REG_MMIO, 0x2c02, &mmSPI_SHADER_TMA_LO_PS[0], sizeof(mmSPI_SHADER_TMA_LO_PS)/sizeof(mmSPI_SHADER_TMA_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_PS", REG_MMIO, 0x2c03, &mmSPI_SHADER_TMA_HI_PS[0], sizeof(mmSPI_SHADER_TMA_HI_PS)/sizeof(mmSPI_SHADER_TMA_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_PS", REG_MMIO, 0x2c07, &mmSPI_SHADER_PGM_RSRC3_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_PS)/sizeof(mmSPI_SHADER_PGM_RSRC3_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_PS", REG_MMIO, 0x2c08, &mmSPI_SHADER_PGM_LO_PS[0], sizeof(mmSPI_SHADER_PGM_LO_PS)/sizeof(mmSPI_SHADER_PGM_LO_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_PS", REG_MMIO, 0x2c09, &mmSPI_SHADER_PGM_HI_PS[0], sizeof(mmSPI_SHADER_PGM_HI_PS)/sizeof(mmSPI_SHADER_PGM_HI_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_PS", REG_MMIO, 0x2c0a, &mmSPI_SHADER_PGM_RSRC1_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_PS)/sizeof(mmSPI_SHADER_PGM_RSRC1_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_PS", REG_MMIO, 0x2c0b, &mmSPI_SHADER_PGM_RSRC2_PS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_PS)/sizeof(mmSPI_SHADER_PGM_RSRC2_PS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_0", REG_MMIO, 0x2c0c, &mmSPI_SHADER_USER_DATA_PS_0[0], sizeof(mmSPI_SHADER_USER_DATA_PS_0)/sizeof(mmSPI_SHADER_USER_DATA_PS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_1", REG_MMIO, 0x2c0d, &mmSPI_SHADER_USER_DATA_PS_1[0], sizeof(mmSPI_SHADER_USER_DATA_PS_1)/sizeof(mmSPI_SHADER_USER_DATA_PS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_2", REG_MMIO, 0x2c0e, &mmSPI_SHADER_USER_DATA_PS_2[0], sizeof(mmSPI_SHADER_USER_DATA_PS_2)/sizeof(mmSPI_SHADER_USER_DATA_PS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_3", REG_MMIO, 0x2c0f, &mmSPI_SHADER_USER_DATA_PS_3[0], sizeof(mmSPI_SHADER_USER_DATA_PS_3)/sizeof(mmSPI_SHADER_USER_DATA_PS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_4", REG_MMIO, 0x2c10, &mmSPI_SHADER_USER_DATA_PS_4[0], sizeof(mmSPI_SHADER_USER_DATA_PS_4)/sizeof(mmSPI_SHADER_USER_DATA_PS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_5", REG_MMIO, 0x2c11, &mmSPI_SHADER_USER_DATA_PS_5[0], sizeof(mmSPI_SHADER_USER_DATA_PS_5)/sizeof(mmSPI_SHADER_USER_DATA_PS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_6", REG_MMIO, 0x2c12, &mmSPI_SHADER_USER_DATA_PS_6[0], sizeof(mmSPI_SHADER_USER_DATA_PS_6)/sizeof(mmSPI_SHADER_USER_DATA_PS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_7", REG_MMIO, 0x2c13, &mmSPI_SHADER_USER_DATA_PS_7[0], sizeof(mmSPI_SHADER_USER_DATA_PS_7)/sizeof(mmSPI_SHADER_USER_DATA_PS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_8", REG_MMIO, 0x2c14, &mmSPI_SHADER_USER_DATA_PS_8[0], sizeof(mmSPI_SHADER_USER_DATA_PS_8)/sizeof(mmSPI_SHADER_USER_DATA_PS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_9", REG_MMIO, 0x2c15, &mmSPI_SHADER_USER_DATA_PS_9[0], sizeof(mmSPI_SHADER_USER_DATA_PS_9)/sizeof(mmSPI_SHADER_USER_DATA_PS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_10", REG_MMIO, 0x2c16, &mmSPI_SHADER_USER_DATA_PS_10[0], sizeof(mmSPI_SHADER_USER_DATA_PS_10)/sizeof(mmSPI_SHADER_USER_DATA_PS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_11", REG_MMIO, 0x2c17, &mmSPI_SHADER_USER_DATA_PS_11[0], sizeof(mmSPI_SHADER_USER_DATA_PS_11)/sizeof(mmSPI_SHADER_USER_DATA_PS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_12", REG_MMIO, 0x2c18, &mmSPI_SHADER_USER_DATA_PS_12[0], sizeof(mmSPI_SHADER_USER_DATA_PS_12)/sizeof(mmSPI_SHADER_USER_DATA_PS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_13", REG_MMIO, 0x2c19, &mmSPI_SHADER_USER_DATA_PS_13[0], sizeof(mmSPI_SHADER_USER_DATA_PS_13)/sizeof(mmSPI_SHADER_USER_DATA_PS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_14", REG_MMIO, 0x2c1a, &mmSPI_SHADER_USER_DATA_PS_14[0], sizeof(mmSPI_SHADER_USER_DATA_PS_14)/sizeof(mmSPI_SHADER_USER_DATA_PS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_PS_15", REG_MMIO, 0x2c1b, &mmSPI_SHADER_USER_DATA_PS_15[0], sizeof(mmSPI_SHADER_USER_DATA_PS_15)/sizeof(mmSPI_SHADER_USER_DATA_PS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_VS", REG_MMIO, 0x2c40, &mmSPI_SHADER_TBA_LO_VS[0], sizeof(mmSPI_SHADER_TBA_LO_VS)/sizeof(mmSPI_SHADER_TBA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_VS", REG_MMIO, 0x2c41, &mmSPI_SHADER_TBA_HI_VS[0], sizeof(mmSPI_SHADER_TBA_HI_VS)/sizeof(mmSPI_SHADER_TBA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_VS", REG_MMIO, 0x2c42, &mmSPI_SHADER_TMA_LO_VS[0], sizeof(mmSPI_SHADER_TMA_LO_VS)/sizeof(mmSPI_SHADER_TMA_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_VS", REG_MMIO, 0x2c43, &mmSPI_SHADER_TMA_HI_VS[0], sizeof(mmSPI_SHADER_TMA_HI_VS)/sizeof(mmSPI_SHADER_TMA_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_VS", REG_MMIO, 0x2c46, &mmSPI_SHADER_PGM_RSRC3_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_VS)/sizeof(mmSPI_SHADER_PGM_RSRC3_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_LATE_ALLOC_VS", REG_MMIO, 0x2c47, &mmSPI_SHADER_LATE_ALLOC_VS[0], sizeof(mmSPI_SHADER_LATE_ALLOC_VS)/sizeof(mmSPI_SHADER_LATE_ALLOC_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_VS", REG_MMIO, 0x2c48, &mmSPI_SHADER_PGM_LO_VS[0], sizeof(mmSPI_SHADER_PGM_LO_VS)/sizeof(mmSPI_SHADER_PGM_LO_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_VS", REG_MMIO, 0x2c49, &mmSPI_SHADER_PGM_HI_VS[0], sizeof(mmSPI_SHADER_PGM_HI_VS)/sizeof(mmSPI_SHADER_PGM_HI_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_VS", REG_MMIO, 0x2c4a, &mmSPI_SHADER_PGM_RSRC1_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_VS)/sizeof(mmSPI_SHADER_PGM_RSRC1_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_VS", REG_MMIO, 0x2c4b, &mmSPI_SHADER_PGM_RSRC2_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_0", REG_MMIO, 0x2c4c, &mmSPI_SHADER_USER_DATA_VS_0[0], sizeof(mmSPI_SHADER_USER_DATA_VS_0)/sizeof(mmSPI_SHADER_USER_DATA_VS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_1", REG_MMIO, 0x2c4d, &mmSPI_SHADER_USER_DATA_VS_1[0], sizeof(mmSPI_SHADER_USER_DATA_VS_1)/sizeof(mmSPI_SHADER_USER_DATA_VS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_2", REG_MMIO, 0x2c4e, &mmSPI_SHADER_USER_DATA_VS_2[0], sizeof(mmSPI_SHADER_USER_DATA_VS_2)/sizeof(mmSPI_SHADER_USER_DATA_VS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_3", REG_MMIO, 0x2c4f, &mmSPI_SHADER_USER_DATA_VS_3[0], sizeof(mmSPI_SHADER_USER_DATA_VS_3)/sizeof(mmSPI_SHADER_USER_DATA_VS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_4", REG_MMIO, 0x2c50, &mmSPI_SHADER_USER_DATA_VS_4[0], sizeof(mmSPI_SHADER_USER_DATA_VS_4)/sizeof(mmSPI_SHADER_USER_DATA_VS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_5", REG_MMIO, 0x2c51, &mmSPI_SHADER_USER_DATA_VS_5[0], sizeof(mmSPI_SHADER_USER_DATA_VS_5)/sizeof(mmSPI_SHADER_USER_DATA_VS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_6", REG_MMIO, 0x2c52, &mmSPI_SHADER_USER_DATA_VS_6[0], sizeof(mmSPI_SHADER_USER_DATA_VS_6)/sizeof(mmSPI_SHADER_USER_DATA_VS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_7", REG_MMIO, 0x2c53, &mmSPI_SHADER_USER_DATA_VS_7[0], sizeof(mmSPI_SHADER_USER_DATA_VS_7)/sizeof(mmSPI_SHADER_USER_DATA_VS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_8", REG_MMIO, 0x2c54, &mmSPI_SHADER_USER_DATA_VS_8[0], sizeof(mmSPI_SHADER_USER_DATA_VS_8)/sizeof(mmSPI_SHADER_USER_DATA_VS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_9", REG_MMIO, 0x2c55, &mmSPI_SHADER_USER_DATA_VS_9[0], sizeof(mmSPI_SHADER_USER_DATA_VS_9)/sizeof(mmSPI_SHADER_USER_DATA_VS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_10", REG_MMIO, 0x2c56, &mmSPI_SHADER_USER_DATA_VS_10[0], sizeof(mmSPI_SHADER_USER_DATA_VS_10)/sizeof(mmSPI_SHADER_USER_DATA_VS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_11", REG_MMIO, 0x2c57, &mmSPI_SHADER_USER_DATA_VS_11[0], sizeof(mmSPI_SHADER_USER_DATA_VS_11)/sizeof(mmSPI_SHADER_USER_DATA_VS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_12", REG_MMIO, 0x2c58, &mmSPI_SHADER_USER_DATA_VS_12[0], sizeof(mmSPI_SHADER_USER_DATA_VS_12)/sizeof(mmSPI_SHADER_USER_DATA_VS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_13", REG_MMIO, 0x2c59, &mmSPI_SHADER_USER_DATA_VS_13[0], sizeof(mmSPI_SHADER_USER_DATA_VS_13)/sizeof(mmSPI_SHADER_USER_DATA_VS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_14", REG_MMIO, 0x2c5a, &mmSPI_SHADER_USER_DATA_VS_14[0], sizeof(mmSPI_SHADER_USER_DATA_VS_14)/sizeof(mmSPI_SHADER_USER_DATA_VS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_VS_15", REG_MMIO, 0x2c5b, &mmSPI_SHADER_USER_DATA_VS_15[0], sizeof(mmSPI_SHADER_USER_DATA_VS_15)/sizeof(mmSPI_SHADER_USER_DATA_VS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES_VS", REG_MMIO, 0x2c7c, &mmSPI_SHADER_PGM_RSRC2_ES_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_VS", REG_MMIO, 0x2c7d, &mmSPI_SHADER_PGM_RSRC2_LS_VS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_VS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_VS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_GS", REG_MMIO, 0x2c80, &mmSPI_SHADER_TBA_LO_GS[0], sizeof(mmSPI_SHADER_TBA_LO_GS)/sizeof(mmSPI_SHADER_TBA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_GS", REG_MMIO, 0x2c81, &mmSPI_SHADER_TBA_HI_GS[0], sizeof(mmSPI_SHADER_TBA_HI_GS)/sizeof(mmSPI_SHADER_TBA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_GS", REG_MMIO, 0x2c82, &mmSPI_SHADER_TMA_LO_GS[0], sizeof(mmSPI_SHADER_TMA_LO_GS)/sizeof(mmSPI_SHADER_TMA_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_GS", REG_MMIO, 0x2c83, &mmSPI_SHADER_TMA_HI_GS[0], sizeof(mmSPI_SHADER_TMA_HI_GS)/sizeof(mmSPI_SHADER_TMA_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_GS", REG_MMIO, 0x2c87, &mmSPI_SHADER_PGM_RSRC3_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_GS)/sizeof(mmSPI_SHADER_PGM_RSRC3_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_GS", REG_MMIO, 0x2c88, &mmSPI_SHADER_PGM_LO_GS[0], sizeof(mmSPI_SHADER_PGM_LO_GS)/sizeof(mmSPI_SHADER_PGM_LO_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_GS", REG_MMIO, 0x2c89, &mmSPI_SHADER_PGM_HI_GS[0], sizeof(mmSPI_SHADER_PGM_HI_GS)/sizeof(mmSPI_SHADER_PGM_HI_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_GS", REG_MMIO, 0x2c8a, &mmSPI_SHADER_PGM_RSRC1_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_GS)/sizeof(mmSPI_SHADER_PGM_RSRC1_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_GS", REG_MMIO, 0x2c8b, &mmSPI_SHADER_PGM_RSRC2_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_0", REG_MMIO, 0x2c8c, &mmSPI_SHADER_USER_DATA_GS_0[0], sizeof(mmSPI_SHADER_USER_DATA_GS_0)/sizeof(mmSPI_SHADER_USER_DATA_GS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_1", REG_MMIO, 0x2c8d, &mmSPI_SHADER_USER_DATA_GS_1[0], sizeof(mmSPI_SHADER_USER_DATA_GS_1)/sizeof(mmSPI_SHADER_USER_DATA_GS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_2", REG_MMIO, 0x2c8e, &mmSPI_SHADER_USER_DATA_GS_2[0], sizeof(mmSPI_SHADER_USER_DATA_GS_2)/sizeof(mmSPI_SHADER_USER_DATA_GS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_3", REG_MMIO, 0x2c8f, &mmSPI_SHADER_USER_DATA_GS_3[0], sizeof(mmSPI_SHADER_USER_DATA_GS_3)/sizeof(mmSPI_SHADER_USER_DATA_GS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_4", REG_MMIO, 0x2c90, &mmSPI_SHADER_USER_DATA_GS_4[0], sizeof(mmSPI_SHADER_USER_DATA_GS_4)/sizeof(mmSPI_SHADER_USER_DATA_GS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_5", REG_MMIO, 0x2c91, &mmSPI_SHADER_USER_DATA_GS_5[0], sizeof(mmSPI_SHADER_USER_DATA_GS_5)/sizeof(mmSPI_SHADER_USER_DATA_GS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_6", REG_MMIO, 0x2c92, &mmSPI_SHADER_USER_DATA_GS_6[0], sizeof(mmSPI_SHADER_USER_DATA_GS_6)/sizeof(mmSPI_SHADER_USER_DATA_GS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_7", REG_MMIO, 0x2c93, &mmSPI_SHADER_USER_DATA_GS_7[0], sizeof(mmSPI_SHADER_USER_DATA_GS_7)/sizeof(mmSPI_SHADER_USER_DATA_GS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_8", REG_MMIO, 0x2c94, &mmSPI_SHADER_USER_DATA_GS_8[0], sizeof(mmSPI_SHADER_USER_DATA_GS_8)/sizeof(mmSPI_SHADER_USER_DATA_GS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_9", REG_MMIO, 0x2c95, &mmSPI_SHADER_USER_DATA_GS_9[0], sizeof(mmSPI_SHADER_USER_DATA_GS_9)/sizeof(mmSPI_SHADER_USER_DATA_GS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_10", REG_MMIO, 0x2c96, &mmSPI_SHADER_USER_DATA_GS_10[0], sizeof(mmSPI_SHADER_USER_DATA_GS_10)/sizeof(mmSPI_SHADER_USER_DATA_GS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_11", REG_MMIO, 0x2c97, &mmSPI_SHADER_USER_DATA_GS_11[0], sizeof(mmSPI_SHADER_USER_DATA_GS_11)/sizeof(mmSPI_SHADER_USER_DATA_GS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_12", REG_MMIO, 0x2c98, &mmSPI_SHADER_USER_DATA_GS_12[0], sizeof(mmSPI_SHADER_USER_DATA_GS_12)/sizeof(mmSPI_SHADER_USER_DATA_GS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_13", REG_MMIO, 0x2c99, &mmSPI_SHADER_USER_DATA_GS_13[0], sizeof(mmSPI_SHADER_USER_DATA_GS_13)/sizeof(mmSPI_SHADER_USER_DATA_GS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_14", REG_MMIO, 0x2c9a, &mmSPI_SHADER_USER_DATA_GS_14[0], sizeof(mmSPI_SHADER_USER_DATA_GS_14)/sizeof(mmSPI_SHADER_USER_DATA_GS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_GS_15", REG_MMIO, 0x2c9b, &mmSPI_SHADER_USER_DATA_GS_15[0], sizeof(mmSPI_SHADER_USER_DATA_GS_15)/sizeof(mmSPI_SHADER_USER_DATA_GS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES_GS", REG_MMIO, 0x2cbc, &mmSPI_SHADER_PGM_RSRC2_ES_GS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES_GS)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES_GS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_ES", REG_MMIO, 0x2cc0, &mmSPI_SHADER_TBA_LO_ES[0], sizeof(mmSPI_SHADER_TBA_LO_ES)/sizeof(mmSPI_SHADER_TBA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_ES", REG_MMIO, 0x2cc1, &mmSPI_SHADER_TBA_HI_ES[0], sizeof(mmSPI_SHADER_TBA_HI_ES)/sizeof(mmSPI_SHADER_TBA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_ES", REG_MMIO, 0x2cc2, &mmSPI_SHADER_TMA_LO_ES[0], sizeof(mmSPI_SHADER_TMA_LO_ES)/sizeof(mmSPI_SHADER_TMA_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_ES", REG_MMIO, 0x2cc3, &mmSPI_SHADER_TMA_HI_ES[0], sizeof(mmSPI_SHADER_TMA_HI_ES)/sizeof(mmSPI_SHADER_TMA_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_ES", REG_MMIO, 0x2cc7, &mmSPI_SHADER_PGM_RSRC3_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC3_ES)/sizeof(mmSPI_SHADER_PGM_RSRC3_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_ES", REG_MMIO, 0x2cc8, &mmSPI_SHADER_PGM_LO_ES[0], sizeof(mmSPI_SHADER_PGM_LO_ES)/sizeof(mmSPI_SHADER_PGM_LO_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_ES", REG_MMIO, 0x2cc9, &mmSPI_SHADER_PGM_HI_ES[0], sizeof(mmSPI_SHADER_PGM_HI_ES)/sizeof(mmSPI_SHADER_PGM_HI_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_ES", REG_MMIO, 0x2cca, &mmSPI_SHADER_PGM_RSRC1_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC1_ES)/sizeof(mmSPI_SHADER_PGM_RSRC1_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_ES", REG_MMIO, 0x2ccb, &mmSPI_SHADER_PGM_RSRC2_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_0", REG_MMIO, 0x2ccc, &mmSPI_SHADER_USER_DATA_ES_0[0], sizeof(mmSPI_SHADER_USER_DATA_ES_0)/sizeof(mmSPI_SHADER_USER_DATA_ES_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_1", REG_MMIO, 0x2ccd, &mmSPI_SHADER_USER_DATA_ES_1[0], sizeof(mmSPI_SHADER_USER_DATA_ES_1)/sizeof(mmSPI_SHADER_USER_DATA_ES_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_2", REG_MMIO, 0x2cce, &mmSPI_SHADER_USER_DATA_ES_2[0], sizeof(mmSPI_SHADER_USER_DATA_ES_2)/sizeof(mmSPI_SHADER_USER_DATA_ES_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_3", REG_MMIO, 0x2ccf, &mmSPI_SHADER_USER_DATA_ES_3[0], sizeof(mmSPI_SHADER_USER_DATA_ES_3)/sizeof(mmSPI_SHADER_USER_DATA_ES_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_4", REG_MMIO, 0x2cd0, &mmSPI_SHADER_USER_DATA_ES_4[0], sizeof(mmSPI_SHADER_USER_DATA_ES_4)/sizeof(mmSPI_SHADER_USER_DATA_ES_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_5", REG_MMIO, 0x2cd1, &mmSPI_SHADER_USER_DATA_ES_5[0], sizeof(mmSPI_SHADER_USER_DATA_ES_5)/sizeof(mmSPI_SHADER_USER_DATA_ES_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_6", REG_MMIO, 0x2cd2, &mmSPI_SHADER_USER_DATA_ES_6[0], sizeof(mmSPI_SHADER_USER_DATA_ES_6)/sizeof(mmSPI_SHADER_USER_DATA_ES_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_7", REG_MMIO, 0x2cd3, &mmSPI_SHADER_USER_DATA_ES_7[0], sizeof(mmSPI_SHADER_USER_DATA_ES_7)/sizeof(mmSPI_SHADER_USER_DATA_ES_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_8", REG_MMIO, 0x2cd4, &mmSPI_SHADER_USER_DATA_ES_8[0], sizeof(mmSPI_SHADER_USER_DATA_ES_8)/sizeof(mmSPI_SHADER_USER_DATA_ES_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_9", REG_MMIO, 0x2cd5, &mmSPI_SHADER_USER_DATA_ES_9[0], sizeof(mmSPI_SHADER_USER_DATA_ES_9)/sizeof(mmSPI_SHADER_USER_DATA_ES_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_10", REG_MMIO, 0x2cd6, &mmSPI_SHADER_USER_DATA_ES_10[0], sizeof(mmSPI_SHADER_USER_DATA_ES_10)/sizeof(mmSPI_SHADER_USER_DATA_ES_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_11", REG_MMIO, 0x2cd7, &mmSPI_SHADER_USER_DATA_ES_11[0], sizeof(mmSPI_SHADER_USER_DATA_ES_11)/sizeof(mmSPI_SHADER_USER_DATA_ES_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_12", REG_MMIO, 0x2cd8, &mmSPI_SHADER_USER_DATA_ES_12[0], sizeof(mmSPI_SHADER_USER_DATA_ES_12)/sizeof(mmSPI_SHADER_USER_DATA_ES_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_13", REG_MMIO, 0x2cd9, &mmSPI_SHADER_USER_DATA_ES_13[0], sizeof(mmSPI_SHADER_USER_DATA_ES_13)/sizeof(mmSPI_SHADER_USER_DATA_ES_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_14", REG_MMIO, 0x2cda, &mmSPI_SHADER_USER_DATA_ES_14[0], sizeof(mmSPI_SHADER_USER_DATA_ES_14)/sizeof(mmSPI_SHADER_USER_DATA_ES_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_ES_15", REG_MMIO, 0x2cdb, &mmSPI_SHADER_USER_DATA_ES_15[0], sizeof(mmSPI_SHADER_USER_DATA_ES_15)/sizeof(mmSPI_SHADER_USER_DATA_ES_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_ES", REG_MMIO, 0x2cfd, &mmSPI_SHADER_PGM_RSRC2_LS_ES[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_ES)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_ES[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_HS", REG_MMIO, 0x2d00, &mmSPI_SHADER_TBA_LO_HS[0], sizeof(mmSPI_SHADER_TBA_LO_HS)/sizeof(mmSPI_SHADER_TBA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_HS", REG_MMIO, 0x2d01, &mmSPI_SHADER_TBA_HI_HS[0], sizeof(mmSPI_SHADER_TBA_HI_HS)/sizeof(mmSPI_SHADER_TBA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_HS", REG_MMIO, 0x2d02, &mmSPI_SHADER_TMA_LO_HS[0], sizeof(mmSPI_SHADER_TMA_LO_HS)/sizeof(mmSPI_SHADER_TMA_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_HS", REG_MMIO, 0x2d03, &mmSPI_SHADER_TMA_HI_HS[0], sizeof(mmSPI_SHADER_TMA_HI_HS)/sizeof(mmSPI_SHADER_TMA_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_HS", REG_MMIO, 0x2d07, &mmSPI_SHADER_PGM_RSRC3_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_HS)/sizeof(mmSPI_SHADER_PGM_RSRC3_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_HS", REG_MMIO, 0x2d08, &mmSPI_SHADER_PGM_LO_HS[0], sizeof(mmSPI_SHADER_PGM_LO_HS)/sizeof(mmSPI_SHADER_PGM_LO_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_HS", REG_MMIO, 0x2d09, &mmSPI_SHADER_PGM_HI_HS[0], sizeof(mmSPI_SHADER_PGM_HI_HS)/sizeof(mmSPI_SHADER_PGM_HI_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_HS", REG_MMIO, 0x2d0a, &mmSPI_SHADER_PGM_RSRC1_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_HS)/sizeof(mmSPI_SHADER_PGM_RSRC1_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_HS", REG_MMIO, 0x2d0b, &mmSPI_SHADER_PGM_RSRC2_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_0", REG_MMIO, 0x2d0c, &mmSPI_SHADER_USER_DATA_HS_0[0], sizeof(mmSPI_SHADER_USER_DATA_HS_0)/sizeof(mmSPI_SHADER_USER_DATA_HS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_1", REG_MMIO, 0x2d0d, &mmSPI_SHADER_USER_DATA_HS_1[0], sizeof(mmSPI_SHADER_USER_DATA_HS_1)/sizeof(mmSPI_SHADER_USER_DATA_HS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_2", REG_MMIO, 0x2d0e, &mmSPI_SHADER_USER_DATA_HS_2[0], sizeof(mmSPI_SHADER_USER_DATA_HS_2)/sizeof(mmSPI_SHADER_USER_DATA_HS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_3", REG_MMIO, 0x2d0f, &mmSPI_SHADER_USER_DATA_HS_3[0], sizeof(mmSPI_SHADER_USER_DATA_HS_3)/sizeof(mmSPI_SHADER_USER_DATA_HS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_4", REG_MMIO, 0x2d10, &mmSPI_SHADER_USER_DATA_HS_4[0], sizeof(mmSPI_SHADER_USER_DATA_HS_4)/sizeof(mmSPI_SHADER_USER_DATA_HS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_5", REG_MMIO, 0x2d11, &mmSPI_SHADER_USER_DATA_HS_5[0], sizeof(mmSPI_SHADER_USER_DATA_HS_5)/sizeof(mmSPI_SHADER_USER_DATA_HS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_6", REG_MMIO, 0x2d12, &mmSPI_SHADER_USER_DATA_HS_6[0], sizeof(mmSPI_SHADER_USER_DATA_HS_6)/sizeof(mmSPI_SHADER_USER_DATA_HS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_7", REG_MMIO, 0x2d13, &mmSPI_SHADER_USER_DATA_HS_7[0], sizeof(mmSPI_SHADER_USER_DATA_HS_7)/sizeof(mmSPI_SHADER_USER_DATA_HS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_8", REG_MMIO, 0x2d14, &mmSPI_SHADER_USER_DATA_HS_8[0], sizeof(mmSPI_SHADER_USER_DATA_HS_8)/sizeof(mmSPI_SHADER_USER_DATA_HS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_9", REG_MMIO, 0x2d15, &mmSPI_SHADER_USER_DATA_HS_9[0], sizeof(mmSPI_SHADER_USER_DATA_HS_9)/sizeof(mmSPI_SHADER_USER_DATA_HS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_10", REG_MMIO, 0x2d16, &mmSPI_SHADER_USER_DATA_HS_10[0], sizeof(mmSPI_SHADER_USER_DATA_HS_10)/sizeof(mmSPI_SHADER_USER_DATA_HS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_11", REG_MMIO, 0x2d17, &mmSPI_SHADER_USER_DATA_HS_11[0], sizeof(mmSPI_SHADER_USER_DATA_HS_11)/sizeof(mmSPI_SHADER_USER_DATA_HS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_12", REG_MMIO, 0x2d18, &mmSPI_SHADER_USER_DATA_HS_12[0], sizeof(mmSPI_SHADER_USER_DATA_HS_12)/sizeof(mmSPI_SHADER_USER_DATA_HS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_13", REG_MMIO, 0x2d19, &mmSPI_SHADER_USER_DATA_HS_13[0], sizeof(mmSPI_SHADER_USER_DATA_HS_13)/sizeof(mmSPI_SHADER_USER_DATA_HS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_14", REG_MMIO, 0x2d1a, &mmSPI_SHADER_USER_DATA_HS_14[0], sizeof(mmSPI_SHADER_USER_DATA_HS_14)/sizeof(mmSPI_SHADER_USER_DATA_HS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_HS_15", REG_MMIO, 0x2d1b, &mmSPI_SHADER_USER_DATA_HS_15[0], sizeof(mmSPI_SHADER_USER_DATA_HS_15)/sizeof(mmSPI_SHADER_USER_DATA_HS_15[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS_HS", REG_MMIO, 0x2d3d, &mmSPI_SHADER_PGM_RSRC2_LS_HS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS_HS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS_HS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_LO_LS", REG_MMIO, 0x2d40, &mmSPI_SHADER_TBA_LO_LS[0], sizeof(mmSPI_SHADER_TBA_LO_LS)/sizeof(mmSPI_SHADER_TBA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TBA_HI_LS", REG_MMIO, 0x2d41, &mmSPI_SHADER_TBA_HI_LS[0], sizeof(mmSPI_SHADER_TBA_HI_LS)/sizeof(mmSPI_SHADER_TBA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_LO_LS", REG_MMIO, 0x2d42, &mmSPI_SHADER_TMA_LO_LS[0], sizeof(mmSPI_SHADER_TMA_LO_LS)/sizeof(mmSPI_SHADER_TMA_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_TMA_HI_LS", REG_MMIO, 0x2d43, &mmSPI_SHADER_TMA_HI_LS[0], sizeof(mmSPI_SHADER_TMA_HI_LS)/sizeof(mmSPI_SHADER_TMA_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC3_LS", REG_MMIO, 0x2d47, &mmSPI_SHADER_PGM_RSRC3_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC3_LS)/sizeof(mmSPI_SHADER_PGM_RSRC3_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_LO_LS", REG_MMIO, 0x2d48, &mmSPI_SHADER_PGM_LO_LS[0], sizeof(mmSPI_SHADER_PGM_LO_LS)/sizeof(mmSPI_SHADER_PGM_LO_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_HI_LS", REG_MMIO, 0x2d49, &mmSPI_SHADER_PGM_HI_LS[0], sizeof(mmSPI_SHADER_PGM_HI_LS)/sizeof(mmSPI_SHADER_PGM_HI_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC1_LS", REG_MMIO, 0x2d4a, &mmSPI_SHADER_PGM_RSRC1_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC1_LS)/sizeof(mmSPI_SHADER_PGM_RSRC1_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_PGM_RSRC2_LS", REG_MMIO, 0x2d4b, &mmSPI_SHADER_PGM_RSRC2_LS[0], sizeof(mmSPI_SHADER_PGM_RSRC2_LS)/sizeof(mmSPI_SHADER_PGM_RSRC2_LS[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_0", REG_MMIO, 0x2d4c, &mmSPI_SHADER_USER_DATA_LS_0[0], sizeof(mmSPI_SHADER_USER_DATA_LS_0)/sizeof(mmSPI_SHADER_USER_DATA_LS_0[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_1", REG_MMIO, 0x2d4d, &mmSPI_SHADER_USER_DATA_LS_1[0], sizeof(mmSPI_SHADER_USER_DATA_LS_1)/sizeof(mmSPI_SHADER_USER_DATA_LS_1[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_2", REG_MMIO, 0x2d4e, &mmSPI_SHADER_USER_DATA_LS_2[0], sizeof(mmSPI_SHADER_USER_DATA_LS_2)/sizeof(mmSPI_SHADER_USER_DATA_LS_2[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_3", REG_MMIO, 0x2d4f, &mmSPI_SHADER_USER_DATA_LS_3[0], sizeof(mmSPI_SHADER_USER_DATA_LS_3)/sizeof(mmSPI_SHADER_USER_DATA_LS_3[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_4", REG_MMIO, 0x2d50, &mmSPI_SHADER_USER_DATA_LS_4[0], sizeof(mmSPI_SHADER_USER_DATA_LS_4)/sizeof(mmSPI_SHADER_USER_DATA_LS_4[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_5", REG_MMIO, 0x2d51, &mmSPI_SHADER_USER_DATA_LS_5[0], sizeof(mmSPI_SHADER_USER_DATA_LS_5)/sizeof(mmSPI_SHADER_USER_DATA_LS_5[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_6", REG_MMIO, 0x2d52, &mmSPI_SHADER_USER_DATA_LS_6[0], sizeof(mmSPI_SHADER_USER_DATA_LS_6)/sizeof(mmSPI_SHADER_USER_DATA_LS_6[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_7", REG_MMIO, 0x2d53, &mmSPI_SHADER_USER_DATA_LS_7[0], sizeof(mmSPI_SHADER_USER_DATA_LS_7)/sizeof(mmSPI_SHADER_USER_DATA_LS_7[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_8", REG_MMIO, 0x2d54, &mmSPI_SHADER_USER_DATA_LS_8[0], sizeof(mmSPI_SHADER_USER_DATA_LS_8)/sizeof(mmSPI_SHADER_USER_DATA_LS_8[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_9", REG_MMIO, 0x2d55, &mmSPI_SHADER_USER_DATA_LS_9[0], sizeof(mmSPI_SHADER_USER_DATA_LS_9)/sizeof(mmSPI_SHADER_USER_DATA_LS_9[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_10", REG_MMIO, 0x2d56, &mmSPI_SHADER_USER_DATA_LS_10[0], sizeof(mmSPI_SHADER_USER_DATA_LS_10)/sizeof(mmSPI_SHADER_USER_DATA_LS_10[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_11", REG_MMIO, 0x2d57, &mmSPI_SHADER_USER_DATA_LS_11[0], sizeof(mmSPI_SHADER_USER_DATA_LS_11)/sizeof(mmSPI_SHADER_USER_DATA_LS_11[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_12", REG_MMIO, 0x2d58, &mmSPI_SHADER_USER_DATA_LS_12[0], sizeof(mmSPI_SHADER_USER_DATA_LS_12)/sizeof(mmSPI_SHADER_USER_DATA_LS_12[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_13", REG_MMIO, 0x2d59, &mmSPI_SHADER_USER_DATA_LS_13[0], sizeof(mmSPI_SHADER_USER_DATA_LS_13)/sizeof(mmSPI_SHADER_USER_DATA_LS_13[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_14", REG_MMIO, 0x2d5a, &mmSPI_SHADER_USER_DATA_LS_14[0], sizeof(mmSPI_SHADER_USER_DATA_LS_14)/sizeof(mmSPI_SHADER_USER_DATA_LS_14[0]), 0, 0 },
+	{ "mmSPI_SHADER_USER_DATA_LS_15", REG_MMIO, 0x2d5b, &mmSPI_SHADER_USER_DATA_LS_15[0], sizeof(mmSPI_SHADER_USER_DATA_LS_15)/sizeof(mmSPI_SHADER_USER_DATA_LS_15[0]), 0, 0 },
+	{ "mmCOMPUTE_DISPATCH_INITIATOR", REG_MMIO, 0x2e00, &mmCOMPUTE_DISPATCH_INITIATOR[0], sizeof(mmCOMPUTE_DISPATCH_INITIATOR)/sizeof(mmCOMPUTE_DISPATCH_INITIATOR[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_X", REG_MMIO, 0x2e01, &mmCOMPUTE_DIM_X[0], sizeof(mmCOMPUTE_DIM_X)/sizeof(mmCOMPUTE_DIM_X[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Y", REG_MMIO, 0x2e02, &mmCOMPUTE_DIM_Y[0], sizeof(mmCOMPUTE_DIM_Y)/sizeof(mmCOMPUTE_DIM_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_DIM_Z", REG_MMIO, 0x2e03, &mmCOMPUTE_DIM_Z[0], sizeof(mmCOMPUTE_DIM_Z)/sizeof(mmCOMPUTE_DIM_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_START_X", REG_MMIO, 0x2e04, &mmCOMPUTE_START_X[0], sizeof(mmCOMPUTE_START_X)/sizeof(mmCOMPUTE_START_X[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Y", REG_MMIO, 0x2e05, &mmCOMPUTE_START_Y[0], sizeof(mmCOMPUTE_START_Y)/sizeof(mmCOMPUTE_START_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_START_Z", REG_MMIO, 0x2e06, &mmCOMPUTE_START_Z[0], sizeof(mmCOMPUTE_START_Z)/sizeof(mmCOMPUTE_START_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_X", REG_MMIO, 0x2e07, &mmCOMPUTE_NUM_THREAD_X[0], sizeof(mmCOMPUTE_NUM_THREAD_X)/sizeof(mmCOMPUTE_NUM_THREAD_X[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Y", REG_MMIO, 0x2e08, &mmCOMPUTE_NUM_THREAD_Y[0], sizeof(mmCOMPUTE_NUM_THREAD_Y)/sizeof(mmCOMPUTE_NUM_THREAD_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_NUM_THREAD_Z", REG_MMIO, 0x2e09, &mmCOMPUTE_NUM_THREAD_Z[0], sizeof(mmCOMPUTE_NUM_THREAD_Z)/sizeof(mmCOMPUTE_NUM_THREAD_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_PIPELINESTAT_ENABLE", REG_MMIO, 0x2e0a, &mmCOMPUTE_PIPELINESTAT_ENABLE[0], sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE)/sizeof(mmCOMPUTE_PIPELINESTAT_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_PERFCOUNT_ENABLE", REG_MMIO, 0x2e0b, &mmCOMPUTE_PERFCOUNT_ENABLE[0], sizeof(mmCOMPUTE_PERFCOUNT_ENABLE)/sizeof(mmCOMPUTE_PERFCOUNT_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_LO", REG_MMIO, 0x2e0c, &mmCOMPUTE_PGM_LO[0], sizeof(mmCOMPUTE_PGM_LO)/sizeof(mmCOMPUTE_PGM_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_HI", REG_MMIO, 0x2e0d, &mmCOMPUTE_PGM_HI[0], sizeof(mmCOMPUTE_PGM_HI)/sizeof(mmCOMPUTE_PGM_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_LO", REG_MMIO, 0x2e0e, &mmCOMPUTE_TBA_LO[0], sizeof(mmCOMPUTE_TBA_LO)/sizeof(mmCOMPUTE_TBA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TBA_HI", REG_MMIO, 0x2e0f, &mmCOMPUTE_TBA_HI[0], sizeof(mmCOMPUTE_TBA_HI)/sizeof(mmCOMPUTE_TBA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_LO", REG_MMIO, 0x2e10, &mmCOMPUTE_TMA_LO[0], sizeof(mmCOMPUTE_TMA_LO)/sizeof(mmCOMPUTE_TMA_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_TMA_HI", REG_MMIO, 0x2e11, &mmCOMPUTE_TMA_HI[0], sizeof(mmCOMPUTE_TMA_HI)/sizeof(mmCOMPUTE_TMA_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC1", REG_MMIO, 0x2e12, &mmCOMPUTE_PGM_RSRC1[0], sizeof(mmCOMPUTE_PGM_RSRC1)/sizeof(mmCOMPUTE_PGM_RSRC1[0]), 0, 0 },
+	{ "mmCOMPUTE_PGM_RSRC2", REG_MMIO, 0x2e13, &mmCOMPUTE_PGM_RSRC2[0], sizeof(mmCOMPUTE_PGM_RSRC2)/sizeof(mmCOMPUTE_PGM_RSRC2[0]), 0, 0 },
+	{ "mmCOMPUTE_VMID", REG_MMIO, 0x2e14, &mmCOMPUTE_VMID[0], sizeof(mmCOMPUTE_VMID)/sizeof(mmCOMPUTE_VMID[0]), 0, 0 },
+	{ "mmCOMPUTE_RESOURCE_LIMITS", REG_MMIO, 0x2e15, &mmCOMPUTE_RESOURCE_LIMITS[0], sizeof(mmCOMPUTE_RESOURCE_LIMITS)/sizeof(mmCOMPUTE_RESOURCE_LIMITS[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE0", REG_MMIO, 0x2e16, &mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE0[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE1", REG_MMIO, 0x2e17, &mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE1[0]), 0, 0 },
+	{ "mmCOMPUTE_TMPRING_SIZE", REG_MMIO, 0x2e18, &mmCOMPUTE_TMPRING_SIZE[0], sizeof(mmCOMPUTE_TMPRING_SIZE)/sizeof(mmCOMPUTE_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE2", REG_MMIO, 0x2e19, &mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE2[0]), 0, 0 },
+	{ "mmCOMPUTE_STATIC_THREAD_MGMT_SE3", REG_MMIO, 0x2e1a, &mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0], sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3)/sizeof(mmCOMPUTE_STATIC_THREAD_MGMT_SE3[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_X", REG_MMIO, 0x2e1b, &mmCOMPUTE_RESTART_X[0], sizeof(mmCOMPUTE_RESTART_X)/sizeof(mmCOMPUTE_RESTART_X[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_Y", REG_MMIO, 0x2e1c, &mmCOMPUTE_RESTART_Y[0], sizeof(mmCOMPUTE_RESTART_Y)/sizeof(mmCOMPUTE_RESTART_Y[0]), 0, 0 },
+	{ "mmCOMPUTE_RESTART_Z", REG_MMIO, 0x2e1d, &mmCOMPUTE_RESTART_Z[0], sizeof(mmCOMPUTE_RESTART_Z)/sizeof(mmCOMPUTE_RESTART_Z[0]), 0, 0 },
+	{ "mmCOMPUTE_THREAD_TRACE_ENABLE", REG_MMIO, 0x2e1e, &mmCOMPUTE_THREAD_TRACE_ENABLE[0], sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE)/sizeof(mmCOMPUTE_THREAD_TRACE_ENABLE[0]), 0, 0 },
+	{ "mmCOMPUTE_MISC_RESERVED", REG_MMIO, 0x2e1f, &mmCOMPUTE_MISC_RESERVED[0], sizeof(mmCOMPUTE_MISC_RESERVED)/sizeof(mmCOMPUTE_MISC_RESERVED[0]), 0, 0 },
+	{ "mmCOMPUTE_DISPATCH_ID", REG_MMIO, 0x2e20, &mmCOMPUTE_DISPATCH_ID[0], sizeof(mmCOMPUTE_DISPATCH_ID)/sizeof(mmCOMPUTE_DISPATCH_ID[0]), 0, 0 },
+	{ "mmCOMPUTE_THREADGROUP_ID", REG_MMIO, 0x2e21, &mmCOMPUTE_THREADGROUP_ID[0], sizeof(mmCOMPUTE_THREADGROUP_ID)/sizeof(mmCOMPUTE_THREADGROUP_ID[0]), 0, 0 },
+	{ "mmCOMPUTE_RELAUNCH", REG_MMIO, 0x2e22, &mmCOMPUTE_RELAUNCH[0], sizeof(mmCOMPUTE_RELAUNCH)/sizeof(mmCOMPUTE_RELAUNCH[0]), 0, 0 },
+	{ "mmCOMPUTE_WAVE_RESTORE_ADDR_LO", REG_MMIO, 0x2e23, &mmCOMPUTE_WAVE_RESTORE_ADDR_LO[0], sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_LO)/sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_LO[0]), 0, 0 },
+	{ "mmCOMPUTE_WAVE_RESTORE_ADDR_HI", REG_MMIO, 0x2e24, &mmCOMPUTE_WAVE_RESTORE_ADDR_HI[0], sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_HI)/sizeof(mmCOMPUTE_WAVE_RESTORE_ADDR_HI[0]), 0, 0 },
+	{ "mmCOMPUTE_WAVE_RESTORE_CONTROL", REG_MMIO, 0x2e25, &mmCOMPUTE_WAVE_RESTORE_CONTROL[0], sizeof(mmCOMPUTE_WAVE_RESTORE_CONTROL)/sizeof(mmCOMPUTE_WAVE_RESTORE_CONTROL[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_0", REG_MMIO, 0x2e40, &mmCOMPUTE_USER_DATA_0[0], sizeof(mmCOMPUTE_USER_DATA_0)/sizeof(mmCOMPUTE_USER_DATA_0[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_1", REG_MMIO, 0x2e41, &mmCOMPUTE_USER_DATA_1[0], sizeof(mmCOMPUTE_USER_DATA_1)/sizeof(mmCOMPUTE_USER_DATA_1[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_2", REG_MMIO, 0x2e42, &mmCOMPUTE_USER_DATA_2[0], sizeof(mmCOMPUTE_USER_DATA_2)/sizeof(mmCOMPUTE_USER_DATA_2[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_3", REG_MMIO, 0x2e43, &mmCOMPUTE_USER_DATA_3[0], sizeof(mmCOMPUTE_USER_DATA_3)/sizeof(mmCOMPUTE_USER_DATA_3[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_4", REG_MMIO, 0x2e44, &mmCOMPUTE_USER_DATA_4[0], sizeof(mmCOMPUTE_USER_DATA_4)/sizeof(mmCOMPUTE_USER_DATA_4[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_5", REG_MMIO, 0x2e45, &mmCOMPUTE_USER_DATA_5[0], sizeof(mmCOMPUTE_USER_DATA_5)/sizeof(mmCOMPUTE_USER_DATA_5[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_6", REG_MMIO, 0x2e46, &mmCOMPUTE_USER_DATA_6[0], sizeof(mmCOMPUTE_USER_DATA_6)/sizeof(mmCOMPUTE_USER_DATA_6[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_7", REG_MMIO, 0x2e47, &mmCOMPUTE_USER_DATA_7[0], sizeof(mmCOMPUTE_USER_DATA_7)/sizeof(mmCOMPUTE_USER_DATA_7[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_8", REG_MMIO, 0x2e48, &mmCOMPUTE_USER_DATA_8[0], sizeof(mmCOMPUTE_USER_DATA_8)/sizeof(mmCOMPUTE_USER_DATA_8[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_9", REG_MMIO, 0x2e49, &mmCOMPUTE_USER_DATA_9[0], sizeof(mmCOMPUTE_USER_DATA_9)/sizeof(mmCOMPUTE_USER_DATA_9[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_10", REG_MMIO, 0x2e4a, &mmCOMPUTE_USER_DATA_10[0], sizeof(mmCOMPUTE_USER_DATA_10)/sizeof(mmCOMPUTE_USER_DATA_10[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_11", REG_MMIO, 0x2e4b, &mmCOMPUTE_USER_DATA_11[0], sizeof(mmCOMPUTE_USER_DATA_11)/sizeof(mmCOMPUTE_USER_DATA_11[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_12", REG_MMIO, 0x2e4c, &mmCOMPUTE_USER_DATA_12[0], sizeof(mmCOMPUTE_USER_DATA_12)/sizeof(mmCOMPUTE_USER_DATA_12[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_13", REG_MMIO, 0x2e4d, &mmCOMPUTE_USER_DATA_13[0], sizeof(mmCOMPUTE_USER_DATA_13)/sizeof(mmCOMPUTE_USER_DATA_13[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_14", REG_MMIO, 0x2e4e, &mmCOMPUTE_USER_DATA_14[0], sizeof(mmCOMPUTE_USER_DATA_14)/sizeof(mmCOMPUTE_USER_DATA_14[0]), 0, 0 },
+	{ "mmCOMPUTE_USER_DATA_15", REG_MMIO, 0x2e4f, &mmCOMPUTE_USER_DATA_15[0], sizeof(mmCOMPUTE_USER_DATA_15)/sizeof(mmCOMPUTE_USER_DATA_15[0]), 0, 0 },
+	{ "mmCOMPUTE_NOWHERE", REG_MMIO, 0x2e7f, &mmCOMPUTE_NOWHERE[0], sizeof(mmCOMPUTE_NOWHERE)/sizeof(mmCOMPUTE_NOWHERE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG03", REG_SMC, 0x3, &ixCLIPPER_DEBUG_REG03[0], sizeof(ixCLIPPER_DEBUG_REG03)/sizeof(ixCLIPPER_DEBUG_REG03[0]), 0, 0 },
+	{ "ixDIDT_SQ_CTRL_OCP", REG_SMC, 0x3, &ixDIDT_SQ_CTRL_OCP[0], sizeof(ixDIDT_SQ_CTRL_OCP)/sizeof(ixDIDT_SQ_CTRL_OCP[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG3", REG_SMC, 0x3, &ixGDS_DEBUG_REG3[0], sizeof(ixGDS_DEBUG_REG3)/sizeof(ixGDS_DEBUG_REG3[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG3", REG_SMC, 0x3, &ixWD_DEBUG_REG3[0], sizeof(ixWD_DEBUG_REG3)/sizeof(ixWD_DEBUG_REG3[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT0_3", REG_SMC, 0x30, &ixDIDT_DB_WEIGHT0_3[0], sizeof(ixDIDT_DB_WEIGHT0_3)/sizeof(ixDIDT_DB_WEIGHT0_3[0]), 0, 0 },
+	{ "mmCP_DFY_CNTL", REG_MMIO, 0x3020, &mmCP_DFY_CNTL[0], sizeof(mmCP_DFY_CNTL)/sizeof(mmCP_DFY_CNTL[0]), 0, 0 },
+	{ "mmCP_DFY_STAT", REG_MMIO, 0x3021, &mmCP_DFY_STAT[0], sizeof(mmCP_DFY_STAT)/sizeof(mmCP_DFY_STAT[0]), 0, 0 },
+	{ "mmCP_DFY_ADDR_HI", REG_MMIO, 0x3022, &mmCP_DFY_ADDR_HI[0], sizeof(mmCP_DFY_ADDR_HI)/sizeof(mmCP_DFY_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DFY_ADDR_LO", REG_MMIO, 0x3023, &mmCP_DFY_ADDR_LO[0], sizeof(mmCP_DFY_ADDR_LO)/sizeof(mmCP_DFY_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_0", REG_MMIO, 0x3024, &mmCP_DFY_DATA_0[0], sizeof(mmCP_DFY_DATA_0)/sizeof(mmCP_DFY_DATA_0[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_1", REG_MMIO, 0x3025, &mmCP_DFY_DATA_1[0], sizeof(mmCP_DFY_DATA_1)/sizeof(mmCP_DFY_DATA_1[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_2", REG_MMIO, 0x3026, &mmCP_DFY_DATA_2[0], sizeof(mmCP_DFY_DATA_2)/sizeof(mmCP_DFY_DATA_2[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_3", REG_MMIO, 0x3027, &mmCP_DFY_DATA_3[0], sizeof(mmCP_DFY_DATA_3)/sizeof(mmCP_DFY_DATA_3[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_4", REG_MMIO, 0x3028, &mmCP_DFY_DATA_4[0], sizeof(mmCP_DFY_DATA_4)/sizeof(mmCP_DFY_DATA_4[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_5", REG_MMIO, 0x3029, &mmCP_DFY_DATA_5[0], sizeof(mmCP_DFY_DATA_5)/sizeof(mmCP_DFY_DATA_5[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_6", REG_MMIO, 0x302a, &mmCP_DFY_DATA_6[0], sizeof(mmCP_DFY_DATA_6)/sizeof(mmCP_DFY_DATA_6[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_7", REG_MMIO, 0x302b, &mmCP_DFY_DATA_7[0], sizeof(mmCP_DFY_DATA_7)/sizeof(mmCP_DFY_DATA_7[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_8", REG_MMIO, 0x302c, &mmCP_DFY_DATA_8[0], sizeof(mmCP_DFY_DATA_8)/sizeof(mmCP_DFY_DATA_8[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_9", REG_MMIO, 0x302d, &mmCP_DFY_DATA_9[0], sizeof(mmCP_DFY_DATA_9)/sizeof(mmCP_DFY_DATA_9[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_10", REG_MMIO, 0x302e, &mmCP_DFY_DATA_10[0], sizeof(mmCP_DFY_DATA_10)/sizeof(mmCP_DFY_DATA_10[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_11", REG_MMIO, 0x302f, &mmCP_DFY_DATA_11[0], sizeof(mmCP_DFY_DATA_11)/sizeof(mmCP_DFY_DATA_11[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_12", REG_MMIO, 0x3030, &mmCP_DFY_DATA_12[0], sizeof(mmCP_DFY_DATA_12)/sizeof(mmCP_DFY_DATA_12[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_13", REG_MMIO, 0x3031, &mmCP_DFY_DATA_13[0], sizeof(mmCP_DFY_DATA_13)/sizeof(mmCP_DFY_DATA_13[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_14", REG_MMIO, 0x3032, &mmCP_DFY_DATA_14[0], sizeof(mmCP_DFY_DATA_14)/sizeof(mmCP_DFY_DATA_14[0]), 0, 0 },
+	{ "mmCP_DFY_DATA_15", REG_MMIO, 0x3033, &mmCP_DFY_DATA_15[0], sizeof(mmCP_DFY_DATA_15)/sizeof(mmCP_DFY_DATA_15[0]), 0, 0 },
+	{ "mmCP_DFY_CMD", REG_MMIO, 0x3034, &mmCP_DFY_CMD[0], sizeof(mmCP_DFY_CMD)/sizeof(mmCP_DFY_CMD[0]), 0, 0 },
+	{ "mmCP_CPC_MGCG_SYNC_CNTL", REG_MMIO, 0x3036, &mmCP_CPC_MGCG_SYNC_CNTL[0], sizeof(mmCP_CPC_MGCG_SYNC_CNTL)/sizeof(mmCP_CPC_MGCG_SYNC_CNTL[0]), 0, 0 },
+	{ "mmCP_ATCL1_CNTL", REG_MMIO, 0x303c, &mmCP_ATCL1_CNTL[0], sizeof(mmCP_ATCL1_CNTL)/sizeof(mmCP_ATCL1_CNTL[0]), 0, 0 },
+	{ "mmCP_RB0_BASE", REG_MMIO, 0x3040, &mmCP_RB0_BASE[0], sizeof(mmCP_RB0_BASE)/sizeof(mmCP_RB0_BASE[0]), 0, 0 },
+	{ "mmCP_RB_BASE", REG_MMIO, 0x3040, &mmCP_RB_BASE[0], sizeof(mmCP_RB_BASE)/sizeof(mmCP_RB_BASE[0]), 0, 0 },
+	{ "mmCP_RB0_CNTL", REG_MMIO, 0x3041, &mmCP_RB0_CNTL[0], sizeof(mmCP_RB0_CNTL)/sizeof(mmCP_RB0_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_CNTL", REG_MMIO, 0x3041, &mmCP_RB_CNTL[0], sizeof(mmCP_RB_CNTL)/sizeof(mmCP_RB_CNTL[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_WR", REG_MMIO, 0x3042, &mmCP_RB_RPTR_WR[0], sizeof(mmCP_RB_RPTR_WR)/sizeof(mmCP_RB_RPTR_WR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB0_RPTR_ADDR[0], sizeof(mmCP_RB0_RPTR_ADDR)/sizeof(mmCP_RB0_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_ADDR", REG_MMIO, 0x3043, &mmCP_RB_RPTR_ADDR[0], sizeof(mmCP_RB_RPTR_ADDR)/sizeof(mmCP_RB_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB0_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB0_RPTR_ADDR_HI[0], sizeof(mmCP_RB0_RPTR_ADDR_HI)/sizeof(mmCP_RB0_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB_RPTR_ADDR_HI", REG_MMIO, 0x3044, &mmCP_RB_RPTR_ADDR_HI[0], sizeof(mmCP_RB_RPTR_ADDR_HI)/sizeof(mmCP_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB0_WPTR", REG_MMIO, 0x3045, &mmCP_RB0_WPTR[0], sizeof(mmCP_RB0_WPTR)/sizeof(mmCP_RB0_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR", REG_MMIO, 0x3045, &mmCP_RB_WPTR[0], sizeof(mmCP_RB_WPTR)/sizeof(mmCP_RB_WPTR[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3046, &mmCP_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_LO)/sizeof(mmCP_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3047, &mmCP_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_RB_WPTR_POLL_ADDR_HI)/sizeof(mmCP_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmGC_PRIV_MODE", REG_MMIO, 0x3048, NULL, 0, 0, 0 },
+	{ "mmCP_INT_CNTL", REG_MMIO, 0x3049, &mmCP_INT_CNTL[0], sizeof(mmCP_INT_CNTL)/sizeof(mmCP_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_INT_STATUS", REG_MMIO, 0x304a, &mmCP_INT_STATUS[0], sizeof(mmCP_INT_STATUS)/sizeof(mmCP_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_DEVICE_ID", REG_MMIO, 0x304b, &mmCP_DEVICE_ID[0], sizeof(mmCP_DEVICE_ID)/sizeof(mmCP_DEVICE_ID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE_PRIORITY_CNTS", REG_MMIO, 0x304c, &mmCP_ME0_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME0_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_RING_PRIORITY_CNTS", REG_MMIO, 0x304c, &mmCP_RING_PRIORITY_CNTS[0], sizeof(mmCP_RING_PRIORITY_CNTS)/sizeof(mmCP_RING_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE0_PRIORITY", REG_MMIO, 0x304d, &mmCP_ME0_PIPE0_PRIORITY[0], sizeof(mmCP_ME0_PIPE0_PRIORITY)/sizeof(mmCP_ME0_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING0_PRIORITY", REG_MMIO, 0x304d, &mmCP_RING0_PRIORITY[0], sizeof(mmCP_RING0_PRIORITY)/sizeof(mmCP_RING0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE1_PRIORITY", REG_MMIO, 0x304e, &mmCP_ME0_PIPE1_PRIORITY[0], sizeof(mmCP_ME0_PIPE1_PRIORITY)/sizeof(mmCP_ME0_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING1_PRIORITY", REG_MMIO, 0x304e, &mmCP_RING1_PRIORITY[0], sizeof(mmCP_RING1_PRIORITY)/sizeof(mmCP_RING1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE2_PRIORITY", REG_MMIO, 0x304f, &mmCP_ME0_PIPE2_PRIORITY[0], sizeof(mmCP_ME0_PIPE2_PRIORITY)/sizeof(mmCP_ME0_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_RING2_PRIORITY", REG_MMIO, 0x304f, &mmCP_RING2_PRIORITY[0], sizeof(mmCP_RING2_PRIORITY)/sizeof(mmCP_RING2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ENDIAN_SWAP", REG_MMIO, 0x3050, &mmCP_ENDIAN_SWAP[0], sizeof(mmCP_ENDIAN_SWAP)/sizeof(mmCP_ENDIAN_SWAP[0]), 0, 0 },
+	{ "mmCP_RB_VMID", REG_MMIO, 0x3051, &mmCP_RB_VMID[0], sizeof(mmCP_RB_VMID)/sizeof(mmCP_RB_VMID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE0_VMID", REG_MMIO, 0x3052, &mmCP_ME0_PIPE0_VMID[0], sizeof(mmCP_ME0_PIPE0_VMID)/sizeof(mmCP_ME0_PIPE0_VMID[0]), 0, 0 },
+	{ "mmCP_ME0_PIPE1_VMID", REG_MMIO, 0x3053, &mmCP_ME0_PIPE1_VMID[0], sizeof(mmCP_ME0_PIPE1_VMID)/sizeof(mmCP_ME0_PIPE1_VMID[0]), 0, 0 },
+	{ "mmCP_RB_DOORBELL_CONTROL", REG_MMIO, 0x3059, &mmCP_RB_DOORBELL_CONTROL[0], sizeof(mmCP_RB_DOORBELL_CONTROL)/sizeof(mmCP_RB_DOORBELL_CONTROL[0]), 0, 0 },
+	{ "mmCP_RB_DOORBELL_RANGE_LOWER", REG_MMIO, 0x305a, &mmCP_RB_DOORBELL_RANGE_LOWER[0], sizeof(mmCP_RB_DOORBELL_RANGE_LOWER)/sizeof(mmCP_RB_DOORBELL_RANGE_LOWER[0]), 0, 0 },
+	{ "mmCP_RB_DOORBELL_RANGE_UPPER", REG_MMIO, 0x305b, &mmCP_RB_DOORBELL_RANGE_UPPER[0], sizeof(mmCP_RB_DOORBELL_RANGE_UPPER)/sizeof(mmCP_RB_DOORBELL_RANGE_UPPER[0]), 0, 0 },
+	{ "mmCP_MEC_DOORBELL_RANGE_LOWER", REG_MMIO, 0x305c, &mmCP_MEC_DOORBELL_RANGE_LOWER[0], sizeof(mmCP_MEC_DOORBELL_RANGE_LOWER)/sizeof(mmCP_MEC_DOORBELL_RANGE_LOWER[0]), 0, 0 },
+	{ "mmCP_MEC_DOORBELL_RANGE_UPPER", REG_MMIO, 0x305d, &mmCP_MEC_DOORBELL_RANGE_UPPER[0], sizeof(mmCP_MEC_DOORBELL_RANGE_UPPER)/sizeof(mmCP_MEC_DOORBELL_RANGE_UPPER[0]), 0, 0 },
+	{ "mmCP_RB1_BASE", REG_MMIO, 0x3060, &mmCP_RB1_BASE[0], sizeof(mmCP_RB1_BASE)/sizeof(mmCP_RB1_BASE[0]), 0, 0 },
+	{ "mmCP_RB1_CNTL", REG_MMIO, 0x3061, &mmCP_RB1_CNTL[0], sizeof(mmCP_RB1_CNTL)/sizeof(mmCP_RB1_CNTL[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR", REG_MMIO, 0x3062, &mmCP_RB1_RPTR_ADDR[0], sizeof(mmCP_RB1_RPTR_ADDR)/sizeof(mmCP_RB1_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB1_RPTR_ADDR_HI", REG_MMIO, 0x3063, &mmCP_RB1_RPTR_ADDR_HI[0], sizeof(mmCP_RB1_RPTR_ADDR_HI)/sizeof(mmCP_RB1_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB1_WPTR", REG_MMIO, 0x3064, &mmCP_RB1_WPTR[0], sizeof(mmCP_RB1_WPTR)/sizeof(mmCP_RB1_WPTR[0]), 0, 0 },
+	{ "mmCP_RB2_BASE", REG_MMIO, 0x3065, &mmCP_RB2_BASE[0], sizeof(mmCP_RB2_BASE)/sizeof(mmCP_RB2_BASE[0]), 0, 0 },
+	{ "mmCP_RB2_CNTL", REG_MMIO, 0x3066, &mmCP_RB2_CNTL[0], sizeof(mmCP_RB2_CNTL)/sizeof(mmCP_RB2_CNTL[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR", REG_MMIO, 0x3067, &mmCP_RB2_RPTR_ADDR[0], sizeof(mmCP_RB2_RPTR_ADDR)/sizeof(mmCP_RB2_RPTR_ADDR[0]), 0, 0 },
+	{ "mmCP_RB2_RPTR_ADDR_HI", REG_MMIO, 0x3068, &mmCP_RB2_RPTR_ADDR_HI[0], sizeof(mmCP_RB2_RPTR_ADDR_HI)/sizeof(mmCP_RB2_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_RB2_WPTR", REG_MMIO, 0x3069, &mmCP_RB2_WPTR[0], sizeof(mmCP_RB2_WPTR)/sizeof(mmCP_RB2_WPTR[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING0", REG_MMIO, 0x306a, &mmCP_INT_CNTL_RING0[0], sizeof(mmCP_INT_CNTL_RING0)/sizeof(mmCP_INT_CNTL_RING0[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING1", REG_MMIO, 0x306b, &mmCP_INT_CNTL_RING1[0], sizeof(mmCP_INT_CNTL_RING1)/sizeof(mmCP_INT_CNTL_RING1[0]), 0, 0 },
+	{ "mmCP_INT_CNTL_RING2", REG_MMIO, 0x306c, &mmCP_INT_CNTL_RING2[0], sizeof(mmCP_INT_CNTL_RING2)/sizeof(mmCP_INT_CNTL_RING2[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING0", REG_MMIO, 0x306d, &mmCP_INT_STATUS_RING0[0], sizeof(mmCP_INT_STATUS_RING0)/sizeof(mmCP_INT_STATUS_RING0[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING1", REG_MMIO, 0x306e, &mmCP_INT_STATUS_RING1[0], sizeof(mmCP_INT_STATUS_RING1)/sizeof(mmCP_INT_STATUS_RING1[0]), 0, 0 },
+	{ "mmCP_INT_STATUS_RING2", REG_MMIO, 0x306f, &mmCP_INT_STATUS_RING2[0], sizeof(mmCP_INT_STATUS_RING2)/sizeof(mmCP_INT_STATUS_RING2[0]), 0, 0 },
+	{ "mmCP_PWR_CNTL", REG_MMIO, 0x3078, &mmCP_PWR_CNTL[0], sizeof(mmCP_PWR_CNTL)/sizeof(mmCP_PWR_CNTL[0]), 0, 0 },
+	{ "mmCP_MEM_SLP_CNTL", REG_MMIO, 0x3079, &mmCP_MEM_SLP_CNTL[0], sizeof(mmCP_MEM_SLP_CNTL)/sizeof(mmCP_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE", REG_MMIO, 0x307a, &mmCP_ECC_FIRSTOCCURRENCE[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE)/sizeof(mmCP_ECC_FIRSTOCCURRENCE[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING0", REG_MMIO, 0x307b, &mmCP_ECC_FIRSTOCCURRENCE_RING0[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING0[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING1", REG_MMIO, 0x307c, &mmCP_ECC_FIRSTOCCURRENCE_RING1[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING1[0]), 0, 0 },
+	{ "mmCP_ECC_FIRSTOCCURRENCE_RING2", REG_MMIO, 0x307d, &mmCP_ECC_FIRSTOCCURRENCE_RING2[0], sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2)/sizeof(mmCP_ECC_FIRSTOCCURRENCE_RING2[0]), 0, 0 },
+	{ "mmGB_EDC_MODE", REG_MMIO, 0x307e, &mmGB_EDC_MODE[0], sizeof(mmGB_EDC_MODE)/sizeof(mmGB_EDC_MODE[0]), 0, 0 },
+	{ "mmCP_CPF_DEBUG", REG_MMIO, 0x3080, NULL, 0, 0, 0 },
+	{ "mmCP_PQ_WPTR_POLL_CNTL", REG_MMIO, 0x3083, &mmCP_PQ_WPTR_POLL_CNTL[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL)/sizeof(mmCP_PQ_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmCP_PQ_WPTR_POLL_CNTL1", REG_MMIO, 0x3084, &mmCP_PQ_WPTR_POLL_CNTL1[0], sizeof(mmCP_PQ_WPTR_POLL_CNTL1)/sizeof(mmCP_PQ_WPTR_POLL_CNTL1[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_INT_CNTL", REG_MMIO, 0x3085, &mmCP_ME1_PIPE0_INT_CNTL[0], sizeof(mmCP_ME1_PIPE0_INT_CNTL)/sizeof(mmCP_ME1_PIPE0_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_INT_CNTL", REG_MMIO, 0x3086, &mmCP_ME1_PIPE1_INT_CNTL[0], sizeof(mmCP_ME1_PIPE1_INT_CNTL)/sizeof(mmCP_ME1_PIPE1_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_INT_CNTL", REG_MMIO, 0x3087, &mmCP_ME1_PIPE2_INT_CNTL[0], sizeof(mmCP_ME1_PIPE2_INT_CNTL)/sizeof(mmCP_ME1_PIPE2_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_INT_CNTL", REG_MMIO, 0x3088, &mmCP_ME1_PIPE3_INT_CNTL[0], sizeof(mmCP_ME1_PIPE3_INT_CNTL)/sizeof(mmCP_ME1_PIPE3_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_INT_CNTL", REG_MMIO, 0x3089, &mmCP_ME2_PIPE0_INT_CNTL[0], sizeof(mmCP_ME2_PIPE0_INT_CNTL)/sizeof(mmCP_ME2_PIPE0_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_INT_CNTL", REG_MMIO, 0x308a, &mmCP_ME2_PIPE1_INT_CNTL[0], sizeof(mmCP_ME2_PIPE1_INT_CNTL)/sizeof(mmCP_ME2_PIPE1_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_INT_CNTL", REG_MMIO, 0x308b, &mmCP_ME2_PIPE2_INT_CNTL[0], sizeof(mmCP_ME2_PIPE2_INT_CNTL)/sizeof(mmCP_ME2_PIPE2_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_INT_CNTL", REG_MMIO, 0x308c, &mmCP_ME2_PIPE3_INT_CNTL[0], sizeof(mmCP_ME2_PIPE3_INT_CNTL)/sizeof(mmCP_ME2_PIPE3_INT_CNTL[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_INT_STATUS", REG_MMIO, 0x308d, &mmCP_ME1_PIPE0_INT_STATUS[0], sizeof(mmCP_ME1_PIPE0_INT_STATUS)/sizeof(mmCP_ME1_PIPE0_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_INT_STATUS", REG_MMIO, 0x308e, &mmCP_ME1_PIPE1_INT_STATUS[0], sizeof(mmCP_ME1_PIPE1_INT_STATUS)/sizeof(mmCP_ME1_PIPE1_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_INT_STATUS", REG_MMIO, 0x308f, &mmCP_ME1_PIPE2_INT_STATUS[0], sizeof(mmCP_ME1_PIPE2_INT_STATUS)/sizeof(mmCP_ME1_PIPE2_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_INT_STATUS", REG_MMIO, 0x3090, &mmCP_ME1_PIPE3_INT_STATUS[0], sizeof(mmCP_ME1_PIPE3_INT_STATUS)/sizeof(mmCP_ME1_PIPE3_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_INT_STATUS", REG_MMIO, 0x3091, &mmCP_ME2_PIPE0_INT_STATUS[0], sizeof(mmCP_ME2_PIPE0_INT_STATUS)/sizeof(mmCP_ME2_PIPE0_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_INT_STATUS", REG_MMIO, 0x3092, &mmCP_ME2_PIPE1_INT_STATUS[0], sizeof(mmCP_ME2_PIPE1_INT_STATUS)/sizeof(mmCP_ME2_PIPE1_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_INT_STATUS", REG_MMIO, 0x3093, &mmCP_ME2_PIPE2_INT_STATUS[0], sizeof(mmCP_ME2_PIPE2_INT_STATUS)/sizeof(mmCP_ME2_PIPE2_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_INT_STATUS", REG_MMIO, 0x3094, &mmCP_ME2_PIPE3_INT_STATUS[0], sizeof(mmCP_ME2_PIPE3_INT_STATUS)/sizeof(mmCP_ME2_PIPE3_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_ME1_INT_STAT_DEBUG", REG_MMIO, 0x3095, &mmCP_ME1_INT_STAT_DEBUG[0], sizeof(mmCP_ME1_INT_STAT_DEBUG)/sizeof(mmCP_ME1_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCP_ME2_INT_STAT_DEBUG", REG_MMIO, 0x3096, &mmCP_ME2_INT_STAT_DEBUG[0], sizeof(mmCP_ME2_INT_STAT_DEBUG)/sizeof(mmCP_ME2_INT_STAT_DEBUG[0]), 0, 0 },
+	{ "mmCC_GC_EDC_CONFIG", REG_MMIO, 0x3098, &mmCC_GC_EDC_CONFIG[0], sizeof(mmCC_GC_EDC_CONFIG)/sizeof(mmCC_GC_EDC_CONFIG[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE_PRIORITY_CNTS", REG_MMIO, 0x3099, &mmCP_ME1_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME1_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE0_PRIORITY", REG_MMIO, 0x309a, &mmCP_ME1_PIPE0_PRIORITY[0], sizeof(mmCP_ME1_PIPE0_PRIORITY)/sizeof(mmCP_ME1_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE1_PRIORITY", REG_MMIO, 0x309b, &mmCP_ME1_PIPE1_PRIORITY[0], sizeof(mmCP_ME1_PIPE1_PRIORITY)/sizeof(mmCP_ME1_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE2_PRIORITY", REG_MMIO, 0x309c, &mmCP_ME1_PIPE2_PRIORITY[0], sizeof(mmCP_ME1_PIPE2_PRIORITY)/sizeof(mmCP_ME1_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME1_PIPE3_PRIORITY", REG_MMIO, 0x309d, &mmCP_ME1_PIPE3_PRIORITY[0], sizeof(mmCP_ME1_PIPE3_PRIORITY)/sizeof(mmCP_ME1_PIPE3_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE_PRIORITY_CNTS", REG_MMIO, 0x309e, &mmCP_ME2_PIPE_PRIORITY_CNTS[0], sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS)/sizeof(mmCP_ME2_PIPE_PRIORITY_CNTS[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE0_PRIORITY", REG_MMIO, 0x309f, &mmCP_ME2_PIPE0_PRIORITY[0], sizeof(mmCP_ME2_PIPE0_PRIORITY)/sizeof(mmCP_ME2_PIPE0_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE1_PRIORITY", REG_MMIO, 0x30a0, &mmCP_ME2_PIPE1_PRIORITY[0], sizeof(mmCP_ME2_PIPE1_PRIORITY)/sizeof(mmCP_ME2_PIPE1_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE2_PRIORITY", REG_MMIO, 0x30a1, &mmCP_ME2_PIPE2_PRIORITY[0], sizeof(mmCP_ME2_PIPE2_PRIORITY)/sizeof(mmCP_ME2_PIPE2_PRIORITY[0]), 0, 0 },
+	{ "mmCP_ME2_PIPE3_PRIORITY", REG_MMIO, 0x30a2, &mmCP_ME2_PIPE3_PRIORITY[0], sizeof(mmCP_ME2_PIPE3_PRIORITY)/sizeof(mmCP_ME2_PIPE3_PRIORITY[0]), 0, 0 },
+	{ "mmCP_CE_PRGRM_CNTR_START", REG_MMIO, 0x30a3, &mmCP_CE_PRGRM_CNTR_START[0], sizeof(mmCP_CE_PRGRM_CNTR_START)/sizeof(mmCP_CE_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_PFP_PRGRM_CNTR_START", REG_MMIO, 0x30a4, &mmCP_PFP_PRGRM_CNTR_START[0], sizeof(mmCP_PFP_PRGRM_CNTR_START)/sizeof(mmCP_PFP_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_ME_PRGRM_CNTR_START", REG_MMIO, 0x30a5, &mmCP_ME_PRGRM_CNTR_START[0], sizeof(mmCP_ME_PRGRM_CNTR_START)/sizeof(mmCP_ME_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_MEC1_PRGRM_CNTR_START", REG_MMIO, 0x30a6, &mmCP_MEC1_PRGRM_CNTR_START[0], sizeof(mmCP_MEC1_PRGRM_CNTR_START)/sizeof(mmCP_MEC1_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_MEC2_PRGRM_CNTR_START", REG_MMIO, 0x30a7, &mmCP_MEC2_PRGRM_CNTR_START[0], sizeof(mmCP_MEC2_PRGRM_CNTR_START)/sizeof(mmCP_MEC2_PRGRM_CNTR_START[0]), 0, 0 },
+	{ "mmCP_CE_INTR_ROUTINE_START", REG_MMIO, 0x30a8, &mmCP_CE_INTR_ROUTINE_START[0], sizeof(mmCP_CE_INTR_ROUTINE_START)/sizeof(mmCP_CE_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_PFP_INTR_ROUTINE_START", REG_MMIO, 0x30a9, &mmCP_PFP_INTR_ROUTINE_START[0], sizeof(mmCP_PFP_INTR_ROUTINE_START)/sizeof(mmCP_PFP_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_ME_INTR_ROUTINE_START", REG_MMIO, 0x30aa, &mmCP_ME_INTR_ROUTINE_START[0], sizeof(mmCP_ME_INTR_ROUTINE_START)/sizeof(mmCP_ME_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_MEC1_INTR_ROUTINE_START", REG_MMIO, 0x30ab, &mmCP_MEC1_INTR_ROUTINE_START[0], sizeof(mmCP_MEC1_INTR_ROUTINE_START)/sizeof(mmCP_MEC1_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_MEC2_INTR_ROUTINE_START", REG_MMIO, 0x30ac, &mmCP_MEC2_INTR_ROUTINE_START[0], sizeof(mmCP_MEC2_INTR_ROUTINE_START)/sizeof(mmCP_MEC2_INTR_ROUTINE_START[0]), 0, 0 },
+	{ "mmCP_CONTEXT_CNTL", REG_MMIO, 0x30ad, &mmCP_CONTEXT_CNTL[0], sizeof(mmCP_CONTEXT_CNTL)/sizeof(mmCP_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmCP_MAX_CONTEXT", REG_MMIO, 0x30ae, &mmCP_MAX_CONTEXT[0], sizeof(mmCP_MAX_CONTEXT)/sizeof(mmCP_MAX_CONTEXT[0]), 0, 0 },
+	{ "mmCP_IQ_WAIT_TIME1", REG_MMIO, 0x30af, &mmCP_IQ_WAIT_TIME1[0], sizeof(mmCP_IQ_WAIT_TIME1)/sizeof(mmCP_IQ_WAIT_TIME1[0]), 0, 0 },
+	{ "mmCP_IQ_WAIT_TIME2", REG_MMIO, 0x30b0, &mmCP_IQ_WAIT_TIME2[0], sizeof(mmCP_IQ_WAIT_TIME2)/sizeof(mmCP_IQ_WAIT_TIME2[0]), 0, 0 },
+	{ "mmCP_RB0_BASE_HI", REG_MMIO, 0x30b1, &mmCP_RB0_BASE_HI[0], sizeof(mmCP_RB0_BASE_HI)/sizeof(mmCP_RB0_BASE_HI[0]), 0, 0 },
+	{ "mmCP_RB1_BASE_HI", REG_MMIO, 0x30b2, &mmCP_RB1_BASE_HI[0], sizeof(mmCP_RB1_BASE_HI)/sizeof(mmCP_RB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_VMID_RESET", REG_MMIO, 0x30b3, &mmCP_VMID_RESET[0], sizeof(mmCP_VMID_RESET)/sizeof(mmCP_VMID_RESET[0]), 0, 0 },
+	{ "mmCPC_INT_CNTL", REG_MMIO, 0x30b4, &mmCPC_INT_CNTL[0], sizeof(mmCPC_INT_CNTL)/sizeof(mmCPC_INT_CNTL[0]), 0, 0 },
+	{ "mmCPC_INT_STATUS", REG_MMIO, 0x30b5, &mmCPC_INT_STATUS[0], sizeof(mmCPC_INT_STATUS)/sizeof(mmCPC_INT_STATUS[0]), 0, 0 },
+	{ "mmCP_VMID_PREEMPT", REG_MMIO, 0x30b6, &mmCP_VMID_PREEMPT[0], sizeof(mmCP_VMID_PREEMPT)/sizeof(mmCP_VMID_PREEMPT[0]), 0, 0 },
+	{ "mmCPC_INT_CNTX_ID", REG_MMIO, 0x30b7, &mmCPC_INT_CNTX_ID[0], sizeof(mmCPC_INT_CNTX_ID)/sizeof(mmCPC_INT_CNTX_ID[0]), 0, 0 },
+	{ "mmCP_PQ_STATUS", REG_MMIO, 0x30b8, &mmCP_PQ_STATUS[0], sizeof(mmCP_PQ_STATUS)/sizeof(mmCP_PQ_STATUS[0]), 0, 0 },
+	{ "mmCP_CPC_IC_BASE_LO", REG_MMIO, 0x30b9, &mmCP_CPC_IC_BASE_LO[0], sizeof(mmCP_CPC_IC_BASE_LO)/sizeof(mmCP_CPC_IC_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CPC_IC_BASE_HI", REG_MMIO, 0x30ba, &mmCP_CPC_IC_BASE_HI[0], sizeof(mmCP_CPC_IC_BASE_HI)/sizeof(mmCP_CPC_IC_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CPC_IC_BASE_CNTL", REG_MMIO, 0x30bb, &mmCP_CPC_IC_BASE_CNTL[0], sizeof(mmCP_CPC_IC_BASE_CNTL)/sizeof(mmCP_CPC_IC_BASE_CNTL[0]), 0, 0 },
+	{ "mmCP_CPC_IC_OP_CNTL", REG_MMIO, 0x30bc, &mmCP_CPC_IC_OP_CNTL[0], sizeof(mmCP_CPC_IC_OP_CNTL)/sizeof(mmCP_CPC_IC_OP_CNTL[0]), 0, 0 },
+	{ "mmCP_MEC1_F32_INT_DIS", REG_MMIO, 0x30bd, &mmCP_MEC1_F32_INT_DIS[0], sizeof(mmCP_MEC1_F32_INT_DIS)/sizeof(mmCP_MEC1_F32_INT_DIS[0]), 0, 0 },
+	{ "mmCP_MEC2_F32_INT_DIS", REG_MMIO, 0x30be, &mmCP_MEC2_F32_INT_DIS[0], sizeof(mmCP_MEC2_F32_INT_DIS)/sizeof(mmCP_MEC2_F32_INT_DIS[0]), 0, 0 },
+	{ "mmCP_VMID_STATUS", REG_MMIO, 0x30bf, &mmCP_VMID_STATUS[0], sizeof(mmCP_VMID_STATUS)/sizeof(mmCP_VMID_STATUS[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT4_7", REG_SMC, 0x31, &ixDIDT_DB_WEIGHT4_7[0], sizeof(ixDIDT_DB_WEIGHT4_7)/sizeof(ixDIDT_DB_WEIGHT4_7[0]), 0, 0 },
+	{ "mmSPI_ARB_PRIORITY", REG_MMIO, 0x31c0, &mmSPI_ARB_PRIORITY[0], sizeof(mmSPI_ARB_PRIORITY)/sizeof(mmSPI_ARB_PRIORITY[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_0", REG_MMIO, 0x31c1, &mmSPI_ARB_CYCLES_0[0], sizeof(mmSPI_ARB_CYCLES_0)/sizeof(mmSPI_ARB_CYCLES_0[0]), 0, 0 },
+	{ "mmSPI_ARB_CYCLES_1", REG_MMIO, 0x31c2, &mmSPI_ARB_CYCLES_1[0], sizeof(mmSPI_ARB_CYCLES_1)/sizeof(mmSPI_ARB_CYCLES_1[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_GFX", REG_MMIO, 0x31c3, &mmSPI_CDBG_SYS_GFX[0], sizeof(mmSPI_CDBG_SYS_GFX)/sizeof(mmSPI_CDBG_SYS_GFX[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_HP3D", REG_MMIO, 0x31c4, &mmSPI_CDBG_SYS_HP3D[0], sizeof(mmSPI_CDBG_SYS_HP3D)/sizeof(mmSPI_CDBG_SYS_HP3D[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_CS0", REG_MMIO, 0x31c5, &mmSPI_CDBG_SYS_CS0[0], sizeof(mmSPI_CDBG_SYS_CS0)/sizeof(mmSPI_CDBG_SYS_CS0[0]), 0, 0 },
+	{ "mmSPI_CDBG_SYS_CS1", REG_MMIO, 0x31c6, &mmSPI_CDBG_SYS_CS1[0], sizeof(mmSPI_CDBG_SYS_CS1)/sizeof(mmSPI_CDBG_SYS_CS1[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_GFX", REG_MMIO, 0x31c7, &mmSPI_WCL_PIPE_PERCENT_GFX[0], sizeof(mmSPI_WCL_PIPE_PERCENT_GFX)/sizeof(mmSPI_WCL_PIPE_PERCENT_GFX[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_HP3D", REG_MMIO, 0x31c8, &mmSPI_WCL_PIPE_PERCENT_HP3D[0], sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D)/sizeof(mmSPI_WCL_PIPE_PERCENT_HP3D[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS0", REG_MMIO, 0x31c9, &mmSPI_WCL_PIPE_PERCENT_CS0[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS0)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS0[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS1", REG_MMIO, 0x31ca, &mmSPI_WCL_PIPE_PERCENT_CS1[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS1)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS1[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS2", REG_MMIO, 0x31cb, &mmSPI_WCL_PIPE_PERCENT_CS2[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS2)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS2[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS3", REG_MMIO, 0x31cc, &mmSPI_WCL_PIPE_PERCENT_CS3[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS3)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS3[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS4", REG_MMIO, 0x31cd, &mmSPI_WCL_PIPE_PERCENT_CS4[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS4)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS4[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS5", REG_MMIO, 0x31ce, &mmSPI_WCL_PIPE_PERCENT_CS5[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS5)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS5[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS6", REG_MMIO, 0x31cf, &mmSPI_WCL_PIPE_PERCENT_CS6[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS6)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS6[0]), 0, 0 },
+	{ "mmSPI_WCL_PIPE_PERCENT_CS7", REG_MMIO, 0x31d0, &mmSPI_WCL_PIPE_PERCENT_CS7[0], sizeof(mmSPI_WCL_PIPE_PERCENT_CS7)/sizeof(mmSPI_WCL_PIPE_PERCENT_CS7[0]), 0, 0 },
+	{ "mmSPI_GDBG_WAVE_CNTL", REG_MMIO, 0x31d1, &mmSPI_GDBG_WAVE_CNTL[0], sizeof(mmSPI_GDBG_WAVE_CNTL)/sizeof(mmSPI_GDBG_WAVE_CNTL[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_CONFIG", REG_MMIO, 0x31d2, &mmSPI_GDBG_TRAP_CONFIG[0], sizeof(mmSPI_GDBG_TRAP_CONFIG)/sizeof(mmSPI_GDBG_TRAP_CONFIG[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_MASK", REG_MMIO, 0x31d3, &mmSPI_GDBG_TRAP_MASK[0], sizeof(mmSPI_GDBG_TRAP_MASK)/sizeof(mmSPI_GDBG_TRAP_MASK[0]), 0, 0 },
+	{ "mmSPI_GDBG_TBA_LO", REG_MMIO, 0x31d4, &mmSPI_GDBG_TBA_LO[0], sizeof(mmSPI_GDBG_TBA_LO)/sizeof(mmSPI_GDBG_TBA_LO[0]), 0, 0 },
+	{ "mmSPI_GDBG_TBA_HI", REG_MMIO, 0x31d5, &mmSPI_GDBG_TBA_HI[0], sizeof(mmSPI_GDBG_TBA_HI)/sizeof(mmSPI_GDBG_TBA_HI[0]), 0, 0 },
+	{ "mmSPI_GDBG_TMA_LO", REG_MMIO, 0x31d6, &mmSPI_GDBG_TMA_LO[0], sizeof(mmSPI_GDBG_TMA_LO)/sizeof(mmSPI_GDBG_TMA_LO[0]), 0, 0 },
+	{ "mmSPI_GDBG_TMA_HI", REG_MMIO, 0x31d7, &mmSPI_GDBG_TMA_HI[0], sizeof(mmSPI_GDBG_TMA_HI)/sizeof(mmSPI_GDBG_TMA_HI[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_DATA0", REG_MMIO, 0x31d8, &mmSPI_GDBG_TRAP_DATA0[0], sizeof(mmSPI_GDBG_TRAP_DATA0)/sizeof(mmSPI_GDBG_TRAP_DATA0[0]), 0, 0 },
+	{ "mmSPI_GDBG_TRAP_DATA1", REG_MMIO, 0x31d9, &mmSPI_GDBG_TRAP_DATA1[0], sizeof(mmSPI_GDBG_TRAP_DATA1)/sizeof(mmSPI_GDBG_TRAP_DATA1[0]), 0, 0 },
+	{ "mmSPI_RESET_DEBUG", REG_MMIO, 0x31da, &mmSPI_RESET_DEBUG[0], sizeof(mmSPI_RESET_DEBUG)/sizeof(mmSPI_RESET_DEBUG[0]), 0, 0 },
+	{ "mmSPI_COMPUTE_QUEUE_RESET", REG_MMIO, 0x31db, &mmSPI_COMPUTE_QUEUE_RESET[0], sizeof(mmSPI_COMPUTE_QUEUE_RESET)/sizeof(mmSPI_COMPUTE_QUEUE_RESET[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_0", REG_MMIO, 0x31dc, &mmSPI_RESOURCE_RESERVE_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_CU_0[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_1", REG_MMIO, 0x31dd, &mmSPI_RESOURCE_RESERVE_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_CU_1[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_2", REG_MMIO, 0x31de, &mmSPI_RESOURCE_RESERVE_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_CU_2[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_3", REG_MMIO, 0x31df, &mmSPI_RESOURCE_RESERVE_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_CU_3[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_4", REG_MMIO, 0x31e0, &mmSPI_RESOURCE_RESERVE_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_CU_4[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_5", REG_MMIO, 0x31e1, &mmSPI_RESOURCE_RESERVE_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_CU_5[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_6", REG_MMIO, 0x31e2, &mmSPI_RESOURCE_RESERVE_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_CU_6[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_7", REG_MMIO, 0x31e3, &mmSPI_RESOURCE_RESERVE_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_CU_7[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_8", REG_MMIO, 0x31e4, &mmSPI_RESOURCE_RESERVE_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_CU_8[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_9", REG_MMIO, 0x31e5, &mmSPI_RESOURCE_RESERVE_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_CU_9[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_0", REG_MMIO, 0x31e6, &mmSPI_RESOURCE_RESERVE_EN_CU_0[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_0[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_1", REG_MMIO, 0x31e7, &mmSPI_RESOURCE_RESERVE_EN_CU_1[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_1[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_2", REG_MMIO, 0x31e8, &mmSPI_RESOURCE_RESERVE_EN_CU_2[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_2[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_3", REG_MMIO, 0x31e9, &mmSPI_RESOURCE_RESERVE_EN_CU_3[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_3[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_4", REG_MMIO, 0x31ea, &mmSPI_RESOURCE_RESERVE_EN_CU_4[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_4[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_5", REG_MMIO, 0x31eb, &mmSPI_RESOURCE_RESERVE_EN_CU_5[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_5[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_6", REG_MMIO, 0x31ec, &mmSPI_RESOURCE_RESERVE_EN_CU_6[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_6[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_7", REG_MMIO, 0x31ed, &mmSPI_RESOURCE_RESERVE_EN_CU_7[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_7[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_8", REG_MMIO, 0x31ee, &mmSPI_RESOURCE_RESERVE_EN_CU_8[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_8[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_9", REG_MMIO, 0x31ef, &mmSPI_RESOURCE_RESERVE_EN_CU_9[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_9[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_10", REG_MMIO, 0x31f0, &mmSPI_RESOURCE_RESERVE_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_CU_10[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_11", REG_MMIO, 0x31f1, &mmSPI_RESOURCE_RESERVE_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_CU_11[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_10", REG_MMIO, 0x31f2, &mmSPI_RESOURCE_RESERVE_EN_CU_10[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_10[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_11", REG_MMIO, 0x31f3, &mmSPI_RESOURCE_RESERVE_EN_CU_11[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_11[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_12", REG_MMIO, 0x31f4, &mmSPI_RESOURCE_RESERVE_CU_12[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_12)/sizeof(mmSPI_RESOURCE_RESERVE_CU_12[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_13", REG_MMIO, 0x31f5, &mmSPI_RESOURCE_RESERVE_CU_13[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_13)/sizeof(mmSPI_RESOURCE_RESERVE_CU_13[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_14", REG_MMIO, 0x31f6, &mmSPI_RESOURCE_RESERVE_CU_14[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_14)/sizeof(mmSPI_RESOURCE_RESERVE_CU_14[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_CU_15", REG_MMIO, 0x31f7, &mmSPI_RESOURCE_RESERVE_CU_15[0], sizeof(mmSPI_RESOURCE_RESERVE_CU_15)/sizeof(mmSPI_RESOURCE_RESERVE_CU_15[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_12", REG_MMIO, 0x31f8, &mmSPI_RESOURCE_RESERVE_EN_CU_12[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_12)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_12[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_13", REG_MMIO, 0x31f9, &mmSPI_RESOURCE_RESERVE_EN_CU_13[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_13)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_13[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_14", REG_MMIO, 0x31fa, &mmSPI_RESOURCE_RESERVE_EN_CU_14[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_14)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_14[0]), 0, 0 },
+	{ "mmSPI_RESOURCE_RESERVE_EN_CU_15", REG_MMIO, 0x31fb, &mmSPI_RESOURCE_RESERVE_EN_CU_15[0], sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_15)/sizeof(mmSPI_RESOURCE_RESERVE_EN_CU_15[0]), 0, 0 },
+	{ "mmSPI_COMPUTE_WF_CTX_SAVE", REG_MMIO, 0x31fc, &mmSPI_COMPUTE_WF_CTX_SAVE[0], sizeof(mmSPI_COMPUTE_WF_CTX_SAVE)/sizeof(mmSPI_COMPUTE_WF_CTX_SAVE[0]), 0, 0 },
+	{ "ixDIDT_DB_WEIGHT8_11", REG_SMC, 0x32, &ixDIDT_DB_WEIGHT8_11[0], sizeof(ixDIDT_DB_WEIGHT8_11)/sizeof(ixDIDT_DB_WEIGHT8_11[0]), 0, 0 },
+	{ "mmCP_HPD_ROQ_OFFSETS", REG_MMIO, 0x3240, &mmCP_HPD_ROQ_OFFSETS[0], sizeof(mmCP_HPD_ROQ_OFFSETS)/sizeof(mmCP_HPD_ROQ_OFFSETS[0]), 0, 0 },
+	{ "mmCP_HPD_STATUS0", REG_MMIO, 0x3241, &mmCP_HPD_STATUS0[0], sizeof(mmCP_HPD_STATUS0)/sizeof(mmCP_HPD_STATUS0[0]), 0, 0 },
+	{ "mmCP_MQD_BASE_ADDR", REG_MMIO, 0x3245, &mmCP_MQD_BASE_ADDR[0], sizeof(mmCP_MQD_BASE_ADDR)/sizeof(mmCP_MQD_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_MQD_BASE_ADDR_HI", REG_MMIO, 0x3246, &mmCP_MQD_BASE_ADDR_HI[0], sizeof(mmCP_MQD_BASE_ADDR_HI)/sizeof(mmCP_MQD_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_ACTIVE", REG_MMIO, 0x3247, &mmCP_HQD_ACTIVE[0], sizeof(mmCP_HQD_ACTIVE)/sizeof(mmCP_HQD_ACTIVE[0]), 0, 0 },
+	{ "mmCP_HQD_VMID", REG_MMIO, 0x3248, &mmCP_HQD_VMID[0], sizeof(mmCP_HQD_VMID)/sizeof(mmCP_HQD_VMID[0]), 0, 0 },
+	{ "mmCP_HQD_PERSISTENT_STATE", REG_MMIO, 0x3249, &mmCP_HQD_PERSISTENT_STATE[0], sizeof(mmCP_HQD_PERSISTENT_STATE)/sizeof(mmCP_HQD_PERSISTENT_STATE[0]), 0, 0 },
+	{ "mmCP_HQD_PIPE_PRIORITY", REG_MMIO, 0x324a, &mmCP_HQD_PIPE_PRIORITY[0], sizeof(mmCP_HQD_PIPE_PRIORITY)/sizeof(mmCP_HQD_PIPE_PRIORITY[0]), 0, 0 },
+	{ "mmCP_HQD_QUEUE_PRIORITY", REG_MMIO, 0x324b, &mmCP_HQD_QUEUE_PRIORITY[0], sizeof(mmCP_HQD_QUEUE_PRIORITY)/sizeof(mmCP_HQD_QUEUE_PRIORITY[0]), 0, 0 },
+	{ "mmCP_HQD_QUANTUM", REG_MMIO, 0x324c, &mmCP_HQD_QUANTUM[0], sizeof(mmCP_HQD_QUANTUM)/sizeof(mmCP_HQD_QUANTUM[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_BASE", REG_MMIO, 0x324d, &mmCP_HQD_PQ_BASE[0], sizeof(mmCP_HQD_PQ_BASE)/sizeof(mmCP_HQD_PQ_BASE[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_BASE_HI", REG_MMIO, 0x324e, &mmCP_HQD_PQ_BASE_HI[0], sizeof(mmCP_HQD_PQ_BASE_HI)/sizeof(mmCP_HQD_PQ_BASE_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR", REG_MMIO, 0x324f, &mmCP_HQD_PQ_RPTR[0], sizeof(mmCP_HQD_PQ_RPTR)/sizeof(mmCP_HQD_PQ_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR", REG_MMIO, 0x3250, &mmCP_HQD_PQ_RPTR_REPORT_ADDR[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI", REG_MMIO, 0x3251, &mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0], sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI)/sizeof(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR", REG_MMIO, 0x3252, &mmCP_HQD_PQ_WPTR_POLL_ADDR[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3253, &mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0], sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI)/sizeof(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_DOORBELL_CONTROL", REG_MMIO, 0x3254, &mmCP_HQD_PQ_DOORBELL_CONTROL[0], sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL)/sizeof(mmCP_HQD_PQ_DOORBELL_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_WPTR", REG_MMIO, 0x3255, &mmCP_HQD_PQ_WPTR[0], sizeof(mmCP_HQD_PQ_WPTR)/sizeof(mmCP_HQD_PQ_WPTR[0]), 0, 0 },
+	{ "mmCP_HQD_PQ_CONTROL", REG_MMIO, 0x3256, &mmCP_HQD_PQ_CONTROL[0], sizeof(mmCP_HQD_PQ_CONTROL)/sizeof(mmCP_HQD_PQ_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_IB_BASE_ADDR", REG_MMIO, 0x3257, &mmCP_HQD_IB_BASE_ADDR[0], sizeof(mmCP_HQD_IB_BASE_ADDR)/sizeof(mmCP_HQD_IB_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_IB_BASE_ADDR_HI", REG_MMIO, 0x3258, &mmCP_HQD_IB_BASE_ADDR_HI[0], sizeof(mmCP_HQD_IB_BASE_ADDR_HI)/sizeof(mmCP_HQD_IB_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_IB_RPTR", REG_MMIO, 0x3259, &mmCP_HQD_IB_RPTR[0], sizeof(mmCP_HQD_IB_RPTR)/sizeof(mmCP_HQD_IB_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_IB_CONTROL", REG_MMIO, 0x325a, &mmCP_HQD_IB_CONTROL[0], sizeof(mmCP_HQD_IB_CONTROL)/sizeof(mmCP_HQD_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_IQ_TIMER", REG_MMIO, 0x325b, &mmCP_HQD_IQ_TIMER[0], sizeof(mmCP_HQD_IQ_TIMER)/sizeof(mmCP_HQD_IQ_TIMER[0]), 0, 0 },
+	{ "mmCP_HQD_IQ_RPTR", REG_MMIO, 0x325c, &mmCP_HQD_IQ_RPTR[0], sizeof(mmCP_HQD_IQ_RPTR)/sizeof(mmCP_HQD_IQ_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_DEQUEUE_REQUEST", REG_MMIO, 0x325d, &mmCP_HQD_DEQUEUE_REQUEST[0], sizeof(mmCP_HQD_DEQUEUE_REQUEST)/sizeof(mmCP_HQD_DEQUEUE_REQUEST[0]), 0, 0 },
+	{ "mmCP_HQD_DMA_OFFLOAD", REG_MMIO, 0x325e, &mmCP_HQD_DMA_OFFLOAD[0], sizeof(mmCP_HQD_DMA_OFFLOAD)/sizeof(mmCP_HQD_DMA_OFFLOAD[0]), 0, 0 },
+	{ "mmCP_HQD_OFFLOAD", REG_MMIO, 0x325e, &mmCP_HQD_OFFLOAD[0], sizeof(mmCP_HQD_OFFLOAD)/sizeof(mmCP_HQD_OFFLOAD[0]), 0, 0 },
+	{ "mmCP_HQD_SEMA_CMD", REG_MMIO, 0x325f, &mmCP_HQD_SEMA_CMD[0], sizeof(mmCP_HQD_SEMA_CMD)/sizeof(mmCP_HQD_SEMA_CMD[0]), 0, 0 },
+	{ "mmCP_HQD_MSG_TYPE", REG_MMIO, 0x3260, &mmCP_HQD_MSG_TYPE[0], sizeof(mmCP_HQD_MSG_TYPE)/sizeof(mmCP_HQD_MSG_TYPE[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC0_PREOP_LO", REG_MMIO, 0x3261, &mmCP_HQD_ATOMIC0_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC0_PREOP_HI", REG_MMIO, 0x3262, &mmCP_HQD_ATOMIC0_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC0_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC1_PREOP_LO", REG_MMIO, 0x3263, &mmCP_HQD_ATOMIC1_PREOP_LO[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_LO)/sizeof(mmCP_HQD_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_HQD_ATOMIC1_PREOP_HI", REG_MMIO, 0x3264, &mmCP_HQD_ATOMIC1_PREOP_HI[0], sizeof(mmCP_HQD_ATOMIC1_PREOP_HI)/sizeof(mmCP_HQD_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_SCHEDULER0", REG_MMIO, 0x3265, &mmCP_HQD_HQ_SCHEDULER0[0], sizeof(mmCP_HQD_HQ_SCHEDULER0)/sizeof(mmCP_HQD_HQ_SCHEDULER0[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_STATUS0", REG_MMIO, 0x3265, &mmCP_HQD_HQ_STATUS0[0], sizeof(mmCP_HQD_HQ_STATUS0)/sizeof(mmCP_HQD_HQ_STATUS0[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_SCHEDULER1", REG_MMIO, 0x3266, &mmCP_HQD_HQ_SCHEDULER1[0], sizeof(mmCP_HQD_HQ_SCHEDULER1)/sizeof(mmCP_HQD_HQ_SCHEDULER1[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_CONTROL0", REG_MMIO, 0x3266, &mmCP_HQD_HQ_CONTROL0[0], sizeof(mmCP_HQD_HQ_CONTROL0)/sizeof(mmCP_HQD_HQ_CONTROL0[0]), 0, 0 },
+	{ "mmCP_MQD_CONTROL", REG_MMIO, 0x3267, &mmCP_MQD_CONTROL[0], sizeof(mmCP_MQD_CONTROL)/sizeof(mmCP_MQD_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_STATUS1", REG_MMIO, 0x3268, &mmCP_HQD_HQ_STATUS1[0], sizeof(mmCP_HQD_HQ_STATUS1)/sizeof(mmCP_HQD_HQ_STATUS1[0]), 0, 0 },
+	{ "mmCP_HQD_HQ_CONTROL1", REG_MMIO, 0x3269, &mmCP_HQD_HQ_CONTROL1[0], sizeof(mmCP_HQD_HQ_CONTROL1)/sizeof(mmCP_HQD_HQ_CONTROL1[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_BASE_ADDR", REG_MMIO, 0x326a, &mmCP_HQD_EOP_BASE_ADDR[0], sizeof(mmCP_HQD_EOP_BASE_ADDR)/sizeof(mmCP_HQD_EOP_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_BASE_ADDR_HI", REG_MMIO, 0x326b, &mmCP_HQD_EOP_BASE_ADDR_HI[0], sizeof(mmCP_HQD_EOP_BASE_ADDR_HI)/sizeof(mmCP_HQD_EOP_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_CONTROL", REG_MMIO, 0x326c, &mmCP_HQD_EOP_CONTROL[0], sizeof(mmCP_HQD_EOP_CONTROL)/sizeof(mmCP_HQD_EOP_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_RPTR", REG_MMIO, 0x326d, &mmCP_HQD_EOP_RPTR[0], sizeof(mmCP_HQD_EOP_RPTR)/sizeof(mmCP_HQD_EOP_RPTR[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_WPTR", REG_MMIO, 0x326e, &mmCP_HQD_EOP_WPTR[0], sizeof(mmCP_HQD_EOP_WPTR)/sizeof(mmCP_HQD_EOP_WPTR[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_EVENTS", REG_MMIO, 0x326f, &mmCP_HQD_EOP_EVENTS[0], sizeof(mmCP_HQD_EOP_EVENTS)/sizeof(mmCP_HQD_EOP_EVENTS[0]), 0, 0 },
+	{ "mmCP_HQD_CTX_SAVE_BASE_ADDR_LO", REG_MMIO, 0x3270, &mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[0], sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO)/sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_HQD_CTX_SAVE_BASE_ADDR_HI", REG_MMIO, 0x3271, &mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[0], sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI)/sizeof(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_HQD_CTX_SAVE_CONTROL", REG_MMIO, 0x3272, &mmCP_HQD_CTX_SAVE_CONTROL[0], sizeof(mmCP_HQD_CTX_SAVE_CONTROL)/sizeof(mmCP_HQD_CTX_SAVE_CONTROL[0]), 0, 0 },
+	{ "mmCP_HQD_CNTL_STACK_OFFSET", REG_MMIO, 0x3273, &mmCP_HQD_CNTL_STACK_OFFSET[0], sizeof(mmCP_HQD_CNTL_STACK_OFFSET)/sizeof(mmCP_HQD_CNTL_STACK_OFFSET[0]), 0, 0 },
+	{ "mmCP_HQD_CNTL_STACK_SIZE", REG_MMIO, 0x3274, &mmCP_HQD_CNTL_STACK_SIZE[0], sizeof(mmCP_HQD_CNTL_STACK_SIZE)/sizeof(mmCP_HQD_CNTL_STACK_SIZE[0]), 0, 0 },
+	{ "mmCP_HQD_WG_STATE_OFFSET", REG_MMIO, 0x3275, &mmCP_HQD_WG_STATE_OFFSET[0], sizeof(mmCP_HQD_WG_STATE_OFFSET)/sizeof(mmCP_HQD_WG_STATE_OFFSET[0]), 0, 0 },
+	{ "mmCP_HQD_CTX_SAVE_SIZE", REG_MMIO, 0x3276, &mmCP_HQD_CTX_SAVE_SIZE[0], sizeof(mmCP_HQD_CTX_SAVE_SIZE)/sizeof(mmCP_HQD_CTX_SAVE_SIZE[0]), 0, 0 },
+	{ "mmCP_HQD_GDS_RESOURCE_STATE", REG_MMIO, 0x3277, &mmCP_HQD_GDS_RESOURCE_STATE[0], sizeof(mmCP_HQD_GDS_RESOURCE_STATE)/sizeof(mmCP_HQD_GDS_RESOURCE_STATE[0]), 0, 0 },
+	{ "mmCP_HQD_ERROR", REG_MMIO, 0x3278, &mmCP_HQD_ERROR[0], sizeof(mmCP_HQD_ERROR)/sizeof(mmCP_HQD_ERROR[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_WPTR_MEM", REG_MMIO, 0x3279, &mmCP_HQD_EOP_WPTR_MEM[0], sizeof(mmCP_HQD_EOP_WPTR_MEM)/sizeof(mmCP_HQD_EOP_WPTR_MEM[0]), 0, 0 },
+	{ "mmCP_HQD_EOP_DONES", REG_MMIO, 0x327a, &mmCP_HQD_EOP_DONES[0], sizeof(mmCP_HQD_EOP_DONES)/sizeof(mmCP_HQD_EOP_DONES[0]), 0, 0 },
+	{ "mmDIDT_IND_INDEX", REG_MMIO, 0x3280, &mmDIDT_IND_INDEX[0], sizeof(mmDIDT_IND_INDEX)/sizeof(mmDIDT_IND_INDEX[0]), 0, 0 },
+	{ "mmDIDT_IND_DATA", REG_MMIO, 0x3281, &mmDIDT_IND_DATA[0], sizeof(mmDIDT_IND_DATA)/sizeof(mmDIDT_IND_DATA[0]), 0, 0 },
+	{ "mmTCP_WATCH0_ADDR_H", REG_MMIO, 0x32a0, &mmTCP_WATCH0_ADDR_H[0], sizeof(mmTCP_WATCH0_ADDR_H)/sizeof(mmTCP_WATCH0_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH0_ADDR_L", REG_MMIO, 0x32a1, &mmTCP_WATCH0_ADDR_L[0], sizeof(mmTCP_WATCH0_ADDR_L)/sizeof(mmTCP_WATCH0_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH0_CNTL", REG_MMIO, 0x32a2, &mmTCP_WATCH0_CNTL[0], sizeof(mmTCP_WATCH0_CNTL)/sizeof(mmTCP_WATCH0_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH1_ADDR_H", REG_MMIO, 0x32a3, &mmTCP_WATCH1_ADDR_H[0], sizeof(mmTCP_WATCH1_ADDR_H)/sizeof(mmTCP_WATCH1_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH1_ADDR_L", REG_MMIO, 0x32a4, &mmTCP_WATCH1_ADDR_L[0], sizeof(mmTCP_WATCH1_ADDR_L)/sizeof(mmTCP_WATCH1_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH1_CNTL", REG_MMIO, 0x32a5, &mmTCP_WATCH1_CNTL[0], sizeof(mmTCP_WATCH1_CNTL)/sizeof(mmTCP_WATCH1_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH2_ADDR_H", REG_MMIO, 0x32a6, &mmTCP_WATCH2_ADDR_H[0], sizeof(mmTCP_WATCH2_ADDR_H)/sizeof(mmTCP_WATCH2_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH2_ADDR_L", REG_MMIO, 0x32a7, &mmTCP_WATCH2_ADDR_L[0], sizeof(mmTCP_WATCH2_ADDR_L)/sizeof(mmTCP_WATCH2_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH2_CNTL", REG_MMIO, 0x32a8, &mmTCP_WATCH2_CNTL[0], sizeof(mmTCP_WATCH2_CNTL)/sizeof(mmTCP_WATCH2_CNTL[0]), 0, 0 },
+	{ "mmTCP_WATCH3_ADDR_H", REG_MMIO, 0x32a9, &mmTCP_WATCH3_ADDR_H[0], sizeof(mmTCP_WATCH3_ADDR_H)/sizeof(mmTCP_WATCH3_ADDR_H[0]), 0, 0 },
+	{ "mmTCP_WATCH3_ADDR_L", REG_MMIO, 0x32aa, &mmTCP_WATCH3_ADDR_L[0], sizeof(mmTCP_WATCH3_ADDR_L)/sizeof(mmTCP_WATCH3_ADDR_L[0]), 0, 0 },
+	{ "mmTCP_WATCH3_CNTL", REG_MMIO, 0x32ab, &mmTCP_WATCH3_CNTL[0], sizeof(mmTCP_WATCH3_CNTL)/sizeof(mmTCP_WATCH3_CNTL[0]), 0, 0 },
+	{ "mmTCP_GATCL1_CNTL", REG_MMIO, 0x32b0, &mmTCP_GATCL1_CNTL[0], sizeof(mmTCP_GATCL1_CNTL)/sizeof(mmTCP_GATCL1_CNTL[0]), 0, 0 },
+	{ "mmTCP_ATC_EDC_GATCL1_CNT", REG_MMIO, 0x32b1, &mmTCP_ATC_EDC_GATCL1_CNT[0], sizeof(mmTCP_ATC_EDC_GATCL1_CNT)/sizeof(mmTCP_ATC_EDC_GATCL1_CNT[0]), 0, 0 },
+	{ "mmTCP_GATCL1_DSM_CNTL", REG_MMIO, 0x32b2, &mmTCP_GATCL1_DSM_CNTL[0], sizeof(mmTCP_GATCL1_DSM_CNTL)/sizeof(mmTCP_GATCL1_DSM_CNTL[0]), 0, 0 },
+	{ "mmTCP_DSM_CNTL", REG_MMIO, 0x32b3, &mmTCP_DSM_CNTL[0], sizeof(mmTCP_DSM_CNTL)/sizeof(mmTCP_DSM_CNTL[0]), 0, 0 },
+	{ "mmTCP_CNTL2", REG_MMIO, 0x32b4, &mmTCP_CNTL2[0], sizeof(mmTCP_CNTL2)/sizeof(mmTCP_CNTL2[0]), 0, 0 },
+	{ "mmGDS_VMID0_BASE", REG_MMIO, 0x3300, &mmGDS_VMID0_BASE[0], sizeof(mmGDS_VMID0_BASE)/sizeof(mmGDS_VMID0_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID0_SIZE", REG_MMIO, 0x3301, &mmGDS_VMID0_SIZE[0], sizeof(mmGDS_VMID0_SIZE)/sizeof(mmGDS_VMID0_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID1_BASE", REG_MMIO, 0x3302, &mmGDS_VMID1_BASE[0], sizeof(mmGDS_VMID1_BASE)/sizeof(mmGDS_VMID1_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID1_SIZE", REG_MMIO, 0x3303, &mmGDS_VMID1_SIZE[0], sizeof(mmGDS_VMID1_SIZE)/sizeof(mmGDS_VMID1_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID2_BASE", REG_MMIO, 0x3304, &mmGDS_VMID2_BASE[0], sizeof(mmGDS_VMID2_BASE)/sizeof(mmGDS_VMID2_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID2_SIZE", REG_MMIO, 0x3305, &mmGDS_VMID2_SIZE[0], sizeof(mmGDS_VMID2_SIZE)/sizeof(mmGDS_VMID2_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID3_BASE", REG_MMIO, 0x3306, &mmGDS_VMID3_BASE[0], sizeof(mmGDS_VMID3_BASE)/sizeof(mmGDS_VMID3_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID3_SIZE", REG_MMIO, 0x3307, &mmGDS_VMID3_SIZE[0], sizeof(mmGDS_VMID3_SIZE)/sizeof(mmGDS_VMID3_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID4_BASE", REG_MMIO, 0x3308, &mmGDS_VMID4_BASE[0], sizeof(mmGDS_VMID4_BASE)/sizeof(mmGDS_VMID4_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID4_SIZE", REG_MMIO, 0x3309, &mmGDS_VMID4_SIZE[0], sizeof(mmGDS_VMID4_SIZE)/sizeof(mmGDS_VMID4_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID5_BASE", REG_MMIO, 0x330a, &mmGDS_VMID5_BASE[0], sizeof(mmGDS_VMID5_BASE)/sizeof(mmGDS_VMID5_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID5_SIZE", REG_MMIO, 0x330b, &mmGDS_VMID5_SIZE[0], sizeof(mmGDS_VMID5_SIZE)/sizeof(mmGDS_VMID5_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID6_BASE", REG_MMIO, 0x330c, &mmGDS_VMID6_BASE[0], sizeof(mmGDS_VMID6_BASE)/sizeof(mmGDS_VMID6_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID6_SIZE", REG_MMIO, 0x330d, &mmGDS_VMID6_SIZE[0], sizeof(mmGDS_VMID6_SIZE)/sizeof(mmGDS_VMID6_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID7_BASE", REG_MMIO, 0x330e, &mmGDS_VMID7_BASE[0], sizeof(mmGDS_VMID7_BASE)/sizeof(mmGDS_VMID7_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID7_SIZE", REG_MMIO, 0x330f, &mmGDS_VMID7_SIZE[0], sizeof(mmGDS_VMID7_SIZE)/sizeof(mmGDS_VMID7_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID8_BASE", REG_MMIO, 0x3310, &mmGDS_VMID8_BASE[0], sizeof(mmGDS_VMID8_BASE)/sizeof(mmGDS_VMID8_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID8_SIZE", REG_MMIO, 0x3311, &mmGDS_VMID8_SIZE[0], sizeof(mmGDS_VMID8_SIZE)/sizeof(mmGDS_VMID8_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID9_BASE", REG_MMIO, 0x3312, &mmGDS_VMID9_BASE[0], sizeof(mmGDS_VMID9_BASE)/sizeof(mmGDS_VMID9_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID9_SIZE", REG_MMIO, 0x3313, &mmGDS_VMID9_SIZE[0], sizeof(mmGDS_VMID9_SIZE)/sizeof(mmGDS_VMID9_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID10_BASE", REG_MMIO, 0x3314, &mmGDS_VMID10_BASE[0], sizeof(mmGDS_VMID10_BASE)/sizeof(mmGDS_VMID10_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID10_SIZE", REG_MMIO, 0x3315, &mmGDS_VMID10_SIZE[0], sizeof(mmGDS_VMID10_SIZE)/sizeof(mmGDS_VMID10_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID11_BASE", REG_MMIO, 0x3316, &mmGDS_VMID11_BASE[0], sizeof(mmGDS_VMID11_BASE)/sizeof(mmGDS_VMID11_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID11_SIZE", REG_MMIO, 0x3317, &mmGDS_VMID11_SIZE[0], sizeof(mmGDS_VMID11_SIZE)/sizeof(mmGDS_VMID11_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID12_BASE", REG_MMIO, 0x3318, &mmGDS_VMID12_BASE[0], sizeof(mmGDS_VMID12_BASE)/sizeof(mmGDS_VMID12_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID12_SIZE", REG_MMIO, 0x3319, &mmGDS_VMID12_SIZE[0], sizeof(mmGDS_VMID12_SIZE)/sizeof(mmGDS_VMID12_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID13_BASE", REG_MMIO, 0x331a, &mmGDS_VMID13_BASE[0], sizeof(mmGDS_VMID13_BASE)/sizeof(mmGDS_VMID13_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID13_SIZE", REG_MMIO, 0x331b, &mmGDS_VMID13_SIZE[0], sizeof(mmGDS_VMID13_SIZE)/sizeof(mmGDS_VMID13_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID14_BASE", REG_MMIO, 0x331c, &mmGDS_VMID14_BASE[0], sizeof(mmGDS_VMID14_BASE)/sizeof(mmGDS_VMID14_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID14_SIZE", REG_MMIO, 0x331d, &mmGDS_VMID14_SIZE[0], sizeof(mmGDS_VMID14_SIZE)/sizeof(mmGDS_VMID14_SIZE[0]), 0, 0 },
+	{ "mmGDS_VMID15_BASE", REG_MMIO, 0x331e, &mmGDS_VMID15_BASE[0], sizeof(mmGDS_VMID15_BASE)/sizeof(mmGDS_VMID15_BASE[0]), 0, 0 },
+	{ "mmGDS_VMID15_SIZE", REG_MMIO, 0x331f, &mmGDS_VMID15_SIZE[0], sizeof(mmGDS_VMID15_SIZE)/sizeof(mmGDS_VMID15_SIZE[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID0", REG_MMIO, 0x3320, &mmGDS_GWS_VMID0[0], sizeof(mmGDS_GWS_VMID0)/sizeof(mmGDS_GWS_VMID0[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID1", REG_MMIO, 0x3321, &mmGDS_GWS_VMID1[0], sizeof(mmGDS_GWS_VMID1)/sizeof(mmGDS_GWS_VMID1[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID2", REG_MMIO, 0x3322, &mmGDS_GWS_VMID2[0], sizeof(mmGDS_GWS_VMID2)/sizeof(mmGDS_GWS_VMID2[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID3", REG_MMIO, 0x3323, &mmGDS_GWS_VMID3[0], sizeof(mmGDS_GWS_VMID3)/sizeof(mmGDS_GWS_VMID3[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID4", REG_MMIO, 0x3324, &mmGDS_GWS_VMID4[0], sizeof(mmGDS_GWS_VMID4)/sizeof(mmGDS_GWS_VMID4[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID5", REG_MMIO, 0x3325, &mmGDS_GWS_VMID5[0], sizeof(mmGDS_GWS_VMID5)/sizeof(mmGDS_GWS_VMID5[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID6", REG_MMIO, 0x3326, &mmGDS_GWS_VMID6[0], sizeof(mmGDS_GWS_VMID6)/sizeof(mmGDS_GWS_VMID6[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID7", REG_MMIO, 0x3327, &mmGDS_GWS_VMID7[0], sizeof(mmGDS_GWS_VMID7)/sizeof(mmGDS_GWS_VMID7[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID8", REG_MMIO, 0x3328, &mmGDS_GWS_VMID8[0], sizeof(mmGDS_GWS_VMID8)/sizeof(mmGDS_GWS_VMID8[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID9", REG_MMIO, 0x3329, &mmGDS_GWS_VMID9[0], sizeof(mmGDS_GWS_VMID9)/sizeof(mmGDS_GWS_VMID9[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID10", REG_MMIO, 0x332a, &mmGDS_GWS_VMID10[0], sizeof(mmGDS_GWS_VMID10)/sizeof(mmGDS_GWS_VMID10[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID11", REG_MMIO, 0x332b, &mmGDS_GWS_VMID11[0], sizeof(mmGDS_GWS_VMID11)/sizeof(mmGDS_GWS_VMID11[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID12", REG_MMIO, 0x332c, &mmGDS_GWS_VMID12[0], sizeof(mmGDS_GWS_VMID12)/sizeof(mmGDS_GWS_VMID12[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID13", REG_MMIO, 0x332d, &mmGDS_GWS_VMID13[0], sizeof(mmGDS_GWS_VMID13)/sizeof(mmGDS_GWS_VMID13[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID14", REG_MMIO, 0x332e, &mmGDS_GWS_VMID14[0], sizeof(mmGDS_GWS_VMID14)/sizeof(mmGDS_GWS_VMID14[0]), 0, 0 },
+	{ "mmGDS_GWS_VMID15", REG_MMIO, 0x332f, &mmGDS_GWS_VMID15[0], sizeof(mmGDS_GWS_VMID15)/sizeof(mmGDS_GWS_VMID15[0]), 0, 0 },
+	{ "mmGDS_OA_VMID0", REG_MMIO, 0x3330, &mmGDS_OA_VMID0[0], sizeof(mmGDS_OA_VMID0)/sizeof(mmGDS_OA_VMID0[0]), 0, 0 },
+	{ "mmGDS_OA_VMID1", REG_MMIO, 0x3331, &mmGDS_OA_VMID1[0], sizeof(mmGDS_OA_VMID1)/sizeof(mmGDS_OA_VMID1[0]), 0, 0 },
+	{ "mmGDS_OA_VMID2", REG_MMIO, 0x3332, &mmGDS_OA_VMID2[0], sizeof(mmGDS_OA_VMID2)/sizeof(mmGDS_OA_VMID2[0]), 0, 0 },
+	{ "mmGDS_OA_VMID3", REG_MMIO, 0x3333, &mmGDS_OA_VMID3[0], sizeof(mmGDS_OA_VMID3)/sizeof(mmGDS_OA_VMID3[0]), 0, 0 },
+	{ "mmGDS_OA_VMID4", REG_MMIO, 0x3334, &mmGDS_OA_VMID4[0], sizeof(mmGDS_OA_VMID4)/sizeof(mmGDS_OA_VMID4[0]), 0, 0 },
+	{ "mmGDS_OA_VMID5", REG_MMIO, 0x3335, &mmGDS_OA_VMID5[0], sizeof(mmGDS_OA_VMID5)/sizeof(mmGDS_OA_VMID5[0]), 0, 0 },
+	{ "mmGDS_OA_VMID6", REG_MMIO, 0x3336, &mmGDS_OA_VMID6[0], sizeof(mmGDS_OA_VMID6)/sizeof(mmGDS_OA_VMID6[0]), 0, 0 },
+	{ "mmGDS_OA_VMID7", REG_MMIO, 0x3337, &mmGDS_OA_VMID7[0], sizeof(mmGDS_OA_VMID7)/sizeof(mmGDS_OA_VMID7[0]), 0, 0 },
+	{ "mmGDS_OA_VMID8", REG_MMIO, 0x3338, &mmGDS_OA_VMID8[0], sizeof(mmGDS_OA_VMID8)/sizeof(mmGDS_OA_VMID8[0]), 0, 0 },
+	{ "mmGDS_OA_VMID9", REG_MMIO, 0x3339, &mmGDS_OA_VMID9[0], sizeof(mmGDS_OA_VMID9)/sizeof(mmGDS_OA_VMID9[0]), 0, 0 },
+	{ "mmGDS_OA_VMID10", REG_MMIO, 0x333a, &mmGDS_OA_VMID10[0], sizeof(mmGDS_OA_VMID10)/sizeof(mmGDS_OA_VMID10[0]), 0, 0 },
+	{ "mmGDS_OA_VMID11", REG_MMIO, 0x333b, &mmGDS_OA_VMID11[0], sizeof(mmGDS_OA_VMID11)/sizeof(mmGDS_OA_VMID11[0]), 0, 0 },
+	{ "mmGDS_OA_VMID12", REG_MMIO, 0x333c, &mmGDS_OA_VMID12[0], sizeof(mmGDS_OA_VMID12)/sizeof(mmGDS_OA_VMID12[0]), 0, 0 },
+	{ "mmGDS_OA_VMID13", REG_MMIO, 0x333d, &mmGDS_OA_VMID13[0], sizeof(mmGDS_OA_VMID13)/sizeof(mmGDS_OA_VMID13[0]), 0, 0 },
+	{ "mmGDS_OA_VMID14", REG_MMIO, 0x333e, &mmGDS_OA_VMID14[0], sizeof(mmGDS_OA_VMID14)/sizeof(mmGDS_OA_VMID14[0]), 0, 0 },
+	{ "mmGDS_OA_VMID15", REG_MMIO, 0x333f, &mmGDS_OA_VMID15[0], sizeof(mmGDS_OA_VMID15)/sizeof(mmGDS_OA_VMID15[0]), 0, 0 },
+	{ "mmGDS_GWS_RESET0", REG_MMIO, 0x3344, &mmGDS_GWS_RESET0[0], sizeof(mmGDS_GWS_RESET0)/sizeof(mmGDS_GWS_RESET0[0]), 0, 0 },
+	{ "mmGDS_GWS_RESET1", REG_MMIO, 0x3345, &mmGDS_GWS_RESET1[0], sizeof(mmGDS_GWS_RESET1)/sizeof(mmGDS_GWS_RESET1[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_RESET", REG_MMIO, 0x3346, &mmGDS_GWS_RESOURCE_RESET[0], sizeof(mmGDS_GWS_RESOURCE_RESET)/sizeof(mmGDS_GWS_RESOURCE_RESET[0]), 0, 0 },
+	{ "mmGDS_COMPUTE_MAX_WAVE_ID", REG_MMIO, 0x3348, &mmGDS_COMPUTE_MAX_WAVE_ID[0], sizeof(mmGDS_COMPUTE_MAX_WAVE_ID)/sizeof(mmGDS_COMPUTE_MAX_WAVE_ID[0]), 0, 0 },
+	{ "mmGDS_OA_RESET_MASK", REG_MMIO, 0x3349, &mmGDS_OA_RESET_MASK[0], sizeof(mmGDS_OA_RESET_MASK)/sizeof(mmGDS_OA_RESET_MASK[0]), 0, 0 },
+	{ "mmGDS_OA_RESET", REG_MMIO, 0x334a, &mmGDS_OA_RESET[0], sizeof(mmGDS_OA_RESET)/sizeof(mmGDS_OA_RESET[0]), 0, 0 },
+	{ "mmGDS_ENHANCE", REG_MMIO, 0x334b, &mmGDS_ENHANCE[0], sizeof(mmGDS_ENHANCE)/sizeof(mmGDS_ENHANCE[0]), 0, 0 },
+	{ "mmGDS_OA_CGPG_RESTORE", REG_MMIO, 0x334c, &mmGDS_OA_CGPG_RESTORE[0], sizeof(mmGDS_OA_CGPG_RESTORE)/sizeof(mmGDS_OA_CGPG_RESTORE[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_STATUS", REG_MMIO, 0x334d, &mmGDS_CS_CTXSW_STATUS[0], sizeof(mmGDS_CS_CTXSW_STATUS)/sizeof(mmGDS_CS_CTXSW_STATUS[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_CNT0", REG_MMIO, 0x334e, &mmGDS_CS_CTXSW_CNT0[0], sizeof(mmGDS_CS_CTXSW_CNT0)/sizeof(mmGDS_CS_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_CNT1", REG_MMIO, 0x334f, &mmGDS_CS_CTXSW_CNT1[0], sizeof(mmGDS_CS_CTXSW_CNT1)/sizeof(mmGDS_CS_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_CNT2", REG_MMIO, 0x3350, &mmGDS_CS_CTXSW_CNT2[0], sizeof(mmGDS_CS_CTXSW_CNT2)/sizeof(mmGDS_CS_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_CS_CTXSW_CNT3", REG_MMIO, 0x3351, &mmGDS_CS_CTXSW_CNT3[0], sizeof(mmGDS_CS_CTXSW_CNT3)/sizeof(mmGDS_CS_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_GFX_CTXSW_STATUS", REG_MMIO, 0x3352, &mmGDS_GFX_CTXSW_STATUS[0], sizeof(mmGDS_GFX_CTXSW_STATUS)/sizeof(mmGDS_GFX_CTXSW_STATUS[0]), 0, 0 },
+	{ "mmGDS_VS_CTXSW_CNT0", REG_MMIO, 0x3353, &mmGDS_VS_CTXSW_CNT0[0], sizeof(mmGDS_VS_CTXSW_CNT0)/sizeof(mmGDS_VS_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_VS_CTXSW_CNT1", REG_MMIO, 0x3354, &mmGDS_VS_CTXSW_CNT1[0], sizeof(mmGDS_VS_CTXSW_CNT1)/sizeof(mmGDS_VS_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_VS_CTXSW_CNT2", REG_MMIO, 0x3355, &mmGDS_VS_CTXSW_CNT2[0], sizeof(mmGDS_VS_CTXSW_CNT2)/sizeof(mmGDS_VS_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_VS_CTXSW_CNT3", REG_MMIO, 0x3356, &mmGDS_VS_CTXSW_CNT3[0], sizeof(mmGDS_VS_CTXSW_CNT3)/sizeof(mmGDS_VS_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS0_CTXSW_CNT0", REG_MMIO, 0x3357, &mmGDS_PS0_CTXSW_CNT0[0], sizeof(mmGDS_PS0_CTXSW_CNT0)/sizeof(mmGDS_PS0_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS0_CTXSW_CNT1", REG_MMIO, 0x3358, &mmGDS_PS0_CTXSW_CNT1[0], sizeof(mmGDS_PS0_CTXSW_CNT1)/sizeof(mmGDS_PS0_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS0_CTXSW_CNT2", REG_MMIO, 0x3359, &mmGDS_PS0_CTXSW_CNT2[0], sizeof(mmGDS_PS0_CTXSW_CNT2)/sizeof(mmGDS_PS0_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS0_CTXSW_CNT3", REG_MMIO, 0x335a, &mmGDS_PS0_CTXSW_CNT3[0], sizeof(mmGDS_PS0_CTXSW_CNT3)/sizeof(mmGDS_PS0_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS1_CTXSW_CNT0", REG_MMIO, 0x335b, &mmGDS_PS1_CTXSW_CNT0[0], sizeof(mmGDS_PS1_CTXSW_CNT0)/sizeof(mmGDS_PS1_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS1_CTXSW_CNT1", REG_MMIO, 0x335c, &mmGDS_PS1_CTXSW_CNT1[0], sizeof(mmGDS_PS1_CTXSW_CNT1)/sizeof(mmGDS_PS1_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS1_CTXSW_CNT2", REG_MMIO, 0x335d, &mmGDS_PS1_CTXSW_CNT2[0], sizeof(mmGDS_PS1_CTXSW_CNT2)/sizeof(mmGDS_PS1_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS1_CTXSW_CNT3", REG_MMIO, 0x335e, &mmGDS_PS1_CTXSW_CNT3[0], sizeof(mmGDS_PS1_CTXSW_CNT3)/sizeof(mmGDS_PS1_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS2_CTXSW_CNT0", REG_MMIO, 0x335f, &mmGDS_PS2_CTXSW_CNT0[0], sizeof(mmGDS_PS2_CTXSW_CNT0)/sizeof(mmGDS_PS2_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS2_CTXSW_CNT1", REG_MMIO, 0x3360, &mmGDS_PS2_CTXSW_CNT1[0], sizeof(mmGDS_PS2_CTXSW_CNT1)/sizeof(mmGDS_PS2_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS2_CTXSW_CNT2", REG_MMIO, 0x3361, &mmGDS_PS2_CTXSW_CNT2[0], sizeof(mmGDS_PS2_CTXSW_CNT2)/sizeof(mmGDS_PS2_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS2_CTXSW_CNT3", REG_MMIO, 0x3362, &mmGDS_PS2_CTXSW_CNT3[0], sizeof(mmGDS_PS2_CTXSW_CNT3)/sizeof(mmGDS_PS2_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS3_CTXSW_CNT0", REG_MMIO, 0x3363, &mmGDS_PS3_CTXSW_CNT0[0], sizeof(mmGDS_PS3_CTXSW_CNT0)/sizeof(mmGDS_PS3_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS3_CTXSW_CNT1", REG_MMIO, 0x3364, &mmGDS_PS3_CTXSW_CNT1[0], sizeof(mmGDS_PS3_CTXSW_CNT1)/sizeof(mmGDS_PS3_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS3_CTXSW_CNT2", REG_MMIO, 0x3365, &mmGDS_PS3_CTXSW_CNT2[0], sizeof(mmGDS_PS3_CTXSW_CNT2)/sizeof(mmGDS_PS3_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS3_CTXSW_CNT3", REG_MMIO, 0x3366, &mmGDS_PS3_CTXSW_CNT3[0], sizeof(mmGDS_PS3_CTXSW_CNT3)/sizeof(mmGDS_PS3_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS4_CTXSW_CNT0", REG_MMIO, 0x3367, &mmGDS_PS4_CTXSW_CNT0[0], sizeof(mmGDS_PS4_CTXSW_CNT0)/sizeof(mmGDS_PS4_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS4_CTXSW_CNT1", REG_MMIO, 0x3368, &mmGDS_PS4_CTXSW_CNT1[0], sizeof(mmGDS_PS4_CTXSW_CNT1)/sizeof(mmGDS_PS4_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS4_CTXSW_CNT2", REG_MMIO, 0x3369, &mmGDS_PS4_CTXSW_CNT2[0], sizeof(mmGDS_PS4_CTXSW_CNT2)/sizeof(mmGDS_PS4_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS4_CTXSW_CNT3", REG_MMIO, 0x336a, &mmGDS_PS4_CTXSW_CNT3[0], sizeof(mmGDS_PS4_CTXSW_CNT3)/sizeof(mmGDS_PS4_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS5_CTXSW_CNT0", REG_MMIO, 0x336b, &mmGDS_PS5_CTXSW_CNT0[0], sizeof(mmGDS_PS5_CTXSW_CNT0)/sizeof(mmGDS_PS5_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS5_CTXSW_CNT1", REG_MMIO, 0x336c, &mmGDS_PS5_CTXSW_CNT1[0], sizeof(mmGDS_PS5_CTXSW_CNT1)/sizeof(mmGDS_PS5_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS5_CTXSW_CNT2", REG_MMIO, 0x336d, &mmGDS_PS5_CTXSW_CNT2[0], sizeof(mmGDS_PS5_CTXSW_CNT2)/sizeof(mmGDS_PS5_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS5_CTXSW_CNT3", REG_MMIO, 0x336e, &mmGDS_PS5_CTXSW_CNT3[0], sizeof(mmGDS_PS5_CTXSW_CNT3)/sizeof(mmGDS_PS5_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS6_CTXSW_CNT0", REG_MMIO, 0x336f, &mmGDS_PS6_CTXSW_CNT0[0], sizeof(mmGDS_PS6_CTXSW_CNT0)/sizeof(mmGDS_PS6_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS6_CTXSW_CNT1", REG_MMIO, 0x3370, &mmGDS_PS6_CTXSW_CNT1[0], sizeof(mmGDS_PS6_CTXSW_CNT1)/sizeof(mmGDS_PS6_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS6_CTXSW_CNT2", REG_MMIO, 0x3371, &mmGDS_PS6_CTXSW_CNT2[0], sizeof(mmGDS_PS6_CTXSW_CNT2)/sizeof(mmGDS_PS6_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS6_CTXSW_CNT3", REG_MMIO, 0x3372, &mmGDS_PS6_CTXSW_CNT3[0], sizeof(mmGDS_PS6_CTXSW_CNT3)/sizeof(mmGDS_PS6_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmGDS_PS7_CTXSW_CNT0", REG_MMIO, 0x3373, &mmGDS_PS7_CTXSW_CNT0[0], sizeof(mmGDS_PS7_CTXSW_CNT0)/sizeof(mmGDS_PS7_CTXSW_CNT0[0]), 0, 0 },
+	{ "mmGDS_PS7_CTXSW_CNT1", REG_MMIO, 0x3374, &mmGDS_PS7_CTXSW_CNT1[0], sizeof(mmGDS_PS7_CTXSW_CNT1)/sizeof(mmGDS_PS7_CTXSW_CNT1[0]), 0, 0 },
+	{ "mmGDS_PS7_CTXSW_CNT2", REG_MMIO, 0x3375, &mmGDS_PS7_CTXSW_CNT2[0], sizeof(mmGDS_PS7_CTXSW_CNT2)/sizeof(mmGDS_PS7_CTXSW_CNT2[0]), 0, 0 },
+	{ "mmGDS_PS7_CTXSW_CNT3", REG_MMIO, 0x3376, &mmGDS_PS7_CTXSW_CNT3[0], sizeof(mmGDS_PS7_CTXSW_CNT3)/sizeof(mmGDS_PS7_CTXSW_CNT3[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_CONTROL", REG_MMIO, 0x3380, &mmRAS_SIGNATURE_CONTROL[0], sizeof(mmRAS_SIGNATURE_CONTROL)/sizeof(mmRAS_SIGNATURE_CONTROL[0]), 0, 0 },
+	{ "mmRAS_SIGNATURE_MASK", REG_MMIO, 0x3381, &mmRAS_SIGNATURE_MASK[0], sizeof(mmRAS_SIGNATURE_MASK)/sizeof(mmRAS_SIGNATURE_MASK[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE0", REG_MMIO, 0x3382, &mmRAS_SX_SIGNATURE0[0], sizeof(mmRAS_SX_SIGNATURE0)/sizeof(mmRAS_SX_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE1", REG_MMIO, 0x3383, &mmRAS_SX_SIGNATURE1[0], sizeof(mmRAS_SX_SIGNATURE1)/sizeof(mmRAS_SX_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE2", REG_MMIO, 0x3384, &mmRAS_SX_SIGNATURE2[0], sizeof(mmRAS_SX_SIGNATURE2)/sizeof(mmRAS_SX_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SX_SIGNATURE3", REG_MMIO, 0x3385, &mmRAS_SX_SIGNATURE3[0], sizeof(mmRAS_SX_SIGNATURE3)/sizeof(mmRAS_SX_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_DB_SIGNATURE0", REG_MMIO, 0x338b, &mmRAS_DB_SIGNATURE0[0], sizeof(mmRAS_DB_SIGNATURE0)/sizeof(mmRAS_DB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_PA_SIGNATURE0", REG_MMIO, 0x338c, &mmRAS_PA_SIGNATURE0[0], sizeof(mmRAS_PA_SIGNATURE0)/sizeof(mmRAS_PA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_VGT_SIGNATURE0", REG_MMIO, 0x338d, &mmRAS_VGT_SIGNATURE0[0], sizeof(mmRAS_VGT_SIGNATURE0)/sizeof(mmRAS_VGT_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE0", REG_MMIO, 0x338f, &mmRAS_SC_SIGNATURE0[0], sizeof(mmRAS_SC_SIGNATURE0)/sizeof(mmRAS_SC_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE1", REG_MMIO, 0x3390, &mmRAS_SC_SIGNATURE1[0], sizeof(mmRAS_SC_SIGNATURE1)/sizeof(mmRAS_SC_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE2", REG_MMIO, 0x3391, &mmRAS_SC_SIGNATURE2[0], sizeof(mmRAS_SC_SIGNATURE2)/sizeof(mmRAS_SC_SIGNATURE2[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE3", REG_MMIO, 0x3392, &mmRAS_SC_SIGNATURE3[0], sizeof(mmRAS_SC_SIGNATURE3)/sizeof(mmRAS_SC_SIGNATURE3[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE4", REG_MMIO, 0x3393, &mmRAS_SC_SIGNATURE4[0], sizeof(mmRAS_SC_SIGNATURE4)/sizeof(mmRAS_SC_SIGNATURE4[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE5", REG_MMIO, 0x3394, &mmRAS_SC_SIGNATURE5[0], sizeof(mmRAS_SC_SIGNATURE5)/sizeof(mmRAS_SC_SIGNATURE5[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE6", REG_MMIO, 0x3395, &mmRAS_SC_SIGNATURE6[0], sizeof(mmRAS_SC_SIGNATURE6)/sizeof(mmRAS_SC_SIGNATURE6[0]), 0, 0 },
+	{ "mmRAS_SC_SIGNATURE7", REG_MMIO, 0x3396, &mmRAS_SC_SIGNATURE7[0], sizeof(mmRAS_SC_SIGNATURE7)/sizeof(mmRAS_SC_SIGNATURE7[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE0", REG_MMIO, 0x3397, &mmRAS_IA_SIGNATURE0[0], sizeof(mmRAS_IA_SIGNATURE0)/sizeof(mmRAS_IA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_IA_SIGNATURE1", REG_MMIO, 0x3398, &mmRAS_IA_SIGNATURE1[0], sizeof(mmRAS_IA_SIGNATURE1)/sizeof(mmRAS_IA_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE0", REG_MMIO, 0x3399, &mmRAS_SPI_SIGNATURE0[0], sizeof(mmRAS_SPI_SIGNATURE0)/sizeof(mmRAS_SPI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_SPI_SIGNATURE1", REG_MMIO, 0x339a, &mmRAS_SPI_SIGNATURE1[0], sizeof(mmRAS_SPI_SIGNATURE1)/sizeof(mmRAS_SPI_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_TA_SIGNATURE0", REG_MMIO, 0x339b, &mmRAS_TA_SIGNATURE0[0], sizeof(mmRAS_TA_SIGNATURE0)/sizeof(mmRAS_TA_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_TD_SIGNATURE0", REG_MMIO, 0x339c, &mmRAS_TD_SIGNATURE0[0], sizeof(mmRAS_TD_SIGNATURE0)/sizeof(mmRAS_TD_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_CB_SIGNATURE0", REG_MMIO, 0x339d, &mmRAS_CB_SIGNATURE0[0], sizeof(mmRAS_CB_SIGNATURE0)/sizeof(mmRAS_CB_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE0", REG_MMIO, 0x339e, &mmRAS_BCI_SIGNATURE0[0], sizeof(mmRAS_BCI_SIGNATURE0)/sizeof(mmRAS_BCI_SIGNATURE0[0]), 0, 0 },
+	{ "mmRAS_BCI_SIGNATURE1", REG_MMIO, 0x339f, &mmRAS_BCI_SIGNATURE1[0], sizeof(mmRAS_BCI_SIGNATURE1)/sizeof(mmRAS_BCI_SIGNATURE1[0]), 0, 0 },
+	{ "mmRAS_TA_SIGNATURE1", REG_MMIO, 0x33a0, &mmRAS_TA_SIGNATURE1[0], sizeof(mmRAS_TA_SIGNATURE1)/sizeof(mmRAS_TA_SIGNATURE1[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG04", REG_SMC, 0x4, &ixCLIPPER_DEBUG_REG04[0], sizeof(ixCLIPPER_DEBUG_REG04)/sizeof(ixCLIPPER_DEBUG_REG04[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG4", REG_SMC, 0x4, &ixGDS_DEBUG_REG4[0], sizeof(ixGDS_DEBUG_REG4)/sizeof(ixGDS_DEBUG_REG4[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG4", REG_SMC, 0x4, &ixWD_DEBUG_REG4[0], sizeof(ixWD_DEBUG_REG4)/sizeof(ixWD_DEBUG_REG4[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL0", REG_SMC, 0x40, &ixDIDT_TD_CTRL0[0], sizeof(ixDIDT_TD_CTRL0)/sizeof(ixDIDT_TD_CTRL0[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL1", REG_SMC, 0x41, &ixDIDT_TD_CTRL1[0], sizeof(ixDIDT_TD_CTRL1)/sizeof(ixDIDT_TD_CTRL1[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL2", REG_SMC, 0x42, &ixDIDT_TD_CTRL2[0], sizeof(ixDIDT_TD_CTRL2)/sizeof(ixDIDT_TD_CTRL2[0]), 0, 0 },
+	{ "ixDIDT_TD_CTRL_OCP", REG_SMC, 0x43, &ixDIDT_TD_CTRL_OCP[0], sizeof(ixDIDT_TD_CTRL_OCP)/sizeof(ixDIDT_TD_CTRL_OCP[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG05", REG_SMC, 0x5, &ixCLIPPER_DEBUG_REG05[0], sizeof(ixCLIPPER_DEBUG_REG05)/sizeof(ixCLIPPER_DEBUG_REG05[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG5", REG_SMC, 0x5, &ixGDS_DEBUG_REG5[0], sizeof(ixGDS_DEBUG_REG5)/sizeof(ixGDS_DEBUG_REG5[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG5", REG_SMC, 0x5, &ixWD_DEBUG_REG5[0], sizeof(ixWD_DEBUG_REG5)/sizeof(ixWD_DEBUG_REG5[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT0_3", REG_SMC, 0x50, &ixDIDT_TD_WEIGHT0_3[0], sizeof(ixDIDT_TD_WEIGHT0_3)/sizeof(ixDIDT_TD_WEIGHT0_3[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT4_7", REG_SMC, 0x51, &ixDIDT_TD_WEIGHT4_7[0], sizeof(ixDIDT_TD_WEIGHT4_7)/sizeof(ixDIDT_TD_WEIGHT4_7[0]), 0, 0 },
+	{ "ixDIDT_TD_WEIGHT8_11", REG_SMC, 0x52, &ixDIDT_TD_WEIGHT8_11[0], sizeof(ixDIDT_TD_WEIGHT8_11)/sizeof(ixDIDT_TD_WEIGHT8_11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG06", REG_SMC, 0x6, &ixCLIPPER_DEBUG_REG06[0], sizeof(ixCLIPPER_DEBUG_REG06)/sizeof(ixCLIPPER_DEBUG_REG06[0]), 0, 0 },
+	{ "ixGDS_DEBUG_REG6", REG_SMC, 0x6, &ixGDS_DEBUG_REG6[0], sizeof(ixGDS_DEBUG_REG6)/sizeof(ixGDS_DEBUG_REG6[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG6", REG_SMC, 0x6, &ixWD_DEBUG_REG6[0], sizeof(ixWD_DEBUG_REG6)/sizeof(ixWD_DEBUG_REG6[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL0", REG_SMC, 0x60, &ixDIDT_TCP_CTRL0[0], sizeof(ixDIDT_TCP_CTRL0)/sizeof(ixDIDT_TCP_CTRL0[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL1", REG_SMC, 0x61, &ixDIDT_TCP_CTRL1[0], sizeof(ixDIDT_TCP_CTRL1)/sizeof(ixDIDT_TCP_CTRL1[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL2", REG_SMC, 0x62, &ixDIDT_TCP_CTRL2[0], sizeof(ixDIDT_TCP_CTRL2)/sizeof(ixDIDT_TCP_CTRL2[0]), 0, 0 },
+	{ "ixDIDT_TCP_CTRL_OCP", REG_SMC, 0x63, &ixDIDT_TCP_CTRL_OCP[0], sizeof(ixDIDT_TCP_CTRL_OCP)/sizeof(ixDIDT_TCP_CTRL_OCP[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG07", REG_SMC, 0x7, &ixCLIPPER_DEBUG_REG07[0], sizeof(ixCLIPPER_DEBUG_REG07)/sizeof(ixCLIPPER_DEBUG_REG07[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG18", REG_SMC, 0x7, &ixVGT_DEBUG_REG18[0], sizeof(ixVGT_DEBUG_REG18)/sizeof(ixVGT_DEBUG_REG18[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG7", REG_SMC, 0x7, &ixWD_DEBUG_REG7[0], sizeof(ixWD_DEBUG_REG7)/sizeof(ixWD_DEBUG_REG7[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT0_3", REG_SMC, 0x70, &ixDIDT_TCP_WEIGHT0_3[0], sizeof(ixDIDT_TCP_WEIGHT0_3)/sizeof(ixDIDT_TCP_WEIGHT0_3[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT4_7", REG_SMC, 0x71, &ixDIDT_TCP_WEIGHT4_7[0], sizeof(ixDIDT_TCP_WEIGHT4_7)/sizeof(ixDIDT_TCP_WEIGHT4_7[0]), 0, 0 },
+	{ "ixDIDT_TCP_WEIGHT8_11", REG_SMC, 0x72, &ixDIDT_TCP_WEIGHT8_11[0], sizeof(ixDIDT_TCP_WEIGHT8_11)/sizeof(ixDIDT_TCP_WEIGHT8_11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG08", REG_SMC, 0x8, &ixCLIPPER_DEBUG_REG08[0], sizeof(ixCLIPPER_DEBUG_REG08)/sizeof(ixCLIPPER_DEBUG_REG08[0]), 0, 0 },
+	{ "ixSQ_DEBUG_STS_LOCAL", REG_SMC, 0x8, &ixSQ_DEBUG_STS_LOCAL[0], sizeof(ixSQ_DEBUG_STS_LOCAL)/sizeof(ixSQ_DEBUG_STS_LOCAL[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG8", REG_SMC, 0x8, &ixVGT_DEBUG_REG8[0], sizeof(ixVGT_DEBUG_REG8)/sizeof(ixVGT_DEBUG_REG8[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG8", REG_SMC, 0x8, &ixWD_DEBUG_REG8[0], sizeof(ixWD_DEBUG_REG8)/sizeof(ixWD_DEBUG_REG8[0]), 0, 0 },
+	{ "ixDIDT_DBR_CTRL0", REG_SMC, 0x80, &ixDIDT_DBR_CTRL0[0], sizeof(ixDIDT_DBR_CTRL0)/sizeof(ixDIDT_DBR_CTRL0[0]), 0, 0 },
+	{ "ixDIDT_DBR_CTRL1", REG_SMC, 0x81, &ixDIDT_DBR_CTRL1[0], sizeof(ixDIDT_DBR_CTRL1)/sizeof(ixDIDT_DBR_CTRL1[0]), 0, 0 },
+	{ "ixDIDT_DBR_CTRL2", REG_SMC, 0x82, &ixDIDT_DBR_CTRL2[0], sizeof(ixDIDT_DBR_CTRL2)/sizeof(ixDIDT_DBR_CTRL2[0]), 0, 0 },
+	{ "ixDIDT_DBR_CTRL_OCP", REG_SMC, 0x83, &ixDIDT_DBR_CTRL_OCP[0], sizeof(ixDIDT_DBR_CTRL_OCP)/sizeof(ixDIDT_DBR_CTRL_OCP[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG09", REG_SMC, 0x9, &ixCLIPPER_DEBUG_REG09[0], sizeof(ixCLIPPER_DEBUG_REG09)/sizeof(ixCLIPPER_DEBUG_REG09[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG9", REG_SMC, 0x9, &ixVGT_DEBUG_REG9[0], sizeof(ixVGT_DEBUG_REG9)/sizeof(ixVGT_DEBUG_REG9[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG9", REG_SMC, 0x9, &ixWD_DEBUG_REG9[0], sizeof(ixWD_DEBUG_REG9)/sizeof(ixWD_DEBUG_REG9[0]), 0, 0 },
+	{ "ixDIDT_DBR_WEIGHT0_3", REG_SMC, 0x90, &ixDIDT_DBR_WEIGHT0_3[0], sizeof(ixDIDT_DBR_WEIGHT0_3)/sizeof(ixDIDT_DBR_WEIGHT0_3[0]), 0, 0 },
+	{ "ixDIDT_DBR_WEIGHT4_7", REG_SMC, 0x91, &ixDIDT_DBR_WEIGHT4_7[0], sizeof(ixDIDT_DBR_WEIGHT4_7)/sizeof(ixDIDT_DBR_WEIGHT4_7[0]), 0, 0 },
+	{ "ixDIDT_DBR_WEIGHT8_11", REG_SMC, 0x92, &ixDIDT_DBR_WEIGHT8_11[0], sizeof(ixDIDT_DBR_WEIGHT8_11)/sizeof(ixDIDT_DBR_WEIGHT8_11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG10", REG_SMC, 0xa, &ixCLIPPER_DEBUG_REG10[0], sizeof(ixCLIPPER_DEBUG_REG10)/sizeof(ixCLIPPER_DEBUG_REG10[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG10", REG_SMC, 0xa, &ixVGT_DEBUG_REG10[0], sizeof(ixVGT_DEBUG_REG10)/sizeof(ixVGT_DEBUG_REG10[0]), 0, 0 },
+	{ "ixWD_DEBUG_REG10", REG_SMC, 0xa, &ixWD_DEBUG_REG10[0], sizeof(ixWD_DEBUG_REG10)/sizeof(ixWD_DEBUG_REG10[0]), 0, 0 },
+	{ "mmDB_RENDER_CONTROL", REG_MMIO, 0xa000, &mmDB_RENDER_CONTROL[0], sizeof(mmDB_RENDER_CONTROL)/sizeof(mmDB_RENDER_CONTROL[0]), 0, 0 },
+	{ "mmDB_COUNT_CONTROL", REG_MMIO, 0xa001, &mmDB_COUNT_CONTROL[0], sizeof(mmDB_COUNT_CONTROL)/sizeof(mmDB_COUNT_CONTROL[0]), 0, 0 },
+	{ "mmDB_DEPTH_VIEW", REG_MMIO, 0xa002, &mmDB_DEPTH_VIEW[0], sizeof(mmDB_DEPTH_VIEW)/sizeof(mmDB_DEPTH_VIEW[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE", REG_MMIO, 0xa003, &mmDB_RENDER_OVERRIDE[0], sizeof(mmDB_RENDER_OVERRIDE)/sizeof(mmDB_RENDER_OVERRIDE[0]), 0, 0 },
+	{ "mmDB_RENDER_OVERRIDE2", REG_MMIO, 0xa004, &mmDB_RENDER_OVERRIDE2[0], sizeof(mmDB_RENDER_OVERRIDE2)/sizeof(mmDB_RENDER_OVERRIDE2[0]), 0, 0 },
+	{ "mmDB_HTILE_DATA_BASE", REG_MMIO, 0xa005, &mmDB_HTILE_DATA_BASE[0], sizeof(mmDB_HTILE_DATA_BASE)/sizeof(mmDB_HTILE_DATA_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MIN", REG_MMIO, 0xa008, &mmDB_DEPTH_BOUNDS_MIN[0], sizeof(mmDB_DEPTH_BOUNDS_MIN)/sizeof(mmDB_DEPTH_BOUNDS_MIN[0]), 0, 0 },
+	{ "mmDB_DEPTH_BOUNDS_MAX", REG_MMIO, 0xa009, &mmDB_DEPTH_BOUNDS_MAX[0], sizeof(mmDB_DEPTH_BOUNDS_MAX)/sizeof(mmDB_DEPTH_BOUNDS_MAX[0]), 0, 0 },
+	{ "mmDB_STENCIL_CLEAR", REG_MMIO, 0xa00a, &mmDB_STENCIL_CLEAR[0], sizeof(mmDB_STENCIL_CLEAR)/sizeof(mmDB_STENCIL_CLEAR[0]), 0, 0 },
+	{ "mmDB_DEPTH_CLEAR", REG_MMIO, 0xa00b, &mmDB_DEPTH_CLEAR[0], sizeof(mmDB_DEPTH_CLEAR)/sizeof(mmDB_DEPTH_CLEAR[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_TL", REG_MMIO, 0xa00c, &mmPA_SC_SCREEN_SCISSOR_TL[0], sizeof(mmPA_SC_SCREEN_SCISSOR_TL)/sizeof(mmPA_SC_SCREEN_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_SCISSOR_BR", REG_MMIO, 0xa00d, &mmPA_SC_SCREEN_SCISSOR_BR[0], sizeof(mmPA_SC_SCREEN_SCISSOR_BR)/sizeof(mmPA_SC_SCREEN_SCISSOR_BR[0]), 0, 0 },
+	{ "mmDB_DEPTH_INFO", REG_MMIO, 0xa00f, &mmDB_DEPTH_INFO[0], sizeof(mmDB_DEPTH_INFO)/sizeof(mmDB_DEPTH_INFO[0]), 0, 0 },
+	{ "mmDB_Z_INFO", REG_MMIO, 0xa010, &mmDB_Z_INFO[0], sizeof(mmDB_Z_INFO)/sizeof(mmDB_Z_INFO[0]), 0, 0 },
+	{ "mmDB_STENCIL_INFO", REG_MMIO, 0xa011, &mmDB_STENCIL_INFO[0], sizeof(mmDB_STENCIL_INFO)/sizeof(mmDB_STENCIL_INFO[0]), 0, 0 },
+	{ "mmDB_Z_READ_BASE", REG_MMIO, 0xa012, &mmDB_Z_READ_BASE[0], sizeof(mmDB_Z_READ_BASE)/sizeof(mmDB_Z_READ_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_READ_BASE", REG_MMIO, 0xa013, &mmDB_STENCIL_READ_BASE[0], sizeof(mmDB_STENCIL_READ_BASE)/sizeof(mmDB_STENCIL_READ_BASE[0]), 0, 0 },
+	{ "mmDB_Z_WRITE_BASE", REG_MMIO, 0xa014, &mmDB_Z_WRITE_BASE[0], sizeof(mmDB_Z_WRITE_BASE)/sizeof(mmDB_Z_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_STENCIL_WRITE_BASE", REG_MMIO, 0xa015, &mmDB_STENCIL_WRITE_BASE[0], sizeof(mmDB_STENCIL_WRITE_BASE)/sizeof(mmDB_STENCIL_WRITE_BASE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SIZE", REG_MMIO, 0xa016, &mmDB_DEPTH_SIZE[0], sizeof(mmDB_DEPTH_SIZE)/sizeof(mmDB_DEPTH_SIZE[0]), 0, 0 },
+	{ "mmDB_DEPTH_SLICE", REG_MMIO, 0xa017, &mmDB_DEPTH_SLICE[0], sizeof(mmDB_DEPTH_SLICE)/sizeof(mmDB_DEPTH_SLICE[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR", REG_MMIO, 0xa020, &mmTA_BC_BASE_ADDR[0], sizeof(mmTA_BC_BASE_ADDR)/sizeof(mmTA_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_BC_BASE_ADDR_HI", REG_MMIO, 0xa021, &mmTA_BC_BASE_ADDR_HI[0], sizeof(mmTA_BC_BASE_ADDR_HI)/sizeof(mmTA_BC_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_0", REG_MMIO, 0xa07a, &mmCOHER_DEST_BASE_HI_0[0], sizeof(mmCOHER_DEST_BASE_HI_0)/sizeof(mmCOHER_DEST_BASE_HI_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_1", REG_MMIO, 0xa07b, &mmCOHER_DEST_BASE_HI_1[0], sizeof(mmCOHER_DEST_BASE_HI_1)/sizeof(mmCOHER_DEST_BASE_HI_1[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_2", REG_MMIO, 0xa07c, &mmCOHER_DEST_BASE_HI_2[0], sizeof(mmCOHER_DEST_BASE_HI_2)/sizeof(mmCOHER_DEST_BASE_HI_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_HI_3", REG_MMIO, 0xa07d, &mmCOHER_DEST_BASE_HI_3[0], sizeof(mmCOHER_DEST_BASE_HI_3)/sizeof(mmCOHER_DEST_BASE_HI_3[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_2", REG_MMIO, 0xa07e, &mmCOHER_DEST_BASE_2[0], sizeof(mmCOHER_DEST_BASE_2)/sizeof(mmCOHER_DEST_BASE_2[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_3", REG_MMIO, 0xa07f, &mmCOHER_DEST_BASE_3[0], sizeof(mmCOHER_DEST_BASE_3)/sizeof(mmCOHER_DEST_BASE_3[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_OFFSET", REG_MMIO, 0xa080, &mmPA_SC_WINDOW_OFFSET[0], sizeof(mmPA_SC_WINDOW_OFFSET)/sizeof(mmPA_SC_WINDOW_OFFSET[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_TL", REG_MMIO, 0xa081, &mmPA_SC_WINDOW_SCISSOR_TL[0], sizeof(mmPA_SC_WINDOW_SCISSOR_TL)/sizeof(mmPA_SC_WINDOW_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_WINDOW_SCISSOR_BR", REG_MMIO, 0xa082, &mmPA_SC_WINDOW_SCISSOR_BR[0], sizeof(mmPA_SC_WINDOW_SCISSOR_BR)/sizeof(mmPA_SC_WINDOW_SCISSOR_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_RULE", REG_MMIO, 0xa083, &mmPA_SC_CLIPRECT_RULE[0], sizeof(mmPA_SC_CLIPRECT_RULE)/sizeof(mmPA_SC_CLIPRECT_RULE[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_TL", REG_MMIO, 0xa084, &mmPA_SC_CLIPRECT_0_TL[0], sizeof(mmPA_SC_CLIPRECT_0_TL)/sizeof(mmPA_SC_CLIPRECT_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_0_BR", REG_MMIO, 0xa085, &mmPA_SC_CLIPRECT_0_BR[0], sizeof(mmPA_SC_CLIPRECT_0_BR)/sizeof(mmPA_SC_CLIPRECT_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_TL", REG_MMIO, 0xa086, &mmPA_SC_CLIPRECT_1_TL[0], sizeof(mmPA_SC_CLIPRECT_1_TL)/sizeof(mmPA_SC_CLIPRECT_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_1_BR", REG_MMIO, 0xa087, &mmPA_SC_CLIPRECT_1_BR[0], sizeof(mmPA_SC_CLIPRECT_1_BR)/sizeof(mmPA_SC_CLIPRECT_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_TL", REG_MMIO, 0xa088, &mmPA_SC_CLIPRECT_2_TL[0], sizeof(mmPA_SC_CLIPRECT_2_TL)/sizeof(mmPA_SC_CLIPRECT_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_2_BR", REG_MMIO, 0xa089, &mmPA_SC_CLIPRECT_2_BR[0], sizeof(mmPA_SC_CLIPRECT_2_BR)/sizeof(mmPA_SC_CLIPRECT_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_TL", REG_MMIO, 0xa08a, &mmPA_SC_CLIPRECT_3_TL[0], sizeof(mmPA_SC_CLIPRECT_3_TL)/sizeof(mmPA_SC_CLIPRECT_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_CLIPRECT_3_BR", REG_MMIO, 0xa08b, &mmPA_SC_CLIPRECT_3_BR[0], sizeof(mmPA_SC_CLIPRECT_3_BR)/sizeof(mmPA_SC_CLIPRECT_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_EDGERULE", REG_MMIO, 0xa08c, &mmPA_SC_EDGERULE[0], sizeof(mmPA_SC_EDGERULE)/sizeof(mmPA_SC_EDGERULE[0]), 0, 0 },
+	{ "mmPA_SU_HARDWARE_SCREEN_OFFSET", REG_MMIO, 0xa08d, &mmPA_SU_HARDWARE_SCREEN_OFFSET[0], sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET)/sizeof(mmPA_SU_HARDWARE_SCREEN_OFFSET[0]), 0, 0 },
+	{ "mmCB_TARGET_MASK", REG_MMIO, 0xa08e, &mmCB_TARGET_MASK[0], sizeof(mmCB_TARGET_MASK)/sizeof(mmCB_TARGET_MASK[0]), 0, 0 },
+	{ "mmCB_SHADER_MASK", REG_MMIO, 0xa08f, &mmCB_SHADER_MASK[0], sizeof(mmCB_SHADER_MASK)/sizeof(mmCB_SHADER_MASK[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_TL", REG_MMIO, 0xa090, &mmPA_SC_GENERIC_SCISSOR_TL[0], sizeof(mmPA_SC_GENERIC_SCISSOR_TL)/sizeof(mmPA_SC_GENERIC_SCISSOR_TL[0]), 0, 0 },
+	{ "mmPA_SC_GENERIC_SCISSOR_BR", REG_MMIO, 0xa091, &mmPA_SC_GENERIC_SCISSOR_BR[0], sizeof(mmPA_SC_GENERIC_SCISSOR_BR)/sizeof(mmPA_SC_GENERIC_SCISSOR_BR[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_0", REG_MMIO, 0xa092, &mmCOHER_DEST_BASE_0[0], sizeof(mmCOHER_DEST_BASE_0)/sizeof(mmCOHER_DEST_BASE_0[0]), 0, 0 },
+	{ "mmCOHER_DEST_BASE_1", REG_MMIO, 0xa093, &mmCOHER_DEST_BASE_1[0], sizeof(mmCOHER_DEST_BASE_1)/sizeof(mmCOHER_DEST_BASE_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_TL", REG_MMIO, 0xa094, &mmPA_SC_VPORT_SCISSOR_0_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_0_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_0_BR", REG_MMIO, 0xa095, &mmPA_SC_VPORT_SCISSOR_0_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_0_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_0_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_TL", REG_MMIO, 0xa096, &mmPA_SC_VPORT_SCISSOR_1_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_1_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_1_BR", REG_MMIO, 0xa097, &mmPA_SC_VPORT_SCISSOR_1_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_1_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_1_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_TL", REG_MMIO, 0xa098, &mmPA_SC_VPORT_SCISSOR_2_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_2_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_2_BR", REG_MMIO, 0xa099, &mmPA_SC_VPORT_SCISSOR_2_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_2_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_2_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_TL", REG_MMIO, 0xa09a, &mmPA_SC_VPORT_SCISSOR_3_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_3_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_3_BR", REG_MMIO, 0xa09b, &mmPA_SC_VPORT_SCISSOR_3_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_3_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_3_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_TL", REG_MMIO, 0xa09c, &mmPA_SC_VPORT_SCISSOR_4_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_4_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_4_BR", REG_MMIO, 0xa09d, &mmPA_SC_VPORT_SCISSOR_4_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_4_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_4_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_TL", REG_MMIO, 0xa09e, &mmPA_SC_VPORT_SCISSOR_5_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_5_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_5_BR", REG_MMIO, 0xa09f, &mmPA_SC_VPORT_SCISSOR_5_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_5_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_5_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_TL", REG_MMIO, 0xa0a0, &mmPA_SC_VPORT_SCISSOR_6_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_6_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_6_BR", REG_MMIO, 0xa0a1, &mmPA_SC_VPORT_SCISSOR_6_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_6_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_6_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_TL", REG_MMIO, 0xa0a2, &mmPA_SC_VPORT_SCISSOR_7_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_7_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_7_BR", REG_MMIO, 0xa0a3, &mmPA_SC_VPORT_SCISSOR_7_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_7_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_7_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_TL", REG_MMIO, 0xa0a4, &mmPA_SC_VPORT_SCISSOR_8_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_8_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_8_BR", REG_MMIO, 0xa0a5, &mmPA_SC_VPORT_SCISSOR_8_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_8_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_8_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_TL", REG_MMIO, 0xa0a6, &mmPA_SC_VPORT_SCISSOR_9_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_9_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_9_BR", REG_MMIO, 0xa0a7, &mmPA_SC_VPORT_SCISSOR_9_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_9_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_9_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_TL", REG_MMIO, 0xa0a8, &mmPA_SC_VPORT_SCISSOR_10_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_10_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_10_BR", REG_MMIO, 0xa0a9, &mmPA_SC_VPORT_SCISSOR_10_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_10_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_10_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_TL", REG_MMIO, 0xa0aa, &mmPA_SC_VPORT_SCISSOR_11_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_11_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_11_BR", REG_MMIO, 0xa0ab, &mmPA_SC_VPORT_SCISSOR_11_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_11_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_11_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_TL", REG_MMIO, 0xa0ac, &mmPA_SC_VPORT_SCISSOR_12_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_12_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_12_BR", REG_MMIO, 0xa0ad, &mmPA_SC_VPORT_SCISSOR_12_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_12_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_12_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_TL", REG_MMIO, 0xa0ae, &mmPA_SC_VPORT_SCISSOR_13_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_13_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_13_BR", REG_MMIO, 0xa0af, &mmPA_SC_VPORT_SCISSOR_13_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_13_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_13_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_TL", REG_MMIO, 0xa0b0, &mmPA_SC_VPORT_SCISSOR_14_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_14_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_14_BR", REG_MMIO, 0xa0b1, &mmPA_SC_VPORT_SCISSOR_14_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_14_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_14_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_TL", REG_MMIO, 0xa0b2, &mmPA_SC_VPORT_SCISSOR_15_TL[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_TL)/sizeof(mmPA_SC_VPORT_SCISSOR_15_TL[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_SCISSOR_15_BR", REG_MMIO, 0xa0b3, &mmPA_SC_VPORT_SCISSOR_15_BR[0], sizeof(mmPA_SC_VPORT_SCISSOR_15_BR)/sizeof(mmPA_SC_VPORT_SCISSOR_15_BR[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_0", REG_MMIO, 0xa0b4, &mmPA_SC_VPORT_ZMIN_0[0], sizeof(mmPA_SC_VPORT_ZMIN_0)/sizeof(mmPA_SC_VPORT_ZMIN_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_0", REG_MMIO, 0xa0b5, &mmPA_SC_VPORT_ZMAX_0[0], sizeof(mmPA_SC_VPORT_ZMAX_0)/sizeof(mmPA_SC_VPORT_ZMAX_0[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_1", REG_MMIO, 0xa0b6, &mmPA_SC_VPORT_ZMIN_1[0], sizeof(mmPA_SC_VPORT_ZMIN_1)/sizeof(mmPA_SC_VPORT_ZMIN_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_1", REG_MMIO, 0xa0b7, &mmPA_SC_VPORT_ZMAX_1[0], sizeof(mmPA_SC_VPORT_ZMAX_1)/sizeof(mmPA_SC_VPORT_ZMAX_1[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_2", REG_MMIO, 0xa0b8, &mmPA_SC_VPORT_ZMIN_2[0], sizeof(mmPA_SC_VPORT_ZMIN_2)/sizeof(mmPA_SC_VPORT_ZMIN_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_2", REG_MMIO, 0xa0b9, &mmPA_SC_VPORT_ZMAX_2[0], sizeof(mmPA_SC_VPORT_ZMAX_2)/sizeof(mmPA_SC_VPORT_ZMAX_2[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_3", REG_MMIO, 0xa0ba, &mmPA_SC_VPORT_ZMIN_3[0], sizeof(mmPA_SC_VPORT_ZMIN_3)/sizeof(mmPA_SC_VPORT_ZMIN_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_3", REG_MMIO, 0xa0bb, &mmPA_SC_VPORT_ZMAX_3[0], sizeof(mmPA_SC_VPORT_ZMAX_3)/sizeof(mmPA_SC_VPORT_ZMAX_3[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_4", REG_MMIO, 0xa0bc, &mmPA_SC_VPORT_ZMIN_4[0], sizeof(mmPA_SC_VPORT_ZMIN_4)/sizeof(mmPA_SC_VPORT_ZMIN_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_4", REG_MMIO, 0xa0bd, &mmPA_SC_VPORT_ZMAX_4[0], sizeof(mmPA_SC_VPORT_ZMAX_4)/sizeof(mmPA_SC_VPORT_ZMAX_4[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_5", REG_MMIO, 0xa0be, &mmPA_SC_VPORT_ZMIN_5[0], sizeof(mmPA_SC_VPORT_ZMIN_5)/sizeof(mmPA_SC_VPORT_ZMIN_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_5", REG_MMIO, 0xa0bf, &mmPA_SC_VPORT_ZMAX_5[0], sizeof(mmPA_SC_VPORT_ZMAX_5)/sizeof(mmPA_SC_VPORT_ZMAX_5[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_6", REG_MMIO, 0xa0c0, &mmPA_SC_VPORT_ZMIN_6[0], sizeof(mmPA_SC_VPORT_ZMIN_6)/sizeof(mmPA_SC_VPORT_ZMIN_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_6", REG_MMIO, 0xa0c1, &mmPA_SC_VPORT_ZMAX_6[0], sizeof(mmPA_SC_VPORT_ZMAX_6)/sizeof(mmPA_SC_VPORT_ZMAX_6[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_7", REG_MMIO, 0xa0c2, &mmPA_SC_VPORT_ZMIN_7[0], sizeof(mmPA_SC_VPORT_ZMIN_7)/sizeof(mmPA_SC_VPORT_ZMIN_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_7", REG_MMIO, 0xa0c3, &mmPA_SC_VPORT_ZMAX_7[0], sizeof(mmPA_SC_VPORT_ZMAX_7)/sizeof(mmPA_SC_VPORT_ZMAX_7[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_8", REG_MMIO, 0xa0c4, &mmPA_SC_VPORT_ZMIN_8[0], sizeof(mmPA_SC_VPORT_ZMIN_8)/sizeof(mmPA_SC_VPORT_ZMIN_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_8", REG_MMIO, 0xa0c5, &mmPA_SC_VPORT_ZMAX_8[0], sizeof(mmPA_SC_VPORT_ZMAX_8)/sizeof(mmPA_SC_VPORT_ZMAX_8[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_9", REG_MMIO, 0xa0c6, &mmPA_SC_VPORT_ZMIN_9[0], sizeof(mmPA_SC_VPORT_ZMIN_9)/sizeof(mmPA_SC_VPORT_ZMIN_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_9", REG_MMIO, 0xa0c7, &mmPA_SC_VPORT_ZMAX_9[0], sizeof(mmPA_SC_VPORT_ZMAX_9)/sizeof(mmPA_SC_VPORT_ZMAX_9[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_10", REG_MMIO, 0xa0c8, &mmPA_SC_VPORT_ZMIN_10[0], sizeof(mmPA_SC_VPORT_ZMIN_10)/sizeof(mmPA_SC_VPORT_ZMIN_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_10", REG_MMIO, 0xa0c9, &mmPA_SC_VPORT_ZMAX_10[0], sizeof(mmPA_SC_VPORT_ZMAX_10)/sizeof(mmPA_SC_VPORT_ZMAX_10[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_11", REG_MMIO, 0xa0ca, &mmPA_SC_VPORT_ZMIN_11[0], sizeof(mmPA_SC_VPORT_ZMIN_11)/sizeof(mmPA_SC_VPORT_ZMIN_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_11", REG_MMIO, 0xa0cb, &mmPA_SC_VPORT_ZMAX_11[0], sizeof(mmPA_SC_VPORT_ZMAX_11)/sizeof(mmPA_SC_VPORT_ZMAX_11[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_12", REG_MMIO, 0xa0cc, &mmPA_SC_VPORT_ZMIN_12[0], sizeof(mmPA_SC_VPORT_ZMIN_12)/sizeof(mmPA_SC_VPORT_ZMIN_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_12", REG_MMIO, 0xa0cd, &mmPA_SC_VPORT_ZMAX_12[0], sizeof(mmPA_SC_VPORT_ZMAX_12)/sizeof(mmPA_SC_VPORT_ZMAX_12[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_13", REG_MMIO, 0xa0ce, &mmPA_SC_VPORT_ZMIN_13[0], sizeof(mmPA_SC_VPORT_ZMIN_13)/sizeof(mmPA_SC_VPORT_ZMIN_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_13", REG_MMIO, 0xa0cf, &mmPA_SC_VPORT_ZMAX_13[0], sizeof(mmPA_SC_VPORT_ZMAX_13)/sizeof(mmPA_SC_VPORT_ZMAX_13[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_14", REG_MMIO, 0xa0d0, &mmPA_SC_VPORT_ZMIN_14[0], sizeof(mmPA_SC_VPORT_ZMIN_14)/sizeof(mmPA_SC_VPORT_ZMIN_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_14", REG_MMIO, 0xa0d1, &mmPA_SC_VPORT_ZMAX_14[0], sizeof(mmPA_SC_VPORT_ZMAX_14)/sizeof(mmPA_SC_VPORT_ZMAX_14[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMIN_15", REG_MMIO, 0xa0d2, &mmPA_SC_VPORT_ZMIN_15[0], sizeof(mmPA_SC_VPORT_ZMIN_15)/sizeof(mmPA_SC_VPORT_ZMIN_15[0]), 0, 0 },
+	{ "mmPA_SC_VPORT_ZMAX_15", REG_MMIO, 0xa0d3, &mmPA_SC_VPORT_ZMAX_15[0], sizeof(mmPA_SC_VPORT_ZMAX_15)/sizeof(mmPA_SC_VPORT_ZMAX_15[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG", REG_MMIO, 0xa0d4, &mmPA_SC_RASTER_CONFIG[0], sizeof(mmPA_SC_RASTER_CONFIG)/sizeof(mmPA_SC_RASTER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_RASTER_CONFIG_1", REG_MMIO, 0xa0d5, &mmPA_SC_RASTER_CONFIG_1[0], sizeof(mmPA_SC_RASTER_CONFIG_1)/sizeof(mmPA_SC_RASTER_CONFIG_1[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_CONTROL", REG_MMIO, 0xa0d6, &mmPA_SC_SCREEN_EXTENT_CONTROL[0], sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL)/sizeof(mmPA_SC_SCREEN_EXTENT_CONTROL[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTX_CNTL", REG_MMIO, 0xa0d8, &mmCP_PERFMON_CNTX_CNTL[0], sizeof(mmCP_PERFMON_CNTX_CNTL)/sizeof(mmCP_PERFMON_CNTX_CNTL[0]), 0, 0 },
+	{ "mmCP_RINGID", REG_MMIO, 0xa0d9, &mmCP_RINGID[0], sizeof(mmCP_RINGID)/sizeof(mmCP_RINGID[0]), 0, 0 },
+	{ "mmCP_VMID", REG_MMIO, 0xa0da, &mmCP_VMID[0], sizeof(mmCP_VMID)/sizeof(mmCP_VMID[0]), 0, 0 },
+	{ "mmVGT_MAX_VTX_INDX", REG_MMIO, 0xa100, &mmVGT_MAX_VTX_INDX[0], sizeof(mmVGT_MAX_VTX_INDX)/sizeof(mmVGT_MAX_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_MIN_VTX_INDX", REG_MMIO, 0xa101, &mmVGT_MIN_VTX_INDX[0], sizeof(mmVGT_MIN_VTX_INDX)/sizeof(mmVGT_MIN_VTX_INDX[0]), 0, 0 },
+	{ "mmVGT_INDX_OFFSET", REG_MMIO, 0xa102, &mmVGT_INDX_OFFSET[0], sizeof(mmVGT_INDX_OFFSET)/sizeof(mmVGT_INDX_OFFSET[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_INDX", REG_MMIO, 0xa103, &mmVGT_MULTI_PRIM_IB_RESET_INDX[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_INDX[0]), 0, 0 },
+	{ "mmCB_BLEND_RED", REG_MMIO, 0xa105, &mmCB_BLEND_RED[0], sizeof(mmCB_BLEND_RED)/sizeof(mmCB_BLEND_RED[0]), 0, 0 },
+	{ "mmCB_BLEND_GREEN", REG_MMIO, 0xa106, &mmCB_BLEND_GREEN[0], sizeof(mmCB_BLEND_GREEN)/sizeof(mmCB_BLEND_GREEN[0]), 0, 0 },
+	{ "mmCB_BLEND_BLUE", REG_MMIO, 0xa107, &mmCB_BLEND_BLUE[0], sizeof(mmCB_BLEND_BLUE)/sizeof(mmCB_BLEND_BLUE[0]), 0, 0 },
+	{ "mmCB_BLEND_ALPHA", REG_MMIO, 0xa108, &mmCB_BLEND_ALPHA[0], sizeof(mmCB_BLEND_ALPHA)/sizeof(mmCB_BLEND_ALPHA[0]), 0, 0 },
+	{ "mmCB_DCC_CONTROL", REG_MMIO, 0xa109, &mmCB_DCC_CONTROL[0], sizeof(mmCB_DCC_CONTROL)/sizeof(mmCB_DCC_CONTROL[0]), 0, 0 },
+	{ "mmDB_STENCIL_CONTROL", REG_MMIO, 0xa10b, &mmDB_STENCIL_CONTROL[0], sizeof(mmDB_STENCIL_CONTROL)/sizeof(mmDB_STENCIL_CONTROL[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK", REG_MMIO, 0xa10c, &mmDB_STENCILREFMASK[0], sizeof(mmDB_STENCILREFMASK)/sizeof(mmDB_STENCILREFMASK[0]), 0, 0 },
+	{ "mmDB_STENCILREFMASK_BF", REG_MMIO, 0xa10d, &mmDB_STENCILREFMASK_BF[0], sizeof(mmDB_STENCILREFMASK_BF)/sizeof(mmDB_STENCILREFMASK_BF[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE", REG_MMIO, 0xa10f, &mmPA_CL_VPORT_XSCALE[0], sizeof(mmPA_CL_VPORT_XSCALE)/sizeof(mmPA_CL_VPORT_XSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET", REG_MMIO, 0xa110, &mmPA_CL_VPORT_XOFFSET[0], sizeof(mmPA_CL_VPORT_XOFFSET)/sizeof(mmPA_CL_VPORT_XOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE", REG_MMIO, 0xa111, &mmPA_CL_VPORT_YSCALE[0], sizeof(mmPA_CL_VPORT_YSCALE)/sizeof(mmPA_CL_VPORT_YSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET", REG_MMIO, 0xa112, &mmPA_CL_VPORT_YOFFSET[0], sizeof(mmPA_CL_VPORT_YOFFSET)/sizeof(mmPA_CL_VPORT_YOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE", REG_MMIO, 0xa113, &mmPA_CL_VPORT_ZSCALE[0], sizeof(mmPA_CL_VPORT_ZSCALE)/sizeof(mmPA_CL_VPORT_ZSCALE[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET", REG_MMIO, 0xa114, &mmPA_CL_VPORT_ZOFFSET[0], sizeof(mmPA_CL_VPORT_ZOFFSET)/sizeof(mmPA_CL_VPORT_ZOFFSET[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_1", REG_MMIO, 0xa115, &mmPA_CL_VPORT_XSCALE_1[0], sizeof(mmPA_CL_VPORT_XSCALE_1)/sizeof(mmPA_CL_VPORT_XSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_1", REG_MMIO, 0xa116, &mmPA_CL_VPORT_XOFFSET_1[0], sizeof(mmPA_CL_VPORT_XOFFSET_1)/sizeof(mmPA_CL_VPORT_XOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_1", REG_MMIO, 0xa117, &mmPA_CL_VPORT_YSCALE_1[0], sizeof(mmPA_CL_VPORT_YSCALE_1)/sizeof(mmPA_CL_VPORT_YSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_1", REG_MMIO, 0xa118, &mmPA_CL_VPORT_YOFFSET_1[0], sizeof(mmPA_CL_VPORT_YOFFSET_1)/sizeof(mmPA_CL_VPORT_YOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_1", REG_MMIO, 0xa119, &mmPA_CL_VPORT_ZSCALE_1[0], sizeof(mmPA_CL_VPORT_ZSCALE_1)/sizeof(mmPA_CL_VPORT_ZSCALE_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_1", REG_MMIO, 0xa11a, &mmPA_CL_VPORT_ZOFFSET_1[0], sizeof(mmPA_CL_VPORT_ZOFFSET_1)/sizeof(mmPA_CL_VPORT_ZOFFSET_1[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_2", REG_MMIO, 0xa11b, &mmPA_CL_VPORT_XSCALE_2[0], sizeof(mmPA_CL_VPORT_XSCALE_2)/sizeof(mmPA_CL_VPORT_XSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_2", REG_MMIO, 0xa11c, &mmPA_CL_VPORT_XOFFSET_2[0], sizeof(mmPA_CL_VPORT_XOFFSET_2)/sizeof(mmPA_CL_VPORT_XOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_2", REG_MMIO, 0xa11d, &mmPA_CL_VPORT_YSCALE_2[0], sizeof(mmPA_CL_VPORT_YSCALE_2)/sizeof(mmPA_CL_VPORT_YSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_2", REG_MMIO, 0xa11e, &mmPA_CL_VPORT_YOFFSET_2[0], sizeof(mmPA_CL_VPORT_YOFFSET_2)/sizeof(mmPA_CL_VPORT_YOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_2", REG_MMIO, 0xa11f, &mmPA_CL_VPORT_ZSCALE_2[0], sizeof(mmPA_CL_VPORT_ZSCALE_2)/sizeof(mmPA_CL_VPORT_ZSCALE_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_2", REG_MMIO, 0xa120, &mmPA_CL_VPORT_ZOFFSET_2[0], sizeof(mmPA_CL_VPORT_ZOFFSET_2)/sizeof(mmPA_CL_VPORT_ZOFFSET_2[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_3", REG_MMIO, 0xa121, &mmPA_CL_VPORT_XSCALE_3[0], sizeof(mmPA_CL_VPORT_XSCALE_3)/sizeof(mmPA_CL_VPORT_XSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_3", REG_MMIO, 0xa122, &mmPA_CL_VPORT_XOFFSET_3[0], sizeof(mmPA_CL_VPORT_XOFFSET_3)/sizeof(mmPA_CL_VPORT_XOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_3", REG_MMIO, 0xa123, &mmPA_CL_VPORT_YSCALE_3[0], sizeof(mmPA_CL_VPORT_YSCALE_3)/sizeof(mmPA_CL_VPORT_YSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_3", REG_MMIO, 0xa124, &mmPA_CL_VPORT_YOFFSET_3[0], sizeof(mmPA_CL_VPORT_YOFFSET_3)/sizeof(mmPA_CL_VPORT_YOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_3", REG_MMIO, 0xa125, &mmPA_CL_VPORT_ZSCALE_3[0], sizeof(mmPA_CL_VPORT_ZSCALE_3)/sizeof(mmPA_CL_VPORT_ZSCALE_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_3", REG_MMIO, 0xa126, &mmPA_CL_VPORT_ZOFFSET_3[0], sizeof(mmPA_CL_VPORT_ZOFFSET_3)/sizeof(mmPA_CL_VPORT_ZOFFSET_3[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_4", REG_MMIO, 0xa127, &mmPA_CL_VPORT_XSCALE_4[0], sizeof(mmPA_CL_VPORT_XSCALE_4)/sizeof(mmPA_CL_VPORT_XSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_4", REG_MMIO, 0xa128, &mmPA_CL_VPORT_XOFFSET_4[0], sizeof(mmPA_CL_VPORT_XOFFSET_4)/sizeof(mmPA_CL_VPORT_XOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_4", REG_MMIO, 0xa129, &mmPA_CL_VPORT_YSCALE_4[0], sizeof(mmPA_CL_VPORT_YSCALE_4)/sizeof(mmPA_CL_VPORT_YSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_4", REG_MMIO, 0xa12a, &mmPA_CL_VPORT_YOFFSET_4[0], sizeof(mmPA_CL_VPORT_YOFFSET_4)/sizeof(mmPA_CL_VPORT_YOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_4", REG_MMIO, 0xa12b, &mmPA_CL_VPORT_ZSCALE_4[0], sizeof(mmPA_CL_VPORT_ZSCALE_4)/sizeof(mmPA_CL_VPORT_ZSCALE_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_4", REG_MMIO, 0xa12c, &mmPA_CL_VPORT_ZOFFSET_4[0], sizeof(mmPA_CL_VPORT_ZOFFSET_4)/sizeof(mmPA_CL_VPORT_ZOFFSET_4[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_5", REG_MMIO, 0xa12d, &mmPA_CL_VPORT_XSCALE_5[0], sizeof(mmPA_CL_VPORT_XSCALE_5)/sizeof(mmPA_CL_VPORT_XSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_5", REG_MMIO, 0xa12e, &mmPA_CL_VPORT_XOFFSET_5[0], sizeof(mmPA_CL_VPORT_XOFFSET_5)/sizeof(mmPA_CL_VPORT_XOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_5", REG_MMIO, 0xa12f, &mmPA_CL_VPORT_YSCALE_5[0], sizeof(mmPA_CL_VPORT_YSCALE_5)/sizeof(mmPA_CL_VPORT_YSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_5", REG_MMIO, 0xa130, &mmPA_CL_VPORT_YOFFSET_5[0], sizeof(mmPA_CL_VPORT_YOFFSET_5)/sizeof(mmPA_CL_VPORT_YOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_5", REG_MMIO, 0xa131, &mmPA_CL_VPORT_ZSCALE_5[0], sizeof(mmPA_CL_VPORT_ZSCALE_5)/sizeof(mmPA_CL_VPORT_ZSCALE_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_5", REG_MMIO, 0xa132, &mmPA_CL_VPORT_ZOFFSET_5[0], sizeof(mmPA_CL_VPORT_ZOFFSET_5)/sizeof(mmPA_CL_VPORT_ZOFFSET_5[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_6", REG_MMIO, 0xa133, &mmPA_CL_VPORT_XSCALE_6[0], sizeof(mmPA_CL_VPORT_XSCALE_6)/sizeof(mmPA_CL_VPORT_XSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_6", REG_MMIO, 0xa134, &mmPA_CL_VPORT_XOFFSET_6[0], sizeof(mmPA_CL_VPORT_XOFFSET_6)/sizeof(mmPA_CL_VPORT_XOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_6", REG_MMIO, 0xa135, &mmPA_CL_VPORT_YSCALE_6[0], sizeof(mmPA_CL_VPORT_YSCALE_6)/sizeof(mmPA_CL_VPORT_YSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_6", REG_MMIO, 0xa136, &mmPA_CL_VPORT_YOFFSET_6[0], sizeof(mmPA_CL_VPORT_YOFFSET_6)/sizeof(mmPA_CL_VPORT_YOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_6", REG_MMIO, 0xa137, &mmPA_CL_VPORT_ZSCALE_6[0], sizeof(mmPA_CL_VPORT_ZSCALE_6)/sizeof(mmPA_CL_VPORT_ZSCALE_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_6", REG_MMIO, 0xa138, &mmPA_CL_VPORT_ZOFFSET_6[0], sizeof(mmPA_CL_VPORT_ZOFFSET_6)/sizeof(mmPA_CL_VPORT_ZOFFSET_6[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_7", REG_MMIO, 0xa139, &mmPA_CL_VPORT_XSCALE_7[0], sizeof(mmPA_CL_VPORT_XSCALE_7)/sizeof(mmPA_CL_VPORT_XSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_7", REG_MMIO, 0xa13a, &mmPA_CL_VPORT_XOFFSET_7[0], sizeof(mmPA_CL_VPORT_XOFFSET_7)/sizeof(mmPA_CL_VPORT_XOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_7", REG_MMIO, 0xa13b, &mmPA_CL_VPORT_YSCALE_7[0], sizeof(mmPA_CL_VPORT_YSCALE_7)/sizeof(mmPA_CL_VPORT_YSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_7", REG_MMIO, 0xa13c, &mmPA_CL_VPORT_YOFFSET_7[0], sizeof(mmPA_CL_VPORT_YOFFSET_7)/sizeof(mmPA_CL_VPORT_YOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_7", REG_MMIO, 0xa13d, &mmPA_CL_VPORT_ZSCALE_7[0], sizeof(mmPA_CL_VPORT_ZSCALE_7)/sizeof(mmPA_CL_VPORT_ZSCALE_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_7", REG_MMIO, 0xa13e, &mmPA_CL_VPORT_ZOFFSET_7[0], sizeof(mmPA_CL_VPORT_ZOFFSET_7)/sizeof(mmPA_CL_VPORT_ZOFFSET_7[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_8", REG_MMIO, 0xa13f, &mmPA_CL_VPORT_XSCALE_8[0], sizeof(mmPA_CL_VPORT_XSCALE_8)/sizeof(mmPA_CL_VPORT_XSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_8", REG_MMIO, 0xa140, &mmPA_CL_VPORT_XOFFSET_8[0], sizeof(mmPA_CL_VPORT_XOFFSET_8)/sizeof(mmPA_CL_VPORT_XOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_8", REG_MMIO, 0xa141, &mmPA_CL_VPORT_YSCALE_8[0], sizeof(mmPA_CL_VPORT_YSCALE_8)/sizeof(mmPA_CL_VPORT_YSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_8", REG_MMIO, 0xa142, &mmPA_CL_VPORT_YOFFSET_8[0], sizeof(mmPA_CL_VPORT_YOFFSET_8)/sizeof(mmPA_CL_VPORT_YOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_8", REG_MMIO, 0xa143, &mmPA_CL_VPORT_ZSCALE_8[0], sizeof(mmPA_CL_VPORT_ZSCALE_8)/sizeof(mmPA_CL_VPORT_ZSCALE_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_8", REG_MMIO, 0xa144, &mmPA_CL_VPORT_ZOFFSET_8[0], sizeof(mmPA_CL_VPORT_ZOFFSET_8)/sizeof(mmPA_CL_VPORT_ZOFFSET_8[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_9", REG_MMIO, 0xa145, &mmPA_CL_VPORT_XSCALE_9[0], sizeof(mmPA_CL_VPORT_XSCALE_9)/sizeof(mmPA_CL_VPORT_XSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_9", REG_MMIO, 0xa146, &mmPA_CL_VPORT_XOFFSET_9[0], sizeof(mmPA_CL_VPORT_XOFFSET_9)/sizeof(mmPA_CL_VPORT_XOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_9", REG_MMIO, 0xa147, &mmPA_CL_VPORT_YSCALE_9[0], sizeof(mmPA_CL_VPORT_YSCALE_9)/sizeof(mmPA_CL_VPORT_YSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_9", REG_MMIO, 0xa148, &mmPA_CL_VPORT_YOFFSET_9[0], sizeof(mmPA_CL_VPORT_YOFFSET_9)/sizeof(mmPA_CL_VPORT_YOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_9", REG_MMIO, 0xa149, &mmPA_CL_VPORT_ZSCALE_9[0], sizeof(mmPA_CL_VPORT_ZSCALE_9)/sizeof(mmPA_CL_VPORT_ZSCALE_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_9", REG_MMIO, 0xa14a, &mmPA_CL_VPORT_ZOFFSET_9[0], sizeof(mmPA_CL_VPORT_ZOFFSET_9)/sizeof(mmPA_CL_VPORT_ZOFFSET_9[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_10", REG_MMIO, 0xa14b, &mmPA_CL_VPORT_XSCALE_10[0], sizeof(mmPA_CL_VPORT_XSCALE_10)/sizeof(mmPA_CL_VPORT_XSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_10", REG_MMIO, 0xa14c, &mmPA_CL_VPORT_XOFFSET_10[0], sizeof(mmPA_CL_VPORT_XOFFSET_10)/sizeof(mmPA_CL_VPORT_XOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_10", REG_MMIO, 0xa14d, &mmPA_CL_VPORT_YSCALE_10[0], sizeof(mmPA_CL_VPORT_YSCALE_10)/sizeof(mmPA_CL_VPORT_YSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_10", REG_MMIO, 0xa14e, &mmPA_CL_VPORT_YOFFSET_10[0], sizeof(mmPA_CL_VPORT_YOFFSET_10)/sizeof(mmPA_CL_VPORT_YOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_10", REG_MMIO, 0xa14f, &mmPA_CL_VPORT_ZSCALE_10[0], sizeof(mmPA_CL_VPORT_ZSCALE_10)/sizeof(mmPA_CL_VPORT_ZSCALE_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_10", REG_MMIO, 0xa150, &mmPA_CL_VPORT_ZOFFSET_10[0], sizeof(mmPA_CL_VPORT_ZOFFSET_10)/sizeof(mmPA_CL_VPORT_ZOFFSET_10[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_11", REG_MMIO, 0xa151, &mmPA_CL_VPORT_XSCALE_11[0], sizeof(mmPA_CL_VPORT_XSCALE_11)/sizeof(mmPA_CL_VPORT_XSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_11", REG_MMIO, 0xa152, &mmPA_CL_VPORT_XOFFSET_11[0], sizeof(mmPA_CL_VPORT_XOFFSET_11)/sizeof(mmPA_CL_VPORT_XOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_11", REG_MMIO, 0xa153, &mmPA_CL_VPORT_YSCALE_11[0], sizeof(mmPA_CL_VPORT_YSCALE_11)/sizeof(mmPA_CL_VPORT_YSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_11", REG_MMIO, 0xa154, &mmPA_CL_VPORT_YOFFSET_11[0], sizeof(mmPA_CL_VPORT_YOFFSET_11)/sizeof(mmPA_CL_VPORT_YOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_11", REG_MMIO, 0xa155, &mmPA_CL_VPORT_ZSCALE_11[0], sizeof(mmPA_CL_VPORT_ZSCALE_11)/sizeof(mmPA_CL_VPORT_ZSCALE_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_11", REG_MMIO, 0xa156, &mmPA_CL_VPORT_ZOFFSET_11[0], sizeof(mmPA_CL_VPORT_ZOFFSET_11)/sizeof(mmPA_CL_VPORT_ZOFFSET_11[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_12", REG_MMIO, 0xa157, &mmPA_CL_VPORT_XSCALE_12[0], sizeof(mmPA_CL_VPORT_XSCALE_12)/sizeof(mmPA_CL_VPORT_XSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_12", REG_MMIO, 0xa158, &mmPA_CL_VPORT_XOFFSET_12[0], sizeof(mmPA_CL_VPORT_XOFFSET_12)/sizeof(mmPA_CL_VPORT_XOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_12", REG_MMIO, 0xa159, &mmPA_CL_VPORT_YSCALE_12[0], sizeof(mmPA_CL_VPORT_YSCALE_12)/sizeof(mmPA_CL_VPORT_YSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_12", REG_MMIO, 0xa15a, &mmPA_CL_VPORT_YOFFSET_12[0], sizeof(mmPA_CL_VPORT_YOFFSET_12)/sizeof(mmPA_CL_VPORT_YOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_12", REG_MMIO, 0xa15b, &mmPA_CL_VPORT_ZSCALE_12[0], sizeof(mmPA_CL_VPORT_ZSCALE_12)/sizeof(mmPA_CL_VPORT_ZSCALE_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_12", REG_MMIO, 0xa15c, &mmPA_CL_VPORT_ZOFFSET_12[0], sizeof(mmPA_CL_VPORT_ZOFFSET_12)/sizeof(mmPA_CL_VPORT_ZOFFSET_12[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_13", REG_MMIO, 0xa15d, &mmPA_CL_VPORT_XSCALE_13[0], sizeof(mmPA_CL_VPORT_XSCALE_13)/sizeof(mmPA_CL_VPORT_XSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_13", REG_MMIO, 0xa15e, &mmPA_CL_VPORT_XOFFSET_13[0], sizeof(mmPA_CL_VPORT_XOFFSET_13)/sizeof(mmPA_CL_VPORT_XOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_13", REG_MMIO, 0xa15f, &mmPA_CL_VPORT_YSCALE_13[0], sizeof(mmPA_CL_VPORT_YSCALE_13)/sizeof(mmPA_CL_VPORT_YSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_13", REG_MMIO, 0xa160, &mmPA_CL_VPORT_YOFFSET_13[0], sizeof(mmPA_CL_VPORT_YOFFSET_13)/sizeof(mmPA_CL_VPORT_YOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_13", REG_MMIO, 0xa161, &mmPA_CL_VPORT_ZSCALE_13[0], sizeof(mmPA_CL_VPORT_ZSCALE_13)/sizeof(mmPA_CL_VPORT_ZSCALE_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_13", REG_MMIO, 0xa162, &mmPA_CL_VPORT_ZOFFSET_13[0], sizeof(mmPA_CL_VPORT_ZOFFSET_13)/sizeof(mmPA_CL_VPORT_ZOFFSET_13[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_14", REG_MMIO, 0xa163, &mmPA_CL_VPORT_XSCALE_14[0], sizeof(mmPA_CL_VPORT_XSCALE_14)/sizeof(mmPA_CL_VPORT_XSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_14", REG_MMIO, 0xa164, &mmPA_CL_VPORT_XOFFSET_14[0], sizeof(mmPA_CL_VPORT_XOFFSET_14)/sizeof(mmPA_CL_VPORT_XOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_14", REG_MMIO, 0xa165, &mmPA_CL_VPORT_YSCALE_14[0], sizeof(mmPA_CL_VPORT_YSCALE_14)/sizeof(mmPA_CL_VPORT_YSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_14", REG_MMIO, 0xa166, &mmPA_CL_VPORT_YOFFSET_14[0], sizeof(mmPA_CL_VPORT_YOFFSET_14)/sizeof(mmPA_CL_VPORT_YOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_14", REG_MMIO, 0xa167, &mmPA_CL_VPORT_ZSCALE_14[0], sizeof(mmPA_CL_VPORT_ZSCALE_14)/sizeof(mmPA_CL_VPORT_ZSCALE_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_14", REG_MMIO, 0xa168, &mmPA_CL_VPORT_ZOFFSET_14[0], sizeof(mmPA_CL_VPORT_ZOFFSET_14)/sizeof(mmPA_CL_VPORT_ZOFFSET_14[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XSCALE_15", REG_MMIO, 0xa169, &mmPA_CL_VPORT_XSCALE_15[0], sizeof(mmPA_CL_VPORT_XSCALE_15)/sizeof(mmPA_CL_VPORT_XSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_XOFFSET_15", REG_MMIO, 0xa16a, &mmPA_CL_VPORT_XOFFSET_15[0], sizeof(mmPA_CL_VPORT_XOFFSET_15)/sizeof(mmPA_CL_VPORT_XOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YSCALE_15", REG_MMIO, 0xa16b, &mmPA_CL_VPORT_YSCALE_15[0], sizeof(mmPA_CL_VPORT_YSCALE_15)/sizeof(mmPA_CL_VPORT_YSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_YOFFSET_15", REG_MMIO, 0xa16c, &mmPA_CL_VPORT_YOFFSET_15[0], sizeof(mmPA_CL_VPORT_YOFFSET_15)/sizeof(mmPA_CL_VPORT_YOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZSCALE_15", REG_MMIO, 0xa16d, &mmPA_CL_VPORT_ZSCALE_15[0], sizeof(mmPA_CL_VPORT_ZSCALE_15)/sizeof(mmPA_CL_VPORT_ZSCALE_15[0]), 0, 0 },
+	{ "mmPA_CL_VPORT_ZOFFSET_15", REG_MMIO, 0xa16e, &mmPA_CL_VPORT_ZOFFSET_15[0], sizeof(mmPA_CL_VPORT_ZOFFSET_15)/sizeof(mmPA_CL_VPORT_ZOFFSET_15[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_X", REG_MMIO, 0xa16f, &mmPA_CL_UCP_0_X[0], sizeof(mmPA_CL_UCP_0_X)/sizeof(mmPA_CL_UCP_0_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Y", REG_MMIO, 0xa170, &mmPA_CL_UCP_0_Y[0], sizeof(mmPA_CL_UCP_0_Y)/sizeof(mmPA_CL_UCP_0_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_Z", REG_MMIO, 0xa171, &mmPA_CL_UCP_0_Z[0], sizeof(mmPA_CL_UCP_0_Z)/sizeof(mmPA_CL_UCP_0_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_0_W", REG_MMIO, 0xa172, &mmPA_CL_UCP_0_W[0], sizeof(mmPA_CL_UCP_0_W)/sizeof(mmPA_CL_UCP_0_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_X", REG_MMIO, 0xa173, &mmPA_CL_UCP_1_X[0], sizeof(mmPA_CL_UCP_1_X)/sizeof(mmPA_CL_UCP_1_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Y", REG_MMIO, 0xa174, &mmPA_CL_UCP_1_Y[0], sizeof(mmPA_CL_UCP_1_Y)/sizeof(mmPA_CL_UCP_1_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_Z", REG_MMIO, 0xa175, &mmPA_CL_UCP_1_Z[0], sizeof(mmPA_CL_UCP_1_Z)/sizeof(mmPA_CL_UCP_1_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_1_W", REG_MMIO, 0xa176, &mmPA_CL_UCP_1_W[0], sizeof(mmPA_CL_UCP_1_W)/sizeof(mmPA_CL_UCP_1_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_X", REG_MMIO, 0xa177, &mmPA_CL_UCP_2_X[0], sizeof(mmPA_CL_UCP_2_X)/sizeof(mmPA_CL_UCP_2_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Y", REG_MMIO, 0xa178, &mmPA_CL_UCP_2_Y[0], sizeof(mmPA_CL_UCP_2_Y)/sizeof(mmPA_CL_UCP_2_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_Z", REG_MMIO, 0xa179, &mmPA_CL_UCP_2_Z[0], sizeof(mmPA_CL_UCP_2_Z)/sizeof(mmPA_CL_UCP_2_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_2_W", REG_MMIO, 0xa17a, &mmPA_CL_UCP_2_W[0], sizeof(mmPA_CL_UCP_2_W)/sizeof(mmPA_CL_UCP_2_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_X", REG_MMIO, 0xa17b, &mmPA_CL_UCP_3_X[0], sizeof(mmPA_CL_UCP_3_X)/sizeof(mmPA_CL_UCP_3_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Y", REG_MMIO, 0xa17c, &mmPA_CL_UCP_3_Y[0], sizeof(mmPA_CL_UCP_3_Y)/sizeof(mmPA_CL_UCP_3_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_Z", REG_MMIO, 0xa17d, &mmPA_CL_UCP_3_Z[0], sizeof(mmPA_CL_UCP_3_Z)/sizeof(mmPA_CL_UCP_3_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_3_W", REG_MMIO, 0xa17e, &mmPA_CL_UCP_3_W[0], sizeof(mmPA_CL_UCP_3_W)/sizeof(mmPA_CL_UCP_3_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_X", REG_MMIO, 0xa17f, &mmPA_CL_UCP_4_X[0], sizeof(mmPA_CL_UCP_4_X)/sizeof(mmPA_CL_UCP_4_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Y", REG_MMIO, 0xa180, &mmPA_CL_UCP_4_Y[0], sizeof(mmPA_CL_UCP_4_Y)/sizeof(mmPA_CL_UCP_4_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_Z", REG_MMIO, 0xa181, &mmPA_CL_UCP_4_Z[0], sizeof(mmPA_CL_UCP_4_Z)/sizeof(mmPA_CL_UCP_4_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_4_W", REG_MMIO, 0xa182, &mmPA_CL_UCP_4_W[0], sizeof(mmPA_CL_UCP_4_W)/sizeof(mmPA_CL_UCP_4_W[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_X", REG_MMIO, 0xa183, &mmPA_CL_UCP_5_X[0], sizeof(mmPA_CL_UCP_5_X)/sizeof(mmPA_CL_UCP_5_X[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Y", REG_MMIO, 0xa184, &mmPA_CL_UCP_5_Y[0], sizeof(mmPA_CL_UCP_5_Y)/sizeof(mmPA_CL_UCP_5_Y[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_Z", REG_MMIO, 0xa185, &mmPA_CL_UCP_5_Z[0], sizeof(mmPA_CL_UCP_5_Z)/sizeof(mmPA_CL_UCP_5_Z[0]), 0, 0 },
+	{ "mmPA_CL_UCP_5_W", REG_MMIO, 0xa186, &mmPA_CL_UCP_5_W[0], sizeof(mmPA_CL_UCP_5_W)/sizeof(mmPA_CL_UCP_5_W[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_0", REG_MMIO, 0xa191, &mmSPI_PS_INPUT_CNTL_0[0], sizeof(mmSPI_PS_INPUT_CNTL_0)/sizeof(mmSPI_PS_INPUT_CNTL_0[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_1", REG_MMIO, 0xa192, &mmSPI_PS_INPUT_CNTL_1[0], sizeof(mmSPI_PS_INPUT_CNTL_1)/sizeof(mmSPI_PS_INPUT_CNTL_1[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_2", REG_MMIO, 0xa193, &mmSPI_PS_INPUT_CNTL_2[0], sizeof(mmSPI_PS_INPUT_CNTL_2)/sizeof(mmSPI_PS_INPUT_CNTL_2[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_3", REG_MMIO, 0xa194, &mmSPI_PS_INPUT_CNTL_3[0], sizeof(mmSPI_PS_INPUT_CNTL_3)/sizeof(mmSPI_PS_INPUT_CNTL_3[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_4", REG_MMIO, 0xa195, &mmSPI_PS_INPUT_CNTL_4[0], sizeof(mmSPI_PS_INPUT_CNTL_4)/sizeof(mmSPI_PS_INPUT_CNTL_4[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_5", REG_MMIO, 0xa196, &mmSPI_PS_INPUT_CNTL_5[0], sizeof(mmSPI_PS_INPUT_CNTL_5)/sizeof(mmSPI_PS_INPUT_CNTL_5[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_6", REG_MMIO, 0xa197, &mmSPI_PS_INPUT_CNTL_6[0], sizeof(mmSPI_PS_INPUT_CNTL_6)/sizeof(mmSPI_PS_INPUT_CNTL_6[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_7", REG_MMIO, 0xa198, &mmSPI_PS_INPUT_CNTL_7[0], sizeof(mmSPI_PS_INPUT_CNTL_7)/sizeof(mmSPI_PS_INPUT_CNTL_7[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_8", REG_MMIO, 0xa199, &mmSPI_PS_INPUT_CNTL_8[0], sizeof(mmSPI_PS_INPUT_CNTL_8)/sizeof(mmSPI_PS_INPUT_CNTL_8[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_9", REG_MMIO, 0xa19a, &mmSPI_PS_INPUT_CNTL_9[0], sizeof(mmSPI_PS_INPUT_CNTL_9)/sizeof(mmSPI_PS_INPUT_CNTL_9[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_10", REG_MMIO, 0xa19b, &mmSPI_PS_INPUT_CNTL_10[0], sizeof(mmSPI_PS_INPUT_CNTL_10)/sizeof(mmSPI_PS_INPUT_CNTL_10[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_11", REG_MMIO, 0xa19c, &mmSPI_PS_INPUT_CNTL_11[0], sizeof(mmSPI_PS_INPUT_CNTL_11)/sizeof(mmSPI_PS_INPUT_CNTL_11[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_12", REG_MMIO, 0xa19d, &mmSPI_PS_INPUT_CNTL_12[0], sizeof(mmSPI_PS_INPUT_CNTL_12)/sizeof(mmSPI_PS_INPUT_CNTL_12[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_13", REG_MMIO, 0xa19e, &mmSPI_PS_INPUT_CNTL_13[0], sizeof(mmSPI_PS_INPUT_CNTL_13)/sizeof(mmSPI_PS_INPUT_CNTL_13[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_14", REG_MMIO, 0xa19f, &mmSPI_PS_INPUT_CNTL_14[0], sizeof(mmSPI_PS_INPUT_CNTL_14)/sizeof(mmSPI_PS_INPUT_CNTL_14[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_15", REG_MMIO, 0xa1a0, &mmSPI_PS_INPUT_CNTL_15[0], sizeof(mmSPI_PS_INPUT_CNTL_15)/sizeof(mmSPI_PS_INPUT_CNTL_15[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_16", REG_MMIO, 0xa1a1, &mmSPI_PS_INPUT_CNTL_16[0], sizeof(mmSPI_PS_INPUT_CNTL_16)/sizeof(mmSPI_PS_INPUT_CNTL_16[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_17", REG_MMIO, 0xa1a2, &mmSPI_PS_INPUT_CNTL_17[0], sizeof(mmSPI_PS_INPUT_CNTL_17)/sizeof(mmSPI_PS_INPUT_CNTL_17[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_18", REG_MMIO, 0xa1a3, &mmSPI_PS_INPUT_CNTL_18[0], sizeof(mmSPI_PS_INPUT_CNTL_18)/sizeof(mmSPI_PS_INPUT_CNTL_18[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_19", REG_MMIO, 0xa1a4, &mmSPI_PS_INPUT_CNTL_19[0], sizeof(mmSPI_PS_INPUT_CNTL_19)/sizeof(mmSPI_PS_INPUT_CNTL_19[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_20", REG_MMIO, 0xa1a5, &mmSPI_PS_INPUT_CNTL_20[0], sizeof(mmSPI_PS_INPUT_CNTL_20)/sizeof(mmSPI_PS_INPUT_CNTL_20[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_21", REG_MMIO, 0xa1a6, &mmSPI_PS_INPUT_CNTL_21[0], sizeof(mmSPI_PS_INPUT_CNTL_21)/sizeof(mmSPI_PS_INPUT_CNTL_21[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_22", REG_MMIO, 0xa1a7, &mmSPI_PS_INPUT_CNTL_22[0], sizeof(mmSPI_PS_INPUT_CNTL_22)/sizeof(mmSPI_PS_INPUT_CNTL_22[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_23", REG_MMIO, 0xa1a8, &mmSPI_PS_INPUT_CNTL_23[0], sizeof(mmSPI_PS_INPUT_CNTL_23)/sizeof(mmSPI_PS_INPUT_CNTL_23[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_24", REG_MMIO, 0xa1a9, &mmSPI_PS_INPUT_CNTL_24[0], sizeof(mmSPI_PS_INPUT_CNTL_24)/sizeof(mmSPI_PS_INPUT_CNTL_24[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_25", REG_MMIO, 0xa1aa, &mmSPI_PS_INPUT_CNTL_25[0], sizeof(mmSPI_PS_INPUT_CNTL_25)/sizeof(mmSPI_PS_INPUT_CNTL_25[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_26", REG_MMIO, 0xa1ab, &mmSPI_PS_INPUT_CNTL_26[0], sizeof(mmSPI_PS_INPUT_CNTL_26)/sizeof(mmSPI_PS_INPUT_CNTL_26[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_27", REG_MMIO, 0xa1ac, &mmSPI_PS_INPUT_CNTL_27[0], sizeof(mmSPI_PS_INPUT_CNTL_27)/sizeof(mmSPI_PS_INPUT_CNTL_27[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_28", REG_MMIO, 0xa1ad, &mmSPI_PS_INPUT_CNTL_28[0], sizeof(mmSPI_PS_INPUT_CNTL_28)/sizeof(mmSPI_PS_INPUT_CNTL_28[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_29", REG_MMIO, 0xa1ae, &mmSPI_PS_INPUT_CNTL_29[0], sizeof(mmSPI_PS_INPUT_CNTL_29)/sizeof(mmSPI_PS_INPUT_CNTL_29[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_30", REG_MMIO, 0xa1af, &mmSPI_PS_INPUT_CNTL_30[0], sizeof(mmSPI_PS_INPUT_CNTL_30)/sizeof(mmSPI_PS_INPUT_CNTL_30[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_CNTL_31", REG_MMIO, 0xa1b0, &mmSPI_PS_INPUT_CNTL_31[0], sizeof(mmSPI_PS_INPUT_CNTL_31)/sizeof(mmSPI_PS_INPUT_CNTL_31[0]), 0, 0 },
+	{ "mmSPI_VS_OUT_CONFIG", REG_MMIO, 0xa1b1, &mmSPI_VS_OUT_CONFIG[0], sizeof(mmSPI_VS_OUT_CONFIG)/sizeof(mmSPI_VS_OUT_CONFIG[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ENA", REG_MMIO, 0xa1b3, &mmSPI_PS_INPUT_ENA[0], sizeof(mmSPI_PS_INPUT_ENA)/sizeof(mmSPI_PS_INPUT_ENA[0]), 0, 0 },
+	{ "mmSPI_PS_INPUT_ADDR", REG_MMIO, 0xa1b4, &mmSPI_PS_INPUT_ADDR[0], sizeof(mmSPI_PS_INPUT_ADDR)/sizeof(mmSPI_PS_INPUT_ADDR[0]), 0, 0 },
+	{ "mmSPI_INTERP_CONTROL_0", REG_MMIO, 0xa1b5, &mmSPI_INTERP_CONTROL_0[0], sizeof(mmSPI_INTERP_CONTROL_0)/sizeof(mmSPI_INTERP_CONTROL_0[0]), 0, 0 },
+	{ "mmSPI_PS_IN_CONTROL", REG_MMIO, 0xa1b6, &mmSPI_PS_IN_CONTROL[0], sizeof(mmSPI_PS_IN_CONTROL)/sizeof(mmSPI_PS_IN_CONTROL[0]), 0, 0 },
+	{ "mmSPI_BARYC_CNTL", REG_MMIO, 0xa1b8, &mmSPI_BARYC_CNTL[0], sizeof(mmSPI_BARYC_CNTL)/sizeof(mmSPI_BARYC_CNTL[0]), 0, 0 },
+	{ "mmSPI_TMPRING_SIZE", REG_MMIO, 0xa1ba, &mmSPI_TMPRING_SIZE[0], sizeof(mmSPI_TMPRING_SIZE)/sizeof(mmSPI_TMPRING_SIZE[0]), 0, 0 },
+	{ "mmSPI_SHADER_POS_FORMAT", REG_MMIO, 0xa1c3, &mmSPI_SHADER_POS_FORMAT[0], sizeof(mmSPI_SHADER_POS_FORMAT)/sizeof(mmSPI_SHADER_POS_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_Z_FORMAT", REG_MMIO, 0xa1c4, &mmSPI_SHADER_Z_FORMAT[0], sizeof(mmSPI_SHADER_Z_FORMAT)/sizeof(mmSPI_SHADER_Z_FORMAT[0]), 0, 0 },
+	{ "mmSPI_SHADER_COL_FORMAT", REG_MMIO, 0xa1c5, &mmSPI_SHADER_COL_FORMAT[0], sizeof(mmSPI_SHADER_COL_FORMAT)/sizeof(mmSPI_SHADER_COL_FORMAT[0]), 0, 0 },
+	{ "mmSX_PS_DOWNCONVERT", REG_MMIO, 0xa1d5, &mmSX_PS_DOWNCONVERT[0], sizeof(mmSX_PS_DOWNCONVERT)/sizeof(mmSX_PS_DOWNCONVERT[0]), 0, 0 },
+	{ "mmSX_BLEND_OPT_EPSILON", REG_MMIO, 0xa1d6, &mmSX_BLEND_OPT_EPSILON[0], sizeof(mmSX_BLEND_OPT_EPSILON)/sizeof(mmSX_BLEND_OPT_EPSILON[0]), 0, 0 },
+	{ "mmSX_BLEND_OPT_CONTROL", REG_MMIO, 0xa1d7, &mmSX_BLEND_OPT_CONTROL[0], sizeof(mmSX_BLEND_OPT_CONTROL)/sizeof(mmSX_BLEND_OPT_CONTROL[0]), 0, 0 },
+	{ "mmSX_MRT0_BLEND_OPT", REG_MMIO, 0xa1d8, &mmSX_MRT0_BLEND_OPT[0], sizeof(mmSX_MRT0_BLEND_OPT)/sizeof(mmSX_MRT0_BLEND_OPT[0]), 0, 0 },
+	{ "mmSX_MRT1_BLEND_OPT", REG_MMIO, 0xa1d9, &mmSX_MRT1_BLEND_OPT[0], sizeof(mmSX_MRT1_BLEND_OPT)/sizeof(mmSX_MRT1_BLEND_OPT[0]), 0, 0 },
+	{ "mmSX_MRT2_BLEND_OPT", REG_MMIO, 0xa1da, &mmSX_MRT2_BLEND_OPT[0], sizeof(mmSX_MRT2_BLEND_OPT)/sizeof(mmSX_MRT2_BLEND_OPT[0]), 0, 0 },
+	{ "mmSX_MRT3_BLEND_OPT", REG_MMIO, 0xa1db, &mmSX_MRT3_BLEND_OPT[0], sizeof(mmSX_MRT3_BLEND_OPT)/sizeof(mmSX_MRT3_BLEND_OPT[0]), 0, 0 },
+	{ "mmSX_MRT4_BLEND_OPT", REG_MMIO, 0xa1dc, &mmSX_MRT4_BLEND_OPT[0], sizeof(mmSX_MRT4_BLEND_OPT)/sizeof(mmSX_MRT4_BLEND_OPT[0]), 0, 0 },
+	{ "mmSX_MRT5_BLEND_OPT", REG_MMIO, 0xa1dd, &mmSX_MRT5_BLEND_OPT[0], sizeof(mmSX_MRT5_BLEND_OPT)/sizeof(mmSX_MRT5_BLEND_OPT[0]), 0, 0 },
+	{ "mmSX_MRT6_BLEND_OPT", REG_MMIO, 0xa1de, &mmSX_MRT6_BLEND_OPT[0], sizeof(mmSX_MRT6_BLEND_OPT)/sizeof(mmSX_MRT6_BLEND_OPT[0]), 0, 0 },
+	{ "mmSX_MRT7_BLEND_OPT", REG_MMIO, 0xa1df, &mmSX_MRT7_BLEND_OPT[0], sizeof(mmSX_MRT7_BLEND_OPT)/sizeof(mmSX_MRT7_BLEND_OPT[0]), 0, 0 },
+	{ "mmCB_BLEND0_CONTROL", REG_MMIO, 0xa1e0, &mmCB_BLEND0_CONTROL[0], sizeof(mmCB_BLEND0_CONTROL)/sizeof(mmCB_BLEND0_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND1_CONTROL", REG_MMIO, 0xa1e1, &mmCB_BLEND1_CONTROL[0], sizeof(mmCB_BLEND1_CONTROL)/sizeof(mmCB_BLEND1_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND2_CONTROL", REG_MMIO, 0xa1e2, &mmCB_BLEND2_CONTROL[0], sizeof(mmCB_BLEND2_CONTROL)/sizeof(mmCB_BLEND2_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND3_CONTROL", REG_MMIO, 0xa1e3, &mmCB_BLEND3_CONTROL[0], sizeof(mmCB_BLEND3_CONTROL)/sizeof(mmCB_BLEND3_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND4_CONTROL", REG_MMIO, 0xa1e4, &mmCB_BLEND4_CONTROL[0], sizeof(mmCB_BLEND4_CONTROL)/sizeof(mmCB_BLEND4_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND5_CONTROL", REG_MMIO, 0xa1e5, &mmCB_BLEND5_CONTROL[0], sizeof(mmCB_BLEND5_CONTROL)/sizeof(mmCB_BLEND5_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND6_CONTROL", REG_MMIO, 0xa1e6, &mmCB_BLEND6_CONTROL[0], sizeof(mmCB_BLEND6_CONTROL)/sizeof(mmCB_BLEND6_CONTROL[0]), 0, 0 },
+	{ "mmCB_BLEND7_CONTROL", REG_MMIO, 0xa1e7, &mmCB_BLEND7_CONTROL[0], sizeof(mmCB_BLEND7_CONTROL)/sizeof(mmCB_BLEND7_CONTROL[0]), 0, 0 },
+	{ "mmCS_COPY_STATE", REG_MMIO, 0xa1f3, &mmCS_COPY_STATE[0], sizeof(mmCS_COPY_STATE)/sizeof(mmCS_COPY_STATE[0]), 0, 0 },
+	{ "mmGFX_COPY_STATE", REG_MMIO, 0xa1f4, &mmGFX_COPY_STATE[0], sizeof(mmGFX_COPY_STATE)/sizeof(mmGFX_COPY_STATE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_X_RAD", REG_MMIO, 0xa1f5, &mmPA_CL_POINT_X_RAD[0], sizeof(mmPA_CL_POINT_X_RAD)/sizeof(mmPA_CL_POINT_X_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_Y_RAD", REG_MMIO, 0xa1f6, &mmPA_CL_POINT_Y_RAD[0], sizeof(mmPA_CL_POINT_Y_RAD)/sizeof(mmPA_CL_POINT_Y_RAD[0]), 0, 0 },
+	{ "mmPA_CL_POINT_SIZE", REG_MMIO, 0xa1f7, &mmPA_CL_POINT_SIZE[0], sizeof(mmPA_CL_POINT_SIZE)/sizeof(mmPA_CL_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_CL_POINT_CULL_RAD", REG_MMIO, 0xa1f8, &mmPA_CL_POINT_CULL_RAD[0], sizeof(mmPA_CL_POINT_CULL_RAD)/sizeof(mmPA_CL_POINT_CULL_RAD[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE_HI", REG_MMIO, 0xa1f9, &mmVGT_DMA_BASE_HI[0], sizeof(mmVGT_DMA_BASE_HI)/sizeof(mmVGT_DMA_BASE_HI[0]), 0, 0 },
+	{ "mmVGT_DMA_BASE", REG_MMIO, 0xa1fa, &mmVGT_DMA_BASE[0], sizeof(mmVGT_DMA_BASE)/sizeof(mmVGT_DMA_BASE[0]), 0, 0 },
+	{ "mmVGT_DRAW_INITIATOR", REG_MMIO, 0xa1fc, &mmVGT_DRAW_INITIATOR[0], sizeof(mmVGT_DRAW_INITIATOR)/sizeof(mmVGT_DRAW_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_IMMED_DATA", REG_MMIO, 0xa1fd, &mmVGT_IMMED_DATA[0], sizeof(mmVGT_IMMED_DATA)/sizeof(mmVGT_IMMED_DATA[0]), 0, 0 },
+	{ "mmVGT_EVENT_ADDRESS_REG", REG_MMIO, 0xa1fe, &mmVGT_EVENT_ADDRESS_REG[0], sizeof(mmVGT_EVENT_ADDRESS_REG)/sizeof(mmVGT_EVENT_ADDRESS_REG[0]), 0, 0 },
+	{ "mmDB_DEPTH_CONTROL", REG_MMIO, 0xa200, &mmDB_DEPTH_CONTROL[0], sizeof(mmDB_DEPTH_CONTROL)/sizeof(mmDB_DEPTH_CONTROL[0]), 0, 0 },
+	{ "mmDB_EQAA", REG_MMIO, 0xa201, &mmDB_EQAA[0], sizeof(mmDB_EQAA)/sizeof(mmDB_EQAA[0]), 0, 0 },
+	{ "mmCB_COLOR_CONTROL", REG_MMIO, 0xa202, &mmCB_COLOR_CONTROL[0], sizeof(mmCB_COLOR_CONTROL)/sizeof(mmCB_COLOR_CONTROL[0]), 0, 0 },
+	{ "mmDB_SHADER_CONTROL", REG_MMIO, 0xa203, &mmDB_SHADER_CONTROL[0], sizeof(mmDB_SHADER_CONTROL)/sizeof(mmDB_SHADER_CONTROL[0]), 0, 0 },
+	{ "mmPA_CL_CLIP_CNTL", REG_MMIO, 0xa204, &mmPA_CL_CLIP_CNTL[0], sizeof(mmPA_CL_CLIP_CNTL)/sizeof(mmPA_CL_CLIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_SC_MODE_CNTL", REG_MMIO, 0xa205, &mmPA_SU_SC_MODE_CNTL[0], sizeof(mmPA_SU_SC_MODE_CNTL)/sizeof(mmPA_SU_SC_MODE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VTE_CNTL", REG_MMIO, 0xa206, &mmPA_CL_VTE_CNTL[0], sizeof(mmPA_CL_VTE_CNTL)/sizeof(mmPA_CL_VTE_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_VS_OUT_CNTL", REG_MMIO, 0xa207, &mmPA_CL_VS_OUT_CNTL[0], sizeof(mmPA_CL_VS_OUT_CNTL)/sizeof(mmPA_CL_VS_OUT_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_NANINF_CNTL", REG_MMIO, 0xa208, &mmPA_CL_NANINF_CNTL[0], sizeof(mmPA_CL_NANINF_CNTL)/sizeof(mmPA_CL_NANINF_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_CNTL", REG_MMIO, 0xa209, &mmPA_SU_LINE_STIPPLE_CNTL[0], sizeof(mmPA_SU_LINE_STIPPLE_CNTL)/sizeof(mmPA_SU_LINE_STIPPLE_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_SCALE", REG_MMIO, 0xa20a, &mmPA_SU_LINE_STIPPLE_SCALE[0], sizeof(mmPA_SU_LINE_STIPPLE_SCALE)/sizeof(mmPA_SU_LINE_STIPPLE_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_PRIM_FILTER_CNTL", REG_MMIO, 0xa20b, &mmPA_SU_PRIM_FILTER_CNTL[0], sizeof(mmPA_SU_PRIM_FILTER_CNTL)/sizeof(mmPA_SU_PRIM_FILTER_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POINT_SIZE", REG_MMIO, 0xa280, &mmPA_SU_POINT_SIZE[0], sizeof(mmPA_SU_POINT_SIZE)/sizeof(mmPA_SU_POINT_SIZE[0]), 0, 0 },
+	{ "mmPA_SU_POINT_MINMAX", REG_MMIO, 0xa281, &mmPA_SU_POINT_MINMAX[0], sizeof(mmPA_SU_POINT_MINMAX)/sizeof(mmPA_SU_POINT_MINMAX[0]), 0, 0 },
+	{ "mmPA_SU_LINE_CNTL", REG_MMIO, 0xa282, &mmPA_SU_LINE_CNTL[0], sizeof(mmPA_SU_LINE_CNTL)/sizeof(mmPA_SU_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE", REG_MMIO, 0xa283, &mmPA_SC_LINE_STIPPLE[0], sizeof(mmPA_SC_LINE_STIPPLE)/sizeof(mmPA_SC_LINE_STIPPLE[0]), 0, 0 },
+	{ "mmVGT_OUTPUT_PATH_CNTL", REG_MMIO, 0xa284, &mmVGT_OUTPUT_PATH_CNTL[0], sizeof(mmVGT_OUTPUT_PATH_CNTL)/sizeof(mmVGT_OUTPUT_PATH_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_CNTL", REG_MMIO, 0xa285, &mmVGT_HOS_CNTL[0], sizeof(mmVGT_HOS_CNTL)/sizeof(mmVGT_HOS_CNTL[0]), 0, 0 },
+	{ "mmVGT_HOS_MAX_TESS_LEVEL", REG_MMIO, 0xa286, &mmVGT_HOS_MAX_TESS_LEVEL[0], sizeof(mmVGT_HOS_MAX_TESS_LEVEL)/sizeof(mmVGT_HOS_MAX_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_MIN_TESS_LEVEL", REG_MMIO, 0xa287, &mmVGT_HOS_MIN_TESS_LEVEL[0], sizeof(mmVGT_HOS_MIN_TESS_LEVEL)/sizeof(mmVGT_HOS_MIN_TESS_LEVEL[0]), 0, 0 },
+	{ "mmVGT_HOS_REUSE_DEPTH", REG_MMIO, 0xa288, &mmVGT_HOS_REUSE_DEPTH[0], sizeof(mmVGT_HOS_REUSE_DEPTH)/sizeof(mmVGT_HOS_REUSE_DEPTH[0]), 0, 0 },
+	{ "mmVGT_GROUP_PRIM_TYPE", REG_MMIO, 0xa289, &mmVGT_GROUP_PRIM_TYPE[0], sizeof(mmVGT_GROUP_PRIM_TYPE)/sizeof(mmVGT_GROUP_PRIM_TYPE[0]), 0, 0 },
+	{ "mmVGT_GROUP_FIRST_DECR", REG_MMIO, 0xa28a, &mmVGT_GROUP_FIRST_DECR[0], sizeof(mmVGT_GROUP_FIRST_DECR)/sizeof(mmVGT_GROUP_FIRST_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_DECR", REG_MMIO, 0xa28b, &mmVGT_GROUP_DECR[0], sizeof(mmVGT_GROUP_DECR)/sizeof(mmVGT_GROUP_DECR[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_CNTL", REG_MMIO, 0xa28c, &mmVGT_GROUP_VECT_0_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_CNTL)/sizeof(mmVGT_GROUP_VECT_0_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_CNTL", REG_MMIO, 0xa28d, &mmVGT_GROUP_VECT_1_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_CNTL)/sizeof(mmVGT_GROUP_VECT_1_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_0_FMT_CNTL", REG_MMIO, 0xa28e, &mmVGT_GROUP_VECT_0_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_0_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GROUP_VECT_1_FMT_CNTL", REG_MMIO, 0xa28f, &mmVGT_GROUP_VECT_1_FMT_CNTL[0], sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL)/sizeof(mmVGT_GROUP_VECT_1_FMT_CNTL[0]), 0, 0 },
+	{ "mmVGT_GS_MODE", REG_MMIO, 0xa290, &mmVGT_GS_MODE[0], sizeof(mmVGT_GS_MODE)/sizeof(mmVGT_GS_MODE[0]), 0, 0 },
+	{ "mmVGT_GS_ONCHIP_CNTL", REG_MMIO, 0xa291, &mmVGT_GS_ONCHIP_CNTL[0], sizeof(mmVGT_GS_ONCHIP_CNTL)/sizeof(mmVGT_GS_ONCHIP_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_0", REG_MMIO, 0xa292, &mmPA_SC_MODE_CNTL_0[0], sizeof(mmPA_SC_MODE_CNTL_0)/sizeof(mmPA_SC_MODE_CNTL_0[0]), 0, 0 },
+	{ "mmPA_SC_MODE_CNTL_1", REG_MMIO, 0xa293, &mmPA_SC_MODE_CNTL_1[0], sizeof(mmPA_SC_MODE_CNTL_1)/sizeof(mmPA_SC_MODE_CNTL_1[0]), 0, 0 },
+	{ "mmVGT_ENHANCE", REG_MMIO, 0xa294, &mmVGT_ENHANCE[0], sizeof(mmVGT_ENHANCE)/sizeof(mmVGT_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_GS_PER_ES", REG_MMIO, 0xa295, &mmVGT_GS_PER_ES[0], sizeof(mmVGT_GS_PER_ES)/sizeof(mmVGT_GS_PER_ES[0]), 0, 0 },
+	{ "mmVGT_ES_PER_GS", REG_MMIO, 0xa296, &mmVGT_ES_PER_GS[0], sizeof(mmVGT_ES_PER_GS)/sizeof(mmVGT_ES_PER_GS[0]), 0, 0 },
+	{ "mmVGT_GS_PER_VS", REG_MMIO, 0xa297, &mmVGT_GS_PER_VS[0], sizeof(mmVGT_GS_PER_VS)/sizeof(mmVGT_GS_PER_VS[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_1", REG_MMIO, 0xa298, &mmVGT_GSVS_RING_OFFSET_1[0], sizeof(mmVGT_GSVS_RING_OFFSET_1)/sizeof(mmVGT_GSVS_RING_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_2", REG_MMIO, 0xa299, &mmVGT_GSVS_RING_OFFSET_2[0], sizeof(mmVGT_GSVS_RING_OFFSET_2)/sizeof(mmVGT_GSVS_RING_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_OFFSET_3", REG_MMIO, 0xa29a, &mmVGT_GSVS_RING_OFFSET_3[0], sizeof(mmVGT_GSVS_RING_OFFSET_3)/sizeof(mmVGT_GSVS_RING_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_GS_OUT_PRIM_TYPE", REG_MMIO, 0xa29b, &mmVGT_GS_OUT_PRIM_TYPE[0], sizeof(mmVGT_GS_OUT_PRIM_TYPE)/sizeof(mmVGT_GS_OUT_PRIM_TYPE[0]), 0, 0 },
+	{ "mmIA_ENHANCE", REG_MMIO, 0xa29c, &mmIA_ENHANCE[0], sizeof(mmIA_ENHANCE)/sizeof(mmIA_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_DMA_SIZE", REG_MMIO, 0xa29d, &mmVGT_DMA_SIZE[0], sizeof(mmVGT_DMA_SIZE)/sizeof(mmVGT_DMA_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_MAX_SIZE", REG_MMIO, 0xa29e, &mmVGT_DMA_MAX_SIZE[0], sizeof(mmVGT_DMA_MAX_SIZE)/sizeof(mmVGT_DMA_MAX_SIZE[0]), 0, 0 },
+	{ "mmVGT_DMA_INDEX_TYPE", REG_MMIO, 0xa29f, &mmVGT_DMA_INDEX_TYPE[0], sizeof(mmVGT_DMA_INDEX_TYPE)/sizeof(mmVGT_DMA_INDEX_TYPE[0]), 0, 0 },
+	{ "mmWD_ENHANCE", REG_MMIO, 0xa2a0, &mmWD_ENHANCE[0], sizeof(mmWD_ENHANCE)/sizeof(mmWD_ENHANCE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_EN", REG_MMIO, 0xa2a1, &mmVGT_PRIMITIVEID_EN[0], sizeof(mmVGT_PRIMITIVEID_EN)/sizeof(mmVGT_PRIMITIVEID_EN[0]), 0, 0 },
+	{ "mmVGT_DMA_NUM_INSTANCES", REG_MMIO, 0xa2a2, &mmVGT_DMA_NUM_INSTANCES[0], sizeof(mmVGT_DMA_NUM_INSTANCES)/sizeof(mmVGT_DMA_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVEID_RESET", REG_MMIO, 0xa2a3, &mmVGT_PRIMITIVEID_RESET[0], sizeof(mmVGT_PRIMITIVEID_RESET)/sizeof(mmVGT_PRIMITIVEID_RESET[0]), 0, 0 },
+	{ "mmVGT_EVENT_INITIATOR", REG_MMIO, 0xa2a4, &mmVGT_EVENT_INITIATOR[0], sizeof(mmVGT_EVENT_INITIATOR)/sizeof(mmVGT_EVENT_INITIATOR[0]), 0, 0 },
+	{ "mmVGT_MULTI_PRIM_IB_RESET_EN", REG_MMIO, 0xa2a5, &mmVGT_MULTI_PRIM_IB_RESET_EN[0], sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN)/sizeof(mmVGT_MULTI_PRIM_IB_RESET_EN[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_0", REG_MMIO, 0xa2a8, &mmVGT_INSTANCE_STEP_RATE_0[0], sizeof(mmVGT_INSTANCE_STEP_RATE_0)/sizeof(mmVGT_INSTANCE_STEP_RATE_0[0]), 0, 0 },
+	{ "mmVGT_INSTANCE_STEP_RATE_1", REG_MMIO, 0xa2a9, &mmVGT_INSTANCE_STEP_RATE_1[0], sizeof(mmVGT_INSTANCE_STEP_RATE_1)/sizeof(mmVGT_INSTANCE_STEP_RATE_1[0]), 0, 0 },
+	{ "mmIA_MULTI_VGT_PARAM", REG_MMIO, 0xa2aa, &mmIA_MULTI_VGT_PARAM[0], sizeof(mmIA_MULTI_VGT_PARAM)/sizeof(mmIA_MULTI_VGT_PARAM[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_ITEMSIZE", REG_MMIO, 0xa2ab, &mmVGT_ESGS_RING_ITEMSIZE[0], sizeof(mmVGT_ESGS_RING_ITEMSIZE)/sizeof(mmVGT_ESGS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_ITEMSIZE", REG_MMIO, 0xa2ac, &mmVGT_GSVS_RING_ITEMSIZE[0], sizeof(mmVGT_GSVS_RING_ITEMSIZE)/sizeof(mmVGT_GSVS_RING_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_REUSE_OFF", REG_MMIO, 0xa2ad, &mmVGT_REUSE_OFF[0], sizeof(mmVGT_REUSE_OFF)/sizeof(mmVGT_REUSE_OFF[0]), 0, 0 },
+	{ "mmVGT_VTX_CNT_EN", REG_MMIO, 0xa2ae, &mmVGT_VTX_CNT_EN[0], sizeof(mmVGT_VTX_CNT_EN)/sizeof(mmVGT_VTX_CNT_EN[0]), 0, 0 },
+	{ "mmDB_HTILE_SURFACE", REG_MMIO, 0xa2af, &mmDB_HTILE_SURFACE[0], sizeof(mmDB_HTILE_SURFACE)/sizeof(mmDB_HTILE_SURFACE[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE0", REG_MMIO, 0xa2b0, &mmDB_SRESULTS_COMPARE_STATE0[0], sizeof(mmDB_SRESULTS_COMPARE_STATE0)/sizeof(mmDB_SRESULTS_COMPARE_STATE0[0]), 0, 0 },
+	{ "mmDB_SRESULTS_COMPARE_STATE1", REG_MMIO, 0xa2b1, &mmDB_SRESULTS_COMPARE_STATE1[0], sizeof(mmDB_SRESULTS_COMPARE_STATE1)/sizeof(mmDB_SRESULTS_COMPARE_STATE1[0]), 0, 0 },
+	{ "mmDB_PRELOAD_CONTROL", REG_MMIO, 0xa2b2, &mmDB_PRELOAD_CONTROL[0], sizeof(mmDB_PRELOAD_CONTROL)/sizeof(mmDB_PRELOAD_CONTROL[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_0", REG_MMIO, 0xa2b4, &mmVGT_STRMOUT_BUFFER_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_0", REG_MMIO, 0xa2b5, &mmVGT_STRMOUT_VTX_STRIDE_0[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_0)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_0", REG_MMIO, 0xa2b7, &mmVGT_STRMOUT_BUFFER_OFFSET_0[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_1", REG_MMIO, 0xa2b8, &mmVGT_STRMOUT_BUFFER_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_1", REG_MMIO, 0xa2b9, &mmVGT_STRMOUT_VTX_STRIDE_1[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_1)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_1", REG_MMIO, 0xa2bb, &mmVGT_STRMOUT_BUFFER_OFFSET_1[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_2", REG_MMIO, 0xa2bc, &mmVGT_STRMOUT_BUFFER_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_2", REG_MMIO, 0xa2bd, &mmVGT_STRMOUT_VTX_STRIDE_2[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_2)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_2", REG_MMIO, 0xa2bf, &mmVGT_STRMOUT_BUFFER_OFFSET_2[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_SIZE_3", REG_MMIO, 0xa2c0, &mmVGT_STRMOUT_BUFFER_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_VTX_STRIDE_3", REG_MMIO, 0xa2c1, &mmVGT_STRMOUT_VTX_STRIDE_3[0], sizeof(mmVGT_STRMOUT_VTX_STRIDE_3)/sizeof(mmVGT_STRMOUT_VTX_STRIDE_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_OFFSET_3", REG_MMIO, 0xa2c3, &mmVGT_STRMOUT_BUFFER_OFFSET_3[0], sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3)/sizeof(mmVGT_STRMOUT_BUFFER_OFFSET_3[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET", REG_MMIO, 0xa2ca, &mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE", REG_MMIO, 0xa2cb, &mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE", REG_MMIO, 0xa2cc, &mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0], sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE)/sizeof(mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE[0]), 0, 0 },
+	{ "mmVGT_GS_MAX_VERT_OUT", REG_MMIO, 0xa2ce, &mmVGT_GS_MAX_VERT_OUT[0], sizeof(mmVGT_GS_MAX_VERT_OUT)/sizeof(mmVGT_GS_MAX_VERT_OUT[0]), 0, 0 },
+	{ "mmVGT_TESS_DISTRIBUTION", REG_MMIO, 0xa2d4, &mmVGT_TESS_DISTRIBUTION[0], sizeof(mmVGT_TESS_DISTRIBUTION)/sizeof(mmVGT_TESS_DISTRIBUTION[0]), 0, 0 },
+	{ "mmVGT_SHADER_STAGES_EN", REG_MMIO, 0xa2d5, &mmVGT_SHADER_STAGES_EN[0], sizeof(mmVGT_SHADER_STAGES_EN)/sizeof(mmVGT_SHADER_STAGES_EN[0]), 0, 0 },
+	{ "mmVGT_LS_HS_CONFIG", REG_MMIO, 0xa2d6, &mmVGT_LS_HS_CONFIG[0], sizeof(mmVGT_LS_HS_CONFIG)/sizeof(mmVGT_LS_HS_CONFIG[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE", REG_MMIO, 0xa2d7, &mmVGT_GS_VERT_ITEMSIZE[0], sizeof(mmVGT_GS_VERT_ITEMSIZE)/sizeof(mmVGT_GS_VERT_ITEMSIZE[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_1", REG_MMIO, 0xa2d8, &mmVGT_GS_VERT_ITEMSIZE_1[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_1)/sizeof(mmVGT_GS_VERT_ITEMSIZE_1[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_2", REG_MMIO, 0xa2d9, &mmVGT_GS_VERT_ITEMSIZE_2[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_2)/sizeof(mmVGT_GS_VERT_ITEMSIZE_2[0]), 0, 0 },
+	{ "mmVGT_GS_VERT_ITEMSIZE_3", REG_MMIO, 0xa2da, &mmVGT_GS_VERT_ITEMSIZE_3[0], sizeof(mmVGT_GS_VERT_ITEMSIZE_3)/sizeof(mmVGT_GS_VERT_ITEMSIZE_3[0]), 0, 0 },
+	{ "mmVGT_TF_PARAM", REG_MMIO, 0xa2db, &mmVGT_TF_PARAM[0], sizeof(mmVGT_TF_PARAM)/sizeof(mmVGT_TF_PARAM[0]), 0, 0 },
+	{ "mmDB_ALPHA_TO_MASK", REG_MMIO, 0xa2dc, &mmDB_ALPHA_TO_MASK[0], sizeof(mmDB_ALPHA_TO_MASK)/sizeof(mmDB_ALPHA_TO_MASK[0]), 0, 0 },
+	{ "mmVGT_DISPATCH_DRAW_INDEX", REG_MMIO, 0xa2dd, &mmVGT_DISPATCH_DRAW_INDEX[0], sizeof(mmVGT_DISPATCH_DRAW_INDEX)/sizeof(mmVGT_DISPATCH_DRAW_INDEX[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_DB_FMT_CNTL", REG_MMIO, 0xa2de, &mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0], sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL)/sizeof(mmPA_SU_POLY_OFFSET_DB_FMT_CNTL[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_CLAMP", REG_MMIO, 0xa2df, &mmPA_SU_POLY_OFFSET_CLAMP[0], sizeof(mmPA_SU_POLY_OFFSET_CLAMP)/sizeof(mmPA_SU_POLY_OFFSET_CLAMP[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_SCALE", REG_MMIO, 0xa2e0, &mmPA_SU_POLY_OFFSET_FRONT_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_FRONT_OFFSET", REG_MMIO, 0xa2e1, &mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_FRONT_OFFSET[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_SCALE", REG_MMIO, 0xa2e2, &mmPA_SU_POLY_OFFSET_BACK_SCALE[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE)/sizeof(mmPA_SU_POLY_OFFSET_BACK_SCALE[0]), 0, 0 },
+	{ "mmPA_SU_POLY_OFFSET_BACK_OFFSET", REG_MMIO, 0xa2e3, &mmPA_SU_POLY_OFFSET_BACK_OFFSET[0], sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET)/sizeof(mmPA_SU_POLY_OFFSET_BACK_OFFSET[0]), 0, 0 },
+	{ "mmVGT_GS_INSTANCE_CNT", REG_MMIO, 0xa2e4, &mmVGT_GS_INSTANCE_CNT[0], sizeof(mmVGT_GS_INSTANCE_CNT)/sizeof(mmVGT_GS_INSTANCE_CNT[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_CONFIG", REG_MMIO, 0xa2e5, &mmVGT_STRMOUT_CONFIG[0], sizeof(mmVGT_STRMOUT_CONFIG)/sizeof(mmVGT_STRMOUT_CONFIG[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_CONFIG", REG_MMIO, 0xa2e6, &mmVGT_STRMOUT_BUFFER_CONFIG[0], sizeof(mmVGT_STRMOUT_BUFFER_CONFIG)/sizeof(mmVGT_STRMOUT_BUFFER_CONFIG[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_0", REG_MMIO, 0xa2f5, &mmPA_SC_CENTROID_PRIORITY_0[0], sizeof(mmPA_SC_CENTROID_PRIORITY_0)/sizeof(mmPA_SC_CENTROID_PRIORITY_0[0]), 0, 0 },
+	{ "mmPA_SC_CENTROID_PRIORITY_1", REG_MMIO, 0xa2f6, &mmPA_SC_CENTROID_PRIORITY_1[0], sizeof(mmPA_SC_CENTROID_PRIORITY_1)/sizeof(mmPA_SC_CENTROID_PRIORITY_1[0]), 0, 0 },
+	{ "mmPA_SC_LINE_CNTL", REG_MMIO, 0xa2f7, &mmPA_SC_LINE_CNTL[0], sizeof(mmPA_SC_LINE_CNTL)/sizeof(mmPA_SC_LINE_CNTL[0]), 0, 0 },
+	{ "mmPA_SC_AA_CONFIG", REG_MMIO, 0xa2f8, &mmPA_SC_AA_CONFIG[0], sizeof(mmPA_SC_AA_CONFIG)/sizeof(mmPA_SC_AA_CONFIG[0]), 0, 0 },
+	{ "mmPA_SU_VTX_CNTL", REG_MMIO, 0xa2f9, &mmPA_SU_VTX_CNTL[0], sizeof(mmPA_SU_VTX_CNTL)/sizeof(mmPA_SU_VTX_CNTL[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_CLIP_ADJ", REG_MMIO, 0xa2fa, &mmPA_CL_GB_VERT_CLIP_ADJ[0], sizeof(mmPA_CL_GB_VERT_CLIP_ADJ)/sizeof(mmPA_CL_GB_VERT_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_VERT_DISC_ADJ", REG_MMIO, 0xa2fb, &mmPA_CL_GB_VERT_DISC_ADJ[0], sizeof(mmPA_CL_GB_VERT_DISC_ADJ)/sizeof(mmPA_CL_GB_VERT_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_CLIP_ADJ", REG_MMIO, 0xa2fc, &mmPA_CL_GB_HORZ_CLIP_ADJ[0], sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ)/sizeof(mmPA_CL_GB_HORZ_CLIP_ADJ[0]), 0, 0 },
+	{ "mmPA_CL_GB_HORZ_DISC_ADJ", REG_MMIO, 0xa2fd, &mmPA_CL_GB_HORZ_DISC_ADJ[0], sizeof(mmPA_CL_GB_HORZ_DISC_ADJ)/sizeof(mmPA_CL_GB_HORZ_DISC_ADJ[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0", REG_MMIO, 0xa2fe, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1", REG_MMIO, 0xa2ff, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2", REG_MMIO, 0xa300, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3", REG_MMIO, 0xa301, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0", REG_MMIO, 0xa302, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1", REG_MMIO, 0xa303, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2", REG_MMIO, 0xa304, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3", REG_MMIO, 0xa305, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0", REG_MMIO, 0xa306, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1", REG_MMIO, 0xa307, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2", REG_MMIO, 0xa308, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3", REG_MMIO, 0xa309, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0", REG_MMIO, 0xa30a, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1", REG_MMIO, 0xa30b, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2", REG_MMIO, 0xa30c, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2[0]), 0, 0 },
+	{ "mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3", REG_MMIO, 0xa30d, &mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0], sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3)/sizeof(mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y0_X1Y0", REG_MMIO, 0xa30e, &mmPA_SC_AA_MASK_X0Y0_X1Y0[0], sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0)/sizeof(mmPA_SC_AA_MASK_X0Y0_X1Y0[0]), 0, 0 },
+	{ "mmPA_SC_AA_MASK_X0Y1_X1Y1", REG_MMIO, 0xa30f, &mmPA_SC_AA_MASK_X0Y1_X1Y1[0], sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1)/sizeof(mmPA_SC_AA_MASK_X0Y1_X1Y1[0]), 0, 0 },
+	{ "mmPA_SC_SHADER_CONTROL", REG_MMIO, 0xa310, &mmPA_SC_SHADER_CONTROL[0], sizeof(mmPA_SC_SHADER_CONTROL)/sizeof(mmPA_SC_SHADER_CONTROL[0]), 0, 0 },
+	{ "mmVGT_VERTEX_REUSE_BLOCK_CNTL", REG_MMIO, 0xa316, &mmVGT_VERTEX_REUSE_BLOCK_CNTL[0], sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL)/sizeof(mmVGT_VERTEX_REUSE_BLOCK_CNTL[0]), 0, 0 },
+	{ "mmVGT_OUT_DEALLOC_CNTL", REG_MMIO, 0xa317, &mmVGT_OUT_DEALLOC_CNTL[0], sizeof(mmVGT_OUT_DEALLOC_CNTL)/sizeof(mmVGT_OUT_DEALLOC_CNTL[0]), 0, 0 },
+	{ "mmCB_COLOR0_BASE", REG_MMIO, 0xa318, &mmCB_COLOR0_BASE[0], sizeof(mmCB_COLOR0_BASE)/sizeof(mmCB_COLOR0_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR0_PITCH", REG_MMIO, 0xa319, &mmCB_COLOR0_PITCH[0], sizeof(mmCB_COLOR0_PITCH)/sizeof(mmCB_COLOR0_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR0_SLICE", REG_MMIO, 0xa31a, &mmCB_COLOR0_SLICE[0], sizeof(mmCB_COLOR0_SLICE)/sizeof(mmCB_COLOR0_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_VIEW", REG_MMIO, 0xa31b, &mmCB_COLOR0_VIEW[0], sizeof(mmCB_COLOR0_VIEW)/sizeof(mmCB_COLOR0_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR0_INFO", REG_MMIO, 0xa31c, &mmCB_COLOR0_INFO[0], sizeof(mmCB_COLOR0_INFO)/sizeof(mmCB_COLOR0_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR0_ATTRIB", REG_MMIO, 0xa31d, &mmCB_COLOR0_ATTRIB[0], sizeof(mmCB_COLOR0_ATTRIB)/sizeof(mmCB_COLOR0_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR0_DCC_CONTROL", REG_MMIO, 0xa31e, &mmCB_COLOR0_DCC_CONTROL[0], sizeof(mmCB_COLOR0_DCC_CONTROL)/sizeof(mmCB_COLOR0_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK", REG_MMIO, 0xa31f, &mmCB_COLOR0_CMASK[0], sizeof(mmCB_COLOR0_CMASK)/sizeof(mmCB_COLOR0_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_CMASK_SLICE", REG_MMIO, 0xa320, &mmCB_COLOR0_CMASK_SLICE[0], sizeof(mmCB_COLOR0_CMASK_SLICE)/sizeof(mmCB_COLOR0_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK", REG_MMIO, 0xa321, &mmCB_COLOR0_FMASK[0], sizeof(mmCB_COLOR0_FMASK)/sizeof(mmCB_COLOR0_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR0_FMASK_SLICE", REG_MMIO, 0xa322, &mmCB_COLOR0_FMASK_SLICE[0], sizeof(mmCB_COLOR0_FMASK_SLICE)/sizeof(mmCB_COLOR0_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD0", REG_MMIO, 0xa323, &mmCB_COLOR0_CLEAR_WORD0[0], sizeof(mmCB_COLOR0_CLEAR_WORD0)/sizeof(mmCB_COLOR0_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR0_CLEAR_WORD1", REG_MMIO, 0xa324, &mmCB_COLOR0_CLEAR_WORD1[0], sizeof(mmCB_COLOR0_CLEAR_WORD1)/sizeof(mmCB_COLOR0_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR0_DCC_BASE", REG_MMIO, 0xa325, &mmCB_COLOR0_DCC_BASE[0], sizeof(mmCB_COLOR0_DCC_BASE)/sizeof(mmCB_COLOR0_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR1_BASE", REG_MMIO, 0xa327, &mmCB_COLOR1_BASE[0], sizeof(mmCB_COLOR1_BASE)/sizeof(mmCB_COLOR1_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR1_PITCH", REG_MMIO, 0xa328, &mmCB_COLOR1_PITCH[0], sizeof(mmCB_COLOR1_PITCH)/sizeof(mmCB_COLOR1_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR1_SLICE", REG_MMIO, 0xa329, &mmCB_COLOR1_SLICE[0], sizeof(mmCB_COLOR1_SLICE)/sizeof(mmCB_COLOR1_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_VIEW", REG_MMIO, 0xa32a, &mmCB_COLOR1_VIEW[0], sizeof(mmCB_COLOR1_VIEW)/sizeof(mmCB_COLOR1_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR1_INFO", REG_MMIO, 0xa32b, &mmCB_COLOR1_INFO[0], sizeof(mmCB_COLOR1_INFO)/sizeof(mmCB_COLOR1_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR1_ATTRIB", REG_MMIO, 0xa32c, &mmCB_COLOR1_ATTRIB[0], sizeof(mmCB_COLOR1_ATTRIB)/sizeof(mmCB_COLOR1_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR1_DCC_CONTROL", REG_MMIO, 0xa32d, &mmCB_COLOR1_DCC_CONTROL[0], sizeof(mmCB_COLOR1_DCC_CONTROL)/sizeof(mmCB_COLOR1_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK", REG_MMIO, 0xa32e, &mmCB_COLOR1_CMASK[0], sizeof(mmCB_COLOR1_CMASK)/sizeof(mmCB_COLOR1_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_CMASK_SLICE", REG_MMIO, 0xa32f, &mmCB_COLOR1_CMASK_SLICE[0], sizeof(mmCB_COLOR1_CMASK_SLICE)/sizeof(mmCB_COLOR1_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK", REG_MMIO, 0xa330, &mmCB_COLOR1_FMASK[0], sizeof(mmCB_COLOR1_FMASK)/sizeof(mmCB_COLOR1_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR1_FMASK_SLICE", REG_MMIO, 0xa331, &mmCB_COLOR1_FMASK_SLICE[0], sizeof(mmCB_COLOR1_FMASK_SLICE)/sizeof(mmCB_COLOR1_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD0", REG_MMIO, 0xa332, &mmCB_COLOR1_CLEAR_WORD0[0], sizeof(mmCB_COLOR1_CLEAR_WORD0)/sizeof(mmCB_COLOR1_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR1_CLEAR_WORD1", REG_MMIO, 0xa333, &mmCB_COLOR1_CLEAR_WORD1[0], sizeof(mmCB_COLOR1_CLEAR_WORD1)/sizeof(mmCB_COLOR1_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR1_DCC_BASE", REG_MMIO, 0xa334, &mmCB_COLOR1_DCC_BASE[0], sizeof(mmCB_COLOR1_DCC_BASE)/sizeof(mmCB_COLOR1_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR2_BASE", REG_MMIO, 0xa336, &mmCB_COLOR2_BASE[0], sizeof(mmCB_COLOR2_BASE)/sizeof(mmCB_COLOR2_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR2_PITCH", REG_MMIO, 0xa337, &mmCB_COLOR2_PITCH[0], sizeof(mmCB_COLOR2_PITCH)/sizeof(mmCB_COLOR2_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR2_SLICE", REG_MMIO, 0xa338, &mmCB_COLOR2_SLICE[0], sizeof(mmCB_COLOR2_SLICE)/sizeof(mmCB_COLOR2_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_VIEW", REG_MMIO, 0xa339, &mmCB_COLOR2_VIEW[0], sizeof(mmCB_COLOR2_VIEW)/sizeof(mmCB_COLOR2_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR2_INFO", REG_MMIO, 0xa33a, &mmCB_COLOR2_INFO[0], sizeof(mmCB_COLOR2_INFO)/sizeof(mmCB_COLOR2_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR2_ATTRIB", REG_MMIO, 0xa33b, &mmCB_COLOR2_ATTRIB[0], sizeof(mmCB_COLOR2_ATTRIB)/sizeof(mmCB_COLOR2_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR2_DCC_CONTROL", REG_MMIO, 0xa33c, &mmCB_COLOR2_DCC_CONTROL[0], sizeof(mmCB_COLOR2_DCC_CONTROL)/sizeof(mmCB_COLOR2_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK", REG_MMIO, 0xa33d, &mmCB_COLOR2_CMASK[0], sizeof(mmCB_COLOR2_CMASK)/sizeof(mmCB_COLOR2_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_CMASK_SLICE", REG_MMIO, 0xa33e, &mmCB_COLOR2_CMASK_SLICE[0], sizeof(mmCB_COLOR2_CMASK_SLICE)/sizeof(mmCB_COLOR2_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK", REG_MMIO, 0xa33f, &mmCB_COLOR2_FMASK[0], sizeof(mmCB_COLOR2_FMASK)/sizeof(mmCB_COLOR2_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR2_FMASK_SLICE", REG_MMIO, 0xa340, &mmCB_COLOR2_FMASK_SLICE[0], sizeof(mmCB_COLOR2_FMASK_SLICE)/sizeof(mmCB_COLOR2_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD0", REG_MMIO, 0xa341, &mmCB_COLOR2_CLEAR_WORD0[0], sizeof(mmCB_COLOR2_CLEAR_WORD0)/sizeof(mmCB_COLOR2_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR2_CLEAR_WORD1", REG_MMIO, 0xa342, &mmCB_COLOR2_CLEAR_WORD1[0], sizeof(mmCB_COLOR2_CLEAR_WORD1)/sizeof(mmCB_COLOR2_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR2_DCC_BASE", REG_MMIO, 0xa343, &mmCB_COLOR2_DCC_BASE[0], sizeof(mmCB_COLOR2_DCC_BASE)/sizeof(mmCB_COLOR2_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR3_BASE", REG_MMIO, 0xa345, &mmCB_COLOR3_BASE[0], sizeof(mmCB_COLOR3_BASE)/sizeof(mmCB_COLOR3_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR3_PITCH", REG_MMIO, 0xa346, &mmCB_COLOR3_PITCH[0], sizeof(mmCB_COLOR3_PITCH)/sizeof(mmCB_COLOR3_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR3_SLICE", REG_MMIO, 0xa347, &mmCB_COLOR3_SLICE[0], sizeof(mmCB_COLOR3_SLICE)/sizeof(mmCB_COLOR3_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_VIEW", REG_MMIO, 0xa348, &mmCB_COLOR3_VIEW[0], sizeof(mmCB_COLOR3_VIEW)/sizeof(mmCB_COLOR3_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR3_INFO", REG_MMIO, 0xa349, &mmCB_COLOR3_INFO[0], sizeof(mmCB_COLOR3_INFO)/sizeof(mmCB_COLOR3_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR3_ATTRIB", REG_MMIO, 0xa34a, &mmCB_COLOR3_ATTRIB[0], sizeof(mmCB_COLOR3_ATTRIB)/sizeof(mmCB_COLOR3_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR3_DCC_CONTROL", REG_MMIO, 0xa34b, &mmCB_COLOR3_DCC_CONTROL[0], sizeof(mmCB_COLOR3_DCC_CONTROL)/sizeof(mmCB_COLOR3_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK", REG_MMIO, 0xa34c, &mmCB_COLOR3_CMASK[0], sizeof(mmCB_COLOR3_CMASK)/sizeof(mmCB_COLOR3_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_CMASK_SLICE", REG_MMIO, 0xa34d, &mmCB_COLOR3_CMASK_SLICE[0], sizeof(mmCB_COLOR3_CMASK_SLICE)/sizeof(mmCB_COLOR3_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK", REG_MMIO, 0xa34e, &mmCB_COLOR3_FMASK[0], sizeof(mmCB_COLOR3_FMASK)/sizeof(mmCB_COLOR3_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR3_FMASK_SLICE", REG_MMIO, 0xa34f, &mmCB_COLOR3_FMASK_SLICE[0], sizeof(mmCB_COLOR3_FMASK_SLICE)/sizeof(mmCB_COLOR3_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD0", REG_MMIO, 0xa350, &mmCB_COLOR3_CLEAR_WORD0[0], sizeof(mmCB_COLOR3_CLEAR_WORD0)/sizeof(mmCB_COLOR3_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR3_CLEAR_WORD1", REG_MMIO, 0xa351, &mmCB_COLOR3_CLEAR_WORD1[0], sizeof(mmCB_COLOR3_CLEAR_WORD1)/sizeof(mmCB_COLOR3_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR3_DCC_BASE", REG_MMIO, 0xa352, &mmCB_COLOR3_DCC_BASE[0], sizeof(mmCB_COLOR3_DCC_BASE)/sizeof(mmCB_COLOR3_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR4_BASE", REG_MMIO, 0xa354, &mmCB_COLOR4_BASE[0], sizeof(mmCB_COLOR4_BASE)/sizeof(mmCB_COLOR4_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR4_PITCH", REG_MMIO, 0xa355, &mmCB_COLOR4_PITCH[0], sizeof(mmCB_COLOR4_PITCH)/sizeof(mmCB_COLOR4_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR4_SLICE", REG_MMIO, 0xa356, &mmCB_COLOR4_SLICE[0], sizeof(mmCB_COLOR4_SLICE)/sizeof(mmCB_COLOR4_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_VIEW", REG_MMIO, 0xa357, &mmCB_COLOR4_VIEW[0], sizeof(mmCB_COLOR4_VIEW)/sizeof(mmCB_COLOR4_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR4_INFO", REG_MMIO, 0xa358, &mmCB_COLOR4_INFO[0], sizeof(mmCB_COLOR4_INFO)/sizeof(mmCB_COLOR4_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR4_ATTRIB", REG_MMIO, 0xa359, &mmCB_COLOR4_ATTRIB[0], sizeof(mmCB_COLOR4_ATTRIB)/sizeof(mmCB_COLOR4_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR4_DCC_CONTROL", REG_MMIO, 0xa35a, &mmCB_COLOR4_DCC_CONTROL[0], sizeof(mmCB_COLOR4_DCC_CONTROL)/sizeof(mmCB_COLOR4_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK", REG_MMIO, 0xa35b, &mmCB_COLOR4_CMASK[0], sizeof(mmCB_COLOR4_CMASK)/sizeof(mmCB_COLOR4_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_CMASK_SLICE", REG_MMIO, 0xa35c, &mmCB_COLOR4_CMASK_SLICE[0], sizeof(mmCB_COLOR4_CMASK_SLICE)/sizeof(mmCB_COLOR4_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK", REG_MMIO, 0xa35d, &mmCB_COLOR4_FMASK[0], sizeof(mmCB_COLOR4_FMASK)/sizeof(mmCB_COLOR4_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR4_FMASK_SLICE", REG_MMIO, 0xa35e, &mmCB_COLOR4_FMASK_SLICE[0], sizeof(mmCB_COLOR4_FMASK_SLICE)/sizeof(mmCB_COLOR4_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD0", REG_MMIO, 0xa35f, &mmCB_COLOR4_CLEAR_WORD0[0], sizeof(mmCB_COLOR4_CLEAR_WORD0)/sizeof(mmCB_COLOR4_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR4_CLEAR_WORD1", REG_MMIO, 0xa360, &mmCB_COLOR4_CLEAR_WORD1[0], sizeof(mmCB_COLOR4_CLEAR_WORD1)/sizeof(mmCB_COLOR4_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR4_DCC_BASE", REG_MMIO, 0xa361, &mmCB_COLOR4_DCC_BASE[0], sizeof(mmCB_COLOR4_DCC_BASE)/sizeof(mmCB_COLOR4_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR5_BASE", REG_MMIO, 0xa363, &mmCB_COLOR5_BASE[0], sizeof(mmCB_COLOR5_BASE)/sizeof(mmCB_COLOR5_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR5_PITCH", REG_MMIO, 0xa364, &mmCB_COLOR5_PITCH[0], sizeof(mmCB_COLOR5_PITCH)/sizeof(mmCB_COLOR5_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR5_SLICE", REG_MMIO, 0xa365, &mmCB_COLOR5_SLICE[0], sizeof(mmCB_COLOR5_SLICE)/sizeof(mmCB_COLOR5_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_VIEW", REG_MMIO, 0xa366, &mmCB_COLOR5_VIEW[0], sizeof(mmCB_COLOR5_VIEW)/sizeof(mmCB_COLOR5_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR5_INFO", REG_MMIO, 0xa367, &mmCB_COLOR5_INFO[0], sizeof(mmCB_COLOR5_INFO)/sizeof(mmCB_COLOR5_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR5_ATTRIB", REG_MMIO, 0xa368, &mmCB_COLOR5_ATTRIB[0], sizeof(mmCB_COLOR5_ATTRIB)/sizeof(mmCB_COLOR5_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR5_DCC_CONTROL", REG_MMIO, 0xa369, &mmCB_COLOR5_DCC_CONTROL[0], sizeof(mmCB_COLOR5_DCC_CONTROL)/sizeof(mmCB_COLOR5_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK", REG_MMIO, 0xa36a, &mmCB_COLOR5_CMASK[0], sizeof(mmCB_COLOR5_CMASK)/sizeof(mmCB_COLOR5_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_CMASK_SLICE", REG_MMIO, 0xa36b, &mmCB_COLOR5_CMASK_SLICE[0], sizeof(mmCB_COLOR5_CMASK_SLICE)/sizeof(mmCB_COLOR5_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK", REG_MMIO, 0xa36c, &mmCB_COLOR5_FMASK[0], sizeof(mmCB_COLOR5_FMASK)/sizeof(mmCB_COLOR5_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR5_FMASK_SLICE", REG_MMIO, 0xa36d, &mmCB_COLOR5_FMASK_SLICE[0], sizeof(mmCB_COLOR5_FMASK_SLICE)/sizeof(mmCB_COLOR5_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD0", REG_MMIO, 0xa36e, &mmCB_COLOR5_CLEAR_WORD0[0], sizeof(mmCB_COLOR5_CLEAR_WORD0)/sizeof(mmCB_COLOR5_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR5_CLEAR_WORD1", REG_MMIO, 0xa36f, &mmCB_COLOR5_CLEAR_WORD1[0], sizeof(mmCB_COLOR5_CLEAR_WORD1)/sizeof(mmCB_COLOR5_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR5_DCC_BASE", REG_MMIO, 0xa370, &mmCB_COLOR5_DCC_BASE[0], sizeof(mmCB_COLOR5_DCC_BASE)/sizeof(mmCB_COLOR5_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR6_BASE", REG_MMIO, 0xa372, &mmCB_COLOR6_BASE[0], sizeof(mmCB_COLOR6_BASE)/sizeof(mmCB_COLOR6_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR6_PITCH", REG_MMIO, 0xa373, &mmCB_COLOR6_PITCH[0], sizeof(mmCB_COLOR6_PITCH)/sizeof(mmCB_COLOR6_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR6_SLICE", REG_MMIO, 0xa374, &mmCB_COLOR6_SLICE[0], sizeof(mmCB_COLOR6_SLICE)/sizeof(mmCB_COLOR6_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_VIEW", REG_MMIO, 0xa375, &mmCB_COLOR6_VIEW[0], sizeof(mmCB_COLOR6_VIEW)/sizeof(mmCB_COLOR6_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR6_INFO", REG_MMIO, 0xa376, &mmCB_COLOR6_INFO[0], sizeof(mmCB_COLOR6_INFO)/sizeof(mmCB_COLOR6_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR6_ATTRIB", REG_MMIO, 0xa377, &mmCB_COLOR6_ATTRIB[0], sizeof(mmCB_COLOR6_ATTRIB)/sizeof(mmCB_COLOR6_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR6_DCC_CONTROL", REG_MMIO, 0xa378, &mmCB_COLOR6_DCC_CONTROL[0], sizeof(mmCB_COLOR6_DCC_CONTROL)/sizeof(mmCB_COLOR6_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK", REG_MMIO, 0xa379, &mmCB_COLOR6_CMASK[0], sizeof(mmCB_COLOR6_CMASK)/sizeof(mmCB_COLOR6_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_CMASK_SLICE", REG_MMIO, 0xa37a, &mmCB_COLOR6_CMASK_SLICE[0], sizeof(mmCB_COLOR6_CMASK_SLICE)/sizeof(mmCB_COLOR6_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK", REG_MMIO, 0xa37b, &mmCB_COLOR6_FMASK[0], sizeof(mmCB_COLOR6_FMASK)/sizeof(mmCB_COLOR6_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR6_FMASK_SLICE", REG_MMIO, 0xa37c, &mmCB_COLOR6_FMASK_SLICE[0], sizeof(mmCB_COLOR6_FMASK_SLICE)/sizeof(mmCB_COLOR6_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD0", REG_MMIO, 0xa37d, &mmCB_COLOR6_CLEAR_WORD0[0], sizeof(mmCB_COLOR6_CLEAR_WORD0)/sizeof(mmCB_COLOR6_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR6_CLEAR_WORD1", REG_MMIO, 0xa37e, &mmCB_COLOR6_CLEAR_WORD1[0], sizeof(mmCB_COLOR6_CLEAR_WORD1)/sizeof(mmCB_COLOR6_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR6_DCC_BASE", REG_MMIO, 0xa37f, &mmCB_COLOR6_DCC_BASE[0], sizeof(mmCB_COLOR6_DCC_BASE)/sizeof(mmCB_COLOR6_DCC_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR7_BASE", REG_MMIO, 0xa381, &mmCB_COLOR7_BASE[0], sizeof(mmCB_COLOR7_BASE)/sizeof(mmCB_COLOR7_BASE[0]), 0, 0 },
+	{ "mmCB_COLOR7_PITCH", REG_MMIO, 0xa382, &mmCB_COLOR7_PITCH[0], sizeof(mmCB_COLOR7_PITCH)/sizeof(mmCB_COLOR7_PITCH[0]), 0, 0 },
+	{ "mmCB_COLOR7_SLICE", REG_MMIO, 0xa383, &mmCB_COLOR7_SLICE[0], sizeof(mmCB_COLOR7_SLICE)/sizeof(mmCB_COLOR7_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_VIEW", REG_MMIO, 0xa384, &mmCB_COLOR7_VIEW[0], sizeof(mmCB_COLOR7_VIEW)/sizeof(mmCB_COLOR7_VIEW[0]), 0, 0 },
+	{ "mmCB_COLOR7_INFO", REG_MMIO, 0xa385, &mmCB_COLOR7_INFO[0], sizeof(mmCB_COLOR7_INFO)/sizeof(mmCB_COLOR7_INFO[0]), 0, 0 },
+	{ "mmCB_COLOR7_ATTRIB", REG_MMIO, 0xa386, &mmCB_COLOR7_ATTRIB[0], sizeof(mmCB_COLOR7_ATTRIB)/sizeof(mmCB_COLOR7_ATTRIB[0]), 0, 0 },
+	{ "mmCB_COLOR7_DCC_CONTROL", REG_MMIO, 0xa387, &mmCB_COLOR7_DCC_CONTROL[0], sizeof(mmCB_COLOR7_DCC_CONTROL)/sizeof(mmCB_COLOR7_DCC_CONTROL[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK", REG_MMIO, 0xa388, &mmCB_COLOR7_CMASK[0], sizeof(mmCB_COLOR7_CMASK)/sizeof(mmCB_COLOR7_CMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_CMASK_SLICE", REG_MMIO, 0xa389, &mmCB_COLOR7_CMASK_SLICE[0], sizeof(mmCB_COLOR7_CMASK_SLICE)/sizeof(mmCB_COLOR7_CMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK", REG_MMIO, 0xa38a, &mmCB_COLOR7_FMASK[0], sizeof(mmCB_COLOR7_FMASK)/sizeof(mmCB_COLOR7_FMASK[0]), 0, 0 },
+	{ "mmCB_COLOR7_FMASK_SLICE", REG_MMIO, 0xa38b, &mmCB_COLOR7_FMASK_SLICE[0], sizeof(mmCB_COLOR7_FMASK_SLICE)/sizeof(mmCB_COLOR7_FMASK_SLICE[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD0", REG_MMIO, 0xa38c, &mmCB_COLOR7_CLEAR_WORD0[0], sizeof(mmCB_COLOR7_CLEAR_WORD0)/sizeof(mmCB_COLOR7_CLEAR_WORD0[0]), 0, 0 },
+	{ "mmCB_COLOR7_CLEAR_WORD1", REG_MMIO, 0xa38d, &mmCB_COLOR7_CLEAR_WORD1[0], sizeof(mmCB_COLOR7_CLEAR_WORD1)/sizeof(mmCB_COLOR7_CLEAR_WORD1[0]), 0, 0 },
+	{ "mmCB_COLOR7_DCC_BASE", REG_MMIO, 0xa38e, &mmCB_COLOR7_DCC_BASE[0], sizeof(mmCB_COLOR7_DCC_BASE)/sizeof(mmCB_COLOR7_DCC_BASE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG11", REG_SMC, 0xb, &ixCLIPPER_DEBUG_REG11[0], sizeof(ixCLIPPER_DEBUG_REG11)/sizeof(ixCLIPPER_DEBUG_REG11[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG11", REG_SMC, 0xb, &ixVGT_DEBUG_REG11[0], sizeof(ixVGT_DEBUG_REG11)/sizeof(ixVGT_DEBUG_REG11[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG12", REG_SMC, 0xc, &ixCLIPPER_DEBUG_REG12[0], sizeof(ixCLIPPER_DEBUG_REG12)/sizeof(ixCLIPPER_DEBUG_REG12[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG12", REG_SMC, 0xc, &ixVGT_DEBUG_REG12[0], sizeof(ixVGT_DEBUG_REG12)/sizeof(ixVGT_DEBUG_REG12[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_LO", REG_MMIO, 0xc000, &mmCP_EOP_DONE_ADDR_LO[0], sizeof(mmCP_EOP_DONE_ADDR_LO)/sizeof(mmCP_EOP_DONE_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_ADDR_HI", REG_MMIO, 0xc001, &mmCP_EOP_DONE_ADDR_HI[0], sizeof(mmCP_EOP_DONE_ADDR_HI)/sizeof(mmCP_EOP_DONE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_LO", REG_MMIO, 0xc002, &mmCP_EOP_DONE_DATA_LO[0], sizeof(mmCP_EOP_DONE_DATA_LO)/sizeof(mmCP_EOP_DONE_DATA_LO[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_HI", REG_MMIO, 0xc003, &mmCP_EOP_DONE_DATA_HI[0], sizeof(mmCP_EOP_DONE_DATA_HI)/sizeof(mmCP_EOP_DONE_DATA_HI[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_LO", REG_MMIO, 0xc004, &mmCP_EOP_LAST_FENCE_LO[0], sizeof(mmCP_EOP_LAST_FENCE_LO)/sizeof(mmCP_EOP_LAST_FENCE_LO[0]), 0, 0 },
+	{ "mmCP_EOP_LAST_FENCE_HI", REG_MMIO, 0xc005, &mmCP_EOP_LAST_FENCE_HI[0], sizeof(mmCP_EOP_LAST_FENCE_HI)/sizeof(mmCP_EOP_LAST_FENCE_HI[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_LO", REG_MMIO, 0xc006, &mmCP_STREAM_OUT_ADDR_LO[0], sizeof(mmCP_STREAM_OUT_ADDR_LO)/sizeof(mmCP_STREAM_OUT_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_ADDR_HI", REG_MMIO, 0xc007, &mmCP_STREAM_OUT_ADDR_HI[0], sizeof(mmCP_STREAM_OUT_ADDR_HI)/sizeof(mmCP_STREAM_OUT_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_LO", REG_MMIO, 0xc008, &mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT0_HI", REG_MMIO, 0xc009, &mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_LO", REG_MMIO, 0xc00a, &mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT0_HI", REG_MMIO, 0xc00b, &mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_LO", REG_MMIO, 0xc00c, &mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT1_HI", REG_MMIO, 0xc00d, &mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_LO", REG_MMIO, 0xc00e, &mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT1_HI", REG_MMIO, 0xc00f, &mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_LO", REG_MMIO, 0xc010, &mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT2_HI", REG_MMIO, 0xc011, &mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_LO", REG_MMIO, 0xc012, &mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT2_HI", REG_MMIO, 0xc013, &mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT2_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_LO", REG_MMIO, 0xc014, &mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_WRITTEN_COUNT3_HI", REG_MMIO, 0xc015, &mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_WRITTEN_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_LO", REG_MMIO, 0xc016, &mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_LO[0]), 0, 0 },
+	{ "mmCP_NUM_PRIM_NEEDED_COUNT3_HI", REG_MMIO, 0xc017, &mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0], sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI)/sizeof(mmCP_NUM_PRIM_NEEDED_COUNT3_HI[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_LO", REG_MMIO, 0xc018, &mmCP_PIPE_STATS_ADDR_LO[0], sizeof(mmCP_PIPE_STATS_ADDR_LO)/sizeof(mmCP_PIPE_STATS_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_ADDR_HI", REG_MMIO, 0xc019, &mmCP_PIPE_STATS_ADDR_HI[0], sizeof(mmCP_PIPE_STATS_ADDR_HI)/sizeof(mmCP_PIPE_STATS_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_LO", REG_MMIO, 0xc01a, &mmCP_VGT_IAVERT_COUNT_LO[0], sizeof(mmCP_VGT_IAVERT_COUNT_LO)/sizeof(mmCP_VGT_IAVERT_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAVERT_COUNT_HI", REG_MMIO, 0xc01b, &mmCP_VGT_IAVERT_COUNT_HI[0], sizeof(mmCP_VGT_IAVERT_COUNT_HI)/sizeof(mmCP_VGT_IAVERT_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_LO", REG_MMIO, 0xc01c, &mmCP_VGT_IAPRIM_COUNT_LO[0], sizeof(mmCP_VGT_IAPRIM_COUNT_LO)/sizeof(mmCP_VGT_IAPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_IAPRIM_COUNT_HI", REG_MMIO, 0xc01d, &mmCP_VGT_IAPRIM_COUNT_HI[0], sizeof(mmCP_VGT_IAPRIM_COUNT_HI)/sizeof(mmCP_VGT_IAPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_LO", REG_MMIO, 0xc01e, &mmCP_VGT_GSPRIM_COUNT_LO[0], sizeof(mmCP_VGT_GSPRIM_COUNT_LO)/sizeof(mmCP_VGT_GSPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSPRIM_COUNT_HI", REG_MMIO, 0xc01f, &mmCP_VGT_GSPRIM_COUNT_HI[0], sizeof(mmCP_VGT_GSPRIM_COUNT_HI)/sizeof(mmCP_VGT_GSPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_LO", REG_MMIO, 0xc020, &mmCP_VGT_VSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_VSINVOC_COUNT_LO)/sizeof(mmCP_VGT_VSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_VSINVOC_COUNT_HI", REG_MMIO, 0xc021, &mmCP_VGT_VSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_VSINVOC_COUNT_HI)/sizeof(mmCP_VGT_VSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_LO", REG_MMIO, 0xc022, &mmCP_VGT_GSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_GSINVOC_COUNT_LO)/sizeof(mmCP_VGT_GSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_GSINVOC_COUNT_HI", REG_MMIO, 0xc023, &mmCP_VGT_GSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_GSINVOC_COUNT_HI)/sizeof(mmCP_VGT_GSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_LO", REG_MMIO, 0xc024, &mmCP_VGT_HSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_HSINVOC_COUNT_LO)/sizeof(mmCP_VGT_HSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_HSINVOC_COUNT_HI", REG_MMIO, 0xc025, &mmCP_VGT_HSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_HSINVOC_COUNT_HI)/sizeof(mmCP_VGT_HSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_LO", REG_MMIO, 0xc026, &mmCP_VGT_DSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_DSINVOC_COUNT_LO)/sizeof(mmCP_VGT_DSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_DSINVOC_COUNT_HI", REG_MMIO, 0xc027, &mmCP_VGT_DSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_DSINVOC_COUNT_HI)/sizeof(mmCP_VGT_DSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_LO", REG_MMIO, 0xc028, &mmCP_PA_CINVOC_COUNT_LO[0], sizeof(mmCP_PA_CINVOC_COUNT_LO)/sizeof(mmCP_PA_CINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CINVOC_COUNT_HI", REG_MMIO, 0xc029, &mmCP_PA_CINVOC_COUNT_HI[0], sizeof(mmCP_PA_CINVOC_COUNT_HI)/sizeof(mmCP_PA_CINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_LO", REG_MMIO, 0xc02a, &mmCP_PA_CPRIM_COUNT_LO[0], sizeof(mmCP_PA_CPRIM_COUNT_LO)/sizeof(mmCP_PA_CPRIM_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_PA_CPRIM_COUNT_HI", REG_MMIO, 0xc02b, &mmCP_PA_CPRIM_COUNT_HI[0], sizeof(mmCP_PA_CPRIM_COUNT_HI)/sizeof(mmCP_PA_CPRIM_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_LO", REG_MMIO, 0xc02c, &mmCP_SC_PSINVOC_COUNT0_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT0_LO)/sizeof(mmCP_SC_PSINVOC_COUNT0_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT0_HI", REG_MMIO, 0xc02d, &mmCP_SC_PSINVOC_COUNT0_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT0_HI)/sizeof(mmCP_SC_PSINVOC_COUNT0_HI[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_LO", REG_MMIO, 0xc02e, &mmCP_SC_PSINVOC_COUNT1_LO[0], sizeof(mmCP_SC_PSINVOC_COUNT1_LO)/sizeof(mmCP_SC_PSINVOC_COUNT1_LO[0]), 0, 0 },
+	{ "mmCP_SC_PSINVOC_COUNT1_HI", REG_MMIO, 0xc02f, &mmCP_SC_PSINVOC_COUNT1_HI[0], sizeof(mmCP_SC_PSINVOC_COUNT1_HI)/sizeof(mmCP_SC_PSINVOC_COUNT1_HI[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_LO", REG_MMIO, 0xc030, &mmCP_VGT_CSINVOC_COUNT_LO[0], sizeof(mmCP_VGT_CSINVOC_COUNT_LO)/sizeof(mmCP_VGT_CSINVOC_COUNT_LO[0]), 0, 0 },
+	{ "mmCP_VGT_CSINVOC_COUNT_HI", REG_MMIO, 0xc031, &mmCP_VGT_CSINVOC_COUNT_HI[0], sizeof(mmCP_VGT_CSINVOC_COUNT_HI)/sizeof(mmCP_VGT_CSINVOC_COUNT_HI[0]), 0, 0 },
+	{ "mmCP_PIPE_STATS_CONTROL", REG_MMIO, 0xc03d, &mmCP_PIPE_STATS_CONTROL[0], sizeof(mmCP_PIPE_STATS_CONTROL)/sizeof(mmCP_PIPE_STATS_CONTROL[0]), 0, 0 },
+	{ "mmCP_STREAM_OUT_CONTROL", REG_MMIO, 0xc03e, &mmCP_STREAM_OUT_CONTROL[0], sizeof(mmCP_STREAM_OUT_CONTROL)/sizeof(mmCP_STREAM_OUT_CONTROL[0]), 0, 0 },
+	{ "mmCP_STRMOUT_CNTL", REG_MMIO, 0xc03f, &mmCP_STRMOUT_CNTL[0], sizeof(mmCP_STRMOUT_CNTL)/sizeof(mmCP_STRMOUT_CNTL[0]), 0, 0 },
+	{ "mmSCRATCH_REG0", REG_MMIO, 0xc040, &mmSCRATCH_REG0[0], sizeof(mmSCRATCH_REG0)/sizeof(mmSCRATCH_REG0[0]), 0, 0 },
+	{ "mmSCRATCH_REG1", REG_MMIO, 0xc041, &mmSCRATCH_REG1[0], sizeof(mmSCRATCH_REG1)/sizeof(mmSCRATCH_REG1[0]), 0, 0 },
+	{ "mmSCRATCH_REG2", REG_MMIO, 0xc042, &mmSCRATCH_REG2[0], sizeof(mmSCRATCH_REG2)/sizeof(mmSCRATCH_REG2[0]), 0, 0 },
+	{ "mmSCRATCH_REG3", REG_MMIO, 0xc043, &mmSCRATCH_REG3[0], sizeof(mmSCRATCH_REG3)/sizeof(mmSCRATCH_REG3[0]), 0, 0 },
+	{ "mmSCRATCH_REG4", REG_MMIO, 0xc044, &mmSCRATCH_REG4[0], sizeof(mmSCRATCH_REG4)/sizeof(mmSCRATCH_REG4[0]), 0, 0 },
+	{ "mmSCRATCH_REG5", REG_MMIO, 0xc045, &mmSCRATCH_REG5[0], sizeof(mmSCRATCH_REG5)/sizeof(mmSCRATCH_REG5[0]), 0, 0 },
+	{ "mmSCRATCH_REG6", REG_MMIO, 0xc046, &mmSCRATCH_REG6[0], sizeof(mmSCRATCH_REG6)/sizeof(mmSCRATCH_REG6[0]), 0, 0 },
+	{ "mmSCRATCH_REG7", REG_MMIO, 0xc047, &mmSCRATCH_REG7[0], sizeof(mmSCRATCH_REG7)/sizeof(mmSCRATCH_REG7[0]), 0, 0 },
+	{ "mmSCRATCH_UMSK", REG_MMIO, 0xc050, &mmSCRATCH_UMSK[0], sizeof(mmSCRATCH_UMSK)/sizeof(mmSCRATCH_UMSK[0]), 0, 0 },
+	{ "mmSCRATCH_ADDR", REG_MMIO, 0xc051, &mmSCRATCH_ADDR[0], sizeof(mmSCRATCH_ADDR)/sizeof(mmSCRATCH_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_ATOMIC_PREOP_LO", REG_MMIO, 0xc052, &mmCP_PFP_ATOMIC_PREOP_LO[0], sizeof(mmCP_PFP_ATOMIC_PREOP_LO)/sizeof(mmCP_PFP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_ATOMIC_PREOP_HI", REG_MMIO, 0xc053, &mmCP_PFP_ATOMIC_PREOP_HI[0], sizeof(mmCP_PFP_ATOMIC_PREOP_HI)/sizeof(mmCP_PFP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc054, &mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc055, &mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc056, &mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_PFP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc057, &mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_PFP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_LO", REG_MMIO, 0xc058, &mmCP_APPEND_ADDR_LO[0], sizeof(mmCP_APPEND_ADDR_LO)/sizeof(mmCP_APPEND_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_APPEND_ADDR_HI", REG_MMIO, 0xc059, &mmCP_APPEND_ADDR_HI[0], sizeof(mmCP_APPEND_ADDR_HI)/sizeof(mmCP_APPEND_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_APPEND_DATA", REG_MMIO, 0xc05a, &mmCP_APPEND_DATA[0], sizeof(mmCP_APPEND_DATA)/sizeof(mmCP_APPEND_DATA[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_CS_FENCE", REG_MMIO, 0xc05b, &mmCP_APPEND_LAST_CS_FENCE[0], sizeof(mmCP_APPEND_LAST_CS_FENCE)/sizeof(mmCP_APPEND_LAST_CS_FENCE[0]), 0, 0 },
+	{ "mmCP_APPEND_LAST_PS_FENCE", REG_MMIO, 0xc05c, &mmCP_APPEND_LAST_PS_FENCE[0], sizeof(mmCP_APPEND_LAST_PS_FENCE)/sizeof(mmCP_APPEND_LAST_PS_FENCE[0]), 0, 0 },
+	{ "mmCP_ME_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &mmCP_ME_ATOMIC_PREOP_LO[0], sizeof(mmCP_ME_ATOMIC_PREOP_LO)/sizeof(mmCP_ME_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_LO", REG_MMIO, 0xc05d, &mmCP_ATOMIC_PREOP_LO[0], sizeof(mmCP_ATOMIC_PREOP_LO)/sizeof(mmCP_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &mmCP_ME_ATOMIC_PREOP_HI[0], sizeof(mmCP_ME_ATOMIC_PREOP_HI)/sizeof(mmCP_ME_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ATOMIC_PREOP_HI", REG_MMIO, 0xc05e, &mmCP_ATOMIC_PREOP_HI[0], sizeof(mmCP_ATOMIC_PREOP_HI)/sizeof(mmCP_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &mmCP_ME_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_LO", REG_MMIO, 0xc05f, &mmCP_GDS_ATOMIC0_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC0_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &mmCP_ME_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC0_PREOP_HI", REG_MMIO, 0xc060, &mmCP_GDS_ATOMIC0_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC0_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC0_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &mmCP_ME_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_LO", REG_MMIO, 0xc061, &mmCP_GDS_ATOMIC1_PREOP_LO[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_LO)/sizeof(mmCP_GDS_ATOMIC1_PREOP_LO[0]), 0, 0 },
+	{ "mmCP_ME_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &mmCP_ME_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_ME_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_GDS_ATOMIC1_PREOP_HI", REG_MMIO, 0xc062, &mmCP_GDS_ATOMIC1_PREOP_HI[0], sizeof(mmCP_GDS_ATOMIC1_PREOP_HI)/sizeof(mmCP_GDS_ATOMIC1_PREOP_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_LO", REG_MMIO, 0xc069, &mmCP_ME_MC_WADDR_LO[0], sizeof(mmCP_ME_MC_WADDR_LO)/sizeof(mmCP_ME_MC_WADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WADDR_HI", REG_MMIO, 0xc06a, &mmCP_ME_MC_WADDR_HI[0], sizeof(mmCP_ME_MC_WADDR_HI)/sizeof(mmCP_ME_MC_WADDR_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_LO", REG_MMIO, 0xc06b, &mmCP_ME_MC_WDATA_LO[0], sizeof(mmCP_ME_MC_WDATA_LO)/sizeof(mmCP_ME_MC_WDATA_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_WDATA_HI", REG_MMIO, 0xc06c, &mmCP_ME_MC_WDATA_HI[0], sizeof(mmCP_ME_MC_WDATA_HI)/sizeof(mmCP_ME_MC_WDATA_HI[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_LO", REG_MMIO, 0xc06d, &mmCP_ME_MC_RADDR_LO[0], sizeof(mmCP_ME_MC_RADDR_LO)/sizeof(mmCP_ME_MC_RADDR_LO[0]), 0, 0 },
+	{ "mmCP_ME_MC_RADDR_HI", REG_MMIO, 0xc06e, &mmCP_ME_MC_RADDR_HI[0], sizeof(mmCP_ME_MC_RADDR_HI)/sizeof(mmCP_ME_MC_RADDR_HI[0]), 0, 0 },
+	{ "mmCP_SEM_WAIT_TIMER", REG_MMIO, 0xc06f, &mmCP_SEM_WAIT_TIMER[0], sizeof(mmCP_SEM_WAIT_TIMER)/sizeof(mmCP_SEM_WAIT_TIMER[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_LO", REG_MMIO, 0xc070, &mmCP_SIG_SEM_ADDR_LO[0], sizeof(mmCP_SIG_SEM_ADDR_LO)/sizeof(mmCP_SIG_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_SIG_SEM_ADDR_HI", REG_MMIO, 0xc071, &mmCP_SIG_SEM_ADDR_HI[0], sizeof(mmCP_SIG_SEM_ADDR_HI)/sizeof(mmCP_SIG_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_WAIT_REG_MEM_TIMEOUT", REG_MMIO, 0xc074, &mmCP_WAIT_REG_MEM_TIMEOUT[0], sizeof(mmCP_WAIT_REG_MEM_TIMEOUT)/sizeof(mmCP_WAIT_REG_MEM_TIMEOUT[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_LO", REG_MMIO, 0xc075, &mmCP_WAIT_SEM_ADDR_LO[0], sizeof(mmCP_WAIT_SEM_ADDR_LO)/sizeof(mmCP_WAIT_SEM_ADDR_LO[0]), 0, 0 },
+	{ "mmCP_WAIT_SEM_ADDR_HI", REG_MMIO, 0xc076, &mmCP_WAIT_SEM_ADDR_HI[0], sizeof(mmCP_WAIT_SEM_ADDR_HI)/sizeof(mmCP_WAIT_SEM_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_CONTROL", REG_MMIO, 0xc077, &mmCP_DMA_PFP_CONTROL[0], sizeof(mmCP_DMA_PFP_CONTROL)/sizeof(mmCP_DMA_PFP_CONTROL[0]), 0, 0 },
+	{ "mmCP_DMA_ME_CONTROL", REG_MMIO, 0xc078, &mmCP_DMA_ME_CONTROL[0], sizeof(mmCP_DMA_ME_CONTROL)/sizeof(mmCP_DMA_ME_CONTROL[0]), 0, 0 },
+	{ "mmCP_COHER_BASE_HI", REG_MMIO, 0xc079, &mmCP_COHER_BASE_HI[0], sizeof(mmCP_COHER_BASE_HI)/sizeof(mmCP_COHER_BASE_HI[0]), 0, 0 },
+	{ "mmCP_COHER_START_DELAY", REG_MMIO, 0xc07b, &mmCP_COHER_START_DELAY[0], sizeof(mmCP_COHER_START_DELAY)/sizeof(mmCP_COHER_START_DELAY[0]), 0, 0 },
+	{ "mmCP_COHER_CNTL", REG_MMIO, 0xc07c, &mmCP_COHER_CNTL[0], sizeof(mmCP_COHER_CNTL)/sizeof(mmCP_COHER_CNTL[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE", REG_MMIO, 0xc07d, &mmCP_COHER_SIZE[0], sizeof(mmCP_COHER_SIZE)/sizeof(mmCP_COHER_SIZE[0]), 0, 0 },
+	{ "mmCP_COHER_BASE", REG_MMIO, 0xc07e, &mmCP_COHER_BASE[0], sizeof(mmCP_COHER_BASE)/sizeof(mmCP_COHER_BASE[0]), 0, 0 },
+	{ "mmCP_COHER_STATUS", REG_MMIO, 0xc07f, &mmCP_COHER_STATUS[0], sizeof(mmCP_COHER_STATUS)/sizeof(mmCP_COHER_STATUS[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR", REG_MMIO, 0xc080, &mmCP_DMA_ME_SRC_ADDR[0], sizeof(mmCP_DMA_ME_SRC_ADDR)/sizeof(mmCP_DMA_ME_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_SRC_ADDR_HI", REG_MMIO, 0xc081, &mmCP_DMA_ME_SRC_ADDR_HI[0], sizeof(mmCP_DMA_ME_SRC_ADDR_HI)/sizeof(mmCP_DMA_ME_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR", REG_MMIO, 0xc082, &mmCP_DMA_ME_DST_ADDR[0], sizeof(mmCP_DMA_ME_DST_ADDR)/sizeof(mmCP_DMA_ME_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_ME_DST_ADDR_HI", REG_MMIO, 0xc083, &mmCP_DMA_ME_DST_ADDR_HI[0], sizeof(mmCP_DMA_ME_DST_ADDR_HI)/sizeof(mmCP_DMA_ME_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_ME_COMMAND", REG_MMIO, 0xc084, &mmCP_DMA_ME_COMMAND[0], sizeof(mmCP_DMA_ME_COMMAND)/sizeof(mmCP_DMA_ME_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR", REG_MMIO, 0xc085, &mmCP_DMA_PFP_SRC_ADDR[0], sizeof(mmCP_DMA_PFP_SRC_ADDR)/sizeof(mmCP_DMA_PFP_SRC_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_SRC_ADDR_HI", REG_MMIO, 0xc086, &mmCP_DMA_PFP_SRC_ADDR_HI[0], sizeof(mmCP_DMA_PFP_SRC_ADDR_HI)/sizeof(mmCP_DMA_PFP_SRC_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR", REG_MMIO, 0xc087, &mmCP_DMA_PFP_DST_ADDR[0], sizeof(mmCP_DMA_PFP_DST_ADDR)/sizeof(mmCP_DMA_PFP_DST_ADDR[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_DST_ADDR_HI", REG_MMIO, 0xc088, &mmCP_DMA_PFP_DST_ADDR_HI[0], sizeof(mmCP_DMA_PFP_DST_ADDR_HI)/sizeof(mmCP_DMA_PFP_DST_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DMA_PFP_COMMAND", REG_MMIO, 0xc089, &mmCP_DMA_PFP_COMMAND[0], sizeof(mmCP_DMA_PFP_COMMAND)/sizeof(mmCP_DMA_PFP_COMMAND[0]), 0, 0 },
+	{ "mmCP_DMA_CNTL", REG_MMIO, 0xc08a, &mmCP_DMA_CNTL[0], sizeof(mmCP_DMA_CNTL)/sizeof(mmCP_DMA_CNTL[0]), 0, 0 },
+	{ "mmCP_DMA_READ_TAGS", REG_MMIO, 0xc08b, &mmCP_DMA_READ_TAGS[0], sizeof(mmCP_DMA_READ_TAGS)/sizeof(mmCP_DMA_READ_TAGS[0]), 0, 0 },
+	{ "mmCP_COHER_SIZE_HI", REG_MMIO, 0xc08c, &mmCP_COHER_SIZE_HI[0], sizeof(mmCP_COHER_SIZE_HI)/sizeof(mmCP_COHER_SIZE_HI[0]), 0, 0 },
+	{ "mmCP_PFP_IB_CONTROL", REG_MMIO, 0xc08d, &mmCP_PFP_IB_CONTROL[0], sizeof(mmCP_PFP_IB_CONTROL)/sizeof(mmCP_PFP_IB_CONTROL[0]), 0, 0 },
+	{ "mmCP_PFP_LOAD_CONTROL", REG_MMIO, 0xc08e, &mmCP_PFP_LOAD_CONTROL[0], sizeof(mmCP_PFP_LOAD_CONTROL)/sizeof(mmCP_PFP_LOAD_CONTROL[0]), 0, 0 },
+	{ "mmCP_SCRATCH_INDEX", REG_MMIO, 0xc08f, &mmCP_SCRATCH_INDEX[0], sizeof(mmCP_SCRATCH_INDEX)/sizeof(mmCP_SCRATCH_INDEX[0]), 0, 0 },
+	{ "mmCP_SCRATCH_DATA", REG_MMIO, 0xc090, &mmCP_SCRATCH_DATA[0], sizeof(mmCP_SCRATCH_DATA)/sizeof(mmCP_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmCP_RB_OFFSET", REG_MMIO, 0xc091, &mmCP_RB_OFFSET[0], sizeof(mmCP_RB_OFFSET)/sizeof(mmCP_RB_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_OFFSET", REG_MMIO, 0xc092, &mmCP_IB1_OFFSET[0], sizeof(mmCP_IB1_OFFSET)/sizeof(mmCP_IB1_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB2_OFFSET", REG_MMIO, 0xc093, &mmCP_IB2_OFFSET[0], sizeof(mmCP_IB2_OFFSET)/sizeof(mmCP_IB2_OFFSET[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_BEGIN", REG_MMIO, 0xc094, &mmCP_IB1_PREAMBLE_BEGIN[0], sizeof(mmCP_IB1_PREAMBLE_BEGIN)/sizeof(mmCP_IB1_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB1_PREAMBLE_END", REG_MMIO, 0xc095, &mmCP_IB1_PREAMBLE_END[0], sizeof(mmCP_IB1_PREAMBLE_END)/sizeof(mmCP_IB1_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_BEGIN", REG_MMIO, 0xc096, &mmCP_IB2_PREAMBLE_BEGIN[0], sizeof(mmCP_IB2_PREAMBLE_BEGIN)/sizeof(mmCP_IB2_PREAMBLE_BEGIN[0]), 0, 0 },
+	{ "mmCP_IB2_PREAMBLE_END", REG_MMIO, 0xc097, &mmCP_IB2_PREAMBLE_END[0], sizeof(mmCP_IB2_PREAMBLE_END)/sizeof(mmCP_IB2_PREAMBLE_END[0]), 0, 0 },
+	{ "mmCP_CE_IB1_OFFSET", REG_MMIO, 0xc098, &mmCP_CE_IB1_OFFSET[0], sizeof(mmCP_CE_IB1_OFFSET)/sizeof(mmCP_CE_IB1_OFFSET[0]), 0, 0 },
+	{ "mmCP_CE_IB2_OFFSET", REG_MMIO, 0xc099, &mmCP_CE_IB2_OFFSET[0], sizeof(mmCP_CE_IB2_OFFSET)/sizeof(mmCP_CE_IB2_OFFSET[0]), 0, 0 },
+	{ "mmCP_CE_COUNTER", REG_MMIO, 0xc09a, &mmCP_CE_COUNTER[0], sizeof(mmCP_CE_COUNTER)/sizeof(mmCP_CE_COUNTER[0]), 0, 0 },
+	{ "mmCP_CE_RB_OFFSET", REG_MMIO, 0xc09b, &mmCP_CE_RB_OFFSET[0], sizeof(mmCP_CE_RB_OFFSET)/sizeof(mmCP_CE_RB_OFFSET[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_LO", REG_MMIO, 0xc0c3, &mmCP_CE_INIT_BASE_LO[0], sizeof(mmCP_CE_INIT_BASE_LO)/sizeof(mmCP_CE_INIT_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BASE_HI", REG_MMIO, 0xc0c4, &mmCP_CE_INIT_BASE_HI[0], sizeof(mmCP_CE_INIT_BASE_HI)/sizeof(mmCP_CE_INIT_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_INIT_BUFSZ", REG_MMIO, 0xc0c5, &mmCP_CE_INIT_BUFSZ[0], sizeof(mmCP_CE_INIT_BUFSZ)/sizeof(mmCP_CE_INIT_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_LO", REG_MMIO, 0xc0c6, &mmCP_CE_IB1_BASE_LO[0], sizeof(mmCP_CE_IB1_BASE_LO)/sizeof(mmCP_CE_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BASE_HI", REG_MMIO, 0xc0c7, &mmCP_CE_IB1_BASE_HI[0], sizeof(mmCP_CE_IB1_BASE_HI)/sizeof(mmCP_CE_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB1_BUFSZ", REG_MMIO, 0xc0c8, &mmCP_CE_IB1_BUFSZ[0], sizeof(mmCP_CE_IB1_BUFSZ)/sizeof(mmCP_CE_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_LO", REG_MMIO, 0xc0c9, &mmCP_CE_IB2_BASE_LO[0], sizeof(mmCP_CE_IB2_BASE_LO)/sizeof(mmCP_CE_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BASE_HI", REG_MMIO, 0xc0ca, &mmCP_CE_IB2_BASE_HI[0], sizeof(mmCP_CE_IB2_BASE_HI)/sizeof(mmCP_CE_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_CE_IB2_BUFSZ", REG_MMIO, 0xc0cb, &mmCP_CE_IB2_BUFSZ[0], sizeof(mmCP_CE_IB2_BUFSZ)/sizeof(mmCP_CE_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_LO", REG_MMIO, 0xc0cc, &mmCP_IB1_BASE_LO[0], sizeof(mmCP_IB1_BASE_LO)/sizeof(mmCP_IB1_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB1_BASE_HI", REG_MMIO, 0xc0cd, &mmCP_IB1_BASE_HI[0], sizeof(mmCP_IB1_BASE_HI)/sizeof(mmCP_IB1_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB1_BUFSZ", REG_MMIO, 0xc0ce, &mmCP_IB1_BUFSZ[0], sizeof(mmCP_IB1_BUFSZ)/sizeof(mmCP_IB1_BUFSZ[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_LO", REG_MMIO, 0xc0cf, &mmCP_IB2_BASE_LO[0], sizeof(mmCP_IB2_BASE_LO)/sizeof(mmCP_IB2_BASE_LO[0]), 0, 0 },
+	{ "mmCP_IB2_BASE_HI", REG_MMIO, 0xc0d0, &mmCP_IB2_BASE_HI[0], sizeof(mmCP_IB2_BASE_HI)/sizeof(mmCP_IB2_BASE_HI[0]), 0, 0 },
+	{ "mmCP_IB2_BUFSZ", REG_MMIO, 0xc0d1, &mmCP_IB2_BUFSZ[0], sizeof(mmCP_IB2_BUFSZ)/sizeof(mmCP_IB2_BUFSZ[0]), 0, 0 },
+	{ "mmCP_ST_BASE_LO", REG_MMIO, 0xc0d2, &mmCP_ST_BASE_LO[0], sizeof(mmCP_ST_BASE_LO)/sizeof(mmCP_ST_BASE_LO[0]), 0, 0 },
+	{ "mmCP_ST_BASE_HI", REG_MMIO, 0xc0d3, &mmCP_ST_BASE_HI[0], sizeof(mmCP_ST_BASE_HI)/sizeof(mmCP_ST_BASE_HI[0]), 0, 0 },
+	{ "mmCP_ST_BUFSZ", REG_MMIO, 0xc0d4, &mmCP_ST_BUFSZ[0], sizeof(mmCP_ST_BUFSZ)/sizeof(mmCP_ST_BUFSZ[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_EVENT_CNTL", REG_MMIO, 0xc0d5, &mmCP_EOP_DONE_EVENT_CNTL[0], sizeof(mmCP_EOP_DONE_EVENT_CNTL)/sizeof(mmCP_EOP_DONE_EVENT_CNTL[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_DATA_CNTL", REG_MMIO, 0xc0d6, &mmCP_EOP_DONE_DATA_CNTL[0], sizeof(mmCP_EOP_DONE_DATA_CNTL)/sizeof(mmCP_EOP_DONE_DATA_CNTL[0]), 0, 0 },
+	{ "mmCP_EOP_DONE_CNTX_ID", REG_MMIO, 0xc0d7, &mmCP_EOP_DONE_CNTX_ID[0], sizeof(mmCP_EOP_DONE_CNTX_ID)/sizeof(mmCP_EOP_DONE_CNTX_ID[0]), 0, 0 },
+	{ "mmCP_PFP_COMPLETION_STATUS", REG_MMIO, 0xc0ec, &mmCP_PFP_COMPLETION_STATUS[0], sizeof(mmCP_PFP_COMPLETION_STATUS)/sizeof(mmCP_PFP_COMPLETION_STATUS[0]), 0, 0 },
+	{ "mmCP_CE_COMPLETION_STATUS", REG_MMIO, 0xc0ed, &mmCP_CE_COMPLETION_STATUS[0], sizeof(mmCP_CE_COMPLETION_STATUS)/sizeof(mmCP_CE_COMPLETION_STATUS[0]), 0, 0 },
+	{ "mmCP_PRED_NOT_VISIBLE", REG_MMIO, 0xc0ee, &mmCP_PRED_NOT_VISIBLE[0], sizeof(mmCP_PRED_NOT_VISIBLE)/sizeof(mmCP_PRED_NOT_VISIBLE[0]), 0, 0 },
+	{ "mmCP_PFP_METADATA_BASE_ADDR", REG_MMIO, 0xc0f0, &mmCP_PFP_METADATA_BASE_ADDR[0], sizeof(mmCP_PFP_METADATA_BASE_ADDR)/sizeof(mmCP_PFP_METADATA_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_METADATA_BASE_ADDR_HI", REG_MMIO, 0xc0f1, &mmCP_PFP_METADATA_BASE_ADDR_HI[0], sizeof(mmCP_PFP_METADATA_BASE_ADDR_HI)/sizeof(mmCP_PFP_METADATA_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_CE_METADATA_BASE_ADDR", REG_MMIO, 0xc0f2, &mmCP_CE_METADATA_BASE_ADDR[0], sizeof(mmCP_CE_METADATA_BASE_ADDR)/sizeof(mmCP_CE_METADATA_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_CE_METADATA_BASE_ADDR_HI", REG_MMIO, 0xc0f3, &mmCP_CE_METADATA_BASE_ADDR_HI[0], sizeof(mmCP_CE_METADATA_BASE_ADDR_HI)/sizeof(mmCP_CE_METADATA_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DRAW_INDX_INDR_ADDR", REG_MMIO, 0xc0f4, &mmCP_DRAW_INDX_INDR_ADDR[0], sizeof(mmCP_DRAW_INDX_INDR_ADDR)/sizeof(mmCP_DRAW_INDX_INDR_ADDR[0]), 0, 0 },
+	{ "mmCP_DRAW_INDX_INDR_ADDR_HI", REG_MMIO, 0xc0f5, &mmCP_DRAW_INDX_INDR_ADDR_HI[0], sizeof(mmCP_DRAW_INDX_INDR_ADDR_HI)/sizeof(mmCP_DRAW_INDX_INDR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_DISPATCH_INDR_ADDR", REG_MMIO, 0xc0f6, &mmCP_DISPATCH_INDR_ADDR[0], sizeof(mmCP_DISPATCH_INDR_ADDR)/sizeof(mmCP_DISPATCH_INDR_ADDR[0]), 0, 0 },
+	{ "mmCP_DISPATCH_INDR_ADDR_HI", REG_MMIO, 0xc0f7, &mmCP_DISPATCH_INDR_ADDR_HI[0], sizeof(mmCP_DISPATCH_INDR_ADDR_HI)/sizeof(mmCP_DISPATCH_INDR_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_INDEX_BASE_ADDR", REG_MMIO, 0xc0f8, &mmCP_INDEX_BASE_ADDR[0], sizeof(mmCP_INDEX_BASE_ADDR)/sizeof(mmCP_INDEX_BASE_ADDR[0]), 0, 0 },
+	{ "mmCP_INDEX_BASE_ADDR_HI", REG_MMIO, 0xc0f9, &mmCP_INDEX_BASE_ADDR_HI[0], sizeof(mmCP_INDEX_BASE_ADDR_HI)/sizeof(mmCP_INDEX_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_INDEX_TYPE", REG_MMIO, 0xc0fa, &mmCP_INDEX_TYPE[0], sizeof(mmCP_INDEX_TYPE)/sizeof(mmCP_INDEX_TYPE[0]), 0, 0 },
+	{ "mmCP_GDS_BKUP_ADDR", REG_MMIO, 0xc0fb, &mmCP_GDS_BKUP_ADDR[0], sizeof(mmCP_GDS_BKUP_ADDR)/sizeof(mmCP_GDS_BKUP_ADDR[0]), 0, 0 },
+	{ "mmCP_GDS_BKUP_ADDR_HI", REG_MMIO, 0xc0fc, &mmCP_GDS_BKUP_ADDR_HI[0], sizeof(mmCP_GDS_BKUP_ADDR_HI)/sizeof(mmCP_GDS_BKUP_ADDR_HI[0]), 0, 0 },
+	{ "mmCP_SAMPLE_STATUS", REG_MMIO, 0xc0fd, &mmCP_SAMPLE_STATUS[0], sizeof(mmCP_SAMPLE_STATUS)/sizeof(mmCP_SAMPLE_STATUS[0]), 0, 0 },
+	{ "mmGRBM_GFX_INDEX", REG_MMIO, 0xc200, &mmGRBM_GFX_INDEX[0], sizeof(mmGRBM_GFX_INDEX)/sizeof(mmGRBM_GFX_INDEX[0]), 0, 0 },
+	{ "mmVGT_ESGS_RING_SIZE", REG_MMIO, 0xc240, &mmVGT_ESGS_RING_SIZE[0], sizeof(mmVGT_ESGS_RING_SIZE)/sizeof(mmVGT_ESGS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_GSVS_RING_SIZE", REG_MMIO, 0xc241, &mmVGT_GSVS_RING_SIZE[0], sizeof(mmVGT_GSVS_RING_SIZE)/sizeof(mmVGT_GSVS_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_PRIMITIVE_TYPE", REG_MMIO, 0xc242, &mmVGT_PRIMITIVE_TYPE[0], sizeof(mmVGT_PRIMITIVE_TYPE)/sizeof(mmVGT_PRIMITIVE_TYPE[0]), 0, 0 },
+	{ "mmVGT_INDEX_TYPE", REG_MMIO, 0xc243, &mmVGT_INDEX_TYPE[0], sizeof(mmVGT_INDEX_TYPE)/sizeof(mmVGT_INDEX_TYPE[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0", REG_MMIO, 0xc244, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1", REG_MMIO, 0xc245, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2", REG_MMIO, 0xc246, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2[0]), 0, 0 },
+	{ "mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3", REG_MMIO, 0xc247, &mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0], sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3)/sizeof(mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3[0]), 0, 0 },
+	{ "mmVGT_NUM_INDICES", REG_MMIO, 0xc24c, &mmVGT_NUM_INDICES[0], sizeof(mmVGT_NUM_INDICES)/sizeof(mmVGT_NUM_INDICES[0]), 0, 0 },
+	{ "mmVGT_NUM_INSTANCES", REG_MMIO, 0xc24d, &mmVGT_NUM_INSTANCES[0], sizeof(mmVGT_NUM_INSTANCES)/sizeof(mmVGT_NUM_INSTANCES[0]), 0, 0 },
+	{ "mmVGT_TF_RING_SIZE", REG_MMIO, 0xc24e, &mmVGT_TF_RING_SIZE[0], sizeof(mmVGT_TF_RING_SIZE)/sizeof(mmVGT_TF_RING_SIZE[0]), 0, 0 },
+	{ "mmVGT_HS_OFFCHIP_PARAM", REG_MMIO, 0xc24f, &mmVGT_HS_OFFCHIP_PARAM[0], sizeof(mmVGT_HS_OFFCHIP_PARAM)/sizeof(mmVGT_HS_OFFCHIP_PARAM[0]), 0, 0 },
+	{ "mmVGT_TF_MEMORY_BASE", REG_MMIO, 0xc250, &mmVGT_TF_MEMORY_BASE[0], sizeof(mmVGT_TF_MEMORY_BASE)/sizeof(mmVGT_TF_MEMORY_BASE[0]), 0, 0 },
+	{ "mmPA_SU_LINE_STIPPLE_VALUE", REG_MMIO, 0xc280, &mmPA_SU_LINE_STIPPLE_VALUE[0], sizeof(mmPA_SU_LINE_STIPPLE_VALUE)/sizeof(mmPA_SU_LINE_STIPPLE_VALUE[0]), 0, 0 },
+	{ "mmPA_SC_LINE_STIPPLE_STATE", REG_MMIO, 0xc281, &mmPA_SC_LINE_STIPPLE_STATE[0], sizeof(mmPA_SC_LINE_STIPPLE_STATE)/sizeof(mmPA_SC_LINE_STIPPLE_STATE[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MIN_0", REG_MMIO, 0xc284, &mmPA_SC_SCREEN_EXTENT_MIN_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_0[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MAX_0", REG_MMIO, 0xc285, &mmPA_SC_SCREEN_EXTENT_MAX_0[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_0[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MIN_1", REG_MMIO, 0xc286, &mmPA_SC_SCREEN_EXTENT_MIN_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MIN_1[0]), 0, 0 },
+	{ "mmPA_SC_SCREEN_EXTENT_MAX_1", REG_MMIO, 0xc28b, &mmPA_SC_SCREEN_EXTENT_MAX_1[0], sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1)/sizeof(mmPA_SC_SCREEN_EXTENT_MAX_1[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a0, &mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a1, &mmPA_SC_P3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_V", REG_MMIO, 0xc2a2, &mmPA_SC_P3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2a3, &mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_P3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2a4, &mmPA_SC_P3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_P3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2a8, &mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_H", REG_MMIO, 0xc2a9, &mmPA_SC_HP3D_TRAP_SCREEN_H[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_V", REG_MMIO, 0xc2aa, &mmPA_SC_HP3D_TRAP_SCREEN_V[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2ab, &mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_HP3D_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2ac, &mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_HP3D_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_HV_EN", REG_MMIO, 0xc2b0, &mmPA_SC_TRAP_SCREEN_HV_EN[0], sizeof(mmPA_SC_TRAP_SCREEN_HV_EN)/sizeof(mmPA_SC_TRAP_SCREEN_HV_EN[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_H", REG_MMIO, 0xc2b1, &mmPA_SC_TRAP_SCREEN_H[0], sizeof(mmPA_SC_TRAP_SCREEN_H)/sizeof(mmPA_SC_TRAP_SCREEN_H[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_V", REG_MMIO, 0xc2b2, &mmPA_SC_TRAP_SCREEN_V[0], sizeof(mmPA_SC_TRAP_SCREEN_V)/sizeof(mmPA_SC_TRAP_SCREEN_V[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_OCCURRENCE", REG_MMIO, 0xc2b3, &mmPA_SC_TRAP_SCREEN_OCCURRENCE[0], sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE)/sizeof(mmPA_SC_TRAP_SCREEN_OCCURRENCE[0]), 0, 0 },
+	{ "mmPA_SC_TRAP_SCREEN_COUNT", REG_MMIO, 0xc2b4, &mmPA_SC_TRAP_SCREEN_COUNT[0], sizeof(mmPA_SC_TRAP_SCREEN_COUNT)/sizeof(mmPA_SC_TRAP_SCREEN_COUNT[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE", REG_MMIO, 0xc330, &mmSQ_THREAD_TRACE_BASE[0], sizeof(mmSQ_THREAD_TRACE_BASE)/sizeof(mmSQ_THREAD_TRACE_BASE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_SIZE", REG_MMIO, 0xc331, &mmSQ_THREAD_TRACE_SIZE[0], sizeof(mmSQ_THREAD_TRACE_SIZE)/sizeof(mmSQ_THREAD_TRACE_SIZE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MASK", REG_MMIO, 0xc332, &mmSQ_THREAD_TRACE_MASK[0], sizeof(mmSQ_THREAD_TRACE_MASK)/sizeof(mmSQ_THREAD_TRACE_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK", REG_MMIO, 0xc333, &mmSQ_THREAD_TRACE_TOKEN_MASK[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_PERF_MASK", REG_MMIO, 0xc334, &mmSQ_THREAD_TRACE_PERF_MASK[0], sizeof(mmSQ_THREAD_TRACE_PERF_MASK)/sizeof(mmSQ_THREAD_TRACE_PERF_MASK[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_CTRL", REG_MMIO, 0xc335, &mmSQ_THREAD_TRACE_CTRL[0], sizeof(mmSQ_THREAD_TRACE_CTRL)/sizeof(mmSQ_THREAD_TRACE_CTRL[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_MODE", REG_MMIO, 0xc336, &mmSQ_THREAD_TRACE_MODE[0], sizeof(mmSQ_THREAD_TRACE_MODE)/sizeof(mmSQ_THREAD_TRACE_MODE[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_BASE2", REG_MMIO, 0xc337, &mmSQ_THREAD_TRACE_BASE2[0], sizeof(mmSQ_THREAD_TRACE_BASE2)/sizeof(mmSQ_THREAD_TRACE_BASE2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_TOKEN_MASK2", REG_MMIO, 0xc338, &mmSQ_THREAD_TRACE_TOKEN_MASK2[0], sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2)/sizeof(mmSQ_THREAD_TRACE_TOKEN_MASK2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_WPTR", REG_MMIO, 0xc339, &mmSQ_THREAD_TRACE_WPTR[0], sizeof(mmSQ_THREAD_TRACE_WPTR)/sizeof(mmSQ_THREAD_TRACE_WPTR[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_STATUS", REG_MMIO, 0xc33a, &mmSQ_THREAD_TRACE_STATUS[0], sizeof(mmSQ_THREAD_TRACE_STATUS)/sizeof(mmSQ_THREAD_TRACE_STATUS[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_HIWATER", REG_MMIO, 0xc33b, &mmSQ_THREAD_TRACE_HIWATER[0], sizeof(mmSQ_THREAD_TRACE_HIWATER)/sizeof(mmSQ_THREAD_TRACE_HIWATER[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_0", REG_MMIO, 0xc340, &mmSQ_THREAD_TRACE_USERDATA_0[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_0)/sizeof(mmSQ_THREAD_TRACE_USERDATA_0[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_1", REG_MMIO, 0xc341, &mmSQ_THREAD_TRACE_USERDATA_1[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_1)/sizeof(mmSQ_THREAD_TRACE_USERDATA_1[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_2", REG_MMIO, 0xc342, &mmSQ_THREAD_TRACE_USERDATA_2[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_2)/sizeof(mmSQ_THREAD_TRACE_USERDATA_2[0]), 0, 0 },
+	{ "mmSQ_THREAD_TRACE_USERDATA_3", REG_MMIO, 0xc343, &mmSQ_THREAD_TRACE_USERDATA_3[0], sizeof(mmSQ_THREAD_TRACE_USERDATA_3)/sizeof(mmSQ_THREAD_TRACE_USERDATA_3[0]), 0, 0 },
+	{ "mmSQC_CACHES", REG_MMIO, 0xc348, &mmSQC_CACHES[0], sizeof(mmSQC_CACHES)/sizeof(mmSQC_CACHES[0]), 0, 0 },
+	{ "mmSQC_WRITEBACK", REG_MMIO, 0xc349, &mmSQC_WRITEBACK[0], sizeof(mmSQC_WRITEBACK)/sizeof(mmSQC_WRITEBACK[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR", REG_MMIO, 0xc380, &mmTA_CS_BC_BASE_ADDR[0], sizeof(mmTA_CS_BC_BASE_ADDR)/sizeof(mmTA_CS_BC_BASE_ADDR[0]), 0, 0 },
+	{ "mmTA_CS_BC_BASE_ADDR_HI", REG_MMIO, 0xc381, &mmTA_CS_BC_BASE_ADDR_HI[0], sizeof(mmTA_CS_BC_BASE_ADDR_HI)/sizeof(mmTA_CS_BC_BASE_ADDR_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT0_LOW", REG_MMIO, 0xc3c0, &mmDB_OCCLUSION_COUNT0_LOW[0], sizeof(mmDB_OCCLUSION_COUNT0_LOW)/sizeof(mmDB_OCCLUSION_COUNT0_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT0_HI", REG_MMIO, 0xc3c1, &mmDB_OCCLUSION_COUNT0_HI[0], sizeof(mmDB_OCCLUSION_COUNT0_HI)/sizeof(mmDB_OCCLUSION_COUNT0_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT1_LOW", REG_MMIO, 0xc3c2, &mmDB_OCCLUSION_COUNT1_LOW[0], sizeof(mmDB_OCCLUSION_COUNT1_LOW)/sizeof(mmDB_OCCLUSION_COUNT1_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT1_HI", REG_MMIO, 0xc3c3, &mmDB_OCCLUSION_COUNT1_HI[0], sizeof(mmDB_OCCLUSION_COUNT1_HI)/sizeof(mmDB_OCCLUSION_COUNT1_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT2_LOW", REG_MMIO, 0xc3c4, &mmDB_OCCLUSION_COUNT2_LOW[0], sizeof(mmDB_OCCLUSION_COUNT2_LOW)/sizeof(mmDB_OCCLUSION_COUNT2_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT2_HI", REG_MMIO, 0xc3c5, &mmDB_OCCLUSION_COUNT2_HI[0], sizeof(mmDB_OCCLUSION_COUNT2_HI)/sizeof(mmDB_OCCLUSION_COUNT2_HI[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT3_LOW", REG_MMIO, 0xc3c6, &mmDB_OCCLUSION_COUNT3_LOW[0], sizeof(mmDB_OCCLUSION_COUNT3_LOW)/sizeof(mmDB_OCCLUSION_COUNT3_LOW[0]), 0, 0 },
+	{ "mmDB_OCCLUSION_COUNT3_HI", REG_MMIO, 0xc3c7, &mmDB_OCCLUSION_COUNT3_HI[0], sizeof(mmDB_OCCLUSION_COUNT3_HI)/sizeof(mmDB_OCCLUSION_COUNT3_HI[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_LOW", REG_MMIO, 0xc3fe, &mmDB_ZPASS_COUNT_LOW[0], sizeof(mmDB_ZPASS_COUNT_LOW)/sizeof(mmDB_ZPASS_COUNT_LOW[0]), 0, 0 },
+	{ "mmDB_ZPASS_COUNT_HI", REG_MMIO, 0xc3ff, &mmDB_ZPASS_COUNT_HI[0], sizeof(mmDB_ZPASS_COUNT_HI)/sizeof(mmDB_ZPASS_COUNT_HI[0]), 0, 0 },
+	{ "mmGDS_RD_ADDR", REG_MMIO, 0xc400, &mmGDS_RD_ADDR[0], sizeof(mmGDS_RD_ADDR)/sizeof(mmGDS_RD_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_DATA", REG_MMIO, 0xc401, &mmGDS_RD_DATA[0], sizeof(mmGDS_RD_DATA)/sizeof(mmGDS_RD_DATA[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_ADDR", REG_MMIO, 0xc402, &mmGDS_RD_BURST_ADDR[0], sizeof(mmGDS_RD_BURST_ADDR)/sizeof(mmGDS_RD_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_COUNT", REG_MMIO, 0xc403, &mmGDS_RD_BURST_COUNT[0], sizeof(mmGDS_RD_BURST_COUNT)/sizeof(mmGDS_RD_BURST_COUNT[0]), 0, 0 },
+	{ "mmGDS_RD_BURST_DATA", REG_MMIO, 0xc404, &mmGDS_RD_BURST_DATA[0], sizeof(mmGDS_RD_BURST_DATA)/sizeof(mmGDS_RD_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_ADDR", REG_MMIO, 0xc405, &mmGDS_WR_ADDR[0], sizeof(mmGDS_WR_ADDR)/sizeof(mmGDS_WR_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_DATA", REG_MMIO, 0xc406, &mmGDS_WR_DATA[0], sizeof(mmGDS_WR_DATA)/sizeof(mmGDS_WR_DATA[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_ADDR", REG_MMIO, 0xc407, &mmGDS_WR_BURST_ADDR[0], sizeof(mmGDS_WR_BURST_ADDR)/sizeof(mmGDS_WR_BURST_ADDR[0]), 0, 0 },
+	{ "mmGDS_WR_BURST_DATA", REG_MMIO, 0xc408, &mmGDS_WR_BURST_DATA[0], sizeof(mmGDS_WR_BURST_DATA)/sizeof(mmGDS_WR_BURST_DATA[0]), 0, 0 },
+	{ "mmGDS_WRITE_COMPLETE", REG_MMIO, 0xc409, &mmGDS_WRITE_COMPLETE[0], sizeof(mmGDS_WRITE_COMPLETE)/sizeof(mmGDS_WRITE_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_CNTL", REG_MMIO, 0xc40a, &mmGDS_ATOM_CNTL[0], sizeof(mmGDS_ATOM_CNTL)/sizeof(mmGDS_ATOM_CNTL[0]), 0, 0 },
+	{ "mmGDS_ATOM_COMPLETE", REG_MMIO, 0xc40b, &mmGDS_ATOM_COMPLETE[0], sizeof(mmGDS_ATOM_COMPLETE)/sizeof(mmGDS_ATOM_COMPLETE[0]), 0, 0 },
+	{ "mmGDS_ATOM_BASE", REG_MMIO, 0xc40c, &mmGDS_ATOM_BASE[0], sizeof(mmGDS_ATOM_BASE)/sizeof(mmGDS_ATOM_BASE[0]), 0, 0 },
+	{ "mmGDS_ATOM_SIZE", REG_MMIO, 0xc40d, &mmGDS_ATOM_SIZE[0], sizeof(mmGDS_ATOM_SIZE)/sizeof(mmGDS_ATOM_SIZE[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET0", REG_MMIO, 0xc40e, &mmGDS_ATOM_OFFSET0[0], sizeof(mmGDS_ATOM_OFFSET0)/sizeof(mmGDS_ATOM_OFFSET0[0]), 0, 0 },
+	{ "mmGDS_ATOM_OFFSET1", REG_MMIO, 0xc40f, &mmGDS_ATOM_OFFSET1[0], sizeof(mmGDS_ATOM_OFFSET1)/sizeof(mmGDS_ATOM_OFFSET1[0]), 0, 0 },
+	{ "mmGDS_ATOM_DST", REG_MMIO, 0xc410, &mmGDS_ATOM_DST[0], sizeof(mmGDS_ATOM_DST)/sizeof(mmGDS_ATOM_DST[0]), 0, 0 },
+	{ "mmGDS_ATOM_OP", REG_MMIO, 0xc411, &mmGDS_ATOM_OP[0], sizeof(mmGDS_ATOM_OP)/sizeof(mmGDS_ATOM_OP[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0", REG_MMIO, 0xc412, &mmGDS_ATOM_SRC0[0], sizeof(mmGDS_ATOM_SRC0)/sizeof(mmGDS_ATOM_SRC0[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC0_U", REG_MMIO, 0xc413, &mmGDS_ATOM_SRC0_U[0], sizeof(mmGDS_ATOM_SRC0_U)/sizeof(mmGDS_ATOM_SRC0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1", REG_MMIO, 0xc414, &mmGDS_ATOM_SRC1[0], sizeof(mmGDS_ATOM_SRC1)/sizeof(mmGDS_ATOM_SRC1[0]), 0, 0 },
+	{ "mmGDS_ATOM_SRC1_U", REG_MMIO, 0xc415, &mmGDS_ATOM_SRC1_U[0], sizeof(mmGDS_ATOM_SRC1_U)/sizeof(mmGDS_ATOM_SRC1_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0", REG_MMIO, 0xc416, &mmGDS_ATOM_READ0[0], sizeof(mmGDS_ATOM_READ0)/sizeof(mmGDS_ATOM_READ0[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ0_U", REG_MMIO, 0xc417, &mmGDS_ATOM_READ0_U[0], sizeof(mmGDS_ATOM_READ0_U)/sizeof(mmGDS_ATOM_READ0_U[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1", REG_MMIO, 0xc418, &mmGDS_ATOM_READ1[0], sizeof(mmGDS_ATOM_READ1)/sizeof(mmGDS_ATOM_READ1[0]), 0, 0 },
+	{ "mmGDS_ATOM_READ1_U", REG_MMIO, 0xc419, &mmGDS_ATOM_READ1_U[0], sizeof(mmGDS_ATOM_READ1_U)/sizeof(mmGDS_ATOM_READ1_U[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNTL", REG_MMIO, 0xc41a, &mmGDS_GWS_RESOURCE_CNTL[0], sizeof(mmGDS_GWS_RESOURCE_CNTL)/sizeof(mmGDS_GWS_RESOURCE_CNTL[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE", REG_MMIO, 0xc41b, &mmGDS_GWS_RESOURCE[0], sizeof(mmGDS_GWS_RESOURCE)/sizeof(mmGDS_GWS_RESOURCE[0]), 0, 0 },
+	{ "mmGDS_GWS_RESOURCE_CNT", REG_MMIO, 0xc41c, &mmGDS_GWS_RESOURCE_CNT[0], sizeof(mmGDS_GWS_RESOURCE_CNT)/sizeof(mmGDS_GWS_RESOURCE_CNT[0]), 0, 0 },
+	{ "mmGDS_OA_CNTL", REG_MMIO, 0xc41d, &mmGDS_OA_CNTL[0], sizeof(mmGDS_OA_CNTL)/sizeof(mmGDS_OA_CNTL[0]), 0, 0 },
+	{ "mmGDS_OA_COUNTER", REG_MMIO, 0xc41e, &mmGDS_OA_COUNTER[0], sizeof(mmGDS_OA_COUNTER)/sizeof(mmGDS_OA_COUNTER[0]), 0, 0 },
+	{ "mmGDS_OA_ADDRESS", REG_MMIO, 0xc41f, &mmGDS_OA_ADDRESS[0], sizeof(mmGDS_OA_ADDRESS)/sizeof(mmGDS_OA_ADDRESS[0]), 0, 0 },
+	{ "mmGDS_OA_INCDEC", REG_MMIO, 0xc420, &mmGDS_OA_INCDEC[0], sizeof(mmGDS_OA_INCDEC)/sizeof(mmGDS_OA_INCDEC[0]), 0, 0 },
+	{ "mmGDS_OA_RING_SIZE", REG_MMIO, 0xc421, &mmGDS_OA_RING_SIZE[0], sizeof(mmGDS_OA_RING_SIZE)/sizeof(mmGDS_OA_RING_SIZE[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG13", REG_SMC, 0xd, &ixCLIPPER_DEBUG_REG13[0], sizeof(ixCLIPPER_DEBUG_REG13)/sizeof(ixCLIPPER_DEBUG_REG13[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG13", REG_SMC, 0xd, &ixVGT_DEBUG_REG13[0], sizeof(ixVGT_DEBUG_REG13)/sizeof(ixVGT_DEBUG_REG13[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_LO", REG_MMIO, 0xd000, &mmCPG_PERFCOUNTER1_LO[0], sizeof(mmCPG_PERFCOUNTER1_LO)/sizeof(mmCPG_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_HI", REG_MMIO, 0xd001, &mmCPG_PERFCOUNTER1_HI[0], sizeof(mmCPG_PERFCOUNTER1_HI)/sizeof(mmCPG_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_LO", REG_MMIO, 0xd002, &mmCPG_PERFCOUNTER0_LO[0], sizeof(mmCPG_PERFCOUNTER0_LO)/sizeof(mmCPG_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_HI", REG_MMIO, 0xd003, &mmCPG_PERFCOUNTER0_HI[0], sizeof(mmCPG_PERFCOUNTER0_HI)/sizeof(mmCPG_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_LO", REG_MMIO, 0xd004, &mmCPC_PERFCOUNTER1_LO[0], sizeof(mmCPC_PERFCOUNTER1_LO)/sizeof(mmCPC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_HI", REG_MMIO, 0xd005, &mmCPC_PERFCOUNTER1_HI[0], sizeof(mmCPC_PERFCOUNTER1_HI)/sizeof(mmCPC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_LO", REG_MMIO, 0xd006, &mmCPC_PERFCOUNTER0_LO[0], sizeof(mmCPC_PERFCOUNTER0_LO)/sizeof(mmCPC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_HI", REG_MMIO, 0xd007, &mmCPC_PERFCOUNTER0_HI[0], sizeof(mmCPC_PERFCOUNTER0_HI)/sizeof(mmCPC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_LO", REG_MMIO, 0xd008, &mmCPF_PERFCOUNTER1_LO[0], sizeof(mmCPF_PERFCOUNTER1_LO)/sizeof(mmCPF_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_HI", REG_MMIO, 0xd009, &mmCPF_PERFCOUNTER1_HI[0], sizeof(mmCPF_PERFCOUNTER1_HI)/sizeof(mmCPF_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_LO", REG_MMIO, 0xd00a, &mmCPF_PERFCOUNTER0_LO[0], sizeof(mmCPF_PERFCOUNTER0_LO)/sizeof(mmCPF_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_HI", REG_MMIO, 0xd00b, &mmCPF_PERFCOUNTER0_HI[0], sizeof(mmCPF_PERFCOUNTER0_HI)/sizeof(mmCPF_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_LO", REG_MMIO, 0xd040, &mmGRBM_PERFCOUNTER0_LO[0], sizeof(mmGRBM_PERFCOUNTER0_LO)/sizeof(mmGRBM_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_HI", REG_MMIO, 0xd041, &mmGRBM_PERFCOUNTER0_HI[0], sizeof(mmGRBM_PERFCOUNTER0_HI)/sizeof(mmGRBM_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_LO", REG_MMIO, 0xd043, &mmGRBM_PERFCOUNTER1_LO[0], sizeof(mmGRBM_PERFCOUNTER1_LO)/sizeof(mmGRBM_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_HI", REG_MMIO, 0xd044, &mmGRBM_PERFCOUNTER1_HI[0], sizeof(mmGRBM_PERFCOUNTER1_HI)/sizeof(mmGRBM_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_LO", REG_MMIO, 0xd045, &mmGRBM_SE0_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE0_PERFCOUNTER_LO)/sizeof(mmGRBM_SE0_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_HI", REG_MMIO, 0xd046, &mmGRBM_SE0_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE0_PERFCOUNTER_HI)/sizeof(mmGRBM_SE0_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_LO", REG_MMIO, 0xd047, &mmGRBM_SE1_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE1_PERFCOUNTER_LO)/sizeof(mmGRBM_SE1_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_HI", REG_MMIO, 0xd048, &mmGRBM_SE1_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE1_PERFCOUNTER_HI)/sizeof(mmGRBM_SE1_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_LO", REG_MMIO, 0xd049, &mmGRBM_SE2_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE2_PERFCOUNTER_LO)/sizeof(mmGRBM_SE2_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_HI", REG_MMIO, 0xd04a, &mmGRBM_SE2_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE2_PERFCOUNTER_HI)/sizeof(mmGRBM_SE2_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_LO", REG_MMIO, 0xd04b, &mmGRBM_SE3_PERFCOUNTER_LO[0], sizeof(mmGRBM_SE3_PERFCOUNTER_LO)/sizeof(mmGRBM_SE3_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_HI", REG_MMIO, 0xd04c, &mmGRBM_SE3_PERFCOUNTER_HI[0], sizeof(mmGRBM_SE3_PERFCOUNTER_HI)/sizeof(mmGRBM_SE3_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_LO", REG_MMIO, 0xd080, &mmWD_PERFCOUNTER0_LO[0], sizeof(mmWD_PERFCOUNTER0_LO)/sizeof(mmWD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_HI", REG_MMIO, 0xd081, &mmWD_PERFCOUNTER0_HI[0], sizeof(mmWD_PERFCOUNTER0_HI)/sizeof(mmWD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_LO", REG_MMIO, 0xd082, &mmWD_PERFCOUNTER1_LO[0], sizeof(mmWD_PERFCOUNTER1_LO)/sizeof(mmWD_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_HI", REG_MMIO, 0xd083, &mmWD_PERFCOUNTER1_HI[0], sizeof(mmWD_PERFCOUNTER1_HI)/sizeof(mmWD_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_LO", REG_MMIO, 0xd084, &mmWD_PERFCOUNTER2_LO[0], sizeof(mmWD_PERFCOUNTER2_LO)/sizeof(mmWD_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_HI", REG_MMIO, 0xd085, &mmWD_PERFCOUNTER2_HI[0], sizeof(mmWD_PERFCOUNTER2_HI)/sizeof(mmWD_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_LO", REG_MMIO, 0xd086, &mmWD_PERFCOUNTER3_LO[0], sizeof(mmWD_PERFCOUNTER3_LO)/sizeof(mmWD_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_HI", REG_MMIO, 0xd087, &mmWD_PERFCOUNTER3_HI[0], sizeof(mmWD_PERFCOUNTER3_HI)/sizeof(mmWD_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_LO", REG_MMIO, 0xd088, &mmIA_PERFCOUNTER0_LO[0], sizeof(mmIA_PERFCOUNTER0_LO)/sizeof(mmIA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_HI", REG_MMIO, 0xd089, &mmIA_PERFCOUNTER0_HI[0], sizeof(mmIA_PERFCOUNTER0_HI)/sizeof(mmIA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_LO", REG_MMIO, 0xd08a, &mmIA_PERFCOUNTER1_LO[0], sizeof(mmIA_PERFCOUNTER1_LO)/sizeof(mmIA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_HI", REG_MMIO, 0xd08b, &mmIA_PERFCOUNTER1_HI[0], sizeof(mmIA_PERFCOUNTER1_HI)/sizeof(mmIA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_LO", REG_MMIO, 0xd08c, &mmIA_PERFCOUNTER2_LO[0], sizeof(mmIA_PERFCOUNTER2_LO)/sizeof(mmIA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_HI", REG_MMIO, 0xd08d, &mmIA_PERFCOUNTER2_HI[0], sizeof(mmIA_PERFCOUNTER2_HI)/sizeof(mmIA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_LO", REG_MMIO, 0xd08e, &mmIA_PERFCOUNTER3_LO[0], sizeof(mmIA_PERFCOUNTER3_LO)/sizeof(mmIA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_HI", REG_MMIO, 0xd08f, &mmIA_PERFCOUNTER3_HI[0], sizeof(mmIA_PERFCOUNTER3_HI)/sizeof(mmIA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_LO", REG_MMIO, 0xd090, &mmVGT_PERFCOUNTER0_LO[0], sizeof(mmVGT_PERFCOUNTER0_LO)/sizeof(mmVGT_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_HI", REG_MMIO, 0xd091, &mmVGT_PERFCOUNTER0_HI[0], sizeof(mmVGT_PERFCOUNTER0_HI)/sizeof(mmVGT_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_LO", REG_MMIO, 0xd092, &mmVGT_PERFCOUNTER1_LO[0], sizeof(mmVGT_PERFCOUNTER1_LO)/sizeof(mmVGT_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_HI", REG_MMIO, 0xd093, &mmVGT_PERFCOUNTER1_HI[0], sizeof(mmVGT_PERFCOUNTER1_HI)/sizeof(mmVGT_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_LO", REG_MMIO, 0xd094, &mmVGT_PERFCOUNTER2_LO[0], sizeof(mmVGT_PERFCOUNTER2_LO)/sizeof(mmVGT_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_HI", REG_MMIO, 0xd095, &mmVGT_PERFCOUNTER2_HI[0], sizeof(mmVGT_PERFCOUNTER2_HI)/sizeof(mmVGT_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_LO", REG_MMIO, 0xd096, &mmVGT_PERFCOUNTER3_LO[0], sizeof(mmVGT_PERFCOUNTER3_LO)/sizeof(mmVGT_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_HI", REG_MMIO, 0xd097, &mmVGT_PERFCOUNTER3_HI[0], sizeof(mmVGT_PERFCOUNTER3_HI)/sizeof(mmVGT_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_LO", REG_MMIO, 0xd100, &mmPA_SU_PERFCOUNTER0_LO[0], sizeof(mmPA_SU_PERFCOUNTER0_LO)/sizeof(mmPA_SU_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_HI", REG_MMIO, 0xd101, &mmPA_SU_PERFCOUNTER0_HI[0], sizeof(mmPA_SU_PERFCOUNTER0_HI)/sizeof(mmPA_SU_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_LO", REG_MMIO, 0xd102, &mmPA_SU_PERFCOUNTER1_LO[0], sizeof(mmPA_SU_PERFCOUNTER1_LO)/sizeof(mmPA_SU_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_HI", REG_MMIO, 0xd103, &mmPA_SU_PERFCOUNTER1_HI[0], sizeof(mmPA_SU_PERFCOUNTER1_HI)/sizeof(mmPA_SU_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_LO", REG_MMIO, 0xd104, &mmPA_SU_PERFCOUNTER2_LO[0], sizeof(mmPA_SU_PERFCOUNTER2_LO)/sizeof(mmPA_SU_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_HI", REG_MMIO, 0xd105, &mmPA_SU_PERFCOUNTER2_HI[0], sizeof(mmPA_SU_PERFCOUNTER2_HI)/sizeof(mmPA_SU_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_LO", REG_MMIO, 0xd106, &mmPA_SU_PERFCOUNTER3_LO[0], sizeof(mmPA_SU_PERFCOUNTER3_LO)/sizeof(mmPA_SU_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_HI", REG_MMIO, 0xd107, &mmPA_SU_PERFCOUNTER3_HI[0], sizeof(mmPA_SU_PERFCOUNTER3_HI)/sizeof(mmPA_SU_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_LO", REG_MMIO, 0xd140, &mmPA_SC_PERFCOUNTER0_LO[0], sizeof(mmPA_SC_PERFCOUNTER0_LO)/sizeof(mmPA_SC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_HI", REG_MMIO, 0xd141, &mmPA_SC_PERFCOUNTER0_HI[0], sizeof(mmPA_SC_PERFCOUNTER0_HI)/sizeof(mmPA_SC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_LO", REG_MMIO, 0xd142, &mmPA_SC_PERFCOUNTER1_LO[0], sizeof(mmPA_SC_PERFCOUNTER1_LO)/sizeof(mmPA_SC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_HI", REG_MMIO, 0xd143, &mmPA_SC_PERFCOUNTER1_HI[0], sizeof(mmPA_SC_PERFCOUNTER1_HI)/sizeof(mmPA_SC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_LO", REG_MMIO, 0xd144, &mmPA_SC_PERFCOUNTER2_LO[0], sizeof(mmPA_SC_PERFCOUNTER2_LO)/sizeof(mmPA_SC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_HI", REG_MMIO, 0xd145, &mmPA_SC_PERFCOUNTER2_HI[0], sizeof(mmPA_SC_PERFCOUNTER2_HI)/sizeof(mmPA_SC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_LO", REG_MMIO, 0xd146, &mmPA_SC_PERFCOUNTER3_LO[0], sizeof(mmPA_SC_PERFCOUNTER3_LO)/sizeof(mmPA_SC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_HI", REG_MMIO, 0xd147, &mmPA_SC_PERFCOUNTER3_HI[0], sizeof(mmPA_SC_PERFCOUNTER3_HI)/sizeof(mmPA_SC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_LO", REG_MMIO, 0xd148, &mmPA_SC_PERFCOUNTER4_LO[0], sizeof(mmPA_SC_PERFCOUNTER4_LO)/sizeof(mmPA_SC_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_HI", REG_MMIO, 0xd149, &mmPA_SC_PERFCOUNTER4_HI[0], sizeof(mmPA_SC_PERFCOUNTER4_HI)/sizeof(mmPA_SC_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_LO", REG_MMIO, 0xd14a, &mmPA_SC_PERFCOUNTER5_LO[0], sizeof(mmPA_SC_PERFCOUNTER5_LO)/sizeof(mmPA_SC_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_HI", REG_MMIO, 0xd14b, &mmPA_SC_PERFCOUNTER5_HI[0], sizeof(mmPA_SC_PERFCOUNTER5_HI)/sizeof(mmPA_SC_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_LO", REG_MMIO, 0xd14c, &mmPA_SC_PERFCOUNTER6_LO[0], sizeof(mmPA_SC_PERFCOUNTER6_LO)/sizeof(mmPA_SC_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_HI", REG_MMIO, 0xd14d, &mmPA_SC_PERFCOUNTER6_HI[0], sizeof(mmPA_SC_PERFCOUNTER6_HI)/sizeof(mmPA_SC_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_LO", REG_MMIO, 0xd14e, &mmPA_SC_PERFCOUNTER7_LO[0], sizeof(mmPA_SC_PERFCOUNTER7_LO)/sizeof(mmPA_SC_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_HI", REG_MMIO, 0xd14f, &mmPA_SC_PERFCOUNTER7_HI[0], sizeof(mmPA_SC_PERFCOUNTER7_HI)/sizeof(mmPA_SC_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_HI", REG_MMIO, 0xd180, &mmSPI_PERFCOUNTER0_HI[0], sizeof(mmSPI_PERFCOUNTER0_HI)/sizeof(mmSPI_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_LO", REG_MMIO, 0xd181, &mmSPI_PERFCOUNTER0_LO[0], sizeof(mmSPI_PERFCOUNTER0_LO)/sizeof(mmSPI_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_HI", REG_MMIO, 0xd182, &mmSPI_PERFCOUNTER1_HI[0], sizeof(mmSPI_PERFCOUNTER1_HI)/sizeof(mmSPI_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_LO", REG_MMIO, 0xd183, &mmSPI_PERFCOUNTER1_LO[0], sizeof(mmSPI_PERFCOUNTER1_LO)/sizeof(mmSPI_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_HI", REG_MMIO, 0xd184, &mmSPI_PERFCOUNTER2_HI[0], sizeof(mmSPI_PERFCOUNTER2_HI)/sizeof(mmSPI_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_LO", REG_MMIO, 0xd185, &mmSPI_PERFCOUNTER2_LO[0], sizeof(mmSPI_PERFCOUNTER2_LO)/sizeof(mmSPI_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_HI", REG_MMIO, 0xd186, &mmSPI_PERFCOUNTER3_HI[0], sizeof(mmSPI_PERFCOUNTER3_HI)/sizeof(mmSPI_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_LO", REG_MMIO, 0xd187, &mmSPI_PERFCOUNTER3_LO[0], sizeof(mmSPI_PERFCOUNTER3_LO)/sizeof(mmSPI_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_HI", REG_MMIO, 0xd188, &mmSPI_PERFCOUNTER4_HI[0], sizeof(mmSPI_PERFCOUNTER4_HI)/sizeof(mmSPI_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_LO", REG_MMIO, 0xd189, &mmSPI_PERFCOUNTER4_LO[0], sizeof(mmSPI_PERFCOUNTER4_LO)/sizeof(mmSPI_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_HI", REG_MMIO, 0xd18a, &mmSPI_PERFCOUNTER5_HI[0], sizeof(mmSPI_PERFCOUNTER5_HI)/sizeof(mmSPI_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_LO", REG_MMIO, 0xd18b, &mmSPI_PERFCOUNTER5_LO[0], sizeof(mmSPI_PERFCOUNTER5_LO)/sizeof(mmSPI_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_LO", REG_MMIO, 0xd1c0, &mmSQ_PERFCOUNTER0_LO[0], sizeof(mmSQ_PERFCOUNTER0_LO)/sizeof(mmSQ_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_HI", REG_MMIO, 0xd1c1, &mmSQ_PERFCOUNTER0_HI[0], sizeof(mmSQ_PERFCOUNTER0_HI)/sizeof(mmSQ_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_LO", REG_MMIO, 0xd1c2, &mmSQ_PERFCOUNTER1_LO[0], sizeof(mmSQ_PERFCOUNTER1_LO)/sizeof(mmSQ_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_HI", REG_MMIO, 0xd1c3, &mmSQ_PERFCOUNTER1_HI[0], sizeof(mmSQ_PERFCOUNTER1_HI)/sizeof(mmSQ_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_LO", REG_MMIO, 0xd1c4, &mmSQ_PERFCOUNTER2_LO[0], sizeof(mmSQ_PERFCOUNTER2_LO)/sizeof(mmSQ_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_HI", REG_MMIO, 0xd1c5, &mmSQ_PERFCOUNTER2_HI[0], sizeof(mmSQ_PERFCOUNTER2_HI)/sizeof(mmSQ_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_LO", REG_MMIO, 0xd1c6, &mmSQ_PERFCOUNTER3_LO[0], sizeof(mmSQ_PERFCOUNTER3_LO)/sizeof(mmSQ_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_HI", REG_MMIO, 0xd1c7, &mmSQ_PERFCOUNTER3_HI[0], sizeof(mmSQ_PERFCOUNTER3_HI)/sizeof(mmSQ_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_LO", REG_MMIO, 0xd1c8, &mmSQ_PERFCOUNTER4_LO[0], sizeof(mmSQ_PERFCOUNTER4_LO)/sizeof(mmSQ_PERFCOUNTER4_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_HI", REG_MMIO, 0xd1c9, &mmSQ_PERFCOUNTER4_HI[0], sizeof(mmSQ_PERFCOUNTER4_HI)/sizeof(mmSQ_PERFCOUNTER4_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_LO", REG_MMIO, 0xd1ca, &mmSQ_PERFCOUNTER5_LO[0], sizeof(mmSQ_PERFCOUNTER5_LO)/sizeof(mmSQ_PERFCOUNTER5_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_HI", REG_MMIO, 0xd1cb, &mmSQ_PERFCOUNTER5_HI[0], sizeof(mmSQ_PERFCOUNTER5_HI)/sizeof(mmSQ_PERFCOUNTER5_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_LO", REG_MMIO, 0xd1cc, &mmSQ_PERFCOUNTER6_LO[0], sizeof(mmSQ_PERFCOUNTER6_LO)/sizeof(mmSQ_PERFCOUNTER6_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_HI", REG_MMIO, 0xd1cd, &mmSQ_PERFCOUNTER6_HI[0], sizeof(mmSQ_PERFCOUNTER6_HI)/sizeof(mmSQ_PERFCOUNTER6_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_LO", REG_MMIO, 0xd1ce, &mmSQ_PERFCOUNTER7_LO[0], sizeof(mmSQ_PERFCOUNTER7_LO)/sizeof(mmSQ_PERFCOUNTER7_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_HI", REG_MMIO, 0xd1cf, &mmSQ_PERFCOUNTER7_HI[0], sizeof(mmSQ_PERFCOUNTER7_HI)/sizeof(mmSQ_PERFCOUNTER7_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_LO", REG_MMIO, 0xd1d0, &mmSQ_PERFCOUNTER8_LO[0], sizeof(mmSQ_PERFCOUNTER8_LO)/sizeof(mmSQ_PERFCOUNTER8_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_HI", REG_MMIO, 0xd1d1, &mmSQ_PERFCOUNTER8_HI[0], sizeof(mmSQ_PERFCOUNTER8_HI)/sizeof(mmSQ_PERFCOUNTER8_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_LO", REG_MMIO, 0xd1d2, &mmSQ_PERFCOUNTER9_LO[0], sizeof(mmSQ_PERFCOUNTER9_LO)/sizeof(mmSQ_PERFCOUNTER9_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_HI", REG_MMIO, 0xd1d3, &mmSQ_PERFCOUNTER9_HI[0], sizeof(mmSQ_PERFCOUNTER9_HI)/sizeof(mmSQ_PERFCOUNTER9_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_LO", REG_MMIO, 0xd1d4, &mmSQ_PERFCOUNTER10_LO[0], sizeof(mmSQ_PERFCOUNTER10_LO)/sizeof(mmSQ_PERFCOUNTER10_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_HI", REG_MMIO, 0xd1d5, &mmSQ_PERFCOUNTER10_HI[0], sizeof(mmSQ_PERFCOUNTER10_HI)/sizeof(mmSQ_PERFCOUNTER10_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_LO", REG_MMIO, 0xd1d6, &mmSQ_PERFCOUNTER11_LO[0], sizeof(mmSQ_PERFCOUNTER11_LO)/sizeof(mmSQ_PERFCOUNTER11_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_HI", REG_MMIO, 0xd1d7, &mmSQ_PERFCOUNTER11_HI[0], sizeof(mmSQ_PERFCOUNTER11_HI)/sizeof(mmSQ_PERFCOUNTER11_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_LO", REG_MMIO, 0xd1d8, &mmSQ_PERFCOUNTER12_LO[0], sizeof(mmSQ_PERFCOUNTER12_LO)/sizeof(mmSQ_PERFCOUNTER12_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_HI", REG_MMIO, 0xd1d9, &mmSQ_PERFCOUNTER12_HI[0], sizeof(mmSQ_PERFCOUNTER12_HI)/sizeof(mmSQ_PERFCOUNTER12_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_LO", REG_MMIO, 0xd1da, &mmSQ_PERFCOUNTER13_LO[0], sizeof(mmSQ_PERFCOUNTER13_LO)/sizeof(mmSQ_PERFCOUNTER13_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_HI", REG_MMIO, 0xd1db, &mmSQ_PERFCOUNTER13_HI[0], sizeof(mmSQ_PERFCOUNTER13_HI)/sizeof(mmSQ_PERFCOUNTER13_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_LO", REG_MMIO, 0xd1dc, &mmSQ_PERFCOUNTER14_LO[0], sizeof(mmSQ_PERFCOUNTER14_LO)/sizeof(mmSQ_PERFCOUNTER14_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_HI", REG_MMIO, 0xd1dd, &mmSQ_PERFCOUNTER14_HI[0], sizeof(mmSQ_PERFCOUNTER14_HI)/sizeof(mmSQ_PERFCOUNTER14_HI[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_LO", REG_MMIO, 0xd1de, &mmSQ_PERFCOUNTER15_LO[0], sizeof(mmSQ_PERFCOUNTER15_LO)/sizeof(mmSQ_PERFCOUNTER15_LO[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_HI", REG_MMIO, 0xd1df, &mmSQ_PERFCOUNTER15_HI[0], sizeof(mmSQ_PERFCOUNTER15_HI)/sizeof(mmSQ_PERFCOUNTER15_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_LO", REG_MMIO, 0xd240, &mmSX_PERFCOUNTER0_LO[0], sizeof(mmSX_PERFCOUNTER0_LO)/sizeof(mmSX_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_HI", REG_MMIO, 0xd241, &mmSX_PERFCOUNTER0_HI[0], sizeof(mmSX_PERFCOUNTER0_HI)/sizeof(mmSX_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_LO", REG_MMIO, 0xd242, &mmSX_PERFCOUNTER1_LO[0], sizeof(mmSX_PERFCOUNTER1_LO)/sizeof(mmSX_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_HI", REG_MMIO, 0xd243, &mmSX_PERFCOUNTER1_HI[0], sizeof(mmSX_PERFCOUNTER1_HI)/sizeof(mmSX_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_LO", REG_MMIO, 0xd244, &mmSX_PERFCOUNTER2_LO[0], sizeof(mmSX_PERFCOUNTER2_LO)/sizeof(mmSX_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_HI", REG_MMIO, 0xd245, &mmSX_PERFCOUNTER2_HI[0], sizeof(mmSX_PERFCOUNTER2_HI)/sizeof(mmSX_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_LO", REG_MMIO, 0xd246, &mmSX_PERFCOUNTER3_LO[0], sizeof(mmSX_PERFCOUNTER3_LO)/sizeof(mmSX_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_HI", REG_MMIO, 0xd247, &mmSX_PERFCOUNTER3_HI[0], sizeof(mmSX_PERFCOUNTER3_HI)/sizeof(mmSX_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_LO", REG_MMIO, 0xd280, &mmGDS_PERFCOUNTER0_LO[0], sizeof(mmGDS_PERFCOUNTER0_LO)/sizeof(mmGDS_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_HI", REG_MMIO, 0xd281, &mmGDS_PERFCOUNTER0_HI[0], sizeof(mmGDS_PERFCOUNTER0_HI)/sizeof(mmGDS_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_LO", REG_MMIO, 0xd282, &mmGDS_PERFCOUNTER1_LO[0], sizeof(mmGDS_PERFCOUNTER1_LO)/sizeof(mmGDS_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_HI", REG_MMIO, 0xd283, &mmGDS_PERFCOUNTER1_HI[0], sizeof(mmGDS_PERFCOUNTER1_HI)/sizeof(mmGDS_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_LO", REG_MMIO, 0xd284, &mmGDS_PERFCOUNTER2_LO[0], sizeof(mmGDS_PERFCOUNTER2_LO)/sizeof(mmGDS_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_HI", REG_MMIO, 0xd285, &mmGDS_PERFCOUNTER2_HI[0], sizeof(mmGDS_PERFCOUNTER2_HI)/sizeof(mmGDS_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_LO", REG_MMIO, 0xd286, &mmGDS_PERFCOUNTER3_LO[0], sizeof(mmGDS_PERFCOUNTER3_LO)/sizeof(mmGDS_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_HI", REG_MMIO, 0xd287, &mmGDS_PERFCOUNTER3_HI[0], sizeof(mmGDS_PERFCOUNTER3_HI)/sizeof(mmGDS_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_LO", REG_MMIO, 0xd2c0, &mmTA_PERFCOUNTER0_LO[0], sizeof(mmTA_PERFCOUNTER0_LO)/sizeof(mmTA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_HI", REG_MMIO, 0xd2c1, &mmTA_PERFCOUNTER0_HI[0], sizeof(mmTA_PERFCOUNTER0_HI)/sizeof(mmTA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_LO", REG_MMIO, 0xd2c2, &mmTA_PERFCOUNTER1_LO[0], sizeof(mmTA_PERFCOUNTER1_LO)/sizeof(mmTA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_HI", REG_MMIO, 0xd2c3, &mmTA_PERFCOUNTER1_HI[0], sizeof(mmTA_PERFCOUNTER1_HI)/sizeof(mmTA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_LO", REG_MMIO, 0xd300, &mmTD_PERFCOUNTER0_LO[0], sizeof(mmTD_PERFCOUNTER0_LO)/sizeof(mmTD_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_HI", REG_MMIO, 0xd301, &mmTD_PERFCOUNTER0_HI[0], sizeof(mmTD_PERFCOUNTER0_HI)/sizeof(mmTD_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_LO", REG_MMIO, 0xd302, &mmTD_PERFCOUNTER1_LO[0], sizeof(mmTD_PERFCOUNTER1_LO)/sizeof(mmTD_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_HI", REG_MMIO, 0xd303, &mmTD_PERFCOUNTER1_HI[0], sizeof(mmTD_PERFCOUNTER1_HI)/sizeof(mmTD_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_LO", REG_MMIO, 0xd340, &mmTCP_PERFCOUNTER0_LO[0], sizeof(mmTCP_PERFCOUNTER0_LO)/sizeof(mmTCP_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_HI", REG_MMIO, 0xd341, &mmTCP_PERFCOUNTER0_HI[0], sizeof(mmTCP_PERFCOUNTER0_HI)/sizeof(mmTCP_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_LO", REG_MMIO, 0xd342, &mmTCP_PERFCOUNTER1_LO[0], sizeof(mmTCP_PERFCOUNTER1_LO)/sizeof(mmTCP_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_HI", REG_MMIO, 0xd343, &mmTCP_PERFCOUNTER1_HI[0], sizeof(mmTCP_PERFCOUNTER1_HI)/sizeof(mmTCP_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_LO", REG_MMIO, 0xd344, &mmTCP_PERFCOUNTER2_LO[0], sizeof(mmTCP_PERFCOUNTER2_LO)/sizeof(mmTCP_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_HI", REG_MMIO, 0xd345, &mmTCP_PERFCOUNTER2_HI[0], sizeof(mmTCP_PERFCOUNTER2_HI)/sizeof(mmTCP_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_LO", REG_MMIO, 0xd346, &mmTCP_PERFCOUNTER3_LO[0], sizeof(mmTCP_PERFCOUNTER3_LO)/sizeof(mmTCP_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_HI", REG_MMIO, 0xd347, &mmTCP_PERFCOUNTER3_HI[0], sizeof(mmTCP_PERFCOUNTER3_HI)/sizeof(mmTCP_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_LO", REG_MMIO, 0xd380, &mmTCC_PERFCOUNTER0_LO[0], sizeof(mmTCC_PERFCOUNTER0_LO)/sizeof(mmTCC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_HI", REG_MMIO, 0xd381, &mmTCC_PERFCOUNTER0_HI[0], sizeof(mmTCC_PERFCOUNTER0_HI)/sizeof(mmTCC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_LO", REG_MMIO, 0xd382, &mmTCC_PERFCOUNTER1_LO[0], sizeof(mmTCC_PERFCOUNTER1_LO)/sizeof(mmTCC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_HI", REG_MMIO, 0xd383, &mmTCC_PERFCOUNTER1_HI[0], sizeof(mmTCC_PERFCOUNTER1_HI)/sizeof(mmTCC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_LO", REG_MMIO, 0xd384, &mmTCC_PERFCOUNTER2_LO[0], sizeof(mmTCC_PERFCOUNTER2_LO)/sizeof(mmTCC_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_HI", REG_MMIO, 0xd385, &mmTCC_PERFCOUNTER2_HI[0], sizeof(mmTCC_PERFCOUNTER2_HI)/sizeof(mmTCC_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_LO", REG_MMIO, 0xd386, &mmTCC_PERFCOUNTER3_LO[0], sizeof(mmTCC_PERFCOUNTER3_LO)/sizeof(mmTCC_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_HI", REG_MMIO, 0xd387, &mmTCC_PERFCOUNTER3_HI[0], sizeof(mmTCC_PERFCOUNTER3_HI)/sizeof(mmTCC_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_LO", REG_MMIO, 0xd390, &mmTCA_PERFCOUNTER0_LO[0], sizeof(mmTCA_PERFCOUNTER0_LO)/sizeof(mmTCA_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_HI", REG_MMIO, 0xd391, &mmTCA_PERFCOUNTER0_HI[0], sizeof(mmTCA_PERFCOUNTER0_HI)/sizeof(mmTCA_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_LO", REG_MMIO, 0xd392, &mmTCA_PERFCOUNTER1_LO[0], sizeof(mmTCA_PERFCOUNTER1_LO)/sizeof(mmTCA_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_HI", REG_MMIO, 0xd393, &mmTCA_PERFCOUNTER1_HI[0], sizeof(mmTCA_PERFCOUNTER1_HI)/sizeof(mmTCA_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_LO", REG_MMIO, 0xd394, &mmTCA_PERFCOUNTER2_LO[0], sizeof(mmTCA_PERFCOUNTER2_LO)/sizeof(mmTCA_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_HI", REG_MMIO, 0xd395, &mmTCA_PERFCOUNTER2_HI[0], sizeof(mmTCA_PERFCOUNTER2_HI)/sizeof(mmTCA_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_LO", REG_MMIO, 0xd396, &mmTCA_PERFCOUNTER3_LO[0], sizeof(mmTCA_PERFCOUNTER3_LO)/sizeof(mmTCA_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_HI", REG_MMIO, 0xd397, &mmTCA_PERFCOUNTER3_HI[0], sizeof(mmTCA_PERFCOUNTER3_HI)/sizeof(mmTCA_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_LO", REG_MMIO, 0xd406, &mmCB_PERFCOUNTER0_LO[0], sizeof(mmCB_PERFCOUNTER0_LO)/sizeof(mmCB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_HI", REG_MMIO, 0xd407, &mmCB_PERFCOUNTER0_HI[0], sizeof(mmCB_PERFCOUNTER0_HI)/sizeof(mmCB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_LO", REG_MMIO, 0xd408, &mmCB_PERFCOUNTER1_LO[0], sizeof(mmCB_PERFCOUNTER1_LO)/sizeof(mmCB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_HI", REG_MMIO, 0xd409, &mmCB_PERFCOUNTER1_HI[0], sizeof(mmCB_PERFCOUNTER1_HI)/sizeof(mmCB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_LO", REG_MMIO, 0xd40a, &mmCB_PERFCOUNTER2_LO[0], sizeof(mmCB_PERFCOUNTER2_LO)/sizeof(mmCB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_HI", REG_MMIO, 0xd40b, &mmCB_PERFCOUNTER2_HI[0], sizeof(mmCB_PERFCOUNTER2_HI)/sizeof(mmCB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_LO", REG_MMIO, 0xd40c, &mmCB_PERFCOUNTER3_LO[0], sizeof(mmCB_PERFCOUNTER3_LO)/sizeof(mmCB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_HI", REG_MMIO, 0xd40d, &mmCB_PERFCOUNTER3_HI[0], sizeof(mmCB_PERFCOUNTER3_HI)/sizeof(mmCB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_LO", REG_MMIO, 0xd440, &mmDB_PERFCOUNTER0_LO[0], sizeof(mmDB_PERFCOUNTER0_LO)/sizeof(mmDB_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_HI", REG_MMIO, 0xd441, &mmDB_PERFCOUNTER0_HI[0], sizeof(mmDB_PERFCOUNTER0_HI)/sizeof(mmDB_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_LO", REG_MMIO, 0xd442, &mmDB_PERFCOUNTER1_LO[0], sizeof(mmDB_PERFCOUNTER1_LO)/sizeof(mmDB_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_HI", REG_MMIO, 0xd443, &mmDB_PERFCOUNTER1_HI[0], sizeof(mmDB_PERFCOUNTER1_HI)/sizeof(mmDB_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_LO", REG_MMIO, 0xd444, &mmDB_PERFCOUNTER2_LO[0], sizeof(mmDB_PERFCOUNTER2_LO)/sizeof(mmDB_PERFCOUNTER2_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_HI", REG_MMIO, 0xd445, &mmDB_PERFCOUNTER2_HI[0], sizeof(mmDB_PERFCOUNTER2_HI)/sizeof(mmDB_PERFCOUNTER2_HI[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_LO", REG_MMIO, 0xd446, &mmDB_PERFCOUNTER3_LO[0], sizeof(mmDB_PERFCOUNTER3_LO)/sizeof(mmDB_PERFCOUNTER3_LO[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_HI", REG_MMIO, 0xd447, &mmDB_PERFCOUNTER3_HI[0], sizeof(mmDB_PERFCOUNTER3_HI)/sizeof(mmDB_PERFCOUNTER3_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_LO", REG_MMIO, 0xd480, &mmRLC_PERFCOUNTER0_LO[0], sizeof(mmRLC_PERFCOUNTER0_LO)/sizeof(mmRLC_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_HI", REG_MMIO, 0xd481, &mmRLC_PERFCOUNTER0_HI[0], sizeof(mmRLC_PERFCOUNTER0_HI)/sizeof(mmRLC_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_LO", REG_MMIO, 0xd482, &mmRLC_PERFCOUNTER1_LO[0], sizeof(mmRLC_PERFCOUNTER1_LO)/sizeof(mmRLC_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_HI", REG_MMIO, 0xd483, &mmRLC_PERFCOUNTER1_HI[0], sizeof(mmRLC_PERFCOUNTER1_HI)/sizeof(mmRLC_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER1_SELECT", REG_MMIO, 0xd800, &mmCPG_PERFCOUNTER1_SELECT[0], sizeof(mmCPG_PERFCOUNTER1_SELECT)/sizeof(mmCPG_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd801, &mmCPG_PERFCOUNTER0_SELECT1[0], sizeof(mmCPG_PERFCOUNTER0_SELECT1)/sizeof(mmCPG_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPG_PERFCOUNTER0_SELECT", REG_MMIO, 0xd802, &mmCPG_PERFCOUNTER0_SELECT[0], sizeof(mmCPG_PERFCOUNTER0_SELECT)/sizeof(mmCPG_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd803, &mmCPC_PERFCOUNTER1_SELECT[0], sizeof(mmCPC_PERFCOUNTER1_SELECT)/sizeof(mmCPC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd804, &mmCPC_PERFCOUNTER0_SELECT1[0], sizeof(mmCPC_PERFCOUNTER0_SELECT1)/sizeof(mmCPC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER1_SELECT", REG_MMIO, 0xd805, &mmCPF_PERFCOUNTER1_SELECT[0], sizeof(mmCPF_PERFCOUNTER1_SELECT)/sizeof(mmCPF_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd806, &mmCPF_PERFCOUNTER0_SELECT1[0], sizeof(mmCPF_PERFCOUNTER0_SELECT1)/sizeof(mmCPF_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCPF_PERFCOUNTER0_SELECT", REG_MMIO, 0xd807, &mmCPF_PERFCOUNTER0_SELECT[0], sizeof(mmCPF_PERFCOUNTER0_SELECT)/sizeof(mmCPF_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCP_PERFMON_CNTL", REG_MMIO, 0xd808, &mmCP_PERFMON_CNTL[0], sizeof(mmCP_PERFMON_CNTL)/sizeof(mmCP_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmCPC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd809, &mmCPC_PERFCOUNTER0_SELECT[0], sizeof(mmCPC_PERFCOUNTER0_SELECT)/sizeof(mmCPC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCP_DRAW_OBJECT", REG_MMIO, 0xd810, &mmCP_DRAW_OBJECT[0], sizeof(mmCP_DRAW_OBJECT)/sizeof(mmCP_DRAW_OBJECT[0]), 0, 0 },
+	{ "mmCP_DRAW_OBJECT_COUNTER", REG_MMIO, 0xd811, &mmCP_DRAW_OBJECT_COUNTER[0], sizeof(mmCP_DRAW_OBJECT_COUNTER)/sizeof(mmCP_DRAW_OBJECT_COUNTER[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_MASK_HI", REG_MMIO, 0xd812, &mmCP_DRAW_WINDOW_MASK_HI[0], sizeof(mmCP_DRAW_WINDOW_MASK_HI)/sizeof(mmCP_DRAW_WINDOW_MASK_HI[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_HI", REG_MMIO, 0xd813, &mmCP_DRAW_WINDOW_HI[0], sizeof(mmCP_DRAW_WINDOW_HI)/sizeof(mmCP_DRAW_WINDOW_HI[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_LO", REG_MMIO, 0xd814, &mmCP_DRAW_WINDOW_LO[0], sizeof(mmCP_DRAW_WINDOW_LO)/sizeof(mmCP_DRAW_WINDOW_LO[0]), 0, 0 },
+	{ "mmCP_DRAW_WINDOW_CNTL", REG_MMIO, 0xd815, &mmCP_DRAW_WINDOW_CNTL[0], sizeof(mmCP_DRAW_WINDOW_CNTL)/sizeof(mmCP_DRAW_WINDOW_CNTL[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0xd840, &mmGRBM_PERFCOUNTER0_SELECT[0], sizeof(mmGRBM_PERFCOUNTER0_SELECT)/sizeof(mmGRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0xd841, &mmGRBM_PERFCOUNTER1_SELECT[0], sizeof(mmGRBM_PERFCOUNTER1_SELECT)/sizeof(mmGRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE0_PERFCOUNTER_SELECT", REG_MMIO, 0xd842, &mmGRBM_SE0_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE0_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE1_PERFCOUNTER_SELECT", REG_MMIO, 0xd843, &mmGRBM_SE1_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE1_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE2_PERFCOUNTER_SELECT", REG_MMIO, 0xd844, &mmGRBM_SE2_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE2_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmGRBM_SE3_PERFCOUNTER_SELECT", REG_MMIO, 0xd845, &mmGRBM_SE3_PERFCOUNTER_SELECT[0], sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT)/sizeof(mmGRBM_SE3_PERFCOUNTER_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER0_SELECT", REG_MMIO, 0xd880, &mmWD_PERFCOUNTER0_SELECT[0], sizeof(mmWD_PERFCOUNTER0_SELECT)/sizeof(mmWD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER1_SELECT", REG_MMIO, 0xd881, &mmWD_PERFCOUNTER1_SELECT[0], sizeof(mmWD_PERFCOUNTER1_SELECT)/sizeof(mmWD_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER2_SELECT", REG_MMIO, 0xd882, &mmWD_PERFCOUNTER2_SELECT[0], sizeof(mmWD_PERFCOUNTER2_SELECT)/sizeof(mmWD_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmWD_PERFCOUNTER3_SELECT", REG_MMIO, 0xd883, &mmWD_PERFCOUNTER3_SELECT[0], sizeof(mmWD_PERFCOUNTER3_SELECT)/sizeof(mmWD_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT", REG_MMIO, 0xd884, &mmIA_PERFCOUNTER0_SELECT[0], sizeof(mmIA_PERFCOUNTER0_SELECT)/sizeof(mmIA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER1_SELECT", REG_MMIO, 0xd885, &mmIA_PERFCOUNTER1_SELECT[0], sizeof(mmIA_PERFCOUNTER1_SELECT)/sizeof(mmIA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER2_SELECT", REG_MMIO, 0xd886, &mmIA_PERFCOUNTER2_SELECT[0], sizeof(mmIA_PERFCOUNTER2_SELECT)/sizeof(mmIA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER3_SELECT", REG_MMIO, 0xd887, &mmIA_PERFCOUNTER3_SELECT[0], sizeof(mmIA_PERFCOUNTER3_SELECT)/sizeof(mmIA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmIA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd888, &mmIA_PERFCOUNTER0_SELECT1[0], sizeof(mmIA_PERFCOUNTER0_SELECT1)/sizeof(mmIA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT", REG_MMIO, 0xd88c, &mmVGT_PERFCOUNTER0_SELECT[0], sizeof(mmVGT_PERFCOUNTER0_SELECT)/sizeof(mmVGT_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT", REG_MMIO, 0xd88d, &mmVGT_PERFCOUNTER1_SELECT[0], sizeof(mmVGT_PERFCOUNTER1_SELECT)/sizeof(mmVGT_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER2_SELECT", REG_MMIO, 0xd88e, &mmVGT_PERFCOUNTER2_SELECT[0], sizeof(mmVGT_PERFCOUNTER2_SELECT)/sizeof(mmVGT_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER3_SELECT", REG_MMIO, 0xd88f, &mmVGT_PERFCOUNTER3_SELECT[0], sizeof(mmVGT_PERFCOUNTER3_SELECT)/sizeof(mmVGT_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd890, &mmVGT_PERFCOUNTER0_SELECT1[0], sizeof(mmVGT_PERFCOUNTER0_SELECT1)/sizeof(mmVGT_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd891, &mmVGT_PERFCOUNTER1_SELECT1[0], sizeof(mmVGT_PERFCOUNTER1_SELECT1)/sizeof(mmVGT_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmVGT_PERFCOUNTER_SEID_MASK", REG_MMIO, 0xd894, &mmVGT_PERFCOUNTER_SEID_MASK[0], sizeof(mmVGT_PERFCOUNTER_SEID_MASK)/sizeof(mmVGT_PERFCOUNTER_SEID_MASK[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT", REG_MMIO, 0xd900, &mmPA_SU_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd901, &mmPA_SU_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT", REG_MMIO, 0xd902, &mmPA_SU_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd903, &mmPA_SU_PERFCOUNTER1_SELECT1[0], sizeof(mmPA_SU_PERFCOUNTER1_SELECT1)/sizeof(mmPA_SU_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER2_SELECT", REG_MMIO, 0xd904, &mmPA_SU_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER2_SELECT)/sizeof(mmPA_SU_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SU_PERFCOUNTER3_SELECT", REG_MMIO, 0xd905, &mmPA_SU_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SU_PERFCOUNTER3_SELECT)/sizeof(mmPA_SU_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT", REG_MMIO, 0xd940, &mmPA_SC_PERFCOUNTER0_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd941, &mmPA_SC_PERFCOUNTER0_SELECT1[0], sizeof(mmPA_SC_PERFCOUNTER0_SELECT1)/sizeof(mmPA_SC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER1_SELECT", REG_MMIO, 0xd942, &mmPA_SC_PERFCOUNTER1_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER1_SELECT)/sizeof(mmPA_SC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER2_SELECT", REG_MMIO, 0xd943, &mmPA_SC_PERFCOUNTER2_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER2_SELECT)/sizeof(mmPA_SC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER3_SELECT", REG_MMIO, 0xd944, &mmPA_SC_PERFCOUNTER3_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER3_SELECT)/sizeof(mmPA_SC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER4_SELECT", REG_MMIO, 0xd945, &mmPA_SC_PERFCOUNTER4_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER4_SELECT)/sizeof(mmPA_SC_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER5_SELECT", REG_MMIO, 0xd946, &mmPA_SC_PERFCOUNTER5_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER5_SELECT)/sizeof(mmPA_SC_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER6_SELECT", REG_MMIO, 0xd947, &mmPA_SC_PERFCOUNTER6_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER6_SELECT)/sizeof(mmPA_SC_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmPA_SC_PERFCOUNTER7_SELECT", REG_MMIO, 0xd948, &mmPA_SC_PERFCOUNTER7_SELECT[0], sizeof(mmPA_SC_PERFCOUNTER7_SELECT)/sizeof(mmPA_SC_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT", REG_MMIO, 0xd980, &mmSPI_PERFCOUNTER0_SELECT[0], sizeof(mmSPI_PERFCOUNTER0_SELECT)/sizeof(mmSPI_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT", REG_MMIO, 0xd981, &mmSPI_PERFCOUNTER1_SELECT[0], sizeof(mmSPI_PERFCOUNTER1_SELECT)/sizeof(mmSPI_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT", REG_MMIO, 0xd982, &mmSPI_PERFCOUNTER2_SELECT[0], sizeof(mmSPI_PERFCOUNTER2_SELECT)/sizeof(mmSPI_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT", REG_MMIO, 0xd983, &mmSPI_PERFCOUNTER3_SELECT[0], sizeof(mmSPI_PERFCOUNTER3_SELECT)/sizeof(mmSPI_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER0_SELECT1", REG_MMIO, 0xd984, &mmSPI_PERFCOUNTER0_SELECT1[0], sizeof(mmSPI_PERFCOUNTER0_SELECT1)/sizeof(mmSPI_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER1_SELECT1", REG_MMIO, 0xd985, &mmSPI_PERFCOUNTER1_SELECT1[0], sizeof(mmSPI_PERFCOUNTER1_SELECT1)/sizeof(mmSPI_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER2_SELECT1", REG_MMIO, 0xd986, &mmSPI_PERFCOUNTER2_SELECT1[0], sizeof(mmSPI_PERFCOUNTER2_SELECT1)/sizeof(mmSPI_PERFCOUNTER2_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER3_SELECT1", REG_MMIO, 0xd987, &mmSPI_PERFCOUNTER3_SELECT1[0], sizeof(mmSPI_PERFCOUNTER3_SELECT1)/sizeof(mmSPI_PERFCOUNTER3_SELECT1[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER4_SELECT", REG_MMIO, 0xd988, &mmSPI_PERFCOUNTER4_SELECT[0], sizeof(mmSPI_PERFCOUNTER4_SELECT)/sizeof(mmSPI_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER5_SELECT", REG_MMIO, 0xd989, &mmSPI_PERFCOUNTER5_SELECT[0], sizeof(mmSPI_PERFCOUNTER5_SELECT)/sizeof(mmSPI_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSPI_PERFCOUNTER_BINS", REG_MMIO, 0xd98a, &mmSPI_PERFCOUNTER_BINS[0], sizeof(mmSPI_PERFCOUNTER_BINS)/sizeof(mmSPI_PERFCOUNTER_BINS[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER0_SELECT", REG_MMIO, 0xd9c0, &mmSQ_PERFCOUNTER0_SELECT[0], sizeof(mmSQ_PERFCOUNTER0_SELECT)/sizeof(mmSQ_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER1_SELECT", REG_MMIO, 0xd9c1, &mmSQ_PERFCOUNTER1_SELECT[0], sizeof(mmSQ_PERFCOUNTER1_SELECT)/sizeof(mmSQ_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER2_SELECT", REG_MMIO, 0xd9c2, &mmSQ_PERFCOUNTER2_SELECT[0], sizeof(mmSQ_PERFCOUNTER2_SELECT)/sizeof(mmSQ_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER3_SELECT", REG_MMIO, 0xd9c3, &mmSQ_PERFCOUNTER3_SELECT[0], sizeof(mmSQ_PERFCOUNTER3_SELECT)/sizeof(mmSQ_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER4_SELECT", REG_MMIO, 0xd9c4, &mmSQ_PERFCOUNTER4_SELECT[0], sizeof(mmSQ_PERFCOUNTER4_SELECT)/sizeof(mmSQ_PERFCOUNTER4_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER5_SELECT", REG_MMIO, 0xd9c5, &mmSQ_PERFCOUNTER5_SELECT[0], sizeof(mmSQ_PERFCOUNTER5_SELECT)/sizeof(mmSQ_PERFCOUNTER5_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER6_SELECT", REG_MMIO, 0xd9c6, &mmSQ_PERFCOUNTER6_SELECT[0], sizeof(mmSQ_PERFCOUNTER6_SELECT)/sizeof(mmSQ_PERFCOUNTER6_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER7_SELECT", REG_MMIO, 0xd9c7, &mmSQ_PERFCOUNTER7_SELECT[0], sizeof(mmSQ_PERFCOUNTER7_SELECT)/sizeof(mmSQ_PERFCOUNTER7_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER8_SELECT", REG_MMIO, 0xd9c8, &mmSQ_PERFCOUNTER8_SELECT[0], sizeof(mmSQ_PERFCOUNTER8_SELECT)/sizeof(mmSQ_PERFCOUNTER8_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER9_SELECT", REG_MMIO, 0xd9c9, &mmSQ_PERFCOUNTER9_SELECT[0], sizeof(mmSQ_PERFCOUNTER9_SELECT)/sizeof(mmSQ_PERFCOUNTER9_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER10_SELECT", REG_MMIO, 0xd9ca, &mmSQ_PERFCOUNTER10_SELECT[0], sizeof(mmSQ_PERFCOUNTER10_SELECT)/sizeof(mmSQ_PERFCOUNTER10_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER11_SELECT", REG_MMIO, 0xd9cb, &mmSQ_PERFCOUNTER11_SELECT[0], sizeof(mmSQ_PERFCOUNTER11_SELECT)/sizeof(mmSQ_PERFCOUNTER11_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER12_SELECT", REG_MMIO, 0xd9cc, &mmSQ_PERFCOUNTER12_SELECT[0], sizeof(mmSQ_PERFCOUNTER12_SELECT)/sizeof(mmSQ_PERFCOUNTER12_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER13_SELECT", REG_MMIO, 0xd9cd, &mmSQ_PERFCOUNTER13_SELECT[0], sizeof(mmSQ_PERFCOUNTER13_SELECT)/sizeof(mmSQ_PERFCOUNTER13_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER14_SELECT", REG_MMIO, 0xd9ce, &mmSQ_PERFCOUNTER14_SELECT[0], sizeof(mmSQ_PERFCOUNTER14_SELECT)/sizeof(mmSQ_PERFCOUNTER14_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER15_SELECT", REG_MMIO, 0xd9cf, &mmSQ_PERFCOUNTER15_SELECT[0], sizeof(mmSQ_PERFCOUNTER15_SELECT)/sizeof(mmSQ_PERFCOUNTER15_SELECT[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL", REG_MMIO, 0xd9e0, &mmSQ_PERFCOUNTER_CTRL[0], sizeof(mmSQ_PERFCOUNTER_CTRL)/sizeof(mmSQ_PERFCOUNTER_CTRL[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_MASK", REG_MMIO, 0xd9e1, &mmSQ_PERFCOUNTER_MASK[0], sizeof(mmSQ_PERFCOUNTER_MASK)/sizeof(mmSQ_PERFCOUNTER_MASK[0]), 0, 0 },
+	{ "mmSQ_PERFCOUNTER_CTRL2", REG_MMIO, 0xd9e2, &mmSQ_PERFCOUNTER_CTRL2[0], sizeof(mmSQ_PERFCOUNTER_CTRL2)/sizeof(mmSQ_PERFCOUNTER_CTRL2[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT", REG_MMIO, 0xda40, &mmSX_PERFCOUNTER0_SELECT[0], sizeof(mmSX_PERFCOUNTER0_SELECT)/sizeof(mmSX_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT", REG_MMIO, 0xda41, &mmSX_PERFCOUNTER1_SELECT[0], sizeof(mmSX_PERFCOUNTER1_SELECT)/sizeof(mmSX_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER2_SELECT", REG_MMIO, 0xda42, &mmSX_PERFCOUNTER2_SELECT[0], sizeof(mmSX_PERFCOUNTER2_SELECT)/sizeof(mmSX_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER3_SELECT", REG_MMIO, 0xda43, &mmSX_PERFCOUNTER3_SELECT[0], sizeof(mmSX_PERFCOUNTER3_SELECT)/sizeof(mmSX_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda44, &mmSX_PERFCOUNTER0_SELECT1[0], sizeof(mmSX_PERFCOUNTER0_SELECT1)/sizeof(mmSX_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmSX_PERFCOUNTER1_SELECT1", REG_MMIO, 0xda45, &mmSX_PERFCOUNTER1_SELECT1[0], sizeof(mmSX_PERFCOUNTER1_SELECT1)/sizeof(mmSX_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT", REG_MMIO, 0xda80, &mmGDS_PERFCOUNTER0_SELECT[0], sizeof(mmGDS_PERFCOUNTER0_SELECT)/sizeof(mmGDS_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER1_SELECT", REG_MMIO, 0xda81, &mmGDS_PERFCOUNTER1_SELECT[0], sizeof(mmGDS_PERFCOUNTER1_SELECT)/sizeof(mmGDS_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER2_SELECT", REG_MMIO, 0xda82, &mmGDS_PERFCOUNTER2_SELECT[0], sizeof(mmGDS_PERFCOUNTER2_SELECT)/sizeof(mmGDS_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER3_SELECT", REG_MMIO, 0xda83, &mmGDS_PERFCOUNTER3_SELECT[0], sizeof(mmGDS_PERFCOUNTER3_SELECT)/sizeof(mmGDS_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmGDS_PERFCOUNTER0_SELECT1", REG_MMIO, 0xda84, &mmGDS_PERFCOUNTER0_SELECT1[0], sizeof(mmGDS_PERFCOUNTER0_SELECT1)/sizeof(mmGDS_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdac0, &mmTA_PERFCOUNTER0_SELECT[0], sizeof(mmTA_PERFCOUNTER0_SELECT)/sizeof(mmTA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdac1, &mmTA_PERFCOUNTER0_SELECT1[0], sizeof(mmTA_PERFCOUNTER0_SELECT1)/sizeof(mmTA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdac2, &mmTA_PERFCOUNTER1_SELECT[0], sizeof(mmTA_PERFCOUNTER1_SELECT)/sizeof(mmTA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb00, &mmTD_PERFCOUNTER0_SELECT[0], sizeof(mmTD_PERFCOUNTER0_SELECT)/sizeof(mmTD_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb01, &mmTD_PERFCOUNTER0_SELECT1[0], sizeof(mmTD_PERFCOUNTER0_SELECT1)/sizeof(mmTD_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTD_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb02, &mmTD_PERFCOUNTER1_SELECT[0], sizeof(mmTD_PERFCOUNTER1_SELECT)/sizeof(mmTD_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb40, &mmTCP_PERFCOUNTER0_SELECT[0], sizeof(mmTCP_PERFCOUNTER0_SELECT)/sizeof(mmTCP_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb41, &mmTCP_PERFCOUNTER0_SELECT1[0], sizeof(mmTCP_PERFCOUNTER0_SELECT1)/sizeof(mmTCP_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb42, &mmTCP_PERFCOUNTER1_SELECT[0], sizeof(mmTCP_PERFCOUNTER1_SELECT)/sizeof(mmTCP_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb43, &mmTCP_PERFCOUNTER1_SELECT1[0], sizeof(mmTCP_PERFCOUNTER1_SELECT1)/sizeof(mmTCP_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb44, &mmTCP_PERFCOUNTER2_SELECT[0], sizeof(mmTCP_PERFCOUNTER2_SELECT)/sizeof(mmTCP_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCP_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb45, &mmTCP_PERFCOUNTER3_SELECT[0], sizeof(mmTCP_PERFCOUNTER3_SELECT)/sizeof(mmTCP_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb80, &mmTCC_PERFCOUNTER0_SELECT[0], sizeof(mmTCC_PERFCOUNTER0_SELECT)/sizeof(mmTCC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb81, &mmTCC_PERFCOUNTER0_SELECT1[0], sizeof(mmTCC_PERFCOUNTER0_SELECT1)/sizeof(mmTCC_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb82, &mmTCC_PERFCOUNTER1_SELECT[0], sizeof(mmTCC_PERFCOUNTER1_SELECT)/sizeof(mmTCC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb83, &mmTCC_PERFCOUNTER1_SELECT1[0], sizeof(mmTCC_PERFCOUNTER1_SELECT1)/sizeof(mmTCC_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb84, &mmTCC_PERFCOUNTER2_SELECT[0], sizeof(mmTCC_PERFCOUNTER2_SELECT)/sizeof(mmTCC_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCC_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb85, &mmTCC_PERFCOUNTER3_SELECT[0], sizeof(mmTCC_PERFCOUNTER3_SELECT)/sizeof(mmTCC_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT", REG_MMIO, 0xdb90, &mmTCA_PERFCOUNTER0_SELECT[0], sizeof(mmTCA_PERFCOUNTER0_SELECT)/sizeof(mmTCA_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdb91, &mmTCA_PERFCOUNTER0_SELECT1[0], sizeof(mmTCA_PERFCOUNTER0_SELECT1)/sizeof(mmTCA_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT", REG_MMIO, 0xdb92, &mmTCA_PERFCOUNTER1_SELECT[0], sizeof(mmTCA_PERFCOUNTER1_SELECT)/sizeof(mmTCA_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdb93, &mmTCA_PERFCOUNTER1_SELECT1[0], sizeof(mmTCA_PERFCOUNTER1_SELECT1)/sizeof(mmTCA_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER2_SELECT", REG_MMIO, 0xdb94, &mmTCA_PERFCOUNTER2_SELECT[0], sizeof(mmTCA_PERFCOUNTER2_SELECT)/sizeof(mmTCA_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmTCA_PERFCOUNTER3_SELECT", REG_MMIO, 0xdb95, &mmTCA_PERFCOUNTER3_SELECT[0], sizeof(mmTCA_PERFCOUNTER3_SELECT)/sizeof(mmTCA_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER_FILTER", REG_MMIO, 0xdc00, &mmCB_PERFCOUNTER_FILTER[0], sizeof(mmCB_PERFCOUNTER_FILTER)/sizeof(mmCB_PERFCOUNTER_FILTER[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc01, &mmCB_PERFCOUNTER0_SELECT[0], sizeof(mmCB_PERFCOUNTER0_SELECT)/sizeof(mmCB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc02, &mmCB_PERFCOUNTER0_SELECT1[0], sizeof(mmCB_PERFCOUNTER0_SELECT1)/sizeof(mmCB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc03, &mmCB_PERFCOUNTER1_SELECT[0], sizeof(mmCB_PERFCOUNTER1_SELECT)/sizeof(mmCB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc04, &mmCB_PERFCOUNTER2_SELECT[0], sizeof(mmCB_PERFCOUNTER2_SELECT)/sizeof(mmCB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmCB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc05, &mmCB_PERFCOUNTER3_SELECT[0], sizeof(mmCB_PERFCOUNTER3_SELECT)/sizeof(mmCB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT", REG_MMIO, 0xdc40, &mmDB_PERFCOUNTER0_SELECT[0], sizeof(mmDB_PERFCOUNTER0_SELECT)/sizeof(mmDB_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER0_SELECT1", REG_MMIO, 0xdc41, &mmDB_PERFCOUNTER0_SELECT1[0], sizeof(mmDB_PERFCOUNTER0_SELECT1)/sizeof(mmDB_PERFCOUNTER0_SELECT1[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT", REG_MMIO, 0xdc42, &mmDB_PERFCOUNTER1_SELECT[0], sizeof(mmDB_PERFCOUNTER1_SELECT)/sizeof(mmDB_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER1_SELECT1", REG_MMIO, 0xdc43, &mmDB_PERFCOUNTER1_SELECT1[0], sizeof(mmDB_PERFCOUNTER1_SELECT1)/sizeof(mmDB_PERFCOUNTER1_SELECT1[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER2_SELECT", REG_MMIO, 0xdc44, &mmDB_PERFCOUNTER2_SELECT[0], sizeof(mmDB_PERFCOUNTER2_SELECT)/sizeof(mmDB_PERFCOUNTER2_SELECT[0]), 0, 0 },
+	{ "mmDB_PERFCOUNTER3_SELECT", REG_MMIO, 0xdc46, &mmDB_PERFCOUNTER3_SELECT[0], sizeof(mmDB_PERFCOUNTER3_SELECT)/sizeof(mmDB_PERFCOUNTER3_SELECT[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_CNTL", REG_MMIO, 0xdc80, &mmRLC_SPM_PERFMON_CNTL[0], sizeof(mmRLC_SPM_PERFMON_CNTL)/sizeof(mmRLC_SPM_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_BASE_LO", REG_MMIO, 0xdc81, &mmRLC_SPM_PERFMON_RING_BASE_LO[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_LO[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_BASE_HI", REG_MMIO, 0xdc82, &mmRLC_SPM_PERFMON_RING_BASE_HI[0], sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI)/sizeof(mmRLC_SPM_PERFMON_RING_BASE_HI[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_RING_SIZE", REG_MMIO, 0xdc83, &mmRLC_SPM_PERFMON_RING_SIZE[0], sizeof(mmRLC_SPM_PERFMON_RING_SIZE)/sizeof(mmRLC_SPM_PERFMON_RING_SIZE[0]), 0, 0 },
+	{ "mmRLC_SPM_PERFMON_SEGMENT_SIZE", REG_MMIO, 0xdc84, &mmRLC_SPM_PERFMON_SEGMENT_SIZE[0], sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE)/sizeof(mmRLC_SPM_PERFMON_SEGMENT_SIZE[0]), 0, 0 },
+	{ "mmRLC_SPM_SE_MUXSEL_ADDR", REG_MMIO, 0xdc85, &mmRLC_SPM_SE_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_SE_MUXSEL_ADDR)/sizeof(mmRLC_SPM_SE_MUXSEL_ADDR[0]), 0, 0 },
+	{ "mmRLC_SPM_SE_MUXSEL_DATA", REG_MMIO, 0xdc86, &mmRLC_SPM_SE_MUXSEL_DATA[0], sizeof(mmRLC_SPM_SE_MUXSEL_DATA)/sizeof(mmRLC_SPM_SE_MUXSEL_DATA[0]), 0, 0 },
+	{ "mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc87, &mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc88, &mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc89, &mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8a, &mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8b, &mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8c, &mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8d, &mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc8e, &mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc90, &mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc91, &mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc92, &mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc93, &mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc94, &mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc95, &mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc96, &mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc97, &mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc98, &mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY", REG_MMIO, 0xdc9a, &mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0], sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY)/sizeof(mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY[0]), 0, 0 },
+	{ "mmRLC_SPM_GLOBAL_MUXSEL_ADDR", REG_MMIO, 0xdc9b, &mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_ADDR[0]), 0, 0 },
+	{ "mmRLC_SPM_GLOBAL_MUXSEL_DATA", REG_MMIO, 0xdc9c, &mmRLC_SPM_GLOBAL_MUXSEL_DATA[0], sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA)/sizeof(mmRLC_SPM_GLOBAL_MUXSEL_DATA[0]), 0, 0 },
+	{ "mmRLC_SPM_RING_RDPTR", REG_MMIO, 0xdc9d, &mmRLC_SPM_RING_RDPTR[0], sizeof(mmRLC_SPM_RING_RDPTR)/sizeof(mmRLC_SPM_RING_RDPTR[0]), 0, 0 },
+	{ "mmRLC_SPM_SEGMENT_THRESHOLD", REG_MMIO, 0xdc9e, &mmRLC_SPM_SEGMENT_THRESHOLD[0], sizeof(mmRLC_SPM_SEGMENT_THRESHOLD)/sizeof(mmRLC_SPM_SEGMENT_THRESHOLD[0]), 0, 0 },
+	{ "mmRLC_PERFMON_CLK_CNTL", REG_MMIO, 0xdcbf, &mmRLC_PERFMON_CLK_CNTL[0], sizeof(mmRLC_PERFMON_CLK_CNTL)/sizeof(mmRLC_PERFMON_CLK_CNTL[0]), 0, 0 },
+	{ "mmRLC_PERFMON_CNTL", REG_MMIO, 0xdcc0, &mmRLC_PERFMON_CNTL[0], sizeof(mmRLC_PERFMON_CNTL)/sizeof(mmRLC_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER0_SELECT", REG_MMIO, 0xdcc1, &mmRLC_PERFCOUNTER0_SELECT[0], sizeof(mmRLC_PERFCOUNTER0_SELECT)/sizeof(mmRLC_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmRLC_PERFCOUNTER1_SELECT", REG_MMIO, 0xdcc2, &mmRLC_PERFCOUNTER1_SELECT[0], sizeof(mmRLC_PERFCOUNTER1_SELECT)/sizeof(mmRLC_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG14", REG_SMC, 0xe, &ixCLIPPER_DEBUG_REG14[0], sizeof(ixCLIPPER_DEBUG_REG14)/sizeof(ixCLIPPER_DEBUG_REG14[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG14", REG_SMC, 0xe, &ixVGT_DEBUG_REG14[0], sizeof(ixVGT_DEBUG_REG14)/sizeof(ixVGT_DEBUG_REG14[0]), 0, 0 },
+	{ "mmRLC_CNTL", REG_MMIO, 0xec00, &mmRLC_CNTL[0], sizeof(mmRLC_CNTL)/sizeof(mmRLC_CNTL[0]), 0, 0 },
+	{ "mmRLC_DEBUG_SELECT", REG_MMIO, 0xec01, &mmRLC_DEBUG_SELECT[0], sizeof(mmRLC_DEBUG_SELECT)/sizeof(mmRLC_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_DEBUG", REG_MMIO, 0xec02, &mmRLC_DEBUG[0], sizeof(mmRLC_DEBUG)/sizeof(mmRLC_DEBUG[0]), 0, 0 },
+	{ "mmRLC_MC_CNTL", REG_MMIO, 0xec03, &mmRLC_MC_CNTL[0], sizeof(mmRLC_MC_CNTL)/sizeof(mmRLC_MC_CNTL[0]), 0, 0 },
+	{ "mmRLC_STAT", REG_MMIO, 0xec04, &mmRLC_STAT[0], sizeof(mmRLC_STAT)/sizeof(mmRLC_STAT[0]), 0, 0 },
+	{ "mmRLC_SAFE_MODE", REG_MMIO, 0xec05, &mmRLC_SAFE_MODE[0], sizeof(mmRLC_SAFE_MODE)/sizeof(mmRLC_SAFE_MODE[0]), 0, 0 },
+	{ "mmRLC_MEM_SLP_CNTL", REG_MMIO, 0xec06, &mmRLC_MEM_SLP_CNTL[0], sizeof(mmRLC_MEM_SLP_CNTL)/sizeof(mmRLC_MEM_SLP_CNTL[0]), 0, 0 },
+	{ "mmSMU_RLC_RESPONSE", REG_MMIO, 0xec07, &mmSMU_RLC_RESPONSE[0], sizeof(mmSMU_RLC_RESPONSE)/sizeof(mmSMU_RLC_RESPONSE[0]), 0, 0 },
+	{ "mmRLC_RLCV_SAFE_MODE", REG_MMIO, 0xec08, &mmRLC_RLCV_SAFE_MODE[0], sizeof(mmRLC_RLCV_SAFE_MODE)/sizeof(mmRLC_RLCV_SAFE_MODE[0]), 0, 0 },
+	{ "mmRLC_SMU_SAFE_MODE", REG_MMIO, 0xec09, &mmRLC_SMU_SAFE_MODE[0], sizeof(mmRLC_SMU_SAFE_MODE)/sizeof(mmRLC_SMU_SAFE_MODE[0]), 0, 0 },
+	{ "mmRLC_RLCV_COMMAND", REG_MMIO, 0xec0a, &mmRLC_RLCV_COMMAND[0], sizeof(mmRLC_RLCV_COMMAND)/sizeof(mmRLC_RLCV_COMMAND[0]), 0, 0 },
+	{ "mmRLC_CLK_CNTL", REG_MMIO, 0xec0b, &mmRLC_CLK_CNTL[0], sizeof(mmRLC_CLK_CNTL)/sizeof(mmRLC_CLK_CNTL[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_MAX", REG_MMIO, 0xec12, &mmRLC_LB_CNTR_MAX[0], sizeof(mmRLC_LB_CNTR_MAX)/sizeof(mmRLC_LB_CNTR_MAX[0]), 0, 0 },
+	{ "mmRLC_LB_CNTL", REG_MMIO, 0xec19, &mmRLC_LB_CNTL[0], sizeof(mmRLC_LB_CNTL)/sizeof(mmRLC_LB_CNTL[0]), 0, 0 },
+	{ "mmRLC_MGCG_CTRL", REG_MMIO, 0xec1a, &mmRLC_MGCG_CTRL[0], sizeof(mmRLC_MGCG_CTRL)/sizeof(mmRLC_MGCG_CTRL[0]), 0, 0 },
+	{ "mmRLC_LB_CNTR_INIT", REG_MMIO, 0xec1b, &mmRLC_LB_CNTR_INIT[0], sizeof(mmRLC_LB_CNTR_INIT)/sizeof(mmRLC_LB_CNTR_INIT[0]), 0, 0 },
+	{ "mmRLC_LOAD_BALANCE_CNTR", REG_MMIO, 0xec1c, &mmRLC_LOAD_BALANCE_CNTR[0], sizeof(mmRLC_LOAD_BALANCE_CNTR)/sizeof(mmRLC_LOAD_BALANCE_CNTR[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG_INST_ADDR", REG_MMIO, 0xec1d, &mmRLC_GPM_DEBUG_INST_ADDR[0], sizeof(mmRLC_GPM_DEBUG_INST_ADDR)/sizeof(mmRLC_GPM_DEBUG_INST_ADDR[0]), 0, 0 },
+	{ "mmRLC_JUMP_TABLE_RESTORE", REG_MMIO, 0xec1e, &mmRLC_JUMP_TABLE_RESTORE[0], sizeof(mmRLC_JUMP_TABLE_RESTORE)/sizeof(mmRLC_JUMP_TABLE_RESTORE[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY_2", REG_MMIO, 0xec1f, &mmRLC_PG_DELAY_2[0], sizeof(mmRLC_PG_DELAY_2)/sizeof(mmRLC_PG_DELAY_2[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG_SELECT", REG_MMIO, 0xec20, &mmRLC_GPM_DEBUG_SELECT[0], sizeof(mmRLC_GPM_DEBUG_SELECT)/sizeof(mmRLC_GPM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG", REG_MMIO, 0xec21, &mmRLC_GPM_DEBUG[0], sizeof(mmRLC_GPM_DEBUG)/sizeof(mmRLC_GPM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG_INST_A", REG_MMIO, 0xec22, &mmRLC_GPM_DEBUG_INST_A[0], sizeof(mmRLC_GPM_DEBUG_INST_A)/sizeof(mmRLC_GPM_DEBUG_INST_A[0]), 0, 0 },
+	{ "mmRLC_GPM_DEBUG_INST_B", REG_MMIO, 0xec23, &mmRLC_GPM_DEBUG_INST_B[0], sizeof(mmRLC_GPM_DEBUG_INST_B)/sizeof(mmRLC_GPM_DEBUG_INST_B[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_LSB", REG_MMIO, 0xec24, &mmRLC_GPU_CLOCK_COUNT_LSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_LSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_LSB[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_COUNT_MSB", REG_MMIO, 0xec25, &mmRLC_GPU_CLOCK_COUNT_MSB[0], sizeof(mmRLC_GPU_CLOCK_COUNT_MSB)/sizeof(mmRLC_GPU_CLOCK_COUNT_MSB[0]), 0, 0 },
+	{ "mmRLC_CAPTURE_GPU_CLOCK_COUNT", REG_MMIO, 0xec26, &mmRLC_CAPTURE_GPU_CLOCK_COUNT[0], sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT)/sizeof(mmRLC_CAPTURE_GPU_CLOCK_COUNT[0]), 0, 0 },
+	{ "mmRLC_UCODE_CNTL", REG_MMIO, 0xec27, &mmRLC_UCODE_CNTL[0], sizeof(mmRLC_UCODE_CNTL)/sizeof(mmRLC_UCODE_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_RESET", REG_MMIO, 0xec28, &mmRLC_GPM_THREAD_RESET[0], sizeof(mmRLC_GPM_THREAD_RESET)/sizeof(mmRLC_GPM_THREAD_RESET[0]), 0, 0 },
+	{ "mmRLC_GPM_STAT", REG_MMIO, 0xec40, &mmRLC_GPM_STAT[0], sizeof(mmRLC_GPM_STAT)/sizeof(mmRLC_GPM_STAT[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32_RES_SEL", REG_MMIO, 0xec41, &mmRLC_GPU_CLOCK_32_RES_SEL[0], sizeof(mmRLC_GPU_CLOCK_32_RES_SEL)/sizeof(mmRLC_GPU_CLOCK_32_RES_SEL[0]), 0, 0 },
+	{ "mmRLC_GPU_CLOCK_32", REG_MMIO, 0xec42, &mmRLC_GPU_CLOCK_32[0], sizeof(mmRLC_GPU_CLOCK_32)/sizeof(mmRLC_GPU_CLOCK_32[0]), 0, 0 },
+	{ "mmRLC_PG_CNTL", REG_MMIO, 0xec43, &mmRLC_PG_CNTL[0], sizeof(mmRLC_PG_CNTL)/sizeof(mmRLC_PG_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_PRIORITY", REG_MMIO, 0xec44, &mmRLC_GPM_THREAD_PRIORITY[0], sizeof(mmRLC_GPM_THREAD_PRIORITY)/sizeof(mmRLC_GPM_THREAD_PRIORITY[0]), 0, 0 },
+	{ "mmRLC_GPM_THREAD_ENABLE", REG_MMIO, 0xec45, &mmRLC_GPM_THREAD_ENABLE[0], sizeof(mmRLC_GPM_THREAD_ENABLE)/sizeof(mmRLC_GPM_THREAD_ENABLE[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD0", REG_MMIO, 0xec46, &mmRLC_GPM_VMID_THREAD0[0], sizeof(mmRLC_GPM_VMID_THREAD0)/sizeof(mmRLC_GPM_VMID_THREAD0[0]), 0, 0 },
+	{ "mmRLC_GPM_VMID_THREAD1", REG_MMIO, 0xec47, &mmRLC_GPM_VMID_THREAD1[0], sizeof(mmRLC_GPM_VMID_THREAD1)/sizeof(mmRLC_GPM_VMID_THREAD1[0]), 0, 0 },
+	{ "mmRLC_CGTT_MGCG_OVERRIDE", REG_MMIO, 0xec48, &mmRLC_CGTT_MGCG_OVERRIDE[0], sizeof(mmRLC_CGTT_MGCG_OVERRIDE)/sizeof(mmRLC_CGTT_MGCG_OVERRIDE[0]), 0, 0 },
+	{ "mmRLC_CGCG_CGLS_CTRL", REG_MMIO, 0xec49, &mmRLC_CGCG_CGLS_CTRL[0], sizeof(mmRLC_CGCG_CGLS_CTRL)/sizeof(mmRLC_CGCG_CGLS_CTRL[0]), 0, 0 },
+	{ "mmRLC_CGCG_RAMP_CTRL", REG_MMIO, 0xec4a, &mmRLC_CGCG_RAMP_CTRL[0], sizeof(mmRLC_CGCG_RAMP_CTRL)/sizeof(mmRLC_CGCG_RAMP_CTRL[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_STATUS", REG_MMIO, 0xec4b, &mmRLC_DYN_PG_STATUS[0], sizeof(mmRLC_DYN_PG_STATUS)/sizeof(mmRLC_DYN_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_DYN_PG_REQUEST", REG_MMIO, 0xec4c, &mmRLC_DYN_PG_REQUEST[0], sizeof(mmRLC_DYN_PG_REQUEST)/sizeof(mmRLC_DYN_PG_REQUEST[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY", REG_MMIO, 0xec4d, &mmRLC_PG_DELAY[0], sizeof(mmRLC_PG_DELAY)/sizeof(mmRLC_PG_DELAY[0]), 0, 0 },
+	{ "mmRLC_CU_STATUS", REG_MMIO, 0xec4e, &mmRLC_CU_STATUS[0], sizeof(mmRLC_CU_STATUS)/sizeof(mmRLC_CU_STATUS[0]), 0, 0 },
+	{ "mmRLC_LB_INIT_CU_MASK", REG_MMIO, 0xec4f, &mmRLC_LB_INIT_CU_MASK[0], sizeof(mmRLC_LB_INIT_CU_MASK)/sizeof(mmRLC_LB_INIT_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_ALWAYS_ACTIVE_CU_MASK", REG_MMIO, 0xec50, &mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0], sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK)/sizeof(mmRLC_LB_ALWAYS_ACTIVE_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_LB_PARAMS", REG_MMIO, 0xec51, &mmRLC_LB_PARAMS[0], sizeof(mmRLC_LB_PARAMS)/sizeof(mmRLC_LB_PARAMS[0]), 0, 0 },
+	{ "mmRLC_THREAD1_DELAY", REG_MMIO, 0xec52, &mmRLC_THREAD1_DELAY[0], sizeof(mmRLC_THREAD1_DELAY)/sizeof(mmRLC_THREAD1_DELAY[0]), 0, 0 },
+	{ "mmRLC_PG_ALWAYS_ON_CU_MASK", REG_MMIO, 0xec53, &mmRLC_PG_ALWAYS_ON_CU_MASK[0], sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK)/sizeof(mmRLC_PG_ALWAYS_ON_CU_MASK[0]), 0, 0 },
+	{ "mmRLC_MAX_PG_CU", REG_MMIO, 0xec54, &mmRLC_MAX_PG_CU[0], sizeof(mmRLC_MAX_PG_CU)/sizeof(mmRLC_MAX_PG_CU[0]), 0, 0 },
+	{ "mmRLC_AUTO_PG_CTRL", REG_MMIO, 0xec55, &mmRLC_AUTO_PG_CTRL[0], sizeof(mmRLC_AUTO_PG_CTRL)/sizeof(mmRLC_AUTO_PG_CTRL[0]), 0, 0 },
+	{ "mmRLC_SMU_GRBM_REG_SAVE_CTRL", REG_MMIO, 0xec56, &mmRLC_SMU_GRBM_REG_SAVE_CTRL[0], sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL)/sizeof(mmRLC_SMU_GRBM_REG_SAVE_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_MASTER_INDEX", REG_MMIO, 0xec59, &mmRLC_SERDES_RD_MASTER_INDEX[0], sizeof(mmRLC_SERDES_RD_MASTER_INDEX)/sizeof(mmRLC_SERDES_RD_MASTER_INDEX[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_0", REG_MMIO, 0xec5a, &mmRLC_SERDES_RD_DATA_0[0], sizeof(mmRLC_SERDES_RD_DATA_0)/sizeof(mmRLC_SERDES_RD_DATA_0[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_1", REG_MMIO, 0xec5b, &mmRLC_SERDES_RD_DATA_1[0], sizeof(mmRLC_SERDES_RD_DATA_1)/sizeof(mmRLC_SERDES_RD_DATA_1[0]), 0, 0 },
+	{ "mmRLC_SERDES_RD_DATA_2", REG_MMIO, 0xec5c, &mmRLC_SERDES_RD_DATA_2[0], sizeof(mmRLC_SERDES_RD_DATA_2)/sizeof(mmRLC_SERDES_RD_DATA_2[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_CU_MASTER_MASK", REG_MMIO, 0xec5d, &mmRLC_SERDES_WR_CU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_CU_MASTER_MASK[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_NONCU_MASTER_MASK", REG_MMIO, 0xec5e, &mmRLC_SERDES_WR_NONCU_MASTER_MASK[0], sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK)/sizeof(mmRLC_SERDES_WR_NONCU_MASTER_MASK[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_CTRL", REG_MMIO, 0xec5f, &mmRLC_SERDES_WR_CTRL[0], sizeof(mmRLC_SERDES_WR_CTRL)/sizeof(mmRLC_SERDES_WR_CTRL[0]), 0, 0 },
+	{ "mmRLC_SERDES_WR_DATA", REG_MMIO, 0xec60, &mmRLC_SERDES_WR_DATA[0], sizeof(mmRLC_SERDES_WR_DATA)/sizeof(mmRLC_SERDES_WR_DATA[0]), 0, 0 },
+	{ "mmRLC_SERDES_CU_MASTER_BUSY", REG_MMIO, 0xec61, &mmRLC_SERDES_CU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_CU_MASTER_BUSY)/sizeof(mmRLC_SERDES_CU_MASTER_BUSY[0]), 0, 0 },
+	{ "mmRLC_SERDES_NONCU_MASTER_BUSY", REG_MMIO, 0xec62, &mmRLC_SERDES_NONCU_MASTER_BUSY[0], sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY)/sizeof(mmRLC_SERDES_NONCU_MASTER_BUSY[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_0", REG_MMIO, 0xec63, &mmRLC_GPM_GENERAL_0[0], sizeof(mmRLC_GPM_GENERAL_0)/sizeof(mmRLC_GPM_GENERAL_0[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_1", REG_MMIO, 0xec64, &mmRLC_GPM_GENERAL_1[0], sizeof(mmRLC_GPM_GENERAL_1)/sizeof(mmRLC_GPM_GENERAL_1[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_2", REG_MMIO, 0xec65, &mmRLC_GPM_GENERAL_2[0], sizeof(mmRLC_GPM_GENERAL_2)/sizeof(mmRLC_GPM_GENERAL_2[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_3", REG_MMIO, 0xec66, &mmRLC_GPM_GENERAL_3[0], sizeof(mmRLC_GPM_GENERAL_3)/sizeof(mmRLC_GPM_GENERAL_3[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_4", REG_MMIO, 0xec67, &mmRLC_GPM_GENERAL_4[0], sizeof(mmRLC_GPM_GENERAL_4)/sizeof(mmRLC_GPM_GENERAL_4[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_5", REG_MMIO, 0xec68, &mmRLC_GPM_GENERAL_5[0], sizeof(mmRLC_GPM_GENERAL_5)/sizeof(mmRLC_GPM_GENERAL_5[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_6", REG_MMIO, 0xec69, &mmRLC_GPM_GENERAL_6[0], sizeof(mmRLC_GPM_GENERAL_6)/sizeof(mmRLC_GPM_GENERAL_6[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_7", REG_MMIO, 0xec6a, &mmRLC_GPM_GENERAL_7[0], sizeof(mmRLC_GPM_GENERAL_7)/sizeof(mmRLC_GPM_GENERAL_7[0]), 0, 0 },
+	{ "mmRLC_GPM_SCRATCH_ADDR", REG_MMIO, 0xec6c, &mmRLC_GPM_SCRATCH_ADDR[0], sizeof(mmRLC_GPM_SCRATCH_ADDR)/sizeof(mmRLC_GPM_SCRATCH_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_SCRATCH_DATA", REG_MMIO, 0xec6d, &mmRLC_GPM_SCRATCH_DATA[0], sizeof(mmRLC_GPM_SCRATCH_DATA)/sizeof(mmRLC_GPM_SCRATCH_DATA[0]), 0, 0 },
+	{ "mmRLC_STATIC_PG_STATUS", REG_MMIO, 0xec6e, &mmRLC_STATIC_PG_STATUS[0], sizeof(mmRLC_STATIC_PG_STATUS)/sizeof(mmRLC_STATIC_PG_STATUS[0]), 0, 0 },
+	{ "mmRLC_GPM_PERF_COUNT_0", REG_MMIO, 0xec6f, &mmRLC_GPM_PERF_COUNT_0[0], sizeof(mmRLC_GPM_PERF_COUNT_0)/sizeof(mmRLC_GPM_PERF_COUNT_0[0]), 0, 0 },
+	{ "mmRLC_GPM_PERF_COUNT_1", REG_MMIO, 0xec70, &mmRLC_GPM_PERF_COUNT_1[0], sizeof(mmRLC_GPM_PERF_COUNT_1)/sizeof(mmRLC_GPM_PERF_COUNT_1[0]), 0, 0 },
+	{ "mmRLC_SPM_VMID", REG_MMIO, 0xec71, &mmRLC_SPM_VMID[0], sizeof(mmRLC_SPM_VMID)/sizeof(mmRLC_SPM_VMID[0]), 0, 0 },
+	{ "mmRLC_SPM_INT_CNTL", REG_MMIO, 0xec72, &mmRLC_SPM_INT_CNTL[0], sizeof(mmRLC_SPM_INT_CNTL)/sizeof(mmRLC_SPM_INT_CNTL[0]), 0, 0 },
+	{ "mmRLC_SPM_INT_STATUS", REG_MMIO, 0xec73, &mmRLC_SPM_INT_STATUS[0], sizeof(mmRLC_SPM_INT_STATUS)/sizeof(mmRLC_SPM_INT_STATUS[0]), 0, 0 },
+	{ "mmRLC_SPM_DEBUG_SELECT", REG_MMIO, 0xec74, &mmRLC_SPM_DEBUG_SELECT[0], sizeof(mmRLC_SPM_DEBUG_SELECT)/sizeof(mmRLC_SPM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_SPM_DEBUG", REG_MMIO, 0xec75, &mmRLC_SPM_DEBUG[0], sizeof(mmRLC_SPM_DEBUG)/sizeof(mmRLC_SPM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_SMU_MESSAGE", REG_MMIO, 0xec76, &mmRLC_SMU_MESSAGE[0], sizeof(mmRLC_SMU_MESSAGE)/sizeof(mmRLC_SMU_MESSAGE[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_SIZE", REG_MMIO, 0xec77, &mmRLC_GPM_LOG_SIZE[0], sizeof(mmRLC_GPM_LOG_SIZE)/sizeof(mmRLC_GPM_LOG_SIZE[0]), 0, 0 },
+	{ "mmRLC_PG_DELAY_3", REG_MMIO, 0xec78, &mmRLC_PG_DELAY_3[0], sizeof(mmRLC_PG_DELAY_3)/sizeof(mmRLC_PG_DELAY_3[0]), 0, 0 },
+	{ "mmRLC_GPR_REG1", REG_MMIO, 0xec79, &mmRLC_GPR_REG1[0], sizeof(mmRLC_GPR_REG1)/sizeof(mmRLC_GPR_REG1[0]), 0, 0 },
+	{ "mmRLC_GPR_REG2", REG_MMIO, 0xec7a, &mmRLC_GPR_REG2[0], sizeof(mmRLC_GPR_REG2)/sizeof(mmRLC_GPR_REG2[0]), 0, 0 },
+	{ "mmRLC_GPM_LOG_CONT", REG_MMIO, 0xec7b, &mmRLC_GPM_LOG_CONT[0], sizeof(mmRLC_GPM_LOG_CONT)/sizeof(mmRLC_GPM_LOG_CONT[0]), 0, 0 },
+	{ "mmRLC_GPM_INT_DISABLE_TH0", REG_MMIO, 0xec7c, &mmRLC_GPM_INT_DISABLE_TH0[0], sizeof(mmRLC_GPM_INT_DISABLE_TH0)/sizeof(mmRLC_GPM_INT_DISABLE_TH0[0]), 0, 0 },
+	{ "mmRLC_GPM_INT_DISABLE_TH1", REG_MMIO, 0xec7d, &mmRLC_GPM_INT_DISABLE_TH1[0], sizeof(mmRLC_GPM_INT_DISABLE_TH1)/sizeof(mmRLC_GPM_INT_DISABLE_TH1[0]), 0, 0 },
+	{ "mmRLC_GPM_INT_FORCE_TH0", REG_MMIO, 0xec7e, &mmRLC_GPM_INT_FORCE_TH0[0], sizeof(mmRLC_GPM_INT_FORCE_TH0)/sizeof(mmRLC_GPM_INT_FORCE_TH0[0]), 0, 0 },
+	{ "mmRLC_GPM_INT_FORCE_TH1", REG_MMIO, 0xec7f, &mmRLC_GPM_INT_FORCE_TH1[0], sizeof(mmRLC_GPM_INT_FORCE_TH1)/sizeof(mmRLC_GPM_INT_FORCE_TH1[0]), 0, 0 },
+	{ "mmRLC_SRM_CNTL", REG_MMIO, 0xec80, &mmRLC_SRM_CNTL[0], sizeof(mmRLC_SRM_CNTL)/sizeof(mmRLC_SRM_CNTL[0]), 0, 0 },
+	{ "mmRLC_SRM_DEBUG_SELECT", REG_MMIO, 0xec81, &mmRLC_SRM_DEBUG_SELECT[0], sizeof(mmRLC_SRM_DEBUG_SELECT)/sizeof(mmRLC_SRM_DEBUG_SELECT[0]), 0, 0 },
+	{ "mmRLC_SRM_DEBUG", REG_MMIO, 0xec82, &mmRLC_SRM_DEBUG[0], sizeof(mmRLC_SRM_DEBUG)/sizeof(mmRLC_SRM_DEBUG[0]), 0, 0 },
+	{ "mmRLC_SRM_ARAM_ADDR", REG_MMIO, 0xec83, &mmRLC_SRM_ARAM_ADDR[0], sizeof(mmRLC_SRM_ARAM_ADDR)/sizeof(mmRLC_SRM_ARAM_ADDR[0]), 0, 0 },
+	{ "mmRLC_SRM_ARAM_DATA", REG_MMIO, 0xec84, &mmRLC_SRM_ARAM_DATA[0], sizeof(mmRLC_SRM_ARAM_DATA)/sizeof(mmRLC_SRM_ARAM_DATA[0]), 0, 0 },
+	{ "mmRLC_SRM_DRAM_ADDR", REG_MMIO, 0xec85, &mmRLC_SRM_DRAM_ADDR[0], sizeof(mmRLC_SRM_DRAM_ADDR)/sizeof(mmRLC_SRM_DRAM_ADDR[0]), 0, 0 },
+	{ "mmRLC_SRM_DRAM_DATA", REG_MMIO, 0xec86, &mmRLC_SRM_DRAM_DATA[0], sizeof(mmRLC_SRM_DRAM_DATA)/sizeof(mmRLC_SRM_DRAM_DATA[0]), 0, 0 },
+	{ "mmRLC_SRM_GPM_COMMAND", REG_MMIO, 0xec87, &mmRLC_SRM_GPM_COMMAND[0], sizeof(mmRLC_SRM_GPM_COMMAND)/sizeof(mmRLC_SRM_GPM_COMMAND[0]), 0, 0 },
+	{ "mmRLC_SRM_GPM_COMMAND_STATUS", REG_MMIO, 0xec88, &mmRLC_SRM_GPM_COMMAND_STATUS[0], sizeof(mmRLC_SRM_GPM_COMMAND_STATUS)/sizeof(mmRLC_SRM_GPM_COMMAND_STATUS[0]), 0, 0 },
+	{ "mmRLC_SRM_RLCV_COMMAND", REG_MMIO, 0xec89, &mmRLC_SRM_RLCV_COMMAND[0], sizeof(mmRLC_SRM_RLCV_COMMAND)/sizeof(mmRLC_SRM_RLCV_COMMAND[0]), 0, 0 },
+	{ "mmRLC_SRM_RLCV_COMMAND_STATUS", REG_MMIO, 0xec8a, &mmRLC_SRM_RLCV_COMMAND_STATUS[0], sizeof(mmRLC_SRM_RLCV_COMMAND_STATUS)/sizeof(mmRLC_SRM_RLCV_COMMAND_STATUS[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_0", REG_MMIO, 0xec8b, &mmRLC_SRM_INDEX_CNTL_ADDR_0[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_0)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_0[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_1", REG_MMIO, 0xec8c, &mmRLC_SRM_INDEX_CNTL_ADDR_1[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_1)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_1[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_2", REG_MMIO, 0xec8d, &mmRLC_SRM_INDEX_CNTL_ADDR_2[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_2)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_2[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_3", REG_MMIO, 0xec8e, &mmRLC_SRM_INDEX_CNTL_ADDR_3[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_3)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_3[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_4", REG_MMIO, 0xec8f, &mmRLC_SRM_INDEX_CNTL_ADDR_4[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_4)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_4[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_5", REG_MMIO, 0xec90, &mmRLC_SRM_INDEX_CNTL_ADDR_5[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_5)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_5[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_6", REG_MMIO, 0xec91, &mmRLC_SRM_INDEX_CNTL_ADDR_6[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_6)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_6[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_ADDR_7", REG_MMIO, 0xec92, &mmRLC_SRM_INDEX_CNTL_ADDR_7[0], sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_7)/sizeof(mmRLC_SRM_INDEX_CNTL_ADDR_7[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_0", REG_MMIO, 0xec93, &mmRLC_SRM_INDEX_CNTL_DATA_0[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_0)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_0[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_1", REG_MMIO, 0xec94, &mmRLC_SRM_INDEX_CNTL_DATA_1[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_1)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_1[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_2", REG_MMIO, 0xec95, &mmRLC_SRM_INDEX_CNTL_DATA_2[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_2)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_2[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_3", REG_MMIO, 0xec96, &mmRLC_SRM_INDEX_CNTL_DATA_3[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_3)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_3[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_4", REG_MMIO, 0xec97, &mmRLC_SRM_INDEX_CNTL_DATA_4[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_4)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_4[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_5", REG_MMIO, 0xec98, &mmRLC_SRM_INDEX_CNTL_DATA_5[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_5)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_5[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_6", REG_MMIO, 0xec99, &mmRLC_SRM_INDEX_CNTL_DATA_6[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_6)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_6[0]), 0, 0 },
+	{ "mmRLC_SRM_INDEX_CNTL_DATA_7", REG_MMIO, 0xec9a, &mmRLC_SRM_INDEX_CNTL_DATA_7[0], sizeof(mmRLC_SRM_INDEX_CNTL_DATA_7)/sizeof(mmRLC_SRM_INDEX_CNTL_DATA_7[0]), 0, 0 },
+	{ "mmRLC_SRM_STAT", REG_MMIO, 0xec9b, &mmRLC_SRM_STAT[0], sizeof(mmRLC_SRM_STAT)/sizeof(mmRLC_SRM_STAT[0]), 0, 0 },
+	{ "mmRLC_SRM_GPM_ABORT", REG_MMIO, 0xec9c, &mmRLC_SRM_GPM_ABORT[0], sizeof(mmRLC_SRM_GPM_ABORT)/sizeof(mmRLC_SRM_GPM_ABORT[0]), 0, 0 },
+	{ "mmRLC_CSIB_ADDR_LO", REG_MMIO, 0xeca2, &mmRLC_CSIB_ADDR_LO[0], sizeof(mmRLC_CSIB_ADDR_LO)/sizeof(mmRLC_CSIB_ADDR_LO[0]), 0, 0 },
+	{ "mmRLC_CSIB_ADDR_HI", REG_MMIO, 0xeca3, &mmRLC_CSIB_ADDR_HI[0], sizeof(mmRLC_CSIB_ADDR_HI)/sizeof(mmRLC_CSIB_ADDR_HI[0]), 0, 0 },
+	{ "mmRLC_CSIB_LENGTH", REG_MMIO, 0xeca4, &mmRLC_CSIB_LENGTH[0], sizeof(mmRLC_CSIB_LENGTH)/sizeof(mmRLC_CSIB_LENGTH[0]), 0, 0 },
+	{ "mmRLC_CP_RESPONSE0", REG_MMIO, 0xeca5, &mmRLC_CP_RESPONSE0[0], sizeof(mmRLC_CP_RESPONSE0)/sizeof(mmRLC_CP_RESPONSE0[0]), 0, 0 },
+	{ "mmRLC_CP_RESPONSE1", REG_MMIO, 0xeca6, &mmRLC_CP_RESPONSE1[0], sizeof(mmRLC_CP_RESPONSE1)/sizeof(mmRLC_CP_RESPONSE1[0]), 0, 0 },
+	{ "mmRLC_CP_RESPONSE2", REG_MMIO, 0xeca7, &mmRLC_CP_RESPONSE2[0], sizeof(mmRLC_CP_RESPONSE2)/sizeof(mmRLC_CP_RESPONSE2[0]), 0, 0 },
+	{ "mmRLC_CP_RESPONSE3", REG_MMIO, 0xeca8, &mmRLC_CP_RESPONSE3[0], sizeof(mmRLC_CP_RESPONSE3)/sizeof(mmRLC_CP_RESPONSE3[0]), 0, 0 },
+	{ "mmRLC_SMU_COMMAND", REG_MMIO, 0xeca9, &mmRLC_SMU_COMMAND[0], sizeof(mmRLC_SMU_COMMAND)/sizeof(mmRLC_SMU_COMMAND[0]), 0, 0 },
+	{ "mmRLC_CP_SCHEDULERS", REG_MMIO, 0xecaa, &mmRLC_CP_SCHEDULERS[0], sizeof(mmRLC_CP_SCHEDULERS)/sizeof(mmRLC_CP_SCHEDULERS[0]), 0, 0 },
+	{ "mmRLC_SMU_ARGUMENT_1", REG_MMIO, 0xecab, &mmRLC_SMU_ARGUMENT_1[0], sizeof(mmRLC_SMU_ARGUMENT_1)/sizeof(mmRLC_SMU_ARGUMENT_1[0]), 0, 0 },
+	{ "mmRLC_SMU_ARGUMENT_2", REG_MMIO, 0xecac, &mmRLC_SMU_ARGUMENT_2[0], sizeof(mmRLC_SMU_ARGUMENT_2)/sizeof(mmRLC_SMU_ARGUMENT_2[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_8", REG_MMIO, 0xecad, &mmRLC_GPM_GENERAL_8[0], sizeof(mmRLC_GPM_GENERAL_8)/sizeof(mmRLC_GPM_GENERAL_8[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_9", REG_MMIO, 0xecae, &mmRLC_GPM_GENERAL_9[0], sizeof(mmRLC_GPM_GENERAL_9)/sizeof(mmRLC_GPM_GENERAL_9[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_10", REG_MMIO, 0xecaf, &mmRLC_GPM_GENERAL_10[0], sizeof(mmRLC_GPM_GENERAL_10)/sizeof(mmRLC_GPM_GENERAL_10[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_11", REG_MMIO, 0xecb0, &mmRLC_GPM_GENERAL_11[0], sizeof(mmRLC_GPM_GENERAL_11)/sizeof(mmRLC_GPM_GENERAL_11[0]), 0, 0 },
+	{ "mmRLC_GPM_GENERAL_12", REG_MMIO, 0xecb1, &mmRLC_GPM_GENERAL_12[0], sizeof(mmRLC_GPM_GENERAL_12)/sizeof(mmRLC_GPM_GENERAL_12[0]), 0, 0 },
+	{ "ixCLIPPER_DEBUG_REG15", REG_SMC, 0xf, &ixCLIPPER_DEBUG_REG15[0], sizeof(ixCLIPPER_DEBUG_REG15)/sizeof(ixCLIPPER_DEBUG_REG15[0]), 0, 0 },
+	{ "ixVGT_DEBUG_REG15", REG_SMC, 0xf, &ixVGT_DEBUG_REG15[0], sizeof(ixVGT_DEBUG_REG15)/sizeof(ixVGT_DEBUG_REG15[0]), 0, 0 },
+	{ "mmCGTS_SM_CTRL_REG", REG_MMIO, 0xf000, &mmCGTS_SM_CTRL_REG[0], sizeof(mmCGTS_SM_CTRL_REG)/sizeof(mmCGTS_SM_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_CTRL_REG", REG_MMIO, 0xf001, &mmCGTS_RD_CTRL_REG[0], sizeof(mmCGTS_RD_CTRL_REG)/sizeof(mmCGTS_RD_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_RD_REG", REG_MMIO, 0xf002, &mmCGTS_RD_REG[0], sizeof(mmCGTS_RD_REG)/sizeof(mmCGTS_RD_REG[0]), 0, 0 },
+	{ "mmCGTS_TCC_DISABLE", REG_MMIO, 0xf003, &mmCGTS_TCC_DISABLE[0], sizeof(mmCGTS_TCC_DISABLE)/sizeof(mmCGTS_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_USER_TCC_DISABLE", REG_MMIO, 0xf004, &mmCGTS_USER_TCC_DISABLE[0], sizeof(mmCGTS_USER_TCC_DISABLE)/sizeof(mmCGTS_USER_TCC_DISABLE[0]), 0, 0 },
+	{ "mmCGTS_CU0_SP0_CTRL_REG", REG_MMIO, 0xf008, &mmCGTS_CU0_SP0_CTRL_REG[0], sizeof(mmCGTS_CU0_SP0_CTRL_REG)/sizeof(mmCGTS_CU0_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_LDS_SQ_CTRL_REG", REG_MMIO, 0xf009, &mmCGTS_CU0_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU0_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_TA_SQC_CTRL_REG", REG_MMIO, 0xf00a, &mmCGTS_CU0_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU0_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_SP1_CTRL_REG", REG_MMIO, 0xf00b, &mmCGTS_CU0_SP1_CTRL_REG[0], sizeof(mmCGTS_CU0_SP1_CTRL_REG)/sizeof(mmCGTS_CU0_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU0_TD_TCP_CTRL_REG", REG_MMIO, 0xf00c, &mmCGTS_CU0_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU0_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_SP0_CTRL_REG", REG_MMIO, 0xf00d, &mmCGTS_CU1_SP0_CTRL_REG[0], sizeof(mmCGTS_CU1_SP0_CTRL_REG)/sizeof(mmCGTS_CU1_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_LDS_SQ_CTRL_REG", REG_MMIO, 0xf00e, &mmCGTS_CU1_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU1_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_TA_CTRL_REG", REG_MMIO, 0xf00f, &mmCGTS_CU1_TA_CTRL_REG[0], sizeof(mmCGTS_CU1_TA_CTRL_REG)/sizeof(mmCGTS_CU1_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_SP1_CTRL_REG", REG_MMIO, 0xf010, &mmCGTS_CU1_SP1_CTRL_REG[0], sizeof(mmCGTS_CU1_SP1_CTRL_REG)/sizeof(mmCGTS_CU1_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU1_TD_TCP_CTRL_REG", REG_MMIO, 0xf011, &mmCGTS_CU1_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU1_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_SP0_CTRL_REG", REG_MMIO, 0xf012, &mmCGTS_CU2_SP0_CTRL_REG[0], sizeof(mmCGTS_CU2_SP0_CTRL_REG)/sizeof(mmCGTS_CU2_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_LDS_SQ_CTRL_REG", REG_MMIO, 0xf013, &mmCGTS_CU2_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU2_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_TA_CTRL_REG", REG_MMIO, 0xf014, &mmCGTS_CU2_TA_CTRL_REG[0], sizeof(mmCGTS_CU2_TA_CTRL_REG)/sizeof(mmCGTS_CU2_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_SP1_CTRL_REG", REG_MMIO, 0xf015, &mmCGTS_CU2_SP1_CTRL_REG[0], sizeof(mmCGTS_CU2_SP1_CTRL_REG)/sizeof(mmCGTS_CU2_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU2_TD_TCP_CTRL_REG", REG_MMIO, 0xf016, &mmCGTS_CU2_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU2_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_SP0_CTRL_REG", REG_MMIO, 0xf017, &mmCGTS_CU3_SP0_CTRL_REG[0], sizeof(mmCGTS_CU3_SP0_CTRL_REG)/sizeof(mmCGTS_CU3_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_LDS_SQ_CTRL_REG", REG_MMIO, 0xf018, &mmCGTS_CU3_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU3_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_TA_CTRL_REG", REG_MMIO, 0xf019, &mmCGTS_CU3_TA_CTRL_REG[0], sizeof(mmCGTS_CU3_TA_CTRL_REG)/sizeof(mmCGTS_CU3_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_SP1_CTRL_REG", REG_MMIO, 0xf01a, &mmCGTS_CU3_SP1_CTRL_REG[0], sizeof(mmCGTS_CU3_SP1_CTRL_REG)/sizeof(mmCGTS_CU3_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU3_TD_TCP_CTRL_REG", REG_MMIO, 0xf01b, &mmCGTS_CU3_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU3_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_SP0_CTRL_REG", REG_MMIO, 0xf01c, &mmCGTS_CU4_SP0_CTRL_REG[0], sizeof(mmCGTS_CU4_SP0_CTRL_REG)/sizeof(mmCGTS_CU4_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_LDS_SQ_CTRL_REG", REG_MMIO, 0xf01d, &mmCGTS_CU4_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU4_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_TA_SQC_CTRL_REG", REG_MMIO, 0xf01e, &mmCGTS_CU4_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU4_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_SP1_CTRL_REG", REG_MMIO, 0xf01f, &mmCGTS_CU4_SP1_CTRL_REG[0], sizeof(mmCGTS_CU4_SP1_CTRL_REG)/sizeof(mmCGTS_CU4_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU4_TD_TCP_CTRL_REG", REG_MMIO, 0xf020, &mmCGTS_CU4_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU4_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_SP0_CTRL_REG", REG_MMIO, 0xf021, &mmCGTS_CU5_SP0_CTRL_REG[0], sizeof(mmCGTS_CU5_SP0_CTRL_REG)/sizeof(mmCGTS_CU5_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_LDS_SQ_CTRL_REG", REG_MMIO, 0xf022, &mmCGTS_CU5_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU5_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_TA_CTRL_REG", REG_MMIO, 0xf023, &mmCGTS_CU5_TA_CTRL_REG[0], sizeof(mmCGTS_CU5_TA_CTRL_REG)/sizeof(mmCGTS_CU5_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_SP1_CTRL_REG", REG_MMIO, 0xf024, &mmCGTS_CU5_SP1_CTRL_REG[0], sizeof(mmCGTS_CU5_SP1_CTRL_REG)/sizeof(mmCGTS_CU5_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU5_TD_TCP_CTRL_REG", REG_MMIO, 0xf025, &mmCGTS_CU5_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU5_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_SP0_CTRL_REG", REG_MMIO, 0xf026, &mmCGTS_CU6_SP0_CTRL_REG[0], sizeof(mmCGTS_CU6_SP0_CTRL_REG)/sizeof(mmCGTS_CU6_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_LDS_SQ_CTRL_REG", REG_MMIO, 0xf027, &mmCGTS_CU6_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU6_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_TA_CTRL_REG", REG_MMIO, 0xf028, &mmCGTS_CU6_TA_CTRL_REG[0], sizeof(mmCGTS_CU6_TA_CTRL_REG)/sizeof(mmCGTS_CU6_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_SP1_CTRL_REG", REG_MMIO, 0xf029, &mmCGTS_CU6_SP1_CTRL_REG[0], sizeof(mmCGTS_CU6_SP1_CTRL_REG)/sizeof(mmCGTS_CU6_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU6_TD_TCP_CTRL_REG", REG_MMIO, 0xf02a, &mmCGTS_CU6_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU6_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_SP0_CTRL_REG", REG_MMIO, 0xf02b, &mmCGTS_CU7_SP0_CTRL_REG[0], sizeof(mmCGTS_CU7_SP0_CTRL_REG)/sizeof(mmCGTS_CU7_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_LDS_SQ_CTRL_REG", REG_MMIO, 0xf02c, &mmCGTS_CU7_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU7_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_TA_CTRL_REG", REG_MMIO, 0xf02d, &mmCGTS_CU7_TA_CTRL_REG[0], sizeof(mmCGTS_CU7_TA_CTRL_REG)/sizeof(mmCGTS_CU7_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_SP1_CTRL_REG", REG_MMIO, 0xf02e, &mmCGTS_CU7_SP1_CTRL_REG[0], sizeof(mmCGTS_CU7_SP1_CTRL_REG)/sizeof(mmCGTS_CU7_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU7_TD_TCP_CTRL_REG", REG_MMIO, 0xf02f, &mmCGTS_CU7_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU7_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_SP0_CTRL_REG", REG_MMIO, 0xf030, &mmCGTS_CU8_SP0_CTRL_REG[0], sizeof(mmCGTS_CU8_SP0_CTRL_REG)/sizeof(mmCGTS_CU8_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_LDS_SQ_CTRL_REG", REG_MMIO, 0xf031, &mmCGTS_CU8_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU8_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_TA_SQC_CTRL_REG", REG_MMIO, 0xf032, &mmCGTS_CU8_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU8_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_SP1_CTRL_REG", REG_MMIO, 0xf033, &mmCGTS_CU8_SP1_CTRL_REG[0], sizeof(mmCGTS_CU8_SP1_CTRL_REG)/sizeof(mmCGTS_CU8_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU8_TD_TCP_CTRL_REG", REG_MMIO, 0xf034, &mmCGTS_CU8_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU8_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_SP0_CTRL_REG", REG_MMIO, 0xf035, &mmCGTS_CU9_SP0_CTRL_REG[0], sizeof(mmCGTS_CU9_SP0_CTRL_REG)/sizeof(mmCGTS_CU9_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_LDS_SQ_CTRL_REG", REG_MMIO, 0xf036, &mmCGTS_CU9_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU9_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_TA_CTRL_REG", REG_MMIO, 0xf037, &mmCGTS_CU9_TA_CTRL_REG[0], sizeof(mmCGTS_CU9_TA_CTRL_REG)/sizeof(mmCGTS_CU9_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_SP1_CTRL_REG", REG_MMIO, 0xf038, &mmCGTS_CU9_SP1_CTRL_REG[0], sizeof(mmCGTS_CU9_SP1_CTRL_REG)/sizeof(mmCGTS_CU9_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU9_TD_TCP_CTRL_REG", REG_MMIO, 0xf039, &mmCGTS_CU9_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU9_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_SP0_CTRL_REG", REG_MMIO, 0xf03a, &mmCGTS_CU10_SP0_CTRL_REG[0], sizeof(mmCGTS_CU10_SP0_CTRL_REG)/sizeof(mmCGTS_CU10_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_LDS_SQ_CTRL_REG", REG_MMIO, 0xf03b, &mmCGTS_CU10_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU10_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_TA_CTRL_REG", REG_MMIO, 0xf03c, &mmCGTS_CU10_TA_CTRL_REG[0], sizeof(mmCGTS_CU10_TA_CTRL_REG)/sizeof(mmCGTS_CU10_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_SP1_CTRL_REG", REG_MMIO, 0xf03d, &mmCGTS_CU10_SP1_CTRL_REG[0], sizeof(mmCGTS_CU10_SP1_CTRL_REG)/sizeof(mmCGTS_CU10_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU10_TD_TCP_CTRL_REG", REG_MMIO, 0xf03e, &mmCGTS_CU10_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU10_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_SP0_CTRL_REG", REG_MMIO, 0xf03f, &mmCGTS_CU11_SP0_CTRL_REG[0], sizeof(mmCGTS_CU11_SP0_CTRL_REG)/sizeof(mmCGTS_CU11_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_LDS_SQ_CTRL_REG", REG_MMIO, 0xf040, &mmCGTS_CU11_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU11_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_TA_CTRL_REG", REG_MMIO, 0xf041, &mmCGTS_CU11_TA_CTRL_REG[0], sizeof(mmCGTS_CU11_TA_CTRL_REG)/sizeof(mmCGTS_CU11_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_SP1_CTRL_REG", REG_MMIO, 0xf042, &mmCGTS_CU11_SP1_CTRL_REG[0], sizeof(mmCGTS_CU11_SP1_CTRL_REG)/sizeof(mmCGTS_CU11_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU11_TD_TCP_CTRL_REG", REG_MMIO, 0xf043, &mmCGTS_CU11_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU11_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_SP0_CTRL_REG", REG_MMIO, 0xf044, &mmCGTS_CU12_SP0_CTRL_REG[0], sizeof(mmCGTS_CU12_SP0_CTRL_REG)/sizeof(mmCGTS_CU12_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_LDS_SQ_CTRL_REG", REG_MMIO, 0xf045, &mmCGTS_CU12_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU12_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_TA_SQC_CTRL_REG", REG_MMIO, 0xf046, &mmCGTS_CU12_TA_SQC_CTRL_REG[0], sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG)/sizeof(mmCGTS_CU12_TA_SQC_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_SP1_CTRL_REG", REG_MMIO, 0xf047, &mmCGTS_CU12_SP1_CTRL_REG[0], sizeof(mmCGTS_CU12_SP1_CTRL_REG)/sizeof(mmCGTS_CU12_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU12_TD_TCP_CTRL_REG", REG_MMIO, 0xf048, &mmCGTS_CU12_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU12_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_SP0_CTRL_REG", REG_MMIO, 0xf049, &mmCGTS_CU13_SP0_CTRL_REG[0], sizeof(mmCGTS_CU13_SP0_CTRL_REG)/sizeof(mmCGTS_CU13_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04a, &mmCGTS_CU13_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU13_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_TA_CTRL_REG", REG_MMIO, 0xf04b, &mmCGTS_CU13_TA_CTRL_REG[0], sizeof(mmCGTS_CU13_TA_CTRL_REG)/sizeof(mmCGTS_CU13_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_SP1_CTRL_REG", REG_MMIO, 0xf04c, &mmCGTS_CU13_SP1_CTRL_REG[0], sizeof(mmCGTS_CU13_SP1_CTRL_REG)/sizeof(mmCGTS_CU13_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU13_TD_TCP_CTRL_REG", REG_MMIO, 0xf04d, &mmCGTS_CU13_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU13_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_SP0_CTRL_REG", REG_MMIO, 0xf04e, &mmCGTS_CU14_SP0_CTRL_REG[0], sizeof(mmCGTS_CU14_SP0_CTRL_REG)/sizeof(mmCGTS_CU14_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_LDS_SQ_CTRL_REG", REG_MMIO, 0xf04f, &mmCGTS_CU14_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU14_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_TA_CTRL_REG", REG_MMIO, 0xf050, &mmCGTS_CU14_TA_CTRL_REG[0], sizeof(mmCGTS_CU14_TA_CTRL_REG)/sizeof(mmCGTS_CU14_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_SP1_CTRL_REG", REG_MMIO, 0xf051, &mmCGTS_CU14_SP1_CTRL_REG[0], sizeof(mmCGTS_CU14_SP1_CTRL_REG)/sizeof(mmCGTS_CU14_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU14_TD_TCP_CTRL_REG", REG_MMIO, 0xf052, &mmCGTS_CU14_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU14_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_SP0_CTRL_REG", REG_MMIO, 0xf053, &mmCGTS_CU15_SP0_CTRL_REG[0], sizeof(mmCGTS_CU15_SP0_CTRL_REG)/sizeof(mmCGTS_CU15_SP0_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_LDS_SQ_CTRL_REG", REG_MMIO, 0xf054, &mmCGTS_CU15_LDS_SQ_CTRL_REG[0], sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG)/sizeof(mmCGTS_CU15_LDS_SQ_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_TA_CTRL_REG", REG_MMIO, 0xf055, &mmCGTS_CU15_TA_CTRL_REG[0], sizeof(mmCGTS_CU15_TA_CTRL_REG)/sizeof(mmCGTS_CU15_TA_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_SP1_CTRL_REG", REG_MMIO, 0xf056, &mmCGTS_CU15_SP1_CTRL_REG[0], sizeof(mmCGTS_CU15_SP1_CTRL_REG)/sizeof(mmCGTS_CU15_SP1_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTS_CU15_TD_TCP_CTRL_REG", REG_MMIO, 0xf057, &mmCGTS_CU15_TD_TCP_CTRL_REG[0], sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG)/sizeof(mmCGTS_CU15_TD_TCP_CTRL_REG[0]), 0, 0 },
+	{ "mmCGTT_SPI_CLK_CTRL", REG_MMIO, 0xf080, &mmCGTT_SPI_CLK_CTRL[0], sizeof(mmCGTT_SPI_CLK_CTRL)/sizeof(mmCGTT_SPI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_PC_CLK_CTRL", REG_MMIO, 0xf081, &mmCGTT_PC_CLK_CTRL[0], sizeof(mmCGTT_PC_CLK_CTRL)/sizeof(mmCGTT_PC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_BCI_CLK_CTRL", REG_MMIO, 0xf082, &mmCGTT_BCI_CLK_CTRL[0], sizeof(mmCGTT_BCI_CLK_CTRL)/sizeof(mmCGTT_BCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_VGT_CLK_CTRL", REG_MMIO, 0xf084, &mmCGTT_VGT_CLK_CTRL[0], sizeof(mmCGTT_VGT_CLK_CTRL)/sizeof(mmCGTT_VGT_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_IA_CLK_CTRL", REG_MMIO, 0xf085, &mmCGTT_IA_CLK_CTRL[0], sizeof(mmCGTT_IA_CLK_CTRL)/sizeof(mmCGTT_IA_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_WD_CLK_CTRL", REG_MMIO, 0xf086, &mmCGTT_WD_CLK_CTRL[0], sizeof(mmCGTT_WD_CLK_CTRL)/sizeof(mmCGTT_WD_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_PA_CLK_CTRL", REG_MMIO, 0xf088, &mmCGTT_PA_CLK_CTRL[0], sizeof(mmCGTT_PA_CLK_CTRL)/sizeof(mmCGTT_PA_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SC_CLK_CTRL", REG_MMIO, 0xf089, &mmCGTT_SC_CLK_CTRL[0], sizeof(mmCGTT_SC_CLK_CTRL)/sizeof(mmCGTT_SC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQ_CLK_CTRL", REG_MMIO, 0xf08c, &mmCGTT_SQ_CLK_CTRL[0], sizeof(mmCGTT_SQ_CLK_CTRL)/sizeof(mmCGTT_SQ_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_SQG_CLK_CTRL", REG_MMIO, 0xf08d, &mmCGTT_SQG_CLK_CTRL[0], sizeof(mmCGTT_SQG_CLK_CTRL)/sizeof(mmCGTT_SQG_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_ALU_CLK_CTRL", REG_MMIO, 0xf08e, &mmSQ_ALU_CLK_CTRL[0], sizeof(mmSQ_ALU_CLK_CTRL)/sizeof(mmSQ_ALU_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_TEX_CLK_CTRL", REG_MMIO, 0xf08f, &mmSQ_TEX_CLK_CTRL[0], sizeof(mmSQ_TEX_CLK_CTRL)/sizeof(mmSQ_TEX_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_LDS_CLK_CTRL", REG_MMIO, 0xf090, &mmSQ_LDS_CLK_CTRL[0], sizeof(mmSQ_LDS_CLK_CTRL)/sizeof(mmSQ_LDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE", REG_MMIO, 0xf091, &mmSQ_POWER_THROTTLE[0], sizeof(mmSQ_POWER_THROTTLE)/sizeof(mmSQ_POWER_THROTTLE[0]), 0, 0 },
+	{ "mmSQ_POWER_THROTTLE2", REG_MMIO, 0xf092, &mmSQ_POWER_THROTTLE2[0], sizeof(mmSQ_POWER_THROTTLE2)/sizeof(mmSQ_POWER_THROTTLE2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL0", REG_MMIO, 0xf094, &mmCGTT_SX_CLK_CTRL0[0], sizeof(mmCGTT_SX_CLK_CTRL0)/sizeof(mmCGTT_SX_CLK_CTRL0[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL1", REG_MMIO, 0xf095, &mmCGTT_SX_CLK_CTRL1[0], sizeof(mmCGTT_SX_CLK_CTRL1)/sizeof(mmCGTT_SX_CLK_CTRL1[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL2", REG_MMIO, 0xf096, &mmCGTT_SX_CLK_CTRL2[0], sizeof(mmCGTT_SX_CLK_CTRL2)/sizeof(mmCGTT_SX_CLK_CTRL2[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL3", REG_MMIO, 0xf097, &mmCGTT_SX_CLK_CTRL3[0], sizeof(mmCGTT_SX_CLK_CTRL3)/sizeof(mmCGTT_SX_CLK_CTRL3[0]), 0, 0 },
+	{ "mmCGTT_SX_CLK_CTRL4", REG_MMIO, 0xf098, &mmCGTT_SX_CLK_CTRL4[0], sizeof(mmCGTT_SX_CLK_CTRL4)/sizeof(mmCGTT_SX_CLK_CTRL4[0]), 0, 0 },
+	{ "mmTD_CGTT_CTRL", REG_MMIO, 0xf09c, &mmTD_CGTT_CTRL[0], sizeof(mmTD_CGTT_CTRL)/sizeof(mmTD_CGTT_CTRL[0]), 0, 0 },
+	{ "mmTA_CGTT_CTRL", REG_MMIO, 0xf09d, &mmTA_CGTT_CTRL[0], sizeof(mmTA_CGTT_CTRL)/sizeof(mmTA_CGTT_CTRL[0]), 0, 0 },
+	{ "mmCGTT_TCP_CLK_CTRL", REG_MMIO, 0xf09e, &mmCGTT_TCP_CLK_CTRL[0], sizeof(mmCGTT_TCP_CLK_CTRL)/sizeof(mmCGTT_TCP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_TCI_CLK_CTRL", REG_MMIO, 0xf09f, &mmCGTT_TCI_CLK_CTRL[0], sizeof(mmCGTT_TCI_CLK_CTRL)/sizeof(mmCGTT_TCI_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_GDS_CLK_CTRL", REG_MMIO, 0xf0a0, &mmCGTT_GDS_CLK_CTRL[0], sizeof(mmCGTT_GDS_CLK_CTRL)/sizeof(mmCGTT_GDS_CLK_CTRL[0]), 0, 0 },
+	{ "mmDB_CGTT_CLK_CTRL_0", REG_MMIO, 0xf0a4, &mmDB_CGTT_CLK_CTRL_0[0], sizeof(mmDB_CGTT_CLK_CTRL_0)/sizeof(mmDB_CGTT_CLK_CTRL_0[0]), 0, 0 },
+	{ "mmCB_CGTT_SCLK_CTRL", REG_MMIO, 0xf0a8, &mmCB_CGTT_SCLK_CTRL[0], sizeof(mmCB_CGTT_SCLK_CTRL)/sizeof(mmCB_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCC_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ac, &mmTCC_CGTT_SCLK_CTRL[0], sizeof(mmTCC_CGTT_SCLK_CTRL)/sizeof(mmTCC_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmTCA_CGTT_SCLK_CTRL", REG_MMIO, 0xf0ad, &mmTCA_CGTT_SCLK_CTRL[0], sizeof(mmTCA_CGTT_SCLK_CTRL)/sizeof(mmTCA_CGTT_SCLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CP_CLK_CTRL", REG_MMIO, 0xf0b0, &mmCGTT_CP_CLK_CTRL[0], sizeof(mmCGTT_CP_CLK_CTRL)/sizeof(mmCGTT_CP_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CPF_CLK_CTRL", REG_MMIO, 0xf0b1, &mmCGTT_CPF_CLK_CTRL[0], sizeof(mmCGTT_CPF_CLK_CTRL)/sizeof(mmCGTT_CPF_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_CPC_CLK_CTRL", REG_MMIO, 0xf0b2, &mmCGTT_CPC_CLK_CTRL[0], sizeof(mmCGTT_CPC_CLK_CTRL)/sizeof(mmCGTT_CPC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCGTT_RLC_CLK_CTRL", REG_MMIO, 0xf0b8, &mmCGTT_RLC_CLK_CTRL[0], sizeof(mmCGTT_RLC_CLK_CTRL)/sizeof(mmCGTT_RLC_CLK_CTRL[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_ADDR", REG_MMIO, 0xf814, &mmCP_PFP_UCODE_ADDR[0], sizeof(mmCP_PFP_UCODE_ADDR)/sizeof(mmCP_PFP_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_PFP_UCODE_DATA", REG_MMIO, 0xf815, &mmCP_PFP_UCODE_DATA[0], sizeof(mmCP_PFP_UCODE_DATA)/sizeof(mmCP_PFP_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_ME_RAM_RADDR", REG_MMIO, 0xf816, &mmCP_ME_RAM_RADDR[0], sizeof(mmCP_ME_RAM_RADDR)/sizeof(mmCP_ME_RAM_RADDR[0]), 0, 0 },
+	{ "mmCP_ME_RAM_DATA", REG_MMIO, 0xf817, &mmCP_ME_RAM_DATA[0], sizeof(mmCP_ME_RAM_DATA)/sizeof(mmCP_ME_RAM_DATA[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_ADDR", REG_MMIO, 0xf818, &mmCP_CE_UCODE_ADDR[0], sizeof(mmCP_CE_UCODE_ADDR)/sizeof(mmCP_CE_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_CE_UCODE_DATA", REG_MMIO, 0xf819, &mmCP_CE_UCODE_DATA[0], sizeof(mmCP_CE_UCODE_DATA)/sizeof(mmCP_CE_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_UCODE_ADDR", REG_MMIO, 0xf81a, &mmCP_MEC_ME1_UCODE_ADDR[0], sizeof(mmCP_MEC_ME1_UCODE_ADDR)/sizeof(mmCP_MEC_ME1_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_MEC_ME1_UCODE_DATA", REG_MMIO, 0xf81b, &mmCP_MEC_ME1_UCODE_DATA[0], sizeof(mmCP_MEC_ME1_UCODE_DATA)/sizeof(mmCP_MEC_ME1_UCODE_DATA[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_UCODE_ADDR", REG_MMIO, 0xf81c, &mmCP_MEC_ME2_UCODE_ADDR[0], sizeof(mmCP_MEC_ME2_UCODE_ADDR)/sizeof(mmCP_MEC_ME2_UCODE_ADDR[0]), 0, 0 },
+	{ "mmCP_MEC_ME2_UCODE_DATA", REG_MMIO, 0xf81d, &mmCP_MEC_ME2_UCODE_DATA[0], sizeof(mmCP_MEC_ME2_UCODE_DATA)/sizeof(mmCP_MEC_ME2_UCODE_DATA[0]), 0, 0 },
+	{ "mmGPU_BIST_CONTROL", REG_MMIO, 0xf835, &mmGPU_BIST_CONTROL[0], sizeof(mmGPU_BIST_CONTROL)/sizeof(mmGPU_BIST_CONTROL[0]), 0, 0 },
+	{ "mmRLC_ROM_CNTL", REG_MMIO, 0xf836, &mmRLC_ROM_CNTL[0], sizeof(mmRLC_ROM_CNTL)/sizeof(mmRLC_ROM_CNTL[0]), 0, 0 },
+	{ "mmRLC_GPM_UCODE_ADDR", REG_MMIO, 0xf83c, &mmRLC_GPM_UCODE_ADDR[0], sizeof(mmRLC_GPM_UCODE_ADDR)/sizeof(mmRLC_GPM_UCODE_ADDR[0]), 0, 0 },
+	{ "mmRLC_GPM_UCODE_DATA", REG_MMIO, 0xf83d, &mmRLC_GPM_UCODE_DATA[0], sizeof(mmRLC_GPM_UCODE_DATA)/sizeof(mmRLC_GPM_UCODE_DATA[0]), 0, 0 },
+	{ "mmGRBM_HYP_CAM_INDEX", REG_MMIO, 0xf83e, &mmGRBM_HYP_CAM_INDEX[0], sizeof(mmGRBM_HYP_CAM_INDEX)/sizeof(mmGRBM_HYP_CAM_INDEX[0]), 0, 0 },
+	{ "mmGRBM_CAM_INDEX", REG_MMIO, 0xf83e, &mmGRBM_CAM_INDEX[0], sizeof(mmGRBM_CAM_INDEX)/sizeof(mmGRBM_CAM_INDEX[0]), 0, 0 },
+	{ "mmGRBM_HYP_CAM_DATA", REG_MMIO, 0xf83f, &mmGRBM_HYP_CAM_DATA[0], sizeof(mmGRBM_HYP_CAM_DATA)/sizeof(mmGRBM_HYP_CAM_DATA[0]), 0, 0 },
+	{ "mmGRBM_CAM_DATA", REG_MMIO, 0xf83f, &mmGRBM_CAM_DATA[0], sizeof(mmGRBM_CAM_DATA)/sizeof(mmGRBM_CAM_DATA[0]), 0, 0 },
+	{ "mmSQ_HV_VMID_CTRL", REG_MMIO, 0xf840, &mmSQ_HV_VMID_CTRL[0], sizeof(mmSQ_HV_VMID_CTRL)/sizeof(mmSQ_HV_VMID_CTRL[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_VF_ENABLE", REG_MMIO, 0xfb00, &mmRLC_GPU_IOV_VF_ENABLE[0], sizeof(mmRLC_GPU_IOV_VF_ENABLE)/sizeof(mmRLC_GPU_IOV_VF_ENABLE[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_ACTIVE_FCN_ID", REG_MMIO, 0xfb40, &mmRLC_GPU_IOV_ACTIVE_FCN_ID[0], sizeof(mmRLC_GPU_IOV_ACTIVE_FCN_ID)/sizeof(mmRLC_GPU_IOV_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmRLC_GPU_IOV_RLC_RESPONSE", REG_MMIO, 0xfb4d, &mmRLC_GPU_IOV_RLC_RESPONSE[0], sizeof(mmRLC_GPU_IOV_RLC_RESPONSE)/sizeof(mmRLC_GPU_IOV_RLC_RESPONSE[0]), 0, 0 },
diff --git a/src/lib/ip/gmc60.c b/src/lib/ip/gmc60.c
new file mode 100644
index 0000000..e154922
--- /dev/null
+++ b/src/lib/ip/gmc60.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gmc60_bits.i"
+
+static const struct umr_reg gmc60_registers[] = {
+#include "gmc60_regs.i"
+};
+
+
+struct umr_ip_block *umr_create_gmc60(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gmc60";
+	ip->no_regs = sizeof(gmc60_registers)/sizeof(gmc60_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gmc60_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, gmc60_registers, sizeof(gmc60_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gmc60_bits.i b/src/lib/ip/gmc60_bits.i
new file mode 100644
index 0000000..746dd64
--- /dev/null
+++ b/src/lib/ip/gmc60_bits.i
@@ -0,0 +1,8339 @@
+static struct umr_bitfield ixMC_IO_DEBUG_UP_0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_2[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_3[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_4[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_5[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_6[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_7[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_8[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_9[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_10[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_11[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_12[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_13[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_14[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_15[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_16[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_17[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_18[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_19[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_20[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_21[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_22[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_23[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_24[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_25[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_26[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_27[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_28[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_29[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_30[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_31[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_32[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_33[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_34[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_35[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_36[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_37[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_38[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_39[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_40[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_41[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_42[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_43[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_44[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_45[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_46[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_47[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_48[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_49[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_50[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_51[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_52[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_53[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_54[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_55[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_56[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_57[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_58[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_59[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_60[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_61[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_62[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_63[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_64[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_65[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_66[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_67[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_68[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_69[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_70[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_71[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_72[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_73[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_74[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_75[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_76[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_77[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_78[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_79[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_80[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_81[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_82[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_83[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_84[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_85[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_86[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_87[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_88[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_89[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_90[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_91[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_92[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_93[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_94[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_95[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_96[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_97[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_98[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_99[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_100[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_101[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_102[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_103[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_104[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_105[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_106[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_107[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_108[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_109[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_110[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_111[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_112[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_113[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_114[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_115[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_116[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_117[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_118[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_119[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_120[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_121[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_122[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_123[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_124[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_125[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_126[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_127[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_128[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_129[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_130[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_131[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_132[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_133[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_134[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_135[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_136[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_137[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_138[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_139[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_140[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_141[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_142[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_143[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_144[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_145[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_146[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_147[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_148[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_149[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_150[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_151[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_152[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_153[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_154[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_155[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_156[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_157[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_158[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_159[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL[] = {
+	 { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default },
+	 { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default },
+	 { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default },
+	 { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default },
+	 { "L2_CACHE_4K_SWAP_TAG_INDEX_LSBS", 26, 27, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS", 28, 30, &umr_bitfield_default },
+	 { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default },
+	 { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default },
+	 { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL2[] = {
+	 { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default },
+	 { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default },
+	 { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_VMID_MODE", 23, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL3[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default },
+	 { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_STATUS[] = {
+	 { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default },
+	 { "L2_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = {
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = {
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = {
+	 { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default },
+	 { "DUMMY_PAGE_COMPARE_MASK", 2, 3, &umr_bitfield_default },
+	 { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR[] = {
+	 { "DUMMY_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL2[] = {
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL2[] = {
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_REQUEST[] = {
+	 { "INVALIDATE_DOMAIN_0", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_10", 10, 10, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_11", 11, 11, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_12", 12, 12, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_13", 13, 13, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_14", 14, 14, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_15", 15, 15, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_1", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_2", 2, 2, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_3", 3, 3, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_4", 4, 4, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_5", 5, 5, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_6", 6, 6, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_7", 7, 7, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_8", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_9", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_RESPONSE[] = {
+	 { "DOMAIN_INVALIDATED_0", 0, 0, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_10", 10, 10, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_11", 11, 11, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_12", 12, 12, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_13", 13, 13, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_14", 14, 14, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_15", 15, 15, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_1", 1, 1, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_2", 2, 2, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_3", 3, 3, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_4", 4, 4, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_5", 5, 5, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_6", 6, 6, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_7", 7, 7, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_8", 8, 8, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_9", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_CNTL[] = {
+	 { "L1_TLB_STORE_INVALID_ENTRIES", 3, 3, &umr_bitfield_default },
+	 { "L2_CACHE_STORE_INVALID_ENTRIES", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = {
+	 { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[] = {
+	 { "MEMORY_CLIENT_ID", 12, 19, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[] = {
+	 { "MEMORY_CLIENT_ID", 12, 19, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_FAULT_CLIENT_ID[] = {
+	 { "MEMORY_CLIENT", 0, 8, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_MASK", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DEBUG[] = {
+	 { "FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CG[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKA[] = {
+	 { "BANK_SELECT_MASK", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKB[] = {
+	 { "BANK_SELECT_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[] = {
+	 { "PHYSICAL_PAGE_OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG[] = {
+	 { "MCC_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHMAP[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "NOOFCHAN", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHREMAP[] = {
+	 { "CHAN0", 0, 2, &umr_bitfield_default },
+	 { "CHAN1", 3, 5, &umr_bitfield_default },
+	 { "CHAN2", 6, 8, &umr_bitfield_default },
+	 { "CHAN3", 9, 11, &umr_bitfield_default },
+	 { "CHAN4", 12, 14, &umr_bitfield_default },
+	 { "CHAN5", 15, 17, &umr_bitfield_default },
+	 { "CHAN6", 18, 20, &umr_bitfield_default },
+	 { "CHAN7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "XDMAM", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "XDMA", 12, 15, &umr_bitfield_default },
+	 { "XDMAM", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_SYS[] = {
+	 { "DMIF", 12, 15, &umr_bitfield_default },
+	 { "MCIF", 16, 19, &umr_bitfield_default },
+	 { "RLC", 0, 3, &umr_bitfield_default },
+	 { "SMU", 20, 23, &umr_bitfield_default },
+	 { "VCE", 24, 27, &umr_bitfield_default },
+	 { "VCEU", 28, 31, &umr_bitfield_default },
+	 { "VMC", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_SYS[] = {
+	 { "IH", 0, 3, &umr_bitfield_default },
+	 { "MCIF", 4, 7, &umr_bitfield_default },
+	 { "RLC", 8, 11, &umr_bitfield_default },
+	 { "SMU", 20, 23, &umr_bitfield_default },
+	 { "VCE", 24, 27, &umr_bitfield_default },
+	 { "VCEU", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_OTH[] = {
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "UVD_EXT1", 24, 27, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_OTH[] = {
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "UVD_EXT1", 28, 31, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "XDP", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_LOCATION[] = {
+	 { "FB_BASE", 0, 15, &umr_bitfield_default },
+	 { "FB_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_TOP[] = {
+	 { "AGP_TOP", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BOT[] = {
+	 { "AGP_BOT", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BASE[] = {
+	 { "AGP_BASE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_CNTL[] = {
+	 { "DC_MEMORY_WRITE_LOCAL", 8, 8, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_SYSTEM", 9, 9, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_0_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_1_MODE", 2, 3, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_2_MODE", 4, 5, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_3_MODE", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = {
+	 { "ECO_BITS", 7, 10, &umr_bitfield_default },
+	 { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default },
+	 { "ENABLE_L1_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
+	 { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_OFFSET[] = {
+	 { "FB_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCD_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG_MCD[] = {
+	 { "INDEX", 13, 28, &umr_bitfield_default },
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MEM_POWER_LS[] = {
+	 { "LS_HOLD", 6, 11, &umr_bitfield_default },
+	 { "LS_SETUP", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_BLACKOUT_CNTL[] = {
+	 { "BLACKOUT_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_POWER[] = {
+	 { "PM_BLACKOUT_CNTL", 3, 4, &umr_bitfield_default },
+	 { "SRBM_GATE_OVERRIDE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_HUB_CG[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_VM_CG[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_SIP_CG[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_DBG[] = {
+	 { "SELECT0", 0, 3, &umr_bitfield_default },
+	 { "SELECT1", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_STATUS[] = {
+	 { "GFX_BUSY", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDREQ", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDRET", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRREQ", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRRET", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_READ", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_WRITE", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_READ", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_WRITE", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE", 1, 1, &umr_bitfield_default },
+	 { "READ_DEADLOCK_WARNING", 12, 12, &umr_bitfield_default },
+	 { "RPB_BUSY", 10, 10, &umr_bitfield_default },
+	 { "WRITE_DEADLOCK_WARNING", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_OVERRIDE[] = {
+	 { "IDLE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_FRAMING[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CNTL[] = {
+	 { "DEBUG_REG", 5, 12, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_INTERNAL", 15, 15, &umr_bitfield_default },
+	 { "DISP_WAIT_EOP", 18, 18, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 16, 16, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL0", 1, 1, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_INTERNAL", 3, 3, &umr_bitfield_default },
+	 { "LCLWRREQ_BYPASS", 17, 17, &umr_bitfield_default },
+	 { "MCD_WAIT_EOP", 19, 19, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SIP_WAIT_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ERR[] = {
+	 { "MGPU1_TARG_SYS", 0, 0, &umr_bitfield_default },
+	 { "MGPU2_TARG_SYS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RDRET", 1, 17, &umr_bitfield_default },
+	 { "WRREQ", 18, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_STATUS[] = {
+	 { "GBL0_BYPASS_STOR_FULL", 7, 7, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 6, 6, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 5, 5, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 10, 10, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 9, 9, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 8, 8, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDW_WR_AVAIL", 11, 11, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDX_WR_AVAIL", 12, 12, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDY_WR_AVAIL", 13, 13, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDZ_WR_AVAIL", 14, 14, &umr_bitfield_default },
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_STATUS[] = {
+	 { "GBL0_BYPASS_STOR_FULL", 7, 7, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 6, 6, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 5, 5, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 10, 10, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 9, 9, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 8, 8, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "PWRXPRESS_ERR", 11, 11, &umr_bitfield_default },
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_STATUS[] = {
+	 { "MCDW_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDX_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDY_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_AVAIL", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CNTL[] = {
+	 { "BREAK_HDP_DEADLOCK", 9, 9, &umr_bitfield_default },
+	 { "DEBUG_REG", 10, 16, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 18, 18, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL0", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 3, 3, &umr_bitfield_default },
+	 { "MCDW_STALL_MODE", 5, 5, &umr_bitfield_default },
+	 { "MCDX_STALL_MODE", 6, 6, &umr_bitfield_default },
+	 { "MCDY_STALL_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCDZ_STALL_MODE", 8, 8, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "PWRXPRESS_MODE", 19, 19, &umr_bitfield_default },
+	 { "REMOTE_BLACKOUT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_CNTL[] = {
+	 { "BP_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "BP", 1, 20, &umr_bitfield_default },
+	 { "DEBUG_REG", 22, 29, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 30, 30, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 31, 31, &umr_bitfield_default },
+	 { "JUMPAHEAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS[] = {
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MGPU2[] = {
+	 { "CID2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL0[] = {
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL1[] = {
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MGPU[] = {
+	 { "CID", 8, 15, &umr_bitfield_default },
+	 { "ENABLE", 23, 23, &umr_bitfield_default },
+	 { "MGPU_PRIORITY_TIME", 16, 22, &umr_bitfield_default },
+	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
+	 { "STOR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS[] = {
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS2[] = {
+	 { "STOR1_PRI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_SHARED_DAGB_DLY[] = {
+	 { "CLI", 16, 20, &umr_bitfield_default },
+	 { "DLY", 0, 5, &umr_bitfield_default },
+	 { "POS", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_IDLE_STATUS[] = {
+	 { "OUTSTANDING_CP_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_CP_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_READ", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_WRITE", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_GFX_READ", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_GFX_WRITE", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_READ", 16, 16, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_WRITE", 17, 17, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_READ", 18, 18, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_WRITE", 19, 19, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_READ", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_WRITE", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_READ", 14, 14, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_WRITE", 15, 15, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_READ", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_WRITE", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_READ", 24, 24, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_WRITE", 25, 25, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_READ", 20, 20, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_WRITE", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDW[] = {
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDX[] = {
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDY[] = {
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDZ[] = {
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SIP[] = {
+	 { "ASK_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 8, 14, &umr_bitfield_default },
+	 { "DUMMY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL0[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL1[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SMU[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_HDP[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_RLC[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SEM[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCE[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UMC[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UVD[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCIF[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VMC[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCEU[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDW[] = {
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDX[] = {
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDY[] = {
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDZ[] = {
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SIP[] = {
+	 { "ASK_CREDITS", 2, 8, &umr_bitfield_default },
+	 { "STALL_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH0[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCIF[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCE[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDP[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_IH[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_RLC[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SEM[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SMU[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH1[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UMC[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UVD[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_HDP[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDW[] = {
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDX[] = {
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDY[] = {
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDZ[] = {
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCEU[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMAM[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMA[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_XDMAM[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_DEBUG[] = {
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_DEBUG[] = {
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_DEBUG[] = {
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR4[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR5[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR6[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR7[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR8[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR9[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP0[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP1[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP2[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP3[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP4[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP5[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP6[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP7[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP8[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP9[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP0[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP1[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP2[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP3[] = {
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG0[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG1[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG2[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG3[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG4[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG5[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG6[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG7[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG8[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG9[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG10[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG11[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG12[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG13[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG14[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG15[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG16[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG17[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG18[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG19[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_LB_ADDR[] = {
+	 { "CMP0", 0, 9, &umr_bitfield_default },
+	 { "CMP1", 20, 25, &umr_bitfield_default },
+	 { "MASK0", 10, 19, &umr_bitfield_default },
+	 { "MASK1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_HST[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_SID[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_STS[] = {
+	 { "PBUF_VLD", 0, 15, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 16, 22, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 23, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_CFG[] = {
+	 { "HST_MAX", 16, 17, &umr_bitfield_default },
+	 { "SID_MAX", 18, 19, &umr_bitfield_default },
+	 { "TIMEOUT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_CFG[] = {
+	 { "ADDR_SIZE", 0, 3, &umr_bitfield_default },
+	 { "ATC_TRANSLATED", 12, 12, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 8, 8, &umr_bitfield_default },
+	 { "RD_EN", 11, 11, &umr_bitfield_default },
+	 { "REGBAR_FROM_SYSBAR", 10, 10, &umr_bitfield_default },
+	 { "SEND_BAR", 4, 5, &umr_bitfield_default },
+	 { "SEND_DIS", 7, 7, &umr_bitfield_default },
+	 { "SNOOP", 6, 6, &umr_bitfield_default },
+	 { "UPDATE_DIS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR0[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR1[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR2[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR3[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR4[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR5[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR6[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR7[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_SETUP[] = {
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DEBUG[] = {
+	 { "HOST_FLUSH", 8, 11, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 12, 15, &umr_bitfield_default },
+	 { "SEL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_ABOVE[] = {
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+	 { "EN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_BELOW[] = {
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+	 { "EN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR0[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR1[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR2[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR3[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR4[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR5[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR6[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR7[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR8[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR9[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR0[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR1[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR2[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR3[] = {
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLK_GAT[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG[] = {
+	 { "BIF_MEM_SNOOP_SEL", 25, 25, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_VAL", 26, 26, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_SEL", 23, 23, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_VAL", 24, 24, &umr_bitfield_default },
+	 { "MC_WRRET_ASK", 8, 15, &umr_bitfield_default },
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "XSP_ORDERING_SEL", 30, 30, &umr_bitfield_default },
+	 { "XSP_ORDERING_VAL", 31, 31, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 16, 22, &umr_bitfield_default },
+	 { "XSP_SNOOP_SEL", 27, 28, &umr_bitfield_default },
+	 { "XSP_SNOOP_VAL", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_STS[] = {
+	 { "CNS_BUF_BUSY", 18, 18, &umr_bitfield_default },
+	 { "CNS_BUF_FULL", 17, 17, &umr_bitfield_default },
+	 { "HOP_ATTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "HOP_DATA_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "RPB_RDREQ_CRD", 19, 26, &umr_bitfield_default },
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PIPE_STS[] = {
+	 { "RET_BUF_FULL", 23, 23, &umr_bitfield_default },
+	 { "WCB_ANY_PBUF", 0, 0, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 1, 7, &umr_bitfield_default },
+	 { "WCB_HST_DATA_OBUF_FULL", 21, 21, &umr_bitfield_default },
+	 { "WCB_HST_RD_PTR_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "WCB_HST_REQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "WCB_HST_REQ_OBUF_FULL", 19, 19, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 8, 14, &umr_bitfield_default },
+	 { "WCB_SID_DATA_OBUF_FULL", 22, 22, &umr_bitfield_default },
+	 { "WCB_SID_RD_PTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "WCB_SID_REQ_FIFO_FULL", 18, 18, &umr_bitfield_default },
+	 { "WCB_SID_REQ_OBUF_FULL", 20, 20, &umr_bitfield_default },
+	 { "XPB_CLK_BUSY_BITS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_SUB_CTRL[] = {
+	 { "RESET_CGR", 19, 19, &umr_bitfield_default },
+	 { "RESET_CNS", 10, 10, &umr_bitfield_default },
+	 { "RESET_HOP", 16, 16, &umr_bitfield_default },
+	 { "RESET_HST", 15, 15, &umr_bitfield_default },
+	 { "RESET_MAP", 13, 13, &umr_bitfield_default },
+	 { "RESET_RET", 12, 12, &umr_bitfield_default },
+	 { "RESET_RTR", 11, 11, &umr_bitfield_default },
+	 { "RESET_SID", 17, 17, &umr_bitfield_default },
+	 { "RESET_SRB", 18, 18, &umr_bitfield_default },
+	 { "RESET_WCB", 14, 14, &umr_bitfield_default },
+	 { "STALL_CNS_RTR_REQ", 1, 1, &umr_bitfield_default },
+	 { "STALL_HST_HOP_REQ", 8, 8, &umr_bitfield_default },
+	 { "STALL_MAP_WCB_REQ", 4, 4, &umr_bitfield_default },
+	 { "STALL_MC_XSP_REQ_SEND", 6, 6, &umr_bitfield_default },
+	 { "STALL_RTR_MAP_REQ", 3, 3, &umr_bitfield_default },
+	 { "STALL_RTR_RPB_WRREQ", 2, 2, &umr_bitfield_default },
+	 { "STALL_WCB_HST_REQ", 7, 7, &umr_bitfield_default },
+	 { "STALL_WCB_SID_REQ", 5, 5, &umr_bitfield_default },
+	 { "STALL_XPB_RPB_REQ_ATTR", 9, 9, &umr_bitfield_default },
+	 { "WRREQ_BYPASS_XPB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[] = {
+	 { "ALTER_FLUSH_NUM", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PERF_KNOBS[] = {
+	 { "CNS_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+	 { "WCB_HST_FIFO_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "WCB_SID_FIFO_DEPTH", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY_W1C[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MISC_CFG[] = {
+	 { "FIELDNAME0", 0, 7, &umr_bitfield_default },
+	 { "FIELDNAME1", 8, 15, &umr_bitfield_default },
+	 { "FIELDNAME2", 16, 23, &umr_bitfield_default },
+	 { "FIELDNAME3", 24, 30, &umr_bitfield_default },
+	 { "TRIGGERNAME", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG20[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG21[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG22[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG23[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG24[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG25[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG26[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG27[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG28[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG29[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG30[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG31[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG2[] = {
+	 { "RPB_RDREQ_CRD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA_RD[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG32[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG33[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG34[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG35[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG36[] = {
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CONF[] = {
+	 { "RPB_RD_PCIE_ORDER", 16, 16, &umr_bitfield_default },
+	 { "RPB_WR_PCIE_ORDER", 17, 17, &umr_bitfield_default },
+	 { "XPB_PCIE_ORDER", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_IF_CONF[] = {
+	 { "OUTSTANDING_WRRET_ASK", 8, 15, &umr_bitfield_default },
+	 { "RPB_BIF_CREDITS", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_DBG1[] = {
+	 { "DEBUG_BITS", 20, 31, &umr_bitfield_default },
+	 { "RPB_BIF_OUTSTANDING_RD_32B", 8, 19, &umr_bitfield_default },
+	 { "RPB_BIF_OUTSTANDING_RD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_EFF_CNTL[] = {
+	 { "RD_LAZY_TIMER", 8, 15, &umr_bitfield_default },
+	 { "WR_LAZY_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_ARB_CNTL[] = {
+	 { "ATC_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "RD_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "WR_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_BIF_CNTL[] = {
+	 { "ARB_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "XPB_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_COMBINE_CNTL[] = {
+	 { "WC_ALIGN", 7, 7, &umr_bitfield_default },
+	 { "WC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "WC_FLUSH_TIMER", 3, 6, &umr_bitfield_default },
+	 { "WC_MAX_PACKET_SIZE", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_RD_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_WR[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "READ_QUEUE", 11, 12, &umr_bitfield_default },
+	 { "UPDATE", 13, 13, &umr_bitfield_default },
+	 { "UPDATE_MODE", 8, 8, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 9, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_RD[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "READ_QUEUE", 10, 11, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_CNTL[] = {
+	 { "CLEAR_ALL_PERF_COUNTERS", 3, 3, &umr_bitfield_default },
+	 { "CLEAR_SELECTED_PERF_COUNTER", 2, 2, &umr_bitfield_default },
+	 { "ENABLE_PERF_COUNTERS", 5, 8, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_0", 9, 13, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_1", 14, 18, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_2", 19, 23, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_3", 24, 28, &umr_bitfield_default },
+	 { "PERF_COUNTER_SELECT", 0, 1, &umr_bitfield_default },
+	 { "STOP_ON_COUNTER_SATURATION", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_STATUS[] = {
+	 { "PERFORMANCE_COUNTER_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX[] = {
+	 { "OFFSET", 1, 5, &umr_bitfield_default },
+	 { "START", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX_DATA[] = {
+	 { "READ_ENTRIES", 16, 31, &umr_bitfield_default },
+	 { "WRITE_ENTRIES", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_XTRA_ENABLE[] = {
+	 { "ARB_DBG", 8, 11, &umr_bitfield_default },
+	 { "CB1_RD", 0, 0, &umr_bitfield_default },
+	 { "CB1_WR", 1, 1, &umr_bitfield_default },
+	 { "DB1_RD", 2, 2, &umr_bitfield_default },
+	 { "DB1_WR", 3, 3, &umr_bitfield_default },
+	 { "TC2_RD", 4, 4, &umr_bitfield_default },
+	 { "TC2_WR", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_MC_MAX_CHANNEL[] = {
+	 { "NOOFCHAN", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG[] = {
+	 { "INDEX", 6, 21, &umr_bitfield_default },
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CNTL[] = {
+	 { "EXEMPTPM", 3, 3, &umr_bitfield_default },
+	 { "GFX_IDLE_OVERRIDE", 4, 5, &umr_bitfield_default },
+	 { "IGNOREPM", 2, 2, &umr_bitfield_default },
+	 { "MCD_SRBM_MASK_ENABLE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_VM[] = {
+	 { "READ_ALL", 0, 5, &umr_bitfield_default },
+	 { "WRITE_ALL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_RD[] = {
+	 { "HUB_PRI", 25, 25, &umr_bitfield_default },
+	 { "LCL_PRI", 24, 24, &umr_bitfield_default },
+	 { "READ_HUB", 8, 15, &umr_bitfield_default },
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "READ_PRI", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_WR[] = {
+	 { "HUB_PRI", 16, 16, &umr_bitfield_default },
+	 { "LCL_PRI", 17, 17, &umr_bitfield_default },
+	 { "WRITE_HUB", 8, 15, &umr_bitfield_default },
+	 { "WRITE_LCL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_CNTL[] = {
+	 { "CENTER_RD_MAX_BURST", 1, 4, &umr_bitfield_default },
+	 { "CENTER_WR_MAX_BURST", 6, 9, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 5, 5, &umr_bitfield_default },
+	 { "JUMP_AHEAD", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS[] = {
+	 { "CNTR_RD_HUB_HP", 18, 23, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_LP", 12, 17, &umr_bitfield_default },
+	 { "CNTR_RD_LCL", 24, 29, &umr_bitfield_default },
+	 { "REMRDRET", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_RET_MODE[] = {
+	 { "INORDER_RD", 0, 0, &umr_bitfield_default },
+	 { "INORDER_WR", 1, 1, &umr_bitfield_default },
+	 { "LCLPRI_RD", 4, 4, &umr_bitfield_default },
+	 { "LCLPRI_WR", 5, 5, &umr_bitfield_default },
+	 { "REMPRI_RD", 2, 2, &umr_bitfield_default },
+	 { "REMPRI_WR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_DLY[] = {
+	 { "CLI", 16, 20, &umr_bitfield_default },
+	 { "DLY", 0, 4, &umr_bitfield_default },
+	 { "POS", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_REMREQ[] = {
+	 { "CREDITS_ENABLE", 14, 14, &umr_bitfield_default },
+	 { "READ_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "WRITE_CREDITS", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC0[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC1[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS_WR[] = {
+	 { "CNTR_WR_HUB", 0, 5, &umr_bitfield_default },
+	 { "CNTR_WR_LCL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_RD_CNTL[] = {
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_WR_CNTL[] = {
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_CB[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_DB[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC0[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC1[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_HUB[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_CB[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_DB[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_HUB[] = {
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_XBAR[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_LCL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_LCL[] = {
+	 { "CB0", 12, 15, &umr_bitfield_default },
+	 { "CBCMASK0", 16, 19, &umr_bitfield_default },
+	 { "CBFMASK0", 20, 23, &umr_bitfield_default },
+	 { "DB0", 24, 27, &umr_bitfield_default },
+	 { "DBHTILE0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_LCL[] = {
+	 { "CB0", 0, 3, &umr_bitfield_default },
+	 { "CBCMASK0", 4, 7, &umr_bitfield_default },
+	 { "CBFMASK0", 8, 11, &umr_bitfield_default },
+	 { "CBIMMED0", 28, 31, &umr_bitfield_default },
+	 { "DB0", 12, 15, &umr_bitfield_default },
+	 { "DBHTILE0", 16, 19, &umr_bitfield_default },
+	 { "SX0", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_CNTL2[] = {
+	 { "CID", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_RSLT2[] = {
+	 { "CB_RD_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CB_WR_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DB_RD_BUSY", 7, 7, &umr_bitfield_default },
+	 { "DB_WR_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SX_WR_BUSY", 14, 14, &umr_bitfield_default },
+	 { "TC0_RD_BUSY", 8, 8, &umr_bitfield_default },
+	 { "TC0_WR_BUSY", 16, 16, &umr_bitfield_default },
+	 { "TC1_RD_BUSY", 10, 10, &umr_bitfield_default },
+	 { "TC1_WR_BUSY", 17, 17, &umr_bitfield_default },
+	 { "TC2_RD_BUSY", 15, 15, &umr_bitfield_default },
+	 { "TC2_WR_BUSY", 18, 18, &umr_bitfield_default },
+	 { "VC0_RD_BUSY", 9, 9, &umr_bitfield_default },
+	 { "VC1_RD_BUSY", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_RD_CG[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_WR_CG[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_VM_CG[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_DEBUG[] = {
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_DEBUG[] = {
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_DEBUG[] = {
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_DEBUG[] = {
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_FED_CNTL[] = {
+	 { "KEEP_POISON_IN_PAGE", 4, 4, &umr_bitfield_default },
+	 { "MODE", 0, 1, &umr_bitfield_default },
+	 { "WR_ERR", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_STATUS[] = {
+	 { "CORR_CLEAR0", 8, 8, &umr_bitfield_default },
+	 { "CORR_CLEAR1", 12, 12, &umr_bitfield_default },
+	 { "CORR_STS0", 0, 0, &umr_bitfield_default },
+	 { "CORR_STS1", 4, 4, &umr_bitfield_default },
+	 { "FED_CLEAR0", 10, 10, &umr_bitfield_default },
+	 { "FED_CLEAR1", 14, 14, &umr_bitfield_default },
+	 { "FED_STS0", 2, 2, &umr_bitfield_default },
+	 { "FED_STS1", 6, 6, &umr_bitfield_default },
+	 { "RSVD0", 3, 3, &umr_bitfield_default },
+	 { "RSVD1", 7, 7, &umr_bitfield_default },
+	 { "RSVD2", 11, 11, &umr_bitfield_default },
+	 { "UNCORR_CLEAR0", 9, 9, &umr_bitfield_default },
+	 { "UNCORR_CLEAR1", 13, 13, &umr_bitfield_default },
+	 { "UNCORR_STS0", 1, 1, &umr_bitfield_default },
+	 { "UNCORR_STS1", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_MISC[] = {
+	 { "STREAK_BREAK", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG[] = {
+	 { "DATA_FIELD", 3, 4, &umr_bitfield_default },
+	 { "DIRECTION", 2, 2, &umr_bitfield_default },
+	 { "NUM_ERR_BITS", 0, 1, &umr_bitfield_default },
+	 { "SW_INJECTION", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG2[] = {
+	 { "ERR0_START", 8, 15, &umr_bitfield_default },
+	 { "ERR1_START", 16, 23, &umr_bitfield_default },
+	 { "ERR2_START", 24, 31, &umr_bitfield_default },
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2[] = {
+	 { "CLOSE_BANK_RMW", 14, 14, &umr_bitfield_default },
+	 { "COLFIFO_WATER", 15, 20, &umr_bitfield_default },
+	 { "ECC_MODE", 1, 2, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "EXOR_BANK_SEL", 5, 6, &umr_bitfield_default },
+	 { "NO_GECC_CLI", 7, 10, &umr_bitfield_default },
+	 { "PAGE_BIT0", 3, 4, &umr_bitfield_default },
+	 { "READ_ERR", 11, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_CLI[] = {
+	 { "NO_GECC_CLI0", 0, 7, &umr_bitfield_default },
+	 { "NO_GECC_CLI1", 8, 15, &umr_bitfield_default },
+	 { "NO_GECC_CLI2", 16, 23, &umr_bitfield_default },
+	 { "NO_GECC_CLI3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WCDR_2[] = {
+	 { "DEBUG_0", 9, 9, &umr_bitfield_default },
+	 { "DEBUG_1", 10, 10, &umr_bitfield_default },
+	 { "DEBUG_2", 11, 11, &umr_bitfield_default },
+	 { "DEBUG_3", 12, 12, &umr_bitfield_default },
+	 { "DEBUG_4", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_5", 14, 14, &umr_bitfield_default },
+	 { "WPRE_INC_STEP", 0, 3, &umr_bitfield_default },
+	 { "WPRE_MIN_THRESHOLD", 4, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DATA[] = {
+	 { "PATTERN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL0[] = {
+	 { "BREAK_ON_HARSH", 8, 8, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTRD", 9, 9, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTWR", 10, 10, &umr_bitfield_default },
+	 { "DATA_CNTL", 24, 24, &umr_bitfield_default },
+	 { "DEBUG_RSV_0", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_RSV_1", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_RSV_2", 17, 17, &umr_bitfield_default },
+	 { "DEBUG_RSV_3", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_RSV_4", 19, 19, &umr_bitfield_default },
+	 { "DEBUG_RSV_5", 20, 20, &umr_bitfield_default },
+	 { "DEBUG_RSV_6", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_RSV_7", 22, 22, &umr_bitfield_default },
+	 { "DEBUG_RSV_8", 23, 23, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "FLUSH_ON_ENTER", 4, 4, &umr_bitfield_default },
+	 { "HARSH_START", 5, 5, &umr_bitfield_default },
+	 { "NEIGHBOR_BIT", 25, 25, &umr_bitfield_default },
+	 { "START_IDLE", 1, 1, &umr_bitfield_default },
+	 { "START_R2W", 2, 3, &umr_bitfield_default },
+	 { "START_R2W_RFSH", 14, 14, &umr_bitfield_default },
+	 { "TPS_HARSH_PRIORITY", 6, 6, &umr_bitfield_default },
+	 { "TRAIN_PERIOD", 11, 13, &umr_bitfield_default },
+	 { "TWRT_HARSH_PRIORITY", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL1[] = {
+	 { "WINDOW_DEC_THRESHOLD", 13, 19, &umr_bitfield_default },
+	 { "WINDOW_INC_THRESHOLD", 6, 12, &umr_bitfield_default },
+	 { "WINDOW_SIZE", 0, 4, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MAX", 20, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MIN", 25, 29, &umr_bitfield_default },
+	 { "WINDOW_UPDATE_COUNT", 30, 31, &umr_bitfield_default },
+	 { "WINDOW_UPDATE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL2[] = {
+	 { "FILTER_CNTL", 13, 13, &umr_bitfield_default },
+	 { "PHASE_ADJUST_SIZE", 12, 12, &umr_bitfield_default },
+	 { "PHASE_ADJUST_THRESHOLD", 6, 11, &umr_bitfield_default },
+	 { "SAMPLE_CNT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DEBUG[] = {
+	 { "DEBUG_BYTE_CH0", 0, 1, &umr_bitfield_default },
+	 { "DEBUG_BYTE_CH1", 2, 3, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH0", 4, 11, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH1", 17, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH0", 12, 16, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH1", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CAC_CNTL[] = {
+	 { "ALLOW_OVERFLOW", 13, 13, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "READ_WEIGHT", 1, 6, &umr_bitfield_default },
+	 { "WRITE_WEIGHT", 7, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC2[] = {
+	 { "ARB_DEBUG29", 29, 29, &umr_bitfield_default },
+	 { "GECC", 18, 18, &umr_bitfield_default },
+	 { "GECC_RST", 19, 19, &umr_bitfield_default },
+	 { "GECC_STATUS", 20, 20, &umr_bitfield_default },
+	 { "POP_IDLE_REPLAY", 11, 11, &umr_bitfield_default },
+	 { "RDRET_NO_BP", 13, 13, &umr_bitfield_default },
+	 { "RDRET_NO_REORDERING", 12, 12, &umr_bitfield_default },
+	 { "RDRET_SEQ_SKID", 14, 17, &umr_bitfield_default },
+	 { "REPLAY_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "SEQ_RDY_POP_IDLE", 30, 30, &umr_bitfield_default },
+	 { "TAGFIFO_THRESHOLD", 21, 24, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT4", 6, 6, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT5", 7, 7, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT6", 8, 8, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT7", 9, 9, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT8", 10, 10, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "TCCDL4_REPLAY_EOB", 31, 31, &umr_bitfield_default },
+	 { "WCDR_REPLAY_MASKCNT", 25, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC[] = {
+	 { "CALI_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CALI_RATES", 21, 22, &umr_bitfield_default },
+	 { "CHAN_COUPLE", 3, 10, &umr_bitfield_default },
+	 { "DISPURG_NOSW2WR", 24, 24, &umr_bitfield_default },
+	 { "DISPURG_STALL", 25, 25, &umr_bitfield_default },
+	 { "DISPURG_THROTTLE", 26, 29, &umr_bitfield_default },
+	 { "DISPURGVLD_NOWRT", 23, 23, &umr_bitfield_default },
+	 { "HARSHNESS", 11, 18, &umr_bitfield_default },
+	 { "IDLE_RFSH", 1, 1, &umr_bitfield_default },
+	 { "SMART_RDWR_SW", 19, 19, &umr_bitfield_default },
+	 { "STICKY_RFSH", 0, 0, &umr_bitfield_default },
+	 { "STUTTER_RFSH", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BANKMAP[] = {
+	 { "BANK0", 0, 3, &umr_bitfield_default },
+	 { "BANK1", 4, 7, &umr_bitfield_default },
+	 { "BANK2", 8, 11, &umr_bitfield_default },
+	 { "BANK3", 12, 15, &umr_bitfield_default },
+	 { "RANK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RAMCFG[] = {
+	 { "CHANSIZE", 8, 8, &umr_bitfield_default },
+	 { "NOOFBANK", 0, 1, &umr_bitfield_default },
+	 { "NOOFCOLS", 6, 7, &umr_bitfield_default },
+	 { "NOOFGROUPS", 12, 12, &umr_bitfield_default },
+	 { "NOOFRANKS", 2, 2, &umr_bitfield_default },
+	 { "NOOFROWS", 3, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_POP[] = {
+	 { "ALLOW_EOB_BY_WRRET_STALL", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_ARB", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_TWO_PAGE", 18, 18, &umr_bitfield_default },
+	 { "POP_DEPTH", 2, 5, &umr_bitfield_default },
+	 { "QUICK_STOP", 17, 17, &umr_bitfield_default },
+	 { "SKID_DEPTH", 12, 14, &umr_bitfield_default },
+	 { "SPEC_OPEN", 1, 1, &umr_bitfield_default },
+	 { "WAIT_AFTER_RFSH", 15, 16, &umr_bitfield_default },
+	 { "WRDATAINDEX_DEPTH", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MINCLKS[] = {
+	 { "ARB_RW_SWITCH", 16, 16, &umr_bitfield_default },
+	 { "READ_CLKS", 0, 7, &umr_bitfield_default },
+	 { "WRITE_CLKS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SQM_CNTL[] = {
+	 { "DYN_SQM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "MIN_PENAL", 0, 7, &umr_bitfield_default },
+	 { "RATIO_DEBUG", 24, 31, &umr_bitfield_default },
+	 { "RATIO", 16, 23, &umr_bitfield_default },
+	 { "SQM_RESERVE", 9, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_HASH[] = {
+	 { "BANK_XOR_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "COL_XOR", 4, 11, &umr_bitfield_default },
+	 { "ROW_XOR", 12, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2[] = {
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_RD[] = {
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_WR[] = {
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_RD[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_WR[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_RD[] = {
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_WR[] = {
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_RD[] = {
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_WR[] = {
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_CNTL[] = {
+	 { "ACCUM", 11, 11, &umr_bitfield_default },
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "URG0", 1, 5, &umr_bitfield_default },
+	 { "URG1", 6, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_RATE[] = {
+	 { "POWERMODE0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PM_CNTL[] = {
+	 { "BLKOUT_ON_D1", 5, 5, &umr_bitfield_default },
+	 { "IDLE_CNT", 20, 23, &umr_bitfield_default },
+	 { "IDLE_ON_D1", 6, 6, &umr_bitfield_default },
+	 { "IDLE_ON_D2", 18, 18, &umr_bitfield_default },
+	 { "IDLE_ON_D3", 19, 19, &umr_bitfield_default },
+	 { "OVERRIDE_CGSTATE", 0, 1, &umr_bitfield_default },
+	 { "OVRR_CGRFSH", 2, 2, &umr_bitfield_default },
+	 { "OVRR_CGSQM", 3, 3, &umr_bitfield_default },
+	 { "OVRR_PM", 7, 7, &umr_bitfield_default },
+	 { "OVRR_PM_STATE", 8, 9, &umr_bitfield_default },
+	 { "OVRR_RD", 10, 10, &umr_bitfield_default },
+	 { "OVRR_RD_STATE", 11, 11, &umr_bitfield_default },
+	 { "OVRR_RFSH", 14, 14, &umr_bitfield_default },
+	 { "OVRR_RFSH_STATE", 15, 15, &umr_bitfield_default },
+	 { "OVRR_WR", 12, 12, &umr_bitfield_default },
+	 { "OVRR_WR_STATE", 13, 13, &umr_bitfield_default },
+	 { "SRFSH_ON_D1", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_RD_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_WR_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_RD[] = {
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_WR[] = {
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REMREQ[] = {
+	 { "RD_WATER", 0, 7, &umr_bitfield_default },
+	 { "WR_LAZY_TIMER", 20, 23, &umr_bitfield_default },
+	 { "WR_MAXBURST_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WR_WATER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REPLAY[] = {
+	 { "BOS_ENABLE_WAIT_CYC", 7, 7, &umr_bitfield_default },
+	 { "BOS_WAIT_CYC", 8, 14, &umr_bitfield_default },
+	 { "BREAK_ON_STALL", 6, 6, &umr_bitfield_default },
+	 { "ENABLE_RD", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_WR", 1, 1, &umr_bitfield_default },
+	 { "IGNORE_WR_CDC", 5, 5, &umr_bitfield_default },
+	 { "RAW_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "WAW_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "WRACK_MODE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_RD[] = {
+	 { "DISP", 16, 23, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_WR[] = {
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 16, 23, &umr_bitfield_default },
+	 { "WRRET_SEQ_SKID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CG[] = {
+	 { "CG_ARB_REQ", 0, 7, &umr_bitfield_default },
+	 { "CG_ARB_RESP", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WCDR[] = {
+	 { "IDLE_BURST", 7, 12, &umr_bitfield_default },
+	 { "IDLE_BURST_MODE", 13, 13, &umr_bitfield_default },
+	 { "IDLE_DEGLITCH_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "IDLE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IDLE_PERIOD", 2, 6, &umr_bitfield_default },
+	 { "IDLE_WAKEUP", 14, 15, &umr_bitfield_default },
+	 { "SEQ_IDLE", 1, 1, &umr_bitfield_default },
+	 { "WPRE_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "WPRE_INC_READ", 25, 25, &umr_bitfield_default },
+	 { "WPRE_INC_SEQIDLE", 27, 27, &umr_bitfield_default },
+	 { "WPRE_INC_SKIDIDLE", 26, 26, &umr_bitfield_default },
+	 { "WPRE_MAX_BURST", 22, 24, &umr_bitfield_default },
+	 { "WPRE_THRESHOLD", 18, 21, &umr_bitfield_default },
+	 { "WPRE_TWOPAGE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING_1[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2_1[] = {
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BURST_TIME[] = {
+	 { "STATE0", 0, 4, &umr_bitfield_default },
+	 { "STATE1", 5, 9, &umr_bitfield_default },
+	 { "STATE2", 10, 14, &umr_bitfield_default },
+	 { "STATE3", 15, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CNTL[] = {
+	 { "ADR_MODE", 5, 5, &umr_bitfield_default },
+	 { "DAT_MODE", 6, 6, &umr_bitfield_default },
+	 { "DONE", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_D0", 12, 12, &umr_bitfield_default },
+	 { "ENABLE_D1", 13, 13, &umr_bitfield_default },
+	 { "LOAD_RTDATA_CH", 14, 14, &umr_bitfield_default },
+	 { "LOAD_RTDATA", 31, 31, &umr_bitfield_default },
+	 { "LOOP_CNT", 16, 27, &umr_bitfield_default },
+	 { "LOOP", 10, 11, &umr_bitfield_default },
+	 { "MOP_MODE", 4, 4, &umr_bitfield_default },
+	 { "PTR_RST_D0", 2, 2, &umr_bitfield_default },
+	 { "PTR_RST_D1", 3, 3, &umr_bitfield_default },
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "RUN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_AUTO_CNTL[] = {
+	 { "ADR_GEN", 4, 7, &umr_bitfield_default },
+	 { "ADR_RESET", 25, 25, &umr_bitfield_default },
+	 { "LFSR_KEY", 8, 23, &umr_bitfield_default },
+	 { "LFSR_RESET", 24, 24, &umr_bitfield_default },
+	 { "MOP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DIR_CNTL[] = {
+	 { "CMD_RTR_D0", 6, 6, &umr_bitfield_default },
+	 { "CMD_RTR_D1", 8, 8, &umr_bitfield_default },
+	 { "DATA_LOAD", 5, 5, &umr_bitfield_default },
+	 { "DAT_RTR_D0", 7, 7, &umr_bitfield_default },
+	 { "DAT_RTR_D1", 9, 9, &umr_bitfield_default },
+	 { "EOB", 3, 3, &umr_bitfield_default },
+	 { "MOP3", 10, 10, &umr_bitfield_default },
+	 { "MOP_LOAD", 4, 4, &umr_bitfield_default },
+	 { "MOP", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_SADDR[] = {
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_EADDR[] = {
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_MASK[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_MISMATCH_ADDR[] = {
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD0[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD1[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD2[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD3[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD4[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD5[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD6[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD7[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_MASK[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_EDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_0_S[] = {
+	 { "SCLK_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_1_S[] = {
+	 { "SCLK_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_STATUS_S[] = {
+	 { "SEQ0_ARB_CMD_FIFO_FULL", 4, 4, &umr_bitfield_default },
+	 { "SEQ0_ARB_DATA_FIFO_FULL", 0, 0, &umr_bitfield_default },
+	 { "SEQ0_RS_DATA_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "SEQ1_ARB_CMD_FIFO_FULL", 5, 5, &umr_bitfield_default },
+	 { "SEQ1_ARB_DATA_FIFO_FULL", 1, 1, &umr_bitfield_default },
+	 { "SEQ1_RS_DATA_FIFO_EMPTY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_DATAPORT[] = {
+	 { "DATA_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MPLL_OVERRIDE[] = {
+	 { "AD_PLL_RESET_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "ATGM_CLK_SEL_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_RESET_OVERRIDE", 1, 1, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_RESET_OVERRIDE", 2, 2, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_RESET_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_RESET_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "TEST_BYPASS_CLK_EN_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "TEST_BYPASS_CLK_SEL_OVERRIDE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CNTL[] = {
+	 { "ARB_REQCMD_WMK", 20, 23, &umr_bitfield_default },
+	 { "ARB_REQDAT_WMK", 24, 27, &umr_bitfield_default },
+	 { "ARB_RTDAT_WMK", 28, 31, &umr_bitfield_default },
+	 { "BANKGROUP_ENB", 18, 18, &umr_bitfield_default },
+	 { "BANKGROUP_SIZE", 17, 17, &umr_bitfield_default },
+	 { "CHANNEL_DISABLE", 8, 9, &umr_bitfield_default },
+	 { "DAT_INV", 6, 6, &umr_bitfield_default },
+	 { "MEM_ADDR_MAP_BANK", 2, 3, &umr_bitfield_default },
+	 { "MEM_ADDR_MAP_COLS", 0, 1, &umr_bitfield_default },
+	 { "MSK_DF1", 7, 7, &umr_bitfield_default },
+	 { "MSKOFF_DAT_TH", 15, 15, &umr_bitfield_default },
+	 { "MSKOFF_DAT_TL", 14, 14, &umr_bitfield_default },
+	 { "RET_HOLD_EOP", 16, 16, &umr_bitfield_default },
+	 { "RTR_OVERRIDE", 19, 19, &umr_bitfield_default },
+	 { "SAFE_MODE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM[] = {
+	 { "ADR_2CK", 0, 0, &umr_bitfield_default },
+	 { "ADR_DF1", 2, 2, &umr_bitfield_default },
+	 { "ADR_MUX", 1, 1, &umr_bitfield_default },
+	 { "AP8", 3, 3, &umr_bitfield_default },
+	 { "BO4", 14, 14, &umr_bitfield_default },
+	 { "CKE_ACT", 13, 13, &umr_bitfield_default },
+	 { "CKE_DYN", 12, 12, &umr_bitfield_default },
+	 { "DAT_DF1", 4, 4, &umr_bitfield_default },
+	 { "DAT_INV", 24, 24, &umr_bitfield_default },
+	 { "DLL_CLR", 15, 15, &umr_bitfield_default },
+	 { "DLL_CNT", 16, 23, &umr_bitfield_default },
+	 { "DQM_ACT", 7, 7, &umr_bitfield_default },
+	 { "DQM_DF1", 6, 6, &umr_bitfield_default },
+	 { "DQS_DF1", 5, 5, &umr_bitfield_default },
+	 { "INV_ACM", 25, 25, &umr_bitfield_default },
+	 { "ODT_ACT", 27, 27, &umr_bitfield_default },
+	 { "ODT_ENB", 26, 26, &umr_bitfield_default },
+	 { "RST_CTL", 28, 28, &umr_bitfield_default },
+	 { "STB_CNT", 8, 11, &umr_bitfield_default },
+	 { "TRI_CKE", 30, 30, &umr_bitfield_default },
+	 { "TRI_MIO_DYN", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM_2[] = {
+	 { "ADBI_ACT", 26, 26, &umr_bitfield_default },
+	 { "ADBI_DF1", 25, 25, &umr_bitfield_default },
+	 { "ADR_DBI_ACM", 2, 2, &umr_bitfield_default },
+	 { "ADR_DBI", 1, 1, &umr_bitfield_default },
+	 { "ADR_DDR", 0, 0, &umr_bitfield_default },
+	 { "BNK_MRS", 13, 13, &umr_bitfield_default },
+	 { "CMD_QDR", 3, 3, &umr_bitfield_default },
+	 { "CS_BY16", 31, 31, &umr_bitfield_default },
+	 { "DAT_QDR", 4, 4, &umr_bitfield_default },
+	 { "DBI_ACT", 28, 28, &umr_bitfield_default },
+	 { "DBI_DF1", 27, 27, &umr_bitfield_default },
+	 { "DBI_EDC_DF1", 29, 29, &umr_bitfield_default },
+	 { "DBI_OVR", 14, 14, &umr_bitfield_default },
+	 { "DLL_EST", 12, 12, &umr_bitfield_default },
+	 { "DQM_EST", 7, 7, &umr_bitfield_default },
+	 { "PCH_BNK", 24, 24, &umr_bitfield_default },
+	 { "PLL_CLR", 11, 11, &umr_bitfield_default },
+	 { "PLL_CNT", 16, 23, &umr_bitfield_default },
+	 { "PLL_EST", 10, 10, &umr_bitfield_default },
+	 { "RDAT_EDC", 6, 6, &umr_bitfield_default },
+	 { "RD_DQS", 8, 8, &umr_bitfield_default },
+	 { "TESTCHIP_EN", 30, 30, &umr_bitfield_default },
+	 { "TRI_CLK", 15, 15, &umr_bitfield_default },
+	 { "WDAT_EDC", 5, 5, &umr_bitfield_default },
+	 { "WR_DQS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RAS_TIMING[] = {
+	 { "TRCDRA", 15, 19, &umr_bitfield_default },
+	 { "TRCDR", 10, 14, &umr_bitfield_default },
+	 { "TRCDWA", 5, 9, &umr_bitfield_default },
+	 { "TRCDW", 0, 4, &umr_bitfield_default },
+	 { "TRC", 24, 30, &umr_bitfield_default },
+	 { "TRRD", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CAS_TIMING[] = {
+	 { "TCCDL", 9, 11, &umr_bitfield_default },
+	 { "TCL", 24, 28, &umr_bitfield_default },
+	 { "TNOPR", 2, 3, &umr_bitfield_default },
+	 { "TNOPW", 0, 1, &umr_bitfield_default },
+	 { "TR2R", 12, 15, &umr_bitfield_default },
+	 { "TR2W", 4, 8, &umr_bitfield_default },
+	 { "TW2R", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING[] = {
+	 { "TRFC", 20, 28, &umr_bitfield_default },
+	 { "TRP", 15, 19, &umr_bitfield_default },
+	 { "TRP_RDA", 8, 13, &umr_bitfield_default },
+	 { "TRP_WRA", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING2[] = {
+	 { "FAW", 8, 12, &umr_bitfield_default },
+	 { "PA2RDATA", 0, 2, &umr_bitfield_default },
+	 { "PA2WDATA", 4, 6, &umr_bitfield_default },
+	 { "T32AW", 21, 24, &umr_bitfield_default },
+	 { "TREDC", 13, 15, &umr_bitfield_default },
+	 { "TWDATATR", 28, 31, &umr_bitfield_default },
+	 { "TWEDC", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_TIMING[] = {
+	 { "SEQ_IDLE", 18, 20, &umr_bitfield_default },
+	 { "SEQ_IDLE_SS", 24, 31, &umr_bitfield_default },
+	 { "TCKE", 12, 17, &umr_bitfield_default },
+	 { "TCKE_PULSE", 8, 11, &umr_bitfield_default },
+	 { "TCKE_PULSE_MSB", 23, 23, &umr_bitfield_default },
+	 { "TCKSRE", 0, 2, &umr_bitfield_default },
+	 { "TCKSRX", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D0[] = {
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D1[] = {
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D0[] = {
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D1[] = {
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CMD[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "CHAN0", 24, 24, &umr_bitfield_default },
+	 { "CHAN1", 25, 25, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_CNTL[] = {
+	 { "BKPT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "FAST_WRITE", 6, 6, &umr_bitfield_default },
+	 { "PGM_CHKSUM", 23, 31, &umr_bitfield_default },
+	 { "PGM_READ", 5, 5, &umr_bitfield_default },
+	 { "PGM_WRITE", 4, 4, &umr_bitfield_default },
+	 { "RESET_PC", 3, 3, &umr_bitfield_default },
+	 { "RUN", 0, 0, &umr_bitfield_default },
+	 { "SINGLE_STEP", 1, 1, &umr_bitfield_default },
+	 { "SW_WAKE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_PGM[] = {
+	 { "CNTL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_AUTO_CMD[] = {
+	 { "ADR", 0, 16, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_AUTO_CFG[] = {
+	 { "DLL_CNT", 24, 31, &umr_bitfield_default },
+	 { "EXIT_ALLOW_STOP", 11, 11, &umr_bitfield_default },
+	 { "MRS_WAIT_CNT", 16, 19, &umr_bitfield_default },
+	 { "PREA_SRX", 13, 13, &umr_bitfield_default },
+	 { "RFS_SRX", 12, 12, &umr_bitfield_default },
+	 { "RST_MRS", 1, 1, &umr_bitfield_default },
+	 { "RXPDNB", 22, 22, &umr_bitfield_default },
+	 { "SCDS_MODE", 10, 10, &umr_bitfield_default },
+	 { "SELFREFR_COMMIT_0", 15, 15, &umr_bitfield_default },
+	 { "SELFREFR_COMMIT_1", 23, 23, &umr_bitfield_default },
+	 { "SS_ALWAYS_SLF", 8, 8, &umr_bitfield_default },
+	 { "SS_S_SLF", 9, 9, &umr_bitfield_default },
+	 { "STUTTER_EN", 14, 14, &umr_bitfield_default },
+	 { "SYC_CLK", 0, 0, &umr_bitfield_default },
+	 { "TRI_MIO", 2, 2, &umr_bitfield_default },
+	 { "WRITE_DURING_DLOCK", 20, 20, &umr_bitfield_default },
+	 { "XSR_TMR", 4, 7, &umr_bitfield_default },
+	 { "YCLK_ON", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_CNTL[] = {
+	 { "CAL_PWRON", 31, 31, &umr_bitfield_default },
+	 { "CAL_VREF", 16, 22, &umr_bitfield_default },
+	 { "CAL_VREFMODE", 6, 6, &umr_bitfield_default },
+	 { "CAL_VREF_SEL", 5, 5, &umr_bitfield_default },
+	 { "CAL_WHEN_IDLE", 29, 29, &umr_bitfield_default },
+	 { "CAL_WHEN_REFRESH", 30, 30, &umr_bitfield_default },
+	 { "CLEAR_TIMEOUT_ERR", 9, 9, &umr_bitfield_default },
+	 { "MEM_IO_SAMPLE_CNT", 13, 15, &umr_bitfield_default },
+	 { "MEM_IO_UPDATE_RATE", 0, 4, &umr_bitfield_default },
+	 { "TIMEOUT_ERR", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_DEBUG[] = {
+	 { "DEBUG_CAL_DONE", 31, 31, &umr_bitfield_default },
+	 { "DEBUG_CAL_EN", 28, 28, &umr_bitfield_default },
+	 { "DEBUG_CAL_INTR", 30, 30, &umr_bitfield_default },
+	 { "DEBUG_CAL_START", 29, 29, &umr_bitfield_default },
+	 { "PMVCAL_RESERVED", 16, 27, &umr_bitfield_default },
+	 { "TIMEOUT_CNTR", 8, 15, &umr_bitfield_default },
+	 { "TSTARTUP_CNTR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_STATUS[] = {
+	 { "NSTR_ACCUM_VAL", 24, 31, &umr_bitfield_default },
+	 { "NSTR_CAL", 16, 23, &umr_bitfield_default },
+	 { "PSTR_ACCUM_VAL", 8, 15, &umr_bitfield_default },
+	 { "PSTR_CAL", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WCDR_CTRL[] = {
+	 { "AREF_EN", 14, 14, &umr_bitfield_default },
+	 { "PRBS_EN", 20, 20, &umr_bitfield_default },
+	 { "PRBS_RST", 21, 21, &umr_bitfield_default },
+	 { "PREAMBLE", 24, 27, &umr_bitfield_default },
+	 { "PRE_MASK", 28, 31, &umr_bitfield_default },
+	 { "RD_EN", 13, 13, &umr_bitfield_default },
+	 { "TRAIN_EN", 15, 15, &umr_bitfield_default },
+	 { "TWCDRL", 16, 19, &umr_bitfield_default },
+	 { "WCDR_PRE", 0, 7, &umr_bitfield_default },
+	 { "WCDR_TIM", 8, 11, &umr_bitfield_default },
+	 { "WR_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_CNTL[] = {
+	 { "AUTO_REFRESH_ADDR_TRAIN", 8, 8, &umr_bitfield_default },
+	 { "AUTO_REFRESH_READ_TRAIN", 10, 10, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WAKEUP_EARLY", 20, 20, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WCK_TRAIN", 9, 9, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WRITE_TRAIN", 11, 11, &umr_bitfield_default },
+	 { "BLOCK_ARB_RD_D0", 24, 24, &umr_bitfield_default },
+	 { "BLOCK_ARB_RD_D1", 26, 26, &umr_bitfield_default },
+	 { "BLOCK_ARB_WR_D0", 25, 25, &umr_bitfield_default },
+	 { "BLOCK_ARB_WR_D1", 27, 27, &umr_bitfield_default },
+	 { "BOOT_UP_ADDR_TRAIN", 0, 0, &umr_bitfield_default },
+	 { "BOOT_UP_READ_TRAIN", 2, 2, &umr_bitfield_default },
+	 { "BOOT_UP_WCK_TRAIN", 1, 1, &umr_bitfield_default },
+	 { "BOOT_UP_WRITE_TRAIN", 3, 3, &umr_bitfield_default },
+	 { "DISP_ASTOP_WAKEUP", 29, 29, &umr_bitfield_default },
+	 { "READ_ECC_ADDR_TRAIN", 16, 16, &umr_bitfield_default },
+	 { "READ_ECC_READ_TRAIN", 18, 18, &umr_bitfield_default },
+	 { "READ_ECC_WCK_TRAIN", 17, 17, &umr_bitfield_default },
+	 { "READ_ECC_WRITE_TRAIN", 19, 19, &umr_bitfield_default },
+	 { "SELF_REFRESH_ADDR_TRAIN", 4, 4, &umr_bitfield_default },
+	 { "SELF_REFRESH_READ_TRAIN", 6, 6, &umr_bitfield_default },
+	 { "SELF_REFRESH_WCK_TRAIN", 5, 5, &umr_bitfield_default },
+	 { "SELF_REFRESH_WRITE_TRAIN", 7, 7, &umr_bitfield_default },
+	 { "STOP_WCK_D0", 21, 21, &umr_bitfield_default },
+	 { "STOP_WCK_D1", 22, 22, &umr_bitfield_default },
+	 { "SW_WAKEUP", 28, 28, &umr_bitfield_default },
+	 { "TRAIN_DONE_D0", 30, 30, &umr_bitfield_default },
+	 { "TRAIN_DONE_D1", 31, 31, &umr_bitfield_default },
+	 { "WRITE_ECC_ADDR_TRAIN", 12, 12, &umr_bitfield_default },
+	 { "WRITE_ECC_READ_TRAIN", 14, 14, &umr_bitfield_default },
+	 { "WRITE_ECC_WCK_TRAIN", 13, 13, &umr_bitfield_default },
+	 { "WRITE_ECC_WRITE_TRAIN", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD[] = {
+	 { "READ_EDC_THRESHOLD", 16, 31, &umr_bitfield_default },
+	 { "WRITE_EDC_THRESHOLD", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_EDGE[] = {
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_MASK[] = {
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_CAPTURE[] = {
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_CLEAR[] = {
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "CLEARALL", 16, 16, &umr_bitfield_default },
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_TIMING[] = {
+	 { "TARF2T", 5, 9, &umr_bitfield_default },
+	 { "TLD2LD", 15, 19, &umr_bitfield_default },
+	 { "TT2ROW", 10, 14, &umr_bitfield_default },
+	 { "TWT2RT", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDCCDR_R_D0[] = {
+	 { "EDC0", 0, 7, &umr_bitfield_default },
+	 { "EDC1", 8, 15, &umr_bitfield_default },
+	 { "EDC2", 16, 23, &umr_bitfield_default },
+	 { "EDC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDCCDR_R_D1[] = {
+	 { "EDC0", 0, 7, &umr_bitfield_default },
+	 { "EDC1", 8, 15, &umr_bitfield_default },
+	 { "EDC2", 16, 23, &umr_bitfield_default },
+	 { "EDC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_0_D0[] = {
+	 { "DQ_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_1_D0[] = {
+	 { "DBI_STATUS", 0, 3, &umr_bitfield_default },
+	 { "EDC_STATUS", 4, 7, &umr_bitfield_default },
+	 { "PMA_PRBSCLR", 28, 28, &umr_bitfield_default },
+	 { "PMD0_PRBSCLR", 29, 29, &umr_bitfield_default },
+	 { "PMD1_PRBSCLR", 30, 30, &umr_bitfield_default },
+	 { "WCDR_STATUS", 12, 15, &umr_bitfield_default },
+	 { "WCK_STATUS", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDC_STATUS_D0[] = {
+	 { "REDC_CNT", 16, 31, &umr_bitfield_default },
+	 { "WEDC_CNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_0_D1[] = {
+	 { "DQ_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_1_D1[] = {
+	 { "DBI_STATUS", 0, 3, &umr_bitfield_default },
+	 { "EDC_STATUS", 4, 7, &umr_bitfield_default },
+	 { "PMA_PRBSCLR", 28, 28, &umr_bitfield_default },
+	 { "PMD0_PRBSCLR", 29, 29, &umr_bitfield_default },
+	 { "PMD1_PRBSCLR", 30, 30, &umr_bitfield_default },
+	 { "WCDR_STATUS", 12, 15, &umr_bitfield_default },
+	 { "WCK_STATUS", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDC_STATUS_D1[] = {
+	 { "REDC_CNT", 16, 31, &umr_bitfield_default },
+	 { "WEDC_CNT", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY0_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY1_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_APHY_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "CKE_BIT", 30, 30, &umr_bitfield_default },
+	 { "CKE_SEL", 31, 31, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "NDRV", 20, 22, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "PMA_LOOPBACK", 13, 15, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXBPASS_SEL", 12, 12, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 27, 29, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "TXRESET", 25, 25, &umr_bitfield_default },
+	 { "YCLKON", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY0_D0[] = {
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY1_D0[] = {
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_DPHY_STR_CNTL_D0[] = {
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_D_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_S_STR", 29, 29, &umr_bitfield_default },
+	 { "NSTR_OFF_D", 6, 11, &umr_bitfield_default },
+	 { "NSTR_OFF_S", 18, 23, &umr_bitfield_default },
+	 { "PSTR_OFF_D", 0, 5, &umr_bitfield_default },
+	 { "PSTR_OFF_S", 12, 17, &umr_bitfield_default },
+	 { "USE_D_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_S_CAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY0_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY1_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_APHY_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "CKE_BIT", 30, 30, &umr_bitfield_default },
+	 { "CKE_SEL", 31, 31, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "NDRV", 20, 22, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "PMA_LOOPBACK", 13, 15, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXBPASS_SEL", 12, 12, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 27, 29, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "TXRESET", 25, 25, &umr_bitfield_default },
+	 { "YCLKON", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY0_D1[] = {
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY1_D1[] = {
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_DPHY_STR_CNTL_D1[] = {
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_D_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_S_STR", 29, 29, &umr_bitfield_default },
+	 { "NSTR_OFF_D", 6, 11, &umr_bitfield_default },
+	 { "NSTR_OFF_S", 18, 23, &umr_bitfield_default },
+	 { "PSTR_OFF_D", 0, 5, &umr_bitfield_default },
+	 { "PSTR_OFF_S", 12, 17, &umr_bitfield_default },
+	 { "USE_D_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_S_CAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL_D0[] = {
+	 { "DQRXCDREN_B0", 22, 22, &umr_bitfield_default },
+	 { "DQRXCDREN_B1", 23, 23, &umr_bitfield_default },
+	 { "DQRXSEL_B0", 28, 28, &umr_bitfield_default },
+	 { "DQRXSEL_B1", 29, 29, &umr_bitfield_default },
+	 { "DQTXCDREN_B0", 20, 20, &umr_bitfield_default },
+	 { "DQTXCDREN_B1", 21, 21, &umr_bitfield_default },
+	 { "DQTXSEL_B0", 30, 30, &umr_bitfield_default },
+	 { "DQTXSEL_B1", 31, 31, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B01", 10, 10, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B23", 11, 11, &umr_bitfield_default },
+	 { "RXCDREN_B01", 8, 8, &umr_bitfield_default },
+	 { "RXCDREN_B23", 9, 9, &umr_bitfield_default },
+	 { "RXPHASE1_B01", 12, 15, &umr_bitfield_default },
+	 { "RXPHASE1_B23", 16, 19, &umr_bitfield_default },
+	 { "RXPHASE_B01", 0, 3, &umr_bitfield_default },
+	 { "RXPHASE_B23", 4, 7, &umr_bitfield_default },
+	 { "WCDREDC_B0", 26, 26, &umr_bitfield_default },
+	 { "WCDREDC_B1", 27, 27, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B0", 24, 24, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL_D1[] = {
+	 { "DQRXCDREN_B0", 22, 22, &umr_bitfield_default },
+	 { "DQRXCDREN_B1", 23, 23, &umr_bitfield_default },
+	 { "DQRXSEL_B0", 28, 28, &umr_bitfield_default },
+	 { "DQRXSEL_B1", 29, 29, &umr_bitfield_default },
+	 { "DQTXCDREN_B0", 20, 20, &umr_bitfield_default },
+	 { "DQTXCDREN_B1", 21, 21, &umr_bitfield_default },
+	 { "DQTXSEL_B0", 30, 30, &umr_bitfield_default },
+	 { "DQTXSEL_B1", 31, 31, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B01", 10, 10, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B23", 11, 11, &umr_bitfield_default },
+	 { "RXCDREN_B01", 8, 8, &umr_bitfield_default },
+	 { "RXCDREN_B23", 9, 9, &umr_bitfield_default },
+	 { "RXPHASE1_B01", 12, 15, &umr_bitfield_default },
+	 { "RXPHASE1_B23", 16, 19, &umr_bitfield_default },
+	 { "RXPHASE_B01", 0, 3, &umr_bitfield_default },
+	 { "RXPHASE_B23", 4, 7, &umr_bitfield_default },
+	 { "WCDREDC_B0", 26, 26, &umr_bitfield_default },
+	 { "WCDREDC_B1", 27, 27, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B0", 24, 24, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_FIFO_CTL[] = {
+	 { "CG_DIS_D0", 8, 8, &umr_bitfield_default },
+	 { "CG_DIS_D1", 9, 9, &umr_bitfield_default },
+	 { "R_LD_INIT", 4, 5, &umr_bitfield_default },
+	 { "R_SYC_SEL", 6, 7, &umr_bitfield_default },
+	 { "SYC_DLY", 12, 14, &umr_bitfield_default },
+	 { "W_ASYC_EXT", 16, 17, &umr_bitfield_default },
+	 { "W_DSYC_EXT", 18, 19, &umr_bitfield_default },
+	 { "W_LD_INIT_D0", 0, 1, &umr_bitfield_default },
+	 { "W_LD_INIT_D1", 10, 11, &umr_bitfield_default },
+	 { "W_SYC_SEL", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE0_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE1_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE2_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE3_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_DBI_D0[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_EDC_D0[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_FCK_D0[] = {
+	 { "FCK0", 0, 3, &umr_bitfield_default },
+	 { "FCK1", 4, 7, &umr_bitfield_default },
+	 { "FCK2", 8, 11, &umr_bitfield_default },
+	 { "FCK3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC8[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE0_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE1_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE2_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE3_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_DBI_D1[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_EDC_D1[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_FCK_D1[] = {
+	 { "FCK0", 0, 3, &umr_bitfield_default },
+	 { "FCK1", 4, 7, &umr_bitfield_default },
+	 { "FCK2", 8, 11, &umr_bitfield_default },
+	 { "FCK3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE0_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE1_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE2_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE3_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_DBI_D0[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_EDC_D0[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE0_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE1_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE2_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE3_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_DBI_D1[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_EDC_D1[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL[] = {
+	 { "ATBEN", 24, 29, &umr_bitfield_default },
+	 { "ATBSEL_D0", 31, 31, &umr_bitfield_default },
+	 { "ATBSEL_D1", 30, 30, &umr_bitfield_default },
+	 { "ATBSEL", 20, 23, &umr_bitfield_default },
+	 { "MEM_IO_IMP_MAX", 8, 15, &umr_bitfield_default },
+	 { "MEM_IO_IMP_MIN", 0, 7, &umr_bitfield_default },
+	 { "OVL_YCLKON_D0", 18, 18, &umr_bitfield_default },
+	 { "OVL_YCLKON_D1", 19, 19, &umr_bitfield_default },
+	 { "RXPHASE_GRAY", 17, 17, &umr_bitfield_default },
+	 { "TXPHASE_GRAY", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL_D0[] = {
+	 { "CK_AUTO_EN", 20, 20, &umr_bitfield_default },
+	 { "CK_DELAY_N", 22, 23, &umr_bitfield_default },
+	 { "CK_DELAY_P", 24, 25, &umr_bitfield_default },
+	 { "CK_DELAY_SEL", 21, 21, &umr_bitfield_default },
+	 { "DELAY_ADR_SYNC", 4, 4, &umr_bitfield_default },
+	 { "DELAY_CLK_SYNC", 2, 2, &umr_bitfield_default },
+	 { "DELAY_CMD_SYNC", 3, 3, &umr_bitfield_default },
+	 { "DIFF_STR", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_ADR", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_CMD", 12, 12, &umr_bitfield_default },
+	 { "EN_RD_STR_DLY", 11, 11, &umr_bitfield_default },
+	 { "FORCE_EN_RD_STR", 10, 10, &umr_bitfield_default },
+	 { "GDDR_PWRON", 30, 30, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_ADR", 9, 9, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CLK", 7, 7, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CMD", 8, 8, &umr_bitfield_default },
+	 { "TXPWROFF_CKE", 27, 27, &umr_bitfield_default },
+	 { "TXPWROFF_CLK", 31, 31, &umr_bitfield_default },
+	 { "UNI_STR", 28, 28, &umr_bitfield_default },
+	 { "VREFI_EN", 14, 14, &umr_bitfield_default },
+	 { "VREFI_SEL", 15, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL_D1[] = {
+	 { "CK_AUTO_EN", 20, 20, &umr_bitfield_default },
+	 { "CK_DELAY_N", 22, 23, &umr_bitfield_default },
+	 { "CK_DELAY_P", 24, 25, &umr_bitfield_default },
+	 { "CK_DELAY_SEL", 21, 21, &umr_bitfield_default },
+	 { "DELAY_ADR_SYNC", 4, 4, &umr_bitfield_default },
+	 { "DELAY_CLK_SYNC", 2, 2, &umr_bitfield_default },
+	 { "DELAY_CMD_SYNC", 3, 3, &umr_bitfield_default },
+	 { "DELAY_DATA_SYNC", 0, 0, &umr_bitfield_default },
+	 { "DELAY_STR_SYNC", 1, 1, &umr_bitfield_default },
+	 { "DIFF_STR", 29, 29, &umr_bitfield_default },
+	 { "DISABLE_ADR", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_CMD", 12, 12, &umr_bitfield_default },
+	 { "EN_RD_STR_DLY", 11, 11, &umr_bitfield_default },
+	 { "FORCE_EN_RD_STR", 10, 10, &umr_bitfield_default },
+	 { "GDDR_PWRON", 30, 30, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_ADR", 9, 9, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CLK", 7, 7, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CMD", 8, 8, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_DATA", 5, 5, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_STR", 6, 6, &umr_bitfield_default },
+	 { "TXPWROFF_CKE", 27, 27, &umr_bitfield_default },
+	 { "TXPWROFF_CLK", 31, 31, &umr_bitfield_default },
+	 { "UNI_STR", 28, 28, &umr_bitfield_default },
+	 { "VREFI_EN", 14, 14, &umr_bitfield_default },
+	 { "VREFI_SEL", 15, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_NPL_STATUS[] = {
+	 { "D0_NDELAY", 2, 3, &umr_bitfield_default },
+	 { "D0_NEARLY", 5, 5, &umr_bitfield_default },
+	 { "D0_PDELAY", 0, 1, &umr_bitfield_default },
+	 { "D0_PEARLY", 4, 4, &umr_bitfield_default },
+	 { "D1_NDELAY", 8, 9, &umr_bitfield_default },
+	 { "D1_NEARLY", 11, 11, &umr_bitfield_default },
+	 { "D1_PDELAY", 6, 7, &umr_bitfield_default },
+	 { "D1_PEARLY", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_CNTL[] = {
+	 { "CNTL", 30, 31, &umr_bitfield_default },
+	 { "MONITOR_PERIOD", 0, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CTL[] = {
+	 { "SEL_A", 0, 3, &umr_bitfield_default },
+	 { "SEL_B", 4, 7, &umr_bitfield_default },
+	 { "SEL_CH0_C", 8, 11, &umr_bitfield_default },
+	 { "SEL_CH0_D", 12, 15, &umr_bitfield_default },
+	 { "SEL_CH1_A", 16, 19, &umr_bitfield_default },
+	 { "SEL_CH1_B", 20, 23, &umr_bitfield_default },
+	 { "SEL_CH1_C", 24, 27, &umr_bitfield_default },
+	 { "SEL_CH1_D", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_A_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_A_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_B_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_B_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_STATUS_M[] = {
+	 { "CMD_RDY_D0", 2, 2, &umr_bitfield_default },
+	 { "CMD_RDY_D1", 3, 3, &umr_bitfield_default },
+	 { "PMG_FSMSTATE", 20, 24, &umr_bitfield_default },
+	 { "PMG_PWRSTATE", 16, 16, &umr_bitfield_default },
+	 { "PWRUP_COMPL_D0", 0, 0, &umr_bitfield_default },
+	 { "PWRUP_COMPL_D1", 1, 1, &umr_bitfield_default },
+	 { "SEQ0_ARB_CMD_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "SEQ0_BUSY_HYS", 25, 25, &umr_bitfield_default },
+	 { "SEQ0_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SEQ0_RS_DATA_FIFO_FULL", 12, 12, &umr_bitfield_default },
+	 { "SEQ1_ARB_CMD_FIFO_EMPTY", 9, 9, &umr_bitfield_default },
+	 { "SEQ1_BUSY_HYS", 26, 26, &umr_bitfield_default },
+	 { "SEQ1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "SEQ1_RS_DATA_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "SLF_D0", 4, 4, &umr_bitfield_default },
+	 { "SLF_D1", 5, 5, &umr_bitfield_default },
+	 { "SS_SLF_D0", 6, 6, &umr_bitfield_default },
+	 { "SS_SLF_D1", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_VENDOR_ID_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_VENDOR_ID_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_M[] = {
+	 { "MCLK_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_EMRS[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CFG[] = {
+	 { "DPM_WAKE", 10, 10, &umr_bitfield_default },
+	 { "EARLY_ACK_ACPI", 22, 22, &umr_bitfield_default },
+	 { "MRS_WAIT_CNT", 16, 19, &umr_bitfield_default },
+	 { "PREA_SRX", 13, 13, &umr_bitfield_default },
+	 { "RFS_SRX", 12, 12, &umr_bitfield_default },
+	 { "RST_EMRS", 2, 2, &umr_bitfield_default },
+	 { "RST_MRS1", 8, 8, &umr_bitfield_default },
+	 { "RST_MRS2", 9, 9, &umr_bitfield_default },
+	 { "RST_MRS", 1, 1, &umr_bitfield_default },
+	 { "RXPDNB", 25, 25, &umr_bitfield_default },
+	 { "SYC_CLK", 0, 0, &umr_bitfield_default },
+	 { "TRI_MIO", 3, 3, &umr_bitfield_default },
+	 { "WRITE_DURING_DLOCK", 20, 20, &umr_bitfield_default },
+	 { "XSR_TMR", 4, 7, &umr_bitfield_default },
+	 { "YCLK_ON", 21, 21, &umr_bitfield_default },
+	 { "ZQCL_SEND", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP2_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP3_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_IR_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_DEC_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_PGM_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_R_PGM[] = {
+	 { "PGM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC3[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC4[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMP_CNTL[] = {
+	 { "CMP", 16, 17, &umr_bitfield_default },
+	 { "CMP_MASK_BIT", 4, 11, &umr_bitfield_default },
+	 { "CMP_MASK_BYTE", 0, 3, &umr_bitfield_default },
+	 { "DATA_STORE_MODE", 20, 21, &umr_bitfield_default },
+	 { "DATA_STORE_SEL", 13, 13, &umr_bitfield_default },
+	 { "DAT_MODE", 18, 18, &umr_bitfield_default },
+	 { "EDC_STORE_MODE", 19, 19, &umr_bitfield_default },
+	 { "EDC_STORE_SEL", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_CMD_FIFO", 15, 15, &umr_bitfield_default },
+	 { "LOAD_RTEDC", 12, 12, &umr_bitfield_default },
+	 { "MISMATCH_CNT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMD_CNTL[] = {
+	 { "CMD_ISSUE_LOOP", 2, 2, &umr_bitfield_default },
+	 { "CMD_ISSUE_MODE", 1, 1, &umr_bitfield_default },
+	 { "CMD_ISSUE_MODE_U", 16, 16, &umr_bitfield_default },
+	 { "CMD_ISSUE_RUN", 17, 17, &umr_bitfield_default },
+	 { "DONE", 31, 31, &umr_bitfield_default },
+	 { "ENABLE_D0", 28, 28, &umr_bitfield_default },
+	 { "ENABLE_D1", 29, 29, &umr_bitfield_default },
+	 { "LOOP_CNT_MAX", 4, 15, &umr_bitfield_default },
+	 { "LOOP_CNT_RD", 18, 27, &umr_bitfield_default },
+	 { "LOOP_END_CONDITION", 3, 3, &umr_bitfield_default },
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "STATUS_CH", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP0_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP1_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_DEBUG_INDEX[] = {
+	 { "IO_DEBUG_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_DEBUG_DATA[] = {
+	 { "IO_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BYTE_REMAP_D0[] = {
+	 { "BYTE0", 0, 1, &umr_bitfield_default },
+	 { "BYTE1", 2, 3, &umr_bitfield_default },
+	 { "BYTE2", 4, 5, &umr_bitfield_default },
+	 { "BYTE3", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BYTE_REMAP_D1[] = {
+	 { "BYTE0", 0, 1, &umr_bitfield_default },
+	 { "BYTE1", 2, 3, &umr_bitfield_default },
+	 { "BYTE2", 4, 5, &umr_bitfield_default },
+	 { "BYTE3", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC5[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC6[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_APHY_STR_CNTL_D0[] = {
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_A_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_D_RD_STR", 29, 29, &umr_bitfield_default },
+	 { "NSTR_OFF_A", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_A", 0, 5, &umr_bitfield_default },
+	 { "PSTR_OFF_D_RD", 12, 17, &umr_bitfield_default },
+	 { "USE_A_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_D_RD_CAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_APHY_STR_CNTL_D1[] = {
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_A_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_D_RD_STR", 29, 29, &umr_bitfield_default },
+	 { "NSTR_OFF_A", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_A", 0, 5, &umr_bitfield_default },
+	 { "PSTR_OFF_D_RD", 12, 17, &umr_bitfield_default },
+	 { "USE_A_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_D_RD_CAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC7[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CG[] = {
+	 { "CG_SEQ_REQ", 0, 7, &umr_bitfield_default },
+	 { "CG_SEQ_RESP", 8, 15, &umr_bitfield_default },
+	 { "SEQ_CG_REQ", 16, 23, &umr_bitfield_default },
+	 { "SEQ_CG_RESP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RAS_TIMING_LP[] = {
+	 { "TRCDRA", 15, 19, &umr_bitfield_default },
+	 { "TRCDR", 10, 14, &umr_bitfield_default },
+	 { "TRCDWA", 5, 9, &umr_bitfield_default },
+	 { "TRCDW", 0, 4, &umr_bitfield_default },
+	 { "TRC", 24, 30, &umr_bitfield_default },
+	 { "TRRD", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CAS_TIMING_LP[] = {
+	 { "TCCDL", 9, 11, &umr_bitfield_default },
+	 { "TCL", 24, 28, &umr_bitfield_default },
+	 { "TNOPR", 2, 3, &umr_bitfield_default },
+	 { "TNOPW", 0, 1, &umr_bitfield_default },
+	 { "TR2R", 12, 15, &umr_bitfield_default },
+	 { "TR2W", 4, 8, &umr_bitfield_default },
+	 { "TW2R", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING_LP[] = {
+	 { "TRFC", 20, 28, &umr_bitfield_default },
+	 { "TRP", 15, 19, &umr_bitfield_default },
+	 { "TRP_RDA", 8, 13, &umr_bitfield_default },
+	 { "TRP_WRA", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING2_LP[] = {
+	 { "FAW", 8, 12, &umr_bitfield_default },
+	 { "PA2RDATA", 0, 2, &umr_bitfield_default },
+	 { "PA2WDATA", 4, 6, &umr_bitfield_default },
+	 { "TADR", 21, 23, &umr_bitfield_default },
+	 { "TFCKTR", 24, 27, &umr_bitfield_default },
+	 { "TREDC", 13, 15, &umr_bitfield_default },
+	 { "TWDATATR", 28, 31, &umr_bitfield_default },
+	 { "TWEDC", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D0_LP[] = {
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D1_LP[] = {
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_EMRS_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B0_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B1_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B2_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B3_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B0_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B1_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B2_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B3_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD0[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD1[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD2[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD3[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD4[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD5[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD6[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD7[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RDBI[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_REDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMP_CNTL_2[] = {
+	 { "DATA_STORE_CNT", 0, 4, &umr_bitfield_default },
+	 { "DATA_STORE_CNT_RST", 8, 8, &umr_bitfield_default },
+	 { "EDC_STORE_CNT", 12, 16, &umr_bitfield_default },
+	 { "EDC_STORE_CNT_RST", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RESERVE_D0[] = {
+	 { "APHY_RSV", 24, 31, &umr_bitfield_default },
+	 { "DPHY0_RSV", 0, 11, &umr_bitfield_default },
+	 { "DPHY1_RSV", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RESERVE_D1[] = {
+	 { "APHY_RSV", 24, 31, &umr_bitfield_default },
+	 { "DPHY0_RSV", 0, 11, &umr_bitfield_default },
+	 { "DPHY1_RSV", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_HWCNTL[] = {
+	 { "ACAO", 18, 18, &umr_bitfield_default },
+	 { "AC_DLY", 8, 9, &umr_bitfield_default },
+	 { "D_DLY", 6, 7, &umr_bitfield_default },
+	 { "G_DLY", 10, 13, &umr_bitfield_default },
+	 { "PWRGATE_EN", 0, 0, &umr_bitfield_default },
+	 { "RXAO", 17, 17, &umr_bitfield_default },
+	 { "STAGGER_EN", 1, 1, &umr_bitfield_default },
+	 { "TPGCG", 2, 5, &umr_bitfield_default },
+	 { "TXAO", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_SWCNTL_0[] = {
+	 { "GMCON_SR_COMMIT", 31, 31, &umr_bitfield_default },
+	 { "PMA0_AC_ENB", 16, 16, &umr_bitfield_default },
+	 { "PMD0_DBI_RX_ENB", 5, 5, &umr_bitfield_default },
+	 { "PMD0_DBI_TX_ENB", 1, 1, &umr_bitfield_default },
+	 { "PMD0_DQ_RX_ENB", 4, 4, &umr_bitfield_default },
+	 { "PMD0_DQ_TX_ENB", 0, 0, &umr_bitfield_default },
+	 { "PMD0_EDC_RX_ENB", 6, 6, &umr_bitfield_default },
+	 { "PMD0_EDC_TX_ENB", 2, 2, &umr_bitfield_default },
+	 { "PMD0_WCLKX_RX_ENB", 7, 7, &umr_bitfield_default },
+	 { "PMD0_WCLKX_TX_ENB", 3, 3, &umr_bitfield_default },
+	 { "PMD1_DBI_RX_ENB", 13, 13, &umr_bitfield_default },
+	 { "PMD1_DBI_TX_ENB", 9, 9, &umr_bitfield_default },
+	 { "PMD1_DQ_RX_ENB", 12, 12, &umr_bitfield_default },
+	 { "PMD1_DQ_TX_ENB", 8, 8, &umr_bitfield_default },
+	 { "PMD1_EDC_RX_ENB", 14, 14, &umr_bitfield_default },
+	 { "PMD1_EDC_TX_ENB", 10, 10, &umr_bitfield_default },
+	 { "PMD1_WCLKX_RX_ENB", 15, 15, &umr_bitfield_default },
+	 { "PMD1_WCLKX_TX_ENB", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_SWCNTL_1[] = {
+	 { "GMCON_SR_COMMIT", 31, 31, &umr_bitfield_default },
+	 { "PMA1_AC_ENB", 16, 16, &umr_bitfield_default },
+	 { "PMD2_DBI_RX_ENB", 5, 5, &umr_bitfield_default },
+	 { "PMD2_DBI_TX_ENB", 1, 1, &umr_bitfield_default },
+	 { "PMD2_DQ_RX_ENB", 4, 4, &umr_bitfield_default },
+	 { "PMD2_DQ_TX_ENB", 0, 0, &umr_bitfield_default },
+	 { "PMD2_EDC_RX_ENB", 6, 6, &umr_bitfield_default },
+	 { "PMD2_EDC_TX_ENB", 2, 2, &umr_bitfield_default },
+	 { "PMD2_WCLKX_RX_ENB", 7, 7, &umr_bitfield_default },
+	 { "PMD2_WCLKX_TX_ENB", 3, 3, &umr_bitfield_default },
+	 { "PMD3_DBI_RX_ENB", 13, 13, &umr_bitfield_default },
+	 { "PMD3_DBI_TX_ENB", 9, 9, &umr_bitfield_default },
+	 { "PMD3_DQ_RX_ENB", 12, 12, &umr_bitfield_default },
+	 { "PMD3_DQ_TX_ENB", 8, 8, &umr_bitfield_default },
+	 { "PMD3_EDC_RX_ENB", 14, 14, &umr_bitfield_default },
+	 { "PMD3_EDC_TX_ENB", 10, 10, &umr_bitfield_default },
+	 { "PMD3_WCLKX_RX_ENB", 15, 15, &umr_bitfield_default },
+	 { "PMD3_WCLKX_TX_ENB", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_DQ_STATUS[] = {
+	 { "CH0_DQ_NSTR", 8, 15, &umr_bitfield_default },
+	 { "CH0_DQ_PSTR", 0, 7, &umr_bitfield_default },
+	 { "CH1_DQ_NSTR", 24, 31, &umr_bitfield_default },
+	 { "CH1_DQ_PSTR", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TCG_CNTL[] = {
+	 { "AREF_BOTH", 26, 26, &umr_bitfield_default },
+	 { "AREF_LAST", 25, 25, &umr_bitfield_default },
+	 { "BURST_NUM", 19, 21, &umr_bitfield_default },
+	 { "DATA_CNT", 12, 15, &umr_bitfield_default },
+	 { "DONE", 31, 31, &umr_bitfield_default },
+	 { "ENABLE_D0", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_D1", 2, 2, &umr_bitfield_default },
+	 { "FRAME_TRAIN", 18, 18, &umr_bitfield_default },
+	 { "INFINITE_CMD", 7, 7, &umr_bitfield_default },
+	 { "ISSUE_AREF", 22, 22, &umr_bitfield_default },
+	 { "LOAD_FIFO", 16, 16, &umr_bitfield_default },
+	 { "MOP", 8, 11, &umr_bitfield_default },
+	 { "NFIFO", 4, 6, &umr_bitfield_default },
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "SHORT_LDFF", 17, 17, &umr_bitfield_default },
+	 { "START", 3, 3, &umr_bitfield_default },
+	 { "TXDBI_CNTL", 23, 23, &umr_bitfield_default },
+	 { "VPTR_MASK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_CTRL[] = {
+	 { "CAPTURE_START", 1, 1, &umr_bitfield_default },
+	 { "DIRECTION", 5, 5, &umr_bitfield_default },
+	 { "DONE", 2, 2, &umr_bitfield_default },
+	 { "ERR", 3, 3, &umr_bitfield_default },
+	 { "INVERT", 6, 6, &umr_bitfield_default },
+	 { "MASK_BITS", 7, 7, &umr_bitfield_default },
+	 { "POINTER", 16, 31, &umr_bitfield_default },
+	 { "ROT_INV", 10, 10, &umr_bitfield_default },
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "STEP", 4, 4, &umr_bitfield_default },
+	 { "UPDATE_LOOP", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_GCNT[] = {
+	 { "COMP_VALUE", 16, 31, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_OCNT[] = {
+	 { "CMP_VALUE", 16, 31, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_NCNT[] = {
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "NIBBLE_SKIP", 24, 27, &umr_bitfield_default },
+	 { "RANGE_HIGH", 20, 23, &umr_bitfield_default },
+	 { "RANGE_LOW", 16, 19, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_BCNT[] = {
+	 { "BCNT_TESTS", 8, 15, &umr_bitfield_default },
+	 { "COMP_VALUE", 16, 23, &umr_bitfield_default },
+	 { "DONE_TESTS", 24, 31, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_FLAG[] = {
+	 { "ERROR_TESTS", 24, 31, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "FLAG_TESTS", 8, 15, &umr_bitfield_default },
+	 { "NBBL_MASK", 16, 19, &umr_bitfield_default },
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_UPDATE[] = {
+	 { "AREF_COUNT", 16, 23, &umr_bitfield_default },
+	 { "CAPTR_TESTS", 24, 31, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "UPDT_TESTS", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_EDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DBI[] = {
+	 { "DBI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D0_LP[] = {
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D1_LP[] = {
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TIMER_WR[] = {
+	 { "COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TIMER_RD[] = {
+	 { "COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM_ERROR_INSERTION[] = {
+	 { "RX", 16, 31, &umr_bitfield_default },
+	 { "TX", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_D0[] = {
+	 { "RXC0_DLY", 0, 3, &umr_bitfield_default },
+	 { "RXC0_EXT", 4, 7, &umr_bitfield_default },
+	 { "RXC1_DLY", 8, 11, &umr_bitfield_default },
+	 { "RXC1_EXT", 12, 15, &umr_bitfield_default },
+	 { "TXC0_DLY", 16, 18, &umr_bitfield_default },
+	 { "TXC0_EXT", 20, 23, &umr_bitfield_default },
+	 { "TXC1_DLY", 24, 26, &umr_bitfield_default },
+	 { "TXC1_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_D1[] = {
+	 { "RXC0_DLY", 0, 3, &umr_bitfield_default },
+	 { "RXC0_EXT", 4, 7, &umr_bitfield_default },
+	 { "RXC1_DLY", 8, 11, &umr_bitfield_default },
+	 { "RXC1_EXT", 12, 15, &umr_bitfield_default },
+	 { "TXC0_DLY", 16, 18, &umr_bitfield_default },
+	 { "TXC0_EXT", 20, 23, &umr_bitfield_default },
+	 { "TXC1_DLY", 24, 26, &umr_bitfield_default },
+	 { "TXC1_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_2[] = {
+	 { "ADR_CLKEN_D0", 18, 18, &umr_bitfield_default },
+	 { "ADR_CLKEN_D1", 19, 19, &umr_bitfield_default },
+	 { "IND_LD_CNT", 0, 6, &umr_bitfield_default },
+	 { "RXC0_FRC", 12, 12, &umr_bitfield_default },
+	 { "RXC0_INV", 8, 8, &umr_bitfield_default },
+	 { "RXC1_FRC", 13, 13, &umr_bitfield_default },
+	 { "RXC1_INV", 9, 9, &umr_bitfield_default },
+	 { "TXC0_FRC", 14, 14, &umr_bitfield_default },
+	 { "TXC0_INV", 10, 10, &umr_bitfield_default },
+	 { "TXC1_FRC", 15, 15, &umr_bitfield_default },
+	 { "TXC1_INV", 11, 11, &umr_bitfield_default },
+	 { "TX_CDREN_D0", 16, 16, &umr_bitfield_default },
+	 { "TX_CDREN_D1", 17, 17, &umr_bitfield_default },
+	 { "WR_DLY", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DEBUG_INDEX[] = {
+	 { "TSM_DEBUG_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DEBUG_DATA[] = {
+	 { "TSM_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS1[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS1_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_TIMING_LP[] = {
+	 { "SEQ_IDLE", 18, 20, &umr_bitfield_default },
+	 { "SEQ_IDLE_SS", 24, 31, &umr_bitfield_default },
+	 { "TCKE", 12, 17, &umr_bitfield_default },
+	 { "TCKE_PULSE", 8, 11, &umr_bitfield_default },
+	 { "TCKE_PULSE_MSB", 23, 23, &umr_bitfield_default },
+	 { "TCKSRE", 0, 2, &umr_bitfield_default },
+	 { "TCKSRX", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CNTL_2[] = {
+	 { "ARB_RTDAT_WMK_MSB", 8, 9, &umr_bitfield_default },
+	 { "DRST_NSTR", 10, 15, &umr_bitfield_default },
+	 { "DRST_PSTR", 16, 21, &umr_bitfield_default },
+	 { "PLL_RX_PWRON_D0", 24, 27, &umr_bitfield_default },
+	 { "PLL_RX_PWRON_D1", 28, 31, &umr_bitfield_default },
+	 { "PLL_TX_PWRON_D0", 22, 22, &umr_bitfield_default },
+	 { "PLL_TX_PWRON_D1", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_2[] = {
+	 { "DAT_DLY_H_D0", 0, 0, &umr_bitfield_default },
+	 { "DAT_DLY_H_D1", 3, 3, &umr_bitfield_default },
+	 { "DQS_DLY_H_D0", 1, 1, &umr_bitfield_default },
+	 { "DQS_DLY_H_D1", 4, 4, &umr_bitfield_default },
+	 { "OEN_DLY_H_D0", 2, 2, &umr_bitfield_default },
+	 { "OEN_DLY_H_D1", 5, 5, &umr_bitfield_default },
+	 { "WCDR_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_2_LP[] = {
+	 { "DAT_DLY_H_D0", 0, 0, &umr_bitfield_default },
+	 { "DAT_DLY_H_D1", 3, 3, &umr_bitfield_default },
+	 { "DQS_DLY_H_D0", 1, 1, &umr_bitfield_default },
+	 { "DQS_DLY_H_D1", 4, 4, &umr_bitfield_default },
+	 { "OEN_DLY_H_D0", 2, 2, &umr_bitfield_default },
+	 { "OEN_DLY_H_D1", 5, 5, &umr_bitfield_default },
+	 { "WCDR_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS2[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS2_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_C_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_C_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_D_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_D_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL1_D0[] = {
+	 { "DQ_RXPHASE_B0", 0, 7, &umr_bitfield_default },
+	 { "DQ_RXPHASE_B1", 8, 15, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B0", 16, 23, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL1_D1[] = {
+	 { "DQ_RXPHASE_B0", 0, 7, &umr_bitfield_default },
+	 { "DQ_RXPHASE_B1", 8, 15, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B0", 16, 23, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY0_D0[] = {
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY1_D0[] = {
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY0_D1[] = {
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY1_D1[] = {
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_WCDR[] = {
+	 { "WCDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL2_D0[] = {
+	 { "CDR_FB_SEL0", 0, 0, &umr_bitfield_default },
+	 { "CDR_FB_SEL1", 1, 1, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR0", 2, 2, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR1", 3, 3, &umr_bitfield_default },
+	 { "TXCDRBYPASS0", 4, 4, &umr_bitfield_default },
+	 { "TXCDRBYPASS1", 5, 5, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR0", 6, 6, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR1", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL2_D1[] = {
+	 { "CDR_FB_SEL0", 0, 0, &umr_bitfield_default },
+	 { "CDR_FB_SEL1", 1, 1, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR0", 2, 2, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR1", 3, 3, &umr_bitfield_default },
+	 { "TXCDRBYPASS0", 4, 4, &umr_bitfield_default },
+	 { "TXCDRBYPASS1", 5, 5, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR0", 6, 6, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR1", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_MISC[] = {
+	 { "WCDR_MASK", 16, 19, &umr_bitfield_default },
+	 { "WCDR_PTR", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC9[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCLK_PWRMGT_CNTL[] = {
+	 { "DLL_READY", 6, 6, &umr_bitfield_default },
+	 { "DLL_READY_READ", 24, 24, &umr_bitfield_default },
+	 { "DLL_SPEED", 0, 4, &umr_bitfield_default },
+	 { "MC_INT_CNTL", 7, 7, &umr_bitfield_default },
+	 { "MRDCK0_PDNB", 8, 8, &umr_bitfield_default },
+	 { "MRDCK0_RESET", 16, 16, &umr_bitfield_default },
+	 { "MRDCK1_PDNB", 9, 9, &umr_bitfield_default },
+	 { "MRDCK1_RESET", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDLL_CNTL[] = {
+	 { "DLL_LOCK_TIME", 12, 21, &umr_bitfield_default },
+	 { "DLL_RESET_TIME", 0, 9, &umr_bitfield_default },
+	 { "MRDCK0_BYPASS", 24, 24, &umr_bitfield_default },
+	 { "MRDCK1_BYPASS", 25, 25, &umr_bitfield_default },
+	 { "PWR2_MODE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SEQ_UCODE_1[] = {
+	 { "INSTR0", 0, 3, &umr_bitfield_default },
+	 { "INSTR1", 4, 7, &umr_bitfield_default },
+	 { "INSTR2", 8, 11, &umr_bitfield_default },
+	 { "INSTR3", 12, 15, &umr_bitfield_default },
+	 { "INSTR4", 16, 19, &umr_bitfield_default },
+	 { "INSTR5", 20, 23, &umr_bitfield_default },
+	 { "INSTR6", 24, 27, &umr_bitfield_default },
+	 { "INSTR7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SEQ_UCODE_2[] = {
+	 { "INSTR10", 8, 11, &umr_bitfield_default },
+	 { "INSTR11", 12, 15, &umr_bitfield_default },
+	 { "INSTR12", 16, 19, &umr_bitfield_default },
+	 { "INSTR13", 20, 23, &umr_bitfield_default },
+	 { "INSTR14", 24, 27, &umr_bitfield_default },
+	 { "INSTR15", 28, 31, &umr_bitfield_default },
+	 { "INSTR8", 0, 3, &umr_bitfield_default },
+	 { "INSTR9", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_CNTL_MODE[] = {
+	 { "FAST_LOCK_CNTRL", 21, 22, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 20, 20, &umr_bitfield_default },
+	 { "FORCE_TESTMODE", 17, 17, &umr_bitfield_default },
+	 { "GLOBAL_MPLL_RESET", 31, 31, &umr_bitfield_default },
+	 { "INSTR_DELAY", 0, 7, &umr_bitfield_default },
+	 { "MPLL_CHG_STATUS", 16, 16, &umr_bitfield_default },
+	 { "MPLL_CTLREQ", 14, 14, &umr_bitfield_default },
+	 { "MPLL_MCLK_SEL", 11, 11, &umr_bitfield_default },
+	 { "MPLL_SW_DIR_CONTROL", 8, 8, &umr_bitfield_default },
+	 { "QDR", 13, 13, &umr_bitfield_default },
+	 { "SPARE_1", 12, 12, &umr_bitfield_default },
+	 { "SPARE_2", 23, 23, &umr_bitfield_default },
+	 { "SPARE_3", 28, 30, &umr_bitfield_default },
+	 { "SS_DSMODE_EN", 26, 26, &umr_bitfield_default },
+	 { "SS_SSEN", 24, 25, &umr_bitfield_default },
+	 { "VTOI_BIAS_CNTRL", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL[] = {
+	 { "BG_100ADJ", 8, 11, &umr_bitfield_default },
+	 { "BG_135ADJ", 16, 19, &umr_bitfield_default },
+	 { "BWCTRL", 20, 27, &umr_bitfield_default },
+	 { "REG_BIAS", 30, 31, &umr_bitfield_default },
+	 { "SPARE_0", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL_1[] = {
+	 { "CLKF", 16, 27, &umr_bitfield_default },
+	 { "CLKFRAC", 4, 15, &umr_bitfield_default },
+	 { "SPARE_0", 2, 3, &umr_bitfield_default },
+	 { "SPARE_1", 28, 31, &umr_bitfield_default },
+	 { "VCO_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL_2[] = {
+	 { "BACKUP_2", 17, 19, &umr_bitfield_default },
+	 { "BACKUP", 27, 31, &umr_bitfield_default },
+	 { "LF_CNTRL", 20, 26, &umr_bitfield_default },
+	 { "MPLL_UNLOCK_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 12, 13, &umr_bitfield_default },
+	 { "RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "RESET_TIMER", 10, 11, &umr_bitfield_default },
+	 { "TEST_BYPCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "TEST_BYPCLK_SRC", 4, 4, &umr_bitfield_default },
+	 { "TEST_BYPMCLK", 6, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC_BYPASS", 5, 5, &umr_bitfield_default },
+	 { "TEST_FBDIV_SSC_BYPASS", 9, 9, &umr_bitfield_default },
+	 { "TEST_VCTL_CNTRL", 8, 8, &umr_bitfield_default },
+	 { "TEST_VCTL_EN", 1, 1, &umr_bitfield_default },
+	 { "VCTRLADC_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_AD_FUNC_CNTL[] = {
+	 { "SPARE", 3, 31, &umr_bitfield_default },
+	 { "YCLK_POST_DIV", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_FUNC_CNTL[] = {
+	 { "SPARE_0", 3, 3, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+	 { "YCLK_POST_DIV", 0, 2, &umr_bitfield_default },
+	 { "YCLK_SEL", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_TIME[] = {
+	 { "MPLL_LOCK_TIME", 0, 15, &umr_bitfield_default },
+	 { "MPLL_RESET_TIME", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SS1[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+	 { "SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SS2[] = {
+	 { "CLKS", 0, 11, &umr_bitfield_default },
+	 { "SPARE", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_CONTROL[] = {
+	 { "AD_BG_PWRON", 12, 12, &umr_bitfield_default },
+	 { "AD_PLL_PWRON", 13, 13, &umr_bitfield_default },
+	 { "AD_PLL_RESET", 14, 14, &umr_bitfield_default },
+	 { "DQ_0_0_BG_PWRON", 16, 16, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_PWRON", 17, 17, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_RESET", 18, 18, &umr_bitfield_default },
+	 { "DQ_0_1_BG_PWRON", 20, 20, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_PWRON", 21, 21, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_RESET", 22, 22, &umr_bitfield_default },
+	 { "DQ_1_0_BG_PWRON", 24, 24, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_PWRON", 25, 25, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_RESET", 26, 26, &umr_bitfield_default },
+	 { "DQ_1_1_BG_PWRON", 28, 28, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_RESET", 30, 30, &umr_bitfield_default },
+	 { "GDDR_PWRON", 0, 0, &umr_bitfield_default },
+	 { "PLL_BUF_PWRON_TX", 2, 2, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 1, 1, &umr_bitfield_default },
+	 { "SPARE_AD_0", 15, 15, &umr_bitfield_default },
+	 { "SPARE_DQ_0_0", 19, 19, &umr_bitfield_default },
+	 { "SPARE_DQ_0_1", 23, 23, &umr_bitfield_default },
+	 { "SPARE_DQ_1_0", 27, 27, &umr_bitfield_default },
+	 { "SPARE_DQ_1_1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_AD_STATUS[] = {
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_0_0_STATUS[] = {
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_0_1_STATUS[] = {
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_1_0_STATUS[] = {
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_1_1_STATUS[] = {
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_2_D0[] = {
+	 { "ABI_STATUS", 28, 28, &umr_bitfield_default },
+	 { "ADDR_STATUS", 16, 25, &umr_bitfield_default },
+	 { "CAS_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CKB_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CKE_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CS_STATUS", 4, 5, &umr_bitfield_default },
+	 { "RAS_STATUS", 9, 9, &umr_bitfield_default },
+	 { "WE_STATUS", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_2_D1[] = {
+	 { "ABI_STATUS", 28, 28, &umr_bitfield_default },
+	 { "ADDR_STATUS", 16, 25, &umr_bitfield_default },
+	 { "CAS_STATUS", 10, 10, &umr_bitfield_default },
+	 { "CKB_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CKE_STATUS", 8, 8, &umr_bitfield_default },
+	 { "CK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CS_STATUS", 4, 5, &umr_bitfield_default },
+	 { "RAS_STATUS", 9, 9, &umr_bitfield_default },
+	 { "WE_STATUS", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_CNTL_1[] = {
+	 { "PAUSE", 0, 0, &umr_bitfield_default },
+	 { "SEL_A_MSB", 8, 8, &umr_bitfield_default },
+	 { "SEL_B_MSB", 9, 9, &umr_bitfield_default },
+	 { "SEL_CH0_C_MSB", 10, 10, &umr_bitfield_default },
+	 { "SEL_CH0_D_MSB", 11, 11, &umr_bitfield_default },
+	 { "SEL_CH1_A_MSB", 12, 12, &umr_bitfield_default },
+	 { "SEL_CH1_B_MSB", 13, 13, &umr_bitfield_default },
+	 { "SEL_CH1_C_MSB", 14, 14, &umr_bitfield_default },
+	 { "SEL_CH1_D_MSB", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD2[] = {
+	 { "THRESHOLD_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD3[] = {
+	 { "CH0_LINK_RETRAIN_IN_PROGRESS", 8, 8, &umr_bitfield_default },
+	 { "CH0_LINK_RETRAIN_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CH1_LINK_RETRAIN_IN_PROGRESS", 9, 9, &umr_bitfield_default },
+	 { "CH1_LINK_RETRAIN_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_RETRAIN_STATUS", 2, 2, &umr_bitfield_default },
+	 { "RETRAIN_MONITOR", 4, 5, &umr_bitfield_default },
+	 { "RETRAIN_VBI", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ADDR_DEC[] = {
+	 { "GECC", 1, 1, &umr_bitfield_default },
+	 { "NO_DIV_BY_3", 0, 0, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 3, 3, &umr_bitfield_default },
+	 { "RB_SPLIT", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_REMOTE[] = {
+	 { "RDREQ_EN_GOQ", 1, 1, &umr_bitfield_default },
+	 { "WRREQ_EN_GOQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_PRI_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT2[] = {
+	 { "HUB_LP_RDRET_SKID", 16, 23, &umr_bitfield_default },
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_CHTRIREMAP[] = {
+	 { "CH0", 0, 1, &umr_bitfield_default },
+	 { "CH1", 2, 3, &umr_bitfield_default },
+	 { "CH2", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_TWOCHAN[] = {
+	 { "CH0", 1, 2, &umr_bitfield_default },
+	 { "CH1", 3, 4, &umr_bitfield_default },
+	 { "DISABLE_ONEPORT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB[] = {
+	 { "BREAK_BURST_CID_CHANGE", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_HUB_STALL_HIGHEST", 1, 1, &umr_bitfield_default },
+	 { "HUBRD_HIGHEST", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB_MAX_BURST[] = {
+	 { "RD_PORT0", 0, 3, &umr_bitfield_default },
+	 { "RD_PORT1", 4, 7, &umr_bitfield_default },
+	 { "RD_PORT2", 8, 11, &umr_bitfield_default },
+	 { "RD_PORT3", 12, 15, &umr_bitfield_default },
+	 { "WR_PORT0", 16, 19, &umr_bitfield_default },
+	 { "WR_PORT1", 20, 23, &umr_bitfield_default },
+	 { "WR_PORT2", 24, 27, &umr_bitfield_default },
+	 { "WR_PORT3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL0[] = {
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL1[] = {
+	 { "START_TRIG_ID", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 16, 23, &umr_bitfield_default },
+	 { "THRESH_CNTR_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL2[] = {
+	 { "MON0_ID", 0, 7, &umr_bitfield_default },
+	 { "MON1_ID", 8, 15, &umr_bitfield_default },
+	 { "MON2_ID", 16, 23, &umr_bitfield_default },
+	 { "MON3_ID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT2[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT3[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_MAX_THSH[] = {
+	 { "MON0", 0, 7, &umr_bitfield_default },
+	 { "MON1", 8, 15, &umr_bitfield_default },
+	 { "MON2", 16, 23, &umr_bitfield_default },
+	 { "MON3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE0[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE1[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_CNTL[] = {
+	 { "CREDITS_ATS_RPB", 8, 13, &umr_bitfield_default },
+	 { "DEBUG_ECO", 16, 19, &umr_bitfield_default },
+	 { "DISABLE_ATC", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_PASID", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_PRI", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEBUG[] = {
+	 { "ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS", 2, 2, &umr_bitfield_default },
+	 { "DISALLOW_ERR_TO_DONE", 14, 14, &umr_bitfield_default },
+	 { "EXE_BIT", 7, 7, &umr_bitfield_default },
+	 { "IDENT_RETURN", 1, 1, &umr_bitfield_default },
+	 { "IGNORE_FED", 15, 15, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED", 16, 16, &umr_bitfield_default },
+	 { "NUM_REQUESTS_AT_ERR", 10, 13, &umr_bitfield_default },
+	 { "PAGE_REQUEST_PERMS", 8, 8, &umr_bitfield_default },
+	 { "PAGE_REQUESTS_USE_RELAXED_ORDERING", 5, 5, &umr_bitfield_default },
+	 { "PRIV_BIT", 6, 6, &umr_bitfield_default },
+	 { "UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_DEBUG[] = {
+	 { "ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES", 8, 8, &umr_bitfield_default },
+	 { "CLEAR_FAULT_STATUS_ADDR", 16, 16, &umr_bitfield_default },
+	 { "CREDITS_ATS_IH", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "CRASHED", 1, 1, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_CNTL[] = {
+	 { "FAULT_CRASH_TABLE", 20, 25, &umr_bitfield_default },
+	 { "FAULT_INTERRUPT_TABLE", 10, 15, &umr_bitfield_default },
+	 { "FAULT_REGISTER_LOG", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_INFO[] = {
+	 { "EXTRA_INFO2", 16, 16, &umr_bitfield_default },
+	 { "EXTRA_INFO", 15, 15, &umr_bitfield_default },
+	 { "FAULT_TYPE", 0, 5, &umr_bitfield_default },
+	 { "INVALIDATION", 17, 17, &umr_bitfield_default },
+	 { "PAGE_ADDR_HIGH", 24, 27, &umr_bitfield_default },
+	 { "PAGE_REQUEST", 18, 18, &umr_bitfield_default },
+	 { "STATUS", 19, 23, &umr_bitfield_default },
+	 { "VMID", 10, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_ADDR[] = {
+	 { "PAGE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_LOW[] = {
+	 { "DEFAULT_PAGE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_CNTL[] = {
+	 { "DEFAULT_PAGE_HIGH", 2, 5, &umr_bitfield_default },
+	 { "SEND_DEFAULT_PAGE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_MISC_CG[] = {
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL[] = {
+	 { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 10, 10, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 4, 5, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG[] = {
+	 { "CREDITS_L2_ATS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_CNTL[] = {
+	 { "DONT_NEED_ATS_BEHAVIOR", 0, 1, &umr_bitfield_default },
+	 { "NEED_ATS_BEHAVIOR", 2, 2, &umr_bitfield_default },
+	 { "NEED_ATS_SNOOP_DEFAULT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_ADDRESS_OFFSET[] = {
+	 { "LOGICAL_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_DEBUG_TLB[] = {
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_DEBUG_TLB[] = {
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_STATUS[] = {
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_STATUS[] = {
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[] = {
+	 { "VMID0_REMAPPING_FINISHED", 0, 0, &umr_bitfield_default },
+	 { "VMID10_REMAPPING_FINISHED", 10, 10, &umr_bitfield_default },
+	 { "VMID11_REMAPPING_FINISHED", 11, 11, &umr_bitfield_default },
+	 { "VMID12_REMAPPING_FINISHED", 12, 12, &umr_bitfield_default },
+	 { "VMID13_REMAPPING_FINISHED", 13, 13, &umr_bitfield_default },
+	 { "VMID14_REMAPPING_FINISHED", 14, 14, &umr_bitfield_default },
+	 { "VMID15_REMAPPING_FINISHED", 15, 15, &umr_bitfield_default },
+	 { "VMID1_REMAPPING_FINISHED", 1, 1, &umr_bitfield_default },
+	 { "VMID2_REMAPPING_FINISHED", 2, 2, &umr_bitfield_default },
+	 { "VMID3_REMAPPING_FINISHED", 3, 3, &umr_bitfield_default },
+	 { "VMID4_REMAPPING_FINISHED", 4, 4, &umr_bitfield_default },
+	 { "VMID5_REMAPPING_FINISHED", 5, 5, &umr_bitfield_default },
+	 { "VMID6_REMAPPING_FINISHED", 6, 6, &umr_bitfield_default },
+	 { "VMID7_REMAPPING_FINISHED", 7, 7, &umr_bitfield_default },
+	 { "VMID8_REMAPPING_FINISHED", 8, 8, &umr_bitfield_default },
+	 { "VMID9_REMAPPING_FINISHED", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID0_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID1_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID2_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID3_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID4_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID5_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID6_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID7_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID8_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID9_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID10_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID11_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID12_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID13_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID14_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID15_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_INDEX[] = {
+	 { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_DATA[] = {
+	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_EXECUTE[] = {
+	 { "RENG_EXECUTE_DSP_END_PTR", 12, 21, &umr_bitfield_default },
+	 { "RENG_EXECUTE_END_PTR", 22, 31, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW_START_PTR", 2, 11, &umr_bitfield_default },
+	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC[] = {
+	 { "ALLOW_DEEP_SLEEP_MODE", 28, 29, &umr_bitfield_default },
+	 { "CRITICAL_REGS_LOCK", 27, 27, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW_MODE", 10, 10, &umr_bitfield_default },
+	 { "RENG_EXECUTE_ON_REG_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "RENG_SRBM_CREDITS_MCD", 12, 15, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_ALLOW_SR", 25, 25, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_GMC_OFFLINE", 26, 26, &umr_bitfield_default },
+	 { "STCTRL_FORCE_ALLOW_SR", 30, 30, &umr_bitfield_default },
+	 { "STCTRL_GMC_IDLE_THRESHOLD", 17, 18, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STOP", 22, 22, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PRE_SR", 21, 21, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PROTECTION_FAULT", 24, 24, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_SR_COMMIT", 23, 23, &umr_bitfield_default },
+	 { "STCTRL_SRBM_IDLE_THRESHOLD", 19, 20, &umr_bitfield_default },
+	 { "STCTRL_STUTTER_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC2[] = {
+	 { "RENG_MEM_POWER_CTRL_OVERRIDE0", 0, 2, &umr_bitfield_default },
+	 { "RENG_MEM_POWER_CTRL_OVERRIDE1", 3, 5, &umr_bitfield_default },
+	 { "RENG_SR_HOLD_THRESHOLD", 10, 15, &umr_bitfield_default },
+	 { "STCTRL_EXTEND_GMC_OFFLINE", 29, 29, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ARB_BUSY", 28, 28, &umr_bitfield_default },
+	 { "STCTRL_LPT_TARGET", 16, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE1", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL0[] = {
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL1[] = {
+	 { "MON0_ID", 18, 23, &umr_bitfield_default },
+	 { "MON1_ID", 24, 29, &umr_bitfield_default },
+	 { "START_TRIG_ID", 6, 11, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 12, 17, &umr_bitfield_default },
+	 { "THRESH_CNTR_ID", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "READ", 13, 13, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+	 { "RSRVD", 14, 26, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "WRITE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_WRITE[] = {
+	 { "WRITE_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_READ[] = {
+	 { "PGFSM_SELECT", 24, 27, &umr_bitfield_default },
+	 { "READ_VALUE", 0, 23, &umr_bitfield_default },
+	 { "SERDES_MASTER_BUSY", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC3[] = {
+	 { "RENG_DISABLE_MCC", 0, 5, &umr_bitfield_default },
+	 { "RENG_DISABLE_MCD", 6, 11, &umr_bitfield_default },
+	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_DEBUG[] = {
+	 { "GFX_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "GFX_STALL", 0, 0, &umr_bitfield_default },
+	 { "MISC_FLAGS", 2, 29, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gmc60_regs.i b/src/lib/ip/gmc60_regs.i
new file mode 100644
index 0000000..56f1806
--- /dev/null
+++ b/src/lib/ip/gmc60_regs.i
@@ -0,0 +1,1229 @@
+	{ "ixMC_IO_DEBUG_UP_0", REG_SMC, 0x0000, &ixMC_IO_DEBUG_UP_0[0], sizeof(ixMC_IO_DEBUG_UP_0)/sizeof(ixMC_IO_DEBUG_UP_0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_1", REG_SMC, 0x0001, &ixMC_IO_DEBUG_UP_1[0], sizeof(ixMC_IO_DEBUG_UP_1)/sizeof(ixMC_IO_DEBUG_UP_1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_2", REG_SMC, 0x0002, &ixMC_IO_DEBUG_UP_2[0], sizeof(ixMC_IO_DEBUG_UP_2)/sizeof(ixMC_IO_DEBUG_UP_2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_3", REG_SMC, 0x0003, &ixMC_IO_DEBUG_UP_3[0], sizeof(ixMC_IO_DEBUG_UP_3)/sizeof(ixMC_IO_DEBUG_UP_3[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_4", REG_SMC, 0x0004, &ixMC_IO_DEBUG_UP_4[0], sizeof(ixMC_IO_DEBUG_UP_4)/sizeof(ixMC_IO_DEBUG_UP_4[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_5", REG_SMC, 0x0005, &ixMC_IO_DEBUG_UP_5[0], sizeof(ixMC_IO_DEBUG_UP_5)/sizeof(ixMC_IO_DEBUG_UP_5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_6", REG_SMC, 0x0006, &ixMC_IO_DEBUG_UP_6[0], sizeof(ixMC_IO_DEBUG_UP_6)/sizeof(ixMC_IO_DEBUG_UP_6[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_7", REG_SMC, 0x0007, &ixMC_IO_DEBUG_UP_7[0], sizeof(ixMC_IO_DEBUG_UP_7)/sizeof(ixMC_IO_DEBUG_UP_7[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_8", REG_SMC, 0x0008, &ixMC_IO_DEBUG_UP_8[0], sizeof(ixMC_IO_DEBUG_UP_8)/sizeof(ixMC_IO_DEBUG_UP_8[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_9", REG_SMC, 0x0009, &ixMC_IO_DEBUG_UP_9[0], sizeof(ixMC_IO_DEBUG_UP_9)/sizeof(ixMC_IO_DEBUG_UP_9[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_10", REG_SMC, 0x000A, &ixMC_IO_DEBUG_UP_10[0], sizeof(ixMC_IO_DEBUG_UP_10)/sizeof(ixMC_IO_DEBUG_UP_10[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_11", REG_SMC, 0x000B, &ixMC_IO_DEBUG_UP_11[0], sizeof(ixMC_IO_DEBUG_UP_11)/sizeof(ixMC_IO_DEBUG_UP_11[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_12", REG_SMC, 0x000C, &ixMC_IO_DEBUG_UP_12[0], sizeof(ixMC_IO_DEBUG_UP_12)/sizeof(ixMC_IO_DEBUG_UP_12[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_13", REG_SMC, 0x000D, &ixMC_IO_DEBUG_UP_13[0], sizeof(ixMC_IO_DEBUG_UP_13)/sizeof(ixMC_IO_DEBUG_UP_13[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_14", REG_SMC, 0x000E, &ixMC_IO_DEBUG_UP_14[0], sizeof(ixMC_IO_DEBUG_UP_14)/sizeof(ixMC_IO_DEBUG_UP_14[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_15", REG_SMC, 0x000F, &ixMC_IO_DEBUG_UP_15[0], sizeof(ixMC_IO_DEBUG_UP_15)/sizeof(ixMC_IO_DEBUG_UP_15[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_16", REG_SMC, 0x0010, &ixMC_IO_DEBUG_UP_16[0], sizeof(ixMC_IO_DEBUG_UP_16)/sizeof(ixMC_IO_DEBUG_UP_16[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_17", REG_SMC, 0x0011, &ixMC_IO_DEBUG_UP_17[0], sizeof(ixMC_IO_DEBUG_UP_17)/sizeof(ixMC_IO_DEBUG_UP_17[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_18", REG_SMC, 0x0012, &ixMC_IO_DEBUG_UP_18[0], sizeof(ixMC_IO_DEBUG_UP_18)/sizeof(ixMC_IO_DEBUG_UP_18[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_19", REG_SMC, 0x0013, &ixMC_IO_DEBUG_UP_19[0], sizeof(ixMC_IO_DEBUG_UP_19)/sizeof(ixMC_IO_DEBUG_UP_19[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_20", REG_SMC, 0x0014, &ixMC_IO_DEBUG_UP_20[0], sizeof(ixMC_IO_DEBUG_UP_20)/sizeof(ixMC_IO_DEBUG_UP_20[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_21", REG_SMC, 0x0015, &ixMC_IO_DEBUG_UP_21[0], sizeof(ixMC_IO_DEBUG_UP_21)/sizeof(ixMC_IO_DEBUG_UP_21[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_22", REG_SMC, 0x0016, &ixMC_IO_DEBUG_UP_22[0], sizeof(ixMC_IO_DEBUG_UP_22)/sizeof(ixMC_IO_DEBUG_UP_22[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_23", REG_SMC, 0x0017, &ixMC_IO_DEBUG_UP_23[0], sizeof(ixMC_IO_DEBUG_UP_23)/sizeof(ixMC_IO_DEBUG_UP_23[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_24", REG_SMC, 0x0018, &ixMC_IO_DEBUG_UP_24[0], sizeof(ixMC_IO_DEBUG_UP_24)/sizeof(ixMC_IO_DEBUG_UP_24[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_25", REG_SMC, 0x0019, &ixMC_IO_DEBUG_UP_25[0], sizeof(ixMC_IO_DEBUG_UP_25)/sizeof(ixMC_IO_DEBUG_UP_25[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_26", REG_SMC, 0x001A, &ixMC_IO_DEBUG_UP_26[0], sizeof(ixMC_IO_DEBUG_UP_26)/sizeof(ixMC_IO_DEBUG_UP_26[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_27", REG_SMC, 0x001B, &ixMC_IO_DEBUG_UP_27[0], sizeof(ixMC_IO_DEBUG_UP_27)/sizeof(ixMC_IO_DEBUG_UP_27[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_28", REG_SMC, 0x001C, &ixMC_IO_DEBUG_UP_28[0], sizeof(ixMC_IO_DEBUG_UP_28)/sizeof(ixMC_IO_DEBUG_UP_28[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_29", REG_SMC, 0x001D, &ixMC_IO_DEBUG_UP_29[0], sizeof(ixMC_IO_DEBUG_UP_29)/sizeof(ixMC_IO_DEBUG_UP_29[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_30", REG_SMC, 0x001E, &ixMC_IO_DEBUG_UP_30[0], sizeof(ixMC_IO_DEBUG_UP_30)/sizeof(ixMC_IO_DEBUG_UP_30[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_31", REG_SMC, 0x001F, &ixMC_IO_DEBUG_UP_31[0], sizeof(ixMC_IO_DEBUG_UP_31)/sizeof(ixMC_IO_DEBUG_UP_31[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_32", REG_SMC, 0x0020, &ixMC_IO_DEBUG_UP_32[0], sizeof(ixMC_IO_DEBUG_UP_32)/sizeof(ixMC_IO_DEBUG_UP_32[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_33", REG_SMC, 0x0021, &ixMC_IO_DEBUG_UP_33[0], sizeof(ixMC_IO_DEBUG_UP_33)/sizeof(ixMC_IO_DEBUG_UP_33[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_34", REG_SMC, 0x0022, &ixMC_IO_DEBUG_UP_34[0], sizeof(ixMC_IO_DEBUG_UP_34)/sizeof(ixMC_IO_DEBUG_UP_34[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_35", REG_SMC, 0x0023, &ixMC_IO_DEBUG_UP_35[0], sizeof(ixMC_IO_DEBUG_UP_35)/sizeof(ixMC_IO_DEBUG_UP_35[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_36", REG_SMC, 0x0024, &ixMC_IO_DEBUG_UP_36[0], sizeof(ixMC_IO_DEBUG_UP_36)/sizeof(ixMC_IO_DEBUG_UP_36[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_37", REG_SMC, 0x0025, &ixMC_IO_DEBUG_UP_37[0], sizeof(ixMC_IO_DEBUG_UP_37)/sizeof(ixMC_IO_DEBUG_UP_37[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_38", REG_SMC, 0x0026, &ixMC_IO_DEBUG_UP_38[0], sizeof(ixMC_IO_DEBUG_UP_38)/sizeof(ixMC_IO_DEBUG_UP_38[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_39", REG_SMC, 0x0027, &ixMC_IO_DEBUG_UP_39[0], sizeof(ixMC_IO_DEBUG_UP_39)/sizeof(ixMC_IO_DEBUG_UP_39[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_40", REG_SMC, 0x0028, &ixMC_IO_DEBUG_UP_40[0], sizeof(ixMC_IO_DEBUG_UP_40)/sizeof(ixMC_IO_DEBUG_UP_40[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_41", REG_SMC, 0x0029, &ixMC_IO_DEBUG_UP_41[0], sizeof(ixMC_IO_DEBUG_UP_41)/sizeof(ixMC_IO_DEBUG_UP_41[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_42", REG_SMC, 0x002A, &ixMC_IO_DEBUG_UP_42[0], sizeof(ixMC_IO_DEBUG_UP_42)/sizeof(ixMC_IO_DEBUG_UP_42[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_43", REG_SMC, 0x002B, &ixMC_IO_DEBUG_UP_43[0], sizeof(ixMC_IO_DEBUG_UP_43)/sizeof(ixMC_IO_DEBUG_UP_43[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_44", REG_SMC, 0x002C, &ixMC_IO_DEBUG_UP_44[0], sizeof(ixMC_IO_DEBUG_UP_44)/sizeof(ixMC_IO_DEBUG_UP_44[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_45", REG_SMC, 0x002D, &ixMC_IO_DEBUG_UP_45[0], sizeof(ixMC_IO_DEBUG_UP_45)/sizeof(ixMC_IO_DEBUG_UP_45[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_46", REG_SMC, 0x002E, &ixMC_IO_DEBUG_UP_46[0], sizeof(ixMC_IO_DEBUG_UP_46)/sizeof(ixMC_IO_DEBUG_UP_46[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_47", REG_SMC, 0x002F, &ixMC_IO_DEBUG_UP_47[0], sizeof(ixMC_IO_DEBUG_UP_47)/sizeof(ixMC_IO_DEBUG_UP_47[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_48", REG_SMC, 0x0030, &ixMC_IO_DEBUG_UP_48[0], sizeof(ixMC_IO_DEBUG_UP_48)/sizeof(ixMC_IO_DEBUG_UP_48[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_49", REG_SMC, 0x0031, &ixMC_IO_DEBUG_UP_49[0], sizeof(ixMC_IO_DEBUG_UP_49)/sizeof(ixMC_IO_DEBUG_UP_49[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_50", REG_SMC, 0x0032, &ixMC_IO_DEBUG_UP_50[0], sizeof(ixMC_IO_DEBUG_UP_50)/sizeof(ixMC_IO_DEBUG_UP_50[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_51", REG_SMC, 0x0033, &ixMC_IO_DEBUG_UP_51[0], sizeof(ixMC_IO_DEBUG_UP_51)/sizeof(ixMC_IO_DEBUG_UP_51[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_52", REG_SMC, 0x0034, &ixMC_IO_DEBUG_UP_52[0], sizeof(ixMC_IO_DEBUG_UP_52)/sizeof(ixMC_IO_DEBUG_UP_52[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_53", REG_SMC, 0x0035, &ixMC_IO_DEBUG_UP_53[0], sizeof(ixMC_IO_DEBUG_UP_53)/sizeof(ixMC_IO_DEBUG_UP_53[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_54", REG_SMC, 0x0036, &ixMC_IO_DEBUG_UP_54[0], sizeof(ixMC_IO_DEBUG_UP_54)/sizeof(ixMC_IO_DEBUG_UP_54[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_55", REG_SMC, 0x0037, &ixMC_IO_DEBUG_UP_55[0], sizeof(ixMC_IO_DEBUG_UP_55)/sizeof(ixMC_IO_DEBUG_UP_55[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_56", REG_SMC, 0x0038, &ixMC_IO_DEBUG_UP_56[0], sizeof(ixMC_IO_DEBUG_UP_56)/sizeof(ixMC_IO_DEBUG_UP_56[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_57", REG_SMC, 0x0039, &ixMC_IO_DEBUG_UP_57[0], sizeof(ixMC_IO_DEBUG_UP_57)/sizeof(ixMC_IO_DEBUG_UP_57[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_58", REG_SMC, 0x003A, &ixMC_IO_DEBUG_UP_58[0], sizeof(ixMC_IO_DEBUG_UP_58)/sizeof(ixMC_IO_DEBUG_UP_58[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_59", REG_SMC, 0x003B, &ixMC_IO_DEBUG_UP_59[0], sizeof(ixMC_IO_DEBUG_UP_59)/sizeof(ixMC_IO_DEBUG_UP_59[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_60", REG_SMC, 0x003C, &ixMC_IO_DEBUG_UP_60[0], sizeof(ixMC_IO_DEBUG_UP_60)/sizeof(ixMC_IO_DEBUG_UP_60[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_61", REG_SMC, 0x003D, &ixMC_IO_DEBUG_UP_61[0], sizeof(ixMC_IO_DEBUG_UP_61)/sizeof(ixMC_IO_DEBUG_UP_61[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_62", REG_SMC, 0x003E, &ixMC_IO_DEBUG_UP_62[0], sizeof(ixMC_IO_DEBUG_UP_62)/sizeof(ixMC_IO_DEBUG_UP_62[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_63", REG_SMC, 0x003F, &ixMC_IO_DEBUG_UP_63[0], sizeof(ixMC_IO_DEBUG_UP_63)/sizeof(ixMC_IO_DEBUG_UP_63[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_64", REG_SMC, 0x0040, &ixMC_IO_DEBUG_UP_64[0], sizeof(ixMC_IO_DEBUG_UP_64)/sizeof(ixMC_IO_DEBUG_UP_64[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_65", REG_SMC, 0x0041, &ixMC_IO_DEBUG_UP_65[0], sizeof(ixMC_IO_DEBUG_UP_65)/sizeof(ixMC_IO_DEBUG_UP_65[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_66", REG_SMC, 0x0042, &ixMC_IO_DEBUG_UP_66[0], sizeof(ixMC_IO_DEBUG_UP_66)/sizeof(ixMC_IO_DEBUG_UP_66[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_67", REG_SMC, 0x0043, &ixMC_IO_DEBUG_UP_67[0], sizeof(ixMC_IO_DEBUG_UP_67)/sizeof(ixMC_IO_DEBUG_UP_67[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_68", REG_SMC, 0x0044, &ixMC_IO_DEBUG_UP_68[0], sizeof(ixMC_IO_DEBUG_UP_68)/sizeof(ixMC_IO_DEBUG_UP_68[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_69", REG_SMC, 0x0045, &ixMC_IO_DEBUG_UP_69[0], sizeof(ixMC_IO_DEBUG_UP_69)/sizeof(ixMC_IO_DEBUG_UP_69[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_70", REG_SMC, 0x0046, &ixMC_IO_DEBUG_UP_70[0], sizeof(ixMC_IO_DEBUG_UP_70)/sizeof(ixMC_IO_DEBUG_UP_70[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_71", REG_SMC, 0x0047, &ixMC_IO_DEBUG_UP_71[0], sizeof(ixMC_IO_DEBUG_UP_71)/sizeof(ixMC_IO_DEBUG_UP_71[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_72", REG_SMC, 0x0048, &ixMC_IO_DEBUG_UP_72[0], sizeof(ixMC_IO_DEBUG_UP_72)/sizeof(ixMC_IO_DEBUG_UP_72[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_73", REG_SMC, 0x0049, &ixMC_IO_DEBUG_UP_73[0], sizeof(ixMC_IO_DEBUG_UP_73)/sizeof(ixMC_IO_DEBUG_UP_73[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_74", REG_SMC, 0x004A, &ixMC_IO_DEBUG_UP_74[0], sizeof(ixMC_IO_DEBUG_UP_74)/sizeof(ixMC_IO_DEBUG_UP_74[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_75", REG_SMC, 0x004B, &ixMC_IO_DEBUG_UP_75[0], sizeof(ixMC_IO_DEBUG_UP_75)/sizeof(ixMC_IO_DEBUG_UP_75[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_76", REG_SMC, 0x004C, &ixMC_IO_DEBUG_UP_76[0], sizeof(ixMC_IO_DEBUG_UP_76)/sizeof(ixMC_IO_DEBUG_UP_76[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_77", REG_SMC, 0x004D, &ixMC_IO_DEBUG_UP_77[0], sizeof(ixMC_IO_DEBUG_UP_77)/sizeof(ixMC_IO_DEBUG_UP_77[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_78", REG_SMC, 0x004E, &ixMC_IO_DEBUG_UP_78[0], sizeof(ixMC_IO_DEBUG_UP_78)/sizeof(ixMC_IO_DEBUG_UP_78[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_79", REG_SMC, 0x004F, &ixMC_IO_DEBUG_UP_79[0], sizeof(ixMC_IO_DEBUG_UP_79)/sizeof(ixMC_IO_DEBUG_UP_79[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_80", REG_SMC, 0x0050, &ixMC_IO_DEBUG_UP_80[0], sizeof(ixMC_IO_DEBUG_UP_80)/sizeof(ixMC_IO_DEBUG_UP_80[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_81", REG_SMC, 0x0051, &ixMC_IO_DEBUG_UP_81[0], sizeof(ixMC_IO_DEBUG_UP_81)/sizeof(ixMC_IO_DEBUG_UP_81[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_82", REG_SMC, 0x0052, &ixMC_IO_DEBUG_UP_82[0], sizeof(ixMC_IO_DEBUG_UP_82)/sizeof(ixMC_IO_DEBUG_UP_82[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_83", REG_SMC, 0x0053, &ixMC_IO_DEBUG_UP_83[0], sizeof(ixMC_IO_DEBUG_UP_83)/sizeof(ixMC_IO_DEBUG_UP_83[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_84", REG_SMC, 0x0054, &ixMC_IO_DEBUG_UP_84[0], sizeof(ixMC_IO_DEBUG_UP_84)/sizeof(ixMC_IO_DEBUG_UP_84[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_85", REG_SMC, 0x0055, &ixMC_IO_DEBUG_UP_85[0], sizeof(ixMC_IO_DEBUG_UP_85)/sizeof(ixMC_IO_DEBUG_UP_85[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_86", REG_SMC, 0x0056, &ixMC_IO_DEBUG_UP_86[0], sizeof(ixMC_IO_DEBUG_UP_86)/sizeof(ixMC_IO_DEBUG_UP_86[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_87", REG_SMC, 0x0057, &ixMC_IO_DEBUG_UP_87[0], sizeof(ixMC_IO_DEBUG_UP_87)/sizeof(ixMC_IO_DEBUG_UP_87[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_88", REG_SMC, 0x0058, &ixMC_IO_DEBUG_UP_88[0], sizeof(ixMC_IO_DEBUG_UP_88)/sizeof(ixMC_IO_DEBUG_UP_88[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_89", REG_SMC, 0x0059, &ixMC_IO_DEBUG_UP_89[0], sizeof(ixMC_IO_DEBUG_UP_89)/sizeof(ixMC_IO_DEBUG_UP_89[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_90", REG_SMC, 0x005A, &ixMC_IO_DEBUG_UP_90[0], sizeof(ixMC_IO_DEBUG_UP_90)/sizeof(ixMC_IO_DEBUG_UP_90[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_91", REG_SMC, 0x005B, &ixMC_IO_DEBUG_UP_91[0], sizeof(ixMC_IO_DEBUG_UP_91)/sizeof(ixMC_IO_DEBUG_UP_91[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_92", REG_SMC, 0x005C, &ixMC_IO_DEBUG_UP_92[0], sizeof(ixMC_IO_DEBUG_UP_92)/sizeof(ixMC_IO_DEBUG_UP_92[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_93", REG_SMC, 0x005D, &ixMC_IO_DEBUG_UP_93[0], sizeof(ixMC_IO_DEBUG_UP_93)/sizeof(ixMC_IO_DEBUG_UP_93[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_94", REG_SMC, 0x005E, &ixMC_IO_DEBUG_UP_94[0], sizeof(ixMC_IO_DEBUG_UP_94)/sizeof(ixMC_IO_DEBUG_UP_94[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_95", REG_SMC, 0x005F, &ixMC_IO_DEBUG_UP_95[0], sizeof(ixMC_IO_DEBUG_UP_95)/sizeof(ixMC_IO_DEBUG_UP_95[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_96", REG_SMC, 0x0060, &ixMC_IO_DEBUG_UP_96[0], sizeof(ixMC_IO_DEBUG_UP_96)/sizeof(ixMC_IO_DEBUG_UP_96[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_97", REG_SMC, 0x0061, &ixMC_IO_DEBUG_UP_97[0], sizeof(ixMC_IO_DEBUG_UP_97)/sizeof(ixMC_IO_DEBUG_UP_97[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_98", REG_SMC, 0x0062, &ixMC_IO_DEBUG_UP_98[0], sizeof(ixMC_IO_DEBUG_UP_98)/sizeof(ixMC_IO_DEBUG_UP_98[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_99", REG_SMC, 0x0063, &ixMC_IO_DEBUG_UP_99[0], sizeof(ixMC_IO_DEBUG_UP_99)/sizeof(ixMC_IO_DEBUG_UP_99[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_100", REG_SMC, 0x0064, &ixMC_IO_DEBUG_UP_100[0], sizeof(ixMC_IO_DEBUG_UP_100)/sizeof(ixMC_IO_DEBUG_UP_100[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_101", REG_SMC, 0x0065, &ixMC_IO_DEBUG_UP_101[0], sizeof(ixMC_IO_DEBUG_UP_101)/sizeof(ixMC_IO_DEBUG_UP_101[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_102", REG_SMC, 0x0066, &ixMC_IO_DEBUG_UP_102[0], sizeof(ixMC_IO_DEBUG_UP_102)/sizeof(ixMC_IO_DEBUG_UP_102[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_103", REG_SMC, 0x0067, &ixMC_IO_DEBUG_UP_103[0], sizeof(ixMC_IO_DEBUG_UP_103)/sizeof(ixMC_IO_DEBUG_UP_103[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_104", REG_SMC, 0x0068, &ixMC_IO_DEBUG_UP_104[0], sizeof(ixMC_IO_DEBUG_UP_104)/sizeof(ixMC_IO_DEBUG_UP_104[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_105", REG_SMC, 0x0069, &ixMC_IO_DEBUG_UP_105[0], sizeof(ixMC_IO_DEBUG_UP_105)/sizeof(ixMC_IO_DEBUG_UP_105[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_106", REG_SMC, 0x006A, &ixMC_IO_DEBUG_UP_106[0], sizeof(ixMC_IO_DEBUG_UP_106)/sizeof(ixMC_IO_DEBUG_UP_106[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_107", REG_SMC, 0x006B, &ixMC_IO_DEBUG_UP_107[0], sizeof(ixMC_IO_DEBUG_UP_107)/sizeof(ixMC_IO_DEBUG_UP_107[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_108", REG_SMC, 0x006C, &ixMC_IO_DEBUG_UP_108[0], sizeof(ixMC_IO_DEBUG_UP_108)/sizeof(ixMC_IO_DEBUG_UP_108[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_109", REG_SMC, 0x006D, &ixMC_IO_DEBUG_UP_109[0], sizeof(ixMC_IO_DEBUG_UP_109)/sizeof(ixMC_IO_DEBUG_UP_109[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_110", REG_SMC, 0x006E, &ixMC_IO_DEBUG_UP_110[0], sizeof(ixMC_IO_DEBUG_UP_110)/sizeof(ixMC_IO_DEBUG_UP_110[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_111", REG_SMC, 0x006F, &ixMC_IO_DEBUG_UP_111[0], sizeof(ixMC_IO_DEBUG_UP_111)/sizeof(ixMC_IO_DEBUG_UP_111[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_112", REG_SMC, 0x0070, &ixMC_IO_DEBUG_UP_112[0], sizeof(ixMC_IO_DEBUG_UP_112)/sizeof(ixMC_IO_DEBUG_UP_112[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_113", REG_SMC, 0x0071, &ixMC_IO_DEBUG_UP_113[0], sizeof(ixMC_IO_DEBUG_UP_113)/sizeof(ixMC_IO_DEBUG_UP_113[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_114", REG_SMC, 0x0072, &ixMC_IO_DEBUG_UP_114[0], sizeof(ixMC_IO_DEBUG_UP_114)/sizeof(ixMC_IO_DEBUG_UP_114[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_115", REG_SMC, 0x0073, &ixMC_IO_DEBUG_UP_115[0], sizeof(ixMC_IO_DEBUG_UP_115)/sizeof(ixMC_IO_DEBUG_UP_115[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_116", REG_SMC, 0x0074, &ixMC_IO_DEBUG_UP_116[0], sizeof(ixMC_IO_DEBUG_UP_116)/sizeof(ixMC_IO_DEBUG_UP_116[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_117", REG_SMC, 0x0075, &ixMC_IO_DEBUG_UP_117[0], sizeof(ixMC_IO_DEBUG_UP_117)/sizeof(ixMC_IO_DEBUG_UP_117[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_118", REG_SMC, 0x0076, &ixMC_IO_DEBUG_UP_118[0], sizeof(ixMC_IO_DEBUG_UP_118)/sizeof(ixMC_IO_DEBUG_UP_118[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_119", REG_SMC, 0x0077, &ixMC_IO_DEBUG_UP_119[0], sizeof(ixMC_IO_DEBUG_UP_119)/sizeof(ixMC_IO_DEBUG_UP_119[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_120", REG_SMC, 0x0078, &ixMC_IO_DEBUG_UP_120[0], sizeof(ixMC_IO_DEBUG_UP_120)/sizeof(ixMC_IO_DEBUG_UP_120[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_121", REG_SMC, 0x0079, &ixMC_IO_DEBUG_UP_121[0], sizeof(ixMC_IO_DEBUG_UP_121)/sizeof(ixMC_IO_DEBUG_UP_121[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_122", REG_SMC, 0x007A, &ixMC_IO_DEBUG_UP_122[0], sizeof(ixMC_IO_DEBUG_UP_122)/sizeof(ixMC_IO_DEBUG_UP_122[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_123", REG_SMC, 0x007B, &ixMC_IO_DEBUG_UP_123[0], sizeof(ixMC_IO_DEBUG_UP_123)/sizeof(ixMC_IO_DEBUG_UP_123[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_124", REG_SMC, 0x007C, &ixMC_IO_DEBUG_UP_124[0], sizeof(ixMC_IO_DEBUG_UP_124)/sizeof(ixMC_IO_DEBUG_UP_124[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_125", REG_SMC, 0x007D, &ixMC_IO_DEBUG_UP_125[0], sizeof(ixMC_IO_DEBUG_UP_125)/sizeof(ixMC_IO_DEBUG_UP_125[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_126", REG_SMC, 0x007E, &ixMC_IO_DEBUG_UP_126[0], sizeof(ixMC_IO_DEBUG_UP_126)/sizeof(ixMC_IO_DEBUG_UP_126[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_127", REG_SMC, 0x007F, &ixMC_IO_DEBUG_UP_127[0], sizeof(ixMC_IO_DEBUG_UP_127)/sizeof(ixMC_IO_DEBUG_UP_127[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_128", REG_SMC, 0x0080, &ixMC_IO_DEBUG_UP_128[0], sizeof(ixMC_IO_DEBUG_UP_128)/sizeof(ixMC_IO_DEBUG_UP_128[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_129", REG_SMC, 0x0081, &ixMC_IO_DEBUG_UP_129[0], sizeof(ixMC_IO_DEBUG_UP_129)/sizeof(ixMC_IO_DEBUG_UP_129[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_130", REG_SMC, 0x0082, &ixMC_IO_DEBUG_UP_130[0], sizeof(ixMC_IO_DEBUG_UP_130)/sizeof(ixMC_IO_DEBUG_UP_130[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_131", REG_SMC, 0x0083, &ixMC_IO_DEBUG_UP_131[0], sizeof(ixMC_IO_DEBUG_UP_131)/sizeof(ixMC_IO_DEBUG_UP_131[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_132", REG_SMC, 0x0084, &ixMC_IO_DEBUG_UP_132[0], sizeof(ixMC_IO_DEBUG_UP_132)/sizeof(ixMC_IO_DEBUG_UP_132[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_133", REG_SMC, 0x0085, &ixMC_IO_DEBUG_UP_133[0], sizeof(ixMC_IO_DEBUG_UP_133)/sizeof(ixMC_IO_DEBUG_UP_133[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_134", REG_SMC, 0x0086, &ixMC_IO_DEBUG_UP_134[0], sizeof(ixMC_IO_DEBUG_UP_134)/sizeof(ixMC_IO_DEBUG_UP_134[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_135", REG_SMC, 0x0087, &ixMC_IO_DEBUG_UP_135[0], sizeof(ixMC_IO_DEBUG_UP_135)/sizeof(ixMC_IO_DEBUG_UP_135[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_136", REG_SMC, 0x0088, &ixMC_IO_DEBUG_UP_136[0], sizeof(ixMC_IO_DEBUG_UP_136)/sizeof(ixMC_IO_DEBUG_UP_136[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_137", REG_SMC, 0x0089, &ixMC_IO_DEBUG_UP_137[0], sizeof(ixMC_IO_DEBUG_UP_137)/sizeof(ixMC_IO_DEBUG_UP_137[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_138", REG_SMC, 0x008A, &ixMC_IO_DEBUG_UP_138[0], sizeof(ixMC_IO_DEBUG_UP_138)/sizeof(ixMC_IO_DEBUG_UP_138[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_139", REG_SMC, 0x008B, &ixMC_IO_DEBUG_UP_139[0], sizeof(ixMC_IO_DEBUG_UP_139)/sizeof(ixMC_IO_DEBUG_UP_139[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_140", REG_SMC, 0x008C, &ixMC_IO_DEBUG_UP_140[0], sizeof(ixMC_IO_DEBUG_UP_140)/sizeof(ixMC_IO_DEBUG_UP_140[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_141", REG_SMC, 0x008D, &ixMC_IO_DEBUG_UP_141[0], sizeof(ixMC_IO_DEBUG_UP_141)/sizeof(ixMC_IO_DEBUG_UP_141[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_142", REG_SMC, 0x008E, &ixMC_IO_DEBUG_UP_142[0], sizeof(ixMC_IO_DEBUG_UP_142)/sizeof(ixMC_IO_DEBUG_UP_142[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_143", REG_SMC, 0x008F, &ixMC_IO_DEBUG_UP_143[0], sizeof(ixMC_IO_DEBUG_UP_143)/sizeof(ixMC_IO_DEBUG_UP_143[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_144", REG_SMC, 0x0090, &ixMC_IO_DEBUG_UP_144[0], sizeof(ixMC_IO_DEBUG_UP_144)/sizeof(ixMC_IO_DEBUG_UP_144[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_145", REG_SMC, 0x0091, &ixMC_IO_DEBUG_UP_145[0], sizeof(ixMC_IO_DEBUG_UP_145)/sizeof(ixMC_IO_DEBUG_UP_145[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_146", REG_SMC, 0x0092, &ixMC_IO_DEBUG_UP_146[0], sizeof(ixMC_IO_DEBUG_UP_146)/sizeof(ixMC_IO_DEBUG_UP_146[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_147", REG_SMC, 0x0093, &ixMC_IO_DEBUG_UP_147[0], sizeof(ixMC_IO_DEBUG_UP_147)/sizeof(ixMC_IO_DEBUG_UP_147[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_148", REG_SMC, 0x0094, &ixMC_IO_DEBUG_UP_148[0], sizeof(ixMC_IO_DEBUG_UP_148)/sizeof(ixMC_IO_DEBUG_UP_148[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_149", REG_SMC, 0x0095, &ixMC_IO_DEBUG_UP_149[0], sizeof(ixMC_IO_DEBUG_UP_149)/sizeof(ixMC_IO_DEBUG_UP_149[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_150", REG_SMC, 0x0096, &ixMC_IO_DEBUG_UP_150[0], sizeof(ixMC_IO_DEBUG_UP_150)/sizeof(ixMC_IO_DEBUG_UP_150[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_151", REG_SMC, 0x0097, &ixMC_IO_DEBUG_UP_151[0], sizeof(ixMC_IO_DEBUG_UP_151)/sizeof(ixMC_IO_DEBUG_UP_151[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_152", REG_SMC, 0x0098, &ixMC_IO_DEBUG_UP_152[0], sizeof(ixMC_IO_DEBUG_UP_152)/sizeof(ixMC_IO_DEBUG_UP_152[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_153", REG_SMC, 0x0099, &ixMC_IO_DEBUG_UP_153[0], sizeof(ixMC_IO_DEBUG_UP_153)/sizeof(ixMC_IO_DEBUG_UP_153[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_154", REG_SMC, 0x009A, &ixMC_IO_DEBUG_UP_154[0], sizeof(ixMC_IO_DEBUG_UP_154)/sizeof(ixMC_IO_DEBUG_UP_154[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_155", REG_SMC, 0x009B, &ixMC_IO_DEBUG_UP_155[0], sizeof(ixMC_IO_DEBUG_UP_155)/sizeof(ixMC_IO_DEBUG_UP_155[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_156", REG_SMC, 0x009C, &ixMC_IO_DEBUG_UP_156[0], sizeof(ixMC_IO_DEBUG_UP_156)/sizeof(ixMC_IO_DEBUG_UP_156[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_157", REG_SMC, 0x009D, &ixMC_IO_DEBUG_UP_157[0], sizeof(ixMC_IO_DEBUG_UP_157)/sizeof(ixMC_IO_DEBUG_UP_157[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_158", REG_SMC, 0x009E, &ixMC_IO_DEBUG_UP_158[0], sizeof(ixMC_IO_DEBUG_UP_158)/sizeof(ixMC_IO_DEBUG_UP_158[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_159", REG_SMC, 0x009F, &ixMC_IO_DEBUG_UP_159[0], sizeof(ixMC_IO_DEBUG_UP_159)/sizeof(ixMC_IO_DEBUG_UP_159[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_MISC_D0", REG_SMC, 0x00A0, &ixMC_IO_DEBUG_DQB0L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_MISC_D0", REG_SMC, 0x00A1, &ixMC_IO_DEBUG_DQB0H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_MISC_D0", REG_SMC, 0x00A2, &ixMC_IO_DEBUG_DQB1L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_MISC_D0", REG_SMC, 0x00A3, &ixMC_IO_DEBUG_DQB1H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_MISC_D0", REG_SMC, 0x00A4, &ixMC_IO_DEBUG_DQB2L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_MISC_D0", REG_SMC, 0x00A5, &ixMC_IO_DEBUG_DQB2H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_MISC_D0", REG_SMC, 0x00A6, &ixMC_IO_DEBUG_DQB3L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_MISC_D0", REG_SMC, 0x00A7, &ixMC_IO_DEBUG_DQB3H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_MISC_D0", REG_SMC, 0x00A8, &ixMC_IO_DEBUG_DBI_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DBI_MISC_D0)/sizeof(ixMC_IO_DEBUG_DBI_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_MISC_D0", REG_SMC, 0x00A9, &ixMC_IO_DEBUG_EDC_MISC_D0[0], sizeof(ixMC_IO_DEBUG_EDC_MISC_D0)/sizeof(ixMC_IO_DEBUG_EDC_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_MISC_D0", REG_SMC, 0x00AA, &ixMC_IO_DEBUG_WCK_MISC_D0[0], sizeof(ixMC_IO_DEBUG_WCK_MISC_D0)/sizeof(ixMC_IO_DEBUG_WCK_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_MISC_D0", REG_SMC, 0x00AB, &ixMC_IO_DEBUG_CK_MISC_D0[0], sizeof(ixMC_IO_DEBUG_CK_MISC_D0)/sizeof(ixMC_IO_DEBUG_CK_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_MISC_D0", REG_SMC, 0x00AC, &ixMC_IO_DEBUG_ADDRL_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_MISC_D0", REG_SMC, 0x00AD, &ixMC_IO_DEBUG_ADDRH_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_MISC_D0", REG_SMC, 0x00AE, &ixMC_IO_DEBUG_ACMD_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_MISC_D0)/sizeof(ixMC_IO_DEBUG_ACMD_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_MISC_D0", REG_SMC, 0x00AF, &ixMC_IO_DEBUG_CMD_MISC_D0[0], sizeof(ixMC_IO_DEBUG_CMD_MISC_D0)/sizeof(ixMC_IO_DEBUG_CMD_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_MISC_D1", REG_SMC, 0x00B0, &ixMC_IO_DEBUG_DQB0L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_MISC_D1", REG_SMC, 0x00B1, &ixMC_IO_DEBUG_DQB0H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_MISC_D1", REG_SMC, 0x00B2, &ixMC_IO_DEBUG_DQB1L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_MISC_D1", REG_SMC, 0x00B3, &ixMC_IO_DEBUG_DQB1H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_MISC_D1", REG_SMC, 0x00B4, &ixMC_IO_DEBUG_DQB2L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_MISC_D1", REG_SMC, 0x00B5, &ixMC_IO_DEBUG_DQB2H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_MISC_D1", REG_SMC, 0x00B6, &ixMC_IO_DEBUG_DQB3L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_MISC_D1", REG_SMC, 0x00B7, &ixMC_IO_DEBUG_DQB3H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_MISC_D1", REG_SMC, 0x00B8, &ixMC_IO_DEBUG_DBI_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DBI_MISC_D1)/sizeof(ixMC_IO_DEBUG_DBI_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_MISC_D1", REG_SMC, 0x00B9, &ixMC_IO_DEBUG_EDC_MISC_D1[0], sizeof(ixMC_IO_DEBUG_EDC_MISC_D1)/sizeof(ixMC_IO_DEBUG_EDC_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_MISC_D1", REG_SMC, 0x00BA, &ixMC_IO_DEBUG_WCK_MISC_D1[0], sizeof(ixMC_IO_DEBUG_WCK_MISC_D1)/sizeof(ixMC_IO_DEBUG_WCK_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_MISC_D1", REG_SMC, 0x00BB, &ixMC_IO_DEBUG_CK_MISC_D1[0], sizeof(ixMC_IO_DEBUG_CK_MISC_D1)/sizeof(ixMC_IO_DEBUG_CK_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_MISC_D1", REG_SMC, 0x00BC, &ixMC_IO_DEBUG_ADDRL_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_MISC_D1", REG_SMC, 0x00BD, &ixMC_IO_DEBUG_ADDRH_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_MISC_D1", REG_SMC, 0x00BE, &ixMC_IO_DEBUG_ACMD_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_MISC_D1)/sizeof(ixMC_IO_DEBUG_ACMD_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_MISC_D1", REG_SMC, 0x00BF, &ixMC_IO_DEBUG_CMD_MISC_D1[0], sizeof(ixMC_IO_DEBUG_CMD_MISC_D1)/sizeof(ixMC_IO_DEBUG_CMD_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_CLKSEL_D0", REG_SMC, 0x00C0, &ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_CLKSEL_D0", REG_SMC, 0x00C1, &ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_CLKSEL_D0", REG_SMC, 0x00C2, &ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_CLKSEL_D0", REG_SMC, 0x00C3, &ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_CLKSEL_D0", REG_SMC, 0x00C4, &ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_CLKSEL_D0", REG_SMC, 0x00C5, &ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_CLKSEL_D0", REG_SMC, 0x00C6, &ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_CLKSEL_D0", REG_SMC, 0x00C7, &ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CLKSEL_D0", REG_SMC, 0x00C8, &ixMC_IO_DEBUG_DBI_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CLKSEL_D0", REG_SMC, 0x00C9, &ixMC_IO_DEBUG_EDC_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_CLKSEL_D0", REG_SMC, 0x00CA, &ixMC_IO_DEBUG_WCK_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_CLKSEL_D0", REG_SMC, 0x00CB, &ixMC_IO_DEBUG_CK_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_CLKSEL_D0", REG_SMC, 0x00CC, &ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_CLKSEL_D0", REG_SMC, 0x00CD, &ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_CLKSEL_D0", REG_SMC, 0x00CE, &ixMC_IO_DEBUG_ACMD_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_CLKSEL_D0", REG_SMC, 0x00CF, &ixMC_IO_DEBUG_CMD_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_CLKSEL_D1", REG_SMC, 0x00D0, &ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_CLKSEL_D1", REG_SMC, 0x00D1, &ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_CLKSEL_D1", REG_SMC, 0x00D2, &ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_CLKSEL_D1", REG_SMC, 0x00D3, &ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_CLKSEL_D1", REG_SMC, 0x00D4, &ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_CLKSEL_D1", REG_SMC, 0x00D5, &ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_CLKSEL_D1", REG_SMC, 0x00D6, &ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_CLKSEL_D1", REG_SMC, 0x00D7, &ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CLKSEL_D1", REG_SMC, 0x00D8, &ixMC_IO_DEBUG_DBI_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CLKSEL_D1", REG_SMC, 0x00D9, &ixMC_IO_DEBUG_EDC_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_CLKSEL_D1", REG_SMC, 0x00DA, &ixMC_IO_DEBUG_WCK_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_CLKSEL_D1", REG_SMC, 0x00DB, &ixMC_IO_DEBUG_CK_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_CLKSEL_D1", REG_SMC, 0x00DC, &ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_CLKSEL_D1", REG_SMC, 0x00DD, &ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_CLKSEL_D1", REG_SMC, 0x00DE, &ixMC_IO_DEBUG_ACMD_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_CLKSEL_D1", REG_SMC, 0x00DF, &ixMC_IO_DEBUG_CMD_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_OFSCAL_D0", REG_SMC, 0x00E0, &ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_OFSCAL_D0", REG_SMC, 0x00E1, &ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_OFSCAL_D0", REG_SMC, 0x00E2, &ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_OFSCAL_D0", REG_SMC, 0x00E3, &ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_OFSCAL_D0", REG_SMC, 0x00E4, &ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_OFSCAL_D0", REG_SMC, 0x00E5, &ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_OFSCAL_D0", REG_SMC, 0x00E6, &ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_OFSCAL_D0", REG_SMC, 0x00E7, &ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_OFSCAL_D0", REG_SMC, 0x00E8, &ixMC_IO_DEBUG_DBI_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_OFSCAL_D0", REG_SMC, 0x00E9, &ixMC_IO_DEBUG_EDC_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_OFSCAL_D0", REG_SMC, 0x00EA, &ixMC_IO_DEBUG_WCK_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0", REG_SMC, 0x00EB, &ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0", REG_SMC, 0x00EC, &ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0", REG_SMC, 0x00ED, &ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_OFSCAL_D0", REG_SMC, 0x00EE, &ixMC_IO_DEBUG_ACMD_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_OFSCAL_D0", REG_SMC, 0x00EF, &ixMC_IO_DEBUG_CMD_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_OFSCAL_D1", REG_SMC, 0x00F0, &ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_OFSCAL_D1", REG_SMC, 0x00F1, &ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_OFSCAL_D1", REG_SMC, 0x00F2, &ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_OFSCAL_D1", REG_SMC, 0x00F3, &ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_OFSCAL_D1", REG_SMC, 0x00F4, &ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_OFSCAL_D1", REG_SMC, 0x00F5, &ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_OFSCAL_D1", REG_SMC, 0x00F6, &ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_OFSCAL_D1", REG_SMC, 0x00F7, &ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_OFSCAL_D1", REG_SMC, 0x00F8, &ixMC_IO_DEBUG_DBI_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_OFSCAL_D1", REG_SMC, 0x00F9, &ixMC_IO_DEBUG_EDC_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_OFSCAL_D1", REG_SMC, 0x00FA, &ixMC_IO_DEBUG_WCK_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1", REG_SMC, 0x00FB, &ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1", REG_SMC, 0x00FC, &ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1", REG_SMC, 0x00FD, &ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_OFSCAL_D1", REG_SMC, 0x00FE, &ixMC_IO_DEBUG_ACMD_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_OFSCAL_D1", REG_SMC, 0x00FF, &ixMC_IO_DEBUG_CMD_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RXPHASE_D0", REG_SMC, 0x0100, &ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RXPHASE_D0", REG_SMC, 0x0101, &ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RXPHASE_D0", REG_SMC, 0x0102, &ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RXPHASE_D0", REG_SMC, 0x0103, &ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RXPHASE_D0", REG_SMC, 0x0104, &ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RXPHASE_D0", REG_SMC, 0x0105, &ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RXPHASE_D0", REG_SMC, 0x0106, &ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RXPHASE_D0", REG_SMC, 0x0107, &ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RXPHASE_D0", REG_SMC, 0x0108, &ixMC_IO_DEBUG_DBI_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RXPHASE_D0", REG_SMC, 0x0109, &ixMC_IO_DEBUG_EDC_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RXPHASE_D0", REG_SMC, 0x010A, &ixMC_IO_DEBUG_WCK_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_RXPHASE_D0", REG_SMC, 0x010B, &ixMC_IO_DEBUG_CK_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_RXPHASE_D0", REG_SMC, 0x010C, &ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_RXPHASE_D0", REG_SMC, 0x010D, &ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_RXPHASE_D0", REG_SMC, 0x010E, &ixMC_IO_DEBUG_ACMD_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RXPHASE_D0", REG_SMC, 0x010F, &ixMC_IO_DEBUG_CMD_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RXPHASE_D1", REG_SMC, 0x0110, &ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RXPHASE_D1", REG_SMC, 0x0111, &ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RXPHASE_D1", REG_SMC, 0x0112, &ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RXPHASE_D1", REG_SMC, 0x0113, &ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RXPHASE_D1", REG_SMC, 0x0114, &ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RXPHASE_D1", REG_SMC, 0x0115, &ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RXPHASE_D1", REG_SMC, 0x0116, &ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RXPHASE_D1", REG_SMC, 0x0117, &ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RXPHASE_D1", REG_SMC, 0x0118, &ixMC_IO_DEBUG_DBI_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RXPHASE_D1", REG_SMC, 0x0119, &ixMC_IO_DEBUG_EDC_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RXPHASE_D1", REG_SMC, 0x011A, &ixMC_IO_DEBUG_WCK_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_RXPHASE_D1", REG_SMC, 0x011B, &ixMC_IO_DEBUG_CK_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_RXPHASE_D1", REG_SMC, 0x011C, &ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_RXPHASE_D1", REG_SMC, 0x011D, &ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_RXPHASE_D1", REG_SMC, 0x011E, &ixMC_IO_DEBUG_ACMD_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RXPHASE_D1", REG_SMC, 0x011F, &ixMC_IO_DEBUG_CMD_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXPHASE_D0", REG_SMC, 0x0120, &ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXPHASE_D0", REG_SMC, 0x0121, &ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXPHASE_D0", REG_SMC, 0x0122, &ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXPHASE_D0", REG_SMC, 0x0123, &ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXPHASE_D0", REG_SMC, 0x0124, &ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXPHASE_D0", REG_SMC, 0x0125, &ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXPHASE_D0", REG_SMC, 0x0126, &ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXPHASE_D0", REG_SMC, 0x0127, &ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXPHASE_D0", REG_SMC, 0x0128, &ixMC_IO_DEBUG_DBI_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXPHASE_D0", REG_SMC, 0x0129, &ixMC_IO_DEBUG_EDC_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXPHASE_D0", REG_SMC, 0x012A, &ixMC_IO_DEBUG_WCK_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXPHASE_D0", REG_SMC, 0x012B, &ixMC_IO_DEBUG_CK_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXPHASE_D0", REG_SMC, 0x012C, &ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXPHASE_D0", REG_SMC, 0x012D, &ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXPHASE_D0", REG_SMC, 0x012E, &ixMC_IO_DEBUG_ACMD_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXPHASE_D0", REG_SMC, 0x012F, &ixMC_IO_DEBUG_CMD_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXPHASE_D1", REG_SMC, 0x0130, &ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXPHASE_D1", REG_SMC, 0x0131, &ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXPHASE_D1", REG_SMC, 0x0132, &ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXPHASE_D1", REG_SMC, 0x0133, &ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXPHASE_D1", REG_SMC, 0x0134, &ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXPHASE_D1", REG_SMC, 0x0135, &ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXPHASE_D1", REG_SMC, 0x0136, &ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXPHASE_D1", REG_SMC, 0x0137, &ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXPHASE_D1", REG_SMC, 0x0138, &ixMC_IO_DEBUG_DBI_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXPHASE_D1", REG_SMC, 0x0139, &ixMC_IO_DEBUG_EDC_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXPHASE_D1", REG_SMC, 0x013A, &ixMC_IO_DEBUG_WCK_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXPHASE_D1", REG_SMC, 0x013B, &ixMC_IO_DEBUG_CK_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXPHASE_D1", REG_SMC, 0x013C, &ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXPHASE_D1", REG_SMC, 0x013D, &ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXPHASE_D1", REG_SMC, 0x013E, &ixMC_IO_DEBUG_ACMD_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXPHASE_D1", REG_SMC, 0x013F, &ixMC_IO_DEBUG_CMD_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0", REG_SMC, 0x0140, &ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0", REG_SMC, 0x0141, &ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0", REG_SMC, 0x0142, &ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0", REG_SMC, 0x0143, &ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0", REG_SMC, 0x0144, &ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0", REG_SMC, 0x0145, &ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0", REG_SMC, 0x0146, &ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0", REG_SMC, 0x0147, &ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0", REG_SMC, 0x0148, &ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0", REG_SMC, 0x0149, &ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0", REG_SMC, 0x014A, &ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0", REG_SMC, 0x014B, &ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0", REG_SMC, 0x014C, &ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0", REG_SMC, 0x014D, &ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0", REG_SMC, 0x014E, &ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0", REG_SMC, 0x014F, &ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1", REG_SMC, 0x0150, &ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1", REG_SMC, 0x0151, &ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1", REG_SMC, 0x0152, &ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1", REG_SMC, 0x0153, &ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1", REG_SMC, 0x0154, &ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1", REG_SMC, 0x0155, &ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1", REG_SMC, 0x0156, &ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1", REG_SMC, 0x0157, &ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1", REG_SMC, 0x0158, &ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1", REG_SMC, 0x0159, &ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1", REG_SMC, 0x015A, &ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1", REG_SMC, 0x015B, &ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1", REG_SMC, 0x015C, &ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1", REG_SMC, 0x015D, &ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1", REG_SMC, 0x015E, &ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1", REG_SMC, 0x015F, &ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXSLF_D0", REG_SMC, 0x0160, &ixMC_IO_DEBUG_DQB0L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXSLF_D0", REG_SMC, 0x0161, &ixMC_IO_DEBUG_DQB0H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXSLF_D0", REG_SMC, 0x0162, &ixMC_IO_DEBUG_DQB1L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXSLF_D0", REG_SMC, 0x0163, &ixMC_IO_DEBUG_DQB1H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXSLF_D0", REG_SMC, 0x0164, &ixMC_IO_DEBUG_DQB2L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXSLF_D0", REG_SMC, 0x0165, &ixMC_IO_DEBUG_DQB2H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXSLF_D0", REG_SMC, 0x0166, &ixMC_IO_DEBUG_DQB3L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXSLF_D0", REG_SMC, 0x0167, &ixMC_IO_DEBUG_DQB3H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXSLF_D0", REG_SMC, 0x0168, &ixMC_IO_DEBUG_DBI_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXSLF_D0", REG_SMC, 0x0169, &ixMC_IO_DEBUG_EDC_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXSLF_D0", REG_SMC, 0x016A, &ixMC_IO_DEBUG_WCK_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXSLF_D0", REG_SMC, 0x016B, &ixMC_IO_DEBUG_CK_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_CK_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXSLF_D0", REG_SMC, 0x016C, &ixMC_IO_DEBUG_ADDRL_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXSLF_D0", REG_SMC, 0x016D, &ixMC_IO_DEBUG_ADDRH_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXSLF_D0", REG_SMC, 0x016E, &ixMC_IO_DEBUG_ACMD_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXSLF_D0", REG_SMC, 0x016F, &ixMC_IO_DEBUG_CMD_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXSLF_D1", REG_SMC, 0x0170, &ixMC_IO_DEBUG_DQB0L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXSLF_D1", REG_SMC, 0x0171, &ixMC_IO_DEBUG_DQB0H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXSLF_D1", REG_SMC, 0x0172, &ixMC_IO_DEBUG_DQB1L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXSLF_D1", REG_SMC, 0x0173, &ixMC_IO_DEBUG_DQB1H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXSLF_D1", REG_SMC, 0x0174, &ixMC_IO_DEBUG_DQB2L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXSLF_D1", REG_SMC, 0x0175, &ixMC_IO_DEBUG_DQB2H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXSLF_D1", REG_SMC, 0x0176, &ixMC_IO_DEBUG_DQB3L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXSLF_D1", REG_SMC, 0x0177, &ixMC_IO_DEBUG_DQB3H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXSLF_D1", REG_SMC, 0x0178, &ixMC_IO_DEBUG_DBI_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXSLF_D1", REG_SMC, 0x0179, &ixMC_IO_DEBUG_EDC_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXSLF_D1", REG_SMC, 0x017A, &ixMC_IO_DEBUG_WCK_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXSLF_D1", REG_SMC, 0x017B, &ixMC_IO_DEBUG_CK_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_CK_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXSLF_D1", REG_SMC, 0x017C, &ixMC_IO_DEBUG_ADDRL_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXSLF_D1", REG_SMC, 0x017D, &ixMC_IO_DEBUG_ADDRH_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXSLF_D1", REG_SMC, 0x017E, &ixMC_IO_DEBUG_ACMD_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXSLF_D1", REG_SMC, 0x017F, &ixMC_IO_DEBUG_CMD_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0", REG_SMC, 0x0180, &ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0", REG_SMC, 0x0181, &ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0", REG_SMC, 0x0182, &ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0", REG_SMC, 0x0183, &ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0", REG_SMC, 0x0184, &ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0", REG_SMC, 0x0185, &ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0", REG_SMC, 0x0186, &ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0", REG_SMC, 0x0187, &ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PD_D0", REG_SMC, 0x0188, &ixMC_IO_DEBUG_DBI_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PD_D0", REG_SMC, 0x0189, &ixMC_IO_DEBUG_EDC_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PD_D0", REG_SMC, 0x018A, &ixMC_IO_DEBUG_WCK_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PD_D0", REG_SMC, 0x018B, &ixMC_IO_DEBUG_CK_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0", REG_SMC, 0x018C, &ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0", REG_SMC, 0x018D, &ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PD_D0", REG_SMC, 0x018E, &ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PD_D0", REG_SMC, 0x018F, &ixMC_IO_DEBUG_CMD_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1", REG_SMC, 0x0190, &ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1", REG_SMC, 0x0191, &ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1", REG_SMC, 0x0192, &ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1", REG_SMC, 0x0193, &ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1", REG_SMC, 0x0194, &ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1", REG_SMC, 0x0195, &ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1", REG_SMC, 0x0196, &ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1", REG_SMC, 0x0197, &ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PD_D1", REG_SMC, 0x0198, &ixMC_IO_DEBUG_DBI_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PD_D1", REG_SMC, 0x0199, &ixMC_IO_DEBUG_EDC_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PD_D1", REG_SMC, 0x019A, &ixMC_IO_DEBUG_WCK_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PD_D1", REG_SMC, 0x019B, &ixMC_IO_DEBUG_CK_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1", REG_SMC, 0x019C, &ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1", REG_SMC, 0x019D, &ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PD_D1", REG_SMC, 0x019E, &ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PD_D1", REG_SMC, 0x019F, &ixMC_IO_DEBUG_CMD_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0", REG_SMC, 0x01A0, &ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0", REG_SMC, 0x01A1, &ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0", REG_SMC, 0x01A2, &ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0", REG_SMC, 0x01A3, &ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0", REG_SMC, 0x01A4, &ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0", REG_SMC, 0x01A5, &ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0", REG_SMC, 0x01A6, &ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0", REG_SMC, 0x01A7, &ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PU_D0", REG_SMC, 0x01A8, &ixMC_IO_DEBUG_DBI_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PU_D0", REG_SMC, 0x01A9, &ixMC_IO_DEBUG_EDC_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PU_D0", REG_SMC, 0x01AA, &ixMC_IO_DEBUG_WCK_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PU_D0", REG_SMC, 0x01AB, &ixMC_IO_DEBUG_CK_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0", REG_SMC, 0x01AC, &ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0", REG_SMC, 0x01AD, &ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PU_D0", REG_SMC, 0x01AE, &ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PU_D0", REG_SMC, 0x01AF, &ixMC_IO_DEBUG_CMD_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1", REG_SMC, 0x01B0, &ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1", REG_SMC, 0x01B1, &ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1", REG_SMC, 0x01B2, &ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1", REG_SMC, 0x01B3, &ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1", REG_SMC, 0x01B4, &ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1", REG_SMC, 0x01B5, &ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1", REG_SMC, 0x01B6, &ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1", REG_SMC, 0x01B7, &ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PU_D1", REG_SMC, 0x01B8, &ixMC_IO_DEBUG_DBI_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PU_D1", REG_SMC, 0x01B9, &ixMC_IO_DEBUG_EDC_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PU_D1", REG_SMC, 0x01BA, &ixMC_IO_DEBUG_WCK_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PU_D1", REG_SMC, 0x01BB, &ixMC_IO_DEBUG_CK_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1", REG_SMC, 0x01BC, &ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1", REG_SMC, 0x01BD, &ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PU_D1", REG_SMC, 0x01BE, &ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PU_D1", REG_SMC, 0x01BF, &ixMC_IO_DEBUG_CMD_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_EQ_D0", REG_SMC, 0x01C0, &ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_EQ_D0", REG_SMC, 0x01C1, &ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_EQ_D0", REG_SMC, 0x01C2, &ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_EQ_D0", REG_SMC, 0x01C3, &ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_EQ_D0", REG_SMC, 0x01C4, &ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_EQ_D0", REG_SMC, 0x01C5, &ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_EQ_D0", REG_SMC, 0x01C6, &ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_EQ_D0", REG_SMC, 0x01C7, &ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_EQ_D0", REG_SMC, 0x01C8, &ixMC_IO_DEBUG_DBI_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_D0", REG_SMC, 0x01C9, &ixMC_IO_DEBUG_EDC_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_EQ_D0", REG_SMC, 0x01CA, &ixMC_IO_DEBUG_WCK_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0", REG_SMC, 0x01CB, &ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0", REG_SMC, 0x01CC, &ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0", REG_SMC, 0x01CD, &ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0", REG_SMC, 0x01CE, &ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RX_EQ_D0", REG_SMC, 0x01CF, &ixMC_IO_DEBUG_CMD_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_EQ_D1", REG_SMC, 0x01D0, &ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_EQ_D1", REG_SMC, 0x01D1, &ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_EQ_D1", REG_SMC, 0x01D2, &ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_EQ_D1", REG_SMC, 0x01D3, &ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_EQ_D1", REG_SMC, 0x01D4, &ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_EQ_D1", REG_SMC, 0x01D5, &ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_EQ_D1", REG_SMC, 0x01D6, &ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_EQ_D1", REG_SMC, 0x01D7, &ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_EQ_D1", REG_SMC, 0x01D8, &ixMC_IO_DEBUG_DBI_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_D1", REG_SMC, 0x01D9, &ixMC_IO_DEBUG_EDC_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_EQ_D1", REG_SMC, 0x01DA, &ixMC_IO_DEBUG_WCK_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1", REG_SMC, 0x01DB, &ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1", REG_SMC, 0x01DC, &ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1", REG_SMC, 0x01DD, &ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1", REG_SMC, 0x01DE, &ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RX_EQ_D1", REG_SMC, 0x01DF, &ixMC_IO_DEBUG_CMD_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_MISC_D0", REG_SMC, 0x01E0, &ixMC_IO_DEBUG_WCDR_MISC_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_MISC_D0)/sizeof(ixMC_IO_DEBUG_WCDR_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CLKSEL_D0", REG_SMC, 0x01E1, &ixMC_IO_DEBUG_WCDR_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_OFSCAL_D0", REG_SMC, 0x01E2, &ixMC_IO_DEBUG_WCDR_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RXPHASE_D0", REG_SMC, 0x01E3, &ixMC_IO_DEBUG_WCDR_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXPHASE_D0", REG_SMC, 0x01E4, &ixMC_IO_DEBUG_WCDR_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0", REG_SMC, 0x01E5, &ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXSLF_D0", REG_SMC, 0x01E6, &ixMC_IO_DEBUG_WCDR_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PD_D0", REG_SMC, 0x01E7, &ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PU_D0", REG_SMC, 0x01E8, &ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_D0", REG_SMC, 0x01E9, &ixMC_IO_DEBUG_WCDR_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0", REG_SMC, 0x01EA, &ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0", REG_SMC, 0x01EB, &ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0", REG_SMC, 0x01EC, &ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_MISC_D1", REG_SMC, 0x01F0, &ixMC_IO_DEBUG_WCDR_MISC_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_MISC_D1)/sizeof(ixMC_IO_DEBUG_WCDR_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CLKSEL_D1", REG_SMC, 0x01F1, &ixMC_IO_DEBUG_WCDR_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_OFSCAL_D1", REG_SMC, 0x01F2, &ixMC_IO_DEBUG_WCDR_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RXPHASE_D1", REG_SMC, 0x01F3, &ixMC_IO_DEBUG_WCDR_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXPHASE_D1", REG_SMC, 0x01F4, &ixMC_IO_DEBUG_WCDR_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1", REG_SMC, 0x01F5, &ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXSLF_D1", REG_SMC, 0x01F6, &ixMC_IO_DEBUG_WCDR_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PD_D1", REG_SMC, 0x01F7, &ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PU_D1", REG_SMC, 0x01F8, &ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_D1", REG_SMC, 0x01F9, &ixMC_IO_DEBUG_WCDR_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1", REG_SMC, 0x01FA, &ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1", REG_SMC, 0x01FB, &ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1", REG_SMC, 0x01FC, &ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "mmVM_L2_CNTL", REG_MMIO, 0x0500, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 },
+	{ "mmVM_L2_CNTL2", REG_MMIO, 0x0501, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 },
+	{ "mmVM_L2_CNTL3", REG_MMIO, 0x0502, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 },
+	{ "mmVM_L2_STATUS", REG_MMIO, 0x0503, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x0504, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x0505, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x0506, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_ADDR", REG_MMIO, 0x0507, &mmVM_DUMMY_PAGE_FAULT_ADDR[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL2", REG_MMIO, 0x050C, &mmVM_CONTEXT0_CNTL2[0], sizeof(mmVM_CONTEXT0_CNTL2)/sizeof(mmVM_CONTEXT0_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL2", REG_MMIO, 0x050D, &mmVM_CONTEXT1_CNTL2[0], sizeof(mmVM_CONTEXT1_CNTL2)/sizeof(mmVM_CONTEXT1_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x050E, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x050F, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0510, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0511, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0512, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0513, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0514, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0515, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_REQUEST", REG_MMIO, 0x051E, &mmVM_INVALIDATE_REQUEST[0], sizeof(mmVM_INVALIDATE_REQUEST)/sizeof(mmVM_INVALIDATE_REQUEST[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_RESPONSE", REG_MMIO, 0x051F, &mmVM_INVALIDATE_RESPONSE[0], sizeof(mmVM_INVALIDATE_RESPONSE)/sizeof(mmVM_INVALIDATE_RESPONSE[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_LOW_ADDR", REG_MMIO, 0x052C, &mmVM_PRT_APERTURE0_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE0_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_LOW_ADDR", REG_MMIO, 0x052D, &mmVM_PRT_APERTURE1_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE1_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_LOW_ADDR", REG_MMIO, 0x052E, &mmVM_PRT_APERTURE2_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE2_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE2_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_LOW_ADDR", REG_MMIO, 0x052F, &mmVM_PRT_APERTURE3_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE3_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE3_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_HIGH_ADDR", REG_MMIO, 0x0530, &mmVM_PRT_APERTURE0_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_HIGH_ADDR", REG_MMIO, 0x0531, &mmVM_PRT_APERTURE1_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_HIGH_ADDR", REG_MMIO, 0x0532, &mmVM_PRT_APERTURE2_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_HIGH_ADDR", REG_MMIO, 0x0533, &mmVM_PRT_APERTURE3_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_CNTL", REG_MMIO, 0x0534, &mmVM_PRT_CNTL[0], sizeof(mmVM_PRT_CNTL)/sizeof(mmVM_PRT_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x0535, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_STATUS", REG_MMIO, 0x0536, &mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_STATUS", REG_MMIO, 0x0537, &mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_ADDR", REG_MMIO, 0x053E, &mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_ADDR", REG_MMIO, 0x053F, &mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x0546, &mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x0547, &mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_FAULT_CLIENT_ID", REG_MMIO, 0x054E, &mmVM_FAULT_CLIENT_ID[0], sizeof(mmVM_FAULT_CLIENT_ID)/sizeof(mmVM_FAULT_CLIENT_ID[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x054F, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0550, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0551, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0552, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0553, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0554, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0555, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x0556, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR", REG_MMIO, 0x0557, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR", REG_MMIO, 0x0558, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR", REG_MMIO, 0x055F, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR", REG_MMIO, 0x0560, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "mmVM_DEBUG", REG_MMIO, 0x056F, &mmVM_DEBUG[0], sizeof(mmVM_DEBUG)/sizeof(mmVM_DEBUG[0]), 0, 0 },
+	{ "mmVM_L2_CG", REG_MMIO, 0x0570, &mmVM_L2_CG[0], sizeof(mmVM_L2_CG)/sizeof(mmVM_L2_CG[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKA", REG_MMIO, 0x0572, &mmVM_L2_BANK_SELECT_MASKA[0], sizeof(mmVM_L2_BANK_SELECT_MASKA)/sizeof(mmVM_L2_BANK_SELECT_MASKA[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKB", REG_MMIO, 0x0573, &mmVM_L2_BANK_SELECT_MASKB[0], sizeof(mmVM_L2_BANK_SELECT_MASKB)/sizeof(mmVM_L2_BANK_SELECT_MASKB[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", REG_MMIO, 0x0575, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", REG_MMIO, 0x0576, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", REG_MMIO, 0x0577, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0]), 0, 0 },
+	{ "mmMC_CONFIG", REG_MMIO, 0x0800, &mmMC_CONFIG[0], sizeof(mmMC_CONFIG)/sizeof(mmMC_CONFIG[0]), 0, 0 },
+	{ "mmMC_SHARED_CHMAP", REG_MMIO, 0x0801, &mmMC_SHARED_CHMAP[0], sizeof(mmMC_SHARED_CHMAP)/sizeof(mmMC_SHARED_CHMAP[0]), 0, 0 },
+	{ "mmMC_SHARED_CHREMAP", REG_MMIO, 0x0802, &mmMC_SHARED_CHREMAP[0], sizeof(mmMC_SHARED_CHREMAP)/sizeof(mmMC_SHARED_CHREMAP[0]), 0, 0 },
+	{ "mmMC_RD_GRP_GFX", REG_MMIO, 0x0803, &mmMC_RD_GRP_GFX[0], sizeof(mmMC_RD_GRP_GFX)/sizeof(mmMC_RD_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_WR_GRP_GFX", REG_MMIO, 0x0804, &mmMC_WR_GRP_GFX[0], sizeof(mmMC_WR_GRP_GFX)/sizeof(mmMC_WR_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_RD_GRP_SYS", REG_MMIO, 0x0805, &mmMC_RD_GRP_SYS[0], sizeof(mmMC_RD_GRP_SYS)/sizeof(mmMC_RD_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_WR_GRP_SYS", REG_MMIO, 0x0806, &mmMC_WR_GRP_SYS[0], sizeof(mmMC_WR_GRP_SYS)/sizeof(mmMC_WR_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_RD_GRP_OTH", REG_MMIO, 0x0807, &mmMC_RD_GRP_OTH[0], sizeof(mmMC_RD_GRP_OTH)/sizeof(mmMC_RD_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_WR_GRP_OTH", REG_MMIO, 0x0808, &mmMC_WR_GRP_OTH[0], sizeof(mmMC_WR_GRP_OTH)/sizeof(mmMC_WR_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_VM_FB_LOCATION", REG_MMIO, 0x0809, &mmMC_VM_FB_LOCATION[0], sizeof(mmMC_VM_FB_LOCATION)/sizeof(mmMC_VM_FB_LOCATION[0]), 0, 0 },
+	{ "mmMC_VM_AGP_TOP", REG_MMIO, 0x080A, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BOT", REG_MMIO, 0x080B, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BASE", REG_MMIO, 0x080C, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x080D, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x080E, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", REG_MMIO, 0x080F, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_CNTL", REG_MMIO, 0x0810, &mmMC_VM_DC_WRITE_CNTL[0], sizeof(mmMC_VM_DC_WRITE_CNTL)/sizeof(mmMC_VM_DC_WRITE_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR", REG_MMIO, 0x0811, &mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR", REG_MMIO, 0x0812, &mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR", REG_MMIO, 0x0813, &mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR", REG_MMIO, 0x0814, &mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR", REG_MMIO, 0x0815, &mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR", REG_MMIO, 0x0816, &mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR", REG_MMIO, 0x0817, &mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR", REG_MMIO, 0x0818, &mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x0819, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_FB_OFFSET", REG_MMIO, 0x081A, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 },
+	{ "mmMC_CONFIG_MCD", REG_MMIO, 0x0828, &mmMC_CONFIG_MCD[0], sizeof(mmMC_CONFIG_MCD)/sizeof(mmMC_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG_MCD", REG_MMIO, 0x0829, &mmMC_CG_CONFIG_MCD[0], sizeof(mmMC_CG_CONFIG_MCD)/sizeof(mmMC_CG_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_MEM_POWER_LS", REG_MMIO, 0x082A, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 },
+	{ "mmMC_SHARED_BLACKOUT_CNTL", REG_MMIO, 0x082B, &mmMC_SHARED_BLACKOUT_CNTL[0], sizeof(mmMC_SHARED_BLACKOUT_CNTL)/sizeof(mmMC_SHARED_BLACKOUT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_POWER", REG_MMIO, 0x082D, &mmMC_HUB_MISC_POWER[0], sizeof(mmMC_HUB_MISC_POWER)/sizeof(mmMC_HUB_MISC_POWER[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_HUB_CG", REG_MMIO, 0x082E, &mmMC_HUB_MISC_HUB_CG[0], sizeof(mmMC_HUB_MISC_HUB_CG)/sizeof(mmMC_HUB_MISC_HUB_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_VM_CG", REG_MMIO, 0x082F, &mmMC_HUB_MISC_VM_CG[0], sizeof(mmMC_HUB_MISC_VM_CG)/sizeof(mmMC_HUB_MISC_VM_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_SIP_CG", REG_MMIO, 0x0830, &mmMC_HUB_MISC_SIP_CG[0], sizeof(mmMC_HUB_MISC_SIP_CG)/sizeof(mmMC_HUB_MISC_SIP_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_DBG", REG_MMIO, 0x0831, &mmMC_HUB_MISC_DBG[0], sizeof(mmMC_HUB_MISC_DBG)/sizeof(mmMC_HUB_MISC_DBG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_STATUS", REG_MMIO, 0x0832, &mmMC_HUB_MISC_STATUS[0], sizeof(mmMC_HUB_MISC_STATUS)/sizeof(mmMC_HUB_MISC_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_OVERRIDE", REG_MMIO, 0x0833, &mmMC_HUB_MISC_OVERRIDE[0], sizeof(mmMC_HUB_MISC_OVERRIDE)/sizeof(mmMC_HUB_MISC_OVERRIDE[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_FRAMING", REG_MMIO, 0x0834, &mmMC_HUB_MISC_FRAMING[0], sizeof(mmMC_HUB_MISC_FRAMING)/sizeof(mmMC_HUB_MISC_FRAMING[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CNTL", REG_MMIO, 0x0835, &mmMC_HUB_WDP_CNTL[0], sizeof(mmMC_HUB_WDP_CNTL)/sizeof(mmMC_HUB_WDP_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ERR", REG_MMIO, 0x0836, &mmMC_HUB_WDP_ERR[0], sizeof(mmMC_HUB_WDP_ERR)/sizeof(mmMC_HUB_WDP_ERR[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BP", REG_MMIO, 0x0837, &mmMC_HUB_WDP_BP[0], sizeof(mmMC_HUB_WDP_BP)/sizeof(mmMC_HUB_WDP_BP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_STATUS", REG_MMIO, 0x0838, &mmMC_HUB_WDP_STATUS[0], sizeof(mmMC_HUB_WDP_STATUS)/sizeof(mmMC_HUB_WDP_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_STATUS", REG_MMIO, 0x0839, &mmMC_HUB_RDREQ_STATUS[0], sizeof(mmMC_HUB_RDREQ_STATUS)/sizeof(mmMC_HUB_RDREQ_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_STATUS", REG_MMIO, 0x083A, &mmMC_HUB_WRRET_STATUS[0], sizeof(mmMC_HUB_WRRET_STATUS)/sizeof(mmMC_HUB_WRRET_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CNTL", REG_MMIO, 0x083B, &mmMC_HUB_RDREQ_CNTL[0], sizeof(mmMC_HUB_RDREQ_CNTL)/sizeof(mmMC_HUB_RDREQ_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_CNTL", REG_MMIO, 0x083C, &mmMC_HUB_WRRET_CNTL[0], sizeof(mmMC_HUB_WRRET_CNTL)/sizeof(mmMC_HUB_WRRET_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_WTM_CNTL", REG_MMIO, 0x083D, &mmMC_HUB_RDREQ_WTM_CNTL[0], sizeof(mmMC_HUB_RDREQ_WTM_CNTL)/sizeof(mmMC_HUB_RDREQ_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_WTM_CNTL", REG_MMIO, 0x083E, &mmMC_HUB_WDP_WTM_CNTL[0], sizeof(mmMC_HUB_WDP_WTM_CNTL)/sizeof(mmMC_HUB_WDP_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS", REG_MMIO, 0x083F, &mmMC_HUB_WDP_CREDITS[0], sizeof(mmMC_HUB_WDP_CREDITS)/sizeof(mmMC_HUB_WDP_CREDITS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MGPU2", REG_MMIO, 0x0840, &mmMC_HUB_WDP_MGPU2[0], sizeof(mmMC_HUB_WDP_MGPU2)/sizeof(mmMC_HUB_WDP_MGPU2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL0", REG_MMIO, 0x0841, &mmMC_HUB_WDP_GBL0[0], sizeof(mmMC_HUB_WDP_GBL0)/sizeof(mmMC_HUB_WDP_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL1", REG_MMIO, 0x0842, &mmMC_HUB_WDP_GBL1[0], sizeof(mmMC_HUB_WDP_GBL1)/sizeof(mmMC_HUB_WDP_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MGPU", REG_MMIO, 0x0843, &mmMC_HUB_WDP_MGPU[0], sizeof(mmMC_HUB_WDP_MGPU)/sizeof(mmMC_HUB_WDP_MGPU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS", REG_MMIO, 0x0844, &mmMC_HUB_RDREQ_CREDITS[0], sizeof(mmMC_HUB_RDREQ_CREDITS)/sizeof(mmMC_HUB_RDREQ_CREDITS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS2", REG_MMIO, 0x0845, &mmMC_HUB_RDREQ_CREDITS2[0], sizeof(mmMC_HUB_RDREQ_CREDITS2)/sizeof(mmMC_HUB_RDREQ_CREDITS2[0]), 0, 0 },
+	{ "mmMC_HUB_SHARED_DAGB_DLY", REG_MMIO, 0x0846, &mmMC_HUB_SHARED_DAGB_DLY[0], sizeof(mmMC_HUB_SHARED_DAGB_DLY)/sizeof(mmMC_HUB_SHARED_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_IDLE_STATUS", REG_MMIO, 0x0847, &mmMC_HUB_MISC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_IDLE_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF_LIMIT", REG_MMIO, 0x0848, &mmMC_HUB_RDREQ_DMIF_LIMIT[0], sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT)/sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDW", REG_MMIO, 0x0851, &mmMC_HUB_RDREQ_MCDW[0], sizeof(mmMC_HUB_RDREQ_MCDW)/sizeof(mmMC_HUB_RDREQ_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDX", REG_MMIO, 0x0852, &mmMC_HUB_RDREQ_MCDX[0], sizeof(mmMC_HUB_RDREQ_MCDX)/sizeof(mmMC_HUB_RDREQ_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDY", REG_MMIO, 0x0853, &mmMC_HUB_RDREQ_MCDY[0], sizeof(mmMC_HUB_RDREQ_MCDY)/sizeof(mmMC_HUB_RDREQ_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDZ", REG_MMIO, 0x0854, &mmMC_HUB_RDREQ_MCDZ[0], sizeof(mmMC_HUB_RDREQ_MCDZ)/sizeof(mmMC_HUB_RDREQ_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SIP", REG_MMIO, 0x0855, &mmMC_HUB_RDREQ_SIP[0], sizeof(mmMC_HUB_RDREQ_SIP)/sizeof(mmMC_HUB_RDREQ_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL0", REG_MMIO, 0x0856, &mmMC_HUB_RDREQ_GBL0[0], sizeof(mmMC_HUB_RDREQ_GBL0)/sizeof(mmMC_HUB_RDREQ_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL1", REG_MMIO, 0x0857, &mmMC_HUB_RDREQ_GBL1[0], sizeof(mmMC_HUB_RDREQ_GBL1)/sizeof(mmMC_HUB_RDREQ_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SMU", REG_MMIO, 0x0858, &mmMC_HUB_RDREQ_SMU[0], sizeof(mmMC_HUB_RDREQ_SMU)/sizeof(mmMC_HUB_RDREQ_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_HDP", REG_MMIO, 0x085B, &mmMC_HUB_RDREQ_HDP[0], sizeof(mmMC_HUB_RDREQ_HDP)/sizeof(mmMC_HUB_RDREQ_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_RLC", REG_MMIO, 0x085D, &mmMC_HUB_RDREQ_RLC[0], sizeof(mmMC_HUB_RDREQ_RLC)/sizeof(mmMC_HUB_RDREQ_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SEM", REG_MMIO, 0x085E, &mmMC_HUB_RDREQ_SEM[0], sizeof(mmMC_HUB_RDREQ_SEM)/sizeof(mmMC_HUB_RDREQ_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCE", REG_MMIO, 0x085F, &mmMC_HUB_RDREQ_VCE[0], sizeof(mmMC_HUB_RDREQ_VCE)/sizeof(mmMC_HUB_RDREQ_VCE[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UMC", REG_MMIO, 0x0860, &mmMC_HUB_RDREQ_UMC[0], sizeof(mmMC_HUB_RDREQ_UMC)/sizeof(mmMC_HUB_RDREQ_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UVD", REG_MMIO, 0x0861, &mmMC_HUB_RDREQ_UVD[0], sizeof(mmMC_HUB_RDREQ_UVD)/sizeof(mmMC_HUB_RDREQ_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF", REG_MMIO, 0x0863, &mmMC_HUB_RDREQ_DMIF[0], sizeof(mmMC_HUB_RDREQ_DMIF)/sizeof(mmMC_HUB_RDREQ_DMIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCIF", REG_MMIO, 0x0864, &mmMC_HUB_RDREQ_MCIF[0], sizeof(mmMC_HUB_RDREQ_MCIF)/sizeof(mmMC_HUB_RDREQ_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VMC", REG_MMIO, 0x0865, &mmMC_HUB_RDREQ_VMC[0], sizeof(mmMC_HUB_RDREQ_VMC)/sizeof(mmMC_HUB_RDREQ_VMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCEU", REG_MMIO, 0x0866, &mmMC_HUB_RDREQ_VCEU[0], sizeof(mmMC_HUB_RDREQ_VCEU)/sizeof(mmMC_HUB_RDREQ_VCEU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDW", REG_MMIO, 0x0867, &mmMC_HUB_WDP_MCDW[0], sizeof(mmMC_HUB_WDP_MCDW)/sizeof(mmMC_HUB_WDP_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDX", REG_MMIO, 0x0868, &mmMC_HUB_WDP_MCDX[0], sizeof(mmMC_HUB_WDP_MCDX)/sizeof(mmMC_HUB_WDP_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDY", REG_MMIO, 0x0869, &mmMC_HUB_WDP_MCDY[0], sizeof(mmMC_HUB_WDP_MCDY)/sizeof(mmMC_HUB_WDP_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDZ", REG_MMIO, 0x086A, &mmMC_HUB_WDP_MCDZ[0], sizeof(mmMC_HUB_WDP_MCDZ)/sizeof(mmMC_HUB_WDP_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SIP", REG_MMIO, 0x086B, &mmMC_HUB_WDP_SIP[0], sizeof(mmMC_HUB_WDP_SIP)/sizeof(mmMC_HUB_WDP_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH0", REG_MMIO, 0x086E, &mmMC_HUB_WDP_SH0[0], sizeof(mmMC_HUB_WDP_SH0)/sizeof(mmMC_HUB_WDP_SH0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCIF", REG_MMIO, 0x086F, &mmMC_HUB_WDP_MCIF[0], sizeof(mmMC_HUB_WDP_MCIF)/sizeof(mmMC_HUB_WDP_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCE", REG_MMIO, 0x0870, &mmMC_HUB_WDP_VCE[0], sizeof(mmMC_HUB_WDP_VCE)/sizeof(mmMC_HUB_WDP_VCE[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDP", REG_MMIO, 0x0871, &mmMC_HUB_WDP_XDP[0], sizeof(mmMC_HUB_WDP_XDP)/sizeof(mmMC_HUB_WDP_XDP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_IH", REG_MMIO, 0x0872, &mmMC_HUB_WDP_IH[0], sizeof(mmMC_HUB_WDP_IH)/sizeof(mmMC_HUB_WDP_IH[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_RLC", REG_MMIO, 0x0873, &mmMC_HUB_WDP_RLC[0], sizeof(mmMC_HUB_WDP_RLC)/sizeof(mmMC_HUB_WDP_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SEM", REG_MMIO, 0x0874, &mmMC_HUB_WDP_SEM[0], sizeof(mmMC_HUB_WDP_SEM)/sizeof(mmMC_HUB_WDP_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SMU", REG_MMIO, 0x0875, &mmMC_HUB_WDP_SMU[0], sizeof(mmMC_HUB_WDP_SMU)/sizeof(mmMC_HUB_WDP_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH1", REG_MMIO, 0x0876, &mmMC_HUB_WDP_SH1[0], sizeof(mmMC_HUB_WDP_SH1)/sizeof(mmMC_HUB_WDP_SH1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UMC", REG_MMIO, 0x0877, &mmMC_HUB_WDP_UMC[0], sizeof(mmMC_HUB_WDP_UMC)/sizeof(mmMC_HUB_WDP_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UVD", REG_MMIO, 0x0878, &mmMC_HUB_WDP_UVD[0], sizeof(mmMC_HUB_WDP_UVD)/sizeof(mmMC_HUB_WDP_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_HDP", REG_MMIO, 0x0879, &mmMC_HUB_WDP_HDP[0], sizeof(mmMC_HUB_WDP_HDP)/sizeof(mmMC_HUB_WDP_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDW", REG_MMIO, 0x087B, &mmMC_HUB_WRRET_MCDW[0], sizeof(mmMC_HUB_WRRET_MCDW)/sizeof(mmMC_HUB_WRRET_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDX", REG_MMIO, 0x087C, &mmMC_HUB_WRRET_MCDX[0], sizeof(mmMC_HUB_WRRET_MCDX)/sizeof(mmMC_HUB_WRRET_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDY", REG_MMIO, 0x087D, &mmMC_HUB_WRRET_MCDY[0], sizeof(mmMC_HUB_WRRET_MCDY)/sizeof(mmMC_HUB_WRRET_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDZ", REG_MMIO, 0x087E, &mmMC_HUB_WRRET_MCDZ[0], sizeof(mmMC_HUB_WRRET_MCDZ)/sizeof(mmMC_HUB_WRRET_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCEU", REG_MMIO, 0x087F, &mmMC_HUB_WDP_VCEU[0], sizeof(mmMC_HUB_WDP_VCEU)/sizeof(mmMC_HUB_WDP_VCEU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMAM", REG_MMIO, 0x0880, &mmMC_HUB_WDP_XDMAM[0], sizeof(mmMC_HUB_WDP_XDMAM)/sizeof(mmMC_HUB_WDP_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMA", REG_MMIO, 0x0881, &mmMC_HUB_WDP_XDMA[0], sizeof(mmMC_HUB_WDP_XDMA)/sizeof(mmMC_HUB_WDP_XDMA[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_XDMAM", REG_MMIO, 0x0882, &mmMC_HUB_RDREQ_XDMAM[0], sizeof(mmMC_HUB_RDREQ_XDMAM)/sizeof(mmMC_HUB_RDREQ_XDMAM[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_DEBUG", REG_MMIO, 0x0891, &mmMC_VM_MB_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_DEBUG", REG_MMIO, 0x0893, &mmMC_VM_MB_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_STATUS", REG_MMIO, 0x0895, &mmMC_VM_MB_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB0_STATUS)/sizeof(mmMC_VM_MB_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB1_STATUS", REG_MMIO, 0x0896, &mmMC_VM_MB_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB1_STATUS)/sizeof(mmMC_VM_MB_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_STATUS", REG_MMIO, 0x0897, &mmMC_VM_MB_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB2_STATUS)/sizeof(mmMC_VM_MB_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L2ARBITER_L2_CREDITS", REG_MMIO, 0x08A1, &mmMC_VM_MB_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_DEBUG", REG_MMIO, 0x08A5, &mmMC_VM_MB_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_STATUS", REG_MMIO, 0x08A6, &mmMC_VM_MB_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB3_STATUS)/sizeof(mmMC_VM_MB_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR0", REG_MMIO, 0x08CD, &mmMC_XPB_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR1", REG_MMIO, 0x08CE, &mmMC_XPB_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR2", REG_MMIO, 0x08CF, &mmMC_XPB_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR3", REG_MMIO, 0x08D0, &mmMC_XPB_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR4", REG_MMIO, 0x08D1, &mmMC_XPB_RTR_SRC_APRTR4[0], sizeof(mmMC_XPB_RTR_SRC_APRTR4)/sizeof(mmMC_XPB_RTR_SRC_APRTR4[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR5", REG_MMIO, 0x08D2, &mmMC_XPB_RTR_SRC_APRTR5[0], sizeof(mmMC_XPB_RTR_SRC_APRTR5)/sizeof(mmMC_XPB_RTR_SRC_APRTR5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR6", REG_MMIO, 0x08D3, &mmMC_XPB_RTR_SRC_APRTR6[0], sizeof(mmMC_XPB_RTR_SRC_APRTR6)/sizeof(mmMC_XPB_RTR_SRC_APRTR6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR7", REG_MMIO, 0x08D4, &mmMC_XPB_RTR_SRC_APRTR7[0], sizeof(mmMC_XPB_RTR_SRC_APRTR7)/sizeof(mmMC_XPB_RTR_SRC_APRTR7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR8", REG_MMIO, 0x08D5, &mmMC_XPB_RTR_SRC_APRTR8[0], sizeof(mmMC_XPB_RTR_SRC_APRTR8)/sizeof(mmMC_XPB_RTR_SRC_APRTR8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR9", REG_MMIO, 0x08D6, &mmMC_XPB_RTR_SRC_APRTR9[0], sizeof(mmMC_XPB_RTR_SRC_APRTR9)/sizeof(mmMC_XPB_RTR_SRC_APRTR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR0", REG_MMIO, 0x08D7, &mmMC_XPB_XDMA_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR1", REG_MMIO, 0x08D8, &mmMC_XPB_XDMA_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR2", REG_MMIO, 0x08D9, &mmMC_XPB_XDMA_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR3", REG_MMIO, 0x08DA, &mmMC_XPB_XDMA_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP0", REG_MMIO, 0x08DB, &mmMC_XPB_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_RTR_DEST_MAP0)/sizeof(mmMC_XPB_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP1", REG_MMIO, 0x08DC, &mmMC_XPB_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_RTR_DEST_MAP1)/sizeof(mmMC_XPB_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP2", REG_MMIO, 0x08DD, &mmMC_XPB_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_RTR_DEST_MAP2)/sizeof(mmMC_XPB_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP3", REG_MMIO, 0x08DE, &mmMC_XPB_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_RTR_DEST_MAP3)/sizeof(mmMC_XPB_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP4", REG_MMIO, 0x08DF, &mmMC_XPB_RTR_DEST_MAP4[0], sizeof(mmMC_XPB_RTR_DEST_MAP4)/sizeof(mmMC_XPB_RTR_DEST_MAP4[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP5", REG_MMIO, 0x08E0, &mmMC_XPB_RTR_DEST_MAP5[0], sizeof(mmMC_XPB_RTR_DEST_MAP5)/sizeof(mmMC_XPB_RTR_DEST_MAP5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP6", REG_MMIO, 0x08E1, &mmMC_XPB_RTR_DEST_MAP6[0], sizeof(mmMC_XPB_RTR_DEST_MAP6)/sizeof(mmMC_XPB_RTR_DEST_MAP6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP7", REG_MMIO, 0x08E2, &mmMC_XPB_RTR_DEST_MAP7[0], sizeof(mmMC_XPB_RTR_DEST_MAP7)/sizeof(mmMC_XPB_RTR_DEST_MAP7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP8", REG_MMIO, 0x08E3, &mmMC_XPB_RTR_DEST_MAP8[0], sizeof(mmMC_XPB_RTR_DEST_MAP8)/sizeof(mmMC_XPB_RTR_DEST_MAP8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP9", REG_MMIO, 0x08E4, &mmMC_XPB_RTR_DEST_MAP9[0], sizeof(mmMC_XPB_RTR_DEST_MAP9)/sizeof(mmMC_XPB_RTR_DEST_MAP9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP0", REG_MMIO, 0x08E5, &mmMC_XPB_XDMA_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP1", REG_MMIO, 0x08E6, &mmMC_XPB_XDMA_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP2", REG_MMIO, 0x08E7, &mmMC_XPB_XDMA_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP3", REG_MMIO, 0x08E8, &mmMC_XPB_XDMA_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG0", REG_MMIO, 0x08E9, &mmMC_XPB_CLG_CFG0[0], sizeof(mmMC_XPB_CLG_CFG0)/sizeof(mmMC_XPB_CLG_CFG0[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG1", REG_MMIO, 0x08EA, &mmMC_XPB_CLG_CFG1[0], sizeof(mmMC_XPB_CLG_CFG1)/sizeof(mmMC_XPB_CLG_CFG1[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG2", REG_MMIO, 0x08EB, &mmMC_XPB_CLG_CFG2[0], sizeof(mmMC_XPB_CLG_CFG2)/sizeof(mmMC_XPB_CLG_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG3", REG_MMIO, 0x08EC, &mmMC_XPB_CLG_CFG3[0], sizeof(mmMC_XPB_CLG_CFG3)/sizeof(mmMC_XPB_CLG_CFG3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG4", REG_MMIO, 0x08ED, &mmMC_XPB_CLG_CFG4[0], sizeof(mmMC_XPB_CLG_CFG4)/sizeof(mmMC_XPB_CLG_CFG4[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG5", REG_MMIO, 0x08EE, &mmMC_XPB_CLG_CFG5[0], sizeof(mmMC_XPB_CLG_CFG5)/sizeof(mmMC_XPB_CLG_CFG5[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG6", REG_MMIO, 0x08EF, &mmMC_XPB_CLG_CFG6[0], sizeof(mmMC_XPB_CLG_CFG6)/sizeof(mmMC_XPB_CLG_CFG6[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG7", REG_MMIO, 0x08F0, &mmMC_XPB_CLG_CFG7[0], sizeof(mmMC_XPB_CLG_CFG7)/sizeof(mmMC_XPB_CLG_CFG7[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG8", REG_MMIO, 0x08F1, &mmMC_XPB_CLG_CFG8[0], sizeof(mmMC_XPB_CLG_CFG8)/sizeof(mmMC_XPB_CLG_CFG8[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG9", REG_MMIO, 0x08F2, &mmMC_XPB_CLG_CFG9[0], sizeof(mmMC_XPB_CLG_CFG9)/sizeof(mmMC_XPB_CLG_CFG9[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG10", REG_MMIO, 0x08F3, &mmMC_XPB_CLG_CFG10[0], sizeof(mmMC_XPB_CLG_CFG10)/sizeof(mmMC_XPB_CLG_CFG10[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG11", REG_MMIO, 0x08F4, &mmMC_XPB_CLG_CFG11[0], sizeof(mmMC_XPB_CLG_CFG11)/sizeof(mmMC_XPB_CLG_CFG11[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG12", REG_MMIO, 0x08F5, &mmMC_XPB_CLG_CFG12[0], sizeof(mmMC_XPB_CLG_CFG12)/sizeof(mmMC_XPB_CLG_CFG12[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG13", REG_MMIO, 0x08F6, &mmMC_XPB_CLG_CFG13[0], sizeof(mmMC_XPB_CLG_CFG13)/sizeof(mmMC_XPB_CLG_CFG13[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG14", REG_MMIO, 0x08F7, &mmMC_XPB_CLG_CFG14[0], sizeof(mmMC_XPB_CLG_CFG14)/sizeof(mmMC_XPB_CLG_CFG14[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG15", REG_MMIO, 0x08F8, &mmMC_XPB_CLG_CFG15[0], sizeof(mmMC_XPB_CLG_CFG15)/sizeof(mmMC_XPB_CLG_CFG15[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG16", REG_MMIO, 0x08F9, &mmMC_XPB_CLG_CFG16[0], sizeof(mmMC_XPB_CLG_CFG16)/sizeof(mmMC_XPB_CLG_CFG16[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG17", REG_MMIO, 0x08FA, &mmMC_XPB_CLG_CFG17[0], sizeof(mmMC_XPB_CLG_CFG17)/sizeof(mmMC_XPB_CLG_CFG17[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG18", REG_MMIO, 0x08FB, &mmMC_XPB_CLG_CFG18[0], sizeof(mmMC_XPB_CLG_CFG18)/sizeof(mmMC_XPB_CLG_CFG18[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG19", REG_MMIO, 0x08FC, &mmMC_XPB_CLG_CFG19[0], sizeof(mmMC_XPB_CLG_CFG19)/sizeof(mmMC_XPB_CLG_CFG19[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA", REG_MMIO, 0x08FD, &mmMC_XPB_CLG_EXTRA[0], sizeof(mmMC_XPB_CLG_EXTRA)/sizeof(mmMC_XPB_CLG_EXTRA[0]), 0, 0 },
+	{ "mmMC_XPB_LB_ADDR", REG_MMIO, 0x08FE, &mmMC_XPB_LB_ADDR[0], sizeof(mmMC_XPB_LB_ADDR)/sizeof(mmMC_XPB_LB_ADDR[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_HST", REG_MMIO, 0x08FF, &mmMC_XPB_UNC_THRESH_HST[0], sizeof(mmMC_XPB_UNC_THRESH_HST)/sizeof(mmMC_XPB_UNC_THRESH_HST[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_SID", REG_MMIO, 0x0900, &mmMC_XPB_UNC_THRESH_SID[0], sizeof(mmMC_XPB_UNC_THRESH_SID)/sizeof(mmMC_XPB_UNC_THRESH_SID[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_STS", REG_MMIO, 0x0901, &mmMC_XPB_WCB_STS[0], sizeof(mmMC_XPB_WCB_STS)/sizeof(mmMC_XPB_WCB_STS[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_CFG", REG_MMIO, 0x0902, &mmMC_XPB_WCB_CFG[0], sizeof(mmMC_XPB_WCB_CFG)/sizeof(mmMC_XPB_WCB_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_CFG", REG_MMIO, 0x0903, &mmMC_XPB_P2P_BAR_CFG[0], sizeof(mmMC_XPB_P2P_BAR_CFG)/sizeof(mmMC_XPB_P2P_BAR_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR0", REG_MMIO, 0x0904, &mmMC_XPB_P2P_BAR0[0], sizeof(mmMC_XPB_P2P_BAR0)/sizeof(mmMC_XPB_P2P_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR1", REG_MMIO, 0x0905, &mmMC_XPB_P2P_BAR1[0], sizeof(mmMC_XPB_P2P_BAR1)/sizeof(mmMC_XPB_P2P_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR2", REG_MMIO, 0x0906, &mmMC_XPB_P2P_BAR2[0], sizeof(mmMC_XPB_P2P_BAR2)/sizeof(mmMC_XPB_P2P_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR3", REG_MMIO, 0x0907, &mmMC_XPB_P2P_BAR3[0], sizeof(mmMC_XPB_P2P_BAR3)/sizeof(mmMC_XPB_P2P_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR4", REG_MMIO, 0x0908, &mmMC_XPB_P2P_BAR4[0], sizeof(mmMC_XPB_P2P_BAR4)/sizeof(mmMC_XPB_P2P_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR5", REG_MMIO, 0x0909, &mmMC_XPB_P2P_BAR5[0], sizeof(mmMC_XPB_P2P_BAR5)/sizeof(mmMC_XPB_P2P_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR6", REG_MMIO, 0x090A, &mmMC_XPB_P2P_BAR6[0], sizeof(mmMC_XPB_P2P_BAR6)/sizeof(mmMC_XPB_P2P_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR7", REG_MMIO, 0x090B, &mmMC_XPB_P2P_BAR7[0], sizeof(mmMC_XPB_P2P_BAR7)/sizeof(mmMC_XPB_P2P_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_SETUP", REG_MMIO, 0x090C, &mmMC_XPB_P2P_BAR_SETUP[0], sizeof(mmMC_XPB_P2P_BAR_SETUP)/sizeof(mmMC_XPB_P2P_BAR_SETUP[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DEBUG", REG_MMIO, 0x090D, &mmMC_XPB_P2P_BAR_DEBUG[0], sizeof(mmMC_XPB_P2P_BAR_DEBUG)/sizeof(mmMC_XPB_P2P_BAR_DEBUG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_ABOVE", REG_MMIO, 0x090E, &mmMC_XPB_P2P_BAR_DELTA_ABOVE[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE)/sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_BELOW", REG_MMIO, 0x090F, &mmMC_XPB_P2P_BAR_DELTA_BELOW[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW)/sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR0", REG_MMIO, 0x0910, &mmMC_XPB_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_PEER_SYS_BAR0)/sizeof(mmMC_XPB_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR1", REG_MMIO, 0x0911, &mmMC_XPB_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_PEER_SYS_BAR1)/sizeof(mmMC_XPB_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR2", REG_MMIO, 0x0912, &mmMC_XPB_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_PEER_SYS_BAR2)/sizeof(mmMC_XPB_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR3", REG_MMIO, 0x0913, &mmMC_XPB_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_PEER_SYS_BAR3)/sizeof(mmMC_XPB_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR4", REG_MMIO, 0x0914, &mmMC_XPB_PEER_SYS_BAR4[0], sizeof(mmMC_XPB_PEER_SYS_BAR4)/sizeof(mmMC_XPB_PEER_SYS_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR5", REG_MMIO, 0x0915, &mmMC_XPB_PEER_SYS_BAR5[0], sizeof(mmMC_XPB_PEER_SYS_BAR5)/sizeof(mmMC_XPB_PEER_SYS_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR6", REG_MMIO, 0x0916, &mmMC_XPB_PEER_SYS_BAR6[0], sizeof(mmMC_XPB_PEER_SYS_BAR6)/sizeof(mmMC_XPB_PEER_SYS_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR7", REG_MMIO, 0x0917, &mmMC_XPB_PEER_SYS_BAR7[0], sizeof(mmMC_XPB_PEER_SYS_BAR7)/sizeof(mmMC_XPB_PEER_SYS_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR8", REG_MMIO, 0x0918, &mmMC_XPB_PEER_SYS_BAR8[0], sizeof(mmMC_XPB_PEER_SYS_BAR8)/sizeof(mmMC_XPB_PEER_SYS_BAR8[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR9", REG_MMIO, 0x0919, &mmMC_XPB_PEER_SYS_BAR9[0], sizeof(mmMC_XPB_PEER_SYS_BAR9)/sizeof(mmMC_XPB_PEER_SYS_BAR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR0", REG_MMIO, 0x091A, &mmMC_XPB_XDMA_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR1", REG_MMIO, 0x091B, &mmMC_XPB_XDMA_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR2", REG_MMIO, 0x091C, &mmMC_XPB_XDMA_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR3", REG_MMIO, 0x091D, &mmMC_XPB_XDMA_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_CLK_GAT", REG_MMIO, 0x091E, &mmMC_XPB_CLK_GAT[0], sizeof(mmMC_XPB_CLK_GAT)/sizeof(mmMC_XPB_CLK_GAT[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG", REG_MMIO, 0x091F, &mmMC_XPB_INTF_CFG[0], sizeof(mmMC_XPB_INTF_CFG)/sizeof(mmMC_XPB_INTF_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_STS", REG_MMIO, 0x0920, &mmMC_XPB_INTF_STS[0], sizeof(mmMC_XPB_INTF_STS)/sizeof(mmMC_XPB_INTF_STS[0]), 0, 0 },
+	{ "mmMC_XPB_PIPE_STS", REG_MMIO, 0x0921, &mmMC_XPB_PIPE_STS[0], sizeof(mmMC_XPB_PIPE_STS)/sizeof(mmMC_XPB_PIPE_STS[0]), 0, 0 },
+	{ "mmMC_XPB_SUB_CTRL", REG_MMIO, 0x0922, &mmMC_XPB_SUB_CTRL[0], sizeof(mmMC_XPB_SUB_CTRL)/sizeof(mmMC_XPB_SUB_CTRL[0]), 0, 0 },
+	{ "mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB", REG_MMIO, 0x0923, &mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0], sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB)/sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0]), 0, 0 },
+	{ "mmMC_XPB_PERF_KNOBS", REG_MMIO, 0x0924, &mmMC_XPB_PERF_KNOBS[0], sizeof(mmMC_XPB_PERF_KNOBS)/sizeof(mmMC_XPB_PERF_KNOBS[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY", REG_MMIO, 0x0925, &mmMC_XPB_STICKY[0], sizeof(mmMC_XPB_STICKY)/sizeof(mmMC_XPB_STICKY[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY_W1C", REG_MMIO, 0x0926, &mmMC_XPB_STICKY_W1C[0], sizeof(mmMC_XPB_STICKY_W1C)/sizeof(mmMC_XPB_STICKY_W1C[0]), 0, 0 },
+	{ "mmMC_XPB_MISC_CFG", REG_MMIO, 0x0927, &mmMC_XPB_MISC_CFG[0], sizeof(mmMC_XPB_MISC_CFG)/sizeof(mmMC_XPB_MISC_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG20", REG_MMIO, 0x0928, &mmMC_XPB_CLG_CFG20[0], sizeof(mmMC_XPB_CLG_CFG20)/sizeof(mmMC_XPB_CLG_CFG20[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG21", REG_MMIO, 0x0929, &mmMC_XPB_CLG_CFG21[0], sizeof(mmMC_XPB_CLG_CFG21)/sizeof(mmMC_XPB_CLG_CFG21[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG22", REG_MMIO, 0x092A, &mmMC_XPB_CLG_CFG22[0], sizeof(mmMC_XPB_CLG_CFG22)/sizeof(mmMC_XPB_CLG_CFG22[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG23", REG_MMIO, 0x092B, &mmMC_XPB_CLG_CFG23[0], sizeof(mmMC_XPB_CLG_CFG23)/sizeof(mmMC_XPB_CLG_CFG23[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG24", REG_MMIO, 0x092C, &mmMC_XPB_CLG_CFG24[0], sizeof(mmMC_XPB_CLG_CFG24)/sizeof(mmMC_XPB_CLG_CFG24[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG25", REG_MMIO, 0x092D, &mmMC_XPB_CLG_CFG25[0], sizeof(mmMC_XPB_CLG_CFG25)/sizeof(mmMC_XPB_CLG_CFG25[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG26", REG_MMIO, 0x092E, &mmMC_XPB_CLG_CFG26[0], sizeof(mmMC_XPB_CLG_CFG26)/sizeof(mmMC_XPB_CLG_CFG26[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG27", REG_MMIO, 0x092F, &mmMC_XPB_CLG_CFG27[0], sizeof(mmMC_XPB_CLG_CFG27)/sizeof(mmMC_XPB_CLG_CFG27[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG28", REG_MMIO, 0x0930, &mmMC_XPB_CLG_CFG28[0], sizeof(mmMC_XPB_CLG_CFG28)/sizeof(mmMC_XPB_CLG_CFG28[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG29", REG_MMIO, 0x0931, &mmMC_XPB_CLG_CFG29[0], sizeof(mmMC_XPB_CLG_CFG29)/sizeof(mmMC_XPB_CLG_CFG29[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG30", REG_MMIO, 0x0932, &mmMC_XPB_CLG_CFG30[0], sizeof(mmMC_XPB_CLG_CFG30)/sizeof(mmMC_XPB_CLG_CFG30[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG31", REG_MMIO, 0x0933, &mmMC_XPB_CLG_CFG31[0], sizeof(mmMC_XPB_CLG_CFG31)/sizeof(mmMC_XPB_CLG_CFG31[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG2", REG_MMIO, 0x0934, &mmMC_XPB_INTF_CFG2[0], sizeof(mmMC_XPB_INTF_CFG2)/sizeof(mmMC_XPB_INTF_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA_RD", REG_MMIO, 0x0935, &mmMC_XPB_CLG_EXTRA_RD[0], sizeof(mmMC_XPB_CLG_EXTRA_RD)/sizeof(mmMC_XPB_CLG_EXTRA_RD[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG32", REG_MMIO, 0x0936, &mmMC_XPB_CLG_CFG32[0], sizeof(mmMC_XPB_CLG_CFG32)/sizeof(mmMC_XPB_CLG_CFG32[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG33", REG_MMIO, 0x0937, &mmMC_XPB_CLG_CFG33[0], sizeof(mmMC_XPB_CLG_CFG33)/sizeof(mmMC_XPB_CLG_CFG33[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG34", REG_MMIO, 0x0938, &mmMC_XPB_CLG_CFG34[0], sizeof(mmMC_XPB_CLG_CFG34)/sizeof(mmMC_XPB_CLG_CFG34[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG35", REG_MMIO, 0x0939, &mmMC_XPB_CLG_CFG35[0], sizeof(mmMC_XPB_CLG_CFG35)/sizeof(mmMC_XPB_CLG_CFG35[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG36", REG_MMIO, 0x093A, &mmMC_XPB_CLG_CFG36[0], sizeof(mmMC_XPB_CLG_CFG36)/sizeof(mmMC_XPB_CLG_CFG36[0]), 0, 0 },
+	{ "mmMC_RPB_CONF", REG_MMIO, 0x094D, &mmMC_RPB_CONF[0], sizeof(mmMC_RPB_CONF)/sizeof(mmMC_RPB_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_IF_CONF", REG_MMIO, 0x094E, &mmMC_RPB_IF_CONF[0], sizeof(mmMC_RPB_IF_CONF)/sizeof(mmMC_RPB_IF_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_DBG1", REG_MMIO, 0x094F, &mmMC_RPB_DBG1[0], sizeof(mmMC_RPB_DBG1)/sizeof(mmMC_RPB_DBG1[0]), 0, 0 },
+	{ "mmMC_RPB_EFF_CNTL", REG_MMIO, 0x0950, &mmMC_RPB_EFF_CNTL[0], sizeof(mmMC_RPB_EFF_CNTL)/sizeof(mmMC_RPB_EFF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_ARB_CNTL", REG_MMIO, 0x0951, &mmMC_RPB_ARB_CNTL[0], sizeof(mmMC_RPB_ARB_CNTL)/sizeof(mmMC_RPB_ARB_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_BIF_CNTL", REG_MMIO, 0x0952, &mmMC_RPB_BIF_CNTL[0], sizeof(mmMC_RPB_BIF_CNTL)/sizeof(mmMC_RPB_BIF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_SWITCH_CNTL", REG_MMIO, 0x0953, &mmMC_RPB_WR_SWITCH_CNTL[0], sizeof(mmMC_RPB_WR_SWITCH_CNTL)/sizeof(mmMC_RPB_WR_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_COMBINE_CNTL", REG_MMIO, 0x0954, &mmMC_RPB_WR_COMBINE_CNTL[0], sizeof(mmMC_RPB_WR_COMBINE_CNTL)/sizeof(mmMC_RPB_WR_COMBINE_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_RD_SWITCH_CNTL", REG_MMIO, 0x0955, &mmMC_RPB_RD_SWITCH_CNTL[0], sizeof(mmMC_RPB_RD_SWITCH_CNTL)/sizeof(mmMC_RPB_RD_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_WR", REG_MMIO, 0x0956, &mmMC_RPB_CID_QUEUE_WR[0], sizeof(mmMC_RPB_CID_QUEUE_WR)/sizeof(mmMC_RPB_CID_QUEUE_WR[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_RD", REG_MMIO, 0x0957, &mmMC_RPB_CID_QUEUE_RD[0], sizeof(mmMC_RPB_CID_QUEUE_RD)/sizeof(mmMC_RPB_CID_QUEUE_RD[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_CNTL", REG_MMIO, 0x0958, &mmMC_RPB_PERF_COUNTER_CNTL[0], sizeof(mmMC_RPB_PERF_COUNTER_CNTL)/sizeof(mmMC_RPB_PERF_COUNTER_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_STATUS", REG_MMIO, 0x0959, &mmMC_RPB_PERF_COUNTER_STATUS[0], sizeof(mmMC_RPB_PERF_COUNTER_STATUS)/sizeof(mmMC_RPB_PERF_COUNTER_STATUS[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX", REG_MMIO, 0x095A, &mmMC_RPB_CID_QUEUE_EX[0], sizeof(mmMC_RPB_CID_QUEUE_EX)/sizeof(mmMC_RPB_CID_QUEUE_EX[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX_DATA", REG_MMIO, 0x095B, &mmMC_RPB_CID_QUEUE_EX_DATA[0], sizeof(mmMC_RPB_CID_QUEUE_EX_DATA)/sizeof(mmMC_RPB_CID_QUEUE_EX_DATA[0]), 0, 0 },
+	{ "mmMC_CITF_XTRA_ENABLE", REG_MMIO, 0x096D, &mmMC_CITF_XTRA_ENABLE[0], sizeof(mmMC_CITF_XTRA_ENABLE)/sizeof(mmMC_CITF_XTRA_ENABLE[0]), 0, 0 },
+	{ "mmCC_MC_MAX_CHANNEL", REG_MMIO, 0x096E, &mmCC_MC_MAX_CHANNEL[0], sizeof(mmCC_MC_MAX_CHANNEL)/sizeof(mmCC_MC_MAX_CHANNEL[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG", REG_MMIO, 0x096F, &mmMC_CG_CONFIG[0], sizeof(mmMC_CG_CONFIG)/sizeof(mmMC_CG_CONFIG[0]), 0, 0 },
+	{ "mmMC_CITF_CNTL", REG_MMIO, 0x0970, &mmMC_CITF_CNTL[0], sizeof(mmMC_CITF_CNTL)/sizeof(mmMC_CITF_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_VM", REG_MMIO, 0x0971, &mmMC_CITF_CREDITS_VM[0], sizeof(mmMC_CITF_CREDITS_VM)/sizeof(mmMC_CITF_CREDITS_VM[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_RD", REG_MMIO, 0x0972, &mmMC_CITF_CREDITS_ARB_RD[0], sizeof(mmMC_CITF_CREDITS_ARB_RD)/sizeof(mmMC_CITF_CREDITS_ARB_RD[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_WR", REG_MMIO, 0x0973, &mmMC_CITF_CREDITS_ARB_WR[0], sizeof(mmMC_CITF_CREDITS_ARB_WR)/sizeof(mmMC_CITF_CREDITS_ARB_WR[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_CNTL", REG_MMIO, 0x0974, &mmMC_CITF_DAGB_CNTL[0], sizeof(mmMC_CITF_DAGB_CNTL)/sizeof(mmMC_CITF_DAGB_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS", REG_MMIO, 0x0975, &mmMC_CITF_INT_CREDITS[0], sizeof(mmMC_CITF_INT_CREDITS)/sizeof(mmMC_CITF_INT_CREDITS[0]), 0, 0 },
+	{ "mmMC_CITF_RET_MODE", REG_MMIO, 0x0976, &mmMC_CITF_RET_MODE[0], sizeof(mmMC_CITF_RET_MODE)/sizeof(mmMC_CITF_RET_MODE[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_DLY", REG_MMIO, 0x0977, &mmMC_CITF_DAGB_DLY[0], sizeof(mmMC_CITF_DAGB_DLY)/sizeof(mmMC_CITF_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_RD_GRP_EXT", REG_MMIO, 0x0978, &mmMC_RD_GRP_EXT[0], sizeof(mmMC_RD_GRP_EXT)/sizeof(mmMC_RD_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_WR_GRP_EXT", REG_MMIO, 0x0979, &mmMC_WR_GRP_EXT[0], sizeof(mmMC_WR_GRP_EXT)/sizeof(mmMC_WR_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_CITF_REMREQ", REG_MMIO, 0x097A, &mmMC_CITF_REMREQ[0], sizeof(mmMC_CITF_REMREQ)/sizeof(mmMC_CITF_REMREQ[0]), 0, 0 },
+	{ "mmMC_WR_TC0", REG_MMIO, 0x097B, &mmMC_WR_TC0[0], sizeof(mmMC_WR_TC0)/sizeof(mmMC_WR_TC0[0]), 0, 0 },
+	{ "mmMC_WR_TC1", REG_MMIO, 0x097C, &mmMC_WR_TC1[0], sizeof(mmMC_WR_TC1)/sizeof(mmMC_WR_TC1[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS_WR", REG_MMIO, 0x097D, &mmMC_CITF_INT_CREDITS_WR[0], sizeof(mmMC_CITF_INT_CREDITS_WR)/sizeof(mmMC_CITF_INT_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_RD_CNTL", REG_MMIO, 0x097F, &mmMC_CITF_WTM_RD_CNTL[0], sizeof(mmMC_CITF_WTM_RD_CNTL)/sizeof(mmMC_CITF_WTM_RD_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_WR_CNTL", REG_MMIO, 0x0980, &mmMC_CITF_WTM_WR_CNTL[0], sizeof(mmMC_CITF_WTM_WR_CNTL)/sizeof(mmMC_CITF_WTM_WR_CNTL[0]), 0, 0 },
+	{ "mmMC_RD_CB", REG_MMIO, 0x0981, &mmMC_RD_CB[0], sizeof(mmMC_RD_CB)/sizeof(mmMC_RD_CB[0]), 0, 0 },
+	{ "mmMC_RD_DB", REG_MMIO, 0x0982, &mmMC_RD_DB[0], sizeof(mmMC_RD_DB)/sizeof(mmMC_RD_DB[0]), 0, 0 },
+	{ "mmMC_RD_TC0", REG_MMIO, 0x0983, &mmMC_RD_TC0[0], sizeof(mmMC_RD_TC0)/sizeof(mmMC_RD_TC0[0]), 0, 0 },
+	{ "mmMC_RD_TC1", REG_MMIO, 0x0984, &mmMC_RD_TC1[0], sizeof(mmMC_RD_TC1)/sizeof(mmMC_RD_TC1[0]), 0, 0 },
+	{ "mmMC_RD_HUB", REG_MMIO, 0x0985, &mmMC_RD_HUB[0], sizeof(mmMC_RD_HUB)/sizeof(mmMC_RD_HUB[0]), 0, 0 },
+	{ "mmMC_WR_CB", REG_MMIO, 0x0986, &mmMC_WR_CB[0], sizeof(mmMC_WR_CB)/sizeof(mmMC_WR_CB[0]), 0, 0 },
+	{ "mmMC_WR_DB", REG_MMIO, 0x0987, &mmMC_WR_DB[0], sizeof(mmMC_WR_DB)/sizeof(mmMC_WR_DB[0]), 0, 0 },
+	{ "mmMC_WR_HUB", REG_MMIO, 0x0988, &mmMC_WR_HUB[0], sizeof(mmMC_WR_HUB)/sizeof(mmMC_WR_HUB[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_XBAR", REG_MMIO, 0x0989, &mmMC_CITF_CREDITS_XBAR[0], sizeof(mmMC_CITF_CREDITS_XBAR)/sizeof(mmMC_CITF_CREDITS_XBAR[0]), 0, 0 },
+	{ "mmMC_RD_GRP_LCL", REG_MMIO, 0x098A, &mmMC_RD_GRP_LCL[0], sizeof(mmMC_RD_GRP_LCL)/sizeof(mmMC_RD_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_WR_GRP_LCL", REG_MMIO, 0x098B, &mmMC_WR_GRP_LCL[0], sizeof(mmMC_WR_GRP_LCL)/sizeof(mmMC_WR_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_CNTL2", REG_MMIO, 0x098E, &mmMC_CITF_PERF_MON_CNTL2[0], sizeof(mmMC_CITF_PERF_MON_CNTL2)/sizeof(mmMC_CITF_PERF_MON_CNTL2[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_RSLT2", REG_MMIO, 0x0991, &mmMC_CITF_PERF_MON_RSLT2[0], sizeof(mmMC_CITF_PERF_MON_RSLT2)/sizeof(mmMC_CITF_PERF_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_RD_CG", REG_MMIO, 0x0992, &mmMC_CITF_MISC_RD_CG[0], sizeof(mmMC_CITF_MISC_RD_CG)/sizeof(mmMC_CITF_MISC_RD_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_WR_CG", REG_MMIO, 0x0993, &mmMC_CITF_MISC_WR_CG[0], sizeof(mmMC_CITF_MISC_WR_CG)/sizeof(mmMC_CITF_MISC_WR_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_VM_CG", REG_MMIO, 0x0994, &mmMC_CITF_MISC_VM_CG[0], sizeof(mmMC_CITF_MISC_VM_CG)/sizeof(mmMC_CITF_MISC_VM_CG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_DEBUG", REG_MMIO, 0x0998, &mmMC_VM_MD_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_DEBUG", REG_MMIO, 0x0999, &mmMC_VM_MD_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB1_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_DEBUG", REG_MMIO, 0x099A, &mmMC_VM_MD_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_STATUS", REG_MMIO, 0x099B, &mmMC_VM_MD_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB0_STATUS)/sizeof(mmMC_VM_MD_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_STATUS", REG_MMIO, 0x099C, &mmMC_VM_MD_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB1_STATUS)/sizeof(mmMC_VM_MD_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_STATUS", REG_MMIO, 0x099D, &mmMC_VM_MD_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB2_STATUS)/sizeof(mmMC_VM_MD_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L2ARBITER_L2_CREDITS", REG_MMIO, 0x09A4, &mmMC_VM_MD_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_DEBUG", REG_MMIO, 0x09A7, &mmMC_VM_MD_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_STATUS", REG_MMIO, 0x09A8, &mmMC_VM_MD_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB3_STATUS)/sizeof(mmMC_VM_MD_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_FED_CNTL", REG_MMIO, 0x09C1, &mmMC_ARB_FED_CNTL[0], sizeof(mmMC_ARB_FED_CNTL)/sizeof(mmMC_ARB_FED_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_STATUS", REG_MMIO, 0x09C2, &mmMC_ARB_GECC2_STATUS[0], sizeof(mmMC_ARB_GECC2_STATUS)/sizeof(mmMC_ARB_GECC2_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_MISC", REG_MMIO, 0x09C3, &mmMC_ARB_GECC2_MISC[0], sizeof(mmMC_ARB_GECC2_MISC)/sizeof(mmMC_ARB_GECC2_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG", REG_MMIO, 0x09C4, &mmMC_ARB_GECC2_DEBUG[0], sizeof(mmMC_ARB_GECC2_DEBUG)/sizeof(mmMC_ARB_GECC2_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG2", REG_MMIO, 0x09C5, &mmMC_ARB_GECC2_DEBUG2[0], sizeof(mmMC_ARB_GECC2_DEBUG2)/sizeof(mmMC_ARB_GECC2_DEBUG2[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2", REG_MMIO, 0x09C9, &mmMC_ARB_GECC2[0], sizeof(mmMC_ARB_GECC2)/sizeof(mmMC_ARB_GECC2[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_CLI", REG_MMIO, 0x09CA, &mmMC_ARB_GECC2_CLI[0], sizeof(mmMC_ARB_GECC2_CLI)/sizeof(mmMC_ARB_GECC2_CLI[0]), 0, 0 },
+	{ "mmMC_ARB_WCDR_2", REG_MMIO, 0x09CE, &mmMC_ARB_WCDR_2[0], sizeof(mmMC_ARB_WCDR_2)/sizeof(mmMC_ARB_WCDR_2[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DATA", REG_MMIO, 0x09CF, &mmMC_ARB_RTT_DATA[0], sizeof(mmMC_ARB_RTT_DATA)/sizeof(mmMC_ARB_RTT_DATA[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL0", REG_MMIO, 0x09D0, &mmMC_ARB_RTT_CNTL0[0], sizeof(mmMC_ARB_RTT_CNTL0)/sizeof(mmMC_ARB_RTT_CNTL0[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL1", REG_MMIO, 0x09D1, &mmMC_ARB_RTT_CNTL1[0], sizeof(mmMC_ARB_RTT_CNTL1)/sizeof(mmMC_ARB_RTT_CNTL1[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL2", REG_MMIO, 0x09D2, &mmMC_ARB_RTT_CNTL2[0], sizeof(mmMC_ARB_RTT_CNTL2)/sizeof(mmMC_ARB_RTT_CNTL2[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DEBUG", REG_MMIO, 0x09D3, &mmMC_ARB_RTT_DEBUG[0], sizeof(mmMC_ARB_RTT_DEBUG)/sizeof(mmMC_ARB_RTT_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_CAC_CNTL", REG_MMIO, 0x09D4, &mmMC_ARB_CAC_CNTL[0], sizeof(mmMC_ARB_CAC_CNTL)/sizeof(mmMC_ARB_CAC_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_MISC2", REG_MMIO, 0x09D5, &mmMC_ARB_MISC2[0], sizeof(mmMC_ARB_MISC2)/sizeof(mmMC_ARB_MISC2[0]), 0, 0 },
+	{ "mmMC_ARB_MISC", REG_MMIO, 0x09D6, &mmMC_ARB_MISC[0], sizeof(mmMC_ARB_MISC)/sizeof(mmMC_ARB_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_BANKMAP", REG_MMIO, 0x09D7, &mmMC_ARB_BANKMAP[0], sizeof(mmMC_ARB_BANKMAP)/sizeof(mmMC_ARB_BANKMAP[0]), 0, 0 },
+	{ "mmMC_ARB_RAMCFG", REG_MMIO, 0x09D8, &mmMC_ARB_RAMCFG[0], sizeof(mmMC_ARB_RAMCFG)/sizeof(mmMC_ARB_RAMCFG[0]), 0, 0 },
+	{ "mmMC_ARB_POP", REG_MMIO, 0x09D9, &mmMC_ARB_POP[0], sizeof(mmMC_ARB_POP)/sizeof(mmMC_ARB_POP[0]), 0, 0 },
+	{ "mmMC_ARB_MINCLKS", REG_MMIO, 0x09DA, &mmMC_ARB_MINCLKS[0], sizeof(mmMC_ARB_MINCLKS)/sizeof(mmMC_ARB_MINCLKS[0]), 0, 0 },
+	{ "mmMC_ARB_SQM_CNTL", REG_MMIO, 0x09DB, &mmMC_ARB_SQM_CNTL[0], sizeof(mmMC_ARB_SQM_CNTL)/sizeof(mmMC_ARB_SQM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_HASH", REG_MMIO, 0x09DC, &mmMC_ARB_ADDR_HASH[0], sizeof(mmMC_ARB_ADDR_HASH)/sizeof(mmMC_ARB_ADDR_HASH[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING", REG_MMIO, 0x09DD, &mmMC_ARB_DRAM_TIMING[0], sizeof(mmMC_ARB_DRAM_TIMING)/sizeof(mmMC_ARB_DRAM_TIMING[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2", REG_MMIO, 0x09DE, &mmMC_ARB_DRAM_TIMING2[0], sizeof(mmMC_ARB_DRAM_TIMING2)/sizeof(mmMC_ARB_DRAM_TIMING2[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_RD", REG_MMIO, 0x09DF, &mmMC_ARB_WTM_CNTL_RD[0], sizeof(mmMC_ARB_WTM_CNTL_RD)/sizeof(mmMC_ARB_WTM_CNTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_WR", REG_MMIO, 0x09E0, &mmMC_ARB_WTM_CNTL_WR[0], sizeof(mmMC_ARB_WTM_CNTL_WR)/sizeof(mmMC_ARB_WTM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_RD", REG_MMIO, 0x09E1, &mmMC_ARB_WTM_GRPWT_RD[0], sizeof(mmMC_ARB_WTM_GRPWT_RD)/sizeof(mmMC_ARB_WTM_GRPWT_RD[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_WR", REG_MMIO, 0x09E2, &mmMC_ARB_WTM_GRPWT_WR[0], sizeof(mmMC_ARB_WTM_GRPWT_WR)/sizeof(mmMC_ARB_WTM_GRPWT_WR[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_RD", REG_MMIO, 0x09E3, &mmMC_ARB_TM_CNTL_RD[0], sizeof(mmMC_ARB_TM_CNTL_RD)/sizeof(mmMC_ARB_TM_CNTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_WR", REG_MMIO, 0x09E4, &mmMC_ARB_TM_CNTL_WR[0], sizeof(mmMC_ARB_TM_CNTL_WR)/sizeof(mmMC_ARB_TM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_RD", REG_MMIO, 0x09E5, &mmMC_ARB_LAZY0_RD[0], sizeof(mmMC_ARB_LAZY0_RD)/sizeof(mmMC_ARB_LAZY0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_WR", REG_MMIO, 0x09E6, &mmMC_ARB_LAZY0_WR[0], sizeof(mmMC_ARB_LAZY0_WR)/sizeof(mmMC_ARB_LAZY0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_RD", REG_MMIO, 0x09E7, &mmMC_ARB_LAZY1_RD[0], sizeof(mmMC_ARB_LAZY1_RD)/sizeof(mmMC_ARB_LAZY1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_WR", REG_MMIO, 0x09E8, &mmMC_ARB_LAZY1_WR[0], sizeof(mmMC_ARB_LAZY1_WR)/sizeof(mmMC_ARB_LAZY1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_RD", REG_MMIO, 0x09E9, &mmMC_ARB_AGE_RD[0], sizeof(mmMC_ARB_AGE_RD)/sizeof(mmMC_ARB_AGE_RD[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_WR", REG_MMIO, 0x09EA, &mmMC_ARB_AGE_WR[0], sizeof(mmMC_ARB_AGE_WR)/sizeof(mmMC_ARB_AGE_WR[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_CNTL", REG_MMIO, 0x09EB, &mmMC_ARB_RFSH_CNTL[0], sizeof(mmMC_ARB_RFSH_CNTL)/sizeof(mmMC_ARB_RFSH_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_RATE", REG_MMIO, 0x09EC, &mmMC_ARB_RFSH_RATE[0], sizeof(mmMC_ARB_RFSH_RATE)/sizeof(mmMC_ARB_RFSH_RATE[0]), 0, 0 },
+	{ "mmMC_ARB_PM_CNTL", REG_MMIO, 0x09ED, &mmMC_ARB_PM_CNTL[0], sizeof(mmMC_ARB_PM_CNTL)/sizeof(mmMC_ARB_PM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_RD_CNTL", REG_MMIO, 0x09EE, &mmMC_ARB_GDEC_RD_CNTL[0], sizeof(mmMC_ARB_GDEC_RD_CNTL)/sizeof(mmMC_ARB_GDEC_RD_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_WR_CNTL", REG_MMIO, 0x09EF, &mmMC_ARB_GDEC_WR_CNTL[0], sizeof(mmMC_ARB_GDEC_WR_CNTL)/sizeof(mmMC_ARB_GDEC_WR_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_LM_RD", REG_MMIO, 0x09F0, &mmMC_ARB_LM_RD[0], sizeof(mmMC_ARB_LM_RD)/sizeof(mmMC_ARB_LM_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LM_WR", REG_MMIO, 0x09F1, &mmMC_ARB_LM_WR[0], sizeof(mmMC_ARB_LM_WR)/sizeof(mmMC_ARB_LM_WR[0]), 0, 0 },
+	{ "mmMC_ARB_REMREQ", REG_MMIO, 0x09F2, &mmMC_ARB_REMREQ[0], sizeof(mmMC_ARB_REMREQ)/sizeof(mmMC_ARB_REMREQ[0]), 0, 0 },
+	{ "mmMC_ARB_REPLAY", REG_MMIO, 0x09F3, &mmMC_ARB_REPLAY[0], sizeof(mmMC_ARB_REPLAY)/sizeof(mmMC_ARB_REPLAY[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_RD", REG_MMIO, 0x09F4, &mmMC_ARB_RET_CREDITS_RD[0], sizeof(mmMC_ARB_RET_CREDITS_RD)/sizeof(mmMC_ARB_RET_CREDITS_RD[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_WR", REG_MMIO, 0x09F5, &mmMC_ARB_RET_CREDITS_WR[0], sizeof(mmMC_ARB_RET_CREDITS_WR)/sizeof(mmMC_ARB_RET_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_ARB_CG", REG_MMIO, 0x09FA, &mmMC_ARB_CG[0], sizeof(mmMC_ARB_CG)/sizeof(mmMC_ARB_CG[0]), 0, 0 },
+	{ "mmMC_ARB_WCDR", REG_MMIO, 0x09FB, &mmMC_ARB_WCDR[0], sizeof(mmMC_ARB_WCDR)/sizeof(mmMC_ARB_WCDR[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING_1", REG_MMIO, 0x09FC, &mmMC_ARB_DRAM_TIMING_1[0], sizeof(mmMC_ARB_DRAM_TIMING_1)/sizeof(mmMC_ARB_DRAM_TIMING_1[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2_1", REG_MMIO, 0x09FF, &mmMC_ARB_DRAM_TIMING2_1[0], sizeof(mmMC_ARB_DRAM_TIMING2_1)/sizeof(mmMC_ARB_DRAM_TIMING2_1[0]), 0, 0 },
+	{ "mmMC_ARB_BURST_TIME", REG_MMIO, 0x0A02, &mmMC_ARB_BURST_TIME[0], sizeof(mmMC_ARB_BURST_TIME)/sizeof(mmMC_ARB_BURST_TIME[0]), 0, 0 },
+	{ "mmMC_BIST_CNTL", REG_MMIO, 0x0A05, &mmMC_BIST_CNTL[0], sizeof(mmMC_BIST_CNTL)/sizeof(mmMC_BIST_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_AUTO_CNTL", REG_MMIO, 0x0A06, &mmMC_BIST_AUTO_CNTL[0], sizeof(mmMC_BIST_AUTO_CNTL)/sizeof(mmMC_BIST_AUTO_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_DIR_CNTL", REG_MMIO, 0x0A07, &mmMC_BIST_DIR_CNTL[0], sizeof(mmMC_BIST_DIR_CNTL)/sizeof(mmMC_BIST_DIR_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_SADDR", REG_MMIO, 0x0A08, &mmMC_BIST_SADDR[0], sizeof(mmMC_BIST_SADDR)/sizeof(mmMC_BIST_SADDR[0]), 0, 0 },
+	{ "mmMC_BIST_EADDR", REG_MMIO, 0x0A09, &mmMC_BIST_EADDR[0], sizeof(mmMC_BIST_EADDR)/sizeof(mmMC_BIST_EADDR[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD0", REG_MMIO, 0x0A0A, &mmMC_BIST_DATA_WORD0[0], sizeof(mmMC_BIST_DATA_WORD0)/sizeof(mmMC_BIST_DATA_WORD0[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD1", REG_MMIO, 0x0A0B, &mmMC_BIST_DATA_WORD1[0], sizeof(mmMC_BIST_DATA_WORD1)/sizeof(mmMC_BIST_DATA_WORD1[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD2", REG_MMIO, 0x0A0C, &mmMC_BIST_DATA_WORD2[0], sizeof(mmMC_BIST_DATA_WORD2)/sizeof(mmMC_BIST_DATA_WORD2[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD3", REG_MMIO, 0x0A0D, &mmMC_BIST_DATA_WORD3[0], sizeof(mmMC_BIST_DATA_WORD3)/sizeof(mmMC_BIST_DATA_WORD3[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD4", REG_MMIO, 0x0A0E, &mmMC_BIST_DATA_WORD4[0], sizeof(mmMC_BIST_DATA_WORD4)/sizeof(mmMC_BIST_DATA_WORD4[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD5", REG_MMIO, 0x0A0F, &mmMC_BIST_DATA_WORD5[0], sizeof(mmMC_BIST_DATA_WORD5)/sizeof(mmMC_BIST_DATA_WORD5[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD6", REG_MMIO, 0x0A10, &mmMC_BIST_DATA_WORD6[0], sizeof(mmMC_BIST_DATA_WORD6)/sizeof(mmMC_BIST_DATA_WORD6[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD7", REG_MMIO, 0x0A11, &mmMC_BIST_DATA_WORD7[0], sizeof(mmMC_BIST_DATA_WORD7)/sizeof(mmMC_BIST_DATA_WORD7[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_MASK", REG_MMIO, 0x0A12, &mmMC_BIST_DATA_MASK[0], sizeof(mmMC_BIST_DATA_MASK)/sizeof(mmMC_BIST_DATA_MASK[0]), 0, 0 },
+	{ "mmMC_BIST_MISMATCH_ADDR", REG_MMIO, 0x0A13, &mmMC_BIST_MISMATCH_ADDR[0], sizeof(mmMC_BIST_MISMATCH_ADDR)/sizeof(mmMC_BIST_MISMATCH_ADDR[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD0", REG_MMIO, 0x0A14, &mmMC_BIST_RDATA_WORD0[0], sizeof(mmMC_BIST_RDATA_WORD0)/sizeof(mmMC_BIST_RDATA_WORD0[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD1", REG_MMIO, 0x0A15, &mmMC_BIST_RDATA_WORD1[0], sizeof(mmMC_BIST_RDATA_WORD1)/sizeof(mmMC_BIST_RDATA_WORD1[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD2", REG_MMIO, 0x0A16, &mmMC_BIST_RDATA_WORD2[0], sizeof(mmMC_BIST_RDATA_WORD2)/sizeof(mmMC_BIST_RDATA_WORD2[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD3", REG_MMIO, 0x0A17, &mmMC_BIST_RDATA_WORD3[0], sizeof(mmMC_BIST_RDATA_WORD3)/sizeof(mmMC_BIST_RDATA_WORD3[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD4", REG_MMIO, 0x0A18, &mmMC_BIST_RDATA_WORD4[0], sizeof(mmMC_BIST_RDATA_WORD4)/sizeof(mmMC_BIST_RDATA_WORD4[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD5", REG_MMIO, 0x0A19, &mmMC_BIST_RDATA_WORD5[0], sizeof(mmMC_BIST_RDATA_WORD5)/sizeof(mmMC_BIST_RDATA_WORD5[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD6", REG_MMIO, 0x0A1A, &mmMC_BIST_RDATA_WORD6[0], sizeof(mmMC_BIST_RDATA_WORD6)/sizeof(mmMC_BIST_RDATA_WORD6[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD7", REG_MMIO, 0x0A1B, &mmMC_BIST_RDATA_WORD7[0], sizeof(mmMC_BIST_RDATA_WORD7)/sizeof(mmMC_BIST_RDATA_WORD7[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_MASK", REG_MMIO, 0x0A1C, &mmMC_BIST_RDATA_MASK[0], sizeof(mmMC_BIST_RDATA_MASK)/sizeof(mmMC_BIST_RDATA_MASK[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_EDC", REG_MMIO, 0x0A1D, &mmMC_BIST_RDATA_EDC[0], sizeof(mmMC_BIST_RDATA_EDC)/sizeof(mmMC_BIST_RDATA_EDC[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_0_S", REG_MMIO, 0x0A1E, &mmMC_SEQ_RESERVE_0_S[0], sizeof(mmMC_SEQ_RESERVE_0_S)/sizeof(mmMC_SEQ_RESERVE_0_S[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_1_S", REG_MMIO, 0x0A1F, &mmMC_SEQ_RESERVE_1_S[0], sizeof(mmMC_SEQ_RESERVE_1_S)/sizeof(mmMC_SEQ_RESERVE_1_S[0]), 0, 0 },
+	{ "mmMC_SEQ_STATUS_S", REG_MMIO, 0x0A20, &mmMC_SEQ_STATUS_S[0], sizeof(mmMC_SEQ_STATUS_S)/sizeof(mmMC_SEQ_STATUS_S[0]), 0, 0 },
+	{ "mmMC_CG_DATAPORT", REG_MMIO, 0x0A21, &mmMC_CG_DATAPORT[0], sizeof(mmMC_CG_DATAPORT)/sizeof(mmMC_CG_DATAPORT[0]), 0, 0 },
+	{ "mmMC_SEQ_MPLL_OVERRIDE", REG_MMIO, 0x0A22, &mmMC_SEQ_MPLL_OVERRIDE[0], sizeof(mmMC_SEQ_MPLL_OVERRIDE)/sizeof(mmMC_SEQ_MPLL_OVERRIDE[0]), 0, 0 },
+	{ "mmMC_SEQ_CNTL", REG_MMIO, 0x0A25, &mmMC_SEQ_CNTL[0], sizeof(mmMC_SEQ_CNTL)/sizeof(mmMC_SEQ_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM", REG_MMIO, 0x0A26, &mmMC_SEQ_DRAM[0], sizeof(mmMC_SEQ_DRAM)/sizeof(mmMC_SEQ_DRAM[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM_2", REG_MMIO, 0x0A27, &mmMC_SEQ_DRAM_2[0], sizeof(mmMC_SEQ_DRAM_2)/sizeof(mmMC_SEQ_DRAM_2[0]), 0, 0 },
+	{ "mmMC_SEQ_RAS_TIMING", REG_MMIO, 0x0A28, &mmMC_SEQ_RAS_TIMING[0], sizeof(mmMC_SEQ_RAS_TIMING)/sizeof(mmMC_SEQ_RAS_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_CAS_TIMING", REG_MMIO, 0x0A29, &mmMC_SEQ_CAS_TIMING[0], sizeof(mmMC_SEQ_CAS_TIMING)/sizeof(mmMC_SEQ_CAS_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING", REG_MMIO, 0x0A2A, &mmMC_SEQ_MISC_TIMING[0], sizeof(mmMC_SEQ_MISC_TIMING)/sizeof(mmMC_SEQ_MISC_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING2", REG_MMIO, 0x0A2B, &mmMC_SEQ_MISC_TIMING2[0], sizeof(mmMC_SEQ_MISC_TIMING2)/sizeof(mmMC_SEQ_MISC_TIMING2[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_TIMING", REG_MMIO, 0x0A2C, &mmMC_SEQ_PMG_TIMING[0], sizeof(mmMC_SEQ_PMG_TIMING)/sizeof(mmMC_SEQ_PMG_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D0", REG_MMIO, 0x0A2D, &mmMC_SEQ_RD_CTL_D0[0], sizeof(mmMC_SEQ_RD_CTL_D0)/sizeof(mmMC_SEQ_RD_CTL_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D1", REG_MMIO, 0x0A2E, &mmMC_SEQ_RD_CTL_D1[0], sizeof(mmMC_SEQ_RD_CTL_D1)/sizeof(mmMC_SEQ_RD_CTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D0", REG_MMIO, 0x0A2F, &mmMC_SEQ_WR_CTL_D0[0], sizeof(mmMC_SEQ_WR_CTL_D0)/sizeof(mmMC_SEQ_WR_CTL_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D1", REG_MMIO, 0x0A30, &mmMC_SEQ_WR_CTL_D1[0], sizeof(mmMC_SEQ_WR_CTL_D1)/sizeof(mmMC_SEQ_WR_CTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_CMD", REG_MMIO, 0x0A31, &mmMC_SEQ_CMD[0], sizeof(mmMC_SEQ_CMD)/sizeof(mmMC_SEQ_CMD[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_CNTL", REG_MMIO, 0x0A32, &mmMC_SEQ_SUP_CNTL[0], sizeof(mmMC_SEQ_SUP_CNTL)/sizeof(mmMC_SEQ_SUP_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_PGM", REG_MMIO, 0x0A33, &mmMC_SEQ_SUP_PGM[0], sizeof(mmMC_SEQ_SUP_PGM)/sizeof(mmMC_SEQ_SUP_PGM[0]), 0, 0 },
+	{ "mmMC_PMG_AUTO_CMD", REG_MMIO, 0x0A34, &mmMC_PMG_AUTO_CMD[0], sizeof(mmMC_PMG_AUTO_CMD)/sizeof(mmMC_PMG_AUTO_CMD[0]), 0, 0 },
+	{ "mmMC_PMG_AUTO_CFG", REG_MMIO, 0x0A35, &mmMC_PMG_AUTO_CFG[0], sizeof(mmMC_PMG_AUTO_CFG)/sizeof(mmMC_PMG_AUTO_CFG[0]), 0, 0 },
+	{ "mmMC_IMP_CNTL", REG_MMIO, 0x0A36, &mmMC_IMP_CNTL[0], sizeof(mmMC_IMP_CNTL)/sizeof(mmMC_IMP_CNTL[0]), 0, 0 },
+	{ "mmMC_IMP_DEBUG", REG_MMIO, 0x0A37, &mmMC_IMP_DEBUG[0], sizeof(mmMC_IMP_DEBUG)/sizeof(mmMC_IMP_DEBUG[0]), 0, 0 },
+	{ "mmMC_IMP_STATUS", REG_MMIO, 0x0A38, &mmMC_IMP_STATUS[0], sizeof(mmMC_IMP_STATUS)/sizeof(mmMC_IMP_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_WCDR_CTRL", REG_MMIO, 0x0A39, &mmMC_SEQ_WCDR_CTRL[0], sizeof(mmMC_SEQ_WCDR_CTRL)/sizeof(mmMC_SEQ_WCDR_CTRL[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_CNTL", REG_MMIO, 0x0A3A, &mmMC_SEQ_TRAIN_WAKEUP_CNTL[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_CNTL)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD", REG_MMIO, 0x0A3B, &mmMC_SEQ_TRAIN_EDC_THRESHOLD[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_EDGE", REG_MMIO, 0x0A3C, &mmMC_SEQ_TRAIN_WAKEUP_EDGE[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_EDGE)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_EDGE[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_MASK", REG_MMIO, 0x0A3D, &mmMC_SEQ_TRAIN_WAKEUP_MASK[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_MASK)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_MASK[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_CAPTURE", REG_MMIO, 0x0A3E, &mmMC_SEQ_TRAIN_CAPTURE[0], sizeof(mmMC_SEQ_TRAIN_CAPTURE)/sizeof(mmMC_SEQ_TRAIN_CAPTURE[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_CLEAR", REG_MMIO, 0x0A3F, &mmMC_SEQ_TRAIN_WAKEUP_CLEAR[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_CLEAR)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_CLEAR[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_TIMING", REG_MMIO, 0x0A40, &mmMC_SEQ_TRAIN_TIMING[0], sizeof(mmMC_SEQ_TRAIN_TIMING)/sizeof(mmMC_SEQ_TRAIN_TIMING[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDCCDR_R_D0", REG_MMIO, 0x0A41, &mmMC_TRAIN_EDCCDR_R_D0[0], sizeof(mmMC_TRAIN_EDCCDR_R_D0)/sizeof(mmMC_TRAIN_EDCCDR_R_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDCCDR_R_D1", REG_MMIO, 0x0A42, &mmMC_TRAIN_EDCCDR_R_D1[0], sizeof(mmMC_TRAIN_EDCCDR_R_D1)/sizeof(mmMC_TRAIN_EDCCDR_R_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_0_D0", REG_MMIO, 0x0A43, &mmMC_TRAIN_PRBSERR_0_D0[0], sizeof(mmMC_TRAIN_PRBSERR_0_D0)/sizeof(mmMC_TRAIN_PRBSERR_0_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_1_D0", REG_MMIO, 0x0A44, &mmMC_TRAIN_PRBSERR_1_D0[0], sizeof(mmMC_TRAIN_PRBSERR_1_D0)/sizeof(mmMC_TRAIN_PRBSERR_1_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDC_STATUS_D0", REG_MMIO, 0x0A45, &mmMC_TRAIN_EDC_STATUS_D0[0], sizeof(mmMC_TRAIN_EDC_STATUS_D0)/sizeof(mmMC_TRAIN_EDC_STATUS_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_0_D1", REG_MMIO, 0x0A46, &mmMC_TRAIN_PRBSERR_0_D1[0], sizeof(mmMC_TRAIN_PRBSERR_0_D1)/sizeof(mmMC_TRAIN_PRBSERR_0_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_1_D1", REG_MMIO, 0x0A47, &mmMC_TRAIN_PRBSERR_1_D1[0], sizeof(mmMC_TRAIN_PRBSERR_1_D1)/sizeof(mmMC_TRAIN_PRBSERR_1_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDC_STATUS_D1", REG_MMIO, 0x0A48, &mmMC_TRAIN_EDC_STATUS_D1[0], sizeof(mmMC_TRAIN_EDC_STATUS_D1)/sizeof(mmMC_TRAIN_EDC_STATUS_D1[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY0_D0", REG_MMIO, 0x0A49, &mmMC_IO_TXCNTL_DPHY0_D0[0], sizeof(mmMC_IO_TXCNTL_DPHY0_D0)/sizeof(mmMC_IO_TXCNTL_DPHY0_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY1_D0", REG_MMIO, 0x0A4A, &mmMC_IO_TXCNTL_DPHY1_D0[0], sizeof(mmMC_IO_TXCNTL_DPHY1_D0)/sizeof(mmMC_IO_TXCNTL_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_APHY_D0", REG_MMIO, 0x0A4B, &mmMC_IO_TXCNTL_APHY_D0[0], sizeof(mmMC_IO_TXCNTL_APHY_D0)/sizeof(mmMC_IO_TXCNTL_APHY_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY0_D0", REG_MMIO, 0x0A4C, &mmMC_IO_RXCNTL_DPHY0_D0[0], sizeof(mmMC_IO_RXCNTL_DPHY0_D0)/sizeof(mmMC_IO_RXCNTL_DPHY0_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY1_D0", REG_MMIO, 0x0A4D, &mmMC_IO_RXCNTL_DPHY1_D0[0], sizeof(mmMC_IO_RXCNTL_DPHY1_D0)/sizeof(mmMC_IO_RXCNTL_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_DPHY_STR_CNTL_D0", REG_MMIO, 0x0A4E, &mmMC_IO_DPHY_STR_CNTL_D0[0], sizeof(mmMC_IO_DPHY_STR_CNTL_D0)/sizeof(mmMC_IO_DPHY_STR_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY0_D1", REG_MMIO, 0x0A4F, &mmMC_IO_TXCNTL_DPHY0_D1[0], sizeof(mmMC_IO_TXCNTL_DPHY0_D1)/sizeof(mmMC_IO_TXCNTL_DPHY0_D1[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY1_D1", REG_MMIO, 0x0A50, &mmMC_IO_TXCNTL_DPHY1_D1[0], sizeof(mmMC_IO_TXCNTL_DPHY1_D1)/sizeof(mmMC_IO_TXCNTL_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_APHY_D1", REG_MMIO, 0x0A51, &mmMC_IO_TXCNTL_APHY_D1[0], sizeof(mmMC_IO_TXCNTL_APHY_D1)/sizeof(mmMC_IO_TXCNTL_APHY_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY0_D1", REG_MMIO, 0x0A52, &mmMC_IO_RXCNTL_DPHY0_D1[0], sizeof(mmMC_IO_RXCNTL_DPHY0_D1)/sizeof(mmMC_IO_RXCNTL_DPHY0_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY1_D1", REG_MMIO, 0x0A53, &mmMC_IO_RXCNTL_DPHY1_D1[0], sizeof(mmMC_IO_RXCNTL_DPHY1_D1)/sizeof(mmMC_IO_RXCNTL_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_IO_DPHY_STR_CNTL_D1", REG_MMIO, 0x0A54, &mmMC_IO_DPHY_STR_CNTL_D1[0], sizeof(mmMC_IO_DPHY_STR_CNTL_D1)/sizeof(mmMC_IO_DPHY_STR_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL_D0", REG_MMIO, 0x0A55, &mmMC_IO_CDRCNTL_D0[0], sizeof(mmMC_IO_CDRCNTL_D0)/sizeof(mmMC_IO_CDRCNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL_D1", REG_MMIO, 0x0A56, &mmMC_IO_CDRCNTL_D1[0], sizeof(mmMC_IO_CDRCNTL_D1)/sizeof(mmMC_IO_CDRCNTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_FIFO_CTL", REG_MMIO, 0x0A57, &mmMC_SEQ_FIFO_CTL[0], sizeof(mmMC_SEQ_FIFO_CTL)/sizeof(mmMC_SEQ_FIFO_CTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE0_D0", REG_MMIO, 0x0A58, &mmMC_SEQ_TXFRAMING_BYTE0_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE1_D0", REG_MMIO, 0x0A59, &mmMC_SEQ_TXFRAMING_BYTE1_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE2_D0", REG_MMIO, 0x0A5A, &mmMC_SEQ_TXFRAMING_BYTE2_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE3_D0", REG_MMIO, 0x0A5B, &mmMC_SEQ_TXFRAMING_BYTE3_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_DBI_D0", REG_MMIO, 0x0A5C, &mmMC_SEQ_TXFRAMING_DBI_D0[0], sizeof(mmMC_SEQ_TXFRAMING_DBI_D0)/sizeof(mmMC_SEQ_TXFRAMING_DBI_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_EDC_D0", REG_MMIO, 0x0A5D, &mmMC_SEQ_TXFRAMING_EDC_D0[0], sizeof(mmMC_SEQ_TXFRAMING_EDC_D0)/sizeof(mmMC_SEQ_TXFRAMING_EDC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_FCK_D0", REG_MMIO, 0x0A5E, &mmMC_SEQ_TXFRAMING_FCK_D0[0], sizeof(mmMC_SEQ_TXFRAMING_FCK_D0)/sizeof(mmMC_SEQ_TXFRAMING_FCK_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC8", REG_MMIO, 0x0A5F, &mmMC_SEQ_MISC8[0], sizeof(mmMC_SEQ_MISC8)/sizeof(mmMC_SEQ_MISC8[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE0_D1", REG_MMIO, 0x0A60, &mmMC_SEQ_TXFRAMING_BYTE0_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE1_D1", REG_MMIO, 0x0A61, &mmMC_SEQ_TXFRAMING_BYTE1_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE2_D1", REG_MMIO, 0x0A62, &mmMC_SEQ_TXFRAMING_BYTE2_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE3_D1", REG_MMIO, 0x0A63, &mmMC_SEQ_TXFRAMING_BYTE3_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_DBI_D1", REG_MMIO, 0x0A64, &mmMC_SEQ_TXFRAMING_DBI_D1[0], sizeof(mmMC_SEQ_TXFRAMING_DBI_D1)/sizeof(mmMC_SEQ_TXFRAMING_DBI_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_EDC_D1", REG_MMIO, 0x0A65, &mmMC_SEQ_TXFRAMING_EDC_D1[0], sizeof(mmMC_SEQ_TXFRAMING_EDC_D1)/sizeof(mmMC_SEQ_TXFRAMING_EDC_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_FCK_D1", REG_MMIO, 0x0A66, &mmMC_SEQ_TXFRAMING_FCK_D1[0], sizeof(mmMC_SEQ_TXFRAMING_FCK_D1)/sizeof(mmMC_SEQ_TXFRAMING_FCK_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE0_D0", REG_MMIO, 0x0A67, &mmMC_SEQ_RXFRAMING_BYTE0_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE1_D0", REG_MMIO, 0x0A68, &mmMC_SEQ_RXFRAMING_BYTE1_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE2_D0", REG_MMIO, 0x0A69, &mmMC_SEQ_RXFRAMING_BYTE2_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE3_D0", REG_MMIO, 0x0A6A, &mmMC_SEQ_RXFRAMING_BYTE3_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_DBI_D0", REG_MMIO, 0x0A6B, &mmMC_SEQ_RXFRAMING_DBI_D0[0], sizeof(mmMC_SEQ_RXFRAMING_DBI_D0)/sizeof(mmMC_SEQ_RXFRAMING_DBI_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_EDC_D0", REG_MMIO, 0x0A6C, &mmMC_SEQ_RXFRAMING_EDC_D0[0], sizeof(mmMC_SEQ_RXFRAMING_EDC_D0)/sizeof(mmMC_SEQ_RXFRAMING_EDC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE0_D1", REG_MMIO, 0x0A6D, &mmMC_SEQ_RXFRAMING_BYTE0_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE1_D1", REG_MMIO, 0x0A6E, &mmMC_SEQ_RXFRAMING_BYTE1_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE2_D1", REG_MMIO, 0x0A6F, &mmMC_SEQ_RXFRAMING_BYTE2_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE3_D1", REG_MMIO, 0x0A70, &mmMC_SEQ_RXFRAMING_BYTE3_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_DBI_D1", REG_MMIO, 0x0A71, &mmMC_SEQ_RXFRAMING_DBI_D1[0], sizeof(mmMC_SEQ_RXFRAMING_DBI_D1)/sizeof(mmMC_SEQ_RXFRAMING_DBI_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_EDC_D1", REG_MMIO, 0x0A72, &mmMC_SEQ_RXFRAMING_EDC_D1[0], sizeof(mmMC_SEQ_RXFRAMING_EDC_D1)/sizeof(mmMC_SEQ_RXFRAMING_EDC_D1[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL", REG_MMIO, 0x0A73, &mmMC_IO_PAD_CNTL[0], sizeof(mmMC_IO_PAD_CNTL)/sizeof(mmMC_IO_PAD_CNTL[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL_D0", REG_MMIO, 0x0A74, &mmMC_IO_PAD_CNTL_D0[0], sizeof(mmMC_IO_PAD_CNTL_D0)/sizeof(mmMC_IO_PAD_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL_D1", REG_MMIO, 0x0A75, &mmMC_IO_PAD_CNTL_D1[0], sizeof(mmMC_IO_PAD_CNTL_D1)/sizeof(mmMC_IO_PAD_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_NPL_STATUS", REG_MMIO, 0x0A76, &mmMC_NPL_STATUS[0], sizeof(mmMC_NPL_STATUS)/sizeof(mmMC_NPL_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_CNTL", REG_MMIO, 0x0A77, &mmMC_SEQ_PERF_CNTL[0], sizeof(mmMC_SEQ_PERF_CNTL)/sizeof(mmMC_SEQ_PERF_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CTL", REG_MMIO, 0x0A78, &mmMC_SEQ_PERF_SEQ_CTL[0], sizeof(mmMC_SEQ_PERF_SEQ_CTL)/sizeof(mmMC_SEQ_PERF_SEQ_CTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_A_I0", REG_MMIO, 0x0A79, &mmMC_SEQ_PERF_SEQ_CNT_A_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_A_I1", REG_MMIO, 0x0A7A, &mmMC_SEQ_PERF_SEQ_CNT_A_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_B_I0", REG_MMIO, 0x0A7B, &mmMC_SEQ_PERF_SEQ_CNT_B_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_B_I1", REG_MMIO, 0x0A7C, &mmMC_SEQ_PERF_SEQ_CNT_B_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_STATUS_M", REG_MMIO, 0x0A7D, &mmMC_SEQ_STATUS_M[0], sizeof(mmMC_SEQ_STATUS_M)/sizeof(mmMC_SEQ_STATUS_M[0]), 0, 0 },
+	{ "mmMC_SEQ_VENDOR_ID_I0", REG_MMIO, 0x0A7E, &mmMC_SEQ_VENDOR_ID_I0[0], sizeof(mmMC_SEQ_VENDOR_ID_I0)/sizeof(mmMC_SEQ_VENDOR_ID_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_VENDOR_ID_I1", REG_MMIO, 0x0A7F, &mmMC_SEQ_VENDOR_ID_I1[0], sizeof(mmMC_SEQ_VENDOR_ID_I1)/sizeof(mmMC_SEQ_VENDOR_ID_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC0", REG_MMIO, 0x0A80, &mmMC_SEQ_MISC0[0], sizeof(mmMC_SEQ_MISC0)/sizeof(mmMC_SEQ_MISC0[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC1", REG_MMIO, 0x0A81, &mmMC_SEQ_MISC1[0], sizeof(mmMC_SEQ_MISC1)/sizeof(mmMC_SEQ_MISC1[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_M", REG_MMIO, 0x0A82, &mmMC_SEQ_RESERVE_M[0], sizeof(mmMC_SEQ_RESERVE_M)/sizeof(mmMC_SEQ_RESERVE_M[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_EMRS", REG_MMIO, 0x0A83, &mmMC_PMG_CMD_EMRS[0], sizeof(mmMC_PMG_CMD_EMRS)/sizeof(mmMC_PMG_CMD_EMRS[0]), 0, 0 },
+	{ "mmMC_PMG_CFG", REG_MMIO, 0x0A84, &mmMC_PMG_CFG[0], sizeof(mmMC_PMG_CFG)/sizeof(mmMC_PMG_CFG[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP2_STAT", REG_MMIO, 0x0A85, &mmMC_SEQ_SUP_GP2_STAT[0], sizeof(mmMC_SEQ_SUP_GP2_STAT)/sizeof(mmMC_SEQ_SUP_GP2_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP3_STAT", REG_MMIO, 0x0A86, &mmMC_SEQ_SUP_GP3_STAT[0], sizeof(mmMC_SEQ_SUP_GP3_STAT)/sizeof(mmMC_SEQ_SUP_GP3_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_IR_STAT", REG_MMIO, 0x0A87, &mmMC_SEQ_SUP_IR_STAT[0], sizeof(mmMC_SEQ_SUP_IR_STAT)/sizeof(mmMC_SEQ_SUP_IR_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_DEC_STAT", REG_MMIO, 0x0A88, &mmMC_SEQ_SUP_DEC_STAT[0], sizeof(mmMC_SEQ_SUP_DEC_STAT)/sizeof(mmMC_SEQ_SUP_DEC_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_PGM_STAT", REG_MMIO, 0x0A89, &mmMC_SEQ_SUP_PGM_STAT[0], sizeof(mmMC_SEQ_SUP_PGM_STAT)/sizeof(mmMC_SEQ_SUP_PGM_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_R_PGM", REG_MMIO, 0x0A8A, &mmMC_SEQ_SUP_R_PGM[0], sizeof(mmMC_SEQ_SUP_R_PGM)/sizeof(mmMC_SEQ_SUP_R_PGM[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC3", REG_MMIO, 0x0A8B, &mmMC_SEQ_MISC3[0], sizeof(mmMC_SEQ_MISC3)/sizeof(mmMC_SEQ_MISC3[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC4", REG_MMIO, 0x0A8C, &mmMC_SEQ_MISC4[0], sizeof(mmMC_SEQ_MISC4)/sizeof(mmMC_SEQ_MISC4[0]), 0, 0 },
+	{ "mmMC_BIST_CMP_CNTL", REG_MMIO, 0x0A8D, &mmMC_BIST_CMP_CNTL[0], sizeof(mmMC_BIST_CMP_CNTL)/sizeof(mmMC_BIST_CMP_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_CMD_CNTL", REG_MMIO, 0x0A8E, &mmMC_BIST_CMD_CNTL[0], sizeof(mmMC_BIST_CMD_CNTL)/sizeof(mmMC_BIST_CMD_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP0_STAT", REG_MMIO, 0x0A8F, &mmMC_SEQ_SUP_GP0_STAT[0], sizeof(mmMC_SEQ_SUP_GP0_STAT)/sizeof(mmMC_SEQ_SUP_GP0_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP1_STAT", REG_MMIO, 0x0A90, &mmMC_SEQ_SUP_GP1_STAT[0], sizeof(mmMC_SEQ_SUP_GP1_STAT)/sizeof(mmMC_SEQ_SUP_GP1_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_DEBUG_INDEX", REG_MMIO, 0x0A91, &mmMC_SEQ_IO_DEBUG_INDEX[0], sizeof(mmMC_SEQ_IO_DEBUG_INDEX)/sizeof(mmMC_SEQ_IO_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_DEBUG_DATA", REG_MMIO, 0x0A92, &mmMC_SEQ_IO_DEBUG_DATA[0], sizeof(mmMC_SEQ_IO_DEBUG_DATA)/sizeof(mmMC_SEQ_IO_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMC_SEQ_BYTE_REMAP_D0", REG_MMIO, 0x0A93, &mmMC_SEQ_BYTE_REMAP_D0[0], sizeof(mmMC_SEQ_BYTE_REMAP_D0)/sizeof(mmMC_SEQ_BYTE_REMAP_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BYTE_REMAP_D1", REG_MMIO, 0x0A94, &mmMC_SEQ_BYTE_REMAP_D1[0], sizeof(mmMC_SEQ_BYTE_REMAP_D1)/sizeof(mmMC_SEQ_BYTE_REMAP_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC5", REG_MMIO, 0x0A95, &mmMC_SEQ_MISC5[0], sizeof(mmMC_SEQ_MISC5)/sizeof(mmMC_SEQ_MISC5[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC6", REG_MMIO, 0x0A96, &mmMC_SEQ_MISC6[0], sizeof(mmMC_SEQ_MISC6)/sizeof(mmMC_SEQ_MISC6[0]), 0, 0 },
+	{ "mmMC_IO_APHY_STR_CNTL_D0", REG_MMIO, 0x0A97, &mmMC_IO_APHY_STR_CNTL_D0[0], sizeof(mmMC_IO_APHY_STR_CNTL_D0)/sizeof(mmMC_IO_APHY_STR_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_APHY_STR_CNTL_D1", REG_MMIO, 0x0A98, &mmMC_IO_APHY_STR_CNTL_D1[0], sizeof(mmMC_IO_APHY_STR_CNTL_D1)/sizeof(mmMC_IO_APHY_STR_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC7", REG_MMIO, 0x0A99, &mmMC_SEQ_MISC7[0], sizeof(mmMC_SEQ_MISC7)/sizeof(mmMC_SEQ_MISC7[0]), 0, 0 },
+	{ "mmMC_SEQ_CG", REG_MMIO, 0x0A9A, &mmMC_SEQ_CG[0], sizeof(mmMC_SEQ_CG)/sizeof(mmMC_SEQ_CG[0]), 0, 0 },
+	{ "mmMC_SEQ_RAS_TIMING_LP", REG_MMIO, 0x0A9B, &mmMC_SEQ_RAS_TIMING_LP[0], sizeof(mmMC_SEQ_RAS_TIMING_LP)/sizeof(mmMC_SEQ_RAS_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_CAS_TIMING_LP", REG_MMIO, 0x0A9C, &mmMC_SEQ_CAS_TIMING_LP[0], sizeof(mmMC_SEQ_CAS_TIMING_LP)/sizeof(mmMC_SEQ_CAS_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING_LP", REG_MMIO, 0x0A9D, &mmMC_SEQ_MISC_TIMING_LP[0], sizeof(mmMC_SEQ_MISC_TIMING_LP)/sizeof(mmMC_SEQ_MISC_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING2_LP", REG_MMIO, 0x0A9E, &mmMC_SEQ_MISC_TIMING2_LP[0], sizeof(mmMC_SEQ_MISC_TIMING2_LP)/sizeof(mmMC_SEQ_MISC_TIMING2_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D0_LP", REG_MMIO, 0x0A9F, &mmMC_SEQ_WR_CTL_D0_LP[0], sizeof(mmMC_SEQ_WR_CTL_D0_LP)/sizeof(mmMC_SEQ_WR_CTL_D0_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D1_LP", REG_MMIO, 0x0AA0, &mmMC_SEQ_WR_CTL_D1_LP[0], sizeof(mmMC_SEQ_WR_CTL_D1_LP)/sizeof(mmMC_SEQ_WR_CTL_D1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_EMRS_LP", REG_MMIO, 0x0AA1, &mmMC_SEQ_PMG_CMD_EMRS_LP[0], sizeof(mmMC_SEQ_PMG_CMD_EMRS_LP)/sizeof(mmMC_SEQ_PMG_CMD_EMRS_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS_LP", REG_MMIO, 0x0AA2, &mmMC_SEQ_PMG_CMD_MRS_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B0_D0", REG_MMIO, 0x0AA3, &mmMC_SEQ_BIT_REMAP_B0_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B0_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B1_D0", REG_MMIO, 0x0AA4, &mmMC_SEQ_BIT_REMAP_B1_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B1_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B2_D0", REG_MMIO, 0x0AA5, &mmMC_SEQ_BIT_REMAP_B2_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B2_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B3_D0", REG_MMIO, 0x0AA6, &mmMC_SEQ_BIT_REMAP_B3_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B3_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B0_D1", REG_MMIO, 0x0AA7, &mmMC_SEQ_BIT_REMAP_B0_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B0_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B1_D1", REG_MMIO, 0x0AA8, &mmMC_SEQ_BIT_REMAP_B1_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B1_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B2_D1", REG_MMIO, 0x0AA9, &mmMC_SEQ_BIT_REMAP_B2_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B2_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B3_D1", REG_MMIO, 0x0AAA, &mmMC_SEQ_BIT_REMAP_B3_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B3_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B3_D1[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS", REG_MMIO, 0x0AAB, &mmMC_PMG_CMD_MRS[0], sizeof(mmMC_PMG_CMD_MRS)/sizeof(mmMC_PMG_CMD_MRS[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD0", REG_MMIO, 0x0AAC, &mmMC_SEQ_IO_RWORD0[0], sizeof(mmMC_SEQ_IO_RWORD0)/sizeof(mmMC_SEQ_IO_RWORD0[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD1", REG_MMIO, 0x0AAD, &mmMC_SEQ_IO_RWORD1[0], sizeof(mmMC_SEQ_IO_RWORD1)/sizeof(mmMC_SEQ_IO_RWORD1[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD2", REG_MMIO, 0x0AAE, &mmMC_SEQ_IO_RWORD2[0], sizeof(mmMC_SEQ_IO_RWORD2)/sizeof(mmMC_SEQ_IO_RWORD2[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD3", REG_MMIO, 0x0AAF, &mmMC_SEQ_IO_RWORD3[0], sizeof(mmMC_SEQ_IO_RWORD3)/sizeof(mmMC_SEQ_IO_RWORD3[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD4", REG_MMIO, 0x0AB0, &mmMC_SEQ_IO_RWORD4[0], sizeof(mmMC_SEQ_IO_RWORD4)/sizeof(mmMC_SEQ_IO_RWORD4[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD5", REG_MMIO, 0x0AB1, &mmMC_SEQ_IO_RWORD5[0], sizeof(mmMC_SEQ_IO_RWORD5)/sizeof(mmMC_SEQ_IO_RWORD5[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD6", REG_MMIO, 0x0AB2, &mmMC_SEQ_IO_RWORD6[0], sizeof(mmMC_SEQ_IO_RWORD6)/sizeof(mmMC_SEQ_IO_RWORD6[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD7", REG_MMIO, 0x0AB3, &mmMC_SEQ_IO_RWORD7[0], sizeof(mmMC_SEQ_IO_RWORD7)/sizeof(mmMC_SEQ_IO_RWORD7[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RDBI", REG_MMIO, 0x0AB4, &mmMC_SEQ_IO_RDBI[0], sizeof(mmMC_SEQ_IO_RDBI)/sizeof(mmMC_SEQ_IO_RDBI[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_REDC", REG_MMIO, 0x0AB5, &mmMC_SEQ_IO_REDC[0], sizeof(mmMC_SEQ_IO_REDC)/sizeof(mmMC_SEQ_IO_REDC[0]), 0, 0 },
+	{ "mmMC_BIST_CMP_CNTL_2", REG_MMIO, 0x0AB6, &mmMC_BIST_CMP_CNTL_2[0], sizeof(mmMC_BIST_CMP_CNTL_2)/sizeof(mmMC_BIST_CMP_CNTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RESERVE_D0", REG_MMIO, 0x0AB7, &mmMC_SEQ_IO_RESERVE_D0[0], sizeof(mmMC_SEQ_IO_RESERVE_D0)/sizeof(mmMC_SEQ_IO_RESERVE_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RESERVE_D1", REG_MMIO, 0x0AB8, &mmMC_SEQ_IO_RESERVE_D1[0], sizeof(mmMC_SEQ_IO_RESERVE_D1)/sizeof(mmMC_SEQ_IO_RESERVE_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_HWCNTL", REG_MMIO, 0x0AB9, &mmMC_SEQ_PMG_PG_HWCNTL[0], sizeof(mmMC_SEQ_PMG_PG_HWCNTL)/sizeof(mmMC_SEQ_PMG_PG_HWCNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_SWCNTL_0", REG_MMIO, 0x0ABA, &mmMC_SEQ_PMG_PG_SWCNTL_0[0], sizeof(mmMC_SEQ_PMG_PG_SWCNTL_0)/sizeof(mmMC_SEQ_PMG_PG_SWCNTL_0[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_SWCNTL_1", REG_MMIO, 0x0ABB, &mmMC_SEQ_PMG_PG_SWCNTL_1[0], sizeof(mmMC_SEQ_PMG_PG_SWCNTL_1)/sizeof(mmMC_SEQ_PMG_PG_SWCNTL_1[0]), 0, 0 },
+	{ "mmMC_IMP_DQ_STATUS", REG_MMIO, 0x0ABC, &mmMC_IMP_DQ_STATUS[0], sizeof(mmMC_IMP_DQ_STATUS)/sizeof(mmMC_IMP_DQ_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_TCG_CNTL", REG_MMIO, 0x0ABD, &mmMC_SEQ_TCG_CNTL[0], sizeof(mmMC_SEQ_TCG_CNTL)/sizeof(mmMC_SEQ_TCG_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_CTRL", REG_MMIO, 0x0ABE, &mmMC_SEQ_TSM_CTRL[0], sizeof(mmMC_SEQ_TSM_CTRL)/sizeof(mmMC_SEQ_TSM_CTRL[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_GCNT", REG_MMIO, 0x0ABF, &mmMC_SEQ_TSM_GCNT[0], sizeof(mmMC_SEQ_TSM_GCNT)/sizeof(mmMC_SEQ_TSM_GCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_OCNT", REG_MMIO, 0x0AC0, &mmMC_SEQ_TSM_OCNT[0], sizeof(mmMC_SEQ_TSM_OCNT)/sizeof(mmMC_SEQ_TSM_OCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_NCNT", REG_MMIO, 0x0AC1, &mmMC_SEQ_TSM_NCNT[0], sizeof(mmMC_SEQ_TSM_NCNT)/sizeof(mmMC_SEQ_TSM_NCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_BCNT", REG_MMIO, 0x0AC2, &mmMC_SEQ_TSM_BCNT[0], sizeof(mmMC_SEQ_TSM_BCNT)/sizeof(mmMC_SEQ_TSM_BCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_FLAG", REG_MMIO, 0x0AC3, &mmMC_SEQ_TSM_FLAG[0], sizeof(mmMC_SEQ_TSM_FLAG)/sizeof(mmMC_SEQ_TSM_FLAG[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_UPDATE", REG_MMIO, 0x0AC4, &mmMC_SEQ_TSM_UPDATE[0], sizeof(mmMC_SEQ_TSM_UPDATE)/sizeof(mmMC_SEQ_TSM_UPDATE[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_EDC", REG_MMIO, 0x0AC5, &mmMC_SEQ_TSM_EDC[0], sizeof(mmMC_SEQ_TSM_EDC)/sizeof(mmMC_SEQ_TSM_EDC[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DBI", REG_MMIO, 0x0AC6, &mmMC_SEQ_TSM_DBI[0], sizeof(mmMC_SEQ_TSM_DBI)/sizeof(mmMC_SEQ_TSM_DBI[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D0_LP", REG_MMIO, 0x0AC7, &mmMC_SEQ_RD_CTL_D0_LP[0], sizeof(mmMC_SEQ_RD_CTL_D0_LP)/sizeof(mmMC_SEQ_RD_CTL_D0_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D1_LP", REG_MMIO, 0x0AC8, &mmMC_SEQ_RD_CTL_D1_LP[0], sizeof(mmMC_SEQ_RD_CTL_D1_LP)/sizeof(mmMC_SEQ_RD_CTL_D1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_TIMER_WR", REG_MMIO, 0x0AC9, &mmMC_SEQ_TIMER_WR[0], sizeof(mmMC_SEQ_TIMER_WR)/sizeof(mmMC_SEQ_TIMER_WR[0]), 0, 0 },
+	{ "mmMC_SEQ_TIMER_RD", REG_MMIO, 0x0ACA, &mmMC_SEQ_TIMER_RD[0], sizeof(mmMC_SEQ_TIMER_RD)/sizeof(mmMC_SEQ_TIMER_RD[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM_ERROR_INSERTION", REG_MMIO, 0x0ACB, &mmMC_SEQ_DRAM_ERROR_INSERTION[0], sizeof(mmMC_SEQ_DRAM_ERROR_INSERTION)/sizeof(mmMC_SEQ_DRAM_ERROR_INSERTION[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_D0", REG_MMIO, 0x0ACC, &mmMC_PHY_TIMING_D0[0], sizeof(mmMC_PHY_TIMING_D0)/sizeof(mmMC_PHY_TIMING_D0[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_D1", REG_MMIO, 0x0ACD, &mmMC_PHY_TIMING_D1[0], sizeof(mmMC_PHY_TIMING_D1)/sizeof(mmMC_PHY_TIMING_D1[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_2", REG_MMIO, 0x0ACE, &mmMC_PHY_TIMING_2[0], sizeof(mmMC_PHY_TIMING_2)/sizeof(mmMC_PHY_TIMING_2[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DEBUG_INDEX", REG_MMIO, 0x0ACF, &mmMC_SEQ_TSM_DEBUG_INDEX[0], sizeof(mmMC_SEQ_TSM_DEBUG_INDEX)/sizeof(mmMC_SEQ_TSM_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DEBUG_DATA", REG_MMIO, 0x0AD0, &mmMC_SEQ_TSM_DEBUG_DATA[0], sizeof(mmMC_SEQ_TSM_DEBUG_DATA)/sizeof(mmMC_SEQ_TSM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS1", REG_MMIO, 0x0AD1, &mmMC_PMG_CMD_MRS1[0], sizeof(mmMC_PMG_CMD_MRS1)/sizeof(mmMC_PMG_CMD_MRS1[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS1_LP", REG_MMIO, 0x0AD2, &mmMC_SEQ_PMG_CMD_MRS1_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS1_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_TIMING_LP", REG_MMIO, 0x0AD3, &mmMC_SEQ_PMG_TIMING_LP[0], sizeof(mmMC_SEQ_PMG_TIMING_LP)/sizeof(mmMC_SEQ_PMG_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_CNTL_2", REG_MMIO, 0x0AD4, &mmMC_SEQ_CNTL_2[0], sizeof(mmMC_SEQ_CNTL_2)/sizeof(mmMC_SEQ_CNTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_2", REG_MMIO, 0x0AD5, &mmMC_SEQ_WR_CTL_2[0], sizeof(mmMC_SEQ_WR_CTL_2)/sizeof(mmMC_SEQ_WR_CTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_2_LP", REG_MMIO, 0x0AD6, &mmMC_SEQ_WR_CTL_2_LP[0], sizeof(mmMC_SEQ_WR_CTL_2_LP)/sizeof(mmMC_SEQ_WR_CTL_2_LP[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS2", REG_MMIO, 0x0AD7, &mmMC_PMG_CMD_MRS2[0], sizeof(mmMC_PMG_CMD_MRS2)/sizeof(mmMC_PMG_CMD_MRS2[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS2_LP", REG_MMIO, 0x0AD8, &mmMC_SEQ_PMG_CMD_MRS2_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS2_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS2_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_C_I0", REG_MMIO, 0x0AD9, &mmMC_SEQ_PERF_SEQ_CNT_C_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_C_I1", REG_MMIO, 0x0ADA, &mmMC_SEQ_PERF_SEQ_CNT_C_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_D_I0", REG_MMIO, 0x0ADB, &mmMC_SEQ_PERF_SEQ_CNT_D_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_D_I1", REG_MMIO, 0x0ADC, &mmMC_SEQ_PERF_SEQ_CNT_D_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I1[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL1_D0", REG_MMIO, 0x0ADD, &mmMC_IO_CDRCNTL1_D0[0], sizeof(mmMC_IO_CDRCNTL1_D0)/sizeof(mmMC_IO_CDRCNTL1_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL1_D1", REG_MMIO, 0x0ADE, &mmMC_IO_CDRCNTL1_D1[0], sizeof(mmMC_IO_CDRCNTL1_D1)/sizeof(mmMC_IO_CDRCNTL1_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY0_D0", REG_MMIO, 0x0ADF, &mmMC_IO_RXCNTL1_DPHY0_D0[0], sizeof(mmMC_IO_RXCNTL1_DPHY0_D0)/sizeof(mmMC_IO_RXCNTL1_DPHY0_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY1_D0", REG_MMIO, 0x0AE0, &mmMC_IO_RXCNTL1_DPHY1_D0[0], sizeof(mmMC_IO_RXCNTL1_DPHY1_D0)/sizeof(mmMC_IO_RXCNTL1_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY0_D1", REG_MMIO, 0x0AE1, &mmMC_IO_RXCNTL1_DPHY0_D1[0], sizeof(mmMC_IO_RXCNTL1_DPHY0_D1)/sizeof(mmMC_IO_RXCNTL1_DPHY0_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY1_D1", REG_MMIO, 0x0AE2, &mmMC_IO_RXCNTL1_DPHY1_D1[0], sizeof(mmMC_IO_RXCNTL1_DPHY1_D1)/sizeof(mmMC_IO_RXCNTL1_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_WCDR", REG_MMIO, 0x0AE3, &mmMC_SEQ_TSM_WCDR[0], sizeof(mmMC_SEQ_TSM_WCDR)/sizeof(mmMC_SEQ_TSM_WCDR[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL2_D0", REG_MMIO, 0x0AE4, &mmMC_IO_CDRCNTL2_D0[0], sizeof(mmMC_IO_CDRCNTL2_D0)/sizeof(mmMC_IO_CDRCNTL2_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL2_D1", REG_MMIO, 0x0AE5, &mmMC_IO_CDRCNTL2_D1[0], sizeof(mmMC_IO_CDRCNTL2_D1)/sizeof(mmMC_IO_CDRCNTL2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_MISC", REG_MMIO, 0x0AE6, &mmMC_SEQ_TSM_MISC[0], sizeof(mmMC_SEQ_TSM_MISC)/sizeof(mmMC_SEQ_TSM_MISC[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC9", REG_MMIO, 0x0AE7, &mmMC_SEQ_MISC9[0], sizeof(mmMC_SEQ_MISC9)/sizeof(mmMC_SEQ_MISC9[0]), 0, 0 },
+	{ "mmMCLK_PWRMGT_CNTL", REG_MMIO, 0x0AE8, &mmMCLK_PWRMGT_CNTL[0], sizeof(mmMCLK_PWRMGT_CNTL)/sizeof(mmMCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "mmDLL_CNTL", REG_MMIO, 0x0AE9, &mmDLL_CNTL[0], sizeof(mmDLL_CNTL)/sizeof(mmDLL_CNTL[0]), 0, 0 },
+	{ "mmMPLL_SEQ_UCODE_1", REG_MMIO, 0x0AEA, &mmMPLL_SEQ_UCODE_1[0], sizeof(mmMPLL_SEQ_UCODE_1)/sizeof(mmMPLL_SEQ_UCODE_1[0]), 0, 0 },
+	{ "mmMPLL_SEQ_UCODE_2", REG_MMIO, 0x0AEB, &mmMPLL_SEQ_UCODE_2[0], sizeof(mmMPLL_SEQ_UCODE_2)/sizeof(mmMPLL_SEQ_UCODE_2[0]), 0, 0 },
+	{ "mmMPLL_CNTL_MODE", REG_MMIO, 0x0AEC, &mmMPLL_CNTL_MODE[0], sizeof(mmMPLL_CNTL_MODE)/sizeof(mmMPLL_CNTL_MODE[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL", REG_MMIO, 0x0AED, &mmMPLL_FUNC_CNTL[0], sizeof(mmMPLL_FUNC_CNTL)/sizeof(mmMPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL_1", REG_MMIO, 0x0AEE, &mmMPLL_FUNC_CNTL_1[0], sizeof(mmMPLL_FUNC_CNTL_1)/sizeof(mmMPLL_FUNC_CNTL_1[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL_2", REG_MMIO, 0x0AEF, &mmMPLL_FUNC_CNTL_2[0], sizeof(mmMPLL_FUNC_CNTL_2)/sizeof(mmMPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "mmMPLL_AD_FUNC_CNTL", REG_MMIO, 0x0AF0, &mmMPLL_AD_FUNC_CNTL[0], sizeof(mmMPLL_AD_FUNC_CNTL)/sizeof(mmMPLL_AD_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_DQ_FUNC_CNTL", REG_MMIO, 0x0AF1, &mmMPLL_DQ_FUNC_CNTL[0], sizeof(mmMPLL_DQ_FUNC_CNTL)/sizeof(mmMPLL_DQ_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_TIME", REG_MMIO, 0x0AF2, &mmMPLL_TIME[0], sizeof(mmMPLL_TIME)/sizeof(mmMPLL_TIME[0]), 0, 0 },
+	{ "mmMPLL_SS1", REG_MMIO, 0x0AF3, &mmMPLL_SS1[0], sizeof(mmMPLL_SS1)/sizeof(mmMPLL_SS1[0]), 0, 0 },
+	{ "mmMPLL_SS2", REG_MMIO, 0x0AF4, &mmMPLL_SS2[0], sizeof(mmMPLL_SS2)/sizeof(mmMPLL_SS2[0]), 0, 0 },
+	{ "mmMPLL_CONTROL", REG_MMIO, 0x0AF5, &mmMPLL_CONTROL[0], sizeof(mmMPLL_CONTROL)/sizeof(mmMPLL_CONTROL[0]), 0, 0 },
+	{ "mmMPLL_AD_STATUS", REG_MMIO, 0x0AF6, &mmMPLL_AD_STATUS[0], sizeof(mmMPLL_AD_STATUS)/sizeof(mmMPLL_AD_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_0_0_STATUS", REG_MMIO, 0x0AF7, &mmMPLL_DQ_0_0_STATUS[0], sizeof(mmMPLL_DQ_0_0_STATUS)/sizeof(mmMPLL_DQ_0_0_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_0_1_STATUS", REG_MMIO, 0x0AF8, &mmMPLL_DQ_0_1_STATUS[0], sizeof(mmMPLL_DQ_0_1_STATUS)/sizeof(mmMPLL_DQ_0_1_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_1_0_STATUS", REG_MMIO, 0x0AF9, &mmMPLL_DQ_1_0_STATUS[0], sizeof(mmMPLL_DQ_1_0_STATUS)/sizeof(mmMPLL_DQ_1_0_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_1_1_STATUS", REG_MMIO, 0x0AFA, &mmMPLL_DQ_1_1_STATUS[0], sizeof(mmMPLL_DQ_1_1_STATUS)/sizeof(mmMPLL_DQ_1_1_STATUS[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_2_D0", REG_MMIO, 0x0AFB, &mmMC_TRAIN_PRBSERR_2_D0[0], sizeof(mmMC_TRAIN_PRBSERR_2_D0)/sizeof(mmMC_TRAIN_PRBSERR_2_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_2_D1", REG_MMIO, 0x0AFC, &mmMC_TRAIN_PRBSERR_2_D1[0], sizeof(mmMC_TRAIN_PRBSERR_2_D1)/sizeof(mmMC_TRAIN_PRBSERR_2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_CNTL_1", REG_MMIO, 0x0AFD, &mmMC_SEQ_PERF_CNTL_1[0], sizeof(mmMC_SEQ_PERF_CNTL_1)/sizeof(mmMC_SEQ_PERF_CNTL_1[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD2", REG_MMIO, 0x0AFE, &mmMC_SEQ_TRAIN_EDC_THRESHOLD2[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD2)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD2[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD3", REG_MMIO, 0x0AFF, &mmMC_SEQ_TRAIN_EDC_THRESHOLD3[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD3)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD3[0]), 0, 0 },
+	{ "mmMC_XBAR_ADDR_DEC", REG_MMIO, 0x0C80, &mmMC_XBAR_ADDR_DEC[0], sizeof(mmMC_XBAR_ADDR_DEC)/sizeof(mmMC_XBAR_ADDR_DEC[0]), 0, 0 },
+	{ "mmMC_XBAR_REMOTE", REG_MMIO, 0x0C81, &mmMC_XBAR_REMOTE[0], sizeof(mmMC_XBAR_REMOTE)/sizeof(mmMC_XBAR_REMOTE[0]), 0, 0 },
+	{ "mmMC_XBAR_WRREQ_CREDIT", REG_MMIO, 0x0C82, &mmMC_XBAR_WRREQ_CREDIT[0], sizeof(mmMC_XBAR_WRREQ_CREDIT)/sizeof(mmMC_XBAR_WRREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_CREDIT", REG_MMIO, 0x0C83, &mmMC_XBAR_RDREQ_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_CREDIT)/sizeof(mmMC_XBAR_RDREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_PRI_CREDIT", REG_MMIO, 0x0C84, &mmMC_XBAR_RDREQ_PRI_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT)/sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT1", REG_MMIO, 0x0C85, &mmMC_XBAR_WRRET_CREDIT1[0], sizeof(mmMC_XBAR_WRRET_CREDIT1)/sizeof(mmMC_XBAR_WRRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT2", REG_MMIO, 0x0C86, &mmMC_XBAR_WRRET_CREDIT2[0], sizeof(mmMC_XBAR_WRRET_CREDIT2)/sizeof(mmMC_XBAR_WRRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT1", REG_MMIO, 0x0C87, &mmMC_XBAR_RDRET_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_CREDIT1)/sizeof(mmMC_XBAR_RDRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT2", REG_MMIO, 0x0C88, &mmMC_XBAR_RDRET_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_CREDIT2)/sizeof(mmMC_XBAR_RDRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT1", REG_MMIO, 0x0C89, &mmMC_XBAR_RDRET_PRI_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT2", REG_MMIO, 0x0C8A, &mmMC_XBAR_RDRET_PRI_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_CHTRIREMAP", REG_MMIO, 0x0C8B, &mmMC_XBAR_CHTRIREMAP[0], sizeof(mmMC_XBAR_CHTRIREMAP)/sizeof(mmMC_XBAR_CHTRIREMAP[0]), 0, 0 },
+	{ "mmMC_XBAR_TWOCHAN", REG_MMIO, 0x0C8C, &mmMC_XBAR_TWOCHAN[0], sizeof(mmMC_XBAR_TWOCHAN)/sizeof(mmMC_XBAR_TWOCHAN[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB", REG_MMIO, 0x0C8D, &mmMC_XBAR_ARB[0], sizeof(mmMC_XBAR_ARB)/sizeof(mmMC_XBAR_ARB[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB_MAX_BURST", REG_MMIO, 0x0C8E, &mmMC_XBAR_ARB_MAX_BURST[0], sizeof(mmMC_XBAR_ARB_MAX_BURST)/sizeof(mmMC_XBAR_ARB_MAX_BURST[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL0", REG_MMIO, 0x0C8F, &mmMC_XBAR_PERF_MON_CNTL0[0], sizeof(mmMC_XBAR_PERF_MON_CNTL0)/sizeof(mmMC_XBAR_PERF_MON_CNTL0[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL1", REG_MMIO, 0x0C90, &mmMC_XBAR_PERF_MON_CNTL1[0], sizeof(mmMC_XBAR_PERF_MON_CNTL1)/sizeof(mmMC_XBAR_PERF_MON_CNTL1[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL2", REG_MMIO, 0x0C91, &mmMC_XBAR_PERF_MON_CNTL2[0], sizeof(mmMC_XBAR_PERF_MON_CNTL2)/sizeof(mmMC_XBAR_PERF_MON_CNTL2[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT0", REG_MMIO, 0x0C92, &mmMC_XBAR_PERF_MON_RSLT0[0], sizeof(mmMC_XBAR_PERF_MON_RSLT0)/sizeof(mmMC_XBAR_PERF_MON_RSLT0[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT1", REG_MMIO, 0x0C93, &mmMC_XBAR_PERF_MON_RSLT1[0], sizeof(mmMC_XBAR_PERF_MON_RSLT1)/sizeof(mmMC_XBAR_PERF_MON_RSLT1[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT2", REG_MMIO, 0x0C94, &mmMC_XBAR_PERF_MON_RSLT2[0], sizeof(mmMC_XBAR_PERF_MON_RSLT2)/sizeof(mmMC_XBAR_PERF_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT3", REG_MMIO, 0x0C95, &mmMC_XBAR_PERF_MON_RSLT3[0], sizeof(mmMC_XBAR_PERF_MON_RSLT3)/sizeof(mmMC_XBAR_PERF_MON_RSLT3[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_MAX_THSH", REG_MMIO, 0x0C96, &mmMC_XBAR_PERF_MON_MAX_THSH[0], sizeof(mmMC_XBAR_PERF_MON_MAX_THSH)/sizeof(mmMC_XBAR_PERF_MON_MAX_THSH[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE0", REG_MMIO, 0x0C97, &mmMC_XBAR_SPARE0[0], sizeof(mmMC_XBAR_SPARE0)/sizeof(mmMC_XBAR_SPARE0[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE1", REG_MMIO, 0x0C98, &mmMC_XBAR_SPARE1[0], sizeof(mmMC_XBAR_SPARE1)/sizeof(mmMC_XBAR_SPARE1[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_LOW_ADDR", REG_MMIO, 0x0CC0, &mmATC_VM_APERTURE0_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE0_LOW_ADDR)/sizeof(mmATC_VM_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_LOW_ADDR", REG_MMIO, 0x0CC1, &mmATC_VM_APERTURE1_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE1_LOW_ADDR)/sizeof(mmATC_VM_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_HIGH_ADDR", REG_MMIO, 0x0CC2, &mmATC_VM_APERTURE0_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE0_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_HIGH_ADDR", REG_MMIO, 0x0CC3, &mmATC_VM_APERTURE1_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE1_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL", REG_MMIO, 0x0CC4, &mmATC_VM_APERTURE0_CNTL[0], sizeof(mmATC_VM_APERTURE0_CNTL)/sizeof(mmATC_VM_APERTURE0_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL", REG_MMIO, 0x0CC5, &mmATC_VM_APERTURE1_CNTL[0], sizeof(mmATC_VM_APERTURE1_CNTL)/sizeof(mmATC_VM_APERTURE1_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL2", REG_MMIO, 0x0CC6, &mmATC_VM_APERTURE0_CNTL2[0], sizeof(mmATC_VM_APERTURE0_CNTL2)/sizeof(mmATC_VM_APERTURE0_CNTL2[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL2", REG_MMIO, 0x0CC7, &mmATC_VM_APERTURE1_CNTL2[0], sizeof(mmATC_VM_APERTURE1_CNTL2)/sizeof(mmATC_VM_APERTURE1_CNTL2[0]), 0, 0 },
+	{ "mmATC_ATS_CNTL", REG_MMIO, 0x0CC9, &mmATC_ATS_CNTL[0], sizeof(mmATC_ATS_CNTL)/sizeof(mmATC_ATS_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_DEBUG", REG_MMIO, 0x0CCA, &mmATC_ATS_DEBUG[0], sizeof(mmATC_ATS_DEBUG)/sizeof(mmATC_ATS_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_DEBUG", REG_MMIO, 0x0CCB, &mmATC_ATS_FAULT_DEBUG[0], sizeof(mmATC_ATS_FAULT_DEBUG)/sizeof(mmATC_ATS_FAULT_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_STATUS", REG_MMIO, 0x0CCC, &mmATC_ATS_STATUS[0], sizeof(mmATC_ATS_STATUS)/sizeof(mmATC_ATS_STATUS[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_CNTL", REG_MMIO, 0x0CCD, &mmATC_ATS_FAULT_CNTL[0], sizeof(mmATC_ATS_FAULT_CNTL)/sizeof(mmATC_ATS_FAULT_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_INFO", REG_MMIO, 0x0CCE, &mmATC_ATS_FAULT_STATUS_INFO[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO)/sizeof(mmATC_ATS_FAULT_STATUS_INFO[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_ADDR", REG_MMIO, 0x0CCF, &mmATC_ATS_FAULT_STATUS_ADDR[0], sizeof(mmATC_ATS_FAULT_STATUS_ADDR)/sizeof(mmATC_ATS_FAULT_STATUS_ADDR[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_LOW", REG_MMIO, 0x0CD0, &mmATC_ATS_DEFAULT_PAGE_LOW[0], sizeof(mmATC_ATS_DEFAULT_PAGE_LOW)/sizeof(mmATC_ATS_DEFAULT_PAGE_LOW[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_CNTL", REG_MMIO, 0x0CD1, &mmATC_ATS_DEFAULT_PAGE_CNTL[0], sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL)/sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL[0]), 0, 0 },
+	{ "mmATC_MISC_CG", REG_MMIO, 0x0CD4, &mmATC_MISC_CG[0], sizeof(mmATC_MISC_CG)/sizeof(mmATC_MISC_CG[0]), 0, 0 },
+	{ "mmATC_L2_CNTL", REG_MMIO, 0x0CD5, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG", REG_MMIO, 0x0CD7, &mmATC_L2_DEBUG[0], sizeof(mmATC_L2_DEBUG)/sizeof(mmATC_L2_DEBUG[0]), 0, 0 },
+	{ "mmATC_L1_CNTL", REG_MMIO, 0x0CDC, &mmATC_L1_CNTL[0], sizeof(mmATC_L1_CNTL)/sizeof(mmATC_L1_CNTL[0]), 0, 0 },
+	{ "mmATC_L1_ADDRESS_OFFSET", REG_MMIO, 0x0CDD, &mmATC_L1_ADDRESS_OFFSET[0], sizeof(mmATC_L1_ADDRESS_OFFSET)/sizeof(mmATC_L1_ADDRESS_OFFSET[0]), 0, 0 },
+	{ "mmATC_L1RD_DEBUG_TLB", REG_MMIO, 0x0CDE, &mmATC_L1RD_DEBUG_TLB[0], sizeof(mmATC_L1RD_DEBUG_TLB)/sizeof(mmATC_L1RD_DEBUG_TLB[0]), 0, 0 },
+	{ "mmATC_L1WR_DEBUG_TLB", REG_MMIO, 0x0CDF, &mmATC_L1WR_DEBUG_TLB[0], sizeof(mmATC_L1WR_DEBUG_TLB)/sizeof(mmATC_L1WR_DEBUG_TLB[0]), 0, 0 },
+	{ "mmATC_L1RD_STATUS", REG_MMIO, 0x0CE0, &mmATC_L1RD_STATUS[0], sizeof(mmATC_L1RD_STATUS)/sizeof(mmATC_L1RD_STATUS[0]), 0, 0 },
+	{ "mmATC_L1WR_STATUS", REG_MMIO, 0x0CE1, &mmATC_L1WR_STATUS[0], sizeof(mmATC_L1WR_STATUS)/sizeof(mmATC_L1WR_STATUS[0]), 0, 0 },
+	{ "mmATC_VMID_PASID_MAPPING_UPDATE_STATUS", REG_MMIO, 0x0CE6, &mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0], sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)/sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmATC_VMID0_PASID_MAPPING", REG_MMIO, 0x0CE7, &mmATC_VMID0_PASID_MAPPING[0], sizeof(mmATC_VMID0_PASID_MAPPING)/sizeof(mmATC_VMID0_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID1_PASID_MAPPING", REG_MMIO, 0x0CE8, &mmATC_VMID1_PASID_MAPPING[0], sizeof(mmATC_VMID1_PASID_MAPPING)/sizeof(mmATC_VMID1_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID2_PASID_MAPPING", REG_MMIO, 0x0CE9, &mmATC_VMID2_PASID_MAPPING[0], sizeof(mmATC_VMID2_PASID_MAPPING)/sizeof(mmATC_VMID2_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID3_PASID_MAPPING", REG_MMIO, 0x0CEA, &mmATC_VMID3_PASID_MAPPING[0], sizeof(mmATC_VMID3_PASID_MAPPING)/sizeof(mmATC_VMID3_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID4_PASID_MAPPING", REG_MMIO, 0x0CEB, &mmATC_VMID4_PASID_MAPPING[0], sizeof(mmATC_VMID4_PASID_MAPPING)/sizeof(mmATC_VMID4_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID5_PASID_MAPPING", REG_MMIO, 0x0CEC, &mmATC_VMID5_PASID_MAPPING[0], sizeof(mmATC_VMID5_PASID_MAPPING)/sizeof(mmATC_VMID5_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID6_PASID_MAPPING", REG_MMIO, 0x0CED, &mmATC_VMID6_PASID_MAPPING[0], sizeof(mmATC_VMID6_PASID_MAPPING)/sizeof(mmATC_VMID6_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID7_PASID_MAPPING", REG_MMIO, 0x0CEE, &mmATC_VMID7_PASID_MAPPING[0], sizeof(mmATC_VMID7_PASID_MAPPING)/sizeof(mmATC_VMID7_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID8_PASID_MAPPING", REG_MMIO, 0x0CEF, &mmATC_VMID8_PASID_MAPPING[0], sizeof(mmATC_VMID8_PASID_MAPPING)/sizeof(mmATC_VMID8_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID9_PASID_MAPPING", REG_MMIO, 0x0CF0, &mmATC_VMID9_PASID_MAPPING[0], sizeof(mmATC_VMID9_PASID_MAPPING)/sizeof(mmATC_VMID9_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID10_PASID_MAPPING", REG_MMIO, 0x0CF1, &mmATC_VMID10_PASID_MAPPING[0], sizeof(mmATC_VMID10_PASID_MAPPING)/sizeof(mmATC_VMID10_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID11_PASID_MAPPING", REG_MMIO, 0x0CF2, &mmATC_VMID11_PASID_MAPPING[0], sizeof(mmATC_VMID11_PASID_MAPPING)/sizeof(mmATC_VMID11_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID12_PASID_MAPPING", REG_MMIO, 0x0CF3, &mmATC_VMID12_PASID_MAPPING[0], sizeof(mmATC_VMID12_PASID_MAPPING)/sizeof(mmATC_VMID12_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID13_PASID_MAPPING", REG_MMIO, 0x0CF4, &mmATC_VMID13_PASID_MAPPING[0], sizeof(mmATC_VMID13_PASID_MAPPING)/sizeof(mmATC_VMID13_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID14_PASID_MAPPING", REG_MMIO, 0x0CF5, &mmATC_VMID14_PASID_MAPPING[0], sizeof(mmATC_VMID14_PASID_MAPPING)/sizeof(mmATC_VMID14_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID15_PASID_MAPPING", REG_MMIO, 0x0CF6, &mmATC_VMID15_PASID_MAPPING[0], sizeof(mmATC_VMID15_PASID_MAPPING)/sizeof(mmATC_VMID15_PASID_MAPPING[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_INDEX", REG_MMIO, 0x0D40, &mmGMCON_RENG_RAM_INDEX[0], sizeof(mmGMCON_RENG_RAM_INDEX)/sizeof(mmGMCON_RENG_RAM_INDEX[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_DATA", REG_MMIO, 0x0D41, &mmGMCON_RENG_RAM_DATA[0], sizeof(mmGMCON_RENG_RAM_DATA)/sizeof(mmGMCON_RENG_RAM_DATA[0]), 0, 0 },
+	{ "mmGMCON_RENG_EXECUTE", REG_MMIO, 0x0D42, &mmGMCON_RENG_EXECUTE[0], sizeof(mmGMCON_RENG_EXECUTE)/sizeof(mmGMCON_RENG_EXECUTE[0]), 0, 0 },
+	{ "mmGMCON_MISC", REG_MMIO, 0x0D43, &mmGMCON_MISC[0], sizeof(mmGMCON_MISC)/sizeof(mmGMCON_MISC[0]), 0, 0 },
+	{ "mmGMCON_MISC2", REG_MMIO, 0x0D44, &mmGMCON_MISC2[0], sizeof(mmGMCON_MISC2)/sizeof(mmGMCON_MISC2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0x0D45, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0x0D46, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0x0D47, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0", REG_MMIO, 0x0D48, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0x0D49, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL0", REG_MMIO, 0x0D4A, &mmGMCON_PERF_MON_CNTL0[0], sizeof(mmGMCON_PERF_MON_CNTL0)/sizeof(mmGMCON_PERF_MON_CNTL0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL1", REG_MMIO, 0x0D4B, &mmGMCON_PERF_MON_CNTL1[0], sizeof(mmGMCON_PERF_MON_CNTL1)/sizeof(mmGMCON_PERF_MON_CNTL1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT0", REG_MMIO, 0x0D4C, &mmGMCON_PERF_MON_RSLT0[0], sizeof(mmGMCON_PERF_MON_RSLT0)/sizeof(mmGMCON_PERF_MON_RSLT0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT1", REG_MMIO, 0x0D4D, &mmGMCON_PERF_MON_RSLT1[0], sizeof(mmGMCON_PERF_MON_RSLT1)/sizeof(mmGMCON_PERF_MON_RSLT1[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_CONFIG", REG_MMIO, 0x0D4E, &mmGMCON_PGFSM_CONFIG[0], sizeof(mmGMCON_PGFSM_CONFIG)/sizeof(mmGMCON_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_WRITE", REG_MMIO, 0x0D4F, &mmGMCON_PGFSM_WRITE[0], sizeof(mmGMCON_PGFSM_WRITE)/sizeof(mmGMCON_PGFSM_WRITE[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_READ", REG_MMIO, 0x0D50, &mmGMCON_PGFSM_READ[0], sizeof(mmGMCON_PGFSM_READ)/sizeof(mmGMCON_PGFSM_READ[0]), 0, 0 },
+	{ "mmGMCON_MISC3", REG_MMIO, 0x0D51, &mmGMCON_MISC3[0], sizeof(mmGMCON_MISC3)/sizeof(mmGMCON_MISC3[0]), 0, 0 },
+	{ "mmGMCON_DEBUG", REG_MMIO, 0x0D5F, &mmGMCON_DEBUG[0], sizeof(mmGMCON_DEBUG)/sizeof(mmGMCON_DEBUG[0]), 0, 0 },
diff --git a/src/lib/ip/gmc70.c b/src/lib/ip/gmc70.c
new file mode 100644
index 0000000..6255e96
--- /dev/null
+++ b/src/lib/ip/gmc70.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gmc70_bits.i"
+
+static const struct umr_reg gmc70_registers[] = {
+#include "gmc70_regs.i"
+};
+
+
+struct umr_ip_block *umr_create_gmc70(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gmc70";
+	ip->no_regs = sizeof(gmc70_registers)/sizeof(gmc70_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gmc70_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, gmc70_registers, sizeof(gmc70_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gmc70_bits.i b/src/lib/ip/gmc70_bits.i
new file mode 100644
index 0000000..e3b00a5
--- /dev/null
+++ b/src/lib/ip/gmc70_bits.i
@@ -0,0 +1,4294 @@
+static struct umr_bitfield mmVM_L2_CNTL[] = {
+	 { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default },
+	 { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default },
+	 { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default },
+	 { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default },
+	 { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default },
+	 { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default },
+	 { "L2_CACHE_4K_SWAP_TAG_INDEX_LSBS", 26, 27, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL2[] = {
+	 { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_VMID_MODE", 23, 25, &umr_bitfield_default },
+	 { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default },
+	 { "PDE_CACHE_EFFECTIVE_SIZE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL3[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default },
+	 { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default },
+	 { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default },
+	 { "PDE_CACHE_FORCE_MISS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_STATUS[] = {
+	 { "L2_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = {
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = {
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = {
+	 { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default },
+	 { "DUMMY_PAGE_COMPARE_MASK", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR[] = {
+	 { "DUMMY_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL2[] = {
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL2[] = {
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_REQUEST[] = {
+	 { "INVALIDATE_DOMAIN_0", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_1", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_2", 2, 2, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_3", 3, 3, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_4", 4, 4, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_5", 5, 5, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_6", 6, 6, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_7", 7, 7, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_8", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_9", 9, 9, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_10", 10, 10, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_11", 11, 11, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_12", 12, 12, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_13", 13, 13, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_14", 14, 14, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_RESPONSE[] = {
+	 { "DOMAIN_INVALIDATED_0", 0, 0, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_1", 1, 1, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_2", 2, 2, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_3", 3, 3, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_4", 4, 4, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_5", 5, 5, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_6", 6, 6, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_7", 7, 7, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_8", 8, 8, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_9", 9, 9, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_10", 10, 10, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_11", 11, 11, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_12", 12, 12, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_13", 13, 13, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_14", 14, 14, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_CNTL[] = {
+	 { "CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS", 0, 0, &umr_bitfield_default },
+	 { "TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_STORE_INVALID_ENTRIES", 2, 2, &umr_bitfield_default },
+	 { "L1_TLB_STORE_INVALID_ENTRIES", 3, 3, &umr_bitfield_default },
+	 { "CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS", 4, 4, &umr_bitfield_default },
+	 { "TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+	 { "MASK_PDE0_FAULT", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = {
+	 { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 19, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 19, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[] = {
+	 { "NAME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[] = {
+	 { "NAME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_FAULT_CLIENT_ID[] = {
+	 { "MEMORY_CLIENT", 0, 8, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_MASK", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DEBUG[] = {
+	 { "FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CG[] = {
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKA[] = {
+	 { "BANK_SELECT_MASK", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKB[] = {
+	 { "BANK_SELECT_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[] = {
+	 { "PHYSICAL_PAGE_OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERF_MON_CNTL0_ECC[] = {
+	 { "ALLOW_WRAP", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG[] = {
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
+	 { "MCC_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHMAP[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "NOOFCHAN", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHREMAP[] = {
+	 { "CHAN0", 0, 2, &umr_bitfield_default },
+	 { "CHAN1", 3, 5, &umr_bitfield_default },
+	 { "CHAN2", 6, 8, &umr_bitfield_default },
+	 { "CHAN3", 9, 11, &umr_bitfield_default },
+	 { "CHAN4", 12, 14, &umr_bitfield_default },
+	 { "CHAN5", 15, 17, &umr_bitfield_default },
+	 { "CHAN6", 18, 20, &umr_bitfield_default },
+	 { "CHAN7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "SH", 4, 7, &umr_bitfield_default },
+	 { "IA", 8, 11, &umr_bitfield_default },
+	 { "ACPG", 12, 15, &umr_bitfield_default },
+	 { "ACPO", 16, 19, &umr_bitfield_default },
+	 { "XDMAM", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "SH", 4, 7, &umr_bitfield_default },
+	 { "ACPG", 8, 11, &umr_bitfield_default },
+	 { "ACPO", 12, 15, &umr_bitfield_default },
+	 { "XDMA", 16, 19, &umr_bitfield_default },
+	 { "XDMAM", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_SYS[] = {
+	 { "RLC", 0, 3, &umr_bitfield_default },
+	 { "VMC", 4, 7, &umr_bitfield_default },
+	 { "SDMA1", 8, 11, &umr_bitfield_default },
+	 { "DMIF", 12, 15, &umr_bitfield_default },
+	 { "MCIF", 16, 19, &umr_bitfield_default },
+	 { "SMU", 20, 23, &umr_bitfield_default },
+	 { "VCE", 24, 27, &umr_bitfield_default },
+	 { "VCEU", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_SYS[] = {
+	 { "IH", 0, 3, &umr_bitfield_default },
+	 { "MCIF", 4, 7, &umr_bitfield_default },
+	 { "RLC", 8, 11, &umr_bitfield_default },
+	 { "SAM", 12, 15, &umr_bitfield_default },
+	 { "SMU", 16, 19, &umr_bitfield_default },
+	 { "SDMA1", 20, 23, &umr_bitfield_default },
+	 { "VCE", 24, 27, &umr_bitfield_default },
+	 { "VCEU", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_OTH[] = {
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "SDMA0", 4, 7, &umr_bitfield_default },
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "UVD_EXT1", 24, 27, &umr_bitfield_default },
+	 { "SAM", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_OTH[] = {
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "SDMA0", 4, 7, &umr_bitfield_default },
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "XDP", 24, 27, &umr_bitfield_default },
+	 { "UVD_EXT1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_LOCATION[] = {
+	 { "FB_BASE", 0, 15, &umr_bitfield_default },
+	 { "FB_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_TOP[] = {
+	 { "AGP_TOP", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BOT[] = {
+	 { "AGP_BOT", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BASE[] = {
+	 { "AGP_BASE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_CNTL[] = {
+	 { "DC_WRITE_HIT_REGION_0_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_1_MODE", 2, 3, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_2_MODE", 4, 5, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_3_MODE", 6, 7, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_LOCAL", 8, 8, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_SYSTEM", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = {
+	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L1_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
+	 { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default },
+	 { "ECO_BITS", 7, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_OFFSET[] = {
+	 { "FB_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_STEERING[] = {
+	 { "DEFAULT_STEERING", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MCD_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "INDEX", 13, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MEM_POWER_LS[] = {
+	 { "LS_SETUP", 0, 5, &umr_bitfield_default },
+	 { "LS_HOLD", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_BLACKOUT_CNTL[] = {
+	 { "BLACKOUT_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_POWER[] = {
+	 { "SRBM_GATE_OVERRIDE", 2, 2, &umr_bitfield_default },
+	 { "PM_BLACKOUT_CNTL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_HUB_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_VM_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_SIP_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_DBG[] = {
+	 { "SELECT0", 0, 3, &umr_bitfield_default },
+	 { "SELECT1", 4, 7, &umr_bitfield_default },
+	 { "CTRL0", 8, 12, &umr_bitfield_default },
+	 { "CTRL1", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_STATUS[] = {
+	 { "OUTSTANDING_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDREQ", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDRET", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRREQ", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRRET", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_READ", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_WRITE", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_READ", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_WRITE", 9, 9, &umr_bitfield_default },
+	 { "RPB_BUSY", 10, 10, &umr_bitfield_default },
+	 { "WRITE_DEADLOCK_WARNING", 11, 11, &umr_bitfield_default },
+	 { "READ_DEADLOCK_WARNING", 12, 12, &umr_bitfield_default },
+	 { "GFX_BUSY", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_OVERRIDE[] = {
+	 { "IDLE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_FRAMING[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CNTL[] = {
+	 { "JUMPAHEAD_GBL0", 1, 1, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_INTERNAL", 3, 3, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_REG", 5, 12, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_INTERNAL", 15, 15, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 16, 16, &umr_bitfield_default },
+	 { "LCLWRREQ_BYPASS", 17, 17, &umr_bitfield_default },
+	 { "DISP_WAIT_EOP", 18, 18, &umr_bitfield_default },
+	 { "MCD_WAIT_EOP", 19, 19, &umr_bitfield_default },
+	 { "SIP_WAIT_EOP", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ERR[] = {
+	 { "MGPU1_TARG_SYS", 0, 0, &umr_bitfield_default },
+	 { "MGPU2_TARG_SYS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RDRET", 1, 17, &umr_bitfield_default },
+	 { "WRREQ", 18, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_STATUS[] = {
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 5, 5, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 6, 6, &umr_bitfield_default },
+	 { "GBL0_BYPASS_STOR_FULL", 7, 7, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 8, 8, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 9, 9, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_STATUS[] = {
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 5, 5, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 6, 6, &umr_bitfield_default },
+	 { "GBL0_BYPASS_STOR_FULL", 7, 7, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 8, 8, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 9, 9, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 10, 10, &umr_bitfield_default },
+	 { "PWRXPRESS_ERR", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_STATUS[] = {
+	 { "MCDW_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDX_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDY_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_AVAIL", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CNTL[] = {
+	 { "REMOTE_BLACKOUT", 0, 0, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL0", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 3, 3, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCDW_STALL_MODE", 5, 5, &umr_bitfield_default },
+	 { "MCDX_STALL_MODE", 6, 6, &umr_bitfield_default },
+	 { "MCDY_STALL_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCDZ_STALL_MODE", 8, 8, &umr_bitfield_default },
+	 { "BREAK_HDP_DEADLOCK", 9, 9, &umr_bitfield_default },
+	 { "DEBUG_REG", 10, 16, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 18, 18, &umr_bitfield_default },
+	 { "PWRXPRESS_MODE", 19, 19, &umr_bitfield_default },
+	 { "ACPG_HP_TO_MCD_OVERRIDE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_CNTL[] = {
+	 { "JUMPAHEAD", 0, 0, &umr_bitfield_default },
+	 { "BP", 1, 20, &umr_bitfield_default },
+	 { "BP_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_REG", 22, 29, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 30, 30, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS[] = {
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MGPU2[] = {
+	 { "CID2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL0[] = {
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL1[] = {
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MGPU[] = {
+	 { "STOR", 0, 7, &umr_bitfield_default },
+	 { "CID", 8, 15, &umr_bitfield_default },
+	 { "MGPU_PRIORITY_TIME", 16, 22, &umr_bitfield_default },
+	 { "ENABLE", 23, 23, &umr_bitfield_default },
+	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS[] = {
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS2[] = {
+	 { "STOR1_PRI", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_SHARED_DAGB_DLY[] = {
+	 { "DLY", 0, 5, &umr_bitfield_default },
+	 { "CLI", 16, 20, &umr_bitfield_default },
+	 { "POS", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_IDLE_STATUS[] = {
+	 { "OUTSTANDING_GFX_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_GFX_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_READ", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_WRITE", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_READ", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_WRITE", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_READ", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_WRITE", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_READ", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_WRITE", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_READ", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_WRITE", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_READ", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_WRITE", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_READ", 14, 14, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_WRITE", 15, 15, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_READ", 16, 16, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_WRITE", 17, 17, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_READ", 18, 18, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_WRITE", 19, 19, &umr_bitfield_default },
+	 { "OUTSTANDING_IA_READ", 20, 20, &umr_bitfield_default },
+	 { "OUTSTANDING_IA_WRITE", 21, 21, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_READ", 22, 22, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_WRITE", 23, 23, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_READ", 24, 24, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_WRITE", 25, 25, &umr_bitfield_default },
+	 { "OUTSTANDING_CP_READ", 26, 26, &umr_bitfield_default },
+	 { "OUTSTANDING_CP_WRITE", 27, 27, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_READ", 28, 28, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_WRITE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPG_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH3[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_IA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_IA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDW[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDX[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDY[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDZ[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SIP[] = {
+	 { "ASK_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "DUMMY", 7, 7, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL0[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL1[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SMU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SDMA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_HDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SDMA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_RLC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SEM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UVD[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_IA[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCEU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDW[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDX[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDY[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDZ[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SIP[] = {
+	 { "STALL_MODE", 0, 1, &umr_bitfield_default },
+	 { "ASK_CREDITS", 2, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SDMA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_IH[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_RLC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SEM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SMU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UVD[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_HDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SDMA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDW[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDX[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDY[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDZ[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCEU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMA[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_XDMAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPO[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ACPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ACPO[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CPC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CPF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CPC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CPF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_L1_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_UNTRANSLATED_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_L1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR4[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR5[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR6[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR7[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR8[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR9[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP0[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP1[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP2[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP3[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP4[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP5[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP6[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP7[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP8[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP9[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP0[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP1[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP2[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP3[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG0[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG1[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG2[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG3[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG4[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG5[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG6[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG7[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG8[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG9[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG10[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG11[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG12[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG13[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG14[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG15[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG16[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG17[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG18[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG19[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_LB_ADDR[] = {
+	 { "CMP0", 0, 9, &umr_bitfield_default },
+	 { "MASK0", 10, 19, &umr_bitfield_default },
+	 { "CMP1", 20, 25, &umr_bitfield_default },
+	 { "MASK1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_HST[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_SID[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_STS[] = {
+	 { "PBUF_VLD", 0, 15, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 16, 22, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 23, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_CFG[] = {
+	 { "TIMEOUT", 0, 15, &umr_bitfield_default },
+	 { "HST_MAX", 16, 17, &umr_bitfield_default },
+	 { "SID_MAX", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_CFG[] = {
+	 { "ADDR_SIZE", 0, 3, &umr_bitfield_default },
+	 { "SEND_BAR", 4, 5, &umr_bitfield_default },
+	 { "SNOOP", 6, 6, &umr_bitfield_default },
+	 { "SEND_DIS", 7, 7, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 8, 8, &umr_bitfield_default },
+	 { "UPDATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "REGBAR_FROM_SYSBAR", 10, 10, &umr_bitfield_default },
+	 { "RD_EN", 11, 11, &umr_bitfield_default },
+	 { "ATC_TRANSLATED", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR0[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR1[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR2[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR3[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR4[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR5[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR6[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR7[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_SETUP[] = {
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DEBUG[] = {
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "HOST_FLUSH", 8, 11, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_ABOVE[] = {
+	 { "EN", 0, 7, &umr_bitfield_default },
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_BELOW[] = {
+	 { "EN", 0, 7, &umr_bitfield_default },
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR4[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR5[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR6[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR7[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR8[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR9[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLK_GAT[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG[] = {
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "MC_WRRET_ASK", 8, 15, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 16, 22, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_SEL", 23, 23, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_VAL", 24, 24, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_SEL", 25, 25, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_VAL", 26, 26, &umr_bitfield_default },
+	 { "XSP_SNOOP_SEL", 27, 28, &umr_bitfield_default },
+	 { "XSP_SNOOP_VAL", 29, 29, &umr_bitfield_default },
+	 { "XSP_ORDERING_SEL", 30, 30, &umr_bitfield_default },
+	 { "XSP_ORDERING_VAL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_STS[] = {
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 8, 14, &umr_bitfield_default },
+	 { "HOP_DATA_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "HOP_ATTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "CNS_BUF_FULL", 17, 17, &umr_bitfield_default },
+	 { "CNS_BUF_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RPB_RDREQ_CRD", 19, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PIPE_STS[] = {
+	 { "WCB_ANY_PBUF", 0, 0, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 1, 7, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 8, 14, &umr_bitfield_default },
+	 { "WCB_HST_RD_PTR_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "WCB_SID_RD_PTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "WCB_HST_REQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "WCB_SID_REQ_FIFO_FULL", 18, 18, &umr_bitfield_default },
+	 { "WCB_HST_REQ_OBUF_FULL", 19, 19, &umr_bitfield_default },
+	 { "WCB_SID_REQ_OBUF_FULL", 20, 20, &umr_bitfield_default },
+	 { "WCB_HST_DATA_OBUF_FULL", 21, 21, &umr_bitfield_default },
+	 { "WCB_SID_DATA_OBUF_FULL", 22, 22, &umr_bitfield_default },
+	 { "RET_BUF_FULL", 23, 23, &umr_bitfield_default },
+	 { "XPB_CLK_BUSY_BITS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_SUB_CTRL[] = {
+	 { "WRREQ_BYPASS_XPB", 0, 0, &umr_bitfield_default },
+	 { "STALL_CNS_RTR_REQ", 1, 1, &umr_bitfield_default },
+	 { "STALL_RTR_RPB_WRREQ", 2, 2, &umr_bitfield_default },
+	 { "STALL_RTR_MAP_REQ", 3, 3, &umr_bitfield_default },
+	 { "STALL_MAP_WCB_REQ", 4, 4, &umr_bitfield_default },
+	 { "STALL_WCB_SID_REQ", 5, 5, &umr_bitfield_default },
+	 { "STALL_MC_XSP_REQ_SEND", 6, 6, &umr_bitfield_default },
+	 { "STALL_WCB_HST_REQ", 7, 7, &umr_bitfield_default },
+	 { "STALL_HST_HOP_REQ", 8, 8, &umr_bitfield_default },
+	 { "STALL_XPB_RPB_REQ_ATTR", 9, 9, &umr_bitfield_default },
+	 { "RESET_CNS", 10, 10, &umr_bitfield_default },
+	 { "RESET_RTR", 11, 11, &umr_bitfield_default },
+	 { "RESET_RET", 12, 12, &umr_bitfield_default },
+	 { "RESET_MAP", 13, 13, &umr_bitfield_default },
+	 { "RESET_WCB", 14, 14, &umr_bitfield_default },
+	 { "RESET_HST", 15, 15, &umr_bitfield_default },
+	 { "RESET_HOP", 16, 16, &umr_bitfield_default },
+	 { "RESET_SID", 17, 17, &umr_bitfield_default },
+	 { "RESET_SRB", 18, 18, &umr_bitfield_default },
+	 { "RESET_CGR", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[] = {
+	 { "ALTER_FLUSH_NUM", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PERF_KNOBS[] = {
+	 { "CNS_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+	 { "WCB_HST_FIFO_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "WCB_SID_FIFO_DEPTH", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY_W1C[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MISC_CFG[] = {
+	 { "FIELDNAME0", 0, 7, &umr_bitfield_default },
+	 { "FIELDNAME1", 8, 15, &umr_bitfield_default },
+	 { "FIELDNAME2", 16, 23, &umr_bitfield_default },
+	 { "FIELDNAME3", 24, 30, &umr_bitfield_default },
+	 { "TRIGGERNAME", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG20[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG21[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG22[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG23[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG24[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG25[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG26[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG27[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG28[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG29[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG30[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG31[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG2[] = {
+	 { "RPB_RDREQ_CRD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA_RD[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG32[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG33[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG34[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG35[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG36[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CONF[] = {
+	 { "XPB_PCIE_ORDER", 15, 15, &umr_bitfield_default },
+	 { "RPB_RD_PCIE_ORDER", 16, 16, &umr_bitfield_default },
+	 { "RPB_WR_PCIE_ORDER", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_IF_CONF[] = {
+	 { "RPB_BIF_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_WRRET_ASK", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_DBG1[] = {
+	 { "RPB_BIF_OUTSTANDING_RD", 0, 7, &umr_bitfield_default },
+	 { "RPB_BIF_OUTSTANDING_RD_32B", 8, 19, &umr_bitfield_default },
+	 { "DEBUG_BITS", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_EFF_CNTL[] = {
+	 { "WR_LAZY_TIMER", 0, 7, &umr_bitfield_default },
+	 { "RD_LAZY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_ARB_CNTL[] = {
+	 { "WR_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "RD_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "ATC_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_BIF_CNTL[] = {
+	 { "ARB_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "XPB_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_COMBINE_CNTL[] = {
+	 { "WC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "WC_MAX_PACKET_SIZE", 1, 2, &umr_bitfield_default },
+	 { "WC_FLUSH_TIMER", 3, 6, &umr_bitfield_default },
+	 { "WC_ALIGN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_RD_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_WR[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "UPDATE_MODE", 8, 8, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 9, 10, &umr_bitfield_default },
+	 { "READ_QUEUE", 11, 12, &umr_bitfield_default },
+	 { "UPDATE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_RD[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 8, 9, &umr_bitfield_default },
+	 { "READ_QUEUE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 1, &umr_bitfield_default },
+	 { "CLEAR_SELECTED_PERF_COUNTER", 2, 2, &umr_bitfield_default },
+	 { "CLEAR_ALL_PERF_COUNTERS", 3, 3, &umr_bitfield_default },
+	 { "STOP_ON_COUNTER_SATURATION", 4, 4, &umr_bitfield_default },
+	 { "ENABLE_PERF_COUNTERS", 5, 8, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_0", 9, 13, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_1", 14, 18, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_2", 19, 23, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_3", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_STATUS[] = {
+	 { "PERFORMANCE_COUNTER_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX_DATA[] = {
+	 { "WRITE_ENTRIES", 0, 15, &umr_bitfield_default },
+	 { "READ_ENTRIES", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_XTRA_ENABLE[] = {
+	 { "CB1_RD", 0, 0, &umr_bitfield_default },
+	 { "CB1_WR", 1, 1, &umr_bitfield_default },
+	 { "DB1_RD", 2, 2, &umr_bitfield_default },
+	 { "DB1_WR", 3, 3, &umr_bitfield_default },
+	 { "TC2_RD", 4, 4, &umr_bitfield_default },
+	 { "ARB_DBG", 8, 11, &umr_bitfield_default },
+	 { "TC2_WR", 12, 12, &umr_bitfield_default },
+	 { "CB0_CONNECT_CNTL", 13, 14, &umr_bitfield_default },
+	 { "DB0_CONNECT_CNTL", 15, 16, &umr_bitfield_default },
+	 { "CB1_CONNECT_CNTL", 17, 18, &umr_bitfield_default },
+	 { "DB1_CONNECT_CNTL", 19, 20, &umr_bitfield_default },
+	 { "TC0_CONNECT_CNTL", 21, 22, &umr_bitfield_default },
+	 { "TC1_CONNECT_CNTL", 23, 24, &umr_bitfield_default },
+	 { "CB0_CID_CNTL_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DB0_CID_CNTL_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CB1_CID_CNTL_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "DB1_CID_CNTL_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "TC2_REPAIR_ENABLE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_MC_MAX_CHANNEL[] = {
+	 { "NOOFCHAN", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG[] = {
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
+	 { "INDEX", 6, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CNTL[] = {
+	 { "IGNOREPM", 2, 2, &umr_bitfield_default },
+	 { "EXEMPTPM", 3, 3, &umr_bitfield_default },
+	 { "GFX_IDLE_OVERRIDE", 4, 5, &umr_bitfield_default },
+	 { "MCD_SRBM_MASK_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "CNTR_CHMAP_MODE", 7, 7, &umr_bitfield_default },
+	 { "REMOTE_RB_CONNECT_ENABLE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_VM[] = {
+	 { "READ_ALL", 0, 5, &umr_bitfield_default },
+	 { "WRITE_ALL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_RD[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "READ_HUB", 8, 15, &umr_bitfield_default },
+	 { "READ_PRI", 16, 23, &umr_bitfield_default },
+	 { "LCL_PRI", 24, 24, &umr_bitfield_default },
+	 { "HUB_PRI", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_WR[] = {
+	 { "WRITE_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_HUB", 8, 15, &umr_bitfield_default },
+	 { "HUB_PRI", 16, 16, &umr_bitfield_default },
+	 { "LCL_PRI", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_CNTL[] = {
+	 { "JUMP_AHEAD", 0, 0, &umr_bitfield_default },
+	 { "CENTER_RD_MAX_BURST", 1, 4, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 5, 5, &umr_bitfield_default },
+	 { "CENTER_WR_MAX_BURST", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS[] = {
+	 { "REMRDRET", 0, 5, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_LP", 12, 17, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_HP", 18, 23, &umr_bitfield_default },
+	 { "CNTR_RD_LCL", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_RET_MODE[] = {
+	 { "INORDER_RD", 0, 0, &umr_bitfield_default },
+	 { "INORDER_WR", 1, 1, &umr_bitfield_default },
+	 { "REMPRI_RD", 2, 2, &umr_bitfield_default },
+	 { "REMPRI_WR", 3, 3, &umr_bitfield_default },
+	 { "LCLPRI_RD", 4, 4, &umr_bitfield_default },
+	 { "LCLPRI_WR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_DLY[] = {
+	 { "DLY", 0, 4, &umr_bitfield_default },
+	 { "CLI", 16, 20, &umr_bitfield_default },
+	 { "POS", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_REMREQ[] = {
+	 { "READ_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "WRITE_CREDITS", 7, 13, &umr_bitfield_default },
+	 { "CREDITS_ENABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS_WR[] = {
+	 { "CNTR_WR_HUB", 0, 5, &umr_bitfield_default },
+	 { "CNTR_WR_LCL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_RD_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_LOCAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_WR_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_LOCAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_CB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_DB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_HUB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_CB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_DB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_HUB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_XBAR[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_LCL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_LCL[] = {
+	 { "CB0", 12, 15, &umr_bitfield_default },
+	 { "CBCMASK0", 16, 19, &umr_bitfield_default },
+	 { "CBFMASK0", 20, 23, &umr_bitfield_default },
+	 { "DB0", 24, 27, &umr_bitfield_default },
+	 { "DBHTILE0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_LCL[] = {
+	 { "CB0", 0, 3, &umr_bitfield_default },
+	 { "CBCMASK0", 4, 7, &umr_bitfield_default },
+	 { "CBFMASK0", 8, 11, &umr_bitfield_default },
+	 { "DB0", 12, 15, &umr_bitfield_default },
+	 { "DBHTILE0", 16, 19, &umr_bitfield_default },
+	 { "SX0", 20, 23, &umr_bitfield_default },
+	 { "CBIMMED0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_CNTL2[] = {
+	 { "CID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_RSLT2[] = {
+	 { "CB_RD_BUSY", 6, 6, &umr_bitfield_default },
+	 { "DB_RD_BUSY", 7, 7, &umr_bitfield_default },
+	 { "TC0_RD_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VC0_RD_BUSY", 9, 9, &umr_bitfield_default },
+	 { "TC1_RD_BUSY", 10, 10, &umr_bitfield_default },
+	 { "VC1_RD_BUSY", 11, 11, &umr_bitfield_default },
+	 { "CB_WR_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DB_WR_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SX_WR_BUSY", 14, 14, &umr_bitfield_default },
+	 { "TC2_RD_BUSY", 15, 15, &umr_bitfield_default },
+	 { "TC0_WR_BUSY", 16, 16, &umr_bitfield_default },
+	 { "TC1_WR_BUSY", 17, 17, &umr_bitfield_default },
+	 { "TC2_WR_BUSY", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_RD_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_WR_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_VM_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_CNTL[] = {
+	 { "RESET_RD_GROUP0", 0, 0, &umr_bitfield_default },
+	 { "RESET_RD_GROUP1", 1, 1, &umr_bitfield_default },
+	 { "RESET_RD_GROUP2", 2, 2, &umr_bitfield_default },
+	 { "RESET_RD_GROUP3", 3, 3, &umr_bitfield_default },
+	 { "RESET_RD_GROUP4", 4, 4, &umr_bitfield_default },
+	 { "RESET_RD_GROUP5", 5, 5, &umr_bitfield_default },
+	 { "RESET_RD_GROUP6", 6, 6, &umr_bitfield_default },
+	 { "RESET_RD_GROUP7", 7, 7, &umr_bitfield_default },
+	 { "RESET_WR_GROUP0", 8, 8, &umr_bitfield_default },
+	 { "RESET_WR_GROUP1", 9, 9, &umr_bitfield_default },
+	 { "RESET_WR_GROUP2", 10, 10, &umr_bitfield_default },
+	 { "RESET_WR_GROUP3", 11, 11, &umr_bitfield_default },
+	 { "RESET_WR_GROUP4", 12, 12, &umr_bitfield_default },
+	 { "RESET_WR_GROUP5", 13, 13, &umr_bitfield_default },
+	 { "RESET_WR_GROUP6", 14, 14, &umr_bitfield_default },
+	 { "RESET_WR_GROUP7", 15, 15, &umr_bitfield_default },
+	 { "AGE_LOW_RATE_RD", 16, 18, &umr_bitfield_default },
+	 { "AGE_LOW_RATE_WR", 19, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS2[] = {
+	 { "ACP_WR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_FED_CNTL[] = {
+	 { "MODE", 0, 1, &umr_bitfield_default },
+	 { "WR_ERR", 2, 3, &umr_bitfield_default },
+	 { "KEEP_POISON_IN_PAGE", 4, 4, &umr_bitfield_default },
+	 { "RDRET_PARITY_NACK", 5, 5, &umr_bitfield_default },
+	 { "USE_LEGACY_NACK", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_RSV", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_STATUS[] = {
+	 { "CORR_STS0", 0, 0, &umr_bitfield_default },
+	 { "UNCORR_STS0", 1, 1, &umr_bitfield_default },
+	 { "FED_STS0", 2, 2, &umr_bitfield_default },
+	 { "RSVD0", 3, 3, &umr_bitfield_default },
+	 { "CORR_STS1", 4, 4, &umr_bitfield_default },
+	 { "UNCORR_STS1", 5, 5, &umr_bitfield_default },
+	 { "FED_STS1", 6, 6, &umr_bitfield_default },
+	 { "RSVD1", 7, 7, &umr_bitfield_default },
+	 { "CORR_CLEAR0", 8, 8, &umr_bitfield_default },
+	 { "UNCORR_CLEAR0", 9, 9, &umr_bitfield_default },
+	 { "FED_CLEAR0", 10, 10, &umr_bitfield_default },
+	 { "RSVD2", 11, 11, &umr_bitfield_default },
+	 { "CORR_CLEAR1", 12, 12, &umr_bitfield_default },
+	 { "UNCORR_CLEAR1", 13, 13, &umr_bitfield_default },
+	 { "FED_CLEAR1", 14, 14, &umr_bitfield_default },
+	 { "RSVD3", 15, 15, &umr_bitfield_default },
+	 { "RMWRD_CORR_STS0", 16, 16, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_STS0", 17, 17, &umr_bitfield_default },
+	 { "RSVD4", 18, 19, &umr_bitfield_default },
+	 { "RMWRD_CORR_STS1", 20, 20, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_STS1", 21, 21, &umr_bitfield_default },
+	 { "RSVD5", 22, 23, &umr_bitfield_default },
+	 { "RMWRD_CORR_CLEAR0", 24, 24, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_CLEAR0", 25, 25, &umr_bitfield_default },
+	 { "RSVD6", 26, 27, &umr_bitfield_default },
+	 { "RMWRD_CORR_CLEAR1", 28, 28, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_CLEAR1", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_MISC[] = {
+	 { "STREAK_BREAK", 0, 3, &umr_bitfield_default },
+	 { "COL10_HACK", 4, 4, &umr_bitfield_default },
+	 { "CWRD_IN_REPLAY", 5, 5, &umr_bitfield_default },
+	 { "NO_EOB_ALL_WR_IN_REPLAY", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_RSV", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG[] = {
+	 { "NUM_ERR_BITS", 0, 1, &umr_bitfield_default },
+	 { "DIRECTION", 2, 2, &umr_bitfield_default },
+	 { "DATA_FIELD", 3, 4, &umr_bitfield_default },
+	 { "SW_INJECTION", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG2[] = {
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+	 { "ERR0_START", 8, 15, &umr_bitfield_default },
+	 { "ERR1_START", 16, 23, &umr_bitfield_default },
+	 { "ERR2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ECC_MODE", 1, 2, &umr_bitfield_default },
+	 { "PAGE_BIT0", 3, 4, &umr_bitfield_default },
+	 { "EXOR_BANK_SEL", 5, 6, &umr_bitfield_default },
+	 { "NO_GECC_CLI", 7, 10, &umr_bitfield_default },
+	 { "READ_ERR", 11, 13, &umr_bitfield_default },
+	 { "CLOSE_BANK_RMW", 14, 14, &umr_bitfield_default },
+	 { "COLFIFO_WATER", 15, 20, &umr_bitfield_default },
+	 { "WRADDR_CONV", 21, 21, &umr_bitfield_default },
+	 { "RMWRD_UNCOR_POISON", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_CLI[] = {
+	 { "NO_GECC_CLI0", 0, 7, &umr_bitfield_default },
+	 { "NO_GECC_CLI1", 8, 15, &umr_bitfield_default },
+	 { "NO_GECC_CLI2", 16, 23, &umr_bitfield_default },
+	 { "NO_GECC_CLI3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_SWIZ0[] = {
+	 { "A8", 0, 3, &umr_bitfield_default },
+	 { "A9", 4, 7, &umr_bitfield_default },
+	 { "A10", 8, 11, &umr_bitfield_default },
+	 { "A11", 12, 15, &umr_bitfield_default },
+	 { "A12", 16, 19, &umr_bitfield_default },
+	 { "A13", 20, 23, &umr_bitfield_default },
+	 { "A14", 24, 27, &umr_bitfield_default },
+	 { "A15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_SWIZ1[] = {
+	 { "A16", 0, 3, &umr_bitfield_default },
+	 { "A17", 4, 7, &umr_bitfield_default },
+	 { "A18", 8, 11, &umr_bitfield_default },
+	 { "A19", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC3[] = {
+	 { "NO_GECC_EXT_EOB", 0, 0, &umr_bitfield_default },
+	 { "TBD_FIELD", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WCDR_2[] = {
+	 { "WPRE_INC_STEP", 0, 3, &umr_bitfield_default },
+	 { "WPRE_MIN_THRESHOLD", 4, 8, &umr_bitfield_default },
+	 { "DEBUG_0", 9, 9, &umr_bitfield_default },
+	 { "DEBUG_1", 10, 10, &umr_bitfield_default },
+	 { "DEBUG_2", 11, 11, &umr_bitfield_default },
+	 { "DEBUG_3", 12, 12, &umr_bitfield_default },
+	 { "DEBUG_4", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_5", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DATA[] = {
+	 { "PATTERN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "START_IDLE", 1, 1, &umr_bitfield_default },
+	 { "START_R2W", 2, 3, &umr_bitfield_default },
+	 { "FLUSH_ON_ENTER", 4, 4, &umr_bitfield_default },
+	 { "HARSH_START", 5, 5, &umr_bitfield_default },
+	 { "TPS_HARSH_PRIORITY", 6, 6, &umr_bitfield_default },
+	 { "TWRT_HARSH_PRIORITY", 7, 7, &umr_bitfield_default },
+	 { "BREAK_ON_HARSH", 8, 8, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTRD", 9, 9, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTWR", 10, 10, &umr_bitfield_default },
+	 { "TRAIN_PERIOD", 11, 13, &umr_bitfield_default },
+	 { "START_R2W_RFSH", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_RSV_0", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_RSV_1", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_RSV_2", 17, 17, &umr_bitfield_default },
+	 { "DEBUG_RSV_3", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_RSV_4", 19, 19, &umr_bitfield_default },
+	 { "DEBUG_RSV_5", 20, 20, &umr_bitfield_default },
+	 { "DEBUG_RSV_6", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_RSV_7", 22, 22, &umr_bitfield_default },
+	 { "DEBUG_RSV_8", 23, 23, &umr_bitfield_default },
+	 { "DATA_CNTL", 24, 24, &umr_bitfield_default },
+	 { "NEIGHBOR_BIT", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL1[] = {
+	 { "WINDOW_SIZE", 0, 4, &umr_bitfield_default },
+	 { "WINDOW_UPDATE", 5, 5, &umr_bitfield_default },
+	 { "WINDOW_INC_THRESHOLD", 6, 12, &umr_bitfield_default },
+	 { "WINDOW_DEC_THRESHOLD", 13, 19, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MAX", 20, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MIN", 25, 29, &umr_bitfield_default },
+	 { "WINDOW_UPDATE_COUNT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL2[] = {
+	 { "SAMPLE_CNT", 0, 5, &umr_bitfield_default },
+	 { "PHASE_ADJUST_THRESHOLD", 6, 11, &umr_bitfield_default },
+	 { "PHASE_ADJUST_SIZE", 12, 12, &umr_bitfield_default },
+	 { "FILTER_CNTL", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DEBUG[] = {
+	 { "DEBUG_BYTE_CH0", 0, 1, &umr_bitfield_default },
+	 { "DEBUG_BYTE_CH1", 2, 3, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH0", 4, 11, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH0", 12, 16, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH1", 17, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH1", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CAC_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "READ_WEIGHT", 1, 6, &umr_bitfield_default },
+	 { "WRITE_WEIGHT", 7, 12, &umr_bitfield_default },
+	 { "ALLOW_OVERFLOW", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC2[] = {
+	 { "TCCDL4_BANKBIT3_XOR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT4", 6, 6, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT5", 7, 7, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT6", 8, 8, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT7", 9, 9, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT8", 10, 10, &umr_bitfield_default },
+	 { "POP_IDLE_REPLAY", 11, 11, &umr_bitfield_default },
+	 { "RDRET_NO_REORDERING", 12, 12, &umr_bitfield_default },
+	 { "RDRET_NO_BP", 13, 13, &umr_bitfield_default },
+	 { "RDRET_SEQ_SKID", 14, 17, &umr_bitfield_default },
+	 { "GECC", 18, 18, &umr_bitfield_default },
+	 { "GECC_RST", 19, 19, &umr_bitfield_default },
+	 { "GECC_STATUS", 20, 20, &umr_bitfield_default },
+	 { "TAGFIFO_THRESHOLD", 21, 24, &umr_bitfield_default },
+	 { "WCDR_REPLAY_MASKCNT", 25, 27, &umr_bitfield_default },
+	 { "REPLAY_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "ARB_DEBUG29", 29, 29, &umr_bitfield_default },
+	 { "SEQ_RDY_POP_IDLE", 30, 30, &umr_bitfield_default },
+	 { "TCCDL4_REPLAY_EOB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC[] = {
+	 { "STICKY_RFSH", 0, 0, &umr_bitfield_default },
+	 { "IDLE_RFSH", 1, 1, &umr_bitfield_default },
+	 { "STUTTER_RFSH", 2, 2, &umr_bitfield_default },
+	 { "CHAN_COUPLE", 3, 10, &umr_bitfield_default },
+	 { "HARSHNESS", 11, 18, &umr_bitfield_default },
+	 { "SMART_RDWR_SW", 19, 19, &umr_bitfield_default },
+	 { "CALI_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CALI_RATES", 21, 22, &umr_bitfield_default },
+	 { "DISPURGVLD_NOWRT", 23, 23, &umr_bitfield_default },
+	 { "DISPURG_NOSW2WR", 24, 24, &umr_bitfield_default },
+	 { "DISPURG_STALL", 25, 25, &umr_bitfield_default },
+	 { "DISPURG_THROTTLE", 26, 29, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT", 30, 30, &umr_bitfield_default },
+	 { "ACPURG_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BANKMAP[] = {
+	 { "BANK0", 0, 3, &umr_bitfield_default },
+	 { "BANK1", 4, 7, &umr_bitfield_default },
+	 { "BANK2", 8, 11, &umr_bitfield_default },
+	 { "BANK3", 12, 15, &umr_bitfield_default },
+	 { "RANK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RAMCFG[] = {
+	 { "NOOFBANK", 0, 1, &umr_bitfield_default },
+	 { "NOOFRANKS", 2, 2, &umr_bitfield_default },
+	 { "NOOFROWS", 3, 5, &umr_bitfield_default },
+	 { "NOOFCOLS", 6, 7, &umr_bitfield_default },
+	 { "CHANSIZE", 8, 8, &umr_bitfield_default },
+	 { "RSV_1", 9, 9, &umr_bitfield_default },
+	 { "RSV_2", 10, 10, &umr_bitfield_default },
+	 { "RSV_3", 11, 11, &umr_bitfield_default },
+	 { "NOOFGROUPS", 12, 12, &umr_bitfield_default },
+	 { "RSV_4", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_POP[] = {
+	 { "ENABLE_ARB", 0, 0, &umr_bitfield_default },
+	 { "SPEC_OPEN", 1, 1, &umr_bitfield_default },
+	 { "POP_DEPTH", 2, 5, &umr_bitfield_default },
+	 { "WRDATAINDEX_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "SKID_DEPTH", 12, 14, &umr_bitfield_default },
+	 { "WAIT_AFTER_RFSH", 15, 16, &umr_bitfield_default },
+	 { "QUICK_STOP", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_PAGE", 18, 18, &umr_bitfield_default },
+	 { "ALLOW_EOB_BY_WRRET_STALL", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MINCLKS[] = {
+	 { "READ_CLKS", 0, 7, &umr_bitfield_default },
+	 { "WRITE_CLKS", 8, 15, &umr_bitfield_default },
+	 { "ARB_RW_SWITCH", 16, 16, &umr_bitfield_default },
+	 { "RW_SWITCH_HARSH", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SQM_CNTL[] = {
+	 { "MIN_PENAL", 0, 7, &umr_bitfield_default },
+	 { "DYN_SQM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "SQM_RDY16", 9, 9, &umr_bitfield_default },
+	 { "SQM_RESERVE", 10, 15, &umr_bitfield_default },
+	 { "RATIO", 16, 23, &umr_bitfield_default },
+	 { "RATIO_DEBUG", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_HASH[] = {
+	 { "BANK_XOR_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "COL_XOR", 4, 11, &umr_bitfield_default },
+	 { "ROW_XOR", 12, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2[] = {
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_RD[] = {
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "ACP_HARSH_PRI", 11, 11, &umr_bitfield_default },
+	 { "ACP_OVER_DISP", 12, 12, &umr_bitfield_default },
+	 { "FORCE_ACP_URG", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_WR[] = {
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "ACP_HARSH_PRI", 11, 11, &umr_bitfield_default },
+	 { "ACP_OVER_DISP", 12, 12, &umr_bitfield_default },
+	 { "FORCE_ACP_URG", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_RD[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_WR[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_RD[] = {
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_WR[] = {
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_RD[] = {
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_WR[] = {
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "URG0", 1, 5, &umr_bitfield_default },
+	 { "URG1", 6, 10, &umr_bitfield_default },
+	 { "ACCUM", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_RATE[] = {
+	 { "POWERMODE0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PM_CNTL[] = {
+	 { "OVERRIDE_CGSTATE", 0, 1, &umr_bitfield_default },
+	 { "OVRR_CGRFSH", 2, 2, &umr_bitfield_default },
+	 { "OVRR_CGSQM", 3, 3, &umr_bitfield_default },
+	 { "SRFSH_ON_D1", 4, 4, &umr_bitfield_default },
+	 { "BLKOUT_ON_D1", 5, 5, &umr_bitfield_default },
+	 { "IDLE_ON_D1", 6, 6, &umr_bitfield_default },
+	 { "OVRR_PM", 7, 7, &umr_bitfield_default },
+	 { "OVRR_PM_STATE", 8, 9, &umr_bitfield_default },
+	 { "OVRR_RD", 10, 10, &umr_bitfield_default },
+	 { "OVRR_RD_STATE", 11, 11, &umr_bitfield_default },
+	 { "OVRR_WR", 12, 12, &umr_bitfield_default },
+	 { "OVRR_WR_STATE", 13, 13, &umr_bitfield_default },
+	 { "OVRR_RFSH", 14, 14, &umr_bitfield_default },
+	 { "OVRR_RFSH_STATE", 15, 15, &umr_bitfield_default },
+	 { "RSV_0", 16, 17, &umr_bitfield_default },
+	 { "IDLE_ON_D2", 18, 18, &umr_bitfield_default },
+	 { "IDLE_ON_D3", 19, 19, &umr_bitfield_default },
+	 { "IDLE_CNT", 20, 23, &umr_bitfield_default },
+	 { "RSV_1", 24, 24, &umr_bitfield_default },
+	 { "RSV_2", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_RD_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_WR_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_RD[] = {
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_WR[] = {
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REMREQ[] = {
+	 { "RD_WATER", 0, 7, &umr_bitfield_default },
+	 { "WR_WATER", 8, 15, &umr_bitfield_default },
+	 { "WR_MAXBURST_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WR_LAZY_TIMER", 20, 23, &umr_bitfield_default },
+	 { "ENABLE_REMOTE_NACK_REQ", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REPLAY[] = {
+	 { "ENABLE_RD", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_WR", 1, 1, &umr_bitfield_default },
+	 { "WRACK_MODE", 2, 2, &umr_bitfield_default },
+	 { "WAW_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RAW_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "IGNORE_WR_CDC", 5, 5, &umr_bitfield_default },
+	 { "BREAK_ON_STALL", 6, 6, &umr_bitfield_default },
+	 { "BOS_ENABLE_WAIT_CYC", 7, 7, &umr_bitfield_default },
+	 { "BOS_WAIT_CYC", 8, 14, &umr_bitfield_default },
+	 { "NO_PCH_AT_REPLAY_START", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_RD[] = {
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "DISP", 16, 23, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_WR[] = {
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 16, 23, &umr_bitfield_default },
+	 { "WRRET_SEQ_SKID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_CID[] = {
+	 { "CID_CH0", 0, 7, &umr_bitfield_default },
+	 { "CID_CH1", 8, 15, &umr_bitfield_default },
+	 { "WRITE_CH0", 16, 16, &umr_bitfield_default },
+	 { "WRITE_CH1", 17, 17, &umr_bitfield_default },
+	 { "REALTIME_CH0", 18, 18, &umr_bitfield_default },
+	 { "REALTIME_CH1", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_RSLT0[] = {
+	 { "MAX_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_RSLT1[] = {
+	 { "MAX_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SSM[] = {
+	 { "FORMAT", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CG[] = {
+	 { "CG_ARB_REQ", 0, 7, &umr_bitfield_default },
+	 { "CG_ARB_RESP", 8, 15, &umr_bitfield_default },
+	 { "RSV_0", 16, 23, &umr_bitfield_default },
+	 { "RSV_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WCDR[] = {
+	 { "IDLE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SEQ_IDLE", 1, 1, &umr_bitfield_default },
+	 { "IDLE_PERIOD", 2, 6, &umr_bitfield_default },
+	 { "IDLE_BURST", 7, 12, &umr_bitfield_default },
+	 { "IDLE_BURST_MODE", 13, 13, &umr_bitfield_default },
+	 { "IDLE_WAKEUP", 14, 15, &umr_bitfield_default },
+	 { "IDLE_DEGLITCH_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "WPRE_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "WPRE_THRESHOLD", 18, 21, &umr_bitfield_default },
+	 { "WPRE_MAX_BURST", 22, 24, &umr_bitfield_default },
+	 { "WPRE_INC_READ", 25, 25, &umr_bitfield_default },
+	 { "WPRE_INC_SKIDIDLE", 26, 26, &umr_bitfield_default },
+	 { "WPRE_INC_SEQIDLE", 27, 27, &umr_bitfield_default },
+	 { "WPRE_TWOPAGE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING_1[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BUSY_STATUS[] = {
+	 { "LM_RD0", 0, 0, &umr_bitfield_default },
+	 { "LM_RD1", 1, 1, &umr_bitfield_default },
+	 { "LM_WR0", 2, 2, &umr_bitfield_default },
+	 { "LM_WR1", 3, 3, &umr_bitfield_default },
+	 { "HM_RD0", 4, 4, &umr_bitfield_default },
+	 { "HM_RD1", 5, 5, &umr_bitfield_default },
+	 { "HM_WR0", 6, 6, &umr_bitfield_default },
+	 { "HM_WR1", 7, 7, &umr_bitfield_default },
+	 { "WDE_RD0", 8, 8, &umr_bitfield_default },
+	 { "WDE_RD1", 9, 9, &umr_bitfield_default },
+	 { "WDE_WR0", 10, 10, &umr_bitfield_default },
+	 { "WDE_WR1", 11, 11, &umr_bitfield_default },
+	 { "POP0", 12, 12, &umr_bitfield_default },
+	 { "POP1", 13, 13, &umr_bitfield_default },
+	 { "TAGFIFO0", 14, 14, &umr_bitfield_default },
+	 { "TAGFIFO1", 15, 15, &umr_bitfield_default },
+	 { "REPLAY0", 16, 16, &umr_bitfield_default },
+	 { "REPLAY1", 17, 17, &umr_bitfield_default },
+	 { "RDRET0", 18, 18, &umr_bitfield_default },
+	 { "RDRET1", 19, 19, &umr_bitfield_default },
+	 { "GECC2_RD0", 20, 20, &umr_bitfield_default },
+	 { "GECC2_RD1", 21, 21, &umr_bitfield_default },
+	 { "GECC2_WR0", 22, 22, &umr_bitfield_default },
+	 { "GECC2_WR1", 23, 23, &umr_bitfield_default },
+	 { "WCDR0", 24, 24, &umr_bitfield_default },
+	 { "WCDR1", 25, 25, &umr_bitfield_default },
+	 { "RTT0", 26, 26, &umr_bitfield_default },
+	 { "RTT1", 27, 27, &umr_bitfield_default },
+	 { "REM_RD0", 28, 28, &umr_bitfield_default },
+	 { "REM_RD1", 29, 29, &umr_bitfield_default },
+	 { "REM_WR0", 30, 30, &umr_bitfield_default },
+	 { "REM_WR1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2_1[] = {
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BURST_TIME[] = {
+	 { "STATE0", 0, 4, &umr_bitfield_default },
+	 { "STATE1", 5, 9, &umr_bitfield_default },
+	 { "STATE2", 10, 14, &umr_bitfield_default },
+	 { "STATE3", 15, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CS0_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CS0_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CS1_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CS1_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CS2_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CS2_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CS3_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CS3_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_BANK_ADDR_MAPPING[] = {
+	 { "DIMM0ADDRMAP", 0, 3, &umr_bitfield_default },
+	 { "DIMM1ADDRMAP", 4, 7, &umr_bitfield_default },
+	 { "BANKSWIZZLEMODE", 8, 8, &umr_bitfield_default },
+	 { "BANKSWAP", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_BANK_ADDR_MAPPING[] = {
+	 { "DIMM0ADDRMAP", 0, 3, &umr_bitfield_default },
+	 { "DIMM1ADDRMAP", 4, 7, &umr_bitfield_default },
+	 { "BANKSWIZZLEMODE", 8, 8, &umr_bitfield_default },
+	 { "BANKSWAP", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CTL_BASE[] = {
+	 { "DCTSEL", 0, 2, &umr_bitfield_default },
+	 { "DCTINTLVEN", 3, 6, &umr_bitfield_default },
+	 { "DCTBASEADDR", 7, 27, &umr_bitfield_default },
+	 { "DCTOFFSETEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CTL_BASE[] = {
+	 { "DCTSEL", 0, 2, &umr_bitfield_default },
+	 { "DCTINTLVEN", 3, 6, &umr_bitfield_default },
+	 { "DCTBASEADDR", 7, 27, &umr_bitfield_default },
+	 { "DCTOFFSETEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CTL_LIMIT[] = {
+	 { "DCTLIMITADDR", 0, 20, &umr_bitfield_default },
+	 { "DRAMHOLEVALID", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CTL_LIMIT[] = {
+	 { "DCTLIMITADDR", 0, 20, &umr_bitfield_default },
+	 { "DRAMHOLEVALID", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_CTL_HIGH_01[] = {
+	 { "DCTHIGHADDROFF0", 0, 11, &umr_bitfield_default },
+	 { "DCTHIGHADDROFF1", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_CTL_HIGH_23[] = {
+	 { "DCTHIGHADDROFF2", 0, 11, &umr_bitfield_default },
+	 { "DCTHIGHADDROFF3", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_MODE[] = {
+	 { "DCTSELINTLVADDR", 0, 2, &umr_bitfield_default },
+	 { "GDDR5EN", 3, 3, &umr_bitfield_default },
+	 { "DRAMHOLEOFFSET", 4, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_APER_BASE[] = {
+	 { "BASE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_APER_TOP[] = {
+	 { "TOP", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_C6SAVE_APER_BASE[] = {
+	 { "BASE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_C6SAVE_APER_TOP[] = {
+	 { "TOP", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_APER_DEF[] = {
+	 { "DEF", 0, 27, &umr_bitfield_default },
+	 { "LOCK_MC_FUS_DRAM_REGS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_ARB_GARLIC_ISOC_PRI[] = {
+	 { "DMIF_RD_TOKURG_EN", 0, 0, &umr_bitfield_default },
+	 { "UVD_RD_TOKURG_EN", 1, 1, &umr_bitfield_default },
+	 { "VCE_RD_TOKURG_EN", 2, 2, &umr_bitfield_default },
+	 { "ACP_RD_TOKURG_EN", 3, 3, &umr_bitfield_default },
+	 { "DMIF_RD_PRIURG_EN", 4, 4, &umr_bitfield_default },
+	 { "UVD_RD_PRIURG_EN", 5, 5, &umr_bitfield_default },
+	 { "VCE_RD_PRIURG_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_RD_PRIURG_EN", 7, 7, &umr_bitfield_default },
+	 { "DMIF_RD_ISOC_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_RD_ISOC_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_RD_ISOC_EN", 10, 10, &umr_bitfield_default },
+	 { "MCIF_RD_ISOC_EN", 11, 11, &umr_bitfield_default },
+	 { "UMC_RD_ISOC_EN", 12, 12, &umr_bitfield_default },
+	 { "VCEU_RD_ISOC_EN", 13, 13, &umr_bitfield_default },
+	 { "ACP_RD_ISOC_EN", 14, 14, &umr_bitfield_default },
+	 { "REQPRI_OVERRIDE_EN", 15, 15, &umr_bitfield_default },
+	 { "REQPRI_OVERRIDE_VAL", 16, 17, &umr_bitfield_default },
+	 { "PRIPRMTE_OVERRIDE_EN", 18, 18, &umr_bitfield_default },
+	 { "TOKURG_OVERRIDE_EN", 19, 19, &umr_bitfield_default },
+	 { "PRIURG_OVERRIDE_EN", 20, 20, &umr_bitfield_default },
+	 { "PRIPRMTE_OVERRIDE_VAL", 21, 21, &umr_bitfield_default },
+	 { "TOKURG_OVERRIDE_VAL", 22, 22, &umr_bitfield_default },
+	 { "PRIURG_OVERRIDE_VAL", 23, 23, &umr_bitfield_default },
+	 { "GARLIC_REQ_CREDITS", 24, 28, &umr_bitfield_default },
+	 { "MM_REL_LATE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_ARB_GARLIC_CNTL[] = {
+	 { "RX_RDRESP_FIFO_PTR_INIT_VALUE", 0, 7, &umr_bitfield_default },
+	 { "RX_WRRESP_FIFO_PTR_INIT_VALUE", 8, 14, &umr_bitfield_default },
+	 { "EN_64_BYTE_WRITE", 15, 15, &umr_bitfield_default },
+	 { "EDC_RESPONSE_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OUTSTANDING_RDRESP_LIMIT", 17, 25, &umr_bitfield_default },
+	 { "OUTSTANDING_WRRESP_LIMIT", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_ARB_GARLIC_WR_PRI[] = {
+	 { "CB_WR_PRI", 0, 1, &umr_bitfield_default },
+	 { "DB_WR_PRI", 2, 3, &umr_bitfield_default },
+	 { "TC_WR_PRI", 4, 5, &umr_bitfield_default },
+	 { "CP_WR_PRI", 6, 7, &umr_bitfield_default },
+	 { "HDP_WR_PRI", 8, 9, &umr_bitfield_default },
+	 { "XDP_WR_PRI", 10, 11, &umr_bitfield_default },
+	 { "UMC_WR_PRI", 12, 13, &umr_bitfield_default },
+	 { "UVD_WR_PRI", 14, 15, &umr_bitfield_default },
+	 { "RLC_WR_PRI", 16, 17, &umr_bitfield_default },
+	 { "IH_WR_PRI", 18, 19, &umr_bitfield_default },
+	 { "SDMA_WR_PRI", 20, 21, &umr_bitfield_default },
+	 { "SEM_WR_PRI", 22, 23, &umr_bitfield_default },
+	 { "SH_WR_PRI", 24, 25, &umr_bitfield_default },
+	 { "MCIF_WR_PRI", 26, 27, &umr_bitfield_default },
+	 { "VCE_WR_PRI", 28, 29, &umr_bitfield_default },
+	 { "VCEU_WR_PRI", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_ARB_GARLIC_WR_PRI2[] = {
+	 { "SMU_WR_PRI", 0, 1, &umr_bitfield_default },
+	 { "SAM_WR_PRI", 2, 3, &umr_bitfield_default },
+	 { "ACP_WR_PRI", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_DATAPORT[] = {
+	 { "DATA_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ADDR_DEC[] = {
+	 { "NO_DIV_BY_3", 0, 0, &umr_bitfield_default },
+	 { "GECC", 1, 1, &umr_bitfield_default },
+	 { "RB_SPLIT", 2, 2, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_REMOTE[] = {
+	 { "WRREQ_EN_GOQ", 0, 0, &umr_bitfield_default },
+	 { "RDREQ_EN_GOQ", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_PRI_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+	 { "HUB_LP_RDRET_SKID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_CHTRIREMAP[] = {
+	 { "CH0", 0, 1, &umr_bitfield_default },
+	 { "CH1", 2, 3, &umr_bitfield_default },
+	 { "CH2", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_TWOCHAN[] = {
+	 { "DISABLE_ONEPORT", 0, 0, &umr_bitfield_default },
+	 { "CH0", 1, 2, &umr_bitfield_default },
+	 { "CH1", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB[] = {
+	 { "HUBRD_HIGHEST", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_HUB_STALL_HIGHEST", 1, 1, &umr_bitfield_default },
+	 { "BREAK_BURST_CID_CHANGE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB_MAX_BURST[] = {
+	 { "RD_PORT0", 0, 3, &umr_bitfield_default },
+	 { "RD_PORT1", 4, 7, &umr_bitfield_default },
+	 { "RD_PORT2", 8, 11, &umr_bitfield_default },
+	 { "RD_PORT3", 12, 15, &umr_bitfield_default },
+	 { "WR_PORT0", 16, 19, &umr_bitfield_default },
+	 { "WR_PORT1", 20, 23, &umr_bitfield_default },
+	 { "WR_PORT2", 24, 27, &umr_bitfield_default },
+	 { "WR_PORT3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL0[] = {
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL1[] = {
+	 { "THRESH_CNTR_ID", 0, 7, &umr_bitfield_default },
+	 { "START_TRIG_ID", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL2[] = {
+	 { "MON0_ID", 0, 7, &umr_bitfield_default },
+	 { "MON1_ID", 8, 15, &umr_bitfield_default },
+	 { "MON2_ID", 16, 23, &umr_bitfield_default },
+	 { "MON3_ID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT2[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT3[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_MAX_THSH[] = {
+	 { "MON0", 0, 7, &umr_bitfield_default },
+	 { "MON1", 8, 15, &umr_bitfield_default },
+	 { "MON2", 16, 23, &umr_bitfield_default },
+	 { "MON3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE0[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE1[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_CNTL[] = {
+	 { "DISABLE_ATC", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_PRI", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_PASID", 2, 2, &umr_bitfield_default },
+	 { "CREDITS_ATS_RPB", 8, 13, &umr_bitfield_default },
+	 { "DEBUG_ECO", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEBUG[] = {
+	 { "INVALIDATE_ALL", 0, 0, &umr_bitfield_default },
+	 { "IDENT_RETURN", 1, 1, &umr_bitfield_default },
+	 { "ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS", 2, 2, &umr_bitfield_default },
+	 { "PAGE_REQUESTS_USE_RELAXED_ORDERING", 5, 5, &umr_bitfield_default },
+	 { "PRIV_BIT", 6, 6, &umr_bitfield_default },
+	 { "EXE_BIT", 7, 7, &umr_bitfield_default },
+	 { "PAGE_REQUEST_PERMS", 8, 8, &umr_bitfield_default },
+	 { "UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE", 9, 9, &umr_bitfield_default },
+	 { "NUM_REQUESTS_AT_ERR", 10, 13, &umr_bitfield_default },
+	 { "DISALLOW_ERR_TO_DONE", 14, 14, &umr_bitfield_default },
+	 { "IGNORE_FED", 15, 15, &umr_bitfield_default },
+	 { "INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_BUS_SELECT", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_DEBUG[] = {
+	 { "CREDITS_ATS_IH", 0, 4, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES", 8, 8, &umr_bitfield_default },
+	 { "CLEAR_FAULT_STATUS_ADDR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "CRASHED", 1, 1, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_CNTL[] = {
+	 { "FAULT_REGISTER_LOG", 0, 5, &umr_bitfield_default },
+	 { "FAULT_INTERRUPT_TABLE", 10, 15, &umr_bitfield_default },
+	 { "FAULT_CRASH_TABLE", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_INFO[] = {
+	 { "FAULT_TYPE", 0, 5, &umr_bitfield_default },
+	 { "VMID", 10, 14, &umr_bitfield_default },
+	 { "EXTRA_INFO", 15, 15, &umr_bitfield_default },
+	 { "EXTRA_INFO2", 16, 16, &umr_bitfield_default },
+	 { "INVALIDATION", 17, 17, &umr_bitfield_default },
+	 { "PAGE_REQUEST", 18, 18, &umr_bitfield_default },
+	 { "STATUS", 19, 23, &umr_bitfield_default },
+	 { "PAGE_ADDR_HIGH", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_ADDR[] = {
+	 { "PAGE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_LOW[] = {
+	 { "DEFAULT_PAGE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_CNTL[] = {
+	 { "SEND_DEFAULT_PAGE", 0, 0, &umr_bitfield_default },
+	 { "DEFAULT_PAGE_HIGH", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_MISC_CG[] = {
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL[] = {
+	 { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 4, 5, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 8, 8, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL2[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE", 8, 8, &umr_bitfield_default },
+	 { "L2_CACHE_SWAP_TAG_INDEX_LSBS", 9, 11, &umr_bitfield_default },
+	 { "L2_CACHE_VMID_MODE", 12, 14, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 15, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG[] = {
+	 { "CREDITS_L2_ATS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG2[] = {
+	 { "EFFECTIVE_CACHE_SIZE", 0, 4, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 5, 7, &umr_bitfield_default },
+	 { "FORCE_CACHE_MISS", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CACHING_SPECULATIVE_READ_RETURNS", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_BUS_SELECT", 15, 16, &umr_bitfield_default },
+	 { "DEBUG_ECO", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_CNTL[] = {
+	 { "DONT_NEED_ATS_BEHAVIOR", 0, 1, &umr_bitfield_default },
+	 { "NEED_ATS_BEHAVIOR", 2, 2, &umr_bitfield_default },
+	 { "NEED_ATS_SNOOP_DEFAULT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_ADDRESS_OFFSET[] = {
+	 { "LOGICAL_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[] = {
+	 { "VMID0_REMAPPING_FINISHED", 0, 0, &umr_bitfield_default },
+	 { "VMID1_REMAPPING_FINISHED", 1, 1, &umr_bitfield_default },
+	 { "VMID2_REMAPPING_FINISHED", 2, 2, &umr_bitfield_default },
+	 { "VMID3_REMAPPING_FINISHED", 3, 3, &umr_bitfield_default },
+	 { "VMID4_REMAPPING_FINISHED", 4, 4, &umr_bitfield_default },
+	 { "VMID5_REMAPPING_FINISHED", 5, 5, &umr_bitfield_default },
+	 { "VMID6_REMAPPING_FINISHED", 6, 6, &umr_bitfield_default },
+	 { "VMID7_REMAPPING_FINISHED", 7, 7, &umr_bitfield_default },
+	 { "VMID8_REMAPPING_FINISHED", 8, 8, &umr_bitfield_default },
+	 { "VMID9_REMAPPING_FINISHED", 9, 9, &umr_bitfield_default },
+	 { "VMID10_REMAPPING_FINISHED", 10, 10, &umr_bitfield_default },
+	 { "VMID11_REMAPPING_FINISHED", 11, 11, &umr_bitfield_default },
+	 { "VMID12_REMAPPING_FINISHED", 12, 12, &umr_bitfield_default },
+	 { "VMID13_REMAPPING_FINISHED", 13, 13, &umr_bitfield_default },
+	 { "VMID14_REMAPPING_FINISHED", 14, 14, &umr_bitfield_default },
+	 { "VMID15_REMAPPING_FINISHED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID0_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID1_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID2_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID3_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID4_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID5_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID6_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID7_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID8_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID9_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID10_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID11_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID12_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID13_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID14_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID15_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_INDEX[] = {
+	 { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_DATA[] = {
+	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_EXECUTE[] = {
+	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW_START_PTR", 2, 11, &umr_bitfield_default },
+	 { "RENG_EXECUTE_DSP_END_PTR", 12, 21, &umr_bitfield_default },
+	 { "RENG_EXECUTE_END_PTR", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC[] = {
+	 { "RENG_EXECUTE_NOW_MODE", 10, 10, &umr_bitfield_default },
+	 { "RENG_EXECUTE_ON_REG_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "RENG_SRBM_CREDITS_MCD", 12, 15, &umr_bitfield_default },
+	 { "STCTRL_STUTTER_EN", 16, 16, &umr_bitfield_default },
+	 { "STCTRL_GMC_IDLE_THRESHOLD", 17, 18, &umr_bitfield_default },
+	 { "STCTRL_SRBM_IDLE_THRESHOLD", 19, 20, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PRE_SR", 21, 21, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STOP", 22, 22, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_SR_COMMIT", 23, 23, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PROTECTION_FAULT", 24, 24, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_ALLOW_SR", 25, 25, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_GMC_OFFLINE", 26, 26, &umr_bitfield_default },
+	 { "CRITICAL_REGS_LOCK", 27, 27, &umr_bitfield_default },
+	 { "ALLOW_DEEP_SLEEP_MODE", 28, 30, &umr_bitfield_default },
+	 { "STCTRL_FORCE_ALLOW_SR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC2[] = {
+	 { "RENG_MEM_POWER_CTRL_OVERRIDE0", 0, 2, &umr_bitfield_default },
+	 { "RENG_MEM_POWER_CTRL_OVERRIDE1", 3, 5, &umr_bitfield_default },
+	 { "STCTRL_NONDISP_IDLE_THRESHOLD", 6, 10, &umr_bitfield_default },
+	 { "RENG_SR_HOLD_THRESHOLD", 11, 16, &umr_bitfield_default },
+	 { "STCTRL_LPT_TARGET", 17, 28, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ARB_BUSY", 29, 29, &umr_bitfield_default },
+	 { "STCTRL_EXTEND_GMC_OFFLINE", 30, 30, &umr_bitfield_default },
+	 { "STCTRL_TIMER_PULSE_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE1", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL0[] = {
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL1[] = {
+	 { "THRESH_CNTR_ID", 0, 5, &umr_bitfield_default },
+	 { "START_TRIG_ID", 6, 11, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 12, 17, &umr_bitfield_default },
+	 { "MON0_ID", 18, 23, &umr_bitfield_default },
+	 { "MON1_ID", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE", 12, 12, &umr_bitfield_default },
+	 { "READ", 13, 13, &umr_bitfield_default },
+	 { "RSRVD", 14, 26, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_WRITE[] = {
+	 { "WRITE_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_READ[] = {
+	 { "READ_VALUE", 0, 23, &umr_bitfield_default },
+	 { "PGFSM_SELECT", 24, 27, &umr_bitfield_default },
+	 { "SERDES_MASTER_BUSY", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC3[] = {
+	 { "RENG_DISABLE_MCC", 0, 5, &umr_bitfield_default },
+	 { "RENG_DISABLE_MCD", 6, 11, &umr_bitfield_default },
+	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 12, 23, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STUTTER", 24, 24, &umr_bitfield_default },
+	 { "RENG_MEM_LS_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "STCTRL_EXCLUDE_NONMEM_CLIENTS", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MASK[] = {
+	 { "STCTRL_BUSY_MASK_ACP_RD", 0, 0, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_ACP_WR", 1, 1, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_VCE_RD", 2, 2, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_VCE_WR", 3, 3, &umr_bitfield_default },
+	 { "STCTRL_SR_HANDSHAKE_MASK", 4, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_DEBUG[] = {
+	 { "GFX_STALL", 0, 0, &umr_bitfield_default },
+	 { "GFX_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "MISC_FLAGS", 2, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_EN_RD[] = {
+	 { "TX_PRI", 0, 7, &umr_bitfield_default },
+	 { "BW_PRI", 8, 15, &umr_bitfield_default },
+	 { "FIX_PRI", 16, 23, &umr_bitfield_default },
+	 { "ST_PRI", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_EN_WR[] = {
+	 { "TX_PRI", 0, 7, &umr_bitfield_default },
+	 { "BW_PRI", 8, 15, &umr_bitfield_default },
+	 { "FIX_PRI", 16, 23, &umr_bitfield_default },
+	 { "ST_PRI", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_CTL_RD[] = {
+	 { "FORCE_HIGHEST", 0, 7, &umr_bitfield_default },
+	 { "HARSH_RR", 8, 8, &umr_bitfield_default },
+	 { "BANK_AGE_ONLY", 9, 9, &umr_bitfield_default },
+	 { "USE_LEGACY_HARSH", 10, 10, &umr_bitfield_default },
+	 { "BWCNT_CATCHUP", 11, 11, &umr_bitfield_default },
+	 { "ST_MODE", 12, 13, &umr_bitfield_default },
+	 { "FORCE_STALL", 14, 21, &umr_bitfield_default },
+	 { "PERF_MON_SEL", 22, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_CTL_WR[] = {
+	 { "FORCE_HIGHEST", 0, 7, &umr_bitfield_default },
+	 { "HARSH_RR", 8, 8, &umr_bitfield_default },
+	 { "BANK_AGE_ONLY", 9, 9, &umr_bitfield_default },
+	 { "USE_LEGACY_HARSH", 10, 10, &umr_bitfield_default },
+	 { "BWCNT_CATCHUP", 11, 11, &umr_bitfield_default },
+	 { "ST_MODE", 12, 13, &umr_bitfield_default },
+	 { "FORCE_STALL", 14, 21, &umr_bitfield_default },
+	 { "PERF_MON_SEL", 22, 24, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gmc70_regs.i b/src/lib/ip/gmc70_regs.i
new file mode 100644
index 0000000..bc1753b
--- /dev/null
+++ b/src/lib/ip/gmc70_regs.i
@@ -0,0 +1,629 @@
+	{ "mmVM_L2_CNTL", REG_MMIO, 0x500, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 },
+	{ "mmVM_L2_CNTL2", REG_MMIO, 0x501, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 },
+	{ "mmVM_L2_CNTL3", REG_MMIO, 0x502, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 },
+	{ "mmVM_L2_STATUS", REG_MMIO, 0x503, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x504, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x505, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x506, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_ADDR", REG_MMIO, 0x507, &mmVM_DUMMY_PAGE_FAULT_ADDR[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL2", REG_MMIO, 0x50c, &mmVM_CONTEXT0_CNTL2[0], sizeof(mmVM_CONTEXT0_CNTL2)/sizeof(mmVM_CONTEXT0_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL2", REG_MMIO, 0x50d, &mmVM_CONTEXT1_CNTL2[0], sizeof(mmVM_CONTEXT1_CNTL2)/sizeof(mmVM_CONTEXT1_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50e, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50f, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x510, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x511, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x512, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x513, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x514, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x515, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_REQUEST", REG_MMIO, 0x51e, &mmVM_INVALIDATE_REQUEST[0], sizeof(mmVM_INVALIDATE_REQUEST)/sizeof(mmVM_INVALIDATE_REQUEST[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_RESPONSE", REG_MMIO, 0x51f, &mmVM_INVALIDATE_RESPONSE[0], sizeof(mmVM_INVALIDATE_RESPONSE)/sizeof(mmVM_INVALIDATE_RESPONSE[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_LOW_ADDR", REG_MMIO, 0x52c, &mmVM_PRT_APERTURE0_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE0_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_LOW_ADDR", REG_MMIO, 0x52d, &mmVM_PRT_APERTURE1_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE1_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_LOW_ADDR", REG_MMIO, 0x52e, &mmVM_PRT_APERTURE2_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE2_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE2_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_LOW_ADDR", REG_MMIO, 0x52f, &mmVM_PRT_APERTURE3_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE3_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE3_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_HIGH_ADDR", REG_MMIO, 0x530, &mmVM_PRT_APERTURE0_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_HIGH_ADDR", REG_MMIO, 0x531, &mmVM_PRT_APERTURE1_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_HIGH_ADDR", REG_MMIO, 0x532, &mmVM_PRT_APERTURE2_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_HIGH_ADDR", REG_MMIO, 0x533, &mmVM_PRT_APERTURE3_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_CNTL", REG_MMIO, 0x534, &mmVM_PRT_CNTL[0], sizeof(mmVM_PRT_CNTL)/sizeof(mmVM_PRT_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x535, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_STATUS", REG_MMIO, 0x536, &mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_STATUS", REG_MMIO, 0x537, &mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x538, &mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x539, &mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53e, &mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53f, &mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x546, &mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x547, &mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_FAULT_CLIENT_ID", REG_MMIO, 0x54e, &mmVM_FAULT_CLIENT_ID[0], sizeof(mmVM_FAULT_CLIENT_ID)/sizeof(mmVM_FAULT_CLIENT_ID[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x54f, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x550, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x551, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x552, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x553, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x554, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x555, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x556, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR", REG_MMIO, 0x557, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR", REG_MMIO, 0x558, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR", REG_MMIO, 0x55f, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR", REG_MMIO, 0x560, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "mmVM_DEBUG", REG_MMIO, 0x56f, &mmVM_DEBUG[0], sizeof(mmVM_DEBUG)/sizeof(mmVM_DEBUG[0]), 0, 0 },
+	{ "mmVM_L2_CG", REG_MMIO, 0x570, &mmVM_L2_CG[0], sizeof(mmVM_L2_CG)/sizeof(mmVM_L2_CG[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKA", REG_MMIO, 0x572, &mmVM_L2_BANK_SELECT_MASKA[0], sizeof(mmVM_L2_BANK_SELECT_MASKA)/sizeof(mmVM_L2_BANK_SELECT_MASKA[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKB", REG_MMIO, 0x573, &mmVM_L2_BANK_SELECT_MASKB[0], sizeof(mmVM_L2_BANK_SELECT_MASKB)/sizeof(mmVM_L2_BANK_SELECT_MASKB[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", REG_MMIO, 0x575, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", REG_MMIO, 0x576, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", REG_MMIO, 0x577, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_LO", REG_MMIO, 0x7a0, &mmMC_CITF_PERFCOUNTER_LO[0], sizeof(mmMC_CITF_PERFCOUNTER_LO)/sizeof(mmMC_CITF_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_LO", REG_MMIO, 0x7a1, &mmMC_HUB_PERFCOUNTER_LO[0], sizeof(mmMC_HUB_PERFCOUNTER_LO)/sizeof(mmMC_HUB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_LO", REG_MMIO, 0x7a2, &mmMC_RPB_PERFCOUNTER_LO[0], sizeof(mmMC_RPB_PERFCOUNTER_LO)/sizeof(mmMC_RPB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_LO", REG_MMIO, 0x7a3, &mmMC_MCBVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCBVM_PERFCOUNTER_LO)/sizeof(mmMC_MCBVM_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_LO", REG_MMIO, 0x7a4, &mmMC_MCDVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCDVM_PERFCOUNTER_LO)/sizeof(mmMC_MCDVM_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_LO", REG_MMIO, 0x7a5, &mmMC_VM_L2_PERFCOUNTER_LO[0], sizeof(mmMC_VM_L2_PERFCOUNTER_LO)/sizeof(mmMC_VM_L2_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_LO", REG_MMIO, 0x7a6, &mmMC_ARB_PERFCOUNTER_LO[0], sizeof(mmMC_ARB_PERFCOUNTER_LO)/sizeof(mmMC_ARB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_LO", REG_MMIO, 0x7a7, &mmATC_PERFCOUNTER_LO[0], sizeof(mmATC_PERFCOUNTER_LO)/sizeof(mmATC_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_HI", REG_MMIO, 0x7a8, &mmMC_CITF_PERFCOUNTER_HI[0], sizeof(mmMC_CITF_PERFCOUNTER_HI)/sizeof(mmMC_CITF_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_HI", REG_MMIO, 0x7a9, &mmMC_HUB_PERFCOUNTER_HI[0], sizeof(mmMC_HUB_PERFCOUNTER_HI)/sizeof(mmMC_HUB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_HI", REG_MMIO, 0x7aa, &mmMC_MCBVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCBVM_PERFCOUNTER_HI)/sizeof(mmMC_MCBVM_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_HI", REG_MMIO, 0x7ab, &mmMC_MCDVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCDVM_PERFCOUNTER_HI)/sizeof(mmMC_MCDVM_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_HI", REG_MMIO, 0x7ac, &mmMC_RPB_PERFCOUNTER_HI[0], sizeof(mmMC_RPB_PERFCOUNTER_HI)/sizeof(mmMC_RPB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_HI", REG_MMIO, 0x7ad, &mmMC_VM_L2_PERFCOUNTER_HI[0], sizeof(mmMC_VM_L2_PERFCOUNTER_HI)/sizeof(mmMC_VM_L2_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_HI", REG_MMIO, 0x7ae, &mmMC_ARB_PERFCOUNTER_HI[0], sizeof(mmMC_ARB_PERFCOUNTER_HI)/sizeof(mmMC_ARB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_HI", REG_MMIO, 0x7af, &mmATC_PERFCOUNTER_HI[0], sizeof(mmATC_PERFCOUNTER_HI)/sizeof(mmATC_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER0_CFG", REG_MMIO, 0x7b0, &mmMC_CITF_PERFCOUNTER0_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER0_CFG)/sizeof(mmMC_CITF_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER1_CFG", REG_MMIO, 0x7b1, &mmMC_CITF_PERFCOUNTER1_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER1_CFG)/sizeof(mmMC_CITF_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER2_CFG", REG_MMIO, 0x7b2, &mmMC_CITF_PERFCOUNTER2_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER2_CFG)/sizeof(mmMC_CITF_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER3_CFG", REG_MMIO, 0x7b3, &mmMC_CITF_PERFCOUNTER3_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER3_CFG)/sizeof(mmMC_CITF_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b4, &mmMC_HUB_PERFCOUNTER0_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER0_CFG)/sizeof(mmMC_HUB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b5, &mmMC_HUB_PERFCOUNTER1_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER1_CFG)/sizeof(mmMC_HUB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER2_CFG", REG_MMIO, 0x7b6, &mmMC_HUB_PERFCOUNTER2_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER2_CFG)/sizeof(mmMC_HUB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER3_CFG", REG_MMIO, 0x7b7, &mmMC_HUB_PERFCOUNTER3_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER3_CFG)/sizeof(mmMC_HUB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b8, &mmMC_RPB_PERFCOUNTER0_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER0_CFG)/sizeof(mmMC_RPB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b9, &mmMC_RPB_PERFCOUNTER1_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER1_CFG)/sizeof(mmMC_RPB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER2_CFG", REG_MMIO, 0x7ba, &mmMC_RPB_PERFCOUNTER2_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER2_CFG)/sizeof(mmMC_RPB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bb, &mmMC_RPB_PERFCOUNTER3_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER3_CFG)/sizeof(mmMC_RPB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER0_CFG", REG_MMIO, 0x7bc, &mmMC_ARB_PERFCOUNTER0_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER0_CFG)/sizeof(mmMC_ARB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER1_CFG", REG_MMIO, 0x7bd, &mmMC_ARB_PERFCOUNTER1_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER1_CFG)/sizeof(mmMC_ARB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER2_CFG", REG_MMIO, 0x7be, &mmMC_ARB_PERFCOUNTER2_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER2_CFG)/sizeof(mmMC_ARB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bf, &mmMC_ARB_PERFCOUNTER3_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER3_CFG)/sizeof(mmMC_ARB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c0, &mmMC_MCBVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c1, &mmMC_MCBVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c2, &mmMC_MCBVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c3, &mmMC_MCBVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c4, &mmMC_MCDVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c5, &mmMC_MCDVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c6, &mmMC_MCDVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c7, &mmMC_MCDVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7c8, &mmATC_PERFCOUNTER0_CFG[0], sizeof(mmATC_PERFCOUNTER0_CFG)/sizeof(mmATC_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7c9, &mmATC_PERFCOUNTER1_CFG[0], sizeof(mmATC_PERFCOUNTER1_CFG)/sizeof(mmATC_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER2_CFG", REG_MMIO, 0x7ca, &mmATC_PERFCOUNTER2_CFG[0], sizeof(mmATC_PERFCOUNTER2_CFG)/sizeof(mmATC_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER3_CFG", REG_MMIO, 0x7cb, &mmATC_PERFCOUNTER3_CFG[0], sizeof(mmATC_PERFCOUNTER3_CFG)/sizeof(mmATC_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x7cc, &mmMC_VM_L2_PERFCOUNTER0_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x7cd, &mmMC_VM_L2_PERFCOUNTER1_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7ce, &mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7cf, &mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d0, &mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d1, &mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d2, &mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d3, &mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d4, &mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d5, &mmATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_LO", REG_MMIO, 0x7d6, &mmCHUB_ATC_PERFCOUNTER_LO[0], sizeof(mmCHUB_ATC_PERFCOUNTER_LO)/sizeof(mmCHUB_ATC_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_HI", REG_MMIO, 0x7d7, &mmCHUB_ATC_PERFCOUNTER_HI[0], sizeof(mmCHUB_ATC_PERFCOUNTER_HI)/sizeof(mmCHUB_ATC_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7d8, &mmCHUB_ATC_PERFCOUNTER0_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7d9, &mmCHUB_ATC_PERFCOUNTER1_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7da, &mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_PERF_MON_CNTL0_ECC", REG_MMIO, 0x7db, &mmMC_ARB_PERF_MON_CNTL0_ECC[0], sizeof(mmMC_ARB_PERF_MON_CNTL0_ECC)/sizeof(mmMC_ARB_PERF_MON_CNTL0_ECC[0]), 0, 0 },
+	{ "mmMC_CONFIG", REG_MMIO, 0x800, &mmMC_CONFIG[0], sizeof(mmMC_CONFIG)/sizeof(mmMC_CONFIG[0]), 0, 0 },
+	{ "mmMC_SHARED_CHMAP", REG_MMIO, 0x801, &mmMC_SHARED_CHMAP[0], sizeof(mmMC_SHARED_CHMAP)/sizeof(mmMC_SHARED_CHMAP[0]), 0, 0 },
+	{ "mmMC_SHARED_CHREMAP", REG_MMIO, 0x802, &mmMC_SHARED_CHREMAP[0], sizeof(mmMC_SHARED_CHREMAP)/sizeof(mmMC_SHARED_CHREMAP[0]), 0, 0 },
+	{ "mmMC_RD_GRP_GFX", REG_MMIO, 0x803, &mmMC_RD_GRP_GFX[0], sizeof(mmMC_RD_GRP_GFX)/sizeof(mmMC_RD_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_WR_GRP_GFX", REG_MMIO, 0x804, &mmMC_WR_GRP_GFX[0], sizeof(mmMC_WR_GRP_GFX)/sizeof(mmMC_WR_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_RD_GRP_SYS", REG_MMIO, 0x805, &mmMC_RD_GRP_SYS[0], sizeof(mmMC_RD_GRP_SYS)/sizeof(mmMC_RD_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_WR_GRP_SYS", REG_MMIO, 0x806, &mmMC_WR_GRP_SYS[0], sizeof(mmMC_WR_GRP_SYS)/sizeof(mmMC_WR_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_RD_GRP_OTH", REG_MMIO, 0x807, &mmMC_RD_GRP_OTH[0], sizeof(mmMC_RD_GRP_OTH)/sizeof(mmMC_RD_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_WR_GRP_OTH", REG_MMIO, 0x808, &mmMC_WR_GRP_OTH[0], sizeof(mmMC_WR_GRP_OTH)/sizeof(mmMC_WR_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_VM_FB_LOCATION", REG_MMIO, 0x809, &mmMC_VM_FB_LOCATION[0], sizeof(mmMC_VM_FB_LOCATION)/sizeof(mmMC_VM_FB_LOCATION[0]), 0, 0 },
+	{ "mmMC_VM_AGP_TOP", REG_MMIO, 0x80a, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BOT", REG_MMIO, 0x80b, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BASE", REG_MMIO, 0x80c, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x80d, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x80e, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", REG_MMIO, 0x80f, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_CNTL", REG_MMIO, 0x810, &mmMC_VM_DC_WRITE_CNTL[0], sizeof(mmMC_VM_DC_WRITE_CNTL)/sizeof(mmMC_VM_DC_WRITE_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR", REG_MMIO, 0x811, &mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR", REG_MMIO, 0x812, &mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR", REG_MMIO, 0x813, &mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR", REG_MMIO, 0x814, &mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR", REG_MMIO, 0x815, &mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR", REG_MMIO, 0x816, &mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR", REG_MMIO, 0x817, &mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR", REG_MMIO, 0x818, &mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x819, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_FB_OFFSET", REG_MMIO, 0x81a, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 },
+	{ "mmMC_VM_STEERING", REG_MMIO, 0x81b, &mmMC_VM_STEERING[0], sizeof(mmMC_VM_STEERING)/sizeof(mmMC_VM_STEERING[0]), 0, 0 },
+	{ "mmMC_CONFIG_MCD", REG_MMIO, 0x828, &mmMC_CONFIG_MCD[0], sizeof(mmMC_CONFIG_MCD)/sizeof(mmMC_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG_MCD", REG_MMIO, 0x829, &mmMC_CG_CONFIG_MCD[0], sizeof(mmMC_CG_CONFIG_MCD)/sizeof(mmMC_CG_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_MEM_POWER_LS", REG_MMIO, 0x82a, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 },
+	{ "mmMC_SHARED_BLACKOUT_CNTL", REG_MMIO, 0x82b, &mmMC_SHARED_BLACKOUT_CNTL[0], sizeof(mmMC_SHARED_BLACKOUT_CNTL)/sizeof(mmMC_SHARED_BLACKOUT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_POWER", REG_MMIO, 0x82d, &mmMC_HUB_MISC_POWER[0], sizeof(mmMC_HUB_MISC_POWER)/sizeof(mmMC_HUB_MISC_POWER[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_HUB_CG", REG_MMIO, 0x82e, &mmMC_HUB_MISC_HUB_CG[0], sizeof(mmMC_HUB_MISC_HUB_CG)/sizeof(mmMC_HUB_MISC_HUB_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_VM_CG", REG_MMIO, 0x82f, &mmMC_HUB_MISC_VM_CG[0], sizeof(mmMC_HUB_MISC_VM_CG)/sizeof(mmMC_HUB_MISC_VM_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_SIP_CG", REG_MMIO, 0x830, &mmMC_HUB_MISC_SIP_CG[0], sizeof(mmMC_HUB_MISC_SIP_CG)/sizeof(mmMC_HUB_MISC_SIP_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_DBG", REG_MMIO, 0x831, &mmMC_HUB_MISC_DBG[0], sizeof(mmMC_HUB_MISC_DBG)/sizeof(mmMC_HUB_MISC_DBG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_STATUS", REG_MMIO, 0x832, &mmMC_HUB_MISC_STATUS[0], sizeof(mmMC_HUB_MISC_STATUS)/sizeof(mmMC_HUB_MISC_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_OVERRIDE", REG_MMIO, 0x833, &mmMC_HUB_MISC_OVERRIDE[0], sizeof(mmMC_HUB_MISC_OVERRIDE)/sizeof(mmMC_HUB_MISC_OVERRIDE[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_FRAMING", REG_MMIO, 0x834, &mmMC_HUB_MISC_FRAMING[0], sizeof(mmMC_HUB_MISC_FRAMING)/sizeof(mmMC_HUB_MISC_FRAMING[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CNTL", REG_MMIO, 0x835, &mmMC_HUB_WDP_CNTL[0], sizeof(mmMC_HUB_WDP_CNTL)/sizeof(mmMC_HUB_WDP_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ERR", REG_MMIO, 0x836, &mmMC_HUB_WDP_ERR[0], sizeof(mmMC_HUB_WDP_ERR)/sizeof(mmMC_HUB_WDP_ERR[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BP", REG_MMIO, 0x837, &mmMC_HUB_WDP_BP[0], sizeof(mmMC_HUB_WDP_BP)/sizeof(mmMC_HUB_WDP_BP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_STATUS", REG_MMIO, 0x838, &mmMC_HUB_WDP_STATUS[0], sizeof(mmMC_HUB_WDP_STATUS)/sizeof(mmMC_HUB_WDP_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_STATUS", REG_MMIO, 0x839, &mmMC_HUB_RDREQ_STATUS[0], sizeof(mmMC_HUB_RDREQ_STATUS)/sizeof(mmMC_HUB_RDREQ_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_STATUS", REG_MMIO, 0x83a, &mmMC_HUB_WRRET_STATUS[0], sizeof(mmMC_HUB_WRRET_STATUS)/sizeof(mmMC_HUB_WRRET_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CNTL", REG_MMIO, 0x83b, &mmMC_HUB_RDREQ_CNTL[0], sizeof(mmMC_HUB_RDREQ_CNTL)/sizeof(mmMC_HUB_RDREQ_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_CNTL", REG_MMIO, 0x83c, &mmMC_HUB_WRRET_CNTL[0], sizeof(mmMC_HUB_WRRET_CNTL)/sizeof(mmMC_HUB_WRRET_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_WTM_CNTL", REG_MMIO, 0x83d, &mmMC_HUB_RDREQ_WTM_CNTL[0], sizeof(mmMC_HUB_RDREQ_WTM_CNTL)/sizeof(mmMC_HUB_RDREQ_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_WTM_CNTL", REG_MMIO, 0x83e, &mmMC_HUB_WDP_WTM_CNTL[0], sizeof(mmMC_HUB_WDP_WTM_CNTL)/sizeof(mmMC_HUB_WDP_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS", REG_MMIO, 0x83f, &mmMC_HUB_WDP_CREDITS[0], sizeof(mmMC_HUB_WDP_CREDITS)/sizeof(mmMC_HUB_WDP_CREDITS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MGPU2", REG_MMIO, 0x840, &mmMC_HUB_WDP_MGPU2[0], sizeof(mmMC_HUB_WDP_MGPU2)/sizeof(mmMC_HUB_WDP_MGPU2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL0", REG_MMIO, 0x841, &mmMC_HUB_WDP_GBL0[0], sizeof(mmMC_HUB_WDP_GBL0)/sizeof(mmMC_HUB_WDP_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL1", REG_MMIO, 0x842, &mmMC_HUB_WDP_GBL1[0], sizeof(mmMC_HUB_WDP_GBL1)/sizeof(mmMC_HUB_WDP_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MGPU", REG_MMIO, 0x843, &mmMC_HUB_WDP_MGPU[0], sizeof(mmMC_HUB_WDP_MGPU)/sizeof(mmMC_HUB_WDP_MGPU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS", REG_MMIO, 0x844, &mmMC_HUB_RDREQ_CREDITS[0], sizeof(mmMC_HUB_RDREQ_CREDITS)/sizeof(mmMC_HUB_RDREQ_CREDITS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS2", REG_MMIO, 0x845, &mmMC_HUB_RDREQ_CREDITS2[0], sizeof(mmMC_HUB_RDREQ_CREDITS2)/sizeof(mmMC_HUB_RDREQ_CREDITS2[0]), 0, 0 },
+	{ "mmMC_HUB_SHARED_DAGB_DLY", REG_MMIO, 0x846, &mmMC_HUB_SHARED_DAGB_DLY[0], sizeof(mmMC_HUB_SHARED_DAGB_DLY)/sizeof(mmMC_HUB_SHARED_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_IDLE_STATUS", REG_MMIO, 0x847, &mmMC_HUB_MISC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_IDLE_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF_LIMIT", REG_MMIO, 0x848, &mmMC_HUB_RDREQ_DMIF_LIMIT[0], sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT)/sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPG_LIMIT", REG_MMIO, 0x849, &mmMC_HUB_RDREQ_ACPG_LIMIT[0], sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT)/sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH2", REG_MMIO, 0x84d, &mmMC_HUB_WDP_SH2[0], sizeof(mmMC_HUB_WDP_SH2)/sizeof(mmMC_HUB_WDP_SH2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH3", REG_MMIO, 0x84e, &mmMC_HUB_WDP_SH3[0], sizeof(mmMC_HUB_WDP_SH3)/sizeof(mmMC_HUB_WDP_SH3[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_IA0", REG_MMIO, 0x84f, &mmMC_HUB_RDREQ_IA0[0], sizeof(mmMC_HUB_RDREQ_IA0)/sizeof(mmMC_HUB_RDREQ_IA0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_IA1", REG_MMIO, 0x850, &mmMC_HUB_RDREQ_IA1[0], sizeof(mmMC_HUB_RDREQ_IA1)/sizeof(mmMC_HUB_RDREQ_IA1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDW", REG_MMIO, 0x851, &mmMC_HUB_RDREQ_MCDW[0], sizeof(mmMC_HUB_RDREQ_MCDW)/sizeof(mmMC_HUB_RDREQ_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDX", REG_MMIO, 0x852, &mmMC_HUB_RDREQ_MCDX[0], sizeof(mmMC_HUB_RDREQ_MCDX)/sizeof(mmMC_HUB_RDREQ_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDY", REG_MMIO, 0x853, &mmMC_HUB_RDREQ_MCDY[0], sizeof(mmMC_HUB_RDREQ_MCDY)/sizeof(mmMC_HUB_RDREQ_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDZ", REG_MMIO, 0x854, &mmMC_HUB_RDREQ_MCDZ[0], sizeof(mmMC_HUB_RDREQ_MCDZ)/sizeof(mmMC_HUB_RDREQ_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SIP", REG_MMIO, 0x855, &mmMC_HUB_RDREQ_SIP[0], sizeof(mmMC_HUB_RDREQ_SIP)/sizeof(mmMC_HUB_RDREQ_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL0", REG_MMIO, 0x856, &mmMC_HUB_RDREQ_GBL0[0], sizeof(mmMC_HUB_RDREQ_GBL0)/sizeof(mmMC_HUB_RDREQ_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL1", REG_MMIO, 0x857, &mmMC_HUB_RDREQ_GBL1[0], sizeof(mmMC_HUB_RDREQ_GBL1)/sizeof(mmMC_HUB_RDREQ_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SMU", REG_MMIO, 0x858, &mmMC_HUB_RDREQ_SMU[0], sizeof(mmMC_HUB_RDREQ_SMU)/sizeof(mmMC_HUB_RDREQ_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CPG", REG_MMIO, 0x859, &mmMC_HUB_RDREQ_CPG[0], sizeof(mmMC_HUB_RDREQ_CPG)/sizeof(mmMC_HUB_RDREQ_CPG[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SDMA0", REG_MMIO, 0x85a, &mmMC_HUB_RDREQ_SDMA0[0], sizeof(mmMC_HUB_RDREQ_SDMA0)/sizeof(mmMC_HUB_RDREQ_SDMA0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_HDP", REG_MMIO, 0x85b, &mmMC_HUB_RDREQ_HDP[0], sizeof(mmMC_HUB_RDREQ_HDP)/sizeof(mmMC_HUB_RDREQ_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SDMA1", REG_MMIO, 0x85c, &mmMC_HUB_RDREQ_SDMA1[0], sizeof(mmMC_HUB_RDREQ_SDMA1)/sizeof(mmMC_HUB_RDREQ_SDMA1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_RLC", REG_MMIO, 0x85d, &mmMC_HUB_RDREQ_RLC[0], sizeof(mmMC_HUB_RDREQ_RLC)/sizeof(mmMC_HUB_RDREQ_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SEM", REG_MMIO, 0x85e, &mmMC_HUB_RDREQ_SEM[0], sizeof(mmMC_HUB_RDREQ_SEM)/sizeof(mmMC_HUB_RDREQ_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCE", REG_MMIO, 0x85f, &mmMC_HUB_RDREQ_VCE[0], sizeof(mmMC_HUB_RDREQ_VCE)/sizeof(mmMC_HUB_RDREQ_VCE[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UMC", REG_MMIO, 0x860, &mmMC_HUB_RDREQ_UMC[0], sizeof(mmMC_HUB_RDREQ_UMC)/sizeof(mmMC_HUB_RDREQ_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UVD", REG_MMIO, 0x861, &mmMC_HUB_RDREQ_UVD[0], sizeof(mmMC_HUB_RDREQ_UVD)/sizeof(mmMC_HUB_RDREQ_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_IA", REG_MMIO, 0x862, &mmMC_HUB_RDREQ_IA[0], sizeof(mmMC_HUB_RDREQ_IA)/sizeof(mmMC_HUB_RDREQ_IA[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF", REG_MMIO, 0x863, &mmMC_HUB_RDREQ_DMIF[0], sizeof(mmMC_HUB_RDREQ_DMIF)/sizeof(mmMC_HUB_RDREQ_DMIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCIF", REG_MMIO, 0x864, &mmMC_HUB_RDREQ_MCIF[0], sizeof(mmMC_HUB_RDREQ_MCIF)/sizeof(mmMC_HUB_RDREQ_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VMC", REG_MMIO, 0x865, &mmMC_HUB_RDREQ_VMC[0], sizeof(mmMC_HUB_RDREQ_VMC)/sizeof(mmMC_HUB_RDREQ_VMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCEU", REG_MMIO, 0x866, &mmMC_HUB_RDREQ_VCEU[0], sizeof(mmMC_HUB_RDREQ_VCEU)/sizeof(mmMC_HUB_RDREQ_VCEU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDW", REG_MMIO, 0x867, &mmMC_HUB_WDP_MCDW[0], sizeof(mmMC_HUB_WDP_MCDW)/sizeof(mmMC_HUB_WDP_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDX", REG_MMIO, 0x868, &mmMC_HUB_WDP_MCDX[0], sizeof(mmMC_HUB_WDP_MCDX)/sizeof(mmMC_HUB_WDP_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDY", REG_MMIO, 0x869, &mmMC_HUB_WDP_MCDY[0], sizeof(mmMC_HUB_WDP_MCDY)/sizeof(mmMC_HUB_WDP_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDZ", REG_MMIO, 0x86a, &mmMC_HUB_WDP_MCDZ[0], sizeof(mmMC_HUB_WDP_MCDZ)/sizeof(mmMC_HUB_WDP_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SIP", REG_MMIO, 0x86b, &mmMC_HUB_WDP_SIP[0], sizeof(mmMC_HUB_WDP_SIP)/sizeof(mmMC_HUB_WDP_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CPG", REG_MMIO, 0x86c, &mmMC_HUB_WDP_CPG[0], sizeof(mmMC_HUB_WDP_CPG)/sizeof(mmMC_HUB_WDP_CPG[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SDMA1", REG_MMIO, 0x86d, &mmMC_HUB_WDP_SDMA1[0], sizeof(mmMC_HUB_WDP_SDMA1)/sizeof(mmMC_HUB_WDP_SDMA1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH0", REG_MMIO, 0x86e, &mmMC_HUB_WDP_SH0[0], sizeof(mmMC_HUB_WDP_SH0)/sizeof(mmMC_HUB_WDP_SH0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCIF", REG_MMIO, 0x86f, &mmMC_HUB_WDP_MCIF[0], sizeof(mmMC_HUB_WDP_MCIF)/sizeof(mmMC_HUB_WDP_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCE", REG_MMIO, 0x870, &mmMC_HUB_WDP_VCE[0], sizeof(mmMC_HUB_WDP_VCE)/sizeof(mmMC_HUB_WDP_VCE[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDP", REG_MMIO, 0x871, &mmMC_HUB_WDP_XDP[0], sizeof(mmMC_HUB_WDP_XDP)/sizeof(mmMC_HUB_WDP_XDP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_IH", REG_MMIO, 0x872, &mmMC_HUB_WDP_IH[0], sizeof(mmMC_HUB_WDP_IH)/sizeof(mmMC_HUB_WDP_IH[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_RLC", REG_MMIO, 0x873, &mmMC_HUB_WDP_RLC[0], sizeof(mmMC_HUB_WDP_RLC)/sizeof(mmMC_HUB_WDP_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SEM", REG_MMIO, 0x874, &mmMC_HUB_WDP_SEM[0], sizeof(mmMC_HUB_WDP_SEM)/sizeof(mmMC_HUB_WDP_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SMU", REG_MMIO, 0x875, &mmMC_HUB_WDP_SMU[0], sizeof(mmMC_HUB_WDP_SMU)/sizeof(mmMC_HUB_WDP_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH1", REG_MMIO, 0x876, &mmMC_HUB_WDP_SH1[0], sizeof(mmMC_HUB_WDP_SH1)/sizeof(mmMC_HUB_WDP_SH1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UMC", REG_MMIO, 0x877, &mmMC_HUB_WDP_UMC[0], sizeof(mmMC_HUB_WDP_UMC)/sizeof(mmMC_HUB_WDP_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UVD", REG_MMIO, 0x878, &mmMC_HUB_WDP_UVD[0], sizeof(mmMC_HUB_WDP_UVD)/sizeof(mmMC_HUB_WDP_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_HDP", REG_MMIO, 0x879, &mmMC_HUB_WDP_HDP[0], sizeof(mmMC_HUB_WDP_HDP)/sizeof(mmMC_HUB_WDP_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SDMA0", REG_MMIO, 0x87a, &mmMC_HUB_WDP_SDMA0[0], sizeof(mmMC_HUB_WDP_SDMA0)/sizeof(mmMC_HUB_WDP_SDMA0[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDW", REG_MMIO, 0x87b, &mmMC_HUB_WRRET_MCDW[0], sizeof(mmMC_HUB_WRRET_MCDW)/sizeof(mmMC_HUB_WRRET_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDX", REG_MMIO, 0x87c, &mmMC_HUB_WRRET_MCDX[0], sizeof(mmMC_HUB_WRRET_MCDX)/sizeof(mmMC_HUB_WRRET_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDY", REG_MMIO, 0x87d, &mmMC_HUB_WRRET_MCDY[0], sizeof(mmMC_HUB_WRRET_MCDY)/sizeof(mmMC_HUB_WRRET_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDZ", REG_MMIO, 0x87e, &mmMC_HUB_WRRET_MCDZ[0], sizeof(mmMC_HUB_WRRET_MCDZ)/sizeof(mmMC_HUB_WRRET_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCEU", REG_MMIO, 0x87f, &mmMC_HUB_WDP_VCEU[0], sizeof(mmMC_HUB_WDP_VCEU)/sizeof(mmMC_HUB_WDP_VCEU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMAM", REG_MMIO, 0x880, &mmMC_HUB_WDP_XDMAM[0], sizeof(mmMC_HUB_WDP_XDMAM)/sizeof(mmMC_HUB_WDP_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMA", REG_MMIO, 0x881, &mmMC_HUB_WDP_XDMA[0], sizeof(mmMC_HUB_WDP_XDMA)/sizeof(mmMC_HUB_WDP_XDMA[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_XDMAM", REG_MMIO, 0x882, &mmMC_HUB_RDREQ_XDMAM[0], sizeof(mmMC_HUB_RDREQ_XDMAM)/sizeof(mmMC_HUB_RDREQ_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPG", REG_MMIO, 0x883, &mmMC_HUB_RDREQ_ACPG[0], sizeof(mmMC_HUB_RDREQ_ACPG)/sizeof(mmMC_HUB_RDREQ_ACPG[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPO", REG_MMIO, 0x884, &mmMC_HUB_RDREQ_ACPO[0], sizeof(mmMC_HUB_RDREQ_ACPO)/sizeof(mmMC_HUB_RDREQ_ACPO[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SAM", REG_MMIO, 0x885, &mmMC_HUB_RDREQ_SAM[0], sizeof(mmMC_HUB_RDREQ_SAM)/sizeof(mmMC_HUB_RDREQ_SAM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ACPG", REG_MMIO, 0x886, &mmMC_HUB_WDP_ACPG[0], sizeof(mmMC_HUB_WDP_ACPG)/sizeof(mmMC_HUB_WDP_ACPG[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ACPO", REG_MMIO, 0x887, &mmMC_HUB_WDP_ACPO[0], sizeof(mmMC_HUB_WDP_ACPO)/sizeof(mmMC_HUB_WDP_ACPO[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SAM", REG_MMIO, 0x888, &mmMC_HUB_WDP_SAM[0], sizeof(mmMC_HUB_WDP_SAM)/sizeof(mmMC_HUB_WDP_SAM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CPC", REG_MMIO, 0x889, &mmMC_HUB_RDREQ_CPC[0], sizeof(mmMC_HUB_RDREQ_CPC)/sizeof(mmMC_HUB_RDREQ_CPC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CPF", REG_MMIO, 0x88a, &mmMC_HUB_RDREQ_CPF[0], sizeof(mmMC_HUB_RDREQ_CPF)/sizeof(mmMC_HUB_RDREQ_CPF[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CPC", REG_MMIO, 0x88b, &mmMC_HUB_WDP_CPC[0], sizeof(mmMC_HUB_WDP_CPC)/sizeof(mmMC_HUB_WDP_CPC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CPF", REG_MMIO, 0x88c, &mmMC_HUB_WDP_CPF[0], sizeof(mmMC_HUB_WDP_CPF)/sizeof(mmMC_HUB_WDP_CPF[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_DEBUG", REG_MMIO, 0x891, &mmMC_VM_MB_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_DEBUG", REG_MMIO, 0x893, &mmMC_VM_MB_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_STATUS", REG_MMIO, 0x895, &mmMC_VM_MB_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB0_STATUS)/sizeof(mmMC_VM_MB_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB1_STATUS", REG_MMIO, 0x896, &mmMC_VM_MB_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB1_STATUS)/sizeof(mmMC_VM_MB_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_STATUS", REG_MMIO, 0x897, &mmMC_VM_MB_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB2_STATUS)/sizeof(mmMC_VM_MB_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L2ARBITER_L2_CREDITS", REG_MMIO, 0x8a1, &mmMC_VM_MB_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_DEBUG", REG_MMIO, 0x8a5, &mmMC_VM_MB_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_STATUS", REG_MMIO, 0x8a6, &mmMC_VM_MB_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB3_STATUS)/sizeof(mmMC_VM_MB_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "mmCHUB_ATC_L1_DEBUG_TLB", REG_MMIO, 0x8c00, &mmCHUB_ATC_L1_DEBUG_TLB[0], sizeof(mmCHUB_ATC_L1_DEBUG_TLB)/sizeof(mmCHUB_ATC_L1_DEBUG_TLB[0]), 0, 0 },
+	{ "mmCHUB_ATC_L1_STATUS", REG_MMIO, 0x8c01, &mmCHUB_ATC_L1_STATUS[0], sizeof(mmCHUB_ATC_L1_STATUS)/sizeof(mmCHUB_ATC_L1_STATUS[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR0", REG_MMIO, 0x8cd, &mmMC_XPB_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR1", REG_MMIO, 0x8ce, &mmMC_XPB_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR2", REG_MMIO, 0x8cf, &mmMC_XPB_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR3", REG_MMIO, 0x8d0, &mmMC_XPB_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR4", REG_MMIO, 0x8d1, &mmMC_XPB_RTR_SRC_APRTR4[0], sizeof(mmMC_XPB_RTR_SRC_APRTR4)/sizeof(mmMC_XPB_RTR_SRC_APRTR4[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR5", REG_MMIO, 0x8d2, &mmMC_XPB_RTR_SRC_APRTR5[0], sizeof(mmMC_XPB_RTR_SRC_APRTR5)/sizeof(mmMC_XPB_RTR_SRC_APRTR5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR6", REG_MMIO, 0x8d3, &mmMC_XPB_RTR_SRC_APRTR6[0], sizeof(mmMC_XPB_RTR_SRC_APRTR6)/sizeof(mmMC_XPB_RTR_SRC_APRTR6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR7", REG_MMIO, 0x8d4, &mmMC_XPB_RTR_SRC_APRTR7[0], sizeof(mmMC_XPB_RTR_SRC_APRTR7)/sizeof(mmMC_XPB_RTR_SRC_APRTR7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR8", REG_MMIO, 0x8d5, &mmMC_XPB_RTR_SRC_APRTR8[0], sizeof(mmMC_XPB_RTR_SRC_APRTR8)/sizeof(mmMC_XPB_RTR_SRC_APRTR8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR9", REG_MMIO, 0x8d6, &mmMC_XPB_RTR_SRC_APRTR9[0], sizeof(mmMC_XPB_RTR_SRC_APRTR9)/sizeof(mmMC_XPB_RTR_SRC_APRTR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR0", REG_MMIO, 0x8d7, &mmMC_XPB_XDMA_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR1", REG_MMIO, 0x8d8, &mmMC_XPB_XDMA_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR2", REG_MMIO, 0x8d9, &mmMC_XPB_XDMA_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR3", REG_MMIO, 0x8da, &mmMC_XPB_XDMA_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP0", REG_MMIO, 0x8db, &mmMC_XPB_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_RTR_DEST_MAP0)/sizeof(mmMC_XPB_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP1", REG_MMIO, 0x8dc, &mmMC_XPB_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_RTR_DEST_MAP1)/sizeof(mmMC_XPB_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP2", REG_MMIO, 0x8dd, &mmMC_XPB_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_RTR_DEST_MAP2)/sizeof(mmMC_XPB_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP3", REG_MMIO, 0x8de, &mmMC_XPB_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_RTR_DEST_MAP3)/sizeof(mmMC_XPB_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP4", REG_MMIO, 0x8df, &mmMC_XPB_RTR_DEST_MAP4[0], sizeof(mmMC_XPB_RTR_DEST_MAP4)/sizeof(mmMC_XPB_RTR_DEST_MAP4[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP5", REG_MMIO, 0x8e0, &mmMC_XPB_RTR_DEST_MAP5[0], sizeof(mmMC_XPB_RTR_DEST_MAP5)/sizeof(mmMC_XPB_RTR_DEST_MAP5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP6", REG_MMIO, 0x8e1, &mmMC_XPB_RTR_DEST_MAP6[0], sizeof(mmMC_XPB_RTR_DEST_MAP6)/sizeof(mmMC_XPB_RTR_DEST_MAP6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP7", REG_MMIO, 0x8e2, &mmMC_XPB_RTR_DEST_MAP7[0], sizeof(mmMC_XPB_RTR_DEST_MAP7)/sizeof(mmMC_XPB_RTR_DEST_MAP7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP8", REG_MMIO, 0x8e3, &mmMC_XPB_RTR_DEST_MAP8[0], sizeof(mmMC_XPB_RTR_DEST_MAP8)/sizeof(mmMC_XPB_RTR_DEST_MAP8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP9", REG_MMIO, 0x8e4, &mmMC_XPB_RTR_DEST_MAP9[0], sizeof(mmMC_XPB_RTR_DEST_MAP9)/sizeof(mmMC_XPB_RTR_DEST_MAP9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP0", REG_MMIO, 0x8e5, &mmMC_XPB_XDMA_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP1", REG_MMIO, 0x8e6, &mmMC_XPB_XDMA_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP2", REG_MMIO, 0x8e7, &mmMC_XPB_XDMA_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP3", REG_MMIO, 0x8e8, &mmMC_XPB_XDMA_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG0", REG_MMIO, 0x8e9, &mmMC_XPB_CLG_CFG0[0], sizeof(mmMC_XPB_CLG_CFG0)/sizeof(mmMC_XPB_CLG_CFG0[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG1", REG_MMIO, 0x8ea, &mmMC_XPB_CLG_CFG1[0], sizeof(mmMC_XPB_CLG_CFG1)/sizeof(mmMC_XPB_CLG_CFG1[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG2", REG_MMIO, 0x8eb, &mmMC_XPB_CLG_CFG2[0], sizeof(mmMC_XPB_CLG_CFG2)/sizeof(mmMC_XPB_CLG_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG3", REG_MMIO, 0x8ec, &mmMC_XPB_CLG_CFG3[0], sizeof(mmMC_XPB_CLG_CFG3)/sizeof(mmMC_XPB_CLG_CFG3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG4", REG_MMIO, 0x8ed, &mmMC_XPB_CLG_CFG4[0], sizeof(mmMC_XPB_CLG_CFG4)/sizeof(mmMC_XPB_CLG_CFG4[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG5", REG_MMIO, 0x8ee, &mmMC_XPB_CLG_CFG5[0], sizeof(mmMC_XPB_CLG_CFG5)/sizeof(mmMC_XPB_CLG_CFG5[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG6", REG_MMIO, 0x8ef, &mmMC_XPB_CLG_CFG6[0], sizeof(mmMC_XPB_CLG_CFG6)/sizeof(mmMC_XPB_CLG_CFG6[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG7", REG_MMIO, 0x8f0, &mmMC_XPB_CLG_CFG7[0], sizeof(mmMC_XPB_CLG_CFG7)/sizeof(mmMC_XPB_CLG_CFG7[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG8", REG_MMIO, 0x8f1, &mmMC_XPB_CLG_CFG8[0], sizeof(mmMC_XPB_CLG_CFG8)/sizeof(mmMC_XPB_CLG_CFG8[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG9", REG_MMIO, 0x8f2, &mmMC_XPB_CLG_CFG9[0], sizeof(mmMC_XPB_CLG_CFG9)/sizeof(mmMC_XPB_CLG_CFG9[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG10", REG_MMIO, 0x8f3, &mmMC_XPB_CLG_CFG10[0], sizeof(mmMC_XPB_CLG_CFG10)/sizeof(mmMC_XPB_CLG_CFG10[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG11", REG_MMIO, 0x8f4, &mmMC_XPB_CLG_CFG11[0], sizeof(mmMC_XPB_CLG_CFG11)/sizeof(mmMC_XPB_CLG_CFG11[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG12", REG_MMIO, 0x8f5, &mmMC_XPB_CLG_CFG12[0], sizeof(mmMC_XPB_CLG_CFG12)/sizeof(mmMC_XPB_CLG_CFG12[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG13", REG_MMIO, 0x8f6, &mmMC_XPB_CLG_CFG13[0], sizeof(mmMC_XPB_CLG_CFG13)/sizeof(mmMC_XPB_CLG_CFG13[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG14", REG_MMIO, 0x8f7, &mmMC_XPB_CLG_CFG14[0], sizeof(mmMC_XPB_CLG_CFG14)/sizeof(mmMC_XPB_CLG_CFG14[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG15", REG_MMIO, 0x8f8, &mmMC_XPB_CLG_CFG15[0], sizeof(mmMC_XPB_CLG_CFG15)/sizeof(mmMC_XPB_CLG_CFG15[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG16", REG_MMIO, 0x8f9, &mmMC_XPB_CLG_CFG16[0], sizeof(mmMC_XPB_CLG_CFG16)/sizeof(mmMC_XPB_CLG_CFG16[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG17", REG_MMIO, 0x8fa, &mmMC_XPB_CLG_CFG17[0], sizeof(mmMC_XPB_CLG_CFG17)/sizeof(mmMC_XPB_CLG_CFG17[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG18", REG_MMIO, 0x8fb, &mmMC_XPB_CLG_CFG18[0], sizeof(mmMC_XPB_CLG_CFG18)/sizeof(mmMC_XPB_CLG_CFG18[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG19", REG_MMIO, 0x8fc, &mmMC_XPB_CLG_CFG19[0], sizeof(mmMC_XPB_CLG_CFG19)/sizeof(mmMC_XPB_CLG_CFG19[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA", REG_MMIO, 0x8fd, &mmMC_XPB_CLG_EXTRA[0], sizeof(mmMC_XPB_CLG_EXTRA)/sizeof(mmMC_XPB_CLG_EXTRA[0]), 0, 0 },
+	{ "mmMC_XPB_LB_ADDR", REG_MMIO, 0x8fe, &mmMC_XPB_LB_ADDR[0], sizeof(mmMC_XPB_LB_ADDR)/sizeof(mmMC_XPB_LB_ADDR[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_HST", REG_MMIO, 0x8ff, &mmMC_XPB_UNC_THRESH_HST[0], sizeof(mmMC_XPB_UNC_THRESH_HST)/sizeof(mmMC_XPB_UNC_THRESH_HST[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_SID", REG_MMIO, 0x900, &mmMC_XPB_UNC_THRESH_SID[0], sizeof(mmMC_XPB_UNC_THRESH_SID)/sizeof(mmMC_XPB_UNC_THRESH_SID[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_STS", REG_MMIO, 0x901, &mmMC_XPB_WCB_STS[0], sizeof(mmMC_XPB_WCB_STS)/sizeof(mmMC_XPB_WCB_STS[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_CFG", REG_MMIO, 0x902, &mmMC_XPB_WCB_CFG[0], sizeof(mmMC_XPB_WCB_CFG)/sizeof(mmMC_XPB_WCB_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_CFG", REG_MMIO, 0x903, &mmMC_XPB_P2P_BAR_CFG[0], sizeof(mmMC_XPB_P2P_BAR_CFG)/sizeof(mmMC_XPB_P2P_BAR_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR0", REG_MMIO, 0x904, &mmMC_XPB_P2P_BAR0[0], sizeof(mmMC_XPB_P2P_BAR0)/sizeof(mmMC_XPB_P2P_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR1", REG_MMIO, 0x905, &mmMC_XPB_P2P_BAR1[0], sizeof(mmMC_XPB_P2P_BAR1)/sizeof(mmMC_XPB_P2P_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR2", REG_MMIO, 0x906, &mmMC_XPB_P2P_BAR2[0], sizeof(mmMC_XPB_P2P_BAR2)/sizeof(mmMC_XPB_P2P_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR3", REG_MMIO, 0x907, &mmMC_XPB_P2P_BAR3[0], sizeof(mmMC_XPB_P2P_BAR3)/sizeof(mmMC_XPB_P2P_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR4", REG_MMIO, 0x908, &mmMC_XPB_P2P_BAR4[0], sizeof(mmMC_XPB_P2P_BAR4)/sizeof(mmMC_XPB_P2P_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR5", REG_MMIO, 0x909, &mmMC_XPB_P2P_BAR5[0], sizeof(mmMC_XPB_P2P_BAR5)/sizeof(mmMC_XPB_P2P_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR6", REG_MMIO, 0x90a, &mmMC_XPB_P2P_BAR6[0], sizeof(mmMC_XPB_P2P_BAR6)/sizeof(mmMC_XPB_P2P_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR7", REG_MMIO, 0x90b, &mmMC_XPB_P2P_BAR7[0], sizeof(mmMC_XPB_P2P_BAR7)/sizeof(mmMC_XPB_P2P_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_SETUP", REG_MMIO, 0x90c, &mmMC_XPB_P2P_BAR_SETUP[0], sizeof(mmMC_XPB_P2P_BAR_SETUP)/sizeof(mmMC_XPB_P2P_BAR_SETUP[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DEBUG", REG_MMIO, 0x90d, &mmMC_XPB_P2P_BAR_DEBUG[0], sizeof(mmMC_XPB_P2P_BAR_DEBUG)/sizeof(mmMC_XPB_P2P_BAR_DEBUG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_ABOVE", REG_MMIO, 0x90e, &mmMC_XPB_P2P_BAR_DELTA_ABOVE[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE)/sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_BELOW", REG_MMIO, 0x90f, &mmMC_XPB_P2P_BAR_DELTA_BELOW[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW)/sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR0", REG_MMIO, 0x910, &mmMC_XPB_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_PEER_SYS_BAR0)/sizeof(mmMC_XPB_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR1", REG_MMIO, 0x911, &mmMC_XPB_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_PEER_SYS_BAR1)/sizeof(mmMC_XPB_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR2", REG_MMIO, 0x912, &mmMC_XPB_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_PEER_SYS_BAR2)/sizeof(mmMC_XPB_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR3", REG_MMIO, 0x913, &mmMC_XPB_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_PEER_SYS_BAR3)/sizeof(mmMC_XPB_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR4", REG_MMIO, 0x914, &mmMC_XPB_PEER_SYS_BAR4[0], sizeof(mmMC_XPB_PEER_SYS_BAR4)/sizeof(mmMC_XPB_PEER_SYS_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR5", REG_MMIO, 0x915, &mmMC_XPB_PEER_SYS_BAR5[0], sizeof(mmMC_XPB_PEER_SYS_BAR5)/sizeof(mmMC_XPB_PEER_SYS_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR6", REG_MMIO, 0x916, &mmMC_XPB_PEER_SYS_BAR6[0], sizeof(mmMC_XPB_PEER_SYS_BAR6)/sizeof(mmMC_XPB_PEER_SYS_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR7", REG_MMIO, 0x917, &mmMC_XPB_PEER_SYS_BAR7[0], sizeof(mmMC_XPB_PEER_SYS_BAR7)/sizeof(mmMC_XPB_PEER_SYS_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR8", REG_MMIO, 0x918, &mmMC_XPB_PEER_SYS_BAR8[0], sizeof(mmMC_XPB_PEER_SYS_BAR8)/sizeof(mmMC_XPB_PEER_SYS_BAR8[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR9", REG_MMIO, 0x919, &mmMC_XPB_PEER_SYS_BAR9[0], sizeof(mmMC_XPB_PEER_SYS_BAR9)/sizeof(mmMC_XPB_PEER_SYS_BAR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR0", REG_MMIO, 0x91a, &mmMC_XPB_XDMA_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR1", REG_MMIO, 0x91b, &mmMC_XPB_XDMA_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR2", REG_MMIO, 0x91c, &mmMC_XPB_XDMA_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR3", REG_MMIO, 0x91d, &mmMC_XPB_XDMA_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_CLK_GAT", REG_MMIO, 0x91e, &mmMC_XPB_CLK_GAT[0], sizeof(mmMC_XPB_CLK_GAT)/sizeof(mmMC_XPB_CLK_GAT[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG", REG_MMIO, 0x91f, &mmMC_XPB_INTF_CFG[0], sizeof(mmMC_XPB_INTF_CFG)/sizeof(mmMC_XPB_INTF_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_STS", REG_MMIO, 0x920, &mmMC_XPB_INTF_STS[0], sizeof(mmMC_XPB_INTF_STS)/sizeof(mmMC_XPB_INTF_STS[0]), 0, 0 },
+	{ "mmMC_XPB_PIPE_STS", REG_MMIO, 0x921, &mmMC_XPB_PIPE_STS[0], sizeof(mmMC_XPB_PIPE_STS)/sizeof(mmMC_XPB_PIPE_STS[0]), 0, 0 },
+	{ "mmMC_XPB_SUB_CTRL", REG_MMIO, 0x922, &mmMC_XPB_SUB_CTRL[0], sizeof(mmMC_XPB_SUB_CTRL)/sizeof(mmMC_XPB_SUB_CTRL[0]), 0, 0 },
+	{ "mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB", REG_MMIO, 0x923, &mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0], sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB)/sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0]), 0, 0 },
+	{ "mmMC_XPB_PERF_KNOBS", REG_MMIO, 0x924, &mmMC_XPB_PERF_KNOBS[0], sizeof(mmMC_XPB_PERF_KNOBS)/sizeof(mmMC_XPB_PERF_KNOBS[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY", REG_MMIO, 0x925, &mmMC_XPB_STICKY[0], sizeof(mmMC_XPB_STICKY)/sizeof(mmMC_XPB_STICKY[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY_W1C", REG_MMIO, 0x926, &mmMC_XPB_STICKY_W1C[0], sizeof(mmMC_XPB_STICKY_W1C)/sizeof(mmMC_XPB_STICKY_W1C[0]), 0, 0 },
+	{ "mmMC_XPB_MISC_CFG", REG_MMIO, 0x927, &mmMC_XPB_MISC_CFG[0], sizeof(mmMC_XPB_MISC_CFG)/sizeof(mmMC_XPB_MISC_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG20", REG_MMIO, 0x928, &mmMC_XPB_CLG_CFG20[0], sizeof(mmMC_XPB_CLG_CFG20)/sizeof(mmMC_XPB_CLG_CFG20[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG21", REG_MMIO, 0x929, &mmMC_XPB_CLG_CFG21[0], sizeof(mmMC_XPB_CLG_CFG21)/sizeof(mmMC_XPB_CLG_CFG21[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG22", REG_MMIO, 0x92a, &mmMC_XPB_CLG_CFG22[0], sizeof(mmMC_XPB_CLG_CFG22)/sizeof(mmMC_XPB_CLG_CFG22[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG23", REG_MMIO, 0x92b, &mmMC_XPB_CLG_CFG23[0], sizeof(mmMC_XPB_CLG_CFG23)/sizeof(mmMC_XPB_CLG_CFG23[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG24", REG_MMIO, 0x92c, &mmMC_XPB_CLG_CFG24[0], sizeof(mmMC_XPB_CLG_CFG24)/sizeof(mmMC_XPB_CLG_CFG24[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG25", REG_MMIO, 0x92d, &mmMC_XPB_CLG_CFG25[0], sizeof(mmMC_XPB_CLG_CFG25)/sizeof(mmMC_XPB_CLG_CFG25[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG26", REG_MMIO, 0x92e, &mmMC_XPB_CLG_CFG26[0], sizeof(mmMC_XPB_CLG_CFG26)/sizeof(mmMC_XPB_CLG_CFG26[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG27", REG_MMIO, 0x92f, &mmMC_XPB_CLG_CFG27[0], sizeof(mmMC_XPB_CLG_CFG27)/sizeof(mmMC_XPB_CLG_CFG27[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG28", REG_MMIO, 0x930, &mmMC_XPB_CLG_CFG28[0], sizeof(mmMC_XPB_CLG_CFG28)/sizeof(mmMC_XPB_CLG_CFG28[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG29", REG_MMIO, 0x931, &mmMC_XPB_CLG_CFG29[0], sizeof(mmMC_XPB_CLG_CFG29)/sizeof(mmMC_XPB_CLG_CFG29[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG30", REG_MMIO, 0x932, &mmMC_XPB_CLG_CFG30[0], sizeof(mmMC_XPB_CLG_CFG30)/sizeof(mmMC_XPB_CLG_CFG30[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG31", REG_MMIO, 0x933, &mmMC_XPB_CLG_CFG31[0], sizeof(mmMC_XPB_CLG_CFG31)/sizeof(mmMC_XPB_CLG_CFG31[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG2", REG_MMIO, 0x934, &mmMC_XPB_INTF_CFG2[0], sizeof(mmMC_XPB_INTF_CFG2)/sizeof(mmMC_XPB_INTF_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA_RD", REG_MMIO, 0x935, &mmMC_XPB_CLG_EXTRA_RD[0], sizeof(mmMC_XPB_CLG_EXTRA_RD)/sizeof(mmMC_XPB_CLG_EXTRA_RD[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG32", REG_MMIO, 0x936, &mmMC_XPB_CLG_CFG32[0], sizeof(mmMC_XPB_CLG_CFG32)/sizeof(mmMC_XPB_CLG_CFG32[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG33", REG_MMIO, 0x937, &mmMC_XPB_CLG_CFG33[0], sizeof(mmMC_XPB_CLG_CFG33)/sizeof(mmMC_XPB_CLG_CFG33[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG34", REG_MMIO, 0x938, &mmMC_XPB_CLG_CFG34[0], sizeof(mmMC_XPB_CLG_CFG34)/sizeof(mmMC_XPB_CLG_CFG34[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG35", REG_MMIO, 0x939, &mmMC_XPB_CLG_CFG35[0], sizeof(mmMC_XPB_CLG_CFG35)/sizeof(mmMC_XPB_CLG_CFG35[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG36", REG_MMIO, 0x93a, &mmMC_XPB_CLG_CFG36[0], sizeof(mmMC_XPB_CLG_CFG36)/sizeof(mmMC_XPB_CLG_CFG36[0]), 0, 0 },
+	{ "mmMC_RPB_CONF", REG_MMIO, 0x94d, &mmMC_RPB_CONF[0], sizeof(mmMC_RPB_CONF)/sizeof(mmMC_RPB_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_IF_CONF", REG_MMIO, 0x94e, &mmMC_RPB_IF_CONF[0], sizeof(mmMC_RPB_IF_CONF)/sizeof(mmMC_RPB_IF_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_DBG1", REG_MMIO, 0x94f, &mmMC_RPB_DBG1[0], sizeof(mmMC_RPB_DBG1)/sizeof(mmMC_RPB_DBG1[0]), 0, 0 },
+	{ "mmMC_RPB_EFF_CNTL", REG_MMIO, 0x950, &mmMC_RPB_EFF_CNTL[0], sizeof(mmMC_RPB_EFF_CNTL)/sizeof(mmMC_RPB_EFF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_ARB_CNTL", REG_MMIO, 0x951, &mmMC_RPB_ARB_CNTL[0], sizeof(mmMC_RPB_ARB_CNTL)/sizeof(mmMC_RPB_ARB_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_BIF_CNTL", REG_MMIO, 0x952, &mmMC_RPB_BIF_CNTL[0], sizeof(mmMC_RPB_BIF_CNTL)/sizeof(mmMC_RPB_BIF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_SWITCH_CNTL", REG_MMIO, 0x953, &mmMC_RPB_WR_SWITCH_CNTL[0], sizeof(mmMC_RPB_WR_SWITCH_CNTL)/sizeof(mmMC_RPB_WR_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_COMBINE_CNTL", REG_MMIO, 0x954, &mmMC_RPB_WR_COMBINE_CNTL[0], sizeof(mmMC_RPB_WR_COMBINE_CNTL)/sizeof(mmMC_RPB_WR_COMBINE_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_RD_SWITCH_CNTL", REG_MMIO, 0x955, &mmMC_RPB_RD_SWITCH_CNTL[0], sizeof(mmMC_RPB_RD_SWITCH_CNTL)/sizeof(mmMC_RPB_RD_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_WR", REG_MMIO, 0x956, &mmMC_RPB_CID_QUEUE_WR[0], sizeof(mmMC_RPB_CID_QUEUE_WR)/sizeof(mmMC_RPB_CID_QUEUE_WR[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_RD", REG_MMIO, 0x957, &mmMC_RPB_CID_QUEUE_RD[0], sizeof(mmMC_RPB_CID_QUEUE_RD)/sizeof(mmMC_RPB_CID_QUEUE_RD[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_CNTL", REG_MMIO, 0x958, &mmMC_RPB_PERF_COUNTER_CNTL[0], sizeof(mmMC_RPB_PERF_COUNTER_CNTL)/sizeof(mmMC_RPB_PERF_COUNTER_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_STATUS", REG_MMIO, 0x959, &mmMC_RPB_PERF_COUNTER_STATUS[0], sizeof(mmMC_RPB_PERF_COUNTER_STATUS)/sizeof(mmMC_RPB_PERF_COUNTER_STATUS[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX", REG_MMIO, 0x95a, &mmMC_RPB_CID_QUEUE_EX[0], sizeof(mmMC_RPB_CID_QUEUE_EX)/sizeof(mmMC_RPB_CID_QUEUE_EX[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX_DATA", REG_MMIO, 0x95b, &mmMC_RPB_CID_QUEUE_EX_DATA[0], sizeof(mmMC_RPB_CID_QUEUE_EX_DATA)/sizeof(mmMC_RPB_CID_QUEUE_EX_DATA[0]), 0, 0 },
+	{ "mmMC_CITF_XTRA_ENABLE", REG_MMIO, 0x96d, &mmMC_CITF_XTRA_ENABLE[0], sizeof(mmMC_CITF_XTRA_ENABLE)/sizeof(mmMC_CITF_XTRA_ENABLE[0]), 0, 0 },
+	{ "mmCC_MC_MAX_CHANNEL", REG_MMIO, 0x96e, &mmCC_MC_MAX_CHANNEL[0], sizeof(mmCC_MC_MAX_CHANNEL)/sizeof(mmCC_MC_MAX_CHANNEL[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG", REG_MMIO, 0x96f, &mmMC_CG_CONFIG[0], sizeof(mmMC_CG_CONFIG)/sizeof(mmMC_CG_CONFIG[0]), 0, 0 },
+	{ "mmMC_CITF_CNTL", REG_MMIO, 0x970, &mmMC_CITF_CNTL[0], sizeof(mmMC_CITF_CNTL)/sizeof(mmMC_CITF_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_VM", REG_MMIO, 0x971, &mmMC_CITF_CREDITS_VM[0], sizeof(mmMC_CITF_CREDITS_VM)/sizeof(mmMC_CITF_CREDITS_VM[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_RD", REG_MMIO, 0x972, &mmMC_CITF_CREDITS_ARB_RD[0], sizeof(mmMC_CITF_CREDITS_ARB_RD)/sizeof(mmMC_CITF_CREDITS_ARB_RD[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_WR", REG_MMIO, 0x973, &mmMC_CITF_CREDITS_ARB_WR[0], sizeof(mmMC_CITF_CREDITS_ARB_WR)/sizeof(mmMC_CITF_CREDITS_ARB_WR[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_CNTL", REG_MMIO, 0x974, &mmMC_CITF_DAGB_CNTL[0], sizeof(mmMC_CITF_DAGB_CNTL)/sizeof(mmMC_CITF_DAGB_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS", REG_MMIO, 0x975, &mmMC_CITF_INT_CREDITS[0], sizeof(mmMC_CITF_INT_CREDITS)/sizeof(mmMC_CITF_INT_CREDITS[0]), 0, 0 },
+	{ "mmMC_CITF_RET_MODE", REG_MMIO, 0x976, &mmMC_CITF_RET_MODE[0], sizeof(mmMC_CITF_RET_MODE)/sizeof(mmMC_CITF_RET_MODE[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_DLY", REG_MMIO, 0x977, &mmMC_CITF_DAGB_DLY[0], sizeof(mmMC_CITF_DAGB_DLY)/sizeof(mmMC_CITF_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_RD_GRP_EXT", REG_MMIO, 0x978, &mmMC_RD_GRP_EXT[0], sizeof(mmMC_RD_GRP_EXT)/sizeof(mmMC_RD_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_WR_GRP_EXT", REG_MMIO, 0x979, &mmMC_WR_GRP_EXT[0], sizeof(mmMC_WR_GRP_EXT)/sizeof(mmMC_WR_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_CITF_REMREQ", REG_MMIO, 0x97a, &mmMC_CITF_REMREQ[0], sizeof(mmMC_CITF_REMREQ)/sizeof(mmMC_CITF_REMREQ[0]), 0, 0 },
+	{ "mmMC_WR_TC0", REG_MMIO, 0x97b, &mmMC_WR_TC0[0], sizeof(mmMC_WR_TC0)/sizeof(mmMC_WR_TC0[0]), 0, 0 },
+	{ "mmMC_WR_TC1", REG_MMIO, 0x97c, &mmMC_WR_TC1[0], sizeof(mmMC_WR_TC1)/sizeof(mmMC_WR_TC1[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS_WR", REG_MMIO, 0x97d, &mmMC_CITF_INT_CREDITS_WR[0], sizeof(mmMC_CITF_INT_CREDITS_WR)/sizeof(mmMC_CITF_INT_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_RD_CNTL", REG_MMIO, 0x97f, &mmMC_CITF_WTM_RD_CNTL[0], sizeof(mmMC_CITF_WTM_RD_CNTL)/sizeof(mmMC_CITF_WTM_RD_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_WR_CNTL", REG_MMIO, 0x980, &mmMC_CITF_WTM_WR_CNTL[0], sizeof(mmMC_CITF_WTM_WR_CNTL)/sizeof(mmMC_CITF_WTM_WR_CNTL[0]), 0, 0 },
+	{ "mmMC_RD_CB", REG_MMIO, 0x981, &mmMC_RD_CB[0], sizeof(mmMC_RD_CB)/sizeof(mmMC_RD_CB[0]), 0, 0 },
+	{ "mmMC_RD_DB", REG_MMIO, 0x982, &mmMC_RD_DB[0], sizeof(mmMC_RD_DB)/sizeof(mmMC_RD_DB[0]), 0, 0 },
+	{ "mmMC_RD_TC0", REG_MMIO, 0x983, &mmMC_RD_TC0[0], sizeof(mmMC_RD_TC0)/sizeof(mmMC_RD_TC0[0]), 0, 0 },
+	{ "mmMC_RD_TC1", REG_MMIO, 0x984, &mmMC_RD_TC1[0], sizeof(mmMC_RD_TC1)/sizeof(mmMC_RD_TC1[0]), 0, 0 },
+	{ "mmMC_RD_HUB", REG_MMIO, 0x985, &mmMC_RD_HUB[0], sizeof(mmMC_RD_HUB)/sizeof(mmMC_RD_HUB[0]), 0, 0 },
+	{ "mmMC_WR_CB", REG_MMIO, 0x986, &mmMC_WR_CB[0], sizeof(mmMC_WR_CB)/sizeof(mmMC_WR_CB[0]), 0, 0 },
+	{ "mmMC_WR_DB", REG_MMIO, 0x987, &mmMC_WR_DB[0], sizeof(mmMC_WR_DB)/sizeof(mmMC_WR_DB[0]), 0, 0 },
+	{ "mmMC_WR_HUB", REG_MMIO, 0x988, &mmMC_WR_HUB[0], sizeof(mmMC_WR_HUB)/sizeof(mmMC_WR_HUB[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_XBAR", REG_MMIO, 0x989, &mmMC_CITF_CREDITS_XBAR[0], sizeof(mmMC_CITF_CREDITS_XBAR)/sizeof(mmMC_CITF_CREDITS_XBAR[0]), 0, 0 },
+	{ "mmMC_RD_GRP_LCL", REG_MMIO, 0x98a, &mmMC_RD_GRP_LCL[0], sizeof(mmMC_RD_GRP_LCL)/sizeof(mmMC_RD_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_WR_GRP_LCL", REG_MMIO, 0x98b, &mmMC_WR_GRP_LCL[0], sizeof(mmMC_WR_GRP_LCL)/sizeof(mmMC_WR_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_CNTL2", REG_MMIO, 0x98e, &mmMC_CITF_PERF_MON_CNTL2[0], sizeof(mmMC_CITF_PERF_MON_CNTL2)/sizeof(mmMC_CITF_PERF_MON_CNTL2[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_RSLT2", REG_MMIO, 0x991, &mmMC_CITF_PERF_MON_RSLT2[0], sizeof(mmMC_CITF_PERF_MON_RSLT2)/sizeof(mmMC_CITF_PERF_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_RD_CG", REG_MMIO, 0x992, &mmMC_CITF_MISC_RD_CG[0], sizeof(mmMC_CITF_MISC_RD_CG)/sizeof(mmMC_CITF_MISC_RD_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_WR_CG", REG_MMIO, 0x993, &mmMC_CITF_MISC_WR_CG[0], sizeof(mmMC_CITF_MISC_WR_CG)/sizeof(mmMC_CITF_MISC_WR_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_VM_CG", REG_MMIO, 0x994, &mmMC_CITF_MISC_VM_CG[0], sizeof(mmMC_CITF_MISC_VM_CG)/sizeof(mmMC_CITF_MISC_VM_CG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_DEBUG", REG_MMIO, 0x998, &mmMC_VM_MD_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_DEBUG", REG_MMIO, 0x999, &mmMC_VM_MD_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB1_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_DEBUG", REG_MMIO, 0x99a, &mmMC_VM_MD_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_STATUS", REG_MMIO, 0x99b, &mmMC_VM_MD_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB0_STATUS)/sizeof(mmMC_VM_MD_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_STATUS", REG_MMIO, 0x99c, &mmMC_VM_MD_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB1_STATUS)/sizeof(mmMC_VM_MD_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_STATUS", REG_MMIO, 0x99d, &mmMC_VM_MD_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB2_STATUS)/sizeof(mmMC_VM_MD_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L2ARBITER_L2_CREDITS", REG_MMIO, 0x9a4, &mmMC_VM_MD_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_DEBUG", REG_MMIO, 0x9a7, &mmMC_VM_MD_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_STATUS", REG_MMIO, 0x9a8, &mmMC_VM_MD_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB3_STATUS)/sizeof(mmMC_VM_MD_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_CNTL", REG_MMIO, 0x9bf, &mmMC_ARB_AGE_CNTL[0], sizeof(mmMC_ARB_AGE_CNTL)/sizeof(mmMC_ARB_AGE_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS2", REG_MMIO, 0x9c0, &mmMC_ARB_RET_CREDITS2[0], sizeof(mmMC_ARB_RET_CREDITS2)/sizeof(mmMC_ARB_RET_CREDITS2[0]), 0, 0 },
+	{ "mmMC_ARB_FED_CNTL", REG_MMIO, 0x9c1, &mmMC_ARB_FED_CNTL[0], sizeof(mmMC_ARB_FED_CNTL)/sizeof(mmMC_ARB_FED_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_STATUS", REG_MMIO, 0x9c2, &mmMC_ARB_GECC2_STATUS[0], sizeof(mmMC_ARB_GECC2_STATUS)/sizeof(mmMC_ARB_GECC2_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_MISC", REG_MMIO, 0x9c3, &mmMC_ARB_GECC2_MISC[0], sizeof(mmMC_ARB_GECC2_MISC)/sizeof(mmMC_ARB_GECC2_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG", REG_MMIO, 0x9c4, &mmMC_ARB_GECC2_DEBUG[0], sizeof(mmMC_ARB_GECC2_DEBUG)/sizeof(mmMC_ARB_GECC2_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG2", REG_MMIO, 0x9c5, &mmMC_ARB_GECC2_DEBUG2[0], sizeof(mmMC_ARB_GECC2_DEBUG2)/sizeof(mmMC_ARB_GECC2_DEBUG2[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2", REG_MMIO, 0x9c9, &mmMC_ARB_GECC2[0], sizeof(mmMC_ARB_GECC2)/sizeof(mmMC_ARB_GECC2[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_CLI", REG_MMIO, 0x9ca, &mmMC_ARB_GECC2_CLI[0], sizeof(mmMC_ARB_GECC2_CLI)/sizeof(mmMC_ARB_GECC2_CLI[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_SWIZ0", REG_MMIO, 0x9cb, &mmMC_ARB_ADDR_SWIZ0[0], sizeof(mmMC_ARB_ADDR_SWIZ0)/sizeof(mmMC_ARB_ADDR_SWIZ0[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_SWIZ1", REG_MMIO, 0x9cc, &mmMC_ARB_ADDR_SWIZ1[0], sizeof(mmMC_ARB_ADDR_SWIZ1)/sizeof(mmMC_ARB_ADDR_SWIZ1[0]), 0, 0 },
+	{ "mmMC_ARB_MISC3", REG_MMIO, 0x9cd, &mmMC_ARB_MISC3[0], sizeof(mmMC_ARB_MISC3)/sizeof(mmMC_ARB_MISC3[0]), 0, 0 },
+	{ "mmMC_ARB_WCDR_2", REG_MMIO, 0x9ce, &mmMC_ARB_WCDR_2[0], sizeof(mmMC_ARB_WCDR_2)/sizeof(mmMC_ARB_WCDR_2[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DATA", REG_MMIO, 0x9cf, &mmMC_ARB_RTT_DATA[0], sizeof(mmMC_ARB_RTT_DATA)/sizeof(mmMC_ARB_RTT_DATA[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL0", REG_MMIO, 0x9d0, &mmMC_ARB_RTT_CNTL0[0], sizeof(mmMC_ARB_RTT_CNTL0)/sizeof(mmMC_ARB_RTT_CNTL0[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL1", REG_MMIO, 0x9d1, &mmMC_ARB_RTT_CNTL1[0], sizeof(mmMC_ARB_RTT_CNTL1)/sizeof(mmMC_ARB_RTT_CNTL1[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL2", REG_MMIO, 0x9d2, &mmMC_ARB_RTT_CNTL2[0], sizeof(mmMC_ARB_RTT_CNTL2)/sizeof(mmMC_ARB_RTT_CNTL2[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DEBUG", REG_MMIO, 0x9d3, &mmMC_ARB_RTT_DEBUG[0], sizeof(mmMC_ARB_RTT_DEBUG)/sizeof(mmMC_ARB_RTT_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_CAC_CNTL", REG_MMIO, 0x9d4, &mmMC_ARB_CAC_CNTL[0], sizeof(mmMC_ARB_CAC_CNTL)/sizeof(mmMC_ARB_CAC_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_MISC2", REG_MMIO, 0x9d5, &mmMC_ARB_MISC2[0], sizeof(mmMC_ARB_MISC2)/sizeof(mmMC_ARB_MISC2[0]), 0, 0 },
+	{ "mmMC_ARB_MISC", REG_MMIO, 0x9d6, &mmMC_ARB_MISC[0], sizeof(mmMC_ARB_MISC)/sizeof(mmMC_ARB_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_BANKMAP", REG_MMIO, 0x9d7, &mmMC_ARB_BANKMAP[0], sizeof(mmMC_ARB_BANKMAP)/sizeof(mmMC_ARB_BANKMAP[0]), 0, 0 },
+	{ "mmMC_ARB_RAMCFG", REG_MMIO, 0x9d8, &mmMC_ARB_RAMCFG[0], sizeof(mmMC_ARB_RAMCFG)/sizeof(mmMC_ARB_RAMCFG[0]), 0, 0 },
+	{ "mmMC_ARB_POP", REG_MMIO, 0x9d9, &mmMC_ARB_POP[0], sizeof(mmMC_ARB_POP)/sizeof(mmMC_ARB_POP[0]), 0, 0 },
+	{ "mmMC_ARB_MINCLKS", REG_MMIO, 0x9da, &mmMC_ARB_MINCLKS[0], sizeof(mmMC_ARB_MINCLKS)/sizeof(mmMC_ARB_MINCLKS[0]), 0, 0 },
+	{ "mmMC_ARB_SQM_CNTL", REG_MMIO, 0x9db, &mmMC_ARB_SQM_CNTL[0], sizeof(mmMC_ARB_SQM_CNTL)/sizeof(mmMC_ARB_SQM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_HASH", REG_MMIO, 0x9dc, &mmMC_ARB_ADDR_HASH[0], sizeof(mmMC_ARB_ADDR_HASH)/sizeof(mmMC_ARB_ADDR_HASH[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING", REG_MMIO, 0x9dd, &mmMC_ARB_DRAM_TIMING[0], sizeof(mmMC_ARB_DRAM_TIMING)/sizeof(mmMC_ARB_DRAM_TIMING[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2", REG_MMIO, 0x9de, &mmMC_ARB_DRAM_TIMING2[0], sizeof(mmMC_ARB_DRAM_TIMING2)/sizeof(mmMC_ARB_DRAM_TIMING2[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_RD", REG_MMIO, 0x9df, &mmMC_ARB_WTM_CNTL_RD[0], sizeof(mmMC_ARB_WTM_CNTL_RD)/sizeof(mmMC_ARB_WTM_CNTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_WR", REG_MMIO, 0x9e0, &mmMC_ARB_WTM_CNTL_WR[0], sizeof(mmMC_ARB_WTM_CNTL_WR)/sizeof(mmMC_ARB_WTM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_RD", REG_MMIO, 0x9e1, &mmMC_ARB_WTM_GRPWT_RD[0], sizeof(mmMC_ARB_WTM_GRPWT_RD)/sizeof(mmMC_ARB_WTM_GRPWT_RD[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_WR", REG_MMIO, 0x9e2, &mmMC_ARB_WTM_GRPWT_WR[0], sizeof(mmMC_ARB_WTM_GRPWT_WR)/sizeof(mmMC_ARB_WTM_GRPWT_WR[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_RD", REG_MMIO, 0x9e3, &mmMC_ARB_TM_CNTL_RD[0], sizeof(mmMC_ARB_TM_CNTL_RD)/sizeof(mmMC_ARB_TM_CNTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_WR", REG_MMIO, 0x9e4, &mmMC_ARB_TM_CNTL_WR[0], sizeof(mmMC_ARB_TM_CNTL_WR)/sizeof(mmMC_ARB_TM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_RD", REG_MMIO, 0x9e5, &mmMC_ARB_LAZY0_RD[0], sizeof(mmMC_ARB_LAZY0_RD)/sizeof(mmMC_ARB_LAZY0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_WR", REG_MMIO, 0x9e6, &mmMC_ARB_LAZY0_WR[0], sizeof(mmMC_ARB_LAZY0_WR)/sizeof(mmMC_ARB_LAZY0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_RD", REG_MMIO, 0x9e7, &mmMC_ARB_LAZY1_RD[0], sizeof(mmMC_ARB_LAZY1_RD)/sizeof(mmMC_ARB_LAZY1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_WR", REG_MMIO, 0x9e8, &mmMC_ARB_LAZY1_WR[0], sizeof(mmMC_ARB_LAZY1_WR)/sizeof(mmMC_ARB_LAZY1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_RD", REG_MMIO, 0x9e9, &mmMC_ARB_AGE_RD[0], sizeof(mmMC_ARB_AGE_RD)/sizeof(mmMC_ARB_AGE_RD[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_WR", REG_MMIO, 0x9ea, &mmMC_ARB_AGE_WR[0], sizeof(mmMC_ARB_AGE_WR)/sizeof(mmMC_ARB_AGE_WR[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_CNTL", REG_MMIO, 0x9eb, &mmMC_ARB_RFSH_CNTL[0], sizeof(mmMC_ARB_RFSH_CNTL)/sizeof(mmMC_ARB_RFSH_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_RATE", REG_MMIO, 0x9ec, &mmMC_ARB_RFSH_RATE[0], sizeof(mmMC_ARB_RFSH_RATE)/sizeof(mmMC_ARB_RFSH_RATE[0]), 0, 0 },
+	{ "mmMC_ARB_PM_CNTL", REG_MMIO, 0x9ed, &mmMC_ARB_PM_CNTL[0], sizeof(mmMC_ARB_PM_CNTL)/sizeof(mmMC_ARB_PM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_RD_CNTL", REG_MMIO, 0x9ee, &mmMC_ARB_GDEC_RD_CNTL[0], sizeof(mmMC_ARB_GDEC_RD_CNTL)/sizeof(mmMC_ARB_GDEC_RD_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_WR_CNTL", REG_MMIO, 0x9ef, &mmMC_ARB_GDEC_WR_CNTL[0], sizeof(mmMC_ARB_GDEC_WR_CNTL)/sizeof(mmMC_ARB_GDEC_WR_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_LM_RD", REG_MMIO, 0x9f0, &mmMC_ARB_LM_RD[0], sizeof(mmMC_ARB_LM_RD)/sizeof(mmMC_ARB_LM_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LM_WR", REG_MMIO, 0x9f1, &mmMC_ARB_LM_WR[0], sizeof(mmMC_ARB_LM_WR)/sizeof(mmMC_ARB_LM_WR[0]), 0, 0 },
+	{ "mmMC_ARB_REMREQ", REG_MMIO, 0x9f2, &mmMC_ARB_REMREQ[0], sizeof(mmMC_ARB_REMREQ)/sizeof(mmMC_ARB_REMREQ[0]), 0, 0 },
+	{ "mmMC_ARB_REPLAY", REG_MMIO, 0x9f3, &mmMC_ARB_REPLAY[0], sizeof(mmMC_ARB_REPLAY)/sizeof(mmMC_ARB_REPLAY[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_RD", REG_MMIO, 0x9f4, &mmMC_ARB_RET_CREDITS_RD[0], sizeof(mmMC_ARB_RET_CREDITS_RD)/sizeof(mmMC_ARB_RET_CREDITS_RD[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_WR", REG_MMIO, 0x9f5, &mmMC_ARB_RET_CREDITS_WR[0], sizeof(mmMC_ARB_RET_CREDITS_WR)/sizeof(mmMC_ARB_RET_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_CID", REG_MMIO, 0x9f6, &mmMC_ARB_MAX_LAT_CID[0], sizeof(mmMC_ARB_MAX_LAT_CID)/sizeof(mmMC_ARB_MAX_LAT_CID[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_RSLT0", REG_MMIO, 0x9f7, &mmMC_ARB_MAX_LAT_RSLT0[0], sizeof(mmMC_ARB_MAX_LAT_RSLT0)/sizeof(mmMC_ARB_MAX_LAT_RSLT0[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_RSLT1", REG_MMIO, 0x9f8, &mmMC_ARB_MAX_LAT_RSLT1[0], sizeof(mmMC_ARB_MAX_LAT_RSLT1)/sizeof(mmMC_ARB_MAX_LAT_RSLT1[0]), 0, 0 },
+	{ "mmMC_ARB_SSM", REG_MMIO, 0x9f9, &mmMC_ARB_SSM[0], sizeof(mmMC_ARB_SSM)/sizeof(mmMC_ARB_SSM[0]), 0, 0 },
+	{ "mmMC_ARB_CG", REG_MMIO, 0x9fa, &mmMC_ARB_CG[0], sizeof(mmMC_ARB_CG)/sizeof(mmMC_ARB_CG[0]), 0, 0 },
+	{ "mmMC_ARB_WCDR", REG_MMIO, 0x9fb, &mmMC_ARB_WCDR[0], sizeof(mmMC_ARB_WCDR)/sizeof(mmMC_ARB_WCDR[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING_1", REG_MMIO, 0x9fc, &mmMC_ARB_DRAM_TIMING_1[0], sizeof(mmMC_ARB_DRAM_TIMING_1)/sizeof(mmMC_ARB_DRAM_TIMING_1[0]), 0, 0 },
+	{ "mmMC_ARB_BUSY_STATUS", REG_MMIO, 0x9fd, &mmMC_ARB_BUSY_STATUS[0], sizeof(mmMC_ARB_BUSY_STATUS)/sizeof(mmMC_ARB_BUSY_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2_1", REG_MMIO, 0x9ff, &mmMC_ARB_DRAM_TIMING2_1[0], sizeof(mmMC_ARB_DRAM_TIMING2_1)/sizeof(mmMC_ARB_DRAM_TIMING2_1[0]), 0, 0 },
+	{ "mmMC_ARB_BURST_TIME", REG_MMIO, 0xa02, &mmMC_ARB_BURST_TIME[0], sizeof(mmMC_ARB_BURST_TIME)/sizeof(mmMC_ARB_BURST_TIME[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS0_BASE", REG_MMIO, 0xa05, &mmMC_FUS_DRAM0_CS0_BASE[0], sizeof(mmMC_FUS_DRAM0_CS0_BASE)/sizeof(mmMC_FUS_DRAM0_CS0_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS0_BASE", REG_MMIO, 0xa06, &mmMC_FUS_DRAM1_CS0_BASE[0], sizeof(mmMC_FUS_DRAM1_CS0_BASE)/sizeof(mmMC_FUS_DRAM1_CS0_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS1_BASE", REG_MMIO, 0xa07, &mmMC_FUS_DRAM0_CS1_BASE[0], sizeof(mmMC_FUS_DRAM0_CS1_BASE)/sizeof(mmMC_FUS_DRAM0_CS1_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS1_BASE", REG_MMIO, 0xa08, &mmMC_FUS_DRAM1_CS1_BASE[0], sizeof(mmMC_FUS_DRAM1_CS1_BASE)/sizeof(mmMC_FUS_DRAM1_CS1_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS2_BASE", REG_MMIO, 0xa09, &mmMC_FUS_DRAM0_CS2_BASE[0], sizeof(mmMC_FUS_DRAM0_CS2_BASE)/sizeof(mmMC_FUS_DRAM0_CS2_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS2_BASE", REG_MMIO, 0xa0a, &mmMC_FUS_DRAM1_CS2_BASE[0], sizeof(mmMC_FUS_DRAM1_CS2_BASE)/sizeof(mmMC_FUS_DRAM1_CS2_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS3_BASE", REG_MMIO, 0xa0b, &mmMC_FUS_DRAM0_CS3_BASE[0], sizeof(mmMC_FUS_DRAM0_CS3_BASE)/sizeof(mmMC_FUS_DRAM0_CS3_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS3_BASE", REG_MMIO, 0xa0c, &mmMC_FUS_DRAM1_CS3_BASE[0], sizeof(mmMC_FUS_DRAM1_CS3_BASE)/sizeof(mmMC_FUS_DRAM1_CS3_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS01_MASK", REG_MMIO, 0xa0d, NULL, 0, 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS01_MASK", REG_MMIO, 0xa0e, NULL, 0, 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS23_MASK", REG_MMIO, 0xa0f, NULL, 0, 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS23_MASK", REG_MMIO, 0xa10, NULL, 0, 0, 0 },
+	{ "mmMC_FUS_DRAM0_BANK_ADDR_MAPPING", REG_MMIO, 0xa11, &mmMC_FUS_DRAM0_BANK_ADDR_MAPPING[0], sizeof(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING)/sizeof(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_BANK_ADDR_MAPPING", REG_MMIO, 0xa12, &mmMC_FUS_DRAM1_BANK_ADDR_MAPPING[0], sizeof(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING)/sizeof(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CTL_BASE", REG_MMIO, 0xa13, &mmMC_FUS_DRAM0_CTL_BASE[0], sizeof(mmMC_FUS_DRAM0_CTL_BASE)/sizeof(mmMC_FUS_DRAM0_CTL_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CTL_BASE", REG_MMIO, 0xa14, &mmMC_FUS_DRAM1_CTL_BASE[0], sizeof(mmMC_FUS_DRAM1_CTL_BASE)/sizeof(mmMC_FUS_DRAM1_CTL_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CTL_LIMIT", REG_MMIO, 0xa15, &mmMC_FUS_DRAM0_CTL_LIMIT[0], sizeof(mmMC_FUS_DRAM0_CTL_LIMIT)/sizeof(mmMC_FUS_DRAM0_CTL_LIMIT[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CTL_LIMIT", REG_MMIO, 0xa16, &mmMC_FUS_DRAM1_CTL_LIMIT[0], sizeof(mmMC_FUS_DRAM1_CTL_LIMIT)/sizeof(mmMC_FUS_DRAM1_CTL_LIMIT[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_CTL_HIGH_01", REG_MMIO, 0xa17, &mmMC_FUS_DRAM_CTL_HIGH_01[0], sizeof(mmMC_FUS_DRAM_CTL_HIGH_01)/sizeof(mmMC_FUS_DRAM_CTL_HIGH_01[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_CTL_HIGH_23", REG_MMIO, 0xa18, &mmMC_FUS_DRAM_CTL_HIGH_23[0], sizeof(mmMC_FUS_DRAM_CTL_HIGH_23)/sizeof(mmMC_FUS_DRAM_CTL_HIGH_23[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_MODE", REG_MMIO, 0xa19, &mmMC_FUS_DRAM_MODE[0], sizeof(mmMC_FUS_DRAM_MODE)/sizeof(mmMC_FUS_DRAM_MODE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_APER_BASE", REG_MMIO, 0xa1a, &mmMC_FUS_DRAM_APER_BASE[0], sizeof(mmMC_FUS_DRAM_APER_BASE)/sizeof(mmMC_FUS_DRAM_APER_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_APER_TOP", REG_MMIO, 0xa1b, &mmMC_FUS_DRAM_APER_TOP[0], sizeof(mmMC_FUS_DRAM_APER_TOP)/sizeof(mmMC_FUS_DRAM_APER_TOP[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_C6SAVE_APER_BASE", REG_MMIO, 0xa1c, &mmMC_FUS_DRAM_C6SAVE_APER_BASE[0], sizeof(mmMC_FUS_DRAM_C6SAVE_APER_BASE)/sizeof(mmMC_FUS_DRAM_C6SAVE_APER_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_C6SAVE_APER_TOP", REG_MMIO, 0xa1d, &mmMC_FUS_DRAM_C6SAVE_APER_TOP[0], sizeof(mmMC_FUS_DRAM_C6SAVE_APER_TOP)/sizeof(mmMC_FUS_DRAM_C6SAVE_APER_TOP[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_APER_DEF", REG_MMIO, 0xa1e, &mmMC_FUS_DRAM_APER_DEF[0], sizeof(mmMC_FUS_DRAM_APER_DEF)/sizeof(mmMC_FUS_DRAM_APER_DEF[0]), 0, 0 },
+	{ "mmMC_FUS_ARB_GARLIC_ISOC_PRI", REG_MMIO, 0xa1f, &mmMC_FUS_ARB_GARLIC_ISOC_PRI[0], sizeof(mmMC_FUS_ARB_GARLIC_ISOC_PRI)/sizeof(mmMC_FUS_ARB_GARLIC_ISOC_PRI[0]), 0, 0 },
+	{ "mmMC_FUS_ARB_GARLIC_CNTL", REG_MMIO, 0xa20, &mmMC_FUS_ARB_GARLIC_CNTL[0], sizeof(mmMC_FUS_ARB_GARLIC_CNTL)/sizeof(mmMC_FUS_ARB_GARLIC_CNTL[0]), 0, 0 },
+	{ "mmMC_FUS_ARB_GARLIC_WR_PRI", REG_MMIO, 0xa21, &mmMC_FUS_ARB_GARLIC_WR_PRI[0], sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI)/sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI[0]), 0, 0 },
+	{ "mmMC_FUS_ARB_GARLIC_WR_PRI2", REG_MMIO, 0xa22, &mmMC_FUS_ARB_GARLIC_WR_PRI2[0], sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI2)/sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI2[0]), 0, 0 },
+	{ "mmMC_CG_DATAPORT", REG_MMIO, 0xa32, &mmMC_CG_DATAPORT[0], sizeof(mmMC_CG_DATAPORT)/sizeof(mmMC_CG_DATAPORT[0]), 0, 0 },
+	{ "mmMC_XBAR_ADDR_DEC", REG_MMIO, 0xc80, &mmMC_XBAR_ADDR_DEC[0], sizeof(mmMC_XBAR_ADDR_DEC)/sizeof(mmMC_XBAR_ADDR_DEC[0]), 0, 0 },
+	{ "mmMC_XBAR_REMOTE", REG_MMIO, 0xc81, &mmMC_XBAR_REMOTE[0], sizeof(mmMC_XBAR_REMOTE)/sizeof(mmMC_XBAR_REMOTE[0]), 0, 0 },
+	{ "mmMC_XBAR_WRREQ_CREDIT", REG_MMIO, 0xc82, &mmMC_XBAR_WRREQ_CREDIT[0], sizeof(mmMC_XBAR_WRREQ_CREDIT)/sizeof(mmMC_XBAR_WRREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_CREDIT", REG_MMIO, 0xc83, &mmMC_XBAR_RDREQ_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_CREDIT)/sizeof(mmMC_XBAR_RDREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_PRI_CREDIT", REG_MMIO, 0xc84, &mmMC_XBAR_RDREQ_PRI_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT)/sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT1", REG_MMIO, 0xc85, &mmMC_XBAR_WRRET_CREDIT1[0], sizeof(mmMC_XBAR_WRRET_CREDIT1)/sizeof(mmMC_XBAR_WRRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT2", REG_MMIO, 0xc86, &mmMC_XBAR_WRRET_CREDIT2[0], sizeof(mmMC_XBAR_WRRET_CREDIT2)/sizeof(mmMC_XBAR_WRRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT1", REG_MMIO, 0xc87, &mmMC_XBAR_RDRET_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_CREDIT1)/sizeof(mmMC_XBAR_RDRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT2", REG_MMIO, 0xc88, &mmMC_XBAR_RDRET_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_CREDIT2)/sizeof(mmMC_XBAR_RDRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT1", REG_MMIO, 0xc89, &mmMC_XBAR_RDRET_PRI_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT2", REG_MMIO, 0xc8a, &mmMC_XBAR_RDRET_PRI_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_CHTRIREMAP", REG_MMIO, 0xc8b, &mmMC_XBAR_CHTRIREMAP[0], sizeof(mmMC_XBAR_CHTRIREMAP)/sizeof(mmMC_XBAR_CHTRIREMAP[0]), 0, 0 },
+	{ "mmMC_XBAR_TWOCHAN", REG_MMIO, 0xc8c, &mmMC_XBAR_TWOCHAN[0], sizeof(mmMC_XBAR_TWOCHAN)/sizeof(mmMC_XBAR_TWOCHAN[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB", REG_MMIO, 0xc8d, &mmMC_XBAR_ARB[0], sizeof(mmMC_XBAR_ARB)/sizeof(mmMC_XBAR_ARB[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB_MAX_BURST", REG_MMIO, 0xc8e, &mmMC_XBAR_ARB_MAX_BURST[0], sizeof(mmMC_XBAR_ARB_MAX_BURST)/sizeof(mmMC_XBAR_ARB_MAX_BURST[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL0", REG_MMIO, 0xc8f, &mmMC_XBAR_PERF_MON_CNTL0[0], sizeof(mmMC_XBAR_PERF_MON_CNTL0)/sizeof(mmMC_XBAR_PERF_MON_CNTL0[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL1", REG_MMIO, 0xc90, &mmMC_XBAR_PERF_MON_CNTL1[0], sizeof(mmMC_XBAR_PERF_MON_CNTL1)/sizeof(mmMC_XBAR_PERF_MON_CNTL1[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL2", REG_MMIO, 0xc91, &mmMC_XBAR_PERF_MON_CNTL2[0], sizeof(mmMC_XBAR_PERF_MON_CNTL2)/sizeof(mmMC_XBAR_PERF_MON_CNTL2[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT0", REG_MMIO, 0xc92, &mmMC_XBAR_PERF_MON_RSLT0[0], sizeof(mmMC_XBAR_PERF_MON_RSLT0)/sizeof(mmMC_XBAR_PERF_MON_RSLT0[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT1", REG_MMIO, 0xc93, &mmMC_XBAR_PERF_MON_RSLT1[0], sizeof(mmMC_XBAR_PERF_MON_RSLT1)/sizeof(mmMC_XBAR_PERF_MON_RSLT1[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT2", REG_MMIO, 0xc94, &mmMC_XBAR_PERF_MON_RSLT2[0], sizeof(mmMC_XBAR_PERF_MON_RSLT2)/sizeof(mmMC_XBAR_PERF_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT3", REG_MMIO, 0xc95, &mmMC_XBAR_PERF_MON_RSLT3[0], sizeof(mmMC_XBAR_PERF_MON_RSLT3)/sizeof(mmMC_XBAR_PERF_MON_RSLT3[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_MAX_THSH", REG_MMIO, 0xc96, &mmMC_XBAR_PERF_MON_MAX_THSH[0], sizeof(mmMC_XBAR_PERF_MON_MAX_THSH)/sizeof(mmMC_XBAR_PERF_MON_MAX_THSH[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE0", REG_MMIO, 0xc97, &mmMC_XBAR_SPARE0[0], sizeof(mmMC_XBAR_SPARE0)/sizeof(mmMC_XBAR_SPARE0[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE1", REG_MMIO, 0xc98, &mmMC_XBAR_SPARE1[0], sizeof(mmMC_XBAR_SPARE1)/sizeof(mmMC_XBAR_SPARE1[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_LOW_ADDR", REG_MMIO, 0xcc0, &mmATC_VM_APERTURE0_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE0_LOW_ADDR)/sizeof(mmATC_VM_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_LOW_ADDR", REG_MMIO, 0xcc1, &mmATC_VM_APERTURE1_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE1_LOW_ADDR)/sizeof(mmATC_VM_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_HIGH_ADDR", REG_MMIO, 0xcc2, &mmATC_VM_APERTURE0_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE0_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_HIGH_ADDR", REG_MMIO, 0xcc3, &mmATC_VM_APERTURE1_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE1_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL", REG_MMIO, 0xcc4, &mmATC_VM_APERTURE0_CNTL[0], sizeof(mmATC_VM_APERTURE0_CNTL)/sizeof(mmATC_VM_APERTURE0_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL", REG_MMIO, 0xcc5, &mmATC_VM_APERTURE1_CNTL[0], sizeof(mmATC_VM_APERTURE1_CNTL)/sizeof(mmATC_VM_APERTURE1_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL2", REG_MMIO, 0xcc6, &mmATC_VM_APERTURE0_CNTL2[0], sizeof(mmATC_VM_APERTURE0_CNTL2)/sizeof(mmATC_VM_APERTURE0_CNTL2[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL2", REG_MMIO, 0xcc7, &mmATC_VM_APERTURE1_CNTL2[0], sizeof(mmATC_VM_APERTURE1_CNTL2)/sizeof(mmATC_VM_APERTURE1_CNTL2[0]), 0, 0 },
+	{ "mmATC_ATS_CNTL", REG_MMIO, 0xcc9, &mmATC_ATS_CNTL[0], sizeof(mmATC_ATS_CNTL)/sizeof(mmATC_ATS_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_DEBUG", REG_MMIO, 0xcca, &mmATC_ATS_DEBUG[0], sizeof(mmATC_ATS_DEBUG)/sizeof(mmATC_ATS_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_DEBUG", REG_MMIO, 0xccb, &mmATC_ATS_FAULT_DEBUG[0], sizeof(mmATC_ATS_FAULT_DEBUG)/sizeof(mmATC_ATS_FAULT_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_STATUS", REG_MMIO, 0xccc, &mmATC_ATS_STATUS[0], sizeof(mmATC_ATS_STATUS)/sizeof(mmATC_ATS_STATUS[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_CNTL", REG_MMIO, 0xccd, &mmATC_ATS_FAULT_CNTL[0], sizeof(mmATC_ATS_FAULT_CNTL)/sizeof(mmATC_ATS_FAULT_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_INFO", REG_MMIO, 0xcce, &mmATC_ATS_FAULT_STATUS_INFO[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO)/sizeof(mmATC_ATS_FAULT_STATUS_INFO[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_ADDR", REG_MMIO, 0xccf, &mmATC_ATS_FAULT_STATUS_ADDR[0], sizeof(mmATC_ATS_FAULT_STATUS_ADDR)/sizeof(mmATC_ATS_FAULT_STATUS_ADDR[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_LOW", REG_MMIO, 0xcd0, &mmATC_ATS_DEFAULT_PAGE_LOW[0], sizeof(mmATC_ATS_DEFAULT_PAGE_LOW)/sizeof(mmATC_ATS_DEFAULT_PAGE_LOW[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_CNTL", REG_MMIO, 0xcd1, &mmATC_ATS_DEFAULT_PAGE_CNTL[0], sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL)/sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL[0]), 0, 0 },
+	{ "mmATC_MISC_CG", REG_MMIO, 0xcd4, &mmATC_MISC_CG[0], sizeof(mmATC_MISC_CG)/sizeof(mmATC_MISC_CG[0]), 0, 0 },
+	{ "mmATC_L2_CNTL", REG_MMIO, 0xcd5, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 },
+	{ "mmATC_L2_CNTL2", REG_MMIO, 0xcd6, &mmATC_L2_CNTL2[0], sizeof(mmATC_L2_CNTL2)/sizeof(mmATC_L2_CNTL2[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG", REG_MMIO, 0xcd7, &mmATC_L2_DEBUG[0], sizeof(mmATC_L2_DEBUG)/sizeof(mmATC_L2_DEBUG[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG2", REG_MMIO, 0xcd8, &mmATC_L2_DEBUG2[0], sizeof(mmATC_L2_DEBUG2)/sizeof(mmATC_L2_DEBUG2[0]), 0, 0 },
+	{ "mmATC_L1_CNTL", REG_MMIO, 0xcdc, &mmATC_L1_CNTL[0], sizeof(mmATC_L1_CNTL)/sizeof(mmATC_L1_CNTL[0]), 0, 0 },
+	{ "mmATC_L1_ADDRESS_OFFSET", REG_MMIO, 0xcdd, &mmATC_L1_ADDRESS_OFFSET[0], sizeof(mmATC_L1_ADDRESS_OFFSET)/sizeof(mmATC_L1_ADDRESS_OFFSET[0]), 0, 0 },
+	{ "mmATC_L1RD_DEBUG_TLB", REG_MMIO, 0xcde, &mmATC_L1RD_DEBUG_TLB[0], sizeof(mmATC_L1RD_DEBUG_TLB)/sizeof(mmATC_L1RD_DEBUG_TLB[0]), 0, 0 },
+	{ "mmATC_L1WR_DEBUG_TLB", REG_MMIO, 0xcdf, &mmATC_L1WR_DEBUG_TLB[0], sizeof(mmATC_L1WR_DEBUG_TLB)/sizeof(mmATC_L1WR_DEBUG_TLB[0]), 0, 0 },
+	{ "mmATC_L1RD_STATUS", REG_MMIO, 0xce0, &mmATC_L1RD_STATUS[0], sizeof(mmATC_L1RD_STATUS)/sizeof(mmATC_L1RD_STATUS[0]), 0, 0 },
+	{ "mmATC_L1WR_STATUS", REG_MMIO, 0xce1, &mmATC_L1WR_STATUS[0], sizeof(mmATC_L1WR_STATUS)/sizeof(mmATC_L1WR_STATUS[0]), 0, 0 },
+	{ "mmATC_VMID_PASID_MAPPING_UPDATE_STATUS", REG_MMIO, 0xce6, &mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0], sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)/sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmATC_VMID0_PASID_MAPPING", REG_MMIO, 0xce7, &mmATC_VMID0_PASID_MAPPING[0], sizeof(mmATC_VMID0_PASID_MAPPING)/sizeof(mmATC_VMID0_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID1_PASID_MAPPING", REG_MMIO, 0xce8, &mmATC_VMID1_PASID_MAPPING[0], sizeof(mmATC_VMID1_PASID_MAPPING)/sizeof(mmATC_VMID1_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID2_PASID_MAPPING", REG_MMIO, 0xce9, &mmATC_VMID2_PASID_MAPPING[0], sizeof(mmATC_VMID2_PASID_MAPPING)/sizeof(mmATC_VMID2_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID3_PASID_MAPPING", REG_MMIO, 0xcea, &mmATC_VMID3_PASID_MAPPING[0], sizeof(mmATC_VMID3_PASID_MAPPING)/sizeof(mmATC_VMID3_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID4_PASID_MAPPING", REG_MMIO, 0xceb, &mmATC_VMID4_PASID_MAPPING[0], sizeof(mmATC_VMID4_PASID_MAPPING)/sizeof(mmATC_VMID4_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID5_PASID_MAPPING", REG_MMIO, 0xcec, &mmATC_VMID5_PASID_MAPPING[0], sizeof(mmATC_VMID5_PASID_MAPPING)/sizeof(mmATC_VMID5_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID6_PASID_MAPPING", REG_MMIO, 0xced, &mmATC_VMID6_PASID_MAPPING[0], sizeof(mmATC_VMID6_PASID_MAPPING)/sizeof(mmATC_VMID6_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID7_PASID_MAPPING", REG_MMIO, 0xcee, &mmATC_VMID7_PASID_MAPPING[0], sizeof(mmATC_VMID7_PASID_MAPPING)/sizeof(mmATC_VMID7_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID8_PASID_MAPPING", REG_MMIO, 0xcef, &mmATC_VMID8_PASID_MAPPING[0], sizeof(mmATC_VMID8_PASID_MAPPING)/sizeof(mmATC_VMID8_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID9_PASID_MAPPING", REG_MMIO, 0xcf0, &mmATC_VMID9_PASID_MAPPING[0], sizeof(mmATC_VMID9_PASID_MAPPING)/sizeof(mmATC_VMID9_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID10_PASID_MAPPING", REG_MMIO, 0xcf1, &mmATC_VMID10_PASID_MAPPING[0], sizeof(mmATC_VMID10_PASID_MAPPING)/sizeof(mmATC_VMID10_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID11_PASID_MAPPING", REG_MMIO, 0xcf2, &mmATC_VMID11_PASID_MAPPING[0], sizeof(mmATC_VMID11_PASID_MAPPING)/sizeof(mmATC_VMID11_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID12_PASID_MAPPING", REG_MMIO, 0xcf3, &mmATC_VMID12_PASID_MAPPING[0], sizeof(mmATC_VMID12_PASID_MAPPING)/sizeof(mmATC_VMID12_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID13_PASID_MAPPING", REG_MMIO, 0xcf4, &mmATC_VMID13_PASID_MAPPING[0], sizeof(mmATC_VMID13_PASID_MAPPING)/sizeof(mmATC_VMID13_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID14_PASID_MAPPING", REG_MMIO, 0xcf5, &mmATC_VMID14_PASID_MAPPING[0], sizeof(mmATC_VMID14_PASID_MAPPING)/sizeof(mmATC_VMID14_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID15_PASID_MAPPING", REG_MMIO, 0xcf6, &mmATC_VMID15_PASID_MAPPING[0], sizeof(mmATC_VMID15_PASID_MAPPING)/sizeof(mmATC_VMID15_PASID_MAPPING[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_INDEX", REG_MMIO, 0xd40, &mmGMCON_RENG_RAM_INDEX[0], sizeof(mmGMCON_RENG_RAM_INDEX)/sizeof(mmGMCON_RENG_RAM_INDEX[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_DATA", REG_MMIO, 0xd41, &mmGMCON_RENG_RAM_DATA[0], sizeof(mmGMCON_RENG_RAM_DATA)/sizeof(mmGMCON_RENG_RAM_DATA[0]), 0, 0 },
+	{ "mmGMCON_RENG_EXECUTE", REG_MMIO, 0xd42, &mmGMCON_RENG_EXECUTE[0], sizeof(mmGMCON_RENG_EXECUTE)/sizeof(mmGMCON_RENG_EXECUTE[0]), 0, 0 },
+	{ "mmGMCON_MISC", REG_MMIO, 0xd43, &mmGMCON_MISC[0], sizeof(mmGMCON_MISC)/sizeof(mmGMCON_MISC[0]), 0, 0 },
+	{ "mmGMCON_MISC2", REG_MMIO, 0xd44, &mmGMCON_MISC2[0], sizeof(mmGMCON_MISC2)/sizeof(mmGMCON_MISC2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0xd45, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0xd46, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0xd47, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0", REG_MMIO, 0xd48, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0xd49, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL0", REG_MMIO, 0xd4a, &mmGMCON_PERF_MON_CNTL0[0], sizeof(mmGMCON_PERF_MON_CNTL0)/sizeof(mmGMCON_PERF_MON_CNTL0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL1", REG_MMIO, 0xd4b, &mmGMCON_PERF_MON_CNTL1[0], sizeof(mmGMCON_PERF_MON_CNTL1)/sizeof(mmGMCON_PERF_MON_CNTL1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT0", REG_MMIO, 0xd4c, &mmGMCON_PERF_MON_RSLT0[0], sizeof(mmGMCON_PERF_MON_RSLT0)/sizeof(mmGMCON_PERF_MON_RSLT0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT1", REG_MMIO, 0xd4d, &mmGMCON_PERF_MON_RSLT1[0], sizeof(mmGMCON_PERF_MON_RSLT1)/sizeof(mmGMCON_PERF_MON_RSLT1[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_CONFIG", REG_MMIO, 0xd4e, &mmGMCON_PGFSM_CONFIG[0], sizeof(mmGMCON_PGFSM_CONFIG)/sizeof(mmGMCON_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_WRITE", REG_MMIO, 0xd4f, &mmGMCON_PGFSM_WRITE[0], sizeof(mmGMCON_PGFSM_WRITE)/sizeof(mmGMCON_PGFSM_WRITE[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_READ", REG_MMIO, 0xd50, &mmGMCON_PGFSM_READ[0], sizeof(mmGMCON_PGFSM_READ)/sizeof(mmGMCON_PGFSM_READ[0]), 0, 0 },
+	{ "mmGMCON_MISC3", REG_MMIO, 0xd51, &mmGMCON_MISC3[0], sizeof(mmGMCON_MISC3)/sizeof(mmGMCON_MISC3[0]), 0, 0 },
+	{ "mmGMCON_MASK", REG_MMIO, 0xd52, &mmGMCON_MASK[0], sizeof(mmGMCON_MASK)/sizeof(mmGMCON_MASK[0]), 0, 0 },
+	{ "mmGMCON_DEBUG", REG_MMIO, 0xd5f, &mmGMCON_DEBUG[0], sizeof(mmGMCON_DEBUG)/sizeof(mmGMCON_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_EN_RD", REG_MMIO, 0xdc0, &mmMC_ARB_HARSH_EN_RD[0], sizeof(mmMC_ARB_HARSH_EN_RD)/sizeof(mmMC_ARB_HARSH_EN_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_EN_WR", REG_MMIO, 0xdc1, &mmMC_ARB_HARSH_EN_WR[0], sizeof(mmMC_ARB_HARSH_EN_WR)/sizeof(mmMC_ARB_HARSH_EN_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI0_RD", REG_MMIO, 0xdc2, &mmMC_ARB_HARSH_TX_HI0_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI0_RD)/sizeof(mmMC_ARB_HARSH_TX_HI0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI0_WR", REG_MMIO, 0xdc3, &mmMC_ARB_HARSH_TX_HI0_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI0_WR)/sizeof(mmMC_ARB_HARSH_TX_HI0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI1_RD", REG_MMIO, 0xdc4, &mmMC_ARB_HARSH_TX_HI1_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI1_RD)/sizeof(mmMC_ARB_HARSH_TX_HI1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI1_WR", REG_MMIO, 0xdc5, &mmMC_ARB_HARSH_TX_HI1_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI1_WR)/sizeof(mmMC_ARB_HARSH_TX_HI1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO0_RD", REG_MMIO, 0xdc6, &mmMC_ARB_HARSH_TX_LO0_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO0_RD)/sizeof(mmMC_ARB_HARSH_TX_LO0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO0_WR", REG_MMIO, 0xdc7, &mmMC_ARB_HARSH_TX_LO0_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO0_WR)/sizeof(mmMC_ARB_HARSH_TX_LO0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO1_RD", REG_MMIO, 0xdc8, &mmMC_ARB_HARSH_TX_LO1_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO1_RD)/sizeof(mmMC_ARB_HARSH_TX_LO1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO1_WR", REG_MMIO, 0xdc9, &mmMC_ARB_HARSH_TX_LO1_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO1_WR)/sizeof(mmMC_ARB_HARSH_TX_LO1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD0_RD", REG_MMIO, 0xdca, &mmMC_ARB_HARSH_BWPERIOD0_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD0_WR", REG_MMIO, 0xdcb, &mmMC_ARB_HARSH_BWPERIOD0_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD1_RD", REG_MMIO, 0xdcc, &mmMC_ARB_HARSH_BWPERIOD1_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD1_WR", REG_MMIO, 0xdcd, &mmMC_ARB_HARSH_BWPERIOD1_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT0_RD", REG_MMIO, 0xdce, &mmMC_ARB_HARSH_BWCNT0_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT0_RD)/sizeof(mmMC_ARB_HARSH_BWCNT0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT0_WR", REG_MMIO, 0xdcf, &mmMC_ARB_HARSH_BWCNT0_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT0_WR)/sizeof(mmMC_ARB_HARSH_BWCNT0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT1_RD", REG_MMIO, 0xdd0, &mmMC_ARB_HARSH_BWCNT1_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT1_RD)/sizeof(mmMC_ARB_HARSH_BWCNT1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT1_WR", REG_MMIO, 0xdd1, &mmMC_ARB_HARSH_BWCNT1_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT1_WR)/sizeof(mmMC_ARB_HARSH_BWCNT1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT0_RD", REG_MMIO, 0xdd2, &mmMC_ARB_HARSH_SAT0_RD[0], sizeof(mmMC_ARB_HARSH_SAT0_RD)/sizeof(mmMC_ARB_HARSH_SAT0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT0_WR", REG_MMIO, 0xdd3, &mmMC_ARB_HARSH_SAT0_WR[0], sizeof(mmMC_ARB_HARSH_SAT0_WR)/sizeof(mmMC_ARB_HARSH_SAT0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT1_RD", REG_MMIO, 0xdd4, &mmMC_ARB_HARSH_SAT1_RD[0], sizeof(mmMC_ARB_HARSH_SAT1_RD)/sizeof(mmMC_ARB_HARSH_SAT1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT1_WR", REG_MMIO, 0xdd5, &mmMC_ARB_HARSH_SAT1_WR[0], sizeof(mmMC_ARB_HARSH_SAT1_WR)/sizeof(mmMC_ARB_HARSH_SAT1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_CTL_RD", REG_MMIO, 0xdd6, &mmMC_ARB_HARSH_CTL_RD[0], sizeof(mmMC_ARB_HARSH_CTL_RD)/sizeof(mmMC_ARB_HARSH_CTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_CTL_WR", REG_MMIO, 0xdd7, &mmMC_ARB_HARSH_CTL_WR[0], sizeof(mmMC_ARB_HARSH_CTL_WR)/sizeof(mmMC_ARB_HARSH_CTL_WR[0]), 0, 0 },
diff --git a/src/lib/ip/gmc71.c b/src/lib/ip/gmc71.c
new file mode 100644
index 0000000..8b01212
--- /dev/null
+++ b/src/lib/ip/gmc71.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gmc71_bits.i"
+
+static const struct umr_reg gmc71_registers[] = {
+#include "gmc71_regs.i"
+};
+
+struct umr_ip_block *umr_create_gmc71(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gmc71";
+	ip->no_regs = sizeof(gmc71_registers)/sizeof(gmc71_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gmc71_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, gmc71_registers, sizeof(gmc71_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gmc71_bits.i b/src/lib/ip/gmc71_bits.i
new file mode 100644
index 0000000..5802bc9
--- /dev/null
+++ b/src/lib/ip/gmc71_bits.i
@@ -0,0 +1,10042 @@
+static struct umr_bitfield ixMC_TSM_DEBUG_GCNT[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_FLAG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_ST01[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_ST23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_ST45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BKPT[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_20[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_21[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_22[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_23[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_24[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_25[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_26[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_27[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_28[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_29[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_30[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_31[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_MISC[] = {
+	 { "FLAG", 0, 7, &umr_bitfield_default },
+	 { "NCNT_RD", 8, 11, &umr_bitfield_default },
+	 { "NCNT_WR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_2[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_32[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_33[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_34[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_35[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_36[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_37[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_38[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_39[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_40[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_41[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_42[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_43[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_44[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_45[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_46[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_47[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT0[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_3[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_48[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_49[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_50[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_51[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_52[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_53[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_54[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_55[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_56[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_57[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_58[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_59[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_60[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_61[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_62[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_63[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT1[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_4[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_64[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_65[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_66[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_67[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_68[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_69[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_70[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_71[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_72[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_73[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_74[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_75[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_76[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_77[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_78[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_79[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT2[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_5[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_80[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL[] = {
+	 { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default },
+	 { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default },
+	 { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default },
+	 { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default },
+	 { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default },
+	 { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default },
+	 { "L2_CACHE_4K_SWAP_TAG_INDEX_LSBS", 26, 27, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL2[] = {
+	 { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_VMID_MODE", 23, 25, &umr_bitfield_default },
+	 { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default },
+	 { "PDE_CACHE_EFFECTIVE_SIZE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL3[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default },
+	 { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default },
+	 { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default },
+	 { "PDE_CACHE_FORCE_MISS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_STATUS[] = {
+	 { "L2_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = {
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = {
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = {
+	 { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default },
+	 { "DUMMY_PAGE_COMPARE_MASK", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR[] = {
+	 { "DUMMY_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL2[] = {
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL2[] = {
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_81[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_REQUEST[] = {
+	 { "INVALIDATE_DOMAIN_0", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_1", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_2", 2, 2, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_3", 3, 3, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_4", 4, 4, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_5", 5, 5, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_6", 6, 6, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_7", 7, 7, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_8", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_9", 9, 9, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_10", 10, 10, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_11", 11, 11, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_12", 12, 12, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_13", 13, 13, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_14", 14, 14, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_RESPONSE[] = {
+	 { "DOMAIN_INVALIDATED_0", 0, 0, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_1", 1, 1, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_2", 2, 2, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_3", 3, 3, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_4", 4, 4, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_5", 5, 5, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_6", 6, 6, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_7", 7, 7, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_8", 8, 8, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_9", 9, 9, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_10", 10, 10, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_11", 11, 11, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_12", 12, 12, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_13", 13, 13, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_14", 14, 14, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_82[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_83[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_CNTL[] = {
+	 { "CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS", 0, 0, &umr_bitfield_default },
+	 { "TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_STORE_INVALID_ENTRIES", 2, 2, &umr_bitfield_default },
+	 { "L1_TLB_STORE_INVALID_ENTRIES", 3, 3, &umr_bitfield_default },
+	 { "CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS", 4, 4, &umr_bitfield_default },
+	 { "TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+	 { "MASK_PDE0_FAULT", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = {
+	 { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 20, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 20, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[] = {
+	 { "NAME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[] = {
+	 { "NAME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_84[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_FAULT_CLIENT_ID[] = {
+	 { "MEMORY_CLIENT", 0, 8, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_MASK", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_85[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_86[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DEBUG[] = {
+	 { "FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_87[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CG[] = {
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKA[] = {
+	 { "BANK_SELECT_MASK", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKB[] = {
+	 { "BANK_SELECT_MASK", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[] = {
+	 { "PHYSICAL_PAGE_OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_88[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_89[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_90[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_91[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_92[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_93[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_94[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_95[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT3[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_6[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_96[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_97[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_98[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_99[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_100[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_101[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_102[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_103[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_104[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_105[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_106[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_107[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_108[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_109[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_110[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_111[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT4[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_7[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_112[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_113[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_114[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_115[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_116[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_117[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_118[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_119[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_120[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_121[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_122[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_123[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_124[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_125[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERF_MON_CNTL0_ECC[] = {
+	 { "ALLOW_WRAP", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_126[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_127[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT5[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_8[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_128[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG[] = {
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCDS_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCDT_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCDU_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCDV_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MCC_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHMAP[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "NOOFCHAN", 12, 15, &umr_bitfield_default },
+	 { "CHAN3", 16, 19, &umr_bitfield_default },
+	 { "CHAN4", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHREMAP[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "CHAN3", 12, 15, &umr_bitfield_default },
+	 { "CHAN4", 16, 19, &umr_bitfield_default },
+	 { "CHAN5", 20, 23, &umr_bitfield_default },
+	 { "CHAN6", 24, 27, &umr_bitfield_default },
+	 { "CHAN7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "SH", 4, 7, &umr_bitfield_default },
+	 { "IA", 8, 11, &umr_bitfield_default },
+	 { "ACPG", 12, 15, &umr_bitfield_default },
+	 { "ACPO", 16, 19, &umr_bitfield_default },
+	 { "ISP", 20, 23, &umr_bitfield_default },
+	 { "XDMAM", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "SH", 4, 7, &umr_bitfield_default },
+	 { "ACPG", 8, 11, &umr_bitfield_default },
+	 { "ACPO", 12, 15, &umr_bitfield_default },
+	 { "ISP", 16, 19, &umr_bitfield_default },
+	 { "XDMA", 20, 23, &umr_bitfield_default },
+	 { "XDMAM", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_SYS[] = {
+	 { "RLC", 0, 3, &umr_bitfield_default },
+	 { "VMC", 4, 7, &umr_bitfield_default },
+	 { "SDMA1", 8, 11, &umr_bitfield_default },
+	 { "DMIF", 12, 15, &umr_bitfield_default },
+	 { "MCIF", 16, 19, &umr_bitfield_default },
+	 { "SMU", 20, 23, &umr_bitfield_default },
+	 { "VCE", 24, 27, &umr_bitfield_default },
+	 { "VCEU", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_SYS[] = {
+	 { "IH", 0, 3, &umr_bitfield_default },
+	 { "MCIF", 4, 7, &umr_bitfield_default },
+	 { "RLC", 8, 11, &umr_bitfield_default },
+	 { "SAM", 12, 15, &umr_bitfield_default },
+	 { "SMU", 16, 19, &umr_bitfield_default },
+	 { "SDMA1", 20, 23, &umr_bitfield_default },
+	 { "VCE", 24, 27, &umr_bitfield_default },
+	 { "VCEU", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_OTH[] = {
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "SDMA0", 4, 7, &umr_bitfield_default },
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "UVD_EXT1", 24, 27, &umr_bitfield_default },
+	 { "SAM", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_OTH[] = {
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "SDMA0", 4, 7, &umr_bitfield_default },
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "XDP", 24, 27, &umr_bitfield_default },
+	 { "UVD_EXT1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_LOCATION[] = {
+	 { "FB_BASE", 0, 15, &umr_bitfield_default },
+	 { "FB_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_TOP[] = {
+	 { "AGP_TOP", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BOT[] = {
+	 { "AGP_BOT", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BASE[] = {
+	 { "AGP_BASE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_129[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_CNTL[] = {
+	 { "DC_WRITE_HIT_REGION_0_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_1_MODE", 2, 3, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_2_MODE", 4, 5, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_3_MODE", 6, 7, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_LOCAL", 8, 8, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_SYSTEM", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = {
+	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L1_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
+	 { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default },
+	 { "ECO_BITS", 7, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_OFFSET[] = {
+	 { "FB_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_STEERING[] = {
+	 { "DEFAULT_STEERING", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHREMAP2[] = {
+	 { "CHAN8", 0, 3, &umr_bitfield_default },
+	 { "CHAN9", 4, 7, &umr_bitfield_default },
+	 { "CHAN10", 8, 11, &umr_bitfield_default },
+	 { "CHAN11", 12, 15, &umr_bitfield_default },
+	 { "CHAN12", 16, 19, &umr_bitfield_default },
+	 { "CHAN13", 20, 23, &umr_bitfield_default },
+	 { "CHAN14", 24, 27, &umr_bitfield_default },
+	 { "CHAN15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_130[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCD6_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCD7_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MC_RD_ENABLE_SUB", 11, 11, &umr_bitfield_default },
+	 { "ARB0_WR_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "ARB1_WR_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "MCD_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCD6_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCD7_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MC_RD_ENABLE_SUB", 11, 11, &umr_bitfield_default },
+	 { "INDEX", 13, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MEM_POWER_LS[] = {
+	 { "LS_SETUP", 0, 5, &umr_bitfield_default },
+	 { "LS_HOLD", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_BLACKOUT_CNTL[] = {
+	 { "BLACKOUT_MODE", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_POWER[] = {
+	 { "SRBM_GATE_OVERRIDE", 2, 2, &umr_bitfield_default },
+	 { "PM_BLACKOUT_CNTL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_HUB_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_VM_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_131[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_SIP_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_STATUS[] = {
+	 { "OUTSTANDING_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDREQ", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDRET", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRREQ", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRRET", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_READ", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_WRITE", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_READ", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_WRITE", 9, 9, &umr_bitfield_default },
+	 { "RPB_BUSY", 10, 10, &umr_bitfield_default },
+	 { "WRITE_DEADLOCK_WARNING", 11, 11, &umr_bitfield_default },
+	 { "READ_DEADLOCK_WARNING", 12, 12, &umr_bitfield_default },
+	 { "GFX_BUSY", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_OVERRIDE[] = {
+	 { "IDLE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_FRAMING[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CNTL[] = {
+	 { "JUMPAHEAD_GBL0", 1, 1, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_INTERNAL", 3, 3, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_REG", 5, 12, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_INTERNAL", 15, 15, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 16, 16, &umr_bitfield_default },
+	 { "LCLWRREQ_BYPASS", 17, 17, &umr_bitfield_default },
+	 { "DISP_WAIT_EOP", 18, 18, &umr_bitfield_default },
+	 { "MCD_WAIT_EOP", 19, 19, &umr_bitfield_default },
+	 { "SIP_WAIT_EOP", 20, 20, &umr_bitfield_default },
+	 { "UVD_VCE_WRITE_PRI_EN", 21, 21, &umr_bitfield_default },
+	 { "WRITE_PRI_EN", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ERR[] = {
+	 { "MGPU1_TARG_SYS", 0, 0, &umr_bitfield_default },
+	 { "MGPU2_TARG_SYS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RDRET", 1, 17, &umr_bitfield_default },
+	 { "WRREQ", 18, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_STATUS[] = {
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDS_RD_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDT_RD_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDU_RD_AVAIL", 7, 7, &umr_bitfield_default },
+	 { "MCDV_RD_AVAIL", 8, 8, &umr_bitfield_default },
+	 { "MCDW_WR_AVAIL", 9, 9, &umr_bitfield_default },
+	 { "MCDX_WR_AVAIL", 10, 10, &umr_bitfield_default },
+	 { "MCDY_WR_AVAIL", 11, 11, &umr_bitfield_default },
+	 { "MCDZ_WR_AVAIL", 12, 12, &umr_bitfield_default },
+	 { "MCDS_WR_AVAIL", 13, 13, &umr_bitfield_default },
+	 { "MCDT_WR_AVAIL", 14, 14, &umr_bitfield_default },
+	 { "MCDU_WR_AVAIL", 15, 15, &umr_bitfield_default },
+	 { "MCDV_WR_AVAIL", 16, 16, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 17, 17, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 18, 18, &umr_bitfield_default },
+	 { "GBL0_BYPASS_STOR_FULL", 19, 19, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 20, 20, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 21, 21, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_STATUS[] = {
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDS_RD_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDT_RD_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDU_RD_AVAIL", 7, 7, &umr_bitfield_default },
+	 { "MCDV_RD_AVAIL", 8, 8, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 9, 9, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 10, 10, &umr_bitfield_default },
+	 { "GBL0_BYPASS_STOR_FULL", 11, 11, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 12, 12, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 13, 13, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 14, 14, &umr_bitfield_default },
+	 { "PWRXPRESS_ERR", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_STATUS[] = {
+	 { "MCDW_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDX_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDY_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDS_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDT_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDU_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDV_AVAIL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CNTL[] = {
+	 { "REMOTE_BLACKOUT", 0, 0, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL0", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 3, 3, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCDW_STALL_MODE", 5, 5, &umr_bitfield_default },
+	 { "MCDX_STALL_MODE", 6, 6, &umr_bitfield_default },
+	 { "MCDY_STALL_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCDZ_STALL_MODE", 8, 8, &umr_bitfield_default },
+	 { "MCDS_STALL_MODE", 9, 9, &umr_bitfield_default },
+	 { "MCDT_STALL_MODE", 10, 10, &umr_bitfield_default },
+	 { "MCDU_STALL_MODE", 11, 11, &umr_bitfield_default },
+	 { "MCDV_STALL_MODE", 12, 12, &umr_bitfield_default },
+	 { "BREAK_HDP_DEADLOCK", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_REG", 14, 20, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 22, 22, &umr_bitfield_default },
+	 { "PWRXPRESS_MODE", 23, 23, &umr_bitfield_default },
+	 { "ACPG_HP_TO_MCD_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "GBL0_PRI_ENABLE", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_CNTL[] = {
+	 { "JUMPAHEAD", 0, 0, &umr_bitfield_default },
+	 { "BP", 1, 20, &umr_bitfield_default },
+	 { "BP_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_REG", 22, 29, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 30, 30, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS[] = {
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_132[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS2[] = {
+	 { "STOR0_PRI", 0, 7, &umr_bitfield_default },
+	 { "STOR1_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL0[] = {
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 17, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL1[] = {
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 17, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS[] = {
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS2[] = {
+	 { "STOR0_PRI", 0, 7, &umr_bitfield_default },
+	 { "STOR1_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_SHARED_DAGB_DLY[] = {
+	 { "DLY", 0, 5, &umr_bitfield_default },
+	 { "CLI", 16, 21, &umr_bitfield_default },
+	 { "POS", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_IDLE_STATUS[] = {
+	 { "OUTSTANDING_GFX_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_GFX_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_READ", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_WRITE", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_READ", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_WRITE", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_READ", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_WRITE", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_READ", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_WRITE", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_READ", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_WRITE", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_READ", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_WRITE", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_READ", 14, 14, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_WRITE", 15, 15, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_READ", 16, 16, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_WRITE", 17, 17, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_READ", 18, 18, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_WRITE", 19, 19, &umr_bitfield_default },
+	 { "OUTSTANDING_IA_READ", 20, 20, &umr_bitfield_default },
+	 { "OUTSTANDING_IA_WRITE", 21, 21, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_READ", 22, 22, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_WRITE", 23, 23, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_READ", 24, 24, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_WRITE", 25, 25, &umr_bitfield_default },
+	 { "OUTSTANDING_CP_READ", 26, 26, &umr_bitfield_default },
+	 { "OUTSTANDING_CP_WRITE", 27, 27, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_READ", 28, 28, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_WRITE", 29, 29, &umr_bitfield_default },
+	 { "OUTSTANDING_ISP_READ", 30, 30, &umr_bitfield_default },
+	 { "OUTSTANDING_ISP_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPG_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BYPASS_GBL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+	 { "HDP_PRIORITY_TIME", 17, 23, &umr_bitfield_default },
+	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BYPASS_GBL1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+	 { "HDP_PRIORITY_TIME", 17, 23, &umr_bitfield_default },
+	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_BYPASS_GBL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH3[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_IA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_133[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_IA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDW[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDX[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDY[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDZ[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SIP[] = {
+	 { "ASK_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "DUMMY", 7, 7, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL0[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL1[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SMU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SDMA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_HDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SDMA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_RLC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SEM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_134[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UVD[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_IA[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCEU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDW[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDX[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDY[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDZ[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SIP[] = {
+	 { "STALL_MODE", 0, 1, &umr_bitfield_default },
+	 { "ASK_CREDITS", 2, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SDMA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_135[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCE[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_IH[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_RLC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SEM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SMU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UVD[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_HDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SDMA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDW[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDX[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDY[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDZ[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCEU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_136[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMA[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_XDMAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPO[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ACPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ACPO[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CPC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CPF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CPC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CPF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_137[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_138[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_139[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_140[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_141[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR4[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR5[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR6[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR7[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR8[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR9[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP0[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP1[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP2[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP3[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP4[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_142[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP5[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP6[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP7[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP8[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP9[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP0[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP1[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP2[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP3[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG0[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG1[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG2[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG3[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG4[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG5[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG6[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_143[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG7[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG8[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG9[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG10[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG11[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG12[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG13[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG14[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG15[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG16[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG17[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG18[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG19[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_LB_ADDR[] = {
+	 { "CMP0", 0, 9, &umr_bitfield_default },
+	 { "MASK0", 10, 19, &umr_bitfield_default },
+	 { "CMP1", 20, 25, &umr_bitfield_default },
+	 { "MASK1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_HST[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT6[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_9[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_144[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_SID[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_STS[] = {
+	 { "PBUF_VLD", 0, 15, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 16, 22, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 23, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_CFG[] = {
+	 { "TIMEOUT", 0, 15, &umr_bitfield_default },
+	 { "HST_MAX", 16, 17, &umr_bitfield_default },
+	 { "SID_MAX", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_CFG[] = {
+	 { "ADDR_SIZE", 0, 3, &umr_bitfield_default },
+	 { "SEND_BAR", 4, 5, &umr_bitfield_default },
+	 { "SNOOP", 6, 6, &umr_bitfield_default },
+	 { "SEND_DIS", 7, 7, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 8, 8, &umr_bitfield_default },
+	 { "UPDATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "REGBAR_FROM_SYSBAR", 10, 10, &umr_bitfield_default },
+	 { "RD_EN", 11, 11, &umr_bitfield_default },
+	 { "ATC_TRANSLATED", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR0[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR1[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR2[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR3[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR4[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR5[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR6[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR7[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_SETUP[] = {
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DEBUG[] = {
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "HOST_FLUSH", 8, 11, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_ABOVE[] = {
+	 { "EN", 0, 7, &umr_bitfield_default },
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_BELOW[] = {
+	 { "EN", 0, 7, &umr_bitfield_default },
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_145[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR4[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR5[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR6[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR7[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR8[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR9[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLK_GAT[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG[] = {
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "MC_WRRET_ASK", 8, 15, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 16, 22, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_SEL", 23, 23, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_VAL", 24, 24, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_SEL", 25, 25, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_VAL", 26, 26, &umr_bitfield_default },
+	 { "XSP_SNOOP_SEL", 27, 28, &umr_bitfield_default },
+	 { "XSP_SNOOP_VAL", 29, 29, &umr_bitfield_default },
+	 { "XSP_ORDERING_SEL", 30, 30, &umr_bitfield_default },
+	 { "XSP_ORDERING_VAL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_146[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_STS[] = {
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 8, 14, &umr_bitfield_default },
+	 { "HOP_DATA_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "HOP_ATTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "CNS_BUF_FULL", 17, 17, &umr_bitfield_default },
+	 { "CNS_BUF_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RPB_RDREQ_CRD", 19, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PIPE_STS[] = {
+	 { "WCB_ANY_PBUF", 0, 0, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 1, 7, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 8, 14, &umr_bitfield_default },
+	 { "WCB_HST_RD_PTR_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "WCB_SID_RD_PTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "WCB_HST_REQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "WCB_SID_REQ_FIFO_FULL", 18, 18, &umr_bitfield_default },
+	 { "WCB_HST_REQ_OBUF_FULL", 19, 19, &umr_bitfield_default },
+	 { "WCB_SID_REQ_OBUF_FULL", 20, 20, &umr_bitfield_default },
+	 { "WCB_HST_DATA_OBUF_FULL", 21, 21, &umr_bitfield_default },
+	 { "WCB_SID_DATA_OBUF_FULL", 22, 22, &umr_bitfield_default },
+	 { "RET_BUF_FULL", 23, 23, &umr_bitfield_default },
+	 { "XPB_CLK_BUSY_BITS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_SUB_CTRL[] = {
+	 { "WRREQ_BYPASS_XPB", 0, 0, &umr_bitfield_default },
+	 { "STALL_CNS_RTR_REQ", 1, 1, &umr_bitfield_default },
+	 { "STALL_RTR_RPB_WRREQ", 2, 2, &umr_bitfield_default },
+	 { "STALL_RTR_MAP_REQ", 3, 3, &umr_bitfield_default },
+	 { "STALL_MAP_WCB_REQ", 4, 4, &umr_bitfield_default },
+	 { "STALL_WCB_SID_REQ", 5, 5, &umr_bitfield_default },
+	 { "STALL_MC_XSP_REQ_SEND", 6, 6, &umr_bitfield_default },
+	 { "STALL_WCB_HST_REQ", 7, 7, &umr_bitfield_default },
+	 { "STALL_HST_HOP_REQ", 8, 8, &umr_bitfield_default },
+	 { "STALL_XPB_RPB_REQ_ATTR", 9, 9, &umr_bitfield_default },
+	 { "RESET_CNS", 10, 10, &umr_bitfield_default },
+	 { "RESET_RTR", 11, 11, &umr_bitfield_default },
+	 { "RESET_RET", 12, 12, &umr_bitfield_default },
+	 { "RESET_MAP", 13, 13, &umr_bitfield_default },
+	 { "RESET_WCB", 14, 14, &umr_bitfield_default },
+	 { "RESET_HST", 15, 15, &umr_bitfield_default },
+	 { "RESET_HOP", 16, 16, &umr_bitfield_default },
+	 { "RESET_SID", 17, 17, &umr_bitfield_default },
+	 { "RESET_SRB", 18, 18, &umr_bitfield_default },
+	 { "RESET_CGR", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[] = {
+	 { "ALTER_FLUSH_NUM", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PERF_KNOBS[] = {
+	 { "CNS_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+	 { "WCB_HST_FIFO_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "WCB_SID_FIFO_DEPTH", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY_W1C[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MISC_CFG[] = {
+	 { "FIELDNAME0", 0, 7, &umr_bitfield_default },
+	 { "FIELDNAME1", 8, 15, &umr_bitfield_default },
+	 { "FIELDNAME2", 16, 23, &umr_bitfield_default },
+	 { "FIELDNAME3", 24, 30, &umr_bitfield_default },
+	 { "TRIGGERNAME", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG20[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG21[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG22[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG23[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG24[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG25[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG26[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG27[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_147[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG28[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG29[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG30[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG31[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG2[] = {
+	 { "RPB_RDREQ_CRD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA_RD[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG32[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG33[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG34[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG35[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG36[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_148[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CONF[] = {
+	 { "XPB_PCIE_ORDER", 15, 15, &umr_bitfield_default },
+	 { "RPB_RD_PCIE_ORDER", 16, 16, &umr_bitfield_default },
+	 { "RPB_WR_PCIE_ORDER", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_IF_CONF[] = {
+	 { "RPB_BIF_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_WRRET_ASK", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_DBG1[] = {
+	 { "RPB_BIF_OUTSTANDING_RD", 0, 7, &umr_bitfield_default },
+	 { "RPB_BIF_OUTSTANDING_RD_32B", 8, 19, &umr_bitfield_default },
+	 { "DEBUG_BITS", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_149[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_EFF_CNTL[] = {
+	 { "WR_LAZY_TIMER", 0, 7, &umr_bitfield_default },
+	 { "RD_LAZY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_ARB_CNTL[] = {
+	 { "WR_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "RD_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "ATC_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_BIF_CNTL[] = {
+	 { "ARB_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "XPB_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_COMBINE_CNTL[] = {
+	 { "WC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "WC_MAX_PACKET_SIZE", 1, 2, &umr_bitfield_default },
+	 { "WC_FLUSH_TIMER", 3, 6, &umr_bitfield_default },
+	 { "WC_ALIGN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_RD_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_WR[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "UPDATE_MODE", 8, 8, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 9, 10, &umr_bitfield_default },
+	 { "READ_QUEUE", 11, 12, &umr_bitfield_default },
+	 { "UPDATE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_RD[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 8, 9, &umr_bitfield_default },
+	 { "READ_QUEUE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 1, &umr_bitfield_default },
+	 { "CLEAR_SELECTED_PERF_COUNTER", 2, 2, &umr_bitfield_default },
+	 { "CLEAR_ALL_PERF_COUNTERS", 3, 3, &umr_bitfield_default },
+	 { "STOP_ON_COUNTER_SATURATION", 4, 4, &umr_bitfield_default },
+	 { "ENABLE_PERF_COUNTERS", 5, 8, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_0", 9, 13, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_1", 14, 18, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_2", 19, 23, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_3", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_STATUS[] = {
+	 { "PERFORMANCE_COUNTER_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX_DATA[] = {
+	 { "WRITE_ENTRIES", 0, 15, &umr_bitfield_default },
+	 { "READ_ENTRIES", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_TCI_CNTL[] = {
+	 { "TCI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TCI_POLICY", 1, 2, &umr_bitfield_default },
+	 { "TCI_VOL", 3, 3, &umr_bitfield_default },
+	 { "TCI_VMID", 4, 7, &umr_bitfield_default },
+	 { "TCI_REQ_CREDITS", 8, 15, &umr_bitfield_default },
+	 { "TCI_MAX_WRITES", 16, 23, &umr_bitfield_default },
+	 { "TCI_MAX_READS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_150[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_XTRA_ENABLE[] = {
+	 { "CB1_RD", 0, 0, &umr_bitfield_default },
+	 { "CB1_WR", 1, 1, &umr_bitfield_default },
+	 { "DB1_RD", 2, 2, &umr_bitfield_default },
+	 { "DB1_WR", 3, 3, &umr_bitfield_default },
+	 { "TC2_RD", 4, 4, &umr_bitfield_default },
+	 { "ARB_DBG", 8, 11, &umr_bitfield_default },
+	 { "TC2_WR", 12, 12, &umr_bitfield_default },
+	 { "CB0_CONNECT_CNTL", 13, 14, &umr_bitfield_default },
+	 { "DB0_CONNECT_CNTL", 15, 16, &umr_bitfield_default },
+	 { "CB1_CONNECT_CNTL", 17, 18, &umr_bitfield_default },
+	 { "DB1_CONNECT_CNTL", 19, 20, &umr_bitfield_default },
+	 { "TC0_CONNECT_CNTL", 21, 22, &umr_bitfield_default },
+	 { "TC1_CONNECT_CNTL", 23, 24, &umr_bitfield_default },
+	 { "CB0_CID_CNTL_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DB0_CID_CNTL_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CB1_CID_CNTL_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "DB1_CID_CNTL_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "TC2_REPAIR_ENABLE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_MC_MAX_CHANNEL[] = {
+	 { "NOOFCHAN", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG[] = {
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
+	 { "INDEX", 6, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_151[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CNTL[] = {
+	 { "IGNOREPM", 2, 2, &umr_bitfield_default },
+	 { "EXEMPTPM", 3, 3, &umr_bitfield_default },
+	 { "GFX_IDLE_OVERRIDE", 4, 5, &umr_bitfield_default },
+	 { "MCD_SRBM_MASK_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "CNTR_CHMAP_MODE", 7, 8, &umr_bitfield_default },
+	 { "REMOTE_RB_CONNECT_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_VM[] = {
+	 { "READ_ALL", 0, 5, &umr_bitfield_default },
+	 { "WRITE_ALL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_RD[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "READ_HUB", 8, 15, &umr_bitfield_default },
+	 { "READ_PRI", 16, 23, &umr_bitfield_default },
+	 { "LCL_PRI", 24, 24, &umr_bitfield_default },
+	 { "HUB_PRI", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_WR[] = {
+	 { "WRITE_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_HUB", 8, 15, &umr_bitfield_default },
+	 { "WRITE_PRI", 16, 23, &umr_bitfield_default },
+	 { "HUB_PRI", 24, 24, &umr_bitfield_default },
+	 { "LCL_PRI", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_CNTL[] = {
+	 { "JUMP_AHEAD", 0, 0, &umr_bitfield_default },
+	 { "CENTER_RD_MAX_BURST", 1, 4, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 5, 5, &umr_bitfield_default },
+	 { "CENTER_WR_MAX_BURST", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS[] = {
+	 { "REMRDRET", 0, 5, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_LP", 12, 17, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_HP", 18, 23, &umr_bitfield_default },
+	 { "CNTR_RD_LCL", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_RET_MODE[] = {
+	 { "INORDER_RD", 0, 0, &umr_bitfield_default },
+	 { "INORDER_WR", 1, 1, &umr_bitfield_default },
+	 { "REMPRI_RD", 2, 2, &umr_bitfield_default },
+	 { "REMPRI_WR", 3, 3, &umr_bitfield_default },
+	 { "LCLPRI_RD", 4, 4, &umr_bitfield_default },
+	 { "LCLPRI_WR", 5, 5, &umr_bitfield_default },
+	 { "RDRET_STALL_EN", 6, 6, &umr_bitfield_default },
+	 { "RDRET_STALL_THRESHOLD", 7, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_DLY[] = {
+	 { "DLY", 0, 4, &umr_bitfield_default },
+	 { "CLI", 16, 21, &umr_bitfield_default },
+	 { "POS", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_REMREQ[] = {
+	 { "READ_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "WRITE_CREDITS", 7, 13, &umr_bitfield_default },
+	 { "CREDITS_ENABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS_WR[] = {
+	 { "CNTR_WR_HUB", 0, 5, &umr_bitfield_default },
+	 { "CNTR_WR_LCL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_RD_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_LOCAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_152[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_WR_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_LOCAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_CB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_DB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_HUB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_CB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_DB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_HUB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_XBAR[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_LCL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_LCL[] = {
+	 { "CB0", 12, 15, &umr_bitfield_default },
+	 { "CBCMASK0", 16, 19, &umr_bitfield_default },
+	 { "CBFMASK0", 20, 23, &umr_bitfield_default },
+	 { "DB0", 24, 27, &umr_bitfield_default },
+	 { "DBHTILE0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_LCL[] = {
+	 { "CB0", 0, 3, &umr_bitfield_default },
+	 { "CBCMASK0", 4, 7, &umr_bitfield_default },
+	 { "CBFMASK0", 8, 11, &umr_bitfield_default },
+	 { "DB0", 12, 15, &umr_bitfield_default },
+	 { "DBHTILE0", 16, 19, &umr_bitfield_default },
+	 { "SX0", 20, 23, &umr_bitfield_default },
+	 { "CBIMMED0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_CNTL2[] = {
+	 { "CID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_153[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_RSLT2[] = {
+	 { "CB_RD_BUSY", 6, 6, &umr_bitfield_default },
+	 { "DB_RD_BUSY", 7, 7, &umr_bitfield_default },
+	 { "TC0_RD_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VC0_RD_BUSY", 9, 9, &umr_bitfield_default },
+	 { "TC1_RD_BUSY", 10, 10, &umr_bitfield_default },
+	 { "VC1_RD_BUSY", 11, 11, &umr_bitfield_default },
+	 { "CB_WR_BUSY", 12, 12, &umr_bitfield_default },
+	 { "DB_WR_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SX_WR_BUSY", 14, 14, &umr_bitfield_default },
+	 { "TC2_RD_BUSY", 15, 15, &umr_bitfield_default },
+	 { "TC0_WR_BUSY", 16, 16, &umr_bitfield_default },
+	 { "TC1_WR_BUSY", 17, 17, &umr_bitfield_default },
+	 { "TC2_WR_BUSY", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_RD_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_WR_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_VM_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_154[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_155[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_CNTL[] = {
+	 { "RESET_RD_GROUP0", 0, 0, &umr_bitfield_default },
+	 { "RESET_RD_GROUP1", 1, 1, &umr_bitfield_default },
+	 { "RESET_RD_GROUP2", 2, 2, &umr_bitfield_default },
+	 { "RESET_RD_GROUP3", 3, 3, &umr_bitfield_default },
+	 { "RESET_RD_GROUP4", 4, 4, &umr_bitfield_default },
+	 { "RESET_RD_GROUP5", 5, 5, &umr_bitfield_default },
+	 { "RESET_RD_GROUP6", 6, 6, &umr_bitfield_default },
+	 { "RESET_RD_GROUP7", 7, 7, &umr_bitfield_default },
+	 { "RESET_WR_GROUP0", 8, 8, &umr_bitfield_default },
+	 { "RESET_WR_GROUP1", 9, 9, &umr_bitfield_default },
+	 { "RESET_WR_GROUP2", 10, 10, &umr_bitfield_default },
+	 { "RESET_WR_GROUP3", 11, 11, &umr_bitfield_default },
+	 { "RESET_WR_GROUP4", 12, 12, &umr_bitfield_default },
+	 { "RESET_WR_GROUP5", 13, 13, &umr_bitfield_default },
+	 { "RESET_WR_GROUP6", 14, 14, &umr_bitfield_default },
+	 { "RESET_WR_GROUP7", 15, 15, &umr_bitfield_default },
+	 { "AGE_LOW_RATE_RD", 16, 18, &umr_bitfield_default },
+	 { "AGE_LOW_RATE_WR", 19, 21, &umr_bitfield_default },
+	 { "TIMER_STALL_RD", 22, 22, &umr_bitfield_default },
+	 { "TIMER_STALL_WR", 23, 23, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT_RD", 24, 24, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT_WR", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_156[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS2[] = {
+	 { "ACP_WR", 0, 7, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_EN_RD", 8, 8, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_EN_WR", 9, 9, &umr_bitfield_default },
+	 { "ACP_RDRET_URG", 10, 10, &umr_bitfield_default },
+	 { "HDP_RDRET_URG", 11, 11, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_MONITOR_RD", 12, 12, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_MONITOR_WR", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_FED_CNTL[] = {
+	 { "MODE", 0, 1, &umr_bitfield_default },
+	 { "WR_ERR", 2, 3, &umr_bitfield_default },
+	 { "KEEP_POISON_IN_PAGE", 4, 4, &umr_bitfield_default },
+	 { "RDRET_PARITY_NACK", 5, 5, &umr_bitfield_default },
+	 { "USE_LEGACY_NACK", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_RSV", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_STATUS[] = {
+	 { "CORR_STS0", 0, 0, &umr_bitfield_default },
+	 { "UNCORR_STS0", 1, 1, &umr_bitfield_default },
+	 { "FED_STS0", 2, 2, &umr_bitfield_default },
+	 { "RSVD0", 3, 3, &umr_bitfield_default },
+	 { "CORR_STS1", 4, 4, &umr_bitfield_default },
+	 { "UNCORR_STS1", 5, 5, &umr_bitfield_default },
+	 { "FED_STS1", 6, 6, &umr_bitfield_default },
+	 { "RSVD1", 7, 7, &umr_bitfield_default },
+	 { "CORR_CLEAR0", 8, 8, &umr_bitfield_default },
+	 { "UNCORR_CLEAR0", 9, 9, &umr_bitfield_default },
+	 { "FED_CLEAR0", 10, 10, &umr_bitfield_default },
+	 { "RSVD2", 11, 11, &umr_bitfield_default },
+	 { "CORR_CLEAR1", 12, 12, &umr_bitfield_default },
+	 { "UNCORR_CLEAR1", 13, 13, &umr_bitfield_default },
+	 { "FED_CLEAR1", 14, 14, &umr_bitfield_default },
+	 { "RSVD3", 15, 15, &umr_bitfield_default },
+	 { "RMWRD_CORR_STS0", 16, 16, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_STS0", 17, 17, &umr_bitfield_default },
+	 { "RSVD4", 18, 19, &umr_bitfield_default },
+	 { "RMWRD_CORR_STS1", 20, 20, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_STS1", 21, 21, &umr_bitfield_default },
+	 { "RSVD5", 22, 23, &umr_bitfield_default },
+	 { "RMWRD_CORR_CLEAR0", 24, 24, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_CLEAR0", 25, 25, &umr_bitfield_default },
+	 { "RSVD6", 26, 27, &umr_bitfield_default },
+	 { "RMWRD_CORR_CLEAR1", 28, 28, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_CLEAR1", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_MISC[] = {
+	 { "STREAK_BREAK", 0, 3, &umr_bitfield_default },
+	 { "COL10_HACK", 4, 4, &umr_bitfield_default },
+	 { "CWRD_IN_REPLAY", 5, 5, &umr_bitfield_default },
+	 { "NO_EOB_ALL_WR_IN_REPLAY", 6, 6, &umr_bitfield_default },
+	 { "RMW_LM_WR_STALL", 7, 7, &umr_bitfield_default },
+	 { "RMW_STALL_RELEASE", 8, 8, &umr_bitfield_default },
+	 { "WR_EDC_MASK_REPLAY", 9, 9, &umr_bitfield_default },
+	 { "CWRD_REPLAY_AGAIN", 10, 10, &umr_bitfield_default },
+	 { "WRRDWR_REPLAY_AGAIN", 11, 11, &umr_bitfield_default },
+	 { "ALLOW_RMW_ERR_AFTER_REPLAY", 12, 12, &umr_bitfield_default },
+	 { "DEBUG_RSV", 13, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG[] = {
+	 { "NUM_ERR_BITS", 0, 1, &umr_bitfield_default },
+	 { "DIRECTION", 2, 2, &umr_bitfield_default },
+	 { "DATA_FIELD", 3, 4, &umr_bitfield_default },
+	 { "SW_INJECTION", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG2[] = {
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+	 { "ERR0_START", 8, 15, &umr_bitfield_default },
+	 { "ERR1_START", 16, 23, &umr_bitfield_default },
+	 { "ERR2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERF_CID[] = {
+	 { "CH0", 0, 7, &umr_bitfield_default },
+	 { "CH1", 8, 15, &umr_bitfield_default },
+	 { "CH0_EN", 16, 16, &umr_bitfield_default },
+	 { "CH1_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ECC_MODE", 1, 2, &umr_bitfield_default },
+	 { "PAGE_BIT0", 3, 4, &umr_bitfield_default },
+	 { "EXOR_BANK_SEL", 5, 6, &umr_bitfield_default },
+	 { "NO_GECC_CLI", 7, 10, &umr_bitfield_default },
+	 { "READ_ERR", 11, 13, &umr_bitfield_default },
+	 { "CLOSE_BANK_RMW", 14, 14, &umr_bitfield_default },
+	 { "COLFIFO_WATER", 15, 20, &umr_bitfield_default },
+	 { "WRADDR_CONV", 21, 21, &umr_bitfield_default },
+	 { "RMWRD_UNCOR_POISON", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_CLI[] = {
+	 { "NO_GECC_CLI0", 0, 7, &umr_bitfield_default },
+	 { "NO_GECC_CLI1", 8, 15, &umr_bitfield_default },
+	 { "NO_GECC_CLI2", 16, 23, &umr_bitfield_default },
+	 { "NO_GECC_CLI3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_SWIZ0[] = {
+	 { "A8", 0, 3, &umr_bitfield_default },
+	 { "A9", 4, 7, &umr_bitfield_default },
+	 { "A10", 8, 11, &umr_bitfield_default },
+	 { "A11", 12, 15, &umr_bitfield_default },
+	 { "A12", 16, 19, &umr_bitfield_default },
+	 { "A13", 20, 23, &umr_bitfield_default },
+	 { "A14", 24, 27, &umr_bitfield_default },
+	 { "A15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_SWIZ1[] = {
+	 { "A16", 0, 3, &umr_bitfield_default },
+	 { "A17", 4, 7, &umr_bitfield_default },
+	 { "A18", 8, 11, &umr_bitfield_default },
+	 { "A19", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC3[] = {
+	 { "NO_GECC_EXT_EOB", 0, 0, &umr_bitfield_default },
+	 { "CHAN4_EN", 1, 1, &umr_bitfield_default },
+	 { "CHAN4_ARB_SEL", 2, 2, &umr_bitfield_default },
+	 { "TBD_FIELD", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WCDR_2[] = {
+	 { "WPRE_INC_STEP", 0, 3, &umr_bitfield_default },
+	 { "WPRE_MIN_THRESHOLD", 4, 8, &umr_bitfield_default },
+	 { "DEBUG_0", 9, 9, &umr_bitfield_default },
+	 { "DEBUG_1", 10, 10, &umr_bitfield_default },
+	 { "DEBUG_2", 11, 11, &umr_bitfield_default },
+	 { "DEBUG_3", 12, 12, &umr_bitfield_default },
+	 { "DEBUG_4", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_5", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DATA[] = {
+	 { "PATTERN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_157[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "START_IDLE", 1, 1, &umr_bitfield_default },
+	 { "START_R2W", 2, 3, &umr_bitfield_default },
+	 { "FLUSH_ON_ENTER", 4, 4, &umr_bitfield_default },
+	 { "HARSH_START", 5, 5, &umr_bitfield_default },
+	 { "TPS_HARSH_PRIORITY", 6, 6, &umr_bitfield_default },
+	 { "TWRT_HARSH_PRIORITY", 7, 7, &umr_bitfield_default },
+	 { "BREAK_ON_HARSH", 8, 8, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTRD", 9, 9, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTWR", 10, 10, &umr_bitfield_default },
+	 { "TRAIN_PERIOD", 11, 13, &umr_bitfield_default },
+	 { "START_R2W_RFSH", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_RSV_0", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_RSV_1", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_RSV_2", 17, 17, &umr_bitfield_default },
+	 { "DEBUG_RSV_3", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_RSV_4", 19, 19, &umr_bitfield_default },
+	 { "DEBUG_RSV_5", 20, 20, &umr_bitfield_default },
+	 { "DEBUG_RSV_6", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_RSV_7", 22, 22, &umr_bitfield_default },
+	 { "DEBUG_RSV_8", 23, 23, &umr_bitfield_default },
+	 { "DATA_CNTL", 24, 24, &umr_bitfield_default },
+	 { "NEIGHBOR_BIT", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL1[] = {
+	 { "WINDOW_SIZE", 0, 4, &umr_bitfield_default },
+	 { "WINDOW_UPDATE", 5, 5, &umr_bitfield_default },
+	 { "WINDOW_INC_THRESHOLD", 6, 12, &umr_bitfield_default },
+	 { "WINDOW_DEC_THRESHOLD", 13, 19, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MAX", 20, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MIN", 25, 29, &umr_bitfield_default },
+	 { "WINDOW_UPDATE_COUNT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL2[] = {
+	 { "SAMPLE_CNT", 0, 5, &umr_bitfield_default },
+	 { "PHASE_ADJUST_THRESHOLD", 6, 11, &umr_bitfield_default },
+	 { "PHASE_ADJUST_SIZE", 12, 12, &umr_bitfield_default },
+	 { "FILTER_CNTL", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DEBUG[] = {
+	 { "DEBUG_BYTE_CH0", 0, 1, &umr_bitfield_default },
+	 { "DEBUG_BYTE_CH1", 2, 3, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH0", 4, 11, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH0", 12, 16, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH1", 17, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH1", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CAC_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "READ_WEIGHT", 1, 6, &umr_bitfield_default },
+	 { "WRITE_WEIGHT", 7, 12, &umr_bitfield_default },
+	 { "ALLOW_OVERFLOW", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC2[] = {
+	 { "TCCDL4_BANKBIT3_XOR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT4", 6, 6, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT5", 7, 7, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT6", 8, 8, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT7", 9, 9, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT8", 10, 10, &umr_bitfield_default },
+	 { "POP_IDLE_REPLAY", 11, 11, &umr_bitfield_default },
+	 { "RDRET_NO_REORDERING", 12, 12, &umr_bitfield_default },
+	 { "RDRET_NO_BP", 13, 13, &umr_bitfield_default },
+	 { "RDRET_SEQ_SKID", 14, 17, &umr_bitfield_default },
+	 { "GECC", 18, 18, &umr_bitfield_default },
+	 { "GECC_RST", 19, 19, &umr_bitfield_default },
+	 { "GECC_STATUS", 20, 20, &umr_bitfield_default },
+	 { "TAGFIFO_THRESHOLD", 21, 24, &umr_bitfield_default },
+	 { "WCDR_REPLAY_MASKCNT", 25, 27, &umr_bitfield_default },
+	 { "REPLAY_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "ARB_DEBUG29", 29, 29, &umr_bitfield_default },
+	 { "SEQ_RDY_POP_IDLE", 30, 30, &umr_bitfield_default },
+	 { "TCCDL4_REPLAY_EOB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC[] = {
+	 { "STICKY_RFSH", 0, 0, &umr_bitfield_default },
+	 { "IDLE_RFSH", 1, 1, &umr_bitfield_default },
+	 { "STUTTER_RFSH", 2, 2, &umr_bitfield_default },
+	 { "CHAN_COUPLE", 3, 10, &umr_bitfield_default },
+	 { "HARSHNESS", 11, 18, &umr_bitfield_default },
+	 { "SMART_RDWR_SW", 19, 19, &umr_bitfield_default },
+	 { "CALI_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CALI_RATES", 21, 22, &umr_bitfield_default },
+	 { "DISPURGVLD_NOWRT", 23, 23, &umr_bitfield_default },
+	 { "DISPURG_NOSW2WR", 24, 24, &umr_bitfield_default },
+	 { "DISPURG_STALL", 25, 25, &umr_bitfield_default },
+	 { "DISPURG_THROTTLE", 26, 29, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT", 30, 30, &umr_bitfield_default },
+	 { "ACPURG_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BANKMAP[] = {
+	 { "BANK0", 0, 3, &umr_bitfield_default },
+	 { "BANK1", 4, 7, &umr_bitfield_default },
+	 { "BANK2", 8, 11, &umr_bitfield_default },
+	 { "BANK3", 12, 15, &umr_bitfield_default },
+	 { "RANK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RAMCFG[] = {
+	 { "NOOFBANK", 0, 1, &umr_bitfield_default },
+	 { "NOOFRANKS", 2, 2, &umr_bitfield_default },
+	 { "NOOFROWS", 3, 5, &umr_bitfield_default },
+	 { "NOOFCOLS", 6, 7, &umr_bitfield_default },
+	 { "CHANSIZE", 8, 8, &umr_bitfield_default },
+	 { "RSV_1", 9, 9, &umr_bitfield_default },
+	 { "RSV_2", 10, 10, &umr_bitfield_default },
+	 { "RSV_3", 11, 11, &umr_bitfield_default },
+	 { "NOOFGROUPS", 12, 12, &umr_bitfield_default },
+	 { "RSV_4", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_POP[] = {
+	 { "ENABLE_ARB", 0, 0, &umr_bitfield_default },
+	 { "SPEC_OPEN", 1, 1, &umr_bitfield_default },
+	 { "POP_DEPTH", 2, 5, &umr_bitfield_default },
+	 { "WRDATAINDEX_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "SKID_DEPTH", 12, 14, &umr_bitfield_default },
+	 { "WAIT_AFTER_RFSH", 15, 16, &umr_bitfield_default },
+	 { "QUICK_STOP", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_PAGE", 18, 18, &umr_bitfield_default },
+	 { "ALLOW_EOB_BY_WRRET_STALL", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MINCLKS[] = {
+	 { "READ_CLKS", 0, 7, &umr_bitfield_default },
+	 { "WRITE_CLKS", 8, 15, &umr_bitfield_default },
+	 { "ARB_RW_SWITCH", 16, 16, &umr_bitfield_default },
+	 { "RW_SWITCH_HARSH", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SQM_CNTL[] = {
+	 { "MIN_PENAL", 0, 7, &umr_bitfield_default },
+	 { "DYN_SQM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "SQM_RDY16", 9, 9, &umr_bitfield_default },
+	 { "SQM_RESERVE", 10, 15, &umr_bitfield_default },
+	 { "RATIO", 16, 23, &umr_bitfield_default },
+	 { "RATIO_DEBUG", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_HASH[] = {
+	 { "BANK_XOR_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "COL_XOR", 4, 11, &umr_bitfield_default },
+	 { "ROW_XOR", 12, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2[] = {
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_RD[] = {
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "ACP_HARSH_PRI", 11, 11, &umr_bitfield_default },
+	 { "ACP_OVER_DISP", 12, 12, &umr_bitfield_default },
+	 { "FORCE_ACP_URG", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_158[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_WR[] = {
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "ACP_HARSH_PRI", 11, 11, &umr_bitfield_default },
+	 { "ACP_OVER_DISP", 12, 12, &umr_bitfield_default },
+	 { "FORCE_ACP_URG", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_RD[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_WR[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_RD[] = {
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_WR[] = {
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_RD[] = {
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_WR[] = {
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "URG0", 1, 5, &umr_bitfield_default },
+	 { "URG1", 6, 10, &umr_bitfield_default },
+	 { "ACCUM", 11, 11, &umr_bitfield_default },
+	 { "SINGLE_BANK", 12, 12, &umr_bitfield_default },
+	 { "PUSH_SINGLE_BANK_REFRESH", 13, 13, &umr_bitfield_default },
+	 { "PENDING_RATE_SEL", 14, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_RATE[] = {
+	 { "POWERMODE0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PM_CNTL[] = {
+	 { "OVERRIDE_CGSTATE", 0, 1, &umr_bitfield_default },
+	 { "OVRR_CGRFSH", 2, 2, &umr_bitfield_default },
+	 { "OVRR_CGSQM", 3, 3, &umr_bitfield_default },
+	 { "SRFSH_ON_D1", 4, 4, &umr_bitfield_default },
+	 { "BLKOUT_ON_D1", 5, 5, &umr_bitfield_default },
+	 { "IDLE_ON_D1", 6, 6, &umr_bitfield_default },
+	 { "OVRR_PM", 7, 7, &umr_bitfield_default },
+	 { "OVRR_PM_STATE", 8, 9, &umr_bitfield_default },
+	 { "OVRR_RD", 10, 10, &umr_bitfield_default },
+	 { "OVRR_RD_STATE", 11, 11, &umr_bitfield_default },
+	 { "OVRR_WR", 12, 12, &umr_bitfield_default },
+	 { "OVRR_WR_STATE", 13, 13, &umr_bitfield_default },
+	 { "OVRR_RFSH", 14, 14, &umr_bitfield_default },
+	 { "OVRR_RFSH_STATE", 15, 15, &umr_bitfield_default },
+	 { "RSV_0", 16, 17, &umr_bitfield_default },
+	 { "IDLE_ON_D2", 18, 18, &umr_bitfield_default },
+	 { "IDLE_ON_D3", 19, 19, &umr_bitfield_default },
+	 { "IDLE_CNT", 20, 23, &umr_bitfield_default },
+	 { "RSV_1", 24, 24, &umr_bitfield_default },
+	 { "RSV_2", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_RD_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_WR_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_159[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_RD[] = {
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_WR[] = {
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+	 { "MASKWR_LM_EOB", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REMREQ[] = {
+	 { "RD_WATER", 0, 7, &umr_bitfield_default },
+	 { "WR_WATER", 8, 15, &umr_bitfield_default },
+	 { "WR_MAXBURST_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WR_LAZY_TIMER", 20, 23, &umr_bitfield_default },
+	 { "ENABLE_REMOTE_NACK_REQ", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REPLAY[] = {
+	 { "ENABLE_RD", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_WR", 1, 1, &umr_bitfield_default },
+	 { "WRACK_MODE", 2, 2, &umr_bitfield_default },
+	 { "WAW_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RAW_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "IGNORE_WR_CDC", 5, 5, &umr_bitfield_default },
+	 { "BREAK_ON_STALL", 6, 6, &umr_bitfield_default },
+	 { "BOS_ENABLE_WAIT_CYC", 7, 7, &umr_bitfield_default },
+	 { "BOS_WAIT_CYC", 8, 14, &umr_bitfield_default },
+	 { "NO_PCH_AT_REPLAY_START", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_RD[] = {
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "DISP", 16, 23, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_WR[] = {
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 16, 23, &umr_bitfield_default },
+	 { "WRRET_SEQ_SKID", 24, 27, &umr_bitfield_default },
+	 { "WRRET_BP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_CID[] = {
+	 { "CID_CH0", 0, 7, &umr_bitfield_default },
+	 { "CID_CH1", 8, 15, &umr_bitfield_default },
+	 { "WRITE_CH0", 16, 16, &umr_bitfield_default },
+	 { "WRITE_CH1", 17, 17, &umr_bitfield_default },
+	 { "REALTIME_CH0", 18, 18, &umr_bitfield_default },
+	 { "REALTIME_CH1", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_RSLT0[] = {
+	 { "MAX_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_RSLT1[] = {
+	 { "MAX_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SSM[] = {
+	 { "FORMAT", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CG[] = {
+	 { "CG_ARB_REQ", 0, 7, &umr_bitfield_default },
+	 { "CG_ARB_RESP", 8, 15, &umr_bitfield_default },
+	 { "RSV_0", 16, 23, &umr_bitfield_default },
+	 { "RSV_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WCDR[] = {
+	 { "IDLE_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SEQ_IDLE", 1, 1, &umr_bitfield_default },
+	 { "IDLE_PERIOD", 2, 6, &umr_bitfield_default },
+	 { "IDLE_BURST", 7, 12, &umr_bitfield_default },
+	 { "IDLE_BURST_MODE", 13, 13, &umr_bitfield_default },
+	 { "IDLE_WAKEUP", 14, 15, &umr_bitfield_default },
+	 { "IDLE_DEGLITCH_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "WPRE_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "WPRE_THRESHOLD", 18, 21, &umr_bitfield_default },
+	 { "WPRE_MAX_BURST", 22, 24, &umr_bitfield_default },
+	 { "WPRE_INC_READ", 25, 25, &umr_bitfield_default },
+	 { "WPRE_INC_SKIDIDLE", 26, 26, &umr_bitfield_default },
+	 { "WPRE_INC_SEQIDLE", 27, 27, &umr_bitfield_default },
+	 { "WPRE_TWOPAGE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING_1[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BUSY_STATUS[] = {
+	 { "LM_RD0", 0, 0, &umr_bitfield_default },
+	 { "LM_RD1", 1, 1, &umr_bitfield_default },
+	 { "LM_WR0", 2, 2, &umr_bitfield_default },
+	 { "LM_WR1", 3, 3, &umr_bitfield_default },
+	 { "HM_RD0", 4, 4, &umr_bitfield_default },
+	 { "HM_RD1", 5, 5, &umr_bitfield_default },
+	 { "HM_WR0", 6, 6, &umr_bitfield_default },
+	 { "HM_WR1", 7, 7, &umr_bitfield_default },
+	 { "WDE_RD0", 8, 8, &umr_bitfield_default },
+	 { "WDE_RD1", 9, 9, &umr_bitfield_default },
+	 { "WDE_WR0", 10, 10, &umr_bitfield_default },
+	 { "WDE_WR1", 11, 11, &umr_bitfield_default },
+	 { "POP0", 12, 12, &umr_bitfield_default },
+	 { "POP1", 13, 13, &umr_bitfield_default },
+	 { "TAGFIFO0", 14, 14, &umr_bitfield_default },
+	 { "TAGFIFO1", 15, 15, &umr_bitfield_default },
+	 { "REPLAY0", 16, 16, &umr_bitfield_default },
+	 { "REPLAY1", 17, 17, &umr_bitfield_default },
+	 { "RDRET0", 18, 18, &umr_bitfield_default },
+	 { "RDRET1", 19, 19, &umr_bitfield_default },
+	 { "GECC2_RD0", 20, 20, &umr_bitfield_default },
+	 { "GECC2_RD1", 21, 21, &umr_bitfield_default },
+	 { "GECC2_WR0", 22, 22, &umr_bitfield_default },
+	 { "GECC2_WR1", 23, 23, &umr_bitfield_default },
+	 { "WCDR0", 24, 24, &umr_bitfield_default },
+	 { "WCDR1", 25, 25, &umr_bitfield_default },
+	 { "RTT0", 26, 26, &umr_bitfield_default },
+	 { "RTT1", 27, 27, &umr_bitfield_default },
+	 { "REM_RD0", 28, 28, &umr_bitfield_default },
+	 { "REM_RD1", 29, 29, &umr_bitfield_default },
+	 { "REM_WR0", 30, 30, &umr_bitfield_default },
+	 { "REM_WR1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2_1[] = {
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT7[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_10[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BURST_TIME[] = {
+	 { "STATE0", 0, 4, &umr_bitfield_default },
+	 { "STATE1", 5, 9, &umr_bitfield_default },
+	 { "STATE2", 10, 14, &umr_bitfield_default },
+	 { "STATE3", 15, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CNTL[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "RUN", 1, 1, &umr_bitfield_default },
+	 { "PTR_RST_D0", 2, 2, &umr_bitfield_default },
+	 { "PTR_RST_D1", 3, 3, &umr_bitfield_default },
+	 { "MOP_MODE", 4, 4, &umr_bitfield_default },
+	 { "ADR_MODE", 5, 5, &umr_bitfield_default },
+	 { "DAT_MODE", 6, 6, &umr_bitfield_default },
+	 { "LOOP", 10, 11, &umr_bitfield_default },
+	 { "ENABLE_D0", 12, 12, &umr_bitfield_default },
+	 { "ENABLE_D1", 13, 13, &umr_bitfield_default },
+	 { "LOAD_RTDATA_CH", 14, 14, &umr_bitfield_default },
+	 { "LOOP_CNT", 16, 27, &umr_bitfield_default },
+	 { "DONE", 30, 30, &umr_bitfield_default },
+	 { "LOAD_RTDATA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_AUTO_CNTL[] = {
+	 { "MOP", 0, 1, &umr_bitfield_default },
+	 { "ADR_GEN", 4, 7, &umr_bitfield_default },
+	 { "LFSR_KEY", 8, 23, &umr_bitfield_default },
+	 { "LFSR_RESET", 24, 24, &umr_bitfield_default },
+	 { "ADR_RESET", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DIR_CNTL[] = {
+	 { "MOP", 0, 2, &umr_bitfield_default },
+	 { "EOB", 3, 3, &umr_bitfield_default },
+	 { "MOP_LOAD", 4, 4, &umr_bitfield_default },
+	 { "DATA_LOAD", 5, 5, &umr_bitfield_default },
+	 { "CMD_RTR_D0", 6, 6, &umr_bitfield_default },
+	 { "DAT_RTR_D0", 7, 7, &umr_bitfield_default },
+	 { "CMD_RTR_D1", 8, 8, &umr_bitfield_default },
+	 { "DAT_RTR_D1", 9, 9, &umr_bitfield_default },
+	 { "MOP3", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_SADDR[] = {
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_EADDR[] = {
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_MASK[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_MISMATCH_ADDR[] = {
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD0[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD1[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD2[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD3[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD4[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD5[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD6[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD7[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_MASK[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_EDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_0_S[] = {
+	 { "MCLK_GCK_SEL", 0, 0, &umr_bitfield_default },
+	 { "SCLK_FIELD", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_1_S[] = {
+	 { "SCLK_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_STATUS_S[] = {
+	 { "SEQ0_ARB_DATA_FIFO_FULL", 0, 0, &umr_bitfield_default },
+	 { "SEQ1_ARB_DATA_FIFO_FULL", 1, 1, &umr_bitfield_default },
+	 { "SEQ0_ARB_CMD_FIFO_FULL", 4, 4, &umr_bitfield_default },
+	 { "SEQ1_ARB_CMD_FIFO_FULL", 5, 5, &umr_bitfield_default },
+	 { "SEQ0_RS_DATA_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "SEQ1_RS_DATA_FIFO_EMPTY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_DATAPORT[] = {
+	 { "DATA_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MPLL_OVERRIDE[] = {
+	 { "AD_PLL_RESET_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_RESET_OVERRIDE", 1, 1, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_RESET_OVERRIDE", 2, 2, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_RESET_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_RESET_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "ATGM_CLK_SEL_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "TEST_BYPASS_CLK_EN_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "TEST_BYPASS_CLK_SEL_OVERRIDE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CNTL[] = {
+	 { "MEM_ADDR_MAP_COLS", 0, 1, &umr_bitfield_default },
+	 { "MEM_ADDR_MAP_BANK", 2, 3, &umr_bitfield_default },
+	 { "SAFE_MODE", 4, 5, &umr_bitfield_default },
+	 { "DAT_INV", 6, 6, &umr_bitfield_default },
+	 { "MSK_DF1", 7, 7, &umr_bitfield_default },
+	 { "CHANNEL_DISABLE", 8, 9, &umr_bitfield_default },
+	 { "MSKOFF_DAT_TL", 14, 14, &umr_bitfield_default },
+	 { "MSKOFF_DAT_TH", 15, 15, &umr_bitfield_default },
+	 { "RET_HOLD_EOP", 16, 16, &umr_bitfield_default },
+	 { "BANKGROUP_SIZE", 17, 17, &umr_bitfield_default },
+	 { "BANKGROUP_ENB", 18, 18, &umr_bitfield_default },
+	 { "RTR_OVERRIDE", 19, 19, &umr_bitfield_default },
+	 { "ARB_REQCMD_WMK", 20, 23, &umr_bitfield_default },
+	 { "ARB_REQDAT_WMK", 24, 27, &umr_bitfield_default },
+	 { "ARB_RTDAT_WMK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM[] = {
+	 { "ADR_2CK", 0, 0, &umr_bitfield_default },
+	 { "ADR_MUX", 1, 1, &umr_bitfield_default },
+	 { "ADR_DF1", 2, 2, &umr_bitfield_default },
+	 { "AP8", 3, 3, &umr_bitfield_default },
+	 { "DAT_DF1", 4, 4, &umr_bitfield_default },
+	 { "DQS_DF1", 5, 5, &umr_bitfield_default },
+	 { "DQM_DF1", 6, 6, &umr_bitfield_default },
+	 { "DQM_ACT", 7, 7, &umr_bitfield_default },
+	 { "STB_CNT", 8, 11, &umr_bitfield_default },
+	 { "CKE_DYN", 12, 12, &umr_bitfield_default },
+	 { "CKE_ACT", 13, 13, &umr_bitfield_default },
+	 { "BO4", 14, 14, &umr_bitfield_default },
+	 { "DLL_CLR", 15, 15, &umr_bitfield_default },
+	 { "DLL_CNT", 16, 23, &umr_bitfield_default },
+	 { "DAT_INV", 24, 24, &umr_bitfield_default },
+	 { "INV_ACM", 25, 25, &umr_bitfield_default },
+	 { "ODT_ENB", 26, 26, &umr_bitfield_default },
+	 { "ODT_ACT", 27, 27, &umr_bitfield_default },
+	 { "RST_CTL", 28, 28, &umr_bitfield_default },
+	 { "TRI_MIO_DYN", 29, 29, &umr_bitfield_default },
+	 { "TRI_CKE", 30, 30, &umr_bitfield_default },
+	 { "RDSTRB_RSYC_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM_2[] = {
+	 { "ADR_DDR", 0, 0, &umr_bitfield_default },
+	 { "ADR_DBI", 1, 1, &umr_bitfield_default },
+	 { "ADR_DBI_ACM", 2, 2, &umr_bitfield_default },
+	 { "CMD_QDR", 3, 3, &umr_bitfield_default },
+	 { "DAT_QDR", 4, 4, &umr_bitfield_default },
+	 { "WDAT_EDC", 5, 5, &umr_bitfield_default },
+	 { "RDAT_EDC", 6, 6, &umr_bitfield_default },
+	 { "DQM_EST", 7, 7, &umr_bitfield_default },
+	 { "RD_DQS", 8, 8, &umr_bitfield_default },
+	 { "WR_DQS", 9, 9, &umr_bitfield_default },
+	 { "PLL_EST", 10, 10, &umr_bitfield_default },
+	 { "PLL_CLR", 11, 11, &umr_bitfield_default },
+	 { "DLL_EST", 12, 12, &umr_bitfield_default },
+	 { "BNK_MRS", 13, 13, &umr_bitfield_default },
+	 { "DBI_OVR", 14, 14, &umr_bitfield_default },
+	 { "TRI_CLK", 15, 15, &umr_bitfield_default },
+	 { "PLL_CNT", 16, 23, &umr_bitfield_default },
+	 { "PCH_BNK", 24, 24, &umr_bitfield_default },
+	 { "ADBI_DF1", 25, 25, &umr_bitfield_default },
+	 { "ADBI_ACT", 26, 26, &umr_bitfield_default },
+	 { "DBI_DF1", 27, 27, &umr_bitfield_default },
+	 { "DBI_ACT", 28, 28, &umr_bitfield_default },
+	 { "DBI_EDC_DF1", 29, 29, &umr_bitfield_default },
+	 { "TESTCHIP_EN", 30, 30, &umr_bitfield_default },
+	 { "CS_BY16", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RAS_TIMING[] = {
+	 { "TRCDW", 0, 4, &umr_bitfield_default },
+	 { "TRCDWA", 5, 9, &umr_bitfield_default },
+	 { "TRCDR", 10, 14, &umr_bitfield_default },
+	 { "TRCDRA", 15, 19, &umr_bitfield_default },
+	 { "TRRD", 20, 23, &umr_bitfield_default },
+	 { "TRC", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CAS_TIMING[] = {
+	 { "TNOPW", 0, 1, &umr_bitfield_default },
+	 { "TNOPR", 2, 3, &umr_bitfield_default },
+	 { "TR2W", 4, 8, &umr_bitfield_default },
+	 { "TCCDL", 9, 11, &umr_bitfield_default },
+	 { "TR2R", 12, 15, &umr_bitfield_default },
+	 { "TW2R", 16, 20, &umr_bitfield_default },
+	 { "TCL", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING[] = {
+	 { "TRP_WRA", 0, 5, &umr_bitfield_default },
+	 { "TRP_RDA", 8, 13, &umr_bitfield_default },
+	 { "TRP", 15, 19, &umr_bitfield_default },
+	 { "TRFC", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING2[] = {
+	 { "PA2RDATA", 0, 2, &umr_bitfield_default },
+	 { "PA2WDATA", 4, 6, &umr_bitfield_default },
+	 { "FAW", 8, 12, &umr_bitfield_default },
+	 { "TREDC", 13, 15, &umr_bitfield_default },
+	 { "TWEDC", 16, 20, &umr_bitfield_default },
+	 { "T32AW", 21, 24, &umr_bitfield_default },
+	 { "TWDATATR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_TIMING[] = {
+	 { "TCKSRE", 0, 2, &umr_bitfield_default },
+	 { "TCKSRX", 4, 6, &umr_bitfield_default },
+	 { "TCKE_PULSE", 8, 11, &umr_bitfield_default },
+	 { "TCKE", 12, 17, &umr_bitfield_default },
+	 { "SEQ_IDLE", 18, 20, &umr_bitfield_default },
+	 { "TCKE_PULSE_MSB", 23, 23, &umr_bitfield_default },
+	 { "SEQ_IDLE_SS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D0[] = {
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D1[] = {
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D0[] = {
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D1[] = {
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CMD[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "CHAN0", 24, 24, &umr_bitfield_default },
+	 { "CHAN1", 25, 25, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_CNTL[] = {
+	 { "RUN", 0, 0, &umr_bitfield_default },
+	 { "SINGLE_STEP", 1, 1, &umr_bitfield_default },
+	 { "SW_WAKE", 2, 2, &umr_bitfield_default },
+	 { "RESET_PC", 3, 3, &umr_bitfield_default },
+	 { "PGM_WRITE", 4, 4, &umr_bitfield_default },
+	 { "PGM_READ", 5, 5, &umr_bitfield_default },
+	 { "FAST_WRITE", 6, 6, &umr_bitfield_default },
+	 { "BKPT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "PGM_CHKSUM", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_PGM[] = {
+	 { "CNTL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_AUTO_CMD[] = {
+	 { "ADR", 0, 16, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_AUTO_CFG[] = {
+	 { "SYC_CLK", 0, 0, &umr_bitfield_default },
+	 { "RST_MRS", 1, 1, &umr_bitfield_default },
+	 { "TRI_MIO", 2, 2, &umr_bitfield_default },
+	 { "XSR_TMR", 4, 7, &umr_bitfield_default },
+	 { "SS_ALWAYS_SLF", 8, 8, &umr_bitfield_default },
+	 { "SS_S_SLF", 9, 9, &umr_bitfield_default },
+	 { "SCDS_MODE", 10, 10, &umr_bitfield_default },
+	 { "EXIT_ALLOW_STOP", 11, 11, &umr_bitfield_default },
+	 { "RFS_SRX", 12, 12, &umr_bitfield_default },
+	 { "PREA_SRX", 13, 13, &umr_bitfield_default },
+	 { "STUTTER_EN", 14, 14, &umr_bitfield_default },
+	 { "SELFREFR_COMMIT_0", 15, 15, &umr_bitfield_default },
+	 { "MRS_WAIT_CNT", 16, 19, &umr_bitfield_default },
+	 { "WRITE_DURING_DLOCK", 20, 20, &umr_bitfield_default },
+	 { "YCLK_ON", 21, 21, &umr_bitfield_default },
+	 { "RXPDNB", 22, 22, &umr_bitfield_default },
+	 { "SELFREFR_COMMIT_1", 23, 23, &umr_bitfield_default },
+	 { "DLL_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_CNTL[] = {
+	 { "MEM_IO_UPDATE_RATE", 0, 4, &umr_bitfield_default },
+	 { "CAL_VREF_SEL", 5, 5, &umr_bitfield_default },
+	 { "CAL_VREFMODE", 6, 6, &umr_bitfield_default },
+	 { "TIMEOUT_ERR", 8, 8, &umr_bitfield_default },
+	 { "CLEAR_TIMEOUT_ERR", 9, 9, &umr_bitfield_default },
+	 { "MEM_IO_SAMPLE_CNT", 13, 15, &umr_bitfield_default },
+	 { "CAL_VREF", 16, 22, &umr_bitfield_default },
+	 { "CAL_WHEN_IDLE", 29, 29, &umr_bitfield_default },
+	 { "CAL_WHEN_REFRESH", 30, 30, &umr_bitfield_default },
+	 { "CAL_PWRON", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_DEBUG[] = {
+	 { "TSTARTUP_CNTR", 0, 7, &umr_bitfield_default },
+	 { "TIMEOUT_CNTR", 8, 15, &umr_bitfield_default },
+	 { "PMVCAL_RESERVED", 16, 27, &umr_bitfield_default },
+	 { "DEBUG_CAL_EN", 28, 28, &umr_bitfield_default },
+	 { "DEBUG_CAL_START", 29, 29, &umr_bitfield_default },
+	 { "DEBUG_CAL_INTR", 30, 30, &umr_bitfield_default },
+	 { "DEBUG_CAL_DONE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_STATUS[] = {
+	 { "PSTR_CAL", 0, 7, &umr_bitfield_default },
+	 { "PSTR_ACCUM_VAL", 8, 15, &umr_bitfield_default },
+	 { "NSTR_CAL", 16, 23, &umr_bitfield_default },
+	 { "NSTR_ACCUM_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WCDR_CTRL[] = {
+	 { "WCDR_PRE", 0, 7, &umr_bitfield_default },
+	 { "WCDR_TIM", 8, 11, &umr_bitfield_default },
+	 { "WR_EN", 12, 12, &umr_bitfield_default },
+	 { "RD_EN", 13, 13, &umr_bitfield_default },
+	 { "AREF_EN", 14, 14, &umr_bitfield_default },
+	 { "TRAIN_EN", 15, 15, &umr_bitfield_default },
+	 { "TWCDRL", 16, 19, &umr_bitfield_default },
+	 { "PRBS_EN", 20, 20, &umr_bitfield_default },
+	 { "PRBS_RST", 21, 21, &umr_bitfield_default },
+	 { "PREAMBLE", 24, 27, &umr_bitfield_default },
+	 { "PRE_MASK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_CNTL[] = {
+	 { "BOOT_UP_ADDR_TRAIN", 0, 0, &umr_bitfield_default },
+	 { "BOOT_UP_WCK_TRAIN", 1, 1, &umr_bitfield_default },
+	 { "BOOT_UP_READ_TRAIN", 2, 2, &umr_bitfield_default },
+	 { "BOOT_UP_WRITE_TRAIN", 3, 3, &umr_bitfield_default },
+	 { "SELF_REFRESH_ADDR_TRAIN", 4, 4, &umr_bitfield_default },
+	 { "SELF_REFRESH_WCK_TRAIN", 5, 5, &umr_bitfield_default },
+	 { "SELF_REFRESH_READ_TRAIN", 6, 6, &umr_bitfield_default },
+	 { "SELF_REFRESH_WRITE_TRAIN", 7, 7, &umr_bitfield_default },
+	 { "AUTO_REFRESH_ADDR_TRAIN", 8, 8, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WCK_TRAIN", 9, 9, &umr_bitfield_default },
+	 { "AUTO_REFRESH_READ_TRAIN", 10, 10, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WRITE_TRAIN", 11, 11, &umr_bitfield_default },
+	 { "WRITE_ECC_ADDR_TRAIN", 12, 12, &umr_bitfield_default },
+	 { "WRITE_ECC_WCK_TRAIN", 13, 13, &umr_bitfield_default },
+	 { "WRITE_ECC_READ_TRAIN", 14, 14, &umr_bitfield_default },
+	 { "WRITE_ECC_WRITE_TRAIN", 15, 15, &umr_bitfield_default },
+	 { "READ_ECC_ADDR_TRAIN", 16, 16, &umr_bitfield_default },
+	 { "READ_ECC_WCK_TRAIN", 17, 17, &umr_bitfield_default },
+	 { "READ_ECC_READ_TRAIN", 18, 18, &umr_bitfield_default },
+	 { "READ_ECC_WRITE_TRAIN", 19, 19, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WAKEUP_EARLY", 20, 20, &umr_bitfield_default },
+	 { "STOP_WCK_D0", 21, 21, &umr_bitfield_default },
+	 { "STOP_WCK_D1", 22, 22, &umr_bitfield_default },
+	 { "BLOCK_ARB_RD_D0", 24, 24, &umr_bitfield_default },
+	 { "BLOCK_ARB_WR_D0", 25, 25, &umr_bitfield_default },
+	 { "BLOCK_ARB_RD_D1", 26, 26, &umr_bitfield_default },
+	 { "BLOCK_ARB_WR_D1", 27, 27, &umr_bitfield_default },
+	 { "SW_WAKEUP", 28, 28, &umr_bitfield_default },
+	 { "DISP_ASTOP_WAKEUP", 29, 29, &umr_bitfield_default },
+	 { "TRAIN_DONE_D0", 30, 30, &umr_bitfield_default },
+	 { "TRAIN_DONE_D1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD[] = {
+	 { "WRITE_EDC_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "READ_EDC_THRESHOLD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_EDGE[] = {
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "SREG_WAKEUP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_MASK[] = {
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "SREG_WAKEUP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_CAPTURE[] = {
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "SREG_WAKEUP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_CLEAR[] = {
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "CLEARALL", 16, 16, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "SREG_WAKEUP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_TIMING[] = {
+	 { "TWT2RT", 0, 4, &umr_bitfield_default },
+	 { "TARF2T", 5, 9, &umr_bitfield_default },
+	 { "TT2ROW", 10, 14, &umr_bitfield_default },
+	 { "TLD2LD", 15, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDCCDR_R_D0[] = {
+	 { "EDC0", 0, 7, &umr_bitfield_default },
+	 { "EDC1", 8, 15, &umr_bitfield_default },
+	 { "EDC2", 16, 23, &umr_bitfield_default },
+	 { "EDC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDCCDR_R_D1[] = {
+	 { "EDC0", 0, 7, &umr_bitfield_default },
+	 { "EDC1", 8, 15, &umr_bitfield_default },
+	 { "EDC2", 16, 23, &umr_bitfield_default },
+	 { "EDC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_0_D0[] = {
+	 { "DQ_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_1_D0[] = {
+	 { "DBI_STATUS", 0, 3, &umr_bitfield_default },
+	 { "EDC_STATUS", 4, 7, &umr_bitfield_default },
+	 { "WCK_STATUS", 8, 11, &umr_bitfield_default },
+	 { "WCDR_STATUS", 12, 15, &umr_bitfield_default },
+	 { "PMA_PRBSCLR", 28, 28, &umr_bitfield_default },
+	 { "PMD0_PRBSCLR", 29, 29, &umr_bitfield_default },
+	 { "PMD1_PRBSCLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDC_STATUS_D0[] = {
+	 { "WEDC_CNT", 0, 15, &umr_bitfield_default },
+	 { "REDC_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_0_D1[] = {
+	 { "DQ_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_1_D1[] = {
+	 { "DBI_STATUS", 0, 3, &umr_bitfield_default },
+	 { "EDC_STATUS", 4, 7, &umr_bitfield_default },
+	 { "WCK_STATUS", 8, 11, &umr_bitfield_default },
+	 { "WCDR_STATUS", 12, 15, &umr_bitfield_default },
+	 { "PMA_PRBSCLR", 28, 28, &umr_bitfield_default },
+	 { "PMD0_PRBSCLR", 29, 29, &umr_bitfield_default },
+	 { "PMD1_PRBSCLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDC_STATUS_D1[] = {
+	 { "WEDC_CNT", 0, 15, &umr_bitfield_default },
+	 { "REDC_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY0_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY1_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_APHY_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "TXBPASS_SEL", 12, 12, &umr_bitfield_default },
+	 { "PMA_LOOPBACK", 13, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 22, &umr_bitfield_default },
+	 { "YCLKON", 23, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXRESET", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 27, 29, &umr_bitfield_default },
+	 { "CKE_BIT", 30, 30, &umr_bitfield_default },
+	 { "CKE_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY0_D0[] = {
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY1_D0[] = {
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_DPHY_STR_CNTL_D0[] = {
+	 { "PSTR_OFF_D", 0, 5, &umr_bitfield_default },
+	 { "NSTR_OFF_D", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_S", 12, 17, &umr_bitfield_default },
+	 { "NSTR_OFF_S", 18, 23, &umr_bitfield_default },
+	 { "USE_D_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_S_CAL", 25, 25, &umr_bitfield_default },
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_D_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_S_STR", 29, 29, &umr_bitfield_default },
+	 { "AUTO_LD_STR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY0_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY1_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_APHY_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "TXBPASS_SEL", 12, 12, &umr_bitfield_default },
+	 { "PMA_LOOPBACK", 13, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 22, &umr_bitfield_default },
+	 { "YCLKON", 23, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXRESET", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 27, 29, &umr_bitfield_default },
+	 { "CKE_BIT", 30, 30, &umr_bitfield_default },
+	 { "CKE_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY0_D1[] = {
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY1_D1[] = {
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_DPHY_STR_CNTL_D1[] = {
+	 { "PSTR_OFF_D", 0, 5, &umr_bitfield_default },
+	 { "NSTR_OFF_D", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_S", 12, 17, &umr_bitfield_default },
+	 { "NSTR_OFF_S", 18, 23, &umr_bitfield_default },
+	 { "USE_D_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_S_CAL", 25, 25, &umr_bitfield_default },
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_D_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_S_STR", 29, 29, &umr_bitfield_default },
+	 { "AUTO_LD_STR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL_D0[] = {
+	 { "RXPHASE_B01", 0, 3, &umr_bitfield_default },
+	 { "RXPHASE_B23", 4, 7, &umr_bitfield_default },
+	 { "RXCDREN_B01", 8, 8, &umr_bitfield_default },
+	 { "RXCDREN_B23", 9, 9, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B01", 10, 10, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B23", 11, 11, &umr_bitfield_default },
+	 { "RXPHASE1_B01", 12, 15, &umr_bitfield_default },
+	 { "RXPHASE1_B23", 16, 19, &umr_bitfield_default },
+	 { "DQTXCDREN_B0", 20, 20, &umr_bitfield_default },
+	 { "DQTXCDREN_B1", 21, 21, &umr_bitfield_default },
+	 { "DQRXCDREN_B0", 22, 22, &umr_bitfield_default },
+	 { "DQRXCDREN_B1", 23, 23, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B0", 24, 24, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B1", 25, 25, &umr_bitfield_default },
+	 { "WCDREDC_B0", 26, 26, &umr_bitfield_default },
+	 { "WCDREDC_B1", 27, 27, &umr_bitfield_default },
+	 { "DQRXSEL_B0", 28, 28, &umr_bitfield_default },
+	 { "DQRXSEL_B1", 29, 29, &umr_bitfield_default },
+	 { "DQTXSEL_B0", 30, 30, &umr_bitfield_default },
+	 { "DQTXSEL_B1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL_D1[] = {
+	 { "RXPHASE_B01", 0, 3, &umr_bitfield_default },
+	 { "RXPHASE_B23", 4, 7, &umr_bitfield_default },
+	 { "RXCDREN_B01", 8, 8, &umr_bitfield_default },
+	 { "RXCDREN_B23", 9, 9, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B01", 10, 10, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B23", 11, 11, &umr_bitfield_default },
+	 { "RXPHASE1_B01", 12, 15, &umr_bitfield_default },
+	 { "RXPHASE1_B23", 16, 19, &umr_bitfield_default },
+	 { "DQTXCDREN_B0", 20, 20, &umr_bitfield_default },
+	 { "DQTXCDREN_B1", 21, 21, &umr_bitfield_default },
+	 { "DQRXCDREN_B0", 22, 22, &umr_bitfield_default },
+	 { "DQRXCDREN_B1", 23, 23, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B0", 24, 24, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B1", 25, 25, &umr_bitfield_default },
+	 { "WCDREDC_B0", 26, 26, &umr_bitfield_default },
+	 { "WCDREDC_B1", 27, 27, &umr_bitfield_default },
+	 { "DQRXSEL_B0", 28, 28, &umr_bitfield_default },
+	 { "DQRXSEL_B1", 29, 29, &umr_bitfield_default },
+	 { "DQTXSEL_B0", 30, 30, &umr_bitfield_default },
+	 { "DQTXSEL_B1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_FIFO_CTL[] = {
+	 { "W_LD_INIT_D0", 0, 1, &umr_bitfield_default },
+	 { "W_SYC_SEL", 2, 3, &umr_bitfield_default },
+	 { "R_LD_INIT", 4, 5, &umr_bitfield_default },
+	 { "R_SYC_SEL", 6, 7, &umr_bitfield_default },
+	 { "CG_DIS_D0", 8, 8, &umr_bitfield_default },
+	 { "CG_DIS_D1", 9, 9, &umr_bitfield_default },
+	 { "W_LD_INIT_D1", 10, 11, &umr_bitfield_default },
+	 { "SYC_DLY", 12, 14, &umr_bitfield_default },
+	 { "W_ASYC_EXT", 16, 17, &umr_bitfield_default },
+	 { "W_DSYC_EXT", 18, 19, &umr_bitfield_default },
+	 { "R_DQS_LD_INIT", 20, 23, &umr_bitfield_default },
+	 { "R_DQS_STEP", 24, 27, &umr_bitfield_default },
+	 { "R_DQS_FRC", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE0_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE1_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE2_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE3_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_DBI_D0[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_EDC_D0[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_FCK_D0[] = {
+	 { "FCK0", 0, 3, &umr_bitfield_default },
+	 { "FCK1", 4, 7, &umr_bitfield_default },
+	 { "FCK2", 8, 11, &umr_bitfield_default },
+	 { "FCK3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC8[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE0_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE1_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE2_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE3_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_DBI_D1[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_EDC_D1[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_FCK_D1[] = {
+	 { "FCK0", 0, 3, &umr_bitfield_default },
+	 { "FCK1", 4, 7, &umr_bitfield_default },
+	 { "FCK2", 8, 11, &umr_bitfield_default },
+	 { "FCK3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE0_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE1_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE2_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE3_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_DBI_D0[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_EDC_D0[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE0_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE1_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE2_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE3_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_DBI_D1[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_EDC_D1[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL[] = {
+	 { "MEM_IO_IMP_MIN", 0, 7, &umr_bitfield_default },
+	 { "MEM_IO_IMP_MAX", 8, 15, &umr_bitfield_default },
+	 { "TXPHASE_GRAY", 16, 16, &umr_bitfield_default },
+	 { "RXPHASE_GRAY", 17, 17, &umr_bitfield_default },
+	 { "OVL_YCLKON_D0", 18, 18, &umr_bitfield_default },
+	 { "OVL_YCLKON_D1", 19, 19, &umr_bitfield_default },
+	 { "ATBSEL", 20, 23, &umr_bitfield_default },
+	 { "ATBEN", 24, 29, &umr_bitfield_default },
+	 { "ATBSEL_D1", 30, 30, &umr_bitfield_default },
+	 { "ATBSEL_D0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL_D0[] = {
+	 { "DELAY_CLK_SYNC", 2, 2, &umr_bitfield_default },
+	 { "DELAY_CMD_SYNC", 3, 3, &umr_bitfield_default },
+	 { "DELAY_ADR_SYNC", 4, 4, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CLK", 7, 7, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CMD", 8, 8, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_ADR", 9, 9, &umr_bitfield_default },
+	 { "FORCE_EN_RD_STR", 10, 10, &umr_bitfield_default },
+	 { "EN_RD_STR_DLY", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CMD", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_ADR", 13, 13, &umr_bitfield_default },
+	 { "VREFI_EN", 14, 14, &umr_bitfield_default },
+	 { "VREFI_SEL", 15, 19, &umr_bitfield_default },
+	 { "CK_AUTO_EN", 20, 20, &umr_bitfield_default },
+	 { "CK_DELAY_SEL", 21, 21, &umr_bitfield_default },
+	 { "CK_DELAY_N", 22, 23, &umr_bitfield_default },
+	 { "CK_DELAY_P", 24, 25, &umr_bitfield_default },
+	 { "TXPWROFF_CKE", 27, 27, &umr_bitfield_default },
+	 { "UNI_STR", 28, 28, &umr_bitfield_default },
+	 { "DIFF_STR", 29, 29, &umr_bitfield_default },
+	 { "GDDR_PWRON", 30, 30, &umr_bitfield_default },
+	 { "TXPWROFF_CLK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL_D1[] = {
+	 { "DELAY_DATA_SYNC", 0, 0, &umr_bitfield_default },
+	 { "DELAY_STR_SYNC", 1, 1, &umr_bitfield_default },
+	 { "DELAY_CLK_SYNC", 2, 2, &umr_bitfield_default },
+	 { "DELAY_CMD_SYNC", 3, 3, &umr_bitfield_default },
+	 { "DELAY_ADR_SYNC", 4, 4, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_DATA", 5, 5, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_STR", 6, 6, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CLK", 7, 7, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CMD", 8, 8, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_ADR", 9, 9, &umr_bitfield_default },
+	 { "FORCE_EN_RD_STR", 10, 10, &umr_bitfield_default },
+	 { "EN_RD_STR_DLY", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CMD", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_ADR", 13, 13, &umr_bitfield_default },
+	 { "VREFI_EN", 14, 14, &umr_bitfield_default },
+	 { "VREFI_SEL", 15, 19, &umr_bitfield_default },
+	 { "CK_AUTO_EN", 20, 20, &umr_bitfield_default },
+	 { "CK_DELAY_SEL", 21, 21, &umr_bitfield_default },
+	 { "CK_DELAY_N", 22, 23, &umr_bitfield_default },
+	 { "CK_DELAY_P", 24, 25, &umr_bitfield_default },
+	 { "TXPWROFF_CKE", 27, 27, &umr_bitfield_default },
+	 { "UNI_STR", 28, 28, &umr_bitfield_default },
+	 { "DIFF_STR", 29, 29, &umr_bitfield_default },
+	 { "GDDR_PWRON", 30, 30, &umr_bitfield_default },
+	 { "TXPWROFF_CLK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_NPL_STATUS[] = {
+	 { "D0_PDELAY", 0, 1, &umr_bitfield_default },
+	 { "D0_NDELAY", 2, 3, &umr_bitfield_default },
+	 { "D0_PEARLY", 4, 4, &umr_bitfield_default },
+	 { "D0_NEARLY", 5, 5, &umr_bitfield_default },
+	 { "D1_PDELAY", 6, 7, &umr_bitfield_default },
+	 { "D1_NDELAY", 8, 9, &umr_bitfield_default },
+	 { "D1_PEARLY", 10, 10, &umr_bitfield_default },
+	 { "D1_NEARLY", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_CNTL[] = {
+	 { "MONITOR_PERIOD", 0, 29, &umr_bitfield_default },
+	 { "CNTL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CTL[] = {
+	 { "SEL_A", 0, 3, &umr_bitfield_default },
+	 { "SEL_B", 4, 7, &umr_bitfield_default },
+	 { "SEL_CH0_C", 8, 11, &umr_bitfield_default },
+	 { "SEL_CH0_D", 12, 15, &umr_bitfield_default },
+	 { "SEL_CH1_A", 16, 19, &umr_bitfield_default },
+	 { "SEL_CH1_B", 20, 23, &umr_bitfield_default },
+	 { "SEL_CH1_C", 24, 27, &umr_bitfield_default },
+	 { "SEL_CH1_D", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_A_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_A_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_B_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_B_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_STATUS_M[] = {
+	 { "PWRUP_COMPL_D0", 0, 0, &umr_bitfield_default },
+	 { "PWRUP_COMPL_D1", 1, 1, &umr_bitfield_default },
+	 { "CMD_RDY_D0", 2, 2, &umr_bitfield_default },
+	 { "CMD_RDY_D1", 3, 3, &umr_bitfield_default },
+	 { "SLF_D0", 4, 4, &umr_bitfield_default },
+	 { "SLF_D1", 5, 5, &umr_bitfield_default },
+	 { "SS_SLF_D0", 6, 6, &umr_bitfield_default },
+	 { "SS_SLF_D1", 7, 7, &umr_bitfield_default },
+	 { "SEQ0_ARB_CMD_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "SEQ1_ARB_CMD_FIFO_EMPTY", 9, 9, &umr_bitfield_default },
+	 { "SEQ0_RS_DATA_FIFO_FULL", 12, 12, &umr_bitfield_default },
+	 { "SEQ1_RS_DATA_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "SEQ0_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SEQ1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "PMG_PWRSTATE", 16, 16, &umr_bitfield_default },
+	 { "PMG_FSMSTATE", 20, 24, &umr_bitfield_default },
+	 { "SEQ0_BUSY_HYS", 25, 25, &umr_bitfield_default },
+	 { "SEQ1_BUSY_HYS", 26, 26, &umr_bitfield_default },
+	 { "SEQ0_ALLOWSTOP", 27, 27, &umr_bitfield_default },
+	 { "SEQ1_ALLOWSTOP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_VENDOR_ID_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_VENDOR_ID_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_M[] = {
+	 { "MCLK_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_EMRS[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CFG[] = {
+	 { "SYC_CLK", 0, 0, &umr_bitfield_default },
+	 { "RST_MRS", 1, 1, &umr_bitfield_default },
+	 { "RST_EMRS", 2, 2, &umr_bitfield_default },
+	 { "TRI_MIO", 3, 3, &umr_bitfield_default },
+	 { "XSR_TMR", 4, 7, &umr_bitfield_default },
+	 { "RST_MRS1", 8, 8, &umr_bitfield_default },
+	 { "RST_MRS2", 9, 9, &umr_bitfield_default },
+	 { "DPM_WAKE", 10, 10, &umr_bitfield_default },
+	 { "RFS_SRX", 12, 12, &umr_bitfield_default },
+	 { "PREA_SRX", 13, 13, &umr_bitfield_default },
+	 { "MRS_WAIT_CNT", 16, 19, &umr_bitfield_default },
+	 { "WRITE_DURING_DLOCK", 20, 20, &umr_bitfield_default },
+	 { "YCLK_ON", 21, 21, &umr_bitfield_default },
+	 { "EARLY_ACK_ACPI", 22, 22, &umr_bitfield_default },
+	 { "RXPDNB", 25, 25, &umr_bitfield_default },
+	 { "ZQCL_SEND", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP2_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP3_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_IR_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_DEC_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_PGM_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_R_PGM[] = {
+	 { "PGM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC3[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC4[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMP_CNTL[] = {
+	 { "CMP_MASK_BYTE", 0, 3, &umr_bitfield_default },
+	 { "CMP_MASK_BIT", 4, 11, &umr_bitfield_default },
+	 { "LOAD_RTEDC", 12, 12, &umr_bitfield_default },
+	 { "DATA_STORE_SEL", 13, 13, &umr_bitfield_default },
+	 { "EDC_STORE_SEL", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_CMD_FIFO", 15, 15, &umr_bitfield_default },
+	 { "CMP", 16, 17, &umr_bitfield_default },
+	 { "DAT_MODE", 18, 18, &umr_bitfield_default },
+	 { "EDC_STORE_MODE", 19, 19, &umr_bitfield_default },
+	 { "DATA_STORE_MODE", 20, 21, &umr_bitfield_default },
+	 { "MISMATCH_CNT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMD_CNTL[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "CMD_ISSUE_MODE", 1, 1, &umr_bitfield_default },
+	 { "CMD_ISSUE_LOOP", 2, 2, &umr_bitfield_default },
+	 { "LOOP_END_CONDITION", 3, 3, &umr_bitfield_default },
+	 { "LOOP_CNT_MAX", 4, 15, &umr_bitfield_default },
+	 { "CMD_ISSUE_MODE_U", 16, 16, &umr_bitfield_default },
+	 { "CMD_ISSUE_RUN", 17, 17, &umr_bitfield_default },
+	 { "LOOP_CNT_RD", 18, 27, &umr_bitfield_default },
+	 { "ENABLE_D0", 28, 28, &umr_bitfield_default },
+	 { "ENABLE_D1", 29, 29, &umr_bitfield_default },
+	 { "STATUS_CH", 30, 30, &umr_bitfield_default },
+	 { "DONE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP0_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP1_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_DEBUG_INDEX[] = {
+	 { "IO_DEBUG_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_DEBUG_DATA[] = {
+	 { "IO_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BYTE_REMAP_D0[] = {
+	 { "BYTE0", 0, 1, &umr_bitfield_default },
+	 { "BYTE1", 2, 3, &umr_bitfield_default },
+	 { "BYTE2", 4, 5, &umr_bitfield_default },
+	 { "BYTE3", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BYTE_REMAP_D1[] = {
+	 { "BYTE0", 0, 1, &umr_bitfield_default },
+	 { "BYTE1", 2, 3, &umr_bitfield_default },
+	 { "BYTE2", 4, 5, &umr_bitfield_default },
+	 { "BYTE3", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC5[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC6[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_APHY_STR_CNTL_D0[] = {
+	 { "PSTR_OFF_A", 0, 5, &umr_bitfield_default },
+	 { "NSTR_OFF_A", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_D_RD", 12, 17, &umr_bitfield_default },
+	 { "USE_A_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_D_RD_CAL", 25, 25, &umr_bitfield_default },
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_A_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_D_RD_STR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_APHY_STR_CNTL_D1[] = {
+	 { "PSTR_OFF_A", 0, 5, &umr_bitfield_default },
+	 { "NSTR_OFF_A", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_D_RD", 12, 17, &umr_bitfield_default },
+	 { "USE_A_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_D_RD_CAL", 25, 25, &umr_bitfield_default },
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_A_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_D_RD_STR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC7[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CG[] = {
+	 { "CG_SEQ_REQ", 0, 7, &umr_bitfield_default },
+	 { "CG_SEQ_RESP", 8, 15, &umr_bitfield_default },
+	 { "SEQ_CG_REQ", 16, 23, &umr_bitfield_default },
+	 { "SEQ_CG_RESP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RAS_TIMING_LP[] = {
+	 { "TRCDW", 0, 4, &umr_bitfield_default },
+	 { "TRCDWA", 5, 9, &umr_bitfield_default },
+	 { "TRCDR", 10, 14, &umr_bitfield_default },
+	 { "TRCDRA", 15, 19, &umr_bitfield_default },
+	 { "TRRD", 20, 23, &umr_bitfield_default },
+	 { "TRC", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CAS_TIMING_LP[] = {
+	 { "TNOPW", 0, 1, &umr_bitfield_default },
+	 { "TNOPR", 2, 3, &umr_bitfield_default },
+	 { "TR2W", 4, 8, &umr_bitfield_default },
+	 { "TCCDL", 9, 11, &umr_bitfield_default },
+	 { "TR2R", 12, 15, &umr_bitfield_default },
+	 { "TW2R", 16, 20, &umr_bitfield_default },
+	 { "TCL", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING_LP[] = {
+	 { "TRP_WRA", 0, 5, &umr_bitfield_default },
+	 { "TRP_RDA", 8, 13, &umr_bitfield_default },
+	 { "TRP", 15, 19, &umr_bitfield_default },
+	 { "TRFC", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING2_LP[] = {
+	 { "PA2RDATA", 0, 2, &umr_bitfield_default },
+	 { "PA2WDATA", 4, 6, &umr_bitfield_default },
+	 { "FAW", 8, 12, &umr_bitfield_default },
+	 { "TREDC", 13, 15, &umr_bitfield_default },
+	 { "TWEDC", 16, 20, &umr_bitfield_default },
+	 { "TADR", 21, 23, &umr_bitfield_default },
+	 { "TFCKTR", 24, 27, &umr_bitfield_default },
+	 { "TWDATATR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D0_LP[] = {
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D1_LP[] = {
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_EMRS_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B0_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B1_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B2_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B3_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B0_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B1_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B2_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B3_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD0[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD1[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD2[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD3[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD4[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD5[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD6[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD7[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RDBI[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_REDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMP_CNTL_2[] = {
+	 { "DATA_STORE_CNT", 0, 4, &umr_bitfield_default },
+	 { "DATA_STORE_CNT_RST", 8, 8, &umr_bitfield_default },
+	 { "EDC_STORE_CNT", 12, 16, &umr_bitfield_default },
+	 { "EDC_STORE_CNT_RST", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RESERVE_D0[] = {
+	 { "DPHY0_RSV", 0, 11, &umr_bitfield_default },
+	 { "DPHY1_RSV", 12, 23, &umr_bitfield_default },
+	 { "APHY_RSV", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RESERVE_D1[] = {
+	 { "DPHY0_RSV", 0, 11, &umr_bitfield_default },
+	 { "DPHY1_RSV", 12, 23, &umr_bitfield_default },
+	 { "APHY_RSV", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_HWCNTL[] = {
+	 { "PWRGATE_EN", 0, 0, &umr_bitfield_default },
+	 { "STAGGER_EN", 1, 1, &umr_bitfield_default },
+	 { "TPGCG", 2, 5, &umr_bitfield_default },
+	 { "D_DLY", 6, 7, &umr_bitfield_default },
+	 { "AC_DLY", 8, 9, &umr_bitfield_default },
+	 { "G_DLY", 10, 13, &umr_bitfield_default },
+	 { "TXAO", 16, 16, &umr_bitfield_default },
+	 { "RXAO", 17, 17, &umr_bitfield_default },
+	 { "ACAO", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_SWCNTL_0[] = {
+	 { "PMD0_DQ_TX_ENB", 0, 0, &umr_bitfield_default },
+	 { "PMD0_DBI_TX_ENB", 1, 1, &umr_bitfield_default },
+	 { "PMD0_EDC_TX_ENB", 2, 2, &umr_bitfield_default },
+	 { "PMD0_WCLKX_TX_ENB", 3, 3, &umr_bitfield_default },
+	 { "PMD0_DQ_RX_ENB", 4, 4, &umr_bitfield_default },
+	 { "PMD0_DBI_RX_ENB", 5, 5, &umr_bitfield_default },
+	 { "PMD0_EDC_RX_ENB", 6, 6, &umr_bitfield_default },
+	 { "PMD0_WCLKX_RX_ENB", 7, 7, &umr_bitfield_default },
+	 { "PMD1_DQ_TX_ENB", 8, 8, &umr_bitfield_default },
+	 { "PMD1_DBI_TX_ENB", 9, 9, &umr_bitfield_default },
+	 { "PMD1_EDC_TX_ENB", 10, 10, &umr_bitfield_default },
+	 { "PMD1_WCLKX_TX_ENB", 11, 11, &umr_bitfield_default },
+	 { "PMD1_DQ_RX_ENB", 12, 12, &umr_bitfield_default },
+	 { "PMD1_DBI_RX_ENB", 13, 13, &umr_bitfield_default },
+	 { "PMD1_EDC_RX_ENB", 14, 14, &umr_bitfield_default },
+	 { "PMD1_WCLKX_RX_ENB", 15, 15, &umr_bitfield_default },
+	 { "PMA0_AC_ENB", 16, 16, &umr_bitfield_default },
+	 { "GMCON_SR_COMMIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_SWCNTL_1[] = {
+	 { "PMD2_DQ_TX_ENB", 0, 0, &umr_bitfield_default },
+	 { "PMD2_DBI_TX_ENB", 1, 1, &umr_bitfield_default },
+	 { "PMD2_EDC_TX_ENB", 2, 2, &umr_bitfield_default },
+	 { "PMD2_WCLKX_TX_ENB", 3, 3, &umr_bitfield_default },
+	 { "PMD2_DQ_RX_ENB", 4, 4, &umr_bitfield_default },
+	 { "PMD2_DBI_RX_ENB", 5, 5, &umr_bitfield_default },
+	 { "PMD2_EDC_RX_ENB", 6, 6, &umr_bitfield_default },
+	 { "PMD2_WCLKX_RX_ENB", 7, 7, &umr_bitfield_default },
+	 { "PMD3_DQ_TX_ENB", 8, 8, &umr_bitfield_default },
+	 { "PMD3_DBI_TX_ENB", 9, 9, &umr_bitfield_default },
+	 { "PMD3_EDC_TX_ENB", 10, 10, &umr_bitfield_default },
+	 { "PMD3_WCLKX_TX_ENB", 11, 11, &umr_bitfield_default },
+	 { "PMD3_DQ_RX_ENB", 12, 12, &umr_bitfield_default },
+	 { "PMD3_DBI_RX_ENB", 13, 13, &umr_bitfield_default },
+	 { "PMD3_EDC_RX_ENB", 14, 14, &umr_bitfield_default },
+	 { "PMD3_WCLKX_RX_ENB", 15, 15, &umr_bitfield_default },
+	 { "PMA1_AC_ENB", 16, 16, &umr_bitfield_default },
+	 { "GMCON_SR_COMMIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_DQ_STATUS[] = {
+	 { "CH0_DQ_PSTR", 0, 7, &umr_bitfield_default },
+	 { "CH0_DQ_NSTR", 8, 15, &umr_bitfield_default },
+	 { "CH1_DQ_PSTR", 16, 23, &umr_bitfield_default },
+	 { "CH1_DQ_NSTR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TCG_CNTL[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_D0", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_D1", 2, 2, &umr_bitfield_default },
+	 { "START", 3, 3, &umr_bitfield_default },
+	 { "NFIFO", 4, 6, &umr_bitfield_default },
+	 { "INFINITE_CMD", 7, 7, &umr_bitfield_default },
+	 { "MOP", 8, 11, &umr_bitfield_default },
+	 { "DATA_CNT", 12, 15, &umr_bitfield_default },
+	 { "LOAD_FIFO", 16, 16, &umr_bitfield_default },
+	 { "SHORT_LDFF", 17, 17, &umr_bitfield_default },
+	 { "FRAME_TRAIN", 18, 18, &umr_bitfield_default },
+	 { "BURST_NUM", 19, 21, &umr_bitfield_default },
+	 { "ISSUE_AREF", 22, 22, &umr_bitfield_default },
+	 { "TXDBI_CNTL", 23, 23, &umr_bitfield_default },
+	 { "VPTR_MASK", 24, 24, &umr_bitfield_default },
+	 { "AREF_LAST", 25, 25, &umr_bitfield_default },
+	 { "AREF_BOTH", 26, 26, &umr_bitfield_default },
+	 { "LD_RTDATA_OVR", 28, 28, &umr_bitfield_default },
+	 { "LD_RTDATA_CH", 29, 29, &umr_bitfield_default },
+	 { "DONE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_CTRL[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "CAPTURE_START", 1, 1, &umr_bitfield_default },
+	 { "DONE", 2, 2, &umr_bitfield_default },
+	 { "ERR", 3, 3, &umr_bitfield_default },
+	 { "STEP", 4, 4, &umr_bitfield_default },
+	 { "DIRECTION", 5, 5, &umr_bitfield_default },
+	 { "INVERT", 6, 6, &umr_bitfield_default },
+	 { "MASK_BITS", 7, 7, &umr_bitfield_default },
+	 { "UPDATE_LOOP", 8, 9, &umr_bitfield_default },
+	 { "ROT_INV", 10, 10, &umr_bitfield_default },
+	 { "DUAL_CH_EN", 11, 11, &umr_bitfield_default },
+	 { "DONE0", 12, 12, &umr_bitfield_default },
+	 { "DONE1", 13, 13, &umr_bitfield_default },
+	 { "POINTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_GCNT[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "COMP_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_OCNT[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "CMP_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_NCNT[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "RANGE_LOW", 16, 19, &umr_bitfield_default },
+	 { "RANGE_HIGH", 20, 23, &umr_bitfield_default },
+	 { "NIBBLE_SKIP", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_BCNT[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "BCNT_TESTS", 8, 15, &umr_bitfield_default },
+	 { "COMP_VALUE", 16, 23, &umr_bitfield_default },
+	 { "DONE_TESTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_FLAG[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "FLAG_TESTS", 8, 15, &umr_bitfield_default },
+	 { "NBBL_MASK", 16, 19, &umr_bitfield_default },
+	 { "ERROR_TESTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_UPDATE[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "UPDT_TESTS", 8, 15, &umr_bitfield_default },
+	 { "AREF_COUNT", 16, 23, &umr_bitfield_default },
+	 { "CAPTR_TESTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_EDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DBI[] = {
+	 { "DBI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D0_LP[] = {
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D1_LP[] = {
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TIMER_WR[] = {
+	 { "COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TIMER_RD[] = {
+	 { "COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM_ERROR_INSERTION[] = {
+	 { "TX", 0, 15, &umr_bitfield_default },
+	 { "RX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_D0[] = {
+	 { "RXC0_DLY", 0, 3, &umr_bitfield_default },
+	 { "RXC0_EXT", 4, 7, &umr_bitfield_default },
+	 { "RXC1_DLY", 8, 11, &umr_bitfield_default },
+	 { "RXC1_EXT", 12, 15, &umr_bitfield_default },
+	 { "TXC0_DLY", 16, 18, &umr_bitfield_default },
+	 { "TXC0_EXT", 20, 23, &umr_bitfield_default },
+	 { "TXC1_DLY", 24, 26, &umr_bitfield_default },
+	 { "TXC1_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_D1[] = {
+	 { "RXC0_DLY", 0, 3, &umr_bitfield_default },
+	 { "RXC0_EXT", 4, 7, &umr_bitfield_default },
+	 { "RXC1_DLY", 8, 11, &umr_bitfield_default },
+	 { "RXC1_EXT", 12, 15, &umr_bitfield_default },
+	 { "TXC0_DLY", 16, 18, &umr_bitfield_default },
+	 { "TXC0_EXT", 20, 23, &umr_bitfield_default },
+	 { "TXC1_DLY", 24, 26, &umr_bitfield_default },
+	 { "TXC1_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_2[] = {
+	 { "IND_LD_CNT", 0, 6, &umr_bitfield_default },
+	 { "RXC0_INV", 8, 8, &umr_bitfield_default },
+	 { "RXC1_INV", 9, 9, &umr_bitfield_default },
+	 { "TXC0_INV", 10, 10, &umr_bitfield_default },
+	 { "TXC1_INV", 11, 11, &umr_bitfield_default },
+	 { "RXC0_FRC", 12, 12, &umr_bitfield_default },
+	 { "RXC1_FRC", 13, 13, &umr_bitfield_default },
+	 { "TXC0_FRC", 14, 14, &umr_bitfield_default },
+	 { "TXC1_FRC", 15, 15, &umr_bitfield_default },
+	 { "TX_CDREN_D0", 16, 16, &umr_bitfield_default },
+	 { "TX_CDREN_D1", 17, 17, &umr_bitfield_default },
+	 { "ADR_CLKEN_D0", 18, 18, &umr_bitfield_default },
+	 { "ADR_CLKEN_D1", 19, 19, &umr_bitfield_default },
+	 { "WR_DLY", 20, 23, &umr_bitfield_default },
+	 { "RXDPWRONC0_FRC", 24, 24, &umr_bitfield_default },
+	 { "RXDPWRONC1_FRC", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DEBUG_INDEX[] = {
+	 { "TSM_DEBUG_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DEBUG_DATA[] = {
+	 { "TSM_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS1[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS1_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_TIMING_LP[] = {
+	 { "TCKSRE", 0, 2, &umr_bitfield_default },
+	 { "TCKSRX", 4, 6, &umr_bitfield_default },
+	 { "TCKE_PULSE", 8, 11, &umr_bitfield_default },
+	 { "TCKE", 12, 17, &umr_bitfield_default },
+	 { "SEQ_IDLE", 18, 20, &umr_bitfield_default },
+	 { "TCKE_PULSE_MSB", 23, 23, &umr_bitfield_default },
+	 { "SEQ_IDLE_SS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CNTL_2[] = {
+	 { "DRST_PDRV", 0, 3, &umr_bitfield_default },
+	 { "DRST_PU", 4, 4, &umr_bitfield_default },
+	 { "DRST_PD", 5, 5, &umr_bitfield_default },
+	 { "ARB_RTDAT_WMK_MSB", 8, 9, &umr_bitfield_default },
+	 { "DRST_NSTR", 10, 15, &umr_bitfield_default },
+	 { "DRST_PSTR", 16, 21, &umr_bitfield_default },
+	 { "PLL_TX_PWRON_D0", 22, 22, &umr_bitfield_default },
+	 { "PLL_TX_PWRON_D1", 23, 23, &umr_bitfield_default },
+	 { "PLL_RX_PWRON_D0", 24, 27, &umr_bitfield_default },
+	 { "PLL_RX_PWRON_D1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_2[] = {
+	 { "DAT_DLY_H_D0", 0, 0, &umr_bitfield_default },
+	 { "DQS_DLY_H_D0", 1, 1, &umr_bitfield_default },
+	 { "OEN_DLY_H_D0", 2, 2, &umr_bitfield_default },
+	 { "DAT_DLY_H_D1", 3, 3, &umr_bitfield_default },
+	 { "DQS_DLY_H_D1", 4, 4, &umr_bitfield_default },
+	 { "OEN_DLY_H_D1", 5, 5, &umr_bitfield_default },
+	 { "WCDR_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_2_LP[] = {
+	 { "DAT_DLY_H_D0", 0, 0, &umr_bitfield_default },
+	 { "DQS_DLY_H_D0", 1, 1, &umr_bitfield_default },
+	 { "OEN_DLY_H_D0", 2, 2, &umr_bitfield_default },
+	 { "DAT_DLY_H_D1", 3, 3, &umr_bitfield_default },
+	 { "DQS_DLY_H_D1", 4, 4, &umr_bitfield_default },
+	 { "OEN_DLY_H_D1", 5, 5, &umr_bitfield_default },
+	 { "WCDR_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS2[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS2_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_C_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_C_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_D_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_D_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL1_D0[] = {
+	 { "DQ_RXPHASE_B0", 0, 7, &umr_bitfield_default },
+	 { "DQ_RXPHASE_B1", 8, 15, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B0", 16, 23, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL1_D1[] = {
+	 { "DQ_RXPHASE_B0", 0, 7, &umr_bitfield_default },
+	 { "DQ_RXPHASE_B1", 8, 15, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B0", 16, 23, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY0_D0[] = {
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "DLL_PWRGOOD_OVR", 19, 19, &umr_bitfield_default },
+	 { "DLL_VCTRLADC_EN", 20, 20, &umr_bitfield_default },
+	 { "DLL_MSTR_STBY", 21, 21, &umr_bitfield_default },
+	 { "RXLEQ_EN", 22, 22, &umr_bitfield_default },
+	 { "RXLEQ_NXT", 23, 23, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY1_D0[] = {
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "DLL_PWRGOOD_OVR", 19, 19, &umr_bitfield_default },
+	 { "DLL_VCTRLADC_EN", 20, 20, &umr_bitfield_default },
+	 { "DLL_MSTR_STBY", 21, 21, &umr_bitfield_default },
+	 { "RXLEQ_EN", 22, 22, &umr_bitfield_default },
+	 { "RXLEQ_NXT", 23, 23, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY0_D1[] = {
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "DLL_PWRGOOD_OVR", 19, 19, &umr_bitfield_default },
+	 { "DLL_VCTRLADC_EN", 20, 20, &umr_bitfield_default },
+	 { "DLL_MSTR_STBY", 21, 21, &umr_bitfield_default },
+	 { "RXLEQ_EN", 22, 22, &umr_bitfield_default },
+	 { "RXLEQ_NXT", 23, 23, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY1_D1[] = {
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "DLL_PWRGOOD_OVR", 19, 19, &umr_bitfield_default },
+	 { "DLL_VCTRLADC_EN", 20, 20, &umr_bitfield_default },
+	 { "DLL_MSTR_STBY", 21, 21, &umr_bitfield_default },
+	 { "RXLEQ_EN", 22, 22, &umr_bitfield_default },
+	 { "RXLEQ_NXT", 23, 23, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_WCDR[] = {
+	 { "WCDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL2_D0[] = {
+	 { "CDR_FB_SEL0", 0, 0, &umr_bitfield_default },
+	 { "CDR_FB_SEL1", 1, 1, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR0", 2, 2, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR1", 3, 3, &umr_bitfield_default },
+	 { "TXCDRBYPASS0", 4, 4, &umr_bitfield_default },
+	 { "TXCDRBYPASS1", 5, 5, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR0", 6, 6, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR1", 7, 7, &umr_bitfield_default },
+	 { "WCDRTXPWRON", 8, 11, &umr_bitfield_default },
+	 { "WCDRTXSEL", 12, 15, &umr_bitfield_default },
+	 { "WCDRTRACK01", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL2_D1[] = {
+	 { "CDR_FB_SEL0", 0, 0, &umr_bitfield_default },
+	 { "CDR_FB_SEL1", 1, 1, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR0", 2, 2, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR1", 3, 3, &umr_bitfield_default },
+	 { "TXCDRBYPASS0", 4, 4, &umr_bitfield_default },
+	 { "TXCDRBYPASS1", 5, 5, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR0", 6, 6, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR1", 7, 7, &umr_bitfield_default },
+	 { "WCDRTXPWRON", 8, 11, &umr_bitfield_default },
+	 { "WCDRTXSEL", 12, 15, &umr_bitfield_default },
+	 { "WCDRTRACK01", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_MISC[] = {
+	 { "WCDR_PTR", 0, 15, &umr_bitfield_default },
+	 { "WCDR_MASK", 16, 19, &umr_bitfield_default },
+	 { "CH1_OFFSET", 20, 25, &umr_bitfield_default },
+	 { "CH1_WCDR_OFFSET", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC9[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCLK_PWRMGT_CNTL[] = {
+	 { "DLL_SPEED", 0, 4, &umr_bitfield_default },
+	 { "DLL_READY", 6, 6, &umr_bitfield_default },
+	 { "MC_INT_CNTL", 7, 7, &umr_bitfield_default },
+	 { "MRDCK0_PDNB", 8, 8, &umr_bitfield_default },
+	 { "MRDCK1_PDNB", 9, 9, &umr_bitfield_default },
+	 { "MRDCK0_RESET", 16, 16, &umr_bitfield_default },
+	 { "MRDCK1_RESET", 17, 17, &umr_bitfield_default },
+	 { "DLL_READY_READ", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDLL_CNTL[] = {
+	 { "DLL_RESET_TIME", 0, 9, &umr_bitfield_default },
+	 { "DLL_LOCK_TIME", 12, 21, &umr_bitfield_default },
+	 { "MRDCK0_BYPASS", 24, 24, &umr_bitfield_default },
+	 { "MRDCK1_BYPASS", 25, 25, &umr_bitfield_default },
+	 { "PWR2_MODE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SEQ_UCODE_1[] = {
+	 { "INSTR0", 0, 3, &umr_bitfield_default },
+	 { "INSTR1", 4, 7, &umr_bitfield_default },
+	 { "INSTR2", 8, 11, &umr_bitfield_default },
+	 { "INSTR3", 12, 15, &umr_bitfield_default },
+	 { "INSTR4", 16, 19, &umr_bitfield_default },
+	 { "INSTR5", 20, 23, &umr_bitfield_default },
+	 { "INSTR6", 24, 27, &umr_bitfield_default },
+	 { "INSTR7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SEQ_UCODE_2[] = {
+	 { "INSTR8", 0, 3, &umr_bitfield_default },
+	 { "INSTR9", 4, 7, &umr_bitfield_default },
+	 { "INSTR10", 8, 11, &umr_bitfield_default },
+	 { "INSTR11", 12, 15, &umr_bitfield_default },
+	 { "INSTR12", 16, 19, &umr_bitfield_default },
+	 { "INSTR13", 20, 23, &umr_bitfield_default },
+	 { "INSTR14", 24, 27, &umr_bitfield_default },
+	 { "INSTR15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_CNTL_MODE[] = {
+	 { "INSTR_DELAY", 0, 7, &umr_bitfield_default },
+	 { "MPLL_SW_DIR_CONTROL", 8, 8, &umr_bitfield_default },
+	 { "MPLL_MCLK_SEL", 11, 11, &umr_bitfield_default },
+	 { "SPARE_1", 12, 12, &umr_bitfield_default },
+	 { "QDR", 13, 13, &umr_bitfield_default },
+	 { "MPLL_CTLREQ", 14, 14, &umr_bitfield_default },
+	 { "MPLL_CHG_STATUS", 16, 16, &umr_bitfield_default },
+	 { "FORCE_TESTMODE", 17, 17, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 20, 20, &umr_bitfield_default },
+	 { "FAST_LOCK_CNTRL", 21, 22, &umr_bitfield_default },
+	 { "SPARE_2", 23, 23, &umr_bitfield_default },
+	 { "SS_SSEN", 24, 25, &umr_bitfield_default },
+	 { "SS_DSMODE_EN", 26, 26, &umr_bitfield_default },
+	 { "VTOI_BIAS_CNTRL", 27, 27, &umr_bitfield_default },
+	 { "SPARE_3", 28, 30, &umr_bitfield_default },
+	 { "GLOBAL_MPLL_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL[] = {
+	 { "SPARE_0", 5, 5, &umr_bitfield_default },
+	 { "BG_100ADJ", 8, 11, &umr_bitfield_default },
+	 { "BG_135ADJ", 16, 19, &umr_bitfield_default },
+	 { "BWCTRL", 20, 27, &umr_bitfield_default },
+	 { "REG_BIAS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL_1[] = {
+	 { "VCO_MODE", 0, 1, &umr_bitfield_default },
+	 { "SPARE_0", 2, 3, &umr_bitfield_default },
+	 { "CLKFRAC", 4, 15, &umr_bitfield_default },
+	 { "CLKF", 16, 27, &umr_bitfield_default },
+	 { "SPARE_1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL_2[] = {
+	 { "VCTRLADC_EN", 0, 0, &umr_bitfield_default },
+	 { "TEST_VCTL_EN", 1, 1, &umr_bitfield_default },
+	 { "RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "TEST_BYPCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "TEST_BYPCLK_SRC", 4, 4, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC_BYPASS", 5, 5, &umr_bitfield_default },
+	 { "TEST_BYPMCLK", 6, 6, &umr_bitfield_default },
+	 { "MPLL_UNLOCK_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "TEST_VCTL_CNTRL", 8, 8, &umr_bitfield_default },
+	 { "TEST_FBDIV_SSC_BYPASS", 9, 9, &umr_bitfield_default },
+	 { "RESET_TIMER", 10, 11, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 12, 13, &umr_bitfield_default },
+	 { "RISEFBVCO_EN", 14, 14, &umr_bitfield_default },
+	 { "PWRGOOD_OVR", 15, 15, &umr_bitfield_default },
+	 { "ISO_DIS_P", 16, 16, &umr_bitfield_default },
+	 { "BACKUP_2", 17, 19, &umr_bitfield_default },
+	 { "LF_CNTRL", 20, 26, &umr_bitfield_default },
+	 { "BACKUP", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_AD_FUNC_CNTL[] = {
+	 { "YCLK_POST_DIV", 0, 2, &umr_bitfield_default },
+	 { "SPARE", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_FUNC_CNTL[] = {
+	 { "YCLK_POST_DIV", 0, 2, &umr_bitfield_default },
+	 { "SPARE_0", 3, 3, &umr_bitfield_default },
+	 { "YCLK_SEL", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_TIME[] = {
+	 { "MPLL_LOCK_TIME", 0, 15, &umr_bitfield_default },
+	 { "MPLL_RESET_TIME", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SS1[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+	 { "SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SS2[] = {
+	 { "CLKS", 0, 11, &umr_bitfield_default },
+	 { "SPARE", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_CONTROL[] = {
+	 { "GDDR_PWRON", 0, 0, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 1, 1, &umr_bitfield_default },
+	 { "PLL_BUF_PWRON_TX", 2, 2, &umr_bitfield_default },
+	 { "AD_BG_PWRON", 12, 12, &umr_bitfield_default },
+	 { "AD_PLL_PWRON", 13, 13, &umr_bitfield_default },
+	 { "AD_PLL_RESET", 14, 14, &umr_bitfield_default },
+	 { "SPARE_AD_0", 15, 15, &umr_bitfield_default },
+	 { "DQ_0_0_BG_PWRON", 16, 16, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_PWRON", 17, 17, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_RESET", 18, 18, &umr_bitfield_default },
+	 { "SPARE_DQ_0_0", 19, 19, &umr_bitfield_default },
+	 { "DQ_0_1_BG_PWRON", 20, 20, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_PWRON", 21, 21, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_RESET", 22, 22, &umr_bitfield_default },
+	 { "SPARE_DQ_0_1", 23, 23, &umr_bitfield_default },
+	 { "DQ_1_0_BG_PWRON", 24, 24, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_PWRON", 25, 25, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_RESET", 26, 26, &umr_bitfield_default },
+	 { "SPARE_DQ_1_0", 27, 27, &umr_bitfield_default },
+	 { "DQ_1_1_BG_PWRON", 28, 28, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_RESET", 30, 30, &umr_bitfield_default },
+	 { "SPARE_DQ_1_1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_AD_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_0_0_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_0_1_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_1_0_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_1_1_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_2_D0[] = {
+	 { "CK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CKB_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CS_STATUS", 4, 5, &umr_bitfield_default },
+	 { "CKE_STATUS", 8, 8, &umr_bitfield_default },
+	 { "RAS_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CAS_STATUS", 10, 10, &umr_bitfield_default },
+	 { "WE_STATUS", 11, 11, &umr_bitfield_default },
+	 { "ADDR_STATUS", 16, 25, &umr_bitfield_default },
+	 { "ABI_STATUS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_2_D1[] = {
+	 { "CK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CKB_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CS_STATUS", 4, 5, &umr_bitfield_default },
+	 { "CKE_STATUS", 8, 8, &umr_bitfield_default },
+	 { "RAS_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CAS_STATUS", 10, 10, &umr_bitfield_default },
+	 { "WE_STATUS", 11, 11, &umr_bitfield_default },
+	 { "ADDR_STATUS", 16, 25, &umr_bitfield_default },
+	 { "ABI_STATUS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_CNTL_1[] = {
+	 { "PAUSE", 0, 0, &umr_bitfield_default },
+	 { "SEL_A_MSB", 8, 8, &umr_bitfield_default },
+	 { "SEL_B_MSB", 9, 9, &umr_bitfield_default },
+	 { "SEL_CH0_C_MSB", 10, 10, &umr_bitfield_default },
+	 { "SEL_CH0_D_MSB", 11, 11, &umr_bitfield_default },
+	 { "SEL_CH1_A_MSB", 12, 12, &umr_bitfield_default },
+	 { "SEL_CH1_B_MSB", 13, 13, &umr_bitfield_default },
+	 { "SEL_CH1_C_MSB", 14, 14, &umr_bitfield_default },
+	 { "SEL_CH1_D_MSB", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD2[] = {
+	 { "THRESHOLD_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD3[] = {
+	 { "CH0_LINK_RETRAIN_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CH1_LINK_RETRAIN_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_RETRAIN_STATUS", 2, 2, &umr_bitfield_default },
+	 { "RETRAIN_VBI", 3, 3, &umr_bitfield_default },
+	 { "RETRAIN_MONITOR", 4, 5, &umr_bitfield_default },
+	 { "CH0_LINK_RETRAIN_IN_PROGRESS", 8, 8, &umr_bitfield_default },
+	 { "CH1_LINK_RETRAIN_IN_PROGRESS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT8[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_11[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT9[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_12[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ADDR_DEC[] = {
+	 { "NO_DIV_BY_3", 0, 0, &umr_bitfield_default },
+	 { "GECC", 1, 1, &umr_bitfield_default },
+	 { "RB_SPLIT", 2, 2, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_REMOTE[] = {
+	 { "WRREQ_EN_GOQ", 0, 0, &umr_bitfield_default },
+	 { "RDREQ_EN_GOQ", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_PRI_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+	 { "HUB_LP_RDRET_SKID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_CHTRIREMAP[] = {
+	 { "CH0", 0, 1, &umr_bitfield_default },
+	 { "CH1", 2, 3, &umr_bitfield_default },
+	 { "CH2", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_TWOCHAN[] = {
+	 { "DISABLE_ONEPORT", 0, 0, &umr_bitfield_default },
+	 { "CH0", 1, 2, &umr_bitfield_default },
+	 { "CH1", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB[] = {
+	 { "HUBRD_HIGHEST", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_HUB_STALL_HIGHEST", 1, 1, &umr_bitfield_default },
+	 { "BREAK_BURST_CID_CHANGE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB_MAX_BURST[] = {
+	 { "RD_PORT0", 0, 3, &umr_bitfield_default },
+	 { "RD_PORT1", 4, 7, &umr_bitfield_default },
+	 { "RD_PORT2", 8, 11, &umr_bitfield_default },
+	 { "RD_PORT3", 12, 15, &umr_bitfield_default },
+	 { "WR_PORT0", 16, 19, &umr_bitfield_default },
+	 { "WR_PORT1", 20, 23, &umr_bitfield_default },
+	 { "WR_PORT2", 24, 27, &umr_bitfield_default },
+	 { "WR_PORT3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL0[] = {
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL1[] = {
+	 { "THRESH_CNTR_ID", 0, 7, &umr_bitfield_default },
+	 { "START_TRIG_ID", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_CNTL2[] = {
+	 { "MON0_ID", 0, 7, &umr_bitfield_default },
+	 { "MON1_ID", 8, 15, &umr_bitfield_default },
+	 { "MON2_ID", 16, 23, &umr_bitfield_default },
+	 { "MON3_ID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT2[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_RSLT3[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_PERF_MON_MAX_THSH[] = {
+	 { "MON0", 0, 7, &umr_bitfield_default },
+	 { "MON1", 8, 15, &umr_bitfield_default },
+	 { "MON2", 16, 23, &umr_bitfield_default },
+	 { "MON3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE0[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE1[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_CNTL[] = {
+	 { "DISABLE_ATC", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_PRI", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_PASID", 2, 2, &umr_bitfield_default },
+	 { "CREDITS_ATS_RPB", 8, 13, &umr_bitfield_default },
+	 { "DEBUG_ECO", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEBUG[] = {
+	 { "INVALIDATE_ALL", 0, 0, &umr_bitfield_default },
+	 { "IDENT_RETURN", 1, 1, &umr_bitfield_default },
+	 { "ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS", 2, 2, &umr_bitfield_default },
+	 { "PAGE_REQUESTS_USE_RELAXED_ORDERING", 5, 5, &umr_bitfield_default },
+	 { "PRIV_BIT", 6, 6, &umr_bitfield_default },
+	 { "EXE_BIT", 7, 7, &umr_bitfield_default },
+	 { "PAGE_REQUEST_PERMS", 8, 8, &umr_bitfield_default },
+	 { "UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE", 9, 9, &umr_bitfield_default },
+	 { "NUM_REQUESTS_AT_ERR", 10, 13, &umr_bitfield_default },
+	 { "DISALLOW_ERR_TO_DONE", 14, 14, &umr_bitfield_default },
+	 { "IGNORE_FED", 15, 15, &umr_bitfield_default },
+	 { "INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_BUS_SELECT", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_DEBUG[] = {
+	 { "CREDITS_ATS_IH", 0, 4, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES", 8, 8, &umr_bitfield_default },
+	 { "CLEAR_FAULT_STATUS_ADDR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "CRASHED", 1, 1, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_CNTL[] = {
+	 { "FAULT_REGISTER_LOG", 0, 5, &umr_bitfield_default },
+	 { "FAULT_INTERRUPT_TABLE", 10, 15, &umr_bitfield_default },
+	 { "FAULT_CRASH_TABLE", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_INFO[] = {
+	 { "FAULT_TYPE", 0, 5, &umr_bitfield_default },
+	 { "VMID", 10, 14, &umr_bitfield_default },
+	 { "EXTRA_INFO", 15, 15, &umr_bitfield_default },
+	 { "EXTRA_INFO2", 16, 16, &umr_bitfield_default },
+	 { "INVALIDATION", 17, 17, &umr_bitfield_default },
+	 { "PAGE_REQUEST", 18, 18, &umr_bitfield_default },
+	 { "STATUS", 19, 23, &umr_bitfield_default },
+	 { "PAGE_ADDR_HIGH", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_ADDR[] = {
+	 { "PAGE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_LOW[] = {
+	 { "DEFAULT_PAGE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_CNTL[] = {
+	 { "SEND_DEFAULT_PAGE", 0, 0, &umr_bitfield_default },
+	 { "DEFAULT_PAGE_HIGH", 2, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_MISC_CG[] = {
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL[] = {
+	 { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 4, 5, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 8, 8, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL2[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE", 8, 8, &umr_bitfield_default },
+	 { "L2_CACHE_SWAP_TAG_INDEX_LSBS", 9, 11, &umr_bitfield_default },
+	 { "L2_CACHE_VMID_MODE", 12, 14, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 15, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG[] = {
+	 { "CREDITS_L2_ATS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG2[] = {
+	 { "EFFECTIVE_CACHE_SIZE", 0, 4, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 5, 7, &umr_bitfield_default },
+	 { "FORCE_CACHE_MISS", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_CACHING_SPECULATIVE_READ_RETURNS", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_BUS_SELECT", 15, 16, &umr_bitfield_default },
+	 { "DEBUG_ECO", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_CNTL[] = {
+	 { "DONT_NEED_ATS_BEHAVIOR", 0, 1, &umr_bitfield_default },
+	 { "NEED_ATS_BEHAVIOR", 2, 2, &umr_bitfield_default },
+	 { "NEED_ATS_SNOOP_DEFAULT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_ADDRESS_OFFSET[] = {
+	 { "LOGICAL_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[] = {
+	 { "VMID0_REMAPPING_FINISHED", 0, 0, &umr_bitfield_default },
+	 { "VMID1_REMAPPING_FINISHED", 1, 1, &umr_bitfield_default },
+	 { "VMID2_REMAPPING_FINISHED", 2, 2, &umr_bitfield_default },
+	 { "VMID3_REMAPPING_FINISHED", 3, 3, &umr_bitfield_default },
+	 { "VMID4_REMAPPING_FINISHED", 4, 4, &umr_bitfield_default },
+	 { "VMID5_REMAPPING_FINISHED", 5, 5, &umr_bitfield_default },
+	 { "VMID6_REMAPPING_FINISHED", 6, 6, &umr_bitfield_default },
+	 { "VMID7_REMAPPING_FINISHED", 7, 7, &umr_bitfield_default },
+	 { "VMID8_REMAPPING_FINISHED", 8, 8, &umr_bitfield_default },
+	 { "VMID9_REMAPPING_FINISHED", 9, 9, &umr_bitfield_default },
+	 { "VMID10_REMAPPING_FINISHED", 10, 10, &umr_bitfield_default },
+	 { "VMID11_REMAPPING_FINISHED", 11, 11, &umr_bitfield_default },
+	 { "VMID12_REMAPPING_FINISHED", 12, 12, &umr_bitfield_default },
+	 { "VMID13_REMAPPING_FINISHED", 13, 13, &umr_bitfield_default },
+	 { "VMID14_REMAPPING_FINISHED", 14, 14, &umr_bitfield_default },
+	 { "VMID15_REMAPPING_FINISHED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID0_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID1_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID2_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID3_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID4_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID5_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID6_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID7_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID8_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID9_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID10_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID11_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID12_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID13_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID14_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID15_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT10[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_13[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_INDEX[] = {
+	 { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_DATA[] = {
+	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_EXECUTE[] = {
+	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW_START_PTR", 2, 11, &umr_bitfield_default },
+	 { "RENG_EXECUTE_DSP_END_PTR", 12, 21, &umr_bitfield_default },
+	 { "RENG_EXECUTE_END_PTR", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC[] = {
+	 { "RENG_EXECUTE_NOW_MODE", 10, 10, &umr_bitfield_default },
+	 { "RENG_EXECUTE_ON_REG_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "RENG_SRBM_CREDITS_MCD", 12, 15, &umr_bitfield_default },
+	 { "STCTRL_STUTTER_EN", 16, 16, &umr_bitfield_default },
+	 { "STCTRL_GMC_IDLE_THRESHOLD", 17, 18, &umr_bitfield_default },
+	 { "STCTRL_SRBM_IDLE_THRESHOLD", 19, 20, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PRE_SR", 21, 21, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STOP", 22, 22, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_SR_COMMIT", 23, 23, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PROTECTION_FAULT", 24, 24, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_ALLOW_SR", 25, 25, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_GMC_OFFLINE", 26, 26, &umr_bitfield_default },
+	 { "CRITICAL_REGS_LOCK", 27, 27, &umr_bitfield_default },
+	 { "ALLOW_DEEP_SLEEP_MODE", 28, 30, &umr_bitfield_default },
+	 { "STCTRL_FORCE_ALLOW_SR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC2[] = {
+	 { "GMCON_MISC2_RESERVED0", 0, 5, &umr_bitfield_default },
+	 { "STCTRL_NONDISP_IDLE_THRESHOLD", 6, 10, &umr_bitfield_default },
+	 { "RENG_SR_HOLD_THRESHOLD", 11, 16, &umr_bitfield_default },
+	 { "GMCON_MISC2_RESERVED1", 17, 28, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ARB_BUSY", 29, 29, &umr_bitfield_default },
+	 { "STCTRL_EXTEND_GMC_OFFLINE", 30, 30, &umr_bitfield_default },
+	 { "STCTRL_TIMER_PULSE_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE1", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL0[] = {
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+	 { "THRESH_CNTR_ID_EXT", 29, 29, &umr_bitfield_default },
+	 { "START_TRIG_ID_EXT", 30, 30, &umr_bitfield_default },
+	 { "STOP_TRIG_ID_EXT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL1[] = {
+	 { "THRESH_CNTR_ID", 0, 5, &umr_bitfield_default },
+	 { "START_TRIG_ID", 6, 11, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 12, 17, &umr_bitfield_default },
+	 { "MON0_ID", 18, 24, &umr_bitfield_default },
+	 { "MON1_ID", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE", 12, 12, &umr_bitfield_default },
+	 { "READ", 13, 13, &umr_bitfield_default },
+	 { "RSRVD", 14, 26, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_WRITE[] = {
+	 { "WRITE_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_READ[] = {
+	 { "READ_VALUE", 0, 23, &umr_bitfield_default },
+	 { "PGFSM_SELECT", 24, 27, &umr_bitfield_default },
+	 { "SERDES_MASTER_BUSY", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC3[] = {
+	 { "RENG_DISABLE_MCC", 0, 7, &umr_bitfield_default },
+	 { "RENG_DISABLE_MCD", 8, 15, &umr_bitfield_default },
+	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 16, 27, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STUTTER", 28, 28, &umr_bitfield_default },
+	 { "RENG_MEM_LS_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "STCTRL_EXCLUDE_NONMEM_CLIENTS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MASK[] = {
+	 { "STCTRL_BUSY_MASK_ACP_RD", 0, 0, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_ACP_WR", 1, 1, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_VCE_RD", 2, 2, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_VCE_WR", 3, 3, &umr_bitfield_default },
+	 { "STCTRL_SR_HANDSHAKE_MASK", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_LPT_TARGET[] = {
+	 { "STCTRL_LPT_TARGET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_DEBUG[] = {
+	 { "GFX_STALL", 0, 0, &umr_bitfield_default },
+	 { "GFX_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "MISC_FLAGS", 2, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CNTL_3[] = {
+	 { "PIPE_DELAY_OUT_D0", 0, 2, &umr_bitfield_default },
+	 { "PIPE_DELAY_IN_D0", 3, 5, &umr_bitfield_default },
+	 { "PIPE_DELAY_OUT_D1", 6, 8, &umr_bitfield_default },
+	 { "PIPE_DELAY_IN_D1", 9, 11, &umr_bitfield_default },
+	 { "REPCG_EN_D0", 12, 12, &umr_bitfield_default },
+	 { "REPCG_EN_D1", 13, 13, &umr_bitfield_default },
+	 { "REPCG_OFF_DLY", 16, 19, &umr_bitfield_default },
+	 { "FCK_FRC", 20, 20, &umr_bitfield_default },
+	 { "DBI_FRC", 21, 21, &umr_bitfield_default },
+	 { "PRGRM_CDC", 22, 22, &umr_bitfield_default },
+	 { "DQS_FRC", 23, 23, &umr_bitfield_default },
+	 { "DQS_FRC_PAT", 24, 27, &umr_bitfield_default },
+	 { "IDSC_EN", 30, 30, &umr_bitfield_default },
+	 { "CAC_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CTRL[] = {
+	 { "CH0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CH1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "WCKOFF_EARLY", 2, 2, &umr_bitfield_default },
+	 { "WCKOFF_LATE", 3, 3, &umr_bitfield_default },
+	 { "TPD2MRS", 4, 9, &umr_bitfield_default },
+	 { "TMRS2WCK", 12, 15, &umr_bitfield_default },
+	 { "TWCK2MRS", 16, 19, &umr_bitfield_default },
+	 { "TMRD", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CTRL_LP[] = {
+	 { "CH0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CH1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "WCKOFF_EARLY", 2, 2, &umr_bitfield_default },
+	 { "WCKOFF_LATE", 3, 3, &umr_bitfield_default },
+	 { "TPD2MRS", 4, 9, &umr_bitfield_default },
+	 { "TMRS2WCK", 12, 15, &umr_bitfield_default },
+	 { "TWCK2MRS", 16, 19, &umr_bitfield_default },
+	 { "TMRD", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CMD0[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CMD0_LP[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CMD1[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CMD1_LP[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SREG_READ[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SREG_STATUS[] = {
+	 { "AVAIL_RTN", 0, 3, &umr_bitfield_default },
+	 { "PND_RD", 8, 11, &umr_bitfield_default },
+	 { "PND_WR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PHYREG_BCAST[] = {
+	 { "CH0_EN", 0, 0, &umr_bitfield_default },
+	 { "CH1_EN", 1, 1, &umr_bitfield_default },
+	 { "CKE_MASK", 7, 7, &umr_bitfield_default },
+	 { "DQ_MASK", 8, 8, &umr_bitfield_default },
+	 { "DBI_MASK", 9, 9, &umr_bitfield_default },
+	 { "EDC_MASK", 10, 10, &umr_bitfield_default },
+	 { "WCK_MASK", 11, 11, &umr_bitfield_default },
+	 { "WCDR_MASK", 12, 12, &umr_bitfield_default },
+	 { "CLK_MASK", 13, 13, &umr_bitfield_default },
+	 { "CMD_MASK", 14, 14, &umr_bitfield_default },
+	 { "ADR_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_DVS_CTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TDVS", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_DVS_CTL_LP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TDVS", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_DVS_CMD[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 23, 23, &umr_bitfield_default },
+	 { "ADR_MSB0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_DVS_CMD_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 23, 23, &umr_bitfield_default },
+	 { "ADR_MSB0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DLL_STBY[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "VCTRLADC_FRC", 1, 1, &umr_bitfield_default },
+	 { "VCTRLADC_VAL", 2, 2, &umr_bitfield_default },
+	 { "MSTRSTBY_FRC", 3, 3, &umr_bitfield_default },
+	 { "MSTRSTBY_VAL", 4, 4, &umr_bitfield_default },
+	 { "ENTR_DLY", 5, 7, &umr_bitfield_default },
+	 { "STBY_DLY", 8, 11, &umr_bitfield_default },
+	 { "TCKE_PULSE_EXTN", 12, 15, &umr_bitfield_default },
+	 { "TCKE_EXTN", 16, 23, &umr_bitfield_default },
+	 { "EXIT_DLY", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DLL_STBY_LP[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "VCTRLADC_FRC", 1, 1, &umr_bitfield_default },
+	 { "VCTRLADC_VAL", 2, 2, &umr_bitfield_default },
+	 { "MSTRSTBY_FRC", 3, 3, &umr_bitfield_default },
+	 { "MSTRSTBY_VAL", 4, 4, &umr_bitfield_default },
+	 { "ENTR_DLY", 5, 7, &umr_bitfield_default },
+	 { "STBY_DLY", 8, 11, &umr_bitfield_default },
+	 { "TCKE_PULSE_EXTN", 12, 15, &umr_bitfield_default },
+	 { "TCKE_EXTN", 16, 23, &umr_bitfield_default },
+	 { "EXIT_DLY", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_MISCCTRL0[] = {
+	 { "UDD_ON_STATUS_BITS", 0, 0, &umr_bitfield_default },
+	 { "LOAD_DATA_SEL", 1, 1, &umr_bitfield_default },
+	 { "LOAD_UDD", 2, 2, &umr_bitfield_default },
+	 { "ADR_STATUS_SEL", 3, 3, &umr_bitfield_default },
+	 { "DATA_SEL", 4, 7, &umr_bitfield_default },
+	 { "PRBS_CHK_LOAD_CNT", 8, 14, &umr_bitfield_default },
+	 { "UDD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_MISCCTRL1[] = {
+	 { "PRBS_ERR_CNT_LIMIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_MISCCTRL2[] = {
+	 { "PRBS_RUN_LENGTH", 0, 16, &umr_bitfield_default },
+	 { "PRBS_FREERUN", 17, 17, &umr_bitfield_default },
+	 { "PRBS15_MODE", 18, 18, &umr_bitfield_default },
+	 { "PRBS23_MODE", 19, 19, &umr_bitfield_default },
+	 { "STOP_ON_NEXT_ERR", 20, 20, &umr_bitfield_default },
+	 { "STOP_CLK", 21, 21, &umr_bitfield_default },
+	 { "SWEEP_DLY", 24, 25, &umr_bitfield_default },
+	 { "GRAY_CODE_EN", 26, 26, &umr_bitfield_default },
+	 { "SEL_PHY_PRBS_CHK", 28, 28, &umr_bitfield_default },
+	 { "SEL_AC_PRBS_CHK", 29, 29, &umr_bitfield_default },
+	 { "STATUS_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_CONFIG0[] = {
+	 { "CONF_EN_CH0", 0, 0, &umr_bitfield_default },
+	 { "CONF_EN_CH1", 1, 1, &umr_bitfield_default },
+	 { "CONF_AUTO_EN", 2, 2, &umr_bitfield_default },
+	 { "MASK", 4, 7, &umr_bitfield_default },
+	 { "PTR", 8, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_CONFIG1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_SETUP[] = {
+	 { "DLB_EN", 0, 0, &umr_bitfield_default },
+	 { "DLB_FIFO_EN", 1, 1, &umr_bitfield_default },
+	 { "DLB_STATUS_EN", 2, 2, &umr_bitfield_default },
+	 { "DLB_CONFIG_EN", 3, 3, &umr_bitfield_default },
+	 { "DLB_PRBS_EN", 4, 4, &umr_bitfield_default },
+	 { "PRBS_GEN_RST", 5, 5, &umr_bitfield_default },
+	 { "PRBS_CHK_RST", 6, 6, &umr_bitfield_default },
+	 { "PRBS_PHY_RST", 7, 7, &umr_bitfield_default },
+	 { "QDR_MODE", 8, 8, &umr_bitfield_default },
+	 { "CHK_DATA_BITS", 16, 23, &umr_bitfield_default },
+	 { "MEM_BIT_SEL", 24, 28, &umr_bitfield_default },
+	 { "RXTXLP_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_SETUPSWEEP[] = {
+	 { "DLL_RST", 0, 0, &umr_bitfield_default },
+	 { "CONFIG", 1, 1, &umr_bitfield_default },
+	 { "MASTER", 2, 2, &umr_bitfield_default },
+	 { "DLLDLY", 4, 7, &umr_bitfield_default },
+	 { "DLLSTEPS", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_SETUPFIFO[] = {
+	 { "WRITE_FIFO_RST", 0, 0, &umr_bitfield_default },
+	 { "READ_FIFO_RST", 1, 1, &umr_bitfield_default },
+	 { "BOTH_FIFO_RST", 2, 2, &umr_bitfield_default },
+	 { "SYNC_RST", 3, 3, &umr_bitfield_default },
+	 { "SYNC_RST_MASK", 4, 5, &umr_bitfield_default },
+	 { "OUTPUT_EN_RST", 6, 6, &umr_bitfield_default },
+	 { "SHIFT_WR_FIFO_PTR", 8, 9, &umr_bitfield_default },
+	 { "DELAY_RD_FIFO_PTR", 10, 12, &umr_bitfield_default },
+	 { "STROBE", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_WRITE_MASK[] = {
+	 { "BIT_MASK", 0, 21, &umr_bitfield_default },
+	 { "CH_MASK", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS[] = {
+	 { "STICK_ERROR", 0, 3, &umr_bitfield_default },
+	 { "LOCK", 4, 7, &umr_bitfield_default },
+	 { "SWEEP_DONE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_EN_RD[] = {
+	 { "TX_PRI", 0, 7, &umr_bitfield_default },
+	 { "BW_PRI", 8, 15, &umr_bitfield_default },
+	 { "FIX_PRI", 16, 23, &umr_bitfield_default },
+	 { "ST_PRI", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_EN_WR[] = {
+	 { "TX_PRI", 0, 7, &umr_bitfield_default },
+	 { "BW_PRI", 8, 15, &umr_bitfield_default },
+	 { "FIX_PRI", 16, 23, &umr_bitfield_default },
+	 { "ST_PRI", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_CTL_RD[] = {
+	 { "FORCE_HIGHEST", 0, 7, &umr_bitfield_default },
+	 { "HARSH_RR", 8, 8, &umr_bitfield_default },
+	 { "BANK_AGE_ONLY", 9, 9, &umr_bitfield_default },
+	 { "USE_LEGACY_HARSH", 10, 10, &umr_bitfield_default },
+	 { "BWCNT_CATCHUP", 11, 11, &umr_bitfield_default },
+	 { "ST_MODE", 12, 13, &umr_bitfield_default },
+	 { "FORCE_STALL", 14, 21, &umr_bitfield_default },
+	 { "PERF_MON_SEL", 22, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_CTL_WR[] = {
+	 { "FORCE_HIGHEST", 0, 7, &umr_bitfield_default },
+	 { "HARSH_RR", 8, 8, &umr_bitfield_default },
+	 { "BANK_AGE_ONLY", 9, 9, &umr_bitfield_default },
+	 { "USE_LEGACY_HARSH", 10, 10, &umr_bitfield_default },
+	 { "BWCNT_CATCHUP", 11, 11, &umr_bitfield_default },
+	 { "ST_MODE", 12, 13, &umr_bitfield_default },
+	 { "FORCE_STALL", 14, 21, &umr_bitfield_default },
+	 { "PERF_MON_SEL", 22, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_SPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_MPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_CCPU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_SPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_MPS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_MPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_CCPU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDV[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDV[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDS[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDT[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDU[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDV[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDW[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDX[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDY[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDZ[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDS[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDT[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDU[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDV[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BP2[] = {
+	 { "RDRET", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_14[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_15[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gmc71_regs.i b/src/lib/ip/gmc71_regs.i
new file mode 100644
index 0000000..415cf3e
--- /dev/null
+++ b/src/lib/ip/gmc71_regs.i
@@ -0,0 +1,1432 @@
+	{ "ixMC_TSM_DEBUG_GCNT", REG_SMC, 0x0, &ixMC_TSM_DEBUG_GCNT[0], sizeof(ixMC_TSM_DEBUG_GCNT)/sizeof(ixMC_TSM_DEBUG_GCNT[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_0", REG_SMC, 0x0, &ixMC_IO_DEBUG_UP_0[0], sizeof(ixMC_IO_DEBUG_UP_0)/sizeof(ixMC_IO_DEBUG_UP_0[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_FLAG", REG_SMC, 0x1, &ixMC_TSM_DEBUG_FLAG[0], sizeof(ixMC_TSM_DEBUG_FLAG)/sizeof(ixMC_TSM_DEBUG_FLAG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_1", REG_SMC, 0x1, &ixMC_IO_DEBUG_UP_1[0], sizeof(ixMC_IO_DEBUG_UP_1)/sizeof(ixMC_IO_DEBUG_UP_1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_ST01", REG_SMC, 0x10, &ixMC_TSM_DEBUG_ST01[0], sizeof(ixMC_TSM_DEBUG_ST01)/sizeof(ixMC_TSM_DEBUG_ST01[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RXPHASE_D0", REG_SMC, 0x100, &ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RXPHASE_D0", REG_SMC, 0x101, &ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RXPHASE_D0", REG_SMC, 0x102, &ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RXPHASE_D0", REG_SMC, 0x103, &ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RXPHASE_D0", REG_SMC, 0x104, &ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RXPHASE_D0", REG_SMC, 0x105, &ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RXPHASE_D0", REG_SMC, 0x106, &ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RXPHASE_D0", REG_SMC, 0x107, &ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RXPHASE_D0", REG_SMC, 0x108, &ixMC_IO_DEBUG_DBI_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RXPHASE_D0", REG_SMC, 0x109, &ixMC_IO_DEBUG_EDC_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RXPHASE_D0", REG_SMC, 0x10a, &ixMC_IO_DEBUG_WCK_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_RXPHASE_D0", REG_SMC, 0x10b, &ixMC_IO_DEBUG_CK_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_RXPHASE_D0", REG_SMC, 0x10c, &ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_RXPHASE_D0", REG_SMC, 0x10d, &ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_RXPHASE_D0", REG_SMC, 0x10e, &ixMC_IO_DEBUG_ACMD_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RXPHASE_D0", REG_SMC, 0x10f, &ixMC_IO_DEBUG_CMD_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_ST23", REG_SMC, 0x11, &ixMC_TSM_DEBUG_ST23[0], sizeof(ixMC_TSM_DEBUG_ST23)/sizeof(ixMC_TSM_DEBUG_ST23[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RXPHASE_D1", REG_SMC, 0x110, &ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RXPHASE_D1", REG_SMC, 0x111, &ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RXPHASE_D1", REG_SMC, 0x112, &ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RXPHASE_D1", REG_SMC, 0x113, &ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RXPHASE_D1", REG_SMC, 0x114, &ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RXPHASE_D1", REG_SMC, 0x115, &ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RXPHASE_D1", REG_SMC, 0x116, &ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RXPHASE_D1", REG_SMC, 0x117, &ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RXPHASE_D1", REG_SMC, 0x118, &ixMC_IO_DEBUG_DBI_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RXPHASE_D1", REG_SMC, 0x119, &ixMC_IO_DEBUG_EDC_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RXPHASE_D1", REG_SMC, 0x11a, &ixMC_IO_DEBUG_WCK_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_RXPHASE_D1", REG_SMC, 0x11b, &ixMC_IO_DEBUG_CK_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_RXPHASE_D1", REG_SMC, 0x11c, &ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_RXPHASE_D1", REG_SMC, 0x11d, &ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_RXPHASE_D1", REG_SMC, 0x11e, &ixMC_IO_DEBUG_ACMD_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RXPHASE_D1", REG_SMC, 0x11f, &ixMC_IO_DEBUG_CMD_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_ST45", REG_SMC, 0x12, &ixMC_TSM_DEBUG_ST45[0], sizeof(ixMC_TSM_DEBUG_ST45)/sizeof(ixMC_TSM_DEBUG_ST45[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXPHASE_D0", REG_SMC, 0x120, &ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXPHASE_D0", REG_SMC, 0x121, &ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXPHASE_D0", REG_SMC, 0x122, &ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXPHASE_D0", REG_SMC, 0x123, &ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXPHASE_D0", REG_SMC, 0x124, &ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXPHASE_D0", REG_SMC, 0x125, &ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXPHASE_D0", REG_SMC, 0x126, &ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXPHASE_D0", REG_SMC, 0x127, &ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXPHASE_D0", REG_SMC, 0x128, &ixMC_IO_DEBUG_DBI_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXPHASE_D0", REG_SMC, 0x129, &ixMC_IO_DEBUG_EDC_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXPHASE_D0", REG_SMC, 0x12a, &ixMC_IO_DEBUG_WCK_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXPHASE_D0", REG_SMC, 0x12b, &ixMC_IO_DEBUG_CK_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXPHASE_D0", REG_SMC, 0x12c, &ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXPHASE_D0", REG_SMC, 0x12d, &ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXPHASE_D0", REG_SMC, 0x12e, &ixMC_IO_DEBUG_ACMD_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXPHASE_D0", REG_SMC, 0x12f, &ixMC_IO_DEBUG_CMD_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BKPT", REG_SMC, 0x13, &ixMC_TSM_DEBUG_BKPT[0], sizeof(ixMC_TSM_DEBUG_BKPT)/sizeof(ixMC_TSM_DEBUG_BKPT[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXPHASE_D1", REG_SMC, 0x130, &ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXPHASE_D1", REG_SMC, 0x131, &ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXPHASE_D1", REG_SMC, 0x132, &ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXPHASE_D1", REG_SMC, 0x133, &ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXPHASE_D1", REG_SMC, 0x134, &ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXPHASE_D1", REG_SMC, 0x135, &ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXPHASE_D1", REG_SMC, 0x136, &ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXPHASE_D1", REG_SMC, 0x137, &ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXPHASE_D1", REG_SMC, 0x138, &ixMC_IO_DEBUG_DBI_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXPHASE_D1", REG_SMC, 0x139, &ixMC_IO_DEBUG_EDC_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXPHASE_D1", REG_SMC, 0x13a, &ixMC_IO_DEBUG_WCK_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXPHASE_D1", REG_SMC, 0x13b, &ixMC_IO_DEBUG_CK_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXPHASE_D1", REG_SMC, 0x13c, &ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXPHASE_D1", REG_SMC, 0x13d, &ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXPHASE_D1", REG_SMC, 0x13e, &ixMC_IO_DEBUG_ACMD_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXPHASE_D1", REG_SMC, 0x13f, &ixMC_IO_DEBUG_CMD_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_20", REG_SMC, 0x14, &ixMC_IO_DEBUG_UP_20[0], sizeof(ixMC_IO_DEBUG_UP_20)/sizeof(ixMC_IO_DEBUG_UP_20[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0", REG_SMC, 0x140, &ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0", REG_SMC, 0x141, &ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0", REG_SMC, 0x142, &ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0", REG_SMC, 0x143, &ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0", REG_SMC, 0x144, &ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0", REG_SMC, 0x145, &ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0", REG_SMC, 0x146, &ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0", REG_SMC, 0x147, &ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0", REG_SMC, 0x148, &ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0", REG_SMC, 0x149, &ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0", REG_SMC, 0x14a, &ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0", REG_SMC, 0x14b, &ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0", REG_SMC, 0x14c, &ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0", REG_SMC, 0x14d, &ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0", REG_SMC, 0x14e, &ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0", REG_SMC, 0x14f, &ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_21", REG_SMC, 0x15, &ixMC_IO_DEBUG_UP_21[0], sizeof(ixMC_IO_DEBUG_UP_21)/sizeof(ixMC_IO_DEBUG_UP_21[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1", REG_SMC, 0x150, &ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1", REG_SMC, 0x151, &ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1", REG_SMC, 0x152, &ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1", REG_SMC, 0x153, &ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1", REG_SMC, 0x154, &ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1", REG_SMC, 0x155, &ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1", REG_SMC, 0x156, &ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1", REG_SMC, 0x157, &ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1", REG_SMC, 0x158, &ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1", REG_SMC, 0x159, &ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1", REG_SMC, 0x15a, &ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1", REG_SMC, 0x15b, &ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1", REG_SMC, 0x15c, &ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1", REG_SMC, 0x15d, &ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1", REG_SMC, 0x15e, &ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1", REG_SMC, 0x15f, &ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_22", REG_SMC, 0x16, &ixMC_IO_DEBUG_UP_22[0], sizeof(ixMC_IO_DEBUG_UP_22)/sizeof(ixMC_IO_DEBUG_UP_22[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXSLF_D0", REG_SMC, 0x160, &ixMC_IO_DEBUG_DQB0L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXSLF_D0", REG_SMC, 0x161, &ixMC_IO_DEBUG_DQB0H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXSLF_D0", REG_SMC, 0x162, &ixMC_IO_DEBUG_DQB1L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXSLF_D0", REG_SMC, 0x163, &ixMC_IO_DEBUG_DQB1H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXSLF_D0", REG_SMC, 0x164, &ixMC_IO_DEBUG_DQB2L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXSLF_D0", REG_SMC, 0x165, &ixMC_IO_DEBUG_DQB2H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXSLF_D0", REG_SMC, 0x166, &ixMC_IO_DEBUG_DQB3L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXSLF_D0", REG_SMC, 0x167, &ixMC_IO_DEBUG_DQB3H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXSLF_D0", REG_SMC, 0x168, &ixMC_IO_DEBUG_DBI_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXSLF_D0", REG_SMC, 0x169, &ixMC_IO_DEBUG_EDC_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXSLF_D0", REG_SMC, 0x16a, &ixMC_IO_DEBUG_WCK_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXSLF_D0", REG_SMC, 0x16b, &ixMC_IO_DEBUG_CK_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_CK_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXSLF_D0", REG_SMC, 0x16c, &ixMC_IO_DEBUG_ADDRL_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXSLF_D0", REG_SMC, 0x16d, &ixMC_IO_DEBUG_ADDRH_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXSLF_D0", REG_SMC, 0x16e, &ixMC_IO_DEBUG_ACMD_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXSLF_D0", REG_SMC, 0x16f, &ixMC_IO_DEBUG_CMD_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_23", REG_SMC, 0x17, &ixMC_IO_DEBUG_UP_23[0], sizeof(ixMC_IO_DEBUG_UP_23)/sizeof(ixMC_IO_DEBUG_UP_23[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXSLF_D1", REG_SMC, 0x170, &ixMC_IO_DEBUG_DQB0L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXSLF_D1", REG_SMC, 0x171, &ixMC_IO_DEBUG_DQB0H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXSLF_D1", REG_SMC, 0x172, &ixMC_IO_DEBUG_DQB1L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXSLF_D1", REG_SMC, 0x173, &ixMC_IO_DEBUG_DQB1H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXSLF_D1", REG_SMC, 0x174, &ixMC_IO_DEBUG_DQB2L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXSLF_D1", REG_SMC, 0x175, &ixMC_IO_DEBUG_DQB2H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXSLF_D1", REG_SMC, 0x176, &ixMC_IO_DEBUG_DQB3L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXSLF_D1", REG_SMC, 0x177, &ixMC_IO_DEBUG_DQB3H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXSLF_D1", REG_SMC, 0x178, &ixMC_IO_DEBUG_DBI_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXSLF_D1", REG_SMC, 0x179, &ixMC_IO_DEBUG_EDC_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXSLF_D1", REG_SMC, 0x17a, &ixMC_IO_DEBUG_WCK_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXSLF_D1", REG_SMC, 0x17b, &ixMC_IO_DEBUG_CK_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_CK_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXSLF_D1", REG_SMC, 0x17c, &ixMC_IO_DEBUG_ADDRL_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXSLF_D1", REG_SMC, 0x17d, &ixMC_IO_DEBUG_ADDRH_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXSLF_D1", REG_SMC, 0x17e, &ixMC_IO_DEBUG_ACMD_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXSLF_D1", REG_SMC, 0x17f, &ixMC_IO_DEBUG_CMD_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_24", REG_SMC, 0x18, &ixMC_IO_DEBUG_UP_24[0], sizeof(ixMC_IO_DEBUG_UP_24)/sizeof(ixMC_IO_DEBUG_UP_24[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0", REG_SMC, 0x180, &ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0", REG_SMC, 0x181, &ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0", REG_SMC, 0x182, &ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0", REG_SMC, 0x183, &ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0", REG_SMC, 0x184, &ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0", REG_SMC, 0x185, &ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0", REG_SMC, 0x186, &ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0", REG_SMC, 0x187, &ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PD_D0", REG_SMC, 0x188, &ixMC_IO_DEBUG_DBI_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PD_D0", REG_SMC, 0x189, &ixMC_IO_DEBUG_EDC_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PD_D0", REG_SMC, 0x18a, &ixMC_IO_DEBUG_WCK_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PD_D0", REG_SMC, 0x18b, &ixMC_IO_DEBUG_CK_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0", REG_SMC, 0x18c, &ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0", REG_SMC, 0x18d, &ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PD_D0", REG_SMC, 0x18e, &ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PD_D0", REG_SMC, 0x18f, &ixMC_IO_DEBUG_CMD_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_25", REG_SMC, 0x19, &ixMC_IO_DEBUG_UP_25[0], sizeof(ixMC_IO_DEBUG_UP_25)/sizeof(ixMC_IO_DEBUG_UP_25[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1", REG_SMC, 0x190, &ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1", REG_SMC, 0x191, &ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1", REG_SMC, 0x192, &ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1", REG_SMC, 0x193, &ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1", REG_SMC, 0x194, &ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1", REG_SMC, 0x195, &ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1", REG_SMC, 0x196, &ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1", REG_SMC, 0x197, &ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PD_D1", REG_SMC, 0x198, &ixMC_IO_DEBUG_DBI_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PD_D1", REG_SMC, 0x199, &ixMC_IO_DEBUG_EDC_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PD_D1", REG_SMC, 0x19a, &ixMC_IO_DEBUG_WCK_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PD_D1", REG_SMC, 0x19b, &ixMC_IO_DEBUG_CK_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1", REG_SMC, 0x19c, &ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1", REG_SMC, 0x19d, &ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PD_D1", REG_SMC, 0x19e, &ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PD_D1", REG_SMC, 0x19f, &ixMC_IO_DEBUG_CMD_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_26", REG_SMC, 0x1a, &ixMC_IO_DEBUG_UP_26[0], sizeof(ixMC_IO_DEBUG_UP_26)/sizeof(ixMC_IO_DEBUG_UP_26[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0", REG_SMC, 0x1a0, &ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0", REG_SMC, 0x1a1, &ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0", REG_SMC, 0x1a2, &ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0", REG_SMC, 0x1a3, &ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0", REG_SMC, 0x1a4, &ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0", REG_SMC, 0x1a5, &ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0", REG_SMC, 0x1a6, &ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0", REG_SMC, 0x1a7, &ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PU_D0", REG_SMC, 0x1a8, &ixMC_IO_DEBUG_DBI_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PU_D0", REG_SMC, 0x1a9, &ixMC_IO_DEBUG_EDC_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PU_D0", REG_SMC, 0x1aa, &ixMC_IO_DEBUG_WCK_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PU_D0", REG_SMC, 0x1ab, &ixMC_IO_DEBUG_CK_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0", REG_SMC, 0x1ac, &ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0", REG_SMC, 0x1ad, &ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PU_D0", REG_SMC, 0x1ae, &ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PU_D0", REG_SMC, 0x1af, &ixMC_IO_DEBUG_CMD_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_27", REG_SMC, 0x1b, &ixMC_IO_DEBUG_UP_27[0], sizeof(ixMC_IO_DEBUG_UP_27)/sizeof(ixMC_IO_DEBUG_UP_27[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1", REG_SMC, 0x1b0, &ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1", REG_SMC, 0x1b1, &ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1", REG_SMC, 0x1b2, &ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1", REG_SMC, 0x1b3, &ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1", REG_SMC, 0x1b4, &ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1", REG_SMC, 0x1b5, &ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1", REG_SMC, 0x1b6, &ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1", REG_SMC, 0x1b7, &ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PU_D1", REG_SMC, 0x1b8, &ixMC_IO_DEBUG_DBI_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PU_D1", REG_SMC, 0x1b9, &ixMC_IO_DEBUG_EDC_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PU_D1", REG_SMC, 0x1ba, &ixMC_IO_DEBUG_WCK_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PU_D1", REG_SMC, 0x1bb, &ixMC_IO_DEBUG_CK_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1", REG_SMC, 0x1bc, &ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1", REG_SMC, 0x1bd, &ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PU_D1", REG_SMC, 0x1be, &ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PU_D1", REG_SMC, 0x1bf, &ixMC_IO_DEBUG_CMD_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_28", REG_SMC, 0x1c, &ixMC_IO_DEBUG_UP_28[0], sizeof(ixMC_IO_DEBUG_UP_28)/sizeof(ixMC_IO_DEBUG_UP_28[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_EQ_D0", REG_SMC, 0x1c0, &ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_EQ_D0", REG_SMC, 0x1c1, &ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_EQ_D0", REG_SMC, 0x1c2, &ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_EQ_D0", REG_SMC, 0x1c3, &ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_EQ_D0", REG_SMC, 0x1c4, &ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_EQ_D0", REG_SMC, 0x1c5, &ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_EQ_D0", REG_SMC, 0x1c6, &ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_EQ_D0", REG_SMC, 0x1c7, &ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_EQ_D0", REG_SMC, 0x1c8, &ixMC_IO_DEBUG_DBI_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_D0", REG_SMC, 0x1c9, &ixMC_IO_DEBUG_EDC_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_EQ_D0", REG_SMC, 0x1ca, &ixMC_IO_DEBUG_WCK_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0", REG_SMC, 0x1cb, &ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0", REG_SMC, 0x1cc, &ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0", REG_SMC, 0x1cd, &ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0", REG_SMC, 0x1ce, &ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RX_EQ_D0", REG_SMC, 0x1cf, &ixMC_IO_DEBUG_CMD_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_29", REG_SMC, 0x1d, &ixMC_IO_DEBUG_UP_29[0], sizeof(ixMC_IO_DEBUG_UP_29)/sizeof(ixMC_IO_DEBUG_UP_29[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_EQ_D1", REG_SMC, 0x1d0, &ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_EQ_D1", REG_SMC, 0x1d1, &ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_EQ_D1", REG_SMC, 0x1d2, &ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_EQ_D1", REG_SMC, 0x1d3, &ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_EQ_D1", REG_SMC, 0x1d4, &ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_EQ_D1", REG_SMC, 0x1d5, &ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_EQ_D1", REG_SMC, 0x1d6, &ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_EQ_D1", REG_SMC, 0x1d7, &ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_EQ_D1", REG_SMC, 0x1d8, &ixMC_IO_DEBUG_DBI_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_D1", REG_SMC, 0x1d9, &ixMC_IO_DEBUG_EDC_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_EQ_D1", REG_SMC, 0x1da, &ixMC_IO_DEBUG_WCK_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1", REG_SMC, 0x1db, &ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1", REG_SMC, 0x1dc, &ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1", REG_SMC, 0x1dd, &ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1", REG_SMC, 0x1de, &ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RX_EQ_D1", REG_SMC, 0x1df, &ixMC_IO_DEBUG_CMD_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_30", REG_SMC, 0x1e, &ixMC_IO_DEBUG_UP_30[0], sizeof(ixMC_IO_DEBUG_UP_30)/sizeof(ixMC_IO_DEBUG_UP_30[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_MISC_D0", REG_SMC, 0x1e0, &ixMC_IO_DEBUG_WCDR_MISC_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_MISC_D0)/sizeof(ixMC_IO_DEBUG_WCDR_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CLKSEL_D0", REG_SMC, 0x1e1, &ixMC_IO_DEBUG_WCDR_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_OFSCAL_D0", REG_SMC, 0x1e2, &ixMC_IO_DEBUG_WCDR_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RXPHASE_D0", REG_SMC, 0x1e3, &ixMC_IO_DEBUG_WCDR_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXPHASE_D0", REG_SMC, 0x1e4, &ixMC_IO_DEBUG_WCDR_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0", REG_SMC, 0x1e5, &ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXSLF_D0", REG_SMC, 0x1e6, &ixMC_IO_DEBUG_WCDR_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PD_D0", REG_SMC, 0x1e7, &ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PU_D0", REG_SMC, 0x1e8, &ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_D0", REG_SMC, 0x1e9, &ixMC_IO_DEBUG_WCDR_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0", REG_SMC, 0x1ea, &ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0", REG_SMC, 0x1eb, &ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0", REG_SMC, 0x1ec, &ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_31", REG_SMC, 0x1f, &ixMC_IO_DEBUG_UP_31[0], sizeof(ixMC_IO_DEBUG_UP_31)/sizeof(ixMC_IO_DEBUG_UP_31[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_MISC_D1", REG_SMC, 0x1f0, &ixMC_IO_DEBUG_WCDR_MISC_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_MISC_D1)/sizeof(ixMC_IO_DEBUG_WCDR_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CLKSEL_D1", REG_SMC, 0x1f1, &ixMC_IO_DEBUG_WCDR_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_OFSCAL_D1", REG_SMC, 0x1f2, &ixMC_IO_DEBUG_WCDR_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RXPHASE_D1", REG_SMC, 0x1f3, &ixMC_IO_DEBUG_WCDR_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXPHASE_D1", REG_SMC, 0x1f4, &ixMC_IO_DEBUG_WCDR_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1", REG_SMC, 0x1f5, &ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXSLF_D1", REG_SMC, 0x1f6, &ixMC_IO_DEBUG_WCDR_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PD_D1", REG_SMC, 0x1f7, &ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PU_D1", REG_SMC, 0x1f8, &ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_D1", REG_SMC, 0x1f9, &ixMC_IO_DEBUG_WCDR_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1", REG_SMC, 0x1fa, &ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1", REG_SMC, 0x1fb, &ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1", REG_SMC, 0x1fc, &ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_MISC", REG_SMC, 0x2, &ixMC_TSM_DEBUG_MISC[0], sizeof(ixMC_TSM_DEBUG_MISC)/sizeof(ixMC_TSM_DEBUG_MISC[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_2", REG_SMC, 0x2, &ixMC_IO_DEBUG_UP_2[0], sizeof(ixMC_IO_DEBUG_UP_2)/sizeof(ixMC_IO_DEBUG_UP_2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_32", REG_SMC, 0x20, &ixMC_IO_DEBUG_UP_32[0], sizeof(ixMC_IO_DEBUG_UP_32)/sizeof(ixMC_IO_DEBUG_UP_32[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_33", REG_SMC, 0x21, &ixMC_IO_DEBUG_UP_33[0], sizeof(ixMC_IO_DEBUG_UP_33)/sizeof(ixMC_IO_DEBUG_UP_33[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_34", REG_SMC, 0x22, &ixMC_IO_DEBUG_UP_34[0], sizeof(ixMC_IO_DEBUG_UP_34)/sizeof(ixMC_IO_DEBUG_UP_34[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_35", REG_SMC, 0x23, &ixMC_IO_DEBUG_UP_35[0], sizeof(ixMC_IO_DEBUG_UP_35)/sizeof(ixMC_IO_DEBUG_UP_35[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_36", REG_SMC, 0x24, &ixMC_IO_DEBUG_UP_36[0], sizeof(ixMC_IO_DEBUG_UP_36)/sizeof(ixMC_IO_DEBUG_UP_36[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_37", REG_SMC, 0x25, &ixMC_IO_DEBUG_UP_37[0], sizeof(ixMC_IO_DEBUG_UP_37)/sizeof(ixMC_IO_DEBUG_UP_37[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_38", REG_SMC, 0x26, &ixMC_IO_DEBUG_UP_38[0], sizeof(ixMC_IO_DEBUG_UP_38)/sizeof(ixMC_IO_DEBUG_UP_38[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_39", REG_SMC, 0x27, &ixMC_IO_DEBUG_UP_39[0], sizeof(ixMC_IO_DEBUG_UP_39)/sizeof(ixMC_IO_DEBUG_UP_39[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_40", REG_SMC, 0x28, &ixMC_IO_DEBUG_UP_40[0], sizeof(ixMC_IO_DEBUG_UP_40)/sizeof(ixMC_IO_DEBUG_UP_40[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_41", REG_SMC, 0x29, &ixMC_IO_DEBUG_UP_41[0], sizeof(ixMC_IO_DEBUG_UP_41)/sizeof(ixMC_IO_DEBUG_UP_41[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_42", REG_SMC, 0x2a, &ixMC_IO_DEBUG_UP_42[0], sizeof(ixMC_IO_DEBUG_UP_42)/sizeof(ixMC_IO_DEBUG_UP_42[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_43", REG_SMC, 0x2b, &ixMC_IO_DEBUG_UP_43[0], sizeof(ixMC_IO_DEBUG_UP_43)/sizeof(ixMC_IO_DEBUG_UP_43[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_44", REG_SMC, 0x2c, &ixMC_IO_DEBUG_UP_44[0], sizeof(ixMC_IO_DEBUG_UP_44)/sizeof(ixMC_IO_DEBUG_UP_44[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_45", REG_SMC, 0x2d, &ixMC_IO_DEBUG_UP_45[0], sizeof(ixMC_IO_DEBUG_UP_45)/sizeof(ixMC_IO_DEBUG_UP_45[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_46", REG_SMC, 0x2e, &ixMC_IO_DEBUG_UP_46[0], sizeof(ixMC_IO_DEBUG_UP_46)/sizeof(ixMC_IO_DEBUG_UP_46[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_47", REG_SMC, 0x2f, &ixMC_IO_DEBUG_UP_47[0], sizeof(ixMC_IO_DEBUG_UP_47)/sizeof(ixMC_IO_DEBUG_UP_47[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT0", REG_SMC, 0x3, &ixMC_TSM_DEBUG_BCNT0[0], sizeof(ixMC_TSM_DEBUG_BCNT0)/sizeof(ixMC_TSM_DEBUG_BCNT0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_3", REG_SMC, 0x3, &ixMC_IO_DEBUG_UP_3[0], sizeof(ixMC_IO_DEBUG_UP_3)/sizeof(ixMC_IO_DEBUG_UP_3[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_48", REG_SMC, 0x30, &ixMC_IO_DEBUG_UP_48[0], sizeof(ixMC_IO_DEBUG_UP_48)/sizeof(ixMC_IO_DEBUG_UP_48[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_49", REG_SMC, 0x31, &ixMC_IO_DEBUG_UP_49[0], sizeof(ixMC_IO_DEBUG_UP_49)/sizeof(ixMC_IO_DEBUG_UP_49[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_50", REG_SMC, 0x32, &ixMC_IO_DEBUG_UP_50[0], sizeof(ixMC_IO_DEBUG_UP_50)/sizeof(ixMC_IO_DEBUG_UP_50[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_51", REG_SMC, 0x33, &ixMC_IO_DEBUG_UP_51[0], sizeof(ixMC_IO_DEBUG_UP_51)/sizeof(ixMC_IO_DEBUG_UP_51[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_52", REG_SMC, 0x34, &ixMC_IO_DEBUG_UP_52[0], sizeof(ixMC_IO_DEBUG_UP_52)/sizeof(ixMC_IO_DEBUG_UP_52[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_53", REG_SMC, 0x35, &ixMC_IO_DEBUG_UP_53[0], sizeof(ixMC_IO_DEBUG_UP_53)/sizeof(ixMC_IO_DEBUG_UP_53[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_54", REG_SMC, 0x36, &ixMC_IO_DEBUG_UP_54[0], sizeof(ixMC_IO_DEBUG_UP_54)/sizeof(ixMC_IO_DEBUG_UP_54[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_55", REG_SMC, 0x37, &ixMC_IO_DEBUG_UP_55[0], sizeof(ixMC_IO_DEBUG_UP_55)/sizeof(ixMC_IO_DEBUG_UP_55[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_56", REG_SMC, 0x38, &ixMC_IO_DEBUG_UP_56[0], sizeof(ixMC_IO_DEBUG_UP_56)/sizeof(ixMC_IO_DEBUG_UP_56[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_57", REG_SMC, 0x39, &ixMC_IO_DEBUG_UP_57[0], sizeof(ixMC_IO_DEBUG_UP_57)/sizeof(ixMC_IO_DEBUG_UP_57[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_58", REG_SMC, 0x3a, &ixMC_IO_DEBUG_UP_58[0], sizeof(ixMC_IO_DEBUG_UP_58)/sizeof(ixMC_IO_DEBUG_UP_58[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_59", REG_SMC, 0x3b, &ixMC_IO_DEBUG_UP_59[0], sizeof(ixMC_IO_DEBUG_UP_59)/sizeof(ixMC_IO_DEBUG_UP_59[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_60", REG_SMC, 0x3c, &ixMC_IO_DEBUG_UP_60[0], sizeof(ixMC_IO_DEBUG_UP_60)/sizeof(ixMC_IO_DEBUG_UP_60[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_61", REG_SMC, 0x3d, &ixMC_IO_DEBUG_UP_61[0], sizeof(ixMC_IO_DEBUG_UP_61)/sizeof(ixMC_IO_DEBUG_UP_61[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_62", REG_SMC, 0x3e, &ixMC_IO_DEBUG_UP_62[0], sizeof(ixMC_IO_DEBUG_UP_62)/sizeof(ixMC_IO_DEBUG_UP_62[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_63", REG_SMC, 0x3f, &ixMC_IO_DEBUG_UP_63[0], sizeof(ixMC_IO_DEBUG_UP_63)/sizeof(ixMC_IO_DEBUG_UP_63[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT1", REG_SMC, 0x4, &ixMC_TSM_DEBUG_BCNT1[0], sizeof(ixMC_TSM_DEBUG_BCNT1)/sizeof(ixMC_TSM_DEBUG_BCNT1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_4", REG_SMC, 0x4, &ixMC_IO_DEBUG_UP_4[0], sizeof(ixMC_IO_DEBUG_UP_4)/sizeof(ixMC_IO_DEBUG_UP_4[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_64", REG_SMC, 0x40, &ixMC_IO_DEBUG_UP_64[0], sizeof(ixMC_IO_DEBUG_UP_64)/sizeof(ixMC_IO_DEBUG_UP_64[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_65", REG_SMC, 0x41, &ixMC_IO_DEBUG_UP_65[0], sizeof(ixMC_IO_DEBUG_UP_65)/sizeof(ixMC_IO_DEBUG_UP_65[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_66", REG_SMC, 0x42, &ixMC_IO_DEBUG_UP_66[0], sizeof(ixMC_IO_DEBUG_UP_66)/sizeof(ixMC_IO_DEBUG_UP_66[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_67", REG_SMC, 0x43, &ixMC_IO_DEBUG_UP_67[0], sizeof(ixMC_IO_DEBUG_UP_67)/sizeof(ixMC_IO_DEBUG_UP_67[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_68", REG_SMC, 0x44, &ixMC_IO_DEBUG_UP_68[0], sizeof(ixMC_IO_DEBUG_UP_68)/sizeof(ixMC_IO_DEBUG_UP_68[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_69", REG_SMC, 0x45, &ixMC_IO_DEBUG_UP_69[0], sizeof(ixMC_IO_DEBUG_UP_69)/sizeof(ixMC_IO_DEBUG_UP_69[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_70", REG_SMC, 0x46, &ixMC_IO_DEBUG_UP_70[0], sizeof(ixMC_IO_DEBUG_UP_70)/sizeof(ixMC_IO_DEBUG_UP_70[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_71", REG_SMC, 0x47, &ixMC_IO_DEBUG_UP_71[0], sizeof(ixMC_IO_DEBUG_UP_71)/sizeof(ixMC_IO_DEBUG_UP_71[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_72", REG_SMC, 0x48, &ixMC_IO_DEBUG_UP_72[0], sizeof(ixMC_IO_DEBUG_UP_72)/sizeof(ixMC_IO_DEBUG_UP_72[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_73", REG_SMC, 0x49, &ixMC_IO_DEBUG_UP_73[0], sizeof(ixMC_IO_DEBUG_UP_73)/sizeof(ixMC_IO_DEBUG_UP_73[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_74", REG_SMC, 0x4a, &ixMC_IO_DEBUG_UP_74[0], sizeof(ixMC_IO_DEBUG_UP_74)/sizeof(ixMC_IO_DEBUG_UP_74[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_75", REG_SMC, 0x4b, &ixMC_IO_DEBUG_UP_75[0], sizeof(ixMC_IO_DEBUG_UP_75)/sizeof(ixMC_IO_DEBUG_UP_75[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_76", REG_SMC, 0x4c, &ixMC_IO_DEBUG_UP_76[0], sizeof(ixMC_IO_DEBUG_UP_76)/sizeof(ixMC_IO_DEBUG_UP_76[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_77", REG_SMC, 0x4d, &ixMC_IO_DEBUG_UP_77[0], sizeof(ixMC_IO_DEBUG_UP_77)/sizeof(ixMC_IO_DEBUG_UP_77[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_78", REG_SMC, 0x4e, &ixMC_IO_DEBUG_UP_78[0], sizeof(ixMC_IO_DEBUG_UP_78)/sizeof(ixMC_IO_DEBUG_UP_78[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_79", REG_SMC, 0x4f, &ixMC_IO_DEBUG_UP_79[0], sizeof(ixMC_IO_DEBUG_UP_79)/sizeof(ixMC_IO_DEBUG_UP_79[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT2", REG_SMC, 0x5, &ixMC_TSM_DEBUG_BCNT2[0], sizeof(ixMC_TSM_DEBUG_BCNT2)/sizeof(ixMC_TSM_DEBUG_BCNT2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_5", REG_SMC, 0x5, &ixMC_IO_DEBUG_UP_5[0], sizeof(ixMC_IO_DEBUG_UP_5)/sizeof(ixMC_IO_DEBUG_UP_5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_80", REG_SMC, 0x50, &ixMC_IO_DEBUG_UP_80[0], sizeof(ixMC_IO_DEBUG_UP_80)/sizeof(ixMC_IO_DEBUG_UP_80[0]), 0, 0 },
+	{ "mmVM_L2_CNTL", REG_MMIO, 0x500, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 },
+	{ "mmVM_L2_CNTL2", REG_MMIO, 0x501, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 },
+	{ "mmVM_L2_CNTL3", REG_MMIO, 0x502, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 },
+	{ "mmVM_L2_STATUS", REG_MMIO, 0x503, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x504, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x505, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x506, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_ADDR", REG_MMIO, 0x507, &mmVM_DUMMY_PAGE_FAULT_ADDR[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL2", REG_MMIO, 0x50c, &mmVM_CONTEXT0_CNTL2[0], sizeof(mmVM_CONTEXT0_CNTL2)/sizeof(mmVM_CONTEXT0_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL2", REG_MMIO, 0x50d, &mmVM_CONTEXT1_CNTL2[0], sizeof(mmVM_CONTEXT1_CNTL2)/sizeof(mmVM_CONTEXT1_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50e, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50f, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_81", REG_SMC, 0x51, &ixMC_IO_DEBUG_UP_81[0], sizeof(ixMC_IO_DEBUG_UP_81)/sizeof(ixMC_IO_DEBUG_UP_81[0]), 0, 0 },
+	{ "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x510, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x511, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x512, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x513, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x514, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x515, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_REQUEST", REG_MMIO, 0x51e, &mmVM_INVALIDATE_REQUEST[0], sizeof(mmVM_INVALIDATE_REQUEST)/sizeof(mmVM_INVALIDATE_REQUEST[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_RESPONSE", REG_MMIO, 0x51f, &mmVM_INVALIDATE_RESPONSE[0], sizeof(mmVM_INVALIDATE_RESPONSE)/sizeof(mmVM_INVALIDATE_RESPONSE[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_82", REG_SMC, 0x52, &ixMC_IO_DEBUG_UP_82[0], sizeof(ixMC_IO_DEBUG_UP_82)/sizeof(ixMC_IO_DEBUG_UP_82[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_LOW_ADDR", REG_MMIO, 0x52c, &mmVM_PRT_APERTURE0_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE0_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_LOW_ADDR", REG_MMIO, 0x52d, &mmVM_PRT_APERTURE1_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE1_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_LOW_ADDR", REG_MMIO, 0x52e, &mmVM_PRT_APERTURE2_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE2_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE2_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_LOW_ADDR", REG_MMIO, 0x52f, &mmVM_PRT_APERTURE3_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE3_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE3_LOW_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_83", REG_SMC, 0x53, &ixMC_IO_DEBUG_UP_83[0], sizeof(ixMC_IO_DEBUG_UP_83)/sizeof(ixMC_IO_DEBUG_UP_83[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_HIGH_ADDR", REG_MMIO, 0x530, &mmVM_PRT_APERTURE0_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_HIGH_ADDR", REG_MMIO, 0x531, &mmVM_PRT_APERTURE1_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_HIGH_ADDR", REG_MMIO, 0x532, &mmVM_PRT_APERTURE2_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_HIGH_ADDR", REG_MMIO, 0x533, &mmVM_PRT_APERTURE3_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_CNTL", REG_MMIO, 0x534, &mmVM_PRT_CNTL[0], sizeof(mmVM_PRT_CNTL)/sizeof(mmVM_PRT_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x535, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_STATUS", REG_MMIO, 0x536, &mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_STATUS", REG_MMIO, 0x537, &mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x538, &mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x539, &mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53e, &mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53f, &mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_84", REG_SMC, 0x54, &ixMC_IO_DEBUG_UP_84[0], sizeof(ixMC_IO_DEBUG_UP_84)/sizeof(ixMC_IO_DEBUG_UP_84[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x546, &mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x547, &mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_FAULT_CLIENT_ID", REG_MMIO, 0x54e, &mmVM_FAULT_CLIENT_ID[0], sizeof(mmVM_FAULT_CLIENT_ID)/sizeof(mmVM_FAULT_CLIENT_ID[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x54f, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_85", REG_SMC, 0x55, &ixMC_IO_DEBUG_UP_85[0], sizeof(ixMC_IO_DEBUG_UP_85)/sizeof(ixMC_IO_DEBUG_UP_85[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x550, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x551, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x552, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x553, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x554, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x555, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x556, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR", REG_MMIO, 0x557, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR", REG_MMIO, 0x558, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR", REG_MMIO, 0x55f, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_86", REG_SMC, 0x56, &ixMC_IO_DEBUG_UP_86[0], sizeof(ixMC_IO_DEBUG_UP_86)/sizeof(ixMC_IO_DEBUG_UP_86[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR", REG_MMIO, 0x560, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "mmVM_DEBUG", REG_MMIO, 0x56f, &mmVM_DEBUG[0], sizeof(mmVM_DEBUG)/sizeof(mmVM_DEBUG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_87", REG_SMC, 0x57, &ixMC_IO_DEBUG_UP_87[0], sizeof(ixMC_IO_DEBUG_UP_87)/sizeof(ixMC_IO_DEBUG_UP_87[0]), 0, 0 },
+	{ "mmVM_L2_CG", REG_MMIO, 0x570, &mmVM_L2_CG[0], sizeof(mmVM_L2_CG)/sizeof(mmVM_L2_CG[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKA", REG_MMIO, 0x572, &mmVM_L2_BANK_SELECT_MASKA[0], sizeof(mmVM_L2_BANK_SELECT_MASKA)/sizeof(mmVM_L2_BANK_SELECT_MASKA[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKB", REG_MMIO, 0x573, &mmVM_L2_BANK_SELECT_MASKB[0], sizeof(mmVM_L2_BANK_SELECT_MASKB)/sizeof(mmVM_L2_BANK_SELECT_MASKB[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", REG_MMIO, 0x575, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", REG_MMIO, 0x576, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", REG_MMIO, 0x577, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_88", REG_SMC, 0x58, &ixMC_IO_DEBUG_UP_88[0], sizeof(ixMC_IO_DEBUG_UP_88)/sizeof(ixMC_IO_DEBUG_UP_88[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_89", REG_SMC, 0x59, &ixMC_IO_DEBUG_UP_89[0], sizeof(ixMC_IO_DEBUG_UP_89)/sizeof(ixMC_IO_DEBUG_UP_89[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_90", REG_SMC, 0x5a, &ixMC_IO_DEBUG_UP_90[0], sizeof(ixMC_IO_DEBUG_UP_90)/sizeof(ixMC_IO_DEBUG_UP_90[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_91", REG_SMC, 0x5b, &ixMC_IO_DEBUG_UP_91[0], sizeof(ixMC_IO_DEBUG_UP_91)/sizeof(ixMC_IO_DEBUG_UP_91[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_92", REG_SMC, 0x5c, &ixMC_IO_DEBUG_UP_92[0], sizeof(ixMC_IO_DEBUG_UP_92)/sizeof(ixMC_IO_DEBUG_UP_92[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_93", REG_SMC, 0x5d, &ixMC_IO_DEBUG_UP_93[0], sizeof(ixMC_IO_DEBUG_UP_93)/sizeof(ixMC_IO_DEBUG_UP_93[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_94", REG_SMC, 0x5e, &ixMC_IO_DEBUG_UP_94[0], sizeof(ixMC_IO_DEBUG_UP_94)/sizeof(ixMC_IO_DEBUG_UP_94[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_95", REG_SMC, 0x5f, &ixMC_IO_DEBUG_UP_95[0], sizeof(ixMC_IO_DEBUG_UP_95)/sizeof(ixMC_IO_DEBUG_UP_95[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT3", REG_SMC, 0x6, &ixMC_TSM_DEBUG_BCNT3[0], sizeof(ixMC_TSM_DEBUG_BCNT3)/sizeof(ixMC_TSM_DEBUG_BCNT3[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_6", REG_SMC, 0x6, &ixMC_IO_DEBUG_UP_6[0], sizeof(ixMC_IO_DEBUG_UP_6)/sizeof(ixMC_IO_DEBUG_UP_6[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_96", REG_SMC, 0x60, &ixMC_IO_DEBUG_UP_96[0], sizeof(ixMC_IO_DEBUG_UP_96)/sizeof(ixMC_IO_DEBUG_UP_96[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_97", REG_SMC, 0x61, &ixMC_IO_DEBUG_UP_97[0], sizeof(ixMC_IO_DEBUG_UP_97)/sizeof(ixMC_IO_DEBUG_UP_97[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_98", REG_SMC, 0x62, &ixMC_IO_DEBUG_UP_98[0], sizeof(ixMC_IO_DEBUG_UP_98)/sizeof(ixMC_IO_DEBUG_UP_98[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_99", REG_SMC, 0x63, &ixMC_IO_DEBUG_UP_99[0], sizeof(ixMC_IO_DEBUG_UP_99)/sizeof(ixMC_IO_DEBUG_UP_99[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_100", REG_SMC, 0x64, &ixMC_IO_DEBUG_UP_100[0], sizeof(ixMC_IO_DEBUG_UP_100)/sizeof(ixMC_IO_DEBUG_UP_100[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_101", REG_SMC, 0x65, &ixMC_IO_DEBUG_UP_101[0], sizeof(ixMC_IO_DEBUG_UP_101)/sizeof(ixMC_IO_DEBUG_UP_101[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_102", REG_SMC, 0x66, &ixMC_IO_DEBUG_UP_102[0], sizeof(ixMC_IO_DEBUG_UP_102)/sizeof(ixMC_IO_DEBUG_UP_102[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_103", REG_SMC, 0x67, &ixMC_IO_DEBUG_UP_103[0], sizeof(ixMC_IO_DEBUG_UP_103)/sizeof(ixMC_IO_DEBUG_UP_103[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_104", REG_SMC, 0x68, &ixMC_IO_DEBUG_UP_104[0], sizeof(ixMC_IO_DEBUG_UP_104)/sizeof(ixMC_IO_DEBUG_UP_104[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_105", REG_SMC, 0x69, &ixMC_IO_DEBUG_UP_105[0], sizeof(ixMC_IO_DEBUG_UP_105)/sizeof(ixMC_IO_DEBUG_UP_105[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_106", REG_SMC, 0x6a, &ixMC_IO_DEBUG_UP_106[0], sizeof(ixMC_IO_DEBUG_UP_106)/sizeof(ixMC_IO_DEBUG_UP_106[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_107", REG_SMC, 0x6b, &ixMC_IO_DEBUG_UP_107[0], sizeof(ixMC_IO_DEBUG_UP_107)/sizeof(ixMC_IO_DEBUG_UP_107[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_108", REG_SMC, 0x6c, &ixMC_IO_DEBUG_UP_108[0], sizeof(ixMC_IO_DEBUG_UP_108)/sizeof(ixMC_IO_DEBUG_UP_108[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_109", REG_SMC, 0x6d, &ixMC_IO_DEBUG_UP_109[0], sizeof(ixMC_IO_DEBUG_UP_109)/sizeof(ixMC_IO_DEBUG_UP_109[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_110", REG_SMC, 0x6e, &ixMC_IO_DEBUG_UP_110[0], sizeof(ixMC_IO_DEBUG_UP_110)/sizeof(ixMC_IO_DEBUG_UP_110[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_111", REG_SMC, 0x6f, &ixMC_IO_DEBUG_UP_111[0], sizeof(ixMC_IO_DEBUG_UP_111)/sizeof(ixMC_IO_DEBUG_UP_111[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT4", REG_SMC, 0x7, &ixMC_TSM_DEBUG_BCNT4[0], sizeof(ixMC_TSM_DEBUG_BCNT4)/sizeof(ixMC_TSM_DEBUG_BCNT4[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_7", REG_SMC, 0x7, &ixMC_IO_DEBUG_UP_7[0], sizeof(ixMC_IO_DEBUG_UP_7)/sizeof(ixMC_IO_DEBUG_UP_7[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_112", REG_SMC, 0x70, &ixMC_IO_DEBUG_UP_112[0], sizeof(ixMC_IO_DEBUG_UP_112)/sizeof(ixMC_IO_DEBUG_UP_112[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_113", REG_SMC, 0x71, &ixMC_IO_DEBUG_UP_113[0], sizeof(ixMC_IO_DEBUG_UP_113)/sizeof(ixMC_IO_DEBUG_UP_113[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_114", REG_SMC, 0x72, &ixMC_IO_DEBUG_UP_114[0], sizeof(ixMC_IO_DEBUG_UP_114)/sizeof(ixMC_IO_DEBUG_UP_114[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_115", REG_SMC, 0x73, &ixMC_IO_DEBUG_UP_115[0], sizeof(ixMC_IO_DEBUG_UP_115)/sizeof(ixMC_IO_DEBUG_UP_115[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_116", REG_SMC, 0x74, &ixMC_IO_DEBUG_UP_116[0], sizeof(ixMC_IO_DEBUG_UP_116)/sizeof(ixMC_IO_DEBUG_UP_116[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_117", REG_SMC, 0x75, &ixMC_IO_DEBUG_UP_117[0], sizeof(ixMC_IO_DEBUG_UP_117)/sizeof(ixMC_IO_DEBUG_UP_117[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_118", REG_SMC, 0x76, &ixMC_IO_DEBUG_UP_118[0], sizeof(ixMC_IO_DEBUG_UP_118)/sizeof(ixMC_IO_DEBUG_UP_118[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_119", REG_SMC, 0x77, &ixMC_IO_DEBUG_UP_119[0], sizeof(ixMC_IO_DEBUG_UP_119)/sizeof(ixMC_IO_DEBUG_UP_119[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_120", REG_SMC, 0x78, &ixMC_IO_DEBUG_UP_120[0], sizeof(ixMC_IO_DEBUG_UP_120)/sizeof(ixMC_IO_DEBUG_UP_120[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_121", REG_SMC, 0x79, &ixMC_IO_DEBUG_UP_121[0], sizeof(ixMC_IO_DEBUG_UP_121)/sizeof(ixMC_IO_DEBUG_UP_121[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_122", REG_SMC, 0x7a, &ixMC_IO_DEBUG_UP_122[0], sizeof(ixMC_IO_DEBUG_UP_122)/sizeof(ixMC_IO_DEBUG_UP_122[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_LO", REG_MMIO, 0x7a0, &mmMC_CITF_PERFCOUNTER_LO[0], sizeof(mmMC_CITF_PERFCOUNTER_LO)/sizeof(mmMC_CITF_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_LO", REG_MMIO, 0x7a1, &mmMC_HUB_PERFCOUNTER_LO[0], sizeof(mmMC_HUB_PERFCOUNTER_LO)/sizeof(mmMC_HUB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_LO", REG_MMIO, 0x7a2, &mmMC_RPB_PERFCOUNTER_LO[0], sizeof(mmMC_RPB_PERFCOUNTER_LO)/sizeof(mmMC_RPB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_LO", REG_MMIO, 0x7a3, &mmMC_MCBVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCBVM_PERFCOUNTER_LO)/sizeof(mmMC_MCBVM_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_LO", REG_MMIO, 0x7a4, &mmMC_MCDVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCDVM_PERFCOUNTER_LO)/sizeof(mmMC_MCDVM_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_LO", REG_MMIO, 0x7a5, &mmMC_VM_L2_PERFCOUNTER_LO[0], sizeof(mmMC_VM_L2_PERFCOUNTER_LO)/sizeof(mmMC_VM_L2_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_LO", REG_MMIO, 0x7a6, &mmMC_ARB_PERFCOUNTER_LO[0], sizeof(mmMC_ARB_PERFCOUNTER_LO)/sizeof(mmMC_ARB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_LO", REG_MMIO, 0x7a7, &mmATC_PERFCOUNTER_LO[0], sizeof(mmATC_PERFCOUNTER_LO)/sizeof(mmATC_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_HI", REG_MMIO, 0x7a8, &mmMC_CITF_PERFCOUNTER_HI[0], sizeof(mmMC_CITF_PERFCOUNTER_HI)/sizeof(mmMC_CITF_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_HI", REG_MMIO, 0x7a9, &mmMC_HUB_PERFCOUNTER_HI[0], sizeof(mmMC_HUB_PERFCOUNTER_HI)/sizeof(mmMC_HUB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_HI", REG_MMIO, 0x7aa, &mmMC_MCBVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCBVM_PERFCOUNTER_HI)/sizeof(mmMC_MCBVM_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_HI", REG_MMIO, 0x7ab, &mmMC_MCDVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCDVM_PERFCOUNTER_HI)/sizeof(mmMC_MCDVM_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_HI", REG_MMIO, 0x7ac, &mmMC_RPB_PERFCOUNTER_HI[0], sizeof(mmMC_RPB_PERFCOUNTER_HI)/sizeof(mmMC_RPB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_HI", REG_MMIO, 0x7ad, &mmMC_VM_L2_PERFCOUNTER_HI[0], sizeof(mmMC_VM_L2_PERFCOUNTER_HI)/sizeof(mmMC_VM_L2_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_HI", REG_MMIO, 0x7ae, &mmMC_ARB_PERFCOUNTER_HI[0], sizeof(mmMC_ARB_PERFCOUNTER_HI)/sizeof(mmMC_ARB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_HI", REG_MMIO, 0x7af, &mmATC_PERFCOUNTER_HI[0], sizeof(mmATC_PERFCOUNTER_HI)/sizeof(mmATC_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_123", REG_SMC, 0x7b, &ixMC_IO_DEBUG_UP_123[0], sizeof(ixMC_IO_DEBUG_UP_123)/sizeof(ixMC_IO_DEBUG_UP_123[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER0_CFG", REG_MMIO, 0x7b0, &mmMC_CITF_PERFCOUNTER0_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER0_CFG)/sizeof(mmMC_CITF_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER1_CFG", REG_MMIO, 0x7b1, &mmMC_CITF_PERFCOUNTER1_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER1_CFG)/sizeof(mmMC_CITF_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER2_CFG", REG_MMIO, 0x7b2, &mmMC_CITF_PERFCOUNTER2_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER2_CFG)/sizeof(mmMC_CITF_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER3_CFG", REG_MMIO, 0x7b3, &mmMC_CITF_PERFCOUNTER3_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER3_CFG)/sizeof(mmMC_CITF_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b4, &mmMC_HUB_PERFCOUNTER0_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER0_CFG)/sizeof(mmMC_HUB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b5, &mmMC_HUB_PERFCOUNTER1_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER1_CFG)/sizeof(mmMC_HUB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER2_CFG", REG_MMIO, 0x7b6, &mmMC_HUB_PERFCOUNTER2_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER2_CFG)/sizeof(mmMC_HUB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER3_CFG", REG_MMIO, 0x7b7, &mmMC_HUB_PERFCOUNTER3_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER3_CFG)/sizeof(mmMC_HUB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b8, &mmMC_RPB_PERFCOUNTER0_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER0_CFG)/sizeof(mmMC_RPB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b9, &mmMC_RPB_PERFCOUNTER1_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER1_CFG)/sizeof(mmMC_RPB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER2_CFG", REG_MMIO, 0x7ba, &mmMC_RPB_PERFCOUNTER2_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER2_CFG)/sizeof(mmMC_RPB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bb, &mmMC_RPB_PERFCOUNTER3_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER3_CFG)/sizeof(mmMC_RPB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER0_CFG", REG_MMIO, 0x7bc, &mmMC_ARB_PERFCOUNTER0_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER0_CFG)/sizeof(mmMC_ARB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER1_CFG", REG_MMIO, 0x7bd, &mmMC_ARB_PERFCOUNTER1_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER1_CFG)/sizeof(mmMC_ARB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER2_CFG", REG_MMIO, 0x7be, &mmMC_ARB_PERFCOUNTER2_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER2_CFG)/sizeof(mmMC_ARB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bf, &mmMC_ARB_PERFCOUNTER3_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER3_CFG)/sizeof(mmMC_ARB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_124", REG_SMC, 0x7c, &ixMC_IO_DEBUG_UP_124[0], sizeof(ixMC_IO_DEBUG_UP_124)/sizeof(ixMC_IO_DEBUG_UP_124[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c0, &mmMC_MCBVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c1, &mmMC_MCBVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c2, &mmMC_MCBVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c3, &mmMC_MCBVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c4, &mmMC_MCDVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c5, &mmMC_MCDVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c6, &mmMC_MCDVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c7, &mmMC_MCDVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7c8, &mmATC_PERFCOUNTER0_CFG[0], sizeof(mmATC_PERFCOUNTER0_CFG)/sizeof(mmATC_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7c9, &mmATC_PERFCOUNTER1_CFG[0], sizeof(mmATC_PERFCOUNTER1_CFG)/sizeof(mmATC_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER2_CFG", REG_MMIO, 0x7ca, &mmATC_PERFCOUNTER2_CFG[0], sizeof(mmATC_PERFCOUNTER2_CFG)/sizeof(mmATC_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER3_CFG", REG_MMIO, 0x7cb, &mmATC_PERFCOUNTER3_CFG[0], sizeof(mmATC_PERFCOUNTER3_CFG)/sizeof(mmATC_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x7cc, &mmMC_VM_L2_PERFCOUNTER0_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x7cd, &mmMC_VM_L2_PERFCOUNTER1_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7ce, &mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7cf, &mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_125", REG_SMC, 0x7d, &ixMC_IO_DEBUG_UP_125[0], sizeof(ixMC_IO_DEBUG_UP_125)/sizeof(ixMC_IO_DEBUG_UP_125[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d0, &mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d1, &mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d2, &mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d3, &mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d4, &mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d5, &mmATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_LO", REG_MMIO, 0x7d6, &mmCHUB_ATC_PERFCOUNTER_LO[0], sizeof(mmCHUB_ATC_PERFCOUNTER_LO)/sizeof(mmCHUB_ATC_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_HI", REG_MMIO, 0x7d7, &mmCHUB_ATC_PERFCOUNTER_HI[0], sizeof(mmCHUB_ATC_PERFCOUNTER_HI)/sizeof(mmCHUB_ATC_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7d8, &mmCHUB_ATC_PERFCOUNTER0_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7d9, &mmCHUB_ATC_PERFCOUNTER1_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7da, &mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_PERF_MON_CNTL0_ECC", REG_MMIO, 0x7db, &mmMC_ARB_PERF_MON_CNTL0_ECC[0], sizeof(mmMC_ARB_PERF_MON_CNTL0_ECC)/sizeof(mmMC_ARB_PERF_MON_CNTL0_ECC[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_126", REG_SMC, 0x7e, &ixMC_IO_DEBUG_UP_126[0], sizeof(ixMC_IO_DEBUG_UP_126)/sizeof(ixMC_IO_DEBUG_UP_126[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_127", REG_SMC, 0x7f, &ixMC_IO_DEBUG_UP_127[0], sizeof(ixMC_IO_DEBUG_UP_127)/sizeof(ixMC_IO_DEBUG_UP_127[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT5", REG_SMC, 0x8, &ixMC_TSM_DEBUG_BCNT5[0], sizeof(ixMC_TSM_DEBUG_BCNT5)/sizeof(ixMC_TSM_DEBUG_BCNT5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_8", REG_SMC, 0x8, &ixMC_IO_DEBUG_UP_8[0], sizeof(ixMC_IO_DEBUG_UP_8)/sizeof(ixMC_IO_DEBUG_UP_8[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_128", REG_SMC, 0x80, &ixMC_IO_DEBUG_UP_128[0], sizeof(ixMC_IO_DEBUG_UP_128)/sizeof(ixMC_IO_DEBUG_UP_128[0]), 0, 0 },
+	{ "mmMC_CONFIG", REG_MMIO, 0x800, &mmMC_CONFIG[0], sizeof(mmMC_CONFIG)/sizeof(mmMC_CONFIG[0]), 0, 0 },
+	{ "mmMC_SHARED_CHMAP", REG_MMIO, 0x801, &mmMC_SHARED_CHMAP[0], sizeof(mmMC_SHARED_CHMAP)/sizeof(mmMC_SHARED_CHMAP[0]), 0, 0 },
+	{ "mmMC_SHARED_CHREMAP", REG_MMIO, 0x802, &mmMC_SHARED_CHREMAP[0], sizeof(mmMC_SHARED_CHREMAP)/sizeof(mmMC_SHARED_CHREMAP[0]), 0, 0 },
+	{ "mmMC_RD_GRP_GFX", REG_MMIO, 0x803, &mmMC_RD_GRP_GFX[0], sizeof(mmMC_RD_GRP_GFX)/sizeof(mmMC_RD_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_WR_GRP_GFX", REG_MMIO, 0x804, &mmMC_WR_GRP_GFX[0], sizeof(mmMC_WR_GRP_GFX)/sizeof(mmMC_WR_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_RD_GRP_SYS", REG_MMIO, 0x805, &mmMC_RD_GRP_SYS[0], sizeof(mmMC_RD_GRP_SYS)/sizeof(mmMC_RD_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_WR_GRP_SYS", REG_MMIO, 0x806, &mmMC_WR_GRP_SYS[0], sizeof(mmMC_WR_GRP_SYS)/sizeof(mmMC_WR_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_RD_GRP_OTH", REG_MMIO, 0x807, &mmMC_RD_GRP_OTH[0], sizeof(mmMC_RD_GRP_OTH)/sizeof(mmMC_RD_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_WR_GRP_OTH", REG_MMIO, 0x808, &mmMC_WR_GRP_OTH[0], sizeof(mmMC_WR_GRP_OTH)/sizeof(mmMC_WR_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_VM_FB_LOCATION", REG_MMIO, 0x809, &mmMC_VM_FB_LOCATION[0], sizeof(mmMC_VM_FB_LOCATION)/sizeof(mmMC_VM_FB_LOCATION[0]), 0, 0 },
+	{ "mmMC_VM_AGP_TOP", REG_MMIO, 0x80a, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BOT", REG_MMIO, 0x80b, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BASE", REG_MMIO, 0x80c, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x80d, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x80e, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", REG_MMIO, 0x80f, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_129", REG_SMC, 0x81, &ixMC_IO_DEBUG_UP_129[0], sizeof(ixMC_IO_DEBUG_UP_129)/sizeof(ixMC_IO_DEBUG_UP_129[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_CNTL", REG_MMIO, 0x810, &mmMC_VM_DC_WRITE_CNTL[0], sizeof(mmMC_VM_DC_WRITE_CNTL)/sizeof(mmMC_VM_DC_WRITE_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR", REG_MMIO, 0x811, &mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR", REG_MMIO, 0x812, &mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR", REG_MMIO, 0x813, &mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR", REG_MMIO, 0x814, &mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR", REG_MMIO, 0x815, &mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR", REG_MMIO, 0x816, &mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR", REG_MMIO, 0x817, &mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR", REG_MMIO, 0x818, &mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x819, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_FB_OFFSET", REG_MMIO, 0x81a, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 },
+	{ "mmMC_VM_STEERING", REG_MMIO, 0x81b, &mmMC_VM_STEERING[0], sizeof(mmMC_VM_STEERING)/sizeof(mmMC_VM_STEERING[0]), 0, 0 },
+	{ "mmMC_SHARED_CHREMAP2", REG_MMIO, 0x81c, &mmMC_SHARED_CHREMAP2[0], sizeof(mmMC_SHARED_CHREMAP2)/sizeof(mmMC_SHARED_CHREMAP2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_130", REG_SMC, 0x82, &ixMC_IO_DEBUG_UP_130[0], sizeof(ixMC_IO_DEBUG_UP_130)/sizeof(ixMC_IO_DEBUG_UP_130[0]), 0, 0 },
+	{ "mmMC_CONFIG_MCD", REG_MMIO, 0x828, &mmMC_CONFIG_MCD[0], sizeof(mmMC_CONFIG_MCD)/sizeof(mmMC_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG_MCD", REG_MMIO, 0x829, &mmMC_CG_CONFIG_MCD[0], sizeof(mmMC_CG_CONFIG_MCD)/sizeof(mmMC_CG_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_MEM_POWER_LS", REG_MMIO, 0x82a, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 },
+	{ "mmMC_SHARED_BLACKOUT_CNTL", REG_MMIO, 0x82b, &mmMC_SHARED_BLACKOUT_CNTL[0], sizeof(mmMC_SHARED_BLACKOUT_CNTL)/sizeof(mmMC_SHARED_BLACKOUT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_POWER", REG_MMIO, 0x82d, &mmMC_HUB_MISC_POWER[0], sizeof(mmMC_HUB_MISC_POWER)/sizeof(mmMC_HUB_MISC_POWER[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_HUB_CG", REG_MMIO, 0x82e, &mmMC_HUB_MISC_HUB_CG[0], sizeof(mmMC_HUB_MISC_HUB_CG)/sizeof(mmMC_HUB_MISC_HUB_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_VM_CG", REG_MMIO, 0x82f, &mmMC_HUB_MISC_VM_CG[0], sizeof(mmMC_HUB_MISC_VM_CG)/sizeof(mmMC_HUB_MISC_VM_CG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_131", REG_SMC, 0x83, &ixMC_IO_DEBUG_UP_131[0], sizeof(ixMC_IO_DEBUG_UP_131)/sizeof(ixMC_IO_DEBUG_UP_131[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_SIP_CG", REG_MMIO, 0x830, &mmMC_HUB_MISC_SIP_CG[0], sizeof(mmMC_HUB_MISC_SIP_CG)/sizeof(mmMC_HUB_MISC_SIP_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_STATUS", REG_MMIO, 0x832, &mmMC_HUB_MISC_STATUS[0], sizeof(mmMC_HUB_MISC_STATUS)/sizeof(mmMC_HUB_MISC_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_OVERRIDE", REG_MMIO, 0x833, &mmMC_HUB_MISC_OVERRIDE[0], sizeof(mmMC_HUB_MISC_OVERRIDE)/sizeof(mmMC_HUB_MISC_OVERRIDE[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_FRAMING", REG_MMIO, 0x834, &mmMC_HUB_MISC_FRAMING[0], sizeof(mmMC_HUB_MISC_FRAMING)/sizeof(mmMC_HUB_MISC_FRAMING[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CNTL", REG_MMIO, 0x835, &mmMC_HUB_WDP_CNTL[0], sizeof(mmMC_HUB_WDP_CNTL)/sizeof(mmMC_HUB_WDP_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ERR", REG_MMIO, 0x836, &mmMC_HUB_WDP_ERR[0], sizeof(mmMC_HUB_WDP_ERR)/sizeof(mmMC_HUB_WDP_ERR[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BP", REG_MMIO, 0x837, &mmMC_HUB_WDP_BP[0], sizeof(mmMC_HUB_WDP_BP)/sizeof(mmMC_HUB_WDP_BP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_STATUS", REG_MMIO, 0x838, &mmMC_HUB_WDP_STATUS[0], sizeof(mmMC_HUB_WDP_STATUS)/sizeof(mmMC_HUB_WDP_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_STATUS", REG_MMIO, 0x839, &mmMC_HUB_RDREQ_STATUS[0], sizeof(mmMC_HUB_RDREQ_STATUS)/sizeof(mmMC_HUB_RDREQ_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_STATUS", REG_MMIO, 0x83a, &mmMC_HUB_WRRET_STATUS[0], sizeof(mmMC_HUB_WRRET_STATUS)/sizeof(mmMC_HUB_WRRET_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CNTL", REG_MMIO, 0x83b, &mmMC_HUB_RDREQ_CNTL[0], sizeof(mmMC_HUB_RDREQ_CNTL)/sizeof(mmMC_HUB_RDREQ_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_CNTL", REG_MMIO, 0x83c, &mmMC_HUB_WRRET_CNTL[0], sizeof(mmMC_HUB_WRRET_CNTL)/sizeof(mmMC_HUB_WRRET_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_WTM_CNTL", REG_MMIO, 0x83d, &mmMC_HUB_RDREQ_WTM_CNTL[0], sizeof(mmMC_HUB_RDREQ_WTM_CNTL)/sizeof(mmMC_HUB_RDREQ_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_WTM_CNTL", REG_MMIO, 0x83e, &mmMC_HUB_WDP_WTM_CNTL[0], sizeof(mmMC_HUB_WDP_WTM_CNTL)/sizeof(mmMC_HUB_WDP_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS", REG_MMIO, 0x83f, &mmMC_HUB_WDP_CREDITS[0], sizeof(mmMC_HUB_WDP_CREDITS)/sizeof(mmMC_HUB_WDP_CREDITS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_132", REG_SMC, 0x84, &ixMC_IO_DEBUG_UP_132[0], sizeof(ixMC_IO_DEBUG_UP_132)/sizeof(ixMC_IO_DEBUG_UP_132[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS2", REG_MMIO, 0x840, &mmMC_HUB_WDP_CREDITS2[0], sizeof(mmMC_HUB_WDP_CREDITS2)/sizeof(mmMC_HUB_WDP_CREDITS2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL0", REG_MMIO, 0x841, &mmMC_HUB_WDP_GBL0[0], sizeof(mmMC_HUB_WDP_GBL0)/sizeof(mmMC_HUB_WDP_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL1", REG_MMIO, 0x842, &mmMC_HUB_WDP_GBL1[0], sizeof(mmMC_HUB_WDP_GBL1)/sizeof(mmMC_HUB_WDP_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS", REG_MMIO, 0x844, &mmMC_HUB_RDREQ_CREDITS[0], sizeof(mmMC_HUB_RDREQ_CREDITS)/sizeof(mmMC_HUB_RDREQ_CREDITS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS2", REG_MMIO, 0x845, &mmMC_HUB_RDREQ_CREDITS2[0], sizeof(mmMC_HUB_RDREQ_CREDITS2)/sizeof(mmMC_HUB_RDREQ_CREDITS2[0]), 0, 0 },
+	{ "mmMC_HUB_SHARED_DAGB_DLY", REG_MMIO, 0x846, &mmMC_HUB_SHARED_DAGB_DLY[0], sizeof(mmMC_HUB_SHARED_DAGB_DLY)/sizeof(mmMC_HUB_SHARED_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_IDLE_STATUS", REG_MMIO, 0x847, &mmMC_HUB_MISC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_IDLE_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF_LIMIT", REG_MMIO, 0x848, &mmMC_HUB_RDREQ_DMIF_LIMIT[0], sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT)/sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPG_LIMIT", REG_MMIO, 0x849, &mmMC_HUB_RDREQ_ACPG_LIMIT[0], sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT)/sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BYPASS_GBL0", REG_MMIO, 0x84a, &mmMC_HUB_WDP_BYPASS_GBL0[0], sizeof(mmMC_HUB_WDP_BYPASS_GBL0)/sizeof(mmMC_HUB_WDP_BYPASS_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BYPASS_GBL1", REG_MMIO, 0x84b, &mmMC_HUB_WDP_BYPASS_GBL1[0], sizeof(mmMC_HUB_WDP_BYPASS_GBL1)/sizeof(mmMC_HUB_WDP_BYPASS_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_BYPASS_GBL0", REG_MMIO, 0x84c, &mmMC_HUB_RDREQ_BYPASS_GBL0[0], sizeof(mmMC_HUB_RDREQ_BYPASS_GBL0)/sizeof(mmMC_HUB_RDREQ_BYPASS_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH2", REG_MMIO, 0x84d, &mmMC_HUB_WDP_SH2[0], sizeof(mmMC_HUB_WDP_SH2)/sizeof(mmMC_HUB_WDP_SH2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH3", REG_MMIO, 0x84e, &mmMC_HUB_WDP_SH3[0], sizeof(mmMC_HUB_WDP_SH3)/sizeof(mmMC_HUB_WDP_SH3[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_IA0", REG_MMIO, 0x84f, &mmMC_HUB_RDREQ_IA0[0], sizeof(mmMC_HUB_RDREQ_IA0)/sizeof(mmMC_HUB_RDREQ_IA0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_133", REG_SMC, 0x85, &ixMC_IO_DEBUG_UP_133[0], sizeof(ixMC_IO_DEBUG_UP_133)/sizeof(ixMC_IO_DEBUG_UP_133[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_IA1", REG_MMIO, 0x850, &mmMC_HUB_RDREQ_IA1[0], sizeof(mmMC_HUB_RDREQ_IA1)/sizeof(mmMC_HUB_RDREQ_IA1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDW", REG_MMIO, 0x851, &mmMC_HUB_RDREQ_MCDW[0], sizeof(mmMC_HUB_RDREQ_MCDW)/sizeof(mmMC_HUB_RDREQ_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDX", REG_MMIO, 0x852, &mmMC_HUB_RDREQ_MCDX[0], sizeof(mmMC_HUB_RDREQ_MCDX)/sizeof(mmMC_HUB_RDREQ_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDY", REG_MMIO, 0x853, &mmMC_HUB_RDREQ_MCDY[0], sizeof(mmMC_HUB_RDREQ_MCDY)/sizeof(mmMC_HUB_RDREQ_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDZ", REG_MMIO, 0x854, &mmMC_HUB_RDREQ_MCDZ[0], sizeof(mmMC_HUB_RDREQ_MCDZ)/sizeof(mmMC_HUB_RDREQ_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SIP", REG_MMIO, 0x855, &mmMC_HUB_RDREQ_SIP[0], sizeof(mmMC_HUB_RDREQ_SIP)/sizeof(mmMC_HUB_RDREQ_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL0", REG_MMIO, 0x856, &mmMC_HUB_RDREQ_GBL0[0], sizeof(mmMC_HUB_RDREQ_GBL0)/sizeof(mmMC_HUB_RDREQ_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL1", REG_MMIO, 0x857, &mmMC_HUB_RDREQ_GBL1[0], sizeof(mmMC_HUB_RDREQ_GBL1)/sizeof(mmMC_HUB_RDREQ_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SMU", REG_MMIO, 0x858, &mmMC_HUB_RDREQ_SMU[0], sizeof(mmMC_HUB_RDREQ_SMU)/sizeof(mmMC_HUB_RDREQ_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CPG", REG_MMIO, 0x859, &mmMC_HUB_RDREQ_CPG[0], sizeof(mmMC_HUB_RDREQ_CPG)/sizeof(mmMC_HUB_RDREQ_CPG[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SDMA0", REG_MMIO, 0x85a, &mmMC_HUB_RDREQ_SDMA0[0], sizeof(mmMC_HUB_RDREQ_SDMA0)/sizeof(mmMC_HUB_RDREQ_SDMA0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_HDP", REG_MMIO, 0x85b, &mmMC_HUB_RDREQ_HDP[0], sizeof(mmMC_HUB_RDREQ_HDP)/sizeof(mmMC_HUB_RDREQ_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SDMA1", REG_MMIO, 0x85c, &mmMC_HUB_RDREQ_SDMA1[0], sizeof(mmMC_HUB_RDREQ_SDMA1)/sizeof(mmMC_HUB_RDREQ_SDMA1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_RLC", REG_MMIO, 0x85d, &mmMC_HUB_RDREQ_RLC[0], sizeof(mmMC_HUB_RDREQ_RLC)/sizeof(mmMC_HUB_RDREQ_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SEM", REG_MMIO, 0x85e, &mmMC_HUB_RDREQ_SEM[0], sizeof(mmMC_HUB_RDREQ_SEM)/sizeof(mmMC_HUB_RDREQ_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCE", REG_MMIO, 0x85f, &mmMC_HUB_RDREQ_VCE[0], sizeof(mmMC_HUB_RDREQ_VCE)/sizeof(mmMC_HUB_RDREQ_VCE[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_134", REG_SMC, 0x86, &ixMC_IO_DEBUG_UP_134[0], sizeof(ixMC_IO_DEBUG_UP_134)/sizeof(ixMC_IO_DEBUG_UP_134[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UMC", REG_MMIO, 0x860, &mmMC_HUB_RDREQ_UMC[0], sizeof(mmMC_HUB_RDREQ_UMC)/sizeof(mmMC_HUB_RDREQ_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UVD", REG_MMIO, 0x861, &mmMC_HUB_RDREQ_UVD[0], sizeof(mmMC_HUB_RDREQ_UVD)/sizeof(mmMC_HUB_RDREQ_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_IA", REG_MMIO, 0x862, &mmMC_HUB_RDREQ_IA[0], sizeof(mmMC_HUB_RDREQ_IA)/sizeof(mmMC_HUB_RDREQ_IA[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF", REG_MMIO, 0x863, &mmMC_HUB_RDREQ_DMIF[0], sizeof(mmMC_HUB_RDREQ_DMIF)/sizeof(mmMC_HUB_RDREQ_DMIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCIF", REG_MMIO, 0x864, &mmMC_HUB_RDREQ_MCIF[0], sizeof(mmMC_HUB_RDREQ_MCIF)/sizeof(mmMC_HUB_RDREQ_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VMC", REG_MMIO, 0x865, &mmMC_HUB_RDREQ_VMC[0], sizeof(mmMC_HUB_RDREQ_VMC)/sizeof(mmMC_HUB_RDREQ_VMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCEU", REG_MMIO, 0x866, &mmMC_HUB_RDREQ_VCEU[0], sizeof(mmMC_HUB_RDREQ_VCEU)/sizeof(mmMC_HUB_RDREQ_VCEU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDW", REG_MMIO, 0x867, &mmMC_HUB_WDP_MCDW[0], sizeof(mmMC_HUB_WDP_MCDW)/sizeof(mmMC_HUB_WDP_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDX", REG_MMIO, 0x868, &mmMC_HUB_WDP_MCDX[0], sizeof(mmMC_HUB_WDP_MCDX)/sizeof(mmMC_HUB_WDP_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDY", REG_MMIO, 0x869, &mmMC_HUB_WDP_MCDY[0], sizeof(mmMC_HUB_WDP_MCDY)/sizeof(mmMC_HUB_WDP_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDZ", REG_MMIO, 0x86a, &mmMC_HUB_WDP_MCDZ[0], sizeof(mmMC_HUB_WDP_MCDZ)/sizeof(mmMC_HUB_WDP_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SIP", REG_MMIO, 0x86b, &mmMC_HUB_WDP_SIP[0], sizeof(mmMC_HUB_WDP_SIP)/sizeof(mmMC_HUB_WDP_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CPG", REG_MMIO, 0x86c, &mmMC_HUB_WDP_CPG[0], sizeof(mmMC_HUB_WDP_CPG)/sizeof(mmMC_HUB_WDP_CPG[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SDMA1", REG_MMIO, 0x86d, &mmMC_HUB_WDP_SDMA1[0], sizeof(mmMC_HUB_WDP_SDMA1)/sizeof(mmMC_HUB_WDP_SDMA1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH0", REG_MMIO, 0x86e, &mmMC_HUB_WDP_SH0[0], sizeof(mmMC_HUB_WDP_SH0)/sizeof(mmMC_HUB_WDP_SH0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCIF", REG_MMIO, 0x86f, &mmMC_HUB_WDP_MCIF[0], sizeof(mmMC_HUB_WDP_MCIF)/sizeof(mmMC_HUB_WDP_MCIF[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_135", REG_SMC, 0x87, &ixMC_IO_DEBUG_UP_135[0], sizeof(ixMC_IO_DEBUG_UP_135)/sizeof(ixMC_IO_DEBUG_UP_135[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCE", REG_MMIO, 0x870, &mmMC_HUB_WDP_VCE[0], sizeof(mmMC_HUB_WDP_VCE)/sizeof(mmMC_HUB_WDP_VCE[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDP", REG_MMIO, 0x871, &mmMC_HUB_WDP_XDP[0], sizeof(mmMC_HUB_WDP_XDP)/sizeof(mmMC_HUB_WDP_XDP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_IH", REG_MMIO, 0x872, &mmMC_HUB_WDP_IH[0], sizeof(mmMC_HUB_WDP_IH)/sizeof(mmMC_HUB_WDP_IH[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_RLC", REG_MMIO, 0x873, &mmMC_HUB_WDP_RLC[0], sizeof(mmMC_HUB_WDP_RLC)/sizeof(mmMC_HUB_WDP_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SEM", REG_MMIO, 0x874, &mmMC_HUB_WDP_SEM[0], sizeof(mmMC_HUB_WDP_SEM)/sizeof(mmMC_HUB_WDP_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SMU", REG_MMIO, 0x875, &mmMC_HUB_WDP_SMU[0], sizeof(mmMC_HUB_WDP_SMU)/sizeof(mmMC_HUB_WDP_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH1", REG_MMIO, 0x876, &mmMC_HUB_WDP_SH1[0], sizeof(mmMC_HUB_WDP_SH1)/sizeof(mmMC_HUB_WDP_SH1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UMC", REG_MMIO, 0x877, &mmMC_HUB_WDP_UMC[0], sizeof(mmMC_HUB_WDP_UMC)/sizeof(mmMC_HUB_WDP_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UVD", REG_MMIO, 0x878, &mmMC_HUB_WDP_UVD[0], sizeof(mmMC_HUB_WDP_UVD)/sizeof(mmMC_HUB_WDP_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_HDP", REG_MMIO, 0x879, &mmMC_HUB_WDP_HDP[0], sizeof(mmMC_HUB_WDP_HDP)/sizeof(mmMC_HUB_WDP_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SDMA0", REG_MMIO, 0x87a, &mmMC_HUB_WDP_SDMA0[0], sizeof(mmMC_HUB_WDP_SDMA0)/sizeof(mmMC_HUB_WDP_SDMA0[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDW", REG_MMIO, 0x87b, &mmMC_HUB_WRRET_MCDW[0], sizeof(mmMC_HUB_WRRET_MCDW)/sizeof(mmMC_HUB_WRRET_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDX", REG_MMIO, 0x87c, &mmMC_HUB_WRRET_MCDX[0], sizeof(mmMC_HUB_WRRET_MCDX)/sizeof(mmMC_HUB_WRRET_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDY", REG_MMIO, 0x87d, &mmMC_HUB_WRRET_MCDY[0], sizeof(mmMC_HUB_WRRET_MCDY)/sizeof(mmMC_HUB_WRRET_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDZ", REG_MMIO, 0x87e, &mmMC_HUB_WRRET_MCDZ[0], sizeof(mmMC_HUB_WRRET_MCDZ)/sizeof(mmMC_HUB_WRRET_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCEU", REG_MMIO, 0x87f, &mmMC_HUB_WDP_VCEU[0], sizeof(mmMC_HUB_WDP_VCEU)/sizeof(mmMC_HUB_WDP_VCEU[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_136", REG_SMC, 0x88, &ixMC_IO_DEBUG_UP_136[0], sizeof(ixMC_IO_DEBUG_UP_136)/sizeof(ixMC_IO_DEBUG_UP_136[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMAM", REG_MMIO, 0x880, &mmMC_HUB_WDP_XDMAM[0], sizeof(mmMC_HUB_WDP_XDMAM)/sizeof(mmMC_HUB_WDP_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMA", REG_MMIO, 0x881, &mmMC_HUB_WDP_XDMA[0], sizeof(mmMC_HUB_WDP_XDMA)/sizeof(mmMC_HUB_WDP_XDMA[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_XDMAM", REG_MMIO, 0x882, &mmMC_HUB_RDREQ_XDMAM[0], sizeof(mmMC_HUB_RDREQ_XDMAM)/sizeof(mmMC_HUB_RDREQ_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPG", REG_MMIO, 0x883, &mmMC_HUB_RDREQ_ACPG[0], sizeof(mmMC_HUB_RDREQ_ACPG)/sizeof(mmMC_HUB_RDREQ_ACPG[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPO", REG_MMIO, 0x884, &mmMC_HUB_RDREQ_ACPO[0], sizeof(mmMC_HUB_RDREQ_ACPO)/sizeof(mmMC_HUB_RDREQ_ACPO[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SAM", REG_MMIO, 0x885, &mmMC_HUB_RDREQ_SAM[0], sizeof(mmMC_HUB_RDREQ_SAM)/sizeof(mmMC_HUB_RDREQ_SAM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ACPG", REG_MMIO, 0x886, &mmMC_HUB_WDP_ACPG[0], sizeof(mmMC_HUB_WDP_ACPG)/sizeof(mmMC_HUB_WDP_ACPG[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ACPO", REG_MMIO, 0x887, &mmMC_HUB_WDP_ACPO[0], sizeof(mmMC_HUB_WDP_ACPO)/sizeof(mmMC_HUB_WDP_ACPO[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SAM", REG_MMIO, 0x888, &mmMC_HUB_WDP_SAM[0], sizeof(mmMC_HUB_WDP_SAM)/sizeof(mmMC_HUB_WDP_SAM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CPC", REG_MMIO, 0x889, &mmMC_HUB_RDREQ_CPC[0], sizeof(mmMC_HUB_RDREQ_CPC)/sizeof(mmMC_HUB_RDREQ_CPC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CPF", REG_MMIO, 0x88a, &mmMC_HUB_RDREQ_CPF[0], sizeof(mmMC_HUB_RDREQ_CPF)/sizeof(mmMC_HUB_RDREQ_CPF[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CPC", REG_MMIO, 0x88b, &mmMC_HUB_WDP_CPC[0], sizeof(mmMC_HUB_WDP_CPC)/sizeof(mmMC_HUB_WDP_CPC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CPF", REG_MMIO, 0x88c, &mmMC_HUB_WDP_CPF[0], sizeof(mmMC_HUB_WDP_CPF)/sizeof(mmMC_HUB_WDP_CPF[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_137", REG_SMC, 0x89, &ixMC_IO_DEBUG_UP_137[0], sizeof(ixMC_IO_DEBUG_UP_137)/sizeof(ixMC_IO_DEBUG_UP_137[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_DEBUG", REG_MMIO, 0x891, &mmMC_VM_MB_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_DEBUG", REG_MMIO, 0x893, &mmMC_VM_MB_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_STATUS", REG_MMIO, 0x895, &mmMC_VM_MB_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB0_STATUS)/sizeof(mmMC_VM_MB_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB1_STATUS", REG_MMIO, 0x896, &mmMC_VM_MB_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB1_STATUS)/sizeof(mmMC_VM_MB_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_STATUS", REG_MMIO, 0x897, &mmMC_VM_MB_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB2_STATUS)/sizeof(mmMC_VM_MB_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_138", REG_SMC, 0x8a, &ixMC_IO_DEBUG_UP_138[0], sizeof(ixMC_IO_DEBUG_UP_138)/sizeof(ixMC_IO_DEBUG_UP_138[0]), 0, 0 },
+	{ "mmMC_VM_MB_L2ARBITER_L2_CREDITS", REG_MMIO, 0x8a1, &mmMC_VM_MB_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_DEBUG", REG_MMIO, 0x8a5, &mmMC_VM_MB_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_STATUS", REG_MMIO, 0x8a6, &mmMC_VM_MB_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB3_STATUS)/sizeof(mmMC_VM_MB_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_139", REG_SMC, 0x8b, &ixMC_IO_DEBUG_UP_139[0], sizeof(ixMC_IO_DEBUG_UP_139)/sizeof(ixMC_IO_DEBUG_UP_139[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_140", REG_SMC, 0x8c, &ixMC_IO_DEBUG_UP_140[0], sizeof(ixMC_IO_DEBUG_UP_140)/sizeof(ixMC_IO_DEBUG_UP_140[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR0", REG_MMIO, 0x8cd, &mmMC_XPB_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR1", REG_MMIO, 0x8ce, &mmMC_XPB_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR2", REG_MMIO, 0x8cf, &mmMC_XPB_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_141", REG_SMC, 0x8d, &ixMC_IO_DEBUG_UP_141[0], sizeof(ixMC_IO_DEBUG_UP_141)/sizeof(ixMC_IO_DEBUG_UP_141[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR3", REG_MMIO, 0x8d0, &mmMC_XPB_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR4", REG_MMIO, 0x8d1, &mmMC_XPB_RTR_SRC_APRTR4[0], sizeof(mmMC_XPB_RTR_SRC_APRTR4)/sizeof(mmMC_XPB_RTR_SRC_APRTR4[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR5", REG_MMIO, 0x8d2, &mmMC_XPB_RTR_SRC_APRTR5[0], sizeof(mmMC_XPB_RTR_SRC_APRTR5)/sizeof(mmMC_XPB_RTR_SRC_APRTR5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR6", REG_MMIO, 0x8d3, &mmMC_XPB_RTR_SRC_APRTR6[0], sizeof(mmMC_XPB_RTR_SRC_APRTR6)/sizeof(mmMC_XPB_RTR_SRC_APRTR6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR7", REG_MMIO, 0x8d4, &mmMC_XPB_RTR_SRC_APRTR7[0], sizeof(mmMC_XPB_RTR_SRC_APRTR7)/sizeof(mmMC_XPB_RTR_SRC_APRTR7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR8", REG_MMIO, 0x8d5, &mmMC_XPB_RTR_SRC_APRTR8[0], sizeof(mmMC_XPB_RTR_SRC_APRTR8)/sizeof(mmMC_XPB_RTR_SRC_APRTR8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR9", REG_MMIO, 0x8d6, &mmMC_XPB_RTR_SRC_APRTR9[0], sizeof(mmMC_XPB_RTR_SRC_APRTR9)/sizeof(mmMC_XPB_RTR_SRC_APRTR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR0", REG_MMIO, 0x8d7, &mmMC_XPB_XDMA_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR1", REG_MMIO, 0x8d8, &mmMC_XPB_XDMA_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR2", REG_MMIO, 0x8d9, &mmMC_XPB_XDMA_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR3", REG_MMIO, 0x8da, &mmMC_XPB_XDMA_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP0", REG_MMIO, 0x8db, &mmMC_XPB_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_RTR_DEST_MAP0)/sizeof(mmMC_XPB_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP1", REG_MMIO, 0x8dc, &mmMC_XPB_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_RTR_DEST_MAP1)/sizeof(mmMC_XPB_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP2", REG_MMIO, 0x8dd, &mmMC_XPB_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_RTR_DEST_MAP2)/sizeof(mmMC_XPB_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP3", REG_MMIO, 0x8de, &mmMC_XPB_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_RTR_DEST_MAP3)/sizeof(mmMC_XPB_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP4", REG_MMIO, 0x8df, &mmMC_XPB_RTR_DEST_MAP4[0], sizeof(mmMC_XPB_RTR_DEST_MAP4)/sizeof(mmMC_XPB_RTR_DEST_MAP4[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_142", REG_SMC, 0x8e, &ixMC_IO_DEBUG_UP_142[0], sizeof(ixMC_IO_DEBUG_UP_142)/sizeof(ixMC_IO_DEBUG_UP_142[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP5", REG_MMIO, 0x8e0, &mmMC_XPB_RTR_DEST_MAP5[0], sizeof(mmMC_XPB_RTR_DEST_MAP5)/sizeof(mmMC_XPB_RTR_DEST_MAP5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP6", REG_MMIO, 0x8e1, &mmMC_XPB_RTR_DEST_MAP6[0], sizeof(mmMC_XPB_RTR_DEST_MAP6)/sizeof(mmMC_XPB_RTR_DEST_MAP6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP7", REG_MMIO, 0x8e2, &mmMC_XPB_RTR_DEST_MAP7[0], sizeof(mmMC_XPB_RTR_DEST_MAP7)/sizeof(mmMC_XPB_RTR_DEST_MAP7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP8", REG_MMIO, 0x8e3, &mmMC_XPB_RTR_DEST_MAP8[0], sizeof(mmMC_XPB_RTR_DEST_MAP8)/sizeof(mmMC_XPB_RTR_DEST_MAP8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP9", REG_MMIO, 0x8e4, &mmMC_XPB_RTR_DEST_MAP9[0], sizeof(mmMC_XPB_RTR_DEST_MAP9)/sizeof(mmMC_XPB_RTR_DEST_MAP9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP0", REG_MMIO, 0x8e5, &mmMC_XPB_XDMA_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP1", REG_MMIO, 0x8e6, &mmMC_XPB_XDMA_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP2", REG_MMIO, 0x8e7, &mmMC_XPB_XDMA_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP3", REG_MMIO, 0x8e8, &mmMC_XPB_XDMA_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG0", REG_MMIO, 0x8e9, &mmMC_XPB_CLG_CFG0[0], sizeof(mmMC_XPB_CLG_CFG0)/sizeof(mmMC_XPB_CLG_CFG0[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG1", REG_MMIO, 0x8ea, &mmMC_XPB_CLG_CFG1[0], sizeof(mmMC_XPB_CLG_CFG1)/sizeof(mmMC_XPB_CLG_CFG1[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG2", REG_MMIO, 0x8eb, &mmMC_XPB_CLG_CFG2[0], sizeof(mmMC_XPB_CLG_CFG2)/sizeof(mmMC_XPB_CLG_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG3", REG_MMIO, 0x8ec, &mmMC_XPB_CLG_CFG3[0], sizeof(mmMC_XPB_CLG_CFG3)/sizeof(mmMC_XPB_CLG_CFG3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG4", REG_MMIO, 0x8ed, &mmMC_XPB_CLG_CFG4[0], sizeof(mmMC_XPB_CLG_CFG4)/sizeof(mmMC_XPB_CLG_CFG4[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG5", REG_MMIO, 0x8ee, &mmMC_XPB_CLG_CFG5[0], sizeof(mmMC_XPB_CLG_CFG5)/sizeof(mmMC_XPB_CLG_CFG5[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG6", REG_MMIO, 0x8ef, &mmMC_XPB_CLG_CFG6[0], sizeof(mmMC_XPB_CLG_CFG6)/sizeof(mmMC_XPB_CLG_CFG6[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_143", REG_SMC, 0x8f, &ixMC_IO_DEBUG_UP_143[0], sizeof(ixMC_IO_DEBUG_UP_143)/sizeof(ixMC_IO_DEBUG_UP_143[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG7", REG_MMIO, 0x8f0, &mmMC_XPB_CLG_CFG7[0], sizeof(mmMC_XPB_CLG_CFG7)/sizeof(mmMC_XPB_CLG_CFG7[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG8", REG_MMIO, 0x8f1, &mmMC_XPB_CLG_CFG8[0], sizeof(mmMC_XPB_CLG_CFG8)/sizeof(mmMC_XPB_CLG_CFG8[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG9", REG_MMIO, 0x8f2, &mmMC_XPB_CLG_CFG9[0], sizeof(mmMC_XPB_CLG_CFG9)/sizeof(mmMC_XPB_CLG_CFG9[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG10", REG_MMIO, 0x8f3, &mmMC_XPB_CLG_CFG10[0], sizeof(mmMC_XPB_CLG_CFG10)/sizeof(mmMC_XPB_CLG_CFG10[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG11", REG_MMIO, 0x8f4, &mmMC_XPB_CLG_CFG11[0], sizeof(mmMC_XPB_CLG_CFG11)/sizeof(mmMC_XPB_CLG_CFG11[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG12", REG_MMIO, 0x8f5, &mmMC_XPB_CLG_CFG12[0], sizeof(mmMC_XPB_CLG_CFG12)/sizeof(mmMC_XPB_CLG_CFG12[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG13", REG_MMIO, 0x8f6, &mmMC_XPB_CLG_CFG13[0], sizeof(mmMC_XPB_CLG_CFG13)/sizeof(mmMC_XPB_CLG_CFG13[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG14", REG_MMIO, 0x8f7, &mmMC_XPB_CLG_CFG14[0], sizeof(mmMC_XPB_CLG_CFG14)/sizeof(mmMC_XPB_CLG_CFG14[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG15", REG_MMIO, 0x8f8, &mmMC_XPB_CLG_CFG15[0], sizeof(mmMC_XPB_CLG_CFG15)/sizeof(mmMC_XPB_CLG_CFG15[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG16", REG_MMIO, 0x8f9, &mmMC_XPB_CLG_CFG16[0], sizeof(mmMC_XPB_CLG_CFG16)/sizeof(mmMC_XPB_CLG_CFG16[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG17", REG_MMIO, 0x8fa, &mmMC_XPB_CLG_CFG17[0], sizeof(mmMC_XPB_CLG_CFG17)/sizeof(mmMC_XPB_CLG_CFG17[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG18", REG_MMIO, 0x8fb, &mmMC_XPB_CLG_CFG18[0], sizeof(mmMC_XPB_CLG_CFG18)/sizeof(mmMC_XPB_CLG_CFG18[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG19", REG_MMIO, 0x8fc, &mmMC_XPB_CLG_CFG19[0], sizeof(mmMC_XPB_CLG_CFG19)/sizeof(mmMC_XPB_CLG_CFG19[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA", REG_MMIO, 0x8fd, &mmMC_XPB_CLG_EXTRA[0], sizeof(mmMC_XPB_CLG_EXTRA)/sizeof(mmMC_XPB_CLG_EXTRA[0]), 0, 0 },
+	{ "mmMC_XPB_LB_ADDR", REG_MMIO, 0x8fe, &mmMC_XPB_LB_ADDR[0], sizeof(mmMC_XPB_LB_ADDR)/sizeof(mmMC_XPB_LB_ADDR[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_HST", REG_MMIO, 0x8ff, &mmMC_XPB_UNC_THRESH_HST[0], sizeof(mmMC_XPB_UNC_THRESH_HST)/sizeof(mmMC_XPB_UNC_THRESH_HST[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT6", REG_SMC, 0x9, &ixMC_TSM_DEBUG_BCNT6[0], sizeof(ixMC_TSM_DEBUG_BCNT6)/sizeof(ixMC_TSM_DEBUG_BCNT6[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_9", REG_SMC, 0x9, &ixMC_IO_DEBUG_UP_9[0], sizeof(ixMC_IO_DEBUG_UP_9)/sizeof(ixMC_IO_DEBUG_UP_9[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_144", REG_SMC, 0x90, &ixMC_IO_DEBUG_UP_144[0], sizeof(ixMC_IO_DEBUG_UP_144)/sizeof(ixMC_IO_DEBUG_UP_144[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_SID", REG_MMIO, 0x900, &mmMC_XPB_UNC_THRESH_SID[0], sizeof(mmMC_XPB_UNC_THRESH_SID)/sizeof(mmMC_XPB_UNC_THRESH_SID[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_STS", REG_MMIO, 0x901, &mmMC_XPB_WCB_STS[0], sizeof(mmMC_XPB_WCB_STS)/sizeof(mmMC_XPB_WCB_STS[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_CFG", REG_MMIO, 0x902, &mmMC_XPB_WCB_CFG[0], sizeof(mmMC_XPB_WCB_CFG)/sizeof(mmMC_XPB_WCB_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_CFG", REG_MMIO, 0x903, &mmMC_XPB_P2P_BAR_CFG[0], sizeof(mmMC_XPB_P2P_BAR_CFG)/sizeof(mmMC_XPB_P2P_BAR_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR0", REG_MMIO, 0x904, &mmMC_XPB_P2P_BAR0[0], sizeof(mmMC_XPB_P2P_BAR0)/sizeof(mmMC_XPB_P2P_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR1", REG_MMIO, 0x905, &mmMC_XPB_P2P_BAR1[0], sizeof(mmMC_XPB_P2P_BAR1)/sizeof(mmMC_XPB_P2P_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR2", REG_MMIO, 0x906, &mmMC_XPB_P2P_BAR2[0], sizeof(mmMC_XPB_P2P_BAR2)/sizeof(mmMC_XPB_P2P_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR3", REG_MMIO, 0x907, &mmMC_XPB_P2P_BAR3[0], sizeof(mmMC_XPB_P2P_BAR3)/sizeof(mmMC_XPB_P2P_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR4", REG_MMIO, 0x908, &mmMC_XPB_P2P_BAR4[0], sizeof(mmMC_XPB_P2P_BAR4)/sizeof(mmMC_XPB_P2P_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR5", REG_MMIO, 0x909, &mmMC_XPB_P2P_BAR5[0], sizeof(mmMC_XPB_P2P_BAR5)/sizeof(mmMC_XPB_P2P_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR6", REG_MMIO, 0x90a, &mmMC_XPB_P2P_BAR6[0], sizeof(mmMC_XPB_P2P_BAR6)/sizeof(mmMC_XPB_P2P_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR7", REG_MMIO, 0x90b, &mmMC_XPB_P2P_BAR7[0], sizeof(mmMC_XPB_P2P_BAR7)/sizeof(mmMC_XPB_P2P_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_SETUP", REG_MMIO, 0x90c, &mmMC_XPB_P2P_BAR_SETUP[0], sizeof(mmMC_XPB_P2P_BAR_SETUP)/sizeof(mmMC_XPB_P2P_BAR_SETUP[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DEBUG", REG_MMIO, 0x90d, &mmMC_XPB_P2P_BAR_DEBUG[0], sizeof(mmMC_XPB_P2P_BAR_DEBUG)/sizeof(mmMC_XPB_P2P_BAR_DEBUG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_ABOVE", REG_MMIO, 0x90e, &mmMC_XPB_P2P_BAR_DELTA_ABOVE[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE)/sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_BELOW", REG_MMIO, 0x90f, &mmMC_XPB_P2P_BAR_DELTA_BELOW[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW)/sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_145", REG_SMC, 0x91, &ixMC_IO_DEBUG_UP_145[0], sizeof(ixMC_IO_DEBUG_UP_145)/sizeof(ixMC_IO_DEBUG_UP_145[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR0", REG_MMIO, 0x910, &mmMC_XPB_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_PEER_SYS_BAR0)/sizeof(mmMC_XPB_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR1", REG_MMIO, 0x911, &mmMC_XPB_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_PEER_SYS_BAR1)/sizeof(mmMC_XPB_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR2", REG_MMIO, 0x912, &mmMC_XPB_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_PEER_SYS_BAR2)/sizeof(mmMC_XPB_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR3", REG_MMIO, 0x913, &mmMC_XPB_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_PEER_SYS_BAR3)/sizeof(mmMC_XPB_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR4", REG_MMIO, 0x914, &mmMC_XPB_PEER_SYS_BAR4[0], sizeof(mmMC_XPB_PEER_SYS_BAR4)/sizeof(mmMC_XPB_PEER_SYS_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR5", REG_MMIO, 0x915, &mmMC_XPB_PEER_SYS_BAR5[0], sizeof(mmMC_XPB_PEER_SYS_BAR5)/sizeof(mmMC_XPB_PEER_SYS_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR6", REG_MMIO, 0x916, &mmMC_XPB_PEER_SYS_BAR6[0], sizeof(mmMC_XPB_PEER_SYS_BAR6)/sizeof(mmMC_XPB_PEER_SYS_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR7", REG_MMIO, 0x917, &mmMC_XPB_PEER_SYS_BAR7[0], sizeof(mmMC_XPB_PEER_SYS_BAR7)/sizeof(mmMC_XPB_PEER_SYS_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR8", REG_MMIO, 0x918, &mmMC_XPB_PEER_SYS_BAR8[0], sizeof(mmMC_XPB_PEER_SYS_BAR8)/sizeof(mmMC_XPB_PEER_SYS_BAR8[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR9", REG_MMIO, 0x919, &mmMC_XPB_PEER_SYS_BAR9[0], sizeof(mmMC_XPB_PEER_SYS_BAR9)/sizeof(mmMC_XPB_PEER_SYS_BAR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR0", REG_MMIO, 0x91a, &mmMC_XPB_XDMA_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR1", REG_MMIO, 0x91b, &mmMC_XPB_XDMA_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR2", REG_MMIO, 0x91c, &mmMC_XPB_XDMA_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR3", REG_MMIO, 0x91d, &mmMC_XPB_XDMA_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_CLK_GAT", REG_MMIO, 0x91e, &mmMC_XPB_CLK_GAT[0], sizeof(mmMC_XPB_CLK_GAT)/sizeof(mmMC_XPB_CLK_GAT[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG", REG_MMIO, 0x91f, &mmMC_XPB_INTF_CFG[0], sizeof(mmMC_XPB_INTF_CFG)/sizeof(mmMC_XPB_INTF_CFG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_146", REG_SMC, 0x92, &ixMC_IO_DEBUG_UP_146[0], sizeof(ixMC_IO_DEBUG_UP_146)/sizeof(ixMC_IO_DEBUG_UP_146[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_STS", REG_MMIO, 0x920, &mmMC_XPB_INTF_STS[0], sizeof(mmMC_XPB_INTF_STS)/sizeof(mmMC_XPB_INTF_STS[0]), 0, 0 },
+	{ "mmMC_XPB_PIPE_STS", REG_MMIO, 0x921, &mmMC_XPB_PIPE_STS[0], sizeof(mmMC_XPB_PIPE_STS)/sizeof(mmMC_XPB_PIPE_STS[0]), 0, 0 },
+	{ "mmMC_XPB_SUB_CTRL", REG_MMIO, 0x922, &mmMC_XPB_SUB_CTRL[0], sizeof(mmMC_XPB_SUB_CTRL)/sizeof(mmMC_XPB_SUB_CTRL[0]), 0, 0 },
+	{ "mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB", REG_MMIO, 0x923, &mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0], sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB)/sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0]), 0, 0 },
+	{ "mmMC_XPB_PERF_KNOBS", REG_MMIO, 0x924, &mmMC_XPB_PERF_KNOBS[0], sizeof(mmMC_XPB_PERF_KNOBS)/sizeof(mmMC_XPB_PERF_KNOBS[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY", REG_MMIO, 0x925, &mmMC_XPB_STICKY[0], sizeof(mmMC_XPB_STICKY)/sizeof(mmMC_XPB_STICKY[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY_W1C", REG_MMIO, 0x926, &mmMC_XPB_STICKY_W1C[0], sizeof(mmMC_XPB_STICKY_W1C)/sizeof(mmMC_XPB_STICKY_W1C[0]), 0, 0 },
+	{ "mmMC_XPB_MISC_CFG", REG_MMIO, 0x927, &mmMC_XPB_MISC_CFG[0], sizeof(mmMC_XPB_MISC_CFG)/sizeof(mmMC_XPB_MISC_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG20", REG_MMIO, 0x928, &mmMC_XPB_CLG_CFG20[0], sizeof(mmMC_XPB_CLG_CFG20)/sizeof(mmMC_XPB_CLG_CFG20[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG21", REG_MMIO, 0x929, &mmMC_XPB_CLG_CFG21[0], sizeof(mmMC_XPB_CLG_CFG21)/sizeof(mmMC_XPB_CLG_CFG21[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG22", REG_MMIO, 0x92a, &mmMC_XPB_CLG_CFG22[0], sizeof(mmMC_XPB_CLG_CFG22)/sizeof(mmMC_XPB_CLG_CFG22[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG23", REG_MMIO, 0x92b, &mmMC_XPB_CLG_CFG23[0], sizeof(mmMC_XPB_CLG_CFG23)/sizeof(mmMC_XPB_CLG_CFG23[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG24", REG_MMIO, 0x92c, &mmMC_XPB_CLG_CFG24[0], sizeof(mmMC_XPB_CLG_CFG24)/sizeof(mmMC_XPB_CLG_CFG24[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG25", REG_MMIO, 0x92d, &mmMC_XPB_CLG_CFG25[0], sizeof(mmMC_XPB_CLG_CFG25)/sizeof(mmMC_XPB_CLG_CFG25[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG26", REG_MMIO, 0x92e, &mmMC_XPB_CLG_CFG26[0], sizeof(mmMC_XPB_CLG_CFG26)/sizeof(mmMC_XPB_CLG_CFG26[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG27", REG_MMIO, 0x92f, &mmMC_XPB_CLG_CFG27[0], sizeof(mmMC_XPB_CLG_CFG27)/sizeof(mmMC_XPB_CLG_CFG27[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_147", REG_SMC, 0x93, &ixMC_IO_DEBUG_UP_147[0], sizeof(ixMC_IO_DEBUG_UP_147)/sizeof(ixMC_IO_DEBUG_UP_147[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG28", REG_MMIO, 0x930, &mmMC_XPB_CLG_CFG28[0], sizeof(mmMC_XPB_CLG_CFG28)/sizeof(mmMC_XPB_CLG_CFG28[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG29", REG_MMIO, 0x931, &mmMC_XPB_CLG_CFG29[0], sizeof(mmMC_XPB_CLG_CFG29)/sizeof(mmMC_XPB_CLG_CFG29[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG30", REG_MMIO, 0x932, &mmMC_XPB_CLG_CFG30[0], sizeof(mmMC_XPB_CLG_CFG30)/sizeof(mmMC_XPB_CLG_CFG30[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG31", REG_MMIO, 0x933, &mmMC_XPB_CLG_CFG31[0], sizeof(mmMC_XPB_CLG_CFG31)/sizeof(mmMC_XPB_CLG_CFG31[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG2", REG_MMIO, 0x934, &mmMC_XPB_INTF_CFG2[0], sizeof(mmMC_XPB_INTF_CFG2)/sizeof(mmMC_XPB_INTF_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA_RD", REG_MMIO, 0x935, &mmMC_XPB_CLG_EXTRA_RD[0], sizeof(mmMC_XPB_CLG_EXTRA_RD)/sizeof(mmMC_XPB_CLG_EXTRA_RD[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG32", REG_MMIO, 0x936, &mmMC_XPB_CLG_CFG32[0], sizeof(mmMC_XPB_CLG_CFG32)/sizeof(mmMC_XPB_CLG_CFG32[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG33", REG_MMIO, 0x937, &mmMC_XPB_CLG_CFG33[0], sizeof(mmMC_XPB_CLG_CFG33)/sizeof(mmMC_XPB_CLG_CFG33[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG34", REG_MMIO, 0x938, &mmMC_XPB_CLG_CFG34[0], sizeof(mmMC_XPB_CLG_CFG34)/sizeof(mmMC_XPB_CLG_CFG34[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG35", REG_MMIO, 0x939, &mmMC_XPB_CLG_CFG35[0], sizeof(mmMC_XPB_CLG_CFG35)/sizeof(mmMC_XPB_CLG_CFG35[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG36", REG_MMIO, 0x93a, &mmMC_XPB_CLG_CFG36[0], sizeof(mmMC_XPB_CLG_CFG36)/sizeof(mmMC_XPB_CLG_CFG36[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_148", REG_SMC, 0x94, &ixMC_IO_DEBUG_UP_148[0], sizeof(ixMC_IO_DEBUG_UP_148)/sizeof(ixMC_IO_DEBUG_UP_148[0]), 0, 0 },
+	{ "mmMC_RPB_CONF", REG_MMIO, 0x94d, &mmMC_RPB_CONF[0], sizeof(mmMC_RPB_CONF)/sizeof(mmMC_RPB_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_IF_CONF", REG_MMIO, 0x94e, &mmMC_RPB_IF_CONF[0], sizeof(mmMC_RPB_IF_CONF)/sizeof(mmMC_RPB_IF_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_DBG1", REG_MMIO, 0x94f, &mmMC_RPB_DBG1[0], sizeof(mmMC_RPB_DBG1)/sizeof(mmMC_RPB_DBG1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_149", REG_SMC, 0x95, &ixMC_IO_DEBUG_UP_149[0], sizeof(ixMC_IO_DEBUG_UP_149)/sizeof(ixMC_IO_DEBUG_UP_149[0]), 0, 0 },
+	{ "mmMC_RPB_EFF_CNTL", REG_MMIO, 0x950, &mmMC_RPB_EFF_CNTL[0], sizeof(mmMC_RPB_EFF_CNTL)/sizeof(mmMC_RPB_EFF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_ARB_CNTL", REG_MMIO, 0x951, &mmMC_RPB_ARB_CNTL[0], sizeof(mmMC_RPB_ARB_CNTL)/sizeof(mmMC_RPB_ARB_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_BIF_CNTL", REG_MMIO, 0x952, &mmMC_RPB_BIF_CNTL[0], sizeof(mmMC_RPB_BIF_CNTL)/sizeof(mmMC_RPB_BIF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_SWITCH_CNTL", REG_MMIO, 0x953, &mmMC_RPB_WR_SWITCH_CNTL[0], sizeof(mmMC_RPB_WR_SWITCH_CNTL)/sizeof(mmMC_RPB_WR_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_COMBINE_CNTL", REG_MMIO, 0x954, &mmMC_RPB_WR_COMBINE_CNTL[0], sizeof(mmMC_RPB_WR_COMBINE_CNTL)/sizeof(mmMC_RPB_WR_COMBINE_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_RD_SWITCH_CNTL", REG_MMIO, 0x955, &mmMC_RPB_RD_SWITCH_CNTL[0], sizeof(mmMC_RPB_RD_SWITCH_CNTL)/sizeof(mmMC_RPB_RD_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_WR", REG_MMIO, 0x956, &mmMC_RPB_CID_QUEUE_WR[0], sizeof(mmMC_RPB_CID_QUEUE_WR)/sizeof(mmMC_RPB_CID_QUEUE_WR[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_RD", REG_MMIO, 0x957, &mmMC_RPB_CID_QUEUE_RD[0], sizeof(mmMC_RPB_CID_QUEUE_RD)/sizeof(mmMC_RPB_CID_QUEUE_RD[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_CNTL", REG_MMIO, 0x958, &mmMC_RPB_PERF_COUNTER_CNTL[0], sizeof(mmMC_RPB_PERF_COUNTER_CNTL)/sizeof(mmMC_RPB_PERF_COUNTER_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_STATUS", REG_MMIO, 0x959, &mmMC_RPB_PERF_COUNTER_STATUS[0], sizeof(mmMC_RPB_PERF_COUNTER_STATUS)/sizeof(mmMC_RPB_PERF_COUNTER_STATUS[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX", REG_MMIO, 0x95a, &mmMC_RPB_CID_QUEUE_EX[0], sizeof(mmMC_RPB_CID_QUEUE_EX)/sizeof(mmMC_RPB_CID_QUEUE_EX[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX_DATA", REG_MMIO, 0x95b, &mmMC_RPB_CID_QUEUE_EX_DATA[0], sizeof(mmMC_RPB_CID_QUEUE_EX_DATA)/sizeof(mmMC_RPB_CID_QUEUE_EX_DATA[0]), 0, 0 },
+	{ "mmMC_RPB_TCI_CNTL", REG_MMIO, 0x95c, &mmMC_RPB_TCI_CNTL[0], sizeof(mmMC_RPB_TCI_CNTL)/sizeof(mmMC_RPB_TCI_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_150", REG_SMC, 0x96, &ixMC_IO_DEBUG_UP_150[0], sizeof(ixMC_IO_DEBUG_UP_150)/sizeof(ixMC_IO_DEBUG_UP_150[0]), 0, 0 },
+	{ "mmMC_CITF_XTRA_ENABLE", REG_MMIO, 0x96d, &mmMC_CITF_XTRA_ENABLE[0], sizeof(mmMC_CITF_XTRA_ENABLE)/sizeof(mmMC_CITF_XTRA_ENABLE[0]), 0, 0 },
+	{ "mmCC_MC_MAX_CHANNEL", REG_MMIO, 0x96e, &mmCC_MC_MAX_CHANNEL[0], sizeof(mmCC_MC_MAX_CHANNEL)/sizeof(mmCC_MC_MAX_CHANNEL[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG", REG_MMIO, 0x96f, &mmMC_CG_CONFIG[0], sizeof(mmMC_CG_CONFIG)/sizeof(mmMC_CG_CONFIG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_151", REG_SMC, 0x97, &ixMC_IO_DEBUG_UP_151[0], sizeof(ixMC_IO_DEBUG_UP_151)/sizeof(ixMC_IO_DEBUG_UP_151[0]), 0, 0 },
+	{ "mmMC_CITF_CNTL", REG_MMIO, 0x970, &mmMC_CITF_CNTL[0], sizeof(mmMC_CITF_CNTL)/sizeof(mmMC_CITF_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_VM", REG_MMIO, 0x971, &mmMC_CITF_CREDITS_VM[0], sizeof(mmMC_CITF_CREDITS_VM)/sizeof(mmMC_CITF_CREDITS_VM[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_RD", REG_MMIO, 0x972, &mmMC_CITF_CREDITS_ARB_RD[0], sizeof(mmMC_CITF_CREDITS_ARB_RD)/sizeof(mmMC_CITF_CREDITS_ARB_RD[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_WR", REG_MMIO, 0x973, &mmMC_CITF_CREDITS_ARB_WR[0], sizeof(mmMC_CITF_CREDITS_ARB_WR)/sizeof(mmMC_CITF_CREDITS_ARB_WR[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_CNTL", REG_MMIO, 0x974, &mmMC_CITF_DAGB_CNTL[0], sizeof(mmMC_CITF_DAGB_CNTL)/sizeof(mmMC_CITF_DAGB_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS", REG_MMIO, 0x975, &mmMC_CITF_INT_CREDITS[0], sizeof(mmMC_CITF_INT_CREDITS)/sizeof(mmMC_CITF_INT_CREDITS[0]), 0, 0 },
+	{ "mmMC_CITF_RET_MODE", REG_MMIO, 0x976, &mmMC_CITF_RET_MODE[0], sizeof(mmMC_CITF_RET_MODE)/sizeof(mmMC_CITF_RET_MODE[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_DLY", REG_MMIO, 0x977, &mmMC_CITF_DAGB_DLY[0], sizeof(mmMC_CITF_DAGB_DLY)/sizeof(mmMC_CITF_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_RD_GRP_EXT", REG_MMIO, 0x978, &mmMC_RD_GRP_EXT[0], sizeof(mmMC_RD_GRP_EXT)/sizeof(mmMC_RD_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_WR_GRP_EXT", REG_MMIO, 0x979, &mmMC_WR_GRP_EXT[0], sizeof(mmMC_WR_GRP_EXT)/sizeof(mmMC_WR_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_CITF_REMREQ", REG_MMIO, 0x97a, &mmMC_CITF_REMREQ[0], sizeof(mmMC_CITF_REMREQ)/sizeof(mmMC_CITF_REMREQ[0]), 0, 0 },
+	{ "mmMC_WR_TC0", REG_MMIO, 0x97b, &mmMC_WR_TC0[0], sizeof(mmMC_WR_TC0)/sizeof(mmMC_WR_TC0[0]), 0, 0 },
+	{ "mmMC_WR_TC1", REG_MMIO, 0x97c, &mmMC_WR_TC1[0], sizeof(mmMC_WR_TC1)/sizeof(mmMC_WR_TC1[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS_WR", REG_MMIO, 0x97d, &mmMC_CITF_INT_CREDITS_WR[0], sizeof(mmMC_CITF_INT_CREDITS_WR)/sizeof(mmMC_CITF_INT_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_RD_CNTL", REG_MMIO, 0x97f, &mmMC_CITF_WTM_RD_CNTL[0], sizeof(mmMC_CITF_WTM_RD_CNTL)/sizeof(mmMC_CITF_WTM_RD_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_152", REG_SMC, 0x98, &ixMC_IO_DEBUG_UP_152[0], sizeof(ixMC_IO_DEBUG_UP_152)/sizeof(ixMC_IO_DEBUG_UP_152[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_WR_CNTL", REG_MMIO, 0x980, &mmMC_CITF_WTM_WR_CNTL[0], sizeof(mmMC_CITF_WTM_WR_CNTL)/sizeof(mmMC_CITF_WTM_WR_CNTL[0]), 0, 0 },
+	{ "mmMC_RD_CB", REG_MMIO, 0x981, &mmMC_RD_CB[0], sizeof(mmMC_RD_CB)/sizeof(mmMC_RD_CB[0]), 0, 0 },
+	{ "mmMC_RD_DB", REG_MMIO, 0x982, &mmMC_RD_DB[0], sizeof(mmMC_RD_DB)/sizeof(mmMC_RD_DB[0]), 0, 0 },
+	{ "mmMC_RD_TC0", REG_MMIO, 0x983, &mmMC_RD_TC0[0], sizeof(mmMC_RD_TC0)/sizeof(mmMC_RD_TC0[0]), 0, 0 },
+	{ "mmMC_RD_TC1", REG_MMIO, 0x984, &mmMC_RD_TC1[0], sizeof(mmMC_RD_TC1)/sizeof(mmMC_RD_TC1[0]), 0, 0 },
+	{ "mmMC_RD_HUB", REG_MMIO, 0x985, &mmMC_RD_HUB[0], sizeof(mmMC_RD_HUB)/sizeof(mmMC_RD_HUB[0]), 0, 0 },
+	{ "mmMC_WR_CB", REG_MMIO, 0x986, &mmMC_WR_CB[0], sizeof(mmMC_WR_CB)/sizeof(mmMC_WR_CB[0]), 0, 0 },
+	{ "mmMC_WR_DB", REG_MMIO, 0x987, &mmMC_WR_DB[0], sizeof(mmMC_WR_DB)/sizeof(mmMC_WR_DB[0]), 0, 0 },
+	{ "mmMC_WR_HUB", REG_MMIO, 0x988, &mmMC_WR_HUB[0], sizeof(mmMC_WR_HUB)/sizeof(mmMC_WR_HUB[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_XBAR", REG_MMIO, 0x989, &mmMC_CITF_CREDITS_XBAR[0], sizeof(mmMC_CITF_CREDITS_XBAR)/sizeof(mmMC_CITF_CREDITS_XBAR[0]), 0, 0 },
+	{ "mmMC_RD_GRP_LCL", REG_MMIO, 0x98a, &mmMC_RD_GRP_LCL[0], sizeof(mmMC_RD_GRP_LCL)/sizeof(mmMC_RD_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_WR_GRP_LCL", REG_MMIO, 0x98b, &mmMC_WR_GRP_LCL[0], sizeof(mmMC_WR_GRP_LCL)/sizeof(mmMC_WR_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_CNTL2", REG_MMIO, 0x98e, &mmMC_CITF_PERF_MON_CNTL2[0], sizeof(mmMC_CITF_PERF_MON_CNTL2)/sizeof(mmMC_CITF_PERF_MON_CNTL2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_153", REG_SMC, 0x99, &ixMC_IO_DEBUG_UP_153[0], sizeof(ixMC_IO_DEBUG_UP_153)/sizeof(ixMC_IO_DEBUG_UP_153[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_RSLT2", REG_MMIO, 0x991, &mmMC_CITF_PERF_MON_RSLT2[0], sizeof(mmMC_CITF_PERF_MON_RSLT2)/sizeof(mmMC_CITF_PERF_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_RD_CG", REG_MMIO, 0x992, &mmMC_CITF_MISC_RD_CG[0], sizeof(mmMC_CITF_MISC_RD_CG)/sizeof(mmMC_CITF_MISC_RD_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_WR_CG", REG_MMIO, 0x993, &mmMC_CITF_MISC_WR_CG[0], sizeof(mmMC_CITF_MISC_WR_CG)/sizeof(mmMC_CITF_MISC_WR_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_VM_CG", REG_MMIO, 0x994, &mmMC_CITF_MISC_VM_CG[0], sizeof(mmMC_CITF_MISC_VM_CG)/sizeof(mmMC_CITF_MISC_VM_CG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_DEBUG", REG_MMIO, 0x998, &mmMC_VM_MD_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_DEBUG", REG_MMIO, 0x999, &mmMC_VM_MD_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB1_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_DEBUG", REG_MMIO, 0x99a, &mmMC_VM_MD_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_STATUS", REG_MMIO, 0x99b, &mmMC_VM_MD_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB0_STATUS)/sizeof(mmMC_VM_MD_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_STATUS", REG_MMIO, 0x99c, &mmMC_VM_MD_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB1_STATUS)/sizeof(mmMC_VM_MD_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_STATUS", REG_MMIO, 0x99d, &mmMC_VM_MD_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB2_STATUS)/sizeof(mmMC_VM_MD_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_154", REG_SMC, 0x9a, &ixMC_IO_DEBUG_UP_154[0], sizeof(ixMC_IO_DEBUG_UP_154)/sizeof(ixMC_IO_DEBUG_UP_154[0]), 0, 0 },
+	{ "mmMC_VM_MD_L2ARBITER_L2_CREDITS", REG_MMIO, 0x9a4, &mmMC_VM_MD_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_DEBUG", REG_MMIO, 0x9a7, &mmMC_VM_MD_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_STATUS", REG_MMIO, 0x9a8, &mmMC_VM_MD_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB3_STATUS)/sizeof(mmMC_VM_MD_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_155", REG_SMC, 0x9b, &ixMC_IO_DEBUG_UP_155[0], sizeof(ixMC_IO_DEBUG_UP_155)/sizeof(ixMC_IO_DEBUG_UP_155[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_CNTL", REG_MMIO, 0x9bf, &mmMC_ARB_AGE_CNTL[0], sizeof(mmMC_ARB_AGE_CNTL)/sizeof(mmMC_ARB_AGE_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_156", REG_SMC, 0x9c, &ixMC_IO_DEBUG_UP_156[0], sizeof(ixMC_IO_DEBUG_UP_156)/sizeof(ixMC_IO_DEBUG_UP_156[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS2", REG_MMIO, 0x9c0, &mmMC_ARB_RET_CREDITS2[0], sizeof(mmMC_ARB_RET_CREDITS2)/sizeof(mmMC_ARB_RET_CREDITS2[0]), 0, 0 },
+	{ "mmMC_ARB_FED_CNTL", REG_MMIO, 0x9c1, &mmMC_ARB_FED_CNTL[0], sizeof(mmMC_ARB_FED_CNTL)/sizeof(mmMC_ARB_FED_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_STATUS", REG_MMIO, 0x9c2, &mmMC_ARB_GECC2_STATUS[0], sizeof(mmMC_ARB_GECC2_STATUS)/sizeof(mmMC_ARB_GECC2_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_MISC", REG_MMIO, 0x9c3, &mmMC_ARB_GECC2_MISC[0], sizeof(mmMC_ARB_GECC2_MISC)/sizeof(mmMC_ARB_GECC2_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG", REG_MMIO, 0x9c4, &mmMC_ARB_GECC2_DEBUG[0], sizeof(mmMC_ARB_GECC2_DEBUG)/sizeof(mmMC_ARB_GECC2_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG2", REG_MMIO, 0x9c5, &mmMC_ARB_GECC2_DEBUG2[0], sizeof(mmMC_ARB_GECC2_DEBUG2)/sizeof(mmMC_ARB_GECC2_DEBUG2[0]), 0, 0 },
+	{ "mmMC_ARB_PERF_CID", REG_MMIO, 0x9c6, &mmMC_ARB_PERF_CID[0], sizeof(mmMC_ARB_PERF_CID)/sizeof(mmMC_ARB_PERF_CID[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2", REG_MMIO, 0x9c9, &mmMC_ARB_GECC2[0], sizeof(mmMC_ARB_GECC2)/sizeof(mmMC_ARB_GECC2[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_CLI", REG_MMIO, 0x9ca, &mmMC_ARB_GECC2_CLI[0], sizeof(mmMC_ARB_GECC2_CLI)/sizeof(mmMC_ARB_GECC2_CLI[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_SWIZ0", REG_MMIO, 0x9cb, &mmMC_ARB_ADDR_SWIZ0[0], sizeof(mmMC_ARB_ADDR_SWIZ0)/sizeof(mmMC_ARB_ADDR_SWIZ0[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_SWIZ1", REG_MMIO, 0x9cc, &mmMC_ARB_ADDR_SWIZ1[0], sizeof(mmMC_ARB_ADDR_SWIZ1)/sizeof(mmMC_ARB_ADDR_SWIZ1[0]), 0, 0 },
+	{ "mmMC_ARB_MISC3", REG_MMIO, 0x9cd, &mmMC_ARB_MISC3[0], sizeof(mmMC_ARB_MISC3)/sizeof(mmMC_ARB_MISC3[0]), 0, 0 },
+	{ "mmMC_ARB_WCDR_2", REG_MMIO, 0x9ce, &mmMC_ARB_WCDR_2[0], sizeof(mmMC_ARB_WCDR_2)/sizeof(mmMC_ARB_WCDR_2[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DATA", REG_MMIO, 0x9cf, &mmMC_ARB_RTT_DATA[0], sizeof(mmMC_ARB_RTT_DATA)/sizeof(mmMC_ARB_RTT_DATA[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_157", REG_SMC, 0x9d, &ixMC_IO_DEBUG_UP_157[0], sizeof(ixMC_IO_DEBUG_UP_157)/sizeof(ixMC_IO_DEBUG_UP_157[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL0", REG_MMIO, 0x9d0, &mmMC_ARB_RTT_CNTL0[0], sizeof(mmMC_ARB_RTT_CNTL0)/sizeof(mmMC_ARB_RTT_CNTL0[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL1", REG_MMIO, 0x9d1, &mmMC_ARB_RTT_CNTL1[0], sizeof(mmMC_ARB_RTT_CNTL1)/sizeof(mmMC_ARB_RTT_CNTL1[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL2", REG_MMIO, 0x9d2, &mmMC_ARB_RTT_CNTL2[0], sizeof(mmMC_ARB_RTT_CNTL2)/sizeof(mmMC_ARB_RTT_CNTL2[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DEBUG", REG_MMIO, 0x9d3, &mmMC_ARB_RTT_DEBUG[0], sizeof(mmMC_ARB_RTT_DEBUG)/sizeof(mmMC_ARB_RTT_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_CAC_CNTL", REG_MMIO, 0x9d4, &mmMC_ARB_CAC_CNTL[0], sizeof(mmMC_ARB_CAC_CNTL)/sizeof(mmMC_ARB_CAC_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_MISC2", REG_MMIO, 0x9d5, &mmMC_ARB_MISC2[0], sizeof(mmMC_ARB_MISC2)/sizeof(mmMC_ARB_MISC2[0]), 0, 0 },
+	{ "mmMC_ARB_MISC", REG_MMIO, 0x9d6, &mmMC_ARB_MISC[0], sizeof(mmMC_ARB_MISC)/sizeof(mmMC_ARB_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_BANKMAP", REG_MMIO, 0x9d7, &mmMC_ARB_BANKMAP[0], sizeof(mmMC_ARB_BANKMAP)/sizeof(mmMC_ARB_BANKMAP[0]), 0, 0 },
+	{ "mmMC_ARB_RAMCFG", REG_MMIO, 0x9d8, &mmMC_ARB_RAMCFG[0], sizeof(mmMC_ARB_RAMCFG)/sizeof(mmMC_ARB_RAMCFG[0]), 0, 0 },
+	{ "mmMC_ARB_POP", REG_MMIO, 0x9d9, &mmMC_ARB_POP[0], sizeof(mmMC_ARB_POP)/sizeof(mmMC_ARB_POP[0]), 0, 0 },
+	{ "mmMC_ARB_MINCLKS", REG_MMIO, 0x9da, &mmMC_ARB_MINCLKS[0], sizeof(mmMC_ARB_MINCLKS)/sizeof(mmMC_ARB_MINCLKS[0]), 0, 0 },
+	{ "mmMC_ARB_SQM_CNTL", REG_MMIO, 0x9db, &mmMC_ARB_SQM_CNTL[0], sizeof(mmMC_ARB_SQM_CNTL)/sizeof(mmMC_ARB_SQM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_HASH", REG_MMIO, 0x9dc, &mmMC_ARB_ADDR_HASH[0], sizeof(mmMC_ARB_ADDR_HASH)/sizeof(mmMC_ARB_ADDR_HASH[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING", REG_MMIO, 0x9dd, &mmMC_ARB_DRAM_TIMING[0], sizeof(mmMC_ARB_DRAM_TIMING)/sizeof(mmMC_ARB_DRAM_TIMING[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2", REG_MMIO, 0x9de, &mmMC_ARB_DRAM_TIMING2[0], sizeof(mmMC_ARB_DRAM_TIMING2)/sizeof(mmMC_ARB_DRAM_TIMING2[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_RD", REG_MMIO, 0x9df, &mmMC_ARB_WTM_CNTL_RD[0], sizeof(mmMC_ARB_WTM_CNTL_RD)/sizeof(mmMC_ARB_WTM_CNTL_RD[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_158", REG_SMC, 0x9e, &ixMC_IO_DEBUG_UP_158[0], sizeof(ixMC_IO_DEBUG_UP_158)/sizeof(ixMC_IO_DEBUG_UP_158[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_WR", REG_MMIO, 0x9e0, &mmMC_ARB_WTM_CNTL_WR[0], sizeof(mmMC_ARB_WTM_CNTL_WR)/sizeof(mmMC_ARB_WTM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_RD", REG_MMIO, 0x9e1, &mmMC_ARB_WTM_GRPWT_RD[0], sizeof(mmMC_ARB_WTM_GRPWT_RD)/sizeof(mmMC_ARB_WTM_GRPWT_RD[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_WR", REG_MMIO, 0x9e2, &mmMC_ARB_WTM_GRPWT_WR[0], sizeof(mmMC_ARB_WTM_GRPWT_WR)/sizeof(mmMC_ARB_WTM_GRPWT_WR[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_RD", REG_MMIO, 0x9e3, &mmMC_ARB_TM_CNTL_RD[0], sizeof(mmMC_ARB_TM_CNTL_RD)/sizeof(mmMC_ARB_TM_CNTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_WR", REG_MMIO, 0x9e4, &mmMC_ARB_TM_CNTL_WR[0], sizeof(mmMC_ARB_TM_CNTL_WR)/sizeof(mmMC_ARB_TM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_RD", REG_MMIO, 0x9e5, &mmMC_ARB_LAZY0_RD[0], sizeof(mmMC_ARB_LAZY0_RD)/sizeof(mmMC_ARB_LAZY0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_WR", REG_MMIO, 0x9e6, &mmMC_ARB_LAZY0_WR[0], sizeof(mmMC_ARB_LAZY0_WR)/sizeof(mmMC_ARB_LAZY0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_RD", REG_MMIO, 0x9e7, &mmMC_ARB_LAZY1_RD[0], sizeof(mmMC_ARB_LAZY1_RD)/sizeof(mmMC_ARB_LAZY1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_WR", REG_MMIO, 0x9e8, &mmMC_ARB_LAZY1_WR[0], sizeof(mmMC_ARB_LAZY1_WR)/sizeof(mmMC_ARB_LAZY1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_RD", REG_MMIO, 0x9e9, &mmMC_ARB_AGE_RD[0], sizeof(mmMC_ARB_AGE_RD)/sizeof(mmMC_ARB_AGE_RD[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_WR", REG_MMIO, 0x9ea, &mmMC_ARB_AGE_WR[0], sizeof(mmMC_ARB_AGE_WR)/sizeof(mmMC_ARB_AGE_WR[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_CNTL", REG_MMIO, 0x9eb, &mmMC_ARB_RFSH_CNTL[0], sizeof(mmMC_ARB_RFSH_CNTL)/sizeof(mmMC_ARB_RFSH_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_RATE", REG_MMIO, 0x9ec, &mmMC_ARB_RFSH_RATE[0], sizeof(mmMC_ARB_RFSH_RATE)/sizeof(mmMC_ARB_RFSH_RATE[0]), 0, 0 },
+	{ "mmMC_ARB_PM_CNTL", REG_MMIO, 0x9ed, &mmMC_ARB_PM_CNTL[0], sizeof(mmMC_ARB_PM_CNTL)/sizeof(mmMC_ARB_PM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_RD_CNTL", REG_MMIO, 0x9ee, &mmMC_ARB_GDEC_RD_CNTL[0], sizeof(mmMC_ARB_GDEC_RD_CNTL)/sizeof(mmMC_ARB_GDEC_RD_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_WR_CNTL", REG_MMIO, 0x9ef, &mmMC_ARB_GDEC_WR_CNTL[0], sizeof(mmMC_ARB_GDEC_WR_CNTL)/sizeof(mmMC_ARB_GDEC_WR_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_159", REG_SMC, 0x9f, &ixMC_IO_DEBUG_UP_159[0], sizeof(ixMC_IO_DEBUG_UP_159)/sizeof(ixMC_IO_DEBUG_UP_159[0]), 0, 0 },
+	{ "mmMC_ARB_LM_RD", REG_MMIO, 0x9f0, &mmMC_ARB_LM_RD[0], sizeof(mmMC_ARB_LM_RD)/sizeof(mmMC_ARB_LM_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LM_WR", REG_MMIO, 0x9f1, &mmMC_ARB_LM_WR[0], sizeof(mmMC_ARB_LM_WR)/sizeof(mmMC_ARB_LM_WR[0]), 0, 0 },
+	{ "mmMC_ARB_REMREQ", REG_MMIO, 0x9f2, &mmMC_ARB_REMREQ[0], sizeof(mmMC_ARB_REMREQ)/sizeof(mmMC_ARB_REMREQ[0]), 0, 0 },
+	{ "mmMC_ARB_REPLAY", REG_MMIO, 0x9f3, &mmMC_ARB_REPLAY[0], sizeof(mmMC_ARB_REPLAY)/sizeof(mmMC_ARB_REPLAY[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_RD", REG_MMIO, 0x9f4, &mmMC_ARB_RET_CREDITS_RD[0], sizeof(mmMC_ARB_RET_CREDITS_RD)/sizeof(mmMC_ARB_RET_CREDITS_RD[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_WR", REG_MMIO, 0x9f5, &mmMC_ARB_RET_CREDITS_WR[0], sizeof(mmMC_ARB_RET_CREDITS_WR)/sizeof(mmMC_ARB_RET_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_CID", REG_MMIO, 0x9f6, &mmMC_ARB_MAX_LAT_CID[0], sizeof(mmMC_ARB_MAX_LAT_CID)/sizeof(mmMC_ARB_MAX_LAT_CID[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_RSLT0", REG_MMIO, 0x9f7, &mmMC_ARB_MAX_LAT_RSLT0[0], sizeof(mmMC_ARB_MAX_LAT_RSLT0)/sizeof(mmMC_ARB_MAX_LAT_RSLT0[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_RSLT1", REG_MMIO, 0x9f8, &mmMC_ARB_MAX_LAT_RSLT1[0], sizeof(mmMC_ARB_MAX_LAT_RSLT1)/sizeof(mmMC_ARB_MAX_LAT_RSLT1[0]), 0, 0 },
+	{ "mmMC_ARB_SSM", REG_MMIO, 0x9f9, &mmMC_ARB_SSM[0], sizeof(mmMC_ARB_SSM)/sizeof(mmMC_ARB_SSM[0]), 0, 0 },
+	{ "mmMC_ARB_CG", REG_MMIO, 0x9fa, &mmMC_ARB_CG[0], sizeof(mmMC_ARB_CG)/sizeof(mmMC_ARB_CG[0]), 0, 0 },
+	{ "mmMC_ARB_WCDR", REG_MMIO, 0x9fb, &mmMC_ARB_WCDR[0], sizeof(mmMC_ARB_WCDR)/sizeof(mmMC_ARB_WCDR[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING_1", REG_MMIO, 0x9fc, &mmMC_ARB_DRAM_TIMING_1[0], sizeof(mmMC_ARB_DRAM_TIMING_1)/sizeof(mmMC_ARB_DRAM_TIMING_1[0]), 0, 0 },
+	{ "mmMC_ARB_BUSY_STATUS", REG_MMIO, 0x9fd, &mmMC_ARB_BUSY_STATUS[0], sizeof(mmMC_ARB_BUSY_STATUS)/sizeof(mmMC_ARB_BUSY_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2_1", REG_MMIO, 0x9ff, &mmMC_ARB_DRAM_TIMING2_1[0], sizeof(mmMC_ARB_DRAM_TIMING2_1)/sizeof(mmMC_ARB_DRAM_TIMING2_1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT7", REG_SMC, 0xa, &ixMC_TSM_DEBUG_BCNT7[0], sizeof(ixMC_TSM_DEBUG_BCNT7)/sizeof(ixMC_TSM_DEBUG_BCNT7[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_10", REG_SMC, 0xa, &ixMC_IO_DEBUG_UP_10[0], sizeof(ixMC_IO_DEBUG_UP_10)/sizeof(ixMC_IO_DEBUG_UP_10[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_MISC_D0", REG_SMC, 0xa0, &ixMC_IO_DEBUG_DQB0L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D0[0]), 0, 0 },
+	{ "mmMC_ARB_BURST_TIME", REG_MMIO, 0xa02, &mmMC_ARB_BURST_TIME[0], sizeof(mmMC_ARB_BURST_TIME)/sizeof(mmMC_ARB_BURST_TIME[0]), 0, 0 },
+	{ "mmMC_BIST_CNTL", REG_MMIO, 0xa05, &mmMC_BIST_CNTL[0], sizeof(mmMC_BIST_CNTL)/sizeof(mmMC_BIST_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_AUTO_CNTL", REG_MMIO, 0xa06, &mmMC_BIST_AUTO_CNTL[0], sizeof(mmMC_BIST_AUTO_CNTL)/sizeof(mmMC_BIST_AUTO_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_DIR_CNTL", REG_MMIO, 0xa07, &mmMC_BIST_DIR_CNTL[0], sizeof(mmMC_BIST_DIR_CNTL)/sizeof(mmMC_BIST_DIR_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_SADDR", REG_MMIO, 0xa08, &mmMC_BIST_SADDR[0], sizeof(mmMC_BIST_SADDR)/sizeof(mmMC_BIST_SADDR[0]), 0, 0 },
+	{ "mmMC_BIST_EADDR", REG_MMIO, 0xa09, &mmMC_BIST_EADDR[0], sizeof(mmMC_BIST_EADDR)/sizeof(mmMC_BIST_EADDR[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD0", REG_MMIO, 0xa0a, &mmMC_BIST_DATA_WORD0[0], sizeof(mmMC_BIST_DATA_WORD0)/sizeof(mmMC_BIST_DATA_WORD0[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD1", REG_MMIO, 0xa0b, &mmMC_BIST_DATA_WORD1[0], sizeof(mmMC_BIST_DATA_WORD1)/sizeof(mmMC_BIST_DATA_WORD1[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD2", REG_MMIO, 0xa0c, &mmMC_BIST_DATA_WORD2[0], sizeof(mmMC_BIST_DATA_WORD2)/sizeof(mmMC_BIST_DATA_WORD2[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD3", REG_MMIO, 0xa0d, &mmMC_BIST_DATA_WORD3[0], sizeof(mmMC_BIST_DATA_WORD3)/sizeof(mmMC_BIST_DATA_WORD3[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD4", REG_MMIO, 0xa0e, &mmMC_BIST_DATA_WORD4[0], sizeof(mmMC_BIST_DATA_WORD4)/sizeof(mmMC_BIST_DATA_WORD4[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD5", REG_MMIO, 0xa0f, &mmMC_BIST_DATA_WORD5[0], sizeof(mmMC_BIST_DATA_WORD5)/sizeof(mmMC_BIST_DATA_WORD5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_MISC_D0", REG_SMC, 0xa1, &ixMC_IO_DEBUG_DQB0H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D0[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD6", REG_MMIO, 0xa10, &mmMC_BIST_DATA_WORD6[0], sizeof(mmMC_BIST_DATA_WORD6)/sizeof(mmMC_BIST_DATA_WORD6[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD7", REG_MMIO, 0xa11, &mmMC_BIST_DATA_WORD7[0], sizeof(mmMC_BIST_DATA_WORD7)/sizeof(mmMC_BIST_DATA_WORD7[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_MASK", REG_MMIO, 0xa12, &mmMC_BIST_DATA_MASK[0], sizeof(mmMC_BIST_DATA_MASK)/sizeof(mmMC_BIST_DATA_MASK[0]), 0, 0 },
+	{ "mmMC_BIST_MISMATCH_ADDR", REG_MMIO, 0xa13, &mmMC_BIST_MISMATCH_ADDR[0], sizeof(mmMC_BIST_MISMATCH_ADDR)/sizeof(mmMC_BIST_MISMATCH_ADDR[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD0", REG_MMIO, 0xa14, &mmMC_BIST_RDATA_WORD0[0], sizeof(mmMC_BIST_RDATA_WORD0)/sizeof(mmMC_BIST_RDATA_WORD0[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD1", REG_MMIO, 0xa15, &mmMC_BIST_RDATA_WORD1[0], sizeof(mmMC_BIST_RDATA_WORD1)/sizeof(mmMC_BIST_RDATA_WORD1[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD2", REG_MMIO, 0xa16, &mmMC_BIST_RDATA_WORD2[0], sizeof(mmMC_BIST_RDATA_WORD2)/sizeof(mmMC_BIST_RDATA_WORD2[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD3", REG_MMIO, 0xa17, &mmMC_BIST_RDATA_WORD3[0], sizeof(mmMC_BIST_RDATA_WORD3)/sizeof(mmMC_BIST_RDATA_WORD3[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD4", REG_MMIO, 0xa18, &mmMC_BIST_RDATA_WORD4[0], sizeof(mmMC_BIST_RDATA_WORD4)/sizeof(mmMC_BIST_RDATA_WORD4[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD5", REG_MMIO, 0xa19, &mmMC_BIST_RDATA_WORD5[0], sizeof(mmMC_BIST_RDATA_WORD5)/sizeof(mmMC_BIST_RDATA_WORD5[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD6", REG_MMIO, 0xa1a, &mmMC_BIST_RDATA_WORD6[0], sizeof(mmMC_BIST_RDATA_WORD6)/sizeof(mmMC_BIST_RDATA_WORD6[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD7", REG_MMIO, 0xa1b, &mmMC_BIST_RDATA_WORD7[0], sizeof(mmMC_BIST_RDATA_WORD7)/sizeof(mmMC_BIST_RDATA_WORD7[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_MASK", REG_MMIO, 0xa1c, &mmMC_BIST_RDATA_MASK[0], sizeof(mmMC_BIST_RDATA_MASK)/sizeof(mmMC_BIST_RDATA_MASK[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_EDC", REG_MMIO, 0xa1d, &mmMC_BIST_RDATA_EDC[0], sizeof(mmMC_BIST_RDATA_EDC)/sizeof(mmMC_BIST_RDATA_EDC[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_0_S", REG_MMIO, 0xa1e, &mmMC_SEQ_RESERVE_0_S[0], sizeof(mmMC_SEQ_RESERVE_0_S)/sizeof(mmMC_SEQ_RESERVE_0_S[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_1_S", REG_MMIO, 0xa1f, &mmMC_SEQ_RESERVE_1_S[0], sizeof(mmMC_SEQ_RESERVE_1_S)/sizeof(mmMC_SEQ_RESERVE_1_S[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_MISC_D0", REG_SMC, 0xa2, &ixMC_IO_DEBUG_DQB1L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_STATUS_S", REG_MMIO, 0xa20, &mmMC_SEQ_STATUS_S[0], sizeof(mmMC_SEQ_STATUS_S)/sizeof(mmMC_SEQ_STATUS_S[0]), 0, 0 },
+	{ "mmMC_CG_DATAPORT", REG_MMIO, 0xa21, &mmMC_CG_DATAPORT[0], sizeof(mmMC_CG_DATAPORT)/sizeof(mmMC_CG_DATAPORT[0]), 0, 0 },
+	{ "mmMC_SEQ_MPLL_OVERRIDE", REG_MMIO, 0xa22, &mmMC_SEQ_MPLL_OVERRIDE[0], sizeof(mmMC_SEQ_MPLL_OVERRIDE)/sizeof(mmMC_SEQ_MPLL_OVERRIDE[0]), 0, 0 },
+	{ "mmMC_SEQ_CNTL", REG_MMIO, 0xa25, &mmMC_SEQ_CNTL[0], sizeof(mmMC_SEQ_CNTL)/sizeof(mmMC_SEQ_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM", REG_MMIO, 0xa26, &mmMC_SEQ_DRAM[0], sizeof(mmMC_SEQ_DRAM)/sizeof(mmMC_SEQ_DRAM[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM_2", REG_MMIO, 0xa27, &mmMC_SEQ_DRAM_2[0], sizeof(mmMC_SEQ_DRAM_2)/sizeof(mmMC_SEQ_DRAM_2[0]), 0, 0 },
+	{ "mmMC_SEQ_RAS_TIMING", REG_MMIO, 0xa28, &mmMC_SEQ_RAS_TIMING[0], sizeof(mmMC_SEQ_RAS_TIMING)/sizeof(mmMC_SEQ_RAS_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_CAS_TIMING", REG_MMIO, 0xa29, &mmMC_SEQ_CAS_TIMING[0], sizeof(mmMC_SEQ_CAS_TIMING)/sizeof(mmMC_SEQ_CAS_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING", REG_MMIO, 0xa2a, &mmMC_SEQ_MISC_TIMING[0], sizeof(mmMC_SEQ_MISC_TIMING)/sizeof(mmMC_SEQ_MISC_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING2", REG_MMIO, 0xa2b, &mmMC_SEQ_MISC_TIMING2[0], sizeof(mmMC_SEQ_MISC_TIMING2)/sizeof(mmMC_SEQ_MISC_TIMING2[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_TIMING", REG_MMIO, 0xa2c, &mmMC_SEQ_PMG_TIMING[0], sizeof(mmMC_SEQ_PMG_TIMING)/sizeof(mmMC_SEQ_PMG_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D0", REG_MMIO, 0xa2d, &mmMC_SEQ_RD_CTL_D0[0], sizeof(mmMC_SEQ_RD_CTL_D0)/sizeof(mmMC_SEQ_RD_CTL_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D1", REG_MMIO, 0xa2e, &mmMC_SEQ_RD_CTL_D1[0], sizeof(mmMC_SEQ_RD_CTL_D1)/sizeof(mmMC_SEQ_RD_CTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D0", REG_MMIO, 0xa2f, &mmMC_SEQ_WR_CTL_D0[0], sizeof(mmMC_SEQ_WR_CTL_D0)/sizeof(mmMC_SEQ_WR_CTL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_MISC_D0", REG_SMC, 0xa3, &ixMC_IO_DEBUG_DQB1H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D1", REG_MMIO, 0xa30, &mmMC_SEQ_WR_CTL_D1[0], sizeof(mmMC_SEQ_WR_CTL_D1)/sizeof(mmMC_SEQ_WR_CTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_CMD", REG_MMIO, 0xa31, &mmMC_SEQ_CMD[0], sizeof(mmMC_SEQ_CMD)/sizeof(mmMC_SEQ_CMD[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_CNTL", REG_MMIO, 0xa32, &mmMC_SEQ_SUP_CNTL[0], sizeof(mmMC_SEQ_SUP_CNTL)/sizeof(mmMC_SEQ_SUP_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_PGM", REG_MMIO, 0xa33, &mmMC_SEQ_SUP_PGM[0], sizeof(mmMC_SEQ_SUP_PGM)/sizeof(mmMC_SEQ_SUP_PGM[0]), 0, 0 },
+	{ "mmMC_PMG_AUTO_CMD", REG_MMIO, 0xa34, &mmMC_PMG_AUTO_CMD[0], sizeof(mmMC_PMG_AUTO_CMD)/sizeof(mmMC_PMG_AUTO_CMD[0]), 0, 0 },
+	{ "mmMC_PMG_AUTO_CFG", REG_MMIO, 0xa35, &mmMC_PMG_AUTO_CFG[0], sizeof(mmMC_PMG_AUTO_CFG)/sizeof(mmMC_PMG_AUTO_CFG[0]), 0, 0 },
+	{ "mmMC_IMP_CNTL", REG_MMIO, 0xa36, &mmMC_IMP_CNTL[0], sizeof(mmMC_IMP_CNTL)/sizeof(mmMC_IMP_CNTL[0]), 0, 0 },
+	{ "mmMC_IMP_DEBUG", REG_MMIO, 0xa37, &mmMC_IMP_DEBUG[0], sizeof(mmMC_IMP_DEBUG)/sizeof(mmMC_IMP_DEBUG[0]), 0, 0 },
+	{ "mmMC_IMP_STATUS", REG_MMIO, 0xa38, &mmMC_IMP_STATUS[0], sizeof(mmMC_IMP_STATUS)/sizeof(mmMC_IMP_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_WCDR_CTRL", REG_MMIO, 0xa39, &mmMC_SEQ_WCDR_CTRL[0], sizeof(mmMC_SEQ_WCDR_CTRL)/sizeof(mmMC_SEQ_WCDR_CTRL[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_CNTL", REG_MMIO, 0xa3a, &mmMC_SEQ_TRAIN_WAKEUP_CNTL[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_CNTL)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD", REG_MMIO, 0xa3b, &mmMC_SEQ_TRAIN_EDC_THRESHOLD[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_EDGE", REG_MMIO, 0xa3c, &mmMC_SEQ_TRAIN_WAKEUP_EDGE[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_EDGE)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_EDGE[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_MASK", REG_MMIO, 0xa3d, &mmMC_SEQ_TRAIN_WAKEUP_MASK[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_MASK)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_MASK[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_CAPTURE", REG_MMIO, 0xa3e, &mmMC_SEQ_TRAIN_CAPTURE[0], sizeof(mmMC_SEQ_TRAIN_CAPTURE)/sizeof(mmMC_SEQ_TRAIN_CAPTURE[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_CLEAR", REG_MMIO, 0xa3f, &mmMC_SEQ_TRAIN_WAKEUP_CLEAR[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_CLEAR)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_CLEAR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_MISC_D0", REG_SMC, 0xa4, &ixMC_IO_DEBUG_DQB2L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_TIMING", REG_MMIO, 0xa40, &mmMC_SEQ_TRAIN_TIMING[0], sizeof(mmMC_SEQ_TRAIN_TIMING)/sizeof(mmMC_SEQ_TRAIN_TIMING[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDCCDR_R_D0", REG_MMIO, 0xa41, &mmMC_TRAIN_EDCCDR_R_D0[0], sizeof(mmMC_TRAIN_EDCCDR_R_D0)/sizeof(mmMC_TRAIN_EDCCDR_R_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDCCDR_R_D1", REG_MMIO, 0xa42, &mmMC_TRAIN_EDCCDR_R_D1[0], sizeof(mmMC_TRAIN_EDCCDR_R_D1)/sizeof(mmMC_TRAIN_EDCCDR_R_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_0_D0", REG_MMIO, 0xa43, &mmMC_TRAIN_PRBSERR_0_D0[0], sizeof(mmMC_TRAIN_PRBSERR_0_D0)/sizeof(mmMC_TRAIN_PRBSERR_0_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_1_D0", REG_MMIO, 0xa44, &mmMC_TRAIN_PRBSERR_1_D0[0], sizeof(mmMC_TRAIN_PRBSERR_1_D0)/sizeof(mmMC_TRAIN_PRBSERR_1_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDC_STATUS_D0", REG_MMIO, 0xa45, &mmMC_TRAIN_EDC_STATUS_D0[0], sizeof(mmMC_TRAIN_EDC_STATUS_D0)/sizeof(mmMC_TRAIN_EDC_STATUS_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_0_D1", REG_MMIO, 0xa46, &mmMC_TRAIN_PRBSERR_0_D1[0], sizeof(mmMC_TRAIN_PRBSERR_0_D1)/sizeof(mmMC_TRAIN_PRBSERR_0_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_1_D1", REG_MMIO, 0xa47, &mmMC_TRAIN_PRBSERR_1_D1[0], sizeof(mmMC_TRAIN_PRBSERR_1_D1)/sizeof(mmMC_TRAIN_PRBSERR_1_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDC_STATUS_D1", REG_MMIO, 0xa48, &mmMC_TRAIN_EDC_STATUS_D1[0], sizeof(mmMC_TRAIN_EDC_STATUS_D1)/sizeof(mmMC_TRAIN_EDC_STATUS_D1[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY0_D0", REG_MMIO, 0xa49, &mmMC_IO_TXCNTL_DPHY0_D0[0], sizeof(mmMC_IO_TXCNTL_DPHY0_D0)/sizeof(mmMC_IO_TXCNTL_DPHY0_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY1_D0", REG_MMIO, 0xa4a, &mmMC_IO_TXCNTL_DPHY1_D0[0], sizeof(mmMC_IO_TXCNTL_DPHY1_D0)/sizeof(mmMC_IO_TXCNTL_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_APHY_D0", REG_MMIO, 0xa4b, &mmMC_IO_TXCNTL_APHY_D0[0], sizeof(mmMC_IO_TXCNTL_APHY_D0)/sizeof(mmMC_IO_TXCNTL_APHY_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY0_D0", REG_MMIO, 0xa4c, &mmMC_IO_RXCNTL_DPHY0_D0[0], sizeof(mmMC_IO_RXCNTL_DPHY0_D0)/sizeof(mmMC_IO_RXCNTL_DPHY0_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY1_D0", REG_MMIO, 0xa4d, &mmMC_IO_RXCNTL_DPHY1_D0[0], sizeof(mmMC_IO_RXCNTL_DPHY1_D0)/sizeof(mmMC_IO_RXCNTL_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_DPHY_STR_CNTL_D0", REG_MMIO, 0xa4e, &mmMC_IO_DPHY_STR_CNTL_D0[0], sizeof(mmMC_IO_DPHY_STR_CNTL_D0)/sizeof(mmMC_IO_DPHY_STR_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY0_D1", REG_MMIO, 0xa4f, &mmMC_IO_TXCNTL_DPHY0_D1[0], sizeof(mmMC_IO_TXCNTL_DPHY0_D1)/sizeof(mmMC_IO_TXCNTL_DPHY0_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_MISC_D0", REG_SMC, 0xa5, &ixMC_IO_DEBUG_DQB2H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY1_D1", REG_MMIO, 0xa50, &mmMC_IO_TXCNTL_DPHY1_D1[0], sizeof(mmMC_IO_TXCNTL_DPHY1_D1)/sizeof(mmMC_IO_TXCNTL_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_APHY_D1", REG_MMIO, 0xa51, &mmMC_IO_TXCNTL_APHY_D1[0], sizeof(mmMC_IO_TXCNTL_APHY_D1)/sizeof(mmMC_IO_TXCNTL_APHY_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY0_D1", REG_MMIO, 0xa52, &mmMC_IO_RXCNTL_DPHY0_D1[0], sizeof(mmMC_IO_RXCNTL_DPHY0_D1)/sizeof(mmMC_IO_RXCNTL_DPHY0_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY1_D1", REG_MMIO, 0xa53, &mmMC_IO_RXCNTL_DPHY1_D1[0], sizeof(mmMC_IO_RXCNTL_DPHY1_D1)/sizeof(mmMC_IO_RXCNTL_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_IO_DPHY_STR_CNTL_D1", REG_MMIO, 0xa54, &mmMC_IO_DPHY_STR_CNTL_D1[0], sizeof(mmMC_IO_DPHY_STR_CNTL_D1)/sizeof(mmMC_IO_DPHY_STR_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL_D0", REG_MMIO, 0xa55, &mmMC_IO_CDRCNTL_D0[0], sizeof(mmMC_IO_CDRCNTL_D0)/sizeof(mmMC_IO_CDRCNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL_D1", REG_MMIO, 0xa56, &mmMC_IO_CDRCNTL_D1[0], sizeof(mmMC_IO_CDRCNTL_D1)/sizeof(mmMC_IO_CDRCNTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_FIFO_CTL", REG_MMIO, 0xa57, &mmMC_SEQ_FIFO_CTL[0], sizeof(mmMC_SEQ_FIFO_CTL)/sizeof(mmMC_SEQ_FIFO_CTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE0_D0", REG_MMIO, 0xa58, &mmMC_SEQ_TXFRAMING_BYTE0_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE1_D0", REG_MMIO, 0xa59, &mmMC_SEQ_TXFRAMING_BYTE1_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE2_D0", REG_MMIO, 0xa5a, &mmMC_SEQ_TXFRAMING_BYTE2_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE3_D0", REG_MMIO, 0xa5b, &mmMC_SEQ_TXFRAMING_BYTE3_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_DBI_D0", REG_MMIO, 0xa5c, &mmMC_SEQ_TXFRAMING_DBI_D0[0], sizeof(mmMC_SEQ_TXFRAMING_DBI_D0)/sizeof(mmMC_SEQ_TXFRAMING_DBI_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_EDC_D0", REG_MMIO, 0xa5d, &mmMC_SEQ_TXFRAMING_EDC_D0[0], sizeof(mmMC_SEQ_TXFRAMING_EDC_D0)/sizeof(mmMC_SEQ_TXFRAMING_EDC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_FCK_D0", REG_MMIO, 0xa5e, &mmMC_SEQ_TXFRAMING_FCK_D0[0], sizeof(mmMC_SEQ_TXFRAMING_FCK_D0)/sizeof(mmMC_SEQ_TXFRAMING_FCK_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC8", REG_MMIO, 0xa5f, &mmMC_SEQ_MISC8[0], sizeof(mmMC_SEQ_MISC8)/sizeof(mmMC_SEQ_MISC8[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_MISC_D0", REG_SMC, 0xa6, &ixMC_IO_DEBUG_DQB3L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE0_D1", REG_MMIO, 0xa60, &mmMC_SEQ_TXFRAMING_BYTE0_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE1_D1", REG_MMIO, 0xa61, &mmMC_SEQ_TXFRAMING_BYTE1_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE2_D1", REG_MMIO, 0xa62, &mmMC_SEQ_TXFRAMING_BYTE2_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE3_D1", REG_MMIO, 0xa63, &mmMC_SEQ_TXFRAMING_BYTE3_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_DBI_D1", REG_MMIO, 0xa64, &mmMC_SEQ_TXFRAMING_DBI_D1[0], sizeof(mmMC_SEQ_TXFRAMING_DBI_D1)/sizeof(mmMC_SEQ_TXFRAMING_DBI_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_EDC_D1", REG_MMIO, 0xa65, &mmMC_SEQ_TXFRAMING_EDC_D1[0], sizeof(mmMC_SEQ_TXFRAMING_EDC_D1)/sizeof(mmMC_SEQ_TXFRAMING_EDC_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_FCK_D1", REG_MMIO, 0xa66, &mmMC_SEQ_TXFRAMING_FCK_D1[0], sizeof(mmMC_SEQ_TXFRAMING_FCK_D1)/sizeof(mmMC_SEQ_TXFRAMING_FCK_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE0_D0", REG_MMIO, 0xa67, &mmMC_SEQ_RXFRAMING_BYTE0_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE1_D0", REG_MMIO, 0xa68, &mmMC_SEQ_RXFRAMING_BYTE1_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE2_D0", REG_MMIO, 0xa69, &mmMC_SEQ_RXFRAMING_BYTE2_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE3_D0", REG_MMIO, 0xa6a, &mmMC_SEQ_RXFRAMING_BYTE3_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_DBI_D0", REG_MMIO, 0xa6b, &mmMC_SEQ_RXFRAMING_DBI_D0[0], sizeof(mmMC_SEQ_RXFRAMING_DBI_D0)/sizeof(mmMC_SEQ_RXFRAMING_DBI_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_EDC_D0", REG_MMIO, 0xa6c, &mmMC_SEQ_RXFRAMING_EDC_D0[0], sizeof(mmMC_SEQ_RXFRAMING_EDC_D0)/sizeof(mmMC_SEQ_RXFRAMING_EDC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE0_D1", REG_MMIO, 0xa6d, &mmMC_SEQ_RXFRAMING_BYTE0_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE1_D1", REG_MMIO, 0xa6e, &mmMC_SEQ_RXFRAMING_BYTE1_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE2_D1", REG_MMIO, 0xa6f, &mmMC_SEQ_RXFRAMING_BYTE2_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_MISC_D0", REG_SMC, 0xa7, &ixMC_IO_DEBUG_DQB3H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE3_D1", REG_MMIO, 0xa70, &mmMC_SEQ_RXFRAMING_BYTE3_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_DBI_D1", REG_MMIO, 0xa71, &mmMC_SEQ_RXFRAMING_DBI_D1[0], sizeof(mmMC_SEQ_RXFRAMING_DBI_D1)/sizeof(mmMC_SEQ_RXFRAMING_DBI_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_EDC_D1", REG_MMIO, 0xa72, &mmMC_SEQ_RXFRAMING_EDC_D1[0], sizeof(mmMC_SEQ_RXFRAMING_EDC_D1)/sizeof(mmMC_SEQ_RXFRAMING_EDC_D1[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL", REG_MMIO, 0xa73, &mmMC_IO_PAD_CNTL[0], sizeof(mmMC_IO_PAD_CNTL)/sizeof(mmMC_IO_PAD_CNTL[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL_D0", REG_MMIO, 0xa74, &mmMC_IO_PAD_CNTL_D0[0], sizeof(mmMC_IO_PAD_CNTL_D0)/sizeof(mmMC_IO_PAD_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL_D1", REG_MMIO, 0xa75, &mmMC_IO_PAD_CNTL_D1[0], sizeof(mmMC_IO_PAD_CNTL_D1)/sizeof(mmMC_IO_PAD_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_NPL_STATUS", REG_MMIO, 0xa76, &mmMC_NPL_STATUS[0], sizeof(mmMC_NPL_STATUS)/sizeof(mmMC_NPL_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_CNTL", REG_MMIO, 0xa77, &mmMC_SEQ_PERF_CNTL[0], sizeof(mmMC_SEQ_PERF_CNTL)/sizeof(mmMC_SEQ_PERF_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CTL", REG_MMIO, 0xa78, &mmMC_SEQ_PERF_SEQ_CTL[0], sizeof(mmMC_SEQ_PERF_SEQ_CTL)/sizeof(mmMC_SEQ_PERF_SEQ_CTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_A_I0", REG_MMIO, 0xa79, &mmMC_SEQ_PERF_SEQ_CNT_A_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_A_I1", REG_MMIO, 0xa7a, &mmMC_SEQ_PERF_SEQ_CNT_A_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_B_I0", REG_MMIO, 0xa7b, &mmMC_SEQ_PERF_SEQ_CNT_B_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_B_I1", REG_MMIO, 0xa7c, &mmMC_SEQ_PERF_SEQ_CNT_B_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_STATUS_M", REG_MMIO, 0xa7d, &mmMC_SEQ_STATUS_M[0], sizeof(mmMC_SEQ_STATUS_M)/sizeof(mmMC_SEQ_STATUS_M[0]), 0, 0 },
+	{ "mmMC_SEQ_VENDOR_ID_I0", REG_MMIO, 0xa7e, &mmMC_SEQ_VENDOR_ID_I0[0], sizeof(mmMC_SEQ_VENDOR_ID_I0)/sizeof(mmMC_SEQ_VENDOR_ID_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_VENDOR_ID_I1", REG_MMIO, 0xa7f, &mmMC_SEQ_VENDOR_ID_I1[0], sizeof(mmMC_SEQ_VENDOR_ID_I1)/sizeof(mmMC_SEQ_VENDOR_ID_I1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_MISC_D0", REG_SMC, 0xa8, &ixMC_IO_DEBUG_DBI_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DBI_MISC_D0)/sizeof(ixMC_IO_DEBUG_DBI_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC0", REG_MMIO, 0xa80, &mmMC_SEQ_MISC0[0], sizeof(mmMC_SEQ_MISC0)/sizeof(mmMC_SEQ_MISC0[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC1", REG_MMIO, 0xa81, &mmMC_SEQ_MISC1[0], sizeof(mmMC_SEQ_MISC1)/sizeof(mmMC_SEQ_MISC1[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_M", REG_MMIO, 0xa82, &mmMC_SEQ_RESERVE_M[0], sizeof(mmMC_SEQ_RESERVE_M)/sizeof(mmMC_SEQ_RESERVE_M[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_EMRS", REG_MMIO, 0xa83, &mmMC_PMG_CMD_EMRS[0], sizeof(mmMC_PMG_CMD_EMRS)/sizeof(mmMC_PMG_CMD_EMRS[0]), 0, 0 },
+	{ "mmMC_PMG_CFG", REG_MMIO, 0xa84, &mmMC_PMG_CFG[0], sizeof(mmMC_PMG_CFG)/sizeof(mmMC_PMG_CFG[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP2_STAT", REG_MMIO, 0xa85, &mmMC_SEQ_SUP_GP2_STAT[0], sizeof(mmMC_SEQ_SUP_GP2_STAT)/sizeof(mmMC_SEQ_SUP_GP2_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP3_STAT", REG_MMIO, 0xa86, &mmMC_SEQ_SUP_GP3_STAT[0], sizeof(mmMC_SEQ_SUP_GP3_STAT)/sizeof(mmMC_SEQ_SUP_GP3_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_IR_STAT", REG_MMIO, 0xa87, &mmMC_SEQ_SUP_IR_STAT[0], sizeof(mmMC_SEQ_SUP_IR_STAT)/sizeof(mmMC_SEQ_SUP_IR_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_DEC_STAT", REG_MMIO, 0xa88, &mmMC_SEQ_SUP_DEC_STAT[0], sizeof(mmMC_SEQ_SUP_DEC_STAT)/sizeof(mmMC_SEQ_SUP_DEC_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_PGM_STAT", REG_MMIO, 0xa89, &mmMC_SEQ_SUP_PGM_STAT[0], sizeof(mmMC_SEQ_SUP_PGM_STAT)/sizeof(mmMC_SEQ_SUP_PGM_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_R_PGM", REG_MMIO, 0xa8a, &mmMC_SEQ_SUP_R_PGM[0], sizeof(mmMC_SEQ_SUP_R_PGM)/sizeof(mmMC_SEQ_SUP_R_PGM[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC3", REG_MMIO, 0xa8b, &mmMC_SEQ_MISC3[0], sizeof(mmMC_SEQ_MISC3)/sizeof(mmMC_SEQ_MISC3[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC4", REG_MMIO, 0xa8c, &mmMC_SEQ_MISC4[0], sizeof(mmMC_SEQ_MISC4)/sizeof(mmMC_SEQ_MISC4[0]), 0, 0 },
+	{ "mmMC_BIST_CMP_CNTL", REG_MMIO, 0xa8d, &mmMC_BIST_CMP_CNTL[0], sizeof(mmMC_BIST_CMP_CNTL)/sizeof(mmMC_BIST_CMP_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_CMD_CNTL", REG_MMIO, 0xa8e, &mmMC_BIST_CMD_CNTL[0], sizeof(mmMC_BIST_CMD_CNTL)/sizeof(mmMC_BIST_CMD_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP0_STAT", REG_MMIO, 0xa8f, &mmMC_SEQ_SUP_GP0_STAT[0], sizeof(mmMC_SEQ_SUP_GP0_STAT)/sizeof(mmMC_SEQ_SUP_GP0_STAT[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_MISC_D0", REG_SMC, 0xa9, &ixMC_IO_DEBUG_EDC_MISC_D0[0], sizeof(ixMC_IO_DEBUG_EDC_MISC_D0)/sizeof(ixMC_IO_DEBUG_EDC_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP1_STAT", REG_MMIO, 0xa90, &mmMC_SEQ_SUP_GP1_STAT[0], sizeof(mmMC_SEQ_SUP_GP1_STAT)/sizeof(mmMC_SEQ_SUP_GP1_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_DEBUG_INDEX", REG_MMIO, 0xa91, &mmMC_SEQ_IO_DEBUG_INDEX[0], sizeof(mmMC_SEQ_IO_DEBUG_INDEX)/sizeof(mmMC_SEQ_IO_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_DEBUG_DATA", REG_MMIO, 0xa92, &mmMC_SEQ_IO_DEBUG_DATA[0], sizeof(mmMC_SEQ_IO_DEBUG_DATA)/sizeof(mmMC_SEQ_IO_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMC_SEQ_BYTE_REMAP_D0", REG_MMIO, 0xa93, &mmMC_SEQ_BYTE_REMAP_D0[0], sizeof(mmMC_SEQ_BYTE_REMAP_D0)/sizeof(mmMC_SEQ_BYTE_REMAP_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BYTE_REMAP_D1", REG_MMIO, 0xa94, &mmMC_SEQ_BYTE_REMAP_D1[0], sizeof(mmMC_SEQ_BYTE_REMAP_D1)/sizeof(mmMC_SEQ_BYTE_REMAP_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC5", REG_MMIO, 0xa95, &mmMC_SEQ_MISC5[0], sizeof(mmMC_SEQ_MISC5)/sizeof(mmMC_SEQ_MISC5[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC6", REG_MMIO, 0xa96, &mmMC_SEQ_MISC6[0], sizeof(mmMC_SEQ_MISC6)/sizeof(mmMC_SEQ_MISC6[0]), 0, 0 },
+	{ "mmMC_IO_APHY_STR_CNTL_D0", REG_MMIO, 0xa97, &mmMC_IO_APHY_STR_CNTL_D0[0], sizeof(mmMC_IO_APHY_STR_CNTL_D0)/sizeof(mmMC_IO_APHY_STR_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_APHY_STR_CNTL_D1", REG_MMIO, 0xa98, &mmMC_IO_APHY_STR_CNTL_D1[0], sizeof(mmMC_IO_APHY_STR_CNTL_D1)/sizeof(mmMC_IO_APHY_STR_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC7", REG_MMIO, 0xa99, &mmMC_SEQ_MISC7[0], sizeof(mmMC_SEQ_MISC7)/sizeof(mmMC_SEQ_MISC7[0]), 0, 0 },
+	{ "mmMC_SEQ_CG", REG_MMIO, 0xa9a, &mmMC_SEQ_CG[0], sizeof(mmMC_SEQ_CG)/sizeof(mmMC_SEQ_CG[0]), 0, 0 },
+	{ "mmMC_SEQ_RAS_TIMING_LP", REG_MMIO, 0xa9b, &mmMC_SEQ_RAS_TIMING_LP[0], sizeof(mmMC_SEQ_RAS_TIMING_LP)/sizeof(mmMC_SEQ_RAS_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_CAS_TIMING_LP", REG_MMIO, 0xa9c, &mmMC_SEQ_CAS_TIMING_LP[0], sizeof(mmMC_SEQ_CAS_TIMING_LP)/sizeof(mmMC_SEQ_CAS_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING_LP", REG_MMIO, 0xa9d, &mmMC_SEQ_MISC_TIMING_LP[0], sizeof(mmMC_SEQ_MISC_TIMING_LP)/sizeof(mmMC_SEQ_MISC_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING2_LP", REG_MMIO, 0xa9e, &mmMC_SEQ_MISC_TIMING2_LP[0], sizeof(mmMC_SEQ_MISC_TIMING2_LP)/sizeof(mmMC_SEQ_MISC_TIMING2_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D0_LP", REG_MMIO, 0xa9f, &mmMC_SEQ_WR_CTL_D0_LP[0], sizeof(mmMC_SEQ_WR_CTL_D0_LP)/sizeof(mmMC_SEQ_WR_CTL_D0_LP[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_MISC_D0", REG_SMC, 0xaa, &ixMC_IO_DEBUG_WCK_MISC_D0[0], sizeof(ixMC_IO_DEBUG_WCK_MISC_D0)/sizeof(ixMC_IO_DEBUG_WCK_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D1_LP", REG_MMIO, 0xaa0, &mmMC_SEQ_WR_CTL_D1_LP[0], sizeof(mmMC_SEQ_WR_CTL_D1_LP)/sizeof(mmMC_SEQ_WR_CTL_D1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_EMRS_LP", REG_MMIO, 0xaa1, &mmMC_SEQ_PMG_CMD_EMRS_LP[0], sizeof(mmMC_SEQ_PMG_CMD_EMRS_LP)/sizeof(mmMC_SEQ_PMG_CMD_EMRS_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS_LP", REG_MMIO, 0xaa2, &mmMC_SEQ_PMG_CMD_MRS_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B0_D0", REG_MMIO, 0xaa3, &mmMC_SEQ_BIT_REMAP_B0_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B0_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B1_D0", REG_MMIO, 0xaa4, &mmMC_SEQ_BIT_REMAP_B1_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B1_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B2_D0", REG_MMIO, 0xaa5, &mmMC_SEQ_BIT_REMAP_B2_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B2_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B3_D0", REG_MMIO, 0xaa6, &mmMC_SEQ_BIT_REMAP_B3_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B3_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B0_D1", REG_MMIO, 0xaa7, &mmMC_SEQ_BIT_REMAP_B0_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B0_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B1_D1", REG_MMIO, 0xaa8, &mmMC_SEQ_BIT_REMAP_B1_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B1_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B2_D1", REG_MMIO, 0xaa9, &mmMC_SEQ_BIT_REMAP_B2_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B2_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B3_D1", REG_MMIO, 0xaaa, &mmMC_SEQ_BIT_REMAP_B3_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B3_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B3_D1[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS", REG_MMIO, 0xaab, &mmMC_PMG_CMD_MRS[0], sizeof(mmMC_PMG_CMD_MRS)/sizeof(mmMC_PMG_CMD_MRS[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD0", REG_MMIO, 0xaac, &mmMC_SEQ_IO_RWORD0[0], sizeof(mmMC_SEQ_IO_RWORD0)/sizeof(mmMC_SEQ_IO_RWORD0[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD1", REG_MMIO, 0xaad, &mmMC_SEQ_IO_RWORD1[0], sizeof(mmMC_SEQ_IO_RWORD1)/sizeof(mmMC_SEQ_IO_RWORD1[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD2", REG_MMIO, 0xaae, &mmMC_SEQ_IO_RWORD2[0], sizeof(mmMC_SEQ_IO_RWORD2)/sizeof(mmMC_SEQ_IO_RWORD2[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD3", REG_MMIO, 0xaaf, &mmMC_SEQ_IO_RWORD3[0], sizeof(mmMC_SEQ_IO_RWORD3)/sizeof(mmMC_SEQ_IO_RWORD3[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_MISC_D0", REG_SMC, 0xab, &ixMC_IO_DEBUG_CK_MISC_D0[0], sizeof(ixMC_IO_DEBUG_CK_MISC_D0)/sizeof(ixMC_IO_DEBUG_CK_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD4", REG_MMIO, 0xab0, &mmMC_SEQ_IO_RWORD4[0], sizeof(mmMC_SEQ_IO_RWORD4)/sizeof(mmMC_SEQ_IO_RWORD4[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD5", REG_MMIO, 0xab1, &mmMC_SEQ_IO_RWORD5[0], sizeof(mmMC_SEQ_IO_RWORD5)/sizeof(mmMC_SEQ_IO_RWORD5[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD6", REG_MMIO, 0xab2, &mmMC_SEQ_IO_RWORD6[0], sizeof(mmMC_SEQ_IO_RWORD6)/sizeof(mmMC_SEQ_IO_RWORD6[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD7", REG_MMIO, 0xab3, &mmMC_SEQ_IO_RWORD7[0], sizeof(mmMC_SEQ_IO_RWORD7)/sizeof(mmMC_SEQ_IO_RWORD7[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RDBI", REG_MMIO, 0xab4, &mmMC_SEQ_IO_RDBI[0], sizeof(mmMC_SEQ_IO_RDBI)/sizeof(mmMC_SEQ_IO_RDBI[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_REDC", REG_MMIO, 0xab5, &mmMC_SEQ_IO_REDC[0], sizeof(mmMC_SEQ_IO_REDC)/sizeof(mmMC_SEQ_IO_REDC[0]), 0, 0 },
+	{ "mmMC_BIST_CMP_CNTL_2", REG_MMIO, 0xab6, &mmMC_BIST_CMP_CNTL_2[0], sizeof(mmMC_BIST_CMP_CNTL_2)/sizeof(mmMC_BIST_CMP_CNTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RESERVE_D0", REG_MMIO, 0xab7, &mmMC_SEQ_IO_RESERVE_D0[0], sizeof(mmMC_SEQ_IO_RESERVE_D0)/sizeof(mmMC_SEQ_IO_RESERVE_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RESERVE_D1", REG_MMIO, 0xab8, &mmMC_SEQ_IO_RESERVE_D1[0], sizeof(mmMC_SEQ_IO_RESERVE_D1)/sizeof(mmMC_SEQ_IO_RESERVE_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_HWCNTL", REG_MMIO, 0xab9, &mmMC_SEQ_PMG_PG_HWCNTL[0], sizeof(mmMC_SEQ_PMG_PG_HWCNTL)/sizeof(mmMC_SEQ_PMG_PG_HWCNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_SWCNTL_0", REG_MMIO, 0xaba, &mmMC_SEQ_PMG_PG_SWCNTL_0[0], sizeof(mmMC_SEQ_PMG_PG_SWCNTL_0)/sizeof(mmMC_SEQ_PMG_PG_SWCNTL_0[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_SWCNTL_1", REG_MMIO, 0xabb, &mmMC_SEQ_PMG_PG_SWCNTL_1[0], sizeof(mmMC_SEQ_PMG_PG_SWCNTL_1)/sizeof(mmMC_SEQ_PMG_PG_SWCNTL_1[0]), 0, 0 },
+	{ "mmMC_IMP_DQ_STATUS", REG_MMIO, 0xabc, &mmMC_IMP_DQ_STATUS[0], sizeof(mmMC_IMP_DQ_STATUS)/sizeof(mmMC_IMP_DQ_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_TCG_CNTL", REG_MMIO, 0xabd, &mmMC_SEQ_TCG_CNTL[0], sizeof(mmMC_SEQ_TCG_CNTL)/sizeof(mmMC_SEQ_TCG_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_CTRL", REG_MMIO, 0xabe, &mmMC_SEQ_TSM_CTRL[0], sizeof(mmMC_SEQ_TSM_CTRL)/sizeof(mmMC_SEQ_TSM_CTRL[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_GCNT", REG_MMIO, 0xabf, &mmMC_SEQ_TSM_GCNT[0], sizeof(mmMC_SEQ_TSM_GCNT)/sizeof(mmMC_SEQ_TSM_GCNT[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_MISC_D0", REG_SMC, 0xac, &ixMC_IO_DEBUG_ADDRL_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_OCNT", REG_MMIO, 0xac0, &mmMC_SEQ_TSM_OCNT[0], sizeof(mmMC_SEQ_TSM_OCNT)/sizeof(mmMC_SEQ_TSM_OCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_NCNT", REG_MMIO, 0xac1, &mmMC_SEQ_TSM_NCNT[0], sizeof(mmMC_SEQ_TSM_NCNT)/sizeof(mmMC_SEQ_TSM_NCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_BCNT", REG_MMIO, 0xac2, &mmMC_SEQ_TSM_BCNT[0], sizeof(mmMC_SEQ_TSM_BCNT)/sizeof(mmMC_SEQ_TSM_BCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_FLAG", REG_MMIO, 0xac3, &mmMC_SEQ_TSM_FLAG[0], sizeof(mmMC_SEQ_TSM_FLAG)/sizeof(mmMC_SEQ_TSM_FLAG[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_UPDATE", REG_MMIO, 0xac4, &mmMC_SEQ_TSM_UPDATE[0], sizeof(mmMC_SEQ_TSM_UPDATE)/sizeof(mmMC_SEQ_TSM_UPDATE[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_EDC", REG_MMIO, 0xac5, &mmMC_SEQ_TSM_EDC[0], sizeof(mmMC_SEQ_TSM_EDC)/sizeof(mmMC_SEQ_TSM_EDC[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DBI", REG_MMIO, 0xac6, &mmMC_SEQ_TSM_DBI[0], sizeof(mmMC_SEQ_TSM_DBI)/sizeof(mmMC_SEQ_TSM_DBI[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D0_LP", REG_MMIO, 0xac7, &mmMC_SEQ_RD_CTL_D0_LP[0], sizeof(mmMC_SEQ_RD_CTL_D0_LP)/sizeof(mmMC_SEQ_RD_CTL_D0_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D1_LP", REG_MMIO, 0xac8, &mmMC_SEQ_RD_CTL_D1_LP[0], sizeof(mmMC_SEQ_RD_CTL_D1_LP)/sizeof(mmMC_SEQ_RD_CTL_D1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_TIMER_WR", REG_MMIO, 0xac9, &mmMC_SEQ_TIMER_WR[0], sizeof(mmMC_SEQ_TIMER_WR)/sizeof(mmMC_SEQ_TIMER_WR[0]), 0, 0 },
+	{ "mmMC_SEQ_TIMER_RD", REG_MMIO, 0xaca, &mmMC_SEQ_TIMER_RD[0], sizeof(mmMC_SEQ_TIMER_RD)/sizeof(mmMC_SEQ_TIMER_RD[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM_ERROR_INSERTION", REG_MMIO, 0xacb, &mmMC_SEQ_DRAM_ERROR_INSERTION[0], sizeof(mmMC_SEQ_DRAM_ERROR_INSERTION)/sizeof(mmMC_SEQ_DRAM_ERROR_INSERTION[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_D0", REG_MMIO, 0xacc, &mmMC_PHY_TIMING_D0[0], sizeof(mmMC_PHY_TIMING_D0)/sizeof(mmMC_PHY_TIMING_D0[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_D1", REG_MMIO, 0xacd, &mmMC_PHY_TIMING_D1[0], sizeof(mmMC_PHY_TIMING_D1)/sizeof(mmMC_PHY_TIMING_D1[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_2", REG_MMIO, 0xace, &mmMC_PHY_TIMING_2[0], sizeof(mmMC_PHY_TIMING_2)/sizeof(mmMC_PHY_TIMING_2[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DEBUG_INDEX", REG_MMIO, 0xacf, &mmMC_SEQ_TSM_DEBUG_INDEX[0], sizeof(mmMC_SEQ_TSM_DEBUG_INDEX)/sizeof(mmMC_SEQ_TSM_DEBUG_INDEX[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_MISC_D0", REG_SMC, 0xad, &ixMC_IO_DEBUG_ADDRH_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DEBUG_DATA", REG_MMIO, 0xad0, &mmMC_SEQ_TSM_DEBUG_DATA[0], sizeof(mmMC_SEQ_TSM_DEBUG_DATA)/sizeof(mmMC_SEQ_TSM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS1", REG_MMIO, 0xad1, &mmMC_PMG_CMD_MRS1[0], sizeof(mmMC_PMG_CMD_MRS1)/sizeof(mmMC_PMG_CMD_MRS1[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS1_LP", REG_MMIO, 0xad2, &mmMC_SEQ_PMG_CMD_MRS1_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS1_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_TIMING_LP", REG_MMIO, 0xad3, &mmMC_SEQ_PMG_TIMING_LP[0], sizeof(mmMC_SEQ_PMG_TIMING_LP)/sizeof(mmMC_SEQ_PMG_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_CNTL_2", REG_MMIO, 0xad4, &mmMC_SEQ_CNTL_2[0], sizeof(mmMC_SEQ_CNTL_2)/sizeof(mmMC_SEQ_CNTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_2", REG_MMIO, 0xad5, &mmMC_SEQ_WR_CTL_2[0], sizeof(mmMC_SEQ_WR_CTL_2)/sizeof(mmMC_SEQ_WR_CTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_2_LP", REG_MMIO, 0xad6, &mmMC_SEQ_WR_CTL_2_LP[0], sizeof(mmMC_SEQ_WR_CTL_2_LP)/sizeof(mmMC_SEQ_WR_CTL_2_LP[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS2", REG_MMIO, 0xad7, &mmMC_PMG_CMD_MRS2[0], sizeof(mmMC_PMG_CMD_MRS2)/sizeof(mmMC_PMG_CMD_MRS2[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS2_LP", REG_MMIO, 0xad8, &mmMC_SEQ_PMG_CMD_MRS2_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS2_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS2_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_C_I0", REG_MMIO, 0xad9, &mmMC_SEQ_PERF_SEQ_CNT_C_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_C_I1", REG_MMIO, 0xada, &mmMC_SEQ_PERF_SEQ_CNT_C_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_D_I0", REG_MMIO, 0xadb, &mmMC_SEQ_PERF_SEQ_CNT_D_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_D_I1", REG_MMIO, 0xadc, &mmMC_SEQ_PERF_SEQ_CNT_D_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I1[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL1_D0", REG_MMIO, 0xadd, &mmMC_IO_CDRCNTL1_D0[0], sizeof(mmMC_IO_CDRCNTL1_D0)/sizeof(mmMC_IO_CDRCNTL1_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL1_D1", REG_MMIO, 0xade, &mmMC_IO_CDRCNTL1_D1[0], sizeof(mmMC_IO_CDRCNTL1_D1)/sizeof(mmMC_IO_CDRCNTL1_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY0_D0", REG_MMIO, 0xadf, &mmMC_IO_RXCNTL1_DPHY0_D0[0], sizeof(mmMC_IO_RXCNTL1_DPHY0_D0)/sizeof(mmMC_IO_RXCNTL1_DPHY0_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_MISC_D0", REG_SMC, 0xae, &ixMC_IO_DEBUG_ACMD_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_MISC_D0)/sizeof(ixMC_IO_DEBUG_ACMD_MISC_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY1_D0", REG_MMIO, 0xae0, &mmMC_IO_RXCNTL1_DPHY1_D0[0], sizeof(mmMC_IO_RXCNTL1_DPHY1_D0)/sizeof(mmMC_IO_RXCNTL1_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY0_D1", REG_MMIO, 0xae1, &mmMC_IO_RXCNTL1_DPHY0_D1[0], sizeof(mmMC_IO_RXCNTL1_DPHY0_D1)/sizeof(mmMC_IO_RXCNTL1_DPHY0_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY1_D1", REG_MMIO, 0xae2, &mmMC_IO_RXCNTL1_DPHY1_D1[0], sizeof(mmMC_IO_RXCNTL1_DPHY1_D1)/sizeof(mmMC_IO_RXCNTL1_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_WCDR", REG_MMIO, 0xae3, &mmMC_SEQ_TSM_WCDR[0], sizeof(mmMC_SEQ_TSM_WCDR)/sizeof(mmMC_SEQ_TSM_WCDR[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL2_D0", REG_MMIO, 0xae4, &mmMC_IO_CDRCNTL2_D0[0], sizeof(mmMC_IO_CDRCNTL2_D0)/sizeof(mmMC_IO_CDRCNTL2_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL2_D1", REG_MMIO, 0xae5, &mmMC_IO_CDRCNTL2_D1[0], sizeof(mmMC_IO_CDRCNTL2_D1)/sizeof(mmMC_IO_CDRCNTL2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_MISC", REG_MMIO, 0xae6, &mmMC_SEQ_TSM_MISC[0], sizeof(mmMC_SEQ_TSM_MISC)/sizeof(mmMC_SEQ_TSM_MISC[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC9", REG_MMIO, 0xae7, &mmMC_SEQ_MISC9[0], sizeof(mmMC_SEQ_MISC9)/sizeof(mmMC_SEQ_MISC9[0]), 0, 0 },
+	{ "mmMCLK_PWRMGT_CNTL", REG_MMIO, 0xae8, &mmMCLK_PWRMGT_CNTL[0], sizeof(mmMCLK_PWRMGT_CNTL)/sizeof(mmMCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "mmDLL_CNTL", REG_MMIO, 0xae9, &mmDLL_CNTL[0], sizeof(mmDLL_CNTL)/sizeof(mmDLL_CNTL[0]), 0, 0 },
+	{ "mmMPLL_SEQ_UCODE_1", REG_MMIO, 0xaea, &mmMPLL_SEQ_UCODE_1[0], sizeof(mmMPLL_SEQ_UCODE_1)/sizeof(mmMPLL_SEQ_UCODE_1[0]), 0, 0 },
+	{ "mmMPLL_SEQ_UCODE_2", REG_MMIO, 0xaeb, &mmMPLL_SEQ_UCODE_2[0], sizeof(mmMPLL_SEQ_UCODE_2)/sizeof(mmMPLL_SEQ_UCODE_2[0]), 0, 0 },
+	{ "mmMPLL_CNTL_MODE", REG_MMIO, 0xaec, &mmMPLL_CNTL_MODE[0], sizeof(mmMPLL_CNTL_MODE)/sizeof(mmMPLL_CNTL_MODE[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL", REG_MMIO, 0xaed, &mmMPLL_FUNC_CNTL[0], sizeof(mmMPLL_FUNC_CNTL)/sizeof(mmMPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL_1", REG_MMIO, 0xaee, &mmMPLL_FUNC_CNTL_1[0], sizeof(mmMPLL_FUNC_CNTL_1)/sizeof(mmMPLL_FUNC_CNTL_1[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL_2", REG_MMIO, 0xaef, &mmMPLL_FUNC_CNTL_2[0], sizeof(mmMPLL_FUNC_CNTL_2)/sizeof(mmMPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_MISC_D0", REG_SMC, 0xaf, &ixMC_IO_DEBUG_CMD_MISC_D0[0], sizeof(ixMC_IO_DEBUG_CMD_MISC_D0)/sizeof(ixMC_IO_DEBUG_CMD_MISC_D0[0]), 0, 0 },
+	{ "mmMPLL_AD_FUNC_CNTL", REG_MMIO, 0xaf0, &mmMPLL_AD_FUNC_CNTL[0], sizeof(mmMPLL_AD_FUNC_CNTL)/sizeof(mmMPLL_AD_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_DQ_FUNC_CNTL", REG_MMIO, 0xaf1, &mmMPLL_DQ_FUNC_CNTL[0], sizeof(mmMPLL_DQ_FUNC_CNTL)/sizeof(mmMPLL_DQ_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_TIME", REG_MMIO, 0xaf2, &mmMPLL_TIME[0], sizeof(mmMPLL_TIME)/sizeof(mmMPLL_TIME[0]), 0, 0 },
+	{ "mmMPLL_SS1", REG_MMIO, 0xaf3, &mmMPLL_SS1[0], sizeof(mmMPLL_SS1)/sizeof(mmMPLL_SS1[0]), 0, 0 },
+	{ "mmMPLL_SS2", REG_MMIO, 0xaf4, &mmMPLL_SS2[0], sizeof(mmMPLL_SS2)/sizeof(mmMPLL_SS2[0]), 0, 0 },
+	{ "mmMPLL_CONTROL", REG_MMIO, 0xaf5, &mmMPLL_CONTROL[0], sizeof(mmMPLL_CONTROL)/sizeof(mmMPLL_CONTROL[0]), 0, 0 },
+	{ "mmMPLL_AD_STATUS", REG_MMIO, 0xaf6, &mmMPLL_AD_STATUS[0], sizeof(mmMPLL_AD_STATUS)/sizeof(mmMPLL_AD_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_0_0_STATUS", REG_MMIO, 0xaf7, &mmMPLL_DQ_0_0_STATUS[0], sizeof(mmMPLL_DQ_0_0_STATUS)/sizeof(mmMPLL_DQ_0_0_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_0_1_STATUS", REG_MMIO, 0xaf8, &mmMPLL_DQ_0_1_STATUS[0], sizeof(mmMPLL_DQ_0_1_STATUS)/sizeof(mmMPLL_DQ_0_1_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_1_0_STATUS", REG_MMIO, 0xaf9, &mmMPLL_DQ_1_0_STATUS[0], sizeof(mmMPLL_DQ_1_0_STATUS)/sizeof(mmMPLL_DQ_1_0_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_1_1_STATUS", REG_MMIO, 0xafa, &mmMPLL_DQ_1_1_STATUS[0], sizeof(mmMPLL_DQ_1_1_STATUS)/sizeof(mmMPLL_DQ_1_1_STATUS[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_2_D0", REG_MMIO, 0xafb, &mmMC_TRAIN_PRBSERR_2_D0[0], sizeof(mmMC_TRAIN_PRBSERR_2_D0)/sizeof(mmMC_TRAIN_PRBSERR_2_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_2_D1", REG_MMIO, 0xafc, &mmMC_TRAIN_PRBSERR_2_D1[0], sizeof(mmMC_TRAIN_PRBSERR_2_D1)/sizeof(mmMC_TRAIN_PRBSERR_2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_CNTL_1", REG_MMIO, 0xafd, &mmMC_SEQ_PERF_CNTL_1[0], sizeof(mmMC_SEQ_PERF_CNTL_1)/sizeof(mmMC_SEQ_PERF_CNTL_1[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD2", REG_MMIO, 0xafe, &mmMC_SEQ_TRAIN_EDC_THRESHOLD2[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD2)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD2[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD3", REG_MMIO, 0xaff, &mmMC_SEQ_TRAIN_EDC_THRESHOLD3[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD3)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD3[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT8", REG_SMC, 0xb, &ixMC_TSM_DEBUG_BCNT8[0], sizeof(ixMC_TSM_DEBUG_BCNT8)/sizeof(ixMC_TSM_DEBUG_BCNT8[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_11", REG_SMC, 0xb, &ixMC_IO_DEBUG_UP_11[0], sizeof(ixMC_IO_DEBUG_UP_11)/sizeof(ixMC_IO_DEBUG_UP_11[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_MISC_D1", REG_SMC, 0xb0, &ixMC_IO_DEBUG_DQB0L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_MISC_D1", REG_SMC, 0xb1, &ixMC_IO_DEBUG_DQB0H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_MISC_D1", REG_SMC, 0xb2, &ixMC_IO_DEBUG_DQB1L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_MISC_D1", REG_SMC, 0xb3, &ixMC_IO_DEBUG_DQB1H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_MISC_D1", REG_SMC, 0xb4, &ixMC_IO_DEBUG_DQB2L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_MISC_D1", REG_SMC, 0xb5, &ixMC_IO_DEBUG_DQB2H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_MISC_D1", REG_SMC, 0xb6, &ixMC_IO_DEBUG_DQB3L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_MISC_D1", REG_SMC, 0xb7, &ixMC_IO_DEBUG_DQB3H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_MISC_D1", REG_SMC, 0xb8, &ixMC_IO_DEBUG_DBI_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DBI_MISC_D1)/sizeof(ixMC_IO_DEBUG_DBI_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_MISC_D1", REG_SMC, 0xb9, &ixMC_IO_DEBUG_EDC_MISC_D1[0], sizeof(ixMC_IO_DEBUG_EDC_MISC_D1)/sizeof(ixMC_IO_DEBUG_EDC_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_MISC_D1", REG_SMC, 0xba, &ixMC_IO_DEBUG_WCK_MISC_D1[0], sizeof(ixMC_IO_DEBUG_WCK_MISC_D1)/sizeof(ixMC_IO_DEBUG_WCK_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_MISC_D1", REG_SMC, 0xbb, &ixMC_IO_DEBUG_CK_MISC_D1[0], sizeof(ixMC_IO_DEBUG_CK_MISC_D1)/sizeof(ixMC_IO_DEBUG_CK_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_MISC_D1", REG_SMC, 0xbc, &ixMC_IO_DEBUG_ADDRL_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_MISC_D1", REG_SMC, 0xbd, &ixMC_IO_DEBUG_ADDRH_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_MISC_D1", REG_SMC, 0xbe, &ixMC_IO_DEBUG_ACMD_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_MISC_D1)/sizeof(ixMC_IO_DEBUG_ACMD_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_MISC_D1", REG_SMC, 0xbf, &ixMC_IO_DEBUG_CMD_MISC_D1[0], sizeof(ixMC_IO_DEBUG_CMD_MISC_D1)/sizeof(ixMC_IO_DEBUG_CMD_MISC_D1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT9", REG_SMC, 0xc, &ixMC_TSM_DEBUG_BCNT9[0], sizeof(ixMC_TSM_DEBUG_BCNT9)/sizeof(ixMC_TSM_DEBUG_BCNT9[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_12", REG_SMC, 0xc, &ixMC_IO_DEBUG_UP_12[0], sizeof(ixMC_IO_DEBUG_UP_12)/sizeof(ixMC_IO_DEBUG_UP_12[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_CLKSEL_D0", REG_SMC, 0xc0, &ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_CLKSEL_D0", REG_SMC, 0xc1, &ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_CLKSEL_D0", REG_SMC, 0xc2, &ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_CLKSEL_D0", REG_SMC, 0xc3, &ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_CLKSEL_D0", REG_SMC, 0xc4, &ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_CLKSEL_D0", REG_SMC, 0xc5, &ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_CLKSEL_D0", REG_SMC, 0xc6, &ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_CLKSEL_D0", REG_SMC, 0xc7, &ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CLKSEL_D0", REG_SMC, 0xc8, &ixMC_IO_DEBUG_DBI_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D0[0]), 0, 0 },
+	{ "mmMC_XBAR_ADDR_DEC", REG_MMIO, 0xc80, &mmMC_XBAR_ADDR_DEC[0], sizeof(mmMC_XBAR_ADDR_DEC)/sizeof(mmMC_XBAR_ADDR_DEC[0]), 0, 0 },
+	{ "mmMC_XBAR_REMOTE", REG_MMIO, 0xc81, &mmMC_XBAR_REMOTE[0], sizeof(mmMC_XBAR_REMOTE)/sizeof(mmMC_XBAR_REMOTE[0]), 0, 0 },
+	{ "mmMC_XBAR_WRREQ_CREDIT", REG_MMIO, 0xc82, &mmMC_XBAR_WRREQ_CREDIT[0], sizeof(mmMC_XBAR_WRREQ_CREDIT)/sizeof(mmMC_XBAR_WRREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_CREDIT", REG_MMIO, 0xc83, &mmMC_XBAR_RDREQ_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_CREDIT)/sizeof(mmMC_XBAR_RDREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_PRI_CREDIT", REG_MMIO, 0xc84, &mmMC_XBAR_RDREQ_PRI_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT)/sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT1", REG_MMIO, 0xc85, &mmMC_XBAR_WRRET_CREDIT1[0], sizeof(mmMC_XBAR_WRRET_CREDIT1)/sizeof(mmMC_XBAR_WRRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT2", REG_MMIO, 0xc86, &mmMC_XBAR_WRRET_CREDIT2[0], sizeof(mmMC_XBAR_WRRET_CREDIT2)/sizeof(mmMC_XBAR_WRRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT1", REG_MMIO, 0xc87, &mmMC_XBAR_RDRET_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_CREDIT1)/sizeof(mmMC_XBAR_RDRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT2", REG_MMIO, 0xc88, &mmMC_XBAR_RDRET_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_CREDIT2)/sizeof(mmMC_XBAR_RDRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT1", REG_MMIO, 0xc89, &mmMC_XBAR_RDRET_PRI_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT2", REG_MMIO, 0xc8a, &mmMC_XBAR_RDRET_PRI_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_CHTRIREMAP", REG_MMIO, 0xc8b, &mmMC_XBAR_CHTRIREMAP[0], sizeof(mmMC_XBAR_CHTRIREMAP)/sizeof(mmMC_XBAR_CHTRIREMAP[0]), 0, 0 },
+	{ "mmMC_XBAR_TWOCHAN", REG_MMIO, 0xc8c, &mmMC_XBAR_TWOCHAN[0], sizeof(mmMC_XBAR_TWOCHAN)/sizeof(mmMC_XBAR_TWOCHAN[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB", REG_MMIO, 0xc8d, &mmMC_XBAR_ARB[0], sizeof(mmMC_XBAR_ARB)/sizeof(mmMC_XBAR_ARB[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB_MAX_BURST", REG_MMIO, 0xc8e, &mmMC_XBAR_ARB_MAX_BURST[0], sizeof(mmMC_XBAR_ARB_MAX_BURST)/sizeof(mmMC_XBAR_ARB_MAX_BURST[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL0", REG_MMIO, 0xc8f, &mmMC_XBAR_PERF_MON_CNTL0[0], sizeof(mmMC_XBAR_PERF_MON_CNTL0)/sizeof(mmMC_XBAR_PERF_MON_CNTL0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CLKSEL_D0", REG_SMC, 0xc9, &ixMC_IO_DEBUG_EDC_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D0[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL1", REG_MMIO, 0xc90, &mmMC_XBAR_PERF_MON_CNTL1[0], sizeof(mmMC_XBAR_PERF_MON_CNTL1)/sizeof(mmMC_XBAR_PERF_MON_CNTL1[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_CNTL2", REG_MMIO, 0xc91, &mmMC_XBAR_PERF_MON_CNTL2[0], sizeof(mmMC_XBAR_PERF_MON_CNTL2)/sizeof(mmMC_XBAR_PERF_MON_CNTL2[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT0", REG_MMIO, 0xc92, &mmMC_XBAR_PERF_MON_RSLT0[0], sizeof(mmMC_XBAR_PERF_MON_RSLT0)/sizeof(mmMC_XBAR_PERF_MON_RSLT0[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT1", REG_MMIO, 0xc93, &mmMC_XBAR_PERF_MON_RSLT1[0], sizeof(mmMC_XBAR_PERF_MON_RSLT1)/sizeof(mmMC_XBAR_PERF_MON_RSLT1[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT2", REG_MMIO, 0xc94, &mmMC_XBAR_PERF_MON_RSLT2[0], sizeof(mmMC_XBAR_PERF_MON_RSLT2)/sizeof(mmMC_XBAR_PERF_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_RSLT3", REG_MMIO, 0xc95, &mmMC_XBAR_PERF_MON_RSLT3[0], sizeof(mmMC_XBAR_PERF_MON_RSLT3)/sizeof(mmMC_XBAR_PERF_MON_RSLT3[0]), 0, 0 },
+	{ "mmMC_XBAR_PERF_MON_MAX_THSH", REG_MMIO, 0xc96, &mmMC_XBAR_PERF_MON_MAX_THSH[0], sizeof(mmMC_XBAR_PERF_MON_MAX_THSH)/sizeof(mmMC_XBAR_PERF_MON_MAX_THSH[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE0", REG_MMIO, 0xc97, &mmMC_XBAR_SPARE0[0], sizeof(mmMC_XBAR_SPARE0)/sizeof(mmMC_XBAR_SPARE0[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE1", REG_MMIO, 0xc98, &mmMC_XBAR_SPARE1[0], sizeof(mmMC_XBAR_SPARE1)/sizeof(mmMC_XBAR_SPARE1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_CLKSEL_D0", REG_SMC, 0xca, &ixMC_IO_DEBUG_WCK_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_CLKSEL_D0", REG_SMC, 0xcb, &ixMC_IO_DEBUG_CK_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_CLKSEL_D0", REG_SMC, 0xcc, &ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_LOW_ADDR", REG_MMIO, 0xcc0, &mmATC_VM_APERTURE0_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE0_LOW_ADDR)/sizeof(mmATC_VM_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_LOW_ADDR", REG_MMIO, 0xcc1, &mmATC_VM_APERTURE1_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE1_LOW_ADDR)/sizeof(mmATC_VM_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_HIGH_ADDR", REG_MMIO, 0xcc2, &mmATC_VM_APERTURE0_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE0_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_HIGH_ADDR", REG_MMIO, 0xcc3, &mmATC_VM_APERTURE1_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE1_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL", REG_MMIO, 0xcc4, &mmATC_VM_APERTURE0_CNTL[0], sizeof(mmATC_VM_APERTURE0_CNTL)/sizeof(mmATC_VM_APERTURE0_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL", REG_MMIO, 0xcc5, &mmATC_VM_APERTURE1_CNTL[0], sizeof(mmATC_VM_APERTURE1_CNTL)/sizeof(mmATC_VM_APERTURE1_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL2", REG_MMIO, 0xcc6, &mmATC_VM_APERTURE0_CNTL2[0], sizeof(mmATC_VM_APERTURE0_CNTL2)/sizeof(mmATC_VM_APERTURE0_CNTL2[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL2", REG_MMIO, 0xcc7, &mmATC_VM_APERTURE1_CNTL2[0], sizeof(mmATC_VM_APERTURE1_CNTL2)/sizeof(mmATC_VM_APERTURE1_CNTL2[0]), 0, 0 },
+	{ "mmATC_ATS_CNTL", REG_MMIO, 0xcc9, &mmATC_ATS_CNTL[0], sizeof(mmATC_ATS_CNTL)/sizeof(mmATC_ATS_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_DEBUG", REG_MMIO, 0xcca, &mmATC_ATS_DEBUG[0], sizeof(mmATC_ATS_DEBUG)/sizeof(mmATC_ATS_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_DEBUG", REG_MMIO, 0xccb, &mmATC_ATS_FAULT_DEBUG[0], sizeof(mmATC_ATS_FAULT_DEBUG)/sizeof(mmATC_ATS_FAULT_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_STATUS", REG_MMIO, 0xccc, &mmATC_ATS_STATUS[0], sizeof(mmATC_ATS_STATUS)/sizeof(mmATC_ATS_STATUS[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_CNTL", REG_MMIO, 0xccd, &mmATC_ATS_FAULT_CNTL[0], sizeof(mmATC_ATS_FAULT_CNTL)/sizeof(mmATC_ATS_FAULT_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_INFO", REG_MMIO, 0xcce, &mmATC_ATS_FAULT_STATUS_INFO[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO)/sizeof(mmATC_ATS_FAULT_STATUS_INFO[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_ADDR", REG_MMIO, 0xccf, &mmATC_ATS_FAULT_STATUS_ADDR[0], sizeof(mmATC_ATS_FAULT_STATUS_ADDR)/sizeof(mmATC_ATS_FAULT_STATUS_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_CLKSEL_D0", REG_SMC, 0xcd, &ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_LOW", REG_MMIO, 0xcd0, &mmATC_ATS_DEFAULT_PAGE_LOW[0], sizeof(mmATC_ATS_DEFAULT_PAGE_LOW)/sizeof(mmATC_ATS_DEFAULT_PAGE_LOW[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_CNTL", REG_MMIO, 0xcd1, &mmATC_ATS_DEFAULT_PAGE_CNTL[0], sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL)/sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL[0]), 0, 0 },
+	{ "mmATC_MISC_CG", REG_MMIO, 0xcd4, &mmATC_MISC_CG[0], sizeof(mmATC_MISC_CG)/sizeof(mmATC_MISC_CG[0]), 0, 0 },
+	{ "mmATC_L2_CNTL", REG_MMIO, 0xcd5, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 },
+	{ "mmATC_L2_CNTL2", REG_MMIO, 0xcd6, &mmATC_L2_CNTL2[0], sizeof(mmATC_L2_CNTL2)/sizeof(mmATC_L2_CNTL2[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG", REG_MMIO, 0xcd7, &mmATC_L2_DEBUG[0], sizeof(mmATC_L2_DEBUG)/sizeof(mmATC_L2_DEBUG[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG2", REG_MMIO, 0xcd8, &mmATC_L2_DEBUG2[0], sizeof(mmATC_L2_DEBUG2)/sizeof(mmATC_L2_DEBUG2[0]), 0, 0 },
+	{ "mmATC_L1_CNTL", REG_MMIO, 0xcdc, &mmATC_L1_CNTL[0], sizeof(mmATC_L1_CNTL)/sizeof(mmATC_L1_CNTL[0]), 0, 0 },
+	{ "mmATC_L1_ADDRESS_OFFSET", REG_MMIO, 0xcdd, &mmATC_L1_ADDRESS_OFFSET[0], sizeof(mmATC_L1_ADDRESS_OFFSET)/sizeof(mmATC_L1_ADDRESS_OFFSET[0]), 0, 0 },
+	{ "mmATC_L1RD_DEBUG_TLB", REG_MMIO, 0xcde, &mmATC_L1RD_DEBUG_TLB[0], sizeof(mmATC_L1RD_DEBUG_TLB)/sizeof(mmATC_L1RD_DEBUG_TLB[0]), 0, 0 },
+	{ "mmATC_L1WR_DEBUG_TLB", REG_MMIO, 0xcdf, &mmATC_L1WR_DEBUG_TLB[0], sizeof(mmATC_L1WR_DEBUG_TLB)/sizeof(mmATC_L1WR_DEBUG_TLB[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_CLKSEL_D0", REG_SMC, 0xce, &ixMC_IO_DEBUG_ACMD_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D0[0]), 0, 0 },
+	{ "mmATC_L1RD_STATUS", REG_MMIO, 0xce0, &mmATC_L1RD_STATUS[0], sizeof(mmATC_L1RD_STATUS)/sizeof(mmATC_L1RD_STATUS[0]), 0, 0 },
+	{ "mmATC_L1WR_STATUS", REG_MMIO, 0xce1, &mmATC_L1WR_STATUS[0], sizeof(mmATC_L1WR_STATUS)/sizeof(mmATC_L1WR_STATUS[0]), 0, 0 },
+	{ "mmATC_VMID_PASID_MAPPING_UPDATE_STATUS", REG_MMIO, 0xce6, &mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0], sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)/sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmATC_VMID0_PASID_MAPPING", REG_MMIO, 0xce7, &mmATC_VMID0_PASID_MAPPING[0], sizeof(mmATC_VMID0_PASID_MAPPING)/sizeof(mmATC_VMID0_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID1_PASID_MAPPING", REG_MMIO, 0xce8, &mmATC_VMID1_PASID_MAPPING[0], sizeof(mmATC_VMID1_PASID_MAPPING)/sizeof(mmATC_VMID1_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID2_PASID_MAPPING", REG_MMIO, 0xce9, &mmATC_VMID2_PASID_MAPPING[0], sizeof(mmATC_VMID2_PASID_MAPPING)/sizeof(mmATC_VMID2_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID3_PASID_MAPPING", REG_MMIO, 0xcea, &mmATC_VMID3_PASID_MAPPING[0], sizeof(mmATC_VMID3_PASID_MAPPING)/sizeof(mmATC_VMID3_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID4_PASID_MAPPING", REG_MMIO, 0xceb, &mmATC_VMID4_PASID_MAPPING[0], sizeof(mmATC_VMID4_PASID_MAPPING)/sizeof(mmATC_VMID4_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID5_PASID_MAPPING", REG_MMIO, 0xcec, &mmATC_VMID5_PASID_MAPPING[0], sizeof(mmATC_VMID5_PASID_MAPPING)/sizeof(mmATC_VMID5_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID6_PASID_MAPPING", REG_MMIO, 0xced, &mmATC_VMID6_PASID_MAPPING[0], sizeof(mmATC_VMID6_PASID_MAPPING)/sizeof(mmATC_VMID6_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID7_PASID_MAPPING", REG_MMIO, 0xcee, &mmATC_VMID7_PASID_MAPPING[0], sizeof(mmATC_VMID7_PASID_MAPPING)/sizeof(mmATC_VMID7_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID8_PASID_MAPPING", REG_MMIO, 0xcef, &mmATC_VMID8_PASID_MAPPING[0], sizeof(mmATC_VMID8_PASID_MAPPING)/sizeof(mmATC_VMID8_PASID_MAPPING[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_CLKSEL_D0", REG_SMC, 0xcf, &ixMC_IO_DEBUG_CMD_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D0[0]), 0, 0 },
+	{ "mmATC_VMID9_PASID_MAPPING", REG_MMIO, 0xcf0, &mmATC_VMID9_PASID_MAPPING[0], sizeof(mmATC_VMID9_PASID_MAPPING)/sizeof(mmATC_VMID9_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID10_PASID_MAPPING", REG_MMIO, 0xcf1, &mmATC_VMID10_PASID_MAPPING[0], sizeof(mmATC_VMID10_PASID_MAPPING)/sizeof(mmATC_VMID10_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID11_PASID_MAPPING", REG_MMIO, 0xcf2, &mmATC_VMID11_PASID_MAPPING[0], sizeof(mmATC_VMID11_PASID_MAPPING)/sizeof(mmATC_VMID11_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID12_PASID_MAPPING", REG_MMIO, 0xcf3, &mmATC_VMID12_PASID_MAPPING[0], sizeof(mmATC_VMID12_PASID_MAPPING)/sizeof(mmATC_VMID12_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID13_PASID_MAPPING", REG_MMIO, 0xcf4, &mmATC_VMID13_PASID_MAPPING[0], sizeof(mmATC_VMID13_PASID_MAPPING)/sizeof(mmATC_VMID13_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID14_PASID_MAPPING", REG_MMIO, 0xcf5, &mmATC_VMID14_PASID_MAPPING[0], sizeof(mmATC_VMID14_PASID_MAPPING)/sizeof(mmATC_VMID14_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID15_PASID_MAPPING", REG_MMIO, 0xcf6, &mmATC_VMID15_PASID_MAPPING[0], sizeof(mmATC_VMID15_PASID_MAPPING)/sizeof(mmATC_VMID15_PASID_MAPPING[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT10", REG_SMC, 0xd, &ixMC_TSM_DEBUG_BCNT10[0], sizeof(ixMC_TSM_DEBUG_BCNT10)/sizeof(ixMC_TSM_DEBUG_BCNT10[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_13", REG_SMC, 0xd, &ixMC_IO_DEBUG_UP_13[0], sizeof(ixMC_IO_DEBUG_UP_13)/sizeof(ixMC_IO_DEBUG_UP_13[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_CLKSEL_D1", REG_SMC, 0xd0, &ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_CLKSEL_D1", REG_SMC, 0xd1, &ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_CLKSEL_D1", REG_SMC, 0xd2, &ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_CLKSEL_D1", REG_SMC, 0xd3, &ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_CLKSEL_D1", REG_SMC, 0xd4, &ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_INDEX", REG_MMIO, 0xd40, &mmGMCON_RENG_RAM_INDEX[0], sizeof(mmGMCON_RENG_RAM_INDEX)/sizeof(mmGMCON_RENG_RAM_INDEX[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_DATA", REG_MMIO, 0xd41, &mmGMCON_RENG_RAM_DATA[0], sizeof(mmGMCON_RENG_RAM_DATA)/sizeof(mmGMCON_RENG_RAM_DATA[0]), 0, 0 },
+	{ "mmGMCON_RENG_EXECUTE", REG_MMIO, 0xd42, &mmGMCON_RENG_EXECUTE[0], sizeof(mmGMCON_RENG_EXECUTE)/sizeof(mmGMCON_RENG_EXECUTE[0]), 0, 0 },
+	{ "mmGMCON_MISC", REG_MMIO, 0xd43, &mmGMCON_MISC[0], sizeof(mmGMCON_MISC)/sizeof(mmGMCON_MISC[0]), 0, 0 },
+	{ "mmGMCON_MISC2", REG_MMIO, 0xd44, &mmGMCON_MISC2[0], sizeof(mmGMCON_MISC2)/sizeof(mmGMCON_MISC2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0xd45, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0xd46, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0xd47, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0", REG_MMIO, 0xd48, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0xd49, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL0", REG_MMIO, 0xd4a, &mmGMCON_PERF_MON_CNTL0[0], sizeof(mmGMCON_PERF_MON_CNTL0)/sizeof(mmGMCON_PERF_MON_CNTL0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL1", REG_MMIO, 0xd4b, &mmGMCON_PERF_MON_CNTL1[0], sizeof(mmGMCON_PERF_MON_CNTL1)/sizeof(mmGMCON_PERF_MON_CNTL1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT0", REG_MMIO, 0xd4c, &mmGMCON_PERF_MON_RSLT0[0], sizeof(mmGMCON_PERF_MON_RSLT0)/sizeof(mmGMCON_PERF_MON_RSLT0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT1", REG_MMIO, 0xd4d, &mmGMCON_PERF_MON_RSLT1[0], sizeof(mmGMCON_PERF_MON_RSLT1)/sizeof(mmGMCON_PERF_MON_RSLT1[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_CONFIG", REG_MMIO, 0xd4e, &mmGMCON_PGFSM_CONFIG[0], sizeof(mmGMCON_PGFSM_CONFIG)/sizeof(mmGMCON_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_WRITE", REG_MMIO, 0xd4f, &mmGMCON_PGFSM_WRITE[0], sizeof(mmGMCON_PGFSM_WRITE)/sizeof(mmGMCON_PGFSM_WRITE[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_CLKSEL_D1", REG_SMC, 0xd5, &ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_READ", REG_MMIO, 0xd50, &mmGMCON_PGFSM_READ[0], sizeof(mmGMCON_PGFSM_READ)/sizeof(mmGMCON_PGFSM_READ[0]), 0, 0 },
+	{ "mmGMCON_MISC3", REG_MMIO, 0xd51, &mmGMCON_MISC3[0], sizeof(mmGMCON_MISC3)/sizeof(mmGMCON_MISC3[0]), 0, 0 },
+	{ "mmGMCON_MASK", REG_MMIO, 0xd52, &mmGMCON_MASK[0], sizeof(mmGMCON_MASK)/sizeof(mmGMCON_MASK[0]), 0, 0 },
+	{ "mmGMCON_LPT_TARGET", REG_MMIO, 0xd53, &mmGMCON_LPT_TARGET[0], sizeof(mmGMCON_LPT_TARGET)/sizeof(mmGMCON_LPT_TARGET[0]), 0, 0 },
+	{ "mmGMCON_DEBUG", REG_MMIO, 0xd5f, &mmGMCON_DEBUG[0], sizeof(mmGMCON_DEBUG)/sizeof(mmGMCON_DEBUG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_CLKSEL_D1", REG_SMC, 0xd6, &ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_CLKSEL_D1", REG_SMC, 0xd7, &ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CLKSEL_D1", REG_SMC, 0xd8, &ixMC_IO_DEBUG_DBI_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_CNTL_3", REG_MMIO, 0xd80, &mmMC_SEQ_CNTL_3[0], sizeof(mmMC_SEQ_CNTL_3)/sizeof(mmMC_SEQ_CNTL_3[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CTRL", REG_MMIO, 0xd81, &mmMC_SEQ_G5PDX_CTRL[0], sizeof(mmMC_SEQ_G5PDX_CTRL)/sizeof(mmMC_SEQ_G5PDX_CTRL[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CTRL_LP", REG_MMIO, 0xd82, &mmMC_SEQ_G5PDX_CTRL_LP[0], sizeof(mmMC_SEQ_G5PDX_CTRL_LP)/sizeof(mmMC_SEQ_G5PDX_CTRL_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CMD0", REG_MMIO, 0xd83, &mmMC_SEQ_G5PDX_CMD0[0], sizeof(mmMC_SEQ_G5PDX_CMD0)/sizeof(mmMC_SEQ_G5PDX_CMD0[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CMD0_LP", REG_MMIO, 0xd84, &mmMC_SEQ_G5PDX_CMD0_LP[0], sizeof(mmMC_SEQ_G5PDX_CMD0_LP)/sizeof(mmMC_SEQ_G5PDX_CMD0_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CMD1", REG_MMIO, 0xd85, &mmMC_SEQ_G5PDX_CMD1[0], sizeof(mmMC_SEQ_G5PDX_CMD1)/sizeof(mmMC_SEQ_G5PDX_CMD1[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CMD1_LP", REG_MMIO, 0xd86, &mmMC_SEQ_G5PDX_CMD1_LP[0], sizeof(mmMC_SEQ_G5PDX_CMD1_LP)/sizeof(mmMC_SEQ_G5PDX_CMD1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_SREG_READ", REG_MMIO, 0xd87, &mmMC_SEQ_SREG_READ[0], sizeof(mmMC_SEQ_SREG_READ)/sizeof(mmMC_SEQ_SREG_READ[0]), 0, 0 },
+	{ "mmMC_SEQ_SREG_STATUS", REG_MMIO, 0xd88, &mmMC_SEQ_SREG_STATUS[0], sizeof(mmMC_SEQ_SREG_STATUS)/sizeof(mmMC_SEQ_SREG_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_PHYREG_BCAST", REG_MMIO, 0xd89, &mmMC_SEQ_PHYREG_BCAST[0], sizeof(mmMC_SEQ_PHYREG_BCAST)/sizeof(mmMC_SEQ_PHYREG_BCAST[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_DVS_CTL", REG_MMIO, 0xd8a, &mmMC_SEQ_PMG_DVS_CTL[0], sizeof(mmMC_SEQ_PMG_DVS_CTL)/sizeof(mmMC_SEQ_PMG_DVS_CTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_DVS_CTL_LP", REG_MMIO, 0xd8b, &mmMC_SEQ_PMG_DVS_CTL_LP[0], sizeof(mmMC_SEQ_PMG_DVS_CTL_LP)/sizeof(mmMC_SEQ_PMG_DVS_CTL_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_DVS_CMD", REG_MMIO, 0xd8c, &mmMC_SEQ_PMG_DVS_CMD[0], sizeof(mmMC_SEQ_PMG_DVS_CMD)/sizeof(mmMC_SEQ_PMG_DVS_CMD[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_DVS_CMD_LP", REG_MMIO, 0xd8d, &mmMC_SEQ_PMG_DVS_CMD_LP[0], sizeof(mmMC_SEQ_PMG_DVS_CMD_LP)/sizeof(mmMC_SEQ_PMG_DVS_CMD_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_DLL_STBY", REG_MMIO, 0xd8e, &mmMC_SEQ_DLL_STBY[0], sizeof(mmMC_SEQ_DLL_STBY)/sizeof(mmMC_SEQ_DLL_STBY[0]), 0, 0 },
+	{ "mmMC_SEQ_DLL_STBY_LP", REG_MMIO, 0xd8f, &mmMC_SEQ_DLL_STBY_LP[0], sizeof(mmMC_SEQ_DLL_STBY_LP)/sizeof(mmMC_SEQ_DLL_STBY_LP[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CLKSEL_D1", REG_SMC, 0xd9, &ixMC_IO_DEBUG_EDC_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_DLB_MISCCTRL0", REG_MMIO, 0xd90, &mmMC_DLB_MISCCTRL0[0], sizeof(mmMC_DLB_MISCCTRL0)/sizeof(mmMC_DLB_MISCCTRL0[0]), 0, 0 },
+	{ "mmMC_DLB_MISCCTRL1", REG_MMIO, 0xd91, &mmMC_DLB_MISCCTRL1[0], sizeof(mmMC_DLB_MISCCTRL1)/sizeof(mmMC_DLB_MISCCTRL1[0]), 0, 0 },
+	{ "mmMC_DLB_MISCCTRL2", REG_MMIO, 0xd92, &mmMC_DLB_MISCCTRL2[0], sizeof(mmMC_DLB_MISCCTRL2)/sizeof(mmMC_DLB_MISCCTRL2[0]), 0, 0 },
+	{ "mmMC_DLB_CONFIG0", REG_MMIO, 0xd93, &mmMC_DLB_CONFIG0[0], sizeof(mmMC_DLB_CONFIG0)/sizeof(mmMC_DLB_CONFIG0[0]), 0, 0 },
+	{ "mmMC_DLB_CONFIG1", REG_MMIO, 0xd94, &mmMC_DLB_CONFIG1[0], sizeof(mmMC_DLB_CONFIG1)/sizeof(mmMC_DLB_CONFIG1[0]), 0, 0 },
+	{ "mmMC_DLB_SETUP", REG_MMIO, 0xd95, &mmMC_DLB_SETUP[0], sizeof(mmMC_DLB_SETUP)/sizeof(mmMC_DLB_SETUP[0]), 0, 0 },
+	{ "mmMC_DLB_SETUPSWEEP", REG_MMIO, 0xd96, &mmMC_DLB_SETUPSWEEP[0], sizeof(mmMC_DLB_SETUPSWEEP)/sizeof(mmMC_DLB_SETUPSWEEP[0]), 0, 0 },
+	{ "mmMC_DLB_SETUPFIFO", REG_MMIO, 0xd97, &mmMC_DLB_SETUPFIFO[0], sizeof(mmMC_DLB_SETUPFIFO)/sizeof(mmMC_DLB_SETUPFIFO[0]), 0, 0 },
+	{ "mmMC_DLB_WRITE_MASK", REG_MMIO, 0xd98, &mmMC_DLB_WRITE_MASK[0], sizeof(mmMC_DLB_WRITE_MASK)/sizeof(mmMC_DLB_WRITE_MASK[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS", REG_MMIO, 0xd99, &mmMC_DLB_STATUS[0], sizeof(mmMC_DLB_STATUS)/sizeof(mmMC_DLB_STATUS[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC0", REG_MMIO, 0xd9a, &mmMC_DLB_STATUS_MISC0[0], sizeof(mmMC_DLB_STATUS_MISC0)/sizeof(mmMC_DLB_STATUS_MISC0[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC1", REG_MMIO, 0xd9b, &mmMC_DLB_STATUS_MISC1[0], sizeof(mmMC_DLB_STATUS_MISC1)/sizeof(mmMC_DLB_STATUS_MISC1[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC2", REG_MMIO, 0xd9c, &mmMC_DLB_STATUS_MISC2[0], sizeof(mmMC_DLB_STATUS_MISC2)/sizeof(mmMC_DLB_STATUS_MISC2[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC3", REG_MMIO, 0xd9d, &mmMC_DLB_STATUS_MISC3[0], sizeof(mmMC_DLB_STATUS_MISC3)/sizeof(mmMC_DLB_STATUS_MISC3[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC4", REG_MMIO, 0xd9e, &mmMC_DLB_STATUS_MISC4[0], sizeof(mmMC_DLB_STATUS_MISC4)/sizeof(mmMC_DLB_STATUS_MISC4[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC5", REG_MMIO, 0xd9f, &mmMC_DLB_STATUS_MISC5[0], sizeof(mmMC_DLB_STATUS_MISC5)/sizeof(mmMC_DLB_STATUS_MISC5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_CLKSEL_D1", REG_SMC, 0xda, &ixMC_IO_DEBUG_WCK_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC6", REG_MMIO, 0xda0, &mmMC_DLB_STATUS_MISC6[0], sizeof(mmMC_DLB_STATUS_MISC6)/sizeof(mmMC_DLB_STATUS_MISC6[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC7", REG_MMIO, 0xda1, &mmMC_DLB_STATUS_MISC7[0], sizeof(mmMC_DLB_STATUS_MISC7)/sizeof(mmMC_DLB_STATUS_MISC7[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_CLKSEL_D1", REG_SMC, 0xdb, &ixMC_IO_DEBUG_CK_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_CLKSEL_D1", REG_SMC, 0xdc, &ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_EN_RD", REG_MMIO, 0xdc0, &mmMC_ARB_HARSH_EN_RD[0], sizeof(mmMC_ARB_HARSH_EN_RD)/sizeof(mmMC_ARB_HARSH_EN_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_EN_WR", REG_MMIO, 0xdc1, &mmMC_ARB_HARSH_EN_WR[0], sizeof(mmMC_ARB_HARSH_EN_WR)/sizeof(mmMC_ARB_HARSH_EN_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI0_RD", REG_MMIO, 0xdc2, &mmMC_ARB_HARSH_TX_HI0_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI0_RD)/sizeof(mmMC_ARB_HARSH_TX_HI0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI0_WR", REG_MMIO, 0xdc3, &mmMC_ARB_HARSH_TX_HI0_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI0_WR)/sizeof(mmMC_ARB_HARSH_TX_HI0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI1_RD", REG_MMIO, 0xdc4, &mmMC_ARB_HARSH_TX_HI1_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI1_RD)/sizeof(mmMC_ARB_HARSH_TX_HI1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI1_WR", REG_MMIO, 0xdc5, &mmMC_ARB_HARSH_TX_HI1_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI1_WR)/sizeof(mmMC_ARB_HARSH_TX_HI1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO0_RD", REG_MMIO, 0xdc6, &mmMC_ARB_HARSH_TX_LO0_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO0_RD)/sizeof(mmMC_ARB_HARSH_TX_LO0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO0_WR", REG_MMIO, 0xdc7, &mmMC_ARB_HARSH_TX_LO0_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO0_WR)/sizeof(mmMC_ARB_HARSH_TX_LO0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO1_RD", REG_MMIO, 0xdc8, &mmMC_ARB_HARSH_TX_LO1_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO1_RD)/sizeof(mmMC_ARB_HARSH_TX_LO1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO1_WR", REG_MMIO, 0xdc9, &mmMC_ARB_HARSH_TX_LO1_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO1_WR)/sizeof(mmMC_ARB_HARSH_TX_LO1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD0_RD", REG_MMIO, 0xdca, &mmMC_ARB_HARSH_BWPERIOD0_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD0_WR", REG_MMIO, 0xdcb, &mmMC_ARB_HARSH_BWPERIOD0_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD1_RD", REG_MMIO, 0xdcc, &mmMC_ARB_HARSH_BWPERIOD1_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD1_WR", REG_MMIO, 0xdcd, &mmMC_ARB_HARSH_BWPERIOD1_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT0_RD", REG_MMIO, 0xdce, &mmMC_ARB_HARSH_BWCNT0_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT0_RD)/sizeof(mmMC_ARB_HARSH_BWCNT0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT0_WR", REG_MMIO, 0xdcf, &mmMC_ARB_HARSH_BWCNT0_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT0_WR)/sizeof(mmMC_ARB_HARSH_BWCNT0_WR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_CLKSEL_D1", REG_SMC, 0xdd, &ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT1_RD", REG_MMIO, 0xdd0, &mmMC_ARB_HARSH_BWCNT1_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT1_RD)/sizeof(mmMC_ARB_HARSH_BWCNT1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT1_WR", REG_MMIO, 0xdd1, &mmMC_ARB_HARSH_BWCNT1_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT1_WR)/sizeof(mmMC_ARB_HARSH_BWCNT1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT0_RD", REG_MMIO, 0xdd2, &mmMC_ARB_HARSH_SAT0_RD[0], sizeof(mmMC_ARB_HARSH_SAT0_RD)/sizeof(mmMC_ARB_HARSH_SAT0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT0_WR", REG_MMIO, 0xdd3, &mmMC_ARB_HARSH_SAT0_WR[0], sizeof(mmMC_ARB_HARSH_SAT0_WR)/sizeof(mmMC_ARB_HARSH_SAT0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT1_RD", REG_MMIO, 0xdd4, &mmMC_ARB_HARSH_SAT1_RD[0], sizeof(mmMC_ARB_HARSH_SAT1_RD)/sizeof(mmMC_ARB_HARSH_SAT1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT1_WR", REG_MMIO, 0xdd5, &mmMC_ARB_HARSH_SAT1_WR[0], sizeof(mmMC_ARB_HARSH_SAT1_WR)/sizeof(mmMC_ARB_HARSH_SAT1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_CTL_RD", REG_MMIO, 0xdd6, &mmMC_ARB_HARSH_CTL_RD[0], sizeof(mmMC_ARB_HARSH_CTL_RD)/sizeof(mmMC_ARB_HARSH_CTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_CTL_WR", REG_MMIO, 0xdd7, &mmMC_ARB_HARSH_CTL_WR[0], sizeof(mmMC_ARB_HARSH_CTL_WR)/sizeof(mmMC_ARB_HARSH_CTL_WR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_CLKSEL_D1", REG_SMC, 0xde, &ixMC_IO_DEBUG_ACMD_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_SPM", REG_MMIO, 0xde0, &mmMC_HUB_RDREQ_ISP_SPM[0], sizeof(mmMC_HUB_RDREQ_ISP_SPM)/sizeof(mmMC_HUB_RDREQ_ISP_SPM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_MPM", REG_MMIO, 0xde1, &mmMC_HUB_RDREQ_ISP_MPM[0], sizeof(mmMC_HUB_RDREQ_ISP_MPM)/sizeof(mmMC_HUB_RDREQ_ISP_MPM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_CCPU", REG_MMIO, 0xde2, &mmMC_HUB_RDREQ_ISP_CCPU[0], sizeof(mmMC_HUB_RDREQ_ISP_CCPU)/sizeof(mmMC_HUB_RDREQ_ISP_CCPU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_SPM", REG_MMIO, 0xde3, &mmMC_HUB_WDP_ISP_SPM[0], sizeof(mmMC_HUB_WDP_ISP_SPM)/sizeof(mmMC_HUB_WDP_ISP_SPM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_MPS", REG_MMIO, 0xde4, &mmMC_HUB_WDP_ISP_MPS[0], sizeof(mmMC_HUB_WDP_ISP_MPS)/sizeof(mmMC_HUB_WDP_ISP_MPS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_MPM", REG_MMIO, 0xde5, &mmMC_HUB_WDP_ISP_MPM[0], sizeof(mmMC_HUB_WDP_ISP_MPM)/sizeof(mmMC_HUB_WDP_ISP_MPM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_CCPU", REG_MMIO, 0xde6, &mmMC_HUB_WDP_ISP_CCPU[0], sizeof(mmMC_HUB_WDP_ISP_CCPU)/sizeof(mmMC_HUB_WDP_ISP_CCPU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDS", REG_MMIO, 0xde7, &mmMC_HUB_RDREQ_MCDS[0], sizeof(mmMC_HUB_RDREQ_MCDS)/sizeof(mmMC_HUB_RDREQ_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDT", REG_MMIO, 0xde8, &mmMC_HUB_RDREQ_MCDT[0], sizeof(mmMC_HUB_RDREQ_MCDT)/sizeof(mmMC_HUB_RDREQ_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDU", REG_MMIO, 0xde9, &mmMC_HUB_RDREQ_MCDU[0], sizeof(mmMC_HUB_RDREQ_MCDU)/sizeof(mmMC_HUB_RDREQ_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDV", REG_MMIO, 0xdea, &mmMC_HUB_RDREQ_MCDV[0], sizeof(mmMC_HUB_RDREQ_MCDV)/sizeof(mmMC_HUB_RDREQ_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDS", REG_MMIO, 0xdeb, &mmMC_HUB_WDP_MCDS[0], sizeof(mmMC_HUB_WDP_MCDS)/sizeof(mmMC_HUB_WDP_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDT", REG_MMIO, 0xdec, &mmMC_HUB_WDP_MCDT[0], sizeof(mmMC_HUB_WDP_MCDT)/sizeof(mmMC_HUB_WDP_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDU", REG_MMIO, 0xded, &mmMC_HUB_WDP_MCDU[0], sizeof(mmMC_HUB_WDP_MCDU)/sizeof(mmMC_HUB_WDP_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDV", REG_MMIO, 0xdee, &mmMC_HUB_WDP_MCDV[0], sizeof(mmMC_HUB_WDP_MCDV)/sizeof(mmMC_HUB_WDP_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDS", REG_MMIO, 0xdef, &mmMC_HUB_WRRET_MCDS[0], sizeof(mmMC_HUB_WRRET_MCDS)/sizeof(mmMC_HUB_WRRET_MCDS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_CLKSEL_D1", REG_SMC, 0xdf, &ixMC_IO_DEBUG_CMD_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDT", REG_MMIO, 0xdf0, &mmMC_HUB_WRRET_MCDT[0], sizeof(mmMC_HUB_WRRET_MCDT)/sizeof(mmMC_HUB_WRRET_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDU", REG_MMIO, 0xdf1, &mmMC_HUB_WRRET_MCDU[0], sizeof(mmMC_HUB_WRRET_MCDU)/sizeof(mmMC_HUB_WRRET_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDV", REG_MMIO, 0xdf2, &mmMC_HUB_WRRET_MCDV[0], sizeof(mmMC_HUB_WRRET_MCDV)/sizeof(mmMC_HUB_WRRET_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDW", REG_MMIO, 0xdf3, &mmMC_HUB_WDP_CREDITS_MCDW[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDW)/sizeof(mmMC_HUB_WDP_CREDITS_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDX", REG_MMIO, 0xdf4, &mmMC_HUB_WDP_CREDITS_MCDX[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDX)/sizeof(mmMC_HUB_WDP_CREDITS_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDY", REG_MMIO, 0xdf5, &mmMC_HUB_WDP_CREDITS_MCDY[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDY)/sizeof(mmMC_HUB_WDP_CREDITS_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDZ", REG_MMIO, 0xdf6, &mmMC_HUB_WDP_CREDITS_MCDZ[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDZ)/sizeof(mmMC_HUB_WDP_CREDITS_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDS", REG_MMIO, 0xdf7, &mmMC_HUB_WDP_CREDITS_MCDS[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDS)/sizeof(mmMC_HUB_WDP_CREDITS_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDT", REG_MMIO, 0xdf8, &mmMC_HUB_WDP_CREDITS_MCDT[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDT)/sizeof(mmMC_HUB_WDP_CREDITS_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDU", REG_MMIO, 0xdf9, &mmMC_HUB_WDP_CREDITS_MCDU[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDU)/sizeof(mmMC_HUB_WDP_CREDITS_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDV", REG_MMIO, 0xdfa, &mmMC_HUB_WDP_CREDITS_MCDV[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDV)/sizeof(mmMC_HUB_WDP_CREDITS_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BP2", REG_MMIO, 0xdfb, &mmMC_HUB_WDP_BP2[0], sizeof(mmMC_HUB_WDP_BP2)/sizeof(mmMC_HUB_WDP_BP2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_14", REG_SMC, 0xe, &ixMC_IO_DEBUG_UP_14[0], sizeof(ixMC_IO_DEBUG_UP_14)/sizeof(ixMC_IO_DEBUG_UP_14[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_OFSCAL_D0", REG_SMC, 0xe0, &ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_OFSCAL_D0", REG_SMC, 0xe1, &ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_OFSCAL_D0", REG_SMC, 0xe2, &ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_OFSCAL_D0", REG_SMC, 0xe3, &ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_OFSCAL_D0", REG_SMC, 0xe4, &ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_OFSCAL_D0", REG_SMC, 0xe5, &ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_OFSCAL_D0", REG_SMC, 0xe6, &ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_OFSCAL_D0", REG_SMC, 0xe7, &ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_OFSCAL_D0", REG_SMC, 0xe8, &ixMC_IO_DEBUG_DBI_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_OFSCAL_D0", REG_SMC, 0xe9, &ixMC_IO_DEBUG_EDC_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_OFSCAL_D0", REG_SMC, 0xea, &ixMC_IO_DEBUG_WCK_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0", REG_SMC, 0xeb, &ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0", REG_SMC, 0xec, &ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0", REG_SMC, 0xed, &ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_OFSCAL_D0", REG_SMC, 0xee, &ixMC_IO_DEBUG_ACMD_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_OFSCAL_D0", REG_SMC, 0xef, &ixMC_IO_DEBUG_CMD_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_15", REG_SMC, 0xf, &ixMC_IO_DEBUG_UP_15[0], sizeof(ixMC_IO_DEBUG_UP_15)/sizeof(ixMC_IO_DEBUG_UP_15[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_OFSCAL_D1", REG_SMC, 0xf0, &ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_OFSCAL_D1", REG_SMC, 0xf1, &ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_OFSCAL_D1", REG_SMC, 0xf2, &ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_OFSCAL_D1", REG_SMC, 0xf3, &ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_OFSCAL_D1", REG_SMC, 0xf4, &ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_OFSCAL_D1", REG_SMC, 0xf5, &ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_OFSCAL_D1", REG_SMC, 0xf6, &ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_OFSCAL_D1", REG_SMC, 0xf7, &ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_OFSCAL_D1", REG_SMC, 0xf8, &ixMC_IO_DEBUG_DBI_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_OFSCAL_D1", REG_SMC, 0xf9, &ixMC_IO_DEBUG_EDC_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_OFSCAL_D1", REG_SMC, 0xfa, &ixMC_IO_DEBUG_WCK_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1", REG_SMC, 0xfb, &ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1", REG_SMC, 0xfc, &ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1", REG_SMC, 0xfd, &ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_OFSCAL_D1", REG_SMC, 0xfe, &ixMC_IO_DEBUG_ACMD_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_OFSCAL_D1", REG_SMC, 0xff, &ixMC_IO_DEBUG_CMD_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D1[0]), 0, 0 },
diff --git a/src/lib/ip/gmc81.c b/src/lib/ip/gmc81.c
new file mode 100644
index 0000000..2c98857
--- /dev/null
+++ b/src/lib/ip/gmc81.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gmc81_bits.i"
+static const struct umr_reg gmc81_registers[] = {
+#include "gmc81_regs.i"
+};
+
+struct umr_ip_block *umr_create_gmc81(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gmc81";
+	ip->no_regs = sizeof(gmc81_registers)/sizeof(gmc81_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gmc81_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, gmc81_registers, sizeof(gmc81_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gmc81_bits.i b/src/lib/ip/gmc81_bits.i
new file mode 100644
index 0000000..8fdf177
--- /dev/null
+++ b/src/lib/ip/gmc81_bits.i
@@ -0,0 +1,10959 @@
+static struct umr_bitfield ixMC_TSM_DEBUG_GCNT[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_FLAG[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_ST01[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_ST23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_ST45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BKPT[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_20[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_21[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_22[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_23[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_24[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_25[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_26[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_27[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_28[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_29[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_30[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXPHASE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXSLF_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_31[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXPHASE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXSLF_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_MISC[] = {
+	 { "FLAG", 0, 7, &umr_bitfield_default },
+	 { "NCNT_RD", 8, 11, &umr_bitfield_default },
+	 { "NCNT_WR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_2[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_32[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_33[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_34[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_35[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_36[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_37[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_38[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_39[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_40[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_41[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_42[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_43[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_44[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_45[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_46[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_47[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT0[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_3[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_48[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_49[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_50[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_51[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_52[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_53[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_54[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_55[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_56[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_57[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_58[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_59[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_60[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_61[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_62[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_63[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT1[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_4[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_64[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_65[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_66[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_67[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_68[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_69[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_70[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_71[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_72[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_73[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_74[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_75[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_76[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_77[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_78[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_79[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT2[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_5[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_80[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL[] = {
+	 { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default },
+	 { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default },
+	 { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default },
+	 { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default },
+	 { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default },
+	 { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default },
+	 { "L2_CACHE_4K_SWAP_TAG_INDEX_LSBS", 26, 27, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL2[] = {
+	 { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_VMID_MODE", 23, 25, &umr_bitfield_default },
+	 { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default },
+	 { "PDE_CACHE_EFFECTIVE_SIZE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL3[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default },
+	 { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default },
+	 { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default },
+	 { "PDE_CACHE_FORCE_MISS", 30, 30, &umr_bitfield_default },
+	 { "L2_CACHE_4K_ASSOCIATIVITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_STATUS[] = {
+	 { "L2_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = {
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = {
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = {
+	 { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default },
+	 { "DUMMY_PAGE_COMPARE_MASK", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR[] = {
+	 { "DUMMY_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL2[] = {
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL2[] = {
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_81[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_REQUEST[] = {
+	 { "INVALIDATE_DOMAIN_0", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_1", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_2", 2, 2, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_3", 3, 3, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_4", 4, 4, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_5", 5, 5, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_6", 6, 6, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_7", 7, 7, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_8", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_9", 9, 9, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_10", 10, 10, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_11", 11, 11, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_12", 12, 12, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_13", 13, 13, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_14", 14, 14, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_RESPONSE[] = {
+	 { "DOMAIN_INVALIDATED_0", 0, 0, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_1", 1, 1, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_2", 2, 2, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_3", 3, 3, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_4", 4, 4, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_5", 5, 5, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_6", 6, 6, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_7", 7, 7, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_8", 8, 8, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_9", 9, 9, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_10", 10, 10, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_11", 11, 11, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_12", 12, 12, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_13", 13, 13, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_14", 14, 14, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_82[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_83[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_CNTL[] = {
+	 { "CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS", 0, 0, &umr_bitfield_default },
+	 { "TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_STORE_INVALID_ENTRIES", 2, 2, &umr_bitfield_default },
+	 { "L1_TLB_STORE_INVALID_ENTRIES", 3, 3, &umr_bitfield_default },
+	 { "CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS", 4, 4, &umr_bitfield_default },
+	 { "TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+	 { "MASK_PDE0_FAULT", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = {
+	 { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 20, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+	 { "ATOMIC", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 20, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+	 { "ATOMIC", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[] = {
+	 { "NAME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[] = {
+	 { "NAME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_84[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_FAULT_CLIENT_ID[] = {
+	 { "MEMORY_CLIENT", 0, 8, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_MASK", 9, 17, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID_MSB", 18, 18, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID_MASK_MSB", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_85[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_86[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DEBUG[] = {
+	 { "FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_87[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CG[] = {
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OVERRIDE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKA[] = {
+	 { "BANK_SELECT_MASK", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKB[] = {
+	 { "BANK_SELECT_MASK", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[] = {
+	 { "PHYSICAL_PAGE_OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL4[] = {
+	 { "L2_CACHE_4K_PARTITION_COUNT", 0, 5, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL", 6, 6, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED", 7, 7, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP", 8, 8, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL", 9, 9, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED", 10, 10, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP", 11, 11, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL", 12, 12, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED", 13, 13, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP", 14, 14, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL", 15, 15, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED", 16, 16, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP", 17, 17, &umr_bitfield_default },
+	 { "L2_CACHE_4K_LRU_ADDR_MATCHING", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID[] = {
+	 { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default },
+	 { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default },
+	 { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID2[] = {
+	 { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default },
+	 { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default },
+	 { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_88[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_89[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_90[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_91[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_92[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_93[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_94[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUFMGR_SW_CONTROL[] = {
+	 { "MCIF_WB_BUFMGR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_DUALSIZE_REQ", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_INT_ACK", 5, 5, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_LOCK", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_P_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUFMGR_CUR_LINE_R[] = {
+	 { "MCIF_WB_BUFMGR_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUFMGR_STATUS[] = {
+	 { "MCIF_WB_BUFMGR_VCE_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_CUR_BUF", 4, 6, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_DUALSIZE_STATUS", 7, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_CUR_LINE_L", 12, 24, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_NEXT_BUF", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_PITCH[] = {
+	 { "MCIF_WB_BUF_LUMA_PITCH", 8, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_CHROMA_PITCH", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_STATUS[] = {
+	 { "MCIF_WB_BUF_1_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_VCE_LOCKED", 2, 2, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_MODE", 5, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_FIELD", 15, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_CUR_LINE_L", 16, 28, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_STATUS2[] = {
+	 { "MCIF_WB_BUF_1_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_NEW_CONTENT", 13, 13, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_STATUS[] = {
+	 { "MCIF_WB_BUF_2_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_VCE_LOCKED", 2, 2, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_MODE", 5, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_FIELD", 15, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_CUR_LINE_L", 16, 28, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_STATUS2[] = {
+	 { "MCIF_WB_BUF_2_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_NEW_CONTENT", 13, 13, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_STATUS[] = {
+	 { "MCIF_WB_BUF_3_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_VCE_LOCKED", 2, 2, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_MODE", 5, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_FIELD", 15, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_CUR_LINE_L", 16, 28, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_STATUS2[] = {
+	 { "MCIF_WB_BUF_3_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_NEW_CONTENT", 13, 13, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_STATUS[] = {
+	 { "MCIF_WB_BUF_4_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_VCE_LOCKED", 2, 2, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_MODE", 5, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_FIELD", 15, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_CUR_LINE_L", 16, 28, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_STATUS2[] = {
+	 { "MCIF_WB_BUF_4_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_NEW_CONTENT", 13, 13, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_ARBITRATION_CONTROL[] = {
+	 { "MCIF_WB_CLIENT_ARBITRATION_SLICE", 0, 1, &umr_bitfield_default },
+	 { "MCIF_WB_TIME_PER_PIXEL", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_URGENCY_WATERMARK[] = {
+	 { "MCIF_WB_CLIENT0_URGENCY_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "MCIF_WB_CLIENT1_URGENCY_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_TEST_DEBUG_INDEX[] = {
+	 { "MCIF_WB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MCIF_WB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_TEST_DEBUG_DATA[] = {
+	 { "MCIF_WB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_ADDR_Y[] = {
+	 { "MCIF_WB_BUF_1_ADDR_Y", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_ADDR_Y_OFFSET[] = {
+	 { "MCIF_WB_BUF_1_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_ADDR_C[] = {
+	 { "MCIF_WB_BUF_1_ADDR_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_ADDR_C_OFFSET[] = {
+	 { "MCIF_WB_BUF_1_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_ADDR_Y[] = {
+	 { "MCIF_WB_BUF_2_ADDR_Y", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_ADDR_Y_OFFSET[] = {
+	 { "MCIF_WB_BUF_2_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_ADDR_C[] = {
+	 { "MCIF_WB_BUF_2_ADDR_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_ADDR_C_OFFSET[] = {
+	 { "MCIF_WB_BUF_2_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_ADDR_Y[] = {
+	 { "MCIF_WB_BUF_3_ADDR_Y", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_ADDR_Y_OFFSET[] = {
+	 { "MCIF_WB_BUF_3_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_ADDR_C[] = {
+	 { "MCIF_WB_BUF_3_ADDR_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_ADDR_C_OFFSET[] = {
+	 { "MCIF_WB_BUF_3_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_ADDR_Y[] = {
+	 { "MCIF_WB_BUF_4_ADDR_Y", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_ADDR_Y_OFFSET[] = {
+	 { "MCIF_WB_BUF_4_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_ADDR_C[] = {
+	 { "MCIF_WB_BUF_4_ADDR_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_ADDR_C_OFFSET[] = {
+	 { "MCIF_WB_BUF_4_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUFMGR_VCE_CONTROL[] = {
+	 { "MCIF_WB_BUFMGR_VCE_LOCK_IGNORE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_VCE_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_VCE_INT_ACK", 5, 5, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_VCE_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_VCE_LOCK", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SLICE_SIZE", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_HVVMID_CONTROL[] = {
+	 { "MCIF_WB_DEFAULT_VMID", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_ALLOWED_VMID_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_95[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT3[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_6[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_96[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_97[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_98[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_99[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_100[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_101[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_102[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_103[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_104[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_105[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_106[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_107[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_108[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_109[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_110[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_111[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT4[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_7[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_112[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_113[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_114[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_115[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_116[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_117[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_118[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_119[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_120[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_121[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_122[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_123[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_124[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_125[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_126[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_127[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT5[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_8[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_128[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG[] = {
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCDS_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCDT_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCDU_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCDV_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MCC_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHMAP[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "NOOFCHAN", 12, 15, &umr_bitfield_default },
+	 { "CHAN3", 16, 19, &umr_bitfield_default },
+	 { "CHAN4", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHREMAP[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "CHAN3", 12, 15, &umr_bitfield_default },
+	 { "CHAN4", 16, 19, &umr_bitfield_default },
+	 { "CHAN5", 20, 23, &umr_bitfield_default },
+	 { "CHAN6", 24, 27, &umr_bitfield_default },
+	 { "CHAN7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "SH", 4, 7, &umr_bitfield_default },
+	 { "TLS", 8, 11, &umr_bitfield_default },
+	 { "ACPG", 12, 15, &umr_bitfield_default },
+	 { "ACPO", 16, 19, &umr_bitfield_default },
+	 { "XDMAM", 20, 23, &umr_bitfield_default },
+	 { "ISP", 24, 27, &umr_bitfield_default },
+	 { "VP8", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_GFX[] = {
+	 { "VIN0", 0, 3, &umr_bitfield_default },
+	 { "SH", 4, 7, &umr_bitfield_default },
+	 { "ACPG", 8, 11, &umr_bitfield_default },
+	 { "ACPO", 12, 15, &umr_bitfield_default },
+	 { "ISP", 16, 19, &umr_bitfield_default },
+	 { "VP8", 20, 23, &umr_bitfield_default },
+	 { "XDMA", 24, 27, &umr_bitfield_default },
+	 { "XDMAM", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_SYS[] = {
+	 { "RLC", 0, 3, &umr_bitfield_default },
+	 { "VMC", 4, 7, &umr_bitfield_default },
+	 { "SDMA1", 8, 11, &umr_bitfield_default },
+	 { "DMIF", 12, 15, &umr_bitfield_default },
+	 { "MCIF", 16, 19, &umr_bitfield_default },
+	 { "SMU", 20, 23, &umr_bitfield_default },
+	 { "VCE0", 24, 27, &umr_bitfield_default },
+	 { "VCE1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_SYS[] = {
+	 { "IH", 0, 3, &umr_bitfield_default },
+	 { "MCIF", 4, 7, &umr_bitfield_default },
+	 { "RLC", 8, 11, &umr_bitfield_default },
+	 { "SAMMSP", 12, 15, &umr_bitfield_default },
+	 { "SMU", 16, 19, &umr_bitfield_default },
+	 { "SDMA1", 20, 23, &umr_bitfield_default },
+	 { "VCE0", 24, 27, &umr_bitfield_default },
+	 { "VCE1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_OTH[] = {
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "SDMA0", 4, 7, &umr_bitfield_default },
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "UVD_EXT1", 24, 27, &umr_bitfield_default },
+	 { "SAMMSP", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_OTH[] = {
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "SDMA0", 4, 7, &umr_bitfield_default },
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "XDP", 24, 27, &umr_bitfield_default },
+	 { "UVD_EXT1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_LOCATION[] = {
+	 { "FB_BASE", 0, 15, &umr_bitfield_default },
+	 { "FB_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_TOP[] = {
+	 { "AGP_TOP", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BOT[] = {
+	 { "AGP_BOT", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BASE[] = {
+	 { "AGP_BASE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_129[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_CNTL[] = {
+	 { "DC_WRITE_HIT_REGION_0_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_1_MODE", 2, 3, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_2_MODE", 4, 5, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_3_MODE", 6, 7, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_LOCAL", 8, 8, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_SYSTEM", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = {
+	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L1_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
+	 { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default },
+	 { "ECO_BITS", 7, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_OFFSET[] = {
+	 { "FB_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_STEERING[] = {
+	 { "DEFAULT_STEERING", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHREMAP2[] = {
+	 { "CHAN8", 0, 3, &umr_bitfield_default },
+	 { "CHAN9", 4, 7, &umr_bitfield_default },
+	 { "CHAN10", 8, 11, &umr_bitfield_default },
+	 { "CHAN11", 12, 15, &umr_bitfield_default },
+	 { "CHAN12", 16, 19, &umr_bitfield_default },
+	 { "CHAN13", 20, 23, &umr_bitfield_default },
+	 { "CHAN14", 24, 27, &umr_bitfield_default },
+	 { "CHAN15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_ACTIVE_FCN_ID[] = {
+	 { "VFID", 0, 3, &umr_bitfield_default },
+	 { "VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_130[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCD6_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCD7_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MC_RD_ENABLE_SUB", 11, 11, &umr_bitfield_default },
+	 { "ARB0_WR_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "ARB1_WR_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "MCD_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCD6_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCD7_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MC_RD_ENABLE_SUB", 11, 11, &umr_bitfield_default },
+	 { "INDEX", 13, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MEM_POWER_LS[] = {
+	 { "LS_SETUP", 0, 5, &umr_bitfield_default },
+	 { "LS_HOLD", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_BLACKOUT_CNTL[] = {
+	 { "BLACKOUT_MODE", 0, 2, &umr_bitfield_default },
+	 { "BLACKOUT_SEQ_FREE", 3, 3, &umr_bitfield_default },
+	 { "BLACKOUT_MCD_NUM", 4, 11, &umr_bitfield_default },
+	 { "FREE_TIE_HIGH", 12, 12, &umr_bitfield_default },
+	 { "SRBM_DUMMY_READ_RETURN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_POWER[] = {
+	 { "SRBM_GATE_OVERRIDE", 2, 2, &umr_bitfield_default },
+	 { "PM_BLACKOUT_CNTL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_HUB_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_VM_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_131[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_SIP_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_STATUS[] = {
+	 { "OUTSTANDING_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_ATOMIC", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDREQ", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDRET", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRREQ", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRRET", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_ATOMIC_REQ", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_ATOMIC_RET", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_READ", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_WRITE", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_ATOMIC", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_READ", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_WRITE", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_ATOMIC", 14, 14, &umr_bitfield_default },
+	 { "RPB_BUSY", 15, 15, &umr_bitfield_default },
+	 { "WRITE_DEADLOCK_WARNING", 16, 16, &umr_bitfield_default },
+	 { "READ_DEADLOCK_WARNING", 17, 17, &umr_bitfield_default },
+	 { "ATOMIC_DEADLOCK_WARNING", 18, 18, &umr_bitfield_default },
+	 { "GFX_BUSY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_OVERRIDE[] = {
+	 { "IDLE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_FRAMING[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CNTL[] = {
+	 { "JUMPAHEAD_GBL0", 1, 1, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_INTERNAL", 3, 3, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_REG", 5, 12, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_INTERNAL", 15, 15, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 16, 16, &umr_bitfield_default },
+	 { "LCLWRREQ_BYPASS", 17, 17, &umr_bitfield_default },
+	 { "DISP_WAIT_EOP", 18, 18, &umr_bitfield_default },
+	 { "MCD_WAIT_EOP", 19, 19, &umr_bitfield_default },
+	 { "SIP_WAIT_EOP", 20, 20, &umr_bitfield_default },
+	 { "UVD_VCE_WRITE_PRI_EN", 21, 21, &umr_bitfield_default },
+	 { "WRITE_PRI_EN", 22, 22, &umr_bitfield_default },
+	 { "IH_PHYSADDR_ENABLE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ERR[] = {
+	 { "MGPU1_TARG_SYS", 0, 0, &umr_bitfield_default },
+	 { "MGPU2_TARG_SYS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RDRET", 1, 17, &umr_bitfield_default },
+	 { "WRREQ", 18, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_STATUS[] = {
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDS_RD_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDT_RD_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDU_RD_AVAIL", 7, 7, &umr_bitfield_default },
+	 { "MCDV_RD_AVAIL", 8, 8, &umr_bitfield_default },
+	 { "MCDW_WR_AVAIL", 9, 9, &umr_bitfield_default },
+	 { "MCDX_WR_AVAIL", 10, 10, &umr_bitfield_default },
+	 { "MCDY_WR_AVAIL", 11, 11, &umr_bitfield_default },
+	 { "MCDZ_WR_AVAIL", 12, 12, &umr_bitfield_default },
+	 { "MCDS_WR_AVAIL", 13, 13, &umr_bitfield_default },
+	 { "MCDT_WR_AVAIL", 14, 14, &umr_bitfield_default },
+	 { "MCDU_WR_AVAIL", 15, 15, &umr_bitfield_default },
+	 { "MCDV_WR_AVAIL", 16, 16, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 17, 17, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 18, 18, &umr_bitfield_default },
+	 { "GBL0_BYPASS_STOR_FULL", 19, 19, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 20, 20, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 21, 21, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_STATUS[] = {
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDS_RD_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDT_RD_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDU_RD_AVAIL", 7, 7, &umr_bitfield_default },
+	 { "MCDV_RD_AVAIL", 8, 8, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 9, 9, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 10, 10, &umr_bitfield_default },
+	 { "GBL0_BYPASS_STOR_FULL", 11, 11, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 12, 12, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 13, 13, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 14, 14, &umr_bitfield_default },
+	 { "PWRXPRESS_ERR", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_STATUS[] = {
+	 { "MCDW_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDX_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDY_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDS_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDT_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDU_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDV_AVAIL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CNTL[] = {
+	 { "REMOTE_BLACKOUT", 0, 0, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL0", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 3, 3, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCDW_STALL_MODE", 5, 5, &umr_bitfield_default },
+	 { "MCDX_STALL_MODE", 6, 6, &umr_bitfield_default },
+	 { "MCDY_STALL_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCDZ_STALL_MODE", 8, 8, &umr_bitfield_default },
+	 { "MCDS_STALL_MODE", 9, 9, &umr_bitfield_default },
+	 { "MCDT_STALL_MODE", 10, 10, &umr_bitfield_default },
+	 { "MCDU_STALL_MODE", 11, 11, &umr_bitfield_default },
+	 { "MCDV_STALL_MODE", 12, 12, &umr_bitfield_default },
+	 { "BREAK_HDP_DEADLOCK", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_REG", 14, 20, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 22, 22, &umr_bitfield_default },
+	 { "PWRXPRESS_MODE", 23, 23, &umr_bitfield_default },
+	 { "ACPG_HP_TO_MCD_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "GBL0_PRI_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "UVD_TRANSCODE_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "DMIF_URG_THRESHOLD", 27, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_CNTL[] = {
+	 { "JUMPAHEAD", 0, 0, &umr_bitfield_default },
+	 { "BP", 1, 20, &umr_bitfield_default },
+	 { "BP_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_REG", 22, 29, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 30, 30, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS[] = {
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_132[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS2[] = {
+	 { "STOR0_PRI", 0, 7, &umr_bitfield_default },
+	 { "STOR1_PRI", 8, 15, &umr_bitfield_default },
+	 { "VM2", 16, 23, &umr_bitfield_default },
+	 { "VM3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL0[] = {
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 17, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_URG", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL1[] = {
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 17, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_URG", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS3[] = {
+	 { "STOR0_URG", 0, 7, &umr_bitfield_default },
+	 { "STOR1_URG", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS[] = {
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS2[] = {
+	 { "STOR0_PRI", 0, 7, &umr_bitfield_default },
+	 { "STOR1_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_SHARED_DAGB_DLY[] = {
+	 { "DLY", 0, 5, &umr_bitfield_default },
+	 { "CLI", 16, 21, &umr_bitfield_default },
+	 { "POS", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_IDLE_STATUS[] = {
+	 { "OUTSTANDING_GFX_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_GFX_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_READ", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_WRITE", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_READ", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_WRITE", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_READ", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_WRITE", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_READ", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_WRITE", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_READ", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_WRITE", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_READ", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_WRITE", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_READ", 14, 14, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_WRITE", 15, 15, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_READ", 16, 16, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_WRITE", 17, 17, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_READ", 18, 18, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_WRITE", 19, 19, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_READ", 20, 20, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_WRITE", 21, 21, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_READ", 22, 22, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_WRITE", 23, 23, &umr_bitfield_default },
+	 { "OUTSTANDING_SAMMSP_READ", 24, 24, &umr_bitfield_default },
+	 { "OUTSTANDING_SAMMSP_WRITE", 25, 25, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_READ", 26, 26, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_WRITE", 27, 27, &umr_bitfield_default },
+	 { "OUTSTANDING_ISP_READ", 28, 28, &umr_bitfield_default },
+	 { "OUTSTANDING_ISP_WRITE", 29, 29, &umr_bitfield_default },
+	 { "OUTSTANDING_VP8_READ", 30, 30, &umr_bitfield_default },
+	 { "OUTSTANDING_VP8_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPG_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BYPASS_GBL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+	 { "HDP_PRIORITY_TIME", 17, 23, &umr_bitfield_default },
+	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BYPASS_GBL1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+	 { "HDP_PRIORITY_TIME", 17, 23, &umr_bitfield_default },
+	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_BYPASS_GBL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH3[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_ATOMIC_IDLE_STATUS[] = {
+	 { "OUTSTANDING_GFX_ATOMIC", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_ATOMIC", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_ATOMIC", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_ATOMIC", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_ATOMIC", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_ATOMIC", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_ATOMIC", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_ATOMIC", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_ATOMIC", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_ATOMIC", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_ATOMIC", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_ATOMIC", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_SAMMSP_ATOMIC", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_ATOMIC", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_ISP_ATOMIC", 14, 14, &umr_bitfield_default },
+	 { "OUTSTANDING_VP8_ATOMIC", 15, 15, &umr_bitfield_default },
+	 { "OUTSTANDING_VIN0_READ", 16, 16, &umr_bitfield_default },
+	 { "OUTSTANDING_VIN0_WRITE", 17, 17, &umr_bitfield_default },
+	 { "OUTSTANDING_VIN0_ATOMIC", 18, 18, &umr_bitfield_default },
+	 { "OUTSTANDING_TLS_READ", 19, 19, &umr_bitfield_default },
+	 { "OUTSTANDING_TLS_WRITE", 20, 20, &umr_bitfield_default },
+	 { "OUTSTANDING_TLS_ATOMIC", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_133[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VIN0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDW[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDX[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDY[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDZ[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SIP[] = {
+	 { "ASK_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "MED_CREDIT_SEL", 7, 7, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL0[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL1[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SMU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SDMA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_HDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SDMA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_RLC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SEM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCE0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_134[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UVD[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_TLS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCEU0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDW[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDX[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDY[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDZ[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SIP[] = {
+	 { "STALL_MODE", 0, 1, &umr_bitfield_default },
+	 { "ASK_CREDITS", 2, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SDMA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCE0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_135[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_IH[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_RLC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SEM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SMU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UVD[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_HDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SDMA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDW[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDX[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDY[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDZ[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCEU0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMA[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_136[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_XDMAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPO[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SAMMSP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VP8[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VP8U[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ACPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ACPO[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SAMMSP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VP8[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VP8U[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_137[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB1_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_138[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_139[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_140[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_141[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR4[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR5[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR6[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR7[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR8[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR9[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP0[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP1[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP2[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP3[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP4[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_142[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP5[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP6[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP7[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP8[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP9[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP0[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP1[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP2[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP3[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG0[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG1[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG2[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG3[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG4[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG5[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG6[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_143[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG7[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG8[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG9[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG10[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG11[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG12[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG13[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG14[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG15[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG16[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG17[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG18[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG19[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_LB_ADDR[] = {
+	 { "CMP0", 0, 9, &umr_bitfield_default },
+	 { "MASK0", 10, 19, &umr_bitfield_default },
+	 { "CMP1", 20, 25, &umr_bitfield_default },
+	 { "MASK1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_HST[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT6[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_9[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_144[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_SID[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_STS[] = {
+	 { "PBUF_VLD", 0, 15, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 16, 22, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 23, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_CFG[] = {
+	 { "TIMEOUT", 0, 15, &umr_bitfield_default },
+	 { "HST_MAX", 16, 17, &umr_bitfield_default },
+	 { "SID_MAX", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_CFG[] = {
+	 { "ADDR_SIZE", 0, 3, &umr_bitfield_default },
+	 { "SEND_BAR", 4, 5, &umr_bitfield_default },
+	 { "SNOOP", 6, 6, &umr_bitfield_default },
+	 { "SEND_DIS", 7, 7, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 8, 8, &umr_bitfield_default },
+	 { "UPDATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "REGBAR_FROM_SYSBAR", 10, 10, &umr_bitfield_default },
+	 { "RD_EN", 11, 11, &umr_bitfield_default },
+	 { "ATC_TRANSLATED", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR0[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR1[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR2[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR3[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR4[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR5[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR6[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR7[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_SETUP[] = {
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DEBUG[] = {
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "HOST_FLUSH", 8, 11, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_ABOVE[] = {
+	 { "EN", 0, 7, &umr_bitfield_default },
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_BELOW[] = {
+	 { "EN", 0, 7, &umr_bitfield_default },
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_145[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR4[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR5[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR6[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR7[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR8[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR9[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLK_GAT[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG[] = {
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "MC_WRRET_ASK", 8, 15, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 16, 22, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_SEL", 23, 23, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_VAL", 24, 24, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_SEL", 25, 25, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_VAL", 26, 26, &umr_bitfield_default },
+	 { "XSP_SNOOP_SEL", 27, 28, &umr_bitfield_default },
+	 { "XSP_SNOOP_VAL", 29, 29, &umr_bitfield_default },
+	 { "XSP_ORDERING_SEL", 30, 30, &umr_bitfield_default },
+	 { "XSP_ORDERING_VAL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_146[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_STS[] = {
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 8, 14, &umr_bitfield_default },
+	 { "HOP_DATA_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "HOP_ATTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "CNS_BUF_FULL", 17, 17, &umr_bitfield_default },
+	 { "CNS_BUF_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RPB_RDREQ_CRD", 19, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PIPE_STS[] = {
+	 { "WCB_ANY_PBUF", 0, 0, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 1, 7, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 8, 14, &umr_bitfield_default },
+	 { "WCB_HST_RD_PTR_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "WCB_SID_RD_PTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "WCB_HST_REQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "WCB_SID_REQ_FIFO_FULL", 18, 18, &umr_bitfield_default },
+	 { "WCB_HST_REQ_OBUF_FULL", 19, 19, &umr_bitfield_default },
+	 { "WCB_SID_REQ_OBUF_FULL", 20, 20, &umr_bitfield_default },
+	 { "WCB_HST_DATA_OBUF_FULL", 21, 21, &umr_bitfield_default },
+	 { "WCB_SID_DATA_OBUF_FULL", 22, 22, &umr_bitfield_default },
+	 { "RET_BUF_FULL", 23, 23, &umr_bitfield_default },
+	 { "XPB_CLK_BUSY_BITS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_SUB_CTRL[] = {
+	 { "WRREQ_BYPASS_XPB", 0, 0, &umr_bitfield_default },
+	 { "STALL_CNS_RTR_REQ", 1, 1, &umr_bitfield_default },
+	 { "STALL_RTR_RPB_WRREQ", 2, 2, &umr_bitfield_default },
+	 { "STALL_RTR_MAP_REQ", 3, 3, &umr_bitfield_default },
+	 { "STALL_MAP_WCB_REQ", 4, 4, &umr_bitfield_default },
+	 { "STALL_WCB_SID_REQ", 5, 5, &umr_bitfield_default },
+	 { "STALL_MC_XSP_REQ_SEND", 6, 6, &umr_bitfield_default },
+	 { "STALL_WCB_HST_REQ", 7, 7, &umr_bitfield_default },
+	 { "STALL_HST_HOP_REQ", 8, 8, &umr_bitfield_default },
+	 { "STALL_XPB_RPB_REQ_ATTR", 9, 9, &umr_bitfield_default },
+	 { "RESET_CNS", 10, 10, &umr_bitfield_default },
+	 { "RESET_RTR", 11, 11, &umr_bitfield_default },
+	 { "RESET_RET", 12, 12, &umr_bitfield_default },
+	 { "RESET_MAP", 13, 13, &umr_bitfield_default },
+	 { "RESET_WCB", 14, 14, &umr_bitfield_default },
+	 { "RESET_HST", 15, 15, &umr_bitfield_default },
+	 { "RESET_HOP", 16, 16, &umr_bitfield_default },
+	 { "RESET_SID", 17, 17, &umr_bitfield_default },
+	 { "RESET_SRB", 18, 18, &umr_bitfield_default },
+	 { "RESET_CGR", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[] = {
+	 { "ALTER_FLUSH_NUM", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PERF_KNOBS[] = {
+	 { "CNS_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+	 { "WCB_HST_FIFO_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "WCB_SID_FIFO_DEPTH", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY_W1C[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MISC_CFG[] = {
+	 { "FIELDNAME0", 0, 7, &umr_bitfield_default },
+	 { "FIELDNAME1", 8, 15, &umr_bitfield_default },
+	 { "FIELDNAME2", 16, 23, &umr_bitfield_default },
+	 { "FIELDNAME3", 24, 30, &umr_bitfield_default },
+	 { "TRIGGERNAME", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG20[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG21[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG22[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG23[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG24[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG25[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG26[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG27[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_147[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG28[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG29[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG30[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG31[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG2[] = {
+	 { "RPB_RDREQ_CRD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA_RD[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG32[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG33[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG34[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG35[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG36[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_148[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CONF[] = {
+	 { "XPB_PCIE_ORDER", 15, 15, &umr_bitfield_default },
+	 { "RPB_RD_PCIE_ORDER", 16, 16, &umr_bitfield_default },
+	 { "RPB_WR_PCIE_ORDER", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_IF_CONF[] = {
+	 { "RPB_BIF_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_WRRET_ASK", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_DBG1[] = {
+	 { "RPB_BIF_OUTSTANDING_RD", 0, 7, &umr_bitfield_default },
+	 { "RPB_BIF_OUTSTANDING_RD_32B", 8, 19, &umr_bitfield_default },
+	 { "DEBUG_BITS", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_149[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_EFF_CNTL[] = {
+	 { "WR_LAZY_TIMER", 0, 7, &umr_bitfield_default },
+	 { "RD_LAZY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_ARB_CNTL[] = {
+	 { "WR_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "RD_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "ATC_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_BIF_CNTL[] = {
+	 { "ARB_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "XPB_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_COMBINE_CNTL[] = {
+	 { "WC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "WC_MAX_PACKET_SIZE", 1, 2, &umr_bitfield_default },
+	 { "WC_FLUSH_TIMER", 3, 6, &umr_bitfield_default },
+	 { "WC_ALIGN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_RD_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_WR[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "UPDATE_MODE", 8, 8, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 9, 10, &umr_bitfield_default },
+	 { "READ_QUEUE", 11, 12, &umr_bitfield_default },
+	 { "UPDATE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_RD[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 8, 9, &umr_bitfield_default },
+	 { "READ_QUEUE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 1, &umr_bitfield_default },
+	 { "CLEAR_SELECTED_PERF_COUNTER", 2, 2, &umr_bitfield_default },
+	 { "CLEAR_ALL_PERF_COUNTERS", 3, 3, &umr_bitfield_default },
+	 { "STOP_ON_COUNTER_SATURATION", 4, 4, &umr_bitfield_default },
+	 { "ENABLE_PERF_COUNTERS", 5, 8, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_0", 9, 13, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_1", 14, 18, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_2", 19, 23, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_3", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_STATUS[] = {
+	 { "PERFORMANCE_COUNTER_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX_DATA[] = {
+	 { "WRITE_ENTRIES", 0, 15, &umr_bitfield_default },
+	 { "READ_ENTRIES", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_TCI_CNTL[] = {
+	 { "TCI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TCI_POLICY", 1, 2, &umr_bitfield_default },
+	 { "TCI_VOL", 3, 3, &umr_bitfield_default },
+	 { "TCI_VMID", 4, 7, &umr_bitfield_default },
+	 { "TCI_REQ_CREDITS", 8, 15, &umr_bitfield_default },
+	 { "TCI_MAX_WRITES", 16, 23, &umr_bitfield_default },
+	 { "TCI_MAX_READS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_TCI_CNTL2[] = {
+	 { "TCI_POLICY", 0, 0, &umr_bitfield_default },
+	 { "TCI_MTYPE", 1, 2, &umr_bitfield_default },
+	 { "TCI_SNOOP", 3, 3, &umr_bitfield_default },
+	 { "TCI_PHYSICAL", 4, 4, &umr_bitfield_default },
+	 { "TCI_PERF_CNTR_EN", 5, 5, &umr_bitfield_default },
+	 { "TCI_EXE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_150[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_XTRA_ENABLE[] = {
+	 { "CB1_RD", 0, 0, &umr_bitfield_default },
+	 { "CB1_WR", 1, 1, &umr_bitfield_default },
+	 { "DB1_RD", 2, 2, &umr_bitfield_default },
+	 { "DB1_WR", 3, 3, &umr_bitfield_default },
+	 { "TC2_RD", 4, 4, &umr_bitfield_default },
+	 { "ARB_DBG", 8, 11, &umr_bitfield_default },
+	 { "TC2_WR", 12, 12, &umr_bitfield_default },
+	 { "CB0_CONNECT_CNTL", 13, 14, &umr_bitfield_default },
+	 { "DB0_CONNECT_CNTL", 15, 16, &umr_bitfield_default },
+	 { "CB1_CONNECT_CNTL", 17, 18, &umr_bitfield_default },
+	 { "DB1_CONNECT_CNTL", 19, 20, &umr_bitfield_default },
+	 { "TC0_CONNECT_CNTL", 21, 22, &umr_bitfield_default },
+	 { "TC1_CONNECT_CNTL", 23, 24, &umr_bitfield_default },
+	 { "CB0_CID_CNTL_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DB0_CID_CNTL_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CB1_CID_CNTL_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "DB1_CID_CNTL_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "TC2_REPAIR_ENABLE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_MC_MAX_CHANNEL[] = {
+	 { "NOOFCHAN", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG[] = {
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
+	 { "INDEX", 6, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_151[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CNTL[] = {
+	 { "IGNOREPM", 2, 2, &umr_bitfield_default },
+	 { "EXEMPTPM", 3, 3, &umr_bitfield_default },
+	 { "GFX_IDLE_OVERRIDE", 4, 5, &umr_bitfield_default },
+	 { "MCD_SRBM_MASK_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "CNTR_CHMAP_MODE", 7, 8, &umr_bitfield_default },
+	 { "REMOTE_RB_CONNECT_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_VM[] = {
+	 { "READ_ALL", 0, 5, &umr_bitfield_default },
+	 { "WRITE_ALL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_RD[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "READ_HUB", 8, 15, &umr_bitfield_default },
+	 { "READ_PRI", 16, 23, &umr_bitfield_default },
+	 { "LCL_PRI", 24, 24, &umr_bitfield_default },
+	 { "HUB_PRI", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_WR[] = {
+	 { "WRITE_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_HUB", 8, 15, &umr_bitfield_default },
+	 { "WRITE_PRI", 16, 23, &umr_bitfield_default },
+	 { "HUB_PRI", 24, 24, &umr_bitfield_default },
+	 { "LCL_PRI", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_CNTL[] = {
+	 { "JUMP_AHEAD", 0, 0, &umr_bitfield_default },
+	 { "CENTER_RD_MAX_BURST", 1, 4, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 5, 5, &umr_bitfield_default },
+	 { "CENTER_WR_MAX_BURST", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS[] = {
+	 { "REMRDRET", 0, 5, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_LP", 12, 17, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_HP", 18, 23, &umr_bitfield_default },
+	 { "CNTR_RD_LCL", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_RET_MODE[] = {
+	 { "INORDER_RD", 0, 0, &umr_bitfield_default },
+	 { "INORDER_WR", 1, 1, &umr_bitfield_default },
+	 { "REMPRI_RD", 2, 2, &umr_bitfield_default },
+	 { "REMPRI_WR", 3, 3, &umr_bitfield_default },
+	 { "LCLPRI_RD", 4, 4, &umr_bitfield_default },
+	 { "LCLPRI_WR", 5, 5, &umr_bitfield_default },
+	 { "RDRET_STALL_EN", 6, 6, &umr_bitfield_default },
+	 { "RDRET_STALL_THRESHOLD", 7, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_DLY[] = {
+	 { "DLY", 0, 4, &umr_bitfield_default },
+	 { "CLI", 16, 21, &umr_bitfield_default },
+	 { "POS", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_REMREQ[] = {
+	 { "READ_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "WRITE_CREDITS", 7, 13, &umr_bitfield_default },
+	 { "CREDITS_ENABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS_WR[] = {
+	 { "CNTR_WR_HUB", 0, 5, &umr_bitfield_default },
+	 { "CNTR_WR_LCL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_RD2[] = {
+	 { "READ_MED", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_RD_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_LOCAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_152[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_WR_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_LOCAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_CB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_DB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_HUB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_CB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_DB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_HUB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_XBAR[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_LCL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_LCL[] = {
+	 { "CB0", 12, 15, &umr_bitfield_default },
+	 { "CBCMASK0", 16, 19, &umr_bitfield_default },
+	 { "CBFMASK0", 20, 23, &umr_bitfield_default },
+	 { "DB0", 24, 27, &umr_bitfield_default },
+	 { "DBHTILE0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_LCL[] = {
+	 { "CB0", 0, 3, &umr_bitfield_default },
+	 { "CBCMASK0", 4, 7, &umr_bitfield_default },
+	 { "CBFMASK0", 8, 11, &umr_bitfield_default },
+	 { "DB0", 12, 15, &umr_bitfield_default },
+	 { "DBHTILE0", 16, 19, &umr_bitfield_default },
+	 { "SX0", 20, 23, &umr_bitfield_default },
+	 { "CBIMMED0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_CNTL2[] = {
+	 { "CID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_153[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_RSLT2[] = {
+	 { "CB_RD_BUSY", 1, 1, &umr_bitfield_default },
+	 { "DB_RD_BUSY", 2, 2, &umr_bitfield_default },
+	 { "TC0_RD_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VC0_RD_BUSY", 4, 4, &umr_bitfield_default },
+	 { "TC1_RD_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VC1_RD_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CB_WR_BUSY", 7, 7, &umr_bitfield_default },
+	 { "DB_WR_BUSY", 8, 8, &umr_bitfield_default },
+	 { "SX_WR_BUSY", 9, 9, &umr_bitfield_default },
+	 { "TC2_RD_BUSY", 10, 10, &umr_bitfield_default },
+	 { "TC0_WR_BUSY", 11, 11, &umr_bitfield_default },
+	 { "TC1_WR_BUSY", 12, 12, &umr_bitfield_default },
+	 { "TC2_WR_BUSY", 13, 13, &umr_bitfield_default },
+	 { "TC0_ATOM_BUSY", 14, 14, &umr_bitfield_default },
+	 { "TC1_ATOM_BUSY", 15, 15, &umr_bitfield_default },
+	 { "TC2_ATOM_BUSY", 16, 16, &umr_bitfield_default },
+	 { "CB_ATOM_BUSY", 17, 17, &umr_bitfield_default },
+	 { "DB_ATOM_BUSY", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_RD_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_WR_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_VM_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_154[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_155[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ATOMIC[] = {
+	 { "TC_GRP", 0, 2, &umr_bitfield_default },
+	 { "TC_GRP_EN", 3, 3, &umr_bitfield_default },
+	 { "SDMA_GRP", 4, 6, &umr_bitfield_default },
+	 { "SDMA_GRP_EN", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING", 8, 15, &umr_bitfield_default },
+	 { "ATOMIC_RTN_GRP", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_CNTL[] = {
+	 { "RESET_RD_GROUP0", 0, 0, &umr_bitfield_default },
+	 { "RESET_RD_GROUP1", 1, 1, &umr_bitfield_default },
+	 { "RESET_RD_GROUP2", 2, 2, &umr_bitfield_default },
+	 { "RESET_RD_GROUP3", 3, 3, &umr_bitfield_default },
+	 { "RESET_RD_GROUP4", 4, 4, &umr_bitfield_default },
+	 { "RESET_RD_GROUP5", 5, 5, &umr_bitfield_default },
+	 { "RESET_RD_GROUP6", 6, 6, &umr_bitfield_default },
+	 { "RESET_RD_GROUP7", 7, 7, &umr_bitfield_default },
+	 { "RESET_WR_GROUP0", 8, 8, &umr_bitfield_default },
+	 { "RESET_WR_GROUP1", 9, 9, &umr_bitfield_default },
+	 { "RESET_WR_GROUP2", 10, 10, &umr_bitfield_default },
+	 { "RESET_WR_GROUP3", 11, 11, &umr_bitfield_default },
+	 { "RESET_WR_GROUP4", 12, 12, &umr_bitfield_default },
+	 { "RESET_WR_GROUP5", 13, 13, &umr_bitfield_default },
+	 { "RESET_WR_GROUP6", 14, 14, &umr_bitfield_default },
+	 { "RESET_WR_GROUP7", 15, 15, &umr_bitfield_default },
+	 { "AGE_LOW_RATE_RD", 16, 18, &umr_bitfield_default },
+	 { "AGE_LOW_RATE_WR", 19, 21, &umr_bitfield_default },
+	 { "TIMER_STALL_RD", 22, 22, &umr_bitfield_default },
+	 { "TIMER_STALL_WR", 23, 23, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT_RD", 24, 24, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT_WR", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_156[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS2[] = {
+	 { "ACP_WR", 0, 7, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_EN_RD", 8, 8, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_EN_WR", 9, 9, &umr_bitfield_default },
+	 { "ACP_RDRET_URG", 10, 10, &umr_bitfield_default },
+	 { "HDP_RDRET_URG", 11, 11, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_MONITOR_RD", 12, 12, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_MONITOR_WR", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_DISP_RDY_RD", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_ACP_RDY_WR", 15, 15, &umr_bitfield_default },
+	 { "RDRET_CREDIT_MED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_FED_CNTL[] = {
+	 { "MODE", 0, 1, &umr_bitfield_default },
+	 { "WR_ERR", 2, 3, &umr_bitfield_default },
+	 { "KEEP_POISON_IN_PAGE", 4, 4, &umr_bitfield_default },
+	 { "RDRET_PARITY_NACK", 5, 5, &umr_bitfield_default },
+	 { "USE_LEGACY_NACK", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_RSV", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_STATUS[] = {
+	 { "CORR_STS0", 0, 0, &umr_bitfield_default },
+	 { "UNCORR_STS0", 1, 1, &umr_bitfield_default },
+	 { "FED_STS0", 2, 2, &umr_bitfield_default },
+	 { "RSVD0", 3, 3, &umr_bitfield_default },
+	 { "CORR_STS1", 4, 4, &umr_bitfield_default },
+	 { "UNCORR_STS1", 5, 5, &umr_bitfield_default },
+	 { "FED_STS1", 6, 6, &umr_bitfield_default },
+	 { "RSVD1", 7, 7, &umr_bitfield_default },
+	 { "CORR_CLEAR0", 8, 8, &umr_bitfield_default },
+	 { "UNCORR_CLEAR0", 9, 9, &umr_bitfield_default },
+	 { "FED_CLEAR0", 10, 10, &umr_bitfield_default },
+	 { "RSVD2", 11, 11, &umr_bitfield_default },
+	 { "CORR_CLEAR1", 12, 12, &umr_bitfield_default },
+	 { "UNCORR_CLEAR1", 13, 13, &umr_bitfield_default },
+	 { "FED_CLEAR1", 14, 14, &umr_bitfield_default },
+	 { "RSVD3", 15, 15, &umr_bitfield_default },
+	 { "RMWRD_CORR_STS0", 16, 16, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_STS0", 17, 17, &umr_bitfield_default },
+	 { "RSVD4", 18, 19, &umr_bitfield_default },
+	 { "RMWRD_CORR_STS1", 20, 20, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_STS1", 21, 21, &umr_bitfield_default },
+	 { "RSVD5", 22, 23, &umr_bitfield_default },
+	 { "RMWRD_CORR_CLEAR0", 24, 24, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_CLEAR0", 25, 25, &umr_bitfield_default },
+	 { "RSVD6", 26, 27, &umr_bitfield_default },
+	 { "RMWRD_CORR_CLEAR1", 28, 28, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_CLEAR1", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_MISC[] = {
+	 { "STREAK_BREAK", 0, 3, &umr_bitfield_default },
+	 { "COL10_HACK", 4, 4, &umr_bitfield_default },
+	 { "CWRD_IN_REPLAY", 5, 5, &umr_bitfield_default },
+	 { "NO_EOB_ALL_WR_IN_REPLAY", 6, 6, &umr_bitfield_default },
+	 { "RMW_LM_WR_STALL", 7, 7, &umr_bitfield_default },
+	 { "RMW_STALL_RELEASE", 8, 8, &umr_bitfield_default },
+	 { "WR_EDC_MASK_REPLAY", 9, 9, &umr_bitfield_default },
+	 { "CWRD_REPLAY_AGAIN", 10, 10, &umr_bitfield_default },
+	 { "WRRDWR_REPLAY_AGAIN", 11, 11, &umr_bitfield_default },
+	 { "ALLOW_RMW_ERR_AFTER_REPLAY", 12, 12, &umr_bitfield_default },
+	 { "DEBUG_RSV", 13, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG[] = {
+	 { "NUM_ERR_BITS", 0, 1, &umr_bitfield_default },
+	 { "DIRECTION", 2, 2, &umr_bitfield_default },
+	 { "DATA_FIELD", 3, 4, &umr_bitfield_default },
+	 { "SW_INJECTION", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG2[] = {
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+	 { "ERR0_START", 8, 15, &umr_bitfield_default },
+	 { "ERR1_START", 16, 23, &umr_bitfield_default },
+	 { "ERR2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERF_CID[] = {
+	 { "CH0", 0, 7, &umr_bitfield_default },
+	 { "CH1", 8, 15, &umr_bitfield_default },
+	 { "CH0_EN", 16, 16, &umr_bitfield_default },
+	 { "CH1_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SNOOP[] = {
+	 { "TC_GRP_RD", 0, 2, &umr_bitfield_default },
+	 { "TC_GRP_RD_EN", 3, 3, &umr_bitfield_default },
+	 { "TC_GRP_WR", 4, 6, &umr_bitfield_default },
+	 { "TC_GRP_WR_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_GRP_RD", 8, 10, &umr_bitfield_default },
+	 { "SDMA_GRP_RD_EN", 11, 11, &umr_bitfield_default },
+	 { "SDMA_GRP_WR", 12, 14, &umr_bitfield_default },
+	 { "SDMA_GRP_WR_EN", 15, 15, &umr_bitfield_default },
+	 { "OUTSTANDING_RD", 16, 23, &umr_bitfield_default },
+	 { "OUTSTANDING_WR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB[] = {
+	 { "GRUB_WATERMARK", 0, 7, &umr_bitfield_default },
+	 { "GRUB_WATERMARK_PRI", 8, 15, &umr_bitfield_default },
+	 { "GRUB_WATERMARK_MED", 16, 23, &umr_bitfield_default },
+	 { "REG_WR_EN", 24, 25, &umr_bitfield_default },
+	 { "REG_RD_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ECC_MODE", 1, 2, &umr_bitfield_default },
+	 { "PAGE_BIT0", 3, 4, &umr_bitfield_default },
+	 { "EXOR_BANK_SEL", 5, 6, &umr_bitfield_default },
+	 { "NO_GECC_CLI", 7, 10, &umr_bitfield_default },
+	 { "READ_ERR", 11, 13, &umr_bitfield_default },
+	 { "CLOSE_BANK_RMW", 14, 14, &umr_bitfield_default },
+	 { "COLFIFO_WATER", 15, 20, &umr_bitfield_default },
+	 { "WRADDR_CONV", 21, 21, &umr_bitfield_default },
+	 { "RMWRD_UNCOR_POISON", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_CLI[] = {
+	 { "NO_GECC_CLI0", 0, 7, &umr_bitfield_default },
+	 { "NO_GECC_CLI1", 8, 15, &umr_bitfield_default },
+	 { "NO_GECC_CLI2", 16, 23, &umr_bitfield_default },
+	 { "NO_GECC_CLI3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_SWIZ0[] = {
+	 { "A8", 0, 3, &umr_bitfield_default },
+	 { "A9", 4, 7, &umr_bitfield_default },
+	 { "A10", 8, 11, &umr_bitfield_default },
+	 { "A11", 12, 15, &umr_bitfield_default },
+	 { "A12", 16, 19, &umr_bitfield_default },
+	 { "A13", 20, 23, &umr_bitfield_default },
+	 { "A14", 24, 27, &umr_bitfield_default },
+	 { "A15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_SWIZ1[] = {
+	 { "A16", 0, 3, &umr_bitfield_default },
+	 { "A17", 4, 7, &umr_bitfield_default },
+	 { "A18", 8, 11, &umr_bitfield_default },
+	 { "A19", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC3[] = {
+	 { "NO_GECC_EXT_EOB", 0, 0, &umr_bitfield_default },
+	 { "CHAN4_EN", 1, 1, &umr_bitfield_default },
+	 { "CHAN4_ARB_SEL", 2, 2, &umr_bitfield_default },
+	 { "UVD_URG_MODE", 3, 3, &umr_bitfield_default },
+	 { "UVD_DMIF_HARSH_WT_EN", 4, 4, &umr_bitfield_default },
+	 { "TBD_FIELD", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PROMOTE[] = {
+	 { "URGENT_RD", 0, 7, &umr_bitfield_default },
+	 { "URGENT_WR", 8, 15, &umr_bitfield_default },
+	 { "PROMOTE_RD", 16, 23, &umr_bitfield_default },
+	 { "PROMOTE_WR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DATA[] = {
+	 { "PATTERN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_157[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "START_IDLE", 1, 1, &umr_bitfield_default },
+	 { "START_R2W", 2, 3, &umr_bitfield_default },
+	 { "FLUSH_ON_ENTER", 4, 4, &umr_bitfield_default },
+	 { "HARSH_START", 5, 5, &umr_bitfield_default },
+	 { "TPS_HARSH_PRIORITY", 6, 6, &umr_bitfield_default },
+	 { "TWRT_HARSH_PRIORITY", 7, 7, &umr_bitfield_default },
+	 { "BREAK_ON_HARSH", 8, 8, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTRD", 9, 9, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTWR", 10, 10, &umr_bitfield_default },
+	 { "TRAIN_PERIOD", 11, 13, &umr_bitfield_default },
+	 { "START_R2W_RFSH", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_RSV_0", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_RSV_1", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_RSV_2", 17, 17, &umr_bitfield_default },
+	 { "DEBUG_RSV_3", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_RSV_4", 19, 19, &umr_bitfield_default },
+	 { "DEBUG_RSV_5", 20, 20, &umr_bitfield_default },
+	 { "DEBUG_RSV_6", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_RSV_7", 22, 22, &umr_bitfield_default },
+	 { "DEBUG_RSV_8", 23, 23, &umr_bitfield_default },
+	 { "DATA_CNTL", 24, 24, &umr_bitfield_default },
+	 { "NEIGHBOR_BIT", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL1[] = {
+	 { "WINDOW_SIZE", 0, 4, &umr_bitfield_default },
+	 { "WINDOW_UPDATE", 5, 5, &umr_bitfield_default },
+	 { "WINDOW_INC_THRESHOLD", 6, 12, &umr_bitfield_default },
+	 { "WINDOW_DEC_THRESHOLD", 13, 19, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MAX", 20, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MIN", 25, 29, &umr_bitfield_default },
+	 { "WINDOW_UPDATE_COUNT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL2[] = {
+	 { "SAMPLE_CNT", 0, 5, &umr_bitfield_default },
+	 { "PHASE_ADJUST_THRESHOLD", 6, 11, &umr_bitfield_default },
+	 { "PHASE_ADJUST_SIZE", 12, 12, &umr_bitfield_default },
+	 { "FILTER_CNTL", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DEBUG[] = {
+	 { "DEBUG_BYTE_CH0", 0, 1, &umr_bitfield_default },
+	 { "DEBUG_BYTE_CH1", 2, 3, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH0", 4, 11, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH0", 12, 16, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH1", 17, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH1", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CAC_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "READ_WEIGHT", 1, 6, &umr_bitfield_default },
+	 { "WRITE_WEIGHT", 7, 12, &umr_bitfield_default },
+	 { "ALLOW_OVERFLOW", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC2[] = {
+	 { "TCCDL4_BANKBIT3_XOR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT4", 6, 6, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT5", 7, 7, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT6", 8, 8, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT7", 9, 9, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT8", 10, 10, &umr_bitfield_default },
+	 { "POP_IDLE_REPLAY", 11, 11, &umr_bitfield_default },
+	 { "RDRET_NO_REORDERING", 12, 12, &umr_bitfield_default },
+	 { "RDRET_NO_BP", 13, 13, &umr_bitfield_default },
+	 { "RDRET_SEQ_SKID", 14, 17, &umr_bitfield_default },
+	 { "GECC", 18, 18, &umr_bitfield_default },
+	 { "GECC_RST", 19, 19, &umr_bitfield_default },
+	 { "GECC_STATUS", 20, 20, &umr_bitfield_default },
+	 { "TAGFIFO_THRESHOLD", 21, 24, &umr_bitfield_default },
+	 { "WCDR_REPLAY_MASKCNT", 25, 27, &umr_bitfield_default },
+	 { "REPLAY_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "ARB_DEBUG29", 29, 29, &umr_bitfield_default },
+	 { "SEQ_RDY_POP_IDLE", 30, 30, &umr_bitfield_default },
+	 { "TCCDL4_REPLAY_EOB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC[] = {
+	 { "STICKY_RFSH", 0, 0, &umr_bitfield_default },
+	 { "IDLE_RFSH", 1, 1, &umr_bitfield_default },
+	 { "STUTTER_RFSH", 2, 2, &umr_bitfield_default },
+	 { "CHAN_COUPLE", 3, 10, &umr_bitfield_default },
+	 { "HARSHNESS", 11, 18, &umr_bitfield_default },
+	 { "SMART_RDWR_SW", 19, 19, &umr_bitfield_default },
+	 { "CALI_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CALI_RATES", 21, 22, &umr_bitfield_default },
+	 { "DISPURGVLD_NOWRT", 23, 23, &umr_bitfield_default },
+	 { "DISPURG_NOSW2WR", 24, 24, &umr_bitfield_default },
+	 { "DISPURG_STALL", 25, 25, &umr_bitfield_default },
+	 { "DISPURG_THROTTLE", 26, 29, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT", 30, 30, &umr_bitfield_default },
+	 { "ACPURG_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BANKMAP[] = {
+	 { "BANK0", 0, 3, &umr_bitfield_default },
+	 { "BANK1", 4, 7, &umr_bitfield_default },
+	 { "BANK2", 8, 11, &umr_bitfield_default },
+	 { "BANK3", 12, 15, &umr_bitfield_default },
+	 { "RANK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RAMCFG[] = {
+	 { "NOOFBANK", 0, 1, &umr_bitfield_default },
+	 { "NOOFRANKS", 2, 2, &umr_bitfield_default },
+	 { "NOOFROWS", 3, 5, &umr_bitfield_default },
+	 { "NOOFCOLS", 6, 7, &umr_bitfield_default },
+	 { "CHANSIZE", 8, 8, &umr_bitfield_default },
+	 { "RSV_1", 9, 9, &umr_bitfield_default },
+	 { "RSV_2", 10, 10, &umr_bitfield_default },
+	 { "RSV_3", 11, 11, &umr_bitfield_default },
+	 { "NOOFGROUPS", 12, 12, &umr_bitfield_default },
+	 { "RSV_4", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_POP[] = {
+	 { "ENABLE_ARB", 0, 0, &umr_bitfield_default },
+	 { "SPEC_OPEN", 1, 1, &umr_bitfield_default },
+	 { "POP_DEPTH", 2, 5, &umr_bitfield_default },
+	 { "WRDATAINDEX_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "SKID_DEPTH", 12, 14, &umr_bitfield_default },
+	 { "WAIT_AFTER_RFSH", 15, 16, &umr_bitfield_default },
+	 { "QUICK_STOP", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_PAGE", 18, 18, &umr_bitfield_default },
+	 { "ALLOW_EOB_BY_WRRET_STALL", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MINCLKS[] = {
+	 { "READ_CLKS", 0, 7, &umr_bitfield_default },
+	 { "WRITE_CLKS", 8, 15, &umr_bitfield_default },
+	 { "ARB_RW_SWITCH", 16, 16, &umr_bitfield_default },
+	 { "RW_SWITCH_HARSH", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SQM_CNTL[] = {
+	 { "MIN_PENAL", 0, 7, &umr_bitfield_default },
+	 { "DYN_SQM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "SQM_RDY16", 9, 9, &umr_bitfield_default },
+	 { "SQM_RESERVE", 10, 15, &umr_bitfield_default },
+	 { "RATIO", 16, 23, &umr_bitfield_default },
+	 { "RATIO_DEBUG", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_HASH[] = {
+	 { "BANK_XOR_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "COL_XOR", 4, 11, &umr_bitfield_default },
+	 { "ROW_XOR", 12, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2[] = {
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_RD[] = {
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "ACP_HARSH_PRI", 11, 11, &umr_bitfield_default },
+	 { "ACP_OVER_DISP", 12, 12, &umr_bitfield_default },
+	 { "FORCE_ACP_URG", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_158[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_WR[] = {
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "ACP_HARSH_PRI", 11, 11, &umr_bitfield_default },
+	 { "ACP_OVER_DISP", 12, 12, &umr_bitfield_default },
+	 { "FORCE_ACP_URG", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_RD[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_WR[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_RD[] = {
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_WR[] = {
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_RD[] = {
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_WR[] = {
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "URG0", 1, 5, &umr_bitfield_default },
+	 { "URG1", 6, 10, &umr_bitfield_default },
+	 { "ACCUM", 11, 11, &umr_bitfield_default },
+	 { "SINGLE_BANK", 12, 12, &umr_bitfield_default },
+	 { "PUSH_SINGLE_BANK_REFRESH", 13, 13, &umr_bitfield_default },
+	 { "PENDING_RATE_SEL", 14, 16, &umr_bitfield_default },
+	 { "REFSB_PER_PAGE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_RATE[] = {
+	 { "POWERMODE0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PM_CNTL[] = {
+	 { "OVERRIDE_CGSTATE", 0, 1, &umr_bitfield_default },
+	 { "OVRR_CGRFSH", 2, 2, &umr_bitfield_default },
+	 { "OVRR_CGSQM", 3, 3, &umr_bitfield_default },
+	 { "SRFSH_ON_D1", 4, 4, &umr_bitfield_default },
+	 { "BLKOUT_ON_D1", 5, 5, &umr_bitfield_default },
+	 { "IDLE_ON_D1", 6, 6, &umr_bitfield_default },
+	 { "OVRR_PM", 7, 7, &umr_bitfield_default },
+	 { "OVRR_PM_STATE", 8, 9, &umr_bitfield_default },
+	 { "OVRR_RD", 10, 10, &umr_bitfield_default },
+	 { "OVRR_RD_STATE", 11, 11, &umr_bitfield_default },
+	 { "OVRR_WR", 12, 12, &umr_bitfield_default },
+	 { "OVRR_WR_STATE", 13, 13, &umr_bitfield_default },
+	 { "OVRR_RFSH", 14, 14, &umr_bitfield_default },
+	 { "OVRR_RFSH_STATE", 15, 15, &umr_bitfield_default },
+	 { "OVRR_RD0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "OVRR_RD1_BUSY", 17, 17, &umr_bitfield_default },
+	 { "IDLE_ON_D2", 18, 18, &umr_bitfield_default },
+	 { "IDLE_ON_D3", 19, 19, &umr_bitfield_default },
+	 { "IDLE_CNT", 20, 23, &umr_bitfield_default },
+	 { "OVRR_WR0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "OVRR_WR1_BUSY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_RD_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_WR_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_159[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_RD[] = {
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_WR[] = {
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+	 { "MASKWR_LM_EOB", 24, 24, &umr_bitfield_default },
+	 { "ATOMIC_LM_EOB", 25, 25, &umr_bitfield_default },
+	 { "ATOMIC_RTN_LM_EOB", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REMREQ[] = {
+	 { "RD_WATER", 0, 7, &umr_bitfield_default },
+	 { "WR_WATER", 8, 15, &umr_bitfield_default },
+	 { "WR_MAXBURST_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WR_LAZY_TIMER", 20, 23, &umr_bitfield_default },
+	 { "ENABLE_REMOTE_NACK_REQ", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REPLAY[] = {
+	 { "ENABLE_RD", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_WR", 1, 1, &umr_bitfield_default },
+	 { "WRACK_MODE", 2, 2, &umr_bitfield_default },
+	 { "WAW_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RAW_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "IGNORE_WR_CDC", 5, 5, &umr_bitfield_default },
+	 { "BREAK_ON_STALL", 6, 6, &umr_bitfield_default },
+	 { "BOS_ENABLE_WAIT_CYC", 7, 7, &umr_bitfield_default },
+	 { "BOS_WAIT_CYC", 8, 14, &umr_bitfield_default },
+	 { "NO_PCH_AT_REPLAY_START", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_RD[] = {
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "DISP", 16, 23, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_WR[] = {
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 16, 23, &umr_bitfield_default },
+	 { "WRRET_SEQ_SKID", 24, 27, &umr_bitfield_default },
+	 { "WRRET_BP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_CID[] = {
+	 { "CID_CH0", 0, 7, &umr_bitfield_default },
+	 { "CID_CH1", 8, 15, &umr_bitfield_default },
+	 { "WRITE_CH0", 16, 16, &umr_bitfield_default },
+	 { "WRITE_CH1", 17, 17, &umr_bitfield_default },
+	 { "REALTIME_CH0", 18, 18, &umr_bitfield_default },
+	 { "REALTIME_CH1", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_RSLT0[] = {
+	 { "MAX_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_RSLT1[] = {
+	 { "MAX_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_REALTIME_RD[] = {
+	 { "CB0", 0, 0, &umr_bitfield_default },
+	 { "CBCMASK0", 1, 1, &umr_bitfield_default },
+	 { "CBFMASK0", 2, 2, &umr_bitfield_default },
+	 { "DB0", 3, 3, &umr_bitfield_default },
+	 { "DBHTILE0", 4, 4, &umr_bitfield_default },
+	 { "DBSTEN0", 5, 5, &umr_bitfield_default },
+	 { "TC0", 6, 6, &umr_bitfield_default },
+	 { "IA", 7, 7, &umr_bitfield_default },
+	 { "ACPG", 8, 8, &umr_bitfield_default },
+	 { "ACPO", 9, 9, &umr_bitfield_default },
+	 { "DMIF", 10, 10, &umr_bitfield_default },
+	 { "DMIF_EXT0", 11, 11, &umr_bitfield_default },
+	 { "DMIF_EXT1", 12, 12, &umr_bitfield_default },
+	 { "DMIF_TW", 13, 13, &umr_bitfield_default },
+	 { "MCIF", 14, 14, &umr_bitfield_default },
+	 { "RLC", 15, 15, &umr_bitfield_default },
+	 { "VMC", 16, 16, &umr_bitfield_default },
+	 { "SDMA1", 17, 17, &umr_bitfield_default },
+	 { "SMU", 18, 18, &umr_bitfield_default },
+	 { "VCE0", 19, 19, &umr_bitfield_default },
+	 { "VCE1", 20, 20, &umr_bitfield_default },
+	 { "XDMAM", 21, 21, &umr_bitfield_default },
+	 { "SDMA0", 22, 22, &umr_bitfield_default },
+	 { "HDP", 23, 23, &umr_bitfield_default },
+	 { "UMC", 24, 24, &umr_bitfield_default },
+	 { "UVD", 25, 25, &umr_bitfield_default },
+	 { "UVD_EXT0", 26, 26, &umr_bitfield_default },
+	 { "UVD_EXT1", 27, 27, &umr_bitfield_default },
+	 { "SEM", 28, 28, &umr_bitfield_default },
+	 { "SAMMSP", 29, 29, &umr_bitfield_default },
+	 { "VP8", 30, 30, &umr_bitfield_default },
+	 { "ISP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CG[] = {
+	 { "CG_ARB_REQ", 0, 7, &umr_bitfield_default },
+	 { "CG_ARB_RESP", 8, 15, &umr_bitfield_default },
+	 { "RSV_0", 16, 23, &umr_bitfield_default },
+	 { "RSV_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_REALTIME_WR[] = {
+	 { "CB0", 0, 0, &umr_bitfield_default },
+	 { "CBCMASK0", 1, 1, &umr_bitfield_default },
+	 { "CBFMASK0", 2, 2, &umr_bitfield_default },
+	 { "CBIMMED0", 3, 3, &umr_bitfield_default },
+	 { "DB0", 4, 4, &umr_bitfield_default },
+	 { "DBHTILE0", 5, 5, &umr_bitfield_default },
+	 { "DBSTEN0", 6, 6, &umr_bitfield_default },
+	 { "TC0", 7, 7, &umr_bitfield_default },
+	 { "SH", 8, 8, &umr_bitfield_default },
+	 { "ACPG", 9, 9, &umr_bitfield_default },
+	 { "ACPO", 10, 10, &umr_bitfield_default },
+	 { "MCIF", 11, 11, &umr_bitfield_default },
+	 { "RLC", 12, 12, &umr_bitfield_default },
+	 { "SDMA1", 13, 13, &umr_bitfield_default },
+	 { "SMU", 14, 14, &umr_bitfield_default },
+	 { "VCE0", 15, 15, &umr_bitfield_default },
+	 { "VCE1", 16, 16, &umr_bitfield_default },
+	 { "SAMMSP", 17, 17, &umr_bitfield_default },
+	 { "XDMA", 18, 18, &umr_bitfield_default },
+	 { "XDMAM", 19, 19, &umr_bitfield_default },
+	 { "SDMA0", 20, 20, &umr_bitfield_default },
+	 { "HDP", 21, 21, &umr_bitfield_default },
+	 { "UMC", 22, 22, &umr_bitfield_default },
+	 { "UVD", 23, 23, &umr_bitfield_default },
+	 { "UVD_EXT0", 24, 24, &umr_bitfield_default },
+	 { "UVD_EXT1", 25, 25, &umr_bitfield_default },
+	 { "XDP", 26, 26, &umr_bitfield_default },
+	 { "SEM", 27, 27, &umr_bitfield_default },
+	 { "IH", 28, 28, &umr_bitfield_default },
+	 { "VP8", 29, 29, &umr_bitfield_default },
+	 { "ISP", 30, 30, &umr_bitfield_default },
+	 { "VIN0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING_1[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BUSY_STATUS[] = {
+	 { "LM_RD0", 0, 0, &umr_bitfield_default },
+	 { "LM_RD1", 1, 1, &umr_bitfield_default },
+	 { "LM_WR0", 2, 2, &umr_bitfield_default },
+	 { "LM_WR1", 3, 3, &umr_bitfield_default },
+	 { "HM_RD0", 4, 4, &umr_bitfield_default },
+	 { "HM_RD1", 5, 5, &umr_bitfield_default },
+	 { "HM_WR0", 6, 6, &umr_bitfield_default },
+	 { "HM_WR1", 7, 7, &umr_bitfield_default },
+	 { "WDE_RD0", 8, 8, &umr_bitfield_default },
+	 { "WDE_RD1", 9, 9, &umr_bitfield_default },
+	 { "WDE_WR0", 10, 10, &umr_bitfield_default },
+	 { "WDE_WR1", 11, 11, &umr_bitfield_default },
+	 { "POP0", 12, 12, &umr_bitfield_default },
+	 { "POP1", 13, 13, &umr_bitfield_default },
+	 { "TAGFIFO0", 14, 14, &umr_bitfield_default },
+	 { "TAGFIFO1", 15, 15, &umr_bitfield_default },
+	 { "REPLAY0", 16, 16, &umr_bitfield_default },
+	 { "REPLAY1", 17, 17, &umr_bitfield_default },
+	 { "RDRET0", 18, 18, &umr_bitfield_default },
+	 { "RDRET1", 19, 19, &umr_bitfield_default },
+	 { "GECC2_RD0", 20, 20, &umr_bitfield_default },
+	 { "GECC2_RD1", 21, 21, &umr_bitfield_default },
+	 { "GECC2_WR0", 22, 22, &umr_bitfield_default },
+	 { "GECC2_WR1", 23, 23, &umr_bitfield_default },
+	 { "WRRET0", 24, 24, &umr_bitfield_default },
+	 { "WRRET1", 25, 25, &umr_bitfield_default },
+	 { "RTT0", 26, 26, &umr_bitfield_default },
+	 { "RTT1", 27, 27, &umr_bitfield_default },
+	 { "REM_RD0", 28, 28, &umr_bitfield_default },
+	 { "REM_RD1", 29, 29, &umr_bitfield_default },
+	 { "REM_WR0", 30, 30, &umr_bitfield_default },
+	 { "REM_WR1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2_1[] = {
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT7[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_10[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB2[] = {
+	 { "REALTIME_GRP_RD", 0, 7, &umr_bitfield_default },
+	 { "REALTIME_GRP_WR", 8, 15, &umr_bitfield_default },
+	 { "DISP_RD_STALL_EN", 16, 16, &umr_bitfield_default },
+	 { "ACP_RD_STALL_EN", 17, 17, &umr_bitfield_default },
+	 { "UVD_RD_STALL_EN", 18, 18, &umr_bitfield_default },
+	 { "VCE0_RD_STALL_EN", 19, 19, &umr_bitfield_default },
+	 { "VCE1_RD_STALL_EN", 20, 20, &umr_bitfield_default },
+	 { "REALTIME_RD_WTS", 21, 21, &umr_bitfield_default },
+	 { "REALTIME_WR_WTS", 22, 22, &umr_bitfield_default },
+	 { "URGENT_BY_DISP_STALL", 23, 23, &umr_bitfield_default },
+	 { "PROMOTE_BY_DMIF_URG", 24, 24, &umr_bitfield_default },
+	 { "PRIORITY_URGENT_OUTSTANDING_ONLY_RD", 25, 25, &umr_bitfield_default },
+	 { "PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD", 26, 26, &umr_bitfield_default },
+	 { "PRIORITY_URGENT_OUTSTANDING_ONLY_WR", 27, 27, &umr_bitfield_default },
+	 { "PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BURST_TIME[] = {
+	 { "STATE0", 0, 4, &umr_bitfield_default },
+	 { "STATE1", 5, 9, &umr_bitfield_default },
+	 { "TRRDS0", 10, 14, &umr_bitfield_default },
+	 { "TRRDS1", 15, 19, &umr_bitfield_default },
+	 { "TRRDL0", 20, 24, &umr_bitfield_default },
+	 { "TRRDL1", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CNTL[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "RUN", 1, 1, &umr_bitfield_default },
+	 { "PTR_RST_D0", 2, 2, &umr_bitfield_default },
+	 { "PTR_RST_D1", 3, 3, &umr_bitfield_default },
+	 { "MOP_MODE", 4, 4, &umr_bitfield_default },
+	 { "ADR_MODE", 5, 5, &umr_bitfield_default },
+	 { "DAT_MODE", 6, 6, &umr_bitfield_default },
+	 { "LOOP", 10, 11, &umr_bitfield_default },
+	 { "ENABLE_D0", 12, 12, &umr_bitfield_default },
+	 { "ENABLE_D1", 13, 13, &umr_bitfield_default },
+	 { "LOAD_RTDATA_CH", 14, 14, &umr_bitfield_default },
+	 { "LOOP_CNT", 16, 27, &umr_bitfield_default },
+	 { "DONE", 30, 30, &umr_bitfield_default },
+	 { "LOAD_RTDATA", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_AUTO_CNTL[] = {
+	 { "MOP", 0, 1, &umr_bitfield_default },
+	 { "ADR_GEN", 4, 7, &umr_bitfield_default },
+	 { "LFSR_KEY", 8, 23, &umr_bitfield_default },
+	 { "LFSR_RESET", 24, 24, &umr_bitfield_default },
+	 { "ADR_RESET", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DIR_CNTL[] = {
+	 { "MOP", 0, 2, &umr_bitfield_default },
+	 { "EOB", 3, 3, &umr_bitfield_default },
+	 { "MOP_LOAD", 4, 4, &umr_bitfield_default },
+	 { "DATA_LOAD", 5, 5, &umr_bitfield_default },
+	 { "CMD_RTR_D0", 6, 6, &umr_bitfield_default },
+	 { "DAT_RTR_D0", 7, 7, &umr_bitfield_default },
+	 { "CMD_RTR_D1", 8, 8, &umr_bitfield_default },
+	 { "DAT_RTR_D1", 9, 9, &umr_bitfield_default },
+	 { "MOP3", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_SADDR[] = {
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_EADDR[] = {
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_WORD7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_DATA_MASK[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_MISMATCH_ADDR[] = {
+	 { "COL", 0, 9, &umr_bitfield_default },
+	 { "ROW", 10, 23, &umr_bitfield_default },
+	 { "BANK", 24, 27, &umr_bitfield_default },
+	 { "RANK", 28, 28, &umr_bitfield_default },
+	 { "COLH", 29, 29, &umr_bitfield_default },
+	 { "ROWH", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD0[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD1[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD2[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD3[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD4[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD5[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD6[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_WORD7[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_MASK[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_RDATA_EDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_0_S[] = {
+	 { "SCLK_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_1_S[] = {
+	 { "SCLK_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_STATUS_S[] = {
+	 { "SEQ0_ARB_DATA_FIFO_FULL", 0, 0, &umr_bitfield_default },
+	 { "SEQ1_ARB_DATA_FIFO_FULL", 1, 1, &umr_bitfield_default },
+	 { "SEQ0_ARB_CMD_FIFO_FULL", 4, 4, &umr_bitfield_default },
+	 { "SEQ1_ARB_CMD_FIFO_FULL", 5, 5, &umr_bitfield_default },
+	 { "SEQ0_RS_DATA_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "SEQ1_RS_DATA_FIFO_EMPTY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_DATAPORT[] = {
+	 { "DATA_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MPLL_OVERRIDE[] = {
+	 { "AD_PLL_RESET_OVERRIDE", 0, 0, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_RESET_OVERRIDE", 1, 1, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_RESET_OVERRIDE", 2, 2, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_RESET_OVERRIDE", 3, 3, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_RESET_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "ATGM_CLK_SEL_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "TEST_BYPASS_CLK_EN_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "TEST_BYPASS_CLK_SEL_OVERRIDE", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CNTL[] = {
+	 { "MEM_ADDR_MAP_COLS", 0, 1, &umr_bitfield_default },
+	 { "MEM_ADDR_MAP_BANK", 2, 3, &umr_bitfield_default },
+	 { "SAFE_MODE", 4, 5, &umr_bitfield_default },
+	 { "DAT_INV", 6, 6, &umr_bitfield_default },
+	 { "MSK_DF1", 7, 7, &umr_bitfield_default },
+	 { "CHANNEL_DISABLE", 8, 9, &umr_bitfield_default },
+	 { "MSKOFF_DAT_TL", 14, 14, &umr_bitfield_default },
+	 { "MSKOFF_DAT_TH", 15, 15, &umr_bitfield_default },
+	 { "RET_HOLD_EOP", 16, 16, &umr_bitfield_default },
+	 { "BANKGROUP_SIZE", 17, 17, &umr_bitfield_default },
+	 { "BANKGROUP_ENB", 18, 18, &umr_bitfield_default },
+	 { "RTR_OVERRIDE", 19, 19, &umr_bitfield_default },
+	 { "ARB_REQCMD_WMK", 20, 23, &umr_bitfield_default },
+	 { "ARB_REQDAT_WMK", 24, 27, &umr_bitfield_default },
+	 { "ARB_RTDAT_WMK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM[] = {
+	 { "ADR_2CK", 0, 0, &umr_bitfield_default },
+	 { "ADR_MUX", 1, 1, &umr_bitfield_default },
+	 { "ADR_DF1", 2, 2, &umr_bitfield_default },
+	 { "AP8", 3, 3, &umr_bitfield_default },
+	 { "DAT_DF1", 4, 4, &umr_bitfield_default },
+	 { "DQS_DF1", 5, 5, &umr_bitfield_default },
+	 { "DQM_DF1", 6, 6, &umr_bitfield_default },
+	 { "DQM_ACT", 7, 7, &umr_bitfield_default },
+	 { "STB_CNT", 8, 11, &umr_bitfield_default },
+	 { "CKE_DYN", 12, 12, &umr_bitfield_default },
+	 { "CKE_ACT", 13, 13, &umr_bitfield_default },
+	 { "BO4", 14, 14, &umr_bitfield_default },
+	 { "DLL_CLR", 15, 15, &umr_bitfield_default },
+	 { "DLL_CNT", 16, 23, &umr_bitfield_default },
+	 { "DAT_INV", 24, 24, &umr_bitfield_default },
+	 { "INV_ACM", 25, 25, &umr_bitfield_default },
+	 { "ODT_ENB", 26, 26, &umr_bitfield_default },
+	 { "ODT_ACT", 27, 27, &umr_bitfield_default },
+	 { "RST_CTL", 28, 28, &umr_bitfield_default },
+	 { "TRI_MIO_DYN", 29, 29, &umr_bitfield_default },
+	 { "TRI_CKE", 30, 30, &umr_bitfield_default },
+	 { "RDSTRB_RSYC_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM_2[] = {
+	 { "ADR_DDR", 0, 0, &umr_bitfield_default },
+	 { "ADR_DBI", 1, 1, &umr_bitfield_default },
+	 { "ADR_DBI_ACM", 2, 2, &umr_bitfield_default },
+	 { "CMD_QDR", 3, 3, &umr_bitfield_default },
+	 { "DAT_QDR", 4, 4, &umr_bitfield_default },
+	 { "WDAT_EDC", 5, 5, &umr_bitfield_default },
+	 { "RDAT_EDC", 6, 6, &umr_bitfield_default },
+	 { "DQM_EST", 7, 7, &umr_bitfield_default },
+	 { "RD_DQS", 8, 8, &umr_bitfield_default },
+	 { "WR_DQS", 9, 9, &umr_bitfield_default },
+	 { "PLL_EST", 10, 10, &umr_bitfield_default },
+	 { "PLL_CLR", 11, 11, &umr_bitfield_default },
+	 { "DLL_EST", 12, 12, &umr_bitfield_default },
+	 { "BNK_MRS", 13, 13, &umr_bitfield_default },
+	 { "DBI_OVR", 14, 14, &umr_bitfield_default },
+	 { "TRI_CLK", 15, 15, &umr_bitfield_default },
+	 { "PLL_CNT", 16, 23, &umr_bitfield_default },
+	 { "PCH_BNK", 24, 24, &umr_bitfield_default },
+	 { "ADBI_DF1", 25, 25, &umr_bitfield_default },
+	 { "ADBI_ACT", 26, 26, &umr_bitfield_default },
+	 { "DBI_DF1", 27, 27, &umr_bitfield_default },
+	 { "DBI_ACT", 28, 28, &umr_bitfield_default },
+	 { "DBI_EDC_DF1", 29, 29, &umr_bitfield_default },
+	 { "TESTCHIP_EN", 30, 30, &umr_bitfield_default },
+	 { "CS_BY16", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RAS_TIMING[] = {
+	 { "TRCDW", 0, 4, &umr_bitfield_default },
+	 { "TRCDWA", 5, 9, &umr_bitfield_default },
+	 { "TRCDR", 10, 14, &umr_bitfield_default },
+	 { "TRCDRA", 15, 19, &umr_bitfield_default },
+	 { "TRRD", 20, 23, &umr_bitfield_default },
+	 { "TRC", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CAS_TIMING[] = {
+	 { "TNOPW", 0, 1, &umr_bitfield_default },
+	 { "TNOPR", 2, 3, &umr_bitfield_default },
+	 { "TR2W", 4, 8, &umr_bitfield_default },
+	 { "TCCDL", 9, 11, &umr_bitfield_default },
+	 { "TR2R", 12, 15, &umr_bitfield_default },
+	 { "TW2R", 16, 20, &umr_bitfield_default },
+	 { "TCL", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING[] = {
+	 { "TRP_WRA", 0, 5, &umr_bitfield_default },
+	 { "TRP_RDA", 8, 13, &umr_bitfield_default },
+	 { "TRP", 15, 19, &umr_bitfield_default },
+	 { "TRFC", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING2[] = {
+	 { "PA2RDATA", 0, 2, &umr_bitfield_default },
+	 { "PA2WDATA", 4, 6, &umr_bitfield_default },
+	 { "FAW", 8, 12, &umr_bitfield_default },
+	 { "TREDC", 13, 15, &umr_bitfield_default },
+	 { "TWEDC", 16, 20, &umr_bitfield_default },
+	 { "T32AW", 21, 24, &umr_bitfield_default },
+	 { "TWDATATR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_TIMING[] = {
+	 { "TCKSRE", 0, 2, &umr_bitfield_default },
+	 { "TCKSRX", 4, 6, &umr_bitfield_default },
+	 { "TCKE_PULSE", 8, 11, &umr_bitfield_default },
+	 { "TCKE", 12, 17, &umr_bitfield_default },
+	 { "SEQ_IDLE", 18, 20, &umr_bitfield_default },
+	 { "TCKE_PULSE_MSB", 23, 23, &umr_bitfield_default },
+	 { "SEQ_IDLE_SS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D0[] = {
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D1[] = {
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D0[] = {
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D1[] = {
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CMD[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "CHAN0", 24, 24, &umr_bitfield_default },
+	 { "CHAN1", 25, 25, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_CNTL[] = {
+	 { "RUN", 0, 0, &umr_bitfield_default },
+	 { "SINGLE_STEP", 1, 1, &umr_bitfield_default },
+	 { "SW_WAKE", 2, 2, &umr_bitfield_default },
+	 { "RESET_PC", 3, 3, &umr_bitfield_default },
+	 { "PGM_WRITE", 4, 4, &umr_bitfield_default },
+	 { "PGM_READ", 5, 5, &umr_bitfield_default },
+	 { "FAST_WRITE", 6, 6, &umr_bitfield_default },
+	 { "BKPT_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "PGM_CHKSUM", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_PGM[] = {
+	 { "CNTL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_AUTO_CMD[] = {
+	 { "ADR", 0, 16, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_AUTO_CFG[] = {
+	 { "SYC_CLK", 0, 0, &umr_bitfield_default },
+	 { "RST_MRS", 1, 1, &umr_bitfield_default },
+	 { "TRI_MIO", 2, 2, &umr_bitfield_default },
+	 { "XSR_TMR", 4, 7, &umr_bitfield_default },
+	 { "SS_ALWAYS_SLF", 8, 8, &umr_bitfield_default },
+	 { "SS_S_SLF", 9, 9, &umr_bitfield_default },
+	 { "SCDS_MODE", 10, 10, &umr_bitfield_default },
+	 { "EXIT_ALLOW_STOP", 11, 11, &umr_bitfield_default },
+	 { "RFS_SRX", 12, 12, &umr_bitfield_default },
+	 { "PREA_SRX", 13, 13, &umr_bitfield_default },
+	 { "STUTTER_EN", 14, 14, &umr_bitfield_default },
+	 { "SELFREFR_COMMIT_0", 15, 15, &umr_bitfield_default },
+	 { "MRS_WAIT_CNT", 16, 19, &umr_bitfield_default },
+	 { "WRITE_DURING_DLOCK", 20, 20, &umr_bitfield_default },
+	 { "YCLK_ON", 21, 21, &umr_bitfield_default },
+	 { "RXPDNB", 22, 22, &umr_bitfield_default },
+	 { "SELFREFR_COMMIT_1", 23, 23, &umr_bitfield_default },
+	 { "DLL_CNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_CNTL[] = {
+	 { "MEM_IO_UPDATE_RATE", 0, 4, &umr_bitfield_default },
+	 { "CAL_VREF_SEL", 5, 5, &umr_bitfield_default },
+	 { "CAL_VREFMODE", 6, 6, &umr_bitfield_default },
+	 { "TIMEOUT_ERR", 8, 8, &umr_bitfield_default },
+	 { "CLEAR_TIMEOUT_ERR", 9, 9, &umr_bitfield_default },
+	 { "MEM_IO_SAMPLE_CNT", 13, 15, &umr_bitfield_default },
+	 { "CAL_VREF", 16, 22, &umr_bitfield_default },
+	 { "CAL_WHEN_IDLE", 29, 29, &umr_bitfield_default },
+	 { "CAL_WHEN_REFRESH", 30, 30, &umr_bitfield_default },
+	 { "CAL_PWRON", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_DEBUG[] = {
+	 { "TSTARTUP_CNTR", 0, 7, &umr_bitfield_default },
+	 { "TIMEOUT_CNTR", 8, 15, &umr_bitfield_default },
+	 { "PMVCAL_RESERVED", 16, 27, &umr_bitfield_default },
+	 { "DEBUG_CAL_EN", 28, 28, &umr_bitfield_default },
+	 { "DEBUG_CAL_START", 29, 29, &umr_bitfield_default },
+	 { "DEBUG_CAL_INTR", 30, 30, &umr_bitfield_default },
+	 { "DEBUG_CAL_DONE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_STATUS[] = {
+	 { "PSTR_CAL", 0, 7, &umr_bitfield_default },
+	 { "PSTR_ACCUM_VAL", 8, 15, &umr_bitfield_default },
+	 { "NSTR_CAL", 16, 23, &umr_bitfield_default },
+	 { "NSTR_ACCUM_VAL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WCDR_CTRL[] = {
+	 { "WCDR_PRE", 0, 7, &umr_bitfield_default },
+	 { "WCDR_TIM", 8, 11, &umr_bitfield_default },
+	 { "WR_EN", 12, 12, &umr_bitfield_default },
+	 { "RD_EN", 13, 13, &umr_bitfield_default },
+	 { "AREF_EN", 14, 14, &umr_bitfield_default },
+	 { "TRAIN_EN", 15, 15, &umr_bitfield_default },
+	 { "TWCDRL", 16, 19, &umr_bitfield_default },
+	 { "PRBS_EN", 20, 20, &umr_bitfield_default },
+	 { "PRBS_RST", 21, 21, &umr_bitfield_default },
+	 { "PREAMBLE", 24, 27, &umr_bitfield_default },
+	 { "PRE_MASK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_CNTL[] = {
+	 { "BOOT_UP_ADDR_TRAIN", 0, 0, &umr_bitfield_default },
+	 { "BOOT_UP_WCK_TRAIN", 1, 1, &umr_bitfield_default },
+	 { "BOOT_UP_READ_TRAIN", 2, 2, &umr_bitfield_default },
+	 { "BOOT_UP_WRITE_TRAIN", 3, 3, &umr_bitfield_default },
+	 { "SELF_REFRESH_ADDR_TRAIN", 4, 4, &umr_bitfield_default },
+	 { "SELF_REFRESH_WCK_TRAIN", 5, 5, &umr_bitfield_default },
+	 { "SELF_REFRESH_READ_TRAIN", 6, 6, &umr_bitfield_default },
+	 { "SELF_REFRESH_WRITE_TRAIN", 7, 7, &umr_bitfield_default },
+	 { "AUTO_REFRESH_ADDR_TRAIN", 8, 8, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WCK_TRAIN", 9, 9, &umr_bitfield_default },
+	 { "AUTO_REFRESH_READ_TRAIN", 10, 10, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WRITE_TRAIN", 11, 11, &umr_bitfield_default },
+	 { "WRITE_ECC_ADDR_TRAIN", 12, 12, &umr_bitfield_default },
+	 { "WRITE_ECC_WCK_TRAIN", 13, 13, &umr_bitfield_default },
+	 { "WRITE_ECC_READ_TRAIN", 14, 14, &umr_bitfield_default },
+	 { "WRITE_ECC_WRITE_TRAIN", 15, 15, &umr_bitfield_default },
+	 { "READ_ECC_ADDR_TRAIN", 16, 16, &umr_bitfield_default },
+	 { "READ_ECC_WCK_TRAIN", 17, 17, &umr_bitfield_default },
+	 { "READ_ECC_READ_TRAIN", 18, 18, &umr_bitfield_default },
+	 { "READ_ECC_WRITE_TRAIN", 19, 19, &umr_bitfield_default },
+	 { "AUTO_REFRESH_WAKEUP_EARLY", 20, 20, &umr_bitfield_default },
+	 { "STOP_WCK_D0", 21, 21, &umr_bitfield_default },
+	 { "STOP_WCK_D1", 22, 22, &umr_bitfield_default },
+	 { "BLOCK_ARB_RD_D0", 24, 24, &umr_bitfield_default },
+	 { "BLOCK_ARB_WR_D0", 25, 25, &umr_bitfield_default },
+	 { "BLOCK_ARB_RD_D1", 26, 26, &umr_bitfield_default },
+	 { "BLOCK_ARB_WR_D1", 27, 27, &umr_bitfield_default },
+	 { "SW_WAKEUP", 28, 28, &umr_bitfield_default },
+	 { "DISP_ASTOP_WAKEUP", 29, 29, &umr_bitfield_default },
+	 { "TRAIN_DONE_D0", 30, 30, &umr_bitfield_default },
+	 { "TRAIN_DONE_D1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD[] = {
+	 { "WRITE_EDC_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "READ_EDC_THRESHOLD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_EDGE[] = {
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "SREG_WAKEUP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_MASK[] = {
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "SREG_WAKEUP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_CAPTURE[] = {
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "SREG_WAKEUP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_WAKEUP_CLEAR[] = {
+	 { "D0_ARF_WAKEUP", 0, 0, &umr_bitfield_default },
+	 { "D1_ARF_WAKEUP", 1, 1, &umr_bitfield_default },
+	 { "D0_REDC_WAKEUP", 2, 2, &umr_bitfield_default },
+	 { "D1_REDC_WAKEUP", 3, 3, &umr_bitfield_default },
+	 { "D0_WEDC_WAKEUP", 4, 4, &umr_bitfield_default },
+	 { "D1_WEDC_WAKEUP", 5, 5, &umr_bitfield_default },
+	 { "MCLK_FREQ_CHANGE_WAKEUP", 6, 6, &umr_bitfield_default },
+	 { "SCLK_SRBM_READY_WAKEUP", 7, 7, &umr_bitfield_default },
+	 { "D0_CMD_FIFO_READY_WAKEUP", 8, 8, &umr_bitfield_default },
+	 { "D1_CMD_FIFO_READY_WAKEUP", 9, 9, &umr_bitfield_default },
+	 { "D0_DATA_FIFO_READY_WAKEUP", 10, 10, &umr_bitfield_default },
+	 { "D1_DATA_FIFO_READY_WAKEUP", 11, 11, &umr_bitfield_default },
+	 { "SOFTWARE_WAKEUP_WAKEUP", 12, 12, &umr_bitfield_default },
+	 { "RESERVE0_WAKEUP", 13, 13, &umr_bitfield_default },
+	 { "TSM_DONE_WAKEUP", 14, 14, &umr_bitfield_default },
+	 { "TIMER_DONE_WAKEUP", 15, 15, &umr_bitfield_default },
+	 { "CLEARALL", 16, 16, &umr_bitfield_default },
+	 { "TCG_DONE_WAKEUP", 17, 17, &umr_bitfield_default },
+	 { "ALLOWSTOP0_WAKEUP", 18, 18, &umr_bitfield_default },
+	 { "ALLOWSTOP1_WAKEUP", 19, 19, &umr_bitfield_default },
+	 { "DPM_WAKEUP", 20, 20, &umr_bitfield_default },
+	 { "ALLOWSTOPB0_WAKEUP", 21, 21, &umr_bitfield_default },
+	 { "ALLOWSTOPB1_WAKEUP", 22, 22, &umr_bitfield_default },
+	 { "DPM_LPT_WAKEUP", 23, 23, &umr_bitfield_default },
+	 { "D0_IDLEH_WAKEUP", 24, 24, &umr_bitfield_default },
+	 { "D1_IDLEH_WAKEUP", 25, 25, &umr_bitfield_default },
+	 { "PHY_PG_WAKEUP", 26, 26, &umr_bitfield_default },
+	 { "SREG_WAKEUP", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_TIMING[] = {
+	 { "TWT2RT", 0, 4, &umr_bitfield_default },
+	 { "TARF2T", 5, 9, &umr_bitfield_default },
+	 { "TT2ROW", 10, 14, &umr_bitfield_default },
+	 { "TLD2LD", 15, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDCCDR_R_D0[] = {
+	 { "EDC0", 0, 7, &umr_bitfield_default },
+	 { "EDC1", 8, 15, &umr_bitfield_default },
+	 { "EDC2", 16, 23, &umr_bitfield_default },
+	 { "EDC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDCCDR_R_D1[] = {
+	 { "EDC0", 0, 7, &umr_bitfield_default },
+	 { "EDC1", 8, 15, &umr_bitfield_default },
+	 { "EDC2", 16, 23, &umr_bitfield_default },
+	 { "EDC3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_0_D0[] = {
+	 { "DQ_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_1_D0[] = {
+	 { "DBI_STATUS", 0, 3, &umr_bitfield_default },
+	 { "EDC_STATUS", 4, 7, &umr_bitfield_default },
+	 { "WCK_STATUS", 8, 11, &umr_bitfield_default },
+	 { "WCDR_STATUS", 12, 15, &umr_bitfield_default },
+	 { "PMA_PRBSCLR", 28, 28, &umr_bitfield_default },
+	 { "PMD0_PRBSCLR", 29, 29, &umr_bitfield_default },
+	 { "PMD1_PRBSCLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDC_STATUS_D0[] = {
+	 { "WEDC_CNT", 0, 15, &umr_bitfield_default },
+	 { "REDC_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_0_D1[] = {
+	 { "DQ_STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_1_D1[] = {
+	 { "DBI_STATUS", 0, 3, &umr_bitfield_default },
+	 { "EDC_STATUS", 4, 7, &umr_bitfield_default },
+	 { "WCK_STATUS", 8, 11, &umr_bitfield_default },
+	 { "WCDR_STATUS", 12, 15, &umr_bitfield_default },
+	 { "PMA_PRBSCLR", 28, 28, &umr_bitfield_default },
+	 { "PMD0_PRBSCLR", 29, 29, &umr_bitfield_default },
+	 { "PMD1_PRBSCLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_EDC_STATUS_D1[] = {
+	 { "WEDC_CNT", 0, 15, &umr_bitfield_default },
+	 { "REDC_CNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY0_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY1_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_APHY_D0[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "TXBPASS_SEL", 12, 12, &umr_bitfield_default },
+	 { "PMA_LOOPBACK", 13, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 22, &umr_bitfield_default },
+	 { "YCLKON", 23, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXRESET", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 27, 29, &umr_bitfield_default },
+	 { "CKE_BIT", 30, 30, &umr_bitfield_default },
+	 { "CKE_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY0_D0[] = {
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY1_D0[] = {
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_DPHY_STR_CNTL_D0[] = {
+	 { "PSTR_OFF_D", 0, 5, &umr_bitfield_default },
+	 { "NSTR_OFF_D", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_S", 12, 17, &umr_bitfield_default },
+	 { "NSTR_OFF_S", 18, 23, &umr_bitfield_default },
+	 { "USE_D_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_S_CAL", 25, 25, &umr_bitfield_default },
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_D_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_S_STR", 29, 29, &umr_bitfield_default },
+	 { "AUTO_LD_STR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY0_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_DPHY1_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "NTERM", 12, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "EDCTX_CLKGATE_EN", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "PLL_LOOPBCK", 27, 27, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_TXCNTL_APHY_D1[] = {
+	 { "BIASSEL", 0, 1, &umr_bitfield_default },
+	 { "DRVDUTY", 2, 3, &umr_bitfield_default },
+	 { "LOWCMEN", 4, 4, &umr_bitfield_default },
+	 { "QDR", 5, 5, &umr_bitfield_default },
+	 { "EMPH", 6, 6, &umr_bitfield_default },
+	 { "TXPD", 7, 7, &umr_bitfield_default },
+	 { "PTERM", 8, 11, &umr_bitfield_default },
+	 { "TXBPASS_SEL", 12, 12, &umr_bitfield_default },
+	 { "PMA_LOOPBACK", 13, 15, &umr_bitfield_default },
+	 { "PDRV", 16, 19, &umr_bitfield_default },
+	 { "NDRV", 20, 22, &umr_bitfield_default },
+	 { "YCLKON", 23, 23, &umr_bitfield_default },
+	 { "TSTEN", 24, 24, &umr_bitfield_default },
+	 { "TXRESET", 25, 25, &umr_bitfield_default },
+	 { "TXBYPASS", 26, 26, &umr_bitfield_default },
+	 { "TXBYPASS_DATA", 27, 29, &umr_bitfield_default },
+	 { "CKE_BIT", 30, 30, &umr_bitfield_default },
+	 { "CKE_SEL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY0_D1[] = {
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL_DPHY1_D1[] = {
+	 { "RXBIASSEL", 0, 1, &umr_bitfield_default },
+	 { "RCVSEL", 2, 2, &umr_bitfield_default },
+	 { "VREFPDNB", 3, 3, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 4, 5, &umr_bitfield_default },
+	 { "RXPDNB", 6, 6, &umr_bitfield_default },
+	 { "RXLP", 7, 7, &umr_bitfield_default },
+	 { "VREFCAL", 8, 11, &umr_bitfield_default },
+	 { "VREFCAL_STR", 12, 15, &umr_bitfield_default },
+	 { "VREFSEL", 16, 16, &umr_bitfield_default },
+	 { "RX_PEAKSEL", 18, 19, &umr_bitfield_default },
+	 { "DLL_ADJ_B0", 20, 22, &umr_bitfield_default },
+	 { "DLL_ADJ_B1", 24, 26, &umr_bitfield_default },
+	 { "DLL_ADJ_M", 28, 28, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DLL_BW_CTRL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_DPHY_STR_CNTL_D1[] = {
+	 { "PSTR_OFF_D", 0, 5, &umr_bitfield_default },
+	 { "NSTR_OFF_D", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_S", 12, 17, &umr_bitfield_default },
+	 { "NSTR_OFF_S", 18, 23, &umr_bitfield_default },
+	 { "USE_D_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_S_CAL", 25, 25, &umr_bitfield_default },
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_D_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_S_STR", 29, 29, &umr_bitfield_default },
+	 { "AUTO_LD_STR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL_D0[] = {
+	 { "RXPHASE_B01", 0, 3, &umr_bitfield_default },
+	 { "RXPHASE_B23", 4, 7, &umr_bitfield_default },
+	 { "RXCDREN_B01", 8, 8, &umr_bitfield_default },
+	 { "RXCDREN_B23", 9, 9, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B01", 10, 10, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B23", 11, 11, &umr_bitfield_default },
+	 { "RXPHASE1_B01", 12, 15, &umr_bitfield_default },
+	 { "RXPHASE1_B23", 16, 19, &umr_bitfield_default },
+	 { "DQTXCDREN_B0", 20, 20, &umr_bitfield_default },
+	 { "DQTXCDREN_B1", 21, 21, &umr_bitfield_default },
+	 { "DQRXCDREN_B0", 22, 22, &umr_bitfield_default },
+	 { "DQRXCDREN_B1", 23, 23, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B0", 24, 24, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B1", 25, 25, &umr_bitfield_default },
+	 { "WCDREDC_B0", 26, 26, &umr_bitfield_default },
+	 { "WCDREDC_B1", 27, 27, &umr_bitfield_default },
+	 { "DQRXSEL_B0", 28, 28, &umr_bitfield_default },
+	 { "DQRXSEL_B1", 29, 29, &umr_bitfield_default },
+	 { "DQTXSEL_B0", 30, 30, &umr_bitfield_default },
+	 { "DQTXSEL_B1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL_D1[] = {
+	 { "RXPHASE_B01", 0, 3, &umr_bitfield_default },
+	 { "RXPHASE_B23", 4, 7, &umr_bitfield_default },
+	 { "RXCDREN_B01", 8, 8, &umr_bitfield_default },
+	 { "RXCDREN_B23", 9, 9, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B01", 10, 10, &umr_bitfield_default },
+	 { "RXCDRBYPASS_B23", 11, 11, &umr_bitfield_default },
+	 { "RXPHASE1_B01", 12, 15, &umr_bitfield_default },
+	 { "RXPHASE1_B23", 16, 19, &umr_bitfield_default },
+	 { "DQTXCDREN_B0", 20, 20, &umr_bitfield_default },
+	 { "DQTXCDREN_B1", 21, 21, &umr_bitfield_default },
+	 { "DQRXCDREN_B0", 22, 22, &umr_bitfield_default },
+	 { "DQRXCDREN_B1", 23, 23, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B0", 24, 24, &umr_bitfield_default },
+	 { "WCDRRXCDREN_B1", 25, 25, &umr_bitfield_default },
+	 { "WCDREDC_B0", 26, 26, &umr_bitfield_default },
+	 { "WCDREDC_B1", 27, 27, &umr_bitfield_default },
+	 { "DQRXSEL_B0", 28, 28, &umr_bitfield_default },
+	 { "DQRXSEL_B1", 29, 29, &umr_bitfield_default },
+	 { "DQTXSEL_B0", 30, 30, &umr_bitfield_default },
+	 { "DQTXSEL_B1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_FIFO_CTL[] = {
+	 { "W_LD_INIT_D0", 0, 1, &umr_bitfield_default },
+	 { "W_SYC_SEL", 2, 3, &umr_bitfield_default },
+	 { "R_LD_INIT", 4, 5, &umr_bitfield_default },
+	 { "R_SYC_SEL", 6, 7, &umr_bitfield_default },
+	 { "CG_DIS_D0", 8, 8, &umr_bitfield_default },
+	 { "CG_DIS_D1", 9, 9, &umr_bitfield_default },
+	 { "W_LD_INIT_D1", 10, 11, &umr_bitfield_default },
+	 { "SYC_DLY", 12, 14, &umr_bitfield_default },
+	 { "W_ASYC_EXT", 16, 17, &umr_bitfield_default },
+	 { "W_DSYC_EXT", 18, 19, &umr_bitfield_default },
+	 { "R_DQS_LD_INIT", 20, 23, &umr_bitfield_default },
+	 { "R_DQS_STEP", 24, 27, &umr_bitfield_default },
+	 { "R_DQS_FRC", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE0_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE1_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE2_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE3_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_DBI_D0[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_EDC_D0[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_FCK_D0[] = {
+	 { "FCK0", 0, 3, &umr_bitfield_default },
+	 { "FCK1", 4, 7, &umr_bitfield_default },
+	 { "FCK2", 8, 11, &umr_bitfield_default },
+	 { "FCK3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC8[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE0_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE1_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE2_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_BYTE3_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_DBI_D1[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_EDC_D1[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TXFRAMING_FCK_D1[] = {
+	 { "FCK0", 0, 3, &umr_bitfield_default },
+	 { "FCK1", 4, 7, &umr_bitfield_default },
+	 { "FCK2", 8, 11, &umr_bitfield_default },
+	 { "FCK3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE0_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE1_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE2_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE3_D0[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_DBI_D0[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_EDC_D0[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE0_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE1_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE2_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_BYTE3_D1[] = {
+	 { "DQ0", 0, 3, &umr_bitfield_default },
+	 { "DQ1", 4, 7, &umr_bitfield_default },
+	 { "DQ2", 8, 11, &umr_bitfield_default },
+	 { "DQ3", 12, 15, &umr_bitfield_default },
+	 { "DQ4", 16, 19, &umr_bitfield_default },
+	 { "DQ5", 20, 23, &umr_bitfield_default },
+	 { "DQ6", 24, 27, &umr_bitfield_default },
+	 { "DQ7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_DBI_D1[] = {
+	 { "DBI0", 0, 3, &umr_bitfield_default },
+	 { "DBI1", 4, 7, &umr_bitfield_default },
+	 { "DBI2", 8, 11, &umr_bitfield_default },
+	 { "DBI3", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RXFRAMING_EDC_D1[] = {
+	 { "EDC0", 0, 3, &umr_bitfield_default },
+	 { "EDC1", 4, 7, &umr_bitfield_default },
+	 { "EDC2", 8, 11, &umr_bitfield_default },
+	 { "EDC3", 12, 15, &umr_bitfield_default },
+	 { "WCDR0", 16, 19, &umr_bitfield_default },
+	 { "WCDR1", 20, 23, &umr_bitfield_default },
+	 { "WCDR2", 24, 27, &umr_bitfield_default },
+	 { "WCDR3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL[] = {
+	 { "MEM_IO_IMP_MIN", 0, 7, &umr_bitfield_default },
+	 { "MEM_IO_IMP_MAX", 8, 15, &umr_bitfield_default },
+	 { "TXPHASE_GRAY", 16, 16, &umr_bitfield_default },
+	 { "RXPHASE_GRAY", 17, 17, &umr_bitfield_default },
+	 { "OVL_YCLKON_D0", 18, 18, &umr_bitfield_default },
+	 { "OVL_YCLKON_D1", 19, 19, &umr_bitfield_default },
+	 { "ATBSEL", 20, 23, &umr_bitfield_default },
+	 { "ATBEN", 24, 29, &umr_bitfield_default },
+	 { "ATBSEL_D1", 30, 30, &umr_bitfield_default },
+	 { "ATBSEL_D0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL_D0[] = {
+	 { "DELAY_CLK_SYNC", 2, 2, &umr_bitfield_default },
+	 { "DELAY_CMD_SYNC", 3, 3, &umr_bitfield_default },
+	 { "DELAY_ADR_SYNC", 4, 4, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CLK", 7, 7, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CMD", 8, 8, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_ADR", 9, 9, &umr_bitfield_default },
+	 { "FORCE_EN_RD_STR", 10, 10, &umr_bitfield_default },
+	 { "EN_RD_STR_DLY", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CMD", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_ADR", 13, 13, &umr_bitfield_default },
+	 { "VREFI_EN", 14, 14, &umr_bitfield_default },
+	 { "VREFI_SEL", 15, 19, &umr_bitfield_default },
+	 { "CK_AUTO_EN", 20, 20, &umr_bitfield_default },
+	 { "CK_DELAY_SEL", 21, 21, &umr_bitfield_default },
+	 { "CK_DELAY_N", 22, 23, &umr_bitfield_default },
+	 { "CK_DELAY_P", 24, 25, &umr_bitfield_default },
+	 { "TXPWROFF_CKE", 27, 27, &umr_bitfield_default },
+	 { "UNI_STR", 28, 28, &umr_bitfield_default },
+	 { "DIFF_STR", 29, 29, &umr_bitfield_default },
+	 { "GDDR_PWRON", 30, 30, &umr_bitfield_default },
+	 { "TXPWROFF_CLK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_PAD_CNTL_D1[] = {
+	 { "DELAY_DATA_SYNC", 0, 0, &umr_bitfield_default },
+	 { "DELAY_STR_SYNC", 1, 1, &umr_bitfield_default },
+	 { "DELAY_CLK_SYNC", 2, 2, &umr_bitfield_default },
+	 { "DELAY_CMD_SYNC", 3, 3, &umr_bitfield_default },
+	 { "DELAY_ADR_SYNC", 4, 4, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_DATA", 5, 5, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_STR", 6, 6, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CLK", 7, 7, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_CMD", 8, 8, &umr_bitfield_default },
+	 { "MEM_FALL_OUT_ADR", 9, 9, &umr_bitfield_default },
+	 { "FORCE_EN_RD_STR", 10, 10, &umr_bitfield_default },
+	 { "EN_RD_STR_DLY", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CMD", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_ADR", 13, 13, &umr_bitfield_default },
+	 { "VREFI_EN", 14, 14, &umr_bitfield_default },
+	 { "VREFI_SEL", 15, 19, &umr_bitfield_default },
+	 { "CK_AUTO_EN", 20, 20, &umr_bitfield_default },
+	 { "CK_DELAY_SEL", 21, 21, &umr_bitfield_default },
+	 { "CK_DELAY_N", 22, 23, &umr_bitfield_default },
+	 { "CK_DELAY_P", 24, 25, &umr_bitfield_default },
+	 { "TXPWROFF_CKE", 27, 27, &umr_bitfield_default },
+	 { "UNI_STR", 28, 28, &umr_bitfield_default },
+	 { "DIFF_STR", 29, 29, &umr_bitfield_default },
+	 { "GDDR_PWRON", 30, 30, &umr_bitfield_default },
+	 { "TXPWROFF_CLK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_NPL_STATUS[] = {
+	 { "D0_PDELAY", 0, 1, &umr_bitfield_default },
+	 { "D0_NDELAY", 2, 3, &umr_bitfield_default },
+	 { "D0_PEARLY", 4, 4, &umr_bitfield_default },
+	 { "D0_NEARLY", 5, 5, &umr_bitfield_default },
+	 { "D1_PDELAY", 6, 7, &umr_bitfield_default },
+	 { "D1_NDELAY", 8, 9, &umr_bitfield_default },
+	 { "D1_PEARLY", 10, 10, &umr_bitfield_default },
+	 { "D1_NEARLY", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_CNTL[] = {
+	 { "MONITOR_PERIOD", 0, 29, &umr_bitfield_default },
+	 { "CNTL", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CTL[] = {
+	 { "SEL_A", 0, 3, &umr_bitfield_default },
+	 { "SEL_B", 4, 7, &umr_bitfield_default },
+	 { "SEL_CH0_C", 8, 11, &umr_bitfield_default },
+	 { "SEL_CH0_D", 12, 15, &umr_bitfield_default },
+	 { "SEL_CH1_A", 16, 19, &umr_bitfield_default },
+	 { "SEL_CH1_B", 20, 23, &umr_bitfield_default },
+	 { "SEL_CH1_C", 24, 27, &umr_bitfield_default },
+	 { "SEL_CH1_D", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_A_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_A_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_B_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_B_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_STATUS_M[] = {
+	 { "PWRUP_COMPL_D0", 0, 0, &umr_bitfield_default },
+	 { "PWRUP_COMPL_D1", 1, 1, &umr_bitfield_default },
+	 { "CMD_RDY_D0", 2, 2, &umr_bitfield_default },
+	 { "CMD_RDY_D1", 3, 3, &umr_bitfield_default },
+	 { "SLF_D0", 4, 4, &umr_bitfield_default },
+	 { "SLF_D1", 5, 5, &umr_bitfield_default },
+	 { "SS_SLF_D0", 6, 6, &umr_bitfield_default },
+	 { "SS_SLF_D1", 7, 7, &umr_bitfield_default },
+	 { "SEQ0_ARB_CMD_FIFO_EMPTY", 8, 8, &umr_bitfield_default },
+	 { "SEQ1_ARB_CMD_FIFO_EMPTY", 9, 9, &umr_bitfield_default },
+	 { "SEQ0_RS_DATA_FIFO_FULL", 12, 12, &umr_bitfield_default },
+	 { "SEQ1_RS_DATA_FIFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "SEQ0_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SEQ1_BUSY", 15, 15, &umr_bitfield_default },
+	 { "PMG_PWRSTATE", 16, 16, &umr_bitfield_default },
+	 { "PMG_FSMSTATE", 20, 24, &umr_bitfield_default },
+	 { "SEQ0_BUSY_HYS", 25, 25, &umr_bitfield_default },
+	 { "SEQ1_BUSY_HYS", 26, 26, &umr_bitfield_default },
+	 { "SEQ0_ALLOWSTOP", 27, 27, &umr_bitfield_default },
+	 { "SEQ1_ALLOWSTOP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_VENDOR_ID_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_VENDOR_ID_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RESERVE_M[] = {
+	 { "MCLK_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_EMRS[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CFG[] = {
+	 { "SYC_CLK", 0, 0, &umr_bitfield_default },
+	 { "RST_MRS", 1, 1, &umr_bitfield_default },
+	 { "RST_EMRS", 2, 2, &umr_bitfield_default },
+	 { "TRI_MIO", 3, 3, &umr_bitfield_default },
+	 { "XSR_TMR", 4, 7, &umr_bitfield_default },
+	 { "RST_MRS1", 8, 8, &umr_bitfield_default },
+	 { "RST_MRS2", 9, 9, &umr_bitfield_default },
+	 { "DPM_WAKE", 10, 10, &umr_bitfield_default },
+	 { "RFS_SRX", 12, 12, &umr_bitfield_default },
+	 { "PREA_SRX", 13, 13, &umr_bitfield_default },
+	 { "MRS_WAIT_CNT", 16, 19, &umr_bitfield_default },
+	 { "WRITE_DURING_DLOCK", 20, 20, &umr_bitfield_default },
+	 { "YCLK_ON", 21, 21, &umr_bitfield_default },
+	 { "EARLY_ACK_ACPI", 22, 22, &umr_bitfield_default },
+	 { "RXPDNB", 25, 25, &umr_bitfield_default },
+	 { "ZQCL_SEND", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP2_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP3_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_IR_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_DEC_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_PGM_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_R_PGM[] = {
+	 { "PGM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC3[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC4[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMP_CNTL[] = {
+	 { "CMP_MASK_BYTE", 0, 3, &umr_bitfield_default },
+	 { "CMP_MASK_BIT", 4, 11, &umr_bitfield_default },
+	 { "LOAD_RTEDC", 12, 12, &umr_bitfield_default },
+	 { "DATA_STORE_SEL", 13, 13, &umr_bitfield_default },
+	 { "EDC_STORE_SEL", 14, 14, &umr_bitfield_default },
+	 { "ENABLE_CMD_FIFO", 15, 15, &umr_bitfield_default },
+	 { "CMP", 16, 17, &umr_bitfield_default },
+	 { "DAT_MODE", 18, 18, &umr_bitfield_default },
+	 { "EDC_STORE_MODE", 19, 19, &umr_bitfield_default },
+	 { "DATA_STORE_MODE", 20, 21, &umr_bitfield_default },
+	 { "MISMATCH_CNT", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMD_CNTL[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "CMD_ISSUE_MODE", 1, 1, &umr_bitfield_default },
+	 { "CMD_ISSUE_LOOP", 2, 2, &umr_bitfield_default },
+	 { "LOOP_END_CONDITION", 3, 3, &umr_bitfield_default },
+	 { "LOOP_CNT_MAX", 4, 15, &umr_bitfield_default },
+	 { "CMD_ISSUE_MODE_U", 16, 16, &umr_bitfield_default },
+	 { "CMD_ISSUE_RUN", 17, 17, &umr_bitfield_default },
+	 { "LOOP_CNT_RD", 18, 27, &umr_bitfield_default },
+	 { "ENABLE_D0", 28, 28, &umr_bitfield_default },
+	 { "ENABLE_D1", 29, 29, &umr_bitfield_default },
+	 { "STATUS_CH", 30, 30, &umr_bitfield_default },
+	 { "DONE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP0_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SUP_GP1_STAT[] = {
+	 { "STATUS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_DEBUG_INDEX[] = {
+	 { "IO_DEBUG_INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_DEBUG_DATA[] = {
+	 { "IO_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BYTE_REMAP_D0[] = {
+	 { "BYTE0", 0, 1, &umr_bitfield_default },
+	 { "BYTE1", 2, 3, &umr_bitfield_default },
+	 { "BYTE2", 4, 5, &umr_bitfield_default },
+	 { "BYTE3", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BYTE_REMAP_D1[] = {
+	 { "BYTE0", 0, 1, &umr_bitfield_default },
+	 { "BYTE1", 2, 3, &umr_bitfield_default },
+	 { "BYTE2", 4, 5, &umr_bitfield_default },
+	 { "BYTE3", 6, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC5[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC6[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_APHY_STR_CNTL_D0[] = {
+	 { "PSTR_OFF_A", 0, 5, &umr_bitfield_default },
+	 { "NSTR_OFF_A", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_D_RD", 12, 17, &umr_bitfield_default },
+	 { "USE_A_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_D_RD_CAL", 25, 25, &umr_bitfield_default },
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_A_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_D_RD_STR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_APHY_STR_CNTL_D1[] = {
+	 { "PSTR_OFF_A", 0, 5, &umr_bitfield_default },
+	 { "NSTR_OFF_A", 6, 11, &umr_bitfield_default },
+	 { "PSTR_OFF_D_RD", 12, 17, &umr_bitfield_default },
+	 { "USE_A_CAL", 24, 24, &umr_bitfield_default },
+	 { "USE_D_RD_CAL", 25, 25, &umr_bitfield_default },
+	 { "CAL_SEL", 26, 27, &umr_bitfield_default },
+	 { "LOAD_A_STR", 28, 28, &umr_bitfield_default },
+	 { "LOAD_D_RD_STR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC7[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CG[] = {
+	 { "CG_SEQ_REQ", 0, 7, &umr_bitfield_default },
+	 { "CG_SEQ_RESP", 8, 15, &umr_bitfield_default },
+	 { "SEQ_CG_REQ", 16, 23, &umr_bitfield_default },
+	 { "SEQ_CG_RESP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RAS_TIMING_LP[] = {
+	 { "TRCDW", 0, 4, &umr_bitfield_default },
+	 { "TRCDWA", 5, 9, &umr_bitfield_default },
+	 { "TRCDR", 10, 14, &umr_bitfield_default },
+	 { "TRCDRA", 15, 19, &umr_bitfield_default },
+	 { "TRRD", 20, 23, &umr_bitfield_default },
+	 { "TRC", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CAS_TIMING_LP[] = {
+	 { "TNOPW", 0, 1, &umr_bitfield_default },
+	 { "TNOPR", 2, 3, &umr_bitfield_default },
+	 { "TR2W", 4, 8, &umr_bitfield_default },
+	 { "TCCDL", 9, 11, &umr_bitfield_default },
+	 { "TR2R", 12, 15, &umr_bitfield_default },
+	 { "TW2R", 16, 20, &umr_bitfield_default },
+	 { "TCL", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING_LP[] = {
+	 { "TRP_WRA", 0, 5, &umr_bitfield_default },
+	 { "TRP_RDA", 8, 13, &umr_bitfield_default },
+	 { "TRP", 15, 19, &umr_bitfield_default },
+	 { "TRFC", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC_TIMING2_LP[] = {
+	 { "PA2RDATA", 0, 2, &umr_bitfield_default },
+	 { "PA2WDATA", 4, 6, &umr_bitfield_default },
+	 { "FAW", 8, 12, &umr_bitfield_default },
+	 { "TREDC", 13, 15, &umr_bitfield_default },
+	 { "TWEDC", 16, 20, &umr_bitfield_default },
+	 { "TADR", 21, 23, &umr_bitfield_default },
+	 { "TFCKTR", 24, 27, &umr_bitfield_default },
+	 { "TWDATATR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D0_LP[] = {
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_D1_LP[] = {
+	 { "DAT_DLY", 0, 3, &umr_bitfield_default },
+	 { "DQS_DLY", 4, 7, &umr_bitfield_default },
+	 { "DQS_XTR", 8, 8, &umr_bitfield_default },
+	 { "DAT_2Y_DLY", 9, 9, &umr_bitfield_default },
+	 { "ADR_2Y_DLY", 10, 10, &umr_bitfield_default },
+	 { "CMD_2Y_DLY", 11, 11, &umr_bitfield_default },
+	 { "OEN_DLY", 12, 15, &umr_bitfield_default },
+	 { "OEN_EXT", 16, 19, &umr_bitfield_default },
+	 { "OEN_SEL", 20, 21, &umr_bitfield_default },
+	 { "ODT_DLY", 24, 27, &umr_bitfield_default },
+	 { "ODT_EXT", 28, 28, &umr_bitfield_default },
+	 { "ADR_DLY", 29, 29, &umr_bitfield_default },
+	 { "CMD_DLY", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_EMRS_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B0_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B1_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B2_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B3_D0[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B0_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B1_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B2_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_BIT_REMAP_B3_D1[] = {
+	 { "BIT0", 0, 2, &umr_bitfield_default },
+	 { "BIT1", 3, 5, &umr_bitfield_default },
+	 { "BIT2", 6, 8, &umr_bitfield_default },
+	 { "BIT3", 9, 11, &umr_bitfield_default },
+	 { "BIT4", 12, 14, &umr_bitfield_default },
+	 { "BIT5", 15, 17, &umr_bitfield_default },
+	 { "BIT6", 18, 20, &umr_bitfield_default },
+	 { "BIT7", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD0[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD1[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD2[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD3[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD4[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD5[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD6[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RWORD7[] = {
+	 { "RDATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RDBI[] = {
+	 { "MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_REDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_BIST_CMP_CNTL_2[] = {
+	 { "DATA_STORE_CNT", 0, 4, &umr_bitfield_default },
+	 { "DATA_STORE_CNT_RST", 8, 8, &umr_bitfield_default },
+	 { "EDC_STORE_CNT", 12, 16, &umr_bitfield_default },
+	 { "EDC_STORE_CNT_RST", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RESERVE_D0[] = {
+	 { "DPHY0_RSV", 0, 11, &umr_bitfield_default },
+	 { "DPHY1_RSV", 12, 23, &umr_bitfield_default },
+	 { "APHY_RSV", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_IO_RESERVE_D1[] = {
+	 { "DPHY0_RSV", 0, 11, &umr_bitfield_default },
+	 { "DPHY1_RSV", 12, 23, &umr_bitfield_default },
+	 { "APHY_RSV", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_HWCNTL[] = {
+	 { "PWRGATE_EN", 0, 0, &umr_bitfield_default },
+	 { "STAGGER_EN", 1, 1, &umr_bitfield_default },
+	 { "TPGCG", 2, 5, &umr_bitfield_default },
+	 { "D_DLY", 6, 7, &umr_bitfield_default },
+	 { "AC_DLY", 8, 9, &umr_bitfield_default },
+	 { "G_DLY", 10, 13, &umr_bitfield_default },
+	 { "TXAO", 16, 16, &umr_bitfield_default },
+	 { "RXAO", 17, 17, &umr_bitfield_default },
+	 { "ACAO", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_SWCNTL_0[] = {
+	 { "PMD0_DQ_TX_ENB", 0, 0, &umr_bitfield_default },
+	 { "PMD0_DBI_TX_ENB", 1, 1, &umr_bitfield_default },
+	 { "PMD0_EDC_TX_ENB", 2, 2, &umr_bitfield_default },
+	 { "PMD0_WCLKX_TX_ENB", 3, 3, &umr_bitfield_default },
+	 { "PMD0_DQ_RX_ENB", 4, 4, &umr_bitfield_default },
+	 { "PMD0_DBI_RX_ENB", 5, 5, &umr_bitfield_default },
+	 { "PMD0_EDC_RX_ENB", 6, 6, &umr_bitfield_default },
+	 { "PMD0_WCLKX_RX_ENB", 7, 7, &umr_bitfield_default },
+	 { "PMD1_DQ_TX_ENB", 8, 8, &umr_bitfield_default },
+	 { "PMD1_DBI_TX_ENB", 9, 9, &umr_bitfield_default },
+	 { "PMD1_EDC_TX_ENB", 10, 10, &umr_bitfield_default },
+	 { "PMD1_WCLKX_TX_ENB", 11, 11, &umr_bitfield_default },
+	 { "PMD1_DQ_RX_ENB", 12, 12, &umr_bitfield_default },
+	 { "PMD1_DBI_RX_ENB", 13, 13, &umr_bitfield_default },
+	 { "PMD1_EDC_RX_ENB", 14, 14, &umr_bitfield_default },
+	 { "PMD1_WCLKX_RX_ENB", 15, 15, &umr_bitfield_default },
+	 { "PMA0_AC_ENB", 16, 16, &umr_bitfield_default },
+	 { "GMCON_SR_COMMIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_PG_SWCNTL_1[] = {
+	 { "PMD2_DQ_TX_ENB", 0, 0, &umr_bitfield_default },
+	 { "PMD2_DBI_TX_ENB", 1, 1, &umr_bitfield_default },
+	 { "PMD2_EDC_TX_ENB", 2, 2, &umr_bitfield_default },
+	 { "PMD2_WCLKX_TX_ENB", 3, 3, &umr_bitfield_default },
+	 { "PMD2_DQ_RX_ENB", 4, 4, &umr_bitfield_default },
+	 { "PMD2_DBI_RX_ENB", 5, 5, &umr_bitfield_default },
+	 { "PMD2_EDC_RX_ENB", 6, 6, &umr_bitfield_default },
+	 { "PMD2_WCLKX_RX_ENB", 7, 7, &umr_bitfield_default },
+	 { "PMD3_DQ_TX_ENB", 8, 8, &umr_bitfield_default },
+	 { "PMD3_DBI_TX_ENB", 9, 9, &umr_bitfield_default },
+	 { "PMD3_EDC_TX_ENB", 10, 10, &umr_bitfield_default },
+	 { "PMD3_WCLKX_TX_ENB", 11, 11, &umr_bitfield_default },
+	 { "PMD3_DQ_RX_ENB", 12, 12, &umr_bitfield_default },
+	 { "PMD3_DBI_RX_ENB", 13, 13, &umr_bitfield_default },
+	 { "PMD3_EDC_RX_ENB", 14, 14, &umr_bitfield_default },
+	 { "PMD3_WCLKX_RX_ENB", 15, 15, &umr_bitfield_default },
+	 { "PMA1_AC_ENB", 16, 16, &umr_bitfield_default },
+	 { "GMCON_SR_COMMIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IMP_DQ_STATUS[] = {
+	 { "CH0_DQ_PSTR", 0, 7, &umr_bitfield_default },
+	 { "CH0_DQ_NSTR", 8, 15, &umr_bitfield_default },
+	 { "CH1_DQ_PSTR", 16, 23, &umr_bitfield_default },
+	 { "CH1_DQ_NSTR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TCG_CNTL[] = {
+	 { "RESET", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_D0", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_D1", 2, 2, &umr_bitfield_default },
+	 { "START", 3, 3, &umr_bitfield_default },
+	 { "NFIFO", 4, 6, &umr_bitfield_default },
+	 { "INFINITE_CMD", 7, 7, &umr_bitfield_default },
+	 { "MOP", 8, 11, &umr_bitfield_default },
+	 { "DATA_CNT", 12, 15, &umr_bitfield_default },
+	 { "LOAD_FIFO", 16, 16, &umr_bitfield_default },
+	 { "SHORT_LDFF", 17, 17, &umr_bitfield_default },
+	 { "FRAME_TRAIN", 18, 18, &umr_bitfield_default },
+	 { "BURST_NUM", 19, 21, &umr_bitfield_default },
+	 { "ISSUE_AREF", 22, 22, &umr_bitfield_default },
+	 { "TXDBI_CNTL", 23, 23, &umr_bitfield_default },
+	 { "VPTR_MASK", 24, 24, &umr_bitfield_default },
+	 { "AREF_LAST", 25, 25, &umr_bitfield_default },
+	 { "AREF_BOTH", 26, 26, &umr_bitfield_default },
+	 { "LD_RTDATA_OVR", 28, 28, &umr_bitfield_default },
+	 { "LD_RTDATA_CH", 29, 29, &umr_bitfield_default },
+	 { "DONE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_CTRL[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "CAPTURE_START", 1, 1, &umr_bitfield_default },
+	 { "DONE", 2, 2, &umr_bitfield_default },
+	 { "ERR", 3, 3, &umr_bitfield_default },
+	 { "STEP", 4, 4, &umr_bitfield_default },
+	 { "DIRECTION", 5, 5, &umr_bitfield_default },
+	 { "INVERT", 6, 6, &umr_bitfield_default },
+	 { "MASK_BITS", 7, 7, &umr_bitfield_default },
+	 { "UPDATE_LOOP", 8, 9, &umr_bitfield_default },
+	 { "ROT_INV", 10, 10, &umr_bitfield_default },
+	 { "DUAL_CH_EN", 11, 11, &umr_bitfield_default },
+	 { "DONE0", 12, 12, &umr_bitfield_default },
+	 { "DONE1", 13, 13, &umr_bitfield_default },
+	 { "POINTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_GCNT[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "COMP_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_OCNT[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "CMP_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_NCNT[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "TESTS", 8, 15, &umr_bitfield_default },
+	 { "RANGE_LOW", 16, 19, &umr_bitfield_default },
+	 { "RANGE_HIGH", 20, 23, &umr_bitfield_default },
+	 { "NIBBLE_SKIP", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_BCNT[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "BCNT_TESTS", 8, 15, &umr_bitfield_default },
+	 { "COMP_VALUE", 16, 23, &umr_bitfield_default },
+	 { "DONE_TESTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_FLAG[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "FLAG_TESTS", 8, 15, &umr_bitfield_default },
+	 { "NBBL_MASK", 16, 19, &umr_bitfield_default },
+	 { "ERROR_TESTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_UPDATE[] = {
+	 { "TRUE_ACT", 0, 3, &umr_bitfield_default },
+	 { "FALSE_ACT", 4, 7, &umr_bitfield_default },
+	 { "UPDT_TESTS", 8, 15, &umr_bitfield_default },
+	 { "AREF_COUNT", 16, 23, &umr_bitfield_default },
+	 { "CAPTR_TESTS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_EDC[] = {
+	 { "EDC", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DBI[] = {
+	 { "DBI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D0_LP[] = {
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_RD_CTL_D1_LP[] = {
+	 { "RCV_DLY", 0, 2, &umr_bitfield_default },
+	 { "RCV_EXT", 3, 7, &umr_bitfield_default },
+	 { "RST_SEL", 8, 9, &umr_bitfield_default },
+	 { "RXDPWRON_DLY", 10, 11, &umr_bitfield_default },
+	 { "RST_HLD", 12, 15, &umr_bitfield_default },
+	 { "STR_PRE", 16, 16, &umr_bitfield_default },
+	 { "STR_PST", 17, 17, &umr_bitfield_default },
+	 { "RBS_DLY", 20, 24, &umr_bitfield_default },
+	 { "RBS_WEDC_DLY", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TIMER_WR[] = {
+	 { "COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TIMER_RD[] = {
+	 { "COUNTER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DRAM_ERROR_INSERTION[] = {
+	 { "TX", 0, 15, &umr_bitfield_default },
+	 { "RX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_D0[] = {
+	 { "RXC0_DLY", 0, 3, &umr_bitfield_default },
+	 { "RXC0_EXT", 4, 7, &umr_bitfield_default },
+	 { "RXC1_DLY", 8, 11, &umr_bitfield_default },
+	 { "RXC1_EXT", 12, 15, &umr_bitfield_default },
+	 { "TXC0_DLY", 16, 18, &umr_bitfield_default },
+	 { "TXC0_EXT", 20, 23, &umr_bitfield_default },
+	 { "TXC1_DLY", 24, 26, &umr_bitfield_default },
+	 { "TXC1_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_D1[] = {
+	 { "RXC0_DLY", 0, 3, &umr_bitfield_default },
+	 { "RXC0_EXT", 4, 7, &umr_bitfield_default },
+	 { "RXC1_DLY", 8, 11, &umr_bitfield_default },
+	 { "RXC1_EXT", 12, 15, &umr_bitfield_default },
+	 { "TXC0_DLY", 16, 18, &umr_bitfield_default },
+	 { "TXC0_EXT", 20, 23, &umr_bitfield_default },
+	 { "TXC1_DLY", 24, 26, &umr_bitfield_default },
+	 { "TXC1_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PHY_TIMING_2[] = {
+	 { "IND_LD_CNT", 0, 6, &umr_bitfield_default },
+	 { "RXC0_INV", 8, 8, &umr_bitfield_default },
+	 { "RXC1_INV", 9, 9, &umr_bitfield_default },
+	 { "TXC0_INV", 10, 10, &umr_bitfield_default },
+	 { "TXC1_INV", 11, 11, &umr_bitfield_default },
+	 { "RXC0_FRC", 12, 12, &umr_bitfield_default },
+	 { "RXC1_FRC", 13, 13, &umr_bitfield_default },
+	 { "TXC0_FRC", 14, 14, &umr_bitfield_default },
+	 { "TXC1_FRC", 15, 15, &umr_bitfield_default },
+	 { "TX_CDREN_D0", 16, 16, &umr_bitfield_default },
+	 { "TX_CDREN_D1", 17, 17, &umr_bitfield_default },
+	 { "ADR_CLKEN_D0", 18, 18, &umr_bitfield_default },
+	 { "ADR_CLKEN_D1", 19, 19, &umr_bitfield_default },
+	 { "WR_DLY", 20, 23, &umr_bitfield_default },
+	 { "RXDPWRONC0_FRC", 24, 24, &umr_bitfield_default },
+	 { "RXDPWRONC1_FRC", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DEBUG_INDEX[] = {
+	 { "TSM_DEBUG_INDEX", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_DEBUG_DATA[] = {
+	 { "TSM_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS1[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS1_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_TIMING_LP[] = {
+	 { "TCKSRE", 0, 2, &umr_bitfield_default },
+	 { "TCKSRX", 4, 6, &umr_bitfield_default },
+	 { "TCKE_PULSE", 8, 11, &umr_bitfield_default },
+	 { "TCKE", 12, 17, &umr_bitfield_default },
+	 { "SEQ_IDLE", 18, 20, &umr_bitfield_default },
+	 { "TCKE_PULSE_MSB", 23, 23, &umr_bitfield_default },
+	 { "SEQ_IDLE_SS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CNTL_2[] = {
+	 { "DRST_PDRV", 0, 3, &umr_bitfield_default },
+	 { "DRST_PU", 4, 4, &umr_bitfield_default },
+	 { "DRST_PD", 5, 5, &umr_bitfield_default },
+	 { "ARB_RTDAT_WMK_MSB", 8, 9, &umr_bitfield_default },
+	 { "DRST_NSTR", 10, 15, &umr_bitfield_default },
+	 { "DRST_PSTR", 16, 21, &umr_bitfield_default },
+	 { "PLL_TX_PWRON_D0", 22, 22, &umr_bitfield_default },
+	 { "PLL_TX_PWRON_D1", 23, 23, &umr_bitfield_default },
+	 { "PLL_RX_PWRON_D0", 24, 27, &umr_bitfield_default },
+	 { "PLL_RX_PWRON_D1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_2[] = {
+	 { "DAT_DLY_H_D0", 0, 0, &umr_bitfield_default },
+	 { "DQS_DLY_H_D0", 1, 1, &umr_bitfield_default },
+	 { "OEN_DLY_H_D0", 2, 2, &umr_bitfield_default },
+	 { "DAT_DLY_H_D1", 3, 3, &umr_bitfield_default },
+	 { "DQS_DLY_H_D1", 4, 4, &umr_bitfield_default },
+	 { "OEN_DLY_H_D1", 5, 5, &umr_bitfield_default },
+	 { "WCDR_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_WR_CTL_2_LP[] = {
+	 { "DAT_DLY_H_D0", 0, 0, &umr_bitfield_default },
+	 { "DQS_DLY_H_D0", 1, 1, &umr_bitfield_default },
+	 { "OEN_DLY_H_D0", 2, 2, &umr_bitfield_default },
+	 { "DAT_DLY_H_D1", 3, 3, &umr_bitfield_default },
+	 { "DQS_DLY_H_D1", 4, 4, &umr_bitfield_default },
+	 { "OEN_DLY_H_D1", 5, 5, &umr_bitfield_default },
+	 { "WCDR_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_PMG_CMD_MRS2[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_CMD_MRS2_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 28, 28, &umr_bitfield_default },
+	 { "ADR_MSB0", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_C_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_C_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_D_I0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_SEQ_CNT_D_I1[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL1_D0[] = {
+	 { "DQ_RXPHASE_B0", 0, 7, &umr_bitfield_default },
+	 { "DQ_RXPHASE_B1", 8, 15, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B0", 16, 23, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL1_D1[] = {
+	 { "DQ_RXPHASE_B0", 0, 7, &umr_bitfield_default },
+	 { "DQ_RXPHASE_B1", 8, 15, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B0", 16, 23, &umr_bitfield_default },
+	 { "WCDR_TXPHASE_B1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY0_D0[] = {
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "DLL_PWRGOOD_OVR", 19, 19, &umr_bitfield_default },
+	 { "DLL_VCTRLADC_EN", 20, 20, &umr_bitfield_default },
+	 { "DLL_MSTR_STBY", 21, 21, &umr_bitfield_default },
+	 { "RXLEQ_EN", 22, 22, &umr_bitfield_default },
+	 { "RXLEQ_NXT", 23, 23, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY1_D0[] = {
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "DLL_PWRGOOD_OVR", 19, 19, &umr_bitfield_default },
+	 { "DLL_VCTRLADC_EN", 20, 20, &umr_bitfield_default },
+	 { "DLL_MSTR_STBY", 21, 21, &umr_bitfield_default },
+	 { "RXLEQ_EN", 22, 22, &umr_bitfield_default },
+	 { "RXLEQ_NXT", 23, 23, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY0_D1[] = {
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "DLL_PWRGOOD_OVR", 19, 19, &umr_bitfield_default },
+	 { "DLL_VCTRLADC_EN", 20, 20, &umr_bitfield_default },
+	 { "DLL_MSTR_STBY", 21, 21, &umr_bitfield_default },
+	 { "RXLEQ_EN", 22, 22, &umr_bitfield_default },
+	 { "RXLEQ_NXT", 23, 23, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_RXCNTL1_DPHY1_D1[] = {
+	 { "VREFCAL1_MSB", 0, 3, &umr_bitfield_default },
+	 { "VREFCAL2_MSB", 4, 7, &umr_bitfield_default },
+	 { "VREFCAL3", 8, 15, &umr_bitfield_default },
+	 { "VREFSEL2", 16, 16, &umr_bitfield_default },
+	 { "VREFSEL3", 17, 17, &umr_bitfield_default },
+	 { "VREFPDNB_1", 18, 18, &umr_bitfield_default },
+	 { "DLL_PWRGOOD_OVR", 19, 19, &umr_bitfield_default },
+	 { "DLL_VCTRLADC_EN", 20, 20, &umr_bitfield_default },
+	 { "DLL_MSTR_STBY", 21, 21, &umr_bitfield_default },
+	 { "RXLEQ_EN", 22, 22, &umr_bitfield_default },
+	 { "RXLEQ_NXT", 23, 23, &umr_bitfield_default },
+	 { "PMD_LOOPBACK", 25, 27, &umr_bitfield_default },
+	 { "DLL_RSV", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_WCDR[] = {
+	 { "WCDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL2_D0[] = {
+	 { "CDR_FB_SEL0", 0, 0, &umr_bitfield_default },
+	 { "CDR_FB_SEL1", 1, 1, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR0", 2, 2, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR1", 3, 3, &umr_bitfield_default },
+	 { "TXCDRBYPASS0", 4, 4, &umr_bitfield_default },
+	 { "TXCDRBYPASS1", 5, 5, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR0", 6, 6, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR1", 7, 7, &umr_bitfield_default },
+	 { "WCDRTXPWRON", 8, 11, &umr_bitfield_default },
+	 { "WCDRTXSEL", 12, 15, &umr_bitfield_default },
+	 { "WCDRTRACK01", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_IO_CDRCNTL2_D1[] = {
+	 { "CDR_FB_SEL0", 0, 0, &umr_bitfield_default },
+	 { "CDR_FB_SEL1", 1, 1, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR0", 2, 2, &umr_bitfield_default },
+	 { "EDC_RXEN_OVR1", 3, 3, &umr_bitfield_default },
+	 { "TXCDRBYPASS0", 4, 4, &umr_bitfield_default },
+	 { "TXCDRBYPASS1", 5, 5, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR0", 6, 6, &umr_bitfield_default },
+	 { "WCK_RXEN_OVR1", 7, 7, &umr_bitfield_default },
+	 { "WCDRTXPWRON", 8, 11, &umr_bitfield_default },
+	 { "WCDRTXSEL", 12, 15, &umr_bitfield_default },
+	 { "WCDRTRACK01", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TSM_MISC[] = {
+	 { "WCDR_PTR", 0, 15, &umr_bitfield_default },
+	 { "WCDR_MASK", 16, 19, &umr_bitfield_default },
+	 { "CH1_OFFSET", 20, 25, &umr_bitfield_default },
+	 { "CH1_WCDR_OFFSET", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_MISC9[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCLK_PWRMGT_CNTL[] = {
+	 { "DLL_SPEED", 0, 4, &umr_bitfield_default },
+	 { "DLL_READY", 6, 6, &umr_bitfield_default },
+	 { "MC_INT_CNTL", 7, 7, &umr_bitfield_default },
+	 { "MRDCK0_PDNB", 8, 8, &umr_bitfield_default },
+	 { "MRDCK1_PDNB", 9, 9, &umr_bitfield_default },
+	 { "MRDCK0_RESET", 16, 16, &umr_bitfield_default },
+	 { "MRDCK1_RESET", 17, 17, &umr_bitfield_default },
+	 { "DLL_READY_READ", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDLL_CNTL[] = {
+	 { "DLL_RESET_TIME", 0, 9, &umr_bitfield_default },
+	 { "DLL_LOCK_TIME", 12, 21, &umr_bitfield_default },
+	 { "MRDCK0_BYPASS", 24, 24, &umr_bitfield_default },
+	 { "MRDCK1_BYPASS", 25, 25, &umr_bitfield_default },
+	 { "PWR2_MODE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SEQ_UCODE_1[] = {
+	 { "INSTR0", 0, 3, &umr_bitfield_default },
+	 { "INSTR1", 4, 7, &umr_bitfield_default },
+	 { "INSTR2", 8, 11, &umr_bitfield_default },
+	 { "INSTR3", 12, 15, &umr_bitfield_default },
+	 { "INSTR4", 16, 19, &umr_bitfield_default },
+	 { "INSTR5", 20, 23, &umr_bitfield_default },
+	 { "INSTR6", 24, 27, &umr_bitfield_default },
+	 { "INSTR7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SEQ_UCODE_2[] = {
+	 { "INSTR8", 0, 3, &umr_bitfield_default },
+	 { "INSTR9", 4, 7, &umr_bitfield_default },
+	 { "INSTR10", 8, 11, &umr_bitfield_default },
+	 { "INSTR11", 12, 15, &umr_bitfield_default },
+	 { "INSTR12", 16, 19, &umr_bitfield_default },
+	 { "INSTR13", 20, 23, &umr_bitfield_default },
+	 { "INSTR14", 24, 27, &umr_bitfield_default },
+	 { "INSTR15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_CNTL_MODE[] = {
+	 { "INSTR_DELAY", 0, 7, &umr_bitfield_default },
+	 { "MPLL_SW_DIR_CONTROL", 8, 8, &umr_bitfield_default },
+	 { "GDDR_PWRON_OVR", 9, 9, &umr_bitfield_default },
+	 { "MPLL_MCLK_SEL", 11, 11, &umr_bitfield_default },
+	 { "SPARE_1", 12, 12, &umr_bitfield_default },
+	 { "QDR", 13, 13, &umr_bitfield_default },
+	 { "MPLL_CTLREQ", 14, 14, &umr_bitfield_default },
+	 { "MPLL_CHG_STATUS", 16, 16, &umr_bitfield_default },
+	 { "FORCE_TESTMODE", 17, 17, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 20, 20, &umr_bitfield_default },
+	 { "FAST_LOCK_CNTRL", 21, 22, &umr_bitfield_default },
+	 { "SPARE_2", 23, 23, &umr_bitfield_default },
+	 { "SS_SSEN", 24, 25, &umr_bitfield_default },
+	 { "SS_DSMODE_EN", 26, 26, &umr_bitfield_default },
+	 { "VTOI_BIAS_CNTRL", 27, 27, &umr_bitfield_default },
+	 { "SPARE_3", 28, 30, &umr_bitfield_default },
+	 { "GLOBAL_MPLL_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL[] = {
+	 { "SPARE_0", 5, 5, &umr_bitfield_default },
+	 { "BG_100ADJ", 8, 11, &umr_bitfield_default },
+	 { "BG_135ADJ", 16, 19, &umr_bitfield_default },
+	 { "BWCTRL", 20, 27, &umr_bitfield_default },
+	 { "REG_BIAS", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL_1[] = {
+	 { "VCO_MODE", 0, 1, &umr_bitfield_default },
+	 { "SPARE_0", 2, 3, &umr_bitfield_default },
+	 { "CLKFRAC", 4, 15, &umr_bitfield_default },
+	 { "CLKF", 16, 27, &umr_bitfield_default },
+	 { "SPARE_1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_FUNC_CNTL_2[] = {
+	 { "VCTRLADC_EN", 0, 0, &umr_bitfield_default },
+	 { "TEST_VCTL_EN", 1, 1, &umr_bitfield_default },
+	 { "RESET_EN", 2, 2, &umr_bitfield_default },
+	 { "TEST_BYPCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "TEST_BYPCLK_SRC", 4, 4, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC_BYPASS", 5, 5, &umr_bitfield_default },
+	 { "TEST_BYPMCLK", 6, 6, &umr_bitfield_default },
+	 { "MPLL_UNLOCK_CLEAR", 7, 7, &umr_bitfield_default },
+	 { "TEST_VCTL_CNTRL", 8, 8, &umr_bitfield_default },
+	 { "TEST_FBDIV_SSC_BYPASS", 9, 9, &umr_bitfield_default },
+	 { "RESET_TIMER", 10, 11, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 12, 13, &umr_bitfield_default },
+	 { "RISEFBVCO_EN", 14, 14, &umr_bitfield_default },
+	 { "PWRGOOD_OVR", 15, 15, &umr_bitfield_default },
+	 { "ISO_DIS_P", 16, 16, &umr_bitfield_default },
+	 { "BACKUP_2", 17, 19, &umr_bitfield_default },
+	 { "LF_CNTRL", 20, 26, &umr_bitfield_default },
+	 { "BACKUP", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_MISC_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_AD_FUNC_CNTL[] = {
+	 { "YCLK_POST_DIV", 0, 2, &umr_bitfield_default },
+	 { "SPARE", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_FUNC_CNTL[] = {
+	 { "YCLK_POST_DIV", 0, 2, &umr_bitfield_default },
+	 { "SPARE_0", 3, 3, &umr_bitfield_default },
+	 { "YCLK_SEL", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_TIME[] = {
+	 { "MPLL_LOCK_TIME", 0, 15, &umr_bitfield_default },
+	 { "MPLL_RESET_TIME", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SS1[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+	 { "SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_SS2[] = {
+	 { "CLKS", 0, 11, &umr_bitfield_default },
+	 { "SPARE", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_CONTROL[] = {
+	 { "GDDR_PWRON", 0, 0, &umr_bitfield_default },
+	 { "REFCLK_PWRON", 1, 1, &umr_bitfield_default },
+	 { "PLL_BUF_PWRON_TX", 2, 2, &umr_bitfield_default },
+	 { "AD_BG_PWRON", 12, 12, &umr_bitfield_default },
+	 { "AD_PLL_PWRON", 13, 13, &umr_bitfield_default },
+	 { "AD_PLL_RESET", 14, 14, &umr_bitfield_default },
+	 { "SPARE_AD_0", 15, 15, &umr_bitfield_default },
+	 { "DQ_0_0_BG_PWRON", 16, 16, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_PWRON", 17, 17, &umr_bitfield_default },
+	 { "DQ_0_0_PLL_RESET", 18, 18, &umr_bitfield_default },
+	 { "SPARE_DQ_0_0", 19, 19, &umr_bitfield_default },
+	 { "DQ_0_1_BG_PWRON", 20, 20, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_PWRON", 21, 21, &umr_bitfield_default },
+	 { "DQ_0_1_PLL_RESET", 22, 22, &umr_bitfield_default },
+	 { "SPARE_DQ_0_1", 23, 23, &umr_bitfield_default },
+	 { "DQ_1_0_BG_PWRON", 24, 24, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_PWRON", 25, 25, &umr_bitfield_default },
+	 { "DQ_1_0_PLL_RESET", 26, 26, &umr_bitfield_default },
+	 { "SPARE_DQ_1_0", 27, 27, &umr_bitfield_default },
+	 { "DQ_1_1_BG_PWRON", 28, 28, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_PWRON", 29, 29, &umr_bitfield_default },
+	 { "DQ_1_1_PLL_RESET", 30, 30, &umr_bitfield_default },
+	 { "SPARE_DQ_1_1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_AD_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_0_0_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_0_1_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_1_0_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMPLL_DQ_1_1_STATUS[] = {
+	 { "VCTRLADC", 0, 2, &umr_bitfield_default },
+	 { "TEST_FBDIV_FRAC", 4, 6, &umr_bitfield_default },
+	 { "TEST_FBDIV_INT", 7, 16, &umr_bitfield_default },
+	 { "OINT_RESET", 17, 17, &umr_bitfield_default },
+	 { "FREQ_LOCK", 18, 18, &umr_bitfield_default },
+	 { "FREQ_UNLOCK_STICKY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_2_D0[] = {
+	 { "CK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CKB_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CS_STATUS", 4, 5, &umr_bitfield_default },
+	 { "CKE_STATUS", 8, 8, &umr_bitfield_default },
+	 { "RAS_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CAS_STATUS", 10, 10, &umr_bitfield_default },
+	 { "WE_STATUS", 11, 11, &umr_bitfield_default },
+	 { "ADDR_STATUS", 16, 25, &umr_bitfield_default },
+	 { "ABI_STATUS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_TRAIN_PRBSERR_2_D1[] = {
+	 { "CK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CKB_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CS_STATUS", 4, 5, &umr_bitfield_default },
+	 { "CKE_STATUS", 8, 8, &umr_bitfield_default },
+	 { "RAS_STATUS", 9, 9, &umr_bitfield_default },
+	 { "CAS_STATUS", 10, 10, &umr_bitfield_default },
+	 { "WE_STATUS", 11, 11, &umr_bitfield_default },
+	 { "ADDR_STATUS", 16, 25, &umr_bitfield_default },
+	 { "ABI_STATUS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PERF_CNTL_1[] = {
+	 { "PAUSE", 0, 0, &umr_bitfield_default },
+	 { "SEL_A_MSB", 8, 8, &umr_bitfield_default },
+	 { "SEL_B_MSB", 9, 9, &umr_bitfield_default },
+	 { "SEL_CH0_C_MSB", 10, 10, &umr_bitfield_default },
+	 { "SEL_CH0_D_MSB", 11, 11, &umr_bitfield_default },
+	 { "SEL_CH1_A_MSB", 12, 12, &umr_bitfield_default },
+	 { "SEL_CH1_B_MSB", 13, 13, &umr_bitfield_default },
+	 { "SEL_CH1_C_MSB", 14, 14, &umr_bitfield_default },
+	 { "SEL_CH1_D_MSB", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD2[] = {
+	 { "THRESHOLD_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_TRAIN_EDC_THRESHOLD3[] = {
+	 { "CH0_LINK_RETRAIN_STATUS", 0, 0, &umr_bitfield_default },
+	 { "CH1_LINK_RETRAIN_STATUS", 1, 1, &umr_bitfield_default },
+	 { "CLEAR_RETRAIN_STATUS", 2, 2, &umr_bitfield_default },
+	 { "RETRAIN_VBI", 3, 3, &umr_bitfield_default },
+	 { "RETRAIN_MONITOR", 4, 5, &umr_bitfield_default },
+	 { "CH0_LINK_RETRAIN_IN_PROGRESS", 8, 8, &umr_bitfield_default },
+	 { "CH1_LINK_RETRAIN_IN_PROGRESS", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT8[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_11[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_MISC_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT9[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_12[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ADDR_DEC[] = {
+	 { "NO_DIV_BY_3", 0, 0, &umr_bitfield_default },
+	 { "GECC", 1, 1, &umr_bitfield_default },
+	 { "RB_SPLIT", 2, 2, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_REMOTE[] = {
+	 { "WRREQ_EN_GOQ", 0, 0, &umr_bitfield_default },
+	 { "RDREQ_EN_GOQ", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_PRI_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+	 { "HUB_LP_RDRET_SKID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_CHTRIREMAP[] = {
+	 { "CH0", 0, 1, &umr_bitfield_default },
+	 { "CH1", 2, 3, &umr_bitfield_default },
+	 { "CH2", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_TWOCHAN[] = {
+	 { "DISABLE_ONEPORT", 0, 0, &umr_bitfield_default },
+	 { "CH0", 1, 2, &umr_bitfield_default },
+	 { "CH1", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB[] = {
+	 { "HUBRD_HIGHEST", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_HUB_STALL_HIGHEST", 1, 1, &umr_bitfield_default },
+	 { "BREAK_BURST_CID_CHANGE", 2, 2, &umr_bitfield_default },
+	 { "ACP_RDRET_URG", 3, 3, &umr_bitfield_default },
+	 { "HDP_RDRET_URG", 4, 4, &umr_bitfield_default },
+	 { "BREAK_BURST_BY_URG", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB_MAX_BURST[] = {
+	 { "RD_PORT0", 0, 3, &umr_bitfield_default },
+	 { "RD_PORT1", 4, 7, &umr_bitfield_default },
+	 { "RD_PORT2", 8, 11, &umr_bitfield_default },
+	 { "RD_PORT3", 12, 15, &umr_bitfield_default },
+	 { "WR_PORT0", 16, 19, &umr_bitfield_default },
+	 { "WR_PORT1", 20, 23, &umr_bitfield_default },
+	 { "WR_PORT2", 24, 27, &umr_bitfield_default },
+	 { "WR_PORT3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_CNTL0[] = {
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_CNTL1[] = {
+	 { "THRESH_CNTR_ID", 0, 7, &umr_bitfield_default },
+	 { "START_TRIG_ID", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_CNTL2[] = {
+	 { "MON0_ID", 0, 7, &umr_bitfield_default },
+	 { "MON1_ID", 8, 15, &umr_bitfield_default },
+	 { "MON2_ID", 16, 23, &umr_bitfield_default },
+	 { "MON3_ID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_RSLT2[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_RSLT3[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_MAX_THSH[] = {
+	 { "MON0", 0, 7, &umr_bitfield_default },
+	 { "MON1", 8, 15, &umr_bitfield_default },
+	 { "MON2", 16, 23, &umr_bitfield_default },
+	 { "MON3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE0[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE1[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_CNTL[] = {
+	 { "DISABLE_ATC", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_PRI", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_PASID", 2, 2, &umr_bitfield_default },
+	 { "CREDITS_ATS_RPB", 8, 13, &umr_bitfield_default },
+	 { "DEBUG_ECO", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEBUG[] = {
+	 { "INVALIDATE_ALL", 0, 0, &umr_bitfield_default },
+	 { "IDENT_RETURN", 1, 1, &umr_bitfield_default },
+	 { "ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS", 2, 2, &umr_bitfield_default },
+	 { "PAGE_REQUESTS_USE_RELAXED_ORDERING", 5, 5, &umr_bitfield_default },
+	 { "PRIV_BIT", 6, 6, &umr_bitfield_default },
+	 { "EXE_BIT", 7, 7, &umr_bitfield_default },
+	 { "PAGE_REQUEST_PERMS", 8, 8, &umr_bitfield_default },
+	 { "UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE", 9, 9, &umr_bitfield_default },
+	 { "NUM_REQUESTS_AT_ERR", 10, 13, &umr_bitfield_default },
+	 { "DISALLOW_ERR_TO_DONE", 14, 14, &umr_bitfield_default },
+	 { "IGNORE_FED", 15, 15, &umr_bitfield_default },
+	 { "INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_BUS_SELECT", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_VMID0_PASID_MAPPING", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATION_ON_WORLD_SWITCH", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_DEBUG[] = {
+	 { "CREDITS_ATS_IH", 0, 4, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES", 8, 8, &umr_bitfield_default },
+	 { "CLEAR_FAULT_STATUS_ADDR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "CRASHED", 1, 1, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_CNTL[] = {
+	 { "FAULT_REGISTER_LOG", 0, 8, &umr_bitfield_default },
+	 { "FAULT_INTERRUPT_TABLE", 10, 18, &umr_bitfield_default },
+	 { "FAULT_CRASH_TABLE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_INFO[] = {
+	 { "FAULT_TYPE", 0, 8, &umr_bitfield_default },
+	 { "VMID", 10, 14, &umr_bitfield_default },
+	 { "EXTRA_INFO", 15, 15, &umr_bitfield_default },
+	 { "EXTRA_INFO2", 16, 16, &umr_bitfield_default },
+	 { "INVALIDATION", 17, 17, &umr_bitfield_default },
+	 { "PAGE_REQUEST", 18, 18, &umr_bitfield_default },
+	 { "STATUS", 19, 23, &umr_bitfield_default },
+	 { "PAGE_ADDR_HIGH", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_ADDR[] = {
+	 { "PAGE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_LOW[] = {
+	 { "DEFAULT_PAGE", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_CNTL[] = {
+	 { "SEND_DEFAULT_PAGE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_INFO2[] = {
+	 { "VF", 0, 0, &umr_bitfield_default },
+	 { "VFID", 1, 5, &umr_bitfield_default },
+	 { "L1_ID", 9, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_MISC_CG[] = {
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL[] = {
+	 { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 4, 5, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 8, 8, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL2[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE", 8, 8, &umr_bitfield_default },
+	 { "L2_CACHE_SWAP_TAG_INDEX_LSBS", 9, 11, &umr_bitfield_default },
+	 { "L2_CACHE_VMID_MODE", 12, 14, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 15, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG[] = {
+	 { "CREDITS_L2_ATS", 0, 5, &umr_bitfield_default },
+	 { "L2_MEM_SELECT", 7, 7, &umr_bitfield_default },
+	 { "CACHE_INDEX", 8, 19, &umr_bitfield_default },
+	 { "CACHE_SELECT", 24, 24, &umr_bitfield_default },
+	 { "CACHE_BANK_SELECT", 25, 25, &umr_bitfield_default },
+	 { "CACHE_WAY_SELECT", 27, 27, &umr_bitfield_default },
+	 { "CACHE_READ", 29, 29, &umr_bitfield_default },
+	 { "CACHE_INJECT_SOFT_PARITY_ERROR", 30, 30, &umr_bitfield_default },
+	 { "CACHE_INJECT_HARD_PARITY_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG2[] = {
+	 { "EFFECTIVE_CACHE_SIZE", 0, 4, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 5, 7, &umr_bitfield_default },
+	 { "FORCE_CACHE_MISS", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_2M_CACHE", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CACHING_SPECULATIVE_RETURNS", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_BUS_SELECT", 15, 16, &umr_bitfield_default },
+	 { "DEBUG_ECO", 17, 18, &umr_bitfield_default },
+	 { "EFFECTIVE_2M_CACHE_SIZE", 19, 22, &umr_bitfield_default },
+	 { "CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD", 23, 30, &umr_bitfield_default },
+	 { "CLEAR_PARITY_ERROR_INFO", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CACHE_DATA0[] = {
+	 { "DATA_REGISTER_VALID", 0, 0, &umr_bitfield_default },
+	 { "CACHE_ENTRY_VALID", 1, 1, &umr_bitfield_default },
+	 { "CACHED_ATTRIBUTES", 2, 24, &umr_bitfield_default },
+	 { "VIRTUAL_PAGE_ADDRESS_HIGH", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CACHE_DATA1[] = {
+	 { "VIRTUAL_PAGE_ADDRESS_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CACHE_DATA2[] = {
+	 { "PHYSICAL_PAGE_ADDRESS_LOW", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_CNTL[] = {
+	 { "DONT_NEED_ATS_BEHAVIOR", 0, 1, &umr_bitfield_default },
+	 { "NEED_ATS_BEHAVIOR", 2, 2, &umr_bitfield_default },
+	 { "NEED_ATS_SNOOP_DEFAULT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_ADDRESS_OFFSET[] = {
+	 { "LOGICAL_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+	 { "CAM_PARITY_ERRORS", 12, 16, &umr_bitfield_default },
+	 { "CAM_INDEX", 17, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+	 { "CAM_PARITY_ERRORS", 12, 16, &umr_bitfield_default },
+	 { "CAM_INDEX", 17, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_DEBUG2_TLB[] = {
+	 { "XNACK_RETRY_PERIOD", 0, 11, &umr_bitfield_default },
+	 { "XNACK_RETRY_MODE", 14, 15, &umr_bitfield_default },
+	 { "INJECT_SOFT_PARITY_ERROR", 16, 16, &umr_bitfield_default },
+	 { "INJECT_HARD_PARITY_ERROR", 17, 17, &umr_bitfield_default },
+	 { "CLEAR_CAM_PARITY_ERROR", 18, 18, &umr_bitfield_default },
+	 { "CAM_INDEX", 19, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_DEBUG2_TLB[] = {
+	 { "XNACK_RETRY_PERIOD", 0, 11, &umr_bitfield_default },
+	 { "XNACK_RETRY_MODE", 14, 15, &umr_bitfield_default },
+	 { "INJECT_SOFT_PARITY_ERROR", 16, 16, &umr_bitfield_default },
+	 { "INJECT_HARD_PARITY_ERROR", 17, 17, &umr_bitfield_default },
+	 { "CLEAR_CAM_PARITY_ERROR", 18, 18, &umr_bitfield_default },
+	 { "CAM_INDEX", 19, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[] = {
+	 { "VMID0_REMAPPING_FINISHED", 0, 0, &umr_bitfield_default },
+	 { "VMID1_REMAPPING_FINISHED", 1, 1, &umr_bitfield_default },
+	 { "VMID2_REMAPPING_FINISHED", 2, 2, &umr_bitfield_default },
+	 { "VMID3_REMAPPING_FINISHED", 3, 3, &umr_bitfield_default },
+	 { "VMID4_REMAPPING_FINISHED", 4, 4, &umr_bitfield_default },
+	 { "VMID5_REMAPPING_FINISHED", 5, 5, &umr_bitfield_default },
+	 { "VMID6_REMAPPING_FINISHED", 6, 6, &umr_bitfield_default },
+	 { "VMID7_REMAPPING_FINISHED", 7, 7, &umr_bitfield_default },
+	 { "VMID8_REMAPPING_FINISHED", 8, 8, &umr_bitfield_default },
+	 { "VMID9_REMAPPING_FINISHED", 9, 9, &umr_bitfield_default },
+	 { "VMID10_REMAPPING_FINISHED", 10, 10, &umr_bitfield_default },
+	 { "VMID11_REMAPPING_FINISHED", 11, 11, &umr_bitfield_default },
+	 { "VMID12_REMAPPING_FINISHED", 12, 12, &umr_bitfield_default },
+	 { "VMID13_REMAPPING_FINISHED", 13, 13, &umr_bitfield_default },
+	 { "VMID14_REMAPPING_FINISHED", 14, 14, &umr_bitfield_default },
+	 { "VMID15_REMAPPING_FINISHED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID0_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID1_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID2_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID3_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID4_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID5_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID6_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID7_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID8_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_CLKSEL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID9_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID10_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID11_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID12_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID13_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID14_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID15_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_TSM_DEBUG_BCNT10[] = {
+	 { "BYTE0", 0, 7, &umr_bitfield_default },
+	 { "BYTE1", 8, 15, &umr_bitfield_default },
+	 { "BYTE2", 16, 23, &umr_bitfield_default },
+	 { "BYTE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_13[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_VMID_STATUS[] = {
+	 { "VMID0_OUTSTANDING", 0, 0, &umr_bitfield_default },
+	 { "VMID1_OUTSTANDING", 1, 1, &umr_bitfield_default },
+	 { "VMID2_OUTSTANDING", 2, 2, &umr_bitfield_default },
+	 { "VMID3_OUTSTANDING", 3, 3, &umr_bitfield_default },
+	 { "VMID4_OUTSTANDING", 4, 4, &umr_bitfield_default },
+	 { "VMID5_OUTSTANDING", 5, 5, &umr_bitfield_default },
+	 { "VMID6_OUTSTANDING", 6, 6, &umr_bitfield_default },
+	 { "VMID7_OUTSTANDING", 7, 7, &umr_bitfield_default },
+	 { "VMID8_OUTSTANDING", 8, 8, &umr_bitfield_default },
+	 { "VMID9_OUTSTANDING", 9, 9, &umr_bitfield_default },
+	 { "VMID10_OUTSTANDING", 10, 10, &umr_bitfield_default },
+	 { "VMID11_OUTSTANDING", 11, 11, &umr_bitfield_default },
+	 { "VMID12_OUTSTANDING", 12, 12, &umr_bitfield_default },
+	 { "VMID13_OUTSTANDING", 13, 13, &umr_bitfield_default },
+	 { "VMID14_OUTSTANDING", 14, 14, &umr_bitfield_default },
+	 { "VMID15_OUTSTANDING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_SMU_STATUS[] = {
+	 { "VDDGFX_POWERED_DOWN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL3[] = {
+	 { "ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING", 0, 6, &umr_bitfield_default },
+	 { "ENABLE_FREE_COUNTER", 7, 7, &umr_bitfield_default },
+	 { "L2_CACHE_EVICTION_THRESHOLD", 8, 12, &umr_bitfield_default },
+	 { "DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION", 13, 13, &umr_bitfield_default },
+	 { "L2_DELAY_SEND_INVALIDATION_REQUEST", 14, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "PARITY_ERROR_INFO", 1, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_STATUS2[] = {
+	 { "CACHE_ADDRESS_MODE", 0, 2, &umr_bitfield_default },
+	 { "PARITY_ERROR_INFO", 3, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_INDEX[] = {
+	 { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_DATA[] = {
+	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_EXECUTE[] = {
+	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW_START_PTR", 2, 11, &umr_bitfield_default },
+	 { "RENG_EXECUTE_DSP_END_PTR", 12, 21, &umr_bitfield_default },
+	 { "RENG_EXECUTE_END_PTR", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC[] = {
+	 { "RENG_EXECUTE_NOW_MODE", 10, 10, &umr_bitfield_default },
+	 { "RENG_EXECUTE_ON_REG_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "RENG_SRBM_CREDITS_MCD", 12, 15, &umr_bitfield_default },
+	 { "STCTRL_STUTTER_EN", 16, 16, &umr_bitfield_default },
+	 { "STCTRL_GMC_IDLE_THRESHOLD", 17, 18, &umr_bitfield_default },
+	 { "STCTRL_SRBM_IDLE_THRESHOLD", 19, 20, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PRE_SR", 21, 21, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STOP", 22, 22, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_SR_COMMIT", 23, 23, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PROTECTION_FAULT", 24, 24, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_ALLOW_SR", 25, 25, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_GMC_OFFLINE", 26, 26, &umr_bitfield_default },
+	 { "CRITICAL_REGS_LOCK", 27, 27, &umr_bitfield_default },
+	 { "ALLOW_DEEP_SLEEP_MODE", 28, 30, &umr_bitfield_default },
+	 { "STCTRL_FORCE_ALLOW_SR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC2[] = {
+	 { "GMCON_MISC2_RESERVED0", 0, 5, &umr_bitfield_default },
+	 { "STCTRL_NONDISP_IDLE_THRESHOLD", 6, 10, &umr_bitfield_default },
+	 { "RENG_SR_HOLD_THRESHOLD", 11, 16, &umr_bitfield_default },
+	 { "GMCON_MISC2_RESERVED1", 17, 28, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ARB_BUSY", 29, 29, &umr_bitfield_default },
+	 { "STCTRL_EXTEND_GMC_OFFLINE", 30, 30, &umr_bitfield_default },
+	 { "STCTRL_TIMER_PULSE_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE1", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL0[] = {
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+	 { "THRESH_CNTR_ID_EXT", 29, 29, &umr_bitfield_default },
+	 { "START_TRIG_ID_EXT", 30, 30, &umr_bitfield_default },
+	 { "STOP_TRIG_ID_EXT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL1[] = {
+	 { "THRESH_CNTR_ID", 0, 5, &umr_bitfield_default },
+	 { "START_TRIG_ID", 6, 11, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 12, 17, &umr_bitfield_default },
+	 { "MON0_ID", 18, 24, &umr_bitfield_default },
+	 { "MON1_ID", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE", 12, 12, &umr_bitfield_default },
+	 { "READ", 13, 13, &umr_bitfield_default },
+	 { "RSRVD", 14, 26, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_WRITE[] = {
+	 { "WRITE_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_READ[] = {
+	 { "READ_VALUE", 0, 23, &umr_bitfield_default },
+	 { "PGFSM_SELECT", 24, 27, &umr_bitfield_default },
+	 { "SERDES_MASTER_BUSY", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC3[] = {
+	 { "RENG_DISABLE_MCC", 0, 7, &umr_bitfield_default },
+	 { "RENG_DISABLE_MCD", 8, 15, &umr_bitfield_default },
+	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 16, 27, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STUTTER", 28, 28, &umr_bitfield_default },
+	 { "RENG_MEM_LS_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "STCTRL_EXCLUDE_NONMEM_CLIENTS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MASK[] = {
+	 { "STCTRL_BUSY_MASK_ACP_RD", 0, 0, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_ACP_WR", 1, 1, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_VCE_RD", 2, 2, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_VCE_WR", 3, 3, &umr_bitfield_default },
+	 { "STCTRL_SR_HANDSHAKE_MASK", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_LPT_TARGET[] = {
+	 { "STCTRL_LPT_TARGET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_DEBUG[] = {
+	 { "GFX_STALL", 0, 0, &umr_bitfield_default },
+	 { "GFX_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "GMCON_DEBUG_RESERVED0", 2, 2, &umr_bitfield_default },
+	 { "SR_COMMIT_STATE", 3, 3, &umr_bitfield_default },
+	 { "STCTRL_ST", 4, 7, &umr_bitfield_default },
+	 { "MISC_FLAGS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_CNTL_3[] = {
+	 { "PIPE_DELAY_OUT_D0", 0, 2, &umr_bitfield_default },
+	 { "PIPE_DELAY_IN_D0", 3, 5, &umr_bitfield_default },
+	 { "PIPE_DELAY_OUT_D1", 6, 8, &umr_bitfield_default },
+	 { "PIPE_DELAY_IN_D1", 9, 11, &umr_bitfield_default },
+	 { "REPCG_EN_D0", 12, 12, &umr_bitfield_default },
+	 { "REPCG_EN_D1", 13, 13, &umr_bitfield_default },
+	 { "REPCG_OFF_DLY", 16, 19, &umr_bitfield_default },
+	 { "FCK_FRC", 20, 20, &umr_bitfield_default },
+	 { "DBI_FRC", 21, 21, &umr_bitfield_default },
+	 { "PRGRM_CDC", 22, 22, &umr_bitfield_default },
+	 { "DQS_FRC", 23, 23, &umr_bitfield_default },
+	 { "DQS_FRC_PAT", 24, 27, &umr_bitfield_default },
+	 { "IDSC_EN", 30, 30, &umr_bitfield_default },
+	 { "CAC_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CTRL[] = {
+	 { "CH0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CH1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "WCKOFF_EARLY", 2, 2, &umr_bitfield_default },
+	 { "WCKOFF_LATE", 3, 3, &umr_bitfield_default },
+	 { "TPD2MRS", 4, 9, &umr_bitfield_default },
+	 { "TMRS2WCK", 12, 15, &umr_bitfield_default },
+	 { "TWCK2MRS", 16, 19, &umr_bitfield_default },
+	 { "TMRD", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CTRL_LP[] = {
+	 { "CH0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CH1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "WCKOFF_EARLY", 2, 2, &umr_bitfield_default },
+	 { "WCKOFF_LATE", 3, 3, &umr_bitfield_default },
+	 { "TPD2MRS", 4, 9, &umr_bitfield_default },
+	 { "TMRS2WCK", 12, 15, &umr_bitfield_default },
+	 { "TWCK2MRS", 16, 19, &umr_bitfield_default },
+	 { "TMRD", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CMD0[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CMD0_LP[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CMD1[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_G5PDX_CMD1_LP[] = {
+	 { "CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SREG_READ[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_SREG_STATUS[] = {
+	 { "AVAIL_RTN", 0, 3, &umr_bitfield_default },
+	 { "PND_RD", 8, 11, &umr_bitfield_default },
+	 { "PND_WR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PHYREG_BCAST[] = {
+	 { "CH0_EN", 0, 0, &umr_bitfield_default },
+	 { "CH1_EN", 1, 1, &umr_bitfield_default },
+	 { "CKE_MASK", 7, 7, &umr_bitfield_default },
+	 { "DQ_MASK", 8, 8, &umr_bitfield_default },
+	 { "DBI_MASK", 9, 9, &umr_bitfield_default },
+	 { "EDC_MASK", 10, 10, &umr_bitfield_default },
+	 { "WCK_MASK", 11, 11, &umr_bitfield_default },
+	 { "WCDR_MASK", 12, 12, &umr_bitfield_default },
+	 { "CLK_MASK", 13, 13, &umr_bitfield_default },
+	 { "CMD_MASK", 14, 14, &umr_bitfield_default },
+	 { "ADR_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_DVS_CTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TDVS", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_DVS_CTL_LP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TDVS", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_DVS_CMD[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 23, 23, &umr_bitfield_default },
+	 { "ADR_MSB0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_PMG_DVS_CMD_LP[] = {
+	 { "ADR", 0, 15, &umr_bitfield_default },
+	 { "MOP", 16, 18, &umr_bitfield_default },
+	 { "BNK_MSB", 19, 19, &umr_bitfield_default },
+	 { "END", 20, 20, &umr_bitfield_default },
+	 { "CSB", 21, 22, &umr_bitfield_default },
+	 { "ADR_MSB1", 23, 23, &umr_bitfield_default },
+	 { "ADR_MSB0", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DLL_STBY[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "VCTRLADC_FRC", 1, 1, &umr_bitfield_default },
+	 { "VCTRLADC_VAL", 2, 2, &umr_bitfield_default },
+	 { "MSTRSTBY_FRC", 3, 3, &umr_bitfield_default },
+	 { "MSTRSTBY_VAL", 4, 4, &umr_bitfield_default },
+	 { "ENTR_DLY", 5, 7, &umr_bitfield_default },
+	 { "STBY_DLY", 8, 11, &umr_bitfield_default },
+	 { "TCKE_PULSE_EXTN", 12, 15, &umr_bitfield_default },
+	 { "TCKE_EXTN", 16, 23, &umr_bitfield_default },
+	 { "EXIT_DLY", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SEQ_DLL_STBY_LP[] = {
+	 { "EN", 0, 0, &umr_bitfield_default },
+	 { "VCTRLADC_FRC", 1, 1, &umr_bitfield_default },
+	 { "VCTRLADC_VAL", 2, 2, &umr_bitfield_default },
+	 { "MSTRSTBY_FRC", 3, 3, &umr_bitfield_default },
+	 { "MSTRSTBY_VAL", 4, 4, &umr_bitfield_default },
+	 { "ENTR_DLY", 5, 7, &umr_bitfield_default },
+	 { "STBY_DLY", 8, 11, &umr_bitfield_default },
+	 { "TCKE_PULSE_EXTN", 12, 15, &umr_bitfield_default },
+	 { "TCKE_EXTN", 16, 23, &umr_bitfield_default },
+	 { "EXIT_DLY", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_MISCCTRL0[] = {
+	 { "UDD_ON_STATUS_BITS", 0, 0, &umr_bitfield_default },
+	 { "LOAD_DATA_SEL", 1, 1, &umr_bitfield_default },
+	 { "LOAD_UDD", 2, 2, &umr_bitfield_default },
+	 { "ADR_STATUS_SEL", 3, 3, &umr_bitfield_default },
+	 { "DATA_SEL", 4, 7, &umr_bitfield_default },
+	 { "PRBS_CHK_LOAD_CNT", 8, 14, &umr_bitfield_default },
+	 { "UDD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_MISCCTRL1[] = {
+	 { "PRBS_ERR_CNT_LIMIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_MISCCTRL2[] = {
+	 { "PRBS_RUN_LENGTH", 0, 16, &umr_bitfield_default },
+	 { "PRBS_FREERUN", 17, 17, &umr_bitfield_default },
+	 { "PRBS15_MODE", 18, 18, &umr_bitfield_default },
+	 { "PRBS23_MODE", 19, 19, &umr_bitfield_default },
+	 { "STOP_ON_NEXT_ERR", 20, 20, &umr_bitfield_default },
+	 { "STOP_CLK", 21, 21, &umr_bitfield_default },
+	 { "SWEEP_DLY", 24, 25, &umr_bitfield_default },
+	 { "GRAY_CODE_EN", 26, 26, &umr_bitfield_default },
+	 { "SEL_PHY_PRBS_CHK", 28, 28, &umr_bitfield_default },
+	 { "SEL_AC_PRBS_CHK", 29, 29, &umr_bitfield_default },
+	 { "STATUS_SEL", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_CONFIG0[] = {
+	 { "CONF_EN_CH0", 0, 0, &umr_bitfield_default },
+	 { "CONF_EN_CH1", 1, 1, &umr_bitfield_default },
+	 { "CONF_AUTO_EN", 2, 2, &umr_bitfield_default },
+	 { "MASK", 4, 7, &umr_bitfield_default },
+	 { "PTR", 8, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_CONFIG1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_SETUP[] = {
+	 { "DLB_EN", 0, 0, &umr_bitfield_default },
+	 { "DLB_FIFO_EN", 1, 1, &umr_bitfield_default },
+	 { "DLB_STATUS_EN", 2, 2, &umr_bitfield_default },
+	 { "DLB_CONFIG_EN", 3, 3, &umr_bitfield_default },
+	 { "DLB_PRBS_EN", 4, 4, &umr_bitfield_default },
+	 { "PRBS_GEN_RST", 5, 5, &umr_bitfield_default },
+	 { "PRBS_CHK_RST", 6, 6, &umr_bitfield_default },
+	 { "PRBS_PHY_RST", 7, 7, &umr_bitfield_default },
+	 { "QDR_MODE", 8, 8, &umr_bitfield_default },
+	 { "CHK_DATA_BITS", 16, 23, &umr_bitfield_default },
+	 { "MEM_BIT_SEL", 24, 28, &umr_bitfield_default },
+	 { "RXTXLP_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_SETUPSWEEP[] = {
+	 { "DLL_RST", 0, 0, &umr_bitfield_default },
+	 { "CONFIG", 1, 1, &umr_bitfield_default },
+	 { "MASTER", 2, 2, &umr_bitfield_default },
+	 { "DLLDLY", 4, 7, &umr_bitfield_default },
+	 { "DLLSTEPS", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_SETUPFIFO[] = {
+	 { "WRITE_FIFO_RST", 0, 0, &umr_bitfield_default },
+	 { "READ_FIFO_RST", 1, 1, &umr_bitfield_default },
+	 { "BOTH_FIFO_RST", 2, 2, &umr_bitfield_default },
+	 { "SYNC_RST", 3, 3, &umr_bitfield_default },
+	 { "SYNC_RST_MASK", 4, 5, &umr_bitfield_default },
+	 { "OUTPUT_EN_RST", 6, 6, &umr_bitfield_default },
+	 { "SHIFT_WR_FIFO_PTR", 8, 9, &umr_bitfield_default },
+	 { "DELAY_RD_FIFO_PTR", 10, 12, &umr_bitfield_default },
+	 { "STROBE", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_WRITE_MASK[] = {
+	 { "BIT_MASK", 0, 21, &umr_bitfield_default },
+	 { "CH_MASK", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS[] = {
+	 { "STICK_ERROR", 0, 3, &umr_bitfield_default },
+	 { "LOCK", 4, 7, &umr_bitfield_default },
+	 { "SWEEP_DONE", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_DLB_STATUS_MISC7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CK_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_EN_RD[] = {
+	 { "TX_PRI", 0, 7, &umr_bitfield_default },
+	 { "BW_PRI", 8, 15, &umr_bitfield_default },
+	 { "FIX_PRI", 16, 23, &umr_bitfield_default },
+	 { "ST_PRI", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_EN_WR[] = {
+	 { "TX_PRI", 0, 7, &umr_bitfield_default },
+	 { "BW_PRI", 8, 15, &umr_bitfield_default },
+	 { "FIX_PRI", 16, 23, &umr_bitfield_default },
+	 { "ST_PRI", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_CTL_RD[] = {
+	 { "FORCE_HIGHEST", 0, 7, &umr_bitfield_default },
+	 { "HARSH_RR", 8, 8, &umr_bitfield_default },
+	 { "BANK_AGE_ONLY", 9, 9, &umr_bitfield_default },
+	 { "USE_LEGACY_HARSH", 10, 10, &umr_bitfield_default },
+	 { "BWCNT_CATCHUP", 11, 11, &umr_bitfield_default },
+	 { "ST_MODE", 12, 13, &umr_bitfield_default },
+	 { "FORCE_STALL", 14, 21, &umr_bitfield_default },
+	 { "PERF_MON_SEL", 22, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_CTL_WR[] = {
+	 { "FORCE_HIGHEST", 0, 7, &umr_bitfield_default },
+	 { "HARSH_RR", 8, 8, &umr_bitfield_default },
+	 { "BANK_AGE_ONLY", 9, 9, &umr_bitfield_default },
+	 { "USE_LEGACY_HARSH", 10, 10, &umr_bitfield_default },
+	 { "BWCNT_CATCHUP", 11, 11, &umr_bitfield_default },
+	 { "ST_MODE", 12, 13, &umr_bitfield_default },
+	 { "FORCE_STALL", 14, 21, &umr_bitfield_default },
+	 { "PERF_MON_SEL", 22, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PRIORITY1_RD[] = {
+	 { "CB0", 0, 1, &umr_bitfield_default },
+	 { "CBCMASK0", 2, 3, &umr_bitfield_default },
+	 { "CBFMASK0", 4, 5, &umr_bitfield_default },
+	 { "DB0", 6, 7, &umr_bitfield_default },
+	 { "DBHTILE0", 8, 9, &umr_bitfield_default },
+	 { "DBSTEN0", 10, 11, &umr_bitfield_default },
+	 { "TC0", 12, 13, &umr_bitfield_default },
+	 { "ACPG", 14, 15, &umr_bitfield_default },
+	 { "ACPO", 16, 17, &umr_bitfield_default },
+	 { "DMIF", 18, 19, &umr_bitfield_default },
+	 { "DMIF_EXT0", 20, 21, &umr_bitfield_default },
+	 { "DMIF_EXT1", 22, 23, &umr_bitfield_default },
+	 { "DMIF_TW", 24, 25, &umr_bitfield_default },
+	 { "MCIF", 26, 27, &umr_bitfield_default },
+	 { "RLC", 28, 29, &umr_bitfield_default },
+	 { "VMC", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PRIORITY1_WR[] = {
+	 { "CB0", 0, 1, &umr_bitfield_default },
+	 { "CBCMASK0", 2, 3, &umr_bitfield_default },
+	 { "CBFMASK0", 4, 5, &umr_bitfield_default },
+	 { "CBIMMED0", 6, 7, &umr_bitfield_default },
+	 { "DB0", 8, 9, &umr_bitfield_default },
+	 { "DBHTILE0", 10, 11, &umr_bitfield_default },
+	 { "DBSTEN0", 12, 13, &umr_bitfield_default },
+	 { "TC0", 14, 15, &umr_bitfield_default },
+	 { "SH", 16, 17, &umr_bitfield_default },
+	 { "ACPG", 18, 19, &umr_bitfield_default },
+	 { "ACPO", 20, 21, &umr_bitfield_default },
+	 { "MCIF", 22, 23, &umr_bitfield_default },
+	 { "RLC", 24, 25, &umr_bitfield_default },
+	 { "SDMA1", 26, 27, &umr_bitfield_default },
+	 { "SMU", 28, 29, &umr_bitfield_default },
+	 { "VCE0", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PRIORITY2_RD[] = {
+	 { "SDMA1", 0, 1, &umr_bitfield_default },
+	 { "SMU", 2, 3, &umr_bitfield_default },
+	 { "VCE0", 4, 5, &umr_bitfield_default },
+	 { "VCE1", 6, 7, &umr_bitfield_default },
+	 { "XDMAM", 8, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 11, &umr_bitfield_default },
+	 { "HDP", 12, 13, &umr_bitfield_default },
+	 { "UMC", 14, 15, &umr_bitfield_default },
+	 { "UVD", 16, 17, &umr_bitfield_default },
+	 { "UVD_EXT0", 18, 19, &umr_bitfield_default },
+	 { "UVD_EXT1", 20, 21, &umr_bitfield_default },
+	 { "SEM", 22, 23, &umr_bitfield_default },
+	 { "SAMMSP", 24, 25, &umr_bitfield_default },
+	 { "VP8", 26, 27, &umr_bitfield_default },
+	 { "ISP", 28, 29, &umr_bitfield_default },
+	 { "RSV2", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PRIORITY2_WR[] = {
+	 { "VCE1", 0, 1, &umr_bitfield_default },
+	 { "SAMMSP", 2, 3, &umr_bitfield_default },
+	 { "XDMA", 4, 5, &umr_bitfield_default },
+	 { "XDMAM", 6, 7, &umr_bitfield_default },
+	 { "SDMA0", 8, 9, &umr_bitfield_default },
+	 { "HDP", 10, 11, &umr_bitfield_default },
+	 { "UMC", 12, 13, &umr_bitfield_default },
+	 { "UVD", 14, 15, &umr_bitfield_default },
+	 { "UVD_EXT0", 16, 17, &umr_bitfield_default },
+	 { "UVD_EXT1", 18, 19, &umr_bitfield_default },
+	 { "XDP", 20, 21, &umr_bitfield_default },
+	 { "SEM", 22, 23, &umr_bitfield_default },
+	 { "IH", 24, 25, &umr_bitfield_default },
+	 { "VP8", 26, 27, &umr_bitfield_default },
+	 { "ISP", 28, 29, &umr_bitfield_default },
+	 { "VIN0", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_SPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_MPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_CCPU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_SPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_MPS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_MPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_CCPU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 20, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDV[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDV[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDS[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_CLKSEL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDT[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDU[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDV[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDW[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+	 { "WR_URG", 14, 20, &umr_bitfield_default },
+	 { "WR_URG_STALL_THRESHOLD", 21, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDX[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+	 { "WR_URG", 14, 20, &umr_bitfield_default },
+	 { "WR_URG_STALL_THRESHOLD", 21, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDY[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+	 { "WR_URG", 14, 20, &umr_bitfield_default },
+	 { "WR_URG_STALL_THRESHOLD", 21, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDZ[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+	 { "WR_URG", 14, 20, &umr_bitfield_default },
+	 { "WR_URG_STALL_THRESHOLD", 21, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDS[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+	 { "WR_URG", 14, 20, &umr_bitfield_default },
+	 { "WR_URG_STALL_THRESHOLD", 21, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDT[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+	 { "WR_URG", 14, 20, &umr_bitfield_default },
+	 { "WR_URG_STALL_THRESHOLD", 21, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDU[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+	 { "WR_URG", 14, 20, &umr_bitfield_default },
+	 { "WR_URG_STALL_THRESHOLD", 21, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDV[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+	 { "WR_URG", 14, 20, &umr_bitfield_default },
+	 { "WR_URG_STALL_THRESHOLD", 21, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BP2[] = {
+	 { "RDRET", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCE1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCEU1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCE1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCEU1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "URG_BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_14[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_OFSCAL_D0[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_UP_15[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_DBI_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF0[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF1[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF2[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF3[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF4[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF5[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF6[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF7[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF8[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF9[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF10[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF11[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF12[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF13[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF14[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF15[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_MMIOBASE[] = {
+	 { "MMIOBASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_MMIOLIMIT[] = {
+	 { "MMIOLIMIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_PCI_CTRL[] = {
+	 { "MMIOENABLE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_PCI_ARB[] = {
+	 { "VGA_HOLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_TOP_OF_DRAM_SLOT1[] = {
+	 { "TOP_OF_DRAM", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_LOWER_TOP_OF_DRAM2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LOWER_TOM2", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_UPPER_TOP_OF_DRAM2[] = {
+	 { "UPPER_TOM2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_TOP_OF_DRAM3[] = {
+	 { "TOM3_LIMIT", 0, 29, &umr_bitfield_default },
+	 { "TOM3_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_LO_0[] = {
+	 { "MARC_BASE_LO_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_HI_0[] = {
+	 { "MARC_BASE_HI_0", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_0[] = {
+	 { "MARC_ENABLE_0", 0, 0, &umr_bitfield_default },
+	 { "MARC_READONLY_0", 1, 1, &umr_bitfield_default },
+	 { "MARC_RELOC_LO_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_0[] = {
+	 { "MARC_RELOC_HI_0", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_LO_0[] = {
+	 { "MARC_LEN_LO_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_HI_0[] = {
+	 { "MARC_LEN_HI_0", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_LO_1[] = {
+	 { "MARC_BASE_LO_1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_HI_1[] = {
+	 { "MARC_BASE_HI_1", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_1[] = {
+	 { "MARC_ENABLE_1", 0, 0, &umr_bitfield_default },
+	 { "MARC_READONLY_1", 1, 1, &umr_bitfield_default },
+	 { "MARC_RELOC_LO_1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_1[] = {
+	 { "MARC_RELOC_HI_1", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_LO_1[] = {
+	 { "MARC_LEN_LO_1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_HI_1[] = {
+	 { "MARC_LEN_HI_1", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_LO_2[] = {
+	 { "MARC_BASE_LO_2", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_HI_2[] = {
+	 { "MARC_BASE_HI_2", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_2[] = {
+	 { "MARC_ENABLE_2", 0, 0, &umr_bitfield_default },
+	 { "MARC_READONLY_2", 1, 1, &umr_bitfield_default },
+	 { "MARC_RELOC_LO_2", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_2[] = {
+	 { "MARC_RELOC_HI_2", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_LO_2[] = {
+	 { "MARC_LEN_LO_2", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_HI_2[] = {
+	 { "MARC_LEN_HI_2", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_LO_3[] = {
+	 { "MARC_BASE_LO_3", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_HI_3[] = {
+	 { "MARC_BASE_HI_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_3[] = {
+	 { "MARC_ENABLE_3", 0, 0, &umr_bitfield_default },
+	 { "MARC_READONLY_3", 1, 1, &umr_bitfield_default },
+	 { "MARC_RELOC_LO_3", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_3[] = {
+	 { "MARC_RELOC_HI_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_LO_3[] = {
+	 { "MARC_LEN_LO_3", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_HI_3[] = {
+	 { "MARC_LEN_HI_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_CNTL[] = {
+	 { "ENABLE_ALL_CLIENTS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL0[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR0[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR0[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL1[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR1[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR1[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL2[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR2[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR2[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL3[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR3[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR3[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL4[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR4[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR4[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL5[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR5[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR5[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL6[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR6[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR6[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL7[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR7[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR7[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_CNTL8[] = {
+	 { "REQ_STREAM_ID", 0, 8, &umr_bitfield_default },
+	 { "EN", 12, 12, &umr_bitfield_default },
+	 { "PREFETCH_DONE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_START_ADDR8[] = {
+	 { "START_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_END_ADDR8[] = {
+	 { "END_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 20, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+	 { "ATOMIC", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_WCK_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_ACMD_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_IO_DEBUG_CMD_OFSCAL_D1[] = {
+	 { "VALUE0", 0, 7, &umr_bitfield_default },
+	 { "VALUE1", 8, 15, &umr_bitfield_default },
+	 { "VALUE2", 16, 23, &umr_bitfield_default },
+	 { "VALUE3", 24, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gmc81_regs.i b/src/lib/ip/gmc81_regs.i
new file mode 100644
index 0000000..d6d798e
--- /dev/null
+++ b/src/lib/ip/gmc81_regs.i
@@ -0,0 +1,1676 @@
+	{ "ixMC_TSM_DEBUG_GCNT", REG_SMC, 0x0, &ixMC_TSM_DEBUG_GCNT[0], sizeof(ixMC_TSM_DEBUG_GCNT)/sizeof(ixMC_TSM_DEBUG_GCNT[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_0", REG_SMC, 0x0, &ixMC_IO_DEBUG_UP_0[0], sizeof(ixMC_IO_DEBUG_UP_0)/sizeof(ixMC_IO_DEBUG_UP_0[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_FLAG", REG_SMC, 0x1, &ixMC_TSM_DEBUG_FLAG[0], sizeof(ixMC_TSM_DEBUG_FLAG)/sizeof(ixMC_TSM_DEBUG_FLAG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_1", REG_SMC, 0x1, &ixMC_IO_DEBUG_UP_1[0], sizeof(ixMC_IO_DEBUG_UP_1)/sizeof(ixMC_IO_DEBUG_UP_1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_ST01", REG_SMC, 0x10, &ixMC_TSM_DEBUG_ST01[0], sizeof(ixMC_TSM_DEBUG_ST01)/sizeof(ixMC_TSM_DEBUG_ST01[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RXPHASE_D0", REG_SMC, 0x100, &ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RXPHASE_D0", REG_SMC, 0x101, &ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RXPHASE_D0", REG_SMC, 0x102, &ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RXPHASE_D0", REG_SMC, 0x103, &ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RXPHASE_D0", REG_SMC, 0x104, &ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RXPHASE_D0", REG_SMC, 0x105, &ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RXPHASE_D0", REG_SMC, 0x106, &ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RXPHASE_D0", REG_SMC, 0x107, &ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RXPHASE_D0", REG_SMC, 0x108, &ixMC_IO_DEBUG_DBI_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RXPHASE_D0", REG_SMC, 0x109, &ixMC_IO_DEBUG_EDC_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RXPHASE_D0", REG_SMC, 0x10a, &ixMC_IO_DEBUG_WCK_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_RXPHASE_D0", REG_SMC, 0x10b, &ixMC_IO_DEBUG_CK_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_RXPHASE_D0", REG_SMC, 0x10c, &ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_RXPHASE_D0", REG_SMC, 0x10d, &ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_RXPHASE_D0", REG_SMC, 0x10e, &ixMC_IO_DEBUG_ACMD_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RXPHASE_D0", REG_SMC, 0x10f, &ixMC_IO_DEBUG_CMD_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_ST23", REG_SMC, 0x11, &ixMC_TSM_DEBUG_ST23[0], sizeof(ixMC_TSM_DEBUG_ST23)/sizeof(ixMC_TSM_DEBUG_ST23[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RXPHASE_D1", REG_SMC, 0x110, &ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RXPHASE_D1", REG_SMC, 0x111, &ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RXPHASE_D1", REG_SMC, 0x112, &ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RXPHASE_D1", REG_SMC, 0x113, &ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RXPHASE_D1", REG_SMC, 0x114, &ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RXPHASE_D1", REG_SMC, 0x115, &ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RXPHASE_D1", REG_SMC, 0x116, &ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RXPHASE_D1", REG_SMC, 0x117, &ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RXPHASE_D1", REG_SMC, 0x118, &ixMC_IO_DEBUG_DBI_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DBI_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RXPHASE_D1", REG_SMC, 0x119, &ixMC_IO_DEBUG_EDC_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_EDC_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RXPHASE_D1", REG_SMC, 0x11a, &ixMC_IO_DEBUG_WCK_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCK_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_RXPHASE_D1", REG_SMC, 0x11b, &ixMC_IO_DEBUG_CK_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CK_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_RXPHASE_D1", REG_SMC, 0x11c, &ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_RXPHASE_D1", REG_SMC, 0x11d, &ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_RXPHASE_D1", REG_SMC, 0x11e, &ixMC_IO_DEBUG_ACMD_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ACMD_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RXPHASE_D1", REG_SMC, 0x11f, &ixMC_IO_DEBUG_CMD_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CMD_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_ST45", REG_SMC, 0x12, &ixMC_TSM_DEBUG_ST45[0], sizeof(ixMC_TSM_DEBUG_ST45)/sizeof(ixMC_TSM_DEBUG_ST45[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXPHASE_D0", REG_SMC, 0x120, &ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXPHASE_D0", REG_SMC, 0x121, &ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXPHASE_D0", REG_SMC, 0x122, &ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXPHASE_D0", REG_SMC, 0x123, &ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXPHASE_D0", REG_SMC, 0x124, &ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXPHASE_D0", REG_SMC, 0x125, &ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXPHASE_D0", REG_SMC, 0x126, &ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXPHASE_D0", REG_SMC, 0x127, &ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXPHASE_D0", REG_SMC, 0x128, &ixMC_IO_DEBUG_DBI_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXPHASE_D0", REG_SMC, 0x129, &ixMC_IO_DEBUG_EDC_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXPHASE_D0", REG_SMC, 0x12a, &ixMC_IO_DEBUG_WCK_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXPHASE_D0", REG_SMC, 0x12b, &ixMC_IO_DEBUG_CK_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXPHASE_D0", REG_SMC, 0x12c, &ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXPHASE_D0", REG_SMC, 0x12d, &ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXPHASE_D0", REG_SMC, 0x12e, &ixMC_IO_DEBUG_ACMD_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXPHASE_D0", REG_SMC, 0x12f, &ixMC_IO_DEBUG_CMD_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BKPT", REG_SMC, 0x13, &ixMC_TSM_DEBUG_BKPT[0], sizeof(ixMC_TSM_DEBUG_BKPT)/sizeof(ixMC_TSM_DEBUG_BKPT[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXPHASE_D1", REG_SMC, 0x130, &ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXPHASE_D1", REG_SMC, 0x131, &ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXPHASE_D1", REG_SMC, 0x132, &ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXPHASE_D1", REG_SMC, 0x133, &ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXPHASE_D1", REG_SMC, 0x134, &ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXPHASE_D1", REG_SMC, 0x135, &ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXPHASE_D1", REG_SMC, 0x136, &ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXPHASE_D1", REG_SMC, 0x137, &ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXPHASE_D1", REG_SMC, 0x138, &ixMC_IO_DEBUG_DBI_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXPHASE_D1", REG_SMC, 0x139, &ixMC_IO_DEBUG_EDC_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXPHASE_D1", REG_SMC, 0x13a, &ixMC_IO_DEBUG_WCK_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXPHASE_D1", REG_SMC, 0x13b, &ixMC_IO_DEBUG_CK_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CK_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXPHASE_D1", REG_SMC, 0x13c, &ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXPHASE_D1", REG_SMC, 0x13d, &ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXPHASE_D1", REG_SMC, 0x13e, &ixMC_IO_DEBUG_ACMD_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXPHASE_D1", REG_SMC, 0x13f, &ixMC_IO_DEBUG_CMD_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_20", REG_SMC, 0x14, &ixMC_IO_DEBUG_UP_20[0], sizeof(ixMC_IO_DEBUG_UP_20)/sizeof(ixMC_IO_DEBUG_UP_20[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0", REG_SMC, 0x140, &ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0", REG_SMC, 0x141, &ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0", REG_SMC, 0x142, &ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0", REG_SMC, 0x143, &ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0", REG_SMC, 0x144, &ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0", REG_SMC, 0x145, &ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0", REG_SMC, 0x146, &ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0", REG_SMC, 0x147, &ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0", REG_SMC, 0x148, &ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0", REG_SMC, 0x149, &ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0", REG_SMC, 0x14a, &ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0", REG_SMC, 0x14b, &ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0", REG_SMC, 0x14c, &ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0", REG_SMC, 0x14d, &ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0", REG_SMC, 0x14e, &ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0", REG_SMC, 0x14f, &ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_21", REG_SMC, 0x15, &ixMC_IO_DEBUG_UP_21[0], sizeof(ixMC_IO_DEBUG_UP_21)/sizeof(ixMC_IO_DEBUG_UP_21[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1", REG_SMC, 0x150, &ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1", REG_SMC, 0x151, &ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1", REG_SMC, 0x152, &ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1", REG_SMC, 0x153, &ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1", REG_SMC, 0x154, &ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1", REG_SMC, 0x155, &ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1", REG_SMC, 0x156, &ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1", REG_SMC, 0x157, &ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1", REG_SMC, 0x158, &ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1", REG_SMC, 0x159, &ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1", REG_SMC, 0x15a, &ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1", REG_SMC, 0x15b, &ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1", REG_SMC, 0x15c, &ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1", REG_SMC, 0x15d, &ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1", REG_SMC, 0x15e, &ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1", REG_SMC, 0x15f, &ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_22", REG_SMC, 0x16, &ixMC_IO_DEBUG_UP_22[0], sizeof(ixMC_IO_DEBUG_UP_22)/sizeof(ixMC_IO_DEBUG_UP_22[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXSLF_D0", REG_SMC, 0x160, &ixMC_IO_DEBUG_DQB0L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXSLF_D0", REG_SMC, 0x161, &ixMC_IO_DEBUG_DQB0H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXSLF_D0", REG_SMC, 0x162, &ixMC_IO_DEBUG_DQB1L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXSLF_D0", REG_SMC, 0x163, &ixMC_IO_DEBUG_DQB1H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXSLF_D0", REG_SMC, 0x164, &ixMC_IO_DEBUG_DQB2L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXSLF_D0", REG_SMC, 0x165, &ixMC_IO_DEBUG_DQB2H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXSLF_D0", REG_SMC, 0x166, &ixMC_IO_DEBUG_DQB3L_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXSLF_D0", REG_SMC, 0x167, &ixMC_IO_DEBUG_DQB3H_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXSLF_D0", REG_SMC, 0x168, &ixMC_IO_DEBUG_DBI_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXSLF_D0", REG_SMC, 0x169, &ixMC_IO_DEBUG_EDC_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXSLF_D0", REG_SMC, 0x16a, &ixMC_IO_DEBUG_WCK_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXSLF_D0", REG_SMC, 0x16b, &ixMC_IO_DEBUG_CK_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_CK_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXSLF_D0", REG_SMC, 0x16c, &ixMC_IO_DEBUG_ADDRL_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXSLF_D0", REG_SMC, 0x16d, &ixMC_IO_DEBUG_ADDRH_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXSLF_D0", REG_SMC, 0x16e, &ixMC_IO_DEBUG_ACMD_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXSLF_D0", REG_SMC, 0x16f, &ixMC_IO_DEBUG_CMD_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_23", REG_SMC, 0x17, &ixMC_IO_DEBUG_UP_23[0], sizeof(ixMC_IO_DEBUG_UP_23)/sizeof(ixMC_IO_DEBUG_UP_23[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXSLF_D1", REG_SMC, 0x170, &ixMC_IO_DEBUG_DQB0L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXSLF_D1", REG_SMC, 0x171, &ixMC_IO_DEBUG_DQB0H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXSLF_D1", REG_SMC, 0x172, &ixMC_IO_DEBUG_DQB1L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXSLF_D1", REG_SMC, 0x173, &ixMC_IO_DEBUG_DQB1H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXSLF_D1", REG_SMC, 0x174, &ixMC_IO_DEBUG_DQB2L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXSLF_D1", REG_SMC, 0x175, &ixMC_IO_DEBUG_DQB2H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXSLF_D1", REG_SMC, 0x176, &ixMC_IO_DEBUG_DQB3L_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXSLF_D1", REG_SMC, 0x177, &ixMC_IO_DEBUG_DQB3H_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXSLF_D1", REG_SMC, 0x178, &ixMC_IO_DEBUG_DBI_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXSLF_D1", REG_SMC, 0x179, &ixMC_IO_DEBUG_EDC_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXSLF_D1", REG_SMC, 0x17a, &ixMC_IO_DEBUG_WCK_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXSLF_D1", REG_SMC, 0x17b, &ixMC_IO_DEBUG_CK_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_CK_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXSLF_D1", REG_SMC, 0x17c, &ixMC_IO_DEBUG_ADDRL_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXSLF_D1", REG_SMC, 0x17d, &ixMC_IO_DEBUG_ADDRH_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXSLF_D1", REG_SMC, 0x17e, &ixMC_IO_DEBUG_ACMD_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXSLF_D1", REG_SMC, 0x17f, &ixMC_IO_DEBUG_CMD_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_24", REG_SMC, 0x18, &ixMC_IO_DEBUG_UP_24[0], sizeof(ixMC_IO_DEBUG_UP_24)/sizeof(ixMC_IO_DEBUG_UP_24[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0", REG_SMC, 0x180, &ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0", REG_SMC, 0x181, &ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0", REG_SMC, 0x182, &ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0", REG_SMC, 0x183, &ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0", REG_SMC, 0x184, &ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0", REG_SMC, 0x185, &ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0", REG_SMC, 0x186, &ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0", REG_SMC, 0x187, &ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PD_D0", REG_SMC, 0x188, &ixMC_IO_DEBUG_DBI_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PD_D0", REG_SMC, 0x189, &ixMC_IO_DEBUG_EDC_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PD_D0", REG_SMC, 0x18a, &ixMC_IO_DEBUG_WCK_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PD_D0", REG_SMC, 0x18b, &ixMC_IO_DEBUG_CK_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0", REG_SMC, 0x18c, &ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0", REG_SMC, 0x18d, &ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PD_D0", REG_SMC, 0x18e, &ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PD_D0", REG_SMC, 0x18f, &ixMC_IO_DEBUG_CMD_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_25", REG_SMC, 0x19, &ixMC_IO_DEBUG_UP_25[0], sizeof(ixMC_IO_DEBUG_UP_25)/sizeof(ixMC_IO_DEBUG_UP_25[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1", REG_SMC, 0x190, &ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1", REG_SMC, 0x191, &ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1", REG_SMC, 0x192, &ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1", REG_SMC, 0x193, &ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1", REG_SMC, 0x194, &ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1", REG_SMC, 0x195, &ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1", REG_SMC, 0x196, &ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1", REG_SMC, 0x197, &ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PD_D1", REG_SMC, 0x198, &ixMC_IO_DEBUG_DBI_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PD_D1", REG_SMC, 0x199, &ixMC_IO_DEBUG_EDC_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PD_D1", REG_SMC, 0x19a, &ixMC_IO_DEBUG_WCK_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PD_D1", REG_SMC, 0x19b, &ixMC_IO_DEBUG_CK_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1", REG_SMC, 0x19c, &ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1", REG_SMC, 0x19d, &ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PD_D1", REG_SMC, 0x19e, &ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PD_D1", REG_SMC, 0x19f, &ixMC_IO_DEBUG_CMD_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_26", REG_SMC, 0x1a, &ixMC_IO_DEBUG_UP_26[0], sizeof(ixMC_IO_DEBUG_UP_26)/sizeof(ixMC_IO_DEBUG_UP_26[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0", REG_SMC, 0x1a0, &ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0", REG_SMC, 0x1a1, &ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0", REG_SMC, 0x1a2, &ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0", REG_SMC, 0x1a3, &ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0", REG_SMC, 0x1a4, &ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0", REG_SMC, 0x1a5, &ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0", REG_SMC, 0x1a6, &ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0", REG_SMC, 0x1a7, &ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PU_D0", REG_SMC, 0x1a8, &ixMC_IO_DEBUG_DBI_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PU_D0", REG_SMC, 0x1a9, &ixMC_IO_DEBUG_EDC_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PU_D0", REG_SMC, 0x1aa, &ixMC_IO_DEBUG_WCK_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PU_D0", REG_SMC, 0x1ab, &ixMC_IO_DEBUG_CK_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0", REG_SMC, 0x1ac, &ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0", REG_SMC, 0x1ad, &ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PU_D0", REG_SMC, 0x1ae, &ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PU_D0", REG_SMC, 0x1af, &ixMC_IO_DEBUG_CMD_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_27", REG_SMC, 0x1b, &ixMC_IO_DEBUG_UP_27[0], sizeof(ixMC_IO_DEBUG_UP_27)/sizeof(ixMC_IO_DEBUG_UP_27[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1", REG_SMC, 0x1b0, &ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1", REG_SMC, 0x1b1, &ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1", REG_SMC, 0x1b2, &ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1", REG_SMC, 0x1b3, &ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1", REG_SMC, 0x1b4, &ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1", REG_SMC, 0x1b5, &ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1", REG_SMC, 0x1b6, &ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1", REG_SMC, 0x1b7, &ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_TXBST_PU_D1", REG_SMC, 0x1b8, &ixMC_IO_DEBUG_DBI_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_DBI_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_TXBST_PU_D1", REG_SMC, 0x1b9, &ixMC_IO_DEBUG_EDC_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_EDC_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_TXBST_PU_D1", REG_SMC, 0x1ba, &ixMC_IO_DEBUG_WCK_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_WCK_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_TXBST_PU_D1", REG_SMC, 0x1bb, &ixMC_IO_DEBUG_CK_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_CK_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1", REG_SMC, 0x1bc, &ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1", REG_SMC, 0x1bd, &ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_TXBST_PU_D1", REG_SMC, 0x1be, &ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_ACMD_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_TXBST_PU_D1", REG_SMC, 0x1bf, &ixMC_IO_DEBUG_CMD_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_CMD_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_28", REG_SMC, 0x1c, &ixMC_IO_DEBUG_UP_28[0], sizeof(ixMC_IO_DEBUG_UP_28)/sizeof(ixMC_IO_DEBUG_UP_28[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_EQ_D0", REG_SMC, 0x1c0, &ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_EQ_D0", REG_SMC, 0x1c1, &ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_EQ_D0", REG_SMC, 0x1c2, &ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_EQ_D0", REG_SMC, 0x1c3, &ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_EQ_D0", REG_SMC, 0x1c4, &ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_EQ_D0", REG_SMC, 0x1c5, &ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_EQ_D0", REG_SMC, 0x1c6, &ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_EQ_D0", REG_SMC, 0x1c7, &ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_EQ_D0", REG_SMC, 0x1c8, &ixMC_IO_DEBUG_DBI_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_D0", REG_SMC, 0x1c9, &ixMC_IO_DEBUG_EDC_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_EQ_D0", REG_SMC, 0x1ca, &ixMC_IO_DEBUG_WCK_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0", REG_SMC, 0x1cb, &ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0", REG_SMC, 0x1cc, &ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0", REG_SMC, 0x1cd, &ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0", REG_SMC, 0x1ce, &ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RX_EQ_D0", REG_SMC, 0x1cf, &ixMC_IO_DEBUG_CMD_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_29", REG_SMC, 0x1d, &ixMC_IO_DEBUG_UP_29[0], sizeof(ixMC_IO_DEBUG_UP_29)/sizeof(ixMC_IO_DEBUG_UP_29[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_RX_EQ_D1", REG_SMC, 0x1d0, &ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_RX_EQ_D1", REG_SMC, 0x1d1, &ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_RX_EQ_D1", REG_SMC, 0x1d2, &ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_RX_EQ_D1", REG_SMC, 0x1d3, &ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_RX_EQ_D1", REG_SMC, 0x1d4, &ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_RX_EQ_D1", REG_SMC, 0x1d5, &ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_RX_EQ_D1", REG_SMC, 0x1d6, &ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_RX_EQ_D1", REG_SMC, 0x1d7, &ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_RX_EQ_D1", REG_SMC, 0x1d8, &ixMC_IO_DEBUG_DBI_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_DBI_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_D1", REG_SMC, 0x1d9, &ixMC_IO_DEBUG_EDC_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_RX_EQ_D1", REG_SMC, 0x1da, &ixMC_IO_DEBUG_WCK_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_WCK_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1", REG_SMC, 0x1db, &ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1", REG_SMC, 0x1dc, &ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1", REG_SMC, 0x1dd, &ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1", REG_SMC, 0x1de, &ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_RX_EQ_D1", REG_SMC, 0x1df, &ixMC_IO_DEBUG_CMD_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_CMD_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_30", REG_SMC, 0x1e, &ixMC_IO_DEBUG_UP_30[0], sizeof(ixMC_IO_DEBUG_UP_30)/sizeof(ixMC_IO_DEBUG_UP_30[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_MISC_D0", REG_SMC, 0x1e0, &ixMC_IO_DEBUG_WCDR_MISC_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_MISC_D0)/sizeof(ixMC_IO_DEBUG_WCDR_MISC_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CLKSEL_D0", REG_SMC, 0x1e1, &ixMC_IO_DEBUG_WCDR_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_OFSCAL_D0", REG_SMC, 0x1e2, &ixMC_IO_DEBUG_WCDR_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RXPHASE_D0", REG_SMC, 0x1e3, &ixMC_IO_DEBUG_WCDR_RXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXPHASE_D0", REG_SMC, 0x1e4, &ixMC_IO_DEBUG_WCDR_TXPHASE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0", REG_SMC, 0x1e5, &ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXSLF_D0", REG_SMC, 0x1e6, &ixMC_IO_DEBUG_WCDR_TXSLF_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PD_D0", REG_SMC, 0x1e7, &ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PU_D0", REG_SMC, 0x1e8, &ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D0)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_D0", REG_SMC, 0x1e9, &ixMC_IO_DEBUG_WCDR_RX_EQ_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0", REG_SMC, 0x1ea, &ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0", REG_SMC, 0x1eb, &ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0", REG_SMC, 0x1ec, &ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_31", REG_SMC, 0x1f, &ixMC_IO_DEBUG_UP_31[0], sizeof(ixMC_IO_DEBUG_UP_31)/sizeof(ixMC_IO_DEBUG_UP_31[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_MISC_D1", REG_SMC, 0x1f0, &ixMC_IO_DEBUG_WCDR_MISC_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_MISC_D1)/sizeof(ixMC_IO_DEBUG_WCDR_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CLKSEL_D1", REG_SMC, 0x1f1, &ixMC_IO_DEBUG_WCDR_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_OFSCAL_D1", REG_SMC, 0x1f2, &ixMC_IO_DEBUG_WCDR_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RXPHASE_D1", REG_SMC, 0x1f3, &ixMC_IO_DEBUG_WCDR_RXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXPHASE_D1", REG_SMC, 0x1f4, &ixMC_IO_DEBUG_WCDR_TXPHASE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXPHASE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1", REG_SMC, 0x1f5, &ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXSLF_D1", REG_SMC, 0x1f6, &ixMC_IO_DEBUG_WCDR_TXSLF_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXSLF_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PD_D1", REG_SMC, 0x1f7, &ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PD_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_TXBST_PU_D1", REG_SMC, 0x1f8, &ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D1)/sizeof(ixMC_IO_DEBUG_WCDR_TXBST_PU_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_D1", REG_SMC, 0x1f9, &ixMC_IO_DEBUG_WCDR_RX_EQ_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1", REG_SMC, 0x1fa, &ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1", REG_SMC, 0x1fb, &ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1", REG_SMC, 0x1fc, &ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_MISC", REG_SMC, 0x2, &ixMC_TSM_DEBUG_MISC[0], sizeof(ixMC_TSM_DEBUG_MISC)/sizeof(ixMC_TSM_DEBUG_MISC[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_2", REG_SMC, 0x2, &ixMC_IO_DEBUG_UP_2[0], sizeof(ixMC_IO_DEBUG_UP_2)/sizeof(ixMC_IO_DEBUG_UP_2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_32", REG_SMC, 0x20, &ixMC_IO_DEBUG_UP_32[0], sizeof(ixMC_IO_DEBUG_UP_32)/sizeof(ixMC_IO_DEBUG_UP_32[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_33", REG_SMC, 0x21, &ixMC_IO_DEBUG_UP_33[0], sizeof(ixMC_IO_DEBUG_UP_33)/sizeof(ixMC_IO_DEBUG_UP_33[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_34", REG_SMC, 0x22, &ixMC_IO_DEBUG_UP_34[0], sizeof(ixMC_IO_DEBUG_UP_34)/sizeof(ixMC_IO_DEBUG_UP_34[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_35", REG_SMC, 0x23, &ixMC_IO_DEBUG_UP_35[0], sizeof(ixMC_IO_DEBUG_UP_35)/sizeof(ixMC_IO_DEBUG_UP_35[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_36", REG_SMC, 0x24, &ixMC_IO_DEBUG_UP_36[0], sizeof(ixMC_IO_DEBUG_UP_36)/sizeof(ixMC_IO_DEBUG_UP_36[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_37", REG_SMC, 0x25, &ixMC_IO_DEBUG_UP_37[0], sizeof(ixMC_IO_DEBUG_UP_37)/sizeof(ixMC_IO_DEBUG_UP_37[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_38", REG_SMC, 0x26, &ixMC_IO_DEBUG_UP_38[0], sizeof(ixMC_IO_DEBUG_UP_38)/sizeof(ixMC_IO_DEBUG_UP_38[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_39", REG_SMC, 0x27, &ixMC_IO_DEBUG_UP_39[0], sizeof(ixMC_IO_DEBUG_UP_39)/sizeof(ixMC_IO_DEBUG_UP_39[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_40", REG_SMC, 0x28, &ixMC_IO_DEBUG_UP_40[0], sizeof(ixMC_IO_DEBUG_UP_40)/sizeof(ixMC_IO_DEBUG_UP_40[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_41", REG_SMC, 0x29, &ixMC_IO_DEBUG_UP_41[0], sizeof(ixMC_IO_DEBUG_UP_41)/sizeof(ixMC_IO_DEBUG_UP_41[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_42", REG_SMC, 0x2a, &ixMC_IO_DEBUG_UP_42[0], sizeof(ixMC_IO_DEBUG_UP_42)/sizeof(ixMC_IO_DEBUG_UP_42[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_43", REG_SMC, 0x2b, &ixMC_IO_DEBUG_UP_43[0], sizeof(ixMC_IO_DEBUG_UP_43)/sizeof(ixMC_IO_DEBUG_UP_43[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_44", REG_SMC, 0x2c, &ixMC_IO_DEBUG_UP_44[0], sizeof(ixMC_IO_DEBUG_UP_44)/sizeof(ixMC_IO_DEBUG_UP_44[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_45", REG_SMC, 0x2d, &ixMC_IO_DEBUG_UP_45[0], sizeof(ixMC_IO_DEBUG_UP_45)/sizeof(ixMC_IO_DEBUG_UP_45[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_46", REG_SMC, 0x2e, &ixMC_IO_DEBUG_UP_46[0], sizeof(ixMC_IO_DEBUG_UP_46)/sizeof(ixMC_IO_DEBUG_UP_46[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_47", REG_SMC, 0x2f, &ixMC_IO_DEBUG_UP_47[0], sizeof(ixMC_IO_DEBUG_UP_47)/sizeof(ixMC_IO_DEBUG_UP_47[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT0", REG_SMC, 0x3, &ixMC_TSM_DEBUG_BCNT0[0], sizeof(ixMC_TSM_DEBUG_BCNT0)/sizeof(ixMC_TSM_DEBUG_BCNT0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_3", REG_SMC, 0x3, &ixMC_IO_DEBUG_UP_3[0], sizeof(ixMC_IO_DEBUG_UP_3)/sizeof(ixMC_IO_DEBUG_UP_3[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_48", REG_SMC, 0x30, &ixMC_IO_DEBUG_UP_48[0], sizeof(ixMC_IO_DEBUG_UP_48)/sizeof(ixMC_IO_DEBUG_UP_48[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_49", REG_SMC, 0x31, &ixMC_IO_DEBUG_UP_49[0], sizeof(ixMC_IO_DEBUG_UP_49)/sizeof(ixMC_IO_DEBUG_UP_49[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_50", REG_SMC, 0x32, &ixMC_IO_DEBUG_UP_50[0], sizeof(ixMC_IO_DEBUG_UP_50)/sizeof(ixMC_IO_DEBUG_UP_50[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_51", REG_SMC, 0x33, &ixMC_IO_DEBUG_UP_51[0], sizeof(ixMC_IO_DEBUG_UP_51)/sizeof(ixMC_IO_DEBUG_UP_51[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_52", REG_SMC, 0x34, &ixMC_IO_DEBUG_UP_52[0], sizeof(ixMC_IO_DEBUG_UP_52)/sizeof(ixMC_IO_DEBUG_UP_52[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_53", REG_SMC, 0x35, &ixMC_IO_DEBUG_UP_53[0], sizeof(ixMC_IO_DEBUG_UP_53)/sizeof(ixMC_IO_DEBUG_UP_53[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_54", REG_SMC, 0x36, &ixMC_IO_DEBUG_UP_54[0], sizeof(ixMC_IO_DEBUG_UP_54)/sizeof(ixMC_IO_DEBUG_UP_54[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_55", REG_SMC, 0x37, &ixMC_IO_DEBUG_UP_55[0], sizeof(ixMC_IO_DEBUG_UP_55)/sizeof(ixMC_IO_DEBUG_UP_55[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_56", REG_SMC, 0x38, &ixMC_IO_DEBUG_UP_56[0], sizeof(ixMC_IO_DEBUG_UP_56)/sizeof(ixMC_IO_DEBUG_UP_56[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_57", REG_SMC, 0x39, &ixMC_IO_DEBUG_UP_57[0], sizeof(ixMC_IO_DEBUG_UP_57)/sizeof(ixMC_IO_DEBUG_UP_57[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_58", REG_SMC, 0x3a, &ixMC_IO_DEBUG_UP_58[0], sizeof(ixMC_IO_DEBUG_UP_58)/sizeof(ixMC_IO_DEBUG_UP_58[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_59", REG_SMC, 0x3b, &ixMC_IO_DEBUG_UP_59[0], sizeof(ixMC_IO_DEBUG_UP_59)/sizeof(ixMC_IO_DEBUG_UP_59[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_60", REG_SMC, 0x3c, &ixMC_IO_DEBUG_UP_60[0], sizeof(ixMC_IO_DEBUG_UP_60)/sizeof(ixMC_IO_DEBUG_UP_60[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_61", REG_SMC, 0x3d, &ixMC_IO_DEBUG_UP_61[0], sizeof(ixMC_IO_DEBUG_UP_61)/sizeof(ixMC_IO_DEBUG_UP_61[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_62", REG_SMC, 0x3e, &ixMC_IO_DEBUG_UP_62[0], sizeof(ixMC_IO_DEBUG_UP_62)/sizeof(ixMC_IO_DEBUG_UP_62[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_63", REG_SMC, 0x3f, &ixMC_IO_DEBUG_UP_63[0], sizeof(ixMC_IO_DEBUG_UP_63)/sizeof(ixMC_IO_DEBUG_UP_63[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT1", REG_SMC, 0x4, &ixMC_TSM_DEBUG_BCNT1[0], sizeof(ixMC_TSM_DEBUG_BCNT1)/sizeof(ixMC_TSM_DEBUG_BCNT1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_4", REG_SMC, 0x4, &ixMC_IO_DEBUG_UP_4[0], sizeof(ixMC_IO_DEBUG_UP_4)/sizeof(ixMC_IO_DEBUG_UP_4[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_64", REG_SMC, 0x40, &ixMC_IO_DEBUG_UP_64[0], sizeof(ixMC_IO_DEBUG_UP_64)/sizeof(ixMC_IO_DEBUG_UP_64[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_65", REG_SMC, 0x41, &ixMC_IO_DEBUG_UP_65[0], sizeof(ixMC_IO_DEBUG_UP_65)/sizeof(ixMC_IO_DEBUG_UP_65[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_66", REG_SMC, 0x42, &ixMC_IO_DEBUG_UP_66[0], sizeof(ixMC_IO_DEBUG_UP_66)/sizeof(ixMC_IO_DEBUG_UP_66[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_67", REG_SMC, 0x43, &ixMC_IO_DEBUG_UP_67[0], sizeof(ixMC_IO_DEBUG_UP_67)/sizeof(ixMC_IO_DEBUG_UP_67[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_68", REG_SMC, 0x44, &ixMC_IO_DEBUG_UP_68[0], sizeof(ixMC_IO_DEBUG_UP_68)/sizeof(ixMC_IO_DEBUG_UP_68[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_69", REG_SMC, 0x45, &ixMC_IO_DEBUG_UP_69[0], sizeof(ixMC_IO_DEBUG_UP_69)/sizeof(ixMC_IO_DEBUG_UP_69[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_70", REG_SMC, 0x46, &ixMC_IO_DEBUG_UP_70[0], sizeof(ixMC_IO_DEBUG_UP_70)/sizeof(ixMC_IO_DEBUG_UP_70[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_71", REG_SMC, 0x47, &ixMC_IO_DEBUG_UP_71[0], sizeof(ixMC_IO_DEBUG_UP_71)/sizeof(ixMC_IO_DEBUG_UP_71[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_72", REG_SMC, 0x48, &ixMC_IO_DEBUG_UP_72[0], sizeof(ixMC_IO_DEBUG_UP_72)/sizeof(ixMC_IO_DEBUG_UP_72[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_73", REG_SMC, 0x49, &ixMC_IO_DEBUG_UP_73[0], sizeof(ixMC_IO_DEBUG_UP_73)/sizeof(ixMC_IO_DEBUG_UP_73[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_74", REG_SMC, 0x4a, &ixMC_IO_DEBUG_UP_74[0], sizeof(ixMC_IO_DEBUG_UP_74)/sizeof(ixMC_IO_DEBUG_UP_74[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_75", REG_SMC, 0x4b, &ixMC_IO_DEBUG_UP_75[0], sizeof(ixMC_IO_DEBUG_UP_75)/sizeof(ixMC_IO_DEBUG_UP_75[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_76", REG_SMC, 0x4c, &ixMC_IO_DEBUG_UP_76[0], sizeof(ixMC_IO_DEBUG_UP_76)/sizeof(ixMC_IO_DEBUG_UP_76[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_77", REG_SMC, 0x4d, &ixMC_IO_DEBUG_UP_77[0], sizeof(ixMC_IO_DEBUG_UP_77)/sizeof(ixMC_IO_DEBUG_UP_77[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_78", REG_SMC, 0x4e, &ixMC_IO_DEBUG_UP_78[0], sizeof(ixMC_IO_DEBUG_UP_78)/sizeof(ixMC_IO_DEBUG_UP_78[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_79", REG_SMC, 0x4f, &ixMC_IO_DEBUG_UP_79[0], sizeof(ixMC_IO_DEBUG_UP_79)/sizeof(ixMC_IO_DEBUG_UP_79[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT2", REG_SMC, 0x5, &ixMC_TSM_DEBUG_BCNT2[0], sizeof(ixMC_TSM_DEBUG_BCNT2)/sizeof(ixMC_TSM_DEBUG_BCNT2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_5", REG_SMC, 0x5, &ixMC_IO_DEBUG_UP_5[0], sizeof(ixMC_IO_DEBUG_UP_5)/sizeof(ixMC_IO_DEBUG_UP_5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_80", REG_SMC, 0x50, &ixMC_IO_DEBUG_UP_80[0], sizeof(ixMC_IO_DEBUG_UP_80)/sizeof(ixMC_IO_DEBUG_UP_80[0]), 0, 0 },
+	{ "mmVM_L2_CNTL", REG_MMIO, 0x500, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 },
+	{ "mmVM_L2_CNTL2", REG_MMIO, 0x501, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 },
+	{ "mmVM_L2_CNTL3", REG_MMIO, 0x502, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 },
+	{ "mmVM_L2_STATUS", REG_MMIO, 0x503, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x504, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x505, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x506, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_ADDR", REG_MMIO, 0x507, &mmVM_DUMMY_PAGE_FAULT_ADDR[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL2", REG_MMIO, 0x50c, &mmVM_CONTEXT0_CNTL2[0], sizeof(mmVM_CONTEXT0_CNTL2)/sizeof(mmVM_CONTEXT0_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL2", REG_MMIO, 0x50d, &mmVM_CONTEXT1_CNTL2[0], sizeof(mmVM_CONTEXT1_CNTL2)/sizeof(mmVM_CONTEXT1_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50e, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50f, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_81", REG_SMC, 0x51, &ixMC_IO_DEBUG_UP_81[0], sizeof(ixMC_IO_DEBUG_UP_81)/sizeof(ixMC_IO_DEBUG_UP_81[0]), 0, 0 },
+	{ "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x510, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x511, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x512, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x513, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x514, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x515, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_REQUEST", REG_MMIO, 0x51e, &mmVM_INVALIDATE_REQUEST[0], sizeof(mmVM_INVALIDATE_REQUEST)/sizeof(mmVM_INVALIDATE_REQUEST[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_RESPONSE", REG_MMIO, 0x51f, &mmVM_INVALIDATE_RESPONSE[0], sizeof(mmVM_INVALIDATE_RESPONSE)/sizeof(mmVM_INVALIDATE_RESPONSE[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_82", REG_SMC, 0x52, &ixMC_IO_DEBUG_UP_82[0], sizeof(ixMC_IO_DEBUG_UP_82)/sizeof(ixMC_IO_DEBUG_UP_82[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_LOW_ADDR", REG_MMIO, 0x52c, &mmVM_PRT_APERTURE0_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE0_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_LOW_ADDR", REG_MMIO, 0x52d, &mmVM_PRT_APERTURE1_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE1_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_LOW_ADDR", REG_MMIO, 0x52e, &mmVM_PRT_APERTURE2_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE2_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE2_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_LOW_ADDR", REG_MMIO, 0x52f, &mmVM_PRT_APERTURE3_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE3_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE3_LOW_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_83", REG_SMC, 0x53, &ixMC_IO_DEBUG_UP_83[0], sizeof(ixMC_IO_DEBUG_UP_83)/sizeof(ixMC_IO_DEBUG_UP_83[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_HIGH_ADDR", REG_MMIO, 0x530, &mmVM_PRT_APERTURE0_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_HIGH_ADDR", REG_MMIO, 0x531, &mmVM_PRT_APERTURE1_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_HIGH_ADDR", REG_MMIO, 0x532, &mmVM_PRT_APERTURE2_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_HIGH_ADDR", REG_MMIO, 0x533, &mmVM_PRT_APERTURE3_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_CNTL", REG_MMIO, 0x534, &mmVM_PRT_CNTL[0], sizeof(mmVM_PRT_CNTL)/sizeof(mmVM_PRT_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x535, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_STATUS", REG_MMIO, 0x536, &mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_STATUS", REG_MMIO, 0x537, &mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x538, &mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x539, &mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53e, &mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53f, &mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_84", REG_SMC, 0x54, &ixMC_IO_DEBUG_UP_84[0], sizeof(ixMC_IO_DEBUG_UP_84)/sizeof(ixMC_IO_DEBUG_UP_84[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x546, &mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x547, &mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_FAULT_CLIENT_ID", REG_MMIO, 0x54e, &mmVM_FAULT_CLIENT_ID[0], sizeof(mmVM_FAULT_CLIENT_ID)/sizeof(mmVM_FAULT_CLIENT_ID[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x54f, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_85", REG_SMC, 0x55, &ixMC_IO_DEBUG_UP_85[0], sizeof(ixMC_IO_DEBUG_UP_85)/sizeof(ixMC_IO_DEBUG_UP_85[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x550, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x551, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x552, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x553, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x554, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x555, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x556, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR", REG_MMIO, 0x557, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR", REG_MMIO, 0x558, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR", REG_MMIO, 0x55f, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_86", REG_SMC, 0x56, &ixMC_IO_DEBUG_UP_86[0], sizeof(ixMC_IO_DEBUG_UP_86)/sizeof(ixMC_IO_DEBUG_UP_86[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR", REG_MMIO, 0x560, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "mmVM_DEBUG", REG_MMIO, 0x56f, &mmVM_DEBUG[0], sizeof(mmVM_DEBUG)/sizeof(mmVM_DEBUG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_87", REG_SMC, 0x57, &ixMC_IO_DEBUG_UP_87[0], sizeof(ixMC_IO_DEBUG_UP_87)/sizeof(ixMC_IO_DEBUG_UP_87[0]), 0, 0 },
+	{ "mmVM_L2_CG", REG_MMIO, 0x570, &mmVM_L2_CG[0], sizeof(mmVM_L2_CG)/sizeof(mmVM_L2_CG[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKA", REG_MMIO, 0x572, &mmVM_L2_BANK_SELECT_MASKA[0], sizeof(mmVM_L2_BANK_SELECT_MASKA)/sizeof(mmVM_L2_BANK_SELECT_MASKA[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKB", REG_MMIO, 0x573, &mmVM_L2_BANK_SELECT_MASKB[0], sizeof(mmVM_L2_BANK_SELECT_MASKB)/sizeof(mmVM_L2_BANK_SELECT_MASKB[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", REG_MMIO, 0x575, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", REG_MMIO, 0x576, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", REG_MMIO, 0x577, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0]), 0, 0 },
+	{ "mmVM_L2_CNTL4", REG_MMIO, 0x578, &mmVM_L2_CNTL4[0], sizeof(mmVM_L2_CNTL4)/sizeof(mmVM_L2_CNTL4[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_RESERVED_CID", REG_MMIO, 0x579, &mmVM_L2_BANK_SELECT_RESERVED_CID[0], sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID)/sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_RESERVED_CID2", REG_MMIO, 0x57a, &mmVM_L2_BANK_SELECT_RESERVED_CID2[0], sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID2)/sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_88", REG_SMC, 0x58, &ixMC_IO_DEBUG_UP_88[0], sizeof(ixMC_IO_DEBUG_UP_88)/sizeof(ixMC_IO_DEBUG_UP_88[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_89", REG_SMC, 0x59, &ixMC_IO_DEBUG_UP_89[0], sizeof(ixMC_IO_DEBUG_UP_89)/sizeof(ixMC_IO_DEBUG_UP_89[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_90", REG_SMC, 0x5a, &ixMC_IO_DEBUG_UP_90[0], sizeof(ixMC_IO_DEBUG_UP_90)/sizeof(ixMC_IO_DEBUG_UP_90[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_91", REG_SMC, 0x5b, &ixMC_IO_DEBUG_UP_91[0], sizeof(ixMC_IO_DEBUG_UP_91)/sizeof(ixMC_IO_DEBUG_UP_91[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_92", REG_SMC, 0x5c, &ixMC_IO_DEBUG_UP_92[0], sizeof(ixMC_IO_DEBUG_UP_92)/sizeof(ixMC_IO_DEBUG_UP_92[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_93", REG_SMC, 0x5d, &ixMC_IO_DEBUG_UP_93[0], sizeof(ixMC_IO_DEBUG_UP_93)/sizeof(ixMC_IO_DEBUG_UP_93[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_94", REG_SMC, 0x5e, &ixMC_IO_DEBUG_UP_94[0], sizeof(ixMC_IO_DEBUG_UP_94)/sizeof(ixMC_IO_DEBUG_UP_94[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x5e78, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x5e78, &mmMCIF_WB_BUFMGR_SW_CONTROL[0], sizeof(mmMCIF_WB_BUFMGR_SW_CONTROL)/sizeof(mmMCIF_WB_BUFMGR_SW_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x5e79, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x5e79, &mmMCIF_WB_BUFMGR_CUR_LINE_R[0], sizeof(mmMCIF_WB_BUFMGR_CUR_LINE_R)/sizeof(mmMCIF_WB_BUFMGR_CUR_LINE_R[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x5e7a, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x5e7a, &mmMCIF_WB_BUFMGR_STATUS[0], sizeof(mmMCIF_WB_BUFMGR_STATUS)/sizeof(mmMCIF_WB_BUFMGR_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_PITCH", REG_MMIO, 0x5e7b, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_PITCH", REG_MMIO, 0x5e7b, &mmMCIF_WB_BUF_PITCH[0], sizeof(mmMCIF_WB_BUF_PITCH)/sizeof(mmMCIF_WB_BUF_PITCH[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_STATUS", REG_MMIO, 0x5e7c, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_STATUS", REG_MMIO, 0x5e7c, &mmMCIF_WB_BUF_1_STATUS[0], sizeof(mmMCIF_WB_BUF_1_STATUS)/sizeof(mmMCIF_WB_BUF_1_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x5e7d, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x5e7d, &mmMCIF_WB_BUF_1_STATUS2[0], sizeof(mmMCIF_WB_BUF_1_STATUS2)/sizeof(mmMCIF_WB_BUF_1_STATUS2[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_STATUS", REG_MMIO, 0x5e7e, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_STATUS", REG_MMIO, 0x5e7e, &mmMCIF_WB_BUF_2_STATUS[0], sizeof(mmMCIF_WB_BUF_2_STATUS)/sizeof(mmMCIF_WB_BUF_2_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x5e7f, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x5e7f, &mmMCIF_WB_BUF_2_STATUS2[0], sizeof(mmMCIF_WB_BUF_2_STATUS2)/sizeof(mmMCIF_WB_BUF_2_STATUS2[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_STATUS", REG_MMIO, 0x5e80, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_STATUS", REG_MMIO, 0x5e80, &mmMCIF_WB_BUF_3_STATUS[0], sizeof(mmMCIF_WB_BUF_3_STATUS)/sizeof(mmMCIF_WB_BUF_3_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x5e81, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x5e81, &mmMCIF_WB_BUF_3_STATUS2[0], sizeof(mmMCIF_WB_BUF_3_STATUS2)/sizeof(mmMCIF_WB_BUF_3_STATUS2[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_STATUS", REG_MMIO, 0x5e82, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_STATUS", REG_MMIO, 0x5e82, &mmMCIF_WB_BUF_4_STATUS[0], sizeof(mmMCIF_WB_BUF_4_STATUS)/sizeof(mmMCIF_WB_BUF_4_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x5e83, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x5e83, &mmMCIF_WB_BUF_4_STATUS2[0], sizeof(mmMCIF_WB_BUF_4_STATUS2)/sizeof(mmMCIF_WB_BUF_4_STATUS2[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x5e84, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x5e84, &mmMCIF_WB_ARBITRATION_CONTROL[0], sizeof(mmMCIF_WB_ARBITRATION_CONTROL)/sizeof(mmMCIF_WB_ARBITRATION_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK", REG_MMIO, 0x5e85, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_URGENCY_WATERMARK", REG_MMIO, 0x5e85, &mmMCIF_WB_URGENCY_WATERMARK[0], sizeof(mmMCIF_WB_URGENCY_WATERMARK)/sizeof(mmMCIF_WB_URGENCY_WATERMARK[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX", REG_MMIO, 0x5e86, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_TEST_DEBUG_INDEX", REG_MMIO, 0x5e86, &mmMCIF_WB_TEST_DEBUG_INDEX[0], sizeof(mmMCIF_WB_TEST_DEBUG_INDEX)/sizeof(mmMCIF_WB_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA", REG_MMIO, 0x5e87, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_TEST_DEBUG_DATA", REG_MMIO, 0x5e87, &mmMCIF_WB_TEST_DEBUG_DATA[0], sizeof(mmMCIF_WB_TEST_DEBUG_DATA)/sizeof(mmMCIF_WB_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x5e88, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x5e88, &mmMCIF_WB_BUF_1_ADDR_Y[0], sizeof(mmMCIF_WB_BUF_1_ADDR_Y)/sizeof(mmMCIF_WB_BUF_1_ADDR_Y[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x5e89, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x5e89, &mmMCIF_WB_BUF_1_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB_BUF_1_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB_BUF_1_ADDR_Y_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x5e8a, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x5e8a, &mmMCIF_WB_BUF_1_ADDR_C[0], sizeof(mmMCIF_WB_BUF_1_ADDR_C)/sizeof(mmMCIF_WB_BUF_1_ADDR_C[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x5e8b, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x5e8b, &mmMCIF_WB_BUF_1_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB_BUF_1_ADDR_C_OFFSET)/sizeof(mmMCIF_WB_BUF_1_ADDR_C_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x5e8c, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x5e8c, &mmMCIF_WB_BUF_2_ADDR_Y[0], sizeof(mmMCIF_WB_BUF_2_ADDR_Y)/sizeof(mmMCIF_WB_BUF_2_ADDR_Y[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x5e8d, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x5e8d, &mmMCIF_WB_BUF_2_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB_BUF_2_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB_BUF_2_ADDR_Y_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x5e8e, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x5e8e, &mmMCIF_WB_BUF_2_ADDR_C[0], sizeof(mmMCIF_WB_BUF_2_ADDR_C)/sizeof(mmMCIF_WB_BUF_2_ADDR_C[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x5e8f, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x5e8f, &mmMCIF_WB_BUF_2_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB_BUF_2_ADDR_C_OFFSET)/sizeof(mmMCIF_WB_BUF_2_ADDR_C_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x5e90, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x5e90, &mmMCIF_WB_BUF_3_ADDR_Y[0], sizeof(mmMCIF_WB_BUF_3_ADDR_Y)/sizeof(mmMCIF_WB_BUF_3_ADDR_Y[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x5e91, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x5e91, &mmMCIF_WB_BUF_3_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB_BUF_3_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB_BUF_3_ADDR_Y_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x5e92, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x5e92, &mmMCIF_WB_BUF_3_ADDR_C[0], sizeof(mmMCIF_WB_BUF_3_ADDR_C)/sizeof(mmMCIF_WB_BUF_3_ADDR_C[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x5e93, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x5e93, &mmMCIF_WB_BUF_3_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB_BUF_3_ADDR_C_OFFSET)/sizeof(mmMCIF_WB_BUF_3_ADDR_C_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x5e94, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x5e94, &mmMCIF_WB_BUF_4_ADDR_Y[0], sizeof(mmMCIF_WB_BUF_4_ADDR_Y)/sizeof(mmMCIF_WB_BUF_4_ADDR_Y[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x5e95, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x5e95, &mmMCIF_WB_BUF_4_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB_BUF_4_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB_BUF_4_ADDR_Y_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x5e96, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x5e96, &mmMCIF_WB_BUF_4_ADDR_C[0], sizeof(mmMCIF_WB_BUF_4_ADDR_C)/sizeof(mmMCIF_WB_BUF_4_ADDR_C[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x5e97, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x5e97, &mmMCIF_WB_BUF_4_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB_BUF_4_ADDR_C_OFFSET)/sizeof(mmMCIF_WB_BUF_4_ADDR_C_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x5e98, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x5e98, &mmMCIF_WB_BUFMGR_VCE_CONTROL[0], sizeof(mmMCIF_WB_BUFMGR_VCE_CONTROL)/sizeof(mmMCIF_WB_BUFMGR_VCE_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL", REG_MMIO, 0x5e99, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_HVVMID_CONTROL", REG_MMIO, 0x5e99, &mmMCIF_WB_HVVMID_CONTROL[0], sizeof(mmMCIF_WB_HVVMID_CONTROL)/sizeof(mmMCIF_WB_HVVMID_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x5eb8, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x5eb9, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x5eba, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_PITCH", REG_MMIO, 0x5ebb, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_STATUS", REG_MMIO, 0x5ebc, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x5ebd, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_STATUS", REG_MMIO, 0x5ebe, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x5ebf, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_STATUS", REG_MMIO, 0x5ec0, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x5ec1, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_STATUS", REG_MMIO, 0x5ec2, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x5ec3, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x5ec4, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK", REG_MMIO, 0x5ec5, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX", REG_MMIO, 0x5ec6, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA", REG_MMIO, 0x5ec7, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x5ec8, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x5ec9, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x5eca, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x5ecb, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x5ecc, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x5ecd, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x5ece, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x5ecf, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x5ed0, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x5ed1, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x5ed2, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x5ed3, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x5ed4, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x5ed5, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x5ed6, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x5ed7, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x5ed8, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL", REG_MMIO, 0x5ed9, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x5ef8, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x5ef9, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x5efa, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_PITCH", REG_MMIO, 0x5efb, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_STATUS", REG_MMIO, 0x5efc, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x5efd, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_STATUS", REG_MMIO, 0x5efe, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x5eff, NULL, 0, 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_95", REG_SMC, 0x5f, &ixMC_IO_DEBUG_UP_95[0], sizeof(ixMC_IO_DEBUG_UP_95)/sizeof(ixMC_IO_DEBUG_UP_95[0]), 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_STATUS", REG_MMIO, 0x5f00, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x5f01, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_STATUS", REG_MMIO, 0x5f02, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x5f03, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x5f04, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK", REG_MMIO, 0x5f05, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX", REG_MMIO, 0x5f06, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA", REG_MMIO, 0x5f07, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x5f08, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x5f09, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x5f0a, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x5f0b, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x5f0c, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x5f0d, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x5f0e, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x5f0f, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x5f10, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x5f11, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x5f12, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x5f13, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x5f14, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x5f15, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x5f16, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x5f17, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x5f18, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL", REG_MMIO, 0x5f19, NULL, 0, 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT3", REG_SMC, 0x6, &ixMC_TSM_DEBUG_BCNT3[0], sizeof(ixMC_TSM_DEBUG_BCNT3)/sizeof(ixMC_TSM_DEBUG_BCNT3[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_6", REG_SMC, 0x6, &ixMC_IO_DEBUG_UP_6[0], sizeof(ixMC_IO_DEBUG_UP_6)/sizeof(ixMC_IO_DEBUG_UP_6[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_96", REG_SMC, 0x60, &ixMC_IO_DEBUG_UP_96[0], sizeof(ixMC_IO_DEBUG_UP_96)/sizeof(ixMC_IO_DEBUG_UP_96[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_97", REG_SMC, 0x61, &ixMC_IO_DEBUG_UP_97[0], sizeof(ixMC_IO_DEBUG_UP_97)/sizeof(ixMC_IO_DEBUG_UP_97[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_98", REG_SMC, 0x62, &ixMC_IO_DEBUG_UP_98[0], sizeof(ixMC_IO_DEBUG_UP_98)/sizeof(ixMC_IO_DEBUG_UP_98[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_99", REG_SMC, 0x63, &ixMC_IO_DEBUG_UP_99[0], sizeof(ixMC_IO_DEBUG_UP_99)/sizeof(ixMC_IO_DEBUG_UP_99[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_100", REG_SMC, 0x64, &ixMC_IO_DEBUG_UP_100[0], sizeof(ixMC_IO_DEBUG_UP_100)/sizeof(ixMC_IO_DEBUG_UP_100[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_101", REG_SMC, 0x65, &ixMC_IO_DEBUG_UP_101[0], sizeof(ixMC_IO_DEBUG_UP_101)/sizeof(ixMC_IO_DEBUG_UP_101[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_102", REG_SMC, 0x66, &ixMC_IO_DEBUG_UP_102[0], sizeof(ixMC_IO_DEBUG_UP_102)/sizeof(ixMC_IO_DEBUG_UP_102[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_103", REG_SMC, 0x67, &ixMC_IO_DEBUG_UP_103[0], sizeof(ixMC_IO_DEBUG_UP_103)/sizeof(ixMC_IO_DEBUG_UP_103[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_104", REG_SMC, 0x68, &ixMC_IO_DEBUG_UP_104[0], sizeof(ixMC_IO_DEBUG_UP_104)/sizeof(ixMC_IO_DEBUG_UP_104[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_105", REG_SMC, 0x69, &ixMC_IO_DEBUG_UP_105[0], sizeof(ixMC_IO_DEBUG_UP_105)/sizeof(ixMC_IO_DEBUG_UP_105[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_106", REG_SMC, 0x6a, &ixMC_IO_DEBUG_UP_106[0], sizeof(ixMC_IO_DEBUG_UP_106)/sizeof(ixMC_IO_DEBUG_UP_106[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_107", REG_SMC, 0x6b, &ixMC_IO_DEBUG_UP_107[0], sizeof(ixMC_IO_DEBUG_UP_107)/sizeof(ixMC_IO_DEBUG_UP_107[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_108", REG_SMC, 0x6c, &ixMC_IO_DEBUG_UP_108[0], sizeof(ixMC_IO_DEBUG_UP_108)/sizeof(ixMC_IO_DEBUG_UP_108[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_109", REG_SMC, 0x6d, &ixMC_IO_DEBUG_UP_109[0], sizeof(ixMC_IO_DEBUG_UP_109)/sizeof(ixMC_IO_DEBUG_UP_109[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_110", REG_SMC, 0x6e, &ixMC_IO_DEBUG_UP_110[0], sizeof(ixMC_IO_DEBUG_UP_110)/sizeof(ixMC_IO_DEBUG_UP_110[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_111", REG_SMC, 0x6f, &ixMC_IO_DEBUG_UP_111[0], sizeof(ixMC_IO_DEBUG_UP_111)/sizeof(ixMC_IO_DEBUG_UP_111[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT4", REG_SMC, 0x7, &ixMC_TSM_DEBUG_BCNT4[0], sizeof(ixMC_TSM_DEBUG_BCNT4)/sizeof(ixMC_TSM_DEBUG_BCNT4[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_7", REG_SMC, 0x7, &ixMC_IO_DEBUG_UP_7[0], sizeof(ixMC_IO_DEBUG_UP_7)/sizeof(ixMC_IO_DEBUG_UP_7[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_112", REG_SMC, 0x70, &ixMC_IO_DEBUG_UP_112[0], sizeof(ixMC_IO_DEBUG_UP_112)/sizeof(ixMC_IO_DEBUG_UP_112[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_113", REG_SMC, 0x71, &ixMC_IO_DEBUG_UP_113[0], sizeof(ixMC_IO_DEBUG_UP_113)/sizeof(ixMC_IO_DEBUG_UP_113[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_114", REG_SMC, 0x72, &ixMC_IO_DEBUG_UP_114[0], sizeof(ixMC_IO_DEBUG_UP_114)/sizeof(ixMC_IO_DEBUG_UP_114[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_115", REG_SMC, 0x73, &ixMC_IO_DEBUG_UP_115[0], sizeof(ixMC_IO_DEBUG_UP_115)/sizeof(ixMC_IO_DEBUG_UP_115[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_116", REG_SMC, 0x74, &ixMC_IO_DEBUG_UP_116[0], sizeof(ixMC_IO_DEBUG_UP_116)/sizeof(ixMC_IO_DEBUG_UP_116[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_117", REG_SMC, 0x75, &ixMC_IO_DEBUG_UP_117[0], sizeof(ixMC_IO_DEBUG_UP_117)/sizeof(ixMC_IO_DEBUG_UP_117[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_118", REG_SMC, 0x76, &ixMC_IO_DEBUG_UP_118[0], sizeof(ixMC_IO_DEBUG_UP_118)/sizeof(ixMC_IO_DEBUG_UP_118[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_119", REG_SMC, 0x77, &ixMC_IO_DEBUG_UP_119[0], sizeof(ixMC_IO_DEBUG_UP_119)/sizeof(ixMC_IO_DEBUG_UP_119[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_120", REG_SMC, 0x78, &ixMC_IO_DEBUG_UP_120[0], sizeof(ixMC_IO_DEBUG_UP_120)/sizeof(ixMC_IO_DEBUG_UP_120[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_121", REG_SMC, 0x79, &ixMC_IO_DEBUG_UP_121[0], sizeof(ixMC_IO_DEBUG_UP_121)/sizeof(ixMC_IO_DEBUG_UP_121[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_122", REG_SMC, 0x7a, &ixMC_IO_DEBUG_UP_122[0], sizeof(ixMC_IO_DEBUG_UP_122)/sizeof(ixMC_IO_DEBUG_UP_122[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_LO", REG_MMIO, 0x7a0, &mmMC_CITF_PERFCOUNTER_LO[0], sizeof(mmMC_CITF_PERFCOUNTER_LO)/sizeof(mmMC_CITF_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_LO", REG_MMIO, 0x7a1, &mmMC_HUB_PERFCOUNTER_LO[0], sizeof(mmMC_HUB_PERFCOUNTER_LO)/sizeof(mmMC_HUB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_LO", REG_MMIO, 0x7a2, &mmMC_RPB_PERFCOUNTER_LO[0], sizeof(mmMC_RPB_PERFCOUNTER_LO)/sizeof(mmMC_RPB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_LO", REG_MMIO, 0x7a3, &mmMC_MCBVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCBVM_PERFCOUNTER_LO)/sizeof(mmMC_MCBVM_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_LO", REG_MMIO, 0x7a4, &mmMC_MCDVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCDVM_PERFCOUNTER_LO)/sizeof(mmMC_MCDVM_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_LO", REG_MMIO, 0x7a5, &mmMC_VM_L2_PERFCOUNTER_LO[0], sizeof(mmMC_VM_L2_PERFCOUNTER_LO)/sizeof(mmMC_VM_L2_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_LO", REG_MMIO, 0x7a6, &mmMC_ARB_PERFCOUNTER_LO[0], sizeof(mmMC_ARB_PERFCOUNTER_LO)/sizeof(mmMC_ARB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_LO", REG_MMIO, 0x7a7, &mmATC_PERFCOUNTER_LO[0], sizeof(mmATC_PERFCOUNTER_LO)/sizeof(mmATC_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_HI", REG_MMIO, 0x7a8, &mmMC_CITF_PERFCOUNTER_HI[0], sizeof(mmMC_CITF_PERFCOUNTER_HI)/sizeof(mmMC_CITF_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_HI", REG_MMIO, 0x7a9, &mmMC_HUB_PERFCOUNTER_HI[0], sizeof(mmMC_HUB_PERFCOUNTER_HI)/sizeof(mmMC_HUB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_HI", REG_MMIO, 0x7aa, &mmMC_MCBVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCBVM_PERFCOUNTER_HI)/sizeof(mmMC_MCBVM_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_HI", REG_MMIO, 0x7ab, &mmMC_MCDVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCDVM_PERFCOUNTER_HI)/sizeof(mmMC_MCDVM_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_HI", REG_MMIO, 0x7ac, &mmMC_RPB_PERFCOUNTER_HI[0], sizeof(mmMC_RPB_PERFCOUNTER_HI)/sizeof(mmMC_RPB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_HI", REG_MMIO, 0x7ad, &mmMC_VM_L2_PERFCOUNTER_HI[0], sizeof(mmMC_VM_L2_PERFCOUNTER_HI)/sizeof(mmMC_VM_L2_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_HI", REG_MMIO, 0x7ae, &mmMC_ARB_PERFCOUNTER_HI[0], sizeof(mmMC_ARB_PERFCOUNTER_HI)/sizeof(mmMC_ARB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_HI", REG_MMIO, 0x7af, &mmATC_PERFCOUNTER_HI[0], sizeof(mmATC_PERFCOUNTER_HI)/sizeof(mmATC_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_123", REG_SMC, 0x7b, &ixMC_IO_DEBUG_UP_123[0], sizeof(ixMC_IO_DEBUG_UP_123)/sizeof(ixMC_IO_DEBUG_UP_123[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER0_CFG", REG_MMIO, 0x7b0, &mmMC_CITF_PERFCOUNTER0_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER0_CFG)/sizeof(mmMC_CITF_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER1_CFG", REG_MMIO, 0x7b1, &mmMC_CITF_PERFCOUNTER1_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER1_CFG)/sizeof(mmMC_CITF_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER2_CFG", REG_MMIO, 0x7b2, &mmMC_CITF_PERFCOUNTER2_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER2_CFG)/sizeof(mmMC_CITF_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER3_CFG", REG_MMIO, 0x7b3, &mmMC_CITF_PERFCOUNTER3_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER3_CFG)/sizeof(mmMC_CITF_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b4, &mmMC_HUB_PERFCOUNTER0_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER0_CFG)/sizeof(mmMC_HUB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b5, &mmMC_HUB_PERFCOUNTER1_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER1_CFG)/sizeof(mmMC_HUB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER2_CFG", REG_MMIO, 0x7b6, &mmMC_HUB_PERFCOUNTER2_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER2_CFG)/sizeof(mmMC_HUB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER3_CFG", REG_MMIO, 0x7b7, &mmMC_HUB_PERFCOUNTER3_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER3_CFG)/sizeof(mmMC_HUB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b8, &mmMC_RPB_PERFCOUNTER0_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER0_CFG)/sizeof(mmMC_RPB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b9, &mmMC_RPB_PERFCOUNTER1_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER1_CFG)/sizeof(mmMC_RPB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER2_CFG", REG_MMIO, 0x7ba, &mmMC_RPB_PERFCOUNTER2_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER2_CFG)/sizeof(mmMC_RPB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bb, &mmMC_RPB_PERFCOUNTER3_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER3_CFG)/sizeof(mmMC_RPB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER0_CFG", REG_MMIO, 0x7bc, &mmMC_ARB_PERFCOUNTER0_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER0_CFG)/sizeof(mmMC_ARB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER1_CFG", REG_MMIO, 0x7bd, &mmMC_ARB_PERFCOUNTER1_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER1_CFG)/sizeof(mmMC_ARB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER2_CFG", REG_MMIO, 0x7be, &mmMC_ARB_PERFCOUNTER2_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER2_CFG)/sizeof(mmMC_ARB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bf, &mmMC_ARB_PERFCOUNTER3_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER3_CFG)/sizeof(mmMC_ARB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_124", REG_SMC, 0x7c, &ixMC_IO_DEBUG_UP_124[0], sizeof(ixMC_IO_DEBUG_UP_124)/sizeof(ixMC_IO_DEBUG_UP_124[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c0, &mmMC_MCBVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c1, &mmMC_MCBVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c2, &mmMC_MCBVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c3, &mmMC_MCBVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c4, &mmMC_MCDVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c5, &mmMC_MCDVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c6, &mmMC_MCDVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c7, &mmMC_MCDVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7c8, &mmATC_PERFCOUNTER0_CFG[0], sizeof(mmATC_PERFCOUNTER0_CFG)/sizeof(mmATC_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7c9, &mmATC_PERFCOUNTER1_CFG[0], sizeof(mmATC_PERFCOUNTER1_CFG)/sizeof(mmATC_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER2_CFG", REG_MMIO, 0x7ca, &mmATC_PERFCOUNTER2_CFG[0], sizeof(mmATC_PERFCOUNTER2_CFG)/sizeof(mmATC_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER3_CFG", REG_MMIO, 0x7cb, &mmATC_PERFCOUNTER3_CFG[0], sizeof(mmATC_PERFCOUNTER3_CFG)/sizeof(mmATC_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x7cc, &mmMC_VM_L2_PERFCOUNTER0_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x7cd, &mmMC_VM_L2_PERFCOUNTER1_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7ce, &mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7cf, &mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_125", REG_SMC, 0x7d, &ixMC_IO_DEBUG_UP_125[0], sizeof(ixMC_IO_DEBUG_UP_125)/sizeof(ixMC_IO_DEBUG_UP_125[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d0, &mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d1, &mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d2, &mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d3, &mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d4, &mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d5, &mmATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_LO", REG_MMIO, 0x7d6, &mmCHUB_ATC_PERFCOUNTER_LO[0], sizeof(mmCHUB_ATC_PERFCOUNTER_LO)/sizeof(mmCHUB_ATC_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_HI", REG_MMIO, 0x7d7, &mmCHUB_ATC_PERFCOUNTER_HI[0], sizeof(mmCHUB_ATC_PERFCOUNTER_HI)/sizeof(mmCHUB_ATC_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7d8, &mmCHUB_ATC_PERFCOUNTER0_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7d9, &mmCHUB_ATC_PERFCOUNTER1_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7da, &mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_126", REG_SMC, 0x7e, &ixMC_IO_DEBUG_UP_126[0], sizeof(ixMC_IO_DEBUG_UP_126)/sizeof(ixMC_IO_DEBUG_UP_126[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_127", REG_SMC, 0x7f, &ixMC_IO_DEBUG_UP_127[0], sizeof(ixMC_IO_DEBUG_UP_127)/sizeof(ixMC_IO_DEBUG_UP_127[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT5", REG_SMC, 0x8, &ixMC_TSM_DEBUG_BCNT5[0], sizeof(ixMC_TSM_DEBUG_BCNT5)/sizeof(ixMC_TSM_DEBUG_BCNT5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_8", REG_SMC, 0x8, &ixMC_IO_DEBUG_UP_8[0], sizeof(ixMC_IO_DEBUG_UP_8)/sizeof(ixMC_IO_DEBUG_UP_8[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_128", REG_SMC, 0x80, &ixMC_IO_DEBUG_UP_128[0], sizeof(ixMC_IO_DEBUG_UP_128)/sizeof(ixMC_IO_DEBUG_UP_128[0]), 0, 0 },
+	{ "mmMC_CONFIG", REG_MMIO, 0x800, &mmMC_CONFIG[0], sizeof(mmMC_CONFIG)/sizeof(mmMC_CONFIG[0]), 0, 0 },
+	{ "mmMC_SHARED_CHMAP", REG_MMIO, 0x801, &mmMC_SHARED_CHMAP[0], sizeof(mmMC_SHARED_CHMAP)/sizeof(mmMC_SHARED_CHMAP[0]), 0, 0 },
+	{ "mmMC_SHARED_CHREMAP", REG_MMIO, 0x802, &mmMC_SHARED_CHREMAP[0], sizeof(mmMC_SHARED_CHREMAP)/sizeof(mmMC_SHARED_CHREMAP[0]), 0, 0 },
+	{ "mmMC_RD_GRP_GFX", REG_MMIO, 0x803, &mmMC_RD_GRP_GFX[0], sizeof(mmMC_RD_GRP_GFX)/sizeof(mmMC_RD_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_WR_GRP_GFX", REG_MMIO, 0x804, &mmMC_WR_GRP_GFX[0], sizeof(mmMC_WR_GRP_GFX)/sizeof(mmMC_WR_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_RD_GRP_SYS", REG_MMIO, 0x805, &mmMC_RD_GRP_SYS[0], sizeof(mmMC_RD_GRP_SYS)/sizeof(mmMC_RD_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_WR_GRP_SYS", REG_MMIO, 0x806, &mmMC_WR_GRP_SYS[0], sizeof(mmMC_WR_GRP_SYS)/sizeof(mmMC_WR_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_RD_GRP_OTH", REG_MMIO, 0x807, &mmMC_RD_GRP_OTH[0], sizeof(mmMC_RD_GRP_OTH)/sizeof(mmMC_RD_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_WR_GRP_OTH", REG_MMIO, 0x808, &mmMC_WR_GRP_OTH[0], sizeof(mmMC_WR_GRP_OTH)/sizeof(mmMC_WR_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_VM_FB_LOCATION", REG_MMIO, 0x809, &mmMC_VM_FB_LOCATION[0], sizeof(mmMC_VM_FB_LOCATION)/sizeof(mmMC_VM_FB_LOCATION[0]), 0, 0 },
+	{ "mmMC_VM_AGP_TOP", REG_MMIO, 0x80a, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BOT", REG_MMIO, 0x80b, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BASE", REG_MMIO, 0x80c, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x80d, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x80e, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", REG_MMIO, 0x80f, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_129", REG_SMC, 0x81, &ixMC_IO_DEBUG_UP_129[0], sizeof(ixMC_IO_DEBUG_UP_129)/sizeof(ixMC_IO_DEBUG_UP_129[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_CNTL", REG_MMIO, 0x810, &mmMC_VM_DC_WRITE_CNTL[0], sizeof(mmMC_VM_DC_WRITE_CNTL)/sizeof(mmMC_VM_DC_WRITE_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR", REG_MMIO, 0x811, &mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR", REG_MMIO, 0x812, &mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR", REG_MMIO, 0x813, &mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR", REG_MMIO, 0x814, &mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR", REG_MMIO, 0x815, &mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR", REG_MMIO, 0x816, &mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR", REG_MMIO, 0x817, &mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR", REG_MMIO, 0x818, &mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x819, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_FB_OFFSET", REG_MMIO, 0x81a, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 },
+	{ "mmMC_VM_STEERING", REG_MMIO, 0x81b, &mmMC_VM_STEERING[0], sizeof(mmMC_VM_STEERING)/sizeof(mmMC_VM_STEERING[0]), 0, 0 },
+	{ "mmMC_SHARED_CHREMAP2", REG_MMIO, 0x81c, &mmMC_SHARED_CHREMAP2[0], sizeof(mmMC_SHARED_CHREMAP2)/sizeof(mmMC_SHARED_CHREMAP2[0]), 0, 0 },
+	{ "mmMC_SHARED_VF_ENABLE", REG_MMIO, 0x81d, &mmMC_SHARED_VF_ENABLE[0], sizeof(mmMC_SHARED_VF_ENABLE)/sizeof(mmMC_SHARED_VF_ENABLE[0]), 0, 0 },
+	{ "mmMC_SHARED_VIRT_RESET_REQ", REG_MMIO, 0x81e, &mmMC_SHARED_VIRT_RESET_REQ[0], sizeof(mmMC_SHARED_VIRT_RESET_REQ)/sizeof(mmMC_SHARED_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmMC_SHARED_ACTIVE_FCN_ID", REG_MMIO, 0x81f, &mmMC_SHARED_ACTIVE_FCN_ID[0], sizeof(mmMC_SHARED_ACTIVE_FCN_ID)/sizeof(mmMC_SHARED_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_130", REG_SMC, 0x82, &ixMC_IO_DEBUG_UP_130[0], sizeof(ixMC_IO_DEBUG_UP_130)/sizeof(ixMC_IO_DEBUG_UP_130[0]), 0, 0 },
+	{ "mmMC_CONFIG_MCD", REG_MMIO, 0x828, &mmMC_CONFIG_MCD[0], sizeof(mmMC_CONFIG_MCD)/sizeof(mmMC_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG_MCD", REG_MMIO, 0x829, &mmMC_CG_CONFIG_MCD[0], sizeof(mmMC_CG_CONFIG_MCD)/sizeof(mmMC_CG_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_MEM_POWER_LS", REG_MMIO, 0x82a, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 },
+	{ "mmMC_SHARED_BLACKOUT_CNTL", REG_MMIO, 0x82b, &mmMC_SHARED_BLACKOUT_CNTL[0], sizeof(mmMC_SHARED_BLACKOUT_CNTL)/sizeof(mmMC_SHARED_BLACKOUT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_POWER", REG_MMIO, 0x82d, &mmMC_HUB_MISC_POWER[0], sizeof(mmMC_HUB_MISC_POWER)/sizeof(mmMC_HUB_MISC_POWER[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_HUB_CG", REG_MMIO, 0x82e, &mmMC_HUB_MISC_HUB_CG[0], sizeof(mmMC_HUB_MISC_HUB_CG)/sizeof(mmMC_HUB_MISC_HUB_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_VM_CG", REG_MMIO, 0x82f, &mmMC_HUB_MISC_VM_CG[0], sizeof(mmMC_HUB_MISC_VM_CG)/sizeof(mmMC_HUB_MISC_VM_CG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_131", REG_SMC, 0x83, &ixMC_IO_DEBUG_UP_131[0], sizeof(ixMC_IO_DEBUG_UP_131)/sizeof(ixMC_IO_DEBUG_UP_131[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_SIP_CG", REG_MMIO, 0x830, &mmMC_HUB_MISC_SIP_CG[0], sizeof(mmMC_HUB_MISC_SIP_CG)/sizeof(mmMC_HUB_MISC_SIP_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_STATUS", REG_MMIO, 0x832, &mmMC_HUB_MISC_STATUS[0], sizeof(mmMC_HUB_MISC_STATUS)/sizeof(mmMC_HUB_MISC_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_OVERRIDE", REG_MMIO, 0x833, &mmMC_HUB_MISC_OVERRIDE[0], sizeof(mmMC_HUB_MISC_OVERRIDE)/sizeof(mmMC_HUB_MISC_OVERRIDE[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_FRAMING", REG_MMIO, 0x834, &mmMC_HUB_MISC_FRAMING[0], sizeof(mmMC_HUB_MISC_FRAMING)/sizeof(mmMC_HUB_MISC_FRAMING[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CNTL", REG_MMIO, 0x835, &mmMC_HUB_WDP_CNTL[0], sizeof(mmMC_HUB_WDP_CNTL)/sizeof(mmMC_HUB_WDP_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ERR", REG_MMIO, 0x836, &mmMC_HUB_WDP_ERR[0], sizeof(mmMC_HUB_WDP_ERR)/sizeof(mmMC_HUB_WDP_ERR[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BP", REG_MMIO, 0x837, &mmMC_HUB_WDP_BP[0], sizeof(mmMC_HUB_WDP_BP)/sizeof(mmMC_HUB_WDP_BP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_STATUS", REG_MMIO, 0x838, &mmMC_HUB_WDP_STATUS[0], sizeof(mmMC_HUB_WDP_STATUS)/sizeof(mmMC_HUB_WDP_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_STATUS", REG_MMIO, 0x839, &mmMC_HUB_RDREQ_STATUS[0], sizeof(mmMC_HUB_RDREQ_STATUS)/sizeof(mmMC_HUB_RDREQ_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_STATUS", REG_MMIO, 0x83a, &mmMC_HUB_WRRET_STATUS[0], sizeof(mmMC_HUB_WRRET_STATUS)/sizeof(mmMC_HUB_WRRET_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CNTL", REG_MMIO, 0x83b, &mmMC_HUB_RDREQ_CNTL[0], sizeof(mmMC_HUB_RDREQ_CNTL)/sizeof(mmMC_HUB_RDREQ_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_CNTL", REG_MMIO, 0x83c, &mmMC_HUB_WRRET_CNTL[0], sizeof(mmMC_HUB_WRRET_CNTL)/sizeof(mmMC_HUB_WRRET_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_WTM_CNTL", REG_MMIO, 0x83d, &mmMC_HUB_RDREQ_WTM_CNTL[0], sizeof(mmMC_HUB_RDREQ_WTM_CNTL)/sizeof(mmMC_HUB_RDREQ_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_WTM_CNTL", REG_MMIO, 0x83e, &mmMC_HUB_WDP_WTM_CNTL[0], sizeof(mmMC_HUB_WDP_WTM_CNTL)/sizeof(mmMC_HUB_WDP_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS", REG_MMIO, 0x83f, &mmMC_HUB_WDP_CREDITS[0], sizeof(mmMC_HUB_WDP_CREDITS)/sizeof(mmMC_HUB_WDP_CREDITS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_132", REG_SMC, 0x84, &ixMC_IO_DEBUG_UP_132[0], sizeof(ixMC_IO_DEBUG_UP_132)/sizeof(ixMC_IO_DEBUG_UP_132[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS2", REG_MMIO, 0x840, &mmMC_HUB_WDP_CREDITS2[0], sizeof(mmMC_HUB_WDP_CREDITS2)/sizeof(mmMC_HUB_WDP_CREDITS2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL0", REG_MMIO, 0x841, &mmMC_HUB_WDP_GBL0[0], sizeof(mmMC_HUB_WDP_GBL0)/sizeof(mmMC_HUB_WDP_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL1", REG_MMIO, 0x842, &mmMC_HUB_WDP_GBL1[0], sizeof(mmMC_HUB_WDP_GBL1)/sizeof(mmMC_HUB_WDP_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS3", REG_MMIO, 0x843, &mmMC_HUB_WDP_CREDITS3[0], sizeof(mmMC_HUB_WDP_CREDITS3)/sizeof(mmMC_HUB_WDP_CREDITS3[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS", REG_MMIO, 0x844, &mmMC_HUB_RDREQ_CREDITS[0], sizeof(mmMC_HUB_RDREQ_CREDITS)/sizeof(mmMC_HUB_RDREQ_CREDITS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS2", REG_MMIO, 0x845, &mmMC_HUB_RDREQ_CREDITS2[0], sizeof(mmMC_HUB_RDREQ_CREDITS2)/sizeof(mmMC_HUB_RDREQ_CREDITS2[0]), 0, 0 },
+	{ "mmMC_HUB_SHARED_DAGB_DLY", REG_MMIO, 0x846, &mmMC_HUB_SHARED_DAGB_DLY[0], sizeof(mmMC_HUB_SHARED_DAGB_DLY)/sizeof(mmMC_HUB_SHARED_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_IDLE_STATUS", REG_MMIO, 0x847, &mmMC_HUB_MISC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_IDLE_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF_LIMIT", REG_MMIO, 0x848, &mmMC_HUB_RDREQ_DMIF_LIMIT[0], sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT)/sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPG_LIMIT", REG_MMIO, 0x849, &mmMC_HUB_RDREQ_ACPG_LIMIT[0], sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT)/sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BYPASS_GBL0", REG_MMIO, 0x84a, &mmMC_HUB_WDP_BYPASS_GBL0[0], sizeof(mmMC_HUB_WDP_BYPASS_GBL0)/sizeof(mmMC_HUB_WDP_BYPASS_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BYPASS_GBL1", REG_MMIO, 0x84b, &mmMC_HUB_WDP_BYPASS_GBL1[0], sizeof(mmMC_HUB_WDP_BYPASS_GBL1)/sizeof(mmMC_HUB_WDP_BYPASS_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_BYPASS_GBL0", REG_MMIO, 0x84c, &mmMC_HUB_RDREQ_BYPASS_GBL0[0], sizeof(mmMC_HUB_RDREQ_BYPASS_GBL0)/sizeof(mmMC_HUB_RDREQ_BYPASS_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH2", REG_MMIO, 0x84d, &mmMC_HUB_WDP_SH2[0], sizeof(mmMC_HUB_WDP_SH2)/sizeof(mmMC_HUB_WDP_SH2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH3", REG_MMIO, 0x84e, &mmMC_HUB_WDP_SH3[0], sizeof(mmMC_HUB_WDP_SH3)/sizeof(mmMC_HUB_WDP_SH3[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_ATOMIC_IDLE_STATUS", REG_MMIO, 0x84f, &mmMC_HUB_MISC_ATOMIC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_ATOMIC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_ATOMIC_IDLE_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_133", REG_SMC, 0x85, &ixMC_IO_DEBUG_UP_133[0], sizeof(ixMC_IO_DEBUG_UP_133)/sizeof(ixMC_IO_DEBUG_UP_133[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VIN0", REG_MMIO, 0x850, &mmMC_HUB_WDP_VIN0[0], sizeof(mmMC_HUB_WDP_VIN0)/sizeof(mmMC_HUB_WDP_VIN0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDW", REG_MMIO, 0x851, &mmMC_HUB_RDREQ_MCDW[0], sizeof(mmMC_HUB_RDREQ_MCDW)/sizeof(mmMC_HUB_RDREQ_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDX", REG_MMIO, 0x852, &mmMC_HUB_RDREQ_MCDX[0], sizeof(mmMC_HUB_RDREQ_MCDX)/sizeof(mmMC_HUB_RDREQ_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDY", REG_MMIO, 0x853, &mmMC_HUB_RDREQ_MCDY[0], sizeof(mmMC_HUB_RDREQ_MCDY)/sizeof(mmMC_HUB_RDREQ_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDZ", REG_MMIO, 0x854, &mmMC_HUB_RDREQ_MCDZ[0], sizeof(mmMC_HUB_RDREQ_MCDZ)/sizeof(mmMC_HUB_RDREQ_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SIP", REG_MMIO, 0x855, &mmMC_HUB_RDREQ_SIP[0], sizeof(mmMC_HUB_RDREQ_SIP)/sizeof(mmMC_HUB_RDREQ_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL0", REG_MMIO, 0x856, &mmMC_HUB_RDREQ_GBL0[0], sizeof(mmMC_HUB_RDREQ_GBL0)/sizeof(mmMC_HUB_RDREQ_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL1", REG_MMIO, 0x857, &mmMC_HUB_RDREQ_GBL1[0], sizeof(mmMC_HUB_RDREQ_GBL1)/sizeof(mmMC_HUB_RDREQ_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SMU", REG_MMIO, 0x858, &mmMC_HUB_RDREQ_SMU[0], sizeof(mmMC_HUB_RDREQ_SMU)/sizeof(mmMC_HUB_RDREQ_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SDMA0", REG_MMIO, 0x859, &mmMC_HUB_RDREQ_SDMA0[0], sizeof(mmMC_HUB_RDREQ_SDMA0)/sizeof(mmMC_HUB_RDREQ_SDMA0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_HDP", REG_MMIO, 0x85a, &mmMC_HUB_RDREQ_HDP[0], sizeof(mmMC_HUB_RDREQ_HDP)/sizeof(mmMC_HUB_RDREQ_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SDMA1", REG_MMIO, 0x85b, &mmMC_HUB_RDREQ_SDMA1[0], sizeof(mmMC_HUB_RDREQ_SDMA1)/sizeof(mmMC_HUB_RDREQ_SDMA1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_RLC", REG_MMIO, 0x85c, &mmMC_HUB_RDREQ_RLC[0], sizeof(mmMC_HUB_RDREQ_RLC)/sizeof(mmMC_HUB_RDREQ_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SEM", REG_MMIO, 0x85d, &mmMC_HUB_RDREQ_SEM[0], sizeof(mmMC_HUB_RDREQ_SEM)/sizeof(mmMC_HUB_RDREQ_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCE0", REG_MMIO, 0x85e, &mmMC_HUB_RDREQ_VCE0[0], sizeof(mmMC_HUB_RDREQ_VCE0)/sizeof(mmMC_HUB_RDREQ_VCE0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UMC", REG_MMIO, 0x85f, &mmMC_HUB_RDREQ_UMC[0], sizeof(mmMC_HUB_RDREQ_UMC)/sizeof(mmMC_HUB_RDREQ_UMC[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_134", REG_SMC, 0x86, &ixMC_IO_DEBUG_UP_134[0], sizeof(ixMC_IO_DEBUG_UP_134)/sizeof(ixMC_IO_DEBUG_UP_134[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UVD", REG_MMIO, 0x860, &mmMC_HUB_RDREQ_UVD[0], sizeof(mmMC_HUB_RDREQ_UVD)/sizeof(mmMC_HUB_RDREQ_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_TLS", REG_MMIO, 0x861, &mmMC_HUB_RDREQ_TLS[0], sizeof(mmMC_HUB_RDREQ_TLS)/sizeof(mmMC_HUB_RDREQ_TLS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF", REG_MMIO, 0x862, &mmMC_HUB_RDREQ_DMIF[0], sizeof(mmMC_HUB_RDREQ_DMIF)/sizeof(mmMC_HUB_RDREQ_DMIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCIF", REG_MMIO, 0x863, &mmMC_HUB_RDREQ_MCIF[0], sizeof(mmMC_HUB_RDREQ_MCIF)/sizeof(mmMC_HUB_RDREQ_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VMC", REG_MMIO, 0x864, &mmMC_HUB_RDREQ_VMC[0], sizeof(mmMC_HUB_RDREQ_VMC)/sizeof(mmMC_HUB_RDREQ_VMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCEU0", REG_MMIO, 0x865, &mmMC_HUB_RDREQ_VCEU0[0], sizeof(mmMC_HUB_RDREQ_VCEU0)/sizeof(mmMC_HUB_RDREQ_VCEU0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDW", REG_MMIO, 0x866, &mmMC_HUB_WDP_MCDW[0], sizeof(mmMC_HUB_WDP_MCDW)/sizeof(mmMC_HUB_WDP_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDX", REG_MMIO, 0x867, &mmMC_HUB_WDP_MCDX[0], sizeof(mmMC_HUB_WDP_MCDX)/sizeof(mmMC_HUB_WDP_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDY", REG_MMIO, 0x868, &mmMC_HUB_WDP_MCDY[0], sizeof(mmMC_HUB_WDP_MCDY)/sizeof(mmMC_HUB_WDP_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDZ", REG_MMIO, 0x869, &mmMC_HUB_WDP_MCDZ[0], sizeof(mmMC_HUB_WDP_MCDZ)/sizeof(mmMC_HUB_WDP_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SIP", REG_MMIO, 0x86a, &mmMC_HUB_WDP_SIP[0], sizeof(mmMC_HUB_WDP_SIP)/sizeof(mmMC_HUB_WDP_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SDMA1", REG_MMIO, 0x86b, &mmMC_HUB_WDP_SDMA1[0], sizeof(mmMC_HUB_WDP_SDMA1)/sizeof(mmMC_HUB_WDP_SDMA1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH0", REG_MMIO, 0x86c, &mmMC_HUB_WDP_SH0[0], sizeof(mmMC_HUB_WDP_SH0)/sizeof(mmMC_HUB_WDP_SH0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCIF", REG_MMIO, 0x86d, &mmMC_HUB_WDP_MCIF[0], sizeof(mmMC_HUB_WDP_MCIF)/sizeof(mmMC_HUB_WDP_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCE0", REG_MMIO, 0x86e, &mmMC_HUB_WDP_VCE0[0], sizeof(mmMC_HUB_WDP_VCE0)/sizeof(mmMC_HUB_WDP_VCE0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDP", REG_MMIO, 0x86f, &mmMC_HUB_WDP_XDP[0], sizeof(mmMC_HUB_WDP_XDP)/sizeof(mmMC_HUB_WDP_XDP[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_135", REG_SMC, 0x87, &ixMC_IO_DEBUG_UP_135[0], sizeof(ixMC_IO_DEBUG_UP_135)/sizeof(ixMC_IO_DEBUG_UP_135[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_IH", REG_MMIO, 0x870, &mmMC_HUB_WDP_IH[0], sizeof(mmMC_HUB_WDP_IH)/sizeof(mmMC_HUB_WDP_IH[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_RLC", REG_MMIO, 0x871, &mmMC_HUB_WDP_RLC[0], sizeof(mmMC_HUB_WDP_RLC)/sizeof(mmMC_HUB_WDP_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SEM", REG_MMIO, 0x872, &mmMC_HUB_WDP_SEM[0], sizeof(mmMC_HUB_WDP_SEM)/sizeof(mmMC_HUB_WDP_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SMU", REG_MMIO, 0x873, &mmMC_HUB_WDP_SMU[0], sizeof(mmMC_HUB_WDP_SMU)/sizeof(mmMC_HUB_WDP_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH1", REG_MMIO, 0x874, &mmMC_HUB_WDP_SH1[0], sizeof(mmMC_HUB_WDP_SH1)/sizeof(mmMC_HUB_WDP_SH1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UMC", REG_MMIO, 0x875, &mmMC_HUB_WDP_UMC[0], sizeof(mmMC_HUB_WDP_UMC)/sizeof(mmMC_HUB_WDP_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UVD", REG_MMIO, 0x876, &mmMC_HUB_WDP_UVD[0], sizeof(mmMC_HUB_WDP_UVD)/sizeof(mmMC_HUB_WDP_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_HDP", REG_MMIO, 0x877, &mmMC_HUB_WDP_HDP[0], sizeof(mmMC_HUB_WDP_HDP)/sizeof(mmMC_HUB_WDP_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SDMA0", REG_MMIO, 0x878, &mmMC_HUB_WDP_SDMA0[0], sizeof(mmMC_HUB_WDP_SDMA0)/sizeof(mmMC_HUB_WDP_SDMA0[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDW", REG_MMIO, 0x879, &mmMC_HUB_WRRET_MCDW[0], sizeof(mmMC_HUB_WRRET_MCDW)/sizeof(mmMC_HUB_WRRET_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDX", REG_MMIO, 0x87a, &mmMC_HUB_WRRET_MCDX[0], sizeof(mmMC_HUB_WRRET_MCDX)/sizeof(mmMC_HUB_WRRET_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDY", REG_MMIO, 0x87b, &mmMC_HUB_WRRET_MCDY[0], sizeof(mmMC_HUB_WRRET_MCDY)/sizeof(mmMC_HUB_WRRET_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDZ", REG_MMIO, 0x87c, &mmMC_HUB_WRRET_MCDZ[0], sizeof(mmMC_HUB_WRRET_MCDZ)/sizeof(mmMC_HUB_WRRET_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCEU0", REG_MMIO, 0x87d, &mmMC_HUB_WDP_VCEU0[0], sizeof(mmMC_HUB_WDP_VCEU0)/sizeof(mmMC_HUB_WDP_VCEU0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMAM", REG_MMIO, 0x87e, &mmMC_HUB_WDP_XDMAM[0], sizeof(mmMC_HUB_WDP_XDMAM)/sizeof(mmMC_HUB_WDP_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMA", REG_MMIO, 0x87f, &mmMC_HUB_WDP_XDMA[0], sizeof(mmMC_HUB_WDP_XDMA)/sizeof(mmMC_HUB_WDP_XDMA[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_136", REG_SMC, 0x88, &ixMC_IO_DEBUG_UP_136[0], sizeof(ixMC_IO_DEBUG_UP_136)/sizeof(ixMC_IO_DEBUG_UP_136[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_XDMAM", REG_MMIO, 0x880, &mmMC_HUB_RDREQ_XDMAM[0], sizeof(mmMC_HUB_RDREQ_XDMAM)/sizeof(mmMC_HUB_RDREQ_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPG", REG_MMIO, 0x881, &mmMC_HUB_RDREQ_ACPG[0], sizeof(mmMC_HUB_RDREQ_ACPG)/sizeof(mmMC_HUB_RDREQ_ACPG[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPO", REG_MMIO, 0x882, &mmMC_HUB_RDREQ_ACPO[0], sizeof(mmMC_HUB_RDREQ_ACPO)/sizeof(mmMC_HUB_RDREQ_ACPO[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SAMMSP", REG_MMIO, 0x883, &mmMC_HUB_RDREQ_SAMMSP[0], sizeof(mmMC_HUB_RDREQ_SAMMSP)/sizeof(mmMC_HUB_RDREQ_SAMMSP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VP8", REG_MMIO, 0x884, &mmMC_HUB_RDREQ_VP8[0], sizeof(mmMC_HUB_RDREQ_VP8)/sizeof(mmMC_HUB_RDREQ_VP8[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VP8U", REG_MMIO, 0x885, &mmMC_HUB_RDREQ_VP8U[0], sizeof(mmMC_HUB_RDREQ_VP8U)/sizeof(mmMC_HUB_RDREQ_VP8U[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ACPG", REG_MMIO, 0x886, &mmMC_HUB_WDP_ACPG[0], sizeof(mmMC_HUB_WDP_ACPG)/sizeof(mmMC_HUB_WDP_ACPG[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ACPO", REG_MMIO, 0x887, &mmMC_HUB_WDP_ACPO[0], sizeof(mmMC_HUB_WDP_ACPO)/sizeof(mmMC_HUB_WDP_ACPO[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SAMMSP", REG_MMIO, 0x888, &mmMC_HUB_WDP_SAMMSP[0], sizeof(mmMC_HUB_WDP_SAMMSP)/sizeof(mmMC_HUB_WDP_SAMMSP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VP8", REG_MMIO, 0x889, &mmMC_HUB_WDP_VP8[0], sizeof(mmMC_HUB_WDP_VP8)/sizeof(mmMC_HUB_WDP_VP8[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VP8U", REG_MMIO, 0x88a, &mmMC_HUB_WDP_VP8U[0], sizeof(mmMC_HUB_WDP_VP8U)/sizeof(mmMC_HUB_WDP_VP8U[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_137", REG_SMC, 0x89, &ixMC_IO_DEBUG_UP_137[0], sizeof(ixMC_IO_DEBUG_UP_137)/sizeof(ixMC_IO_DEBUG_UP_137[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_DEBUG", REG_MMIO, 0x891, &mmMC_VM_MB_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB1_DEBUG", REG_MMIO, 0x892, &mmMC_VM_MB_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB1_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_DEBUG", REG_MMIO, 0x893, &mmMC_VM_MB_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_STATUS", REG_MMIO, 0x895, &mmMC_VM_MB_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB0_STATUS)/sizeof(mmMC_VM_MB_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB1_STATUS", REG_MMIO, 0x896, &mmMC_VM_MB_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB1_STATUS)/sizeof(mmMC_VM_MB_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_STATUS", REG_MMIO, 0x897, &mmMC_VM_MB_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB2_STATUS)/sizeof(mmMC_VM_MB_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_138", REG_SMC, 0x8a, &ixMC_IO_DEBUG_UP_138[0], sizeof(ixMC_IO_DEBUG_UP_138)/sizeof(ixMC_IO_DEBUG_UP_138[0]), 0, 0 },
+	{ "mmMC_VM_MB_L2ARBITER_L2_CREDITS", REG_MMIO, 0x8a1, &mmMC_VM_MB_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_DEBUG", REG_MMIO, 0x8a5, &mmMC_VM_MB_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_STATUS", REG_MMIO, 0x8a6, &mmMC_VM_MB_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB3_STATUS)/sizeof(mmMC_VM_MB_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_139", REG_SMC, 0x8b, &ixMC_IO_DEBUG_UP_139[0], sizeof(ixMC_IO_DEBUG_UP_139)/sizeof(ixMC_IO_DEBUG_UP_139[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_140", REG_SMC, 0x8c, &ixMC_IO_DEBUG_UP_140[0], sizeof(ixMC_IO_DEBUG_UP_140)/sizeof(ixMC_IO_DEBUG_UP_140[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR0", REG_MMIO, 0x8cd, &mmMC_XPB_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR1", REG_MMIO, 0x8ce, &mmMC_XPB_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR2", REG_MMIO, 0x8cf, &mmMC_XPB_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_141", REG_SMC, 0x8d, &ixMC_IO_DEBUG_UP_141[0], sizeof(ixMC_IO_DEBUG_UP_141)/sizeof(ixMC_IO_DEBUG_UP_141[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR3", REG_MMIO, 0x8d0, &mmMC_XPB_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR4", REG_MMIO, 0x8d1, &mmMC_XPB_RTR_SRC_APRTR4[0], sizeof(mmMC_XPB_RTR_SRC_APRTR4)/sizeof(mmMC_XPB_RTR_SRC_APRTR4[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR5", REG_MMIO, 0x8d2, &mmMC_XPB_RTR_SRC_APRTR5[0], sizeof(mmMC_XPB_RTR_SRC_APRTR5)/sizeof(mmMC_XPB_RTR_SRC_APRTR5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR6", REG_MMIO, 0x8d3, &mmMC_XPB_RTR_SRC_APRTR6[0], sizeof(mmMC_XPB_RTR_SRC_APRTR6)/sizeof(mmMC_XPB_RTR_SRC_APRTR6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR7", REG_MMIO, 0x8d4, &mmMC_XPB_RTR_SRC_APRTR7[0], sizeof(mmMC_XPB_RTR_SRC_APRTR7)/sizeof(mmMC_XPB_RTR_SRC_APRTR7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR8", REG_MMIO, 0x8d5, &mmMC_XPB_RTR_SRC_APRTR8[0], sizeof(mmMC_XPB_RTR_SRC_APRTR8)/sizeof(mmMC_XPB_RTR_SRC_APRTR8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR9", REG_MMIO, 0x8d6, &mmMC_XPB_RTR_SRC_APRTR9[0], sizeof(mmMC_XPB_RTR_SRC_APRTR9)/sizeof(mmMC_XPB_RTR_SRC_APRTR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR0", REG_MMIO, 0x8d7, &mmMC_XPB_XDMA_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR1", REG_MMIO, 0x8d8, &mmMC_XPB_XDMA_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR2", REG_MMIO, 0x8d9, &mmMC_XPB_XDMA_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR3", REG_MMIO, 0x8da, &mmMC_XPB_XDMA_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP0", REG_MMIO, 0x8db, &mmMC_XPB_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_RTR_DEST_MAP0)/sizeof(mmMC_XPB_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP1", REG_MMIO, 0x8dc, &mmMC_XPB_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_RTR_DEST_MAP1)/sizeof(mmMC_XPB_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP2", REG_MMIO, 0x8dd, &mmMC_XPB_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_RTR_DEST_MAP2)/sizeof(mmMC_XPB_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP3", REG_MMIO, 0x8de, &mmMC_XPB_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_RTR_DEST_MAP3)/sizeof(mmMC_XPB_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP4", REG_MMIO, 0x8df, &mmMC_XPB_RTR_DEST_MAP4[0], sizeof(mmMC_XPB_RTR_DEST_MAP4)/sizeof(mmMC_XPB_RTR_DEST_MAP4[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_142", REG_SMC, 0x8e, &ixMC_IO_DEBUG_UP_142[0], sizeof(ixMC_IO_DEBUG_UP_142)/sizeof(ixMC_IO_DEBUG_UP_142[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP5", REG_MMIO, 0x8e0, &mmMC_XPB_RTR_DEST_MAP5[0], sizeof(mmMC_XPB_RTR_DEST_MAP5)/sizeof(mmMC_XPB_RTR_DEST_MAP5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP6", REG_MMIO, 0x8e1, &mmMC_XPB_RTR_DEST_MAP6[0], sizeof(mmMC_XPB_RTR_DEST_MAP6)/sizeof(mmMC_XPB_RTR_DEST_MAP6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP7", REG_MMIO, 0x8e2, &mmMC_XPB_RTR_DEST_MAP7[0], sizeof(mmMC_XPB_RTR_DEST_MAP7)/sizeof(mmMC_XPB_RTR_DEST_MAP7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP8", REG_MMIO, 0x8e3, &mmMC_XPB_RTR_DEST_MAP8[0], sizeof(mmMC_XPB_RTR_DEST_MAP8)/sizeof(mmMC_XPB_RTR_DEST_MAP8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP9", REG_MMIO, 0x8e4, &mmMC_XPB_RTR_DEST_MAP9[0], sizeof(mmMC_XPB_RTR_DEST_MAP9)/sizeof(mmMC_XPB_RTR_DEST_MAP9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP0", REG_MMIO, 0x8e5, &mmMC_XPB_XDMA_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP1", REG_MMIO, 0x8e6, &mmMC_XPB_XDMA_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP2", REG_MMIO, 0x8e7, &mmMC_XPB_XDMA_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP3", REG_MMIO, 0x8e8, &mmMC_XPB_XDMA_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG0", REG_MMIO, 0x8e9, &mmMC_XPB_CLG_CFG0[0], sizeof(mmMC_XPB_CLG_CFG0)/sizeof(mmMC_XPB_CLG_CFG0[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG1", REG_MMIO, 0x8ea, &mmMC_XPB_CLG_CFG1[0], sizeof(mmMC_XPB_CLG_CFG1)/sizeof(mmMC_XPB_CLG_CFG1[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG2", REG_MMIO, 0x8eb, &mmMC_XPB_CLG_CFG2[0], sizeof(mmMC_XPB_CLG_CFG2)/sizeof(mmMC_XPB_CLG_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG3", REG_MMIO, 0x8ec, &mmMC_XPB_CLG_CFG3[0], sizeof(mmMC_XPB_CLG_CFG3)/sizeof(mmMC_XPB_CLG_CFG3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG4", REG_MMIO, 0x8ed, &mmMC_XPB_CLG_CFG4[0], sizeof(mmMC_XPB_CLG_CFG4)/sizeof(mmMC_XPB_CLG_CFG4[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG5", REG_MMIO, 0x8ee, &mmMC_XPB_CLG_CFG5[0], sizeof(mmMC_XPB_CLG_CFG5)/sizeof(mmMC_XPB_CLG_CFG5[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG6", REG_MMIO, 0x8ef, &mmMC_XPB_CLG_CFG6[0], sizeof(mmMC_XPB_CLG_CFG6)/sizeof(mmMC_XPB_CLG_CFG6[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_143", REG_SMC, 0x8f, &ixMC_IO_DEBUG_UP_143[0], sizeof(ixMC_IO_DEBUG_UP_143)/sizeof(ixMC_IO_DEBUG_UP_143[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG7", REG_MMIO, 0x8f0, &mmMC_XPB_CLG_CFG7[0], sizeof(mmMC_XPB_CLG_CFG7)/sizeof(mmMC_XPB_CLG_CFG7[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG8", REG_MMIO, 0x8f1, &mmMC_XPB_CLG_CFG8[0], sizeof(mmMC_XPB_CLG_CFG8)/sizeof(mmMC_XPB_CLG_CFG8[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG9", REG_MMIO, 0x8f2, &mmMC_XPB_CLG_CFG9[0], sizeof(mmMC_XPB_CLG_CFG9)/sizeof(mmMC_XPB_CLG_CFG9[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG10", REG_MMIO, 0x8f3, &mmMC_XPB_CLG_CFG10[0], sizeof(mmMC_XPB_CLG_CFG10)/sizeof(mmMC_XPB_CLG_CFG10[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG11", REG_MMIO, 0x8f4, &mmMC_XPB_CLG_CFG11[0], sizeof(mmMC_XPB_CLG_CFG11)/sizeof(mmMC_XPB_CLG_CFG11[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG12", REG_MMIO, 0x8f5, &mmMC_XPB_CLG_CFG12[0], sizeof(mmMC_XPB_CLG_CFG12)/sizeof(mmMC_XPB_CLG_CFG12[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG13", REG_MMIO, 0x8f6, &mmMC_XPB_CLG_CFG13[0], sizeof(mmMC_XPB_CLG_CFG13)/sizeof(mmMC_XPB_CLG_CFG13[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG14", REG_MMIO, 0x8f7, &mmMC_XPB_CLG_CFG14[0], sizeof(mmMC_XPB_CLG_CFG14)/sizeof(mmMC_XPB_CLG_CFG14[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG15", REG_MMIO, 0x8f8, &mmMC_XPB_CLG_CFG15[0], sizeof(mmMC_XPB_CLG_CFG15)/sizeof(mmMC_XPB_CLG_CFG15[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG16", REG_MMIO, 0x8f9, &mmMC_XPB_CLG_CFG16[0], sizeof(mmMC_XPB_CLG_CFG16)/sizeof(mmMC_XPB_CLG_CFG16[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG17", REG_MMIO, 0x8fa, &mmMC_XPB_CLG_CFG17[0], sizeof(mmMC_XPB_CLG_CFG17)/sizeof(mmMC_XPB_CLG_CFG17[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG18", REG_MMIO, 0x8fb, &mmMC_XPB_CLG_CFG18[0], sizeof(mmMC_XPB_CLG_CFG18)/sizeof(mmMC_XPB_CLG_CFG18[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG19", REG_MMIO, 0x8fc, &mmMC_XPB_CLG_CFG19[0], sizeof(mmMC_XPB_CLG_CFG19)/sizeof(mmMC_XPB_CLG_CFG19[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA", REG_MMIO, 0x8fd, &mmMC_XPB_CLG_EXTRA[0], sizeof(mmMC_XPB_CLG_EXTRA)/sizeof(mmMC_XPB_CLG_EXTRA[0]), 0, 0 },
+	{ "mmMC_XPB_LB_ADDR", REG_MMIO, 0x8fe, &mmMC_XPB_LB_ADDR[0], sizeof(mmMC_XPB_LB_ADDR)/sizeof(mmMC_XPB_LB_ADDR[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_HST", REG_MMIO, 0x8ff, &mmMC_XPB_UNC_THRESH_HST[0], sizeof(mmMC_XPB_UNC_THRESH_HST)/sizeof(mmMC_XPB_UNC_THRESH_HST[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT6", REG_SMC, 0x9, &ixMC_TSM_DEBUG_BCNT6[0], sizeof(ixMC_TSM_DEBUG_BCNT6)/sizeof(ixMC_TSM_DEBUG_BCNT6[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_9", REG_SMC, 0x9, &ixMC_IO_DEBUG_UP_9[0], sizeof(ixMC_IO_DEBUG_UP_9)/sizeof(ixMC_IO_DEBUG_UP_9[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_144", REG_SMC, 0x90, &ixMC_IO_DEBUG_UP_144[0], sizeof(ixMC_IO_DEBUG_UP_144)/sizeof(ixMC_IO_DEBUG_UP_144[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_SID", REG_MMIO, 0x900, &mmMC_XPB_UNC_THRESH_SID[0], sizeof(mmMC_XPB_UNC_THRESH_SID)/sizeof(mmMC_XPB_UNC_THRESH_SID[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_STS", REG_MMIO, 0x901, &mmMC_XPB_WCB_STS[0], sizeof(mmMC_XPB_WCB_STS)/sizeof(mmMC_XPB_WCB_STS[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_CFG", REG_MMIO, 0x902, &mmMC_XPB_WCB_CFG[0], sizeof(mmMC_XPB_WCB_CFG)/sizeof(mmMC_XPB_WCB_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_CFG", REG_MMIO, 0x903, &mmMC_XPB_P2P_BAR_CFG[0], sizeof(mmMC_XPB_P2P_BAR_CFG)/sizeof(mmMC_XPB_P2P_BAR_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR0", REG_MMIO, 0x904, &mmMC_XPB_P2P_BAR0[0], sizeof(mmMC_XPB_P2P_BAR0)/sizeof(mmMC_XPB_P2P_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR1", REG_MMIO, 0x905, &mmMC_XPB_P2P_BAR1[0], sizeof(mmMC_XPB_P2P_BAR1)/sizeof(mmMC_XPB_P2P_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR2", REG_MMIO, 0x906, &mmMC_XPB_P2P_BAR2[0], sizeof(mmMC_XPB_P2P_BAR2)/sizeof(mmMC_XPB_P2P_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR3", REG_MMIO, 0x907, &mmMC_XPB_P2P_BAR3[0], sizeof(mmMC_XPB_P2P_BAR3)/sizeof(mmMC_XPB_P2P_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR4", REG_MMIO, 0x908, &mmMC_XPB_P2P_BAR4[0], sizeof(mmMC_XPB_P2P_BAR4)/sizeof(mmMC_XPB_P2P_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR5", REG_MMIO, 0x909, &mmMC_XPB_P2P_BAR5[0], sizeof(mmMC_XPB_P2P_BAR5)/sizeof(mmMC_XPB_P2P_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR6", REG_MMIO, 0x90a, &mmMC_XPB_P2P_BAR6[0], sizeof(mmMC_XPB_P2P_BAR6)/sizeof(mmMC_XPB_P2P_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR7", REG_MMIO, 0x90b, &mmMC_XPB_P2P_BAR7[0], sizeof(mmMC_XPB_P2P_BAR7)/sizeof(mmMC_XPB_P2P_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_SETUP", REG_MMIO, 0x90c, &mmMC_XPB_P2P_BAR_SETUP[0], sizeof(mmMC_XPB_P2P_BAR_SETUP)/sizeof(mmMC_XPB_P2P_BAR_SETUP[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DEBUG", REG_MMIO, 0x90d, &mmMC_XPB_P2P_BAR_DEBUG[0], sizeof(mmMC_XPB_P2P_BAR_DEBUG)/sizeof(mmMC_XPB_P2P_BAR_DEBUG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_ABOVE", REG_MMIO, 0x90e, &mmMC_XPB_P2P_BAR_DELTA_ABOVE[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE)/sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_BELOW", REG_MMIO, 0x90f, &mmMC_XPB_P2P_BAR_DELTA_BELOW[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW)/sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_145", REG_SMC, 0x91, &ixMC_IO_DEBUG_UP_145[0], sizeof(ixMC_IO_DEBUG_UP_145)/sizeof(ixMC_IO_DEBUG_UP_145[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR0", REG_MMIO, 0x910, &mmMC_XPB_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_PEER_SYS_BAR0)/sizeof(mmMC_XPB_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR1", REG_MMIO, 0x911, &mmMC_XPB_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_PEER_SYS_BAR1)/sizeof(mmMC_XPB_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR2", REG_MMIO, 0x912, &mmMC_XPB_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_PEER_SYS_BAR2)/sizeof(mmMC_XPB_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR3", REG_MMIO, 0x913, &mmMC_XPB_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_PEER_SYS_BAR3)/sizeof(mmMC_XPB_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR4", REG_MMIO, 0x914, &mmMC_XPB_PEER_SYS_BAR4[0], sizeof(mmMC_XPB_PEER_SYS_BAR4)/sizeof(mmMC_XPB_PEER_SYS_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR5", REG_MMIO, 0x915, &mmMC_XPB_PEER_SYS_BAR5[0], sizeof(mmMC_XPB_PEER_SYS_BAR5)/sizeof(mmMC_XPB_PEER_SYS_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR6", REG_MMIO, 0x916, &mmMC_XPB_PEER_SYS_BAR6[0], sizeof(mmMC_XPB_PEER_SYS_BAR6)/sizeof(mmMC_XPB_PEER_SYS_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR7", REG_MMIO, 0x917, &mmMC_XPB_PEER_SYS_BAR7[0], sizeof(mmMC_XPB_PEER_SYS_BAR7)/sizeof(mmMC_XPB_PEER_SYS_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR8", REG_MMIO, 0x918, &mmMC_XPB_PEER_SYS_BAR8[0], sizeof(mmMC_XPB_PEER_SYS_BAR8)/sizeof(mmMC_XPB_PEER_SYS_BAR8[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR9", REG_MMIO, 0x919, &mmMC_XPB_PEER_SYS_BAR9[0], sizeof(mmMC_XPB_PEER_SYS_BAR9)/sizeof(mmMC_XPB_PEER_SYS_BAR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR0", REG_MMIO, 0x91a, &mmMC_XPB_XDMA_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR1", REG_MMIO, 0x91b, &mmMC_XPB_XDMA_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR2", REG_MMIO, 0x91c, &mmMC_XPB_XDMA_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR3", REG_MMIO, 0x91d, &mmMC_XPB_XDMA_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_CLK_GAT", REG_MMIO, 0x91e, &mmMC_XPB_CLK_GAT[0], sizeof(mmMC_XPB_CLK_GAT)/sizeof(mmMC_XPB_CLK_GAT[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG", REG_MMIO, 0x91f, &mmMC_XPB_INTF_CFG[0], sizeof(mmMC_XPB_INTF_CFG)/sizeof(mmMC_XPB_INTF_CFG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_146", REG_SMC, 0x92, &ixMC_IO_DEBUG_UP_146[0], sizeof(ixMC_IO_DEBUG_UP_146)/sizeof(ixMC_IO_DEBUG_UP_146[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_STS", REG_MMIO, 0x920, &mmMC_XPB_INTF_STS[0], sizeof(mmMC_XPB_INTF_STS)/sizeof(mmMC_XPB_INTF_STS[0]), 0, 0 },
+	{ "mmMC_XPB_PIPE_STS", REG_MMIO, 0x921, &mmMC_XPB_PIPE_STS[0], sizeof(mmMC_XPB_PIPE_STS)/sizeof(mmMC_XPB_PIPE_STS[0]), 0, 0 },
+	{ "mmMC_XPB_SUB_CTRL", REG_MMIO, 0x922, &mmMC_XPB_SUB_CTRL[0], sizeof(mmMC_XPB_SUB_CTRL)/sizeof(mmMC_XPB_SUB_CTRL[0]), 0, 0 },
+	{ "mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB", REG_MMIO, 0x923, &mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0], sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB)/sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0]), 0, 0 },
+	{ "mmMC_XPB_PERF_KNOBS", REG_MMIO, 0x924, &mmMC_XPB_PERF_KNOBS[0], sizeof(mmMC_XPB_PERF_KNOBS)/sizeof(mmMC_XPB_PERF_KNOBS[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY", REG_MMIO, 0x925, &mmMC_XPB_STICKY[0], sizeof(mmMC_XPB_STICKY)/sizeof(mmMC_XPB_STICKY[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY_W1C", REG_MMIO, 0x926, &mmMC_XPB_STICKY_W1C[0], sizeof(mmMC_XPB_STICKY_W1C)/sizeof(mmMC_XPB_STICKY_W1C[0]), 0, 0 },
+	{ "mmMC_XPB_MISC_CFG", REG_MMIO, 0x927, &mmMC_XPB_MISC_CFG[0], sizeof(mmMC_XPB_MISC_CFG)/sizeof(mmMC_XPB_MISC_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG20", REG_MMIO, 0x928, &mmMC_XPB_CLG_CFG20[0], sizeof(mmMC_XPB_CLG_CFG20)/sizeof(mmMC_XPB_CLG_CFG20[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG21", REG_MMIO, 0x929, &mmMC_XPB_CLG_CFG21[0], sizeof(mmMC_XPB_CLG_CFG21)/sizeof(mmMC_XPB_CLG_CFG21[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG22", REG_MMIO, 0x92a, &mmMC_XPB_CLG_CFG22[0], sizeof(mmMC_XPB_CLG_CFG22)/sizeof(mmMC_XPB_CLG_CFG22[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG23", REG_MMIO, 0x92b, &mmMC_XPB_CLG_CFG23[0], sizeof(mmMC_XPB_CLG_CFG23)/sizeof(mmMC_XPB_CLG_CFG23[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG24", REG_MMIO, 0x92c, &mmMC_XPB_CLG_CFG24[0], sizeof(mmMC_XPB_CLG_CFG24)/sizeof(mmMC_XPB_CLG_CFG24[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG25", REG_MMIO, 0x92d, &mmMC_XPB_CLG_CFG25[0], sizeof(mmMC_XPB_CLG_CFG25)/sizeof(mmMC_XPB_CLG_CFG25[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG26", REG_MMIO, 0x92e, &mmMC_XPB_CLG_CFG26[0], sizeof(mmMC_XPB_CLG_CFG26)/sizeof(mmMC_XPB_CLG_CFG26[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG27", REG_MMIO, 0x92f, &mmMC_XPB_CLG_CFG27[0], sizeof(mmMC_XPB_CLG_CFG27)/sizeof(mmMC_XPB_CLG_CFG27[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_147", REG_SMC, 0x93, &ixMC_IO_DEBUG_UP_147[0], sizeof(ixMC_IO_DEBUG_UP_147)/sizeof(ixMC_IO_DEBUG_UP_147[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG28", REG_MMIO, 0x930, &mmMC_XPB_CLG_CFG28[0], sizeof(mmMC_XPB_CLG_CFG28)/sizeof(mmMC_XPB_CLG_CFG28[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG29", REG_MMIO, 0x931, &mmMC_XPB_CLG_CFG29[0], sizeof(mmMC_XPB_CLG_CFG29)/sizeof(mmMC_XPB_CLG_CFG29[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG30", REG_MMIO, 0x932, &mmMC_XPB_CLG_CFG30[0], sizeof(mmMC_XPB_CLG_CFG30)/sizeof(mmMC_XPB_CLG_CFG30[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG31", REG_MMIO, 0x933, &mmMC_XPB_CLG_CFG31[0], sizeof(mmMC_XPB_CLG_CFG31)/sizeof(mmMC_XPB_CLG_CFG31[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG2", REG_MMIO, 0x934, &mmMC_XPB_INTF_CFG2[0], sizeof(mmMC_XPB_INTF_CFG2)/sizeof(mmMC_XPB_INTF_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA_RD", REG_MMIO, 0x935, &mmMC_XPB_CLG_EXTRA_RD[0], sizeof(mmMC_XPB_CLG_EXTRA_RD)/sizeof(mmMC_XPB_CLG_EXTRA_RD[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG32", REG_MMIO, 0x936, &mmMC_XPB_CLG_CFG32[0], sizeof(mmMC_XPB_CLG_CFG32)/sizeof(mmMC_XPB_CLG_CFG32[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG33", REG_MMIO, 0x937, &mmMC_XPB_CLG_CFG33[0], sizeof(mmMC_XPB_CLG_CFG33)/sizeof(mmMC_XPB_CLG_CFG33[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG34", REG_MMIO, 0x938, &mmMC_XPB_CLG_CFG34[0], sizeof(mmMC_XPB_CLG_CFG34)/sizeof(mmMC_XPB_CLG_CFG34[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG35", REG_MMIO, 0x939, &mmMC_XPB_CLG_CFG35[0], sizeof(mmMC_XPB_CLG_CFG35)/sizeof(mmMC_XPB_CLG_CFG35[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG36", REG_MMIO, 0x93a, &mmMC_XPB_CLG_CFG36[0], sizeof(mmMC_XPB_CLG_CFG36)/sizeof(mmMC_XPB_CLG_CFG36[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_148", REG_SMC, 0x94, &ixMC_IO_DEBUG_UP_148[0], sizeof(ixMC_IO_DEBUG_UP_148)/sizeof(ixMC_IO_DEBUG_UP_148[0]), 0, 0 },
+	{ "mmMC_RPB_CONF", REG_MMIO, 0x94d, &mmMC_RPB_CONF[0], sizeof(mmMC_RPB_CONF)/sizeof(mmMC_RPB_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_IF_CONF", REG_MMIO, 0x94e, &mmMC_RPB_IF_CONF[0], sizeof(mmMC_RPB_IF_CONF)/sizeof(mmMC_RPB_IF_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_DBG1", REG_MMIO, 0x94f, &mmMC_RPB_DBG1[0], sizeof(mmMC_RPB_DBG1)/sizeof(mmMC_RPB_DBG1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_149", REG_SMC, 0x95, &ixMC_IO_DEBUG_UP_149[0], sizeof(ixMC_IO_DEBUG_UP_149)/sizeof(ixMC_IO_DEBUG_UP_149[0]), 0, 0 },
+	{ "mmMC_RPB_EFF_CNTL", REG_MMIO, 0x950, &mmMC_RPB_EFF_CNTL[0], sizeof(mmMC_RPB_EFF_CNTL)/sizeof(mmMC_RPB_EFF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_ARB_CNTL", REG_MMIO, 0x951, &mmMC_RPB_ARB_CNTL[0], sizeof(mmMC_RPB_ARB_CNTL)/sizeof(mmMC_RPB_ARB_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_BIF_CNTL", REG_MMIO, 0x952, &mmMC_RPB_BIF_CNTL[0], sizeof(mmMC_RPB_BIF_CNTL)/sizeof(mmMC_RPB_BIF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_SWITCH_CNTL", REG_MMIO, 0x953, &mmMC_RPB_WR_SWITCH_CNTL[0], sizeof(mmMC_RPB_WR_SWITCH_CNTL)/sizeof(mmMC_RPB_WR_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_COMBINE_CNTL", REG_MMIO, 0x954, &mmMC_RPB_WR_COMBINE_CNTL[0], sizeof(mmMC_RPB_WR_COMBINE_CNTL)/sizeof(mmMC_RPB_WR_COMBINE_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_RD_SWITCH_CNTL", REG_MMIO, 0x955, &mmMC_RPB_RD_SWITCH_CNTL[0], sizeof(mmMC_RPB_RD_SWITCH_CNTL)/sizeof(mmMC_RPB_RD_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_WR", REG_MMIO, 0x956, &mmMC_RPB_CID_QUEUE_WR[0], sizeof(mmMC_RPB_CID_QUEUE_WR)/sizeof(mmMC_RPB_CID_QUEUE_WR[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_RD", REG_MMIO, 0x957, &mmMC_RPB_CID_QUEUE_RD[0], sizeof(mmMC_RPB_CID_QUEUE_RD)/sizeof(mmMC_RPB_CID_QUEUE_RD[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_CNTL", REG_MMIO, 0x958, &mmMC_RPB_PERF_COUNTER_CNTL[0], sizeof(mmMC_RPB_PERF_COUNTER_CNTL)/sizeof(mmMC_RPB_PERF_COUNTER_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_STATUS", REG_MMIO, 0x959, &mmMC_RPB_PERF_COUNTER_STATUS[0], sizeof(mmMC_RPB_PERF_COUNTER_STATUS)/sizeof(mmMC_RPB_PERF_COUNTER_STATUS[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX", REG_MMIO, 0x95a, &mmMC_RPB_CID_QUEUE_EX[0], sizeof(mmMC_RPB_CID_QUEUE_EX)/sizeof(mmMC_RPB_CID_QUEUE_EX[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX_DATA", REG_MMIO, 0x95b, &mmMC_RPB_CID_QUEUE_EX_DATA[0], sizeof(mmMC_RPB_CID_QUEUE_EX_DATA)/sizeof(mmMC_RPB_CID_QUEUE_EX_DATA[0]), 0, 0 },
+	{ "mmMC_RPB_TCI_CNTL", REG_MMIO, 0x95c, &mmMC_RPB_TCI_CNTL[0], sizeof(mmMC_RPB_TCI_CNTL)/sizeof(mmMC_RPB_TCI_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_TCI_CNTL2", REG_MMIO, 0x95d, &mmMC_RPB_TCI_CNTL2[0], sizeof(mmMC_RPB_TCI_CNTL2)/sizeof(mmMC_RPB_TCI_CNTL2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_150", REG_SMC, 0x96, &ixMC_IO_DEBUG_UP_150[0], sizeof(ixMC_IO_DEBUG_UP_150)/sizeof(ixMC_IO_DEBUG_UP_150[0]), 0, 0 },
+	{ "mmMC_CITF_XTRA_ENABLE", REG_MMIO, 0x96d, &mmMC_CITF_XTRA_ENABLE[0], sizeof(mmMC_CITF_XTRA_ENABLE)/sizeof(mmMC_CITF_XTRA_ENABLE[0]), 0, 0 },
+	{ "mmCC_MC_MAX_CHANNEL", REG_MMIO, 0x96e, &mmCC_MC_MAX_CHANNEL[0], sizeof(mmCC_MC_MAX_CHANNEL)/sizeof(mmCC_MC_MAX_CHANNEL[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG", REG_MMIO, 0x96f, &mmMC_CG_CONFIG[0], sizeof(mmMC_CG_CONFIG)/sizeof(mmMC_CG_CONFIG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_151", REG_SMC, 0x97, &ixMC_IO_DEBUG_UP_151[0], sizeof(ixMC_IO_DEBUG_UP_151)/sizeof(ixMC_IO_DEBUG_UP_151[0]), 0, 0 },
+	{ "mmMC_CITF_CNTL", REG_MMIO, 0x970, &mmMC_CITF_CNTL[0], sizeof(mmMC_CITF_CNTL)/sizeof(mmMC_CITF_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_VM", REG_MMIO, 0x971, &mmMC_CITF_CREDITS_VM[0], sizeof(mmMC_CITF_CREDITS_VM)/sizeof(mmMC_CITF_CREDITS_VM[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_RD", REG_MMIO, 0x972, &mmMC_CITF_CREDITS_ARB_RD[0], sizeof(mmMC_CITF_CREDITS_ARB_RD)/sizeof(mmMC_CITF_CREDITS_ARB_RD[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_WR", REG_MMIO, 0x973, &mmMC_CITF_CREDITS_ARB_WR[0], sizeof(mmMC_CITF_CREDITS_ARB_WR)/sizeof(mmMC_CITF_CREDITS_ARB_WR[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_CNTL", REG_MMIO, 0x974, &mmMC_CITF_DAGB_CNTL[0], sizeof(mmMC_CITF_DAGB_CNTL)/sizeof(mmMC_CITF_DAGB_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS", REG_MMIO, 0x975, &mmMC_CITF_INT_CREDITS[0], sizeof(mmMC_CITF_INT_CREDITS)/sizeof(mmMC_CITF_INT_CREDITS[0]), 0, 0 },
+	{ "mmMC_CITF_RET_MODE", REG_MMIO, 0x976, &mmMC_CITF_RET_MODE[0], sizeof(mmMC_CITF_RET_MODE)/sizeof(mmMC_CITF_RET_MODE[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_DLY", REG_MMIO, 0x977, &mmMC_CITF_DAGB_DLY[0], sizeof(mmMC_CITF_DAGB_DLY)/sizeof(mmMC_CITF_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_RD_GRP_EXT", REG_MMIO, 0x978, &mmMC_RD_GRP_EXT[0], sizeof(mmMC_RD_GRP_EXT)/sizeof(mmMC_RD_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_WR_GRP_EXT", REG_MMIO, 0x979, &mmMC_WR_GRP_EXT[0], sizeof(mmMC_WR_GRP_EXT)/sizeof(mmMC_WR_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_CITF_REMREQ", REG_MMIO, 0x97a, &mmMC_CITF_REMREQ[0], sizeof(mmMC_CITF_REMREQ)/sizeof(mmMC_CITF_REMREQ[0]), 0, 0 },
+	{ "mmMC_WR_TC0", REG_MMIO, 0x97b, &mmMC_WR_TC0[0], sizeof(mmMC_WR_TC0)/sizeof(mmMC_WR_TC0[0]), 0, 0 },
+	{ "mmMC_WR_TC1", REG_MMIO, 0x97c, &mmMC_WR_TC1[0], sizeof(mmMC_WR_TC1)/sizeof(mmMC_WR_TC1[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS_WR", REG_MMIO, 0x97d, &mmMC_CITF_INT_CREDITS_WR[0], sizeof(mmMC_CITF_INT_CREDITS_WR)/sizeof(mmMC_CITF_INT_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_RD2", REG_MMIO, 0x97e, &mmMC_CITF_CREDITS_ARB_RD2[0], sizeof(mmMC_CITF_CREDITS_ARB_RD2)/sizeof(mmMC_CITF_CREDITS_ARB_RD2[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_RD_CNTL", REG_MMIO, 0x97f, &mmMC_CITF_WTM_RD_CNTL[0], sizeof(mmMC_CITF_WTM_RD_CNTL)/sizeof(mmMC_CITF_WTM_RD_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_152", REG_SMC, 0x98, &ixMC_IO_DEBUG_UP_152[0], sizeof(ixMC_IO_DEBUG_UP_152)/sizeof(ixMC_IO_DEBUG_UP_152[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_WR_CNTL", REG_MMIO, 0x980, &mmMC_CITF_WTM_WR_CNTL[0], sizeof(mmMC_CITF_WTM_WR_CNTL)/sizeof(mmMC_CITF_WTM_WR_CNTL[0]), 0, 0 },
+	{ "mmMC_RD_CB", REG_MMIO, 0x981, &mmMC_RD_CB[0], sizeof(mmMC_RD_CB)/sizeof(mmMC_RD_CB[0]), 0, 0 },
+	{ "mmMC_RD_DB", REG_MMIO, 0x982, &mmMC_RD_DB[0], sizeof(mmMC_RD_DB)/sizeof(mmMC_RD_DB[0]), 0, 0 },
+	{ "mmMC_RD_TC0", REG_MMIO, 0x983, &mmMC_RD_TC0[0], sizeof(mmMC_RD_TC0)/sizeof(mmMC_RD_TC0[0]), 0, 0 },
+	{ "mmMC_RD_TC1", REG_MMIO, 0x984, &mmMC_RD_TC1[0], sizeof(mmMC_RD_TC1)/sizeof(mmMC_RD_TC1[0]), 0, 0 },
+	{ "mmMC_RD_HUB", REG_MMIO, 0x985, &mmMC_RD_HUB[0], sizeof(mmMC_RD_HUB)/sizeof(mmMC_RD_HUB[0]), 0, 0 },
+	{ "mmMC_WR_CB", REG_MMIO, 0x986, &mmMC_WR_CB[0], sizeof(mmMC_WR_CB)/sizeof(mmMC_WR_CB[0]), 0, 0 },
+	{ "mmMC_WR_DB", REG_MMIO, 0x987, &mmMC_WR_DB[0], sizeof(mmMC_WR_DB)/sizeof(mmMC_WR_DB[0]), 0, 0 },
+	{ "mmMC_WR_HUB", REG_MMIO, 0x988, &mmMC_WR_HUB[0], sizeof(mmMC_WR_HUB)/sizeof(mmMC_WR_HUB[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_XBAR", REG_MMIO, 0x989, &mmMC_CITF_CREDITS_XBAR[0], sizeof(mmMC_CITF_CREDITS_XBAR)/sizeof(mmMC_CITF_CREDITS_XBAR[0]), 0, 0 },
+	{ "mmMC_RD_GRP_LCL", REG_MMIO, 0x98a, &mmMC_RD_GRP_LCL[0], sizeof(mmMC_RD_GRP_LCL)/sizeof(mmMC_RD_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_WR_GRP_LCL", REG_MMIO, 0x98b, &mmMC_WR_GRP_LCL[0], sizeof(mmMC_WR_GRP_LCL)/sizeof(mmMC_WR_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_CNTL2", REG_MMIO, 0x98e, &mmMC_CITF_PERF_MON_CNTL2[0], sizeof(mmMC_CITF_PERF_MON_CNTL2)/sizeof(mmMC_CITF_PERF_MON_CNTL2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_153", REG_SMC, 0x99, &ixMC_IO_DEBUG_UP_153[0], sizeof(ixMC_IO_DEBUG_UP_153)/sizeof(ixMC_IO_DEBUG_UP_153[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_RSLT2", REG_MMIO, 0x991, &mmMC_CITF_PERF_MON_RSLT2[0], sizeof(mmMC_CITF_PERF_MON_RSLT2)/sizeof(mmMC_CITF_PERF_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_RD_CG", REG_MMIO, 0x992, &mmMC_CITF_MISC_RD_CG[0], sizeof(mmMC_CITF_MISC_RD_CG)/sizeof(mmMC_CITF_MISC_RD_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_WR_CG", REG_MMIO, 0x993, &mmMC_CITF_MISC_WR_CG[0], sizeof(mmMC_CITF_MISC_WR_CG)/sizeof(mmMC_CITF_MISC_WR_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_VM_CG", REG_MMIO, 0x994, &mmMC_CITF_MISC_VM_CG[0], sizeof(mmMC_CITF_MISC_VM_CG)/sizeof(mmMC_CITF_MISC_VM_CG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_DEBUG", REG_MMIO, 0x998, &mmMC_VM_MD_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_DEBUG", REG_MMIO, 0x999, &mmMC_VM_MD_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB1_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_DEBUG", REG_MMIO, 0x99a, &mmMC_VM_MD_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_STATUS", REG_MMIO, 0x99b, &mmMC_VM_MD_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB0_STATUS)/sizeof(mmMC_VM_MD_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_STATUS", REG_MMIO, 0x99c, &mmMC_VM_MD_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB1_STATUS)/sizeof(mmMC_VM_MD_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_STATUS", REG_MMIO, 0x99d, &mmMC_VM_MD_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB2_STATUS)/sizeof(mmMC_VM_MD_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_154", REG_SMC, 0x9a, &ixMC_IO_DEBUG_UP_154[0], sizeof(ixMC_IO_DEBUG_UP_154)/sizeof(ixMC_IO_DEBUG_UP_154[0]), 0, 0 },
+	{ "mmMC_VM_MD_L2ARBITER_L2_CREDITS", REG_MMIO, 0x9a4, &mmMC_VM_MD_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_DEBUG", REG_MMIO, 0x9a7, &mmMC_VM_MD_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_STATUS", REG_MMIO, 0x9a8, &mmMC_VM_MD_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB3_STATUS)/sizeof(mmMC_VM_MD_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_155", REG_SMC, 0x9b, &ixMC_IO_DEBUG_UP_155[0], sizeof(ixMC_IO_DEBUG_UP_155)/sizeof(ixMC_IO_DEBUG_UP_155[0]), 0, 0 },
+	{ "mmMC_ARB_ATOMIC", REG_MMIO, 0x9be, &mmMC_ARB_ATOMIC[0], sizeof(mmMC_ARB_ATOMIC)/sizeof(mmMC_ARB_ATOMIC[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_CNTL", REG_MMIO, 0x9bf, &mmMC_ARB_AGE_CNTL[0], sizeof(mmMC_ARB_AGE_CNTL)/sizeof(mmMC_ARB_AGE_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_156", REG_SMC, 0x9c, &ixMC_IO_DEBUG_UP_156[0], sizeof(ixMC_IO_DEBUG_UP_156)/sizeof(ixMC_IO_DEBUG_UP_156[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS2", REG_MMIO, 0x9c0, &mmMC_ARB_RET_CREDITS2[0], sizeof(mmMC_ARB_RET_CREDITS2)/sizeof(mmMC_ARB_RET_CREDITS2[0]), 0, 0 },
+	{ "mmMC_ARB_FED_CNTL", REG_MMIO, 0x9c1, &mmMC_ARB_FED_CNTL[0], sizeof(mmMC_ARB_FED_CNTL)/sizeof(mmMC_ARB_FED_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_STATUS", REG_MMIO, 0x9c2, &mmMC_ARB_GECC2_STATUS[0], sizeof(mmMC_ARB_GECC2_STATUS)/sizeof(mmMC_ARB_GECC2_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_MISC", REG_MMIO, 0x9c3, &mmMC_ARB_GECC2_MISC[0], sizeof(mmMC_ARB_GECC2_MISC)/sizeof(mmMC_ARB_GECC2_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG", REG_MMIO, 0x9c4, &mmMC_ARB_GECC2_DEBUG[0], sizeof(mmMC_ARB_GECC2_DEBUG)/sizeof(mmMC_ARB_GECC2_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG2", REG_MMIO, 0x9c5, &mmMC_ARB_GECC2_DEBUG2[0], sizeof(mmMC_ARB_GECC2_DEBUG2)/sizeof(mmMC_ARB_GECC2_DEBUG2[0]), 0, 0 },
+	{ "mmMC_ARB_PERF_CID", REG_MMIO, 0x9c6, &mmMC_ARB_PERF_CID[0], sizeof(mmMC_ARB_PERF_CID)/sizeof(mmMC_ARB_PERF_CID[0]), 0, 0 },
+	{ "mmMC_ARB_SNOOP", REG_MMIO, 0x9c7, &mmMC_ARB_SNOOP[0], sizeof(mmMC_ARB_SNOOP)/sizeof(mmMC_ARB_SNOOP[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB", REG_MMIO, 0x9c8, &mmMC_ARB_GRUB[0], sizeof(mmMC_ARB_GRUB)/sizeof(mmMC_ARB_GRUB[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2", REG_MMIO, 0x9c9, &mmMC_ARB_GECC2[0], sizeof(mmMC_ARB_GECC2)/sizeof(mmMC_ARB_GECC2[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_CLI", REG_MMIO, 0x9ca, &mmMC_ARB_GECC2_CLI[0], sizeof(mmMC_ARB_GECC2_CLI)/sizeof(mmMC_ARB_GECC2_CLI[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_SWIZ0", REG_MMIO, 0x9cb, &mmMC_ARB_ADDR_SWIZ0[0], sizeof(mmMC_ARB_ADDR_SWIZ0)/sizeof(mmMC_ARB_ADDR_SWIZ0[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_SWIZ1", REG_MMIO, 0x9cc, &mmMC_ARB_ADDR_SWIZ1[0], sizeof(mmMC_ARB_ADDR_SWIZ1)/sizeof(mmMC_ARB_ADDR_SWIZ1[0]), 0, 0 },
+	{ "mmMC_ARB_MISC3", REG_MMIO, 0x9cd, &mmMC_ARB_MISC3[0], sizeof(mmMC_ARB_MISC3)/sizeof(mmMC_ARB_MISC3[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PROMOTE", REG_MMIO, 0x9ce, &mmMC_ARB_GRUB_PROMOTE[0], sizeof(mmMC_ARB_GRUB_PROMOTE)/sizeof(mmMC_ARB_GRUB_PROMOTE[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DATA", REG_MMIO, 0x9cf, &mmMC_ARB_RTT_DATA[0], sizeof(mmMC_ARB_RTT_DATA)/sizeof(mmMC_ARB_RTT_DATA[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_157", REG_SMC, 0x9d, &ixMC_IO_DEBUG_UP_157[0], sizeof(ixMC_IO_DEBUG_UP_157)/sizeof(ixMC_IO_DEBUG_UP_157[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL0", REG_MMIO, 0x9d0, &mmMC_ARB_RTT_CNTL0[0], sizeof(mmMC_ARB_RTT_CNTL0)/sizeof(mmMC_ARB_RTT_CNTL0[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL1", REG_MMIO, 0x9d1, &mmMC_ARB_RTT_CNTL1[0], sizeof(mmMC_ARB_RTT_CNTL1)/sizeof(mmMC_ARB_RTT_CNTL1[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL2", REG_MMIO, 0x9d2, &mmMC_ARB_RTT_CNTL2[0], sizeof(mmMC_ARB_RTT_CNTL2)/sizeof(mmMC_ARB_RTT_CNTL2[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DEBUG", REG_MMIO, 0x9d3, &mmMC_ARB_RTT_DEBUG[0], sizeof(mmMC_ARB_RTT_DEBUG)/sizeof(mmMC_ARB_RTT_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_CAC_CNTL", REG_MMIO, 0x9d4, &mmMC_ARB_CAC_CNTL[0], sizeof(mmMC_ARB_CAC_CNTL)/sizeof(mmMC_ARB_CAC_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_MISC2", REG_MMIO, 0x9d5, &mmMC_ARB_MISC2[0], sizeof(mmMC_ARB_MISC2)/sizeof(mmMC_ARB_MISC2[0]), 0, 0 },
+	{ "mmMC_ARB_MISC", REG_MMIO, 0x9d6, &mmMC_ARB_MISC[0], sizeof(mmMC_ARB_MISC)/sizeof(mmMC_ARB_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_BANKMAP", REG_MMIO, 0x9d7, &mmMC_ARB_BANKMAP[0], sizeof(mmMC_ARB_BANKMAP)/sizeof(mmMC_ARB_BANKMAP[0]), 0, 0 },
+	{ "mmMC_ARB_RAMCFG", REG_MMIO, 0x9d8, &mmMC_ARB_RAMCFG[0], sizeof(mmMC_ARB_RAMCFG)/sizeof(mmMC_ARB_RAMCFG[0]), 0, 0 },
+	{ "mmMC_ARB_POP", REG_MMIO, 0x9d9, &mmMC_ARB_POP[0], sizeof(mmMC_ARB_POP)/sizeof(mmMC_ARB_POP[0]), 0, 0 },
+	{ "mmMC_ARB_MINCLKS", REG_MMIO, 0x9da, &mmMC_ARB_MINCLKS[0], sizeof(mmMC_ARB_MINCLKS)/sizeof(mmMC_ARB_MINCLKS[0]), 0, 0 },
+	{ "mmMC_ARB_SQM_CNTL", REG_MMIO, 0x9db, &mmMC_ARB_SQM_CNTL[0], sizeof(mmMC_ARB_SQM_CNTL)/sizeof(mmMC_ARB_SQM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_HASH", REG_MMIO, 0x9dc, &mmMC_ARB_ADDR_HASH[0], sizeof(mmMC_ARB_ADDR_HASH)/sizeof(mmMC_ARB_ADDR_HASH[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING", REG_MMIO, 0x9dd, &mmMC_ARB_DRAM_TIMING[0], sizeof(mmMC_ARB_DRAM_TIMING)/sizeof(mmMC_ARB_DRAM_TIMING[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2", REG_MMIO, 0x9de, &mmMC_ARB_DRAM_TIMING2[0], sizeof(mmMC_ARB_DRAM_TIMING2)/sizeof(mmMC_ARB_DRAM_TIMING2[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_RD", REG_MMIO, 0x9df, &mmMC_ARB_WTM_CNTL_RD[0], sizeof(mmMC_ARB_WTM_CNTL_RD)/sizeof(mmMC_ARB_WTM_CNTL_RD[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_158", REG_SMC, 0x9e, &ixMC_IO_DEBUG_UP_158[0], sizeof(ixMC_IO_DEBUG_UP_158)/sizeof(ixMC_IO_DEBUG_UP_158[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_WR", REG_MMIO, 0x9e0, &mmMC_ARB_WTM_CNTL_WR[0], sizeof(mmMC_ARB_WTM_CNTL_WR)/sizeof(mmMC_ARB_WTM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_RD", REG_MMIO, 0x9e1, &mmMC_ARB_WTM_GRPWT_RD[0], sizeof(mmMC_ARB_WTM_GRPWT_RD)/sizeof(mmMC_ARB_WTM_GRPWT_RD[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_WR", REG_MMIO, 0x9e2, &mmMC_ARB_WTM_GRPWT_WR[0], sizeof(mmMC_ARB_WTM_GRPWT_WR)/sizeof(mmMC_ARB_WTM_GRPWT_WR[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_RD", REG_MMIO, 0x9e3, &mmMC_ARB_TM_CNTL_RD[0], sizeof(mmMC_ARB_TM_CNTL_RD)/sizeof(mmMC_ARB_TM_CNTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_WR", REG_MMIO, 0x9e4, &mmMC_ARB_TM_CNTL_WR[0], sizeof(mmMC_ARB_TM_CNTL_WR)/sizeof(mmMC_ARB_TM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_RD", REG_MMIO, 0x9e5, &mmMC_ARB_LAZY0_RD[0], sizeof(mmMC_ARB_LAZY0_RD)/sizeof(mmMC_ARB_LAZY0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_WR", REG_MMIO, 0x9e6, &mmMC_ARB_LAZY0_WR[0], sizeof(mmMC_ARB_LAZY0_WR)/sizeof(mmMC_ARB_LAZY0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_RD", REG_MMIO, 0x9e7, &mmMC_ARB_LAZY1_RD[0], sizeof(mmMC_ARB_LAZY1_RD)/sizeof(mmMC_ARB_LAZY1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_WR", REG_MMIO, 0x9e8, &mmMC_ARB_LAZY1_WR[0], sizeof(mmMC_ARB_LAZY1_WR)/sizeof(mmMC_ARB_LAZY1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_RD", REG_MMIO, 0x9e9, &mmMC_ARB_AGE_RD[0], sizeof(mmMC_ARB_AGE_RD)/sizeof(mmMC_ARB_AGE_RD[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_WR", REG_MMIO, 0x9ea, &mmMC_ARB_AGE_WR[0], sizeof(mmMC_ARB_AGE_WR)/sizeof(mmMC_ARB_AGE_WR[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_CNTL", REG_MMIO, 0x9eb, &mmMC_ARB_RFSH_CNTL[0], sizeof(mmMC_ARB_RFSH_CNTL)/sizeof(mmMC_ARB_RFSH_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_RATE", REG_MMIO, 0x9ec, &mmMC_ARB_RFSH_RATE[0], sizeof(mmMC_ARB_RFSH_RATE)/sizeof(mmMC_ARB_RFSH_RATE[0]), 0, 0 },
+	{ "mmMC_ARB_PM_CNTL", REG_MMIO, 0x9ed, &mmMC_ARB_PM_CNTL[0], sizeof(mmMC_ARB_PM_CNTL)/sizeof(mmMC_ARB_PM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_RD_CNTL", REG_MMIO, 0x9ee, &mmMC_ARB_GDEC_RD_CNTL[0], sizeof(mmMC_ARB_GDEC_RD_CNTL)/sizeof(mmMC_ARB_GDEC_RD_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_WR_CNTL", REG_MMIO, 0x9ef, &mmMC_ARB_GDEC_WR_CNTL[0], sizeof(mmMC_ARB_GDEC_WR_CNTL)/sizeof(mmMC_ARB_GDEC_WR_CNTL[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_159", REG_SMC, 0x9f, &ixMC_IO_DEBUG_UP_159[0], sizeof(ixMC_IO_DEBUG_UP_159)/sizeof(ixMC_IO_DEBUG_UP_159[0]), 0, 0 },
+	{ "mmMC_ARB_LM_RD", REG_MMIO, 0x9f0, &mmMC_ARB_LM_RD[0], sizeof(mmMC_ARB_LM_RD)/sizeof(mmMC_ARB_LM_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LM_WR", REG_MMIO, 0x9f1, &mmMC_ARB_LM_WR[0], sizeof(mmMC_ARB_LM_WR)/sizeof(mmMC_ARB_LM_WR[0]), 0, 0 },
+	{ "mmMC_ARB_REMREQ", REG_MMIO, 0x9f2, &mmMC_ARB_REMREQ[0], sizeof(mmMC_ARB_REMREQ)/sizeof(mmMC_ARB_REMREQ[0]), 0, 0 },
+	{ "mmMC_ARB_REPLAY", REG_MMIO, 0x9f3, &mmMC_ARB_REPLAY[0], sizeof(mmMC_ARB_REPLAY)/sizeof(mmMC_ARB_REPLAY[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_RD", REG_MMIO, 0x9f4, &mmMC_ARB_RET_CREDITS_RD[0], sizeof(mmMC_ARB_RET_CREDITS_RD)/sizeof(mmMC_ARB_RET_CREDITS_RD[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_WR", REG_MMIO, 0x9f5, &mmMC_ARB_RET_CREDITS_WR[0], sizeof(mmMC_ARB_RET_CREDITS_WR)/sizeof(mmMC_ARB_RET_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_CID", REG_MMIO, 0x9f6, &mmMC_ARB_MAX_LAT_CID[0], sizeof(mmMC_ARB_MAX_LAT_CID)/sizeof(mmMC_ARB_MAX_LAT_CID[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_RSLT0", REG_MMIO, 0x9f7, &mmMC_ARB_MAX_LAT_RSLT0[0], sizeof(mmMC_ARB_MAX_LAT_RSLT0)/sizeof(mmMC_ARB_MAX_LAT_RSLT0[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_RSLT1", REG_MMIO, 0x9f8, &mmMC_ARB_MAX_LAT_RSLT1[0], sizeof(mmMC_ARB_MAX_LAT_RSLT1)/sizeof(mmMC_ARB_MAX_LAT_RSLT1[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_REALTIME_RD", REG_MMIO, 0x9f9, &mmMC_ARB_GRUB_REALTIME_RD[0], sizeof(mmMC_ARB_GRUB_REALTIME_RD)/sizeof(mmMC_ARB_GRUB_REALTIME_RD[0]), 0, 0 },
+	{ "mmMC_ARB_CG", REG_MMIO, 0x9fa, &mmMC_ARB_CG[0], sizeof(mmMC_ARB_CG)/sizeof(mmMC_ARB_CG[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_REALTIME_WR", REG_MMIO, 0x9fb, &mmMC_ARB_GRUB_REALTIME_WR[0], sizeof(mmMC_ARB_GRUB_REALTIME_WR)/sizeof(mmMC_ARB_GRUB_REALTIME_WR[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING_1", REG_MMIO, 0x9fc, &mmMC_ARB_DRAM_TIMING_1[0], sizeof(mmMC_ARB_DRAM_TIMING_1)/sizeof(mmMC_ARB_DRAM_TIMING_1[0]), 0, 0 },
+	{ "mmMC_ARB_BUSY_STATUS", REG_MMIO, 0x9fd, &mmMC_ARB_BUSY_STATUS[0], sizeof(mmMC_ARB_BUSY_STATUS)/sizeof(mmMC_ARB_BUSY_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2_1", REG_MMIO, 0x9ff, &mmMC_ARB_DRAM_TIMING2_1[0], sizeof(mmMC_ARB_DRAM_TIMING2_1)/sizeof(mmMC_ARB_DRAM_TIMING2_1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT7", REG_SMC, 0xa, &ixMC_TSM_DEBUG_BCNT7[0], sizeof(ixMC_TSM_DEBUG_BCNT7)/sizeof(ixMC_TSM_DEBUG_BCNT7[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_10", REG_SMC, 0xa, &ixMC_IO_DEBUG_UP_10[0], sizeof(ixMC_IO_DEBUG_UP_10)/sizeof(ixMC_IO_DEBUG_UP_10[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_MISC_D0", REG_SMC, 0xa0, &ixMC_IO_DEBUG_DQB0L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D0[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB2", REG_MMIO, 0xa01, &mmMC_ARB_GRUB2[0], sizeof(mmMC_ARB_GRUB2)/sizeof(mmMC_ARB_GRUB2[0]), 0, 0 },
+	{ "mmMC_ARB_BURST_TIME", REG_MMIO, 0xa02, &mmMC_ARB_BURST_TIME[0], sizeof(mmMC_ARB_BURST_TIME)/sizeof(mmMC_ARB_BURST_TIME[0]), 0, 0 },
+	{ "mmMC_BIST_CNTL", REG_MMIO, 0xa05, &mmMC_BIST_CNTL[0], sizeof(mmMC_BIST_CNTL)/sizeof(mmMC_BIST_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_AUTO_CNTL", REG_MMIO, 0xa06, &mmMC_BIST_AUTO_CNTL[0], sizeof(mmMC_BIST_AUTO_CNTL)/sizeof(mmMC_BIST_AUTO_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_DIR_CNTL", REG_MMIO, 0xa07, &mmMC_BIST_DIR_CNTL[0], sizeof(mmMC_BIST_DIR_CNTL)/sizeof(mmMC_BIST_DIR_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_SADDR", REG_MMIO, 0xa08, &mmMC_BIST_SADDR[0], sizeof(mmMC_BIST_SADDR)/sizeof(mmMC_BIST_SADDR[0]), 0, 0 },
+	{ "mmMC_BIST_EADDR", REG_MMIO, 0xa09, &mmMC_BIST_EADDR[0], sizeof(mmMC_BIST_EADDR)/sizeof(mmMC_BIST_EADDR[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD0", REG_MMIO, 0xa0a, &mmMC_BIST_DATA_WORD0[0], sizeof(mmMC_BIST_DATA_WORD0)/sizeof(mmMC_BIST_DATA_WORD0[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD1", REG_MMIO, 0xa0b, &mmMC_BIST_DATA_WORD1[0], sizeof(mmMC_BIST_DATA_WORD1)/sizeof(mmMC_BIST_DATA_WORD1[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD2", REG_MMIO, 0xa0c, &mmMC_BIST_DATA_WORD2[0], sizeof(mmMC_BIST_DATA_WORD2)/sizeof(mmMC_BIST_DATA_WORD2[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD3", REG_MMIO, 0xa0d, &mmMC_BIST_DATA_WORD3[0], sizeof(mmMC_BIST_DATA_WORD3)/sizeof(mmMC_BIST_DATA_WORD3[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD4", REG_MMIO, 0xa0e, &mmMC_BIST_DATA_WORD4[0], sizeof(mmMC_BIST_DATA_WORD4)/sizeof(mmMC_BIST_DATA_WORD4[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD5", REG_MMIO, 0xa0f, &mmMC_BIST_DATA_WORD5[0], sizeof(mmMC_BIST_DATA_WORD5)/sizeof(mmMC_BIST_DATA_WORD5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_MISC_D0", REG_SMC, 0xa1, &ixMC_IO_DEBUG_DQB0H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D0[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD6", REG_MMIO, 0xa10, &mmMC_BIST_DATA_WORD6[0], sizeof(mmMC_BIST_DATA_WORD6)/sizeof(mmMC_BIST_DATA_WORD6[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_WORD7", REG_MMIO, 0xa11, &mmMC_BIST_DATA_WORD7[0], sizeof(mmMC_BIST_DATA_WORD7)/sizeof(mmMC_BIST_DATA_WORD7[0]), 0, 0 },
+	{ "mmMC_BIST_DATA_MASK", REG_MMIO, 0xa12, &mmMC_BIST_DATA_MASK[0], sizeof(mmMC_BIST_DATA_MASK)/sizeof(mmMC_BIST_DATA_MASK[0]), 0, 0 },
+	{ "mmMC_BIST_MISMATCH_ADDR", REG_MMIO, 0xa13, &mmMC_BIST_MISMATCH_ADDR[0], sizeof(mmMC_BIST_MISMATCH_ADDR)/sizeof(mmMC_BIST_MISMATCH_ADDR[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD0", REG_MMIO, 0xa14, &mmMC_BIST_RDATA_WORD0[0], sizeof(mmMC_BIST_RDATA_WORD0)/sizeof(mmMC_BIST_RDATA_WORD0[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD1", REG_MMIO, 0xa15, &mmMC_BIST_RDATA_WORD1[0], sizeof(mmMC_BIST_RDATA_WORD1)/sizeof(mmMC_BIST_RDATA_WORD1[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD2", REG_MMIO, 0xa16, &mmMC_BIST_RDATA_WORD2[0], sizeof(mmMC_BIST_RDATA_WORD2)/sizeof(mmMC_BIST_RDATA_WORD2[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD3", REG_MMIO, 0xa17, &mmMC_BIST_RDATA_WORD3[0], sizeof(mmMC_BIST_RDATA_WORD3)/sizeof(mmMC_BIST_RDATA_WORD3[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD4", REG_MMIO, 0xa18, &mmMC_BIST_RDATA_WORD4[0], sizeof(mmMC_BIST_RDATA_WORD4)/sizeof(mmMC_BIST_RDATA_WORD4[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD5", REG_MMIO, 0xa19, &mmMC_BIST_RDATA_WORD5[0], sizeof(mmMC_BIST_RDATA_WORD5)/sizeof(mmMC_BIST_RDATA_WORD5[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD6", REG_MMIO, 0xa1a, &mmMC_BIST_RDATA_WORD6[0], sizeof(mmMC_BIST_RDATA_WORD6)/sizeof(mmMC_BIST_RDATA_WORD6[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_WORD7", REG_MMIO, 0xa1b, &mmMC_BIST_RDATA_WORD7[0], sizeof(mmMC_BIST_RDATA_WORD7)/sizeof(mmMC_BIST_RDATA_WORD7[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_MASK", REG_MMIO, 0xa1c, &mmMC_BIST_RDATA_MASK[0], sizeof(mmMC_BIST_RDATA_MASK)/sizeof(mmMC_BIST_RDATA_MASK[0]), 0, 0 },
+	{ "mmMC_BIST_RDATA_EDC", REG_MMIO, 0xa1d, &mmMC_BIST_RDATA_EDC[0], sizeof(mmMC_BIST_RDATA_EDC)/sizeof(mmMC_BIST_RDATA_EDC[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_0_S", REG_MMIO, 0xa1e, &mmMC_SEQ_RESERVE_0_S[0], sizeof(mmMC_SEQ_RESERVE_0_S)/sizeof(mmMC_SEQ_RESERVE_0_S[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_1_S", REG_MMIO, 0xa1f, &mmMC_SEQ_RESERVE_1_S[0], sizeof(mmMC_SEQ_RESERVE_1_S)/sizeof(mmMC_SEQ_RESERVE_1_S[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_MISC_D0", REG_SMC, 0xa2, &ixMC_IO_DEBUG_DQB1L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_STATUS_S", REG_MMIO, 0xa20, &mmMC_SEQ_STATUS_S[0], sizeof(mmMC_SEQ_STATUS_S)/sizeof(mmMC_SEQ_STATUS_S[0]), 0, 0 },
+	{ "mmMC_CG_DATAPORT", REG_MMIO, 0xa21, &mmMC_CG_DATAPORT[0], sizeof(mmMC_CG_DATAPORT)/sizeof(mmMC_CG_DATAPORT[0]), 0, 0 },
+	{ "mmMC_SEQ_MPLL_OVERRIDE", REG_MMIO, 0xa22, &mmMC_SEQ_MPLL_OVERRIDE[0], sizeof(mmMC_SEQ_MPLL_OVERRIDE)/sizeof(mmMC_SEQ_MPLL_OVERRIDE[0]), 0, 0 },
+	{ "mmMC_SEQ_CNTL", REG_MMIO, 0xa25, &mmMC_SEQ_CNTL[0], sizeof(mmMC_SEQ_CNTL)/sizeof(mmMC_SEQ_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM", REG_MMIO, 0xa26, &mmMC_SEQ_DRAM[0], sizeof(mmMC_SEQ_DRAM)/sizeof(mmMC_SEQ_DRAM[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM_2", REG_MMIO, 0xa27, &mmMC_SEQ_DRAM_2[0], sizeof(mmMC_SEQ_DRAM_2)/sizeof(mmMC_SEQ_DRAM_2[0]), 0, 0 },
+	{ "mmMC_SEQ_RAS_TIMING", REG_MMIO, 0xa28, &mmMC_SEQ_RAS_TIMING[0], sizeof(mmMC_SEQ_RAS_TIMING)/sizeof(mmMC_SEQ_RAS_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_CAS_TIMING", REG_MMIO, 0xa29, &mmMC_SEQ_CAS_TIMING[0], sizeof(mmMC_SEQ_CAS_TIMING)/sizeof(mmMC_SEQ_CAS_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING", REG_MMIO, 0xa2a, &mmMC_SEQ_MISC_TIMING[0], sizeof(mmMC_SEQ_MISC_TIMING)/sizeof(mmMC_SEQ_MISC_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING2", REG_MMIO, 0xa2b, &mmMC_SEQ_MISC_TIMING2[0], sizeof(mmMC_SEQ_MISC_TIMING2)/sizeof(mmMC_SEQ_MISC_TIMING2[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_TIMING", REG_MMIO, 0xa2c, &mmMC_SEQ_PMG_TIMING[0], sizeof(mmMC_SEQ_PMG_TIMING)/sizeof(mmMC_SEQ_PMG_TIMING[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D0", REG_MMIO, 0xa2d, &mmMC_SEQ_RD_CTL_D0[0], sizeof(mmMC_SEQ_RD_CTL_D0)/sizeof(mmMC_SEQ_RD_CTL_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D1", REG_MMIO, 0xa2e, &mmMC_SEQ_RD_CTL_D1[0], sizeof(mmMC_SEQ_RD_CTL_D1)/sizeof(mmMC_SEQ_RD_CTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D0", REG_MMIO, 0xa2f, &mmMC_SEQ_WR_CTL_D0[0], sizeof(mmMC_SEQ_WR_CTL_D0)/sizeof(mmMC_SEQ_WR_CTL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_MISC_D0", REG_SMC, 0xa3, &ixMC_IO_DEBUG_DQB1H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D1", REG_MMIO, 0xa30, &mmMC_SEQ_WR_CTL_D1[0], sizeof(mmMC_SEQ_WR_CTL_D1)/sizeof(mmMC_SEQ_WR_CTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_CMD", REG_MMIO, 0xa31, &mmMC_SEQ_CMD[0], sizeof(mmMC_SEQ_CMD)/sizeof(mmMC_SEQ_CMD[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_CNTL", REG_MMIO, 0xa32, &mmMC_SEQ_SUP_CNTL[0], sizeof(mmMC_SEQ_SUP_CNTL)/sizeof(mmMC_SEQ_SUP_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_PGM", REG_MMIO, 0xa33, &mmMC_SEQ_SUP_PGM[0], sizeof(mmMC_SEQ_SUP_PGM)/sizeof(mmMC_SEQ_SUP_PGM[0]), 0, 0 },
+	{ "mmMC_PMG_AUTO_CMD", REG_MMIO, 0xa34, &mmMC_PMG_AUTO_CMD[0], sizeof(mmMC_PMG_AUTO_CMD)/sizeof(mmMC_PMG_AUTO_CMD[0]), 0, 0 },
+	{ "mmMC_PMG_AUTO_CFG", REG_MMIO, 0xa35, &mmMC_PMG_AUTO_CFG[0], sizeof(mmMC_PMG_AUTO_CFG)/sizeof(mmMC_PMG_AUTO_CFG[0]), 0, 0 },
+	{ "mmMC_IMP_CNTL", REG_MMIO, 0xa36, &mmMC_IMP_CNTL[0], sizeof(mmMC_IMP_CNTL)/sizeof(mmMC_IMP_CNTL[0]), 0, 0 },
+	{ "mmMC_IMP_DEBUG", REG_MMIO, 0xa37, &mmMC_IMP_DEBUG[0], sizeof(mmMC_IMP_DEBUG)/sizeof(mmMC_IMP_DEBUG[0]), 0, 0 },
+	{ "mmMC_IMP_STATUS", REG_MMIO, 0xa38, &mmMC_IMP_STATUS[0], sizeof(mmMC_IMP_STATUS)/sizeof(mmMC_IMP_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_WCDR_CTRL", REG_MMIO, 0xa39, &mmMC_SEQ_WCDR_CTRL[0], sizeof(mmMC_SEQ_WCDR_CTRL)/sizeof(mmMC_SEQ_WCDR_CTRL[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_CNTL", REG_MMIO, 0xa3a, &mmMC_SEQ_TRAIN_WAKEUP_CNTL[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_CNTL)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD", REG_MMIO, 0xa3b, &mmMC_SEQ_TRAIN_EDC_THRESHOLD[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_EDGE", REG_MMIO, 0xa3c, &mmMC_SEQ_TRAIN_WAKEUP_EDGE[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_EDGE)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_EDGE[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_MASK", REG_MMIO, 0xa3d, &mmMC_SEQ_TRAIN_WAKEUP_MASK[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_MASK)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_MASK[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_CAPTURE", REG_MMIO, 0xa3e, &mmMC_SEQ_TRAIN_CAPTURE[0], sizeof(mmMC_SEQ_TRAIN_CAPTURE)/sizeof(mmMC_SEQ_TRAIN_CAPTURE[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_WAKEUP_CLEAR", REG_MMIO, 0xa3f, &mmMC_SEQ_TRAIN_WAKEUP_CLEAR[0], sizeof(mmMC_SEQ_TRAIN_WAKEUP_CLEAR)/sizeof(mmMC_SEQ_TRAIN_WAKEUP_CLEAR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_MISC_D0", REG_SMC, 0xa4, &ixMC_IO_DEBUG_DQB2L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_TIMING", REG_MMIO, 0xa40, &mmMC_SEQ_TRAIN_TIMING[0], sizeof(mmMC_SEQ_TRAIN_TIMING)/sizeof(mmMC_SEQ_TRAIN_TIMING[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDCCDR_R_D0", REG_MMIO, 0xa41, &mmMC_TRAIN_EDCCDR_R_D0[0], sizeof(mmMC_TRAIN_EDCCDR_R_D0)/sizeof(mmMC_TRAIN_EDCCDR_R_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDCCDR_R_D1", REG_MMIO, 0xa42, &mmMC_TRAIN_EDCCDR_R_D1[0], sizeof(mmMC_TRAIN_EDCCDR_R_D1)/sizeof(mmMC_TRAIN_EDCCDR_R_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_0_D0", REG_MMIO, 0xa43, &mmMC_TRAIN_PRBSERR_0_D0[0], sizeof(mmMC_TRAIN_PRBSERR_0_D0)/sizeof(mmMC_TRAIN_PRBSERR_0_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_1_D0", REG_MMIO, 0xa44, &mmMC_TRAIN_PRBSERR_1_D0[0], sizeof(mmMC_TRAIN_PRBSERR_1_D0)/sizeof(mmMC_TRAIN_PRBSERR_1_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDC_STATUS_D0", REG_MMIO, 0xa45, &mmMC_TRAIN_EDC_STATUS_D0[0], sizeof(mmMC_TRAIN_EDC_STATUS_D0)/sizeof(mmMC_TRAIN_EDC_STATUS_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_0_D1", REG_MMIO, 0xa46, &mmMC_TRAIN_PRBSERR_0_D1[0], sizeof(mmMC_TRAIN_PRBSERR_0_D1)/sizeof(mmMC_TRAIN_PRBSERR_0_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_1_D1", REG_MMIO, 0xa47, &mmMC_TRAIN_PRBSERR_1_D1[0], sizeof(mmMC_TRAIN_PRBSERR_1_D1)/sizeof(mmMC_TRAIN_PRBSERR_1_D1[0]), 0, 0 },
+	{ "mmMC_TRAIN_EDC_STATUS_D1", REG_MMIO, 0xa48, &mmMC_TRAIN_EDC_STATUS_D1[0], sizeof(mmMC_TRAIN_EDC_STATUS_D1)/sizeof(mmMC_TRAIN_EDC_STATUS_D1[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY0_D0", REG_MMIO, 0xa49, &mmMC_IO_TXCNTL_DPHY0_D0[0], sizeof(mmMC_IO_TXCNTL_DPHY0_D0)/sizeof(mmMC_IO_TXCNTL_DPHY0_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY1_D0", REG_MMIO, 0xa4a, &mmMC_IO_TXCNTL_DPHY1_D0[0], sizeof(mmMC_IO_TXCNTL_DPHY1_D0)/sizeof(mmMC_IO_TXCNTL_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_APHY_D0", REG_MMIO, 0xa4b, &mmMC_IO_TXCNTL_APHY_D0[0], sizeof(mmMC_IO_TXCNTL_APHY_D0)/sizeof(mmMC_IO_TXCNTL_APHY_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY0_D0", REG_MMIO, 0xa4c, &mmMC_IO_RXCNTL_DPHY0_D0[0], sizeof(mmMC_IO_RXCNTL_DPHY0_D0)/sizeof(mmMC_IO_RXCNTL_DPHY0_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY1_D0", REG_MMIO, 0xa4d, &mmMC_IO_RXCNTL_DPHY1_D0[0], sizeof(mmMC_IO_RXCNTL_DPHY1_D0)/sizeof(mmMC_IO_RXCNTL_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_DPHY_STR_CNTL_D0", REG_MMIO, 0xa4e, &mmMC_IO_DPHY_STR_CNTL_D0[0], sizeof(mmMC_IO_DPHY_STR_CNTL_D0)/sizeof(mmMC_IO_DPHY_STR_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY0_D1", REG_MMIO, 0xa4f, &mmMC_IO_TXCNTL_DPHY0_D1[0], sizeof(mmMC_IO_TXCNTL_DPHY0_D1)/sizeof(mmMC_IO_TXCNTL_DPHY0_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_MISC_D0", REG_SMC, 0xa5, &ixMC_IO_DEBUG_DQB2H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D0[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_DPHY1_D1", REG_MMIO, 0xa50, &mmMC_IO_TXCNTL_DPHY1_D1[0], sizeof(mmMC_IO_TXCNTL_DPHY1_D1)/sizeof(mmMC_IO_TXCNTL_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_IO_TXCNTL_APHY_D1", REG_MMIO, 0xa51, &mmMC_IO_TXCNTL_APHY_D1[0], sizeof(mmMC_IO_TXCNTL_APHY_D1)/sizeof(mmMC_IO_TXCNTL_APHY_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY0_D1", REG_MMIO, 0xa52, &mmMC_IO_RXCNTL_DPHY0_D1[0], sizeof(mmMC_IO_RXCNTL_DPHY0_D1)/sizeof(mmMC_IO_RXCNTL_DPHY0_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL_DPHY1_D1", REG_MMIO, 0xa53, &mmMC_IO_RXCNTL_DPHY1_D1[0], sizeof(mmMC_IO_RXCNTL_DPHY1_D1)/sizeof(mmMC_IO_RXCNTL_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_IO_DPHY_STR_CNTL_D1", REG_MMIO, 0xa54, &mmMC_IO_DPHY_STR_CNTL_D1[0], sizeof(mmMC_IO_DPHY_STR_CNTL_D1)/sizeof(mmMC_IO_DPHY_STR_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL_D0", REG_MMIO, 0xa55, &mmMC_IO_CDRCNTL_D0[0], sizeof(mmMC_IO_CDRCNTL_D0)/sizeof(mmMC_IO_CDRCNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL_D1", REG_MMIO, 0xa56, &mmMC_IO_CDRCNTL_D1[0], sizeof(mmMC_IO_CDRCNTL_D1)/sizeof(mmMC_IO_CDRCNTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_FIFO_CTL", REG_MMIO, 0xa57, &mmMC_SEQ_FIFO_CTL[0], sizeof(mmMC_SEQ_FIFO_CTL)/sizeof(mmMC_SEQ_FIFO_CTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE0_D0", REG_MMIO, 0xa58, &mmMC_SEQ_TXFRAMING_BYTE0_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE1_D0", REG_MMIO, 0xa59, &mmMC_SEQ_TXFRAMING_BYTE1_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE2_D0", REG_MMIO, 0xa5a, &mmMC_SEQ_TXFRAMING_BYTE2_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE3_D0", REG_MMIO, 0xa5b, &mmMC_SEQ_TXFRAMING_BYTE3_D0[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D0)/sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_DBI_D0", REG_MMIO, 0xa5c, &mmMC_SEQ_TXFRAMING_DBI_D0[0], sizeof(mmMC_SEQ_TXFRAMING_DBI_D0)/sizeof(mmMC_SEQ_TXFRAMING_DBI_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_EDC_D0", REG_MMIO, 0xa5d, &mmMC_SEQ_TXFRAMING_EDC_D0[0], sizeof(mmMC_SEQ_TXFRAMING_EDC_D0)/sizeof(mmMC_SEQ_TXFRAMING_EDC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_FCK_D0", REG_MMIO, 0xa5e, &mmMC_SEQ_TXFRAMING_FCK_D0[0], sizeof(mmMC_SEQ_TXFRAMING_FCK_D0)/sizeof(mmMC_SEQ_TXFRAMING_FCK_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC8", REG_MMIO, 0xa5f, &mmMC_SEQ_MISC8[0], sizeof(mmMC_SEQ_MISC8)/sizeof(mmMC_SEQ_MISC8[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_MISC_D0", REG_SMC, 0xa6, &ixMC_IO_DEBUG_DQB3L_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE0_D1", REG_MMIO, 0xa60, &mmMC_SEQ_TXFRAMING_BYTE0_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE1_D1", REG_MMIO, 0xa61, &mmMC_SEQ_TXFRAMING_BYTE1_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE2_D1", REG_MMIO, 0xa62, &mmMC_SEQ_TXFRAMING_BYTE2_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_BYTE3_D1", REG_MMIO, 0xa63, &mmMC_SEQ_TXFRAMING_BYTE3_D1[0], sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D1)/sizeof(mmMC_SEQ_TXFRAMING_BYTE3_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_DBI_D1", REG_MMIO, 0xa64, &mmMC_SEQ_TXFRAMING_DBI_D1[0], sizeof(mmMC_SEQ_TXFRAMING_DBI_D1)/sizeof(mmMC_SEQ_TXFRAMING_DBI_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_EDC_D1", REG_MMIO, 0xa65, &mmMC_SEQ_TXFRAMING_EDC_D1[0], sizeof(mmMC_SEQ_TXFRAMING_EDC_D1)/sizeof(mmMC_SEQ_TXFRAMING_EDC_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TXFRAMING_FCK_D1", REG_MMIO, 0xa66, &mmMC_SEQ_TXFRAMING_FCK_D1[0], sizeof(mmMC_SEQ_TXFRAMING_FCK_D1)/sizeof(mmMC_SEQ_TXFRAMING_FCK_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE0_D0", REG_MMIO, 0xa67, &mmMC_SEQ_RXFRAMING_BYTE0_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE1_D0", REG_MMIO, 0xa68, &mmMC_SEQ_RXFRAMING_BYTE1_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE2_D0", REG_MMIO, 0xa69, &mmMC_SEQ_RXFRAMING_BYTE2_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE3_D0", REG_MMIO, 0xa6a, &mmMC_SEQ_RXFRAMING_BYTE3_D0[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D0)/sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_DBI_D0", REG_MMIO, 0xa6b, &mmMC_SEQ_RXFRAMING_DBI_D0[0], sizeof(mmMC_SEQ_RXFRAMING_DBI_D0)/sizeof(mmMC_SEQ_RXFRAMING_DBI_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_EDC_D0", REG_MMIO, 0xa6c, &mmMC_SEQ_RXFRAMING_EDC_D0[0], sizeof(mmMC_SEQ_RXFRAMING_EDC_D0)/sizeof(mmMC_SEQ_RXFRAMING_EDC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE0_D1", REG_MMIO, 0xa6d, &mmMC_SEQ_RXFRAMING_BYTE0_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE1_D1", REG_MMIO, 0xa6e, &mmMC_SEQ_RXFRAMING_BYTE1_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE2_D1", REG_MMIO, 0xa6f, &mmMC_SEQ_RXFRAMING_BYTE2_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE2_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_MISC_D0", REG_SMC, 0xa7, &ixMC_IO_DEBUG_DQB3H_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_BYTE3_D1", REG_MMIO, 0xa70, &mmMC_SEQ_RXFRAMING_BYTE3_D1[0], sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D1)/sizeof(mmMC_SEQ_RXFRAMING_BYTE3_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_DBI_D1", REG_MMIO, 0xa71, &mmMC_SEQ_RXFRAMING_DBI_D1[0], sizeof(mmMC_SEQ_RXFRAMING_DBI_D1)/sizeof(mmMC_SEQ_RXFRAMING_DBI_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_RXFRAMING_EDC_D1", REG_MMIO, 0xa72, &mmMC_SEQ_RXFRAMING_EDC_D1[0], sizeof(mmMC_SEQ_RXFRAMING_EDC_D1)/sizeof(mmMC_SEQ_RXFRAMING_EDC_D1[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL", REG_MMIO, 0xa73, &mmMC_IO_PAD_CNTL[0], sizeof(mmMC_IO_PAD_CNTL)/sizeof(mmMC_IO_PAD_CNTL[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL_D0", REG_MMIO, 0xa74, &mmMC_IO_PAD_CNTL_D0[0], sizeof(mmMC_IO_PAD_CNTL_D0)/sizeof(mmMC_IO_PAD_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_PAD_CNTL_D1", REG_MMIO, 0xa75, &mmMC_IO_PAD_CNTL_D1[0], sizeof(mmMC_IO_PAD_CNTL_D1)/sizeof(mmMC_IO_PAD_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_NPL_STATUS", REG_MMIO, 0xa76, &mmMC_NPL_STATUS[0], sizeof(mmMC_NPL_STATUS)/sizeof(mmMC_NPL_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_CNTL", REG_MMIO, 0xa77, &mmMC_SEQ_PERF_CNTL[0], sizeof(mmMC_SEQ_PERF_CNTL)/sizeof(mmMC_SEQ_PERF_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CTL", REG_MMIO, 0xa78, &mmMC_SEQ_PERF_SEQ_CTL[0], sizeof(mmMC_SEQ_PERF_SEQ_CTL)/sizeof(mmMC_SEQ_PERF_SEQ_CTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_A_I0", REG_MMIO, 0xa79, &mmMC_SEQ_PERF_SEQ_CNT_A_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_A_I1", REG_MMIO, 0xa7a, &mmMC_SEQ_PERF_SEQ_CNT_A_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_A_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_B_I0", REG_MMIO, 0xa7b, &mmMC_SEQ_PERF_SEQ_CNT_B_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_B_I1", REG_MMIO, 0xa7c, &mmMC_SEQ_PERF_SEQ_CNT_B_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_B_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_STATUS_M", REG_MMIO, 0xa7d, &mmMC_SEQ_STATUS_M[0], sizeof(mmMC_SEQ_STATUS_M)/sizeof(mmMC_SEQ_STATUS_M[0]), 0, 0 },
+	{ "mmMC_SEQ_VENDOR_ID_I0", REG_MMIO, 0xa7e, &mmMC_SEQ_VENDOR_ID_I0[0], sizeof(mmMC_SEQ_VENDOR_ID_I0)/sizeof(mmMC_SEQ_VENDOR_ID_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_VENDOR_ID_I1", REG_MMIO, 0xa7f, &mmMC_SEQ_VENDOR_ID_I1[0], sizeof(mmMC_SEQ_VENDOR_ID_I1)/sizeof(mmMC_SEQ_VENDOR_ID_I1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_MISC_D0", REG_SMC, 0xa8, &ixMC_IO_DEBUG_DBI_MISC_D0[0], sizeof(ixMC_IO_DEBUG_DBI_MISC_D0)/sizeof(ixMC_IO_DEBUG_DBI_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC0", REG_MMIO, 0xa80, &mmMC_SEQ_MISC0[0], sizeof(mmMC_SEQ_MISC0)/sizeof(mmMC_SEQ_MISC0[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC1", REG_MMIO, 0xa81, &mmMC_SEQ_MISC1[0], sizeof(mmMC_SEQ_MISC1)/sizeof(mmMC_SEQ_MISC1[0]), 0, 0 },
+	{ "mmMC_SEQ_RESERVE_M", REG_MMIO, 0xa82, &mmMC_SEQ_RESERVE_M[0], sizeof(mmMC_SEQ_RESERVE_M)/sizeof(mmMC_SEQ_RESERVE_M[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_EMRS", REG_MMIO, 0xa83, &mmMC_PMG_CMD_EMRS[0], sizeof(mmMC_PMG_CMD_EMRS)/sizeof(mmMC_PMG_CMD_EMRS[0]), 0, 0 },
+	{ "mmMC_PMG_CFG", REG_MMIO, 0xa84, &mmMC_PMG_CFG[0], sizeof(mmMC_PMG_CFG)/sizeof(mmMC_PMG_CFG[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP2_STAT", REG_MMIO, 0xa85, &mmMC_SEQ_SUP_GP2_STAT[0], sizeof(mmMC_SEQ_SUP_GP2_STAT)/sizeof(mmMC_SEQ_SUP_GP2_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP3_STAT", REG_MMIO, 0xa86, &mmMC_SEQ_SUP_GP3_STAT[0], sizeof(mmMC_SEQ_SUP_GP3_STAT)/sizeof(mmMC_SEQ_SUP_GP3_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_IR_STAT", REG_MMIO, 0xa87, &mmMC_SEQ_SUP_IR_STAT[0], sizeof(mmMC_SEQ_SUP_IR_STAT)/sizeof(mmMC_SEQ_SUP_IR_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_DEC_STAT", REG_MMIO, 0xa88, &mmMC_SEQ_SUP_DEC_STAT[0], sizeof(mmMC_SEQ_SUP_DEC_STAT)/sizeof(mmMC_SEQ_SUP_DEC_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_PGM_STAT", REG_MMIO, 0xa89, &mmMC_SEQ_SUP_PGM_STAT[0], sizeof(mmMC_SEQ_SUP_PGM_STAT)/sizeof(mmMC_SEQ_SUP_PGM_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_R_PGM", REG_MMIO, 0xa8a, &mmMC_SEQ_SUP_R_PGM[0], sizeof(mmMC_SEQ_SUP_R_PGM)/sizeof(mmMC_SEQ_SUP_R_PGM[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC3", REG_MMIO, 0xa8b, &mmMC_SEQ_MISC3[0], sizeof(mmMC_SEQ_MISC3)/sizeof(mmMC_SEQ_MISC3[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC4", REG_MMIO, 0xa8c, &mmMC_SEQ_MISC4[0], sizeof(mmMC_SEQ_MISC4)/sizeof(mmMC_SEQ_MISC4[0]), 0, 0 },
+	{ "mmMC_BIST_CMP_CNTL", REG_MMIO, 0xa8d, &mmMC_BIST_CMP_CNTL[0], sizeof(mmMC_BIST_CMP_CNTL)/sizeof(mmMC_BIST_CMP_CNTL[0]), 0, 0 },
+	{ "mmMC_BIST_CMD_CNTL", REG_MMIO, 0xa8e, &mmMC_BIST_CMD_CNTL[0], sizeof(mmMC_BIST_CMD_CNTL)/sizeof(mmMC_BIST_CMD_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP0_STAT", REG_MMIO, 0xa8f, &mmMC_SEQ_SUP_GP0_STAT[0], sizeof(mmMC_SEQ_SUP_GP0_STAT)/sizeof(mmMC_SEQ_SUP_GP0_STAT[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_MISC_D0", REG_SMC, 0xa9, &ixMC_IO_DEBUG_EDC_MISC_D0[0], sizeof(ixMC_IO_DEBUG_EDC_MISC_D0)/sizeof(ixMC_IO_DEBUG_EDC_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_SUP_GP1_STAT", REG_MMIO, 0xa90, &mmMC_SEQ_SUP_GP1_STAT[0], sizeof(mmMC_SEQ_SUP_GP1_STAT)/sizeof(mmMC_SEQ_SUP_GP1_STAT[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_DEBUG_INDEX", REG_MMIO, 0xa91, &mmMC_SEQ_IO_DEBUG_INDEX[0], sizeof(mmMC_SEQ_IO_DEBUG_INDEX)/sizeof(mmMC_SEQ_IO_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_DEBUG_DATA", REG_MMIO, 0xa92, &mmMC_SEQ_IO_DEBUG_DATA[0], sizeof(mmMC_SEQ_IO_DEBUG_DATA)/sizeof(mmMC_SEQ_IO_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMC_SEQ_BYTE_REMAP_D0", REG_MMIO, 0xa93, &mmMC_SEQ_BYTE_REMAP_D0[0], sizeof(mmMC_SEQ_BYTE_REMAP_D0)/sizeof(mmMC_SEQ_BYTE_REMAP_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BYTE_REMAP_D1", REG_MMIO, 0xa94, &mmMC_SEQ_BYTE_REMAP_D1[0], sizeof(mmMC_SEQ_BYTE_REMAP_D1)/sizeof(mmMC_SEQ_BYTE_REMAP_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC5", REG_MMIO, 0xa95, &mmMC_SEQ_MISC5[0], sizeof(mmMC_SEQ_MISC5)/sizeof(mmMC_SEQ_MISC5[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC6", REG_MMIO, 0xa96, &mmMC_SEQ_MISC6[0], sizeof(mmMC_SEQ_MISC6)/sizeof(mmMC_SEQ_MISC6[0]), 0, 0 },
+	{ "mmMC_IO_APHY_STR_CNTL_D0", REG_MMIO, 0xa97, &mmMC_IO_APHY_STR_CNTL_D0[0], sizeof(mmMC_IO_APHY_STR_CNTL_D0)/sizeof(mmMC_IO_APHY_STR_CNTL_D0[0]), 0, 0 },
+	{ "mmMC_IO_APHY_STR_CNTL_D1", REG_MMIO, 0xa98, &mmMC_IO_APHY_STR_CNTL_D1[0], sizeof(mmMC_IO_APHY_STR_CNTL_D1)/sizeof(mmMC_IO_APHY_STR_CNTL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC7", REG_MMIO, 0xa99, &mmMC_SEQ_MISC7[0], sizeof(mmMC_SEQ_MISC7)/sizeof(mmMC_SEQ_MISC7[0]), 0, 0 },
+	{ "mmMC_SEQ_CG", REG_MMIO, 0xa9a, &mmMC_SEQ_CG[0], sizeof(mmMC_SEQ_CG)/sizeof(mmMC_SEQ_CG[0]), 0, 0 },
+	{ "mmMC_SEQ_RAS_TIMING_LP", REG_MMIO, 0xa9b, &mmMC_SEQ_RAS_TIMING_LP[0], sizeof(mmMC_SEQ_RAS_TIMING_LP)/sizeof(mmMC_SEQ_RAS_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_CAS_TIMING_LP", REG_MMIO, 0xa9c, &mmMC_SEQ_CAS_TIMING_LP[0], sizeof(mmMC_SEQ_CAS_TIMING_LP)/sizeof(mmMC_SEQ_CAS_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING_LP", REG_MMIO, 0xa9d, &mmMC_SEQ_MISC_TIMING_LP[0], sizeof(mmMC_SEQ_MISC_TIMING_LP)/sizeof(mmMC_SEQ_MISC_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC_TIMING2_LP", REG_MMIO, 0xa9e, &mmMC_SEQ_MISC_TIMING2_LP[0], sizeof(mmMC_SEQ_MISC_TIMING2_LP)/sizeof(mmMC_SEQ_MISC_TIMING2_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D0_LP", REG_MMIO, 0xa9f, &mmMC_SEQ_WR_CTL_D0_LP[0], sizeof(mmMC_SEQ_WR_CTL_D0_LP)/sizeof(mmMC_SEQ_WR_CTL_D0_LP[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_MISC_D0", REG_SMC, 0xaa, &ixMC_IO_DEBUG_WCK_MISC_D0[0], sizeof(ixMC_IO_DEBUG_WCK_MISC_D0)/sizeof(ixMC_IO_DEBUG_WCK_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_D1_LP", REG_MMIO, 0xaa0, &mmMC_SEQ_WR_CTL_D1_LP[0], sizeof(mmMC_SEQ_WR_CTL_D1_LP)/sizeof(mmMC_SEQ_WR_CTL_D1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_EMRS_LP", REG_MMIO, 0xaa1, &mmMC_SEQ_PMG_CMD_EMRS_LP[0], sizeof(mmMC_SEQ_PMG_CMD_EMRS_LP)/sizeof(mmMC_SEQ_PMG_CMD_EMRS_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS_LP", REG_MMIO, 0xaa2, &mmMC_SEQ_PMG_CMD_MRS_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B0_D0", REG_MMIO, 0xaa3, &mmMC_SEQ_BIT_REMAP_B0_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B0_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B0_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B1_D0", REG_MMIO, 0xaa4, &mmMC_SEQ_BIT_REMAP_B1_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B1_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B1_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B2_D0", REG_MMIO, 0xaa5, &mmMC_SEQ_BIT_REMAP_B2_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B2_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B2_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B3_D0", REG_MMIO, 0xaa6, &mmMC_SEQ_BIT_REMAP_B3_D0[0], sizeof(mmMC_SEQ_BIT_REMAP_B3_D0)/sizeof(mmMC_SEQ_BIT_REMAP_B3_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B0_D1", REG_MMIO, 0xaa7, &mmMC_SEQ_BIT_REMAP_B0_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B0_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B0_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B1_D1", REG_MMIO, 0xaa8, &mmMC_SEQ_BIT_REMAP_B1_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B1_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B2_D1", REG_MMIO, 0xaa9, &mmMC_SEQ_BIT_REMAP_B2_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B2_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_BIT_REMAP_B3_D1", REG_MMIO, 0xaaa, &mmMC_SEQ_BIT_REMAP_B3_D1[0], sizeof(mmMC_SEQ_BIT_REMAP_B3_D1)/sizeof(mmMC_SEQ_BIT_REMAP_B3_D1[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS", REG_MMIO, 0xaab, &mmMC_PMG_CMD_MRS[0], sizeof(mmMC_PMG_CMD_MRS)/sizeof(mmMC_PMG_CMD_MRS[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD0", REG_MMIO, 0xaac, &mmMC_SEQ_IO_RWORD0[0], sizeof(mmMC_SEQ_IO_RWORD0)/sizeof(mmMC_SEQ_IO_RWORD0[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD1", REG_MMIO, 0xaad, &mmMC_SEQ_IO_RWORD1[0], sizeof(mmMC_SEQ_IO_RWORD1)/sizeof(mmMC_SEQ_IO_RWORD1[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD2", REG_MMIO, 0xaae, &mmMC_SEQ_IO_RWORD2[0], sizeof(mmMC_SEQ_IO_RWORD2)/sizeof(mmMC_SEQ_IO_RWORD2[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD3", REG_MMIO, 0xaaf, &mmMC_SEQ_IO_RWORD3[0], sizeof(mmMC_SEQ_IO_RWORD3)/sizeof(mmMC_SEQ_IO_RWORD3[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_MISC_D0", REG_SMC, 0xab, &ixMC_IO_DEBUG_CK_MISC_D0[0], sizeof(ixMC_IO_DEBUG_CK_MISC_D0)/sizeof(ixMC_IO_DEBUG_CK_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD4", REG_MMIO, 0xab0, &mmMC_SEQ_IO_RWORD4[0], sizeof(mmMC_SEQ_IO_RWORD4)/sizeof(mmMC_SEQ_IO_RWORD4[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD5", REG_MMIO, 0xab1, &mmMC_SEQ_IO_RWORD5[0], sizeof(mmMC_SEQ_IO_RWORD5)/sizeof(mmMC_SEQ_IO_RWORD5[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD6", REG_MMIO, 0xab2, &mmMC_SEQ_IO_RWORD6[0], sizeof(mmMC_SEQ_IO_RWORD6)/sizeof(mmMC_SEQ_IO_RWORD6[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RWORD7", REG_MMIO, 0xab3, &mmMC_SEQ_IO_RWORD7[0], sizeof(mmMC_SEQ_IO_RWORD7)/sizeof(mmMC_SEQ_IO_RWORD7[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RDBI", REG_MMIO, 0xab4, &mmMC_SEQ_IO_RDBI[0], sizeof(mmMC_SEQ_IO_RDBI)/sizeof(mmMC_SEQ_IO_RDBI[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_REDC", REG_MMIO, 0xab5, &mmMC_SEQ_IO_REDC[0], sizeof(mmMC_SEQ_IO_REDC)/sizeof(mmMC_SEQ_IO_REDC[0]), 0, 0 },
+	{ "mmMC_BIST_CMP_CNTL_2", REG_MMIO, 0xab6, &mmMC_BIST_CMP_CNTL_2[0], sizeof(mmMC_BIST_CMP_CNTL_2)/sizeof(mmMC_BIST_CMP_CNTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RESERVE_D0", REG_MMIO, 0xab7, &mmMC_SEQ_IO_RESERVE_D0[0], sizeof(mmMC_SEQ_IO_RESERVE_D0)/sizeof(mmMC_SEQ_IO_RESERVE_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_IO_RESERVE_D1", REG_MMIO, 0xab8, &mmMC_SEQ_IO_RESERVE_D1[0], sizeof(mmMC_SEQ_IO_RESERVE_D1)/sizeof(mmMC_SEQ_IO_RESERVE_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_HWCNTL", REG_MMIO, 0xab9, &mmMC_SEQ_PMG_PG_HWCNTL[0], sizeof(mmMC_SEQ_PMG_PG_HWCNTL)/sizeof(mmMC_SEQ_PMG_PG_HWCNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_SWCNTL_0", REG_MMIO, 0xaba, &mmMC_SEQ_PMG_PG_SWCNTL_0[0], sizeof(mmMC_SEQ_PMG_PG_SWCNTL_0)/sizeof(mmMC_SEQ_PMG_PG_SWCNTL_0[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_PG_SWCNTL_1", REG_MMIO, 0xabb, &mmMC_SEQ_PMG_PG_SWCNTL_1[0], sizeof(mmMC_SEQ_PMG_PG_SWCNTL_1)/sizeof(mmMC_SEQ_PMG_PG_SWCNTL_1[0]), 0, 0 },
+	{ "mmMC_IMP_DQ_STATUS", REG_MMIO, 0xabc, &mmMC_IMP_DQ_STATUS[0], sizeof(mmMC_IMP_DQ_STATUS)/sizeof(mmMC_IMP_DQ_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_TCG_CNTL", REG_MMIO, 0xabd, &mmMC_SEQ_TCG_CNTL[0], sizeof(mmMC_SEQ_TCG_CNTL)/sizeof(mmMC_SEQ_TCG_CNTL[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_CTRL", REG_MMIO, 0xabe, &mmMC_SEQ_TSM_CTRL[0], sizeof(mmMC_SEQ_TSM_CTRL)/sizeof(mmMC_SEQ_TSM_CTRL[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_GCNT", REG_MMIO, 0xabf, &mmMC_SEQ_TSM_GCNT[0], sizeof(mmMC_SEQ_TSM_GCNT)/sizeof(mmMC_SEQ_TSM_GCNT[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_MISC_D0", REG_SMC, 0xac, &ixMC_IO_DEBUG_ADDRL_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_OCNT", REG_MMIO, 0xac0, &mmMC_SEQ_TSM_OCNT[0], sizeof(mmMC_SEQ_TSM_OCNT)/sizeof(mmMC_SEQ_TSM_OCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_NCNT", REG_MMIO, 0xac1, &mmMC_SEQ_TSM_NCNT[0], sizeof(mmMC_SEQ_TSM_NCNT)/sizeof(mmMC_SEQ_TSM_NCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_BCNT", REG_MMIO, 0xac2, &mmMC_SEQ_TSM_BCNT[0], sizeof(mmMC_SEQ_TSM_BCNT)/sizeof(mmMC_SEQ_TSM_BCNT[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_FLAG", REG_MMIO, 0xac3, &mmMC_SEQ_TSM_FLAG[0], sizeof(mmMC_SEQ_TSM_FLAG)/sizeof(mmMC_SEQ_TSM_FLAG[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_UPDATE", REG_MMIO, 0xac4, &mmMC_SEQ_TSM_UPDATE[0], sizeof(mmMC_SEQ_TSM_UPDATE)/sizeof(mmMC_SEQ_TSM_UPDATE[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_EDC", REG_MMIO, 0xac5, &mmMC_SEQ_TSM_EDC[0], sizeof(mmMC_SEQ_TSM_EDC)/sizeof(mmMC_SEQ_TSM_EDC[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DBI", REG_MMIO, 0xac6, &mmMC_SEQ_TSM_DBI[0], sizeof(mmMC_SEQ_TSM_DBI)/sizeof(mmMC_SEQ_TSM_DBI[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D0_LP", REG_MMIO, 0xac7, &mmMC_SEQ_RD_CTL_D0_LP[0], sizeof(mmMC_SEQ_RD_CTL_D0_LP)/sizeof(mmMC_SEQ_RD_CTL_D0_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_RD_CTL_D1_LP", REG_MMIO, 0xac8, &mmMC_SEQ_RD_CTL_D1_LP[0], sizeof(mmMC_SEQ_RD_CTL_D1_LP)/sizeof(mmMC_SEQ_RD_CTL_D1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_TIMER_WR", REG_MMIO, 0xac9, &mmMC_SEQ_TIMER_WR[0], sizeof(mmMC_SEQ_TIMER_WR)/sizeof(mmMC_SEQ_TIMER_WR[0]), 0, 0 },
+	{ "mmMC_SEQ_TIMER_RD", REG_MMIO, 0xaca, &mmMC_SEQ_TIMER_RD[0], sizeof(mmMC_SEQ_TIMER_RD)/sizeof(mmMC_SEQ_TIMER_RD[0]), 0, 0 },
+	{ "mmMC_SEQ_DRAM_ERROR_INSERTION", REG_MMIO, 0xacb, &mmMC_SEQ_DRAM_ERROR_INSERTION[0], sizeof(mmMC_SEQ_DRAM_ERROR_INSERTION)/sizeof(mmMC_SEQ_DRAM_ERROR_INSERTION[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_D0", REG_MMIO, 0xacc, &mmMC_PHY_TIMING_D0[0], sizeof(mmMC_PHY_TIMING_D0)/sizeof(mmMC_PHY_TIMING_D0[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_D1", REG_MMIO, 0xacd, &mmMC_PHY_TIMING_D1[0], sizeof(mmMC_PHY_TIMING_D1)/sizeof(mmMC_PHY_TIMING_D1[0]), 0, 0 },
+	{ "mmMC_PHY_TIMING_2", REG_MMIO, 0xace, &mmMC_PHY_TIMING_2[0], sizeof(mmMC_PHY_TIMING_2)/sizeof(mmMC_PHY_TIMING_2[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DEBUG_INDEX", REG_MMIO, 0xacf, &mmMC_SEQ_TSM_DEBUG_INDEX[0], sizeof(mmMC_SEQ_TSM_DEBUG_INDEX)/sizeof(mmMC_SEQ_TSM_DEBUG_INDEX[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_MISC_D0", REG_SMC, 0xad, &ixMC_IO_DEBUG_ADDRH_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D0[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_DEBUG_DATA", REG_MMIO, 0xad0, &mmMC_SEQ_TSM_DEBUG_DATA[0], sizeof(mmMC_SEQ_TSM_DEBUG_DATA)/sizeof(mmMC_SEQ_TSM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS1", REG_MMIO, 0xad1, &mmMC_PMG_CMD_MRS1[0], sizeof(mmMC_PMG_CMD_MRS1)/sizeof(mmMC_PMG_CMD_MRS1[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS1_LP", REG_MMIO, 0xad2, &mmMC_SEQ_PMG_CMD_MRS1_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS1_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_TIMING_LP", REG_MMIO, 0xad3, &mmMC_SEQ_PMG_TIMING_LP[0], sizeof(mmMC_SEQ_PMG_TIMING_LP)/sizeof(mmMC_SEQ_PMG_TIMING_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_CNTL_2", REG_MMIO, 0xad4, &mmMC_SEQ_CNTL_2[0], sizeof(mmMC_SEQ_CNTL_2)/sizeof(mmMC_SEQ_CNTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_2", REG_MMIO, 0xad5, &mmMC_SEQ_WR_CTL_2[0], sizeof(mmMC_SEQ_WR_CTL_2)/sizeof(mmMC_SEQ_WR_CTL_2[0]), 0, 0 },
+	{ "mmMC_SEQ_WR_CTL_2_LP", REG_MMIO, 0xad6, &mmMC_SEQ_WR_CTL_2_LP[0], sizeof(mmMC_SEQ_WR_CTL_2_LP)/sizeof(mmMC_SEQ_WR_CTL_2_LP[0]), 0, 0 },
+	{ "mmMC_PMG_CMD_MRS2", REG_MMIO, 0xad7, &mmMC_PMG_CMD_MRS2[0], sizeof(mmMC_PMG_CMD_MRS2)/sizeof(mmMC_PMG_CMD_MRS2[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_CMD_MRS2_LP", REG_MMIO, 0xad8, &mmMC_SEQ_PMG_CMD_MRS2_LP[0], sizeof(mmMC_SEQ_PMG_CMD_MRS2_LP)/sizeof(mmMC_SEQ_PMG_CMD_MRS2_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_C_I0", REG_MMIO, 0xad9, &mmMC_SEQ_PERF_SEQ_CNT_C_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_C_I1", REG_MMIO, 0xada, &mmMC_SEQ_PERF_SEQ_CNT_C_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_C_I1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_D_I0", REG_MMIO, 0xadb, &mmMC_SEQ_PERF_SEQ_CNT_D_I0[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I0)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I0[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_SEQ_CNT_D_I1", REG_MMIO, 0xadc, &mmMC_SEQ_PERF_SEQ_CNT_D_I1[0], sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I1)/sizeof(mmMC_SEQ_PERF_SEQ_CNT_D_I1[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL1_D0", REG_MMIO, 0xadd, &mmMC_IO_CDRCNTL1_D0[0], sizeof(mmMC_IO_CDRCNTL1_D0)/sizeof(mmMC_IO_CDRCNTL1_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL1_D1", REG_MMIO, 0xade, &mmMC_IO_CDRCNTL1_D1[0], sizeof(mmMC_IO_CDRCNTL1_D1)/sizeof(mmMC_IO_CDRCNTL1_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY0_D0", REG_MMIO, 0xadf, &mmMC_IO_RXCNTL1_DPHY0_D0[0], sizeof(mmMC_IO_RXCNTL1_DPHY0_D0)/sizeof(mmMC_IO_RXCNTL1_DPHY0_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_MISC_D0", REG_SMC, 0xae, &ixMC_IO_DEBUG_ACMD_MISC_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_MISC_D0)/sizeof(ixMC_IO_DEBUG_ACMD_MISC_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY1_D0", REG_MMIO, 0xae0, &mmMC_IO_RXCNTL1_DPHY1_D0[0], sizeof(mmMC_IO_RXCNTL1_DPHY1_D0)/sizeof(mmMC_IO_RXCNTL1_DPHY1_D0[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY0_D1", REG_MMIO, 0xae1, &mmMC_IO_RXCNTL1_DPHY0_D1[0], sizeof(mmMC_IO_RXCNTL1_DPHY0_D1)/sizeof(mmMC_IO_RXCNTL1_DPHY0_D1[0]), 0, 0 },
+	{ "mmMC_IO_RXCNTL1_DPHY1_D1", REG_MMIO, 0xae2, &mmMC_IO_RXCNTL1_DPHY1_D1[0], sizeof(mmMC_IO_RXCNTL1_DPHY1_D1)/sizeof(mmMC_IO_RXCNTL1_DPHY1_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_WCDR", REG_MMIO, 0xae3, &mmMC_SEQ_TSM_WCDR[0], sizeof(mmMC_SEQ_TSM_WCDR)/sizeof(mmMC_SEQ_TSM_WCDR[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL2_D0", REG_MMIO, 0xae4, &mmMC_IO_CDRCNTL2_D0[0], sizeof(mmMC_IO_CDRCNTL2_D0)/sizeof(mmMC_IO_CDRCNTL2_D0[0]), 0, 0 },
+	{ "mmMC_IO_CDRCNTL2_D1", REG_MMIO, 0xae5, &mmMC_IO_CDRCNTL2_D1[0], sizeof(mmMC_IO_CDRCNTL2_D1)/sizeof(mmMC_IO_CDRCNTL2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_TSM_MISC", REG_MMIO, 0xae6, &mmMC_SEQ_TSM_MISC[0], sizeof(mmMC_SEQ_TSM_MISC)/sizeof(mmMC_SEQ_TSM_MISC[0]), 0, 0 },
+	{ "mmMC_SEQ_MISC9", REG_MMIO, 0xae7, &mmMC_SEQ_MISC9[0], sizeof(mmMC_SEQ_MISC9)/sizeof(mmMC_SEQ_MISC9[0]), 0, 0 },
+	{ "mmMCLK_PWRMGT_CNTL", REG_MMIO, 0xae8, &mmMCLK_PWRMGT_CNTL[0], sizeof(mmMCLK_PWRMGT_CNTL)/sizeof(mmMCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "mmDLL_CNTL", REG_MMIO, 0xae9, &mmDLL_CNTL[0], sizeof(mmDLL_CNTL)/sizeof(mmDLL_CNTL[0]), 0, 0 },
+	{ "mmMPLL_SEQ_UCODE_1", REG_MMIO, 0xaea, &mmMPLL_SEQ_UCODE_1[0], sizeof(mmMPLL_SEQ_UCODE_1)/sizeof(mmMPLL_SEQ_UCODE_1[0]), 0, 0 },
+	{ "mmMPLL_SEQ_UCODE_2", REG_MMIO, 0xaeb, &mmMPLL_SEQ_UCODE_2[0], sizeof(mmMPLL_SEQ_UCODE_2)/sizeof(mmMPLL_SEQ_UCODE_2[0]), 0, 0 },
+	{ "mmMPLL_CNTL_MODE", REG_MMIO, 0xaec, &mmMPLL_CNTL_MODE[0], sizeof(mmMPLL_CNTL_MODE)/sizeof(mmMPLL_CNTL_MODE[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL", REG_MMIO, 0xaed, &mmMPLL_FUNC_CNTL[0], sizeof(mmMPLL_FUNC_CNTL)/sizeof(mmMPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL_1", REG_MMIO, 0xaee, &mmMPLL_FUNC_CNTL_1[0], sizeof(mmMPLL_FUNC_CNTL_1)/sizeof(mmMPLL_FUNC_CNTL_1[0]), 0, 0 },
+	{ "mmMPLL_FUNC_CNTL_2", REG_MMIO, 0xaef, &mmMPLL_FUNC_CNTL_2[0], sizeof(mmMPLL_FUNC_CNTL_2)/sizeof(mmMPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_MISC_D0", REG_SMC, 0xaf, &ixMC_IO_DEBUG_CMD_MISC_D0[0], sizeof(ixMC_IO_DEBUG_CMD_MISC_D0)/sizeof(ixMC_IO_DEBUG_CMD_MISC_D0[0]), 0, 0 },
+	{ "mmMPLL_AD_FUNC_CNTL", REG_MMIO, 0xaf0, &mmMPLL_AD_FUNC_CNTL[0], sizeof(mmMPLL_AD_FUNC_CNTL)/sizeof(mmMPLL_AD_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_DQ_FUNC_CNTL", REG_MMIO, 0xaf1, &mmMPLL_DQ_FUNC_CNTL[0], sizeof(mmMPLL_DQ_FUNC_CNTL)/sizeof(mmMPLL_DQ_FUNC_CNTL[0]), 0, 0 },
+	{ "mmMPLL_TIME", REG_MMIO, 0xaf2, &mmMPLL_TIME[0], sizeof(mmMPLL_TIME)/sizeof(mmMPLL_TIME[0]), 0, 0 },
+	{ "mmMPLL_SS1", REG_MMIO, 0xaf3, &mmMPLL_SS1[0], sizeof(mmMPLL_SS1)/sizeof(mmMPLL_SS1[0]), 0, 0 },
+	{ "mmMPLL_SS2", REG_MMIO, 0xaf4, &mmMPLL_SS2[0], sizeof(mmMPLL_SS2)/sizeof(mmMPLL_SS2[0]), 0, 0 },
+	{ "mmMPLL_CONTROL", REG_MMIO, 0xaf5, &mmMPLL_CONTROL[0], sizeof(mmMPLL_CONTROL)/sizeof(mmMPLL_CONTROL[0]), 0, 0 },
+	{ "mmMPLL_AD_STATUS", REG_MMIO, 0xaf6, &mmMPLL_AD_STATUS[0], sizeof(mmMPLL_AD_STATUS)/sizeof(mmMPLL_AD_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_0_0_STATUS", REG_MMIO, 0xaf7, &mmMPLL_DQ_0_0_STATUS[0], sizeof(mmMPLL_DQ_0_0_STATUS)/sizeof(mmMPLL_DQ_0_0_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_0_1_STATUS", REG_MMIO, 0xaf8, &mmMPLL_DQ_0_1_STATUS[0], sizeof(mmMPLL_DQ_0_1_STATUS)/sizeof(mmMPLL_DQ_0_1_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_1_0_STATUS", REG_MMIO, 0xaf9, &mmMPLL_DQ_1_0_STATUS[0], sizeof(mmMPLL_DQ_1_0_STATUS)/sizeof(mmMPLL_DQ_1_0_STATUS[0]), 0, 0 },
+	{ "mmMPLL_DQ_1_1_STATUS", REG_MMIO, 0xafa, &mmMPLL_DQ_1_1_STATUS[0], sizeof(mmMPLL_DQ_1_1_STATUS)/sizeof(mmMPLL_DQ_1_1_STATUS[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_2_D0", REG_MMIO, 0xafb, &mmMC_TRAIN_PRBSERR_2_D0[0], sizeof(mmMC_TRAIN_PRBSERR_2_D0)/sizeof(mmMC_TRAIN_PRBSERR_2_D0[0]), 0, 0 },
+	{ "mmMC_TRAIN_PRBSERR_2_D1", REG_MMIO, 0xafc, &mmMC_TRAIN_PRBSERR_2_D1[0], sizeof(mmMC_TRAIN_PRBSERR_2_D1)/sizeof(mmMC_TRAIN_PRBSERR_2_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_PERF_CNTL_1", REG_MMIO, 0xafd, &mmMC_SEQ_PERF_CNTL_1[0], sizeof(mmMC_SEQ_PERF_CNTL_1)/sizeof(mmMC_SEQ_PERF_CNTL_1[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD2", REG_MMIO, 0xafe, &mmMC_SEQ_TRAIN_EDC_THRESHOLD2[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD2)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD2[0]), 0, 0 },
+	{ "mmMC_SEQ_TRAIN_EDC_THRESHOLD3", REG_MMIO, 0xaff, &mmMC_SEQ_TRAIN_EDC_THRESHOLD3[0], sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD3)/sizeof(mmMC_SEQ_TRAIN_EDC_THRESHOLD3[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT8", REG_SMC, 0xb, &ixMC_TSM_DEBUG_BCNT8[0], sizeof(ixMC_TSM_DEBUG_BCNT8)/sizeof(ixMC_TSM_DEBUG_BCNT8[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_11", REG_SMC, 0xb, &ixMC_IO_DEBUG_UP_11[0], sizeof(ixMC_IO_DEBUG_UP_11)/sizeof(ixMC_IO_DEBUG_UP_11[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_MISC_D1", REG_SMC, 0xb0, &ixMC_IO_DEBUG_DQB0L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_MISC_D1", REG_SMC, 0xb1, &ixMC_IO_DEBUG_DQB0H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_MISC_D1", REG_SMC, 0xb2, &ixMC_IO_DEBUG_DQB1L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_MISC_D1", REG_SMC, 0xb3, &ixMC_IO_DEBUG_DQB1H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_MISC_D1", REG_SMC, 0xb4, &ixMC_IO_DEBUG_DQB2L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_MISC_D1", REG_SMC, 0xb5, &ixMC_IO_DEBUG_DQB2H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_MISC_D1", REG_SMC, 0xb6, &ixMC_IO_DEBUG_DQB3L_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_MISC_D1", REG_SMC, 0xb7, &ixMC_IO_DEBUG_DQB3H_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_MISC_D1", REG_SMC, 0xb8, &ixMC_IO_DEBUG_DBI_MISC_D1[0], sizeof(ixMC_IO_DEBUG_DBI_MISC_D1)/sizeof(ixMC_IO_DEBUG_DBI_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_MISC_D1", REG_SMC, 0xb9, &ixMC_IO_DEBUG_EDC_MISC_D1[0], sizeof(ixMC_IO_DEBUG_EDC_MISC_D1)/sizeof(ixMC_IO_DEBUG_EDC_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_MISC_D1", REG_SMC, 0xba, &ixMC_IO_DEBUG_WCK_MISC_D1[0], sizeof(ixMC_IO_DEBUG_WCK_MISC_D1)/sizeof(ixMC_IO_DEBUG_WCK_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_MISC_D1", REG_SMC, 0xbb, &ixMC_IO_DEBUG_CK_MISC_D1[0], sizeof(ixMC_IO_DEBUG_CK_MISC_D1)/sizeof(ixMC_IO_DEBUG_CK_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_MISC_D1", REG_SMC, 0xbc, &ixMC_IO_DEBUG_ADDRL_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_MISC_D1", REG_SMC, 0xbd, &ixMC_IO_DEBUG_ADDRH_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_MISC_D1", REG_SMC, 0xbe, &ixMC_IO_DEBUG_ACMD_MISC_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_MISC_D1)/sizeof(ixMC_IO_DEBUG_ACMD_MISC_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_MISC_D1", REG_SMC, 0xbf, &ixMC_IO_DEBUG_CMD_MISC_D1[0], sizeof(ixMC_IO_DEBUG_CMD_MISC_D1)/sizeof(ixMC_IO_DEBUG_CMD_MISC_D1[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT9", REG_SMC, 0xc, &ixMC_TSM_DEBUG_BCNT9[0], sizeof(ixMC_TSM_DEBUG_BCNT9)/sizeof(ixMC_TSM_DEBUG_BCNT9[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_12", REG_SMC, 0xc, &ixMC_IO_DEBUG_UP_12[0], sizeof(ixMC_IO_DEBUG_UP_12)/sizeof(ixMC_IO_DEBUG_UP_12[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_CLKSEL_D0", REG_SMC, 0xc0, &ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_CLKSEL_D0", REG_SMC, 0xc1, &ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_CLKSEL_D0", REG_SMC, 0xc2, &ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_CLKSEL_D0", REG_SMC, 0xc3, &ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_CLKSEL_D0", REG_SMC, 0xc4, &ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_CLKSEL_D0", REG_SMC, 0xc5, &ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_CLKSEL_D0", REG_SMC, 0xc6, &ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_CLKSEL_D0", REG_SMC, 0xc7, &ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CLKSEL_D0", REG_SMC, 0xc8, &ixMC_IO_DEBUG_DBI_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D0[0]), 0, 0 },
+	{ "mmMC_XBAR_ADDR_DEC", REG_MMIO, 0xc80, &mmMC_XBAR_ADDR_DEC[0], sizeof(mmMC_XBAR_ADDR_DEC)/sizeof(mmMC_XBAR_ADDR_DEC[0]), 0, 0 },
+	{ "mmMC_XBAR_REMOTE", REG_MMIO, 0xc81, &mmMC_XBAR_REMOTE[0], sizeof(mmMC_XBAR_REMOTE)/sizeof(mmMC_XBAR_REMOTE[0]), 0, 0 },
+	{ "mmMC_XBAR_WRREQ_CREDIT", REG_MMIO, 0xc82, &mmMC_XBAR_WRREQ_CREDIT[0], sizeof(mmMC_XBAR_WRREQ_CREDIT)/sizeof(mmMC_XBAR_WRREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_CREDIT", REG_MMIO, 0xc83, &mmMC_XBAR_RDREQ_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_CREDIT)/sizeof(mmMC_XBAR_RDREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_PRI_CREDIT", REG_MMIO, 0xc84, &mmMC_XBAR_RDREQ_PRI_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT)/sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT1", REG_MMIO, 0xc85, &mmMC_XBAR_WRRET_CREDIT1[0], sizeof(mmMC_XBAR_WRRET_CREDIT1)/sizeof(mmMC_XBAR_WRRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT2", REG_MMIO, 0xc86, &mmMC_XBAR_WRRET_CREDIT2[0], sizeof(mmMC_XBAR_WRRET_CREDIT2)/sizeof(mmMC_XBAR_WRRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT1", REG_MMIO, 0xc87, &mmMC_XBAR_RDRET_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_CREDIT1)/sizeof(mmMC_XBAR_RDRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT2", REG_MMIO, 0xc88, &mmMC_XBAR_RDRET_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_CREDIT2)/sizeof(mmMC_XBAR_RDRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT1", REG_MMIO, 0xc89, &mmMC_XBAR_RDRET_PRI_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT2", REG_MMIO, 0xc8a, &mmMC_XBAR_RDRET_PRI_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_CHTRIREMAP", REG_MMIO, 0xc8b, &mmMC_XBAR_CHTRIREMAP[0], sizeof(mmMC_XBAR_CHTRIREMAP)/sizeof(mmMC_XBAR_CHTRIREMAP[0]), 0, 0 },
+	{ "mmMC_XBAR_TWOCHAN", REG_MMIO, 0xc8c, &mmMC_XBAR_TWOCHAN[0], sizeof(mmMC_XBAR_TWOCHAN)/sizeof(mmMC_XBAR_TWOCHAN[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB", REG_MMIO, 0xc8d, &mmMC_XBAR_ARB[0], sizeof(mmMC_XBAR_ARB)/sizeof(mmMC_XBAR_ARB[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB_MAX_BURST", REG_MMIO, 0xc8e, &mmMC_XBAR_ARB_MAX_BURST[0], sizeof(mmMC_XBAR_ARB_MAX_BURST)/sizeof(mmMC_XBAR_ARB_MAX_BURST[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_CNTL0", REG_MMIO, 0xc8f, &mmMC_XBAR_FIFO_MON_CNTL0[0], sizeof(mmMC_XBAR_FIFO_MON_CNTL0)/sizeof(mmMC_XBAR_FIFO_MON_CNTL0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CLKSEL_D0", REG_SMC, 0xc9, &ixMC_IO_DEBUG_EDC_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D0[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_CNTL1", REG_MMIO, 0xc90, &mmMC_XBAR_FIFO_MON_CNTL1[0], sizeof(mmMC_XBAR_FIFO_MON_CNTL1)/sizeof(mmMC_XBAR_FIFO_MON_CNTL1[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_CNTL2", REG_MMIO, 0xc91, &mmMC_XBAR_FIFO_MON_CNTL2[0], sizeof(mmMC_XBAR_FIFO_MON_CNTL2)/sizeof(mmMC_XBAR_FIFO_MON_CNTL2[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_RSLT0", REG_MMIO, 0xc92, &mmMC_XBAR_FIFO_MON_RSLT0[0], sizeof(mmMC_XBAR_FIFO_MON_RSLT0)/sizeof(mmMC_XBAR_FIFO_MON_RSLT0[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_RSLT1", REG_MMIO, 0xc93, &mmMC_XBAR_FIFO_MON_RSLT1[0], sizeof(mmMC_XBAR_FIFO_MON_RSLT1)/sizeof(mmMC_XBAR_FIFO_MON_RSLT1[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_RSLT2", REG_MMIO, 0xc94, &mmMC_XBAR_FIFO_MON_RSLT2[0], sizeof(mmMC_XBAR_FIFO_MON_RSLT2)/sizeof(mmMC_XBAR_FIFO_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_RSLT3", REG_MMIO, 0xc95, &mmMC_XBAR_FIFO_MON_RSLT3[0], sizeof(mmMC_XBAR_FIFO_MON_RSLT3)/sizeof(mmMC_XBAR_FIFO_MON_RSLT3[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_MAX_THSH", REG_MMIO, 0xc96, &mmMC_XBAR_FIFO_MON_MAX_THSH[0], sizeof(mmMC_XBAR_FIFO_MON_MAX_THSH)/sizeof(mmMC_XBAR_FIFO_MON_MAX_THSH[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE0", REG_MMIO, 0xc97, &mmMC_XBAR_SPARE0[0], sizeof(mmMC_XBAR_SPARE0)/sizeof(mmMC_XBAR_SPARE0[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE1", REG_MMIO, 0xc98, &mmMC_XBAR_SPARE1[0], sizeof(mmMC_XBAR_SPARE1)/sizeof(mmMC_XBAR_SPARE1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_CLKSEL_D0", REG_SMC, 0xca, &ixMC_IO_DEBUG_WCK_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_CLKSEL_D0", REG_SMC, 0xcb, &ixMC_IO_DEBUG_CK_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_CLKSEL_D0", REG_SMC, 0xcc, &ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D0[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_LOW_ADDR", REG_MMIO, 0xcc0, &mmATC_VM_APERTURE0_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE0_LOW_ADDR)/sizeof(mmATC_VM_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_LOW_ADDR", REG_MMIO, 0xcc1, &mmATC_VM_APERTURE1_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE1_LOW_ADDR)/sizeof(mmATC_VM_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_HIGH_ADDR", REG_MMIO, 0xcc2, &mmATC_VM_APERTURE0_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE0_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_HIGH_ADDR", REG_MMIO, 0xcc3, &mmATC_VM_APERTURE1_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE1_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL", REG_MMIO, 0xcc4, &mmATC_VM_APERTURE0_CNTL[0], sizeof(mmATC_VM_APERTURE0_CNTL)/sizeof(mmATC_VM_APERTURE0_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL", REG_MMIO, 0xcc5, &mmATC_VM_APERTURE1_CNTL[0], sizeof(mmATC_VM_APERTURE1_CNTL)/sizeof(mmATC_VM_APERTURE1_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL2", REG_MMIO, 0xcc6, &mmATC_VM_APERTURE0_CNTL2[0], sizeof(mmATC_VM_APERTURE0_CNTL2)/sizeof(mmATC_VM_APERTURE0_CNTL2[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL2", REG_MMIO, 0xcc7, &mmATC_VM_APERTURE1_CNTL2[0], sizeof(mmATC_VM_APERTURE1_CNTL2)/sizeof(mmATC_VM_APERTURE1_CNTL2[0]), 0, 0 },
+	{ "mmATC_ATS_CNTL", REG_MMIO, 0xcc9, &mmATC_ATS_CNTL[0], sizeof(mmATC_ATS_CNTL)/sizeof(mmATC_ATS_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_DEBUG", REG_MMIO, 0xcca, &mmATC_ATS_DEBUG[0], sizeof(mmATC_ATS_DEBUG)/sizeof(mmATC_ATS_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_DEBUG", REG_MMIO, 0xccb, &mmATC_ATS_FAULT_DEBUG[0], sizeof(mmATC_ATS_FAULT_DEBUG)/sizeof(mmATC_ATS_FAULT_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_STATUS", REG_MMIO, 0xccc, &mmATC_ATS_STATUS[0], sizeof(mmATC_ATS_STATUS)/sizeof(mmATC_ATS_STATUS[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_CNTL", REG_MMIO, 0xccd, &mmATC_ATS_FAULT_CNTL[0], sizeof(mmATC_ATS_FAULT_CNTL)/sizeof(mmATC_ATS_FAULT_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_INFO", REG_MMIO, 0xcce, &mmATC_ATS_FAULT_STATUS_INFO[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO)/sizeof(mmATC_ATS_FAULT_STATUS_INFO[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_ADDR", REG_MMIO, 0xccf, &mmATC_ATS_FAULT_STATUS_ADDR[0], sizeof(mmATC_ATS_FAULT_STATUS_ADDR)/sizeof(mmATC_ATS_FAULT_STATUS_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_CLKSEL_D0", REG_SMC, 0xcd, &ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D0[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_LOW", REG_MMIO, 0xcd0, &mmATC_ATS_DEFAULT_PAGE_LOW[0], sizeof(mmATC_ATS_DEFAULT_PAGE_LOW)/sizeof(mmATC_ATS_DEFAULT_PAGE_LOW[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_CNTL", REG_MMIO, 0xcd1, &mmATC_ATS_DEFAULT_PAGE_CNTL[0], sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL)/sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_INFO2", REG_MMIO, 0xcd2, &mmATC_ATS_FAULT_STATUS_INFO2[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO2)/sizeof(mmATC_ATS_FAULT_STATUS_INFO2[0]), 0, 0 },
+	{ "mmATC_MISC_CG", REG_MMIO, 0xcd4, &mmATC_MISC_CG[0], sizeof(mmATC_MISC_CG)/sizeof(mmATC_MISC_CG[0]), 0, 0 },
+	{ "mmATC_L2_CNTL", REG_MMIO, 0xcd5, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 },
+	{ "mmATC_L2_CNTL2", REG_MMIO, 0xcd6, &mmATC_L2_CNTL2[0], sizeof(mmATC_L2_CNTL2)/sizeof(mmATC_L2_CNTL2[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG", REG_MMIO, 0xcd7, &mmATC_L2_DEBUG[0], sizeof(mmATC_L2_DEBUG)/sizeof(mmATC_L2_DEBUG[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG2", REG_MMIO, 0xcd8, &mmATC_L2_DEBUG2[0], sizeof(mmATC_L2_DEBUG2)/sizeof(mmATC_L2_DEBUG2[0]), 0, 0 },
+	{ "mmATC_L2_CACHE_DATA0", REG_MMIO, 0xcd9, &mmATC_L2_CACHE_DATA0[0], sizeof(mmATC_L2_CACHE_DATA0)/sizeof(mmATC_L2_CACHE_DATA0[0]), 0, 0 },
+	{ "mmATC_L2_CACHE_DATA1", REG_MMIO, 0xcda, &mmATC_L2_CACHE_DATA1[0], sizeof(mmATC_L2_CACHE_DATA1)/sizeof(mmATC_L2_CACHE_DATA1[0]), 0, 0 },
+	{ "mmATC_L2_CACHE_DATA2", REG_MMIO, 0xcdb, &mmATC_L2_CACHE_DATA2[0], sizeof(mmATC_L2_CACHE_DATA2)/sizeof(mmATC_L2_CACHE_DATA2[0]), 0, 0 },
+	{ "mmATC_L1_CNTL", REG_MMIO, 0xcdc, &mmATC_L1_CNTL[0], sizeof(mmATC_L1_CNTL)/sizeof(mmATC_L1_CNTL[0]), 0, 0 },
+	{ "mmATC_L1_ADDRESS_OFFSET", REG_MMIO, 0xcdd, &mmATC_L1_ADDRESS_OFFSET[0], sizeof(mmATC_L1_ADDRESS_OFFSET)/sizeof(mmATC_L1_ADDRESS_OFFSET[0]), 0, 0 },
+	{ "mmATC_L1RD_DEBUG_TLB", REG_MMIO, 0xcde, &mmATC_L1RD_DEBUG_TLB[0], sizeof(mmATC_L1RD_DEBUG_TLB)/sizeof(mmATC_L1RD_DEBUG_TLB[0]), 0, 0 },
+	{ "mmATC_L1WR_DEBUG_TLB", REG_MMIO, 0xcdf, &mmATC_L1WR_DEBUG_TLB[0], sizeof(mmATC_L1WR_DEBUG_TLB)/sizeof(mmATC_L1WR_DEBUG_TLB[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_CLKSEL_D0", REG_SMC, 0xce, &ixMC_IO_DEBUG_ACMD_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D0[0]), 0, 0 },
+	{ "mmATC_L1RD_STATUS", REG_MMIO, 0xce0, &mmATC_L1RD_STATUS[0], sizeof(mmATC_L1RD_STATUS)/sizeof(mmATC_L1RD_STATUS[0]), 0, 0 },
+	{ "mmATC_L1WR_STATUS", REG_MMIO, 0xce1, &mmATC_L1WR_STATUS[0], sizeof(mmATC_L1WR_STATUS)/sizeof(mmATC_L1WR_STATUS[0]), 0, 0 },
+	{ "mmATC_L1RD_DEBUG2_TLB", REG_MMIO, 0xce2, &mmATC_L1RD_DEBUG2_TLB[0], sizeof(mmATC_L1RD_DEBUG2_TLB)/sizeof(mmATC_L1RD_DEBUG2_TLB[0]), 0, 0 },
+	{ "mmATC_L1WR_DEBUG2_TLB", REG_MMIO, 0xce3, &mmATC_L1WR_DEBUG2_TLB[0], sizeof(mmATC_L1WR_DEBUG2_TLB)/sizeof(mmATC_L1WR_DEBUG2_TLB[0]), 0, 0 },
+	{ "mmATC_VMID_PASID_MAPPING_UPDATE_STATUS", REG_MMIO, 0xce6, &mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0], sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)/sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmATC_VMID0_PASID_MAPPING", REG_MMIO, 0xce7, &mmATC_VMID0_PASID_MAPPING[0], sizeof(mmATC_VMID0_PASID_MAPPING)/sizeof(mmATC_VMID0_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID1_PASID_MAPPING", REG_MMIO, 0xce8, &mmATC_VMID1_PASID_MAPPING[0], sizeof(mmATC_VMID1_PASID_MAPPING)/sizeof(mmATC_VMID1_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID2_PASID_MAPPING", REG_MMIO, 0xce9, &mmATC_VMID2_PASID_MAPPING[0], sizeof(mmATC_VMID2_PASID_MAPPING)/sizeof(mmATC_VMID2_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID3_PASID_MAPPING", REG_MMIO, 0xcea, &mmATC_VMID3_PASID_MAPPING[0], sizeof(mmATC_VMID3_PASID_MAPPING)/sizeof(mmATC_VMID3_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID4_PASID_MAPPING", REG_MMIO, 0xceb, &mmATC_VMID4_PASID_MAPPING[0], sizeof(mmATC_VMID4_PASID_MAPPING)/sizeof(mmATC_VMID4_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID5_PASID_MAPPING", REG_MMIO, 0xcec, &mmATC_VMID5_PASID_MAPPING[0], sizeof(mmATC_VMID5_PASID_MAPPING)/sizeof(mmATC_VMID5_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID6_PASID_MAPPING", REG_MMIO, 0xced, &mmATC_VMID6_PASID_MAPPING[0], sizeof(mmATC_VMID6_PASID_MAPPING)/sizeof(mmATC_VMID6_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID7_PASID_MAPPING", REG_MMIO, 0xcee, &mmATC_VMID7_PASID_MAPPING[0], sizeof(mmATC_VMID7_PASID_MAPPING)/sizeof(mmATC_VMID7_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID8_PASID_MAPPING", REG_MMIO, 0xcef, &mmATC_VMID8_PASID_MAPPING[0], sizeof(mmATC_VMID8_PASID_MAPPING)/sizeof(mmATC_VMID8_PASID_MAPPING[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_CLKSEL_D0", REG_SMC, 0xcf, &ixMC_IO_DEBUG_CMD_CLKSEL_D0[0], sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D0)/sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D0[0]), 0, 0 },
+	{ "mmATC_VMID9_PASID_MAPPING", REG_MMIO, 0xcf0, &mmATC_VMID9_PASID_MAPPING[0], sizeof(mmATC_VMID9_PASID_MAPPING)/sizeof(mmATC_VMID9_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID10_PASID_MAPPING", REG_MMIO, 0xcf1, &mmATC_VMID10_PASID_MAPPING[0], sizeof(mmATC_VMID10_PASID_MAPPING)/sizeof(mmATC_VMID10_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID11_PASID_MAPPING", REG_MMIO, 0xcf2, &mmATC_VMID11_PASID_MAPPING[0], sizeof(mmATC_VMID11_PASID_MAPPING)/sizeof(mmATC_VMID11_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID12_PASID_MAPPING", REG_MMIO, 0xcf3, &mmATC_VMID12_PASID_MAPPING[0], sizeof(mmATC_VMID12_PASID_MAPPING)/sizeof(mmATC_VMID12_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID13_PASID_MAPPING", REG_MMIO, 0xcf4, &mmATC_VMID13_PASID_MAPPING[0], sizeof(mmATC_VMID13_PASID_MAPPING)/sizeof(mmATC_VMID13_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID14_PASID_MAPPING", REG_MMIO, 0xcf5, &mmATC_VMID14_PASID_MAPPING[0], sizeof(mmATC_VMID14_PASID_MAPPING)/sizeof(mmATC_VMID14_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID15_PASID_MAPPING", REG_MMIO, 0xcf6, &mmATC_VMID15_PASID_MAPPING[0], sizeof(mmATC_VMID15_PASID_MAPPING)/sizeof(mmATC_VMID15_PASID_MAPPING[0]), 0, 0 },
+	{ "ixMC_TSM_DEBUG_BCNT10", REG_SMC, 0xd, &ixMC_TSM_DEBUG_BCNT10[0], sizeof(ixMC_TSM_DEBUG_BCNT10)/sizeof(ixMC_TSM_DEBUG_BCNT10[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_13", REG_SMC, 0xd, &ixMC_IO_DEBUG_UP_13[0], sizeof(ixMC_IO_DEBUG_UP_13)/sizeof(ixMC_IO_DEBUG_UP_13[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_CLKSEL_D1", REG_SMC, 0xd0, &ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_CLKSEL_D1[0]), 0, 0 },
+	{ "mmATC_ATS_VMID_STATUS", REG_MMIO, 0xd07, &mmATC_ATS_VMID_STATUS[0], sizeof(mmATC_ATS_VMID_STATUS)/sizeof(mmATC_ATS_VMID_STATUS[0]), 0, 0 },
+	{ "mmATC_ATS_SMU_STATUS", REG_MMIO, 0xd08, &mmATC_ATS_SMU_STATUS[0], sizeof(mmATC_ATS_SMU_STATUS)/sizeof(mmATC_ATS_SMU_STATUS[0]), 0, 0 },
+	{ "mmATC_L2_CNTL3", REG_MMIO, 0xd09, &mmATC_L2_CNTL3[0], sizeof(mmATC_L2_CNTL3)/sizeof(mmATC_L2_CNTL3[0]), 0, 0 },
+	{ "mmATC_L2_STATUS", REG_MMIO, 0xd0a, &mmATC_L2_STATUS[0], sizeof(mmATC_L2_STATUS)/sizeof(mmATC_L2_STATUS[0]), 0, 0 },
+	{ "mmATC_L2_STATUS2", REG_MMIO, 0xd0b, &mmATC_L2_STATUS2[0], sizeof(mmATC_L2_STATUS2)/sizeof(mmATC_L2_STATUS2[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_CLKSEL_D1", REG_SMC, 0xd1, &ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_CLKSEL_D1", REG_SMC, 0xd2, &ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_CLKSEL_D1", REG_SMC, 0xd3, &ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_CLKSEL_D1", REG_SMC, 0xd4, &ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_CLKSEL_D1[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_INDEX", REG_MMIO, 0xd40, &mmGMCON_RENG_RAM_INDEX[0], sizeof(mmGMCON_RENG_RAM_INDEX)/sizeof(mmGMCON_RENG_RAM_INDEX[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_DATA", REG_MMIO, 0xd41, &mmGMCON_RENG_RAM_DATA[0], sizeof(mmGMCON_RENG_RAM_DATA)/sizeof(mmGMCON_RENG_RAM_DATA[0]), 0, 0 },
+	{ "mmGMCON_RENG_EXECUTE", REG_MMIO, 0xd42, &mmGMCON_RENG_EXECUTE[0], sizeof(mmGMCON_RENG_EXECUTE)/sizeof(mmGMCON_RENG_EXECUTE[0]), 0, 0 },
+	{ "mmGMCON_MISC", REG_MMIO, 0xd43, &mmGMCON_MISC[0], sizeof(mmGMCON_MISC)/sizeof(mmGMCON_MISC[0]), 0, 0 },
+	{ "mmGMCON_MISC2", REG_MMIO, 0xd44, &mmGMCON_MISC2[0], sizeof(mmGMCON_MISC2)/sizeof(mmGMCON_MISC2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0xd45, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0xd46, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0xd47, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0", REG_MMIO, 0xd48, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0xd49, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL0", REG_MMIO, 0xd4a, &mmGMCON_PERF_MON_CNTL0[0], sizeof(mmGMCON_PERF_MON_CNTL0)/sizeof(mmGMCON_PERF_MON_CNTL0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL1", REG_MMIO, 0xd4b, &mmGMCON_PERF_MON_CNTL1[0], sizeof(mmGMCON_PERF_MON_CNTL1)/sizeof(mmGMCON_PERF_MON_CNTL1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT0", REG_MMIO, 0xd4c, &mmGMCON_PERF_MON_RSLT0[0], sizeof(mmGMCON_PERF_MON_RSLT0)/sizeof(mmGMCON_PERF_MON_RSLT0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT1", REG_MMIO, 0xd4d, &mmGMCON_PERF_MON_RSLT1[0], sizeof(mmGMCON_PERF_MON_RSLT1)/sizeof(mmGMCON_PERF_MON_RSLT1[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_CONFIG", REG_MMIO, 0xd4e, &mmGMCON_PGFSM_CONFIG[0], sizeof(mmGMCON_PGFSM_CONFIG)/sizeof(mmGMCON_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_WRITE", REG_MMIO, 0xd4f, &mmGMCON_PGFSM_WRITE[0], sizeof(mmGMCON_PGFSM_WRITE)/sizeof(mmGMCON_PGFSM_WRITE[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_CLKSEL_D1", REG_SMC, 0xd5, &ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_CLKSEL_D1[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_READ", REG_MMIO, 0xd50, &mmGMCON_PGFSM_READ[0], sizeof(mmGMCON_PGFSM_READ)/sizeof(mmGMCON_PGFSM_READ[0]), 0, 0 },
+	{ "mmGMCON_MISC3", REG_MMIO, 0xd51, &mmGMCON_MISC3[0], sizeof(mmGMCON_MISC3)/sizeof(mmGMCON_MISC3[0]), 0, 0 },
+	{ "mmGMCON_MASK", REG_MMIO, 0xd52, &mmGMCON_MASK[0], sizeof(mmGMCON_MASK)/sizeof(mmGMCON_MASK[0]), 0, 0 },
+	{ "mmGMCON_LPT_TARGET", REG_MMIO, 0xd53, &mmGMCON_LPT_TARGET[0], sizeof(mmGMCON_LPT_TARGET)/sizeof(mmGMCON_LPT_TARGET[0]), 0, 0 },
+	{ "mmGMCON_DEBUG", REG_MMIO, 0xd5f, &mmGMCON_DEBUG[0], sizeof(mmGMCON_DEBUG)/sizeof(mmGMCON_DEBUG[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_CLKSEL_D1", REG_SMC, 0xd6, &ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_CLKSEL_D1", REG_SMC, 0xd7, &ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_CLKSEL_D1", REG_SMC, 0xd8, &ixMC_IO_DEBUG_DBI_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_DBI_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_SEQ_CNTL_3", REG_MMIO, 0xd80, &mmMC_SEQ_CNTL_3[0], sizeof(mmMC_SEQ_CNTL_3)/sizeof(mmMC_SEQ_CNTL_3[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CTRL", REG_MMIO, 0xd81, &mmMC_SEQ_G5PDX_CTRL[0], sizeof(mmMC_SEQ_G5PDX_CTRL)/sizeof(mmMC_SEQ_G5PDX_CTRL[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CTRL_LP", REG_MMIO, 0xd82, &mmMC_SEQ_G5PDX_CTRL_LP[0], sizeof(mmMC_SEQ_G5PDX_CTRL_LP)/sizeof(mmMC_SEQ_G5PDX_CTRL_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CMD0", REG_MMIO, 0xd83, &mmMC_SEQ_G5PDX_CMD0[0], sizeof(mmMC_SEQ_G5PDX_CMD0)/sizeof(mmMC_SEQ_G5PDX_CMD0[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CMD0_LP", REG_MMIO, 0xd84, &mmMC_SEQ_G5PDX_CMD0_LP[0], sizeof(mmMC_SEQ_G5PDX_CMD0_LP)/sizeof(mmMC_SEQ_G5PDX_CMD0_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CMD1", REG_MMIO, 0xd85, &mmMC_SEQ_G5PDX_CMD1[0], sizeof(mmMC_SEQ_G5PDX_CMD1)/sizeof(mmMC_SEQ_G5PDX_CMD1[0]), 0, 0 },
+	{ "mmMC_SEQ_G5PDX_CMD1_LP", REG_MMIO, 0xd86, &mmMC_SEQ_G5PDX_CMD1_LP[0], sizeof(mmMC_SEQ_G5PDX_CMD1_LP)/sizeof(mmMC_SEQ_G5PDX_CMD1_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_SREG_READ", REG_MMIO, 0xd87, &mmMC_SEQ_SREG_READ[0], sizeof(mmMC_SEQ_SREG_READ)/sizeof(mmMC_SEQ_SREG_READ[0]), 0, 0 },
+	{ "mmMC_SEQ_SREG_STATUS", REG_MMIO, 0xd88, &mmMC_SEQ_SREG_STATUS[0], sizeof(mmMC_SEQ_SREG_STATUS)/sizeof(mmMC_SEQ_SREG_STATUS[0]), 0, 0 },
+	{ "mmMC_SEQ_PHYREG_BCAST", REG_MMIO, 0xd89, &mmMC_SEQ_PHYREG_BCAST[0], sizeof(mmMC_SEQ_PHYREG_BCAST)/sizeof(mmMC_SEQ_PHYREG_BCAST[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_DVS_CTL", REG_MMIO, 0xd8a, &mmMC_SEQ_PMG_DVS_CTL[0], sizeof(mmMC_SEQ_PMG_DVS_CTL)/sizeof(mmMC_SEQ_PMG_DVS_CTL[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_DVS_CTL_LP", REG_MMIO, 0xd8b, &mmMC_SEQ_PMG_DVS_CTL_LP[0], sizeof(mmMC_SEQ_PMG_DVS_CTL_LP)/sizeof(mmMC_SEQ_PMG_DVS_CTL_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_DVS_CMD", REG_MMIO, 0xd8c, &mmMC_SEQ_PMG_DVS_CMD[0], sizeof(mmMC_SEQ_PMG_DVS_CMD)/sizeof(mmMC_SEQ_PMG_DVS_CMD[0]), 0, 0 },
+	{ "mmMC_SEQ_PMG_DVS_CMD_LP", REG_MMIO, 0xd8d, &mmMC_SEQ_PMG_DVS_CMD_LP[0], sizeof(mmMC_SEQ_PMG_DVS_CMD_LP)/sizeof(mmMC_SEQ_PMG_DVS_CMD_LP[0]), 0, 0 },
+	{ "mmMC_SEQ_DLL_STBY", REG_MMIO, 0xd8e, &mmMC_SEQ_DLL_STBY[0], sizeof(mmMC_SEQ_DLL_STBY)/sizeof(mmMC_SEQ_DLL_STBY[0]), 0, 0 },
+	{ "mmMC_SEQ_DLL_STBY_LP", REG_MMIO, 0xd8f, &mmMC_SEQ_DLL_STBY_LP[0], sizeof(mmMC_SEQ_DLL_STBY_LP)/sizeof(mmMC_SEQ_DLL_STBY_LP[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CLKSEL_D1", REG_SMC, 0xd9, &ixMC_IO_DEBUG_EDC_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_EDC_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_DLB_MISCCTRL0", REG_MMIO, 0xd90, &mmMC_DLB_MISCCTRL0[0], sizeof(mmMC_DLB_MISCCTRL0)/sizeof(mmMC_DLB_MISCCTRL0[0]), 0, 0 },
+	{ "mmMC_DLB_MISCCTRL1", REG_MMIO, 0xd91, &mmMC_DLB_MISCCTRL1[0], sizeof(mmMC_DLB_MISCCTRL1)/sizeof(mmMC_DLB_MISCCTRL1[0]), 0, 0 },
+	{ "mmMC_DLB_MISCCTRL2", REG_MMIO, 0xd92, &mmMC_DLB_MISCCTRL2[0], sizeof(mmMC_DLB_MISCCTRL2)/sizeof(mmMC_DLB_MISCCTRL2[0]), 0, 0 },
+	{ "mmMC_DLB_CONFIG0", REG_MMIO, 0xd93, &mmMC_DLB_CONFIG0[0], sizeof(mmMC_DLB_CONFIG0)/sizeof(mmMC_DLB_CONFIG0[0]), 0, 0 },
+	{ "mmMC_DLB_CONFIG1", REG_MMIO, 0xd94, &mmMC_DLB_CONFIG1[0], sizeof(mmMC_DLB_CONFIG1)/sizeof(mmMC_DLB_CONFIG1[0]), 0, 0 },
+	{ "mmMC_DLB_SETUP", REG_MMIO, 0xd95, &mmMC_DLB_SETUP[0], sizeof(mmMC_DLB_SETUP)/sizeof(mmMC_DLB_SETUP[0]), 0, 0 },
+	{ "mmMC_DLB_SETUPSWEEP", REG_MMIO, 0xd96, &mmMC_DLB_SETUPSWEEP[0], sizeof(mmMC_DLB_SETUPSWEEP)/sizeof(mmMC_DLB_SETUPSWEEP[0]), 0, 0 },
+	{ "mmMC_DLB_SETUPFIFO", REG_MMIO, 0xd97, &mmMC_DLB_SETUPFIFO[0], sizeof(mmMC_DLB_SETUPFIFO)/sizeof(mmMC_DLB_SETUPFIFO[0]), 0, 0 },
+	{ "mmMC_DLB_WRITE_MASK", REG_MMIO, 0xd98, &mmMC_DLB_WRITE_MASK[0], sizeof(mmMC_DLB_WRITE_MASK)/sizeof(mmMC_DLB_WRITE_MASK[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS", REG_MMIO, 0xd99, &mmMC_DLB_STATUS[0], sizeof(mmMC_DLB_STATUS)/sizeof(mmMC_DLB_STATUS[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC0", REG_MMIO, 0xd9a, &mmMC_DLB_STATUS_MISC0[0], sizeof(mmMC_DLB_STATUS_MISC0)/sizeof(mmMC_DLB_STATUS_MISC0[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC1", REG_MMIO, 0xd9b, &mmMC_DLB_STATUS_MISC1[0], sizeof(mmMC_DLB_STATUS_MISC1)/sizeof(mmMC_DLB_STATUS_MISC1[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC2", REG_MMIO, 0xd9c, &mmMC_DLB_STATUS_MISC2[0], sizeof(mmMC_DLB_STATUS_MISC2)/sizeof(mmMC_DLB_STATUS_MISC2[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC3", REG_MMIO, 0xd9d, &mmMC_DLB_STATUS_MISC3[0], sizeof(mmMC_DLB_STATUS_MISC3)/sizeof(mmMC_DLB_STATUS_MISC3[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC4", REG_MMIO, 0xd9e, &mmMC_DLB_STATUS_MISC4[0], sizeof(mmMC_DLB_STATUS_MISC4)/sizeof(mmMC_DLB_STATUS_MISC4[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC5", REG_MMIO, 0xd9f, &mmMC_DLB_STATUS_MISC5[0], sizeof(mmMC_DLB_STATUS_MISC5)/sizeof(mmMC_DLB_STATUS_MISC5[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_CLKSEL_D1", REG_SMC, 0xda, &ixMC_IO_DEBUG_WCK_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_WCK_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC6", REG_MMIO, 0xda0, &mmMC_DLB_STATUS_MISC6[0], sizeof(mmMC_DLB_STATUS_MISC6)/sizeof(mmMC_DLB_STATUS_MISC6[0]), 0, 0 },
+	{ "mmMC_DLB_STATUS_MISC7", REG_MMIO, 0xda1, &mmMC_DLB_STATUS_MISC7[0], sizeof(mmMC_DLB_STATUS_MISC7)/sizeof(mmMC_DLB_STATUS_MISC7[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CK_CLKSEL_D1", REG_SMC, 0xdb, &ixMC_IO_DEBUG_CK_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_CK_CLKSEL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRL_CLKSEL_D1", REG_SMC, 0xdc, &ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ADDRL_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_EN_RD", REG_MMIO, 0xdc0, &mmMC_ARB_HARSH_EN_RD[0], sizeof(mmMC_ARB_HARSH_EN_RD)/sizeof(mmMC_ARB_HARSH_EN_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_EN_WR", REG_MMIO, 0xdc1, &mmMC_ARB_HARSH_EN_WR[0], sizeof(mmMC_ARB_HARSH_EN_WR)/sizeof(mmMC_ARB_HARSH_EN_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI0_RD", REG_MMIO, 0xdc2, &mmMC_ARB_HARSH_TX_HI0_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI0_RD)/sizeof(mmMC_ARB_HARSH_TX_HI0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI0_WR", REG_MMIO, 0xdc3, &mmMC_ARB_HARSH_TX_HI0_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI0_WR)/sizeof(mmMC_ARB_HARSH_TX_HI0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI1_RD", REG_MMIO, 0xdc4, &mmMC_ARB_HARSH_TX_HI1_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI1_RD)/sizeof(mmMC_ARB_HARSH_TX_HI1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI1_WR", REG_MMIO, 0xdc5, &mmMC_ARB_HARSH_TX_HI1_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI1_WR)/sizeof(mmMC_ARB_HARSH_TX_HI1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO0_RD", REG_MMIO, 0xdc6, &mmMC_ARB_HARSH_TX_LO0_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO0_RD)/sizeof(mmMC_ARB_HARSH_TX_LO0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO0_WR", REG_MMIO, 0xdc7, &mmMC_ARB_HARSH_TX_LO0_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO0_WR)/sizeof(mmMC_ARB_HARSH_TX_LO0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO1_RD", REG_MMIO, 0xdc8, &mmMC_ARB_HARSH_TX_LO1_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO1_RD)/sizeof(mmMC_ARB_HARSH_TX_LO1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO1_WR", REG_MMIO, 0xdc9, &mmMC_ARB_HARSH_TX_LO1_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO1_WR)/sizeof(mmMC_ARB_HARSH_TX_LO1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD0_RD", REG_MMIO, 0xdca, &mmMC_ARB_HARSH_BWPERIOD0_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD0_WR", REG_MMIO, 0xdcb, &mmMC_ARB_HARSH_BWPERIOD0_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD1_RD", REG_MMIO, 0xdcc, &mmMC_ARB_HARSH_BWPERIOD1_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD1_WR", REG_MMIO, 0xdcd, &mmMC_ARB_HARSH_BWPERIOD1_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT0_RD", REG_MMIO, 0xdce, &mmMC_ARB_HARSH_BWCNT0_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT0_RD)/sizeof(mmMC_ARB_HARSH_BWCNT0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT0_WR", REG_MMIO, 0xdcf, &mmMC_ARB_HARSH_BWCNT0_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT0_WR)/sizeof(mmMC_ARB_HARSH_BWCNT0_WR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ADDRH_CLKSEL_D1", REG_SMC, 0xdd, &ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ADDRH_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT1_RD", REG_MMIO, 0xdd0, &mmMC_ARB_HARSH_BWCNT1_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT1_RD)/sizeof(mmMC_ARB_HARSH_BWCNT1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT1_WR", REG_MMIO, 0xdd1, &mmMC_ARB_HARSH_BWCNT1_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT1_WR)/sizeof(mmMC_ARB_HARSH_BWCNT1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT0_RD", REG_MMIO, 0xdd2, &mmMC_ARB_HARSH_SAT0_RD[0], sizeof(mmMC_ARB_HARSH_SAT0_RD)/sizeof(mmMC_ARB_HARSH_SAT0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT0_WR", REG_MMIO, 0xdd3, &mmMC_ARB_HARSH_SAT0_WR[0], sizeof(mmMC_ARB_HARSH_SAT0_WR)/sizeof(mmMC_ARB_HARSH_SAT0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT1_RD", REG_MMIO, 0xdd4, &mmMC_ARB_HARSH_SAT1_RD[0], sizeof(mmMC_ARB_HARSH_SAT1_RD)/sizeof(mmMC_ARB_HARSH_SAT1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT1_WR", REG_MMIO, 0xdd5, &mmMC_ARB_HARSH_SAT1_WR[0], sizeof(mmMC_ARB_HARSH_SAT1_WR)/sizeof(mmMC_ARB_HARSH_SAT1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_CTL_RD", REG_MMIO, 0xdd6, &mmMC_ARB_HARSH_CTL_RD[0], sizeof(mmMC_ARB_HARSH_CTL_RD)/sizeof(mmMC_ARB_HARSH_CTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_CTL_WR", REG_MMIO, 0xdd7, &mmMC_ARB_HARSH_CTL_WR[0], sizeof(mmMC_ARB_HARSH_CTL_WR)/sizeof(mmMC_ARB_HARSH_CTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PRIORITY1_RD", REG_MMIO, 0xdd8, &mmMC_ARB_GRUB_PRIORITY1_RD[0], sizeof(mmMC_ARB_GRUB_PRIORITY1_RD)/sizeof(mmMC_ARB_GRUB_PRIORITY1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PRIORITY1_WR", REG_MMIO, 0xdd9, &mmMC_ARB_GRUB_PRIORITY1_WR[0], sizeof(mmMC_ARB_GRUB_PRIORITY1_WR)/sizeof(mmMC_ARB_GRUB_PRIORITY1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PRIORITY2_RD", REG_MMIO, 0xdda, &mmMC_ARB_GRUB_PRIORITY2_RD[0], sizeof(mmMC_ARB_GRUB_PRIORITY2_RD)/sizeof(mmMC_ARB_GRUB_PRIORITY2_RD[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PRIORITY2_WR", REG_MMIO, 0xddb, &mmMC_ARB_GRUB_PRIORITY2_WR[0], sizeof(mmMC_ARB_GRUB_PRIORITY2_WR)/sizeof(mmMC_ARB_GRUB_PRIORITY2_WR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_CLKSEL_D1", REG_SMC, 0xde, &ixMC_IO_DEBUG_ACMD_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_ACMD_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_SPM", REG_MMIO, 0xde0, &mmMC_HUB_RDREQ_ISP_SPM[0], sizeof(mmMC_HUB_RDREQ_ISP_SPM)/sizeof(mmMC_HUB_RDREQ_ISP_SPM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_MPM", REG_MMIO, 0xde1, &mmMC_HUB_RDREQ_ISP_MPM[0], sizeof(mmMC_HUB_RDREQ_ISP_MPM)/sizeof(mmMC_HUB_RDREQ_ISP_MPM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_CCPU", REG_MMIO, 0xde2, &mmMC_HUB_RDREQ_ISP_CCPU[0], sizeof(mmMC_HUB_RDREQ_ISP_CCPU)/sizeof(mmMC_HUB_RDREQ_ISP_CCPU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_SPM", REG_MMIO, 0xde3, &mmMC_HUB_WDP_ISP_SPM[0], sizeof(mmMC_HUB_WDP_ISP_SPM)/sizeof(mmMC_HUB_WDP_ISP_SPM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_MPS", REG_MMIO, 0xde4, &mmMC_HUB_WDP_ISP_MPS[0], sizeof(mmMC_HUB_WDP_ISP_MPS)/sizeof(mmMC_HUB_WDP_ISP_MPS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_MPM", REG_MMIO, 0xde5, &mmMC_HUB_WDP_ISP_MPM[0], sizeof(mmMC_HUB_WDP_ISP_MPM)/sizeof(mmMC_HUB_WDP_ISP_MPM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_CCPU", REG_MMIO, 0xde6, &mmMC_HUB_WDP_ISP_CCPU[0], sizeof(mmMC_HUB_WDP_ISP_CCPU)/sizeof(mmMC_HUB_WDP_ISP_CCPU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDS", REG_MMIO, 0xde7, &mmMC_HUB_RDREQ_MCDS[0], sizeof(mmMC_HUB_RDREQ_MCDS)/sizeof(mmMC_HUB_RDREQ_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDT", REG_MMIO, 0xde8, &mmMC_HUB_RDREQ_MCDT[0], sizeof(mmMC_HUB_RDREQ_MCDT)/sizeof(mmMC_HUB_RDREQ_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDU", REG_MMIO, 0xde9, &mmMC_HUB_RDREQ_MCDU[0], sizeof(mmMC_HUB_RDREQ_MCDU)/sizeof(mmMC_HUB_RDREQ_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDV", REG_MMIO, 0xdea, &mmMC_HUB_RDREQ_MCDV[0], sizeof(mmMC_HUB_RDREQ_MCDV)/sizeof(mmMC_HUB_RDREQ_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDS", REG_MMIO, 0xdeb, &mmMC_HUB_WDP_MCDS[0], sizeof(mmMC_HUB_WDP_MCDS)/sizeof(mmMC_HUB_WDP_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDT", REG_MMIO, 0xdec, &mmMC_HUB_WDP_MCDT[0], sizeof(mmMC_HUB_WDP_MCDT)/sizeof(mmMC_HUB_WDP_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDU", REG_MMIO, 0xded, &mmMC_HUB_WDP_MCDU[0], sizeof(mmMC_HUB_WDP_MCDU)/sizeof(mmMC_HUB_WDP_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDV", REG_MMIO, 0xdee, &mmMC_HUB_WDP_MCDV[0], sizeof(mmMC_HUB_WDP_MCDV)/sizeof(mmMC_HUB_WDP_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDS", REG_MMIO, 0xdef, &mmMC_HUB_WRRET_MCDS[0], sizeof(mmMC_HUB_WRRET_MCDS)/sizeof(mmMC_HUB_WRRET_MCDS[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_CLKSEL_D1", REG_SMC, 0xdf, &ixMC_IO_DEBUG_CMD_CLKSEL_D1[0], sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D1)/sizeof(ixMC_IO_DEBUG_CMD_CLKSEL_D1[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDT", REG_MMIO, 0xdf0, &mmMC_HUB_WRRET_MCDT[0], sizeof(mmMC_HUB_WRRET_MCDT)/sizeof(mmMC_HUB_WRRET_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDU", REG_MMIO, 0xdf1, &mmMC_HUB_WRRET_MCDU[0], sizeof(mmMC_HUB_WRRET_MCDU)/sizeof(mmMC_HUB_WRRET_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDV", REG_MMIO, 0xdf2, &mmMC_HUB_WRRET_MCDV[0], sizeof(mmMC_HUB_WRRET_MCDV)/sizeof(mmMC_HUB_WRRET_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDW", REG_MMIO, 0xdf3, &mmMC_HUB_WDP_CREDITS_MCDW[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDW)/sizeof(mmMC_HUB_WDP_CREDITS_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDX", REG_MMIO, 0xdf4, &mmMC_HUB_WDP_CREDITS_MCDX[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDX)/sizeof(mmMC_HUB_WDP_CREDITS_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDY", REG_MMIO, 0xdf5, &mmMC_HUB_WDP_CREDITS_MCDY[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDY)/sizeof(mmMC_HUB_WDP_CREDITS_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDZ", REG_MMIO, 0xdf6, &mmMC_HUB_WDP_CREDITS_MCDZ[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDZ)/sizeof(mmMC_HUB_WDP_CREDITS_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDS", REG_MMIO, 0xdf7, &mmMC_HUB_WDP_CREDITS_MCDS[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDS)/sizeof(mmMC_HUB_WDP_CREDITS_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDT", REG_MMIO, 0xdf8, &mmMC_HUB_WDP_CREDITS_MCDT[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDT)/sizeof(mmMC_HUB_WDP_CREDITS_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDU", REG_MMIO, 0xdf9, &mmMC_HUB_WDP_CREDITS_MCDU[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDU)/sizeof(mmMC_HUB_WDP_CREDITS_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDV", REG_MMIO, 0xdfa, &mmMC_HUB_WDP_CREDITS_MCDV[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDV)/sizeof(mmMC_HUB_WDP_CREDITS_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BP2", REG_MMIO, 0xdfb, &mmMC_HUB_WDP_BP2[0], sizeof(mmMC_HUB_WDP_BP2)/sizeof(mmMC_HUB_WDP_BP2[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCE1", REG_MMIO, 0xdfc, &mmMC_HUB_RDREQ_VCE1[0], sizeof(mmMC_HUB_RDREQ_VCE1)/sizeof(mmMC_HUB_RDREQ_VCE1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCEU1", REG_MMIO, 0xdfd, &mmMC_HUB_RDREQ_VCEU1[0], sizeof(mmMC_HUB_RDREQ_VCEU1)/sizeof(mmMC_HUB_RDREQ_VCEU1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCE1", REG_MMIO, 0xdfe, &mmMC_HUB_WDP_VCE1[0], sizeof(mmMC_HUB_WDP_VCE1)/sizeof(mmMC_HUB_WDP_VCE1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCEU1", REG_MMIO, 0xdff, &mmMC_HUB_WDP_VCEU1[0], sizeof(mmMC_HUB_WDP_VCEU1)/sizeof(mmMC_HUB_WDP_VCEU1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_14", REG_SMC, 0xe, &ixMC_IO_DEBUG_UP_14[0], sizeof(ixMC_IO_DEBUG_UP_14)/sizeof(ixMC_IO_DEBUG_UP_14[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_OFSCAL_D0", REG_SMC, 0xe0, &ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_OFSCAL_D0", REG_SMC, 0xe1, &ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_OFSCAL_D0", REG_SMC, 0xe2, &ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_OFSCAL_D0", REG_SMC, 0xe3, &ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_OFSCAL_D0", REG_SMC, 0xe4, &ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_OFSCAL_D0", REG_SMC, 0xe5, &ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_OFSCAL_D0", REG_SMC, 0xe6, &ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_OFSCAL_D0", REG_SMC, 0xe7, &ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_OFSCAL_D0", REG_SMC, 0xe8, &ixMC_IO_DEBUG_DBI_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_OFSCAL_D0", REG_SMC, 0xe9, &ixMC_IO_DEBUG_EDC_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_OFSCAL_D0", REG_SMC, 0xea, &ixMC_IO_DEBUG_WCK_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0", REG_SMC, 0xeb, &ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0", REG_SMC, 0xec, &ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[0], sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0)/sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0", REG_SMC, 0xed, &ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[0], sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0)/sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_OFSCAL_D0", REG_SMC, 0xee, &ixMC_IO_DEBUG_ACMD_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_OFSCAL_D0", REG_SMC, 0xef, &ixMC_IO_DEBUG_CMD_OFSCAL_D0[0], sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D0)/sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D0[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_UP_15", REG_SMC, 0xf, &ixMC_IO_DEBUG_UP_15[0], sizeof(ixMC_IO_DEBUG_UP_15)/sizeof(ixMC_IO_DEBUG_UP_15[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0L_OFSCAL_D1", REG_SMC, 0xf0, &ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB0H_OFSCAL_D1", REG_SMC, 0xf1, &ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB0H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1L_OFSCAL_D1", REG_SMC, 0xf2, &ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB1H_OFSCAL_D1", REG_SMC, 0xf3, &ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB1H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2L_OFSCAL_D1", REG_SMC, 0xf4, &ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB2H_OFSCAL_D1", REG_SMC, 0xf5, &ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB2H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3L_OFSCAL_D1", REG_SMC, 0xf6, &ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3L_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DQB3H_OFSCAL_D1", REG_SMC, 0xf7, &ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DQB3H_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_DBI_OFSCAL_D1", REG_SMC, 0xf8, &ixMC_IO_DEBUG_DBI_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_DBI_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_OFSCAL_D1", REG_SMC, 0xf9, &ixMC_IO_DEBUG_EDC_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_EDC_OFSCAL_D1[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF0", REG_MMIO, 0xf980, &mmMC_VM_FB_SIZE_OFFSET_VF0[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF0)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF0[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF1", REG_MMIO, 0xf981, &mmMC_VM_FB_SIZE_OFFSET_VF1[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF1)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF1[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF2", REG_MMIO, 0xf982, &mmMC_VM_FB_SIZE_OFFSET_VF2[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF2)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF2[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF3", REG_MMIO, 0xf983, &mmMC_VM_FB_SIZE_OFFSET_VF3[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF3)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF3[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF4", REG_MMIO, 0xf984, &mmMC_VM_FB_SIZE_OFFSET_VF4[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF4)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF4[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF5", REG_MMIO, 0xf985, &mmMC_VM_FB_SIZE_OFFSET_VF5[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF5)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF5[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF6", REG_MMIO, 0xf986, &mmMC_VM_FB_SIZE_OFFSET_VF6[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF6)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF6[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF7", REG_MMIO, 0xf987, &mmMC_VM_FB_SIZE_OFFSET_VF7[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF7)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF7[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF8", REG_MMIO, 0xf988, &mmMC_VM_FB_SIZE_OFFSET_VF8[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF8)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF8[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF9", REG_MMIO, 0xf989, &mmMC_VM_FB_SIZE_OFFSET_VF9[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF9)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF9[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF10", REG_MMIO, 0xf98a, &mmMC_VM_FB_SIZE_OFFSET_VF10[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF10)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF10[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF11", REG_MMIO, 0xf98b, &mmMC_VM_FB_SIZE_OFFSET_VF11[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF11)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF11[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF12", REG_MMIO, 0xf98c, &mmMC_VM_FB_SIZE_OFFSET_VF12[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF12)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF12[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF13", REG_MMIO, 0xf98d, &mmMC_VM_FB_SIZE_OFFSET_VF13[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF13)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF13[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF14", REG_MMIO, 0xf98e, &mmMC_VM_FB_SIZE_OFFSET_VF14[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF14)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF14[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF15", REG_MMIO, 0xf98f, &mmMC_VM_FB_SIZE_OFFSET_VF15[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF15)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF15[0]), 0, 0 },
+	{ "mmMC_VM_NB_MMIOBASE", REG_MMIO, 0xf990, &mmMC_VM_NB_MMIOBASE[0], sizeof(mmMC_VM_NB_MMIOBASE)/sizeof(mmMC_VM_NB_MMIOBASE[0]), 0, 0 },
+	{ "mmMC_VM_NB_MMIOLIMIT", REG_MMIO, 0xf991, &mmMC_VM_NB_MMIOLIMIT[0], sizeof(mmMC_VM_NB_MMIOLIMIT)/sizeof(mmMC_VM_NB_MMIOLIMIT[0]), 0, 0 },
+	{ "mmMC_VM_NB_PCI_CTRL", REG_MMIO, 0xf992, &mmMC_VM_NB_PCI_CTRL[0], sizeof(mmMC_VM_NB_PCI_CTRL)/sizeof(mmMC_VM_NB_PCI_CTRL[0]), 0, 0 },
+	{ "mmMC_VM_NB_PCI_ARB", REG_MMIO, 0xf993, &mmMC_VM_NB_PCI_ARB[0], sizeof(mmMC_VM_NB_PCI_ARB)/sizeof(mmMC_VM_NB_PCI_ARB[0]), 0, 0 },
+	{ "mmMC_VM_NB_TOP_OF_DRAM_SLOT1", REG_MMIO, 0xf994, &mmMC_VM_NB_TOP_OF_DRAM_SLOT1[0], sizeof(mmMC_VM_NB_TOP_OF_DRAM_SLOT1)/sizeof(mmMC_VM_NB_TOP_OF_DRAM_SLOT1[0]), 0, 0 },
+	{ "mmMC_VM_NB_LOWER_TOP_OF_DRAM2", REG_MMIO, 0xf995, &mmMC_VM_NB_LOWER_TOP_OF_DRAM2[0], sizeof(mmMC_VM_NB_LOWER_TOP_OF_DRAM2)/sizeof(mmMC_VM_NB_LOWER_TOP_OF_DRAM2[0]), 0, 0 },
+	{ "mmMC_VM_NB_UPPER_TOP_OF_DRAM2", REG_MMIO, 0xf996, &mmMC_VM_NB_UPPER_TOP_OF_DRAM2[0], sizeof(mmMC_VM_NB_UPPER_TOP_OF_DRAM2)/sizeof(mmMC_VM_NB_UPPER_TOP_OF_DRAM2[0]), 0, 0 },
+	{ "mmMC_VM_NB_TOP_OF_DRAM3", REG_MMIO, 0xf997, &mmMC_VM_NB_TOP_OF_DRAM3[0], sizeof(mmMC_VM_NB_TOP_OF_DRAM3)/sizeof(mmMC_VM_NB_TOP_OF_DRAM3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_LO_0", REG_MMIO, 0xf998, &mmMC_VM_MARC_BASE_LO_0[0], sizeof(mmMC_VM_MARC_BASE_LO_0)/sizeof(mmMC_VM_MARC_BASE_LO_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_HI_0", REG_MMIO, 0xf999, &mmMC_VM_MARC_BASE_HI_0[0], sizeof(mmMC_VM_MARC_BASE_HI_0)/sizeof(mmMC_VM_MARC_BASE_HI_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_LO_0", REG_MMIO, 0xf99a, &mmMC_VM_MARC_RELOC_LO_0[0], sizeof(mmMC_VM_MARC_RELOC_LO_0)/sizeof(mmMC_VM_MARC_RELOC_LO_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_HI_0", REG_MMIO, 0xf99b, &mmMC_VM_MARC_RELOC_HI_0[0], sizeof(mmMC_VM_MARC_RELOC_HI_0)/sizeof(mmMC_VM_MARC_RELOC_HI_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_LO_0", REG_MMIO, 0xf99c, &mmMC_VM_MARC_LEN_LO_0[0], sizeof(mmMC_VM_MARC_LEN_LO_0)/sizeof(mmMC_VM_MARC_LEN_LO_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_HI_0", REG_MMIO, 0xf99d, &mmMC_VM_MARC_LEN_HI_0[0], sizeof(mmMC_VM_MARC_LEN_HI_0)/sizeof(mmMC_VM_MARC_LEN_HI_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_LO_1", REG_MMIO, 0xf99e, &mmMC_VM_MARC_BASE_LO_1[0], sizeof(mmMC_VM_MARC_BASE_LO_1)/sizeof(mmMC_VM_MARC_BASE_LO_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_HI_1", REG_MMIO, 0xf99f, &mmMC_VM_MARC_BASE_HI_1[0], sizeof(mmMC_VM_MARC_BASE_HI_1)/sizeof(mmMC_VM_MARC_BASE_HI_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_LO_1", REG_MMIO, 0xf9a0, &mmMC_VM_MARC_RELOC_LO_1[0], sizeof(mmMC_VM_MARC_RELOC_LO_1)/sizeof(mmMC_VM_MARC_RELOC_LO_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_HI_1", REG_MMIO, 0xf9a1, &mmMC_VM_MARC_RELOC_HI_1[0], sizeof(mmMC_VM_MARC_RELOC_HI_1)/sizeof(mmMC_VM_MARC_RELOC_HI_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_LO_1", REG_MMIO, 0xf9a2, &mmMC_VM_MARC_LEN_LO_1[0], sizeof(mmMC_VM_MARC_LEN_LO_1)/sizeof(mmMC_VM_MARC_LEN_LO_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_HI_1", REG_MMIO, 0xf9a3, &mmMC_VM_MARC_LEN_HI_1[0], sizeof(mmMC_VM_MARC_LEN_HI_1)/sizeof(mmMC_VM_MARC_LEN_HI_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_LO_2", REG_MMIO, 0xf9a4, &mmMC_VM_MARC_BASE_LO_2[0], sizeof(mmMC_VM_MARC_BASE_LO_2)/sizeof(mmMC_VM_MARC_BASE_LO_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_HI_2", REG_MMIO, 0xf9a5, &mmMC_VM_MARC_BASE_HI_2[0], sizeof(mmMC_VM_MARC_BASE_HI_2)/sizeof(mmMC_VM_MARC_BASE_HI_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_LO_2", REG_MMIO, 0xf9a6, &mmMC_VM_MARC_RELOC_LO_2[0], sizeof(mmMC_VM_MARC_RELOC_LO_2)/sizeof(mmMC_VM_MARC_RELOC_LO_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_HI_2", REG_MMIO, 0xf9a7, &mmMC_VM_MARC_RELOC_HI_2[0], sizeof(mmMC_VM_MARC_RELOC_HI_2)/sizeof(mmMC_VM_MARC_RELOC_HI_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_LO_2", REG_MMIO, 0xf9a8, &mmMC_VM_MARC_LEN_LO_2[0], sizeof(mmMC_VM_MARC_LEN_LO_2)/sizeof(mmMC_VM_MARC_LEN_LO_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_HI_2", REG_MMIO, 0xf9a9, &mmMC_VM_MARC_LEN_HI_2[0], sizeof(mmMC_VM_MARC_LEN_HI_2)/sizeof(mmMC_VM_MARC_LEN_HI_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_LO_3", REG_MMIO, 0xf9aa, &mmMC_VM_MARC_BASE_LO_3[0], sizeof(mmMC_VM_MARC_BASE_LO_3)/sizeof(mmMC_VM_MARC_BASE_LO_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_HI_3", REG_MMIO, 0xf9ab, &mmMC_VM_MARC_BASE_HI_3[0], sizeof(mmMC_VM_MARC_BASE_HI_3)/sizeof(mmMC_VM_MARC_BASE_HI_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_LO_3", REG_MMIO, 0xf9ac, &mmMC_VM_MARC_RELOC_LO_3[0], sizeof(mmMC_VM_MARC_RELOC_LO_3)/sizeof(mmMC_VM_MARC_RELOC_LO_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_HI_3", REG_MMIO, 0xf9ad, &mmMC_VM_MARC_RELOC_HI_3[0], sizeof(mmMC_VM_MARC_RELOC_HI_3)/sizeof(mmMC_VM_MARC_RELOC_HI_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_LO_3", REG_MMIO, 0xf9ae, &mmMC_VM_MARC_LEN_LO_3[0], sizeof(mmMC_VM_MARC_LEN_LO_3)/sizeof(mmMC_VM_MARC_LEN_LO_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_HI_3", REG_MMIO, 0xf9af, &mmMC_VM_MARC_LEN_HI_3[0], sizeof(mmMC_VM_MARC_LEN_HI_3)/sizeof(mmMC_VM_MARC_LEN_HI_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_CNTL", REG_MMIO, 0xf9b0, &mmMC_VM_MARC_CNTL[0], sizeof(mmMC_VM_MARC_CNTL)/sizeof(mmMC_VM_MARC_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL0", REG_MMIO, 0xf9b1, &mmMC_VM_MB_L1_TLS0_CNTL0[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL0)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL0[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR0", REG_MMIO, 0xf9b2, &mmMC_VM_MB_L1_TLS0_START_ADDR0[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR0)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR0[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR0", REG_MMIO, 0xf9b3, &mmMC_VM_MB_L1_TLS0_END_ADDR0[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR0)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR0[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL1", REG_MMIO, 0xf9b4, &mmMC_VM_MB_L1_TLS0_CNTL1[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL1)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL1[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR1", REG_MMIO, 0xf9b5, &mmMC_VM_MB_L1_TLS0_START_ADDR1[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR1)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR1[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR1", REG_MMIO, 0xf9b6, &mmMC_VM_MB_L1_TLS0_END_ADDR1[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR1)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR1[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL2", REG_MMIO, 0xf9b7, &mmMC_VM_MB_L1_TLS0_CNTL2[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL2)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL2[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR2", REG_MMIO, 0xf9b8, &mmMC_VM_MB_L1_TLS0_START_ADDR2[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR2)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR2[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR2", REG_MMIO, 0xf9b9, &mmMC_VM_MB_L1_TLS0_END_ADDR2[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR2)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR2[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL3", REG_MMIO, 0xf9ba, &mmMC_VM_MB_L1_TLS0_CNTL3[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL3)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL3[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR3", REG_MMIO, 0xf9bb, &mmMC_VM_MB_L1_TLS0_START_ADDR3[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR3)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR3[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR3", REG_MMIO, 0xf9bc, &mmMC_VM_MB_L1_TLS0_END_ADDR3[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR3)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR3[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL4", REG_MMIO, 0xf9bd, &mmMC_VM_MB_L1_TLS0_CNTL4[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL4)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL4[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR4", REG_MMIO, 0xf9be, &mmMC_VM_MB_L1_TLS0_START_ADDR4[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR4)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR4[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR4", REG_MMIO, 0xf9bf, &mmMC_VM_MB_L1_TLS0_END_ADDR4[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR4)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR4[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL5", REG_MMIO, 0xf9c0, &mmMC_VM_MB_L1_TLS0_CNTL5[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL5)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL5[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR5", REG_MMIO, 0xf9c1, &mmMC_VM_MB_L1_TLS0_START_ADDR5[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR5)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR5[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR5", REG_MMIO, 0xf9c2, &mmMC_VM_MB_L1_TLS0_END_ADDR5[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR5)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR5[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL6", REG_MMIO, 0xf9c3, &mmMC_VM_MB_L1_TLS0_CNTL6[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL6)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL6[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR6", REG_MMIO, 0xf9c4, &mmMC_VM_MB_L1_TLS0_START_ADDR6[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR6)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR6[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR6", REG_MMIO, 0xf9c5, &mmMC_VM_MB_L1_TLS0_END_ADDR6[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR6)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR6[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL7", REG_MMIO, 0xf9c6, &mmMC_VM_MB_L1_TLS0_CNTL7[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL7)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL7[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR7", REG_MMIO, 0xf9c7, &mmMC_VM_MB_L1_TLS0_START_ADDR7[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR7)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR7[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR7", REG_MMIO, 0xf9c8, &mmMC_VM_MB_L1_TLS0_END_ADDR7[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR7)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR7[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_CNTL8", REG_MMIO, 0xf9c9, &mmMC_VM_MB_L1_TLS0_CNTL8[0], sizeof(mmMC_VM_MB_L1_TLS0_CNTL8)/sizeof(mmMC_VM_MB_L1_TLS0_CNTL8[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_START_ADDR8", REG_MMIO, 0xf9ca, &mmMC_VM_MB_L1_TLS0_START_ADDR8[0], sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR8)/sizeof(mmMC_VM_MB_L1_TLS0_START_ADDR8[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_END_ADDR8", REG_MMIO, 0xf9cb, &mmMC_VM_MB_L1_TLS0_END_ADDR8[0], sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR8)/sizeof(mmMC_VM_MB_L1_TLS0_END_ADDR8[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS", REG_MMIO, 0xf9cc, &mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS[0], sizeof(mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS)/sizeof(mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR", REG_MMIO, 0xf9cd, &mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR[0], sizeof(mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR)/sizeof(mmMC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_WCK_OFSCAL_D1", REG_SMC, 0xfa, &ixMC_IO_DEBUG_WCK_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_WCK_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1", REG_SMC, 0xfb, &ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1", REG_SMC, 0xfc, &ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[0], sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1)/sizeof(ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1", REG_SMC, 0xfd, &ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[0], sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1)/sizeof(ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_ACMD_OFSCAL_D1", REG_SMC, 0xfe, &ixMC_IO_DEBUG_ACMD_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_ACMD_OFSCAL_D1[0]), 0, 0 },
+	{ "ixMC_IO_DEBUG_CMD_OFSCAL_D1", REG_SMC, 0xff, &ixMC_IO_DEBUG_CMD_OFSCAL_D1[0], sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D1)/sizeof(ixMC_IO_DEBUG_CMD_OFSCAL_D1[0]), 0, 0 },
diff --git a/src/lib/ip/gmc82.c b/src/lib/ip/gmc82.c
new file mode 100644
index 0000000..0710b1b
--- /dev/null
+++ b/src/lib/ip/gmc82.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "gmc82_bits.i"
+
+static const struct umr_reg gmc82_registers[] = {
+#include "gmc82_regs.i"
+};
+
+struct umr_ip_block *umr_create_gmc82(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "gmc82";
+	ip->no_regs = sizeof(gmc82_registers)/sizeof(gmc82_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(gmc82_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, gmc82_registers, sizeof(gmc82_registers));
+	return ip;
+}
diff --git a/src/lib/ip/gmc82_bits.i b/src/lib/ip/gmc82_bits.i
new file mode 100644
index 0000000..d0c2bfe
--- /dev/null
+++ b/src/lib/ip/gmc82_bits.i
@@ -0,0 +1,5463 @@
+static struct umr_bitfield mmVM_L2_CNTL[] = {
+	 { "ENABLE_L2_CACHE", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L2_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_PTE_ENDIAN_SWAP_MODE", 2, 3, &umr_bitfield_default },
+	 { "L2_CACHE_PDE_ENDIAN_SWAP_MODE", 4, 5, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_TAG_GENERATION_MODE", 8, 8, &umr_bitfield_default },
+	 { "ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE", 9, 9, &umr_bitfield_default },
+	 { "ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE", 10, 10, &umr_bitfield_default },
+	 { "ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY", 11, 11, &umr_bitfield_default },
+	 { "L2_PDE0_CACHE_SPLIT_MODE", 12, 14, &umr_bitfield_default },
+	 { "EFFECTIVE_L2_QUEUE_SIZE", 15, 17, &umr_bitfield_default },
+	 { "PDE_FAULT_CLASSIFICATION", 18, 18, &umr_bitfield_default },
+	 { "CONTEXT1_IDENTITY_ACCESS_MODE", 19, 20, &umr_bitfield_default },
+	 { "IDENTITY_MODE_FRAGMENT_SIZE", 21, 25, &umr_bitfield_default },
+	 { "L2_CACHE_4K_SWAP_TAG_INDEX_LSBS", 26, 27, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL2[] = {
+	 { "INVALIDATE_ALL_L1_TLBS", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_L2_CACHE", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_BIGK_CACHE_OPTIMIZATION", 22, 22, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_VMID_MODE", 23, 25, &umr_bitfield_default },
+	 { "INVALIDATE_CACHE_MODE", 26, 27, &umr_bitfield_default },
+	 { "PDE_CACHE_EFFECTIVE_SIZE", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL3[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 8, 12, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FRAGMENT_SIZE", 15, 19, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_ASSOCIATIVITY", 20, 20, &umr_bitfield_default },
+	 { "L2_CACHE_4K_EFFECTIVE_SIZE", 21, 23, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_EFFECTIVE_SIZE", 24, 27, &umr_bitfield_default },
+	 { "L2_CACHE_4K_FORCE_MISS", 28, 28, &umr_bitfield_default },
+	 { "L2_CACHE_BIGK_FORCE_MISS", 29, 29, &umr_bitfield_default },
+	 { "PDE_CACHE_FORCE_MISS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_STATUS[] = {
+	 { "L2_BUSY", 0, 0, &umr_bitfield_default },
+	 { "CONTEXT_DOMAIN_BUSY", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL[] = {
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL[] = {
+	 { "ENABLE_CONTEXT", 0, 0, &umr_bitfield_default },
+	 { "PAGE_TABLE_DEPTH", 1, 2, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 3, 3, &umr_bitfield_default },
+	 { "RANGE_PROTECTION_FAULT_ENABLE_DEFAULT", 4, 4, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT", 6, 6, &umr_bitfield_default },
+	 { "DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT", 7, 7, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT", 9, 9, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_DEFAULT", 10, 10, &umr_bitfield_default },
+	 { "PDE0_PROTECTION_FAULT_ENABLE_SAVE", 11, 11, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_INTERRUPT", 12, 12, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_DEFAULT", 13, 13, &umr_bitfield_default },
+	 { "VALID_PROTECTION_FAULT_ENABLE_SAVE", 14, 14, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_INTERRUPT", 15, 15, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_DEFAULT", 16, 16, &umr_bitfield_default },
+	 { "READ_PROTECTION_FAULT_ENABLE_SAVE", 17, 17, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT", 18, 18, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_DEFAULT", 19, 19, &umr_bitfield_default },
+	 { "WRITE_PROTECTION_FAULT_ENABLE_SAVE", 20, 20, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT", 21, 21, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT", 22, 22, &umr_bitfield_default },
+	 { "EXECUTE_PROTECTION_FAULT_ENABLE_SAVE", 23, 23, &umr_bitfield_default },
+	 { "PAGE_TABLE_BLOCK_SIZE", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_CNTL[] = {
+	 { "DUMMY_PAGE_FAULT_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "DUMMY_PAGE_ADDRESS_LOGICAL", 1, 1, &umr_bitfield_default },
+	 { "DUMMY_PAGE_COMPARE_MASK", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DUMMY_PAGE_FAULT_ADDR[] = {
+	 { "DUMMY_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_CNTL2[] = {
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_CNTL2[] = {
+	 { "CLEAR_PROTECTION_FAULT_STATUS_ADDR", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT", 1, 1, &umr_bitfield_default },
+	 { "ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES", 3, 3, &umr_bitfield_default },
+	 { "WAIT_FOR_IDLE_WHEN_INVALIDATE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_REQUEST[] = {
+	 { "INVALIDATE_DOMAIN_0", 0, 0, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_1", 1, 1, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_2", 2, 2, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_3", 3, 3, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_4", 4, 4, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_5", 5, 5, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_6", 6, 6, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_7", 7, 7, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_8", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_9", 9, 9, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_10", 10, 10, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_11", 11, 11, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_12", 12, 12, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_13", 13, 13, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_14", 14, 14, &umr_bitfield_default },
+	 { "INVALIDATE_DOMAIN_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_INVALIDATE_RESPONSE[] = {
+	 { "DOMAIN_INVALIDATED_0", 0, 0, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_1", 1, 1, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_2", 2, 2, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_3", 3, 3, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_4", 4, 4, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_5", 5, 5, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_6", 6, 6, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_7", 7, 7, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_8", 8, 8, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_9", 9, 9, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_10", 10, 10, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_11", 11, 11, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_12", 12, 12, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_13", 13, 13, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_14", 14, 14, &umr_bitfield_default },
+	 { "DOMAIN_INVALIDATED_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE0_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE1_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE2_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_APERTURE3_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_PRT_CNTL[] = {
+	 { "CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS", 0, 0, &umr_bitfield_default },
+	 { "TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS", 1, 1, &umr_bitfield_default },
+	 { "L2_CACHE_STORE_INVALID_ENTRIES", 2, 2, &umr_bitfield_default },
+	 { "L1_TLB_STORE_INVALID_ENTRIES", 3, 3, &umr_bitfield_default },
+	 { "CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS", 4, 4, &umr_bitfield_default },
+	 { "TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+	 { "MASK_PDE0_FAULT", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXTS_DISABLE[] = {
+	 { "DISABLE_CONTEXT_0", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_1", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_2", 2, 2, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_3", 3, 3, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_4", 4, 4, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_5", 5, 5, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_6", 6, 6, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_7", 7, 7, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_8", 8, 8, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_9", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_10", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_11", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_12", 12, 12, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_13", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_14", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_CONTEXT_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 20, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+	 { "ATOMIC", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[] = {
+	 { "PROTECTIONS", 0, 7, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID", 12, 20, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_RW", 24, 24, &umr_bitfield_default },
+	 { "VMID", 25, 28, &umr_bitfield_default },
+	 { "ATOMIC", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[] = {
+	 { "NAME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[] = {
+	 { "NAME", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[] = {
+	 { "LOGICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_ADDR", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_FAULT_CLIENT_ID[] = {
+	 { "MEMORY_CLIENT", 0, 8, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_MASK", 9, 17, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID_MSB", 18, 18, &umr_bitfield_default },
+	 { "MEMORY_CLIENT_ID_MASK_MSB", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_DEBUG[] = {
+	 { "FLAGS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CG[] = {
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+	 { "OVERRIDE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKA[] = {
+	 { "BANK_SELECT_MASK", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_MASKB[] = {
+	 { "BANK_SELECT_MASK", 0, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[] = {
+	 { "PHYSICAL_PAGE_OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_CNTL4[] = {
+	 { "L2_CACHE_4K_PARTITION_COUNT", 0, 5, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL", 6, 6, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED", 7, 7, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP", 8, 8, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL", 9, 9, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED", 10, 10, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP", 11, 11, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL", 12, 12, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED", 13, 13, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP", 14, 14, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL", 15, 15, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED", 16, 16, &umr_bitfield_default },
+	 { "VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVM_L2_BANK_SELECT_RESERVED_CID[] = {
+	 { "RESERVED_READ_CLIENT_ID", 0, 8, &umr_bitfield_default },
+	 { "RESERVED_WRITE_CLIENT_ID", 10, 18, &umr_bitfield_default },
+	 { "ENABLE", 20, 20, &umr_bitfield_default },
+	 { "RESERVED_CACHE_INVALIDATION_MODE", 24, 24, &umr_bitfield_default },
+	 { "RESERVED_CACHE_PRIVATE_INVALIDATION", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUFMGR_SW_CONTROL[] = {
+	 { "MCIF_WB_BUFMGR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_DUALSIZE_REQ", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_INT_ACK", 5, 5, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_LOCK", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_P_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUFMGR_CUR_LINE_R[] = {
+	 { "MCIF_WB_BUFMGR_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUFMGR_STATUS[] = {
+	 { "MCIF_WB_BUFMGR_VCE_INT_STATUS", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SW_INT_STATUS", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_CUR_BUF", 4, 6, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_DUALSIZE_STATUS", 7, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_CUR_LINE_L", 12, 24, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_NEXT_BUF", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_PITCH[] = {
+	 { "MCIF_WB_BUF_LUMA_PITCH", 8, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_CHROMA_PITCH", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_STATUS[] = {
+	 { "MCIF_WB_BUF_1_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_VCE_LOCKED", 2, 2, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_MODE", 5, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_FIELD", 15, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_CUR_LINE_L", 16, 28, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_STATUS2[] = {
+	 { "MCIF_WB_BUF_1_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_NEW_CONTENT", 13, 13, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_1_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_STATUS[] = {
+	 { "MCIF_WB_BUF_2_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_VCE_LOCKED", 2, 2, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_MODE", 5, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_FIELD", 15, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_CUR_LINE_L", 16, 28, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_STATUS2[] = {
+	 { "MCIF_WB_BUF_2_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_NEW_CONTENT", 13, 13, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_2_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_STATUS[] = {
+	 { "MCIF_WB_BUF_3_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_VCE_LOCKED", 2, 2, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_MODE", 5, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_FIELD", 15, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_CUR_LINE_L", 16, 28, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_STATUS2[] = {
+	 { "MCIF_WB_BUF_3_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_NEW_CONTENT", 13, 13, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_3_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_STATUS[] = {
+	 { "MCIF_WB_BUF_4_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_SW_LOCKED", 1, 1, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_VCE_LOCKED", 2, 2, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_OVERFLOW", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_MODE", 5, 7, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_BUFTAG", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_NXT_BUF", 12, 14, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_FIELD", 15, 15, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_CUR_LINE_L", 16, 28, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_LONG_LINE_ERROR", 29, 29, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_SHORT_LINE_ERROR", 30, 30, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_FRAME_LENGTH_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_STATUS2[] = {
+	 { "MCIF_WB_BUF_4_CUR_LINE_R", 0, 12, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_NEW_CONTENT", 13, 13, &umr_bitfield_default },
+	 { "MCIF_WB_BUF_4_COLOR_DEPTH", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_ARBITRATION_CONTROL[] = {
+	 { "MCIF_WB_CLIENT_ARBITRATION_SLICE", 0, 1, &umr_bitfield_default },
+	 { "MCIF_WB_TIME_PER_PIXEL", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_URGENCY_WATERMARK[] = {
+	 { "MCIF_WB_CLIENT0_URGENCY_WATERMARK", 0, 15, &umr_bitfield_default },
+	 { "MCIF_WB_CLIENT1_URGENCY_WATERMARK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_TEST_DEBUG_INDEX[] = {
+	 { "MCIF_WB_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "MCIF_WB_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_TEST_DEBUG_DATA[] = {
+	 { "MCIF_WB_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_ADDR_Y[] = {
+	 { "MCIF_WB_BUF_1_ADDR_Y", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_ADDR_Y_OFFSET[] = {
+	 { "MCIF_WB_BUF_1_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_ADDR_C[] = {
+	 { "MCIF_WB_BUF_1_ADDR_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_1_ADDR_C_OFFSET[] = {
+	 { "MCIF_WB_BUF_1_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_ADDR_Y[] = {
+	 { "MCIF_WB_BUF_2_ADDR_Y", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_ADDR_Y_OFFSET[] = {
+	 { "MCIF_WB_BUF_2_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_ADDR_C[] = {
+	 { "MCIF_WB_BUF_2_ADDR_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_2_ADDR_C_OFFSET[] = {
+	 { "MCIF_WB_BUF_2_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_ADDR_Y[] = {
+	 { "MCIF_WB_BUF_3_ADDR_Y", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_ADDR_Y_OFFSET[] = {
+	 { "MCIF_WB_BUF_3_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_ADDR_C[] = {
+	 { "MCIF_WB_BUF_3_ADDR_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_3_ADDR_C_OFFSET[] = {
+	 { "MCIF_WB_BUF_3_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_ADDR_Y[] = {
+	 { "MCIF_WB_BUF_4_ADDR_Y", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_ADDR_Y_OFFSET[] = {
+	 { "MCIF_WB_BUF_4_ADDR_Y_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_ADDR_C[] = {
+	 { "MCIF_WB_BUF_4_ADDR_C", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUF_4_ADDR_C_OFFSET[] = {
+	 { "MCIF_WB_BUF_4_ADDR_C_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_BUFMGR_VCE_CONTROL[] = {
+	 { "MCIF_WB_BUFMGR_VCE_LOCK_IGNORE", 0, 0, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_VCE_INT_EN", 4, 4, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_VCE_INT_ACK", 5, 5, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_VCE_SLICE_INT_EN", 6, 6, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_VCE_LOCK", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_BUFMGR_SLICE_SIZE", 16, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMCIF_WB_HVVMID_CONTROL[] = {
+	 { "MCIF_WB_DEFAULT_VMID", 8, 11, &umr_bitfield_default },
+	 { "MCIF_WB_ALLOWED_VMID_MASK", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER2_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER3_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_PERFCOUNTER_LO[] = {
+	 { "COUNTER_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_PERFCOUNTER_HI[] = {
+	 { "COUNTER_HI", 0, 15, &umr_bitfield_default },
+	 { "COMPARE_VALUE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_PERFCOUNTER0_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_PERFCOUNTER1_CFG[] = {
+	 { "PERF_SEL", 0, 7, &umr_bitfield_default },
+	 { "PERF_SEL_END", 8, 15, &umr_bitfield_default },
+	 { "PERF_MODE", 24, 27, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CLEAR", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_PERFCOUNTER_RSLT_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 3, &umr_bitfield_default },
+	 { "START_TRIGGER", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIGGER", 16, 23, &umr_bitfield_default },
+	 { "ENABLE_ANY", 24, 24, &umr_bitfield_default },
+	 { "CLEAR_ALL", 25, 25, &umr_bitfield_default },
+	 { "STOP_ALL_ON_SATURATE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG[] = {
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCDS_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCDT_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCDU_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCDV_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MCC_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHMAP[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "NOOFCHAN", 12, 15, &umr_bitfield_default },
+	 { "CHAN3", 16, 19, &umr_bitfield_default },
+	 { "CHAN4", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHREMAP[] = {
+	 { "CHAN0", 0, 3, &umr_bitfield_default },
+	 { "CHAN1", 4, 7, &umr_bitfield_default },
+	 { "CHAN2", 8, 11, &umr_bitfield_default },
+	 { "CHAN3", 12, 15, &umr_bitfield_default },
+	 { "CHAN4", 16, 19, &umr_bitfield_default },
+	 { "CHAN5", 20, 23, &umr_bitfield_default },
+	 { "CHAN6", 24, 27, &umr_bitfield_default },
+	 { "CHAN7", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "SH", 4, 7, &umr_bitfield_default },
+	 { "IA", 8, 11, &umr_bitfield_default },
+	 { "ACPG", 12, 15, &umr_bitfield_default },
+	 { "ACPO", 16, 19, &umr_bitfield_default },
+	 { "XDMAM", 20, 23, &umr_bitfield_default },
+	 { "ISP", 24, 27, &umr_bitfield_default },
+	 { "VP8", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_GFX[] = {
+	 { "CP", 0, 3, &umr_bitfield_default },
+	 { "SH", 4, 7, &umr_bitfield_default },
+	 { "ACPG", 8, 11, &umr_bitfield_default },
+	 { "ACPO", 12, 15, &umr_bitfield_default },
+	 { "ISP", 16, 19, &umr_bitfield_default },
+	 { "VP8", 20, 23, &umr_bitfield_default },
+	 { "XDMA", 24, 27, &umr_bitfield_default },
+	 { "XDMAM", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_SYS[] = {
+	 { "RLC", 0, 3, &umr_bitfield_default },
+	 { "VMC", 4, 7, &umr_bitfield_default },
+	 { "SDMA1", 8, 11, &umr_bitfield_default },
+	 { "DMIF", 12, 15, &umr_bitfield_default },
+	 { "MCIF", 16, 19, &umr_bitfield_default },
+	 { "SMU", 20, 23, &umr_bitfield_default },
+	 { "VCE0", 24, 27, &umr_bitfield_default },
+	 { "VCE1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_SYS[] = {
+	 { "IH", 0, 3, &umr_bitfield_default },
+	 { "MCIF", 4, 7, &umr_bitfield_default },
+	 { "RLC", 8, 11, &umr_bitfield_default },
+	 { "SAMMSP", 12, 15, &umr_bitfield_default },
+	 { "SMU", 16, 19, &umr_bitfield_default },
+	 { "SDMA1", 20, 23, &umr_bitfield_default },
+	 { "VCE0", 24, 27, &umr_bitfield_default },
+	 { "VCE1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_OTH[] = {
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "SDMA0", 4, 7, &umr_bitfield_default },
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "UVD_EXT1", 24, 27, &umr_bitfield_default },
+	 { "SAMMSP", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_OTH[] = {
+	 { "UVD_EXT0", 0, 3, &umr_bitfield_default },
+	 { "SDMA0", 4, 7, &umr_bitfield_default },
+	 { "HDP", 8, 11, &umr_bitfield_default },
+	 { "SEM", 12, 15, &umr_bitfield_default },
+	 { "UMC", 16, 19, &umr_bitfield_default },
+	 { "UVD", 20, 23, &umr_bitfield_default },
+	 { "XDP", 24, 27, &umr_bitfield_default },
+	 { "UVD_EXT1", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_LOCATION[] = {
+	 { "FB_BASE", 0, 15, &umr_bitfield_default },
+	 { "FB_TOP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_TOP[] = {
+	 { "AGP_TOP", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BOT[] = {
+	 { "AGP_BOT", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_AGP_BASE[] = {
+	 { "AGP_BASE", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[] = {
+	 { "LOGICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[] = {
+	 { "PHYSICAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_CNTL[] = {
+	 { "DC_WRITE_HIT_REGION_0_MODE", 0, 1, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_1_MODE", 2, 3, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_2_MODE", 4, 5, &umr_bitfield_default },
+	 { "DC_WRITE_HIT_REGION_3_MODE", 6, 7, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_LOCAL", 8, 8, &umr_bitfield_default },
+	 { "DC_MEMORY_WRITE_SYSTEM", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[] = {
+	 { "PHYSICAL_ADDRESS", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MX_L1_TLB_CNTL[] = {
+	 { "ENABLE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_L1_FRAGMENT_PROCESSING", 1, 1, &umr_bitfield_default },
+	 { "SYSTEM_ACCESS_MODE", 3, 4, &umr_bitfield_default },
+	 { "SYSTEM_APERTURE_UNMAPPED_ACCESS", 5, 5, &umr_bitfield_default },
+	 { "ENABLE_ADVANCED_DRIVER_MODEL", 6, 6, &umr_bitfield_default },
+	 { "ECO_BITS", 7, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_OFFSET[] = {
+	 { "FB_OFFSET", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_STEERING[] = {
+	 { "DEFAULT_STEERING", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_CHREMAP2[] = {
+	 { "CHAN8", 0, 3, &umr_bitfield_default },
+	 { "CHAN9", 4, 7, &umr_bitfield_default },
+	 { "CHAN10", 8, 11, &umr_bitfield_default },
+	 { "CHAN11", 12, 15, &umr_bitfield_default },
+	 { "CHAN12", 16, 19, &umr_bitfield_default },
+	 { "CHAN13", 20, 23, &umr_bitfield_default },
+	 { "CHAN14", 24, 27, &umr_bitfield_default },
+	 { "CHAN15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_ACTIVE_FCN_ID[] = {
+	 { "VFID", 0, 3, &umr_bitfield_default },
+	 { "VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCD6_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCD7_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MC_RD_ENABLE_SUB", 11, 11, &umr_bitfield_default },
+	 { "ARB0_WR_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "ARB1_WR_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "MCD_INDEX_MODE_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG_MCD[] = {
+	 { "MCD0_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCD1_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCD2_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCD3_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MCD4_WR_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCD5_WR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MCD6_WR_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "MCD7_WR_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 8, 10, &umr_bitfield_default },
+	 { "MC_RD_ENABLE_SUB", 11, 11, &umr_bitfield_default },
+	 { "INDEX", 13, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_MEM_POWER_LS[] = {
+	 { "LS_SETUP", 0, 5, &umr_bitfield_default },
+	 { "LS_HOLD", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_SHARED_BLACKOUT_CNTL[] = {
+	 { "BLACKOUT_MODE", 0, 2, &umr_bitfield_default },
+	 { "BLACKOUT_SEQ_FREE", 3, 3, &umr_bitfield_default },
+	 { "BLACKOUT_MCD_NUM", 4, 11, &umr_bitfield_default },
+	 { "FREE_TIE_HIGH", 12, 12, &umr_bitfield_default },
+	 { "SRBM_DUMMY_READ_RETURN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_POWER[] = {
+	 { "SRBM_GATE_OVERRIDE", 2, 2, &umr_bitfield_default },
+	 { "PM_BLACKOUT_CNTL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_HUB_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_VM_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_SIP_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_STATUS[] = {
+	 { "OUTSTANDING_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_ATOMIC", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDREQ", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_RDRET", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRREQ", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_WRRET", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_ATOMIC_REQ", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_HUB_ATOMIC_RET", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_READ", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_WRITE", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_RPB_ATOMIC", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_READ", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_WRITE", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_MCD_ATOMIC", 14, 14, &umr_bitfield_default },
+	 { "RPB_BUSY", 15, 15, &umr_bitfield_default },
+	 { "WRITE_DEADLOCK_WARNING", 16, 16, &umr_bitfield_default },
+	 { "READ_DEADLOCK_WARNING", 17, 17, &umr_bitfield_default },
+	 { "ATOMIC_DEADLOCK_WARNING", 18, 18, &umr_bitfield_default },
+	 { "GFX_BUSY", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_OVERRIDE[] = {
+	 { "IDLE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_FRAMING[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CNTL[] = {
+	 { "JUMPAHEAD_GBL0", 1, 1, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_INTERNAL", 3, 3, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "DEBUG_REG", 5, 12, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_INTERNAL", 15, 15, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 16, 16, &umr_bitfield_default },
+	 { "LCLWRREQ_BYPASS", 17, 17, &umr_bitfield_default },
+	 { "DISP_WAIT_EOP", 18, 18, &umr_bitfield_default },
+	 { "MCD_WAIT_EOP", 19, 19, &umr_bitfield_default },
+	 { "SIP_WAIT_EOP", 20, 20, &umr_bitfield_default },
+	 { "UVD_VCE_WRITE_PRI_EN", 21, 21, &umr_bitfield_default },
+	 { "WRITE_PRI_EN", 22, 22, &umr_bitfield_default },
+	 { "IH_PHYSADDR_ENABLE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ERR[] = {
+	 { "MGPU1_TARG_SYS", 0, 0, &umr_bitfield_default },
+	 { "MGPU2_TARG_SYS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RDRET", 1, 17, &umr_bitfield_default },
+	 { "WRREQ", 18, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_STATUS[] = {
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDS_RD_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDT_RD_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDU_RD_AVAIL", 7, 7, &umr_bitfield_default },
+	 { "MCDV_RD_AVAIL", 8, 8, &umr_bitfield_default },
+	 { "MCDW_WR_AVAIL", 9, 9, &umr_bitfield_default },
+	 { "MCDX_WR_AVAIL", 10, 10, &umr_bitfield_default },
+	 { "MCDY_WR_AVAIL", 11, 11, &umr_bitfield_default },
+	 { "MCDZ_WR_AVAIL", 12, 12, &umr_bitfield_default },
+	 { "MCDS_WR_AVAIL", 13, 13, &umr_bitfield_default },
+	 { "MCDT_WR_AVAIL", 14, 14, &umr_bitfield_default },
+	 { "MCDU_WR_AVAIL", 15, 15, &umr_bitfield_default },
+	 { "MCDV_WR_AVAIL", 16, 16, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 17, 17, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 18, 18, &umr_bitfield_default },
+	 { "GBL0_BYPASS_STOR_FULL", 19, 19, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 20, 20, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 21, 21, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_STATUS[] = {
+	 { "SIP_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDW_RD_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDX_RD_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDY_RD_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDZ_RD_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDS_RD_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDT_RD_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDU_RD_AVAIL", 7, 7, &umr_bitfield_default },
+	 { "MCDV_RD_AVAIL", 8, 8, &umr_bitfield_default },
+	 { "GBL0_VM_FULL", 9, 9, &umr_bitfield_default },
+	 { "GBL0_STOR_FULL", 10, 10, &umr_bitfield_default },
+	 { "GBL0_BYPASS_STOR_FULL", 11, 11, &umr_bitfield_default },
+	 { "GBL1_VM_FULL", 12, 12, &umr_bitfield_default },
+	 { "GBL1_STOR_FULL", 13, 13, &umr_bitfield_default },
+	 { "GBL1_BYPASS_STOR_FULL", 14, 14, &umr_bitfield_default },
+	 { "PWRXPRESS_ERR", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_STATUS[] = {
+	 { "MCDW_AVAIL", 0, 0, &umr_bitfield_default },
+	 { "MCDX_AVAIL", 1, 1, &umr_bitfield_default },
+	 { "MCDY_AVAIL", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_AVAIL", 3, 3, &umr_bitfield_default },
+	 { "MCDS_AVAIL", 4, 4, &umr_bitfield_default },
+	 { "MCDT_AVAIL", 5, 5, &umr_bitfield_default },
+	 { "MCDU_AVAIL", 6, 6, &umr_bitfield_default },
+	 { "MCDV_AVAIL", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CNTL[] = {
+	 { "REMOTE_BLACKOUT", 0, 0, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL0", 2, 2, &umr_bitfield_default },
+	 { "JUMPAHEAD_GBL1", 3, 3, &umr_bitfield_default },
+	 { "OVERRIDE_STALL_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MCDW_STALL_MODE", 5, 5, &umr_bitfield_default },
+	 { "MCDX_STALL_MODE", 6, 6, &umr_bitfield_default },
+	 { "MCDY_STALL_MODE", 7, 7, &umr_bitfield_default },
+	 { "MCDZ_STALL_MODE", 8, 8, &umr_bitfield_default },
+	 { "MCDS_STALL_MODE", 9, 9, &umr_bitfield_default },
+	 { "MCDT_STALL_MODE", 10, 10, &umr_bitfield_default },
+	 { "MCDU_STALL_MODE", 11, 11, &umr_bitfield_default },
+	 { "MCDV_STALL_MODE", 12, 12, &umr_bitfield_default },
+	 { "BREAK_HDP_DEADLOCK", 13, 13, &umr_bitfield_default },
+	 { "DEBUG_REG", 14, 20, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL0", 21, 21, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT_GBL1", 22, 22, &umr_bitfield_default },
+	 { "PWRXPRESS_MODE", 23, 23, &umr_bitfield_default },
+	 { "ACPG_HP_TO_MCD_OVERRIDE", 24, 24, &umr_bitfield_default },
+	 { "GBL0_PRI_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "UVD_TRANSCODE_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "DMIF_URG_THRESHOLD", 27, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_CNTL[] = {
+	 { "JUMPAHEAD", 0, 0, &umr_bitfield_default },
+	 { "BP", 1, 20, &umr_bitfield_default },
+	 { "BP_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_REG", 22, 29, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 30, 30, &umr_bitfield_default },
+	 { "FAIR_CH_SW", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_WTM_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS[] = {
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS2[] = {
+	 { "STOR0_PRI", 0, 7, &umr_bitfield_default },
+	 { "STOR1_PRI", 8, 15, &umr_bitfield_default },
+	 { "VM2", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL0[] = {
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 17, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_GBL1[] = {
+	 { "MAXBURST", 0, 3, &umr_bitfield_default },
+	 { "LAZY_TIMER", 4, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 8, 15, &umr_bitfield_default },
+	 { "STALL_MODE", 16, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 17, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS[] = {
+	 { "VM0", 0, 7, &umr_bitfield_default },
+	 { "VM1", 8, 15, &umr_bitfield_default },
+	 { "STOR0", 16, 23, &umr_bitfield_default },
+	 { "STOR1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_CREDITS2[] = {
+	 { "STOR0_PRI", 0, 7, &umr_bitfield_default },
+	 { "STOR1_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_SHARED_DAGB_DLY[] = {
+	 { "DLY", 0, 5, &umr_bitfield_default },
+	 { "CLI", 16, 21, &umr_bitfield_default },
+	 { "POS", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_IDLE_STATUS[] = {
+	 { "OUTSTANDING_GFX_READ", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_GFX_WRITE", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_READ", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_WRITE", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_READ", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_WRITE", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_READ", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_WRITE", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_READ", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_WRITE", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_READ", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_WRITE", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_READ", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_WRITE", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_READ", 14, 14, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_WRITE", 15, 15, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_READ", 16, 16, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_WRITE", 17, 17, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_READ", 18, 18, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_WRITE", 19, 19, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_READ", 20, 20, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_WRITE", 21, 21, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_READ", 22, 22, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_WRITE", 23, 23, &umr_bitfield_default },
+	 { "OUTSTANDING_SAMMSP_READ", 24, 24, &umr_bitfield_default },
+	 { "OUTSTANDING_SAMMSP_WRITE", 25, 25, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_READ", 26, 26, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_WRITE", 27, 27, &umr_bitfield_default },
+	 { "OUTSTANDING_ISP_READ", 28, 28, &umr_bitfield_default },
+	 { "OUTSTANDING_ISP_WRITE", 29, 29, &umr_bitfield_default },
+	 { "OUTSTANDING_VP8_READ", 30, 30, &umr_bitfield_default },
+	 { "OUTSTANDING_VP8_WRITE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPG_LIMIT[] = {
+	 { "ENABLE", 0, 1, &umr_bitfield_default },
+	 { "LIMIT_COUNT", 2, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BYPASS_GBL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+	 { "HDP_PRIORITY_TIME", 17, 23, &umr_bitfield_default },
+	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BYPASS_GBL1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+	 { "HDP_PRIORITY_TIME", 17, 23, &umr_bitfield_default },
+	 { "OTH_PRIORITY_TIME", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_BYPASS_GBL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CID1", 1, 8, &umr_bitfield_default },
+	 { "CID2", 9, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH3[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_MISC_ATOMIC_IDLE_STATUS[] = {
+	 { "OUTSTANDING_GFX_ATOMIC", 0, 0, &umr_bitfield_default },
+	 { "OUTSTANDING_RLC_ATOMIC", 1, 1, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA0_ATOMIC", 2, 2, &umr_bitfield_default },
+	 { "OUTSTANDING_SDMA1_ATOMIC", 3, 3, &umr_bitfield_default },
+	 { "OUTSTANDING_DISP_ATOMIC", 4, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_UVD_ATOMIC", 5, 5, &umr_bitfield_default },
+	 { "OUTSTANDING_SMU_ATOMIC", 6, 6, &umr_bitfield_default },
+	 { "OUTSTANDING_HDP_ATOMIC", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_OTH_ATOMIC", 8, 8, &umr_bitfield_default },
+	 { "OUTSTANDING_VMC_ATOMIC", 9, 9, &umr_bitfield_default },
+	 { "OUTSTANDING_VCE_ATOMIC", 10, 10, &umr_bitfield_default },
+	 { "OUTSTANDING_ACP_ATOMIC", 11, 11, &umr_bitfield_default },
+	 { "OUTSTANDING_SAMMSP_ATOMIC", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_XDMA_ATOMIC", 13, 13, &umr_bitfield_default },
+	 { "OUTSTANDING_ISP_ATOMIC", 14, 14, &umr_bitfield_default },
+	 { "OUTSTANDING_VP8_ATOMIC", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDW[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDX[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDY[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDZ[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "MED_CREDITS", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SIP[] = {
+	 { "ASK_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "MED_CREDIT_SEL", 7, 7, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 8, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL0[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_GBL1[] = {
+	 { "STALL_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "STALL_THRESHOLD_PRI", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SMU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SDMA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_HDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SDMA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_RLC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SEM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCE0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_UVD[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_DMIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCEU0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDW[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDX[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDY[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDZ[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SIP[] = {
+	 { "STALL_MODE", 0, 1, &umr_bitfield_default },
+	 { "ASK_CREDITS", 2, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SDMA1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCIF[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCE0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_IH[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_RLC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SEM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SMU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SH1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UMC[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_UVD[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_HDP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SDMA0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDW[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDX[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDY[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDZ[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCEU0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_XDMA[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_XDMAM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ACPO[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_SAMMSP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VP8[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VP8U[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ACPG[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ACPO[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_SAMMSP[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VP8[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VP8U[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB1_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MB_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR4[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR5[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR6[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR7[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR8[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_SRC_APRTR9[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR0[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR1[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR2[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_SRC_APRTR3[] = {
+	 { "BASE_ADDR", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP0[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP1[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP2[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP3[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP4[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP5[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP6[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP7[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP8[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_RTR_DEST_MAP9[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP0[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP1[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP2[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_RTR_DEST_MAP3[] = {
+	 { "NMR", 0, 0, &umr_bitfield_default },
+	 { "DEST_OFFSET", 1, 19, &umr_bitfield_default },
+	 { "DEST_SEL", 20, 23, &umr_bitfield_default },
+	 { "DEST_SEL_RPB", 24, 24, &umr_bitfield_default },
+	 { "SIDE_OK", 25, 25, &umr_bitfield_default },
+	 { "APRTR_SIZE", 26, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG0[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG1[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG2[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG3[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG4[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG5[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG6[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG7[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG8[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG9[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG10[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG11[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG12[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG13[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG14[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG15[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG16[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG17[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG18[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG19[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_LB_ADDR[] = {
+	 { "CMP0", 0, 9, &umr_bitfield_default },
+	 { "MASK0", 10, 19, &umr_bitfield_default },
+	 { "CMP1", 20, 25, &umr_bitfield_default },
+	 { "MASK1", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_HST[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_UNC_THRESH_SID[] = {
+	 { "CHANGE_PREF", 0, 5, &umr_bitfield_default },
+	 { "STRONG_PREF", 6, 11, &umr_bitfield_default },
+	 { "USE_UNFULL", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_STS[] = {
+	 { "PBUF_VLD", 0, 15, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 16, 22, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 23, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_WCB_CFG[] = {
+	 { "TIMEOUT", 0, 15, &umr_bitfield_default },
+	 { "HST_MAX", 16, 17, &umr_bitfield_default },
+	 { "SID_MAX", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_CFG[] = {
+	 { "ADDR_SIZE", 0, 3, &umr_bitfield_default },
+	 { "SEND_BAR", 4, 5, &umr_bitfield_default },
+	 { "SNOOP", 6, 6, &umr_bitfield_default },
+	 { "SEND_DIS", 7, 7, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 8, 8, &umr_bitfield_default },
+	 { "UPDATE_DIS", 9, 9, &umr_bitfield_default },
+	 { "REGBAR_FROM_SYSBAR", 10, 10, &umr_bitfield_default },
+	 { "RD_EN", 11, 11, &umr_bitfield_default },
+	 { "ATC_TRANSLATED", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR0[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR1[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR2[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR3[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR4[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR5[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR6[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR7[] = {
+	 { "HOST_FLUSH", 0, 3, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 4, 7, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_SETUP[] = {
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "REG_SYS_BAR", 8, 11, &umr_bitfield_default },
+	 { "VALID", 12, 12, &umr_bitfield_default },
+	 { "SEND_DIS", 13, 13, &umr_bitfield_default },
+	 { "COMPRESS_DIS", 14, 14, &umr_bitfield_default },
+	 { "RESERVED", 15, 15, &umr_bitfield_default },
+	 { "ADDRESS", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DEBUG[] = {
+	 { "SEL", 0, 7, &umr_bitfield_default },
+	 { "HOST_FLUSH", 8, 11, &umr_bitfield_default },
+	 { "MEM_SYS_BAR", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_ABOVE[] = {
+	 { "EN", 0, 7, &umr_bitfield_default },
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_P2P_BAR_DELTA_BELOW[] = {
+	 { "EN", 0, 7, &umr_bitfield_default },
+	 { "DELTA", 8, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR4[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR5[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR6[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR7[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR8[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PEER_SYS_BAR9[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_XDMA_PEER_SYS_BAR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "SIDE_OK", 1, 1, &umr_bitfield_default },
+	 { "ADDR", 2, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLK_GAT[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG[] = {
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "MC_WRRET_ASK", 8, 15, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 16, 22, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_SEL", 23, 23, &umr_bitfield_default },
+	 { "BIF_REG_SNOOP_VAL", 24, 24, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_SEL", 25, 25, &umr_bitfield_default },
+	 { "BIF_MEM_SNOOP_VAL", 26, 26, &umr_bitfield_default },
+	 { "XSP_SNOOP_SEL", 27, 28, &umr_bitfield_default },
+	 { "XSP_SNOOP_VAL", 29, 29, &umr_bitfield_default },
+	 { "XSP_ORDERING_SEL", 30, 30, &umr_bitfield_default },
+	 { "XSP_ORDERING_VAL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_STS[] = {
+	 { "RPB_WRREQ_CRD", 0, 7, &umr_bitfield_default },
+	 { "XSP_REQ_CRD", 8, 14, &umr_bitfield_default },
+	 { "HOP_DATA_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "HOP_ATTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "CNS_BUF_FULL", 17, 17, &umr_bitfield_default },
+	 { "CNS_BUF_BUSY", 18, 18, &umr_bitfield_default },
+	 { "RPB_RDREQ_CRD", 19, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PIPE_STS[] = {
+	 { "WCB_ANY_PBUF", 0, 0, &umr_bitfield_default },
+	 { "WCB_HST_DATA_BUF_CNT", 1, 7, &umr_bitfield_default },
+	 { "WCB_SID_DATA_BUF_CNT", 8, 14, &umr_bitfield_default },
+	 { "WCB_HST_RD_PTR_BUF_FULL", 15, 15, &umr_bitfield_default },
+	 { "WCB_SID_RD_PTR_BUF_FULL", 16, 16, &umr_bitfield_default },
+	 { "WCB_HST_REQ_FIFO_FULL", 17, 17, &umr_bitfield_default },
+	 { "WCB_SID_REQ_FIFO_FULL", 18, 18, &umr_bitfield_default },
+	 { "WCB_HST_REQ_OBUF_FULL", 19, 19, &umr_bitfield_default },
+	 { "WCB_SID_REQ_OBUF_FULL", 20, 20, &umr_bitfield_default },
+	 { "WCB_HST_DATA_OBUF_FULL", 21, 21, &umr_bitfield_default },
+	 { "WCB_SID_DATA_OBUF_FULL", 22, 22, &umr_bitfield_default },
+	 { "RET_BUF_FULL", 23, 23, &umr_bitfield_default },
+	 { "XPB_CLK_BUSY_BITS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_SUB_CTRL[] = {
+	 { "WRREQ_BYPASS_XPB", 0, 0, &umr_bitfield_default },
+	 { "STALL_CNS_RTR_REQ", 1, 1, &umr_bitfield_default },
+	 { "STALL_RTR_RPB_WRREQ", 2, 2, &umr_bitfield_default },
+	 { "STALL_RTR_MAP_REQ", 3, 3, &umr_bitfield_default },
+	 { "STALL_MAP_WCB_REQ", 4, 4, &umr_bitfield_default },
+	 { "STALL_WCB_SID_REQ", 5, 5, &umr_bitfield_default },
+	 { "STALL_MC_XSP_REQ_SEND", 6, 6, &umr_bitfield_default },
+	 { "STALL_WCB_HST_REQ", 7, 7, &umr_bitfield_default },
+	 { "STALL_HST_HOP_REQ", 8, 8, &umr_bitfield_default },
+	 { "STALL_XPB_RPB_REQ_ATTR", 9, 9, &umr_bitfield_default },
+	 { "RESET_CNS", 10, 10, &umr_bitfield_default },
+	 { "RESET_RTR", 11, 11, &umr_bitfield_default },
+	 { "RESET_RET", 12, 12, &umr_bitfield_default },
+	 { "RESET_MAP", 13, 13, &umr_bitfield_default },
+	 { "RESET_WCB", 14, 14, &umr_bitfield_default },
+	 { "RESET_HST", 15, 15, &umr_bitfield_default },
+	 { "RESET_HOP", 16, 16, &umr_bitfield_default },
+	 { "RESET_SID", 17, 17, &umr_bitfield_default },
+	 { "RESET_SRB", 18, 18, &umr_bitfield_default },
+	 { "RESET_CGR", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[] = {
+	 { "ALTER_FLUSH_NUM", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_PERF_KNOBS[] = {
+	 { "CNS_FIFO_DEPTH", 0, 5, &umr_bitfield_default },
+	 { "WCB_HST_FIFO_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "WCB_SID_FIFO_DEPTH", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_STICKY_W1C[] = {
+	 { "BITS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_MISC_CFG[] = {
+	 { "FIELDNAME0", 0, 7, &umr_bitfield_default },
+	 { "FIELDNAME1", 8, 15, &umr_bitfield_default },
+	 { "FIELDNAME2", 16, 23, &umr_bitfield_default },
+	 { "FIELDNAME3", 24, 30, &umr_bitfield_default },
+	 { "TRIGGERNAME", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG20[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG21[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG22[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG23[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG24[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG25[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG26[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG27[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG28[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG29[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG30[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG31[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_INTF_CFG2[] = {
+	 { "RPB_RDREQ_CRD", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_EXTRA_RD[] = {
+	 { "CMP0", 0, 7, &umr_bitfield_default },
+	 { "MSK0", 8, 15, &umr_bitfield_default },
+	 { "VLD0", 16, 16, &umr_bitfield_default },
+	 { "CMP1", 17, 24, &umr_bitfield_default },
+	 { "VLD1", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG32[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG33[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG34[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG35[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XPB_CLG_CFG36[] = {
+	 { "WCB_NUM", 0, 3, &umr_bitfield_default },
+	 { "LB_TYPE", 4, 6, &umr_bitfield_default },
+	 { "P2P_BAR", 7, 9, &umr_bitfield_default },
+	 { "HOST_FLUSH", 10, 13, &umr_bitfield_default },
+	 { "SIDE_FLUSH", 14, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CONF[] = {
+	 { "XPB_PCIE_ORDER", 15, 15, &umr_bitfield_default },
+	 { "RPB_RD_PCIE_ORDER", 16, 16, &umr_bitfield_default },
+	 { "RPB_WR_PCIE_ORDER", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_IF_CONF[] = {
+	 { "RPB_BIF_CREDITS", 0, 7, &umr_bitfield_default },
+	 { "OUTSTANDING_WRRET_ASK", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_DBG1[] = {
+	 { "RPB_BIF_OUTSTANDING_RD", 0, 7, &umr_bitfield_default },
+	 { "RPB_BIF_OUTSTANDING_RD_32B", 8, 19, &umr_bitfield_default },
+	 { "DEBUG_BITS", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_EFF_CNTL[] = {
+	 { "WR_LAZY_TIMER", 0, 7, &umr_bitfield_default },
+	 { "RD_LAZY_TIMER", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_ARB_CNTL[] = {
+	 { "WR_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "RD_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "ATC_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_BIF_CNTL[] = {
+	 { "ARB_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "XPB_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_WR_COMBINE_CNTL[] = {
+	 { "WC_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "WC_MAX_PACKET_SIZE", 1, 2, &umr_bitfield_default },
+	 { "WC_FLUSH_TIMER", 3, 6, &umr_bitfield_default },
+	 { "WC_ALIGN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_RD_SWITCH_CNTL[] = {
+	 { "QUEUE0_SWITCH_NUM", 0, 7, &umr_bitfield_default },
+	 { "QUEUE1_SWITCH_NUM", 8, 15, &umr_bitfield_default },
+	 { "QUEUE2_SWITCH_NUM", 16, 23, &umr_bitfield_default },
+	 { "QUEUE3_SWITCH_NUM", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_WR[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "UPDATE_MODE", 8, 8, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 9, 10, &umr_bitfield_default },
+	 { "READ_QUEUE", 11, 12, &umr_bitfield_default },
+	 { "UPDATE", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_RD[] = {
+	 { "CLIENT_ID", 0, 7, &umr_bitfield_default },
+	 { "WRITE_QUEUE", 8, 9, &umr_bitfield_default },
+	 { "READ_QUEUE", 10, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_CNTL[] = {
+	 { "PERF_COUNTER_SELECT", 0, 1, &umr_bitfield_default },
+	 { "CLEAR_SELECTED_PERF_COUNTER", 2, 2, &umr_bitfield_default },
+	 { "CLEAR_ALL_PERF_COUNTERS", 3, 3, &umr_bitfield_default },
+	 { "STOP_ON_COUNTER_SATURATION", 4, 4, &umr_bitfield_default },
+	 { "ENABLE_PERF_COUNTERS", 5, 8, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_0", 9, 13, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_1", 14, 18, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_2", 19, 23, &umr_bitfield_default },
+	 { "PERF_COUNTER_ASSIGN_3", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_PERF_COUNTER_STATUS[] = {
+	 { "PERFORMANCE_COUNTER_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_CID_QUEUE_EX_DATA[] = {
+	 { "WRITE_ENTRIES", 0, 15, &umr_bitfield_default },
+	 { "READ_ENTRIES", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_TCI_CNTL[] = {
+	 { "TCI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "TCI_POLICY", 1, 2, &umr_bitfield_default },
+	 { "TCI_VOL", 3, 3, &umr_bitfield_default },
+	 { "TCI_VMID", 4, 7, &umr_bitfield_default },
+	 { "TCI_REQ_CREDITS", 8, 15, &umr_bitfield_default },
+	 { "TCI_MAX_WRITES", 16, 23, &umr_bitfield_default },
+	 { "TCI_MAX_READS", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RPB_TCI_CNTL2[] = {
+	 { "TCI_POLICY", 0, 0, &umr_bitfield_default },
+	 { "TCI_MTYPE", 1, 2, &umr_bitfield_default },
+	 { "TCI_SNOOP", 3, 3, &umr_bitfield_default },
+	 { "TCI_PHYSICAL", 4, 4, &umr_bitfield_default },
+	 { "TCI_PERF_CNTR_EN", 5, 5, &umr_bitfield_default },
+	 { "TCI_EXE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_XTRA_ENABLE[] = {
+	 { "CB1_RD", 0, 0, &umr_bitfield_default },
+	 { "CB1_WR", 1, 1, &umr_bitfield_default },
+	 { "DB1_RD", 2, 2, &umr_bitfield_default },
+	 { "DB1_WR", 3, 3, &umr_bitfield_default },
+	 { "TC2_RD", 4, 4, &umr_bitfield_default },
+	 { "ARB_DBG", 8, 11, &umr_bitfield_default },
+	 { "TC2_WR", 12, 12, &umr_bitfield_default },
+	 { "CB0_CONNECT_CNTL", 13, 14, &umr_bitfield_default },
+	 { "DB0_CONNECT_CNTL", 15, 16, &umr_bitfield_default },
+	 { "CB1_CONNECT_CNTL", 17, 18, &umr_bitfield_default },
+	 { "DB1_CONNECT_CNTL", 19, 20, &umr_bitfield_default },
+	 { "TC0_CONNECT_CNTL", 21, 22, &umr_bitfield_default },
+	 { "TC1_CONNECT_CNTL", 23, 24, &umr_bitfield_default },
+	 { "CB0_CID_CNTL_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DB0_CID_CNTL_ENABLE", 26, 26, &umr_bitfield_default },
+	 { "CB1_CID_CNTL_ENABLE", 27, 27, &umr_bitfield_default },
+	 { "DB1_CID_CNTL_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "TC2_REPAIR_ENABLE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_MC_MAX_CHANNEL[] = {
+	 { "NOOFCHAN", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_CONFIG[] = {
+	 { "MCDW_WR_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MCDX_WR_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MCDY_WR_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "MCDZ_WR_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "MC_RD_ENABLE", 4, 5, &umr_bitfield_default },
+	 { "INDEX", 6, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CNTL[] = {
+	 { "IGNOREPM", 2, 2, &umr_bitfield_default },
+	 { "EXEMPTPM", 3, 3, &umr_bitfield_default },
+	 { "GFX_IDLE_OVERRIDE", 4, 5, &umr_bitfield_default },
+	 { "MCD_SRBM_MASK_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "CNTR_CHMAP_MODE", 7, 8, &umr_bitfield_default },
+	 { "REMOTE_RB_CONNECT_ENABLE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_VM[] = {
+	 { "READ_ALL", 0, 5, &umr_bitfield_default },
+	 { "WRITE_ALL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_RD[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "READ_HUB", 8, 15, &umr_bitfield_default },
+	 { "READ_PRI", 16, 23, &umr_bitfield_default },
+	 { "LCL_PRI", 24, 24, &umr_bitfield_default },
+	 { "HUB_PRI", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_WR[] = {
+	 { "WRITE_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_HUB", 8, 15, &umr_bitfield_default },
+	 { "WRITE_PRI", 16, 23, &umr_bitfield_default },
+	 { "HUB_PRI", 24, 24, &umr_bitfield_default },
+	 { "LCL_PRI", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_CNTL[] = {
+	 { "JUMP_AHEAD", 0, 0, &umr_bitfield_default },
+	 { "CENTER_RD_MAX_BURST", 1, 4, &umr_bitfield_default },
+	 { "DISABLE_SELF_INIT", 5, 5, &umr_bitfield_default },
+	 { "CENTER_WR_MAX_BURST", 6, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS[] = {
+	 { "REMRDRET", 0, 5, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_LP", 12, 17, &umr_bitfield_default },
+	 { "CNTR_RD_HUB_HP", 18, 23, &umr_bitfield_default },
+	 { "CNTR_RD_LCL", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_RET_MODE[] = {
+	 { "INORDER_RD", 0, 0, &umr_bitfield_default },
+	 { "INORDER_WR", 1, 1, &umr_bitfield_default },
+	 { "REMPRI_RD", 2, 2, &umr_bitfield_default },
+	 { "REMPRI_WR", 3, 3, &umr_bitfield_default },
+	 { "LCLPRI_RD", 4, 4, &umr_bitfield_default },
+	 { "LCLPRI_WR", 5, 5, &umr_bitfield_default },
+	 { "RDRET_STALL_EN", 6, 6, &umr_bitfield_default },
+	 { "RDRET_STALL_THRESHOLD", 7, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_DAGB_DLY[] = {
+	 { "DLY", 0, 4, &umr_bitfield_default },
+	 { "CLI", 16, 21, &umr_bitfield_default },
+	 { "POS", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_EXT[] = {
+	 { "DBSTEN0", 0, 3, &umr_bitfield_default },
+	 { "TC0", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_REMREQ[] = {
+	 { "READ_CREDITS", 0, 6, &umr_bitfield_default },
+	 { "WRITE_CREDITS", 7, 13, &umr_bitfield_default },
+	 { "CREDITS_ENABLE", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_TC1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_INT_CREDITS_WR[] = {
+	 { "CNTR_WR_HUB", 0, 5, &umr_bitfield_default },
+	 { "CNTR_WR_LCL", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_ARB_RD2[] = {
+	 { "READ_MED", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_RD_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_LOCAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_WTM_WR_CNTL[] = {
+	 { "GROUP0_DECREMENT", 0, 2, &umr_bitfield_default },
+	 { "GROUP1_DECREMENT", 3, 5, &umr_bitfield_default },
+	 { "GROUP2_DECREMENT", 6, 8, &umr_bitfield_default },
+	 { "GROUP3_DECREMENT", 9, 11, &umr_bitfield_default },
+	 { "GROUP4_DECREMENT", 12, 14, &umr_bitfield_default },
+	 { "GROUP5_DECREMENT", 15, 17, &umr_bitfield_default },
+	 { "GROUP6_DECREMENT", 18, 20, &umr_bitfield_default },
+	 { "GROUP7_DECREMENT", 21, 23, &umr_bitfield_default },
+	 { "DISABLE_REMOTE", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_LOCAL", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_CB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_DB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_TC1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_HUB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_CB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_DB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_HUB[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAX_BURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_CREDITS_XBAR[] = {
+	 { "READ_LCL", 0, 7, &umr_bitfield_default },
+	 { "WRITE_LCL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_RD_GRP_LCL[] = {
+	 { "CB0", 12, 15, &umr_bitfield_default },
+	 { "CBCMASK0", 16, 19, &umr_bitfield_default },
+	 { "CBFMASK0", 20, 23, &umr_bitfield_default },
+	 { "DB0", 24, 27, &umr_bitfield_default },
+	 { "DBHTILE0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_WR_GRP_LCL[] = {
+	 { "CB0", 0, 3, &umr_bitfield_default },
+	 { "CBCMASK0", 4, 7, &umr_bitfield_default },
+	 { "CBFMASK0", 8, 11, &umr_bitfield_default },
+	 { "DB0", 12, 15, &umr_bitfield_default },
+	 { "DBHTILE0", 16, 19, &umr_bitfield_default },
+	 { "SX0", 20, 23, &umr_bitfield_default },
+	 { "CBIMMED0", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_CNTL2[] = {
+	 { "CID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_PERF_MON_RSLT2[] = {
+	 { "CB_RD_BUSY", 1, 1, &umr_bitfield_default },
+	 { "DB_RD_BUSY", 2, 2, &umr_bitfield_default },
+	 { "TC0_RD_BUSY", 3, 3, &umr_bitfield_default },
+	 { "VC0_RD_BUSY", 4, 4, &umr_bitfield_default },
+	 { "TC1_RD_BUSY", 5, 5, &umr_bitfield_default },
+	 { "VC1_RD_BUSY", 6, 6, &umr_bitfield_default },
+	 { "CB_WR_BUSY", 7, 7, &umr_bitfield_default },
+	 { "DB_WR_BUSY", 8, 8, &umr_bitfield_default },
+	 { "SX_WR_BUSY", 9, 9, &umr_bitfield_default },
+	 { "TC2_RD_BUSY", 10, 10, &umr_bitfield_default },
+	 { "TC0_WR_BUSY", 11, 11, &umr_bitfield_default },
+	 { "TC1_WR_BUSY", 12, 12, &umr_bitfield_default },
+	 { "TC2_WR_BUSY", 13, 13, &umr_bitfield_default },
+	 { "TC0_ATOM_BUSY", 14, 14, &umr_bitfield_default },
+	 { "TC1_ATOM_BUSY", 15, 15, &umr_bitfield_default },
+	 { "TC2_ATOM_BUSY", 16, 16, &umr_bitfield_default },
+	 { "CB_ATOM_BUSY", 17, 17, &umr_bitfield_default },
+	 { "DB_ATOM_BUSY", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_RD_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_WR_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CITF_MISC_VM_CG[] = {
+	 { "ONDLY", 0, 5, &umr_bitfield_default },
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "RDYDLY", 12, 17, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB0_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB1_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L2ARBITER_L2_CREDITS[] = {
+	 { "L2_IF_CREDITS", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_DEBUG[] = {
+	 { "INVALIDATE_L1_TLB", 0, 0, &umr_bitfield_default },
+	 { "SEND_FREE_AT_RTN", 8, 8, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_TLB_SIZE", 9, 11, &umr_bitfield_default },
+	 { "EFFECTIVE_L1_QUEUE_SIZE", 12, 14, &umr_bitfield_default },
+	 { "L1_TLB_DEBUG", 15, 18, &umr_bitfield_default },
+	 { "L1_TLB_FORCE_MISS", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MD_L1_TLB3_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ATOMIC[] = {
+	 { "TC_GRP", 0, 2, &umr_bitfield_default },
+	 { "TC_GRP_EN", 3, 3, &umr_bitfield_default },
+	 { "SDMA_GRP", 4, 6, &umr_bitfield_default },
+	 { "SDMA_GRP_EN", 7, 7, &umr_bitfield_default },
+	 { "OUTSTANDING", 8, 15, &umr_bitfield_default },
+	 { "ATOMIC_RTN_GRP", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_CNTL[] = {
+	 { "RESET_RD_GROUP0", 0, 0, &umr_bitfield_default },
+	 { "RESET_RD_GROUP1", 1, 1, &umr_bitfield_default },
+	 { "RESET_RD_GROUP2", 2, 2, &umr_bitfield_default },
+	 { "RESET_RD_GROUP3", 3, 3, &umr_bitfield_default },
+	 { "RESET_RD_GROUP4", 4, 4, &umr_bitfield_default },
+	 { "RESET_RD_GROUP5", 5, 5, &umr_bitfield_default },
+	 { "RESET_RD_GROUP6", 6, 6, &umr_bitfield_default },
+	 { "RESET_RD_GROUP7", 7, 7, &umr_bitfield_default },
+	 { "RESET_WR_GROUP0", 8, 8, &umr_bitfield_default },
+	 { "RESET_WR_GROUP1", 9, 9, &umr_bitfield_default },
+	 { "RESET_WR_GROUP2", 10, 10, &umr_bitfield_default },
+	 { "RESET_WR_GROUP3", 11, 11, &umr_bitfield_default },
+	 { "RESET_WR_GROUP4", 12, 12, &umr_bitfield_default },
+	 { "RESET_WR_GROUP5", 13, 13, &umr_bitfield_default },
+	 { "RESET_WR_GROUP6", 14, 14, &umr_bitfield_default },
+	 { "RESET_WR_GROUP7", 15, 15, &umr_bitfield_default },
+	 { "AGE_LOW_RATE_RD", 16, 18, &umr_bitfield_default },
+	 { "AGE_LOW_RATE_WR", 19, 21, &umr_bitfield_default },
+	 { "TIMER_STALL_RD", 22, 22, &umr_bitfield_default },
+	 { "TIMER_STALL_WR", 23, 23, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT_RD", 24, 24, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT_WR", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS2[] = {
+	 { "ACP_WR", 0, 7, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_EN_RD", 8, 8, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_EN_WR", 9, 9, &umr_bitfield_default },
+	 { "ACP_RDRET_URG", 10, 10, &umr_bitfield_default },
+	 { "HDP_RDRET_URG", 11, 11, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_MONITOR_RD", 12, 12, &umr_bitfield_default },
+	 { "NECKDOWN_CNTR_MONITOR_WR", 13, 13, &umr_bitfield_default },
+	 { "DISABLE_DISP_RDY_RD", 14, 14, &umr_bitfield_default },
+	 { "DISABLE_ACP_RDY_WR", 15, 15, &umr_bitfield_default },
+	 { "RDRET_CREDIT_MED", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_FED_CNTL[] = {
+	 { "MODE", 0, 1, &umr_bitfield_default },
+	 { "WR_ERR", 2, 3, &umr_bitfield_default },
+	 { "KEEP_POISON_IN_PAGE", 4, 4, &umr_bitfield_default },
+	 { "RDRET_PARITY_NACK", 5, 5, &umr_bitfield_default },
+	 { "USE_LEGACY_NACK", 6, 6, &umr_bitfield_default },
+	 { "DEBUG_RSV", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_STATUS[] = {
+	 { "CORR_STS0", 0, 0, &umr_bitfield_default },
+	 { "UNCORR_STS0", 1, 1, &umr_bitfield_default },
+	 { "FED_STS0", 2, 2, &umr_bitfield_default },
+	 { "RSVD0", 3, 3, &umr_bitfield_default },
+	 { "CORR_STS1", 4, 4, &umr_bitfield_default },
+	 { "UNCORR_STS1", 5, 5, &umr_bitfield_default },
+	 { "FED_STS1", 6, 6, &umr_bitfield_default },
+	 { "RSVD1", 7, 7, &umr_bitfield_default },
+	 { "CORR_CLEAR0", 8, 8, &umr_bitfield_default },
+	 { "UNCORR_CLEAR0", 9, 9, &umr_bitfield_default },
+	 { "FED_CLEAR0", 10, 10, &umr_bitfield_default },
+	 { "RSVD2", 11, 11, &umr_bitfield_default },
+	 { "CORR_CLEAR1", 12, 12, &umr_bitfield_default },
+	 { "UNCORR_CLEAR1", 13, 13, &umr_bitfield_default },
+	 { "FED_CLEAR1", 14, 14, &umr_bitfield_default },
+	 { "RSVD3", 15, 15, &umr_bitfield_default },
+	 { "RMWRD_CORR_STS0", 16, 16, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_STS0", 17, 17, &umr_bitfield_default },
+	 { "RSVD4", 18, 19, &umr_bitfield_default },
+	 { "RMWRD_CORR_STS1", 20, 20, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_STS1", 21, 21, &umr_bitfield_default },
+	 { "RSVD5", 22, 23, &umr_bitfield_default },
+	 { "RMWRD_CORR_CLEAR0", 24, 24, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_CLEAR0", 25, 25, &umr_bitfield_default },
+	 { "RSVD6", 26, 27, &umr_bitfield_default },
+	 { "RMWRD_CORR_CLEAR1", 28, 28, &umr_bitfield_default },
+	 { "RMWRD_UNCORR_CLEAR1", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_MISC[] = {
+	 { "STREAK_BREAK", 0, 3, &umr_bitfield_default },
+	 { "COL10_HACK", 4, 4, &umr_bitfield_default },
+	 { "CWRD_IN_REPLAY", 5, 5, &umr_bitfield_default },
+	 { "NO_EOB_ALL_WR_IN_REPLAY", 6, 6, &umr_bitfield_default },
+	 { "RMW_LM_WR_STALL", 7, 7, &umr_bitfield_default },
+	 { "RMW_STALL_RELEASE", 8, 8, &umr_bitfield_default },
+	 { "WR_EDC_MASK_REPLAY", 9, 9, &umr_bitfield_default },
+	 { "CWRD_REPLAY_AGAIN", 10, 10, &umr_bitfield_default },
+	 { "WRRDWR_REPLAY_AGAIN", 11, 11, &umr_bitfield_default },
+	 { "ALLOW_RMW_ERR_AFTER_REPLAY", 12, 12, &umr_bitfield_default },
+	 { "DEBUG_RSV", 13, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG[] = {
+	 { "NUM_ERR_BITS", 0, 1, &umr_bitfield_default },
+	 { "DIRECTION", 2, 2, &umr_bitfield_default },
+	 { "DATA_FIELD", 3, 4, &umr_bitfield_default },
+	 { "SW_INJECTION", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_DEBUG2[] = {
+	 { "PERIOD", 0, 7, &umr_bitfield_default },
+	 { "ERR0_START", 8, 15, &umr_bitfield_default },
+	 { "ERR1_START", 16, 23, &umr_bitfield_default },
+	 { "ERR2_START", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PERF_CID[] = {
+	 { "CH0", 0, 7, &umr_bitfield_default },
+	 { "CH1", 8, 15, &umr_bitfield_default },
+	 { "CH0_EN", 16, 16, &umr_bitfield_default },
+	 { "CH1_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SNOOP[] = {
+	 { "TC_GRP_RD", 0, 2, &umr_bitfield_default },
+	 { "TC_GRP_RD_EN", 3, 3, &umr_bitfield_default },
+	 { "TC_GRP_WR", 4, 6, &umr_bitfield_default },
+	 { "TC_GRP_WR_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_GRP_RD", 8, 10, &umr_bitfield_default },
+	 { "SDMA_GRP_RD_EN", 11, 11, &umr_bitfield_default },
+	 { "SDMA_GRP_WR", 12, 14, &umr_bitfield_default },
+	 { "SDMA_GRP_WR_EN", 15, 15, &umr_bitfield_default },
+	 { "OUTSTANDING_RD", 16, 23, &umr_bitfield_default },
+	 { "OUTSTANDING_WR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB[] = {
+	 { "GRUB_WATERMARK", 0, 7, &umr_bitfield_default },
+	 { "GRUB_WATERMARK_PRI", 8, 15, &umr_bitfield_default },
+	 { "GRUB_WATERMARK_MED", 16, 23, &umr_bitfield_default },
+	 { "REG_WR_EN", 24, 25, &umr_bitfield_default },
+	 { "REG_RD_SEL", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ECC_MODE", 1, 2, &umr_bitfield_default },
+	 { "PAGE_BIT0", 3, 4, &umr_bitfield_default },
+	 { "EXOR_BANK_SEL", 5, 6, &umr_bitfield_default },
+	 { "NO_GECC_CLI", 7, 10, &umr_bitfield_default },
+	 { "READ_ERR", 11, 13, &umr_bitfield_default },
+	 { "CLOSE_BANK_RMW", 14, 14, &umr_bitfield_default },
+	 { "COLFIFO_WATER", 15, 20, &umr_bitfield_default },
+	 { "WRADDR_CONV", 21, 21, &umr_bitfield_default },
+	 { "RMWRD_UNCOR_POISON", 22, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GECC2_CLI[] = {
+	 { "NO_GECC_CLI0", 0, 7, &umr_bitfield_default },
+	 { "NO_GECC_CLI1", 8, 15, &umr_bitfield_default },
+	 { "NO_GECC_CLI2", 16, 23, &umr_bitfield_default },
+	 { "NO_GECC_CLI3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_SWIZ0[] = {
+	 { "A8", 0, 3, &umr_bitfield_default },
+	 { "A9", 4, 7, &umr_bitfield_default },
+	 { "A10", 8, 11, &umr_bitfield_default },
+	 { "A11", 12, 15, &umr_bitfield_default },
+	 { "A12", 16, 19, &umr_bitfield_default },
+	 { "A13", 20, 23, &umr_bitfield_default },
+	 { "A14", 24, 27, &umr_bitfield_default },
+	 { "A15", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_SWIZ1[] = {
+	 { "A16", 0, 3, &umr_bitfield_default },
+	 { "A17", 4, 7, &umr_bitfield_default },
+	 { "A18", 8, 11, &umr_bitfield_default },
+	 { "A19", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC3[] = {
+	 { "NO_GECC_EXT_EOB", 0, 0, &umr_bitfield_default },
+	 { "CHAN4_EN", 1, 1, &umr_bitfield_default },
+	 { "CHAN4_ARB_SEL", 2, 2, &umr_bitfield_default },
+	 { "UVD_URG_MODE", 3, 3, &umr_bitfield_default },
+	 { "UVD_DMIF_HARSH_WT_EN", 4, 4, &umr_bitfield_default },
+	 { "TBD_FIELD", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PROMOTE[] = {
+	 { "URGENT_RD", 0, 7, &umr_bitfield_default },
+	 { "URGENT_WR", 8, 15, &umr_bitfield_default },
+	 { "PROMOTE_RD", 16, 23, &umr_bitfield_default },
+	 { "PROMOTE_WR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DATA[] = {
+	 { "PATTERN", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL0[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "START_IDLE", 1, 1, &umr_bitfield_default },
+	 { "START_R2W", 2, 3, &umr_bitfield_default },
+	 { "FLUSH_ON_ENTER", 4, 4, &umr_bitfield_default },
+	 { "HARSH_START", 5, 5, &umr_bitfield_default },
+	 { "TPS_HARSH_PRIORITY", 6, 6, &umr_bitfield_default },
+	 { "TWRT_HARSH_PRIORITY", 7, 7, &umr_bitfield_default },
+	 { "BREAK_ON_HARSH", 8, 8, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTRD", 9, 9, &umr_bitfield_default },
+	 { "BREAK_ON_URGENTWR", 10, 10, &umr_bitfield_default },
+	 { "TRAIN_PERIOD", 11, 13, &umr_bitfield_default },
+	 { "START_R2W_RFSH", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_RSV_0", 15, 15, &umr_bitfield_default },
+	 { "DEBUG_RSV_1", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_RSV_2", 17, 17, &umr_bitfield_default },
+	 { "DEBUG_RSV_3", 18, 18, &umr_bitfield_default },
+	 { "DEBUG_RSV_4", 19, 19, &umr_bitfield_default },
+	 { "DEBUG_RSV_5", 20, 20, &umr_bitfield_default },
+	 { "DEBUG_RSV_6", 21, 21, &umr_bitfield_default },
+	 { "DEBUG_RSV_7", 22, 22, &umr_bitfield_default },
+	 { "DEBUG_RSV_8", 23, 23, &umr_bitfield_default },
+	 { "DATA_CNTL", 24, 24, &umr_bitfield_default },
+	 { "NEIGHBOR_BIT", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL1[] = {
+	 { "WINDOW_SIZE", 0, 4, &umr_bitfield_default },
+	 { "WINDOW_UPDATE", 5, 5, &umr_bitfield_default },
+	 { "WINDOW_INC_THRESHOLD", 6, 12, &umr_bitfield_default },
+	 { "WINDOW_DEC_THRESHOLD", 13, 19, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MAX", 20, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_MIN", 25, 29, &umr_bitfield_default },
+	 { "WINDOW_UPDATE_COUNT", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_CNTL2[] = {
+	 { "SAMPLE_CNT", 0, 5, &umr_bitfield_default },
+	 { "PHASE_ADJUST_THRESHOLD", 6, 11, &umr_bitfield_default },
+	 { "PHASE_ADJUST_SIZE", 12, 12, &umr_bitfield_default },
+	 { "FILTER_CNTL", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RTT_DEBUG[] = {
+	 { "DEBUG_BYTE_CH0", 0, 1, &umr_bitfield_default },
+	 { "DEBUG_BYTE_CH1", 2, 3, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH0", 4, 11, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH0", 12, 16, &umr_bitfield_default },
+	 { "SHIFTED_PHASE_CH1", 17, 24, &umr_bitfield_default },
+	 { "WINDOW_SIZE_CH1", 25, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CAC_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "READ_WEIGHT", 1, 6, &umr_bitfield_default },
+	 { "WRITE_WEIGHT", 7, 12, &umr_bitfield_default },
+	 { "ALLOW_OVERFLOW", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC2[] = {
+	 { "TCCDL4_BANKBIT3_XOR_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT4", 6, 6, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT5", 7, 7, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT6", 8, 8, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT7", 9, 9, &umr_bitfield_default },
+	 { "TCCDL4_BANKBIT3_XOR_COLBIT8", 10, 10, &umr_bitfield_default },
+	 { "POP_IDLE_REPLAY", 11, 11, &umr_bitfield_default },
+	 { "RDRET_NO_REORDERING", 12, 12, &umr_bitfield_default },
+	 { "RDRET_NO_BP", 13, 13, &umr_bitfield_default },
+	 { "RDRET_SEQ_SKID", 14, 17, &umr_bitfield_default },
+	 { "GECC", 18, 18, &umr_bitfield_default },
+	 { "GECC_RST", 19, 19, &umr_bitfield_default },
+	 { "GECC_STATUS", 20, 20, &umr_bitfield_default },
+	 { "TAGFIFO_THRESHOLD", 21, 24, &umr_bitfield_default },
+	 { "WCDR_REPLAY_MASKCNT", 25, 27, &umr_bitfield_default },
+	 { "REPLAY_DEBUG", 28, 28, &umr_bitfield_default },
+	 { "ARB_DEBUG29", 29, 29, &umr_bitfield_default },
+	 { "SEQ_RDY_POP_IDLE", 30, 30, &umr_bitfield_default },
+	 { "TCCDL4_REPLAY_EOB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MISC[] = {
+	 { "STICKY_RFSH", 0, 0, &umr_bitfield_default },
+	 { "IDLE_RFSH", 1, 1, &umr_bitfield_default },
+	 { "STUTTER_RFSH", 2, 2, &umr_bitfield_default },
+	 { "CHAN_COUPLE", 3, 10, &umr_bitfield_default },
+	 { "HARSHNESS", 11, 18, &umr_bitfield_default },
+	 { "SMART_RDWR_SW", 19, 19, &umr_bitfield_default },
+	 { "CALI_ENABLE", 20, 20, &umr_bitfield_default },
+	 { "CALI_RATES", 21, 22, &umr_bitfield_default },
+	 { "DISPURGVLD_NOWRT", 23, 23, &umr_bitfield_default },
+	 { "DISPURG_NOSW2WR", 24, 24, &umr_bitfield_default },
+	 { "DISPURG_STALL", 25, 25, &umr_bitfield_default },
+	 { "DISPURG_THROTTLE", 26, 29, &umr_bitfield_default },
+	 { "EXTEND_WEIGHT", 30, 30, &umr_bitfield_default },
+	 { "ACPURG_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BANKMAP[] = {
+	 { "BANK0", 0, 3, &umr_bitfield_default },
+	 { "BANK1", 4, 7, &umr_bitfield_default },
+	 { "BANK2", 8, 11, &umr_bitfield_default },
+	 { "BANK3", 12, 15, &umr_bitfield_default },
+	 { "RANK", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RAMCFG[] = {
+	 { "NOOFBANK", 0, 1, &umr_bitfield_default },
+	 { "NOOFRANKS", 2, 2, &umr_bitfield_default },
+	 { "NOOFROWS", 3, 5, &umr_bitfield_default },
+	 { "NOOFCOLS", 6, 7, &umr_bitfield_default },
+	 { "CHANSIZE", 8, 8, &umr_bitfield_default },
+	 { "RSV_1", 9, 9, &umr_bitfield_default },
+	 { "RSV_2", 10, 10, &umr_bitfield_default },
+	 { "RSV_3", 11, 11, &umr_bitfield_default },
+	 { "NOOFGROUPS", 12, 12, &umr_bitfield_default },
+	 { "RSV_4", 13, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_POP[] = {
+	 { "ENABLE_ARB", 0, 0, &umr_bitfield_default },
+	 { "SPEC_OPEN", 1, 1, &umr_bitfield_default },
+	 { "POP_DEPTH", 2, 5, &umr_bitfield_default },
+	 { "WRDATAINDEX_DEPTH", 6, 11, &umr_bitfield_default },
+	 { "SKID_DEPTH", 12, 14, &umr_bitfield_default },
+	 { "WAIT_AFTER_RFSH", 15, 16, &umr_bitfield_default },
+	 { "QUICK_STOP", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_PAGE", 18, 18, &umr_bitfield_default },
+	 { "ALLOW_EOB_BY_WRRET_STALL", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MINCLKS[] = {
+	 { "READ_CLKS", 0, 7, &umr_bitfield_default },
+	 { "WRITE_CLKS", 8, 15, &umr_bitfield_default },
+	 { "ARB_RW_SWITCH", 16, 16, &umr_bitfield_default },
+	 { "RW_SWITCH_HARSH", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_SQM_CNTL[] = {
+	 { "MIN_PENAL", 0, 7, &umr_bitfield_default },
+	 { "DYN_SQM_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "SQM_RDY16", 9, 9, &umr_bitfield_default },
+	 { "SQM_RESERVE", 10, 15, &umr_bitfield_default },
+	 { "RATIO", 16, 23, &umr_bitfield_default },
+	 { "RATIO_DEBUG", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_ADDR_HASH[] = {
+	 { "BANK_XOR_ENABLE", 0, 3, &umr_bitfield_default },
+	 { "COL_XOR", 4, 11, &umr_bitfield_default },
+	 { "ROW_XOR", 12, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2[] = {
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_RD[] = {
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "ACP_HARSH_PRI", 11, 11, &umr_bitfield_default },
+	 { "ACP_OVER_DISP", 12, 12, &umr_bitfield_default },
+	 { "FORCE_ACP_URG", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_CNTL_WR[] = {
+	 { "WTMODE", 0, 1, &umr_bitfield_default },
+	 { "HARSH_PRI", 2, 2, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP0", 3, 3, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP1", 4, 4, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP2", 5, 5, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP3", 6, 6, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP4", 7, 7, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP5", 8, 8, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP6", 9, 9, &umr_bitfield_default },
+	 { "ALLOW_STUTTER_GRP7", 10, 10, &umr_bitfield_default },
+	 { "ACP_HARSH_PRI", 11, 11, &umr_bitfield_default },
+	 { "ACP_OVER_DISP", 12, 12, &umr_bitfield_default },
+	 { "FORCE_ACP_URG", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_RD[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_WTM_GRPWT_WR[] = {
+	 { "GRP0", 0, 1, &umr_bitfield_default },
+	 { "GRP1", 2, 3, &umr_bitfield_default },
+	 { "GRP2", 4, 5, &umr_bitfield_default },
+	 { "GRP3", 6, 7, &umr_bitfield_default },
+	 { "GRP4", 8, 9, &umr_bitfield_default },
+	 { "GRP5", 10, 11, &umr_bitfield_default },
+	 { "GRP6", 12, 13, &umr_bitfield_default },
+	 { "GRP7", 14, 15, &umr_bitfield_default },
+	 { "GRP_EXT", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_RD[] = {
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_TM_CNTL_WR[] = {
+	 { "GROUPBY_RANK", 0, 0, &umr_bitfield_default },
+	 { "BANK_SELECT", 1, 2, &umr_bitfield_default },
+	 { "MATCH_RANK", 3, 3, &umr_bitfield_default },
+	 { "MATCH_BANK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LAZY1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_RD[] = {
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_AGE_WR[] = {
+	 { "RATE_GROUP0", 0, 1, &umr_bitfield_default },
+	 { "RATE_GROUP1", 2, 3, &umr_bitfield_default },
+	 { "RATE_GROUP2", 4, 5, &umr_bitfield_default },
+	 { "RATE_GROUP3", 6, 7, &umr_bitfield_default },
+	 { "RATE_GROUP4", 8, 9, &umr_bitfield_default },
+	 { "RATE_GROUP5", 10, 11, &umr_bitfield_default },
+	 { "RATE_GROUP6", 12, 13, &umr_bitfield_default },
+	 { "RATE_GROUP7", 14, 15, &umr_bitfield_default },
+	 { "ENABLE_GROUP0", 16, 16, &umr_bitfield_default },
+	 { "ENABLE_GROUP1", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_GROUP2", 18, 18, &umr_bitfield_default },
+	 { "ENABLE_GROUP3", 19, 19, &umr_bitfield_default },
+	 { "ENABLE_GROUP4", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_GROUP5", 21, 21, &umr_bitfield_default },
+	 { "ENABLE_GROUP6", 22, 22, &umr_bitfield_default },
+	 { "ENABLE_GROUP7", 23, 23, &umr_bitfield_default },
+	 { "DIVIDE_GROUP0", 24, 24, &umr_bitfield_default },
+	 { "DIVIDE_GROUP1", 25, 25, &umr_bitfield_default },
+	 { "DIVIDE_GROUP2", 26, 26, &umr_bitfield_default },
+	 { "DIVIDE_GROUP3", 27, 27, &umr_bitfield_default },
+	 { "DIVIDE_GROUP4", 28, 28, &umr_bitfield_default },
+	 { "DIVIDE_GROUP5", 29, 29, &umr_bitfield_default },
+	 { "DIVIDE_GROUP6", 30, 30, &umr_bitfield_default },
+	 { "DIVIDE_GROUP7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "URG0", 1, 5, &umr_bitfield_default },
+	 { "URG1", 6, 10, &umr_bitfield_default },
+	 { "ACCUM", 11, 11, &umr_bitfield_default },
+	 { "SINGLE_BANK", 12, 12, &umr_bitfield_default },
+	 { "PUSH_SINGLE_BANK_REFRESH", 13, 13, &umr_bitfield_default },
+	 { "PENDING_RATE_SEL", 14, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RFSH_RATE[] = {
+	 { "POWERMODE0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_PM_CNTL[] = {
+	 { "OVERRIDE_CGSTATE", 0, 1, &umr_bitfield_default },
+	 { "OVRR_CGRFSH", 2, 2, &umr_bitfield_default },
+	 { "OVRR_CGSQM", 3, 3, &umr_bitfield_default },
+	 { "SRFSH_ON_D1", 4, 4, &umr_bitfield_default },
+	 { "BLKOUT_ON_D1", 5, 5, &umr_bitfield_default },
+	 { "IDLE_ON_D1", 6, 6, &umr_bitfield_default },
+	 { "OVRR_PM", 7, 7, &umr_bitfield_default },
+	 { "OVRR_PM_STATE", 8, 9, &umr_bitfield_default },
+	 { "OVRR_RD", 10, 10, &umr_bitfield_default },
+	 { "OVRR_RD_STATE", 11, 11, &umr_bitfield_default },
+	 { "OVRR_WR", 12, 12, &umr_bitfield_default },
+	 { "OVRR_WR_STATE", 13, 13, &umr_bitfield_default },
+	 { "OVRR_RFSH", 14, 14, &umr_bitfield_default },
+	 { "OVRR_RFSH_STATE", 15, 15, &umr_bitfield_default },
+	 { "OVRR_RD0_BUSY", 16, 16, &umr_bitfield_default },
+	 { "OVRR_RD1_BUSY", 17, 17, &umr_bitfield_default },
+	 { "IDLE_ON_D2", 18, 18, &umr_bitfield_default },
+	 { "IDLE_ON_D3", 19, 19, &umr_bitfield_default },
+	 { "IDLE_CNT", 20, 23, &umr_bitfield_default },
+	 { "OVRR_WR0_BUSY", 24, 24, &umr_bitfield_default },
+	 { "OVRR_WR1_BUSY", 25, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_RD_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GDEC_WR_CNTL[] = {
+	 { "PAGEBIT0", 0, 3, &umr_bitfield_default },
+	 { "PAGEBIT1", 4, 7, &umr_bitfield_default },
+	 { "USE_RANK", 8, 8, &umr_bitfield_default },
+	 { "USE_RSNO", 9, 9, &umr_bitfield_default },
+	 { "REM_DEFAULT_GRP", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_RD[] = {
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_LM_WR[] = {
+	 { "STREAK_LIMIT", 0, 7, &umr_bitfield_default },
+	 { "STREAK_LIMIT_UBER", 8, 15, &umr_bitfield_default },
+	 { "STREAK_BREAK", 16, 16, &umr_bitfield_default },
+	 { "STREAK_UBER", 17, 17, &umr_bitfield_default },
+	 { "ENABLE_TWO_LIST", 18, 18, &umr_bitfield_default },
+	 { "POPIDLE_RST_TWOLIST", 19, 19, &umr_bitfield_default },
+	 { "SKID1_RST_TWOLIST", 20, 20, &umr_bitfield_default },
+	 { "BANKGROUP_CONFIG", 21, 23, &umr_bitfield_default },
+	 { "MASKWR_LM_EOB", 24, 24, &umr_bitfield_default },
+	 { "ATOMIC_LM_EOB", 25, 25, &umr_bitfield_default },
+	 { "ATOMIC_RTN_LM_EOB", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REMREQ[] = {
+	 { "RD_WATER", 0, 7, &umr_bitfield_default },
+	 { "WR_WATER", 8, 15, &umr_bitfield_default },
+	 { "WR_MAXBURST_SIZE", 16, 19, &umr_bitfield_default },
+	 { "WR_LAZY_TIMER", 20, 23, &umr_bitfield_default },
+	 { "ENABLE_REMOTE_NACK_REQ", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_REPLAY[] = {
+	 { "ENABLE_RD", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_WR", 1, 1, &umr_bitfield_default },
+	 { "WRACK_MODE", 2, 2, &umr_bitfield_default },
+	 { "WAW_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "RAW_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "IGNORE_WR_CDC", 5, 5, &umr_bitfield_default },
+	 { "BREAK_ON_STALL", 6, 6, &umr_bitfield_default },
+	 { "BOS_ENABLE_WAIT_CYC", 7, 7, &umr_bitfield_default },
+	 { "BOS_WAIT_CYC", 8, 14, &umr_bitfield_default },
+	 { "NO_PCH_AT_REPLAY_START", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_RD[] = {
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "DISP", 16, 23, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_RET_CREDITS_WR[] = {
+	 { "LCL", 0, 7, &umr_bitfield_default },
+	 { "HUB", 8, 15, &umr_bitfield_default },
+	 { "RETURN_CREDIT", 16, 23, &umr_bitfield_default },
+	 { "WRRET_SEQ_SKID", 24, 27, &umr_bitfield_default },
+	 { "WRRET_BP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_CID[] = {
+	 { "CID_CH0", 0, 7, &umr_bitfield_default },
+	 { "CID_CH1", 8, 15, &umr_bitfield_default },
+	 { "WRITE_CH0", 16, 16, &umr_bitfield_default },
+	 { "WRITE_CH1", 17, 17, &umr_bitfield_default },
+	 { "REALTIME_CH0", 18, 18, &umr_bitfield_default },
+	 { "REALTIME_CH1", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_RSLT0[] = {
+	 { "MAX_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_MAX_LAT_RSLT1[] = {
+	 { "MAX_LATENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_REALTIME_RD[] = {
+	 { "CB0", 0, 0, &umr_bitfield_default },
+	 { "CBCMASK0", 1, 1, &umr_bitfield_default },
+	 { "CBFMASK0", 2, 2, &umr_bitfield_default },
+	 { "DB0", 3, 3, &umr_bitfield_default },
+	 { "DBHTILE0", 4, 4, &umr_bitfield_default },
+	 { "DBSTEN0", 5, 5, &umr_bitfield_default },
+	 { "TC0", 6, 6, &umr_bitfield_default },
+	 { "IA", 7, 7, &umr_bitfield_default },
+	 { "ACPG", 8, 8, &umr_bitfield_default },
+	 { "ACPO", 9, 9, &umr_bitfield_default },
+	 { "DMIF", 10, 10, &umr_bitfield_default },
+	 { "DMIF_EXT0", 11, 11, &umr_bitfield_default },
+	 { "DMIF_EXT1", 12, 12, &umr_bitfield_default },
+	 { "DMIF_TW", 13, 13, &umr_bitfield_default },
+	 { "MCIF", 14, 14, &umr_bitfield_default },
+	 { "RLC", 15, 15, &umr_bitfield_default },
+	 { "VMC", 16, 16, &umr_bitfield_default },
+	 { "SDMA1", 17, 17, &umr_bitfield_default },
+	 { "SMU", 18, 18, &umr_bitfield_default },
+	 { "VCE0", 19, 19, &umr_bitfield_default },
+	 { "VCE1", 20, 20, &umr_bitfield_default },
+	 { "XDMAM", 21, 21, &umr_bitfield_default },
+	 { "SDMA0", 22, 22, &umr_bitfield_default },
+	 { "HDP", 23, 23, &umr_bitfield_default },
+	 { "UMC", 24, 24, &umr_bitfield_default },
+	 { "UVD", 25, 25, &umr_bitfield_default },
+	 { "UVD_EXT0", 26, 26, &umr_bitfield_default },
+	 { "UVD_EXT1", 27, 27, &umr_bitfield_default },
+	 { "SEM", 28, 28, &umr_bitfield_default },
+	 { "SAMMSP", 29, 29, &umr_bitfield_default },
+	 { "VP8", 30, 30, &umr_bitfield_default },
+	 { "ISP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_CG[] = {
+	 { "CG_ARB_REQ", 0, 7, &umr_bitfield_default },
+	 { "CG_ARB_RESP", 8, 15, &umr_bitfield_default },
+	 { "RSV_0", 16, 23, &umr_bitfield_default },
+	 { "RSV_1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_REALTIME_WR[] = {
+	 { "CB0", 0, 0, &umr_bitfield_default },
+	 { "CBCMASK0", 1, 1, &umr_bitfield_default },
+	 { "CBFMASK0", 2, 2, &umr_bitfield_default },
+	 { "CBIMMED0", 3, 3, &umr_bitfield_default },
+	 { "DB0", 4, 4, &umr_bitfield_default },
+	 { "DBHTILE0", 5, 5, &umr_bitfield_default },
+	 { "DBSTEN0", 6, 6, &umr_bitfield_default },
+	 { "TC0", 7, 7, &umr_bitfield_default },
+	 { "SH", 8, 8, &umr_bitfield_default },
+	 { "ACPG", 9, 9, &umr_bitfield_default },
+	 { "ACPO", 10, 10, &umr_bitfield_default },
+	 { "MCIF", 11, 11, &umr_bitfield_default },
+	 { "RLC", 12, 12, &umr_bitfield_default },
+	 { "SDMA1", 13, 13, &umr_bitfield_default },
+	 { "SMU", 14, 14, &umr_bitfield_default },
+	 { "VCE0", 15, 15, &umr_bitfield_default },
+	 { "VCE1", 16, 16, &umr_bitfield_default },
+	 { "SAMMSP", 17, 17, &umr_bitfield_default },
+	 { "XDMA", 18, 18, &umr_bitfield_default },
+	 { "XDMAM", 19, 19, &umr_bitfield_default },
+	 { "SDMA0", 20, 20, &umr_bitfield_default },
+	 { "HDP", 21, 21, &umr_bitfield_default },
+	 { "UMC", 22, 22, &umr_bitfield_default },
+	 { "UVD", 23, 23, &umr_bitfield_default },
+	 { "UVD_EXT0", 24, 24, &umr_bitfield_default },
+	 { "UVD_EXT1", 25, 25, &umr_bitfield_default },
+	 { "XDP", 26, 26, &umr_bitfield_default },
+	 { "SEM", 27, 27, &umr_bitfield_default },
+	 { "IH", 28, 28, &umr_bitfield_default },
+	 { "VP8", 29, 29, &umr_bitfield_default },
+	 { "ISP", 30, 30, &umr_bitfield_default },
+	 { "VIN0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING_1[] = {
+	 { "ACTRD", 0, 7, &umr_bitfield_default },
+	 { "ACTWR", 8, 15, &umr_bitfield_default },
+	 { "RASMACTRD", 16, 23, &umr_bitfield_default },
+	 { "RASMACTWR", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BUSY_STATUS[] = {
+	 { "LM_RD0", 0, 0, &umr_bitfield_default },
+	 { "LM_RD1", 1, 1, &umr_bitfield_default },
+	 { "LM_WR0", 2, 2, &umr_bitfield_default },
+	 { "LM_WR1", 3, 3, &umr_bitfield_default },
+	 { "HM_RD0", 4, 4, &umr_bitfield_default },
+	 { "HM_RD1", 5, 5, &umr_bitfield_default },
+	 { "HM_WR0", 6, 6, &umr_bitfield_default },
+	 { "HM_WR1", 7, 7, &umr_bitfield_default },
+	 { "WDE_RD0", 8, 8, &umr_bitfield_default },
+	 { "WDE_RD1", 9, 9, &umr_bitfield_default },
+	 { "WDE_WR0", 10, 10, &umr_bitfield_default },
+	 { "WDE_WR1", 11, 11, &umr_bitfield_default },
+	 { "POP0", 12, 12, &umr_bitfield_default },
+	 { "POP1", 13, 13, &umr_bitfield_default },
+	 { "TAGFIFO0", 14, 14, &umr_bitfield_default },
+	 { "TAGFIFO1", 15, 15, &umr_bitfield_default },
+	 { "REPLAY0", 16, 16, &umr_bitfield_default },
+	 { "REPLAY1", 17, 17, &umr_bitfield_default },
+	 { "RDRET0", 18, 18, &umr_bitfield_default },
+	 { "RDRET1", 19, 19, &umr_bitfield_default },
+	 { "GECC2_RD0", 20, 20, &umr_bitfield_default },
+	 { "GECC2_RD1", 21, 21, &umr_bitfield_default },
+	 { "GECC2_WR0", 22, 22, &umr_bitfield_default },
+	 { "GECC2_WR1", 23, 23, &umr_bitfield_default },
+	 { "WRRET0", 24, 24, &umr_bitfield_default },
+	 { "WRRET1", 25, 25, &umr_bitfield_default },
+	 { "RTT0", 26, 26, &umr_bitfield_default },
+	 { "RTT1", 27, 27, &umr_bitfield_default },
+	 { "REM_RD0", 28, 28, &umr_bitfield_default },
+	 { "REM_RD1", 29, 29, &umr_bitfield_default },
+	 { "REM_WR0", 30, 30, &umr_bitfield_default },
+	 { "REM_WR1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_DRAM_TIMING2_1[] = {
+	 { "RAS2RAS", 0, 7, &umr_bitfield_default },
+	 { "RP", 8, 15, &umr_bitfield_default },
+	 { "WRPLUSRP", 16, 23, &umr_bitfield_default },
+	 { "BUS_TURN", 24, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB2[] = {
+	 { "REALTIME_GRP_RD", 0, 7, &umr_bitfield_default },
+	 { "REALTIME_GRP_WR", 8, 15, &umr_bitfield_default },
+	 { "DISP_RD_STALL_EN", 16, 16, &umr_bitfield_default },
+	 { "ACP_RD_STALL_EN", 17, 17, &umr_bitfield_default },
+	 { "UVD_RD_STALL_EN", 18, 18, &umr_bitfield_default },
+	 { "VCE0_RD_STALL_EN", 19, 19, &umr_bitfield_default },
+	 { "VCE1_RD_STALL_EN", 20, 20, &umr_bitfield_default },
+	 { "REALTIME_RD_WTS", 21, 21, &umr_bitfield_default },
+	 { "REALTIME_WR_WTS", 22, 22, &umr_bitfield_default },
+	 { "URGENT_BY_DISP_STALL", 23, 23, &umr_bitfield_default },
+	 { "PROMOTE_BY_DMIF_URG", 24, 24, &umr_bitfield_default },
+	 { "PRIORITY_URGENT_OUTSTANDING_ONLY_RD", 25, 25, &umr_bitfield_default },
+	 { "PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD", 26, 26, &umr_bitfield_default },
+	 { "PRIORITY_URGENT_OUTSTANDING_ONLY_WR", 27, 27, &umr_bitfield_default },
+	 { "PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_BURST_TIME[] = {
+	 { "STATE0", 0, 4, &umr_bitfield_default },
+	 { "STATE1", 5, 9, &umr_bitfield_default },
+	 { "STATE2", 10, 14, &umr_bitfield_default },
+	 { "STATE3", 15, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CS0_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CS0_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CS1_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CS1_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CS2_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CS2_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CS3_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CS3_BASE[] = {
+	 { "CSENABLE", 0, 0, &umr_bitfield_default },
+	 { "BASEADDR21_11", 5, 15, &umr_bitfield_default },
+	 { "BASEADDR38_27", 19, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_BANK_ADDR_MAPPING[] = {
+	 { "DIMM0ADDRMAP", 0, 3, &umr_bitfield_default },
+	 { "DIMM1ADDRMAP", 4, 7, &umr_bitfield_default },
+	 { "BANKSWIZZLEMODE", 8, 8, &umr_bitfield_default },
+	 { "BANKSWAP", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_BANK_ADDR_MAPPING[] = {
+	 { "DIMM0ADDRMAP", 0, 3, &umr_bitfield_default },
+	 { "DIMM1ADDRMAP", 4, 7, &umr_bitfield_default },
+	 { "BANKSWIZZLEMODE", 8, 8, &umr_bitfield_default },
+	 { "BANKSWAP", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CTL_BASE[] = {
+	 { "DCTSEL", 0, 2, &umr_bitfield_default },
+	 { "DCTINTLVEN", 3, 6, &umr_bitfield_default },
+	 { "DCTBASEADDR", 7, 27, &umr_bitfield_default },
+	 { "DCTOFFSETEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CTL_BASE[] = {
+	 { "DCTSEL", 0, 2, &umr_bitfield_default },
+	 { "DCTINTLVEN", 3, 6, &umr_bitfield_default },
+	 { "DCTBASEADDR", 7, 27, &umr_bitfield_default },
+	 { "DCTOFFSETEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM0_CTL_LIMIT[] = {
+	 { "DCTLIMITADDR", 0, 20, &umr_bitfield_default },
+	 { "DRAMHOLEVALID", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM1_CTL_LIMIT[] = {
+	 { "DCTLIMITADDR", 0, 20, &umr_bitfield_default },
+	 { "DRAMHOLEVALID", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_CTL_HIGH_01[] = {
+	 { "DCTHIGHADDROFF0", 0, 11, &umr_bitfield_default },
+	 { "DCTHIGHADDROFF1", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_CTL_HIGH_23[] = {
+	 { "DCTHIGHADDROFF2", 0, 11, &umr_bitfield_default },
+	 { "DCTHIGHADDROFF3", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_MODE[] = {
+	 { "DCTSELINTLVADDR", 0, 2, &umr_bitfield_default },
+	 { "DRAMTYPE", 3, 5, &umr_bitfield_default },
+	 { "DRAMHOLEOFFSET", 6, 14, &umr_bitfield_default },
+	 { "DDR3LPX32", 15, 15, &umr_bitfield_default },
+	 { "BANKGROUPSWAP", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_APER_BASE[] = {
+	 { "BASE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_APER_TOP[] = {
+	 { "TOP", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_DRAM_APER_DEF[] = {
+	 { "DEF", 0, 27, &umr_bitfield_default },
+	 { "LOCK_MC_FUS_DRAM_REGS", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_ARB_GARLIC_ISOC_PRI[] = {
+	 { "DMIF_RD_TOKURG_EN", 0, 0, &umr_bitfield_default },
+	 { "UVD_RD_TOKURG_EN", 1, 1, &umr_bitfield_default },
+	 { "VCE_RD_TOKURG_EN", 2, 2, &umr_bitfield_default },
+	 { "ACP_RD_TOKURG_EN", 3, 3, &umr_bitfield_default },
+	 { "DMIF_RD_PRIURG_EN", 4, 4, &umr_bitfield_default },
+	 { "UVD_RD_PRIURG_EN", 5, 5, &umr_bitfield_default },
+	 { "VCE_RD_PRIURG_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_RD_PRIURG_EN", 7, 7, &umr_bitfield_default },
+	 { "DMIF_RD_ISOC_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_RD_ISOC_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_RD_ISOC_EN", 10, 10, &umr_bitfield_default },
+	 { "MCIF_RD_ISOC_EN", 11, 11, &umr_bitfield_default },
+	 { "UMC_RD_ISOC_EN", 12, 12, &umr_bitfield_default },
+	 { "VCEU_RD_ISOC_EN", 13, 13, &umr_bitfield_default },
+	 { "ACP_RD_ISOC_EN", 14, 14, &umr_bitfield_default },
+	 { "REQPRI_OVERRIDE_EN", 15, 15, &umr_bitfield_default },
+	 { "REQPRI_OVERRIDE_VAL", 16, 17, &umr_bitfield_default },
+	 { "PRIPRMTE_OVERRIDE_EN", 18, 18, &umr_bitfield_default },
+	 { "TOKURG_OVERRIDE_EN", 19, 19, &umr_bitfield_default },
+	 { "PRIURG_OVERRIDE_EN", 20, 20, &umr_bitfield_default },
+	 { "PRIPRMTE_OVERRIDE_VAL", 21, 21, &umr_bitfield_default },
+	 { "TOKURG_OVERRIDE_VAL", 22, 22, &umr_bitfield_default },
+	 { "PRIURG_OVERRIDE_VAL", 23, 23, &umr_bitfield_default },
+	 { "GARLIC_REQ_CREDITS", 24, 28, &umr_bitfield_default },
+	 { "MM_REL_LATE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_ARB_GARLIC_CNTL[] = {
+	 { "RX_RDRESP_FIFO_PTR_INIT_VALUE", 0, 7, &umr_bitfield_default },
+	 { "RX_WRRESP_FIFO_PTR_INIT_VALUE", 8, 14, &umr_bitfield_default },
+	 { "EN_64_BYTE_WRITE", 15, 15, &umr_bitfield_default },
+	 { "EDC_RESPONSE_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OUTSTANDING_RDRESP_LIMIT", 17, 25, &umr_bitfield_default },
+	 { "OUTSTANDING_WRRESP_LIMIT", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_ARB_GARLIC_WR_PRI[] = {
+	 { "CB_WR_PRI", 0, 1, &umr_bitfield_default },
+	 { "DB_WR_PRI", 2, 3, &umr_bitfield_default },
+	 { "TC_WR_PRI", 4, 5, &umr_bitfield_default },
+	 { "CP_WR_PRI", 6, 7, &umr_bitfield_default },
+	 { "HDP_WR_PRI", 8, 9, &umr_bitfield_default },
+	 { "XDP_WR_PRI", 10, 11, &umr_bitfield_default },
+	 { "UMC_WR_PRI", 12, 13, &umr_bitfield_default },
+	 { "UVD_WR_PRI", 14, 15, &umr_bitfield_default },
+	 { "RLC_WR_PRI", 16, 17, &umr_bitfield_default },
+	 { "IH_WR_PRI", 18, 19, &umr_bitfield_default },
+	 { "SDMA_WR_PRI", 20, 21, &umr_bitfield_default },
+	 { "SEM_WR_PRI", 22, 23, &umr_bitfield_default },
+	 { "SH_WR_PRI", 24, 25, &umr_bitfield_default },
+	 { "MCIF_WR_PRI", 26, 27, &umr_bitfield_default },
+	 { "VCE_WR_PRI", 28, 29, &umr_bitfield_default },
+	 { "VCEU_WR_PRI", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_FUS_ARB_GARLIC_WR_PRI2[] = {
+	 { "SMU_WR_PRI", 0, 1, &umr_bitfield_default },
+	 { "SAM_WR_PRI", 2, 3, &umr_bitfield_default },
+	 { "ACP_WR_PRI", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_CG_DATAPORT[] = {
+	 { "DATA_FIELD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_PROBE_MAP[] = {
+	 { "ADDR0_TO_TC_MAP", 0, 1, &umr_bitfield_default },
+	 { "ADDR1_TO_TC_MAP", 2, 3, &umr_bitfield_default },
+	 { "ADDR2_TO_TC_MAP", 4, 5, &umr_bitfield_default },
+	 { "ADDR3_TO_TC_MAP", 6, 7, &umr_bitfield_default },
+	 { "ADDR0_TO_GRUB_MAP", 8, 8, &umr_bitfield_default },
+	 { "ADDR1_TO_GRUB_MAP", 9, 9, &umr_bitfield_default },
+	 { "ADDR2_TO_GRUB_MAP", 10, 10, &umr_bitfield_default },
+	 { "ADDR3_TO_GRUB_MAP", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_POST_PROBE_DELAY[] = {
+	 { "REQ_TO_RSP_DELAY", 0, 4, &umr_bitfield_default },
+	 { "REQLCL_TO_RET_DELAY", 8, 12, &umr_bitfield_default },
+	 { "REQREM_TO_RET_DELAY", 16, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_PROBE_CREDITS[] = {
+	 { "CREDITS_LIMIT_LO", 0, 5, &umr_bitfield_default },
+	 { "CREDITS_LIMIT_HI", 8, 13, &umr_bitfield_default },
+	 { "INTPRB_FIFO_LEVEL", 15, 15, &umr_bitfield_default },
+	 { "INTPRB_TIMEOUT_THRESH", 16, 18, &umr_bitfield_default },
+	 { "MEM_TIMEOUT_THRESH", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_FEATURES[] = {
+	 { "WR_COMBINE_OFF", 0, 0, &umr_bitfield_default },
+	 { "SCLK_CG_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "PRB_FILTER_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "ARB_NRT_STACK_DISABLE", 3, 3, &umr_bitfield_default },
+	 { "ARB_FIXED_PRIORITY", 4, 4, &umr_bitfield_default },
+	 { "PRIORITY_UPDATE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "RT_BYPASS_OFF", 6, 6, &umr_bitfield_default },
+	 { "SYNC_ON_ERROR_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "SYNC_REFLECT_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "ARB_STALL_EN", 10, 10, &umr_bitfield_default },
+	 { "CREDIT_STALL_EN", 11, 11, &umr_bitfield_default },
+	 { "ARB_STALL_SET_SEL", 12, 13, &umr_bitfield_default },
+	 { "ARB_STALL_CLR_SEL", 14, 15, &umr_bitfield_default },
+	 { "CREDIT_STALL_SET_SEL", 16, 17, &umr_bitfield_default },
+	 { "CREDIT_STALL_CLR_SEL", 18, 19, &umr_bitfield_default },
+	 { "WR_REORDER_OFF", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_TX_CREDITS[] = {
+	 { "SRCTAG_LIMIT", 0, 5, &umr_bitfield_default },
+	 { "SRCTAG_RT_RESERVE", 8, 11, &umr_bitfield_default },
+	 { "NPC_RT_RESERVE", 12, 15, &umr_bitfield_default },
+	 { "NPD_RT_RESERVE", 16, 19, &umr_bitfield_default },
+	 { "TX_FIFO_DEPTH", 20, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_TCB_INDEX[] = {
+	 { "INDEX", 0, 6, &umr_bitfield_default },
+	 { "TCB0_WR_EN", 8, 8, &umr_bitfield_default },
+	 { "TCB1_WR_EN", 9, 9, &umr_bitfield_default },
+	 { "RD_EN", 10, 10, &umr_bitfield_default },
+	 { "TCB_SEL", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_TCB_DATA_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_GRUB_TCB_DATA_HI[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ADDR_DEC[] = {
+	 { "NO_DIV_BY_3", 0, 0, &umr_bitfield_default },
+	 { "GECC", 1, 1, &umr_bitfield_default },
+	 { "RB_SPLIT", 2, 2, &umr_bitfield_default },
+	 { "RB_SPLIT_COLHI", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_REMOTE[] = {
+	 { "WRREQ_EN_GOQ", 0, 0, &umr_bitfield_default },
+	 { "RDREQ_EN_GOQ", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDREQ_PRI_CREDIT[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_WRRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+	 { "HUB_LP_RDRET_SKID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT1[] = {
+	 { "OUT0", 0, 7, &umr_bitfield_default },
+	 { "OUT1", 8, 15, &umr_bitfield_default },
+	 { "OUT2", 16, 23, &umr_bitfield_default },
+	 { "OUT3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_RDRET_PRI_CREDIT2[] = {
+	 { "OUT4", 0, 7, &umr_bitfield_default },
+	 { "OUT5", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_CHTRIREMAP[] = {
+	 { "CH0", 0, 1, &umr_bitfield_default },
+	 { "CH1", 2, 3, &umr_bitfield_default },
+	 { "CH2", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_TWOCHAN[] = {
+	 { "DISABLE_ONEPORT", 0, 0, &umr_bitfield_default },
+	 { "CH0", 1, 2, &umr_bitfield_default },
+	 { "CH1", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB[] = {
+	 { "HUBRD_HIGHEST", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_HUB_STALL_HIGHEST", 1, 1, &umr_bitfield_default },
+	 { "BREAK_BURST_CID_CHANGE", 2, 2, &umr_bitfield_default },
+	 { "ACP_RDRET_URG", 3, 3, &umr_bitfield_default },
+	 { "HDP_RDRET_URG", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_ARB_MAX_BURST[] = {
+	 { "RD_PORT0", 0, 3, &umr_bitfield_default },
+	 { "RD_PORT1", 4, 7, &umr_bitfield_default },
+	 { "RD_PORT2", 8, 11, &umr_bitfield_default },
+	 { "RD_PORT3", 12, 15, &umr_bitfield_default },
+	 { "WR_PORT0", 16, 19, &umr_bitfield_default },
+	 { "WR_PORT1", 20, 23, &umr_bitfield_default },
+	 { "WR_PORT2", 24, 27, &umr_bitfield_default },
+	 { "WR_PORT3", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_CNTL0[] = {
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_CNTL1[] = {
+	 { "THRESH_CNTR_ID", 0, 7, &umr_bitfield_default },
+	 { "START_TRIG_ID", 8, 15, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_CNTL2[] = {
+	 { "MON0_ID", 0, 7, &umr_bitfield_default },
+	 { "MON1_ID", 8, 15, &umr_bitfield_default },
+	 { "MON2_ID", 16, 23, &umr_bitfield_default },
+	 { "MON3_ID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_RSLT2[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_RSLT3[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_FIFO_MON_MAX_THSH[] = {
+	 { "MON0", 0, 7, &umr_bitfield_default },
+	 { "MON1", 8, 15, &umr_bitfield_default },
+	 { "MON2", 16, 23, &umr_bitfield_default },
+	 { "MON3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE0[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_XBAR_SPARE1[] = {
+	 { "BIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_LOW_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_HIGH_ADDR[] = {
+	 { "VIRTUAL_PAGE_NUMBER", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL[] = {
+	 { "ATS_ACCESS_MODE", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE0_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VM_APERTURE1_CNTL2[] = {
+	 { "VMIDS_USING_RANGE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_CNTL[] = {
+	 { "DISABLE_ATC", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_PRI", 1, 1, &umr_bitfield_default },
+	 { "DISABLE_PASID", 2, 2, &umr_bitfield_default },
+	 { "CREDITS_ATS_RPB", 8, 13, &umr_bitfield_default },
+	 { "DEBUG_ECO", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEBUG[] = {
+	 { "INVALIDATE_ALL", 0, 0, &umr_bitfield_default },
+	 { "IDENT_RETURN", 1, 1, &umr_bitfield_default },
+	 { "ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS", 2, 2, &umr_bitfield_default },
+	 { "PAGE_REQUESTS_USE_RELAXED_ORDERING", 5, 5, &umr_bitfield_default },
+	 { "PRIV_BIT", 6, 6, &umr_bitfield_default },
+	 { "EXE_BIT", 7, 7, &umr_bitfield_default },
+	 { "PAGE_REQUEST_PERMS", 8, 8, &umr_bitfield_default },
+	 { "UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE", 9, 9, &umr_bitfield_default },
+	 { "NUM_REQUESTS_AT_ERR", 10, 13, &umr_bitfield_default },
+	 { "DISALLOW_ERR_TO_DONE", 14, 14, &umr_bitfield_default },
+	 { "IGNORE_FED", 15, 15, &umr_bitfield_default },
+	 { "INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED", 16, 16, &umr_bitfield_default },
+	 { "DEBUG_BUS_SELECT", 17, 17, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_PER_DOMAIN", 18, 18, &umr_bitfield_default },
+	 { "DISABLE_VMID0_PASID_MAPPING", 19, 19, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATION_ON_WORLD_SWITCH", 20, 20, &umr_bitfield_default },
+	 { "ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_DEBUG[] = {
+	 { "CREDITS_ATS_IH", 0, 4, &umr_bitfield_default },
+	 { "ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES", 8, 8, &umr_bitfield_default },
+	 { "CLEAR_FAULT_STATUS_ADDR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "CRASHED", 1, 1, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_CNTL[] = {
+	 { "FAULT_REGISTER_LOG", 0, 8, &umr_bitfield_default },
+	 { "FAULT_INTERRUPT_TABLE", 10, 18, &umr_bitfield_default },
+	 { "FAULT_CRASH_TABLE", 20, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_INFO[] = {
+	 { "FAULT_TYPE", 0, 8, &umr_bitfield_default },
+	 { "VMID", 10, 14, &umr_bitfield_default },
+	 { "EXTRA_INFO", 15, 15, &umr_bitfield_default },
+	 { "EXTRA_INFO2", 16, 16, &umr_bitfield_default },
+	 { "INVALIDATION", 17, 17, &umr_bitfield_default },
+	 { "PAGE_REQUEST", 18, 18, &umr_bitfield_default },
+	 { "STATUS", 19, 23, &umr_bitfield_default },
+	 { "PAGE_ADDR_HIGH", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_ADDR[] = {
+	 { "PAGE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_LOW[] = {
+	 { "DEFAULT_PAGE", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_DEFAULT_PAGE_CNTL[] = {
+	 { "SEND_DEFAULT_PAGE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_FAULT_STATUS_INFO2[] = {
+	 { "VF", 0, 0, &umr_bitfield_default },
+	 { "VFID", 1, 5, &umr_bitfield_default },
+	 { "L1_ID", 9, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_MISC_CG[] = {
+	 { "OFFDLY", 6, 11, &umr_bitfield_default },
+	 { "ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MEM_LS_ENABLE", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL[] = {
+	 { "NUMBER_OF_TRANSLATION_READ_REQUESTS", 0, 1, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITE_REQUESTS", 4, 5, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD", 8, 8, &umr_bitfield_default },
+	 { "NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL2[] = {
+	 { "BANK_SELECT", 0, 5, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_MODE", 6, 7, &umr_bitfield_default },
+	 { "ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE", 8, 8, &umr_bitfield_default },
+	 { "L2_CACHE_SWAP_TAG_INDEX_LSBS", 9, 11, &umr_bitfield_default },
+	 { "L2_CACHE_VMID_MODE", 12, 14, &umr_bitfield_default },
+	 { "L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE", 15, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG[] = {
+	 { "CREDITS_L2_ATS", 0, 5, &umr_bitfield_default },
+	 { "L2_MEM_SELECT", 7, 7, &umr_bitfield_default },
+	 { "CACHE_INDEX", 8, 19, &umr_bitfield_default },
+	 { "CACHE_SELECT", 24, 24, &umr_bitfield_default },
+	 { "CACHE_BANK_SELECT", 25, 25, &umr_bitfield_default },
+	 { "CACHE_WAY_SELECT", 27, 27, &umr_bitfield_default },
+	 { "CACHE_READ", 29, 29, &umr_bitfield_default },
+	 { "CACHE_INJECT_SOFT_PARITY_ERROR", 30, 30, &umr_bitfield_default },
+	 { "CACHE_INJECT_HARD_PARITY_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_DEBUG2[] = {
+	 { "EFFECTIVE_CACHE_SIZE", 0, 4, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 5, 7, &umr_bitfield_default },
+	 { "FORCE_CACHE_MISS", 8, 8, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 9, 9, &umr_bitfield_default },
+	 { "DISABLE_2M_CACHE", 10, 10, &umr_bitfield_default },
+	 { "DISABLE_CACHING_SPECULATIVE_RETURNS", 11, 11, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 14, 14, &umr_bitfield_default },
+	 { "DEBUG_BUS_SELECT", 15, 16, &umr_bitfield_default },
+	 { "DEBUG_ECO", 17, 18, &umr_bitfield_default },
+	 { "EFFECTIVE_2M_CACHE_SIZE", 19, 22, &umr_bitfield_default },
+	 { "CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD", 23, 30, &umr_bitfield_default },
+	 { "CLEAR_PARITY_ERROR_INFO", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CACHE_DATA0[] = {
+	 { "DATA_REGISTER_VALID", 0, 0, &umr_bitfield_default },
+	 { "CACHE_ENTRY_VALID", 1, 1, &umr_bitfield_default },
+	 { "CACHED_ATTRIBUTES", 2, 24, &umr_bitfield_default },
+	 { "VIRTUAL_PAGE_ADDRESS_HIGH", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CACHE_DATA1[] = {
+	 { "VIRTUAL_PAGE_ADDRESS_LOW", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CACHE_DATA2[] = {
+	 { "PHYSICAL_PAGE_ADDRESS_LOW", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_CNTL[] = {
+	 { "DONT_NEED_ATS_BEHAVIOR", 0, 1, &umr_bitfield_default },
+	 { "NEED_ATS_BEHAVIOR", 2, 2, &umr_bitfield_default },
+	 { "NEED_ATS_SNOOP_DEFAULT", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1_ADDRESS_OFFSET[] = {
+	 { "LOGICAL_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_DEBUG_TLB[] = {
+	 { "DISABLE_FRAGMENTS", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_INVALIDATE_BY_ADDRESS_RANGE", 1, 1, &umr_bitfield_default },
+	 { "EFFECTIVE_CAM_SIZE", 4, 7, &umr_bitfield_default },
+	 { "EFFECTIVE_WORK_QUEUE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "CREDITS_L1_L2", 12, 17, &umr_bitfield_default },
+	 { "CREDITS_L1_RPB", 20, 27, &umr_bitfield_default },
+	 { "DEBUG_ECO", 28, 29, &umr_bitfield_default },
+	 { "INVALIDATE_ALL", 30, 30, &umr_bitfield_default },
+	 { "DISABLE_CACHING_FAULT_RETURNS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+	 { "CAM_PARITY_ERRORS", 12, 16, &umr_bitfield_default },
+	 { "CAM_INDEX", 17, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "DEADLOCK_DETECTION", 1, 1, &umr_bitfield_default },
+	 { "BAD_NEED_ATS", 8, 8, &umr_bitfield_default },
+	 { "CAM_PARITY_ERRORS", 12, 16, &umr_bitfield_default },
+	 { "CAM_INDEX", 17, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1RD_DEBUG2_TLB[] = {
+	 { "XNACK_RETRY_PERIOD", 0, 11, &umr_bitfield_default },
+	 { "XNACK_RETRY_MODE", 14, 15, &umr_bitfield_default },
+	 { "INJECT_SOFT_PARITY_ERROR", 16, 16, &umr_bitfield_default },
+	 { "INJECT_HARD_PARITY_ERROR", 17, 17, &umr_bitfield_default },
+	 { "CLEAR_CAM_PARITY_ERROR", 18, 18, &umr_bitfield_default },
+	 { "CAM_INDEX", 19, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L1WR_DEBUG2_TLB[] = {
+	 { "XNACK_RETRY_PERIOD", 0, 11, &umr_bitfield_default },
+	 { "XNACK_RETRY_MODE", 14, 15, &umr_bitfield_default },
+	 { "INJECT_SOFT_PARITY_ERROR", 16, 16, &umr_bitfield_default },
+	 { "INJECT_HARD_PARITY_ERROR", 17, 17, &umr_bitfield_default },
+	 { "CLEAR_CAM_PARITY_ERROR", 18, 18, &umr_bitfield_default },
+	 { "CAM_INDEX", 19, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[] = {
+	 { "VMID0_REMAPPING_FINISHED", 0, 0, &umr_bitfield_default },
+	 { "VMID1_REMAPPING_FINISHED", 1, 1, &umr_bitfield_default },
+	 { "VMID2_REMAPPING_FINISHED", 2, 2, &umr_bitfield_default },
+	 { "VMID3_REMAPPING_FINISHED", 3, 3, &umr_bitfield_default },
+	 { "VMID4_REMAPPING_FINISHED", 4, 4, &umr_bitfield_default },
+	 { "VMID5_REMAPPING_FINISHED", 5, 5, &umr_bitfield_default },
+	 { "VMID6_REMAPPING_FINISHED", 6, 6, &umr_bitfield_default },
+	 { "VMID7_REMAPPING_FINISHED", 7, 7, &umr_bitfield_default },
+	 { "VMID8_REMAPPING_FINISHED", 8, 8, &umr_bitfield_default },
+	 { "VMID9_REMAPPING_FINISHED", 9, 9, &umr_bitfield_default },
+	 { "VMID10_REMAPPING_FINISHED", 10, 10, &umr_bitfield_default },
+	 { "VMID11_REMAPPING_FINISHED", 11, 11, &umr_bitfield_default },
+	 { "VMID12_REMAPPING_FINISHED", 12, 12, &umr_bitfield_default },
+	 { "VMID13_REMAPPING_FINISHED", 13, 13, &umr_bitfield_default },
+	 { "VMID14_REMAPPING_FINISHED", 14, 14, &umr_bitfield_default },
+	 { "VMID15_REMAPPING_FINISHED", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID0_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID1_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID2_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID3_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID4_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID5_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID6_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID7_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID8_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID9_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID10_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID11_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID12_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID13_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID14_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_VMID15_PASID_MAPPING[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+	 { "NO_INVALIDATION", 30, 30, &umr_bitfield_default },
+	 { "VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_VMID_STATUS[] = {
+	 { "VMID0_OUTSTANDING", 0, 0, &umr_bitfield_default },
+	 { "VMID1_OUTSTANDING", 1, 1, &umr_bitfield_default },
+	 { "VMID2_OUTSTANDING", 2, 2, &umr_bitfield_default },
+	 { "VMID3_OUTSTANDING", 3, 3, &umr_bitfield_default },
+	 { "VMID4_OUTSTANDING", 4, 4, &umr_bitfield_default },
+	 { "VMID5_OUTSTANDING", 5, 5, &umr_bitfield_default },
+	 { "VMID6_OUTSTANDING", 6, 6, &umr_bitfield_default },
+	 { "VMID7_OUTSTANDING", 7, 7, &umr_bitfield_default },
+	 { "VMID8_OUTSTANDING", 8, 8, &umr_bitfield_default },
+	 { "VMID9_OUTSTANDING", 9, 9, &umr_bitfield_default },
+	 { "VMID10_OUTSTANDING", 10, 10, &umr_bitfield_default },
+	 { "VMID11_OUTSTANDING", 11, 11, &umr_bitfield_default },
+	 { "VMID12_OUTSTANDING", 12, 12, &umr_bitfield_default },
+	 { "VMID13_OUTSTANDING", 13, 13, &umr_bitfield_default },
+	 { "VMID14_OUTSTANDING", 14, 14, &umr_bitfield_default },
+	 { "VMID15_OUTSTANDING", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_ATS_SMU_STATUS[] = {
+	 { "VDDGFX_POWERED_DOWN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_CNTL3[] = {
+	 { "ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING", 0, 6, &umr_bitfield_default },
+	 { "ENABLE_FREE_COUNTER", 7, 7, &umr_bitfield_default },
+	 { "L2_CACHE_EVICTION_THRESHOLD", 8, 12, &umr_bitfield_default },
+	 { "DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION", 13, 13, &umr_bitfield_default },
+	 { "L2_DELAY_SEND_INVALIDATION_REQUEST", 14, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_STATUS[] = {
+	 { "BUSY", 0, 0, &umr_bitfield_default },
+	 { "PARITY_ERROR_INFO", 1, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmATC_L2_STATUS2[] = {
+	 { "CACHE_ADDRESS_MODE", 0, 2, &umr_bitfield_default },
+	 { "PARITY_ERROR_INFO", 3, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_INDEX[] = {
+	 { "RENG_RAM_INDEX", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_RAM_DATA[] = {
+	 { "RENG_RAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_RENG_EXECUTE[] = {
+	 { "RENG_EXECUTE_ON_PWR_UP", 0, 0, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW", 1, 1, &umr_bitfield_default },
+	 { "RENG_EXECUTE_NOW_START_PTR", 2, 11, &umr_bitfield_default },
+	 { "RENG_EXECUTE_DSP_END_PTR", 12, 21, &umr_bitfield_default },
+	 { "RENG_EXECUTE_END_PTR", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC[] = {
+	 { "RENG_EXECUTE_NOW_MODE", 10, 10, &umr_bitfield_default },
+	 { "RENG_EXECUTE_ON_REG_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "RENG_SRBM_CREDITS_MCD", 12, 15, &umr_bitfield_default },
+	 { "STCTRL_STUTTER_EN", 16, 16, &umr_bitfield_default },
+	 { "STCTRL_GMC_IDLE_THRESHOLD", 17, 18, &umr_bitfield_default },
+	 { "STCTRL_SRBM_IDLE_THRESHOLD", 19, 20, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PRE_SR", 21, 21, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STOP", 22, 22, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_SR_COMMIT", 23, 23, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_PROTECTION_FAULT", 24, 24, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_ALLOW_SR", 25, 25, &umr_bitfield_default },
+	 { "STCTRL_DISABLE_GMC_OFFLINE", 26, 26, &umr_bitfield_default },
+	 { "CRITICAL_REGS_LOCK", 27, 27, &umr_bitfield_default },
+	 { "ALLOW_DEEP_SLEEP_MODE", 28, 30, &umr_bitfield_default },
+	 { "STCTRL_FORCE_ALLOW_SR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC2[] = {
+	 { "GMCON_MISC2_RESERVED0", 0, 5, &umr_bitfield_default },
+	 { "STCTRL_NONDISP_IDLE_THRESHOLD", 6, 10, &umr_bitfield_default },
+	 { "RENG_SR_HOLD_THRESHOLD", 11, 16, &umr_bitfield_default },
+	 { "GMCON_MISC2_RESERVED1", 17, 28, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ARB_BUSY", 29, 29, &umr_bitfield_default },
+	 { "STCTRL_EXTEND_GMC_OFFLINE", 30, 30, &umr_bitfield_default },
+	 { "STCTRL_TIMER_PULSE_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE1", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[] = {
+	 { "STCTRL_REGISTER_SAVE_BASE2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_LIMIT2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL0", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[] = {
+	 { "STCTRL_REGISTER_SAVE_EXCL2", 0, 15, &umr_bitfield_default },
+	 { "STCTRL_REGISTER_SAVE_EXCL3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL0[] = {
+	 { "START_THRESH", 0, 11, &umr_bitfield_default },
+	 { "STOP_THRESH", 12, 23, &umr_bitfield_default },
+	 { "START_MODE", 24, 25, &umr_bitfield_default },
+	 { "STOP_MODE", 26, 27, &umr_bitfield_default },
+	 { "ALLOW_WRAP", 28, 28, &umr_bitfield_default },
+	 { "THRESH_CNTR_ID_EXT", 29, 29, &umr_bitfield_default },
+	 { "START_TRIG_ID_EXT", 30, 30, &umr_bitfield_default },
+	 { "STOP_TRIG_ID_EXT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_CNTL1[] = {
+	 { "THRESH_CNTR_ID", 0, 5, &umr_bitfield_default },
+	 { "START_TRIG_ID", 6, 11, &umr_bitfield_default },
+	 { "STOP_TRIG_ID", 12, 17, &umr_bitfield_default },
+	 { "MON0_ID", 18, 24, &umr_bitfield_default },
+	 { "MON1_ID", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT0[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PERF_MON_RSLT1[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE", 12, 12, &umr_bitfield_default },
+	 { "READ", 13, 13, &umr_bitfield_default },
+	 { "RSRVD", 14, 26, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_WRITE[] = {
+	 { "WRITE_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_PGFSM_READ[] = {
+	 { "READ_VALUE", 0, 23, &umr_bitfield_default },
+	 { "PGFSM_SELECT", 24, 27, &umr_bitfield_default },
+	 { "SERDES_MASTER_BUSY", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MISC3[] = {
+	 { "RENG_DISABLE_MCC", 0, 7, &umr_bitfield_default },
+	 { "RENG_DISABLE_MCD", 8, 15, &umr_bitfield_default },
+	 { "STCTRL_FORCE_PGFSM_CMD_DONE", 16, 27, &umr_bitfield_default },
+	 { "STCTRL_IGNORE_ALLOW_STUTTER", 28, 28, &umr_bitfield_default },
+	 { "RENG_MEM_LS_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "STCTRL_EXCLUDE_NONMEM_CLIENTS", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_MASK[] = {
+	 { "STCTRL_BUSY_MASK_ACP_RD", 0, 0, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_ACP_WR", 1, 1, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_VCE_RD", 2, 2, &umr_bitfield_default },
+	 { "STCTRL_BUSY_MASK_VCE_WR", 3, 3, &umr_bitfield_default },
+	 { "STCTRL_SR_HANDSHAKE_MASK", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_LPT_TARGET[] = {
+	 { "STCTRL_LPT_TARGET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGMCON_DEBUG[] = {
+	 { "GFX_STALL", 0, 0, &umr_bitfield_default },
+	 { "GFX_CLEAR", 1, 1, &umr_bitfield_default },
+	 { "GMCON_DEBUG_RESERVED0", 2, 2, &umr_bitfield_default },
+	 { "SR_COMMIT_STATE", 3, 3, &umr_bitfield_default },
+	 { "STCTRL_ST", 4, 7, &umr_bitfield_default },
+	 { "MISC_FLAGS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_EN_RD[] = {
+	 { "TX_PRI", 0, 7, &umr_bitfield_default },
+	 { "BW_PRI", 8, 15, &umr_bitfield_default },
+	 { "FIX_PRI", 16, 23, &umr_bitfield_default },
+	 { "ST_PRI", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_EN_WR[] = {
+	 { "TX_PRI", 0, 7, &umr_bitfield_default },
+	 { "BW_PRI", 8, 15, &umr_bitfield_default },
+	 { "FIX_PRI", 16, 23, &umr_bitfield_default },
+	 { "ST_PRI", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_HI1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_TX_LO1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWPERIOD1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_BWCNT1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT0_RD[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT0_WR[] = {
+	 { "GROUP0", 0, 7, &umr_bitfield_default },
+	 { "GROUP1", 8, 15, &umr_bitfield_default },
+	 { "GROUP2", 16, 23, &umr_bitfield_default },
+	 { "GROUP3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT1_RD[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_SAT1_WR[] = {
+	 { "GROUP4", 0, 7, &umr_bitfield_default },
+	 { "GROUP5", 8, 15, &umr_bitfield_default },
+	 { "GROUP6", 16, 23, &umr_bitfield_default },
+	 { "GROUP7", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_CTL_RD[] = {
+	 { "FORCE_HIGHEST", 0, 7, &umr_bitfield_default },
+	 { "HARSH_RR", 8, 8, &umr_bitfield_default },
+	 { "BANK_AGE_ONLY", 9, 9, &umr_bitfield_default },
+	 { "USE_LEGACY_HARSH", 10, 10, &umr_bitfield_default },
+	 { "BWCNT_CATCHUP", 11, 11, &umr_bitfield_default },
+	 { "ST_MODE", 12, 13, &umr_bitfield_default },
+	 { "FORCE_STALL", 14, 21, &umr_bitfield_default },
+	 { "PERF_MON_SEL", 22, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_HARSH_CTL_WR[] = {
+	 { "FORCE_HIGHEST", 0, 7, &umr_bitfield_default },
+	 { "HARSH_RR", 8, 8, &umr_bitfield_default },
+	 { "BANK_AGE_ONLY", 9, 9, &umr_bitfield_default },
+	 { "USE_LEGACY_HARSH", 10, 10, &umr_bitfield_default },
+	 { "BWCNT_CATCHUP", 11, 11, &umr_bitfield_default },
+	 { "ST_MODE", 12, 13, &umr_bitfield_default },
+	 { "FORCE_STALL", 14, 21, &umr_bitfield_default },
+	 { "PERF_MON_SEL", 22, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PRIORITY1_RD[] = {
+	 { "CB0", 0, 1, &umr_bitfield_default },
+	 { "CBCMASK0", 2, 3, &umr_bitfield_default },
+	 { "CBFMASK0", 4, 5, &umr_bitfield_default },
+	 { "DB0", 6, 7, &umr_bitfield_default },
+	 { "DBHTILE0", 8, 9, &umr_bitfield_default },
+	 { "DBSTEN0", 10, 11, &umr_bitfield_default },
+	 { "TC0", 12, 13, &umr_bitfield_default },
+	 { "ACPG", 14, 15, &umr_bitfield_default },
+	 { "ACPO", 16, 17, &umr_bitfield_default },
+	 { "DMIF", 18, 19, &umr_bitfield_default },
+	 { "DMIF_EXT0", 20, 21, &umr_bitfield_default },
+	 { "DMIF_EXT1", 22, 23, &umr_bitfield_default },
+	 { "DMIF_TW", 24, 25, &umr_bitfield_default },
+	 { "MCIF", 26, 27, &umr_bitfield_default },
+	 { "RLC", 28, 29, &umr_bitfield_default },
+	 { "VMC", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PRIORITY1_WR[] = {
+	 { "CB0", 0, 1, &umr_bitfield_default },
+	 { "CBCMASK0", 2, 3, &umr_bitfield_default },
+	 { "CBFMASK0", 4, 5, &umr_bitfield_default },
+	 { "CBIMMED0", 6, 7, &umr_bitfield_default },
+	 { "DB0", 8, 9, &umr_bitfield_default },
+	 { "DBHTILE0", 10, 11, &umr_bitfield_default },
+	 { "DBSTEN0", 12, 13, &umr_bitfield_default },
+	 { "TC0", 14, 15, &umr_bitfield_default },
+	 { "SH", 16, 17, &umr_bitfield_default },
+	 { "ACPG", 18, 19, &umr_bitfield_default },
+	 { "ACPO", 20, 21, &umr_bitfield_default },
+	 { "MCIF", 22, 23, &umr_bitfield_default },
+	 { "RLC", 24, 25, &umr_bitfield_default },
+	 { "SDMA1", 26, 27, &umr_bitfield_default },
+	 { "SMU", 28, 29, &umr_bitfield_default },
+	 { "VCE0", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PRIORITY2_RD[] = {
+	 { "SDMA1", 0, 1, &umr_bitfield_default },
+	 { "SMU", 2, 3, &umr_bitfield_default },
+	 { "VCE0", 4, 5, &umr_bitfield_default },
+	 { "VCE1", 6, 7, &umr_bitfield_default },
+	 { "XDMAM", 8, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 11, &umr_bitfield_default },
+	 { "HDP", 12, 13, &umr_bitfield_default },
+	 { "UMC", 14, 15, &umr_bitfield_default },
+	 { "UVD", 16, 17, &umr_bitfield_default },
+	 { "UVD_EXT0", 18, 19, &umr_bitfield_default },
+	 { "UVD_EXT1", 20, 21, &umr_bitfield_default },
+	 { "SEM", 22, 23, &umr_bitfield_default },
+	 { "SAMMSP", 24, 25, &umr_bitfield_default },
+	 { "VP8", 26, 27, &umr_bitfield_default },
+	 { "ISP", 28, 29, &umr_bitfield_default },
+	 { "RSV2", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_ARB_GRUB_PRIORITY2_WR[] = {
+	 { "VCE1", 0, 1, &umr_bitfield_default },
+	 { "SAMMSP", 2, 3, &umr_bitfield_default },
+	 { "XDMA", 4, 5, &umr_bitfield_default },
+	 { "XDMAM", 6, 7, &umr_bitfield_default },
+	 { "SDMA0", 8, 9, &umr_bitfield_default },
+	 { "HDP", 10, 11, &umr_bitfield_default },
+	 { "UMC", 12, 13, &umr_bitfield_default },
+	 { "UVD", 14, 15, &umr_bitfield_default },
+	 { "UVD_EXT0", 16, 17, &umr_bitfield_default },
+	 { "UVD_EXT1", 18, 19, &umr_bitfield_default },
+	 { "XDP", 20, 21, &umr_bitfield_default },
+	 { "SEM", 22, 23, &umr_bitfield_default },
+	 { "IH", 24, 25, &umr_bitfield_default },
+	 { "VP8", 26, 27, &umr_bitfield_default },
+	 { "ISP", 28, 29, &umr_bitfield_default },
+	 { "VIN0", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_SPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_MPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_ISP_CCPU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_SPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_MPS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_MPM[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_ISP_CCPU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+	 { "PRIORITY_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "STALL_FILTER_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 19, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_MCDV[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "BUS", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "LAZY_TIMER", 7, 10, &umr_bitfield_default },
+	 { "ASK_CREDITS", 11, 17, &umr_bitfield_default },
+	 { "DISPLAY_CREDITS", 18, 24, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDS[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDT[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDU[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_MCDV[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 1, 1, &umr_bitfield_default },
+	 { "STALL_MODE", 2, 2, &umr_bitfield_default },
+	 { "MAXBURST", 3, 6, &umr_bitfield_default },
+	 { "ASK_CREDITS", 7, 12, &umr_bitfield_default },
+	 { "LAZY_TIMER", 13, 16, &umr_bitfield_default },
+	 { "STALL_THRESHOLD", 17, 23, &umr_bitfield_default },
+	 { "ASK_CREDITS_W", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDS[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDT[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDU[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WRRET_MCDV[] = {
+	 { "STALL_MODE", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_COUNT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDW[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDX[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDY[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDZ[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDS[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDT[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDU[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_CREDITS_MCDV[] = {
+	 { "WR_PRI", 0, 6, &umr_bitfield_default },
+	 { "WR_PRI_STALL_THRESHOLD", 7, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_BP2[] = {
+	 { "RDRET", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCE1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_RDREQ_VCEU1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCE1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "VM_BYPASS", 16, 16, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_HUB_WDP_VCEU1[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "PRESCALE", 1, 2, &umr_bitfield_default },
+	 { "BLACKOUT_EXEMPT", 3, 3, &umr_bitfield_default },
+	 { "STALL_MODE", 4, 5, &umr_bitfield_default },
+	 { "STALL_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "MAXBURST", 7, 10, &umr_bitfield_default },
+	 { "LAZY_TIMER", 11, 14, &umr_bitfield_default },
+	 { "STALL_OVERRIDE_WTM", 15, 15, &umr_bitfield_default },
+	 { "BYPASS_AVAIL_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF0[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF1[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF2[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF3[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF4[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF5[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF6[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF7[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF8[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF9[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF10[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF11[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF12[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF13[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF14[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_FB_SIZE_OFFSET_VF15[] = {
+	 { "VF_FB_SIZE", 0, 15, &umr_bitfield_default },
+	 { "VF_FB_OFFSET", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_MMIOBASE[] = {
+	 { "MMIOBASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_MMIOLIMIT[] = {
+	 { "MMIOLIMIT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_PCI_CTRL[] = {
+	 { "MMIOENABLE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_PCI_ARB[] = {
+	 { "VGA_HOLE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_TOP_OF_DRAM_SLOT1[] = {
+	 { "TOP_OF_DRAM", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_LOWER_TOP_OF_DRAM2[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LOWER_TOM2", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_UPPER_TOP_OF_DRAM2[] = {
+	 { "UPPER_TOM2", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_NB_TOP_OF_DRAM3[] = {
+	 { "TOM3_LIMIT", 0, 29, &umr_bitfield_default },
+	 { "TOM3_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_LO_0[] = {
+	 { "MARC_BASE_LO_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_HI_0[] = {
+	 { "MARC_BASE_HI_0", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_0[] = {
+	 { "MARC_ENABLE_0", 0, 0, &umr_bitfield_default },
+	 { "MARC_READONLY_0", 1, 1, &umr_bitfield_default },
+	 { "MARC_RELOC_LO_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_0[] = {
+	 { "MARC_RELOC_HI_0", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_LO_0[] = {
+	 { "MARC_LEN_LO_0", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_HI_0[] = {
+	 { "MARC_LEN_HI_0", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_LO_1[] = {
+	 { "MARC_BASE_LO_1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_HI_1[] = {
+	 { "MARC_BASE_HI_1", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_1[] = {
+	 { "MARC_ENABLE_1", 0, 0, &umr_bitfield_default },
+	 { "MARC_READONLY_1", 1, 1, &umr_bitfield_default },
+	 { "MARC_RELOC_LO_1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_1[] = {
+	 { "MARC_RELOC_HI_1", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_LO_1[] = {
+	 { "MARC_LEN_LO_1", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_HI_1[] = {
+	 { "MARC_LEN_HI_1", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_LO_2[] = {
+	 { "MARC_BASE_LO_2", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_HI_2[] = {
+	 { "MARC_BASE_HI_2", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_2[] = {
+	 { "MARC_ENABLE_2", 0, 0, &umr_bitfield_default },
+	 { "MARC_READONLY_2", 1, 1, &umr_bitfield_default },
+	 { "MARC_RELOC_LO_2", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_2[] = {
+	 { "MARC_RELOC_HI_2", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_LO_2[] = {
+	 { "MARC_LEN_LO_2", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_HI_2[] = {
+	 { "MARC_LEN_HI_2", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_LO_3[] = {
+	 { "MARC_BASE_LO_3", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_BASE_HI_3[] = {
+	 { "MARC_BASE_HI_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_LO_3[] = {
+	 { "MARC_ENABLE_3", 0, 0, &umr_bitfield_default },
+	 { "MARC_READONLY_3", 1, 1, &umr_bitfield_default },
+	 { "MARC_RELOC_LO_3", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_RELOC_HI_3[] = {
+	 { "MARC_RELOC_HI_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_LO_3[] = {
+	 { "MARC_LEN_LO_3", 12, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_LEN_HI_3[] = {
+	 { "MARC_LEN_HI_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMC_VM_MARC_CNTL[] = {
+	 { "ENABLE_ALL_CLIENTS", 0, 0, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/gmc82_regs.i b/src/lib/ip/gmc82_regs.i
new file mode 100644
index 0000000..2f8b259
--- /dev/null
+++ b/src/lib/ip/gmc82_regs.i
@@ -0,0 +1,882 @@
+	{ "mmVM_L2_CNTL", REG_MMIO, 0x500, &mmVM_L2_CNTL[0], sizeof(mmVM_L2_CNTL)/sizeof(mmVM_L2_CNTL[0]), 0, 0 },
+	{ "mmVM_L2_CNTL2", REG_MMIO, 0x501, &mmVM_L2_CNTL2[0], sizeof(mmVM_L2_CNTL2)/sizeof(mmVM_L2_CNTL2[0]), 0, 0 },
+	{ "mmVM_L2_CNTL3", REG_MMIO, 0x502, &mmVM_L2_CNTL3[0], sizeof(mmVM_L2_CNTL3)/sizeof(mmVM_L2_CNTL3[0]), 0, 0 },
+	{ "mmVM_L2_STATUS", REG_MMIO, 0x503, &mmVM_L2_STATUS[0], sizeof(mmVM_L2_STATUS)/sizeof(mmVM_L2_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL", REG_MMIO, 0x504, &mmVM_CONTEXT0_CNTL[0], sizeof(mmVM_CONTEXT0_CNTL)/sizeof(mmVM_CONTEXT0_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL", REG_MMIO, 0x505, &mmVM_CONTEXT1_CNTL[0], sizeof(mmVM_CONTEXT1_CNTL)/sizeof(mmVM_CONTEXT1_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_CNTL", REG_MMIO, 0x506, &mmVM_DUMMY_PAGE_FAULT_CNTL[0], sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL)/sizeof(mmVM_DUMMY_PAGE_FAULT_CNTL[0]), 0, 0 },
+	{ "mmVM_DUMMY_PAGE_FAULT_ADDR", REG_MMIO, 0x507, &mmVM_DUMMY_PAGE_FAULT_ADDR[0], sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR)/sizeof(mmVM_DUMMY_PAGE_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_CNTL2", REG_MMIO, 0x50c, &mmVM_CONTEXT0_CNTL2[0], sizeof(mmVM_CONTEXT0_CNTL2)/sizeof(mmVM_CONTEXT0_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_CNTL2", REG_MMIO, 0x50d, &mmVM_CONTEXT1_CNTL2[0], sizeof(mmVM_CONTEXT1_CNTL2)/sizeof(mmVM_CONTEXT1_CNTL2[0]), 0, 0 },
+	{ "mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50e, &mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x50f, &mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x510, &mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x511, &mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x512, &mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x513, &mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x514, &mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x515, &mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_REQUEST", REG_MMIO, 0x51e, &mmVM_INVALIDATE_REQUEST[0], sizeof(mmVM_INVALIDATE_REQUEST)/sizeof(mmVM_INVALIDATE_REQUEST[0]), 0, 0 },
+	{ "mmVM_INVALIDATE_RESPONSE", REG_MMIO, 0x51f, &mmVM_INVALIDATE_RESPONSE[0], sizeof(mmVM_INVALIDATE_RESPONSE)/sizeof(mmVM_INVALIDATE_RESPONSE[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_LOW_ADDR", REG_MMIO, 0x52c, &mmVM_PRT_APERTURE0_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE0_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_LOW_ADDR", REG_MMIO, 0x52d, &mmVM_PRT_APERTURE1_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE1_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_LOW_ADDR", REG_MMIO, 0x52e, &mmVM_PRT_APERTURE2_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE2_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE2_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_LOW_ADDR", REG_MMIO, 0x52f, &mmVM_PRT_APERTURE3_LOW_ADDR[0], sizeof(mmVM_PRT_APERTURE3_LOW_ADDR)/sizeof(mmVM_PRT_APERTURE3_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE0_HIGH_ADDR", REG_MMIO, 0x530, &mmVM_PRT_APERTURE0_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE1_HIGH_ADDR", REG_MMIO, 0x531, &mmVM_PRT_APERTURE1_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE2_HIGH_ADDR", REG_MMIO, 0x532, &mmVM_PRT_APERTURE2_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_APERTURE3_HIGH_ADDR", REG_MMIO, 0x533, &mmVM_PRT_APERTURE3_HIGH_ADDR[0], sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR)/sizeof(mmVM_PRT_APERTURE3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_PRT_CNTL", REG_MMIO, 0x534, &mmVM_PRT_CNTL[0], sizeof(mmVM_PRT_CNTL)/sizeof(mmVM_PRT_CNTL[0]), 0, 0 },
+	{ "mmVM_CONTEXTS_DISABLE", REG_MMIO, 0x535, &mmVM_CONTEXTS_DISABLE[0], sizeof(mmVM_CONTEXTS_DISABLE)/sizeof(mmVM_CONTEXTS_DISABLE[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_STATUS", REG_MMIO, 0x536, &mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_STATUS", REG_MMIO, 0x537, &mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x538, &mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT", REG_MMIO, 0x539, &mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53e, &mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_ADDR", REG_MMIO, 0x53f, &mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x546, &mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR", REG_MMIO, 0x547, &mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0], sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR)/sizeof(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmVM_FAULT_CLIENT_ID", REG_MMIO, 0x54e, &mmVM_FAULT_CLIENT_ID[0], sizeof(mmVM_FAULT_CLIENT_ID)/sizeof(mmVM_FAULT_CLIENT_ID[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x54f, &mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x550, &mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x551, &mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x552, &mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x553, &mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x554, &mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x555, &mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR", REG_MMIO, 0x556, &mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0], sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR)/sizeof(mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_START_ADDR", REG_MMIO, 0x557, &mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_START_ADDR", REG_MMIO, 0x558, &mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT0_PAGE_TABLE_END_ADDR", REG_MMIO, 0x55f, &mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "mmVM_CONTEXT1_PAGE_TABLE_END_ADDR", REG_MMIO, 0x560, &mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0], sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR)/sizeof(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR[0]), 0, 0 },
+	{ "mmVM_DEBUG", REG_MMIO, 0x56f, &mmVM_DEBUG[0], sizeof(mmVM_DEBUG)/sizeof(mmVM_DEBUG[0]), 0, 0 },
+	{ "mmVM_L2_CG", REG_MMIO, 0x570, &mmVM_L2_CG[0], sizeof(mmVM_L2_CG)/sizeof(mmVM_L2_CG[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKA", REG_MMIO, 0x572, &mmVM_L2_BANK_SELECT_MASKA[0], sizeof(mmVM_L2_BANK_SELECT_MASKA)/sizeof(mmVM_L2_BANK_SELECT_MASKA[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_MASKB", REG_MMIO, 0x573, &mmVM_L2_BANK_SELECT_MASKB[0], sizeof(mmVM_L2_BANK_SELECT_MASKB)/sizeof(mmVM_L2_BANK_SELECT_MASKB[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR", REG_MMIO, 0x575, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR", REG_MMIO, 0x576, &mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0], sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR)/sizeof(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET", REG_MMIO, 0x577, &mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0], sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET)/sizeof(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET[0]), 0, 0 },
+	{ "mmVM_L2_CNTL4", REG_MMIO, 0x578, &mmVM_L2_CNTL4[0], sizeof(mmVM_L2_CNTL4)/sizeof(mmVM_L2_CNTL4[0]), 0, 0 },
+	{ "mmVM_L2_BANK_SELECT_RESERVED_CID", REG_MMIO, 0x579, &mmVM_L2_BANK_SELECT_RESERVED_CID[0], sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID)/sizeof(mmVM_L2_BANK_SELECT_RESERVED_CID[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x5e78, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x5e78, &mmMCIF_WB_BUFMGR_SW_CONTROL[0], sizeof(mmMCIF_WB_BUFMGR_SW_CONTROL)/sizeof(mmMCIF_WB_BUFMGR_SW_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x5e79, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x5e79, &mmMCIF_WB_BUFMGR_CUR_LINE_R[0], sizeof(mmMCIF_WB_BUFMGR_CUR_LINE_R)/sizeof(mmMCIF_WB_BUFMGR_CUR_LINE_R[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x5e7a, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x5e7a, &mmMCIF_WB_BUFMGR_STATUS[0], sizeof(mmMCIF_WB_BUFMGR_STATUS)/sizeof(mmMCIF_WB_BUFMGR_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_PITCH", REG_MMIO, 0x5e7b, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_PITCH", REG_MMIO, 0x5e7b, &mmMCIF_WB_BUF_PITCH[0], sizeof(mmMCIF_WB_BUF_PITCH)/sizeof(mmMCIF_WB_BUF_PITCH[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_STATUS", REG_MMIO, 0x5e7c, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_STATUS", REG_MMIO, 0x5e7c, &mmMCIF_WB_BUF_1_STATUS[0], sizeof(mmMCIF_WB_BUF_1_STATUS)/sizeof(mmMCIF_WB_BUF_1_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x5e7d, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x5e7d, &mmMCIF_WB_BUF_1_STATUS2[0], sizeof(mmMCIF_WB_BUF_1_STATUS2)/sizeof(mmMCIF_WB_BUF_1_STATUS2[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_STATUS", REG_MMIO, 0x5e7e, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_STATUS", REG_MMIO, 0x5e7e, &mmMCIF_WB_BUF_2_STATUS[0], sizeof(mmMCIF_WB_BUF_2_STATUS)/sizeof(mmMCIF_WB_BUF_2_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x5e7f, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x5e7f, &mmMCIF_WB_BUF_2_STATUS2[0], sizeof(mmMCIF_WB_BUF_2_STATUS2)/sizeof(mmMCIF_WB_BUF_2_STATUS2[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_STATUS", REG_MMIO, 0x5e80, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_STATUS", REG_MMIO, 0x5e80, &mmMCIF_WB_BUF_3_STATUS[0], sizeof(mmMCIF_WB_BUF_3_STATUS)/sizeof(mmMCIF_WB_BUF_3_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x5e81, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x5e81, &mmMCIF_WB_BUF_3_STATUS2[0], sizeof(mmMCIF_WB_BUF_3_STATUS2)/sizeof(mmMCIF_WB_BUF_3_STATUS2[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_STATUS", REG_MMIO, 0x5e82, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_STATUS", REG_MMIO, 0x5e82, &mmMCIF_WB_BUF_4_STATUS[0], sizeof(mmMCIF_WB_BUF_4_STATUS)/sizeof(mmMCIF_WB_BUF_4_STATUS[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x5e83, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x5e83, &mmMCIF_WB_BUF_4_STATUS2[0], sizeof(mmMCIF_WB_BUF_4_STATUS2)/sizeof(mmMCIF_WB_BUF_4_STATUS2[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x5e84, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x5e84, &mmMCIF_WB_ARBITRATION_CONTROL[0], sizeof(mmMCIF_WB_ARBITRATION_CONTROL)/sizeof(mmMCIF_WB_ARBITRATION_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_URGENCY_WATERMARK", REG_MMIO, 0x5e85, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_URGENCY_WATERMARK", REG_MMIO, 0x5e85, &mmMCIF_WB_URGENCY_WATERMARK[0], sizeof(mmMCIF_WB_URGENCY_WATERMARK)/sizeof(mmMCIF_WB_URGENCY_WATERMARK[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX", REG_MMIO, 0x5e86, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_TEST_DEBUG_INDEX", REG_MMIO, 0x5e86, &mmMCIF_WB_TEST_DEBUG_INDEX[0], sizeof(mmMCIF_WB_TEST_DEBUG_INDEX)/sizeof(mmMCIF_WB_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA", REG_MMIO, 0x5e87, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_TEST_DEBUG_DATA", REG_MMIO, 0x5e87, &mmMCIF_WB_TEST_DEBUG_DATA[0], sizeof(mmMCIF_WB_TEST_DEBUG_DATA)/sizeof(mmMCIF_WB_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x5e88, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x5e88, &mmMCIF_WB_BUF_1_ADDR_Y[0], sizeof(mmMCIF_WB_BUF_1_ADDR_Y)/sizeof(mmMCIF_WB_BUF_1_ADDR_Y[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x5e89, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x5e89, &mmMCIF_WB_BUF_1_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB_BUF_1_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB_BUF_1_ADDR_Y_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x5e8a, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x5e8a, &mmMCIF_WB_BUF_1_ADDR_C[0], sizeof(mmMCIF_WB_BUF_1_ADDR_C)/sizeof(mmMCIF_WB_BUF_1_ADDR_C[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x5e8b, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x5e8b, &mmMCIF_WB_BUF_1_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB_BUF_1_ADDR_C_OFFSET)/sizeof(mmMCIF_WB_BUF_1_ADDR_C_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x5e8c, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x5e8c, &mmMCIF_WB_BUF_2_ADDR_Y[0], sizeof(mmMCIF_WB_BUF_2_ADDR_Y)/sizeof(mmMCIF_WB_BUF_2_ADDR_Y[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x5e8d, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x5e8d, &mmMCIF_WB_BUF_2_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB_BUF_2_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB_BUF_2_ADDR_Y_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x5e8e, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x5e8e, &mmMCIF_WB_BUF_2_ADDR_C[0], sizeof(mmMCIF_WB_BUF_2_ADDR_C)/sizeof(mmMCIF_WB_BUF_2_ADDR_C[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x5e8f, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x5e8f, &mmMCIF_WB_BUF_2_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB_BUF_2_ADDR_C_OFFSET)/sizeof(mmMCIF_WB_BUF_2_ADDR_C_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x5e90, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x5e90, &mmMCIF_WB_BUF_3_ADDR_Y[0], sizeof(mmMCIF_WB_BUF_3_ADDR_Y)/sizeof(mmMCIF_WB_BUF_3_ADDR_Y[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x5e91, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x5e91, &mmMCIF_WB_BUF_3_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB_BUF_3_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB_BUF_3_ADDR_Y_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x5e92, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x5e92, &mmMCIF_WB_BUF_3_ADDR_C[0], sizeof(mmMCIF_WB_BUF_3_ADDR_C)/sizeof(mmMCIF_WB_BUF_3_ADDR_C[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x5e93, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x5e93, &mmMCIF_WB_BUF_3_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB_BUF_3_ADDR_C_OFFSET)/sizeof(mmMCIF_WB_BUF_3_ADDR_C_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x5e94, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x5e94, &mmMCIF_WB_BUF_4_ADDR_Y[0], sizeof(mmMCIF_WB_BUF_4_ADDR_Y)/sizeof(mmMCIF_WB_BUF_4_ADDR_Y[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x5e95, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x5e95, &mmMCIF_WB_BUF_4_ADDR_Y_OFFSET[0], sizeof(mmMCIF_WB_BUF_4_ADDR_Y_OFFSET)/sizeof(mmMCIF_WB_BUF_4_ADDR_Y_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x5e96, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x5e96, &mmMCIF_WB_BUF_4_ADDR_C[0], sizeof(mmMCIF_WB_BUF_4_ADDR_C)/sizeof(mmMCIF_WB_BUF_4_ADDR_C[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x5e97, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x5e97, &mmMCIF_WB_BUF_4_ADDR_C_OFFSET[0], sizeof(mmMCIF_WB_BUF_4_ADDR_C_OFFSET)/sizeof(mmMCIF_WB_BUF_4_ADDR_C_OFFSET[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x5e98, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x5e98, &mmMCIF_WB_BUFMGR_VCE_CONTROL[0], sizeof(mmMCIF_WB_BUFMGR_VCE_CONTROL)/sizeof(mmMCIF_WB_BUFMGR_VCE_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WB0_MCIF_WB_HVVMID_CONTROL", REG_MMIO, 0x5e99, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB_HVVMID_CONTROL", REG_MMIO, 0x5e99, &mmMCIF_WB_HVVMID_CONTROL[0], sizeof(mmMCIF_WB_HVVMID_CONTROL)/sizeof(mmMCIF_WB_HVVMID_CONTROL[0]), 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x5eb8, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x5eb9, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x5eba, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_PITCH", REG_MMIO, 0x5ebb, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_STATUS", REG_MMIO, 0x5ebc, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x5ebd, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_STATUS", REG_MMIO, 0x5ebe, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x5ebf, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_STATUS", REG_MMIO, 0x5ec0, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x5ec1, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_STATUS", REG_MMIO, 0x5ec2, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x5ec3, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x5ec4, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_URGENCY_WATERMARK", REG_MMIO, 0x5ec5, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX", REG_MMIO, 0x5ec6, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA", REG_MMIO, 0x5ec7, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x5ec8, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x5ec9, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x5eca, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x5ecb, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x5ecc, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x5ecd, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x5ece, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x5ecf, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x5ed0, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x5ed1, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x5ed2, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x5ed3, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x5ed4, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x5ed5, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x5ed6, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x5ed7, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x5ed8, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB1_MCIF_WB_HVVMID_CONTROL", REG_MMIO, 0x5ed9, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL", REG_MMIO, 0x5ef8, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R", REG_MMIO, 0x5ef9, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS", REG_MMIO, 0x5efa, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_PITCH", REG_MMIO, 0x5efb, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_STATUS", REG_MMIO, 0x5efc, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2", REG_MMIO, 0x5efd, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_STATUS", REG_MMIO, 0x5efe, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2", REG_MMIO, 0x5eff, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_STATUS", REG_MMIO, 0x5f00, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2", REG_MMIO, 0x5f01, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_STATUS", REG_MMIO, 0x5f02, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2", REG_MMIO, 0x5f03, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL", REG_MMIO, 0x5f04, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_URGENCY_WATERMARK", REG_MMIO, 0x5f05, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX", REG_MMIO, 0x5f06, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA", REG_MMIO, 0x5f07, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y", REG_MMIO, 0x5f08, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET", REG_MMIO, 0x5f09, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C", REG_MMIO, 0x5f0a, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET", REG_MMIO, 0x5f0b, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y", REG_MMIO, 0x5f0c, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET", REG_MMIO, 0x5f0d, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C", REG_MMIO, 0x5f0e, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET", REG_MMIO, 0x5f0f, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y", REG_MMIO, 0x5f10, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET", REG_MMIO, 0x5f11, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C", REG_MMIO, 0x5f12, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET", REG_MMIO, 0x5f13, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y", REG_MMIO, 0x5f14, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET", REG_MMIO, 0x5f15, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C", REG_MMIO, 0x5f16, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET", REG_MMIO, 0x5f17, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL", REG_MMIO, 0x5f18, NULL, 0, 0, 0 },
+	{ "mmMCIF_WB2_MCIF_WB_HVVMID_CONTROL", REG_MMIO, 0x5f19, NULL, 0, 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_LO", REG_MMIO, 0x7a0, &mmMC_CITF_PERFCOUNTER_LO[0], sizeof(mmMC_CITF_PERFCOUNTER_LO)/sizeof(mmMC_CITF_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_LO", REG_MMIO, 0x7a1, &mmMC_HUB_PERFCOUNTER_LO[0], sizeof(mmMC_HUB_PERFCOUNTER_LO)/sizeof(mmMC_HUB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_LO", REG_MMIO, 0x7a2, &mmMC_RPB_PERFCOUNTER_LO[0], sizeof(mmMC_RPB_PERFCOUNTER_LO)/sizeof(mmMC_RPB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_LO", REG_MMIO, 0x7a3, &mmMC_MCBVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCBVM_PERFCOUNTER_LO)/sizeof(mmMC_MCBVM_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_LO", REG_MMIO, 0x7a4, &mmMC_MCDVM_PERFCOUNTER_LO[0], sizeof(mmMC_MCDVM_PERFCOUNTER_LO)/sizeof(mmMC_MCDVM_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_LO", REG_MMIO, 0x7a5, &mmMC_VM_L2_PERFCOUNTER_LO[0], sizeof(mmMC_VM_L2_PERFCOUNTER_LO)/sizeof(mmMC_VM_L2_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_LO", REG_MMIO, 0x7a6, &mmMC_ARB_PERFCOUNTER_LO[0], sizeof(mmMC_ARB_PERFCOUNTER_LO)/sizeof(mmMC_ARB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_LO", REG_MMIO, 0x7a7, &mmATC_PERFCOUNTER_LO[0], sizeof(mmATC_PERFCOUNTER_LO)/sizeof(mmATC_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_HI", REG_MMIO, 0x7a8, &mmMC_CITF_PERFCOUNTER_HI[0], sizeof(mmMC_CITF_PERFCOUNTER_HI)/sizeof(mmMC_CITF_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_HI", REG_MMIO, 0x7a9, &mmMC_HUB_PERFCOUNTER_HI[0], sizeof(mmMC_HUB_PERFCOUNTER_HI)/sizeof(mmMC_HUB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_HI", REG_MMIO, 0x7aa, &mmMC_MCBVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCBVM_PERFCOUNTER_HI)/sizeof(mmMC_MCBVM_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_HI", REG_MMIO, 0x7ab, &mmMC_MCDVM_PERFCOUNTER_HI[0], sizeof(mmMC_MCDVM_PERFCOUNTER_HI)/sizeof(mmMC_MCDVM_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_HI", REG_MMIO, 0x7ac, &mmMC_RPB_PERFCOUNTER_HI[0], sizeof(mmMC_RPB_PERFCOUNTER_HI)/sizeof(mmMC_RPB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_HI", REG_MMIO, 0x7ad, &mmMC_VM_L2_PERFCOUNTER_HI[0], sizeof(mmMC_VM_L2_PERFCOUNTER_HI)/sizeof(mmMC_VM_L2_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_HI", REG_MMIO, 0x7ae, &mmMC_ARB_PERFCOUNTER_HI[0], sizeof(mmMC_ARB_PERFCOUNTER_HI)/sizeof(mmMC_ARB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_HI", REG_MMIO, 0x7af, &mmATC_PERFCOUNTER_HI[0], sizeof(mmATC_PERFCOUNTER_HI)/sizeof(mmATC_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER0_CFG", REG_MMIO, 0x7b0, &mmMC_CITF_PERFCOUNTER0_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER0_CFG)/sizeof(mmMC_CITF_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER1_CFG", REG_MMIO, 0x7b1, &mmMC_CITF_PERFCOUNTER1_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER1_CFG)/sizeof(mmMC_CITF_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER2_CFG", REG_MMIO, 0x7b2, &mmMC_CITF_PERFCOUNTER2_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER2_CFG)/sizeof(mmMC_CITF_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER3_CFG", REG_MMIO, 0x7b3, &mmMC_CITF_PERFCOUNTER3_CFG[0], sizeof(mmMC_CITF_PERFCOUNTER3_CFG)/sizeof(mmMC_CITF_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b4, &mmMC_HUB_PERFCOUNTER0_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER0_CFG)/sizeof(mmMC_HUB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b5, &mmMC_HUB_PERFCOUNTER1_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER1_CFG)/sizeof(mmMC_HUB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER2_CFG", REG_MMIO, 0x7b6, &mmMC_HUB_PERFCOUNTER2_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER2_CFG)/sizeof(mmMC_HUB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER3_CFG", REG_MMIO, 0x7b7, &mmMC_HUB_PERFCOUNTER3_CFG[0], sizeof(mmMC_HUB_PERFCOUNTER3_CFG)/sizeof(mmMC_HUB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER0_CFG", REG_MMIO, 0x7b8, &mmMC_RPB_PERFCOUNTER0_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER0_CFG)/sizeof(mmMC_RPB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER1_CFG", REG_MMIO, 0x7b9, &mmMC_RPB_PERFCOUNTER1_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER1_CFG)/sizeof(mmMC_RPB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER2_CFG", REG_MMIO, 0x7ba, &mmMC_RPB_PERFCOUNTER2_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER2_CFG)/sizeof(mmMC_RPB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bb, &mmMC_RPB_PERFCOUNTER3_CFG[0], sizeof(mmMC_RPB_PERFCOUNTER3_CFG)/sizeof(mmMC_RPB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER0_CFG", REG_MMIO, 0x7bc, &mmMC_ARB_PERFCOUNTER0_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER0_CFG)/sizeof(mmMC_ARB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER1_CFG", REG_MMIO, 0x7bd, &mmMC_ARB_PERFCOUNTER1_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER1_CFG)/sizeof(mmMC_ARB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER2_CFG", REG_MMIO, 0x7be, &mmMC_ARB_PERFCOUNTER2_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER2_CFG)/sizeof(mmMC_ARB_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER3_CFG", REG_MMIO, 0x7bf, &mmMC_ARB_PERFCOUNTER3_CFG[0], sizeof(mmMC_ARB_PERFCOUNTER3_CFG)/sizeof(mmMC_ARB_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c0, &mmMC_MCBVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c1, &mmMC_MCBVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c2, &mmMC_MCBVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c3, &mmMC_MCBVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCBVM_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER0_CFG", REG_MMIO, 0x7c4, &mmMC_MCDVM_PERFCOUNTER0_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER1_CFG", REG_MMIO, 0x7c5, &mmMC_MCDVM_PERFCOUNTER1_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER2_CFG", REG_MMIO, 0x7c6, &mmMC_MCDVM_PERFCOUNTER2_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER3_CFG", REG_MMIO, 0x7c7, &mmMC_MCDVM_PERFCOUNTER3_CFG[0], sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG)/sizeof(mmMC_MCDVM_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7c8, &mmATC_PERFCOUNTER0_CFG[0], sizeof(mmATC_PERFCOUNTER0_CFG)/sizeof(mmATC_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7c9, &mmATC_PERFCOUNTER1_CFG[0], sizeof(mmATC_PERFCOUNTER1_CFG)/sizeof(mmATC_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER2_CFG", REG_MMIO, 0x7ca, &mmATC_PERFCOUNTER2_CFG[0], sizeof(mmATC_PERFCOUNTER2_CFG)/sizeof(mmATC_PERFCOUNTER2_CFG[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER3_CFG", REG_MMIO, 0x7cb, &mmATC_PERFCOUNTER3_CFG[0], sizeof(mmATC_PERFCOUNTER3_CFG)/sizeof(mmATC_PERFCOUNTER3_CFG[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER0_CFG", REG_MMIO, 0x7cc, &mmMC_VM_L2_PERFCOUNTER0_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER1_CFG", REG_MMIO, 0x7cd, &mmMC_VM_L2_PERFCOUNTER1_CFG[0], sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG)/sizeof(mmMC_VM_L2_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_CITF_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7ce, &mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_CITF_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7cf, &mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_HUB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d0, &mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_RPB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d1, &mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d2, &mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d3, &mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d4, &mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_ARB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7d5, &mmATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_LO", REG_MMIO, 0x7d6, &mmCHUB_ATC_PERFCOUNTER_LO[0], sizeof(mmCHUB_ATC_PERFCOUNTER_LO)/sizeof(mmCHUB_ATC_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_HI", REG_MMIO, 0x7d7, &mmCHUB_ATC_PERFCOUNTER_HI[0], sizeof(mmCHUB_ATC_PERFCOUNTER_HI)/sizeof(mmCHUB_ATC_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER0_CFG", REG_MMIO, 0x7d8, &mmCHUB_ATC_PERFCOUNTER0_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER1_CFG", REG_MMIO, 0x7d9, &mmCHUB_ATC_PERFCOUNTER1_CFG[0], sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG)/sizeof(mmCHUB_ATC_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7da, &mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL)/sizeof(mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_GRUB_PERFCOUNTER_LO", REG_MMIO, 0x7e4, &mmMC_GRUB_PERFCOUNTER_LO[0], sizeof(mmMC_GRUB_PERFCOUNTER_LO)/sizeof(mmMC_GRUB_PERFCOUNTER_LO[0]), 0, 0 },
+	{ "mmMC_GRUB_PERFCOUNTER_HI", REG_MMIO, 0x7e5, &mmMC_GRUB_PERFCOUNTER_HI[0], sizeof(mmMC_GRUB_PERFCOUNTER_HI)/sizeof(mmMC_GRUB_PERFCOUNTER_HI[0]), 0, 0 },
+	{ "mmMC_GRUB_PERFCOUNTER0_CFG", REG_MMIO, 0x7e6, &mmMC_GRUB_PERFCOUNTER0_CFG[0], sizeof(mmMC_GRUB_PERFCOUNTER0_CFG)/sizeof(mmMC_GRUB_PERFCOUNTER0_CFG[0]), 0, 0 },
+	{ "mmMC_GRUB_PERFCOUNTER1_CFG", REG_MMIO, 0x7e7, &mmMC_GRUB_PERFCOUNTER1_CFG[0], sizeof(mmMC_GRUB_PERFCOUNTER1_CFG)/sizeof(mmMC_GRUB_PERFCOUNTER1_CFG[0]), 0, 0 },
+	{ "mmMC_GRUB_PERFCOUNTER_RSLT_CNTL", REG_MMIO, 0x7e8, &mmMC_GRUB_PERFCOUNTER_RSLT_CNTL[0], sizeof(mmMC_GRUB_PERFCOUNTER_RSLT_CNTL)/sizeof(mmMC_GRUB_PERFCOUNTER_RSLT_CNTL[0]), 0, 0 },
+	{ "mmMC_CONFIG", REG_MMIO, 0x800, &mmMC_CONFIG[0], sizeof(mmMC_CONFIG)/sizeof(mmMC_CONFIG[0]), 0, 0 },
+	{ "mmMC_SHARED_CHMAP", REG_MMIO, 0x801, &mmMC_SHARED_CHMAP[0], sizeof(mmMC_SHARED_CHMAP)/sizeof(mmMC_SHARED_CHMAP[0]), 0, 0 },
+	{ "mmMC_SHARED_CHREMAP", REG_MMIO, 0x802, &mmMC_SHARED_CHREMAP[0], sizeof(mmMC_SHARED_CHREMAP)/sizeof(mmMC_SHARED_CHREMAP[0]), 0, 0 },
+	{ "mmMC_RD_GRP_GFX", REG_MMIO, 0x803, &mmMC_RD_GRP_GFX[0], sizeof(mmMC_RD_GRP_GFX)/sizeof(mmMC_RD_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_WR_GRP_GFX", REG_MMIO, 0x804, &mmMC_WR_GRP_GFX[0], sizeof(mmMC_WR_GRP_GFX)/sizeof(mmMC_WR_GRP_GFX[0]), 0, 0 },
+	{ "mmMC_RD_GRP_SYS", REG_MMIO, 0x805, &mmMC_RD_GRP_SYS[0], sizeof(mmMC_RD_GRP_SYS)/sizeof(mmMC_RD_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_WR_GRP_SYS", REG_MMIO, 0x806, &mmMC_WR_GRP_SYS[0], sizeof(mmMC_WR_GRP_SYS)/sizeof(mmMC_WR_GRP_SYS[0]), 0, 0 },
+	{ "mmMC_RD_GRP_OTH", REG_MMIO, 0x807, &mmMC_RD_GRP_OTH[0], sizeof(mmMC_RD_GRP_OTH)/sizeof(mmMC_RD_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_WR_GRP_OTH", REG_MMIO, 0x808, &mmMC_WR_GRP_OTH[0], sizeof(mmMC_WR_GRP_OTH)/sizeof(mmMC_WR_GRP_OTH[0]), 0, 0 },
+	{ "mmMC_VM_FB_LOCATION", REG_MMIO, 0x809, &mmMC_VM_FB_LOCATION[0], sizeof(mmMC_VM_FB_LOCATION)/sizeof(mmMC_VM_FB_LOCATION[0]), 0, 0 },
+	{ "mmMC_VM_AGP_TOP", REG_MMIO, 0x80a, &mmMC_VM_AGP_TOP[0], sizeof(mmMC_VM_AGP_TOP)/sizeof(mmMC_VM_AGP_TOP[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BOT", REG_MMIO, 0x80b, &mmMC_VM_AGP_BOT[0], sizeof(mmMC_VM_AGP_BOT)/sizeof(mmMC_VM_AGP_BOT[0]), 0, 0 },
+	{ "mmMC_VM_AGP_BASE", REG_MMIO, 0x80c, &mmMC_VM_AGP_BASE[0], sizeof(mmMC_VM_AGP_BASE)/sizeof(mmMC_VM_AGP_BASE[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_LOW_ADDR", REG_MMIO, 0x80d, &mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR", REG_MMIO, 0x80e, &mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR", REG_MMIO, 0x80f, &mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0], sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR)/sizeof(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_CNTL", REG_MMIO, 0x810, &mmMC_VM_DC_WRITE_CNTL[0], sizeof(mmMC_VM_DC_WRITE_CNTL)/sizeof(mmMC_VM_DC_WRITE_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR", REG_MMIO, 0x811, &mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR", REG_MMIO, 0x812, &mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR", REG_MMIO, 0x813, &mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR", REG_MMIO, 0x814, &mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR", REG_MMIO, 0x815, &mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR", REG_MMIO, 0x816, &mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR", REG_MMIO, 0x817, &mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR", REG_MMIO, 0x818, &mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0], sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR)/sizeof(mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR[0]), 0, 0 },
+	{ "mmMC_VM_MX_L1_TLB_CNTL", REG_MMIO, 0x819, &mmMC_VM_MX_L1_TLB_CNTL[0], sizeof(mmMC_VM_MX_L1_TLB_CNTL)/sizeof(mmMC_VM_MX_L1_TLB_CNTL[0]), 0, 0 },
+	{ "mmMC_VM_FB_OFFSET", REG_MMIO, 0x81a, &mmMC_VM_FB_OFFSET[0], sizeof(mmMC_VM_FB_OFFSET)/sizeof(mmMC_VM_FB_OFFSET[0]), 0, 0 },
+	{ "mmMC_VM_STEERING", REG_MMIO, 0x81b, &mmMC_VM_STEERING[0], sizeof(mmMC_VM_STEERING)/sizeof(mmMC_VM_STEERING[0]), 0, 0 },
+	{ "mmMC_SHARED_CHREMAP2", REG_MMIO, 0x81c, &mmMC_SHARED_CHREMAP2[0], sizeof(mmMC_SHARED_CHREMAP2)/sizeof(mmMC_SHARED_CHREMAP2[0]), 0, 0 },
+	{ "mmMC_SHARED_VF_ENABLE", REG_MMIO, 0x81d, &mmMC_SHARED_VF_ENABLE[0], sizeof(mmMC_SHARED_VF_ENABLE)/sizeof(mmMC_SHARED_VF_ENABLE[0]), 0, 0 },
+	{ "mmMC_SHARED_VIRT_RESET_REQ", REG_MMIO, 0x81e, &mmMC_SHARED_VIRT_RESET_REQ[0], sizeof(mmMC_SHARED_VIRT_RESET_REQ)/sizeof(mmMC_SHARED_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmMC_SHARED_ACTIVE_FCN_ID", REG_MMIO, 0x81f, &mmMC_SHARED_ACTIVE_FCN_ID[0], sizeof(mmMC_SHARED_ACTIVE_FCN_ID)/sizeof(mmMC_SHARED_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmMC_CONFIG_MCD", REG_MMIO, 0x828, &mmMC_CONFIG_MCD[0], sizeof(mmMC_CONFIG_MCD)/sizeof(mmMC_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG_MCD", REG_MMIO, 0x829, &mmMC_CG_CONFIG_MCD[0], sizeof(mmMC_CG_CONFIG_MCD)/sizeof(mmMC_CG_CONFIG_MCD[0]), 0, 0 },
+	{ "mmMC_MEM_POWER_LS", REG_MMIO, 0x82a, &mmMC_MEM_POWER_LS[0], sizeof(mmMC_MEM_POWER_LS)/sizeof(mmMC_MEM_POWER_LS[0]), 0, 0 },
+	{ "mmMC_SHARED_BLACKOUT_CNTL", REG_MMIO, 0x82b, &mmMC_SHARED_BLACKOUT_CNTL[0], sizeof(mmMC_SHARED_BLACKOUT_CNTL)/sizeof(mmMC_SHARED_BLACKOUT_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_POWER", REG_MMIO, 0x82d, &mmMC_HUB_MISC_POWER[0], sizeof(mmMC_HUB_MISC_POWER)/sizeof(mmMC_HUB_MISC_POWER[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_HUB_CG", REG_MMIO, 0x82e, &mmMC_HUB_MISC_HUB_CG[0], sizeof(mmMC_HUB_MISC_HUB_CG)/sizeof(mmMC_HUB_MISC_HUB_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_VM_CG", REG_MMIO, 0x82f, &mmMC_HUB_MISC_VM_CG[0], sizeof(mmMC_HUB_MISC_VM_CG)/sizeof(mmMC_HUB_MISC_VM_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_SIP_CG", REG_MMIO, 0x830, &mmMC_HUB_MISC_SIP_CG[0], sizeof(mmMC_HUB_MISC_SIP_CG)/sizeof(mmMC_HUB_MISC_SIP_CG[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_STATUS", REG_MMIO, 0x832, &mmMC_HUB_MISC_STATUS[0], sizeof(mmMC_HUB_MISC_STATUS)/sizeof(mmMC_HUB_MISC_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_OVERRIDE", REG_MMIO, 0x833, &mmMC_HUB_MISC_OVERRIDE[0], sizeof(mmMC_HUB_MISC_OVERRIDE)/sizeof(mmMC_HUB_MISC_OVERRIDE[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_FRAMING", REG_MMIO, 0x834, &mmMC_HUB_MISC_FRAMING[0], sizeof(mmMC_HUB_MISC_FRAMING)/sizeof(mmMC_HUB_MISC_FRAMING[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CNTL", REG_MMIO, 0x835, &mmMC_HUB_WDP_CNTL[0], sizeof(mmMC_HUB_WDP_CNTL)/sizeof(mmMC_HUB_WDP_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ERR", REG_MMIO, 0x836, &mmMC_HUB_WDP_ERR[0], sizeof(mmMC_HUB_WDP_ERR)/sizeof(mmMC_HUB_WDP_ERR[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BP", REG_MMIO, 0x837, &mmMC_HUB_WDP_BP[0], sizeof(mmMC_HUB_WDP_BP)/sizeof(mmMC_HUB_WDP_BP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_STATUS", REG_MMIO, 0x838, &mmMC_HUB_WDP_STATUS[0], sizeof(mmMC_HUB_WDP_STATUS)/sizeof(mmMC_HUB_WDP_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_STATUS", REG_MMIO, 0x839, &mmMC_HUB_RDREQ_STATUS[0], sizeof(mmMC_HUB_RDREQ_STATUS)/sizeof(mmMC_HUB_RDREQ_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_STATUS", REG_MMIO, 0x83a, &mmMC_HUB_WRRET_STATUS[0], sizeof(mmMC_HUB_WRRET_STATUS)/sizeof(mmMC_HUB_WRRET_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CNTL", REG_MMIO, 0x83b, &mmMC_HUB_RDREQ_CNTL[0], sizeof(mmMC_HUB_RDREQ_CNTL)/sizeof(mmMC_HUB_RDREQ_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_CNTL", REG_MMIO, 0x83c, &mmMC_HUB_WRRET_CNTL[0], sizeof(mmMC_HUB_WRRET_CNTL)/sizeof(mmMC_HUB_WRRET_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_WTM_CNTL", REG_MMIO, 0x83d, &mmMC_HUB_RDREQ_WTM_CNTL[0], sizeof(mmMC_HUB_RDREQ_WTM_CNTL)/sizeof(mmMC_HUB_RDREQ_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_WTM_CNTL", REG_MMIO, 0x83e, &mmMC_HUB_WDP_WTM_CNTL[0], sizeof(mmMC_HUB_WDP_WTM_CNTL)/sizeof(mmMC_HUB_WDP_WTM_CNTL[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS", REG_MMIO, 0x83f, &mmMC_HUB_WDP_CREDITS[0], sizeof(mmMC_HUB_WDP_CREDITS)/sizeof(mmMC_HUB_WDP_CREDITS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS2", REG_MMIO, 0x840, &mmMC_HUB_WDP_CREDITS2[0], sizeof(mmMC_HUB_WDP_CREDITS2)/sizeof(mmMC_HUB_WDP_CREDITS2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL0", REG_MMIO, 0x841, &mmMC_HUB_WDP_GBL0[0], sizeof(mmMC_HUB_WDP_GBL0)/sizeof(mmMC_HUB_WDP_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_GBL1", REG_MMIO, 0x842, &mmMC_HUB_WDP_GBL1[0], sizeof(mmMC_HUB_WDP_GBL1)/sizeof(mmMC_HUB_WDP_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS", REG_MMIO, 0x844, &mmMC_HUB_RDREQ_CREDITS[0], sizeof(mmMC_HUB_RDREQ_CREDITS)/sizeof(mmMC_HUB_RDREQ_CREDITS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_CREDITS2", REG_MMIO, 0x845, &mmMC_HUB_RDREQ_CREDITS2[0], sizeof(mmMC_HUB_RDREQ_CREDITS2)/sizeof(mmMC_HUB_RDREQ_CREDITS2[0]), 0, 0 },
+	{ "mmMC_HUB_SHARED_DAGB_DLY", REG_MMIO, 0x846, &mmMC_HUB_SHARED_DAGB_DLY[0], sizeof(mmMC_HUB_SHARED_DAGB_DLY)/sizeof(mmMC_HUB_SHARED_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_IDLE_STATUS", REG_MMIO, 0x847, &mmMC_HUB_MISC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_IDLE_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF_LIMIT", REG_MMIO, 0x848, &mmMC_HUB_RDREQ_DMIF_LIMIT[0], sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT)/sizeof(mmMC_HUB_RDREQ_DMIF_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPG_LIMIT", REG_MMIO, 0x849, &mmMC_HUB_RDREQ_ACPG_LIMIT[0], sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT)/sizeof(mmMC_HUB_RDREQ_ACPG_LIMIT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BYPASS_GBL0", REG_MMIO, 0x84a, &mmMC_HUB_WDP_BYPASS_GBL0[0], sizeof(mmMC_HUB_WDP_BYPASS_GBL0)/sizeof(mmMC_HUB_WDP_BYPASS_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BYPASS_GBL1", REG_MMIO, 0x84b, &mmMC_HUB_WDP_BYPASS_GBL1[0], sizeof(mmMC_HUB_WDP_BYPASS_GBL1)/sizeof(mmMC_HUB_WDP_BYPASS_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_BYPASS_GBL0", REG_MMIO, 0x84c, &mmMC_HUB_RDREQ_BYPASS_GBL0[0], sizeof(mmMC_HUB_RDREQ_BYPASS_GBL0)/sizeof(mmMC_HUB_RDREQ_BYPASS_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH2", REG_MMIO, 0x84d, &mmMC_HUB_WDP_SH2[0], sizeof(mmMC_HUB_WDP_SH2)/sizeof(mmMC_HUB_WDP_SH2[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH3", REG_MMIO, 0x84e, &mmMC_HUB_WDP_SH3[0], sizeof(mmMC_HUB_WDP_SH3)/sizeof(mmMC_HUB_WDP_SH3[0]), 0, 0 },
+	{ "mmMC_HUB_MISC_ATOMIC_IDLE_STATUS", REG_MMIO, 0x84f, &mmMC_HUB_MISC_ATOMIC_IDLE_STATUS[0], sizeof(mmMC_HUB_MISC_ATOMIC_IDLE_STATUS)/sizeof(mmMC_HUB_MISC_ATOMIC_IDLE_STATUS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDW", REG_MMIO, 0x851, &mmMC_HUB_RDREQ_MCDW[0], sizeof(mmMC_HUB_RDREQ_MCDW)/sizeof(mmMC_HUB_RDREQ_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDX", REG_MMIO, 0x852, &mmMC_HUB_RDREQ_MCDX[0], sizeof(mmMC_HUB_RDREQ_MCDX)/sizeof(mmMC_HUB_RDREQ_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDY", REG_MMIO, 0x853, &mmMC_HUB_RDREQ_MCDY[0], sizeof(mmMC_HUB_RDREQ_MCDY)/sizeof(mmMC_HUB_RDREQ_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDZ", REG_MMIO, 0x854, &mmMC_HUB_RDREQ_MCDZ[0], sizeof(mmMC_HUB_RDREQ_MCDZ)/sizeof(mmMC_HUB_RDREQ_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SIP", REG_MMIO, 0x855, &mmMC_HUB_RDREQ_SIP[0], sizeof(mmMC_HUB_RDREQ_SIP)/sizeof(mmMC_HUB_RDREQ_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL0", REG_MMIO, 0x856, &mmMC_HUB_RDREQ_GBL0[0], sizeof(mmMC_HUB_RDREQ_GBL0)/sizeof(mmMC_HUB_RDREQ_GBL0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_GBL1", REG_MMIO, 0x857, &mmMC_HUB_RDREQ_GBL1[0], sizeof(mmMC_HUB_RDREQ_GBL1)/sizeof(mmMC_HUB_RDREQ_GBL1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SMU", REG_MMIO, 0x858, &mmMC_HUB_RDREQ_SMU[0], sizeof(mmMC_HUB_RDREQ_SMU)/sizeof(mmMC_HUB_RDREQ_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SDMA0", REG_MMIO, 0x859, &mmMC_HUB_RDREQ_SDMA0[0], sizeof(mmMC_HUB_RDREQ_SDMA0)/sizeof(mmMC_HUB_RDREQ_SDMA0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_HDP", REG_MMIO, 0x85a, &mmMC_HUB_RDREQ_HDP[0], sizeof(mmMC_HUB_RDREQ_HDP)/sizeof(mmMC_HUB_RDREQ_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SDMA1", REG_MMIO, 0x85b, &mmMC_HUB_RDREQ_SDMA1[0], sizeof(mmMC_HUB_RDREQ_SDMA1)/sizeof(mmMC_HUB_RDREQ_SDMA1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_RLC", REG_MMIO, 0x85c, &mmMC_HUB_RDREQ_RLC[0], sizeof(mmMC_HUB_RDREQ_RLC)/sizeof(mmMC_HUB_RDREQ_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SEM", REG_MMIO, 0x85d, &mmMC_HUB_RDREQ_SEM[0], sizeof(mmMC_HUB_RDREQ_SEM)/sizeof(mmMC_HUB_RDREQ_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCE0", REG_MMIO, 0x85e, &mmMC_HUB_RDREQ_VCE0[0], sizeof(mmMC_HUB_RDREQ_VCE0)/sizeof(mmMC_HUB_RDREQ_VCE0[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UMC", REG_MMIO, 0x85f, &mmMC_HUB_RDREQ_UMC[0], sizeof(mmMC_HUB_RDREQ_UMC)/sizeof(mmMC_HUB_RDREQ_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_UVD", REG_MMIO, 0x860, &mmMC_HUB_RDREQ_UVD[0], sizeof(mmMC_HUB_RDREQ_UVD)/sizeof(mmMC_HUB_RDREQ_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_DMIF", REG_MMIO, 0x862, &mmMC_HUB_RDREQ_DMIF[0], sizeof(mmMC_HUB_RDREQ_DMIF)/sizeof(mmMC_HUB_RDREQ_DMIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCIF", REG_MMIO, 0x863, &mmMC_HUB_RDREQ_MCIF[0], sizeof(mmMC_HUB_RDREQ_MCIF)/sizeof(mmMC_HUB_RDREQ_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VMC", REG_MMIO, 0x864, &mmMC_HUB_RDREQ_VMC[0], sizeof(mmMC_HUB_RDREQ_VMC)/sizeof(mmMC_HUB_RDREQ_VMC[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCEU0", REG_MMIO, 0x865, &mmMC_HUB_RDREQ_VCEU0[0], sizeof(mmMC_HUB_RDREQ_VCEU0)/sizeof(mmMC_HUB_RDREQ_VCEU0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDW", REG_MMIO, 0x866, &mmMC_HUB_WDP_MCDW[0], sizeof(mmMC_HUB_WDP_MCDW)/sizeof(mmMC_HUB_WDP_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDX", REG_MMIO, 0x867, &mmMC_HUB_WDP_MCDX[0], sizeof(mmMC_HUB_WDP_MCDX)/sizeof(mmMC_HUB_WDP_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDY", REG_MMIO, 0x868, &mmMC_HUB_WDP_MCDY[0], sizeof(mmMC_HUB_WDP_MCDY)/sizeof(mmMC_HUB_WDP_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDZ", REG_MMIO, 0x869, &mmMC_HUB_WDP_MCDZ[0], sizeof(mmMC_HUB_WDP_MCDZ)/sizeof(mmMC_HUB_WDP_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SIP", REG_MMIO, 0x86a, &mmMC_HUB_WDP_SIP[0], sizeof(mmMC_HUB_WDP_SIP)/sizeof(mmMC_HUB_WDP_SIP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SDMA1", REG_MMIO, 0x86b, &mmMC_HUB_WDP_SDMA1[0], sizeof(mmMC_HUB_WDP_SDMA1)/sizeof(mmMC_HUB_WDP_SDMA1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH0", REG_MMIO, 0x86c, &mmMC_HUB_WDP_SH0[0], sizeof(mmMC_HUB_WDP_SH0)/sizeof(mmMC_HUB_WDP_SH0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCIF", REG_MMIO, 0x86d, &mmMC_HUB_WDP_MCIF[0], sizeof(mmMC_HUB_WDP_MCIF)/sizeof(mmMC_HUB_WDP_MCIF[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCE0", REG_MMIO, 0x86e, &mmMC_HUB_WDP_VCE0[0], sizeof(mmMC_HUB_WDP_VCE0)/sizeof(mmMC_HUB_WDP_VCE0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDP", REG_MMIO, 0x86f, &mmMC_HUB_WDP_XDP[0], sizeof(mmMC_HUB_WDP_XDP)/sizeof(mmMC_HUB_WDP_XDP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_IH", REG_MMIO, 0x870, &mmMC_HUB_WDP_IH[0], sizeof(mmMC_HUB_WDP_IH)/sizeof(mmMC_HUB_WDP_IH[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_RLC", REG_MMIO, 0x871, &mmMC_HUB_WDP_RLC[0], sizeof(mmMC_HUB_WDP_RLC)/sizeof(mmMC_HUB_WDP_RLC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SEM", REG_MMIO, 0x872, &mmMC_HUB_WDP_SEM[0], sizeof(mmMC_HUB_WDP_SEM)/sizeof(mmMC_HUB_WDP_SEM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SMU", REG_MMIO, 0x873, &mmMC_HUB_WDP_SMU[0], sizeof(mmMC_HUB_WDP_SMU)/sizeof(mmMC_HUB_WDP_SMU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SH1", REG_MMIO, 0x874, &mmMC_HUB_WDP_SH1[0], sizeof(mmMC_HUB_WDP_SH1)/sizeof(mmMC_HUB_WDP_SH1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UMC", REG_MMIO, 0x875, &mmMC_HUB_WDP_UMC[0], sizeof(mmMC_HUB_WDP_UMC)/sizeof(mmMC_HUB_WDP_UMC[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_UVD", REG_MMIO, 0x876, &mmMC_HUB_WDP_UVD[0], sizeof(mmMC_HUB_WDP_UVD)/sizeof(mmMC_HUB_WDP_UVD[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_HDP", REG_MMIO, 0x877, &mmMC_HUB_WDP_HDP[0], sizeof(mmMC_HUB_WDP_HDP)/sizeof(mmMC_HUB_WDP_HDP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SDMA0", REG_MMIO, 0x878, &mmMC_HUB_WDP_SDMA0[0], sizeof(mmMC_HUB_WDP_SDMA0)/sizeof(mmMC_HUB_WDP_SDMA0[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDW", REG_MMIO, 0x879, &mmMC_HUB_WRRET_MCDW[0], sizeof(mmMC_HUB_WRRET_MCDW)/sizeof(mmMC_HUB_WRRET_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDX", REG_MMIO, 0x87a, &mmMC_HUB_WRRET_MCDX[0], sizeof(mmMC_HUB_WRRET_MCDX)/sizeof(mmMC_HUB_WRRET_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDY", REG_MMIO, 0x87b, &mmMC_HUB_WRRET_MCDY[0], sizeof(mmMC_HUB_WRRET_MCDY)/sizeof(mmMC_HUB_WRRET_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDZ", REG_MMIO, 0x87c, &mmMC_HUB_WRRET_MCDZ[0], sizeof(mmMC_HUB_WRRET_MCDZ)/sizeof(mmMC_HUB_WRRET_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCEU0", REG_MMIO, 0x87d, &mmMC_HUB_WDP_VCEU0[0], sizeof(mmMC_HUB_WDP_VCEU0)/sizeof(mmMC_HUB_WDP_VCEU0[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMAM", REG_MMIO, 0x87e, &mmMC_HUB_WDP_XDMAM[0], sizeof(mmMC_HUB_WDP_XDMAM)/sizeof(mmMC_HUB_WDP_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_XDMA", REG_MMIO, 0x87f, &mmMC_HUB_WDP_XDMA[0], sizeof(mmMC_HUB_WDP_XDMA)/sizeof(mmMC_HUB_WDP_XDMA[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_XDMAM", REG_MMIO, 0x880, &mmMC_HUB_RDREQ_XDMAM[0], sizeof(mmMC_HUB_RDREQ_XDMAM)/sizeof(mmMC_HUB_RDREQ_XDMAM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPG", REG_MMIO, 0x881, &mmMC_HUB_RDREQ_ACPG[0], sizeof(mmMC_HUB_RDREQ_ACPG)/sizeof(mmMC_HUB_RDREQ_ACPG[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ACPO", REG_MMIO, 0x882, &mmMC_HUB_RDREQ_ACPO[0], sizeof(mmMC_HUB_RDREQ_ACPO)/sizeof(mmMC_HUB_RDREQ_ACPO[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_SAMMSP", REG_MMIO, 0x883, &mmMC_HUB_RDREQ_SAMMSP[0], sizeof(mmMC_HUB_RDREQ_SAMMSP)/sizeof(mmMC_HUB_RDREQ_SAMMSP[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VP8", REG_MMIO, 0x884, &mmMC_HUB_RDREQ_VP8[0], sizeof(mmMC_HUB_RDREQ_VP8)/sizeof(mmMC_HUB_RDREQ_VP8[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VP8U", REG_MMIO, 0x885, &mmMC_HUB_RDREQ_VP8U[0], sizeof(mmMC_HUB_RDREQ_VP8U)/sizeof(mmMC_HUB_RDREQ_VP8U[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ACPG", REG_MMIO, 0x886, &mmMC_HUB_WDP_ACPG[0], sizeof(mmMC_HUB_WDP_ACPG)/sizeof(mmMC_HUB_WDP_ACPG[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ACPO", REG_MMIO, 0x887, &mmMC_HUB_WDP_ACPO[0], sizeof(mmMC_HUB_WDP_ACPO)/sizeof(mmMC_HUB_WDP_ACPO[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_SAMMSP", REG_MMIO, 0x888, &mmMC_HUB_WDP_SAMMSP[0], sizeof(mmMC_HUB_WDP_SAMMSP)/sizeof(mmMC_HUB_WDP_SAMMSP[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VP8", REG_MMIO, 0x889, &mmMC_HUB_WDP_VP8[0], sizeof(mmMC_HUB_WDP_VP8)/sizeof(mmMC_HUB_WDP_VP8[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VP8U", REG_MMIO, 0x88a, &mmMC_HUB_WDP_VP8U[0], sizeof(mmMC_HUB_WDP_VP8U)/sizeof(mmMC_HUB_WDP_VP8U[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_DEBUG", REG_MMIO, 0x891, &mmMC_VM_MB_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB1_DEBUG", REG_MMIO, 0x892, &mmMC_VM_MB_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB1_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_DEBUG", REG_MMIO, 0x893, &mmMC_VM_MB_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB0_STATUS", REG_MMIO, 0x895, &mmMC_VM_MB_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB0_STATUS)/sizeof(mmMC_VM_MB_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB1_STATUS", REG_MMIO, 0x896, &mmMC_VM_MB_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB1_STATUS)/sizeof(mmMC_VM_MB_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB2_STATUS", REG_MMIO, 0x897, &mmMC_VM_MB_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB2_STATUS)/sizeof(mmMC_VM_MB_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L2ARBITER_L2_CREDITS", REG_MMIO, 0x8a1, &mmMC_VM_MB_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MB_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_DEBUG", REG_MMIO, 0x8a5, &mmMC_VM_MB_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MB_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MB_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MB_L1_TLB3_STATUS", REG_MMIO, 0x8a6, &mmMC_VM_MB_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MB_L1_TLB3_STATUS)/sizeof(mmMC_VM_MB_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR0", REG_MMIO, 0x8cd, &mmMC_XPB_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR1", REG_MMIO, 0x8ce, &mmMC_XPB_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR2", REG_MMIO, 0x8cf, &mmMC_XPB_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR3", REG_MMIO, 0x8d0, &mmMC_XPB_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR4", REG_MMIO, 0x8d1, &mmMC_XPB_RTR_SRC_APRTR4[0], sizeof(mmMC_XPB_RTR_SRC_APRTR4)/sizeof(mmMC_XPB_RTR_SRC_APRTR4[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR5", REG_MMIO, 0x8d2, &mmMC_XPB_RTR_SRC_APRTR5[0], sizeof(mmMC_XPB_RTR_SRC_APRTR5)/sizeof(mmMC_XPB_RTR_SRC_APRTR5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR6", REG_MMIO, 0x8d3, &mmMC_XPB_RTR_SRC_APRTR6[0], sizeof(mmMC_XPB_RTR_SRC_APRTR6)/sizeof(mmMC_XPB_RTR_SRC_APRTR6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR7", REG_MMIO, 0x8d4, &mmMC_XPB_RTR_SRC_APRTR7[0], sizeof(mmMC_XPB_RTR_SRC_APRTR7)/sizeof(mmMC_XPB_RTR_SRC_APRTR7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR8", REG_MMIO, 0x8d5, &mmMC_XPB_RTR_SRC_APRTR8[0], sizeof(mmMC_XPB_RTR_SRC_APRTR8)/sizeof(mmMC_XPB_RTR_SRC_APRTR8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_SRC_APRTR9", REG_MMIO, 0x8d6, &mmMC_XPB_RTR_SRC_APRTR9[0], sizeof(mmMC_XPB_RTR_SRC_APRTR9)/sizeof(mmMC_XPB_RTR_SRC_APRTR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR0", REG_MMIO, 0x8d7, &mmMC_XPB_XDMA_RTR_SRC_APRTR0[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR1", REG_MMIO, 0x8d8, &mmMC_XPB_XDMA_RTR_SRC_APRTR1[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR2", REG_MMIO, 0x8d9, &mmMC_XPB_XDMA_RTR_SRC_APRTR2[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_SRC_APRTR3", REG_MMIO, 0x8da, &mmMC_XPB_XDMA_RTR_SRC_APRTR3[0], sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3)/sizeof(mmMC_XPB_XDMA_RTR_SRC_APRTR3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP0", REG_MMIO, 0x8db, &mmMC_XPB_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_RTR_DEST_MAP0)/sizeof(mmMC_XPB_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP1", REG_MMIO, 0x8dc, &mmMC_XPB_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_RTR_DEST_MAP1)/sizeof(mmMC_XPB_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP2", REG_MMIO, 0x8dd, &mmMC_XPB_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_RTR_DEST_MAP2)/sizeof(mmMC_XPB_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP3", REG_MMIO, 0x8de, &mmMC_XPB_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_RTR_DEST_MAP3)/sizeof(mmMC_XPB_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP4", REG_MMIO, 0x8df, &mmMC_XPB_RTR_DEST_MAP4[0], sizeof(mmMC_XPB_RTR_DEST_MAP4)/sizeof(mmMC_XPB_RTR_DEST_MAP4[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP5", REG_MMIO, 0x8e0, &mmMC_XPB_RTR_DEST_MAP5[0], sizeof(mmMC_XPB_RTR_DEST_MAP5)/sizeof(mmMC_XPB_RTR_DEST_MAP5[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP6", REG_MMIO, 0x8e1, &mmMC_XPB_RTR_DEST_MAP6[0], sizeof(mmMC_XPB_RTR_DEST_MAP6)/sizeof(mmMC_XPB_RTR_DEST_MAP6[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP7", REG_MMIO, 0x8e2, &mmMC_XPB_RTR_DEST_MAP7[0], sizeof(mmMC_XPB_RTR_DEST_MAP7)/sizeof(mmMC_XPB_RTR_DEST_MAP7[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP8", REG_MMIO, 0x8e3, &mmMC_XPB_RTR_DEST_MAP8[0], sizeof(mmMC_XPB_RTR_DEST_MAP8)/sizeof(mmMC_XPB_RTR_DEST_MAP8[0]), 0, 0 },
+	{ "mmMC_XPB_RTR_DEST_MAP9", REG_MMIO, 0x8e4, &mmMC_XPB_RTR_DEST_MAP9[0], sizeof(mmMC_XPB_RTR_DEST_MAP9)/sizeof(mmMC_XPB_RTR_DEST_MAP9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP0", REG_MMIO, 0x8e5, &mmMC_XPB_XDMA_RTR_DEST_MAP0[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP1", REG_MMIO, 0x8e6, &mmMC_XPB_XDMA_RTR_DEST_MAP1[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP2", REG_MMIO, 0x8e7, &mmMC_XPB_XDMA_RTR_DEST_MAP2[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_RTR_DEST_MAP3", REG_MMIO, 0x8e8, &mmMC_XPB_XDMA_RTR_DEST_MAP3[0], sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3)/sizeof(mmMC_XPB_XDMA_RTR_DEST_MAP3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG0", REG_MMIO, 0x8e9, &mmMC_XPB_CLG_CFG0[0], sizeof(mmMC_XPB_CLG_CFG0)/sizeof(mmMC_XPB_CLG_CFG0[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG1", REG_MMIO, 0x8ea, &mmMC_XPB_CLG_CFG1[0], sizeof(mmMC_XPB_CLG_CFG1)/sizeof(mmMC_XPB_CLG_CFG1[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG2", REG_MMIO, 0x8eb, &mmMC_XPB_CLG_CFG2[0], sizeof(mmMC_XPB_CLG_CFG2)/sizeof(mmMC_XPB_CLG_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG3", REG_MMIO, 0x8ec, &mmMC_XPB_CLG_CFG3[0], sizeof(mmMC_XPB_CLG_CFG3)/sizeof(mmMC_XPB_CLG_CFG3[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG4", REG_MMIO, 0x8ed, &mmMC_XPB_CLG_CFG4[0], sizeof(mmMC_XPB_CLG_CFG4)/sizeof(mmMC_XPB_CLG_CFG4[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG5", REG_MMIO, 0x8ee, &mmMC_XPB_CLG_CFG5[0], sizeof(mmMC_XPB_CLG_CFG5)/sizeof(mmMC_XPB_CLG_CFG5[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG6", REG_MMIO, 0x8ef, &mmMC_XPB_CLG_CFG6[0], sizeof(mmMC_XPB_CLG_CFG6)/sizeof(mmMC_XPB_CLG_CFG6[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG7", REG_MMIO, 0x8f0, &mmMC_XPB_CLG_CFG7[0], sizeof(mmMC_XPB_CLG_CFG7)/sizeof(mmMC_XPB_CLG_CFG7[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG8", REG_MMIO, 0x8f1, &mmMC_XPB_CLG_CFG8[0], sizeof(mmMC_XPB_CLG_CFG8)/sizeof(mmMC_XPB_CLG_CFG8[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG9", REG_MMIO, 0x8f2, &mmMC_XPB_CLG_CFG9[0], sizeof(mmMC_XPB_CLG_CFG9)/sizeof(mmMC_XPB_CLG_CFG9[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG10", REG_MMIO, 0x8f3, &mmMC_XPB_CLG_CFG10[0], sizeof(mmMC_XPB_CLG_CFG10)/sizeof(mmMC_XPB_CLG_CFG10[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG11", REG_MMIO, 0x8f4, &mmMC_XPB_CLG_CFG11[0], sizeof(mmMC_XPB_CLG_CFG11)/sizeof(mmMC_XPB_CLG_CFG11[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG12", REG_MMIO, 0x8f5, &mmMC_XPB_CLG_CFG12[0], sizeof(mmMC_XPB_CLG_CFG12)/sizeof(mmMC_XPB_CLG_CFG12[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG13", REG_MMIO, 0x8f6, &mmMC_XPB_CLG_CFG13[0], sizeof(mmMC_XPB_CLG_CFG13)/sizeof(mmMC_XPB_CLG_CFG13[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG14", REG_MMIO, 0x8f7, &mmMC_XPB_CLG_CFG14[0], sizeof(mmMC_XPB_CLG_CFG14)/sizeof(mmMC_XPB_CLG_CFG14[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG15", REG_MMIO, 0x8f8, &mmMC_XPB_CLG_CFG15[0], sizeof(mmMC_XPB_CLG_CFG15)/sizeof(mmMC_XPB_CLG_CFG15[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG16", REG_MMIO, 0x8f9, &mmMC_XPB_CLG_CFG16[0], sizeof(mmMC_XPB_CLG_CFG16)/sizeof(mmMC_XPB_CLG_CFG16[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG17", REG_MMIO, 0x8fa, &mmMC_XPB_CLG_CFG17[0], sizeof(mmMC_XPB_CLG_CFG17)/sizeof(mmMC_XPB_CLG_CFG17[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG18", REG_MMIO, 0x8fb, &mmMC_XPB_CLG_CFG18[0], sizeof(mmMC_XPB_CLG_CFG18)/sizeof(mmMC_XPB_CLG_CFG18[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG19", REG_MMIO, 0x8fc, &mmMC_XPB_CLG_CFG19[0], sizeof(mmMC_XPB_CLG_CFG19)/sizeof(mmMC_XPB_CLG_CFG19[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA", REG_MMIO, 0x8fd, &mmMC_XPB_CLG_EXTRA[0], sizeof(mmMC_XPB_CLG_EXTRA)/sizeof(mmMC_XPB_CLG_EXTRA[0]), 0, 0 },
+	{ "mmMC_XPB_LB_ADDR", REG_MMIO, 0x8fe, &mmMC_XPB_LB_ADDR[0], sizeof(mmMC_XPB_LB_ADDR)/sizeof(mmMC_XPB_LB_ADDR[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_HST", REG_MMIO, 0x8ff, &mmMC_XPB_UNC_THRESH_HST[0], sizeof(mmMC_XPB_UNC_THRESH_HST)/sizeof(mmMC_XPB_UNC_THRESH_HST[0]), 0, 0 },
+	{ "mmMC_XPB_UNC_THRESH_SID", REG_MMIO, 0x900, &mmMC_XPB_UNC_THRESH_SID[0], sizeof(mmMC_XPB_UNC_THRESH_SID)/sizeof(mmMC_XPB_UNC_THRESH_SID[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_STS", REG_MMIO, 0x901, &mmMC_XPB_WCB_STS[0], sizeof(mmMC_XPB_WCB_STS)/sizeof(mmMC_XPB_WCB_STS[0]), 0, 0 },
+	{ "mmMC_XPB_WCB_CFG", REG_MMIO, 0x902, &mmMC_XPB_WCB_CFG[0], sizeof(mmMC_XPB_WCB_CFG)/sizeof(mmMC_XPB_WCB_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_CFG", REG_MMIO, 0x903, &mmMC_XPB_P2P_BAR_CFG[0], sizeof(mmMC_XPB_P2P_BAR_CFG)/sizeof(mmMC_XPB_P2P_BAR_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR0", REG_MMIO, 0x904, &mmMC_XPB_P2P_BAR0[0], sizeof(mmMC_XPB_P2P_BAR0)/sizeof(mmMC_XPB_P2P_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR1", REG_MMIO, 0x905, &mmMC_XPB_P2P_BAR1[0], sizeof(mmMC_XPB_P2P_BAR1)/sizeof(mmMC_XPB_P2P_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR2", REG_MMIO, 0x906, &mmMC_XPB_P2P_BAR2[0], sizeof(mmMC_XPB_P2P_BAR2)/sizeof(mmMC_XPB_P2P_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR3", REG_MMIO, 0x907, &mmMC_XPB_P2P_BAR3[0], sizeof(mmMC_XPB_P2P_BAR3)/sizeof(mmMC_XPB_P2P_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR4", REG_MMIO, 0x908, &mmMC_XPB_P2P_BAR4[0], sizeof(mmMC_XPB_P2P_BAR4)/sizeof(mmMC_XPB_P2P_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR5", REG_MMIO, 0x909, &mmMC_XPB_P2P_BAR5[0], sizeof(mmMC_XPB_P2P_BAR5)/sizeof(mmMC_XPB_P2P_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR6", REG_MMIO, 0x90a, &mmMC_XPB_P2P_BAR6[0], sizeof(mmMC_XPB_P2P_BAR6)/sizeof(mmMC_XPB_P2P_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR7", REG_MMIO, 0x90b, &mmMC_XPB_P2P_BAR7[0], sizeof(mmMC_XPB_P2P_BAR7)/sizeof(mmMC_XPB_P2P_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_SETUP", REG_MMIO, 0x90c, &mmMC_XPB_P2P_BAR_SETUP[0], sizeof(mmMC_XPB_P2P_BAR_SETUP)/sizeof(mmMC_XPB_P2P_BAR_SETUP[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DEBUG", REG_MMIO, 0x90d, &mmMC_XPB_P2P_BAR_DEBUG[0], sizeof(mmMC_XPB_P2P_BAR_DEBUG)/sizeof(mmMC_XPB_P2P_BAR_DEBUG[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_ABOVE", REG_MMIO, 0x90e, &mmMC_XPB_P2P_BAR_DELTA_ABOVE[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE)/sizeof(mmMC_XPB_P2P_BAR_DELTA_ABOVE[0]), 0, 0 },
+	{ "mmMC_XPB_P2P_BAR_DELTA_BELOW", REG_MMIO, 0x90f, &mmMC_XPB_P2P_BAR_DELTA_BELOW[0], sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW)/sizeof(mmMC_XPB_P2P_BAR_DELTA_BELOW[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR0", REG_MMIO, 0x910, &mmMC_XPB_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_PEER_SYS_BAR0)/sizeof(mmMC_XPB_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR1", REG_MMIO, 0x911, &mmMC_XPB_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_PEER_SYS_BAR1)/sizeof(mmMC_XPB_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR2", REG_MMIO, 0x912, &mmMC_XPB_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_PEER_SYS_BAR2)/sizeof(mmMC_XPB_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR3", REG_MMIO, 0x913, &mmMC_XPB_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_PEER_SYS_BAR3)/sizeof(mmMC_XPB_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR4", REG_MMIO, 0x914, &mmMC_XPB_PEER_SYS_BAR4[0], sizeof(mmMC_XPB_PEER_SYS_BAR4)/sizeof(mmMC_XPB_PEER_SYS_BAR4[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR5", REG_MMIO, 0x915, &mmMC_XPB_PEER_SYS_BAR5[0], sizeof(mmMC_XPB_PEER_SYS_BAR5)/sizeof(mmMC_XPB_PEER_SYS_BAR5[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR6", REG_MMIO, 0x916, &mmMC_XPB_PEER_SYS_BAR6[0], sizeof(mmMC_XPB_PEER_SYS_BAR6)/sizeof(mmMC_XPB_PEER_SYS_BAR6[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR7", REG_MMIO, 0x917, &mmMC_XPB_PEER_SYS_BAR7[0], sizeof(mmMC_XPB_PEER_SYS_BAR7)/sizeof(mmMC_XPB_PEER_SYS_BAR7[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR8", REG_MMIO, 0x918, &mmMC_XPB_PEER_SYS_BAR8[0], sizeof(mmMC_XPB_PEER_SYS_BAR8)/sizeof(mmMC_XPB_PEER_SYS_BAR8[0]), 0, 0 },
+	{ "mmMC_XPB_PEER_SYS_BAR9", REG_MMIO, 0x919, &mmMC_XPB_PEER_SYS_BAR9[0], sizeof(mmMC_XPB_PEER_SYS_BAR9)/sizeof(mmMC_XPB_PEER_SYS_BAR9[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR0", REG_MMIO, 0x91a, &mmMC_XPB_XDMA_PEER_SYS_BAR0[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR0[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR1", REG_MMIO, 0x91b, &mmMC_XPB_XDMA_PEER_SYS_BAR1[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR1[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR2", REG_MMIO, 0x91c, &mmMC_XPB_XDMA_PEER_SYS_BAR2[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR2[0]), 0, 0 },
+	{ "mmMC_XPB_XDMA_PEER_SYS_BAR3", REG_MMIO, 0x91d, &mmMC_XPB_XDMA_PEER_SYS_BAR3[0], sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3)/sizeof(mmMC_XPB_XDMA_PEER_SYS_BAR3[0]), 0, 0 },
+	{ "mmMC_XPB_CLK_GAT", REG_MMIO, 0x91e, &mmMC_XPB_CLK_GAT[0], sizeof(mmMC_XPB_CLK_GAT)/sizeof(mmMC_XPB_CLK_GAT[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG", REG_MMIO, 0x91f, &mmMC_XPB_INTF_CFG[0], sizeof(mmMC_XPB_INTF_CFG)/sizeof(mmMC_XPB_INTF_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_STS", REG_MMIO, 0x920, &mmMC_XPB_INTF_STS[0], sizeof(mmMC_XPB_INTF_STS)/sizeof(mmMC_XPB_INTF_STS[0]), 0, 0 },
+	{ "mmMC_XPB_PIPE_STS", REG_MMIO, 0x921, &mmMC_XPB_PIPE_STS[0], sizeof(mmMC_XPB_PIPE_STS)/sizeof(mmMC_XPB_PIPE_STS[0]), 0, 0 },
+	{ "mmMC_XPB_SUB_CTRL", REG_MMIO, 0x922, &mmMC_XPB_SUB_CTRL[0], sizeof(mmMC_XPB_SUB_CTRL)/sizeof(mmMC_XPB_SUB_CTRL[0]), 0, 0 },
+	{ "mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB", REG_MMIO, 0x923, &mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0], sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB)/sizeof(mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB[0]), 0, 0 },
+	{ "mmMC_XPB_PERF_KNOBS", REG_MMIO, 0x924, &mmMC_XPB_PERF_KNOBS[0], sizeof(mmMC_XPB_PERF_KNOBS)/sizeof(mmMC_XPB_PERF_KNOBS[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY", REG_MMIO, 0x925, &mmMC_XPB_STICKY[0], sizeof(mmMC_XPB_STICKY)/sizeof(mmMC_XPB_STICKY[0]), 0, 0 },
+	{ "mmMC_XPB_STICKY_W1C", REG_MMIO, 0x926, &mmMC_XPB_STICKY_W1C[0], sizeof(mmMC_XPB_STICKY_W1C)/sizeof(mmMC_XPB_STICKY_W1C[0]), 0, 0 },
+	{ "mmMC_XPB_MISC_CFG", REG_MMIO, 0x927, &mmMC_XPB_MISC_CFG[0], sizeof(mmMC_XPB_MISC_CFG)/sizeof(mmMC_XPB_MISC_CFG[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG20", REG_MMIO, 0x928, &mmMC_XPB_CLG_CFG20[0], sizeof(mmMC_XPB_CLG_CFG20)/sizeof(mmMC_XPB_CLG_CFG20[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG21", REG_MMIO, 0x929, &mmMC_XPB_CLG_CFG21[0], sizeof(mmMC_XPB_CLG_CFG21)/sizeof(mmMC_XPB_CLG_CFG21[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG22", REG_MMIO, 0x92a, &mmMC_XPB_CLG_CFG22[0], sizeof(mmMC_XPB_CLG_CFG22)/sizeof(mmMC_XPB_CLG_CFG22[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG23", REG_MMIO, 0x92b, &mmMC_XPB_CLG_CFG23[0], sizeof(mmMC_XPB_CLG_CFG23)/sizeof(mmMC_XPB_CLG_CFG23[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG24", REG_MMIO, 0x92c, &mmMC_XPB_CLG_CFG24[0], sizeof(mmMC_XPB_CLG_CFG24)/sizeof(mmMC_XPB_CLG_CFG24[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG25", REG_MMIO, 0x92d, &mmMC_XPB_CLG_CFG25[0], sizeof(mmMC_XPB_CLG_CFG25)/sizeof(mmMC_XPB_CLG_CFG25[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG26", REG_MMIO, 0x92e, &mmMC_XPB_CLG_CFG26[0], sizeof(mmMC_XPB_CLG_CFG26)/sizeof(mmMC_XPB_CLG_CFG26[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG27", REG_MMIO, 0x92f, &mmMC_XPB_CLG_CFG27[0], sizeof(mmMC_XPB_CLG_CFG27)/sizeof(mmMC_XPB_CLG_CFG27[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG28", REG_MMIO, 0x930, &mmMC_XPB_CLG_CFG28[0], sizeof(mmMC_XPB_CLG_CFG28)/sizeof(mmMC_XPB_CLG_CFG28[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG29", REG_MMIO, 0x931, &mmMC_XPB_CLG_CFG29[0], sizeof(mmMC_XPB_CLG_CFG29)/sizeof(mmMC_XPB_CLG_CFG29[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG30", REG_MMIO, 0x932, &mmMC_XPB_CLG_CFG30[0], sizeof(mmMC_XPB_CLG_CFG30)/sizeof(mmMC_XPB_CLG_CFG30[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG31", REG_MMIO, 0x933, &mmMC_XPB_CLG_CFG31[0], sizeof(mmMC_XPB_CLG_CFG31)/sizeof(mmMC_XPB_CLG_CFG31[0]), 0, 0 },
+	{ "mmMC_XPB_INTF_CFG2", REG_MMIO, 0x934, &mmMC_XPB_INTF_CFG2[0], sizeof(mmMC_XPB_INTF_CFG2)/sizeof(mmMC_XPB_INTF_CFG2[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_EXTRA_RD", REG_MMIO, 0x935, &mmMC_XPB_CLG_EXTRA_RD[0], sizeof(mmMC_XPB_CLG_EXTRA_RD)/sizeof(mmMC_XPB_CLG_EXTRA_RD[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG32", REG_MMIO, 0x936, &mmMC_XPB_CLG_CFG32[0], sizeof(mmMC_XPB_CLG_CFG32)/sizeof(mmMC_XPB_CLG_CFG32[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG33", REG_MMIO, 0x937, &mmMC_XPB_CLG_CFG33[0], sizeof(mmMC_XPB_CLG_CFG33)/sizeof(mmMC_XPB_CLG_CFG33[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG34", REG_MMIO, 0x938, &mmMC_XPB_CLG_CFG34[0], sizeof(mmMC_XPB_CLG_CFG34)/sizeof(mmMC_XPB_CLG_CFG34[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG35", REG_MMIO, 0x939, &mmMC_XPB_CLG_CFG35[0], sizeof(mmMC_XPB_CLG_CFG35)/sizeof(mmMC_XPB_CLG_CFG35[0]), 0, 0 },
+	{ "mmMC_XPB_CLG_CFG36", REG_MMIO, 0x93a, &mmMC_XPB_CLG_CFG36[0], sizeof(mmMC_XPB_CLG_CFG36)/sizeof(mmMC_XPB_CLG_CFG36[0]), 0, 0 },
+	{ "mmMC_RPB_CONF", REG_MMIO, 0x94d, &mmMC_RPB_CONF[0], sizeof(mmMC_RPB_CONF)/sizeof(mmMC_RPB_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_IF_CONF", REG_MMIO, 0x94e, &mmMC_RPB_IF_CONF[0], sizeof(mmMC_RPB_IF_CONF)/sizeof(mmMC_RPB_IF_CONF[0]), 0, 0 },
+	{ "mmMC_RPB_DBG1", REG_MMIO, 0x94f, &mmMC_RPB_DBG1[0], sizeof(mmMC_RPB_DBG1)/sizeof(mmMC_RPB_DBG1[0]), 0, 0 },
+	{ "mmMC_RPB_EFF_CNTL", REG_MMIO, 0x950, &mmMC_RPB_EFF_CNTL[0], sizeof(mmMC_RPB_EFF_CNTL)/sizeof(mmMC_RPB_EFF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_ARB_CNTL", REG_MMIO, 0x951, &mmMC_RPB_ARB_CNTL[0], sizeof(mmMC_RPB_ARB_CNTL)/sizeof(mmMC_RPB_ARB_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_BIF_CNTL", REG_MMIO, 0x952, &mmMC_RPB_BIF_CNTL[0], sizeof(mmMC_RPB_BIF_CNTL)/sizeof(mmMC_RPB_BIF_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_SWITCH_CNTL", REG_MMIO, 0x953, &mmMC_RPB_WR_SWITCH_CNTL[0], sizeof(mmMC_RPB_WR_SWITCH_CNTL)/sizeof(mmMC_RPB_WR_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_WR_COMBINE_CNTL", REG_MMIO, 0x954, &mmMC_RPB_WR_COMBINE_CNTL[0], sizeof(mmMC_RPB_WR_COMBINE_CNTL)/sizeof(mmMC_RPB_WR_COMBINE_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_RD_SWITCH_CNTL", REG_MMIO, 0x955, &mmMC_RPB_RD_SWITCH_CNTL[0], sizeof(mmMC_RPB_RD_SWITCH_CNTL)/sizeof(mmMC_RPB_RD_SWITCH_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_WR", REG_MMIO, 0x956, &mmMC_RPB_CID_QUEUE_WR[0], sizeof(mmMC_RPB_CID_QUEUE_WR)/sizeof(mmMC_RPB_CID_QUEUE_WR[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_RD", REG_MMIO, 0x957, &mmMC_RPB_CID_QUEUE_RD[0], sizeof(mmMC_RPB_CID_QUEUE_RD)/sizeof(mmMC_RPB_CID_QUEUE_RD[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_CNTL", REG_MMIO, 0x958, &mmMC_RPB_PERF_COUNTER_CNTL[0], sizeof(mmMC_RPB_PERF_COUNTER_CNTL)/sizeof(mmMC_RPB_PERF_COUNTER_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_PERF_COUNTER_STATUS", REG_MMIO, 0x959, &mmMC_RPB_PERF_COUNTER_STATUS[0], sizeof(mmMC_RPB_PERF_COUNTER_STATUS)/sizeof(mmMC_RPB_PERF_COUNTER_STATUS[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX", REG_MMIO, 0x95a, &mmMC_RPB_CID_QUEUE_EX[0], sizeof(mmMC_RPB_CID_QUEUE_EX)/sizeof(mmMC_RPB_CID_QUEUE_EX[0]), 0, 0 },
+	{ "mmMC_RPB_CID_QUEUE_EX_DATA", REG_MMIO, 0x95b, &mmMC_RPB_CID_QUEUE_EX_DATA[0], sizeof(mmMC_RPB_CID_QUEUE_EX_DATA)/sizeof(mmMC_RPB_CID_QUEUE_EX_DATA[0]), 0, 0 },
+	{ "mmMC_RPB_TCI_CNTL", REG_MMIO, 0x95c, &mmMC_RPB_TCI_CNTL[0], sizeof(mmMC_RPB_TCI_CNTL)/sizeof(mmMC_RPB_TCI_CNTL[0]), 0, 0 },
+	{ "mmMC_RPB_TCI_CNTL2", REG_MMIO, 0x95d, &mmMC_RPB_TCI_CNTL2[0], sizeof(mmMC_RPB_TCI_CNTL2)/sizeof(mmMC_RPB_TCI_CNTL2[0]), 0, 0 },
+	{ "mmMC_CITF_XTRA_ENABLE", REG_MMIO, 0x96d, &mmMC_CITF_XTRA_ENABLE[0], sizeof(mmMC_CITF_XTRA_ENABLE)/sizeof(mmMC_CITF_XTRA_ENABLE[0]), 0, 0 },
+	{ "mmCC_MC_MAX_CHANNEL", REG_MMIO, 0x96e, &mmCC_MC_MAX_CHANNEL[0], sizeof(mmCC_MC_MAX_CHANNEL)/sizeof(mmCC_MC_MAX_CHANNEL[0]), 0, 0 },
+	{ "mmMC_CG_CONFIG", REG_MMIO, 0x96f, &mmMC_CG_CONFIG[0], sizeof(mmMC_CG_CONFIG)/sizeof(mmMC_CG_CONFIG[0]), 0, 0 },
+	{ "mmMC_CITF_CNTL", REG_MMIO, 0x970, &mmMC_CITF_CNTL[0], sizeof(mmMC_CITF_CNTL)/sizeof(mmMC_CITF_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_VM", REG_MMIO, 0x971, &mmMC_CITF_CREDITS_VM[0], sizeof(mmMC_CITF_CREDITS_VM)/sizeof(mmMC_CITF_CREDITS_VM[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_RD", REG_MMIO, 0x972, &mmMC_CITF_CREDITS_ARB_RD[0], sizeof(mmMC_CITF_CREDITS_ARB_RD)/sizeof(mmMC_CITF_CREDITS_ARB_RD[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_WR", REG_MMIO, 0x973, &mmMC_CITF_CREDITS_ARB_WR[0], sizeof(mmMC_CITF_CREDITS_ARB_WR)/sizeof(mmMC_CITF_CREDITS_ARB_WR[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_CNTL", REG_MMIO, 0x974, &mmMC_CITF_DAGB_CNTL[0], sizeof(mmMC_CITF_DAGB_CNTL)/sizeof(mmMC_CITF_DAGB_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS", REG_MMIO, 0x975, &mmMC_CITF_INT_CREDITS[0], sizeof(mmMC_CITF_INT_CREDITS)/sizeof(mmMC_CITF_INT_CREDITS[0]), 0, 0 },
+	{ "mmMC_CITF_RET_MODE", REG_MMIO, 0x976, &mmMC_CITF_RET_MODE[0], sizeof(mmMC_CITF_RET_MODE)/sizeof(mmMC_CITF_RET_MODE[0]), 0, 0 },
+	{ "mmMC_CITF_DAGB_DLY", REG_MMIO, 0x977, &mmMC_CITF_DAGB_DLY[0], sizeof(mmMC_CITF_DAGB_DLY)/sizeof(mmMC_CITF_DAGB_DLY[0]), 0, 0 },
+	{ "mmMC_RD_GRP_EXT", REG_MMIO, 0x978, &mmMC_RD_GRP_EXT[0], sizeof(mmMC_RD_GRP_EXT)/sizeof(mmMC_RD_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_WR_GRP_EXT", REG_MMIO, 0x979, &mmMC_WR_GRP_EXT[0], sizeof(mmMC_WR_GRP_EXT)/sizeof(mmMC_WR_GRP_EXT[0]), 0, 0 },
+	{ "mmMC_CITF_REMREQ", REG_MMIO, 0x97a, &mmMC_CITF_REMREQ[0], sizeof(mmMC_CITF_REMREQ)/sizeof(mmMC_CITF_REMREQ[0]), 0, 0 },
+	{ "mmMC_WR_TC0", REG_MMIO, 0x97b, &mmMC_WR_TC0[0], sizeof(mmMC_WR_TC0)/sizeof(mmMC_WR_TC0[0]), 0, 0 },
+	{ "mmMC_WR_TC1", REG_MMIO, 0x97c, &mmMC_WR_TC1[0], sizeof(mmMC_WR_TC1)/sizeof(mmMC_WR_TC1[0]), 0, 0 },
+	{ "mmMC_CITF_INT_CREDITS_WR", REG_MMIO, 0x97d, &mmMC_CITF_INT_CREDITS_WR[0], sizeof(mmMC_CITF_INT_CREDITS_WR)/sizeof(mmMC_CITF_INT_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_ARB_RD2", REG_MMIO, 0x97e, &mmMC_CITF_CREDITS_ARB_RD2[0], sizeof(mmMC_CITF_CREDITS_ARB_RD2)/sizeof(mmMC_CITF_CREDITS_ARB_RD2[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_RD_CNTL", REG_MMIO, 0x97f, &mmMC_CITF_WTM_RD_CNTL[0], sizeof(mmMC_CITF_WTM_RD_CNTL)/sizeof(mmMC_CITF_WTM_RD_CNTL[0]), 0, 0 },
+	{ "mmMC_CITF_WTM_WR_CNTL", REG_MMIO, 0x980, &mmMC_CITF_WTM_WR_CNTL[0], sizeof(mmMC_CITF_WTM_WR_CNTL)/sizeof(mmMC_CITF_WTM_WR_CNTL[0]), 0, 0 },
+	{ "mmMC_RD_CB", REG_MMIO, 0x981, &mmMC_RD_CB[0], sizeof(mmMC_RD_CB)/sizeof(mmMC_RD_CB[0]), 0, 0 },
+	{ "mmMC_RD_DB", REG_MMIO, 0x982, &mmMC_RD_DB[0], sizeof(mmMC_RD_DB)/sizeof(mmMC_RD_DB[0]), 0, 0 },
+	{ "mmMC_RD_TC0", REG_MMIO, 0x983, &mmMC_RD_TC0[0], sizeof(mmMC_RD_TC0)/sizeof(mmMC_RD_TC0[0]), 0, 0 },
+	{ "mmMC_RD_TC1", REG_MMIO, 0x984, &mmMC_RD_TC1[0], sizeof(mmMC_RD_TC1)/sizeof(mmMC_RD_TC1[0]), 0, 0 },
+	{ "mmMC_RD_HUB", REG_MMIO, 0x985, &mmMC_RD_HUB[0], sizeof(mmMC_RD_HUB)/sizeof(mmMC_RD_HUB[0]), 0, 0 },
+	{ "mmMC_WR_CB", REG_MMIO, 0x986, &mmMC_WR_CB[0], sizeof(mmMC_WR_CB)/sizeof(mmMC_WR_CB[0]), 0, 0 },
+	{ "mmMC_WR_DB", REG_MMIO, 0x987, &mmMC_WR_DB[0], sizeof(mmMC_WR_DB)/sizeof(mmMC_WR_DB[0]), 0, 0 },
+	{ "mmMC_WR_HUB", REG_MMIO, 0x988, &mmMC_WR_HUB[0], sizeof(mmMC_WR_HUB)/sizeof(mmMC_WR_HUB[0]), 0, 0 },
+	{ "mmMC_CITF_CREDITS_XBAR", REG_MMIO, 0x989, &mmMC_CITF_CREDITS_XBAR[0], sizeof(mmMC_CITF_CREDITS_XBAR)/sizeof(mmMC_CITF_CREDITS_XBAR[0]), 0, 0 },
+	{ "mmMC_RD_GRP_LCL", REG_MMIO, 0x98a, &mmMC_RD_GRP_LCL[0], sizeof(mmMC_RD_GRP_LCL)/sizeof(mmMC_RD_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_WR_GRP_LCL", REG_MMIO, 0x98b, &mmMC_WR_GRP_LCL[0], sizeof(mmMC_WR_GRP_LCL)/sizeof(mmMC_WR_GRP_LCL[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_CNTL2", REG_MMIO, 0x98e, &mmMC_CITF_PERF_MON_CNTL2[0], sizeof(mmMC_CITF_PERF_MON_CNTL2)/sizeof(mmMC_CITF_PERF_MON_CNTL2[0]), 0, 0 },
+	{ "mmMC_CITF_PERF_MON_RSLT2", REG_MMIO, 0x991, &mmMC_CITF_PERF_MON_RSLT2[0], sizeof(mmMC_CITF_PERF_MON_RSLT2)/sizeof(mmMC_CITF_PERF_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_RD_CG", REG_MMIO, 0x992, &mmMC_CITF_MISC_RD_CG[0], sizeof(mmMC_CITF_MISC_RD_CG)/sizeof(mmMC_CITF_MISC_RD_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_WR_CG", REG_MMIO, 0x993, &mmMC_CITF_MISC_WR_CG[0], sizeof(mmMC_CITF_MISC_WR_CG)/sizeof(mmMC_CITF_MISC_WR_CG[0]), 0, 0 },
+	{ "mmMC_CITF_MISC_VM_CG", REG_MMIO, 0x994, &mmMC_CITF_MISC_VM_CG[0], sizeof(mmMC_CITF_MISC_VM_CG)/sizeof(mmMC_CITF_MISC_VM_CG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_DEBUG", REG_MMIO, 0x998, &mmMC_VM_MD_L1_TLB0_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB0_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB0_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_DEBUG", REG_MMIO, 0x999, &mmMC_VM_MD_L1_TLB1_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB1_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB1_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_DEBUG", REG_MMIO, 0x99a, &mmMC_VM_MD_L1_TLB2_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB2_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB2_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB0_STATUS", REG_MMIO, 0x99b, &mmMC_VM_MD_L1_TLB0_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB0_STATUS)/sizeof(mmMC_VM_MD_L1_TLB0_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB1_STATUS", REG_MMIO, 0x99c, &mmMC_VM_MD_L1_TLB1_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB1_STATUS)/sizeof(mmMC_VM_MD_L1_TLB1_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB2_STATUS", REG_MMIO, 0x99d, &mmMC_VM_MD_L1_TLB2_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB2_STATUS)/sizeof(mmMC_VM_MD_L1_TLB2_STATUS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L2ARBITER_L2_CREDITS", REG_MMIO, 0x9a4, &mmMC_VM_MD_L2ARBITER_L2_CREDITS[0], sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS)/sizeof(mmMC_VM_MD_L2ARBITER_L2_CREDITS[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_DEBUG", REG_MMIO, 0x9a7, &mmMC_VM_MD_L1_TLB3_DEBUG[0], sizeof(mmMC_VM_MD_L1_TLB3_DEBUG)/sizeof(mmMC_VM_MD_L1_TLB3_DEBUG[0]), 0, 0 },
+	{ "mmMC_VM_MD_L1_TLB3_STATUS", REG_MMIO, 0x9a8, &mmMC_VM_MD_L1_TLB3_STATUS[0], sizeof(mmMC_VM_MD_L1_TLB3_STATUS)/sizeof(mmMC_VM_MD_L1_TLB3_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_ATOMIC", REG_MMIO, 0x9be, &mmMC_ARB_ATOMIC[0], sizeof(mmMC_ARB_ATOMIC)/sizeof(mmMC_ARB_ATOMIC[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_CNTL", REG_MMIO, 0x9bf, &mmMC_ARB_AGE_CNTL[0], sizeof(mmMC_ARB_AGE_CNTL)/sizeof(mmMC_ARB_AGE_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS2", REG_MMIO, 0x9c0, &mmMC_ARB_RET_CREDITS2[0], sizeof(mmMC_ARB_RET_CREDITS2)/sizeof(mmMC_ARB_RET_CREDITS2[0]), 0, 0 },
+	{ "mmMC_ARB_FED_CNTL", REG_MMIO, 0x9c1, &mmMC_ARB_FED_CNTL[0], sizeof(mmMC_ARB_FED_CNTL)/sizeof(mmMC_ARB_FED_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_STATUS", REG_MMIO, 0x9c2, &mmMC_ARB_GECC2_STATUS[0], sizeof(mmMC_ARB_GECC2_STATUS)/sizeof(mmMC_ARB_GECC2_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_MISC", REG_MMIO, 0x9c3, &mmMC_ARB_GECC2_MISC[0], sizeof(mmMC_ARB_GECC2_MISC)/sizeof(mmMC_ARB_GECC2_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG", REG_MMIO, 0x9c4, &mmMC_ARB_GECC2_DEBUG[0], sizeof(mmMC_ARB_GECC2_DEBUG)/sizeof(mmMC_ARB_GECC2_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_DEBUG2", REG_MMIO, 0x9c5, &mmMC_ARB_GECC2_DEBUG2[0], sizeof(mmMC_ARB_GECC2_DEBUG2)/sizeof(mmMC_ARB_GECC2_DEBUG2[0]), 0, 0 },
+	{ "mmMC_ARB_PERF_CID", REG_MMIO, 0x9c6, &mmMC_ARB_PERF_CID[0], sizeof(mmMC_ARB_PERF_CID)/sizeof(mmMC_ARB_PERF_CID[0]), 0, 0 },
+	{ "mmMC_ARB_SNOOP", REG_MMIO, 0x9c7, &mmMC_ARB_SNOOP[0], sizeof(mmMC_ARB_SNOOP)/sizeof(mmMC_ARB_SNOOP[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB", REG_MMIO, 0x9c8, &mmMC_ARB_GRUB[0], sizeof(mmMC_ARB_GRUB)/sizeof(mmMC_ARB_GRUB[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2", REG_MMIO, 0x9c9, &mmMC_ARB_GECC2[0], sizeof(mmMC_ARB_GECC2)/sizeof(mmMC_ARB_GECC2[0]), 0, 0 },
+	{ "mmMC_ARB_GECC2_CLI", REG_MMIO, 0x9ca, &mmMC_ARB_GECC2_CLI[0], sizeof(mmMC_ARB_GECC2_CLI)/sizeof(mmMC_ARB_GECC2_CLI[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_SWIZ0", REG_MMIO, 0x9cb, &mmMC_ARB_ADDR_SWIZ0[0], sizeof(mmMC_ARB_ADDR_SWIZ0)/sizeof(mmMC_ARB_ADDR_SWIZ0[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_SWIZ1", REG_MMIO, 0x9cc, &mmMC_ARB_ADDR_SWIZ1[0], sizeof(mmMC_ARB_ADDR_SWIZ1)/sizeof(mmMC_ARB_ADDR_SWIZ1[0]), 0, 0 },
+	{ "mmMC_ARB_MISC3", REG_MMIO, 0x9cd, &mmMC_ARB_MISC3[0], sizeof(mmMC_ARB_MISC3)/sizeof(mmMC_ARB_MISC3[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PROMOTE", REG_MMIO, 0x9ce, &mmMC_ARB_GRUB_PROMOTE[0], sizeof(mmMC_ARB_GRUB_PROMOTE)/sizeof(mmMC_ARB_GRUB_PROMOTE[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DATA", REG_MMIO, 0x9cf, &mmMC_ARB_RTT_DATA[0], sizeof(mmMC_ARB_RTT_DATA)/sizeof(mmMC_ARB_RTT_DATA[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL0", REG_MMIO, 0x9d0, &mmMC_ARB_RTT_CNTL0[0], sizeof(mmMC_ARB_RTT_CNTL0)/sizeof(mmMC_ARB_RTT_CNTL0[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL1", REG_MMIO, 0x9d1, &mmMC_ARB_RTT_CNTL1[0], sizeof(mmMC_ARB_RTT_CNTL1)/sizeof(mmMC_ARB_RTT_CNTL1[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_CNTL2", REG_MMIO, 0x9d2, &mmMC_ARB_RTT_CNTL2[0], sizeof(mmMC_ARB_RTT_CNTL2)/sizeof(mmMC_ARB_RTT_CNTL2[0]), 0, 0 },
+	{ "mmMC_ARB_RTT_DEBUG", REG_MMIO, 0x9d3, &mmMC_ARB_RTT_DEBUG[0], sizeof(mmMC_ARB_RTT_DEBUG)/sizeof(mmMC_ARB_RTT_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_CAC_CNTL", REG_MMIO, 0x9d4, &mmMC_ARB_CAC_CNTL[0], sizeof(mmMC_ARB_CAC_CNTL)/sizeof(mmMC_ARB_CAC_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_MISC2", REG_MMIO, 0x9d5, &mmMC_ARB_MISC2[0], sizeof(mmMC_ARB_MISC2)/sizeof(mmMC_ARB_MISC2[0]), 0, 0 },
+	{ "mmMC_ARB_MISC", REG_MMIO, 0x9d6, &mmMC_ARB_MISC[0], sizeof(mmMC_ARB_MISC)/sizeof(mmMC_ARB_MISC[0]), 0, 0 },
+	{ "mmMC_ARB_BANKMAP", REG_MMIO, 0x9d7, &mmMC_ARB_BANKMAP[0], sizeof(mmMC_ARB_BANKMAP)/sizeof(mmMC_ARB_BANKMAP[0]), 0, 0 },
+	{ "mmMC_ARB_RAMCFG", REG_MMIO, 0x9d8, &mmMC_ARB_RAMCFG[0], sizeof(mmMC_ARB_RAMCFG)/sizeof(mmMC_ARB_RAMCFG[0]), 0, 0 },
+	{ "mmMC_ARB_POP", REG_MMIO, 0x9d9, &mmMC_ARB_POP[0], sizeof(mmMC_ARB_POP)/sizeof(mmMC_ARB_POP[0]), 0, 0 },
+	{ "mmMC_ARB_MINCLKS", REG_MMIO, 0x9da, &mmMC_ARB_MINCLKS[0], sizeof(mmMC_ARB_MINCLKS)/sizeof(mmMC_ARB_MINCLKS[0]), 0, 0 },
+	{ "mmMC_ARB_SQM_CNTL", REG_MMIO, 0x9db, &mmMC_ARB_SQM_CNTL[0], sizeof(mmMC_ARB_SQM_CNTL)/sizeof(mmMC_ARB_SQM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_ADDR_HASH", REG_MMIO, 0x9dc, &mmMC_ARB_ADDR_HASH[0], sizeof(mmMC_ARB_ADDR_HASH)/sizeof(mmMC_ARB_ADDR_HASH[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING", REG_MMIO, 0x9dd, &mmMC_ARB_DRAM_TIMING[0], sizeof(mmMC_ARB_DRAM_TIMING)/sizeof(mmMC_ARB_DRAM_TIMING[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2", REG_MMIO, 0x9de, &mmMC_ARB_DRAM_TIMING2[0], sizeof(mmMC_ARB_DRAM_TIMING2)/sizeof(mmMC_ARB_DRAM_TIMING2[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_RD", REG_MMIO, 0x9df, &mmMC_ARB_WTM_CNTL_RD[0], sizeof(mmMC_ARB_WTM_CNTL_RD)/sizeof(mmMC_ARB_WTM_CNTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_CNTL_WR", REG_MMIO, 0x9e0, &mmMC_ARB_WTM_CNTL_WR[0], sizeof(mmMC_ARB_WTM_CNTL_WR)/sizeof(mmMC_ARB_WTM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_RD", REG_MMIO, 0x9e1, &mmMC_ARB_WTM_GRPWT_RD[0], sizeof(mmMC_ARB_WTM_GRPWT_RD)/sizeof(mmMC_ARB_WTM_GRPWT_RD[0]), 0, 0 },
+	{ "mmMC_ARB_WTM_GRPWT_WR", REG_MMIO, 0x9e2, &mmMC_ARB_WTM_GRPWT_WR[0], sizeof(mmMC_ARB_WTM_GRPWT_WR)/sizeof(mmMC_ARB_WTM_GRPWT_WR[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_RD", REG_MMIO, 0x9e3, &mmMC_ARB_TM_CNTL_RD[0], sizeof(mmMC_ARB_TM_CNTL_RD)/sizeof(mmMC_ARB_TM_CNTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_TM_CNTL_WR", REG_MMIO, 0x9e4, &mmMC_ARB_TM_CNTL_WR[0], sizeof(mmMC_ARB_TM_CNTL_WR)/sizeof(mmMC_ARB_TM_CNTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_RD", REG_MMIO, 0x9e5, &mmMC_ARB_LAZY0_RD[0], sizeof(mmMC_ARB_LAZY0_RD)/sizeof(mmMC_ARB_LAZY0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY0_WR", REG_MMIO, 0x9e6, &mmMC_ARB_LAZY0_WR[0], sizeof(mmMC_ARB_LAZY0_WR)/sizeof(mmMC_ARB_LAZY0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_RD", REG_MMIO, 0x9e7, &mmMC_ARB_LAZY1_RD[0], sizeof(mmMC_ARB_LAZY1_RD)/sizeof(mmMC_ARB_LAZY1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LAZY1_WR", REG_MMIO, 0x9e8, &mmMC_ARB_LAZY1_WR[0], sizeof(mmMC_ARB_LAZY1_WR)/sizeof(mmMC_ARB_LAZY1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_RD", REG_MMIO, 0x9e9, &mmMC_ARB_AGE_RD[0], sizeof(mmMC_ARB_AGE_RD)/sizeof(mmMC_ARB_AGE_RD[0]), 0, 0 },
+	{ "mmMC_ARB_AGE_WR", REG_MMIO, 0x9ea, &mmMC_ARB_AGE_WR[0], sizeof(mmMC_ARB_AGE_WR)/sizeof(mmMC_ARB_AGE_WR[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_CNTL", REG_MMIO, 0x9eb, &mmMC_ARB_RFSH_CNTL[0], sizeof(mmMC_ARB_RFSH_CNTL)/sizeof(mmMC_ARB_RFSH_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_RFSH_RATE", REG_MMIO, 0x9ec, &mmMC_ARB_RFSH_RATE[0], sizeof(mmMC_ARB_RFSH_RATE)/sizeof(mmMC_ARB_RFSH_RATE[0]), 0, 0 },
+	{ "mmMC_ARB_PM_CNTL", REG_MMIO, 0x9ed, &mmMC_ARB_PM_CNTL[0], sizeof(mmMC_ARB_PM_CNTL)/sizeof(mmMC_ARB_PM_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_RD_CNTL", REG_MMIO, 0x9ee, &mmMC_ARB_GDEC_RD_CNTL[0], sizeof(mmMC_ARB_GDEC_RD_CNTL)/sizeof(mmMC_ARB_GDEC_RD_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_GDEC_WR_CNTL", REG_MMIO, 0x9ef, &mmMC_ARB_GDEC_WR_CNTL[0], sizeof(mmMC_ARB_GDEC_WR_CNTL)/sizeof(mmMC_ARB_GDEC_WR_CNTL[0]), 0, 0 },
+	{ "mmMC_ARB_LM_RD", REG_MMIO, 0x9f0, &mmMC_ARB_LM_RD[0], sizeof(mmMC_ARB_LM_RD)/sizeof(mmMC_ARB_LM_RD[0]), 0, 0 },
+	{ "mmMC_ARB_LM_WR", REG_MMIO, 0x9f1, &mmMC_ARB_LM_WR[0], sizeof(mmMC_ARB_LM_WR)/sizeof(mmMC_ARB_LM_WR[0]), 0, 0 },
+	{ "mmMC_ARB_REMREQ", REG_MMIO, 0x9f2, &mmMC_ARB_REMREQ[0], sizeof(mmMC_ARB_REMREQ)/sizeof(mmMC_ARB_REMREQ[0]), 0, 0 },
+	{ "mmMC_ARB_REPLAY", REG_MMIO, 0x9f3, &mmMC_ARB_REPLAY[0], sizeof(mmMC_ARB_REPLAY)/sizeof(mmMC_ARB_REPLAY[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_RD", REG_MMIO, 0x9f4, &mmMC_ARB_RET_CREDITS_RD[0], sizeof(mmMC_ARB_RET_CREDITS_RD)/sizeof(mmMC_ARB_RET_CREDITS_RD[0]), 0, 0 },
+	{ "mmMC_ARB_RET_CREDITS_WR", REG_MMIO, 0x9f5, &mmMC_ARB_RET_CREDITS_WR[0], sizeof(mmMC_ARB_RET_CREDITS_WR)/sizeof(mmMC_ARB_RET_CREDITS_WR[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_CID", REG_MMIO, 0x9f6, &mmMC_ARB_MAX_LAT_CID[0], sizeof(mmMC_ARB_MAX_LAT_CID)/sizeof(mmMC_ARB_MAX_LAT_CID[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_RSLT0", REG_MMIO, 0x9f7, &mmMC_ARB_MAX_LAT_RSLT0[0], sizeof(mmMC_ARB_MAX_LAT_RSLT0)/sizeof(mmMC_ARB_MAX_LAT_RSLT0[0]), 0, 0 },
+	{ "mmMC_ARB_MAX_LAT_RSLT1", REG_MMIO, 0x9f8, &mmMC_ARB_MAX_LAT_RSLT1[0], sizeof(mmMC_ARB_MAX_LAT_RSLT1)/sizeof(mmMC_ARB_MAX_LAT_RSLT1[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_REALTIME_RD", REG_MMIO, 0x9f9, &mmMC_ARB_GRUB_REALTIME_RD[0], sizeof(mmMC_ARB_GRUB_REALTIME_RD)/sizeof(mmMC_ARB_GRUB_REALTIME_RD[0]), 0, 0 },
+	{ "mmMC_ARB_CG", REG_MMIO, 0x9fa, &mmMC_ARB_CG[0], sizeof(mmMC_ARB_CG)/sizeof(mmMC_ARB_CG[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_REALTIME_WR", REG_MMIO, 0x9fb, &mmMC_ARB_GRUB_REALTIME_WR[0], sizeof(mmMC_ARB_GRUB_REALTIME_WR)/sizeof(mmMC_ARB_GRUB_REALTIME_WR[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING_1", REG_MMIO, 0x9fc, &mmMC_ARB_DRAM_TIMING_1[0], sizeof(mmMC_ARB_DRAM_TIMING_1)/sizeof(mmMC_ARB_DRAM_TIMING_1[0]), 0, 0 },
+	{ "mmMC_ARB_BUSY_STATUS", REG_MMIO, 0x9fd, &mmMC_ARB_BUSY_STATUS[0], sizeof(mmMC_ARB_BUSY_STATUS)/sizeof(mmMC_ARB_BUSY_STATUS[0]), 0, 0 },
+	{ "mmMC_ARB_DRAM_TIMING2_1", REG_MMIO, 0x9ff, &mmMC_ARB_DRAM_TIMING2_1[0], sizeof(mmMC_ARB_DRAM_TIMING2_1)/sizeof(mmMC_ARB_DRAM_TIMING2_1[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB2", REG_MMIO, 0xa01, &mmMC_ARB_GRUB2[0], sizeof(mmMC_ARB_GRUB2)/sizeof(mmMC_ARB_GRUB2[0]), 0, 0 },
+	{ "mmMC_ARB_BURST_TIME", REG_MMIO, 0xa02, &mmMC_ARB_BURST_TIME[0], sizeof(mmMC_ARB_BURST_TIME)/sizeof(mmMC_ARB_BURST_TIME[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS0_BASE", REG_MMIO, 0xa05, &mmMC_FUS_DRAM0_CS0_BASE[0], sizeof(mmMC_FUS_DRAM0_CS0_BASE)/sizeof(mmMC_FUS_DRAM0_CS0_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS0_BASE", REG_MMIO, 0xa06, &mmMC_FUS_DRAM1_CS0_BASE[0], sizeof(mmMC_FUS_DRAM1_CS0_BASE)/sizeof(mmMC_FUS_DRAM1_CS0_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS1_BASE", REG_MMIO, 0xa07, &mmMC_FUS_DRAM0_CS1_BASE[0], sizeof(mmMC_FUS_DRAM0_CS1_BASE)/sizeof(mmMC_FUS_DRAM0_CS1_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS1_BASE", REG_MMIO, 0xa08, &mmMC_FUS_DRAM1_CS1_BASE[0], sizeof(mmMC_FUS_DRAM1_CS1_BASE)/sizeof(mmMC_FUS_DRAM1_CS1_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS2_BASE", REG_MMIO, 0xa09, &mmMC_FUS_DRAM0_CS2_BASE[0], sizeof(mmMC_FUS_DRAM0_CS2_BASE)/sizeof(mmMC_FUS_DRAM0_CS2_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS2_BASE", REG_MMIO, 0xa0a, &mmMC_FUS_DRAM1_CS2_BASE[0], sizeof(mmMC_FUS_DRAM1_CS2_BASE)/sizeof(mmMC_FUS_DRAM1_CS2_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS3_BASE", REG_MMIO, 0xa0b, &mmMC_FUS_DRAM0_CS3_BASE[0], sizeof(mmMC_FUS_DRAM0_CS3_BASE)/sizeof(mmMC_FUS_DRAM0_CS3_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS3_BASE", REG_MMIO, 0xa0c, &mmMC_FUS_DRAM1_CS3_BASE[0], sizeof(mmMC_FUS_DRAM1_CS3_BASE)/sizeof(mmMC_FUS_DRAM1_CS3_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS01_MASK", REG_MMIO, 0xa0d, NULL, 0, 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS01_MASK", REG_MMIO, 0xa0e, NULL, 0, 0, 0 },
+	{ "mmMC_FUS_DRAM0_CS23_MASK", REG_MMIO, 0xa0f, NULL, 0, 0, 0 },
+	{ "mmMC_FUS_DRAM1_CS23_MASK", REG_MMIO, 0xa10, NULL, 0, 0, 0 },
+	{ "mmMC_FUS_DRAM0_BANK_ADDR_MAPPING", REG_MMIO, 0xa11, &mmMC_FUS_DRAM0_BANK_ADDR_MAPPING[0], sizeof(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING)/sizeof(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_BANK_ADDR_MAPPING", REG_MMIO, 0xa12, &mmMC_FUS_DRAM1_BANK_ADDR_MAPPING[0], sizeof(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING)/sizeof(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CTL_BASE", REG_MMIO, 0xa13, &mmMC_FUS_DRAM0_CTL_BASE[0], sizeof(mmMC_FUS_DRAM0_CTL_BASE)/sizeof(mmMC_FUS_DRAM0_CTL_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CTL_BASE", REG_MMIO, 0xa14, &mmMC_FUS_DRAM1_CTL_BASE[0], sizeof(mmMC_FUS_DRAM1_CTL_BASE)/sizeof(mmMC_FUS_DRAM1_CTL_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM0_CTL_LIMIT", REG_MMIO, 0xa15, &mmMC_FUS_DRAM0_CTL_LIMIT[0], sizeof(mmMC_FUS_DRAM0_CTL_LIMIT)/sizeof(mmMC_FUS_DRAM0_CTL_LIMIT[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM1_CTL_LIMIT", REG_MMIO, 0xa16, &mmMC_FUS_DRAM1_CTL_LIMIT[0], sizeof(mmMC_FUS_DRAM1_CTL_LIMIT)/sizeof(mmMC_FUS_DRAM1_CTL_LIMIT[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_CTL_HIGH_01", REG_MMIO, 0xa17, &mmMC_FUS_DRAM_CTL_HIGH_01[0], sizeof(mmMC_FUS_DRAM_CTL_HIGH_01)/sizeof(mmMC_FUS_DRAM_CTL_HIGH_01[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_CTL_HIGH_23", REG_MMIO, 0xa18, &mmMC_FUS_DRAM_CTL_HIGH_23[0], sizeof(mmMC_FUS_DRAM_CTL_HIGH_23)/sizeof(mmMC_FUS_DRAM_CTL_HIGH_23[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_MODE", REG_MMIO, 0xa19, &mmMC_FUS_DRAM_MODE[0], sizeof(mmMC_FUS_DRAM_MODE)/sizeof(mmMC_FUS_DRAM_MODE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_APER_BASE", REG_MMIO, 0xa1a, &mmMC_FUS_DRAM_APER_BASE[0], sizeof(mmMC_FUS_DRAM_APER_BASE)/sizeof(mmMC_FUS_DRAM_APER_BASE[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_APER_TOP", REG_MMIO, 0xa1b, &mmMC_FUS_DRAM_APER_TOP[0], sizeof(mmMC_FUS_DRAM_APER_TOP)/sizeof(mmMC_FUS_DRAM_APER_TOP[0]), 0, 0 },
+	{ "mmMC_FUS_DRAM_APER_DEF", REG_MMIO, 0xa1e, &mmMC_FUS_DRAM_APER_DEF[0], sizeof(mmMC_FUS_DRAM_APER_DEF)/sizeof(mmMC_FUS_DRAM_APER_DEF[0]), 0, 0 },
+	{ "mmMC_FUS_ARB_GARLIC_ISOC_PRI", REG_MMIO, 0xa1f, &mmMC_FUS_ARB_GARLIC_ISOC_PRI[0], sizeof(mmMC_FUS_ARB_GARLIC_ISOC_PRI)/sizeof(mmMC_FUS_ARB_GARLIC_ISOC_PRI[0]), 0, 0 },
+	{ "mmMC_FUS_ARB_GARLIC_CNTL", REG_MMIO, 0xa20, &mmMC_FUS_ARB_GARLIC_CNTL[0], sizeof(mmMC_FUS_ARB_GARLIC_CNTL)/sizeof(mmMC_FUS_ARB_GARLIC_CNTL[0]), 0, 0 },
+	{ "mmMC_FUS_ARB_GARLIC_WR_PRI", REG_MMIO, 0xa21, &mmMC_FUS_ARB_GARLIC_WR_PRI[0], sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI)/sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI[0]), 0, 0 },
+	{ "mmMC_FUS_ARB_GARLIC_WR_PRI2", REG_MMIO, 0xa22, &mmMC_FUS_ARB_GARLIC_WR_PRI2[0], sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI2)/sizeof(mmMC_FUS_ARB_GARLIC_WR_PRI2[0]), 0, 0 },
+	{ "mmMC_CG_DATAPORT", REG_MMIO, 0xa32, &mmMC_CG_DATAPORT[0], sizeof(mmMC_CG_DATAPORT)/sizeof(mmMC_CG_DATAPORT[0]), 0, 0 },
+	{ "mmMC_GRUB_PROBE_MAP", REG_MMIO, 0xa33, &mmMC_GRUB_PROBE_MAP[0], sizeof(mmMC_GRUB_PROBE_MAP)/sizeof(mmMC_GRUB_PROBE_MAP[0]), 0, 0 },
+	{ "mmMC_GRUB_POST_PROBE_DELAY", REG_MMIO, 0xa34, &mmMC_GRUB_POST_PROBE_DELAY[0], sizeof(mmMC_GRUB_POST_PROBE_DELAY)/sizeof(mmMC_GRUB_POST_PROBE_DELAY[0]), 0, 0 },
+	{ "mmMC_GRUB_PROBE_CREDITS", REG_MMIO, 0xa35, &mmMC_GRUB_PROBE_CREDITS[0], sizeof(mmMC_GRUB_PROBE_CREDITS)/sizeof(mmMC_GRUB_PROBE_CREDITS[0]), 0, 0 },
+	{ "mmMC_GRUB_FEATURES", REG_MMIO, 0xa36, &mmMC_GRUB_FEATURES[0], sizeof(mmMC_GRUB_FEATURES)/sizeof(mmMC_GRUB_FEATURES[0]), 0, 0 },
+	{ "mmMC_GRUB_TX_CREDITS", REG_MMIO, 0xa37, &mmMC_GRUB_TX_CREDITS[0], sizeof(mmMC_GRUB_TX_CREDITS)/sizeof(mmMC_GRUB_TX_CREDITS[0]), 0, 0 },
+	{ "mmMC_GRUB_TCB_INDEX", REG_MMIO, 0xa38, &mmMC_GRUB_TCB_INDEX[0], sizeof(mmMC_GRUB_TCB_INDEX)/sizeof(mmMC_GRUB_TCB_INDEX[0]), 0, 0 },
+	{ "mmMC_GRUB_TCB_DATA_LO", REG_MMIO, 0xa39, &mmMC_GRUB_TCB_DATA_LO[0], sizeof(mmMC_GRUB_TCB_DATA_LO)/sizeof(mmMC_GRUB_TCB_DATA_LO[0]), 0, 0 },
+	{ "mmMC_GRUB_TCB_DATA_HI", REG_MMIO, 0xa3a, &mmMC_GRUB_TCB_DATA_HI[0], sizeof(mmMC_GRUB_TCB_DATA_HI)/sizeof(mmMC_GRUB_TCB_DATA_HI[0]), 0, 0 },
+	{ "mmMC_XBAR_ADDR_DEC", REG_MMIO, 0xc80, &mmMC_XBAR_ADDR_DEC[0], sizeof(mmMC_XBAR_ADDR_DEC)/sizeof(mmMC_XBAR_ADDR_DEC[0]), 0, 0 },
+	{ "mmMC_XBAR_REMOTE", REG_MMIO, 0xc81, &mmMC_XBAR_REMOTE[0], sizeof(mmMC_XBAR_REMOTE)/sizeof(mmMC_XBAR_REMOTE[0]), 0, 0 },
+	{ "mmMC_XBAR_WRREQ_CREDIT", REG_MMIO, 0xc82, &mmMC_XBAR_WRREQ_CREDIT[0], sizeof(mmMC_XBAR_WRREQ_CREDIT)/sizeof(mmMC_XBAR_WRREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_CREDIT", REG_MMIO, 0xc83, &mmMC_XBAR_RDREQ_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_CREDIT)/sizeof(mmMC_XBAR_RDREQ_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_RDREQ_PRI_CREDIT", REG_MMIO, 0xc84, &mmMC_XBAR_RDREQ_PRI_CREDIT[0], sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT)/sizeof(mmMC_XBAR_RDREQ_PRI_CREDIT[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT1", REG_MMIO, 0xc85, &mmMC_XBAR_WRRET_CREDIT1[0], sizeof(mmMC_XBAR_WRRET_CREDIT1)/sizeof(mmMC_XBAR_WRRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_WRRET_CREDIT2", REG_MMIO, 0xc86, &mmMC_XBAR_WRRET_CREDIT2[0], sizeof(mmMC_XBAR_WRRET_CREDIT2)/sizeof(mmMC_XBAR_WRRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT1", REG_MMIO, 0xc87, &mmMC_XBAR_RDRET_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_CREDIT1)/sizeof(mmMC_XBAR_RDRET_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_CREDIT2", REG_MMIO, 0xc88, &mmMC_XBAR_RDRET_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_CREDIT2)/sizeof(mmMC_XBAR_RDRET_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT1", REG_MMIO, 0xc89, &mmMC_XBAR_RDRET_PRI_CREDIT1[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT1[0]), 0, 0 },
+	{ "mmMC_XBAR_RDRET_PRI_CREDIT2", REG_MMIO, 0xc8a, &mmMC_XBAR_RDRET_PRI_CREDIT2[0], sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2)/sizeof(mmMC_XBAR_RDRET_PRI_CREDIT2[0]), 0, 0 },
+	{ "mmMC_XBAR_CHTRIREMAP", REG_MMIO, 0xc8b, &mmMC_XBAR_CHTRIREMAP[0], sizeof(mmMC_XBAR_CHTRIREMAP)/sizeof(mmMC_XBAR_CHTRIREMAP[0]), 0, 0 },
+	{ "mmMC_XBAR_TWOCHAN", REG_MMIO, 0xc8c, &mmMC_XBAR_TWOCHAN[0], sizeof(mmMC_XBAR_TWOCHAN)/sizeof(mmMC_XBAR_TWOCHAN[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB", REG_MMIO, 0xc8d, &mmMC_XBAR_ARB[0], sizeof(mmMC_XBAR_ARB)/sizeof(mmMC_XBAR_ARB[0]), 0, 0 },
+	{ "mmMC_XBAR_ARB_MAX_BURST", REG_MMIO, 0xc8e, &mmMC_XBAR_ARB_MAX_BURST[0], sizeof(mmMC_XBAR_ARB_MAX_BURST)/sizeof(mmMC_XBAR_ARB_MAX_BURST[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_CNTL0", REG_MMIO, 0xc8f, &mmMC_XBAR_FIFO_MON_CNTL0[0], sizeof(mmMC_XBAR_FIFO_MON_CNTL0)/sizeof(mmMC_XBAR_FIFO_MON_CNTL0[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_CNTL1", REG_MMIO, 0xc90, &mmMC_XBAR_FIFO_MON_CNTL1[0], sizeof(mmMC_XBAR_FIFO_MON_CNTL1)/sizeof(mmMC_XBAR_FIFO_MON_CNTL1[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_CNTL2", REG_MMIO, 0xc91, &mmMC_XBAR_FIFO_MON_CNTL2[0], sizeof(mmMC_XBAR_FIFO_MON_CNTL2)/sizeof(mmMC_XBAR_FIFO_MON_CNTL2[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_RSLT0", REG_MMIO, 0xc92, &mmMC_XBAR_FIFO_MON_RSLT0[0], sizeof(mmMC_XBAR_FIFO_MON_RSLT0)/sizeof(mmMC_XBAR_FIFO_MON_RSLT0[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_RSLT1", REG_MMIO, 0xc93, &mmMC_XBAR_FIFO_MON_RSLT1[0], sizeof(mmMC_XBAR_FIFO_MON_RSLT1)/sizeof(mmMC_XBAR_FIFO_MON_RSLT1[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_RSLT2", REG_MMIO, 0xc94, &mmMC_XBAR_FIFO_MON_RSLT2[0], sizeof(mmMC_XBAR_FIFO_MON_RSLT2)/sizeof(mmMC_XBAR_FIFO_MON_RSLT2[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_RSLT3", REG_MMIO, 0xc95, &mmMC_XBAR_FIFO_MON_RSLT3[0], sizeof(mmMC_XBAR_FIFO_MON_RSLT3)/sizeof(mmMC_XBAR_FIFO_MON_RSLT3[0]), 0, 0 },
+	{ "mmMC_XBAR_FIFO_MON_MAX_THSH", REG_MMIO, 0xc96, &mmMC_XBAR_FIFO_MON_MAX_THSH[0], sizeof(mmMC_XBAR_FIFO_MON_MAX_THSH)/sizeof(mmMC_XBAR_FIFO_MON_MAX_THSH[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE0", REG_MMIO, 0xc97, &mmMC_XBAR_SPARE0[0], sizeof(mmMC_XBAR_SPARE0)/sizeof(mmMC_XBAR_SPARE0[0]), 0, 0 },
+	{ "mmMC_XBAR_SPARE1", REG_MMIO, 0xc98, &mmMC_XBAR_SPARE1[0], sizeof(mmMC_XBAR_SPARE1)/sizeof(mmMC_XBAR_SPARE1[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_LOW_ADDR", REG_MMIO, 0xcc0, &mmATC_VM_APERTURE0_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE0_LOW_ADDR)/sizeof(mmATC_VM_APERTURE0_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_LOW_ADDR", REG_MMIO, 0xcc1, &mmATC_VM_APERTURE1_LOW_ADDR[0], sizeof(mmATC_VM_APERTURE1_LOW_ADDR)/sizeof(mmATC_VM_APERTURE1_LOW_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_HIGH_ADDR", REG_MMIO, 0xcc2, &mmATC_VM_APERTURE0_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE0_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE0_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_HIGH_ADDR", REG_MMIO, 0xcc3, &mmATC_VM_APERTURE1_HIGH_ADDR[0], sizeof(mmATC_VM_APERTURE1_HIGH_ADDR)/sizeof(mmATC_VM_APERTURE1_HIGH_ADDR[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL", REG_MMIO, 0xcc4, &mmATC_VM_APERTURE0_CNTL[0], sizeof(mmATC_VM_APERTURE0_CNTL)/sizeof(mmATC_VM_APERTURE0_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL", REG_MMIO, 0xcc5, &mmATC_VM_APERTURE1_CNTL[0], sizeof(mmATC_VM_APERTURE1_CNTL)/sizeof(mmATC_VM_APERTURE1_CNTL[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE0_CNTL2", REG_MMIO, 0xcc6, &mmATC_VM_APERTURE0_CNTL2[0], sizeof(mmATC_VM_APERTURE0_CNTL2)/sizeof(mmATC_VM_APERTURE0_CNTL2[0]), 0, 0 },
+	{ "mmATC_VM_APERTURE1_CNTL2", REG_MMIO, 0xcc7, &mmATC_VM_APERTURE1_CNTL2[0], sizeof(mmATC_VM_APERTURE1_CNTL2)/sizeof(mmATC_VM_APERTURE1_CNTL2[0]), 0, 0 },
+	{ "mmATC_ATS_CNTL", REG_MMIO, 0xcc9, &mmATC_ATS_CNTL[0], sizeof(mmATC_ATS_CNTL)/sizeof(mmATC_ATS_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_DEBUG", REG_MMIO, 0xcca, &mmATC_ATS_DEBUG[0], sizeof(mmATC_ATS_DEBUG)/sizeof(mmATC_ATS_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_DEBUG", REG_MMIO, 0xccb, &mmATC_ATS_FAULT_DEBUG[0], sizeof(mmATC_ATS_FAULT_DEBUG)/sizeof(mmATC_ATS_FAULT_DEBUG[0]), 0, 0 },
+	{ "mmATC_ATS_STATUS", REG_MMIO, 0xccc, &mmATC_ATS_STATUS[0], sizeof(mmATC_ATS_STATUS)/sizeof(mmATC_ATS_STATUS[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_CNTL", REG_MMIO, 0xccd, &mmATC_ATS_FAULT_CNTL[0], sizeof(mmATC_ATS_FAULT_CNTL)/sizeof(mmATC_ATS_FAULT_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_INFO", REG_MMIO, 0xcce, &mmATC_ATS_FAULT_STATUS_INFO[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO)/sizeof(mmATC_ATS_FAULT_STATUS_INFO[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_ADDR", REG_MMIO, 0xccf, &mmATC_ATS_FAULT_STATUS_ADDR[0], sizeof(mmATC_ATS_FAULT_STATUS_ADDR)/sizeof(mmATC_ATS_FAULT_STATUS_ADDR[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_LOW", REG_MMIO, 0xcd0, &mmATC_ATS_DEFAULT_PAGE_LOW[0], sizeof(mmATC_ATS_DEFAULT_PAGE_LOW)/sizeof(mmATC_ATS_DEFAULT_PAGE_LOW[0]), 0, 0 },
+	{ "mmATC_ATS_DEFAULT_PAGE_CNTL", REG_MMIO, 0xcd1, &mmATC_ATS_DEFAULT_PAGE_CNTL[0], sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL)/sizeof(mmATC_ATS_DEFAULT_PAGE_CNTL[0]), 0, 0 },
+	{ "mmATC_ATS_FAULT_STATUS_INFO2", REG_MMIO, 0xcd2, &mmATC_ATS_FAULT_STATUS_INFO2[0], sizeof(mmATC_ATS_FAULT_STATUS_INFO2)/sizeof(mmATC_ATS_FAULT_STATUS_INFO2[0]), 0, 0 },
+	{ "mmATC_MISC_CG", REG_MMIO, 0xcd4, &mmATC_MISC_CG[0], sizeof(mmATC_MISC_CG)/sizeof(mmATC_MISC_CG[0]), 0, 0 },
+	{ "mmATC_L2_CNTL", REG_MMIO, 0xcd5, &mmATC_L2_CNTL[0], sizeof(mmATC_L2_CNTL)/sizeof(mmATC_L2_CNTL[0]), 0, 0 },
+	{ "mmATC_L2_CNTL2", REG_MMIO, 0xcd6, &mmATC_L2_CNTL2[0], sizeof(mmATC_L2_CNTL2)/sizeof(mmATC_L2_CNTL2[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG", REG_MMIO, 0xcd7, &mmATC_L2_DEBUG[0], sizeof(mmATC_L2_DEBUG)/sizeof(mmATC_L2_DEBUG[0]), 0, 0 },
+	{ "mmATC_L2_DEBUG2", REG_MMIO, 0xcd8, &mmATC_L2_DEBUG2[0], sizeof(mmATC_L2_DEBUG2)/sizeof(mmATC_L2_DEBUG2[0]), 0, 0 },
+	{ "mmATC_L2_CACHE_DATA0", REG_MMIO, 0xcd9, &mmATC_L2_CACHE_DATA0[0], sizeof(mmATC_L2_CACHE_DATA0)/sizeof(mmATC_L2_CACHE_DATA0[0]), 0, 0 },
+	{ "mmATC_L2_CACHE_DATA1", REG_MMIO, 0xcda, &mmATC_L2_CACHE_DATA1[0], sizeof(mmATC_L2_CACHE_DATA1)/sizeof(mmATC_L2_CACHE_DATA1[0]), 0, 0 },
+	{ "mmATC_L2_CACHE_DATA2", REG_MMIO, 0xcdb, &mmATC_L2_CACHE_DATA2[0], sizeof(mmATC_L2_CACHE_DATA2)/sizeof(mmATC_L2_CACHE_DATA2[0]), 0, 0 },
+	{ "mmATC_L1_CNTL", REG_MMIO, 0xcdc, &mmATC_L1_CNTL[0], sizeof(mmATC_L1_CNTL)/sizeof(mmATC_L1_CNTL[0]), 0, 0 },
+	{ "mmATC_L1_ADDRESS_OFFSET", REG_MMIO, 0xcdd, &mmATC_L1_ADDRESS_OFFSET[0], sizeof(mmATC_L1_ADDRESS_OFFSET)/sizeof(mmATC_L1_ADDRESS_OFFSET[0]), 0, 0 },
+	{ "mmATC_L1RD_DEBUG_TLB", REG_MMIO, 0xcde, &mmATC_L1RD_DEBUG_TLB[0], sizeof(mmATC_L1RD_DEBUG_TLB)/sizeof(mmATC_L1RD_DEBUG_TLB[0]), 0, 0 },
+	{ "mmATC_L1WR_DEBUG_TLB", REG_MMIO, 0xcdf, &mmATC_L1WR_DEBUG_TLB[0], sizeof(mmATC_L1WR_DEBUG_TLB)/sizeof(mmATC_L1WR_DEBUG_TLB[0]), 0, 0 },
+	{ "mmATC_L1RD_STATUS", REG_MMIO, 0xce0, &mmATC_L1RD_STATUS[0], sizeof(mmATC_L1RD_STATUS)/sizeof(mmATC_L1RD_STATUS[0]), 0, 0 },
+	{ "mmATC_L1WR_STATUS", REG_MMIO, 0xce1, &mmATC_L1WR_STATUS[0], sizeof(mmATC_L1WR_STATUS)/sizeof(mmATC_L1WR_STATUS[0]), 0, 0 },
+	{ "mmATC_L1RD_DEBUG2_TLB", REG_MMIO, 0xce2, &mmATC_L1RD_DEBUG2_TLB[0], sizeof(mmATC_L1RD_DEBUG2_TLB)/sizeof(mmATC_L1RD_DEBUG2_TLB[0]), 0, 0 },
+	{ "mmATC_L1WR_DEBUG2_TLB", REG_MMIO, 0xce3, &mmATC_L1WR_DEBUG2_TLB[0], sizeof(mmATC_L1WR_DEBUG2_TLB)/sizeof(mmATC_L1WR_DEBUG2_TLB[0]), 0, 0 },
+	{ "mmATC_VMID_PASID_MAPPING_UPDATE_STATUS", REG_MMIO, 0xce6, &mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0], sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)/sizeof(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS[0]), 0, 0 },
+	{ "mmATC_VMID0_PASID_MAPPING", REG_MMIO, 0xce7, &mmATC_VMID0_PASID_MAPPING[0], sizeof(mmATC_VMID0_PASID_MAPPING)/sizeof(mmATC_VMID0_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID1_PASID_MAPPING", REG_MMIO, 0xce8, &mmATC_VMID1_PASID_MAPPING[0], sizeof(mmATC_VMID1_PASID_MAPPING)/sizeof(mmATC_VMID1_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID2_PASID_MAPPING", REG_MMIO, 0xce9, &mmATC_VMID2_PASID_MAPPING[0], sizeof(mmATC_VMID2_PASID_MAPPING)/sizeof(mmATC_VMID2_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID3_PASID_MAPPING", REG_MMIO, 0xcea, &mmATC_VMID3_PASID_MAPPING[0], sizeof(mmATC_VMID3_PASID_MAPPING)/sizeof(mmATC_VMID3_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID4_PASID_MAPPING", REG_MMIO, 0xceb, &mmATC_VMID4_PASID_MAPPING[0], sizeof(mmATC_VMID4_PASID_MAPPING)/sizeof(mmATC_VMID4_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID5_PASID_MAPPING", REG_MMIO, 0xcec, &mmATC_VMID5_PASID_MAPPING[0], sizeof(mmATC_VMID5_PASID_MAPPING)/sizeof(mmATC_VMID5_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID6_PASID_MAPPING", REG_MMIO, 0xced, &mmATC_VMID6_PASID_MAPPING[0], sizeof(mmATC_VMID6_PASID_MAPPING)/sizeof(mmATC_VMID6_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID7_PASID_MAPPING", REG_MMIO, 0xcee, &mmATC_VMID7_PASID_MAPPING[0], sizeof(mmATC_VMID7_PASID_MAPPING)/sizeof(mmATC_VMID7_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID8_PASID_MAPPING", REG_MMIO, 0xcef, &mmATC_VMID8_PASID_MAPPING[0], sizeof(mmATC_VMID8_PASID_MAPPING)/sizeof(mmATC_VMID8_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID9_PASID_MAPPING", REG_MMIO, 0xcf0, &mmATC_VMID9_PASID_MAPPING[0], sizeof(mmATC_VMID9_PASID_MAPPING)/sizeof(mmATC_VMID9_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID10_PASID_MAPPING", REG_MMIO, 0xcf1, &mmATC_VMID10_PASID_MAPPING[0], sizeof(mmATC_VMID10_PASID_MAPPING)/sizeof(mmATC_VMID10_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID11_PASID_MAPPING", REG_MMIO, 0xcf2, &mmATC_VMID11_PASID_MAPPING[0], sizeof(mmATC_VMID11_PASID_MAPPING)/sizeof(mmATC_VMID11_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID12_PASID_MAPPING", REG_MMIO, 0xcf3, &mmATC_VMID12_PASID_MAPPING[0], sizeof(mmATC_VMID12_PASID_MAPPING)/sizeof(mmATC_VMID12_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID13_PASID_MAPPING", REG_MMIO, 0xcf4, &mmATC_VMID13_PASID_MAPPING[0], sizeof(mmATC_VMID13_PASID_MAPPING)/sizeof(mmATC_VMID13_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID14_PASID_MAPPING", REG_MMIO, 0xcf5, &mmATC_VMID14_PASID_MAPPING[0], sizeof(mmATC_VMID14_PASID_MAPPING)/sizeof(mmATC_VMID14_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_VMID15_PASID_MAPPING", REG_MMIO, 0xcf6, &mmATC_VMID15_PASID_MAPPING[0], sizeof(mmATC_VMID15_PASID_MAPPING)/sizeof(mmATC_VMID15_PASID_MAPPING[0]), 0, 0 },
+	{ "mmATC_ATS_VMID_STATUS", REG_MMIO, 0xd07, &mmATC_ATS_VMID_STATUS[0], sizeof(mmATC_ATS_VMID_STATUS)/sizeof(mmATC_ATS_VMID_STATUS[0]), 0, 0 },
+	{ "mmATC_ATS_SMU_STATUS", REG_MMIO, 0xd08, &mmATC_ATS_SMU_STATUS[0], sizeof(mmATC_ATS_SMU_STATUS)/sizeof(mmATC_ATS_SMU_STATUS[0]), 0, 0 },
+	{ "mmATC_L2_CNTL3", REG_MMIO, 0xd09, &mmATC_L2_CNTL3[0], sizeof(mmATC_L2_CNTL3)/sizeof(mmATC_L2_CNTL3[0]), 0, 0 },
+	{ "mmATC_L2_STATUS", REG_MMIO, 0xd0a, &mmATC_L2_STATUS[0], sizeof(mmATC_L2_STATUS)/sizeof(mmATC_L2_STATUS[0]), 0, 0 },
+	{ "mmATC_L2_STATUS2", REG_MMIO, 0xd0b, &mmATC_L2_STATUS2[0], sizeof(mmATC_L2_STATUS2)/sizeof(mmATC_L2_STATUS2[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_INDEX", REG_MMIO, 0xd40, &mmGMCON_RENG_RAM_INDEX[0], sizeof(mmGMCON_RENG_RAM_INDEX)/sizeof(mmGMCON_RENG_RAM_INDEX[0]), 0, 0 },
+	{ "mmGMCON_RENG_RAM_DATA", REG_MMIO, 0xd41, &mmGMCON_RENG_RAM_DATA[0], sizeof(mmGMCON_RENG_RAM_DATA)/sizeof(mmGMCON_RENG_RAM_DATA[0]), 0, 0 },
+	{ "mmGMCON_RENG_EXECUTE", REG_MMIO, 0xd42, &mmGMCON_RENG_EXECUTE[0], sizeof(mmGMCON_RENG_EXECUTE)/sizeof(mmGMCON_RENG_EXECUTE[0]), 0, 0 },
+	{ "mmGMCON_MISC", REG_MMIO, 0xd43, &mmGMCON_MISC[0], sizeof(mmGMCON_MISC)/sizeof(mmGMCON_MISC[0]), 0, 0 },
+	{ "mmGMCON_MISC2", REG_MMIO, 0xd44, &mmGMCON_MISC2[0], sizeof(mmGMCON_MISC2)/sizeof(mmGMCON_MISC2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE0", REG_MMIO, 0xd45, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE1", REG_MMIO, 0xd46, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE1[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_RANGE2", REG_MMIO, 0xd47, &mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_RANGE2[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0", REG_MMIO, 0xd48, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0[0]), 0, 0 },
+	{ "mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1", REG_MMIO, 0xd49, &mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0], sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1)/sizeof(mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL0", REG_MMIO, 0xd4a, &mmGMCON_PERF_MON_CNTL0[0], sizeof(mmGMCON_PERF_MON_CNTL0)/sizeof(mmGMCON_PERF_MON_CNTL0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_CNTL1", REG_MMIO, 0xd4b, &mmGMCON_PERF_MON_CNTL1[0], sizeof(mmGMCON_PERF_MON_CNTL1)/sizeof(mmGMCON_PERF_MON_CNTL1[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT0", REG_MMIO, 0xd4c, &mmGMCON_PERF_MON_RSLT0[0], sizeof(mmGMCON_PERF_MON_RSLT0)/sizeof(mmGMCON_PERF_MON_RSLT0[0]), 0, 0 },
+	{ "mmGMCON_PERF_MON_RSLT1", REG_MMIO, 0xd4d, &mmGMCON_PERF_MON_RSLT1[0], sizeof(mmGMCON_PERF_MON_RSLT1)/sizeof(mmGMCON_PERF_MON_RSLT1[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_CONFIG", REG_MMIO, 0xd4e, &mmGMCON_PGFSM_CONFIG[0], sizeof(mmGMCON_PGFSM_CONFIG)/sizeof(mmGMCON_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_WRITE", REG_MMIO, 0xd4f, &mmGMCON_PGFSM_WRITE[0], sizeof(mmGMCON_PGFSM_WRITE)/sizeof(mmGMCON_PGFSM_WRITE[0]), 0, 0 },
+	{ "mmGMCON_PGFSM_READ", REG_MMIO, 0xd50, &mmGMCON_PGFSM_READ[0], sizeof(mmGMCON_PGFSM_READ)/sizeof(mmGMCON_PGFSM_READ[0]), 0, 0 },
+	{ "mmGMCON_MISC3", REG_MMIO, 0xd51, &mmGMCON_MISC3[0], sizeof(mmGMCON_MISC3)/sizeof(mmGMCON_MISC3[0]), 0, 0 },
+	{ "mmGMCON_MASK", REG_MMIO, 0xd52, &mmGMCON_MASK[0], sizeof(mmGMCON_MASK)/sizeof(mmGMCON_MASK[0]), 0, 0 },
+	{ "mmGMCON_LPT_TARGET", REG_MMIO, 0xd53, &mmGMCON_LPT_TARGET[0], sizeof(mmGMCON_LPT_TARGET)/sizeof(mmGMCON_LPT_TARGET[0]), 0, 0 },
+	{ "mmGMCON_DEBUG", REG_MMIO, 0xd5f, &mmGMCON_DEBUG[0], sizeof(mmGMCON_DEBUG)/sizeof(mmGMCON_DEBUG[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_EN_RD", REG_MMIO, 0xdc0, &mmMC_ARB_HARSH_EN_RD[0], sizeof(mmMC_ARB_HARSH_EN_RD)/sizeof(mmMC_ARB_HARSH_EN_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_EN_WR", REG_MMIO, 0xdc1, &mmMC_ARB_HARSH_EN_WR[0], sizeof(mmMC_ARB_HARSH_EN_WR)/sizeof(mmMC_ARB_HARSH_EN_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI0_RD", REG_MMIO, 0xdc2, &mmMC_ARB_HARSH_TX_HI0_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI0_RD)/sizeof(mmMC_ARB_HARSH_TX_HI0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI0_WR", REG_MMIO, 0xdc3, &mmMC_ARB_HARSH_TX_HI0_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI0_WR)/sizeof(mmMC_ARB_HARSH_TX_HI0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI1_RD", REG_MMIO, 0xdc4, &mmMC_ARB_HARSH_TX_HI1_RD[0], sizeof(mmMC_ARB_HARSH_TX_HI1_RD)/sizeof(mmMC_ARB_HARSH_TX_HI1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_HI1_WR", REG_MMIO, 0xdc5, &mmMC_ARB_HARSH_TX_HI1_WR[0], sizeof(mmMC_ARB_HARSH_TX_HI1_WR)/sizeof(mmMC_ARB_HARSH_TX_HI1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO0_RD", REG_MMIO, 0xdc6, &mmMC_ARB_HARSH_TX_LO0_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO0_RD)/sizeof(mmMC_ARB_HARSH_TX_LO0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO0_WR", REG_MMIO, 0xdc7, &mmMC_ARB_HARSH_TX_LO0_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO0_WR)/sizeof(mmMC_ARB_HARSH_TX_LO0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO1_RD", REG_MMIO, 0xdc8, &mmMC_ARB_HARSH_TX_LO1_RD[0], sizeof(mmMC_ARB_HARSH_TX_LO1_RD)/sizeof(mmMC_ARB_HARSH_TX_LO1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_TX_LO1_WR", REG_MMIO, 0xdc9, &mmMC_ARB_HARSH_TX_LO1_WR[0], sizeof(mmMC_ARB_HARSH_TX_LO1_WR)/sizeof(mmMC_ARB_HARSH_TX_LO1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD0_RD", REG_MMIO, 0xdca, &mmMC_ARB_HARSH_BWPERIOD0_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD0_WR", REG_MMIO, 0xdcb, &mmMC_ARB_HARSH_BWPERIOD0_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD1_RD", REG_MMIO, 0xdcc, &mmMC_ARB_HARSH_BWPERIOD1_RD[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWPERIOD1_WR", REG_MMIO, 0xdcd, &mmMC_ARB_HARSH_BWPERIOD1_WR[0], sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR)/sizeof(mmMC_ARB_HARSH_BWPERIOD1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT0_RD", REG_MMIO, 0xdce, &mmMC_ARB_HARSH_BWCNT0_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT0_RD)/sizeof(mmMC_ARB_HARSH_BWCNT0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT0_WR", REG_MMIO, 0xdcf, &mmMC_ARB_HARSH_BWCNT0_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT0_WR)/sizeof(mmMC_ARB_HARSH_BWCNT0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT1_RD", REG_MMIO, 0xdd0, &mmMC_ARB_HARSH_BWCNT1_RD[0], sizeof(mmMC_ARB_HARSH_BWCNT1_RD)/sizeof(mmMC_ARB_HARSH_BWCNT1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_BWCNT1_WR", REG_MMIO, 0xdd1, &mmMC_ARB_HARSH_BWCNT1_WR[0], sizeof(mmMC_ARB_HARSH_BWCNT1_WR)/sizeof(mmMC_ARB_HARSH_BWCNT1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT0_RD", REG_MMIO, 0xdd2, &mmMC_ARB_HARSH_SAT0_RD[0], sizeof(mmMC_ARB_HARSH_SAT0_RD)/sizeof(mmMC_ARB_HARSH_SAT0_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT0_WR", REG_MMIO, 0xdd3, &mmMC_ARB_HARSH_SAT0_WR[0], sizeof(mmMC_ARB_HARSH_SAT0_WR)/sizeof(mmMC_ARB_HARSH_SAT0_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT1_RD", REG_MMIO, 0xdd4, &mmMC_ARB_HARSH_SAT1_RD[0], sizeof(mmMC_ARB_HARSH_SAT1_RD)/sizeof(mmMC_ARB_HARSH_SAT1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_SAT1_WR", REG_MMIO, 0xdd5, &mmMC_ARB_HARSH_SAT1_WR[0], sizeof(mmMC_ARB_HARSH_SAT1_WR)/sizeof(mmMC_ARB_HARSH_SAT1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_CTL_RD", REG_MMIO, 0xdd6, &mmMC_ARB_HARSH_CTL_RD[0], sizeof(mmMC_ARB_HARSH_CTL_RD)/sizeof(mmMC_ARB_HARSH_CTL_RD[0]), 0, 0 },
+	{ "mmMC_ARB_HARSH_CTL_WR", REG_MMIO, 0xdd7, &mmMC_ARB_HARSH_CTL_WR[0], sizeof(mmMC_ARB_HARSH_CTL_WR)/sizeof(mmMC_ARB_HARSH_CTL_WR[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PRIORITY1_RD", REG_MMIO, 0xdd8, &mmMC_ARB_GRUB_PRIORITY1_RD[0], sizeof(mmMC_ARB_GRUB_PRIORITY1_RD)/sizeof(mmMC_ARB_GRUB_PRIORITY1_RD[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PRIORITY1_WR", REG_MMIO, 0xdd9, &mmMC_ARB_GRUB_PRIORITY1_WR[0], sizeof(mmMC_ARB_GRUB_PRIORITY1_WR)/sizeof(mmMC_ARB_GRUB_PRIORITY1_WR[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PRIORITY2_RD", REG_MMIO, 0xdda, &mmMC_ARB_GRUB_PRIORITY2_RD[0], sizeof(mmMC_ARB_GRUB_PRIORITY2_RD)/sizeof(mmMC_ARB_GRUB_PRIORITY2_RD[0]), 0, 0 },
+	{ "mmMC_ARB_GRUB_PRIORITY2_WR", REG_MMIO, 0xddb, &mmMC_ARB_GRUB_PRIORITY2_WR[0], sizeof(mmMC_ARB_GRUB_PRIORITY2_WR)/sizeof(mmMC_ARB_GRUB_PRIORITY2_WR[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_SPM", REG_MMIO, 0xde0, &mmMC_HUB_RDREQ_ISP_SPM[0], sizeof(mmMC_HUB_RDREQ_ISP_SPM)/sizeof(mmMC_HUB_RDREQ_ISP_SPM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_MPM", REG_MMIO, 0xde1, &mmMC_HUB_RDREQ_ISP_MPM[0], sizeof(mmMC_HUB_RDREQ_ISP_MPM)/sizeof(mmMC_HUB_RDREQ_ISP_MPM[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_ISP_CCPU", REG_MMIO, 0xde2, &mmMC_HUB_RDREQ_ISP_CCPU[0], sizeof(mmMC_HUB_RDREQ_ISP_CCPU)/sizeof(mmMC_HUB_RDREQ_ISP_CCPU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_SPM", REG_MMIO, 0xde3, &mmMC_HUB_WDP_ISP_SPM[0], sizeof(mmMC_HUB_WDP_ISP_SPM)/sizeof(mmMC_HUB_WDP_ISP_SPM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_MPS", REG_MMIO, 0xde4, &mmMC_HUB_WDP_ISP_MPS[0], sizeof(mmMC_HUB_WDP_ISP_MPS)/sizeof(mmMC_HUB_WDP_ISP_MPS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_MPM", REG_MMIO, 0xde5, &mmMC_HUB_WDP_ISP_MPM[0], sizeof(mmMC_HUB_WDP_ISP_MPM)/sizeof(mmMC_HUB_WDP_ISP_MPM[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_ISP_CCPU", REG_MMIO, 0xde6, &mmMC_HUB_WDP_ISP_CCPU[0], sizeof(mmMC_HUB_WDP_ISP_CCPU)/sizeof(mmMC_HUB_WDP_ISP_CCPU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDS", REG_MMIO, 0xde7, &mmMC_HUB_RDREQ_MCDS[0], sizeof(mmMC_HUB_RDREQ_MCDS)/sizeof(mmMC_HUB_RDREQ_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDT", REG_MMIO, 0xde8, &mmMC_HUB_RDREQ_MCDT[0], sizeof(mmMC_HUB_RDREQ_MCDT)/sizeof(mmMC_HUB_RDREQ_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDU", REG_MMIO, 0xde9, &mmMC_HUB_RDREQ_MCDU[0], sizeof(mmMC_HUB_RDREQ_MCDU)/sizeof(mmMC_HUB_RDREQ_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_MCDV", REG_MMIO, 0xdea, &mmMC_HUB_RDREQ_MCDV[0], sizeof(mmMC_HUB_RDREQ_MCDV)/sizeof(mmMC_HUB_RDREQ_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDS", REG_MMIO, 0xdeb, &mmMC_HUB_WDP_MCDS[0], sizeof(mmMC_HUB_WDP_MCDS)/sizeof(mmMC_HUB_WDP_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDT", REG_MMIO, 0xdec, &mmMC_HUB_WDP_MCDT[0], sizeof(mmMC_HUB_WDP_MCDT)/sizeof(mmMC_HUB_WDP_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDU", REG_MMIO, 0xded, &mmMC_HUB_WDP_MCDU[0], sizeof(mmMC_HUB_WDP_MCDU)/sizeof(mmMC_HUB_WDP_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_MCDV", REG_MMIO, 0xdee, &mmMC_HUB_WDP_MCDV[0], sizeof(mmMC_HUB_WDP_MCDV)/sizeof(mmMC_HUB_WDP_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDS", REG_MMIO, 0xdef, &mmMC_HUB_WRRET_MCDS[0], sizeof(mmMC_HUB_WRRET_MCDS)/sizeof(mmMC_HUB_WRRET_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDT", REG_MMIO, 0xdf0, &mmMC_HUB_WRRET_MCDT[0], sizeof(mmMC_HUB_WRRET_MCDT)/sizeof(mmMC_HUB_WRRET_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDU", REG_MMIO, 0xdf1, &mmMC_HUB_WRRET_MCDU[0], sizeof(mmMC_HUB_WRRET_MCDU)/sizeof(mmMC_HUB_WRRET_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WRRET_MCDV", REG_MMIO, 0xdf2, &mmMC_HUB_WRRET_MCDV[0], sizeof(mmMC_HUB_WRRET_MCDV)/sizeof(mmMC_HUB_WRRET_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDW", REG_MMIO, 0xdf3, &mmMC_HUB_WDP_CREDITS_MCDW[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDW)/sizeof(mmMC_HUB_WDP_CREDITS_MCDW[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDX", REG_MMIO, 0xdf4, &mmMC_HUB_WDP_CREDITS_MCDX[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDX)/sizeof(mmMC_HUB_WDP_CREDITS_MCDX[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDY", REG_MMIO, 0xdf5, &mmMC_HUB_WDP_CREDITS_MCDY[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDY)/sizeof(mmMC_HUB_WDP_CREDITS_MCDY[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDZ", REG_MMIO, 0xdf6, &mmMC_HUB_WDP_CREDITS_MCDZ[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDZ)/sizeof(mmMC_HUB_WDP_CREDITS_MCDZ[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDS", REG_MMIO, 0xdf7, &mmMC_HUB_WDP_CREDITS_MCDS[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDS)/sizeof(mmMC_HUB_WDP_CREDITS_MCDS[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDT", REG_MMIO, 0xdf8, &mmMC_HUB_WDP_CREDITS_MCDT[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDT)/sizeof(mmMC_HUB_WDP_CREDITS_MCDT[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDU", REG_MMIO, 0xdf9, &mmMC_HUB_WDP_CREDITS_MCDU[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDU)/sizeof(mmMC_HUB_WDP_CREDITS_MCDU[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_CREDITS_MCDV", REG_MMIO, 0xdfa, &mmMC_HUB_WDP_CREDITS_MCDV[0], sizeof(mmMC_HUB_WDP_CREDITS_MCDV)/sizeof(mmMC_HUB_WDP_CREDITS_MCDV[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_BP2", REG_MMIO, 0xdfb, &mmMC_HUB_WDP_BP2[0], sizeof(mmMC_HUB_WDP_BP2)/sizeof(mmMC_HUB_WDP_BP2[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCE1", REG_MMIO, 0xdfc, &mmMC_HUB_RDREQ_VCE1[0], sizeof(mmMC_HUB_RDREQ_VCE1)/sizeof(mmMC_HUB_RDREQ_VCE1[0]), 0, 0 },
+	{ "mmMC_HUB_RDREQ_VCEU1", REG_MMIO, 0xdfd, &mmMC_HUB_RDREQ_VCEU1[0], sizeof(mmMC_HUB_RDREQ_VCEU1)/sizeof(mmMC_HUB_RDREQ_VCEU1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCE1", REG_MMIO, 0xdfe, &mmMC_HUB_WDP_VCE1[0], sizeof(mmMC_HUB_WDP_VCE1)/sizeof(mmMC_HUB_WDP_VCE1[0]), 0, 0 },
+	{ "mmMC_HUB_WDP_VCEU1", REG_MMIO, 0xdff, &mmMC_HUB_WDP_VCEU1[0], sizeof(mmMC_HUB_WDP_VCEU1)/sizeof(mmMC_HUB_WDP_VCEU1[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF0", REG_MMIO, 0xf980, &mmMC_VM_FB_SIZE_OFFSET_VF0[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF0)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF0[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF1", REG_MMIO, 0xf981, &mmMC_VM_FB_SIZE_OFFSET_VF1[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF1)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF1[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF2", REG_MMIO, 0xf982, &mmMC_VM_FB_SIZE_OFFSET_VF2[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF2)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF2[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF3", REG_MMIO, 0xf983, &mmMC_VM_FB_SIZE_OFFSET_VF3[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF3)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF3[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF4", REG_MMIO, 0xf984, &mmMC_VM_FB_SIZE_OFFSET_VF4[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF4)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF4[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF5", REG_MMIO, 0xf985, &mmMC_VM_FB_SIZE_OFFSET_VF5[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF5)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF5[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF6", REG_MMIO, 0xf986, &mmMC_VM_FB_SIZE_OFFSET_VF6[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF6)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF6[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF7", REG_MMIO, 0xf987, &mmMC_VM_FB_SIZE_OFFSET_VF7[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF7)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF7[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF8", REG_MMIO, 0xf988, &mmMC_VM_FB_SIZE_OFFSET_VF8[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF8)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF8[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF9", REG_MMIO, 0xf989, &mmMC_VM_FB_SIZE_OFFSET_VF9[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF9)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF9[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF10", REG_MMIO, 0xf98a, &mmMC_VM_FB_SIZE_OFFSET_VF10[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF10)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF10[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF11", REG_MMIO, 0xf98b, &mmMC_VM_FB_SIZE_OFFSET_VF11[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF11)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF11[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF12", REG_MMIO, 0xf98c, &mmMC_VM_FB_SIZE_OFFSET_VF12[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF12)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF12[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF13", REG_MMIO, 0xf98d, &mmMC_VM_FB_SIZE_OFFSET_VF13[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF13)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF13[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF14", REG_MMIO, 0xf98e, &mmMC_VM_FB_SIZE_OFFSET_VF14[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF14)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF14[0]), 0, 0 },
+	{ "mmMC_VM_FB_SIZE_OFFSET_VF15", REG_MMIO, 0xf98f, &mmMC_VM_FB_SIZE_OFFSET_VF15[0], sizeof(mmMC_VM_FB_SIZE_OFFSET_VF15)/sizeof(mmMC_VM_FB_SIZE_OFFSET_VF15[0]), 0, 0 },
+	{ "mmMC_VM_NB_MMIOBASE", REG_MMIO, 0xf990, &mmMC_VM_NB_MMIOBASE[0], sizeof(mmMC_VM_NB_MMIOBASE)/sizeof(mmMC_VM_NB_MMIOBASE[0]), 0, 0 },
+	{ "mmMC_VM_NB_MMIOLIMIT", REG_MMIO, 0xf991, &mmMC_VM_NB_MMIOLIMIT[0], sizeof(mmMC_VM_NB_MMIOLIMIT)/sizeof(mmMC_VM_NB_MMIOLIMIT[0]), 0, 0 },
+	{ "mmMC_VM_NB_PCI_CTRL", REG_MMIO, 0xf992, &mmMC_VM_NB_PCI_CTRL[0], sizeof(mmMC_VM_NB_PCI_CTRL)/sizeof(mmMC_VM_NB_PCI_CTRL[0]), 0, 0 },
+	{ "mmMC_VM_NB_PCI_ARB", REG_MMIO, 0xf993, &mmMC_VM_NB_PCI_ARB[0], sizeof(mmMC_VM_NB_PCI_ARB)/sizeof(mmMC_VM_NB_PCI_ARB[0]), 0, 0 },
+	{ "mmMC_VM_NB_TOP_OF_DRAM_SLOT1", REG_MMIO, 0xf994, &mmMC_VM_NB_TOP_OF_DRAM_SLOT1[0], sizeof(mmMC_VM_NB_TOP_OF_DRAM_SLOT1)/sizeof(mmMC_VM_NB_TOP_OF_DRAM_SLOT1[0]), 0, 0 },
+	{ "mmMC_VM_NB_LOWER_TOP_OF_DRAM2", REG_MMIO, 0xf995, &mmMC_VM_NB_LOWER_TOP_OF_DRAM2[0], sizeof(mmMC_VM_NB_LOWER_TOP_OF_DRAM2)/sizeof(mmMC_VM_NB_LOWER_TOP_OF_DRAM2[0]), 0, 0 },
+	{ "mmMC_VM_NB_UPPER_TOP_OF_DRAM2", REG_MMIO, 0xf996, &mmMC_VM_NB_UPPER_TOP_OF_DRAM2[0], sizeof(mmMC_VM_NB_UPPER_TOP_OF_DRAM2)/sizeof(mmMC_VM_NB_UPPER_TOP_OF_DRAM2[0]), 0, 0 },
+	{ "mmMC_VM_NB_TOP_OF_DRAM3", REG_MMIO, 0xf997, &mmMC_VM_NB_TOP_OF_DRAM3[0], sizeof(mmMC_VM_NB_TOP_OF_DRAM3)/sizeof(mmMC_VM_NB_TOP_OF_DRAM3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_LO_0", REG_MMIO, 0xf998, &mmMC_VM_MARC_BASE_LO_0[0], sizeof(mmMC_VM_MARC_BASE_LO_0)/sizeof(mmMC_VM_MARC_BASE_LO_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_HI_0", REG_MMIO, 0xf999, &mmMC_VM_MARC_BASE_HI_0[0], sizeof(mmMC_VM_MARC_BASE_HI_0)/sizeof(mmMC_VM_MARC_BASE_HI_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_LO_0", REG_MMIO, 0xf99a, &mmMC_VM_MARC_RELOC_LO_0[0], sizeof(mmMC_VM_MARC_RELOC_LO_0)/sizeof(mmMC_VM_MARC_RELOC_LO_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_HI_0", REG_MMIO, 0xf99b, &mmMC_VM_MARC_RELOC_HI_0[0], sizeof(mmMC_VM_MARC_RELOC_HI_0)/sizeof(mmMC_VM_MARC_RELOC_HI_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_LO_0", REG_MMIO, 0xf99c, &mmMC_VM_MARC_LEN_LO_0[0], sizeof(mmMC_VM_MARC_LEN_LO_0)/sizeof(mmMC_VM_MARC_LEN_LO_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_HI_0", REG_MMIO, 0xf99d, &mmMC_VM_MARC_LEN_HI_0[0], sizeof(mmMC_VM_MARC_LEN_HI_0)/sizeof(mmMC_VM_MARC_LEN_HI_0[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_LO_1", REG_MMIO, 0xf99e, &mmMC_VM_MARC_BASE_LO_1[0], sizeof(mmMC_VM_MARC_BASE_LO_1)/sizeof(mmMC_VM_MARC_BASE_LO_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_HI_1", REG_MMIO, 0xf99f, &mmMC_VM_MARC_BASE_HI_1[0], sizeof(mmMC_VM_MARC_BASE_HI_1)/sizeof(mmMC_VM_MARC_BASE_HI_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_LO_1", REG_MMIO, 0xf9a0, &mmMC_VM_MARC_RELOC_LO_1[0], sizeof(mmMC_VM_MARC_RELOC_LO_1)/sizeof(mmMC_VM_MARC_RELOC_LO_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_HI_1", REG_MMIO, 0xf9a1, &mmMC_VM_MARC_RELOC_HI_1[0], sizeof(mmMC_VM_MARC_RELOC_HI_1)/sizeof(mmMC_VM_MARC_RELOC_HI_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_LO_1", REG_MMIO, 0xf9a2, &mmMC_VM_MARC_LEN_LO_1[0], sizeof(mmMC_VM_MARC_LEN_LO_1)/sizeof(mmMC_VM_MARC_LEN_LO_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_HI_1", REG_MMIO, 0xf9a3, &mmMC_VM_MARC_LEN_HI_1[0], sizeof(mmMC_VM_MARC_LEN_HI_1)/sizeof(mmMC_VM_MARC_LEN_HI_1[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_LO_2", REG_MMIO, 0xf9a4, &mmMC_VM_MARC_BASE_LO_2[0], sizeof(mmMC_VM_MARC_BASE_LO_2)/sizeof(mmMC_VM_MARC_BASE_LO_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_HI_2", REG_MMIO, 0xf9a5, &mmMC_VM_MARC_BASE_HI_2[0], sizeof(mmMC_VM_MARC_BASE_HI_2)/sizeof(mmMC_VM_MARC_BASE_HI_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_LO_2", REG_MMIO, 0xf9a6, &mmMC_VM_MARC_RELOC_LO_2[0], sizeof(mmMC_VM_MARC_RELOC_LO_2)/sizeof(mmMC_VM_MARC_RELOC_LO_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_HI_2", REG_MMIO, 0xf9a7, &mmMC_VM_MARC_RELOC_HI_2[0], sizeof(mmMC_VM_MARC_RELOC_HI_2)/sizeof(mmMC_VM_MARC_RELOC_HI_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_LO_2", REG_MMIO, 0xf9a8, &mmMC_VM_MARC_LEN_LO_2[0], sizeof(mmMC_VM_MARC_LEN_LO_2)/sizeof(mmMC_VM_MARC_LEN_LO_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_HI_2", REG_MMIO, 0xf9a9, &mmMC_VM_MARC_LEN_HI_2[0], sizeof(mmMC_VM_MARC_LEN_HI_2)/sizeof(mmMC_VM_MARC_LEN_HI_2[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_LO_3", REG_MMIO, 0xf9aa, &mmMC_VM_MARC_BASE_LO_3[0], sizeof(mmMC_VM_MARC_BASE_LO_3)/sizeof(mmMC_VM_MARC_BASE_LO_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_BASE_HI_3", REG_MMIO, 0xf9ab, &mmMC_VM_MARC_BASE_HI_3[0], sizeof(mmMC_VM_MARC_BASE_HI_3)/sizeof(mmMC_VM_MARC_BASE_HI_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_LO_3", REG_MMIO, 0xf9ac, &mmMC_VM_MARC_RELOC_LO_3[0], sizeof(mmMC_VM_MARC_RELOC_LO_3)/sizeof(mmMC_VM_MARC_RELOC_LO_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_RELOC_HI_3", REG_MMIO, 0xf9ad, &mmMC_VM_MARC_RELOC_HI_3[0], sizeof(mmMC_VM_MARC_RELOC_HI_3)/sizeof(mmMC_VM_MARC_RELOC_HI_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_LO_3", REG_MMIO, 0xf9ae, &mmMC_VM_MARC_LEN_LO_3[0], sizeof(mmMC_VM_MARC_LEN_LO_3)/sizeof(mmMC_VM_MARC_LEN_LO_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_LEN_HI_3", REG_MMIO, 0xf9af, &mmMC_VM_MARC_LEN_HI_3[0], sizeof(mmMC_VM_MARC_LEN_HI_3)/sizeof(mmMC_VM_MARC_LEN_HI_3[0]), 0, 0 },
+	{ "mmMC_VM_MARC_CNTL", REG_MMIO, 0xf9b0, &mmMC_VM_MARC_CNTL[0], sizeof(mmMC_VM_MARC_CNTL)/sizeof(mmMC_VM_MARC_CNTL[0]), 0, 0 },
diff --git a/src/lib/ip/oss10.c b/src/lib/ip/oss10.c
new file mode 100644
index 0000000..7d820da
--- /dev/null
+++ b/src/lib/ip/oss10.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "oss10_bits.i"
+
+static const struct umr_reg oss10_registers[] = {
+#include "oss10_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_oss10(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "oss10";
+	ip->no_regs = sizeof(oss10_registers)/sizeof(oss10_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(oss10_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, oss10_registers, sizeof(oss10_registers));
+	return ip;
+}
diff --git a/src/lib/ip/oss10_bits.i b/src/lib/ip/oss10_bits.i
new file mode 100644
index 0000000..311a313
--- /dev/null
+++ b/src/lib/ip/oss10_bits.i
@@ -0,0 +1,1010 @@
+static struct umr_bitfield ixDH_TEST[] = {
+	 { "DH_TEST", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP7[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_PORT_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRINGOSC_MASK[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPU_PORT_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CNTL[] = {
+	 { "COMBINE_SYSTEM_MC", 17, 17, &umr_bitfield_default },
+	 { "PWR_REQUEST_HALT", 16, 16, &umr_bitfield_default },
+	 { "READ_TIMEOUT", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_GFX_CNTL[] = {
+	 { "VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_STATUS2[] = {
+	 { "TST_RQ_PENDING", 1, 1, &umr_bitfield_default },
+	 { "VCE_BUSY", 7, 7, &umr_bitfield_default },
+	 { "VCE_RQ_PENDING", 3, 3, &umr_bitfield_default },
+	 { "XDMA_BUSY", 8, 8, &umr_bitfield_default },
+	 { "XSP_BUSY", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_STATUS[] = {
+	 { "BIF_BUSY", 29, 29, &umr_bitfield_default },
+	 { "GRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "HI_RQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "IH_BUSY", 17, 17, &umr_bitfield_default },
+	 { "IO_EXTERN_SIGNAL", 7, 7, &umr_bitfield_default },
+	 { "MCB_BUSY", 9, 9, &umr_bitfield_default },
+	 { "MCB_NON_DISPLAY_BUSY", 10, 10, &umr_bitfield_default },
+	 { "MCC_BUSY", 11, 11, &umr_bitfield_default },
+	 { "MCD_BUSY", 12, 12, &umr_bitfield_default },
+	 { "SEM_BUSY", 14, 14, &umr_bitfield_default },
+	 { "SMU_RQ_PENDING", 4, 4, &umr_bitfield_default },
+	 { "UVD_BUSY", 19, 19, &umr_bitfield_default },
+	 { "UVD_RQ_PENDING", 1, 1, &umr_bitfield_default },
+	 { "VMC_BUSY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SOFT_RESET[] = {
+	 { "SOFT_RESET_BIF", 1, 1, &umr_bitfield_default },
+	 { "SOFT_RESET_DC", 5, 5, &umr_bitfield_default },
+	 { "SOFT_RESET_GRBM", 8, 8, &umr_bitfield_default },
+	 { "SOFT_RESET_HDP", 9, 9, &umr_bitfield_default },
+	 { "SOFT_RESET_IH", 10, 10, &umr_bitfield_default },
+	 { "SOFT_RESET_MC", 11, 11, &umr_bitfield_default },
+	 { "SOFT_RESET_ORB", 23, 23, &umr_bitfield_default },
+	 { "SOFT_RESET_REGBB", 22, 22, &umr_bitfield_default },
+	 { "SOFT_RESET_ROM", 14, 14, &umr_bitfield_default },
+	 { "SOFT_RESET_SEM", 15, 15, &umr_bitfield_default },
+	 { "SOFT_RESET_TST", 21, 21, &umr_bitfield_default },
+	 { "SOFT_RESET_UVD", 18, 18, &umr_bitfield_default },
+	 { "SOFT_RESET_VCE", 24, 24, &umr_bitfield_default },
+	 { "SOFT_RESET_VMC", 17, 17, &umr_bitfield_default },
+	 { "SOFT_RESET_XDMA", 25, 25, &umr_bitfield_default },
+	 { "SOFT_RESET_XSP", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_CNTL[] = {
+	 { "SRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CHIP_REVISION[] = {
+	 { "CHIP_REVISION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SYS_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SYS_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG[] = {
+	 { "DISABLE_READ_TIMEOUT", 1, 1, &umr_bitfield_default },
+	 { "IGNORE_RDY", 0, 0, &umr_bitfield_default },
+	 { "MC_CLOCK_DOMAIN_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "SNAPSHOT_FREE_CNTRS", 2, 2, &umr_bitfield_default },
+	 { "SYS_CLOCK_DOMAIN_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "UVD_CLOCK_DOMAIN_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "VCE_CLOCK_DOMAIN_OVERRIDE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_SNAPSHOT[] = {
+	 { "BIF_RDY", 7, 7, &umr_bitfield_default },
+	 { "DC_RDY", 6, 6, &umr_bitfield_default },
+	 { "GRBM_RDY", 5, 5, &umr_bitfield_default },
+	 { "MCB_RDY", 0, 0, &umr_bitfield_default },
+	 { "MCC0_RDY", 28, 28, &umr_bitfield_default },
+	 { "MCC1_RDY", 27, 27, &umr_bitfield_default },
+	 { "MCC2_RDY", 26, 26, &umr_bitfield_default },
+	 { "MCC3_RDY", 25, 25, &umr_bitfield_default },
+	 { "MCC4_RDY", 24, 24, &umr_bitfield_default },
+	 { "MCC5_RDY", 23, 23, &umr_bitfield_default },
+	 { "MCC6_RDY", 22, 22, &umr_bitfield_default },
+	 { "MCC7_RDY", 21, 21, &umr_bitfield_default },
+	 { "MCD0_RDY", 20, 20, &umr_bitfield_default },
+	 { "MCD1_RDY", 19, 19, &umr_bitfield_default },
+	 { "MCD2_RDY", 18, 18, &umr_bitfield_default },
+	 { "MCD3_RDY", 17, 17, &umr_bitfield_default },
+	 { "MCD4_RDY", 16, 16, &umr_bitfield_default },
+	 { "MCD5_RDY", 15, 15, &umr_bitfield_default },
+	 { "MCD6_RDY", 14, 14, &umr_bitfield_default },
+	 { "MCD7_RDY", 13, 13, &umr_bitfield_default },
+	 { "ORB_RDY", 12, 12, &umr_bitfield_default },
+	 { "REGBB_RDY", 11, 11, &umr_bitfield_default },
+	 { "UVD_RDY", 9, 9, &umr_bitfield_default },
+	 { "VCE_RDY", 29, 29, &umr_bitfield_default },
+	 { "XDMA_RDY", 8, 8, &umr_bitfield_default },
+	 { "XSP_RDY", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_READ_ERROR[] = {
+	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
+	 { "READ_REQUESTER_GRBM", 25, 25, &umr_bitfield_default },
+	 { "READ_REQUESTER_HI", 24, 24, &umr_bitfield_default },
+	 { "READ_REQUESTER_SMU", 26, 26, &umr_bitfield_default },
+	 { "READ_REQUESTER_TST", 22, 22, &umr_bitfield_default },
+	 { "READ_REQUESTER_UVD", 29, 29, &umr_bitfield_default },
+	 { "READ_REQUESTER_VCE", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_CNTL[] = {
+	 { "RDERR_INT_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_STATUS[] = {
+	 { "RDERR_INT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_ACK[] = {
+	 { "RDERR_INT_ACK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_CLKEN_CNTL[] = {
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_CLKEN_CNTL[] = {
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VCE_CLKEN_CNTL[] = {
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_UVD_CLKEN_CNTL[] = {
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_OVERFLOW_CNTL[] = {
+	 { "XDMA_MSTR_OVERFLOW_COUNT_ENABLE", 31, 31, &umr_bitfield_default },
+	 { "XDMA_MSTR_OVERFLOW_COUNT", 0, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_OVERFLOW_THRESHOLD", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFMON_CNTL[] = {
+	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_LO[] = {
+	 { "PERF_COUNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_HI[] = {
+	 { "PERF_COUNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_LO[] = {
+	 { "PERF_COUNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_HI[] = {
+	 { "PERF_COUNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_HOST_PATH_CNTL[] = {
+	 { "ALL_SURFACES_DIS", 29, 29, &umr_bitfield_default },
+	 { "BIF_RDRET_CREDIT", 0, 2, &umr_bitfield_default },
+	 { "CACHE_INVALIDATE", 22, 22, &umr_bitfield_default },
+	 { "CLOCK_GATING_DIS", 23, 23, &umr_bitfield_default },
+	 { "LIN_RD_CACHE_DIS", 31, 31, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 3, 8, &umr_bitfield_default },
+	 { "RD_STALL_TIMER", 11, 12, &umr_bitfield_default },
+	 { "REG_CLK_ENABLE_COUNT", 24, 27, &umr_bitfield_default },
+	 { "WRITE_COMBINE_EN", 21, 21, &umr_bitfield_default },
+	 { "WRITE_COMBINE_TIMER", 19, 20, &umr_bitfield_default },
+	 { "WRITE_THROUGH_CACHE_DIS", 30, 30, &umr_bitfield_default },
+	 { "WR_STALL_TIMER", 9, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_BASE[] = {
+	 { "NONSURF_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_INFO[] = {
+	 { "NONSURF_ADDR_TYPE", 0, 0, &umr_bitfield_default },
+	 { "NONSURF_ARRAY_MODE", 1, 4, &umr_bitfield_default },
+	 { "NONSURF_BANK_HEIGHT", 24, 25, &umr_bitfield_default },
+	 { "NONSURF_BANK_WIDTH", 22, 23, &umr_bitfield_default },
+	 { "NONSURF_ENDIAN", 5, 6, &umr_bitfield_default },
+	 { "NONSURF_MACRO_TILE_ASPECT", 26, 27, &umr_bitfield_default },
+	 { "NONSURF_MICRO_TILE_MODE", 28, 29, &umr_bitfield_default },
+	 { "NONSURF_NUM_BANKS", 20, 21, &umr_bitfield_default },
+	 { "NONSURF_PIXEL_SIZE", 7, 9, &umr_bitfield_default },
+	 { "NONSURF_PRIV", 15, 15, &umr_bitfield_default },
+	 { "NONSURF_SAMPLE_NUM", 10, 12, &umr_bitfield_default },
+	 { "NONSURF_SAMPLE_SIZE", 13, 14, &umr_bitfield_default },
+	 { "NONSURF_SLICE_TILE_MAX_MSB", 30, 30, &umr_bitfield_default },
+	 { "NONSURF_TILE_COMPACT", 16, 16, &umr_bitfield_default },
+	 { "NONSURF_TILE_SPLIT", 17, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_SIZE[] = {
+	 { "NONSURF_PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "NONSURF_SLICE_TILE_MAX", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURF_FLAGS[] = {
+	 { "NONSURF_READ_FLAG", 1, 1, &umr_bitfield_default },
+	 { "NONSURF_WRITE_FLAG", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURF_FLAGS_CLR[] = {
+	 { "NONSURF_READ_FLAG_CLR", 1, 1, &umr_bitfield_default },
+	 { "NONSURF_WRITE_FLAG_CLR", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_SW_SEMAPHORE[] = {
+	 { "SW_SEMAPHORE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_DEBUG0[] = {
+};
+static struct umr_bitfield mmHDP_DEBUG1[] = {
+};
+static struct umr_bitfield mmHDP_LAST_SURFACE_HIT[] = {
+	 { "LAST_SURFACE_HIT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_TILING_CONFIG[] = {
+	 { "BANK_SWAPS", 11, 13, &umr_bitfield_default },
+	 { "BANK_TILING", 4, 5, &umr_bitfield_default },
+	 { "GROUP_SIZE", 6, 7, &umr_bitfield_default },
+	 { "PIPE_TILING", 1, 3, &umr_bitfield_default },
+	 { "ROW_TILING", 8, 10, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_SC_MULTI_CHIP_CNTL[] = {
+	 { "LOG2_NUM_CHIPS", 0, 2, &umr_bitfield_default },
+	 { "MULTI_CHIP_TILE_SIZE", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_OUTSTANDING_REQ[] = {
+	 { "READ_REQ", 8, 15, &umr_bitfield_default },
+	 { "WRITE_REQ", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MISC_CNTL[] = {
+	 { "ADDRLIB_LINEAR_BYPASS", 20, 20, &umr_bitfield_default },
+	 { "FED_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "FLUSH_INVALIDATE_CACHE", 0, 0, &umr_bitfield_default },
+	 { "HDP_BIF_RDRET_CREDIT", 7, 10, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default },
+	 { "MULTIPLE_READS", 6, 6, &umr_bitfield_default },
+	 { "NO_SPLIT_ARRAY_LINEAR", 12, 12, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE_COUNT_1024", 5, 5, &umr_bitfield_default },
+	 { "READ_CACHE_INVALIDATE", 19, 19, &umr_bitfield_default },
+	 { "SIMULTANEOUS_READS_WRITES", 11, 11, &umr_bitfield_default },
+	 { "VM_ID", 1, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEM_POWER_LS[] = {
+	 { "LS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LS_HOLD", 7, 12, &umr_bitfield_default },
+	 { "LS_SETUP", 1, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_PREFETCH[] = {
+	 { "NONSURF_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_DIR", 3, 5, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_MAX_Z", 9, 19, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_NUM", 6, 8, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_PRI", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_CNTL[] = {
+	 { "MEMIO_ADDR_UPPER", 8, 13, &umr_bitfield_default },
+	 { "MEMIO_BE", 2, 5, &umr_bitfield_default },
+	 { "MEMIO_CLR_RD_ERROR", 15, 15, &umr_bitfield_default },
+	 { "MEMIO_CLR_WR_ERROR", 14, 14, &umr_bitfield_default },
+	 { "MEMIO_OP", 1, 1, &umr_bitfield_default },
+	 { "MEMIO_RD_STROBE", 7, 7, &umr_bitfield_default },
+	 { "MEMIO_SEND", 0, 0, &umr_bitfield_default },
+	 { "MEMIO_WR_STROBE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_ADDR[] = {
+	 { "MEMIO_ADDR_LOWER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_STATUS[] = {
+	 { "MEMIO_RD_ERROR", 3, 3, &umr_bitfield_default },
+	 { "MEMIO_RD_STATUS", 1, 1, &umr_bitfield_default },
+	 { "MEMIO_WR_ERROR", 2, 2, &umr_bitfield_default },
+	 { "MEMIO_WR_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_WR_DATA[] = {
+	 { "MEMIO_WR_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_RD_DATA[] = {
+	 { "MEMIO_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_FIRST[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_FLUSH[] = {
+	 { "D2H_FLUSH_ALTER_FLUSH_NUM", 18, 18, &umr_bitfield_default },
+	 { "D2H_FLUSH_FLUSH_NUM", 0, 3, &umr_bitfield_default },
+	 { "D2H_FLUSH_MBX_ADDR_SEL", 8, 10, &umr_bitfield_default },
+	 { "D2H_FLUSH_MBX_ENC_DATA", 4, 7, &umr_bitfield_default },
+	 { "D2H_FLUSH_RSVD_0", 19, 19, &umr_bitfield_default },
+	 { "D2H_FLUSH_RSVD_1", 20, 20, &umr_bitfield_default },
+	 { "D2H_FLUSH_SEND_HOST", 16, 16, &umr_bitfield_default },
+	 { "D2H_FLUSH_SEND_SIDE", 17, 17, &umr_bitfield_default },
+	 { "D2H_FLUSH_XPB_CLG", 11, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_BAR_UPDATE[] = {
+	 { "D2H_BAR_UPDATE_ADDR", 0, 15, &umr_bitfield_default },
+	 { "D2H_BAR_UPDATE_BAR_NUM", 20, 22, &umr_bitfield_default },
+	 { "D2H_BAR_UPDATE_FLUSH_NUM", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_7[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_8[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_9[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_10[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_11[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_12[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_13[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_14[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_15[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_16[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_17[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_18[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_19[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_20[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_21[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_22[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_23[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_24[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_25[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_26[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_27[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_28[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_29[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_30[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_31[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_32[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_33[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_34[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_LAST[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR_CFG[] = {
+	 { "P2P_BAR_CFG_ADDR_SIZE", 0, 3, &umr_bitfield_default },
+	 { "P2P_BAR_CFG_BAR_FROM", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_OFFSET[] = {
+	 { "P2P_MBX_OFFSET", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR0[] = {
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR1[] = {
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR2[] = {
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR3[] = {
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR4[] = {
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR5[] = {
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR6[] = {
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "VALID", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_MBX_MC_CFG[] = {
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_PRIV", 0, 0, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_SWAP", 1, 2, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_TRAN", 3, 3, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_MC_CFG[] = {
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_PRIV", 0, 0, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_SWAP", 1, 2, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_TRAN", 3, 3, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_VMID", 23, 26, &umr_bitfield_default },
+	 { "HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK", 20, 22, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_PRIV", 4, 4, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_SWAP", 5, 6, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_TRAN", 7, 7, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_VMID", 27, 30, &umr_bitfield_default },
+	 { "HDP_MC_CFG_XDP_HIGHER_PRI_THRESH", 14, 19, &umr_bitfield_default },
+	 { "HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HST_CFG[] = {
+	 { "HST_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
+	 { "HST_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_SID_CFG[] = {
+	 { "SID_CFG_FLNUM_MSB_SEL", 3, 4, &umr_bitfield_default },
+	 { "SID_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
+	 { "SID_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_IPH_CFG[] = {
+	 { "HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING", 12, 12, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_P2P_RD_EN", 13, 13, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE", 0, 5, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE", 6, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_SRBM_CFG[] = {
+	 { "SRBM_CFG_REG_CLK_ENABLE_COUNT", 0, 5, &umr_bitfield_default },
+	 { "SRBM_CFG_REG_CLK_GATING_DIS", 6, 6, &umr_bitfield_default },
+	 { "SRBM_CFG_WAKE_DYN_CLK", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_CGTT_BLK_CTRL[] = {
+	 { "CGTT_BLK_CTRL_0_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_1_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_2_RSVD", 12, 29, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR0[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR1[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR2[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR3[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR4[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR5[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR6[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR7[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_FLUSH_ARMED_STS[] = {
+	 { "FLUSH_ARMED_STS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_FLUSH_CNTR0_STS[] = {
+	 { "FLUSH_CNTR0_STS", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_BUSY_STS[] = {
+	 { "BUSY_BITS", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_STICKY[] = {
+	 { "STICKY_STS", 0, 15, &umr_bitfield_default },
+	 { "STICKY_W1C", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_CHKN[] = {
+	 { "CHKN_0_RSVD", 0, 7, &umr_bitfield_default },
+	 { "CHKN_1_RSVD", 8, 15, &umr_bitfield_default },
+	 { "CHKN_2_RSVD", 16, 23, &umr_bitfield_default },
+	 { "CHKN_3_RSVD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_ADDR[] = {
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+	 { "STS", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_DATA[] = {
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+	 { "STS", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_MASK[] = {
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+	 { "STS", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_BARS_ADDR_39_36[] = {
+	 { "BAR0_ADDR_39_36", 0, 3, &umr_bitfield_default },
+	 { "BAR1_ADDR_39_36", 4, 7, &umr_bitfield_default },
+	 { "BAR2_ADDR_39_36", 8, 11, &umr_bitfield_default },
+	 { "BAR3_ADDR_39_36", 12, 15, &umr_bitfield_default },
+	 { "BAR4_ADDR_39_36", 16, 19, &umr_bitfield_default },
+	 { "BAR5_ADDR_39_36", 20, 23, &umr_bitfield_default },
+	 { "BAR6_ADDR_39_36", 24, 27, &umr_bitfield_default },
+	 { "BAR7_ADDR_39_36", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_FULL_DRAIN_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "RB_GPU_TS_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_TIMER", 9, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_RPTR[] = {
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR[] = {
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+	 { "RB_OVERFLOW", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_CNTL[] = {
+	 { "CLIENT_FIFO_HIGHWATER", 8, 9, &umr_bitfield_default },
+	 { "ENABLE_INTR", 0, 0, &umr_bitfield_default },
+	 { "MC_FIFO_HIGHWATER", 10, 14, &umr_bitfield_default },
+	 { "MC_SWAP", 1, 2, &umr_bitfield_default },
+	 { "MC_TRAN", 3, 3, &umr_bitfield_default },
+	 { "MC_VMID", 25, 28, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_CNT", 20, 24, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 15, 19, &umr_bitfield_default },
+	 { "RPTR_REARM", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_LEVEL_STATUS[] = {
+	 { "BIF_STATUS", 4, 4, &umr_bitfield_default },
+	 { "DC_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ROM_STATUS", 2, 2, &umr_bitfield_default },
+	 { "SRBM_STATUS", 3, 3, &umr_bitfield_default },
+	 { "XDMA_STATUS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_STATUS[] = {
+	 { "BIF_INTERRUPT_LINE", 10, 10, &umr_bitfield_default },
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_IDLE", 1, 1, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_PENDING", 8, 8, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_STALL", 9, 9, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 6, 6, &umr_bitfield_default },
+	 { "MC_WR_STALL", 7, 7, &umr_bitfield_default },
+	 { "RB_FULL_DRAIN", 4, 4, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_IDLE", 2, 2, &umr_bitfield_default },
+	 { "RB_OVERFLOW", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFMON_CNTL[] = {
+	 { "CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "CLEAR1", 9, 9, &umr_bitfield_default },
+	 { "ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "ENABLE1", 8, 8, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_ADVFAULT_CNTL[] = {
+	 { "NUM_FAULTS_DROPPED", 8, 15, &umr_bitfield_default },
+	 { "WAIT_TIMER", 16, 29, &umr_bitfield_default },
+	 { "WATERMARK_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "WATERMARK", 0, 2, &umr_bitfield_default },
+	 { "WATERMARK_REACHED", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MCIF_CONFIG[] = {
+	 { "MC_REQ_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CONFIG[] = {
+	 { "CP_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "CP_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_CONFIG[] = {
+	 { "VCE_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "VCE_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CONFIG[] = {
+	 { "UVD_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "UVD_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX_CLIENTCONFIG[] = {
+	 { "CP_CLIENT0", 0, 2, &umr_bitfield_default },
+	 { "CP_CLIENT1", 3, 5, &umr_bitfield_default },
+	 { "CP_CLIENT2", 6, 8, &umr_bitfield_default },
+	 { "CP_CLIENT3", 9, 11, &umr_bitfield_default },
+	 { "UVD_CLIENT0", 15, 17, &umr_bitfield_default },
+	 { "VCE_CLIENT0", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX[] = {
+	 { "HOSTPORT", 8, 15, &umr_bitfield_default },
+	 { "SIDEPORT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX_CONTROL[] = {
+	 { "HOSTPORT_ENABLE", 8, 15, &umr_bitfield_default },
+	 { "SIDEPORT_ENABLE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DRM_ID_STRAPS[] = {
+	 { "ATI_REV_ID", 28, 31, &umr_bitfield_default },
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_TEST_DEBUG_INDEX[] = {
+	 { "DC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_TEST_DEBUG_DATA[] = {
+	 { "DC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/oss10_regs.i b/src/lib/ip/oss10_regs.i
new file mode 100644
index 0000000..796bfbe
--- /dev/null
+++ b/src/lib/ip/oss10_regs.i
@@ -0,0 +1,246 @@
+	{ "ixDH_TEST", REG_SMC, 0x0000, &ixDH_TEST[0], sizeof(ixDH_TEST)/sizeof(ixDH_TEST[0]), 0, 0 },
+	{ "ixKHFS0", REG_SMC, 0x0004, &ixKHFS0[0], sizeof(ixKHFS0)/sizeof(ixKHFS0[0]), 0, 0 },
+	{ "ixKHFS1", REG_SMC, 0x0008, &ixKHFS1[0], sizeof(ixKHFS1)/sizeof(ixKHFS1[0]), 0, 0 },
+	{ "ixKHFS2", REG_SMC, 0x000C, &ixKHFS2[0], sizeof(ixKHFS2)/sizeof(ixKHFS2[0]), 0, 0 },
+	{ "ixKHFS3", REG_SMC, 0x0010, &ixKHFS3[0], sizeof(ixKHFS3)/sizeof(ixKHFS3[0]), 0, 0 },
+	{ "ixKSESSION0", REG_SMC, 0x0014, &ixKSESSION0[0], sizeof(ixKSESSION0)/sizeof(ixKSESSION0[0]), 0, 0 },
+	{ "ixKSESSION1", REG_SMC, 0x0018, &ixKSESSION1[0], sizeof(ixKSESSION1)/sizeof(ixKSESSION1[0]), 0, 0 },
+	{ "ixKSESSION2", REG_SMC, 0x001C, &ixKSESSION2[0], sizeof(ixKSESSION2)/sizeof(ixKSESSION2[0]), 0, 0 },
+	{ "ixKSESSION3", REG_SMC, 0x0020, &ixKSESSION3[0], sizeof(ixKSESSION3)/sizeof(ixKSESSION3[0]), 0, 0 },
+	{ "ixKSIG0", REG_SMC, 0x0024, &ixKSIG0[0], sizeof(ixKSIG0)/sizeof(ixKSIG0[0]), 0, 0 },
+	{ "ixKSIG1", REG_SMC, 0x0028, &ixKSIG1[0], sizeof(ixKSIG1)/sizeof(ixKSIG1[0]), 0, 0 },
+	{ "ixKSIG2", REG_SMC, 0x002C, &ixKSIG2[0], sizeof(ixKSIG2)/sizeof(ixKSIG2[0]), 0, 0 },
+	{ "ixKSIG3", REG_SMC, 0x0030, &ixKSIG3[0], sizeof(ixKSIG3)/sizeof(ixKSIG3[0]), 0, 0 },
+	{ "ixEXP0", REG_SMC, 0x0034, &ixEXP0[0], sizeof(ixEXP0)/sizeof(ixEXP0[0]), 0, 0 },
+	{ "ixEXP1", REG_SMC, 0x0038, &ixEXP1[0], sizeof(ixEXP1)/sizeof(ixEXP1[0]), 0, 0 },
+	{ "ixEXP2", REG_SMC, 0x003C, &ixEXP2[0], sizeof(ixEXP2)/sizeof(ixEXP2[0]), 0, 0 },
+	{ "ixEXP3", REG_SMC, 0x0040, &ixEXP3[0], sizeof(ixEXP3)/sizeof(ixEXP3[0]), 0, 0 },
+	{ "ixEXP4", REG_SMC, 0x0044, &ixEXP4[0], sizeof(ixEXP4)/sizeof(ixEXP4[0]), 0, 0 },
+	{ "ixEXP5", REG_SMC, 0x0048, &ixEXP5[0], sizeof(ixEXP5)/sizeof(ixEXP5[0]), 0, 0 },
+	{ "ixEXP6", REG_SMC, 0x004C, &ixEXP6[0], sizeof(ixEXP6)/sizeof(ixEXP6[0]), 0, 0 },
+	{ "ixEXP7", REG_SMC, 0x0050, &ixEXP7[0], sizeof(ixEXP7)/sizeof(ixEXP7[0]), 0, 0 },
+	{ "ixLX0", REG_SMC, 0x0054, &ixLX0[0], sizeof(ixLX0)/sizeof(ixLX0[0]), 0, 0 },
+	{ "ixLX1", REG_SMC, 0x0058, &ixLX1[0], sizeof(ixLX1)/sizeof(ixLX1[0]), 0, 0 },
+	{ "ixLX2", REG_SMC, 0x005C, &ixLX2[0], sizeof(ixLX2)/sizeof(ixLX2[0]), 0, 0 },
+	{ "ixLX3", REG_SMC, 0x0060, &ixLX3[0], sizeof(ixLX3)/sizeof(ixLX3[0]), 0, 0 },
+	{ "ixCLIENT2_K0", REG_SMC, 0x01B4, &ixCLIENT2_K0[0], sizeof(ixCLIENT2_K0)/sizeof(ixCLIENT2_K0[0]), 0, 0 },
+	{ "ixCLIENT2_K1", REG_SMC, 0x01B8, &ixCLIENT2_K1[0], sizeof(ixCLIENT2_K1)/sizeof(ixCLIENT2_K1[0]), 0, 0 },
+	{ "ixCLIENT2_K2", REG_SMC, 0x01BC, &ixCLIENT2_K2[0], sizeof(ixCLIENT2_K2)/sizeof(ixCLIENT2_K2[0]), 0, 0 },
+	{ "ixCLIENT2_K3", REG_SMC, 0x01C0, &ixCLIENT2_K3[0], sizeof(ixCLIENT2_K3)/sizeof(ixCLIENT2_K3[0]), 0, 0 },
+	{ "ixCLIENT2_CK0", REG_SMC, 0x01C4, &ixCLIENT2_CK0[0], sizeof(ixCLIENT2_CK0)/sizeof(ixCLIENT2_CK0[0]), 0, 0 },
+	{ "ixCLIENT2_CK1", REG_SMC, 0x01C8, &ixCLIENT2_CK1[0], sizeof(ixCLIENT2_CK1)/sizeof(ixCLIENT2_CK1[0]), 0, 0 },
+	{ "ixCLIENT2_CK2", REG_SMC, 0x01CC, &ixCLIENT2_CK2[0], sizeof(ixCLIENT2_CK2)/sizeof(ixCLIENT2_CK2[0]), 0, 0 },
+	{ "ixCLIENT2_CK3", REG_SMC, 0x01D0, &ixCLIENT2_CK3[0], sizeof(ixCLIENT2_CK3)/sizeof(ixCLIENT2_CK3[0]), 0, 0 },
+	{ "ixCLIENT2_CD0", REG_SMC, 0x01D4, &ixCLIENT2_CD0[0], sizeof(ixCLIENT2_CD0)/sizeof(ixCLIENT2_CD0[0]), 0, 0 },
+	{ "ixCLIENT2_CD1", REG_SMC, 0x01D8, &ixCLIENT2_CD1[0], sizeof(ixCLIENT2_CD1)/sizeof(ixCLIENT2_CD1[0]), 0, 0 },
+	{ "ixCLIENT2_CD2", REG_SMC, 0x01DC, &ixCLIENT2_CD2[0], sizeof(ixCLIENT2_CD2)/sizeof(ixCLIENT2_CD2[0]), 0, 0 },
+	{ "ixCLIENT2_CD3", REG_SMC, 0x01E0, &ixCLIENT2_CD3[0], sizeof(ixCLIENT2_CD3)/sizeof(ixCLIENT2_CD3[0]), 0, 0 },
+	{ "ixCLIENT2_BM", REG_SMC, 0x01E4, &ixCLIENT2_BM[0], sizeof(ixCLIENT2_BM)/sizeof(ixCLIENT2_BM[0]), 0, 0 },
+	{ "ixCLIENT2_OFFSET", REG_SMC, 0x01E8, &ixCLIENT2_OFFSET[0], sizeof(ixCLIENT2_OFFSET)/sizeof(ixCLIENT2_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT2_STATUS", REG_SMC, 0x01EC, &ixCLIENT2_STATUS[0], sizeof(ixCLIENT2_STATUS)/sizeof(ixCLIENT2_STATUS[0]), 0, 0 },
+	{ "ixCLIENT0_K0", REG_SMC, 0x01F0, &ixCLIENT0_K0[0], sizeof(ixCLIENT0_K0)/sizeof(ixCLIENT0_K0[0]), 0, 0 },
+	{ "ixCLIENT0_K1", REG_SMC, 0x01F4, &ixCLIENT0_K1[0], sizeof(ixCLIENT0_K1)/sizeof(ixCLIENT0_K1[0]), 0, 0 },
+	{ "ixCLIENT0_K2", REG_SMC, 0x01F8, &ixCLIENT0_K2[0], sizeof(ixCLIENT0_K2)/sizeof(ixCLIENT0_K2[0]), 0, 0 },
+	{ "ixCLIENT0_K3", REG_SMC, 0x01FC, &ixCLIENT0_K3[0], sizeof(ixCLIENT0_K3)/sizeof(ixCLIENT0_K3[0]), 0, 0 },
+	{ "ixCLIENT0_CK0", REG_SMC, 0x0200, &ixCLIENT0_CK0[0], sizeof(ixCLIENT0_CK0)/sizeof(ixCLIENT0_CK0[0]), 0, 0 },
+	{ "ixCLIENT0_CK1", REG_SMC, 0x0204, &ixCLIENT0_CK1[0], sizeof(ixCLIENT0_CK1)/sizeof(ixCLIENT0_CK1[0]), 0, 0 },
+	{ "ixCLIENT0_CK2", REG_SMC, 0x0208, &ixCLIENT0_CK2[0], sizeof(ixCLIENT0_CK2)/sizeof(ixCLIENT0_CK2[0]), 0, 0 },
+	{ "ixCLIENT0_CK3", REG_SMC, 0x020C, &ixCLIENT0_CK3[0], sizeof(ixCLIENT0_CK3)/sizeof(ixCLIENT0_CK3[0]), 0, 0 },
+	{ "ixCLIENT0_CD0", REG_SMC, 0x0210, &ixCLIENT0_CD0[0], sizeof(ixCLIENT0_CD0)/sizeof(ixCLIENT0_CD0[0]), 0, 0 },
+	{ "ixCLIENT0_CD1", REG_SMC, 0x0214, &ixCLIENT0_CD1[0], sizeof(ixCLIENT0_CD1)/sizeof(ixCLIENT0_CD1[0]), 0, 0 },
+	{ "ixCLIENT0_CD2", REG_SMC, 0x0218, &ixCLIENT0_CD2[0], sizeof(ixCLIENT0_CD2)/sizeof(ixCLIENT0_CD2[0]), 0, 0 },
+	{ "ixCLIENT0_CD3", REG_SMC, 0x021C, &ixCLIENT0_CD3[0], sizeof(ixCLIENT0_CD3)/sizeof(ixCLIENT0_CD3[0]), 0, 0 },
+	{ "ixCLIENT0_BM", REG_SMC, 0x0220, &ixCLIENT0_BM[0], sizeof(ixCLIENT0_BM)/sizeof(ixCLIENT0_BM[0]), 0, 0 },
+	{ "ixCLIENT0_OFFSET", REG_SMC, 0x0224, &ixCLIENT0_OFFSET[0], sizeof(ixCLIENT0_OFFSET)/sizeof(ixCLIENT0_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT0_STATUS", REG_SMC, 0x0228, &ixCLIENT0_STATUS[0], sizeof(ixCLIENT0_STATUS)/sizeof(ixCLIENT0_STATUS[0]), 0, 0 },
+	{ "ixCLIENT1_K0", REG_SMC, 0x022C, &ixCLIENT1_K0[0], sizeof(ixCLIENT1_K0)/sizeof(ixCLIENT1_K0[0]), 0, 0 },
+	{ "ixCLIENT1_K1", REG_SMC, 0x0230, &ixCLIENT1_K1[0], sizeof(ixCLIENT1_K1)/sizeof(ixCLIENT1_K1[0]), 0, 0 },
+	{ "ixCLIENT1_K2", REG_SMC, 0x0234, &ixCLIENT1_K2[0], sizeof(ixCLIENT1_K2)/sizeof(ixCLIENT1_K2[0]), 0, 0 },
+	{ "ixCLIENT1_K3", REG_SMC, 0x0238, &ixCLIENT1_K3[0], sizeof(ixCLIENT1_K3)/sizeof(ixCLIENT1_K3[0]), 0, 0 },
+	{ "ixCLIENT1_CK0", REG_SMC, 0x023C, &ixCLIENT1_CK0[0], sizeof(ixCLIENT1_CK0)/sizeof(ixCLIENT1_CK0[0]), 0, 0 },
+	{ "ixCLIENT1_CK1", REG_SMC, 0x0240, &ixCLIENT1_CK1[0], sizeof(ixCLIENT1_CK1)/sizeof(ixCLIENT1_CK1[0]), 0, 0 },
+	{ "ixCLIENT1_CK2", REG_SMC, 0x0244, &ixCLIENT1_CK2[0], sizeof(ixCLIENT1_CK2)/sizeof(ixCLIENT1_CK2[0]), 0, 0 },
+	{ "ixCLIENT1_CK3", REG_SMC, 0x0248, &ixCLIENT1_CK3[0], sizeof(ixCLIENT1_CK3)/sizeof(ixCLIENT1_CK3[0]), 0, 0 },
+	{ "ixCLIENT1_CD0", REG_SMC, 0x024C, &ixCLIENT1_CD0[0], sizeof(ixCLIENT1_CD0)/sizeof(ixCLIENT1_CD0[0]), 0, 0 },
+	{ "ixCLIENT1_CD1", REG_SMC, 0x0250, &ixCLIENT1_CD1[0], sizeof(ixCLIENT1_CD1)/sizeof(ixCLIENT1_CD1[0]), 0, 0 },
+	{ "ixCLIENT1_CD2", REG_SMC, 0x0254, &ixCLIENT1_CD2[0], sizeof(ixCLIENT1_CD2)/sizeof(ixCLIENT1_CD2[0]), 0, 0 },
+	{ "ixCLIENT1_CD3", REG_SMC, 0x0258, &ixCLIENT1_CD3[0], sizeof(ixCLIENT1_CD3)/sizeof(ixCLIENT1_CD3[0]), 0, 0 },
+	{ "ixCLIENT1_BM", REG_SMC, 0x025C, &ixCLIENT1_BM[0], sizeof(ixCLIENT1_BM)/sizeof(ixCLIENT1_BM[0]), 0, 0 },
+	{ "ixCLIENT1_OFFSET", REG_SMC, 0x0260, &ixCLIENT1_OFFSET[0], sizeof(ixCLIENT1_OFFSET)/sizeof(ixCLIENT1_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT1_PORT_STATUS", REG_SMC, 0x0264, &ixCLIENT1_PORT_STATUS[0], sizeof(ixCLIENT1_PORT_STATUS)/sizeof(ixCLIENT1_PORT_STATUS[0]), 0, 0 },
+	{ "ixKEFUSE0", REG_SMC, 0x0268, &ixKEFUSE0[0], sizeof(ixKEFUSE0)/sizeof(ixKEFUSE0[0]), 0, 0 },
+	{ "ixKEFUSE1", REG_SMC, 0x026C, &ixKEFUSE1[0], sizeof(ixKEFUSE1)/sizeof(ixKEFUSE1[0]), 0, 0 },
+	{ "ixKEFUSE2", REG_SMC, 0x0270, &ixKEFUSE2[0], sizeof(ixKEFUSE2)/sizeof(ixKEFUSE2[0]), 0, 0 },
+	{ "ixKEFUSE3", REG_SMC, 0x0274, &ixKEFUSE3[0], sizeof(ixKEFUSE3)/sizeof(ixKEFUSE3[0]), 0, 0 },
+	{ "ixHFS_SEED0", REG_SMC, 0x0278, &ixHFS_SEED0[0], sizeof(ixHFS_SEED0)/sizeof(ixHFS_SEED0[0]), 0, 0 },
+	{ "ixHFS_SEED1", REG_SMC, 0x027C, &ixHFS_SEED1[0], sizeof(ixHFS_SEED1)/sizeof(ixHFS_SEED1[0]), 0, 0 },
+	{ "ixHFS_SEED2", REG_SMC, 0x0280, &ixHFS_SEED2[0], sizeof(ixHFS_SEED2)/sizeof(ixHFS_SEED2[0]), 0, 0 },
+	{ "ixHFS_SEED3", REG_SMC, 0x0284, &ixHFS_SEED3[0], sizeof(ixHFS_SEED3)/sizeof(ixHFS_SEED3[0]), 0, 0 },
+	{ "ixRINGOSC_MASK", REG_SMC, 0x0288, &ixRINGOSC_MASK[0], sizeof(ixRINGOSC_MASK)/sizeof(ixRINGOSC_MASK[0]), 0, 0 },
+	{ "ixCLIENT0_OFFSET_HI", REG_SMC, 0x0290, &ixCLIENT0_OFFSET_HI[0], sizeof(ixCLIENT0_OFFSET_HI)/sizeof(ixCLIENT0_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT1_OFFSET_HI", REG_SMC, 0x0294, &ixCLIENT1_OFFSET_HI[0], sizeof(ixCLIENT1_OFFSET_HI)/sizeof(ixCLIENT1_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT2_OFFSET_HI", REG_SMC, 0x0298, &ixCLIENT2_OFFSET_HI[0], sizeof(ixCLIENT2_OFFSET_HI)/sizeof(ixCLIENT2_OFFSET_HI[0]), 0, 0 },
+	{ "ixSPU_PORT_STATUS", REG_SMC, 0x029C, &ixSPU_PORT_STATUS[0], sizeof(ixSPU_PORT_STATUS)/sizeof(ixSPU_PORT_STATUS[0]), 0, 0 },
+	{ "ixCLIENT3_OFFSET_HI", REG_SMC, 0x02A0, &ixCLIENT3_OFFSET_HI[0], sizeof(ixCLIENT3_OFFSET_HI)/sizeof(ixCLIENT3_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT3_K0", REG_SMC, 0x02A4, &ixCLIENT3_K0[0], sizeof(ixCLIENT3_K0)/sizeof(ixCLIENT3_K0[0]), 0, 0 },
+	{ "ixCLIENT3_K1", REG_SMC, 0x02A8, &ixCLIENT3_K1[0], sizeof(ixCLIENT3_K1)/sizeof(ixCLIENT3_K1[0]), 0, 0 },
+	{ "ixCLIENT3_K2", REG_SMC, 0x02AC, &ixCLIENT3_K2[0], sizeof(ixCLIENT3_K2)/sizeof(ixCLIENT3_K2[0]), 0, 0 },
+	{ "ixCLIENT3_K3", REG_SMC, 0x02B0, &ixCLIENT3_K3[0], sizeof(ixCLIENT3_K3)/sizeof(ixCLIENT3_K3[0]), 0, 0 },
+	{ "ixCLIENT3_CK0", REG_SMC, 0x02B4, &ixCLIENT3_CK0[0], sizeof(ixCLIENT3_CK0)/sizeof(ixCLIENT3_CK0[0]), 0, 0 },
+	{ "ixCLIENT3_CK1", REG_SMC, 0x02B8, &ixCLIENT3_CK1[0], sizeof(ixCLIENT3_CK1)/sizeof(ixCLIENT3_CK1[0]), 0, 0 },
+	{ "ixCLIENT3_CK2", REG_SMC, 0x02BC, &ixCLIENT3_CK2[0], sizeof(ixCLIENT3_CK2)/sizeof(ixCLIENT3_CK2[0]), 0, 0 },
+	{ "ixCLIENT3_CK3", REG_SMC, 0x02C0, &ixCLIENT3_CK3[0], sizeof(ixCLIENT3_CK3)/sizeof(ixCLIENT3_CK3[0]), 0, 0 },
+	{ "ixCLIENT3_CD0", REG_SMC, 0x02C4, &ixCLIENT3_CD0[0], sizeof(ixCLIENT3_CD0)/sizeof(ixCLIENT3_CD0[0]), 0, 0 },
+	{ "ixCLIENT3_CD1", REG_SMC, 0x02C8, &ixCLIENT3_CD1[0], sizeof(ixCLIENT3_CD1)/sizeof(ixCLIENT3_CD1[0]), 0, 0 },
+	{ "ixCLIENT3_CD2", REG_SMC, 0x02CC, &ixCLIENT3_CD2[0], sizeof(ixCLIENT3_CD2)/sizeof(ixCLIENT3_CD2[0]), 0, 0 },
+	{ "ixCLIENT3_CD3", REG_SMC, 0x02D0, &ixCLIENT3_CD3[0], sizeof(ixCLIENT3_CD3)/sizeof(ixCLIENT3_CD3[0]), 0, 0 },
+	{ "ixCLIENT3_BM", REG_SMC, 0x02D4, &ixCLIENT3_BM[0], sizeof(ixCLIENT3_BM)/sizeof(ixCLIENT3_BM[0]), 0, 0 },
+	{ "ixCLIENT3_OFFSET", REG_SMC, 0x02D8, &ixCLIENT3_OFFSET[0], sizeof(ixCLIENT3_OFFSET)/sizeof(ixCLIENT3_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT3_STATUS", REG_SMC, 0x02DC, &ixCLIENT3_STATUS[0], sizeof(ixCLIENT3_STATUS)/sizeof(ixCLIENT3_STATUS[0]), 0, 0 },
+	{ "mmSRBM_CNTL", REG_MMIO, 0x0390, &mmSRBM_CNTL[0], sizeof(mmSRBM_CNTL)/sizeof(mmSRBM_CNTL[0]), 0, 0 },
+	{ "mmSRBM_GFX_CNTL", REG_MMIO, 0x0391, &mmSRBM_GFX_CNTL[0], sizeof(mmSRBM_GFX_CNTL)/sizeof(mmSRBM_GFX_CNTL[0]), 0, 0 },
+	{ "mmSRBM_STATUS2", REG_MMIO, 0x0393, &mmSRBM_STATUS2[0], sizeof(mmSRBM_STATUS2)/sizeof(mmSRBM_STATUS2[0]), 0, 0 },
+	{ "mmSRBM_STATUS", REG_MMIO, 0x0394, &mmSRBM_STATUS[0], sizeof(mmSRBM_STATUS)/sizeof(mmSRBM_STATUS[0]), 0, 0 },
+	{ "mmSRBM_CAM_INDEX", REG_MMIO, 0x0396, &mmSRBM_CAM_INDEX[0], sizeof(mmSRBM_CAM_INDEX)/sizeof(mmSRBM_CAM_INDEX[0]), 0, 0 },
+	{ "mmSRBM_CAM_DATA", REG_MMIO, 0x0397, &mmSRBM_CAM_DATA[0], sizeof(mmSRBM_CAM_DATA)/sizeof(mmSRBM_CAM_DATA[0]), 0, 0 },
+	{ "mmSRBM_SOFT_RESET", REG_MMIO, 0x0398, &mmSRBM_SOFT_RESET[0], sizeof(mmSRBM_SOFT_RESET)/sizeof(mmSRBM_SOFT_RESET[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_CNTL", REG_MMIO, 0x0399, &mmSRBM_DEBUG_CNTL[0], sizeof(mmSRBM_DEBUG_CNTL)/sizeof(mmSRBM_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_DATA", REG_MMIO, 0x039A, &mmSRBM_DEBUG_DATA[0], sizeof(mmSRBM_DEBUG_DATA)/sizeof(mmSRBM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmSRBM_CHIP_REVISION", REG_MMIO, 0x039B, &mmSRBM_CHIP_REVISION[0], sizeof(mmSRBM_CHIP_REVISION)/sizeof(mmSRBM_CHIP_REVISION[0]), 0, 0 },
+	{ "mmCC_SYS_RB_REDUNDANCY", REG_MMIO, 0x039F, NULL, 0, 0, 0 },
+	{ "mmCC_SYS_RB_BACKEND_DISABLE", REG_MMIO, 0x03A0, &mmCC_SYS_RB_BACKEND_DISABLE[0], sizeof(mmCC_SYS_RB_BACKEND_DISABLE)/sizeof(mmCC_SYS_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmGC_USER_SYS_RB_BACKEND_DISABLE", REG_MMIO, 0x03A1, &mmGC_USER_SYS_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_SYS_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_SYS_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmSRBM_DEBUG", REG_MMIO, 0x03A4, &mmSRBM_DEBUG[0], sizeof(mmSRBM_DEBUG)/sizeof(mmSRBM_DEBUG[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x03A5, &mmSRBM_DEBUG_SNAPSHOT[0], sizeof(mmSRBM_DEBUG_SNAPSHOT)/sizeof(mmSRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
+	{ "mmSRBM_READ_ERROR", REG_MMIO, 0x03A6, &mmSRBM_READ_ERROR[0], sizeof(mmSRBM_READ_ERROR)/sizeof(mmSRBM_READ_ERROR[0]), 0, 0 },
+	{ "mmSRBM_INT_CNTL", REG_MMIO, 0x03A8, &mmSRBM_INT_CNTL[0], sizeof(mmSRBM_INT_CNTL)/sizeof(mmSRBM_INT_CNTL[0]), 0, 0 },
+	{ "mmSRBM_INT_STATUS", REG_MMIO, 0x03A9, &mmSRBM_INT_STATUS[0], sizeof(mmSRBM_INT_STATUS)/sizeof(mmSRBM_INT_STATUS[0]), 0, 0 },
+	{ "mmSRBM_INT_ACK", REG_MMIO, 0x03AA, &mmSRBM_INT_ACK[0], sizeof(mmSRBM_INT_ACK)/sizeof(mmSRBM_INT_ACK[0]), 0, 0 },
+	{ "mmSRBM_MC_CLKEN_CNTL", REG_MMIO, 0x03B3, &mmSRBM_MC_CLKEN_CNTL[0], sizeof(mmSRBM_MC_CLKEN_CNTL)/sizeof(mmSRBM_MC_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_SYS_CLKEN_CNTL", REG_MMIO, 0x03B4, &mmSRBM_SYS_CLKEN_CNTL[0], sizeof(mmSRBM_SYS_CLKEN_CNTL)/sizeof(mmSRBM_SYS_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_VCE_CLKEN_CNTL", REG_MMIO, 0x03B5, &mmSRBM_VCE_CLKEN_CNTL[0], sizeof(mmSRBM_VCE_CLKEN_CNTL)/sizeof(mmSRBM_VCE_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_UVD_CLKEN_CNTL", REG_MMIO, 0x03B6, &mmSRBM_UVD_CLKEN_CNTL[0], sizeof(mmSRBM_UVD_CLKEN_CNTL)/sizeof(mmSRBM_UVD_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x03F8, &mmXDMA_MSTR_MEM_OVERFLOW_CNTL[0], sizeof(mmXDMA_MSTR_MEM_OVERFLOW_CNTL)/sizeof(mmXDMA_MSTR_MEM_OVERFLOW_CNTL[0]), 0, 0 },
+	{ "mmSRBM_PERFMON_CNTL", REG_MMIO, 0x0700, &mmSRBM_PERFMON_CNTL[0], sizeof(mmSRBM_PERFMON_CNTL)/sizeof(mmSRBM_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0x0701, &mmSRBM_PERFCOUNTER0_SELECT[0], sizeof(mmSRBM_PERFCOUNTER0_SELECT)/sizeof(mmSRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0x0702, &mmSRBM_PERFCOUNTER1_SELECT[0], sizeof(mmSRBM_PERFCOUNTER1_SELECT)/sizeof(mmSRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_LO", REG_MMIO, 0x0703, &mmSRBM_PERFCOUNTER0_LO[0], sizeof(mmSRBM_PERFCOUNTER0_LO)/sizeof(mmSRBM_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_HI", REG_MMIO, 0x0704, &mmSRBM_PERFCOUNTER0_HI[0], sizeof(mmSRBM_PERFCOUNTER0_HI)/sizeof(mmSRBM_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_LO", REG_MMIO, 0x0705, &mmSRBM_PERFCOUNTER1_LO[0], sizeof(mmSRBM_PERFCOUNTER1_LO)/sizeof(mmSRBM_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_HI", REG_MMIO, 0x0706, &mmSRBM_PERFCOUNTER1_HI[0], sizeof(mmSRBM_PERFCOUNTER1_HI)/sizeof(mmSRBM_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "mmHDP_HOST_PATH_CNTL", REG_MMIO, 0x0B00, &mmHDP_HOST_PATH_CNTL[0], sizeof(mmHDP_HOST_PATH_CNTL)/sizeof(mmHDP_HOST_PATH_CNTL[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_BASE", REG_MMIO, 0x0B01, &mmHDP_NONSURFACE_BASE[0], sizeof(mmHDP_NONSURFACE_BASE)/sizeof(mmHDP_NONSURFACE_BASE[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_INFO", REG_MMIO, 0x0B02, &mmHDP_NONSURFACE_INFO[0], sizeof(mmHDP_NONSURFACE_INFO)/sizeof(mmHDP_NONSURFACE_INFO[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_SIZE", REG_MMIO, 0x0B03, &mmHDP_NONSURFACE_SIZE[0], sizeof(mmHDP_NONSURFACE_SIZE)/sizeof(mmHDP_NONSURFACE_SIZE[0]), 0, 0 },
+	{ "mmHDP_NONSURF_FLAGS", REG_MMIO, 0x0BC9, &mmHDP_NONSURF_FLAGS[0], sizeof(mmHDP_NONSURF_FLAGS)/sizeof(mmHDP_NONSURF_FLAGS[0]), 0, 0 },
+	{ "mmHDP_NONSURF_FLAGS_CLR", REG_MMIO, 0x0BCA, &mmHDP_NONSURF_FLAGS_CLR[0], sizeof(mmHDP_NONSURF_FLAGS_CLR)/sizeof(mmHDP_NONSURF_FLAGS_CLR[0]), 0, 0 },
+	{ "mmHDP_SW_SEMAPHORE", REG_MMIO, 0x0BCB, &mmHDP_SW_SEMAPHORE[0], sizeof(mmHDP_SW_SEMAPHORE)/sizeof(mmHDP_SW_SEMAPHORE[0]), 0, 0 },
+	{ "mmHDP_DEBUG0", REG_MMIO, 0x0BCC, &mmHDP_DEBUG0[0], sizeof(mmHDP_DEBUG0)/sizeof(mmHDP_DEBUG0[0]), 0, 0 },
+	{ "mmHDP_DEBUG1", REG_MMIO, 0x0BCD, &mmHDP_DEBUG1[0], sizeof(mmHDP_DEBUG1)/sizeof(mmHDP_DEBUG1[0]), 0, 0 },
+	{ "mmHDP_LAST_SURFACE_HIT", REG_MMIO, 0x0BCE, &mmHDP_LAST_SURFACE_HIT[0], sizeof(mmHDP_LAST_SURFACE_HIT)/sizeof(mmHDP_LAST_SURFACE_HIT[0]), 0, 0 },
+	{ "mmHDP_TILING_CONFIG", REG_MMIO, 0x0BCF, &mmHDP_TILING_CONFIG[0], sizeof(mmHDP_TILING_CONFIG)/sizeof(mmHDP_TILING_CONFIG[0]), 0, 0 },
+	{ "mmHDP_SC_MULTI_CHIP_CNTL", REG_MMIO, 0x0BD0, &mmHDP_SC_MULTI_CHIP_CNTL[0], sizeof(mmHDP_SC_MULTI_CHIP_CNTL)/sizeof(mmHDP_SC_MULTI_CHIP_CNTL[0]), 0, 0 },
+	{ "mmHDP_OUTSTANDING_REQ", REG_MMIO, 0x0BD1, &mmHDP_OUTSTANDING_REQ[0], sizeof(mmHDP_OUTSTANDING_REQ)/sizeof(mmHDP_OUTSTANDING_REQ[0]), 0, 0 },
+	{ "mmHDP_ADDR_CONFIG", REG_MMIO, 0x0BD2, &mmHDP_ADDR_CONFIG[0], sizeof(mmHDP_ADDR_CONFIG)/sizeof(mmHDP_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmHDP_MISC_CNTL", REG_MMIO, 0x0BD3, &mmHDP_MISC_CNTL[0], sizeof(mmHDP_MISC_CNTL)/sizeof(mmHDP_MISC_CNTL[0]), 0, 0 },
+	{ "mmHDP_MEM_POWER_LS", REG_MMIO, 0x0BD4, &mmHDP_MEM_POWER_LS[0], sizeof(mmHDP_MEM_POWER_LS)/sizeof(mmHDP_MEM_POWER_LS[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_PREFETCH", REG_MMIO, 0x0BD5, &mmHDP_NONSURFACE_PREFETCH[0], sizeof(mmHDP_NONSURFACE_PREFETCH)/sizeof(mmHDP_NONSURFACE_PREFETCH[0]), 0, 0 },
+	{ "mmHDP_MEMIO_CNTL", REG_MMIO, 0x0BF6, &mmHDP_MEMIO_CNTL[0], sizeof(mmHDP_MEMIO_CNTL)/sizeof(mmHDP_MEMIO_CNTL[0]), 0, 0 },
+	{ "mmHDP_MEMIO_ADDR", REG_MMIO, 0x0BF7, &mmHDP_MEMIO_ADDR[0], sizeof(mmHDP_MEMIO_ADDR)/sizeof(mmHDP_MEMIO_ADDR[0]), 0, 0 },
+	{ "mmHDP_MEMIO_STATUS", REG_MMIO, 0x0BF8, &mmHDP_MEMIO_STATUS[0], sizeof(mmHDP_MEMIO_STATUS)/sizeof(mmHDP_MEMIO_STATUS[0]), 0, 0 },
+	{ "mmHDP_MEMIO_WR_DATA", REG_MMIO, 0x0BF9, &mmHDP_MEMIO_WR_DATA[0], sizeof(mmHDP_MEMIO_WR_DATA)/sizeof(mmHDP_MEMIO_WR_DATA[0]), 0, 0 },
+	{ "mmHDP_MEMIO_RD_DATA", REG_MMIO, 0x0BFA, &mmHDP_MEMIO_RD_DATA[0], sizeof(mmHDP_MEMIO_RD_DATA)/sizeof(mmHDP_MEMIO_RD_DATA[0]), 0, 0 },
+	{ "mmHDP_XDP_DIRECT2HDP_FIRST", REG_MMIO, 0x0C00, &mmHDP_XDP_DIRECT2HDP_FIRST[0], sizeof(mmHDP_XDP_DIRECT2HDP_FIRST)/sizeof(mmHDP_XDP_DIRECT2HDP_FIRST[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_FLUSH", REG_MMIO, 0x0C01, &mmHDP_XDP_D2H_FLUSH[0], sizeof(mmHDP_XDP_D2H_FLUSH)/sizeof(mmHDP_XDP_D2H_FLUSH[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_BAR_UPDATE", REG_MMIO, 0x0C02, &mmHDP_XDP_D2H_BAR_UPDATE[0], sizeof(mmHDP_XDP_D2H_BAR_UPDATE)/sizeof(mmHDP_XDP_D2H_BAR_UPDATE[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_3", REG_MMIO, 0x0C03, &mmHDP_XDP_D2H_RSVD_3[0], sizeof(mmHDP_XDP_D2H_RSVD_3)/sizeof(mmHDP_XDP_D2H_RSVD_3[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_4", REG_MMIO, 0x0C04, &mmHDP_XDP_D2H_RSVD_4[0], sizeof(mmHDP_XDP_D2H_RSVD_4)/sizeof(mmHDP_XDP_D2H_RSVD_4[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_5", REG_MMIO, 0x0C05, &mmHDP_XDP_D2H_RSVD_5[0], sizeof(mmHDP_XDP_D2H_RSVD_5)/sizeof(mmHDP_XDP_D2H_RSVD_5[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_6", REG_MMIO, 0x0C06, &mmHDP_XDP_D2H_RSVD_6[0], sizeof(mmHDP_XDP_D2H_RSVD_6)/sizeof(mmHDP_XDP_D2H_RSVD_6[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_7", REG_MMIO, 0x0C07, &mmHDP_XDP_D2H_RSVD_7[0], sizeof(mmHDP_XDP_D2H_RSVD_7)/sizeof(mmHDP_XDP_D2H_RSVD_7[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_8", REG_MMIO, 0x0C08, &mmHDP_XDP_D2H_RSVD_8[0], sizeof(mmHDP_XDP_D2H_RSVD_8)/sizeof(mmHDP_XDP_D2H_RSVD_8[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_9", REG_MMIO, 0x0C09, &mmHDP_XDP_D2H_RSVD_9[0], sizeof(mmHDP_XDP_D2H_RSVD_9)/sizeof(mmHDP_XDP_D2H_RSVD_9[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_10", REG_MMIO, 0x0C0A, &mmHDP_XDP_D2H_RSVD_10[0], sizeof(mmHDP_XDP_D2H_RSVD_10)/sizeof(mmHDP_XDP_D2H_RSVD_10[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_11", REG_MMIO, 0x0C0B, &mmHDP_XDP_D2H_RSVD_11[0], sizeof(mmHDP_XDP_D2H_RSVD_11)/sizeof(mmHDP_XDP_D2H_RSVD_11[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_12", REG_MMIO, 0x0C0C, &mmHDP_XDP_D2H_RSVD_12[0], sizeof(mmHDP_XDP_D2H_RSVD_12)/sizeof(mmHDP_XDP_D2H_RSVD_12[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_13", REG_MMIO, 0x0C0D, &mmHDP_XDP_D2H_RSVD_13[0], sizeof(mmHDP_XDP_D2H_RSVD_13)/sizeof(mmHDP_XDP_D2H_RSVD_13[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_14", REG_MMIO, 0x0C0E, &mmHDP_XDP_D2H_RSVD_14[0], sizeof(mmHDP_XDP_D2H_RSVD_14)/sizeof(mmHDP_XDP_D2H_RSVD_14[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_15", REG_MMIO, 0x0C0F, &mmHDP_XDP_D2H_RSVD_15[0], sizeof(mmHDP_XDP_D2H_RSVD_15)/sizeof(mmHDP_XDP_D2H_RSVD_15[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_16", REG_MMIO, 0x0C10, &mmHDP_XDP_D2H_RSVD_16[0], sizeof(mmHDP_XDP_D2H_RSVD_16)/sizeof(mmHDP_XDP_D2H_RSVD_16[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_17", REG_MMIO, 0x0C11, &mmHDP_XDP_D2H_RSVD_17[0], sizeof(mmHDP_XDP_D2H_RSVD_17)/sizeof(mmHDP_XDP_D2H_RSVD_17[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_18", REG_MMIO, 0x0C12, &mmHDP_XDP_D2H_RSVD_18[0], sizeof(mmHDP_XDP_D2H_RSVD_18)/sizeof(mmHDP_XDP_D2H_RSVD_18[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_19", REG_MMIO, 0x0C13, &mmHDP_XDP_D2H_RSVD_19[0], sizeof(mmHDP_XDP_D2H_RSVD_19)/sizeof(mmHDP_XDP_D2H_RSVD_19[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_20", REG_MMIO, 0x0C14, &mmHDP_XDP_D2H_RSVD_20[0], sizeof(mmHDP_XDP_D2H_RSVD_20)/sizeof(mmHDP_XDP_D2H_RSVD_20[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_21", REG_MMIO, 0x0C15, &mmHDP_XDP_D2H_RSVD_21[0], sizeof(mmHDP_XDP_D2H_RSVD_21)/sizeof(mmHDP_XDP_D2H_RSVD_21[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_22", REG_MMIO, 0x0C16, &mmHDP_XDP_D2H_RSVD_22[0], sizeof(mmHDP_XDP_D2H_RSVD_22)/sizeof(mmHDP_XDP_D2H_RSVD_22[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_23", REG_MMIO, 0x0C17, &mmHDP_XDP_D2H_RSVD_23[0], sizeof(mmHDP_XDP_D2H_RSVD_23)/sizeof(mmHDP_XDP_D2H_RSVD_23[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_24", REG_MMIO, 0x0C18, &mmHDP_XDP_D2H_RSVD_24[0], sizeof(mmHDP_XDP_D2H_RSVD_24)/sizeof(mmHDP_XDP_D2H_RSVD_24[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_25", REG_MMIO, 0x0C19, &mmHDP_XDP_D2H_RSVD_25[0], sizeof(mmHDP_XDP_D2H_RSVD_25)/sizeof(mmHDP_XDP_D2H_RSVD_25[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_26", REG_MMIO, 0x0C1A, &mmHDP_XDP_D2H_RSVD_26[0], sizeof(mmHDP_XDP_D2H_RSVD_26)/sizeof(mmHDP_XDP_D2H_RSVD_26[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_27", REG_MMIO, 0x0C1B, &mmHDP_XDP_D2H_RSVD_27[0], sizeof(mmHDP_XDP_D2H_RSVD_27)/sizeof(mmHDP_XDP_D2H_RSVD_27[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_28", REG_MMIO, 0x0C1C, &mmHDP_XDP_D2H_RSVD_28[0], sizeof(mmHDP_XDP_D2H_RSVD_28)/sizeof(mmHDP_XDP_D2H_RSVD_28[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_29", REG_MMIO, 0x0C1D, &mmHDP_XDP_D2H_RSVD_29[0], sizeof(mmHDP_XDP_D2H_RSVD_29)/sizeof(mmHDP_XDP_D2H_RSVD_29[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_30", REG_MMIO, 0x0C1E, &mmHDP_XDP_D2H_RSVD_30[0], sizeof(mmHDP_XDP_D2H_RSVD_30)/sizeof(mmHDP_XDP_D2H_RSVD_30[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_31", REG_MMIO, 0x0C1F, &mmHDP_XDP_D2H_RSVD_31[0], sizeof(mmHDP_XDP_D2H_RSVD_31)/sizeof(mmHDP_XDP_D2H_RSVD_31[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_32", REG_MMIO, 0x0C20, &mmHDP_XDP_D2H_RSVD_32[0], sizeof(mmHDP_XDP_D2H_RSVD_32)/sizeof(mmHDP_XDP_D2H_RSVD_32[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_33", REG_MMIO, 0x0C21, &mmHDP_XDP_D2H_RSVD_33[0], sizeof(mmHDP_XDP_D2H_RSVD_33)/sizeof(mmHDP_XDP_D2H_RSVD_33[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_34", REG_MMIO, 0x0C22, &mmHDP_XDP_D2H_RSVD_34[0], sizeof(mmHDP_XDP_D2H_RSVD_34)/sizeof(mmHDP_XDP_D2H_RSVD_34[0]), 0, 0 },
+	{ "mmHDP_XDP_DIRECT2HDP_LAST", REG_MMIO, 0x0C23, &mmHDP_XDP_DIRECT2HDP_LAST[0], sizeof(mmHDP_XDP_DIRECT2HDP_LAST)/sizeof(mmHDP_XDP_DIRECT2HDP_LAST[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR_CFG", REG_MMIO, 0x0C24, &mmHDP_XDP_P2P_BAR_CFG[0], sizeof(mmHDP_XDP_P2P_BAR_CFG)/sizeof(mmHDP_XDP_P2P_BAR_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_OFFSET", REG_MMIO, 0x0C25, &mmHDP_XDP_P2P_MBX_OFFSET[0], sizeof(mmHDP_XDP_P2P_MBX_OFFSET)/sizeof(mmHDP_XDP_P2P_MBX_OFFSET[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR0", REG_MMIO, 0x0C26, &mmHDP_XDP_P2P_MBX_ADDR0[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR0)/sizeof(mmHDP_XDP_P2P_MBX_ADDR0[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR1", REG_MMIO, 0x0C27, &mmHDP_XDP_P2P_MBX_ADDR1[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR1)/sizeof(mmHDP_XDP_P2P_MBX_ADDR1[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR2", REG_MMIO, 0x0C28, &mmHDP_XDP_P2P_MBX_ADDR2[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR2)/sizeof(mmHDP_XDP_P2P_MBX_ADDR2[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR3", REG_MMIO, 0x0C29, &mmHDP_XDP_P2P_MBX_ADDR3[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR3)/sizeof(mmHDP_XDP_P2P_MBX_ADDR3[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR4", REG_MMIO, 0x0C2A, &mmHDP_XDP_P2P_MBX_ADDR4[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR4)/sizeof(mmHDP_XDP_P2P_MBX_ADDR4[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR5", REG_MMIO, 0x0C2B, &mmHDP_XDP_P2P_MBX_ADDR5[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR5)/sizeof(mmHDP_XDP_P2P_MBX_ADDR5[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR6", REG_MMIO, 0x0C2C, &mmHDP_XDP_P2P_MBX_ADDR6[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR6)/sizeof(mmHDP_XDP_P2P_MBX_ADDR6[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_MBX_MC_CFG", REG_MMIO, 0x0C2D, &mmHDP_XDP_HDP_MBX_MC_CFG[0], sizeof(mmHDP_XDP_HDP_MBX_MC_CFG)/sizeof(mmHDP_XDP_HDP_MBX_MC_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_MC_CFG", REG_MMIO, 0x0C2E, &mmHDP_XDP_HDP_MC_CFG[0], sizeof(mmHDP_XDP_HDP_MC_CFG)/sizeof(mmHDP_XDP_HDP_MC_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HST_CFG", REG_MMIO, 0x0C2F, &mmHDP_XDP_HST_CFG[0], sizeof(mmHDP_XDP_HST_CFG)/sizeof(mmHDP_XDP_HST_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_SID_CFG", REG_MMIO, 0x0C30, &mmHDP_XDP_SID_CFG[0], sizeof(mmHDP_XDP_SID_CFG)/sizeof(mmHDP_XDP_SID_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_IPH_CFG", REG_MMIO, 0x0C31, &mmHDP_XDP_HDP_IPH_CFG[0], sizeof(mmHDP_XDP_HDP_IPH_CFG)/sizeof(mmHDP_XDP_HDP_IPH_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_SRBM_CFG", REG_MMIO, 0x0C32, &mmHDP_XDP_SRBM_CFG[0], sizeof(mmHDP_XDP_SRBM_CFG)/sizeof(mmHDP_XDP_SRBM_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_CGTT_BLK_CTRL", REG_MMIO, 0x0C33, &mmHDP_XDP_CGTT_BLK_CTRL[0], sizeof(mmHDP_XDP_CGTT_BLK_CTRL)/sizeof(mmHDP_XDP_CGTT_BLK_CTRL[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR0", REG_MMIO, 0x0C34, &mmHDP_XDP_P2P_BAR0[0], sizeof(mmHDP_XDP_P2P_BAR0)/sizeof(mmHDP_XDP_P2P_BAR0[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR1", REG_MMIO, 0x0C35, &mmHDP_XDP_P2P_BAR1[0], sizeof(mmHDP_XDP_P2P_BAR1)/sizeof(mmHDP_XDP_P2P_BAR1[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR2", REG_MMIO, 0x0C36, &mmHDP_XDP_P2P_BAR2[0], sizeof(mmHDP_XDP_P2P_BAR2)/sizeof(mmHDP_XDP_P2P_BAR2[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR3", REG_MMIO, 0x0C37, &mmHDP_XDP_P2P_BAR3[0], sizeof(mmHDP_XDP_P2P_BAR3)/sizeof(mmHDP_XDP_P2P_BAR3[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR4", REG_MMIO, 0x0C38, &mmHDP_XDP_P2P_BAR4[0], sizeof(mmHDP_XDP_P2P_BAR4)/sizeof(mmHDP_XDP_P2P_BAR4[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR5", REG_MMIO, 0x0C39, &mmHDP_XDP_P2P_BAR5[0], sizeof(mmHDP_XDP_P2P_BAR5)/sizeof(mmHDP_XDP_P2P_BAR5[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR6", REG_MMIO, 0x0C3A, &mmHDP_XDP_P2P_BAR6[0], sizeof(mmHDP_XDP_P2P_BAR6)/sizeof(mmHDP_XDP_P2P_BAR6[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR7", REG_MMIO, 0x0C3B, &mmHDP_XDP_P2P_BAR7[0], sizeof(mmHDP_XDP_P2P_BAR7)/sizeof(mmHDP_XDP_P2P_BAR7[0]), 0, 0 },
+	{ "mmHDP_XDP_FLUSH_ARMED_STS", REG_MMIO, 0x0C3C, &mmHDP_XDP_FLUSH_ARMED_STS[0], sizeof(mmHDP_XDP_FLUSH_ARMED_STS)/sizeof(mmHDP_XDP_FLUSH_ARMED_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_FLUSH_CNTR0_STS", REG_MMIO, 0x0C3D, &mmHDP_XDP_FLUSH_CNTR0_STS[0], sizeof(mmHDP_XDP_FLUSH_CNTR0_STS)/sizeof(mmHDP_XDP_FLUSH_CNTR0_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_BUSY_STS", REG_MMIO, 0x0C3E, &mmHDP_XDP_BUSY_STS[0], sizeof(mmHDP_XDP_BUSY_STS)/sizeof(mmHDP_XDP_BUSY_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_STICKY", REG_MMIO, 0x0C3F, &mmHDP_XDP_STICKY[0], sizeof(mmHDP_XDP_STICKY)/sizeof(mmHDP_XDP_STICKY[0]), 0, 0 },
+	{ "mmHDP_XDP_CHKN", REG_MMIO, 0x0C40, &mmHDP_XDP_CHKN[0], sizeof(mmHDP_XDP_CHKN)/sizeof(mmHDP_XDP_CHKN[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_ADDR", REG_MMIO, 0x0C41, &mmHDP_XDP_DBG_ADDR[0], sizeof(mmHDP_XDP_DBG_ADDR)/sizeof(mmHDP_XDP_DBG_ADDR[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_DATA", REG_MMIO, 0x0C42, &mmHDP_XDP_DBG_DATA[0], sizeof(mmHDP_XDP_DBG_DATA)/sizeof(mmHDP_XDP_DBG_DATA[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_MASK", REG_MMIO, 0x0C43, &mmHDP_XDP_DBG_MASK[0], sizeof(mmHDP_XDP_DBG_MASK)/sizeof(mmHDP_XDP_DBG_MASK[0]), 0, 0 },
+	{ "mmHDP_XDP_BARS_ADDR_39_36", REG_MMIO, 0x0C44, &mmHDP_XDP_BARS_ADDR_39_36[0], sizeof(mmHDP_XDP_BARS_ADDR_39_36)/sizeof(mmHDP_XDP_BARS_ADDR_39_36[0]), 0, 0 },
+	{ "mmIH_RB_CNTL", REG_MMIO, 0x0F80, &mmIH_RB_CNTL[0], sizeof(mmIH_RB_CNTL)/sizeof(mmIH_RB_CNTL[0]), 0, 0 },
+	{ "mmIH_RB_BASE", REG_MMIO, 0x0F81, &mmIH_RB_BASE[0], sizeof(mmIH_RB_BASE)/sizeof(mmIH_RB_BASE[0]), 0, 0 },
+	{ "mmIH_RB_RPTR", REG_MMIO, 0x0F82, &mmIH_RB_RPTR[0], sizeof(mmIH_RB_RPTR)/sizeof(mmIH_RB_RPTR[0]), 0, 0 },
+	{ "mmIH_RB_WPTR", REG_MMIO, 0x0F83, &mmIH_RB_WPTR[0], sizeof(mmIH_RB_WPTR)/sizeof(mmIH_RB_WPTR[0]), 0, 0 },
+	{ "mmIH_RB_WPTR_ADDR_HI", REG_MMIO, 0x0F84, &mmIH_RB_WPTR_ADDR_HI[0], sizeof(mmIH_RB_WPTR_ADDR_HI)/sizeof(mmIH_RB_WPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmIH_RB_WPTR_ADDR_LO", REG_MMIO, 0x0F85, &mmIH_RB_WPTR_ADDR_LO[0], sizeof(mmIH_RB_WPTR_ADDR_LO)/sizeof(mmIH_RB_WPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmIH_CNTL", REG_MMIO, 0x0F86, &mmIH_CNTL[0], sizeof(mmIH_CNTL)/sizeof(mmIH_CNTL[0]), 0, 0 },
+	{ "mmIH_LEVEL_STATUS", REG_MMIO, 0x0F87, &mmIH_LEVEL_STATUS[0], sizeof(mmIH_LEVEL_STATUS)/sizeof(mmIH_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmIH_STATUS", REG_MMIO, 0x0F88, &mmIH_STATUS[0], sizeof(mmIH_STATUS)/sizeof(mmIH_STATUS[0]), 0, 0 },
+	{ "mmIH_PERFMON_CNTL", REG_MMIO, 0x0F89, &mmIH_PERFMON_CNTL[0], sizeof(mmIH_PERFMON_CNTL)/sizeof(mmIH_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmIH_PERFCOUNTER0_RESULT", REG_MMIO, 0x0F8A, &mmIH_PERFCOUNTER0_RESULT[0], sizeof(mmIH_PERFCOUNTER0_RESULT)/sizeof(mmIH_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmIH_PERFCOUNTER1_RESULT", REG_MMIO, 0x0F8B, &mmIH_PERFCOUNTER1_RESULT[0], sizeof(mmIH_PERFCOUNTER1_RESULT)/sizeof(mmIH_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmIH_ADVFAULT_CNTL", REG_MMIO, 0x0F8C, &mmIH_ADVFAULT_CNTL[0], sizeof(mmIH_ADVFAULT_CNTL)/sizeof(mmIH_ADVFAULT_CNTL[0]), 0, 0 },
+	{ "mmSEM_MCIF_CONFIG", REG_MMIO, 0x0F90, &mmSEM_MCIF_CONFIG[0], sizeof(mmSEM_MCIF_CONFIG)/sizeof(mmSEM_MCIF_CONFIG[0]), 0, 0 },
+	{ "mmCP_CONFIG", REG_MMIO, 0x0F92, &mmCP_CONFIG[0], sizeof(mmCP_CONFIG)/sizeof(mmCP_CONFIG[0]), 0, 0 },
+	{ "mmVCE_CONFIG", REG_MMIO, 0x0F94, &mmVCE_CONFIG[0], sizeof(mmVCE_CONFIG)/sizeof(mmVCE_CONFIG[0]), 0, 0 },
+	{ "mmUVD_CONFIG", REG_MMIO, 0x0F98, &mmUVD_CONFIG[0], sizeof(mmUVD_CONFIG)/sizeof(mmUVD_CONFIG[0]), 0, 0 },
+	{ "mmSEM_MAILBOX_CLIENTCONFIG", REG_MMIO, 0x0F9A, &mmSEM_MAILBOX_CLIENTCONFIG[0], sizeof(mmSEM_MAILBOX_CLIENTCONFIG)/sizeof(mmSEM_MAILBOX_CLIENTCONFIG[0]), 0, 0 },
+	{ "mmSEM_MAILBOX", REG_MMIO, 0x0F9B, &mmSEM_MAILBOX[0], sizeof(mmSEM_MAILBOX)/sizeof(mmSEM_MAILBOX[0]), 0, 0 },
+	{ "mmSEM_MAILBOX_CONTROL", REG_MMIO, 0x0F9C, &mmSEM_MAILBOX_CONTROL[0], sizeof(mmSEM_MAILBOX_CONTROL)/sizeof(mmSEM_MAILBOX_CONTROL[0]), 0, 0 },
+	{ "mmCC_DRM_ID_STRAPS", REG_MMIO, 0x1559, &mmCC_DRM_ID_STRAPS[0], sizeof(mmCC_DRM_ID_STRAPS)/sizeof(mmCC_DRM_ID_STRAPS[0]), 0, 0 },
+	{ "mmCGTT_DRM_CLK_CTRL0", REG_MMIO, 0x1579, NULL, 0, 0, 0 },
+	{ "mmDC_TEST_DEBUG_INDEX", REG_MMIO, 0x157C, &mmDC_TEST_DEBUG_INDEX[0], sizeof(mmDC_TEST_DEBUG_INDEX)/sizeof(mmDC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDC_TEST_DEBUG_DATA", REG_MMIO, 0x157D, &mmDC_TEST_DEBUG_DATA[0], sizeof(mmDC_TEST_DEBUG_DATA)/sizeof(mmDC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "mmDMA_TILING_CONFIG", REG_MMIO, 0x342E, NULL, 0, 0, 0 },
diff --git a/src/lib/ip/oss20.c b/src/lib/ip/oss20.c
new file mode 100644
index 0000000..26da1cd
--- /dev/null
+++ b/src/lib/ip/oss20.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "oss20_bits.i"
+
+static const struct umr_reg oss20_registers[] = {
+#include "oss20_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_oss20(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "oss20";
+	ip->no_regs = sizeof(oss20_registers)/sizeof(oss20_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(oss20_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, oss20_registers, sizeof(oss20_registers));
+	return ip;
+}
diff --git a/src/lib/ip/oss20_bits.i b/src/lib/ip/oss20_bits.i
new file mode 100644
index 0000000..fd9c239
--- /dev/null
+++ b/src/lib/ip/oss20_bits.i
@@ -0,0 +1,2221 @@
+static struct umr_bitfield ixDH_TEST[] = {
+	 { "DH_TEST", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DRM_ID_STRAPS[] = {
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+	 { "ATI_REV_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_TEST_DEBUG_INDEX[] = {
+	 { "DC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_TEST_DEBUG_DATA[] = {
+	 { "DC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_PORT_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRINGOSC_MASK[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPU_PORT_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UCODE_ADDR[] = {
+	 { "VALUE", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UCODE_DATA[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_POWER_CNTL[] = {
+	 { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CNTL[] = {
+	 { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SEM_INCOMPLETE_INT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 11, 16, &umr_bitfield_default },
+	 { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 22, 27, &umr_bitfield_default },
+	 { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CHICKEN_BITS[] = {
+	 { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
+	 { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_TILING_CONFIG[] = {
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_HASH[] = {
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "BANK_BITS", 4, 6, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 8, 10, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL[] = {
+	 { "TIMER", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[] = {
+	 { "TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_IB_OFFSET_FETCH[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PROGRAM[] = {
+	 { "STREAM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS_REG[] = {
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "REG_IDLE", 1, 1, &umr_bitfield_default },
+	 { "RB_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
+	 { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
+	 { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
+	 { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
+	 { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
+	 { "INSIDE_IB", 9, 9, &umr_bitfield_default },
+	 { "EX_IDLE", 10, 10, &umr_bitfield_default },
+	 { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
+	 { "PACKET_READY", 12, 12, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
+	 { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
+	 { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
+	 { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
+	 { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
+	 { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
+	 { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
+	 { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
+	 { "SEM_IDLE", 26, 26, &umr_bitfield_default },
+	 { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
+	 { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
+	 { "INT_IDLE", 30, 30, &umr_bitfield_default },
+	 { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS1_REG[] = {
+	 { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
+	 { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
+	 { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
+	 { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
+	 { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
+	 { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
+	 { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
+	 { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
+	 { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
+	 { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFMON_CNTL[] = {
+	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
+	 { "PERF_ENABLE1", 8, 8, &umr_bitfield_default },
+	 { "PERF_CLEAR1", 9, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_F32_CNTL[] = {
+	 { "HALT", 0, 0, &umr_bitfield_default },
+	 { "STEP", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_FREEZE[] = {
+	 { "FREEZE", 4, 4, &umr_bitfield_default },
+	 { "FROZEN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHASE0_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHASE1_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_POWER_GATING[] = {
+	 { "PG_CNTL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUTOMATIC_STATUS_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "PG_STATE_VALID", 2, 2, &umr_bitfield_default },
+	 { "PG_CNTL_STATUS", 4, 5, &umr_bitfield_default },
+	 { "SDMA0_ON_CONDITION", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_ON_CONDITION", 7, 7, &umr_bitfield_default },
+	 { "POWER_OFF_DELAY", 8, 19, &umr_bitfield_default },
+	 { "POWER_ON_DELAY", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE", 12, 12, &umr_bitfield_default },
+	 { "READ", 13, 13, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_WRITE[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_READ[] = {
+	 { "VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+	 { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CONTEXT_CNTL[] = {
+	 { "RESUME_CTX", 16, 16, &umr_bitfield_default },
+	 { "SESSION_SEL", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UCODE_ADDR[] = {
+	 { "VALUE", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UCODE_DATA[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_POWER_CNTL[] = {
+	 { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CNTL[] = {
+	 { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SEM_INCOMPLETE_INT_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 11, 16, &umr_bitfield_default },
+	 { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 22, 27, &umr_bitfield_default },
+	 { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CHICKEN_BITS[] = {
+	 { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
+	 { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_TILING_CONFIG[] = {
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_HASH[] = {
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "BANK_BITS", 4, 6, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 8, 10, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL[] = {
+	 { "TIMER", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[] = {
+	 { "TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RB_RPTR_FETCH[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_IB_OFFSET_FETCH[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PROGRAM[] = {
+	 { "STREAM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS_REG[] = {
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "REG_IDLE", 1, 1, &umr_bitfield_default },
+	 { "RB_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
+	 { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
+	 { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
+	 { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
+	 { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
+	 { "INSIDE_IB", 9, 9, &umr_bitfield_default },
+	 { "EX_IDLE", 10, 10, &umr_bitfield_default },
+	 { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
+	 { "PACKET_READY", 12, 12, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
+	 { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
+	 { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
+	 { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
+	 { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
+	 { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
+	 { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
+	 { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
+	 { "SEM_IDLE", 26, 26, &umr_bitfield_default },
+	 { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
+	 { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
+	 { "INT_IDLE", 30, 30, &umr_bitfield_default },
+	 { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS1_REG[] = {
+	 { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
+	 { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
+	 { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
+	 { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
+	 { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
+	 { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
+	 { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
+	 { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
+	 { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
+	 { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFMON_CNTL[] = {
+	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
+	 { "PERF_ENABLE1", 8, 8, &umr_bitfield_default },
+	 { "PERF_CLEAR1", 9, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_F32_CNTL[] = {
+	 { "HALT", 0, 0, &umr_bitfield_default },
+	 { "STEP", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_FREEZE[] = {
+	 { "FREEZE", 4, 4, &umr_bitfield_default },
+	 { "FROZEN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHASE0_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHASE1_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+	 { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CONTEXT_CNTL[] = {
+	 { "RESUME_CTX", 16, 16, &umr_bitfield_default },
+	 { "SESSION_SEL", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CNTL[] = {
+	 { "READ_TIMEOUT", 0, 12, &umr_bitfield_default },
+	 { "PWR_REQUEST_HALT", 16, 16, &umr_bitfield_default },
+	 { "COMBINE_SYSTEM_MC", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_GFX_CNTL[] = {
+	 { "PIPEID", 0, 1, &umr_bitfield_default },
+	 { "MEID", 2, 3, &umr_bitfield_default },
+	 { "VMID", 4, 7, &umr_bitfield_default },
+	 { "QUEUEID", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_STATUS2[] = {
+	 { "SDMA_RQ_PENDING", 0, 0, &umr_bitfield_default },
+	 { "TST_RQ_PENDING", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_RQ_PENDING", 2, 2, &umr_bitfield_default },
+	 { "VCE_RQ_PENDING", 3, 3, &umr_bitfield_default },
+	 { "XSP_BUSY", 4, 4, &umr_bitfield_default },
+	 { "SDMA_BUSY", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VCE_BUSY", 7, 7, &umr_bitfield_default },
+	 { "XDMA_BUSY", 8, 8, &umr_bitfield_default },
+	 { "CHUB_BUSY", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_STATUS[] = {
+	 { "UVD_RQ_PENDING", 1, 1, &umr_bitfield_default },
+	 { "SAM_RQ_PENDING", 2, 2, &umr_bitfield_default },
+	 { "ACP_RQ_PENDING", 3, 3, &umr_bitfield_default },
+	 { "SMU_RQ_PENDING", 4, 4, &umr_bitfield_default },
+	 { "GRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "HI_RQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "IO_EXTERN_SIGNAL", 7, 7, &umr_bitfield_default },
+	 { "VMC_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MCB_BUSY", 9, 9, &umr_bitfield_default },
+	 { "MCB_NON_DISPLAY_BUSY", 10, 10, &umr_bitfield_default },
+	 { "MCC_BUSY", 11, 11, &umr_bitfield_default },
+	 { "MCD_BUSY", 12, 12, &umr_bitfield_default },
+	 { "SEM_BUSY", 14, 14, &umr_bitfield_default },
+	 { "ACP_BUSY", 16, 16, &umr_bitfield_default },
+	 { "IH_BUSY", 17, 17, &umr_bitfield_default },
+	 { "UVD_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SAM_BUSY", 20, 20, &umr_bitfield_default },
+	 { "BIF_BUSY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SOFT_RESET[] = {
+	 { "SOFT_RESET_BIF", 1, 1, &umr_bitfield_default },
+	 { "SOFT_RESET_ROPLL", 4, 4, &umr_bitfield_default },
+	 { "SOFT_RESET_DC", 5, 5, &umr_bitfield_default },
+	 { "SOFT_RESET_SDMA1", 6, 6, &umr_bitfield_default },
+	 { "SOFT_RESET_GRBM", 8, 8, &umr_bitfield_default },
+	 { "SOFT_RESET_HDP", 9, 9, &umr_bitfield_default },
+	 { "SOFT_RESET_IH", 10, 10, &umr_bitfield_default },
+	 { "SOFT_RESET_MC", 11, 11, &umr_bitfield_default },
+	 { "SOFT_RESET_CHUB", 12, 12, &umr_bitfield_default },
+	 { "SOFT_RESET_ROM", 14, 14, &umr_bitfield_default },
+	 { "SOFT_RESET_SEM", 15, 15, &umr_bitfield_default },
+	 { "SOFT_RESET_SMU", 16, 16, &umr_bitfield_default },
+	 { "SOFT_RESET_VMC", 17, 17, &umr_bitfield_default },
+	 { "SOFT_RESET_UVD", 18, 18, &umr_bitfield_default },
+	 { "SOFT_RESET_XSP", 19, 19, &umr_bitfield_default },
+	 { "SOFT_RESET_SDMA", 20, 20, &umr_bitfield_default },
+	 { "SOFT_RESET_TST", 21, 21, &umr_bitfield_default },
+	 { "SOFT_RESET_REGBB", 22, 22, &umr_bitfield_default },
+	 { "SOFT_RESET_ORB", 23, 23, &umr_bitfield_default },
+	 { "SOFT_RESET_VCE", 24, 24, &umr_bitfield_default },
+	 { "SOFT_RESET_XDMA", 25, 25, &umr_bitfield_default },
+	 { "SOFT_RESET_ACP", 26, 26, &umr_bitfield_default },
+	 { "SOFT_RESET_SAM", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_CNTL[] = {
+	 { "SRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CHIP_REVISION[] = {
+	 { "CHIP_REVISION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SYS_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SYS_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SYS_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG[] = {
+	 { "IGNORE_RDY", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_READ_TIMEOUT", 1, 1, &umr_bitfield_default },
+	 { "SNAPSHOT_FREE_CNTRS", 2, 2, &umr_bitfield_default },
+	 { "SYS_CLOCK_DOMAIN_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "VCE_CLOCK_DOMAIN_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "UVD_CLOCK_DOMAIN_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "SDMA_CLOCK_DOMAIN_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "MC_CLOCK_DOMAIN_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "SAM_CLOCK_DOMAIN_OVERRIDE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_SNAPSHOT[] = {
+	 { "MCB_RDY", 0, 0, &umr_bitfield_default },
+	 { "ROPLL_RDY", 1, 1, &umr_bitfield_default },
+	 { "SMU_RDY", 2, 2, &umr_bitfield_default },
+	 { "SAM_RDY", 3, 3, &umr_bitfield_default },
+	 { "ACP_RDY", 4, 4, &umr_bitfield_default },
+	 { "GRBM_RDY", 5, 5, &umr_bitfield_default },
+	 { "DC_RDY", 6, 6, &umr_bitfield_default },
+	 { "BIF_RDY", 7, 7, &umr_bitfield_default },
+	 { "XDMA_RDY", 8, 8, &umr_bitfield_default },
+	 { "UVD_RDY", 9, 9, &umr_bitfield_default },
+	 { "XSP_RDY", 10, 10, &umr_bitfield_default },
+	 { "REGBB_RDY", 11, 11, &umr_bitfield_default },
+	 { "ORB_RDY", 12, 12, &umr_bitfield_default },
+	 { "MCD7_RDY", 13, 13, &umr_bitfield_default },
+	 { "MCD6_RDY", 14, 14, &umr_bitfield_default },
+	 { "MCD5_RDY", 15, 15, &umr_bitfield_default },
+	 { "MCD4_RDY", 16, 16, &umr_bitfield_default },
+	 { "MCD3_RDY", 17, 17, &umr_bitfield_default },
+	 { "MCD2_RDY", 18, 18, &umr_bitfield_default },
+	 { "MCD1_RDY", 19, 19, &umr_bitfield_default },
+	 { "MCD0_RDY", 20, 20, &umr_bitfield_default },
+	 { "MCC7_RDY", 21, 21, &umr_bitfield_default },
+	 { "MCC6_RDY", 22, 22, &umr_bitfield_default },
+	 { "MCC5_RDY", 23, 23, &umr_bitfield_default },
+	 { "MCC4_RDY", 24, 24, &umr_bitfield_default },
+	 { "MCC3_RDY", 25, 25, &umr_bitfield_default },
+	 { "MCC2_RDY", 26, 26, &umr_bitfield_default },
+	 { "MCC1_RDY", 27, 27, &umr_bitfield_default },
+	 { "MCC0_RDY", 28, 28, &umr_bitfield_default },
+	 { "VCE_RDY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_READ_ERROR[] = {
+	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "READ_REQUESTER_VCE", 20, 20, &umr_bitfield_default },
+	 { "READ_REQUESTER_SDMA1", 21, 21, &umr_bitfield_default },
+	 { "READ_REQUESTER_TST", 22, 22, &umr_bitfield_default },
+	 { "READ_REQUESTER_SAM", 23, 23, &umr_bitfield_default },
+	 { "READ_REQUESTER_HI", 24, 24, &umr_bitfield_default },
+	 { "READ_REQUESTER_GRBM", 25, 25, &umr_bitfield_default },
+	 { "READ_REQUESTER_SMU", 26, 26, &umr_bitfield_default },
+	 { "READ_REQUESTER_ACP", 27, 27, &umr_bitfield_default },
+	 { "READ_REQUESTER_SDMA", 28, 28, &umr_bitfield_default },
+	 { "READ_REQUESTER_UVD", 29, 29, &umr_bitfield_default },
+	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_CNTL[] = {
+	 { "RDERR_INT_MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_STATUS[] = {
+	 { "RDERR_INT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_ACK[] = {
+	 { "RDERR_INT_ACK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VCE_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_UVD_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SDMA_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SAM_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CNTL[] = {
+	 { "XDMA_MSTR_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_READY", 14, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_DEBUG_MODE", 18, 18, &umr_bitfield_default },
+	 { "XDMA_MSTR_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
+	 { "XDMA_MSTR_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "XDMA_MSTR_BIF_STALL_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_STATUS[] = {
+	 { "XDMA_MSTR_VCOUNT_CURRENT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_WRITE_LINE_CURRENT", 16, 27, &umr_bitfield_default },
+	 { "XDMA_MSTR_STATUS_SELECT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_LOCAL_SURFACE_PITCH[] = {
+	 { "XDMA_MSTR_LOCAL_SURFACE_PITCH", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CMD_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_CMD_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_CMD_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_CMD_STALL_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_URGENT_CNTL[] = {
+	 { "XDMA_MSTR_MEM_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG[] = {
+	 { "XDMA_MSTR_UNDERFLOW_LIMIT", 0, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PCIE_NACK_STATUS[] = {
+	 { "XDMA_MSTR_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_NACK_STATUS[] = {
+	 { "XDMA_MSTR_MEM_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_MEM_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_VSYNC_GSL_CHECK[] = {
+	 { "XDMA_MSTR_VSYNC_GSL_CHECK_SEL", 0, 2, &umr_bitfield_default },
+	 { "XDMA_MSTR_VSYNC_GSL_CHECK_V_COUNT", 8, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PIPE_CNTL[] = {
+	 { "XDMA_MSTR_CACHE_LINES", 0, 7, &umr_bitfield_default },
+	 { "XDMA_MSTR_READ_REQUEST", 8, 8, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FRAME_MODE", 9, 9, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_INVALIDATE", 11, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_CHANNEL_ID", 12, 14, &umr_bitfield_default },
+	 { "XDMA_MSTR_FLIP_MODE", 15, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_MIN", 16, 23, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_ACTIVE", 24, 24, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FLUSHING", 25, 25, &umr_bitfield_default },
+	 { "XDMA_MSTR_PIPE_FLIP_PENDING", 26, 26, &umr_bitfield_default },
+	 { "XDMA_MSTR_VSYNC_GSL_ENABLE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_READ_COMMAND[] = {
+	 { "XDMA_MSTR_REQUEST_SIZE", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_REQUEST_PREFETCH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CHANNEL_DIM[] = {
+	 { "XDMA_MSTR_CHANNEL_WIDTH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CHANNEL_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_HEIGHT[] = {
+	 { "XDMA_MSTR_ACTIVE_HEIGHT", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_FRAME_HEIGHT", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR[] = {
+	 { "XDMA_MSTR_CACHE_BASE_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[] = {
+	 { "XDMA_MSTR_CACHE_BASE_ADDR_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CACHE_PITCH[] = {
+	 { "XDMA_MSTR_CACHE_PITCH", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_CHANNEL_START[] = {
+	 { "XDMA_MSTR_CHANNEL_START_X", 0, 13, &umr_bitfield_default },
+	 { "XDMA_MSTR_CHANNEL_START_Y", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_OVERFLOW_CNTL[] = {
+	 { "XDMA_MSTR_OVERFLOW_COUNT", 0, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_OVERFLOW_THRESHOLD", 16, 29, &umr_bitfield_default },
+	 { "XDMA_MSTR_OVERFLOW_BP_ENABLE", 30, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_OVERFLOW_COUNT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_MEM_UNDERFLOW_CNTL[] = {
+	 { "XDMA_MSTR_UNDERFLOW_COUNT", 0, 15, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_THRESHOLD", 16, 29, &umr_bitfield_default },
+	 { "XDMA_MSTR_UNDERFLOW_DETECT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_STATUS[] = {
+	 { "XDMA_MSTR_PERFMEAS_DATA", 0, 23, &umr_bitfield_default },
+	 { "XDMA_MSTR_PERFMEAS_INDEX", 24, 26, &umr_bitfield_default },
+	 { "XDMA_MSTR_PERFMEAS_INDEX_MODE", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_MSTR_PERFMEAS_CNTL[] = {
+	 { "XDMA_MSTR_CACHE_BW_MEAS_ITER", 0, 11, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_BW_SEGID_SEL", 12, 16, &umr_bitfield_default },
+	 { "XDMA_MSTR_CACHE_BW_COUNTER_RST", 17, 17, &umr_bitfield_default },
+	 { "XDMA_MSTR_LT_MEAS_ITER", 19, 30, &umr_bitfield_default },
+	 { "XDMA_MSTR_LT_COUNTER_RST", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CNTL[] = {
+	 { "XDMA_SLV_READ_LINES", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_READY", 9, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "XDMA_SLV_ALPHA_POSITION", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LAT_TEST_EN", 19, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_SOFT_RESET", 20, 20, &umr_bitfield_default },
+	 { "XDMA_SLV_REQ_MAXED_OUT", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_CLIENT_CONFIG[] = {
+	 { "XDMA_SLV_MEM_CLIENT_SWAP", 8, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_VMID", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_CLIENT_PRIV", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_SLS_PITCH[] = {
+	 { "XDMA_SLV_SLS_PITCH", 0, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_SLS_WIDTH", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_URGENT_CNTL[] = {
+	 { "XDMA_SLV_READ_CLIENT_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LIMIT", 4, 7, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_STALL_DELAY", 12, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_URGENT_TIMER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WRITE_URGENT_CNTL[] = {
+	 { "XDMA_SLV_WRITE_STALL", 0, 0, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_URGENT_LEVEL", 8, 11, &umr_bitfield_default },
+	 { "XDMA_SLV_WRITE_STALL_DELAY", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_WB_RATE_CNTL[] = {
+	 { "XDMA_SLV_WB_BURST_SIZE", 0, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_WB_BURST_PERIOD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_MINMAX[] = {
+	 { "XDMA_SLV_READ_LATENCY_MIN", 0, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_MAX", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_AVE[] = {
+	 { "XDMA_SLV_READ_LATENCY_ACC", 0, 19, &umr_bitfield_default },
+	 { "XDMA_SLV_READ_LATENCY_COUNT", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_PCIE_NACK_STATUS[] = {
+	 { "XDMA_SLV_PCIE_NACK_TAG", 0, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK", 12, 13, &umr_bitfield_default },
+	 { "XDMA_SLV_PCIE_NACK_CLR", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_MEM_NACK_STATUS[] = {
+	 { "XDMA_SLV_MEM_NACK_TAG", 0, 15, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK", 16, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_MEM_NACK_CLR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_RDRET_BUF_STATUS[] = {
+	 { "XDMA_SLV_RDRET_FREE_ENTRIES", 0, 9, &umr_bitfield_default },
+	 { "XDMA_SLV_RDRET_BUF_SIZE", 12, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_READ_LATENCY_TIMER[] = {
+	 { "XDMA_SLV_READ_LATENCY_TIMER", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_FLIP_PENDING[] = {
+	 { "XDMA_SLV_FLIP_PENDING", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_CHANNEL_CNTL[] = {
+	 { "XDMA_SLV_CHANNEL_WEIGHT", 0, 8, &umr_bitfield_default },
+	 { "XDMA_SLV_STOP_TRANSFER", 16, 16, &umr_bitfield_default },
+	 { "XDMA_SLV_CHANNEL_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "XDMA_SLV_CHANNEL_ACTIVE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[] = {
+	 { "XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP7[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
+	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_LO[] = {
+	 { "PERF_COUNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_HI[] = {
+	 { "PERF_COUNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_LO[] = {
+	 { "PERF_COUNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_HI[] = {
+	 { "PERF_COUNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_HOST_PATH_CNTL[] = {
+	 { "BIF_RDRET_CREDIT", 0, 2, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 3, 8, &umr_bitfield_default },
+	 { "WR_STALL_TIMER", 9, 10, &umr_bitfield_default },
+	 { "RD_STALL_TIMER", 11, 12, &umr_bitfield_default },
+	 { "WRITE_COMBINE_TIMER", 19, 20, &umr_bitfield_default },
+	 { "WRITE_COMBINE_EN", 21, 21, &umr_bitfield_default },
+	 { "CACHE_INVALIDATE", 22, 22, &umr_bitfield_default },
+	 { "CLOCK_GATING_DIS", 23, 23, &umr_bitfield_default },
+	 { "REG_CLK_ENABLE_COUNT", 24, 27, &umr_bitfield_default },
+	 { "ALL_SURFACES_DIS", 29, 29, &umr_bitfield_default },
+	 { "WRITE_THROUGH_CACHE_DIS", 30, 30, &umr_bitfield_default },
+	 { "LIN_RD_CACHE_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_BASE[] = {
+	 { "NONSURF_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_INFO[] = {
+	 { "NONSURF_ADDR_TYPE", 0, 0, &umr_bitfield_default },
+	 { "NONSURF_ARRAY_MODE", 1, 4, &umr_bitfield_default },
+	 { "NONSURF_ENDIAN", 5, 6, &umr_bitfield_default },
+	 { "NONSURF_PIXEL_SIZE", 7, 9, &umr_bitfield_default },
+	 { "NONSURF_SAMPLE_NUM", 10, 12, &umr_bitfield_default },
+	 { "NONSURF_SAMPLE_SIZE", 13, 14, &umr_bitfield_default },
+	 { "NONSURF_PRIV", 15, 15, &umr_bitfield_default },
+	 { "NONSURF_TILE_COMPACT", 16, 16, &umr_bitfield_default },
+	 { "NONSURF_TILE_SPLIT", 17, 19, &umr_bitfield_default },
+	 { "NONSURF_NUM_BANKS", 20, 21, &umr_bitfield_default },
+	 { "NONSURF_BANK_WIDTH", 22, 23, &umr_bitfield_default },
+	 { "NONSURF_BANK_HEIGHT", 24, 25, &umr_bitfield_default },
+	 { "NONSURF_MACRO_TILE_ASPECT", 26, 27, &umr_bitfield_default },
+	 { "NONSURF_MICRO_TILE_MODE", 28, 30, &umr_bitfield_default },
+	 { "NONSURF_SLICE_TILE_MAX_MSB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_SIZE[] = {
+	 { "NONSURF_PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "NONSURF_SLICE_TILE_MAX", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURF_FLAGS[] = {
+	 { "NONSURF_WRITE_FLAG", 0, 0, &umr_bitfield_default },
+	 { "NONSURF_READ_FLAG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURF_FLAGS_CLR[] = {
+	 { "NONSURF_WRITE_FLAG_CLR", 0, 0, &umr_bitfield_default },
+	 { "NONSURF_READ_FLAG_CLR", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_SW_SEMAPHORE[] = {
+	 { "SW_SEMAPHORE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_DEBUG0[] = {
+};
+static struct umr_bitfield mmHDP_DEBUG1[] = {
+};
+static struct umr_bitfield mmHDP_LAST_SURFACE_HIT[] = {
+	 { "LAST_SURFACE_HIT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_TILING_CONFIG[] = {
+	 { "PIPE_TILING", 1, 3, &umr_bitfield_default },
+	 { "BANK_TILING", 4, 5, &umr_bitfield_default },
+	 { "GROUP_SIZE", 6, 7, &umr_bitfield_default },
+	 { "ROW_TILING", 8, 10, &umr_bitfield_default },
+	 { "BANK_SWAPS", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_SC_MULTI_CHIP_CNTL[] = {
+	 { "LOG2_NUM_CHIPS", 0, 2, &umr_bitfield_default },
+	 { "MULTI_CHIP_TILE_SIZE", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_OUTSTANDING_REQ[] = {
+	 { "WRITE_REQ", 0, 7, &umr_bitfield_default },
+	 { "READ_REQ", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MISC_CNTL[] = {
+	 { "FLUSH_INVALIDATE_CACHE", 0, 0, &umr_bitfield_default },
+	 { "VM_ID", 1, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE_COUNT_1024", 5, 5, &umr_bitfield_default },
+	 { "MULTIPLE_READS", 6, 6, &umr_bitfield_default },
+	 { "HDP_BIF_RDRET_CREDIT", 7, 10, &umr_bitfield_default },
+	 { "SIMULTANEOUS_READS_WRITES", 11, 11, &umr_bitfield_default },
+	 { "NO_SPLIT_ARRAY_LINEAR", 12, 12, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default },
+	 { "READ_CACHE_INVALIDATE", 19, 19, &umr_bitfield_default },
+	 { "ADDRLIB_LINEAR_BYPASS", 20, 20, &umr_bitfield_default },
+	 { "FED_ENABLE", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEM_POWER_LS[] = {
+	 { "LS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LS_SETUP", 1, 6, &umr_bitfield_default },
+	 { "LS_HOLD", 7, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_PREFETCH[] = {
+	 { "NONSURF_PREFETCH_PRI", 0, 2, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_DIR", 3, 5, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_NUM", 6, 8, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_MAX_Z", 9, 19, &umr_bitfield_default },
+	 { "NONSURF_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_CNTL[] = {
+	 { "MEMIO_SEND", 0, 0, &umr_bitfield_default },
+	 { "MEMIO_OP", 1, 1, &umr_bitfield_default },
+	 { "MEMIO_BE", 2, 5, &umr_bitfield_default },
+	 { "MEMIO_WR_STROBE", 6, 6, &umr_bitfield_default },
+	 { "MEMIO_RD_STROBE", 7, 7, &umr_bitfield_default },
+	 { "MEMIO_ADDR_UPPER", 8, 13, &umr_bitfield_default },
+	 { "MEMIO_CLR_WR_ERROR", 14, 14, &umr_bitfield_default },
+	 { "MEMIO_CLR_RD_ERROR", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_ADDR[] = {
+	 { "MEMIO_ADDR_LOWER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_STATUS[] = {
+	 { "MEMIO_WR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "MEMIO_RD_STATUS", 1, 1, &umr_bitfield_default },
+	 { "MEMIO_WR_ERROR", 2, 2, &umr_bitfield_default },
+	 { "MEMIO_RD_ERROR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_WR_DATA[] = {
+	 { "MEMIO_WR_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_RD_DATA[] = {
+	 { "MEMIO_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_FIRST[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_FLUSH[] = {
+	 { "D2H_FLUSH_FLUSH_NUM", 0, 3, &umr_bitfield_default },
+	 { "D2H_FLUSH_MBX_ENC_DATA", 4, 7, &umr_bitfield_default },
+	 { "D2H_FLUSH_MBX_ADDR_SEL", 8, 10, &umr_bitfield_default },
+	 { "D2H_FLUSH_XPB_CLG", 11, 15, &umr_bitfield_default },
+	 { "D2H_FLUSH_SEND_HOST", 16, 16, &umr_bitfield_default },
+	 { "D2H_FLUSH_SEND_SIDE", 17, 17, &umr_bitfield_default },
+	 { "D2H_FLUSH_ALTER_FLUSH_NUM", 18, 18, &umr_bitfield_default },
+	 { "D2H_FLUSH_RSVD_0", 19, 19, &umr_bitfield_default },
+	 { "D2H_FLUSH_RSVD_1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_BAR_UPDATE[] = {
+	 { "D2H_BAR_UPDATE_ADDR", 0, 15, &umr_bitfield_default },
+	 { "D2H_BAR_UPDATE_FLUSH_NUM", 16, 19, &umr_bitfield_default },
+	 { "D2H_BAR_UPDATE_BAR_NUM", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_7[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_8[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_9[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_10[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_11[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_12[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_13[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_14[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_15[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_16[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_17[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_18[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_19[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_20[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_21[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_22[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_23[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_24[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_25[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_26[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_27[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_28[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_29[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_30[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_31[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_32[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_33[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_34[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_LAST[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR_CFG[] = {
+	 { "P2P_BAR_CFG_ADDR_SIZE", 0, 3, &umr_bitfield_default },
+	 { "P2P_BAR_CFG_BAR_FROM", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_OFFSET[] = {
+	 { "P2P_MBX_OFFSET", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR4[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR5[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR6[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_MBX_MC_CFG[] = {
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_PRIV", 0, 0, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_SWAP", 1, 2, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_TRAN", 3, 3, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_MC_CFG[] = {
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_PRIV", 0, 0, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_SWAP", 1, 2, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_TRAN", 3, 3, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_PRIV", 4, 4, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_SWAP", 5, 6, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_TRAN", 7, 7, &umr_bitfield_default },
+	 { "HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE", 8, 13, &umr_bitfield_default },
+	 { "HDP_MC_CFG_XDP_HIGHER_PRI_THRESH", 14, 19, &umr_bitfield_default },
+	 { "HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK", 20, 22, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_VMID", 23, 26, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_VMID", 27, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HST_CFG[] = {
+	 { "HST_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
+	 { "HST_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_SID_CFG[] = {
+	 { "SID_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
+	 { "SID_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
+	 { "SID_CFG_FLNUM_MSB_SEL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_IPH_CFG[] = {
+	 { "HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE", 0, 5, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE", 6, 11, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING", 12, 12, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_P2P_RD_EN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_SRBM_CFG[] = {
+	 { "SRBM_CFG_REG_CLK_ENABLE_COUNT", 0, 5, &umr_bitfield_default },
+	 { "SRBM_CFG_REG_CLK_GATING_DIS", 6, 6, &umr_bitfield_default },
+	 { "SRBM_CFG_WAKE_DYN_CLK", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_CGTT_BLK_CTRL[] = {
+	 { "CGTT_BLK_CTRL_0_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_1_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_2_RSVD", 12, 29, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR0[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR1[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR2[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR3[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR4[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR5[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR6[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR7[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_FLUSH_ARMED_STS[] = {
+	 { "FLUSH_ARMED_STS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_FLUSH_CNTR0_STS[] = {
+	 { "FLUSH_CNTR0_STS", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_BUSY_STS[] = {
+	 { "BUSY_BITS", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_STICKY[] = {
+	 { "STICKY_STS", 0, 15, &umr_bitfield_default },
+	 { "STICKY_W1C", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_CHKN[] = {
+	 { "CHKN_0_RSVD", 0, 7, &umr_bitfield_default },
+	 { "CHKN_1_RSVD", 8, 15, &umr_bitfield_default },
+	 { "CHKN_2_RSVD", 16, 23, &umr_bitfield_default },
+	 { "CHKN_3_RSVD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_ADDR[] = {
+	 { "STS", 0, 15, &umr_bitfield_default },
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_DATA[] = {
+	 { "STS", 0, 15, &umr_bitfield_default },
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_MASK[] = {
+	 { "STS", 0, 15, &umr_bitfield_default },
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_BARS_ADDR_39_36[] = {
+	 { "BAR0_ADDR_39_36", 0, 3, &umr_bitfield_default },
+	 { "BAR1_ADDR_39_36", 4, 7, &umr_bitfield_default },
+	 { "BAR2_ADDR_39_36", 8, 11, &umr_bitfield_default },
+	 { "BAR3_ADDR_39_36", 12, 15, &umr_bitfield_default },
+	 { "BAR4_ADDR_39_36", 16, 19, &umr_bitfield_default },
+	 { "BAR5_ADDR_39_36", 20, 23, &umr_bitfield_default },
+	 { "BAR6_ADDR_39_36", 24, 27, &umr_bitfield_default },
+	 { "BAR7_ADDR_39_36", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_0_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_1_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_2_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_3_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_4_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_5_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_6_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_7_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_8_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_9_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_10_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_11_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_12_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_13_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_14_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_15_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_FULL_DRAIN_ENABLE", 6, 6, &umr_bitfield_default },
+	 { "RB_GPU_TS_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_TIMER", 9, 13, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_RPTR[] = {
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR[] = {
+	 { "RB_OVERFLOW", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_CNTL[] = {
+	 { "ENABLE_INTR", 0, 0, &umr_bitfield_default },
+	 { "MC_SWAP", 1, 2, &umr_bitfield_default },
+	 { "MC_TRAN", 3, 3, &umr_bitfield_default },
+	 { "RPTR_REARM", 4, 4, &umr_bitfield_default },
+	 { "CLIENT_FIFO_HIGHWATER", 8, 9, &umr_bitfield_default },
+	 { "MC_FIFO_HIGHWATER", 10, 14, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 15, 19, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_CNT", 20, 24, &umr_bitfield_default },
+	 { "MC_VMID", 25, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_LEVEL_STATUS[] = {
+	 { "DC_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ROM_STATUS", 2, 2, &umr_bitfield_default },
+	 { "SRBM_STATUS", 3, 3, &umr_bitfield_default },
+	 { "BIF_STATUS", 4, 4, &umr_bitfield_default },
+	 { "XDMA_STATUS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_STATUS[] = {
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_IDLE", 1, 1, &umr_bitfield_default },
+	 { "RB_IDLE", 2, 2, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_FULL_DRAIN", 4, 4, &umr_bitfield_default },
+	 { "RB_OVERFLOW", 5, 5, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 6, 6, &umr_bitfield_default },
+	 { "MC_WR_STALL", 7, 7, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_PENDING", 8, 8, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_STALL", 9, 9, &umr_bitfield_default },
+	 { "BIF_INTERRUPT_LINE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFMON_CNTL[] = {
+	 { "ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
+	 { "ENABLE1", 8, 8, &umr_bitfield_default },
+	 { "CLEAR1", 9, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_ADVFAULT_CNTL[] = {
+	 { "WATERMARK", 0, 2, &umr_bitfield_default },
+	 { "WATERMARK_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "WATERMARK_REACHED", 4, 4, &umr_bitfield_default },
+	 { "NUM_FAULTS_DROPPED", 8, 15, &umr_bitfield_default },
+	 { "WAIT_TIMER", 16, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MCIF_CONFIG[] = {
+	 { "MC_REQ_SWAP", 0, 1, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 2, 7, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_CONFIG[] = {
+	 { "SDMA_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "SDMA_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONFIG[] = {
+	 { "SDMA_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "SDMA_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CONFIG[] = {
+	 { "UVD_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "UVD_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_CONFIG[] = {
+	 { "VCE_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "VCE_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmACP_CONFIG[] = {
+	 { "ACP_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "ACP_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPG_CONFIG[] = {
+	 { "CPG_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "CPG_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC1_CONFIG[] = {
+	 { "CPC1_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "CPC1_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCPC2_CONFIG[] = {
+	 { "CPC2_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "CPC2_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_STATUS[] = {
+	 { "SEM_IDLE", 0, 0, &umr_bitfield_default },
+	 { "SEM_INTERNAL_IDLE", 1, 1, &umr_bitfield_default },
+	 { "MC_RDREQ_FIFO_FULL", 2, 2, &umr_bitfield_default },
+	 { "MC_WRREQ_FIFO_FULL", 3, 3, &umr_bitfield_default },
+	 { "WRITE1_FIFO_FULL", 4, 4, &umr_bitfield_default },
+	 { "CHECK0_FIFO_FULL", 5, 5, &umr_bitfield_default },
+	 { "MC_RDREQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "MC_WRREQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_MAILBOX_PENDING", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_MAILBOX_PENDING", 9, 9, &umr_bitfield_default },
+	 { "UVD_MAILBOX_PENDING", 10, 10, &umr_bitfield_default },
+	 { "VCE_MAILBOX_PENDING", 11, 11, &umr_bitfield_default },
+	 { "CPG1_MAILBOX_PENDING", 12, 12, &umr_bitfield_default },
+	 { "CPG2_MAILBOX_PENDING", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX_CLIENTCONFIG[] = {
+	 { "CP_CLIENT0", 0, 2, &umr_bitfield_default },
+	 { "CP_CLIENT1", 3, 5, &umr_bitfield_default },
+	 { "CP_CLIENT2", 6, 8, &umr_bitfield_default },
+	 { "CP_CLIENT3", 9, 11, &umr_bitfield_default },
+	 { "SDMA_CLIENT0", 12, 14, &umr_bitfield_default },
+	 { "UVD_CLIENT0", 15, 17, &umr_bitfield_default },
+	 { "SDMA1_CLIENT0", 18, 20, &umr_bitfield_default },
+	 { "VCE_CLIENT0", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX[] = {
+	 { "SIDEPORT", 0, 7, &umr_bitfield_default },
+	 { "HOSTPORT", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX_CONTROL[] = {
+	 { "SIDEPORT_ENABLE", 0, 7, &umr_bitfield_default },
+	 { "HOSTPORT_ENABLE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_CHICKEN_BITS[] = {
+	 { "VMID_PIPELINE_EN", 0, 0, &umr_bitfield_default },
+	 { "ENTRY_PIPELINE_EN", 1, 1, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/oss20_regs.i b/src/lib/ip/oss20_regs.i
new file mode 100644
index 0000000..ca3d7e7
--- /dev/null
+++ b/src/lib/ip/oss20_regs.i
@@ -0,0 +1,614 @@
+	{ "ixDH_TEST", REG_SMC, 0x0, &ixDH_TEST[0], sizeof(ixDH_TEST)/sizeof(ixDH_TEST[0]), 0, 0 },
+	{ "ixKHFS3", REG_SMC, 0x10, &ixKHFS3[0], sizeof(ixKHFS3)/sizeof(ixKHFS3[0]), 0, 0 },
+	{ "ixKSESSION0", REG_SMC, 0x14, &ixKSESSION0[0], sizeof(ixKSESSION0)/sizeof(ixKSESSION0[0]), 0, 0 },
+	{ "mmCC_DRM_ID_STRAPS", REG_MMIO, 0x1559, &mmCC_DRM_ID_STRAPS[0], sizeof(mmCC_DRM_ID_STRAPS)/sizeof(mmCC_DRM_ID_STRAPS[0]), 0, 0 },
+	{ "mmCGTT_DRM_CLK_CTRL0", REG_MMIO, 0x1579, NULL, 0, 0, 0 },
+	{ "mmDC_TEST_DEBUG_INDEX", REG_MMIO, 0x157c, &mmDC_TEST_DEBUG_INDEX[0], sizeof(mmDC_TEST_DEBUG_INDEX)/sizeof(mmDC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDC_TEST_DEBUG_DATA", REG_MMIO, 0x157d, &mmDC_TEST_DEBUG_DATA[0], sizeof(mmDC_TEST_DEBUG_DATA)/sizeof(mmDC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixKSESSION1", REG_SMC, 0x18, &ixKSESSION1[0], sizeof(ixKSESSION1)/sizeof(ixKSESSION1[0]), 0, 0 },
+	{ "ixCLIENT2_K0", REG_SMC, 0x1b4, &ixCLIENT2_K0[0], sizeof(ixCLIENT2_K0)/sizeof(ixCLIENT2_K0[0]), 0, 0 },
+	{ "ixCLIENT2_K1", REG_SMC, 0x1b8, &ixCLIENT2_K1[0], sizeof(ixCLIENT2_K1)/sizeof(ixCLIENT2_K1[0]), 0, 0 },
+	{ "ixCLIENT2_K2", REG_SMC, 0x1bc, &ixCLIENT2_K2[0], sizeof(ixCLIENT2_K2)/sizeof(ixCLIENT2_K2[0]), 0, 0 },
+	{ "ixKSESSION2", REG_SMC, 0x1c, &ixKSESSION2[0], sizeof(ixKSESSION2)/sizeof(ixKSESSION2[0]), 0, 0 },
+	{ "ixCLIENT2_K3", REG_SMC, 0x1c0, &ixCLIENT2_K3[0], sizeof(ixCLIENT2_K3)/sizeof(ixCLIENT2_K3[0]), 0, 0 },
+	{ "ixCLIENT2_CK0", REG_SMC, 0x1c4, &ixCLIENT2_CK0[0], sizeof(ixCLIENT2_CK0)/sizeof(ixCLIENT2_CK0[0]), 0, 0 },
+	{ "ixCLIENT2_CK1", REG_SMC, 0x1c8, &ixCLIENT2_CK1[0], sizeof(ixCLIENT2_CK1)/sizeof(ixCLIENT2_CK1[0]), 0, 0 },
+	{ "ixCLIENT2_CK2", REG_SMC, 0x1cc, &ixCLIENT2_CK2[0], sizeof(ixCLIENT2_CK2)/sizeof(ixCLIENT2_CK2[0]), 0, 0 },
+	{ "ixCLIENT2_CK3", REG_SMC, 0x1d0, &ixCLIENT2_CK3[0], sizeof(ixCLIENT2_CK3)/sizeof(ixCLIENT2_CK3[0]), 0, 0 },
+	{ "ixCLIENT2_CD0", REG_SMC, 0x1d4, &ixCLIENT2_CD0[0], sizeof(ixCLIENT2_CD0)/sizeof(ixCLIENT2_CD0[0]), 0, 0 },
+	{ "ixCLIENT2_CD1", REG_SMC, 0x1d8, &ixCLIENT2_CD1[0], sizeof(ixCLIENT2_CD1)/sizeof(ixCLIENT2_CD1[0]), 0, 0 },
+	{ "ixCLIENT2_CD2", REG_SMC, 0x1dc, &ixCLIENT2_CD2[0], sizeof(ixCLIENT2_CD2)/sizeof(ixCLIENT2_CD2[0]), 0, 0 },
+	{ "ixCLIENT2_CD3", REG_SMC, 0x1e0, &ixCLIENT2_CD3[0], sizeof(ixCLIENT2_CD3)/sizeof(ixCLIENT2_CD3[0]), 0, 0 },
+	{ "ixCLIENT2_BM", REG_SMC, 0x1e4, &ixCLIENT2_BM[0], sizeof(ixCLIENT2_BM)/sizeof(ixCLIENT2_BM[0]), 0, 0 },
+	{ "ixCLIENT2_OFFSET", REG_SMC, 0x1e8, &ixCLIENT2_OFFSET[0], sizeof(ixCLIENT2_OFFSET)/sizeof(ixCLIENT2_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT2_STATUS", REG_SMC, 0x1ec, &ixCLIENT2_STATUS[0], sizeof(ixCLIENT2_STATUS)/sizeof(ixCLIENT2_STATUS[0]), 0, 0 },
+	{ "ixCLIENT0_K0", REG_SMC, 0x1f0, &ixCLIENT0_K0[0], sizeof(ixCLIENT0_K0)/sizeof(ixCLIENT0_K0[0]), 0, 0 },
+	{ "ixCLIENT0_K1", REG_SMC, 0x1f4, &ixCLIENT0_K1[0], sizeof(ixCLIENT0_K1)/sizeof(ixCLIENT0_K1[0]), 0, 0 },
+	{ "ixCLIENT0_K2", REG_SMC, 0x1f8, &ixCLIENT0_K2[0], sizeof(ixCLIENT0_K2)/sizeof(ixCLIENT0_K2[0]), 0, 0 },
+	{ "ixCLIENT0_K3", REG_SMC, 0x1fc, &ixCLIENT0_K3[0], sizeof(ixCLIENT0_K3)/sizeof(ixCLIENT0_K3[0]), 0, 0 },
+	{ "ixKSESSION3", REG_SMC, 0x20, &ixKSESSION3[0], sizeof(ixKSESSION3)/sizeof(ixKSESSION3[0]), 0, 0 },
+	{ "ixCLIENT0_CK0", REG_SMC, 0x200, &ixCLIENT0_CK0[0], sizeof(ixCLIENT0_CK0)/sizeof(ixCLIENT0_CK0[0]), 0, 0 },
+	{ "ixCLIENT0_CK1", REG_SMC, 0x204, &ixCLIENT0_CK1[0], sizeof(ixCLIENT0_CK1)/sizeof(ixCLIENT0_CK1[0]), 0, 0 },
+	{ "ixCLIENT0_CK2", REG_SMC, 0x208, &ixCLIENT0_CK2[0], sizeof(ixCLIENT0_CK2)/sizeof(ixCLIENT0_CK2[0]), 0, 0 },
+	{ "ixCLIENT0_CK3", REG_SMC, 0x20c, &ixCLIENT0_CK3[0], sizeof(ixCLIENT0_CK3)/sizeof(ixCLIENT0_CK3[0]), 0, 0 },
+	{ "ixCLIENT0_CD0", REG_SMC, 0x210, &ixCLIENT0_CD0[0], sizeof(ixCLIENT0_CD0)/sizeof(ixCLIENT0_CD0[0]), 0, 0 },
+	{ "ixCLIENT0_CD1", REG_SMC, 0x214, &ixCLIENT0_CD1[0], sizeof(ixCLIENT0_CD1)/sizeof(ixCLIENT0_CD1[0]), 0, 0 },
+	{ "ixCLIENT0_CD2", REG_SMC, 0x218, &ixCLIENT0_CD2[0], sizeof(ixCLIENT0_CD2)/sizeof(ixCLIENT0_CD2[0]), 0, 0 },
+	{ "ixCLIENT0_CD3", REG_SMC, 0x21c, &ixCLIENT0_CD3[0], sizeof(ixCLIENT0_CD3)/sizeof(ixCLIENT0_CD3[0]), 0, 0 },
+	{ "ixCLIENT0_BM", REG_SMC, 0x220, &ixCLIENT0_BM[0], sizeof(ixCLIENT0_BM)/sizeof(ixCLIENT0_BM[0]), 0, 0 },
+	{ "ixCLIENT0_OFFSET", REG_SMC, 0x224, &ixCLIENT0_OFFSET[0], sizeof(ixCLIENT0_OFFSET)/sizeof(ixCLIENT0_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT0_STATUS", REG_SMC, 0x228, &ixCLIENT0_STATUS[0], sizeof(ixCLIENT0_STATUS)/sizeof(ixCLIENT0_STATUS[0]), 0, 0 },
+	{ "ixCLIENT1_K0", REG_SMC, 0x22c, &ixCLIENT1_K0[0], sizeof(ixCLIENT1_K0)/sizeof(ixCLIENT1_K0[0]), 0, 0 },
+	{ "ixCLIENT1_K1", REG_SMC, 0x230, &ixCLIENT1_K1[0], sizeof(ixCLIENT1_K1)/sizeof(ixCLIENT1_K1[0]), 0, 0 },
+	{ "ixCLIENT1_K2", REG_SMC, 0x234, &ixCLIENT1_K2[0], sizeof(ixCLIENT1_K2)/sizeof(ixCLIENT1_K2[0]), 0, 0 },
+	{ "ixCLIENT1_K3", REG_SMC, 0x238, &ixCLIENT1_K3[0], sizeof(ixCLIENT1_K3)/sizeof(ixCLIENT1_K3[0]), 0, 0 },
+	{ "ixCLIENT1_CK0", REG_SMC, 0x23c, &ixCLIENT1_CK0[0], sizeof(ixCLIENT1_CK0)/sizeof(ixCLIENT1_CK0[0]), 0, 0 },
+	{ "ixKSIG0", REG_SMC, 0x24, &ixKSIG0[0], sizeof(ixKSIG0)/sizeof(ixKSIG0[0]), 0, 0 },
+	{ "ixCLIENT1_CK1", REG_SMC, 0x240, &ixCLIENT1_CK1[0], sizeof(ixCLIENT1_CK1)/sizeof(ixCLIENT1_CK1[0]), 0, 0 },
+	{ "ixCLIENT1_CK2", REG_SMC, 0x244, &ixCLIENT1_CK2[0], sizeof(ixCLIENT1_CK2)/sizeof(ixCLIENT1_CK2[0]), 0, 0 },
+	{ "ixCLIENT1_CK3", REG_SMC, 0x248, &ixCLIENT1_CK3[0], sizeof(ixCLIENT1_CK3)/sizeof(ixCLIENT1_CK3[0]), 0, 0 },
+	{ "ixCLIENT1_CD0", REG_SMC, 0x24c, &ixCLIENT1_CD0[0], sizeof(ixCLIENT1_CD0)/sizeof(ixCLIENT1_CD0[0]), 0, 0 },
+	{ "ixCLIENT1_CD1", REG_SMC, 0x250, &ixCLIENT1_CD1[0], sizeof(ixCLIENT1_CD1)/sizeof(ixCLIENT1_CD1[0]), 0, 0 },
+	{ "ixCLIENT1_CD2", REG_SMC, 0x254, &ixCLIENT1_CD2[0], sizeof(ixCLIENT1_CD2)/sizeof(ixCLIENT1_CD2[0]), 0, 0 },
+	{ "ixCLIENT1_CD3", REG_SMC, 0x258, &ixCLIENT1_CD3[0], sizeof(ixCLIENT1_CD3)/sizeof(ixCLIENT1_CD3[0]), 0, 0 },
+	{ "ixCLIENT1_BM", REG_SMC, 0x25c, &ixCLIENT1_BM[0], sizeof(ixCLIENT1_BM)/sizeof(ixCLIENT1_BM[0]), 0, 0 },
+	{ "ixCLIENT1_OFFSET", REG_SMC, 0x260, &ixCLIENT1_OFFSET[0], sizeof(ixCLIENT1_OFFSET)/sizeof(ixCLIENT1_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT1_PORT_STATUS", REG_SMC, 0x264, &ixCLIENT1_PORT_STATUS[0], sizeof(ixCLIENT1_PORT_STATUS)/sizeof(ixCLIENT1_PORT_STATUS[0]), 0, 0 },
+	{ "ixKEFUSE0", REG_SMC, 0x268, &ixKEFUSE0[0], sizeof(ixKEFUSE0)/sizeof(ixKEFUSE0[0]), 0, 0 },
+	{ "ixKEFUSE1", REG_SMC, 0x26c, &ixKEFUSE1[0], sizeof(ixKEFUSE1)/sizeof(ixKEFUSE1[0]), 0, 0 },
+	{ "ixKEFUSE2", REG_SMC, 0x270, &ixKEFUSE2[0], sizeof(ixKEFUSE2)/sizeof(ixKEFUSE2[0]), 0, 0 },
+	{ "ixKEFUSE3", REG_SMC, 0x274, &ixKEFUSE3[0], sizeof(ixKEFUSE3)/sizeof(ixKEFUSE3[0]), 0, 0 },
+	{ "ixHFS_SEED0", REG_SMC, 0x278, &ixHFS_SEED0[0], sizeof(ixHFS_SEED0)/sizeof(ixHFS_SEED0[0]), 0, 0 },
+	{ "ixHFS_SEED1", REG_SMC, 0x27c, &ixHFS_SEED1[0], sizeof(ixHFS_SEED1)/sizeof(ixHFS_SEED1[0]), 0, 0 },
+	{ "ixKSIG1", REG_SMC, 0x28, &ixKSIG1[0], sizeof(ixKSIG1)/sizeof(ixKSIG1[0]), 0, 0 },
+	{ "ixHFS_SEED2", REG_SMC, 0x280, &ixHFS_SEED2[0], sizeof(ixHFS_SEED2)/sizeof(ixHFS_SEED2[0]), 0, 0 },
+	{ "ixHFS_SEED3", REG_SMC, 0x284, &ixHFS_SEED3[0], sizeof(ixHFS_SEED3)/sizeof(ixHFS_SEED3[0]), 0, 0 },
+	{ "ixRINGOSC_MASK", REG_SMC, 0x288, &ixRINGOSC_MASK[0], sizeof(ixRINGOSC_MASK)/sizeof(ixRINGOSC_MASK[0]), 0, 0 },
+	{ "ixCLIENT0_OFFSET_HI", REG_SMC, 0x290, &ixCLIENT0_OFFSET_HI[0], sizeof(ixCLIENT0_OFFSET_HI)/sizeof(ixCLIENT0_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT1_OFFSET_HI", REG_SMC, 0x294, &ixCLIENT1_OFFSET_HI[0], sizeof(ixCLIENT1_OFFSET_HI)/sizeof(ixCLIENT1_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT2_OFFSET_HI", REG_SMC, 0x298, &ixCLIENT2_OFFSET_HI[0], sizeof(ixCLIENT2_OFFSET_HI)/sizeof(ixCLIENT2_OFFSET_HI[0]), 0, 0 },
+	{ "ixSPU_PORT_STATUS", REG_SMC, 0x29c, &ixSPU_PORT_STATUS[0], sizeof(ixSPU_PORT_STATUS)/sizeof(ixSPU_PORT_STATUS[0]), 0, 0 },
+	{ "ixCLIENT3_OFFSET_HI", REG_SMC, 0x2a0, &ixCLIENT3_OFFSET_HI[0], sizeof(ixCLIENT3_OFFSET_HI)/sizeof(ixCLIENT3_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT3_K0", REG_SMC, 0x2a4, &ixCLIENT3_K0[0], sizeof(ixCLIENT3_K0)/sizeof(ixCLIENT3_K0[0]), 0, 0 },
+	{ "ixCLIENT3_K1", REG_SMC, 0x2a8, &ixCLIENT3_K1[0], sizeof(ixCLIENT3_K1)/sizeof(ixCLIENT3_K1[0]), 0, 0 },
+	{ "ixCLIENT3_K2", REG_SMC, 0x2ac, &ixCLIENT3_K2[0], sizeof(ixCLIENT3_K2)/sizeof(ixCLIENT3_K2[0]), 0, 0 },
+	{ "ixCLIENT3_K3", REG_SMC, 0x2b0, &ixCLIENT3_K3[0], sizeof(ixCLIENT3_K3)/sizeof(ixCLIENT3_K3[0]), 0, 0 },
+	{ "ixCLIENT3_CK0", REG_SMC, 0x2b4, &ixCLIENT3_CK0[0], sizeof(ixCLIENT3_CK0)/sizeof(ixCLIENT3_CK0[0]), 0, 0 },
+	{ "ixCLIENT3_CK1", REG_SMC, 0x2b8, &ixCLIENT3_CK1[0], sizeof(ixCLIENT3_CK1)/sizeof(ixCLIENT3_CK1[0]), 0, 0 },
+	{ "ixCLIENT3_CK2", REG_SMC, 0x2bc, &ixCLIENT3_CK2[0], sizeof(ixCLIENT3_CK2)/sizeof(ixCLIENT3_CK2[0]), 0, 0 },
+	{ "ixKSIG2", REG_SMC, 0x2c, &ixKSIG2[0], sizeof(ixKSIG2)/sizeof(ixKSIG2[0]), 0, 0 },
+	{ "ixCLIENT3_CK3", REG_SMC, 0x2c0, &ixCLIENT3_CK3[0], sizeof(ixCLIENT3_CK3)/sizeof(ixCLIENT3_CK3[0]), 0, 0 },
+	{ "ixCLIENT3_CD0", REG_SMC, 0x2c4, &ixCLIENT3_CD0[0], sizeof(ixCLIENT3_CD0)/sizeof(ixCLIENT3_CD0[0]), 0, 0 },
+	{ "ixCLIENT3_CD1", REG_SMC, 0x2c8, &ixCLIENT3_CD1[0], sizeof(ixCLIENT3_CD1)/sizeof(ixCLIENT3_CD1[0]), 0, 0 },
+	{ "ixCLIENT3_CD2", REG_SMC, 0x2cc, &ixCLIENT3_CD2[0], sizeof(ixCLIENT3_CD2)/sizeof(ixCLIENT3_CD2[0]), 0, 0 },
+	{ "ixCLIENT3_CD3", REG_SMC, 0x2d0, &ixCLIENT3_CD3[0], sizeof(ixCLIENT3_CD3)/sizeof(ixCLIENT3_CD3[0]), 0, 0 },
+	{ "ixCLIENT3_BM", REG_SMC, 0x2d4, &ixCLIENT3_BM[0], sizeof(ixCLIENT3_BM)/sizeof(ixCLIENT3_BM[0]), 0, 0 },
+	{ "ixCLIENT3_OFFSET", REG_SMC, 0x2d8, &ixCLIENT3_OFFSET[0], sizeof(ixCLIENT3_OFFSET)/sizeof(ixCLIENT3_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT3_STATUS", REG_SMC, 0x2dc, &ixCLIENT3_STATUS[0], sizeof(ixCLIENT3_STATUS)/sizeof(ixCLIENT3_STATUS[0]), 0, 0 },
+	{ "ixKSIG3", REG_SMC, 0x30, &ixKSIG3[0], sizeof(ixKSIG3)/sizeof(ixKSIG3[0]), 0, 0 },
+	{ "ixEXP0", REG_SMC, 0x34, &ixEXP0[0], sizeof(ixEXP0)/sizeof(ixEXP0[0]), 0, 0 },
+	{ "mmSDMA0_UCODE_ADDR", REG_MMIO, 0x3400, &mmSDMA0_UCODE_ADDR[0], sizeof(mmSDMA0_UCODE_ADDR)/sizeof(mmSDMA0_UCODE_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_UCODE_DATA", REG_MMIO, 0x3401, &mmSDMA0_UCODE_DATA[0], sizeof(mmSDMA0_UCODE_DATA)/sizeof(mmSDMA0_UCODE_DATA[0]), 0, 0 },
+	{ "mmSDMA0_POWER_CNTL", REG_MMIO, 0x3402, &mmSDMA0_POWER_CNTL[0], sizeof(mmSDMA0_POWER_CNTL)/sizeof(mmSDMA0_POWER_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_CLK_CTRL", REG_MMIO, 0x3403, &mmSDMA0_CLK_CTRL[0], sizeof(mmSDMA0_CLK_CTRL)/sizeof(mmSDMA0_CLK_CTRL[0]), 0, 0 },
+	{ "mmSDMA0_CNTL", REG_MMIO, 0x3404, &mmSDMA0_CNTL[0], sizeof(mmSDMA0_CNTL)/sizeof(mmSDMA0_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_CHICKEN_BITS", REG_MMIO, 0x3405, &mmSDMA0_CHICKEN_BITS[0], sizeof(mmSDMA0_CHICKEN_BITS)/sizeof(mmSDMA0_CHICKEN_BITS[0]), 0, 0 },
+	{ "mmSDMA0_TILING_CONFIG", REG_MMIO, 0x3406, &mmSDMA0_TILING_CONFIG[0], sizeof(mmSDMA0_TILING_CONFIG)/sizeof(mmSDMA0_TILING_CONFIG[0]), 0, 0 },
+	{ "mmSDMA0_HASH", REG_MMIO, 0x3407, &mmSDMA0_HASH[0], sizeof(mmSDMA0_HASH)/sizeof(mmSDMA0_HASH[0]), 0, 0 },
+	{ "mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL", REG_MMIO, 0x3408, &mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL[0], sizeof(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL)/sizeof(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x3409, &mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RB_RPTR_FETCH", REG_MMIO, 0x340a, &mmSDMA0_RB_RPTR_FETCH[0], sizeof(mmSDMA0_RB_RPTR_FETCH)/sizeof(mmSDMA0_RB_RPTR_FETCH[0]), 0, 0 },
+	{ "mmSDMA0_IB_OFFSET_FETCH", REG_MMIO, 0x340b, &mmSDMA0_IB_OFFSET_FETCH[0], sizeof(mmSDMA0_IB_OFFSET_FETCH)/sizeof(mmSDMA0_IB_OFFSET_FETCH[0]), 0, 0 },
+	{ "mmSDMA0_PROGRAM", REG_MMIO, 0x340c, &mmSDMA0_PROGRAM[0], sizeof(mmSDMA0_PROGRAM)/sizeof(mmSDMA0_PROGRAM[0]), 0, 0 },
+	{ "mmSDMA0_STATUS_REG", REG_MMIO, 0x340d, &mmSDMA0_STATUS_REG[0], sizeof(mmSDMA0_STATUS_REG)/sizeof(mmSDMA0_STATUS_REG[0]), 0, 0 },
+	{ "mmSDMA0_STATUS1_REG", REG_MMIO, 0x340e, &mmSDMA0_STATUS1_REG[0], sizeof(mmSDMA0_STATUS1_REG)/sizeof(mmSDMA0_STATUS1_REG[0]), 0, 0 },
+	{ "mmSDMA0_PERFMON_CNTL", REG_MMIO, 0x340f, &mmSDMA0_PERFMON_CNTL[0], sizeof(mmSDMA0_PERFMON_CNTL)/sizeof(mmSDMA0_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PERFCOUNTER0_RESULT", REG_MMIO, 0x3410, &mmSDMA0_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER0_RESULT)/sizeof(mmSDMA0_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmSDMA0_PERFCOUNTER1_RESULT", REG_MMIO, 0x3411, &mmSDMA0_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER1_RESULT)/sizeof(mmSDMA0_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmSDMA0_F32_CNTL", REG_MMIO, 0x3412, &mmSDMA0_F32_CNTL[0], sizeof(mmSDMA0_F32_CNTL)/sizeof(mmSDMA0_F32_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_FREEZE", REG_MMIO, 0x3413, &mmSDMA0_FREEZE[0], sizeof(mmSDMA0_FREEZE)/sizeof(mmSDMA0_FREEZE[0]), 0, 0 },
+	{ "mmSDMA0_PHASE0_QUANTUM", REG_MMIO, 0x3414, &mmSDMA0_PHASE0_QUANTUM[0], sizeof(mmSDMA0_PHASE0_QUANTUM)/sizeof(mmSDMA0_PHASE0_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA0_PHASE1_QUANTUM", REG_MMIO, 0x3415, &mmSDMA0_PHASE1_QUANTUM[0], sizeof(mmSDMA0_PHASE1_QUANTUM)/sizeof(mmSDMA0_PHASE1_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA_POWER_GATING", REG_MMIO, 0x3416, &mmSDMA_POWER_GATING[0], sizeof(mmSDMA_POWER_GATING)/sizeof(mmSDMA_POWER_GATING[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_CONFIG", REG_MMIO, 0x3417, &mmSDMA_PGFSM_CONFIG[0], sizeof(mmSDMA_PGFSM_CONFIG)/sizeof(mmSDMA_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_WRITE", REG_MMIO, 0x3418, &mmSDMA_PGFSM_WRITE[0], sizeof(mmSDMA_PGFSM_WRITE)/sizeof(mmSDMA_PGFSM_WRITE[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_READ", REG_MMIO, 0x3419, &mmSDMA_PGFSM_READ[0], sizeof(mmSDMA_PGFSM_READ)/sizeof(mmSDMA_PGFSM_READ[0]), 0, 0 },
+	{ "mmSDMA0_EDC_CONFIG", REG_MMIO, 0x341a, &mmSDMA0_EDC_CONFIG[0], sizeof(mmSDMA0_EDC_CONFIG)/sizeof(mmSDMA0_EDC_CONFIG[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_CNTL", REG_MMIO, 0x3480, &mmSDMA0_GFX_RB_CNTL[0], sizeof(mmSDMA0_GFX_RB_CNTL)/sizeof(mmSDMA0_GFX_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_BASE", REG_MMIO, 0x3481, &mmSDMA0_GFX_RB_BASE[0], sizeof(mmSDMA0_GFX_RB_BASE)/sizeof(mmSDMA0_GFX_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_BASE_HI", REG_MMIO, 0x3482, &mmSDMA0_GFX_RB_BASE_HI[0], sizeof(mmSDMA0_GFX_RB_BASE_HI)/sizeof(mmSDMA0_GFX_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR", REG_MMIO, 0x3483, &mmSDMA0_GFX_RB_RPTR[0], sizeof(mmSDMA0_GFX_RB_RPTR)/sizeof(mmSDMA0_GFX_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR", REG_MMIO, 0x3484, &mmSDMA0_GFX_RB_WPTR[0], sizeof(mmSDMA0_GFX_RB_WPTR)/sizeof(mmSDMA0_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3485, &mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3486, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3487, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x3488, &mmSDMA0_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x3489, &mmSDMA0_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_CNTL", REG_MMIO, 0x348a, &mmSDMA0_GFX_IB_CNTL[0], sizeof(mmSDMA0_GFX_IB_CNTL)/sizeof(mmSDMA0_GFX_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_RPTR", REG_MMIO, 0x348b, &mmSDMA0_GFX_IB_RPTR[0], sizeof(mmSDMA0_GFX_IB_RPTR)/sizeof(mmSDMA0_GFX_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_OFFSET", REG_MMIO, 0x348c, &mmSDMA0_GFX_IB_OFFSET[0], sizeof(mmSDMA0_GFX_IB_OFFSET)/sizeof(mmSDMA0_GFX_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_BASE_LO", REG_MMIO, 0x348d, &mmSDMA0_GFX_IB_BASE_LO[0], sizeof(mmSDMA0_GFX_IB_BASE_LO)/sizeof(mmSDMA0_GFX_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_BASE_HI", REG_MMIO, 0x348e, &mmSDMA0_GFX_IB_BASE_HI[0], sizeof(mmSDMA0_GFX_IB_BASE_HI)/sizeof(mmSDMA0_GFX_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_SIZE", REG_MMIO, 0x348f, &mmSDMA0_GFX_IB_SIZE[0], sizeof(mmSDMA0_GFX_IB_SIZE)/sizeof(mmSDMA0_GFX_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_GFX_SKIP_CNTL", REG_MMIO, 0x3490, &mmSDMA0_GFX_SKIP_CNTL[0], sizeof(mmSDMA0_GFX_SKIP_CNTL)/sizeof(mmSDMA0_GFX_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CONTEXT_STATUS", REG_MMIO, 0x3491, &mmSDMA0_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA0_GFX_CONTEXT_STATUS)/sizeof(mmSDMA0_GFX_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CONTEXT_CNTL", REG_MMIO, 0x3493, &mmSDMA0_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA0_GFX_CONTEXT_CNTL)/sizeof(mmSDMA0_GFX_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_VIRTUAL_ADDR", REG_MMIO, 0x34a7, &mmSDMA0_GFX_VIRTUAL_ADDR[0], sizeof(mmSDMA0_GFX_VIRTUAL_ADDR)/sizeof(mmSDMA0_GFX_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_APE1_CNTL", REG_MMIO, 0x34a8, &mmSDMA0_GFX_APE1_CNTL[0], sizeof(mmSDMA0_GFX_APE1_CNTL)/sizeof(mmSDMA0_GFX_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_WATERMARK", REG_MMIO, 0x34aa, &mmSDMA0_GFX_WATERMARK[0], sizeof(mmSDMA0_GFX_WATERMARK)/sizeof(mmSDMA0_GFX_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_CNTL", REG_MMIO, 0x3500, &mmSDMA0_RLC0_RB_CNTL[0], sizeof(mmSDMA0_RLC0_RB_CNTL)/sizeof(mmSDMA0_RLC0_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_BASE", REG_MMIO, 0x3501, &mmSDMA0_RLC0_RB_BASE[0], sizeof(mmSDMA0_RLC0_RB_BASE)/sizeof(mmSDMA0_RLC0_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_BASE_HI", REG_MMIO, 0x3502, &mmSDMA0_RLC0_RB_BASE_HI[0], sizeof(mmSDMA0_RLC0_RB_BASE_HI)/sizeof(mmSDMA0_RLC0_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR", REG_MMIO, 0x3503, &mmSDMA0_RLC0_RB_RPTR[0], sizeof(mmSDMA0_RLC0_RB_RPTR)/sizeof(mmSDMA0_RLC0_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR", REG_MMIO, 0x3504, &mmSDMA0_RLC0_RB_WPTR[0], sizeof(mmSDMA0_RLC0_RB_WPTR)/sizeof(mmSDMA0_RLC0_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3505, &mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3506, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3507, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x3508, &mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x3509, &mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_CNTL", REG_MMIO, 0x350a, &mmSDMA0_RLC0_IB_CNTL[0], sizeof(mmSDMA0_RLC0_IB_CNTL)/sizeof(mmSDMA0_RLC0_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_RPTR", REG_MMIO, 0x350b, &mmSDMA0_RLC0_IB_RPTR[0], sizeof(mmSDMA0_RLC0_IB_RPTR)/sizeof(mmSDMA0_RLC0_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_OFFSET", REG_MMIO, 0x350c, &mmSDMA0_RLC0_IB_OFFSET[0], sizeof(mmSDMA0_RLC0_IB_OFFSET)/sizeof(mmSDMA0_RLC0_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_BASE_LO", REG_MMIO, 0x350d, &mmSDMA0_RLC0_IB_BASE_LO[0], sizeof(mmSDMA0_RLC0_IB_BASE_LO)/sizeof(mmSDMA0_RLC0_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_BASE_HI", REG_MMIO, 0x350e, &mmSDMA0_RLC0_IB_BASE_HI[0], sizeof(mmSDMA0_RLC0_IB_BASE_HI)/sizeof(mmSDMA0_RLC0_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_SIZE", REG_MMIO, 0x350f, &mmSDMA0_RLC0_IB_SIZE[0], sizeof(mmSDMA0_RLC0_IB_SIZE)/sizeof(mmSDMA0_RLC0_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_SKIP_CNTL", REG_MMIO, 0x3510, &mmSDMA0_RLC0_SKIP_CNTL[0], sizeof(mmSDMA0_RLC0_SKIP_CNTL)/sizeof(mmSDMA0_RLC0_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_CONTEXT_STATUS", REG_MMIO, 0x3511, &mmSDMA0_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC0_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DOORBELL", REG_MMIO, 0x3512, &mmSDMA0_RLC0_DOORBELL[0], sizeof(mmSDMA0_RLC0_DOORBELL)/sizeof(mmSDMA0_RLC0_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_VIRTUAL_ADDR", REG_MMIO, 0x3527, &mmSDMA0_RLC0_VIRTUAL_ADDR[0], sizeof(mmSDMA0_RLC0_VIRTUAL_ADDR)/sizeof(mmSDMA0_RLC0_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_APE1_CNTL", REG_MMIO, 0x3528, &mmSDMA0_RLC0_APE1_CNTL[0], sizeof(mmSDMA0_RLC0_APE1_CNTL)/sizeof(mmSDMA0_RLC0_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DOORBELL_LOG", REG_MMIO, 0x3529, &mmSDMA0_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC0_DOORBELL_LOG)/sizeof(mmSDMA0_RLC0_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_WATERMARK", REG_MMIO, 0x352a, &mmSDMA0_RLC0_WATERMARK[0], sizeof(mmSDMA0_RLC0_WATERMARK)/sizeof(mmSDMA0_RLC0_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_CNTL", REG_MMIO, 0x3580, &mmSDMA0_RLC1_RB_CNTL[0], sizeof(mmSDMA0_RLC1_RB_CNTL)/sizeof(mmSDMA0_RLC1_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_BASE", REG_MMIO, 0x3581, &mmSDMA0_RLC1_RB_BASE[0], sizeof(mmSDMA0_RLC1_RB_BASE)/sizeof(mmSDMA0_RLC1_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_BASE_HI", REG_MMIO, 0x3582, &mmSDMA0_RLC1_RB_BASE_HI[0], sizeof(mmSDMA0_RLC1_RB_BASE_HI)/sizeof(mmSDMA0_RLC1_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR", REG_MMIO, 0x3583, &mmSDMA0_RLC1_RB_RPTR[0], sizeof(mmSDMA0_RLC1_RB_RPTR)/sizeof(mmSDMA0_RLC1_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR", REG_MMIO, 0x3584, &mmSDMA0_RLC1_RB_WPTR[0], sizeof(mmSDMA0_RLC1_RB_WPTR)/sizeof(mmSDMA0_RLC1_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3585, &mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3586, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3587, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x3588, &mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x3589, &mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_CNTL", REG_MMIO, 0x358a, &mmSDMA0_RLC1_IB_CNTL[0], sizeof(mmSDMA0_RLC1_IB_CNTL)/sizeof(mmSDMA0_RLC1_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_RPTR", REG_MMIO, 0x358b, &mmSDMA0_RLC1_IB_RPTR[0], sizeof(mmSDMA0_RLC1_IB_RPTR)/sizeof(mmSDMA0_RLC1_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_OFFSET", REG_MMIO, 0x358c, &mmSDMA0_RLC1_IB_OFFSET[0], sizeof(mmSDMA0_RLC1_IB_OFFSET)/sizeof(mmSDMA0_RLC1_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_BASE_LO", REG_MMIO, 0x358d, &mmSDMA0_RLC1_IB_BASE_LO[0], sizeof(mmSDMA0_RLC1_IB_BASE_LO)/sizeof(mmSDMA0_RLC1_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_BASE_HI", REG_MMIO, 0x358e, &mmSDMA0_RLC1_IB_BASE_HI[0], sizeof(mmSDMA0_RLC1_IB_BASE_HI)/sizeof(mmSDMA0_RLC1_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_SIZE", REG_MMIO, 0x358f, &mmSDMA0_RLC1_IB_SIZE[0], sizeof(mmSDMA0_RLC1_IB_SIZE)/sizeof(mmSDMA0_RLC1_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_SKIP_CNTL", REG_MMIO, 0x3590, &mmSDMA0_RLC1_SKIP_CNTL[0], sizeof(mmSDMA0_RLC1_SKIP_CNTL)/sizeof(mmSDMA0_RLC1_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_CONTEXT_STATUS", REG_MMIO, 0x3591, &mmSDMA0_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC1_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DOORBELL", REG_MMIO, 0x3592, &mmSDMA0_RLC1_DOORBELL[0], sizeof(mmSDMA0_RLC1_DOORBELL)/sizeof(mmSDMA0_RLC1_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_VIRTUAL_ADDR", REG_MMIO, 0x35a7, &mmSDMA0_RLC1_VIRTUAL_ADDR[0], sizeof(mmSDMA0_RLC1_VIRTUAL_ADDR)/sizeof(mmSDMA0_RLC1_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_APE1_CNTL", REG_MMIO, 0x35a8, &mmSDMA0_RLC1_APE1_CNTL[0], sizeof(mmSDMA0_RLC1_APE1_CNTL)/sizeof(mmSDMA0_RLC1_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DOORBELL_LOG", REG_MMIO, 0x35a9, &mmSDMA0_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC1_DOORBELL_LOG)/sizeof(mmSDMA0_RLC1_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_WATERMARK", REG_MMIO, 0x35aa, &mmSDMA0_RLC1_WATERMARK[0], sizeof(mmSDMA0_RLC1_WATERMARK)/sizeof(mmSDMA0_RLC1_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_UCODE_ADDR", REG_MMIO, 0x3600, &mmSDMA1_UCODE_ADDR[0], sizeof(mmSDMA1_UCODE_ADDR)/sizeof(mmSDMA1_UCODE_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_UCODE_DATA", REG_MMIO, 0x3601, &mmSDMA1_UCODE_DATA[0], sizeof(mmSDMA1_UCODE_DATA)/sizeof(mmSDMA1_UCODE_DATA[0]), 0, 0 },
+	{ "mmSDMA1_POWER_CNTL", REG_MMIO, 0x3602, &mmSDMA1_POWER_CNTL[0], sizeof(mmSDMA1_POWER_CNTL)/sizeof(mmSDMA1_POWER_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_CLK_CTRL", REG_MMIO, 0x3603, &mmSDMA1_CLK_CTRL[0], sizeof(mmSDMA1_CLK_CTRL)/sizeof(mmSDMA1_CLK_CTRL[0]), 0, 0 },
+	{ "mmSDMA1_CNTL", REG_MMIO, 0x3604, &mmSDMA1_CNTL[0], sizeof(mmSDMA1_CNTL)/sizeof(mmSDMA1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_CHICKEN_BITS", REG_MMIO, 0x3605, &mmSDMA1_CHICKEN_BITS[0], sizeof(mmSDMA1_CHICKEN_BITS)/sizeof(mmSDMA1_CHICKEN_BITS[0]), 0, 0 },
+	{ "mmSDMA1_TILING_CONFIG", REG_MMIO, 0x3606, &mmSDMA1_TILING_CONFIG[0], sizeof(mmSDMA1_TILING_CONFIG)/sizeof(mmSDMA1_TILING_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_HASH", REG_MMIO, 0x3607, &mmSDMA1_HASH[0], sizeof(mmSDMA1_HASH)/sizeof(mmSDMA1_HASH[0]), 0, 0 },
+	{ "mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL", REG_MMIO, 0x3608, &mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL[0], sizeof(mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL)/sizeof(mmSDMA1_SEM_INCOMPLETE_TIMER_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x3609, &mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RB_RPTR_FETCH", REG_MMIO, 0x360a, &mmSDMA1_RB_RPTR_FETCH[0], sizeof(mmSDMA1_RB_RPTR_FETCH)/sizeof(mmSDMA1_RB_RPTR_FETCH[0]), 0, 0 },
+	{ "mmSDMA1_IB_OFFSET_FETCH", REG_MMIO, 0x360b, &mmSDMA1_IB_OFFSET_FETCH[0], sizeof(mmSDMA1_IB_OFFSET_FETCH)/sizeof(mmSDMA1_IB_OFFSET_FETCH[0]), 0, 0 },
+	{ "mmSDMA1_PROGRAM", REG_MMIO, 0x360c, &mmSDMA1_PROGRAM[0], sizeof(mmSDMA1_PROGRAM)/sizeof(mmSDMA1_PROGRAM[0]), 0, 0 },
+	{ "mmSDMA1_STATUS_REG", REG_MMIO, 0x360d, &mmSDMA1_STATUS_REG[0], sizeof(mmSDMA1_STATUS_REG)/sizeof(mmSDMA1_STATUS_REG[0]), 0, 0 },
+	{ "mmSDMA1_STATUS1_REG", REG_MMIO, 0x360e, &mmSDMA1_STATUS1_REG[0], sizeof(mmSDMA1_STATUS1_REG)/sizeof(mmSDMA1_STATUS1_REG[0]), 0, 0 },
+	{ "mmSDMA1_PERFMON_CNTL", REG_MMIO, 0x360f, &mmSDMA1_PERFMON_CNTL[0], sizeof(mmSDMA1_PERFMON_CNTL)/sizeof(mmSDMA1_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PERFCOUNTER0_RESULT", REG_MMIO, 0x3610, &mmSDMA1_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA1_PERFCOUNTER0_RESULT)/sizeof(mmSDMA1_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmSDMA1_PERFCOUNTER1_RESULT", REG_MMIO, 0x3611, &mmSDMA1_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA1_PERFCOUNTER1_RESULT)/sizeof(mmSDMA1_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmSDMA1_F32_CNTL", REG_MMIO, 0x3612, &mmSDMA1_F32_CNTL[0], sizeof(mmSDMA1_F32_CNTL)/sizeof(mmSDMA1_F32_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_FREEZE", REG_MMIO, 0x3613, &mmSDMA1_FREEZE[0], sizeof(mmSDMA1_FREEZE)/sizeof(mmSDMA1_FREEZE[0]), 0, 0 },
+	{ "mmSDMA1_PHASE0_QUANTUM", REG_MMIO, 0x3614, &mmSDMA1_PHASE0_QUANTUM[0], sizeof(mmSDMA1_PHASE0_QUANTUM)/sizeof(mmSDMA1_PHASE0_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA1_PHASE1_QUANTUM", REG_MMIO, 0x3615, &mmSDMA1_PHASE1_QUANTUM[0], sizeof(mmSDMA1_PHASE1_QUANTUM)/sizeof(mmSDMA1_PHASE1_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA1_EDC_CONFIG", REG_MMIO, 0x361a, &mmSDMA1_EDC_CONFIG[0], sizeof(mmSDMA1_EDC_CONFIG)/sizeof(mmSDMA1_EDC_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_CNTL", REG_MMIO, 0x3680, &mmSDMA1_GFX_RB_CNTL[0], sizeof(mmSDMA1_GFX_RB_CNTL)/sizeof(mmSDMA1_GFX_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_BASE", REG_MMIO, 0x3681, &mmSDMA1_GFX_RB_BASE[0], sizeof(mmSDMA1_GFX_RB_BASE)/sizeof(mmSDMA1_GFX_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_BASE_HI", REG_MMIO, 0x3682, &mmSDMA1_GFX_RB_BASE_HI[0], sizeof(mmSDMA1_GFX_RB_BASE_HI)/sizeof(mmSDMA1_GFX_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR", REG_MMIO, 0x3683, &mmSDMA1_GFX_RB_RPTR[0], sizeof(mmSDMA1_GFX_RB_RPTR)/sizeof(mmSDMA1_GFX_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR", REG_MMIO, 0x3684, &mmSDMA1_GFX_RB_WPTR[0], sizeof(mmSDMA1_GFX_RB_WPTR)/sizeof(mmSDMA1_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3685, &mmSDMA1_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3686, &mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3687, &mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x3688, &mmSDMA1_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x3689, &mmSDMA1_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_CNTL", REG_MMIO, 0x368a, &mmSDMA1_GFX_IB_CNTL[0], sizeof(mmSDMA1_GFX_IB_CNTL)/sizeof(mmSDMA1_GFX_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_RPTR", REG_MMIO, 0x368b, &mmSDMA1_GFX_IB_RPTR[0], sizeof(mmSDMA1_GFX_IB_RPTR)/sizeof(mmSDMA1_GFX_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_OFFSET", REG_MMIO, 0x368c, &mmSDMA1_GFX_IB_OFFSET[0], sizeof(mmSDMA1_GFX_IB_OFFSET)/sizeof(mmSDMA1_GFX_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_BASE_LO", REG_MMIO, 0x368d, &mmSDMA1_GFX_IB_BASE_LO[0], sizeof(mmSDMA1_GFX_IB_BASE_LO)/sizeof(mmSDMA1_GFX_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_BASE_HI", REG_MMIO, 0x368e, &mmSDMA1_GFX_IB_BASE_HI[0], sizeof(mmSDMA1_GFX_IB_BASE_HI)/sizeof(mmSDMA1_GFX_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_SIZE", REG_MMIO, 0x368f, &mmSDMA1_GFX_IB_SIZE[0], sizeof(mmSDMA1_GFX_IB_SIZE)/sizeof(mmSDMA1_GFX_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_GFX_SKIP_CNTL", REG_MMIO, 0x3690, &mmSDMA1_GFX_SKIP_CNTL[0], sizeof(mmSDMA1_GFX_SKIP_CNTL)/sizeof(mmSDMA1_GFX_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CONTEXT_STATUS", REG_MMIO, 0x3691, &mmSDMA1_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA1_GFX_CONTEXT_STATUS)/sizeof(mmSDMA1_GFX_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CONTEXT_CNTL", REG_MMIO, 0x3693, &mmSDMA1_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA1_GFX_CONTEXT_CNTL)/sizeof(mmSDMA1_GFX_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_VIRTUAL_ADDR", REG_MMIO, 0x36a7, &mmSDMA1_GFX_VIRTUAL_ADDR[0], sizeof(mmSDMA1_GFX_VIRTUAL_ADDR)/sizeof(mmSDMA1_GFX_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_APE1_CNTL", REG_MMIO, 0x36a8, &mmSDMA1_GFX_APE1_CNTL[0], sizeof(mmSDMA1_GFX_APE1_CNTL)/sizeof(mmSDMA1_GFX_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_WATERMARK", REG_MMIO, 0x36aa, &mmSDMA1_GFX_WATERMARK[0], sizeof(mmSDMA1_GFX_WATERMARK)/sizeof(mmSDMA1_GFX_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_CNTL", REG_MMIO, 0x3700, &mmSDMA1_RLC0_RB_CNTL[0], sizeof(mmSDMA1_RLC0_RB_CNTL)/sizeof(mmSDMA1_RLC0_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_BASE", REG_MMIO, 0x3701, &mmSDMA1_RLC0_RB_BASE[0], sizeof(mmSDMA1_RLC0_RB_BASE)/sizeof(mmSDMA1_RLC0_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_BASE_HI", REG_MMIO, 0x3702, &mmSDMA1_RLC0_RB_BASE_HI[0], sizeof(mmSDMA1_RLC0_RB_BASE_HI)/sizeof(mmSDMA1_RLC0_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR", REG_MMIO, 0x3703, &mmSDMA1_RLC0_RB_RPTR[0], sizeof(mmSDMA1_RLC0_RB_RPTR)/sizeof(mmSDMA1_RLC0_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR", REG_MMIO, 0x3704, &mmSDMA1_RLC0_RB_WPTR[0], sizeof(mmSDMA1_RLC0_RB_WPTR)/sizeof(mmSDMA1_RLC0_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3705, &mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3706, &mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3707, &mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x3708, &mmSDMA1_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x3709, &mmSDMA1_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_CNTL", REG_MMIO, 0x370a, &mmSDMA1_RLC0_IB_CNTL[0], sizeof(mmSDMA1_RLC0_IB_CNTL)/sizeof(mmSDMA1_RLC0_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_RPTR", REG_MMIO, 0x370b, &mmSDMA1_RLC0_IB_RPTR[0], sizeof(mmSDMA1_RLC0_IB_RPTR)/sizeof(mmSDMA1_RLC0_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_OFFSET", REG_MMIO, 0x370c, &mmSDMA1_RLC0_IB_OFFSET[0], sizeof(mmSDMA1_RLC0_IB_OFFSET)/sizeof(mmSDMA1_RLC0_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_BASE_LO", REG_MMIO, 0x370d, &mmSDMA1_RLC0_IB_BASE_LO[0], sizeof(mmSDMA1_RLC0_IB_BASE_LO)/sizeof(mmSDMA1_RLC0_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_BASE_HI", REG_MMIO, 0x370e, &mmSDMA1_RLC0_IB_BASE_HI[0], sizeof(mmSDMA1_RLC0_IB_BASE_HI)/sizeof(mmSDMA1_RLC0_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_SIZE", REG_MMIO, 0x370f, &mmSDMA1_RLC0_IB_SIZE[0], sizeof(mmSDMA1_RLC0_IB_SIZE)/sizeof(mmSDMA1_RLC0_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_SKIP_CNTL", REG_MMIO, 0x3710, &mmSDMA1_RLC0_SKIP_CNTL[0], sizeof(mmSDMA1_RLC0_SKIP_CNTL)/sizeof(mmSDMA1_RLC0_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_CONTEXT_STATUS", REG_MMIO, 0x3711, &mmSDMA1_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC0_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DOORBELL", REG_MMIO, 0x3712, &mmSDMA1_RLC0_DOORBELL[0], sizeof(mmSDMA1_RLC0_DOORBELL)/sizeof(mmSDMA1_RLC0_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_VIRTUAL_ADDR", REG_MMIO, 0x3727, &mmSDMA1_RLC0_VIRTUAL_ADDR[0], sizeof(mmSDMA1_RLC0_VIRTUAL_ADDR)/sizeof(mmSDMA1_RLC0_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_APE1_CNTL", REG_MMIO, 0x3728, &mmSDMA1_RLC0_APE1_CNTL[0], sizeof(mmSDMA1_RLC0_APE1_CNTL)/sizeof(mmSDMA1_RLC0_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DOORBELL_LOG", REG_MMIO, 0x3729, &mmSDMA1_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC0_DOORBELL_LOG)/sizeof(mmSDMA1_RLC0_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_WATERMARK", REG_MMIO, 0x372a, &mmSDMA1_RLC0_WATERMARK[0], sizeof(mmSDMA1_RLC0_WATERMARK)/sizeof(mmSDMA1_RLC0_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_CNTL", REG_MMIO, 0x3780, &mmSDMA1_RLC1_RB_CNTL[0], sizeof(mmSDMA1_RLC1_RB_CNTL)/sizeof(mmSDMA1_RLC1_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_BASE", REG_MMIO, 0x3781, &mmSDMA1_RLC1_RB_BASE[0], sizeof(mmSDMA1_RLC1_RB_BASE)/sizeof(mmSDMA1_RLC1_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_BASE_HI", REG_MMIO, 0x3782, &mmSDMA1_RLC1_RB_BASE_HI[0], sizeof(mmSDMA1_RLC1_RB_BASE_HI)/sizeof(mmSDMA1_RLC1_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR", REG_MMIO, 0x3783, &mmSDMA1_RLC1_RB_RPTR[0], sizeof(mmSDMA1_RLC1_RB_RPTR)/sizeof(mmSDMA1_RLC1_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR", REG_MMIO, 0x3784, &mmSDMA1_RLC1_RB_WPTR[0], sizeof(mmSDMA1_RLC1_RB_WPTR)/sizeof(mmSDMA1_RLC1_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3785, &mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3786, &mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3787, &mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x3788, &mmSDMA1_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x3789, &mmSDMA1_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_CNTL", REG_MMIO, 0x378a, &mmSDMA1_RLC1_IB_CNTL[0], sizeof(mmSDMA1_RLC1_IB_CNTL)/sizeof(mmSDMA1_RLC1_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_RPTR", REG_MMIO, 0x378b, &mmSDMA1_RLC1_IB_RPTR[0], sizeof(mmSDMA1_RLC1_IB_RPTR)/sizeof(mmSDMA1_RLC1_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_OFFSET", REG_MMIO, 0x378c, &mmSDMA1_RLC1_IB_OFFSET[0], sizeof(mmSDMA1_RLC1_IB_OFFSET)/sizeof(mmSDMA1_RLC1_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_BASE_LO", REG_MMIO, 0x378d, &mmSDMA1_RLC1_IB_BASE_LO[0], sizeof(mmSDMA1_RLC1_IB_BASE_LO)/sizeof(mmSDMA1_RLC1_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_BASE_HI", REG_MMIO, 0x378e, &mmSDMA1_RLC1_IB_BASE_HI[0], sizeof(mmSDMA1_RLC1_IB_BASE_HI)/sizeof(mmSDMA1_RLC1_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_SIZE", REG_MMIO, 0x378f, &mmSDMA1_RLC1_IB_SIZE[0], sizeof(mmSDMA1_RLC1_IB_SIZE)/sizeof(mmSDMA1_RLC1_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_SKIP_CNTL", REG_MMIO, 0x3790, &mmSDMA1_RLC1_SKIP_CNTL[0], sizeof(mmSDMA1_RLC1_SKIP_CNTL)/sizeof(mmSDMA1_RLC1_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_CONTEXT_STATUS", REG_MMIO, 0x3791, &mmSDMA1_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC1_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DOORBELL", REG_MMIO, 0x3792, &mmSDMA1_RLC1_DOORBELL[0], sizeof(mmSDMA1_RLC1_DOORBELL)/sizeof(mmSDMA1_RLC1_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_VIRTUAL_ADDR", REG_MMIO, 0x37a7, &mmSDMA1_RLC1_VIRTUAL_ADDR[0], sizeof(mmSDMA1_RLC1_VIRTUAL_ADDR)/sizeof(mmSDMA1_RLC1_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_APE1_CNTL", REG_MMIO, 0x37a8, &mmSDMA1_RLC1_APE1_CNTL[0], sizeof(mmSDMA1_RLC1_APE1_CNTL)/sizeof(mmSDMA1_RLC1_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DOORBELL_LOG", REG_MMIO, 0x37a9, &mmSDMA1_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC1_DOORBELL_LOG)/sizeof(mmSDMA1_RLC1_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_WATERMARK", REG_MMIO, 0x37aa, &mmSDMA1_RLC1_WATERMARK[0], sizeof(mmSDMA1_RLC1_WATERMARK)/sizeof(mmSDMA1_RLC1_WATERMARK[0]), 0, 0 },
+	{ "ixEXP1", REG_SMC, 0x38, &ixEXP1[0], sizeof(ixEXP1)/sizeof(ixEXP1[0]), 0, 0 },
+	{ "mmSRBM_CNTL", REG_MMIO, 0x390, &mmSRBM_CNTL[0], sizeof(mmSRBM_CNTL)/sizeof(mmSRBM_CNTL[0]), 0, 0 },
+	{ "mmSRBM_GFX_CNTL", REG_MMIO, 0x391, &mmSRBM_GFX_CNTL[0], sizeof(mmSRBM_GFX_CNTL)/sizeof(mmSRBM_GFX_CNTL[0]), 0, 0 },
+	{ "mmSRBM_STATUS2", REG_MMIO, 0x393, &mmSRBM_STATUS2[0], sizeof(mmSRBM_STATUS2)/sizeof(mmSRBM_STATUS2[0]), 0, 0 },
+	{ "mmSRBM_STATUS", REG_MMIO, 0x394, &mmSRBM_STATUS[0], sizeof(mmSRBM_STATUS)/sizeof(mmSRBM_STATUS[0]), 0, 0 },
+	{ "mmSRBM_CAM_INDEX", REG_MMIO, 0x396, &mmSRBM_CAM_INDEX[0], sizeof(mmSRBM_CAM_INDEX)/sizeof(mmSRBM_CAM_INDEX[0]), 0, 0 },
+	{ "mmSRBM_CAM_DATA", REG_MMIO, 0x397, &mmSRBM_CAM_DATA[0], sizeof(mmSRBM_CAM_DATA)/sizeof(mmSRBM_CAM_DATA[0]), 0, 0 },
+	{ "mmSRBM_SOFT_RESET", REG_MMIO, 0x398, &mmSRBM_SOFT_RESET[0], sizeof(mmSRBM_SOFT_RESET)/sizeof(mmSRBM_SOFT_RESET[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_CNTL", REG_MMIO, 0x399, &mmSRBM_DEBUG_CNTL[0], sizeof(mmSRBM_DEBUG_CNTL)/sizeof(mmSRBM_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_DATA", REG_MMIO, 0x39a, &mmSRBM_DEBUG_DATA[0], sizeof(mmSRBM_DEBUG_DATA)/sizeof(mmSRBM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmSRBM_CHIP_REVISION", REG_MMIO, 0x39b, &mmSRBM_CHIP_REVISION[0], sizeof(mmSRBM_CHIP_REVISION)/sizeof(mmSRBM_CHIP_REVISION[0]), 0, 0 },
+	{ "mmCC_SYS_RB_REDUNDANCY", REG_MMIO, 0x39f, &mmCC_SYS_RB_REDUNDANCY[0], sizeof(mmCC_SYS_RB_REDUNDANCY)/sizeof(mmCC_SYS_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmCC_SYS_RB_BACKEND_DISABLE", REG_MMIO, 0x3a0, &mmCC_SYS_RB_BACKEND_DISABLE[0], sizeof(mmCC_SYS_RB_BACKEND_DISABLE)/sizeof(mmCC_SYS_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmGC_USER_SYS_RB_BACKEND_DISABLE", REG_MMIO, 0x3a1, &mmGC_USER_SYS_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_SYS_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_SYS_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmSRBM_DEBUG", REG_MMIO, 0x3a4, &mmSRBM_DEBUG[0], sizeof(mmSRBM_DEBUG)/sizeof(mmSRBM_DEBUG[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x3a5, &mmSRBM_DEBUG_SNAPSHOT[0], sizeof(mmSRBM_DEBUG_SNAPSHOT)/sizeof(mmSRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
+	{ "mmSRBM_READ_ERROR", REG_MMIO, 0x3a6, &mmSRBM_READ_ERROR[0], sizeof(mmSRBM_READ_ERROR)/sizeof(mmSRBM_READ_ERROR[0]), 0, 0 },
+	{ "mmSRBM_INT_CNTL", REG_MMIO, 0x3a8, &mmSRBM_INT_CNTL[0], sizeof(mmSRBM_INT_CNTL)/sizeof(mmSRBM_INT_CNTL[0]), 0, 0 },
+	{ "mmSRBM_INT_STATUS", REG_MMIO, 0x3a9, &mmSRBM_INT_STATUS[0], sizeof(mmSRBM_INT_STATUS)/sizeof(mmSRBM_INT_STATUS[0]), 0, 0 },
+	{ "mmSRBM_INT_ACK", REG_MMIO, 0x3aa, &mmSRBM_INT_ACK[0], sizeof(mmSRBM_INT_ACK)/sizeof(mmSRBM_INT_ACK[0]), 0, 0 },
+	{ "mmSRBM_MC_CLKEN_CNTL", REG_MMIO, 0x3b3, &mmSRBM_MC_CLKEN_CNTL[0], sizeof(mmSRBM_MC_CLKEN_CNTL)/sizeof(mmSRBM_MC_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_SYS_CLKEN_CNTL", REG_MMIO, 0x3b4, &mmSRBM_SYS_CLKEN_CNTL[0], sizeof(mmSRBM_SYS_CLKEN_CNTL)/sizeof(mmSRBM_SYS_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_VCE_CLKEN_CNTL", REG_MMIO, 0x3b5, &mmSRBM_VCE_CLKEN_CNTL[0], sizeof(mmSRBM_VCE_CLKEN_CNTL)/sizeof(mmSRBM_VCE_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_UVD_CLKEN_CNTL", REG_MMIO, 0x3b6, &mmSRBM_UVD_CLKEN_CNTL[0], sizeof(mmSRBM_UVD_CLKEN_CNTL)/sizeof(mmSRBM_UVD_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_SDMA_CLKEN_CNTL", REG_MMIO, 0x3b7, &mmSRBM_SDMA_CLKEN_CNTL[0], sizeof(mmSRBM_SDMA_CLKEN_CNTL)/sizeof(mmSRBM_SDMA_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_SAM_CLKEN_CNTL", REG_MMIO, 0x3b8, &mmSRBM_SAM_CLKEN_CNTL[0], sizeof(mmSRBM_SAM_CLKEN_CNTL)/sizeof(mmSRBM_SAM_CLKEN_CNTL[0]), 0, 0 },
+	{ "ixEXP2", REG_SMC, 0x3c, &ixEXP2[0], sizeof(ixEXP2)/sizeof(ixEXP2[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CNTL", REG_MMIO, 0x3ec, &mmXDMA_MSTR_CNTL[0], sizeof(mmXDMA_MSTR_CNTL)/sizeof(mmXDMA_MSTR_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_STATUS", REG_MMIO, 0x3ed, &mmXDMA_MSTR_STATUS[0], sizeof(mmXDMA_MSTR_STATUS)/sizeof(mmXDMA_MSTR_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_CLIENT_CONFIG", REG_MMIO, 0x3ee, &mmXDMA_MSTR_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_MSTR_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR", REG_MMIO, 0x3ef, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH", REG_MMIO, 0x3f0, &mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_LOCAL_SURFACE_PITCH", REG_MMIO, 0x3f1, &mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0], sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH)/sizeof(mmXDMA_MSTR_LOCAL_SURFACE_PITCH[0]), 0, 0 },
+	{ "mmXDMA_MSTR_CMD_URGENT_CNTL", REG_MMIO, 0x3f2, &mmXDMA_MSTR_CMD_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL)/sizeof(mmXDMA_MSTR_CMD_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_URGENT_CNTL", REG_MMIO, 0x3f3, &mmXDMA_MSTR_MEM_URGENT_CNTL[0], sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL)/sizeof(mmXDMA_MSTR_MEM_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG", REG_MMIO, 0x3f4, &mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG[0], sizeof(mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG)/sizeof(mmXDMA_MSTR_MEM_UNDERFLOW_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_MSTR_PCIE_NACK_STATUS", REG_MMIO, 0x3f5, &mmXDMA_MSTR_PCIE_NACK_STATUS[0], sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS)/sizeof(mmXDMA_MSTR_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_MEM_NACK_STATUS", REG_MMIO, 0x3f6, &mmXDMA_MSTR_MEM_NACK_STATUS[0], sizeof(mmXDMA_MSTR_MEM_NACK_STATUS)/sizeof(mmXDMA_MSTR_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_MSTR_VSYNC_GSL_CHECK", REG_MMIO, 0x3f7, &mmXDMA_MSTR_VSYNC_GSL_CHECK[0], sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK)/sizeof(mmXDMA_MSTR_VSYNC_GSL_CHECK[0]), 0, 0 },
+	{ "ixKHFS0", REG_SMC, 0x4, &ixKHFS0[0], sizeof(ixKHFS0)/sizeof(ixKHFS0[0]), 0, 0 },
+	{ "ixEXP3", REG_SMC, 0x40, &ixEXP3[0], sizeof(ixEXP3)/sizeof(ixEXP3[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x400, &mmXDMA_MSTR_PIPE_CNTL[0], sizeof(mmXDMA_MSTR_PIPE_CNTL)/sizeof(mmXDMA_MSTR_PIPE_CNTL[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_READ_COMMAND", REG_MMIO, 0x401, &mmXDMA_MSTR_READ_COMMAND[0], sizeof(mmXDMA_MSTR_READ_COMMAND)/sizeof(mmXDMA_MSTR_READ_COMMAND[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x402, &mmXDMA_MSTR_CHANNEL_DIM[0], sizeof(mmXDMA_MSTR_CHANNEL_DIM)/sizeof(mmXDMA_MSTR_CHANNEL_DIM[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_HEIGHT", REG_MMIO, 0x403, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_HEIGHT", REG_MMIO, 0x403, &mmXDMA_MSTR_HEIGHT[0], sizeof(mmXDMA_MSTR_HEIGHT)/sizeof(mmXDMA_MSTR_HEIGHT[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x404, &mmXDMA_MSTR_REMOTE_SURFACE_BASE[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x405, &mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x406, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x407, &mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x408, &mmXDMA_MSTR_CACHE_BASE_ADDR[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x409, &mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0], sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH)/sizeof(mmXDMA_MSTR_CACHE_BASE_ADDR_HIGH[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x40a, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x40a, &mmXDMA_MSTR_CACHE_PITCH[0], sizeof(mmXDMA_MSTR_CACHE_PITCH)/sizeof(mmXDMA_MSTR_CACHE_PITCH[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_CHANNEL_START", REG_MMIO, 0x40b, &mmXDMA_MSTR_CHANNEL_START[0], sizeof(mmXDMA_MSTR_CHANNEL_START)/sizeof(mmXDMA_MSTR_CHANNEL_START[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x40c, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x40c, &mmXDMA_MSTR_MEM_OVERFLOW_CNTL[0], sizeof(mmXDMA_MSTR_MEM_OVERFLOW_CNTL)/sizeof(mmXDMA_MSTR_MEM_OVERFLOW_CNTL[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x40d, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x40d, &mmXDMA_MSTR_MEM_UNDERFLOW_CNTL[0], sizeof(mmXDMA_MSTR_MEM_UNDERFLOW_CNTL)/sizeof(mmXDMA_MSTR_MEM_UNDERFLOW_CNTL[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x40e, &mmXDMA_MSTR_PERFMEAS_STATUS[0], sizeof(mmXDMA_MSTR_PERFMEAS_STATUS)/sizeof(mmXDMA_MSTR_PERFMEAS_STATUS[0]), 0, 0 },
+	{ "mmMDMA_PIPE0_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, NULL, 0, 0, 0 },
+	{ "mmXDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x40f, &mmXDMA_MSTR_PERFMEAS_CNTL[0], sizeof(mmXDMA_MSTR_PERFMEAS_CNTL)/sizeof(mmXDMA_MSTR_PERFMEAS_CNTL[0]), 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x410, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x411, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x412, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_HEIGHT", REG_MMIO, 0x413, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x414, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x415, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x416, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x417, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x418, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x419, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x41a, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x41b, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x41c, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x41d, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x41e, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE1_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x41f, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x420, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x421, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x422, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_HEIGHT", REG_MMIO, 0x423, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x424, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x425, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x426, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x427, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x428, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x429, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x42a, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x42b, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x42c, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x42d, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x42e, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE2_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x42f, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x430, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x431, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x432, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_HEIGHT", REG_MMIO, 0x433, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x434, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x435, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x436, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x437, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x438, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x439, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x43a, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x43b, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x43c, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x43d, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x43e, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE3_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x43f, NULL, 0, 0, 0 },
+	{ "ixEXP4", REG_SMC, 0x44, &ixEXP4[0], sizeof(ixEXP4)/sizeof(ixEXP4[0]), 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x440, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x441, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x442, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_HEIGHT", REG_MMIO, 0x443, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x444, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x445, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x446, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x447, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x448, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x449, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x44a, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x44b, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x44c, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x44d, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x44e, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE4_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x44f, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_PIPE_CNTL", REG_MMIO, 0x450, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_READ_COMMAND", REG_MMIO, 0x451, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_DIM", REG_MMIO, 0x452, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_HEIGHT", REG_MMIO, 0x453, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE", REG_MMIO, 0x454, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH", REG_MMIO, 0x455, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS", REG_MMIO, 0x456, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x457, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR", REG_MMIO, 0x458, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_CACHE_BASE_ADDR_HIGH", REG_MMIO, 0x459, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_CACHE_PITCH", REG_MMIO, 0x45a, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_CHANNEL_START", REG_MMIO, 0x45b, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_MEM_OVERFLOW_CNTL", REG_MMIO, 0x45c, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_MEM_UNDERFLOW_CNTL", REG_MMIO, 0x45d, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_STATUS", REG_MMIO, 0x45e, NULL, 0, 0, 0 },
+	{ "mmMDMA_PIPE5_XDMA_MSTR_PERFMEAS_CNTL", REG_MMIO, 0x45f, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CNTL", REG_MMIO, 0x460, &mmXDMA_SLV_CNTL[0], sizeof(mmXDMA_SLV_CNTL)/sizeof(mmXDMA_SLV_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_CLIENT_CONFIG", REG_MMIO, 0x461, &mmXDMA_SLV_MEM_CLIENT_CONFIG[0], sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG)/sizeof(mmXDMA_SLV_MEM_CLIENT_CONFIG[0]), 0, 0 },
+	{ "mmXDMA_SLV_SLS_PITCH", REG_MMIO, 0x462, &mmXDMA_SLV_SLS_PITCH[0], sizeof(mmXDMA_SLV_SLS_PITCH)/sizeof(mmXDMA_SLV_SLS_PITCH[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_URGENT_CNTL", REG_MMIO, 0x463, &mmXDMA_SLV_READ_URGENT_CNTL[0], sizeof(mmXDMA_SLV_READ_URGENT_CNTL)/sizeof(mmXDMA_SLV_READ_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_WRITE_URGENT_CNTL", REG_MMIO, 0x464, &mmXDMA_SLV_WRITE_URGENT_CNTL[0], sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL)/sizeof(mmXDMA_SLV_WRITE_URGENT_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_WB_RATE_CNTL", REG_MMIO, 0x465, &mmXDMA_SLV_WB_RATE_CNTL[0], sizeof(mmXDMA_SLV_WB_RATE_CNTL)/sizeof(mmXDMA_SLV_WB_RATE_CNTL[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_MINMAX", REG_MMIO, 0x466, &mmXDMA_SLV_READ_LATENCY_MINMAX[0], sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX)/sizeof(mmXDMA_SLV_READ_LATENCY_MINMAX[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_AVE", REG_MMIO, 0x467, &mmXDMA_SLV_READ_LATENCY_AVE[0], sizeof(mmXDMA_SLV_READ_LATENCY_AVE)/sizeof(mmXDMA_SLV_READ_LATENCY_AVE[0]), 0, 0 },
+	{ "mmXDMA_SLV_PCIE_NACK_STATUS", REG_MMIO, 0x468, &mmXDMA_SLV_PCIE_NACK_STATUS[0], sizeof(mmXDMA_SLV_PCIE_NACK_STATUS)/sizeof(mmXDMA_SLV_PCIE_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_MEM_NACK_STATUS", REG_MMIO, 0x469, &mmXDMA_SLV_MEM_NACK_STATUS[0], sizeof(mmXDMA_SLV_MEM_NACK_STATUS)/sizeof(mmXDMA_SLV_MEM_NACK_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_RDRET_BUF_STATUS", REG_MMIO, 0x46a, &mmXDMA_SLV_RDRET_BUF_STATUS[0], sizeof(mmXDMA_SLV_RDRET_BUF_STATUS)/sizeof(mmXDMA_SLV_RDRET_BUF_STATUS[0]), 0, 0 },
+	{ "mmXDMA_SLV_READ_LATENCY_TIMER", REG_MMIO, 0x46b, &mmXDMA_SLV_READ_LATENCY_TIMER[0], sizeof(mmXDMA_SLV_READ_LATENCY_TIMER)/sizeof(mmXDMA_SLV_READ_LATENCY_TIMER[0]), 0, 0 },
+	{ "mmXDMA_SLV_FLIP_PENDING", REG_MMIO, 0x46c, &mmXDMA_SLV_FLIP_PENDING[0], sizeof(mmXDMA_SLV_FLIP_PENDING)/sizeof(mmXDMA_SLV_FLIP_PENDING[0]), 0, 0 },
+	{ "mmSDMA_CHANNEL0_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x470, &mmXDMA_SLV_CHANNEL_CNTL[0], sizeof(mmXDMA_SLV_CHANNEL_CNTL)/sizeof(mmXDMA_SLV_CHANNEL_CNTL[0]), 0, 0 },
+	{ "mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x471, &mmXDMA_SLV_REMOTE_GPU_ADDRESS[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS[0]), 0, 0 },
+	{ "mmSDMA_CHANNEL0_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, NULL, 0, 0, 0 },
+	{ "mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x472, &mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0], sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH)/sizeof(mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH[0]), 0, 0 },
+	{ "mmSDMA_CHANNEL1_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x478, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x479, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL1_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x47a, NULL, 0, 0, 0 },
+	{ "ixEXP5", REG_SMC, 0x48, &ixEXP5[0], sizeof(ixEXP5)/sizeof(ixEXP5[0]), 0, 0 },
+	{ "mmSDMA_CHANNEL2_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x480, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x481, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL2_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x482, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL3_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x488, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x489, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL3_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x48a, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL4_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x490, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x491, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL4_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x492, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL5_XDMA_SLV_CHANNEL_CNTL", REG_MMIO, 0x498, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS", REG_MMIO, 0x499, NULL, 0, 0, 0 },
+	{ "mmSDMA_CHANNEL5_XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH", REG_MMIO, 0x49a, NULL, 0, 0, 0 },
+	{ "ixEXP6", REG_SMC, 0x4c, &ixEXP6[0], sizeof(ixEXP6)/sizeof(ixEXP6[0]), 0, 0 },
+	{ "ixEXP7", REG_SMC, 0x50, &ixEXP7[0], sizeof(ixEXP7)/sizeof(ixEXP7[0]), 0, 0 },
+	{ "ixLX0", REG_SMC, 0x54, &ixLX0[0], sizeof(ixLX0)/sizeof(ixLX0[0]), 0, 0 },
+	{ "ixLX1", REG_SMC, 0x58, &ixLX1[0], sizeof(ixLX1)/sizeof(ixLX1[0]), 0, 0 },
+	{ "ixLX2", REG_SMC, 0x5c, &ixLX2[0], sizeof(ixLX2)/sizeof(ixLX2[0]), 0, 0 },
+	{ "ixLX3", REG_SMC, 0x60, &ixLX3[0], sizeof(ixLX3)/sizeof(ixLX3[0]), 0, 0 },
+	{ "mmSRBM_PERFMON_CNTL", REG_MMIO, 0x700, &mmSRBM_PERFMON_CNTL[0], sizeof(mmSRBM_PERFMON_CNTL)/sizeof(mmSRBM_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0x701, &mmSRBM_PERFCOUNTER0_SELECT[0], sizeof(mmSRBM_PERFCOUNTER0_SELECT)/sizeof(mmSRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0x702, &mmSRBM_PERFCOUNTER1_SELECT[0], sizeof(mmSRBM_PERFCOUNTER1_SELECT)/sizeof(mmSRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_LO", REG_MMIO, 0x703, &mmSRBM_PERFCOUNTER0_LO[0], sizeof(mmSRBM_PERFCOUNTER0_LO)/sizeof(mmSRBM_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_HI", REG_MMIO, 0x704, &mmSRBM_PERFCOUNTER0_HI[0], sizeof(mmSRBM_PERFCOUNTER0_HI)/sizeof(mmSRBM_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_LO", REG_MMIO, 0x705, &mmSRBM_PERFCOUNTER1_LO[0], sizeof(mmSRBM_PERFCOUNTER1_LO)/sizeof(mmSRBM_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_HI", REG_MMIO, 0x706, &mmSRBM_PERFCOUNTER1_HI[0], sizeof(mmSRBM_PERFCOUNTER1_HI)/sizeof(mmSRBM_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "ixKHFS1", REG_SMC, 0x8, &ixKHFS1[0], sizeof(ixKHFS1)/sizeof(ixKHFS1[0]), 0, 0 },
+	{ "mmHDP_HOST_PATH_CNTL", REG_MMIO, 0xb00, &mmHDP_HOST_PATH_CNTL[0], sizeof(mmHDP_HOST_PATH_CNTL)/sizeof(mmHDP_HOST_PATH_CNTL[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_BASE", REG_MMIO, 0xb01, &mmHDP_NONSURFACE_BASE[0], sizeof(mmHDP_NONSURFACE_BASE)/sizeof(mmHDP_NONSURFACE_BASE[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_INFO", REG_MMIO, 0xb02, &mmHDP_NONSURFACE_INFO[0], sizeof(mmHDP_NONSURFACE_INFO)/sizeof(mmHDP_NONSURFACE_INFO[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_SIZE", REG_MMIO, 0xb03, &mmHDP_NONSURFACE_SIZE[0], sizeof(mmHDP_NONSURFACE_SIZE)/sizeof(mmHDP_NONSURFACE_SIZE[0]), 0, 0 },
+	{ "mmHDP_NONSURF_FLAGS", REG_MMIO, 0xbc9, &mmHDP_NONSURF_FLAGS[0], sizeof(mmHDP_NONSURF_FLAGS)/sizeof(mmHDP_NONSURF_FLAGS[0]), 0, 0 },
+	{ "mmHDP_NONSURF_FLAGS_CLR", REG_MMIO, 0xbca, &mmHDP_NONSURF_FLAGS_CLR[0], sizeof(mmHDP_NONSURF_FLAGS_CLR)/sizeof(mmHDP_NONSURF_FLAGS_CLR[0]), 0, 0 },
+	{ "mmHDP_SW_SEMAPHORE", REG_MMIO, 0xbcb, &mmHDP_SW_SEMAPHORE[0], sizeof(mmHDP_SW_SEMAPHORE)/sizeof(mmHDP_SW_SEMAPHORE[0]), 0, 0 },
+	{ "mmHDP_DEBUG0", REG_MMIO, 0xbcc, &mmHDP_DEBUG0[0], sizeof(mmHDP_DEBUG0)/sizeof(mmHDP_DEBUG0[0]), 0, 0 },
+	{ "mmHDP_DEBUG1", REG_MMIO, 0xbcd, &mmHDP_DEBUG1[0], sizeof(mmHDP_DEBUG1)/sizeof(mmHDP_DEBUG1[0]), 0, 0 },
+	{ "mmHDP_LAST_SURFACE_HIT", REG_MMIO, 0xbce, &mmHDP_LAST_SURFACE_HIT[0], sizeof(mmHDP_LAST_SURFACE_HIT)/sizeof(mmHDP_LAST_SURFACE_HIT[0]), 0, 0 },
+	{ "mmHDP_TILING_CONFIG", REG_MMIO, 0xbcf, &mmHDP_TILING_CONFIG[0], sizeof(mmHDP_TILING_CONFIG)/sizeof(mmHDP_TILING_CONFIG[0]), 0, 0 },
+	{ "mmHDP_SC_MULTI_CHIP_CNTL", REG_MMIO, 0xbd0, &mmHDP_SC_MULTI_CHIP_CNTL[0], sizeof(mmHDP_SC_MULTI_CHIP_CNTL)/sizeof(mmHDP_SC_MULTI_CHIP_CNTL[0]), 0, 0 },
+	{ "mmHDP_OUTSTANDING_REQ", REG_MMIO, 0xbd1, &mmHDP_OUTSTANDING_REQ[0], sizeof(mmHDP_OUTSTANDING_REQ)/sizeof(mmHDP_OUTSTANDING_REQ[0]), 0, 0 },
+	{ "mmHDP_ADDR_CONFIG", REG_MMIO, 0xbd2, &mmHDP_ADDR_CONFIG[0], sizeof(mmHDP_ADDR_CONFIG)/sizeof(mmHDP_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmHDP_MISC_CNTL", REG_MMIO, 0xbd3, &mmHDP_MISC_CNTL[0], sizeof(mmHDP_MISC_CNTL)/sizeof(mmHDP_MISC_CNTL[0]), 0, 0 },
+	{ "mmHDP_MEM_POWER_LS", REG_MMIO, 0xbd4, &mmHDP_MEM_POWER_LS[0], sizeof(mmHDP_MEM_POWER_LS)/sizeof(mmHDP_MEM_POWER_LS[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_PREFETCH", REG_MMIO, 0xbd5, &mmHDP_NONSURFACE_PREFETCH[0], sizeof(mmHDP_NONSURFACE_PREFETCH)/sizeof(mmHDP_NONSURFACE_PREFETCH[0]), 0, 0 },
+	{ "mmHDP_MEMIO_CNTL", REG_MMIO, 0xbf6, &mmHDP_MEMIO_CNTL[0], sizeof(mmHDP_MEMIO_CNTL)/sizeof(mmHDP_MEMIO_CNTL[0]), 0, 0 },
+	{ "mmHDP_MEMIO_ADDR", REG_MMIO, 0xbf7, &mmHDP_MEMIO_ADDR[0], sizeof(mmHDP_MEMIO_ADDR)/sizeof(mmHDP_MEMIO_ADDR[0]), 0, 0 },
+	{ "mmHDP_MEMIO_STATUS", REG_MMIO, 0xbf8, &mmHDP_MEMIO_STATUS[0], sizeof(mmHDP_MEMIO_STATUS)/sizeof(mmHDP_MEMIO_STATUS[0]), 0, 0 },
+	{ "mmHDP_MEMIO_WR_DATA", REG_MMIO, 0xbf9, &mmHDP_MEMIO_WR_DATA[0], sizeof(mmHDP_MEMIO_WR_DATA)/sizeof(mmHDP_MEMIO_WR_DATA[0]), 0, 0 },
+	{ "mmHDP_MEMIO_RD_DATA", REG_MMIO, 0xbfa, &mmHDP_MEMIO_RD_DATA[0], sizeof(mmHDP_MEMIO_RD_DATA)/sizeof(mmHDP_MEMIO_RD_DATA[0]), 0, 0 },
+	{ "ixKHFS2", REG_SMC, 0xc, &ixKHFS2[0], sizeof(ixKHFS2)/sizeof(ixKHFS2[0]), 0, 0 },
+	{ "mmHDP_XDP_DIRECT2HDP_FIRST", REG_MMIO, 0xc00, &mmHDP_XDP_DIRECT2HDP_FIRST[0], sizeof(mmHDP_XDP_DIRECT2HDP_FIRST)/sizeof(mmHDP_XDP_DIRECT2HDP_FIRST[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_FLUSH", REG_MMIO, 0xc01, &mmHDP_XDP_D2H_FLUSH[0], sizeof(mmHDP_XDP_D2H_FLUSH)/sizeof(mmHDP_XDP_D2H_FLUSH[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_BAR_UPDATE", REG_MMIO, 0xc02, &mmHDP_XDP_D2H_BAR_UPDATE[0], sizeof(mmHDP_XDP_D2H_BAR_UPDATE)/sizeof(mmHDP_XDP_D2H_BAR_UPDATE[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_3", REG_MMIO, 0xc03, &mmHDP_XDP_D2H_RSVD_3[0], sizeof(mmHDP_XDP_D2H_RSVD_3)/sizeof(mmHDP_XDP_D2H_RSVD_3[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_4", REG_MMIO, 0xc04, &mmHDP_XDP_D2H_RSVD_4[0], sizeof(mmHDP_XDP_D2H_RSVD_4)/sizeof(mmHDP_XDP_D2H_RSVD_4[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_5", REG_MMIO, 0xc05, &mmHDP_XDP_D2H_RSVD_5[0], sizeof(mmHDP_XDP_D2H_RSVD_5)/sizeof(mmHDP_XDP_D2H_RSVD_5[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_6", REG_MMIO, 0xc06, &mmHDP_XDP_D2H_RSVD_6[0], sizeof(mmHDP_XDP_D2H_RSVD_6)/sizeof(mmHDP_XDP_D2H_RSVD_6[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_7", REG_MMIO, 0xc07, &mmHDP_XDP_D2H_RSVD_7[0], sizeof(mmHDP_XDP_D2H_RSVD_7)/sizeof(mmHDP_XDP_D2H_RSVD_7[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_8", REG_MMIO, 0xc08, &mmHDP_XDP_D2H_RSVD_8[0], sizeof(mmHDP_XDP_D2H_RSVD_8)/sizeof(mmHDP_XDP_D2H_RSVD_8[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_9", REG_MMIO, 0xc09, &mmHDP_XDP_D2H_RSVD_9[0], sizeof(mmHDP_XDP_D2H_RSVD_9)/sizeof(mmHDP_XDP_D2H_RSVD_9[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_10", REG_MMIO, 0xc0a, &mmHDP_XDP_D2H_RSVD_10[0], sizeof(mmHDP_XDP_D2H_RSVD_10)/sizeof(mmHDP_XDP_D2H_RSVD_10[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_11", REG_MMIO, 0xc0b, &mmHDP_XDP_D2H_RSVD_11[0], sizeof(mmHDP_XDP_D2H_RSVD_11)/sizeof(mmHDP_XDP_D2H_RSVD_11[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_12", REG_MMIO, 0xc0c, &mmHDP_XDP_D2H_RSVD_12[0], sizeof(mmHDP_XDP_D2H_RSVD_12)/sizeof(mmHDP_XDP_D2H_RSVD_12[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_13", REG_MMIO, 0xc0d, &mmHDP_XDP_D2H_RSVD_13[0], sizeof(mmHDP_XDP_D2H_RSVD_13)/sizeof(mmHDP_XDP_D2H_RSVD_13[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_14", REG_MMIO, 0xc0e, &mmHDP_XDP_D2H_RSVD_14[0], sizeof(mmHDP_XDP_D2H_RSVD_14)/sizeof(mmHDP_XDP_D2H_RSVD_14[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_15", REG_MMIO, 0xc0f, &mmHDP_XDP_D2H_RSVD_15[0], sizeof(mmHDP_XDP_D2H_RSVD_15)/sizeof(mmHDP_XDP_D2H_RSVD_15[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_16", REG_MMIO, 0xc10, &mmHDP_XDP_D2H_RSVD_16[0], sizeof(mmHDP_XDP_D2H_RSVD_16)/sizeof(mmHDP_XDP_D2H_RSVD_16[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_17", REG_MMIO, 0xc11, &mmHDP_XDP_D2H_RSVD_17[0], sizeof(mmHDP_XDP_D2H_RSVD_17)/sizeof(mmHDP_XDP_D2H_RSVD_17[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_18", REG_MMIO, 0xc12, &mmHDP_XDP_D2H_RSVD_18[0], sizeof(mmHDP_XDP_D2H_RSVD_18)/sizeof(mmHDP_XDP_D2H_RSVD_18[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_19", REG_MMIO, 0xc13, &mmHDP_XDP_D2H_RSVD_19[0], sizeof(mmHDP_XDP_D2H_RSVD_19)/sizeof(mmHDP_XDP_D2H_RSVD_19[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_20", REG_MMIO, 0xc14, &mmHDP_XDP_D2H_RSVD_20[0], sizeof(mmHDP_XDP_D2H_RSVD_20)/sizeof(mmHDP_XDP_D2H_RSVD_20[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_21", REG_MMIO, 0xc15, &mmHDP_XDP_D2H_RSVD_21[0], sizeof(mmHDP_XDP_D2H_RSVD_21)/sizeof(mmHDP_XDP_D2H_RSVD_21[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_22", REG_MMIO, 0xc16, &mmHDP_XDP_D2H_RSVD_22[0], sizeof(mmHDP_XDP_D2H_RSVD_22)/sizeof(mmHDP_XDP_D2H_RSVD_22[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_23", REG_MMIO, 0xc17, &mmHDP_XDP_D2H_RSVD_23[0], sizeof(mmHDP_XDP_D2H_RSVD_23)/sizeof(mmHDP_XDP_D2H_RSVD_23[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_24", REG_MMIO, 0xc18, &mmHDP_XDP_D2H_RSVD_24[0], sizeof(mmHDP_XDP_D2H_RSVD_24)/sizeof(mmHDP_XDP_D2H_RSVD_24[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_25", REG_MMIO, 0xc19, &mmHDP_XDP_D2H_RSVD_25[0], sizeof(mmHDP_XDP_D2H_RSVD_25)/sizeof(mmHDP_XDP_D2H_RSVD_25[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_26", REG_MMIO, 0xc1a, &mmHDP_XDP_D2H_RSVD_26[0], sizeof(mmHDP_XDP_D2H_RSVD_26)/sizeof(mmHDP_XDP_D2H_RSVD_26[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_27", REG_MMIO, 0xc1b, &mmHDP_XDP_D2H_RSVD_27[0], sizeof(mmHDP_XDP_D2H_RSVD_27)/sizeof(mmHDP_XDP_D2H_RSVD_27[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_28", REG_MMIO, 0xc1c, &mmHDP_XDP_D2H_RSVD_28[0], sizeof(mmHDP_XDP_D2H_RSVD_28)/sizeof(mmHDP_XDP_D2H_RSVD_28[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_29", REG_MMIO, 0xc1d, &mmHDP_XDP_D2H_RSVD_29[0], sizeof(mmHDP_XDP_D2H_RSVD_29)/sizeof(mmHDP_XDP_D2H_RSVD_29[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_30", REG_MMIO, 0xc1e, &mmHDP_XDP_D2H_RSVD_30[0], sizeof(mmHDP_XDP_D2H_RSVD_30)/sizeof(mmHDP_XDP_D2H_RSVD_30[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_31", REG_MMIO, 0xc1f, &mmHDP_XDP_D2H_RSVD_31[0], sizeof(mmHDP_XDP_D2H_RSVD_31)/sizeof(mmHDP_XDP_D2H_RSVD_31[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_32", REG_MMIO, 0xc20, &mmHDP_XDP_D2H_RSVD_32[0], sizeof(mmHDP_XDP_D2H_RSVD_32)/sizeof(mmHDP_XDP_D2H_RSVD_32[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_33", REG_MMIO, 0xc21, &mmHDP_XDP_D2H_RSVD_33[0], sizeof(mmHDP_XDP_D2H_RSVD_33)/sizeof(mmHDP_XDP_D2H_RSVD_33[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_34", REG_MMIO, 0xc22, &mmHDP_XDP_D2H_RSVD_34[0], sizeof(mmHDP_XDP_D2H_RSVD_34)/sizeof(mmHDP_XDP_D2H_RSVD_34[0]), 0, 0 },
+	{ "mmHDP_XDP_DIRECT2HDP_LAST", REG_MMIO, 0xc23, &mmHDP_XDP_DIRECT2HDP_LAST[0], sizeof(mmHDP_XDP_DIRECT2HDP_LAST)/sizeof(mmHDP_XDP_DIRECT2HDP_LAST[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR_CFG", REG_MMIO, 0xc24, &mmHDP_XDP_P2P_BAR_CFG[0], sizeof(mmHDP_XDP_P2P_BAR_CFG)/sizeof(mmHDP_XDP_P2P_BAR_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_OFFSET", REG_MMIO, 0xc25, &mmHDP_XDP_P2P_MBX_OFFSET[0], sizeof(mmHDP_XDP_P2P_MBX_OFFSET)/sizeof(mmHDP_XDP_P2P_MBX_OFFSET[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR0", REG_MMIO, 0xc26, &mmHDP_XDP_P2P_MBX_ADDR0[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR0)/sizeof(mmHDP_XDP_P2P_MBX_ADDR0[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR1", REG_MMIO, 0xc27, &mmHDP_XDP_P2P_MBX_ADDR1[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR1)/sizeof(mmHDP_XDP_P2P_MBX_ADDR1[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR2", REG_MMIO, 0xc28, &mmHDP_XDP_P2P_MBX_ADDR2[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR2)/sizeof(mmHDP_XDP_P2P_MBX_ADDR2[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR3", REG_MMIO, 0xc29, &mmHDP_XDP_P2P_MBX_ADDR3[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR3)/sizeof(mmHDP_XDP_P2P_MBX_ADDR3[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR4", REG_MMIO, 0xc2a, &mmHDP_XDP_P2P_MBX_ADDR4[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR4)/sizeof(mmHDP_XDP_P2P_MBX_ADDR4[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR5", REG_MMIO, 0xc2b, &mmHDP_XDP_P2P_MBX_ADDR5[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR5)/sizeof(mmHDP_XDP_P2P_MBX_ADDR5[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR6", REG_MMIO, 0xc2c, &mmHDP_XDP_P2P_MBX_ADDR6[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR6)/sizeof(mmHDP_XDP_P2P_MBX_ADDR6[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_MBX_MC_CFG", REG_MMIO, 0xc2d, &mmHDP_XDP_HDP_MBX_MC_CFG[0], sizeof(mmHDP_XDP_HDP_MBX_MC_CFG)/sizeof(mmHDP_XDP_HDP_MBX_MC_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_MC_CFG", REG_MMIO, 0xc2e, &mmHDP_XDP_HDP_MC_CFG[0], sizeof(mmHDP_XDP_HDP_MC_CFG)/sizeof(mmHDP_XDP_HDP_MC_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HST_CFG", REG_MMIO, 0xc2f, &mmHDP_XDP_HST_CFG[0], sizeof(mmHDP_XDP_HST_CFG)/sizeof(mmHDP_XDP_HST_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_SID_CFG", REG_MMIO, 0xc30, &mmHDP_XDP_SID_CFG[0], sizeof(mmHDP_XDP_SID_CFG)/sizeof(mmHDP_XDP_SID_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_IPH_CFG", REG_MMIO, 0xc31, &mmHDP_XDP_HDP_IPH_CFG[0], sizeof(mmHDP_XDP_HDP_IPH_CFG)/sizeof(mmHDP_XDP_HDP_IPH_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_SRBM_CFG", REG_MMIO, 0xc32, &mmHDP_XDP_SRBM_CFG[0], sizeof(mmHDP_XDP_SRBM_CFG)/sizeof(mmHDP_XDP_SRBM_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_CGTT_BLK_CTRL", REG_MMIO, 0xc33, &mmHDP_XDP_CGTT_BLK_CTRL[0], sizeof(mmHDP_XDP_CGTT_BLK_CTRL)/sizeof(mmHDP_XDP_CGTT_BLK_CTRL[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR0", REG_MMIO, 0xc34, &mmHDP_XDP_P2P_BAR0[0], sizeof(mmHDP_XDP_P2P_BAR0)/sizeof(mmHDP_XDP_P2P_BAR0[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR1", REG_MMIO, 0xc35, &mmHDP_XDP_P2P_BAR1[0], sizeof(mmHDP_XDP_P2P_BAR1)/sizeof(mmHDP_XDP_P2P_BAR1[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR2", REG_MMIO, 0xc36, &mmHDP_XDP_P2P_BAR2[0], sizeof(mmHDP_XDP_P2P_BAR2)/sizeof(mmHDP_XDP_P2P_BAR2[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR3", REG_MMIO, 0xc37, &mmHDP_XDP_P2P_BAR3[0], sizeof(mmHDP_XDP_P2P_BAR3)/sizeof(mmHDP_XDP_P2P_BAR3[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR4", REG_MMIO, 0xc38, &mmHDP_XDP_P2P_BAR4[0], sizeof(mmHDP_XDP_P2P_BAR4)/sizeof(mmHDP_XDP_P2P_BAR4[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR5", REG_MMIO, 0xc39, &mmHDP_XDP_P2P_BAR5[0], sizeof(mmHDP_XDP_P2P_BAR5)/sizeof(mmHDP_XDP_P2P_BAR5[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR6", REG_MMIO, 0xc3a, &mmHDP_XDP_P2P_BAR6[0], sizeof(mmHDP_XDP_P2P_BAR6)/sizeof(mmHDP_XDP_P2P_BAR6[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR7", REG_MMIO, 0xc3b, &mmHDP_XDP_P2P_BAR7[0], sizeof(mmHDP_XDP_P2P_BAR7)/sizeof(mmHDP_XDP_P2P_BAR7[0]), 0, 0 },
+	{ "mmHDP_XDP_FLUSH_ARMED_STS", REG_MMIO, 0xc3c, &mmHDP_XDP_FLUSH_ARMED_STS[0], sizeof(mmHDP_XDP_FLUSH_ARMED_STS)/sizeof(mmHDP_XDP_FLUSH_ARMED_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_FLUSH_CNTR0_STS", REG_MMIO, 0xc3d, &mmHDP_XDP_FLUSH_CNTR0_STS[0], sizeof(mmHDP_XDP_FLUSH_CNTR0_STS)/sizeof(mmHDP_XDP_FLUSH_CNTR0_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_BUSY_STS", REG_MMIO, 0xc3e, &mmHDP_XDP_BUSY_STS[0], sizeof(mmHDP_XDP_BUSY_STS)/sizeof(mmHDP_XDP_BUSY_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_STICKY", REG_MMIO, 0xc3f, &mmHDP_XDP_STICKY[0], sizeof(mmHDP_XDP_STICKY)/sizeof(mmHDP_XDP_STICKY[0]), 0, 0 },
+	{ "mmHDP_XDP_CHKN", REG_MMIO, 0xc40, &mmHDP_XDP_CHKN[0], sizeof(mmHDP_XDP_CHKN)/sizeof(mmHDP_XDP_CHKN[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_ADDR", REG_MMIO, 0xc41, &mmHDP_XDP_DBG_ADDR[0], sizeof(mmHDP_XDP_DBG_ADDR)/sizeof(mmHDP_XDP_DBG_ADDR[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_DATA", REG_MMIO, 0xc42, &mmHDP_XDP_DBG_DATA[0], sizeof(mmHDP_XDP_DBG_DATA)/sizeof(mmHDP_XDP_DBG_DATA[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_MASK", REG_MMIO, 0xc43, &mmHDP_XDP_DBG_MASK[0], sizeof(mmHDP_XDP_DBG_MASK)/sizeof(mmHDP_XDP_DBG_MASK[0]), 0, 0 },
+	{ "mmHDP_XDP_BARS_ADDR_39_36", REG_MMIO, 0xc44, &mmHDP_XDP_BARS_ADDR_39_36[0], sizeof(mmHDP_XDP_BARS_ADDR_39_36)/sizeof(mmHDP_XDP_BARS_ADDR_39_36[0]), 0, 0 },
+	{ "mmIH_VMID_0_LUT", REG_MMIO, 0xf50, &mmIH_VMID_0_LUT[0], sizeof(mmIH_VMID_0_LUT)/sizeof(mmIH_VMID_0_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_1_LUT", REG_MMIO, 0xf51, &mmIH_VMID_1_LUT[0], sizeof(mmIH_VMID_1_LUT)/sizeof(mmIH_VMID_1_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_2_LUT", REG_MMIO, 0xf52, &mmIH_VMID_2_LUT[0], sizeof(mmIH_VMID_2_LUT)/sizeof(mmIH_VMID_2_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_3_LUT", REG_MMIO, 0xf53, &mmIH_VMID_3_LUT[0], sizeof(mmIH_VMID_3_LUT)/sizeof(mmIH_VMID_3_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_4_LUT", REG_MMIO, 0xf54, &mmIH_VMID_4_LUT[0], sizeof(mmIH_VMID_4_LUT)/sizeof(mmIH_VMID_4_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_5_LUT", REG_MMIO, 0xf55, &mmIH_VMID_5_LUT[0], sizeof(mmIH_VMID_5_LUT)/sizeof(mmIH_VMID_5_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_6_LUT", REG_MMIO, 0xf56, &mmIH_VMID_6_LUT[0], sizeof(mmIH_VMID_6_LUT)/sizeof(mmIH_VMID_6_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_7_LUT", REG_MMIO, 0xf57, &mmIH_VMID_7_LUT[0], sizeof(mmIH_VMID_7_LUT)/sizeof(mmIH_VMID_7_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_8_LUT", REG_MMIO, 0xf58, &mmIH_VMID_8_LUT[0], sizeof(mmIH_VMID_8_LUT)/sizeof(mmIH_VMID_8_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_9_LUT", REG_MMIO, 0xf59, &mmIH_VMID_9_LUT[0], sizeof(mmIH_VMID_9_LUT)/sizeof(mmIH_VMID_9_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_10_LUT", REG_MMIO, 0xf5a, &mmIH_VMID_10_LUT[0], sizeof(mmIH_VMID_10_LUT)/sizeof(mmIH_VMID_10_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_11_LUT", REG_MMIO, 0xf5b, &mmIH_VMID_11_LUT[0], sizeof(mmIH_VMID_11_LUT)/sizeof(mmIH_VMID_11_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_12_LUT", REG_MMIO, 0xf5c, &mmIH_VMID_12_LUT[0], sizeof(mmIH_VMID_12_LUT)/sizeof(mmIH_VMID_12_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_13_LUT", REG_MMIO, 0xf5d, &mmIH_VMID_13_LUT[0], sizeof(mmIH_VMID_13_LUT)/sizeof(mmIH_VMID_13_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_14_LUT", REG_MMIO, 0xf5e, &mmIH_VMID_14_LUT[0], sizeof(mmIH_VMID_14_LUT)/sizeof(mmIH_VMID_14_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_15_LUT", REG_MMIO, 0xf5f, &mmIH_VMID_15_LUT[0], sizeof(mmIH_VMID_15_LUT)/sizeof(mmIH_VMID_15_LUT[0]), 0, 0 },
+	{ "mmIH_RB_CNTL", REG_MMIO, 0xf80, &mmIH_RB_CNTL[0], sizeof(mmIH_RB_CNTL)/sizeof(mmIH_RB_CNTL[0]), 0, 0 },
+	{ "mmIH_RB_BASE", REG_MMIO, 0xf81, &mmIH_RB_BASE[0], sizeof(mmIH_RB_BASE)/sizeof(mmIH_RB_BASE[0]), 0, 0 },
+	{ "mmIH_RB_RPTR", REG_MMIO, 0xf82, &mmIH_RB_RPTR[0], sizeof(mmIH_RB_RPTR)/sizeof(mmIH_RB_RPTR[0]), 0, 0 },
+	{ "mmIH_RB_WPTR", REG_MMIO, 0xf83, &mmIH_RB_WPTR[0], sizeof(mmIH_RB_WPTR)/sizeof(mmIH_RB_WPTR[0]), 0, 0 },
+	{ "mmIH_RB_WPTR_ADDR_HI", REG_MMIO, 0xf84, &mmIH_RB_WPTR_ADDR_HI[0], sizeof(mmIH_RB_WPTR_ADDR_HI)/sizeof(mmIH_RB_WPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmIH_RB_WPTR_ADDR_LO", REG_MMIO, 0xf85, &mmIH_RB_WPTR_ADDR_LO[0], sizeof(mmIH_RB_WPTR_ADDR_LO)/sizeof(mmIH_RB_WPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmIH_CNTL", REG_MMIO, 0xf86, &mmIH_CNTL[0], sizeof(mmIH_CNTL)/sizeof(mmIH_CNTL[0]), 0, 0 },
+	{ "mmIH_LEVEL_STATUS", REG_MMIO, 0xf87, &mmIH_LEVEL_STATUS[0], sizeof(mmIH_LEVEL_STATUS)/sizeof(mmIH_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmIH_STATUS", REG_MMIO, 0xf88, &mmIH_STATUS[0], sizeof(mmIH_STATUS)/sizeof(mmIH_STATUS[0]), 0, 0 },
+	{ "mmIH_PERFMON_CNTL", REG_MMIO, 0xf89, &mmIH_PERFMON_CNTL[0], sizeof(mmIH_PERFMON_CNTL)/sizeof(mmIH_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmIH_PERFCOUNTER0_RESULT", REG_MMIO, 0xf8a, &mmIH_PERFCOUNTER0_RESULT[0], sizeof(mmIH_PERFCOUNTER0_RESULT)/sizeof(mmIH_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmIH_PERFCOUNTER1_RESULT", REG_MMIO, 0xf8b, &mmIH_PERFCOUNTER1_RESULT[0], sizeof(mmIH_PERFCOUNTER1_RESULT)/sizeof(mmIH_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmIH_ADVFAULT_CNTL", REG_MMIO, 0xf8c, &mmIH_ADVFAULT_CNTL[0], sizeof(mmIH_ADVFAULT_CNTL)/sizeof(mmIH_ADVFAULT_CNTL[0]), 0, 0 },
+	{ "mmSEM_MCIF_CONFIG", REG_MMIO, 0xf90, &mmSEM_MCIF_CONFIG[0], sizeof(mmSEM_MCIF_CONFIG)/sizeof(mmSEM_MCIF_CONFIG[0]), 0, 0 },
+	{ "mmSDMA_CONFIG", REG_MMIO, 0xf91, &mmSDMA_CONFIG[0], sizeof(mmSDMA_CONFIG)/sizeof(mmSDMA_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_CONFIG", REG_MMIO, 0xf92, &mmSDMA1_CONFIG[0], sizeof(mmSDMA1_CONFIG)/sizeof(mmSDMA1_CONFIG[0]), 0, 0 },
+	{ "mmUVD_CONFIG", REG_MMIO, 0xf93, &mmUVD_CONFIG[0], sizeof(mmUVD_CONFIG)/sizeof(mmUVD_CONFIG[0]), 0, 0 },
+	{ "mmVCE_CONFIG", REG_MMIO, 0xf94, &mmVCE_CONFIG[0], sizeof(mmVCE_CONFIG)/sizeof(mmVCE_CONFIG[0]), 0, 0 },
+	{ "mmACP_CONFIG", REG_MMIO, 0xf95, &mmACP_CONFIG[0], sizeof(mmACP_CONFIG)/sizeof(mmACP_CONFIG[0]), 0, 0 },
+	{ "mmCPG_CONFIG", REG_MMIO, 0xf96, &mmCPG_CONFIG[0], sizeof(mmCPG_CONFIG)/sizeof(mmCPG_CONFIG[0]), 0, 0 },
+	{ "mmCPC1_CONFIG", REG_MMIO, 0xf97, &mmCPC1_CONFIG[0], sizeof(mmCPC1_CONFIG)/sizeof(mmCPC1_CONFIG[0]), 0, 0 },
+	{ "mmCPC2_CONFIG", REG_MMIO, 0xf98, &mmCPC2_CONFIG[0], sizeof(mmCPC2_CONFIG)/sizeof(mmCPC2_CONFIG[0]), 0, 0 },
+	{ "mmSEM_STATUS", REG_MMIO, 0xf99, &mmSEM_STATUS[0], sizeof(mmSEM_STATUS)/sizeof(mmSEM_STATUS[0]), 0, 0 },
+	{ "mmSEM_EDC_CONFIG", REG_MMIO, 0xf9a, &mmSEM_EDC_CONFIG[0], sizeof(mmSEM_EDC_CONFIG)/sizeof(mmSEM_EDC_CONFIG[0]), 0, 0 },
+	{ "mmSEM_MAILBOX_CLIENTCONFIG", REG_MMIO, 0xf9b, &mmSEM_MAILBOX_CLIENTCONFIG[0], sizeof(mmSEM_MAILBOX_CLIENTCONFIG)/sizeof(mmSEM_MAILBOX_CLIENTCONFIG[0]), 0, 0 },
+	{ "mmSEM_MAILBOX", REG_MMIO, 0xf9c, &mmSEM_MAILBOX[0], sizeof(mmSEM_MAILBOX)/sizeof(mmSEM_MAILBOX[0]), 0, 0 },
+	{ "mmSEM_MAILBOX_CONTROL", REG_MMIO, 0xf9d, &mmSEM_MAILBOX_CONTROL[0], sizeof(mmSEM_MAILBOX_CONTROL)/sizeof(mmSEM_MAILBOX_CONTROL[0]), 0, 0 },
+	{ "mmSEM_CHICKEN_BITS", REG_MMIO, 0xf9e, &mmSEM_CHICKEN_BITS[0], sizeof(mmSEM_CHICKEN_BITS)/sizeof(mmSEM_CHICKEN_BITS[0]), 0, 0 },
diff --git a/src/lib/ip/oss30.c b/src/lib/ip/oss30.c
new file mode 100644
index 0000000..a44421a
--- /dev/null
+++ b/src/lib/ip/oss30.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "oss30_bits.i"
+
+static const struct umr_reg oss30_registers[] = {
+#include "oss30_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_oss30(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "oss30";
+	ip->no_regs = sizeof(oss30_registers)/sizeof(oss30_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(oss30_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, oss30_registers, sizeof(oss30_registers));
+	return ip;
+}
diff --git a/src/lib/ip/oss30_bits.i b/src/lib/ip/oss30_bits.i
new file mode 100644
index 0000000..c423f70
--- /dev/null
+++ b/src/lib/ip/oss30_bits.i
@@ -0,0 +1,3133 @@
+static struct umr_bitfield ixDH_TEST[] = {
+	 { "DH_TEST", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_DRM_ID_STRAPS[] = {
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+	 { "ATI_REV_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_TEST_DEBUG_INDEX[] = {
+	 { "DC_TEST_DEBUG_INDEX", 0, 7, &umr_bitfield_default },
+	 { "DC_TEST_DEBUG_WRITE_EN", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmDC_TEST_DEBUG_DATA[] = {
+	 { "DC_TEST_DEBUG_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSESSION3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_PORT_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKEFUSE3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHFS_SEED3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRINGOSC_MASK[] = {
+	 { "MASK", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT0_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT1_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT2_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPU_PORT_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT3_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_OFFSET_HI[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_K0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_K1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_K2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_K3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_CK0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_CK1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_CK2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKSIG3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_CK3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_CD0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_CD1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_CD2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_CD3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_BM[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_OFFSET[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCLIENT4_STATUS[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UCODE_ADDR[] = {
+	 { "VALUE", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_UCODE_DATA[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_POWER_CNTL[] = {
+	 { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "MEM_POWER_LS_EN", 9, 9, &umr_bitfield_default },
+	 { "MEM_POWER_DS_EN", 10, 10, &umr_bitfield_default },
+	 { "MEM_POWER_SD_EN", 11, 11, &umr_bitfield_default },
+	 { "MEM_POWER_DELAY", 12, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CNTL[] = {
+	 { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ATC_L1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MIDCMD_PREEMPT_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 11, 16, &umr_bitfield_default },
+	 { "MIDCMD_WORLDSWITCH_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 22, 27, &umr_bitfield_default },
+	 { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "IB_PREEMPT_INT_ENABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CHICKEN_BITS[] = {
+	 { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STALL_ON_TRANS_FULL_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STALL_ON_NO_FREE_DATA_BUFFER_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
+	 { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
+	 { "CE_AFIFO_WATERMARK", 26, 27, &umr_bitfield_default },
+	 { "CE_DFIFO_WATERMARK", 28, 29, &umr_bitfield_default },
+	 { "CE_LFIFO_WATERMARK", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_TILING_CONFIG[] = {
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_HASH[] = {
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "BANK_BITS", 4, 6, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 8, 10, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[] = {
+	 { "TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RB_RPTR_FETCH[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_IB_OFFSET_FETCH[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PROGRAM[] = {
+	 { "STREAM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS_REG[] = {
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "REG_IDLE", 1, 1, &umr_bitfield_default },
+	 { "RB_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
+	 { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
+	 { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
+	 { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
+	 { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
+	 { "INSIDE_IB", 9, 9, &umr_bitfield_default },
+	 { "EX_IDLE", 10, 10, &umr_bitfield_default },
+	 { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
+	 { "PACKET_READY", 12, 12, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
+	 { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
+	 { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
+	 { "DELTA_RPTR_FULL", 16, 16, &umr_bitfield_default },
+	 { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
+	 { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
+	 { "DELTA_RPTR_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
+	 { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
+	 { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
+	 { "SEM_IDLE", 26, 26, &umr_bitfield_default },
+	 { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
+	 { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
+	 { "INT_IDLE", 30, 30, &umr_bitfield_default },
+	 { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS1_REG[] = {
+	 { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
+	 { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
+	 { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
+	 { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
+	 { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
+	 { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
+	 { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
+	 { "CE_CMD_IDLE", 9, 9, &umr_bitfield_default },
+	 { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
+	 { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
+	 { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RD_BURST_CNTL[] = {
+	 { "RD_BURST", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_F32_CNTL[] = {
+	 { "HALT", 0, 0, &umr_bitfield_default },
+	 { "STEP", 1, 1, &umr_bitfield_default },
+	 { "DBG_SELECT_BITS", 2, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_FREEZE[] = {
+	 { "FREEZE", 4, 4, &umr_bitfield_default },
+	 { "FROZEN", 5, 5, &umr_bitfield_default },
+	 { "F32_FREEZE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHASE0_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PHASE1_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_POWER_GATING[] = {
+	 { "PG_CNTL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "AUTOMATIC_STATUS_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "PG_STATE_VALID", 2, 2, &umr_bitfield_default },
+	 { "PG_CNTL_STATUS", 4, 5, &umr_bitfield_default },
+	 { "SDMA0_ON_CONDITION", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_ON_CONDITION", 7, 7, &umr_bitfield_default },
+	 { "POWER_OFF_DELAY", 8, 19, &umr_bitfield_default },
+	 { "POWER_ON_DELAY", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "WRITE", 12, 12, &umr_bitfield_default },
+	 { "READ", 13, 13, &umr_bitfield_default },
+	 { "SRBM_OVERRIDE", 27, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_WRITE[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_PGFSM_READ[] = {
+	 { "VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+	 { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_BA_THRESHOLD[] = {
+	 { "READ_THRES", 0, 9, &umr_bitfield_default },
+	 { "WRITE_THRES", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ID[] = {
+	 { "DEVICE_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VERSION[] = {
+	 { "VALUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VM_CNTL[] = {
+	 { "CMD", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VM_CTX_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VM_CTX_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_STATUS2_REG[] = {
+	 { "ID", 0, 1, &umr_bitfield_default },
+	 { "F32_INSTR_PTR", 2, 11, &umr_bitfield_default },
+	 { "CURRENT_FCN_IDLE", 14, 15, &umr_bitfield_default },
+	 { "CMD_OP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ACTIVE_FCN_ID[] = {
+	 { "VFID", 0, 3, &umr_bitfield_default },
+	 { "VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VM_CTX_CNTL[] = {
+	 { "PRIV", 0, 0, &umr_bitfield_default },
+	 { "VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ATOMIC_CNTL[] = {
+	 { "LOOP_TIMER", 0, 30, &umr_bitfield_default },
+	 { "ATOMIC_RTN_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ATOMIC_PREOP_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_ATOMIC_PREOP_HI[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_POWER_CNTL_IDLE[] = {
+	 { "DELAY1", 0, 15, &umr_bitfield_default },
+	 { "DELAY2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERF_REG_TYPE0[] = {
+	 { "SDMA0_PERFMON_CNTL", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_PERFCOUNTER0_RESULT", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_PERFCOUNTER1_RESULT", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_31_3", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE0[] = {
+	 { "SDMA0_GFX_RB_CNTL", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_BASE", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_BASE_HI", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_RPTR", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR_POLL_CNTL", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR_POLL_ADDR_HI", 6, 6, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_WPTR_POLL_ADDR_LO", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_RPTR_ADDR_HI", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_GFX_RB_RPTR_ADDR_LO", 9, 9, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_CNTL", 10, 10, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_RPTR", 11, 11, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_BASE_LO", 13, 13, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_BASE_HI", 14, 14, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_SIZE", 15, 15, &umr_bitfield_default },
+	 { "SDMA0_GFX_SKIP_CNTL", 16, 16, &umr_bitfield_default },
+	 { "SDMA0_GFX_CONTEXT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "SDMA0_GFX_DOORBELL", 18, 18, &umr_bitfield_default },
+	 { "SDMA0_GFX_CONTEXT_CNTL", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE1[] = {
+	 { "SDMA0_GFX_VIRTUAL_ADDR", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_GFX_APE1_CNTL", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_GFX_DOORBELL_LOG", 9, 9, &umr_bitfield_default },
+	 { "SDMA0_GFX_WATERMARK", 10, 10, &umr_bitfield_default },
+	 { "VOID_REG1", 11, 11, &umr_bitfield_default },
+	 { "SDMA0_GFX_CSA_ADDR_LO", 12, 12, &umr_bitfield_default },
+	 { "SDMA0_GFX_CSA_ADDR_HI", 13, 13, &umr_bitfield_default },
+	 { "VOID_REG2", 14, 14, &umr_bitfield_default },
+	 { "SDMA0_GFX_IB_SUB_REMAIN", 15, 15, &umr_bitfield_default },
+	 { "SDMA0_GFX_PREEMPT", 16, 16, &umr_bitfield_default },
+	 { "SDMA0_GFX_DUMMY_REG", 17, 17, &umr_bitfield_default },
+	 { "RESERVED", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_CONTEXT_REG_TYPE2[] = {
+	 { "SDMA0_GFX_MIDCMD_DATA0", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA1", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA2", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA3", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA4", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_DATA5", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_GFX_MIDCMD_CNTL", 6, 6, &umr_bitfield_default },
+	 { "RESERVED", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_REG_TYPE0[] = {
+	 { "SDMA0_UCODE_ADDR", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_UCODE_DATA", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_POWER_CNTL", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_CLK_CTRL", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_CNTL", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_CHICKEN_BITS", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_TILING_CONFIG", 6, 6, &umr_bitfield_default },
+	 { "SDMA0_HASH", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_SEM_WAIT_FAIL_TIMER_CNTL", 9, 9, &umr_bitfield_default },
+	 { "SDMA0_RB_RPTR_FETCH", 10, 10, &umr_bitfield_default },
+	 { "SDMA0_IB_OFFSET_FETCH", 11, 11, &umr_bitfield_default },
+	 { "SDMA0_PROGRAM", 12, 12, &umr_bitfield_default },
+	 { "SDMA0_STATUS_REG", 13, 13, &umr_bitfield_default },
+	 { "SDMA0_STATUS1_REG", 14, 14, &umr_bitfield_default },
+	 { "SDMA0_RD_BURST_CNTL", 15, 15, &umr_bitfield_default },
+	 { "RESERVED_16", 16, 16, &umr_bitfield_default },
+	 { "RESERVED_17", 17, 17, &umr_bitfield_default },
+	 { "SDMA0_F32_CNTL", 18, 18, &umr_bitfield_default },
+	 { "SDMA0_FREEZE", 19, 19, &umr_bitfield_default },
+	 { "SDMA0_PHASE0_QUANTUM", 20, 20, &umr_bitfield_default },
+	 { "SDMA0_PHASE1_QUANTUM", 21, 21, &umr_bitfield_default },
+	 { "SDMA_POWER_GATING", 22, 22, &umr_bitfield_default },
+	 { "SDMA_PGFSM_CONFIG", 23, 23, &umr_bitfield_default },
+	 { "SDMA_PGFSM_WRITE", 24, 24, &umr_bitfield_default },
+	 { "SDMA_PGFSM_READ", 25, 25, &umr_bitfield_default },
+	 { "SDMA0_EDC_CONFIG", 26, 26, &umr_bitfield_default },
+	 { "SDMA0_BA_THRESHOLD", 27, 27, &umr_bitfield_default },
+	 { "SDMA0_DEVICE_ID", 28, 28, &umr_bitfield_default },
+	 { "SDMA0_VERSION", 29, 29, &umr_bitfield_default },
+	 { "RESERVED", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PUB_REG_TYPE1[] = {
+	 { "SDMA0_VM_CNTL", 0, 0, &umr_bitfield_default },
+	 { "SDMA0_VM_CTX_LO", 1, 1, &umr_bitfield_default },
+	 { "SDMA0_VM_CTX_HI", 2, 2, &umr_bitfield_default },
+	 { "SDMA0_STATUS2_REG", 3, 3, &umr_bitfield_default },
+	 { "SDMA0_ACTIVE_FCN_ID", 4, 4, &umr_bitfield_default },
+	 { "SDMA0_VM_CTX_CNTL", 5, 5, &umr_bitfield_default },
+	 { "SDMA0_VIRT_RESET_REQ", 6, 6, &umr_bitfield_default },
+	 { "SDMA0_VF_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_ATOMIC_CNTL", 8, 8, &umr_bitfield_default },
+	 { "SDMA0_ATOMIC_PREOP_LO", 9, 9, &umr_bitfield_default },
+	 { "SDMA0_ATOMIC_PREOP_HI", 10, 10, &umr_bitfield_default },
+	 { "RESERVED", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CONTEXT_CNTL[] = {
+	 { "RESUME_CTX", 16, 16, &umr_bitfield_default },
+	 { "SESSION_SEL", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "INVAL", 1, 1, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_GFX_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "INVAL", 1, 1, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC0_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "INVAL", 1, 1, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_RLC1_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UCODE_ADDR[] = {
+	 { "VALUE", 0, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_UCODE_DATA[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_POWER_CNTL[] = {
+	 { "MEM_POWER_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "MEM_POWER_LS_EN", 9, 9, &umr_bitfield_default },
+	 { "MEM_POWER_DS_EN", 10, 10, &umr_bitfield_default },
+	 { "MEM_POWER_SD_EN", 11, 11, &umr_bitfield_default },
+	 { "MEM_POWER_DELAY", 12, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE7", 24, 24, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE6", 25, 25, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE5", 26, 26, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE4", 27, 27, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE3", 28, 28, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE2", 29, 29, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CNTL[] = {
+	 { "TRAP_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "ATC_L1_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "SEM_WAIT_INT_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "DATA_SWAP_ENABLE", 3, 3, &umr_bitfield_default },
+	 { "FENCE_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "MIDCMD_PREEMPT_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 11, 16, &umr_bitfield_default },
+	 { "MIDCMD_WORLDSWITCH_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "AUTO_CTXSW_ENABLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 22, 27, &umr_bitfield_default },
+	 { "CTXEMPTY_INT_ENABLE", 28, 28, &umr_bitfield_default },
+	 { "FROZEN_INT_ENABLE", 29, 29, &umr_bitfield_default },
+	 { "IB_PREEMPT_INT_ENABLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CHICKEN_BITS[] = {
+	 { "COPY_EFFICIENCY_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "STALL_ON_TRANS_FULL_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "STALL_ON_NO_FREE_DATA_BUFFER_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "COPY_OVERLAP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "SRBM_POLL_RETRYING", 20, 20, &umr_bitfield_default },
+	 { "CG_STATUS_OUTPUT", 23, 23, &umr_bitfield_default },
+	 { "CE_AFIFO_WATERMARK", 26, 27, &umr_bitfield_default },
+	 { "CE_DFIFO_WATERMARK", 28, 29, &umr_bitfield_default },
+	 { "CE_LFIFO_WATERMARK", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_TILING_CONFIG[] = {
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_HASH[] = {
+	 { "CHANNEL_BITS", 0, 2, &umr_bitfield_default },
+	 { "BANK_BITS", 4, 6, &umr_bitfield_default },
+	 { "CHANNEL_XOR_COUNT", 8, 10, &umr_bitfield_default },
+	 { "BANK_XOR_COUNT", 12, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[] = {
+	 { "TIMER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RB_RPTR_FETCH[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_IB_OFFSET_FETCH[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PROGRAM[] = {
+	 { "STREAM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS_REG[] = {
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "REG_IDLE", 1, 1, &umr_bitfield_default },
+	 { "RB_EMPTY", 2, 2, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_CMD_IDLE", 4, 4, &umr_bitfield_default },
+	 { "RB_CMD_FULL", 5, 5, &umr_bitfield_default },
+	 { "IB_CMD_IDLE", 6, 6, &umr_bitfield_default },
+	 { "IB_CMD_FULL", 7, 7, &umr_bitfield_default },
+	 { "BLOCK_IDLE", 8, 8, &umr_bitfield_default },
+	 { "INSIDE_IB", 9, 9, &umr_bitfield_default },
+	 { "EX_IDLE", 10, 10, &umr_bitfield_default },
+	 { "EX_IDLE_POLL_TIMER_EXPIRE", 11, 11, &umr_bitfield_default },
+	 { "PACKET_READY", 12, 12, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 13, 13, &umr_bitfield_default },
+	 { "SRBM_IDLE", 14, 14, &umr_bitfield_default },
+	 { "CONTEXT_EMPTY", 15, 15, &umr_bitfield_default },
+	 { "DELTA_RPTR_FULL", 16, 16, &umr_bitfield_default },
+	 { "RB_MC_RREQ_IDLE", 17, 17, &umr_bitfield_default },
+	 { "IB_MC_RREQ_IDLE", 18, 18, &umr_bitfield_default },
+	 { "MC_RD_IDLE", 19, 19, &umr_bitfield_default },
+	 { "DELTA_RPTR_EMPTY", 20, 20, &umr_bitfield_default },
+	 { "MC_RD_RET_STALL", 21, 21, &umr_bitfield_default },
+	 { "MC_RD_NO_POLL_IDLE", 22, 22, &umr_bitfield_default },
+	 { "PREV_CMD_IDLE", 25, 25, &umr_bitfield_default },
+	 { "SEM_IDLE", 26, 26, &umr_bitfield_default },
+	 { "SEM_REQ_STALL", 27, 27, &umr_bitfield_default },
+	 { "SEM_RESP_STATE", 28, 29, &umr_bitfield_default },
+	 { "INT_IDLE", 30, 30, &umr_bitfield_default },
+	 { "INT_REQ_STALL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS1_REG[] = {
+	 { "CE_WREQ_IDLE", 0, 0, &umr_bitfield_default },
+	 { "CE_WR_IDLE", 1, 1, &umr_bitfield_default },
+	 { "CE_SPLIT_IDLE", 2, 2, &umr_bitfield_default },
+	 { "CE_RREQ_IDLE", 3, 3, &umr_bitfield_default },
+	 { "CE_OUT_IDLE", 4, 4, &umr_bitfield_default },
+	 { "CE_IN_IDLE", 5, 5, &umr_bitfield_default },
+	 { "CE_DST_IDLE", 6, 6, &umr_bitfield_default },
+	 { "CE_CMD_IDLE", 9, 9, &umr_bitfield_default },
+	 { "CE_AFIFO_FULL", 10, 10, &umr_bitfield_default },
+	 { "CE_INFO_FULL", 13, 13, &umr_bitfield_default },
+	 { "CE_INFO1_FULL", 14, 14, &umr_bitfield_default },
+	 { "CE_RD_STALL", 17, 17, &umr_bitfield_default },
+	 { "CE_WR_STALL", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RD_BURST_CNTL[] = {
+	 { "RD_BURST", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_F32_CNTL[] = {
+	 { "HALT", 0, 0, &umr_bitfield_default },
+	 { "STEP", 1, 1, &umr_bitfield_default },
+	 { "DBG_SELECT_BITS", 2, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_FREEZE[] = {
+	 { "FREEZE", 4, 4, &umr_bitfield_default },
+	 { "FROZEN", 5, 5, &umr_bitfield_default },
+	 { "F32_FREEZE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHASE0_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PHASE1_QUANTUM[] = {
+	 { "UNIT", 0, 3, &umr_bitfield_default },
+	 { "VALUE", 8, 23, &umr_bitfield_default },
+	 { "PREFER", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+	 { "ECC_INT_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_BA_THRESHOLD[] = {
+	 { "READ_THRES", 0, 9, &umr_bitfield_default },
+	 { "WRITE_THRES", 16, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ID[] = {
+	 { "DEVICE_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VERSION[] = {
+	 { "VALUE", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VM_CNTL[] = {
+	 { "CMD", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VM_CTX_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VM_CTX_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_STATUS2_REG[] = {
+	 { "ID", 0, 1, &umr_bitfield_default },
+	 { "F32_INSTR_PTR", 2, 11, &umr_bitfield_default },
+	 { "CURRENT_FCN_IDLE", 14, 15, &umr_bitfield_default },
+	 { "CMD_OP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ACTIVE_FCN_ID[] = {
+	 { "VFID", 0, 3, &umr_bitfield_default },
+	 { "VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VM_CTX_CNTL[] = {
+	 { "PRIV", 0, 0, &umr_bitfield_default },
+	 { "VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ATOMIC_CNTL[] = {
+	 { "LOOP_TIMER", 0, 30, &umr_bitfield_default },
+	 { "ATOMIC_RTN_INT_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ATOMIC_PREOP_LO[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_ATOMIC_PREOP_HI[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_POWER_CNTL_IDLE[] = {
+	 { "DELAY1", 0, 15, &umr_bitfield_default },
+	 { "DELAY2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERF_REG_TYPE0[] = {
+	 { "SDMA1_PERFMON_CNTL", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_PERFCOUNTER0_RESULT", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_PERFCOUNTER1_RESULT", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_31_3", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE0[] = {
+	 { "SDMA1_GFX_RB_CNTL", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_BASE", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_BASE_HI", 2, 2, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_RPTR", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR_POLL_CNTL", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR_POLL_ADDR_HI", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_WPTR_POLL_ADDR_LO", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_RPTR_ADDR_HI", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_GFX_RB_RPTR_ADDR_LO", 9, 9, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_CNTL", 10, 10, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_RPTR", 11, 11, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_OFFSET", 12, 12, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_BASE_LO", 13, 13, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_BASE_HI", 14, 14, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_SIZE", 15, 15, &umr_bitfield_default },
+	 { "SDMA1_GFX_SKIP_CNTL", 16, 16, &umr_bitfield_default },
+	 { "SDMA1_GFX_CONTEXT_STATUS", 17, 17, &umr_bitfield_default },
+	 { "SDMA1_GFX_DOORBELL", 18, 18, &umr_bitfield_default },
+	 { "SDMA1_GFX_CONTEXT_CNTL", 19, 19, &umr_bitfield_default },
+	 { "RESERVED", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE1[] = {
+	 { "VOID_REG0", 0, 6, &umr_bitfield_default },
+	 { "SDMA1_GFX_VIRTUAL_ADDR", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_GFX_APE1_CNTL", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_GFX_DOORBELL_LOG", 9, 9, &umr_bitfield_default },
+	 { "SDMA1_GFX_WATERMARK", 10, 10, &umr_bitfield_default },
+	 { "VOID_REG2", 11, 11, &umr_bitfield_default },
+	 { "SDMA1_GFX_CSA_ADDR_LO", 12, 12, &umr_bitfield_default },
+	 { "SDMA1_GFX_CSA_ADDR_HI", 13, 13, &umr_bitfield_default },
+	 { "VOID_REG3", 14, 14, &umr_bitfield_default },
+	 { "SDMA1_GFX_IB_SUB_REMAIN", 15, 15, &umr_bitfield_default },
+	 { "SDMA1_GFX_PREEMPT", 16, 16, &umr_bitfield_default },
+	 { "SDMA1_GFX_DUMMY_REG", 17, 17, &umr_bitfield_default },
+	 { "RESERVED", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONTEXT_REG_TYPE2[] = {
+	 { "SDMA1_GFX_MIDCMD_DATA0", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA1", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA2", 2, 2, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA3", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA4", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_DATA5", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_GFX_MIDCMD_CNTL", 6, 6, &umr_bitfield_default },
+	 { "RESERVED", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_REG_TYPE0[] = {
+	 { "SDMA1_UCODE_ADDR", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_UCODE_DATA", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_POWER_CNTL", 2, 2, &umr_bitfield_default },
+	 { "SDMA1_CLK_CTRL", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_CNTL", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_CHICKEN_BITS", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_TILING_CONFIG", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_HASH", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_SEM_WAIT_FAIL_TIMER_CNTL", 9, 9, &umr_bitfield_default },
+	 { "SDMA1_RB_RPTR_FETCH", 10, 10, &umr_bitfield_default },
+	 { "SDMA1_IB_OFFSET_FETCH", 11, 11, &umr_bitfield_default },
+	 { "SDMA1_PROGRAM", 12, 12, &umr_bitfield_default },
+	 { "SDMA1_STATUS_REG", 13, 13, &umr_bitfield_default },
+	 { "SDMA1_STATUS1_REG", 14, 14, &umr_bitfield_default },
+	 { "SDMA1_RD_BURST_CNTL", 15, 15, &umr_bitfield_default },
+	 { "RESERVED_16", 16, 16, &umr_bitfield_default },
+	 { "RESERVED_17", 17, 17, &umr_bitfield_default },
+	 { "SDMA1_F32_CNTL", 18, 18, &umr_bitfield_default },
+	 { "SDMA1_FREEZE", 19, 19, &umr_bitfield_default },
+	 { "SDMA1_PHASE0_QUANTUM", 20, 20, &umr_bitfield_default },
+	 { "SDMA1_PHASE1_QUANTUM", 21, 21, &umr_bitfield_default },
+	 { "VOID_REG0", 22, 25, &umr_bitfield_default },
+	 { "SDMA1_EDC_CONFIG", 26, 26, &umr_bitfield_default },
+	 { "SDMA1_BA_THRESHOLD", 27, 27, &umr_bitfield_default },
+	 { "SDMA1_DEVICE_ID", 28, 28, &umr_bitfield_default },
+	 { "SDMA1_VERSION", 29, 29, &umr_bitfield_default },
+	 { "RESERVED", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PUB_REG_TYPE1[] = {
+	 { "SDMA1_VM_CNTL", 0, 0, &umr_bitfield_default },
+	 { "SDMA1_VM_CTX_LO", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_VM_CTX_HI", 2, 2, &umr_bitfield_default },
+	 { "SDMA1_STATUS2_REG", 3, 3, &umr_bitfield_default },
+	 { "SDMA1_ACTIVE_FCN_ID", 4, 4, &umr_bitfield_default },
+	 { "SDMA1_VM_CTX_CNTL", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_VIRT_RESET_REQ", 6, 6, &umr_bitfield_default },
+	 { "SDMA1_VF_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "SDMA1_ATOMIC_CNTL", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_ATOMIC_PREOP_LO", 9, 9, &umr_bitfield_default },
+	 { "SDMA1_ATOMIC_PREOP_HI", 10, 10, &umr_bitfield_default },
+	 { "RESERVED", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CONTEXT_CNTL[] = {
+	 { "RESUME_CTX", 16, 16, &umr_bitfield_default },
+	 { "SESSION_SEL", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "INVAL", 1, 1, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_GFX_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "INVAL", 1, 1, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC0_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_SWAP_ENABLE", 9, 9, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_ENABLE", 12, 12, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_SWAP_ENABLE", 13, 13, &umr_bitfield_default },
+	 { "RPTR_WRITEBACK_TIMER", 16, 20, &umr_bitfield_default },
+	 { "RB_PRIV", 23, 23, &umr_bitfield_default },
+	 { "RB_VMID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_BASE_HI[] = {
+	 { "ADDR", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR[] = {
+	 { "OFFSET", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[] = {
+	 { "ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SWAP_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "F32_POLL_ENABLE", 2, 2, &umr_bitfield_default },
+	 { "FREQUENCY", 4, 15, &umr_bitfield_default },
+	 { "IDLE_POLL_COUNT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_RB_RPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_CNTL[] = {
+	 { "IB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "IB_SWAP_ENABLE", 4, 4, &umr_bitfield_default },
+	 { "SWITCH_INSIDE_IB", 8, 8, &umr_bitfield_default },
+	 { "CMD_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_RPTR[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_OFFSET[] = {
+	 { "OFFSET", 2, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_LO[] = {
+	 { "ADDR", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_BASE_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_SIZE[] = {
+	 { "SIZE", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_SKIP_CNTL[] = {
+	 { "SKIP_COUNT", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_CONTEXT_STATUS[] = {
+	 { "SELECTED", 0, 0, &umr_bitfield_default },
+	 { "IDLE", 2, 2, &umr_bitfield_default },
+	 { "EXPIRED", 3, 3, &umr_bitfield_default },
+	 { "EXCEPTION", 4, 6, &umr_bitfield_default },
+	 { "CTXSW_ABLE", 7, 7, &umr_bitfield_default },
+	 { "CTXSW_READY", 8, 8, &umr_bitfield_default },
+	 { "PREEMPTED", 9, 9, &umr_bitfield_default },
+	 { "PREEMPT_DISABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DOORBELL[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_VIRTUAL_ADDR[] = {
+	 { "ATC", 0, 0, &umr_bitfield_default },
+	 { "INVAL", 1, 1, &umr_bitfield_default },
+	 { "PTR32", 4, 4, &umr_bitfield_default },
+	 { "SHARED_BASE", 8, 10, &umr_bitfield_default },
+	 { "VM_HOLE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_APE1_CNTL[] = {
+	 { "BASE", 0, 15, &umr_bitfield_default },
+	 { "LIMIT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DOORBELL_LOG[] = {
+	 { "BE_ERROR", 0, 0, &umr_bitfield_default },
+	 { "DATA", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_WATERMARK[] = {
+	 { "RD_OUTSTANDING", 0, 11, &umr_bitfield_default },
+	 { "WR_OUTSTANDING", 16, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_CSA_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_CSA_ADDR_HI[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_IB_SUB_REMAIN[] = {
+	 { "SIZE", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_PREEMPT[] = {
+	 { "IB_PREEMPT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_DUMMY_REG[] = {
+	 { "DUMMY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA2[] = {
+	 { "DATA2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA3[] = {
+	 { "DATA3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA4[] = {
+	 { "DATA4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_DATA5[] = {
+	 { "DATA5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_RLC1_MIDCMD_CNTL[] = {
+	 { "DATA_VALID", 0, 0, &umr_bitfield_default },
+	 { "COPY_MODE", 1, 1, &umr_bitfield_default },
+	 { "SPLIT_STATE", 4, 7, &umr_bitfield_default },
+	 { "ALLOW_PREEMPT", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CNTL[] = {
+	 { "PWR_REQUEST_HALT", 16, 16, &umr_bitfield_default },
+	 { "COMBINE_SYSTEM_MC", 17, 17, &umr_bitfield_default },
+	 { "REPORT_LAST_RDERR", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_GFX_CNTL[] = {
+	 { "PIPEID", 0, 1, &umr_bitfield_default },
+	 { "MEID", 2, 3, &umr_bitfield_default },
+	 { "VMID", 4, 7, &umr_bitfield_default },
+	 { "QUEUEID", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_READ_CNTL[] = {
+	 { "READ_TIMEOUT", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_STATUS2[] = {
+	 { "SDMA_RQ_PENDING", 0, 0, &umr_bitfield_default },
+	 { "TST_RQ_PENDING", 1, 1, &umr_bitfield_default },
+	 { "SDMA1_RQ_PENDING", 2, 2, &umr_bitfield_default },
+	 { "VCE0_RQ_PENDING", 3, 3, &umr_bitfield_default },
+	 { "VP8_BUSY", 4, 4, &umr_bitfield_default },
+	 { "SDMA_BUSY", 5, 5, &umr_bitfield_default },
+	 { "SDMA1_BUSY", 6, 6, &umr_bitfield_default },
+	 { "VCE0_BUSY", 7, 7, &umr_bitfield_default },
+	 { "XDMA_BUSY", 8, 8, &umr_bitfield_default },
+	 { "CHUB_BUSY", 9, 9, &umr_bitfield_default },
+	 { "SDMA2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "SDMA3_BUSY", 11, 11, &umr_bitfield_default },
+	 { "SAMSCP_BUSY", 12, 12, &umr_bitfield_default },
+	 { "ISP_BUSY", 13, 13, &umr_bitfield_default },
+	 { "VCE1_BUSY", 14, 14, &umr_bitfield_default },
+	 { "ODE_BUSY", 15, 15, &umr_bitfield_default },
+	 { "SDMA2_RQ_PENDING", 16, 16, &umr_bitfield_default },
+	 { "SDMA3_RQ_PENDING", 17, 17, &umr_bitfield_default },
+	 { "SAMSCP_RQ_PENDING", 18, 18, &umr_bitfield_default },
+	 { "ISP_RQ_PENDING", 19, 19, &umr_bitfield_default },
+	 { "VCE1_RQ_PENDING", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_STATUS[] = {
+	 { "UVD_RQ_PENDING", 1, 1, &umr_bitfield_default },
+	 { "SAMMSP_RQ_PENDING", 2, 2, &umr_bitfield_default },
+	 { "ACP_RQ_PENDING", 3, 3, &umr_bitfield_default },
+	 { "SMU_RQ_PENDING", 4, 4, &umr_bitfield_default },
+	 { "GRBM_RQ_PENDING", 5, 5, &umr_bitfield_default },
+	 { "HI_RQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "VMC_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MCB_BUSY", 9, 9, &umr_bitfield_default },
+	 { "MCB_NON_DISPLAY_BUSY", 10, 10, &umr_bitfield_default },
+	 { "MCC_BUSY", 11, 11, &umr_bitfield_default },
+	 { "MCD_BUSY", 12, 12, &umr_bitfield_default },
+	 { "VMC1_BUSY", 13, 13, &umr_bitfield_default },
+	 { "SEM_BUSY", 14, 14, &umr_bitfield_default },
+	 { "ACP_BUSY", 16, 16, &umr_bitfield_default },
+	 { "IH_BUSY", 17, 17, &umr_bitfield_default },
+	 { "UVD_BUSY", 19, 19, &umr_bitfield_default },
+	 { "SAMMSP_BUSY", 20, 20, &umr_bitfield_default },
+	 { "GCATCL2_BUSY", 21, 21, &umr_bitfield_default },
+	 { "OSATCL2_BUSY", 22, 22, &umr_bitfield_default },
+	 { "BIF_BUSY", 29, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_STATUS3[] = {
+	 { "MCC0_BUSY", 0, 0, &umr_bitfield_default },
+	 { "MCC1_BUSY", 1, 1, &umr_bitfield_default },
+	 { "MCC2_BUSY", 2, 2, &umr_bitfield_default },
+	 { "MCC3_BUSY", 3, 3, &umr_bitfield_default },
+	 { "MCC4_BUSY", 4, 4, &umr_bitfield_default },
+	 { "MCC5_BUSY", 5, 5, &umr_bitfield_default },
+	 { "MCC6_BUSY", 6, 6, &umr_bitfield_default },
+	 { "MCC7_BUSY", 7, 7, &umr_bitfield_default },
+	 { "MCD0_BUSY", 8, 8, &umr_bitfield_default },
+	 { "MCD1_BUSY", 9, 9, &umr_bitfield_default },
+	 { "MCD2_BUSY", 10, 10, &umr_bitfield_default },
+	 { "MCD3_BUSY", 11, 11, &umr_bitfield_default },
+	 { "MCD4_BUSY", 12, 12, &umr_bitfield_default },
+	 { "MCD5_BUSY", 13, 13, &umr_bitfield_default },
+	 { "MCD6_BUSY", 14, 14, &umr_bitfield_default },
+	 { "MCD7_BUSY", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SOFT_RESET[] = {
+	 { "SOFT_RESET_ATCL2", 0, 0, &umr_bitfield_default },
+	 { "SOFT_RESET_BIF", 1, 1, &umr_bitfield_default },
+	 { "SOFT_RESET_SDMA3", 2, 2, &umr_bitfield_default },
+	 { "SOFT_RESET_SDMA2", 3, 3, &umr_bitfield_default },
+	 { "SOFT_RESET_GIONB", 4, 4, &umr_bitfield_default },
+	 { "SOFT_RESET_DC", 5, 5, &umr_bitfield_default },
+	 { "SOFT_RESET_SDMA1", 6, 6, &umr_bitfield_default },
+	 { "SOFT_RESET_GRBM", 8, 8, &umr_bitfield_default },
+	 { "SOFT_RESET_HDP", 9, 9, &umr_bitfield_default },
+	 { "SOFT_RESET_IH", 10, 10, &umr_bitfield_default },
+	 { "SOFT_RESET_MC", 11, 11, &umr_bitfield_default },
+	 { "SOFT_RESET_CHUB", 12, 12, &umr_bitfield_default },
+	 { "SOFT_RESET_ESRAM", 13, 13, &umr_bitfield_default },
+	 { "SOFT_RESET_ROM", 14, 14, &umr_bitfield_default },
+	 { "SOFT_RESET_SEM", 15, 15, &umr_bitfield_default },
+	 { "SOFT_RESET_SMU", 16, 16, &umr_bitfield_default },
+	 { "SOFT_RESET_VMC", 17, 17, &umr_bitfield_default },
+	 { "SOFT_RESET_UVD", 18, 18, &umr_bitfield_default },
+	 { "SOFT_RESET_VP8", 19, 19, &umr_bitfield_default },
+	 { "SOFT_RESET_SDMA", 20, 20, &umr_bitfield_default },
+	 { "SOFT_RESET_TST", 21, 21, &umr_bitfield_default },
+	 { "SOFT_RESET_REGBB", 22, 22, &umr_bitfield_default },
+	 { "SOFT_RESET_ODE", 23, 23, &umr_bitfield_default },
+	 { "SOFT_RESET_VCE0", 24, 24, &umr_bitfield_default },
+	 { "SOFT_RESET_XDMA", 25, 25, &umr_bitfield_default },
+	 { "SOFT_RESET_ACP", 26, 26, &umr_bitfield_default },
+	 { "SOFT_RESET_SAMMSP", 27, 27, &umr_bitfield_default },
+	 { "SOFT_RESET_SAMSCP", 28, 28, &umr_bitfield_default },
+	 { "SOFT_RESET_GRN", 29, 29, &umr_bitfield_default },
+	 { "SOFT_RESET_ISP", 30, 30, &umr_bitfield_default },
+	 { "SOFT_RESET_VCE1", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_CNTL[] = {
+	 { "SRBM_DEBUG_INDEX", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CHIP_REVISION[] = {
+	 { "CHIP_REVISION", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CREDIT_RECOVER_CNTL[] = {
+	 { "CREDIT_RECOVER_TIME", 0, 11, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CREDIT_RECOVER[] = {
+	 { "CREDIT_RECOVER_BIF", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_SMU", 1, 1, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_DC", 2, 2, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_GIONB", 3, 3, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_ACP", 4, 4, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_XDMA", 5, 5, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_ODE", 6, 6, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_REGBB", 7, 7, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_VP8", 8, 8, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_GRBM", 9, 9, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_UVD", 10, 10, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_VCE0", 11, 11, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_VCE1", 12, 12, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_ISP", 13, 13, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_SAM", 14, 14, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCB", 15, 15, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCC0", 16, 16, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCC1", 17, 17, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCC2", 18, 18, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCC3", 19, 19, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCC4", 20, 20, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCC5", 21, 21, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCC6", 22, 22, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCC7", 23, 23, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCD0", 24, 24, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCD1", 25, 25, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCD2", 26, 26, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCD3", 27, 27, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCD4", 28, 28, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCD5", 29, 29, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCD6", 30, 30, &umr_bitfield_default },
+	 { "CREDIT_RECOVER_MCD7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CREDIT_RESET[] = {
+	 { "CREDIT_RESET_BIF", 0, 0, &umr_bitfield_default },
+	 { "CREDIT_RESET_SMU", 1, 1, &umr_bitfield_default },
+	 { "CREDIT_RESET_DC", 2, 2, &umr_bitfield_default },
+	 { "CREDIT_RESET_GIONB", 3, 3, &umr_bitfield_default },
+	 { "CREDIT_RESET_ACP", 4, 4, &umr_bitfield_default },
+	 { "CREDIT_RESET_XDMA", 5, 5, &umr_bitfield_default },
+	 { "CREDIT_RESET_ODE", 6, 6, &umr_bitfield_default },
+	 { "CREDIT_RESET_REGBB", 7, 7, &umr_bitfield_default },
+	 { "CREDIT_RESET_VP8", 8, 8, &umr_bitfield_default },
+	 { "CREDIT_RESET_GRBM", 9, 9, &umr_bitfield_default },
+	 { "CREDIT_RESET_UVD", 10, 10, &umr_bitfield_default },
+	 { "CREDIT_RESET_VCE0", 11, 11, &umr_bitfield_default },
+	 { "CREDIT_RESET_VCE1", 12, 12, &umr_bitfield_default },
+	 { "CREDIT_RESET_ISP", 13, 13, &umr_bitfield_default },
+	 { "CREDIT_RESET_SAM", 14, 14, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCB", 15, 15, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCC0", 16, 16, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCC1", 17, 17, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCC2", 18, 18, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCC3", 19, 19, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCC4", 20, 20, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCC5", 21, 21, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCC6", 22, 22, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCC7", 23, 23, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCD0", 24, 24, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCD1", 25, 25, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCD2", 26, 26, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCD3", 27, 27, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCD4", 28, 28, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCD5", 29, 29, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCD6", 30, 30, &umr_bitfield_default },
+	 { "CREDIT_RESET_MCD7", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SYS_RB_REDUNDANCY[] = {
+	 { "FAILED_RB0", 8, 11, &umr_bitfield_default },
+	 { "EN_REDUNDANCY0", 12, 12, &umr_bitfield_default },
+	 { "FAILED_RB1", 16, 19, &umr_bitfield_default },
+	 { "EN_REDUNDANCY1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCC_SYS_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_USER_SYS_RB_BACKEND_DISABLE[] = {
+	 { "BACKEND_DISABLE", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG[] = {
+	 { "IGNORE_RDY", 0, 0, &umr_bitfield_default },
+	 { "DISABLE_READ_TIMEOUT", 1, 1, &umr_bitfield_default },
+	 { "SNAPSHOT_FREE_CNTRS", 2, 2, &umr_bitfield_default },
+	 { "SYS_CLOCK_DOMAIN_OVERRIDE", 4, 4, &umr_bitfield_default },
+	 { "VCE_CLOCK_DOMAIN_OVERRIDE", 5, 5, &umr_bitfield_default },
+	 { "UVD_CLOCK_DOMAIN_OVERRIDE", 6, 6, &umr_bitfield_default },
+	 { "SDMA_CLOCK_DOMAIN_OVERRIDE", 7, 7, &umr_bitfield_default },
+	 { "MC_CLOCK_DOMAIN_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "SAM_CLOCK_DOMAIN_OVERRIDE", 9, 9, &umr_bitfield_default },
+	 { "ISP_CLOCK_DOMAIN_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "VP8_CLOCK_DOMAIN_OVERRIDE", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_SNAPSHOT[] = {
+	 { "MCB_RDY", 0, 0, &umr_bitfield_default },
+	 { "GIONB_RDY", 1, 1, &umr_bitfield_default },
+	 { "SMU_RDY", 2, 2, &umr_bitfield_default },
+	 { "SAMMSP_RDY", 3, 3, &umr_bitfield_default },
+	 { "ACP_RDY", 4, 4, &umr_bitfield_default },
+	 { "GRBM_RDY", 5, 5, &umr_bitfield_default },
+	 { "DC_RDY", 6, 6, &umr_bitfield_default },
+	 { "BIF_RDY", 7, 7, &umr_bitfield_default },
+	 { "XDMA_RDY", 8, 8, &umr_bitfield_default },
+	 { "UVD_RDY", 9, 9, &umr_bitfield_default },
+	 { "VP8_RDY", 10, 10, &umr_bitfield_default },
+	 { "REGBB_RDY", 11, 11, &umr_bitfield_default },
+	 { "ODE_RDY", 12, 12, &umr_bitfield_default },
+	 { "MCD7_RDY", 13, 13, &umr_bitfield_default },
+	 { "MCD6_RDY", 14, 14, &umr_bitfield_default },
+	 { "MCD5_RDY", 15, 15, &umr_bitfield_default },
+	 { "MCD4_RDY", 16, 16, &umr_bitfield_default },
+	 { "MCD3_RDY", 17, 17, &umr_bitfield_default },
+	 { "MCD2_RDY", 18, 18, &umr_bitfield_default },
+	 { "MCD1_RDY", 19, 19, &umr_bitfield_default },
+	 { "MCD0_RDY", 20, 20, &umr_bitfield_default },
+	 { "MCC7_RDY", 21, 21, &umr_bitfield_default },
+	 { "MCC6_RDY", 22, 22, &umr_bitfield_default },
+	 { "MCC5_RDY", 23, 23, &umr_bitfield_default },
+	 { "MCC4_RDY", 24, 24, &umr_bitfield_default },
+	 { "MCC3_RDY", 25, 25, &umr_bitfield_default },
+	 { "MCC2_RDY", 26, 26, &umr_bitfield_default },
+	 { "MCC1_RDY", 27, 27, &umr_bitfield_default },
+	 { "MCC0_RDY", 28, 28, &umr_bitfield_default },
+	 { "VCE0_RDY", 29, 29, &umr_bitfield_default },
+	 { "SAMSCP_RDY", 30, 30, &umr_bitfield_default },
+	 { "ISP_RDY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_READ_ERROR[] = {
+	 { "READ_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "READ_REQUESTER_SDMA3", 18, 18, &umr_bitfield_default },
+	 { "READ_REQUESTER_SDMA2", 19, 19, &umr_bitfield_default },
+	 { "READ_REQUESTER_VCE0", 20, 20, &umr_bitfield_default },
+	 { "READ_REQUESTER_SDMA1", 21, 21, &umr_bitfield_default },
+	 { "READ_REQUESTER_TST", 22, 22, &umr_bitfield_default },
+	 { "READ_REQUESTER_SAMMSP", 23, 23, &umr_bitfield_default },
+	 { "READ_REQUESTER_HI", 24, 24, &umr_bitfield_default },
+	 { "READ_REQUESTER_GRBM", 25, 25, &umr_bitfield_default },
+	 { "READ_REQUESTER_SMU", 26, 26, &umr_bitfield_default },
+	 { "READ_REQUESTER_SAMSCP", 27, 27, &umr_bitfield_default },
+	 { "READ_REQUESTER_SDMA", 28, 28, &umr_bitfield_default },
+	 { "READ_REQUESTER_UVD", 29, 29, &umr_bitfield_default },
+	 { "READ_ERROR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_CNTL[] = {
+	 { "RDERR_INT_MASK", 0, 0, &umr_bitfield_default },
+	 { "RAERR_INT_MASK", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_STATUS[] = {
+	 { "RDERR_INT_STAT", 0, 0, &umr_bitfield_default },
+	 { "RAERR_INT_STAT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_INT_ACK[] = {
+	 { "RDERR_INT_ACK", 0, 0, &umr_bitfield_default },
+	 { "RAERR_INT_ACK", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_FIREWALL_ERROR_SRC[] = {
+	 { "ACCESS_REQUESTER_BIF", 0, 0, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_ACP", 1, 1, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_SAMSCP", 2, 2, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_SAMMSP", 3, 3, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_TST", 5, 5, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_SDMA3", 6, 6, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_SDMA2", 7, 7, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_SDMA1", 8, 8, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_SDMA0", 9, 9, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_UVD", 10, 10, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_VCE0", 11, 11, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_GRBM", 12, 12, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_SMU", 13, 13, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_PEER", 14, 14, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_CPU", 15, 15, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_ISP", 16, 16, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_VCE1", 17, 17, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_RLCHYP", 18, 18, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_SMUHYP", 19, 19, &umr_bitfield_default },
+	 { "ACCESS_REQUESTER_BIFHYP", 20, 20, &umr_bitfield_default },
+	 { "RAERR_FIREWALL_VIOLATION", 24, 24, &umr_bitfield_default },
+	 { "RAERR_HAR_REGIONSIZE_OVERFLOW", 25, 25, &umr_bitfield_default },
+	 { "RAERR_BIF_ADDR_OVERFLOW", 26, 26, &umr_bitfield_default },
+	 { "RAERR_P2SRP_REGIONSIZE_OVERFLOW", 27, 27, &umr_bitfield_default },
+	 { "RAERR_P2SRP_FIREWALL_VIOLATION", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_FIREWALL_ERROR_ADDR[] = {
+	 { "ACCESS_ADDRESS", 2, 17, &umr_bitfield_default },
+	 { "ACCESS_VF", 19, 19, &umr_bitfield_default },
+	 { "ACCESS_VFID", 20, 23, &umr_bitfield_default },
+	 { "FIREWALL_VIOLATION", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DEBUG_SNAPSHOT2[] = {
+	 { "VCE1_RDY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_READ_ERROR2[] = {
+	 { "READ_REQUESTER_ACP", 0, 0, &umr_bitfield_default },
+	 { "READ_REQUESTER_ISP", 1, 1, &umr_bitfield_default },
+	 { "READ_REQUESTER_VCE1", 2, 2, &umr_bitfield_default },
+	 { "READ_VF", 23, 23, &umr_bitfield_default },
+	 { "READ_VFID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DSM_TRIG_CNTL0[] = {
+	 { "DSM_TRIG_ADDR", 0, 15, &umr_bitfield_default },
+	 { "DSM_TRIG_OP", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DSM_TRIG_CNTL1[] = {
+	 { "DSM_TRIG_WD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DSM_TRIG_MASK0[] = {
+	 { "DSM_TRIG_ADDR_MASK", 0, 15, &umr_bitfield_default },
+	 { "DSM_TRIG_OP_MASK", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_DSM_TRIG_MASK1[] = {
+	 { "DSM_TRIG_WD_MASK", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VCE_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_UVD_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SDMA_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SAM_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_ISP_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VP8_CLKEN_CNTL[] = {
+	 { "PREFIX_DELAY_CNT", 0, 3, &umr_bitfield_default },
+	 { "POST_DELAY_CNT", 8, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXP7[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX0[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLX3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFMON_CNTL[] = {
+	 { "PERFMON_STATE", 0, 3, &umr_bitfield_default },
+	 { "PERFMON_ENABLE_MODE", 8, 9, &umr_bitfield_default },
+	 { "PERFMON_SAMPLE_ENABLE", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_SELECT[] = {
+	 { "PERF_SEL", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_LO[] = {
+	 { "PERF_COUNT0_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER0_HI[] = {
+	 { "PERF_COUNT0_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_LO[] = {
+	 { "PERF_COUNT1_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_PERFCOUNTER1_HI[] = {
+	 { "PERF_COUNT1_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS1[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFMON_CNTL[] = {
+	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
+	 { "PERF_ENABLE1", 8, 8, &umr_bitfield_default },
+	 { "PERF_CLEAR1", 9, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA0_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFMON_CNTL[] = {
+	 { "PERF_ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "PERF_CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 7, &umr_bitfield_default },
+	 { "PERF_ENABLE1", 8, 8, &umr_bitfield_default },
+	 { "PERF_CLEAR1", 9, 9, &umr_bitfield_default },
+	 { "PERF_SEL1", 10, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_HOST_PATH_CNTL[] = {
+	 { "BIF_RDRET_CREDIT", 0, 2, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 3, 8, &umr_bitfield_default },
+	 { "WR_STALL_TIMER", 9, 10, &umr_bitfield_default },
+	 { "RD_STALL_TIMER", 11, 12, &umr_bitfield_default },
+	 { "WRITE_COMBINE_TIMER", 19, 20, &umr_bitfield_default },
+	 { "WRITE_COMBINE_EN", 21, 21, &umr_bitfield_default },
+	 { "CACHE_INVALIDATE", 22, 22, &umr_bitfield_default },
+	 { "CLOCK_GATING_DIS", 23, 23, &umr_bitfield_default },
+	 { "REG_CLK_ENABLE_COUNT", 24, 27, &umr_bitfield_default },
+	 { "ALL_SURFACES_DIS", 29, 29, &umr_bitfield_default },
+	 { "WRITE_THROUGH_CACHE_DIS", 30, 30, &umr_bitfield_default },
+	 { "LIN_RD_CACHE_DIS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_BASE[] = {
+	 { "NONSURF_BASE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_INFO[] = {
+	 { "NONSURF_ADDR_TYPE", 0, 0, &umr_bitfield_default },
+	 { "NONSURF_ARRAY_MODE", 1, 4, &umr_bitfield_default },
+	 { "NONSURF_ENDIAN", 5, 6, &umr_bitfield_default },
+	 { "NONSURF_PIXEL_SIZE", 7, 9, &umr_bitfield_default },
+	 { "NONSURF_SAMPLE_NUM", 10, 12, &umr_bitfield_default },
+	 { "NONSURF_SAMPLE_SIZE", 13, 14, &umr_bitfield_default },
+	 { "NONSURF_PRIV", 15, 15, &umr_bitfield_default },
+	 { "NONSURF_TILE_COMPACT", 16, 16, &umr_bitfield_default },
+	 { "NONSURF_TILE_SPLIT", 17, 19, &umr_bitfield_default },
+	 { "NONSURF_NUM_BANKS", 20, 21, &umr_bitfield_default },
+	 { "NONSURF_BANK_WIDTH", 22, 23, &umr_bitfield_default },
+	 { "NONSURF_BANK_HEIGHT", 24, 25, &umr_bitfield_default },
+	 { "NONSURF_MACRO_TILE_ASPECT", 26, 27, &umr_bitfield_default },
+	 { "NONSURF_MICRO_TILE_MODE", 28, 30, &umr_bitfield_default },
+	 { "NONSURF_SLICE_TILE_MAX_MSB", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_SIZE[] = {
+	 { "NONSURF_PITCH_TILE_MAX", 0, 10, &umr_bitfield_default },
+	 { "NONSURF_SLICE_TILE_MAX", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURF_FLAGS[] = {
+	 { "NONSURF_WRITE_FLAG", 0, 0, &umr_bitfield_default },
+	 { "NONSURF_READ_FLAG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURF_FLAGS_CLR[] = {
+	 { "NONSURF_WRITE_FLAG_CLR", 0, 0, &umr_bitfield_default },
+	 { "NONSURF_READ_FLAG_CLR", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_SW_SEMAPHORE[] = {
+	 { "SW_SEMAPHORE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_DEBUG0[] = {
+};
+static struct umr_bitfield mmHDP_DEBUG1[] = {
+};
+static struct umr_bitfield mmHDP_LAST_SURFACE_HIT[] = {
+	 { "LAST_SURFACE_HIT", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_TILING_CONFIG[] = {
+	 { "PIPE_TILING", 1, 3, &umr_bitfield_default },
+	 { "BANK_TILING", 4, 5, &umr_bitfield_default },
+	 { "GROUP_SIZE", 6, 7, &umr_bitfield_default },
+	 { "ROW_TILING", 8, 10, &umr_bitfield_default },
+	 { "BANK_SWAPS", 11, 13, &umr_bitfield_default },
+	 { "SAMPLE_SPLIT", 14, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_SC_MULTI_CHIP_CNTL[] = {
+	 { "LOG2_NUM_CHIPS", 0, 2, &umr_bitfield_default },
+	 { "MULTI_CHIP_TILE_SIZE", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_OUTSTANDING_REQ[] = {
+	 { "WRITE_REQ", 0, 7, &umr_bitfield_default },
+	 { "READ_REQ", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MISC_CNTL[] = {
+	 { "FLUSH_INVALIDATE_CACHE", 0, 0, &umr_bitfield_default },
+	 { "VM_ID", 1, 4, &umr_bitfield_default },
+	 { "OUTSTANDING_WRITE_COUNT_1024", 5, 5, &umr_bitfield_default },
+	 { "MULTIPLE_READS", 6, 6, &umr_bitfield_default },
+	 { "HDP_BIF_RDRET_CREDIT", 7, 10, &umr_bitfield_default },
+	 { "SIMULTANEOUS_READS_WRITES", 11, 11, &umr_bitfield_default },
+	 { "NO_SPLIT_ARRAY_LINEAR", 12, 12, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 13, 18, &umr_bitfield_default },
+	 { "READ_CACHE_INVALIDATE", 19, 19, &umr_bitfield_default },
+	 { "ADDRLIB_LINEAR_BYPASS", 20, 20, &umr_bitfield_default },
+	 { "FED_ENABLE", 21, 21, &umr_bitfield_default },
+	 { "LEGACY_TILING_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "LEGACY_SURFACES_ENABLE", 23, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEM_POWER_LS[] = {
+	 { "LS_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "LS_SETUP", 1, 6, &umr_bitfield_default },
+	 { "LS_HOLD", 7, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_NONSURFACE_PREFETCH[] = {
+	 { "NONSURF_PREFETCH_PRI", 0, 2, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_DIR", 3, 5, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_NUM", 6, 8, &umr_bitfield_default },
+	 { "NONSURF_PREFETCH_MAX_Z", 9, 19, &umr_bitfield_default },
+	 { "NONSURF_PIPE_CONFIG", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_CNTL[] = {
+	 { "MEMIO_SEND", 0, 0, &umr_bitfield_default },
+	 { "MEMIO_OP", 1, 1, &umr_bitfield_default },
+	 { "MEMIO_BE", 2, 5, &umr_bitfield_default },
+	 { "MEMIO_WR_STROBE", 6, 6, &umr_bitfield_default },
+	 { "MEMIO_RD_STROBE", 7, 7, &umr_bitfield_default },
+	 { "MEMIO_ADDR_UPPER", 8, 13, &umr_bitfield_default },
+	 { "MEMIO_CLR_WR_ERROR", 14, 14, &umr_bitfield_default },
+	 { "MEMIO_CLR_RD_ERROR", 15, 15, &umr_bitfield_default },
+	 { "MEMIO_VF", 16, 16, &umr_bitfield_default },
+	 { "MEMIO_VFID", 17, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_ADDR[] = {
+	 { "MEMIO_ADDR_LOWER", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_STATUS[] = {
+	 { "MEMIO_WR_STATUS", 0, 0, &umr_bitfield_default },
+	 { "MEMIO_RD_STATUS", 1, 1, &umr_bitfield_default },
+	 { "MEMIO_WR_ERROR", 2, 2, &umr_bitfield_default },
+	 { "MEMIO_RD_ERROR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_WR_DATA[] = {
+	 { "MEMIO_WR_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_MEMIO_RD_DATA[] = {
+	 { "MEMIO_RD_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_VF_ENABLE[] = {
+	 { "VF_EN", 0, 0, &umr_bitfield_default },
+	 { "VF_NUM", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixKHFS2[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_FIRST[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_FLUSH[] = {
+	 { "D2H_FLUSH_FLUSH_NUM", 0, 3, &umr_bitfield_default },
+	 { "D2H_FLUSH_MBX_ENC_DATA", 4, 7, &umr_bitfield_default },
+	 { "D2H_FLUSH_MBX_ADDR_SEL", 8, 10, &umr_bitfield_default },
+	 { "D2H_FLUSH_XPB_CLG", 11, 15, &umr_bitfield_default },
+	 { "D2H_FLUSH_SEND_HOST", 16, 16, &umr_bitfield_default },
+	 { "D2H_FLUSH_SEND_SIDE", 17, 17, &umr_bitfield_default },
+	 { "D2H_FLUSH_ALTER_FLUSH_NUM", 18, 18, &umr_bitfield_default },
+	 { "D2H_FLUSH_RSVD_0", 19, 19, &umr_bitfield_default },
+	 { "D2H_FLUSH_RSVD_1", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_BAR_UPDATE[] = {
+	 { "D2H_BAR_UPDATE_ADDR", 0, 15, &umr_bitfield_default },
+	 { "D2H_BAR_UPDATE_FLUSH_NUM", 16, 19, &umr_bitfield_default },
+	 { "D2H_BAR_UPDATE_BAR_NUM", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_3[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_4[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_5[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_6[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_7[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_8[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_9[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_10[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_11[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_12[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_13[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_14[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_15[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_16[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_17[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_18[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_19[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_20[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_21[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_22[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_23[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_24[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_25[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_26[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_27[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_28[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_29[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_30[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_31[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_32[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_33[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_D2H_RSVD_34[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DIRECT2HDP_LAST[] = {
+	 { "RESERVED", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR_CFG[] = {
+	 { "P2P_BAR_CFG_ADDR_SIZE", 0, 3, &umr_bitfield_default },
+	 { "P2P_BAR_CFG_BAR_FROM", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_OFFSET[] = {
+	 { "P2P_MBX_OFFSET", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR0[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR1[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR2[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR3[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR4[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR5[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_MBX_ADDR6[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "ADDR", 1, 20, &umr_bitfield_default },
+	 { "ADDR_39_36", 21, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_MBX_MC_CFG[] = {
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_PRIV", 0, 0, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_SWAP", 1, 2, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_TRAN", 3, 3, &umr_bitfield_default },
+	 { "HDP_MBX_MC_CFG_TAP_WRREQ_VMID", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_MC_CFG[] = {
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_PRIV", 0, 0, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_SWAP", 1, 2, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_TRAN", 3, 3, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_PRIV", 4, 4, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_SWAP", 5, 6, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_TRAN", 7, 7, &umr_bitfield_default },
+	 { "HDP_MC_CFG_XL8R_WRREQ_CRD_OVERRIDE", 8, 13, &umr_bitfield_default },
+	 { "HDP_MC_CFG_XDP_HIGHER_PRI_THRESH", 14, 19, &umr_bitfield_default },
+	 { "HDP_MC_CFG_MC_STALL_ON_BUF_FULL_MASK", 20, 22, &umr_bitfield_default },
+	 { "HDP_MC_CFG_HST_TAP_WRREQ_VMID", 23, 26, &umr_bitfield_default },
+	 { "HDP_MC_CFG_SID_TAP_WRREQ_VMID", 27, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HST_CFG[] = {
+	 { "HST_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
+	 { "HST_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_SID_CFG[] = {
+	 { "SID_CFG_WR_COMBINE_EN", 0, 0, &umr_bitfield_default },
+	 { "SID_CFG_WR_COMBINE_TIMER", 1, 2, &umr_bitfield_default },
+	 { "SID_CFG_FLNUM_MSB_SEL", 3, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_HDP_IPH_CFG[] = {
+	 { "HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE", 0, 5, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE", 6, 11, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING", 12, 12, &umr_bitfield_default },
+	 { "HDP_IPH_CFG_P2P_RD_EN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_SRBM_CFG[] = {
+	 { "SRBM_CFG_REG_CLK_ENABLE_COUNT", 0, 5, &umr_bitfield_default },
+	 { "SRBM_CFG_REG_CLK_GATING_DIS", 6, 6, &umr_bitfield_default },
+	 { "SRBM_CFG_WAKE_DYN_CLK", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_CGTT_BLK_CTRL[] = {
+	 { "CGTT_BLK_CTRL_0_ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_1_OFF_DELAY", 4, 11, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_2_RSVD", 12, 29, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_3_SOFT_CORE_OVERRIDE", 30, 30, &umr_bitfield_default },
+	 { "CGTT_BLK_CTRL_4_SOFT_REG_OVERRIDE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR0[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR1[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR2[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR3[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR4[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR5[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR6[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_P2P_BAR7[] = {
+	 { "ADDR", 0, 15, &umr_bitfield_default },
+	 { "FLUSH", 16, 19, &umr_bitfield_default },
+	 { "VALID", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_FLUSH_ARMED_STS[] = {
+	 { "FLUSH_ARMED_STS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_FLUSH_CNTR0_STS[] = {
+	 { "FLUSH_CNTR0_STS", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_BUSY_STS[] = {
+	 { "BUSY_BITS", 0, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_STICKY[] = {
+	 { "STICKY_STS", 0, 15, &umr_bitfield_default },
+	 { "STICKY_W1C", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_CHKN[] = {
+	 { "CHKN_0_RSVD", 0, 7, &umr_bitfield_default },
+	 { "CHKN_1_RSVD", 8, 15, &umr_bitfield_default },
+	 { "CHKN_2_RSVD", 16, 23, &umr_bitfield_default },
+	 { "CHKN_3_RSVD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_ADDR[] = {
+	 { "STS", 0, 15, &umr_bitfield_default },
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_DATA[] = {
+	 { "STS", 0, 15, &umr_bitfield_default },
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_DBG_MASK[] = {
+	 { "STS", 0, 15, &umr_bitfield_default },
+	 { "CTRL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmHDP_XDP_BARS_ADDR_39_36[] = {
+	 { "BAR0_ADDR_39_36", 0, 3, &umr_bitfield_default },
+	 { "BAR1_ADDR_39_36", 4, 7, &umr_bitfield_default },
+	 { "BAR2_ADDR_39_36", 8, 11, &umr_bitfield_default },
+	 { "BAR3_ADDR_39_36", 12, 15, &umr_bitfield_default },
+	 { "BAR4_ADDR_39_36", 16, 19, &umr_bitfield_default },
+	 { "BAR5_ADDR_39_36", 20, 23, &umr_bitfield_default },
+	 { "BAR6_ADDR_39_36", 24, 27, &umr_bitfield_default },
+	 { "BAR7_ADDR_39_36", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_0_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_1_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_2_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_3_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_4_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_5_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_6_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_7_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_8_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_9_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_10_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_11_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_12_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_13_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_14_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VMID_15_LUT[] = {
+	 { "PASID", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_CNTL[] = {
+	 { "RB_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "RB_SIZE", 1, 5, &umr_bitfield_default },
+	 { "RB_GPU_TS_ENABLE", 7, 7, &umr_bitfield_default },
+	 { "WPTR_WRITEBACK_ENABLE", 8, 8, &umr_bitfield_default },
+	 { "ENABLE_INTR", 17, 17, &umr_bitfield_default },
+	 { "MC_SWAP", 18, 19, &umr_bitfield_default },
+	 { "RPTR_REARM", 21, 21, &umr_bitfield_default },
+	 { "MC_VMID", 24, 27, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_CLEAR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_BASE[] = {
+	 { "ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_RPTR[] = {
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR[] = {
+	 { "RB_OVERFLOW", 0, 0, &umr_bitfield_default },
+	 { "OFFSET", 2, 17, &umr_bitfield_default },
+	 { "RB_LEFT_NONE", 18, 18, &umr_bitfield_default },
+	 { "RB_MAY_OVERFLOW", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR_ADDR_HI[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RB_WPTR_ADDR_LO[] = {
+	 { "ADDR", 2, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_CNTL[] = {
+	 { "WPTR_WRITEBACK_TIMER", 0, 4, &umr_bitfield_default },
+	 { "CLIENT_FIFO_HIGHWATER", 8, 9, &umr_bitfield_default },
+	 { "MC_FIFO_HIGHWATER", 10, 14, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 15, 19, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_CNT", 20, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_LEVEL_STATUS[] = {
+	 { "DC_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ROM_STATUS", 2, 2, &umr_bitfield_default },
+	 { "SRBM_STATUS", 3, 3, &umr_bitfield_default },
+	 { "BIF_STATUS", 4, 4, &umr_bitfield_default },
+	 { "XDMA_STATUS", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_STATUS[] = {
+	 { "IDLE", 0, 0, &umr_bitfield_default },
+	 { "INPUT_IDLE", 1, 1, &umr_bitfield_default },
+	 { "RB_IDLE", 2, 2, &umr_bitfield_default },
+	 { "RB_FULL", 3, 3, &umr_bitfield_default },
+	 { "RB_FULL_DRAIN", 4, 4, &umr_bitfield_default },
+	 { "RB_OVERFLOW", 5, 5, &umr_bitfield_default },
+	 { "MC_WR_IDLE", 6, 6, &umr_bitfield_default },
+	 { "MC_WR_STALL", 7, 7, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_PENDING", 8, 8, &umr_bitfield_default },
+	 { "MC_WR_CLEAN_STALL", 9, 9, &umr_bitfield_default },
+	 { "BIF_INTERRUPT_LINE", 10, 10, &umr_bitfield_default },
+	 { "SWITCH_READY", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFMON_CNTL[] = {
+	 { "ENABLE0", 0, 0, &umr_bitfield_default },
+	 { "CLEAR0", 1, 1, &umr_bitfield_default },
+	 { "PERF_SEL0", 2, 9, &umr_bitfield_default },
+	 { "ENABLE1", 10, 10, &umr_bitfield_default },
+	 { "CLEAR1", 11, 11, &umr_bitfield_default },
+	 { "PERF_SEL1", 12, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFCOUNTER0_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_PERFCOUNTER1_RESULT[] = {
+	 { "PERF_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_DEBUG[] = {
+	 { "RB_FULL_DRAIN_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "WPTR_OVERFLOW_ENABLE", 1, 1, &umr_bitfield_default },
+	 { "MC_WR_FIFO_BLOCK_ENABLE", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_DSM_MATCH_VALUE_BIT_31_0[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_DSM_MATCH_VALUE_BIT_63_32[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_DSM_MATCH_VALUE_BIT_95_64[] = {
+	 { "VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_DSM_MATCH_FIELD_CONTROL[] = {
+	 { "SRC_EN", 0, 0, &umr_bitfield_default },
+	 { "FCNID_EN", 1, 1, &umr_bitfield_default },
+	 { "TIMESTAMP_EN", 2, 2, &umr_bitfield_default },
+	 { "RINGID_EN", 3, 3, &umr_bitfield_default },
+	 { "VMID_EN", 4, 4, &umr_bitfield_default },
+	 { "PASID_EN", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_DSM_MATCH_DATA_CONTROL[] = {
+	 { "VALUE", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_DOORBELL_RPTR[] = {
+	 { "OFFSET", 0, 20, &umr_bitfield_default },
+	 { "ENABLE", 28, 28, &umr_bitfield_default },
+	 { "CAPTURED", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_ACTIVE_FCN_ID[] = {
+	 { "VF_ID", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 30, &umr_bitfield_default },
+	 { "PF_VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VF_RB_STATUS[] = {
+	 { "RB_FULL_DRAIN_VF", 0, 15, &umr_bitfield_default },
+	 { "RB_OVERFLOW_VF", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VF_ENABLE[] = {
+	 { "VALUE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VF_RB_BIF_STATUS[] = {
+	 { "RB_FULL_VF", 0, 15, &umr_bitfield_default },
+	 { "BIF_INTERRUPT_LINE_VF", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_VERSION[] = {
+	 { "VALUE", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_LEVEL_INTR_MASK[] = {
+	 { "MASK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_RESET_INCOMPLETE_INT_CNTL[] = {
+	 { "CG", 0, 0, &umr_bitfield_default },
+	 { "DC", 1, 1, &umr_bitfield_default },
+	 { "SAMMSP", 3, 3, &umr_bitfield_default },
+	 { "RLC", 4, 4, &umr_bitfield_default },
+	 { "ROM", 5, 5, &umr_bitfield_default },
+	 { "SRBM", 6, 6, &umr_bitfield_default },
+	 { "VMC", 7, 7, &umr_bitfield_default },
+	 { "UVD", 8, 8, &umr_bitfield_default },
+	 { "BIF", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+	 { "ISP", 12, 12, &umr_bitfield_default },
+	 { "VCE0", 13, 13, &umr_bitfield_default },
+	 { "VCE1", 14, 14, &umr_bitfield_default },
+	 { "ATC", 15, 15, &umr_bitfield_default },
+	 { "XDMA", 16, 16, &umr_bitfield_default },
+	 { "ACP", 17, 17, &umr_bitfield_default },
+	 { "SH", 18, 18, &umr_bitfield_default },
+	 { "SH1", 19, 19, &umr_bitfield_default },
+	 { "SH2", 20, 20, &umr_bitfield_default },
+	 { "SH3", 21, 21, &umr_bitfield_default },
+	 { "RESET_ENABLE", 22, 22, &umr_bitfield_default },
+	 { "INCOMPLETE_CNT", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT[] = {
+	 { "CG", 0, 0, &umr_bitfield_default },
+	 { "DC", 1, 1, &umr_bitfield_default },
+	 { "SAMMSP", 3, 3, &umr_bitfield_default },
+	 { "RLC", 4, 4, &umr_bitfield_default },
+	 { "ROM", 5, 5, &umr_bitfield_default },
+	 { "SRBM", 6, 6, &umr_bitfield_default },
+	 { "VMC", 7, 7, &umr_bitfield_default },
+	 { "UVD", 8, 8, &umr_bitfield_default },
+	 { "BIF", 9, 9, &umr_bitfield_default },
+	 { "SDMA0", 10, 10, &umr_bitfield_default },
+	 { "SDMA1", 11, 11, &umr_bitfield_default },
+	 { "ISP", 12, 12, &umr_bitfield_default },
+	 { "VCE0", 13, 13, &umr_bitfield_default },
+	 { "VCE1", 14, 14, &umr_bitfield_default },
+	 { "ATC", 15, 15, &umr_bitfield_default },
+	 { "XDMA", 16, 16, &umr_bitfield_default },
+	 { "ACP", 17, 17, &umr_bitfield_default },
+	 { "SH", 18, 18, &umr_bitfield_default },
+	 { "SH1", 19, 19, &umr_bitfield_default },
+	 { "SH2", 20, 20, &umr_bitfield_default },
+	 { "SH3", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MCIF_CONFIG[] = {
+	 { "MC_REQ_SWAP", 0, 1, &umr_bitfield_default },
+	 { "MC_WRREQ_CREDIT", 2, 7, &umr_bitfield_default },
+	 { "MC_RDREQ_CREDIT", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA_CONFIG[] = {
+	 { "SDMA_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "SDMA_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSDMA1_CONFIG[] = {
+	 { "SDMA_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "SDMA_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CONFIG[] = {
+	 { "UVD_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "UVD_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_CONFIG[] = {
+	 { "VCE_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "VCE_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_VF_ENABLE[] = {
+	 { "VALUE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCP_CONFIG[] = {
+	 { "CP_RDREQ_URG", 8, 11, &umr_bitfield_default },
+	 { "CP_REQ_TRAN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_ACTIVE_FCN_ID[] = {
+	 { "VFID", 0, 3, &umr_bitfield_default },
+	 { "VF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_STATUS[] = {
+	 { "SEM_IDLE", 0, 0, &umr_bitfield_default },
+	 { "SEM_INTERNAL_IDLE", 1, 1, &umr_bitfield_default },
+	 { "MC_RDREQ_FIFO_FULL", 2, 2, &umr_bitfield_default },
+	 { "MC_WRREQ_FIFO_FULL", 3, 3, &umr_bitfield_default },
+	 { "WRITE1_FIFO_FULL", 4, 4, &umr_bitfield_default },
+	 { "CHECK0_FIFO_FULL", 5, 5, &umr_bitfield_default },
+	 { "MC_RDREQ_PENDING", 6, 6, &umr_bitfield_default },
+	 { "MC_WRREQ_PENDING", 7, 7, &umr_bitfield_default },
+	 { "SDMA0_MAILBOX_PENDING", 8, 8, &umr_bitfield_default },
+	 { "SDMA1_MAILBOX_PENDING", 9, 9, &umr_bitfield_default },
+	 { "UVD_MAILBOX_PENDING", 10, 10, &umr_bitfield_default },
+	 { "VCE_MAILBOX_PENDING", 11, 11, &umr_bitfield_default },
+	 { "CPG1_MAILBOX_PENDING", 12, 12, &umr_bitfield_default },
+	 { "CPG2_MAILBOX_PENDING", 13, 13, &umr_bitfield_default },
+	 { "VCE1_MAILBOX_PENDING", 14, 14, &umr_bitfield_default },
+	 { "SWITCH_READY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_EDC_CONFIG[] = {
+	 { "DIS_EDC", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX_CLIENTCONFIG[] = {
+	 { "CP_CLIENT0", 0, 2, &umr_bitfield_default },
+	 { "CP_CLIENT1", 3, 5, &umr_bitfield_default },
+	 { "CP_CLIENT2", 6, 8, &umr_bitfield_default },
+	 { "CP_CLIENT3", 9, 11, &umr_bitfield_default },
+	 { "SDMA_CLIENT0", 12, 14, &umr_bitfield_default },
+	 { "UVD_CLIENT0", 15, 17, &umr_bitfield_default },
+	 { "SDMA1_CLIENT0", 18, 20, &umr_bitfield_default },
+	 { "VCE_CLIENT0", 21, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX[] = {
+	 { "SIDEPORT", 0, 7, &umr_bitfield_default },
+	 { "HOSTPORT", 8, 15, &umr_bitfield_default },
+	 { "SIDEPORT_EXTRA", 16, 23, &umr_bitfield_default },
+	 { "HOSTPORT_EXTRA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX_CONTROL[] = {
+	 { "SIDEPORT_ENABLE", 0, 7, &umr_bitfield_default },
+	 { "HOSTPORT_ENABLE", 8, 15, &umr_bitfield_default },
+	 { "SIDEPORT_ENABLE_EXTRA", 16, 23, &umr_bitfield_default },
+	 { "HOSTPORT_ENABLE_EXTRA", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_CHICKEN_BITS[] = {
+	 { "VMID_PIPELINE_EN", 0, 0, &umr_bitfield_default },
+	 { "ENTRY_PIPELINE_EN", 1, 1, &umr_bitfield_default },
+	 { "CHECK_COUNTER_EN", 2, 2, &umr_bitfield_default },
+	 { "ECC_BEHAVIOR", 3, 4, &umr_bitfield_default },
+	 { "IDLE_COUNTER_INDEX", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSEM_MAILBOX_CLIENTCONFIG_EXTRA[] = {
+	 { "VCE1_CLIENT0", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_DOMAIN_ADDR0[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_DOMAIN_ADDR1[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_DOMAIN_ADDR2[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_DOMAIN_ADDR3[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_DOMAIN_ADDR4[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_DOMAIN_ADDR5[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_MC_DOMAIN_ADDR6[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_DOMAIN_ADDR0[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_DOMAIN_ADDR1[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_DOMAIN_ADDR2[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_DOMAIN_ADDR3[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_DOMAIN_ADDR4[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_DOMAIN_ADDR5[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SYS_DOMAIN_ADDR6[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SDMA_DOMAIN_ADDR0[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SDMA_DOMAIN_ADDR1[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SDMA_DOMAIN_ADDR2[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SDMA_DOMAIN_ADDR3[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_UVD_DOMAIN_ADDR0[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_UVD_DOMAIN_ADDR1[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_UVD_DOMAIN_ADDR2[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VCE_DOMAIN_ADDR0[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VCE_DOMAIN_ADDR1[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VCE_DOMAIN_ADDR2[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SAM_DOMAIN_ADDR0[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SAM_DOMAIN_ADDR1[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_SAM_DOMAIN_ADDR2[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_ISP_DOMAIN_ADDR0[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_ISP_DOMAIN_ADDR1[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_ISP_DOMAIN_ADDR2[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VP8_DOMAIN_ADDR0[] = {
+	 { "ADDR_LO", 0, 15, &umr_bitfield_default },
+	 { "ADDR_HI", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYS_GRBM_GFX_INDEX_SELECT[] = {
+	 { "SYS_GRBM_GFX_INDEX_SEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSYS_GRBM_GFX_INDEX_DATA[] = {
+	 { "INSTANCE_INDEX", 0, 7, &umr_bitfield_default },
+	 { "SH_INDEX", 8, 15, &umr_bitfield_default },
+	 { "SE_INDEX", 16, 23, &umr_bitfield_default },
+	 { "SH_BROADCAST_WRITES", 29, 29, &umr_bitfield_default },
+	 { "INSTANCE_BROADCAST_WRITES", 30, 30, &umr_bitfield_default },
+	 { "SE_BROADCAST_WRITES", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_GFX_CNTL_SELECT[] = {
+	 { "SRBM_GFX_CNTL_SEL", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_GFX_CNTL_DATA[] = {
+	 { "PIPEID", 0, 1, &umr_bitfield_default },
+	 { "MEID", 2, 3, &umr_bitfield_default },
+	 { "VMID", 4, 7, &umr_bitfield_default },
+	 { "QUEUEID", 8, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VF_ENABLE[] = {
+	 { "VF_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VIRT_CNTL[] = {
+	 { "VF_WRITE_ENABLE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CAM_INDEX[] = {
+	 { "CAM_INDEX", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSRBM_CAM_DATA[] = {
+	 { "CAM_ADDR", 0, 15, &umr_bitfield_default },
+	 { "CAM_REMAPADDR", 16, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/oss30_regs.i b/src/lib/ip/oss30_regs.i
new file mode 100644
index 0000000..21cbb63
--- /dev/null
+++ b/src/lib/ip/oss30_regs.i
@@ -0,0 +1,660 @@
+	{ "ixDH_TEST", REG_SMC, 0x0, &ixDH_TEST[0], sizeof(ixDH_TEST)/sizeof(ixDH_TEST[0]), 0, 0 },
+	{ "ixKHFS3", REG_SMC, 0x10, &ixKHFS3[0], sizeof(ixKHFS3)/sizeof(ixKHFS3[0]), 0, 0 },
+	{ "ixKSESSION0", REG_SMC, 0x14, &ixKSESSION0[0], sizeof(ixKSESSION0)/sizeof(ixKSESSION0[0]), 0, 0 },
+	{ "mmCC_DRM_ID_STRAPS", REG_MMIO, 0x1559, &mmCC_DRM_ID_STRAPS[0], sizeof(mmCC_DRM_ID_STRAPS)/sizeof(mmCC_DRM_ID_STRAPS[0]), 0, 0 },
+	{ "mmCGTT_DRM_CLK_CTRL0", REG_MMIO, 0x1579, NULL, 0, 0, 0 },
+	{ "mmDC_TEST_DEBUG_INDEX", REG_MMIO, 0x157c, &mmDC_TEST_DEBUG_INDEX[0], sizeof(mmDC_TEST_DEBUG_INDEX)/sizeof(mmDC_TEST_DEBUG_INDEX[0]), 0, 0 },
+	{ "mmDC_TEST_DEBUG_DATA", REG_MMIO, 0x157d, &mmDC_TEST_DEBUG_DATA[0], sizeof(mmDC_TEST_DEBUG_DATA)/sizeof(mmDC_TEST_DEBUG_DATA[0]), 0, 0 },
+	{ "ixKSESSION1", REG_SMC, 0x18, &ixKSESSION1[0], sizeof(ixKSESSION1)/sizeof(ixKSESSION1[0]), 0, 0 },
+	{ "ixCLIENT2_K0", REG_SMC, 0x1b4, &ixCLIENT2_K0[0], sizeof(ixCLIENT2_K0)/sizeof(ixCLIENT2_K0[0]), 0, 0 },
+	{ "ixCLIENT2_K1", REG_SMC, 0x1b8, &ixCLIENT2_K1[0], sizeof(ixCLIENT2_K1)/sizeof(ixCLIENT2_K1[0]), 0, 0 },
+	{ "ixCLIENT2_K2", REG_SMC, 0x1bc, &ixCLIENT2_K2[0], sizeof(ixCLIENT2_K2)/sizeof(ixCLIENT2_K2[0]), 0, 0 },
+	{ "ixKSESSION2", REG_SMC, 0x1c, &ixKSESSION2[0], sizeof(ixKSESSION2)/sizeof(ixKSESSION2[0]), 0, 0 },
+	{ "ixCLIENT2_K3", REG_SMC, 0x1c0, &ixCLIENT2_K3[0], sizeof(ixCLIENT2_K3)/sizeof(ixCLIENT2_K3[0]), 0, 0 },
+	{ "ixCLIENT2_CK0", REG_SMC, 0x1c4, &ixCLIENT2_CK0[0], sizeof(ixCLIENT2_CK0)/sizeof(ixCLIENT2_CK0[0]), 0, 0 },
+	{ "ixCLIENT2_CK1", REG_SMC, 0x1c8, &ixCLIENT2_CK1[0], sizeof(ixCLIENT2_CK1)/sizeof(ixCLIENT2_CK1[0]), 0, 0 },
+	{ "ixCLIENT2_CK2", REG_SMC, 0x1cc, &ixCLIENT2_CK2[0], sizeof(ixCLIENT2_CK2)/sizeof(ixCLIENT2_CK2[0]), 0, 0 },
+	{ "ixCLIENT2_CK3", REG_SMC, 0x1d0, &ixCLIENT2_CK3[0], sizeof(ixCLIENT2_CK3)/sizeof(ixCLIENT2_CK3[0]), 0, 0 },
+	{ "ixCLIENT2_CD0", REG_SMC, 0x1d4, &ixCLIENT2_CD0[0], sizeof(ixCLIENT2_CD0)/sizeof(ixCLIENT2_CD0[0]), 0, 0 },
+	{ "ixCLIENT2_CD1", REG_SMC, 0x1d8, &ixCLIENT2_CD1[0], sizeof(ixCLIENT2_CD1)/sizeof(ixCLIENT2_CD1[0]), 0, 0 },
+	{ "ixCLIENT2_CD2", REG_SMC, 0x1dc, &ixCLIENT2_CD2[0], sizeof(ixCLIENT2_CD2)/sizeof(ixCLIENT2_CD2[0]), 0, 0 },
+	{ "ixCLIENT2_CD3", REG_SMC, 0x1e0, &ixCLIENT2_CD3[0], sizeof(ixCLIENT2_CD3)/sizeof(ixCLIENT2_CD3[0]), 0, 0 },
+	{ "ixCLIENT2_BM", REG_SMC, 0x1e4, &ixCLIENT2_BM[0], sizeof(ixCLIENT2_BM)/sizeof(ixCLIENT2_BM[0]), 0, 0 },
+	{ "ixCLIENT2_OFFSET", REG_SMC, 0x1e8, &ixCLIENT2_OFFSET[0], sizeof(ixCLIENT2_OFFSET)/sizeof(ixCLIENT2_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT2_STATUS", REG_SMC, 0x1ec, &ixCLIENT2_STATUS[0], sizeof(ixCLIENT2_STATUS)/sizeof(ixCLIENT2_STATUS[0]), 0, 0 },
+	{ "ixCLIENT0_K0", REG_SMC, 0x1f0, &ixCLIENT0_K0[0], sizeof(ixCLIENT0_K0)/sizeof(ixCLIENT0_K0[0]), 0, 0 },
+	{ "ixCLIENT0_K1", REG_SMC, 0x1f4, &ixCLIENT0_K1[0], sizeof(ixCLIENT0_K1)/sizeof(ixCLIENT0_K1[0]), 0, 0 },
+	{ "ixCLIENT0_K2", REG_SMC, 0x1f8, &ixCLIENT0_K2[0], sizeof(ixCLIENT0_K2)/sizeof(ixCLIENT0_K2[0]), 0, 0 },
+	{ "ixCLIENT0_K3", REG_SMC, 0x1fc, &ixCLIENT0_K3[0], sizeof(ixCLIENT0_K3)/sizeof(ixCLIENT0_K3[0]), 0, 0 },
+	{ "ixKSESSION3", REG_SMC, 0x20, &ixKSESSION3[0], sizeof(ixKSESSION3)/sizeof(ixKSESSION3[0]), 0, 0 },
+	{ "ixCLIENT0_CK0", REG_SMC, 0x200, &ixCLIENT0_CK0[0], sizeof(ixCLIENT0_CK0)/sizeof(ixCLIENT0_CK0[0]), 0, 0 },
+	{ "ixCLIENT0_CK1", REG_SMC, 0x204, &ixCLIENT0_CK1[0], sizeof(ixCLIENT0_CK1)/sizeof(ixCLIENT0_CK1[0]), 0, 0 },
+	{ "ixCLIENT0_CK2", REG_SMC, 0x208, &ixCLIENT0_CK2[0], sizeof(ixCLIENT0_CK2)/sizeof(ixCLIENT0_CK2[0]), 0, 0 },
+	{ "ixCLIENT0_CK3", REG_SMC, 0x20c, &ixCLIENT0_CK3[0], sizeof(ixCLIENT0_CK3)/sizeof(ixCLIENT0_CK3[0]), 0, 0 },
+	{ "ixCLIENT0_CD0", REG_SMC, 0x210, &ixCLIENT0_CD0[0], sizeof(ixCLIENT0_CD0)/sizeof(ixCLIENT0_CD0[0]), 0, 0 },
+	{ "ixCLIENT0_CD1", REG_SMC, 0x214, &ixCLIENT0_CD1[0], sizeof(ixCLIENT0_CD1)/sizeof(ixCLIENT0_CD1[0]), 0, 0 },
+	{ "ixCLIENT0_CD2", REG_SMC, 0x218, &ixCLIENT0_CD2[0], sizeof(ixCLIENT0_CD2)/sizeof(ixCLIENT0_CD2[0]), 0, 0 },
+	{ "ixCLIENT0_CD3", REG_SMC, 0x21c, &ixCLIENT0_CD3[0], sizeof(ixCLIENT0_CD3)/sizeof(ixCLIENT0_CD3[0]), 0, 0 },
+	{ "ixCLIENT0_BM", REG_SMC, 0x220, &ixCLIENT0_BM[0], sizeof(ixCLIENT0_BM)/sizeof(ixCLIENT0_BM[0]), 0, 0 },
+	{ "ixCLIENT0_OFFSET", REG_SMC, 0x224, &ixCLIENT0_OFFSET[0], sizeof(ixCLIENT0_OFFSET)/sizeof(ixCLIENT0_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT0_STATUS", REG_SMC, 0x228, &ixCLIENT0_STATUS[0], sizeof(ixCLIENT0_STATUS)/sizeof(ixCLIENT0_STATUS[0]), 0, 0 },
+	{ "ixCLIENT1_K0", REG_SMC, 0x22c, &ixCLIENT1_K0[0], sizeof(ixCLIENT1_K0)/sizeof(ixCLIENT1_K0[0]), 0, 0 },
+	{ "ixCLIENT1_K1", REG_SMC, 0x230, &ixCLIENT1_K1[0], sizeof(ixCLIENT1_K1)/sizeof(ixCLIENT1_K1[0]), 0, 0 },
+	{ "ixCLIENT1_K2", REG_SMC, 0x234, &ixCLIENT1_K2[0], sizeof(ixCLIENT1_K2)/sizeof(ixCLIENT1_K2[0]), 0, 0 },
+	{ "ixCLIENT1_K3", REG_SMC, 0x238, &ixCLIENT1_K3[0], sizeof(ixCLIENT1_K3)/sizeof(ixCLIENT1_K3[0]), 0, 0 },
+	{ "ixCLIENT1_CK0", REG_SMC, 0x23c, &ixCLIENT1_CK0[0], sizeof(ixCLIENT1_CK0)/sizeof(ixCLIENT1_CK0[0]), 0, 0 },
+	{ "ixKSIG0", REG_SMC, 0x24, &ixKSIG0[0], sizeof(ixKSIG0)/sizeof(ixKSIG0[0]), 0, 0 },
+	{ "ixCLIENT1_CK1", REG_SMC, 0x240, &ixCLIENT1_CK1[0], sizeof(ixCLIENT1_CK1)/sizeof(ixCLIENT1_CK1[0]), 0, 0 },
+	{ "ixCLIENT1_CK2", REG_SMC, 0x244, &ixCLIENT1_CK2[0], sizeof(ixCLIENT1_CK2)/sizeof(ixCLIENT1_CK2[0]), 0, 0 },
+	{ "ixCLIENT1_CK3", REG_SMC, 0x248, &ixCLIENT1_CK3[0], sizeof(ixCLIENT1_CK3)/sizeof(ixCLIENT1_CK3[0]), 0, 0 },
+	{ "ixCLIENT1_CD0", REG_SMC, 0x24c, &ixCLIENT1_CD0[0], sizeof(ixCLIENT1_CD0)/sizeof(ixCLIENT1_CD0[0]), 0, 0 },
+	{ "ixCLIENT1_CD1", REG_SMC, 0x250, &ixCLIENT1_CD1[0], sizeof(ixCLIENT1_CD1)/sizeof(ixCLIENT1_CD1[0]), 0, 0 },
+	{ "ixCLIENT1_CD2", REG_SMC, 0x254, &ixCLIENT1_CD2[0], sizeof(ixCLIENT1_CD2)/sizeof(ixCLIENT1_CD2[0]), 0, 0 },
+	{ "ixCLIENT1_CD3", REG_SMC, 0x258, &ixCLIENT1_CD3[0], sizeof(ixCLIENT1_CD3)/sizeof(ixCLIENT1_CD3[0]), 0, 0 },
+	{ "ixCLIENT1_BM", REG_SMC, 0x25c, &ixCLIENT1_BM[0], sizeof(ixCLIENT1_BM)/sizeof(ixCLIENT1_BM[0]), 0, 0 },
+	{ "ixCLIENT1_OFFSET", REG_SMC, 0x260, &ixCLIENT1_OFFSET[0], sizeof(ixCLIENT1_OFFSET)/sizeof(ixCLIENT1_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT1_PORT_STATUS", REG_SMC, 0x264, &ixCLIENT1_PORT_STATUS[0], sizeof(ixCLIENT1_PORT_STATUS)/sizeof(ixCLIENT1_PORT_STATUS[0]), 0, 0 },
+	{ "ixKEFUSE0", REG_SMC, 0x268, &ixKEFUSE0[0], sizeof(ixKEFUSE0)/sizeof(ixKEFUSE0[0]), 0, 0 },
+	{ "ixKEFUSE1", REG_SMC, 0x26c, &ixKEFUSE1[0], sizeof(ixKEFUSE1)/sizeof(ixKEFUSE1[0]), 0, 0 },
+	{ "ixKEFUSE2", REG_SMC, 0x270, &ixKEFUSE2[0], sizeof(ixKEFUSE2)/sizeof(ixKEFUSE2[0]), 0, 0 },
+	{ "ixKEFUSE3", REG_SMC, 0x274, &ixKEFUSE3[0], sizeof(ixKEFUSE3)/sizeof(ixKEFUSE3[0]), 0, 0 },
+	{ "ixHFS_SEED0", REG_SMC, 0x278, &ixHFS_SEED0[0], sizeof(ixHFS_SEED0)/sizeof(ixHFS_SEED0[0]), 0, 0 },
+	{ "ixHFS_SEED1", REG_SMC, 0x27c, &ixHFS_SEED1[0], sizeof(ixHFS_SEED1)/sizeof(ixHFS_SEED1[0]), 0, 0 },
+	{ "ixKSIG1", REG_SMC, 0x28, &ixKSIG1[0], sizeof(ixKSIG1)/sizeof(ixKSIG1[0]), 0, 0 },
+	{ "ixHFS_SEED2", REG_SMC, 0x280, &ixHFS_SEED2[0], sizeof(ixHFS_SEED2)/sizeof(ixHFS_SEED2[0]), 0, 0 },
+	{ "ixHFS_SEED3", REG_SMC, 0x284, &ixHFS_SEED3[0], sizeof(ixHFS_SEED3)/sizeof(ixHFS_SEED3[0]), 0, 0 },
+	{ "ixRINGOSC_MASK", REG_SMC, 0x288, &ixRINGOSC_MASK[0], sizeof(ixRINGOSC_MASK)/sizeof(ixRINGOSC_MASK[0]), 0, 0 },
+	{ "ixCLIENT0_OFFSET_HI", REG_SMC, 0x290, &ixCLIENT0_OFFSET_HI[0], sizeof(ixCLIENT0_OFFSET_HI)/sizeof(ixCLIENT0_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT1_OFFSET_HI", REG_SMC, 0x294, &ixCLIENT1_OFFSET_HI[0], sizeof(ixCLIENT1_OFFSET_HI)/sizeof(ixCLIENT1_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT2_OFFSET_HI", REG_SMC, 0x298, &ixCLIENT2_OFFSET_HI[0], sizeof(ixCLIENT2_OFFSET_HI)/sizeof(ixCLIENT2_OFFSET_HI[0]), 0, 0 },
+	{ "ixSPU_PORT_STATUS", REG_SMC, 0x29c, &ixSPU_PORT_STATUS[0], sizeof(ixSPU_PORT_STATUS)/sizeof(ixSPU_PORT_STATUS[0]), 0, 0 },
+	{ "ixCLIENT3_OFFSET_HI", REG_SMC, 0x2a0, &ixCLIENT3_OFFSET_HI[0], sizeof(ixCLIENT3_OFFSET_HI)/sizeof(ixCLIENT3_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT3_K0", REG_SMC, 0x2a4, &ixCLIENT3_K0[0], sizeof(ixCLIENT3_K0)/sizeof(ixCLIENT3_K0[0]), 0, 0 },
+	{ "ixCLIENT3_K1", REG_SMC, 0x2a8, &ixCLIENT3_K1[0], sizeof(ixCLIENT3_K1)/sizeof(ixCLIENT3_K1[0]), 0, 0 },
+	{ "ixCLIENT3_K2", REG_SMC, 0x2ac, &ixCLIENT3_K2[0], sizeof(ixCLIENT3_K2)/sizeof(ixCLIENT3_K2[0]), 0, 0 },
+	{ "ixCLIENT3_K3", REG_SMC, 0x2b0, &ixCLIENT3_K3[0], sizeof(ixCLIENT3_K3)/sizeof(ixCLIENT3_K3[0]), 0, 0 },
+	{ "ixCLIENT3_CK0", REG_SMC, 0x2b4, &ixCLIENT3_CK0[0], sizeof(ixCLIENT3_CK0)/sizeof(ixCLIENT3_CK0[0]), 0, 0 },
+	{ "ixCLIENT3_CK1", REG_SMC, 0x2b8, &ixCLIENT3_CK1[0], sizeof(ixCLIENT3_CK1)/sizeof(ixCLIENT3_CK1[0]), 0, 0 },
+	{ "ixCLIENT3_CK2", REG_SMC, 0x2bc, &ixCLIENT3_CK2[0], sizeof(ixCLIENT3_CK2)/sizeof(ixCLIENT3_CK2[0]), 0, 0 },
+	{ "ixKSIG2", REG_SMC, 0x2c, &ixKSIG2[0], sizeof(ixKSIG2)/sizeof(ixKSIG2[0]), 0, 0 },
+	{ "ixCLIENT3_CK3", REG_SMC, 0x2c0, &ixCLIENT3_CK3[0], sizeof(ixCLIENT3_CK3)/sizeof(ixCLIENT3_CK3[0]), 0, 0 },
+	{ "ixCLIENT3_CD0", REG_SMC, 0x2c4, &ixCLIENT3_CD0[0], sizeof(ixCLIENT3_CD0)/sizeof(ixCLIENT3_CD0[0]), 0, 0 },
+	{ "ixCLIENT3_CD1", REG_SMC, 0x2c8, &ixCLIENT3_CD1[0], sizeof(ixCLIENT3_CD1)/sizeof(ixCLIENT3_CD1[0]), 0, 0 },
+	{ "ixCLIENT3_CD2", REG_SMC, 0x2cc, &ixCLIENT3_CD2[0], sizeof(ixCLIENT3_CD2)/sizeof(ixCLIENT3_CD2[0]), 0, 0 },
+	{ "ixCLIENT3_CD3", REG_SMC, 0x2d0, &ixCLIENT3_CD3[0], sizeof(ixCLIENT3_CD3)/sizeof(ixCLIENT3_CD3[0]), 0, 0 },
+	{ "ixCLIENT3_BM", REG_SMC, 0x2d4, &ixCLIENT3_BM[0], sizeof(ixCLIENT3_BM)/sizeof(ixCLIENT3_BM[0]), 0, 0 },
+	{ "ixCLIENT3_OFFSET", REG_SMC, 0x2d8, &ixCLIENT3_OFFSET[0], sizeof(ixCLIENT3_OFFSET)/sizeof(ixCLIENT3_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT3_STATUS", REG_SMC, 0x2dc, &ixCLIENT3_STATUS[0], sizeof(ixCLIENT3_STATUS)/sizeof(ixCLIENT3_STATUS[0]), 0, 0 },
+	{ "ixCLIENT4_OFFSET_HI", REG_SMC, 0x2e0, &ixCLIENT4_OFFSET_HI[0], sizeof(ixCLIENT4_OFFSET_HI)/sizeof(ixCLIENT4_OFFSET_HI[0]), 0, 0 },
+	{ "ixCLIENT4_K0", REG_SMC, 0x2e4, &ixCLIENT4_K0[0], sizeof(ixCLIENT4_K0)/sizeof(ixCLIENT4_K0[0]), 0, 0 },
+	{ "ixCLIENT4_K1", REG_SMC, 0x2e8, &ixCLIENT4_K1[0], sizeof(ixCLIENT4_K1)/sizeof(ixCLIENT4_K1[0]), 0, 0 },
+	{ "ixCLIENT4_K2", REG_SMC, 0x2ec, &ixCLIENT4_K2[0], sizeof(ixCLIENT4_K2)/sizeof(ixCLIENT4_K2[0]), 0, 0 },
+	{ "ixCLIENT4_K3", REG_SMC, 0x2f0, &ixCLIENT4_K3[0], sizeof(ixCLIENT4_K3)/sizeof(ixCLIENT4_K3[0]), 0, 0 },
+	{ "ixCLIENT4_CK0", REG_SMC, 0x2f4, &ixCLIENT4_CK0[0], sizeof(ixCLIENT4_CK0)/sizeof(ixCLIENT4_CK0[0]), 0, 0 },
+	{ "ixCLIENT4_CK1", REG_SMC, 0x2f8, &ixCLIENT4_CK1[0], sizeof(ixCLIENT4_CK1)/sizeof(ixCLIENT4_CK1[0]), 0, 0 },
+	{ "ixCLIENT4_CK2", REG_SMC, 0x2fc, &ixCLIENT4_CK2[0], sizeof(ixCLIENT4_CK2)/sizeof(ixCLIENT4_CK2[0]), 0, 0 },
+	{ "ixKSIG3", REG_SMC, 0x30, &ixKSIG3[0], sizeof(ixKSIG3)/sizeof(ixKSIG3[0]), 0, 0 },
+	{ "ixCLIENT4_CK3", REG_SMC, 0x300, &ixCLIENT4_CK3[0], sizeof(ixCLIENT4_CK3)/sizeof(ixCLIENT4_CK3[0]), 0, 0 },
+	{ "ixCLIENT4_CD0", REG_SMC, 0x304, &ixCLIENT4_CD0[0], sizeof(ixCLIENT4_CD0)/sizeof(ixCLIENT4_CD0[0]), 0, 0 },
+	{ "ixCLIENT4_CD1", REG_SMC, 0x308, &ixCLIENT4_CD1[0], sizeof(ixCLIENT4_CD1)/sizeof(ixCLIENT4_CD1[0]), 0, 0 },
+	{ "ixCLIENT4_CD2", REG_SMC, 0x30c, &ixCLIENT4_CD2[0], sizeof(ixCLIENT4_CD2)/sizeof(ixCLIENT4_CD2[0]), 0, 0 },
+	{ "ixCLIENT4_CD3", REG_SMC, 0x310, &ixCLIENT4_CD3[0], sizeof(ixCLIENT4_CD3)/sizeof(ixCLIENT4_CD3[0]), 0, 0 },
+	{ "ixCLIENT4_BM", REG_SMC, 0x314, &ixCLIENT4_BM[0], sizeof(ixCLIENT4_BM)/sizeof(ixCLIENT4_BM[0]), 0, 0 },
+	{ "ixCLIENT4_OFFSET", REG_SMC, 0x318, &ixCLIENT4_OFFSET[0], sizeof(ixCLIENT4_OFFSET)/sizeof(ixCLIENT4_OFFSET[0]), 0, 0 },
+	{ "ixCLIENT4_STATUS", REG_SMC, 0x31c, &ixCLIENT4_STATUS[0], sizeof(ixCLIENT4_STATUS)/sizeof(ixCLIENT4_STATUS[0]), 0, 0 },
+	{ "ixEXP0", REG_SMC, 0x34, &ixEXP0[0], sizeof(ixEXP0)/sizeof(ixEXP0[0]), 0, 0 },
+	{ "mmSDMA0_UCODE_ADDR", REG_MMIO, 0x3400, &mmSDMA0_UCODE_ADDR[0], sizeof(mmSDMA0_UCODE_ADDR)/sizeof(mmSDMA0_UCODE_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_UCODE_DATA", REG_MMIO, 0x3401, &mmSDMA0_UCODE_DATA[0], sizeof(mmSDMA0_UCODE_DATA)/sizeof(mmSDMA0_UCODE_DATA[0]), 0, 0 },
+	{ "mmSDMA0_POWER_CNTL", REG_MMIO, 0x3402, &mmSDMA0_POWER_CNTL[0], sizeof(mmSDMA0_POWER_CNTL)/sizeof(mmSDMA0_POWER_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_CLK_CTRL", REG_MMIO, 0x3403, &mmSDMA0_CLK_CTRL[0], sizeof(mmSDMA0_CLK_CTRL)/sizeof(mmSDMA0_CLK_CTRL[0]), 0, 0 },
+	{ "mmSDMA0_CNTL", REG_MMIO, 0x3404, &mmSDMA0_CNTL[0], sizeof(mmSDMA0_CNTL)/sizeof(mmSDMA0_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_CHICKEN_BITS", REG_MMIO, 0x3405, &mmSDMA0_CHICKEN_BITS[0], sizeof(mmSDMA0_CHICKEN_BITS)/sizeof(mmSDMA0_CHICKEN_BITS[0]), 0, 0 },
+	{ "mmSDMA0_TILING_CONFIG", REG_MMIO, 0x3406, &mmSDMA0_TILING_CONFIG[0], sizeof(mmSDMA0_TILING_CONFIG)/sizeof(mmSDMA0_TILING_CONFIG[0]), 0, 0 },
+	{ "mmSDMA0_HASH", REG_MMIO, 0x3407, &mmSDMA0_HASH[0], sizeof(mmSDMA0_HASH)/sizeof(mmSDMA0_HASH[0]), 0, 0 },
+	{ "mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x3409, &mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RB_RPTR_FETCH", REG_MMIO, 0x340a, &mmSDMA0_RB_RPTR_FETCH[0], sizeof(mmSDMA0_RB_RPTR_FETCH)/sizeof(mmSDMA0_RB_RPTR_FETCH[0]), 0, 0 },
+	{ "mmSDMA0_IB_OFFSET_FETCH", REG_MMIO, 0x340b, &mmSDMA0_IB_OFFSET_FETCH[0], sizeof(mmSDMA0_IB_OFFSET_FETCH)/sizeof(mmSDMA0_IB_OFFSET_FETCH[0]), 0, 0 },
+	{ "mmSDMA0_PROGRAM", REG_MMIO, 0x340c, &mmSDMA0_PROGRAM[0], sizeof(mmSDMA0_PROGRAM)/sizeof(mmSDMA0_PROGRAM[0]), 0, 0 },
+	{ "mmSDMA0_STATUS_REG", REG_MMIO, 0x340d, &mmSDMA0_STATUS_REG[0], sizeof(mmSDMA0_STATUS_REG)/sizeof(mmSDMA0_STATUS_REG[0]), 0, 0 },
+	{ "mmSDMA0_STATUS1_REG", REG_MMIO, 0x340e, &mmSDMA0_STATUS1_REG[0], sizeof(mmSDMA0_STATUS1_REG)/sizeof(mmSDMA0_STATUS1_REG[0]), 0, 0 },
+	{ "mmSDMA0_RD_BURST_CNTL", REG_MMIO, 0x340f, &mmSDMA0_RD_BURST_CNTL[0], sizeof(mmSDMA0_RD_BURST_CNTL)/sizeof(mmSDMA0_RD_BURST_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_F32_CNTL", REG_MMIO, 0x3412, &mmSDMA0_F32_CNTL[0], sizeof(mmSDMA0_F32_CNTL)/sizeof(mmSDMA0_F32_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_FREEZE", REG_MMIO, 0x3413, &mmSDMA0_FREEZE[0], sizeof(mmSDMA0_FREEZE)/sizeof(mmSDMA0_FREEZE[0]), 0, 0 },
+	{ "mmSDMA0_PHASE0_QUANTUM", REG_MMIO, 0x3414, &mmSDMA0_PHASE0_QUANTUM[0], sizeof(mmSDMA0_PHASE0_QUANTUM)/sizeof(mmSDMA0_PHASE0_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA0_PHASE1_QUANTUM", REG_MMIO, 0x3415, &mmSDMA0_PHASE1_QUANTUM[0], sizeof(mmSDMA0_PHASE1_QUANTUM)/sizeof(mmSDMA0_PHASE1_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA_POWER_GATING", REG_MMIO, 0x3416, &mmSDMA_POWER_GATING[0], sizeof(mmSDMA_POWER_GATING)/sizeof(mmSDMA_POWER_GATING[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_CONFIG", REG_MMIO, 0x3417, &mmSDMA_PGFSM_CONFIG[0], sizeof(mmSDMA_PGFSM_CONFIG)/sizeof(mmSDMA_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_WRITE", REG_MMIO, 0x3418, &mmSDMA_PGFSM_WRITE[0], sizeof(mmSDMA_PGFSM_WRITE)/sizeof(mmSDMA_PGFSM_WRITE[0]), 0, 0 },
+	{ "mmSDMA_PGFSM_READ", REG_MMIO, 0x3419, &mmSDMA_PGFSM_READ[0], sizeof(mmSDMA_PGFSM_READ)/sizeof(mmSDMA_PGFSM_READ[0]), 0, 0 },
+	{ "mmSDMA0_EDC_CONFIG", REG_MMIO, 0x341a, &mmSDMA0_EDC_CONFIG[0], sizeof(mmSDMA0_EDC_CONFIG)/sizeof(mmSDMA0_EDC_CONFIG[0]), 0, 0 },
+	{ "mmSDMA0_BA_THRESHOLD", REG_MMIO, 0x341b, &mmSDMA0_BA_THRESHOLD[0], sizeof(mmSDMA0_BA_THRESHOLD)/sizeof(mmSDMA0_BA_THRESHOLD[0]), 0, 0 },
+	{ "mmSDMA0_ID", REG_MMIO, 0x341c, &mmSDMA0_ID[0], sizeof(mmSDMA0_ID)/sizeof(mmSDMA0_ID[0]), 0, 0 },
+	{ "mmSDMA0_VERSION", REG_MMIO, 0x341d, &mmSDMA0_VERSION[0], sizeof(mmSDMA0_VERSION)/sizeof(mmSDMA0_VERSION[0]), 0, 0 },
+	{ "mmSDMA0_VM_CNTL", REG_MMIO, 0x3420, &mmSDMA0_VM_CNTL[0], sizeof(mmSDMA0_VM_CNTL)/sizeof(mmSDMA0_VM_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_VM_CTX_LO", REG_MMIO, 0x3421, &mmSDMA0_VM_CTX_LO[0], sizeof(mmSDMA0_VM_CTX_LO)/sizeof(mmSDMA0_VM_CTX_LO[0]), 0, 0 },
+	{ "mmSDMA0_VM_CTX_HI", REG_MMIO, 0x3422, &mmSDMA0_VM_CTX_HI[0], sizeof(mmSDMA0_VM_CTX_HI)/sizeof(mmSDMA0_VM_CTX_HI[0]), 0, 0 },
+	{ "mmSDMA0_STATUS2_REG", REG_MMIO, 0x3423, &mmSDMA0_STATUS2_REG[0], sizeof(mmSDMA0_STATUS2_REG)/sizeof(mmSDMA0_STATUS2_REG[0]), 0, 0 },
+	{ "mmSDMA0_ACTIVE_FCN_ID", REG_MMIO, 0x3424, &mmSDMA0_ACTIVE_FCN_ID[0], sizeof(mmSDMA0_ACTIVE_FCN_ID)/sizeof(mmSDMA0_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmSDMA0_VM_CTX_CNTL", REG_MMIO, 0x3425, &mmSDMA0_VM_CTX_CNTL[0], sizeof(mmSDMA0_VM_CTX_CNTL)/sizeof(mmSDMA0_VM_CTX_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_VIRT_RESET_REQ", REG_MMIO, 0x3426, &mmSDMA0_VIRT_RESET_REQ[0], sizeof(mmSDMA0_VIRT_RESET_REQ)/sizeof(mmSDMA0_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmSDMA0_VF_ENABLE", REG_MMIO, 0x3427, &mmSDMA0_VF_ENABLE[0], sizeof(mmSDMA0_VF_ENABLE)/sizeof(mmSDMA0_VF_ENABLE[0]), 0, 0 },
+	{ "mmSDMA0_ATOMIC_CNTL", REG_MMIO, 0x3428, &mmSDMA0_ATOMIC_CNTL[0], sizeof(mmSDMA0_ATOMIC_CNTL)/sizeof(mmSDMA0_ATOMIC_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_ATOMIC_PREOP_LO", REG_MMIO, 0x3429, &mmSDMA0_ATOMIC_PREOP_LO[0], sizeof(mmSDMA0_ATOMIC_PREOP_LO)/sizeof(mmSDMA0_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmSDMA0_ATOMIC_PREOP_HI", REG_MMIO, 0x342a, &mmSDMA0_ATOMIC_PREOP_HI[0], sizeof(mmSDMA0_ATOMIC_PREOP_HI)/sizeof(mmSDMA0_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmSDMA0_POWER_CNTL_IDLE", REG_MMIO, 0x342c, &mmSDMA0_POWER_CNTL_IDLE[0], sizeof(mmSDMA0_POWER_CNTL_IDLE)/sizeof(mmSDMA0_POWER_CNTL_IDLE[0]), 0, 0 },
+	{ "mmSDMA0_PERF_REG_TYPE0", REG_MMIO, 0x3477, &mmSDMA0_PERF_REG_TYPE0[0], sizeof(mmSDMA0_PERF_REG_TYPE0)/sizeof(mmSDMA0_PERF_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA0_CONTEXT_REG_TYPE0", REG_MMIO, 0x3478, &mmSDMA0_CONTEXT_REG_TYPE0[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE0)/sizeof(mmSDMA0_CONTEXT_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA0_CONTEXT_REG_TYPE1", REG_MMIO, 0x3479, &mmSDMA0_CONTEXT_REG_TYPE1[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE1)/sizeof(mmSDMA0_CONTEXT_REG_TYPE1[0]), 0, 0 },
+	{ "mmSDMA0_CONTEXT_REG_TYPE2", REG_MMIO, 0x347a, &mmSDMA0_CONTEXT_REG_TYPE2[0], sizeof(mmSDMA0_CONTEXT_REG_TYPE2)/sizeof(mmSDMA0_CONTEXT_REG_TYPE2[0]), 0, 0 },
+	{ "mmSDMA0_PUB_REG_TYPE0", REG_MMIO, 0x347c, &mmSDMA0_PUB_REG_TYPE0[0], sizeof(mmSDMA0_PUB_REG_TYPE0)/sizeof(mmSDMA0_PUB_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA0_PUB_REG_TYPE1", REG_MMIO, 0x347d, &mmSDMA0_PUB_REG_TYPE1[0], sizeof(mmSDMA0_PUB_REG_TYPE1)/sizeof(mmSDMA0_PUB_REG_TYPE1[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_CNTL", REG_MMIO, 0x3480, &mmSDMA0_GFX_RB_CNTL[0], sizeof(mmSDMA0_GFX_RB_CNTL)/sizeof(mmSDMA0_GFX_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_BASE", REG_MMIO, 0x3481, &mmSDMA0_GFX_RB_BASE[0], sizeof(mmSDMA0_GFX_RB_BASE)/sizeof(mmSDMA0_GFX_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_BASE_HI", REG_MMIO, 0x3482, &mmSDMA0_GFX_RB_BASE_HI[0], sizeof(mmSDMA0_GFX_RB_BASE_HI)/sizeof(mmSDMA0_GFX_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR", REG_MMIO, 0x3483, &mmSDMA0_GFX_RB_RPTR[0], sizeof(mmSDMA0_GFX_RB_RPTR)/sizeof(mmSDMA0_GFX_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR", REG_MMIO, 0x3484, &mmSDMA0_GFX_RB_WPTR[0], sizeof(mmSDMA0_GFX_RB_WPTR)/sizeof(mmSDMA0_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3485, &mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3486, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3487, &mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x3488, &mmSDMA0_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x3489, &mmSDMA0_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_CNTL", REG_MMIO, 0x348a, &mmSDMA0_GFX_IB_CNTL[0], sizeof(mmSDMA0_GFX_IB_CNTL)/sizeof(mmSDMA0_GFX_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_RPTR", REG_MMIO, 0x348b, &mmSDMA0_GFX_IB_RPTR[0], sizeof(mmSDMA0_GFX_IB_RPTR)/sizeof(mmSDMA0_GFX_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_OFFSET", REG_MMIO, 0x348c, &mmSDMA0_GFX_IB_OFFSET[0], sizeof(mmSDMA0_GFX_IB_OFFSET)/sizeof(mmSDMA0_GFX_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_BASE_LO", REG_MMIO, 0x348d, &mmSDMA0_GFX_IB_BASE_LO[0], sizeof(mmSDMA0_GFX_IB_BASE_LO)/sizeof(mmSDMA0_GFX_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_BASE_HI", REG_MMIO, 0x348e, &mmSDMA0_GFX_IB_BASE_HI[0], sizeof(mmSDMA0_GFX_IB_BASE_HI)/sizeof(mmSDMA0_GFX_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_SIZE", REG_MMIO, 0x348f, &mmSDMA0_GFX_IB_SIZE[0], sizeof(mmSDMA0_GFX_IB_SIZE)/sizeof(mmSDMA0_GFX_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_GFX_SKIP_CNTL", REG_MMIO, 0x3490, &mmSDMA0_GFX_SKIP_CNTL[0], sizeof(mmSDMA0_GFX_SKIP_CNTL)/sizeof(mmSDMA0_GFX_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CONTEXT_STATUS", REG_MMIO, 0x3491, &mmSDMA0_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA0_GFX_CONTEXT_STATUS)/sizeof(mmSDMA0_GFX_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_GFX_DOORBELL", REG_MMIO, 0x3492, &mmSDMA0_GFX_DOORBELL[0], sizeof(mmSDMA0_GFX_DOORBELL)/sizeof(mmSDMA0_GFX_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CONTEXT_CNTL", REG_MMIO, 0x3493, &mmSDMA0_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA0_GFX_CONTEXT_CNTL)/sizeof(mmSDMA0_GFX_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_VIRTUAL_ADDR", REG_MMIO, 0x34a7, &mmSDMA0_GFX_VIRTUAL_ADDR[0], sizeof(mmSDMA0_GFX_VIRTUAL_ADDR)/sizeof(mmSDMA0_GFX_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_GFX_APE1_CNTL", REG_MMIO, 0x34a8, &mmSDMA0_GFX_APE1_CNTL[0], sizeof(mmSDMA0_GFX_APE1_CNTL)/sizeof(mmSDMA0_GFX_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_GFX_DOORBELL_LOG", REG_MMIO, 0x34a9, &mmSDMA0_GFX_DOORBELL_LOG[0], sizeof(mmSDMA0_GFX_DOORBELL_LOG)/sizeof(mmSDMA0_GFX_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_GFX_WATERMARK", REG_MMIO, 0x34aa, &mmSDMA0_GFX_WATERMARK[0], sizeof(mmSDMA0_GFX_WATERMARK)/sizeof(mmSDMA0_GFX_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CSA_ADDR_LO", REG_MMIO, 0x34ac, &mmSDMA0_GFX_CSA_ADDR_LO[0], sizeof(mmSDMA0_GFX_CSA_ADDR_LO)/sizeof(mmSDMA0_GFX_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_GFX_CSA_ADDR_HI", REG_MMIO, 0x34ad, &mmSDMA0_GFX_CSA_ADDR_HI[0], sizeof(mmSDMA0_GFX_CSA_ADDR_HI)/sizeof(mmSDMA0_GFX_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_GFX_IB_SUB_REMAIN", REG_MMIO, 0x34af, &mmSDMA0_GFX_IB_SUB_REMAIN[0], sizeof(mmSDMA0_GFX_IB_SUB_REMAIN)/sizeof(mmSDMA0_GFX_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_GFX_PREEMPT", REG_MMIO, 0x34b0, &mmSDMA0_GFX_PREEMPT[0], sizeof(mmSDMA0_GFX_PREEMPT)/sizeof(mmSDMA0_GFX_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_GFX_DUMMY_REG", REG_MMIO, 0x34b1, &mmSDMA0_GFX_DUMMY_REG[0], sizeof(mmSDMA0_GFX_DUMMY_REG)/sizeof(mmSDMA0_GFX_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA0", REG_MMIO, 0x34c1, &mmSDMA0_GFX_MIDCMD_DATA0[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA0)/sizeof(mmSDMA0_GFX_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA1", REG_MMIO, 0x34c2, &mmSDMA0_GFX_MIDCMD_DATA1[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA1)/sizeof(mmSDMA0_GFX_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA2", REG_MMIO, 0x34c3, &mmSDMA0_GFX_MIDCMD_DATA2[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA2)/sizeof(mmSDMA0_GFX_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA3", REG_MMIO, 0x34c4, &mmSDMA0_GFX_MIDCMD_DATA3[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA3)/sizeof(mmSDMA0_GFX_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA4", REG_MMIO, 0x34c5, &mmSDMA0_GFX_MIDCMD_DATA4[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA4)/sizeof(mmSDMA0_GFX_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_DATA5", REG_MMIO, 0x34c6, &mmSDMA0_GFX_MIDCMD_DATA5[0], sizeof(mmSDMA0_GFX_MIDCMD_DATA5)/sizeof(mmSDMA0_GFX_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_GFX_MIDCMD_CNTL", REG_MMIO, 0x34c7, &mmSDMA0_GFX_MIDCMD_CNTL[0], sizeof(mmSDMA0_GFX_MIDCMD_CNTL)/sizeof(mmSDMA0_GFX_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_CNTL", REG_MMIO, 0x3500, &mmSDMA0_RLC0_RB_CNTL[0], sizeof(mmSDMA0_RLC0_RB_CNTL)/sizeof(mmSDMA0_RLC0_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_BASE", REG_MMIO, 0x3501, &mmSDMA0_RLC0_RB_BASE[0], sizeof(mmSDMA0_RLC0_RB_BASE)/sizeof(mmSDMA0_RLC0_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_BASE_HI", REG_MMIO, 0x3502, &mmSDMA0_RLC0_RB_BASE_HI[0], sizeof(mmSDMA0_RLC0_RB_BASE_HI)/sizeof(mmSDMA0_RLC0_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR", REG_MMIO, 0x3503, &mmSDMA0_RLC0_RB_RPTR[0], sizeof(mmSDMA0_RLC0_RB_RPTR)/sizeof(mmSDMA0_RLC0_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR", REG_MMIO, 0x3504, &mmSDMA0_RLC0_RB_WPTR[0], sizeof(mmSDMA0_RLC0_RB_WPTR)/sizeof(mmSDMA0_RLC0_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3505, &mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3506, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3507, &mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x3508, &mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x3509, &mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_CNTL", REG_MMIO, 0x350a, &mmSDMA0_RLC0_IB_CNTL[0], sizeof(mmSDMA0_RLC0_IB_CNTL)/sizeof(mmSDMA0_RLC0_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_RPTR", REG_MMIO, 0x350b, &mmSDMA0_RLC0_IB_RPTR[0], sizeof(mmSDMA0_RLC0_IB_RPTR)/sizeof(mmSDMA0_RLC0_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_OFFSET", REG_MMIO, 0x350c, &mmSDMA0_RLC0_IB_OFFSET[0], sizeof(mmSDMA0_RLC0_IB_OFFSET)/sizeof(mmSDMA0_RLC0_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_BASE_LO", REG_MMIO, 0x350d, &mmSDMA0_RLC0_IB_BASE_LO[0], sizeof(mmSDMA0_RLC0_IB_BASE_LO)/sizeof(mmSDMA0_RLC0_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_BASE_HI", REG_MMIO, 0x350e, &mmSDMA0_RLC0_IB_BASE_HI[0], sizeof(mmSDMA0_RLC0_IB_BASE_HI)/sizeof(mmSDMA0_RLC0_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_SIZE", REG_MMIO, 0x350f, &mmSDMA0_RLC0_IB_SIZE[0], sizeof(mmSDMA0_RLC0_IB_SIZE)/sizeof(mmSDMA0_RLC0_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_SKIP_CNTL", REG_MMIO, 0x3510, &mmSDMA0_RLC0_SKIP_CNTL[0], sizeof(mmSDMA0_RLC0_SKIP_CNTL)/sizeof(mmSDMA0_RLC0_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_CONTEXT_STATUS", REG_MMIO, 0x3511, &mmSDMA0_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC0_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DOORBELL", REG_MMIO, 0x3512, &mmSDMA0_RLC0_DOORBELL[0], sizeof(mmSDMA0_RLC0_DOORBELL)/sizeof(mmSDMA0_RLC0_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_VIRTUAL_ADDR", REG_MMIO, 0x3527, &mmSDMA0_RLC0_VIRTUAL_ADDR[0], sizeof(mmSDMA0_RLC0_VIRTUAL_ADDR)/sizeof(mmSDMA0_RLC0_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_APE1_CNTL", REG_MMIO, 0x3528, &mmSDMA0_RLC0_APE1_CNTL[0], sizeof(mmSDMA0_RLC0_APE1_CNTL)/sizeof(mmSDMA0_RLC0_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DOORBELL_LOG", REG_MMIO, 0x3529, &mmSDMA0_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC0_DOORBELL_LOG)/sizeof(mmSDMA0_RLC0_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_WATERMARK", REG_MMIO, 0x352a, &mmSDMA0_RLC0_WATERMARK[0], sizeof(mmSDMA0_RLC0_WATERMARK)/sizeof(mmSDMA0_RLC0_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_CSA_ADDR_LO", REG_MMIO, 0x352c, &mmSDMA0_RLC0_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC0_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC0_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_CSA_ADDR_HI", REG_MMIO, 0x352d, &mmSDMA0_RLC0_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC0_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC0_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_IB_SUB_REMAIN", REG_MMIO, 0x352f, &mmSDMA0_RLC0_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC0_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC0_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_PREEMPT", REG_MMIO, 0x3530, &mmSDMA0_RLC0_PREEMPT[0], sizeof(mmSDMA0_RLC0_PREEMPT)/sizeof(mmSDMA0_RLC0_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_DUMMY_REG", REG_MMIO, 0x3531, &mmSDMA0_RLC0_DUMMY_REG[0], sizeof(mmSDMA0_RLC0_DUMMY_REG)/sizeof(mmSDMA0_RLC0_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA0", REG_MMIO, 0x3541, &mmSDMA0_RLC0_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA1", REG_MMIO, 0x3542, &mmSDMA0_RLC0_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA2", REG_MMIO, 0x3543, &mmSDMA0_RLC0_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA3", REG_MMIO, 0x3544, &mmSDMA0_RLC0_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA4", REG_MMIO, 0x3545, &mmSDMA0_RLC0_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_DATA5", REG_MMIO, 0x3546, &mmSDMA0_RLC0_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC0_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC0_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC0_MIDCMD_CNTL", REG_MMIO, 0x3547, &mmSDMA0_RLC0_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC0_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC0_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_CNTL", REG_MMIO, 0x3580, &mmSDMA0_RLC1_RB_CNTL[0], sizeof(mmSDMA0_RLC1_RB_CNTL)/sizeof(mmSDMA0_RLC1_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_BASE", REG_MMIO, 0x3581, &mmSDMA0_RLC1_RB_BASE[0], sizeof(mmSDMA0_RLC1_RB_BASE)/sizeof(mmSDMA0_RLC1_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_BASE_HI", REG_MMIO, 0x3582, &mmSDMA0_RLC1_RB_BASE_HI[0], sizeof(mmSDMA0_RLC1_RB_BASE_HI)/sizeof(mmSDMA0_RLC1_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR", REG_MMIO, 0x3583, &mmSDMA0_RLC1_RB_RPTR[0], sizeof(mmSDMA0_RLC1_RB_RPTR)/sizeof(mmSDMA0_RLC1_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR", REG_MMIO, 0x3584, &mmSDMA0_RLC1_RB_WPTR[0], sizeof(mmSDMA0_RLC1_RB_WPTR)/sizeof(mmSDMA0_RLC1_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3585, &mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3586, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3587, &mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x3588, &mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x3589, &mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA0_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_CNTL", REG_MMIO, 0x358a, &mmSDMA0_RLC1_IB_CNTL[0], sizeof(mmSDMA0_RLC1_IB_CNTL)/sizeof(mmSDMA0_RLC1_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_RPTR", REG_MMIO, 0x358b, &mmSDMA0_RLC1_IB_RPTR[0], sizeof(mmSDMA0_RLC1_IB_RPTR)/sizeof(mmSDMA0_RLC1_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_OFFSET", REG_MMIO, 0x358c, &mmSDMA0_RLC1_IB_OFFSET[0], sizeof(mmSDMA0_RLC1_IB_OFFSET)/sizeof(mmSDMA0_RLC1_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_BASE_LO", REG_MMIO, 0x358d, &mmSDMA0_RLC1_IB_BASE_LO[0], sizeof(mmSDMA0_RLC1_IB_BASE_LO)/sizeof(mmSDMA0_RLC1_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_BASE_HI", REG_MMIO, 0x358e, &mmSDMA0_RLC1_IB_BASE_HI[0], sizeof(mmSDMA0_RLC1_IB_BASE_HI)/sizeof(mmSDMA0_RLC1_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_SIZE", REG_MMIO, 0x358f, &mmSDMA0_RLC1_IB_SIZE[0], sizeof(mmSDMA0_RLC1_IB_SIZE)/sizeof(mmSDMA0_RLC1_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_SKIP_CNTL", REG_MMIO, 0x3590, &mmSDMA0_RLC1_SKIP_CNTL[0], sizeof(mmSDMA0_RLC1_SKIP_CNTL)/sizeof(mmSDMA0_RLC1_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_CONTEXT_STATUS", REG_MMIO, 0x3591, &mmSDMA0_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA0_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA0_RLC1_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DOORBELL", REG_MMIO, 0x3592, &mmSDMA0_RLC1_DOORBELL[0], sizeof(mmSDMA0_RLC1_DOORBELL)/sizeof(mmSDMA0_RLC1_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_VIRTUAL_ADDR", REG_MMIO, 0x35a7, &mmSDMA0_RLC1_VIRTUAL_ADDR[0], sizeof(mmSDMA0_RLC1_VIRTUAL_ADDR)/sizeof(mmSDMA0_RLC1_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_APE1_CNTL", REG_MMIO, 0x35a8, &mmSDMA0_RLC1_APE1_CNTL[0], sizeof(mmSDMA0_RLC1_APE1_CNTL)/sizeof(mmSDMA0_RLC1_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DOORBELL_LOG", REG_MMIO, 0x35a9, &mmSDMA0_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA0_RLC1_DOORBELL_LOG)/sizeof(mmSDMA0_RLC1_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_WATERMARK", REG_MMIO, 0x35aa, &mmSDMA0_RLC1_WATERMARK[0], sizeof(mmSDMA0_RLC1_WATERMARK)/sizeof(mmSDMA0_RLC1_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_CSA_ADDR_LO", REG_MMIO, 0x35ac, &mmSDMA0_RLC1_CSA_ADDR_LO[0], sizeof(mmSDMA0_RLC1_CSA_ADDR_LO)/sizeof(mmSDMA0_RLC1_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_CSA_ADDR_HI", REG_MMIO, 0x35ad, &mmSDMA0_RLC1_CSA_ADDR_HI[0], sizeof(mmSDMA0_RLC1_CSA_ADDR_HI)/sizeof(mmSDMA0_RLC1_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_IB_SUB_REMAIN", REG_MMIO, 0x35af, &mmSDMA0_RLC1_IB_SUB_REMAIN[0], sizeof(mmSDMA0_RLC1_IB_SUB_REMAIN)/sizeof(mmSDMA0_RLC1_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_PREEMPT", REG_MMIO, 0x35b0, &mmSDMA0_RLC1_PREEMPT[0], sizeof(mmSDMA0_RLC1_PREEMPT)/sizeof(mmSDMA0_RLC1_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_DUMMY_REG", REG_MMIO, 0x35b1, &mmSDMA0_RLC1_DUMMY_REG[0], sizeof(mmSDMA0_RLC1_DUMMY_REG)/sizeof(mmSDMA0_RLC1_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA0", REG_MMIO, 0x35c1, &mmSDMA0_RLC1_MIDCMD_DATA0[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA0)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA1", REG_MMIO, 0x35c2, &mmSDMA0_RLC1_MIDCMD_DATA1[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA1)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA2", REG_MMIO, 0x35c3, &mmSDMA0_RLC1_MIDCMD_DATA2[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA2)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA3", REG_MMIO, 0x35c4, &mmSDMA0_RLC1_MIDCMD_DATA3[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA3)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA4", REG_MMIO, 0x35c5, &mmSDMA0_RLC1_MIDCMD_DATA4[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA4)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_DATA5", REG_MMIO, 0x35c6, &mmSDMA0_RLC1_MIDCMD_DATA5[0], sizeof(mmSDMA0_RLC1_MIDCMD_DATA5)/sizeof(mmSDMA0_RLC1_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA0_RLC1_MIDCMD_CNTL", REG_MMIO, 0x35c7, &mmSDMA0_RLC1_MIDCMD_CNTL[0], sizeof(mmSDMA0_RLC1_MIDCMD_CNTL)/sizeof(mmSDMA0_RLC1_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_UCODE_ADDR", REG_MMIO, 0x3600, &mmSDMA1_UCODE_ADDR[0], sizeof(mmSDMA1_UCODE_ADDR)/sizeof(mmSDMA1_UCODE_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_UCODE_DATA", REG_MMIO, 0x3601, &mmSDMA1_UCODE_DATA[0], sizeof(mmSDMA1_UCODE_DATA)/sizeof(mmSDMA1_UCODE_DATA[0]), 0, 0 },
+	{ "mmSDMA1_POWER_CNTL", REG_MMIO, 0x3602, &mmSDMA1_POWER_CNTL[0], sizeof(mmSDMA1_POWER_CNTL)/sizeof(mmSDMA1_POWER_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_CLK_CTRL", REG_MMIO, 0x3603, &mmSDMA1_CLK_CTRL[0], sizeof(mmSDMA1_CLK_CTRL)/sizeof(mmSDMA1_CLK_CTRL[0]), 0, 0 },
+	{ "mmSDMA1_CNTL", REG_MMIO, 0x3604, &mmSDMA1_CNTL[0], sizeof(mmSDMA1_CNTL)/sizeof(mmSDMA1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_CHICKEN_BITS", REG_MMIO, 0x3605, &mmSDMA1_CHICKEN_BITS[0], sizeof(mmSDMA1_CHICKEN_BITS)/sizeof(mmSDMA1_CHICKEN_BITS[0]), 0, 0 },
+	{ "mmSDMA1_TILING_CONFIG", REG_MMIO, 0x3606, &mmSDMA1_TILING_CONFIG[0], sizeof(mmSDMA1_TILING_CONFIG)/sizeof(mmSDMA1_TILING_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_HASH", REG_MMIO, 0x3607, &mmSDMA1_HASH[0], sizeof(mmSDMA1_HASH)/sizeof(mmSDMA1_HASH[0]), 0, 0 },
+	{ "mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL", REG_MMIO, 0x3609, &mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[0], sizeof(mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL)/sizeof(mmSDMA1_SEM_WAIT_FAIL_TIMER_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RB_RPTR_FETCH", REG_MMIO, 0x360a, &mmSDMA1_RB_RPTR_FETCH[0], sizeof(mmSDMA1_RB_RPTR_FETCH)/sizeof(mmSDMA1_RB_RPTR_FETCH[0]), 0, 0 },
+	{ "mmSDMA1_IB_OFFSET_FETCH", REG_MMIO, 0x360b, &mmSDMA1_IB_OFFSET_FETCH[0], sizeof(mmSDMA1_IB_OFFSET_FETCH)/sizeof(mmSDMA1_IB_OFFSET_FETCH[0]), 0, 0 },
+	{ "mmSDMA1_PROGRAM", REG_MMIO, 0x360c, &mmSDMA1_PROGRAM[0], sizeof(mmSDMA1_PROGRAM)/sizeof(mmSDMA1_PROGRAM[0]), 0, 0 },
+	{ "mmSDMA1_STATUS_REG", REG_MMIO, 0x360d, &mmSDMA1_STATUS_REG[0], sizeof(mmSDMA1_STATUS_REG)/sizeof(mmSDMA1_STATUS_REG[0]), 0, 0 },
+	{ "mmSDMA1_STATUS1_REG", REG_MMIO, 0x360e, &mmSDMA1_STATUS1_REG[0], sizeof(mmSDMA1_STATUS1_REG)/sizeof(mmSDMA1_STATUS1_REG[0]), 0, 0 },
+	{ "mmSDMA1_RD_BURST_CNTL", REG_MMIO, 0x360f, &mmSDMA1_RD_BURST_CNTL[0], sizeof(mmSDMA1_RD_BURST_CNTL)/sizeof(mmSDMA1_RD_BURST_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_F32_CNTL", REG_MMIO, 0x3612, &mmSDMA1_F32_CNTL[0], sizeof(mmSDMA1_F32_CNTL)/sizeof(mmSDMA1_F32_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_FREEZE", REG_MMIO, 0x3613, &mmSDMA1_FREEZE[0], sizeof(mmSDMA1_FREEZE)/sizeof(mmSDMA1_FREEZE[0]), 0, 0 },
+	{ "mmSDMA1_PHASE0_QUANTUM", REG_MMIO, 0x3614, &mmSDMA1_PHASE0_QUANTUM[0], sizeof(mmSDMA1_PHASE0_QUANTUM)/sizeof(mmSDMA1_PHASE0_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA1_PHASE1_QUANTUM", REG_MMIO, 0x3615, &mmSDMA1_PHASE1_QUANTUM[0], sizeof(mmSDMA1_PHASE1_QUANTUM)/sizeof(mmSDMA1_PHASE1_QUANTUM[0]), 0, 0 },
+	{ "mmSDMA1_EDC_CONFIG", REG_MMIO, 0x361a, &mmSDMA1_EDC_CONFIG[0], sizeof(mmSDMA1_EDC_CONFIG)/sizeof(mmSDMA1_EDC_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_BA_THRESHOLD", REG_MMIO, 0x361b, &mmSDMA1_BA_THRESHOLD[0], sizeof(mmSDMA1_BA_THRESHOLD)/sizeof(mmSDMA1_BA_THRESHOLD[0]), 0, 0 },
+	{ "mmSDMA1_ID", REG_MMIO, 0x361c, &mmSDMA1_ID[0], sizeof(mmSDMA1_ID)/sizeof(mmSDMA1_ID[0]), 0, 0 },
+	{ "mmSDMA1_VERSION", REG_MMIO, 0x361d, &mmSDMA1_VERSION[0], sizeof(mmSDMA1_VERSION)/sizeof(mmSDMA1_VERSION[0]), 0, 0 },
+	{ "mmSDMA1_VM_CNTL", REG_MMIO, 0x3620, &mmSDMA1_VM_CNTL[0], sizeof(mmSDMA1_VM_CNTL)/sizeof(mmSDMA1_VM_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_VM_CTX_LO", REG_MMIO, 0x3621, &mmSDMA1_VM_CTX_LO[0], sizeof(mmSDMA1_VM_CTX_LO)/sizeof(mmSDMA1_VM_CTX_LO[0]), 0, 0 },
+	{ "mmSDMA1_VM_CTX_HI", REG_MMIO, 0x3622, &mmSDMA1_VM_CTX_HI[0], sizeof(mmSDMA1_VM_CTX_HI)/sizeof(mmSDMA1_VM_CTX_HI[0]), 0, 0 },
+	{ "mmSDMA1_STATUS2_REG", REG_MMIO, 0x3623, &mmSDMA1_STATUS2_REG[0], sizeof(mmSDMA1_STATUS2_REG)/sizeof(mmSDMA1_STATUS2_REG[0]), 0, 0 },
+	{ "mmSDMA1_ACTIVE_FCN_ID", REG_MMIO, 0x3624, &mmSDMA1_ACTIVE_FCN_ID[0], sizeof(mmSDMA1_ACTIVE_FCN_ID)/sizeof(mmSDMA1_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmSDMA1_VM_CTX_CNTL", REG_MMIO, 0x3625, &mmSDMA1_VM_CTX_CNTL[0], sizeof(mmSDMA1_VM_CTX_CNTL)/sizeof(mmSDMA1_VM_CTX_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_VIRT_RESET_REQ", REG_MMIO, 0x3626, &mmSDMA1_VIRT_RESET_REQ[0], sizeof(mmSDMA1_VIRT_RESET_REQ)/sizeof(mmSDMA1_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmSDMA1_VF_ENABLE", REG_MMIO, 0x3627, &mmSDMA1_VF_ENABLE[0], sizeof(mmSDMA1_VF_ENABLE)/sizeof(mmSDMA1_VF_ENABLE[0]), 0, 0 },
+	{ "mmSDMA1_ATOMIC_CNTL", REG_MMIO, 0x3628, &mmSDMA1_ATOMIC_CNTL[0], sizeof(mmSDMA1_ATOMIC_CNTL)/sizeof(mmSDMA1_ATOMIC_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_ATOMIC_PREOP_LO", REG_MMIO, 0x3629, &mmSDMA1_ATOMIC_PREOP_LO[0], sizeof(mmSDMA1_ATOMIC_PREOP_LO)/sizeof(mmSDMA1_ATOMIC_PREOP_LO[0]), 0, 0 },
+	{ "mmSDMA1_ATOMIC_PREOP_HI", REG_MMIO, 0x362a, &mmSDMA1_ATOMIC_PREOP_HI[0], sizeof(mmSDMA1_ATOMIC_PREOP_HI)/sizeof(mmSDMA1_ATOMIC_PREOP_HI[0]), 0, 0 },
+	{ "mmSDMA1_POWER_CNTL_IDLE", REG_MMIO, 0x362c, &mmSDMA1_POWER_CNTL_IDLE[0], sizeof(mmSDMA1_POWER_CNTL_IDLE)/sizeof(mmSDMA1_POWER_CNTL_IDLE[0]), 0, 0 },
+	{ "mmSDMA1_PERF_REG_TYPE0", REG_MMIO, 0x3677, &mmSDMA1_PERF_REG_TYPE0[0], sizeof(mmSDMA1_PERF_REG_TYPE0)/sizeof(mmSDMA1_PERF_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA1_CONTEXT_REG_TYPE0", REG_MMIO, 0x3678, &mmSDMA1_CONTEXT_REG_TYPE0[0], sizeof(mmSDMA1_CONTEXT_REG_TYPE0)/sizeof(mmSDMA1_CONTEXT_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA1_CONTEXT_REG_TYPE1", REG_MMIO, 0x3679, &mmSDMA1_CONTEXT_REG_TYPE1[0], sizeof(mmSDMA1_CONTEXT_REG_TYPE1)/sizeof(mmSDMA1_CONTEXT_REG_TYPE1[0]), 0, 0 },
+	{ "mmSDMA1_CONTEXT_REG_TYPE2", REG_MMIO, 0x367a, &mmSDMA1_CONTEXT_REG_TYPE2[0], sizeof(mmSDMA1_CONTEXT_REG_TYPE2)/sizeof(mmSDMA1_CONTEXT_REG_TYPE2[0]), 0, 0 },
+	{ "mmSDMA1_PUB_REG_TYPE0", REG_MMIO, 0x367c, &mmSDMA1_PUB_REG_TYPE0[0], sizeof(mmSDMA1_PUB_REG_TYPE0)/sizeof(mmSDMA1_PUB_REG_TYPE0[0]), 0, 0 },
+	{ "mmSDMA1_PUB_REG_TYPE1", REG_MMIO, 0x367d, &mmSDMA1_PUB_REG_TYPE1[0], sizeof(mmSDMA1_PUB_REG_TYPE1)/sizeof(mmSDMA1_PUB_REG_TYPE1[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_CNTL", REG_MMIO, 0x3680, &mmSDMA1_GFX_RB_CNTL[0], sizeof(mmSDMA1_GFX_RB_CNTL)/sizeof(mmSDMA1_GFX_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_BASE", REG_MMIO, 0x3681, &mmSDMA1_GFX_RB_BASE[0], sizeof(mmSDMA1_GFX_RB_BASE)/sizeof(mmSDMA1_GFX_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_BASE_HI", REG_MMIO, 0x3682, &mmSDMA1_GFX_RB_BASE_HI[0], sizeof(mmSDMA1_GFX_RB_BASE_HI)/sizeof(mmSDMA1_GFX_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR", REG_MMIO, 0x3683, &mmSDMA1_GFX_RB_RPTR[0], sizeof(mmSDMA1_GFX_RB_RPTR)/sizeof(mmSDMA1_GFX_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR", REG_MMIO, 0x3684, &mmSDMA1_GFX_RB_WPTR[0], sizeof(mmSDMA1_GFX_RB_WPTR)/sizeof(mmSDMA1_GFX_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3685, &mmSDMA1_GFX_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3686, &mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3687, &mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_GFX_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR_ADDR_HI", REG_MMIO, 0x3688, &mmSDMA1_GFX_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_RB_RPTR_ADDR_LO", REG_MMIO, 0x3689, &mmSDMA1_GFX_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_GFX_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_CNTL", REG_MMIO, 0x368a, &mmSDMA1_GFX_IB_CNTL[0], sizeof(mmSDMA1_GFX_IB_CNTL)/sizeof(mmSDMA1_GFX_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_RPTR", REG_MMIO, 0x368b, &mmSDMA1_GFX_IB_RPTR[0], sizeof(mmSDMA1_GFX_IB_RPTR)/sizeof(mmSDMA1_GFX_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_OFFSET", REG_MMIO, 0x368c, &mmSDMA1_GFX_IB_OFFSET[0], sizeof(mmSDMA1_GFX_IB_OFFSET)/sizeof(mmSDMA1_GFX_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_BASE_LO", REG_MMIO, 0x368d, &mmSDMA1_GFX_IB_BASE_LO[0], sizeof(mmSDMA1_GFX_IB_BASE_LO)/sizeof(mmSDMA1_GFX_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_BASE_HI", REG_MMIO, 0x368e, &mmSDMA1_GFX_IB_BASE_HI[0], sizeof(mmSDMA1_GFX_IB_BASE_HI)/sizeof(mmSDMA1_GFX_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_SIZE", REG_MMIO, 0x368f, &mmSDMA1_GFX_IB_SIZE[0], sizeof(mmSDMA1_GFX_IB_SIZE)/sizeof(mmSDMA1_GFX_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_GFX_SKIP_CNTL", REG_MMIO, 0x3690, &mmSDMA1_GFX_SKIP_CNTL[0], sizeof(mmSDMA1_GFX_SKIP_CNTL)/sizeof(mmSDMA1_GFX_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CONTEXT_STATUS", REG_MMIO, 0x3691, &mmSDMA1_GFX_CONTEXT_STATUS[0], sizeof(mmSDMA1_GFX_CONTEXT_STATUS)/sizeof(mmSDMA1_GFX_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_GFX_DOORBELL", REG_MMIO, 0x3692, &mmSDMA1_GFX_DOORBELL[0], sizeof(mmSDMA1_GFX_DOORBELL)/sizeof(mmSDMA1_GFX_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CONTEXT_CNTL", REG_MMIO, 0x3693, &mmSDMA1_GFX_CONTEXT_CNTL[0], sizeof(mmSDMA1_GFX_CONTEXT_CNTL)/sizeof(mmSDMA1_GFX_CONTEXT_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_VIRTUAL_ADDR", REG_MMIO, 0x36a7, &mmSDMA1_GFX_VIRTUAL_ADDR[0], sizeof(mmSDMA1_GFX_VIRTUAL_ADDR)/sizeof(mmSDMA1_GFX_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_GFX_APE1_CNTL", REG_MMIO, 0x36a8, &mmSDMA1_GFX_APE1_CNTL[0], sizeof(mmSDMA1_GFX_APE1_CNTL)/sizeof(mmSDMA1_GFX_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_GFX_DOORBELL_LOG", REG_MMIO, 0x36a9, &mmSDMA1_GFX_DOORBELL_LOG[0], sizeof(mmSDMA1_GFX_DOORBELL_LOG)/sizeof(mmSDMA1_GFX_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_GFX_WATERMARK", REG_MMIO, 0x36aa, &mmSDMA1_GFX_WATERMARK[0], sizeof(mmSDMA1_GFX_WATERMARK)/sizeof(mmSDMA1_GFX_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CSA_ADDR_LO", REG_MMIO, 0x36ac, &mmSDMA1_GFX_CSA_ADDR_LO[0], sizeof(mmSDMA1_GFX_CSA_ADDR_LO)/sizeof(mmSDMA1_GFX_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_GFX_CSA_ADDR_HI", REG_MMIO, 0x36ad, &mmSDMA1_GFX_CSA_ADDR_HI[0], sizeof(mmSDMA1_GFX_CSA_ADDR_HI)/sizeof(mmSDMA1_GFX_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_GFX_IB_SUB_REMAIN", REG_MMIO, 0x36af, &mmSDMA1_GFX_IB_SUB_REMAIN[0], sizeof(mmSDMA1_GFX_IB_SUB_REMAIN)/sizeof(mmSDMA1_GFX_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_GFX_PREEMPT", REG_MMIO, 0x36b0, &mmSDMA1_GFX_PREEMPT[0], sizeof(mmSDMA1_GFX_PREEMPT)/sizeof(mmSDMA1_GFX_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_GFX_DUMMY_REG", REG_MMIO, 0x36b1, &mmSDMA1_GFX_DUMMY_REG[0], sizeof(mmSDMA1_GFX_DUMMY_REG)/sizeof(mmSDMA1_GFX_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA0", REG_MMIO, 0x36c1, &mmSDMA1_GFX_MIDCMD_DATA0[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA0)/sizeof(mmSDMA1_GFX_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA1", REG_MMIO, 0x36c2, &mmSDMA1_GFX_MIDCMD_DATA1[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA1)/sizeof(mmSDMA1_GFX_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA2", REG_MMIO, 0x36c3, &mmSDMA1_GFX_MIDCMD_DATA2[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA2)/sizeof(mmSDMA1_GFX_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA3", REG_MMIO, 0x36c4, &mmSDMA1_GFX_MIDCMD_DATA3[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA3)/sizeof(mmSDMA1_GFX_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA4", REG_MMIO, 0x36c5, &mmSDMA1_GFX_MIDCMD_DATA4[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA4)/sizeof(mmSDMA1_GFX_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_DATA5", REG_MMIO, 0x36c6, &mmSDMA1_GFX_MIDCMD_DATA5[0], sizeof(mmSDMA1_GFX_MIDCMD_DATA5)/sizeof(mmSDMA1_GFX_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_GFX_MIDCMD_CNTL", REG_MMIO, 0x36c7, &mmSDMA1_GFX_MIDCMD_CNTL[0], sizeof(mmSDMA1_GFX_MIDCMD_CNTL)/sizeof(mmSDMA1_GFX_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_CNTL", REG_MMIO, 0x3700, &mmSDMA1_RLC0_RB_CNTL[0], sizeof(mmSDMA1_RLC0_RB_CNTL)/sizeof(mmSDMA1_RLC0_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_BASE", REG_MMIO, 0x3701, &mmSDMA1_RLC0_RB_BASE[0], sizeof(mmSDMA1_RLC0_RB_BASE)/sizeof(mmSDMA1_RLC0_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_BASE_HI", REG_MMIO, 0x3702, &mmSDMA1_RLC0_RB_BASE_HI[0], sizeof(mmSDMA1_RLC0_RB_BASE_HI)/sizeof(mmSDMA1_RLC0_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR", REG_MMIO, 0x3703, &mmSDMA1_RLC0_RB_RPTR[0], sizeof(mmSDMA1_RLC0_RB_RPTR)/sizeof(mmSDMA1_RLC0_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR", REG_MMIO, 0x3704, &mmSDMA1_RLC0_RB_WPTR[0], sizeof(mmSDMA1_RLC0_RB_WPTR)/sizeof(mmSDMA1_RLC0_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3705, &mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3706, &mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3707, &mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC0_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR_ADDR_HI", REG_MMIO, 0x3708, &mmSDMA1_RLC0_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_RB_RPTR_ADDR_LO", REG_MMIO, 0x3709, &mmSDMA1_RLC0_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC0_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_CNTL", REG_MMIO, 0x370a, &mmSDMA1_RLC0_IB_CNTL[0], sizeof(mmSDMA1_RLC0_IB_CNTL)/sizeof(mmSDMA1_RLC0_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_RPTR", REG_MMIO, 0x370b, &mmSDMA1_RLC0_IB_RPTR[0], sizeof(mmSDMA1_RLC0_IB_RPTR)/sizeof(mmSDMA1_RLC0_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_OFFSET", REG_MMIO, 0x370c, &mmSDMA1_RLC0_IB_OFFSET[0], sizeof(mmSDMA1_RLC0_IB_OFFSET)/sizeof(mmSDMA1_RLC0_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_BASE_LO", REG_MMIO, 0x370d, &mmSDMA1_RLC0_IB_BASE_LO[0], sizeof(mmSDMA1_RLC0_IB_BASE_LO)/sizeof(mmSDMA1_RLC0_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_BASE_HI", REG_MMIO, 0x370e, &mmSDMA1_RLC0_IB_BASE_HI[0], sizeof(mmSDMA1_RLC0_IB_BASE_HI)/sizeof(mmSDMA1_RLC0_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_SIZE", REG_MMIO, 0x370f, &mmSDMA1_RLC0_IB_SIZE[0], sizeof(mmSDMA1_RLC0_IB_SIZE)/sizeof(mmSDMA1_RLC0_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_SKIP_CNTL", REG_MMIO, 0x3710, &mmSDMA1_RLC0_SKIP_CNTL[0], sizeof(mmSDMA1_RLC0_SKIP_CNTL)/sizeof(mmSDMA1_RLC0_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_CONTEXT_STATUS", REG_MMIO, 0x3711, &mmSDMA1_RLC0_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC0_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC0_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DOORBELL", REG_MMIO, 0x3712, &mmSDMA1_RLC0_DOORBELL[0], sizeof(mmSDMA1_RLC0_DOORBELL)/sizeof(mmSDMA1_RLC0_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_VIRTUAL_ADDR", REG_MMIO, 0x3727, &mmSDMA1_RLC0_VIRTUAL_ADDR[0], sizeof(mmSDMA1_RLC0_VIRTUAL_ADDR)/sizeof(mmSDMA1_RLC0_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_APE1_CNTL", REG_MMIO, 0x3728, &mmSDMA1_RLC0_APE1_CNTL[0], sizeof(mmSDMA1_RLC0_APE1_CNTL)/sizeof(mmSDMA1_RLC0_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DOORBELL_LOG", REG_MMIO, 0x3729, &mmSDMA1_RLC0_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC0_DOORBELL_LOG)/sizeof(mmSDMA1_RLC0_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_WATERMARK", REG_MMIO, 0x372a, &mmSDMA1_RLC0_WATERMARK[0], sizeof(mmSDMA1_RLC0_WATERMARK)/sizeof(mmSDMA1_RLC0_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_CSA_ADDR_LO", REG_MMIO, 0x372c, &mmSDMA1_RLC0_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC0_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC0_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_CSA_ADDR_HI", REG_MMIO, 0x372d, &mmSDMA1_RLC0_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC0_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC0_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_IB_SUB_REMAIN", REG_MMIO, 0x372f, &mmSDMA1_RLC0_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC0_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC0_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_PREEMPT", REG_MMIO, 0x3730, &mmSDMA1_RLC0_PREEMPT[0], sizeof(mmSDMA1_RLC0_PREEMPT)/sizeof(mmSDMA1_RLC0_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_DUMMY_REG", REG_MMIO, 0x3731, &mmSDMA1_RLC0_DUMMY_REG[0], sizeof(mmSDMA1_RLC0_DUMMY_REG)/sizeof(mmSDMA1_RLC0_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA0", REG_MMIO, 0x3741, &mmSDMA1_RLC0_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA1", REG_MMIO, 0x3742, &mmSDMA1_RLC0_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA2", REG_MMIO, 0x3743, &mmSDMA1_RLC0_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA3", REG_MMIO, 0x3744, &mmSDMA1_RLC0_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA4", REG_MMIO, 0x3745, &mmSDMA1_RLC0_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_DATA5", REG_MMIO, 0x3746, &mmSDMA1_RLC0_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC0_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC0_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC0_MIDCMD_CNTL", REG_MMIO, 0x3747, &mmSDMA1_RLC0_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC0_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC0_MIDCMD_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_CNTL", REG_MMIO, 0x3780, &mmSDMA1_RLC1_RB_CNTL[0], sizeof(mmSDMA1_RLC1_RB_CNTL)/sizeof(mmSDMA1_RLC1_RB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_BASE", REG_MMIO, 0x3781, &mmSDMA1_RLC1_RB_BASE[0], sizeof(mmSDMA1_RLC1_RB_BASE)/sizeof(mmSDMA1_RLC1_RB_BASE[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_BASE_HI", REG_MMIO, 0x3782, &mmSDMA1_RLC1_RB_BASE_HI[0], sizeof(mmSDMA1_RLC1_RB_BASE_HI)/sizeof(mmSDMA1_RLC1_RB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR", REG_MMIO, 0x3783, &mmSDMA1_RLC1_RB_RPTR[0], sizeof(mmSDMA1_RLC1_RB_RPTR)/sizeof(mmSDMA1_RLC1_RB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR", REG_MMIO, 0x3784, &mmSDMA1_RLC1_RB_WPTR[0], sizeof(mmSDMA1_RLC1_RB_WPTR)/sizeof(mmSDMA1_RLC1_RB_WPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_CNTL", REG_MMIO, 0x3785, &mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_CNTL)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI", REG_MMIO, 0x3786, &mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO", REG_MMIO, 0x3787, &mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[0], sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO)/sizeof(mmSDMA1_RLC1_RB_WPTR_POLL_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR_ADDR_HI", REG_MMIO, 0x3788, &mmSDMA1_RLC1_RB_RPTR_ADDR_HI[0], sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_HI)/sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_RB_RPTR_ADDR_LO", REG_MMIO, 0x3789, &mmSDMA1_RLC1_RB_RPTR_ADDR_LO[0], sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_LO)/sizeof(mmSDMA1_RLC1_RB_RPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_CNTL", REG_MMIO, 0x378a, &mmSDMA1_RLC1_IB_CNTL[0], sizeof(mmSDMA1_RLC1_IB_CNTL)/sizeof(mmSDMA1_RLC1_IB_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_RPTR", REG_MMIO, 0x378b, &mmSDMA1_RLC1_IB_RPTR[0], sizeof(mmSDMA1_RLC1_IB_RPTR)/sizeof(mmSDMA1_RLC1_IB_RPTR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_OFFSET", REG_MMIO, 0x378c, &mmSDMA1_RLC1_IB_OFFSET[0], sizeof(mmSDMA1_RLC1_IB_OFFSET)/sizeof(mmSDMA1_RLC1_IB_OFFSET[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_BASE_LO", REG_MMIO, 0x378d, &mmSDMA1_RLC1_IB_BASE_LO[0], sizeof(mmSDMA1_RLC1_IB_BASE_LO)/sizeof(mmSDMA1_RLC1_IB_BASE_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_BASE_HI", REG_MMIO, 0x378e, &mmSDMA1_RLC1_IB_BASE_HI[0], sizeof(mmSDMA1_RLC1_IB_BASE_HI)/sizeof(mmSDMA1_RLC1_IB_BASE_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_SIZE", REG_MMIO, 0x378f, &mmSDMA1_RLC1_IB_SIZE[0], sizeof(mmSDMA1_RLC1_IB_SIZE)/sizeof(mmSDMA1_RLC1_IB_SIZE[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_SKIP_CNTL", REG_MMIO, 0x3790, &mmSDMA1_RLC1_SKIP_CNTL[0], sizeof(mmSDMA1_RLC1_SKIP_CNTL)/sizeof(mmSDMA1_RLC1_SKIP_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_CONTEXT_STATUS", REG_MMIO, 0x3791, &mmSDMA1_RLC1_CONTEXT_STATUS[0], sizeof(mmSDMA1_RLC1_CONTEXT_STATUS)/sizeof(mmSDMA1_RLC1_CONTEXT_STATUS[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DOORBELL", REG_MMIO, 0x3792, &mmSDMA1_RLC1_DOORBELL[0], sizeof(mmSDMA1_RLC1_DOORBELL)/sizeof(mmSDMA1_RLC1_DOORBELL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_VIRTUAL_ADDR", REG_MMIO, 0x37a7, &mmSDMA1_RLC1_VIRTUAL_ADDR[0], sizeof(mmSDMA1_RLC1_VIRTUAL_ADDR)/sizeof(mmSDMA1_RLC1_VIRTUAL_ADDR[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_APE1_CNTL", REG_MMIO, 0x37a8, &mmSDMA1_RLC1_APE1_CNTL[0], sizeof(mmSDMA1_RLC1_APE1_CNTL)/sizeof(mmSDMA1_RLC1_APE1_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DOORBELL_LOG", REG_MMIO, 0x37a9, &mmSDMA1_RLC1_DOORBELL_LOG[0], sizeof(mmSDMA1_RLC1_DOORBELL_LOG)/sizeof(mmSDMA1_RLC1_DOORBELL_LOG[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_WATERMARK", REG_MMIO, 0x37aa, &mmSDMA1_RLC1_WATERMARK[0], sizeof(mmSDMA1_RLC1_WATERMARK)/sizeof(mmSDMA1_RLC1_WATERMARK[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_CSA_ADDR_LO", REG_MMIO, 0x37ac, &mmSDMA1_RLC1_CSA_ADDR_LO[0], sizeof(mmSDMA1_RLC1_CSA_ADDR_LO)/sizeof(mmSDMA1_RLC1_CSA_ADDR_LO[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_CSA_ADDR_HI", REG_MMIO, 0x37ad, &mmSDMA1_RLC1_CSA_ADDR_HI[0], sizeof(mmSDMA1_RLC1_CSA_ADDR_HI)/sizeof(mmSDMA1_RLC1_CSA_ADDR_HI[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_IB_SUB_REMAIN", REG_MMIO, 0x37af, &mmSDMA1_RLC1_IB_SUB_REMAIN[0], sizeof(mmSDMA1_RLC1_IB_SUB_REMAIN)/sizeof(mmSDMA1_RLC1_IB_SUB_REMAIN[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_PREEMPT", REG_MMIO, 0x37b0, &mmSDMA1_RLC1_PREEMPT[0], sizeof(mmSDMA1_RLC1_PREEMPT)/sizeof(mmSDMA1_RLC1_PREEMPT[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_DUMMY_REG", REG_MMIO, 0x37b1, &mmSDMA1_RLC1_DUMMY_REG[0], sizeof(mmSDMA1_RLC1_DUMMY_REG)/sizeof(mmSDMA1_RLC1_DUMMY_REG[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA0", REG_MMIO, 0x37c1, &mmSDMA1_RLC1_MIDCMD_DATA0[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA0)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA0[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA1", REG_MMIO, 0x37c2, &mmSDMA1_RLC1_MIDCMD_DATA1[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA1)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA1[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA2", REG_MMIO, 0x37c3, &mmSDMA1_RLC1_MIDCMD_DATA2[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA2)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA2[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA3", REG_MMIO, 0x37c4, &mmSDMA1_RLC1_MIDCMD_DATA3[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA3)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA3[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA4", REG_MMIO, 0x37c5, &mmSDMA1_RLC1_MIDCMD_DATA4[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA4)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA4[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_DATA5", REG_MMIO, 0x37c6, &mmSDMA1_RLC1_MIDCMD_DATA5[0], sizeof(mmSDMA1_RLC1_MIDCMD_DATA5)/sizeof(mmSDMA1_RLC1_MIDCMD_DATA5[0]), 0, 0 },
+	{ "mmSDMA1_RLC1_MIDCMD_CNTL", REG_MMIO, 0x37c7, &mmSDMA1_RLC1_MIDCMD_CNTL[0], sizeof(mmSDMA1_RLC1_MIDCMD_CNTL)/sizeof(mmSDMA1_RLC1_MIDCMD_CNTL[0]), 0, 0 },
+	{ "ixEXP1", REG_SMC, 0x38, &ixEXP1[0], sizeof(ixEXP1)/sizeof(ixEXP1[0]), 0, 0 },
+	{ "mmSRBM_CNTL", REG_MMIO, 0x390, &mmSRBM_CNTL[0], sizeof(mmSRBM_CNTL)/sizeof(mmSRBM_CNTL[0]), 0, 0 },
+	{ "mmSRBM_GFX_CNTL", REG_MMIO, 0x391, &mmSRBM_GFX_CNTL[0], sizeof(mmSRBM_GFX_CNTL)/sizeof(mmSRBM_GFX_CNTL[0]), 0, 0 },
+	{ "mmSRBM_READ_CNTL", REG_MMIO, 0x392, &mmSRBM_READ_CNTL[0], sizeof(mmSRBM_READ_CNTL)/sizeof(mmSRBM_READ_CNTL[0]), 0, 0 },
+	{ "mmSRBM_STATUS2", REG_MMIO, 0x393, &mmSRBM_STATUS2[0], sizeof(mmSRBM_STATUS2)/sizeof(mmSRBM_STATUS2[0]), 0, 0 },
+	{ "mmSRBM_STATUS", REG_MMIO, 0x394, &mmSRBM_STATUS[0], sizeof(mmSRBM_STATUS)/sizeof(mmSRBM_STATUS[0]), 0, 0 },
+	{ "mmSRBM_STATUS3", REG_MMIO, 0x395, &mmSRBM_STATUS3[0], sizeof(mmSRBM_STATUS3)/sizeof(mmSRBM_STATUS3[0]), 0, 0 },
+	{ "mmSRBM_SOFT_RESET", REG_MMIO, 0x398, &mmSRBM_SOFT_RESET[0], sizeof(mmSRBM_SOFT_RESET)/sizeof(mmSRBM_SOFT_RESET[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_CNTL", REG_MMIO, 0x399, &mmSRBM_DEBUG_CNTL[0], sizeof(mmSRBM_DEBUG_CNTL)/sizeof(mmSRBM_DEBUG_CNTL[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_DATA", REG_MMIO, 0x39a, &mmSRBM_DEBUG_DATA[0], sizeof(mmSRBM_DEBUG_DATA)/sizeof(mmSRBM_DEBUG_DATA[0]), 0, 0 },
+	{ "mmSRBM_CHIP_REVISION", REG_MMIO, 0x39b, &mmSRBM_CHIP_REVISION[0], sizeof(mmSRBM_CHIP_REVISION)/sizeof(mmSRBM_CHIP_REVISION[0]), 0, 0 },
+	{ "mmSRBM_CREDIT_RECOVER_CNTL", REG_MMIO, 0x39c, &mmSRBM_CREDIT_RECOVER_CNTL[0], sizeof(mmSRBM_CREDIT_RECOVER_CNTL)/sizeof(mmSRBM_CREDIT_RECOVER_CNTL[0]), 0, 0 },
+	{ "mmSRBM_CREDIT_RECOVER", REG_MMIO, 0x39d, &mmSRBM_CREDIT_RECOVER[0], sizeof(mmSRBM_CREDIT_RECOVER)/sizeof(mmSRBM_CREDIT_RECOVER[0]), 0, 0 },
+	{ "mmSRBM_CREDIT_RESET", REG_MMIO, 0x39e, &mmSRBM_CREDIT_RESET[0], sizeof(mmSRBM_CREDIT_RESET)/sizeof(mmSRBM_CREDIT_RESET[0]), 0, 0 },
+	{ "mmCC_SYS_RB_REDUNDANCY", REG_MMIO, 0x39f, &mmCC_SYS_RB_REDUNDANCY[0], sizeof(mmCC_SYS_RB_REDUNDANCY)/sizeof(mmCC_SYS_RB_REDUNDANCY[0]), 0, 0 },
+	{ "mmCC_SYS_RB_BACKEND_DISABLE", REG_MMIO, 0x3a0, &mmCC_SYS_RB_BACKEND_DISABLE[0], sizeof(mmCC_SYS_RB_BACKEND_DISABLE)/sizeof(mmCC_SYS_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmGC_USER_SYS_RB_BACKEND_DISABLE", REG_MMIO, 0x3a1, &mmGC_USER_SYS_RB_BACKEND_DISABLE[0], sizeof(mmGC_USER_SYS_RB_BACKEND_DISABLE)/sizeof(mmGC_USER_SYS_RB_BACKEND_DISABLE[0]), 0, 0 },
+	{ "mmSRBM_DEBUG", REG_MMIO, 0x3a4, &mmSRBM_DEBUG[0], sizeof(mmSRBM_DEBUG)/sizeof(mmSRBM_DEBUG[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_SNAPSHOT", REG_MMIO, 0x3a5, &mmSRBM_DEBUG_SNAPSHOT[0], sizeof(mmSRBM_DEBUG_SNAPSHOT)/sizeof(mmSRBM_DEBUG_SNAPSHOT[0]), 0, 0 },
+	{ "mmSRBM_READ_ERROR", REG_MMIO, 0x3a6, &mmSRBM_READ_ERROR[0], sizeof(mmSRBM_READ_ERROR)/sizeof(mmSRBM_READ_ERROR[0]), 0, 0 },
+	{ "mmSRBM_INT_CNTL", REG_MMIO, 0x3a8, &mmSRBM_INT_CNTL[0], sizeof(mmSRBM_INT_CNTL)/sizeof(mmSRBM_INT_CNTL[0]), 0, 0 },
+	{ "mmSRBM_INT_STATUS", REG_MMIO, 0x3a9, &mmSRBM_INT_STATUS[0], sizeof(mmSRBM_INT_STATUS)/sizeof(mmSRBM_INT_STATUS[0]), 0, 0 },
+	{ "mmSRBM_INT_ACK", REG_MMIO, 0x3aa, &mmSRBM_INT_ACK[0], sizeof(mmSRBM_INT_ACK)/sizeof(mmSRBM_INT_ACK[0]), 0, 0 },
+	{ "mmSRBM_FIREWALL_ERROR_SRC", REG_MMIO, 0x3ab, &mmSRBM_FIREWALL_ERROR_SRC[0], sizeof(mmSRBM_FIREWALL_ERROR_SRC)/sizeof(mmSRBM_FIREWALL_ERROR_SRC[0]), 0, 0 },
+	{ "mmSRBM_FIREWALL_ERROR_ADDR", REG_MMIO, 0x3ac, &mmSRBM_FIREWALL_ERROR_ADDR[0], sizeof(mmSRBM_FIREWALL_ERROR_ADDR)/sizeof(mmSRBM_FIREWALL_ERROR_ADDR[0]), 0, 0 },
+	{ "mmSRBM_DEBUG_SNAPSHOT2", REG_MMIO, 0x3ad, &mmSRBM_DEBUG_SNAPSHOT2[0], sizeof(mmSRBM_DEBUG_SNAPSHOT2)/sizeof(mmSRBM_DEBUG_SNAPSHOT2[0]), 0, 0 },
+	{ "mmSRBM_READ_ERROR2", REG_MMIO, 0x3ae, &mmSRBM_READ_ERROR2[0], sizeof(mmSRBM_READ_ERROR2)/sizeof(mmSRBM_READ_ERROR2[0]), 0, 0 },
+	{ "mmSRBM_DSM_TRIG_CNTL0", REG_MMIO, 0x3af, &mmSRBM_DSM_TRIG_CNTL0[0], sizeof(mmSRBM_DSM_TRIG_CNTL0)/sizeof(mmSRBM_DSM_TRIG_CNTL0[0]), 0, 0 },
+	{ "mmSRBM_DSM_TRIG_CNTL1", REG_MMIO, 0x3b0, &mmSRBM_DSM_TRIG_CNTL1[0], sizeof(mmSRBM_DSM_TRIG_CNTL1)/sizeof(mmSRBM_DSM_TRIG_CNTL1[0]), 0, 0 },
+	{ "mmSRBM_DSM_TRIG_MASK0", REG_MMIO, 0x3b1, &mmSRBM_DSM_TRIG_MASK0[0], sizeof(mmSRBM_DSM_TRIG_MASK0)/sizeof(mmSRBM_DSM_TRIG_MASK0[0]), 0, 0 },
+	{ "mmSRBM_DSM_TRIG_MASK1", REG_MMIO, 0x3b2, &mmSRBM_DSM_TRIG_MASK1[0], sizeof(mmSRBM_DSM_TRIG_MASK1)/sizeof(mmSRBM_DSM_TRIG_MASK1[0]), 0, 0 },
+	{ "mmSRBM_MC_CLKEN_CNTL", REG_MMIO, 0x3b3, &mmSRBM_MC_CLKEN_CNTL[0], sizeof(mmSRBM_MC_CLKEN_CNTL)/sizeof(mmSRBM_MC_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_SYS_CLKEN_CNTL", REG_MMIO, 0x3b4, &mmSRBM_SYS_CLKEN_CNTL[0], sizeof(mmSRBM_SYS_CLKEN_CNTL)/sizeof(mmSRBM_SYS_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_VCE_CLKEN_CNTL", REG_MMIO, 0x3b5, &mmSRBM_VCE_CLKEN_CNTL[0], sizeof(mmSRBM_VCE_CLKEN_CNTL)/sizeof(mmSRBM_VCE_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_UVD_CLKEN_CNTL", REG_MMIO, 0x3b6, &mmSRBM_UVD_CLKEN_CNTL[0], sizeof(mmSRBM_UVD_CLKEN_CNTL)/sizeof(mmSRBM_UVD_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_SDMA_CLKEN_CNTL", REG_MMIO, 0x3b7, &mmSRBM_SDMA_CLKEN_CNTL[0], sizeof(mmSRBM_SDMA_CLKEN_CNTL)/sizeof(mmSRBM_SDMA_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_SAM_CLKEN_CNTL", REG_MMIO, 0x3b8, &mmSRBM_SAM_CLKEN_CNTL[0], sizeof(mmSRBM_SAM_CLKEN_CNTL)/sizeof(mmSRBM_SAM_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_ISP_CLKEN_CNTL", REG_MMIO, 0x3b9, &mmSRBM_ISP_CLKEN_CNTL[0], sizeof(mmSRBM_ISP_CLKEN_CNTL)/sizeof(mmSRBM_ISP_CLKEN_CNTL[0]), 0, 0 },
+	{ "mmSRBM_VP8_CLKEN_CNTL", REG_MMIO, 0x3ba, &mmSRBM_VP8_CLKEN_CNTL[0], sizeof(mmSRBM_VP8_CLKEN_CNTL)/sizeof(mmSRBM_VP8_CLKEN_CNTL[0]), 0, 0 },
+	{ "ixEXP2", REG_SMC, 0x3c, &ixEXP2[0], sizeof(ixEXP2)/sizeof(ixEXP2[0]), 0, 0 },
+	{ "ixKHFS0", REG_SMC, 0x4, &ixKHFS0[0], sizeof(ixKHFS0)/sizeof(ixKHFS0[0]), 0, 0 },
+	{ "ixEXP3", REG_SMC, 0x40, &ixEXP3[0], sizeof(ixEXP3)/sizeof(ixEXP3[0]), 0, 0 },
+	{ "ixEXP4", REG_SMC, 0x44, &ixEXP4[0], sizeof(ixEXP4)/sizeof(ixEXP4[0]), 0, 0 },
+	{ "ixEXP5", REG_SMC, 0x48, &ixEXP5[0], sizeof(ixEXP5)/sizeof(ixEXP5[0]), 0, 0 },
+	{ "ixEXP6", REG_SMC, 0x4c, &ixEXP6[0], sizeof(ixEXP6)/sizeof(ixEXP6[0]), 0, 0 },
+	{ "ixEXP7", REG_SMC, 0x50, &ixEXP7[0], sizeof(ixEXP7)/sizeof(ixEXP7[0]), 0, 0 },
+	{ "ixLX0", REG_SMC, 0x54, &ixLX0[0], sizeof(ixLX0)/sizeof(ixLX0[0]), 0, 0 },
+	{ "ixLX1", REG_SMC, 0x58, &ixLX1[0], sizeof(ixLX1)/sizeof(ixLX1[0]), 0, 0 },
+	{ "ixLX2", REG_SMC, 0x5c, &ixLX2[0], sizeof(ixLX2)/sizeof(ixLX2[0]), 0, 0 },
+	{ "ixLX3", REG_SMC, 0x60, &ixLX3[0], sizeof(ixLX3)/sizeof(ixLX3[0]), 0, 0 },
+	{ "mmSRBM_PERFMON_CNTL", REG_MMIO, 0x7c00, &mmSRBM_PERFMON_CNTL[0], sizeof(mmSRBM_PERFMON_CNTL)/sizeof(mmSRBM_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_SELECT", REG_MMIO, 0x7c01, &mmSRBM_PERFCOUNTER0_SELECT[0], sizeof(mmSRBM_PERFCOUNTER0_SELECT)/sizeof(mmSRBM_PERFCOUNTER0_SELECT[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_SELECT", REG_MMIO, 0x7c02, &mmSRBM_PERFCOUNTER1_SELECT[0], sizeof(mmSRBM_PERFCOUNTER1_SELECT)/sizeof(mmSRBM_PERFCOUNTER1_SELECT[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_LO", REG_MMIO, 0x7c03, &mmSRBM_PERFCOUNTER0_LO[0], sizeof(mmSRBM_PERFCOUNTER0_LO)/sizeof(mmSRBM_PERFCOUNTER0_LO[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER0_HI", REG_MMIO, 0x7c04, &mmSRBM_PERFCOUNTER0_HI[0], sizeof(mmSRBM_PERFCOUNTER0_HI)/sizeof(mmSRBM_PERFCOUNTER0_HI[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_LO", REG_MMIO, 0x7c05, &mmSRBM_PERFCOUNTER1_LO[0], sizeof(mmSRBM_PERFCOUNTER1_LO)/sizeof(mmSRBM_PERFCOUNTER1_LO[0]), 0, 0 },
+	{ "mmSRBM_PERFCOUNTER1_HI", REG_MMIO, 0x7c06, &mmSRBM_PERFCOUNTER1_HI[0], sizeof(mmSRBM_PERFCOUNTER1_HI)/sizeof(mmSRBM_PERFCOUNTER1_HI[0]), 0, 0 },
+	{ "ixKHFS1", REG_SMC, 0x8, &ixKHFS1[0], sizeof(ixKHFS1)/sizeof(ixKHFS1[0]), 0, 0 },
+	{ "mmSDMA0_PERFMON_CNTL", REG_MMIO, 0x9000, &mmSDMA0_PERFMON_CNTL[0], sizeof(mmSDMA0_PERFMON_CNTL)/sizeof(mmSDMA0_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSDMA0_PERFCOUNTER0_RESULT", REG_MMIO, 0x9001, &mmSDMA0_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER0_RESULT)/sizeof(mmSDMA0_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmSDMA0_PERFCOUNTER1_RESULT", REG_MMIO, 0x9002, &mmSDMA0_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA0_PERFCOUNTER1_RESULT)/sizeof(mmSDMA0_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmSDMA1_PERFMON_CNTL", REG_MMIO, 0x9010, &mmSDMA1_PERFMON_CNTL[0], sizeof(mmSDMA1_PERFMON_CNTL)/sizeof(mmSDMA1_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmSDMA1_PERFCOUNTER0_RESULT", REG_MMIO, 0x9011, &mmSDMA1_PERFCOUNTER0_RESULT[0], sizeof(mmSDMA1_PERFCOUNTER0_RESULT)/sizeof(mmSDMA1_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmSDMA1_PERFCOUNTER1_RESULT", REG_MMIO, 0x9012, &mmSDMA1_PERFCOUNTER1_RESULT[0], sizeof(mmSDMA1_PERFCOUNTER1_RESULT)/sizeof(mmSDMA1_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmHDP_HOST_PATH_CNTL", REG_MMIO, 0xb00, &mmHDP_HOST_PATH_CNTL[0], sizeof(mmHDP_HOST_PATH_CNTL)/sizeof(mmHDP_HOST_PATH_CNTL[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_BASE", REG_MMIO, 0xb01, &mmHDP_NONSURFACE_BASE[0], sizeof(mmHDP_NONSURFACE_BASE)/sizeof(mmHDP_NONSURFACE_BASE[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_INFO", REG_MMIO, 0xb02, &mmHDP_NONSURFACE_INFO[0], sizeof(mmHDP_NONSURFACE_INFO)/sizeof(mmHDP_NONSURFACE_INFO[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_SIZE", REG_MMIO, 0xb03, &mmHDP_NONSURFACE_SIZE[0], sizeof(mmHDP_NONSURFACE_SIZE)/sizeof(mmHDP_NONSURFACE_SIZE[0]), 0, 0 },
+	{ "mmHDP_NONSURF_FLAGS", REG_MMIO, 0xbc9, &mmHDP_NONSURF_FLAGS[0], sizeof(mmHDP_NONSURF_FLAGS)/sizeof(mmHDP_NONSURF_FLAGS[0]), 0, 0 },
+	{ "mmHDP_NONSURF_FLAGS_CLR", REG_MMIO, 0xbca, &mmHDP_NONSURF_FLAGS_CLR[0], sizeof(mmHDP_NONSURF_FLAGS_CLR)/sizeof(mmHDP_NONSURF_FLAGS_CLR[0]), 0, 0 },
+	{ "mmHDP_SW_SEMAPHORE", REG_MMIO, 0xbcb, &mmHDP_SW_SEMAPHORE[0], sizeof(mmHDP_SW_SEMAPHORE)/sizeof(mmHDP_SW_SEMAPHORE[0]), 0, 0 },
+	{ "mmHDP_DEBUG0", REG_MMIO, 0xbcc, &mmHDP_DEBUG0[0], sizeof(mmHDP_DEBUG0)/sizeof(mmHDP_DEBUG0[0]), 0, 0 },
+	{ "mmHDP_DEBUG1", REG_MMIO, 0xbcd, &mmHDP_DEBUG1[0], sizeof(mmHDP_DEBUG1)/sizeof(mmHDP_DEBUG1[0]), 0, 0 },
+	{ "mmHDP_LAST_SURFACE_HIT", REG_MMIO, 0xbce, &mmHDP_LAST_SURFACE_HIT[0], sizeof(mmHDP_LAST_SURFACE_HIT)/sizeof(mmHDP_LAST_SURFACE_HIT[0]), 0, 0 },
+	{ "mmHDP_TILING_CONFIG", REG_MMIO, 0xbcf, &mmHDP_TILING_CONFIG[0], sizeof(mmHDP_TILING_CONFIG)/sizeof(mmHDP_TILING_CONFIG[0]), 0, 0 },
+	{ "mmHDP_SC_MULTI_CHIP_CNTL", REG_MMIO, 0xbd0, &mmHDP_SC_MULTI_CHIP_CNTL[0], sizeof(mmHDP_SC_MULTI_CHIP_CNTL)/sizeof(mmHDP_SC_MULTI_CHIP_CNTL[0]), 0, 0 },
+	{ "mmHDP_OUTSTANDING_REQ", REG_MMIO, 0xbd1, &mmHDP_OUTSTANDING_REQ[0], sizeof(mmHDP_OUTSTANDING_REQ)/sizeof(mmHDP_OUTSTANDING_REQ[0]), 0, 0 },
+	{ "mmHDP_ADDR_CONFIG", REG_MMIO, 0xbd2, &mmHDP_ADDR_CONFIG[0], sizeof(mmHDP_ADDR_CONFIG)/sizeof(mmHDP_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmHDP_MISC_CNTL", REG_MMIO, 0xbd3, &mmHDP_MISC_CNTL[0], sizeof(mmHDP_MISC_CNTL)/sizeof(mmHDP_MISC_CNTL[0]), 0, 0 },
+	{ "mmHDP_MEM_POWER_LS", REG_MMIO, 0xbd4, &mmHDP_MEM_POWER_LS[0], sizeof(mmHDP_MEM_POWER_LS)/sizeof(mmHDP_MEM_POWER_LS[0]), 0, 0 },
+	{ "mmHDP_NONSURFACE_PREFETCH", REG_MMIO, 0xbd5, &mmHDP_NONSURFACE_PREFETCH[0], sizeof(mmHDP_NONSURFACE_PREFETCH)/sizeof(mmHDP_NONSURFACE_PREFETCH[0]), 0, 0 },
+	{ "mmHDP_MEMIO_CNTL", REG_MMIO, 0xbf6, &mmHDP_MEMIO_CNTL[0], sizeof(mmHDP_MEMIO_CNTL)/sizeof(mmHDP_MEMIO_CNTL[0]), 0, 0 },
+	{ "mmHDP_MEMIO_ADDR", REG_MMIO, 0xbf7, &mmHDP_MEMIO_ADDR[0], sizeof(mmHDP_MEMIO_ADDR)/sizeof(mmHDP_MEMIO_ADDR[0]), 0, 0 },
+	{ "mmHDP_MEMIO_STATUS", REG_MMIO, 0xbf8, &mmHDP_MEMIO_STATUS[0], sizeof(mmHDP_MEMIO_STATUS)/sizeof(mmHDP_MEMIO_STATUS[0]), 0, 0 },
+	{ "mmHDP_MEMIO_WR_DATA", REG_MMIO, 0xbf9, &mmHDP_MEMIO_WR_DATA[0], sizeof(mmHDP_MEMIO_WR_DATA)/sizeof(mmHDP_MEMIO_WR_DATA[0]), 0, 0 },
+	{ "mmHDP_MEMIO_RD_DATA", REG_MMIO, 0xbfa, &mmHDP_MEMIO_RD_DATA[0], sizeof(mmHDP_MEMIO_RD_DATA)/sizeof(mmHDP_MEMIO_RD_DATA[0]), 0, 0 },
+	{ "mmHDP_VF_ENABLE", REG_MMIO, 0xbfb, &mmHDP_VF_ENABLE[0], sizeof(mmHDP_VF_ENABLE)/sizeof(mmHDP_VF_ENABLE[0]), 0, 0 },
+	{ "ixKHFS2", REG_SMC, 0xc, &ixKHFS2[0], sizeof(ixKHFS2)/sizeof(ixKHFS2[0]), 0, 0 },
+	{ "mmHDP_XDP_DIRECT2HDP_FIRST", REG_MMIO, 0xc00, &mmHDP_XDP_DIRECT2HDP_FIRST[0], sizeof(mmHDP_XDP_DIRECT2HDP_FIRST)/sizeof(mmHDP_XDP_DIRECT2HDP_FIRST[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_FLUSH", REG_MMIO, 0xc01, &mmHDP_XDP_D2H_FLUSH[0], sizeof(mmHDP_XDP_D2H_FLUSH)/sizeof(mmHDP_XDP_D2H_FLUSH[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_BAR_UPDATE", REG_MMIO, 0xc02, &mmHDP_XDP_D2H_BAR_UPDATE[0], sizeof(mmHDP_XDP_D2H_BAR_UPDATE)/sizeof(mmHDP_XDP_D2H_BAR_UPDATE[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_3", REG_MMIO, 0xc03, &mmHDP_XDP_D2H_RSVD_3[0], sizeof(mmHDP_XDP_D2H_RSVD_3)/sizeof(mmHDP_XDP_D2H_RSVD_3[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_4", REG_MMIO, 0xc04, &mmHDP_XDP_D2H_RSVD_4[0], sizeof(mmHDP_XDP_D2H_RSVD_4)/sizeof(mmHDP_XDP_D2H_RSVD_4[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_5", REG_MMIO, 0xc05, &mmHDP_XDP_D2H_RSVD_5[0], sizeof(mmHDP_XDP_D2H_RSVD_5)/sizeof(mmHDP_XDP_D2H_RSVD_5[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_6", REG_MMIO, 0xc06, &mmHDP_XDP_D2H_RSVD_6[0], sizeof(mmHDP_XDP_D2H_RSVD_6)/sizeof(mmHDP_XDP_D2H_RSVD_6[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_7", REG_MMIO, 0xc07, &mmHDP_XDP_D2H_RSVD_7[0], sizeof(mmHDP_XDP_D2H_RSVD_7)/sizeof(mmHDP_XDP_D2H_RSVD_7[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_8", REG_MMIO, 0xc08, &mmHDP_XDP_D2H_RSVD_8[0], sizeof(mmHDP_XDP_D2H_RSVD_8)/sizeof(mmHDP_XDP_D2H_RSVD_8[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_9", REG_MMIO, 0xc09, &mmHDP_XDP_D2H_RSVD_9[0], sizeof(mmHDP_XDP_D2H_RSVD_9)/sizeof(mmHDP_XDP_D2H_RSVD_9[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_10", REG_MMIO, 0xc0a, &mmHDP_XDP_D2H_RSVD_10[0], sizeof(mmHDP_XDP_D2H_RSVD_10)/sizeof(mmHDP_XDP_D2H_RSVD_10[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_11", REG_MMIO, 0xc0b, &mmHDP_XDP_D2H_RSVD_11[0], sizeof(mmHDP_XDP_D2H_RSVD_11)/sizeof(mmHDP_XDP_D2H_RSVD_11[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_12", REG_MMIO, 0xc0c, &mmHDP_XDP_D2H_RSVD_12[0], sizeof(mmHDP_XDP_D2H_RSVD_12)/sizeof(mmHDP_XDP_D2H_RSVD_12[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_13", REG_MMIO, 0xc0d, &mmHDP_XDP_D2H_RSVD_13[0], sizeof(mmHDP_XDP_D2H_RSVD_13)/sizeof(mmHDP_XDP_D2H_RSVD_13[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_14", REG_MMIO, 0xc0e, &mmHDP_XDP_D2H_RSVD_14[0], sizeof(mmHDP_XDP_D2H_RSVD_14)/sizeof(mmHDP_XDP_D2H_RSVD_14[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_15", REG_MMIO, 0xc0f, &mmHDP_XDP_D2H_RSVD_15[0], sizeof(mmHDP_XDP_D2H_RSVD_15)/sizeof(mmHDP_XDP_D2H_RSVD_15[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_16", REG_MMIO, 0xc10, &mmHDP_XDP_D2H_RSVD_16[0], sizeof(mmHDP_XDP_D2H_RSVD_16)/sizeof(mmHDP_XDP_D2H_RSVD_16[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_17", REG_MMIO, 0xc11, &mmHDP_XDP_D2H_RSVD_17[0], sizeof(mmHDP_XDP_D2H_RSVD_17)/sizeof(mmHDP_XDP_D2H_RSVD_17[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_18", REG_MMIO, 0xc12, &mmHDP_XDP_D2H_RSVD_18[0], sizeof(mmHDP_XDP_D2H_RSVD_18)/sizeof(mmHDP_XDP_D2H_RSVD_18[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_19", REG_MMIO, 0xc13, &mmHDP_XDP_D2H_RSVD_19[0], sizeof(mmHDP_XDP_D2H_RSVD_19)/sizeof(mmHDP_XDP_D2H_RSVD_19[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_20", REG_MMIO, 0xc14, &mmHDP_XDP_D2H_RSVD_20[0], sizeof(mmHDP_XDP_D2H_RSVD_20)/sizeof(mmHDP_XDP_D2H_RSVD_20[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_21", REG_MMIO, 0xc15, &mmHDP_XDP_D2H_RSVD_21[0], sizeof(mmHDP_XDP_D2H_RSVD_21)/sizeof(mmHDP_XDP_D2H_RSVD_21[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_22", REG_MMIO, 0xc16, &mmHDP_XDP_D2H_RSVD_22[0], sizeof(mmHDP_XDP_D2H_RSVD_22)/sizeof(mmHDP_XDP_D2H_RSVD_22[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_23", REG_MMIO, 0xc17, &mmHDP_XDP_D2H_RSVD_23[0], sizeof(mmHDP_XDP_D2H_RSVD_23)/sizeof(mmHDP_XDP_D2H_RSVD_23[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_24", REG_MMIO, 0xc18, &mmHDP_XDP_D2H_RSVD_24[0], sizeof(mmHDP_XDP_D2H_RSVD_24)/sizeof(mmHDP_XDP_D2H_RSVD_24[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_25", REG_MMIO, 0xc19, &mmHDP_XDP_D2H_RSVD_25[0], sizeof(mmHDP_XDP_D2H_RSVD_25)/sizeof(mmHDP_XDP_D2H_RSVD_25[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_26", REG_MMIO, 0xc1a, &mmHDP_XDP_D2H_RSVD_26[0], sizeof(mmHDP_XDP_D2H_RSVD_26)/sizeof(mmHDP_XDP_D2H_RSVD_26[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_27", REG_MMIO, 0xc1b, &mmHDP_XDP_D2H_RSVD_27[0], sizeof(mmHDP_XDP_D2H_RSVD_27)/sizeof(mmHDP_XDP_D2H_RSVD_27[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_28", REG_MMIO, 0xc1c, &mmHDP_XDP_D2H_RSVD_28[0], sizeof(mmHDP_XDP_D2H_RSVD_28)/sizeof(mmHDP_XDP_D2H_RSVD_28[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_29", REG_MMIO, 0xc1d, &mmHDP_XDP_D2H_RSVD_29[0], sizeof(mmHDP_XDP_D2H_RSVD_29)/sizeof(mmHDP_XDP_D2H_RSVD_29[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_30", REG_MMIO, 0xc1e, &mmHDP_XDP_D2H_RSVD_30[0], sizeof(mmHDP_XDP_D2H_RSVD_30)/sizeof(mmHDP_XDP_D2H_RSVD_30[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_31", REG_MMIO, 0xc1f, &mmHDP_XDP_D2H_RSVD_31[0], sizeof(mmHDP_XDP_D2H_RSVD_31)/sizeof(mmHDP_XDP_D2H_RSVD_31[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_32", REG_MMIO, 0xc20, &mmHDP_XDP_D2H_RSVD_32[0], sizeof(mmHDP_XDP_D2H_RSVD_32)/sizeof(mmHDP_XDP_D2H_RSVD_32[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_33", REG_MMIO, 0xc21, &mmHDP_XDP_D2H_RSVD_33[0], sizeof(mmHDP_XDP_D2H_RSVD_33)/sizeof(mmHDP_XDP_D2H_RSVD_33[0]), 0, 0 },
+	{ "mmHDP_XDP_D2H_RSVD_34", REG_MMIO, 0xc22, &mmHDP_XDP_D2H_RSVD_34[0], sizeof(mmHDP_XDP_D2H_RSVD_34)/sizeof(mmHDP_XDP_D2H_RSVD_34[0]), 0, 0 },
+	{ "mmHDP_XDP_DIRECT2HDP_LAST", REG_MMIO, 0xc23, &mmHDP_XDP_DIRECT2HDP_LAST[0], sizeof(mmHDP_XDP_DIRECT2HDP_LAST)/sizeof(mmHDP_XDP_DIRECT2HDP_LAST[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR_CFG", REG_MMIO, 0xc24, &mmHDP_XDP_P2P_BAR_CFG[0], sizeof(mmHDP_XDP_P2P_BAR_CFG)/sizeof(mmHDP_XDP_P2P_BAR_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_OFFSET", REG_MMIO, 0xc25, &mmHDP_XDP_P2P_MBX_OFFSET[0], sizeof(mmHDP_XDP_P2P_MBX_OFFSET)/sizeof(mmHDP_XDP_P2P_MBX_OFFSET[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR0", REG_MMIO, 0xc26, &mmHDP_XDP_P2P_MBX_ADDR0[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR0)/sizeof(mmHDP_XDP_P2P_MBX_ADDR0[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR1", REG_MMIO, 0xc27, &mmHDP_XDP_P2P_MBX_ADDR1[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR1)/sizeof(mmHDP_XDP_P2P_MBX_ADDR1[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR2", REG_MMIO, 0xc28, &mmHDP_XDP_P2P_MBX_ADDR2[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR2)/sizeof(mmHDP_XDP_P2P_MBX_ADDR2[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR3", REG_MMIO, 0xc29, &mmHDP_XDP_P2P_MBX_ADDR3[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR3)/sizeof(mmHDP_XDP_P2P_MBX_ADDR3[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR4", REG_MMIO, 0xc2a, &mmHDP_XDP_P2P_MBX_ADDR4[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR4)/sizeof(mmHDP_XDP_P2P_MBX_ADDR4[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR5", REG_MMIO, 0xc2b, &mmHDP_XDP_P2P_MBX_ADDR5[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR5)/sizeof(mmHDP_XDP_P2P_MBX_ADDR5[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_MBX_ADDR6", REG_MMIO, 0xc2c, &mmHDP_XDP_P2P_MBX_ADDR6[0], sizeof(mmHDP_XDP_P2P_MBX_ADDR6)/sizeof(mmHDP_XDP_P2P_MBX_ADDR6[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_MBX_MC_CFG", REG_MMIO, 0xc2d, &mmHDP_XDP_HDP_MBX_MC_CFG[0], sizeof(mmHDP_XDP_HDP_MBX_MC_CFG)/sizeof(mmHDP_XDP_HDP_MBX_MC_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_MC_CFG", REG_MMIO, 0xc2e, &mmHDP_XDP_HDP_MC_CFG[0], sizeof(mmHDP_XDP_HDP_MC_CFG)/sizeof(mmHDP_XDP_HDP_MC_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HST_CFG", REG_MMIO, 0xc2f, &mmHDP_XDP_HST_CFG[0], sizeof(mmHDP_XDP_HST_CFG)/sizeof(mmHDP_XDP_HST_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_SID_CFG", REG_MMIO, 0xc30, &mmHDP_XDP_SID_CFG[0], sizeof(mmHDP_XDP_SID_CFG)/sizeof(mmHDP_XDP_SID_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_HDP_IPH_CFG", REG_MMIO, 0xc31, &mmHDP_XDP_HDP_IPH_CFG[0], sizeof(mmHDP_XDP_HDP_IPH_CFG)/sizeof(mmHDP_XDP_HDP_IPH_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_SRBM_CFG", REG_MMIO, 0xc32, &mmHDP_XDP_SRBM_CFG[0], sizeof(mmHDP_XDP_SRBM_CFG)/sizeof(mmHDP_XDP_SRBM_CFG[0]), 0, 0 },
+	{ "mmHDP_XDP_CGTT_BLK_CTRL", REG_MMIO, 0xc33, &mmHDP_XDP_CGTT_BLK_CTRL[0], sizeof(mmHDP_XDP_CGTT_BLK_CTRL)/sizeof(mmHDP_XDP_CGTT_BLK_CTRL[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR0", REG_MMIO, 0xc34, &mmHDP_XDP_P2P_BAR0[0], sizeof(mmHDP_XDP_P2P_BAR0)/sizeof(mmHDP_XDP_P2P_BAR0[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR1", REG_MMIO, 0xc35, &mmHDP_XDP_P2P_BAR1[0], sizeof(mmHDP_XDP_P2P_BAR1)/sizeof(mmHDP_XDP_P2P_BAR1[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR2", REG_MMIO, 0xc36, &mmHDP_XDP_P2P_BAR2[0], sizeof(mmHDP_XDP_P2P_BAR2)/sizeof(mmHDP_XDP_P2P_BAR2[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR3", REG_MMIO, 0xc37, &mmHDP_XDP_P2P_BAR3[0], sizeof(mmHDP_XDP_P2P_BAR3)/sizeof(mmHDP_XDP_P2P_BAR3[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR4", REG_MMIO, 0xc38, &mmHDP_XDP_P2P_BAR4[0], sizeof(mmHDP_XDP_P2P_BAR4)/sizeof(mmHDP_XDP_P2P_BAR4[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR5", REG_MMIO, 0xc39, &mmHDP_XDP_P2P_BAR5[0], sizeof(mmHDP_XDP_P2P_BAR5)/sizeof(mmHDP_XDP_P2P_BAR5[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR6", REG_MMIO, 0xc3a, &mmHDP_XDP_P2P_BAR6[0], sizeof(mmHDP_XDP_P2P_BAR6)/sizeof(mmHDP_XDP_P2P_BAR6[0]), 0, 0 },
+	{ "mmHDP_XDP_P2P_BAR7", REG_MMIO, 0xc3b, &mmHDP_XDP_P2P_BAR7[0], sizeof(mmHDP_XDP_P2P_BAR7)/sizeof(mmHDP_XDP_P2P_BAR7[0]), 0, 0 },
+	{ "mmHDP_XDP_FLUSH_ARMED_STS", REG_MMIO, 0xc3c, &mmHDP_XDP_FLUSH_ARMED_STS[0], sizeof(mmHDP_XDP_FLUSH_ARMED_STS)/sizeof(mmHDP_XDP_FLUSH_ARMED_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_FLUSH_CNTR0_STS", REG_MMIO, 0xc3d, &mmHDP_XDP_FLUSH_CNTR0_STS[0], sizeof(mmHDP_XDP_FLUSH_CNTR0_STS)/sizeof(mmHDP_XDP_FLUSH_CNTR0_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_BUSY_STS", REG_MMIO, 0xc3e, &mmHDP_XDP_BUSY_STS[0], sizeof(mmHDP_XDP_BUSY_STS)/sizeof(mmHDP_XDP_BUSY_STS[0]), 0, 0 },
+	{ "mmHDP_XDP_STICKY", REG_MMIO, 0xc3f, &mmHDP_XDP_STICKY[0], sizeof(mmHDP_XDP_STICKY)/sizeof(mmHDP_XDP_STICKY[0]), 0, 0 },
+	{ "mmHDP_XDP_CHKN", REG_MMIO, 0xc40, &mmHDP_XDP_CHKN[0], sizeof(mmHDP_XDP_CHKN)/sizeof(mmHDP_XDP_CHKN[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_ADDR", REG_MMIO, 0xc41, &mmHDP_XDP_DBG_ADDR[0], sizeof(mmHDP_XDP_DBG_ADDR)/sizeof(mmHDP_XDP_DBG_ADDR[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_DATA", REG_MMIO, 0xc42, &mmHDP_XDP_DBG_DATA[0], sizeof(mmHDP_XDP_DBG_DATA)/sizeof(mmHDP_XDP_DBG_DATA[0]), 0, 0 },
+	{ "mmHDP_XDP_DBG_MASK", REG_MMIO, 0xc43, &mmHDP_XDP_DBG_MASK[0], sizeof(mmHDP_XDP_DBG_MASK)/sizeof(mmHDP_XDP_DBG_MASK[0]), 0, 0 },
+	{ "mmHDP_XDP_BARS_ADDR_39_36", REG_MMIO, 0xc44, &mmHDP_XDP_BARS_ADDR_39_36[0], sizeof(mmHDP_XDP_BARS_ADDR_39_36)/sizeof(mmHDP_XDP_BARS_ADDR_39_36[0]), 0, 0 },
+	{ "mmIH_VMID_0_LUT", REG_MMIO, 0xe00, &mmIH_VMID_0_LUT[0], sizeof(mmIH_VMID_0_LUT)/sizeof(mmIH_VMID_0_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_1_LUT", REG_MMIO, 0xe01, &mmIH_VMID_1_LUT[0], sizeof(mmIH_VMID_1_LUT)/sizeof(mmIH_VMID_1_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_2_LUT", REG_MMIO, 0xe02, &mmIH_VMID_2_LUT[0], sizeof(mmIH_VMID_2_LUT)/sizeof(mmIH_VMID_2_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_3_LUT", REG_MMIO, 0xe03, &mmIH_VMID_3_LUT[0], sizeof(mmIH_VMID_3_LUT)/sizeof(mmIH_VMID_3_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_4_LUT", REG_MMIO, 0xe04, &mmIH_VMID_4_LUT[0], sizeof(mmIH_VMID_4_LUT)/sizeof(mmIH_VMID_4_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_5_LUT", REG_MMIO, 0xe05, &mmIH_VMID_5_LUT[0], sizeof(mmIH_VMID_5_LUT)/sizeof(mmIH_VMID_5_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_6_LUT", REG_MMIO, 0xe06, &mmIH_VMID_6_LUT[0], sizeof(mmIH_VMID_6_LUT)/sizeof(mmIH_VMID_6_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_7_LUT", REG_MMIO, 0xe07, &mmIH_VMID_7_LUT[0], sizeof(mmIH_VMID_7_LUT)/sizeof(mmIH_VMID_7_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_8_LUT", REG_MMIO, 0xe08, &mmIH_VMID_8_LUT[0], sizeof(mmIH_VMID_8_LUT)/sizeof(mmIH_VMID_8_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_9_LUT", REG_MMIO, 0xe09, &mmIH_VMID_9_LUT[0], sizeof(mmIH_VMID_9_LUT)/sizeof(mmIH_VMID_9_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_10_LUT", REG_MMIO, 0xe0a, &mmIH_VMID_10_LUT[0], sizeof(mmIH_VMID_10_LUT)/sizeof(mmIH_VMID_10_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_11_LUT", REG_MMIO, 0xe0b, &mmIH_VMID_11_LUT[0], sizeof(mmIH_VMID_11_LUT)/sizeof(mmIH_VMID_11_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_12_LUT", REG_MMIO, 0xe0c, &mmIH_VMID_12_LUT[0], sizeof(mmIH_VMID_12_LUT)/sizeof(mmIH_VMID_12_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_13_LUT", REG_MMIO, 0xe0d, &mmIH_VMID_13_LUT[0], sizeof(mmIH_VMID_13_LUT)/sizeof(mmIH_VMID_13_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_14_LUT", REG_MMIO, 0xe0e, &mmIH_VMID_14_LUT[0], sizeof(mmIH_VMID_14_LUT)/sizeof(mmIH_VMID_14_LUT[0]), 0, 0 },
+	{ "mmIH_VMID_15_LUT", REG_MMIO, 0xe0f, &mmIH_VMID_15_LUT[0], sizeof(mmIH_VMID_15_LUT)/sizeof(mmIH_VMID_15_LUT[0]), 0, 0 },
+	{ "mmIH_RB_CNTL", REG_MMIO, 0xe30, &mmIH_RB_CNTL[0], sizeof(mmIH_RB_CNTL)/sizeof(mmIH_RB_CNTL[0]), 0, 0 },
+	{ "mmIH_RB_BASE", REG_MMIO, 0xe31, &mmIH_RB_BASE[0], sizeof(mmIH_RB_BASE)/sizeof(mmIH_RB_BASE[0]), 0, 0 },
+	{ "mmIH_RB_RPTR", REG_MMIO, 0xe32, &mmIH_RB_RPTR[0], sizeof(mmIH_RB_RPTR)/sizeof(mmIH_RB_RPTR[0]), 0, 0 },
+	{ "mmIH_RB_WPTR", REG_MMIO, 0xe33, &mmIH_RB_WPTR[0], sizeof(mmIH_RB_WPTR)/sizeof(mmIH_RB_WPTR[0]), 0, 0 },
+	{ "mmIH_RB_WPTR_ADDR_HI", REG_MMIO, 0xe34, &mmIH_RB_WPTR_ADDR_HI[0], sizeof(mmIH_RB_WPTR_ADDR_HI)/sizeof(mmIH_RB_WPTR_ADDR_HI[0]), 0, 0 },
+	{ "mmIH_RB_WPTR_ADDR_LO", REG_MMIO, 0xe35, &mmIH_RB_WPTR_ADDR_LO[0], sizeof(mmIH_RB_WPTR_ADDR_LO)/sizeof(mmIH_RB_WPTR_ADDR_LO[0]), 0, 0 },
+	{ "mmIH_CNTL", REG_MMIO, 0xe36, &mmIH_CNTL[0], sizeof(mmIH_CNTL)/sizeof(mmIH_CNTL[0]), 0, 0 },
+	{ "mmIH_LEVEL_STATUS", REG_MMIO, 0xe37, &mmIH_LEVEL_STATUS[0], sizeof(mmIH_LEVEL_STATUS)/sizeof(mmIH_LEVEL_STATUS[0]), 0, 0 },
+	{ "mmIH_STATUS", REG_MMIO, 0xe38, &mmIH_STATUS[0], sizeof(mmIH_STATUS)/sizeof(mmIH_STATUS[0]), 0, 0 },
+	{ "mmIH_PERFMON_CNTL", REG_MMIO, 0xe39, &mmIH_PERFMON_CNTL[0], sizeof(mmIH_PERFMON_CNTL)/sizeof(mmIH_PERFMON_CNTL[0]), 0, 0 },
+	{ "mmIH_PERFCOUNTER0_RESULT", REG_MMIO, 0xe3a, &mmIH_PERFCOUNTER0_RESULT[0], sizeof(mmIH_PERFCOUNTER0_RESULT)/sizeof(mmIH_PERFCOUNTER0_RESULT[0]), 0, 0 },
+	{ "mmIH_PERFCOUNTER1_RESULT", REG_MMIO, 0xe3b, &mmIH_PERFCOUNTER1_RESULT[0], sizeof(mmIH_PERFCOUNTER1_RESULT)/sizeof(mmIH_PERFCOUNTER1_RESULT[0]), 0, 0 },
+	{ "mmIH_DEBUG", REG_MMIO, 0xe3c, &mmIH_DEBUG[0], sizeof(mmIH_DEBUG)/sizeof(mmIH_DEBUG[0]), 0, 0 },
+	{ "mmIH_DSM_MATCH_VALUE_BIT_31_0", REG_MMIO, 0xe3d, &mmIH_DSM_MATCH_VALUE_BIT_31_0[0], sizeof(mmIH_DSM_MATCH_VALUE_BIT_31_0)/sizeof(mmIH_DSM_MATCH_VALUE_BIT_31_0[0]), 0, 0 },
+	{ "mmIH_DSM_MATCH_VALUE_BIT_63_32", REG_MMIO, 0xe3e, &mmIH_DSM_MATCH_VALUE_BIT_63_32[0], sizeof(mmIH_DSM_MATCH_VALUE_BIT_63_32)/sizeof(mmIH_DSM_MATCH_VALUE_BIT_63_32[0]), 0, 0 },
+	{ "mmIH_DSM_MATCH_VALUE_BIT_95_64", REG_MMIO, 0xe3f, &mmIH_DSM_MATCH_VALUE_BIT_95_64[0], sizeof(mmIH_DSM_MATCH_VALUE_BIT_95_64)/sizeof(mmIH_DSM_MATCH_VALUE_BIT_95_64[0]), 0, 0 },
+	{ "mmIH_DSM_MATCH_FIELD_CONTROL", REG_MMIO, 0xe40, &mmIH_DSM_MATCH_FIELD_CONTROL[0], sizeof(mmIH_DSM_MATCH_FIELD_CONTROL)/sizeof(mmIH_DSM_MATCH_FIELD_CONTROL[0]), 0, 0 },
+	{ "mmIH_DSM_MATCH_DATA_CONTROL", REG_MMIO, 0xe41, &mmIH_DSM_MATCH_DATA_CONTROL[0], sizeof(mmIH_DSM_MATCH_DATA_CONTROL)/sizeof(mmIH_DSM_MATCH_DATA_CONTROL[0]), 0, 0 },
+	{ "mmIH_DOORBELL_RPTR", REG_MMIO, 0xe42, &mmIH_DOORBELL_RPTR[0], sizeof(mmIH_DOORBELL_RPTR)/sizeof(mmIH_DOORBELL_RPTR[0]), 0, 0 },
+	{ "mmIH_ACTIVE_FCN_ID", REG_MMIO, 0xe43, &mmIH_ACTIVE_FCN_ID[0], sizeof(mmIH_ACTIVE_FCN_ID)/sizeof(mmIH_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmIH_VF_RB_STATUS", REG_MMIO, 0xe44, &mmIH_VF_RB_STATUS[0], sizeof(mmIH_VF_RB_STATUS)/sizeof(mmIH_VF_RB_STATUS[0]), 0, 0 },
+	{ "mmIH_VF_ENABLE", REG_MMIO, 0xe45, &mmIH_VF_ENABLE[0], sizeof(mmIH_VF_ENABLE)/sizeof(mmIH_VF_ENABLE[0]), 0, 0 },
+	{ "mmIH_VIRT_RESET_REQ", REG_MMIO, 0xe46, &mmIH_VIRT_RESET_REQ[0], sizeof(mmIH_VIRT_RESET_REQ)/sizeof(mmIH_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmIH_VF_RB_BIF_STATUS", REG_MMIO, 0xe47, &mmIH_VF_RB_BIF_STATUS[0], sizeof(mmIH_VF_RB_BIF_STATUS)/sizeof(mmIH_VF_RB_BIF_STATUS[0]), 0, 0 },
+	{ "mmIH_VERSION", REG_MMIO, 0xe48, &mmIH_VERSION[0], sizeof(mmIH_VERSION)/sizeof(mmIH_VERSION[0]), 0, 0 },
+	{ "mmIH_LEVEL_INTR_MASK", REG_MMIO, 0xe49, &mmIH_LEVEL_INTR_MASK[0], sizeof(mmIH_LEVEL_INTR_MASK)/sizeof(mmIH_LEVEL_INTR_MASK[0]), 0, 0 },
+	{ "mmIH_RESET_INCOMPLETE_INT_CNTL", REG_MMIO, 0xe4a, &mmIH_RESET_INCOMPLETE_INT_CNTL[0], sizeof(mmIH_RESET_INCOMPLETE_INT_CNTL)/sizeof(mmIH_RESET_INCOMPLETE_INT_CNTL[0]), 0, 0 },
+	{ "mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT", REG_MMIO, 0xe4b, &mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT[0], sizeof(mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT)/sizeof(mmIH_CLIENT_MAY_SEND_INCOMPLETE_INT[0]), 0, 0 },
+	{ "mmSEM_MCIF_CONFIG", REG_MMIO, 0xf90, &mmSEM_MCIF_CONFIG[0], sizeof(mmSEM_MCIF_CONFIG)/sizeof(mmSEM_MCIF_CONFIG[0]), 0, 0 },
+	{ "mmSDMA_CONFIG", REG_MMIO, 0xf91, &mmSDMA_CONFIG[0], sizeof(mmSDMA_CONFIG)/sizeof(mmSDMA_CONFIG[0]), 0, 0 },
+	{ "mmSDMA1_CONFIG", REG_MMIO, 0xf92, &mmSDMA1_CONFIG[0], sizeof(mmSDMA1_CONFIG)/sizeof(mmSDMA1_CONFIG[0]), 0, 0 },
+	{ "mmUVD_CONFIG", REG_MMIO, 0xf93, &mmUVD_CONFIG[0], sizeof(mmUVD_CONFIG)/sizeof(mmUVD_CONFIG[0]), 0, 0 },
+	{ "mmVCE_CONFIG", REG_MMIO, 0xf94, &mmVCE_CONFIG[0], sizeof(mmVCE_CONFIG)/sizeof(mmVCE_CONFIG[0]), 0, 0 },
+	{ "mmSEM_VF_ENABLE", REG_MMIO, 0xf95, &mmSEM_VF_ENABLE[0], sizeof(mmSEM_VF_ENABLE)/sizeof(mmSEM_VF_ENABLE[0]), 0, 0 },
+	{ "mmCP_CONFIG", REG_MMIO, 0xf96, &mmCP_CONFIG[0], sizeof(mmCP_CONFIG)/sizeof(mmCP_CONFIG[0]), 0, 0 },
+	{ "mmSEM_ACTIVE_FCN_ID", REG_MMIO, 0xf97, &mmSEM_ACTIVE_FCN_ID[0], sizeof(mmSEM_ACTIVE_FCN_ID)/sizeof(mmSEM_ACTIVE_FCN_ID[0]), 0, 0 },
+	{ "mmSEM_VIRT_RESET_REQ", REG_MMIO, 0xf98, &mmSEM_VIRT_RESET_REQ[0], sizeof(mmSEM_VIRT_RESET_REQ)/sizeof(mmSEM_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmSEM_STATUS", REG_MMIO, 0xf99, &mmSEM_STATUS[0], sizeof(mmSEM_STATUS)/sizeof(mmSEM_STATUS[0]), 0, 0 },
+	{ "mmSEM_EDC_CONFIG", REG_MMIO, 0xf9a, &mmSEM_EDC_CONFIG[0], sizeof(mmSEM_EDC_CONFIG)/sizeof(mmSEM_EDC_CONFIG[0]), 0, 0 },
+	{ "mmSEM_MAILBOX_CLIENTCONFIG", REG_MMIO, 0xf9b, &mmSEM_MAILBOX_CLIENTCONFIG[0], sizeof(mmSEM_MAILBOX_CLIENTCONFIG)/sizeof(mmSEM_MAILBOX_CLIENTCONFIG[0]), 0, 0 },
+	{ "mmSEM_MAILBOX", REG_MMIO, 0xf9c, &mmSEM_MAILBOX[0], sizeof(mmSEM_MAILBOX)/sizeof(mmSEM_MAILBOX[0]), 0, 0 },
+	{ "mmSEM_MAILBOX_CONTROL", REG_MMIO, 0xf9d, &mmSEM_MAILBOX_CONTROL[0], sizeof(mmSEM_MAILBOX_CONTROL)/sizeof(mmSEM_MAILBOX_CONTROL[0]), 0, 0 },
+	{ "mmSEM_CHICKEN_BITS", REG_MMIO, 0xf9e, &mmSEM_CHICKEN_BITS[0], sizeof(mmSEM_CHICKEN_BITS)/sizeof(mmSEM_CHICKEN_BITS[0]), 0, 0 },
+	{ "mmSEM_MAILBOX_CLIENTCONFIG_EXTRA", REG_MMIO, 0xf9f, &mmSEM_MAILBOX_CLIENTCONFIG_EXTRA[0], sizeof(mmSEM_MAILBOX_CLIENTCONFIG_EXTRA)/sizeof(mmSEM_MAILBOX_CLIENTCONFIG_EXTRA[0]), 0, 0 },
+	{ "mmSRBM_MC_DOMAIN_ADDR0", REG_MMIO, 0xfa00, &mmSRBM_MC_DOMAIN_ADDR0[0], sizeof(mmSRBM_MC_DOMAIN_ADDR0)/sizeof(mmSRBM_MC_DOMAIN_ADDR0[0]), 0, 0 },
+	{ "mmSRBM_MC_DOMAIN_ADDR1", REG_MMIO, 0xfa01, &mmSRBM_MC_DOMAIN_ADDR1[0], sizeof(mmSRBM_MC_DOMAIN_ADDR1)/sizeof(mmSRBM_MC_DOMAIN_ADDR1[0]), 0, 0 },
+	{ "mmSRBM_MC_DOMAIN_ADDR2", REG_MMIO, 0xfa02, &mmSRBM_MC_DOMAIN_ADDR2[0], sizeof(mmSRBM_MC_DOMAIN_ADDR2)/sizeof(mmSRBM_MC_DOMAIN_ADDR2[0]), 0, 0 },
+	{ "mmSRBM_MC_DOMAIN_ADDR3", REG_MMIO, 0xfa03, &mmSRBM_MC_DOMAIN_ADDR3[0], sizeof(mmSRBM_MC_DOMAIN_ADDR3)/sizeof(mmSRBM_MC_DOMAIN_ADDR3[0]), 0, 0 },
+	{ "mmSRBM_MC_DOMAIN_ADDR4", REG_MMIO, 0xfa04, &mmSRBM_MC_DOMAIN_ADDR4[0], sizeof(mmSRBM_MC_DOMAIN_ADDR4)/sizeof(mmSRBM_MC_DOMAIN_ADDR4[0]), 0, 0 },
+	{ "mmSRBM_MC_DOMAIN_ADDR5", REG_MMIO, 0xfa05, &mmSRBM_MC_DOMAIN_ADDR5[0], sizeof(mmSRBM_MC_DOMAIN_ADDR5)/sizeof(mmSRBM_MC_DOMAIN_ADDR5[0]), 0, 0 },
+	{ "mmSRBM_MC_DOMAIN_ADDR6", REG_MMIO, 0xfa06, &mmSRBM_MC_DOMAIN_ADDR6[0], sizeof(mmSRBM_MC_DOMAIN_ADDR6)/sizeof(mmSRBM_MC_DOMAIN_ADDR6[0]), 0, 0 },
+	{ "mmSRBM_SYS_DOMAIN_ADDR0", REG_MMIO, 0xfa08, &mmSRBM_SYS_DOMAIN_ADDR0[0], sizeof(mmSRBM_SYS_DOMAIN_ADDR0)/sizeof(mmSRBM_SYS_DOMAIN_ADDR0[0]), 0, 0 },
+	{ "mmSRBM_SYS_DOMAIN_ADDR1", REG_MMIO, 0xfa09, &mmSRBM_SYS_DOMAIN_ADDR1[0], sizeof(mmSRBM_SYS_DOMAIN_ADDR1)/sizeof(mmSRBM_SYS_DOMAIN_ADDR1[0]), 0, 0 },
+	{ "mmSRBM_SYS_DOMAIN_ADDR2", REG_MMIO, 0xfa0a, &mmSRBM_SYS_DOMAIN_ADDR2[0], sizeof(mmSRBM_SYS_DOMAIN_ADDR2)/sizeof(mmSRBM_SYS_DOMAIN_ADDR2[0]), 0, 0 },
+	{ "mmSRBM_SYS_DOMAIN_ADDR3", REG_MMIO, 0xfa0b, &mmSRBM_SYS_DOMAIN_ADDR3[0], sizeof(mmSRBM_SYS_DOMAIN_ADDR3)/sizeof(mmSRBM_SYS_DOMAIN_ADDR3[0]), 0, 0 },
+	{ "mmSRBM_SYS_DOMAIN_ADDR4", REG_MMIO, 0xfa0c, &mmSRBM_SYS_DOMAIN_ADDR4[0], sizeof(mmSRBM_SYS_DOMAIN_ADDR4)/sizeof(mmSRBM_SYS_DOMAIN_ADDR4[0]), 0, 0 },
+	{ "mmSRBM_SYS_DOMAIN_ADDR5", REG_MMIO, 0xfa0d, &mmSRBM_SYS_DOMAIN_ADDR5[0], sizeof(mmSRBM_SYS_DOMAIN_ADDR5)/sizeof(mmSRBM_SYS_DOMAIN_ADDR5[0]), 0, 0 },
+	{ "mmSRBM_SYS_DOMAIN_ADDR6", REG_MMIO, 0xfa0e, &mmSRBM_SYS_DOMAIN_ADDR6[0], sizeof(mmSRBM_SYS_DOMAIN_ADDR6)/sizeof(mmSRBM_SYS_DOMAIN_ADDR6[0]), 0, 0 },
+	{ "mmSRBM_SDMA_DOMAIN_ADDR0", REG_MMIO, 0xfa10, &mmSRBM_SDMA_DOMAIN_ADDR0[0], sizeof(mmSRBM_SDMA_DOMAIN_ADDR0)/sizeof(mmSRBM_SDMA_DOMAIN_ADDR0[0]), 0, 0 },
+	{ "mmSRBM_SDMA_DOMAIN_ADDR1", REG_MMIO, 0xfa11, &mmSRBM_SDMA_DOMAIN_ADDR1[0], sizeof(mmSRBM_SDMA_DOMAIN_ADDR1)/sizeof(mmSRBM_SDMA_DOMAIN_ADDR1[0]), 0, 0 },
+	{ "mmSRBM_SDMA_DOMAIN_ADDR2", REG_MMIO, 0xfa12, &mmSRBM_SDMA_DOMAIN_ADDR2[0], sizeof(mmSRBM_SDMA_DOMAIN_ADDR2)/sizeof(mmSRBM_SDMA_DOMAIN_ADDR2[0]), 0, 0 },
+	{ "mmSRBM_SDMA_DOMAIN_ADDR3", REG_MMIO, 0xfa13, &mmSRBM_SDMA_DOMAIN_ADDR3[0], sizeof(mmSRBM_SDMA_DOMAIN_ADDR3)/sizeof(mmSRBM_SDMA_DOMAIN_ADDR3[0]), 0, 0 },
+	{ "mmSRBM_UVD_DOMAIN_ADDR0", REG_MMIO, 0xfa14, &mmSRBM_UVD_DOMAIN_ADDR0[0], sizeof(mmSRBM_UVD_DOMAIN_ADDR0)/sizeof(mmSRBM_UVD_DOMAIN_ADDR0[0]), 0, 0 },
+	{ "mmSRBM_UVD_DOMAIN_ADDR1", REG_MMIO, 0xfa15, &mmSRBM_UVD_DOMAIN_ADDR1[0], sizeof(mmSRBM_UVD_DOMAIN_ADDR1)/sizeof(mmSRBM_UVD_DOMAIN_ADDR1[0]), 0, 0 },
+	{ "mmSRBM_UVD_DOMAIN_ADDR2", REG_MMIO, 0xfa16, &mmSRBM_UVD_DOMAIN_ADDR2[0], sizeof(mmSRBM_UVD_DOMAIN_ADDR2)/sizeof(mmSRBM_UVD_DOMAIN_ADDR2[0]), 0, 0 },
+	{ "mmSRBM_VCE_DOMAIN_ADDR0", REG_MMIO, 0xfa18, &mmSRBM_VCE_DOMAIN_ADDR0[0], sizeof(mmSRBM_VCE_DOMAIN_ADDR0)/sizeof(mmSRBM_VCE_DOMAIN_ADDR0[0]), 0, 0 },
+	{ "mmSRBM_VCE_DOMAIN_ADDR1", REG_MMIO, 0xfa19, &mmSRBM_VCE_DOMAIN_ADDR1[0], sizeof(mmSRBM_VCE_DOMAIN_ADDR1)/sizeof(mmSRBM_VCE_DOMAIN_ADDR1[0]), 0, 0 },
+	{ "mmSRBM_VCE_DOMAIN_ADDR2", REG_MMIO, 0xfa1a, &mmSRBM_VCE_DOMAIN_ADDR2[0], sizeof(mmSRBM_VCE_DOMAIN_ADDR2)/sizeof(mmSRBM_VCE_DOMAIN_ADDR2[0]), 0, 0 },
+	{ "mmSRBM_SAM_DOMAIN_ADDR0", REG_MMIO, 0xfa1c, &mmSRBM_SAM_DOMAIN_ADDR0[0], sizeof(mmSRBM_SAM_DOMAIN_ADDR0)/sizeof(mmSRBM_SAM_DOMAIN_ADDR0[0]), 0, 0 },
+	{ "mmSRBM_SAM_DOMAIN_ADDR1", REG_MMIO, 0xfa1d, &mmSRBM_SAM_DOMAIN_ADDR1[0], sizeof(mmSRBM_SAM_DOMAIN_ADDR1)/sizeof(mmSRBM_SAM_DOMAIN_ADDR1[0]), 0, 0 },
+	{ "mmSRBM_SAM_DOMAIN_ADDR2", REG_MMIO, 0xfa1e, &mmSRBM_SAM_DOMAIN_ADDR2[0], sizeof(mmSRBM_SAM_DOMAIN_ADDR2)/sizeof(mmSRBM_SAM_DOMAIN_ADDR2[0]), 0, 0 },
+	{ "mmSRBM_ISP_DOMAIN_ADDR0", REG_MMIO, 0xfa20, &mmSRBM_ISP_DOMAIN_ADDR0[0], sizeof(mmSRBM_ISP_DOMAIN_ADDR0)/sizeof(mmSRBM_ISP_DOMAIN_ADDR0[0]), 0, 0 },
+	{ "mmSRBM_ISP_DOMAIN_ADDR1", REG_MMIO, 0xfa21, &mmSRBM_ISP_DOMAIN_ADDR1[0], sizeof(mmSRBM_ISP_DOMAIN_ADDR1)/sizeof(mmSRBM_ISP_DOMAIN_ADDR1[0]), 0, 0 },
+	{ "mmSRBM_ISP_DOMAIN_ADDR2", REG_MMIO, 0xfa22, &mmSRBM_ISP_DOMAIN_ADDR2[0], sizeof(mmSRBM_ISP_DOMAIN_ADDR2)/sizeof(mmSRBM_ISP_DOMAIN_ADDR2[0]), 0, 0 },
+	{ "mmSRBM_VP8_DOMAIN_ADDR0", REG_MMIO, 0xfa24, &mmSRBM_VP8_DOMAIN_ADDR0[0], sizeof(mmSRBM_VP8_DOMAIN_ADDR0)/sizeof(mmSRBM_VP8_DOMAIN_ADDR0[0]), 0, 0 },
+	{ "mmSYS_GRBM_GFX_INDEX_SELECT", REG_MMIO, 0xfa2c, &mmSYS_GRBM_GFX_INDEX_SELECT[0], sizeof(mmSYS_GRBM_GFX_INDEX_SELECT)/sizeof(mmSYS_GRBM_GFX_INDEX_SELECT[0]), 0, 0 },
+	{ "mmSYS_GRBM_GFX_INDEX_DATA", REG_MMIO, 0xfa2d, &mmSYS_GRBM_GFX_INDEX_DATA[0], sizeof(mmSYS_GRBM_GFX_INDEX_DATA)/sizeof(mmSYS_GRBM_GFX_INDEX_DATA[0]), 0, 0 },
+	{ "mmSRBM_GFX_CNTL_SELECT", REG_MMIO, 0xfa2e, &mmSRBM_GFX_CNTL_SELECT[0], sizeof(mmSRBM_GFX_CNTL_SELECT)/sizeof(mmSRBM_GFX_CNTL_SELECT[0]), 0, 0 },
+	{ "mmSRBM_GFX_CNTL_DATA", REG_MMIO, 0xfa2f, &mmSRBM_GFX_CNTL_DATA[0], sizeof(mmSRBM_GFX_CNTL_DATA)/sizeof(mmSRBM_GFX_CNTL_DATA[0]), 0, 0 },
+	{ "mmSRBM_VF_ENABLE", REG_MMIO, 0xfa30, &mmSRBM_VF_ENABLE[0], sizeof(mmSRBM_VF_ENABLE)/sizeof(mmSRBM_VF_ENABLE[0]), 0, 0 },
+	{ "mmSRBM_VIRT_CNTL", REG_MMIO, 0xfa31, &mmSRBM_VIRT_CNTL[0], sizeof(mmSRBM_VIRT_CNTL)/sizeof(mmSRBM_VIRT_CNTL[0]), 0, 0 },
+	{ "mmSRBM_VIRT_RESET_REQ", REG_MMIO, 0xfa32, &mmSRBM_VIRT_RESET_REQ[0], sizeof(mmSRBM_VIRT_RESET_REQ)/sizeof(mmSRBM_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "mmSRBM_CAM_INDEX", REG_MMIO, 0xfe34, &mmSRBM_CAM_INDEX[0], sizeof(mmSRBM_CAM_INDEX)/sizeof(mmSRBM_CAM_INDEX[0]), 0, 0 },
+	{ "mmSRBM_CAM_DATA", REG_MMIO, 0xfe35, &mmSRBM_CAM_DATA[0], sizeof(mmSRBM_CAM_DATA)/sizeof(mmSRBM_CAM_DATA[0]), 0, 0 },
diff --git a/src/lib/ip/smu60.c b/src/lib/ip/smu60.c
new file mode 100644
index 0000000..545d1ba
--- /dev/null
+++ b/src/lib/ip/smu60.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "smu60_bits.i"
+
+static const struct umr_reg smu60_registers[] = {
+#include "smu60_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_smu60(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "smu60";
+	ip->no_regs = sizeof(smu60_registers)/sizeof(smu60_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(smu60_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, smu60_registers, sizeof(smu60_registers));
+	return ip;
+}
diff --git a/src/lib/ip/smu60_bits.i b/src/lib/ip/smu60_bits.i
new file mode 100644
index 0000000..7734c28
--- /dev/null
+++ b/src/lib/ip/smu60_bits.i
@@ -0,0 +1,567 @@
+static struct umr_bitfield mmSMC_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_ACCESS_CNTL[] = {
+	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_1", 8, 8, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_2", 16, 16, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_3", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_0[] = {
+	 { "SMC_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_0[] = {
+	 { "SMC_RESP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_1[] = {
+	 { "SMC_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_1[] = {
+	 { "SMC_RESP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_2[] = {
+	 { "SMC_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_2[] = {
+	 { "SMC_RESP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
+	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
+	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
+	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
+	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
+	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
+	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
+	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
+	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
+	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
+	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
+	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
+	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC4_CNTL[] = {
+	 { "MC4_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC4_THRESHOLD", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC4_OVR_SEL[] = {
+	 { "MC4_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC4_OVR_VAL[] = {
+	 { "MC4_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC5_CNTL[] = {
+	 { "MC5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC5_THRESHOLD", 1, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC5_OVR_SEL[] = {
+	 { "MC5_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC5_OVR_VAL[] = {
+	 { "MC5_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL0_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL1_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL2_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL3_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL4_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL5_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL6_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL7_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL8_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL9_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL10_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL11_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL12_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL13_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL14_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL15_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR0_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR1_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR2_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR3_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR4_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR5_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR6_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR7_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR8_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR9_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR10_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR11_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR12_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR13_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR14_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR15_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL0_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL1_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL2_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL3_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL4_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL5_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL6_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL7_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL8_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL9_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL10_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL11_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL12_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL13_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL14_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL15_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR0_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR1_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR2_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR3_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR4_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR5_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR6_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR7_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR8_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR9_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR10_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR11_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR12_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR13_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR14_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR15_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_INT_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_INT_DATA[] = {
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_SW_INT_STAT[] = {
+	 { "SW_INT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_STRENGTH[] = {
+	 { "GPIO_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GPIO_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_MASK[] = {
+	 { "GPIO_MASK", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_A[] = {
+	 { "GPIO_A", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EN[] = {
+	 { "GPIO_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_Y[] = {
+	 { "GPIO_Y", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PINSTRAPS[] = {
+	 { "GPIO_PINSTRAP_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_28", 28, 28, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_29", 29, 29, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_30", 30, 30, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_9", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_EN[] = {
+	 { "GPIO_INT_STAT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT[] = {
+	 { "GPIO_INT_STAT", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_AK[] = {
+	 { "GPIO_INT_STAT_AK_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_28", 28, 28, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_9", 9, 9, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_AK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_EN[] = {
+	 { "GPIO_INT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_TYPE[] = {
+	 { "GPIO_INT_TYPE", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_POLARITY[] = {
+	 { "GPIO_INT_POLARITY", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_POLARITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EXTERN_TRIG_CNTL[] = {
+	 { "EXTERN_TRIG_CLR", 5, 5, &umr_bitfield_default },
+	 { "EXTERN_TRIG_READ", 6, 6, &umr_bitfield_default },
+	 { "EXTERN_TRIG_SEL", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_RCVR_SEL[] = {
+	 { "GPIO_RCVR_SEL", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PU_EN[] = {
+	 { "GPIO_PU_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PD_EN[] = {
+	 { "GPIO_PD_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_PC_C[] = {
+	 { "smc_pc_c", 0, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/smu60_regs.i b/src/lib/ip/smu60_regs.i
new file mode 100644
index 0000000..abc4922
--- /dev/null
+++ b/src/lib/ip/smu60_regs.i
@@ -0,0 +1,119 @@
+	{ "mmSMC_IND_INDEX_0", REG_MMIO, 0x0080, &mmSMC_IND_INDEX_0[0], sizeof(mmSMC_IND_INDEX_0)/sizeof(mmSMC_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_0", REG_MMIO, 0x0081, &mmSMC_IND_DATA_0[0], sizeof(mmSMC_IND_DATA_0)/sizeof(mmSMC_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_1", REG_MMIO, 0x0082, &mmSMC_IND_INDEX_1[0], sizeof(mmSMC_IND_INDEX_1)/sizeof(mmSMC_IND_INDEX_1[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_1", REG_MMIO, 0x0083, &mmSMC_IND_DATA_1[0], sizeof(mmSMC_IND_DATA_1)/sizeof(mmSMC_IND_DATA_1[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_2", REG_MMIO, 0x0084, &mmSMC_IND_INDEX_2[0], sizeof(mmSMC_IND_INDEX_2)/sizeof(mmSMC_IND_INDEX_2[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_2", REG_MMIO, 0x0085, &mmSMC_IND_DATA_2[0], sizeof(mmSMC_IND_DATA_2)/sizeof(mmSMC_IND_DATA_2[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_3", REG_MMIO, 0x0086, &mmSMC_IND_INDEX_3[0], sizeof(mmSMC_IND_INDEX_3)/sizeof(mmSMC_IND_INDEX_3[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_3", REG_MMIO, 0x0087, &mmSMC_IND_DATA_3[0], sizeof(mmSMC_IND_DATA_3)/sizeof(mmSMC_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMC_IND_ACCESS_CNTL", REG_MMIO, 0x008A, &mmSMC_IND_ACCESS_CNTL[0], sizeof(mmSMC_IND_ACCESS_CNTL)/sizeof(mmSMC_IND_ACCESS_CNTL[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_0", REG_MMIO, 0x008B, &mmSMC_MESSAGE_0[0], sizeof(mmSMC_MESSAGE_0)/sizeof(mmSMC_MESSAGE_0[0]), 0, 0 },
+	{ "mmSMC_RESP_0", REG_MMIO, 0x008C, &mmSMC_RESP_0[0], sizeof(mmSMC_RESP_0)/sizeof(mmSMC_RESP_0[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_1", REG_MMIO, 0x008D, &mmSMC_MESSAGE_1[0], sizeof(mmSMC_MESSAGE_1)/sizeof(mmSMC_MESSAGE_1[0]), 0, 0 },
+	{ "mmSMC_RESP_1", REG_MMIO, 0x008E, &mmSMC_RESP_1[0], sizeof(mmSMC_RESP_1)/sizeof(mmSMC_RESP_1[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_2", REG_MMIO, 0x008F, &mmSMC_MESSAGE_2[0], sizeof(mmSMC_MESSAGE_2)/sizeof(mmSMC_MESSAGE_2[0]), 0, 0 },
+	{ "mmSMC_RESP_2", REG_MMIO, 0x0090, &mmSMC_RESP_2[0], sizeof(mmSMC_RESP_2)/sizeof(mmSMC_RESP_2[0]), 0, 0 },
+	{ "ixLCAC_MC0_CNTL", REG_SMC, 0x011C, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0x011D, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0x011E, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC1_CNTL", REG_SMC, 0x011F, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0x0120, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0x0121, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC2_CNTL", REG_SMC, 0x0122, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0x0123, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0x0124, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC3_CNTL", REG_SMC, 0x0125, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0x0126, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0x0127, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC4_CNTL", REG_SMC, 0x0128, &ixLCAC_MC4_CNTL[0], sizeof(ixLCAC_MC4_CNTL)/sizeof(ixLCAC_MC4_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC4_OVR_SEL", REG_SMC, 0x0129, &ixLCAC_MC4_OVR_SEL[0], sizeof(ixLCAC_MC4_OVR_SEL)/sizeof(ixLCAC_MC4_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC4_OVR_VAL", REG_SMC, 0x012A, &ixLCAC_MC4_OVR_VAL[0], sizeof(ixLCAC_MC4_OVR_VAL)/sizeof(ixLCAC_MC4_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC5_CNTL", REG_SMC, 0x012B, &ixLCAC_MC5_CNTL[0], sizeof(ixLCAC_MC5_CNTL)/sizeof(ixLCAC_MC5_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC5_OVR_SEL", REG_SMC, 0x012C, &ixLCAC_MC5_OVR_SEL[0], sizeof(ixLCAC_MC5_OVR_SEL)/sizeof(ixLCAC_MC5_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC5_OVR_VAL", REG_SMC, 0x012D, &ixLCAC_MC5_OVR_VAL[0], sizeof(ixLCAC_MC5_OVR_VAL)/sizeof(ixLCAC_MC5_OVR_VAL[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL0_DATA", REG_SMC, 0x0300, &ixTHM_TMON0_RDIL0_DATA[0], sizeof(ixTHM_TMON0_RDIL0_DATA)/sizeof(ixTHM_TMON0_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL1_DATA", REG_SMC, 0x0301, &ixTHM_TMON0_RDIL1_DATA[0], sizeof(ixTHM_TMON0_RDIL1_DATA)/sizeof(ixTHM_TMON0_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL2_DATA", REG_SMC, 0x0302, &ixTHM_TMON0_RDIL2_DATA[0], sizeof(ixTHM_TMON0_RDIL2_DATA)/sizeof(ixTHM_TMON0_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL3_DATA", REG_SMC, 0x0303, &ixTHM_TMON0_RDIL3_DATA[0], sizeof(ixTHM_TMON0_RDIL3_DATA)/sizeof(ixTHM_TMON0_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL4_DATA", REG_SMC, 0x0304, &ixTHM_TMON0_RDIL4_DATA[0], sizeof(ixTHM_TMON0_RDIL4_DATA)/sizeof(ixTHM_TMON0_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL5_DATA", REG_SMC, 0x0305, &ixTHM_TMON0_RDIL5_DATA[0], sizeof(ixTHM_TMON0_RDIL5_DATA)/sizeof(ixTHM_TMON0_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL6_DATA", REG_SMC, 0x0306, &ixTHM_TMON0_RDIL6_DATA[0], sizeof(ixTHM_TMON0_RDIL6_DATA)/sizeof(ixTHM_TMON0_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL7_DATA", REG_SMC, 0x0307, &ixTHM_TMON0_RDIL7_DATA[0], sizeof(ixTHM_TMON0_RDIL7_DATA)/sizeof(ixTHM_TMON0_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL8_DATA", REG_SMC, 0x0308, &ixTHM_TMON0_RDIL8_DATA[0], sizeof(ixTHM_TMON0_RDIL8_DATA)/sizeof(ixTHM_TMON0_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL9_DATA", REG_SMC, 0x0309, &ixTHM_TMON0_RDIL9_DATA[0], sizeof(ixTHM_TMON0_RDIL9_DATA)/sizeof(ixTHM_TMON0_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL10_DATA", REG_SMC, 0x030A, &ixTHM_TMON0_RDIL10_DATA[0], sizeof(ixTHM_TMON0_RDIL10_DATA)/sizeof(ixTHM_TMON0_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL11_DATA", REG_SMC, 0x030B, &ixTHM_TMON0_RDIL11_DATA[0], sizeof(ixTHM_TMON0_RDIL11_DATA)/sizeof(ixTHM_TMON0_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL12_DATA", REG_SMC, 0x030C, &ixTHM_TMON0_RDIL12_DATA[0], sizeof(ixTHM_TMON0_RDIL12_DATA)/sizeof(ixTHM_TMON0_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL13_DATA", REG_SMC, 0x030D, &ixTHM_TMON0_RDIL13_DATA[0], sizeof(ixTHM_TMON0_RDIL13_DATA)/sizeof(ixTHM_TMON0_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL14_DATA", REG_SMC, 0x030E, &ixTHM_TMON0_RDIL14_DATA[0], sizeof(ixTHM_TMON0_RDIL14_DATA)/sizeof(ixTHM_TMON0_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL15_DATA", REG_SMC, 0x030F, &ixTHM_TMON0_RDIL15_DATA[0], sizeof(ixTHM_TMON0_RDIL15_DATA)/sizeof(ixTHM_TMON0_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR0_DATA", REG_SMC, 0x0310, &ixTHM_TMON0_RDIR0_DATA[0], sizeof(ixTHM_TMON0_RDIR0_DATA)/sizeof(ixTHM_TMON0_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR1_DATA", REG_SMC, 0x0311, &ixTHM_TMON0_RDIR1_DATA[0], sizeof(ixTHM_TMON0_RDIR1_DATA)/sizeof(ixTHM_TMON0_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR2_DATA", REG_SMC, 0x0312, &ixTHM_TMON0_RDIR2_DATA[0], sizeof(ixTHM_TMON0_RDIR2_DATA)/sizeof(ixTHM_TMON0_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR3_DATA", REG_SMC, 0x0313, &ixTHM_TMON0_RDIR3_DATA[0], sizeof(ixTHM_TMON0_RDIR3_DATA)/sizeof(ixTHM_TMON0_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR4_DATA", REG_SMC, 0x0314, &ixTHM_TMON0_RDIR4_DATA[0], sizeof(ixTHM_TMON0_RDIR4_DATA)/sizeof(ixTHM_TMON0_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR5_DATA", REG_SMC, 0x0315, &ixTHM_TMON0_RDIR5_DATA[0], sizeof(ixTHM_TMON0_RDIR5_DATA)/sizeof(ixTHM_TMON0_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR6_DATA", REG_SMC, 0x0316, &ixTHM_TMON0_RDIR6_DATA[0], sizeof(ixTHM_TMON0_RDIR6_DATA)/sizeof(ixTHM_TMON0_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR7_DATA", REG_SMC, 0x0317, &ixTHM_TMON0_RDIR7_DATA[0], sizeof(ixTHM_TMON0_RDIR7_DATA)/sizeof(ixTHM_TMON0_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR8_DATA", REG_SMC, 0x0318, &ixTHM_TMON0_RDIR8_DATA[0], sizeof(ixTHM_TMON0_RDIR8_DATA)/sizeof(ixTHM_TMON0_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR9_DATA", REG_SMC, 0x0319, &ixTHM_TMON0_RDIR9_DATA[0], sizeof(ixTHM_TMON0_RDIR9_DATA)/sizeof(ixTHM_TMON0_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR10_DATA", REG_SMC, 0x031A, &ixTHM_TMON0_RDIR10_DATA[0], sizeof(ixTHM_TMON0_RDIR10_DATA)/sizeof(ixTHM_TMON0_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR11_DATA", REG_SMC, 0x031B, &ixTHM_TMON0_RDIR11_DATA[0], sizeof(ixTHM_TMON0_RDIR11_DATA)/sizeof(ixTHM_TMON0_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR12_DATA", REG_SMC, 0x031C, &ixTHM_TMON0_RDIR12_DATA[0], sizeof(ixTHM_TMON0_RDIR12_DATA)/sizeof(ixTHM_TMON0_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR13_DATA", REG_SMC, 0x031D, &ixTHM_TMON0_RDIR13_DATA[0], sizeof(ixTHM_TMON0_RDIR13_DATA)/sizeof(ixTHM_TMON0_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR14_DATA", REG_SMC, 0x031E, &ixTHM_TMON0_RDIR14_DATA[0], sizeof(ixTHM_TMON0_RDIR14_DATA)/sizeof(ixTHM_TMON0_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR15_DATA", REG_SMC, 0x031F, &ixTHM_TMON0_RDIR15_DATA[0], sizeof(ixTHM_TMON0_RDIR15_DATA)/sizeof(ixTHM_TMON0_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL0_DATA", REG_SMC, 0x0320, &ixTHM_TMON1_RDIL0_DATA[0], sizeof(ixTHM_TMON1_RDIL0_DATA)/sizeof(ixTHM_TMON1_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL1_DATA", REG_SMC, 0x0321, &ixTHM_TMON1_RDIL1_DATA[0], sizeof(ixTHM_TMON1_RDIL1_DATA)/sizeof(ixTHM_TMON1_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL2_DATA", REG_SMC, 0x0322, &ixTHM_TMON1_RDIL2_DATA[0], sizeof(ixTHM_TMON1_RDIL2_DATA)/sizeof(ixTHM_TMON1_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL3_DATA", REG_SMC, 0x0323, &ixTHM_TMON1_RDIL3_DATA[0], sizeof(ixTHM_TMON1_RDIL3_DATA)/sizeof(ixTHM_TMON1_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL4_DATA", REG_SMC, 0x0324, &ixTHM_TMON1_RDIL4_DATA[0], sizeof(ixTHM_TMON1_RDIL4_DATA)/sizeof(ixTHM_TMON1_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL5_DATA", REG_SMC, 0x0325, &ixTHM_TMON1_RDIL5_DATA[0], sizeof(ixTHM_TMON1_RDIL5_DATA)/sizeof(ixTHM_TMON1_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL6_DATA", REG_SMC, 0x0326, &ixTHM_TMON1_RDIL6_DATA[0], sizeof(ixTHM_TMON1_RDIL6_DATA)/sizeof(ixTHM_TMON1_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL7_DATA", REG_SMC, 0x0327, &ixTHM_TMON1_RDIL7_DATA[0], sizeof(ixTHM_TMON1_RDIL7_DATA)/sizeof(ixTHM_TMON1_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL8_DATA", REG_SMC, 0x0328, &ixTHM_TMON1_RDIL8_DATA[0], sizeof(ixTHM_TMON1_RDIL8_DATA)/sizeof(ixTHM_TMON1_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL9_DATA", REG_SMC, 0x0329, &ixTHM_TMON1_RDIL9_DATA[0], sizeof(ixTHM_TMON1_RDIL9_DATA)/sizeof(ixTHM_TMON1_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL10_DATA", REG_SMC, 0x032A, &ixTHM_TMON1_RDIL10_DATA[0], sizeof(ixTHM_TMON1_RDIL10_DATA)/sizeof(ixTHM_TMON1_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL11_DATA", REG_SMC, 0x032B, &ixTHM_TMON1_RDIL11_DATA[0], sizeof(ixTHM_TMON1_RDIL11_DATA)/sizeof(ixTHM_TMON1_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL12_DATA", REG_SMC, 0x032C, &ixTHM_TMON1_RDIL12_DATA[0], sizeof(ixTHM_TMON1_RDIL12_DATA)/sizeof(ixTHM_TMON1_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL13_DATA", REG_SMC, 0x032D, &ixTHM_TMON1_RDIL13_DATA[0], sizeof(ixTHM_TMON1_RDIL13_DATA)/sizeof(ixTHM_TMON1_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL14_DATA", REG_SMC, 0x032E, &ixTHM_TMON1_RDIL14_DATA[0], sizeof(ixTHM_TMON1_RDIL14_DATA)/sizeof(ixTHM_TMON1_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL15_DATA", REG_SMC, 0x032F, &ixTHM_TMON1_RDIL15_DATA[0], sizeof(ixTHM_TMON1_RDIL15_DATA)/sizeof(ixTHM_TMON1_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR0_DATA", REG_SMC, 0x0330, &ixTHM_TMON1_RDIR0_DATA[0], sizeof(ixTHM_TMON1_RDIR0_DATA)/sizeof(ixTHM_TMON1_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR1_DATA", REG_SMC, 0x0331, &ixTHM_TMON1_RDIR1_DATA[0], sizeof(ixTHM_TMON1_RDIR1_DATA)/sizeof(ixTHM_TMON1_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR2_DATA", REG_SMC, 0x0332, &ixTHM_TMON1_RDIR2_DATA[0], sizeof(ixTHM_TMON1_RDIR2_DATA)/sizeof(ixTHM_TMON1_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR3_DATA", REG_SMC, 0x0333, &ixTHM_TMON1_RDIR3_DATA[0], sizeof(ixTHM_TMON1_RDIR3_DATA)/sizeof(ixTHM_TMON1_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR4_DATA", REG_SMC, 0x0334, &ixTHM_TMON1_RDIR4_DATA[0], sizeof(ixTHM_TMON1_RDIR4_DATA)/sizeof(ixTHM_TMON1_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR5_DATA", REG_SMC, 0x0335, &ixTHM_TMON1_RDIR5_DATA[0], sizeof(ixTHM_TMON1_RDIR5_DATA)/sizeof(ixTHM_TMON1_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR6_DATA", REG_SMC, 0x0336, &ixTHM_TMON1_RDIR6_DATA[0], sizeof(ixTHM_TMON1_RDIR6_DATA)/sizeof(ixTHM_TMON1_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR7_DATA", REG_SMC, 0x0337, &ixTHM_TMON1_RDIR7_DATA[0], sizeof(ixTHM_TMON1_RDIR7_DATA)/sizeof(ixTHM_TMON1_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR8_DATA", REG_SMC, 0x0338, &ixTHM_TMON1_RDIR8_DATA[0], sizeof(ixTHM_TMON1_RDIR8_DATA)/sizeof(ixTHM_TMON1_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR9_DATA", REG_SMC, 0x0339, &ixTHM_TMON1_RDIR9_DATA[0], sizeof(ixTHM_TMON1_RDIR9_DATA)/sizeof(ixTHM_TMON1_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR10_DATA", REG_SMC, 0x033A, &ixTHM_TMON1_RDIR10_DATA[0], sizeof(ixTHM_TMON1_RDIR10_DATA)/sizeof(ixTHM_TMON1_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR11_DATA", REG_SMC, 0x033B, &ixTHM_TMON1_RDIR11_DATA[0], sizeof(ixTHM_TMON1_RDIR11_DATA)/sizeof(ixTHM_TMON1_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR12_DATA", REG_SMC, 0x033C, &ixTHM_TMON1_RDIR12_DATA[0], sizeof(ixTHM_TMON1_RDIR12_DATA)/sizeof(ixTHM_TMON1_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR13_DATA", REG_SMC, 0x033D, &ixTHM_TMON1_RDIR13_DATA[0], sizeof(ixTHM_TMON1_RDIR13_DATA)/sizeof(ixTHM_TMON1_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR14_DATA", REG_SMC, 0x033E, &ixTHM_TMON1_RDIR14_DATA[0], sizeof(ixTHM_TMON1_RDIR14_DATA)/sizeof(ixTHM_TMON1_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR15_DATA", REG_SMC, 0x033F, &ixTHM_TMON1_RDIR15_DATA[0], sizeof(ixTHM_TMON1_RDIR15_DATA)/sizeof(ixTHM_TMON1_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_INT_DATA", REG_SMC, 0x0380, &ixTHM_TMON0_INT_DATA[0], sizeof(ixTHM_TMON0_INT_DATA)/sizeof(ixTHM_TMON0_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_INT_DATA", REG_SMC, 0x0381, &ixTHM_TMON1_INT_DATA[0], sizeof(ixTHM_TMON1_INT_DATA)/sizeof(ixTHM_TMON1_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_DEBUG", REG_SMC, 0x03F0, &ixTHM_TMON0_DEBUG[0], sizeof(ixTHM_TMON0_DEBUG)/sizeof(ixTHM_TMON0_DEBUG[0]), 0, 0 },
+	{ "ixTHM_TMON1_DEBUG", REG_SMC, 0x03F1, &ixTHM_TMON1_DEBUG[0], sizeof(ixTHM_TMON1_DEBUG)/sizeof(ixTHM_TMON1_DEBUG[0]), 0, 0 },
+	{ "mmGPIOPAD_SW_INT_STAT", REG_MMIO, 0x05E4, &mmGPIOPAD_SW_INT_STAT[0], sizeof(mmGPIOPAD_SW_INT_STAT)/sizeof(mmGPIOPAD_SW_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_STRENGTH", REG_MMIO, 0x05E5, &mmGPIOPAD_STRENGTH[0], sizeof(mmGPIOPAD_STRENGTH)/sizeof(mmGPIOPAD_STRENGTH[0]), 0, 0 },
+	{ "mmGPIOPAD_MASK", REG_MMIO, 0x05E6, &mmGPIOPAD_MASK[0], sizeof(mmGPIOPAD_MASK)/sizeof(mmGPIOPAD_MASK[0]), 0, 0 },
+	{ "mmGPIOPAD_A", REG_MMIO, 0x05E7, &mmGPIOPAD_A[0], sizeof(mmGPIOPAD_A)/sizeof(mmGPIOPAD_A[0]), 0, 0 },
+	{ "mmGPIOPAD_EN", REG_MMIO, 0x05E8, &mmGPIOPAD_EN[0], sizeof(mmGPIOPAD_EN)/sizeof(mmGPIOPAD_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_Y", REG_MMIO, 0x05E9, &mmGPIOPAD_Y[0], sizeof(mmGPIOPAD_Y)/sizeof(mmGPIOPAD_Y[0]), 0, 0 },
+	{ "mmGPIOPAD_PINSTRAPS", REG_MMIO, 0x05EA, &mmGPIOPAD_PINSTRAPS[0], sizeof(mmGPIOPAD_PINSTRAPS)/sizeof(mmGPIOPAD_PINSTRAPS[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_EN", REG_MMIO, 0x05EB, &mmGPIOPAD_INT_STAT_EN[0], sizeof(mmGPIOPAD_INT_STAT_EN)/sizeof(mmGPIOPAD_INT_STAT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT", REG_MMIO, 0x05EC, &mmGPIOPAD_INT_STAT[0], sizeof(mmGPIOPAD_INT_STAT)/sizeof(mmGPIOPAD_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_AK", REG_MMIO, 0x05ED, &mmGPIOPAD_INT_STAT_AK[0], sizeof(mmGPIOPAD_INT_STAT_AK)/sizeof(mmGPIOPAD_INT_STAT_AK[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_EN", REG_MMIO, 0x05EE, &mmGPIOPAD_INT_EN[0], sizeof(mmGPIOPAD_INT_EN)/sizeof(mmGPIOPAD_INT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_TYPE", REG_MMIO, 0x05EF, &mmGPIOPAD_INT_TYPE[0], sizeof(mmGPIOPAD_INT_TYPE)/sizeof(mmGPIOPAD_INT_TYPE[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_POLARITY", REG_MMIO, 0x05F0, &mmGPIOPAD_INT_POLARITY[0], sizeof(mmGPIOPAD_INT_POLARITY)/sizeof(mmGPIOPAD_INT_POLARITY[0]), 0, 0 },
+	{ "mmGPIOPAD_EXTERN_TRIG_CNTL", REG_MMIO, 0x05F1, &mmGPIOPAD_EXTERN_TRIG_CNTL[0], sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL)/sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL[0]), 0, 0 },
+	{ "mmGPIOPAD_RCVR_SEL", REG_MMIO, 0x05F2, &mmGPIOPAD_RCVR_SEL[0], sizeof(mmGPIOPAD_RCVR_SEL)/sizeof(mmGPIOPAD_RCVR_SEL[0]), 0, 0 },
+	{ "mmGPIOPAD_PU_EN", REG_MMIO, 0x05F3, &mmGPIOPAD_PU_EN[0], sizeof(mmGPIOPAD_PU_EN)/sizeof(mmGPIOPAD_PU_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_PD_EN", REG_MMIO, 0x05F4, &mmGPIOPAD_PD_EN[0], sizeof(mmGPIOPAD_PD_EN)/sizeof(mmGPIOPAD_PD_EN[0]), 0, 0 },
+	{ "ixSMC_PC_C", REG_SMC, 0x80000370, &ixSMC_PC_C[0], sizeof(ixSMC_PC_C)/sizeof(ixSMC_PC_C[0]), 0, 0 },
diff --git a/src/lib/ip/smu700.c b/src/lib/ip/smu700.c
new file mode 100644
index 0000000..86d2426
--- /dev/null
+++ b/src/lib/ip/smu700.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "smu700_bits.i"
+
+static const struct umr_reg smu700_registers[] = {
+#include "smu700_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_smu700(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "smu700";
+	ip->no_regs = sizeof(smu700_registers)/sizeof(smu700_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(smu700_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, smu700_registers, sizeof(smu700_registers));
+	return ip;
+}
diff --git a/src/lib/ip/smu700_bits.i b/src/lib/ip/smu700_bits.i
new file mode 100644
index 0000000..4b6c7a5
--- /dev/null
+++ b/src/lib/ip/smu700_bits.i
@@ -0,0 +1,3277 @@
+static struct umr_bitfield mmCG_FPS_CNT[] = {
+	 { "FPS_CNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_1[] = {
+	 { "SystemFlags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_2[] = {
+	 { "GraphicsPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_3[] = {
+	 { "GraphicsPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_4[] = {
+	 { "GraphicsPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_5[] = {
+	 { "GraphicsPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_6[] = {
+	 { "GraphicsPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_7[] = {
+	 { "GraphicsPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_8[] = {
+	 { "GraphicsPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_9[] = {
+	 { "GraphicsPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_10[] = {
+	 { "GraphicsPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_11[] = {
+	 { "GioPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_12[] = {
+	 { "GioPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_13[] = {
+	 { "GioPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_14[] = {
+	 { "GioPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_15[] = {
+	 { "GioPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_16[] = {
+	 { "GioPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_17[] = {
+	 { "GioPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_18[] = {
+	 { "GioPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_19[] = {
+	 { "GioPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_20[] = {
+	 { "VceLevelCount", 0, 7, &umr_bitfield_default },
+	 { "UvdLevelCount", 8, 15, &umr_bitfield_default },
+	 { "GIOLevelCount", 16, 23, &umr_bitfield_default },
+	 { "GraphicsDpmLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_21[] = {
+	 { "FpsHighThreshold", 0, 15, &umr_bitfield_default },
+	 { "SamuLevelCount", 16, 23, &umr_bitfield_default },
+	 { "AcpLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_22[] = {
+	 { "GraphicsLevel_0_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_23[] = {
+	 { "GraphicsLevel_0_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_24[] = {
+	 { "GraphicsLevel_0_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_VidOffset", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_Vid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_25[] = {
+	 { "GraphicsLevel_0_SclkDid", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_PowerThrottle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_26[] = {
+	 { "GraphicsLevel_0_UpHyst", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_EnabledForActivity", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DisplayWatermark", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_27[] = {
+	 { "GraphicsLevel_0_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_VoltageDownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DownHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_28[] = {
+	 { "GraphicsLevel_0_reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_29[] = {
+	 { "GraphicsLevel_1_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_30[] = {
+	 { "GraphicsLevel_1_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_31[] = {
+	 { "GraphicsLevel_1_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_VidOffset", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_Vid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_32[] = {
+	 { "GraphicsLevel_1_SclkDid", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_PowerThrottle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_33[] = {
+	 { "GraphicsLevel_1_UpHyst", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_EnabledForActivity", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DisplayWatermark", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_34[] = {
+	 { "GraphicsLevel_1_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_VoltageDownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DownHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_35[] = {
+	 { "GraphicsLevel_1_reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_36[] = {
+	 { "GraphicsLevel_2_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_37[] = {
+	 { "GraphicsLevel_2_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_38[] = {
+	 { "GraphicsLevel_2_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_VidOffset", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_Vid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_39[] = {
+	 { "GraphicsLevel_2_SclkDid", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_PowerThrottle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_40[] = {
+	 { "GraphicsLevel_2_UpHyst", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_EnabledForActivity", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DisplayWatermark", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_41[] = {
+	 { "GraphicsLevel_2_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_VoltageDownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DownHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_42[] = {
+	 { "GraphicsLevel_2_reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_43[] = {
+	 { "GraphicsLevel_3_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_44[] = {
+	 { "GraphicsLevel_3_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_45[] = {
+	 { "GraphicsLevel_3_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_VidOffset", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_Vid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_46[] = {
+	 { "GraphicsLevel_3_SclkDid", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_PowerThrottle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_47[] = {
+	 { "GraphicsLevel_3_UpHyst", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_EnabledForActivity", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DisplayWatermark", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_48[] = {
+	 { "GraphicsLevel_3_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_VoltageDownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DownHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_49[] = {
+	 { "GraphicsLevel_3_reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_50[] = {
+	 { "GraphicsLevel_4_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_51[] = {
+	 { "GraphicsLevel_4_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_52[] = {
+	 { "GraphicsLevel_4_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_VidOffset", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_Vid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_53[] = {
+	 { "GraphicsLevel_4_SclkDid", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_PowerThrottle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_54[] = {
+	 { "GraphicsLevel_4_UpHyst", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_EnabledForActivity", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DisplayWatermark", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_55[] = {
+	 { "GraphicsLevel_4_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_VoltageDownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DownHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_56[] = {
+	 { "GraphicsLevel_4_reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_57[] = {
+	 { "GraphicsLevel_5_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_58[] = {
+	 { "GraphicsLevel_5_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_59[] = {
+	 { "GraphicsLevel_5_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_VidOffset", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_Vid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_60[] = {
+	 { "GraphicsLevel_5_SclkDid", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_PowerThrottle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_61[] = {
+	 { "GraphicsLevel_5_UpHyst", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_EnabledForActivity", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DisplayWatermark", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_62[] = {
+	 { "GraphicsLevel_5_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_VoltageDownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DownHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_63[] = {
+	 { "GraphicsLevel_5_reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_64[] = {
+	 { "GraphicsLevel_6_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_65[] = {
+	 { "GraphicsLevel_6_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_66[] = {
+	 { "GraphicsLevel_6_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_VidOffset", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_Vid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_67[] = {
+	 { "GraphicsLevel_6_SclkDid", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_PowerThrottle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_68[] = {
+	 { "GraphicsLevel_6_UpHyst", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_EnabledForActivity", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DisplayWatermark", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_69[] = {
+	 { "GraphicsLevel_6_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_VoltageDownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DownHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_70[] = {
+	 { "GraphicsLevel_6_reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_71[] = {
+	 { "GraphicsLevel_7_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_72[] = {
+	 { "GraphicsLevel_7_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_73[] = {
+	 { "GraphicsLevel_7_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_VidOffset", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_Vid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_74[] = {
+	 { "GraphicsLevel_7_SclkDid", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_PowerThrottle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_75[] = {
+	 { "GraphicsLevel_7_UpHyst", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_EnabledForActivity", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DisplayWatermark", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_76[] = {
+	 { "GraphicsLevel_7_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_VoltageDownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DownHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_77[] = {
+	 { "GraphicsLevel_7_reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_78[] = {
+	 { "ACPILevel_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_79[] = {
+	 { "ACPILevel_MinVddNb", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_80[] = {
+	 { "ACPILevel_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_81[] = {
+	 { "ACPILevel_DisplayWatermark", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_ForceNbPs1", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_GnbSlow", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_82[] = {
+	 { "ACPILevel_padding_2", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_padding_1", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_padding_0", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_83[] = {
+	 { "UvdLevel_0_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_84[] = {
+	 { "UvdLevel_0_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_85[] = {
+	 { "UvdLevel_0_DclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_VclkDivider", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVddNb", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_86[] = {
+	 { "UvdLevel_0_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_DClkBypassCntl", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_0_VClkBypassCntl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_87[] = {
+	 { "UvdLevel_1_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_88[] = {
+	 { "UvdLevel_1_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_89[] = {
+	 { "UvdLevel_1_DclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_VclkDivider", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVddNb", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_90[] = {
+	 { "UvdLevel_1_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_DClkBypassCntl", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_1_VClkBypassCntl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_91[] = {
+	 { "UvdLevel_2_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_92[] = {
+	 { "UvdLevel_2_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_93[] = {
+	 { "UvdLevel_2_DclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_VclkDivider", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVddNb", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_94[] = {
+	 { "UvdLevel_2_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_DClkBypassCntl", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_2_VClkBypassCntl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_95[] = {
+	 { "UvdLevel_3_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_96[] = {
+	 { "UvdLevel_3_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_97[] = {
+	 { "UvdLevel_3_DclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_VclkDivider", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVddNb", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_98[] = {
+	 { "UvdLevel_3_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_DClkBypassCntl", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_3_VClkBypassCntl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_99[] = {
+	 { "UvdLevel_4_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_100[] = {
+	 { "UvdLevel_4_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_101[] = {
+	 { "UvdLevel_4_DclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_VclkDivider", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVddNb", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_102[] = {
+	 { "UvdLevel_4_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_DClkBypassCntl", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_4_VClkBypassCntl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_103[] = {
+	 { "UvdLevel_5_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_104[] = {
+	 { "UvdLevel_5_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_105[] = {
+	 { "UvdLevel_5_DclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_VclkDivider", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVddNb", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_106[] = {
+	 { "UvdLevel_5_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_DClkBypassCntl", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_5_VClkBypassCntl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_107[] = {
+	 { "UvdLevel_6_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_108[] = {
+	 { "UvdLevel_6_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_109[] = {
+	 { "UvdLevel_6_DclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_VclkDivider", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVddNb", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_110[] = {
+	 { "UvdLevel_6_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_DClkBypassCntl", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_6_VClkBypassCntl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_111[] = {
+	 { "UvdLevel_7_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_112[] = {
+	 { "UvdLevel_7_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_113[] = {
+	 { "UvdLevel_7_DclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_VclkDivider", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVddNb", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_114[] = {
+	 { "UvdLevel_7_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_DClkBypassCntl", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_7_VClkBypassCntl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_115[] = {
+	 { "VceLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_116[] = {
+	 { "VceLevel_0_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_0_Divider", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_117[] = {
+	 { "VceLevel_0_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_118[] = {
+	 { "VceLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_119[] = {
+	 { "VceLevel_1_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_1_Divider", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_120[] = {
+	 { "VceLevel_1_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_121[] = {
+	 { "VceLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_122[] = {
+	 { "VceLevel_2_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_2_Divider", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_123[] = {
+	 { "VceLevel_2_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_124[] = {
+	 { "VceLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_125[] = {
+	 { "VceLevel_3_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_3_Divider", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_126[] = {
+	 { "VceLevel_3_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_127[] = {
+	 { "VceLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_128[] = {
+	 { "VceLevel_4_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_4_Divider", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_129[] = {
+	 { "VceLevel_4_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_130[] = {
+	 { "VceLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_131[] = {
+	 { "VceLevel_5_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_5_Divider", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_132[] = {
+	 { "VceLevel_5_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_133[] = {
+	 { "VceLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_134[] = {
+	 { "VceLevel_6_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_6_Divider", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_135[] = {
+	 { "VceLevel_6_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_136[] = {
+	 { "VceLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_137[] = {
+	 { "VceLevel_7_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_7_Divider", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_138[] = {
+	 { "VceLevel_7_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_139[] = {
+	 { "AcpLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_140[] = {
+	 { "AcpLevel_0_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_0_Divider", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_141[] = {
+	 { "AcpLevel_0_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_142[] = {
+	 { "AcpLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_143[] = {
+	 { "AcpLevel_1_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_1_Divider", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_144[] = {
+	 { "AcpLevel_1_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_145[] = {
+	 { "AcpLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_146[] = {
+	 { "AcpLevel_2_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_2_Divider", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_147[] = {
+	 { "AcpLevel_2_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_148[] = {
+	 { "AcpLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_149[] = {
+	 { "AcpLevel_3_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_3_Divider", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_150[] = {
+	 { "AcpLevel_3_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_151[] = {
+	 { "AcpLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_152[] = {
+	 { "AcpLevel_4_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_4_Divider", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_153[] = {
+	 { "AcpLevel_4_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_154[] = {
+	 { "AcpLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_155[] = {
+	 { "AcpLevel_5_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_5_Divider", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_156[] = {
+	 { "AcpLevel_5_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_157[] = {
+	 { "AcpLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_158[] = {
+	 { "AcpLevel_6_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_6_Divider", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_159[] = {
+	 { "AcpLevel_6_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_160[] = {
+	 { "AcpLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_161[] = {
+	 { "AcpLevel_7_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_7_Divider", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_162[] = {
+	 { "AcpLevel_7_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_163[] = {
+	 { "SamuLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_164[] = {
+	 { "SamuLevel_0_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_0_Divider", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_165[] = {
+	 { "SamuLevel_0_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_166[] = {
+	 { "SamuLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_167[] = {
+	 { "SamuLevel_1_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_1_Divider", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_168[] = {
+	 { "SamuLevel_1_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_169[] = {
+	 { "SamuLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_170[] = {
+	 { "SamuLevel_2_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_2_Divider", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_171[] = {
+	 { "SamuLevel_2_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_172[] = {
+	 { "SamuLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_173[] = {
+	 { "SamuLevel_3_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_3_Divider", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_174[] = {
+	 { "SamuLevel_3_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_175[] = {
+	 { "SamuLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_176[] = {
+	 { "SamuLevel_4_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_4_Divider", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_177[] = {
+	 { "SamuLevel_4_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_178[] = {
+	 { "SamuLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_179[] = {
+	 { "SamuLevel_5_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_5_Divider", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_180[] = {
+	 { "SamuLevel_5_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_181[] = {
+	 { "SamuLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_182[] = {
+	 { "SamuLevel_6_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_6_Divider", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_183[] = {
+	 { "SamuLevel_6_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_184[] = {
+	 { "SamuLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_185[] = {
+	 { "SamuLevel_7_ClkBypassCntl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_7_Divider", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_186[] = {
+	 { "SamuLevel_7_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_187[] = {
+	 { "SamuBootLevel", 0, 7, &umr_bitfield_default },
+	 { "AcpBootLevel", 8, 15, &umr_bitfield_default },
+	 { "VceBootLevel", 16, 23, &umr_bitfield_default },
+	 { "UvdBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_188[] = {
+	 { "SAMUInterval", 0, 7, &umr_bitfield_default },
+	 { "ACPInterval", 8, 15, &umr_bitfield_default },
+	 { "VCEInterval", 16, 23, &umr_bitfield_default },
+	 { "UVDInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_189[] = {
+	 { "GraphicsVoltageChangeEnable", 0, 7, &umr_bitfield_default },
+	 { "GraphicsThermThrottleEnable", 8, 15, &umr_bitfield_default },
+	 { "GraphicsInterval", 16, 23, &umr_bitfield_default },
+	 { "GraphicsBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_190[] = {
+	 { "FpsLowThreshold", 0, 15, &umr_bitfield_default },
+	 { "GraphicsClkSlowDivider", 16, 23, &umr_bitfield_default },
+	 { "GraphicsClkSlowEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_191[] = {
+	 { "DisplayCac", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFIRMWARE_FLAGS[] = {
+	 { "INTERRUPTS_ENABLED", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 23, &umr_bitfield_default },
+	 { "TEST_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTEMPERATURE_READ_ADDR[] = {
+	 { "CSR_ADDR", 0, 5, &umr_bitfield_default },
+	 { "TCEN_ID", 6, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_GNB_TEMP[] = {
+	 { "TEMP", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_GLOBAL_TEMP[] = {
+	 { "TEMP", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFEATURE_STATUS[] = {
+	 { "SCLK_DPM_ON", 0, 0, &umr_bitfield_default },
+	 { "MCLK_DPM_ON", 1, 1, &umr_bitfield_default },
+	 { "LCLK_DPM_ON", 2, 2, &umr_bitfield_default },
+	 { "UVD_DPM_ON", 3, 3, &umr_bitfield_default },
+	 { "VCE_DPM_ON", 4, 4, &umr_bitfield_default },
+	 { "ACP_DPM_ON", 5, 5, &umr_bitfield_default },
+	 { "SAMU_DPM_ON", 6, 6, &umr_bitfield_default },
+	 { "PCIE_DPM_ON", 7, 7, &umr_bitfield_default },
+	 { "BAPM_ON", 8, 8, &umr_bitfield_default },
+	 { "LPMX_ON", 9, 9, &umr_bitfield_default },
+	 { "NBDPM_ON", 10, 10, &umr_bitfield_default },
+	 { "LHTC_ON", 11, 11, &umr_bitfield_default },
+	 { "VPC_ON", 12, 12, &umr_bitfield_default },
+	 { "VOLTAGE_CONTROLLER_ON", 13, 13, &umr_bitfield_default },
+	 { "TDC_LIMIT_ON", 14, 14, &umr_bitfield_default },
+	 { "GPU_CAC_ON", 15, 15, &umr_bitfield_default },
+	 { "AVS_ON", 16, 16, &umr_bitfield_default },
+	 { "SPMI_ON", 17, 17, &umr_bitfield_default },
+	 { "SCLK_DPM_FORCED", 18, 18, &umr_bitfield_default },
+	 { "MCLK_DPM_FORCED", 19, 19, &umr_bitfield_default },
+	 { "LCLK_DPM_FORCED", 20, 20, &umr_bitfield_default },
+	 { "PCIE_DPM_FORCED", 21, 21, &umr_bitfield_default },
+	 { "CLK_MON_ON", 22, 22, &umr_bitfield_default },
+	 { "RESERVED", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PLL_RECONF[] = {
+	 { "RECONF_WAIT", 0, 7, &umr_bitfield_default },
+	 { "RECONF_WRAPPER", 8, 15, &umr_bitfield_default },
+	 { "SB_RELOCATE_EN", 16, 23, &umr_bitfield_default },
+	 { "SB_NEW_PORT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_INTERVAL_CNTL_0[] = {
+	 { "LCLK_DPM", 0, 7, &umr_bitfield_default },
+	 { "THERMAL_CNTL", 8, 15, &umr_bitfield_default },
+	 { "VOLTAGE_CNTL", 16, 23, &umr_bitfield_default },
+	 { "LOADLINE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_INTERVAL_CNTL_1[] = {
+	 { "NB_DPM", 0, 7, &umr_bitfield_default },
+	 { "AVS_PERIOD", 8, 15, &umr_bitfield_default },
+	 { "PKGPWR_PERIOD", 16, 23, &umr_bitfield_default },
+	 { "TDP_CNTL", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_INTERVAL_CNTL_2[] = {
+	 { "BAPM_PERIOD", 0, 7, &umr_bitfield_default },
+	 { "HTC_PERIOD", 8, 15, &umr_bitfield_default },
+	 { "TDC_PERIOD", 16, 23, &umr_bitfield_default },
+	 { "LPMX_PERIOD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVPC_INTERVAL_CNTL[] = {
+	 { "VPC_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDISP_PHY_TDP_LIMIT[] = {
+	 { "DisplayPhyTdpLimit", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFCH_PWR_CREDIT[] = {
+	 { "FchPwrCredit", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPKGPWR_MV_AVG[] = {
+	 { "Avg_Pkg_Pwr", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPACKAGE_POWER[] = {
+	 { "Pkg_power", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPKG_PWR_CNTL[] = {
+	 { "CpcGpuPerfPri", 0, 0, &umr_bitfield_default },
+	 { "PkgPwrLimit", 1, 16, &umr_bitfield_default },
+	 { "FchPwrCreditScale", 17, 22, &umr_bitfield_default },
+	 { "PkgHystCoeff", 23, 28, &umr_bitfield_default },
+	 { "RESERVED", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPKG_PWR_STATUS[] = {
+	 { "GnbMinLimitSetFlag", 0, 0, &umr_bitfield_default },
+	 { "PstateLimitSetFlag", 1, 1, &umr_bitfield_default },
+	 { "PkgPwrLimit_base", 2, 17, &umr_bitfield_default },
+	 { "RESERVED", 18, 23, &umr_bitfield_default },
+	 { "PkgPwr_MAWt", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDISP_PHY_CONFIG[] = {
+	 { "Corner", 0, 7, &umr_bitfield_default },
+	 { "DispPHYConfig", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGPU_TDP_LIMIT[] = {
+	 { "Gpu_Tdp_Limit", 0, 15, &umr_bitfield_default },
+	 { "Reserved", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXT_API_IN_DATA_0_0[] = {
+	 { "byte0", 0, 7, &umr_bitfield_default },
+	 { "byte1", 8, 15, &umr_bitfield_default },
+	 { "byte2", 16, 23, &umr_bitfield_default },
+	 { "byte3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXT_API_IN_DATA_0_1[] = {
+	 { "byte0", 0, 7, &umr_bitfield_default },
+	 { "byte1", 8, 15, &umr_bitfield_default },
+	 { "byte2", 16, 23, &umr_bitfield_default },
+	 { "byte3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXT_API_IN_DATA_0_2[] = {
+	 { "byte0", 0, 7, &umr_bitfield_default },
+	 { "byte1", 8, 15, &umr_bitfield_default },
+	 { "byte2", 16, 23, &umr_bitfield_default },
+	 { "byte3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXT_API_IN_DATA_0_3[] = {
+	 { "byte0", 0, 7, &umr_bitfield_default },
+	 { "byte1", 8, 15, &umr_bitfield_default },
+	 { "byte2", 16, 23, &umr_bitfield_default },
+	 { "byte3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXT_API_OUT_DATA_0_0[] = {
+	 { "byte0", 0, 7, &umr_bitfield_default },
+	 { "byte1", 8, 15, &umr_bitfield_default },
+	 { "byte2", 16, 23, &umr_bitfield_default },
+	 { "byte3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXT_API_OUT_DATA_0_1[] = {
+	 { "byte0", 0, 7, &umr_bitfield_default },
+	 { "byte1", 8, 15, &umr_bitfield_default },
+	 { "byte2", 16, 23, &umr_bitfield_default },
+	 { "byte3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXT_API_OUT_DATA_0_2[] = {
+	 { "byte0", 0, 7, &umr_bitfield_default },
+	 { "byte1", 8, 15, &umr_bitfield_default },
+	 { "byte2", 16, 23, &umr_bitfield_default },
+	 { "byte3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixEXT_API_OUT_DATA_0_3[] = {
+	 { "byte0", 0, 7, &umr_bitfield_default },
+	 { "byte1", 8, 15, &umr_bitfield_default },
+	 { "byte2", 16, 23, &umr_bitfield_default },
+	 { "byte3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_1[] = {
+	 { "RefClockFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_2[] = {
+	 { "PmTimerPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_3[] = {
+	 { "FeatureEnables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_4[] = {
+	 { "HandshakeDisables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_5[] = {
+	 { "DisplayPhy4Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy3Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy2Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy1Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_6[] = {
+	 { "DisplayPhy8Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy7Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy6Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy5Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_7[] = {
+	 { "AverageGraphicsActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_8[] = {
+	 { "AverageMemoryActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_9[] = {
+	 { "AverageGioActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_10[] = {
+	 { "PCIeDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "LClkDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "MClkDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "SClkDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_11[] = {
+	 { "VCEDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "ACPDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "SAMUDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "UVDDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_12[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_13[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_14[] = {
+	 { "Reserved_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_15[] = {
+	 { "Reserved_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_16[] = {
+	 { "Reserved_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_17[] = {
+	 { "Reserved_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_18[] = {
+	 { "Reserved_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_19[] = {
+	 { "Reserved_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_20[] = {
+	 { "Reserved_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_21[] = {
+	 { "Reserved_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBAPM_PARAMETERS[] = {
+	 { "MaxPwrCpu_1", 0, 7, &umr_bitfield_default },
+	 { "NomPwrCpu_1", 8, 15, &umr_bitfield_default },
+	 { "MaxPwrCpu_0", 16, 23, &umr_bitfield_default },
+	 { "NomPwrCpu_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBAPM_PARAMETERS_2[] = {
+	 { "MaxPwrGpu", 0, 15, &umr_bitfield_default },
+	 { "NomPwrGpu", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBAPM_PARAMETERS_3[] = {
+	 { "TjOffset", 0, 7, &umr_bitfield_default },
+	 { "EnergyCntNorm", 8, 17, &umr_bitfield_default },
+	 { "Reserved", 18, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBAPM_PARAMETERS_4[] = {
+	 { "MinPwrGpu", 0, 15, &umr_bitfield_default },
+	 { "MidPwrCpu_1", 16, 23, &umr_bitfield_default },
+	 { "MidPwrCpu_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_SVI_TELEMETRY[] = {
+	 { "Iddspike_OCP", 0, 15, &umr_bitfield_default },
+	 { "IddNbspike_OCP", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixBAPM_STATUS[] = {
+	 { "THROTTLE", 0, 7, &umr_bitfield_default },
+	 { "THROTTLE_LAST", 8, 15, &umr_bitfield_default },
+	 { "COUNT_CORE1", 16, 23, &umr_bitfield_default },
+	 { "COUNT_CORE0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_HTC_STATUS[] = {
+	 { "HTC_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "Reserved", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_VPC_STATUS[] = {
+	 { "AllCpuIdleLast", 0, 0, &umr_bitfield_default },
+	 { "Reserved", 1, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixENTITY_TEMPERATURES_1[] = {
+	 { "CORE0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixENTITY_TEMPERATURES_2[] = {
+	 { "CORE1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixENTITY_TEMPERATURES_3[] = {
+	 { "GPU", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCU_POWER[] = {
+	 { "CU0_POWER", 0, 15, &umr_bitfield_default },
+	 { "CU1_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGPU_POWER[] = {
+	 { "IGPU_POWER", 0, 15, &umr_bitfield_default },
+	 { "DGPU_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixNTE_POWER[] = {
+	 { "NTE0_POWER", 0, 15, &umr_bitfield_default },
+	 { "NTE1_POWER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_STATUS[] = {
+	 { "VDD_Boost", 0, 7, &umr_bitfield_default },
+	 { "VDD_Throttle", 8, 15, &umr_bitfield_default },
+	 { "VDDNB_Boost", 16, 23, &umr_bitfield_default },
+	 { "VDDNB_Throttle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_MV_AVERAGE[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDNB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_CONFIG[] = {
+	 { "Enable_VPC_Accumulators", 0, 0, &umr_bitfield_default },
+	 { "Enable_BAPM", 1, 1, &umr_bitfield_default },
+	 { "Enable_TDC_Limit", 2, 2, &umr_bitfield_default },
+	 { "Enable_LPMx", 3, 3, &umr_bitfield_default },
+	 { "Enable_HTC_Limit", 4, 4, &umr_bitfield_default },
+	 { "Enable_NBDPM", 5, 5, &umr_bitfield_default },
+	 { "Enable_LoadLine", 6, 6, &umr_bitfield_default },
+	 { "Reserved", 7, 15, &umr_bitfield_default },
+	 { "Override_VPC_Current", 16, 16, &umr_bitfield_default },
+	 { "Reserved1", 17, 18, &umr_bitfield_default },
+	 { "Override_Calc_Temp", 19, 19, &umr_bitfield_default },
+	 { "Enable_Hybrid_Boost", 20, 20, &umr_bitfield_default },
+	 { "Reserved2", 21, 23, &umr_bitfield_default },
+	 { "PSTATE_AllCpusIdle", 24, 26, &umr_bitfield_default },
+	 { "NBPSTATE_AllCpusIdle", 27, 27, &umr_bitfield_default },
+	 { "Reserved3", 28, 28, &umr_bitfield_default },
+	 { "SVI_Mode", 29, 29, &umr_bitfield_default },
+	 { "Enable_PDM", 30, 30, &umr_bitfield_default },
+	 { "Enable_PKG_PWR_LIMIT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTE0_TEMPERATURE_READ_ADDR[] = {
+	 { "CSR_ADDR", 0, 5, &umr_bitfield_default },
+	 { "TCEN_ID", 6, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTE1_TEMPERATURE_READ_ADDR[] = {
+	 { "CSR_ADDR", 0, 5, &umr_bitfield_default },
+	 { "TCEN_ID", 6, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTE2_TEMPERATURE_READ_ADDR[] = {
+	 { "CSR_ADDR", 0, 5, &umr_bitfield_default },
+	 { "TCEN_ID", 6, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixNB_DPM_CONFIG_1[] = {
+	 { "Dpm0PgNbPsLo", 0, 7, &umr_bitfield_default },
+	 { "Dpm0PgNbPsHi", 8, 15, &umr_bitfield_default },
+	 { "DpmXNbPsLo", 16, 23, &umr_bitfield_default },
+	 { "DpmXNbPsHi", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixNB_DPM_CONFIG_2[] = {
+	 { "Hysteresis", 0, 7, &umr_bitfield_default },
+	 { "SkipPG", 8, 15, &umr_bitfield_default },
+	 { "SkipDPM0", 16, 23, &umr_bitfield_default },
+	 { "EnablePSI1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixNB_DPM_CONFIG_3[] = {
+	 { "RESERVED", 0, 23, &umr_bitfield_default },
+	 { "EnableDpmPstatePoll", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_IDD_OVERRIDE[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDNB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAVS_CONFIG[] = {
+	 { "AvsEnabledForPstates", 0, 7, &umr_bitfield_default },
+	 { "AvsOverrideEnabled", 8, 8, &umr_bitfield_default },
+	 { "AvsPsmTempCompensation", 9, 9, &umr_bitfield_default },
+	 { "RESERVED1", 10, 15, &umr_bitfield_default },
+	 { "AvsOverrideOffset", 16, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_VRM_LIMIT[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDNB", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCU0_PSM_CONFIG[] = {
+	 { "Psm4", 0, 7, &umr_bitfield_default },
+	 { "Psm3", 8, 15, &umr_bitfield_default },
+	 { "Psm2", 16, 23, &umr_bitfield_default },
+	 { "Psm1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCU1_PSM_CONFIG[] = {
+	 { "Psm4", 0, 7, &umr_bitfield_default },
+	 { "Psm3", 8, 15, &umr_bitfield_default },
+	 { "Psm2", 16, 23, &umr_bitfield_default },
+	 { "Psm1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_CONFIG[] = {
+	 { "SpmiTestCode", 0, 7, &umr_bitfield_default },
+	 { "SpmiTestData", 8, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SMC_CHAIN_ADDR[] = {
+	 { "Addr", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_STATUS[] = {
+	 { "OpDone", 0, 7, &umr_bitfield_default },
+	 { "OpFailed", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAVSNB_CONFIG[] = {
+	 { "AvsEnabledForPstates", 0, 3, &umr_bitfield_default },
+	 { "RESERVED0", 4, 7, &umr_bitfield_default },
+	 { "AvsOverrideEnabled", 8, 8, &umr_bitfield_default },
+	 { "AvsPsmTempCompensation", 9, 9, &umr_bitfield_default },
+	 { "RESERVED1", 10, 15, &umr_bitfield_default },
+	 { "AvsOverrideOffset", 16, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixHTC_CONFIG[] = {
+	 { "CSR_ADDR", 0, 5, &umr_bitfield_default },
+	 { "TCEN_ID", 6, 9, &umr_bitfield_default },
+	 { "HTC_ACTIVE_PSTATE_LIMIT", 16, 23, &umr_bitfield_default },
+	 { "Reserved", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAVS_CU0_TEMPERATURE_SENSOR[] = {
+	 { "CsrAddr", 0, 5, &umr_bitfield_default },
+	 { "TcenID", 6, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAVS_CU1_TEMPERATURE_SENSOR[] = {
+	 { "CsrAddr", 0, 5, &umr_bitfield_default },
+	 { "TcenID", 6, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAVS_GNB_TEMPERATURE_SENSOR[] = {
+	 { "CsrAddr", 0, 5, &umr_bitfield_default },
+	 { "TcenID", 6, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixAVS_UNB_TEMPERATURE_SENSOR[] = {
+	 { "CsrAddr", 0, 5, &umr_bitfield_default },
+	 { "TcenID", 6, 9, &umr_bitfield_default },
+	 { "RESERVED", 10, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MONITOR_PORT80_MMIO_ADDR[] = {
+	 { "MMIO_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MONITOR_PORT80_MEMBASE_HI[] = {
+	 { "MEMORY_BASE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MONITOR_PORT80_MEMBASE_LO[] = {
+	 { "MEMORY_BASE_LO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MONITOR_PORT80_MEMSETUP[] = {
+	 { "MEMORY_POSITION", 0, 15, &umr_bitfield_default },
+	 { "MEMORY_BUFFER_SIZE", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MONITOR_PORT80_CTRL[] = {
+	 { "ENABLE_DRAM_SHADOW", 0, 0, &umr_bitfield_default },
+	 { "ENABLE_CSR_SHADOW", 1, 1, &umr_bitfield_default },
+	 { "RESERVED", 2, 15, &umr_bitfield_default },
+	 { "POLLING_INTERVAL", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_TCEN_ALIVE[] = {
+	 { "CORE_TCEN_ID", 0, 7, &umr_bitfield_default },
+	 { "GNB_TCEN_ID", 8, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPDM_STATUS[] = {
+	 { "PDM_ENABLED", 0, 0, &umr_bitfield_default },
+	 { "NewCpcTdpLimit", 1, 16, &umr_bitfield_default },
+	 { "NoofConnectedCores", 17, 20, &umr_bitfield_default },
+	 { "Reserved", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPDM_CNTL_1[] = {
+	 { "BaseCoreTdpLimit0", 0, 7, &umr_bitfield_default },
+	 { "BaseCoreTdpLimit1", 8, 15, &umr_bitfield_default },
+	 { "BaseCoreTdpLimit2", 16, 23, &umr_bitfield_default },
+	 { "GpuPdmMult", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPDM_CNTL_2[] = {
+	 { "HeatPdmTc", 0, 7, &umr_bitfield_default },
+	 { "CoolPdmTc", 8, 15, &umr_bitfield_default },
+	 { "GpuPdmTc", 16, 23, &umr_bitfield_default },
+	 { "GpuActThr", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPDM_CNTL_3[] = {
+	 { "HeatPdmThr1", 0, 7, &umr_bitfield_default },
+	 { "HeatPdmThr2", 8, 15, &umr_bitfield_default },
+	 { "CoolPdmThr1", 16, 23, &umr_bitfield_default },
+	 { "CoolPdmThr2", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_1[] = {
+	 { "BapmPstateVid_3", 0, 7, &umr_bitfield_default },
+	 { "BapmPstateVid_2", 8, 15, &umr_bitfield_default },
+	 { "BapmPstateVid_1", 16, 23, &umr_bitfield_default },
+	 { "BapmPstateVid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_2[] = {
+	 { "BapmPstateVid_7", 0, 7, &umr_bitfield_default },
+	 { "BapmPstateVid_6", 8, 15, &umr_bitfield_default },
+	 { "BapmPstateVid_5", 16, 23, &umr_bitfield_default },
+	 { "BapmPstateVid_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_3[] = {
+	 { "BapmVddNbVidHiSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddNbVidHiSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddNbVidHiSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddNbVidHiSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_4[] = {
+	 { "BapmVddNbVidLoSidd_2", 0, 7, &umr_bitfield_default },
+	 { "BapmVddNbVidLoSidd_1", 8, 15, &umr_bitfield_default },
+	 { "BapmVddNbVidLoSidd_0", 16, 23, &umr_bitfield_default },
+	 { "BapmVddNbVidHiSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_5[] = {
+	 { "CpuIdModel", 0, 7, &umr_bitfield_default },
+	 { "SviLoadLineEn", 8, 15, &umr_bitfield_default },
+	 { "BapmVddNbVidLoSidd_4", 16, 23, &umr_bitfield_default },
+	 { "BapmVddNbVidLoSidd_3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_6[] = {
+	 { "SviLoadLineTrimVddNb", 0, 7, &umr_bitfield_default },
+	 { "SviLoadLineTrimVdd", 8, 15, &umr_bitfield_default },
+	 { "SviLoadLineVddNb", 16, 23, &umr_bitfield_default },
+	 { "SviLoadLineVdd", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_7[] = {
+	 { "BAPMTI_TjOffset_0", 0, 15, &umr_bitfield_default },
+	 { "SviLoadLineOffsetVddNb", 16, 23, &umr_bitfield_default },
+	 { "SviLoadLineOffsetVdd", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_8[] = {
+	 { "BAPMTI_TjOffset_2", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_TjOffset_1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_9[] = {
+	 { "BAPMTI_TjHyst_1", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_TjHyst_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_10[] = {
+	 { "BAPMTI_TjMax_1", 0, 7, &umr_bitfield_default },
+	 { "BAPMTI_TjMax_0", 8, 15, &umr_bitfield_default },
+	 { "BAPMTI_GpuTjHyst", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_11[] = {
+	 { "LhtcTmpLmt", 0, 7, &umr_bitfield_default },
+	 { "LhtcPstateLimit", 8, 15, &umr_bitfield_default },
+	 { "LhtcHystLmt", 16, 23, &umr_bitfield_default },
+	 { "BAPMTI_GpuTjMax", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_12[] = {
+	 { "MaxPwrCpu_1", 0, 7, &umr_bitfield_default },
+	 { "MaxPwrCpu_0", 8, 15, &umr_bitfield_default },
+	 { "NomPwrCpu_1", 16, 23, &umr_bitfield_default },
+	 { "NomPwrCpu_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_13[] = {
+	 { "NomPwrGpu", 0, 15, &umr_bitfield_default },
+	 { "MidPwrCpu_1", 16, 23, &umr_bitfield_default },
+	 { "MidPwrCpu_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_14[] = {
+	 { "MinPwrGpu", 0, 15, &umr_bitfield_default },
+	 { "MaxPwrGpu", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_15[] = {
+	 { "PCIe3PhyOffset", 0, 7, &umr_bitfield_default },
+	 { "PCIe2PhyOffset", 8, 15, &umr_bitfield_default },
+	 { "PCIe1PhyOffset", 16, 23, &umr_bitfield_default },
+	 { "MidPwrTempHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_16[] = {
+	 { "TDC_VDD_PkgLimit", 0, 15, &umr_bitfield_default },
+	 { "DCE2PhyOffset", 16, 23, &umr_bitfield_default },
+	 { "DCE1PhyOffset", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_17[] = {
+	 { "TDC_VDDNB_ThrottleReleaseLimitPerc", 0, 7, &umr_bitfield_default },
+	 { "TDC_VDD_ThrottleReleaseLimitPerc", 8, 15, &umr_bitfield_default },
+	 { "TDC_VDDNB_PkgLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_18[] = {
+	 { "TdcWaterfallCtl", 0, 7, &umr_bitfield_default },
+	 { "TdpAgeRate", 8, 15, &umr_bitfield_default },
+	 { "TdpAgeValue", 16, 23, &umr_bitfield_default },
+	 { "TDC_MAWt", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_19[] = {
+	 { "BapmLhtcCap", 0, 7, &umr_bitfield_default },
+	 { "BapmFuseOverride", 8, 15, &umr_bitfield_default },
+	 { "SmuCoolingIndex", 16, 23, &umr_bitfield_default },
+	 { "SmuSocIndex", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_20[] = {
+	 { "SamClkDid_3", 0, 7, &umr_bitfield_default },
+	 { "SamClkDid_2", 8, 15, &umr_bitfield_default },
+	 { "SamClkDid_1", 16, 23, &umr_bitfield_default },
+	 { "SamClkDid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_21[] = {
+	 { "AmbientTempBase", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureMax", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureMin", 16, 23, &umr_bitfield_default },
+	 { "SamClkDid_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_22[] = {
+	 { "LPMLTemperatureScaler_3", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_2", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_1", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_23[] = {
+	 { "LPMLTemperatureScaler_7", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_6", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_5", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_24[] = {
+	 { "LPMLTemperatureScaler_11", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_10", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_9", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_25[] = {
+	 { "LPMLTemperatureScaler_15", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_14", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_13", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_26[] = {
+	 { "GnbLPML_3", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_2", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_1", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_27[] = {
+	 { "GnbLPML_7", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_6", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_5", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_28[] = {
+	 { "GnbLPML_11", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_10", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_9", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_29[] = {
+	 { "GnbLPML_15", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_14", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_13", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_30[] = {
+	 { "NbVid_3", 0, 7, &umr_bitfield_default },
+	 { "NbVid_2", 8, 15, &umr_bitfield_default },
+	 { "NbVid_1", 16, 23, &umr_bitfield_default },
+	 { "NbVid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_31[] = {
+	 { "CpuVid_3", 0, 7, &umr_bitfield_default },
+	 { "CpuVid_2", 8, 15, &umr_bitfield_default },
+	 { "CpuVid_1", 16, 23, &umr_bitfield_default },
+	 { "CpuVid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_32[] = {
+	 { "CpuVid_7", 0, 7, &umr_bitfield_default },
+	 { "CpuVid_6", 8, 15, &umr_bitfield_default },
+	 { "CpuVid_5", 16, 23, &umr_bitfield_default },
+	 { "CpuVid_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_33[] = {
+	 { "Tdp2Watt", 0, 15, &umr_bitfield_default },
+	 { "GnbLPMLMinVid", 16, 23, &umr_bitfield_default },
+	 { "GnbLPMLMaxVid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_34[] = {
+	 { "Lpml_3", 0, 7, &umr_bitfield_default },
+	 { "Lpml_2", 8, 15, &umr_bitfield_default },
+	 { "Lpml_1", 16, 23, &umr_bitfield_default },
+	 { "Lpml_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_35[] = {
+	 { "Lpml_7", 0, 7, &umr_bitfield_default },
+	 { "Lpml_6", 8, 15, &umr_bitfield_default },
+	 { "Lpml_5", 16, 23, &umr_bitfield_default },
+	 { "Lpml_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_36[] = {
+	 { "Lpmv_3", 0, 7, &umr_bitfield_default },
+	 { "Lpmv_2", 8, 15, &umr_bitfield_default },
+	 { "Lpmv_1", 16, 23, &umr_bitfield_default },
+	 { "Lpmv_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_37[] = {
+	 { "Lpmv_7", 0, 7, &umr_bitfield_default },
+	 { "Lpmv_6", 8, 15, &umr_bitfield_default },
+	 { "Lpmv_5", 16, 23, &umr_bitfield_default },
+	 { "Lpmv_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_38[] = {
+	 { "EClkDid_3", 0, 7, &umr_bitfield_default },
+	 { "EClkDid_2", 8, 15, &umr_bitfield_default },
+	 { "EClkDid_1", 16, 23, &umr_bitfield_default },
+	 { "EClkDid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_39[] = {
+	 { "CoreDis", 0, 7, &umr_bitfield_default },
+	 { "C6CstatePower", 8, 15, &umr_bitfield_default },
+	 { "BoostLock", 16, 23, &umr_bitfield_default },
+	 { "EClkDid_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_40[] = {
+	 { "BapmVddNbBaseLeakageLoSidd", 0, 15, &umr_bitfield_default },
+	 { "BapmVddNbBaseLeakageHiSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_41[] = {
+	 { "VddNbVid_3", 0, 7, &umr_bitfield_default },
+	 { "VddNbVid_2", 8, 15, &umr_bitfield_default },
+	 { "VddNbVid_1", 16, 23, &umr_bitfield_default },
+	 { "VddNbVid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_42[] = {
+	 { "VddNbVidOffset_2", 0, 7, &umr_bitfield_default },
+	 { "VddNbVidOffset_1", 8, 15, &umr_bitfield_default },
+	 { "VddNbVidOffset_0", 16, 23, &umr_bitfield_default },
+	 { "VddNbVid_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_43[] = {
+	 { "BapmDisable", 0, 7, &umr_bitfield_default },
+	 { "CoreTdpLimit0", 8, 15, &umr_bitfield_default },
+	 { "VddNbVidOffset_4", 16, 23, &umr_bitfield_default },
+	 { "VddNbVidOffset_3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_44[] = {
+	 { "LpmlL2_3", 0, 7, &umr_bitfield_default },
+	 { "LpmlL2_2", 8, 15, &umr_bitfield_default },
+	 { "LpmlL2_1", 16, 23, &umr_bitfield_default },
+	 { "LpmlL2_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_45[] = {
+	 { "LpmlL2_7", 0, 7, &umr_bitfield_default },
+	 { "LpmlL2_6", 8, 15, &umr_bitfield_default },
+	 { "LpmlL2_5", 16, 23, &umr_bitfield_default },
+	 { "LpmlL2_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_46[] = {
+	 { "CoolPdmTc", 0, 7, &umr_bitfield_default },
+	 { "BaseCpcTdpLimit2", 8, 15, &umr_bitfield_default },
+	 { "BaseCpcTdpLimit1", 16, 23, &umr_bitfield_default },
+	 { "BaseCpcTdpLimit", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_47[] = {
+	 { "CoolPdmThr2", 0, 7, &umr_bitfield_default },
+	 { "CoolPdmThr1", 8, 15, &umr_bitfield_default },
+	 { "GpuPdmTc", 16, 23, &umr_bitfield_default },
+	 { "HeatPdmTc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_48[] = {
+	 { "PkgPwr_MAWt", 0, 7, &umr_bitfield_default },
+	 { "GpuActThr", 8, 15, &umr_bitfield_default },
+	 { "HeatPdmThr2", 16, 23, &umr_bitfield_default },
+	 { "HeatPdmThr1", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_49[] = {
+	 { "SocketTdp", 0, 15, &umr_bitfield_default },
+	 { "GpuPdmMult", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_50[] = {
+	 { "Reserved2", 0, 15, &umr_bitfield_default },
+	 { "Reserved1", 16, 23, &umr_bitfield_default },
+	 { "NumBoostStates", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_51[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_52[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_53[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_54[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_55[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_56[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_57[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_58[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_59[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_60[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_61[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_62[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_63[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_64[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_65[] = {
+	 { "FUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_0_CNTL_0[] = {
+	 { "LOW_VOLTAGE_REQ_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "VID", 8, 15, &umr_bitfield_default },
+	 { "CLK_DIVIDER", 16, 23, &umr_bitfield_default },
+	 { "STATE_VALID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_0_CNTL_1[] = {
+	 { "MIN_VDDNB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_0_CNTL_2[] = {
+	 { "HYSTERESIS_DOWN", 0, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_UP", 8, 15, &umr_bitfield_default },
+	 { "RESIDENCY_COUNTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_0_CNTL_3[] = {
+	 { "LCLK_FREQUENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLKBYPASSCNTL", 8, 15, &umr_bitfield_default },
+	 { "ENABLED_FOR_THROTTLE", 16, 23, &umr_bitfield_default },
+	 { "ACTIVITY_THRESHOLD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_1_CNTL_0[] = {
+	 { "LOW_VOLTAGE_REQ_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "VID", 8, 15, &umr_bitfield_default },
+	 { "CLK_DIVIDER", 16, 23, &umr_bitfield_default },
+	 { "STATE_VALID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_1_CNTL_1[] = {
+	 { "MIN_VDDNB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_1_CNTL_2[] = {
+	 { "HYSTERESIS_DOWN", 0, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_UP", 8, 15, &umr_bitfield_default },
+	 { "RESIDENCY_COUNTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_1_CNTL_3[] = {
+	 { "LCLK_FREQUENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLKBYPASSCNTL", 8, 15, &umr_bitfield_default },
+	 { "ENABLED_FOR_THROTTLE", 16, 23, &umr_bitfield_default },
+	 { "ACTIVITY_THRESHOLD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_2_CNTL_0[] = {
+	 { "LOW_VOLTAGE_REQ_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "VID", 8, 15, &umr_bitfield_default },
+	 { "CLK_DIVIDER", 16, 23, &umr_bitfield_default },
+	 { "STATE_VALID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_2_CNTL_1[] = {
+	 { "MIN_VDDNB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_2_CNTL_2[] = {
+	 { "HYSTERESIS_DOWN", 0, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_UP", 8, 15, &umr_bitfield_default },
+	 { "RESIDENCY_COUNTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_2_CNTL_3[] = {
+	 { "LCLK_FREQUENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLKBYPASSCNTL", 8, 15, &umr_bitfield_default },
+	 { "ENABLED_FOR_THROTTLE", 16, 23, &umr_bitfield_default },
+	 { "ACTIVITY_THRESHOLD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_3_CNTL_0[] = {
+	 { "LOW_VOLTAGE_REQ_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "VID", 8, 15, &umr_bitfield_default },
+	 { "CLK_DIVIDER", 16, 23, &umr_bitfield_default },
+	 { "STATE_VALID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_3_CNTL_1[] = {
+	 { "MIN_VDDNB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_3_CNTL_2[] = {
+	 { "HYSTERESIS_DOWN", 0, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_UP", 8, 15, &umr_bitfield_default },
+	 { "RESIDENCY_COUNTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_3_CNTL_3[] = {
+	 { "LCLK_FREQUENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLKBYPASSCNTL", 8, 15, &umr_bitfield_default },
+	 { "ENABLED_FOR_THROTTLE", 16, 23, &umr_bitfield_default },
+	 { "ACTIVITY_THRESHOLD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_4_CNTL_0[] = {
+	 { "LOW_VOLTAGE_REQ_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "VID", 8, 15, &umr_bitfield_default },
+	 { "CLK_DIVIDER", 16, 23, &umr_bitfield_default },
+	 { "STATE_VALID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_4_CNTL_1[] = {
+	 { "MIN_VDDNB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_4_CNTL_2[] = {
+	 { "HYSTERESIS_DOWN", 0, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_UP", 8, 15, &umr_bitfield_default },
+	 { "RESIDENCY_COUNTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_4_CNTL_3[] = {
+	 { "LCLK_FREQUENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLKBYPASSCNTL", 8, 15, &umr_bitfield_default },
+	 { "ENABLED_FOR_THROTTLE", 16, 23, &umr_bitfield_default },
+	 { "ACTIVITY_THRESHOLD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_5_CNTL_0[] = {
+	 { "LOW_VOLTAGE_REQ_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "VID", 8, 15, &umr_bitfield_default },
+	 { "CLK_DIVIDER", 16, 23, &umr_bitfield_default },
+	 { "STATE_VALID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_5_CNTL_1[] = {
+	 { "MIN_VDDNB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_5_CNTL_2[] = {
+	 { "HYSTERESIS_DOWN", 0, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_UP", 8, 15, &umr_bitfield_default },
+	 { "RESIDENCY_COUNTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_5_CNTL_3[] = {
+	 { "LCLK_FREQUENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLKBYPASSCNTL", 8, 15, &umr_bitfield_default },
+	 { "ENABLED_FOR_THROTTLE", 16, 23, &umr_bitfield_default },
+	 { "ACTIVITY_THRESHOLD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_6_CNTL_0[] = {
+	 { "LOW_VOLTAGE_REQ_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "VID", 8, 15, &umr_bitfield_default },
+	 { "CLK_DIVIDER", 16, 23, &umr_bitfield_default },
+	 { "STATE_VALID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_6_CNTL_1[] = {
+	 { "MIN_VDDNB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_6_CNTL_2[] = {
+	 { "HYSTERESIS_DOWN", 0, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_UP", 8, 15, &umr_bitfield_default },
+	 { "RESIDENCY_COUNTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_6_CNTL_3[] = {
+	 { "LCLK_FREQUENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLKBYPASSCNTL", 8, 15, &umr_bitfield_default },
+	 { "ENABLED_FOR_THROTTLE", 16, 23, &umr_bitfield_default },
+	 { "ACTIVITY_THRESHOLD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_7_CNTL_0[] = {
+	 { "LOW_VOLTAGE_REQ_THRESHOLD", 0, 7, &umr_bitfield_default },
+	 { "VID", 8, 15, &umr_bitfield_default },
+	 { "CLK_DIVIDER", 16, 23, &umr_bitfield_default },
+	 { "STATE_VALID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_7_CNTL_1[] = {
+	 { "MIN_VDDNB", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_7_CNTL_2[] = {
+	 { "HYSTERESIS_DOWN", 0, 7, &umr_bitfield_default },
+	 { "HYSTERESIS_UP", 8, 15, &umr_bitfield_default },
+	 { "RESIDENCY_COUNTER", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_7_CNTL_3[] = {
+	 { "LCLK_FREQUENCY", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLKBYPASSCNTL", 8, 15, &umr_bitfield_default },
+	 { "ENABLED_FOR_THROTTLE", 16, 23, &umr_bitfield_default },
+	 { "ACTIVITY_THRESHOLD", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_0[] = {
+	 { "K_I", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_1[] = {
+	 { "LF_WINDUP_UPPER_LIM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_2[] = {
+	 { "LF_WINDUP_LOWER_LIM", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_3[] = {
+	 { "STATE_PRECISION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_4[] = {
+	 { "LF_PRECISION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_5[] = {
+	 { "LF_OFFSET", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_6[] = {
+	 { "MAX_STATE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_7[] = {
+	 { "MAX_LF_FRACTION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGIO_PID_CONTROLLER_CNTL_8[] = {
+	 { "STATE_SHIFT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_LEVEL_COUNT[] = {
+	 { "LCLK_DPM_LEVEL_COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_CNTL[] = {
+	 { "RESERVED", 0, 7, &umr_bitfield_default },
+	 { "LCLK_DPM_BOOT_STATE", 8, 15, &umr_bitfield_default },
+	 { "VOLTAGE_CHG_EN", 16, 23, &umr_bitfield_default },
+	 { "LCLK_DPM_EN", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE[] = {
+	 { "CURRENT_STATE", 0, 7, &umr_bitfield_default },
+	 { "TARGET_STATE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL[] = {
+	 { "LCLK_THERMAL_THROTTLING_EN", 0, 7, &umr_bitfield_default },
+	 { "TEMPERATURE_SEL", 8, 15, &umr_bitfield_default },
+	 { "LCLK_TT_MODE", 16, 23, &umr_bitfield_default },
+	 { "TT_HTC_ACTIVE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS[] = {
+	 { "LOW_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "HIGH_THRESHOLD", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_16[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_17[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_18[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_19[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_20[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_21[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_22[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_24[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_25[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_26[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_27[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_28[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_29[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_30[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_31[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_32[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_33[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_34[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_35[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_36[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_37[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_38[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_39[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_40[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_41[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_42[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_43[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_44[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_46[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_47[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_48[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_49[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_50[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_51[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_52[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_53[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_54[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_55[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_56[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_57[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_58[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_59[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_60[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_61[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_62[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_63[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_64[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_65[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_66[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_67[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_68[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_69[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_70[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_71[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_72[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_73[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_74[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_75[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_76[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_77[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_78[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_79[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_80[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_81[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_82[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_83[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_84[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_85[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_86[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_87[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_88[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_89[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_90[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_91[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_92[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_93[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_94[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_95[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_96[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_97[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_98[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_99[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_100[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_101[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_102[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_103[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_104[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_105[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_106[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_107[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_108[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_109[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_110[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_111[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_112[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_113[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_114[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_115[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_116[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_117[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_118[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_119[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_120[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_121[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_122[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_123[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_124[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_125[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_126[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_127[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_RESET_CNTL[] = {
+	 { "rst_reg", 0, 0, &umr_bitfield_default },
+	 { "srbm_soft_rst_override", 1, 1, &umr_bitfield_default },
+	 { "RegReset", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_0[] = {
+	 { "ck_disable", 0, 0, &umr_bitfield_default },
+	 { "auto_cg_en", 1, 1, &umr_bitfield_default },
+	 { "auto_cg_timeout", 8, 23, &umr_bitfield_default },
+	 { "cken", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_1[] = {
+	 { "auto_ck_disable", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_2[] = {
+	 { "wake_on_irq", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_MSG_ARG_0[] = {
+	 { "smc_msg_arg", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_PC_C[] = {
+	 { "smc_pc_c", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SCRATCH9[] = {
+	 { "SCRATCH_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_ACCESS_CNTL[] = {
+	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_1", 1, 1, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_2", 2, 2, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_3", 3, 3, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_4", 4, 4, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_5", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_6", 6, 6, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_7", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_11[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_0[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_0[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_1[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_1[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_2[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_2[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_3[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_3[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_4[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_4[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_5[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_5[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_6[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_6[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_7[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_7[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_0[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_1[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_2[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_3[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_4[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_5[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_6[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_7[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_8[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_8[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_9[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_9[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_10[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_10[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_11[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_11[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_8[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_9[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_10[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_UC_EVENTS[] = {
+	 { "RCU_TST_jpc_rep_req", 0, 0, &umr_bitfield_default },
+	 { "TST_RCU_jpc_rep_done", 1, 1, &umr_bitfield_default },
+	 { "drv_rst_mode", 2, 2, &umr_bitfield_default },
+	 { "TP_Tester", 6, 6, &umr_bitfield_default },
+	 { "boot_seq_done", 7, 7, &umr_bitfield_default },
+	 { "sclk_deep_sleep_exit", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_ACTIVE", 9, 9, &umr_bitfield_default },
+	 { "BREAK_PT2_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "FCH_HALT", 11, 11, &umr_bitfield_default },
+	 { "RCU_GIO_fch_lockdown", 13, 13, &umr_bitfield_default },
+	 { "INTERRUPTS_ENABLED", 16, 16, &umr_bitfield_default },
+	 { "RCU_DtmCnt0_Done", 17, 17, &umr_bitfield_default },
+	 { "RCU_DtmCnt1_Done", 18, 18, &umr_bitfield_default },
+	 { "RCU_DtmCnt2_Done", 19, 19, &umr_bitfield_default },
+	 { "irq31_sel", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_MISC_CTRL[] = {
+	 { "REG_DRV_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "REG_RCU_MEMREP_DIS", 3, 3, &umr_bitfield_default },
+	 { "REG_CC_FUSE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "REG_SAMU_FUSE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "REG_CC_SRBM_RD_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_DONE", 16, 16, &umr_bitfield_default },
+	 { "BREAK_PT2_DONE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_START", 22, 22, &umr_bitfield_default },
+	 { "RST_PULSE_WIDTH", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_RCU_FUSES[] = {
+	 { "GPU_DIS", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "EFUSE_RD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "CG_RST_GLB_REQ_DIS", 5, 5, &umr_bitfield_default },
+	 { "DRV_RST_MODE", 6, 6, &umr_bitfield_default },
+	 { "ROM_DIS", 7, 7, &umr_bitfield_default },
+	 { "JPC_REP_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT1", 9, 9, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT2", 10, 10, &umr_bitfield_default },
+	 { "PHY_FUSE_VALID", 14, 14, &umr_bitfield_default },
+	 { "SMU_IOC_MST_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "FCH_LOCKOUT_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "FCH_XFIRE_FILTER_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "XFIRE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "SAMU_FUSE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "BIF_RST_POLLING_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "MEM_HARDREP_EN", 22, 22, &umr_bitfield_default },
+	 { "PCIE_INIT_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "DSMU_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "RCU_SPARE", 25, 30, &umr_bitfield_default },
+	 { "PSP_ENABLE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_MISC_FUSES[] = {
+	 { "IOMMU_V2_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "MinSClkDid", 2, 8, &umr_bitfield_default },
+	 { "MISC_SPARE", 9, 10, &umr_bitfield_default },
+	 { "PostResetGnbClkDid", 11, 17, &umr_bitfield_default },
+	 { "L2IMU_tn2_dtc_half", 18, 18, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_half", 19, 19, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_half", 20, 20, &umr_bitfield_default },
+	 { "L2IMU_tn2_pdc_half", 21, 21, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_dis", 22, 22, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_dis", 23, 23, &umr_bitfield_default },
+	 { "VCE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "IOC_IOMMU_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "GNB_SPARE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SCLK_VID_FUSES[] = {
+	 { "SClkVid0", 0, 7, &umr_bitfield_default },
+	 { "SClkVid1", 8, 15, &umr_bitfield_default },
+	 { "SClkVid2", 16, 23, &umr_bitfield_default },
+	 { "SClkVid3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOCCFG_FUSES[] = {
+	 { "NB_REV_ID", 1, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOC_FUSES[] = {
+	 { "IOC_FUSES", 1, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_TST_EFUSE1_MISC[] = {
+	 { "RF_RM_6_2", 1, 5, &umr_bitfield_default },
+	 { "RME", 6, 6, &umr_bitfield_default },
+	 { "MBIST_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "HARD_REPAIR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SOFT_REPAIR_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "GPU_DIS", 10, 10, &umr_bitfield_default },
+	 { "SMS_PWRDWN_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "CRBBMP1500_DISA", 12, 12, &umr_bitfield_default },
+	 { "CRBBMP1500_DISB", 13, 13, &umr_bitfield_default },
+	 { "RM_RF8", 14, 14, &umr_bitfield_default },
+	 { "DFT_SPARE1", 22, 22, &umr_bitfield_default },
+	 { "DFT_SPARE2", 23, 23, &umr_bitfield_default },
+	 { "DFT_SPARE3", 24, 24, &umr_bitfield_default },
+	 { "VCE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "DCE_SCAN_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_TST_ID_STRAPS[] = {
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_FCTRL_FUSES[] = {
+	 { "EXT_EFUSE_MACRO_PRESENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_EFUSE_0[] = {
+	 { "EFUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGENERAL_PWRMGT[] = {
+	 { "GLOBAL_PWRMGT_EN", 0, 0, &umr_bitfield_default },
+	 { "STATIC_PM_EN", 1, 1, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_DIS", 2, 2, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_TYPE", 3, 3, &umr_bitfield_default },
+	 { "SW_SMIO_INDEX", 6, 6, &umr_bitfield_default },
+	 { "LOW_VOLT_D2_ACPI", 8, 8, &umr_bitfield_default },
+	 { "LOW_VOLT_D3_ACPI", 9, 9, &umr_bitfield_default },
+	 { "VOLT_PWRMGT_EN", 10, 10, &umr_bitfield_default },
+	 { "SPARE11", 11, 11, &umr_bitfield_default },
+	 { "GPU_COUNTER_ACPI", 14, 14, &umr_bitfield_default },
+	 { "GPU_COUNTER_CLK", 15, 15, &umr_bitfield_default },
+	 { "GPU_COUNTER_OFF", 16, 16, &umr_bitfield_default },
+	 { "GPU_COUNTER_INTF_OFF", 17, 17, &umr_bitfield_default },
+	 { "SPARE18", 18, 18, &umr_bitfield_default },
+	 { "ACPI_D3_VID", 19, 20, &umr_bitfield_default },
+	 { "DYN_SPREAD_SPECTRUM_EN", 23, 23, &umr_bitfield_default },
+	 { "SPARE27", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCNB_PWRMGT_CNTL[] = {
+	 { "GNB_SLOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "GNB_SLOW", 2, 2, &umr_bitfield_default },
+	 { "FORCE_NB_PS1", 3, 3, &umr_bitfield_default },
+	 { "DPM_ENABLED", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_PWRMGT_CNTL[] = {
+	 { "SCLK_PWRMGT_OFF", 0, 0, &umr_bitfield_default },
+	 { "SCLK_LOW_D1", 1, 1, &umr_bitfield_default },
+	 { "DYN_PWR_DOWN_EN", 2, 2, &umr_bitfield_default },
+	 { "RESET_BUSY_CNT", 4, 4, &umr_bitfield_default },
+	 { "RESET_SCLK_CNT", 5, 5, &umr_bitfield_default },
+	 { "RESERVED_0", 6, 6, &umr_bitfield_default },
+	 { "DYN_GFX_CLK_OFF_EN", 7, 7, &umr_bitfield_default },
+	 { "GFX_CLK_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "GFX_CLK_REQUEST_OFF", 9, 9, &umr_bitfield_default },
+	 { "GFX_CLK_FORCE_OFF", 10, 10, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D1", 11, 11, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D2", 12, 12, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D3", 13, 13, &umr_bitfield_default },
+	 { "DYN_LIGHT_SLEEP_EN", 14, 14, &umr_bitfield_default },
+	 { "AUTO_SCLK_PULSE_SKIP", 15, 15, &umr_bitfield_default },
+	 { "LIGHT_SLEEP_COUNTER", 16, 20, &umr_bitfield_default },
+	 { "DYNAMIC_PM_EN", 21, 21, &umr_bitfield_default },
+	 { "DPM_DYN_PWR_DOWN_CNTL", 22, 22, &umr_bitfield_default },
+	 { "DPM_DYN_PWR_DOWN_EN", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_3", 24, 24, &umr_bitfield_default },
+	 { "VOLTAGE_UPDATE_EN", 25, 25, &umr_bitfield_default },
+	 { "FORCE_PM0_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "FORCE_PM1_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "GFX_VOLTAGE_CHANGE_EN", 30, 30, &umr_bitfield_default },
+	 { "GFX_VOLTAGE_CHANGE_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX[] = {
+	 { "TARGET_STATE", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_STATE", 4, 7, &umr_bitfield_default },
+	 { "CURR_MCLK_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MCLK_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_SCLK_INDEX", 16, 20, &umr_bitfield_default },
+	 { "TARG_SCLK_INDEX", 21, 25, &umr_bitfield_default },
+	 { "CURR_LCLK_INDEX", 26, 28, &umr_bitfield_default },
+	 { "TARG_LCLK_INDEX", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 3, &umr_bitfield_default },
+	 { "TST_REF_SEL", 4, 7, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 8, 14, &umr_bitfield_default },
+	 { "TST_RESET", 15, 15, &umr_bitfield_default },
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_STATIC_SCREEN_PARAMETER[] = {
+	 { "STATIC_SCREEN_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL[] = {
+	 { "DISP_GAP", 0, 1, &umr_bitfield_default },
+	 { "VBI_TIMER_COUNT", 4, 17, &umr_bitfield_default },
+	 { "VBI_TIMER_UNIT", 20, 22, &umr_bitfield_default },
+	 { "DISP_GAP_MCHG", 24, 25, &umr_bitfield_default },
+	 { "VBI_TIMER_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACPI_CNTL[] = {
+	 { "SCLK_ACPI_DIV", 0, 6, &umr_bitfield_default },
+	 { "SCLK_CHANGE_SKIP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 16, 16, &umr_bitfield_default },
+	 { "SELF_REFRESH_MASK", 17, 17, &umr_bitfield_default },
+	 { "ALLOW_NBPSTATE_MASK", 18, 18, &umr_bitfield_default },
+	 { "BIF_BUSY_MASK", 19, 19, &umr_bitfield_default },
+	 { "UVD_BUSY_MASK", 20, 20, &umr_bitfield_default },
+	 { "MC0SRBM_BUSY_MASK", 21, 21, &umr_bitfield_default },
+	 { "MC1SRBM_BUSY_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_ALLOW_MASK", 23, 23, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 24, 24, &umr_bitfield_default },
+	 { "SELF_REFRESH_NLC_MASK", 25, 25, &umr_bitfield_default },
+	 { "FAST_EXIT_REQ_NBPSTATE", 26, 26, &umr_bitfield_default },
+	 { "DEEP_SLEEP_ENTRY_MODE", 27, 27, &umr_bitfield_default },
+	 { "MBUS2_ACTIVE_MASK", 28, 28, &umr_bitfield_default },
+	 { "VCE_BUSY_MASK", 29, 29, &umr_bitfield_default },
+	 { "AZ_BUSY_MASK", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RLC_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "HDP_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "ROM_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "PDMA_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "IDCT_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "SDMA_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_AZ_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK", 9, 9, &umr_bitfield_default },
+	 { "UVD_CG_MC_STAT_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "VCE_CG_MC_STAT_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "SAM_CG_MC_STAT_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "SAM_CG_STATUS_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 14, 14, &umr_bitfield_default },
+	 { "SHALLOW_DIV_ID", 21, 23, &umr_bitfield_default },
+	 { "INOUT_CUSHION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_MISC_CNTL[] = {
+	 { "DPM_DS_DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "DPM_SS_DIV_ID", 3, 5, &umr_bitfield_default },
+	 { "OCP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OCP_DS_DIV_ID", 17, 19, &umr_bitfield_default },
+	 { "OCP_SS_DIV_ID", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_VOLTAGE_STATUS[] = {
+	 { "SMU_VOLTAGE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "SMU_VOLTAGE_CURRENT_LEVEL", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL3[] = {
+	 { "GRBM_0_SMU_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRBM_1_SMU_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "GRBM_2_SMU_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "GRBM_3_SMU_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "GRBM_4_SMU_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "GRBM_5_SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "GRBM_6_SMU_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "GRBM_7_SMU_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "GRBM_8_SMU_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "GRBM_9_SMU_BUSY_MASK", 9, 9, &umr_bitfield_default },
+	 { "GRBM_10_SMU_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "GRBM_11_SMU_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "GRBM_12_SMU_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "GRBM_13_SMU_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "GRBM_14_SMU_BUSY_MASK", 14, 14, &umr_bitfield_default },
+	 { "GRBM_15_SMU_BUSY_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_1[] = {
+	 { "CURR_VDDCI_INDEX", 0, 3, &umr_bitfield_default },
+	 { "TARG_VDDCI_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_MVDD_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MVDD_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_VDDC_INDEX", 16, 19, &umr_bitfield_default },
+	 { "TARG_VDDC_INDEX", 20, 23, &umr_bitfield_default },
+	 { "CURR_PCIE_INDEX", 24, 27, &umr_bitfield_default },
+	 { "TARG_PCIE_INDEX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ULV_PARAMETER[] = {
+	 { "ULV_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "ULV_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_0[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_1[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_2[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_3[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_4[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_5[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_6[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
+	 { "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_MIN_DIV[] = {
+	 { "FRACV", 0, 11, &umr_bitfield_default },
+	 { "INTV", 12, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "L1IMU_SMU_IDLE_MASK", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_BIT3", 3, 3, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 4, 4, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE1_MASK", 6, 6, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE2_MASK", 7, 7, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE3_MASK", 8, 8, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE4_MASK", 9, 9, &umr_bitfield_default },
+	 { "L1IMUGPP_IDLE_MASK", 10, 10, &umr_bitfield_default },
+	 { "L1IMUGPPSB_IDLE_MASK", 11, 11, &umr_bitfield_default },
+	 { "L1IMUBIF_IDLE_MASK", 12, 12, &umr_bitfield_default },
+	 { "L1IMUINTGEN_IDLE_MASK", 13, 13, &umr_bitfield_default },
+	 { "L2IMU_IDLE_MASK", 14, 14, &umr_bitfield_default },
+	 { "ORB_IDLE_MASK", 15, 15, &umr_bitfield_default },
+	 { "ON_INB_WAKE_MASK", 16, 16, &umr_bitfield_default },
+	 { "ON_INB_WAKE_ACK_MASK", 17, 17, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_MASK", 18, 18, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_ACK_MASK", 19, 19, &umr_bitfield_default },
+	 { "DMAACTIVE_MASK", 20, 20, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_CNTL[] = {
+	 { "SX0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SX0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "SX0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "SX0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_OVR_SEL[] = {
+	 { "SX0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_OVR_VAL[] = {
+	 { "SX0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
+	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
+	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
+	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
+	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC1_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC1_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
+	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
+	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
+	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC2_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC2_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
+	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
+	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
+	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC3_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC3_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
+	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
+	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_CNTL[] = {
+	 { "CPL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CPL_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "CPL_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "CPL_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_SEL[] = {
+	 { "CPL_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_VAL[] = {
+	 { "CPL_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_CNTL[] = {
+	 { "DCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_STATUS[] = {
+	 { "DCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_CNTL[] = {
+	 { "VCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_STATUS[] = {
+	 { "VCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_CNTL[] = {
+	 { "ECLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_STATUS[] = {
+	 { "ECLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACLK_CNTL[] = {
+	 { "ACLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_DFS_BYPASS_CNTL[] = {
+	 { "BYPASSECLK", 0, 0, &umr_bitfield_default },
+	 { "BYPASSLCLK", 1, 1, &umr_bitfield_default },
+	 { "BYPASSEVCLK", 2, 2, &umr_bitfield_default },
+	 { "BYPASSDCLK", 3, 3, &umr_bitfield_default },
+	 { "BYPASSVCLK", 4, 4, &umr_bitfield_default },
+	 { "BYPASSDISPCLK", 5, 5, &umr_bitfield_default },
+	 { "BYPASSDPREFCLK", 6, 6, &umr_bitfield_default },
+	 { "BYPASSACLK", 7, 7, &umr_bitfield_default },
+	 { "BYPASSADIVCLK", 8, 8, &umr_bitfield_default },
+	 { "BYPASSPSPCLK", 9, 9, &umr_bitfield_default },
+	 { "BYPASSSAMCLK", 10, 10, &umr_bitfield_default },
+	 { "BYPASSSCLK", 11, 11, &umr_bitfield_default },
+	 { "USE_SPLL_BYPASS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL[] = {
+	 { "SPLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "SPLL_PWRON", 1, 1, &umr_bitfield_default },
+	 { "SPLL_DIVEN", 2, 2, &umr_bitfield_default },
+	 { "SPLL_BYPASS_EN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_BYPASS_THRU_DFS", 4, 4, &umr_bitfield_default },
+	 { "SPLL_REF_DIV", 5, 10, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_EN", 12, 12, &umr_bitfield_default },
+	 { "SPLL_BG_PWRON", 13, 13, &umr_bitfield_default },
+	 { "SPLL_BGADJ", 14, 17, &umr_bitfield_default },
+	 { "SPLL_PDIV_A", 18, 24, &umr_bitfield_default },
+	 { "SPLL_REG_BIAS", 25, 27, &umr_bitfield_default },
+	 { "SPLL_OTEST_LOCK_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_2[] = {
+	 { "SCLK_MUX_SEL", 0, 8, &umr_bitfield_default },
+	 { "SPLL_CTLREQ", 11, 11, &umr_bitfield_default },
+	 { "SPLL_BYPASS_CHG", 22, 22, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_CHG", 23, 23, &umr_bitfield_default },
+	 { "SPLL_RESET_CHG", 24, 24, &umr_bitfield_default },
+	 { "SPLL_BABY_STEP_CHG", 25, 25, &umr_bitfield_default },
+	 { "SCLK_MUX_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "SPLL_UNLOCK_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "SPLL_CLKF_UPDATE", 28, 28, &umr_bitfield_default },
+	 { "SPLL_TEST_UNLOCK_CLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_3[] = {
+	 { "SPLL_FB_DIV", 0, 25, &umr_bitfield_default },
+	 { "SPLL_DITHEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_4[] = {
+	 { "SPLL_SCLK_TEST_SEL", 0, 3, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT_SEL", 5, 6, &umr_bitfield_default },
+	 { "SPLL_SCLK_EN", 7, 8, &umr_bitfield_default },
+	 { "SPLL_SSAMP_EN", 9, 9, &umr_bitfield_default },
+	 { "SPLL_SPARE", 10, 18, &umr_bitfield_default },
+	 { "TEST_FRAC_BYPASS", 21, 21, &umr_bitfield_default },
+	 { "SPLL_ILOCK", 23, 23, &umr_bitfield_default },
+	 { "SPLL_FBCLK_SEL", 24, 24, &umr_bitfield_default },
+	 { "SPLL_VCTRLADC_EN", 25, 25, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT", 26, 27, &umr_bitfield_default },
+	 { "SPLL_SPARE_EXT", 28, 30, &umr_bitfield_default },
+	 { "SPLL_VTOI_BIAS_CNTL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_5[] = {
+	 { "FBDIV_SSC_BYPASS", 0, 0, &umr_bitfield_default },
+	 { "RISEFBVCO_EN", 1, 1, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 2, 3, &umr_bitfield_default },
+	 { "RESET_TIMER", 4, 5, &umr_bitfield_default },
+	 { "FAST_LOCK_CNTRL", 6, 7, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 8, 8, &umr_bitfield_default },
+	 { "RESET_ANTI_MUX", 9, 9, &umr_bitfield_default },
+	 { "REFCLK_BYPASS_EN", 10, 10, &umr_bitfield_default },
+	 { "PLLBYPASS", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_6[] = {
+	 { "SCLKMUX0_CLKOFF_CNT", 0, 7, &umr_bitfield_default },
+	 { "SCLKMUX1_CLKOFF_CNT", 8, 15, &umr_bitfield_default },
+	 { "SPLL_VCTL_EN", 16, 16, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_IN", 17, 20, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_OUT", 21, 24, &umr_bitfield_default },
+	 { "SPLL_LF_CNTR", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_7[] = {
+	 { "SPLL_BW_CNTRL", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPLL_CNTL_MODE[] = {
+	 { "SPLL_SW_DIR_CONTROL", 0, 0, &umr_bitfield_default },
+	 { "SPLL_LEGACY_PDIV", 1, 1, &umr_bitfield_default },
+	 { "SPLL_TEST", 2, 2, &umr_bitfield_default },
+	 { "SPLL_FASTEN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_ENSAT", 4, 4, &umr_bitfield_default },
+	 { "SPLL_TEST_CLK_EXT_DIV", 10, 11, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_DLY_CNT", 12, 19, &umr_bitfield_default },
+	 { "SPLL_RESET_EN", 28, 28, &umr_bitfield_default },
+	 { "SPLL_VCO_MODE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM[] = {
+	 { "SSEN", 0, 0, &umr_bitfield_default },
+	 { "CLKS", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM_2[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMPLL_BYPASSCLK_SEL[] = {
+	 { "MPLL_CLKOUT_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL[] = {
+	 { "XTALIN_DIVIDE", 1, 1, &umr_bitfield_default },
+	 { "BCLK_AS_XCLK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_2[] = {
+	 { "ENABLE_XCLK", 0, 0, &umr_bitfield_default },
+	 { "FORCE_BIF_REFCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "MUX_TCLK_TO_XCLK", 8, 8, &umr_bitfield_default },
+	 { "XO_IN_OSCIN_EN", 14, 14, &umr_bitfield_default },
+	 { "XO_IN_ICORE_CLK_OE", 15, 15, &umr_bitfield_default },
+	 { "XO_IN_CML_RXEN", 16, 16, &umr_bitfield_default },
+	 { "XO_IN_BIDIR_CML_OE", 17, 17, &umr_bitfield_default },
+	 { "XO_IN2_OSCIN_EN", 18, 18, &umr_bitfield_default },
+	 { "XO_IN2_ICORE_CLK_OE", 19, 19, &umr_bitfield_default },
+	 { "XO_IN2_CML_RXEN", 20, 20, &umr_bitfield_default },
+	 { "XO_IN2_BIDIR_CML_OE", 21, 21, &umr_bitfield_default },
+	 { "CML_CTRL", 22, 23, &umr_bitfield_default },
+	 { "CLK_SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_CLK_CNTL[] = {
+	 { "CMON_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "CTF_CLK_SHUTOFF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_CLK_CTRL[] = {
+	 { "DEEP_SLEEP_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "ZCLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "DFT_SMS_PG_CLK_SEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 4, &umr_bitfield_default },
+	 { "TST_REF_SEL", 5, 9, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 10, 16, &umr_bitfield_default },
+	 { "TST_RESET", 17, 17, &umr_bitfield_default },
+	 { "TST_CLK_SEL_MODE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL_2[] = {
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_ADFS_CLK_BYPASS_CNTL1[] = {
+	 { "ECLK_BYPASS_CNTL", 0, 2, &umr_bitfield_default },
+	 { "SCLK_BYPASS_CNTL", 3, 5, &umr_bitfield_default },
+	 { "LCLK_BYPASS_CNTL", 6, 8, &umr_bitfield_default },
+	 { "DCLK_BYPASS_CNTL", 9, 11, &umr_bitfield_default },
+	 { "VCLK_BYPASS_CNTL", 12, 14, &umr_bitfield_default },
+	 { "DISPCLK_BYPASS_CNTL", 15, 17, &umr_bitfield_default },
+	 { "DRREFCLK_BYPASS_CNTL", 18, 20, &umr_bitfield_default },
+	 { "ACLK_BYPASS_CNTL", 21, 23, &umr_bitfield_default },
+	 { "SAMCLK_BYPASS_CNTL", 24, 26, &umr_bitfield_default },
+	 { "ACLK_DIV_BYPASS_CNTL", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_ENA[] = {
+	 { "THERM_INTH_SET", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_SET", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_SET", 2, 2, &umr_bitfield_default },
+	 { "THERM_INTH_CLR", 3, 3, &umr_bitfield_default },
+	 { "THERM_INTL_CLR", 4, 4, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CLR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_CTRL[] = {
+	 { "DIG_THERM_INTH", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 8, 15, &umr_bitfield_default },
+	 { "GNB_TEMP_THRESHOLD", 16, 23, &umr_bitfield_default },
+	 { "THERM_INTH_MASK", 24, 24, &umr_bitfield_default },
+	 { "THERM_INTL_MASK", 25, 25, &umr_bitfield_default },
+	 { "THERM_TRIGGER_MASK", 26, 26, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_MASK", 27, 27, &umr_bitfield_default },
+	 { "THERM_GNB_HW_ENA", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_STATUS[] = {
+	 { "THERM_INTH_DETECT", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_DETECT", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_DETECT", 2, 2, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_DETECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MAIN_PLL_OP_FREQ[] = {
+	 { "PLL_OP_FREQ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_STATUS[] = {
+	 { "SMU_DONE", 0, 0, &umr_bitfield_default },
+	 { "SMU_PASS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_FIRMWARE[] = {
+	 { "SMU_IN_PROG", 0, 0, &umr_bitfield_default },
+	 { "SMU_RD_DONE", 1, 2, &umr_bitfield_default },
+	 { "SMU_SRAM_RD_BLOCK_EN", 3, 3, &umr_bitfield_default },
+	 { "SMU_SRAM_WR_BLOCK_EN", 4, 4, &umr_bitfield_default },
+	 { "SMU_counter", 8, 11, &umr_bitfield_default },
+	 { "SMU_MODE", 16, 16, &umr_bitfield_default },
+	 { "SMU_SEL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_INPUT_DATA[] = {
+	 { "START_ADDR", 0, 30, &umr_bitfield_default },
+	 { "AUTO_START", 31, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/smu700_regs.i b/src/lib/ip/smu700_regs.i
new file mode 100644
index 0000000..9f36659
--- /dev/null
+++ b/src/lib/ip/smu700_regs.i
@@ -0,0 +1,703 @@
+	{ "mmCG_FPS_CNT", REG_MMIO, 0x1a4, &mmCG_FPS_CNT[0], sizeof(mmCG_FPS_CNT)/sizeof(mmCG_FPS_CNT[0]), 0, 0 },
+	{ "ixDPM_TABLE_1", REG_SMC, 0x3f000, &ixDPM_TABLE_1[0], sizeof(ixDPM_TABLE_1)/sizeof(ixDPM_TABLE_1[0]), 0, 0 },
+	{ "ixDPM_TABLE_2", REG_SMC, 0x3f004, &ixDPM_TABLE_2[0], sizeof(ixDPM_TABLE_2)/sizeof(ixDPM_TABLE_2[0]), 0, 0 },
+	{ "ixDPM_TABLE_3", REG_SMC, 0x3f008, &ixDPM_TABLE_3[0], sizeof(ixDPM_TABLE_3)/sizeof(ixDPM_TABLE_3[0]), 0, 0 },
+	{ "ixDPM_TABLE_4", REG_SMC, 0x3f00c, &ixDPM_TABLE_4[0], sizeof(ixDPM_TABLE_4)/sizeof(ixDPM_TABLE_4[0]), 0, 0 },
+	{ "ixDPM_TABLE_5", REG_SMC, 0x3f010, &ixDPM_TABLE_5[0], sizeof(ixDPM_TABLE_5)/sizeof(ixDPM_TABLE_5[0]), 0, 0 },
+	{ "ixDPM_TABLE_6", REG_SMC, 0x3f014, &ixDPM_TABLE_6[0], sizeof(ixDPM_TABLE_6)/sizeof(ixDPM_TABLE_6[0]), 0, 0 },
+	{ "ixDPM_TABLE_7", REG_SMC, 0x3f018, &ixDPM_TABLE_7[0], sizeof(ixDPM_TABLE_7)/sizeof(ixDPM_TABLE_7[0]), 0, 0 },
+	{ "ixDPM_TABLE_8", REG_SMC, 0x3f01c, &ixDPM_TABLE_8[0], sizeof(ixDPM_TABLE_8)/sizeof(ixDPM_TABLE_8[0]), 0, 0 },
+	{ "ixDPM_TABLE_9", REG_SMC, 0x3f020, &ixDPM_TABLE_9[0], sizeof(ixDPM_TABLE_9)/sizeof(ixDPM_TABLE_9[0]), 0, 0 },
+	{ "ixDPM_TABLE_10", REG_SMC, 0x3f024, &ixDPM_TABLE_10[0], sizeof(ixDPM_TABLE_10)/sizeof(ixDPM_TABLE_10[0]), 0, 0 },
+	{ "ixDPM_TABLE_11", REG_SMC, 0x3f028, &ixDPM_TABLE_11[0], sizeof(ixDPM_TABLE_11)/sizeof(ixDPM_TABLE_11[0]), 0, 0 },
+	{ "ixDPM_TABLE_12", REG_SMC, 0x3f02c, &ixDPM_TABLE_12[0], sizeof(ixDPM_TABLE_12)/sizeof(ixDPM_TABLE_12[0]), 0, 0 },
+	{ "ixDPM_TABLE_13", REG_SMC, 0x3f030, &ixDPM_TABLE_13[0], sizeof(ixDPM_TABLE_13)/sizeof(ixDPM_TABLE_13[0]), 0, 0 },
+	{ "ixDPM_TABLE_14", REG_SMC, 0x3f034, &ixDPM_TABLE_14[0], sizeof(ixDPM_TABLE_14)/sizeof(ixDPM_TABLE_14[0]), 0, 0 },
+	{ "ixDPM_TABLE_15", REG_SMC, 0x3f038, &ixDPM_TABLE_15[0], sizeof(ixDPM_TABLE_15)/sizeof(ixDPM_TABLE_15[0]), 0, 0 },
+	{ "ixDPM_TABLE_16", REG_SMC, 0x3f03c, &ixDPM_TABLE_16[0], sizeof(ixDPM_TABLE_16)/sizeof(ixDPM_TABLE_16[0]), 0, 0 },
+	{ "ixDPM_TABLE_17", REG_SMC, 0x3f040, &ixDPM_TABLE_17[0], sizeof(ixDPM_TABLE_17)/sizeof(ixDPM_TABLE_17[0]), 0, 0 },
+	{ "ixDPM_TABLE_18", REG_SMC, 0x3f044, &ixDPM_TABLE_18[0], sizeof(ixDPM_TABLE_18)/sizeof(ixDPM_TABLE_18[0]), 0, 0 },
+	{ "ixDPM_TABLE_19", REG_SMC, 0x3f048, &ixDPM_TABLE_19[0], sizeof(ixDPM_TABLE_19)/sizeof(ixDPM_TABLE_19[0]), 0, 0 },
+	{ "ixDPM_TABLE_20", REG_SMC, 0x3f04c, &ixDPM_TABLE_20[0], sizeof(ixDPM_TABLE_20)/sizeof(ixDPM_TABLE_20[0]), 0, 0 },
+	{ "ixDPM_TABLE_21", REG_SMC, 0x3f050, &ixDPM_TABLE_21[0], sizeof(ixDPM_TABLE_21)/sizeof(ixDPM_TABLE_21[0]), 0, 0 },
+	{ "ixDPM_TABLE_22", REG_SMC, 0x3f054, &ixDPM_TABLE_22[0], sizeof(ixDPM_TABLE_22)/sizeof(ixDPM_TABLE_22[0]), 0, 0 },
+	{ "ixDPM_TABLE_23", REG_SMC, 0x3f058, &ixDPM_TABLE_23[0], sizeof(ixDPM_TABLE_23)/sizeof(ixDPM_TABLE_23[0]), 0, 0 },
+	{ "ixDPM_TABLE_24", REG_SMC, 0x3f05c, &ixDPM_TABLE_24[0], sizeof(ixDPM_TABLE_24)/sizeof(ixDPM_TABLE_24[0]), 0, 0 },
+	{ "ixDPM_TABLE_25", REG_SMC, 0x3f060, &ixDPM_TABLE_25[0], sizeof(ixDPM_TABLE_25)/sizeof(ixDPM_TABLE_25[0]), 0, 0 },
+	{ "ixDPM_TABLE_26", REG_SMC, 0x3f064, &ixDPM_TABLE_26[0], sizeof(ixDPM_TABLE_26)/sizeof(ixDPM_TABLE_26[0]), 0, 0 },
+	{ "ixDPM_TABLE_27", REG_SMC, 0x3f068, &ixDPM_TABLE_27[0], sizeof(ixDPM_TABLE_27)/sizeof(ixDPM_TABLE_27[0]), 0, 0 },
+	{ "ixDPM_TABLE_28", REG_SMC, 0x3f06c, &ixDPM_TABLE_28[0], sizeof(ixDPM_TABLE_28)/sizeof(ixDPM_TABLE_28[0]), 0, 0 },
+	{ "ixDPM_TABLE_29", REG_SMC, 0x3f070, &ixDPM_TABLE_29[0], sizeof(ixDPM_TABLE_29)/sizeof(ixDPM_TABLE_29[0]), 0, 0 },
+	{ "ixDPM_TABLE_30", REG_SMC, 0x3f074, &ixDPM_TABLE_30[0], sizeof(ixDPM_TABLE_30)/sizeof(ixDPM_TABLE_30[0]), 0, 0 },
+	{ "ixDPM_TABLE_31", REG_SMC, 0x3f078, &ixDPM_TABLE_31[0], sizeof(ixDPM_TABLE_31)/sizeof(ixDPM_TABLE_31[0]), 0, 0 },
+	{ "ixDPM_TABLE_32", REG_SMC, 0x3f07c, &ixDPM_TABLE_32[0], sizeof(ixDPM_TABLE_32)/sizeof(ixDPM_TABLE_32[0]), 0, 0 },
+	{ "ixDPM_TABLE_33", REG_SMC, 0x3f080, &ixDPM_TABLE_33[0], sizeof(ixDPM_TABLE_33)/sizeof(ixDPM_TABLE_33[0]), 0, 0 },
+	{ "ixDPM_TABLE_34", REG_SMC, 0x3f084, &ixDPM_TABLE_34[0], sizeof(ixDPM_TABLE_34)/sizeof(ixDPM_TABLE_34[0]), 0, 0 },
+	{ "ixDPM_TABLE_35", REG_SMC, 0x3f088, &ixDPM_TABLE_35[0], sizeof(ixDPM_TABLE_35)/sizeof(ixDPM_TABLE_35[0]), 0, 0 },
+	{ "ixDPM_TABLE_36", REG_SMC, 0x3f08c, &ixDPM_TABLE_36[0], sizeof(ixDPM_TABLE_36)/sizeof(ixDPM_TABLE_36[0]), 0, 0 },
+	{ "ixDPM_TABLE_37", REG_SMC, 0x3f090, &ixDPM_TABLE_37[0], sizeof(ixDPM_TABLE_37)/sizeof(ixDPM_TABLE_37[0]), 0, 0 },
+	{ "ixDPM_TABLE_38", REG_SMC, 0x3f094, &ixDPM_TABLE_38[0], sizeof(ixDPM_TABLE_38)/sizeof(ixDPM_TABLE_38[0]), 0, 0 },
+	{ "ixDPM_TABLE_39", REG_SMC, 0x3f098, &ixDPM_TABLE_39[0], sizeof(ixDPM_TABLE_39)/sizeof(ixDPM_TABLE_39[0]), 0, 0 },
+	{ "ixDPM_TABLE_40", REG_SMC, 0x3f09c, &ixDPM_TABLE_40[0], sizeof(ixDPM_TABLE_40)/sizeof(ixDPM_TABLE_40[0]), 0, 0 },
+	{ "ixDPM_TABLE_41", REG_SMC, 0x3f0a0, &ixDPM_TABLE_41[0], sizeof(ixDPM_TABLE_41)/sizeof(ixDPM_TABLE_41[0]), 0, 0 },
+	{ "ixDPM_TABLE_42", REG_SMC, 0x3f0a4, &ixDPM_TABLE_42[0], sizeof(ixDPM_TABLE_42)/sizeof(ixDPM_TABLE_42[0]), 0, 0 },
+	{ "ixDPM_TABLE_43", REG_SMC, 0x3f0a8, &ixDPM_TABLE_43[0], sizeof(ixDPM_TABLE_43)/sizeof(ixDPM_TABLE_43[0]), 0, 0 },
+	{ "ixDPM_TABLE_44", REG_SMC, 0x3f0ac, &ixDPM_TABLE_44[0], sizeof(ixDPM_TABLE_44)/sizeof(ixDPM_TABLE_44[0]), 0, 0 },
+	{ "ixDPM_TABLE_45", REG_SMC, 0x3f0b0, &ixDPM_TABLE_45[0], sizeof(ixDPM_TABLE_45)/sizeof(ixDPM_TABLE_45[0]), 0, 0 },
+	{ "ixDPM_TABLE_46", REG_SMC, 0x3f0b4, &ixDPM_TABLE_46[0], sizeof(ixDPM_TABLE_46)/sizeof(ixDPM_TABLE_46[0]), 0, 0 },
+	{ "ixDPM_TABLE_47", REG_SMC, 0x3f0b8, &ixDPM_TABLE_47[0], sizeof(ixDPM_TABLE_47)/sizeof(ixDPM_TABLE_47[0]), 0, 0 },
+	{ "ixDPM_TABLE_48", REG_SMC, 0x3f0bc, &ixDPM_TABLE_48[0], sizeof(ixDPM_TABLE_48)/sizeof(ixDPM_TABLE_48[0]), 0, 0 },
+	{ "ixDPM_TABLE_49", REG_SMC, 0x3f0c0, &ixDPM_TABLE_49[0], sizeof(ixDPM_TABLE_49)/sizeof(ixDPM_TABLE_49[0]), 0, 0 },
+	{ "ixDPM_TABLE_50", REG_SMC, 0x3f0c4, &ixDPM_TABLE_50[0], sizeof(ixDPM_TABLE_50)/sizeof(ixDPM_TABLE_50[0]), 0, 0 },
+	{ "ixDPM_TABLE_51", REG_SMC, 0x3f0c8, &ixDPM_TABLE_51[0], sizeof(ixDPM_TABLE_51)/sizeof(ixDPM_TABLE_51[0]), 0, 0 },
+	{ "ixDPM_TABLE_52", REG_SMC, 0x3f0cc, &ixDPM_TABLE_52[0], sizeof(ixDPM_TABLE_52)/sizeof(ixDPM_TABLE_52[0]), 0, 0 },
+	{ "ixDPM_TABLE_53", REG_SMC, 0x3f0d0, &ixDPM_TABLE_53[0], sizeof(ixDPM_TABLE_53)/sizeof(ixDPM_TABLE_53[0]), 0, 0 },
+	{ "ixDPM_TABLE_54", REG_SMC, 0x3f0d4, &ixDPM_TABLE_54[0], sizeof(ixDPM_TABLE_54)/sizeof(ixDPM_TABLE_54[0]), 0, 0 },
+	{ "ixDPM_TABLE_55", REG_SMC, 0x3f0d8, &ixDPM_TABLE_55[0], sizeof(ixDPM_TABLE_55)/sizeof(ixDPM_TABLE_55[0]), 0, 0 },
+	{ "ixDPM_TABLE_56", REG_SMC, 0x3f0dc, &ixDPM_TABLE_56[0], sizeof(ixDPM_TABLE_56)/sizeof(ixDPM_TABLE_56[0]), 0, 0 },
+	{ "ixDPM_TABLE_57", REG_SMC, 0x3f0e0, &ixDPM_TABLE_57[0], sizeof(ixDPM_TABLE_57)/sizeof(ixDPM_TABLE_57[0]), 0, 0 },
+	{ "ixDPM_TABLE_58", REG_SMC, 0x3f0e4, &ixDPM_TABLE_58[0], sizeof(ixDPM_TABLE_58)/sizeof(ixDPM_TABLE_58[0]), 0, 0 },
+	{ "ixDPM_TABLE_59", REG_SMC, 0x3f0e8, &ixDPM_TABLE_59[0], sizeof(ixDPM_TABLE_59)/sizeof(ixDPM_TABLE_59[0]), 0, 0 },
+	{ "ixDPM_TABLE_60", REG_SMC, 0x3f0ec, &ixDPM_TABLE_60[0], sizeof(ixDPM_TABLE_60)/sizeof(ixDPM_TABLE_60[0]), 0, 0 },
+	{ "ixDPM_TABLE_61", REG_SMC, 0x3f0f0, &ixDPM_TABLE_61[0], sizeof(ixDPM_TABLE_61)/sizeof(ixDPM_TABLE_61[0]), 0, 0 },
+	{ "ixDPM_TABLE_62", REG_SMC, 0x3f0f4, &ixDPM_TABLE_62[0], sizeof(ixDPM_TABLE_62)/sizeof(ixDPM_TABLE_62[0]), 0, 0 },
+	{ "ixDPM_TABLE_63", REG_SMC, 0x3f0f8, &ixDPM_TABLE_63[0], sizeof(ixDPM_TABLE_63)/sizeof(ixDPM_TABLE_63[0]), 0, 0 },
+	{ "ixDPM_TABLE_64", REG_SMC, 0x3f0fc, &ixDPM_TABLE_64[0], sizeof(ixDPM_TABLE_64)/sizeof(ixDPM_TABLE_64[0]), 0, 0 },
+	{ "ixDPM_TABLE_65", REG_SMC, 0x3f100, &ixDPM_TABLE_65[0], sizeof(ixDPM_TABLE_65)/sizeof(ixDPM_TABLE_65[0]), 0, 0 },
+	{ "ixDPM_TABLE_66", REG_SMC, 0x3f104, &ixDPM_TABLE_66[0], sizeof(ixDPM_TABLE_66)/sizeof(ixDPM_TABLE_66[0]), 0, 0 },
+	{ "ixDPM_TABLE_67", REG_SMC, 0x3f108, &ixDPM_TABLE_67[0], sizeof(ixDPM_TABLE_67)/sizeof(ixDPM_TABLE_67[0]), 0, 0 },
+	{ "ixDPM_TABLE_68", REG_SMC, 0x3f10c, &ixDPM_TABLE_68[0], sizeof(ixDPM_TABLE_68)/sizeof(ixDPM_TABLE_68[0]), 0, 0 },
+	{ "ixDPM_TABLE_69", REG_SMC, 0x3f110, &ixDPM_TABLE_69[0], sizeof(ixDPM_TABLE_69)/sizeof(ixDPM_TABLE_69[0]), 0, 0 },
+	{ "ixDPM_TABLE_70", REG_SMC, 0x3f114, &ixDPM_TABLE_70[0], sizeof(ixDPM_TABLE_70)/sizeof(ixDPM_TABLE_70[0]), 0, 0 },
+	{ "ixDPM_TABLE_71", REG_SMC, 0x3f118, &ixDPM_TABLE_71[0], sizeof(ixDPM_TABLE_71)/sizeof(ixDPM_TABLE_71[0]), 0, 0 },
+	{ "ixDPM_TABLE_72", REG_SMC, 0x3f11c, &ixDPM_TABLE_72[0], sizeof(ixDPM_TABLE_72)/sizeof(ixDPM_TABLE_72[0]), 0, 0 },
+	{ "ixDPM_TABLE_73", REG_SMC, 0x3f120, &ixDPM_TABLE_73[0], sizeof(ixDPM_TABLE_73)/sizeof(ixDPM_TABLE_73[0]), 0, 0 },
+	{ "ixDPM_TABLE_74", REG_SMC, 0x3f124, &ixDPM_TABLE_74[0], sizeof(ixDPM_TABLE_74)/sizeof(ixDPM_TABLE_74[0]), 0, 0 },
+	{ "ixDPM_TABLE_75", REG_SMC, 0x3f128, &ixDPM_TABLE_75[0], sizeof(ixDPM_TABLE_75)/sizeof(ixDPM_TABLE_75[0]), 0, 0 },
+	{ "ixDPM_TABLE_76", REG_SMC, 0x3f12c, &ixDPM_TABLE_76[0], sizeof(ixDPM_TABLE_76)/sizeof(ixDPM_TABLE_76[0]), 0, 0 },
+	{ "ixDPM_TABLE_77", REG_SMC, 0x3f130, &ixDPM_TABLE_77[0], sizeof(ixDPM_TABLE_77)/sizeof(ixDPM_TABLE_77[0]), 0, 0 },
+	{ "ixDPM_TABLE_78", REG_SMC, 0x3f134, &ixDPM_TABLE_78[0], sizeof(ixDPM_TABLE_78)/sizeof(ixDPM_TABLE_78[0]), 0, 0 },
+	{ "ixDPM_TABLE_79", REG_SMC, 0x3f138, &ixDPM_TABLE_79[0], sizeof(ixDPM_TABLE_79)/sizeof(ixDPM_TABLE_79[0]), 0, 0 },
+	{ "ixDPM_TABLE_80", REG_SMC, 0x3f13c, &ixDPM_TABLE_80[0], sizeof(ixDPM_TABLE_80)/sizeof(ixDPM_TABLE_80[0]), 0, 0 },
+	{ "ixDPM_TABLE_81", REG_SMC, 0x3f140, &ixDPM_TABLE_81[0], sizeof(ixDPM_TABLE_81)/sizeof(ixDPM_TABLE_81[0]), 0, 0 },
+	{ "ixDPM_TABLE_82", REG_SMC, 0x3f144, &ixDPM_TABLE_82[0], sizeof(ixDPM_TABLE_82)/sizeof(ixDPM_TABLE_82[0]), 0, 0 },
+	{ "ixDPM_TABLE_83", REG_SMC, 0x3f148, &ixDPM_TABLE_83[0], sizeof(ixDPM_TABLE_83)/sizeof(ixDPM_TABLE_83[0]), 0, 0 },
+	{ "ixDPM_TABLE_84", REG_SMC, 0x3f14c, &ixDPM_TABLE_84[0], sizeof(ixDPM_TABLE_84)/sizeof(ixDPM_TABLE_84[0]), 0, 0 },
+	{ "ixDPM_TABLE_85", REG_SMC, 0x3f150, &ixDPM_TABLE_85[0], sizeof(ixDPM_TABLE_85)/sizeof(ixDPM_TABLE_85[0]), 0, 0 },
+	{ "ixDPM_TABLE_86", REG_SMC, 0x3f154, &ixDPM_TABLE_86[0], sizeof(ixDPM_TABLE_86)/sizeof(ixDPM_TABLE_86[0]), 0, 0 },
+	{ "ixDPM_TABLE_87", REG_SMC, 0x3f158, &ixDPM_TABLE_87[0], sizeof(ixDPM_TABLE_87)/sizeof(ixDPM_TABLE_87[0]), 0, 0 },
+	{ "ixDPM_TABLE_88", REG_SMC, 0x3f15c, &ixDPM_TABLE_88[0], sizeof(ixDPM_TABLE_88)/sizeof(ixDPM_TABLE_88[0]), 0, 0 },
+	{ "ixDPM_TABLE_89", REG_SMC, 0x3f160, &ixDPM_TABLE_89[0], sizeof(ixDPM_TABLE_89)/sizeof(ixDPM_TABLE_89[0]), 0, 0 },
+	{ "ixDPM_TABLE_90", REG_SMC, 0x3f164, &ixDPM_TABLE_90[0], sizeof(ixDPM_TABLE_90)/sizeof(ixDPM_TABLE_90[0]), 0, 0 },
+	{ "ixDPM_TABLE_91", REG_SMC, 0x3f168, &ixDPM_TABLE_91[0], sizeof(ixDPM_TABLE_91)/sizeof(ixDPM_TABLE_91[0]), 0, 0 },
+	{ "ixDPM_TABLE_92", REG_SMC, 0x3f16c, &ixDPM_TABLE_92[0], sizeof(ixDPM_TABLE_92)/sizeof(ixDPM_TABLE_92[0]), 0, 0 },
+	{ "ixDPM_TABLE_93", REG_SMC, 0x3f170, &ixDPM_TABLE_93[0], sizeof(ixDPM_TABLE_93)/sizeof(ixDPM_TABLE_93[0]), 0, 0 },
+	{ "ixDPM_TABLE_94", REG_SMC, 0x3f174, &ixDPM_TABLE_94[0], sizeof(ixDPM_TABLE_94)/sizeof(ixDPM_TABLE_94[0]), 0, 0 },
+	{ "ixDPM_TABLE_95", REG_SMC, 0x3f178, &ixDPM_TABLE_95[0], sizeof(ixDPM_TABLE_95)/sizeof(ixDPM_TABLE_95[0]), 0, 0 },
+	{ "ixDPM_TABLE_96", REG_SMC, 0x3f17c, &ixDPM_TABLE_96[0], sizeof(ixDPM_TABLE_96)/sizeof(ixDPM_TABLE_96[0]), 0, 0 },
+	{ "ixDPM_TABLE_97", REG_SMC, 0x3f180, &ixDPM_TABLE_97[0], sizeof(ixDPM_TABLE_97)/sizeof(ixDPM_TABLE_97[0]), 0, 0 },
+	{ "ixDPM_TABLE_98", REG_SMC, 0x3f184, &ixDPM_TABLE_98[0], sizeof(ixDPM_TABLE_98)/sizeof(ixDPM_TABLE_98[0]), 0, 0 },
+	{ "ixDPM_TABLE_99", REG_SMC, 0x3f188, &ixDPM_TABLE_99[0], sizeof(ixDPM_TABLE_99)/sizeof(ixDPM_TABLE_99[0]), 0, 0 },
+	{ "ixDPM_TABLE_100", REG_SMC, 0x3f18c, &ixDPM_TABLE_100[0], sizeof(ixDPM_TABLE_100)/sizeof(ixDPM_TABLE_100[0]), 0, 0 },
+	{ "ixDPM_TABLE_101", REG_SMC, 0x3f190, &ixDPM_TABLE_101[0], sizeof(ixDPM_TABLE_101)/sizeof(ixDPM_TABLE_101[0]), 0, 0 },
+	{ "ixDPM_TABLE_102", REG_SMC, 0x3f194, &ixDPM_TABLE_102[0], sizeof(ixDPM_TABLE_102)/sizeof(ixDPM_TABLE_102[0]), 0, 0 },
+	{ "ixDPM_TABLE_103", REG_SMC, 0x3f198, &ixDPM_TABLE_103[0], sizeof(ixDPM_TABLE_103)/sizeof(ixDPM_TABLE_103[0]), 0, 0 },
+	{ "ixDPM_TABLE_104", REG_SMC, 0x3f19c, &ixDPM_TABLE_104[0], sizeof(ixDPM_TABLE_104)/sizeof(ixDPM_TABLE_104[0]), 0, 0 },
+	{ "ixDPM_TABLE_105", REG_SMC, 0x3f1a0, &ixDPM_TABLE_105[0], sizeof(ixDPM_TABLE_105)/sizeof(ixDPM_TABLE_105[0]), 0, 0 },
+	{ "ixDPM_TABLE_106", REG_SMC, 0x3f1a4, &ixDPM_TABLE_106[0], sizeof(ixDPM_TABLE_106)/sizeof(ixDPM_TABLE_106[0]), 0, 0 },
+	{ "ixDPM_TABLE_107", REG_SMC, 0x3f1a8, &ixDPM_TABLE_107[0], sizeof(ixDPM_TABLE_107)/sizeof(ixDPM_TABLE_107[0]), 0, 0 },
+	{ "ixDPM_TABLE_108", REG_SMC, 0x3f1ac, &ixDPM_TABLE_108[0], sizeof(ixDPM_TABLE_108)/sizeof(ixDPM_TABLE_108[0]), 0, 0 },
+	{ "ixDPM_TABLE_109", REG_SMC, 0x3f1b0, &ixDPM_TABLE_109[0], sizeof(ixDPM_TABLE_109)/sizeof(ixDPM_TABLE_109[0]), 0, 0 },
+	{ "ixDPM_TABLE_110", REG_SMC, 0x3f1b4, &ixDPM_TABLE_110[0], sizeof(ixDPM_TABLE_110)/sizeof(ixDPM_TABLE_110[0]), 0, 0 },
+	{ "ixDPM_TABLE_111", REG_SMC, 0x3f1b8, &ixDPM_TABLE_111[0], sizeof(ixDPM_TABLE_111)/sizeof(ixDPM_TABLE_111[0]), 0, 0 },
+	{ "ixDPM_TABLE_112", REG_SMC, 0x3f1bc, &ixDPM_TABLE_112[0], sizeof(ixDPM_TABLE_112)/sizeof(ixDPM_TABLE_112[0]), 0, 0 },
+	{ "ixDPM_TABLE_113", REG_SMC, 0x3f1c0, &ixDPM_TABLE_113[0], sizeof(ixDPM_TABLE_113)/sizeof(ixDPM_TABLE_113[0]), 0, 0 },
+	{ "ixDPM_TABLE_114", REG_SMC, 0x3f1c4, &ixDPM_TABLE_114[0], sizeof(ixDPM_TABLE_114)/sizeof(ixDPM_TABLE_114[0]), 0, 0 },
+	{ "ixDPM_TABLE_115", REG_SMC, 0x3f1c8, &ixDPM_TABLE_115[0], sizeof(ixDPM_TABLE_115)/sizeof(ixDPM_TABLE_115[0]), 0, 0 },
+	{ "ixDPM_TABLE_116", REG_SMC, 0x3f1cc, &ixDPM_TABLE_116[0], sizeof(ixDPM_TABLE_116)/sizeof(ixDPM_TABLE_116[0]), 0, 0 },
+	{ "ixDPM_TABLE_117", REG_SMC, 0x3f1d0, &ixDPM_TABLE_117[0], sizeof(ixDPM_TABLE_117)/sizeof(ixDPM_TABLE_117[0]), 0, 0 },
+	{ "ixDPM_TABLE_118", REG_SMC, 0x3f1d4, &ixDPM_TABLE_118[0], sizeof(ixDPM_TABLE_118)/sizeof(ixDPM_TABLE_118[0]), 0, 0 },
+	{ "ixDPM_TABLE_119", REG_SMC, 0x3f1d8, &ixDPM_TABLE_119[0], sizeof(ixDPM_TABLE_119)/sizeof(ixDPM_TABLE_119[0]), 0, 0 },
+	{ "ixDPM_TABLE_120", REG_SMC, 0x3f1dc, &ixDPM_TABLE_120[0], sizeof(ixDPM_TABLE_120)/sizeof(ixDPM_TABLE_120[0]), 0, 0 },
+	{ "ixDPM_TABLE_121", REG_SMC, 0x3f1e0, &ixDPM_TABLE_121[0], sizeof(ixDPM_TABLE_121)/sizeof(ixDPM_TABLE_121[0]), 0, 0 },
+	{ "ixDPM_TABLE_122", REG_SMC, 0x3f1e4, &ixDPM_TABLE_122[0], sizeof(ixDPM_TABLE_122)/sizeof(ixDPM_TABLE_122[0]), 0, 0 },
+	{ "ixDPM_TABLE_123", REG_SMC, 0x3f1e8, &ixDPM_TABLE_123[0], sizeof(ixDPM_TABLE_123)/sizeof(ixDPM_TABLE_123[0]), 0, 0 },
+	{ "ixDPM_TABLE_124", REG_SMC, 0x3f1ec, &ixDPM_TABLE_124[0], sizeof(ixDPM_TABLE_124)/sizeof(ixDPM_TABLE_124[0]), 0, 0 },
+	{ "ixDPM_TABLE_125", REG_SMC, 0x3f1f0, &ixDPM_TABLE_125[0], sizeof(ixDPM_TABLE_125)/sizeof(ixDPM_TABLE_125[0]), 0, 0 },
+	{ "ixDPM_TABLE_126", REG_SMC, 0x3f1f4, &ixDPM_TABLE_126[0], sizeof(ixDPM_TABLE_126)/sizeof(ixDPM_TABLE_126[0]), 0, 0 },
+	{ "ixDPM_TABLE_127", REG_SMC, 0x3f1f8, &ixDPM_TABLE_127[0], sizeof(ixDPM_TABLE_127)/sizeof(ixDPM_TABLE_127[0]), 0, 0 },
+	{ "ixDPM_TABLE_128", REG_SMC, 0x3f1fc, &ixDPM_TABLE_128[0], sizeof(ixDPM_TABLE_128)/sizeof(ixDPM_TABLE_128[0]), 0, 0 },
+	{ "ixDPM_TABLE_129", REG_SMC, 0x3f200, &ixDPM_TABLE_129[0], sizeof(ixDPM_TABLE_129)/sizeof(ixDPM_TABLE_129[0]), 0, 0 },
+	{ "ixDPM_TABLE_130", REG_SMC, 0x3f204, &ixDPM_TABLE_130[0], sizeof(ixDPM_TABLE_130)/sizeof(ixDPM_TABLE_130[0]), 0, 0 },
+	{ "ixDPM_TABLE_131", REG_SMC, 0x3f208, &ixDPM_TABLE_131[0], sizeof(ixDPM_TABLE_131)/sizeof(ixDPM_TABLE_131[0]), 0, 0 },
+	{ "ixDPM_TABLE_132", REG_SMC, 0x3f20c, &ixDPM_TABLE_132[0], sizeof(ixDPM_TABLE_132)/sizeof(ixDPM_TABLE_132[0]), 0, 0 },
+	{ "ixDPM_TABLE_133", REG_SMC, 0x3f210, &ixDPM_TABLE_133[0], sizeof(ixDPM_TABLE_133)/sizeof(ixDPM_TABLE_133[0]), 0, 0 },
+	{ "ixDPM_TABLE_134", REG_SMC, 0x3f214, &ixDPM_TABLE_134[0], sizeof(ixDPM_TABLE_134)/sizeof(ixDPM_TABLE_134[0]), 0, 0 },
+	{ "ixDPM_TABLE_135", REG_SMC, 0x3f218, &ixDPM_TABLE_135[0], sizeof(ixDPM_TABLE_135)/sizeof(ixDPM_TABLE_135[0]), 0, 0 },
+	{ "ixDPM_TABLE_136", REG_SMC, 0x3f21c, &ixDPM_TABLE_136[0], sizeof(ixDPM_TABLE_136)/sizeof(ixDPM_TABLE_136[0]), 0, 0 },
+	{ "ixDPM_TABLE_137", REG_SMC, 0x3f220, &ixDPM_TABLE_137[0], sizeof(ixDPM_TABLE_137)/sizeof(ixDPM_TABLE_137[0]), 0, 0 },
+	{ "ixDPM_TABLE_138", REG_SMC, 0x3f224, &ixDPM_TABLE_138[0], sizeof(ixDPM_TABLE_138)/sizeof(ixDPM_TABLE_138[0]), 0, 0 },
+	{ "ixDPM_TABLE_139", REG_SMC, 0x3f228, &ixDPM_TABLE_139[0], sizeof(ixDPM_TABLE_139)/sizeof(ixDPM_TABLE_139[0]), 0, 0 },
+	{ "ixDPM_TABLE_140", REG_SMC, 0x3f22c, &ixDPM_TABLE_140[0], sizeof(ixDPM_TABLE_140)/sizeof(ixDPM_TABLE_140[0]), 0, 0 },
+	{ "ixDPM_TABLE_141", REG_SMC, 0x3f230, &ixDPM_TABLE_141[0], sizeof(ixDPM_TABLE_141)/sizeof(ixDPM_TABLE_141[0]), 0, 0 },
+	{ "ixDPM_TABLE_142", REG_SMC, 0x3f234, &ixDPM_TABLE_142[0], sizeof(ixDPM_TABLE_142)/sizeof(ixDPM_TABLE_142[0]), 0, 0 },
+	{ "ixDPM_TABLE_143", REG_SMC, 0x3f238, &ixDPM_TABLE_143[0], sizeof(ixDPM_TABLE_143)/sizeof(ixDPM_TABLE_143[0]), 0, 0 },
+	{ "ixDPM_TABLE_144", REG_SMC, 0x3f23c, &ixDPM_TABLE_144[0], sizeof(ixDPM_TABLE_144)/sizeof(ixDPM_TABLE_144[0]), 0, 0 },
+	{ "ixDPM_TABLE_145", REG_SMC, 0x3f240, &ixDPM_TABLE_145[0], sizeof(ixDPM_TABLE_145)/sizeof(ixDPM_TABLE_145[0]), 0, 0 },
+	{ "ixDPM_TABLE_146", REG_SMC, 0x3f244, &ixDPM_TABLE_146[0], sizeof(ixDPM_TABLE_146)/sizeof(ixDPM_TABLE_146[0]), 0, 0 },
+	{ "ixDPM_TABLE_147", REG_SMC, 0x3f248, &ixDPM_TABLE_147[0], sizeof(ixDPM_TABLE_147)/sizeof(ixDPM_TABLE_147[0]), 0, 0 },
+	{ "ixDPM_TABLE_148", REG_SMC, 0x3f24c, &ixDPM_TABLE_148[0], sizeof(ixDPM_TABLE_148)/sizeof(ixDPM_TABLE_148[0]), 0, 0 },
+	{ "ixDPM_TABLE_149", REG_SMC, 0x3f250, &ixDPM_TABLE_149[0], sizeof(ixDPM_TABLE_149)/sizeof(ixDPM_TABLE_149[0]), 0, 0 },
+	{ "ixDPM_TABLE_150", REG_SMC, 0x3f254, &ixDPM_TABLE_150[0], sizeof(ixDPM_TABLE_150)/sizeof(ixDPM_TABLE_150[0]), 0, 0 },
+	{ "ixDPM_TABLE_151", REG_SMC, 0x3f258, &ixDPM_TABLE_151[0], sizeof(ixDPM_TABLE_151)/sizeof(ixDPM_TABLE_151[0]), 0, 0 },
+	{ "ixDPM_TABLE_152", REG_SMC, 0x3f25c, &ixDPM_TABLE_152[0], sizeof(ixDPM_TABLE_152)/sizeof(ixDPM_TABLE_152[0]), 0, 0 },
+	{ "ixDPM_TABLE_153", REG_SMC, 0x3f260, &ixDPM_TABLE_153[0], sizeof(ixDPM_TABLE_153)/sizeof(ixDPM_TABLE_153[0]), 0, 0 },
+	{ "ixDPM_TABLE_154", REG_SMC, 0x3f264, &ixDPM_TABLE_154[0], sizeof(ixDPM_TABLE_154)/sizeof(ixDPM_TABLE_154[0]), 0, 0 },
+	{ "ixDPM_TABLE_155", REG_SMC, 0x3f268, &ixDPM_TABLE_155[0], sizeof(ixDPM_TABLE_155)/sizeof(ixDPM_TABLE_155[0]), 0, 0 },
+	{ "ixDPM_TABLE_156", REG_SMC, 0x3f26c, &ixDPM_TABLE_156[0], sizeof(ixDPM_TABLE_156)/sizeof(ixDPM_TABLE_156[0]), 0, 0 },
+	{ "ixDPM_TABLE_157", REG_SMC, 0x3f270, &ixDPM_TABLE_157[0], sizeof(ixDPM_TABLE_157)/sizeof(ixDPM_TABLE_157[0]), 0, 0 },
+	{ "ixDPM_TABLE_158", REG_SMC, 0x3f274, &ixDPM_TABLE_158[0], sizeof(ixDPM_TABLE_158)/sizeof(ixDPM_TABLE_158[0]), 0, 0 },
+	{ "ixDPM_TABLE_159", REG_SMC, 0x3f278, &ixDPM_TABLE_159[0], sizeof(ixDPM_TABLE_159)/sizeof(ixDPM_TABLE_159[0]), 0, 0 },
+	{ "ixDPM_TABLE_160", REG_SMC, 0x3f27c, &ixDPM_TABLE_160[0], sizeof(ixDPM_TABLE_160)/sizeof(ixDPM_TABLE_160[0]), 0, 0 },
+	{ "ixDPM_TABLE_161", REG_SMC, 0x3f280, &ixDPM_TABLE_161[0], sizeof(ixDPM_TABLE_161)/sizeof(ixDPM_TABLE_161[0]), 0, 0 },
+	{ "ixDPM_TABLE_162", REG_SMC, 0x3f284, &ixDPM_TABLE_162[0], sizeof(ixDPM_TABLE_162)/sizeof(ixDPM_TABLE_162[0]), 0, 0 },
+	{ "ixDPM_TABLE_163", REG_SMC, 0x3f288, &ixDPM_TABLE_163[0], sizeof(ixDPM_TABLE_163)/sizeof(ixDPM_TABLE_163[0]), 0, 0 },
+	{ "ixDPM_TABLE_164", REG_SMC, 0x3f28c, &ixDPM_TABLE_164[0], sizeof(ixDPM_TABLE_164)/sizeof(ixDPM_TABLE_164[0]), 0, 0 },
+	{ "ixDPM_TABLE_165", REG_SMC, 0x3f290, &ixDPM_TABLE_165[0], sizeof(ixDPM_TABLE_165)/sizeof(ixDPM_TABLE_165[0]), 0, 0 },
+	{ "ixDPM_TABLE_166", REG_SMC, 0x3f294, &ixDPM_TABLE_166[0], sizeof(ixDPM_TABLE_166)/sizeof(ixDPM_TABLE_166[0]), 0, 0 },
+	{ "ixDPM_TABLE_167", REG_SMC, 0x3f298, &ixDPM_TABLE_167[0], sizeof(ixDPM_TABLE_167)/sizeof(ixDPM_TABLE_167[0]), 0, 0 },
+	{ "ixDPM_TABLE_168", REG_SMC, 0x3f29c, &ixDPM_TABLE_168[0], sizeof(ixDPM_TABLE_168)/sizeof(ixDPM_TABLE_168[0]), 0, 0 },
+	{ "ixDPM_TABLE_169", REG_SMC, 0x3f2a0, &ixDPM_TABLE_169[0], sizeof(ixDPM_TABLE_169)/sizeof(ixDPM_TABLE_169[0]), 0, 0 },
+	{ "ixDPM_TABLE_170", REG_SMC, 0x3f2a4, &ixDPM_TABLE_170[0], sizeof(ixDPM_TABLE_170)/sizeof(ixDPM_TABLE_170[0]), 0, 0 },
+	{ "ixDPM_TABLE_171", REG_SMC, 0x3f2a8, &ixDPM_TABLE_171[0], sizeof(ixDPM_TABLE_171)/sizeof(ixDPM_TABLE_171[0]), 0, 0 },
+	{ "ixDPM_TABLE_172", REG_SMC, 0x3f2ac, &ixDPM_TABLE_172[0], sizeof(ixDPM_TABLE_172)/sizeof(ixDPM_TABLE_172[0]), 0, 0 },
+	{ "ixDPM_TABLE_173", REG_SMC, 0x3f2b0, &ixDPM_TABLE_173[0], sizeof(ixDPM_TABLE_173)/sizeof(ixDPM_TABLE_173[0]), 0, 0 },
+	{ "ixDPM_TABLE_174", REG_SMC, 0x3f2b4, &ixDPM_TABLE_174[0], sizeof(ixDPM_TABLE_174)/sizeof(ixDPM_TABLE_174[0]), 0, 0 },
+	{ "ixDPM_TABLE_175", REG_SMC, 0x3f2b8, &ixDPM_TABLE_175[0], sizeof(ixDPM_TABLE_175)/sizeof(ixDPM_TABLE_175[0]), 0, 0 },
+	{ "ixDPM_TABLE_176", REG_SMC, 0x3f2bc, &ixDPM_TABLE_176[0], sizeof(ixDPM_TABLE_176)/sizeof(ixDPM_TABLE_176[0]), 0, 0 },
+	{ "ixDPM_TABLE_177", REG_SMC, 0x3f2c0, &ixDPM_TABLE_177[0], sizeof(ixDPM_TABLE_177)/sizeof(ixDPM_TABLE_177[0]), 0, 0 },
+	{ "ixDPM_TABLE_178", REG_SMC, 0x3f2c4, &ixDPM_TABLE_178[0], sizeof(ixDPM_TABLE_178)/sizeof(ixDPM_TABLE_178[0]), 0, 0 },
+	{ "ixDPM_TABLE_179", REG_SMC, 0x3f2c8, &ixDPM_TABLE_179[0], sizeof(ixDPM_TABLE_179)/sizeof(ixDPM_TABLE_179[0]), 0, 0 },
+	{ "ixDPM_TABLE_180", REG_SMC, 0x3f2cc, &ixDPM_TABLE_180[0], sizeof(ixDPM_TABLE_180)/sizeof(ixDPM_TABLE_180[0]), 0, 0 },
+	{ "ixDPM_TABLE_181", REG_SMC, 0x3f2d0, &ixDPM_TABLE_181[0], sizeof(ixDPM_TABLE_181)/sizeof(ixDPM_TABLE_181[0]), 0, 0 },
+	{ "ixDPM_TABLE_182", REG_SMC, 0x3f2d4, &ixDPM_TABLE_182[0], sizeof(ixDPM_TABLE_182)/sizeof(ixDPM_TABLE_182[0]), 0, 0 },
+	{ "ixDPM_TABLE_183", REG_SMC, 0x3f2d8, &ixDPM_TABLE_183[0], sizeof(ixDPM_TABLE_183)/sizeof(ixDPM_TABLE_183[0]), 0, 0 },
+	{ "ixDPM_TABLE_184", REG_SMC, 0x3f2dc, &ixDPM_TABLE_184[0], sizeof(ixDPM_TABLE_184)/sizeof(ixDPM_TABLE_184[0]), 0, 0 },
+	{ "ixDPM_TABLE_185", REG_SMC, 0x3f2e0, &ixDPM_TABLE_185[0], sizeof(ixDPM_TABLE_185)/sizeof(ixDPM_TABLE_185[0]), 0, 0 },
+	{ "ixDPM_TABLE_186", REG_SMC, 0x3f2e4, &ixDPM_TABLE_186[0], sizeof(ixDPM_TABLE_186)/sizeof(ixDPM_TABLE_186[0]), 0, 0 },
+	{ "ixDPM_TABLE_187", REG_SMC, 0x3f2e8, &ixDPM_TABLE_187[0], sizeof(ixDPM_TABLE_187)/sizeof(ixDPM_TABLE_187[0]), 0, 0 },
+	{ "ixDPM_TABLE_188", REG_SMC, 0x3f2ec, &ixDPM_TABLE_188[0], sizeof(ixDPM_TABLE_188)/sizeof(ixDPM_TABLE_188[0]), 0, 0 },
+	{ "ixDPM_TABLE_189", REG_SMC, 0x3f2f0, &ixDPM_TABLE_189[0], sizeof(ixDPM_TABLE_189)/sizeof(ixDPM_TABLE_189[0]), 0, 0 },
+	{ "ixDPM_TABLE_190", REG_SMC, 0x3f2f4, &ixDPM_TABLE_190[0], sizeof(ixDPM_TABLE_190)/sizeof(ixDPM_TABLE_190[0]), 0, 0 },
+	{ "ixDPM_TABLE_191", REG_SMC, 0x3f2f8, &ixDPM_TABLE_191[0], sizeof(ixDPM_TABLE_191)/sizeof(ixDPM_TABLE_191[0]), 0, 0 },
+	{ "ixFIRMWARE_FLAGS", REG_SMC, 0x3f800, &ixFIRMWARE_FLAGS[0], sizeof(ixFIRMWARE_FLAGS)/sizeof(ixFIRMWARE_FLAGS[0]), 0, 0 },
+	{ "ixTEMPERATURE_READ_ADDR", REG_SMC, 0x3f808, &ixTEMPERATURE_READ_ADDR[0], sizeof(ixTEMPERATURE_READ_ADDR)/sizeof(ixTEMPERATURE_READ_ADDR[0]), 0, 0 },
+	{ "ixCURRENT_GNB_TEMP", REG_SMC, 0x3f810, &ixCURRENT_GNB_TEMP[0], sizeof(ixCURRENT_GNB_TEMP)/sizeof(ixCURRENT_GNB_TEMP[0]), 0, 0 },
+	{ "ixCURRENT_GLOBAL_TEMP", REG_SMC, 0x3f814, &ixCURRENT_GLOBAL_TEMP[0], sizeof(ixCURRENT_GLOBAL_TEMP)/sizeof(ixCURRENT_GLOBAL_TEMP[0]), 0, 0 },
+	{ "ixFEATURE_STATUS", REG_SMC, 0x3f818, &ixFEATURE_STATUS[0], sizeof(ixFEATURE_STATUS)/sizeof(ixFEATURE_STATUS[0]), 0, 0 },
+	{ "ixPCIE_PLL_RECONF", REG_SMC, 0x3f81c, &ixPCIE_PLL_RECONF[0], sizeof(ixPCIE_PLL_RECONF)/sizeof(ixPCIE_PLL_RECONF[0]), 0, 0 },
+	{ "ixPM_INTERVAL_CNTL_0", REG_SMC, 0x3f820, &ixPM_INTERVAL_CNTL_0[0], sizeof(ixPM_INTERVAL_CNTL_0)/sizeof(ixPM_INTERVAL_CNTL_0[0]), 0, 0 },
+	{ "ixPM_INTERVAL_CNTL_1", REG_SMC, 0x3f824, &ixPM_INTERVAL_CNTL_1[0], sizeof(ixPM_INTERVAL_CNTL_1)/sizeof(ixPM_INTERVAL_CNTL_1[0]), 0, 0 },
+	{ "ixPM_INTERVAL_CNTL_2", REG_SMC, 0x3f82c, &ixPM_INTERVAL_CNTL_2[0], sizeof(ixPM_INTERVAL_CNTL_2)/sizeof(ixPM_INTERVAL_CNTL_2[0]), 0, 0 },
+	{ "ixVPC_INTERVAL_CNTL", REG_SMC, 0x3f830, &ixVPC_INTERVAL_CNTL[0], sizeof(ixVPC_INTERVAL_CNTL)/sizeof(ixVPC_INTERVAL_CNTL[0]), 0, 0 },
+	{ "ixDISP_PHY_TDP_LIMIT", REG_SMC, 0x3f834, &ixDISP_PHY_TDP_LIMIT[0], sizeof(ixDISP_PHY_TDP_LIMIT)/sizeof(ixDISP_PHY_TDP_LIMIT[0]), 0, 0 },
+	{ "ixFCH_PWR_CREDIT", REG_SMC, 0x3f838, &ixFCH_PWR_CREDIT[0], sizeof(ixFCH_PWR_CREDIT)/sizeof(ixFCH_PWR_CREDIT[0]), 0, 0 },
+	{ "ixPKGPWR_MV_AVG", REG_SMC, 0x3f83c, &ixPKGPWR_MV_AVG[0], sizeof(ixPKGPWR_MV_AVG)/sizeof(ixPKGPWR_MV_AVG[0]), 0, 0 },
+	{ "ixPACKAGE_POWER", REG_SMC, 0x3f840, &ixPACKAGE_POWER[0], sizeof(ixPACKAGE_POWER)/sizeof(ixPACKAGE_POWER[0]), 0, 0 },
+	{ "ixPKG_PWR_CNTL", REG_SMC, 0x3f844, &ixPKG_PWR_CNTL[0], sizeof(ixPKG_PWR_CNTL)/sizeof(ixPKG_PWR_CNTL[0]), 0, 0 },
+	{ "ixPKG_PWR_STATUS", REG_SMC, 0x3f848, &ixPKG_PWR_STATUS[0], sizeof(ixPKG_PWR_STATUS)/sizeof(ixPKG_PWR_STATUS[0]), 0, 0 },
+	{ "ixDISP_PHY_CONFIG", REG_SMC, 0x3f84c, &ixDISP_PHY_CONFIG[0], sizeof(ixDISP_PHY_CONFIG)/sizeof(ixDISP_PHY_CONFIG[0]), 0, 0 },
+	{ "ixGPU_TDP_LIMIT", REG_SMC, 0x3f850, &ixGPU_TDP_LIMIT[0], sizeof(ixGPU_TDP_LIMIT)/sizeof(ixGPU_TDP_LIMIT[0]), 0, 0 },
+	{ "ixEXT_API_IN_DATA_0_0", REG_SMC, 0x3f858, &ixEXT_API_IN_DATA_0_0[0], sizeof(ixEXT_API_IN_DATA_0_0)/sizeof(ixEXT_API_IN_DATA_0_0[0]), 0, 0 },
+	{ "ixEXT_API_IN_DATA_0_1", REG_SMC, 0x3f85c, &ixEXT_API_IN_DATA_0_1[0], sizeof(ixEXT_API_IN_DATA_0_1)/sizeof(ixEXT_API_IN_DATA_0_1[0]), 0, 0 },
+	{ "ixEXT_API_IN_DATA_0_2", REG_SMC, 0x3f860, &ixEXT_API_IN_DATA_0_2[0], sizeof(ixEXT_API_IN_DATA_0_2)/sizeof(ixEXT_API_IN_DATA_0_2[0]), 0, 0 },
+	{ "ixEXT_API_IN_DATA_0_3", REG_SMC, 0x3f864, &ixEXT_API_IN_DATA_0_3[0], sizeof(ixEXT_API_IN_DATA_0_3)/sizeof(ixEXT_API_IN_DATA_0_3[0]), 0, 0 },
+	{ "ixEXT_API_OUT_DATA_0_0", REG_SMC, 0x3f868, &ixEXT_API_OUT_DATA_0_0[0], sizeof(ixEXT_API_OUT_DATA_0_0)/sizeof(ixEXT_API_OUT_DATA_0_0[0]), 0, 0 },
+	{ "ixEXT_API_OUT_DATA_0_1", REG_SMC, 0x3f86c, &ixEXT_API_OUT_DATA_0_1[0], sizeof(ixEXT_API_OUT_DATA_0_1)/sizeof(ixEXT_API_OUT_DATA_0_1[0]), 0, 0 },
+	{ "ixEXT_API_OUT_DATA_0_2", REG_SMC, 0x3f870, &ixEXT_API_OUT_DATA_0_2[0], sizeof(ixEXT_API_OUT_DATA_0_2)/sizeof(ixEXT_API_OUT_DATA_0_2[0]), 0, 0 },
+	{ "ixEXT_API_OUT_DATA_0_3", REG_SMC, 0x3f874, &ixEXT_API_OUT_DATA_0_3[0], sizeof(ixEXT_API_OUT_DATA_0_3)/sizeof(ixEXT_API_OUT_DATA_0_3[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_1", REG_SMC, 0x3f900, &ixSOFT_REGISTERS_TABLE_1[0], sizeof(ixSOFT_REGISTERS_TABLE_1)/sizeof(ixSOFT_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_2", REG_SMC, 0x3f904, &ixSOFT_REGISTERS_TABLE_2[0], sizeof(ixSOFT_REGISTERS_TABLE_2)/sizeof(ixSOFT_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_3", REG_SMC, 0x3f908, &ixSOFT_REGISTERS_TABLE_3[0], sizeof(ixSOFT_REGISTERS_TABLE_3)/sizeof(ixSOFT_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_4", REG_SMC, 0x3f90c, &ixSOFT_REGISTERS_TABLE_4[0], sizeof(ixSOFT_REGISTERS_TABLE_4)/sizeof(ixSOFT_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_5", REG_SMC, 0x3f910, &ixSOFT_REGISTERS_TABLE_5[0], sizeof(ixSOFT_REGISTERS_TABLE_5)/sizeof(ixSOFT_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_6", REG_SMC, 0x3f914, &ixSOFT_REGISTERS_TABLE_6[0], sizeof(ixSOFT_REGISTERS_TABLE_6)/sizeof(ixSOFT_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_7", REG_SMC, 0x3f918, &ixSOFT_REGISTERS_TABLE_7[0], sizeof(ixSOFT_REGISTERS_TABLE_7)/sizeof(ixSOFT_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_8", REG_SMC, 0x3f91c, &ixSOFT_REGISTERS_TABLE_8[0], sizeof(ixSOFT_REGISTERS_TABLE_8)/sizeof(ixSOFT_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_9", REG_SMC, 0x3f920, &ixSOFT_REGISTERS_TABLE_9[0], sizeof(ixSOFT_REGISTERS_TABLE_9)/sizeof(ixSOFT_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_10", REG_SMC, 0x3f924, &ixSOFT_REGISTERS_TABLE_10[0], sizeof(ixSOFT_REGISTERS_TABLE_10)/sizeof(ixSOFT_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_11", REG_SMC, 0x3f928, &ixSOFT_REGISTERS_TABLE_11[0], sizeof(ixSOFT_REGISTERS_TABLE_11)/sizeof(ixSOFT_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_12", REG_SMC, 0x3f92c, &ixSOFT_REGISTERS_TABLE_12[0], sizeof(ixSOFT_REGISTERS_TABLE_12)/sizeof(ixSOFT_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_13", REG_SMC, 0x3f930, &ixSOFT_REGISTERS_TABLE_13[0], sizeof(ixSOFT_REGISTERS_TABLE_13)/sizeof(ixSOFT_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_14", REG_SMC, 0x3f934, &ixSOFT_REGISTERS_TABLE_14[0], sizeof(ixSOFT_REGISTERS_TABLE_14)/sizeof(ixSOFT_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_15", REG_SMC, 0x3f938, &ixSOFT_REGISTERS_TABLE_15[0], sizeof(ixSOFT_REGISTERS_TABLE_15)/sizeof(ixSOFT_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_16", REG_SMC, 0x3f93c, &ixSOFT_REGISTERS_TABLE_16[0], sizeof(ixSOFT_REGISTERS_TABLE_16)/sizeof(ixSOFT_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_17", REG_SMC, 0x3f940, &ixSOFT_REGISTERS_TABLE_17[0], sizeof(ixSOFT_REGISTERS_TABLE_17)/sizeof(ixSOFT_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_18", REG_SMC, 0x3f944, &ixSOFT_REGISTERS_TABLE_18[0], sizeof(ixSOFT_REGISTERS_TABLE_18)/sizeof(ixSOFT_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_19", REG_SMC, 0x3f948, &ixSOFT_REGISTERS_TABLE_19[0], sizeof(ixSOFT_REGISTERS_TABLE_19)/sizeof(ixSOFT_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_20", REG_SMC, 0x3f94c, &ixSOFT_REGISTERS_TABLE_20[0], sizeof(ixSOFT_REGISTERS_TABLE_20)/sizeof(ixSOFT_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_21", REG_SMC, 0x3f950, &ixSOFT_REGISTERS_TABLE_21[0], sizeof(ixSOFT_REGISTERS_TABLE_21)/sizeof(ixSOFT_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixBAPM_PARAMETERS", REG_SMC, 0x3f984, &ixBAPM_PARAMETERS[0], sizeof(ixBAPM_PARAMETERS)/sizeof(ixBAPM_PARAMETERS[0]), 0, 0 },
+	{ "ixBAPM_PARAMETERS_2", REG_SMC, 0x3f988, &ixBAPM_PARAMETERS_2[0], sizeof(ixBAPM_PARAMETERS_2)/sizeof(ixBAPM_PARAMETERS_2[0]), 0, 0 },
+	{ "ixBAPM_PARAMETERS_3", REG_SMC, 0x3f98c, &ixBAPM_PARAMETERS_3[0], sizeof(ixBAPM_PARAMETERS_3)/sizeof(ixBAPM_PARAMETERS_3[0]), 0, 0 },
+	{ "ixBAPM_PARAMETERS_4", REG_SMC, 0x3f990, &ixBAPM_PARAMETERS_4[0], sizeof(ixBAPM_PARAMETERS_4)/sizeof(ixBAPM_PARAMETERS_4[0]), 0, 0 },
+	{ "ixSMU_SVI_TELEMETRY", REG_SMC, 0x3f994, &ixSMU_SVI_TELEMETRY[0], sizeof(ixSMU_SVI_TELEMETRY)/sizeof(ixSMU_SVI_TELEMETRY[0]), 0, 0 },
+	{ "ixBAPM_STATUS", REG_SMC, 0x3f998, &ixBAPM_STATUS[0], sizeof(ixBAPM_STATUS)/sizeof(ixBAPM_STATUS[0]), 0, 0 },
+	{ "ixSMU_HTC_STATUS", REG_SMC, 0x3f99c, &ixSMU_HTC_STATUS[0], sizeof(ixSMU_HTC_STATUS)/sizeof(ixSMU_HTC_STATUS[0]), 0, 0 },
+	{ "ixSMU_VPC_STATUS", REG_SMC, 0x3f9a0, &ixSMU_VPC_STATUS[0], sizeof(ixSMU_VPC_STATUS)/sizeof(ixSMU_VPC_STATUS[0]), 0, 0 },
+	{ "ixENTITY_TEMPERATURES_1", REG_SMC, 0x3f9a4, &ixENTITY_TEMPERATURES_1[0], sizeof(ixENTITY_TEMPERATURES_1)/sizeof(ixENTITY_TEMPERATURES_1[0]), 0, 0 },
+	{ "ixENTITY_TEMPERATURES_2", REG_SMC, 0x3f9a8, &ixENTITY_TEMPERATURES_2[0], sizeof(ixENTITY_TEMPERATURES_2)/sizeof(ixENTITY_TEMPERATURES_2[0]), 0, 0 },
+	{ "ixENTITY_TEMPERATURES_3", REG_SMC, 0x3f9ac, &ixENTITY_TEMPERATURES_3[0], sizeof(ixENTITY_TEMPERATURES_3)/sizeof(ixENTITY_TEMPERATURES_3[0]), 0, 0 },
+	{ "ixCU_POWER", REG_SMC, 0x3f9b0, &ixCU_POWER[0], sizeof(ixCU_POWER)/sizeof(ixCU_POWER[0]), 0, 0 },
+	{ "ixGPU_POWER", REG_SMC, 0x3f9b4, &ixGPU_POWER[0], sizeof(ixGPU_POWER)/sizeof(ixGPU_POWER[0]), 0, 0 },
+	{ "ixNTE_POWER", REG_SMC, 0x3f9b8, &ixNTE_POWER[0], sizeof(ixNTE_POWER)/sizeof(ixNTE_POWER[0]), 0, 0 },
+	{ "ixTDC_STATUS", REG_SMC, 0x3f9d0, &ixTDC_STATUS[0], sizeof(ixTDC_STATUS)/sizeof(ixTDC_STATUS[0]), 0, 0 },
+	{ "ixTDC_MV_AVERAGE", REG_SMC, 0x3f9d4, &ixTDC_MV_AVERAGE[0], sizeof(ixTDC_MV_AVERAGE)/sizeof(ixTDC_MV_AVERAGE[0]), 0, 0 },
+	{ "ixPM_CONFIG", REG_SMC, 0x3f9d8, &ixPM_CONFIG[0], sizeof(ixPM_CONFIG)/sizeof(ixPM_CONFIG[0]), 0, 0 },
+	{ "ixTE0_TEMPERATURE_READ_ADDR", REG_SMC, 0x3f9dc, &ixTE0_TEMPERATURE_READ_ADDR[0], sizeof(ixTE0_TEMPERATURE_READ_ADDR)/sizeof(ixTE0_TEMPERATURE_READ_ADDR[0]), 0, 0 },
+	{ "ixTE1_TEMPERATURE_READ_ADDR", REG_SMC, 0x3f9e0, &ixTE1_TEMPERATURE_READ_ADDR[0], sizeof(ixTE1_TEMPERATURE_READ_ADDR)/sizeof(ixTE1_TEMPERATURE_READ_ADDR[0]), 0, 0 },
+	{ "ixTE2_TEMPERATURE_READ_ADDR", REG_SMC, 0x3f9e4, &ixTE2_TEMPERATURE_READ_ADDR[0], sizeof(ixTE2_TEMPERATURE_READ_ADDR)/sizeof(ixTE2_TEMPERATURE_READ_ADDR[0]), 0, 0 },
+	{ "ixNB_DPM_CONFIG_1", REG_SMC, 0x3f9e8, &ixNB_DPM_CONFIG_1[0], sizeof(ixNB_DPM_CONFIG_1)/sizeof(ixNB_DPM_CONFIG_1[0]), 0, 0 },
+	{ "ixNB_DPM_CONFIG_2", REG_SMC, 0x3f9ec, &ixNB_DPM_CONFIG_2[0], sizeof(ixNB_DPM_CONFIG_2)/sizeof(ixNB_DPM_CONFIG_2[0]), 0, 0 },
+	{ "ixNB_DPM_CONFIG_3", REG_SMC, 0x3f9f0, &ixNB_DPM_CONFIG_3[0], sizeof(ixNB_DPM_CONFIG_3)/sizeof(ixNB_DPM_CONFIG_3[0]), 0, 0 },
+	{ "ixSMU_IDD_OVERRIDE", REG_SMC, 0x3f9fc, &ixSMU_IDD_OVERRIDE[0], sizeof(ixSMU_IDD_OVERRIDE)/sizeof(ixSMU_IDD_OVERRIDE[0]), 0, 0 },
+	{ "ixAVS_CONFIG", REG_SMC, 0x3fa00, &ixAVS_CONFIG[0], sizeof(ixAVS_CONFIG)/sizeof(ixAVS_CONFIG[0]), 0, 0 },
+	{ "ixTDC_VRM_LIMIT", REG_SMC, 0x3fa04, &ixTDC_VRM_LIMIT[0], sizeof(ixTDC_VRM_LIMIT)/sizeof(ixTDC_VRM_LIMIT[0]), 0, 0 },
+	{ "ixCU0_PSM_CONFIG", REG_SMC, 0x3fa08, &ixCU0_PSM_CONFIG[0], sizeof(ixCU0_PSM_CONFIG)/sizeof(ixCU0_PSM_CONFIG[0]), 0, 0 },
+	{ "ixCU1_PSM_CONFIG", REG_SMC, 0x3fa0c, &ixCU1_PSM_CONFIG[0], sizeof(ixCU1_PSM_CONFIG)/sizeof(ixCU1_PSM_CONFIG[0]), 0, 0 },
+	{ "ixSPMI_CONFIG", REG_SMC, 0x3fa10, &ixSPMI_CONFIG[0], sizeof(ixSPMI_CONFIG)/sizeof(ixSPMI_CONFIG[0]), 0, 0 },
+	{ "ixSPMI_SMC_CHAIN_ADDR", REG_SMC, 0x3fa14, &ixSPMI_SMC_CHAIN_ADDR[0], sizeof(ixSPMI_SMC_CHAIN_ADDR)/sizeof(ixSPMI_SMC_CHAIN_ADDR[0]), 0, 0 },
+	{ "ixSPMI_STATUS", REG_SMC, 0x3fa30, &ixSPMI_STATUS[0], sizeof(ixSPMI_STATUS)/sizeof(ixSPMI_STATUS[0]), 0, 0 },
+	{ "ixAVSNB_CONFIG", REG_SMC, 0x3fa34, &ixAVSNB_CONFIG[0], sizeof(ixAVSNB_CONFIG)/sizeof(ixAVSNB_CONFIG[0]), 0, 0 },
+	{ "ixHTC_CONFIG", REG_SMC, 0x3fa38, &ixHTC_CONFIG[0], sizeof(ixHTC_CONFIG)/sizeof(ixHTC_CONFIG[0]), 0, 0 },
+	{ "ixAVS_CU0_TEMPERATURE_SENSOR", REG_SMC, 0x3fa3c, &ixAVS_CU0_TEMPERATURE_SENSOR[0], sizeof(ixAVS_CU0_TEMPERATURE_SENSOR)/sizeof(ixAVS_CU0_TEMPERATURE_SENSOR[0]), 0, 0 },
+	{ "ixAVS_CU1_TEMPERATURE_SENSOR", REG_SMC, 0x3fa40, &ixAVS_CU1_TEMPERATURE_SENSOR[0], sizeof(ixAVS_CU1_TEMPERATURE_SENSOR)/sizeof(ixAVS_CU1_TEMPERATURE_SENSOR[0]), 0, 0 },
+	{ "ixAVS_GNB_TEMPERATURE_SENSOR", REG_SMC, 0x3fa44, &ixAVS_GNB_TEMPERATURE_SENSOR[0], sizeof(ixAVS_GNB_TEMPERATURE_SENSOR)/sizeof(ixAVS_GNB_TEMPERATURE_SENSOR[0]), 0, 0 },
+	{ "ixAVS_UNB_TEMPERATURE_SENSOR", REG_SMC, 0x3fa48, &ixAVS_UNB_TEMPERATURE_SENSOR[0], sizeof(ixAVS_UNB_TEMPERATURE_SENSOR)/sizeof(ixAVS_UNB_TEMPERATURE_SENSOR[0]), 0, 0 },
+	{ "ixSMU_MONITOR_PORT80_MMIO_ADDR", REG_SMC, 0x3fa4c, &ixSMU_MONITOR_PORT80_MMIO_ADDR[0], sizeof(ixSMU_MONITOR_PORT80_MMIO_ADDR)/sizeof(ixSMU_MONITOR_PORT80_MMIO_ADDR[0]), 0, 0 },
+	{ "ixSMU_MONITOR_PORT80_MEMBASE_HI", REG_SMC, 0x3fa50, &ixSMU_MONITOR_PORT80_MEMBASE_HI[0], sizeof(ixSMU_MONITOR_PORT80_MEMBASE_HI)/sizeof(ixSMU_MONITOR_PORT80_MEMBASE_HI[0]), 0, 0 },
+	{ "ixSMU_MONITOR_PORT80_MEMBASE_LO", REG_SMC, 0x3fa54, &ixSMU_MONITOR_PORT80_MEMBASE_LO[0], sizeof(ixSMU_MONITOR_PORT80_MEMBASE_LO)/sizeof(ixSMU_MONITOR_PORT80_MEMBASE_LO[0]), 0, 0 },
+	{ "ixSMU_MONITOR_PORT80_MEMSETUP", REG_SMC, 0x3fa58, &ixSMU_MONITOR_PORT80_MEMSETUP[0], sizeof(ixSMU_MONITOR_PORT80_MEMSETUP)/sizeof(ixSMU_MONITOR_PORT80_MEMSETUP[0]), 0, 0 },
+	{ "ixSMU_MONITOR_PORT80_CTRL", REG_SMC, 0x3fa5c, &ixSMU_MONITOR_PORT80_CTRL[0], sizeof(ixSMU_MONITOR_PORT80_CTRL)/sizeof(ixSMU_MONITOR_PORT80_CTRL[0]), 0, 0 },
+	{ "ixSMU_TCEN_ALIVE", REG_SMC, 0x3fa60, &ixSMU_TCEN_ALIVE[0], sizeof(ixSMU_TCEN_ALIVE)/sizeof(ixSMU_TCEN_ALIVE[0]), 0, 0 },
+	{ "ixPDM_STATUS", REG_SMC, 0x3fa64, &ixPDM_STATUS[0], sizeof(ixPDM_STATUS)/sizeof(ixPDM_STATUS[0]), 0, 0 },
+	{ "ixPDM_CNTL_1", REG_SMC, 0x3fa68, &ixPDM_CNTL_1[0], sizeof(ixPDM_CNTL_1)/sizeof(ixPDM_CNTL_1[0]), 0, 0 },
+	{ "ixPDM_CNTL_2", REG_SMC, 0x3fa6c, &ixPDM_CNTL_2[0], sizeof(ixPDM_CNTL_2)/sizeof(ixPDM_CNTL_2[0]), 0, 0 },
+	{ "ixPDM_CNTL_3", REG_SMC, 0x3fa70, &ixPDM_CNTL_3[0], sizeof(ixPDM_CNTL_3)/sizeof(ixPDM_CNTL_3[0]), 0, 0 },
+	{ "ixPM_FUSES_1", REG_SMC, 0x3fa80, &ixPM_FUSES_1[0], sizeof(ixPM_FUSES_1)/sizeof(ixPM_FUSES_1[0]), 0, 0 },
+	{ "ixPM_FUSES_2", REG_SMC, 0x3fa84, &ixPM_FUSES_2[0], sizeof(ixPM_FUSES_2)/sizeof(ixPM_FUSES_2[0]), 0, 0 },
+	{ "ixPM_FUSES_3", REG_SMC, 0x3fa88, &ixPM_FUSES_3[0], sizeof(ixPM_FUSES_3)/sizeof(ixPM_FUSES_3[0]), 0, 0 },
+	{ "ixPM_FUSES_4", REG_SMC, 0x3fa8c, &ixPM_FUSES_4[0], sizeof(ixPM_FUSES_4)/sizeof(ixPM_FUSES_4[0]), 0, 0 },
+	{ "ixPM_FUSES_5", REG_SMC, 0x3fa90, &ixPM_FUSES_5[0], sizeof(ixPM_FUSES_5)/sizeof(ixPM_FUSES_5[0]), 0, 0 },
+	{ "ixPM_FUSES_6", REG_SMC, 0x3fa94, &ixPM_FUSES_6[0], sizeof(ixPM_FUSES_6)/sizeof(ixPM_FUSES_6[0]), 0, 0 },
+	{ "ixPM_FUSES_7", REG_SMC, 0x3fa98, &ixPM_FUSES_7[0], sizeof(ixPM_FUSES_7)/sizeof(ixPM_FUSES_7[0]), 0, 0 },
+	{ "ixPM_FUSES_8", REG_SMC, 0x3fa9c, &ixPM_FUSES_8[0], sizeof(ixPM_FUSES_8)/sizeof(ixPM_FUSES_8[0]), 0, 0 },
+	{ "ixPM_FUSES_9", REG_SMC, 0x3faa0, &ixPM_FUSES_9[0], sizeof(ixPM_FUSES_9)/sizeof(ixPM_FUSES_9[0]), 0, 0 },
+	{ "ixPM_FUSES_10", REG_SMC, 0x3faa4, &ixPM_FUSES_10[0], sizeof(ixPM_FUSES_10)/sizeof(ixPM_FUSES_10[0]), 0, 0 },
+	{ "ixPM_FUSES_11", REG_SMC, 0x3faa8, &ixPM_FUSES_11[0], sizeof(ixPM_FUSES_11)/sizeof(ixPM_FUSES_11[0]), 0, 0 },
+	{ "ixPM_FUSES_12", REG_SMC, 0x3faac, &ixPM_FUSES_12[0], sizeof(ixPM_FUSES_12)/sizeof(ixPM_FUSES_12[0]), 0, 0 },
+	{ "ixPM_FUSES_13", REG_SMC, 0x3fab0, &ixPM_FUSES_13[0], sizeof(ixPM_FUSES_13)/sizeof(ixPM_FUSES_13[0]), 0, 0 },
+	{ "ixPM_FUSES_14", REG_SMC, 0x3fab4, &ixPM_FUSES_14[0], sizeof(ixPM_FUSES_14)/sizeof(ixPM_FUSES_14[0]), 0, 0 },
+	{ "ixPM_FUSES_15", REG_SMC, 0x3fab8, &ixPM_FUSES_15[0], sizeof(ixPM_FUSES_15)/sizeof(ixPM_FUSES_15[0]), 0, 0 },
+	{ "ixPM_FUSES_16", REG_SMC, 0x3fabc, &ixPM_FUSES_16[0], sizeof(ixPM_FUSES_16)/sizeof(ixPM_FUSES_16[0]), 0, 0 },
+	{ "ixPM_FUSES_17", REG_SMC, 0x3fac0, &ixPM_FUSES_17[0], sizeof(ixPM_FUSES_17)/sizeof(ixPM_FUSES_17[0]), 0, 0 },
+	{ "ixPM_FUSES_18", REG_SMC, 0x3fac4, &ixPM_FUSES_18[0], sizeof(ixPM_FUSES_18)/sizeof(ixPM_FUSES_18[0]), 0, 0 },
+	{ "ixPM_FUSES_19", REG_SMC, 0x3fac8, &ixPM_FUSES_19[0], sizeof(ixPM_FUSES_19)/sizeof(ixPM_FUSES_19[0]), 0, 0 },
+	{ "ixPM_FUSES_20", REG_SMC, 0x3facc, &ixPM_FUSES_20[0], sizeof(ixPM_FUSES_20)/sizeof(ixPM_FUSES_20[0]), 0, 0 },
+	{ "ixPM_FUSES_21", REG_SMC, 0x3fad0, &ixPM_FUSES_21[0], sizeof(ixPM_FUSES_21)/sizeof(ixPM_FUSES_21[0]), 0, 0 },
+	{ "ixPM_FUSES_22", REG_SMC, 0x3fad4, &ixPM_FUSES_22[0], sizeof(ixPM_FUSES_22)/sizeof(ixPM_FUSES_22[0]), 0, 0 },
+	{ "ixPM_FUSES_23", REG_SMC, 0x3fad8, &ixPM_FUSES_23[0], sizeof(ixPM_FUSES_23)/sizeof(ixPM_FUSES_23[0]), 0, 0 },
+	{ "ixPM_FUSES_24", REG_SMC, 0x3fadc, &ixPM_FUSES_24[0], sizeof(ixPM_FUSES_24)/sizeof(ixPM_FUSES_24[0]), 0, 0 },
+	{ "ixPM_FUSES_25", REG_SMC, 0x3fae0, &ixPM_FUSES_25[0], sizeof(ixPM_FUSES_25)/sizeof(ixPM_FUSES_25[0]), 0, 0 },
+	{ "ixPM_FUSES_26", REG_SMC, 0x3fae4, &ixPM_FUSES_26[0], sizeof(ixPM_FUSES_26)/sizeof(ixPM_FUSES_26[0]), 0, 0 },
+	{ "ixPM_FUSES_27", REG_SMC, 0x3fae8, &ixPM_FUSES_27[0], sizeof(ixPM_FUSES_27)/sizeof(ixPM_FUSES_27[0]), 0, 0 },
+	{ "ixPM_FUSES_28", REG_SMC, 0x3faec, &ixPM_FUSES_28[0], sizeof(ixPM_FUSES_28)/sizeof(ixPM_FUSES_28[0]), 0, 0 },
+	{ "ixPM_FUSES_29", REG_SMC, 0x3faf0, &ixPM_FUSES_29[0], sizeof(ixPM_FUSES_29)/sizeof(ixPM_FUSES_29[0]), 0, 0 },
+	{ "ixPM_FUSES_30", REG_SMC, 0x3faf4, &ixPM_FUSES_30[0], sizeof(ixPM_FUSES_30)/sizeof(ixPM_FUSES_30[0]), 0, 0 },
+	{ "ixPM_FUSES_31", REG_SMC, 0x3faf8, &ixPM_FUSES_31[0], sizeof(ixPM_FUSES_31)/sizeof(ixPM_FUSES_31[0]), 0, 0 },
+	{ "ixPM_FUSES_32", REG_SMC, 0x3fafc, &ixPM_FUSES_32[0], sizeof(ixPM_FUSES_32)/sizeof(ixPM_FUSES_32[0]), 0, 0 },
+	{ "ixPM_FUSES_33", REG_SMC, 0x3fb00, &ixPM_FUSES_33[0], sizeof(ixPM_FUSES_33)/sizeof(ixPM_FUSES_33[0]), 0, 0 },
+	{ "ixPM_FUSES_34", REG_SMC, 0x3fb04, &ixPM_FUSES_34[0], sizeof(ixPM_FUSES_34)/sizeof(ixPM_FUSES_34[0]), 0, 0 },
+	{ "ixPM_FUSES_35", REG_SMC, 0x3fb08, &ixPM_FUSES_35[0], sizeof(ixPM_FUSES_35)/sizeof(ixPM_FUSES_35[0]), 0, 0 },
+	{ "ixPM_FUSES_36", REG_SMC, 0x3fb0c, &ixPM_FUSES_36[0], sizeof(ixPM_FUSES_36)/sizeof(ixPM_FUSES_36[0]), 0, 0 },
+	{ "ixPM_FUSES_37", REG_SMC, 0x3fb10, &ixPM_FUSES_37[0], sizeof(ixPM_FUSES_37)/sizeof(ixPM_FUSES_37[0]), 0, 0 },
+	{ "ixPM_FUSES_38", REG_SMC, 0x3fb14, &ixPM_FUSES_38[0], sizeof(ixPM_FUSES_38)/sizeof(ixPM_FUSES_38[0]), 0, 0 },
+	{ "ixPM_FUSES_39", REG_SMC, 0x3fb18, &ixPM_FUSES_39[0], sizeof(ixPM_FUSES_39)/sizeof(ixPM_FUSES_39[0]), 0, 0 },
+	{ "ixPM_FUSES_40", REG_SMC, 0x3fb1c, &ixPM_FUSES_40[0], sizeof(ixPM_FUSES_40)/sizeof(ixPM_FUSES_40[0]), 0, 0 },
+	{ "ixPM_FUSES_41", REG_SMC, 0x3fb20, &ixPM_FUSES_41[0], sizeof(ixPM_FUSES_41)/sizeof(ixPM_FUSES_41[0]), 0, 0 },
+	{ "ixPM_FUSES_42", REG_SMC, 0x3fb24, &ixPM_FUSES_42[0], sizeof(ixPM_FUSES_42)/sizeof(ixPM_FUSES_42[0]), 0, 0 },
+	{ "ixPM_FUSES_43", REG_SMC, 0x3fb28, &ixPM_FUSES_43[0], sizeof(ixPM_FUSES_43)/sizeof(ixPM_FUSES_43[0]), 0, 0 },
+	{ "ixPM_FUSES_44", REG_SMC, 0x3fb2c, &ixPM_FUSES_44[0], sizeof(ixPM_FUSES_44)/sizeof(ixPM_FUSES_44[0]), 0, 0 },
+	{ "ixPM_FUSES_45", REG_SMC, 0x3fb30, &ixPM_FUSES_45[0], sizeof(ixPM_FUSES_45)/sizeof(ixPM_FUSES_45[0]), 0, 0 },
+	{ "ixPM_FUSES_46", REG_SMC, 0x3fb34, &ixPM_FUSES_46[0], sizeof(ixPM_FUSES_46)/sizeof(ixPM_FUSES_46[0]), 0, 0 },
+	{ "ixPM_FUSES_47", REG_SMC, 0x3fb38, &ixPM_FUSES_47[0], sizeof(ixPM_FUSES_47)/sizeof(ixPM_FUSES_47[0]), 0, 0 },
+	{ "ixPM_FUSES_48", REG_SMC, 0x3fb3c, &ixPM_FUSES_48[0], sizeof(ixPM_FUSES_48)/sizeof(ixPM_FUSES_48[0]), 0, 0 },
+	{ "ixPM_FUSES_49", REG_SMC, 0x3fb40, &ixPM_FUSES_49[0], sizeof(ixPM_FUSES_49)/sizeof(ixPM_FUSES_49[0]), 0, 0 },
+	{ "ixPM_FUSES_50", REG_SMC, 0x3fb44, &ixPM_FUSES_50[0], sizeof(ixPM_FUSES_50)/sizeof(ixPM_FUSES_50[0]), 0, 0 },
+	{ "ixPM_FUSES_51", REG_SMC, 0x3fb48, &ixPM_FUSES_51[0], sizeof(ixPM_FUSES_51)/sizeof(ixPM_FUSES_51[0]), 0, 0 },
+	{ "ixPM_FUSES_52", REG_SMC, 0x3fb4c, &ixPM_FUSES_52[0], sizeof(ixPM_FUSES_52)/sizeof(ixPM_FUSES_52[0]), 0, 0 },
+	{ "ixPM_FUSES_53", REG_SMC, 0x3fb50, &ixPM_FUSES_53[0], sizeof(ixPM_FUSES_53)/sizeof(ixPM_FUSES_53[0]), 0, 0 },
+	{ "ixPM_FUSES_54", REG_SMC, 0x3fb54, &ixPM_FUSES_54[0], sizeof(ixPM_FUSES_54)/sizeof(ixPM_FUSES_54[0]), 0, 0 },
+	{ "ixPM_FUSES_55", REG_SMC, 0x3fb58, &ixPM_FUSES_55[0], sizeof(ixPM_FUSES_55)/sizeof(ixPM_FUSES_55[0]), 0, 0 },
+	{ "ixPM_FUSES_56", REG_SMC, 0x3fb5c, &ixPM_FUSES_56[0], sizeof(ixPM_FUSES_56)/sizeof(ixPM_FUSES_56[0]), 0, 0 },
+	{ "ixPM_FUSES_57", REG_SMC, 0x3fb60, &ixPM_FUSES_57[0], sizeof(ixPM_FUSES_57)/sizeof(ixPM_FUSES_57[0]), 0, 0 },
+	{ "ixPM_FUSES_58", REG_SMC, 0x3fb64, &ixPM_FUSES_58[0], sizeof(ixPM_FUSES_58)/sizeof(ixPM_FUSES_58[0]), 0, 0 },
+	{ "ixPM_FUSES_59", REG_SMC, 0x3fb68, &ixPM_FUSES_59[0], sizeof(ixPM_FUSES_59)/sizeof(ixPM_FUSES_59[0]), 0, 0 },
+	{ "ixPM_FUSES_60", REG_SMC, 0x3fb6c, &ixPM_FUSES_60[0], sizeof(ixPM_FUSES_60)/sizeof(ixPM_FUSES_60[0]), 0, 0 },
+	{ "ixPM_FUSES_61", REG_SMC, 0x3fb70, &ixPM_FUSES_61[0], sizeof(ixPM_FUSES_61)/sizeof(ixPM_FUSES_61[0]), 0, 0 },
+	{ "ixPM_FUSES_62", REG_SMC, 0x3fb74, &ixPM_FUSES_62[0], sizeof(ixPM_FUSES_62)/sizeof(ixPM_FUSES_62[0]), 0, 0 },
+	{ "ixPM_FUSES_63", REG_SMC, 0x3fb78, &ixPM_FUSES_63[0], sizeof(ixPM_FUSES_63)/sizeof(ixPM_FUSES_63[0]), 0, 0 },
+	{ "ixPM_FUSES_64", REG_SMC, 0x3fb7c, &ixPM_FUSES_64[0], sizeof(ixPM_FUSES_64)/sizeof(ixPM_FUSES_64[0]), 0, 0 },
+	{ "ixPM_FUSES_65", REG_SMC, 0x3fb80, &ixPM_FUSES_65[0], sizeof(ixPM_FUSES_65)/sizeof(ixPM_FUSES_65[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_0_CNTL_0", REG_SMC, 0x3fd00, &ixSMU_LCLK_DPM_STATE_0_CNTL_0[0], sizeof(ixSMU_LCLK_DPM_STATE_0_CNTL_0)/sizeof(ixSMU_LCLK_DPM_STATE_0_CNTL_0[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_0_CNTL_1", REG_SMC, 0x3fd04, &ixSMU_LCLK_DPM_STATE_0_CNTL_1[0], sizeof(ixSMU_LCLK_DPM_STATE_0_CNTL_1)/sizeof(ixSMU_LCLK_DPM_STATE_0_CNTL_1[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_0_CNTL_2", REG_SMC, 0x3fd08, &ixSMU_LCLK_DPM_STATE_0_CNTL_2[0], sizeof(ixSMU_LCLK_DPM_STATE_0_CNTL_2)/sizeof(ixSMU_LCLK_DPM_STATE_0_CNTL_2[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_0_CNTL_3", REG_SMC, 0x3fd0c, &ixSMU_LCLK_DPM_STATE_0_CNTL_3[0], sizeof(ixSMU_LCLK_DPM_STATE_0_CNTL_3)/sizeof(ixSMU_LCLK_DPM_STATE_0_CNTL_3[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD", REG_SMC, 0x3fd10, &ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD[0], sizeof(ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD)/sizeof(ixSMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_1_CNTL_0", REG_SMC, 0x3fd14, &ixSMU_LCLK_DPM_STATE_1_CNTL_0[0], sizeof(ixSMU_LCLK_DPM_STATE_1_CNTL_0)/sizeof(ixSMU_LCLK_DPM_STATE_1_CNTL_0[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_1_CNTL_1", REG_SMC, 0x3fd18, &ixSMU_LCLK_DPM_STATE_1_CNTL_1[0], sizeof(ixSMU_LCLK_DPM_STATE_1_CNTL_1)/sizeof(ixSMU_LCLK_DPM_STATE_1_CNTL_1[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_1_CNTL_2", REG_SMC, 0x3fd1c, &ixSMU_LCLK_DPM_STATE_1_CNTL_2[0], sizeof(ixSMU_LCLK_DPM_STATE_1_CNTL_2)/sizeof(ixSMU_LCLK_DPM_STATE_1_CNTL_2[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_1_CNTL_3", REG_SMC, 0x3fd20, &ixSMU_LCLK_DPM_STATE_1_CNTL_3[0], sizeof(ixSMU_LCLK_DPM_STATE_1_CNTL_3)/sizeof(ixSMU_LCLK_DPM_STATE_1_CNTL_3[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD", REG_SMC, 0x3fd24, &ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD[0], sizeof(ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD)/sizeof(ixSMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_2_CNTL_0", REG_SMC, 0x3fd28, &ixSMU_LCLK_DPM_STATE_2_CNTL_0[0], sizeof(ixSMU_LCLK_DPM_STATE_2_CNTL_0)/sizeof(ixSMU_LCLK_DPM_STATE_2_CNTL_0[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_2_CNTL_1", REG_SMC, 0x3fd2c, &ixSMU_LCLK_DPM_STATE_2_CNTL_1[0], sizeof(ixSMU_LCLK_DPM_STATE_2_CNTL_1)/sizeof(ixSMU_LCLK_DPM_STATE_2_CNTL_1[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_2_CNTL_2", REG_SMC, 0x3fd30, &ixSMU_LCLK_DPM_STATE_2_CNTL_2[0], sizeof(ixSMU_LCLK_DPM_STATE_2_CNTL_2)/sizeof(ixSMU_LCLK_DPM_STATE_2_CNTL_2[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_2_CNTL_3", REG_SMC, 0x3fd34, &ixSMU_LCLK_DPM_STATE_2_CNTL_3[0], sizeof(ixSMU_LCLK_DPM_STATE_2_CNTL_3)/sizeof(ixSMU_LCLK_DPM_STATE_2_CNTL_3[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD", REG_SMC, 0x3fd38, &ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD[0], sizeof(ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD)/sizeof(ixSMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_3_CNTL_0", REG_SMC, 0x3fd3c, &ixSMU_LCLK_DPM_STATE_3_CNTL_0[0], sizeof(ixSMU_LCLK_DPM_STATE_3_CNTL_0)/sizeof(ixSMU_LCLK_DPM_STATE_3_CNTL_0[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_3_CNTL_1", REG_SMC, 0x3fd40, &ixSMU_LCLK_DPM_STATE_3_CNTL_1[0], sizeof(ixSMU_LCLK_DPM_STATE_3_CNTL_1)/sizeof(ixSMU_LCLK_DPM_STATE_3_CNTL_1[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_3_CNTL_2", REG_SMC, 0x3fd44, &ixSMU_LCLK_DPM_STATE_3_CNTL_2[0], sizeof(ixSMU_LCLK_DPM_STATE_3_CNTL_2)/sizeof(ixSMU_LCLK_DPM_STATE_3_CNTL_2[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_3_CNTL_3", REG_SMC, 0x3fd48, &ixSMU_LCLK_DPM_STATE_3_CNTL_3[0], sizeof(ixSMU_LCLK_DPM_STATE_3_CNTL_3)/sizeof(ixSMU_LCLK_DPM_STATE_3_CNTL_3[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD", REG_SMC, 0x3fd4c, &ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD[0], sizeof(ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD)/sizeof(ixSMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_4_CNTL_0", REG_SMC, 0x3fd50, &ixSMU_LCLK_DPM_STATE_4_CNTL_0[0], sizeof(ixSMU_LCLK_DPM_STATE_4_CNTL_0)/sizeof(ixSMU_LCLK_DPM_STATE_4_CNTL_0[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_4_CNTL_1", REG_SMC, 0x3fd54, &ixSMU_LCLK_DPM_STATE_4_CNTL_1[0], sizeof(ixSMU_LCLK_DPM_STATE_4_CNTL_1)/sizeof(ixSMU_LCLK_DPM_STATE_4_CNTL_1[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_4_CNTL_2", REG_SMC, 0x3fd58, &ixSMU_LCLK_DPM_STATE_4_CNTL_2[0], sizeof(ixSMU_LCLK_DPM_STATE_4_CNTL_2)/sizeof(ixSMU_LCLK_DPM_STATE_4_CNTL_2[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_4_CNTL_3", REG_SMC, 0x3fd5c, &ixSMU_LCLK_DPM_STATE_4_CNTL_3[0], sizeof(ixSMU_LCLK_DPM_STATE_4_CNTL_3)/sizeof(ixSMU_LCLK_DPM_STATE_4_CNTL_3[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD", REG_SMC, 0x3fd60, &ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD[0], sizeof(ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD)/sizeof(ixSMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_5_CNTL_0", REG_SMC, 0x3fd64, &ixSMU_LCLK_DPM_STATE_5_CNTL_0[0], sizeof(ixSMU_LCLK_DPM_STATE_5_CNTL_0)/sizeof(ixSMU_LCLK_DPM_STATE_5_CNTL_0[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_5_CNTL_1", REG_SMC, 0x3fd68, &ixSMU_LCLK_DPM_STATE_5_CNTL_1[0], sizeof(ixSMU_LCLK_DPM_STATE_5_CNTL_1)/sizeof(ixSMU_LCLK_DPM_STATE_5_CNTL_1[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_5_CNTL_2", REG_SMC, 0x3fd6c, &ixSMU_LCLK_DPM_STATE_5_CNTL_2[0], sizeof(ixSMU_LCLK_DPM_STATE_5_CNTL_2)/sizeof(ixSMU_LCLK_DPM_STATE_5_CNTL_2[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_5_CNTL_3", REG_SMC, 0x3fd70, &ixSMU_LCLK_DPM_STATE_5_CNTL_3[0], sizeof(ixSMU_LCLK_DPM_STATE_5_CNTL_3)/sizeof(ixSMU_LCLK_DPM_STATE_5_CNTL_3[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD", REG_SMC, 0x3fd74, &ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD[0], sizeof(ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD)/sizeof(ixSMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_6_CNTL_0", REG_SMC, 0x3fd78, &ixSMU_LCLK_DPM_STATE_6_CNTL_0[0], sizeof(ixSMU_LCLK_DPM_STATE_6_CNTL_0)/sizeof(ixSMU_LCLK_DPM_STATE_6_CNTL_0[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_6_CNTL_1", REG_SMC, 0x3fd7c, &ixSMU_LCLK_DPM_STATE_6_CNTL_1[0], sizeof(ixSMU_LCLK_DPM_STATE_6_CNTL_1)/sizeof(ixSMU_LCLK_DPM_STATE_6_CNTL_1[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_6_CNTL_2", REG_SMC, 0x3fd80, &ixSMU_LCLK_DPM_STATE_6_CNTL_2[0], sizeof(ixSMU_LCLK_DPM_STATE_6_CNTL_2)/sizeof(ixSMU_LCLK_DPM_STATE_6_CNTL_2[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_6_CNTL_3", REG_SMC, 0x3fd84, &ixSMU_LCLK_DPM_STATE_6_CNTL_3[0], sizeof(ixSMU_LCLK_DPM_STATE_6_CNTL_3)/sizeof(ixSMU_LCLK_DPM_STATE_6_CNTL_3[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD", REG_SMC, 0x3fd88, &ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD[0], sizeof(ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD)/sizeof(ixSMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_7_CNTL_0", REG_SMC, 0x3fd8c, &ixSMU_LCLK_DPM_STATE_7_CNTL_0[0], sizeof(ixSMU_LCLK_DPM_STATE_7_CNTL_0)/sizeof(ixSMU_LCLK_DPM_STATE_7_CNTL_0[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_7_CNTL_1", REG_SMC, 0x3fd90, &ixSMU_LCLK_DPM_STATE_7_CNTL_1[0], sizeof(ixSMU_LCLK_DPM_STATE_7_CNTL_1)/sizeof(ixSMU_LCLK_DPM_STATE_7_CNTL_1[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_7_CNTL_2", REG_SMC, 0x3fd94, &ixSMU_LCLK_DPM_STATE_7_CNTL_2[0], sizeof(ixSMU_LCLK_DPM_STATE_7_CNTL_2)/sizeof(ixSMU_LCLK_DPM_STATE_7_CNTL_2[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_7_CNTL_3", REG_SMC, 0x3fd98, &ixSMU_LCLK_DPM_STATE_7_CNTL_3[0], sizeof(ixSMU_LCLK_DPM_STATE_7_CNTL_3)/sizeof(ixSMU_LCLK_DPM_STATE_7_CNTL_3[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD", REG_SMC, 0x3fd9c, &ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD[0], sizeof(ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD)/sizeof(ixSMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_0", REG_SMC, 0x3fda0, &ixGIO_PID_CONTROLLER_CNTL_0[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_0)/sizeof(ixGIO_PID_CONTROLLER_CNTL_0[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_1", REG_SMC, 0x3fda4, &ixGIO_PID_CONTROLLER_CNTL_1[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_1)/sizeof(ixGIO_PID_CONTROLLER_CNTL_1[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_2", REG_SMC, 0x3fda8, &ixGIO_PID_CONTROLLER_CNTL_2[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_2)/sizeof(ixGIO_PID_CONTROLLER_CNTL_2[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_3", REG_SMC, 0x3fdac, &ixGIO_PID_CONTROLLER_CNTL_3[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_3)/sizeof(ixGIO_PID_CONTROLLER_CNTL_3[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_4", REG_SMC, 0x3fdb0, &ixGIO_PID_CONTROLLER_CNTL_4[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_4)/sizeof(ixGIO_PID_CONTROLLER_CNTL_4[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_5", REG_SMC, 0x3fdb4, &ixGIO_PID_CONTROLLER_CNTL_5[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_5)/sizeof(ixGIO_PID_CONTROLLER_CNTL_5[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_6", REG_SMC, 0x3fdb8, &ixGIO_PID_CONTROLLER_CNTL_6[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_6)/sizeof(ixGIO_PID_CONTROLLER_CNTL_6[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_7", REG_SMC, 0x3fdbc, &ixGIO_PID_CONTROLLER_CNTL_7[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_7)/sizeof(ixGIO_PID_CONTROLLER_CNTL_7[0]), 0, 0 },
+	{ "ixGIO_PID_CONTROLLER_CNTL_8", REG_SMC, 0x3fdc0, &ixGIO_PID_CONTROLLER_CNTL_8[0], sizeof(ixGIO_PID_CONTROLLER_CNTL_8)/sizeof(ixGIO_PID_CONTROLLER_CNTL_8[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_LEVEL_COUNT", REG_SMC, 0x3fdc4, &ixSMU_LCLK_DPM_LEVEL_COUNT[0], sizeof(ixSMU_LCLK_DPM_LEVEL_COUNT)/sizeof(ixSMU_LCLK_DPM_LEVEL_COUNT[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_CNTL", REG_SMC, 0x3fdc8, &ixSMU_LCLK_DPM_CNTL[0], sizeof(ixSMU_LCLK_DPM_CNTL)/sizeof(ixSMU_LCLK_DPM_CNTL[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE", REG_SMC, 0x3fdcc, &ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE[0], sizeof(ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE)/sizeof(ixSMU_LCLK_DPM_CURRENT_AND_TARGET_STATE[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL", REG_SMC, 0x3fdd0, &ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL[0], sizeof(ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL)/sizeof(ixSMU_LCLK_DPM_THERMAL_THROTTLING_CNTL[0]), 0, 0 },
+	{ "ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS", REG_SMC, 0x3fdd4, &ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS[0], sizeof(ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS)/sizeof(ixSMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_0", REG_SMC, 0x3fe00, &ixSMU_PM_STATUS_0[0], sizeof(ixSMU_PM_STATUS_0)/sizeof(ixSMU_PM_STATUS_0[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_1", REG_SMC, 0x3fe04, &ixSMU_PM_STATUS_1[0], sizeof(ixSMU_PM_STATUS_1)/sizeof(ixSMU_PM_STATUS_1[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_2", REG_SMC, 0x3fe08, &ixSMU_PM_STATUS_2[0], sizeof(ixSMU_PM_STATUS_2)/sizeof(ixSMU_PM_STATUS_2[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_3", REG_SMC, 0x3fe0c, &ixSMU_PM_STATUS_3[0], sizeof(ixSMU_PM_STATUS_3)/sizeof(ixSMU_PM_STATUS_3[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_4", REG_SMC, 0x3fe10, &ixSMU_PM_STATUS_4[0], sizeof(ixSMU_PM_STATUS_4)/sizeof(ixSMU_PM_STATUS_4[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_5", REG_SMC, 0x3fe14, &ixSMU_PM_STATUS_5[0], sizeof(ixSMU_PM_STATUS_5)/sizeof(ixSMU_PM_STATUS_5[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_6", REG_SMC, 0x3fe18, &ixSMU_PM_STATUS_6[0], sizeof(ixSMU_PM_STATUS_6)/sizeof(ixSMU_PM_STATUS_6[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_7", REG_SMC, 0x3fe1c, &ixSMU_PM_STATUS_7[0], sizeof(ixSMU_PM_STATUS_7)/sizeof(ixSMU_PM_STATUS_7[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_8", REG_SMC, 0x3fe20, &ixSMU_PM_STATUS_8[0], sizeof(ixSMU_PM_STATUS_8)/sizeof(ixSMU_PM_STATUS_8[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_9", REG_SMC, 0x3fe24, &ixSMU_PM_STATUS_9[0], sizeof(ixSMU_PM_STATUS_9)/sizeof(ixSMU_PM_STATUS_9[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_10", REG_SMC, 0x3fe28, &ixSMU_PM_STATUS_10[0], sizeof(ixSMU_PM_STATUS_10)/sizeof(ixSMU_PM_STATUS_10[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_11", REG_SMC, 0x3fe2c, &ixSMU_PM_STATUS_11[0], sizeof(ixSMU_PM_STATUS_11)/sizeof(ixSMU_PM_STATUS_11[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_12", REG_SMC, 0x3fe30, &ixSMU_PM_STATUS_12[0], sizeof(ixSMU_PM_STATUS_12)/sizeof(ixSMU_PM_STATUS_12[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_13", REG_SMC, 0x3fe34, &ixSMU_PM_STATUS_13[0], sizeof(ixSMU_PM_STATUS_13)/sizeof(ixSMU_PM_STATUS_13[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_14", REG_SMC, 0x3fe38, &ixSMU_PM_STATUS_14[0], sizeof(ixSMU_PM_STATUS_14)/sizeof(ixSMU_PM_STATUS_14[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_15", REG_SMC, 0x3fe3c, &ixSMU_PM_STATUS_15[0], sizeof(ixSMU_PM_STATUS_15)/sizeof(ixSMU_PM_STATUS_15[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_16", REG_SMC, 0x3fe40, &ixSMU_PM_STATUS_16[0], sizeof(ixSMU_PM_STATUS_16)/sizeof(ixSMU_PM_STATUS_16[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_17", REG_SMC, 0x3fe44, &ixSMU_PM_STATUS_17[0], sizeof(ixSMU_PM_STATUS_17)/sizeof(ixSMU_PM_STATUS_17[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_18", REG_SMC, 0x3fe48, &ixSMU_PM_STATUS_18[0], sizeof(ixSMU_PM_STATUS_18)/sizeof(ixSMU_PM_STATUS_18[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_19", REG_SMC, 0x3fe4c, &ixSMU_PM_STATUS_19[0], sizeof(ixSMU_PM_STATUS_19)/sizeof(ixSMU_PM_STATUS_19[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_20", REG_SMC, 0x3fe50, &ixSMU_PM_STATUS_20[0], sizeof(ixSMU_PM_STATUS_20)/sizeof(ixSMU_PM_STATUS_20[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_21", REG_SMC, 0x3fe54, &ixSMU_PM_STATUS_21[0], sizeof(ixSMU_PM_STATUS_21)/sizeof(ixSMU_PM_STATUS_21[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_22", REG_SMC, 0x3fe58, &ixSMU_PM_STATUS_22[0], sizeof(ixSMU_PM_STATUS_22)/sizeof(ixSMU_PM_STATUS_22[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_23", REG_SMC, 0x3fe5c, &ixSMU_PM_STATUS_23[0], sizeof(ixSMU_PM_STATUS_23)/sizeof(ixSMU_PM_STATUS_23[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_24", REG_SMC, 0x3fe60, &ixSMU_PM_STATUS_24[0], sizeof(ixSMU_PM_STATUS_24)/sizeof(ixSMU_PM_STATUS_24[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_25", REG_SMC, 0x3fe64, &ixSMU_PM_STATUS_25[0], sizeof(ixSMU_PM_STATUS_25)/sizeof(ixSMU_PM_STATUS_25[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_26", REG_SMC, 0x3fe68, &ixSMU_PM_STATUS_26[0], sizeof(ixSMU_PM_STATUS_26)/sizeof(ixSMU_PM_STATUS_26[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_27", REG_SMC, 0x3fe6c, &ixSMU_PM_STATUS_27[0], sizeof(ixSMU_PM_STATUS_27)/sizeof(ixSMU_PM_STATUS_27[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_28", REG_SMC, 0x3fe70, &ixSMU_PM_STATUS_28[0], sizeof(ixSMU_PM_STATUS_28)/sizeof(ixSMU_PM_STATUS_28[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_29", REG_SMC, 0x3fe74, &ixSMU_PM_STATUS_29[0], sizeof(ixSMU_PM_STATUS_29)/sizeof(ixSMU_PM_STATUS_29[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_30", REG_SMC, 0x3fe78, &ixSMU_PM_STATUS_30[0], sizeof(ixSMU_PM_STATUS_30)/sizeof(ixSMU_PM_STATUS_30[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_31", REG_SMC, 0x3fe7c, &ixSMU_PM_STATUS_31[0], sizeof(ixSMU_PM_STATUS_31)/sizeof(ixSMU_PM_STATUS_31[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_32", REG_SMC, 0x3fe80, &ixSMU_PM_STATUS_32[0], sizeof(ixSMU_PM_STATUS_32)/sizeof(ixSMU_PM_STATUS_32[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_33", REG_SMC, 0x3fe84, &ixSMU_PM_STATUS_33[0], sizeof(ixSMU_PM_STATUS_33)/sizeof(ixSMU_PM_STATUS_33[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_34", REG_SMC, 0x3fe88, &ixSMU_PM_STATUS_34[0], sizeof(ixSMU_PM_STATUS_34)/sizeof(ixSMU_PM_STATUS_34[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_35", REG_SMC, 0x3fe8c, &ixSMU_PM_STATUS_35[0], sizeof(ixSMU_PM_STATUS_35)/sizeof(ixSMU_PM_STATUS_35[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_36", REG_SMC, 0x3fe90, &ixSMU_PM_STATUS_36[0], sizeof(ixSMU_PM_STATUS_36)/sizeof(ixSMU_PM_STATUS_36[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_37", REG_SMC, 0x3fe94, &ixSMU_PM_STATUS_37[0], sizeof(ixSMU_PM_STATUS_37)/sizeof(ixSMU_PM_STATUS_37[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_38", REG_SMC, 0x3fe98, &ixSMU_PM_STATUS_38[0], sizeof(ixSMU_PM_STATUS_38)/sizeof(ixSMU_PM_STATUS_38[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_39", REG_SMC, 0x3fe9c, &ixSMU_PM_STATUS_39[0], sizeof(ixSMU_PM_STATUS_39)/sizeof(ixSMU_PM_STATUS_39[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_40", REG_SMC, 0x3fea0, &ixSMU_PM_STATUS_40[0], sizeof(ixSMU_PM_STATUS_40)/sizeof(ixSMU_PM_STATUS_40[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_41", REG_SMC, 0x3fea4, &ixSMU_PM_STATUS_41[0], sizeof(ixSMU_PM_STATUS_41)/sizeof(ixSMU_PM_STATUS_41[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_42", REG_SMC, 0x3fea8, &ixSMU_PM_STATUS_42[0], sizeof(ixSMU_PM_STATUS_42)/sizeof(ixSMU_PM_STATUS_42[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_43", REG_SMC, 0x3feac, &ixSMU_PM_STATUS_43[0], sizeof(ixSMU_PM_STATUS_43)/sizeof(ixSMU_PM_STATUS_43[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_44", REG_SMC, 0x3feb0, &ixSMU_PM_STATUS_44[0], sizeof(ixSMU_PM_STATUS_44)/sizeof(ixSMU_PM_STATUS_44[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_45", REG_SMC, 0x3feb4, &ixSMU_PM_STATUS_45[0], sizeof(ixSMU_PM_STATUS_45)/sizeof(ixSMU_PM_STATUS_45[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_46", REG_SMC, 0x3feb8, &ixSMU_PM_STATUS_46[0], sizeof(ixSMU_PM_STATUS_46)/sizeof(ixSMU_PM_STATUS_46[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_47", REG_SMC, 0x3febc, &ixSMU_PM_STATUS_47[0], sizeof(ixSMU_PM_STATUS_47)/sizeof(ixSMU_PM_STATUS_47[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_48", REG_SMC, 0x3fec0, &ixSMU_PM_STATUS_48[0], sizeof(ixSMU_PM_STATUS_48)/sizeof(ixSMU_PM_STATUS_48[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_49", REG_SMC, 0x3fec4, &ixSMU_PM_STATUS_49[0], sizeof(ixSMU_PM_STATUS_49)/sizeof(ixSMU_PM_STATUS_49[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_50", REG_SMC, 0x3fec8, &ixSMU_PM_STATUS_50[0], sizeof(ixSMU_PM_STATUS_50)/sizeof(ixSMU_PM_STATUS_50[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_51", REG_SMC, 0x3fecc, &ixSMU_PM_STATUS_51[0], sizeof(ixSMU_PM_STATUS_51)/sizeof(ixSMU_PM_STATUS_51[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_52", REG_SMC, 0x3fed0, &ixSMU_PM_STATUS_52[0], sizeof(ixSMU_PM_STATUS_52)/sizeof(ixSMU_PM_STATUS_52[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_53", REG_SMC, 0x3fed4, &ixSMU_PM_STATUS_53[0], sizeof(ixSMU_PM_STATUS_53)/sizeof(ixSMU_PM_STATUS_53[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_54", REG_SMC, 0x3fed8, &ixSMU_PM_STATUS_54[0], sizeof(ixSMU_PM_STATUS_54)/sizeof(ixSMU_PM_STATUS_54[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_55", REG_SMC, 0x3fedc, &ixSMU_PM_STATUS_55[0], sizeof(ixSMU_PM_STATUS_55)/sizeof(ixSMU_PM_STATUS_55[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_56", REG_SMC, 0x3fee0, &ixSMU_PM_STATUS_56[0], sizeof(ixSMU_PM_STATUS_56)/sizeof(ixSMU_PM_STATUS_56[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_57", REG_SMC, 0x3fee4, &ixSMU_PM_STATUS_57[0], sizeof(ixSMU_PM_STATUS_57)/sizeof(ixSMU_PM_STATUS_57[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_58", REG_SMC, 0x3fee8, &ixSMU_PM_STATUS_58[0], sizeof(ixSMU_PM_STATUS_58)/sizeof(ixSMU_PM_STATUS_58[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_59", REG_SMC, 0x3feec, &ixSMU_PM_STATUS_59[0], sizeof(ixSMU_PM_STATUS_59)/sizeof(ixSMU_PM_STATUS_59[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_60", REG_SMC, 0x3fef0, &ixSMU_PM_STATUS_60[0], sizeof(ixSMU_PM_STATUS_60)/sizeof(ixSMU_PM_STATUS_60[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_61", REG_SMC, 0x3fef4, &ixSMU_PM_STATUS_61[0], sizeof(ixSMU_PM_STATUS_61)/sizeof(ixSMU_PM_STATUS_61[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_62", REG_SMC, 0x3fef8, &ixSMU_PM_STATUS_62[0], sizeof(ixSMU_PM_STATUS_62)/sizeof(ixSMU_PM_STATUS_62[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_63", REG_SMC, 0x3fefc, &ixSMU_PM_STATUS_63[0], sizeof(ixSMU_PM_STATUS_63)/sizeof(ixSMU_PM_STATUS_63[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_64", REG_SMC, 0x3ff00, &ixSMU_PM_STATUS_64[0], sizeof(ixSMU_PM_STATUS_64)/sizeof(ixSMU_PM_STATUS_64[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_65", REG_SMC, 0x3ff04, &ixSMU_PM_STATUS_65[0], sizeof(ixSMU_PM_STATUS_65)/sizeof(ixSMU_PM_STATUS_65[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_66", REG_SMC, 0x3ff08, &ixSMU_PM_STATUS_66[0], sizeof(ixSMU_PM_STATUS_66)/sizeof(ixSMU_PM_STATUS_66[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_67", REG_SMC, 0x3ff0c, &ixSMU_PM_STATUS_67[0], sizeof(ixSMU_PM_STATUS_67)/sizeof(ixSMU_PM_STATUS_67[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_68", REG_SMC, 0x3ff10, &ixSMU_PM_STATUS_68[0], sizeof(ixSMU_PM_STATUS_68)/sizeof(ixSMU_PM_STATUS_68[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_69", REG_SMC, 0x3ff14, &ixSMU_PM_STATUS_69[0], sizeof(ixSMU_PM_STATUS_69)/sizeof(ixSMU_PM_STATUS_69[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_70", REG_SMC, 0x3ff18, &ixSMU_PM_STATUS_70[0], sizeof(ixSMU_PM_STATUS_70)/sizeof(ixSMU_PM_STATUS_70[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_71", REG_SMC, 0x3ff1c, &ixSMU_PM_STATUS_71[0], sizeof(ixSMU_PM_STATUS_71)/sizeof(ixSMU_PM_STATUS_71[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_72", REG_SMC, 0x3ff20, &ixSMU_PM_STATUS_72[0], sizeof(ixSMU_PM_STATUS_72)/sizeof(ixSMU_PM_STATUS_72[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_73", REG_SMC, 0x3ff24, &ixSMU_PM_STATUS_73[0], sizeof(ixSMU_PM_STATUS_73)/sizeof(ixSMU_PM_STATUS_73[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_74", REG_SMC, 0x3ff28, &ixSMU_PM_STATUS_74[0], sizeof(ixSMU_PM_STATUS_74)/sizeof(ixSMU_PM_STATUS_74[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_75", REG_SMC, 0x3ff2c, &ixSMU_PM_STATUS_75[0], sizeof(ixSMU_PM_STATUS_75)/sizeof(ixSMU_PM_STATUS_75[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_76", REG_SMC, 0x3ff30, &ixSMU_PM_STATUS_76[0], sizeof(ixSMU_PM_STATUS_76)/sizeof(ixSMU_PM_STATUS_76[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_77", REG_SMC, 0x3ff34, &ixSMU_PM_STATUS_77[0], sizeof(ixSMU_PM_STATUS_77)/sizeof(ixSMU_PM_STATUS_77[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_78", REG_SMC, 0x3ff38, &ixSMU_PM_STATUS_78[0], sizeof(ixSMU_PM_STATUS_78)/sizeof(ixSMU_PM_STATUS_78[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_79", REG_SMC, 0x3ff3c, &ixSMU_PM_STATUS_79[0], sizeof(ixSMU_PM_STATUS_79)/sizeof(ixSMU_PM_STATUS_79[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_80", REG_SMC, 0x3ff40, &ixSMU_PM_STATUS_80[0], sizeof(ixSMU_PM_STATUS_80)/sizeof(ixSMU_PM_STATUS_80[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_81", REG_SMC, 0x3ff44, &ixSMU_PM_STATUS_81[0], sizeof(ixSMU_PM_STATUS_81)/sizeof(ixSMU_PM_STATUS_81[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_82", REG_SMC, 0x3ff48, &ixSMU_PM_STATUS_82[0], sizeof(ixSMU_PM_STATUS_82)/sizeof(ixSMU_PM_STATUS_82[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_83", REG_SMC, 0x3ff4c, &ixSMU_PM_STATUS_83[0], sizeof(ixSMU_PM_STATUS_83)/sizeof(ixSMU_PM_STATUS_83[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_84", REG_SMC, 0x3ff50, &ixSMU_PM_STATUS_84[0], sizeof(ixSMU_PM_STATUS_84)/sizeof(ixSMU_PM_STATUS_84[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_85", REG_SMC, 0x3ff54, &ixSMU_PM_STATUS_85[0], sizeof(ixSMU_PM_STATUS_85)/sizeof(ixSMU_PM_STATUS_85[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_86", REG_SMC, 0x3ff58, &ixSMU_PM_STATUS_86[0], sizeof(ixSMU_PM_STATUS_86)/sizeof(ixSMU_PM_STATUS_86[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_87", REG_SMC, 0x3ff5c, &ixSMU_PM_STATUS_87[0], sizeof(ixSMU_PM_STATUS_87)/sizeof(ixSMU_PM_STATUS_87[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_88", REG_SMC, 0x3ff60, &ixSMU_PM_STATUS_88[0], sizeof(ixSMU_PM_STATUS_88)/sizeof(ixSMU_PM_STATUS_88[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_89", REG_SMC, 0x3ff64, &ixSMU_PM_STATUS_89[0], sizeof(ixSMU_PM_STATUS_89)/sizeof(ixSMU_PM_STATUS_89[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_90", REG_SMC, 0x3ff68, &ixSMU_PM_STATUS_90[0], sizeof(ixSMU_PM_STATUS_90)/sizeof(ixSMU_PM_STATUS_90[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_91", REG_SMC, 0x3ff6c, &ixSMU_PM_STATUS_91[0], sizeof(ixSMU_PM_STATUS_91)/sizeof(ixSMU_PM_STATUS_91[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_92", REG_SMC, 0x3ff70, &ixSMU_PM_STATUS_92[0], sizeof(ixSMU_PM_STATUS_92)/sizeof(ixSMU_PM_STATUS_92[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_93", REG_SMC, 0x3ff74, &ixSMU_PM_STATUS_93[0], sizeof(ixSMU_PM_STATUS_93)/sizeof(ixSMU_PM_STATUS_93[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_94", REG_SMC, 0x3ff78, &ixSMU_PM_STATUS_94[0], sizeof(ixSMU_PM_STATUS_94)/sizeof(ixSMU_PM_STATUS_94[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_95", REG_SMC, 0x3ff7c, &ixSMU_PM_STATUS_95[0], sizeof(ixSMU_PM_STATUS_95)/sizeof(ixSMU_PM_STATUS_95[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_96", REG_SMC, 0x3ff80, &ixSMU_PM_STATUS_96[0], sizeof(ixSMU_PM_STATUS_96)/sizeof(ixSMU_PM_STATUS_96[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_97", REG_SMC, 0x3ff84, &ixSMU_PM_STATUS_97[0], sizeof(ixSMU_PM_STATUS_97)/sizeof(ixSMU_PM_STATUS_97[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_98", REG_SMC, 0x3ff88, &ixSMU_PM_STATUS_98[0], sizeof(ixSMU_PM_STATUS_98)/sizeof(ixSMU_PM_STATUS_98[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_99", REG_SMC, 0x3ff8c, &ixSMU_PM_STATUS_99[0], sizeof(ixSMU_PM_STATUS_99)/sizeof(ixSMU_PM_STATUS_99[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_100", REG_SMC, 0x3ff90, &ixSMU_PM_STATUS_100[0], sizeof(ixSMU_PM_STATUS_100)/sizeof(ixSMU_PM_STATUS_100[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_101", REG_SMC, 0x3ff94, &ixSMU_PM_STATUS_101[0], sizeof(ixSMU_PM_STATUS_101)/sizeof(ixSMU_PM_STATUS_101[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_102", REG_SMC, 0x3ff98, &ixSMU_PM_STATUS_102[0], sizeof(ixSMU_PM_STATUS_102)/sizeof(ixSMU_PM_STATUS_102[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_103", REG_SMC, 0x3ff9c, &ixSMU_PM_STATUS_103[0], sizeof(ixSMU_PM_STATUS_103)/sizeof(ixSMU_PM_STATUS_103[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_104", REG_SMC, 0x3ffa0, &ixSMU_PM_STATUS_104[0], sizeof(ixSMU_PM_STATUS_104)/sizeof(ixSMU_PM_STATUS_104[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_105", REG_SMC, 0x3ffa4, &ixSMU_PM_STATUS_105[0], sizeof(ixSMU_PM_STATUS_105)/sizeof(ixSMU_PM_STATUS_105[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_106", REG_SMC, 0x3ffa8, &ixSMU_PM_STATUS_106[0], sizeof(ixSMU_PM_STATUS_106)/sizeof(ixSMU_PM_STATUS_106[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_107", REG_SMC, 0x3ffac, &ixSMU_PM_STATUS_107[0], sizeof(ixSMU_PM_STATUS_107)/sizeof(ixSMU_PM_STATUS_107[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_108", REG_SMC, 0x3ffb0, &ixSMU_PM_STATUS_108[0], sizeof(ixSMU_PM_STATUS_108)/sizeof(ixSMU_PM_STATUS_108[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_109", REG_SMC, 0x3ffb4, &ixSMU_PM_STATUS_109[0], sizeof(ixSMU_PM_STATUS_109)/sizeof(ixSMU_PM_STATUS_109[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_110", REG_SMC, 0x3ffb8, &ixSMU_PM_STATUS_110[0], sizeof(ixSMU_PM_STATUS_110)/sizeof(ixSMU_PM_STATUS_110[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_111", REG_SMC, 0x3ffbc, &ixSMU_PM_STATUS_111[0], sizeof(ixSMU_PM_STATUS_111)/sizeof(ixSMU_PM_STATUS_111[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_112", REG_SMC, 0x3ffc0, &ixSMU_PM_STATUS_112[0], sizeof(ixSMU_PM_STATUS_112)/sizeof(ixSMU_PM_STATUS_112[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_113", REG_SMC, 0x3ffc4, &ixSMU_PM_STATUS_113[0], sizeof(ixSMU_PM_STATUS_113)/sizeof(ixSMU_PM_STATUS_113[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_114", REG_SMC, 0x3ffc8, &ixSMU_PM_STATUS_114[0], sizeof(ixSMU_PM_STATUS_114)/sizeof(ixSMU_PM_STATUS_114[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_115", REG_SMC, 0x3ffcc, &ixSMU_PM_STATUS_115[0], sizeof(ixSMU_PM_STATUS_115)/sizeof(ixSMU_PM_STATUS_115[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_116", REG_SMC, 0x3ffd0, &ixSMU_PM_STATUS_116[0], sizeof(ixSMU_PM_STATUS_116)/sizeof(ixSMU_PM_STATUS_116[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_117", REG_SMC, 0x3ffd4, &ixSMU_PM_STATUS_117[0], sizeof(ixSMU_PM_STATUS_117)/sizeof(ixSMU_PM_STATUS_117[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_118", REG_SMC, 0x3ffd8, &ixSMU_PM_STATUS_118[0], sizeof(ixSMU_PM_STATUS_118)/sizeof(ixSMU_PM_STATUS_118[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_119", REG_SMC, 0x3ffdc, &ixSMU_PM_STATUS_119[0], sizeof(ixSMU_PM_STATUS_119)/sizeof(ixSMU_PM_STATUS_119[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_120", REG_SMC, 0x3ffe0, &ixSMU_PM_STATUS_120[0], sizeof(ixSMU_PM_STATUS_120)/sizeof(ixSMU_PM_STATUS_120[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_121", REG_SMC, 0x3ffe4, &ixSMU_PM_STATUS_121[0], sizeof(ixSMU_PM_STATUS_121)/sizeof(ixSMU_PM_STATUS_121[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_122", REG_SMC, 0x3ffe8, &ixSMU_PM_STATUS_122[0], sizeof(ixSMU_PM_STATUS_122)/sizeof(ixSMU_PM_STATUS_122[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_123", REG_SMC, 0x3ffec, &ixSMU_PM_STATUS_123[0], sizeof(ixSMU_PM_STATUS_123)/sizeof(ixSMU_PM_STATUS_123[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_124", REG_SMC, 0x3fff0, &ixSMU_PM_STATUS_124[0], sizeof(ixSMU_PM_STATUS_124)/sizeof(ixSMU_PM_STATUS_124[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_125", REG_SMC, 0x3fff4, &ixSMU_PM_STATUS_125[0], sizeof(ixSMU_PM_STATUS_125)/sizeof(ixSMU_PM_STATUS_125[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_126", REG_SMC, 0x3fff8, &ixSMU_PM_STATUS_126[0], sizeof(ixSMU_PM_STATUS_126)/sizeof(ixSMU_PM_STATUS_126[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_127", REG_SMC, 0x3fffc, &ixSMU_PM_STATUS_127[0], sizeof(ixSMU_PM_STATUS_127)/sizeof(ixSMU_PM_STATUS_127[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_INDEX", REG_MMIO, 0x80, &mmGCK_SMC_IND_INDEX[0], sizeof(mmGCK_SMC_IND_INDEX)/sizeof(mmGCK_SMC_IND_INDEX[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_0", REG_MMIO, 0x80, &mmSMC_IND_INDEX_0[0], sizeof(mmSMC_IND_INDEX_0)/sizeof(mmSMC_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX", REG_MMIO, 0x80, &mmSMC_IND_INDEX[0], sizeof(mmSMC_IND_INDEX)/sizeof(mmSMC_IND_INDEX[0]), 0, 0 },
+	{ "ixSMC_SYSCON_RESET_CNTL", REG_SMC, 0x80000000, &ixSMC_SYSCON_RESET_CNTL[0], sizeof(ixSMC_SYSCON_RESET_CNTL)/sizeof(ixSMC_SYSCON_RESET_CNTL[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_0", REG_SMC, 0x80000004, &ixSMC_SYSCON_CLOCK_CNTL_0[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_0)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_0[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_1", REG_SMC, 0x80000008, &ixSMC_SYSCON_CLOCK_CNTL_1[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_1)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_1[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_2", REG_SMC, 0x8000000c, &ixSMC_SYSCON_CLOCK_CNTL_2[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_2)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_2[0]), 0, 0 },
+	{ "ixSMC_SYSCON_MISC_CNTL", REG_SMC, 0x80000010, NULL, 0, 0, 0 },
+	{ "ixSMC_SYSCON_MSG_ARG_0", REG_SMC, 0x80000068, &ixSMC_SYSCON_MSG_ARG_0[0], sizeof(ixSMC_SYSCON_MSG_ARG_0)/sizeof(ixSMC_SYSCON_MSG_ARG_0[0]), 0, 0 },
+	{ "ixSMC_PC_C", REG_SMC, 0x80000370, &ixSMC_PC_C[0], sizeof(ixSMC_PC_C)/sizeof(ixSMC_PC_C[0]), 0, 0 },
+	{ "ixSMC_SCRATCH9", REG_SMC, 0x80000424, &ixSMC_SCRATCH9[0], sizeof(ixSMC_SCRATCH9)/sizeof(ixSMC_SCRATCH9[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_DATA", REG_MMIO, 0x81, &mmGCK_SMC_IND_DATA[0], sizeof(mmGCK_SMC_IND_DATA)/sizeof(mmGCK_SMC_IND_DATA[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_0", REG_MMIO, 0x81, &mmSMC_IND_DATA_0[0], sizeof(mmSMC_IND_DATA_0)/sizeof(mmSMC_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMC_IND_DATA", REG_MMIO, 0x81, &mmSMC_IND_DATA[0], sizeof(mmSMC_IND_DATA)/sizeof(mmSMC_IND_DATA[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_1", REG_MMIO, 0x82, &mmSMC_IND_INDEX_1[0], sizeof(mmSMC_IND_INDEX_1)/sizeof(mmSMC_IND_INDEX_1[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_1", REG_MMIO, 0x83, &mmSMC_IND_DATA_1[0], sizeof(mmSMC_IND_DATA_1)/sizeof(mmSMC_IND_DATA_1[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_2", REG_MMIO, 0x84, &mmSMC_IND_INDEX_2[0], sizeof(mmSMC_IND_INDEX_2)/sizeof(mmSMC_IND_INDEX_2[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_2", REG_MMIO, 0x85, &mmSMC_IND_DATA_2[0], sizeof(mmSMC_IND_DATA_2)/sizeof(mmSMC_IND_DATA_2[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_3", REG_MMIO, 0x86, &mmSMC_IND_INDEX_3[0], sizeof(mmSMC_IND_INDEX_3)/sizeof(mmSMC_IND_INDEX_3[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_3", REG_MMIO, 0x87, &mmSMC_IND_DATA_3[0], sizeof(mmSMC_IND_DATA_3)/sizeof(mmSMC_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_4", REG_MMIO, 0x88, &mmSMC_IND_INDEX_4[0], sizeof(mmSMC_IND_INDEX_4)/sizeof(mmSMC_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_4", REG_MMIO, 0x89, &mmSMC_IND_DATA_4[0], sizeof(mmSMC_IND_DATA_4)/sizeof(mmSMC_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_5", REG_MMIO, 0x8a, &mmSMC_IND_INDEX_5[0], sizeof(mmSMC_IND_INDEX_5)/sizeof(mmSMC_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_5", REG_MMIO, 0x8b, &mmSMC_IND_DATA_5[0], sizeof(mmSMC_IND_DATA_5)/sizeof(mmSMC_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_6", REG_MMIO, 0x8c, &mmSMC_IND_INDEX_6[0], sizeof(mmSMC_IND_INDEX_6)/sizeof(mmSMC_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_6", REG_MMIO, 0x8d, &mmSMC_IND_DATA_6[0], sizeof(mmSMC_IND_DATA_6)/sizeof(mmSMC_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_7", REG_MMIO, 0x8e, &mmSMC_IND_INDEX_7[0], sizeof(mmSMC_IND_INDEX_7)/sizeof(mmSMC_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_7", REG_MMIO, 0x8f, &mmSMC_IND_DATA_7[0], sizeof(mmSMC_IND_DATA_7)/sizeof(mmSMC_IND_DATA_7[0]), 0, 0 },
+	{ "mmSMC_IND_ACCESS_CNTL", REG_MMIO, 0x90, &mmSMC_IND_ACCESS_CNTL[0], sizeof(mmSMC_IND_ACCESS_CNTL)/sizeof(mmSMC_IND_ACCESS_CNTL[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_11", REG_MMIO, 0x91, &mmSMC_MSG_ARG_11[0], sizeof(mmSMC_MSG_ARG_11)/sizeof(mmSMC_MSG_ARG_11[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_0", REG_MMIO, 0x94, &mmSMC_MESSAGE_0[0], sizeof(mmSMC_MESSAGE_0)/sizeof(mmSMC_MESSAGE_0[0]), 0, 0 },
+	{ "mmSMC_RESP_0", REG_MMIO, 0x95, &mmSMC_RESP_0[0], sizeof(mmSMC_RESP_0)/sizeof(mmSMC_RESP_0[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_1", REG_MMIO, 0x96, &mmSMC_MESSAGE_1[0], sizeof(mmSMC_MESSAGE_1)/sizeof(mmSMC_MESSAGE_1[0]), 0, 0 },
+	{ "mmSMC_RESP_1", REG_MMIO, 0x97, &mmSMC_RESP_1[0], sizeof(mmSMC_RESP_1)/sizeof(mmSMC_RESP_1[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_2", REG_MMIO, 0x98, &mmSMC_MESSAGE_2[0], sizeof(mmSMC_MESSAGE_2)/sizeof(mmSMC_MESSAGE_2[0]), 0, 0 },
+	{ "mmSMC_RESP_2", REG_MMIO, 0x99, &mmSMC_RESP_2[0], sizeof(mmSMC_RESP_2)/sizeof(mmSMC_RESP_2[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_3", REG_MMIO, 0x9a, &mmSMC_MESSAGE_3[0], sizeof(mmSMC_MESSAGE_3)/sizeof(mmSMC_MESSAGE_3[0]), 0, 0 },
+	{ "mmSMC_RESP_3", REG_MMIO, 0x9b, &mmSMC_RESP_3[0], sizeof(mmSMC_RESP_3)/sizeof(mmSMC_RESP_3[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_4", REG_MMIO, 0x9c, &mmSMC_MESSAGE_4[0], sizeof(mmSMC_MESSAGE_4)/sizeof(mmSMC_MESSAGE_4[0]), 0, 0 },
+	{ "mmSMC_RESP_4", REG_MMIO, 0x9d, &mmSMC_RESP_4[0], sizeof(mmSMC_RESP_4)/sizeof(mmSMC_RESP_4[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_5", REG_MMIO, 0x9e, &mmSMC_MESSAGE_5[0], sizeof(mmSMC_MESSAGE_5)/sizeof(mmSMC_MESSAGE_5[0]), 0, 0 },
+	{ "mmSMC_RESP_5", REG_MMIO, 0x9f, &mmSMC_RESP_5[0], sizeof(mmSMC_RESP_5)/sizeof(mmSMC_RESP_5[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_6", REG_MMIO, 0xa0, &mmSMC_MESSAGE_6[0], sizeof(mmSMC_MESSAGE_6)/sizeof(mmSMC_MESSAGE_6[0]), 0, 0 },
+	{ "mmSMC_RESP_6", REG_MMIO, 0xa1, &mmSMC_RESP_6[0], sizeof(mmSMC_RESP_6)/sizeof(mmSMC_RESP_6[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_7", REG_MMIO, 0xa2, &mmSMC_MESSAGE_7[0], sizeof(mmSMC_MESSAGE_7)/sizeof(mmSMC_MESSAGE_7[0]), 0, 0 },
+	{ "mmSMC_RESP_7", REG_MMIO, 0xa3, &mmSMC_RESP_7[0], sizeof(mmSMC_RESP_7)/sizeof(mmSMC_RESP_7[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_0", REG_MMIO, 0xa4, &mmSMC_MSG_ARG_0[0], sizeof(mmSMC_MSG_ARG_0)/sizeof(mmSMC_MSG_ARG_0[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_1", REG_MMIO, 0xa5, &mmSMC_MSG_ARG_1[0], sizeof(mmSMC_MSG_ARG_1)/sizeof(mmSMC_MSG_ARG_1[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_2", REG_MMIO, 0xa6, &mmSMC_MSG_ARG_2[0], sizeof(mmSMC_MSG_ARG_2)/sizeof(mmSMC_MSG_ARG_2[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_3", REG_MMIO, 0xa7, &mmSMC_MSG_ARG_3[0], sizeof(mmSMC_MSG_ARG_3)/sizeof(mmSMC_MSG_ARG_3[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_4", REG_MMIO, 0xa8, &mmSMC_MSG_ARG_4[0], sizeof(mmSMC_MSG_ARG_4)/sizeof(mmSMC_MSG_ARG_4[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_5", REG_MMIO, 0xa9, &mmSMC_MSG_ARG_5[0], sizeof(mmSMC_MSG_ARG_5)/sizeof(mmSMC_MSG_ARG_5[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_6", REG_MMIO, 0xaa, &mmSMC_MSG_ARG_6[0], sizeof(mmSMC_MSG_ARG_6)/sizeof(mmSMC_MSG_ARG_6[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_7", REG_MMIO, 0xab, &mmSMC_MSG_ARG_7[0], sizeof(mmSMC_MSG_ARG_7)/sizeof(mmSMC_MSG_ARG_7[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_8", REG_MMIO, 0xb5, &mmSMC_MESSAGE_8[0], sizeof(mmSMC_MESSAGE_8)/sizeof(mmSMC_MESSAGE_8[0]), 0, 0 },
+	{ "mmSMC_RESP_8", REG_MMIO, 0xb6, &mmSMC_RESP_8[0], sizeof(mmSMC_RESP_8)/sizeof(mmSMC_RESP_8[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_9", REG_MMIO, 0xb7, &mmSMC_MESSAGE_9[0], sizeof(mmSMC_MESSAGE_9)/sizeof(mmSMC_MESSAGE_9[0]), 0, 0 },
+	{ "mmSMC_RESP_9", REG_MMIO, 0xb8, &mmSMC_RESP_9[0], sizeof(mmSMC_RESP_9)/sizeof(mmSMC_RESP_9[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_10", REG_MMIO, 0xb9, &mmSMC_MESSAGE_10[0], sizeof(mmSMC_MESSAGE_10)/sizeof(mmSMC_MESSAGE_10[0]), 0, 0 },
+	{ "mmSMC_RESP_10", REG_MMIO, 0xba, &mmSMC_RESP_10[0], sizeof(mmSMC_RESP_10)/sizeof(mmSMC_RESP_10[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_11", REG_MMIO, 0xbb, &mmSMC_MESSAGE_11[0], sizeof(mmSMC_MESSAGE_11)/sizeof(mmSMC_MESSAGE_11[0]), 0, 0 },
+	{ "mmSMC_RESP_11", REG_MMIO, 0xbc, &mmSMC_RESP_11[0], sizeof(mmSMC_RESP_11)/sizeof(mmSMC_RESP_11[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_8", REG_MMIO, 0xbd, &mmSMC_MSG_ARG_8[0], sizeof(mmSMC_MSG_ARG_8)/sizeof(mmSMC_MSG_ARG_8[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_9", REG_MMIO, 0xbe, &mmSMC_MSG_ARG_9[0], sizeof(mmSMC_MSG_ARG_9)/sizeof(mmSMC_MSG_ARG_9[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_10", REG_MMIO, 0xbf, &mmSMC_MSG_ARG_10[0], sizeof(mmSMC_MSG_ARG_10)/sizeof(mmSMC_MSG_ARG_10[0]), 0, 0 },
+	{ "ixRCU_UC_EVENTS", REG_SMC, 0xc0000004, &ixRCU_UC_EVENTS[0], sizeof(ixRCU_UC_EVENTS)/sizeof(ixRCU_UC_EVENTS[0]), 0, 0 },
+	{ "ixRCU_MISC_CTRL", REG_SMC, 0xc0000010, &ixRCU_MISC_CTRL[0], sizeof(ixRCU_MISC_CTRL)/sizeof(ixRCU_MISC_CTRL[0]), 0, 0 },
+	{ "ixCC_RCU_FUSES", REG_SMC, 0xc00c0000, &ixCC_RCU_FUSES[0], sizeof(ixCC_RCU_FUSES)/sizeof(ixCC_RCU_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_MISC_FUSES", REG_SMC, 0xc00c0004, &ixCC_SMU_MISC_FUSES[0], sizeof(ixCC_SMU_MISC_FUSES)/sizeof(ixCC_SMU_MISC_FUSES[0]), 0, 0 },
+	{ "ixCC_SCLK_VID_FUSES", REG_SMC, 0xc00c0008, &ixCC_SCLK_VID_FUSES[0], sizeof(ixCC_SCLK_VID_FUSES)/sizeof(ixCC_SCLK_VID_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOCCFG_FUSES", REG_SMC, 0xc00c000c, &ixCC_GIO_IOCCFG_FUSES[0], sizeof(ixCC_GIO_IOCCFG_FUSES)/sizeof(ixCC_GIO_IOCCFG_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOC_FUSES", REG_SMC, 0xc00c0010, &ixCC_GIO_IOC_FUSES[0], sizeof(ixCC_GIO_IOC_FUSES)/sizeof(ixCC_GIO_IOC_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_TST_EFUSE1_MISC", REG_SMC, 0xc00c001c, &ixCC_SMU_TST_EFUSE1_MISC[0], sizeof(ixCC_SMU_TST_EFUSE1_MISC)/sizeof(ixCC_SMU_TST_EFUSE1_MISC[0]), 0, 0 },
+	{ "ixCC_TST_ID_STRAPS", REG_SMC, 0xc00c0020, &ixCC_TST_ID_STRAPS[0], sizeof(ixCC_TST_ID_STRAPS)/sizeof(ixCC_TST_ID_STRAPS[0]), 0, 0 },
+	{ "ixCC_FCTRL_FUSES", REG_SMC, 0xc00c0024, &ixCC_FCTRL_FUSES[0], sizeof(ixCC_FCTRL_FUSES)/sizeof(ixCC_FCTRL_FUSES[0]), 0, 0 },
+	{ "ixSMU_EFUSE_0", REG_SMC, 0xc0100000, &ixSMU_EFUSE_0[0], sizeof(ixSMU_EFUSE_0)/sizeof(ixSMU_EFUSE_0[0]), 0, 0 },
+	{ "ixGENERAL_PWRMGT", REG_SMC, 0xc0200000, &ixGENERAL_PWRMGT[0], sizeof(ixGENERAL_PWRMGT)/sizeof(ixGENERAL_PWRMGT[0]), 0, 0 },
+	{ "ixCNB_PWRMGT_CNTL", REG_SMC, 0xc0200004, &ixCNB_PWRMGT_CNTL[0], sizeof(ixCNB_PWRMGT_CNTL)/sizeof(ixCNB_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixSCLK_PWRMGT_CNTL", REG_SMC, 0xc0200008, &ixSCLK_PWRMGT_CNTL[0], sizeof(ixSCLK_PWRMGT_CNTL)/sizeof(ixSCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX", REG_SMC, 0xc0200014, &ixTARGET_AND_CURRENT_PROFILE_INDEX[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX[0]), 0, 0 },
+	{ "ixPLL_TEST_CNTL", REG_SMC, 0xc020003c, &ixPLL_TEST_CNTL[0], sizeof(ixPLL_TEST_CNTL)/sizeof(ixPLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixCG_STATIC_SCREEN_PARAMETER", REG_SMC, 0xc0200044, &ixCG_STATIC_SCREEN_PARAMETER[0], sizeof(ixCG_STATIC_SCREEN_PARAMETER)/sizeof(ixCG_STATIC_SCREEN_PARAMETER[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL", REG_SMC, 0xc0200060, &ixCG_DISPLAY_GAP_CNTL[0], sizeof(ixCG_DISPLAY_GAP_CNTL)/sizeof(ixCG_DISPLAY_GAP_CNTL[0]), 0, 0 },
+	{ "ixCG_ACPI_CNTL", REG_SMC, 0xc0200064, &ixCG_ACPI_CNTL[0], sizeof(ixCG_ACPI_CNTL)/sizeof(ixCG_ACPI_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc0200080, &ixSCLK_DEEP_SLEEP_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200084, &ixSCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL2)/sizeof(ixSCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_MISC_CNTL", REG_SMC, 0xc0200088, &ixSCLK_DEEP_SLEEP_MISC_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc020008c, &ixLCLK_DEEP_SLEEP_CNTL[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL)/sizeof(ixLCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSMU_VOLTAGE_STATUS", REG_SMC, 0xc0200094, &ixSMU_VOLTAGE_STATUS[0], sizeof(ixSMU_VOLTAGE_STATUS)/sizeof(ixSMU_VOLTAGE_STATUS[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL3", REG_SMC, 0xc020009c, &ixSCLK_DEEP_SLEEP_CNTL3[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL3)/sizeof(ixSCLK_DEEP_SLEEP_CNTL3[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_1", REG_SMC, 0xc02000f0, &ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0]), 0, 0 },
+	{ "ixCG_ULV_PARAMETER", REG_SMC, 0xc020015c, &ixCG_ULV_PARAMETER[0], sizeof(ixCG_ULV_PARAMETER)/sizeof(ixCG_ULV_PARAMETER[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_0", REG_SMC, 0xc02001a8, &ixCG_FREQ_TRAN_VOTING_0[0], sizeof(ixCG_FREQ_TRAN_VOTING_0)/sizeof(ixCG_FREQ_TRAN_VOTING_0[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_1", REG_SMC, 0xc02001ac, &ixCG_FREQ_TRAN_VOTING_1[0], sizeof(ixCG_FREQ_TRAN_VOTING_1)/sizeof(ixCG_FREQ_TRAN_VOTING_1[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_2", REG_SMC, 0xc02001b0, &ixCG_FREQ_TRAN_VOTING_2[0], sizeof(ixCG_FREQ_TRAN_VOTING_2)/sizeof(ixCG_FREQ_TRAN_VOTING_2[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_3", REG_SMC, 0xc02001b4, &ixCG_FREQ_TRAN_VOTING_3[0], sizeof(ixCG_FREQ_TRAN_VOTING_3)/sizeof(ixCG_FREQ_TRAN_VOTING_3[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_4", REG_SMC, 0xc02001b8, &ixCG_FREQ_TRAN_VOTING_4[0], sizeof(ixCG_FREQ_TRAN_VOTING_4)/sizeof(ixCG_FREQ_TRAN_VOTING_4[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_5", REG_SMC, 0xc02001bc, &ixCG_FREQ_TRAN_VOTING_5[0], sizeof(ixCG_FREQ_TRAN_VOTING_5)/sizeof(ixCG_FREQ_TRAN_VOTING_5[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, &ixCG_DISPLAY_GAP_CNTL2[0], sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_MIN_DIV", REG_SMC, 0xc0200308, &ixSCLK_MIN_DIV[0], sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixLCAC_SX0_CNTL", REG_SMC, 0xc0400d00, &ixLCAC_SX0_CNTL[0], sizeof(ixLCAC_SX0_CNTL)/sizeof(ixLCAC_SX0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_SX0_OVR_SEL", REG_SMC, 0xc0400d04, &ixLCAC_SX0_OVR_SEL[0], sizeof(ixLCAC_SX0_OVR_SEL)/sizeof(ixLCAC_SX0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_SX0_OVR_VAL", REG_SMC, 0xc0400d08, &ixLCAC_SX0_OVR_VAL[0], sizeof(ixLCAC_SX0_OVR_VAL)/sizeof(ixLCAC_SX0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC0_CNTL", REG_SMC, 0xc0400d30, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0xc0400d34, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0xc0400d38, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC1_CNTL", REG_SMC, 0xc0400d3c, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0xc0400d40, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0xc0400d44, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC2_CNTL", REG_SMC, 0xc0400d48, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0xc0400d4c, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0xc0400d50, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC3_CNTL", REG_SMC, 0xc0400d54, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0xc0400d58, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0xc0400d5c, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_CPL_CNTL", REG_SMC, 0xc0400d80, &ixLCAC_CPL_CNTL[0], sizeof(ixLCAC_CPL_CNTL)/sizeof(ixLCAC_CPL_CNTL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_SEL", REG_SMC, 0xc0400d84, &ixLCAC_CPL_OVR_SEL[0], sizeof(ixLCAC_CPL_OVR_SEL)/sizeof(ixLCAC_CPL_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_VAL", REG_SMC, 0xc0400d88, &ixLCAC_CPL_OVR_VAL[0], sizeof(ixLCAC_CPL_OVR_VAL)/sizeof(ixLCAC_CPL_OVR_VAL[0]), 0, 0 },
+	{ "ixCG_DCLK_CNTL", REG_SMC, 0xc050009c, &ixCG_DCLK_CNTL[0], sizeof(ixCG_DCLK_CNTL)/sizeof(ixCG_DCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_DCLK_STATUS", REG_SMC, 0xc05000a0, &ixCG_DCLK_STATUS[0], sizeof(ixCG_DCLK_STATUS)/sizeof(ixCG_DCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_VCLK_CNTL", REG_SMC, 0xc05000a4, &ixCG_VCLK_CNTL[0], sizeof(ixCG_VCLK_CNTL)/sizeof(ixCG_VCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_VCLK_STATUS", REG_SMC, 0xc05000a8, &ixCG_VCLK_STATUS[0], sizeof(ixCG_VCLK_STATUS)/sizeof(ixCG_VCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ECLK_CNTL", REG_SMC, 0xc05000ac, &ixCG_ECLK_CNTL[0], sizeof(ixCG_ECLK_CNTL)/sizeof(ixCG_ECLK_CNTL[0]), 0, 0 },
+	{ "ixCG_ECLK_STATUS", REG_SMC, 0xc05000b0, &ixCG_ECLK_STATUS[0], sizeof(ixCG_ECLK_STATUS)/sizeof(ixCG_ECLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ACLK_CNTL", REG_SMC, 0xc05000dc, &ixCG_ACLK_CNTL[0], sizeof(ixCG_ACLK_CNTL)/sizeof(ixCG_ACLK_CNTL[0]), 0, 0 },
+	{ "ixGCK_DFS_BYPASS_CNTL", REG_SMC, 0xc0500118, &ixGCK_DFS_BYPASS_CNTL[0], sizeof(ixGCK_DFS_BYPASS_CNTL)/sizeof(ixGCK_DFS_BYPASS_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL", REG_SMC, 0xc0500140, &ixCG_SPLL_FUNC_CNTL[0], sizeof(ixCG_SPLL_FUNC_CNTL)/sizeof(ixCG_SPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_2", REG_SMC, 0xc0500144, &ixCG_SPLL_FUNC_CNTL_2[0], sizeof(ixCG_SPLL_FUNC_CNTL_2)/sizeof(ixCG_SPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_3", REG_SMC, 0xc0500148, &ixCG_SPLL_FUNC_CNTL_3[0], sizeof(ixCG_SPLL_FUNC_CNTL_3)/sizeof(ixCG_SPLL_FUNC_CNTL_3[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_4", REG_SMC, 0xc050014c, &ixCG_SPLL_FUNC_CNTL_4[0], sizeof(ixCG_SPLL_FUNC_CNTL_4)/sizeof(ixCG_SPLL_FUNC_CNTL_4[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_5", REG_SMC, 0xc0500150, &ixCG_SPLL_FUNC_CNTL_5[0], sizeof(ixCG_SPLL_FUNC_CNTL_5)/sizeof(ixCG_SPLL_FUNC_CNTL_5[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_6", REG_SMC, 0xc0500154, &ixCG_SPLL_FUNC_CNTL_6[0], sizeof(ixCG_SPLL_FUNC_CNTL_6)/sizeof(ixCG_SPLL_FUNC_CNTL_6[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_7", REG_SMC, 0xc0500158, &ixCG_SPLL_FUNC_CNTL_7[0], sizeof(ixCG_SPLL_FUNC_CNTL_7)/sizeof(ixCG_SPLL_FUNC_CNTL_7[0]), 0, 0 },
+	{ "ixSPLL_CNTL_MODE", REG_SMC, 0xc0500160, &ixSPLL_CNTL_MODE[0], sizeof(ixSPLL_CNTL_MODE)/sizeof(ixSPLL_CNTL_MODE[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM", REG_SMC, 0xc0500164, &ixCG_SPLL_SPREAD_SPECTRUM[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM_2", REG_SMC, 0xc0500168, &ixCG_SPLL_SPREAD_SPECTRUM_2[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2[0]), 0, 0 },
+	{ "ixMPLL_BYPASSCLK_SEL", REG_SMC, 0xc050019c, &ixMPLL_BYPASSCLK_SEL[0], sizeof(ixMPLL_BYPASSCLK_SEL)/sizeof(ixMPLL_BYPASSCLK_SEL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL", REG_SMC, 0xc05001a0, &ixCG_CLKPIN_CNTL[0], sizeof(ixCG_CLKPIN_CNTL)/sizeof(ixCG_CLKPIN_CNTL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_2", REG_SMC, 0xc05001a4, &ixCG_CLKPIN_CNTL_2[0], sizeof(ixCG_CLKPIN_CNTL_2)/sizeof(ixCG_CLKPIN_CNTL_2[0]), 0, 0 },
+	{ "ixTHM_CLK_CNTL", REG_SMC, 0xc05001a8, &ixTHM_CLK_CNTL[0], sizeof(ixTHM_CLK_CNTL)/sizeof(ixTHM_CLK_CNTL[0]), 0, 0 },
+	{ "ixMISC_CLK_CTRL", REG_SMC, 0xc05001ac, &ixMISC_CLK_CTRL[0], sizeof(ixMISC_CLK_CTRL)/sizeof(ixMISC_CLK_CTRL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL", REG_SMC, 0xc05001c0, &ixGCK_PLL_TEST_CNTL[0], sizeof(ixGCK_PLL_TEST_CNTL)/sizeof(ixGCK_PLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL_2", REG_SMC, 0xc05001c4, &ixGCK_PLL_TEST_CNTL_2[0], sizeof(ixGCK_PLL_TEST_CNTL_2)/sizeof(ixGCK_PLL_TEST_CNTL_2[0]), 0, 0 },
+	{ "ixGCK_ADFS_CLK_BYPASS_CNTL1", REG_SMC, 0xc05001c8, &ixGCK_ADFS_CLK_BYPASS_CNTL1[0], sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1)/sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, &ixCG_THERMAL_INT_ENA[0], sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, &ixCG_THERMAL_INT_CTRL[0], sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, &ixCG_THERMAL_INT_STATUS[0], sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
+	{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, &ixSMU_MAIN_PLL_OP_FREQ[0], sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
+	{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
+	{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
+	{ "ixSMU_INPUT_DATA", REG_SMC, 0xe00030b8, &ixSMU_INPUT_DATA[0], sizeof(ixSMU_INPUT_DATA)/sizeof(ixSMU_INPUT_DATA[0]), 0, 0 },
diff --git a/src/lib/ip/smu701.c b/src/lib/ip/smu701.c
new file mode 100644
index 0000000..06c811e
--- /dev/null
+++ b/src/lib/ip/smu701.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "smu701_bits.i"
+
+static const struct umr_reg smu701_registers[] = {
+#include "smu701_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_smu701(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "smu701";
+	ip->no_regs = sizeof(smu701_registers)/sizeof(smu701_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(smu701_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, smu701_registers, sizeof(smu701_registers));
+	return ip;
+}
diff --git a/src/lib/ip/smu701_bits.i b/src/lib/ip/smu701_bits.i
new file mode 100644
index 0000000..972d8b7
--- /dev/null
+++ b/src/lib/ip/smu701_bits.i
@@ -0,0 +1,5208 @@
+static struct umr_bitfield mmGPIOPAD_SW_INT_STAT[] = {
+	 { "SW_INT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_STRENGTH[] = {
+	 { "GPIO_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GPIO_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_MASK[] = {
+	 { "GPIO_MASK", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_A[] = {
+	 { "GPIO_A", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EN[] = {
+	 { "GPIO_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_Y[] = {
+	 { "GPIO_Y", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PINSTRAPS[] = {
+	 { "GPIO_PINSTRAP_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_28", 28, 28, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_29", 29, 29, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_30", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_EN[] = {
+	 { "GPIO_INT_STAT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT[] = {
+	 { "GPIO_INT_STAT", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_AK[] = {
+	 { "GPIO_INT_STAT_AK_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_28", 28, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_AK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_EN[] = {
+	 { "GPIO_INT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_TYPE[] = {
+	 { "GPIO_INT_TYPE", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_POLARITY[] = {
+	 { "GPIO_INT_POLARITY", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_POLARITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EXTERN_TRIG_CNTL[] = {
+	 { "EXTERN_TRIG_SEL", 0, 4, &umr_bitfield_default },
+	 { "EXTERN_TRIG_CLR", 5, 5, &umr_bitfield_default },
+	 { "EXTERN_TRIG_READ", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_RCVR_SEL[] = {
+	 { "GPIO_RCVR_SEL", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PU_EN[] = {
+	 { "GPIO_PU_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PD_EN[] = {
+	 { "GPIO_PD_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCG_FPS_CNT[] = {
+	 { "FPS_CNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_1[] = {
+	 { "GraphicsPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_2[] = {
+	 { "GraphicsPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_3[] = {
+	 { "GraphicsPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_4[] = {
+	 { "GraphicsPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_5[] = {
+	 { "GraphicsPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_6[] = {
+	 { "GraphicsPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_7[] = {
+	 { "GraphicsPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_8[] = {
+	 { "GraphicsPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_9[] = {
+	 { "GraphicsPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_10[] = {
+	 { "MemoryPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_11[] = {
+	 { "MemoryPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_12[] = {
+	 { "MemoryPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_13[] = {
+	 { "MemoryPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_14[] = {
+	 { "MemoryPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_15[] = {
+	 { "MemoryPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_16[] = {
+	 { "MemoryPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_17[] = {
+	 { "MemoryPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_18[] = {
+	 { "MemoryPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_19[] = {
+	 { "LinkPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_20[] = {
+	 { "LinkPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_21[] = {
+	 { "LinkPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_22[] = {
+	 { "LinkPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_23[] = {
+	 { "LinkPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_24[] = {
+	 { "LinkPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_25[] = {
+	 { "LinkPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_26[] = {
+	 { "LinkPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_27[] = {
+	 { "LinkPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_28[] = {
+	 { "SystemFlags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_29[] = {
+	 { "SmioMaskVddcVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_30[] = {
+	 { "SmioMaskVddcPhase", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_31[] = {
+	 { "SmioMaskVddciVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_32[] = {
+	 { "SmioMaskMvddVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_33[] = {
+	 { "VddcLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_34[] = {
+	 { "VddciLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_35[] = {
+	 { "MvddLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_36[] = {
+	 { "VddcLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_37[] = {
+	 { "VddcLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_38[] = {
+	 { "VddcLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_39[] = {
+	 { "VddcLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_40[] = {
+	 { "VddcLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_41[] = {
+	 { "VddcLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_42[] = {
+	 { "VddcLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_43[] = {
+	 { "VddcLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_44[] = {
+	 { "VddcLevel_4_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_4_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_45[] = {
+	 { "VddcLevel_4_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_4_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_4_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_46[] = {
+	 { "VddcLevel_5_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_5_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_47[] = {
+	 { "VddcLevel_5_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_5_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_5_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_48[] = {
+	 { "VddcLevel_6_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_6_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_49[] = {
+	 { "VddcLevel_6_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_6_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_6_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_50[] = {
+	 { "VddcLevel_7_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_7_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_51[] = {
+	 { "VddcLevel_7_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_7_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_7_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_52[] = {
+	 { "VddciLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_53[] = {
+	 { "VddciLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_54[] = {
+	 { "VddciLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_55[] = {
+	 { "VddciLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_56[] = {
+	 { "VddciLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_57[] = {
+	 { "VddciLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_58[] = {
+	 { "VddciLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_59[] = {
+	 { "VddciLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_60[] = {
+	 { "MvddLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_61[] = {
+	 { "MvddLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_62[] = {
+	 { "MvddLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_63[] = {
+	 { "MvddLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_64[] = {
+	 { "MvddLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_65[] = {
+	 { "MvddLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_66[] = {
+	 { "MvddLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_67[] = {
+	 { "MvddLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_68[] = {
+	 { "UvdLevelCount", 0, 7, &umr_bitfield_default },
+	 { "LinkLevelCount", 8, 15, &umr_bitfield_default },
+	 { "MemoryDpmLevelCount", 16, 23, &umr_bitfield_default },
+	 { "GraphicsDpmLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_69[] = {
+	 { "padding2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevelCount", 8, 15, &umr_bitfield_default },
+	 { "AcpLevelCount", 16, 23, &umr_bitfield_default },
+	 { "VceLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_70[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_71[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_72[] = {
+	 { "Reserved_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_73[] = {
+	 { "Reserved_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_74[] = {
+	 { "Reserved_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_75[] = {
+	 { "GraphicsLevel_0_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_76[] = {
+	 { "GraphicsLevel_0_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_77[] = {
+	 { "GraphicsLevel_0_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_78[] = {
+	 { "GraphicsLevel_0_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_79[] = {
+	 { "GraphicsLevel_0_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_padding1_1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_padding1_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_80[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_81[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_82[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_83[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_84[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_85[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_86[] = {
+	 { "GraphicsLevel_0_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_87[] = {
+	 { "GraphicsLevel_0_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_88[] = {
+	 { "GraphicsLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_89[] = {
+	 { "GraphicsLevel_1_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_90[] = {
+	 { "GraphicsLevel_1_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_91[] = {
+	 { "GraphicsLevel_1_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_92[] = {
+	 { "GraphicsLevel_1_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_93[] = {
+	 { "GraphicsLevel_1_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_padding1_1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_padding1_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_94[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_95[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_96[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_97[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_98[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_99[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_100[] = {
+	 { "GraphicsLevel_1_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_101[] = {
+	 { "GraphicsLevel_1_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_102[] = {
+	 { "GraphicsLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_103[] = {
+	 { "GraphicsLevel_2_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_104[] = {
+	 { "GraphicsLevel_2_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_105[] = {
+	 { "GraphicsLevel_2_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_106[] = {
+	 { "GraphicsLevel_2_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_107[] = {
+	 { "GraphicsLevel_2_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_padding1_1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_padding1_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_108[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_109[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_110[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_111[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_112[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_113[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_114[] = {
+	 { "GraphicsLevel_2_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_115[] = {
+	 { "GraphicsLevel_2_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_116[] = {
+	 { "GraphicsLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_117[] = {
+	 { "GraphicsLevel_3_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_118[] = {
+	 { "GraphicsLevel_3_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_119[] = {
+	 { "GraphicsLevel_3_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_120[] = {
+	 { "GraphicsLevel_3_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_121[] = {
+	 { "GraphicsLevel_3_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_padding1_1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_padding1_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_122[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_123[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_124[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_125[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_126[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_127[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_128[] = {
+	 { "GraphicsLevel_3_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_129[] = {
+	 { "GraphicsLevel_3_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_130[] = {
+	 { "GraphicsLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_131[] = {
+	 { "GraphicsLevel_4_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_132[] = {
+	 { "GraphicsLevel_4_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_133[] = {
+	 { "GraphicsLevel_4_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_134[] = {
+	 { "GraphicsLevel_4_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_135[] = {
+	 { "GraphicsLevel_4_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_padding1_1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_padding1_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_136[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_137[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_138[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_139[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_140[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_141[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_142[] = {
+	 { "GraphicsLevel_4_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_143[] = {
+	 { "GraphicsLevel_4_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_144[] = {
+	 { "GraphicsLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_145[] = {
+	 { "GraphicsLevel_5_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_146[] = {
+	 { "GraphicsLevel_5_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_147[] = {
+	 { "GraphicsLevel_5_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_148[] = {
+	 { "GraphicsLevel_5_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_149[] = {
+	 { "GraphicsLevel_5_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_padding1_1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_padding1_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_150[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_151[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_152[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_153[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_154[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_155[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_156[] = {
+	 { "GraphicsLevel_5_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_157[] = {
+	 { "GraphicsLevel_5_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_158[] = {
+	 { "GraphicsLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_159[] = {
+	 { "GraphicsLevel_6_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_160[] = {
+	 { "GraphicsLevel_6_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_161[] = {
+	 { "GraphicsLevel_6_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_162[] = {
+	 { "GraphicsLevel_6_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_163[] = {
+	 { "GraphicsLevel_6_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_padding1_1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_padding1_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_164[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_165[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_166[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_167[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_168[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_169[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_170[] = {
+	 { "GraphicsLevel_6_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_171[] = {
+	 { "GraphicsLevel_6_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_172[] = {
+	 { "GraphicsLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_173[] = {
+	 { "GraphicsLevel_7_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_174[] = {
+	 { "GraphicsLevel_7_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_175[] = {
+	 { "GraphicsLevel_7_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_176[] = {
+	 { "GraphicsLevel_7_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_177[] = {
+	 { "GraphicsLevel_7_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_padding1_1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_padding1_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_178[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_179[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_180[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_181[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_182[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_183[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_184[] = {
+	 { "GraphicsLevel_7_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_185[] = {
+	 { "GraphicsLevel_7_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_186[] = {
+	 { "GraphicsLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_187[] = {
+	 { "MemoryACPILevel_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_188[] = {
+	 { "MemoryACPILevel_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_189[] = {
+	 { "MemoryACPILevel_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_190[] = {
+	 { "MemoryACPILevel_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_191[] = {
+	 { "MemoryACPILevel_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_192[] = {
+	 { "MemoryACPILevel_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_193[] = {
+	 { "MemoryACPILevel_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_194[] = {
+	 { "MemoryACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_195[] = {
+	 { "MemoryACPILevel_padding1_1", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_padding1_0", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_196[] = {
+	 { "MemoryACPILevel_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_197[] = {
+	 { "MemoryACPILevel_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_198[] = {
+	 { "MemoryACPILevel_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_199[] = {
+	 { "MemoryACPILevel_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_200[] = {
+	 { "MemoryACPILevel_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_201[] = {
+	 { "MemoryACPILevel_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_202[] = {
+	 { "MemoryACPILevel_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_203[] = {
+	 { "MemoryACPILevel_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_204[] = {
+	 { "MemoryACPILevel_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_205[] = {
+	 { "MemoryLevel_0_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_206[] = {
+	 { "MemoryLevel_0_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_207[] = {
+	 { "MemoryLevel_0_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_208[] = {
+	 { "MemoryLevel_0_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_209[] = {
+	 { "MemoryLevel_0_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_210[] = {
+	 { "MemoryLevel_0_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_211[] = {
+	 { "MemoryLevel_0_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_212[] = {
+	 { "MemoryLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_213[] = {
+	 { "MemoryLevel_0_padding1_1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_padding1_0", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_214[] = {
+	 { "MemoryLevel_0_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_215[] = {
+	 { "MemoryLevel_0_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_216[] = {
+	 { "MemoryLevel_0_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_217[] = {
+	 { "MemoryLevel_0_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_218[] = {
+	 { "MemoryLevel_0_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_219[] = {
+	 { "MemoryLevel_0_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_220[] = {
+	 { "MemoryLevel_0_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_221[] = {
+	 { "MemoryLevel_0_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_222[] = {
+	 { "MemoryLevel_0_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_223[] = {
+	 { "MemoryLevel_1_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_224[] = {
+	 { "MemoryLevel_1_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_225[] = {
+	 { "MemoryLevel_1_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_226[] = {
+	 { "MemoryLevel_1_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_227[] = {
+	 { "MemoryLevel_1_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_228[] = {
+	 { "MemoryLevel_1_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_229[] = {
+	 { "MemoryLevel_1_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_230[] = {
+	 { "MemoryLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_231[] = {
+	 { "MemoryLevel_1_padding1_1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_padding1_0", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_232[] = {
+	 { "MemoryLevel_1_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_233[] = {
+	 { "MemoryLevel_1_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_234[] = {
+	 { "MemoryLevel_1_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_235[] = {
+	 { "MemoryLevel_1_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_236[] = {
+	 { "MemoryLevel_1_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_237[] = {
+	 { "MemoryLevel_1_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_238[] = {
+	 { "MemoryLevel_1_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_239[] = {
+	 { "MemoryLevel_1_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_240[] = {
+	 { "MemoryLevel_1_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_241[] = {
+	 { "MemoryLevel_2_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_242[] = {
+	 { "MemoryLevel_2_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_243[] = {
+	 { "MemoryLevel_2_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_244[] = {
+	 { "MemoryLevel_2_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_245[] = {
+	 { "MemoryLevel_2_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_246[] = {
+	 { "MemoryLevel_2_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_247[] = {
+	 { "MemoryLevel_2_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_248[] = {
+	 { "MemoryLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_249[] = {
+	 { "MemoryLevel_2_padding1_1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_padding1_0", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_250[] = {
+	 { "MemoryLevel_2_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_251[] = {
+	 { "MemoryLevel_2_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_252[] = {
+	 { "MemoryLevel_2_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_253[] = {
+	 { "MemoryLevel_2_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_254[] = {
+	 { "MemoryLevel_2_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_255[] = {
+	 { "MemoryLevel_2_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_256[] = {
+	 { "MemoryLevel_2_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_257[] = {
+	 { "MemoryLevel_2_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_258[] = {
+	 { "MemoryLevel_2_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_259[] = {
+	 { "MemoryLevel_3_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_260[] = {
+	 { "MemoryLevel_3_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_261[] = {
+	 { "MemoryLevel_3_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_262[] = {
+	 { "MemoryLevel_3_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_263[] = {
+	 { "MemoryLevel_3_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_264[] = {
+	 { "MemoryLevel_3_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_265[] = {
+	 { "MemoryLevel_3_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_266[] = {
+	 { "MemoryLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_267[] = {
+	 { "MemoryLevel_3_padding1_1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_padding1_0", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_268[] = {
+	 { "MemoryLevel_3_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_269[] = {
+	 { "MemoryLevel_3_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_270[] = {
+	 { "MemoryLevel_3_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_271[] = {
+	 { "MemoryLevel_3_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_272[] = {
+	 { "MemoryLevel_3_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_273[] = {
+	 { "MemoryLevel_3_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_274[] = {
+	 { "MemoryLevel_3_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_275[] = {
+	 { "MemoryLevel_3_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_276[] = {
+	 { "MemoryLevel_3_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_277[] = {
+	 { "MemoryLevel_4_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_278[] = {
+	 { "MemoryLevel_4_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_279[] = {
+	 { "MemoryLevel_4_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_280[] = {
+	 { "MemoryLevel_4_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_281[] = {
+	 { "MemoryLevel_4_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_282[] = {
+	 { "MemoryLevel_4_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_4_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_4_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_4_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_283[] = {
+	 { "MemoryLevel_4_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_4_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_4_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_4_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_284[] = {
+	 { "MemoryLevel_4_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_4_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_4_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_4_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_285[] = {
+	 { "MemoryLevel_4_padding1_1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_4_padding1_0", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_4_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_286[] = {
+	 { "MemoryLevel_4_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_287[] = {
+	 { "MemoryLevel_4_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_288[] = {
+	 { "MemoryLevel_4_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_289[] = {
+	 { "MemoryLevel_4_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_290[] = {
+	 { "MemoryLevel_4_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_291[] = {
+	 { "MemoryLevel_4_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_292[] = {
+	 { "MemoryLevel_4_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_293[] = {
+	 { "MemoryLevel_4_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_294[] = {
+	 { "MemoryLevel_4_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_295[] = {
+	 { "MemoryLevel_5_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_296[] = {
+	 { "MemoryLevel_5_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_297[] = {
+	 { "MemoryLevel_5_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_298[] = {
+	 { "MemoryLevel_5_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_299[] = {
+	 { "MemoryLevel_5_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_300[] = {
+	 { "MemoryLevel_5_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_5_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_5_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_5_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_301[] = {
+	 { "MemoryLevel_5_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_5_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_5_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_5_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_302[] = {
+	 { "MemoryLevel_5_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_5_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_5_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_5_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_303[] = {
+	 { "MemoryLevel_5_padding1_1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_5_padding1_0", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_5_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_304[] = {
+	 { "MemoryLevel_5_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_305[] = {
+	 { "MemoryLevel_5_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_306[] = {
+	 { "MemoryLevel_5_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_307[] = {
+	 { "MemoryLevel_5_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_308[] = {
+	 { "MemoryLevel_5_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_309[] = {
+	 { "MemoryLevel_5_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_310[] = {
+	 { "MemoryLevel_5_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_311[] = {
+	 { "MemoryLevel_5_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_312[] = {
+	 { "MemoryLevel_5_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_313[] = {
+	 { "LinkLevel_0_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_314[] = {
+	 { "LinkLevel_0_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_315[] = {
+	 { "LinkLevel_0_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_316[] = {
+	 { "LinkLevel_0_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_317[] = {
+	 { "LinkLevel_1_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_318[] = {
+	 { "LinkLevel_1_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_319[] = {
+	 { "LinkLevel_1_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_320[] = {
+	 { "LinkLevel_1_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_321[] = {
+	 { "LinkLevel_2_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_322[] = {
+	 { "LinkLevel_2_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_323[] = {
+	 { "LinkLevel_2_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_324[] = {
+	 { "LinkLevel_2_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_325[] = {
+	 { "LinkLevel_3_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_326[] = {
+	 { "LinkLevel_3_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_327[] = {
+	 { "LinkLevel_3_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_328[] = {
+	 { "LinkLevel_3_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_329[] = {
+	 { "LinkLevel_4_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_330[] = {
+	 { "LinkLevel_4_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_331[] = {
+	 { "LinkLevel_4_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_332[] = {
+	 { "LinkLevel_4_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_333[] = {
+	 { "LinkLevel_5_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_334[] = {
+	 { "LinkLevel_5_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_335[] = {
+	 { "LinkLevel_5_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_336[] = {
+	 { "LinkLevel_5_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_337[] = {
+	 { "LinkLevel_6_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_338[] = {
+	 { "LinkLevel_6_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_339[] = {
+	 { "LinkLevel_6_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_340[] = {
+	 { "LinkLevel_6_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_341[] = {
+	 { "LinkLevel_7_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_342[] = {
+	 { "LinkLevel_7_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_343[] = {
+	 { "LinkLevel_7_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_344[] = {
+	 { "LinkLevel_7_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_345[] = {
+	 { "ACPILevel_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_346[] = {
+	 { "ACPILevel_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_347[] = {
+	 { "ACPILevel_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_348[] = {
+	 { "ACPILevel_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_349[] = {
+	 { "ACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_350[] = {
+	 { "ACPILevel_CgSpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_351[] = {
+	 { "ACPILevel_CgSpllFuncCntl2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_352[] = {
+	 { "ACPILevel_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_353[] = {
+	 { "ACPILevel_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_354[] = {
+	 { "ACPILevel_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_355[] = {
+	 { "ACPILevel_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_356[] = {
+	 { "ACPILevel_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_357[] = {
+	 { "ACPILevel_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_358[] = {
+	 { "UvdLevel_0_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_359[] = {
+	 { "UvdLevel_0_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_360[] = {
+	 { "UvdLevel_0_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_361[] = {
+	 { "UvdLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_0_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_362[] = {
+	 { "UvdLevel_1_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_363[] = {
+	 { "UvdLevel_1_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_364[] = {
+	 { "UvdLevel_1_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_365[] = {
+	 { "UvdLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_1_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_366[] = {
+	 { "UvdLevel_2_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_367[] = {
+	 { "UvdLevel_2_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_368[] = {
+	 { "UvdLevel_2_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_369[] = {
+	 { "UvdLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_2_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_370[] = {
+	 { "UvdLevel_3_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_371[] = {
+	 { "UvdLevel_3_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_372[] = {
+	 { "UvdLevel_3_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_373[] = {
+	 { "UvdLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_3_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_374[] = {
+	 { "UvdLevel_4_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_375[] = {
+	 { "UvdLevel_4_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_376[] = {
+	 { "UvdLevel_4_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_377[] = {
+	 { "UvdLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_4_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_378[] = {
+	 { "UvdLevel_5_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_379[] = {
+	 { "UvdLevel_5_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_380[] = {
+	 { "UvdLevel_5_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_381[] = {
+	 { "UvdLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_5_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_382[] = {
+	 { "UvdLevel_6_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_383[] = {
+	 { "UvdLevel_6_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_384[] = {
+	 { "UvdLevel_6_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_385[] = {
+	 { "UvdLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_6_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_386[] = {
+	 { "UvdLevel_7_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_387[] = {
+	 { "UvdLevel_7_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_388[] = {
+	 { "UvdLevel_7_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_389[] = {
+	 { "UvdLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_7_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_390[] = {
+	 { "VceLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_391[] = {
+	 { "VceLevel_0_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_0_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_392[] = {
+	 { "VceLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_393[] = {
+	 { "VceLevel_1_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_1_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_394[] = {
+	 { "VceLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_395[] = {
+	 { "VceLevel_2_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_2_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_396[] = {
+	 { "VceLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_397[] = {
+	 { "VceLevel_3_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_3_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_398[] = {
+	 { "VceLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_399[] = {
+	 { "VceLevel_4_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_4_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_400[] = {
+	 { "VceLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_401[] = {
+	 { "VceLevel_5_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_5_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_402[] = {
+	 { "VceLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_403[] = {
+	 { "VceLevel_6_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_6_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_404[] = {
+	 { "VceLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_405[] = {
+	 { "VceLevel_7_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_7_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_406[] = {
+	 { "AcpLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_407[] = {
+	 { "AcpLevel_0_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_0_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_408[] = {
+	 { "AcpLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_409[] = {
+	 { "AcpLevel_1_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_1_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_410[] = {
+	 { "AcpLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_411[] = {
+	 { "AcpLevel_2_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_2_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_412[] = {
+	 { "AcpLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_413[] = {
+	 { "AcpLevel_3_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_3_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_414[] = {
+	 { "AcpLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_415[] = {
+	 { "AcpLevel_4_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_4_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_416[] = {
+	 { "AcpLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_417[] = {
+	 { "AcpLevel_5_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_5_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_418[] = {
+	 { "AcpLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_419[] = {
+	 { "AcpLevel_6_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_6_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_420[] = {
+	 { "AcpLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_421[] = {
+	 { "AcpLevel_7_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_7_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_422[] = {
+	 { "SamuLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_423[] = {
+	 { "SamuLevel_0_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_0_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_424[] = {
+	 { "SamuLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_425[] = {
+	 { "SamuLevel_1_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_1_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_426[] = {
+	 { "SamuLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_427[] = {
+	 { "SamuLevel_2_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_2_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_428[] = {
+	 { "SamuLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_429[] = {
+	 { "SamuLevel_3_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_3_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_430[] = {
+	 { "SamuLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_431[] = {
+	 { "SamuLevel_4_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_4_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_432[] = {
+	 { "SamuLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_433[] = {
+	 { "SamuLevel_5_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_5_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_434[] = {
+	 { "SamuLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_435[] = {
+	 { "SamuLevel_6_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_6_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_436[] = {
+	 { "SamuLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_437[] = {
+	 { "SamuLevel_7_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_7_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_438[] = {
+	 { "Ulv_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_439[] = {
+	 { "Ulv_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_440[] = {
+	 { "Ulv_VddcPhase", 0, 7, &umr_bitfield_default },
+	 { "Ulv_VddcOffsetVid", 8, 15, &umr_bitfield_default },
+	 { "Ulv_VddcOffset", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_441[] = {
+	 { "Ulv_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_442[] = {
+	 { "SclkStepSize", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_443[] = {
+	 { "Smio_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_444[] = {
+	 { "Smio_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_445[] = {
+	 { "Smio_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_446[] = {
+	 { "Smio_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_447[] = {
+	 { "Smio_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_448[] = {
+	 { "Smio_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_449[] = {
+	 { "Smio_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_450[] = {
+	 { "Smio_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_451[] = {
+	 { "Smio_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_452[] = {
+	 { "Smio_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_453[] = {
+	 { "Smio_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_454[] = {
+	 { "Smio_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_455[] = {
+	 { "Smio_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_456[] = {
+	 { "Smio_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_457[] = {
+	 { "Smio_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_458[] = {
+	 { "Smio_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_459[] = {
+	 { "Smio_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_460[] = {
+	 { "Smio_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_461[] = {
+	 { "Smio_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_462[] = {
+	 { "Smio_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_463[] = {
+	 { "Smio_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_464[] = {
+	 { "Smio_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_465[] = {
+	 { "Smio_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_466[] = {
+	 { "Smio_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_467[] = {
+	 { "Smio_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_468[] = {
+	 { "Smio_25", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_469[] = {
+	 { "Smio_26", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_470[] = {
+	 { "Smio_27", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_471[] = {
+	 { "Smio_28", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_472[] = {
+	 { "Smio_29", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_473[] = {
+	 { "Smio_30", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_474[] = {
+	 { "Smio_31", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_475[] = {
+	 { "SamuBootLevel", 0, 7, &umr_bitfield_default },
+	 { "AcpBootLevel", 8, 15, &umr_bitfield_default },
+	 { "VceBootLevel", 16, 23, &umr_bitfield_default },
+	 { "UvdBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_476[] = {
+	 { "SAMUInterval", 0, 7, &umr_bitfield_default },
+	 { "ACPInterval", 8, 15, &umr_bitfield_default },
+	 { "VCEInterval", 16, 23, &umr_bitfield_default },
+	 { "UVDInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_477[] = {
+	 { "GraphicsInterval", 0, 7, &umr_bitfield_default },
+	 { "GraphicsThermThrottleEnable", 8, 15, &umr_bitfield_default },
+	 { "GraphicsVoltageChangeEnable", 16, 23, &umr_bitfield_default },
+	 { "GraphicsBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_478[] = {
+	 { "TemperatureLimitHigh", 0, 15, &umr_bitfield_default },
+	 { "ThermalInterval", 16, 23, &umr_bitfield_default },
+	 { "VoltageInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_479[] = {
+	 { "MemoryVoltageChangeEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryBootLevel", 8, 15, &umr_bitfield_default },
+	 { "TemperatureLimitLow", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_480[] = {
+	 { "VddcVddciDelta", 0, 15, &umr_bitfield_default },
+	 { "MemoryThermThrottleEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_481[] = {
+	 { "PhaseResponseTime", 0, 15, &umr_bitfield_default },
+	 { "VoltageResponseTime", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_482[] = {
+	 { "DTEMode", 0, 7, &umr_bitfield_default },
+	 { "DTEInterval", 8, 15, &umr_bitfield_default },
+	 { "PCIeGenInterval", 16, 23, &umr_bitfield_default },
+	 { "PCIeBootLinkLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_483[] = {
+	 { "ThermGpio", 0, 7, &umr_bitfield_default },
+	 { "AcDcGpio", 8, 15, &umr_bitfield_default },
+	 { "VRHotGpio", 16, 23, &umr_bitfield_default },
+	 { "SVI2Enable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_484[] = {
+	 { "DisplayCac", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_485[] = {
+	 { "NomPwr", 0, 15, &umr_bitfield_default },
+	 { "MaxPwr", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_486[] = {
+	 { "FpsLowThreshold", 0, 15, &umr_bitfield_default },
+	 { "FpsHighThreshold", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_487[] = {
+	 { "BAPMTI_R_0_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_488[] = {
+	 { "BAPMTI_R_1_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_489[] = {
+	 { "BAPMTI_R_1_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_1_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_490[] = {
+	 { "BAPMTI_R_2_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_491[] = {
+	 { "BAPMTI_R_3_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_492[] = {
+	 { "BAPMTI_R_3_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_3_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_493[] = {
+	 { "BAPMTI_R_4_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_494[] = {
+	 { "BAPMTI_RC_0_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_495[] = {
+	 { "BAPMTI_RC_0_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_0_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_496[] = {
+	 { "BAPMTI_RC_1_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_497[] = {
+	 { "BAPMTI_RC_2_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_498[] = {
+	 { "BAPMTI_RC_2_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_2_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_499[] = {
+	 { "BAPMTI_RC_3_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_500[] = {
+	 { "BAPMTI_RC_4_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_501[] = {
+	 { "BAPMTI_RC_4_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_4_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_502[] = {
+	 { "GpuTjHyst", 0, 7, &umr_bitfield_default },
+	 { "GpuTjMax", 8, 15, &umr_bitfield_default },
+	 { "DTETjOffset", 16, 23, &umr_bitfield_default },
+	 { "DTEAmbientTempBase", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_503[] = {
+	 { "BootVddci", 0, 15, &umr_bitfield_default },
+	 { "BootVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_504[] = {
+	 { "padding", 0, 15, &umr_bitfield_default },
+	 { "BootMVdd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_505[] = {
+	 { "DRAM_LOG_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_506[] = {
+	 { "DRAM_LOG_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_507[] = {
+	 { "DRAM_LOG_PHY_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_508[] = {
+	 { "DRAM_LOG_PHY_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_509[] = {
+	 { "DRAM_LOG_BUFF_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_510[] = {
+	 { "BAPM_TEMP_GRADIENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFIRMWARE_FLAGS[] = {
+	 { "INTERRUPTS_ENABLED", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 23, &umr_bitfield_default },
+	 { "TEST_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_STATUS[] = {
+	 { "VDD_Boost", 0, 7, &umr_bitfield_default },
+	 { "VDD_Throttle", 8, 15, &umr_bitfield_default },
+	 { "VDDC_Boost", 16, 23, &umr_bitfield_default },
+	 { "VDDC_Throttle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_MV_AVERAGE[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_VRM_LIMIT[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFEATURE_STATUS[] = {
+	 { "SCLK_DPM_ON", 0, 0, &umr_bitfield_default },
+	 { "MCLK_DPM_ON", 1, 1, &umr_bitfield_default },
+	 { "LCLK_DPM_ON", 2, 2, &umr_bitfield_default },
+	 { "UVD_DPM_ON", 3, 3, &umr_bitfield_default },
+	 { "VCE_DPM_ON", 4, 4, &umr_bitfield_default },
+	 { "ACP_DPM_ON", 5, 5, &umr_bitfield_default },
+	 { "SAMU_DPM_ON", 6, 6, &umr_bitfield_default },
+	 { "PCIE_DPM_ON", 7, 7, &umr_bitfield_default },
+	 { "BAPM_ON", 8, 8, &umr_bitfield_default },
+	 { "LPMX_ON", 9, 9, &umr_bitfield_default },
+	 { "NBDPM_ON", 10, 10, &umr_bitfield_default },
+	 { "LHTC_ON", 11, 11, &umr_bitfield_default },
+	 { "VPC_ON", 12, 12, &umr_bitfield_default },
+	 { "VOLTAGE_CONTROLLER_ON", 13, 13, &umr_bitfield_default },
+	 { "TDC_LIMIT_ON", 14, 14, &umr_bitfield_default },
+	 { "GPU_CAC_ON", 15, 15, &umr_bitfield_default },
+	 { "AVS_ON", 16, 16, &umr_bitfield_default },
+	 { "SPMI_ON", 17, 17, &umr_bitfield_default },
+	 { "SCLK_DPM_FORCED", 18, 18, &umr_bitfield_default },
+	 { "MCLK_DPM_FORCED", 19, 19, &umr_bitfield_default },
+	 { "LCLK_DPM_FORCED", 20, 20, &umr_bitfield_default },
+	 { "PCIE_DPM_FORCED", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixENTITY_TEMPERATURES_1[] = {
+	 { "GPU", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_1[] = {
+	 { "entries_0_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_2[] = {
+	 { "entries_0_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_3[] = {
+	 { "entries_0_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_4[] = {
+	 { "entries_0_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_5[] = {
+	 { "entries_0_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_6[] = {
+	 { "entries_0_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_7[] = {
+	 { "entries_0_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_8[] = {
+	 { "entries_0_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_9[] = {
+	 { "entries_0_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_10[] = {
+	 { "entries_0_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_11[] = {
+	 { "entries_0_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_12[] = {
+	 { "entries_0_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_13[] = {
+	 { "entries_0_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_14[] = {
+	 { "entries_0_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_15[] = {
+	 { "entries_0_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_16[] = {
+	 { "entries_0_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_17[] = {
+	 { "entries_0_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_18[] = {
+	 { "entries_0_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_19[] = {
+	 { "entries_1_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_20[] = {
+	 { "entries_1_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_21[] = {
+	 { "entries_1_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_22[] = {
+	 { "entries_1_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_23[] = {
+	 { "entries_1_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_24[] = {
+	 { "entries_1_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_25[] = {
+	 { "entries_1_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_26[] = {
+	 { "entries_1_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_27[] = {
+	 { "entries_1_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_28[] = {
+	 { "entries_1_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_29[] = {
+	 { "entries_1_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_30[] = {
+	 { "entries_1_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_31[] = {
+	 { "entries_1_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_32[] = {
+	 { "entries_1_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_33[] = {
+	 { "entries_1_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_34[] = {
+	 { "entries_1_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_35[] = {
+	 { "entries_1_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_36[] = {
+	 { "entries_1_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_37[] = {
+	 { "entries_2_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_38[] = {
+	 { "entries_2_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_39[] = {
+	 { "entries_2_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_40[] = {
+	 { "entries_2_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_41[] = {
+	 { "entries_2_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_42[] = {
+	 { "entries_2_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_43[] = {
+	 { "entries_2_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_44[] = {
+	 { "entries_2_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_45[] = {
+	 { "entries_2_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_46[] = {
+	 { "entries_2_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_47[] = {
+	 { "entries_2_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_48[] = {
+	 { "entries_2_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_49[] = {
+	 { "entries_2_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_50[] = {
+	 { "entries_2_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_51[] = {
+	 { "entries_2_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_52[] = {
+	 { "entries_2_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_53[] = {
+	 { "entries_2_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_54[] = {
+	 { "entries_2_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_55[] = {
+	 { "entries_3_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_56[] = {
+	 { "entries_3_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_57[] = {
+	 { "entries_3_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_58[] = {
+	 { "entries_3_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_59[] = {
+	 { "entries_3_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_60[] = {
+	 { "entries_3_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_61[] = {
+	 { "entries_3_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_62[] = {
+	 { "entries_3_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_63[] = {
+	 { "entries_3_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_64[] = {
+	 { "entries_3_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_65[] = {
+	 { "entries_3_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_66[] = {
+	 { "entries_3_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_67[] = {
+	 { "entries_3_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_68[] = {
+	 { "entries_3_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_69[] = {
+	 { "entries_3_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_70[] = {
+	 { "entries_3_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_71[] = {
+	 { "entries_3_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_72[] = {
+	 { "entries_3_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_73[] = {
+	 { "entries_4_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_74[] = {
+	 { "entries_4_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_75[] = {
+	 { "entries_4_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_76[] = {
+	 { "entries_4_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_77[] = {
+	 { "entries_4_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_78[] = {
+	 { "entries_4_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_79[] = {
+	 { "entries_4_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_80[] = {
+	 { "entries_4_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_81[] = {
+	 { "entries_4_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_82[] = {
+	 { "entries_4_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_83[] = {
+	 { "entries_4_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_84[] = {
+	 { "entries_4_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_85[] = {
+	 { "entries_4_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_86[] = {
+	 { "entries_4_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_87[] = {
+	 { "entries_4_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_88[] = {
+	 { "entries_4_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_89[] = {
+	 { "entries_4_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_90[] = {
+	 { "entries_4_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_91[] = {
+	 { "entries_5_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_92[] = {
+	 { "entries_5_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_93[] = {
+	 { "entries_5_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_94[] = {
+	 { "entries_5_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_95[] = {
+	 { "entries_5_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_96[] = {
+	 { "entries_5_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_97[] = {
+	 { "entries_5_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_98[] = {
+	 { "entries_5_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_99[] = {
+	 { "entries_5_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_100[] = {
+	 { "entries_5_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_101[] = {
+	 { "entries_5_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_102[] = {
+	 { "entries_5_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_103[] = {
+	 { "entries_5_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_104[] = {
+	 { "entries_5_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_105[] = {
+	 { "entries_5_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_106[] = {
+	 { "entries_5_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_107[] = {
+	 { "entries_5_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_108[] = {
+	 { "entries_5_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_109[] = {
+	 { "entries_6_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_110[] = {
+	 { "entries_6_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_111[] = {
+	 { "entries_6_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_112[] = {
+	 { "entries_6_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_113[] = {
+	 { "entries_6_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_114[] = {
+	 { "entries_6_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_115[] = {
+	 { "entries_6_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_116[] = {
+	 { "entries_6_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_117[] = {
+	 { "entries_6_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_118[] = {
+	 { "entries_6_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_119[] = {
+	 { "entries_6_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_120[] = {
+	 { "entries_6_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_121[] = {
+	 { "entries_6_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_122[] = {
+	 { "entries_6_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_123[] = {
+	 { "entries_6_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_124[] = {
+	 { "entries_6_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_125[] = {
+	 { "entries_6_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_126[] = {
+	 { "entries_6_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_127[] = {
+	 { "entries_7_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_128[] = {
+	 { "entries_7_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_129[] = {
+	 { "entries_7_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_130[] = {
+	 { "entries_7_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_131[] = {
+	 { "entries_7_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_132[] = {
+	 { "entries_7_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_133[] = {
+	 { "entries_7_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_134[] = {
+	 { "entries_7_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_135[] = {
+	 { "entries_7_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_136[] = {
+	 { "entries_7_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_137[] = {
+	 { "entries_7_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_138[] = {
+	 { "entries_7_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_139[] = {
+	 { "entries_7_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_140[] = {
+	 { "entries_7_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_141[] = {
+	 { "entries_7_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_142[] = {
+	 { "entries_7_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_143[] = {
+	 { "entries_7_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_144[] = {
+	 { "entries_7_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_1[] = {
+	 { "reserved_2", 0, 7, &umr_bitfield_default },
+	 { "reserved_1", 8, 15, &umr_bitfield_default },
+	 { "reserved_0", 16, 23, &umr_bitfield_default },
+	 { "last", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_2[] = {
+	 { "address_0_s1", 0, 15, &umr_bitfield_default },
+	 { "address_0_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_3[] = {
+	 { "address_1_s1", 0, 15, &umr_bitfield_default },
+	 { "address_1_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_4[] = {
+	 { "address_2_s1", 0, 15, &umr_bitfield_default },
+	 { "address_2_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_5[] = {
+	 { "address_3_s1", 0, 15, &umr_bitfield_default },
+	 { "address_3_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_6[] = {
+	 { "address_4_s1", 0, 15, &umr_bitfield_default },
+	 { "address_4_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_7[] = {
+	 { "address_5_s1", 0, 15, &umr_bitfield_default },
+	 { "address_5_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_8[] = {
+	 { "address_6_s1", 0, 15, &umr_bitfield_default },
+	 { "address_6_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_9[] = {
+	 { "address_7_s1", 0, 15, &umr_bitfield_default },
+	 { "address_7_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_10[] = {
+	 { "address_8_s1", 0, 15, &umr_bitfield_default },
+	 { "address_8_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_11[] = {
+	 { "address_9_s1", 0, 15, &umr_bitfield_default },
+	 { "address_9_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_12[] = {
+	 { "address_10_s1", 0, 15, &umr_bitfield_default },
+	 { "address_10_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_13[] = {
+	 { "address_11_s1", 0, 15, &umr_bitfield_default },
+	 { "address_11_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_14[] = {
+	 { "address_12_s1", 0, 15, &umr_bitfield_default },
+	 { "address_12_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_15[] = {
+	 { "address_13_s1", 0, 15, &umr_bitfield_default },
+	 { "address_13_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_16[] = {
+	 { "address_14_s1", 0, 15, &umr_bitfield_default },
+	 { "address_14_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_17[] = {
+	 { "address_15_s1", 0, 15, &umr_bitfield_default },
+	 { "address_15_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_18[] = {
+	 { "data_0_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_19[] = {
+	 { "data_0_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_20[] = {
+	 { "data_0_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_21[] = {
+	 { "data_0_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_22[] = {
+	 { "data_0_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_23[] = {
+	 { "data_0_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_24[] = {
+	 { "data_0_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_25[] = {
+	 { "data_0_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_26[] = {
+	 { "data_0_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_27[] = {
+	 { "data_0_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_28[] = {
+	 { "data_0_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_29[] = {
+	 { "data_0_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_30[] = {
+	 { "data_0_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_31[] = {
+	 { "data_0_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_32[] = {
+	 { "data_0_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_33[] = {
+	 { "data_0_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_34[] = {
+	 { "data_1_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_35[] = {
+	 { "data_1_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_36[] = {
+	 { "data_1_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_37[] = {
+	 { "data_1_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_38[] = {
+	 { "data_1_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_39[] = {
+	 { "data_1_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_40[] = {
+	 { "data_1_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_41[] = {
+	 { "data_1_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_42[] = {
+	 { "data_1_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_43[] = {
+	 { "data_1_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_44[] = {
+	 { "data_1_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_45[] = {
+	 { "data_1_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_46[] = {
+	 { "data_1_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_47[] = {
+	 { "data_1_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_48[] = {
+	 { "data_1_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_49[] = {
+	 { "data_1_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_50[] = {
+	 { "data_2_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_51[] = {
+	 { "data_2_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_52[] = {
+	 { "data_2_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_53[] = {
+	 { "data_2_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_54[] = {
+	 { "data_2_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_55[] = {
+	 { "data_2_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_56[] = {
+	 { "data_2_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_57[] = {
+	 { "data_2_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_58[] = {
+	 { "data_2_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_59[] = {
+	 { "data_2_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_60[] = {
+	 { "data_2_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_61[] = {
+	 { "data_2_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_62[] = {
+	 { "data_2_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_63[] = {
+	 { "data_2_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_64[] = {
+	 { "data_2_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_65[] = {
+	 { "data_2_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_66[] = {
+	 { "data_3_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_67[] = {
+	 { "data_3_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_68[] = {
+	 { "data_3_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_69[] = {
+	 { "data_3_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_70[] = {
+	 { "data_3_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_71[] = {
+	 { "data_3_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_72[] = {
+	 { "data_3_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_73[] = {
+	 { "data_3_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_74[] = {
+	 { "data_3_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_75[] = {
+	 { "data_3_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_76[] = {
+	 { "data_3_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_77[] = {
+	 { "data_3_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_78[] = {
+	 { "data_3_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_79[] = {
+	 { "data_3_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_80[] = {
+	 { "data_3_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_81[] = {
+	 { "data_3_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_82[] = {
+	 { "data_4_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_83[] = {
+	 { "data_4_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_84[] = {
+	 { "data_4_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_85[] = {
+	 { "data_4_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_86[] = {
+	 { "data_4_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_87[] = {
+	 { "data_4_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_88[] = {
+	 { "data_4_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_89[] = {
+	 { "data_4_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_90[] = {
+	 { "data_4_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_91[] = {
+	 { "data_4_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_92[] = {
+	 { "data_4_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_93[] = {
+	 { "data_4_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_94[] = {
+	 { "data_4_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_95[] = {
+	 { "data_4_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_96[] = {
+	 { "data_4_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_97[] = {
+	 { "data_4_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_98[] = {
+	 { "data_5_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_99[] = {
+	 { "data_5_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_100[] = {
+	 { "data_5_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_101[] = {
+	 { "data_5_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_102[] = {
+	 { "data_5_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_103[] = {
+	 { "data_5_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_104[] = {
+	 { "data_5_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_105[] = {
+	 { "data_5_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_106[] = {
+	 { "data_5_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_107[] = {
+	 { "data_5_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_108[] = {
+	 { "data_5_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_109[] = {
+	 { "data_5_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_110[] = {
+	 { "data_5_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_111[] = {
+	 { "data_5_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_112[] = {
+	 { "data_5_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_113[] = {
+	 { "data_5_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_1[] = {
+	 { "TempMin", 0, 15, &umr_bitfield_default },
+	 { "FdoMode", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_2[] = {
+	 { "TempMax", 0, 15, &umr_bitfield_default },
+	 { "TempMed", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_3[] = {
+	 { "Slope2", 0, 15, &umr_bitfield_default },
+	 { "Slope1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_4[] = {
+	 { "HystUp", 0, 15, &umr_bitfield_default },
+	 { "FdoMin", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_5[] = {
+	 { "HystSlope", 0, 15, &umr_bitfield_default },
+	 { "HystDown", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_6[] = {
+	 { "TempCurr", 0, 15, &umr_bitfield_default },
+	 { "TempRespLim", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_7[] = {
+	 { "PwmCurr", 0, 15, &umr_bitfield_default },
+	 { "SlopeCurr", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_8[] = {
+	 { "RefreshPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_9[] = {
+	 { "Padding", 0, 7, &umr_bitfield_default },
+	 { "TempSrc", 8, 15, &umr_bitfield_default },
+	 { "FdoMax", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_1[] = {
+	 { "RefClockFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_2[] = {
+	 { "PmTimerPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_3[] = {
+	 { "FeatureEnables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_4[] = {
+	 { "PreVBlankGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_5[] = {
+	 { "VBlankTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_6[] = {
+	 { "TrainTimeGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_7[] = {
+	 { "MvddSwitchTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_8[] = {
+	 { "LongestAcpiTrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_9[] = {
+	 { "AcpiDelay", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_10[] = {
+	 { "G5TrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_11[] = {
+	 { "DelayMpllPwron", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_12[] = {
+	 { "VoltageChangeTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_13[] = {
+	 { "HandshakeDisables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_14[] = {
+	 { "DisplayPhy4Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy3Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy2Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy1Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_15[] = {
+	 { "DisplayPhy8Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy7Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy6Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy5Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_16[] = {
+	 { "AverageGraphicsActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_17[] = {
+	 { "AverageMemoryActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_18[] = {
+	 { "AverageGioActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_19[] = {
+	 { "PCIeDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "LClkDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "MClkDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "SClkDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_20[] = {
+	 { "VCEDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "ACPDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "SAMUDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "UVDDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_21[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_22[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_23[] = {
+	 { "Reserved_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_24[] = {
+	 { "Reserved_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_25[] = {
+	 { "Reserved_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_26[] = {
+	 { "Reserved_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_27[] = {
+	 { "Reserved_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_28[] = {
+	 { "Reserved_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_29[] = {
+	 { "Reserved_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_30[] = {
+	 { "Reserved_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_1[] = {
+	 { "BapmVddCVidHiSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_2[] = {
+	 { "BapmVddCVidHiSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_3[] = {
+	 { "BapmVddCVidLoSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_4[] = {
+	 { "BapmVddCVidLoSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_5[] = {
+	 { "VddCVid_3", 0, 7, &umr_bitfield_default },
+	 { "VddCVid_2", 8, 15, &umr_bitfield_default },
+	 { "VddCVid_1", 16, 23, &umr_bitfield_default },
+	 { "VddCVid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_6[] = {
+	 { "VddCVid_7", 0, 7, &umr_bitfield_default },
+	 { "VddCVid_6", 8, 15, &umr_bitfield_default },
+	 { "VddCVid_5", 16, 23, &umr_bitfield_default },
+	 { "VddCVid_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_7[] = {
+	 { "SviLoadLineOffsetVddC", 0, 7, &umr_bitfield_default },
+	 { "SviLoadLineTrimVddC", 8, 15, &umr_bitfield_default },
+	 { "SviLoadLineVddC", 16, 23, &umr_bitfield_default },
+	 { "SviLoadLineEn", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_8[] = {
+	 { "TDC_MAWt", 0, 7, &umr_bitfield_default },
+	 { "TDC_VDDC_ThrottleReleaseLimitPerc", 8, 15, &umr_bitfield_default },
+	 { "TDC_VDDC_PkgLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_9[] = {
+	 { "Reserved", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureMax", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureMin", 16, 23, &umr_bitfield_default },
+	 { "TdcWaterfallCtl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_10[] = {
+	 { "LPMLTemperatureScaler_3", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_2", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_1", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_11[] = {
+	 { "LPMLTemperatureScaler_7", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_6", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_5", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_12[] = {
+	 { "LPMLTemperatureScaler_11", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_10", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_9", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_13[] = {
+	 { "LPMLTemperatureScaler_15", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_14", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_13", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_14[] = {
+	 { "GnbLPML_3", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_2", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_1", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_15[] = {
+	 { "GnbLPML_7", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_6", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_5", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_16[] = {
+	 { "GnbLPML_11", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_10", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_9", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_17[] = {
+	 { "GnbLPML_15", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_14", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_13", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_18[] = {
+	 { "Reserved1_1", 0, 7, &umr_bitfield_default },
+	 { "Reserved1_0", 8, 15, &umr_bitfield_default },
+	 { "GnbLPMLMinVid", 16, 23, &umr_bitfield_default },
+	 { "GnbLPMLMaxVid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_19[] = {
+	 { "BapmVddCBaseLeakageLoSidd", 0, 15, &umr_bitfield_default },
+	 { "BapmVddCBaseLeakageHiSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_16[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_17[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_18[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_19[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_20[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_21[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_22[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_24[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_25[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_26[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_27[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_28[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_29[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_30[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_31[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_32[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_33[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_34[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_35[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_36[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_37[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_38[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_39[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_40[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_41[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_42[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_43[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_44[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_46[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_47[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_48[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_49[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_50[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_51[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_52[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_53[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_54[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_55[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_56[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_57[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_58[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_59[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_60[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_61[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_62[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_63[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_64[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_65[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_66[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_67[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_68[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_69[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_70[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_71[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_72[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_73[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_74[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_75[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_76[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_77[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_78[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_79[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_80[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_81[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_82[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_83[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_84[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_85[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_86[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_87[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_88[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_89[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_90[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_91[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_92[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_93[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_94[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_95[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_96[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_97[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_98[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_99[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_100[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_101[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_102[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_103[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_104[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_105[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_106[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_107[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_108[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_109[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_110[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_111[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_112[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_113[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_114[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_115[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_116[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_117[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_118[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_119[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_120[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_121[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_122[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_123[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_124[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_125[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_126[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_127[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_RESET_CNTL[] = {
+	 { "rst_reg", 0, 0, &umr_bitfield_default },
+	 { "srbm_soft_rst_override", 1, 1, &umr_bitfield_default },
+	 { "RegReset", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_0[] = {
+	 { "ck_disable", 0, 0, &umr_bitfield_default },
+	 { "auto_cg_en", 1, 1, &umr_bitfield_default },
+	 { "auto_cg_timeout", 8, 23, &umr_bitfield_default },
+	 { "cken", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_1[] = {
+	 { "auto_ck_disable", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_2[] = {
+	 { "wake_on_irq", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_MSG_ARG_0[] = {
+	 { "smc_msg_arg", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_PC_C[] = {
+	 { "smc_pc_c", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SCRATCH9[] = {
+	 { "SCRATCH_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_ACCESS_CNTL[] = {
+	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_1", 1, 1, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_2", 2, 2, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_3", 3, 3, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_4", 4, 4, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_5", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_6", 6, 6, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_7", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_11[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_0[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_0[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_1[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_1[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_2[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_2[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_3[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_3[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_4[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_4[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_5[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_5[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_6[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_6[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_7[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_7[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_0[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_1[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_2[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_3[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_4[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_5[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_6[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_7[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_8[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_8[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_9[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_9[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_10[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_10[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_11[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_11[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_8[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_9[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_10[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_UC_EVENTS[] = {
+	 { "RCU_TST_jpc_rep_req", 0, 0, &umr_bitfield_default },
+	 { "TST_RCU_jpc_rep_done", 1, 1, &umr_bitfield_default },
+	 { "drv_rst_mode", 2, 2, &umr_bitfield_default },
+	 { "SMU_DC_efuse_status_invalid", 3, 3, &umr_bitfield_default },
+	 { "TP_Tester", 6, 6, &umr_bitfield_default },
+	 { "boot_seq_done", 7, 7, &umr_bitfield_default },
+	 { "sclk_deep_sleep_exit", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_ACTIVE", 9, 9, &umr_bitfield_default },
+	 { "BREAK_PT2_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "FCH_HALT", 11, 11, &umr_bitfield_default },
+	 { "RCU_GIO_fch_lockdown", 13, 13, &umr_bitfield_default },
+	 { "INTERRUPTS_ENABLED", 16, 16, &umr_bitfield_default },
+	 { "RCU_DtmCnt0_Done", 17, 17, &umr_bitfield_default },
+	 { "RCU_DtmCnt1_Done", 18, 18, &umr_bitfield_default },
+	 { "RCU_DtmCnt2_Done", 19, 19, &umr_bitfield_default },
+	 { "irq31_sel", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_MISC_CTRL[] = {
+	 { "REG_DRV_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "REG_RCU_MEMREP_DIS", 3, 3, &umr_bitfield_default },
+	 { "REG_CC_FUSE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "REG_SAMU_FUSE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "REG_CC_SRBM_RD_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_DONE", 16, 16, &umr_bitfield_default },
+	 { "BREAK_PT2_DONE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_START", 22, 22, &umr_bitfield_default },
+	 { "RST_PULSE_WIDTH", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_RCU_FUSES[] = {
+	 { "GPU_DIS", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "EFUSE_RD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "CG_RST_GLB_REQ_DIS", 5, 5, &umr_bitfield_default },
+	 { "DRV_RST_MODE", 6, 6, &umr_bitfield_default },
+	 { "ROM_DIS", 7, 7, &umr_bitfield_default },
+	 { "JPC_REP_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT1", 9, 9, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT2", 10, 10, &umr_bitfield_default },
+	 { "PHY_FUSE_VALID", 14, 14, &umr_bitfield_default },
+	 { "SMU_IOC_MST_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "FCH_LOCKOUT_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "FCH_XFIRE_FILTER_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "XFIRE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "SAMU_FUSE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "BIF_RST_POLLING_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "MEM_HARDREP_EN", 22, 22, &umr_bitfield_default },
+	 { "PCIE_INIT_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "DSMU_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "RCU_SPARE", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_MISC_FUSES[] = {
+	 { "IOMMU_V2_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "MinSClkDid", 2, 8, &umr_bitfield_default },
+	 { "MISC_SPARE", 9, 10, &umr_bitfield_default },
+	 { "PostResetGnbClkDid", 11, 17, &umr_bitfield_default },
+	 { "L2IMU_tn2_dtc_half", 18, 18, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_half", 19, 19, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_half", 20, 20, &umr_bitfield_default },
+	 { "L2IMU_tn2_pdc_half", 21, 21, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_dis", 22, 22, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_dis", 23, 23, &umr_bitfield_default },
+	 { "VCE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "IOC_IOMMU_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "GNB_SPARE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SCLK_VID_FUSES[] = {
+	 { "SClkVid0", 0, 7, &umr_bitfield_default },
+	 { "SClkVid1", 8, 15, &umr_bitfield_default },
+	 { "SClkVid2", 16, 23, &umr_bitfield_default },
+	 { "SClkVid3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOCCFG_FUSES[] = {
+	 { "NB_REV_ID", 1, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOC_FUSES[] = {
+	 { "IOC_FUSES", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_TST_EFUSE1_MISC[] = {
+	 { "RF_RM_6_2", 1, 5, &umr_bitfield_default },
+	 { "RME", 6, 6, &umr_bitfield_default },
+	 { "MBIST_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "HARD_REPAIR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SOFT_REPAIR_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "GPU_DIS", 10, 10, &umr_bitfield_default },
+	 { "SMS_PWRDWN_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "CRBBMP1500_DISA", 12, 12, &umr_bitfield_default },
+	 { "CRBBMP1500_DISB", 13, 13, &umr_bitfield_default },
+	 { "RM_RF8", 14, 14, &umr_bitfield_default },
+	 { "DFT_SPARE1", 22, 22, &umr_bitfield_default },
+	 { "DFT_SPARE2", 23, 23, &umr_bitfield_default },
+	 { "DFT_SPARE3", 24, 24, &umr_bitfield_default },
+	 { "VCE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "DCE_SCAN_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_TST_ID_STRAPS[] = {
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_FCTRL_FUSES[] = {
+	 { "EXT_EFUSE_MACRO_PRESENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_EFUSE_0[] = {
+	 { "EFUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGENERAL_PWRMGT[] = {
+	 { "GLOBAL_PWRMGT_EN", 0, 0, &umr_bitfield_default },
+	 { "STATIC_PM_EN", 1, 1, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_DIS", 2, 2, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_TYPE", 3, 3, &umr_bitfield_default },
+	 { "SW_SMIO_INDEX", 6, 6, &umr_bitfield_default },
+	 { "LOW_VOLT_D2_ACPI", 8, 8, &umr_bitfield_default },
+	 { "LOW_VOLT_D3_ACPI", 9, 9, &umr_bitfield_default },
+	 { "VOLT_PWRMGT_EN", 10, 10, &umr_bitfield_default },
+	 { "SPARE11", 11, 11, &umr_bitfield_default },
+	 { "GPU_COUNTER_ACPI", 14, 14, &umr_bitfield_default },
+	 { "GPU_COUNTER_CLK", 15, 15, &umr_bitfield_default },
+	 { "GPU_COUNTER_OFF", 16, 16, &umr_bitfield_default },
+	 { "GPU_COUNTER_INTF_OFF", 17, 17, &umr_bitfield_default },
+	 { "SPARE18", 18, 18, &umr_bitfield_default },
+	 { "ACPI_D3_VID", 19, 20, &umr_bitfield_default },
+	 { "DYN_SPREAD_SPECTRUM_EN", 23, 23, &umr_bitfield_default },
+	 { "SPARE27", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCNB_PWRMGT_CNTL[] = {
+	 { "GNB_SLOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "GNB_SLOW", 2, 2, &umr_bitfield_default },
+	 { "FORCE_NB_PS1", 3, 3, &umr_bitfield_default },
+	 { "DPM_ENABLED", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_PWRMGT_CNTL[] = {
+	 { "SCLK_PWRMGT_OFF", 0, 0, &umr_bitfield_default },
+	 { "SCLK_LOW_D1", 1, 1, &umr_bitfield_default },
+	 { "DYN_PWR_DOWN_EN", 2, 2, &umr_bitfield_default },
+	 { "RESET_BUSY_CNT", 4, 4, &umr_bitfield_default },
+	 { "RESET_SCLK_CNT", 5, 5, &umr_bitfield_default },
+	 { "RESERVED_0", 6, 6, &umr_bitfield_default },
+	 { "DYN_GFX_CLK_OFF_EN", 7, 7, &umr_bitfield_default },
+	 { "GFX_CLK_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "GFX_CLK_REQUEST_OFF", 9, 9, &umr_bitfield_default },
+	 { "GFX_CLK_FORCE_OFF", 10, 10, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D1", 11, 11, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D2", 12, 12, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D3", 13, 13, &umr_bitfield_default },
+	 { "DYN_LIGHT_SLEEP_EN", 14, 14, &umr_bitfield_default },
+	 { "AUTO_SCLK_PULSE_SKIP", 15, 15, &umr_bitfield_default },
+	 { "LIGHT_SLEEP_COUNTER", 16, 20, &umr_bitfield_default },
+	 { "DYNAMIC_PM_EN", 21, 21, &umr_bitfield_default },
+	 { "DPM_DYN_PWR_DOWN_CNTL", 22, 22, &umr_bitfield_default },
+	 { "DPM_DYN_PWR_DOWN_EN", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_3", 24, 24, &umr_bitfield_default },
+	 { "VOLTAGE_UPDATE_EN", 25, 25, &umr_bitfield_default },
+	 { "FORCE_PM0_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "FORCE_PM1_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "GFX_VOLTAGE_CHANGE_EN", 30, 30, &umr_bitfield_default },
+	 { "GFX_VOLTAGE_CHANGE_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX[] = {
+	 { "TARGET_STATE", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_STATE", 4, 7, &umr_bitfield_default },
+	 { "CURR_MCLK_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MCLK_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_SCLK_INDEX", 16, 20, &umr_bitfield_default },
+	 { "TARG_SCLK_INDEX", 21, 25, &umr_bitfield_default },
+	 { "CURR_LCLK_INDEX", 26, 28, &umr_bitfield_default },
+	 { "TARG_LCLK_INDEX", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 3, &umr_bitfield_default },
+	 { "TST_REF_SEL", 4, 7, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 8, 14, &umr_bitfield_default },
+	 { "TST_RESET", 15, 15, &umr_bitfield_default },
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_STATIC_SCREEN_PARAMETER[] = {
+	 { "STATIC_SCREEN_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL[] = {
+	 { "DISP_GAP", 0, 1, &umr_bitfield_default },
+	 { "VBI_TIMER_COUNT", 4, 17, &umr_bitfield_default },
+	 { "VBI_TIMER_UNIT", 20, 22, &umr_bitfield_default },
+	 { "DISP_GAP_MCHG", 24, 25, &umr_bitfield_default },
+	 { "VBI_TIMER_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACPI_CNTL[] = {
+	 { "SCLK_ACPI_DIV", 0, 6, &umr_bitfield_default },
+	 { "SCLK_CHANGE_SKIP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 16, 16, &umr_bitfield_default },
+	 { "SELF_REFRESH_MASK", 17, 17, &umr_bitfield_default },
+	 { "ALLOW_NBPSTATE_MASK", 18, 18, &umr_bitfield_default },
+	 { "BIF_BUSY_MASK", 19, 19, &umr_bitfield_default },
+	 { "UVD_BUSY_MASK", 20, 20, &umr_bitfield_default },
+	 { "MC0SRBM_BUSY_MASK", 21, 21, &umr_bitfield_default },
+	 { "MC1SRBM_BUSY_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_ALLOW_MASK", 23, 23, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 24, 24, &umr_bitfield_default },
+	 { "SELF_REFRESH_NLC_MASK", 25, 25, &umr_bitfield_default },
+	 { "FAST_EXIT_REQ_NBPSTATE", 26, 26, &umr_bitfield_default },
+	 { "DEEP_SLEEP_ENTRY_MODE", 27, 27, &umr_bitfield_default },
+	 { "MBUS2_ACTIVE_MASK", 28, 28, &umr_bitfield_default },
+	 { "VCE_BUSY_MASK", 29, 29, &umr_bitfield_default },
+	 { "AZ_BUSY_MASK", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RLC_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "HDP_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "ROM_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "PDMA_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "IDCT_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "SDMA_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_AZ_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK", 9, 9, &umr_bitfield_default },
+	 { "UVD_CG_MC_STAT_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "VCE_CG_MC_STAT_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "SAM_CG_MC_STAT_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "SAM_CG_STATUS_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 14, 14, &umr_bitfield_default },
+	 { "SHALLOW_DIV_ID", 21, 23, &umr_bitfield_default },
+	 { "INOUT_CUSHION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_MISC_CNTL[] = {
+	 { "DPM_DS_DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "DPM_SS_DIV_ID", 3, 5, &umr_bitfield_default },
+	 { "OCP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OCP_DS_DIV_ID", 17, 19, &umr_bitfield_default },
+	 { "OCP_SS_DIV_ID", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL3[] = {
+	 { "GRBM_0_SMU_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRBM_1_SMU_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "GRBM_2_SMU_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "GRBM_3_SMU_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "GRBM_4_SMU_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "GRBM_5_SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "GRBM_6_SMU_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "GRBM_7_SMU_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "GRBM_8_SMU_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "GRBM_9_SMU_BUSY_MASK", 9, 9, &umr_bitfield_default },
+	 { "GRBM_10_SMU_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "GRBM_11_SMU_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "GRBM_12_SMU_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "GRBM_13_SMU_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "GRBM_14_SMU_BUSY_MASK", 14, 14, &umr_bitfield_default },
+	 { "GRBM_15_SMU_BUSY_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_1[] = {
+	 { "CURR_VDDCI_INDEX", 0, 3, &umr_bitfield_default },
+	 { "TARG_VDDCI_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_MVDD_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MVDD_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_VDDC_INDEX", 16, 19, &umr_bitfield_default },
+	 { "TARG_VDDC_INDEX", 20, 23, &umr_bitfield_default },
+	 { "CURR_PCIE_INDEX", 24, 27, &umr_bitfield_default },
+	 { "TARG_PCIE_INDEX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ULV_PARAMETER[] = {
+	 { "ULV_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "ULV_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_0[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_1[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_2[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_3[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_4[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_5[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_6[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
+	 { "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_MIN_DIV[] = {
+	 { "FRACV", 0, 11, &umr_bitfield_default },
+	 { "INTV", 12, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "L1IMU_SMU_IDLE_MASK", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_BIT3", 3, 3, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 4, 4, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE1_MASK", 6, 6, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE2_MASK", 7, 7, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE3_MASK", 8, 8, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE4_MASK", 9, 9, &umr_bitfield_default },
+	 { "L1IMUGPP_IDLE_MASK", 10, 10, &umr_bitfield_default },
+	 { "L1IMUGPPSB_IDLE_MASK", 11, 11, &umr_bitfield_default },
+	 { "L1IMUBIF_IDLE_MASK", 12, 12, &umr_bitfield_default },
+	 { "L1IMUINTGEN_IDLE_MASK", 13, 13, &umr_bitfield_default },
+	 { "L2IMU_IDLE_MASK", 14, 14, &umr_bitfield_default },
+	 { "ORB_IDLE_MASK", 15, 15, &umr_bitfield_default },
+	 { "ON_INB_WAKE_MASK", 16, 16, &umr_bitfield_default },
+	 { "ON_INB_WAKE_ACK_MASK", 17, 17, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_MASK", 18, 18, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_ACK_MASK", 19, 19, &umr_bitfield_default },
+	 { "DMAACTIVE_MASK", 20, 20, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_CTRL[] = {
+	 { "DPM_EVENT_SRC", 0, 2, &umr_bitfield_default },
+	 { "THERM_INC_CLK", 3, 3, &umr_bitfield_default },
+	 { "SPARE", 4, 13, &umr_bitfield_default },
+	 { "DIG_THERM_DPM", 14, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 24, &umr_bitfield_default },
+	 { "CTF_PAD_POLARITY", 25, 25, &umr_bitfield_default },
+	 { "CTF_PAD_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_STATUS[] = {
+	 { "SPARE", 0, 8, &umr_bitfield_default },
+	 { "FDO_PWM_DUTY", 9, 16, &umr_bitfield_default },
+	 { "THERM_ALERT", 17, 17, &umr_bitfield_default },
+	 { "GEN_STATUS", 18, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT[] = {
+	 { "DIG_THERM_CTF", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTH", 8, 15, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 16, 23, &umr_bitfield_default },
+	 { "THERM_INT_MASK", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_CTRL[] = {
+	 { "TS_FILTER", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 7, &umr_bitfield_default },
+	 { "THERMAL_RANGE_RST", 9, 9, &umr_bitfield_default },
+	 { "TEMP_SEL", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_STATUS[] = {
+	 { "ASIC_MAX_TEMP", 0, 8, &umr_bitfield_default },
+	 { "CTF_TEMP", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL0[] = {
+	 { "FDO_STATIC_DUTY", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_DUTY", 8, 15, &umr_bitfield_default },
+	 { "FDO_PWM_MANUAL", 16, 16, &umr_bitfield_default },
+	 { "FDO_PWM_HYSTER", 17, 22, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP_EN", 23, 23, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL1[] = {
+	 { "FMAX_DUTY100", 0, 7, &umr_bitfield_default },
+	 { "FMIN_DUTY", 8, 15, &umr_bitfield_default },
+	 { "M", 16, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 29, &umr_bitfield_default },
+	 { "FDO_PWRDNB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL2[] = {
+	 { "TMIN", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_TIME", 8, 10, &umr_bitfield_default },
+	 { "FDO_PWM_MODE", 11, 13, &umr_bitfield_default },
+	 { "TMIN_HYSTER", 14, 16, &umr_bitfield_default },
+	 { "TMAX", 17, 24, &umr_bitfield_default },
+	 { "TACH_PWM_RESP_RATE", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_CTRL[] = {
+	 { "EDGE_PER_REV", 0, 2, &umr_bitfield_default },
+	 { "TARGET_PERIOD", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_STATUS[] = {
+	 { "TACH_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_THM_STRAPS0[] = {
+	 { "TMON0_BGADJ", 1, 8, &umr_bitfield_default },
+	 { "TMON1_BGADJ", 9, 16, &umr_bitfield_default },
+	 { "TMON_CMON_FUSE_SEL", 17, 17, &umr_bitfield_default },
+	 { "NUM_ACQ", 18, 20, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 21, 23, &umr_bitfield_default },
+	 { "TMON_CONFIG_SOURCE", 24, 24, &umr_bitfield_default },
+	 { "CTF_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "TMON0_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "TMON1_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "TMON2_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "TMON3_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "UNUSED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_CNTL[] = {
+	 { "SX0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SX0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "SX0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "SX0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_OVR_SEL[] = {
+	 { "SX0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_OVR_VAL[] = {
+	 { "SX0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
+	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
+	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
+	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
+	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC1_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC1_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
+	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
+	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
+	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC2_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC2_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
+	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
+	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
+	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC3_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC3_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
+	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
+	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_CNTL[] = {
+	 { "CPL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CPL_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "CPL_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "CPL_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_SEL[] = {
+	 { "CPL_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_VAL[] = {
+	 { "CPL_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_CNTL[] = {
+	 { "DCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_STATUS[] = {
+	 { "DCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_CNTL[] = {
+	 { "VCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_STATUS[] = {
+	 { "VCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_CNTL[] = {
+	 { "ECLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_STATUS[] = {
+	 { "ECLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACLK_CNTL[] = {
+	 { "ACLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_DFS_BYPASS_CNTL[] = {
+	 { "BYPASSECLK", 0, 0, &umr_bitfield_default },
+	 { "BYPASSLCLK", 1, 1, &umr_bitfield_default },
+	 { "BYPASSEVCLK", 2, 2, &umr_bitfield_default },
+	 { "BYPASSDCLK", 3, 3, &umr_bitfield_default },
+	 { "BYPASSVCLK", 4, 4, &umr_bitfield_default },
+	 { "BYPASSDISPCLK", 5, 5, &umr_bitfield_default },
+	 { "BYPASSDPREFCLK", 6, 6, &umr_bitfield_default },
+	 { "BYPASSACLK", 7, 7, &umr_bitfield_default },
+	 { "BYPASSADIVCLK", 8, 8, &umr_bitfield_default },
+	 { "BYPASSPSPCLK", 9, 9, &umr_bitfield_default },
+	 { "BYPASSSAMCLK", 10, 10, &umr_bitfield_default },
+	 { "BYPASSSCLK", 11, 11, &umr_bitfield_default },
+	 { "USE_SPLL_BYPASS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL[] = {
+	 { "SPLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "SPLL_PWRON", 1, 1, &umr_bitfield_default },
+	 { "SPLL_DIVEN", 2, 2, &umr_bitfield_default },
+	 { "SPLL_BYPASS_EN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_BYPASS_THRU_DFS", 4, 4, &umr_bitfield_default },
+	 { "SPLL_REF_DIV", 5, 10, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_EN", 12, 12, &umr_bitfield_default },
+	 { "SPLL_PDIV_A", 20, 26, &umr_bitfield_default },
+	 { "SPLL_DIVA_ACK", 27, 27, &umr_bitfield_default },
+	 { "SPLL_OTEST_LOCK_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_2[] = {
+	 { "SCLK_MUX_SEL", 0, 8, &umr_bitfield_default },
+	 { "SPLL_CTLREQ", 11, 11, &umr_bitfield_default },
+	 { "SPLL_BYPASS_CHG", 22, 22, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_CHG", 23, 23, &umr_bitfield_default },
+	 { "SPLL_RESET_CHG", 24, 24, &umr_bitfield_default },
+	 { "SPLL_BABY_STEP_CHG", 25, 25, &umr_bitfield_default },
+	 { "SCLK_MUX_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "SPLL_UNLOCK_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "SPLL_CLKF_UPDATE", 28, 28, &umr_bitfield_default },
+	 { "SPLL_TEST_UNLOCK_CLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_3[] = {
+	 { "SPLL_FB_DIV", 0, 25, &umr_bitfield_default },
+	 { "SPLL_DITHEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_4[] = {
+	 { "SPLL_SCLK_TEST_SEL", 0, 3, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT_SEL", 5, 6, &umr_bitfield_default },
+	 { "SPLL_SCLK_EN", 7, 8, &umr_bitfield_default },
+	 { "SPLL_SPARE", 9, 18, &umr_bitfield_default },
+	 { "TEST_FRAC_BYPASS", 21, 21, &umr_bitfield_default },
+	 { "SPLL_ILOCK", 23, 23, &umr_bitfield_default },
+	 { "SPLL_FBCLK_SEL", 24, 24, &umr_bitfield_default },
+	 { "SPLL_VCTRLADC_EN", 25, 25, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT", 26, 27, &umr_bitfield_default },
+	 { "SPLL_SPARE_EXT", 28, 30, &umr_bitfield_default },
+	 { "SPLL_VTOI_BIAS_CNTL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_5[] = {
+	 { "FBDIV_SSC_BYPASS", 0, 0, &umr_bitfield_default },
+	 { "RISEFBVCO_EN", 1, 1, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 2, 3, &umr_bitfield_default },
+	 { "RESET_TIMER", 4, 5, &umr_bitfield_default },
+	 { "FAST_LOCK_CNTRL", 6, 7, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 8, 8, &umr_bitfield_default },
+	 { "RESET_ANTI_MUX", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_6[] = {
+	 { "SCLKMUX0_CLKOFF_CNT", 0, 7, &umr_bitfield_default },
+	 { "SCLKMUX1_CLKOFF_CNT", 8, 15, &umr_bitfield_default },
+	 { "SPLL_VCTL_EN", 16, 16, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_IN", 17, 20, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_OUT", 21, 24, &umr_bitfield_default },
+	 { "SPLL_LF_CNTR", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_7[] = {
+	 { "SPLL_BW_CNTRL", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPLL_CNTL_MODE[] = {
+	 { "SPLL_SW_DIR_CONTROL", 0, 0, &umr_bitfield_default },
+	 { "SPLL_LEGACY_PDIV", 1, 1, &umr_bitfield_default },
+	 { "SPLL_TEST", 2, 2, &umr_bitfield_default },
+	 { "SPLL_FASTEN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_ENSAT", 4, 4, &umr_bitfield_default },
+	 { "SPLL_TEST_CLK_EXT_DIV", 10, 11, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_DLY_CNT", 12, 19, &umr_bitfield_default },
+	 { "SPLL_RESET_EN", 28, 28, &umr_bitfield_default },
+	 { "SPLL_VCO_MODE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM[] = {
+	 { "SSEN", 0, 0, &umr_bitfield_default },
+	 { "CLKS", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM_2[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMPLL_BYPASSCLK_SEL[] = {
+	 { "MPLL_CLKOUT_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL[] = {
+	 { "XTALIN_DIVIDE", 1, 1, &umr_bitfield_default },
+	 { "BCLK_AS_XCLK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_2[] = {
+	 { "ENABLE_XCLK", 0, 0, &umr_bitfield_default },
+	 { "FORCE_BIF_REFCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "MUX_TCLK_TO_XCLK", 8, 8, &umr_bitfield_default },
+	 { "XO_IN_OSCIN_EN", 14, 14, &umr_bitfield_default },
+	 { "XO_IN_ICORE_CLK_OE", 15, 15, &umr_bitfield_default },
+	 { "XO_IN_CML_RXEN", 16, 16, &umr_bitfield_default },
+	 { "XO_IN_BIDIR_CML_OE", 17, 17, &umr_bitfield_default },
+	 { "XO_IN2_OSCIN_EN", 18, 18, &umr_bitfield_default },
+	 { "XO_IN2_ICORE_CLK_OE", 19, 19, &umr_bitfield_default },
+	 { "XO_IN2_CML_RXEN", 20, 20, &umr_bitfield_default },
+	 { "XO_IN2_BIDIR_CML_OE", 21, 21, &umr_bitfield_default },
+	 { "CML_CTRL", 22, 23, &umr_bitfield_default },
+	 { "CLK_SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_CLK_CNTL[] = {
+	 { "CMON_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "CTF_CLK_SHUTOFF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_CLK_CTRL[] = {
+	 { "DEEP_SLEEP_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "ZCLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "DFT_SMS_PG_CLK_SEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 4, &umr_bitfield_default },
+	 { "TST_REF_SEL", 5, 9, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 10, 16, &umr_bitfield_default },
+	 { "TST_RESET", 17, 17, &umr_bitfield_default },
+	 { "TST_CLK_SEL_MODE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL_2[] = {
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_ADFS_CLK_BYPASS_CNTL1[] = {
+	 { "ECLK_BYPASS_CNTL", 0, 2, &umr_bitfield_default },
+	 { "SCLK_BYPASS_CNTL", 3, 5, &umr_bitfield_default },
+	 { "LCLK_BYPASS_CNTL", 6, 8, &umr_bitfield_default },
+	 { "DCLK_BYPASS_CNTL", 9, 11, &umr_bitfield_default },
+	 { "VCLK_BYPASS_CNTL", 12, 14, &umr_bitfield_default },
+	 { "DISPCLK_BYPASS_CNTL", 15, 17, &umr_bitfield_default },
+	 { "DRREFCLK_BYPASS_CNTL", 18, 20, &umr_bitfield_default },
+	 { "ACLK_BYPASS_CNTL", 21, 23, &umr_bitfield_default },
+	 { "SAMCLK_BYPASS_CNTL", 24, 26, &umr_bitfield_default },
+	 { "ACLK_DIV_BYPASS_CNTL", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_DC[] = {
+	 { "OSC_EN", 0, 0, &umr_bitfield_default },
+	 { "XTL_LOW_GAIN", 1, 2, &umr_bitfield_default },
+	 { "XTALIN_SEL", 10, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_CNTL[] = {
+	 { "SCK_OVERWRITE", 1, 1, &umr_bitfield_default },
+	 { "CLOCK_GATING_EN", 2, 2, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_SETUP_TIME", 8, 15, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_HOLD_TIME", 16, 23, &umr_bitfield_default },
+	 { "SCK_PRESCALE_REFCLK", 24, 27, &umr_bitfield_default },
+	 { "SCK_PRESCALE_CRYSTAL_CLK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPAGE_MIRROR_CNTL[] = {
+	 { "PAGE_MIRROR_BASE_ADDR", 0, 23, &umr_bitfield_default },
+	 { "PAGE_MIRROR_INVALIDATE", 24, 24, &umr_bitfield_default },
+	 { "PAGE_MIRROR_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "PAGE_MIRROR_USAGE", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_STATUS[] = {
+	 { "ROM_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCGTT_ROM_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_INDEX[] = {
+	 { "ROM_INDEX", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_DATA[] = {
+	 { "ROM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_START[] = {
+	 { "ROM_START", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_CNTL[] = {
+	 { "DATA_SIZE", 0, 15, &umr_bitfield_default },
+	 { "COMMAND_SIZE", 16, 17, &umr_bitfield_default },
+	 { "ROM_SW_RETURN_DATA_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_STATUS[] = {
+	 { "ROM_SW_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_COMMAND[] = {
+	 { "ROM_SW_INSTRUCTION", 0, 7, &umr_bitfield_default },
+	 { "ROM_SW_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_1[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_2[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_3[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_4[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_5[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_6[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_7[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_8[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_9[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_10[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_11[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_12[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_13[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_14[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_15[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_16[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_17[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_18[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_19[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_20[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_21[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_22[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_23[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_24[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_25[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_26[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_27[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_28[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_29[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_30[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_31[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_32[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_33[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_34[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_35[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_36[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_37[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_38[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_39[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_40[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_41[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_42[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_43[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_44[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_45[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_46[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_47[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_48[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_49[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_50[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_51[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_52[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_53[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_54[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_55[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_56[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_57[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_58[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_59[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_60[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_61[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_62[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_63[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_64[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_ENA[] = {
+	 { "THERM_INTH_SET", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_SET", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_SET", 2, 2, &umr_bitfield_default },
+	 { "THERM_INTH_CLR", 3, 3, &umr_bitfield_default },
+	 { "THERM_INTL_CLR", 4, 4, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CLR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_CTRL[] = {
+	 { "DIG_THERM_INTH", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 8, 15, &umr_bitfield_default },
+	 { "GNB_TEMP_THRESHOLD", 16, 23, &umr_bitfield_default },
+	 { "THERM_INTH_MASK", 24, 24, &umr_bitfield_default },
+	 { "THERM_INTL_MASK", 25, 25, &umr_bitfield_default },
+	 { "THERM_TRIGGER_MASK", 26, 26, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_MASK", 27, 27, &umr_bitfield_default },
+	 { "THERM_GNB_HW_ENA", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_STATUS[] = {
+	 { "THERM_INTH_DETECT", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_DETECT", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_DETECT", 2, 2, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_DETECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MAIN_PLL_OP_FREQ[] = {
+	 { "PLL_OP_FREQ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_STATUS[] = {
+	 { "SMU_DONE", 0, 0, &umr_bitfield_default },
+	 { "SMU_PASS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_FIRMWARE[] = {
+	 { "SMU_IN_PROG", 0, 0, &umr_bitfield_default },
+	 { "SMU_RD_DONE", 1, 2, &umr_bitfield_default },
+	 { "SMU_SRAM_RD_BLOCK_EN", 3, 3, &umr_bitfield_default },
+	 { "SMU_SRAM_WR_BLOCK_EN", 4, 4, &umr_bitfield_default },
+	 { "SMU_counter", 8, 11, &umr_bitfield_default },
+	 { "SMU_MODE", 16, 16, &umr_bitfield_default },
+	 { "SMU_SEL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_INPUT_DATA[] = {
+	 { "START_ADDR", 0, 30, &umr_bitfield_default },
+	 { "AUTO_START", 31, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/smu701_regs.i b/src/lib/ip/smu701_regs.i
new file mode 100644
index 0000000..63f85e1
--- /dev/null
+++ b/src/lib/ip/smu701_regs.i
@@ -0,0 +1,1266 @@
+	{ "mmGPIOPAD_SW_INT_STAT", REG_MMIO, 0x180, &mmGPIOPAD_SW_INT_STAT[0], sizeof(mmGPIOPAD_SW_INT_STAT)/sizeof(mmGPIOPAD_SW_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_STRENGTH", REG_MMIO, 0x181, &mmGPIOPAD_STRENGTH[0], sizeof(mmGPIOPAD_STRENGTH)/sizeof(mmGPIOPAD_STRENGTH[0]), 0, 0 },
+	{ "mmGPIOPAD_MASK", REG_MMIO, 0x182, &mmGPIOPAD_MASK[0], sizeof(mmGPIOPAD_MASK)/sizeof(mmGPIOPAD_MASK[0]), 0, 0 },
+	{ "mmGPIOPAD_A", REG_MMIO, 0x183, &mmGPIOPAD_A[0], sizeof(mmGPIOPAD_A)/sizeof(mmGPIOPAD_A[0]), 0, 0 },
+	{ "mmGPIOPAD_EN", REG_MMIO, 0x184, &mmGPIOPAD_EN[0], sizeof(mmGPIOPAD_EN)/sizeof(mmGPIOPAD_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_Y", REG_MMIO, 0x185, &mmGPIOPAD_Y[0], sizeof(mmGPIOPAD_Y)/sizeof(mmGPIOPAD_Y[0]), 0, 0 },
+	{ "mmGPIOPAD_PINSTRAPS", REG_MMIO, 0x186, &mmGPIOPAD_PINSTRAPS[0], sizeof(mmGPIOPAD_PINSTRAPS)/sizeof(mmGPIOPAD_PINSTRAPS[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_EN", REG_MMIO, 0x187, &mmGPIOPAD_INT_STAT_EN[0], sizeof(mmGPIOPAD_INT_STAT_EN)/sizeof(mmGPIOPAD_INT_STAT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT", REG_MMIO, 0x188, &mmGPIOPAD_INT_STAT[0], sizeof(mmGPIOPAD_INT_STAT)/sizeof(mmGPIOPAD_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_AK", REG_MMIO, 0x189, &mmGPIOPAD_INT_STAT_AK[0], sizeof(mmGPIOPAD_INT_STAT_AK)/sizeof(mmGPIOPAD_INT_STAT_AK[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_EN", REG_MMIO, 0x18a, &mmGPIOPAD_INT_EN[0], sizeof(mmGPIOPAD_INT_EN)/sizeof(mmGPIOPAD_INT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_TYPE", REG_MMIO, 0x18b, &mmGPIOPAD_INT_TYPE[0], sizeof(mmGPIOPAD_INT_TYPE)/sizeof(mmGPIOPAD_INT_TYPE[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_POLARITY", REG_MMIO, 0x18c, &mmGPIOPAD_INT_POLARITY[0], sizeof(mmGPIOPAD_INT_POLARITY)/sizeof(mmGPIOPAD_INT_POLARITY[0]), 0, 0 },
+	{ "mmGPIOPAD_EXTERN_TRIG_CNTL", REG_MMIO, 0x18d, &mmGPIOPAD_EXTERN_TRIG_CNTL[0], sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL)/sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL[0]), 0, 0 },
+	{ "mmGPIOPAD_RCVR_SEL", REG_MMIO, 0x191, &mmGPIOPAD_RCVR_SEL[0], sizeof(mmGPIOPAD_RCVR_SEL)/sizeof(mmGPIOPAD_RCVR_SEL[0]), 0, 0 },
+	{ "mmGPIOPAD_PU_EN", REG_MMIO, 0x192, &mmGPIOPAD_PU_EN[0], sizeof(mmGPIOPAD_PU_EN)/sizeof(mmGPIOPAD_PU_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_PD_EN", REG_MMIO, 0x193, &mmGPIOPAD_PD_EN[0], sizeof(mmGPIOPAD_PD_EN)/sizeof(mmGPIOPAD_PD_EN[0]), 0, 0 },
+	{ "mmCG_FPS_CNT", REG_MMIO, 0x1a4, &mmCG_FPS_CNT[0], sizeof(mmCG_FPS_CNT)/sizeof(mmCG_FPS_CNT[0]), 0, 0 },
+	{ "ixDPM_TABLE_1", REG_SMC, 0x3f000, &ixDPM_TABLE_1[0], sizeof(ixDPM_TABLE_1)/sizeof(ixDPM_TABLE_1[0]), 0, 0 },
+	{ "ixDPM_TABLE_2", REG_SMC, 0x3f004, &ixDPM_TABLE_2[0], sizeof(ixDPM_TABLE_2)/sizeof(ixDPM_TABLE_2[0]), 0, 0 },
+	{ "ixDPM_TABLE_3", REG_SMC, 0x3f008, &ixDPM_TABLE_3[0], sizeof(ixDPM_TABLE_3)/sizeof(ixDPM_TABLE_3[0]), 0, 0 },
+	{ "ixDPM_TABLE_4", REG_SMC, 0x3f00c, &ixDPM_TABLE_4[0], sizeof(ixDPM_TABLE_4)/sizeof(ixDPM_TABLE_4[0]), 0, 0 },
+	{ "ixDPM_TABLE_5", REG_SMC, 0x3f010, &ixDPM_TABLE_5[0], sizeof(ixDPM_TABLE_5)/sizeof(ixDPM_TABLE_5[0]), 0, 0 },
+	{ "ixDPM_TABLE_6", REG_SMC, 0x3f014, &ixDPM_TABLE_6[0], sizeof(ixDPM_TABLE_6)/sizeof(ixDPM_TABLE_6[0]), 0, 0 },
+	{ "ixDPM_TABLE_7", REG_SMC, 0x3f018, &ixDPM_TABLE_7[0], sizeof(ixDPM_TABLE_7)/sizeof(ixDPM_TABLE_7[0]), 0, 0 },
+	{ "ixDPM_TABLE_8", REG_SMC, 0x3f01c, &ixDPM_TABLE_8[0], sizeof(ixDPM_TABLE_8)/sizeof(ixDPM_TABLE_8[0]), 0, 0 },
+	{ "ixDPM_TABLE_9", REG_SMC, 0x3f020, &ixDPM_TABLE_9[0], sizeof(ixDPM_TABLE_9)/sizeof(ixDPM_TABLE_9[0]), 0, 0 },
+	{ "ixDPM_TABLE_10", REG_SMC, 0x3f024, &ixDPM_TABLE_10[0], sizeof(ixDPM_TABLE_10)/sizeof(ixDPM_TABLE_10[0]), 0, 0 },
+	{ "ixDPM_TABLE_11", REG_SMC, 0x3f028, &ixDPM_TABLE_11[0], sizeof(ixDPM_TABLE_11)/sizeof(ixDPM_TABLE_11[0]), 0, 0 },
+	{ "ixDPM_TABLE_12", REG_SMC, 0x3f02c, &ixDPM_TABLE_12[0], sizeof(ixDPM_TABLE_12)/sizeof(ixDPM_TABLE_12[0]), 0, 0 },
+	{ "ixDPM_TABLE_13", REG_SMC, 0x3f030, &ixDPM_TABLE_13[0], sizeof(ixDPM_TABLE_13)/sizeof(ixDPM_TABLE_13[0]), 0, 0 },
+	{ "ixDPM_TABLE_14", REG_SMC, 0x3f034, &ixDPM_TABLE_14[0], sizeof(ixDPM_TABLE_14)/sizeof(ixDPM_TABLE_14[0]), 0, 0 },
+	{ "ixDPM_TABLE_15", REG_SMC, 0x3f038, &ixDPM_TABLE_15[0], sizeof(ixDPM_TABLE_15)/sizeof(ixDPM_TABLE_15[0]), 0, 0 },
+	{ "ixDPM_TABLE_16", REG_SMC, 0x3f03c, &ixDPM_TABLE_16[0], sizeof(ixDPM_TABLE_16)/sizeof(ixDPM_TABLE_16[0]), 0, 0 },
+	{ "ixDPM_TABLE_17", REG_SMC, 0x3f040, &ixDPM_TABLE_17[0], sizeof(ixDPM_TABLE_17)/sizeof(ixDPM_TABLE_17[0]), 0, 0 },
+	{ "ixDPM_TABLE_18", REG_SMC, 0x3f044, &ixDPM_TABLE_18[0], sizeof(ixDPM_TABLE_18)/sizeof(ixDPM_TABLE_18[0]), 0, 0 },
+	{ "ixDPM_TABLE_19", REG_SMC, 0x3f048, &ixDPM_TABLE_19[0], sizeof(ixDPM_TABLE_19)/sizeof(ixDPM_TABLE_19[0]), 0, 0 },
+	{ "ixDPM_TABLE_20", REG_SMC, 0x3f04c, &ixDPM_TABLE_20[0], sizeof(ixDPM_TABLE_20)/sizeof(ixDPM_TABLE_20[0]), 0, 0 },
+	{ "ixDPM_TABLE_21", REG_SMC, 0x3f050, &ixDPM_TABLE_21[0], sizeof(ixDPM_TABLE_21)/sizeof(ixDPM_TABLE_21[0]), 0, 0 },
+	{ "ixDPM_TABLE_22", REG_SMC, 0x3f054, &ixDPM_TABLE_22[0], sizeof(ixDPM_TABLE_22)/sizeof(ixDPM_TABLE_22[0]), 0, 0 },
+	{ "ixDPM_TABLE_23", REG_SMC, 0x3f058, &ixDPM_TABLE_23[0], sizeof(ixDPM_TABLE_23)/sizeof(ixDPM_TABLE_23[0]), 0, 0 },
+	{ "ixDPM_TABLE_24", REG_SMC, 0x3f05c, &ixDPM_TABLE_24[0], sizeof(ixDPM_TABLE_24)/sizeof(ixDPM_TABLE_24[0]), 0, 0 },
+	{ "ixDPM_TABLE_25", REG_SMC, 0x3f060, &ixDPM_TABLE_25[0], sizeof(ixDPM_TABLE_25)/sizeof(ixDPM_TABLE_25[0]), 0, 0 },
+	{ "ixDPM_TABLE_26", REG_SMC, 0x3f064, &ixDPM_TABLE_26[0], sizeof(ixDPM_TABLE_26)/sizeof(ixDPM_TABLE_26[0]), 0, 0 },
+	{ "ixDPM_TABLE_27", REG_SMC, 0x3f068, &ixDPM_TABLE_27[0], sizeof(ixDPM_TABLE_27)/sizeof(ixDPM_TABLE_27[0]), 0, 0 },
+	{ "ixDPM_TABLE_28", REG_SMC, 0x3f06c, &ixDPM_TABLE_28[0], sizeof(ixDPM_TABLE_28)/sizeof(ixDPM_TABLE_28[0]), 0, 0 },
+	{ "ixDPM_TABLE_29", REG_SMC, 0x3f070, &ixDPM_TABLE_29[0], sizeof(ixDPM_TABLE_29)/sizeof(ixDPM_TABLE_29[0]), 0, 0 },
+	{ "ixDPM_TABLE_30", REG_SMC, 0x3f074, &ixDPM_TABLE_30[0], sizeof(ixDPM_TABLE_30)/sizeof(ixDPM_TABLE_30[0]), 0, 0 },
+	{ "ixDPM_TABLE_31", REG_SMC, 0x3f078, &ixDPM_TABLE_31[0], sizeof(ixDPM_TABLE_31)/sizeof(ixDPM_TABLE_31[0]), 0, 0 },
+	{ "ixDPM_TABLE_32", REG_SMC, 0x3f07c, &ixDPM_TABLE_32[0], sizeof(ixDPM_TABLE_32)/sizeof(ixDPM_TABLE_32[0]), 0, 0 },
+	{ "ixDPM_TABLE_33", REG_SMC, 0x3f080, &ixDPM_TABLE_33[0], sizeof(ixDPM_TABLE_33)/sizeof(ixDPM_TABLE_33[0]), 0, 0 },
+	{ "ixDPM_TABLE_34", REG_SMC, 0x3f084, &ixDPM_TABLE_34[0], sizeof(ixDPM_TABLE_34)/sizeof(ixDPM_TABLE_34[0]), 0, 0 },
+	{ "ixDPM_TABLE_35", REG_SMC, 0x3f088, &ixDPM_TABLE_35[0], sizeof(ixDPM_TABLE_35)/sizeof(ixDPM_TABLE_35[0]), 0, 0 },
+	{ "ixDPM_TABLE_36", REG_SMC, 0x3f08c, &ixDPM_TABLE_36[0], sizeof(ixDPM_TABLE_36)/sizeof(ixDPM_TABLE_36[0]), 0, 0 },
+	{ "ixDPM_TABLE_37", REG_SMC, 0x3f090, &ixDPM_TABLE_37[0], sizeof(ixDPM_TABLE_37)/sizeof(ixDPM_TABLE_37[0]), 0, 0 },
+	{ "ixDPM_TABLE_38", REG_SMC, 0x3f094, &ixDPM_TABLE_38[0], sizeof(ixDPM_TABLE_38)/sizeof(ixDPM_TABLE_38[0]), 0, 0 },
+	{ "ixDPM_TABLE_39", REG_SMC, 0x3f098, &ixDPM_TABLE_39[0], sizeof(ixDPM_TABLE_39)/sizeof(ixDPM_TABLE_39[0]), 0, 0 },
+	{ "ixDPM_TABLE_40", REG_SMC, 0x3f09c, &ixDPM_TABLE_40[0], sizeof(ixDPM_TABLE_40)/sizeof(ixDPM_TABLE_40[0]), 0, 0 },
+	{ "ixDPM_TABLE_41", REG_SMC, 0x3f0a0, &ixDPM_TABLE_41[0], sizeof(ixDPM_TABLE_41)/sizeof(ixDPM_TABLE_41[0]), 0, 0 },
+	{ "ixDPM_TABLE_42", REG_SMC, 0x3f0a4, &ixDPM_TABLE_42[0], sizeof(ixDPM_TABLE_42)/sizeof(ixDPM_TABLE_42[0]), 0, 0 },
+	{ "ixDPM_TABLE_43", REG_SMC, 0x3f0a8, &ixDPM_TABLE_43[0], sizeof(ixDPM_TABLE_43)/sizeof(ixDPM_TABLE_43[0]), 0, 0 },
+	{ "ixDPM_TABLE_44", REG_SMC, 0x3f0ac, &ixDPM_TABLE_44[0], sizeof(ixDPM_TABLE_44)/sizeof(ixDPM_TABLE_44[0]), 0, 0 },
+	{ "ixDPM_TABLE_45", REG_SMC, 0x3f0b0, &ixDPM_TABLE_45[0], sizeof(ixDPM_TABLE_45)/sizeof(ixDPM_TABLE_45[0]), 0, 0 },
+	{ "ixDPM_TABLE_46", REG_SMC, 0x3f0b4, &ixDPM_TABLE_46[0], sizeof(ixDPM_TABLE_46)/sizeof(ixDPM_TABLE_46[0]), 0, 0 },
+	{ "ixDPM_TABLE_47", REG_SMC, 0x3f0b8, &ixDPM_TABLE_47[0], sizeof(ixDPM_TABLE_47)/sizeof(ixDPM_TABLE_47[0]), 0, 0 },
+	{ "ixDPM_TABLE_48", REG_SMC, 0x3f0bc, &ixDPM_TABLE_48[0], sizeof(ixDPM_TABLE_48)/sizeof(ixDPM_TABLE_48[0]), 0, 0 },
+	{ "ixDPM_TABLE_49", REG_SMC, 0x3f0c0, &ixDPM_TABLE_49[0], sizeof(ixDPM_TABLE_49)/sizeof(ixDPM_TABLE_49[0]), 0, 0 },
+	{ "ixDPM_TABLE_50", REG_SMC, 0x3f0c4, &ixDPM_TABLE_50[0], sizeof(ixDPM_TABLE_50)/sizeof(ixDPM_TABLE_50[0]), 0, 0 },
+	{ "ixDPM_TABLE_51", REG_SMC, 0x3f0c8, &ixDPM_TABLE_51[0], sizeof(ixDPM_TABLE_51)/sizeof(ixDPM_TABLE_51[0]), 0, 0 },
+	{ "ixDPM_TABLE_52", REG_SMC, 0x3f0cc, &ixDPM_TABLE_52[0], sizeof(ixDPM_TABLE_52)/sizeof(ixDPM_TABLE_52[0]), 0, 0 },
+	{ "ixDPM_TABLE_53", REG_SMC, 0x3f0d0, &ixDPM_TABLE_53[0], sizeof(ixDPM_TABLE_53)/sizeof(ixDPM_TABLE_53[0]), 0, 0 },
+	{ "ixDPM_TABLE_54", REG_SMC, 0x3f0d4, &ixDPM_TABLE_54[0], sizeof(ixDPM_TABLE_54)/sizeof(ixDPM_TABLE_54[0]), 0, 0 },
+	{ "ixDPM_TABLE_55", REG_SMC, 0x3f0d8, &ixDPM_TABLE_55[0], sizeof(ixDPM_TABLE_55)/sizeof(ixDPM_TABLE_55[0]), 0, 0 },
+	{ "ixDPM_TABLE_56", REG_SMC, 0x3f0dc, &ixDPM_TABLE_56[0], sizeof(ixDPM_TABLE_56)/sizeof(ixDPM_TABLE_56[0]), 0, 0 },
+	{ "ixDPM_TABLE_57", REG_SMC, 0x3f0e0, &ixDPM_TABLE_57[0], sizeof(ixDPM_TABLE_57)/sizeof(ixDPM_TABLE_57[0]), 0, 0 },
+	{ "ixDPM_TABLE_58", REG_SMC, 0x3f0e4, &ixDPM_TABLE_58[0], sizeof(ixDPM_TABLE_58)/sizeof(ixDPM_TABLE_58[0]), 0, 0 },
+	{ "ixDPM_TABLE_59", REG_SMC, 0x3f0e8, &ixDPM_TABLE_59[0], sizeof(ixDPM_TABLE_59)/sizeof(ixDPM_TABLE_59[0]), 0, 0 },
+	{ "ixDPM_TABLE_60", REG_SMC, 0x3f0ec, &ixDPM_TABLE_60[0], sizeof(ixDPM_TABLE_60)/sizeof(ixDPM_TABLE_60[0]), 0, 0 },
+	{ "ixDPM_TABLE_61", REG_SMC, 0x3f0f0, &ixDPM_TABLE_61[0], sizeof(ixDPM_TABLE_61)/sizeof(ixDPM_TABLE_61[0]), 0, 0 },
+	{ "ixDPM_TABLE_62", REG_SMC, 0x3f0f4, &ixDPM_TABLE_62[0], sizeof(ixDPM_TABLE_62)/sizeof(ixDPM_TABLE_62[0]), 0, 0 },
+	{ "ixDPM_TABLE_63", REG_SMC, 0x3f0f8, &ixDPM_TABLE_63[0], sizeof(ixDPM_TABLE_63)/sizeof(ixDPM_TABLE_63[0]), 0, 0 },
+	{ "ixDPM_TABLE_64", REG_SMC, 0x3f0fc, &ixDPM_TABLE_64[0], sizeof(ixDPM_TABLE_64)/sizeof(ixDPM_TABLE_64[0]), 0, 0 },
+	{ "ixDPM_TABLE_65", REG_SMC, 0x3f100, &ixDPM_TABLE_65[0], sizeof(ixDPM_TABLE_65)/sizeof(ixDPM_TABLE_65[0]), 0, 0 },
+	{ "ixDPM_TABLE_66", REG_SMC, 0x3f104, &ixDPM_TABLE_66[0], sizeof(ixDPM_TABLE_66)/sizeof(ixDPM_TABLE_66[0]), 0, 0 },
+	{ "ixDPM_TABLE_67", REG_SMC, 0x3f108, &ixDPM_TABLE_67[0], sizeof(ixDPM_TABLE_67)/sizeof(ixDPM_TABLE_67[0]), 0, 0 },
+	{ "ixDPM_TABLE_68", REG_SMC, 0x3f10c, &ixDPM_TABLE_68[0], sizeof(ixDPM_TABLE_68)/sizeof(ixDPM_TABLE_68[0]), 0, 0 },
+	{ "ixDPM_TABLE_69", REG_SMC, 0x3f110, &ixDPM_TABLE_69[0], sizeof(ixDPM_TABLE_69)/sizeof(ixDPM_TABLE_69[0]), 0, 0 },
+	{ "ixDPM_TABLE_70", REG_SMC, 0x3f114, &ixDPM_TABLE_70[0], sizeof(ixDPM_TABLE_70)/sizeof(ixDPM_TABLE_70[0]), 0, 0 },
+	{ "ixDPM_TABLE_71", REG_SMC, 0x3f118, &ixDPM_TABLE_71[0], sizeof(ixDPM_TABLE_71)/sizeof(ixDPM_TABLE_71[0]), 0, 0 },
+	{ "ixDPM_TABLE_72", REG_SMC, 0x3f11c, &ixDPM_TABLE_72[0], sizeof(ixDPM_TABLE_72)/sizeof(ixDPM_TABLE_72[0]), 0, 0 },
+	{ "ixDPM_TABLE_73", REG_SMC, 0x3f120, &ixDPM_TABLE_73[0], sizeof(ixDPM_TABLE_73)/sizeof(ixDPM_TABLE_73[0]), 0, 0 },
+	{ "ixDPM_TABLE_74", REG_SMC, 0x3f124, &ixDPM_TABLE_74[0], sizeof(ixDPM_TABLE_74)/sizeof(ixDPM_TABLE_74[0]), 0, 0 },
+	{ "ixDPM_TABLE_75", REG_SMC, 0x3f128, &ixDPM_TABLE_75[0], sizeof(ixDPM_TABLE_75)/sizeof(ixDPM_TABLE_75[0]), 0, 0 },
+	{ "ixDPM_TABLE_76", REG_SMC, 0x3f12c, &ixDPM_TABLE_76[0], sizeof(ixDPM_TABLE_76)/sizeof(ixDPM_TABLE_76[0]), 0, 0 },
+	{ "ixDPM_TABLE_77", REG_SMC, 0x3f130, &ixDPM_TABLE_77[0], sizeof(ixDPM_TABLE_77)/sizeof(ixDPM_TABLE_77[0]), 0, 0 },
+	{ "ixDPM_TABLE_78", REG_SMC, 0x3f134, &ixDPM_TABLE_78[0], sizeof(ixDPM_TABLE_78)/sizeof(ixDPM_TABLE_78[0]), 0, 0 },
+	{ "ixDPM_TABLE_79", REG_SMC, 0x3f138, &ixDPM_TABLE_79[0], sizeof(ixDPM_TABLE_79)/sizeof(ixDPM_TABLE_79[0]), 0, 0 },
+	{ "ixDPM_TABLE_80", REG_SMC, 0x3f13c, &ixDPM_TABLE_80[0], sizeof(ixDPM_TABLE_80)/sizeof(ixDPM_TABLE_80[0]), 0, 0 },
+	{ "ixDPM_TABLE_81", REG_SMC, 0x3f140, &ixDPM_TABLE_81[0], sizeof(ixDPM_TABLE_81)/sizeof(ixDPM_TABLE_81[0]), 0, 0 },
+	{ "ixDPM_TABLE_82", REG_SMC, 0x3f144, &ixDPM_TABLE_82[0], sizeof(ixDPM_TABLE_82)/sizeof(ixDPM_TABLE_82[0]), 0, 0 },
+	{ "ixDPM_TABLE_83", REG_SMC, 0x3f148, &ixDPM_TABLE_83[0], sizeof(ixDPM_TABLE_83)/sizeof(ixDPM_TABLE_83[0]), 0, 0 },
+	{ "ixDPM_TABLE_84", REG_SMC, 0x3f14c, &ixDPM_TABLE_84[0], sizeof(ixDPM_TABLE_84)/sizeof(ixDPM_TABLE_84[0]), 0, 0 },
+	{ "ixDPM_TABLE_85", REG_SMC, 0x3f150, &ixDPM_TABLE_85[0], sizeof(ixDPM_TABLE_85)/sizeof(ixDPM_TABLE_85[0]), 0, 0 },
+	{ "ixDPM_TABLE_86", REG_SMC, 0x3f154, &ixDPM_TABLE_86[0], sizeof(ixDPM_TABLE_86)/sizeof(ixDPM_TABLE_86[0]), 0, 0 },
+	{ "ixDPM_TABLE_87", REG_SMC, 0x3f158, &ixDPM_TABLE_87[0], sizeof(ixDPM_TABLE_87)/sizeof(ixDPM_TABLE_87[0]), 0, 0 },
+	{ "ixDPM_TABLE_88", REG_SMC, 0x3f15c, &ixDPM_TABLE_88[0], sizeof(ixDPM_TABLE_88)/sizeof(ixDPM_TABLE_88[0]), 0, 0 },
+	{ "ixDPM_TABLE_89", REG_SMC, 0x3f160, &ixDPM_TABLE_89[0], sizeof(ixDPM_TABLE_89)/sizeof(ixDPM_TABLE_89[0]), 0, 0 },
+	{ "ixDPM_TABLE_90", REG_SMC, 0x3f164, &ixDPM_TABLE_90[0], sizeof(ixDPM_TABLE_90)/sizeof(ixDPM_TABLE_90[0]), 0, 0 },
+	{ "ixDPM_TABLE_91", REG_SMC, 0x3f168, &ixDPM_TABLE_91[0], sizeof(ixDPM_TABLE_91)/sizeof(ixDPM_TABLE_91[0]), 0, 0 },
+	{ "ixDPM_TABLE_92", REG_SMC, 0x3f16c, &ixDPM_TABLE_92[0], sizeof(ixDPM_TABLE_92)/sizeof(ixDPM_TABLE_92[0]), 0, 0 },
+	{ "ixDPM_TABLE_93", REG_SMC, 0x3f170, &ixDPM_TABLE_93[0], sizeof(ixDPM_TABLE_93)/sizeof(ixDPM_TABLE_93[0]), 0, 0 },
+	{ "ixDPM_TABLE_94", REG_SMC, 0x3f174, &ixDPM_TABLE_94[0], sizeof(ixDPM_TABLE_94)/sizeof(ixDPM_TABLE_94[0]), 0, 0 },
+	{ "ixDPM_TABLE_95", REG_SMC, 0x3f178, &ixDPM_TABLE_95[0], sizeof(ixDPM_TABLE_95)/sizeof(ixDPM_TABLE_95[0]), 0, 0 },
+	{ "ixDPM_TABLE_96", REG_SMC, 0x3f17c, &ixDPM_TABLE_96[0], sizeof(ixDPM_TABLE_96)/sizeof(ixDPM_TABLE_96[0]), 0, 0 },
+	{ "ixDPM_TABLE_97", REG_SMC, 0x3f180, &ixDPM_TABLE_97[0], sizeof(ixDPM_TABLE_97)/sizeof(ixDPM_TABLE_97[0]), 0, 0 },
+	{ "ixDPM_TABLE_98", REG_SMC, 0x3f184, &ixDPM_TABLE_98[0], sizeof(ixDPM_TABLE_98)/sizeof(ixDPM_TABLE_98[0]), 0, 0 },
+	{ "ixDPM_TABLE_99", REG_SMC, 0x3f188, &ixDPM_TABLE_99[0], sizeof(ixDPM_TABLE_99)/sizeof(ixDPM_TABLE_99[0]), 0, 0 },
+	{ "ixDPM_TABLE_100", REG_SMC, 0x3f18c, &ixDPM_TABLE_100[0], sizeof(ixDPM_TABLE_100)/sizeof(ixDPM_TABLE_100[0]), 0, 0 },
+	{ "ixDPM_TABLE_101", REG_SMC, 0x3f190, &ixDPM_TABLE_101[0], sizeof(ixDPM_TABLE_101)/sizeof(ixDPM_TABLE_101[0]), 0, 0 },
+	{ "ixDPM_TABLE_102", REG_SMC, 0x3f194, &ixDPM_TABLE_102[0], sizeof(ixDPM_TABLE_102)/sizeof(ixDPM_TABLE_102[0]), 0, 0 },
+	{ "ixDPM_TABLE_103", REG_SMC, 0x3f198, &ixDPM_TABLE_103[0], sizeof(ixDPM_TABLE_103)/sizeof(ixDPM_TABLE_103[0]), 0, 0 },
+	{ "ixDPM_TABLE_104", REG_SMC, 0x3f19c, &ixDPM_TABLE_104[0], sizeof(ixDPM_TABLE_104)/sizeof(ixDPM_TABLE_104[0]), 0, 0 },
+	{ "ixDPM_TABLE_105", REG_SMC, 0x3f1a0, &ixDPM_TABLE_105[0], sizeof(ixDPM_TABLE_105)/sizeof(ixDPM_TABLE_105[0]), 0, 0 },
+	{ "ixDPM_TABLE_106", REG_SMC, 0x3f1a4, &ixDPM_TABLE_106[0], sizeof(ixDPM_TABLE_106)/sizeof(ixDPM_TABLE_106[0]), 0, 0 },
+	{ "ixDPM_TABLE_107", REG_SMC, 0x3f1a8, &ixDPM_TABLE_107[0], sizeof(ixDPM_TABLE_107)/sizeof(ixDPM_TABLE_107[0]), 0, 0 },
+	{ "ixDPM_TABLE_108", REG_SMC, 0x3f1ac, &ixDPM_TABLE_108[0], sizeof(ixDPM_TABLE_108)/sizeof(ixDPM_TABLE_108[0]), 0, 0 },
+	{ "ixDPM_TABLE_109", REG_SMC, 0x3f1b0, &ixDPM_TABLE_109[0], sizeof(ixDPM_TABLE_109)/sizeof(ixDPM_TABLE_109[0]), 0, 0 },
+	{ "ixDPM_TABLE_110", REG_SMC, 0x3f1b4, &ixDPM_TABLE_110[0], sizeof(ixDPM_TABLE_110)/sizeof(ixDPM_TABLE_110[0]), 0, 0 },
+	{ "ixDPM_TABLE_111", REG_SMC, 0x3f1b8, &ixDPM_TABLE_111[0], sizeof(ixDPM_TABLE_111)/sizeof(ixDPM_TABLE_111[0]), 0, 0 },
+	{ "ixDPM_TABLE_112", REG_SMC, 0x3f1bc, &ixDPM_TABLE_112[0], sizeof(ixDPM_TABLE_112)/sizeof(ixDPM_TABLE_112[0]), 0, 0 },
+	{ "ixDPM_TABLE_113", REG_SMC, 0x3f1c0, &ixDPM_TABLE_113[0], sizeof(ixDPM_TABLE_113)/sizeof(ixDPM_TABLE_113[0]), 0, 0 },
+	{ "ixDPM_TABLE_114", REG_SMC, 0x3f1c4, &ixDPM_TABLE_114[0], sizeof(ixDPM_TABLE_114)/sizeof(ixDPM_TABLE_114[0]), 0, 0 },
+	{ "ixDPM_TABLE_115", REG_SMC, 0x3f1c8, &ixDPM_TABLE_115[0], sizeof(ixDPM_TABLE_115)/sizeof(ixDPM_TABLE_115[0]), 0, 0 },
+	{ "ixDPM_TABLE_116", REG_SMC, 0x3f1cc, &ixDPM_TABLE_116[0], sizeof(ixDPM_TABLE_116)/sizeof(ixDPM_TABLE_116[0]), 0, 0 },
+	{ "ixDPM_TABLE_117", REG_SMC, 0x3f1d0, &ixDPM_TABLE_117[0], sizeof(ixDPM_TABLE_117)/sizeof(ixDPM_TABLE_117[0]), 0, 0 },
+	{ "ixDPM_TABLE_118", REG_SMC, 0x3f1d4, &ixDPM_TABLE_118[0], sizeof(ixDPM_TABLE_118)/sizeof(ixDPM_TABLE_118[0]), 0, 0 },
+	{ "ixDPM_TABLE_119", REG_SMC, 0x3f1d8, &ixDPM_TABLE_119[0], sizeof(ixDPM_TABLE_119)/sizeof(ixDPM_TABLE_119[0]), 0, 0 },
+	{ "ixDPM_TABLE_120", REG_SMC, 0x3f1dc, &ixDPM_TABLE_120[0], sizeof(ixDPM_TABLE_120)/sizeof(ixDPM_TABLE_120[0]), 0, 0 },
+	{ "ixDPM_TABLE_121", REG_SMC, 0x3f1e0, &ixDPM_TABLE_121[0], sizeof(ixDPM_TABLE_121)/sizeof(ixDPM_TABLE_121[0]), 0, 0 },
+	{ "ixDPM_TABLE_122", REG_SMC, 0x3f1e4, &ixDPM_TABLE_122[0], sizeof(ixDPM_TABLE_122)/sizeof(ixDPM_TABLE_122[0]), 0, 0 },
+	{ "ixDPM_TABLE_123", REG_SMC, 0x3f1e8, &ixDPM_TABLE_123[0], sizeof(ixDPM_TABLE_123)/sizeof(ixDPM_TABLE_123[0]), 0, 0 },
+	{ "ixDPM_TABLE_124", REG_SMC, 0x3f1ec, &ixDPM_TABLE_124[0], sizeof(ixDPM_TABLE_124)/sizeof(ixDPM_TABLE_124[0]), 0, 0 },
+	{ "ixDPM_TABLE_125", REG_SMC, 0x3f1f0, &ixDPM_TABLE_125[0], sizeof(ixDPM_TABLE_125)/sizeof(ixDPM_TABLE_125[0]), 0, 0 },
+	{ "ixDPM_TABLE_126", REG_SMC, 0x3f1f4, &ixDPM_TABLE_126[0], sizeof(ixDPM_TABLE_126)/sizeof(ixDPM_TABLE_126[0]), 0, 0 },
+	{ "ixDPM_TABLE_127", REG_SMC, 0x3f1f8, &ixDPM_TABLE_127[0], sizeof(ixDPM_TABLE_127)/sizeof(ixDPM_TABLE_127[0]), 0, 0 },
+	{ "ixDPM_TABLE_128", REG_SMC, 0x3f1fc, &ixDPM_TABLE_128[0], sizeof(ixDPM_TABLE_128)/sizeof(ixDPM_TABLE_128[0]), 0, 0 },
+	{ "ixDPM_TABLE_129", REG_SMC, 0x3f200, &ixDPM_TABLE_129[0], sizeof(ixDPM_TABLE_129)/sizeof(ixDPM_TABLE_129[0]), 0, 0 },
+	{ "ixDPM_TABLE_130", REG_SMC, 0x3f204, &ixDPM_TABLE_130[0], sizeof(ixDPM_TABLE_130)/sizeof(ixDPM_TABLE_130[0]), 0, 0 },
+	{ "ixDPM_TABLE_131", REG_SMC, 0x3f208, &ixDPM_TABLE_131[0], sizeof(ixDPM_TABLE_131)/sizeof(ixDPM_TABLE_131[0]), 0, 0 },
+	{ "ixDPM_TABLE_132", REG_SMC, 0x3f20c, &ixDPM_TABLE_132[0], sizeof(ixDPM_TABLE_132)/sizeof(ixDPM_TABLE_132[0]), 0, 0 },
+	{ "ixDPM_TABLE_133", REG_SMC, 0x3f210, &ixDPM_TABLE_133[0], sizeof(ixDPM_TABLE_133)/sizeof(ixDPM_TABLE_133[0]), 0, 0 },
+	{ "ixDPM_TABLE_134", REG_SMC, 0x3f214, &ixDPM_TABLE_134[0], sizeof(ixDPM_TABLE_134)/sizeof(ixDPM_TABLE_134[0]), 0, 0 },
+	{ "ixDPM_TABLE_135", REG_SMC, 0x3f218, &ixDPM_TABLE_135[0], sizeof(ixDPM_TABLE_135)/sizeof(ixDPM_TABLE_135[0]), 0, 0 },
+	{ "ixDPM_TABLE_136", REG_SMC, 0x3f21c, &ixDPM_TABLE_136[0], sizeof(ixDPM_TABLE_136)/sizeof(ixDPM_TABLE_136[0]), 0, 0 },
+	{ "ixDPM_TABLE_137", REG_SMC, 0x3f220, &ixDPM_TABLE_137[0], sizeof(ixDPM_TABLE_137)/sizeof(ixDPM_TABLE_137[0]), 0, 0 },
+	{ "ixDPM_TABLE_138", REG_SMC, 0x3f224, &ixDPM_TABLE_138[0], sizeof(ixDPM_TABLE_138)/sizeof(ixDPM_TABLE_138[0]), 0, 0 },
+	{ "ixDPM_TABLE_139", REG_SMC, 0x3f228, &ixDPM_TABLE_139[0], sizeof(ixDPM_TABLE_139)/sizeof(ixDPM_TABLE_139[0]), 0, 0 },
+	{ "ixDPM_TABLE_140", REG_SMC, 0x3f22c, &ixDPM_TABLE_140[0], sizeof(ixDPM_TABLE_140)/sizeof(ixDPM_TABLE_140[0]), 0, 0 },
+	{ "ixDPM_TABLE_141", REG_SMC, 0x3f230, &ixDPM_TABLE_141[0], sizeof(ixDPM_TABLE_141)/sizeof(ixDPM_TABLE_141[0]), 0, 0 },
+	{ "ixDPM_TABLE_142", REG_SMC, 0x3f234, &ixDPM_TABLE_142[0], sizeof(ixDPM_TABLE_142)/sizeof(ixDPM_TABLE_142[0]), 0, 0 },
+	{ "ixDPM_TABLE_143", REG_SMC, 0x3f238, &ixDPM_TABLE_143[0], sizeof(ixDPM_TABLE_143)/sizeof(ixDPM_TABLE_143[0]), 0, 0 },
+	{ "ixDPM_TABLE_144", REG_SMC, 0x3f23c, &ixDPM_TABLE_144[0], sizeof(ixDPM_TABLE_144)/sizeof(ixDPM_TABLE_144[0]), 0, 0 },
+	{ "ixDPM_TABLE_145", REG_SMC, 0x3f240, &ixDPM_TABLE_145[0], sizeof(ixDPM_TABLE_145)/sizeof(ixDPM_TABLE_145[0]), 0, 0 },
+	{ "ixDPM_TABLE_146", REG_SMC, 0x3f244, &ixDPM_TABLE_146[0], sizeof(ixDPM_TABLE_146)/sizeof(ixDPM_TABLE_146[0]), 0, 0 },
+	{ "ixDPM_TABLE_147", REG_SMC, 0x3f248, &ixDPM_TABLE_147[0], sizeof(ixDPM_TABLE_147)/sizeof(ixDPM_TABLE_147[0]), 0, 0 },
+	{ "ixDPM_TABLE_148", REG_SMC, 0x3f24c, &ixDPM_TABLE_148[0], sizeof(ixDPM_TABLE_148)/sizeof(ixDPM_TABLE_148[0]), 0, 0 },
+	{ "ixDPM_TABLE_149", REG_SMC, 0x3f250, &ixDPM_TABLE_149[0], sizeof(ixDPM_TABLE_149)/sizeof(ixDPM_TABLE_149[0]), 0, 0 },
+	{ "ixDPM_TABLE_150", REG_SMC, 0x3f254, &ixDPM_TABLE_150[0], sizeof(ixDPM_TABLE_150)/sizeof(ixDPM_TABLE_150[0]), 0, 0 },
+	{ "ixDPM_TABLE_151", REG_SMC, 0x3f258, &ixDPM_TABLE_151[0], sizeof(ixDPM_TABLE_151)/sizeof(ixDPM_TABLE_151[0]), 0, 0 },
+	{ "ixDPM_TABLE_152", REG_SMC, 0x3f25c, &ixDPM_TABLE_152[0], sizeof(ixDPM_TABLE_152)/sizeof(ixDPM_TABLE_152[0]), 0, 0 },
+	{ "ixDPM_TABLE_153", REG_SMC, 0x3f260, &ixDPM_TABLE_153[0], sizeof(ixDPM_TABLE_153)/sizeof(ixDPM_TABLE_153[0]), 0, 0 },
+	{ "ixDPM_TABLE_154", REG_SMC, 0x3f264, &ixDPM_TABLE_154[0], sizeof(ixDPM_TABLE_154)/sizeof(ixDPM_TABLE_154[0]), 0, 0 },
+	{ "ixDPM_TABLE_155", REG_SMC, 0x3f268, &ixDPM_TABLE_155[0], sizeof(ixDPM_TABLE_155)/sizeof(ixDPM_TABLE_155[0]), 0, 0 },
+	{ "ixDPM_TABLE_156", REG_SMC, 0x3f26c, &ixDPM_TABLE_156[0], sizeof(ixDPM_TABLE_156)/sizeof(ixDPM_TABLE_156[0]), 0, 0 },
+	{ "ixDPM_TABLE_157", REG_SMC, 0x3f270, &ixDPM_TABLE_157[0], sizeof(ixDPM_TABLE_157)/sizeof(ixDPM_TABLE_157[0]), 0, 0 },
+	{ "ixDPM_TABLE_158", REG_SMC, 0x3f274, &ixDPM_TABLE_158[0], sizeof(ixDPM_TABLE_158)/sizeof(ixDPM_TABLE_158[0]), 0, 0 },
+	{ "ixDPM_TABLE_159", REG_SMC, 0x3f278, &ixDPM_TABLE_159[0], sizeof(ixDPM_TABLE_159)/sizeof(ixDPM_TABLE_159[0]), 0, 0 },
+	{ "ixDPM_TABLE_160", REG_SMC, 0x3f27c, &ixDPM_TABLE_160[0], sizeof(ixDPM_TABLE_160)/sizeof(ixDPM_TABLE_160[0]), 0, 0 },
+	{ "ixDPM_TABLE_161", REG_SMC, 0x3f280, &ixDPM_TABLE_161[0], sizeof(ixDPM_TABLE_161)/sizeof(ixDPM_TABLE_161[0]), 0, 0 },
+	{ "ixDPM_TABLE_162", REG_SMC, 0x3f284, &ixDPM_TABLE_162[0], sizeof(ixDPM_TABLE_162)/sizeof(ixDPM_TABLE_162[0]), 0, 0 },
+	{ "ixDPM_TABLE_163", REG_SMC, 0x3f288, &ixDPM_TABLE_163[0], sizeof(ixDPM_TABLE_163)/sizeof(ixDPM_TABLE_163[0]), 0, 0 },
+	{ "ixDPM_TABLE_164", REG_SMC, 0x3f28c, &ixDPM_TABLE_164[0], sizeof(ixDPM_TABLE_164)/sizeof(ixDPM_TABLE_164[0]), 0, 0 },
+	{ "ixDPM_TABLE_165", REG_SMC, 0x3f290, &ixDPM_TABLE_165[0], sizeof(ixDPM_TABLE_165)/sizeof(ixDPM_TABLE_165[0]), 0, 0 },
+	{ "ixDPM_TABLE_166", REG_SMC, 0x3f294, &ixDPM_TABLE_166[0], sizeof(ixDPM_TABLE_166)/sizeof(ixDPM_TABLE_166[0]), 0, 0 },
+	{ "ixDPM_TABLE_167", REG_SMC, 0x3f298, &ixDPM_TABLE_167[0], sizeof(ixDPM_TABLE_167)/sizeof(ixDPM_TABLE_167[0]), 0, 0 },
+	{ "ixDPM_TABLE_168", REG_SMC, 0x3f29c, &ixDPM_TABLE_168[0], sizeof(ixDPM_TABLE_168)/sizeof(ixDPM_TABLE_168[0]), 0, 0 },
+	{ "ixDPM_TABLE_169", REG_SMC, 0x3f2a0, &ixDPM_TABLE_169[0], sizeof(ixDPM_TABLE_169)/sizeof(ixDPM_TABLE_169[0]), 0, 0 },
+	{ "ixDPM_TABLE_170", REG_SMC, 0x3f2a4, &ixDPM_TABLE_170[0], sizeof(ixDPM_TABLE_170)/sizeof(ixDPM_TABLE_170[0]), 0, 0 },
+	{ "ixDPM_TABLE_171", REG_SMC, 0x3f2a8, &ixDPM_TABLE_171[0], sizeof(ixDPM_TABLE_171)/sizeof(ixDPM_TABLE_171[0]), 0, 0 },
+	{ "ixDPM_TABLE_172", REG_SMC, 0x3f2ac, &ixDPM_TABLE_172[0], sizeof(ixDPM_TABLE_172)/sizeof(ixDPM_TABLE_172[0]), 0, 0 },
+	{ "ixDPM_TABLE_173", REG_SMC, 0x3f2b0, &ixDPM_TABLE_173[0], sizeof(ixDPM_TABLE_173)/sizeof(ixDPM_TABLE_173[0]), 0, 0 },
+	{ "ixDPM_TABLE_174", REG_SMC, 0x3f2b4, &ixDPM_TABLE_174[0], sizeof(ixDPM_TABLE_174)/sizeof(ixDPM_TABLE_174[0]), 0, 0 },
+	{ "ixDPM_TABLE_175", REG_SMC, 0x3f2b8, &ixDPM_TABLE_175[0], sizeof(ixDPM_TABLE_175)/sizeof(ixDPM_TABLE_175[0]), 0, 0 },
+	{ "ixDPM_TABLE_176", REG_SMC, 0x3f2bc, &ixDPM_TABLE_176[0], sizeof(ixDPM_TABLE_176)/sizeof(ixDPM_TABLE_176[0]), 0, 0 },
+	{ "ixDPM_TABLE_177", REG_SMC, 0x3f2c0, &ixDPM_TABLE_177[0], sizeof(ixDPM_TABLE_177)/sizeof(ixDPM_TABLE_177[0]), 0, 0 },
+	{ "ixDPM_TABLE_178", REG_SMC, 0x3f2c4, &ixDPM_TABLE_178[0], sizeof(ixDPM_TABLE_178)/sizeof(ixDPM_TABLE_178[0]), 0, 0 },
+	{ "ixDPM_TABLE_179", REG_SMC, 0x3f2c8, &ixDPM_TABLE_179[0], sizeof(ixDPM_TABLE_179)/sizeof(ixDPM_TABLE_179[0]), 0, 0 },
+	{ "ixDPM_TABLE_180", REG_SMC, 0x3f2cc, &ixDPM_TABLE_180[0], sizeof(ixDPM_TABLE_180)/sizeof(ixDPM_TABLE_180[0]), 0, 0 },
+	{ "ixDPM_TABLE_181", REG_SMC, 0x3f2d0, &ixDPM_TABLE_181[0], sizeof(ixDPM_TABLE_181)/sizeof(ixDPM_TABLE_181[0]), 0, 0 },
+	{ "ixDPM_TABLE_182", REG_SMC, 0x3f2d4, &ixDPM_TABLE_182[0], sizeof(ixDPM_TABLE_182)/sizeof(ixDPM_TABLE_182[0]), 0, 0 },
+	{ "ixDPM_TABLE_183", REG_SMC, 0x3f2d8, &ixDPM_TABLE_183[0], sizeof(ixDPM_TABLE_183)/sizeof(ixDPM_TABLE_183[0]), 0, 0 },
+	{ "ixDPM_TABLE_184", REG_SMC, 0x3f2dc, &ixDPM_TABLE_184[0], sizeof(ixDPM_TABLE_184)/sizeof(ixDPM_TABLE_184[0]), 0, 0 },
+	{ "ixDPM_TABLE_185", REG_SMC, 0x3f2e0, &ixDPM_TABLE_185[0], sizeof(ixDPM_TABLE_185)/sizeof(ixDPM_TABLE_185[0]), 0, 0 },
+	{ "ixDPM_TABLE_186", REG_SMC, 0x3f2e4, &ixDPM_TABLE_186[0], sizeof(ixDPM_TABLE_186)/sizeof(ixDPM_TABLE_186[0]), 0, 0 },
+	{ "ixDPM_TABLE_187", REG_SMC, 0x3f2e8, &ixDPM_TABLE_187[0], sizeof(ixDPM_TABLE_187)/sizeof(ixDPM_TABLE_187[0]), 0, 0 },
+	{ "ixDPM_TABLE_188", REG_SMC, 0x3f2ec, &ixDPM_TABLE_188[0], sizeof(ixDPM_TABLE_188)/sizeof(ixDPM_TABLE_188[0]), 0, 0 },
+	{ "ixDPM_TABLE_189", REG_SMC, 0x3f2f0, &ixDPM_TABLE_189[0], sizeof(ixDPM_TABLE_189)/sizeof(ixDPM_TABLE_189[0]), 0, 0 },
+	{ "ixDPM_TABLE_190", REG_SMC, 0x3f2f4, &ixDPM_TABLE_190[0], sizeof(ixDPM_TABLE_190)/sizeof(ixDPM_TABLE_190[0]), 0, 0 },
+	{ "ixDPM_TABLE_191", REG_SMC, 0x3f2f8, &ixDPM_TABLE_191[0], sizeof(ixDPM_TABLE_191)/sizeof(ixDPM_TABLE_191[0]), 0, 0 },
+	{ "ixDPM_TABLE_192", REG_SMC, 0x3f2fc, &ixDPM_TABLE_192[0], sizeof(ixDPM_TABLE_192)/sizeof(ixDPM_TABLE_192[0]), 0, 0 },
+	{ "ixDPM_TABLE_193", REG_SMC, 0x3f300, &ixDPM_TABLE_193[0], sizeof(ixDPM_TABLE_193)/sizeof(ixDPM_TABLE_193[0]), 0, 0 },
+	{ "ixDPM_TABLE_194", REG_SMC, 0x3f304, &ixDPM_TABLE_194[0], sizeof(ixDPM_TABLE_194)/sizeof(ixDPM_TABLE_194[0]), 0, 0 },
+	{ "ixDPM_TABLE_195", REG_SMC, 0x3f308, &ixDPM_TABLE_195[0], sizeof(ixDPM_TABLE_195)/sizeof(ixDPM_TABLE_195[0]), 0, 0 },
+	{ "ixDPM_TABLE_196", REG_SMC, 0x3f30c, &ixDPM_TABLE_196[0], sizeof(ixDPM_TABLE_196)/sizeof(ixDPM_TABLE_196[0]), 0, 0 },
+	{ "ixDPM_TABLE_197", REG_SMC, 0x3f310, &ixDPM_TABLE_197[0], sizeof(ixDPM_TABLE_197)/sizeof(ixDPM_TABLE_197[0]), 0, 0 },
+	{ "ixDPM_TABLE_198", REG_SMC, 0x3f314, &ixDPM_TABLE_198[0], sizeof(ixDPM_TABLE_198)/sizeof(ixDPM_TABLE_198[0]), 0, 0 },
+	{ "ixDPM_TABLE_199", REG_SMC, 0x3f318, &ixDPM_TABLE_199[0], sizeof(ixDPM_TABLE_199)/sizeof(ixDPM_TABLE_199[0]), 0, 0 },
+	{ "ixDPM_TABLE_200", REG_SMC, 0x3f31c, &ixDPM_TABLE_200[0], sizeof(ixDPM_TABLE_200)/sizeof(ixDPM_TABLE_200[0]), 0, 0 },
+	{ "ixDPM_TABLE_201", REG_SMC, 0x3f320, &ixDPM_TABLE_201[0], sizeof(ixDPM_TABLE_201)/sizeof(ixDPM_TABLE_201[0]), 0, 0 },
+	{ "ixDPM_TABLE_202", REG_SMC, 0x3f324, &ixDPM_TABLE_202[0], sizeof(ixDPM_TABLE_202)/sizeof(ixDPM_TABLE_202[0]), 0, 0 },
+	{ "ixDPM_TABLE_203", REG_SMC, 0x3f328, &ixDPM_TABLE_203[0], sizeof(ixDPM_TABLE_203)/sizeof(ixDPM_TABLE_203[0]), 0, 0 },
+	{ "ixDPM_TABLE_204", REG_SMC, 0x3f32c, &ixDPM_TABLE_204[0], sizeof(ixDPM_TABLE_204)/sizeof(ixDPM_TABLE_204[0]), 0, 0 },
+	{ "ixDPM_TABLE_205", REG_SMC, 0x3f330, &ixDPM_TABLE_205[0], sizeof(ixDPM_TABLE_205)/sizeof(ixDPM_TABLE_205[0]), 0, 0 },
+	{ "ixDPM_TABLE_206", REG_SMC, 0x3f334, &ixDPM_TABLE_206[0], sizeof(ixDPM_TABLE_206)/sizeof(ixDPM_TABLE_206[0]), 0, 0 },
+	{ "ixDPM_TABLE_207", REG_SMC, 0x3f338, &ixDPM_TABLE_207[0], sizeof(ixDPM_TABLE_207)/sizeof(ixDPM_TABLE_207[0]), 0, 0 },
+	{ "ixDPM_TABLE_208", REG_SMC, 0x3f33c, &ixDPM_TABLE_208[0], sizeof(ixDPM_TABLE_208)/sizeof(ixDPM_TABLE_208[0]), 0, 0 },
+	{ "ixDPM_TABLE_209", REG_SMC, 0x3f340, &ixDPM_TABLE_209[0], sizeof(ixDPM_TABLE_209)/sizeof(ixDPM_TABLE_209[0]), 0, 0 },
+	{ "ixDPM_TABLE_210", REG_SMC, 0x3f344, &ixDPM_TABLE_210[0], sizeof(ixDPM_TABLE_210)/sizeof(ixDPM_TABLE_210[0]), 0, 0 },
+	{ "ixDPM_TABLE_211", REG_SMC, 0x3f348, &ixDPM_TABLE_211[0], sizeof(ixDPM_TABLE_211)/sizeof(ixDPM_TABLE_211[0]), 0, 0 },
+	{ "ixDPM_TABLE_212", REG_SMC, 0x3f34c, &ixDPM_TABLE_212[0], sizeof(ixDPM_TABLE_212)/sizeof(ixDPM_TABLE_212[0]), 0, 0 },
+	{ "ixDPM_TABLE_213", REG_SMC, 0x3f350, &ixDPM_TABLE_213[0], sizeof(ixDPM_TABLE_213)/sizeof(ixDPM_TABLE_213[0]), 0, 0 },
+	{ "ixDPM_TABLE_214", REG_SMC, 0x3f354, &ixDPM_TABLE_214[0], sizeof(ixDPM_TABLE_214)/sizeof(ixDPM_TABLE_214[0]), 0, 0 },
+	{ "ixDPM_TABLE_215", REG_SMC, 0x3f358, &ixDPM_TABLE_215[0], sizeof(ixDPM_TABLE_215)/sizeof(ixDPM_TABLE_215[0]), 0, 0 },
+	{ "ixDPM_TABLE_216", REG_SMC, 0x3f35c, &ixDPM_TABLE_216[0], sizeof(ixDPM_TABLE_216)/sizeof(ixDPM_TABLE_216[0]), 0, 0 },
+	{ "ixDPM_TABLE_217", REG_SMC, 0x3f360, &ixDPM_TABLE_217[0], sizeof(ixDPM_TABLE_217)/sizeof(ixDPM_TABLE_217[0]), 0, 0 },
+	{ "ixDPM_TABLE_218", REG_SMC, 0x3f364, &ixDPM_TABLE_218[0], sizeof(ixDPM_TABLE_218)/sizeof(ixDPM_TABLE_218[0]), 0, 0 },
+	{ "ixDPM_TABLE_219", REG_SMC, 0x3f368, &ixDPM_TABLE_219[0], sizeof(ixDPM_TABLE_219)/sizeof(ixDPM_TABLE_219[0]), 0, 0 },
+	{ "ixDPM_TABLE_220", REG_SMC, 0x3f36c, &ixDPM_TABLE_220[0], sizeof(ixDPM_TABLE_220)/sizeof(ixDPM_TABLE_220[0]), 0, 0 },
+	{ "ixDPM_TABLE_221", REG_SMC, 0x3f370, &ixDPM_TABLE_221[0], sizeof(ixDPM_TABLE_221)/sizeof(ixDPM_TABLE_221[0]), 0, 0 },
+	{ "ixDPM_TABLE_222", REG_SMC, 0x3f374, &ixDPM_TABLE_222[0], sizeof(ixDPM_TABLE_222)/sizeof(ixDPM_TABLE_222[0]), 0, 0 },
+	{ "ixDPM_TABLE_223", REG_SMC, 0x3f378, &ixDPM_TABLE_223[0], sizeof(ixDPM_TABLE_223)/sizeof(ixDPM_TABLE_223[0]), 0, 0 },
+	{ "ixDPM_TABLE_224", REG_SMC, 0x3f37c, &ixDPM_TABLE_224[0], sizeof(ixDPM_TABLE_224)/sizeof(ixDPM_TABLE_224[0]), 0, 0 },
+	{ "ixDPM_TABLE_225", REG_SMC, 0x3f380, &ixDPM_TABLE_225[0], sizeof(ixDPM_TABLE_225)/sizeof(ixDPM_TABLE_225[0]), 0, 0 },
+	{ "ixDPM_TABLE_226", REG_SMC, 0x3f384, &ixDPM_TABLE_226[0], sizeof(ixDPM_TABLE_226)/sizeof(ixDPM_TABLE_226[0]), 0, 0 },
+	{ "ixDPM_TABLE_227", REG_SMC, 0x3f388, &ixDPM_TABLE_227[0], sizeof(ixDPM_TABLE_227)/sizeof(ixDPM_TABLE_227[0]), 0, 0 },
+	{ "ixDPM_TABLE_228", REG_SMC, 0x3f38c, &ixDPM_TABLE_228[0], sizeof(ixDPM_TABLE_228)/sizeof(ixDPM_TABLE_228[0]), 0, 0 },
+	{ "ixDPM_TABLE_229", REG_SMC, 0x3f390, &ixDPM_TABLE_229[0], sizeof(ixDPM_TABLE_229)/sizeof(ixDPM_TABLE_229[0]), 0, 0 },
+	{ "ixDPM_TABLE_230", REG_SMC, 0x3f394, &ixDPM_TABLE_230[0], sizeof(ixDPM_TABLE_230)/sizeof(ixDPM_TABLE_230[0]), 0, 0 },
+	{ "ixDPM_TABLE_231", REG_SMC, 0x3f398, &ixDPM_TABLE_231[0], sizeof(ixDPM_TABLE_231)/sizeof(ixDPM_TABLE_231[0]), 0, 0 },
+	{ "ixDPM_TABLE_232", REG_SMC, 0x3f39c, &ixDPM_TABLE_232[0], sizeof(ixDPM_TABLE_232)/sizeof(ixDPM_TABLE_232[0]), 0, 0 },
+	{ "ixDPM_TABLE_233", REG_SMC, 0x3f3a0, &ixDPM_TABLE_233[0], sizeof(ixDPM_TABLE_233)/sizeof(ixDPM_TABLE_233[0]), 0, 0 },
+	{ "ixDPM_TABLE_234", REG_SMC, 0x3f3a4, &ixDPM_TABLE_234[0], sizeof(ixDPM_TABLE_234)/sizeof(ixDPM_TABLE_234[0]), 0, 0 },
+	{ "ixDPM_TABLE_235", REG_SMC, 0x3f3a8, &ixDPM_TABLE_235[0], sizeof(ixDPM_TABLE_235)/sizeof(ixDPM_TABLE_235[0]), 0, 0 },
+	{ "ixDPM_TABLE_236", REG_SMC, 0x3f3ac, &ixDPM_TABLE_236[0], sizeof(ixDPM_TABLE_236)/sizeof(ixDPM_TABLE_236[0]), 0, 0 },
+	{ "ixDPM_TABLE_237", REG_SMC, 0x3f3b0, &ixDPM_TABLE_237[0], sizeof(ixDPM_TABLE_237)/sizeof(ixDPM_TABLE_237[0]), 0, 0 },
+	{ "ixDPM_TABLE_238", REG_SMC, 0x3f3b4, &ixDPM_TABLE_238[0], sizeof(ixDPM_TABLE_238)/sizeof(ixDPM_TABLE_238[0]), 0, 0 },
+	{ "ixDPM_TABLE_239", REG_SMC, 0x3f3b8, &ixDPM_TABLE_239[0], sizeof(ixDPM_TABLE_239)/sizeof(ixDPM_TABLE_239[0]), 0, 0 },
+	{ "ixDPM_TABLE_240", REG_SMC, 0x3f3bc, &ixDPM_TABLE_240[0], sizeof(ixDPM_TABLE_240)/sizeof(ixDPM_TABLE_240[0]), 0, 0 },
+	{ "ixDPM_TABLE_241", REG_SMC, 0x3f3c0, &ixDPM_TABLE_241[0], sizeof(ixDPM_TABLE_241)/sizeof(ixDPM_TABLE_241[0]), 0, 0 },
+	{ "ixDPM_TABLE_242", REG_SMC, 0x3f3c4, &ixDPM_TABLE_242[0], sizeof(ixDPM_TABLE_242)/sizeof(ixDPM_TABLE_242[0]), 0, 0 },
+	{ "ixDPM_TABLE_243", REG_SMC, 0x3f3c8, &ixDPM_TABLE_243[0], sizeof(ixDPM_TABLE_243)/sizeof(ixDPM_TABLE_243[0]), 0, 0 },
+	{ "ixDPM_TABLE_244", REG_SMC, 0x3f3cc, &ixDPM_TABLE_244[0], sizeof(ixDPM_TABLE_244)/sizeof(ixDPM_TABLE_244[0]), 0, 0 },
+	{ "ixDPM_TABLE_245", REG_SMC, 0x3f3d0, &ixDPM_TABLE_245[0], sizeof(ixDPM_TABLE_245)/sizeof(ixDPM_TABLE_245[0]), 0, 0 },
+	{ "ixDPM_TABLE_246", REG_SMC, 0x3f3d4, &ixDPM_TABLE_246[0], sizeof(ixDPM_TABLE_246)/sizeof(ixDPM_TABLE_246[0]), 0, 0 },
+	{ "ixDPM_TABLE_247", REG_SMC, 0x3f3d8, &ixDPM_TABLE_247[0], sizeof(ixDPM_TABLE_247)/sizeof(ixDPM_TABLE_247[0]), 0, 0 },
+	{ "ixDPM_TABLE_248", REG_SMC, 0x3f3dc, &ixDPM_TABLE_248[0], sizeof(ixDPM_TABLE_248)/sizeof(ixDPM_TABLE_248[0]), 0, 0 },
+	{ "ixDPM_TABLE_249", REG_SMC, 0x3f3e0, &ixDPM_TABLE_249[0], sizeof(ixDPM_TABLE_249)/sizeof(ixDPM_TABLE_249[0]), 0, 0 },
+	{ "ixDPM_TABLE_250", REG_SMC, 0x3f3e4, &ixDPM_TABLE_250[0], sizeof(ixDPM_TABLE_250)/sizeof(ixDPM_TABLE_250[0]), 0, 0 },
+	{ "ixDPM_TABLE_251", REG_SMC, 0x3f3e8, &ixDPM_TABLE_251[0], sizeof(ixDPM_TABLE_251)/sizeof(ixDPM_TABLE_251[0]), 0, 0 },
+	{ "ixDPM_TABLE_252", REG_SMC, 0x3f3ec, &ixDPM_TABLE_252[0], sizeof(ixDPM_TABLE_252)/sizeof(ixDPM_TABLE_252[0]), 0, 0 },
+	{ "ixDPM_TABLE_253", REG_SMC, 0x3f3f0, &ixDPM_TABLE_253[0], sizeof(ixDPM_TABLE_253)/sizeof(ixDPM_TABLE_253[0]), 0, 0 },
+	{ "ixDPM_TABLE_254", REG_SMC, 0x3f3f4, &ixDPM_TABLE_254[0], sizeof(ixDPM_TABLE_254)/sizeof(ixDPM_TABLE_254[0]), 0, 0 },
+	{ "ixDPM_TABLE_255", REG_SMC, 0x3f3f8, &ixDPM_TABLE_255[0], sizeof(ixDPM_TABLE_255)/sizeof(ixDPM_TABLE_255[0]), 0, 0 },
+	{ "ixDPM_TABLE_256", REG_SMC, 0x3f3fc, &ixDPM_TABLE_256[0], sizeof(ixDPM_TABLE_256)/sizeof(ixDPM_TABLE_256[0]), 0, 0 },
+	{ "ixDPM_TABLE_257", REG_SMC, 0x3f400, &ixDPM_TABLE_257[0], sizeof(ixDPM_TABLE_257)/sizeof(ixDPM_TABLE_257[0]), 0, 0 },
+	{ "ixDPM_TABLE_258", REG_SMC, 0x3f404, &ixDPM_TABLE_258[0], sizeof(ixDPM_TABLE_258)/sizeof(ixDPM_TABLE_258[0]), 0, 0 },
+	{ "ixDPM_TABLE_259", REG_SMC, 0x3f408, &ixDPM_TABLE_259[0], sizeof(ixDPM_TABLE_259)/sizeof(ixDPM_TABLE_259[0]), 0, 0 },
+	{ "ixDPM_TABLE_260", REG_SMC, 0x3f40c, &ixDPM_TABLE_260[0], sizeof(ixDPM_TABLE_260)/sizeof(ixDPM_TABLE_260[0]), 0, 0 },
+	{ "ixDPM_TABLE_261", REG_SMC, 0x3f410, &ixDPM_TABLE_261[0], sizeof(ixDPM_TABLE_261)/sizeof(ixDPM_TABLE_261[0]), 0, 0 },
+	{ "ixDPM_TABLE_262", REG_SMC, 0x3f414, &ixDPM_TABLE_262[0], sizeof(ixDPM_TABLE_262)/sizeof(ixDPM_TABLE_262[0]), 0, 0 },
+	{ "ixDPM_TABLE_263", REG_SMC, 0x3f418, &ixDPM_TABLE_263[0], sizeof(ixDPM_TABLE_263)/sizeof(ixDPM_TABLE_263[0]), 0, 0 },
+	{ "ixDPM_TABLE_264", REG_SMC, 0x3f41c, &ixDPM_TABLE_264[0], sizeof(ixDPM_TABLE_264)/sizeof(ixDPM_TABLE_264[0]), 0, 0 },
+	{ "ixDPM_TABLE_265", REG_SMC, 0x3f420, &ixDPM_TABLE_265[0], sizeof(ixDPM_TABLE_265)/sizeof(ixDPM_TABLE_265[0]), 0, 0 },
+	{ "ixDPM_TABLE_266", REG_SMC, 0x3f424, &ixDPM_TABLE_266[0], sizeof(ixDPM_TABLE_266)/sizeof(ixDPM_TABLE_266[0]), 0, 0 },
+	{ "ixDPM_TABLE_267", REG_SMC, 0x3f428, &ixDPM_TABLE_267[0], sizeof(ixDPM_TABLE_267)/sizeof(ixDPM_TABLE_267[0]), 0, 0 },
+	{ "ixDPM_TABLE_268", REG_SMC, 0x3f42c, &ixDPM_TABLE_268[0], sizeof(ixDPM_TABLE_268)/sizeof(ixDPM_TABLE_268[0]), 0, 0 },
+	{ "ixDPM_TABLE_269", REG_SMC, 0x3f430, &ixDPM_TABLE_269[0], sizeof(ixDPM_TABLE_269)/sizeof(ixDPM_TABLE_269[0]), 0, 0 },
+	{ "ixDPM_TABLE_270", REG_SMC, 0x3f434, &ixDPM_TABLE_270[0], sizeof(ixDPM_TABLE_270)/sizeof(ixDPM_TABLE_270[0]), 0, 0 },
+	{ "ixDPM_TABLE_271", REG_SMC, 0x3f438, &ixDPM_TABLE_271[0], sizeof(ixDPM_TABLE_271)/sizeof(ixDPM_TABLE_271[0]), 0, 0 },
+	{ "ixDPM_TABLE_272", REG_SMC, 0x3f43c, &ixDPM_TABLE_272[0], sizeof(ixDPM_TABLE_272)/sizeof(ixDPM_TABLE_272[0]), 0, 0 },
+	{ "ixDPM_TABLE_273", REG_SMC, 0x3f440, &ixDPM_TABLE_273[0], sizeof(ixDPM_TABLE_273)/sizeof(ixDPM_TABLE_273[0]), 0, 0 },
+	{ "ixDPM_TABLE_274", REG_SMC, 0x3f444, &ixDPM_TABLE_274[0], sizeof(ixDPM_TABLE_274)/sizeof(ixDPM_TABLE_274[0]), 0, 0 },
+	{ "ixDPM_TABLE_275", REG_SMC, 0x3f448, &ixDPM_TABLE_275[0], sizeof(ixDPM_TABLE_275)/sizeof(ixDPM_TABLE_275[0]), 0, 0 },
+	{ "ixDPM_TABLE_276", REG_SMC, 0x3f44c, &ixDPM_TABLE_276[0], sizeof(ixDPM_TABLE_276)/sizeof(ixDPM_TABLE_276[0]), 0, 0 },
+	{ "ixDPM_TABLE_277", REG_SMC, 0x3f450, &ixDPM_TABLE_277[0], sizeof(ixDPM_TABLE_277)/sizeof(ixDPM_TABLE_277[0]), 0, 0 },
+	{ "ixDPM_TABLE_278", REG_SMC, 0x3f454, &ixDPM_TABLE_278[0], sizeof(ixDPM_TABLE_278)/sizeof(ixDPM_TABLE_278[0]), 0, 0 },
+	{ "ixDPM_TABLE_279", REG_SMC, 0x3f458, &ixDPM_TABLE_279[0], sizeof(ixDPM_TABLE_279)/sizeof(ixDPM_TABLE_279[0]), 0, 0 },
+	{ "ixDPM_TABLE_280", REG_SMC, 0x3f45c, &ixDPM_TABLE_280[0], sizeof(ixDPM_TABLE_280)/sizeof(ixDPM_TABLE_280[0]), 0, 0 },
+	{ "ixDPM_TABLE_281", REG_SMC, 0x3f460, &ixDPM_TABLE_281[0], sizeof(ixDPM_TABLE_281)/sizeof(ixDPM_TABLE_281[0]), 0, 0 },
+	{ "ixDPM_TABLE_282", REG_SMC, 0x3f464, &ixDPM_TABLE_282[0], sizeof(ixDPM_TABLE_282)/sizeof(ixDPM_TABLE_282[0]), 0, 0 },
+	{ "ixDPM_TABLE_283", REG_SMC, 0x3f468, &ixDPM_TABLE_283[0], sizeof(ixDPM_TABLE_283)/sizeof(ixDPM_TABLE_283[0]), 0, 0 },
+	{ "ixDPM_TABLE_284", REG_SMC, 0x3f46c, &ixDPM_TABLE_284[0], sizeof(ixDPM_TABLE_284)/sizeof(ixDPM_TABLE_284[0]), 0, 0 },
+	{ "ixDPM_TABLE_285", REG_SMC, 0x3f470, &ixDPM_TABLE_285[0], sizeof(ixDPM_TABLE_285)/sizeof(ixDPM_TABLE_285[0]), 0, 0 },
+	{ "ixDPM_TABLE_286", REG_SMC, 0x3f474, &ixDPM_TABLE_286[0], sizeof(ixDPM_TABLE_286)/sizeof(ixDPM_TABLE_286[0]), 0, 0 },
+	{ "ixDPM_TABLE_287", REG_SMC, 0x3f478, &ixDPM_TABLE_287[0], sizeof(ixDPM_TABLE_287)/sizeof(ixDPM_TABLE_287[0]), 0, 0 },
+	{ "ixDPM_TABLE_288", REG_SMC, 0x3f47c, &ixDPM_TABLE_288[0], sizeof(ixDPM_TABLE_288)/sizeof(ixDPM_TABLE_288[0]), 0, 0 },
+	{ "ixDPM_TABLE_289", REG_SMC, 0x3f480, &ixDPM_TABLE_289[0], sizeof(ixDPM_TABLE_289)/sizeof(ixDPM_TABLE_289[0]), 0, 0 },
+	{ "ixDPM_TABLE_290", REG_SMC, 0x3f484, &ixDPM_TABLE_290[0], sizeof(ixDPM_TABLE_290)/sizeof(ixDPM_TABLE_290[0]), 0, 0 },
+	{ "ixDPM_TABLE_291", REG_SMC, 0x3f488, &ixDPM_TABLE_291[0], sizeof(ixDPM_TABLE_291)/sizeof(ixDPM_TABLE_291[0]), 0, 0 },
+	{ "ixDPM_TABLE_292", REG_SMC, 0x3f48c, &ixDPM_TABLE_292[0], sizeof(ixDPM_TABLE_292)/sizeof(ixDPM_TABLE_292[0]), 0, 0 },
+	{ "ixDPM_TABLE_293", REG_SMC, 0x3f490, &ixDPM_TABLE_293[0], sizeof(ixDPM_TABLE_293)/sizeof(ixDPM_TABLE_293[0]), 0, 0 },
+	{ "ixDPM_TABLE_294", REG_SMC, 0x3f494, &ixDPM_TABLE_294[0], sizeof(ixDPM_TABLE_294)/sizeof(ixDPM_TABLE_294[0]), 0, 0 },
+	{ "ixDPM_TABLE_295", REG_SMC, 0x3f498, &ixDPM_TABLE_295[0], sizeof(ixDPM_TABLE_295)/sizeof(ixDPM_TABLE_295[0]), 0, 0 },
+	{ "ixDPM_TABLE_296", REG_SMC, 0x3f49c, &ixDPM_TABLE_296[0], sizeof(ixDPM_TABLE_296)/sizeof(ixDPM_TABLE_296[0]), 0, 0 },
+	{ "ixDPM_TABLE_297", REG_SMC, 0x3f4a0, &ixDPM_TABLE_297[0], sizeof(ixDPM_TABLE_297)/sizeof(ixDPM_TABLE_297[0]), 0, 0 },
+	{ "ixDPM_TABLE_298", REG_SMC, 0x3f4a4, &ixDPM_TABLE_298[0], sizeof(ixDPM_TABLE_298)/sizeof(ixDPM_TABLE_298[0]), 0, 0 },
+	{ "ixDPM_TABLE_299", REG_SMC, 0x3f4a8, &ixDPM_TABLE_299[0], sizeof(ixDPM_TABLE_299)/sizeof(ixDPM_TABLE_299[0]), 0, 0 },
+	{ "ixDPM_TABLE_300", REG_SMC, 0x3f4ac, &ixDPM_TABLE_300[0], sizeof(ixDPM_TABLE_300)/sizeof(ixDPM_TABLE_300[0]), 0, 0 },
+	{ "ixDPM_TABLE_301", REG_SMC, 0x3f4b0, &ixDPM_TABLE_301[0], sizeof(ixDPM_TABLE_301)/sizeof(ixDPM_TABLE_301[0]), 0, 0 },
+	{ "ixDPM_TABLE_302", REG_SMC, 0x3f4b4, &ixDPM_TABLE_302[0], sizeof(ixDPM_TABLE_302)/sizeof(ixDPM_TABLE_302[0]), 0, 0 },
+	{ "ixDPM_TABLE_303", REG_SMC, 0x3f4b8, &ixDPM_TABLE_303[0], sizeof(ixDPM_TABLE_303)/sizeof(ixDPM_TABLE_303[0]), 0, 0 },
+	{ "ixDPM_TABLE_304", REG_SMC, 0x3f4bc, &ixDPM_TABLE_304[0], sizeof(ixDPM_TABLE_304)/sizeof(ixDPM_TABLE_304[0]), 0, 0 },
+	{ "ixDPM_TABLE_305", REG_SMC, 0x3f4c0, &ixDPM_TABLE_305[0], sizeof(ixDPM_TABLE_305)/sizeof(ixDPM_TABLE_305[0]), 0, 0 },
+	{ "ixDPM_TABLE_306", REG_SMC, 0x3f4c4, &ixDPM_TABLE_306[0], sizeof(ixDPM_TABLE_306)/sizeof(ixDPM_TABLE_306[0]), 0, 0 },
+	{ "ixDPM_TABLE_307", REG_SMC, 0x3f4c8, &ixDPM_TABLE_307[0], sizeof(ixDPM_TABLE_307)/sizeof(ixDPM_TABLE_307[0]), 0, 0 },
+	{ "ixDPM_TABLE_308", REG_SMC, 0x3f4cc, &ixDPM_TABLE_308[0], sizeof(ixDPM_TABLE_308)/sizeof(ixDPM_TABLE_308[0]), 0, 0 },
+	{ "ixDPM_TABLE_309", REG_SMC, 0x3f4d0, &ixDPM_TABLE_309[0], sizeof(ixDPM_TABLE_309)/sizeof(ixDPM_TABLE_309[0]), 0, 0 },
+	{ "ixDPM_TABLE_310", REG_SMC, 0x3f4d4, &ixDPM_TABLE_310[0], sizeof(ixDPM_TABLE_310)/sizeof(ixDPM_TABLE_310[0]), 0, 0 },
+	{ "ixDPM_TABLE_311", REG_SMC, 0x3f4d8, &ixDPM_TABLE_311[0], sizeof(ixDPM_TABLE_311)/sizeof(ixDPM_TABLE_311[0]), 0, 0 },
+	{ "ixDPM_TABLE_312", REG_SMC, 0x3f4dc, &ixDPM_TABLE_312[0], sizeof(ixDPM_TABLE_312)/sizeof(ixDPM_TABLE_312[0]), 0, 0 },
+	{ "ixDPM_TABLE_313", REG_SMC, 0x3f4e0, &ixDPM_TABLE_313[0], sizeof(ixDPM_TABLE_313)/sizeof(ixDPM_TABLE_313[0]), 0, 0 },
+	{ "ixDPM_TABLE_314", REG_SMC, 0x3f4e4, &ixDPM_TABLE_314[0], sizeof(ixDPM_TABLE_314)/sizeof(ixDPM_TABLE_314[0]), 0, 0 },
+	{ "ixDPM_TABLE_315", REG_SMC, 0x3f4e8, &ixDPM_TABLE_315[0], sizeof(ixDPM_TABLE_315)/sizeof(ixDPM_TABLE_315[0]), 0, 0 },
+	{ "ixDPM_TABLE_316", REG_SMC, 0x3f4ec, &ixDPM_TABLE_316[0], sizeof(ixDPM_TABLE_316)/sizeof(ixDPM_TABLE_316[0]), 0, 0 },
+	{ "ixDPM_TABLE_317", REG_SMC, 0x3f4f0, &ixDPM_TABLE_317[0], sizeof(ixDPM_TABLE_317)/sizeof(ixDPM_TABLE_317[0]), 0, 0 },
+	{ "ixDPM_TABLE_318", REG_SMC, 0x3f4f4, &ixDPM_TABLE_318[0], sizeof(ixDPM_TABLE_318)/sizeof(ixDPM_TABLE_318[0]), 0, 0 },
+	{ "ixDPM_TABLE_319", REG_SMC, 0x3f4f8, &ixDPM_TABLE_319[0], sizeof(ixDPM_TABLE_319)/sizeof(ixDPM_TABLE_319[0]), 0, 0 },
+	{ "ixDPM_TABLE_320", REG_SMC, 0x3f4fc, &ixDPM_TABLE_320[0], sizeof(ixDPM_TABLE_320)/sizeof(ixDPM_TABLE_320[0]), 0, 0 },
+	{ "ixDPM_TABLE_321", REG_SMC, 0x3f500, &ixDPM_TABLE_321[0], sizeof(ixDPM_TABLE_321)/sizeof(ixDPM_TABLE_321[0]), 0, 0 },
+	{ "ixDPM_TABLE_322", REG_SMC, 0x3f504, &ixDPM_TABLE_322[0], sizeof(ixDPM_TABLE_322)/sizeof(ixDPM_TABLE_322[0]), 0, 0 },
+	{ "ixDPM_TABLE_323", REG_SMC, 0x3f508, &ixDPM_TABLE_323[0], sizeof(ixDPM_TABLE_323)/sizeof(ixDPM_TABLE_323[0]), 0, 0 },
+	{ "ixDPM_TABLE_324", REG_SMC, 0x3f50c, &ixDPM_TABLE_324[0], sizeof(ixDPM_TABLE_324)/sizeof(ixDPM_TABLE_324[0]), 0, 0 },
+	{ "ixDPM_TABLE_325", REG_SMC, 0x3f510, &ixDPM_TABLE_325[0], sizeof(ixDPM_TABLE_325)/sizeof(ixDPM_TABLE_325[0]), 0, 0 },
+	{ "ixDPM_TABLE_326", REG_SMC, 0x3f514, &ixDPM_TABLE_326[0], sizeof(ixDPM_TABLE_326)/sizeof(ixDPM_TABLE_326[0]), 0, 0 },
+	{ "ixDPM_TABLE_327", REG_SMC, 0x3f518, &ixDPM_TABLE_327[0], sizeof(ixDPM_TABLE_327)/sizeof(ixDPM_TABLE_327[0]), 0, 0 },
+	{ "ixDPM_TABLE_328", REG_SMC, 0x3f51c, &ixDPM_TABLE_328[0], sizeof(ixDPM_TABLE_328)/sizeof(ixDPM_TABLE_328[0]), 0, 0 },
+	{ "ixDPM_TABLE_329", REG_SMC, 0x3f520, &ixDPM_TABLE_329[0], sizeof(ixDPM_TABLE_329)/sizeof(ixDPM_TABLE_329[0]), 0, 0 },
+	{ "ixDPM_TABLE_330", REG_SMC, 0x3f524, &ixDPM_TABLE_330[0], sizeof(ixDPM_TABLE_330)/sizeof(ixDPM_TABLE_330[0]), 0, 0 },
+	{ "ixDPM_TABLE_331", REG_SMC, 0x3f528, &ixDPM_TABLE_331[0], sizeof(ixDPM_TABLE_331)/sizeof(ixDPM_TABLE_331[0]), 0, 0 },
+	{ "ixDPM_TABLE_332", REG_SMC, 0x3f52c, &ixDPM_TABLE_332[0], sizeof(ixDPM_TABLE_332)/sizeof(ixDPM_TABLE_332[0]), 0, 0 },
+	{ "ixDPM_TABLE_333", REG_SMC, 0x3f530, &ixDPM_TABLE_333[0], sizeof(ixDPM_TABLE_333)/sizeof(ixDPM_TABLE_333[0]), 0, 0 },
+	{ "ixDPM_TABLE_334", REG_SMC, 0x3f534, &ixDPM_TABLE_334[0], sizeof(ixDPM_TABLE_334)/sizeof(ixDPM_TABLE_334[0]), 0, 0 },
+	{ "ixDPM_TABLE_335", REG_SMC, 0x3f538, &ixDPM_TABLE_335[0], sizeof(ixDPM_TABLE_335)/sizeof(ixDPM_TABLE_335[0]), 0, 0 },
+	{ "ixDPM_TABLE_336", REG_SMC, 0x3f53c, &ixDPM_TABLE_336[0], sizeof(ixDPM_TABLE_336)/sizeof(ixDPM_TABLE_336[0]), 0, 0 },
+	{ "ixDPM_TABLE_337", REG_SMC, 0x3f540, &ixDPM_TABLE_337[0], sizeof(ixDPM_TABLE_337)/sizeof(ixDPM_TABLE_337[0]), 0, 0 },
+	{ "ixDPM_TABLE_338", REG_SMC, 0x3f544, &ixDPM_TABLE_338[0], sizeof(ixDPM_TABLE_338)/sizeof(ixDPM_TABLE_338[0]), 0, 0 },
+	{ "ixDPM_TABLE_339", REG_SMC, 0x3f548, &ixDPM_TABLE_339[0], sizeof(ixDPM_TABLE_339)/sizeof(ixDPM_TABLE_339[0]), 0, 0 },
+	{ "ixDPM_TABLE_340", REG_SMC, 0x3f54c, &ixDPM_TABLE_340[0], sizeof(ixDPM_TABLE_340)/sizeof(ixDPM_TABLE_340[0]), 0, 0 },
+	{ "ixDPM_TABLE_341", REG_SMC, 0x3f550, &ixDPM_TABLE_341[0], sizeof(ixDPM_TABLE_341)/sizeof(ixDPM_TABLE_341[0]), 0, 0 },
+	{ "ixDPM_TABLE_342", REG_SMC, 0x3f554, &ixDPM_TABLE_342[0], sizeof(ixDPM_TABLE_342)/sizeof(ixDPM_TABLE_342[0]), 0, 0 },
+	{ "ixDPM_TABLE_343", REG_SMC, 0x3f558, &ixDPM_TABLE_343[0], sizeof(ixDPM_TABLE_343)/sizeof(ixDPM_TABLE_343[0]), 0, 0 },
+	{ "ixDPM_TABLE_344", REG_SMC, 0x3f55c, &ixDPM_TABLE_344[0], sizeof(ixDPM_TABLE_344)/sizeof(ixDPM_TABLE_344[0]), 0, 0 },
+	{ "ixDPM_TABLE_345", REG_SMC, 0x3f560, &ixDPM_TABLE_345[0], sizeof(ixDPM_TABLE_345)/sizeof(ixDPM_TABLE_345[0]), 0, 0 },
+	{ "ixDPM_TABLE_346", REG_SMC, 0x3f564, &ixDPM_TABLE_346[0], sizeof(ixDPM_TABLE_346)/sizeof(ixDPM_TABLE_346[0]), 0, 0 },
+	{ "ixDPM_TABLE_347", REG_SMC, 0x3f568, &ixDPM_TABLE_347[0], sizeof(ixDPM_TABLE_347)/sizeof(ixDPM_TABLE_347[0]), 0, 0 },
+	{ "ixDPM_TABLE_348", REG_SMC, 0x3f56c, &ixDPM_TABLE_348[0], sizeof(ixDPM_TABLE_348)/sizeof(ixDPM_TABLE_348[0]), 0, 0 },
+	{ "ixDPM_TABLE_349", REG_SMC, 0x3f570, &ixDPM_TABLE_349[0], sizeof(ixDPM_TABLE_349)/sizeof(ixDPM_TABLE_349[0]), 0, 0 },
+	{ "ixDPM_TABLE_350", REG_SMC, 0x3f574, &ixDPM_TABLE_350[0], sizeof(ixDPM_TABLE_350)/sizeof(ixDPM_TABLE_350[0]), 0, 0 },
+	{ "ixDPM_TABLE_351", REG_SMC, 0x3f578, &ixDPM_TABLE_351[0], sizeof(ixDPM_TABLE_351)/sizeof(ixDPM_TABLE_351[0]), 0, 0 },
+	{ "ixDPM_TABLE_352", REG_SMC, 0x3f57c, &ixDPM_TABLE_352[0], sizeof(ixDPM_TABLE_352)/sizeof(ixDPM_TABLE_352[0]), 0, 0 },
+	{ "ixDPM_TABLE_353", REG_SMC, 0x3f580, &ixDPM_TABLE_353[0], sizeof(ixDPM_TABLE_353)/sizeof(ixDPM_TABLE_353[0]), 0, 0 },
+	{ "ixDPM_TABLE_354", REG_SMC, 0x3f584, &ixDPM_TABLE_354[0], sizeof(ixDPM_TABLE_354)/sizeof(ixDPM_TABLE_354[0]), 0, 0 },
+	{ "ixDPM_TABLE_355", REG_SMC, 0x3f588, &ixDPM_TABLE_355[0], sizeof(ixDPM_TABLE_355)/sizeof(ixDPM_TABLE_355[0]), 0, 0 },
+	{ "ixDPM_TABLE_356", REG_SMC, 0x3f58c, &ixDPM_TABLE_356[0], sizeof(ixDPM_TABLE_356)/sizeof(ixDPM_TABLE_356[0]), 0, 0 },
+	{ "ixDPM_TABLE_357", REG_SMC, 0x3f590, &ixDPM_TABLE_357[0], sizeof(ixDPM_TABLE_357)/sizeof(ixDPM_TABLE_357[0]), 0, 0 },
+	{ "ixDPM_TABLE_358", REG_SMC, 0x3f594, &ixDPM_TABLE_358[0], sizeof(ixDPM_TABLE_358)/sizeof(ixDPM_TABLE_358[0]), 0, 0 },
+	{ "ixDPM_TABLE_359", REG_SMC, 0x3f598, &ixDPM_TABLE_359[0], sizeof(ixDPM_TABLE_359)/sizeof(ixDPM_TABLE_359[0]), 0, 0 },
+	{ "ixDPM_TABLE_360", REG_SMC, 0x3f59c, &ixDPM_TABLE_360[0], sizeof(ixDPM_TABLE_360)/sizeof(ixDPM_TABLE_360[0]), 0, 0 },
+	{ "ixDPM_TABLE_361", REG_SMC, 0x3f5a0, &ixDPM_TABLE_361[0], sizeof(ixDPM_TABLE_361)/sizeof(ixDPM_TABLE_361[0]), 0, 0 },
+	{ "ixDPM_TABLE_362", REG_SMC, 0x3f5a4, &ixDPM_TABLE_362[0], sizeof(ixDPM_TABLE_362)/sizeof(ixDPM_TABLE_362[0]), 0, 0 },
+	{ "ixDPM_TABLE_363", REG_SMC, 0x3f5a8, &ixDPM_TABLE_363[0], sizeof(ixDPM_TABLE_363)/sizeof(ixDPM_TABLE_363[0]), 0, 0 },
+	{ "ixDPM_TABLE_364", REG_SMC, 0x3f5ac, &ixDPM_TABLE_364[0], sizeof(ixDPM_TABLE_364)/sizeof(ixDPM_TABLE_364[0]), 0, 0 },
+	{ "ixDPM_TABLE_365", REG_SMC, 0x3f5b0, &ixDPM_TABLE_365[0], sizeof(ixDPM_TABLE_365)/sizeof(ixDPM_TABLE_365[0]), 0, 0 },
+	{ "ixDPM_TABLE_366", REG_SMC, 0x3f5b4, &ixDPM_TABLE_366[0], sizeof(ixDPM_TABLE_366)/sizeof(ixDPM_TABLE_366[0]), 0, 0 },
+	{ "ixDPM_TABLE_367", REG_SMC, 0x3f5b8, &ixDPM_TABLE_367[0], sizeof(ixDPM_TABLE_367)/sizeof(ixDPM_TABLE_367[0]), 0, 0 },
+	{ "ixDPM_TABLE_368", REG_SMC, 0x3f5bc, &ixDPM_TABLE_368[0], sizeof(ixDPM_TABLE_368)/sizeof(ixDPM_TABLE_368[0]), 0, 0 },
+	{ "ixDPM_TABLE_369", REG_SMC, 0x3f5c0, &ixDPM_TABLE_369[0], sizeof(ixDPM_TABLE_369)/sizeof(ixDPM_TABLE_369[0]), 0, 0 },
+	{ "ixDPM_TABLE_370", REG_SMC, 0x3f5c4, &ixDPM_TABLE_370[0], sizeof(ixDPM_TABLE_370)/sizeof(ixDPM_TABLE_370[0]), 0, 0 },
+	{ "ixDPM_TABLE_371", REG_SMC, 0x3f5c8, &ixDPM_TABLE_371[0], sizeof(ixDPM_TABLE_371)/sizeof(ixDPM_TABLE_371[0]), 0, 0 },
+	{ "ixDPM_TABLE_372", REG_SMC, 0x3f5cc, &ixDPM_TABLE_372[0], sizeof(ixDPM_TABLE_372)/sizeof(ixDPM_TABLE_372[0]), 0, 0 },
+	{ "ixDPM_TABLE_373", REG_SMC, 0x3f5d0, &ixDPM_TABLE_373[0], sizeof(ixDPM_TABLE_373)/sizeof(ixDPM_TABLE_373[0]), 0, 0 },
+	{ "ixDPM_TABLE_374", REG_SMC, 0x3f5d4, &ixDPM_TABLE_374[0], sizeof(ixDPM_TABLE_374)/sizeof(ixDPM_TABLE_374[0]), 0, 0 },
+	{ "ixDPM_TABLE_375", REG_SMC, 0x3f5d8, &ixDPM_TABLE_375[0], sizeof(ixDPM_TABLE_375)/sizeof(ixDPM_TABLE_375[0]), 0, 0 },
+	{ "ixDPM_TABLE_376", REG_SMC, 0x3f5dc, &ixDPM_TABLE_376[0], sizeof(ixDPM_TABLE_376)/sizeof(ixDPM_TABLE_376[0]), 0, 0 },
+	{ "ixDPM_TABLE_377", REG_SMC, 0x3f5e0, &ixDPM_TABLE_377[0], sizeof(ixDPM_TABLE_377)/sizeof(ixDPM_TABLE_377[0]), 0, 0 },
+	{ "ixDPM_TABLE_378", REG_SMC, 0x3f5e4, &ixDPM_TABLE_378[0], sizeof(ixDPM_TABLE_378)/sizeof(ixDPM_TABLE_378[0]), 0, 0 },
+	{ "ixDPM_TABLE_379", REG_SMC, 0x3f5e8, &ixDPM_TABLE_379[0], sizeof(ixDPM_TABLE_379)/sizeof(ixDPM_TABLE_379[0]), 0, 0 },
+	{ "ixDPM_TABLE_380", REG_SMC, 0x3f5ec, &ixDPM_TABLE_380[0], sizeof(ixDPM_TABLE_380)/sizeof(ixDPM_TABLE_380[0]), 0, 0 },
+	{ "ixDPM_TABLE_381", REG_SMC, 0x3f5f0, &ixDPM_TABLE_381[0], sizeof(ixDPM_TABLE_381)/sizeof(ixDPM_TABLE_381[0]), 0, 0 },
+	{ "ixDPM_TABLE_382", REG_SMC, 0x3f5f4, &ixDPM_TABLE_382[0], sizeof(ixDPM_TABLE_382)/sizeof(ixDPM_TABLE_382[0]), 0, 0 },
+	{ "ixDPM_TABLE_383", REG_SMC, 0x3f5f8, &ixDPM_TABLE_383[0], sizeof(ixDPM_TABLE_383)/sizeof(ixDPM_TABLE_383[0]), 0, 0 },
+	{ "ixDPM_TABLE_384", REG_SMC, 0x3f5fc, &ixDPM_TABLE_384[0], sizeof(ixDPM_TABLE_384)/sizeof(ixDPM_TABLE_384[0]), 0, 0 },
+	{ "ixDPM_TABLE_385", REG_SMC, 0x3f600, &ixDPM_TABLE_385[0], sizeof(ixDPM_TABLE_385)/sizeof(ixDPM_TABLE_385[0]), 0, 0 },
+	{ "ixDPM_TABLE_386", REG_SMC, 0x3f604, &ixDPM_TABLE_386[0], sizeof(ixDPM_TABLE_386)/sizeof(ixDPM_TABLE_386[0]), 0, 0 },
+	{ "ixDPM_TABLE_387", REG_SMC, 0x3f608, &ixDPM_TABLE_387[0], sizeof(ixDPM_TABLE_387)/sizeof(ixDPM_TABLE_387[0]), 0, 0 },
+	{ "ixDPM_TABLE_388", REG_SMC, 0x3f60c, &ixDPM_TABLE_388[0], sizeof(ixDPM_TABLE_388)/sizeof(ixDPM_TABLE_388[0]), 0, 0 },
+	{ "ixDPM_TABLE_389", REG_SMC, 0x3f610, &ixDPM_TABLE_389[0], sizeof(ixDPM_TABLE_389)/sizeof(ixDPM_TABLE_389[0]), 0, 0 },
+	{ "ixDPM_TABLE_390", REG_SMC, 0x3f614, &ixDPM_TABLE_390[0], sizeof(ixDPM_TABLE_390)/sizeof(ixDPM_TABLE_390[0]), 0, 0 },
+	{ "ixDPM_TABLE_391", REG_SMC, 0x3f618, &ixDPM_TABLE_391[0], sizeof(ixDPM_TABLE_391)/sizeof(ixDPM_TABLE_391[0]), 0, 0 },
+	{ "ixDPM_TABLE_392", REG_SMC, 0x3f61c, &ixDPM_TABLE_392[0], sizeof(ixDPM_TABLE_392)/sizeof(ixDPM_TABLE_392[0]), 0, 0 },
+	{ "ixDPM_TABLE_393", REG_SMC, 0x3f620, &ixDPM_TABLE_393[0], sizeof(ixDPM_TABLE_393)/sizeof(ixDPM_TABLE_393[0]), 0, 0 },
+	{ "ixDPM_TABLE_394", REG_SMC, 0x3f624, &ixDPM_TABLE_394[0], sizeof(ixDPM_TABLE_394)/sizeof(ixDPM_TABLE_394[0]), 0, 0 },
+	{ "ixDPM_TABLE_395", REG_SMC, 0x3f628, &ixDPM_TABLE_395[0], sizeof(ixDPM_TABLE_395)/sizeof(ixDPM_TABLE_395[0]), 0, 0 },
+	{ "ixDPM_TABLE_396", REG_SMC, 0x3f62c, &ixDPM_TABLE_396[0], sizeof(ixDPM_TABLE_396)/sizeof(ixDPM_TABLE_396[0]), 0, 0 },
+	{ "ixDPM_TABLE_397", REG_SMC, 0x3f630, &ixDPM_TABLE_397[0], sizeof(ixDPM_TABLE_397)/sizeof(ixDPM_TABLE_397[0]), 0, 0 },
+	{ "ixDPM_TABLE_398", REG_SMC, 0x3f634, &ixDPM_TABLE_398[0], sizeof(ixDPM_TABLE_398)/sizeof(ixDPM_TABLE_398[0]), 0, 0 },
+	{ "ixDPM_TABLE_399", REG_SMC, 0x3f638, &ixDPM_TABLE_399[0], sizeof(ixDPM_TABLE_399)/sizeof(ixDPM_TABLE_399[0]), 0, 0 },
+	{ "ixDPM_TABLE_400", REG_SMC, 0x3f63c, &ixDPM_TABLE_400[0], sizeof(ixDPM_TABLE_400)/sizeof(ixDPM_TABLE_400[0]), 0, 0 },
+	{ "ixDPM_TABLE_401", REG_SMC, 0x3f640, &ixDPM_TABLE_401[0], sizeof(ixDPM_TABLE_401)/sizeof(ixDPM_TABLE_401[0]), 0, 0 },
+	{ "ixDPM_TABLE_402", REG_SMC, 0x3f644, &ixDPM_TABLE_402[0], sizeof(ixDPM_TABLE_402)/sizeof(ixDPM_TABLE_402[0]), 0, 0 },
+	{ "ixDPM_TABLE_403", REG_SMC, 0x3f648, &ixDPM_TABLE_403[0], sizeof(ixDPM_TABLE_403)/sizeof(ixDPM_TABLE_403[0]), 0, 0 },
+	{ "ixDPM_TABLE_404", REG_SMC, 0x3f64c, &ixDPM_TABLE_404[0], sizeof(ixDPM_TABLE_404)/sizeof(ixDPM_TABLE_404[0]), 0, 0 },
+	{ "ixDPM_TABLE_405", REG_SMC, 0x3f650, &ixDPM_TABLE_405[0], sizeof(ixDPM_TABLE_405)/sizeof(ixDPM_TABLE_405[0]), 0, 0 },
+	{ "ixDPM_TABLE_406", REG_SMC, 0x3f654, &ixDPM_TABLE_406[0], sizeof(ixDPM_TABLE_406)/sizeof(ixDPM_TABLE_406[0]), 0, 0 },
+	{ "ixDPM_TABLE_407", REG_SMC, 0x3f658, &ixDPM_TABLE_407[0], sizeof(ixDPM_TABLE_407)/sizeof(ixDPM_TABLE_407[0]), 0, 0 },
+	{ "ixDPM_TABLE_408", REG_SMC, 0x3f65c, &ixDPM_TABLE_408[0], sizeof(ixDPM_TABLE_408)/sizeof(ixDPM_TABLE_408[0]), 0, 0 },
+	{ "ixDPM_TABLE_409", REG_SMC, 0x3f660, &ixDPM_TABLE_409[0], sizeof(ixDPM_TABLE_409)/sizeof(ixDPM_TABLE_409[0]), 0, 0 },
+	{ "ixDPM_TABLE_410", REG_SMC, 0x3f664, &ixDPM_TABLE_410[0], sizeof(ixDPM_TABLE_410)/sizeof(ixDPM_TABLE_410[0]), 0, 0 },
+	{ "ixDPM_TABLE_411", REG_SMC, 0x3f668, &ixDPM_TABLE_411[0], sizeof(ixDPM_TABLE_411)/sizeof(ixDPM_TABLE_411[0]), 0, 0 },
+	{ "ixDPM_TABLE_412", REG_SMC, 0x3f66c, &ixDPM_TABLE_412[0], sizeof(ixDPM_TABLE_412)/sizeof(ixDPM_TABLE_412[0]), 0, 0 },
+	{ "ixDPM_TABLE_413", REG_SMC, 0x3f670, &ixDPM_TABLE_413[0], sizeof(ixDPM_TABLE_413)/sizeof(ixDPM_TABLE_413[0]), 0, 0 },
+	{ "ixDPM_TABLE_414", REG_SMC, 0x3f674, &ixDPM_TABLE_414[0], sizeof(ixDPM_TABLE_414)/sizeof(ixDPM_TABLE_414[0]), 0, 0 },
+	{ "ixDPM_TABLE_415", REG_SMC, 0x3f678, &ixDPM_TABLE_415[0], sizeof(ixDPM_TABLE_415)/sizeof(ixDPM_TABLE_415[0]), 0, 0 },
+	{ "ixDPM_TABLE_416", REG_SMC, 0x3f67c, &ixDPM_TABLE_416[0], sizeof(ixDPM_TABLE_416)/sizeof(ixDPM_TABLE_416[0]), 0, 0 },
+	{ "ixDPM_TABLE_417", REG_SMC, 0x3f680, &ixDPM_TABLE_417[0], sizeof(ixDPM_TABLE_417)/sizeof(ixDPM_TABLE_417[0]), 0, 0 },
+	{ "ixDPM_TABLE_418", REG_SMC, 0x3f684, &ixDPM_TABLE_418[0], sizeof(ixDPM_TABLE_418)/sizeof(ixDPM_TABLE_418[0]), 0, 0 },
+	{ "ixDPM_TABLE_419", REG_SMC, 0x3f688, &ixDPM_TABLE_419[0], sizeof(ixDPM_TABLE_419)/sizeof(ixDPM_TABLE_419[0]), 0, 0 },
+	{ "ixDPM_TABLE_420", REG_SMC, 0x3f68c, &ixDPM_TABLE_420[0], sizeof(ixDPM_TABLE_420)/sizeof(ixDPM_TABLE_420[0]), 0, 0 },
+	{ "ixDPM_TABLE_421", REG_SMC, 0x3f690, &ixDPM_TABLE_421[0], sizeof(ixDPM_TABLE_421)/sizeof(ixDPM_TABLE_421[0]), 0, 0 },
+	{ "ixDPM_TABLE_422", REG_SMC, 0x3f694, &ixDPM_TABLE_422[0], sizeof(ixDPM_TABLE_422)/sizeof(ixDPM_TABLE_422[0]), 0, 0 },
+	{ "ixDPM_TABLE_423", REG_SMC, 0x3f698, &ixDPM_TABLE_423[0], sizeof(ixDPM_TABLE_423)/sizeof(ixDPM_TABLE_423[0]), 0, 0 },
+	{ "ixDPM_TABLE_424", REG_SMC, 0x3f69c, &ixDPM_TABLE_424[0], sizeof(ixDPM_TABLE_424)/sizeof(ixDPM_TABLE_424[0]), 0, 0 },
+	{ "ixDPM_TABLE_425", REG_SMC, 0x3f6a0, &ixDPM_TABLE_425[0], sizeof(ixDPM_TABLE_425)/sizeof(ixDPM_TABLE_425[0]), 0, 0 },
+	{ "ixDPM_TABLE_426", REG_SMC, 0x3f6a4, &ixDPM_TABLE_426[0], sizeof(ixDPM_TABLE_426)/sizeof(ixDPM_TABLE_426[0]), 0, 0 },
+	{ "ixDPM_TABLE_427", REG_SMC, 0x3f6a8, &ixDPM_TABLE_427[0], sizeof(ixDPM_TABLE_427)/sizeof(ixDPM_TABLE_427[0]), 0, 0 },
+	{ "ixDPM_TABLE_428", REG_SMC, 0x3f6ac, &ixDPM_TABLE_428[0], sizeof(ixDPM_TABLE_428)/sizeof(ixDPM_TABLE_428[0]), 0, 0 },
+	{ "ixDPM_TABLE_429", REG_SMC, 0x3f6b0, &ixDPM_TABLE_429[0], sizeof(ixDPM_TABLE_429)/sizeof(ixDPM_TABLE_429[0]), 0, 0 },
+	{ "ixDPM_TABLE_430", REG_SMC, 0x3f6b4, &ixDPM_TABLE_430[0], sizeof(ixDPM_TABLE_430)/sizeof(ixDPM_TABLE_430[0]), 0, 0 },
+	{ "ixDPM_TABLE_431", REG_SMC, 0x3f6b8, &ixDPM_TABLE_431[0], sizeof(ixDPM_TABLE_431)/sizeof(ixDPM_TABLE_431[0]), 0, 0 },
+	{ "ixDPM_TABLE_432", REG_SMC, 0x3f6bc, &ixDPM_TABLE_432[0], sizeof(ixDPM_TABLE_432)/sizeof(ixDPM_TABLE_432[0]), 0, 0 },
+	{ "ixDPM_TABLE_433", REG_SMC, 0x3f6c0, &ixDPM_TABLE_433[0], sizeof(ixDPM_TABLE_433)/sizeof(ixDPM_TABLE_433[0]), 0, 0 },
+	{ "ixDPM_TABLE_434", REG_SMC, 0x3f6c4, &ixDPM_TABLE_434[0], sizeof(ixDPM_TABLE_434)/sizeof(ixDPM_TABLE_434[0]), 0, 0 },
+	{ "ixDPM_TABLE_435", REG_SMC, 0x3f6c8, &ixDPM_TABLE_435[0], sizeof(ixDPM_TABLE_435)/sizeof(ixDPM_TABLE_435[0]), 0, 0 },
+	{ "ixDPM_TABLE_436", REG_SMC, 0x3f6cc, &ixDPM_TABLE_436[0], sizeof(ixDPM_TABLE_436)/sizeof(ixDPM_TABLE_436[0]), 0, 0 },
+	{ "ixDPM_TABLE_437", REG_SMC, 0x3f6d0, &ixDPM_TABLE_437[0], sizeof(ixDPM_TABLE_437)/sizeof(ixDPM_TABLE_437[0]), 0, 0 },
+	{ "ixDPM_TABLE_438", REG_SMC, 0x3f6d4, &ixDPM_TABLE_438[0], sizeof(ixDPM_TABLE_438)/sizeof(ixDPM_TABLE_438[0]), 0, 0 },
+	{ "ixDPM_TABLE_439", REG_SMC, 0x3f6d8, &ixDPM_TABLE_439[0], sizeof(ixDPM_TABLE_439)/sizeof(ixDPM_TABLE_439[0]), 0, 0 },
+	{ "ixDPM_TABLE_440", REG_SMC, 0x3f6dc, &ixDPM_TABLE_440[0], sizeof(ixDPM_TABLE_440)/sizeof(ixDPM_TABLE_440[0]), 0, 0 },
+	{ "ixDPM_TABLE_441", REG_SMC, 0x3f6e0, &ixDPM_TABLE_441[0], sizeof(ixDPM_TABLE_441)/sizeof(ixDPM_TABLE_441[0]), 0, 0 },
+	{ "ixDPM_TABLE_442", REG_SMC, 0x3f6e4, &ixDPM_TABLE_442[0], sizeof(ixDPM_TABLE_442)/sizeof(ixDPM_TABLE_442[0]), 0, 0 },
+	{ "ixDPM_TABLE_443", REG_SMC, 0x3f6e8, &ixDPM_TABLE_443[0], sizeof(ixDPM_TABLE_443)/sizeof(ixDPM_TABLE_443[0]), 0, 0 },
+	{ "ixDPM_TABLE_444", REG_SMC, 0x3f6ec, &ixDPM_TABLE_444[0], sizeof(ixDPM_TABLE_444)/sizeof(ixDPM_TABLE_444[0]), 0, 0 },
+	{ "ixDPM_TABLE_445", REG_SMC, 0x3f6f0, &ixDPM_TABLE_445[0], sizeof(ixDPM_TABLE_445)/sizeof(ixDPM_TABLE_445[0]), 0, 0 },
+	{ "ixDPM_TABLE_446", REG_SMC, 0x3f6f4, &ixDPM_TABLE_446[0], sizeof(ixDPM_TABLE_446)/sizeof(ixDPM_TABLE_446[0]), 0, 0 },
+	{ "ixDPM_TABLE_447", REG_SMC, 0x3f6f8, &ixDPM_TABLE_447[0], sizeof(ixDPM_TABLE_447)/sizeof(ixDPM_TABLE_447[0]), 0, 0 },
+	{ "ixDPM_TABLE_448", REG_SMC, 0x3f6fc, &ixDPM_TABLE_448[0], sizeof(ixDPM_TABLE_448)/sizeof(ixDPM_TABLE_448[0]), 0, 0 },
+	{ "ixDPM_TABLE_449", REG_SMC, 0x3f700, &ixDPM_TABLE_449[0], sizeof(ixDPM_TABLE_449)/sizeof(ixDPM_TABLE_449[0]), 0, 0 },
+	{ "ixDPM_TABLE_450", REG_SMC, 0x3f704, &ixDPM_TABLE_450[0], sizeof(ixDPM_TABLE_450)/sizeof(ixDPM_TABLE_450[0]), 0, 0 },
+	{ "ixDPM_TABLE_451", REG_SMC, 0x3f708, &ixDPM_TABLE_451[0], sizeof(ixDPM_TABLE_451)/sizeof(ixDPM_TABLE_451[0]), 0, 0 },
+	{ "ixDPM_TABLE_452", REG_SMC, 0x3f70c, &ixDPM_TABLE_452[0], sizeof(ixDPM_TABLE_452)/sizeof(ixDPM_TABLE_452[0]), 0, 0 },
+	{ "ixDPM_TABLE_453", REG_SMC, 0x3f710, &ixDPM_TABLE_453[0], sizeof(ixDPM_TABLE_453)/sizeof(ixDPM_TABLE_453[0]), 0, 0 },
+	{ "ixDPM_TABLE_454", REG_SMC, 0x3f714, &ixDPM_TABLE_454[0], sizeof(ixDPM_TABLE_454)/sizeof(ixDPM_TABLE_454[0]), 0, 0 },
+	{ "ixDPM_TABLE_455", REG_SMC, 0x3f718, &ixDPM_TABLE_455[0], sizeof(ixDPM_TABLE_455)/sizeof(ixDPM_TABLE_455[0]), 0, 0 },
+	{ "ixDPM_TABLE_456", REG_SMC, 0x3f71c, &ixDPM_TABLE_456[0], sizeof(ixDPM_TABLE_456)/sizeof(ixDPM_TABLE_456[0]), 0, 0 },
+	{ "ixDPM_TABLE_457", REG_SMC, 0x3f720, &ixDPM_TABLE_457[0], sizeof(ixDPM_TABLE_457)/sizeof(ixDPM_TABLE_457[0]), 0, 0 },
+	{ "ixDPM_TABLE_458", REG_SMC, 0x3f724, &ixDPM_TABLE_458[0], sizeof(ixDPM_TABLE_458)/sizeof(ixDPM_TABLE_458[0]), 0, 0 },
+	{ "ixDPM_TABLE_459", REG_SMC, 0x3f728, &ixDPM_TABLE_459[0], sizeof(ixDPM_TABLE_459)/sizeof(ixDPM_TABLE_459[0]), 0, 0 },
+	{ "ixDPM_TABLE_460", REG_SMC, 0x3f72c, &ixDPM_TABLE_460[0], sizeof(ixDPM_TABLE_460)/sizeof(ixDPM_TABLE_460[0]), 0, 0 },
+	{ "ixDPM_TABLE_461", REG_SMC, 0x3f730, &ixDPM_TABLE_461[0], sizeof(ixDPM_TABLE_461)/sizeof(ixDPM_TABLE_461[0]), 0, 0 },
+	{ "ixDPM_TABLE_462", REG_SMC, 0x3f734, &ixDPM_TABLE_462[0], sizeof(ixDPM_TABLE_462)/sizeof(ixDPM_TABLE_462[0]), 0, 0 },
+	{ "ixDPM_TABLE_463", REG_SMC, 0x3f738, &ixDPM_TABLE_463[0], sizeof(ixDPM_TABLE_463)/sizeof(ixDPM_TABLE_463[0]), 0, 0 },
+	{ "ixDPM_TABLE_464", REG_SMC, 0x3f73c, &ixDPM_TABLE_464[0], sizeof(ixDPM_TABLE_464)/sizeof(ixDPM_TABLE_464[0]), 0, 0 },
+	{ "ixDPM_TABLE_465", REG_SMC, 0x3f740, &ixDPM_TABLE_465[0], sizeof(ixDPM_TABLE_465)/sizeof(ixDPM_TABLE_465[0]), 0, 0 },
+	{ "ixDPM_TABLE_466", REG_SMC, 0x3f744, &ixDPM_TABLE_466[0], sizeof(ixDPM_TABLE_466)/sizeof(ixDPM_TABLE_466[0]), 0, 0 },
+	{ "ixDPM_TABLE_467", REG_SMC, 0x3f748, &ixDPM_TABLE_467[0], sizeof(ixDPM_TABLE_467)/sizeof(ixDPM_TABLE_467[0]), 0, 0 },
+	{ "ixDPM_TABLE_468", REG_SMC, 0x3f74c, &ixDPM_TABLE_468[0], sizeof(ixDPM_TABLE_468)/sizeof(ixDPM_TABLE_468[0]), 0, 0 },
+	{ "ixDPM_TABLE_469", REG_SMC, 0x3f750, &ixDPM_TABLE_469[0], sizeof(ixDPM_TABLE_469)/sizeof(ixDPM_TABLE_469[0]), 0, 0 },
+	{ "ixDPM_TABLE_470", REG_SMC, 0x3f754, &ixDPM_TABLE_470[0], sizeof(ixDPM_TABLE_470)/sizeof(ixDPM_TABLE_470[0]), 0, 0 },
+	{ "ixDPM_TABLE_471", REG_SMC, 0x3f758, &ixDPM_TABLE_471[0], sizeof(ixDPM_TABLE_471)/sizeof(ixDPM_TABLE_471[0]), 0, 0 },
+	{ "ixDPM_TABLE_472", REG_SMC, 0x3f75c, &ixDPM_TABLE_472[0], sizeof(ixDPM_TABLE_472)/sizeof(ixDPM_TABLE_472[0]), 0, 0 },
+	{ "ixDPM_TABLE_473", REG_SMC, 0x3f760, &ixDPM_TABLE_473[0], sizeof(ixDPM_TABLE_473)/sizeof(ixDPM_TABLE_473[0]), 0, 0 },
+	{ "ixDPM_TABLE_474", REG_SMC, 0x3f764, &ixDPM_TABLE_474[0], sizeof(ixDPM_TABLE_474)/sizeof(ixDPM_TABLE_474[0]), 0, 0 },
+	{ "ixDPM_TABLE_475", REG_SMC, 0x3f768, &ixDPM_TABLE_475[0], sizeof(ixDPM_TABLE_475)/sizeof(ixDPM_TABLE_475[0]), 0, 0 },
+	{ "ixDPM_TABLE_476", REG_SMC, 0x3f76c, &ixDPM_TABLE_476[0], sizeof(ixDPM_TABLE_476)/sizeof(ixDPM_TABLE_476[0]), 0, 0 },
+	{ "ixDPM_TABLE_477", REG_SMC, 0x3f770, &ixDPM_TABLE_477[0], sizeof(ixDPM_TABLE_477)/sizeof(ixDPM_TABLE_477[0]), 0, 0 },
+	{ "ixDPM_TABLE_478", REG_SMC, 0x3f774, &ixDPM_TABLE_478[0], sizeof(ixDPM_TABLE_478)/sizeof(ixDPM_TABLE_478[0]), 0, 0 },
+	{ "ixDPM_TABLE_479", REG_SMC, 0x3f778, &ixDPM_TABLE_479[0], sizeof(ixDPM_TABLE_479)/sizeof(ixDPM_TABLE_479[0]), 0, 0 },
+	{ "ixDPM_TABLE_480", REG_SMC, 0x3f77c, &ixDPM_TABLE_480[0], sizeof(ixDPM_TABLE_480)/sizeof(ixDPM_TABLE_480[0]), 0, 0 },
+	{ "ixDPM_TABLE_481", REG_SMC, 0x3f780, &ixDPM_TABLE_481[0], sizeof(ixDPM_TABLE_481)/sizeof(ixDPM_TABLE_481[0]), 0, 0 },
+	{ "ixDPM_TABLE_482", REG_SMC, 0x3f784, &ixDPM_TABLE_482[0], sizeof(ixDPM_TABLE_482)/sizeof(ixDPM_TABLE_482[0]), 0, 0 },
+	{ "ixDPM_TABLE_483", REG_SMC, 0x3f788, &ixDPM_TABLE_483[0], sizeof(ixDPM_TABLE_483)/sizeof(ixDPM_TABLE_483[0]), 0, 0 },
+	{ "ixDPM_TABLE_484", REG_SMC, 0x3f78c, &ixDPM_TABLE_484[0], sizeof(ixDPM_TABLE_484)/sizeof(ixDPM_TABLE_484[0]), 0, 0 },
+	{ "ixDPM_TABLE_485", REG_SMC, 0x3f790, &ixDPM_TABLE_485[0], sizeof(ixDPM_TABLE_485)/sizeof(ixDPM_TABLE_485[0]), 0, 0 },
+	{ "ixDPM_TABLE_486", REG_SMC, 0x3f794, &ixDPM_TABLE_486[0], sizeof(ixDPM_TABLE_486)/sizeof(ixDPM_TABLE_486[0]), 0, 0 },
+	{ "ixDPM_TABLE_487", REG_SMC, 0x3f798, &ixDPM_TABLE_487[0], sizeof(ixDPM_TABLE_487)/sizeof(ixDPM_TABLE_487[0]), 0, 0 },
+	{ "ixDPM_TABLE_488", REG_SMC, 0x3f79c, &ixDPM_TABLE_488[0], sizeof(ixDPM_TABLE_488)/sizeof(ixDPM_TABLE_488[0]), 0, 0 },
+	{ "ixDPM_TABLE_489", REG_SMC, 0x3f7a0, &ixDPM_TABLE_489[0], sizeof(ixDPM_TABLE_489)/sizeof(ixDPM_TABLE_489[0]), 0, 0 },
+	{ "ixDPM_TABLE_490", REG_SMC, 0x3f7a4, &ixDPM_TABLE_490[0], sizeof(ixDPM_TABLE_490)/sizeof(ixDPM_TABLE_490[0]), 0, 0 },
+	{ "ixDPM_TABLE_491", REG_SMC, 0x3f7a8, &ixDPM_TABLE_491[0], sizeof(ixDPM_TABLE_491)/sizeof(ixDPM_TABLE_491[0]), 0, 0 },
+	{ "ixDPM_TABLE_492", REG_SMC, 0x3f7ac, &ixDPM_TABLE_492[0], sizeof(ixDPM_TABLE_492)/sizeof(ixDPM_TABLE_492[0]), 0, 0 },
+	{ "ixDPM_TABLE_493", REG_SMC, 0x3f7b0, &ixDPM_TABLE_493[0], sizeof(ixDPM_TABLE_493)/sizeof(ixDPM_TABLE_493[0]), 0, 0 },
+	{ "ixDPM_TABLE_494", REG_SMC, 0x3f7b4, &ixDPM_TABLE_494[0], sizeof(ixDPM_TABLE_494)/sizeof(ixDPM_TABLE_494[0]), 0, 0 },
+	{ "ixDPM_TABLE_495", REG_SMC, 0x3f7b8, &ixDPM_TABLE_495[0], sizeof(ixDPM_TABLE_495)/sizeof(ixDPM_TABLE_495[0]), 0, 0 },
+	{ "ixDPM_TABLE_496", REG_SMC, 0x3f7bc, &ixDPM_TABLE_496[0], sizeof(ixDPM_TABLE_496)/sizeof(ixDPM_TABLE_496[0]), 0, 0 },
+	{ "ixDPM_TABLE_497", REG_SMC, 0x3f7c0, &ixDPM_TABLE_497[0], sizeof(ixDPM_TABLE_497)/sizeof(ixDPM_TABLE_497[0]), 0, 0 },
+	{ "ixDPM_TABLE_498", REG_SMC, 0x3f7c4, &ixDPM_TABLE_498[0], sizeof(ixDPM_TABLE_498)/sizeof(ixDPM_TABLE_498[0]), 0, 0 },
+	{ "ixDPM_TABLE_499", REG_SMC, 0x3f7c8, &ixDPM_TABLE_499[0], sizeof(ixDPM_TABLE_499)/sizeof(ixDPM_TABLE_499[0]), 0, 0 },
+	{ "ixDPM_TABLE_500", REG_SMC, 0x3f7cc, &ixDPM_TABLE_500[0], sizeof(ixDPM_TABLE_500)/sizeof(ixDPM_TABLE_500[0]), 0, 0 },
+	{ "ixDPM_TABLE_501", REG_SMC, 0x3f7d0, &ixDPM_TABLE_501[0], sizeof(ixDPM_TABLE_501)/sizeof(ixDPM_TABLE_501[0]), 0, 0 },
+	{ "ixDPM_TABLE_502", REG_SMC, 0x3f7d4, &ixDPM_TABLE_502[0], sizeof(ixDPM_TABLE_502)/sizeof(ixDPM_TABLE_502[0]), 0, 0 },
+	{ "ixDPM_TABLE_503", REG_SMC, 0x3f7d8, &ixDPM_TABLE_503[0], sizeof(ixDPM_TABLE_503)/sizeof(ixDPM_TABLE_503[0]), 0, 0 },
+	{ "ixDPM_TABLE_504", REG_SMC, 0x3f7dc, &ixDPM_TABLE_504[0], sizeof(ixDPM_TABLE_504)/sizeof(ixDPM_TABLE_504[0]), 0, 0 },
+	{ "ixDPM_TABLE_505", REG_SMC, 0x3f7e0, &ixDPM_TABLE_505[0], sizeof(ixDPM_TABLE_505)/sizeof(ixDPM_TABLE_505[0]), 0, 0 },
+	{ "ixDPM_TABLE_506", REG_SMC, 0x3f7e4, &ixDPM_TABLE_506[0], sizeof(ixDPM_TABLE_506)/sizeof(ixDPM_TABLE_506[0]), 0, 0 },
+	{ "ixDPM_TABLE_507", REG_SMC, 0x3f7e8, &ixDPM_TABLE_507[0], sizeof(ixDPM_TABLE_507)/sizeof(ixDPM_TABLE_507[0]), 0, 0 },
+	{ "ixDPM_TABLE_508", REG_SMC, 0x3f7ec, &ixDPM_TABLE_508[0], sizeof(ixDPM_TABLE_508)/sizeof(ixDPM_TABLE_508[0]), 0, 0 },
+	{ "ixDPM_TABLE_509", REG_SMC, 0x3f7f0, &ixDPM_TABLE_509[0], sizeof(ixDPM_TABLE_509)/sizeof(ixDPM_TABLE_509[0]), 0, 0 },
+	{ "ixDPM_TABLE_510", REG_SMC, 0x3f7f4, &ixDPM_TABLE_510[0], sizeof(ixDPM_TABLE_510)/sizeof(ixDPM_TABLE_510[0]), 0, 0 },
+	{ "ixFIRMWARE_FLAGS", REG_SMC, 0x3f800, &ixFIRMWARE_FLAGS[0], sizeof(ixFIRMWARE_FLAGS)/sizeof(ixFIRMWARE_FLAGS[0]), 0, 0 },
+	{ "ixTDC_STATUS", REG_SMC, 0x3f808, &ixTDC_STATUS[0], sizeof(ixTDC_STATUS)/sizeof(ixTDC_STATUS[0]), 0, 0 },
+	{ "ixTDC_MV_AVERAGE", REG_SMC, 0x3f80c, &ixTDC_MV_AVERAGE[0], sizeof(ixTDC_MV_AVERAGE)/sizeof(ixTDC_MV_AVERAGE[0]), 0, 0 },
+	{ "ixTDC_VRM_LIMIT", REG_SMC, 0x3f810, &ixTDC_VRM_LIMIT[0], sizeof(ixTDC_VRM_LIMIT)/sizeof(ixTDC_VRM_LIMIT[0]), 0, 0 },
+	{ "ixFEATURE_STATUS", REG_SMC, 0x3f818, &ixFEATURE_STATUS[0], sizeof(ixFEATURE_STATUS)/sizeof(ixFEATURE_STATUS[0]), 0, 0 },
+	{ "ixENTITY_TEMPERATURES_1", REG_SMC, 0x3f81c, &ixENTITY_TEMPERATURES_1[0], sizeof(ixENTITY_TEMPERATURES_1)/sizeof(ixENTITY_TEMPERATURES_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_1", REG_SMC, 0x3f900, &ixMCARB_DRAM_TIMING_TABLE_1[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_1)/sizeof(ixMCARB_DRAM_TIMING_TABLE_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_2", REG_SMC, 0x3f904, &ixMCARB_DRAM_TIMING_TABLE_2[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_2)/sizeof(ixMCARB_DRAM_TIMING_TABLE_2[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_3", REG_SMC, 0x3f908, &ixMCARB_DRAM_TIMING_TABLE_3[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_3)/sizeof(ixMCARB_DRAM_TIMING_TABLE_3[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_4", REG_SMC, 0x3f90c, &ixMCARB_DRAM_TIMING_TABLE_4[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_4)/sizeof(ixMCARB_DRAM_TIMING_TABLE_4[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_5", REG_SMC, 0x3f910, &ixMCARB_DRAM_TIMING_TABLE_5[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_5)/sizeof(ixMCARB_DRAM_TIMING_TABLE_5[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_6", REG_SMC, 0x3f914, &ixMCARB_DRAM_TIMING_TABLE_6[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_6)/sizeof(ixMCARB_DRAM_TIMING_TABLE_6[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_7", REG_SMC, 0x3f918, &ixMCARB_DRAM_TIMING_TABLE_7[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_7)/sizeof(ixMCARB_DRAM_TIMING_TABLE_7[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_8", REG_SMC, 0x3f91c, &ixMCARB_DRAM_TIMING_TABLE_8[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_8)/sizeof(ixMCARB_DRAM_TIMING_TABLE_8[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_9", REG_SMC, 0x3f920, &ixMCARB_DRAM_TIMING_TABLE_9[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_9)/sizeof(ixMCARB_DRAM_TIMING_TABLE_9[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_10", REG_SMC, 0x3f924, &ixMCARB_DRAM_TIMING_TABLE_10[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_10)/sizeof(ixMCARB_DRAM_TIMING_TABLE_10[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_11", REG_SMC, 0x3f928, &ixMCARB_DRAM_TIMING_TABLE_11[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_11)/sizeof(ixMCARB_DRAM_TIMING_TABLE_11[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_12", REG_SMC, 0x3f92c, &ixMCARB_DRAM_TIMING_TABLE_12[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_12)/sizeof(ixMCARB_DRAM_TIMING_TABLE_12[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_13", REG_SMC, 0x3f930, &ixMCARB_DRAM_TIMING_TABLE_13[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_13)/sizeof(ixMCARB_DRAM_TIMING_TABLE_13[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_14", REG_SMC, 0x3f934, &ixMCARB_DRAM_TIMING_TABLE_14[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_14)/sizeof(ixMCARB_DRAM_TIMING_TABLE_14[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_15", REG_SMC, 0x3f938, &ixMCARB_DRAM_TIMING_TABLE_15[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_15)/sizeof(ixMCARB_DRAM_TIMING_TABLE_15[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_16", REG_SMC, 0x3f93c, &ixMCARB_DRAM_TIMING_TABLE_16[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_16)/sizeof(ixMCARB_DRAM_TIMING_TABLE_16[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_17", REG_SMC, 0x3f940, &ixMCARB_DRAM_TIMING_TABLE_17[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_17)/sizeof(ixMCARB_DRAM_TIMING_TABLE_17[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_18", REG_SMC, 0x3f944, &ixMCARB_DRAM_TIMING_TABLE_18[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_18)/sizeof(ixMCARB_DRAM_TIMING_TABLE_18[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_19", REG_SMC, 0x3f948, &ixMCARB_DRAM_TIMING_TABLE_19[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_19)/sizeof(ixMCARB_DRAM_TIMING_TABLE_19[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_20", REG_SMC, 0x3f94c, &ixMCARB_DRAM_TIMING_TABLE_20[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_20)/sizeof(ixMCARB_DRAM_TIMING_TABLE_20[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_21", REG_SMC, 0x3f950, &ixMCARB_DRAM_TIMING_TABLE_21[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_21)/sizeof(ixMCARB_DRAM_TIMING_TABLE_21[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_22", REG_SMC, 0x3f954, &ixMCARB_DRAM_TIMING_TABLE_22[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_22)/sizeof(ixMCARB_DRAM_TIMING_TABLE_22[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_23", REG_SMC, 0x3f958, &ixMCARB_DRAM_TIMING_TABLE_23[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_23)/sizeof(ixMCARB_DRAM_TIMING_TABLE_23[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_24", REG_SMC, 0x3f95c, &ixMCARB_DRAM_TIMING_TABLE_24[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_24)/sizeof(ixMCARB_DRAM_TIMING_TABLE_24[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_25", REG_SMC, 0x3f960, &ixMCARB_DRAM_TIMING_TABLE_25[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_25)/sizeof(ixMCARB_DRAM_TIMING_TABLE_25[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_26", REG_SMC, 0x3f964, &ixMCARB_DRAM_TIMING_TABLE_26[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_26)/sizeof(ixMCARB_DRAM_TIMING_TABLE_26[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_27", REG_SMC, 0x3f968, &ixMCARB_DRAM_TIMING_TABLE_27[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_27)/sizeof(ixMCARB_DRAM_TIMING_TABLE_27[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_28", REG_SMC, 0x3f96c, &ixMCARB_DRAM_TIMING_TABLE_28[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_28)/sizeof(ixMCARB_DRAM_TIMING_TABLE_28[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_29", REG_SMC, 0x3f970, &ixMCARB_DRAM_TIMING_TABLE_29[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_29)/sizeof(ixMCARB_DRAM_TIMING_TABLE_29[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_30", REG_SMC, 0x3f974, &ixMCARB_DRAM_TIMING_TABLE_30[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_30)/sizeof(ixMCARB_DRAM_TIMING_TABLE_30[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_31", REG_SMC, 0x3f978, &ixMCARB_DRAM_TIMING_TABLE_31[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_31)/sizeof(ixMCARB_DRAM_TIMING_TABLE_31[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_32", REG_SMC, 0x3f97c, &ixMCARB_DRAM_TIMING_TABLE_32[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_32)/sizeof(ixMCARB_DRAM_TIMING_TABLE_32[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_33", REG_SMC, 0x3f980, &ixMCARB_DRAM_TIMING_TABLE_33[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_33)/sizeof(ixMCARB_DRAM_TIMING_TABLE_33[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_34", REG_SMC, 0x3f984, &ixMCARB_DRAM_TIMING_TABLE_34[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_34)/sizeof(ixMCARB_DRAM_TIMING_TABLE_34[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_35", REG_SMC, 0x3f988, &ixMCARB_DRAM_TIMING_TABLE_35[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_35)/sizeof(ixMCARB_DRAM_TIMING_TABLE_35[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_36", REG_SMC, 0x3f98c, &ixMCARB_DRAM_TIMING_TABLE_36[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_36)/sizeof(ixMCARB_DRAM_TIMING_TABLE_36[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_37", REG_SMC, 0x3f990, &ixMCARB_DRAM_TIMING_TABLE_37[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_37)/sizeof(ixMCARB_DRAM_TIMING_TABLE_37[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_38", REG_SMC, 0x3f994, &ixMCARB_DRAM_TIMING_TABLE_38[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_38)/sizeof(ixMCARB_DRAM_TIMING_TABLE_38[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_39", REG_SMC, 0x3f998, &ixMCARB_DRAM_TIMING_TABLE_39[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_39)/sizeof(ixMCARB_DRAM_TIMING_TABLE_39[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_40", REG_SMC, 0x3f99c, &ixMCARB_DRAM_TIMING_TABLE_40[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_40)/sizeof(ixMCARB_DRAM_TIMING_TABLE_40[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_41", REG_SMC, 0x3f9a0, &ixMCARB_DRAM_TIMING_TABLE_41[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_41)/sizeof(ixMCARB_DRAM_TIMING_TABLE_41[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_42", REG_SMC, 0x3f9a4, &ixMCARB_DRAM_TIMING_TABLE_42[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_42)/sizeof(ixMCARB_DRAM_TIMING_TABLE_42[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_43", REG_SMC, 0x3f9a8, &ixMCARB_DRAM_TIMING_TABLE_43[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_43)/sizeof(ixMCARB_DRAM_TIMING_TABLE_43[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_44", REG_SMC, 0x3f9ac, &ixMCARB_DRAM_TIMING_TABLE_44[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_44)/sizeof(ixMCARB_DRAM_TIMING_TABLE_44[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_45", REG_SMC, 0x3f9b0, &ixMCARB_DRAM_TIMING_TABLE_45[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_45)/sizeof(ixMCARB_DRAM_TIMING_TABLE_45[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_46", REG_SMC, 0x3f9b4, &ixMCARB_DRAM_TIMING_TABLE_46[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_46)/sizeof(ixMCARB_DRAM_TIMING_TABLE_46[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_47", REG_SMC, 0x3f9b8, &ixMCARB_DRAM_TIMING_TABLE_47[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_47)/sizeof(ixMCARB_DRAM_TIMING_TABLE_47[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_48", REG_SMC, 0x3f9bc, &ixMCARB_DRAM_TIMING_TABLE_48[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_48)/sizeof(ixMCARB_DRAM_TIMING_TABLE_48[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_49", REG_SMC, 0x3f9c0, &ixMCARB_DRAM_TIMING_TABLE_49[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_49)/sizeof(ixMCARB_DRAM_TIMING_TABLE_49[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_50", REG_SMC, 0x3f9c4, &ixMCARB_DRAM_TIMING_TABLE_50[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_50)/sizeof(ixMCARB_DRAM_TIMING_TABLE_50[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_51", REG_SMC, 0x3f9c8, &ixMCARB_DRAM_TIMING_TABLE_51[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_51)/sizeof(ixMCARB_DRAM_TIMING_TABLE_51[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_52", REG_SMC, 0x3f9cc, &ixMCARB_DRAM_TIMING_TABLE_52[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_52)/sizeof(ixMCARB_DRAM_TIMING_TABLE_52[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_53", REG_SMC, 0x3f9d0, &ixMCARB_DRAM_TIMING_TABLE_53[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_53)/sizeof(ixMCARB_DRAM_TIMING_TABLE_53[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_54", REG_SMC, 0x3f9d4, &ixMCARB_DRAM_TIMING_TABLE_54[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_54)/sizeof(ixMCARB_DRAM_TIMING_TABLE_54[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_55", REG_SMC, 0x3f9d8, &ixMCARB_DRAM_TIMING_TABLE_55[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_55)/sizeof(ixMCARB_DRAM_TIMING_TABLE_55[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_56", REG_SMC, 0x3f9dc, &ixMCARB_DRAM_TIMING_TABLE_56[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_56)/sizeof(ixMCARB_DRAM_TIMING_TABLE_56[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_57", REG_SMC, 0x3f9e0, &ixMCARB_DRAM_TIMING_TABLE_57[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_57)/sizeof(ixMCARB_DRAM_TIMING_TABLE_57[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_58", REG_SMC, 0x3f9e4, &ixMCARB_DRAM_TIMING_TABLE_58[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_58)/sizeof(ixMCARB_DRAM_TIMING_TABLE_58[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_59", REG_SMC, 0x3f9e8, &ixMCARB_DRAM_TIMING_TABLE_59[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_59)/sizeof(ixMCARB_DRAM_TIMING_TABLE_59[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_60", REG_SMC, 0x3f9ec, &ixMCARB_DRAM_TIMING_TABLE_60[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_60)/sizeof(ixMCARB_DRAM_TIMING_TABLE_60[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_61", REG_SMC, 0x3f9f0, &ixMCARB_DRAM_TIMING_TABLE_61[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_61)/sizeof(ixMCARB_DRAM_TIMING_TABLE_61[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_62", REG_SMC, 0x3f9f4, &ixMCARB_DRAM_TIMING_TABLE_62[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_62)/sizeof(ixMCARB_DRAM_TIMING_TABLE_62[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_63", REG_SMC, 0x3f9f8, &ixMCARB_DRAM_TIMING_TABLE_63[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_63)/sizeof(ixMCARB_DRAM_TIMING_TABLE_63[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_64", REG_SMC, 0x3f9fc, &ixMCARB_DRAM_TIMING_TABLE_64[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_64)/sizeof(ixMCARB_DRAM_TIMING_TABLE_64[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_65", REG_SMC, 0x3fa00, &ixMCARB_DRAM_TIMING_TABLE_65[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_65)/sizeof(ixMCARB_DRAM_TIMING_TABLE_65[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_66", REG_SMC, 0x3fa04, &ixMCARB_DRAM_TIMING_TABLE_66[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_66)/sizeof(ixMCARB_DRAM_TIMING_TABLE_66[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_67", REG_SMC, 0x3fa08, &ixMCARB_DRAM_TIMING_TABLE_67[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_67)/sizeof(ixMCARB_DRAM_TIMING_TABLE_67[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_68", REG_SMC, 0x3fa0c, &ixMCARB_DRAM_TIMING_TABLE_68[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_68)/sizeof(ixMCARB_DRAM_TIMING_TABLE_68[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_69", REG_SMC, 0x3fa10, &ixMCARB_DRAM_TIMING_TABLE_69[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_69)/sizeof(ixMCARB_DRAM_TIMING_TABLE_69[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_70", REG_SMC, 0x3fa14, &ixMCARB_DRAM_TIMING_TABLE_70[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_70)/sizeof(ixMCARB_DRAM_TIMING_TABLE_70[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_71", REG_SMC, 0x3fa18, &ixMCARB_DRAM_TIMING_TABLE_71[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_71)/sizeof(ixMCARB_DRAM_TIMING_TABLE_71[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_72", REG_SMC, 0x3fa1c, &ixMCARB_DRAM_TIMING_TABLE_72[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_72)/sizeof(ixMCARB_DRAM_TIMING_TABLE_72[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_73", REG_SMC, 0x3fa20, &ixMCARB_DRAM_TIMING_TABLE_73[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_73)/sizeof(ixMCARB_DRAM_TIMING_TABLE_73[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_74", REG_SMC, 0x3fa24, &ixMCARB_DRAM_TIMING_TABLE_74[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_74)/sizeof(ixMCARB_DRAM_TIMING_TABLE_74[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_75", REG_SMC, 0x3fa28, &ixMCARB_DRAM_TIMING_TABLE_75[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_75)/sizeof(ixMCARB_DRAM_TIMING_TABLE_75[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_76", REG_SMC, 0x3fa2c, &ixMCARB_DRAM_TIMING_TABLE_76[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_76)/sizeof(ixMCARB_DRAM_TIMING_TABLE_76[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_77", REG_SMC, 0x3fa30, &ixMCARB_DRAM_TIMING_TABLE_77[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_77)/sizeof(ixMCARB_DRAM_TIMING_TABLE_77[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_78", REG_SMC, 0x3fa34, &ixMCARB_DRAM_TIMING_TABLE_78[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_78)/sizeof(ixMCARB_DRAM_TIMING_TABLE_78[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_79", REG_SMC, 0x3fa38, &ixMCARB_DRAM_TIMING_TABLE_79[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_79)/sizeof(ixMCARB_DRAM_TIMING_TABLE_79[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_80", REG_SMC, 0x3fa3c, &ixMCARB_DRAM_TIMING_TABLE_80[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_80)/sizeof(ixMCARB_DRAM_TIMING_TABLE_80[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_81", REG_SMC, 0x3fa40, &ixMCARB_DRAM_TIMING_TABLE_81[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_81)/sizeof(ixMCARB_DRAM_TIMING_TABLE_81[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_82", REG_SMC, 0x3fa44, &ixMCARB_DRAM_TIMING_TABLE_82[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_82)/sizeof(ixMCARB_DRAM_TIMING_TABLE_82[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_83", REG_SMC, 0x3fa48, &ixMCARB_DRAM_TIMING_TABLE_83[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_83)/sizeof(ixMCARB_DRAM_TIMING_TABLE_83[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_84", REG_SMC, 0x3fa4c, &ixMCARB_DRAM_TIMING_TABLE_84[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_84)/sizeof(ixMCARB_DRAM_TIMING_TABLE_84[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_85", REG_SMC, 0x3fa50, &ixMCARB_DRAM_TIMING_TABLE_85[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_85)/sizeof(ixMCARB_DRAM_TIMING_TABLE_85[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_86", REG_SMC, 0x3fa54, &ixMCARB_DRAM_TIMING_TABLE_86[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_86)/sizeof(ixMCARB_DRAM_TIMING_TABLE_86[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_87", REG_SMC, 0x3fa58, &ixMCARB_DRAM_TIMING_TABLE_87[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_87)/sizeof(ixMCARB_DRAM_TIMING_TABLE_87[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_88", REG_SMC, 0x3fa5c, &ixMCARB_DRAM_TIMING_TABLE_88[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_88)/sizeof(ixMCARB_DRAM_TIMING_TABLE_88[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_89", REG_SMC, 0x3fa60, &ixMCARB_DRAM_TIMING_TABLE_89[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_89)/sizeof(ixMCARB_DRAM_TIMING_TABLE_89[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_90", REG_SMC, 0x3fa64, &ixMCARB_DRAM_TIMING_TABLE_90[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_90)/sizeof(ixMCARB_DRAM_TIMING_TABLE_90[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_91", REG_SMC, 0x3fa68, &ixMCARB_DRAM_TIMING_TABLE_91[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_91)/sizeof(ixMCARB_DRAM_TIMING_TABLE_91[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_92", REG_SMC, 0x3fa6c, &ixMCARB_DRAM_TIMING_TABLE_92[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_92)/sizeof(ixMCARB_DRAM_TIMING_TABLE_92[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_93", REG_SMC, 0x3fa70, &ixMCARB_DRAM_TIMING_TABLE_93[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_93)/sizeof(ixMCARB_DRAM_TIMING_TABLE_93[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_94", REG_SMC, 0x3fa74, &ixMCARB_DRAM_TIMING_TABLE_94[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_94)/sizeof(ixMCARB_DRAM_TIMING_TABLE_94[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_95", REG_SMC, 0x3fa78, &ixMCARB_DRAM_TIMING_TABLE_95[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_95)/sizeof(ixMCARB_DRAM_TIMING_TABLE_95[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_96", REG_SMC, 0x3fa7c, &ixMCARB_DRAM_TIMING_TABLE_96[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_96)/sizeof(ixMCARB_DRAM_TIMING_TABLE_96[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_97", REG_SMC, 0x3fa80, &ixMCARB_DRAM_TIMING_TABLE_97[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_97)/sizeof(ixMCARB_DRAM_TIMING_TABLE_97[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_98", REG_SMC, 0x3fa84, &ixMCARB_DRAM_TIMING_TABLE_98[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_98)/sizeof(ixMCARB_DRAM_TIMING_TABLE_98[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_99", REG_SMC, 0x3fa88, &ixMCARB_DRAM_TIMING_TABLE_99[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_99)/sizeof(ixMCARB_DRAM_TIMING_TABLE_99[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_100", REG_SMC, 0x3fa8c, &ixMCARB_DRAM_TIMING_TABLE_100[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_100)/sizeof(ixMCARB_DRAM_TIMING_TABLE_100[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_101", REG_SMC, 0x3fa90, &ixMCARB_DRAM_TIMING_TABLE_101[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_101)/sizeof(ixMCARB_DRAM_TIMING_TABLE_101[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_102", REG_SMC, 0x3fa94, &ixMCARB_DRAM_TIMING_TABLE_102[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_102)/sizeof(ixMCARB_DRAM_TIMING_TABLE_102[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_103", REG_SMC, 0x3fa98, &ixMCARB_DRAM_TIMING_TABLE_103[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_103)/sizeof(ixMCARB_DRAM_TIMING_TABLE_103[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_104", REG_SMC, 0x3fa9c, &ixMCARB_DRAM_TIMING_TABLE_104[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_104)/sizeof(ixMCARB_DRAM_TIMING_TABLE_104[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_105", REG_SMC, 0x3faa0, &ixMCARB_DRAM_TIMING_TABLE_105[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_105)/sizeof(ixMCARB_DRAM_TIMING_TABLE_105[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_106", REG_SMC, 0x3faa4, &ixMCARB_DRAM_TIMING_TABLE_106[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_106)/sizeof(ixMCARB_DRAM_TIMING_TABLE_106[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_107", REG_SMC, 0x3faa8, &ixMCARB_DRAM_TIMING_TABLE_107[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_107)/sizeof(ixMCARB_DRAM_TIMING_TABLE_107[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_108", REG_SMC, 0x3faac, &ixMCARB_DRAM_TIMING_TABLE_108[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_108)/sizeof(ixMCARB_DRAM_TIMING_TABLE_108[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_109", REG_SMC, 0x3fab0, &ixMCARB_DRAM_TIMING_TABLE_109[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_109)/sizeof(ixMCARB_DRAM_TIMING_TABLE_109[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_110", REG_SMC, 0x3fab4, &ixMCARB_DRAM_TIMING_TABLE_110[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_110)/sizeof(ixMCARB_DRAM_TIMING_TABLE_110[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_111", REG_SMC, 0x3fab8, &ixMCARB_DRAM_TIMING_TABLE_111[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_111)/sizeof(ixMCARB_DRAM_TIMING_TABLE_111[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_112", REG_SMC, 0x3fabc, &ixMCARB_DRAM_TIMING_TABLE_112[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_112)/sizeof(ixMCARB_DRAM_TIMING_TABLE_112[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_113", REG_SMC, 0x3fac0, &ixMCARB_DRAM_TIMING_TABLE_113[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_113)/sizeof(ixMCARB_DRAM_TIMING_TABLE_113[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_114", REG_SMC, 0x3fac4, &ixMCARB_DRAM_TIMING_TABLE_114[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_114)/sizeof(ixMCARB_DRAM_TIMING_TABLE_114[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_115", REG_SMC, 0x3fac8, &ixMCARB_DRAM_TIMING_TABLE_115[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_115)/sizeof(ixMCARB_DRAM_TIMING_TABLE_115[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_116", REG_SMC, 0x3facc, &ixMCARB_DRAM_TIMING_TABLE_116[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_116)/sizeof(ixMCARB_DRAM_TIMING_TABLE_116[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_117", REG_SMC, 0x3fad0, &ixMCARB_DRAM_TIMING_TABLE_117[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_117)/sizeof(ixMCARB_DRAM_TIMING_TABLE_117[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_118", REG_SMC, 0x3fad4, &ixMCARB_DRAM_TIMING_TABLE_118[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_118)/sizeof(ixMCARB_DRAM_TIMING_TABLE_118[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_119", REG_SMC, 0x3fad8, &ixMCARB_DRAM_TIMING_TABLE_119[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_119)/sizeof(ixMCARB_DRAM_TIMING_TABLE_119[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_120", REG_SMC, 0x3fadc, &ixMCARB_DRAM_TIMING_TABLE_120[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_120)/sizeof(ixMCARB_DRAM_TIMING_TABLE_120[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_121", REG_SMC, 0x3fae0, &ixMCARB_DRAM_TIMING_TABLE_121[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_121)/sizeof(ixMCARB_DRAM_TIMING_TABLE_121[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_122", REG_SMC, 0x3fae4, &ixMCARB_DRAM_TIMING_TABLE_122[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_122)/sizeof(ixMCARB_DRAM_TIMING_TABLE_122[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_123", REG_SMC, 0x3fae8, &ixMCARB_DRAM_TIMING_TABLE_123[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_123)/sizeof(ixMCARB_DRAM_TIMING_TABLE_123[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_124", REG_SMC, 0x3faec, &ixMCARB_DRAM_TIMING_TABLE_124[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_124)/sizeof(ixMCARB_DRAM_TIMING_TABLE_124[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_125", REG_SMC, 0x3faf0, &ixMCARB_DRAM_TIMING_TABLE_125[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_125)/sizeof(ixMCARB_DRAM_TIMING_TABLE_125[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_126", REG_SMC, 0x3faf4, &ixMCARB_DRAM_TIMING_TABLE_126[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_126)/sizeof(ixMCARB_DRAM_TIMING_TABLE_126[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_127", REG_SMC, 0x3faf8, &ixMCARB_DRAM_TIMING_TABLE_127[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_127)/sizeof(ixMCARB_DRAM_TIMING_TABLE_127[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_128", REG_SMC, 0x3fafc, &ixMCARB_DRAM_TIMING_TABLE_128[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_128)/sizeof(ixMCARB_DRAM_TIMING_TABLE_128[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_129", REG_SMC, 0x3fb00, &ixMCARB_DRAM_TIMING_TABLE_129[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_129)/sizeof(ixMCARB_DRAM_TIMING_TABLE_129[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_130", REG_SMC, 0x3fb04, &ixMCARB_DRAM_TIMING_TABLE_130[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_130)/sizeof(ixMCARB_DRAM_TIMING_TABLE_130[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_131", REG_SMC, 0x3fb08, &ixMCARB_DRAM_TIMING_TABLE_131[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_131)/sizeof(ixMCARB_DRAM_TIMING_TABLE_131[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_132", REG_SMC, 0x3fb0c, &ixMCARB_DRAM_TIMING_TABLE_132[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_132)/sizeof(ixMCARB_DRAM_TIMING_TABLE_132[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_133", REG_SMC, 0x3fb10, &ixMCARB_DRAM_TIMING_TABLE_133[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_133)/sizeof(ixMCARB_DRAM_TIMING_TABLE_133[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_134", REG_SMC, 0x3fb14, &ixMCARB_DRAM_TIMING_TABLE_134[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_134)/sizeof(ixMCARB_DRAM_TIMING_TABLE_134[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_135", REG_SMC, 0x3fb18, &ixMCARB_DRAM_TIMING_TABLE_135[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_135)/sizeof(ixMCARB_DRAM_TIMING_TABLE_135[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_136", REG_SMC, 0x3fb1c, &ixMCARB_DRAM_TIMING_TABLE_136[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_136)/sizeof(ixMCARB_DRAM_TIMING_TABLE_136[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_137", REG_SMC, 0x3fb20, &ixMCARB_DRAM_TIMING_TABLE_137[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_137)/sizeof(ixMCARB_DRAM_TIMING_TABLE_137[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_138", REG_SMC, 0x3fb24, &ixMCARB_DRAM_TIMING_TABLE_138[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_138)/sizeof(ixMCARB_DRAM_TIMING_TABLE_138[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_139", REG_SMC, 0x3fb28, &ixMCARB_DRAM_TIMING_TABLE_139[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_139)/sizeof(ixMCARB_DRAM_TIMING_TABLE_139[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_140", REG_SMC, 0x3fb2c, &ixMCARB_DRAM_TIMING_TABLE_140[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_140)/sizeof(ixMCARB_DRAM_TIMING_TABLE_140[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_141", REG_SMC, 0x3fb30, &ixMCARB_DRAM_TIMING_TABLE_141[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_141)/sizeof(ixMCARB_DRAM_TIMING_TABLE_141[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_142", REG_SMC, 0x3fb34, &ixMCARB_DRAM_TIMING_TABLE_142[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_142)/sizeof(ixMCARB_DRAM_TIMING_TABLE_142[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_143", REG_SMC, 0x3fb38, &ixMCARB_DRAM_TIMING_TABLE_143[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_143)/sizeof(ixMCARB_DRAM_TIMING_TABLE_143[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_144", REG_SMC, 0x3fb3c, &ixMCARB_DRAM_TIMING_TABLE_144[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_144)/sizeof(ixMCARB_DRAM_TIMING_TABLE_144[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_1", REG_SMC, 0x3fb40, &ixMC_REGISTERS_TABLE_1[0], sizeof(ixMC_REGISTERS_TABLE_1)/sizeof(ixMC_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_2", REG_SMC, 0x3fb44, &ixMC_REGISTERS_TABLE_2[0], sizeof(ixMC_REGISTERS_TABLE_2)/sizeof(ixMC_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_3", REG_SMC, 0x3fb48, &ixMC_REGISTERS_TABLE_3[0], sizeof(ixMC_REGISTERS_TABLE_3)/sizeof(ixMC_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_4", REG_SMC, 0x3fb4c, &ixMC_REGISTERS_TABLE_4[0], sizeof(ixMC_REGISTERS_TABLE_4)/sizeof(ixMC_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_5", REG_SMC, 0x3fb50, &ixMC_REGISTERS_TABLE_5[0], sizeof(ixMC_REGISTERS_TABLE_5)/sizeof(ixMC_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_6", REG_SMC, 0x3fb54, &ixMC_REGISTERS_TABLE_6[0], sizeof(ixMC_REGISTERS_TABLE_6)/sizeof(ixMC_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_7", REG_SMC, 0x3fb58, &ixMC_REGISTERS_TABLE_7[0], sizeof(ixMC_REGISTERS_TABLE_7)/sizeof(ixMC_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_8", REG_SMC, 0x3fb5c, &ixMC_REGISTERS_TABLE_8[0], sizeof(ixMC_REGISTERS_TABLE_8)/sizeof(ixMC_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_9", REG_SMC, 0x3fb60, &ixMC_REGISTERS_TABLE_9[0], sizeof(ixMC_REGISTERS_TABLE_9)/sizeof(ixMC_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_10", REG_SMC, 0x3fb64, &ixMC_REGISTERS_TABLE_10[0], sizeof(ixMC_REGISTERS_TABLE_10)/sizeof(ixMC_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_11", REG_SMC, 0x3fb68, &ixMC_REGISTERS_TABLE_11[0], sizeof(ixMC_REGISTERS_TABLE_11)/sizeof(ixMC_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_12", REG_SMC, 0x3fb6c, &ixMC_REGISTERS_TABLE_12[0], sizeof(ixMC_REGISTERS_TABLE_12)/sizeof(ixMC_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_13", REG_SMC, 0x3fb70, &ixMC_REGISTERS_TABLE_13[0], sizeof(ixMC_REGISTERS_TABLE_13)/sizeof(ixMC_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_14", REG_SMC, 0x3fb74, &ixMC_REGISTERS_TABLE_14[0], sizeof(ixMC_REGISTERS_TABLE_14)/sizeof(ixMC_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_15", REG_SMC, 0x3fb78, &ixMC_REGISTERS_TABLE_15[0], sizeof(ixMC_REGISTERS_TABLE_15)/sizeof(ixMC_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_16", REG_SMC, 0x3fb7c, &ixMC_REGISTERS_TABLE_16[0], sizeof(ixMC_REGISTERS_TABLE_16)/sizeof(ixMC_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_17", REG_SMC, 0x3fb80, &ixMC_REGISTERS_TABLE_17[0], sizeof(ixMC_REGISTERS_TABLE_17)/sizeof(ixMC_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_18", REG_SMC, 0x3fb84, &ixMC_REGISTERS_TABLE_18[0], sizeof(ixMC_REGISTERS_TABLE_18)/sizeof(ixMC_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_19", REG_SMC, 0x3fb88, &ixMC_REGISTERS_TABLE_19[0], sizeof(ixMC_REGISTERS_TABLE_19)/sizeof(ixMC_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_20", REG_SMC, 0x3fb8c, &ixMC_REGISTERS_TABLE_20[0], sizeof(ixMC_REGISTERS_TABLE_20)/sizeof(ixMC_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_21", REG_SMC, 0x3fb90, &ixMC_REGISTERS_TABLE_21[0], sizeof(ixMC_REGISTERS_TABLE_21)/sizeof(ixMC_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_22", REG_SMC, 0x3fb94, &ixMC_REGISTERS_TABLE_22[0], sizeof(ixMC_REGISTERS_TABLE_22)/sizeof(ixMC_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_23", REG_SMC, 0x3fb98, &ixMC_REGISTERS_TABLE_23[0], sizeof(ixMC_REGISTERS_TABLE_23)/sizeof(ixMC_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_24", REG_SMC, 0x3fb9c, &ixMC_REGISTERS_TABLE_24[0], sizeof(ixMC_REGISTERS_TABLE_24)/sizeof(ixMC_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_25", REG_SMC, 0x3fba0, &ixMC_REGISTERS_TABLE_25[0], sizeof(ixMC_REGISTERS_TABLE_25)/sizeof(ixMC_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_26", REG_SMC, 0x3fba4, &ixMC_REGISTERS_TABLE_26[0], sizeof(ixMC_REGISTERS_TABLE_26)/sizeof(ixMC_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_27", REG_SMC, 0x3fba8, &ixMC_REGISTERS_TABLE_27[0], sizeof(ixMC_REGISTERS_TABLE_27)/sizeof(ixMC_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_28", REG_SMC, 0x3fbac, &ixMC_REGISTERS_TABLE_28[0], sizeof(ixMC_REGISTERS_TABLE_28)/sizeof(ixMC_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_29", REG_SMC, 0x3fbb0, &ixMC_REGISTERS_TABLE_29[0], sizeof(ixMC_REGISTERS_TABLE_29)/sizeof(ixMC_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_30", REG_SMC, 0x3fbb4, &ixMC_REGISTERS_TABLE_30[0], sizeof(ixMC_REGISTERS_TABLE_30)/sizeof(ixMC_REGISTERS_TABLE_30[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_31", REG_SMC, 0x3fbb8, &ixMC_REGISTERS_TABLE_31[0], sizeof(ixMC_REGISTERS_TABLE_31)/sizeof(ixMC_REGISTERS_TABLE_31[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_32", REG_SMC, 0x3fbbc, &ixMC_REGISTERS_TABLE_32[0], sizeof(ixMC_REGISTERS_TABLE_32)/sizeof(ixMC_REGISTERS_TABLE_32[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_33", REG_SMC, 0x3fbc0, &ixMC_REGISTERS_TABLE_33[0], sizeof(ixMC_REGISTERS_TABLE_33)/sizeof(ixMC_REGISTERS_TABLE_33[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_34", REG_SMC, 0x3fbc4, &ixMC_REGISTERS_TABLE_34[0], sizeof(ixMC_REGISTERS_TABLE_34)/sizeof(ixMC_REGISTERS_TABLE_34[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_35", REG_SMC, 0x3fbc8, &ixMC_REGISTERS_TABLE_35[0], sizeof(ixMC_REGISTERS_TABLE_35)/sizeof(ixMC_REGISTERS_TABLE_35[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_36", REG_SMC, 0x3fbcc, &ixMC_REGISTERS_TABLE_36[0], sizeof(ixMC_REGISTERS_TABLE_36)/sizeof(ixMC_REGISTERS_TABLE_36[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_37", REG_SMC, 0x3fbd0, &ixMC_REGISTERS_TABLE_37[0], sizeof(ixMC_REGISTERS_TABLE_37)/sizeof(ixMC_REGISTERS_TABLE_37[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_38", REG_SMC, 0x3fbd4, &ixMC_REGISTERS_TABLE_38[0], sizeof(ixMC_REGISTERS_TABLE_38)/sizeof(ixMC_REGISTERS_TABLE_38[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_39", REG_SMC, 0x3fbd8, &ixMC_REGISTERS_TABLE_39[0], sizeof(ixMC_REGISTERS_TABLE_39)/sizeof(ixMC_REGISTERS_TABLE_39[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_40", REG_SMC, 0x3fbdc, &ixMC_REGISTERS_TABLE_40[0], sizeof(ixMC_REGISTERS_TABLE_40)/sizeof(ixMC_REGISTERS_TABLE_40[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_41", REG_SMC, 0x3fbe0, &ixMC_REGISTERS_TABLE_41[0], sizeof(ixMC_REGISTERS_TABLE_41)/sizeof(ixMC_REGISTERS_TABLE_41[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_42", REG_SMC, 0x3fbe4, &ixMC_REGISTERS_TABLE_42[0], sizeof(ixMC_REGISTERS_TABLE_42)/sizeof(ixMC_REGISTERS_TABLE_42[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_43", REG_SMC, 0x3fbe8, &ixMC_REGISTERS_TABLE_43[0], sizeof(ixMC_REGISTERS_TABLE_43)/sizeof(ixMC_REGISTERS_TABLE_43[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_44", REG_SMC, 0x3fbec, &ixMC_REGISTERS_TABLE_44[0], sizeof(ixMC_REGISTERS_TABLE_44)/sizeof(ixMC_REGISTERS_TABLE_44[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_45", REG_SMC, 0x3fbf0, &ixMC_REGISTERS_TABLE_45[0], sizeof(ixMC_REGISTERS_TABLE_45)/sizeof(ixMC_REGISTERS_TABLE_45[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_46", REG_SMC, 0x3fbf4, &ixMC_REGISTERS_TABLE_46[0], sizeof(ixMC_REGISTERS_TABLE_46)/sizeof(ixMC_REGISTERS_TABLE_46[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_47", REG_SMC, 0x3fbf8, &ixMC_REGISTERS_TABLE_47[0], sizeof(ixMC_REGISTERS_TABLE_47)/sizeof(ixMC_REGISTERS_TABLE_47[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_48", REG_SMC, 0x3fbfc, &ixMC_REGISTERS_TABLE_48[0], sizeof(ixMC_REGISTERS_TABLE_48)/sizeof(ixMC_REGISTERS_TABLE_48[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_49", REG_SMC, 0x3fc00, &ixMC_REGISTERS_TABLE_49[0], sizeof(ixMC_REGISTERS_TABLE_49)/sizeof(ixMC_REGISTERS_TABLE_49[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_50", REG_SMC, 0x3fc04, &ixMC_REGISTERS_TABLE_50[0], sizeof(ixMC_REGISTERS_TABLE_50)/sizeof(ixMC_REGISTERS_TABLE_50[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_51", REG_SMC, 0x3fc08, &ixMC_REGISTERS_TABLE_51[0], sizeof(ixMC_REGISTERS_TABLE_51)/sizeof(ixMC_REGISTERS_TABLE_51[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_52", REG_SMC, 0x3fc0c, &ixMC_REGISTERS_TABLE_52[0], sizeof(ixMC_REGISTERS_TABLE_52)/sizeof(ixMC_REGISTERS_TABLE_52[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_53", REG_SMC, 0x3fc10, &ixMC_REGISTERS_TABLE_53[0], sizeof(ixMC_REGISTERS_TABLE_53)/sizeof(ixMC_REGISTERS_TABLE_53[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_54", REG_SMC, 0x3fc14, &ixMC_REGISTERS_TABLE_54[0], sizeof(ixMC_REGISTERS_TABLE_54)/sizeof(ixMC_REGISTERS_TABLE_54[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_55", REG_SMC, 0x3fc18, &ixMC_REGISTERS_TABLE_55[0], sizeof(ixMC_REGISTERS_TABLE_55)/sizeof(ixMC_REGISTERS_TABLE_55[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_56", REG_SMC, 0x3fc1c, &ixMC_REGISTERS_TABLE_56[0], sizeof(ixMC_REGISTERS_TABLE_56)/sizeof(ixMC_REGISTERS_TABLE_56[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_57", REG_SMC, 0x3fc20, &ixMC_REGISTERS_TABLE_57[0], sizeof(ixMC_REGISTERS_TABLE_57)/sizeof(ixMC_REGISTERS_TABLE_57[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_58", REG_SMC, 0x3fc24, &ixMC_REGISTERS_TABLE_58[0], sizeof(ixMC_REGISTERS_TABLE_58)/sizeof(ixMC_REGISTERS_TABLE_58[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_59", REG_SMC, 0x3fc28, &ixMC_REGISTERS_TABLE_59[0], sizeof(ixMC_REGISTERS_TABLE_59)/sizeof(ixMC_REGISTERS_TABLE_59[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_60", REG_SMC, 0x3fc2c, &ixMC_REGISTERS_TABLE_60[0], sizeof(ixMC_REGISTERS_TABLE_60)/sizeof(ixMC_REGISTERS_TABLE_60[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_61", REG_SMC, 0x3fc30, &ixMC_REGISTERS_TABLE_61[0], sizeof(ixMC_REGISTERS_TABLE_61)/sizeof(ixMC_REGISTERS_TABLE_61[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_62", REG_SMC, 0x3fc34, &ixMC_REGISTERS_TABLE_62[0], sizeof(ixMC_REGISTERS_TABLE_62)/sizeof(ixMC_REGISTERS_TABLE_62[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_63", REG_SMC, 0x3fc38, &ixMC_REGISTERS_TABLE_63[0], sizeof(ixMC_REGISTERS_TABLE_63)/sizeof(ixMC_REGISTERS_TABLE_63[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_64", REG_SMC, 0x3fc3c, &ixMC_REGISTERS_TABLE_64[0], sizeof(ixMC_REGISTERS_TABLE_64)/sizeof(ixMC_REGISTERS_TABLE_64[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_65", REG_SMC, 0x3fc40, &ixMC_REGISTERS_TABLE_65[0], sizeof(ixMC_REGISTERS_TABLE_65)/sizeof(ixMC_REGISTERS_TABLE_65[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_66", REG_SMC, 0x3fc44, &ixMC_REGISTERS_TABLE_66[0], sizeof(ixMC_REGISTERS_TABLE_66)/sizeof(ixMC_REGISTERS_TABLE_66[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_67", REG_SMC, 0x3fc48, &ixMC_REGISTERS_TABLE_67[0], sizeof(ixMC_REGISTERS_TABLE_67)/sizeof(ixMC_REGISTERS_TABLE_67[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_68", REG_SMC, 0x3fc4c, &ixMC_REGISTERS_TABLE_68[0], sizeof(ixMC_REGISTERS_TABLE_68)/sizeof(ixMC_REGISTERS_TABLE_68[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_69", REG_SMC, 0x3fc50, &ixMC_REGISTERS_TABLE_69[0], sizeof(ixMC_REGISTERS_TABLE_69)/sizeof(ixMC_REGISTERS_TABLE_69[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_70", REG_SMC, 0x3fc54, &ixMC_REGISTERS_TABLE_70[0], sizeof(ixMC_REGISTERS_TABLE_70)/sizeof(ixMC_REGISTERS_TABLE_70[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_71", REG_SMC, 0x3fc58, &ixMC_REGISTERS_TABLE_71[0], sizeof(ixMC_REGISTERS_TABLE_71)/sizeof(ixMC_REGISTERS_TABLE_71[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_72", REG_SMC, 0x3fc5c, &ixMC_REGISTERS_TABLE_72[0], sizeof(ixMC_REGISTERS_TABLE_72)/sizeof(ixMC_REGISTERS_TABLE_72[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_73", REG_SMC, 0x3fc60, &ixMC_REGISTERS_TABLE_73[0], sizeof(ixMC_REGISTERS_TABLE_73)/sizeof(ixMC_REGISTERS_TABLE_73[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_74", REG_SMC, 0x3fc64, &ixMC_REGISTERS_TABLE_74[0], sizeof(ixMC_REGISTERS_TABLE_74)/sizeof(ixMC_REGISTERS_TABLE_74[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_75", REG_SMC, 0x3fc68, &ixMC_REGISTERS_TABLE_75[0], sizeof(ixMC_REGISTERS_TABLE_75)/sizeof(ixMC_REGISTERS_TABLE_75[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_76", REG_SMC, 0x3fc6c, &ixMC_REGISTERS_TABLE_76[0], sizeof(ixMC_REGISTERS_TABLE_76)/sizeof(ixMC_REGISTERS_TABLE_76[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_77", REG_SMC, 0x3fc70, &ixMC_REGISTERS_TABLE_77[0], sizeof(ixMC_REGISTERS_TABLE_77)/sizeof(ixMC_REGISTERS_TABLE_77[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_78", REG_SMC, 0x3fc74, &ixMC_REGISTERS_TABLE_78[0], sizeof(ixMC_REGISTERS_TABLE_78)/sizeof(ixMC_REGISTERS_TABLE_78[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_79", REG_SMC, 0x3fc78, &ixMC_REGISTERS_TABLE_79[0], sizeof(ixMC_REGISTERS_TABLE_79)/sizeof(ixMC_REGISTERS_TABLE_79[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_80", REG_SMC, 0x3fc7c, &ixMC_REGISTERS_TABLE_80[0], sizeof(ixMC_REGISTERS_TABLE_80)/sizeof(ixMC_REGISTERS_TABLE_80[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_81", REG_SMC, 0x3fc80, &ixMC_REGISTERS_TABLE_81[0], sizeof(ixMC_REGISTERS_TABLE_81)/sizeof(ixMC_REGISTERS_TABLE_81[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_82", REG_SMC, 0x3fc84, &ixMC_REGISTERS_TABLE_82[0], sizeof(ixMC_REGISTERS_TABLE_82)/sizeof(ixMC_REGISTERS_TABLE_82[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_83", REG_SMC, 0x3fc88, &ixMC_REGISTERS_TABLE_83[0], sizeof(ixMC_REGISTERS_TABLE_83)/sizeof(ixMC_REGISTERS_TABLE_83[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_84", REG_SMC, 0x3fc8c, &ixMC_REGISTERS_TABLE_84[0], sizeof(ixMC_REGISTERS_TABLE_84)/sizeof(ixMC_REGISTERS_TABLE_84[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_85", REG_SMC, 0x3fc90, &ixMC_REGISTERS_TABLE_85[0], sizeof(ixMC_REGISTERS_TABLE_85)/sizeof(ixMC_REGISTERS_TABLE_85[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_86", REG_SMC, 0x3fc94, &ixMC_REGISTERS_TABLE_86[0], sizeof(ixMC_REGISTERS_TABLE_86)/sizeof(ixMC_REGISTERS_TABLE_86[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_87", REG_SMC, 0x3fc98, &ixMC_REGISTERS_TABLE_87[0], sizeof(ixMC_REGISTERS_TABLE_87)/sizeof(ixMC_REGISTERS_TABLE_87[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_88", REG_SMC, 0x3fc9c, &ixMC_REGISTERS_TABLE_88[0], sizeof(ixMC_REGISTERS_TABLE_88)/sizeof(ixMC_REGISTERS_TABLE_88[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_89", REG_SMC, 0x3fca0, &ixMC_REGISTERS_TABLE_89[0], sizeof(ixMC_REGISTERS_TABLE_89)/sizeof(ixMC_REGISTERS_TABLE_89[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_90", REG_SMC, 0x3fca4, &ixMC_REGISTERS_TABLE_90[0], sizeof(ixMC_REGISTERS_TABLE_90)/sizeof(ixMC_REGISTERS_TABLE_90[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_91", REG_SMC, 0x3fca8, &ixMC_REGISTERS_TABLE_91[0], sizeof(ixMC_REGISTERS_TABLE_91)/sizeof(ixMC_REGISTERS_TABLE_91[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_92", REG_SMC, 0x3fcac, &ixMC_REGISTERS_TABLE_92[0], sizeof(ixMC_REGISTERS_TABLE_92)/sizeof(ixMC_REGISTERS_TABLE_92[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_93", REG_SMC, 0x3fcb0, &ixMC_REGISTERS_TABLE_93[0], sizeof(ixMC_REGISTERS_TABLE_93)/sizeof(ixMC_REGISTERS_TABLE_93[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_94", REG_SMC, 0x3fcb4, &ixMC_REGISTERS_TABLE_94[0], sizeof(ixMC_REGISTERS_TABLE_94)/sizeof(ixMC_REGISTERS_TABLE_94[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_95", REG_SMC, 0x3fcb8, &ixMC_REGISTERS_TABLE_95[0], sizeof(ixMC_REGISTERS_TABLE_95)/sizeof(ixMC_REGISTERS_TABLE_95[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_96", REG_SMC, 0x3fcbc, &ixMC_REGISTERS_TABLE_96[0], sizeof(ixMC_REGISTERS_TABLE_96)/sizeof(ixMC_REGISTERS_TABLE_96[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_97", REG_SMC, 0x3fcc0, &ixMC_REGISTERS_TABLE_97[0], sizeof(ixMC_REGISTERS_TABLE_97)/sizeof(ixMC_REGISTERS_TABLE_97[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_98", REG_SMC, 0x3fcc4, &ixMC_REGISTERS_TABLE_98[0], sizeof(ixMC_REGISTERS_TABLE_98)/sizeof(ixMC_REGISTERS_TABLE_98[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_99", REG_SMC, 0x3fcc8, &ixMC_REGISTERS_TABLE_99[0], sizeof(ixMC_REGISTERS_TABLE_99)/sizeof(ixMC_REGISTERS_TABLE_99[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_100", REG_SMC, 0x3fccc, &ixMC_REGISTERS_TABLE_100[0], sizeof(ixMC_REGISTERS_TABLE_100)/sizeof(ixMC_REGISTERS_TABLE_100[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_101", REG_SMC, 0x3fcd0, &ixMC_REGISTERS_TABLE_101[0], sizeof(ixMC_REGISTERS_TABLE_101)/sizeof(ixMC_REGISTERS_TABLE_101[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_102", REG_SMC, 0x3fcd4, &ixMC_REGISTERS_TABLE_102[0], sizeof(ixMC_REGISTERS_TABLE_102)/sizeof(ixMC_REGISTERS_TABLE_102[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_103", REG_SMC, 0x3fcd8, &ixMC_REGISTERS_TABLE_103[0], sizeof(ixMC_REGISTERS_TABLE_103)/sizeof(ixMC_REGISTERS_TABLE_103[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_104", REG_SMC, 0x3fcdc, &ixMC_REGISTERS_TABLE_104[0], sizeof(ixMC_REGISTERS_TABLE_104)/sizeof(ixMC_REGISTERS_TABLE_104[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_105", REG_SMC, 0x3fce0, &ixMC_REGISTERS_TABLE_105[0], sizeof(ixMC_REGISTERS_TABLE_105)/sizeof(ixMC_REGISTERS_TABLE_105[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_106", REG_SMC, 0x3fce4, &ixMC_REGISTERS_TABLE_106[0], sizeof(ixMC_REGISTERS_TABLE_106)/sizeof(ixMC_REGISTERS_TABLE_106[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_107", REG_SMC, 0x3fce8, &ixMC_REGISTERS_TABLE_107[0], sizeof(ixMC_REGISTERS_TABLE_107)/sizeof(ixMC_REGISTERS_TABLE_107[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_108", REG_SMC, 0x3fcec, &ixMC_REGISTERS_TABLE_108[0], sizeof(ixMC_REGISTERS_TABLE_108)/sizeof(ixMC_REGISTERS_TABLE_108[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_109", REG_SMC, 0x3fcf0, &ixMC_REGISTERS_TABLE_109[0], sizeof(ixMC_REGISTERS_TABLE_109)/sizeof(ixMC_REGISTERS_TABLE_109[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_110", REG_SMC, 0x3fcf4, &ixMC_REGISTERS_TABLE_110[0], sizeof(ixMC_REGISTERS_TABLE_110)/sizeof(ixMC_REGISTERS_TABLE_110[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_111", REG_SMC, 0x3fcf8, &ixMC_REGISTERS_TABLE_111[0], sizeof(ixMC_REGISTERS_TABLE_111)/sizeof(ixMC_REGISTERS_TABLE_111[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_112", REG_SMC, 0x3fcfc, &ixMC_REGISTERS_TABLE_112[0], sizeof(ixMC_REGISTERS_TABLE_112)/sizeof(ixMC_REGISTERS_TABLE_112[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_113", REG_SMC, 0x3fd00, &ixMC_REGISTERS_TABLE_113[0], sizeof(ixMC_REGISTERS_TABLE_113)/sizeof(ixMC_REGISTERS_TABLE_113[0]), 0, 0 },
+	{ "ixFAN_TABLE_1", REG_SMC, 0x3fd04, &ixFAN_TABLE_1[0], sizeof(ixFAN_TABLE_1)/sizeof(ixFAN_TABLE_1[0]), 0, 0 },
+	{ "ixFAN_TABLE_2", REG_SMC, 0x3fd08, &ixFAN_TABLE_2[0], sizeof(ixFAN_TABLE_2)/sizeof(ixFAN_TABLE_2[0]), 0, 0 },
+	{ "ixFAN_TABLE_3", REG_SMC, 0x3fd0c, &ixFAN_TABLE_3[0], sizeof(ixFAN_TABLE_3)/sizeof(ixFAN_TABLE_3[0]), 0, 0 },
+	{ "ixFAN_TABLE_4", REG_SMC, 0x3fd10, &ixFAN_TABLE_4[0], sizeof(ixFAN_TABLE_4)/sizeof(ixFAN_TABLE_4[0]), 0, 0 },
+	{ "ixFAN_TABLE_5", REG_SMC, 0x3fd14, &ixFAN_TABLE_5[0], sizeof(ixFAN_TABLE_5)/sizeof(ixFAN_TABLE_5[0]), 0, 0 },
+	{ "ixFAN_TABLE_6", REG_SMC, 0x3fd18, &ixFAN_TABLE_6[0], sizeof(ixFAN_TABLE_6)/sizeof(ixFAN_TABLE_6[0]), 0, 0 },
+	{ "ixFAN_TABLE_7", REG_SMC, 0x3fd1c, &ixFAN_TABLE_7[0], sizeof(ixFAN_TABLE_7)/sizeof(ixFAN_TABLE_7[0]), 0, 0 },
+	{ "ixFAN_TABLE_8", REG_SMC, 0x3fd20, &ixFAN_TABLE_8[0], sizeof(ixFAN_TABLE_8)/sizeof(ixFAN_TABLE_8[0]), 0, 0 },
+	{ "ixFAN_TABLE_9", REG_SMC, 0x3fd24, &ixFAN_TABLE_9[0], sizeof(ixFAN_TABLE_9)/sizeof(ixFAN_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_1", REG_SMC, 0x3fd28, &ixSOFT_REGISTERS_TABLE_1[0], sizeof(ixSOFT_REGISTERS_TABLE_1)/sizeof(ixSOFT_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_2", REG_SMC, 0x3fd2c, &ixSOFT_REGISTERS_TABLE_2[0], sizeof(ixSOFT_REGISTERS_TABLE_2)/sizeof(ixSOFT_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_3", REG_SMC, 0x3fd30, &ixSOFT_REGISTERS_TABLE_3[0], sizeof(ixSOFT_REGISTERS_TABLE_3)/sizeof(ixSOFT_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_4", REG_SMC, 0x3fd34, &ixSOFT_REGISTERS_TABLE_4[0], sizeof(ixSOFT_REGISTERS_TABLE_4)/sizeof(ixSOFT_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_5", REG_SMC, 0x3fd38, &ixSOFT_REGISTERS_TABLE_5[0], sizeof(ixSOFT_REGISTERS_TABLE_5)/sizeof(ixSOFT_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_6", REG_SMC, 0x3fd3c, &ixSOFT_REGISTERS_TABLE_6[0], sizeof(ixSOFT_REGISTERS_TABLE_6)/sizeof(ixSOFT_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_7", REG_SMC, 0x3fd40, &ixSOFT_REGISTERS_TABLE_7[0], sizeof(ixSOFT_REGISTERS_TABLE_7)/sizeof(ixSOFT_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_8", REG_SMC, 0x3fd44, &ixSOFT_REGISTERS_TABLE_8[0], sizeof(ixSOFT_REGISTERS_TABLE_8)/sizeof(ixSOFT_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_9", REG_SMC, 0x3fd48, &ixSOFT_REGISTERS_TABLE_9[0], sizeof(ixSOFT_REGISTERS_TABLE_9)/sizeof(ixSOFT_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_10", REG_SMC, 0x3fd4c, &ixSOFT_REGISTERS_TABLE_10[0], sizeof(ixSOFT_REGISTERS_TABLE_10)/sizeof(ixSOFT_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_11", REG_SMC, 0x3fd50, &ixSOFT_REGISTERS_TABLE_11[0], sizeof(ixSOFT_REGISTERS_TABLE_11)/sizeof(ixSOFT_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_12", REG_SMC, 0x3fd54, &ixSOFT_REGISTERS_TABLE_12[0], sizeof(ixSOFT_REGISTERS_TABLE_12)/sizeof(ixSOFT_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_13", REG_SMC, 0x3fd58, &ixSOFT_REGISTERS_TABLE_13[0], sizeof(ixSOFT_REGISTERS_TABLE_13)/sizeof(ixSOFT_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_14", REG_SMC, 0x3fd5c, &ixSOFT_REGISTERS_TABLE_14[0], sizeof(ixSOFT_REGISTERS_TABLE_14)/sizeof(ixSOFT_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_15", REG_SMC, 0x3fd60, &ixSOFT_REGISTERS_TABLE_15[0], sizeof(ixSOFT_REGISTERS_TABLE_15)/sizeof(ixSOFT_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_16", REG_SMC, 0x3fd64, &ixSOFT_REGISTERS_TABLE_16[0], sizeof(ixSOFT_REGISTERS_TABLE_16)/sizeof(ixSOFT_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_17", REG_SMC, 0x3fd68, &ixSOFT_REGISTERS_TABLE_17[0], sizeof(ixSOFT_REGISTERS_TABLE_17)/sizeof(ixSOFT_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_18", REG_SMC, 0x3fd6c, &ixSOFT_REGISTERS_TABLE_18[0], sizeof(ixSOFT_REGISTERS_TABLE_18)/sizeof(ixSOFT_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_19", REG_SMC, 0x3fd70, &ixSOFT_REGISTERS_TABLE_19[0], sizeof(ixSOFT_REGISTERS_TABLE_19)/sizeof(ixSOFT_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_20", REG_SMC, 0x3fd74, &ixSOFT_REGISTERS_TABLE_20[0], sizeof(ixSOFT_REGISTERS_TABLE_20)/sizeof(ixSOFT_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_21", REG_SMC, 0x3fd78, &ixSOFT_REGISTERS_TABLE_21[0], sizeof(ixSOFT_REGISTERS_TABLE_21)/sizeof(ixSOFT_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_22", REG_SMC, 0x3fd7c, &ixSOFT_REGISTERS_TABLE_22[0], sizeof(ixSOFT_REGISTERS_TABLE_22)/sizeof(ixSOFT_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_23", REG_SMC, 0x3fd80, &ixSOFT_REGISTERS_TABLE_23[0], sizeof(ixSOFT_REGISTERS_TABLE_23)/sizeof(ixSOFT_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_24", REG_SMC, 0x3fd84, &ixSOFT_REGISTERS_TABLE_24[0], sizeof(ixSOFT_REGISTERS_TABLE_24)/sizeof(ixSOFT_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_25", REG_SMC, 0x3fd88, &ixSOFT_REGISTERS_TABLE_25[0], sizeof(ixSOFT_REGISTERS_TABLE_25)/sizeof(ixSOFT_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_26", REG_SMC, 0x3fd8c, &ixSOFT_REGISTERS_TABLE_26[0], sizeof(ixSOFT_REGISTERS_TABLE_26)/sizeof(ixSOFT_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_27", REG_SMC, 0x3fd90, &ixSOFT_REGISTERS_TABLE_27[0], sizeof(ixSOFT_REGISTERS_TABLE_27)/sizeof(ixSOFT_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_28", REG_SMC, 0x3fd94, &ixSOFT_REGISTERS_TABLE_28[0], sizeof(ixSOFT_REGISTERS_TABLE_28)/sizeof(ixSOFT_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_29", REG_SMC, 0x3fd98, &ixSOFT_REGISTERS_TABLE_29[0], sizeof(ixSOFT_REGISTERS_TABLE_29)/sizeof(ixSOFT_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_30", REG_SMC, 0x3fd9c, &ixSOFT_REGISTERS_TABLE_30[0], sizeof(ixSOFT_REGISTERS_TABLE_30)/sizeof(ixSOFT_REGISTERS_TABLE_30[0]), 0, 0 },
+	{ "ixPM_FUSES_1", REG_SMC, 0x3fda0, &ixPM_FUSES_1[0], sizeof(ixPM_FUSES_1)/sizeof(ixPM_FUSES_1[0]), 0, 0 },
+	{ "ixPM_FUSES_2", REG_SMC, 0x3fda4, &ixPM_FUSES_2[0], sizeof(ixPM_FUSES_2)/sizeof(ixPM_FUSES_2[0]), 0, 0 },
+	{ "ixPM_FUSES_3", REG_SMC, 0x3fda8, &ixPM_FUSES_3[0], sizeof(ixPM_FUSES_3)/sizeof(ixPM_FUSES_3[0]), 0, 0 },
+	{ "ixPM_FUSES_4", REG_SMC, 0x3fdac, &ixPM_FUSES_4[0], sizeof(ixPM_FUSES_4)/sizeof(ixPM_FUSES_4[0]), 0, 0 },
+	{ "ixPM_FUSES_5", REG_SMC, 0x3fdb0, &ixPM_FUSES_5[0], sizeof(ixPM_FUSES_5)/sizeof(ixPM_FUSES_5[0]), 0, 0 },
+	{ "ixPM_FUSES_6", REG_SMC, 0x3fdb4, &ixPM_FUSES_6[0], sizeof(ixPM_FUSES_6)/sizeof(ixPM_FUSES_6[0]), 0, 0 },
+	{ "ixPM_FUSES_7", REG_SMC, 0x3fdb8, &ixPM_FUSES_7[0], sizeof(ixPM_FUSES_7)/sizeof(ixPM_FUSES_7[0]), 0, 0 },
+	{ "ixPM_FUSES_8", REG_SMC, 0x3fdbc, &ixPM_FUSES_8[0], sizeof(ixPM_FUSES_8)/sizeof(ixPM_FUSES_8[0]), 0, 0 },
+	{ "ixPM_FUSES_9", REG_SMC, 0x3fdc0, &ixPM_FUSES_9[0], sizeof(ixPM_FUSES_9)/sizeof(ixPM_FUSES_9[0]), 0, 0 },
+	{ "ixPM_FUSES_10", REG_SMC, 0x3fdc4, &ixPM_FUSES_10[0], sizeof(ixPM_FUSES_10)/sizeof(ixPM_FUSES_10[0]), 0, 0 },
+	{ "ixPM_FUSES_11", REG_SMC, 0x3fdc8, &ixPM_FUSES_11[0], sizeof(ixPM_FUSES_11)/sizeof(ixPM_FUSES_11[0]), 0, 0 },
+	{ "ixPM_FUSES_12", REG_SMC, 0x3fdcc, &ixPM_FUSES_12[0], sizeof(ixPM_FUSES_12)/sizeof(ixPM_FUSES_12[0]), 0, 0 },
+	{ "ixPM_FUSES_13", REG_SMC, 0x3fdd0, &ixPM_FUSES_13[0], sizeof(ixPM_FUSES_13)/sizeof(ixPM_FUSES_13[0]), 0, 0 },
+	{ "ixPM_FUSES_14", REG_SMC, 0x3fdd4, &ixPM_FUSES_14[0], sizeof(ixPM_FUSES_14)/sizeof(ixPM_FUSES_14[0]), 0, 0 },
+	{ "ixPM_FUSES_15", REG_SMC, 0x3fdd8, &ixPM_FUSES_15[0], sizeof(ixPM_FUSES_15)/sizeof(ixPM_FUSES_15[0]), 0, 0 },
+	{ "ixPM_FUSES_16", REG_SMC, 0x3fddc, &ixPM_FUSES_16[0], sizeof(ixPM_FUSES_16)/sizeof(ixPM_FUSES_16[0]), 0, 0 },
+	{ "ixPM_FUSES_17", REG_SMC, 0x3fde0, &ixPM_FUSES_17[0], sizeof(ixPM_FUSES_17)/sizeof(ixPM_FUSES_17[0]), 0, 0 },
+	{ "ixPM_FUSES_18", REG_SMC, 0x3fde4, &ixPM_FUSES_18[0], sizeof(ixPM_FUSES_18)/sizeof(ixPM_FUSES_18[0]), 0, 0 },
+	{ "ixPM_FUSES_19", REG_SMC, 0x3fde8, &ixPM_FUSES_19[0], sizeof(ixPM_FUSES_19)/sizeof(ixPM_FUSES_19[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_0", REG_SMC, 0x3fe00, &ixSMU_PM_STATUS_0[0], sizeof(ixSMU_PM_STATUS_0)/sizeof(ixSMU_PM_STATUS_0[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_1", REG_SMC, 0x3fe04, &ixSMU_PM_STATUS_1[0], sizeof(ixSMU_PM_STATUS_1)/sizeof(ixSMU_PM_STATUS_1[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_2", REG_SMC, 0x3fe08, &ixSMU_PM_STATUS_2[0], sizeof(ixSMU_PM_STATUS_2)/sizeof(ixSMU_PM_STATUS_2[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_3", REG_SMC, 0x3fe0c, &ixSMU_PM_STATUS_3[0], sizeof(ixSMU_PM_STATUS_3)/sizeof(ixSMU_PM_STATUS_3[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_4", REG_SMC, 0x3fe10, &ixSMU_PM_STATUS_4[0], sizeof(ixSMU_PM_STATUS_4)/sizeof(ixSMU_PM_STATUS_4[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_5", REG_SMC, 0x3fe14, &ixSMU_PM_STATUS_5[0], sizeof(ixSMU_PM_STATUS_5)/sizeof(ixSMU_PM_STATUS_5[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_6", REG_SMC, 0x3fe18, &ixSMU_PM_STATUS_6[0], sizeof(ixSMU_PM_STATUS_6)/sizeof(ixSMU_PM_STATUS_6[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_7", REG_SMC, 0x3fe1c, &ixSMU_PM_STATUS_7[0], sizeof(ixSMU_PM_STATUS_7)/sizeof(ixSMU_PM_STATUS_7[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_8", REG_SMC, 0x3fe20, &ixSMU_PM_STATUS_8[0], sizeof(ixSMU_PM_STATUS_8)/sizeof(ixSMU_PM_STATUS_8[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_9", REG_SMC, 0x3fe24, &ixSMU_PM_STATUS_9[0], sizeof(ixSMU_PM_STATUS_9)/sizeof(ixSMU_PM_STATUS_9[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_10", REG_SMC, 0x3fe28, &ixSMU_PM_STATUS_10[0], sizeof(ixSMU_PM_STATUS_10)/sizeof(ixSMU_PM_STATUS_10[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_11", REG_SMC, 0x3fe2c, &ixSMU_PM_STATUS_11[0], sizeof(ixSMU_PM_STATUS_11)/sizeof(ixSMU_PM_STATUS_11[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_12", REG_SMC, 0x3fe30, &ixSMU_PM_STATUS_12[0], sizeof(ixSMU_PM_STATUS_12)/sizeof(ixSMU_PM_STATUS_12[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_13", REG_SMC, 0x3fe34, &ixSMU_PM_STATUS_13[0], sizeof(ixSMU_PM_STATUS_13)/sizeof(ixSMU_PM_STATUS_13[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_14", REG_SMC, 0x3fe38, &ixSMU_PM_STATUS_14[0], sizeof(ixSMU_PM_STATUS_14)/sizeof(ixSMU_PM_STATUS_14[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_15", REG_SMC, 0x3fe3c, &ixSMU_PM_STATUS_15[0], sizeof(ixSMU_PM_STATUS_15)/sizeof(ixSMU_PM_STATUS_15[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_16", REG_SMC, 0x3fe40, &ixSMU_PM_STATUS_16[0], sizeof(ixSMU_PM_STATUS_16)/sizeof(ixSMU_PM_STATUS_16[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_17", REG_SMC, 0x3fe44, &ixSMU_PM_STATUS_17[0], sizeof(ixSMU_PM_STATUS_17)/sizeof(ixSMU_PM_STATUS_17[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_18", REG_SMC, 0x3fe48, &ixSMU_PM_STATUS_18[0], sizeof(ixSMU_PM_STATUS_18)/sizeof(ixSMU_PM_STATUS_18[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_19", REG_SMC, 0x3fe4c, &ixSMU_PM_STATUS_19[0], sizeof(ixSMU_PM_STATUS_19)/sizeof(ixSMU_PM_STATUS_19[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_20", REG_SMC, 0x3fe50, &ixSMU_PM_STATUS_20[0], sizeof(ixSMU_PM_STATUS_20)/sizeof(ixSMU_PM_STATUS_20[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_21", REG_SMC, 0x3fe54, &ixSMU_PM_STATUS_21[0], sizeof(ixSMU_PM_STATUS_21)/sizeof(ixSMU_PM_STATUS_21[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_22", REG_SMC, 0x3fe58, &ixSMU_PM_STATUS_22[0], sizeof(ixSMU_PM_STATUS_22)/sizeof(ixSMU_PM_STATUS_22[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_23", REG_SMC, 0x3fe5c, &ixSMU_PM_STATUS_23[0], sizeof(ixSMU_PM_STATUS_23)/sizeof(ixSMU_PM_STATUS_23[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_24", REG_SMC, 0x3fe60, &ixSMU_PM_STATUS_24[0], sizeof(ixSMU_PM_STATUS_24)/sizeof(ixSMU_PM_STATUS_24[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_25", REG_SMC, 0x3fe64, &ixSMU_PM_STATUS_25[0], sizeof(ixSMU_PM_STATUS_25)/sizeof(ixSMU_PM_STATUS_25[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_26", REG_SMC, 0x3fe68, &ixSMU_PM_STATUS_26[0], sizeof(ixSMU_PM_STATUS_26)/sizeof(ixSMU_PM_STATUS_26[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_27", REG_SMC, 0x3fe6c, &ixSMU_PM_STATUS_27[0], sizeof(ixSMU_PM_STATUS_27)/sizeof(ixSMU_PM_STATUS_27[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_28", REG_SMC, 0x3fe70, &ixSMU_PM_STATUS_28[0], sizeof(ixSMU_PM_STATUS_28)/sizeof(ixSMU_PM_STATUS_28[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_29", REG_SMC, 0x3fe74, &ixSMU_PM_STATUS_29[0], sizeof(ixSMU_PM_STATUS_29)/sizeof(ixSMU_PM_STATUS_29[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_30", REG_SMC, 0x3fe78, &ixSMU_PM_STATUS_30[0], sizeof(ixSMU_PM_STATUS_30)/sizeof(ixSMU_PM_STATUS_30[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_31", REG_SMC, 0x3fe7c, &ixSMU_PM_STATUS_31[0], sizeof(ixSMU_PM_STATUS_31)/sizeof(ixSMU_PM_STATUS_31[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_32", REG_SMC, 0x3fe80, &ixSMU_PM_STATUS_32[0], sizeof(ixSMU_PM_STATUS_32)/sizeof(ixSMU_PM_STATUS_32[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_33", REG_SMC, 0x3fe84, &ixSMU_PM_STATUS_33[0], sizeof(ixSMU_PM_STATUS_33)/sizeof(ixSMU_PM_STATUS_33[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_34", REG_SMC, 0x3fe88, &ixSMU_PM_STATUS_34[0], sizeof(ixSMU_PM_STATUS_34)/sizeof(ixSMU_PM_STATUS_34[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_35", REG_SMC, 0x3fe8c, &ixSMU_PM_STATUS_35[0], sizeof(ixSMU_PM_STATUS_35)/sizeof(ixSMU_PM_STATUS_35[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_36", REG_SMC, 0x3fe90, &ixSMU_PM_STATUS_36[0], sizeof(ixSMU_PM_STATUS_36)/sizeof(ixSMU_PM_STATUS_36[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_37", REG_SMC, 0x3fe94, &ixSMU_PM_STATUS_37[0], sizeof(ixSMU_PM_STATUS_37)/sizeof(ixSMU_PM_STATUS_37[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_38", REG_SMC, 0x3fe98, &ixSMU_PM_STATUS_38[0], sizeof(ixSMU_PM_STATUS_38)/sizeof(ixSMU_PM_STATUS_38[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_39", REG_SMC, 0x3fe9c, &ixSMU_PM_STATUS_39[0], sizeof(ixSMU_PM_STATUS_39)/sizeof(ixSMU_PM_STATUS_39[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_40", REG_SMC, 0x3fea0, &ixSMU_PM_STATUS_40[0], sizeof(ixSMU_PM_STATUS_40)/sizeof(ixSMU_PM_STATUS_40[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_41", REG_SMC, 0x3fea4, &ixSMU_PM_STATUS_41[0], sizeof(ixSMU_PM_STATUS_41)/sizeof(ixSMU_PM_STATUS_41[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_42", REG_SMC, 0x3fea8, &ixSMU_PM_STATUS_42[0], sizeof(ixSMU_PM_STATUS_42)/sizeof(ixSMU_PM_STATUS_42[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_43", REG_SMC, 0x3feac, &ixSMU_PM_STATUS_43[0], sizeof(ixSMU_PM_STATUS_43)/sizeof(ixSMU_PM_STATUS_43[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_44", REG_SMC, 0x3feb0, &ixSMU_PM_STATUS_44[0], sizeof(ixSMU_PM_STATUS_44)/sizeof(ixSMU_PM_STATUS_44[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_45", REG_SMC, 0x3feb4, &ixSMU_PM_STATUS_45[0], sizeof(ixSMU_PM_STATUS_45)/sizeof(ixSMU_PM_STATUS_45[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_46", REG_SMC, 0x3feb8, &ixSMU_PM_STATUS_46[0], sizeof(ixSMU_PM_STATUS_46)/sizeof(ixSMU_PM_STATUS_46[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_47", REG_SMC, 0x3febc, &ixSMU_PM_STATUS_47[0], sizeof(ixSMU_PM_STATUS_47)/sizeof(ixSMU_PM_STATUS_47[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_48", REG_SMC, 0x3fec0, &ixSMU_PM_STATUS_48[0], sizeof(ixSMU_PM_STATUS_48)/sizeof(ixSMU_PM_STATUS_48[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_49", REG_SMC, 0x3fec4, &ixSMU_PM_STATUS_49[0], sizeof(ixSMU_PM_STATUS_49)/sizeof(ixSMU_PM_STATUS_49[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_50", REG_SMC, 0x3fec8, &ixSMU_PM_STATUS_50[0], sizeof(ixSMU_PM_STATUS_50)/sizeof(ixSMU_PM_STATUS_50[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_51", REG_SMC, 0x3fecc, &ixSMU_PM_STATUS_51[0], sizeof(ixSMU_PM_STATUS_51)/sizeof(ixSMU_PM_STATUS_51[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_52", REG_SMC, 0x3fed0, &ixSMU_PM_STATUS_52[0], sizeof(ixSMU_PM_STATUS_52)/sizeof(ixSMU_PM_STATUS_52[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_53", REG_SMC, 0x3fed4, &ixSMU_PM_STATUS_53[0], sizeof(ixSMU_PM_STATUS_53)/sizeof(ixSMU_PM_STATUS_53[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_54", REG_SMC, 0x3fed8, &ixSMU_PM_STATUS_54[0], sizeof(ixSMU_PM_STATUS_54)/sizeof(ixSMU_PM_STATUS_54[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_55", REG_SMC, 0x3fedc, &ixSMU_PM_STATUS_55[0], sizeof(ixSMU_PM_STATUS_55)/sizeof(ixSMU_PM_STATUS_55[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_56", REG_SMC, 0x3fee0, &ixSMU_PM_STATUS_56[0], sizeof(ixSMU_PM_STATUS_56)/sizeof(ixSMU_PM_STATUS_56[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_57", REG_SMC, 0x3fee4, &ixSMU_PM_STATUS_57[0], sizeof(ixSMU_PM_STATUS_57)/sizeof(ixSMU_PM_STATUS_57[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_58", REG_SMC, 0x3fee8, &ixSMU_PM_STATUS_58[0], sizeof(ixSMU_PM_STATUS_58)/sizeof(ixSMU_PM_STATUS_58[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_59", REG_SMC, 0x3feec, &ixSMU_PM_STATUS_59[0], sizeof(ixSMU_PM_STATUS_59)/sizeof(ixSMU_PM_STATUS_59[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_60", REG_SMC, 0x3fef0, &ixSMU_PM_STATUS_60[0], sizeof(ixSMU_PM_STATUS_60)/sizeof(ixSMU_PM_STATUS_60[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_61", REG_SMC, 0x3fef4, &ixSMU_PM_STATUS_61[0], sizeof(ixSMU_PM_STATUS_61)/sizeof(ixSMU_PM_STATUS_61[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_62", REG_SMC, 0x3fef8, &ixSMU_PM_STATUS_62[0], sizeof(ixSMU_PM_STATUS_62)/sizeof(ixSMU_PM_STATUS_62[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_63", REG_SMC, 0x3fefc, &ixSMU_PM_STATUS_63[0], sizeof(ixSMU_PM_STATUS_63)/sizeof(ixSMU_PM_STATUS_63[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_64", REG_SMC, 0x3ff00, &ixSMU_PM_STATUS_64[0], sizeof(ixSMU_PM_STATUS_64)/sizeof(ixSMU_PM_STATUS_64[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_65", REG_SMC, 0x3ff04, &ixSMU_PM_STATUS_65[0], sizeof(ixSMU_PM_STATUS_65)/sizeof(ixSMU_PM_STATUS_65[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_66", REG_SMC, 0x3ff08, &ixSMU_PM_STATUS_66[0], sizeof(ixSMU_PM_STATUS_66)/sizeof(ixSMU_PM_STATUS_66[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_67", REG_SMC, 0x3ff0c, &ixSMU_PM_STATUS_67[0], sizeof(ixSMU_PM_STATUS_67)/sizeof(ixSMU_PM_STATUS_67[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_68", REG_SMC, 0x3ff10, &ixSMU_PM_STATUS_68[0], sizeof(ixSMU_PM_STATUS_68)/sizeof(ixSMU_PM_STATUS_68[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_69", REG_SMC, 0x3ff14, &ixSMU_PM_STATUS_69[0], sizeof(ixSMU_PM_STATUS_69)/sizeof(ixSMU_PM_STATUS_69[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_70", REG_SMC, 0x3ff18, &ixSMU_PM_STATUS_70[0], sizeof(ixSMU_PM_STATUS_70)/sizeof(ixSMU_PM_STATUS_70[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_71", REG_SMC, 0x3ff1c, &ixSMU_PM_STATUS_71[0], sizeof(ixSMU_PM_STATUS_71)/sizeof(ixSMU_PM_STATUS_71[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_72", REG_SMC, 0x3ff20, &ixSMU_PM_STATUS_72[0], sizeof(ixSMU_PM_STATUS_72)/sizeof(ixSMU_PM_STATUS_72[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_73", REG_SMC, 0x3ff24, &ixSMU_PM_STATUS_73[0], sizeof(ixSMU_PM_STATUS_73)/sizeof(ixSMU_PM_STATUS_73[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_74", REG_SMC, 0x3ff28, &ixSMU_PM_STATUS_74[0], sizeof(ixSMU_PM_STATUS_74)/sizeof(ixSMU_PM_STATUS_74[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_75", REG_SMC, 0x3ff2c, &ixSMU_PM_STATUS_75[0], sizeof(ixSMU_PM_STATUS_75)/sizeof(ixSMU_PM_STATUS_75[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_76", REG_SMC, 0x3ff30, &ixSMU_PM_STATUS_76[0], sizeof(ixSMU_PM_STATUS_76)/sizeof(ixSMU_PM_STATUS_76[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_77", REG_SMC, 0x3ff34, &ixSMU_PM_STATUS_77[0], sizeof(ixSMU_PM_STATUS_77)/sizeof(ixSMU_PM_STATUS_77[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_78", REG_SMC, 0x3ff38, &ixSMU_PM_STATUS_78[0], sizeof(ixSMU_PM_STATUS_78)/sizeof(ixSMU_PM_STATUS_78[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_79", REG_SMC, 0x3ff3c, &ixSMU_PM_STATUS_79[0], sizeof(ixSMU_PM_STATUS_79)/sizeof(ixSMU_PM_STATUS_79[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_80", REG_SMC, 0x3ff40, &ixSMU_PM_STATUS_80[0], sizeof(ixSMU_PM_STATUS_80)/sizeof(ixSMU_PM_STATUS_80[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_81", REG_SMC, 0x3ff44, &ixSMU_PM_STATUS_81[0], sizeof(ixSMU_PM_STATUS_81)/sizeof(ixSMU_PM_STATUS_81[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_82", REG_SMC, 0x3ff48, &ixSMU_PM_STATUS_82[0], sizeof(ixSMU_PM_STATUS_82)/sizeof(ixSMU_PM_STATUS_82[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_83", REG_SMC, 0x3ff4c, &ixSMU_PM_STATUS_83[0], sizeof(ixSMU_PM_STATUS_83)/sizeof(ixSMU_PM_STATUS_83[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_84", REG_SMC, 0x3ff50, &ixSMU_PM_STATUS_84[0], sizeof(ixSMU_PM_STATUS_84)/sizeof(ixSMU_PM_STATUS_84[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_85", REG_SMC, 0x3ff54, &ixSMU_PM_STATUS_85[0], sizeof(ixSMU_PM_STATUS_85)/sizeof(ixSMU_PM_STATUS_85[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_86", REG_SMC, 0x3ff58, &ixSMU_PM_STATUS_86[0], sizeof(ixSMU_PM_STATUS_86)/sizeof(ixSMU_PM_STATUS_86[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_87", REG_SMC, 0x3ff5c, &ixSMU_PM_STATUS_87[0], sizeof(ixSMU_PM_STATUS_87)/sizeof(ixSMU_PM_STATUS_87[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_88", REG_SMC, 0x3ff60, &ixSMU_PM_STATUS_88[0], sizeof(ixSMU_PM_STATUS_88)/sizeof(ixSMU_PM_STATUS_88[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_89", REG_SMC, 0x3ff64, &ixSMU_PM_STATUS_89[0], sizeof(ixSMU_PM_STATUS_89)/sizeof(ixSMU_PM_STATUS_89[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_90", REG_SMC, 0x3ff68, &ixSMU_PM_STATUS_90[0], sizeof(ixSMU_PM_STATUS_90)/sizeof(ixSMU_PM_STATUS_90[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_91", REG_SMC, 0x3ff6c, &ixSMU_PM_STATUS_91[0], sizeof(ixSMU_PM_STATUS_91)/sizeof(ixSMU_PM_STATUS_91[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_92", REG_SMC, 0x3ff70, &ixSMU_PM_STATUS_92[0], sizeof(ixSMU_PM_STATUS_92)/sizeof(ixSMU_PM_STATUS_92[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_93", REG_SMC, 0x3ff74, &ixSMU_PM_STATUS_93[0], sizeof(ixSMU_PM_STATUS_93)/sizeof(ixSMU_PM_STATUS_93[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_94", REG_SMC, 0x3ff78, &ixSMU_PM_STATUS_94[0], sizeof(ixSMU_PM_STATUS_94)/sizeof(ixSMU_PM_STATUS_94[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_95", REG_SMC, 0x3ff7c, &ixSMU_PM_STATUS_95[0], sizeof(ixSMU_PM_STATUS_95)/sizeof(ixSMU_PM_STATUS_95[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_96", REG_SMC, 0x3ff80, &ixSMU_PM_STATUS_96[0], sizeof(ixSMU_PM_STATUS_96)/sizeof(ixSMU_PM_STATUS_96[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_97", REG_SMC, 0x3ff84, &ixSMU_PM_STATUS_97[0], sizeof(ixSMU_PM_STATUS_97)/sizeof(ixSMU_PM_STATUS_97[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_98", REG_SMC, 0x3ff88, &ixSMU_PM_STATUS_98[0], sizeof(ixSMU_PM_STATUS_98)/sizeof(ixSMU_PM_STATUS_98[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_99", REG_SMC, 0x3ff8c, &ixSMU_PM_STATUS_99[0], sizeof(ixSMU_PM_STATUS_99)/sizeof(ixSMU_PM_STATUS_99[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_100", REG_SMC, 0x3ff90, &ixSMU_PM_STATUS_100[0], sizeof(ixSMU_PM_STATUS_100)/sizeof(ixSMU_PM_STATUS_100[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_101", REG_SMC, 0x3ff94, &ixSMU_PM_STATUS_101[0], sizeof(ixSMU_PM_STATUS_101)/sizeof(ixSMU_PM_STATUS_101[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_102", REG_SMC, 0x3ff98, &ixSMU_PM_STATUS_102[0], sizeof(ixSMU_PM_STATUS_102)/sizeof(ixSMU_PM_STATUS_102[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_103", REG_SMC, 0x3ff9c, &ixSMU_PM_STATUS_103[0], sizeof(ixSMU_PM_STATUS_103)/sizeof(ixSMU_PM_STATUS_103[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_104", REG_SMC, 0x3ffa0, &ixSMU_PM_STATUS_104[0], sizeof(ixSMU_PM_STATUS_104)/sizeof(ixSMU_PM_STATUS_104[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_105", REG_SMC, 0x3ffa4, &ixSMU_PM_STATUS_105[0], sizeof(ixSMU_PM_STATUS_105)/sizeof(ixSMU_PM_STATUS_105[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_106", REG_SMC, 0x3ffa8, &ixSMU_PM_STATUS_106[0], sizeof(ixSMU_PM_STATUS_106)/sizeof(ixSMU_PM_STATUS_106[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_107", REG_SMC, 0x3ffac, &ixSMU_PM_STATUS_107[0], sizeof(ixSMU_PM_STATUS_107)/sizeof(ixSMU_PM_STATUS_107[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_108", REG_SMC, 0x3ffb0, &ixSMU_PM_STATUS_108[0], sizeof(ixSMU_PM_STATUS_108)/sizeof(ixSMU_PM_STATUS_108[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_109", REG_SMC, 0x3ffb4, &ixSMU_PM_STATUS_109[0], sizeof(ixSMU_PM_STATUS_109)/sizeof(ixSMU_PM_STATUS_109[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_110", REG_SMC, 0x3ffb8, &ixSMU_PM_STATUS_110[0], sizeof(ixSMU_PM_STATUS_110)/sizeof(ixSMU_PM_STATUS_110[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_111", REG_SMC, 0x3ffbc, &ixSMU_PM_STATUS_111[0], sizeof(ixSMU_PM_STATUS_111)/sizeof(ixSMU_PM_STATUS_111[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_112", REG_SMC, 0x3ffc0, &ixSMU_PM_STATUS_112[0], sizeof(ixSMU_PM_STATUS_112)/sizeof(ixSMU_PM_STATUS_112[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_113", REG_SMC, 0x3ffc4, &ixSMU_PM_STATUS_113[0], sizeof(ixSMU_PM_STATUS_113)/sizeof(ixSMU_PM_STATUS_113[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_114", REG_SMC, 0x3ffc8, &ixSMU_PM_STATUS_114[0], sizeof(ixSMU_PM_STATUS_114)/sizeof(ixSMU_PM_STATUS_114[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_115", REG_SMC, 0x3ffcc, &ixSMU_PM_STATUS_115[0], sizeof(ixSMU_PM_STATUS_115)/sizeof(ixSMU_PM_STATUS_115[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_116", REG_SMC, 0x3ffd0, &ixSMU_PM_STATUS_116[0], sizeof(ixSMU_PM_STATUS_116)/sizeof(ixSMU_PM_STATUS_116[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_117", REG_SMC, 0x3ffd4, &ixSMU_PM_STATUS_117[0], sizeof(ixSMU_PM_STATUS_117)/sizeof(ixSMU_PM_STATUS_117[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_118", REG_SMC, 0x3ffd8, &ixSMU_PM_STATUS_118[0], sizeof(ixSMU_PM_STATUS_118)/sizeof(ixSMU_PM_STATUS_118[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_119", REG_SMC, 0x3ffdc, &ixSMU_PM_STATUS_119[0], sizeof(ixSMU_PM_STATUS_119)/sizeof(ixSMU_PM_STATUS_119[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_120", REG_SMC, 0x3ffe0, &ixSMU_PM_STATUS_120[0], sizeof(ixSMU_PM_STATUS_120)/sizeof(ixSMU_PM_STATUS_120[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_121", REG_SMC, 0x3ffe4, &ixSMU_PM_STATUS_121[0], sizeof(ixSMU_PM_STATUS_121)/sizeof(ixSMU_PM_STATUS_121[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_122", REG_SMC, 0x3ffe8, &ixSMU_PM_STATUS_122[0], sizeof(ixSMU_PM_STATUS_122)/sizeof(ixSMU_PM_STATUS_122[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_123", REG_SMC, 0x3ffec, &ixSMU_PM_STATUS_123[0], sizeof(ixSMU_PM_STATUS_123)/sizeof(ixSMU_PM_STATUS_123[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_124", REG_SMC, 0x3fff0, &ixSMU_PM_STATUS_124[0], sizeof(ixSMU_PM_STATUS_124)/sizeof(ixSMU_PM_STATUS_124[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_125", REG_SMC, 0x3fff4, &ixSMU_PM_STATUS_125[0], sizeof(ixSMU_PM_STATUS_125)/sizeof(ixSMU_PM_STATUS_125[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_126", REG_SMC, 0x3fff8, &ixSMU_PM_STATUS_126[0], sizeof(ixSMU_PM_STATUS_126)/sizeof(ixSMU_PM_STATUS_126[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_127", REG_SMC, 0x3fffc, &ixSMU_PM_STATUS_127[0], sizeof(ixSMU_PM_STATUS_127)/sizeof(ixSMU_PM_STATUS_127[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_INDEX", REG_MMIO, 0x80, &mmGCK_SMC_IND_INDEX[0], sizeof(mmGCK_SMC_IND_INDEX)/sizeof(mmGCK_SMC_IND_INDEX[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_0", REG_MMIO, 0x80, &mmSMC_IND_INDEX_0[0], sizeof(mmSMC_IND_INDEX_0)/sizeof(mmSMC_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX", REG_MMIO, 0x80, &mmSMC_IND_INDEX[0], sizeof(mmSMC_IND_INDEX)/sizeof(mmSMC_IND_INDEX[0]), 0, 0 },
+	{ "ixSMC_SYSCON_RESET_CNTL", REG_SMC, 0x80000000, &ixSMC_SYSCON_RESET_CNTL[0], sizeof(ixSMC_SYSCON_RESET_CNTL)/sizeof(ixSMC_SYSCON_RESET_CNTL[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_0", REG_SMC, 0x80000004, &ixSMC_SYSCON_CLOCK_CNTL_0[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_0)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_0[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_1", REG_SMC, 0x80000008, &ixSMC_SYSCON_CLOCK_CNTL_1[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_1)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_1[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_2", REG_SMC, 0x8000000c, &ixSMC_SYSCON_CLOCK_CNTL_2[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_2)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_2[0]), 0, 0 },
+	{ "ixSMC_SYSCON_MISC_CNTL", REG_SMC, 0x80000010, NULL, 0, 0, 0 },
+	{ "ixSMC_SYSCON_MSG_ARG_0", REG_SMC, 0x80000068, &ixSMC_SYSCON_MSG_ARG_0[0], sizeof(ixSMC_SYSCON_MSG_ARG_0)/sizeof(ixSMC_SYSCON_MSG_ARG_0[0]), 0, 0 },
+	{ "ixSMC_PC_C", REG_SMC, 0x80000370, &ixSMC_PC_C[0], sizeof(ixSMC_PC_C)/sizeof(ixSMC_PC_C[0]), 0, 0 },
+	{ "ixSMC_SCRATCH9", REG_SMC, 0x80000424, &ixSMC_SCRATCH9[0], sizeof(ixSMC_SCRATCH9)/sizeof(ixSMC_SCRATCH9[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_DATA", REG_MMIO, 0x81, &mmGCK_SMC_IND_DATA[0], sizeof(mmGCK_SMC_IND_DATA)/sizeof(mmGCK_SMC_IND_DATA[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_0", REG_MMIO, 0x81, &mmSMC_IND_DATA_0[0], sizeof(mmSMC_IND_DATA_0)/sizeof(mmSMC_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMC_IND_DATA", REG_MMIO, 0x81, &mmSMC_IND_DATA[0], sizeof(mmSMC_IND_DATA)/sizeof(mmSMC_IND_DATA[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_1", REG_MMIO, 0x82, &mmSMC_IND_INDEX_1[0], sizeof(mmSMC_IND_INDEX_1)/sizeof(mmSMC_IND_INDEX_1[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_1", REG_MMIO, 0x83, &mmSMC_IND_DATA_1[0], sizeof(mmSMC_IND_DATA_1)/sizeof(mmSMC_IND_DATA_1[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_2", REG_MMIO, 0x84, &mmSMC_IND_INDEX_2[0], sizeof(mmSMC_IND_INDEX_2)/sizeof(mmSMC_IND_INDEX_2[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_2", REG_MMIO, 0x85, &mmSMC_IND_DATA_2[0], sizeof(mmSMC_IND_DATA_2)/sizeof(mmSMC_IND_DATA_2[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_3", REG_MMIO, 0x86, &mmSMC_IND_INDEX_3[0], sizeof(mmSMC_IND_INDEX_3)/sizeof(mmSMC_IND_INDEX_3[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_3", REG_MMIO, 0x87, &mmSMC_IND_DATA_3[0], sizeof(mmSMC_IND_DATA_3)/sizeof(mmSMC_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_4", REG_MMIO, 0x88, &mmSMC_IND_INDEX_4[0], sizeof(mmSMC_IND_INDEX_4)/sizeof(mmSMC_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_4", REG_MMIO, 0x89, &mmSMC_IND_DATA_4[0], sizeof(mmSMC_IND_DATA_4)/sizeof(mmSMC_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_5", REG_MMIO, 0x8a, &mmSMC_IND_INDEX_5[0], sizeof(mmSMC_IND_INDEX_5)/sizeof(mmSMC_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_5", REG_MMIO, 0x8b, &mmSMC_IND_DATA_5[0], sizeof(mmSMC_IND_DATA_5)/sizeof(mmSMC_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_6", REG_MMIO, 0x8c, &mmSMC_IND_INDEX_6[0], sizeof(mmSMC_IND_INDEX_6)/sizeof(mmSMC_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_6", REG_MMIO, 0x8d, &mmSMC_IND_DATA_6[0], sizeof(mmSMC_IND_DATA_6)/sizeof(mmSMC_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_7", REG_MMIO, 0x8e, &mmSMC_IND_INDEX_7[0], sizeof(mmSMC_IND_INDEX_7)/sizeof(mmSMC_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_7", REG_MMIO, 0x8f, &mmSMC_IND_DATA_7[0], sizeof(mmSMC_IND_DATA_7)/sizeof(mmSMC_IND_DATA_7[0]), 0, 0 },
+	{ "mmSMC_IND_ACCESS_CNTL", REG_MMIO, 0x90, &mmSMC_IND_ACCESS_CNTL[0], sizeof(mmSMC_IND_ACCESS_CNTL)/sizeof(mmSMC_IND_ACCESS_CNTL[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_11", REG_MMIO, 0x91, &mmSMC_MSG_ARG_11[0], sizeof(mmSMC_MSG_ARG_11)/sizeof(mmSMC_MSG_ARG_11[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_0", REG_MMIO, 0x94, &mmSMC_MESSAGE_0[0], sizeof(mmSMC_MESSAGE_0)/sizeof(mmSMC_MESSAGE_0[0]), 0, 0 },
+	{ "mmSMC_RESP_0", REG_MMIO, 0x95, &mmSMC_RESP_0[0], sizeof(mmSMC_RESP_0)/sizeof(mmSMC_RESP_0[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_1", REG_MMIO, 0x96, &mmSMC_MESSAGE_1[0], sizeof(mmSMC_MESSAGE_1)/sizeof(mmSMC_MESSAGE_1[0]), 0, 0 },
+	{ "mmSMC_RESP_1", REG_MMIO, 0x97, &mmSMC_RESP_1[0], sizeof(mmSMC_RESP_1)/sizeof(mmSMC_RESP_1[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_2", REG_MMIO, 0x98, &mmSMC_MESSAGE_2[0], sizeof(mmSMC_MESSAGE_2)/sizeof(mmSMC_MESSAGE_2[0]), 0, 0 },
+	{ "mmSMC_RESP_2", REG_MMIO, 0x99, &mmSMC_RESP_2[0], sizeof(mmSMC_RESP_2)/sizeof(mmSMC_RESP_2[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_3", REG_MMIO, 0x9a, &mmSMC_MESSAGE_3[0], sizeof(mmSMC_MESSAGE_3)/sizeof(mmSMC_MESSAGE_3[0]), 0, 0 },
+	{ "mmSMC_RESP_3", REG_MMIO, 0x9b, &mmSMC_RESP_3[0], sizeof(mmSMC_RESP_3)/sizeof(mmSMC_RESP_3[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_4", REG_MMIO, 0x9c, &mmSMC_MESSAGE_4[0], sizeof(mmSMC_MESSAGE_4)/sizeof(mmSMC_MESSAGE_4[0]), 0, 0 },
+	{ "mmSMC_RESP_4", REG_MMIO, 0x9d, &mmSMC_RESP_4[0], sizeof(mmSMC_RESP_4)/sizeof(mmSMC_RESP_4[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_5", REG_MMIO, 0x9e, &mmSMC_MESSAGE_5[0], sizeof(mmSMC_MESSAGE_5)/sizeof(mmSMC_MESSAGE_5[0]), 0, 0 },
+	{ "mmSMC_RESP_5", REG_MMIO, 0x9f, &mmSMC_RESP_5[0], sizeof(mmSMC_RESP_5)/sizeof(mmSMC_RESP_5[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_6", REG_MMIO, 0xa0, &mmSMC_MESSAGE_6[0], sizeof(mmSMC_MESSAGE_6)/sizeof(mmSMC_MESSAGE_6[0]), 0, 0 },
+	{ "mmSMC_RESP_6", REG_MMIO, 0xa1, &mmSMC_RESP_6[0], sizeof(mmSMC_RESP_6)/sizeof(mmSMC_RESP_6[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_7", REG_MMIO, 0xa2, &mmSMC_MESSAGE_7[0], sizeof(mmSMC_MESSAGE_7)/sizeof(mmSMC_MESSAGE_7[0]), 0, 0 },
+	{ "mmSMC_RESP_7", REG_MMIO, 0xa3, &mmSMC_RESP_7[0], sizeof(mmSMC_RESP_7)/sizeof(mmSMC_RESP_7[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_0", REG_MMIO, 0xa4, &mmSMC_MSG_ARG_0[0], sizeof(mmSMC_MSG_ARG_0)/sizeof(mmSMC_MSG_ARG_0[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_1", REG_MMIO, 0xa5, &mmSMC_MSG_ARG_1[0], sizeof(mmSMC_MSG_ARG_1)/sizeof(mmSMC_MSG_ARG_1[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_2", REG_MMIO, 0xa6, &mmSMC_MSG_ARG_2[0], sizeof(mmSMC_MSG_ARG_2)/sizeof(mmSMC_MSG_ARG_2[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_3", REG_MMIO, 0xa7, &mmSMC_MSG_ARG_3[0], sizeof(mmSMC_MSG_ARG_3)/sizeof(mmSMC_MSG_ARG_3[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_4", REG_MMIO, 0xa8, &mmSMC_MSG_ARG_4[0], sizeof(mmSMC_MSG_ARG_4)/sizeof(mmSMC_MSG_ARG_4[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_5", REG_MMIO, 0xa9, &mmSMC_MSG_ARG_5[0], sizeof(mmSMC_MSG_ARG_5)/sizeof(mmSMC_MSG_ARG_5[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_6", REG_MMIO, 0xaa, &mmSMC_MSG_ARG_6[0], sizeof(mmSMC_MSG_ARG_6)/sizeof(mmSMC_MSG_ARG_6[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_7", REG_MMIO, 0xab, &mmSMC_MSG_ARG_7[0], sizeof(mmSMC_MSG_ARG_7)/sizeof(mmSMC_MSG_ARG_7[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_8", REG_MMIO, 0xb5, &mmSMC_MESSAGE_8[0], sizeof(mmSMC_MESSAGE_8)/sizeof(mmSMC_MESSAGE_8[0]), 0, 0 },
+	{ "mmSMC_RESP_8", REG_MMIO, 0xb6, &mmSMC_RESP_8[0], sizeof(mmSMC_RESP_8)/sizeof(mmSMC_RESP_8[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_9", REG_MMIO, 0xb7, &mmSMC_MESSAGE_9[0], sizeof(mmSMC_MESSAGE_9)/sizeof(mmSMC_MESSAGE_9[0]), 0, 0 },
+	{ "mmSMC_RESP_9", REG_MMIO, 0xb8, &mmSMC_RESP_9[0], sizeof(mmSMC_RESP_9)/sizeof(mmSMC_RESP_9[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_10", REG_MMIO, 0xb9, &mmSMC_MESSAGE_10[0], sizeof(mmSMC_MESSAGE_10)/sizeof(mmSMC_MESSAGE_10[0]), 0, 0 },
+	{ "mmSMC_RESP_10", REG_MMIO, 0xba, &mmSMC_RESP_10[0], sizeof(mmSMC_RESP_10)/sizeof(mmSMC_RESP_10[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_11", REG_MMIO, 0xbb, &mmSMC_MESSAGE_11[0], sizeof(mmSMC_MESSAGE_11)/sizeof(mmSMC_MESSAGE_11[0]), 0, 0 },
+	{ "mmSMC_RESP_11", REG_MMIO, 0xbc, &mmSMC_RESP_11[0], sizeof(mmSMC_RESP_11)/sizeof(mmSMC_RESP_11[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_8", REG_MMIO, 0xbd, &mmSMC_MSG_ARG_8[0], sizeof(mmSMC_MSG_ARG_8)/sizeof(mmSMC_MSG_ARG_8[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_9", REG_MMIO, 0xbe, &mmSMC_MSG_ARG_9[0], sizeof(mmSMC_MSG_ARG_9)/sizeof(mmSMC_MSG_ARG_9[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_10", REG_MMIO, 0xbf, &mmSMC_MSG_ARG_10[0], sizeof(mmSMC_MSG_ARG_10)/sizeof(mmSMC_MSG_ARG_10[0]), 0, 0 },
+	{ "ixRCU_UC_EVENTS", REG_SMC, 0xc0000004, &ixRCU_UC_EVENTS[0], sizeof(ixRCU_UC_EVENTS)/sizeof(ixRCU_UC_EVENTS[0]), 0, 0 },
+	{ "ixRCU_MISC_CTRL", REG_SMC, 0xc0000010, &ixRCU_MISC_CTRL[0], sizeof(ixRCU_MISC_CTRL)/sizeof(ixRCU_MISC_CTRL[0]), 0, 0 },
+	{ "ixCC_RCU_FUSES", REG_SMC, 0xc00c0000, &ixCC_RCU_FUSES[0], sizeof(ixCC_RCU_FUSES)/sizeof(ixCC_RCU_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_MISC_FUSES", REG_SMC, 0xc00c0004, &ixCC_SMU_MISC_FUSES[0], sizeof(ixCC_SMU_MISC_FUSES)/sizeof(ixCC_SMU_MISC_FUSES[0]), 0, 0 },
+	{ "ixCC_SCLK_VID_FUSES", REG_SMC, 0xc00c0008, &ixCC_SCLK_VID_FUSES[0], sizeof(ixCC_SCLK_VID_FUSES)/sizeof(ixCC_SCLK_VID_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOCCFG_FUSES", REG_SMC, 0xc00c000c, &ixCC_GIO_IOCCFG_FUSES[0], sizeof(ixCC_GIO_IOCCFG_FUSES)/sizeof(ixCC_GIO_IOCCFG_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOC_FUSES", REG_SMC, 0xc00c0010, &ixCC_GIO_IOC_FUSES[0], sizeof(ixCC_GIO_IOC_FUSES)/sizeof(ixCC_GIO_IOC_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_TST_EFUSE1_MISC", REG_SMC, 0xc00c001c, &ixCC_SMU_TST_EFUSE1_MISC[0], sizeof(ixCC_SMU_TST_EFUSE1_MISC)/sizeof(ixCC_SMU_TST_EFUSE1_MISC[0]), 0, 0 },
+	{ "ixCC_TST_ID_STRAPS", REG_SMC, 0xc00c0020, &ixCC_TST_ID_STRAPS[0], sizeof(ixCC_TST_ID_STRAPS)/sizeof(ixCC_TST_ID_STRAPS[0]), 0, 0 },
+	{ "ixCC_FCTRL_FUSES", REG_SMC, 0xc00c0024, &ixCC_FCTRL_FUSES[0], sizeof(ixCC_FCTRL_FUSES)/sizeof(ixCC_FCTRL_FUSES[0]), 0, 0 },
+	{ "ixSMU_EFUSE_0", REG_SMC, 0xc0100000, &ixSMU_EFUSE_0[0], sizeof(ixSMU_EFUSE_0)/sizeof(ixSMU_EFUSE_0[0]), 0, 0 },
+	{ "ixGENERAL_PWRMGT", REG_SMC, 0xc0200000, &ixGENERAL_PWRMGT[0], sizeof(ixGENERAL_PWRMGT)/sizeof(ixGENERAL_PWRMGT[0]), 0, 0 },
+	{ "ixCNB_PWRMGT_CNTL", REG_SMC, 0xc0200004, &ixCNB_PWRMGT_CNTL[0], sizeof(ixCNB_PWRMGT_CNTL)/sizeof(ixCNB_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixSCLK_PWRMGT_CNTL", REG_SMC, 0xc0200008, &ixSCLK_PWRMGT_CNTL[0], sizeof(ixSCLK_PWRMGT_CNTL)/sizeof(ixSCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX", REG_SMC, 0xc0200014, &ixTARGET_AND_CURRENT_PROFILE_INDEX[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX[0]), 0, 0 },
+	{ "ixPLL_TEST_CNTL", REG_SMC, 0xc020003c, &ixPLL_TEST_CNTL[0], sizeof(ixPLL_TEST_CNTL)/sizeof(ixPLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixCG_STATIC_SCREEN_PARAMETER", REG_SMC, 0xc0200044, &ixCG_STATIC_SCREEN_PARAMETER[0], sizeof(ixCG_STATIC_SCREEN_PARAMETER)/sizeof(ixCG_STATIC_SCREEN_PARAMETER[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL", REG_SMC, 0xc0200060, &ixCG_DISPLAY_GAP_CNTL[0], sizeof(ixCG_DISPLAY_GAP_CNTL)/sizeof(ixCG_DISPLAY_GAP_CNTL[0]), 0, 0 },
+	{ "ixCG_ACPI_CNTL", REG_SMC, 0xc0200064, &ixCG_ACPI_CNTL[0], sizeof(ixCG_ACPI_CNTL)/sizeof(ixCG_ACPI_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc0200080, &ixSCLK_DEEP_SLEEP_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200084, &ixSCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL2)/sizeof(ixSCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_MISC_CNTL", REG_SMC, 0xc0200088, &ixSCLK_DEEP_SLEEP_MISC_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc020008c, &ixLCLK_DEEP_SLEEP_CNTL[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL)/sizeof(ixLCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL3", REG_SMC, 0xc020009c, &ixSCLK_DEEP_SLEEP_CNTL3[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL3)/sizeof(ixSCLK_DEEP_SLEEP_CNTL3[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_1", REG_SMC, 0xc02000f0, &ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0]), 0, 0 },
+	{ "ixCG_ULV_PARAMETER", REG_SMC, 0xc020015c, &ixCG_ULV_PARAMETER[0], sizeof(ixCG_ULV_PARAMETER)/sizeof(ixCG_ULV_PARAMETER[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_0", REG_SMC, 0xc02001a8, &ixCG_FREQ_TRAN_VOTING_0[0], sizeof(ixCG_FREQ_TRAN_VOTING_0)/sizeof(ixCG_FREQ_TRAN_VOTING_0[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_1", REG_SMC, 0xc02001ac, &ixCG_FREQ_TRAN_VOTING_1[0], sizeof(ixCG_FREQ_TRAN_VOTING_1)/sizeof(ixCG_FREQ_TRAN_VOTING_1[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_2", REG_SMC, 0xc02001b0, &ixCG_FREQ_TRAN_VOTING_2[0], sizeof(ixCG_FREQ_TRAN_VOTING_2)/sizeof(ixCG_FREQ_TRAN_VOTING_2[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_3", REG_SMC, 0xc02001b4, &ixCG_FREQ_TRAN_VOTING_3[0], sizeof(ixCG_FREQ_TRAN_VOTING_3)/sizeof(ixCG_FREQ_TRAN_VOTING_3[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_4", REG_SMC, 0xc02001b8, &ixCG_FREQ_TRAN_VOTING_4[0], sizeof(ixCG_FREQ_TRAN_VOTING_4)/sizeof(ixCG_FREQ_TRAN_VOTING_4[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_5", REG_SMC, 0xc02001bc, &ixCG_FREQ_TRAN_VOTING_5[0], sizeof(ixCG_FREQ_TRAN_VOTING_5)/sizeof(ixCG_FREQ_TRAN_VOTING_5[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, &ixCG_DISPLAY_GAP_CNTL2[0], sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_MIN_DIV", REG_SMC, 0xc0200308, &ixSCLK_MIN_DIV[0], sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixCG_THERMAL_CTRL", REG_SMC, 0xc0300004, &ixCG_THERMAL_CTRL[0], sizeof(ixCG_THERMAL_CTRL)/sizeof(ixCG_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_STATUS", REG_SMC, 0xc0300008, &ixCG_THERMAL_STATUS[0], sizeof(ixCG_THERMAL_STATUS)/sizeof(ixCG_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT", REG_SMC, 0xc030000c, &ixCG_THERMAL_INT[0], sizeof(ixCG_THERMAL_INT)/sizeof(ixCG_THERMAL_INT[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_CTRL", REG_SMC, 0xc0300010, &ixCG_MULT_THERMAL_CTRL[0], sizeof(ixCG_MULT_THERMAL_CTRL)/sizeof(ixCG_MULT_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_STATUS", REG_SMC, 0xc0300014, &ixCG_MULT_THERMAL_STATUS[0], sizeof(ixCG_MULT_THERMAL_STATUS)/sizeof(ixCG_MULT_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL0", REG_SMC, 0xc0300064, &ixCG_FDO_CTRL0[0], sizeof(ixCG_FDO_CTRL0)/sizeof(ixCG_FDO_CTRL0[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL1", REG_SMC, 0xc0300068, &ixCG_FDO_CTRL1[0], sizeof(ixCG_FDO_CTRL1)/sizeof(ixCG_FDO_CTRL1[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL2", REG_SMC, 0xc030006c, &ixCG_FDO_CTRL2[0], sizeof(ixCG_FDO_CTRL2)/sizeof(ixCG_FDO_CTRL2[0]), 0, 0 },
+	{ "ixCG_TACH_CTRL", REG_SMC, 0xc0300070, &ixCG_TACH_CTRL[0], sizeof(ixCG_TACH_CTRL)/sizeof(ixCG_TACH_CTRL[0]), 0, 0 },
+	{ "ixCG_TACH_STATUS", REG_SMC, 0xc0300074, &ixCG_TACH_STATUS[0], sizeof(ixCG_TACH_STATUS)/sizeof(ixCG_TACH_STATUS[0]), 0, 0 },
+	{ "ixCC_THM_STRAPS0", REG_SMC, 0xc0300080, &ixCC_THM_STRAPS0[0], sizeof(ixCC_THM_STRAPS0)/sizeof(ixCC_THM_STRAPS0[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL0_DATA", REG_SMC, 0xc0300100, &ixTHM_TMON0_RDIL0_DATA[0], sizeof(ixTHM_TMON0_RDIL0_DATA)/sizeof(ixTHM_TMON0_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL1_DATA", REG_SMC, 0xc0300104, &ixTHM_TMON0_RDIL1_DATA[0], sizeof(ixTHM_TMON0_RDIL1_DATA)/sizeof(ixTHM_TMON0_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL2_DATA", REG_SMC, 0xc0300108, &ixTHM_TMON0_RDIL2_DATA[0], sizeof(ixTHM_TMON0_RDIL2_DATA)/sizeof(ixTHM_TMON0_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL3_DATA", REG_SMC, 0xc030010c, &ixTHM_TMON0_RDIL3_DATA[0], sizeof(ixTHM_TMON0_RDIL3_DATA)/sizeof(ixTHM_TMON0_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL4_DATA", REG_SMC, 0xc0300110, &ixTHM_TMON0_RDIL4_DATA[0], sizeof(ixTHM_TMON0_RDIL4_DATA)/sizeof(ixTHM_TMON0_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL5_DATA", REG_SMC, 0xc0300114, &ixTHM_TMON0_RDIL5_DATA[0], sizeof(ixTHM_TMON0_RDIL5_DATA)/sizeof(ixTHM_TMON0_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL6_DATA", REG_SMC, 0xc0300118, &ixTHM_TMON0_RDIL6_DATA[0], sizeof(ixTHM_TMON0_RDIL6_DATA)/sizeof(ixTHM_TMON0_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL7_DATA", REG_SMC, 0xc030011c, &ixTHM_TMON0_RDIL7_DATA[0], sizeof(ixTHM_TMON0_RDIL7_DATA)/sizeof(ixTHM_TMON0_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL8_DATA", REG_SMC, 0xc0300120, &ixTHM_TMON0_RDIL8_DATA[0], sizeof(ixTHM_TMON0_RDIL8_DATA)/sizeof(ixTHM_TMON0_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL9_DATA", REG_SMC, 0xc0300124, &ixTHM_TMON0_RDIL9_DATA[0], sizeof(ixTHM_TMON0_RDIL9_DATA)/sizeof(ixTHM_TMON0_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL10_DATA", REG_SMC, 0xc0300128, &ixTHM_TMON0_RDIL10_DATA[0], sizeof(ixTHM_TMON0_RDIL10_DATA)/sizeof(ixTHM_TMON0_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL11_DATA", REG_SMC, 0xc030012c, &ixTHM_TMON0_RDIL11_DATA[0], sizeof(ixTHM_TMON0_RDIL11_DATA)/sizeof(ixTHM_TMON0_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL12_DATA", REG_SMC, 0xc0300130, &ixTHM_TMON0_RDIL12_DATA[0], sizeof(ixTHM_TMON0_RDIL12_DATA)/sizeof(ixTHM_TMON0_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL13_DATA", REG_SMC, 0xc0300134, &ixTHM_TMON0_RDIL13_DATA[0], sizeof(ixTHM_TMON0_RDIL13_DATA)/sizeof(ixTHM_TMON0_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL14_DATA", REG_SMC, 0xc0300138, &ixTHM_TMON0_RDIL14_DATA[0], sizeof(ixTHM_TMON0_RDIL14_DATA)/sizeof(ixTHM_TMON0_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL15_DATA", REG_SMC, 0xc030013c, &ixTHM_TMON0_RDIL15_DATA[0], sizeof(ixTHM_TMON0_RDIL15_DATA)/sizeof(ixTHM_TMON0_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR0_DATA", REG_SMC, 0xc0300140, &ixTHM_TMON0_RDIR0_DATA[0], sizeof(ixTHM_TMON0_RDIR0_DATA)/sizeof(ixTHM_TMON0_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR1_DATA", REG_SMC, 0xc0300144, &ixTHM_TMON0_RDIR1_DATA[0], sizeof(ixTHM_TMON0_RDIR1_DATA)/sizeof(ixTHM_TMON0_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR2_DATA", REG_SMC, 0xc0300148, &ixTHM_TMON0_RDIR2_DATA[0], sizeof(ixTHM_TMON0_RDIR2_DATA)/sizeof(ixTHM_TMON0_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR3_DATA", REG_SMC, 0xc030014c, &ixTHM_TMON0_RDIR3_DATA[0], sizeof(ixTHM_TMON0_RDIR3_DATA)/sizeof(ixTHM_TMON0_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR4_DATA", REG_SMC, 0xc0300150, &ixTHM_TMON0_RDIR4_DATA[0], sizeof(ixTHM_TMON0_RDIR4_DATA)/sizeof(ixTHM_TMON0_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR5_DATA", REG_SMC, 0xc0300154, &ixTHM_TMON0_RDIR5_DATA[0], sizeof(ixTHM_TMON0_RDIR5_DATA)/sizeof(ixTHM_TMON0_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR6_DATA", REG_SMC, 0xc0300158, &ixTHM_TMON0_RDIR6_DATA[0], sizeof(ixTHM_TMON0_RDIR6_DATA)/sizeof(ixTHM_TMON0_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR7_DATA", REG_SMC, 0xc030015c, &ixTHM_TMON0_RDIR7_DATA[0], sizeof(ixTHM_TMON0_RDIR7_DATA)/sizeof(ixTHM_TMON0_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR8_DATA", REG_SMC, 0xc0300160, &ixTHM_TMON0_RDIR8_DATA[0], sizeof(ixTHM_TMON0_RDIR8_DATA)/sizeof(ixTHM_TMON0_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR9_DATA", REG_SMC, 0xc0300164, &ixTHM_TMON0_RDIR9_DATA[0], sizeof(ixTHM_TMON0_RDIR9_DATA)/sizeof(ixTHM_TMON0_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR10_DATA", REG_SMC, 0xc0300168, &ixTHM_TMON0_RDIR10_DATA[0], sizeof(ixTHM_TMON0_RDIR10_DATA)/sizeof(ixTHM_TMON0_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR11_DATA", REG_SMC, 0xc030016c, &ixTHM_TMON0_RDIR11_DATA[0], sizeof(ixTHM_TMON0_RDIR11_DATA)/sizeof(ixTHM_TMON0_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR12_DATA", REG_SMC, 0xc0300170, &ixTHM_TMON0_RDIR12_DATA[0], sizeof(ixTHM_TMON0_RDIR12_DATA)/sizeof(ixTHM_TMON0_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR13_DATA", REG_SMC, 0xc0300174, &ixTHM_TMON0_RDIR13_DATA[0], sizeof(ixTHM_TMON0_RDIR13_DATA)/sizeof(ixTHM_TMON0_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR14_DATA", REG_SMC, 0xc0300178, &ixTHM_TMON0_RDIR14_DATA[0], sizeof(ixTHM_TMON0_RDIR14_DATA)/sizeof(ixTHM_TMON0_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR15_DATA", REG_SMC, 0xc030017c, &ixTHM_TMON0_RDIR15_DATA[0], sizeof(ixTHM_TMON0_RDIR15_DATA)/sizeof(ixTHM_TMON0_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_INT_DATA", REG_SMC, 0xc0300300, &ixTHM_TMON0_INT_DATA[0], sizeof(ixTHM_TMON0_INT_DATA)/sizeof(ixTHM_TMON0_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_DEBUG", REG_SMC, 0xc0300310, &ixTHM_TMON0_DEBUG[0], sizeof(ixTHM_TMON0_DEBUG)/sizeof(ixTHM_TMON0_DEBUG[0]), 0, 0 },
+	{ "ixLCAC_SX0_CNTL", REG_SMC, 0xc0400d00, &ixLCAC_SX0_CNTL[0], sizeof(ixLCAC_SX0_CNTL)/sizeof(ixLCAC_SX0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_SX0_OVR_SEL", REG_SMC, 0xc0400d04, &ixLCAC_SX0_OVR_SEL[0], sizeof(ixLCAC_SX0_OVR_SEL)/sizeof(ixLCAC_SX0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_SX0_OVR_VAL", REG_SMC, 0xc0400d08, &ixLCAC_SX0_OVR_VAL[0], sizeof(ixLCAC_SX0_OVR_VAL)/sizeof(ixLCAC_SX0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC0_CNTL", REG_SMC, 0xc0400d30, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0xc0400d34, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0xc0400d38, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC1_CNTL", REG_SMC, 0xc0400d3c, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0xc0400d40, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0xc0400d44, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC2_CNTL", REG_SMC, 0xc0400d48, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0xc0400d4c, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0xc0400d50, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC3_CNTL", REG_SMC, 0xc0400d54, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0xc0400d58, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0xc0400d5c, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_CPL_CNTL", REG_SMC, 0xc0400d80, &ixLCAC_CPL_CNTL[0], sizeof(ixLCAC_CPL_CNTL)/sizeof(ixLCAC_CPL_CNTL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_SEL", REG_SMC, 0xc0400d84, &ixLCAC_CPL_OVR_SEL[0], sizeof(ixLCAC_CPL_OVR_SEL)/sizeof(ixLCAC_CPL_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_VAL", REG_SMC, 0xc0400d88, &ixLCAC_CPL_OVR_VAL[0], sizeof(ixLCAC_CPL_OVR_VAL)/sizeof(ixLCAC_CPL_OVR_VAL[0]), 0, 0 },
+	{ "ixCG_DCLK_CNTL", REG_SMC, 0xc050009c, &ixCG_DCLK_CNTL[0], sizeof(ixCG_DCLK_CNTL)/sizeof(ixCG_DCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_DCLK_STATUS", REG_SMC, 0xc05000a0, &ixCG_DCLK_STATUS[0], sizeof(ixCG_DCLK_STATUS)/sizeof(ixCG_DCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_VCLK_CNTL", REG_SMC, 0xc05000a4, &ixCG_VCLK_CNTL[0], sizeof(ixCG_VCLK_CNTL)/sizeof(ixCG_VCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_VCLK_STATUS", REG_SMC, 0xc05000a8, &ixCG_VCLK_STATUS[0], sizeof(ixCG_VCLK_STATUS)/sizeof(ixCG_VCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ECLK_CNTL", REG_SMC, 0xc05000ac, &ixCG_ECLK_CNTL[0], sizeof(ixCG_ECLK_CNTL)/sizeof(ixCG_ECLK_CNTL[0]), 0, 0 },
+	{ "ixCG_ECLK_STATUS", REG_SMC, 0xc05000b0, &ixCG_ECLK_STATUS[0], sizeof(ixCG_ECLK_STATUS)/sizeof(ixCG_ECLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ACLK_CNTL", REG_SMC, 0xc05000dc, &ixCG_ACLK_CNTL[0], sizeof(ixCG_ACLK_CNTL)/sizeof(ixCG_ACLK_CNTL[0]), 0, 0 },
+	{ "ixGCK_DFS_BYPASS_CNTL", REG_SMC, 0xc0500118, &ixGCK_DFS_BYPASS_CNTL[0], sizeof(ixGCK_DFS_BYPASS_CNTL)/sizeof(ixGCK_DFS_BYPASS_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL", REG_SMC, 0xc0500140, &ixCG_SPLL_FUNC_CNTL[0], sizeof(ixCG_SPLL_FUNC_CNTL)/sizeof(ixCG_SPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_2", REG_SMC, 0xc0500144, &ixCG_SPLL_FUNC_CNTL_2[0], sizeof(ixCG_SPLL_FUNC_CNTL_2)/sizeof(ixCG_SPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_3", REG_SMC, 0xc0500148, &ixCG_SPLL_FUNC_CNTL_3[0], sizeof(ixCG_SPLL_FUNC_CNTL_3)/sizeof(ixCG_SPLL_FUNC_CNTL_3[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_4", REG_SMC, 0xc050014c, &ixCG_SPLL_FUNC_CNTL_4[0], sizeof(ixCG_SPLL_FUNC_CNTL_4)/sizeof(ixCG_SPLL_FUNC_CNTL_4[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_5", REG_SMC, 0xc0500150, &ixCG_SPLL_FUNC_CNTL_5[0], sizeof(ixCG_SPLL_FUNC_CNTL_5)/sizeof(ixCG_SPLL_FUNC_CNTL_5[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_6", REG_SMC, 0xc0500154, &ixCG_SPLL_FUNC_CNTL_6[0], sizeof(ixCG_SPLL_FUNC_CNTL_6)/sizeof(ixCG_SPLL_FUNC_CNTL_6[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_7", REG_SMC, 0xc0500158, &ixCG_SPLL_FUNC_CNTL_7[0], sizeof(ixCG_SPLL_FUNC_CNTL_7)/sizeof(ixCG_SPLL_FUNC_CNTL_7[0]), 0, 0 },
+	{ "ixSPLL_CNTL_MODE", REG_SMC, 0xc0500160, &ixSPLL_CNTL_MODE[0], sizeof(ixSPLL_CNTL_MODE)/sizeof(ixSPLL_CNTL_MODE[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM", REG_SMC, 0xc0500164, &ixCG_SPLL_SPREAD_SPECTRUM[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM_2", REG_SMC, 0xc0500168, &ixCG_SPLL_SPREAD_SPECTRUM_2[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2[0]), 0, 0 },
+	{ "ixMPLL_BYPASSCLK_SEL", REG_SMC, 0xc050019c, &ixMPLL_BYPASSCLK_SEL[0], sizeof(ixMPLL_BYPASSCLK_SEL)/sizeof(ixMPLL_BYPASSCLK_SEL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL", REG_SMC, 0xc05001a0, &ixCG_CLKPIN_CNTL[0], sizeof(ixCG_CLKPIN_CNTL)/sizeof(ixCG_CLKPIN_CNTL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_2", REG_SMC, 0xc05001a4, &ixCG_CLKPIN_CNTL_2[0], sizeof(ixCG_CLKPIN_CNTL_2)/sizeof(ixCG_CLKPIN_CNTL_2[0]), 0, 0 },
+	{ "ixTHM_CLK_CNTL", REG_SMC, 0xc05001a8, &ixTHM_CLK_CNTL[0], sizeof(ixTHM_CLK_CNTL)/sizeof(ixTHM_CLK_CNTL[0]), 0, 0 },
+	{ "ixMISC_CLK_CTRL", REG_SMC, 0xc05001ac, &ixMISC_CLK_CTRL[0], sizeof(ixMISC_CLK_CTRL)/sizeof(ixMISC_CLK_CTRL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL", REG_SMC, 0xc05001c0, &ixGCK_PLL_TEST_CNTL[0], sizeof(ixGCK_PLL_TEST_CNTL)/sizeof(ixGCK_PLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL_2", REG_SMC, 0xc05001c4, &ixGCK_PLL_TEST_CNTL_2[0], sizeof(ixGCK_PLL_TEST_CNTL_2)/sizeof(ixGCK_PLL_TEST_CNTL_2[0]), 0, 0 },
+	{ "ixGCK_ADFS_CLK_BYPASS_CNTL1", REG_SMC, 0xc05001c8, &ixGCK_ADFS_CLK_BYPASS_CNTL1[0], sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1)/sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_DC", REG_SMC, 0xc0500204, &ixCG_CLKPIN_CNTL_DC[0], sizeof(ixCG_CLKPIN_CNTL_DC)/sizeof(ixCG_CLKPIN_CNTL_DC[0]), 0, 0 },
+	{ "ixROM_CNTL", REG_SMC, 0xc0600000, &ixROM_CNTL[0], sizeof(ixROM_CNTL)/sizeof(ixROM_CNTL[0]), 0, 0 },
+	{ "ixPAGE_MIRROR_CNTL", REG_SMC, 0xc0600004, &ixPAGE_MIRROR_CNTL[0], sizeof(ixPAGE_MIRROR_CNTL)/sizeof(ixPAGE_MIRROR_CNTL[0]), 0, 0 },
+	{ "ixROM_STATUS", REG_SMC, 0xc0600008, &ixROM_STATUS[0], sizeof(ixROM_STATUS)/sizeof(ixROM_STATUS[0]), 0, 0 },
+	{ "ixCGTT_ROM_CLK_CTRL0", REG_SMC, 0xc060000c, &ixCGTT_ROM_CLK_CTRL0[0], sizeof(ixCGTT_ROM_CLK_CTRL0)/sizeof(ixCGTT_ROM_CLK_CTRL0[0]), 0, 0 },
+	{ "ixROM_INDEX", REG_SMC, 0xc0600010, &ixROM_INDEX[0], sizeof(ixROM_INDEX)/sizeof(ixROM_INDEX[0]), 0, 0 },
+	{ "ixROM_DATA", REG_SMC, 0xc0600014, &ixROM_DATA[0], sizeof(ixROM_DATA)/sizeof(ixROM_DATA[0]), 0, 0 },
+	{ "ixROM_START", REG_SMC, 0xc0600018, &ixROM_START[0], sizeof(ixROM_START)/sizeof(ixROM_START[0]), 0, 0 },
+	{ "ixROM_SW_CNTL", REG_SMC, 0xc060001c, &ixROM_SW_CNTL[0], sizeof(ixROM_SW_CNTL)/sizeof(ixROM_SW_CNTL[0]), 0, 0 },
+	{ "ixROM_SW_STATUS", REG_SMC, 0xc0600020, &ixROM_SW_STATUS[0], sizeof(ixROM_SW_STATUS)/sizeof(ixROM_SW_STATUS[0]), 0, 0 },
+	{ "ixROM_SW_COMMAND", REG_SMC, 0xc0600024, &ixROM_SW_COMMAND[0], sizeof(ixROM_SW_COMMAND)/sizeof(ixROM_SW_COMMAND[0]), 0, 0 },
+	{ "ixROM_SW_DATA_1", REG_SMC, 0xc0600028, &ixROM_SW_DATA_1[0], sizeof(ixROM_SW_DATA_1)/sizeof(ixROM_SW_DATA_1[0]), 0, 0 },
+	{ "ixROM_SW_DATA_2", REG_SMC, 0xc060002c, &ixROM_SW_DATA_2[0], sizeof(ixROM_SW_DATA_2)/sizeof(ixROM_SW_DATA_2[0]), 0, 0 },
+	{ "ixROM_SW_DATA_3", REG_SMC, 0xc0600030, &ixROM_SW_DATA_3[0], sizeof(ixROM_SW_DATA_3)/sizeof(ixROM_SW_DATA_3[0]), 0, 0 },
+	{ "ixROM_SW_DATA_4", REG_SMC, 0xc0600034, &ixROM_SW_DATA_4[0], sizeof(ixROM_SW_DATA_4)/sizeof(ixROM_SW_DATA_4[0]), 0, 0 },
+	{ "ixROM_SW_DATA_5", REG_SMC, 0xc0600038, &ixROM_SW_DATA_5[0], sizeof(ixROM_SW_DATA_5)/sizeof(ixROM_SW_DATA_5[0]), 0, 0 },
+	{ "ixROM_SW_DATA_6", REG_SMC, 0xc060003c, &ixROM_SW_DATA_6[0], sizeof(ixROM_SW_DATA_6)/sizeof(ixROM_SW_DATA_6[0]), 0, 0 },
+	{ "ixROM_SW_DATA_7", REG_SMC, 0xc0600040, &ixROM_SW_DATA_7[0], sizeof(ixROM_SW_DATA_7)/sizeof(ixROM_SW_DATA_7[0]), 0, 0 },
+	{ "ixROM_SW_DATA_8", REG_SMC, 0xc0600044, &ixROM_SW_DATA_8[0], sizeof(ixROM_SW_DATA_8)/sizeof(ixROM_SW_DATA_8[0]), 0, 0 },
+	{ "ixROM_SW_DATA_9", REG_SMC, 0xc0600048, &ixROM_SW_DATA_9[0], sizeof(ixROM_SW_DATA_9)/sizeof(ixROM_SW_DATA_9[0]), 0, 0 },
+	{ "ixROM_SW_DATA_10", REG_SMC, 0xc060004c, &ixROM_SW_DATA_10[0], sizeof(ixROM_SW_DATA_10)/sizeof(ixROM_SW_DATA_10[0]), 0, 0 },
+	{ "ixROM_SW_DATA_11", REG_SMC, 0xc0600050, &ixROM_SW_DATA_11[0], sizeof(ixROM_SW_DATA_11)/sizeof(ixROM_SW_DATA_11[0]), 0, 0 },
+	{ "ixROM_SW_DATA_12", REG_SMC, 0xc0600054, &ixROM_SW_DATA_12[0], sizeof(ixROM_SW_DATA_12)/sizeof(ixROM_SW_DATA_12[0]), 0, 0 },
+	{ "ixROM_SW_DATA_13", REG_SMC, 0xc0600058, &ixROM_SW_DATA_13[0], sizeof(ixROM_SW_DATA_13)/sizeof(ixROM_SW_DATA_13[0]), 0, 0 },
+	{ "ixROM_SW_DATA_14", REG_SMC, 0xc060005c, &ixROM_SW_DATA_14[0], sizeof(ixROM_SW_DATA_14)/sizeof(ixROM_SW_DATA_14[0]), 0, 0 },
+	{ "ixROM_SW_DATA_15", REG_SMC, 0xc0600060, &ixROM_SW_DATA_15[0], sizeof(ixROM_SW_DATA_15)/sizeof(ixROM_SW_DATA_15[0]), 0, 0 },
+	{ "ixROM_SW_DATA_16", REG_SMC, 0xc0600064, &ixROM_SW_DATA_16[0], sizeof(ixROM_SW_DATA_16)/sizeof(ixROM_SW_DATA_16[0]), 0, 0 },
+	{ "ixROM_SW_DATA_17", REG_SMC, 0xc0600068, &ixROM_SW_DATA_17[0], sizeof(ixROM_SW_DATA_17)/sizeof(ixROM_SW_DATA_17[0]), 0, 0 },
+	{ "ixROM_SW_DATA_18", REG_SMC, 0xc060006c, &ixROM_SW_DATA_18[0], sizeof(ixROM_SW_DATA_18)/sizeof(ixROM_SW_DATA_18[0]), 0, 0 },
+	{ "ixROM_SW_DATA_19", REG_SMC, 0xc0600070, &ixROM_SW_DATA_19[0], sizeof(ixROM_SW_DATA_19)/sizeof(ixROM_SW_DATA_19[0]), 0, 0 },
+	{ "ixROM_SW_DATA_20", REG_SMC, 0xc0600074, &ixROM_SW_DATA_20[0], sizeof(ixROM_SW_DATA_20)/sizeof(ixROM_SW_DATA_20[0]), 0, 0 },
+	{ "ixROM_SW_DATA_21", REG_SMC, 0xc0600078, &ixROM_SW_DATA_21[0], sizeof(ixROM_SW_DATA_21)/sizeof(ixROM_SW_DATA_21[0]), 0, 0 },
+	{ "ixROM_SW_DATA_22", REG_SMC, 0xc060007c, &ixROM_SW_DATA_22[0], sizeof(ixROM_SW_DATA_22)/sizeof(ixROM_SW_DATA_22[0]), 0, 0 },
+	{ "ixROM_SW_DATA_23", REG_SMC, 0xc0600080, &ixROM_SW_DATA_23[0], sizeof(ixROM_SW_DATA_23)/sizeof(ixROM_SW_DATA_23[0]), 0, 0 },
+	{ "ixROM_SW_DATA_24", REG_SMC, 0xc0600084, &ixROM_SW_DATA_24[0], sizeof(ixROM_SW_DATA_24)/sizeof(ixROM_SW_DATA_24[0]), 0, 0 },
+	{ "ixROM_SW_DATA_25", REG_SMC, 0xc0600088, &ixROM_SW_DATA_25[0], sizeof(ixROM_SW_DATA_25)/sizeof(ixROM_SW_DATA_25[0]), 0, 0 },
+	{ "ixROM_SW_DATA_26", REG_SMC, 0xc060008c, &ixROM_SW_DATA_26[0], sizeof(ixROM_SW_DATA_26)/sizeof(ixROM_SW_DATA_26[0]), 0, 0 },
+	{ "ixROM_SW_DATA_27", REG_SMC, 0xc0600090, &ixROM_SW_DATA_27[0], sizeof(ixROM_SW_DATA_27)/sizeof(ixROM_SW_DATA_27[0]), 0, 0 },
+	{ "ixROM_SW_DATA_28", REG_SMC, 0xc0600094, &ixROM_SW_DATA_28[0], sizeof(ixROM_SW_DATA_28)/sizeof(ixROM_SW_DATA_28[0]), 0, 0 },
+	{ "ixROM_SW_DATA_29", REG_SMC, 0xc0600098, &ixROM_SW_DATA_29[0], sizeof(ixROM_SW_DATA_29)/sizeof(ixROM_SW_DATA_29[0]), 0, 0 },
+	{ "ixROM_SW_DATA_30", REG_SMC, 0xc060009c, &ixROM_SW_DATA_30[0], sizeof(ixROM_SW_DATA_30)/sizeof(ixROM_SW_DATA_30[0]), 0, 0 },
+	{ "ixROM_SW_DATA_31", REG_SMC, 0xc06000a0, &ixROM_SW_DATA_31[0], sizeof(ixROM_SW_DATA_31)/sizeof(ixROM_SW_DATA_31[0]), 0, 0 },
+	{ "ixROM_SW_DATA_32", REG_SMC, 0xc06000a4, &ixROM_SW_DATA_32[0], sizeof(ixROM_SW_DATA_32)/sizeof(ixROM_SW_DATA_32[0]), 0, 0 },
+	{ "ixROM_SW_DATA_33", REG_SMC, 0xc06000a8, &ixROM_SW_DATA_33[0], sizeof(ixROM_SW_DATA_33)/sizeof(ixROM_SW_DATA_33[0]), 0, 0 },
+	{ "ixROM_SW_DATA_34", REG_SMC, 0xc06000ac, &ixROM_SW_DATA_34[0], sizeof(ixROM_SW_DATA_34)/sizeof(ixROM_SW_DATA_34[0]), 0, 0 },
+	{ "ixROM_SW_DATA_35", REG_SMC, 0xc06000b0, &ixROM_SW_DATA_35[0], sizeof(ixROM_SW_DATA_35)/sizeof(ixROM_SW_DATA_35[0]), 0, 0 },
+	{ "ixROM_SW_DATA_36", REG_SMC, 0xc06000b4, &ixROM_SW_DATA_36[0], sizeof(ixROM_SW_DATA_36)/sizeof(ixROM_SW_DATA_36[0]), 0, 0 },
+	{ "ixROM_SW_DATA_37", REG_SMC, 0xc06000b8, &ixROM_SW_DATA_37[0], sizeof(ixROM_SW_DATA_37)/sizeof(ixROM_SW_DATA_37[0]), 0, 0 },
+	{ "ixROM_SW_DATA_38", REG_SMC, 0xc06000bc, &ixROM_SW_DATA_38[0], sizeof(ixROM_SW_DATA_38)/sizeof(ixROM_SW_DATA_38[0]), 0, 0 },
+	{ "ixROM_SW_DATA_39", REG_SMC, 0xc06000c0, &ixROM_SW_DATA_39[0], sizeof(ixROM_SW_DATA_39)/sizeof(ixROM_SW_DATA_39[0]), 0, 0 },
+	{ "ixROM_SW_DATA_40", REG_SMC, 0xc06000c4, &ixROM_SW_DATA_40[0], sizeof(ixROM_SW_DATA_40)/sizeof(ixROM_SW_DATA_40[0]), 0, 0 },
+	{ "ixROM_SW_DATA_41", REG_SMC, 0xc06000c8, &ixROM_SW_DATA_41[0], sizeof(ixROM_SW_DATA_41)/sizeof(ixROM_SW_DATA_41[0]), 0, 0 },
+	{ "ixROM_SW_DATA_42", REG_SMC, 0xc06000cc, &ixROM_SW_DATA_42[0], sizeof(ixROM_SW_DATA_42)/sizeof(ixROM_SW_DATA_42[0]), 0, 0 },
+	{ "ixROM_SW_DATA_43", REG_SMC, 0xc06000d0, &ixROM_SW_DATA_43[0], sizeof(ixROM_SW_DATA_43)/sizeof(ixROM_SW_DATA_43[0]), 0, 0 },
+	{ "ixROM_SW_DATA_44", REG_SMC, 0xc06000d4, &ixROM_SW_DATA_44[0], sizeof(ixROM_SW_DATA_44)/sizeof(ixROM_SW_DATA_44[0]), 0, 0 },
+	{ "ixROM_SW_DATA_45", REG_SMC, 0xc06000d8, &ixROM_SW_DATA_45[0], sizeof(ixROM_SW_DATA_45)/sizeof(ixROM_SW_DATA_45[0]), 0, 0 },
+	{ "ixROM_SW_DATA_46", REG_SMC, 0xc06000dc, &ixROM_SW_DATA_46[0], sizeof(ixROM_SW_DATA_46)/sizeof(ixROM_SW_DATA_46[0]), 0, 0 },
+	{ "ixROM_SW_DATA_47", REG_SMC, 0xc06000e0, &ixROM_SW_DATA_47[0], sizeof(ixROM_SW_DATA_47)/sizeof(ixROM_SW_DATA_47[0]), 0, 0 },
+	{ "ixROM_SW_DATA_48", REG_SMC, 0xc06000e4, &ixROM_SW_DATA_48[0], sizeof(ixROM_SW_DATA_48)/sizeof(ixROM_SW_DATA_48[0]), 0, 0 },
+	{ "ixROM_SW_DATA_49", REG_SMC, 0xc06000e8, &ixROM_SW_DATA_49[0], sizeof(ixROM_SW_DATA_49)/sizeof(ixROM_SW_DATA_49[0]), 0, 0 },
+	{ "ixROM_SW_DATA_50", REG_SMC, 0xc06000ec, &ixROM_SW_DATA_50[0], sizeof(ixROM_SW_DATA_50)/sizeof(ixROM_SW_DATA_50[0]), 0, 0 },
+	{ "ixROM_SW_DATA_51", REG_SMC, 0xc06000f0, &ixROM_SW_DATA_51[0], sizeof(ixROM_SW_DATA_51)/sizeof(ixROM_SW_DATA_51[0]), 0, 0 },
+	{ "ixROM_SW_DATA_52", REG_SMC, 0xc06000f4, &ixROM_SW_DATA_52[0], sizeof(ixROM_SW_DATA_52)/sizeof(ixROM_SW_DATA_52[0]), 0, 0 },
+	{ "ixROM_SW_DATA_53", REG_SMC, 0xc06000f8, &ixROM_SW_DATA_53[0], sizeof(ixROM_SW_DATA_53)/sizeof(ixROM_SW_DATA_53[0]), 0, 0 },
+	{ "ixROM_SW_DATA_54", REG_SMC, 0xc06000fc, &ixROM_SW_DATA_54[0], sizeof(ixROM_SW_DATA_54)/sizeof(ixROM_SW_DATA_54[0]), 0, 0 },
+	{ "ixROM_SW_DATA_55", REG_SMC, 0xc0600110, &ixROM_SW_DATA_55[0], sizeof(ixROM_SW_DATA_55)/sizeof(ixROM_SW_DATA_55[0]), 0, 0 },
+	{ "ixROM_SW_DATA_56", REG_SMC, 0xc0600114, &ixROM_SW_DATA_56[0], sizeof(ixROM_SW_DATA_56)/sizeof(ixROM_SW_DATA_56[0]), 0, 0 },
+	{ "ixROM_SW_DATA_57", REG_SMC, 0xc0600118, &ixROM_SW_DATA_57[0], sizeof(ixROM_SW_DATA_57)/sizeof(ixROM_SW_DATA_57[0]), 0, 0 },
+	{ "ixROM_SW_DATA_58", REG_SMC, 0xc060011c, &ixROM_SW_DATA_58[0], sizeof(ixROM_SW_DATA_58)/sizeof(ixROM_SW_DATA_58[0]), 0, 0 },
+	{ "ixROM_SW_DATA_59", REG_SMC, 0xc0600120, &ixROM_SW_DATA_59[0], sizeof(ixROM_SW_DATA_59)/sizeof(ixROM_SW_DATA_59[0]), 0, 0 },
+	{ "ixROM_SW_DATA_60", REG_SMC, 0xc0600124, &ixROM_SW_DATA_60[0], sizeof(ixROM_SW_DATA_60)/sizeof(ixROM_SW_DATA_60[0]), 0, 0 },
+	{ "ixROM_SW_DATA_61", REG_SMC, 0xc0600128, &ixROM_SW_DATA_61[0], sizeof(ixROM_SW_DATA_61)/sizeof(ixROM_SW_DATA_61[0]), 0, 0 },
+	{ "ixROM_SW_DATA_62", REG_SMC, 0xc060012c, &ixROM_SW_DATA_62[0], sizeof(ixROM_SW_DATA_62)/sizeof(ixROM_SW_DATA_62[0]), 0, 0 },
+	{ "ixROM_SW_DATA_63", REG_SMC, 0xc0600130, &ixROM_SW_DATA_63[0], sizeof(ixROM_SW_DATA_63)/sizeof(ixROM_SW_DATA_63[0]), 0, 0 },
+	{ "ixROM_SW_DATA_64", REG_SMC, 0xc0600134, &ixROM_SW_DATA_64[0], sizeof(ixROM_SW_DATA_64)/sizeof(ixROM_SW_DATA_64[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, &ixCG_THERMAL_INT_ENA[0], sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, &ixCG_THERMAL_INT_CTRL[0], sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, &ixCG_THERMAL_INT_STATUS[0], sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
+	{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, &ixSMU_MAIN_PLL_OP_FREQ[0], sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
+	{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
+	{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
+	{ "ixSMU_INPUT_DATA", REG_SMC, 0xe00030b8, &ixSMU_INPUT_DATA[0], sizeof(ixSMU_INPUT_DATA)/sizeof(ixSMU_INPUT_DATA[0]), 0, 0 },
diff --git a/src/lib/ip/smu710.c b/src/lib/ip/smu710.c
new file mode 100644
index 0000000..6d68464
--- /dev/null
+++ b/src/lib/ip/smu710.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "smu710_bits.i"
+
+static const struct umr_reg smu710_registers[] = {
+#include "smu710_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_smu710(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "smu710";
+	ip->no_regs = sizeof(smu710_registers)/sizeof(smu710_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(smu710_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, smu710_registers, sizeof(smu710_registers));
+	return ip;
+}
diff --git a/src/lib/ip/smu710_bits.i b/src/lib/ip/smu710_bits.i
new file mode 100644
index 0000000..a4efe3f
--- /dev/null
+++ b/src/lib/ip/smu710_bits.i
@@ -0,0 +1,5364 @@
+static struct umr_bitfield mmGPIOPAD_SW_INT_STAT[] = {
+	 { "SW_INT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_STRENGTH[] = {
+	 { "GPIO_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GPIO_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_MASK[] = {
+	 { "GPIO_MASK", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_A[] = {
+	 { "GPIO_A", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EN[] = {
+	 { "GPIO_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_Y[] = {
+	 { "GPIO_Y", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PINSTRAPS[] = {
+	 { "GPIO_PINSTRAP_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_28", 28, 28, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_29", 29, 29, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_30", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_EN[] = {
+	 { "GPIO_INT_STAT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT[] = {
+	 { "GPIO_INT_STAT", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_AK[] = {
+	 { "GPIO_INT_STAT_AK_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_28", 28, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_AK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_EN[] = {
+	 { "GPIO_INT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_TYPE[] = {
+	 { "GPIO_INT_TYPE", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_POLARITY[] = {
+	 { "GPIO_INT_POLARITY", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_POLARITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EXTERN_TRIG_CNTL[] = {
+	 { "EXTERN_TRIG_SEL", 0, 4, &umr_bitfield_default },
+	 { "EXTERN_TRIG_CLR", 5, 5, &umr_bitfield_default },
+	 { "EXTERN_TRIG_READ", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_RCVR_SEL[] = {
+	 { "GPIO_RCVR_SEL", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PU_EN[] = {
+	 { "GPIO_PU_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PD_EN[] = {
+	 { "GPIO_PD_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCG_FPS_CNT[] = {
+	 { "FPS_CNT", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_1[] = {
+	 { "GraphicsPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_2[] = {
+	 { "GraphicsPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_3[] = {
+	 { "GraphicsPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_4[] = {
+	 { "GraphicsPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_5[] = {
+	 { "GraphicsPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_6[] = {
+	 { "GraphicsPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_7[] = {
+	 { "GraphicsPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_8[] = {
+	 { "GraphicsPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_9[] = {
+	 { "GraphicsPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_10[] = {
+	 { "MemoryPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_11[] = {
+	 { "MemoryPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_12[] = {
+	 { "MemoryPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_13[] = {
+	 { "MemoryPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_14[] = {
+	 { "MemoryPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_15[] = {
+	 { "MemoryPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_16[] = {
+	 { "MemoryPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_17[] = {
+	 { "MemoryPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_18[] = {
+	 { "MemoryPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_19[] = {
+	 { "LinkPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_20[] = {
+	 { "LinkPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_21[] = {
+	 { "LinkPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_22[] = {
+	 { "LinkPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_23[] = {
+	 { "LinkPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_24[] = {
+	 { "LinkPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_25[] = {
+	 { "LinkPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_26[] = {
+	 { "LinkPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_27[] = {
+	 { "LinkPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_28[] = {
+	 { "SystemFlags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_29[] = {
+	 { "SmioMaskVddcVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_30[] = {
+	 { "SmioMaskVddcPhase", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_31[] = {
+	 { "SmioMaskVddciVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_32[] = {
+	 { "SmioMaskMvddVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_33[] = {
+	 { "VddcLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_34[] = {
+	 { "VddciLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_35[] = {
+	 { "MvddLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_36[] = {
+	 { "VddcLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_37[] = {
+	 { "VddcLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_38[] = {
+	 { "VddcLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_39[] = {
+	 { "VddcLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_40[] = {
+	 { "VddcLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_41[] = {
+	 { "VddcLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_42[] = {
+	 { "VddcLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_43[] = {
+	 { "VddcLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_44[] = {
+	 { "VddcLevel_4_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_4_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_45[] = {
+	 { "VddcLevel_4_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_4_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_4_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_46[] = {
+	 { "VddcLevel_5_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_5_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_47[] = {
+	 { "VddcLevel_5_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_5_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_5_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_48[] = {
+	 { "VddcLevel_6_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_6_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_49[] = {
+	 { "VddcLevel_6_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_6_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_6_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_50[] = {
+	 { "VddcLevel_7_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_7_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_51[] = {
+	 { "VddcLevel_7_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_7_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_7_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_52[] = {
+	 { "VddciLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_53[] = {
+	 { "VddciLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_54[] = {
+	 { "VddciLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_55[] = {
+	 { "VddciLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_56[] = {
+	 { "VddciLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_57[] = {
+	 { "VddciLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_58[] = {
+	 { "VddciLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_59[] = {
+	 { "VddciLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_60[] = {
+	 { "MvddLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_61[] = {
+	 { "MvddLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_62[] = {
+	 { "MvddLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_63[] = {
+	 { "MvddLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_64[] = {
+	 { "MvddLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_65[] = {
+	 { "MvddLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_66[] = {
+	 { "MvddLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_67[] = {
+	 { "MvddLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_68[] = {
+	 { "UvdLevelCount", 0, 7, &umr_bitfield_default },
+	 { "LinkLevelCount", 8, 15, &umr_bitfield_default },
+	 { "MemoryDpmLevelCount", 16, 23, &umr_bitfield_default },
+	 { "GraphicsDpmLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_69[] = {
+	 { "MasterDeepSleepControl", 0, 7, &umr_bitfield_default },
+	 { "SamuLevelCount", 8, 15, &umr_bitfield_default },
+	 { "AcpLevelCount", 16, 23, &umr_bitfield_default },
+	 { "VceLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_70[] = {
+	 { "DefaultTdp", 0, 15, &umr_bitfield_default },
+	 { "TargetTdp", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_71[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_72[] = {
+	 { "Reserved_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_73[] = {
+	 { "Reserved_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_74[] = {
+	 { "Reserved_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_75[] = {
+	 { "GraphicsLevel_0_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_76[] = {
+	 { "GraphicsLevel_0_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_77[] = {
+	 { "GraphicsLevel_0_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_78[] = {
+	 { "GraphicsLevel_0_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_79[] = {
+	 { "GraphicsLevel_0_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_padding1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_80[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_81[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_82[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_83[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_84[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_85[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_86[] = {
+	 { "GraphicsLevel_0_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_87[] = {
+	 { "GraphicsLevel_0_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_88[] = {
+	 { "GraphicsLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_89[] = {
+	 { "GraphicsLevel_1_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_90[] = {
+	 { "GraphicsLevel_1_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_91[] = {
+	 { "GraphicsLevel_1_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_92[] = {
+	 { "GraphicsLevel_1_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_93[] = {
+	 { "GraphicsLevel_1_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_padding1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_94[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_95[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_96[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_97[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_98[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_99[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_100[] = {
+	 { "GraphicsLevel_1_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_101[] = {
+	 { "GraphicsLevel_1_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_102[] = {
+	 { "GraphicsLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_103[] = {
+	 { "GraphicsLevel_2_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_104[] = {
+	 { "GraphicsLevel_2_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_105[] = {
+	 { "GraphicsLevel_2_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_106[] = {
+	 { "GraphicsLevel_2_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_107[] = {
+	 { "GraphicsLevel_2_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_padding1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_108[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_109[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_110[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_111[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_112[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_113[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_114[] = {
+	 { "GraphicsLevel_2_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_115[] = {
+	 { "GraphicsLevel_2_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_116[] = {
+	 { "GraphicsLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_117[] = {
+	 { "GraphicsLevel_3_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_118[] = {
+	 { "GraphicsLevel_3_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_119[] = {
+	 { "GraphicsLevel_3_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_120[] = {
+	 { "GraphicsLevel_3_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_121[] = {
+	 { "GraphicsLevel_3_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_padding1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_122[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_123[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_124[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_125[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_126[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_127[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_128[] = {
+	 { "GraphicsLevel_3_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_129[] = {
+	 { "GraphicsLevel_3_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_130[] = {
+	 { "GraphicsLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_131[] = {
+	 { "GraphicsLevel_4_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_132[] = {
+	 { "GraphicsLevel_4_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_133[] = {
+	 { "GraphicsLevel_4_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_134[] = {
+	 { "GraphicsLevel_4_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_135[] = {
+	 { "GraphicsLevel_4_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_padding1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_136[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_137[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_138[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_139[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_140[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_141[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_142[] = {
+	 { "GraphicsLevel_4_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_143[] = {
+	 { "GraphicsLevel_4_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_144[] = {
+	 { "GraphicsLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_145[] = {
+	 { "GraphicsLevel_5_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_146[] = {
+	 { "GraphicsLevel_5_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_147[] = {
+	 { "GraphicsLevel_5_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_148[] = {
+	 { "GraphicsLevel_5_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_149[] = {
+	 { "GraphicsLevel_5_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_padding1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_150[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_151[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_152[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_153[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_154[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_155[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_156[] = {
+	 { "GraphicsLevel_5_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_157[] = {
+	 { "GraphicsLevel_5_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_158[] = {
+	 { "GraphicsLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_159[] = {
+	 { "GraphicsLevel_6_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_160[] = {
+	 { "GraphicsLevel_6_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_161[] = {
+	 { "GraphicsLevel_6_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_162[] = {
+	 { "GraphicsLevel_6_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_163[] = {
+	 { "GraphicsLevel_6_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_padding1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_164[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_165[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_166[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_167[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_168[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_169[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_170[] = {
+	 { "GraphicsLevel_6_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_171[] = {
+	 { "GraphicsLevel_6_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_172[] = {
+	 { "GraphicsLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_173[] = {
+	 { "GraphicsLevel_7_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_174[] = {
+	 { "GraphicsLevel_7_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_175[] = {
+	 { "GraphicsLevel_7_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_176[] = {
+	 { "GraphicsLevel_7_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_177[] = {
+	 { "GraphicsLevel_7_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_padding1", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_178[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_179[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_180[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_181[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_182[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_183[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_184[] = {
+	 { "GraphicsLevel_7_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_185[] = {
+	 { "GraphicsLevel_7_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_186[] = {
+	 { "GraphicsLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DeepSleepDivId", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_187[] = {
+	 { "MemoryACPILevel_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_188[] = {
+	 { "MemoryACPILevel_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_189[] = {
+	 { "MemoryACPILevel_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_190[] = {
+	 { "MemoryACPILevel_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_191[] = {
+	 { "MemoryACPILevel_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_192[] = {
+	 { "MemoryACPILevel_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_193[] = {
+	 { "MemoryACPILevel_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_194[] = {
+	 { "MemoryACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_195[] = {
+	 { "MemoryACPILevel_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_196[] = {
+	 { "MemoryACPILevel_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_197[] = {
+	 { "MemoryACPILevel_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_198[] = {
+	 { "MemoryACPILevel_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_199[] = {
+	 { "MemoryACPILevel_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_200[] = {
+	 { "MemoryACPILevel_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_201[] = {
+	 { "MemoryACPILevel_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_202[] = {
+	 { "MemoryACPILevel_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_203[] = {
+	 { "MemoryACPILevel_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_204[] = {
+	 { "MemoryACPILevel_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_205[] = {
+	 { "MemoryLevel_0_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_206[] = {
+	 { "MemoryLevel_0_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_207[] = {
+	 { "MemoryLevel_0_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_208[] = {
+	 { "MemoryLevel_0_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_209[] = {
+	 { "MemoryLevel_0_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_210[] = {
+	 { "MemoryLevel_0_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_211[] = {
+	 { "MemoryLevel_0_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_212[] = {
+	 { "MemoryLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_213[] = {
+	 { "MemoryLevel_0_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_214[] = {
+	 { "MemoryLevel_0_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_215[] = {
+	 { "MemoryLevel_0_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_216[] = {
+	 { "MemoryLevel_0_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_217[] = {
+	 { "MemoryLevel_0_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_218[] = {
+	 { "MemoryLevel_0_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_219[] = {
+	 { "MemoryLevel_0_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_220[] = {
+	 { "MemoryLevel_0_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_221[] = {
+	 { "MemoryLevel_0_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_222[] = {
+	 { "MemoryLevel_0_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_223[] = {
+	 { "MemoryLevel_1_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_224[] = {
+	 { "MemoryLevel_1_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_225[] = {
+	 { "MemoryLevel_1_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_226[] = {
+	 { "MemoryLevel_1_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_227[] = {
+	 { "MemoryLevel_1_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_228[] = {
+	 { "MemoryLevel_1_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_229[] = {
+	 { "MemoryLevel_1_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_230[] = {
+	 { "MemoryLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_231[] = {
+	 { "MemoryLevel_1_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_232[] = {
+	 { "MemoryLevel_1_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_233[] = {
+	 { "MemoryLevel_1_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_234[] = {
+	 { "MemoryLevel_1_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_235[] = {
+	 { "MemoryLevel_1_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_236[] = {
+	 { "MemoryLevel_1_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_237[] = {
+	 { "MemoryLevel_1_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_238[] = {
+	 { "MemoryLevel_1_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_239[] = {
+	 { "MemoryLevel_1_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_240[] = {
+	 { "MemoryLevel_1_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_241[] = {
+	 { "MemoryLevel_2_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_242[] = {
+	 { "MemoryLevel_2_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_243[] = {
+	 { "MemoryLevel_2_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_244[] = {
+	 { "MemoryLevel_2_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_245[] = {
+	 { "MemoryLevel_2_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_246[] = {
+	 { "MemoryLevel_2_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_247[] = {
+	 { "MemoryLevel_2_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_248[] = {
+	 { "MemoryLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_249[] = {
+	 { "MemoryLevel_2_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_250[] = {
+	 { "MemoryLevel_2_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_251[] = {
+	 { "MemoryLevel_2_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_252[] = {
+	 { "MemoryLevel_2_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_253[] = {
+	 { "MemoryLevel_2_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_254[] = {
+	 { "MemoryLevel_2_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_255[] = {
+	 { "MemoryLevel_2_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_256[] = {
+	 { "MemoryLevel_2_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_257[] = {
+	 { "MemoryLevel_2_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_258[] = {
+	 { "MemoryLevel_2_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_259[] = {
+	 { "MemoryLevel_3_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_260[] = {
+	 { "MemoryLevel_3_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_261[] = {
+	 { "MemoryLevel_3_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_262[] = {
+	 { "MemoryLevel_3_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_263[] = {
+	 { "MemoryLevel_3_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_264[] = {
+	 { "MemoryLevel_3_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_265[] = {
+	 { "MemoryLevel_3_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_266[] = {
+	 { "MemoryLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_267[] = {
+	 { "MemoryLevel_3_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_268[] = {
+	 { "MemoryLevel_3_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_269[] = {
+	 { "MemoryLevel_3_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_270[] = {
+	 { "MemoryLevel_3_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_271[] = {
+	 { "MemoryLevel_3_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_272[] = {
+	 { "MemoryLevel_3_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_273[] = {
+	 { "MemoryLevel_3_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_274[] = {
+	 { "MemoryLevel_3_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_275[] = {
+	 { "MemoryLevel_3_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_276[] = {
+	 { "MemoryLevel_3_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_277[] = {
+	 { "MemoryLevel_4_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_278[] = {
+	 { "MemoryLevel_4_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_279[] = {
+	 { "MemoryLevel_4_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_280[] = {
+	 { "MemoryLevel_4_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_281[] = {
+	 { "MemoryLevel_4_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_282[] = {
+	 { "MemoryLevel_4_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_4_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_4_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_4_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_283[] = {
+	 { "MemoryLevel_4_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_4_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_4_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_4_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_284[] = {
+	 { "MemoryLevel_4_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_4_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_4_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_4_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_285[] = {
+	 { "MemoryLevel_4_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_4_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_4_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_286[] = {
+	 { "MemoryLevel_4_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_287[] = {
+	 { "MemoryLevel_4_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_288[] = {
+	 { "MemoryLevel_4_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_289[] = {
+	 { "MemoryLevel_4_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_290[] = {
+	 { "MemoryLevel_4_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_291[] = {
+	 { "MemoryLevel_4_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_292[] = {
+	 { "MemoryLevel_4_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_293[] = {
+	 { "MemoryLevel_4_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_294[] = {
+	 { "MemoryLevel_4_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_295[] = {
+	 { "MemoryLevel_5_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_296[] = {
+	 { "MemoryLevel_5_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_297[] = {
+	 { "MemoryLevel_5_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_298[] = {
+	 { "MemoryLevel_5_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_299[] = {
+	 { "MemoryLevel_5_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_300[] = {
+	 { "MemoryLevel_5_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_5_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_5_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_5_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_301[] = {
+	 { "MemoryLevel_5_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_5_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_5_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_5_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_302[] = {
+	 { "MemoryLevel_5_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_5_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_5_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_5_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_303[] = {
+	 { "MemoryLevel_5_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_5_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_5_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_304[] = {
+	 { "MemoryLevel_5_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_305[] = {
+	 { "MemoryLevel_5_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_306[] = {
+	 { "MemoryLevel_5_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_307[] = {
+	 { "MemoryLevel_5_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_308[] = {
+	 { "MemoryLevel_5_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_309[] = {
+	 { "MemoryLevel_5_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_310[] = {
+	 { "MemoryLevel_5_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_311[] = {
+	 { "MemoryLevel_5_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_312[] = {
+	 { "MemoryLevel_5_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_313[] = {
+	 { "LinkLevel_0_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_314[] = {
+	 { "LinkLevel_0_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_315[] = {
+	 { "LinkLevel_0_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_316[] = {
+	 { "LinkLevel_0_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_317[] = {
+	 { "LinkLevel_1_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_318[] = {
+	 { "LinkLevel_1_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_319[] = {
+	 { "LinkLevel_1_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_320[] = {
+	 { "LinkLevel_1_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_321[] = {
+	 { "LinkLevel_2_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_322[] = {
+	 { "LinkLevel_2_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_323[] = {
+	 { "LinkLevel_2_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_324[] = {
+	 { "LinkLevel_2_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_325[] = {
+	 { "LinkLevel_3_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_326[] = {
+	 { "LinkLevel_3_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_327[] = {
+	 { "LinkLevel_3_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_328[] = {
+	 { "LinkLevel_3_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_329[] = {
+	 { "LinkLevel_4_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_330[] = {
+	 { "LinkLevel_4_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_331[] = {
+	 { "LinkLevel_4_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_332[] = {
+	 { "LinkLevel_4_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_333[] = {
+	 { "LinkLevel_5_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_334[] = {
+	 { "LinkLevel_5_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_335[] = {
+	 { "LinkLevel_5_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_336[] = {
+	 { "LinkLevel_5_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_337[] = {
+	 { "LinkLevel_6_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_338[] = {
+	 { "LinkLevel_6_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_339[] = {
+	 { "LinkLevel_6_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_340[] = {
+	 { "LinkLevel_6_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_341[] = {
+	 { "LinkLevel_7_Padding", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_342[] = {
+	 { "LinkLevel_7_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_343[] = {
+	 { "LinkLevel_7_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_344[] = {
+	 { "LinkLevel_7_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_345[] = {
+	 { "ACPILevel_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_346[] = {
+	 { "ACPILevel_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_347[] = {
+	 { "ACPILevel_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_348[] = {
+	 { "ACPILevel_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_349[] = {
+	 { "ACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_350[] = {
+	 { "ACPILevel_CgSpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_351[] = {
+	 { "ACPILevel_CgSpllFuncCntl2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_352[] = {
+	 { "ACPILevel_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_353[] = {
+	 { "ACPILevel_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_354[] = {
+	 { "ACPILevel_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_355[] = {
+	 { "ACPILevel_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_356[] = {
+	 { "ACPILevel_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_357[] = {
+	 { "ACPILevel_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_358[] = {
+	 { "UvdLevel_0_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_359[] = {
+	 { "UvdLevel_0_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_360[] = {
+	 { "UvdLevel_0_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_361[] = {
+	 { "UvdLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_0_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_362[] = {
+	 { "UvdLevel_1_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_363[] = {
+	 { "UvdLevel_1_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_364[] = {
+	 { "UvdLevel_1_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_365[] = {
+	 { "UvdLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_1_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_366[] = {
+	 { "UvdLevel_2_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_367[] = {
+	 { "UvdLevel_2_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_368[] = {
+	 { "UvdLevel_2_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_369[] = {
+	 { "UvdLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_2_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_370[] = {
+	 { "UvdLevel_3_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_371[] = {
+	 { "UvdLevel_3_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_372[] = {
+	 { "UvdLevel_3_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_373[] = {
+	 { "UvdLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_3_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_374[] = {
+	 { "UvdLevel_4_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_375[] = {
+	 { "UvdLevel_4_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_376[] = {
+	 { "UvdLevel_4_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_377[] = {
+	 { "UvdLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_4_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_378[] = {
+	 { "UvdLevel_5_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_379[] = {
+	 { "UvdLevel_5_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_380[] = {
+	 { "UvdLevel_5_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_381[] = {
+	 { "UvdLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_5_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_382[] = {
+	 { "UvdLevel_6_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_383[] = {
+	 { "UvdLevel_6_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_384[] = {
+	 { "UvdLevel_6_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_385[] = {
+	 { "UvdLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_6_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_386[] = {
+	 { "UvdLevel_7_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_387[] = {
+	 { "UvdLevel_7_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_388[] = {
+	 { "UvdLevel_7_VclkDivider", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVddcPhases", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_389[] = {
+	 { "UvdLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_7_DclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_390[] = {
+	 { "VceLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_391[] = {
+	 { "VceLevel_0_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_0_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_392[] = {
+	 { "VceLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_393[] = {
+	 { "VceLevel_1_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_1_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_394[] = {
+	 { "VceLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_395[] = {
+	 { "VceLevel_2_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_2_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_396[] = {
+	 { "VceLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_397[] = {
+	 { "VceLevel_3_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_3_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_398[] = {
+	 { "VceLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_399[] = {
+	 { "VceLevel_4_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_4_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_400[] = {
+	 { "VceLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_401[] = {
+	 { "VceLevel_5_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_5_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_402[] = {
+	 { "VceLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_403[] = {
+	 { "VceLevel_6_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_6_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_404[] = {
+	 { "VceLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_405[] = {
+	 { "VceLevel_7_Divider", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_7_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_406[] = {
+	 { "AcpLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_407[] = {
+	 { "AcpLevel_0_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_0_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_408[] = {
+	 { "AcpLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_409[] = {
+	 { "AcpLevel_1_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_1_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_410[] = {
+	 { "AcpLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_411[] = {
+	 { "AcpLevel_2_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_2_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_412[] = {
+	 { "AcpLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_413[] = {
+	 { "AcpLevel_3_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_3_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_414[] = {
+	 { "AcpLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_415[] = {
+	 { "AcpLevel_4_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_4_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_416[] = {
+	 { "AcpLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_417[] = {
+	 { "AcpLevel_5_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_5_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_418[] = {
+	 { "AcpLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_419[] = {
+	 { "AcpLevel_6_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_6_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_420[] = {
+	 { "AcpLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_421[] = {
+	 { "AcpLevel_7_Divider", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_7_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_422[] = {
+	 { "SamuLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_423[] = {
+	 { "SamuLevel_0_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_0_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_424[] = {
+	 { "SamuLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_425[] = {
+	 { "SamuLevel_1_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_1_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_426[] = {
+	 { "SamuLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_427[] = {
+	 { "SamuLevel_2_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_2_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_428[] = {
+	 { "SamuLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_429[] = {
+	 { "SamuLevel_3_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_3_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_430[] = {
+	 { "SamuLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_431[] = {
+	 { "SamuLevel_4_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_4_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_432[] = {
+	 { "SamuLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_433[] = {
+	 { "SamuLevel_5_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_5_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_434[] = {
+	 { "SamuLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_435[] = {
+	 { "SamuLevel_6_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_6_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_436[] = {
+	 { "SamuLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_437[] = {
+	 { "SamuLevel_7_Divider", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_7_MinPhases", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_438[] = {
+	 { "Ulv_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_439[] = {
+	 { "Ulv_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_440[] = {
+	 { "Ulv_VddcPhase", 0, 7, &umr_bitfield_default },
+	 { "Ulv_VddcOffsetVid", 8, 15, &umr_bitfield_default },
+	 { "Ulv_VddcOffset", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_441[] = {
+	 { "Ulv_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_442[] = {
+	 { "SclkStepSize", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_443[] = {
+	 { "Smio_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_444[] = {
+	 { "Smio_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_445[] = {
+	 { "Smio_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_446[] = {
+	 { "Smio_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_447[] = {
+	 { "Smio_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_448[] = {
+	 { "Smio_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_449[] = {
+	 { "Smio_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_450[] = {
+	 { "Smio_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_451[] = {
+	 { "Smio_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_452[] = {
+	 { "Smio_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_453[] = {
+	 { "Smio_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_454[] = {
+	 { "Smio_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_455[] = {
+	 { "Smio_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_456[] = {
+	 { "Smio_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_457[] = {
+	 { "Smio_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_458[] = {
+	 { "Smio_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_459[] = {
+	 { "Smio_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_460[] = {
+	 { "Smio_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_461[] = {
+	 { "Smio_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_462[] = {
+	 { "Smio_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_463[] = {
+	 { "Smio_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_464[] = {
+	 { "Smio_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_465[] = {
+	 { "Smio_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_466[] = {
+	 { "Smio_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_467[] = {
+	 { "Smio_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_468[] = {
+	 { "Smio_25", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_469[] = {
+	 { "Smio_26", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_470[] = {
+	 { "Smio_27", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_471[] = {
+	 { "Smio_28", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_472[] = {
+	 { "Smio_29", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_473[] = {
+	 { "Smio_30", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_474[] = {
+	 { "Smio_31", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_475[] = {
+	 { "SamuBootLevel", 0, 7, &umr_bitfield_default },
+	 { "AcpBootLevel", 8, 15, &umr_bitfield_default },
+	 { "VceBootLevel", 16, 23, &umr_bitfield_default },
+	 { "UvdBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_476[] = {
+	 { "SAMUInterval", 0, 7, &umr_bitfield_default },
+	 { "ACPInterval", 8, 15, &umr_bitfield_default },
+	 { "VCEInterval", 16, 23, &umr_bitfield_default },
+	 { "UVDInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_477[] = {
+	 { "GraphicsInterval", 0, 7, &umr_bitfield_default },
+	 { "GraphicsThermThrottleEnable", 8, 15, &umr_bitfield_default },
+	 { "GraphicsVoltageChangeEnable", 16, 23, &umr_bitfield_default },
+	 { "GraphicsBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_478[] = {
+	 { "TemperatureLimitHigh", 0, 15, &umr_bitfield_default },
+	 { "ThermalInterval", 16, 23, &umr_bitfield_default },
+	 { "VoltageInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_479[] = {
+	 { "MemoryVoltageChangeEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryBootLevel", 8, 15, &umr_bitfield_default },
+	 { "TemperatureLimitLow", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_480[] = {
+	 { "VddcVddciDelta", 0, 15, &umr_bitfield_default },
+	 { "MemoryThermThrottleEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_481[] = {
+	 { "PhaseResponseTime", 0, 15, &umr_bitfield_default },
+	 { "VoltageResponseTime", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_482[] = {
+	 { "DTEMode", 0, 7, &umr_bitfield_default },
+	 { "DTEInterval", 8, 15, &umr_bitfield_default },
+	 { "PCIeGenInterval", 16, 23, &umr_bitfield_default },
+	 { "PCIeBootLinkLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_483[] = {
+	 { "ThermGpio", 0, 7, &umr_bitfield_default },
+	 { "AcDcGpio", 8, 15, &umr_bitfield_default },
+	 { "VRHotGpio", 16, 23, &umr_bitfield_default },
+	 { "SVI2Enable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_484[] = {
+	 { "PPM_TemperatureLimit", 0, 15, &umr_bitfield_default },
+	 { "PPM_PkgPwrLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_485[] = {
+	 { "TargetTdp", 0, 15, &umr_bitfield_default },
+	 { "DefaultTdp", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_486[] = {
+	 { "FpsLowThreshold", 0, 15, &umr_bitfield_default },
+	 { "FpsHighThreshold", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_487[] = {
+	 { "BAPMTI_R_0_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_488[] = {
+	 { "BAPMTI_R_1_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_489[] = {
+	 { "BAPMTI_R_1_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_1_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_490[] = {
+	 { "BAPMTI_R_2_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_491[] = {
+	 { "BAPMTI_R_3_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_492[] = {
+	 { "BAPMTI_R_3_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_3_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_493[] = {
+	 { "BAPMTI_R_4_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_494[] = {
+	 { "BAPMTI_RC_0_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_495[] = {
+	 { "BAPMTI_RC_0_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_0_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_496[] = {
+	 { "BAPMTI_RC_1_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_497[] = {
+	 { "BAPMTI_RC_2_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_498[] = {
+	 { "BAPMTI_RC_2_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_2_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_499[] = {
+	 { "BAPMTI_RC_3_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_500[] = {
+	 { "BAPMTI_RC_4_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_501[] = {
+	 { "BAPMTI_RC_4_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_4_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_502[] = {
+	 { "GpuTjHyst", 0, 7, &umr_bitfield_default },
+	 { "GpuTjMax", 8, 15, &umr_bitfield_default },
+	 { "DTETjOffset", 16, 23, &umr_bitfield_default },
+	 { "DTEAmbientTempBase", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_503[] = {
+	 { "BootVddci", 0, 15, &umr_bitfield_default },
+	 { "BootVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_504[] = {
+	 { "padding", 0, 7, &umr_bitfield_default },
+	 { "PccGpio", 8, 15, &umr_bitfield_default },
+	 { "BootMVdd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_505[] = {
+	 { "BAPM_TEMP_GRADIENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_506[] = {
+	 { "LowSclkInterruptThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFIRMWARE_FLAGS[] = {
+	 { "INTERRUPTS_ENABLED", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 23, &umr_bitfield_default },
+	 { "TEST_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_STATUS[] = {
+	 { "VDD_Boost", 0, 7, &umr_bitfield_default },
+	 { "VDD_Throttle", 8, 15, &umr_bitfield_default },
+	 { "VDDC_Boost", 16, 23, &umr_bitfield_default },
+	 { "VDDC_Throttle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_MV_AVERAGE[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_VRM_LIMIT[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFEATURE_STATUS[] = {
+	 { "SCLK_DPM_ON", 0, 0, &umr_bitfield_default },
+	 { "MCLK_DPM_ON", 1, 1, &umr_bitfield_default },
+	 { "LCLK_DPM_ON", 2, 2, &umr_bitfield_default },
+	 { "UVD_DPM_ON", 3, 3, &umr_bitfield_default },
+	 { "VCE_DPM_ON", 4, 4, &umr_bitfield_default },
+	 { "ACP_DPM_ON", 5, 5, &umr_bitfield_default },
+	 { "SAMU_DPM_ON", 6, 6, &umr_bitfield_default },
+	 { "PCIE_DPM_ON", 7, 7, &umr_bitfield_default },
+	 { "BAPM_ON", 8, 8, &umr_bitfield_default },
+	 { "LPMX_ON", 9, 9, &umr_bitfield_default },
+	 { "NBDPM_ON", 10, 10, &umr_bitfield_default },
+	 { "LHTC_ON", 11, 11, &umr_bitfield_default },
+	 { "VPC_ON", 12, 12, &umr_bitfield_default },
+	 { "VOLTAGE_CONTROLLER_ON", 13, 13, &umr_bitfield_default },
+	 { "TDC_LIMIT_ON", 14, 14, &umr_bitfield_default },
+	 { "GPU_CAC_ON", 15, 15, &umr_bitfield_default },
+	 { "AVS_ON", 16, 16, &umr_bitfield_default },
+	 { "SPMI_ON", 17, 17, &umr_bitfield_default },
+	 { "SCLK_DPM_FORCED", 18, 18, &umr_bitfield_default },
+	 { "MCLK_DPM_FORCED", 19, 19, &umr_bitfield_default },
+	 { "LCLK_DPM_FORCED", 20, 20, &umr_bitfield_default },
+	 { "PCIE_DPM_FORCED", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixENTITY_TEMPERATURES_1[] = {
+	 { "GPU", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_1[] = {
+	 { "entries_0_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_2[] = {
+	 { "entries_0_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_3[] = {
+	 { "entries_0_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_4[] = {
+	 { "entries_0_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_5[] = {
+	 { "entries_0_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_6[] = {
+	 { "entries_0_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_7[] = {
+	 { "entries_0_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_8[] = {
+	 { "entries_0_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_9[] = {
+	 { "entries_0_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_10[] = {
+	 { "entries_0_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_11[] = {
+	 { "entries_0_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_12[] = {
+	 { "entries_0_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_13[] = {
+	 { "entries_0_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_14[] = {
+	 { "entries_0_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_15[] = {
+	 { "entries_0_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_16[] = {
+	 { "entries_0_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_17[] = {
+	 { "entries_0_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_18[] = {
+	 { "entries_0_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_19[] = {
+	 { "entries_1_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_20[] = {
+	 { "entries_1_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_21[] = {
+	 { "entries_1_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_22[] = {
+	 { "entries_1_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_23[] = {
+	 { "entries_1_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_24[] = {
+	 { "entries_1_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_25[] = {
+	 { "entries_1_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_26[] = {
+	 { "entries_1_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_27[] = {
+	 { "entries_1_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_28[] = {
+	 { "entries_1_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_29[] = {
+	 { "entries_1_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_30[] = {
+	 { "entries_1_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_31[] = {
+	 { "entries_1_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_32[] = {
+	 { "entries_1_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_33[] = {
+	 { "entries_1_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_34[] = {
+	 { "entries_1_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_35[] = {
+	 { "entries_1_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_36[] = {
+	 { "entries_1_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_37[] = {
+	 { "entries_2_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_38[] = {
+	 { "entries_2_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_39[] = {
+	 { "entries_2_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_40[] = {
+	 { "entries_2_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_41[] = {
+	 { "entries_2_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_42[] = {
+	 { "entries_2_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_43[] = {
+	 { "entries_2_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_44[] = {
+	 { "entries_2_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_45[] = {
+	 { "entries_2_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_46[] = {
+	 { "entries_2_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_47[] = {
+	 { "entries_2_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_48[] = {
+	 { "entries_2_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_49[] = {
+	 { "entries_2_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_50[] = {
+	 { "entries_2_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_51[] = {
+	 { "entries_2_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_52[] = {
+	 { "entries_2_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_53[] = {
+	 { "entries_2_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_54[] = {
+	 { "entries_2_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_55[] = {
+	 { "entries_3_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_56[] = {
+	 { "entries_3_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_57[] = {
+	 { "entries_3_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_58[] = {
+	 { "entries_3_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_59[] = {
+	 { "entries_3_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_60[] = {
+	 { "entries_3_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_61[] = {
+	 { "entries_3_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_62[] = {
+	 { "entries_3_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_63[] = {
+	 { "entries_3_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_64[] = {
+	 { "entries_3_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_65[] = {
+	 { "entries_3_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_66[] = {
+	 { "entries_3_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_67[] = {
+	 { "entries_3_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_68[] = {
+	 { "entries_3_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_69[] = {
+	 { "entries_3_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_70[] = {
+	 { "entries_3_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_71[] = {
+	 { "entries_3_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_72[] = {
+	 { "entries_3_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_73[] = {
+	 { "entries_4_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_74[] = {
+	 { "entries_4_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_75[] = {
+	 { "entries_4_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_76[] = {
+	 { "entries_4_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_77[] = {
+	 { "entries_4_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_78[] = {
+	 { "entries_4_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_79[] = {
+	 { "entries_4_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_80[] = {
+	 { "entries_4_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_81[] = {
+	 { "entries_4_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_82[] = {
+	 { "entries_4_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_83[] = {
+	 { "entries_4_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_84[] = {
+	 { "entries_4_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_85[] = {
+	 { "entries_4_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_86[] = {
+	 { "entries_4_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_87[] = {
+	 { "entries_4_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_88[] = {
+	 { "entries_4_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_89[] = {
+	 { "entries_4_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_90[] = {
+	 { "entries_4_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_91[] = {
+	 { "entries_5_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_92[] = {
+	 { "entries_5_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_93[] = {
+	 { "entries_5_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_94[] = {
+	 { "entries_5_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_95[] = {
+	 { "entries_5_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_96[] = {
+	 { "entries_5_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_97[] = {
+	 { "entries_5_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_98[] = {
+	 { "entries_5_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_99[] = {
+	 { "entries_5_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_100[] = {
+	 { "entries_5_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_101[] = {
+	 { "entries_5_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_102[] = {
+	 { "entries_5_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_103[] = {
+	 { "entries_5_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_104[] = {
+	 { "entries_5_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_105[] = {
+	 { "entries_5_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_106[] = {
+	 { "entries_5_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_107[] = {
+	 { "entries_5_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_108[] = {
+	 { "entries_5_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_109[] = {
+	 { "entries_6_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_110[] = {
+	 { "entries_6_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_111[] = {
+	 { "entries_6_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_112[] = {
+	 { "entries_6_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_113[] = {
+	 { "entries_6_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_114[] = {
+	 { "entries_6_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_115[] = {
+	 { "entries_6_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_116[] = {
+	 { "entries_6_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_117[] = {
+	 { "entries_6_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_118[] = {
+	 { "entries_6_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_119[] = {
+	 { "entries_6_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_120[] = {
+	 { "entries_6_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_121[] = {
+	 { "entries_6_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_122[] = {
+	 { "entries_6_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_123[] = {
+	 { "entries_6_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_124[] = {
+	 { "entries_6_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_125[] = {
+	 { "entries_6_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_126[] = {
+	 { "entries_6_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_127[] = {
+	 { "entries_7_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_128[] = {
+	 { "entries_7_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_129[] = {
+	 { "entries_7_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_130[] = {
+	 { "entries_7_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_131[] = {
+	 { "entries_7_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_132[] = {
+	 { "entries_7_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_133[] = {
+	 { "entries_7_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_134[] = {
+	 { "entries_7_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_135[] = {
+	 { "entries_7_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_136[] = {
+	 { "entries_7_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_137[] = {
+	 { "entries_7_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_138[] = {
+	 { "entries_7_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_139[] = {
+	 { "entries_7_4_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_140[] = {
+	 { "entries_7_4_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_141[] = {
+	 { "entries_7_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_4_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_142[] = {
+	 { "entries_7_5_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_143[] = {
+	 { "entries_7_5_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_144[] = {
+	 { "entries_7_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_5_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_1[] = {
+	 { "reserved_2", 0, 7, &umr_bitfield_default },
+	 { "reserved_1", 8, 15, &umr_bitfield_default },
+	 { "reserved_0", 16, 23, &umr_bitfield_default },
+	 { "last", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_2[] = {
+	 { "address_0_s1", 0, 15, &umr_bitfield_default },
+	 { "address_0_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_3[] = {
+	 { "address_1_s1", 0, 15, &umr_bitfield_default },
+	 { "address_1_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_4[] = {
+	 { "address_2_s1", 0, 15, &umr_bitfield_default },
+	 { "address_2_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_5[] = {
+	 { "address_3_s1", 0, 15, &umr_bitfield_default },
+	 { "address_3_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_6[] = {
+	 { "address_4_s1", 0, 15, &umr_bitfield_default },
+	 { "address_4_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_7[] = {
+	 { "address_5_s1", 0, 15, &umr_bitfield_default },
+	 { "address_5_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_8[] = {
+	 { "address_6_s1", 0, 15, &umr_bitfield_default },
+	 { "address_6_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_9[] = {
+	 { "address_7_s1", 0, 15, &umr_bitfield_default },
+	 { "address_7_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_10[] = {
+	 { "address_8_s1", 0, 15, &umr_bitfield_default },
+	 { "address_8_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_11[] = {
+	 { "address_9_s1", 0, 15, &umr_bitfield_default },
+	 { "address_9_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_12[] = {
+	 { "address_10_s1", 0, 15, &umr_bitfield_default },
+	 { "address_10_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_13[] = {
+	 { "address_11_s1", 0, 15, &umr_bitfield_default },
+	 { "address_11_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_14[] = {
+	 { "address_12_s1", 0, 15, &umr_bitfield_default },
+	 { "address_12_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_15[] = {
+	 { "address_13_s1", 0, 15, &umr_bitfield_default },
+	 { "address_13_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_16[] = {
+	 { "address_14_s1", 0, 15, &umr_bitfield_default },
+	 { "address_14_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_17[] = {
+	 { "address_15_s1", 0, 15, &umr_bitfield_default },
+	 { "address_15_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_18[] = {
+	 { "data_0_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_19[] = {
+	 { "data_0_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_20[] = {
+	 { "data_0_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_21[] = {
+	 { "data_0_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_22[] = {
+	 { "data_0_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_23[] = {
+	 { "data_0_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_24[] = {
+	 { "data_0_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_25[] = {
+	 { "data_0_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_26[] = {
+	 { "data_0_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_27[] = {
+	 { "data_0_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_28[] = {
+	 { "data_0_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_29[] = {
+	 { "data_0_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_30[] = {
+	 { "data_0_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_31[] = {
+	 { "data_0_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_32[] = {
+	 { "data_0_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_33[] = {
+	 { "data_0_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_34[] = {
+	 { "data_1_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_35[] = {
+	 { "data_1_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_36[] = {
+	 { "data_1_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_37[] = {
+	 { "data_1_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_38[] = {
+	 { "data_1_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_39[] = {
+	 { "data_1_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_40[] = {
+	 { "data_1_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_41[] = {
+	 { "data_1_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_42[] = {
+	 { "data_1_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_43[] = {
+	 { "data_1_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_44[] = {
+	 { "data_1_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_45[] = {
+	 { "data_1_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_46[] = {
+	 { "data_1_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_47[] = {
+	 { "data_1_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_48[] = {
+	 { "data_1_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_49[] = {
+	 { "data_1_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_50[] = {
+	 { "data_2_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_51[] = {
+	 { "data_2_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_52[] = {
+	 { "data_2_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_53[] = {
+	 { "data_2_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_54[] = {
+	 { "data_2_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_55[] = {
+	 { "data_2_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_56[] = {
+	 { "data_2_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_57[] = {
+	 { "data_2_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_58[] = {
+	 { "data_2_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_59[] = {
+	 { "data_2_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_60[] = {
+	 { "data_2_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_61[] = {
+	 { "data_2_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_62[] = {
+	 { "data_2_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_63[] = {
+	 { "data_2_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_64[] = {
+	 { "data_2_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_65[] = {
+	 { "data_2_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_66[] = {
+	 { "data_3_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_67[] = {
+	 { "data_3_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_68[] = {
+	 { "data_3_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_69[] = {
+	 { "data_3_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_70[] = {
+	 { "data_3_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_71[] = {
+	 { "data_3_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_72[] = {
+	 { "data_3_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_73[] = {
+	 { "data_3_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_74[] = {
+	 { "data_3_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_75[] = {
+	 { "data_3_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_76[] = {
+	 { "data_3_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_77[] = {
+	 { "data_3_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_78[] = {
+	 { "data_3_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_79[] = {
+	 { "data_3_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_80[] = {
+	 { "data_3_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_81[] = {
+	 { "data_3_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_82[] = {
+	 { "data_4_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_83[] = {
+	 { "data_4_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_84[] = {
+	 { "data_4_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_85[] = {
+	 { "data_4_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_86[] = {
+	 { "data_4_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_87[] = {
+	 { "data_4_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_88[] = {
+	 { "data_4_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_89[] = {
+	 { "data_4_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_90[] = {
+	 { "data_4_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_91[] = {
+	 { "data_4_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_92[] = {
+	 { "data_4_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_93[] = {
+	 { "data_4_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_94[] = {
+	 { "data_4_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_95[] = {
+	 { "data_4_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_96[] = {
+	 { "data_4_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_97[] = {
+	 { "data_4_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_98[] = {
+	 { "data_5_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_99[] = {
+	 { "data_5_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_100[] = {
+	 { "data_5_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_101[] = {
+	 { "data_5_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_102[] = {
+	 { "data_5_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_103[] = {
+	 { "data_5_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_104[] = {
+	 { "data_5_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_105[] = {
+	 { "data_5_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_106[] = {
+	 { "data_5_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_107[] = {
+	 { "data_5_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_108[] = {
+	 { "data_5_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_109[] = {
+	 { "data_5_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_110[] = {
+	 { "data_5_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_111[] = {
+	 { "data_5_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_112[] = {
+	 { "data_5_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_113[] = {
+	 { "data_5_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_1[] = {
+	 { "TempMin", 0, 15, &umr_bitfield_default },
+	 { "FdoMode", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_2[] = {
+	 { "TempMax", 0, 15, &umr_bitfield_default },
+	 { "TempMed", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_3[] = {
+	 { "Slope2", 0, 15, &umr_bitfield_default },
+	 { "Slope1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_4[] = {
+	 { "HystUp", 0, 15, &umr_bitfield_default },
+	 { "FdoMin", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_5[] = {
+	 { "HystSlope", 0, 15, &umr_bitfield_default },
+	 { "HystDown", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_6[] = {
+	 { "TempCurr", 0, 15, &umr_bitfield_default },
+	 { "TempRespLim", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_7[] = {
+	 { "PwmCurr", 0, 15, &umr_bitfield_default },
+	 { "SlopeCurr", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_8[] = {
+	 { "RefreshPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_9[] = {
+	 { "Padding", 0, 7, &umr_bitfield_default },
+	 { "TempSrc", 8, 15, &umr_bitfield_default },
+	 { "FdoMax", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_1[] = {
+	 { "RefClockFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_2[] = {
+	 { "PmTimerPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_3[] = {
+	 { "FeatureEnables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_4[] = {
+	 { "PreVBlankGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_5[] = {
+	 { "VBlankTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_6[] = {
+	 { "TrainTimeGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_7[] = {
+	 { "MvddSwitchTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_8[] = {
+	 { "LongestAcpiTrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_9[] = {
+	 { "AcpiDelay", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_10[] = {
+	 { "G5TrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_11[] = {
+	 { "DelayMpllPwron", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_12[] = {
+	 { "VoltageChangeTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_13[] = {
+	 { "HandshakeDisables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_14[] = {
+	 { "DisplayPhy4Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy3Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy2Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy1Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_15[] = {
+	 { "DisplayPhy8Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy7Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy6Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy5Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_16[] = {
+	 { "AverageGraphicsActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_17[] = {
+	 { "AverageMemoryActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_18[] = {
+	 { "AverageGioActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_19[] = {
+	 { "PCIeDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "LClkDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "MClkDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "SClkDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_20[] = {
+	 { "VCEDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "ACPDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "SAMUDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "UVDDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_21[] = {
+	 { "DRAM_LOG_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_22[] = {
+	 { "DRAM_LOG_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_23[] = {
+	 { "DRAM_LOG_PHY_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_24[] = {
+	 { "DRAM_LOG_PHY_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_25[] = {
+	 { "DRAM_LOG_BUFF_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_26[] = {
+	 { "UlvEnterCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_27[] = {
+	 { "UlvTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_28[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_29[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_30[] = {
+	 { "Reserved_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_1[] = {
+	 { "BapmVddCVidHiSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_2[] = {
+	 { "BapmVddCVidHiSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_3[] = {
+	 { "BapmVddCVidLoSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_4[] = {
+	 { "BapmVddCVidLoSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_5[] = {
+	 { "VddCVid_3", 0, 7, &umr_bitfield_default },
+	 { "VddCVid_2", 8, 15, &umr_bitfield_default },
+	 { "VddCVid_1", 16, 23, &umr_bitfield_default },
+	 { "VddCVid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_6[] = {
+	 { "VddCVid_7", 0, 7, &umr_bitfield_default },
+	 { "VddCVid_6", 8, 15, &umr_bitfield_default },
+	 { "VddCVid_5", 16, 23, &umr_bitfield_default },
+	 { "VddCVid_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_7[] = {
+	 { "SviLoadLineOffsetVddC", 0, 7, &umr_bitfield_default },
+	 { "SviLoadLineTrimVddC", 8, 15, &umr_bitfield_default },
+	 { "SviLoadLineVddC", 16, 23, &umr_bitfield_default },
+	 { "SviLoadLineEn", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_8[] = {
+	 { "TDC_MAWt", 0, 7, &umr_bitfield_default },
+	 { "TDC_VDDC_ThrottleReleaseLimitPerc", 8, 15, &umr_bitfield_default },
+	 { "TDC_VDDC_PkgLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_9[] = {
+	 { "Reserved", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureMax", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureMin", 16, 23, &umr_bitfield_default },
+	 { "TdcWaterfallCtl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_10[] = {
+	 { "BapmVddCVidHiSidd2_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd2_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd2_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd2_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_11[] = {
+	 { "BapmVddCVidHiSidd2_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd2_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd2_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd2_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_12[] = {
+	 { "FuzzyFan_ErrorRateSetDelta", 0, 15, &umr_bitfield_default },
+	 { "FuzzyFan_ErrorSetDelta", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_13[] = {
+	 { "Reserved6", 0, 15, &umr_bitfield_default },
+	 { "FuzzyFan_PwmSetDelta", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_14[] = {
+	 { "GnbLPML_3", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_2", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_1", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_15[] = {
+	 { "GnbLPML_7", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_6", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_5", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_16[] = {
+	 { "GnbLPML_11", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_10", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_9", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_17[] = {
+	 { "GnbLPML_15", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_14", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_13", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_18[] = {
+	 { "Reserved1_1", 0, 7, &umr_bitfield_default },
+	 { "Reserved1_0", 8, 15, &umr_bitfield_default },
+	 { "GnbLPMLMinVid", 16, 23, &umr_bitfield_default },
+	 { "GnbLPMLMaxVid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_19[] = {
+	 { "BapmVddCBaseLeakageLoSidd", 0, 15, &umr_bitfield_default },
+	 { "BapmVddCBaseLeakageHiSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_16[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_17[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_18[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_19[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_20[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_21[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_22[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_24[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_25[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_26[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_27[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_28[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_29[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_30[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_31[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_32[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_33[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_34[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_35[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_36[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_37[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_38[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_39[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_40[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_41[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_42[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_43[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_44[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_46[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_47[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_48[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_49[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_50[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_51[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_52[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_53[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_54[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_55[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_56[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_57[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_58[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_59[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_60[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_61[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_62[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_63[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_64[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_65[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_66[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_67[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_68[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_69[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_70[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_71[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_72[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_73[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_74[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_75[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_76[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_77[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_78[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_79[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_80[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_81[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_82[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_83[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_84[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_85[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_86[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_87[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_88[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_89[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_90[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_91[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_92[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_93[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_94[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_95[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_96[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_97[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_98[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_99[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_100[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_101[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_102[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_103[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_104[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_105[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_106[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_107[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_108[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_109[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_110[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_111[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_112[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_113[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_114[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_115[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_116[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_117[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_118[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_119[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_120[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_121[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_122[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_123[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_124[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_125[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_126[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_127[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_RESET_CNTL[] = {
+	 { "rst_reg", 0, 0, &umr_bitfield_default },
+	 { "srbm_soft_rst_override", 1, 1, &umr_bitfield_default },
+	 { "RegReset", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_0[] = {
+	 { "ck_disable", 0, 0, &umr_bitfield_default },
+	 { "auto_cg_en", 1, 1, &umr_bitfield_default },
+	 { "auto_cg_timeout", 8, 23, &umr_bitfield_default },
+	 { "cken", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_1[] = {
+	 { "auto_ck_disable", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_2[] = {
+	 { "wake_on_irq", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_MSG_ARG_0[] = {
+	 { "smc_msg_arg", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_PC_C[] = {
+	 { "smc_pc_c", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SCRATCH9[] = {
+	 { "SCRATCH_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_ACCESS_CNTL[] = {
+	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_1", 1, 1, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_2", 2, 2, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_3", 3, 3, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_4", 4, 4, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_5", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_6", 6, 6, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_7", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_11[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_0[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_0[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_1[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_1[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_2[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_2[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_3[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_3[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_4[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_4[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_5[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_5[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_6[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_6[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_7[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_7[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_0[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_1[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_2[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_3[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_4[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_5[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_6[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_7[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_8[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_8[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_9[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_9[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_10[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_10[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_11[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_11[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_8[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_9[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_10[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_UC_EVENTS[] = {
+	 { "RCU_TST_jpc_rep_req", 0, 0, &umr_bitfield_default },
+	 { "TST_RCU_jpc_rep_done", 1, 1, &umr_bitfield_default },
+	 { "drv_rst_mode", 2, 2, &umr_bitfield_default },
+	 { "SMU_DC_efuse_status_invalid", 3, 3, &umr_bitfield_default },
+	 { "TP_Tester", 6, 6, &umr_bitfield_default },
+	 { "boot_seq_done", 7, 7, &umr_bitfield_default },
+	 { "sclk_deep_sleep_exit", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_ACTIVE", 9, 9, &umr_bitfield_default },
+	 { "BREAK_PT2_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "FCH_HALT", 11, 11, &umr_bitfield_default },
+	 { "RCU_GIO_fch_lockdown", 13, 13, &umr_bitfield_default },
+	 { "INTERRUPTS_ENABLED", 16, 16, &umr_bitfield_default },
+	 { "RCU_DtmCnt0_Done", 17, 17, &umr_bitfield_default },
+	 { "RCU_DtmCnt1_Done", 18, 18, &umr_bitfield_default },
+	 { "RCU_DtmCnt2_Done", 19, 19, &umr_bitfield_default },
+	 { "irq31_sel", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_MISC_CTRL[] = {
+	 { "REG_DRV_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "REG_RCU_MEMREP_DIS", 3, 3, &umr_bitfield_default },
+	 { "REG_CC_FUSE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "REG_SAMU_FUSE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "REG_CC_SRBM_RD_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_DONE", 16, 16, &umr_bitfield_default },
+	 { "BREAK_PT2_DONE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_START", 22, 22, &umr_bitfield_default },
+	 { "RST_PULSE_WIDTH", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_RCU_FUSES[] = {
+	 { "GPU_DIS", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "EFUSE_RD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "CG_RST_GLB_REQ_DIS", 5, 5, &umr_bitfield_default },
+	 { "DRV_RST_MODE", 6, 6, &umr_bitfield_default },
+	 { "ROM_DIS", 7, 7, &umr_bitfield_default },
+	 { "JPC_REP_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT1", 9, 9, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT2", 10, 10, &umr_bitfield_default },
+	 { "PHY_FUSE_VALID", 14, 14, &umr_bitfield_default },
+	 { "SMU_IOC_MST_DISABLE", 15, 15, &umr_bitfield_default },
+	 { "FCH_LOCKOUT_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "FCH_XFIRE_FILTER_ENABLE", 17, 17, &umr_bitfield_default },
+	 { "XFIRE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "SAMU_FUSE_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "BIF_RST_POLLING_DISABLE", 20, 20, &umr_bitfield_default },
+	 { "MEM_HARDREP_EN", 22, 22, &umr_bitfield_default },
+	 { "PCIE_INIT_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "DSMU_DISABLE", 24, 24, &umr_bitfield_default },
+	 { "RCU_SPARE", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_MISC_FUSES[] = {
+	 { "IOMMU_V2_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "MinSClkDid", 2, 8, &umr_bitfield_default },
+	 { "MISC_SPARE", 9, 10, &umr_bitfield_default },
+	 { "PostResetGnbClkDid", 11, 17, &umr_bitfield_default },
+	 { "L2IMU_tn2_dtc_half", 18, 18, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_half", 19, 19, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_half", 20, 20, &umr_bitfield_default },
+	 { "L2IMU_tn2_pdc_half", 21, 21, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_dis", 22, 22, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_dis", 23, 23, &umr_bitfield_default },
+	 { "VCE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "IOC_IOMMU_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "GNB_SPARE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SCLK_VID_FUSES[] = {
+	 { "SClkVid0", 0, 7, &umr_bitfield_default },
+	 { "SClkVid1", 8, 15, &umr_bitfield_default },
+	 { "SClkVid2", 16, 23, &umr_bitfield_default },
+	 { "SClkVid3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOCCFG_FUSES[] = {
+	 { "NB_REV_ID", 1, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOC_FUSES[] = {
+	 { "IOC_FUSES", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_TST_EFUSE1_MISC[] = {
+	 { "RF_RM_6_2", 1, 5, &umr_bitfield_default },
+	 { "RME", 6, 6, &umr_bitfield_default },
+	 { "MBIST_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "HARD_REPAIR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SOFT_REPAIR_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "GPU_DIS", 10, 10, &umr_bitfield_default },
+	 { "SMS_PWRDWN_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "CRBBMP1500_DISA", 12, 12, &umr_bitfield_default },
+	 { "CRBBMP1500_DISB", 13, 13, &umr_bitfield_default },
+	 { "RM_RF8", 14, 14, &umr_bitfield_default },
+	 { "DFT_SPARE1", 22, 22, &umr_bitfield_default },
+	 { "DFT_SPARE2", 23, 23, &umr_bitfield_default },
+	 { "DFT_SPARE3", 24, 24, &umr_bitfield_default },
+	 { "VCE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "DCE_SCAN_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_TST_ID_STRAPS[] = {
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_FCTRL_FUSES[] = {
+	 { "EXT_EFUSE_MACRO_PRESENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_EFUSE_0[] = {
+	 { "EFUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGENERAL_PWRMGT[] = {
+	 { "GLOBAL_PWRMGT_EN", 0, 0, &umr_bitfield_default },
+	 { "STATIC_PM_EN", 1, 1, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_DIS", 2, 2, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_TYPE", 3, 3, &umr_bitfield_default },
+	 { "SW_SMIO_INDEX", 6, 6, &umr_bitfield_default },
+	 { "LOW_VOLT_D2_ACPI", 8, 8, &umr_bitfield_default },
+	 { "LOW_VOLT_D3_ACPI", 9, 9, &umr_bitfield_default },
+	 { "VOLT_PWRMGT_EN", 10, 10, &umr_bitfield_default },
+	 { "SPARE11", 11, 11, &umr_bitfield_default },
+	 { "GPU_COUNTER_ACPI", 14, 14, &umr_bitfield_default },
+	 { "GPU_COUNTER_CLK", 15, 15, &umr_bitfield_default },
+	 { "GPU_COUNTER_OFF", 16, 16, &umr_bitfield_default },
+	 { "GPU_COUNTER_INTF_OFF", 17, 17, &umr_bitfield_default },
+	 { "SPARE18", 18, 18, &umr_bitfield_default },
+	 { "ACPI_D3_VID", 19, 20, &umr_bitfield_default },
+	 { "DYN_SPREAD_SPECTRUM_EN", 23, 23, &umr_bitfield_default },
+	 { "SPARE27", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCNB_PWRMGT_CNTL[] = {
+	 { "GNB_SLOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "GNB_SLOW", 2, 2, &umr_bitfield_default },
+	 { "FORCE_NB_PS1", 3, 3, &umr_bitfield_default },
+	 { "DPM_ENABLED", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_PWRMGT_CNTL[] = {
+	 { "SCLK_PWRMGT_OFF", 0, 0, &umr_bitfield_default },
+	 { "SCLK_LOW_D1", 1, 1, &umr_bitfield_default },
+	 { "DYN_PWR_DOWN_EN", 2, 2, &umr_bitfield_default },
+	 { "RESET_BUSY_CNT", 4, 4, &umr_bitfield_default },
+	 { "RESET_SCLK_CNT", 5, 5, &umr_bitfield_default },
+	 { "RESERVED_0", 6, 6, &umr_bitfield_default },
+	 { "DYN_GFX_CLK_OFF_EN", 7, 7, &umr_bitfield_default },
+	 { "GFX_CLK_FORCE_ON", 8, 8, &umr_bitfield_default },
+	 { "GFX_CLK_REQUEST_OFF", 9, 9, &umr_bitfield_default },
+	 { "GFX_CLK_FORCE_OFF", 10, 10, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D1", 11, 11, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D2", 12, 12, &umr_bitfield_default },
+	 { "GFX_CLK_OFF_ACPI_D3", 13, 13, &umr_bitfield_default },
+	 { "DYN_LIGHT_SLEEP_EN", 14, 14, &umr_bitfield_default },
+	 { "AUTO_SCLK_PULSE_SKIP", 15, 15, &umr_bitfield_default },
+	 { "LIGHT_SLEEP_COUNTER", 16, 20, &umr_bitfield_default },
+	 { "DYNAMIC_PM_EN", 21, 21, &umr_bitfield_default },
+	 { "DPM_DYN_PWR_DOWN_CNTL", 22, 22, &umr_bitfield_default },
+	 { "DPM_DYN_PWR_DOWN_EN", 23, 23, &umr_bitfield_default },
+	 { "RESERVED_3", 24, 24, &umr_bitfield_default },
+	 { "VOLTAGE_UPDATE_EN", 25, 25, &umr_bitfield_default },
+	 { "FORCE_PM0_INTERRUPT", 28, 28, &umr_bitfield_default },
+	 { "FORCE_PM1_INTERRUPT", 29, 29, &umr_bitfield_default },
+	 { "GFX_VOLTAGE_CHANGE_EN", 30, 30, &umr_bitfield_default },
+	 { "GFX_VOLTAGE_CHANGE_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX[] = {
+	 { "TARGET_STATE", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_STATE", 4, 7, &umr_bitfield_default },
+	 { "CURR_MCLK_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MCLK_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_SCLK_INDEX", 16, 20, &umr_bitfield_default },
+	 { "TARG_SCLK_INDEX", 21, 25, &umr_bitfield_default },
+	 { "CURR_LCLK_INDEX", 26, 28, &umr_bitfield_default },
+	 { "TARG_LCLK_INDEX", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 3, &umr_bitfield_default },
+	 { "TST_REF_SEL", 4, 7, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 8, 14, &umr_bitfield_default },
+	 { "TST_RESET", 15, 15, &umr_bitfield_default },
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_STATIC_SCREEN_PARAMETER[] = {
+	 { "STATIC_SCREEN_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL[] = {
+	 { "DISP_GAP", 0, 1, &umr_bitfield_default },
+	 { "VBI_TIMER_COUNT", 4, 17, &umr_bitfield_default },
+	 { "VBI_TIMER_UNIT", 20, 22, &umr_bitfield_default },
+	 { "DISP_GAP_MCHG", 24, 25, &umr_bitfield_default },
+	 { "VBI_TIMER_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACPI_CNTL[] = {
+	 { "SCLK_ACPI_DIV", 0, 6, &umr_bitfield_default },
+	 { "SCLK_CHANGE_SKIP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 16, 16, &umr_bitfield_default },
+	 { "SELF_REFRESH_MASK", 17, 17, &umr_bitfield_default },
+	 { "ALLOW_NBPSTATE_MASK", 18, 18, &umr_bitfield_default },
+	 { "BIF_BUSY_MASK", 19, 19, &umr_bitfield_default },
+	 { "UVD_BUSY_MASK", 20, 20, &umr_bitfield_default },
+	 { "MC0SRBM_BUSY_MASK", 21, 21, &umr_bitfield_default },
+	 { "MC1SRBM_BUSY_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_ALLOW_MASK", 23, 23, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 24, 24, &umr_bitfield_default },
+	 { "SELF_REFRESH_NLC_MASK", 25, 25, &umr_bitfield_default },
+	 { "FAST_EXIT_REQ_NBPSTATE", 26, 26, &umr_bitfield_default },
+	 { "DEEP_SLEEP_ENTRY_MODE", 27, 27, &umr_bitfield_default },
+	 { "MBUS2_ACTIVE_MASK", 28, 28, &umr_bitfield_default },
+	 { "VCE_BUSY_MASK", 29, 29, &umr_bitfield_default },
+	 { "AZ_BUSY_MASK", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RLC_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "HDP_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "ROM_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "PDMA_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "IDCT_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "SDMA_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_AZ_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK", 9, 9, &umr_bitfield_default },
+	 { "UVD_CG_MC_STAT_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "VCE_CG_MC_STAT_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "SAM_CG_MC_STAT_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "SAM_CG_STATUS_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 14, 14, &umr_bitfield_default },
+	 { "SHALLOW_DIV_ID", 21, 23, &umr_bitfield_default },
+	 { "INOUT_CUSHION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_MISC_CNTL[] = {
+	 { "DPM_DS_DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "DPM_SS_DIV_ID", 3, 5, &umr_bitfield_default },
+	 { "OCP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OCP_DS_DIV_ID", 17, 19, &umr_bitfield_default },
+	 { "OCP_SS_DIV_ID", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL3[] = {
+	 { "GRBM_0_SMU_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRBM_1_SMU_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "GRBM_2_SMU_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "GRBM_3_SMU_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "GRBM_4_SMU_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "GRBM_5_SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "GRBM_6_SMU_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "GRBM_7_SMU_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "GRBM_8_SMU_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "GRBM_9_SMU_BUSY_MASK", 9, 9, &umr_bitfield_default },
+	 { "GRBM_10_SMU_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "GRBM_11_SMU_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "GRBM_12_SMU_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "GRBM_13_SMU_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "GRBM_14_SMU_BUSY_MASK", 14, 14, &umr_bitfield_default },
+	 { "GRBM_15_SMU_BUSY_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_1[] = {
+	 { "CURR_VDDCI_INDEX", 0, 3, &umr_bitfield_default },
+	 { "TARG_VDDCI_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_MVDD_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MVDD_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_VDDC_INDEX", 16, 19, &umr_bitfield_default },
+	 { "TARG_VDDC_INDEX", 20, 23, &umr_bitfield_default },
+	 { "CURR_PCIE_INDEX", 24, 27, &umr_bitfield_default },
+	 { "TARG_PCIE_INDEX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ULV_PARAMETER[] = {
+	 { "ULV_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "ULV_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_0[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_1[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_2[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_3[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_4[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_5[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_6[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
+	 { "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_MIN_DIV[] = {
+	 { "FRACV", 0, 11, &umr_bitfield_default },
+	 { "INTV", 12, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "L1IMU_SMU_IDLE_MASK", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_BIT3", 3, 3, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 4, 4, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE1_MASK", 6, 6, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE2_MASK", 7, 7, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE3_MASK", 8, 8, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE4_MASK", 9, 9, &umr_bitfield_default },
+	 { "L1IMUGPP_IDLE_MASK", 10, 10, &umr_bitfield_default },
+	 { "L1IMUGPPSB_IDLE_MASK", 11, 11, &umr_bitfield_default },
+	 { "L1IMUBIF_IDLE_MASK", 12, 12, &umr_bitfield_default },
+	 { "L1IMUINTGEN_IDLE_MASK", 13, 13, &umr_bitfield_default },
+	 { "L2IMU_IDLE_MASK", 14, 14, &umr_bitfield_default },
+	 { "ORB_IDLE_MASK", 15, 15, &umr_bitfield_default },
+	 { "ON_INB_WAKE_MASK", 16, 16, &umr_bitfield_default },
+	 { "ON_INB_WAKE_ACK_MASK", 17, 17, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_MASK", 18, 18, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_ACK_MASK", 19, 19, &umr_bitfield_default },
+	 { "DMAACTIVE_MASK", 20, 20, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_CTRL[] = {
+	 { "DPM_EVENT_SRC", 0, 2, &umr_bitfield_default },
+	 { "THERM_INC_CLK", 3, 3, &umr_bitfield_default },
+	 { "SPARE", 4, 13, &umr_bitfield_default },
+	 { "DIG_THERM_DPM", 14, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 24, &umr_bitfield_default },
+	 { "CTF_PAD_POLARITY", 25, 25, &umr_bitfield_default },
+	 { "CTF_PAD_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_STATUS[] = {
+	 { "SPARE", 0, 8, &umr_bitfield_default },
+	 { "FDO_PWM_DUTY", 9, 16, &umr_bitfield_default },
+	 { "THERM_ALERT", 17, 17, &umr_bitfield_default },
+	 { "GEN_STATUS", 18, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT[] = {
+	 { "DIG_THERM_CTF", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTH", 8, 15, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 16, 23, &umr_bitfield_default },
+	 { "THERM_INT_MASK", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_CTRL[] = {
+	 { "TS_FILTER", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 7, &umr_bitfield_default },
+	 { "THERMAL_RANGE_RST", 9, 9, &umr_bitfield_default },
+	 { "TEMP_SEL", 20, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_STATUS[] = {
+	 { "ASIC_MAX_TEMP", 0, 8, &umr_bitfield_default },
+	 { "CTF_TEMP", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL0[] = {
+	 { "FDO_STATIC_DUTY", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_DUTY", 8, 15, &umr_bitfield_default },
+	 { "FDO_PWM_MANUAL", 16, 16, &umr_bitfield_default },
+	 { "FDO_PWM_HYSTER", 17, 22, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP_EN", 23, 23, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL1[] = {
+	 { "FMAX_DUTY100", 0, 7, &umr_bitfield_default },
+	 { "FMIN_DUTY", 8, 15, &umr_bitfield_default },
+	 { "M", 16, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 29, &umr_bitfield_default },
+	 { "FDO_PWRDNB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL2[] = {
+	 { "TMIN", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_TIME", 8, 10, &umr_bitfield_default },
+	 { "FDO_PWM_MODE", 11, 13, &umr_bitfield_default },
+	 { "TMIN_HYSTER", 14, 16, &umr_bitfield_default },
+	 { "TMAX", 17, 24, &umr_bitfield_default },
+	 { "TACH_PWM_RESP_RATE", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_CTRL[] = {
+	 { "EDGE_PER_REV", 0, 2, &umr_bitfield_default },
+	 { "TARGET_PERIOD", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_STATUS[] = {
+	 { "TACH_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_THM_STRAPS0[] = {
+	 { "TMON0_BGADJ", 1, 8, &umr_bitfield_default },
+	 { "TMON1_BGADJ", 9, 16, &umr_bitfield_default },
+	 { "TMON_CMON_FUSE_SEL", 17, 17, &umr_bitfield_default },
+	 { "NUM_ACQ", 18, 20, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 21, 23, &umr_bitfield_default },
+	 { "TMON_CONFIG_SOURCE", 24, 24, &umr_bitfield_default },
+	 { "CTF_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "TMON0_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "TMON1_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "TMON2_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "TMON3_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "UNUSED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_CNTL[] = {
+	 { "SX0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SX0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "SX0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "SX0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_OVR_SEL[] = {
+	 { "SX0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_SX0_OVR_VAL[] = {
+	 { "SX0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
+	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
+	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
+	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
+	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC1_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC1_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
+	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
+	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
+	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC2_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC2_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
+	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
+	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
+	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC3_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC3_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
+	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
+	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_CNTL[] = {
+	 { "CPL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CPL_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "CPL_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "CPL_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_SEL[] = {
+	 { "CPL_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_VAL[] = {
+	 { "CPL_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_CNTL[] = {
+	 { "DCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_STATUS[] = {
+	 { "DCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_CNTL[] = {
+	 { "VCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_STATUS[] = {
+	 { "VCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_CNTL[] = {
+	 { "ECLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_STATUS[] = {
+	 { "ECLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACLK_CNTL[] = {
+	 { "ACLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_DFS_BYPASS_CNTL[] = {
+	 { "BYPASSECLK", 0, 0, &umr_bitfield_default },
+	 { "BYPASSLCLK", 1, 1, &umr_bitfield_default },
+	 { "BYPASSEVCLK", 2, 2, &umr_bitfield_default },
+	 { "BYPASSDCLK", 3, 3, &umr_bitfield_default },
+	 { "BYPASSVCLK", 4, 4, &umr_bitfield_default },
+	 { "BYPASSDISPCLK", 5, 5, &umr_bitfield_default },
+	 { "BYPASSDPREFCLK", 6, 6, &umr_bitfield_default },
+	 { "BYPASSACLK", 7, 7, &umr_bitfield_default },
+	 { "BYPASSADIVCLK", 8, 8, &umr_bitfield_default },
+	 { "BYPASSPSPCLK", 9, 9, &umr_bitfield_default },
+	 { "BYPASSSAMCLK", 10, 10, &umr_bitfield_default },
+	 { "BYPASSSCLK", 11, 11, &umr_bitfield_default },
+	 { "USE_SPLL_BYPASS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL[] = {
+	 { "SPLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "SPLL_PWRON", 1, 1, &umr_bitfield_default },
+	 { "SPLL_DIVEN", 2, 2, &umr_bitfield_default },
+	 { "SPLL_BYPASS_EN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_BYPASS_THRU_DFS", 4, 4, &umr_bitfield_default },
+	 { "SPLL_REF_DIV", 5, 10, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_EN", 12, 12, &umr_bitfield_default },
+	 { "SPLL_PDIV_A", 20, 26, &umr_bitfield_default },
+	 { "SPLL_DIVA_ACK", 27, 27, &umr_bitfield_default },
+	 { "SPLL_OTEST_LOCK_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_2[] = {
+	 { "SCLK_MUX_SEL", 0, 8, &umr_bitfield_default },
+	 { "SPLL_CTLREQ", 11, 11, &umr_bitfield_default },
+	 { "SPLL_BYPASS_CHG", 22, 22, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_CHG", 23, 23, &umr_bitfield_default },
+	 { "SPLL_RESET_CHG", 24, 24, &umr_bitfield_default },
+	 { "SPLL_BABY_STEP_CHG", 25, 25, &umr_bitfield_default },
+	 { "SCLK_MUX_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "SPLL_UNLOCK_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "SPLL_CLKF_UPDATE", 28, 28, &umr_bitfield_default },
+	 { "SPLL_TEST_UNLOCK_CLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_3[] = {
+	 { "SPLL_FB_DIV", 0, 25, &umr_bitfield_default },
+	 { "SPLL_DITHEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_4[] = {
+	 { "SPLL_SCLK_TEST_SEL", 0, 3, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT_SEL", 5, 6, &umr_bitfield_default },
+	 { "SPLL_SCLK_EN", 7, 8, &umr_bitfield_default },
+	 { "SPLL_SPARE", 9, 18, &umr_bitfield_default },
+	 { "TEST_FRAC_BYPASS", 21, 21, &umr_bitfield_default },
+	 { "SPLL_ILOCK", 23, 23, &umr_bitfield_default },
+	 { "SPLL_FBCLK_SEL", 24, 24, &umr_bitfield_default },
+	 { "SPLL_VCTRLADC_EN", 25, 25, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT", 26, 27, &umr_bitfield_default },
+	 { "SPLL_SPARE_EXT", 28, 30, &umr_bitfield_default },
+	 { "SPLL_VTOI_BIAS_CNTL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_5[] = {
+	 { "FBDIV_SSC_BYPASS", 0, 0, &umr_bitfield_default },
+	 { "RISEFBVCO_EN", 1, 1, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 2, 3, &umr_bitfield_default },
+	 { "RESET_TIMER", 4, 5, &umr_bitfield_default },
+	 { "FAST_LOCK_CNTRL", 6, 7, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 8, 8, &umr_bitfield_default },
+	 { "RESET_ANTI_MUX", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_6[] = {
+	 { "SCLKMUX0_CLKOFF_CNT", 0, 7, &umr_bitfield_default },
+	 { "SCLKMUX1_CLKOFF_CNT", 8, 15, &umr_bitfield_default },
+	 { "SPLL_VCTL_EN", 16, 16, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_IN", 17, 20, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_OUT", 21, 24, &umr_bitfield_default },
+	 { "SPLL_LF_CNTR", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_7[] = {
+	 { "SPLL_BW_CNTRL", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPLL_CNTL_MODE[] = {
+	 { "SPLL_SW_DIR_CONTROL", 0, 0, &umr_bitfield_default },
+	 { "SPLL_LEGACY_PDIV", 1, 1, &umr_bitfield_default },
+	 { "SPLL_TEST", 2, 2, &umr_bitfield_default },
+	 { "SPLL_FASTEN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_ENSAT", 4, 4, &umr_bitfield_default },
+	 { "SPLL_TEST_CLK_EXT_DIV", 10, 11, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_DLY_CNT", 12, 19, &umr_bitfield_default },
+	 { "SPLL_RESET_EN", 28, 28, &umr_bitfield_default },
+	 { "SPLL_VCO_MODE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM[] = {
+	 { "SSEN", 0, 0, &umr_bitfield_default },
+	 { "CLKS", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM_2[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMPLL_BYPASSCLK_SEL[] = {
+	 { "MPLL_CLKOUT_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL[] = {
+	 { "XTALIN_DIVIDE", 1, 1, &umr_bitfield_default },
+	 { "BCLK_AS_XCLK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_2[] = {
+	 { "ENABLE_XCLK", 0, 0, &umr_bitfield_default },
+	 { "FORCE_BIF_REFCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "MUX_TCLK_TO_XCLK", 8, 8, &umr_bitfield_default },
+	 { "XO_IN_OSCIN_EN", 14, 14, &umr_bitfield_default },
+	 { "XO_IN_ICORE_CLK_OE", 15, 15, &umr_bitfield_default },
+	 { "XO_IN_CML_RXEN", 16, 16, &umr_bitfield_default },
+	 { "XO_IN_BIDIR_CML_OE", 17, 17, &umr_bitfield_default },
+	 { "XO_IN2_OSCIN_EN", 18, 18, &umr_bitfield_default },
+	 { "XO_IN2_ICORE_CLK_OE", 19, 19, &umr_bitfield_default },
+	 { "XO_IN2_CML_RXEN", 20, 20, &umr_bitfield_default },
+	 { "XO_IN2_BIDIR_CML_OE", 21, 21, &umr_bitfield_default },
+	 { "CML_CTRL", 22, 23, &umr_bitfield_default },
+	 { "CLK_SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_CLK_CNTL[] = {
+	 { "CMON_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "CTF_CLK_SHUTOFF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_CLK_CTRL[] = {
+	 { "DEEP_SLEEP_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "ZCLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "DFT_SMS_PG_CLK_SEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 4, &umr_bitfield_default },
+	 { "TST_REF_SEL", 5, 9, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 10, 16, &umr_bitfield_default },
+	 { "TST_RESET", 17, 17, &umr_bitfield_default },
+	 { "TST_CLK_SEL_MODE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL_2[] = {
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_ADFS_CLK_BYPASS_CNTL1[] = {
+	 { "ECLK_BYPASS_CNTL", 0, 2, &umr_bitfield_default },
+	 { "SCLK_BYPASS_CNTL", 3, 5, &umr_bitfield_default },
+	 { "LCLK_BYPASS_CNTL", 6, 8, &umr_bitfield_default },
+	 { "DCLK_BYPASS_CNTL", 9, 11, &umr_bitfield_default },
+	 { "VCLK_BYPASS_CNTL", 12, 14, &umr_bitfield_default },
+	 { "DISPCLK_BYPASS_CNTL", 15, 17, &umr_bitfield_default },
+	 { "DRREFCLK_BYPASS_CNTL", 18, 20, &umr_bitfield_default },
+	 { "ACLK_BYPASS_CNTL", 21, 23, &umr_bitfield_default },
+	 { "SAMCLK_BYPASS_CNTL", 24, 26, &umr_bitfield_default },
+	 { "ACLK_DIV_BYPASS_CNTL", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_DC[] = {
+	 { "OSC_EN", 0, 0, &umr_bitfield_default },
+	 { "XTL_LOW_GAIN", 1, 2, &umr_bitfield_default },
+	 { "XTALIN_SEL", 10, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_CNTL[] = {
+	 { "SCK_OVERWRITE", 1, 1, &umr_bitfield_default },
+	 { "CLOCK_GATING_EN", 2, 2, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_SETUP_TIME", 8, 15, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_HOLD_TIME", 16, 23, &umr_bitfield_default },
+	 { "SCK_PRESCALE_REFCLK", 24, 27, &umr_bitfield_default },
+	 { "SCK_PRESCALE_CRYSTAL_CLK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPAGE_MIRROR_CNTL[] = {
+	 { "PAGE_MIRROR_BASE_ADDR", 0, 23, &umr_bitfield_default },
+	 { "PAGE_MIRROR_INVALIDATE", 24, 24, &umr_bitfield_default },
+	 { "PAGE_MIRROR_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "PAGE_MIRROR_USAGE", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_STATUS[] = {
+	 { "ROM_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCGTT_ROM_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_INDEX[] = {
+	 { "ROM_INDEX", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_DATA[] = {
+	 { "ROM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_START[] = {
+	 { "ROM_START", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_CNTL[] = {
+	 { "DATA_SIZE", 0, 15, &umr_bitfield_default },
+	 { "COMMAND_SIZE", 16, 17, &umr_bitfield_default },
+	 { "ROM_SW_RETURN_DATA_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_STATUS[] = {
+	 { "ROM_SW_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_COMMAND[] = {
+	 { "ROM_SW_INSTRUCTION", 0, 7, &umr_bitfield_default },
+	 { "ROM_SW_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_1[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_2[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_3[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_4[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_5[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_6[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_7[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_8[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_9[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_10[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_11[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_12[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_13[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_14[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_15[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_16[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_17[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_18[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_19[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_20[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_21[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_22[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_23[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_24[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_25[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_26[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_27[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_28[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_29[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_30[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_31[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_32[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_33[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_34[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_35[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_36[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_37[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_38[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_39[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_40[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_41[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_42[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_43[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_44[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_45[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_46[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_47[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_48[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_49[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_50[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_51[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_52[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_53[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_54[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_55[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_56[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_57[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_58[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_59[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_60[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_61[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_62[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_63[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_64[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_ENA[] = {
+	 { "THERM_INTH_SET", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_SET", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_SET", 2, 2, &umr_bitfield_default },
+	 { "THERM_INTH_CLR", 3, 3, &umr_bitfield_default },
+	 { "THERM_INTL_CLR", 4, 4, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CLR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_CTRL[] = {
+	 { "DIG_THERM_INTH", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 8, 15, &umr_bitfield_default },
+	 { "GNB_TEMP_THRESHOLD", 16, 23, &umr_bitfield_default },
+	 { "THERM_INTH_MASK", 24, 24, &umr_bitfield_default },
+	 { "THERM_INTL_MASK", 25, 25, &umr_bitfield_default },
+	 { "THERM_TRIGGER_MASK", 26, 26, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_MASK", 27, 27, &umr_bitfield_default },
+	 { "THERM_GNB_HW_ENA", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_STATUS[] = {
+	 { "THERM_INTH_DETECT", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_DETECT", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_DETECT", 2, 2, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_DETECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MAIN_PLL_OP_FREQ[] = {
+	 { "PLL_OP_FREQ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_STATUS[] = {
+	 { "SMU_DONE", 0, 0, &umr_bitfield_default },
+	 { "SMU_PASS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_FIRMWARE[] = {
+	 { "SMU_IN_PROG", 0, 0, &umr_bitfield_default },
+	 { "SMU_RD_DONE", 1, 2, &umr_bitfield_default },
+	 { "SMU_SRAM_RD_BLOCK_EN", 3, 3, &umr_bitfield_default },
+	 { "SMU_SRAM_WR_BLOCK_EN", 4, 4, &umr_bitfield_default },
+	 { "SMU_counter", 8, 11, &umr_bitfield_default },
+	 { "SMU_MODE", 16, 16, &umr_bitfield_default },
+	 { "SMU_SEL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_INPUT_DATA[] = {
+	 { "START_ADDR", 0, 30, &umr_bitfield_default },
+	 { "AUTO_START", 31, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/smu710_regs.i b/src/lib/ip/smu710_regs.i
new file mode 100644
index 0000000..b0ba5dc
--- /dev/null
+++ b/src/lib/ip/smu710_regs.i
@@ -0,0 +1,1296 @@
+	{ "mmGPIOPAD_SW_INT_STAT", REG_MMIO, 0x180, &mmGPIOPAD_SW_INT_STAT[0], sizeof(mmGPIOPAD_SW_INT_STAT)/sizeof(mmGPIOPAD_SW_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_STRENGTH", REG_MMIO, 0x181, &mmGPIOPAD_STRENGTH[0], sizeof(mmGPIOPAD_STRENGTH)/sizeof(mmGPIOPAD_STRENGTH[0]), 0, 0 },
+	{ "mmGPIOPAD_MASK", REG_MMIO, 0x182, &mmGPIOPAD_MASK[0], sizeof(mmGPIOPAD_MASK)/sizeof(mmGPIOPAD_MASK[0]), 0, 0 },
+	{ "mmGPIOPAD_A", REG_MMIO, 0x183, &mmGPIOPAD_A[0], sizeof(mmGPIOPAD_A)/sizeof(mmGPIOPAD_A[0]), 0, 0 },
+	{ "mmGPIOPAD_EN", REG_MMIO, 0x184, &mmGPIOPAD_EN[0], sizeof(mmGPIOPAD_EN)/sizeof(mmGPIOPAD_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_Y", REG_MMIO, 0x185, &mmGPIOPAD_Y[0], sizeof(mmGPIOPAD_Y)/sizeof(mmGPIOPAD_Y[0]), 0, 0 },
+	{ "mmGPIOPAD_PINSTRAPS", REG_MMIO, 0x186, &mmGPIOPAD_PINSTRAPS[0], sizeof(mmGPIOPAD_PINSTRAPS)/sizeof(mmGPIOPAD_PINSTRAPS[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_EN", REG_MMIO, 0x187, &mmGPIOPAD_INT_STAT_EN[0], sizeof(mmGPIOPAD_INT_STAT_EN)/sizeof(mmGPIOPAD_INT_STAT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT", REG_MMIO, 0x188, &mmGPIOPAD_INT_STAT[0], sizeof(mmGPIOPAD_INT_STAT)/sizeof(mmGPIOPAD_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_AK", REG_MMIO, 0x189, &mmGPIOPAD_INT_STAT_AK[0], sizeof(mmGPIOPAD_INT_STAT_AK)/sizeof(mmGPIOPAD_INT_STAT_AK[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_EN", REG_MMIO, 0x18a, &mmGPIOPAD_INT_EN[0], sizeof(mmGPIOPAD_INT_EN)/sizeof(mmGPIOPAD_INT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_TYPE", REG_MMIO, 0x18b, &mmGPIOPAD_INT_TYPE[0], sizeof(mmGPIOPAD_INT_TYPE)/sizeof(mmGPIOPAD_INT_TYPE[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_POLARITY", REG_MMIO, 0x18c, &mmGPIOPAD_INT_POLARITY[0], sizeof(mmGPIOPAD_INT_POLARITY)/sizeof(mmGPIOPAD_INT_POLARITY[0]), 0, 0 },
+	{ "mmGPIOPAD_EXTERN_TRIG_CNTL", REG_MMIO, 0x18d, &mmGPIOPAD_EXTERN_TRIG_CNTL[0], sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL)/sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL[0]), 0, 0 },
+	{ "mmGPIOPAD_RCVR_SEL", REG_MMIO, 0x191, &mmGPIOPAD_RCVR_SEL[0], sizeof(mmGPIOPAD_RCVR_SEL)/sizeof(mmGPIOPAD_RCVR_SEL[0]), 0, 0 },
+	{ "mmGPIOPAD_PU_EN", REG_MMIO, 0x192, &mmGPIOPAD_PU_EN[0], sizeof(mmGPIOPAD_PU_EN)/sizeof(mmGPIOPAD_PU_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_PD_EN", REG_MMIO, 0x193, &mmGPIOPAD_PD_EN[0], sizeof(mmGPIOPAD_PD_EN)/sizeof(mmGPIOPAD_PD_EN[0]), 0, 0 },
+	{ "mmCG_FPS_CNT", REG_MMIO, 0x1a4, &mmCG_FPS_CNT[0], sizeof(mmCG_FPS_CNT)/sizeof(mmCG_FPS_CNT[0]), 0, 0 },
+	{ "ixDPM_TABLE_1", REG_SMC, 0x3f000, &ixDPM_TABLE_1[0], sizeof(ixDPM_TABLE_1)/sizeof(ixDPM_TABLE_1[0]), 0, 0 },
+	{ "ixDPM_TABLE_2", REG_SMC, 0x3f004, &ixDPM_TABLE_2[0], sizeof(ixDPM_TABLE_2)/sizeof(ixDPM_TABLE_2[0]), 0, 0 },
+	{ "ixDPM_TABLE_3", REG_SMC, 0x3f008, &ixDPM_TABLE_3[0], sizeof(ixDPM_TABLE_3)/sizeof(ixDPM_TABLE_3[0]), 0, 0 },
+	{ "ixDPM_TABLE_4", REG_SMC, 0x3f00c, &ixDPM_TABLE_4[0], sizeof(ixDPM_TABLE_4)/sizeof(ixDPM_TABLE_4[0]), 0, 0 },
+	{ "ixDPM_TABLE_5", REG_SMC, 0x3f010, &ixDPM_TABLE_5[0], sizeof(ixDPM_TABLE_5)/sizeof(ixDPM_TABLE_5[0]), 0, 0 },
+	{ "ixDPM_TABLE_6", REG_SMC, 0x3f014, &ixDPM_TABLE_6[0], sizeof(ixDPM_TABLE_6)/sizeof(ixDPM_TABLE_6[0]), 0, 0 },
+	{ "ixDPM_TABLE_7", REG_SMC, 0x3f018, &ixDPM_TABLE_7[0], sizeof(ixDPM_TABLE_7)/sizeof(ixDPM_TABLE_7[0]), 0, 0 },
+	{ "ixDPM_TABLE_8", REG_SMC, 0x3f01c, &ixDPM_TABLE_8[0], sizeof(ixDPM_TABLE_8)/sizeof(ixDPM_TABLE_8[0]), 0, 0 },
+	{ "ixDPM_TABLE_9", REG_SMC, 0x3f020, &ixDPM_TABLE_9[0], sizeof(ixDPM_TABLE_9)/sizeof(ixDPM_TABLE_9[0]), 0, 0 },
+	{ "ixDPM_TABLE_10", REG_SMC, 0x3f024, &ixDPM_TABLE_10[0], sizeof(ixDPM_TABLE_10)/sizeof(ixDPM_TABLE_10[0]), 0, 0 },
+	{ "ixDPM_TABLE_11", REG_SMC, 0x3f028, &ixDPM_TABLE_11[0], sizeof(ixDPM_TABLE_11)/sizeof(ixDPM_TABLE_11[0]), 0, 0 },
+	{ "ixDPM_TABLE_12", REG_SMC, 0x3f02c, &ixDPM_TABLE_12[0], sizeof(ixDPM_TABLE_12)/sizeof(ixDPM_TABLE_12[0]), 0, 0 },
+	{ "ixDPM_TABLE_13", REG_SMC, 0x3f030, &ixDPM_TABLE_13[0], sizeof(ixDPM_TABLE_13)/sizeof(ixDPM_TABLE_13[0]), 0, 0 },
+	{ "ixDPM_TABLE_14", REG_SMC, 0x3f034, &ixDPM_TABLE_14[0], sizeof(ixDPM_TABLE_14)/sizeof(ixDPM_TABLE_14[0]), 0, 0 },
+	{ "ixDPM_TABLE_15", REG_SMC, 0x3f038, &ixDPM_TABLE_15[0], sizeof(ixDPM_TABLE_15)/sizeof(ixDPM_TABLE_15[0]), 0, 0 },
+	{ "ixDPM_TABLE_16", REG_SMC, 0x3f03c, &ixDPM_TABLE_16[0], sizeof(ixDPM_TABLE_16)/sizeof(ixDPM_TABLE_16[0]), 0, 0 },
+	{ "ixDPM_TABLE_17", REG_SMC, 0x3f040, &ixDPM_TABLE_17[0], sizeof(ixDPM_TABLE_17)/sizeof(ixDPM_TABLE_17[0]), 0, 0 },
+	{ "ixDPM_TABLE_18", REG_SMC, 0x3f044, &ixDPM_TABLE_18[0], sizeof(ixDPM_TABLE_18)/sizeof(ixDPM_TABLE_18[0]), 0, 0 },
+	{ "ixDPM_TABLE_19", REG_SMC, 0x3f048, &ixDPM_TABLE_19[0], sizeof(ixDPM_TABLE_19)/sizeof(ixDPM_TABLE_19[0]), 0, 0 },
+	{ "ixDPM_TABLE_20", REG_SMC, 0x3f04c, &ixDPM_TABLE_20[0], sizeof(ixDPM_TABLE_20)/sizeof(ixDPM_TABLE_20[0]), 0, 0 },
+	{ "ixDPM_TABLE_21", REG_SMC, 0x3f050, &ixDPM_TABLE_21[0], sizeof(ixDPM_TABLE_21)/sizeof(ixDPM_TABLE_21[0]), 0, 0 },
+	{ "ixDPM_TABLE_22", REG_SMC, 0x3f054, &ixDPM_TABLE_22[0], sizeof(ixDPM_TABLE_22)/sizeof(ixDPM_TABLE_22[0]), 0, 0 },
+	{ "ixDPM_TABLE_23", REG_SMC, 0x3f058, &ixDPM_TABLE_23[0], sizeof(ixDPM_TABLE_23)/sizeof(ixDPM_TABLE_23[0]), 0, 0 },
+	{ "ixDPM_TABLE_24", REG_SMC, 0x3f05c, &ixDPM_TABLE_24[0], sizeof(ixDPM_TABLE_24)/sizeof(ixDPM_TABLE_24[0]), 0, 0 },
+	{ "ixDPM_TABLE_25", REG_SMC, 0x3f060, &ixDPM_TABLE_25[0], sizeof(ixDPM_TABLE_25)/sizeof(ixDPM_TABLE_25[0]), 0, 0 },
+	{ "ixDPM_TABLE_26", REG_SMC, 0x3f064, &ixDPM_TABLE_26[0], sizeof(ixDPM_TABLE_26)/sizeof(ixDPM_TABLE_26[0]), 0, 0 },
+	{ "ixDPM_TABLE_27", REG_SMC, 0x3f068, &ixDPM_TABLE_27[0], sizeof(ixDPM_TABLE_27)/sizeof(ixDPM_TABLE_27[0]), 0, 0 },
+	{ "ixDPM_TABLE_28", REG_SMC, 0x3f06c, &ixDPM_TABLE_28[0], sizeof(ixDPM_TABLE_28)/sizeof(ixDPM_TABLE_28[0]), 0, 0 },
+	{ "ixDPM_TABLE_29", REG_SMC, 0x3f070, &ixDPM_TABLE_29[0], sizeof(ixDPM_TABLE_29)/sizeof(ixDPM_TABLE_29[0]), 0, 0 },
+	{ "ixDPM_TABLE_30", REG_SMC, 0x3f074, &ixDPM_TABLE_30[0], sizeof(ixDPM_TABLE_30)/sizeof(ixDPM_TABLE_30[0]), 0, 0 },
+	{ "ixDPM_TABLE_31", REG_SMC, 0x3f078, &ixDPM_TABLE_31[0], sizeof(ixDPM_TABLE_31)/sizeof(ixDPM_TABLE_31[0]), 0, 0 },
+	{ "ixDPM_TABLE_32", REG_SMC, 0x3f07c, &ixDPM_TABLE_32[0], sizeof(ixDPM_TABLE_32)/sizeof(ixDPM_TABLE_32[0]), 0, 0 },
+	{ "ixDPM_TABLE_33", REG_SMC, 0x3f080, &ixDPM_TABLE_33[0], sizeof(ixDPM_TABLE_33)/sizeof(ixDPM_TABLE_33[0]), 0, 0 },
+	{ "ixDPM_TABLE_34", REG_SMC, 0x3f084, &ixDPM_TABLE_34[0], sizeof(ixDPM_TABLE_34)/sizeof(ixDPM_TABLE_34[0]), 0, 0 },
+	{ "ixDPM_TABLE_35", REG_SMC, 0x3f088, &ixDPM_TABLE_35[0], sizeof(ixDPM_TABLE_35)/sizeof(ixDPM_TABLE_35[0]), 0, 0 },
+	{ "ixDPM_TABLE_36", REG_SMC, 0x3f08c, &ixDPM_TABLE_36[0], sizeof(ixDPM_TABLE_36)/sizeof(ixDPM_TABLE_36[0]), 0, 0 },
+	{ "ixDPM_TABLE_37", REG_SMC, 0x3f090, &ixDPM_TABLE_37[0], sizeof(ixDPM_TABLE_37)/sizeof(ixDPM_TABLE_37[0]), 0, 0 },
+	{ "ixDPM_TABLE_38", REG_SMC, 0x3f094, &ixDPM_TABLE_38[0], sizeof(ixDPM_TABLE_38)/sizeof(ixDPM_TABLE_38[0]), 0, 0 },
+	{ "ixDPM_TABLE_39", REG_SMC, 0x3f098, &ixDPM_TABLE_39[0], sizeof(ixDPM_TABLE_39)/sizeof(ixDPM_TABLE_39[0]), 0, 0 },
+	{ "ixDPM_TABLE_40", REG_SMC, 0x3f09c, &ixDPM_TABLE_40[0], sizeof(ixDPM_TABLE_40)/sizeof(ixDPM_TABLE_40[0]), 0, 0 },
+	{ "ixDPM_TABLE_41", REG_SMC, 0x3f0a0, &ixDPM_TABLE_41[0], sizeof(ixDPM_TABLE_41)/sizeof(ixDPM_TABLE_41[0]), 0, 0 },
+	{ "ixDPM_TABLE_42", REG_SMC, 0x3f0a4, &ixDPM_TABLE_42[0], sizeof(ixDPM_TABLE_42)/sizeof(ixDPM_TABLE_42[0]), 0, 0 },
+	{ "ixDPM_TABLE_43", REG_SMC, 0x3f0a8, &ixDPM_TABLE_43[0], sizeof(ixDPM_TABLE_43)/sizeof(ixDPM_TABLE_43[0]), 0, 0 },
+	{ "ixDPM_TABLE_44", REG_SMC, 0x3f0ac, &ixDPM_TABLE_44[0], sizeof(ixDPM_TABLE_44)/sizeof(ixDPM_TABLE_44[0]), 0, 0 },
+	{ "ixDPM_TABLE_45", REG_SMC, 0x3f0b0, &ixDPM_TABLE_45[0], sizeof(ixDPM_TABLE_45)/sizeof(ixDPM_TABLE_45[0]), 0, 0 },
+	{ "ixDPM_TABLE_46", REG_SMC, 0x3f0b4, &ixDPM_TABLE_46[0], sizeof(ixDPM_TABLE_46)/sizeof(ixDPM_TABLE_46[0]), 0, 0 },
+	{ "ixDPM_TABLE_47", REG_SMC, 0x3f0b8, &ixDPM_TABLE_47[0], sizeof(ixDPM_TABLE_47)/sizeof(ixDPM_TABLE_47[0]), 0, 0 },
+	{ "ixDPM_TABLE_48", REG_SMC, 0x3f0bc, &ixDPM_TABLE_48[0], sizeof(ixDPM_TABLE_48)/sizeof(ixDPM_TABLE_48[0]), 0, 0 },
+	{ "ixDPM_TABLE_49", REG_SMC, 0x3f0c0, &ixDPM_TABLE_49[0], sizeof(ixDPM_TABLE_49)/sizeof(ixDPM_TABLE_49[0]), 0, 0 },
+	{ "ixDPM_TABLE_50", REG_SMC, 0x3f0c4, &ixDPM_TABLE_50[0], sizeof(ixDPM_TABLE_50)/sizeof(ixDPM_TABLE_50[0]), 0, 0 },
+	{ "ixDPM_TABLE_51", REG_SMC, 0x3f0c8, &ixDPM_TABLE_51[0], sizeof(ixDPM_TABLE_51)/sizeof(ixDPM_TABLE_51[0]), 0, 0 },
+	{ "ixDPM_TABLE_52", REG_SMC, 0x3f0cc, &ixDPM_TABLE_52[0], sizeof(ixDPM_TABLE_52)/sizeof(ixDPM_TABLE_52[0]), 0, 0 },
+	{ "ixDPM_TABLE_53", REG_SMC, 0x3f0d0, &ixDPM_TABLE_53[0], sizeof(ixDPM_TABLE_53)/sizeof(ixDPM_TABLE_53[0]), 0, 0 },
+	{ "ixDPM_TABLE_54", REG_SMC, 0x3f0d4, &ixDPM_TABLE_54[0], sizeof(ixDPM_TABLE_54)/sizeof(ixDPM_TABLE_54[0]), 0, 0 },
+	{ "ixDPM_TABLE_55", REG_SMC, 0x3f0d8, &ixDPM_TABLE_55[0], sizeof(ixDPM_TABLE_55)/sizeof(ixDPM_TABLE_55[0]), 0, 0 },
+	{ "ixDPM_TABLE_56", REG_SMC, 0x3f0dc, &ixDPM_TABLE_56[0], sizeof(ixDPM_TABLE_56)/sizeof(ixDPM_TABLE_56[0]), 0, 0 },
+	{ "ixDPM_TABLE_57", REG_SMC, 0x3f0e0, &ixDPM_TABLE_57[0], sizeof(ixDPM_TABLE_57)/sizeof(ixDPM_TABLE_57[0]), 0, 0 },
+	{ "ixDPM_TABLE_58", REG_SMC, 0x3f0e4, &ixDPM_TABLE_58[0], sizeof(ixDPM_TABLE_58)/sizeof(ixDPM_TABLE_58[0]), 0, 0 },
+	{ "ixDPM_TABLE_59", REG_SMC, 0x3f0e8, &ixDPM_TABLE_59[0], sizeof(ixDPM_TABLE_59)/sizeof(ixDPM_TABLE_59[0]), 0, 0 },
+	{ "ixDPM_TABLE_60", REG_SMC, 0x3f0ec, &ixDPM_TABLE_60[0], sizeof(ixDPM_TABLE_60)/sizeof(ixDPM_TABLE_60[0]), 0, 0 },
+	{ "ixDPM_TABLE_61", REG_SMC, 0x3f0f0, &ixDPM_TABLE_61[0], sizeof(ixDPM_TABLE_61)/sizeof(ixDPM_TABLE_61[0]), 0, 0 },
+	{ "ixDPM_TABLE_62", REG_SMC, 0x3f0f4, &ixDPM_TABLE_62[0], sizeof(ixDPM_TABLE_62)/sizeof(ixDPM_TABLE_62[0]), 0, 0 },
+	{ "ixDPM_TABLE_63", REG_SMC, 0x3f0f8, &ixDPM_TABLE_63[0], sizeof(ixDPM_TABLE_63)/sizeof(ixDPM_TABLE_63[0]), 0, 0 },
+	{ "ixDPM_TABLE_64", REG_SMC, 0x3f0fc, &ixDPM_TABLE_64[0], sizeof(ixDPM_TABLE_64)/sizeof(ixDPM_TABLE_64[0]), 0, 0 },
+	{ "ixDPM_TABLE_65", REG_SMC, 0x3f100, &ixDPM_TABLE_65[0], sizeof(ixDPM_TABLE_65)/sizeof(ixDPM_TABLE_65[0]), 0, 0 },
+	{ "ixDPM_TABLE_66", REG_SMC, 0x3f104, &ixDPM_TABLE_66[0], sizeof(ixDPM_TABLE_66)/sizeof(ixDPM_TABLE_66[0]), 0, 0 },
+	{ "ixDPM_TABLE_67", REG_SMC, 0x3f108, &ixDPM_TABLE_67[0], sizeof(ixDPM_TABLE_67)/sizeof(ixDPM_TABLE_67[0]), 0, 0 },
+	{ "ixDPM_TABLE_68", REG_SMC, 0x3f10c, &ixDPM_TABLE_68[0], sizeof(ixDPM_TABLE_68)/sizeof(ixDPM_TABLE_68[0]), 0, 0 },
+	{ "ixDPM_TABLE_69", REG_SMC, 0x3f110, &ixDPM_TABLE_69[0], sizeof(ixDPM_TABLE_69)/sizeof(ixDPM_TABLE_69[0]), 0, 0 },
+	{ "ixDPM_TABLE_70", REG_SMC, 0x3f114, &ixDPM_TABLE_70[0], sizeof(ixDPM_TABLE_70)/sizeof(ixDPM_TABLE_70[0]), 0, 0 },
+	{ "ixDPM_TABLE_71", REG_SMC, 0x3f118, &ixDPM_TABLE_71[0], sizeof(ixDPM_TABLE_71)/sizeof(ixDPM_TABLE_71[0]), 0, 0 },
+	{ "ixDPM_TABLE_72", REG_SMC, 0x3f11c, &ixDPM_TABLE_72[0], sizeof(ixDPM_TABLE_72)/sizeof(ixDPM_TABLE_72[0]), 0, 0 },
+	{ "ixDPM_TABLE_73", REG_SMC, 0x3f120, &ixDPM_TABLE_73[0], sizeof(ixDPM_TABLE_73)/sizeof(ixDPM_TABLE_73[0]), 0, 0 },
+	{ "ixDPM_TABLE_74", REG_SMC, 0x3f124, &ixDPM_TABLE_74[0], sizeof(ixDPM_TABLE_74)/sizeof(ixDPM_TABLE_74[0]), 0, 0 },
+	{ "ixDPM_TABLE_75", REG_SMC, 0x3f128, &ixDPM_TABLE_75[0], sizeof(ixDPM_TABLE_75)/sizeof(ixDPM_TABLE_75[0]), 0, 0 },
+	{ "ixDPM_TABLE_76", REG_SMC, 0x3f12c, &ixDPM_TABLE_76[0], sizeof(ixDPM_TABLE_76)/sizeof(ixDPM_TABLE_76[0]), 0, 0 },
+	{ "ixDPM_TABLE_77", REG_SMC, 0x3f130, &ixDPM_TABLE_77[0], sizeof(ixDPM_TABLE_77)/sizeof(ixDPM_TABLE_77[0]), 0, 0 },
+	{ "ixDPM_TABLE_78", REG_SMC, 0x3f134, &ixDPM_TABLE_78[0], sizeof(ixDPM_TABLE_78)/sizeof(ixDPM_TABLE_78[0]), 0, 0 },
+	{ "ixDPM_TABLE_79", REG_SMC, 0x3f138, &ixDPM_TABLE_79[0], sizeof(ixDPM_TABLE_79)/sizeof(ixDPM_TABLE_79[0]), 0, 0 },
+	{ "ixDPM_TABLE_80", REG_SMC, 0x3f13c, &ixDPM_TABLE_80[0], sizeof(ixDPM_TABLE_80)/sizeof(ixDPM_TABLE_80[0]), 0, 0 },
+	{ "ixDPM_TABLE_81", REG_SMC, 0x3f140, &ixDPM_TABLE_81[0], sizeof(ixDPM_TABLE_81)/sizeof(ixDPM_TABLE_81[0]), 0, 0 },
+	{ "ixDPM_TABLE_82", REG_SMC, 0x3f144, &ixDPM_TABLE_82[0], sizeof(ixDPM_TABLE_82)/sizeof(ixDPM_TABLE_82[0]), 0, 0 },
+	{ "ixDPM_TABLE_83", REG_SMC, 0x3f148, &ixDPM_TABLE_83[0], sizeof(ixDPM_TABLE_83)/sizeof(ixDPM_TABLE_83[0]), 0, 0 },
+	{ "ixDPM_TABLE_84", REG_SMC, 0x3f14c, &ixDPM_TABLE_84[0], sizeof(ixDPM_TABLE_84)/sizeof(ixDPM_TABLE_84[0]), 0, 0 },
+	{ "ixDPM_TABLE_85", REG_SMC, 0x3f150, &ixDPM_TABLE_85[0], sizeof(ixDPM_TABLE_85)/sizeof(ixDPM_TABLE_85[0]), 0, 0 },
+	{ "ixDPM_TABLE_86", REG_SMC, 0x3f154, &ixDPM_TABLE_86[0], sizeof(ixDPM_TABLE_86)/sizeof(ixDPM_TABLE_86[0]), 0, 0 },
+	{ "ixDPM_TABLE_87", REG_SMC, 0x3f158, &ixDPM_TABLE_87[0], sizeof(ixDPM_TABLE_87)/sizeof(ixDPM_TABLE_87[0]), 0, 0 },
+	{ "ixDPM_TABLE_88", REG_SMC, 0x3f15c, &ixDPM_TABLE_88[0], sizeof(ixDPM_TABLE_88)/sizeof(ixDPM_TABLE_88[0]), 0, 0 },
+	{ "ixDPM_TABLE_89", REG_SMC, 0x3f160, &ixDPM_TABLE_89[0], sizeof(ixDPM_TABLE_89)/sizeof(ixDPM_TABLE_89[0]), 0, 0 },
+	{ "ixDPM_TABLE_90", REG_SMC, 0x3f164, &ixDPM_TABLE_90[0], sizeof(ixDPM_TABLE_90)/sizeof(ixDPM_TABLE_90[0]), 0, 0 },
+	{ "ixDPM_TABLE_91", REG_SMC, 0x3f168, &ixDPM_TABLE_91[0], sizeof(ixDPM_TABLE_91)/sizeof(ixDPM_TABLE_91[0]), 0, 0 },
+	{ "ixDPM_TABLE_92", REG_SMC, 0x3f16c, &ixDPM_TABLE_92[0], sizeof(ixDPM_TABLE_92)/sizeof(ixDPM_TABLE_92[0]), 0, 0 },
+	{ "ixDPM_TABLE_93", REG_SMC, 0x3f170, &ixDPM_TABLE_93[0], sizeof(ixDPM_TABLE_93)/sizeof(ixDPM_TABLE_93[0]), 0, 0 },
+	{ "ixDPM_TABLE_94", REG_SMC, 0x3f174, &ixDPM_TABLE_94[0], sizeof(ixDPM_TABLE_94)/sizeof(ixDPM_TABLE_94[0]), 0, 0 },
+	{ "ixDPM_TABLE_95", REG_SMC, 0x3f178, &ixDPM_TABLE_95[0], sizeof(ixDPM_TABLE_95)/sizeof(ixDPM_TABLE_95[0]), 0, 0 },
+	{ "ixDPM_TABLE_96", REG_SMC, 0x3f17c, &ixDPM_TABLE_96[0], sizeof(ixDPM_TABLE_96)/sizeof(ixDPM_TABLE_96[0]), 0, 0 },
+	{ "ixDPM_TABLE_97", REG_SMC, 0x3f180, &ixDPM_TABLE_97[0], sizeof(ixDPM_TABLE_97)/sizeof(ixDPM_TABLE_97[0]), 0, 0 },
+	{ "ixDPM_TABLE_98", REG_SMC, 0x3f184, &ixDPM_TABLE_98[0], sizeof(ixDPM_TABLE_98)/sizeof(ixDPM_TABLE_98[0]), 0, 0 },
+	{ "ixDPM_TABLE_99", REG_SMC, 0x3f188, &ixDPM_TABLE_99[0], sizeof(ixDPM_TABLE_99)/sizeof(ixDPM_TABLE_99[0]), 0, 0 },
+	{ "ixDPM_TABLE_100", REG_SMC, 0x3f18c, &ixDPM_TABLE_100[0], sizeof(ixDPM_TABLE_100)/sizeof(ixDPM_TABLE_100[0]), 0, 0 },
+	{ "ixDPM_TABLE_101", REG_SMC, 0x3f190, &ixDPM_TABLE_101[0], sizeof(ixDPM_TABLE_101)/sizeof(ixDPM_TABLE_101[0]), 0, 0 },
+	{ "ixDPM_TABLE_102", REG_SMC, 0x3f194, &ixDPM_TABLE_102[0], sizeof(ixDPM_TABLE_102)/sizeof(ixDPM_TABLE_102[0]), 0, 0 },
+	{ "ixDPM_TABLE_103", REG_SMC, 0x3f198, &ixDPM_TABLE_103[0], sizeof(ixDPM_TABLE_103)/sizeof(ixDPM_TABLE_103[0]), 0, 0 },
+	{ "ixDPM_TABLE_104", REG_SMC, 0x3f19c, &ixDPM_TABLE_104[0], sizeof(ixDPM_TABLE_104)/sizeof(ixDPM_TABLE_104[0]), 0, 0 },
+	{ "ixDPM_TABLE_105", REG_SMC, 0x3f1a0, &ixDPM_TABLE_105[0], sizeof(ixDPM_TABLE_105)/sizeof(ixDPM_TABLE_105[0]), 0, 0 },
+	{ "ixDPM_TABLE_106", REG_SMC, 0x3f1a4, &ixDPM_TABLE_106[0], sizeof(ixDPM_TABLE_106)/sizeof(ixDPM_TABLE_106[0]), 0, 0 },
+	{ "ixDPM_TABLE_107", REG_SMC, 0x3f1a8, &ixDPM_TABLE_107[0], sizeof(ixDPM_TABLE_107)/sizeof(ixDPM_TABLE_107[0]), 0, 0 },
+	{ "ixDPM_TABLE_108", REG_SMC, 0x3f1ac, &ixDPM_TABLE_108[0], sizeof(ixDPM_TABLE_108)/sizeof(ixDPM_TABLE_108[0]), 0, 0 },
+	{ "ixDPM_TABLE_109", REG_SMC, 0x3f1b0, &ixDPM_TABLE_109[0], sizeof(ixDPM_TABLE_109)/sizeof(ixDPM_TABLE_109[0]), 0, 0 },
+	{ "ixDPM_TABLE_110", REG_SMC, 0x3f1b4, &ixDPM_TABLE_110[0], sizeof(ixDPM_TABLE_110)/sizeof(ixDPM_TABLE_110[0]), 0, 0 },
+	{ "ixDPM_TABLE_111", REG_SMC, 0x3f1b8, &ixDPM_TABLE_111[0], sizeof(ixDPM_TABLE_111)/sizeof(ixDPM_TABLE_111[0]), 0, 0 },
+	{ "ixDPM_TABLE_112", REG_SMC, 0x3f1bc, &ixDPM_TABLE_112[0], sizeof(ixDPM_TABLE_112)/sizeof(ixDPM_TABLE_112[0]), 0, 0 },
+	{ "ixDPM_TABLE_113", REG_SMC, 0x3f1c0, &ixDPM_TABLE_113[0], sizeof(ixDPM_TABLE_113)/sizeof(ixDPM_TABLE_113[0]), 0, 0 },
+	{ "ixDPM_TABLE_114", REG_SMC, 0x3f1c4, &ixDPM_TABLE_114[0], sizeof(ixDPM_TABLE_114)/sizeof(ixDPM_TABLE_114[0]), 0, 0 },
+	{ "ixDPM_TABLE_115", REG_SMC, 0x3f1c8, &ixDPM_TABLE_115[0], sizeof(ixDPM_TABLE_115)/sizeof(ixDPM_TABLE_115[0]), 0, 0 },
+	{ "ixDPM_TABLE_116", REG_SMC, 0x3f1cc, &ixDPM_TABLE_116[0], sizeof(ixDPM_TABLE_116)/sizeof(ixDPM_TABLE_116[0]), 0, 0 },
+	{ "ixDPM_TABLE_117", REG_SMC, 0x3f1d0, &ixDPM_TABLE_117[0], sizeof(ixDPM_TABLE_117)/sizeof(ixDPM_TABLE_117[0]), 0, 0 },
+	{ "ixDPM_TABLE_118", REG_SMC, 0x3f1d4, &ixDPM_TABLE_118[0], sizeof(ixDPM_TABLE_118)/sizeof(ixDPM_TABLE_118[0]), 0, 0 },
+	{ "ixDPM_TABLE_119", REG_SMC, 0x3f1d8, &ixDPM_TABLE_119[0], sizeof(ixDPM_TABLE_119)/sizeof(ixDPM_TABLE_119[0]), 0, 0 },
+	{ "ixDPM_TABLE_120", REG_SMC, 0x3f1dc, &ixDPM_TABLE_120[0], sizeof(ixDPM_TABLE_120)/sizeof(ixDPM_TABLE_120[0]), 0, 0 },
+	{ "ixDPM_TABLE_121", REG_SMC, 0x3f1e0, &ixDPM_TABLE_121[0], sizeof(ixDPM_TABLE_121)/sizeof(ixDPM_TABLE_121[0]), 0, 0 },
+	{ "ixDPM_TABLE_122", REG_SMC, 0x3f1e4, &ixDPM_TABLE_122[0], sizeof(ixDPM_TABLE_122)/sizeof(ixDPM_TABLE_122[0]), 0, 0 },
+	{ "ixDPM_TABLE_123", REG_SMC, 0x3f1e8, &ixDPM_TABLE_123[0], sizeof(ixDPM_TABLE_123)/sizeof(ixDPM_TABLE_123[0]), 0, 0 },
+	{ "ixDPM_TABLE_124", REG_SMC, 0x3f1ec, &ixDPM_TABLE_124[0], sizeof(ixDPM_TABLE_124)/sizeof(ixDPM_TABLE_124[0]), 0, 0 },
+	{ "ixDPM_TABLE_125", REG_SMC, 0x3f1f0, &ixDPM_TABLE_125[0], sizeof(ixDPM_TABLE_125)/sizeof(ixDPM_TABLE_125[0]), 0, 0 },
+	{ "ixDPM_TABLE_126", REG_SMC, 0x3f1f4, &ixDPM_TABLE_126[0], sizeof(ixDPM_TABLE_126)/sizeof(ixDPM_TABLE_126[0]), 0, 0 },
+	{ "ixDPM_TABLE_127", REG_SMC, 0x3f1f8, &ixDPM_TABLE_127[0], sizeof(ixDPM_TABLE_127)/sizeof(ixDPM_TABLE_127[0]), 0, 0 },
+	{ "ixDPM_TABLE_128", REG_SMC, 0x3f1fc, &ixDPM_TABLE_128[0], sizeof(ixDPM_TABLE_128)/sizeof(ixDPM_TABLE_128[0]), 0, 0 },
+	{ "ixDPM_TABLE_129", REG_SMC, 0x3f200, &ixDPM_TABLE_129[0], sizeof(ixDPM_TABLE_129)/sizeof(ixDPM_TABLE_129[0]), 0, 0 },
+	{ "ixDPM_TABLE_130", REG_SMC, 0x3f204, &ixDPM_TABLE_130[0], sizeof(ixDPM_TABLE_130)/sizeof(ixDPM_TABLE_130[0]), 0, 0 },
+	{ "ixDPM_TABLE_131", REG_SMC, 0x3f208, &ixDPM_TABLE_131[0], sizeof(ixDPM_TABLE_131)/sizeof(ixDPM_TABLE_131[0]), 0, 0 },
+	{ "ixDPM_TABLE_132", REG_SMC, 0x3f20c, &ixDPM_TABLE_132[0], sizeof(ixDPM_TABLE_132)/sizeof(ixDPM_TABLE_132[0]), 0, 0 },
+	{ "ixDPM_TABLE_133", REG_SMC, 0x3f210, &ixDPM_TABLE_133[0], sizeof(ixDPM_TABLE_133)/sizeof(ixDPM_TABLE_133[0]), 0, 0 },
+	{ "ixDPM_TABLE_134", REG_SMC, 0x3f214, &ixDPM_TABLE_134[0], sizeof(ixDPM_TABLE_134)/sizeof(ixDPM_TABLE_134[0]), 0, 0 },
+	{ "ixDPM_TABLE_135", REG_SMC, 0x3f218, &ixDPM_TABLE_135[0], sizeof(ixDPM_TABLE_135)/sizeof(ixDPM_TABLE_135[0]), 0, 0 },
+	{ "ixDPM_TABLE_136", REG_SMC, 0x3f21c, &ixDPM_TABLE_136[0], sizeof(ixDPM_TABLE_136)/sizeof(ixDPM_TABLE_136[0]), 0, 0 },
+	{ "ixDPM_TABLE_137", REG_SMC, 0x3f220, &ixDPM_TABLE_137[0], sizeof(ixDPM_TABLE_137)/sizeof(ixDPM_TABLE_137[0]), 0, 0 },
+	{ "ixDPM_TABLE_138", REG_SMC, 0x3f224, &ixDPM_TABLE_138[0], sizeof(ixDPM_TABLE_138)/sizeof(ixDPM_TABLE_138[0]), 0, 0 },
+	{ "ixDPM_TABLE_139", REG_SMC, 0x3f228, &ixDPM_TABLE_139[0], sizeof(ixDPM_TABLE_139)/sizeof(ixDPM_TABLE_139[0]), 0, 0 },
+	{ "ixDPM_TABLE_140", REG_SMC, 0x3f22c, &ixDPM_TABLE_140[0], sizeof(ixDPM_TABLE_140)/sizeof(ixDPM_TABLE_140[0]), 0, 0 },
+	{ "ixDPM_TABLE_141", REG_SMC, 0x3f230, &ixDPM_TABLE_141[0], sizeof(ixDPM_TABLE_141)/sizeof(ixDPM_TABLE_141[0]), 0, 0 },
+	{ "ixDPM_TABLE_142", REG_SMC, 0x3f234, &ixDPM_TABLE_142[0], sizeof(ixDPM_TABLE_142)/sizeof(ixDPM_TABLE_142[0]), 0, 0 },
+	{ "ixDPM_TABLE_143", REG_SMC, 0x3f238, &ixDPM_TABLE_143[0], sizeof(ixDPM_TABLE_143)/sizeof(ixDPM_TABLE_143[0]), 0, 0 },
+	{ "ixDPM_TABLE_144", REG_SMC, 0x3f23c, &ixDPM_TABLE_144[0], sizeof(ixDPM_TABLE_144)/sizeof(ixDPM_TABLE_144[0]), 0, 0 },
+	{ "ixDPM_TABLE_145", REG_SMC, 0x3f240, &ixDPM_TABLE_145[0], sizeof(ixDPM_TABLE_145)/sizeof(ixDPM_TABLE_145[0]), 0, 0 },
+	{ "ixDPM_TABLE_146", REG_SMC, 0x3f244, &ixDPM_TABLE_146[0], sizeof(ixDPM_TABLE_146)/sizeof(ixDPM_TABLE_146[0]), 0, 0 },
+	{ "ixDPM_TABLE_147", REG_SMC, 0x3f248, &ixDPM_TABLE_147[0], sizeof(ixDPM_TABLE_147)/sizeof(ixDPM_TABLE_147[0]), 0, 0 },
+	{ "ixDPM_TABLE_148", REG_SMC, 0x3f24c, &ixDPM_TABLE_148[0], sizeof(ixDPM_TABLE_148)/sizeof(ixDPM_TABLE_148[0]), 0, 0 },
+	{ "ixDPM_TABLE_149", REG_SMC, 0x3f250, &ixDPM_TABLE_149[0], sizeof(ixDPM_TABLE_149)/sizeof(ixDPM_TABLE_149[0]), 0, 0 },
+	{ "ixDPM_TABLE_150", REG_SMC, 0x3f254, &ixDPM_TABLE_150[0], sizeof(ixDPM_TABLE_150)/sizeof(ixDPM_TABLE_150[0]), 0, 0 },
+	{ "ixDPM_TABLE_151", REG_SMC, 0x3f258, &ixDPM_TABLE_151[0], sizeof(ixDPM_TABLE_151)/sizeof(ixDPM_TABLE_151[0]), 0, 0 },
+	{ "ixDPM_TABLE_152", REG_SMC, 0x3f25c, &ixDPM_TABLE_152[0], sizeof(ixDPM_TABLE_152)/sizeof(ixDPM_TABLE_152[0]), 0, 0 },
+	{ "ixDPM_TABLE_153", REG_SMC, 0x3f260, &ixDPM_TABLE_153[0], sizeof(ixDPM_TABLE_153)/sizeof(ixDPM_TABLE_153[0]), 0, 0 },
+	{ "ixDPM_TABLE_154", REG_SMC, 0x3f264, &ixDPM_TABLE_154[0], sizeof(ixDPM_TABLE_154)/sizeof(ixDPM_TABLE_154[0]), 0, 0 },
+	{ "ixDPM_TABLE_155", REG_SMC, 0x3f268, &ixDPM_TABLE_155[0], sizeof(ixDPM_TABLE_155)/sizeof(ixDPM_TABLE_155[0]), 0, 0 },
+	{ "ixDPM_TABLE_156", REG_SMC, 0x3f26c, &ixDPM_TABLE_156[0], sizeof(ixDPM_TABLE_156)/sizeof(ixDPM_TABLE_156[0]), 0, 0 },
+	{ "ixDPM_TABLE_157", REG_SMC, 0x3f270, &ixDPM_TABLE_157[0], sizeof(ixDPM_TABLE_157)/sizeof(ixDPM_TABLE_157[0]), 0, 0 },
+	{ "ixDPM_TABLE_158", REG_SMC, 0x3f274, &ixDPM_TABLE_158[0], sizeof(ixDPM_TABLE_158)/sizeof(ixDPM_TABLE_158[0]), 0, 0 },
+	{ "ixDPM_TABLE_159", REG_SMC, 0x3f278, &ixDPM_TABLE_159[0], sizeof(ixDPM_TABLE_159)/sizeof(ixDPM_TABLE_159[0]), 0, 0 },
+	{ "ixDPM_TABLE_160", REG_SMC, 0x3f27c, &ixDPM_TABLE_160[0], sizeof(ixDPM_TABLE_160)/sizeof(ixDPM_TABLE_160[0]), 0, 0 },
+	{ "ixDPM_TABLE_161", REG_SMC, 0x3f280, &ixDPM_TABLE_161[0], sizeof(ixDPM_TABLE_161)/sizeof(ixDPM_TABLE_161[0]), 0, 0 },
+	{ "ixDPM_TABLE_162", REG_SMC, 0x3f284, &ixDPM_TABLE_162[0], sizeof(ixDPM_TABLE_162)/sizeof(ixDPM_TABLE_162[0]), 0, 0 },
+	{ "ixDPM_TABLE_163", REG_SMC, 0x3f288, &ixDPM_TABLE_163[0], sizeof(ixDPM_TABLE_163)/sizeof(ixDPM_TABLE_163[0]), 0, 0 },
+	{ "ixDPM_TABLE_164", REG_SMC, 0x3f28c, &ixDPM_TABLE_164[0], sizeof(ixDPM_TABLE_164)/sizeof(ixDPM_TABLE_164[0]), 0, 0 },
+	{ "ixDPM_TABLE_165", REG_SMC, 0x3f290, &ixDPM_TABLE_165[0], sizeof(ixDPM_TABLE_165)/sizeof(ixDPM_TABLE_165[0]), 0, 0 },
+	{ "ixDPM_TABLE_166", REG_SMC, 0x3f294, &ixDPM_TABLE_166[0], sizeof(ixDPM_TABLE_166)/sizeof(ixDPM_TABLE_166[0]), 0, 0 },
+	{ "ixDPM_TABLE_167", REG_SMC, 0x3f298, &ixDPM_TABLE_167[0], sizeof(ixDPM_TABLE_167)/sizeof(ixDPM_TABLE_167[0]), 0, 0 },
+	{ "ixDPM_TABLE_168", REG_SMC, 0x3f29c, &ixDPM_TABLE_168[0], sizeof(ixDPM_TABLE_168)/sizeof(ixDPM_TABLE_168[0]), 0, 0 },
+	{ "ixDPM_TABLE_169", REG_SMC, 0x3f2a0, &ixDPM_TABLE_169[0], sizeof(ixDPM_TABLE_169)/sizeof(ixDPM_TABLE_169[0]), 0, 0 },
+	{ "ixDPM_TABLE_170", REG_SMC, 0x3f2a4, &ixDPM_TABLE_170[0], sizeof(ixDPM_TABLE_170)/sizeof(ixDPM_TABLE_170[0]), 0, 0 },
+	{ "ixDPM_TABLE_171", REG_SMC, 0x3f2a8, &ixDPM_TABLE_171[0], sizeof(ixDPM_TABLE_171)/sizeof(ixDPM_TABLE_171[0]), 0, 0 },
+	{ "ixDPM_TABLE_172", REG_SMC, 0x3f2ac, &ixDPM_TABLE_172[0], sizeof(ixDPM_TABLE_172)/sizeof(ixDPM_TABLE_172[0]), 0, 0 },
+	{ "ixDPM_TABLE_173", REG_SMC, 0x3f2b0, &ixDPM_TABLE_173[0], sizeof(ixDPM_TABLE_173)/sizeof(ixDPM_TABLE_173[0]), 0, 0 },
+	{ "ixDPM_TABLE_174", REG_SMC, 0x3f2b4, &ixDPM_TABLE_174[0], sizeof(ixDPM_TABLE_174)/sizeof(ixDPM_TABLE_174[0]), 0, 0 },
+	{ "ixDPM_TABLE_175", REG_SMC, 0x3f2b8, &ixDPM_TABLE_175[0], sizeof(ixDPM_TABLE_175)/sizeof(ixDPM_TABLE_175[0]), 0, 0 },
+	{ "ixDPM_TABLE_176", REG_SMC, 0x3f2bc, &ixDPM_TABLE_176[0], sizeof(ixDPM_TABLE_176)/sizeof(ixDPM_TABLE_176[0]), 0, 0 },
+	{ "ixDPM_TABLE_177", REG_SMC, 0x3f2c0, &ixDPM_TABLE_177[0], sizeof(ixDPM_TABLE_177)/sizeof(ixDPM_TABLE_177[0]), 0, 0 },
+	{ "ixDPM_TABLE_178", REG_SMC, 0x3f2c4, &ixDPM_TABLE_178[0], sizeof(ixDPM_TABLE_178)/sizeof(ixDPM_TABLE_178[0]), 0, 0 },
+	{ "ixDPM_TABLE_179", REG_SMC, 0x3f2c8, &ixDPM_TABLE_179[0], sizeof(ixDPM_TABLE_179)/sizeof(ixDPM_TABLE_179[0]), 0, 0 },
+	{ "ixDPM_TABLE_180", REG_SMC, 0x3f2cc, &ixDPM_TABLE_180[0], sizeof(ixDPM_TABLE_180)/sizeof(ixDPM_TABLE_180[0]), 0, 0 },
+	{ "ixDPM_TABLE_181", REG_SMC, 0x3f2d0, &ixDPM_TABLE_181[0], sizeof(ixDPM_TABLE_181)/sizeof(ixDPM_TABLE_181[0]), 0, 0 },
+	{ "ixDPM_TABLE_182", REG_SMC, 0x3f2d4, &ixDPM_TABLE_182[0], sizeof(ixDPM_TABLE_182)/sizeof(ixDPM_TABLE_182[0]), 0, 0 },
+	{ "ixDPM_TABLE_183", REG_SMC, 0x3f2d8, &ixDPM_TABLE_183[0], sizeof(ixDPM_TABLE_183)/sizeof(ixDPM_TABLE_183[0]), 0, 0 },
+	{ "ixDPM_TABLE_184", REG_SMC, 0x3f2dc, &ixDPM_TABLE_184[0], sizeof(ixDPM_TABLE_184)/sizeof(ixDPM_TABLE_184[0]), 0, 0 },
+	{ "ixDPM_TABLE_185", REG_SMC, 0x3f2e0, &ixDPM_TABLE_185[0], sizeof(ixDPM_TABLE_185)/sizeof(ixDPM_TABLE_185[0]), 0, 0 },
+	{ "ixDPM_TABLE_186", REG_SMC, 0x3f2e4, &ixDPM_TABLE_186[0], sizeof(ixDPM_TABLE_186)/sizeof(ixDPM_TABLE_186[0]), 0, 0 },
+	{ "ixDPM_TABLE_187", REG_SMC, 0x3f2e8, &ixDPM_TABLE_187[0], sizeof(ixDPM_TABLE_187)/sizeof(ixDPM_TABLE_187[0]), 0, 0 },
+	{ "ixDPM_TABLE_188", REG_SMC, 0x3f2ec, &ixDPM_TABLE_188[0], sizeof(ixDPM_TABLE_188)/sizeof(ixDPM_TABLE_188[0]), 0, 0 },
+	{ "ixDPM_TABLE_189", REG_SMC, 0x3f2f0, &ixDPM_TABLE_189[0], sizeof(ixDPM_TABLE_189)/sizeof(ixDPM_TABLE_189[0]), 0, 0 },
+	{ "ixDPM_TABLE_190", REG_SMC, 0x3f2f4, &ixDPM_TABLE_190[0], sizeof(ixDPM_TABLE_190)/sizeof(ixDPM_TABLE_190[0]), 0, 0 },
+	{ "ixDPM_TABLE_191", REG_SMC, 0x3f2f8, &ixDPM_TABLE_191[0], sizeof(ixDPM_TABLE_191)/sizeof(ixDPM_TABLE_191[0]), 0, 0 },
+	{ "ixDPM_TABLE_192", REG_SMC, 0x3f2fc, &ixDPM_TABLE_192[0], sizeof(ixDPM_TABLE_192)/sizeof(ixDPM_TABLE_192[0]), 0, 0 },
+	{ "ixDPM_TABLE_193", REG_SMC, 0x3f300, &ixDPM_TABLE_193[0], sizeof(ixDPM_TABLE_193)/sizeof(ixDPM_TABLE_193[0]), 0, 0 },
+	{ "ixDPM_TABLE_194", REG_SMC, 0x3f304, &ixDPM_TABLE_194[0], sizeof(ixDPM_TABLE_194)/sizeof(ixDPM_TABLE_194[0]), 0, 0 },
+	{ "ixDPM_TABLE_195", REG_SMC, 0x3f308, &ixDPM_TABLE_195[0], sizeof(ixDPM_TABLE_195)/sizeof(ixDPM_TABLE_195[0]), 0, 0 },
+	{ "ixDPM_TABLE_196", REG_SMC, 0x3f30c, &ixDPM_TABLE_196[0], sizeof(ixDPM_TABLE_196)/sizeof(ixDPM_TABLE_196[0]), 0, 0 },
+	{ "ixDPM_TABLE_197", REG_SMC, 0x3f310, &ixDPM_TABLE_197[0], sizeof(ixDPM_TABLE_197)/sizeof(ixDPM_TABLE_197[0]), 0, 0 },
+	{ "ixDPM_TABLE_198", REG_SMC, 0x3f314, &ixDPM_TABLE_198[0], sizeof(ixDPM_TABLE_198)/sizeof(ixDPM_TABLE_198[0]), 0, 0 },
+	{ "ixDPM_TABLE_199", REG_SMC, 0x3f318, &ixDPM_TABLE_199[0], sizeof(ixDPM_TABLE_199)/sizeof(ixDPM_TABLE_199[0]), 0, 0 },
+	{ "ixDPM_TABLE_200", REG_SMC, 0x3f31c, &ixDPM_TABLE_200[0], sizeof(ixDPM_TABLE_200)/sizeof(ixDPM_TABLE_200[0]), 0, 0 },
+	{ "ixDPM_TABLE_201", REG_SMC, 0x3f320, &ixDPM_TABLE_201[0], sizeof(ixDPM_TABLE_201)/sizeof(ixDPM_TABLE_201[0]), 0, 0 },
+	{ "ixDPM_TABLE_202", REG_SMC, 0x3f324, &ixDPM_TABLE_202[0], sizeof(ixDPM_TABLE_202)/sizeof(ixDPM_TABLE_202[0]), 0, 0 },
+	{ "ixDPM_TABLE_203", REG_SMC, 0x3f328, &ixDPM_TABLE_203[0], sizeof(ixDPM_TABLE_203)/sizeof(ixDPM_TABLE_203[0]), 0, 0 },
+	{ "ixDPM_TABLE_204", REG_SMC, 0x3f32c, &ixDPM_TABLE_204[0], sizeof(ixDPM_TABLE_204)/sizeof(ixDPM_TABLE_204[0]), 0, 0 },
+	{ "ixDPM_TABLE_205", REG_SMC, 0x3f330, &ixDPM_TABLE_205[0], sizeof(ixDPM_TABLE_205)/sizeof(ixDPM_TABLE_205[0]), 0, 0 },
+	{ "ixDPM_TABLE_206", REG_SMC, 0x3f334, &ixDPM_TABLE_206[0], sizeof(ixDPM_TABLE_206)/sizeof(ixDPM_TABLE_206[0]), 0, 0 },
+	{ "ixDPM_TABLE_207", REG_SMC, 0x3f338, &ixDPM_TABLE_207[0], sizeof(ixDPM_TABLE_207)/sizeof(ixDPM_TABLE_207[0]), 0, 0 },
+	{ "ixDPM_TABLE_208", REG_SMC, 0x3f33c, &ixDPM_TABLE_208[0], sizeof(ixDPM_TABLE_208)/sizeof(ixDPM_TABLE_208[0]), 0, 0 },
+	{ "ixDPM_TABLE_209", REG_SMC, 0x3f340, &ixDPM_TABLE_209[0], sizeof(ixDPM_TABLE_209)/sizeof(ixDPM_TABLE_209[0]), 0, 0 },
+	{ "ixDPM_TABLE_210", REG_SMC, 0x3f344, &ixDPM_TABLE_210[0], sizeof(ixDPM_TABLE_210)/sizeof(ixDPM_TABLE_210[0]), 0, 0 },
+	{ "ixDPM_TABLE_211", REG_SMC, 0x3f348, &ixDPM_TABLE_211[0], sizeof(ixDPM_TABLE_211)/sizeof(ixDPM_TABLE_211[0]), 0, 0 },
+	{ "ixDPM_TABLE_212", REG_SMC, 0x3f34c, &ixDPM_TABLE_212[0], sizeof(ixDPM_TABLE_212)/sizeof(ixDPM_TABLE_212[0]), 0, 0 },
+	{ "ixDPM_TABLE_213", REG_SMC, 0x3f350, &ixDPM_TABLE_213[0], sizeof(ixDPM_TABLE_213)/sizeof(ixDPM_TABLE_213[0]), 0, 0 },
+	{ "ixDPM_TABLE_214", REG_SMC, 0x3f354, &ixDPM_TABLE_214[0], sizeof(ixDPM_TABLE_214)/sizeof(ixDPM_TABLE_214[0]), 0, 0 },
+	{ "ixDPM_TABLE_215", REG_SMC, 0x3f358, &ixDPM_TABLE_215[0], sizeof(ixDPM_TABLE_215)/sizeof(ixDPM_TABLE_215[0]), 0, 0 },
+	{ "ixDPM_TABLE_216", REG_SMC, 0x3f35c, &ixDPM_TABLE_216[0], sizeof(ixDPM_TABLE_216)/sizeof(ixDPM_TABLE_216[0]), 0, 0 },
+	{ "ixDPM_TABLE_217", REG_SMC, 0x3f360, &ixDPM_TABLE_217[0], sizeof(ixDPM_TABLE_217)/sizeof(ixDPM_TABLE_217[0]), 0, 0 },
+	{ "ixDPM_TABLE_218", REG_SMC, 0x3f364, &ixDPM_TABLE_218[0], sizeof(ixDPM_TABLE_218)/sizeof(ixDPM_TABLE_218[0]), 0, 0 },
+	{ "ixDPM_TABLE_219", REG_SMC, 0x3f368, &ixDPM_TABLE_219[0], sizeof(ixDPM_TABLE_219)/sizeof(ixDPM_TABLE_219[0]), 0, 0 },
+	{ "ixDPM_TABLE_220", REG_SMC, 0x3f36c, &ixDPM_TABLE_220[0], sizeof(ixDPM_TABLE_220)/sizeof(ixDPM_TABLE_220[0]), 0, 0 },
+	{ "ixDPM_TABLE_221", REG_SMC, 0x3f370, &ixDPM_TABLE_221[0], sizeof(ixDPM_TABLE_221)/sizeof(ixDPM_TABLE_221[0]), 0, 0 },
+	{ "ixDPM_TABLE_222", REG_SMC, 0x3f374, &ixDPM_TABLE_222[0], sizeof(ixDPM_TABLE_222)/sizeof(ixDPM_TABLE_222[0]), 0, 0 },
+	{ "ixDPM_TABLE_223", REG_SMC, 0x3f378, &ixDPM_TABLE_223[0], sizeof(ixDPM_TABLE_223)/sizeof(ixDPM_TABLE_223[0]), 0, 0 },
+	{ "ixDPM_TABLE_224", REG_SMC, 0x3f37c, &ixDPM_TABLE_224[0], sizeof(ixDPM_TABLE_224)/sizeof(ixDPM_TABLE_224[0]), 0, 0 },
+	{ "ixDPM_TABLE_225", REG_SMC, 0x3f380, &ixDPM_TABLE_225[0], sizeof(ixDPM_TABLE_225)/sizeof(ixDPM_TABLE_225[0]), 0, 0 },
+	{ "ixDPM_TABLE_226", REG_SMC, 0x3f384, &ixDPM_TABLE_226[0], sizeof(ixDPM_TABLE_226)/sizeof(ixDPM_TABLE_226[0]), 0, 0 },
+	{ "ixDPM_TABLE_227", REG_SMC, 0x3f388, &ixDPM_TABLE_227[0], sizeof(ixDPM_TABLE_227)/sizeof(ixDPM_TABLE_227[0]), 0, 0 },
+	{ "ixDPM_TABLE_228", REG_SMC, 0x3f38c, &ixDPM_TABLE_228[0], sizeof(ixDPM_TABLE_228)/sizeof(ixDPM_TABLE_228[0]), 0, 0 },
+	{ "ixDPM_TABLE_229", REG_SMC, 0x3f390, &ixDPM_TABLE_229[0], sizeof(ixDPM_TABLE_229)/sizeof(ixDPM_TABLE_229[0]), 0, 0 },
+	{ "ixDPM_TABLE_230", REG_SMC, 0x3f394, &ixDPM_TABLE_230[0], sizeof(ixDPM_TABLE_230)/sizeof(ixDPM_TABLE_230[0]), 0, 0 },
+	{ "ixDPM_TABLE_231", REG_SMC, 0x3f398, &ixDPM_TABLE_231[0], sizeof(ixDPM_TABLE_231)/sizeof(ixDPM_TABLE_231[0]), 0, 0 },
+	{ "ixDPM_TABLE_232", REG_SMC, 0x3f39c, &ixDPM_TABLE_232[0], sizeof(ixDPM_TABLE_232)/sizeof(ixDPM_TABLE_232[0]), 0, 0 },
+	{ "ixDPM_TABLE_233", REG_SMC, 0x3f3a0, &ixDPM_TABLE_233[0], sizeof(ixDPM_TABLE_233)/sizeof(ixDPM_TABLE_233[0]), 0, 0 },
+	{ "ixDPM_TABLE_234", REG_SMC, 0x3f3a4, &ixDPM_TABLE_234[0], sizeof(ixDPM_TABLE_234)/sizeof(ixDPM_TABLE_234[0]), 0, 0 },
+	{ "ixDPM_TABLE_235", REG_SMC, 0x3f3a8, &ixDPM_TABLE_235[0], sizeof(ixDPM_TABLE_235)/sizeof(ixDPM_TABLE_235[0]), 0, 0 },
+	{ "ixDPM_TABLE_236", REG_SMC, 0x3f3ac, &ixDPM_TABLE_236[0], sizeof(ixDPM_TABLE_236)/sizeof(ixDPM_TABLE_236[0]), 0, 0 },
+	{ "ixDPM_TABLE_237", REG_SMC, 0x3f3b0, &ixDPM_TABLE_237[0], sizeof(ixDPM_TABLE_237)/sizeof(ixDPM_TABLE_237[0]), 0, 0 },
+	{ "ixDPM_TABLE_238", REG_SMC, 0x3f3b4, &ixDPM_TABLE_238[0], sizeof(ixDPM_TABLE_238)/sizeof(ixDPM_TABLE_238[0]), 0, 0 },
+	{ "ixDPM_TABLE_239", REG_SMC, 0x3f3b8, &ixDPM_TABLE_239[0], sizeof(ixDPM_TABLE_239)/sizeof(ixDPM_TABLE_239[0]), 0, 0 },
+	{ "ixDPM_TABLE_240", REG_SMC, 0x3f3bc, &ixDPM_TABLE_240[0], sizeof(ixDPM_TABLE_240)/sizeof(ixDPM_TABLE_240[0]), 0, 0 },
+	{ "ixDPM_TABLE_241", REG_SMC, 0x3f3c0, &ixDPM_TABLE_241[0], sizeof(ixDPM_TABLE_241)/sizeof(ixDPM_TABLE_241[0]), 0, 0 },
+	{ "ixDPM_TABLE_242", REG_SMC, 0x3f3c4, &ixDPM_TABLE_242[0], sizeof(ixDPM_TABLE_242)/sizeof(ixDPM_TABLE_242[0]), 0, 0 },
+	{ "ixDPM_TABLE_243", REG_SMC, 0x3f3c8, &ixDPM_TABLE_243[0], sizeof(ixDPM_TABLE_243)/sizeof(ixDPM_TABLE_243[0]), 0, 0 },
+	{ "ixDPM_TABLE_244", REG_SMC, 0x3f3cc, &ixDPM_TABLE_244[0], sizeof(ixDPM_TABLE_244)/sizeof(ixDPM_TABLE_244[0]), 0, 0 },
+	{ "ixDPM_TABLE_245", REG_SMC, 0x3f3d0, &ixDPM_TABLE_245[0], sizeof(ixDPM_TABLE_245)/sizeof(ixDPM_TABLE_245[0]), 0, 0 },
+	{ "ixDPM_TABLE_246", REG_SMC, 0x3f3d4, &ixDPM_TABLE_246[0], sizeof(ixDPM_TABLE_246)/sizeof(ixDPM_TABLE_246[0]), 0, 0 },
+	{ "ixDPM_TABLE_247", REG_SMC, 0x3f3d8, &ixDPM_TABLE_247[0], sizeof(ixDPM_TABLE_247)/sizeof(ixDPM_TABLE_247[0]), 0, 0 },
+	{ "ixDPM_TABLE_248", REG_SMC, 0x3f3dc, &ixDPM_TABLE_248[0], sizeof(ixDPM_TABLE_248)/sizeof(ixDPM_TABLE_248[0]), 0, 0 },
+	{ "ixDPM_TABLE_249", REG_SMC, 0x3f3e0, &ixDPM_TABLE_249[0], sizeof(ixDPM_TABLE_249)/sizeof(ixDPM_TABLE_249[0]), 0, 0 },
+	{ "ixDPM_TABLE_250", REG_SMC, 0x3f3e4, &ixDPM_TABLE_250[0], sizeof(ixDPM_TABLE_250)/sizeof(ixDPM_TABLE_250[0]), 0, 0 },
+	{ "ixDPM_TABLE_251", REG_SMC, 0x3f3e8, &ixDPM_TABLE_251[0], sizeof(ixDPM_TABLE_251)/sizeof(ixDPM_TABLE_251[0]), 0, 0 },
+	{ "ixDPM_TABLE_252", REG_SMC, 0x3f3ec, &ixDPM_TABLE_252[0], sizeof(ixDPM_TABLE_252)/sizeof(ixDPM_TABLE_252[0]), 0, 0 },
+	{ "ixDPM_TABLE_253", REG_SMC, 0x3f3f0, &ixDPM_TABLE_253[0], sizeof(ixDPM_TABLE_253)/sizeof(ixDPM_TABLE_253[0]), 0, 0 },
+	{ "ixDPM_TABLE_254", REG_SMC, 0x3f3f4, &ixDPM_TABLE_254[0], sizeof(ixDPM_TABLE_254)/sizeof(ixDPM_TABLE_254[0]), 0, 0 },
+	{ "ixDPM_TABLE_255", REG_SMC, 0x3f3f8, &ixDPM_TABLE_255[0], sizeof(ixDPM_TABLE_255)/sizeof(ixDPM_TABLE_255[0]), 0, 0 },
+	{ "ixDPM_TABLE_256", REG_SMC, 0x3f3fc, &ixDPM_TABLE_256[0], sizeof(ixDPM_TABLE_256)/sizeof(ixDPM_TABLE_256[0]), 0, 0 },
+	{ "ixDPM_TABLE_257", REG_SMC, 0x3f400, &ixDPM_TABLE_257[0], sizeof(ixDPM_TABLE_257)/sizeof(ixDPM_TABLE_257[0]), 0, 0 },
+	{ "ixDPM_TABLE_258", REG_SMC, 0x3f404, &ixDPM_TABLE_258[0], sizeof(ixDPM_TABLE_258)/sizeof(ixDPM_TABLE_258[0]), 0, 0 },
+	{ "ixDPM_TABLE_259", REG_SMC, 0x3f408, &ixDPM_TABLE_259[0], sizeof(ixDPM_TABLE_259)/sizeof(ixDPM_TABLE_259[0]), 0, 0 },
+	{ "ixDPM_TABLE_260", REG_SMC, 0x3f40c, &ixDPM_TABLE_260[0], sizeof(ixDPM_TABLE_260)/sizeof(ixDPM_TABLE_260[0]), 0, 0 },
+	{ "ixDPM_TABLE_261", REG_SMC, 0x3f410, &ixDPM_TABLE_261[0], sizeof(ixDPM_TABLE_261)/sizeof(ixDPM_TABLE_261[0]), 0, 0 },
+	{ "ixDPM_TABLE_262", REG_SMC, 0x3f414, &ixDPM_TABLE_262[0], sizeof(ixDPM_TABLE_262)/sizeof(ixDPM_TABLE_262[0]), 0, 0 },
+	{ "ixDPM_TABLE_263", REG_SMC, 0x3f418, &ixDPM_TABLE_263[0], sizeof(ixDPM_TABLE_263)/sizeof(ixDPM_TABLE_263[0]), 0, 0 },
+	{ "ixDPM_TABLE_264", REG_SMC, 0x3f41c, &ixDPM_TABLE_264[0], sizeof(ixDPM_TABLE_264)/sizeof(ixDPM_TABLE_264[0]), 0, 0 },
+	{ "ixDPM_TABLE_265", REG_SMC, 0x3f420, &ixDPM_TABLE_265[0], sizeof(ixDPM_TABLE_265)/sizeof(ixDPM_TABLE_265[0]), 0, 0 },
+	{ "ixDPM_TABLE_266", REG_SMC, 0x3f424, &ixDPM_TABLE_266[0], sizeof(ixDPM_TABLE_266)/sizeof(ixDPM_TABLE_266[0]), 0, 0 },
+	{ "ixDPM_TABLE_267", REG_SMC, 0x3f428, &ixDPM_TABLE_267[0], sizeof(ixDPM_TABLE_267)/sizeof(ixDPM_TABLE_267[0]), 0, 0 },
+	{ "ixDPM_TABLE_268", REG_SMC, 0x3f42c, &ixDPM_TABLE_268[0], sizeof(ixDPM_TABLE_268)/sizeof(ixDPM_TABLE_268[0]), 0, 0 },
+	{ "ixDPM_TABLE_269", REG_SMC, 0x3f430, &ixDPM_TABLE_269[0], sizeof(ixDPM_TABLE_269)/sizeof(ixDPM_TABLE_269[0]), 0, 0 },
+	{ "ixDPM_TABLE_270", REG_SMC, 0x3f434, &ixDPM_TABLE_270[0], sizeof(ixDPM_TABLE_270)/sizeof(ixDPM_TABLE_270[0]), 0, 0 },
+	{ "ixDPM_TABLE_271", REG_SMC, 0x3f438, &ixDPM_TABLE_271[0], sizeof(ixDPM_TABLE_271)/sizeof(ixDPM_TABLE_271[0]), 0, 0 },
+	{ "ixDPM_TABLE_272", REG_SMC, 0x3f43c, &ixDPM_TABLE_272[0], sizeof(ixDPM_TABLE_272)/sizeof(ixDPM_TABLE_272[0]), 0, 0 },
+	{ "ixDPM_TABLE_273", REG_SMC, 0x3f440, &ixDPM_TABLE_273[0], sizeof(ixDPM_TABLE_273)/sizeof(ixDPM_TABLE_273[0]), 0, 0 },
+	{ "ixDPM_TABLE_274", REG_SMC, 0x3f444, &ixDPM_TABLE_274[0], sizeof(ixDPM_TABLE_274)/sizeof(ixDPM_TABLE_274[0]), 0, 0 },
+	{ "ixDPM_TABLE_275", REG_SMC, 0x3f448, &ixDPM_TABLE_275[0], sizeof(ixDPM_TABLE_275)/sizeof(ixDPM_TABLE_275[0]), 0, 0 },
+	{ "ixDPM_TABLE_276", REG_SMC, 0x3f44c, &ixDPM_TABLE_276[0], sizeof(ixDPM_TABLE_276)/sizeof(ixDPM_TABLE_276[0]), 0, 0 },
+	{ "ixDPM_TABLE_277", REG_SMC, 0x3f450, &ixDPM_TABLE_277[0], sizeof(ixDPM_TABLE_277)/sizeof(ixDPM_TABLE_277[0]), 0, 0 },
+	{ "ixDPM_TABLE_278", REG_SMC, 0x3f454, &ixDPM_TABLE_278[0], sizeof(ixDPM_TABLE_278)/sizeof(ixDPM_TABLE_278[0]), 0, 0 },
+	{ "ixDPM_TABLE_279", REG_SMC, 0x3f458, &ixDPM_TABLE_279[0], sizeof(ixDPM_TABLE_279)/sizeof(ixDPM_TABLE_279[0]), 0, 0 },
+	{ "ixDPM_TABLE_280", REG_SMC, 0x3f45c, &ixDPM_TABLE_280[0], sizeof(ixDPM_TABLE_280)/sizeof(ixDPM_TABLE_280[0]), 0, 0 },
+	{ "ixDPM_TABLE_281", REG_SMC, 0x3f460, &ixDPM_TABLE_281[0], sizeof(ixDPM_TABLE_281)/sizeof(ixDPM_TABLE_281[0]), 0, 0 },
+	{ "ixDPM_TABLE_282", REG_SMC, 0x3f464, &ixDPM_TABLE_282[0], sizeof(ixDPM_TABLE_282)/sizeof(ixDPM_TABLE_282[0]), 0, 0 },
+	{ "ixDPM_TABLE_283", REG_SMC, 0x3f468, &ixDPM_TABLE_283[0], sizeof(ixDPM_TABLE_283)/sizeof(ixDPM_TABLE_283[0]), 0, 0 },
+	{ "ixDPM_TABLE_284", REG_SMC, 0x3f46c, &ixDPM_TABLE_284[0], sizeof(ixDPM_TABLE_284)/sizeof(ixDPM_TABLE_284[0]), 0, 0 },
+	{ "ixDPM_TABLE_285", REG_SMC, 0x3f470, &ixDPM_TABLE_285[0], sizeof(ixDPM_TABLE_285)/sizeof(ixDPM_TABLE_285[0]), 0, 0 },
+	{ "ixDPM_TABLE_286", REG_SMC, 0x3f474, &ixDPM_TABLE_286[0], sizeof(ixDPM_TABLE_286)/sizeof(ixDPM_TABLE_286[0]), 0, 0 },
+	{ "ixDPM_TABLE_287", REG_SMC, 0x3f478, &ixDPM_TABLE_287[0], sizeof(ixDPM_TABLE_287)/sizeof(ixDPM_TABLE_287[0]), 0, 0 },
+	{ "ixDPM_TABLE_288", REG_SMC, 0x3f47c, &ixDPM_TABLE_288[0], sizeof(ixDPM_TABLE_288)/sizeof(ixDPM_TABLE_288[0]), 0, 0 },
+	{ "ixDPM_TABLE_289", REG_SMC, 0x3f480, &ixDPM_TABLE_289[0], sizeof(ixDPM_TABLE_289)/sizeof(ixDPM_TABLE_289[0]), 0, 0 },
+	{ "ixDPM_TABLE_290", REG_SMC, 0x3f484, &ixDPM_TABLE_290[0], sizeof(ixDPM_TABLE_290)/sizeof(ixDPM_TABLE_290[0]), 0, 0 },
+	{ "ixDPM_TABLE_291", REG_SMC, 0x3f488, &ixDPM_TABLE_291[0], sizeof(ixDPM_TABLE_291)/sizeof(ixDPM_TABLE_291[0]), 0, 0 },
+	{ "ixDPM_TABLE_292", REG_SMC, 0x3f48c, &ixDPM_TABLE_292[0], sizeof(ixDPM_TABLE_292)/sizeof(ixDPM_TABLE_292[0]), 0, 0 },
+	{ "ixDPM_TABLE_293", REG_SMC, 0x3f490, &ixDPM_TABLE_293[0], sizeof(ixDPM_TABLE_293)/sizeof(ixDPM_TABLE_293[0]), 0, 0 },
+	{ "ixDPM_TABLE_294", REG_SMC, 0x3f494, &ixDPM_TABLE_294[0], sizeof(ixDPM_TABLE_294)/sizeof(ixDPM_TABLE_294[0]), 0, 0 },
+	{ "ixDPM_TABLE_295", REG_SMC, 0x3f498, &ixDPM_TABLE_295[0], sizeof(ixDPM_TABLE_295)/sizeof(ixDPM_TABLE_295[0]), 0, 0 },
+	{ "ixDPM_TABLE_296", REG_SMC, 0x3f49c, &ixDPM_TABLE_296[0], sizeof(ixDPM_TABLE_296)/sizeof(ixDPM_TABLE_296[0]), 0, 0 },
+	{ "ixDPM_TABLE_297", REG_SMC, 0x3f4a0, &ixDPM_TABLE_297[0], sizeof(ixDPM_TABLE_297)/sizeof(ixDPM_TABLE_297[0]), 0, 0 },
+	{ "ixDPM_TABLE_298", REG_SMC, 0x3f4a4, &ixDPM_TABLE_298[0], sizeof(ixDPM_TABLE_298)/sizeof(ixDPM_TABLE_298[0]), 0, 0 },
+	{ "ixDPM_TABLE_299", REG_SMC, 0x3f4a8, &ixDPM_TABLE_299[0], sizeof(ixDPM_TABLE_299)/sizeof(ixDPM_TABLE_299[0]), 0, 0 },
+	{ "ixDPM_TABLE_300", REG_SMC, 0x3f4ac, &ixDPM_TABLE_300[0], sizeof(ixDPM_TABLE_300)/sizeof(ixDPM_TABLE_300[0]), 0, 0 },
+	{ "ixDPM_TABLE_301", REG_SMC, 0x3f4b0, &ixDPM_TABLE_301[0], sizeof(ixDPM_TABLE_301)/sizeof(ixDPM_TABLE_301[0]), 0, 0 },
+	{ "ixDPM_TABLE_302", REG_SMC, 0x3f4b4, &ixDPM_TABLE_302[0], sizeof(ixDPM_TABLE_302)/sizeof(ixDPM_TABLE_302[0]), 0, 0 },
+	{ "ixDPM_TABLE_303", REG_SMC, 0x3f4b8, &ixDPM_TABLE_303[0], sizeof(ixDPM_TABLE_303)/sizeof(ixDPM_TABLE_303[0]), 0, 0 },
+	{ "ixDPM_TABLE_304", REG_SMC, 0x3f4bc, &ixDPM_TABLE_304[0], sizeof(ixDPM_TABLE_304)/sizeof(ixDPM_TABLE_304[0]), 0, 0 },
+	{ "ixDPM_TABLE_305", REG_SMC, 0x3f4c0, &ixDPM_TABLE_305[0], sizeof(ixDPM_TABLE_305)/sizeof(ixDPM_TABLE_305[0]), 0, 0 },
+	{ "ixDPM_TABLE_306", REG_SMC, 0x3f4c4, &ixDPM_TABLE_306[0], sizeof(ixDPM_TABLE_306)/sizeof(ixDPM_TABLE_306[0]), 0, 0 },
+	{ "ixDPM_TABLE_307", REG_SMC, 0x3f4c8, &ixDPM_TABLE_307[0], sizeof(ixDPM_TABLE_307)/sizeof(ixDPM_TABLE_307[0]), 0, 0 },
+	{ "ixDPM_TABLE_308", REG_SMC, 0x3f4cc, &ixDPM_TABLE_308[0], sizeof(ixDPM_TABLE_308)/sizeof(ixDPM_TABLE_308[0]), 0, 0 },
+	{ "ixDPM_TABLE_309", REG_SMC, 0x3f4d0, &ixDPM_TABLE_309[0], sizeof(ixDPM_TABLE_309)/sizeof(ixDPM_TABLE_309[0]), 0, 0 },
+	{ "ixDPM_TABLE_310", REG_SMC, 0x3f4d4, &ixDPM_TABLE_310[0], sizeof(ixDPM_TABLE_310)/sizeof(ixDPM_TABLE_310[0]), 0, 0 },
+	{ "ixDPM_TABLE_311", REG_SMC, 0x3f4d8, &ixDPM_TABLE_311[0], sizeof(ixDPM_TABLE_311)/sizeof(ixDPM_TABLE_311[0]), 0, 0 },
+	{ "ixDPM_TABLE_312", REG_SMC, 0x3f4dc, &ixDPM_TABLE_312[0], sizeof(ixDPM_TABLE_312)/sizeof(ixDPM_TABLE_312[0]), 0, 0 },
+	{ "ixDPM_TABLE_313", REG_SMC, 0x3f4e0, &ixDPM_TABLE_313[0], sizeof(ixDPM_TABLE_313)/sizeof(ixDPM_TABLE_313[0]), 0, 0 },
+	{ "ixDPM_TABLE_314", REG_SMC, 0x3f4e4, &ixDPM_TABLE_314[0], sizeof(ixDPM_TABLE_314)/sizeof(ixDPM_TABLE_314[0]), 0, 0 },
+	{ "ixDPM_TABLE_315", REG_SMC, 0x3f4e8, &ixDPM_TABLE_315[0], sizeof(ixDPM_TABLE_315)/sizeof(ixDPM_TABLE_315[0]), 0, 0 },
+	{ "ixDPM_TABLE_316", REG_SMC, 0x3f4ec, &ixDPM_TABLE_316[0], sizeof(ixDPM_TABLE_316)/sizeof(ixDPM_TABLE_316[0]), 0, 0 },
+	{ "ixDPM_TABLE_317", REG_SMC, 0x3f4f0, &ixDPM_TABLE_317[0], sizeof(ixDPM_TABLE_317)/sizeof(ixDPM_TABLE_317[0]), 0, 0 },
+	{ "ixDPM_TABLE_318", REG_SMC, 0x3f4f4, &ixDPM_TABLE_318[0], sizeof(ixDPM_TABLE_318)/sizeof(ixDPM_TABLE_318[0]), 0, 0 },
+	{ "ixDPM_TABLE_319", REG_SMC, 0x3f4f8, &ixDPM_TABLE_319[0], sizeof(ixDPM_TABLE_319)/sizeof(ixDPM_TABLE_319[0]), 0, 0 },
+	{ "ixDPM_TABLE_320", REG_SMC, 0x3f4fc, &ixDPM_TABLE_320[0], sizeof(ixDPM_TABLE_320)/sizeof(ixDPM_TABLE_320[0]), 0, 0 },
+	{ "ixDPM_TABLE_321", REG_SMC, 0x3f500, &ixDPM_TABLE_321[0], sizeof(ixDPM_TABLE_321)/sizeof(ixDPM_TABLE_321[0]), 0, 0 },
+	{ "ixDPM_TABLE_322", REG_SMC, 0x3f504, &ixDPM_TABLE_322[0], sizeof(ixDPM_TABLE_322)/sizeof(ixDPM_TABLE_322[0]), 0, 0 },
+	{ "ixDPM_TABLE_323", REG_SMC, 0x3f508, &ixDPM_TABLE_323[0], sizeof(ixDPM_TABLE_323)/sizeof(ixDPM_TABLE_323[0]), 0, 0 },
+	{ "ixDPM_TABLE_324", REG_SMC, 0x3f50c, &ixDPM_TABLE_324[0], sizeof(ixDPM_TABLE_324)/sizeof(ixDPM_TABLE_324[0]), 0, 0 },
+	{ "ixDPM_TABLE_325", REG_SMC, 0x3f510, &ixDPM_TABLE_325[0], sizeof(ixDPM_TABLE_325)/sizeof(ixDPM_TABLE_325[0]), 0, 0 },
+	{ "ixDPM_TABLE_326", REG_SMC, 0x3f514, &ixDPM_TABLE_326[0], sizeof(ixDPM_TABLE_326)/sizeof(ixDPM_TABLE_326[0]), 0, 0 },
+	{ "ixDPM_TABLE_327", REG_SMC, 0x3f518, &ixDPM_TABLE_327[0], sizeof(ixDPM_TABLE_327)/sizeof(ixDPM_TABLE_327[0]), 0, 0 },
+	{ "ixDPM_TABLE_328", REG_SMC, 0x3f51c, &ixDPM_TABLE_328[0], sizeof(ixDPM_TABLE_328)/sizeof(ixDPM_TABLE_328[0]), 0, 0 },
+	{ "ixDPM_TABLE_329", REG_SMC, 0x3f520, &ixDPM_TABLE_329[0], sizeof(ixDPM_TABLE_329)/sizeof(ixDPM_TABLE_329[0]), 0, 0 },
+	{ "ixDPM_TABLE_330", REG_SMC, 0x3f524, &ixDPM_TABLE_330[0], sizeof(ixDPM_TABLE_330)/sizeof(ixDPM_TABLE_330[0]), 0, 0 },
+	{ "ixDPM_TABLE_331", REG_SMC, 0x3f528, &ixDPM_TABLE_331[0], sizeof(ixDPM_TABLE_331)/sizeof(ixDPM_TABLE_331[0]), 0, 0 },
+	{ "ixDPM_TABLE_332", REG_SMC, 0x3f52c, &ixDPM_TABLE_332[0], sizeof(ixDPM_TABLE_332)/sizeof(ixDPM_TABLE_332[0]), 0, 0 },
+	{ "ixDPM_TABLE_333", REG_SMC, 0x3f530, &ixDPM_TABLE_333[0], sizeof(ixDPM_TABLE_333)/sizeof(ixDPM_TABLE_333[0]), 0, 0 },
+	{ "ixDPM_TABLE_334", REG_SMC, 0x3f534, &ixDPM_TABLE_334[0], sizeof(ixDPM_TABLE_334)/sizeof(ixDPM_TABLE_334[0]), 0, 0 },
+	{ "ixDPM_TABLE_335", REG_SMC, 0x3f538, &ixDPM_TABLE_335[0], sizeof(ixDPM_TABLE_335)/sizeof(ixDPM_TABLE_335[0]), 0, 0 },
+	{ "ixDPM_TABLE_336", REG_SMC, 0x3f53c, &ixDPM_TABLE_336[0], sizeof(ixDPM_TABLE_336)/sizeof(ixDPM_TABLE_336[0]), 0, 0 },
+	{ "ixDPM_TABLE_337", REG_SMC, 0x3f540, &ixDPM_TABLE_337[0], sizeof(ixDPM_TABLE_337)/sizeof(ixDPM_TABLE_337[0]), 0, 0 },
+	{ "ixDPM_TABLE_338", REG_SMC, 0x3f544, &ixDPM_TABLE_338[0], sizeof(ixDPM_TABLE_338)/sizeof(ixDPM_TABLE_338[0]), 0, 0 },
+	{ "ixDPM_TABLE_339", REG_SMC, 0x3f548, &ixDPM_TABLE_339[0], sizeof(ixDPM_TABLE_339)/sizeof(ixDPM_TABLE_339[0]), 0, 0 },
+	{ "ixDPM_TABLE_340", REG_SMC, 0x3f54c, &ixDPM_TABLE_340[0], sizeof(ixDPM_TABLE_340)/sizeof(ixDPM_TABLE_340[0]), 0, 0 },
+	{ "ixDPM_TABLE_341", REG_SMC, 0x3f550, &ixDPM_TABLE_341[0], sizeof(ixDPM_TABLE_341)/sizeof(ixDPM_TABLE_341[0]), 0, 0 },
+	{ "ixDPM_TABLE_342", REG_SMC, 0x3f554, &ixDPM_TABLE_342[0], sizeof(ixDPM_TABLE_342)/sizeof(ixDPM_TABLE_342[0]), 0, 0 },
+	{ "ixDPM_TABLE_343", REG_SMC, 0x3f558, &ixDPM_TABLE_343[0], sizeof(ixDPM_TABLE_343)/sizeof(ixDPM_TABLE_343[0]), 0, 0 },
+	{ "ixDPM_TABLE_344", REG_SMC, 0x3f55c, &ixDPM_TABLE_344[0], sizeof(ixDPM_TABLE_344)/sizeof(ixDPM_TABLE_344[0]), 0, 0 },
+	{ "ixDPM_TABLE_345", REG_SMC, 0x3f560, &ixDPM_TABLE_345[0], sizeof(ixDPM_TABLE_345)/sizeof(ixDPM_TABLE_345[0]), 0, 0 },
+	{ "ixDPM_TABLE_346", REG_SMC, 0x3f564, &ixDPM_TABLE_346[0], sizeof(ixDPM_TABLE_346)/sizeof(ixDPM_TABLE_346[0]), 0, 0 },
+	{ "ixDPM_TABLE_347", REG_SMC, 0x3f568, &ixDPM_TABLE_347[0], sizeof(ixDPM_TABLE_347)/sizeof(ixDPM_TABLE_347[0]), 0, 0 },
+	{ "ixDPM_TABLE_348", REG_SMC, 0x3f56c, &ixDPM_TABLE_348[0], sizeof(ixDPM_TABLE_348)/sizeof(ixDPM_TABLE_348[0]), 0, 0 },
+	{ "ixDPM_TABLE_349", REG_SMC, 0x3f570, &ixDPM_TABLE_349[0], sizeof(ixDPM_TABLE_349)/sizeof(ixDPM_TABLE_349[0]), 0, 0 },
+	{ "ixDPM_TABLE_350", REG_SMC, 0x3f574, &ixDPM_TABLE_350[0], sizeof(ixDPM_TABLE_350)/sizeof(ixDPM_TABLE_350[0]), 0, 0 },
+	{ "ixDPM_TABLE_351", REG_SMC, 0x3f578, &ixDPM_TABLE_351[0], sizeof(ixDPM_TABLE_351)/sizeof(ixDPM_TABLE_351[0]), 0, 0 },
+	{ "ixDPM_TABLE_352", REG_SMC, 0x3f57c, &ixDPM_TABLE_352[0], sizeof(ixDPM_TABLE_352)/sizeof(ixDPM_TABLE_352[0]), 0, 0 },
+	{ "ixDPM_TABLE_353", REG_SMC, 0x3f580, &ixDPM_TABLE_353[0], sizeof(ixDPM_TABLE_353)/sizeof(ixDPM_TABLE_353[0]), 0, 0 },
+	{ "ixDPM_TABLE_354", REG_SMC, 0x3f584, &ixDPM_TABLE_354[0], sizeof(ixDPM_TABLE_354)/sizeof(ixDPM_TABLE_354[0]), 0, 0 },
+	{ "ixDPM_TABLE_355", REG_SMC, 0x3f588, &ixDPM_TABLE_355[0], sizeof(ixDPM_TABLE_355)/sizeof(ixDPM_TABLE_355[0]), 0, 0 },
+	{ "ixDPM_TABLE_356", REG_SMC, 0x3f58c, &ixDPM_TABLE_356[0], sizeof(ixDPM_TABLE_356)/sizeof(ixDPM_TABLE_356[0]), 0, 0 },
+	{ "ixDPM_TABLE_357", REG_SMC, 0x3f590, &ixDPM_TABLE_357[0], sizeof(ixDPM_TABLE_357)/sizeof(ixDPM_TABLE_357[0]), 0, 0 },
+	{ "ixDPM_TABLE_358", REG_SMC, 0x3f594, &ixDPM_TABLE_358[0], sizeof(ixDPM_TABLE_358)/sizeof(ixDPM_TABLE_358[0]), 0, 0 },
+	{ "ixDPM_TABLE_359", REG_SMC, 0x3f598, &ixDPM_TABLE_359[0], sizeof(ixDPM_TABLE_359)/sizeof(ixDPM_TABLE_359[0]), 0, 0 },
+	{ "ixDPM_TABLE_360", REG_SMC, 0x3f59c, &ixDPM_TABLE_360[0], sizeof(ixDPM_TABLE_360)/sizeof(ixDPM_TABLE_360[0]), 0, 0 },
+	{ "ixDPM_TABLE_361", REG_SMC, 0x3f5a0, &ixDPM_TABLE_361[0], sizeof(ixDPM_TABLE_361)/sizeof(ixDPM_TABLE_361[0]), 0, 0 },
+	{ "ixDPM_TABLE_362", REG_SMC, 0x3f5a4, &ixDPM_TABLE_362[0], sizeof(ixDPM_TABLE_362)/sizeof(ixDPM_TABLE_362[0]), 0, 0 },
+	{ "ixDPM_TABLE_363", REG_SMC, 0x3f5a8, &ixDPM_TABLE_363[0], sizeof(ixDPM_TABLE_363)/sizeof(ixDPM_TABLE_363[0]), 0, 0 },
+	{ "ixDPM_TABLE_364", REG_SMC, 0x3f5ac, &ixDPM_TABLE_364[0], sizeof(ixDPM_TABLE_364)/sizeof(ixDPM_TABLE_364[0]), 0, 0 },
+	{ "ixDPM_TABLE_365", REG_SMC, 0x3f5b0, &ixDPM_TABLE_365[0], sizeof(ixDPM_TABLE_365)/sizeof(ixDPM_TABLE_365[0]), 0, 0 },
+	{ "ixDPM_TABLE_366", REG_SMC, 0x3f5b4, &ixDPM_TABLE_366[0], sizeof(ixDPM_TABLE_366)/sizeof(ixDPM_TABLE_366[0]), 0, 0 },
+	{ "ixDPM_TABLE_367", REG_SMC, 0x3f5b8, &ixDPM_TABLE_367[0], sizeof(ixDPM_TABLE_367)/sizeof(ixDPM_TABLE_367[0]), 0, 0 },
+	{ "ixDPM_TABLE_368", REG_SMC, 0x3f5bc, &ixDPM_TABLE_368[0], sizeof(ixDPM_TABLE_368)/sizeof(ixDPM_TABLE_368[0]), 0, 0 },
+	{ "ixDPM_TABLE_369", REG_SMC, 0x3f5c0, &ixDPM_TABLE_369[0], sizeof(ixDPM_TABLE_369)/sizeof(ixDPM_TABLE_369[0]), 0, 0 },
+	{ "ixDPM_TABLE_370", REG_SMC, 0x3f5c4, &ixDPM_TABLE_370[0], sizeof(ixDPM_TABLE_370)/sizeof(ixDPM_TABLE_370[0]), 0, 0 },
+	{ "ixDPM_TABLE_371", REG_SMC, 0x3f5c8, &ixDPM_TABLE_371[0], sizeof(ixDPM_TABLE_371)/sizeof(ixDPM_TABLE_371[0]), 0, 0 },
+	{ "ixDPM_TABLE_372", REG_SMC, 0x3f5cc, &ixDPM_TABLE_372[0], sizeof(ixDPM_TABLE_372)/sizeof(ixDPM_TABLE_372[0]), 0, 0 },
+	{ "ixDPM_TABLE_373", REG_SMC, 0x3f5d0, &ixDPM_TABLE_373[0], sizeof(ixDPM_TABLE_373)/sizeof(ixDPM_TABLE_373[0]), 0, 0 },
+	{ "ixDPM_TABLE_374", REG_SMC, 0x3f5d4, &ixDPM_TABLE_374[0], sizeof(ixDPM_TABLE_374)/sizeof(ixDPM_TABLE_374[0]), 0, 0 },
+	{ "ixDPM_TABLE_375", REG_SMC, 0x3f5d8, &ixDPM_TABLE_375[0], sizeof(ixDPM_TABLE_375)/sizeof(ixDPM_TABLE_375[0]), 0, 0 },
+	{ "ixDPM_TABLE_376", REG_SMC, 0x3f5dc, &ixDPM_TABLE_376[0], sizeof(ixDPM_TABLE_376)/sizeof(ixDPM_TABLE_376[0]), 0, 0 },
+	{ "ixDPM_TABLE_377", REG_SMC, 0x3f5e0, &ixDPM_TABLE_377[0], sizeof(ixDPM_TABLE_377)/sizeof(ixDPM_TABLE_377[0]), 0, 0 },
+	{ "ixDPM_TABLE_378", REG_SMC, 0x3f5e4, &ixDPM_TABLE_378[0], sizeof(ixDPM_TABLE_378)/sizeof(ixDPM_TABLE_378[0]), 0, 0 },
+	{ "ixDPM_TABLE_379", REG_SMC, 0x3f5e8, &ixDPM_TABLE_379[0], sizeof(ixDPM_TABLE_379)/sizeof(ixDPM_TABLE_379[0]), 0, 0 },
+	{ "ixDPM_TABLE_380", REG_SMC, 0x3f5ec, &ixDPM_TABLE_380[0], sizeof(ixDPM_TABLE_380)/sizeof(ixDPM_TABLE_380[0]), 0, 0 },
+	{ "ixDPM_TABLE_381", REG_SMC, 0x3f5f0, &ixDPM_TABLE_381[0], sizeof(ixDPM_TABLE_381)/sizeof(ixDPM_TABLE_381[0]), 0, 0 },
+	{ "ixDPM_TABLE_382", REG_SMC, 0x3f5f4, &ixDPM_TABLE_382[0], sizeof(ixDPM_TABLE_382)/sizeof(ixDPM_TABLE_382[0]), 0, 0 },
+	{ "ixDPM_TABLE_383", REG_SMC, 0x3f5f8, &ixDPM_TABLE_383[0], sizeof(ixDPM_TABLE_383)/sizeof(ixDPM_TABLE_383[0]), 0, 0 },
+	{ "ixDPM_TABLE_384", REG_SMC, 0x3f5fc, &ixDPM_TABLE_384[0], sizeof(ixDPM_TABLE_384)/sizeof(ixDPM_TABLE_384[0]), 0, 0 },
+	{ "ixDPM_TABLE_385", REG_SMC, 0x3f600, &ixDPM_TABLE_385[0], sizeof(ixDPM_TABLE_385)/sizeof(ixDPM_TABLE_385[0]), 0, 0 },
+	{ "ixDPM_TABLE_386", REG_SMC, 0x3f604, &ixDPM_TABLE_386[0], sizeof(ixDPM_TABLE_386)/sizeof(ixDPM_TABLE_386[0]), 0, 0 },
+	{ "ixDPM_TABLE_387", REG_SMC, 0x3f608, &ixDPM_TABLE_387[0], sizeof(ixDPM_TABLE_387)/sizeof(ixDPM_TABLE_387[0]), 0, 0 },
+	{ "ixDPM_TABLE_388", REG_SMC, 0x3f60c, &ixDPM_TABLE_388[0], sizeof(ixDPM_TABLE_388)/sizeof(ixDPM_TABLE_388[0]), 0, 0 },
+	{ "ixDPM_TABLE_389", REG_SMC, 0x3f610, &ixDPM_TABLE_389[0], sizeof(ixDPM_TABLE_389)/sizeof(ixDPM_TABLE_389[0]), 0, 0 },
+	{ "ixDPM_TABLE_390", REG_SMC, 0x3f614, &ixDPM_TABLE_390[0], sizeof(ixDPM_TABLE_390)/sizeof(ixDPM_TABLE_390[0]), 0, 0 },
+	{ "ixDPM_TABLE_391", REG_SMC, 0x3f618, &ixDPM_TABLE_391[0], sizeof(ixDPM_TABLE_391)/sizeof(ixDPM_TABLE_391[0]), 0, 0 },
+	{ "ixDPM_TABLE_392", REG_SMC, 0x3f61c, &ixDPM_TABLE_392[0], sizeof(ixDPM_TABLE_392)/sizeof(ixDPM_TABLE_392[0]), 0, 0 },
+	{ "ixDPM_TABLE_393", REG_SMC, 0x3f620, &ixDPM_TABLE_393[0], sizeof(ixDPM_TABLE_393)/sizeof(ixDPM_TABLE_393[0]), 0, 0 },
+	{ "ixDPM_TABLE_394", REG_SMC, 0x3f624, &ixDPM_TABLE_394[0], sizeof(ixDPM_TABLE_394)/sizeof(ixDPM_TABLE_394[0]), 0, 0 },
+	{ "ixDPM_TABLE_395", REG_SMC, 0x3f628, &ixDPM_TABLE_395[0], sizeof(ixDPM_TABLE_395)/sizeof(ixDPM_TABLE_395[0]), 0, 0 },
+	{ "ixDPM_TABLE_396", REG_SMC, 0x3f62c, &ixDPM_TABLE_396[0], sizeof(ixDPM_TABLE_396)/sizeof(ixDPM_TABLE_396[0]), 0, 0 },
+	{ "ixDPM_TABLE_397", REG_SMC, 0x3f630, &ixDPM_TABLE_397[0], sizeof(ixDPM_TABLE_397)/sizeof(ixDPM_TABLE_397[0]), 0, 0 },
+	{ "ixDPM_TABLE_398", REG_SMC, 0x3f634, &ixDPM_TABLE_398[0], sizeof(ixDPM_TABLE_398)/sizeof(ixDPM_TABLE_398[0]), 0, 0 },
+	{ "ixDPM_TABLE_399", REG_SMC, 0x3f638, &ixDPM_TABLE_399[0], sizeof(ixDPM_TABLE_399)/sizeof(ixDPM_TABLE_399[0]), 0, 0 },
+	{ "ixDPM_TABLE_400", REG_SMC, 0x3f63c, &ixDPM_TABLE_400[0], sizeof(ixDPM_TABLE_400)/sizeof(ixDPM_TABLE_400[0]), 0, 0 },
+	{ "ixDPM_TABLE_401", REG_SMC, 0x3f640, &ixDPM_TABLE_401[0], sizeof(ixDPM_TABLE_401)/sizeof(ixDPM_TABLE_401[0]), 0, 0 },
+	{ "ixDPM_TABLE_402", REG_SMC, 0x3f644, &ixDPM_TABLE_402[0], sizeof(ixDPM_TABLE_402)/sizeof(ixDPM_TABLE_402[0]), 0, 0 },
+	{ "ixDPM_TABLE_403", REG_SMC, 0x3f648, &ixDPM_TABLE_403[0], sizeof(ixDPM_TABLE_403)/sizeof(ixDPM_TABLE_403[0]), 0, 0 },
+	{ "ixDPM_TABLE_404", REG_SMC, 0x3f64c, &ixDPM_TABLE_404[0], sizeof(ixDPM_TABLE_404)/sizeof(ixDPM_TABLE_404[0]), 0, 0 },
+	{ "ixDPM_TABLE_405", REG_SMC, 0x3f650, &ixDPM_TABLE_405[0], sizeof(ixDPM_TABLE_405)/sizeof(ixDPM_TABLE_405[0]), 0, 0 },
+	{ "ixDPM_TABLE_406", REG_SMC, 0x3f654, &ixDPM_TABLE_406[0], sizeof(ixDPM_TABLE_406)/sizeof(ixDPM_TABLE_406[0]), 0, 0 },
+	{ "ixDPM_TABLE_407", REG_SMC, 0x3f658, &ixDPM_TABLE_407[0], sizeof(ixDPM_TABLE_407)/sizeof(ixDPM_TABLE_407[0]), 0, 0 },
+	{ "ixDPM_TABLE_408", REG_SMC, 0x3f65c, &ixDPM_TABLE_408[0], sizeof(ixDPM_TABLE_408)/sizeof(ixDPM_TABLE_408[0]), 0, 0 },
+	{ "ixDPM_TABLE_409", REG_SMC, 0x3f660, &ixDPM_TABLE_409[0], sizeof(ixDPM_TABLE_409)/sizeof(ixDPM_TABLE_409[0]), 0, 0 },
+	{ "ixDPM_TABLE_410", REG_SMC, 0x3f664, &ixDPM_TABLE_410[0], sizeof(ixDPM_TABLE_410)/sizeof(ixDPM_TABLE_410[0]), 0, 0 },
+	{ "ixDPM_TABLE_411", REG_SMC, 0x3f668, &ixDPM_TABLE_411[0], sizeof(ixDPM_TABLE_411)/sizeof(ixDPM_TABLE_411[0]), 0, 0 },
+	{ "ixDPM_TABLE_412", REG_SMC, 0x3f66c, &ixDPM_TABLE_412[0], sizeof(ixDPM_TABLE_412)/sizeof(ixDPM_TABLE_412[0]), 0, 0 },
+	{ "ixDPM_TABLE_413", REG_SMC, 0x3f670, &ixDPM_TABLE_413[0], sizeof(ixDPM_TABLE_413)/sizeof(ixDPM_TABLE_413[0]), 0, 0 },
+	{ "ixDPM_TABLE_414", REG_SMC, 0x3f674, &ixDPM_TABLE_414[0], sizeof(ixDPM_TABLE_414)/sizeof(ixDPM_TABLE_414[0]), 0, 0 },
+	{ "ixDPM_TABLE_415", REG_SMC, 0x3f678, &ixDPM_TABLE_415[0], sizeof(ixDPM_TABLE_415)/sizeof(ixDPM_TABLE_415[0]), 0, 0 },
+	{ "ixDPM_TABLE_416", REG_SMC, 0x3f67c, &ixDPM_TABLE_416[0], sizeof(ixDPM_TABLE_416)/sizeof(ixDPM_TABLE_416[0]), 0, 0 },
+	{ "ixDPM_TABLE_417", REG_SMC, 0x3f680, &ixDPM_TABLE_417[0], sizeof(ixDPM_TABLE_417)/sizeof(ixDPM_TABLE_417[0]), 0, 0 },
+	{ "ixDPM_TABLE_418", REG_SMC, 0x3f684, &ixDPM_TABLE_418[0], sizeof(ixDPM_TABLE_418)/sizeof(ixDPM_TABLE_418[0]), 0, 0 },
+	{ "ixDPM_TABLE_419", REG_SMC, 0x3f688, &ixDPM_TABLE_419[0], sizeof(ixDPM_TABLE_419)/sizeof(ixDPM_TABLE_419[0]), 0, 0 },
+	{ "ixDPM_TABLE_420", REG_SMC, 0x3f68c, &ixDPM_TABLE_420[0], sizeof(ixDPM_TABLE_420)/sizeof(ixDPM_TABLE_420[0]), 0, 0 },
+	{ "ixDPM_TABLE_421", REG_SMC, 0x3f690, &ixDPM_TABLE_421[0], sizeof(ixDPM_TABLE_421)/sizeof(ixDPM_TABLE_421[0]), 0, 0 },
+	{ "ixDPM_TABLE_422", REG_SMC, 0x3f694, &ixDPM_TABLE_422[0], sizeof(ixDPM_TABLE_422)/sizeof(ixDPM_TABLE_422[0]), 0, 0 },
+	{ "ixDPM_TABLE_423", REG_SMC, 0x3f698, &ixDPM_TABLE_423[0], sizeof(ixDPM_TABLE_423)/sizeof(ixDPM_TABLE_423[0]), 0, 0 },
+	{ "ixDPM_TABLE_424", REG_SMC, 0x3f69c, &ixDPM_TABLE_424[0], sizeof(ixDPM_TABLE_424)/sizeof(ixDPM_TABLE_424[0]), 0, 0 },
+	{ "ixDPM_TABLE_425", REG_SMC, 0x3f6a0, &ixDPM_TABLE_425[0], sizeof(ixDPM_TABLE_425)/sizeof(ixDPM_TABLE_425[0]), 0, 0 },
+	{ "ixDPM_TABLE_426", REG_SMC, 0x3f6a4, &ixDPM_TABLE_426[0], sizeof(ixDPM_TABLE_426)/sizeof(ixDPM_TABLE_426[0]), 0, 0 },
+	{ "ixDPM_TABLE_427", REG_SMC, 0x3f6a8, &ixDPM_TABLE_427[0], sizeof(ixDPM_TABLE_427)/sizeof(ixDPM_TABLE_427[0]), 0, 0 },
+	{ "ixDPM_TABLE_428", REG_SMC, 0x3f6ac, &ixDPM_TABLE_428[0], sizeof(ixDPM_TABLE_428)/sizeof(ixDPM_TABLE_428[0]), 0, 0 },
+	{ "ixDPM_TABLE_429", REG_SMC, 0x3f6b0, &ixDPM_TABLE_429[0], sizeof(ixDPM_TABLE_429)/sizeof(ixDPM_TABLE_429[0]), 0, 0 },
+	{ "ixDPM_TABLE_430", REG_SMC, 0x3f6b4, &ixDPM_TABLE_430[0], sizeof(ixDPM_TABLE_430)/sizeof(ixDPM_TABLE_430[0]), 0, 0 },
+	{ "ixDPM_TABLE_431", REG_SMC, 0x3f6b8, &ixDPM_TABLE_431[0], sizeof(ixDPM_TABLE_431)/sizeof(ixDPM_TABLE_431[0]), 0, 0 },
+	{ "ixDPM_TABLE_432", REG_SMC, 0x3f6bc, &ixDPM_TABLE_432[0], sizeof(ixDPM_TABLE_432)/sizeof(ixDPM_TABLE_432[0]), 0, 0 },
+	{ "ixDPM_TABLE_433", REG_SMC, 0x3f6c0, &ixDPM_TABLE_433[0], sizeof(ixDPM_TABLE_433)/sizeof(ixDPM_TABLE_433[0]), 0, 0 },
+	{ "ixDPM_TABLE_434", REG_SMC, 0x3f6c4, &ixDPM_TABLE_434[0], sizeof(ixDPM_TABLE_434)/sizeof(ixDPM_TABLE_434[0]), 0, 0 },
+	{ "ixDPM_TABLE_435", REG_SMC, 0x3f6c8, &ixDPM_TABLE_435[0], sizeof(ixDPM_TABLE_435)/sizeof(ixDPM_TABLE_435[0]), 0, 0 },
+	{ "ixDPM_TABLE_436", REG_SMC, 0x3f6cc, &ixDPM_TABLE_436[0], sizeof(ixDPM_TABLE_436)/sizeof(ixDPM_TABLE_436[0]), 0, 0 },
+	{ "ixDPM_TABLE_437", REG_SMC, 0x3f6d0, &ixDPM_TABLE_437[0], sizeof(ixDPM_TABLE_437)/sizeof(ixDPM_TABLE_437[0]), 0, 0 },
+	{ "ixDPM_TABLE_438", REG_SMC, 0x3f6d4, &ixDPM_TABLE_438[0], sizeof(ixDPM_TABLE_438)/sizeof(ixDPM_TABLE_438[0]), 0, 0 },
+	{ "ixDPM_TABLE_439", REG_SMC, 0x3f6d8, &ixDPM_TABLE_439[0], sizeof(ixDPM_TABLE_439)/sizeof(ixDPM_TABLE_439[0]), 0, 0 },
+	{ "ixDPM_TABLE_440", REG_SMC, 0x3f6dc, &ixDPM_TABLE_440[0], sizeof(ixDPM_TABLE_440)/sizeof(ixDPM_TABLE_440[0]), 0, 0 },
+	{ "ixDPM_TABLE_441", REG_SMC, 0x3f6e0, &ixDPM_TABLE_441[0], sizeof(ixDPM_TABLE_441)/sizeof(ixDPM_TABLE_441[0]), 0, 0 },
+	{ "ixDPM_TABLE_442", REG_SMC, 0x3f6e4, &ixDPM_TABLE_442[0], sizeof(ixDPM_TABLE_442)/sizeof(ixDPM_TABLE_442[0]), 0, 0 },
+	{ "ixDPM_TABLE_443", REG_SMC, 0x3f6e8, &ixDPM_TABLE_443[0], sizeof(ixDPM_TABLE_443)/sizeof(ixDPM_TABLE_443[0]), 0, 0 },
+	{ "ixDPM_TABLE_444", REG_SMC, 0x3f6ec, &ixDPM_TABLE_444[0], sizeof(ixDPM_TABLE_444)/sizeof(ixDPM_TABLE_444[0]), 0, 0 },
+	{ "ixDPM_TABLE_445", REG_SMC, 0x3f6f0, &ixDPM_TABLE_445[0], sizeof(ixDPM_TABLE_445)/sizeof(ixDPM_TABLE_445[0]), 0, 0 },
+	{ "ixDPM_TABLE_446", REG_SMC, 0x3f6f4, &ixDPM_TABLE_446[0], sizeof(ixDPM_TABLE_446)/sizeof(ixDPM_TABLE_446[0]), 0, 0 },
+	{ "ixDPM_TABLE_447", REG_SMC, 0x3f6f8, &ixDPM_TABLE_447[0], sizeof(ixDPM_TABLE_447)/sizeof(ixDPM_TABLE_447[0]), 0, 0 },
+	{ "ixDPM_TABLE_448", REG_SMC, 0x3f6fc, &ixDPM_TABLE_448[0], sizeof(ixDPM_TABLE_448)/sizeof(ixDPM_TABLE_448[0]), 0, 0 },
+	{ "ixDPM_TABLE_449", REG_SMC, 0x3f700, &ixDPM_TABLE_449[0], sizeof(ixDPM_TABLE_449)/sizeof(ixDPM_TABLE_449[0]), 0, 0 },
+	{ "ixDPM_TABLE_450", REG_SMC, 0x3f704, &ixDPM_TABLE_450[0], sizeof(ixDPM_TABLE_450)/sizeof(ixDPM_TABLE_450[0]), 0, 0 },
+	{ "ixDPM_TABLE_451", REG_SMC, 0x3f708, &ixDPM_TABLE_451[0], sizeof(ixDPM_TABLE_451)/sizeof(ixDPM_TABLE_451[0]), 0, 0 },
+	{ "ixDPM_TABLE_452", REG_SMC, 0x3f70c, &ixDPM_TABLE_452[0], sizeof(ixDPM_TABLE_452)/sizeof(ixDPM_TABLE_452[0]), 0, 0 },
+	{ "ixDPM_TABLE_453", REG_SMC, 0x3f710, &ixDPM_TABLE_453[0], sizeof(ixDPM_TABLE_453)/sizeof(ixDPM_TABLE_453[0]), 0, 0 },
+	{ "ixDPM_TABLE_454", REG_SMC, 0x3f714, &ixDPM_TABLE_454[0], sizeof(ixDPM_TABLE_454)/sizeof(ixDPM_TABLE_454[0]), 0, 0 },
+	{ "ixDPM_TABLE_455", REG_SMC, 0x3f718, &ixDPM_TABLE_455[0], sizeof(ixDPM_TABLE_455)/sizeof(ixDPM_TABLE_455[0]), 0, 0 },
+	{ "ixDPM_TABLE_456", REG_SMC, 0x3f71c, &ixDPM_TABLE_456[0], sizeof(ixDPM_TABLE_456)/sizeof(ixDPM_TABLE_456[0]), 0, 0 },
+	{ "ixDPM_TABLE_457", REG_SMC, 0x3f720, &ixDPM_TABLE_457[0], sizeof(ixDPM_TABLE_457)/sizeof(ixDPM_TABLE_457[0]), 0, 0 },
+	{ "ixDPM_TABLE_458", REG_SMC, 0x3f724, &ixDPM_TABLE_458[0], sizeof(ixDPM_TABLE_458)/sizeof(ixDPM_TABLE_458[0]), 0, 0 },
+	{ "ixDPM_TABLE_459", REG_SMC, 0x3f728, &ixDPM_TABLE_459[0], sizeof(ixDPM_TABLE_459)/sizeof(ixDPM_TABLE_459[0]), 0, 0 },
+	{ "ixDPM_TABLE_460", REG_SMC, 0x3f72c, &ixDPM_TABLE_460[0], sizeof(ixDPM_TABLE_460)/sizeof(ixDPM_TABLE_460[0]), 0, 0 },
+	{ "ixDPM_TABLE_461", REG_SMC, 0x3f730, &ixDPM_TABLE_461[0], sizeof(ixDPM_TABLE_461)/sizeof(ixDPM_TABLE_461[0]), 0, 0 },
+	{ "ixDPM_TABLE_462", REG_SMC, 0x3f734, &ixDPM_TABLE_462[0], sizeof(ixDPM_TABLE_462)/sizeof(ixDPM_TABLE_462[0]), 0, 0 },
+	{ "ixDPM_TABLE_463", REG_SMC, 0x3f738, &ixDPM_TABLE_463[0], sizeof(ixDPM_TABLE_463)/sizeof(ixDPM_TABLE_463[0]), 0, 0 },
+	{ "ixDPM_TABLE_464", REG_SMC, 0x3f73c, &ixDPM_TABLE_464[0], sizeof(ixDPM_TABLE_464)/sizeof(ixDPM_TABLE_464[0]), 0, 0 },
+	{ "ixDPM_TABLE_465", REG_SMC, 0x3f740, &ixDPM_TABLE_465[0], sizeof(ixDPM_TABLE_465)/sizeof(ixDPM_TABLE_465[0]), 0, 0 },
+	{ "ixDPM_TABLE_466", REG_SMC, 0x3f744, &ixDPM_TABLE_466[0], sizeof(ixDPM_TABLE_466)/sizeof(ixDPM_TABLE_466[0]), 0, 0 },
+	{ "ixDPM_TABLE_467", REG_SMC, 0x3f748, &ixDPM_TABLE_467[0], sizeof(ixDPM_TABLE_467)/sizeof(ixDPM_TABLE_467[0]), 0, 0 },
+	{ "ixDPM_TABLE_468", REG_SMC, 0x3f74c, &ixDPM_TABLE_468[0], sizeof(ixDPM_TABLE_468)/sizeof(ixDPM_TABLE_468[0]), 0, 0 },
+	{ "ixDPM_TABLE_469", REG_SMC, 0x3f750, &ixDPM_TABLE_469[0], sizeof(ixDPM_TABLE_469)/sizeof(ixDPM_TABLE_469[0]), 0, 0 },
+	{ "ixDPM_TABLE_470", REG_SMC, 0x3f754, &ixDPM_TABLE_470[0], sizeof(ixDPM_TABLE_470)/sizeof(ixDPM_TABLE_470[0]), 0, 0 },
+	{ "ixDPM_TABLE_471", REG_SMC, 0x3f758, &ixDPM_TABLE_471[0], sizeof(ixDPM_TABLE_471)/sizeof(ixDPM_TABLE_471[0]), 0, 0 },
+	{ "ixDPM_TABLE_472", REG_SMC, 0x3f75c, &ixDPM_TABLE_472[0], sizeof(ixDPM_TABLE_472)/sizeof(ixDPM_TABLE_472[0]), 0, 0 },
+	{ "ixDPM_TABLE_473", REG_SMC, 0x3f760, &ixDPM_TABLE_473[0], sizeof(ixDPM_TABLE_473)/sizeof(ixDPM_TABLE_473[0]), 0, 0 },
+	{ "ixDPM_TABLE_474", REG_SMC, 0x3f764, &ixDPM_TABLE_474[0], sizeof(ixDPM_TABLE_474)/sizeof(ixDPM_TABLE_474[0]), 0, 0 },
+	{ "ixDPM_TABLE_475", REG_SMC, 0x3f768, &ixDPM_TABLE_475[0], sizeof(ixDPM_TABLE_475)/sizeof(ixDPM_TABLE_475[0]), 0, 0 },
+	{ "ixDPM_TABLE_476", REG_SMC, 0x3f76c, &ixDPM_TABLE_476[0], sizeof(ixDPM_TABLE_476)/sizeof(ixDPM_TABLE_476[0]), 0, 0 },
+	{ "ixDPM_TABLE_477", REG_SMC, 0x3f770, &ixDPM_TABLE_477[0], sizeof(ixDPM_TABLE_477)/sizeof(ixDPM_TABLE_477[0]), 0, 0 },
+	{ "ixDPM_TABLE_478", REG_SMC, 0x3f774, &ixDPM_TABLE_478[0], sizeof(ixDPM_TABLE_478)/sizeof(ixDPM_TABLE_478[0]), 0, 0 },
+	{ "ixDPM_TABLE_479", REG_SMC, 0x3f778, &ixDPM_TABLE_479[0], sizeof(ixDPM_TABLE_479)/sizeof(ixDPM_TABLE_479[0]), 0, 0 },
+	{ "ixDPM_TABLE_480", REG_SMC, 0x3f77c, &ixDPM_TABLE_480[0], sizeof(ixDPM_TABLE_480)/sizeof(ixDPM_TABLE_480[0]), 0, 0 },
+	{ "ixDPM_TABLE_481", REG_SMC, 0x3f780, &ixDPM_TABLE_481[0], sizeof(ixDPM_TABLE_481)/sizeof(ixDPM_TABLE_481[0]), 0, 0 },
+	{ "ixDPM_TABLE_482", REG_SMC, 0x3f784, &ixDPM_TABLE_482[0], sizeof(ixDPM_TABLE_482)/sizeof(ixDPM_TABLE_482[0]), 0, 0 },
+	{ "ixDPM_TABLE_483", REG_SMC, 0x3f788, &ixDPM_TABLE_483[0], sizeof(ixDPM_TABLE_483)/sizeof(ixDPM_TABLE_483[0]), 0, 0 },
+	{ "ixDPM_TABLE_484", REG_SMC, 0x3f78c, &ixDPM_TABLE_484[0], sizeof(ixDPM_TABLE_484)/sizeof(ixDPM_TABLE_484[0]), 0, 0 },
+	{ "ixDPM_TABLE_485", REG_SMC, 0x3f790, &ixDPM_TABLE_485[0], sizeof(ixDPM_TABLE_485)/sizeof(ixDPM_TABLE_485[0]), 0, 0 },
+	{ "ixDPM_TABLE_486", REG_SMC, 0x3f794, &ixDPM_TABLE_486[0], sizeof(ixDPM_TABLE_486)/sizeof(ixDPM_TABLE_486[0]), 0, 0 },
+	{ "ixDPM_TABLE_487", REG_SMC, 0x3f798, &ixDPM_TABLE_487[0], sizeof(ixDPM_TABLE_487)/sizeof(ixDPM_TABLE_487[0]), 0, 0 },
+	{ "ixDPM_TABLE_488", REG_SMC, 0x3f79c, &ixDPM_TABLE_488[0], sizeof(ixDPM_TABLE_488)/sizeof(ixDPM_TABLE_488[0]), 0, 0 },
+	{ "ixDPM_TABLE_489", REG_SMC, 0x3f7a0, &ixDPM_TABLE_489[0], sizeof(ixDPM_TABLE_489)/sizeof(ixDPM_TABLE_489[0]), 0, 0 },
+	{ "ixDPM_TABLE_490", REG_SMC, 0x3f7a4, &ixDPM_TABLE_490[0], sizeof(ixDPM_TABLE_490)/sizeof(ixDPM_TABLE_490[0]), 0, 0 },
+	{ "ixDPM_TABLE_491", REG_SMC, 0x3f7a8, &ixDPM_TABLE_491[0], sizeof(ixDPM_TABLE_491)/sizeof(ixDPM_TABLE_491[0]), 0, 0 },
+	{ "ixDPM_TABLE_492", REG_SMC, 0x3f7ac, &ixDPM_TABLE_492[0], sizeof(ixDPM_TABLE_492)/sizeof(ixDPM_TABLE_492[0]), 0, 0 },
+	{ "ixDPM_TABLE_493", REG_SMC, 0x3f7b0, &ixDPM_TABLE_493[0], sizeof(ixDPM_TABLE_493)/sizeof(ixDPM_TABLE_493[0]), 0, 0 },
+	{ "ixDPM_TABLE_494", REG_SMC, 0x3f7b4, &ixDPM_TABLE_494[0], sizeof(ixDPM_TABLE_494)/sizeof(ixDPM_TABLE_494[0]), 0, 0 },
+	{ "ixDPM_TABLE_495", REG_SMC, 0x3f7b8, &ixDPM_TABLE_495[0], sizeof(ixDPM_TABLE_495)/sizeof(ixDPM_TABLE_495[0]), 0, 0 },
+	{ "ixDPM_TABLE_496", REG_SMC, 0x3f7bc, &ixDPM_TABLE_496[0], sizeof(ixDPM_TABLE_496)/sizeof(ixDPM_TABLE_496[0]), 0, 0 },
+	{ "ixDPM_TABLE_497", REG_SMC, 0x3f7c0, &ixDPM_TABLE_497[0], sizeof(ixDPM_TABLE_497)/sizeof(ixDPM_TABLE_497[0]), 0, 0 },
+	{ "ixDPM_TABLE_498", REG_SMC, 0x3f7c4, &ixDPM_TABLE_498[0], sizeof(ixDPM_TABLE_498)/sizeof(ixDPM_TABLE_498[0]), 0, 0 },
+	{ "ixDPM_TABLE_499", REG_SMC, 0x3f7c8, &ixDPM_TABLE_499[0], sizeof(ixDPM_TABLE_499)/sizeof(ixDPM_TABLE_499[0]), 0, 0 },
+	{ "ixDPM_TABLE_500", REG_SMC, 0x3f7cc, &ixDPM_TABLE_500[0], sizeof(ixDPM_TABLE_500)/sizeof(ixDPM_TABLE_500[0]), 0, 0 },
+	{ "ixDPM_TABLE_501", REG_SMC, 0x3f7d0, &ixDPM_TABLE_501[0], sizeof(ixDPM_TABLE_501)/sizeof(ixDPM_TABLE_501[0]), 0, 0 },
+	{ "ixDPM_TABLE_502", REG_SMC, 0x3f7d4, &ixDPM_TABLE_502[0], sizeof(ixDPM_TABLE_502)/sizeof(ixDPM_TABLE_502[0]), 0, 0 },
+	{ "ixDPM_TABLE_503", REG_SMC, 0x3f7d8, &ixDPM_TABLE_503[0], sizeof(ixDPM_TABLE_503)/sizeof(ixDPM_TABLE_503[0]), 0, 0 },
+	{ "ixDPM_TABLE_504", REG_SMC, 0x3f7dc, &ixDPM_TABLE_504[0], sizeof(ixDPM_TABLE_504)/sizeof(ixDPM_TABLE_504[0]), 0, 0 },
+	{ "ixDPM_TABLE_505", REG_SMC, 0x3f7e0, &ixDPM_TABLE_505[0], sizeof(ixDPM_TABLE_505)/sizeof(ixDPM_TABLE_505[0]), 0, 0 },
+	{ "ixDPM_TABLE_506", REG_SMC, 0x3f7e4, &ixDPM_TABLE_506[0], sizeof(ixDPM_TABLE_506)/sizeof(ixDPM_TABLE_506[0]), 0, 0 },
+	{ "ixFIRMWARE_FLAGS", REG_SMC, 0x3f800, &ixFIRMWARE_FLAGS[0], sizeof(ixFIRMWARE_FLAGS)/sizeof(ixFIRMWARE_FLAGS[0]), 0, 0 },
+	{ "ixTDC_STATUS", REG_SMC, 0x3f808, &ixTDC_STATUS[0], sizeof(ixTDC_STATUS)/sizeof(ixTDC_STATUS[0]), 0, 0 },
+	{ "ixTDC_MV_AVERAGE", REG_SMC, 0x3f80c, &ixTDC_MV_AVERAGE[0], sizeof(ixTDC_MV_AVERAGE)/sizeof(ixTDC_MV_AVERAGE[0]), 0, 0 },
+	{ "ixTDC_VRM_LIMIT", REG_SMC, 0x3f810, &ixTDC_VRM_LIMIT[0], sizeof(ixTDC_VRM_LIMIT)/sizeof(ixTDC_VRM_LIMIT[0]), 0, 0 },
+	{ "ixFEATURE_STATUS", REG_SMC, 0x3f818, &ixFEATURE_STATUS[0], sizeof(ixFEATURE_STATUS)/sizeof(ixFEATURE_STATUS[0]), 0, 0 },
+	{ "ixENTITY_TEMPERATURES_1", REG_SMC, 0x3f81c, &ixENTITY_TEMPERATURES_1[0], sizeof(ixENTITY_TEMPERATURES_1)/sizeof(ixENTITY_TEMPERATURES_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_1", REG_SMC, 0x3f900, &ixMCARB_DRAM_TIMING_TABLE_1[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_1)/sizeof(ixMCARB_DRAM_TIMING_TABLE_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_2", REG_SMC, 0x3f904, &ixMCARB_DRAM_TIMING_TABLE_2[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_2)/sizeof(ixMCARB_DRAM_TIMING_TABLE_2[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_3", REG_SMC, 0x3f908, &ixMCARB_DRAM_TIMING_TABLE_3[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_3)/sizeof(ixMCARB_DRAM_TIMING_TABLE_3[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_4", REG_SMC, 0x3f90c, &ixMCARB_DRAM_TIMING_TABLE_4[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_4)/sizeof(ixMCARB_DRAM_TIMING_TABLE_4[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_5", REG_SMC, 0x3f910, &ixMCARB_DRAM_TIMING_TABLE_5[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_5)/sizeof(ixMCARB_DRAM_TIMING_TABLE_5[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_6", REG_SMC, 0x3f914, &ixMCARB_DRAM_TIMING_TABLE_6[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_6)/sizeof(ixMCARB_DRAM_TIMING_TABLE_6[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_7", REG_SMC, 0x3f918, &ixMCARB_DRAM_TIMING_TABLE_7[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_7)/sizeof(ixMCARB_DRAM_TIMING_TABLE_7[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_8", REG_SMC, 0x3f91c, &ixMCARB_DRAM_TIMING_TABLE_8[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_8)/sizeof(ixMCARB_DRAM_TIMING_TABLE_8[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_9", REG_SMC, 0x3f920, &ixMCARB_DRAM_TIMING_TABLE_9[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_9)/sizeof(ixMCARB_DRAM_TIMING_TABLE_9[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_10", REG_SMC, 0x3f924, &ixMCARB_DRAM_TIMING_TABLE_10[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_10)/sizeof(ixMCARB_DRAM_TIMING_TABLE_10[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_11", REG_SMC, 0x3f928, &ixMCARB_DRAM_TIMING_TABLE_11[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_11)/sizeof(ixMCARB_DRAM_TIMING_TABLE_11[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_12", REG_SMC, 0x3f92c, &ixMCARB_DRAM_TIMING_TABLE_12[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_12)/sizeof(ixMCARB_DRAM_TIMING_TABLE_12[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_13", REG_SMC, 0x3f930, &ixMCARB_DRAM_TIMING_TABLE_13[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_13)/sizeof(ixMCARB_DRAM_TIMING_TABLE_13[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_14", REG_SMC, 0x3f934, &ixMCARB_DRAM_TIMING_TABLE_14[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_14)/sizeof(ixMCARB_DRAM_TIMING_TABLE_14[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_15", REG_SMC, 0x3f938, &ixMCARB_DRAM_TIMING_TABLE_15[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_15)/sizeof(ixMCARB_DRAM_TIMING_TABLE_15[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_16", REG_SMC, 0x3f93c, &ixMCARB_DRAM_TIMING_TABLE_16[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_16)/sizeof(ixMCARB_DRAM_TIMING_TABLE_16[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_17", REG_SMC, 0x3f940, &ixMCARB_DRAM_TIMING_TABLE_17[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_17)/sizeof(ixMCARB_DRAM_TIMING_TABLE_17[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_18", REG_SMC, 0x3f944, &ixMCARB_DRAM_TIMING_TABLE_18[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_18)/sizeof(ixMCARB_DRAM_TIMING_TABLE_18[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_19", REG_SMC, 0x3f948, &ixMCARB_DRAM_TIMING_TABLE_19[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_19)/sizeof(ixMCARB_DRAM_TIMING_TABLE_19[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_20", REG_SMC, 0x3f94c, &ixMCARB_DRAM_TIMING_TABLE_20[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_20)/sizeof(ixMCARB_DRAM_TIMING_TABLE_20[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_21", REG_SMC, 0x3f950, &ixMCARB_DRAM_TIMING_TABLE_21[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_21)/sizeof(ixMCARB_DRAM_TIMING_TABLE_21[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_22", REG_SMC, 0x3f954, &ixMCARB_DRAM_TIMING_TABLE_22[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_22)/sizeof(ixMCARB_DRAM_TIMING_TABLE_22[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_23", REG_SMC, 0x3f958, &ixMCARB_DRAM_TIMING_TABLE_23[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_23)/sizeof(ixMCARB_DRAM_TIMING_TABLE_23[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_24", REG_SMC, 0x3f95c, &ixMCARB_DRAM_TIMING_TABLE_24[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_24)/sizeof(ixMCARB_DRAM_TIMING_TABLE_24[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_25", REG_SMC, 0x3f960, &ixMCARB_DRAM_TIMING_TABLE_25[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_25)/sizeof(ixMCARB_DRAM_TIMING_TABLE_25[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_26", REG_SMC, 0x3f964, &ixMCARB_DRAM_TIMING_TABLE_26[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_26)/sizeof(ixMCARB_DRAM_TIMING_TABLE_26[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_27", REG_SMC, 0x3f968, &ixMCARB_DRAM_TIMING_TABLE_27[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_27)/sizeof(ixMCARB_DRAM_TIMING_TABLE_27[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_28", REG_SMC, 0x3f96c, &ixMCARB_DRAM_TIMING_TABLE_28[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_28)/sizeof(ixMCARB_DRAM_TIMING_TABLE_28[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_29", REG_SMC, 0x3f970, &ixMCARB_DRAM_TIMING_TABLE_29[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_29)/sizeof(ixMCARB_DRAM_TIMING_TABLE_29[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_30", REG_SMC, 0x3f974, &ixMCARB_DRAM_TIMING_TABLE_30[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_30)/sizeof(ixMCARB_DRAM_TIMING_TABLE_30[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_31", REG_SMC, 0x3f978, &ixMCARB_DRAM_TIMING_TABLE_31[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_31)/sizeof(ixMCARB_DRAM_TIMING_TABLE_31[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_32", REG_SMC, 0x3f97c, &ixMCARB_DRAM_TIMING_TABLE_32[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_32)/sizeof(ixMCARB_DRAM_TIMING_TABLE_32[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_33", REG_SMC, 0x3f980, &ixMCARB_DRAM_TIMING_TABLE_33[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_33)/sizeof(ixMCARB_DRAM_TIMING_TABLE_33[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_34", REG_SMC, 0x3f984, &ixMCARB_DRAM_TIMING_TABLE_34[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_34)/sizeof(ixMCARB_DRAM_TIMING_TABLE_34[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_35", REG_SMC, 0x3f988, &ixMCARB_DRAM_TIMING_TABLE_35[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_35)/sizeof(ixMCARB_DRAM_TIMING_TABLE_35[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_36", REG_SMC, 0x3f98c, &ixMCARB_DRAM_TIMING_TABLE_36[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_36)/sizeof(ixMCARB_DRAM_TIMING_TABLE_36[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_37", REG_SMC, 0x3f990, &ixMCARB_DRAM_TIMING_TABLE_37[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_37)/sizeof(ixMCARB_DRAM_TIMING_TABLE_37[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_38", REG_SMC, 0x3f994, &ixMCARB_DRAM_TIMING_TABLE_38[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_38)/sizeof(ixMCARB_DRAM_TIMING_TABLE_38[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_39", REG_SMC, 0x3f998, &ixMCARB_DRAM_TIMING_TABLE_39[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_39)/sizeof(ixMCARB_DRAM_TIMING_TABLE_39[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_40", REG_SMC, 0x3f99c, &ixMCARB_DRAM_TIMING_TABLE_40[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_40)/sizeof(ixMCARB_DRAM_TIMING_TABLE_40[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_41", REG_SMC, 0x3f9a0, &ixMCARB_DRAM_TIMING_TABLE_41[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_41)/sizeof(ixMCARB_DRAM_TIMING_TABLE_41[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_42", REG_SMC, 0x3f9a4, &ixMCARB_DRAM_TIMING_TABLE_42[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_42)/sizeof(ixMCARB_DRAM_TIMING_TABLE_42[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_43", REG_SMC, 0x3f9a8, &ixMCARB_DRAM_TIMING_TABLE_43[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_43)/sizeof(ixMCARB_DRAM_TIMING_TABLE_43[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_44", REG_SMC, 0x3f9ac, &ixMCARB_DRAM_TIMING_TABLE_44[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_44)/sizeof(ixMCARB_DRAM_TIMING_TABLE_44[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_45", REG_SMC, 0x3f9b0, &ixMCARB_DRAM_TIMING_TABLE_45[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_45)/sizeof(ixMCARB_DRAM_TIMING_TABLE_45[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_46", REG_SMC, 0x3f9b4, &ixMCARB_DRAM_TIMING_TABLE_46[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_46)/sizeof(ixMCARB_DRAM_TIMING_TABLE_46[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_47", REG_SMC, 0x3f9b8, &ixMCARB_DRAM_TIMING_TABLE_47[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_47)/sizeof(ixMCARB_DRAM_TIMING_TABLE_47[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_48", REG_SMC, 0x3f9bc, &ixMCARB_DRAM_TIMING_TABLE_48[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_48)/sizeof(ixMCARB_DRAM_TIMING_TABLE_48[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_49", REG_SMC, 0x3f9c0, &ixMCARB_DRAM_TIMING_TABLE_49[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_49)/sizeof(ixMCARB_DRAM_TIMING_TABLE_49[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_50", REG_SMC, 0x3f9c4, &ixMCARB_DRAM_TIMING_TABLE_50[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_50)/sizeof(ixMCARB_DRAM_TIMING_TABLE_50[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_51", REG_SMC, 0x3f9c8, &ixMCARB_DRAM_TIMING_TABLE_51[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_51)/sizeof(ixMCARB_DRAM_TIMING_TABLE_51[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_52", REG_SMC, 0x3f9cc, &ixMCARB_DRAM_TIMING_TABLE_52[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_52)/sizeof(ixMCARB_DRAM_TIMING_TABLE_52[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_53", REG_SMC, 0x3f9d0, &ixMCARB_DRAM_TIMING_TABLE_53[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_53)/sizeof(ixMCARB_DRAM_TIMING_TABLE_53[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_54", REG_SMC, 0x3f9d4, &ixMCARB_DRAM_TIMING_TABLE_54[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_54)/sizeof(ixMCARB_DRAM_TIMING_TABLE_54[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_55", REG_SMC, 0x3f9d8, &ixMCARB_DRAM_TIMING_TABLE_55[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_55)/sizeof(ixMCARB_DRAM_TIMING_TABLE_55[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_56", REG_SMC, 0x3f9dc, &ixMCARB_DRAM_TIMING_TABLE_56[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_56)/sizeof(ixMCARB_DRAM_TIMING_TABLE_56[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_57", REG_SMC, 0x3f9e0, &ixMCARB_DRAM_TIMING_TABLE_57[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_57)/sizeof(ixMCARB_DRAM_TIMING_TABLE_57[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_58", REG_SMC, 0x3f9e4, &ixMCARB_DRAM_TIMING_TABLE_58[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_58)/sizeof(ixMCARB_DRAM_TIMING_TABLE_58[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_59", REG_SMC, 0x3f9e8, &ixMCARB_DRAM_TIMING_TABLE_59[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_59)/sizeof(ixMCARB_DRAM_TIMING_TABLE_59[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_60", REG_SMC, 0x3f9ec, &ixMCARB_DRAM_TIMING_TABLE_60[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_60)/sizeof(ixMCARB_DRAM_TIMING_TABLE_60[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_61", REG_SMC, 0x3f9f0, &ixMCARB_DRAM_TIMING_TABLE_61[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_61)/sizeof(ixMCARB_DRAM_TIMING_TABLE_61[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_62", REG_SMC, 0x3f9f4, &ixMCARB_DRAM_TIMING_TABLE_62[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_62)/sizeof(ixMCARB_DRAM_TIMING_TABLE_62[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_63", REG_SMC, 0x3f9f8, &ixMCARB_DRAM_TIMING_TABLE_63[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_63)/sizeof(ixMCARB_DRAM_TIMING_TABLE_63[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_64", REG_SMC, 0x3f9fc, &ixMCARB_DRAM_TIMING_TABLE_64[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_64)/sizeof(ixMCARB_DRAM_TIMING_TABLE_64[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_65", REG_SMC, 0x3fa00, &ixMCARB_DRAM_TIMING_TABLE_65[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_65)/sizeof(ixMCARB_DRAM_TIMING_TABLE_65[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_66", REG_SMC, 0x3fa04, &ixMCARB_DRAM_TIMING_TABLE_66[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_66)/sizeof(ixMCARB_DRAM_TIMING_TABLE_66[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_67", REG_SMC, 0x3fa08, &ixMCARB_DRAM_TIMING_TABLE_67[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_67)/sizeof(ixMCARB_DRAM_TIMING_TABLE_67[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_68", REG_SMC, 0x3fa0c, &ixMCARB_DRAM_TIMING_TABLE_68[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_68)/sizeof(ixMCARB_DRAM_TIMING_TABLE_68[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_69", REG_SMC, 0x3fa10, &ixMCARB_DRAM_TIMING_TABLE_69[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_69)/sizeof(ixMCARB_DRAM_TIMING_TABLE_69[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_70", REG_SMC, 0x3fa14, &ixMCARB_DRAM_TIMING_TABLE_70[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_70)/sizeof(ixMCARB_DRAM_TIMING_TABLE_70[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_71", REG_SMC, 0x3fa18, &ixMCARB_DRAM_TIMING_TABLE_71[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_71)/sizeof(ixMCARB_DRAM_TIMING_TABLE_71[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_72", REG_SMC, 0x3fa1c, &ixMCARB_DRAM_TIMING_TABLE_72[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_72)/sizeof(ixMCARB_DRAM_TIMING_TABLE_72[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_73", REG_SMC, 0x3fa20, &ixMCARB_DRAM_TIMING_TABLE_73[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_73)/sizeof(ixMCARB_DRAM_TIMING_TABLE_73[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_74", REG_SMC, 0x3fa24, &ixMCARB_DRAM_TIMING_TABLE_74[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_74)/sizeof(ixMCARB_DRAM_TIMING_TABLE_74[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_75", REG_SMC, 0x3fa28, &ixMCARB_DRAM_TIMING_TABLE_75[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_75)/sizeof(ixMCARB_DRAM_TIMING_TABLE_75[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_76", REG_SMC, 0x3fa2c, &ixMCARB_DRAM_TIMING_TABLE_76[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_76)/sizeof(ixMCARB_DRAM_TIMING_TABLE_76[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_77", REG_SMC, 0x3fa30, &ixMCARB_DRAM_TIMING_TABLE_77[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_77)/sizeof(ixMCARB_DRAM_TIMING_TABLE_77[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_78", REG_SMC, 0x3fa34, &ixMCARB_DRAM_TIMING_TABLE_78[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_78)/sizeof(ixMCARB_DRAM_TIMING_TABLE_78[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_79", REG_SMC, 0x3fa38, &ixMCARB_DRAM_TIMING_TABLE_79[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_79)/sizeof(ixMCARB_DRAM_TIMING_TABLE_79[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_80", REG_SMC, 0x3fa3c, &ixMCARB_DRAM_TIMING_TABLE_80[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_80)/sizeof(ixMCARB_DRAM_TIMING_TABLE_80[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_81", REG_SMC, 0x3fa40, &ixMCARB_DRAM_TIMING_TABLE_81[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_81)/sizeof(ixMCARB_DRAM_TIMING_TABLE_81[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_82", REG_SMC, 0x3fa44, &ixMCARB_DRAM_TIMING_TABLE_82[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_82)/sizeof(ixMCARB_DRAM_TIMING_TABLE_82[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_83", REG_SMC, 0x3fa48, &ixMCARB_DRAM_TIMING_TABLE_83[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_83)/sizeof(ixMCARB_DRAM_TIMING_TABLE_83[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_84", REG_SMC, 0x3fa4c, &ixMCARB_DRAM_TIMING_TABLE_84[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_84)/sizeof(ixMCARB_DRAM_TIMING_TABLE_84[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_85", REG_SMC, 0x3fa50, &ixMCARB_DRAM_TIMING_TABLE_85[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_85)/sizeof(ixMCARB_DRAM_TIMING_TABLE_85[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_86", REG_SMC, 0x3fa54, &ixMCARB_DRAM_TIMING_TABLE_86[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_86)/sizeof(ixMCARB_DRAM_TIMING_TABLE_86[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_87", REG_SMC, 0x3fa58, &ixMCARB_DRAM_TIMING_TABLE_87[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_87)/sizeof(ixMCARB_DRAM_TIMING_TABLE_87[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_88", REG_SMC, 0x3fa5c, &ixMCARB_DRAM_TIMING_TABLE_88[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_88)/sizeof(ixMCARB_DRAM_TIMING_TABLE_88[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_89", REG_SMC, 0x3fa60, &ixMCARB_DRAM_TIMING_TABLE_89[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_89)/sizeof(ixMCARB_DRAM_TIMING_TABLE_89[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_90", REG_SMC, 0x3fa64, &ixMCARB_DRAM_TIMING_TABLE_90[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_90)/sizeof(ixMCARB_DRAM_TIMING_TABLE_90[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_91", REG_SMC, 0x3fa68, &ixMCARB_DRAM_TIMING_TABLE_91[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_91)/sizeof(ixMCARB_DRAM_TIMING_TABLE_91[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_92", REG_SMC, 0x3fa6c, &ixMCARB_DRAM_TIMING_TABLE_92[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_92)/sizeof(ixMCARB_DRAM_TIMING_TABLE_92[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_93", REG_SMC, 0x3fa70, &ixMCARB_DRAM_TIMING_TABLE_93[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_93)/sizeof(ixMCARB_DRAM_TIMING_TABLE_93[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_94", REG_SMC, 0x3fa74, &ixMCARB_DRAM_TIMING_TABLE_94[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_94)/sizeof(ixMCARB_DRAM_TIMING_TABLE_94[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_95", REG_SMC, 0x3fa78, &ixMCARB_DRAM_TIMING_TABLE_95[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_95)/sizeof(ixMCARB_DRAM_TIMING_TABLE_95[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_96", REG_SMC, 0x3fa7c, &ixMCARB_DRAM_TIMING_TABLE_96[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_96)/sizeof(ixMCARB_DRAM_TIMING_TABLE_96[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_97", REG_SMC, 0x3fa80, &ixMCARB_DRAM_TIMING_TABLE_97[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_97)/sizeof(ixMCARB_DRAM_TIMING_TABLE_97[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_98", REG_SMC, 0x3fa84, &ixMCARB_DRAM_TIMING_TABLE_98[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_98)/sizeof(ixMCARB_DRAM_TIMING_TABLE_98[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_99", REG_SMC, 0x3fa88, &ixMCARB_DRAM_TIMING_TABLE_99[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_99)/sizeof(ixMCARB_DRAM_TIMING_TABLE_99[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_100", REG_SMC, 0x3fa8c, &ixMCARB_DRAM_TIMING_TABLE_100[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_100)/sizeof(ixMCARB_DRAM_TIMING_TABLE_100[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_101", REG_SMC, 0x3fa90, &ixMCARB_DRAM_TIMING_TABLE_101[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_101)/sizeof(ixMCARB_DRAM_TIMING_TABLE_101[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_102", REG_SMC, 0x3fa94, &ixMCARB_DRAM_TIMING_TABLE_102[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_102)/sizeof(ixMCARB_DRAM_TIMING_TABLE_102[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_103", REG_SMC, 0x3fa98, &ixMCARB_DRAM_TIMING_TABLE_103[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_103)/sizeof(ixMCARB_DRAM_TIMING_TABLE_103[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_104", REG_SMC, 0x3fa9c, &ixMCARB_DRAM_TIMING_TABLE_104[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_104)/sizeof(ixMCARB_DRAM_TIMING_TABLE_104[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_105", REG_SMC, 0x3faa0, &ixMCARB_DRAM_TIMING_TABLE_105[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_105)/sizeof(ixMCARB_DRAM_TIMING_TABLE_105[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_106", REG_SMC, 0x3faa4, &ixMCARB_DRAM_TIMING_TABLE_106[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_106)/sizeof(ixMCARB_DRAM_TIMING_TABLE_106[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_107", REG_SMC, 0x3faa8, &ixMCARB_DRAM_TIMING_TABLE_107[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_107)/sizeof(ixMCARB_DRAM_TIMING_TABLE_107[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_108", REG_SMC, 0x3faac, &ixMCARB_DRAM_TIMING_TABLE_108[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_108)/sizeof(ixMCARB_DRAM_TIMING_TABLE_108[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_109", REG_SMC, 0x3fab0, &ixMCARB_DRAM_TIMING_TABLE_109[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_109)/sizeof(ixMCARB_DRAM_TIMING_TABLE_109[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_110", REG_SMC, 0x3fab4, &ixMCARB_DRAM_TIMING_TABLE_110[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_110)/sizeof(ixMCARB_DRAM_TIMING_TABLE_110[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_111", REG_SMC, 0x3fab8, &ixMCARB_DRAM_TIMING_TABLE_111[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_111)/sizeof(ixMCARB_DRAM_TIMING_TABLE_111[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_112", REG_SMC, 0x3fabc, &ixMCARB_DRAM_TIMING_TABLE_112[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_112)/sizeof(ixMCARB_DRAM_TIMING_TABLE_112[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_113", REG_SMC, 0x3fac0, &ixMCARB_DRAM_TIMING_TABLE_113[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_113)/sizeof(ixMCARB_DRAM_TIMING_TABLE_113[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_114", REG_SMC, 0x3fac4, &ixMCARB_DRAM_TIMING_TABLE_114[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_114)/sizeof(ixMCARB_DRAM_TIMING_TABLE_114[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_115", REG_SMC, 0x3fac8, &ixMCARB_DRAM_TIMING_TABLE_115[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_115)/sizeof(ixMCARB_DRAM_TIMING_TABLE_115[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_116", REG_SMC, 0x3facc, &ixMCARB_DRAM_TIMING_TABLE_116[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_116)/sizeof(ixMCARB_DRAM_TIMING_TABLE_116[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_117", REG_SMC, 0x3fad0, &ixMCARB_DRAM_TIMING_TABLE_117[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_117)/sizeof(ixMCARB_DRAM_TIMING_TABLE_117[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_118", REG_SMC, 0x3fad4, &ixMCARB_DRAM_TIMING_TABLE_118[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_118)/sizeof(ixMCARB_DRAM_TIMING_TABLE_118[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_119", REG_SMC, 0x3fad8, &ixMCARB_DRAM_TIMING_TABLE_119[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_119)/sizeof(ixMCARB_DRAM_TIMING_TABLE_119[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_120", REG_SMC, 0x3fadc, &ixMCARB_DRAM_TIMING_TABLE_120[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_120)/sizeof(ixMCARB_DRAM_TIMING_TABLE_120[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_121", REG_SMC, 0x3fae0, &ixMCARB_DRAM_TIMING_TABLE_121[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_121)/sizeof(ixMCARB_DRAM_TIMING_TABLE_121[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_122", REG_SMC, 0x3fae4, &ixMCARB_DRAM_TIMING_TABLE_122[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_122)/sizeof(ixMCARB_DRAM_TIMING_TABLE_122[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_123", REG_SMC, 0x3fae8, &ixMCARB_DRAM_TIMING_TABLE_123[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_123)/sizeof(ixMCARB_DRAM_TIMING_TABLE_123[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_124", REG_SMC, 0x3faec, &ixMCARB_DRAM_TIMING_TABLE_124[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_124)/sizeof(ixMCARB_DRAM_TIMING_TABLE_124[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_125", REG_SMC, 0x3faf0, &ixMCARB_DRAM_TIMING_TABLE_125[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_125)/sizeof(ixMCARB_DRAM_TIMING_TABLE_125[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_126", REG_SMC, 0x3faf4, &ixMCARB_DRAM_TIMING_TABLE_126[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_126)/sizeof(ixMCARB_DRAM_TIMING_TABLE_126[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_127", REG_SMC, 0x3faf8, &ixMCARB_DRAM_TIMING_TABLE_127[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_127)/sizeof(ixMCARB_DRAM_TIMING_TABLE_127[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_128", REG_SMC, 0x3fafc, &ixMCARB_DRAM_TIMING_TABLE_128[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_128)/sizeof(ixMCARB_DRAM_TIMING_TABLE_128[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_129", REG_SMC, 0x3fb00, &ixMCARB_DRAM_TIMING_TABLE_129[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_129)/sizeof(ixMCARB_DRAM_TIMING_TABLE_129[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_130", REG_SMC, 0x3fb04, &ixMCARB_DRAM_TIMING_TABLE_130[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_130)/sizeof(ixMCARB_DRAM_TIMING_TABLE_130[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_131", REG_SMC, 0x3fb08, &ixMCARB_DRAM_TIMING_TABLE_131[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_131)/sizeof(ixMCARB_DRAM_TIMING_TABLE_131[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_132", REG_SMC, 0x3fb0c, &ixMCARB_DRAM_TIMING_TABLE_132[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_132)/sizeof(ixMCARB_DRAM_TIMING_TABLE_132[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_133", REG_SMC, 0x3fb10, &ixMCARB_DRAM_TIMING_TABLE_133[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_133)/sizeof(ixMCARB_DRAM_TIMING_TABLE_133[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_134", REG_SMC, 0x3fb14, &ixMCARB_DRAM_TIMING_TABLE_134[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_134)/sizeof(ixMCARB_DRAM_TIMING_TABLE_134[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_135", REG_SMC, 0x3fb18, &ixMCARB_DRAM_TIMING_TABLE_135[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_135)/sizeof(ixMCARB_DRAM_TIMING_TABLE_135[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_136", REG_SMC, 0x3fb1c, &ixMCARB_DRAM_TIMING_TABLE_136[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_136)/sizeof(ixMCARB_DRAM_TIMING_TABLE_136[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_137", REG_SMC, 0x3fb20, &ixMCARB_DRAM_TIMING_TABLE_137[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_137)/sizeof(ixMCARB_DRAM_TIMING_TABLE_137[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_138", REG_SMC, 0x3fb24, &ixMCARB_DRAM_TIMING_TABLE_138[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_138)/sizeof(ixMCARB_DRAM_TIMING_TABLE_138[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_139", REG_SMC, 0x3fb28, &ixMCARB_DRAM_TIMING_TABLE_139[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_139)/sizeof(ixMCARB_DRAM_TIMING_TABLE_139[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_140", REG_SMC, 0x3fb2c, &ixMCARB_DRAM_TIMING_TABLE_140[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_140)/sizeof(ixMCARB_DRAM_TIMING_TABLE_140[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_141", REG_SMC, 0x3fb30, &ixMCARB_DRAM_TIMING_TABLE_141[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_141)/sizeof(ixMCARB_DRAM_TIMING_TABLE_141[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_142", REG_SMC, 0x3fb34, &ixMCARB_DRAM_TIMING_TABLE_142[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_142)/sizeof(ixMCARB_DRAM_TIMING_TABLE_142[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_143", REG_SMC, 0x3fb38, &ixMCARB_DRAM_TIMING_TABLE_143[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_143)/sizeof(ixMCARB_DRAM_TIMING_TABLE_143[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_144", REG_SMC, 0x3fb3c, &ixMCARB_DRAM_TIMING_TABLE_144[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_144)/sizeof(ixMCARB_DRAM_TIMING_TABLE_144[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_1", REG_SMC, 0x3fb40, &ixMC_REGISTERS_TABLE_1[0], sizeof(ixMC_REGISTERS_TABLE_1)/sizeof(ixMC_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_2", REG_SMC, 0x3fb44, &ixMC_REGISTERS_TABLE_2[0], sizeof(ixMC_REGISTERS_TABLE_2)/sizeof(ixMC_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_3", REG_SMC, 0x3fb48, &ixMC_REGISTERS_TABLE_3[0], sizeof(ixMC_REGISTERS_TABLE_3)/sizeof(ixMC_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_4", REG_SMC, 0x3fb4c, &ixMC_REGISTERS_TABLE_4[0], sizeof(ixMC_REGISTERS_TABLE_4)/sizeof(ixMC_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_5", REG_SMC, 0x3fb50, &ixMC_REGISTERS_TABLE_5[0], sizeof(ixMC_REGISTERS_TABLE_5)/sizeof(ixMC_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_6", REG_SMC, 0x3fb54, &ixMC_REGISTERS_TABLE_6[0], sizeof(ixMC_REGISTERS_TABLE_6)/sizeof(ixMC_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_7", REG_SMC, 0x3fb58, &ixMC_REGISTERS_TABLE_7[0], sizeof(ixMC_REGISTERS_TABLE_7)/sizeof(ixMC_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_8", REG_SMC, 0x3fb5c, &ixMC_REGISTERS_TABLE_8[0], sizeof(ixMC_REGISTERS_TABLE_8)/sizeof(ixMC_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_9", REG_SMC, 0x3fb60, &ixMC_REGISTERS_TABLE_9[0], sizeof(ixMC_REGISTERS_TABLE_9)/sizeof(ixMC_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_10", REG_SMC, 0x3fb64, &ixMC_REGISTERS_TABLE_10[0], sizeof(ixMC_REGISTERS_TABLE_10)/sizeof(ixMC_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_11", REG_SMC, 0x3fb68, &ixMC_REGISTERS_TABLE_11[0], sizeof(ixMC_REGISTERS_TABLE_11)/sizeof(ixMC_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_12", REG_SMC, 0x3fb6c, &ixMC_REGISTERS_TABLE_12[0], sizeof(ixMC_REGISTERS_TABLE_12)/sizeof(ixMC_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_13", REG_SMC, 0x3fb70, &ixMC_REGISTERS_TABLE_13[0], sizeof(ixMC_REGISTERS_TABLE_13)/sizeof(ixMC_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_14", REG_SMC, 0x3fb74, &ixMC_REGISTERS_TABLE_14[0], sizeof(ixMC_REGISTERS_TABLE_14)/sizeof(ixMC_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_15", REG_SMC, 0x3fb78, &ixMC_REGISTERS_TABLE_15[0], sizeof(ixMC_REGISTERS_TABLE_15)/sizeof(ixMC_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_16", REG_SMC, 0x3fb7c, &ixMC_REGISTERS_TABLE_16[0], sizeof(ixMC_REGISTERS_TABLE_16)/sizeof(ixMC_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_17", REG_SMC, 0x3fb80, &ixMC_REGISTERS_TABLE_17[0], sizeof(ixMC_REGISTERS_TABLE_17)/sizeof(ixMC_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_18", REG_SMC, 0x3fb84, &ixMC_REGISTERS_TABLE_18[0], sizeof(ixMC_REGISTERS_TABLE_18)/sizeof(ixMC_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_19", REG_SMC, 0x3fb88, &ixMC_REGISTERS_TABLE_19[0], sizeof(ixMC_REGISTERS_TABLE_19)/sizeof(ixMC_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_20", REG_SMC, 0x3fb8c, &ixMC_REGISTERS_TABLE_20[0], sizeof(ixMC_REGISTERS_TABLE_20)/sizeof(ixMC_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_21", REG_SMC, 0x3fb90, &ixMC_REGISTERS_TABLE_21[0], sizeof(ixMC_REGISTERS_TABLE_21)/sizeof(ixMC_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_22", REG_SMC, 0x3fb94, &ixMC_REGISTERS_TABLE_22[0], sizeof(ixMC_REGISTERS_TABLE_22)/sizeof(ixMC_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_23", REG_SMC, 0x3fb98, &ixMC_REGISTERS_TABLE_23[0], sizeof(ixMC_REGISTERS_TABLE_23)/sizeof(ixMC_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_24", REG_SMC, 0x3fb9c, &ixMC_REGISTERS_TABLE_24[0], sizeof(ixMC_REGISTERS_TABLE_24)/sizeof(ixMC_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_25", REG_SMC, 0x3fba0, &ixMC_REGISTERS_TABLE_25[0], sizeof(ixMC_REGISTERS_TABLE_25)/sizeof(ixMC_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_26", REG_SMC, 0x3fba4, &ixMC_REGISTERS_TABLE_26[0], sizeof(ixMC_REGISTERS_TABLE_26)/sizeof(ixMC_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_27", REG_SMC, 0x3fba8, &ixMC_REGISTERS_TABLE_27[0], sizeof(ixMC_REGISTERS_TABLE_27)/sizeof(ixMC_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_28", REG_SMC, 0x3fbac, &ixMC_REGISTERS_TABLE_28[0], sizeof(ixMC_REGISTERS_TABLE_28)/sizeof(ixMC_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_29", REG_SMC, 0x3fbb0, &ixMC_REGISTERS_TABLE_29[0], sizeof(ixMC_REGISTERS_TABLE_29)/sizeof(ixMC_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_30", REG_SMC, 0x3fbb4, &ixMC_REGISTERS_TABLE_30[0], sizeof(ixMC_REGISTERS_TABLE_30)/sizeof(ixMC_REGISTERS_TABLE_30[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_31", REG_SMC, 0x3fbb8, &ixMC_REGISTERS_TABLE_31[0], sizeof(ixMC_REGISTERS_TABLE_31)/sizeof(ixMC_REGISTERS_TABLE_31[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_32", REG_SMC, 0x3fbbc, &ixMC_REGISTERS_TABLE_32[0], sizeof(ixMC_REGISTERS_TABLE_32)/sizeof(ixMC_REGISTERS_TABLE_32[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_33", REG_SMC, 0x3fbc0, &ixMC_REGISTERS_TABLE_33[0], sizeof(ixMC_REGISTERS_TABLE_33)/sizeof(ixMC_REGISTERS_TABLE_33[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_34", REG_SMC, 0x3fbc4, &ixMC_REGISTERS_TABLE_34[0], sizeof(ixMC_REGISTERS_TABLE_34)/sizeof(ixMC_REGISTERS_TABLE_34[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_35", REG_SMC, 0x3fbc8, &ixMC_REGISTERS_TABLE_35[0], sizeof(ixMC_REGISTERS_TABLE_35)/sizeof(ixMC_REGISTERS_TABLE_35[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_36", REG_SMC, 0x3fbcc, &ixMC_REGISTERS_TABLE_36[0], sizeof(ixMC_REGISTERS_TABLE_36)/sizeof(ixMC_REGISTERS_TABLE_36[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_37", REG_SMC, 0x3fbd0, &ixMC_REGISTERS_TABLE_37[0], sizeof(ixMC_REGISTERS_TABLE_37)/sizeof(ixMC_REGISTERS_TABLE_37[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_38", REG_SMC, 0x3fbd4, &ixMC_REGISTERS_TABLE_38[0], sizeof(ixMC_REGISTERS_TABLE_38)/sizeof(ixMC_REGISTERS_TABLE_38[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_39", REG_SMC, 0x3fbd8, &ixMC_REGISTERS_TABLE_39[0], sizeof(ixMC_REGISTERS_TABLE_39)/sizeof(ixMC_REGISTERS_TABLE_39[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_40", REG_SMC, 0x3fbdc, &ixMC_REGISTERS_TABLE_40[0], sizeof(ixMC_REGISTERS_TABLE_40)/sizeof(ixMC_REGISTERS_TABLE_40[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_41", REG_SMC, 0x3fbe0, &ixMC_REGISTERS_TABLE_41[0], sizeof(ixMC_REGISTERS_TABLE_41)/sizeof(ixMC_REGISTERS_TABLE_41[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_42", REG_SMC, 0x3fbe4, &ixMC_REGISTERS_TABLE_42[0], sizeof(ixMC_REGISTERS_TABLE_42)/sizeof(ixMC_REGISTERS_TABLE_42[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_43", REG_SMC, 0x3fbe8, &ixMC_REGISTERS_TABLE_43[0], sizeof(ixMC_REGISTERS_TABLE_43)/sizeof(ixMC_REGISTERS_TABLE_43[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_44", REG_SMC, 0x3fbec, &ixMC_REGISTERS_TABLE_44[0], sizeof(ixMC_REGISTERS_TABLE_44)/sizeof(ixMC_REGISTERS_TABLE_44[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_45", REG_SMC, 0x3fbf0, &ixMC_REGISTERS_TABLE_45[0], sizeof(ixMC_REGISTERS_TABLE_45)/sizeof(ixMC_REGISTERS_TABLE_45[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_46", REG_SMC, 0x3fbf4, &ixMC_REGISTERS_TABLE_46[0], sizeof(ixMC_REGISTERS_TABLE_46)/sizeof(ixMC_REGISTERS_TABLE_46[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_47", REG_SMC, 0x3fbf8, &ixMC_REGISTERS_TABLE_47[0], sizeof(ixMC_REGISTERS_TABLE_47)/sizeof(ixMC_REGISTERS_TABLE_47[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_48", REG_SMC, 0x3fbfc, &ixMC_REGISTERS_TABLE_48[0], sizeof(ixMC_REGISTERS_TABLE_48)/sizeof(ixMC_REGISTERS_TABLE_48[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_49", REG_SMC, 0x3fc00, &ixMC_REGISTERS_TABLE_49[0], sizeof(ixMC_REGISTERS_TABLE_49)/sizeof(ixMC_REGISTERS_TABLE_49[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_50", REG_SMC, 0x3fc04, &ixMC_REGISTERS_TABLE_50[0], sizeof(ixMC_REGISTERS_TABLE_50)/sizeof(ixMC_REGISTERS_TABLE_50[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_51", REG_SMC, 0x3fc08, &ixMC_REGISTERS_TABLE_51[0], sizeof(ixMC_REGISTERS_TABLE_51)/sizeof(ixMC_REGISTERS_TABLE_51[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_52", REG_SMC, 0x3fc0c, &ixMC_REGISTERS_TABLE_52[0], sizeof(ixMC_REGISTERS_TABLE_52)/sizeof(ixMC_REGISTERS_TABLE_52[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_53", REG_SMC, 0x3fc10, &ixMC_REGISTERS_TABLE_53[0], sizeof(ixMC_REGISTERS_TABLE_53)/sizeof(ixMC_REGISTERS_TABLE_53[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_54", REG_SMC, 0x3fc14, &ixMC_REGISTERS_TABLE_54[0], sizeof(ixMC_REGISTERS_TABLE_54)/sizeof(ixMC_REGISTERS_TABLE_54[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_55", REG_SMC, 0x3fc18, &ixMC_REGISTERS_TABLE_55[0], sizeof(ixMC_REGISTERS_TABLE_55)/sizeof(ixMC_REGISTERS_TABLE_55[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_56", REG_SMC, 0x3fc1c, &ixMC_REGISTERS_TABLE_56[0], sizeof(ixMC_REGISTERS_TABLE_56)/sizeof(ixMC_REGISTERS_TABLE_56[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_57", REG_SMC, 0x3fc20, &ixMC_REGISTERS_TABLE_57[0], sizeof(ixMC_REGISTERS_TABLE_57)/sizeof(ixMC_REGISTERS_TABLE_57[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_58", REG_SMC, 0x3fc24, &ixMC_REGISTERS_TABLE_58[0], sizeof(ixMC_REGISTERS_TABLE_58)/sizeof(ixMC_REGISTERS_TABLE_58[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_59", REG_SMC, 0x3fc28, &ixMC_REGISTERS_TABLE_59[0], sizeof(ixMC_REGISTERS_TABLE_59)/sizeof(ixMC_REGISTERS_TABLE_59[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_60", REG_SMC, 0x3fc2c, &ixMC_REGISTERS_TABLE_60[0], sizeof(ixMC_REGISTERS_TABLE_60)/sizeof(ixMC_REGISTERS_TABLE_60[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_61", REG_SMC, 0x3fc30, &ixMC_REGISTERS_TABLE_61[0], sizeof(ixMC_REGISTERS_TABLE_61)/sizeof(ixMC_REGISTERS_TABLE_61[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_62", REG_SMC, 0x3fc34, &ixMC_REGISTERS_TABLE_62[0], sizeof(ixMC_REGISTERS_TABLE_62)/sizeof(ixMC_REGISTERS_TABLE_62[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_63", REG_SMC, 0x3fc38, &ixMC_REGISTERS_TABLE_63[0], sizeof(ixMC_REGISTERS_TABLE_63)/sizeof(ixMC_REGISTERS_TABLE_63[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_64", REG_SMC, 0x3fc3c, &ixMC_REGISTERS_TABLE_64[0], sizeof(ixMC_REGISTERS_TABLE_64)/sizeof(ixMC_REGISTERS_TABLE_64[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_65", REG_SMC, 0x3fc40, &ixMC_REGISTERS_TABLE_65[0], sizeof(ixMC_REGISTERS_TABLE_65)/sizeof(ixMC_REGISTERS_TABLE_65[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_66", REG_SMC, 0x3fc44, &ixMC_REGISTERS_TABLE_66[0], sizeof(ixMC_REGISTERS_TABLE_66)/sizeof(ixMC_REGISTERS_TABLE_66[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_67", REG_SMC, 0x3fc48, &ixMC_REGISTERS_TABLE_67[0], sizeof(ixMC_REGISTERS_TABLE_67)/sizeof(ixMC_REGISTERS_TABLE_67[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_68", REG_SMC, 0x3fc4c, &ixMC_REGISTERS_TABLE_68[0], sizeof(ixMC_REGISTERS_TABLE_68)/sizeof(ixMC_REGISTERS_TABLE_68[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_69", REG_SMC, 0x3fc50, &ixMC_REGISTERS_TABLE_69[0], sizeof(ixMC_REGISTERS_TABLE_69)/sizeof(ixMC_REGISTERS_TABLE_69[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_70", REG_SMC, 0x3fc54, &ixMC_REGISTERS_TABLE_70[0], sizeof(ixMC_REGISTERS_TABLE_70)/sizeof(ixMC_REGISTERS_TABLE_70[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_71", REG_SMC, 0x3fc58, &ixMC_REGISTERS_TABLE_71[0], sizeof(ixMC_REGISTERS_TABLE_71)/sizeof(ixMC_REGISTERS_TABLE_71[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_72", REG_SMC, 0x3fc5c, &ixMC_REGISTERS_TABLE_72[0], sizeof(ixMC_REGISTERS_TABLE_72)/sizeof(ixMC_REGISTERS_TABLE_72[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_73", REG_SMC, 0x3fc60, &ixMC_REGISTERS_TABLE_73[0], sizeof(ixMC_REGISTERS_TABLE_73)/sizeof(ixMC_REGISTERS_TABLE_73[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_74", REG_SMC, 0x3fc64, &ixMC_REGISTERS_TABLE_74[0], sizeof(ixMC_REGISTERS_TABLE_74)/sizeof(ixMC_REGISTERS_TABLE_74[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_75", REG_SMC, 0x3fc68, &ixMC_REGISTERS_TABLE_75[0], sizeof(ixMC_REGISTERS_TABLE_75)/sizeof(ixMC_REGISTERS_TABLE_75[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_76", REG_SMC, 0x3fc6c, &ixMC_REGISTERS_TABLE_76[0], sizeof(ixMC_REGISTERS_TABLE_76)/sizeof(ixMC_REGISTERS_TABLE_76[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_77", REG_SMC, 0x3fc70, &ixMC_REGISTERS_TABLE_77[0], sizeof(ixMC_REGISTERS_TABLE_77)/sizeof(ixMC_REGISTERS_TABLE_77[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_78", REG_SMC, 0x3fc74, &ixMC_REGISTERS_TABLE_78[0], sizeof(ixMC_REGISTERS_TABLE_78)/sizeof(ixMC_REGISTERS_TABLE_78[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_79", REG_SMC, 0x3fc78, &ixMC_REGISTERS_TABLE_79[0], sizeof(ixMC_REGISTERS_TABLE_79)/sizeof(ixMC_REGISTERS_TABLE_79[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_80", REG_SMC, 0x3fc7c, &ixMC_REGISTERS_TABLE_80[0], sizeof(ixMC_REGISTERS_TABLE_80)/sizeof(ixMC_REGISTERS_TABLE_80[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_81", REG_SMC, 0x3fc80, &ixMC_REGISTERS_TABLE_81[0], sizeof(ixMC_REGISTERS_TABLE_81)/sizeof(ixMC_REGISTERS_TABLE_81[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_82", REG_SMC, 0x3fc84, &ixMC_REGISTERS_TABLE_82[0], sizeof(ixMC_REGISTERS_TABLE_82)/sizeof(ixMC_REGISTERS_TABLE_82[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_83", REG_SMC, 0x3fc88, &ixMC_REGISTERS_TABLE_83[0], sizeof(ixMC_REGISTERS_TABLE_83)/sizeof(ixMC_REGISTERS_TABLE_83[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_84", REG_SMC, 0x3fc8c, &ixMC_REGISTERS_TABLE_84[0], sizeof(ixMC_REGISTERS_TABLE_84)/sizeof(ixMC_REGISTERS_TABLE_84[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_85", REG_SMC, 0x3fc90, &ixMC_REGISTERS_TABLE_85[0], sizeof(ixMC_REGISTERS_TABLE_85)/sizeof(ixMC_REGISTERS_TABLE_85[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_86", REG_SMC, 0x3fc94, &ixMC_REGISTERS_TABLE_86[0], sizeof(ixMC_REGISTERS_TABLE_86)/sizeof(ixMC_REGISTERS_TABLE_86[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_87", REG_SMC, 0x3fc98, &ixMC_REGISTERS_TABLE_87[0], sizeof(ixMC_REGISTERS_TABLE_87)/sizeof(ixMC_REGISTERS_TABLE_87[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_88", REG_SMC, 0x3fc9c, &ixMC_REGISTERS_TABLE_88[0], sizeof(ixMC_REGISTERS_TABLE_88)/sizeof(ixMC_REGISTERS_TABLE_88[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_89", REG_SMC, 0x3fca0, &ixMC_REGISTERS_TABLE_89[0], sizeof(ixMC_REGISTERS_TABLE_89)/sizeof(ixMC_REGISTERS_TABLE_89[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_90", REG_SMC, 0x3fca4, &ixMC_REGISTERS_TABLE_90[0], sizeof(ixMC_REGISTERS_TABLE_90)/sizeof(ixMC_REGISTERS_TABLE_90[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_91", REG_SMC, 0x3fca8, &ixMC_REGISTERS_TABLE_91[0], sizeof(ixMC_REGISTERS_TABLE_91)/sizeof(ixMC_REGISTERS_TABLE_91[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_92", REG_SMC, 0x3fcac, &ixMC_REGISTERS_TABLE_92[0], sizeof(ixMC_REGISTERS_TABLE_92)/sizeof(ixMC_REGISTERS_TABLE_92[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_93", REG_SMC, 0x3fcb0, &ixMC_REGISTERS_TABLE_93[0], sizeof(ixMC_REGISTERS_TABLE_93)/sizeof(ixMC_REGISTERS_TABLE_93[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_94", REG_SMC, 0x3fcb4, &ixMC_REGISTERS_TABLE_94[0], sizeof(ixMC_REGISTERS_TABLE_94)/sizeof(ixMC_REGISTERS_TABLE_94[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_95", REG_SMC, 0x3fcb8, &ixMC_REGISTERS_TABLE_95[0], sizeof(ixMC_REGISTERS_TABLE_95)/sizeof(ixMC_REGISTERS_TABLE_95[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_96", REG_SMC, 0x3fcbc, &ixMC_REGISTERS_TABLE_96[0], sizeof(ixMC_REGISTERS_TABLE_96)/sizeof(ixMC_REGISTERS_TABLE_96[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_97", REG_SMC, 0x3fcc0, &ixMC_REGISTERS_TABLE_97[0], sizeof(ixMC_REGISTERS_TABLE_97)/sizeof(ixMC_REGISTERS_TABLE_97[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_98", REG_SMC, 0x3fcc4, &ixMC_REGISTERS_TABLE_98[0], sizeof(ixMC_REGISTERS_TABLE_98)/sizeof(ixMC_REGISTERS_TABLE_98[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_99", REG_SMC, 0x3fcc8, &ixMC_REGISTERS_TABLE_99[0], sizeof(ixMC_REGISTERS_TABLE_99)/sizeof(ixMC_REGISTERS_TABLE_99[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_100", REG_SMC, 0x3fccc, &ixMC_REGISTERS_TABLE_100[0], sizeof(ixMC_REGISTERS_TABLE_100)/sizeof(ixMC_REGISTERS_TABLE_100[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_101", REG_SMC, 0x3fcd0, &ixMC_REGISTERS_TABLE_101[0], sizeof(ixMC_REGISTERS_TABLE_101)/sizeof(ixMC_REGISTERS_TABLE_101[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_102", REG_SMC, 0x3fcd4, &ixMC_REGISTERS_TABLE_102[0], sizeof(ixMC_REGISTERS_TABLE_102)/sizeof(ixMC_REGISTERS_TABLE_102[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_103", REG_SMC, 0x3fcd8, &ixMC_REGISTERS_TABLE_103[0], sizeof(ixMC_REGISTERS_TABLE_103)/sizeof(ixMC_REGISTERS_TABLE_103[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_104", REG_SMC, 0x3fcdc, &ixMC_REGISTERS_TABLE_104[0], sizeof(ixMC_REGISTERS_TABLE_104)/sizeof(ixMC_REGISTERS_TABLE_104[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_105", REG_SMC, 0x3fce0, &ixMC_REGISTERS_TABLE_105[0], sizeof(ixMC_REGISTERS_TABLE_105)/sizeof(ixMC_REGISTERS_TABLE_105[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_106", REG_SMC, 0x3fce4, &ixMC_REGISTERS_TABLE_106[0], sizeof(ixMC_REGISTERS_TABLE_106)/sizeof(ixMC_REGISTERS_TABLE_106[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_107", REG_SMC, 0x3fce8, &ixMC_REGISTERS_TABLE_107[0], sizeof(ixMC_REGISTERS_TABLE_107)/sizeof(ixMC_REGISTERS_TABLE_107[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_108", REG_SMC, 0x3fcec, &ixMC_REGISTERS_TABLE_108[0], sizeof(ixMC_REGISTERS_TABLE_108)/sizeof(ixMC_REGISTERS_TABLE_108[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_109", REG_SMC, 0x3fcf0, &ixMC_REGISTERS_TABLE_109[0], sizeof(ixMC_REGISTERS_TABLE_109)/sizeof(ixMC_REGISTERS_TABLE_109[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_110", REG_SMC, 0x3fcf4, &ixMC_REGISTERS_TABLE_110[0], sizeof(ixMC_REGISTERS_TABLE_110)/sizeof(ixMC_REGISTERS_TABLE_110[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_111", REG_SMC, 0x3fcf8, &ixMC_REGISTERS_TABLE_111[0], sizeof(ixMC_REGISTERS_TABLE_111)/sizeof(ixMC_REGISTERS_TABLE_111[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_112", REG_SMC, 0x3fcfc, &ixMC_REGISTERS_TABLE_112[0], sizeof(ixMC_REGISTERS_TABLE_112)/sizeof(ixMC_REGISTERS_TABLE_112[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_113", REG_SMC, 0x3fd00, &ixMC_REGISTERS_TABLE_113[0], sizeof(ixMC_REGISTERS_TABLE_113)/sizeof(ixMC_REGISTERS_TABLE_113[0]), 0, 0 },
+	{ "ixFAN_TABLE_1", REG_SMC, 0x3fd04, &ixFAN_TABLE_1[0], sizeof(ixFAN_TABLE_1)/sizeof(ixFAN_TABLE_1[0]), 0, 0 },
+	{ "ixFAN_TABLE_2", REG_SMC, 0x3fd08, &ixFAN_TABLE_2[0], sizeof(ixFAN_TABLE_2)/sizeof(ixFAN_TABLE_2[0]), 0, 0 },
+	{ "ixFAN_TABLE_3", REG_SMC, 0x3fd0c, &ixFAN_TABLE_3[0], sizeof(ixFAN_TABLE_3)/sizeof(ixFAN_TABLE_3[0]), 0, 0 },
+	{ "ixFAN_TABLE_4", REG_SMC, 0x3fd10, &ixFAN_TABLE_4[0], sizeof(ixFAN_TABLE_4)/sizeof(ixFAN_TABLE_4[0]), 0, 0 },
+	{ "ixFAN_TABLE_5", REG_SMC, 0x3fd14, &ixFAN_TABLE_5[0], sizeof(ixFAN_TABLE_5)/sizeof(ixFAN_TABLE_5[0]), 0, 0 },
+	{ "ixFAN_TABLE_6", REG_SMC, 0x3fd18, &ixFAN_TABLE_6[0], sizeof(ixFAN_TABLE_6)/sizeof(ixFAN_TABLE_6[0]), 0, 0 },
+	{ "ixFAN_TABLE_7", REG_SMC, 0x3fd1c, &ixFAN_TABLE_7[0], sizeof(ixFAN_TABLE_7)/sizeof(ixFAN_TABLE_7[0]), 0, 0 },
+	{ "ixFAN_TABLE_8", REG_SMC, 0x3fd20, &ixFAN_TABLE_8[0], sizeof(ixFAN_TABLE_8)/sizeof(ixFAN_TABLE_8[0]), 0, 0 },
+	{ "ixFAN_TABLE_9", REG_SMC, 0x3fd24, &ixFAN_TABLE_9[0], sizeof(ixFAN_TABLE_9)/sizeof(ixFAN_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_1", REG_SMC, 0x3fd28, &ixSOFT_REGISTERS_TABLE_1[0], sizeof(ixSOFT_REGISTERS_TABLE_1)/sizeof(ixSOFT_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_2", REG_SMC, 0x3fd2c, &ixSOFT_REGISTERS_TABLE_2[0], sizeof(ixSOFT_REGISTERS_TABLE_2)/sizeof(ixSOFT_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_3", REG_SMC, 0x3fd30, &ixSOFT_REGISTERS_TABLE_3[0], sizeof(ixSOFT_REGISTERS_TABLE_3)/sizeof(ixSOFT_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_4", REG_SMC, 0x3fd34, &ixSOFT_REGISTERS_TABLE_4[0], sizeof(ixSOFT_REGISTERS_TABLE_4)/sizeof(ixSOFT_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_5", REG_SMC, 0x3fd38, &ixSOFT_REGISTERS_TABLE_5[0], sizeof(ixSOFT_REGISTERS_TABLE_5)/sizeof(ixSOFT_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_6", REG_SMC, 0x3fd3c, &ixSOFT_REGISTERS_TABLE_6[0], sizeof(ixSOFT_REGISTERS_TABLE_6)/sizeof(ixSOFT_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_7", REG_SMC, 0x3fd40, &ixSOFT_REGISTERS_TABLE_7[0], sizeof(ixSOFT_REGISTERS_TABLE_7)/sizeof(ixSOFT_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_8", REG_SMC, 0x3fd44, &ixSOFT_REGISTERS_TABLE_8[0], sizeof(ixSOFT_REGISTERS_TABLE_8)/sizeof(ixSOFT_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_9", REG_SMC, 0x3fd48, &ixSOFT_REGISTERS_TABLE_9[0], sizeof(ixSOFT_REGISTERS_TABLE_9)/sizeof(ixSOFT_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_10", REG_SMC, 0x3fd4c, &ixSOFT_REGISTERS_TABLE_10[0], sizeof(ixSOFT_REGISTERS_TABLE_10)/sizeof(ixSOFT_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_11", REG_SMC, 0x3fd50, &ixSOFT_REGISTERS_TABLE_11[0], sizeof(ixSOFT_REGISTERS_TABLE_11)/sizeof(ixSOFT_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_12", REG_SMC, 0x3fd54, &ixSOFT_REGISTERS_TABLE_12[0], sizeof(ixSOFT_REGISTERS_TABLE_12)/sizeof(ixSOFT_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_13", REG_SMC, 0x3fd58, &ixSOFT_REGISTERS_TABLE_13[0], sizeof(ixSOFT_REGISTERS_TABLE_13)/sizeof(ixSOFT_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_14", REG_SMC, 0x3fd5c, &ixSOFT_REGISTERS_TABLE_14[0], sizeof(ixSOFT_REGISTERS_TABLE_14)/sizeof(ixSOFT_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_15", REG_SMC, 0x3fd60, &ixSOFT_REGISTERS_TABLE_15[0], sizeof(ixSOFT_REGISTERS_TABLE_15)/sizeof(ixSOFT_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_16", REG_SMC, 0x3fd64, &ixSOFT_REGISTERS_TABLE_16[0], sizeof(ixSOFT_REGISTERS_TABLE_16)/sizeof(ixSOFT_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_17", REG_SMC, 0x3fd68, &ixSOFT_REGISTERS_TABLE_17[0], sizeof(ixSOFT_REGISTERS_TABLE_17)/sizeof(ixSOFT_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_18", REG_SMC, 0x3fd6c, &ixSOFT_REGISTERS_TABLE_18[0], sizeof(ixSOFT_REGISTERS_TABLE_18)/sizeof(ixSOFT_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_19", REG_SMC, 0x3fd70, &ixSOFT_REGISTERS_TABLE_19[0], sizeof(ixSOFT_REGISTERS_TABLE_19)/sizeof(ixSOFT_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_20", REG_SMC, 0x3fd74, &ixSOFT_REGISTERS_TABLE_20[0], sizeof(ixSOFT_REGISTERS_TABLE_20)/sizeof(ixSOFT_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_21", REG_SMC, 0x3fd78, &ixSOFT_REGISTERS_TABLE_21[0], sizeof(ixSOFT_REGISTERS_TABLE_21)/sizeof(ixSOFT_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_22", REG_SMC, 0x3fd7c, &ixSOFT_REGISTERS_TABLE_22[0], sizeof(ixSOFT_REGISTERS_TABLE_22)/sizeof(ixSOFT_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_23", REG_SMC, 0x3fd80, &ixSOFT_REGISTERS_TABLE_23[0], sizeof(ixSOFT_REGISTERS_TABLE_23)/sizeof(ixSOFT_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_24", REG_SMC, 0x3fd84, &ixSOFT_REGISTERS_TABLE_24[0], sizeof(ixSOFT_REGISTERS_TABLE_24)/sizeof(ixSOFT_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_25", REG_SMC, 0x3fd88, &ixSOFT_REGISTERS_TABLE_25[0], sizeof(ixSOFT_REGISTERS_TABLE_25)/sizeof(ixSOFT_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_26", REG_SMC, 0x3fd8c, &ixSOFT_REGISTERS_TABLE_26[0], sizeof(ixSOFT_REGISTERS_TABLE_26)/sizeof(ixSOFT_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_27", REG_SMC, 0x3fd90, &ixSOFT_REGISTERS_TABLE_27[0], sizeof(ixSOFT_REGISTERS_TABLE_27)/sizeof(ixSOFT_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_28", REG_SMC, 0x3fd94, &ixSOFT_REGISTERS_TABLE_28[0], sizeof(ixSOFT_REGISTERS_TABLE_28)/sizeof(ixSOFT_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_29", REG_SMC, 0x3fd98, &ixSOFT_REGISTERS_TABLE_29[0], sizeof(ixSOFT_REGISTERS_TABLE_29)/sizeof(ixSOFT_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_30", REG_SMC, 0x3fd9c, &ixSOFT_REGISTERS_TABLE_30[0], sizeof(ixSOFT_REGISTERS_TABLE_30)/sizeof(ixSOFT_REGISTERS_TABLE_30[0]), 0, 0 },
+	{ "ixPM_FUSES_1", REG_SMC, 0x3fda0, &ixPM_FUSES_1[0], sizeof(ixPM_FUSES_1)/sizeof(ixPM_FUSES_1[0]), 0, 0 },
+	{ "ixPM_FUSES_2", REG_SMC, 0x3fda4, &ixPM_FUSES_2[0], sizeof(ixPM_FUSES_2)/sizeof(ixPM_FUSES_2[0]), 0, 0 },
+	{ "ixPM_FUSES_3", REG_SMC, 0x3fda8, &ixPM_FUSES_3[0], sizeof(ixPM_FUSES_3)/sizeof(ixPM_FUSES_3[0]), 0, 0 },
+	{ "ixPM_FUSES_4", REG_SMC, 0x3fdac, &ixPM_FUSES_4[0], sizeof(ixPM_FUSES_4)/sizeof(ixPM_FUSES_4[0]), 0, 0 },
+	{ "ixPM_FUSES_5", REG_SMC, 0x3fdb0, &ixPM_FUSES_5[0], sizeof(ixPM_FUSES_5)/sizeof(ixPM_FUSES_5[0]), 0, 0 },
+	{ "ixPM_FUSES_6", REG_SMC, 0x3fdb4, &ixPM_FUSES_6[0], sizeof(ixPM_FUSES_6)/sizeof(ixPM_FUSES_6[0]), 0, 0 },
+	{ "ixPM_FUSES_7", REG_SMC, 0x3fdb8, &ixPM_FUSES_7[0], sizeof(ixPM_FUSES_7)/sizeof(ixPM_FUSES_7[0]), 0, 0 },
+	{ "ixPM_FUSES_8", REG_SMC, 0x3fdbc, &ixPM_FUSES_8[0], sizeof(ixPM_FUSES_8)/sizeof(ixPM_FUSES_8[0]), 0, 0 },
+	{ "ixPM_FUSES_9", REG_SMC, 0x3fdc0, &ixPM_FUSES_9[0], sizeof(ixPM_FUSES_9)/sizeof(ixPM_FUSES_9[0]), 0, 0 },
+	{ "ixPM_FUSES_10", REG_SMC, 0x3fdc4, &ixPM_FUSES_10[0], sizeof(ixPM_FUSES_10)/sizeof(ixPM_FUSES_10[0]), 0, 0 },
+	{ "ixPM_FUSES_11", REG_SMC, 0x3fdc8, &ixPM_FUSES_11[0], sizeof(ixPM_FUSES_11)/sizeof(ixPM_FUSES_11[0]), 0, 0 },
+	{ "ixPM_FUSES_12", REG_SMC, 0x3fdcc, &ixPM_FUSES_12[0], sizeof(ixPM_FUSES_12)/sizeof(ixPM_FUSES_12[0]), 0, 0 },
+	{ "ixPM_FUSES_13", REG_SMC, 0x3fdd0, &ixPM_FUSES_13[0], sizeof(ixPM_FUSES_13)/sizeof(ixPM_FUSES_13[0]), 0, 0 },
+	{ "ixPM_FUSES_14", REG_SMC, 0x3fdd4, &ixPM_FUSES_14[0], sizeof(ixPM_FUSES_14)/sizeof(ixPM_FUSES_14[0]), 0, 0 },
+	{ "ixPM_FUSES_15", REG_SMC, 0x3fdd8, &ixPM_FUSES_15[0], sizeof(ixPM_FUSES_15)/sizeof(ixPM_FUSES_15[0]), 0, 0 },
+	{ "ixPM_FUSES_16", REG_SMC, 0x3fddc, &ixPM_FUSES_16[0], sizeof(ixPM_FUSES_16)/sizeof(ixPM_FUSES_16[0]), 0, 0 },
+	{ "ixPM_FUSES_17", REG_SMC, 0x3fde0, &ixPM_FUSES_17[0], sizeof(ixPM_FUSES_17)/sizeof(ixPM_FUSES_17[0]), 0, 0 },
+	{ "ixPM_FUSES_18", REG_SMC, 0x3fde4, &ixPM_FUSES_18[0], sizeof(ixPM_FUSES_18)/sizeof(ixPM_FUSES_18[0]), 0, 0 },
+	{ "ixPM_FUSES_19", REG_SMC, 0x3fde8, &ixPM_FUSES_19[0], sizeof(ixPM_FUSES_19)/sizeof(ixPM_FUSES_19[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_0", REG_SMC, 0x3fe00, &ixSMU_PM_STATUS_0[0], sizeof(ixSMU_PM_STATUS_0)/sizeof(ixSMU_PM_STATUS_0[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_1", REG_SMC, 0x3fe04, &ixSMU_PM_STATUS_1[0], sizeof(ixSMU_PM_STATUS_1)/sizeof(ixSMU_PM_STATUS_1[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_2", REG_SMC, 0x3fe08, &ixSMU_PM_STATUS_2[0], sizeof(ixSMU_PM_STATUS_2)/sizeof(ixSMU_PM_STATUS_2[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_3", REG_SMC, 0x3fe0c, &ixSMU_PM_STATUS_3[0], sizeof(ixSMU_PM_STATUS_3)/sizeof(ixSMU_PM_STATUS_3[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_4", REG_SMC, 0x3fe10, &ixSMU_PM_STATUS_4[0], sizeof(ixSMU_PM_STATUS_4)/sizeof(ixSMU_PM_STATUS_4[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_5", REG_SMC, 0x3fe14, &ixSMU_PM_STATUS_5[0], sizeof(ixSMU_PM_STATUS_5)/sizeof(ixSMU_PM_STATUS_5[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_6", REG_SMC, 0x3fe18, &ixSMU_PM_STATUS_6[0], sizeof(ixSMU_PM_STATUS_6)/sizeof(ixSMU_PM_STATUS_6[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_7", REG_SMC, 0x3fe1c, &ixSMU_PM_STATUS_7[0], sizeof(ixSMU_PM_STATUS_7)/sizeof(ixSMU_PM_STATUS_7[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_8", REG_SMC, 0x3fe20, &ixSMU_PM_STATUS_8[0], sizeof(ixSMU_PM_STATUS_8)/sizeof(ixSMU_PM_STATUS_8[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_9", REG_SMC, 0x3fe24, &ixSMU_PM_STATUS_9[0], sizeof(ixSMU_PM_STATUS_9)/sizeof(ixSMU_PM_STATUS_9[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_10", REG_SMC, 0x3fe28, &ixSMU_PM_STATUS_10[0], sizeof(ixSMU_PM_STATUS_10)/sizeof(ixSMU_PM_STATUS_10[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_11", REG_SMC, 0x3fe2c, &ixSMU_PM_STATUS_11[0], sizeof(ixSMU_PM_STATUS_11)/sizeof(ixSMU_PM_STATUS_11[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_12", REG_SMC, 0x3fe30, &ixSMU_PM_STATUS_12[0], sizeof(ixSMU_PM_STATUS_12)/sizeof(ixSMU_PM_STATUS_12[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_13", REG_SMC, 0x3fe34, &ixSMU_PM_STATUS_13[0], sizeof(ixSMU_PM_STATUS_13)/sizeof(ixSMU_PM_STATUS_13[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_14", REG_SMC, 0x3fe38, &ixSMU_PM_STATUS_14[0], sizeof(ixSMU_PM_STATUS_14)/sizeof(ixSMU_PM_STATUS_14[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_15", REG_SMC, 0x3fe3c, &ixSMU_PM_STATUS_15[0], sizeof(ixSMU_PM_STATUS_15)/sizeof(ixSMU_PM_STATUS_15[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_16", REG_SMC, 0x3fe40, &ixSMU_PM_STATUS_16[0], sizeof(ixSMU_PM_STATUS_16)/sizeof(ixSMU_PM_STATUS_16[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_17", REG_SMC, 0x3fe44, &ixSMU_PM_STATUS_17[0], sizeof(ixSMU_PM_STATUS_17)/sizeof(ixSMU_PM_STATUS_17[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_18", REG_SMC, 0x3fe48, &ixSMU_PM_STATUS_18[0], sizeof(ixSMU_PM_STATUS_18)/sizeof(ixSMU_PM_STATUS_18[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_19", REG_SMC, 0x3fe4c, &ixSMU_PM_STATUS_19[0], sizeof(ixSMU_PM_STATUS_19)/sizeof(ixSMU_PM_STATUS_19[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_20", REG_SMC, 0x3fe50, &ixSMU_PM_STATUS_20[0], sizeof(ixSMU_PM_STATUS_20)/sizeof(ixSMU_PM_STATUS_20[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_21", REG_SMC, 0x3fe54, &ixSMU_PM_STATUS_21[0], sizeof(ixSMU_PM_STATUS_21)/sizeof(ixSMU_PM_STATUS_21[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_22", REG_SMC, 0x3fe58, &ixSMU_PM_STATUS_22[0], sizeof(ixSMU_PM_STATUS_22)/sizeof(ixSMU_PM_STATUS_22[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_23", REG_SMC, 0x3fe5c, &ixSMU_PM_STATUS_23[0], sizeof(ixSMU_PM_STATUS_23)/sizeof(ixSMU_PM_STATUS_23[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_24", REG_SMC, 0x3fe60, &ixSMU_PM_STATUS_24[0], sizeof(ixSMU_PM_STATUS_24)/sizeof(ixSMU_PM_STATUS_24[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_25", REG_SMC, 0x3fe64, &ixSMU_PM_STATUS_25[0], sizeof(ixSMU_PM_STATUS_25)/sizeof(ixSMU_PM_STATUS_25[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_26", REG_SMC, 0x3fe68, &ixSMU_PM_STATUS_26[0], sizeof(ixSMU_PM_STATUS_26)/sizeof(ixSMU_PM_STATUS_26[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_27", REG_SMC, 0x3fe6c, &ixSMU_PM_STATUS_27[0], sizeof(ixSMU_PM_STATUS_27)/sizeof(ixSMU_PM_STATUS_27[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_28", REG_SMC, 0x3fe70, &ixSMU_PM_STATUS_28[0], sizeof(ixSMU_PM_STATUS_28)/sizeof(ixSMU_PM_STATUS_28[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_29", REG_SMC, 0x3fe74, &ixSMU_PM_STATUS_29[0], sizeof(ixSMU_PM_STATUS_29)/sizeof(ixSMU_PM_STATUS_29[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_30", REG_SMC, 0x3fe78, &ixSMU_PM_STATUS_30[0], sizeof(ixSMU_PM_STATUS_30)/sizeof(ixSMU_PM_STATUS_30[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_31", REG_SMC, 0x3fe7c, &ixSMU_PM_STATUS_31[0], sizeof(ixSMU_PM_STATUS_31)/sizeof(ixSMU_PM_STATUS_31[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_32", REG_SMC, 0x3fe80, &ixSMU_PM_STATUS_32[0], sizeof(ixSMU_PM_STATUS_32)/sizeof(ixSMU_PM_STATUS_32[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_33", REG_SMC, 0x3fe84, &ixSMU_PM_STATUS_33[0], sizeof(ixSMU_PM_STATUS_33)/sizeof(ixSMU_PM_STATUS_33[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_34", REG_SMC, 0x3fe88, &ixSMU_PM_STATUS_34[0], sizeof(ixSMU_PM_STATUS_34)/sizeof(ixSMU_PM_STATUS_34[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_35", REG_SMC, 0x3fe8c, &ixSMU_PM_STATUS_35[0], sizeof(ixSMU_PM_STATUS_35)/sizeof(ixSMU_PM_STATUS_35[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_36", REG_SMC, 0x3fe90, &ixSMU_PM_STATUS_36[0], sizeof(ixSMU_PM_STATUS_36)/sizeof(ixSMU_PM_STATUS_36[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_37", REG_SMC, 0x3fe94, &ixSMU_PM_STATUS_37[0], sizeof(ixSMU_PM_STATUS_37)/sizeof(ixSMU_PM_STATUS_37[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_38", REG_SMC, 0x3fe98, &ixSMU_PM_STATUS_38[0], sizeof(ixSMU_PM_STATUS_38)/sizeof(ixSMU_PM_STATUS_38[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_39", REG_SMC, 0x3fe9c, &ixSMU_PM_STATUS_39[0], sizeof(ixSMU_PM_STATUS_39)/sizeof(ixSMU_PM_STATUS_39[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_40", REG_SMC, 0x3fea0, &ixSMU_PM_STATUS_40[0], sizeof(ixSMU_PM_STATUS_40)/sizeof(ixSMU_PM_STATUS_40[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_41", REG_SMC, 0x3fea4, &ixSMU_PM_STATUS_41[0], sizeof(ixSMU_PM_STATUS_41)/sizeof(ixSMU_PM_STATUS_41[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_42", REG_SMC, 0x3fea8, &ixSMU_PM_STATUS_42[0], sizeof(ixSMU_PM_STATUS_42)/sizeof(ixSMU_PM_STATUS_42[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_43", REG_SMC, 0x3feac, &ixSMU_PM_STATUS_43[0], sizeof(ixSMU_PM_STATUS_43)/sizeof(ixSMU_PM_STATUS_43[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_44", REG_SMC, 0x3feb0, &ixSMU_PM_STATUS_44[0], sizeof(ixSMU_PM_STATUS_44)/sizeof(ixSMU_PM_STATUS_44[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_45", REG_SMC, 0x3feb4, &ixSMU_PM_STATUS_45[0], sizeof(ixSMU_PM_STATUS_45)/sizeof(ixSMU_PM_STATUS_45[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_46", REG_SMC, 0x3feb8, &ixSMU_PM_STATUS_46[0], sizeof(ixSMU_PM_STATUS_46)/sizeof(ixSMU_PM_STATUS_46[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_47", REG_SMC, 0x3febc, &ixSMU_PM_STATUS_47[0], sizeof(ixSMU_PM_STATUS_47)/sizeof(ixSMU_PM_STATUS_47[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_48", REG_SMC, 0x3fec0, &ixSMU_PM_STATUS_48[0], sizeof(ixSMU_PM_STATUS_48)/sizeof(ixSMU_PM_STATUS_48[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_49", REG_SMC, 0x3fec4, &ixSMU_PM_STATUS_49[0], sizeof(ixSMU_PM_STATUS_49)/sizeof(ixSMU_PM_STATUS_49[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_50", REG_SMC, 0x3fec8, &ixSMU_PM_STATUS_50[0], sizeof(ixSMU_PM_STATUS_50)/sizeof(ixSMU_PM_STATUS_50[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_51", REG_SMC, 0x3fecc, &ixSMU_PM_STATUS_51[0], sizeof(ixSMU_PM_STATUS_51)/sizeof(ixSMU_PM_STATUS_51[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_52", REG_SMC, 0x3fed0, &ixSMU_PM_STATUS_52[0], sizeof(ixSMU_PM_STATUS_52)/sizeof(ixSMU_PM_STATUS_52[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_53", REG_SMC, 0x3fed4, &ixSMU_PM_STATUS_53[0], sizeof(ixSMU_PM_STATUS_53)/sizeof(ixSMU_PM_STATUS_53[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_54", REG_SMC, 0x3fed8, &ixSMU_PM_STATUS_54[0], sizeof(ixSMU_PM_STATUS_54)/sizeof(ixSMU_PM_STATUS_54[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_55", REG_SMC, 0x3fedc, &ixSMU_PM_STATUS_55[0], sizeof(ixSMU_PM_STATUS_55)/sizeof(ixSMU_PM_STATUS_55[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_56", REG_SMC, 0x3fee0, &ixSMU_PM_STATUS_56[0], sizeof(ixSMU_PM_STATUS_56)/sizeof(ixSMU_PM_STATUS_56[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_57", REG_SMC, 0x3fee4, &ixSMU_PM_STATUS_57[0], sizeof(ixSMU_PM_STATUS_57)/sizeof(ixSMU_PM_STATUS_57[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_58", REG_SMC, 0x3fee8, &ixSMU_PM_STATUS_58[0], sizeof(ixSMU_PM_STATUS_58)/sizeof(ixSMU_PM_STATUS_58[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_59", REG_SMC, 0x3feec, &ixSMU_PM_STATUS_59[0], sizeof(ixSMU_PM_STATUS_59)/sizeof(ixSMU_PM_STATUS_59[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_60", REG_SMC, 0x3fef0, &ixSMU_PM_STATUS_60[0], sizeof(ixSMU_PM_STATUS_60)/sizeof(ixSMU_PM_STATUS_60[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_61", REG_SMC, 0x3fef4, &ixSMU_PM_STATUS_61[0], sizeof(ixSMU_PM_STATUS_61)/sizeof(ixSMU_PM_STATUS_61[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_62", REG_SMC, 0x3fef8, &ixSMU_PM_STATUS_62[0], sizeof(ixSMU_PM_STATUS_62)/sizeof(ixSMU_PM_STATUS_62[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_63", REG_SMC, 0x3fefc, &ixSMU_PM_STATUS_63[0], sizeof(ixSMU_PM_STATUS_63)/sizeof(ixSMU_PM_STATUS_63[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_64", REG_SMC, 0x3ff00, &ixSMU_PM_STATUS_64[0], sizeof(ixSMU_PM_STATUS_64)/sizeof(ixSMU_PM_STATUS_64[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_65", REG_SMC, 0x3ff04, &ixSMU_PM_STATUS_65[0], sizeof(ixSMU_PM_STATUS_65)/sizeof(ixSMU_PM_STATUS_65[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_66", REG_SMC, 0x3ff08, &ixSMU_PM_STATUS_66[0], sizeof(ixSMU_PM_STATUS_66)/sizeof(ixSMU_PM_STATUS_66[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_67", REG_SMC, 0x3ff0c, &ixSMU_PM_STATUS_67[0], sizeof(ixSMU_PM_STATUS_67)/sizeof(ixSMU_PM_STATUS_67[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_68", REG_SMC, 0x3ff10, &ixSMU_PM_STATUS_68[0], sizeof(ixSMU_PM_STATUS_68)/sizeof(ixSMU_PM_STATUS_68[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_69", REG_SMC, 0x3ff14, &ixSMU_PM_STATUS_69[0], sizeof(ixSMU_PM_STATUS_69)/sizeof(ixSMU_PM_STATUS_69[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_70", REG_SMC, 0x3ff18, &ixSMU_PM_STATUS_70[0], sizeof(ixSMU_PM_STATUS_70)/sizeof(ixSMU_PM_STATUS_70[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_71", REG_SMC, 0x3ff1c, &ixSMU_PM_STATUS_71[0], sizeof(ixSMU_PM_STATUS_71)/sizeof(ixSMU_PM_STATUS_71[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_72", REG_SMC, 0x3ff20, &ixSMU_PM_STATUS_72[0], sizeof(ixSMU_PM_STATUS_72)/sizeof(ixSMU_PM_STATUS_72[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_73", REG_SMC, 0x3ff24, &ixSMU_PM_STATUS_73[0], sizeof(ixSMU_PM_STATUS_73)/sizeof(ixSMU_PM_STATUS_73[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_74", REG_SMC, 0x3ff28, &ixSMU_PM_STATUS_74[0], sizeof(ixSMU_PM_STATUS_74)/sizeof(ixSMU_PM_STATUS_74[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_75", REG_SMC, 0x3ff2c, &ixSMU_PM_STATUS_75[0], sizeof(ixSMU_PM_STATUS_75)/sizeof(ixSMU_PM_STATUS_75[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_76", REG_SMC, 0x3ff30, &ixSMU_PM_STATUS_76[0], sizeof(ixSMU_PM_STATUS_76)/sizeof(ixSMU_PM_STATUS_76[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_77", REG_SMC, 0x3ff34, &ixSMU_PM_STATUS_77[0], sizeof(ixSMU_PM_STATUS_77)/sizeof(ixSMU_PM_STATUS_77[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_78", REG_SMC, 0x3ff38, &ixSMU_PM_STATUS_78[0], sizeof(ixSMU_PM_STATUS_78)/sizeof(ixSMU_PM_STATUS_78[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_79", REG_SMC, 0x3ff3c, &ixSMU_PM_STATUS_79[0], sizeof(ixSMU_PM_STATUS_79)/sizeof(ixSMU_PM_STATUS_79[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_80", REG_SMC, 0x3ff40, &ixSMU_PM_STATUS_80[0], sizeof(ixSMU_PM_STATUS_80)/sizeof(ixSMU_PM_STATUS_80[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_81", REG_SMC, 0x3ff44, &ixSMU_PM_STATUS_81[0], sizeof(ixSMU_PM_STATUS_81)/sizeof(ixSMU_PM_STATUS_81[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_82", REG_SMC, 0x3ff48, &ixSMU_PM_STATUS_82[0], sizeof(ixSMU_PM_STATUS_82)/sizeof(ixSMU_PM_STATUS_82[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_83", REG_SMC, 0x3ff4c, &ixSMU_PM_STATUS_83[0], sizeof(ixSMU_PM_STATUS_83)/sizeof(ixSMU_PM_STATUS_83[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_84", REG_SMC, 0x3ff50, &ixSMU_PM_STATUS_84[0], sizeof(ixSMU_PM_STATUS_84)/sizeof(ixSMU_PM_STATUS_84[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_85", REG_SMC, 0x3ff54, &ixSMU_PM_STATUS_85[0], sizeof(ixSMU_PM_STATUS_85)/sizeof(ixSMU_PM_STATUS_85[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_86", REG_SMC, 0x3ff58, &ixSMU_PM_STATUS_86[0], sizeof(ixSMU_PM_STATUS_86)/sizeof(ixSMU_PM_STATUS_86[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_87", REG_SMC, 0x3ff5c, &ixSMU_PM_STATUS_87[0], sizeof(ixSMU_PM_STATUS_87)/sizeof(ixSMU_PM_STATUS_87[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_88", REG_SMC, 0x3ff60, &ixSMU_PM_STATUS_88[0], sizeof(ixSMU_PM_STATUS_88)/sizeof(ixSMU_PM_STATUS_88[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_89", REG_SMC, 0x3ff64, &ixSMU_PM_STATUS_89[0], sizeof(ixSMU_PM_STATUS_89)/sizeof(ixSMU_PM_STATUS_89[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_90", REG_SMC, 0x3ff68, &ixSMU_PM_STATUS_90[0], sizeof(ixSMU_PM_STATUS_90)/sizeof(ixSMU_PM_STATUS_90[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_91", REG_SMC, 0x3ff6c, &ixSMU_PM_STATUS_91[0], sizeof(ixSMU_PM_STATUS_91)/sizeof(ixSMU_PM_STATUS_91[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_92", REG_SMC, 0x3ff70, &ixSMU_PM_STATUS_92[0], sizeof(ixSMU_PM_STATUS_92)/sizeof(ixSMU_PM_STATUS_92[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_93", REG_SMC, 0x3ff74, &ixSMU_PM_STATUS_93[0], sizeof(ixSMU_PM_STATUS_93)/sizeof(ixSMU_PM_STATUS_93[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_94", REG_SMC, 0x3ff78, &ixSMU_PM_STATUS_94[0], sizeof(ixSMU_PM_STATUS_94)/sizeof(ixSMU_PM_STATUS_94[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_95", REG_SMC, 0x3ff7c, &ixSMU_PM_STATUS_95[0], sizeof(ixSMU_PM_STATUS_95)/sizeof(ixSMU_PM_STATUS_95[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_96", REG_SMC, 0x3ff80, &ixSMU_PM_STATUS_96[0], sizeof(ixSMU_PM_STATUS_96)/sizeof(ixSMU_PM_STATUS_96[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_97", REG_SMC, 0x3ff84, &ixSMU_PM_STATUS_97[0], sizeof(ixSMU_PM_STATUS_97)/sizeof(ixSMU_PM_STATUS_97[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_98", REG_SMC, 0x3ff88, &ixSMU_PM_STATUS_98[0], sizeof(ixSMU_PM_STATUS_98)/sizeof(ixSMU_PM_STATUS_98[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_99", REG_SMC, 0x3ff8c, &ixSMU_PM_STATUS_99[0], sizeof(ixSMU_PM_STATUS_99)/sizeof(ixSMU_PM_STATUS_99[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_100", REG_SMC, 0x3ff90, &ixSMU_PM_STATUS_100[0], sizeof(ixSMU_PM_STATUS_100)/sizeof(ixSMU_PM_STATUS_100[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_101", REG_SMC, 0x3ff94, &ixSMU_PM_STATUS_101[0], sizeof(ixSMU_PM_STATUS_101)/sizeof(ixSMU_PM_STATUS_101[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_102", REG_SMC, 0x3ff98, &ixSMU_PM_STATUS_102[0], sizeof(ixSMU_PM_STATUS_102)/sizeof(ixSMU_PM_STATUS_102[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_103", REG_SMC, 0x3ff9c, &ixSMU_PM_STATUS_103[0], sizeof(ixSMU_PM_STATUS_103)/sizeof(ixSMU_PM_STATUS_103[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_104", REG_SMC, 0x3ffa0, &ixSMU_PM_STATUS_104[0], sizeof(ixSMU_PM_STATUS_104)/sizeof(ixSMU_PM_STATUS_104[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_105", REG_SMC, 0x3ffa4, &ixSMU_PM_STATUS_105[0], sizeof(ixSMU_PM_STATUS_105)/sizeof(ixSMU_PM_STATUS_105[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_106", REG_SMC, 0x3ffa8, &ixSMU_PM_STATUS_106[0], sizeof(ixSMU_PM_STATUS_106)/sizeof(ixSMU_PM_STATUS_106[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_107", REG_SMC, 0x3ffac, &ixSMU_PM_STATUS_107[0], sizeof(ixSMU_PM_STATUS_107)/sizeof(ixSMU_PM_STATUS_107[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_108", REG_SMC, 0x3ffb0, &ixSMU_PM_STATUS_108[0], sizeof(ixSMU_PM_STATUS_108)/sizeof(ixSMU_PM_STATUS_108[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_109", REG_SMC, 0x3ffb4, &ixSMU_PM_STATUS_109[0], sizeof(ixSMU_PM_STATUS_109)/sizeof(ixSMU_PM_STATUS_109[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_110", REG_SMC, 0x3ffb8, &ixSMU_PM_STATUS_110[0], sizeof(ixSMU_PM_STATUS_110)/sizeof(ixSMU_PM_STATUS_110[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_111", REG_SMC, 0x3ffbc, &ixSMU_PM_STATUS_111[0], sizeof(ixSMU_PM_STATUS_111)/sizeof(ixSMU_PM_STATUS_111[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_112", REG_SMC, 0x3ffc0, &ixSMU_PM_STATUS_112[0], sizeof(ixSMU_PM_STATUS_112)/sizeof(ixSMU_PM_STATUS_112[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_113", REG_SMC, 0x3ffc4, &ixSMU_PM_STATUS_113[0], sizeof(ixSMU_PM_STATUS_113)/sizeof(ixSMU_PM_STATUS_113[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_114", REG_SMC, 0x3ffc8, &ixSMU_PM_STATUS_114[0], sizeof(ixSMU_PM_STATUS_114)/sizeof(ixSMU_PM_STATUS_114[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_115", REG_SMC, 0x3ffcc, &ixSMU_PM_STATUS_115[0], sizeof(ixSMU_PM_STATUS_115)/sizeof(ixSMU_PM_STATUS_115[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_116", REG_SMC, 0x3ffd0, &ixSMU_PM_STATUS_116[0], sizeof(ixSMU_PM_STATUS_116)/sizeof(ixSMU_PM_STATUS_116[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_117", REG_SMC, 0x3ffd4, &ixSMU_PM_STATUS_117[0], sizeof(ixSMU_PM_STATUS_117)/sizeof(ixSMU_PM_STATUS_117[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_118", REG_SMC, 0x3ffd8, &ixSMU_PM_STATUS_118[0], sizeof(ixSMU_PM_STATUS_118)/sizeof(ixSMU_PM_STATUS_118[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_119", REG_SMC, 0x3ffdc, &ixSMU_PM_STATUS_119[0], sizeof(ixSMU_PM_STATUS_119)/sizeof(ixSMU_PM_STATUS_119[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_120", REG_SMC, 0x3ffe0, &ixSMU_PM_STATUS_120[0], sizeof(ixSMU_PM_STATUS_120)/sizeof(ixSMU_PM_STATUS_120[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_121", REG_SMC, 0x3ffe4, &ixSMU_PM_STATUS_121[0], sizeof(ixSMU_PM_STATUS_121)/sizeof(ixSMU_PM_STATUS_121[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_122", REG_SMC, 0x3ffe8, &ixSMU_PM_STATUS_122[0], sizeof(ixSMU_PM_STATUS_122)/sizeof(ixSMU_PM_STATUS_122[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_123", REG_SMC, 0x3ffec, &ixSMU_PM_STATUS_123[0], sizeof(ixSMU_PM_STATUS_123)/sizeof(ixSMU_PM_STATUS_123[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_124", REG_SMC, 0x3fff0, &ixSMU_PM_STATUS_124[0], sizeof(ixSMU_PM_STATUS_124)/sizeof(ixSMU_PM_STATUS_124[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_125", REG_SMC, 0x3fff4, &ixSMU_PM_STATUS_125[0], sizeof(ixSMU_PM_STATUS_125)/sizeof(ixSMU_PM_STATUS_125[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_126", REG_SMC, 0x3fff8, &ixSMU_PM_STATUS_126[0], sizeof(ixSMU_PM_STATUS_126)/sizeof(ixSMU_PM_STATUS_126[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_127", REG_SMC, 0x3fffc, &ixSMU_PM_STATUS_127[0], sizeof(ixSMU_PM_STATUS_127)/sizeof(ixSMU_PM_STATUS_127[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_INDEX", REG_MMIO, 0x80, &mmGCK_SMC_IND_INDEX[0], sizeof(mmGCK_SMC_IND_INDEX)/sizeof(mmGCK_SMC_IND_INDEX[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_0", REG_MMIO, 0x80, &mmSMC_IND_INDEX_0[0], sizeof(mmSMC_IND_INDEX_0)/sizeof(mmSMC_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX", REG_MMIO, 0x80, &mmSMC_IND_INDEX[0], sizeof(mmSMC_IND_INDEX)/sizeof(mmSMC_IND_INDEX[0]), 0, 0 },
+	{ "ixSMC_SYSCON_RESET_CNTL", REG_SMC, 0x80000000, &ixSMC_SYSCON_RESET_CNTL[0], sizeof(ixSMC_SYSCON_RESET_CNTL)/sizeof(ixSMC_SYSCON_RESET_CNTL[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_0", REG_SMC, 0x80000004, &ixSMC_SYSCON_CLOCK_CNTL_0[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_0)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_0[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_1", REG_SMC, 0x80000008, &ixSMC_SYSCON_CLOCK_CNTL_1[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_1)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_1[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_2", REG_SMC, 0x8000000c, &ixSMC_SYSCON_CLOCK_CNTL_2[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_2)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_2[0]), 0, 0 },
+	{ "ixSMC_SYSCON_MISC_CNTL", REG_SMC, 0x80000010, NULL, 0, 0, 0 },
+	{ "ixSMC_SYSCON_MSG_ARG_0", REG_SMC, 0x80000068, &ixSMC_SYSCON_MSG_ARG_0[0], sizeof(ixSMC_SYSCON_MSG_ARG_0)/sizeof(ixSMC_SYSCON_MSG_ARG_0[0]), 0, 0 },
+	{ "ixSMC_PC_C", REG_SMC, 0x80000370, &ixSMC_PC_C[0], sizeof(ixSMC_PC_C)/sizeof(ixSMC_PC_C[0]), 0, 0 },
+	{ "ixSMC_SCRATCH9", REG_SMC, 0x80000424, &ixSMC_SCRATCH9[0], sizeof(ixSMC_SCRATCH9)/sizeof(ixSMC_SCRATCH9[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_DATA", REG_MMIO, 0x81, &mmGCK_SMC_IND_DATA[0], sizeof(mmGCK_SMC_IND_DATA)/sizeof(mmGCK_SMC_IND_DATA[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_0", REG_MMIO, 0x81, &mmSMC_IND_DATA_0[0], sizeof(mmSMC_IND_DATA_0)/sizeof(mmSMC_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMC_IND_DATA", REG_MMIO, 0x81, &mmSMC_IND_DATA[0], sizeof(mmSMC_IND_DATA)/sizeof(mmSMC_IND_DATA[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_1", REG_MMIO, 0x82, &mmSMC_IND_INDEX_1[0], sizeof(mmSMC_IND_INDEX_1)/sizeof(mmSMC_IND_INDEX_1[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_1", REG_MMIO, 0x83, &mmSMC_IND_DATA_1[0], sizeof(mmSMC_IND_DATA_1)/sizeof(mmSMC_IND_DATA_1[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_2", REG_MMIO, 0x84, &mmSMC_IND_INDEX_2[0], sizeof(mmSMC_IND_INDEX_2)/sizeof(mmSMC_IND_INDEX_2[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_2", REG_MMIO, 0x85, &mmSMC_IND_DATA_2[0], sizeof(mmSMC_IND_DATA_2)/sizeof(mmSMC_IND_DATA_2[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_3", REG_MMIO, 0x86, &mmSMC_IND_INDEX_3[0], sizeof(mmSMC_IND_INDEX_3)/sizeof(mmSMC_IND_INDEX_3[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_3", REG_MMIO, 0x87, &mmSMC_IND_DATA_3[0], sizeof(mmSMC_IND_DATA_3)/sizeof(mmSMC_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_4", REG_MMIO, 0x88, &mmSMC_IND_INDEX_4[0], sizeof(mmSMC_IND_INDEX_4)/sizeof(mmSMC_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_4", REG_MMIO, 0x89, &mmSMC_IND_DATA_4[0], sizeof(mmSMC_IND_DATA_4)/sizeof(mmSMC_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_5", REG_MMIO, 0x8a, &mmSMC_IND_INDEX_5[0], sizeof(mmSMC_IND_INDEX_5)/sizeof(mmSMC_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_5", REG_MMIO, 0x8b, &mmSMC_IND_DATA_5[0], sizeof(mmSMC_IND_DATA_5)/sizeof(mmSMC_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_6", REG_MMIO, 0x8c, &mmSMC_IND_INDEX_6[0], sizeof(mmSMC_IND_INDEX_6)/sizeof(mmSMC_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_6", REG_MMIO, 0x8d, &mmSMC_IND_DATA_6[0], sizeof(mmSMC_IND_DATA_6)/sizeof(mmSMC_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_7", REG_MMIO, 0x8e, &mmSMC_IND_INDEX_7[0], sizeof(mmSMC_IND_INDEX_7)/sizeof(mmSMC_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_7", REG_MMIO, 0x8f, &mmSMC_IND_DATA_7[0], sizeof(mmSMC_IND_DATA_7)/sizeof(mmSMC_IND_DATA_7[0]), 0, 0 },
+	{ "mmSMC_IND_ACCESS_CNTL", REG_MMIO, 0x90, &mmSMC_IND_ACCESS_CNTL[0], sizeof(mmSMC_IND_ACCESS_CNTL)/sizeof(mmSMC_IND_ACCESS_CNTL[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_11", REG_MMIO, 0x91, &mmSMC_MSG_ARG_11[0], sizeof(mmSMC_MSG_ARG_11)/sizeof(mmSMC_MSG_ARG_11[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_0", REG_MMIO, 0x94, &mmSMC_MESSAGE_0[0], sizeof(mmSMC_MESSAGE_0)/sizeof(mmSMC_MESSAGE_0[0]), 0, 0 },
+	{ "mmSMC_RESP_0", REG_MMIO, 0x95, &mmSMC_RESP_0[0], sizeof(mmSMC_RESP_0)/sizeof(mmSMC_RESP_0[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_1", REG_MMIO, 0x96, &mmSMC_MESSAGE_1[0], sizeof(mmSMC_MESSAGE_1)/sizeof(mmSMC_MESSAGE_1[0]), 0, 0 },
+	{ "mmSMC_RESP_1", REG_MMIO, 0x97, &mmSMC_RESP_1[0], sizeof(mmSMC_RESP_1)/sizeof(mmSMC_RESP_1[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_2", REG_MMIO, 0x98, &mmSMC_MESSAGE_2[0], sizeof(mmSMC_MESSAGE_2)/sizeof(mmSMC_MESSAGE_2[0]), 0, 0 },
+	{ "mmSMC_RESP_2", REG_MMIO, 0x99, &mmSMC_RESP_2[0], sizeof(mmSMC_RESP_2)/sizeof(mmSMC_RESP_2[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_3", REG_MMIO, 0x9a, &mmSMC_MESSAGE_3[0], sizeof(mmSMC_MESSAGE_3)/sizeof(mmSMC_MESSAGE_3[0]), 0, 0 },
+	{ "mmSMC_RESP_3", REG_MMIO, 0x9b, &mmSMC_RESP_3[0], sizeof(mmSMC_RESP_3)/sizeof(mmSMC_RESP_3[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_4", REG_MMIO, 0x9c, &mmSMC_MESSAGE_4[0], sizeof(mmSMC_MESSAGE_4)/sizeof(mmSMC_MESSAGE_4[0]), 0, 0 },
+	{ "mmSMC_RESP_4", REG_MMIO, 0x9d, &mmSMC_RESP_4[0], sizeof(mmSMC_RESP_4)/sizeof(mmSMC_RESP_4[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_5", REG_MMIO, 0x9e, &mmSMC_MESSAGE_5[0], sizeof(mmSMC_MESSAGE_5)/sizeof(mmSMC_MESSAGE_5[0]), 0, 0 },
+	{ "mmSMC_RESP_5", REG_MMIO, 0x9f, &mmSMC_RESP_5[0], sizeof(mmSMC_RESP_5)/sizeof(mmSMC_RESP_5[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_6", REG_MMIO, 0xa0, &mmSMC_MESSAGE_6[0], sizeof(mmSMC_MESSAGE_6)/sizeof(mmSMC_MESSAGE_6[0]), 0, 0 },
+	{ "mmSMC_RESP_6", REG_MMIO, 0xa1, &mmSMC_RESP_6[0], sizeof(mmSMC_RESP_6)/sizeof(mmSMC_RESP_6[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_7", REG_MMIO, 0xa2, &mmSMC_MESSAGE_7[0], sizeof(mmSMC_MESSAGE_7)/sizeof(mmSMC_MESSAGE_7[0]), 0, 0 },
+	{ "mmSMC_RESP_7", REG_MMIO, 0xa3, &mmSMC_RESP_7[0], sizeof(mmSMC_RESP_7)/sizeof(mmSMC_RESP_7[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_0", REG_MMIO, 0xa4, &mmSMC_MSG_ARG_0[0], sizeof(mmSMC_MSG_ARG_0)/sizeof(mmSMC_MSG_ARG_0[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_1", REG_MMIO, 0xa5, &mmSMC_MSG_ARG_1[0], sizeof(mmSMC_MSG_ARG_1)/sizeof(mmSMC_MSG_ARG_1[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_2", REG_MMIO, 0xa6, &mmSMC_MSG_ARG_2[0], sizeof(mmSMC_MSG_ARG_2)/sizeof(mmSMC_MSG_ARG_2[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_3", REG_MMIO, 0xa7, &mmSMC_MSG_ARG_3[0], sizeof(mmSMC_MSG_ARG_3)/sizeof(mmSMC_MSG_ARG_3[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_4", REG_MMIO, 0xa8, &mmSMC_MSG_ARG_4[0], sizeof(mmSMC_MSG_ARG_4)/sizeof(mmSMC_MSG_ARG_4[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_5", REG_MMIO, 0xa9, &mmSMC_MSG_ARG_5[0], sizeof(mmSMC_MSG_ARG_5)/sizeof(mmSMC_MSG_ARG_5[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_6", REG_MMIO, 0xaa, &mmSMC_MSG_ARG_6[0], sizeof(mmSMC_MSG_ARG_6)/sizeof(mmSMC_MSG_ARG_6[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_7", REG_MMIO, 0xab, &mmSMC_MSG_ARG_7[0], sizeof(mmSMC_MSG_ARG_7)/sizeof(mmSMC_MSG_ARG_7[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_8", REG_MMIO, 0xb5, &mmSMC_MESSAGE_8[0], sizeof(mmSMC_MESSAGE_8)/sizeof(mmSMC_MESSAGE_8[0]), 0, 0 },
+	{ "mmSMC_RESP_8", REG_MMIO, 0xb6, &mmSMC_RESP_8[0], sizeof(mmSMC_RESP_8)/sizeof(mmSMC_RESP_8[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_9", REG_MMIO, 0xb7, &mmSMC_MESSAGE_9[0], sizeof(mmSMC_MESSAGE_9)/sizeof(mmSMC_MESSAGE_9[0]), 0, 0 },
+	{ "mmSMC_RESP_9", REG_MMIO, 0xb8, &mmSMC_RESP_9[0], sizeof(mmSMC_RESP_9)/sizeof(mmSMC_RESP_9[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_10", REG_MMIO, 0xb9, &mmSMC_MESSAGE_10[0], sizeof(mmSMC_MESSAGE_10)/sizeof(mmSMC_MESSAGE_10[0]), 0, 0 },
+	{ "mmSMC_RESP_10", REG_MMIO, 0xba, &mmSMC_RESP_10[0], sizeof(mmSMC_RESP_10)/sizeof(mmSMC_RESP_10[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_11", REG_MMIO, 0xbb, &mmSMC_MESSAGE_11[0], sizeof(mmSMC_MESSAGE_11)/sizeof(mmSMC_MESSAGE_11[0]), 0, 0 },
+	{ "mmSMC_RESP_11", REG_MMIO, 0xbc, &mmSMC_RESP_11[0], sizeof(mmSMC_RESP_11)/sizeof(mmSMC_RESP_11[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_8", REG_MMIO, 0xbd, &mmSMC_MSG_ARG_8[0], sizeof(mmSMC_MSG_ARG_8)/sizeof(mmSMC_MSG_ARG_8[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_9", REG_MMIO, 0xbe, &mmSMC_MSG_ARG_9[0], sizeof(mmSMC_MSG_ARG_9)/sizeof(mmSMC_MSG_ARG_9[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_10", REG_MMIO, 0xbf, &mmSMC_MSG_ARG_10[0], sizeof(mmSMC_MSG_ARG_10)/sizeof(mmSMC_MSG_ARG_10[0]), 0, 0 },
+	{ "ixRCU_UC_EVENTS", REG_SMC, 0xc0000004, &ixRCU_UC_EVENTS[0], sizeof(ixRCU_UC_EVENTS)/sizeof(ixRCU_UC_EVENTS[0]), 0, 0 },
+	{ "ixRCU_MISC_CTRL", REG_SMC, 0xc0000010, &ixRCU_MISC_CTRL[0], sizeof(ixRCU_MISC_CTRL)/sizeof(ixRCU_MISC_CTRL[0]), 0, 0 },
+	{ "ixCC_RCU_FUSES", REG_SMC, 0xc00c0000, &ixCC_RCU_FUSES[0], sizeof(ixCC_RCU_FUSES)/sizeof(ixCC_RCU_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_MISC_FUSES", REG_SMC, 0xc00c0004, &ixCC_SMU_MISC_FUSES[0], sizeof(ixCC_SMU_MISC_FUSES)/sizeof(ixCC_SMU_MISC_FUSES[0]), 0, 0 },
+	{ "ixCC_SCLK_VID_FUSES", REG_SMC, 0xc00c0008, &ixCC_SCLK_VID_FUSES[0], sizeof(ixCC_SCLK_VID_FUSES)/sizeof(ixCC_SCLK_VID_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOCCFG_FUSES", REG_SMC, 0xc00c000c, &ixCC_GIO_IOCCFG_FUSES[0], sizeof(ixCC_GIO_IOCCFG_FUSES)/sizeof(ixCC_GIO_IOCCFG_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOC_FUSES", REG_SMC, 0xc00c0010, &ixCC_GIO_IOC_FUSES[0], sizeof(ixCC_GIO_IOC_FUSES)/sizeof(ixCC_GIO_IOC_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_TST_EFUSE1_MISC", REG_SMC, 0xc00c001c, &ixCC_SMU_TST_EFUSE1_MISC[0], sizeof(ixCC_SMU_TST_EFUSE1_MISC)/sizeof(ixCC_SMU_TST_EFUSE1_MISC[0]), 0, 0 },
+	{ "ixCC_TST_ID_STRAPS", REG_SMC, 0xc00c0020, &ixCC_TST_ID_STRAPS[0], sizeof(ixCC_TST_ID_STRAPS)/sizeof(ixCC_TST_ID_STRAPS[0]), 0, 0 },
+	{ "ixCC_FCTRL_FUSES", REG_SMC, 0xc00c0024, &ixCC_FCTRL_FUSES[0], sizeof(ixCC_FCTRL_FUSES)/sizeof(ixCC_FCTRL_FUSES[0]), 0, 0 },
+	{ "ixSMU_EFUSE_0", REG_SMC, 0xc0100000, &ixSMU_EFUSE_0[0], sizeof(ixSMU_EFUSE_0)/sizeof(ixSMU_EFUSE_0[0]), 0, 0 },
+	{ "ixGENERAL_PWRMGT", REG_SMC, 0xc0200000, &ixGENERAL_PWRMGT[0], sizeof(ixGENERAL_PWRMGT)/sizeof(ixGENERAL_PWRMGT[0]), 0, 0 },
+	{ "ixCNB_PWRMGT_CNTL", REG_SMC, 0xc0200004, &ixCNB_PWRMGT_CNTL[0], sizeof(ixCNB_PWRMGT_CNTL)/sizeof(ixCNB_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixSCLK_PWRMGT_CNTL", REG_SMC, 0xc0200008, &ixSCLK_PWRMGT_CNTL[0], sizeof(ixSCLK_PWRMGT_CNTL)/sizeof(ixSCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX", REG_SMC, 0xc0200014, &ixTARGET_AND_CURRENT_PROFILE_INDEX[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX[0]), 0, 0 },
+	{ "ixPLL_TEST_CNTL", REG_SMC, 0xc020003c, &ixPLL_TEST_CNTL[0], sizeof(ixPLL_TEST_CNTL)/sizeof(ixPLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixCG_STATIC_SCREEN_PARAMETER", REG_SMC, 0xc0200044, &ixCG_STATIC_SCREEN_PARAMETER[0], sizeof(ixCG_STATIC_SCREEN_PARAMETER)/sizeof(ixCG_STATIC_SCREEN_PARAMETER[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL", REG_SMC, 0xc0200060, &ixCG_DISPLAY_GAP_CNTL[0], sizeof(ixCG_DISPLAY_GAP_CNTL)/sizeof(ixCG_DISPLAY_GAP_CNTL[0]), 0, 0 },
+	{ "ixCG_ACPI_CNTL", REG_SMC, 0xc0200064, &ixCG_ACPI_CNTL[0], sizeof(ixCG_ACPI_CNTL)/sizeof(ixCG_ACPI_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc0200080, &ixSCLK_DEEP_SLEEP_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200084, &ixSCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL2)/sizeof(ixSCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_MISC_CNTL", REG_SMC, 0xc0200088, &ixSCLK_DEEP_SLEEP_MISC_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc020008c, &ixLCLK_DEEP_SLEEP_CNTL[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL)/sizeof(ixLCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL3", REG_SMC, 0xc020009c, &ixSCLK_DEEP_SLEEP_CNTL3[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL3)/sizeof(ixSCLK_DEEP_SLEEP_CNTL3[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_1", REG_SMC, 0xc02000f0, &ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0]), 0, 0 },
+	{ "ixCG_ULV_PARAMETER", REG_SMC, 0xc020015c, &ixCG_ULV_PARAMETER[0], sizeof(ixCG_ULV_PARAMETER)/sizeof(ixCG_ULV_PARAMETER[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_0", REG_SMC, 0xc02001a8, &ixCG_FREQ_TRAN_VOTING_0[0], sizeof(ixCG_FREQ_TRAN_VOTING_0)/sizeof(ixCG_FREQ_TRAN_VOTING_0[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_1", REG_SMC, 0xc02001ac, &ixCG_FREQ_TRAN_VOTING_1[0], sizeof(ixCG_FREQ_TRAN_VOTING_1)/sizeof(ixCG_FREQ_TRAN_VOTING_1[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_2", REG_SMC, 0xc02001b0, &ixCG_FREQ_TRAN_VOTING_2[0], sizeof(ixCG_FREQ_TRAN_VOTING_2)/sizeof(ixCG_FREQ_TRAN_VOTING_2[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_3", REG_SMC, 0xc02001b4, &ixCG_FREQ_TRAN_VOTING_3[0], sizeof(ixCG_FREQ_TRAN_VOTING_3)/sizeof(ixCG_FREQ_TRAN_VOTING_3[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_4", REG_SMC, 0xc02001b8, &ixCG_FREQ_TRAN_VOTING_4[0], sizeof(ixCG_FREQ_TRAN_VOTING_4)/sizeof(ixCG_FREQ_TRAN_VOTING_4[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_5", REG_SMC, 0xc02001bc, &ixCG_FREQ_TRAN_VOTING_5[0], sizeof(ixCG_FREQ_TRAN_VOTING_5)/sizeof(ixCG_FREQ_TRAN_VOTING_5[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, &ixCG_DISPLAY_GAP_CNTL2[0], sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_MIN_DIV", REG_SMC, 0xc0200308, &ixSCLK_MIN_DIV[0], sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixCG_THERMAL_CTRL", REG_SMC, 0xc0300004, &ixCG_THERMAL_CTRL[0], sizeof(ixCG_THERMAL_CTRL)/sizeof(ixCG_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_STATUS", REG_SMC, 0xc0300008, &ixCG_THERMAL_STATUS[0], sizeof(ixCG_THERMAL_STATUS)/sizeof(ixCG_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT", REG_SMC, 0xc030000c, &ixCG_THERMAL_INT[0], sizeof(ixCG_THERMAL_INT)/sizeof(ixCG_THERMAL_INT[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_CTRL", REG_SMC, 0xc0300010, &ixCG_MULT_THERMAL_CTRL[0], sizeof(ixCG_MULT_THERMAL_CTRL)/sizeof(ixCG_MULT_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_STATUS", REG_SMC, 0xc0300014, &ixCG_MULT_THERMAL_STATUS[0], sizeof(ixCG_MULT_THERMAL_STATUS)/sizeof(ixCG_MULT_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL0", REG_SMC, 0xc0300064, &ixCG_FDO_CTRL0[0], sizeof(ixCG_FDO_CTRL0)/sizeof(ixCG_FDO_CTRL0[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL1", REG_SMC, 0xc0300068, &ixCG_FDO_CTRL1[0], sizeof(ixCG_FDO_CTRL1)/sizeof(ixCG_FDO_CTRL1[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL2", REG_SMC, 0xc030006c, &ixCG_FDO_CTRL2[0], sizeof(ixCG_FDO_CTRL2)/sizeof(ixCG_FDO_CTRL2[0]), 0, 0 },
+	{ "ixCG_TACH_CTRL", REG_SMC, 0xc0300070, &ixCG_TACH_CTRL[0], sizeof(ixCG_TACH_CTRL)/sizeof(ixCG_TACH_CTRL[0]), 0, 0 },
+	{ "ixCG_TACH_STATUS", REG_SMC, 0xc0300074, &ixCG_TACH_STATUS[0], sizeof(ixCG_TACH_STATUS)/sizeof(ixCG_TACH_STATUS[0]), 0, 0 },
+	{ "ixCC_THM_STRAPS0", REG_SMC, 0xc0300080, &ixCC_THM_STRAPS0[0], sizeof(ixCC_THM_STRAPS0)/sizeof(ixCC_THM_STRAPS0[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL0_DATA", REG_SMC, 0xc0300100, &ixTHM_TMON0_RDIL0_DATA[0], sizeof(ixTHM_TMON0_RDIL0_DATA)/sizeof(ixTHM_TMON0_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL1_DATA", REG_SMC, 0xc0300104, &ixTHM_TMON0_RDIL1_DATA[0], sizeof(ixTHM_TMON0_RDIL1_DATA)/sizeof(ixTHM_TMON0_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL2_DATA", REG_SMC, 0xc0300108, &ixTHM_TMON0_RDIL2_DATA[0], sizeof(ixTHM_TMON0_RDIL2_DATA)/sizeof(ixTHM_TMON0_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL3_DATA", REG_SMC, 0xc030010c, &ixTHM_TMON0_RDIL3_DATA[0], sizeof(ixTHM_TMON0_RDIL3_DATA)/sizeof(ixTHM_TMON0_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL4_DATA", REG_SMC, 0xc0300110, &ixTHM_TMON0_RDIL4_DATA[0], sizeof(ixTHM_TMON0_RDIL4_DATA)/sizeof(ixTHM_TMON0_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL5_DATA", REG_SMC, 0xc0300114, &ixTHM_TMON0_RDIL5_DATA[0], sizeof(ixTHM_TMON0_RDIL5_DATA)/sizeof(ixTHM_TMON0_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL6_DATA", REG_SMC, 0xc0300118, &ixTHM_TMON0_RDIL6_DATA[0], sizeof(ixTHM_TMON0_RDIL6_DATA)/sizeof(ixTHM_TMON0_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL7_DATA", REG_SMC, 0xc030011c, &ixTHM_TMON0_RDIL7_DATA[0], sizeof(ixTHM_TMON0_RDIL7_DATA)/sizeof(ixTHM_TMON0_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL8_DATA", REG_SMC, 0xc0300120, &ixTHM_TMON0_RDIL8_DATA[0], sizeof(ixTHM_TMON0_RDIL8_DATA)/sizeof(ixTHM_TMON0_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL9_DATA", REG_SMC, 0xc0300124, &ixTHM_TMON0_RDIL9_DATA[0], sizeof(ixTHM_TMON0_RDIL9_DATA)/sizeof(ixTHM_TMON0_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL10_DATA", REG_SMC, 0xc0300128, &ixTHM_TMON0_RDIL10_DATA[0], sizeof(ixTHM_TMON0_RDIL10_DATA)/sizeof(ixTHM_TMON0_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL11_DATA", REG_SMC, 0xc030012c, &ixTHM_TMON0_RDIL11_DATA[0], sizeof(ixTHM_TMON0_RDIL11_DATA)/sizeof(ixTHM_TMON0_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL12_DATA", REG_SMC, 0xc0300130, &ixTHM_TMON0_RDIL12_DATA[0], sizeof(ixTHM_TMON0_RDIL12_DATA)/sizeof(ixTHM_TMON0_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL13_DATA", REG_SMC, 0xc0300134, &ixTHM_TMON0_RDIL13_DATA[0], sizeof(ixTHM_TMON0_RDIL13_DATA)/sizeof(ixTHM_TMON0_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL14_DATA", REG_SMC, 0xc0300138, &ixTHM_TMON0_RDIL14_DATA[0], sizeof(ixTHM_TMON0_RDIL14_DATA)/sizeof(ixTHM_TMON0_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL15_DATA", REG_SMC, 0xc030013c, &ixTHM_TMON0_RDIL15_DATA[0], sizeof(ixTHM_TMON0_RDIL15_DATA)/sizeof(ixTHM_TMON0_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR0_DATA", REG_SMC, 0xc0300140, &ixTHM_TMON0_RDIR0_DATA[0], sizeof(ixTHM_TMON0_RDIR0_DATA)/sizeof(ixTHM_TMON0_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR1_DATA", REG_SMC, 0xc0300144, &ixTHM_TMON0_RDIR1_DATA[0], sizeof(ixTHM_TMON0_RDIR1_DATA)/sizeof(ixTHM_TMON0_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR2_DATA", REG_SMC, 0xc0300148, &ixTHM_TMON0_RDIR2_DATA[0], sizeof(ixTHM_TMON0_RDIR2_DATA)/sizeof(ixTHM_TMON0_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR3_DATA", REG_SMC, 0xc030014c, &ixTHM_TMON0_RDIR3_DATA[0], sizeof(ixTHM_TMON0_RDIR3_DATA)/sizeof(ixTHM_TMON0_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR4_DATA", REG_SMC, 0xc0300150, &ixTHM_TMON0_RDIR4_DATA[0], sizeof(ixTHM_TMON0_RDIR4_DATA)/sizeof(ixTHM_TMON0_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR5_DATA", REG_SMC, 0xc0300154, &ixTHM_TMON0_RDIR5_DATA[0], sizeof(ixTHM_TMON0_RDIR5_DATA)/sizeof(ixTHM_TMON0_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR6_DATA", REG_SMC, 0xc0300158, &ixTHM_TMON0_RDIR6_DATA[0], sizeof(ixTHM_TMON0_RDIR6_DATA)/sizeof(ixTHM_TMON0_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR7_DATA", REG_SMC, 0xc030015c, &ixTHM_TMON0_RDIR7_DATA[0], sizeof(ixTHM_TMON0_RDIR7_DATA)/sizeof(ixTHM_TMON0_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR8_DATA", REG_SMC, 0xc0300160, &ixTHM_TMON0_RDIR8_DATA[0], sizeof(ixTHM_TMON0_RDIR8_DATA)/sizeof(ixTHM_TMON0_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR9_DATA", REG_SMC, 0xc0300164, &ixTHM_TMON0_RDIR9_DATA[0], sizeof(ixTHM_TMON0_RDIR9_DATA)/sizeof(ixTHM_TMON0_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR10_DATA", REG_SMC, 0xc0300168, &ixTHM_TMON0_RDIR10_DATA[0], sizeof(ixTHM_TMON0_RDIR10_DATA)/sizeof(ixTHM_TMON0_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR11_DATA", REG_SMC, 0xc030016c, &ixTHM_TMON0_RDIR11_DATA[0], sizeof(ixTHM_TMON0_RDIR11_DATA)/sizeof(ixTHM_TMON0_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR12_DATA", REG_SMC, 0xc0300170, &ixTHM_TMON0_RDIR12_DATA[0], sizeof(ixTHM_TMON0_RDIR12_DATA)/sizeof(ixTHM_TMON0_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR13_DATA", REG_SMC, 0xc0300174, &ixTHM_TMON0_RDIR13_DATA[0], sizeof(ixTHM_TMON0_RDIR13_DATA)/sizeof(ixTHM_TMON0_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR14_DATA", REG_SMC, 0xc0300178, &ixTHM_TMON0_RDIR14_DATA[0], sizeof(ixTHM_TMON0_RDIR14_DATA)/sizeof(ixTHM_TMON0_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR15_DATA", REG_SMC, 0xc030017c, &ixTHM_TMON0_RDIR15_DATA[0], sizeof(ixTHM_TMON0_RDIR15_DATA)/sizeof(ixTHM_TMON0_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL0_DATA", REG_SMC, 0xc0300180, &ixTHM_TMON1_RDIL0_DATA[0], sizeof(ixTHM_TMON1_RDIL0_DATA)/sizeof(ixTHM_TMON1_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL1_DATA", REG_SMC, 0xc0300184, &ixTHM_TMON1_RDIL1_DATA[0], sizeof(ixTHM_TMON1_RDIL1_DATA)/sizeof(ixTHM_TMON1_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL2_DATA", REG_SMC, 0xc0300188, &ixTHM_TMON1_RDIL2_DATA[0], sizeof(ixTHM_TMON1_RDIL2_DATA)/sizeof(ixTHM_TMON1_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL3_DATA", REG_SMC, 0xc030018c, &ixTHM_TMON1_RDIL3_DATA[0], sizeof(ixTHM_TMON1_RDIL3_DATA)/sizeof(ixTHM_TMON1_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL4_DATA", REG_SMC, 0xc0300190, &ixTHM_TMON1_RDIL4_DATA[0], sizeof(ixTHM_TMON1_RDIL4_DATA)/sizeof(ixTHM_TMON1_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL5_DATA", REG_SMC, 0xc0300194, &ixTHM_TMON1_RDIL5_DATA[0], sizeof(ixTHM_TMON1_RDIL5_DATA)/sizeof(ixTHM_TMON1_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL6_DATA", REG_SMC, 0xc0300198, &ixTHM_TMON1_RDIL6_DATA[0], sizeof(ixTHM_TMON1_RDIL6_DATA)/sizeof(ixTHM_TMON1_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL7_DATA", REG_SMC, 0xc030019c, &ixTHM_TMON1_RDIL7_DATA[0], sizeof(ixTHM_TMON1_RDIL7_DATA)/sizeof(ixTHM_TMON1_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL8_DATA", REG_SMC, 0xc03001a0, &ixTHM_TMON1_RDIL8_DATA[0], sizeof(ixTHM_TMON1_RDIL8_DATA)/sizeof(ixTHM_TMON1_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL9_DATA", REG_SMC, 0xc03001a4, &ixTHM_TMON1_RDIL9_DATA[0], sizeof(ixTHM_TMON1_RDIL9_DATA)/sizeof(ixTHM_TMON1_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL10_DATA", REG_SMC, 0xc03001a8, &ixTHM_TMON1_RDIL10_DATA[0], sizeof(ixTHM_TMON1_RDIL10_DATA)/sizeof(ixTHM_TMON1_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL11_DATA", REG_SMC, 0xc03001ac, &ixTHM_TMON1_RDIL11_DATA[0], sizeof(ixTHM_TMON1_RDIL11_DATA)/sizeof(ixTHM_TMON1_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL12_DATA", REG_SMC, 0xc03001b0, &ixTHM_TMON1_RDIL12_DATA[0], sizeof(ixTHM_TMON1_RDIL12_DATA)/sizeof(ixTHM_TMON1_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL13_DATA", REG_SMC, 0xc03001b4, &ixTHM_TMON1_RDIL13_DATA[0], sizeof(ixTHM_TMON1_RDIL13_DATA)/sizeof(ixTHM_TMON1_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL14_DATA", REG_SMC, 0xc03001b8, &ixTHM_TMON1_RDIL14_DATA[0], sizeof(ixTHM_TMON1_RDIL14_DATA)/sizeof(ixTHM_TMON1_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL15_DATA", REG_SMC, 0xc03001bc, &ixTHM_TMON1_RDIL15_DATA[0], sizeof(ixTHM_TMON1_RDIL15_DATA)/sizeof(ixTHM_TMON1_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR0_DATA", REG_SMC, 0xc03001c0, &ixTHM_TMON1_RDIR0_DATA[0], sizeof(ixTHM_TMON1_RDIR0_DATA)/sizeof(ixTHM_TMON1_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR1_DATA", REG_SMC, 0xc03001c4, &ixTHM_TMON1_RDIR1_DATA[0], sizeof(ixTHM_TMON1_RDIR1_DATA)/sizeof(ixTHM_TMON1_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR2_DATA", REG_SMC, 0xc03001c8, &ixTHM_TMON1_RDIR2_DATA[0], sizeof(ixTHM_TMON1_RDIR2_DATA)/sizeof(ixTHM_TMON1_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR3_DATA", REG_SMC, 0xc03001cc, &ixTHM_TMON1_RDIR3_DATA[0], sizeof(ixTHM_TMON1_RDIR3_DATA)/sizeof(ixTHM_TMON1_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR4_DATA", REG_SMC, 0xc03001d0, &ixTHM_TMON1_RDIR4_DATA[0], sizeof(ixTHM_TMON1_RDIR4_DATA)/sizeof(ixTHM_TMON1_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR5_DATA", REG_SMC, 0xc03001d4, &ixTHM_TMON1_RDIR5_DATA[0], sizeof(ixTHM_TMON1_RDIR5_DATA)/sizeof(ixTHM_TMON1_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR6_DATA", REG_SMC, 0xc03001d8, &ixTHM_TMON1_RDIR6_DATA[0], sizeof(ixTHM_TMON1_RDIR6_DATA)/sizeof(ixTHM_TMON1_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR7_DATA", REG_SMC, 0xc03001dc, &ixTHM_TMON1_RDIR7_DATA[0], sizeof(ixTHM_TMON1_RDIR7_DATA)/sizeof(ixTHM_TMON1_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR8_DATA", REG_SMC, 0xc03001e0, &ixTHM_TMON1_RDIR8_DATA[0], sizeof(ixTHM_TMON1_RDIR8_DATA)/sizeof(ixTHM_TMON1_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR9_DATA", REG_SMC, 0xc03001e4, &ixTHM_TMON1_RDIR9_DATA[0], sizeof(ixTHM_TMON1_RDIR9_DATA)/sizeof(ixTHM_TMON1_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR10_DATA", REG_SMC, 0xc03001e8, &ixTHM_TMON1_RDIR10_DATA[0], sizeof(ixTHM_TMON1_RDIR10_DATA)/sizeof(ixTHM_TMON1_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR11_DATA", REG_SMC, 0xc03001ec, &ixTHM_TMON1_RDIR11_DATA[0], sizeof(ixTHM_TMON1_RDIR11_DATA)/sizeof(ixTHM_TMON1_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR12_DATA", REG_SMC, 0xc03001f0, &ixTHM_TMON1_RDIR12_DATA[0], sizeof(ixTHM_TMON1_RDIR12_DATA)/sizeof(ixTHM_TMON1_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR13_DATA", REG_SMC, 0xc03001f4, &ixTHM_TMON1_RDIR13_DATA[0], sizeof(ixTHM_TMON1_RDIR13_DATA)/sizeof(ixTHM_TMON1_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR14_DATA", REG_SMC, 0xc03001f8, &ixTHM_TMON1_RDIR14_DATA[0], sizeof(ixTHM_TMON1_RDIR14_DATA)/sizeof(ixTHM_TMON1_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR15_DATA", REG_SMC, 0xc03001fc, &ixTHM_TMON1_RDIR15_DATA[0], sizeof(ixTHM_TMON1_RDIR15_DATA)/sizeof(ixTHM_TMON1_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_INT_DATA", REG_SMC, 0xc0300300, &ixTHM_TMON0_INT_DATA[0], sizeof(ixTHM_TMON0_INT_DATA)/sizeof(ixTHM_TMON0_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_INT_DATA", REG_SMC, 0xc0300304, &ixTHM_TMON1_INT_DATA[0], sizeof(ixTHM_TMON1_INT_DATA)/sizeof(ixTHM_TMON1_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_DEBUG", REG_SMC, 0xc0300310, &ixTHM_TMON0_DEBUG[0], sizeof(ixTHM_TMON0_DEBUG)/sizeof(ixTHM_TMON0_DEBUG[0]), 0, 0 },
+	{ "ixTHM_TMON1_DEBUG", REG_SMC, 0xc0300314, &ixTHM_TMON1_DEBUG[0], sizeof(ixTHM_TMON1_DEBUG)/sizeof(ixTHM_TMON1_DEBUG[0]), 0, 0 },
+	{ "ixLCAC_SX0_CNTL", REG_SMC, 0xc0400d00, &ixLCAC_SX0_CNTL[0], sizeof(ixLCAC_SX0_CNTL)/sizeof(ixLCAC_SX0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_SX0_OVR_SEL", REG_SMC, 0xc0400d04, &ixLCAC_SX0_OVR_SEL[0], sizeof(ixLCAC_SX0_OVR_SEL)/sizeof(ixLCAC_SX0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_SX0_OVR_VAL", REG_SMC, 0xc0400d08, &ixLCAC_SX0_OVR_VAL[0], sizeof(ixLCAC_SX0_OVR_VAL)/sizeof(ixLCAC_SX0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC0_CNTL", REG_SMC, 0xc0400d30, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0xc0400d34, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0xc0400d38, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC1_CNTL", REG_SMC, 0xc0400d3c, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0xc0400d40, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0xc0400d44, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC2_CNTL", REG_SMC, 0xc0400d48, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0xc0400d4c, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0xc0400d50, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC3_CNTL", REG_SMC, 0xc0400d54, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0xc0400d58, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0xc0400d5c, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_CPL_CNTL", REG_SMC, 0xc0400d80, &ixLCAC_CPL_CNTL[0], sizeof(ixLCAC_CPL_CNTL)/sizeof(ixLCAC_CPL_CNTL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_SEL", REG_SMC, 0xc0400d84, &ixLCAC_CPL_OVR_SEL[0], sizeof(ixLCAC_CPL_OVR_SEL)/sizeof(ixLCAC_CPL_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_VAL", REG_SMC, 0xc0400d88, &ixLCAC_CPL_OVR_VAL[0], sizeof(ixLCAC_CPL_OVR_VAL)/sizeof(ixLCAC_CPL_OVR_VAL[0]), 0, 0 },
+	{ "ixCG_DCLK_CNTL", REG_SMC, 0xc050009c, &ixCG_DCLK_CNTL[0], sizeof(ixCG_DCLK_CNTL)/sizeof(ixCG_DCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_DCLK_STATUS", REG_SMC, 0xc05000a0, &ixCG_DCLK_STATUS[0], sizeof(ixCG_DCLK_STATUS)/sizeof(ixCG_DCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_VCLK_CNTL", REG_SMC, 0xc05000a4, &ixCG_VCLK_CNTL[0], sizeof(ixCG_VCLK_CNTL)/sizeof(ixCG_VCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_VCLK_STATUS", REG_SMC, 0xc05000a8, &ixCG_VCLK_STATUS[0], sizeof(ixCG_VCLK_STATUS)/sizeof(ixCG_VCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ECLK_CNTL", REG_SMC, 0xc05000ac, &ixCG_ECLK_CNTL[0], sizeof(ixCG_ECLK_CNTL)/sizeof(ixCG_ECLK_CNTL[0]), 0, 0 },
+	{ "ixCG_ECLK_STATUS", REG_SMC, 0xc05000b0, &ixCG_ECLK_STATUS[0], sizeof(ixCG_ECLK_STATUS)/sizeof(ixCG_ECLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ACLK_CNTL", REG_SMC, 0xc05000dc, &ixCG_ACLK_CNTL[0], sizeof(ixCG_ACLK_CNTL)/sizeof(ixCG_ACLK_CNTL[0]), 0, 0 },
+	{ "ixGCK_DFS_BYPASS_CNTL", REG_SMC, 0xc0500118, &ixGCK_DFS_BYPASS_CNTL[0], sizeof(ixGCK_DFS_BYPASS_CNTL)/sizeof(ixGCK_DFS_BYPASS_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL", REG_SMC, 0xc0500140, &ixCG_SPLL_FUNC_CNTL[0], sizeof(ixCG_SPLL_FUNC_CNTL)/sizeof(ixCG_SPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_2", REG_SMC, 0xc0500144, &ixCG_SPLL_FUNC_CNTL_2[0], sizeof(ixCG_SPLL_FUNC_CNTL_2)/sizeof(ixCG_SPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_3", REG_SMC, 0xc0500148, &ixCG_SPLL_FUNC_CNTL_3[0], sizeof(ixCG_SPLL_FUNC_CNTL_3)/sizeof(ixCG_SPLL_FUNC_CNTL_3[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_4", REG_SMC, 0xc050014c, &ixCG_SPLL_FUNC_CNTL_4[0], sizeof(ixCG_SPLL_FUNC_CNTL_4)/sizeof(ixCG_SPLL_FUNC_CNTL_4[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_5", REG_SMC, 0xc0500150, &ixCG_SPLL_FUNC_CNTL_5[0], sizeof(ixCG_SPLL_FUNC_CNTL_5)/sizeof(ixCG_SPLL_FUNC_CNTL_5[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_6", REG_SMC, 0xc0500154, &ixCG_SPLL_FUNC_CNTL_6[0], sizeof(ixCG_SPLL_FUNC_CNTL_6)/sizeof(ixCG_SPLL_FUNC_CNTL_6[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_7", REG_SMC, 0xc0500158, &ixCG_SPLL_FUNC_CNTL_7[0], sizeof(ixCG_SPLL_FUNC_CNTL_7)/sizeof(ixCG_SPLL_FUNC_CNTL_7[0]), 0, 0 },
+	{ "ixSPLL_CNTL_MODE", REG_SMC, 0xc0500160, &ixSPLL_CNTL_MODE[0], sizeof(ixSPLL_CNTL_MODE)/sizeof(ixSPLL_CNTL_MODE[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM", REG_SMC, 0xc0500164, &ixCG_SPLL_SPREAD_SPECTRUM[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM_2", REG_SMC, 0xc0500168, &ixCG_SPLL_SPREAD_SPECTRUM_2[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2[0]), 0, 0 },
+	{ "ixMPLL_BYPASSCLK_SEL", REG_SMC, 0xc050019c, &ixMPLL_BYPASSCLK_SEL[0], sizeof(ixMPLL_BYPASSCLK_SEL)/sizeof(ixMPLL_BYPASSCLK_SEL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL", REG_SMC, 0xc05001a0, &ixCG_CLKPIN_CNTL[0], sizeof(ixCG_CLKPIN_CNTL)/sizeof(ixCG_CLKPIN_CNTL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_2", REG_SMC, 0xc05001a4, &ixCG_CLKPIN_CNTL_2[0], sizeof(ixCG_CLKPIN_CNTL_2)/sizeof(ixCG_CLKPIN_CNTL_2[0]), 0, 0 },
+	{ "ixTHM_CLK_CNTL", REG_SMC, 0xc05001a8, &ixTHM_CLK_CNTL[0], sizeof(ixTHM_CLK_CNTL)/sizeof(ixTHM_CLK_CNTL[0]), 0, 0 },
+	{ "ixMISC_CLK_CTRL", REG_SMC, 0xc05001ac, &ixMISC_CLK_CTRL[0], sizeof(ixMISC_CLK_CTRL)/sizeof(ixMISC_CLK_CTRL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL", REG_SMC, 0xc05001c0, &ixGCK_PLL_TEST_CNTL[0], sizeof(ixGCK_PLL_TEST_CNTL)/sizeof(ixGCK_PLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL_2", REG_SMC, 0xc05001c4, &ixGCK_PLL_TEST_CNTL_2[0], sizeof(ixGCK_PLL_TEST_CNTL_2)/sizeof(ixGCK_PLL_TEST_CNTL_2[0]), 0, 0 },
+	{ "ixGCK_ADFS_CLK_BYPASS_CNTL1", REG_SMC, 0xc05001c8, &ixGCK_ADFS_CLK_BYPASS_CNTL1[0], sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1)/sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_DC", REG_SMC, 0xc0500204, &ixCG_CLKPIN_CNTL_DC[0], sizeof(ixCG_CLKPIN_CNTL_DC)/sizeof(ixCG_CLKPIN_CNTL_DC[0]), 0, 0 },
+	{ "ixROM_CNTL", REG_SMC, 0xc0600000, &ixROM_CNTL[0], sizeof(ixROM_CNTL)/sizeof(ixROM_CNTL[0]), 0, 0 },
+	{ "ixPAGE_MIRROR_CNTL", REG_SMC, 0xc0600004, &ixPAGE_MIRROR_CNTL[0], sizeof(ixPAGE_MIRROR_CNTL)/sizeof(ixPAGE_MIRROR_CNTL[0]), 0, 0 },
+	{ "ixROM_STATUS", REG_SMC, 0xc0600008, &ixROM_STATUS[0], sizeof(ixROM_STATUS)/sizeof(ixROM_STATUS[0]), 0, 0 },
+	{ "ixCGTT_ROM_CLK_CTRL0", REG_SMC, 0xc060000c, &ixCGTT_ROM_CLK_CTRL0[0], sizeof(ixCGTT_ROM_CLK_CTRL0)/sizeof(ixCGTT_ROM_CLK_CTRL0[0]), 0, 0 },
+	{ "ixROM_INDEX", REG_SMC, 0xc0600010, &ixROM_INDEX[0], sizeof(ixROM_INDEX)/sizeof(ixROM_INDEX[0]), 0, 0 },
+	{ "ixROM_DATA", REG_SMC, 0xc0600014, &ixROM_DATA[0], sizeof(ixROM_DATA)/sizeof(ixROM_DATA[0]), 0, 0 },
+	{ "ixROM_START", REG_SMC, 0xc0600018, &ixROM_START[0], sizeof(ixROM_START)/sizeof(ixROM_START[0]), 0, 0 },
+	{ "ixROM_SW_CNTL", REG_SMC, 0xc060001c, &ixROM_SW_CNTL[0], sizeof(ixROM_SW_CNTL)/sizeof(ixROM_SW_CNTL[0]), 0, 0 },
+	{ "ixROM_SW_STATUS", REG_SMC, 0xc0600020, &ixROM_SW_STATUS[0], sizeof(ixROM_SW_STATUS)/sizeof(ixROM_SW_STATUS[0]), 0, 0 },
+	{ "ixROM_SW_COMMAND", REG_SMC, 0xc0600024, &ixROM_SW_COMMAND[0], sizeof(ixROM_SW_COMMAND)/sizeof(ixROM_SW_COMMAND[0]), 0, 0 },
+	{ "ixROM_SW_DATA_1", REG_SMC, 0xc0600028, &ixROM_SW_DATA_1[0], sizeof(ixROM_SW_DATA_1)/sizeof(ixROM_SW_DATA_1[0]), 0, 0 },
+	{ "ixROM_SW_DATA_2", REG_SMC, 0xc060002c, &ixROM_SW_DATA_2[0], sizeof(ixROM_SW_DATA_2)/sizeof(ixROM_SW_DATA_2[0]), 0, 0 },
+	{ "ixROM_SW_DATA_3", REG_SMC, 0xc0600030, &ixROM_SW_DATA_3[0], sizeof(ixROM_SW_DATA_3)/sizeof(ixROM_SW_DATA_3[0]), 0, 0 },
+	{ "ixROM_SW_DATA_4", REG_SMC, 0xc0600034, &ixROM_SW_DATA_4[0], sizeof(ixROM_SW_DATA_4)/sizeof(ixROM_SW_DATA_4[0]), 0, 0 },
+	{ "ixROM_SW_DATA_5", REG_SMC, 0xc0600038, &ixROM_SW_DATA_5[0], sizeof(ixROM_SW_DATA_5)/sizeof(ixROM_SW_DATA_5[0]), 0, 0 },
+	{ "ixROM_SW_DATA_6", REG_SMC, 0xc060003c, &ixROM_SW_DATA_6[0], sizeof(ixROM_SW_DATA_6)/sizeof(ixROM_SW_DATA_6[0]), 0, 0 },
+	{ "ixROM_SW_DATA_7", REG_SMC, 0xc0600040, &ixROM_SW_DATA_7[0], sizeof(ixROM_SW_DATA_7)/sizeof(ixROM_SW_DATA_7[0]), 0, 0 },
+	{ "ixROM_SW_DATA_8", REG_SMC, 0xc0600044, &ixROM_SW_DATA_8[0], sizeof(ixROM_SW_DATA_8)/sizeof(ixROM_SW_DATA_8[0]), 0, 0 },
+	{ "ixROM_SW_DATA_9", REG_SMC, 0xc0600048, &ixROM_SW_DATA_9[0], sizeof(ixROM_SW_DATA_9)/sizeof(ixROM_SW_DATA_9[0]), 0, 0 },
+	{ "ixROM_SW_DATA_10", REG_SMC, 0xc060004c, &ixROM_SW_DATA_10[0], sizeof(ixROM_SW_DATA_10)/sizeof(ixROM_SW_DATA_10[0]), 0, 0 },
+	{ "ixROM_SW_DATA_11", REG_SMC, 0xc0600050, &ixROM_SW_DATA_11[0], sizeof(ixROM_SW_DATA_11)/sizeof(ixROM_SW_DATA_11[0]), 0, 0 },
+	{ "ixROM_SW_DATA_12", REG_SMC, 0xc0600054, &ixROM_SW_DATA_12[0], sizeof(ixROM_SW_DATA_12)/sizeof(ixROM_SW_DATA_12[0]), 0, 0 },
+	{ "ixROM_SW_DATA_13", REG_SMC, 0xc0600058, &ixROM_SW_DATA_13[0], sizeof(ixROM_SW_DATA_13)/sizeof(ixROM_SW_DATA_13[0]), 0, 0 },
+	{ "ixROM_SW_DATA_14", REG_SMC, 0xc060005c, &ixROM_SW_DATA_14[0], sizeof(ixROM_SW_DATA_14)/sizeof(ixROM_SW_DATA_14[0]), 0, 0 },
+	{ "ixROM_SW_DATA_15", REG_SMC, 0xc0600060, &ixROM_SW_DATA_15[0], sizeof(ixROM_SW_DATA_15)/sizeof(ixROM_SW_DATA_15[0]), 0, 0 },
+	{ "ixROM_SW_DATA_16", REG_SMC, 0xc0600064, &ixROM_SW_DATA_16[0], sizeof(ixROM_SW_DATA_16)/sizeof(ixROM_SW_DATA_16[0]), 0, 0 },
+	{ "ixROM_SW_DATA_17", REG_SMC, 0xc0600068, &ixROM_SW_DATA_17[0], sizeof(ixROM_SW_DATA_17)/sizeof(ixROM_SW_DATA_17[0]), 0, 0 },
+	{ "ixROM_SW_DATA_18", REG_SMC, 0xc060006c, &ixROM_SW_DATA_18[0], sizeof(ixROM_SW_DATA_18)/sizeof(ixROM_SW_DATA_18[0]), 0, 0 },
+	{ "ixROM_SW_DATA_19", REG_SMC, 0xc0600070, &ixROM_SW_DATA_19[0], sizeof(ixROM_SW_DATA_19)/sizeof(ixROM_SW_DATA_19[0]), 0, 0 },
+	{ "ixROM_SW_DATA_20", REG_SMC, 0xc0600074, &ixROM_SW_DATA_20[0], sizeof(ixROM_SW_DATA_20)/sizeof(ixROM_SW_DATA_20[0]), 0, 0 },
+	{ "ixROM_SW_DATA_21", REG_SMC, 0xc0600078, &ixROM_SW_DATA_21[0], sizeof(ixROM_SW_DATA_21)/sizeof(ixROM_SW_DATA_21[0]), 0, 0 },
+	{ "ixROM_SW_DATA_22", REG_SMC, 0xc060007c, &ixROM_SW_DATA_22[0], sizeof(ixROM_SW_DATA_22)/sizeof(ixROM_SW_DATA_22[0]), 0, 0 },
+	{ "ixROM_SW_DATA_23", REG_SMC, 0xc0600080, &ixROM_SW_DATA_23[0], sizeof(ixROM_SW_DATA_23)/sizeof(ixROM_SW_DATA_23[0]), 0, 0 },
+	{ "ixROM_SW_DATA_24", REG_SMC, 0xc0600084, &ixROM_SW_DATA_24[0], sizeof(ixROM_SW_DATA_24)/sizeof(ixROM_SW_DATA_24[0]), 0, 0 },
+	{ "ixROM_SW_DATA_25", REG_SMC, 0xc0600088, &ixROM_SW_DATA_25[0], sizeof(ixROM_SW_DATA_25)/sizeof(ixROM_SW_DATA_25[0]), 0, 0 },
+	{ "ixROM_SW_DATA_26", REG_SMC, 0xc060008c, &ixROM_SW_DATA_26[0], sizeof(ixROM_SW_DATA_26)/sizeof(ixROM_SW_DATA_26[0]), 0, 0 },
+	{ "ixROM_SW_DATA_27", REG_SMC, 0xc0600090, &ixROM_SW_DATA_27[0], sizeof(ixROM_SW_DATA_27)/sizeof(ixROM_SW_DATA_27[0]), 0, 0 },
+	{ "ixROM_SW_DATA_28", REG_SMC, 0xc0600094, &ixROM_SW_DATA_28[0], sizeof(ixROM_SW_DATA_28)/sizeof(ixROM_SW_DATA_28[0]), 0, 0 },
+	{ "ixROM_SW_DATA_29", REG_SMC, 0xc0600098, &ixROM_SW_DATA_29[0], sizeof(ixROM_SW_DATA_29)/sizeof(ixROM_SW_DATA_29[0]), 0, 0 },
+	{ "ixROM_SW_DATA_30", REG_SMC, 0xc060009c, &ixROM_SW_DATA_30[0], sizeof(ixROM_SW_DATA_30)/sizeof(ixROM_SW_DATA_30[0]), 0, 0 },
+	{ "ixROM_SW_DATA_31", REG_SMC, 0xc06000a0, &ixROM_SW_DATA_31[0], sizeof(ixROM_SW_DATA_31)/sizeof(ixROM_SW_DATA_31[0]), 0, 0 },
+	{ "ixROM_SW_DATA_32", REG_SMC, 0xc06000a4, &ixROM_SW_DATA_32[0], sizeof(ixROM_SW_DATA_32)/sizeof(ixROM_SW_DATA_32[0]), 0, 0 },
+	{ "ixROM_SW_DATA_33", REG_SMC, 0xc06000a8, &ixROM_SW_DATA_33[0], sizeof(ixROM_SW_DATA_33)/sizeof(ixROM_SW_DATA_33[0]), 0, 0 },
+	{ "ixROM_SW_DATA_34", REG_SMC, 0xc06000ac, &ixROM_SW_DATA_34[0], sizeof(ixROM_SW_DATA_34)/sizeof(ixROM_SW_DATA_34[0]), 0, 0 },
+	{ "ixROM_SW_DATA_35", REG_SMC, 0xc06000b0, &ixROM_SW_DATA_35[0], sizeof(ixROM_SW_DATA_35)/sizeof(ixROM_SW_DATA_35[0]), 0, 0 },
+	{ "ixROM_SW_DATA_36", REG_SMC, 0xc06000b4, &ixROM_SW_DATA_36[0], sizeof(ixROM_SW_DATA_36)/sizeof(ixROM_SW_DATA_36[0]), 0, 0 },
+	{ "ixROM_SW_DATA_37", REG_SMC, 0xc06000b8, &ixROM_SW_DATA_37[0], sizeof(ixROM_SW_DATA_37)/sizeof(ixROM_SW_DATA_37[0]), 0, 0 },
+	{ "ixROM_SW_DATA_38", REG_SMC, 0xc06000bc, &ixROM_SW_DATA_38[0], sizeof(ixROM_SW_DATA_38)/sizeof(ixROM_SW_DATA_38[0]), 0, 0 },
+	{ "ixROM_SW_DATA_39", REG_SMC, 0xc06000c0, &ixROM_SW_DATA_39[0], sizeof(ixROM_SW_DATA_39)/sizeof(ixROM_SW_DATA_39[0]), 0, 0 },
+	{ "ixROM_SW_DATA_40", REG_SMC, 0xc06000c4, &ixROM_SW_DATA_40[0], sizeof(ixROM_SW_DATA_40)/sizeof(ixROM_SW_DATA_40[0]), 0, 0 },
+	{ "ixROM_SW_DATA_41", REG_SMC, 0xc06000c8, &ixROM_SW_DATA_41[0], sizeof(ixROM_SW_DATA_41)/sizeof(ixROM_SW_DATA_41[0]), 0, 0 },
+	{ "ixROM_SW_DATA_42", REG_SMC, 0xc06000cc, &ixROM_SW_DATA_42[0], sizeof(ixROM_SW_DATA_42)/sizeof(ixROM_SW_DATA_42[0]), 0, 0 },
+	{ "ixROM_SW_DATA_43", REG_SMC, 0xc06000d0, &ixROM_SW_DATA_43[0], sizeof(ixROM_SW_DATA_43)/sizeof(ixROM_SW_DATA_43[0]), 0, 0 },
+	{ "ixROM_SW_DATA_44", REG_SMC, 0xc06000d4, &ixROM_SW_DATA_44[0], sizeof(ixROM_SW_DATA_44)/sizeof(ixROM_SW_DATA_44[0]), 0, 0 },
+	{ "ixROM_SW_DATA_45", REG_SMC, 0xc06000d8, &ixROM_SW_DATA_45[0], sizeof(ixROM_SW_DATA_45)/sizeof(ixROM_SW_DATA_45[0]), 0, 0 },
+	{ "ixROM_SW_DATA_46", REG_SMC, 0xc06000dc, &ixROM_SW_DATA_46[0], sizeof(ixROM_SW_DATA_46)/sizeof(ixROM_SW_DATA_46[0]), 0, 0 },
+	{ "ixROM_SW_DATA_47", REG_SMC, 0xc06000e0, &ixROM_SW_DATA_47[0], sizeof(ixROM_SW_DATA_47)/sizeof(ixROM_SW_DATA_47[0]), 0, 0 },
+	{ "ixROM_SW_DATA_48", REG_SMC, 0xc06000e4, &ixROM_SW_DATA_48[0], sizeof(ixROM_SW_DATA_48)/sizeof(ixROM_SW_DATA_48[0]), 0, 0 },
+	{ "ixROM_SW_DATA_49", REG_SMC, 0xc06000e8, &ixROM_SW_DATA_49[0], sizeof(ixROM_SW_DATA_49)/sizeof(ixROM_SW_DATA_49[0]), 0, 0 },
+	{ "ixROM_SW_DATA_50", REG_SMC, 0xc06000ec, &ixROM_SW_DATA_50[0], sizeof(ixROM_SW_DATA_50)/sizeof(ixROM_SW_DATA_50[0]), 0, 0 },
+	{ "ixROM_SW_DATA_51", REG_SMC, 0xc06000f0, &ixROM_SW_DATA_51[0], sizeof(ixROM_SW_DATA_51)/sizeof(ixROM_SW_DATA_51[0]), 0, 0 },
+	{ "ixROM_SW_DATA_52", REG_SMC, 0xc06000f4, &ixROM_SW_DATA_52[0], sizeof(ixROM_SW_DATA_52)/sizeof(ixROM_SW_DATA_52[0]), 0, 0 },
+	{ "ixROM_SW_DATA_53", REG_SMC, 0xc06000f8, &ixROM_SW_DATA_53[0], sizeof(ixROM_SW_DATA_53)/sizeof(ixROM_SW_DATA_53[0]), 0, 0 },
+	{ "ixROM_SW_DATA_54", REG_SMC, 0xc06000fc, &ixROM_SW_DATA_54[0], sizeof(ixROM_SW_DATA_54)/sizeof(ixROM_SW_DATA_54[0]), 0, 0 },
+	{ "ixROM_SW_DATA_55", REG_SMC, 0xc0600100, &ixROM_SW_DATA_55[0], sizeof(ixROM_SW_DATA_55)/sizeof(ixROM_SW_DATA_55[0]), 0, 0 },
+	{ "ixROM_SW_DATA_56", REG_SMC, 0xc0600104, &ixROM_SW_DATA_56[0], sizeof(ixROM_SW_DATA_56)/sizeof(ixROM_SW_DATA_56[0]), 0, 0 },
+	{ "ixROM_SW_DATA_57", REG_SMC, 0xc0600108, &ixROM_SW_DATA_57[0], sizeof(ixROM_SW_DATA_57)/sizeof(ixROM_SW_DATA_57[0]), 0, 0 },
+	{ "ixROM_SW_DATA_58", REG_SMC, 0xc060010c, &ixROM_SW_DATA_58[0], sizeof(ixROM_SW_DATA_58)/sizeof(ixROM_SW_DATA_58[0]), 0, 0 },
+	{ "ixROM_SW_DATA_59", REG_SMC, 0xc0600110, &ixROM_SW_DATA_59[0], sizeof(ixROM_SW_DATA_59)/sizeof(ixROM_SW_DATA_59[0]), 0, 0 },
+	{ "ixROM_SW_DATA_60", REG_SMC, 0xc0600114, &ixROM_SW_DATA_60[0], sizeof(ixROM_SW_DATA_60)/sizeof(ixROM_SW_DATA_60[0]), 0, 0 },
+	{ "ixROM_SW_DATA_61", REG_SMC, 0xc0600118, &ixROM_SW_DATA_61[0], sizeof(ixROM_SW_DATA_61)/sizeof(ixROM_SW_DATA_61[0]), 0, 0 },
+	{ "ixROM_SW_DATA_62", REG_SMC, 0xc060011c, &ixROM_SW_DATA_62[0], sizeof(ixROM_SW_DATA_62)/sizeof(ixROM_SW_DATA_62[0]), 0, 0 },
+	{ "ixROM_SW_DATA_63", REG_SMC, 0xc0600120, &ixROM_SW_DATA_63[0], sizeof(ixROM_SW_DATA_63)/sizeof(ixROM_SW_DATA_63[0]), 0, 0 },
+	{ "ixROM_SW_DATA_64", REG_SMC, 0xc0600124, &ixROM_SW_DATA_64[0], sizeof(ixROM_SW_DATA_64)/sizeof(ixROM_SW_DATA_64[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, &ixCG_THERMAL_INT_ENA[0], sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, &ixCG_THERMAL_INT_CTRL[0], sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, &ixCG_THERMAL_INT_STATUS[0], sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
+	{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, &ixSMU_MAIN_PLL_OP_FREQ[0], sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
+	{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
+	{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
+	{ "ixSMU_INPUT_DATA", REG_SMC, 0xe00030b8, &ixSMU_INPUT_DATA[0], sizeof(ixSMU_INPUT_DATA)/sizeof(ixSMU_INPUT_DATA[0]), 0, 0 },
diff --git a/src/lib/ip/smu711.c b/src/lib/ip/smu711.c
new file mode 100644
index 0000000..00a9f2b
--- /dev/null
+++ b/src/lib/ip/smu711.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "smu711_bits.i"
+
+static const struct umr_reg smu711_registers[] = {
+#include "smu711_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_smu711(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "smu711";
+	ip->no_regs = sizeof(smu711_registers)/sizeof(smu711_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(smu711_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, smu711_registers, sizeof(smu711_registers));
+	return ip;
+}
diff --git a/src/lib/ip/smu711_bits.i b/src/lib/ip/smu711_bits.i
new file mode 100644
index 0000000..6d80325
--- /dev/null
+++ b/src/lib/ip/smu711_bits.i
@@ -0,0 +1,4530 @@
+static struct umr_bitfield mmGPIOPAD_SW_INT_STAT[] = {
+	 { "SW_INT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_STRENGTH[] = {
+	 { "GPIO_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GPIO_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_MASK[] = {
+	 { "GPIO_MASK", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_A[] = {
+	 { "GPIO_A", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EN[] = {
+	 { "GPIO_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_Y[] = {
+	 { "GPIO_Y", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PINSTRAPS[] = {
+	 { "GPIO_PINSTRAP_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_28", 28, 28, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_29", 29, 29, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_30", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_EN[] = {
+	 { "GPIO_INT_STAT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT[] = {
+	 { "GPIO_INT_STAT", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_AK[] = {
+	 { "GPIO_INT_STAT_AK_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_28", 28, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_AK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_EN[] = {
+	 { "GPIO_INT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_TYPE[] = {
+	 { "GPIO_INT_TYPE", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_POLARITY[] = {
+	 { "GPIO_INT_POLARITY", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_POLARITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EXTERN_TRIG_CNTL[] = {
+	 { "EXTERN_TRIG_SEL", 0, 4, &umr_bitfield_default },
+	 { "EXTERN_TRIG_CLR", 5, 5, &umr_bitfield_default },
+	 { "EXTERN_TRIG_READ", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_RCVR_SEL[] = {
+	 { "GPIO_RCVR_SEL", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PU_EN[] = {
+	 { "GPIO_PU_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PD_EN[] = {
+	 { "GPIO_PD_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCG_FPS_CNT[] = {
+	 { "FPS_CNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFIRMWARE_FLAGS[] = {
+	 { "INTERRUPTS_ENABLED", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 23, &umr_bitfield_default },
+	 { "TEST_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_STATUS[] = {
+	 { "VDD_Boost", 0, 7, &umr_bitfield_default },
+	 { "VDD_Throttle", 8, 15, &umr_bitfield_default },
+	 { "VDDC_Boost", 16, 23, &umr_bitfield_default },
+	 { "VDDC_Throttle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_MV_AVERAGE[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_VRM_LIMIT[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFEATURE_STATUS[] = {
+	 { "SCLK_DPM_ON", 0, 0, &umr_bitfield_default },
+	 { "MCLK_DPM_ON", 1, 1, &umr_bitfield_default },
+	 { "LCLK_DPM_ON", 2, 2, &umr_bitfield_default },
+	 { "UVD_DPM_ON", 3, 3, &umr_bitfield_default },
+	 { "VCE_DPM_ON", 4, 4, &umr_bitfield_default },
+	 { "SAMU_DPM_ON", 5, 5, &umr_bitfield_default },
+	 { "ACP_DPM_ON", 6, 6, &umr_bitfield_default },
+	 { "PCIE_DPM_ON", 7, 7, &umr_bitfield_default },
+	 { "BAPM_ON", 8, 8, &umr_bitfield_default },
+	 { "LPMX_ON", 9, 9, &umr_bitfield_default },
+	 { "NBDPM_ON", 10, 10, &umr_bitfield_default },
+	 { "LHTC_ON", 11, 11, &umr_bitfield_default },
+	 { "VPC_ON", 12, 12, &umr_bitfield_default },
+	 { "VOLTAGE_CONTROLLER_ON", 13, 13, &umr_bitfield_default },
+	 { "TDC_LIMIT_ON", 14, 14, &umr_bitfield_default },
+	 { "GPU_CAC_ON", 15, 15, &umr_bitfield_default },
+	 { "AVS_ON", 16, 16, &umr_bitfield_default },
+	 { "SPMI_ON", 17, 17, &umr_bitfield_default },
+	 { "SCLK_DPM_FORCED", 18, 18, &umr_bitfield_default },
+	 { "MCLK_DPM_FORCED", 19, 19, &umr_bitfield_default },
+	 { "LCLK_DPM_FORCED", 20, 20, &umr_bitfield_default },
+	 { "PCIE_DPM_FORCED", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixENTITY_TEMPERATURES_1[] = {
+	 { "GPU", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_1[] = {
+	 { "entries_0_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_2[] = {
+	 { "entries_0_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_3[] = {
+	 { "entries_0_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_4[] = {
+	 { "entries_0_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_5[] = {
+	 { "entries_0_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_6[] = {
+	 { "entries_0_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_7[] = {
+	 { "entries_0_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_8[] = {
+	 { "entries_0_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_9[] = {
+	 { "entries_0_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_10[] = {
+	 { "entries_0_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_11[] = {
+	 { "entries_0_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_12[] = {
+	 { "entries_0_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_13[] = {
+	 { "entries_1_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_14[] = {
+	 { "entries_1_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_15[] = {
+	 { "entries_1_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_16[] = {
+	 { "entries_1_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_17[] = {
+	 { "entries_1_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_18[] = {
+	 { "entries_1_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_19[] = {
+	 { "entries_1_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_20[] = {
+	 { "entries_1_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_21[] = {
+	 { "entries_1_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_22[] = {
+	 { "entries_1_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_23[] = {
+	 { "entries_1_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_24[] = {
+	 { "entries_1_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_25[] = {
+	 { "entries_2_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_26[] = {
+	 { "entries_2_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_27[] = {
+	 { "entries_2_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_28[] = {
+	 { "entries_2_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_29[] = {
+	 { "entries_2_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_30[] = {
+	 { "entries_2_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_31[] = {
+	 { "entries_2_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_32[] = {
+	 { "entries_2_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_33[] = {
+	 { "entries_2_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_34[] = {
+	 { "entries_2_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_35[] = {
+	 { "entries_2_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_36[] = {
+	 { "entries_2_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_37[] = {
+	 { "entries_3_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_38[] = {
+	 { "entries_3_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_39[] = {
+	 { "entries_3_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_40[] = {
+	 { "entries_3_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_41[] = {
+	 { "entries_3_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_42[] = {
+	 { "entries_3_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_43[] = {
+	 { "entries_3_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_44[] = {
+	 { "entries_3_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_45[] = {
+	 { "entries_3_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_46[] = {
+	 { "entries_3_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_47[] = {
+	 { "entries_3_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_48[] = {
+	 { "entries_3_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_49[] = {
+	 { "entries_4_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_50[] = {
+	 { "entries_4_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_51[] = {
+	 { "entries_4_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_52[] = {
+	 { "entries_4_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_53[] = {
+	 { "entries_4_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_54[] = {
+	 { "entries_4_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_55[] = {
+	 { "entries_4_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_56[] = {
+	 { "entries_4_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_57[] = {
+	 { "entries_4_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_58[] = {
+	 { "entries_4_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_59[] = {
+	 { "entries_4_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_60[] = {
+	 { "entries_4_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_61[] = {
+	 { "entries_5_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_62[] = {
+	 { "entries_5_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_63[] = {
+	 { "entries_5_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_64[] = {
+	 { "entries_5_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_65[] = {
+	 { "entries_5_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_66[] = {
+	 { "entries_5_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_67[] = {
+	 { "entries_5_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_68[] = {
+	 { "entries_5_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_69[] = {
+	 { "entries_5_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_70[] = {
+	 { "entries_5_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_71[] = {
+	 { "entries_5_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_72[] = {
+	 { "entries_5_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_73[] = {
+	 { "entries_6_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_74[] = {
+	 { "entries_6_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_75[] = {
+	 { "entries_6_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_76[] = {
+	 { "entries_6_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_77[] = {
+	 { "entries_6_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_78[] = {
+	 { "entries_6_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_79[] = {
+	 { "entries_6_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_80[] = {
+	 { "entries_6_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_81[] = {
+	 { "entries_6_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_82[] = {
+	 { "entries_6_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_83[] = {
+	 { "entries_6_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_84[] = {
+	 { "entries_6_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_85[] = {
+	 { "entries_7_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_86[] = {
+	 { "entries_7_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_87[] = {
+	 { "entries_7_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_88[] = {
+	 { "entries_7_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_89[] = {
+	 { "entries_7_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_90[] = {
+	 { "entries_7_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_91[] = {
+	 { "entries_7_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_92[] = {
+	 { "entries_7_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_93[] = {
+	 { "entries_7_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_94[] = {
+	 { "entries_7_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_95[] = {
+	 { "entries_7_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_96[] = {
+	 { "entries_7_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_1[] = {
+	 { "reserved_2", 0, 7, &umr_bitfield_default },
+	 { "reserved_1", 8, 15, &umr_bitfield_default },
+	 { "reserved_0", 16, 23, &umr_bitfield_default },
+	 { "last", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_2[] = {
+	 { "address_0_s1", 0, 15, &umr_bitfield_default },
+	 { "address_0_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_3[] = {
+	 { "address_1_s1", 0, 15, &umr_bitfield_default },
+	 { "address_1_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_4[] = {
+	 { "address_2_s1", 0, 15, &umr_bitfield_default },
+	 { "address_2_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_5[] = {
+	 { "address_3_s1", 0, 15, &umr_bitfield_default },
+	 { "address_3_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_6[] = {
+	 { "address_4_s1", 0, 15, &umr_bitfield_default },
+	 { "address_4_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_7[] = {
+	 { "address_5_s1", 0, 15, &umr_bitfield_default },
+	 { "address_5_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_8[] = {
+	 { "address_6_s1", 0, 15, &umr_bitfield_default },
+	 { "address_6_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_9[] = {
+	 { "address_7_s1", 0, 15, &umr_bitfield_default },
+	 { "address_7_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_10[] = {
+	 { "address_8_s1", 0, 15, &umr_bitfield_default },
+	 { "address_8_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_11[] = {
+	 { "address_9_s1", 0, 15, &umr_bitfield_default },
+	 { "address_9_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_12[] = {
+	 { "address_10_s1", 0, 15, &umr_bitfield_default },
+	 { "address_10_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_13[] = {
+	 { "address_11_s1", 0, 15, &umr_bitfield_default },
+	 { "address_11_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_14[] = {
+	 { "address_12_s1", 0, 15, &umr_bitfield_default },
+	 { "address_12_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_15[] = {
+	 { "address_13_s1", 0, 15, &umr_bitfield_default },
+	 { "address_13_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_16[] = {
+	 { "address_14_s1", 0, 15, &umr_bitfield_default },
+	 { "address_14_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_17[] = {
+	 { "address_15_s1", 0, 15, &umr_bitfield_default },
+	 { "address_15_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_18[] = {
+	 { "data_0_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_19[] = {
+	 { "data_0_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_20[] = {
+	 { "data_0_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_21[] = {
+	 { "data_0_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_22[] = {
+	 { "data_0_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_23[] = {
+	 { "data_0_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_24[] = {
+	 { "data_0_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_25[] = {
+	 { "data_0_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_26[] = {
+	 { "data_0_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_27[] = {
+	 { "data_0_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_28[] = {
+	 { "data_0_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_29[] = {
+	 { "data_0_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_30[] = {
+	 { "data_0_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_31[] = {
+	 { "data_0_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_32[] = {
+	 { "data_0_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_33[] = {
+	 { "data_0_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_34[] = {
+	 { "data_1_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_35[] = {
+	 { "data_1_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_36[] = {
+	 { "data_1_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_37[] = {
+	 { "data_1_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_38[] = {
+	 { "data_1_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_39[] = {
+	 { "data_1_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_40[] = {
+	 { "data_1_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_41[] = {
+	 { "data_1_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_42[] = {
+	 { "data_1_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_43[] = {
+	 { "data_1_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_44[] = {
+	 { "data_1_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_45[] = {
+	 { "data_1_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_46[] = {
+	 { "data_1_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_47[] = {
+	 { "data_1_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_48[] = {
+	 { "data_1_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_49[] = {
+	 { "data_1_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_50[] = {
+	 { "data_2_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_51[] = {
+	 { "data_2_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_52[] = {
+	 { "data_2_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_53[] = {
+	 { "data_2_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_54[] = {
+	 { "data_2_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_55[] = {
+	 { "data_2_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_56[] = {
+	 { "data_2_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_57[] = {
+	 { "data_2_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_58[] = {
+	 { "data_2_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_59[] = {
+	 { "data_2_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_60[] = {
+	 { "data_2_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_61[] = {
+	 { "data_2_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_62[] = {
+	 { "data_2_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_63[] = {
+	 { "data_2_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_64[] = {
+	 { "data_2_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_65[] = {
+	 { "data_2_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_66[] = {
+	 { "data_3_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_67[] = {
+	 { "data_3_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_68[] = {
+	 { "data_3_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_69[] = {
+	 { "data_3_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_70[] = {
+	 { "data_3_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_71[] = {
+	 { "data_3_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_72[] = {
+	 { "data_3_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_73[] = {
+	 { "data_3_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_74[] = {
+	 { "data_3_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_75[] = {
+	 { "data_3_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_76[] = {
+	 { "data_3_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_77[] = {
+	 { "data_3_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_78[] = {
+	 { "data_3_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_79[] = {
+	 { "data_3_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_80[] = {
+	 { "data_3_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_81[] = {
+	 { "data_3_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_1[] = {
+	 { "GraphicsPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_2[] = {
+	 { "GraphicsPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_3[] = {
+	 { "GraphicsPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_4[] = {
+	 { "GraphicsPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_5[] = {
+	 { "GraphicsPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_6[] = {
+	 { "GraphicsPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_7[] = {
+	 { "GraphicsPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_8[] = {
+	 { "GraphicsPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_9[] = {
+	 { "GraphicsPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_10[] = {
+	 { "MemoryPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_11[] = {
+	 { "MemoryPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_12[] = {
+	 { "MemoryPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_13[] = {
+	 { "MemoryPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_14[] = {
+	 { "MemoryPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_15[] = {
+	 { "MemoryPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_16[] = {
+	 { "MemoryPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_17[] = {
+	 { "MemoryPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_18[] = {
+	 { "MemoryPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_19[] = {
+	 { "LinkPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_20[] = {
+	 { "LinkPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_21[] = {
+	 { "LinkPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_22[] = {
+	 { "LinkPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_23[] = {
+	 { "LinkPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_24[] = {
+	 { "LinkPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_25[] = {
+	 { "LinkPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_26[] = {
+	 { "LinkPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_27[] = {
+	 { "LinkPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_28[] = {
+	 { "SystemFlags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_29[] = {
+	 { "SmioMaskVddcVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_30[] = {
+	 { "SmioMaskVddcPhase", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_31[] = {
+	 { "SmioMaskVddciVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_32[] = {
+	 { "SmioMaskMvddVid", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_33[] = {
+	 { "VddcLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_34[] = {
+	 { "VddciLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_35[] = {
+	 { "MvddLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_36[] = {
+	 { "VddcLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_37[] = {
+	 { "VddcLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_38[] = {
+	 { "VddcLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_39[] = {
+	 { "VddcLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_40[] = {
+	 { "VddcLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_41[] = {
+	 { "VddcLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_42[] = {
+	 { "VddcLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_43[] = {
+	 { "VddcLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_44[] = {
+	 { "VddcLevel_4_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_4_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_45[] = {
+	 { "VddcLevel_4_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_4_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_4_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_46[] = {
+	 { "VddcLevel_5_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_5_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_47[] = {
+	 { "VddcLevel_5_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_5_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_5_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_48[] = {
+	 { "VddcLevel_6_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_6_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_49[] = {
+	 { "VddcLevel_6_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_6_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_6_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_50[] = {
+	 { "VddcLevel_7_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddcLevel_7_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_51[] = {
+	 { "VddcLevel_7_padding", 0, 7, &umr_bitfield_default },
+	 { "VddcLevel_7_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddcLevel_7_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_52[] = {
+	 { "VddciLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_53[] = {
+	 { "VddciLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_54[] = {
+	 { "VddciLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_55[] = {
+	 { "VddciLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_56[] = {
+	 { "VddciLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_57[] = {
+	 { "VddciLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_58[] = {
+	 { "VddciLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "VddciLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_59[] = {
+	 { "VddciLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "VddciLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "VddciLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_60[] = {
+	 { "MvddLevel_0_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_61[] = {
+	 { "MvddLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_0_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_62[] = {
+	 { "MvddLevel_1_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_63[] = {
+	 { "MvddLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_1_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_64[] = {
+	 { "MvddLevel_2_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_65[] = {
+	 { "MvddLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_2_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_66[] = {
+	 { "MvddLevel_3_StdVoltageHiSidd", 0, 15, &umr_bitfield_default },
+	 { "MvddLevel_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_67[] = {
+	 { "MvddLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "MvddLevel_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "MvddLevel_3_StdVoltageLoSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_68[] = {
+	 { "MasterDeepSleepControl", 0, 7, &umr_bitfield_default },
+	 { "LinkLevelCount", 8, 15, &umr_bitfield_default },
+	 { "MemoryDpmLevelCount", 16, 23, &umr_bitfield_default },
+	 { "GraphicsDpmLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_69[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_70[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_71[] = {
+	 { "Reserved_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_72[] = {
+	 { "Reserved_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_73[] = {
+	 { "Reserved_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_74[] = {
+	 { "GraphicsLevel_0_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_75[] = {
+	 { "GraphicsLevel_0_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_76[] = {
+	 { "GraphicsLevel_0_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_77[] = {
+	 { "GraphicsLevel_0_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_78[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_79[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_80[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_81[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_82[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_83[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_84[] = {
+	 { "GraphicsLevel_0_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_85[] = {
+	 { "GraphicsLevel_0_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_86[] = {
+	 { "GraphicsLevel_1_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_87[] = {
+	 { "GraphicsLevel_1_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_88[] = {
+	 { "GraphicsLevel_1_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_89[] = {
+	 { "GraphicsLevel_1_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_90[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_91[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_92[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_93[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_94[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_95[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_96[] = {
+	 { "GraphicsLevel_1_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_97[] = {
+	 { "GraphicsLevel_1_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_98[] = {
+	 { "GraphicsLevel_2_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_99[] = {
+	 { "GraphicsLevel_2_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_100[] = {
+	 { "GraphicsLevel_2_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_101[] = {
+	 { "GraphicsLevel_2_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_102[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_103[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_104[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_105[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_106[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_107[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_108[] = {
+	 { "GraphicsLevel_2_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_109[] = {
+	 { "GraphicsLevel_2_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_110[] = {
+	 { "GraphicsLevel_3_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_111[] = {
+	 { "GraphicsLevel_3_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_112[] = {
+	 { "GraphicsLevel_3_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_113[] = {
+	 { "GraphicsLevel_3_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_114[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_115[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_116[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_117[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_118[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_119[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_120[] = {
+	 { "GraphicsLevel_3_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_121[] = {
+	 { "GraphicsLevel_3_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_122[] = {
+	 { "GraphicsLevel_4_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_123[] = {
+	 { "GraphicsLevel_4_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_124[] = {
+	 { "GraphicsLevel_4_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_125[] = {
+	 { "GraphicsLevel_4_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_126[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_127[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_128[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_129[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_130[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_131[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_132[] = {
+	 { "GraphicsLevel_4_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_133[] = {
+	 { "GraphicsLevel_4_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_134[] = {
+	 { "GraphicsLevel_5_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_135[] = {
+	 { "GraphicsLevel_5_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_136[] = {
+	 { "GraphicsLevel_5_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_137[] = {
+	 { "GraphicsLevel_5_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_138[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_139[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_140[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_141[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_142[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_143[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_144[] = {
+	 { "GraphicsLevel_5_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_145[] = {
+	 { "GraphicsLevel_5_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_146[] = {
+	 { "GraphicsLevel_6_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_147[] = {
+	 { "GraphicsLevel_6_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_148[] = {
+	 { "GraphicsLevel_6_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_149[] = {
+	 { "GraphicsLevel_6_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_150[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_151[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_152[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_153[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_154[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_155[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_156[] = {
+	 { "GraphicsLevel_6_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_157[] = {
+	 { "GraphicsLevel_6_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_158[] = {
+	 { "GraphicsLevel_7_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_159[] = {
+	 { "GraphicsLevel_7_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_160[] = {
+	 { "GraphicsLevel_7_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_161[] = {
+	 { "GraphicsLevel_7_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_162[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_163[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_164[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_165[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_166[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_167[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_168[] = {
+	 { "GraphicsLevel_7_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_169[] = {
+	 { "GraphicsLevel_7_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_170[] = {
+	 { "MemoryACPILevel_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_171[] = {
+	 { "MemoryACPILevel_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_172[] = {
+	 { "MemoryACPILevel_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_173[] = {
+	 { "MemoryACPILevel_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_174[] = {
+	 { "MemoryACPILevel_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_175[] = {
+	 { "MemoryACPILevel_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_176[] = {
+	 { "MemoryACPILevel_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_177[] = {
+	 { "MemoryACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_178[] = {
+	 { "MemoryACPILevel_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_179[] = {
+	 { "MemoryACPILevel_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_180[] = {
+	 { "MemoryACPILevel_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_181[] = {
+	 { "MemoryACPILevel_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_182[] = {
+	 { "MemoryACPILevel_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_183[] = {
+	 { "MemoryACPILevel_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_184[] = {
+	 { "MemoryACPILevel_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_185[] = {
+	 { "MemoryACPILevel_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_186[] = {
+	 { "MemoryACPILevel_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_187[] = {
+	 { "MemoryACPILevel_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_188[] = {
+	 { "MemoryLevel_0_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_189[] = {
+	 { "MemoryLevel_0_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_190[] = {
+	 { "MemoryLevel_0_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_191[] = {
+	 { "MemoryLevel_0_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_192[] = {
+	 { "MemoryLevel_0_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_193[] = {
+	 { "MemoryLevel_0_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_194[] = {
+	 { "MemoryLevel_0_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_195[] = {
+	 { "MemoryLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_196[] = {
+	 { "MemoryLevel_0_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_197[] = {
+	 { "MemoryLevel_0_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_198[] = {
+	 { "MemoryLevel_0_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_199[] = {
+	 { "MemoryLevel_0_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_200[] = {
+	 { "MemoryLevel_0_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_201[] = {
+	 { "MemoryLevel_0_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_202[] = {
+	 { "MemoryLevel_0_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_203[] = {
+	 { "MemoryLevel_0_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_204[] = {
+	 { "MemoryLevel_0_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_205[] = {
+	 { "MemoryLevel_0_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_206[] = {
+	 { "MemoryLevel_1_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_207[] = {
+	 { "MemoryLevel_1_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_208[] = {
+	 { "MemoryLevel_1_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_209[] = {
+	 { "MemoryLevel_1_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_210[] = {
+	 { "MemoryLevel_1_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_211[] = {
+	 { "MemoryLevel_1_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_212[] = {
+	 { "MemoryLevel_1_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_213[] = {
+	 { "MemoryLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_214[] = {
+	 { "MemoryLevel_1_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_215[] = {
+	 { "MemoryLevel_1_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_216[] = {
+	 { "MemoryLevel_1_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_217[] = {
+	 { "MemoryLevel_1_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_218[] = {
+	 { "MemoryLevel_1_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_219[] = {
+	 { "MemoryLevel_1_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_220[] = {
+	 { "MemoryLevel_1_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_221[] = {
+	 { "MemoryLevel_1_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_222[] = {
+	 { "MemoryLevel_1_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_223[] = {
+	 { "MemoryLevel_1_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_224[] = {
+	 { "MemoryLevel_2_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_225[] = {
+	 { "MemoryLevel_2_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_226[] = {
+	 { "MemoryLevel_2_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_227[] = {
+	 { "MemoryLevel_2_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_228[] = {
+	 { "MemoryLevel_2_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_229[] = {
+	 { "MemoryLevel_2_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_230[] = {
+	 { "MemoryLevel_2_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_231[] = {
+	 { "MemoryLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_232[] = {
+	 { "MemoryLevel_2_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_233[] = {
+	 { "MemoryLevel_2_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_234[] = {
+	 { "MemoryLevel_2_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_235[] = {
+	 { "MemoryLevel_2_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_236[] = {
+	 { "MemoryLevel_2_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_237[] = {
+	 { "MemoryLevel_2_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_238[] = {
+	 { "MemoryLevel_2_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_239[] = {
+	 { "MemoryLevel_2_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_240[] = {
+	 { "MemoryLevel_2_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_241[] = {
+	 { "MemoryLevel_2_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_242[] = {
+	 { "MemoryLevel_3_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_243[] = {
+	 { "MemoryLevel_3_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_244[] = {
+	 { "MemoryLevel_3_MinVddci", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_245[] = {
+	 { "MemoryLevel_3_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_246[] = {
+	 { "MemoryLevel_3_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_247[] = {
+	 { "MemoryLevel_3_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_248[] = {
+	 { "MemoryLevel_3_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_249[] = {
+	 { "MemoryLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_250[] = {
+	 { "MemoryLevel_3_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_251[] = {
+	 { "MemoryLevel_3_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_252[] = {
+	 { "MemoryLevel_3_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_253[] = {
+	 { "MemoryLevel_3_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_254[] = {
+	 { "MemoryLevel_3_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_255[] = {
+	 { "MemoryLevel_3_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_256[] = {
+	 { "MemoryLevel_3_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_257[] = {
+	 { "MemoryLevel_3_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_258[] = {
+	 { "MemoryLevel_3_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_259[] = {
+	 { "MemoryLevel_3_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_260[] = {
+	 { "LinkLevel_0_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_261[] = {
+	 { "LinkLevel_0_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_262[] = {
+	 { "LinkLevel_0_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_263[] = {
+	 { "LinkLevel_0_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_264[] = {
+	 { "LinkLevel_1_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_265[] = {
+	 { "LinkLevel_1_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_266[] = {
+	 { "LinkLevel_1_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_267[] = {
+	 { "LinkLevel_1_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_268[] = {
+	 { "LinkLevel_2_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_269[] = {
+	 { "LinkLevel_2_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_270[] = {
+	 { "LinkLevel_2_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_271[] = {
+	 { "LinkLevel_2_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_272[] = {
+	 { "LinkLevel_3_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_273[] = {
+	 { "LinkLevel_3_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_274[] = {
+	 { "LinkLevel_3_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_275[] = {
+	 { "LinkLevel_3_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_276[] = {
+	 { "LinkLevel_4_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_277[] = {
+	 { "LinkLevel_4_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_278[] = {
+	 { "LinkLevel_4_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_279[] = {
+	 { "LinkLevel_4_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_280[] = {
+	 { "LinkLevel_5_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_281[] = {
+	 { "LinkLevel_5_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_282[] = {
+	 { "LinkLevel_5_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_283[] = {
+	 { "LinkLevel_5_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_284[] = {
+	 { "LinkLevel_6_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_285[] = {
+	 { "LinkLevel_6_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_286[] = {
+	 { "LinkLevel_6_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_287[] = {
+	 { "LinkLevel_6_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_288[] = {
+	 { "LinkLevel_7_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_289[] = {
+	 { "LinkLevel_7_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_290[] = {
+	 { "LinkLevel_7_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_291[] = {
+	 { "LinkLevel_7_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_292[] = {
+	 { "ACPILevel_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_293[] = {
+	 { "ACPILevel_MinVddc", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_294[] = {
+	 { "ACPILevel_MinVddcPhases", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_295[] = {
+	 { "ACPILevel_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_296[] = {
+	 { "ACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_297[] = {
+	 { "ACPILevel_CgSpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_298[] = {
+	 { "ACPILevel_CgSpllFuncCntl2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_299[] = {
+	 { "ACPILevel_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_300[] = {
+	 { "ACPILevel_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_301[] = {
+	 { "ACPILevel_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_302[] = {
+	 { "ACPILevel_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_303[] = {
+	 { "ACPILevel_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_304[] = {
+	 { "ACPILevel_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_305[] = {
+	 { "SclkStepSize", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_306[] = {
+	 { "Smio_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_307[] = {
+	 { "Smio_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_308[] = {
+	 { "Smio_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_309[] = {
+	 { "Smio_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_310[] = {
+	 { "Smio_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_311[] = {
+	 { "Smio_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_312[] = {
+	 { "Smio_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_313[] = {
+	 { "Smio_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_314[] = {
+	 { "Smio_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_315[] = {
+	 { "Smio_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_316[] = {
+	 { "Smio_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_317[] = {
+	 { "Smio_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_318[] = {
+	 { "Smio_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_319[] = {
+	 { "Smio_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_320[] = {
+	 { "Smio_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_321[] = {
+	 { "Smio_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_322[] = {
+	 { "Smio_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_323[] = {
+	 { "Smio_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_324[] = {
+	 { "Smio_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_325[] = {
+	 { "Smio_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_326[] = {
+	 { "Smio_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_327[] = {
+	 { "Smio_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_328[] = {
+	 { "Smio_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_329[] = {
+	 { "Smio_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_330[] = {
+	 { "Smio_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_331[] = {
+	 { "Smio_25", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_332[] = {
+	 { "Smio_26", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_333[] = {
+	 { "Smio_27", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_334[] = {
+	 { "Smio_28", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_335[] = {
+	 { "Smio_29", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_336[] = {
+	 { "Smio_30", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_337[] = {
+	 { "Smio_31", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_338[] = {
+	 { "GraphicsInterval", 0, 7, &umr_bitfield_default },
+	 { "GraphicsThermThrottleEnable", 8, 15, &umr_bitfield_default },
+	 { "GraphicsVoltageChangeEnable", 16, 23, &umr_bitfield_default },
+	 { "GraphicsBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_339[] = {
+	 { "TemperatureLimitHigh", 0, 15, &umr_bitfield_default },
+	 { "ThermalInterval", 16, 23, &umr_bitfield_default },
+	 { "VoltageInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_340[] = {
+	 { "MemoryVoltageChangeEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryBootLevel", 8, 15, &umr_bitfield_default },
+	 { "TemperatureLimitLow", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_341[] = {
+	 { "padding2", 0, 7, &umr_bitfield_default },
+	 { "MergedVddci", 8, 15, &umr_bitfield_default },
+	 { "MemoryThermThrottleEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_342[] = {
+	 { "PhaseResponseTime", 0, 15, &umr_bitfield_default },
+	 { "VoltageResponseTime", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_343[] = {
+	 { "DTEMode", 0, 7, &umr_bitfield_default },
+	 { "DTEInterval", 8, 15, &umr_bitfield_default },
+	 { "PCIeGenInterval", 16, 23, &umr_bitfield_default },
+	 { "PCIeBootLinkLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_344[] = {
+	 { "ThermGpio", 0, 7, &umr_bitfield_default },
+	 { "AcDcGpio", 8, 15, &umr_bitfield_default },
+	 { "VRHotGpio", 16, 23, &umr_bitfield_default },
+	 { "SVI2Enable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_345[] = {
+	 { "DisplayCac", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_346[] = {
+	 { "NomPwr", 0, 15, &umr_bitfield_default },
+	 { "MaxPwr", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_347[] = {
+	 { "FpsLowThreshold", 0, 15, &umr_bitfield_default },
+	 { "FpsHighThreshold", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_348[] = {
+	 { "BAPMTI_R_0_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_349[] = {
+	 { "BAPMTI_R_1_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_350[] = {
+	 { "BAPMTI_R_1_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_1_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_351[] = {
+	 { "BAPMTI_R_2_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_352[] = {
+	 { "BAPMTI_R_3_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_353[] = {
+	 { "BAPMTI_R_3_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_3_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_354[] = {
+	 { "BAPMTI_R_4_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_355[] = {
+	 { "BAPMTI_RC_0_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_356[] = {
+	 { "BAPMTI_RC_0_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_0_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_357[] = {
+	 { "BAPMTI_RC_1_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_358[] = {
+	 { "BAPMTI_RC_2_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_359[] = {
+	 { "BAPMTI_RC_2_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_2_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_360[] = {
+	 { "BAPMTI_RC_3_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_361[] = {
+	 { "BAPMTI_RC_4_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_362[] = {
+	 { "BAPMTI_RC_4_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_4_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_363[] = {
+	 { "GpuTjHyst", 0, 7, &umr_bitfield_default },
+	 { "GpuTjMax", 8, 15, &umr_bitfield_default },
+	 { "DTETjOffset", 16, 23, &umr_bitfield_default },
+	 { "DTEAmbientTempBase", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_364[] = {
+	 { "BootVddci", 0, 15, &umr_bitfield_default },
+	 { "BootVddc", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_365[] = {
+	 { "padding", 0, 15, &umr_bitfield_default },
+	 { "BootMVdd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_366[] = {
+	 { "BAPM_TEMP_GRADIENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_367[] = {
+	 { "LowSclkInterruptThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_368[] = {
+	 { "VddGfxReChkWait", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_369[] = {
+	 { "PPM_TemperatureLimit", 0, 15, &umr_bitfield_default },
+	 { "PPM_PkgPwrLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_370[] = {
+	 { "TargetTdp", 0, 15, &umr_bitfield_default },
+	 { "DefaultTdp", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_1[] = {
+	 { "RefClockFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_2[] = {
+	 { "PmTimerPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_3[] = {
+	 { "FeatureEnables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_4[] = {
+	 { "PreVBlankGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_5[] = {
+	 { "VBlankTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_6[] = {
+	 { "TrainTimeGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_7[] = {
+	 { "MvddSwitchTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_8[] = {
+	 { "LongestAcpiTrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_9[] = {
+	 { "AcpiDelay", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_10[] = {
+	 { "G5TrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_11[] = {
+	 { "DelayMpllPwron", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_12[] = {
+	 { "VoltageChangeTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_13[] = {
+	 { "HandshakeDisables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_14[] = {
+	 { "DisplayPhy4Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy3Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy2Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy1Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_15[] = {
+	 { "DisplayPhy8Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy7Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy6Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy5Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_16[] = {
+	 { "AverageGraphicsActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_17[] = {
+	 { "AverageMemoryActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_18[] = {
+	 { "AverageGioActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_19[] = {
+	 { "PCIeDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "LClkDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "MClkDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "SClkDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_20[] = {
+	 { "DRAM_LOG_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_21[] = {
+	 { "DRAM_LOG_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_22[] = {
+	 { "DRAM_LOG_PHY_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_23[] = {
+	 { "DRAM_LOG_PHY_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_24[] = {
+	 { "DRAM_LOG_BUFF_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_25[] = {
+	 { "UlvEnterCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_26[] = {
+	 { "UlvTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_27[] = {
+	 { "UcodeLoadStatus", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_28[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_29[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_1[] = {
+	 { "BapmVddCVidHiSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_2[] = {
+	 { "BapmVddCVidHiSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidHiSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_3[] = {
+	 { "BapmVddCVidLoSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_4[] = {
+	 { "BapmVddCVidLoSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddCVidLoSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_5[] = {
+	 { "VddCVid_3", 0, 7, &umr_bitfield_default },
+	 { "VddCVid_2", 8, 15, &umr_bitfield_default },
+	 { "VddCVid_1", 16, 23, &umr_bitfield_default },
+	 { "VddCVid_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_6[] = {
+	 { "VddCVid_7", 0, 7, &umr_bitfield_default },
+	 { "VddCVid_6", 8, 15, &umr_bitfield_default },
+	 { "VddCVid_5", 16, 23, &umr_bitfield_default },
+	 { "VddCVid_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_7[] = {
+	 { "SviLoadLineOffsetVddC", 0, 7, &umr_bitfield_default },
+	 { "SviLoadLineTrimVddC", 8, 15, &umr_bitfield_default },
+	 { "SviLoadLineVddC", 16, 23, &umr_bitfield_default },
+	 { "SviLoadLineEn", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_8[] = {
+	 { "TDC_MAWt", 0, 7, &umr_bitfield_default },
+	 { "TDC_VDDC_ThrottleReleaseLimitPerc", 8, 15, &umr_bitfield_default },
+	 { "TDC_VDDC_PkgLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_9[] = {
+	 { "Reserved", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureMax", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureMin", 16, 23, &umr_bitfield_default },
+	 { "TdcWaterfallCtl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_10[] = {
+	 { "LPMLTemperatureScaler_3", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_2", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_1", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_11[] = {
+	 { "LPMLTemperatureScaler_7", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_6", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_5", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_12[] = {
+	 { "LPMLTemperatureScaler_11", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_10", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_9", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_13[] = {
+	 { "LPMLTemperatureScaler_15", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_14", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_13", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_14[] = {
+	 { "FuzzyFan_ErrorRateSetDelta", 0, 15, &umr_bitfield_default },
+	 { "FuzzyFan_ErrorSetDelta", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_15[] = {
+	 { "Reserved6", 0, 15, &umr_bitfield_default },
+	 { "FuzzyFan_PwmSetDelta", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_16[] = {
+	 { "GnbLPML_3", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_2", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_1", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_17[] = {
+	 { "GnbLPML_7", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_6", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_5", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_18[] = {
+	 { "GnbLPML_11", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_10", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_9", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_19[] = {
+	 { "GnbLPML_15", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_14", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_13", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_20[] = {
+	 { "Reserved1_1", 0, 7, &umr_bitfield_default },
+	 { "Reserved1_0", 8, 15, &umr_bitfield_default },
+	 { "GnbLPMLMinVid", 16, 23, &umr_bitfield_default },
+	 { "GnbLPMLMaxVid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_21[] = {
+	 { "BapmVddCBaseLeakageLoSidd", 0, 15, &umr_bitfield_default },
+	 { "BapmVddCBaseLeakageHiSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_16[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_17[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_18[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_19[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_20[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_21[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_22[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_24[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_25[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_26[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_27[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_28[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_29[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_30[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_31[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_32[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_33[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_34[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_35[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_36[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_37[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_38[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_39[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_40[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_41[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_42[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_43[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_44[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_46[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_47[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_48[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_49[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_50[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_51[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_52[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_53[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_54[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_55[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_56[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_57[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_58[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_59[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_60[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_61[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_62[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_63[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_64[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_65[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_66[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_67[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_68[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_69[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_70[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_71[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_72[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_73[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_74[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_75[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_76[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_77[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_78[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_79[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_80[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_81[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_82[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_83[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_84[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_85[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_86[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_87[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_88[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_89[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_90[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_91[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_92[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_93[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_94[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_95[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_96[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_97[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_98[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_99[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_100[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_101[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_102[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_103[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_104[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_105[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_106[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_107[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_108[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_109[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_110[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_111[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_112[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_113[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_114[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_115[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_116[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_117[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_118[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_119[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_120[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_121[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_122[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_123[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_124[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_125[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_126[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_127[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_RESET_CNTL[] = {
+	 { "rst_reg", 0, 0, &umr_bitfield_default },
+	 { "srbm_soft_rst_override", 1, 1, &umr_bitfield_default },
+	 { "RegReset", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_0[] = {
+	 { "ck_disable", 0, 0, &umr_bitfield_default },
+	 { "auto_cg_en", 1, 1, &umr_bitfield_default },
+	 { "auto_cg_timeout", 8, 23, &umr_bitfield_default },
+	 { "cken", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_1[] = {
+	 { "auto_ck_disable", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_2[] = {
+	 { "wake_on_irq", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_MSG_ARG_0[] = {
+	 { "smc_msg_arg", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_PC_C[] = {
+	 { "smc_pc_c", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SCRATCH9[] = {
+	 { "SCRATCH_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_ACCESS_CNTL[] = {
+	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_1", 1, 1, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_2", 2, 2, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_3", 3, 3, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_4", 4, 4, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_5", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_6", 6, 6, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_7", 7, 7, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_8", 8, 8, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_9", 9, 9, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_10", 10, 10, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_11", 11, 11, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_12", 12, 12, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_13", 13, 13, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_14", 14, 14, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_11[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_0[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_0[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_1[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_1[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_2[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_2[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_3[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_3[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_4[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_4[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_5[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_5[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_6[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_6[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_7[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_7[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_0[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_1[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_2[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_3[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_4[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_5[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_6[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_7[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_8[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_8[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_9[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_9[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_10[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_10[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_11[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_11[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_8[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_9[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_10[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_UC_EVENTS[] = {
+	 { "RCU_TST_jpc_rep_req", 0, 0, &umr_bitfield_default },
+	 { "TST_RCU_jpc_rep_done", 1, 1, &umr_bitfield_default },
+	 { "drv_rst_mode", 2, 2, &umr_bitfield_default },
+	 { "SMU_DC_efuse_status_invalid", 3, 3, &umr_bitfield_default },
+	 { "TP_Tester", 6, 6, &umr_bitfield_default },
+	 { "boot_seq_done", 7, 7, &umr_bitfield_default },
+	 { "sclk_deep_sleep_exit", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_ACTIVE", 9, 9, &umr_bitfield_default },
+	 { "BREAK_PT2_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "FCH_HALT", 11, 11, &umr_bitfield_default },
+	 { "RCU_GIO_fch_lockdown", 13, 13, &umr_bitfield_default },
+	 { "INTERRUPTS_ENABLED", 16, 16, &umr_bitfield_default },
+	 { "RCU_DtmCnt0_Done", 17, 17, &umr_bitfield_default },
+	 { "RCU_DtmCnt1_Done", 18, 18, &umr_bitfield_default },
+	 { "RCU_DtmCnt2_Done", 19, 19, &umr_bitfield_default },
+	 { "irq31_sel", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_MISC_CTRL[] = {
+	 { "REG_DRV_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "REG_RCU_MEMREP_DIS", 3, 3, &umr_bitfield_default },
+	 { "REG_CC_FUSE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "REG_SAMU_FUSE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "REG_CC_SRBM_RD_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_DONE", 16, 16, &umr_bitfield_default },
+	 { "BREAK_PT2_DONE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_START", 22, 22, &umr_bitfield_default },
+	 { "RST_PULSE_WIDTH", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_RCU_FUSES[] = {
+	 { "GPU_DIS", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "EFUSE_RD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "CG_RST_GLB_REQ_DIS", 5, 5, &umr_bitfield_default },
+	 { "DRV_RST_MODE", 6, 6, &umr_bitfield_default },
+	 { "ROM_DIS", 7, 7, &umr_bitfield_default },
+	 { "JPC_REP_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT1", 9, 9, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT2", 10, 10, &umr_bitfield_default },
+	 { "SMU_IOC_MST_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "FCH_LOCKOUT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "FCH_XFIRE_FILTER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XFIRE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_FUSE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "BIF_RST_POLLING_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "MEM_HARDREP_EN", 21, 21, &umr_bitfield_default },
+	 { "PCIE_INIT_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "DSMU_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "WRP_FUSE_VALID", 24, 24, &umr_bitfield_default },
+	 { "PHY_FUSE_VALID", 25, 25, &umr_bitfield_default },
+	 { "RCU_SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_MISC_FUSES[] = {
+	 { "IOMMU_V2_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "MinSClkDid", 2, 8, &umr_bitfield_default },
+	 { "MISC_SPARE", 9, 10, &umr_bitfield_default },
+	 { "PostResetGnbClkDid", 11, 17, &umr_bitfield_default },
+	 { "L2IMU_tn2_dtc_half", 18, 18, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_half", 19, 19, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_half", 20, 20, &umr_bitfield_default },
+	 { "L2IMU_tn2_pdc_half", 21, 21, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_dis", 22, 22, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_dis", 23, 23, &umr_bitfield_default },
+	 { "VCE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "IOC_IOMMU_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "GNB_SPARE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SCLK_VID_FUSES[] = {
+	 { "SClkVid0", 0, 7, &umr_bitfield_default },
+	 { "SClkVid1", 8, 15, &umr_bitfield_default },
+	 { "SClkVid2", 16, 23, &umr_bitfield_default },
+	 { "SClkVid3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOCCFG_FUSES[] = {
+	 { "NB_REV_ID", 1, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOC_FUSES[] = {
+	 { "IOC_FUSES", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_TST_EFUSE1_MISC[] = {
+	 { "RF_RM_6_2", 1, 5, &umr_bitfield_default },
+	 { "RME", 6, 6, &umr_bitfield_default },
+	 { "MBIST_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "HARD_REPAIR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SOFT_REPAIR_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "GPU_DIS", 10, 10, &umr_bitfield_default },
+	 { "SMS_PWRDWN_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "CRBBMP1500_DISA", 12, 12, &umr_bitfield_default },
+	 { "CRBBMP1500_DISB", 13, 13, &umr_bitfield_default },
+	 { "RM_RF8", 14, 14, &umr_bitfield_default },
+	 { "DFT_SPARE1", 22, 22, &umr_bitfield_default },
+	 { "DFT_SPARE2", 23, 23, &umr_bitfield_default },
+	 { "DFT_SPARE3", 24, 24, &umr_bitfield_default },
+	 { "VCE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "DCE_SCAN_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_TST_ID_STRAPS[] = {
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+	 { "ATI_REV_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_FCTRL_FUSES[] = {
+	 { "EXT_EFUSE_MACRO_PRESENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_HARVEST_FUSES[] = {
+	 { "VCE_DISABLE", 1, 2, &umr_bitfield_default },
+	 { "UVD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "ACP_EXISTS", 6, 6, &umr_bitfield_default },
+	 { "DC_DISABLE", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_EFUSE_0[] = {
+	 { "EFUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGENERAL_PWRMGT[] = {
+	 { "GLOBAL_PWRMGT_EN", 0, 0, &umr_bitfield_default },
+	 { "STATIC_PM_EN", 1, 1, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_DIS", 2, 2, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_TYPE", 3, 3, &umr_bitfield_default },
+	 { "SW_SMIO_INDEX", 6, 6, &umr_bitfield_default },
+	 { "LOW_VOLT_D2_ACPI", 8, 8, &umr_bitfield_default },
+	 { "LOW_VOLT_D3_ACPI", 9, 9, &umr_bitfield_default },
+	 { "VOLT_PWRMGT_EN", 10, 10, &umr_bitfield_default },
+	 { "SPARE11", 11, 11, &umr_bitfield_default },
+	 { "GPU_COUNTER_ACPI", 14, 14, &umr_bitfield_default },
+	 { "GPU_COUNTER_CLK", 15, 15, &umr_bitfield_default },
+	 { "GPU_COUNTER_OFF", 16, 16, &umr_bitfield_default },
+	 { "GPU_COUNTER_INTF_OFF", 17, 17, &umr_bitfield_default },
+	 { "SPARE18", 18, 18, &umr_bitfield_default },
+	 { "ACPI_D3_VID", 19, 20, &umr_bitfield_default },
+	 { "DYN_SPREAD_SPECTRUM_EN", 23, 23, &umr_bitfield_default },
+	 { "SPARE27", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCNB_PWRMGT_CNTL[] = {
+	 { "GNB_SLOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "GNB_SLOW", 2, 2, &umr_bitfield_default },
+	 { "FORCE_NB_PS1", 3, 3, &umr_bitfield_default },
+	 { "DPM_ENABLED", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_PWRMGT_CNTL[] = {
+	 { "SCLK_PWRMGT_OFF", 0, 0, &umr_bitfield_default },
+	 { "RESET_BUSY_CNT", 4, 4, &umr_bitfield_default },
+	 { "RESET_SCLK_CNT", 5, 5, &umr_bitfield_default },
+	 { "DYN_LIGHT_SLEEP_EN", 14, 14, &umr_bitfield_default },
+	 { "AUTO_SCLK_PULSE_SKIP", 15, 15, &umr_bitfield_default },
+	 { "LIGHT_SLEEP_COUNTER", 16, 20, &umr_bitfield_default },
+	 { "DYNAMIC_PM_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX[] = {
+	 { "TARGET_STATE", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_STATE", 4, 7, &umr_bitfield_default },
+	 { "CURR_MCLK_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MCLK_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_SCLK_INDEX", 16, 20, &umr_bitfield_default },
+	 { "TARG_SCLK_INDEX", 21, 25, &umr_bitfield_default },
+	 { "CURR_LCLK_INDEX", 26, 28, &umr_bitfield_default },
+	 { "TARG_LCLK_INDEX", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_PCC_CONTROL[] = {
+	 { "PCC_POLARITY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_PCC_GPIO_SELECT[] = {
+	 { "GPIO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 3, &umr_bitfield_default },
+	 { "TST_REF_SEL", 4, 7, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 8, 14, &umr_bitfield_default },
+	 { "TST_RESET", 15, 15, &umr_bitfield_default },
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_STATIC_SCREEN_PARAMETER[] = {
+	 { "STATIC_SCREEN_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL[] = {
+	 { "DISP_GAP", 0, 1, &umr_bitfield_default },
+	 { "VBI_TIMER_COUNT", 4, 17, &umr_bitfield_default },
+	 { "VBI_TIMER_UNIT", 20, 22, &umr_bitfield_default },
+	 { "DISP_GAP_MCHG", 24, 25, &umr_bitfield_default },
+	 { "VBI_TIMER_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACPI_CNTL[] = {
+	 { "SCLK_ACPI_DIV", 0, 6, &umr_bitfield_default },
+	 { "SCLK_CHANGE_SKIP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_14_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_15_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 16, 16, &umr_bitfield_default },
+	 { "SELF_REFRESH_MASK", 17, 17, &umr_bitfield_default },
+	 { "ALLOW_NBPSTATE_MASK", 18, 18, &umr_bitfield_default },
+	 { "BIF_BUSY_MASK", 19, 19, &umr_bitfield_default },
+	 { "UVD_BUSY_MASK", 20, 20, &umr_bitfield_default },
+	 { "MC0SRBM_BUSY_MASK", 21, 21, &umr_bitfield_default },
+	 { "MC1SRBM_BUSY_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_ALLOW_MASK", 23, 23, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 24, 24, &umr_bitfield_default },
+	 { "SELF_REFRESH_NLC_MASK", 25, 25, &umr_bitfield_default },
+	 { "FAST_EXIT_REQ_NBPSTATE", 26, 26, &umr_bitfield_default },
+	 { "DEEP_SLEEP_ENTRY_MODE", 27, 27, &umr_bitfield_default },
+	 { "MBUS2_ACTIVE_MASK", 28, 28, &umr_bitfield_default },
+	 { "VCE_BUSY_MASK", 29, 29, &umr_bitfield_default },
+	 { "AZ_BUSY_MASK", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RLC_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "HDP_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "ROM_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "PDMA_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "IDCT_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "SDMA_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_AZ_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK", 9, 9, &umr_bitfield_default },
+	 { "UVD_CG_MC_STAT_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "VCE_CG_MC_STAT_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "SAM_CG_MC_STAT_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "SAM_CG_STATUS_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 14, 14, &umr_bitfield_default },
+	 { "SHALLOW_DIV_ID", 21, 23, &umr_bitfield_default },
+	 { "INOUT_CUSHION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_MISC_CNTL[] = {
+	 { "DPM_DS_DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "DPM_SS_DIV_ID", 3, 5, &umr_bitfield_default },
+	 { "OCP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OCP_DS_DIV_ID", 17, 19, &umr_bitfield_default },
+	 { "OCP_SS_DIV_ID", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL3[] = {
+	 { "GRBM_0_SMU_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRBM_1_SMU_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "GRBM_2_SMU_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "GRBM_3_SMU_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "GRBM_4_SMU_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "GRBM_5_SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "GRBM_6_SMU_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "GRBM_7_SMU_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "GRBM_8_SMU_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "GRBM_9_SMU_BUSY_MASK", 9, 9, &umr_bitfield_default },
+	 { "GRBM_10_SMU_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "GRBM_11_SMU_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "GRBM_12_SMU_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "GRBM_13_SMU_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "GRBM_14_SMU_BUSY_MASK", 14, 14, &umr_bitfield_default },
+	 { "GRBM_15_SMU_BUSY_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_1[] = {
+	 { "CURR_VDDCI_INDEX", 0, 3, &umr_bitfield_default },
+	 { "TARG_VDDCI_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_MVDD_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MVDD_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_VDDC_INDEX", 16, 19, &umr_bitfield_default },
+	 { "TARG_VDDC_INDEX", 20, 23, &umr_bitfield_default },
+	 { "CURR_PCIE_INDEX", 24, 27, &umr_bitfield_default },
+	 { "TARG_PCIE_INDEX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ULV_PARAMETER[] = {
+	 { "ULV_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "ULV_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_0[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_1[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_2[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_3[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_4[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_5[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_6[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
+	 { "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "L1IMU_SMU_IDLE_MASK", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_BIT3", 3, 3, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 4, 4, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE1_MASK", 6, 6, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE2_MASK", 7, 7, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE3_MASK", 8, 8, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE4_MASK", 9, 9, &umr_bitfield_default },
+	 { "L1IMUGPP_IDLE_MASK", 10, 10, &umr_bitfield_default },
+	 { "L1IMUGPPSB_IDLE_MASK", 11, 11, &umr_bitfield_default },
+	 { "L1IMUBIF_IDLE_MASK", 12, 12, &umr_bitfield_default },
+	 { "L1IMUINTGEN_IDLE_MASK", 13, 13, &umr_bitfield_default },
+	 { "L2IMU_IDLE_MASK", 14, 14, &umr_bitfield_default },
+	 { "ORB_IDLE_MASK", 15, 15, &umr_bitfield_default },
+	 { "ON_INB_WAKE_MASK", 16, 16, &umr_bitfield_default },
+	 { "ON_INB_WAKE_ACK_MASK", 17, 17, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_MASK", 18, 18, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_ACK_MASK", 19, 19, &umr_bitfield_default },
+	 { "DMAACTIVE_MASK", 20, 20, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_PARAMETER[] = {
+	 { "VDDGFX_IDLE_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "VDDGFX_IDLE_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_CONTROL[] = {
+	 { "VDDGFX_IDLE_EN", 0, 0, &umr_bitfield_default },
+	 { "VDDGFX_IDLE_DETECT", 1, 1, &umr_bitfield_default },
+	 { "FORCE_VDDGFX_IDLE_EXIT", 2, 2, &umr_bitfield_default },
+	 { "SMC_VDDGFX_IDLE_STATE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_EXIT[] = {
+	 { "BIF_EXIT_REQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_CONTROL2[] = {
+	 { "DISP_TIMER_PULSE_WIDTH", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_1_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_0_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_MIN_DIV[] = {
+	 { "FRACV", 0, 11, &umr_bitfield_default },
+	 { "INTV", 12, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_2_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_3_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_4_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_5_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_6_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_7_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_8_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_9_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_10_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_11_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_12_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_13_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_RUNNING", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_CTRL[] = {
+	 { "DPM_EVENT_SRC", 0, 2, &umr_bitfield_default },
+	 { "THERM_INC_CLK", 3, 3, &umr_bitfield_default },
+	 { "SPARE", 4, 13, &umr_bitfield_default },
+	 { "DIG_THERM_DPM", 14, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 24, &umr_bitfield_default },
+	 { "CTF_PAD_POLARITY", 25, 25, &umr_bitfield_default },
+	 { "CTF_PAD_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_STATUS[] = {
+	 { "SPARE", 0, 8, &umr_bitfield_default },
+	 { "FDO_PWM_DUTY", 9, 16, &umr_bitfield_default },
+	 { "THERM_ALERT", 17, 17, &umr_bitfield_default },
+	 { "GEN_STATUS", 18, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT[] = {
+	 { "DIG_THERM_CTF", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTH", 8, 15, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 16, 23, &umr_bitfield_default },
+	 { "THERM_INT_MASK", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_CTRL[] = {
+	 { "TS_FILTER", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 7, &umr_bitfield_default },
+	 { "THERMAL_RANGE_RST", 9, 9, &umr_bitfield_default },
+	 { "TEMP_SEL", 20, 27, &umr_bitfield_default },
+	 { "THM_READY_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_STATUS[] = {
+	 { "ASIC_MAX_TEMP", 0, 8, &umr_bitfield_default },
+	 { "CTF_TEMP", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL0[] = {
+	 { "FDO_STATIC_DUTY", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_DUTY", 8, 15, &umr_bitfield_default },
+	 { "FDO_PWM_MANUAL", 16, 16, &umr_bitfield_default },
+	 { "FDO_PWM_HYSTER", 17, 22, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP_EN", 23, 23, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL1[] = {
+	 { "FMAX_DUTY100", 0, 7, &umr_bitfield_default },
+	 { "FMIN_DUTY", 8, 15, &umr_bitfield_default },
+	 { "M", 16, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 29, &umr_bitfield_default },
+	 { "FDO_PWRDNB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL2[] = {
+	 { "TMIN", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_TIME", 8, 10, &umr_bitfield_default },
+	 { "FDO_PWM_MODE", 11, 13, &umr_bitfield_default },
+	 { "TMIN_HYSTER", 14, 16, &umr_bitfield_default },
+	 { "TMAX", 17, 24, &umr_bitfield_default },
+	 { "TACH_PWM_RESP_RATE", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_CTRL[] = {
+	 { "EDGE_PER_REV", 0, 2, &umr_bitfield_default },
+	 { "TARGET_PERIOD", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_STATUS[] = {
+	 { "TACH_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_THM_STRAPS0[] = {
+	 { "TMON0_BGADJ", 1, 8, &umr_bitfield_default },
+	 { "TMON1_BGADJ", 9, 16, &umr_bitfield_default },
+	 { "TMON_CMON_FUSE_SEL", 17, 17, &umr_bitfield_default },
+	 { "NUM_ACQ", 18, 20, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 21, 23, &umr_bitfield_default },
+	 { "TMON_CONFIG_SOURCE", 24, 24, &umr_bitfield_default },
+	 { "CTF_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "TMON0_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "TMON1_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "TMON2_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "TMON3_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "UNUSED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_STATUS[] = {
+	 { "CURRENT_RDI", 0, 4, &umr_bitfield_default },
+	 { "MEAS_DONE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
+	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
+	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
+	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
+	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC1_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC1_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
+	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
+	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
+	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC2_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC2_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
+	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
+	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
+	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC3_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC3_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
+	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
+	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_CNTL[] = {
+	 { "CPL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CPL_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "CPL_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "CPL_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_SEL[] = {
+	 { "CPL_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_VAL[] = {
+	 { "CPL_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_CNTL[] = {
+	 { "DCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_STATUS[] = {
+	 { "DCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_CNTL[] = {
+	 { "VCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_STATUS[] = {
+	 { "VCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_CNTL[] = {
+	 { "ECLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_STATUS[] = {
+	 { "ECLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACLK_CNTL[] = {
+	 { "ACLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_DFS_BYPASS_CNTL[] = {
+	 { "BYPASSECLK", 0, 0, &umr_bitfield_default },
+	 { "BYPASSLCLK", 1, 1, &umr_bitfield_default },
+	 { "BYPASSEVCLK", 2, 2, &umr_bitfield_default },
+	 { "BYPASSDCLK", 3, 3, &umr_bitfield_default },
+	 { "BYPASSVCLK", 4, 4, &umr_bitfield_default },
+	 { "BYPASSDISPCLK", 5, 5, &umr_bitfield_default },
+	 { "BYPASSDPREFCLK", 6, 6, &umr_bitfield_default },
+	 { "BYPASSACLK", 7, 7, &umr_bitfield_default },
+	 { "BYPASSADIVCLK", 8, 8, &umr_bitfield_default },
+	 { "BYPASSPSPCLK", 9, 9, &umr_bitfield_default },
+	 { "BYPASSSAMCLK", 10, 10, &umr_bitfield_default },
+	 { "BYPASSSCLK", 11, 11, &umr_bitfield_default },
+	 { "USE_SPLL_BYPASS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL[] = {
+	 { "SPLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "SPLL_PWRON", 1, 1, &umr_bitfield_default },
+	 { "SPLL_DIVEN", 2, 2, &umr_bitfield_default },
+	 { "SPLL_BYPASS_EN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_BYPASS_THRU_DFS", 4, 4, &umr_bitfield_default },
+	 { "SPLL_REF_DIV", 5, 10, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_EN", 12, 12, &umr_bitfield_default },
+	 { "SPLL_PDIV_A", 20, 26, &umr_bitfield_default },
+	 { "SPLL_DIVA_ACK", 27, 27, &umr_bitfield_default },
+	 { "SPLL_OTEST_LOCK_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_2[] = {
+	 { "SCLK_MUX_SEL", 0, 8, &umr_bitfield_default },
+	 { "SPLL_CTLREQ", 11, 11, &umr_bitfield_default },
+	 { "SPLL_BYPASS_CHG", 22, 22, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_CHG", 23, 23, &umr_bitfield_default },
+	 { "SPLL_RESET_CHG", 24, 24, &umr_bitfield_default },
+	 { "SPLL_BABY_STEP_CHG", 25, 25, &umr_bitfield_default },
+	 { "SCLK_MUX_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "SPLL_UNLOCK_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "SPLL_CLKF_UPDATE", 28, 28, &umr_bitfield_default },
+	 { "SPLL_TEST_UNLOCK_CLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_3[] = {
+	 { "SPLL_FB_DIV", 0, 25, &umr_bitfield_default },
+	 { "SPLL_DITHEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_4[] = {
+	 { "SPLL_SCLK_TEST_SEL", 0, 3, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT_SEL", 5, 6, &umr_bitfield_default },
+	 { "SPLL_SCLK_EN", 7, 8, &umr_bitfield_default },
+	 { "SPLL_SPARE", 9, 18, &umr_bitfield_default },
+	 { "TEST_FRAC_BYPASS", 21, 21, &umr_bitfield_default },
+	 { "SPLL_ILOCK", 23, 23, &umr_bitfield_default },
+	 { "SPLL_FBCLK_SEL", 24, 24, &umr_bitfield_default },
+	 { "SPLL_VCTRLADC_EN", 25, 25, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT", 26, 27, &umr_bitfield_default },
+	 { "SPLL_SPARE_EXT", 28, 30, &umr_bitfield_default },
+	 { "SPLL_VTOI_BIAS_CNTL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_5[] = {
+	 { "FBDIV_SSC_BYPASS", 0, 0, &umr_bitfield_default },
+	 { "RISEFBVCO_EN", 1, 1, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 2, 3, &umr_bitfield_default },
+	 { "RESET_TIMER", 4, 5, &umr_bitfield_default },
+	 { "FAST_LOCK_CNTRL", 6, 7, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 8, 8, &umr_bitfield_default },
+	 { "RESET_ANTI_MUX", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_6[] = {
+	 { "SCLKMUX0_CLKOFF_CNT", 0, 7, &umr_bitfield_default },
+	 { "SCLKMUX1_CLKOFF_CNT", 8, 15, &umr_bitfield_default },
+	 { "SPLL_VCTL_EN", 16, 16, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_IN", 17, 20, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_OUT", 21, 24, &umr_bitfield_default },
+	 { "SPLL_LF_CNTR", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_7[] = {
+	 { "SPLL_BW_CNTRL", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPLL_CNTL_MODE[] = {
+	 { "SPLL_SW_DIR_CONTROL", 0, 0, &umr_bitfield_default },
+	 { "SPLL_LEGACY_PDIV", 1, 1, &umr_bitfield_default },
+	 { "SPLL_TEST", 2, 2, &umr_bitfield_default },
+	 { "SPLL_FASTEN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_ENSAT", 4, 4, &umr_bitfield_default },
+	 { "SPLL_TEST_CLK_EXT_DIV", 10, 11, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_DLY_CNT", 12, 19, &umr_bitfield_default },
+	 { "SPLL_RESET_EN", 28, 28, &umr_bitfield_default },
+	 { "SPLL_VCO_MODE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM[] = {
+	 { "SSEN", 0, 0, &umr_bitfield_default },
+	 { "CLKS", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM_2[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMPLL_BYPASSCLK_SEL[] = {
+	 { "MPLL_CLKOUT_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL[] = {
+	 { "XTALIN_DIVIDE", 1, 1, &umr_bitfield_default },
+	 { "BCLK_AS_XCLK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_2[] = {
+	 { "ENABLE_XCLK", 0, 0, &umr_bitfield_default },
+	 { "FORCE_BIF_REFCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "MUX_TCLK_TO_XCLK", 8, 8, &umr_bitfield_default },
+	 { "XO_IN_OSCIN_EN", 14, 14, &umr_bitfield_default },
+	 { "XO_IN_ICORE_CLK_OE", 15, 15, &umr_bitfield_default },
+	 { "XO_IN_CML_RXEN", 16, 16, &umr_bitfield_default },
+	 { "XO_IN_BIDIR_CML_OE", 17, 17, &umr_bitfield_default },
+	 { "XO_IN2_OSCIN_EN", 18, 18, &umr_bitfield_default },
+	 { "XO_IN2_ICORE_CLK_OE", 19, 19, &umr_bitfield_default },
+	 { "XO_IN2_CML_RXEN", 20, 20, &umr_bitfield_default },
+	 { "XO_IN2_BIDIR_CML_OE", 21, 21, &umr_bitfield_default },
+	 { "CML_CTRL", 22, 23, &umr_bitfield_default },
+	 { "CLK_SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_CLK_CNTL[] = {
+	 { "CMON_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "CTF_CLK_SHUTOFF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_CLK_CTRL[] = {
+	 { "DEEP_SLEEP_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "ZCLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "DFT_SMS_PG_CLK_SEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 4, &umr_bitfield_default },
+	 { "TST_REF_SEL", 5, 9, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 10, 16, &umr_bitfield_default },
+	 { "TST_RESET", 17, 17, &umr_bitfield_default },
+	 { "TST_CLK_SEL_MODE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL_2[] = {
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_ADFS_CLK_BYPASS_CNTL1[] = {
+	 { "ECLK_BYPASS_CNTL", 0, 2, &umr_bitfield_default },
+	 { "SCLK_BYPASS_CNTL", 3, 5, &umr_bitfield_default },
+	 { "LCLK_BYPASS_CNTL", 6, 8, &umr_bitfield_default },
+	 { "DCLK_BYPASS_CNTL", 9, 11, &umr_bitfield_default },
+	 { "VCLK_BYPASS_CNTL", 12, 14, &umr_bitfield_default },
+	 { "DISPCLK_BYPASS_CNTL", 15, 17, &umr_bitfield_default },
+	 { "DRREFCLK_BYPASS_CNTL", 18, 20, &umr_bitfield_default },
+	 { "ACLK_BYPASS_CNTL", 21, 23, &umr_bitfield_default },
+	 { "SAMCLK_BYPASS_CNTL", 24, 26, &umr_bitfield_default },
+	 { "ACLK_DIV_BYPASS_CNTL", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_DC[] = {
+	 { "OSC_EN", 0, 0, &umr_bitfield_default },
+	 { "XTL_LOW_GAIN", 1, 2, &umr_bitfield_default },
+	 { "XTL_XOCLK_DRV_R_EN", 9, 9, &umr_bitfield_default },
+	 { "XTALIN_SEL", 10, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_CNTL[] = {
+	 { "SCK_OVERWRITE", 1, 1, &umr_bitfield_default },
+	 { "CLOCK_GATING_EN", 2, 2, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_SETUP_TIME", 8, 15, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_HOLD_TIME", 16, 23, &umr_bitfield_default },
+	 { "SCK_PRESCALE_REFCLK", 24, 27, &umr_bitfield_default },
+	 { "SCK_PRESCALE_CRYSTAL_CLK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPAGE_MIRROR_CNTL[] = {
+	 { "PAGE_MIRROR_BASE_ADDR", 0, 23, &umr_bitfield_default },
+	 { "PAGE_MIRROR_INVALIDATE", 24, 24, &umr_bitfield_default },
+	 { "PAGE_MIRROR_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "PAGE_MIRROR_USAGE", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_STATUS[] = {
+	 { "ROM_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCGTT_ROM_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_INDEX[] = {
+	 { "ROM_INDEX", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_DATA[] = {
+	 { "ROM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_START[] = {
+	 { "ROM_START", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_CNTL[] = {
+	 { "DATA_SIZE", 0, 15, &umr_bitfield_default },
+	 { "COMMAND_SIZE", 16, 17, &umr_bitfield_default },
+	 { "ROM_SW_RETURN_DATA_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_STATUS[] = {
+	 { "ROM_SW_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_COMMAND[] = {
+	 { "ROM_SW_INSTRUCTION", 0, 7, &umr_bitfield_default },
+	 { "ROM_SW_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_1[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_2[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_3[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_4[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_5[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_6[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_7[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_8[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_9[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_10[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_11[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_12[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_13[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_14[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_15[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_16[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_17[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_18[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_19[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_20[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_21[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_22[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_23[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_24[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_25[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_26[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_27[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_28[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_29[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_30[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_31[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_32[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_33[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_34[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_35[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_36[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_37[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_38[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_39[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_40[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_41[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_42[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_43[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_44[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_45[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_46[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_47[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_48[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_49[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_50[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_51[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_52[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_53[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_54[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_55[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_56[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_57[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_58[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_59[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_60[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_61[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_62[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_63[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_64[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_ENA[] = {
+	 { "THERM_INTH_SET", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_SET", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_SET", 2, 2, &umr_bitfield_default },
+	 { "THERM_INTH_CLR", 3, 3, &umr_bitfield_default },
+	 { "THERM_INTL_CLR", 4, 4, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CLR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_CTRL[] = {
+	 { "DIG_THERM_INTH", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 8, 15, &umr_bitfield_default },
+	 { "GNB_TEMP_THRESHOLD", 16, 23, &umr_bitfield_default },
+	 { "THERM_INTH_MASK", 24, 24, &umr_bitfield_default },
+	 { "THERM_INTL_MASK", 25, 25, &umr_bitfield_default },
+	 { "THERM_TRIGGER_MASK", 26, 26, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_MASK", 27, 27, &umr_bitfield_default },
+	 { "THERM_GNB_HW_ENA", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_STATUS[] = {
+	 { "THERM_INTH_DETECT", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_DETECT", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_DETECT", 2, 2, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_DETECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MAIN_PLL_OP_FREQ[] = {
+	 { "PLL_OP_FREQ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_STATUS[] = {
+	 { "SMU_DONE", 0, 0, &umr_bitfield_default },
+	 { "SMU_PASS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_FIRMWARE[] = {
+	 { "SMU_IN_PROG", 0, 0, &umr_bitfield_default },
+	 { "SMU_RD_DONE", 1, 2, &umr_bitfield_default },
+	 { "SMU_SRAM_RD_BLOCK_EN", 3, 3, &umr_bitfield_default },
+	 { "SMU_SRAM_WR_BLOCK_EN", 4, 4, &umr_bitfield_default },
+	 { "SMU_counter", 8, 11, &umr_bitfield_default },
+	 { "SMU_MODE", 16, 16, &umr_bitfield_default },
+	 { "SMU_SEL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_INPUT_DATA[] = {
+	 { "START_ADDR", 0, 30, &umr_bitfield_default },
+	 { "AUTO_START", 31, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/smu711_regs.i b/src/lib/ip/smu711_regs.i
new file mode 100644
index 0000000..6e66ecd
--- /dev/null
+++ b/src/lib/ip/smu711_regs.i
@@ -0,0 +1,1077 @@
+	{ "mmGPIOPAD_SW_INT_STAT", REG_MMIO, 0x180, &mmGPIOPAD_SW_INT_STAT[0], sizeof(mmGPIOPAD_SW_INT_STAT)/sizeof(mmGPIOPAD_SW_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_STRENGTH", REG_MMIO, 0x181, &mmGPIOPAD_STRENGTH[0], sizeof(mmGPIOPAD_STRENGTH)/sizeof(mmGPIOPAD_STRENGTH[0]), 0, 0 },
+	{ "mmGPIOPAD_MASK", REG_MMIO, 0x182, &mmGPIOPAD_MASK[0], sizeof(mmGPIOPAD_MASK)/sizeof(mmGPIOPAD_MASK[0]), 0, 0 },
+	{ "mmGPIOPAD_A", REG_MMIO, 0x183, &mmGPIOPAD_A[0], sizeof(mmGPIOPAD_A)/sizeof(mmGPIOPAD_A[0]), 0, 0 },
+	{ "mmGPIOPAD_EN", REG_MMIO, 0x184, &mmGPIOPAD_EN[0], sizeof(mmGPIOPAD_EN)/sizeof(mmGPIOPAD_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_Y", REG_MMIO, 0x185, &mmGPIOPAD_Y[0], sizeof(mmGPIOPAD_Y)/sizeof(mmGPIOPAD_Y[0]), 0, 0 },
+	{ "mmGPIOPAD_PINSTRAPS", REG_MMIO, 0x186, &mmGPIOPAD_PINSTRAPS[0], sizeof(mmGPIOPAD_PINSTRAPS)/sizeof(mmGPIOPAD_PINSTRAPS[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_EN", REG_MMIO, 0x187, &mmGPIOPAD_INT_STAT_EN[0], sizeof(mmGPIOPAD_INT_STAT_EN)/sizeof(mmGPIOPAD_INT_STAT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT", REG_MMIO, 0x188, &mmGPIOPAD_INT_STAT[0], sizeof(mmGPIOPAD_INT_STAT)/sizeof(mmGPIOPAD_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_AK", REG_MMIO, 0x189, &mmGPIOPAD_INT_STAT_AK[0], sizeof(mmGPIOPAD_INT_STAT_AK)/sizeof(mmGPIOPAD_INT_STAT_AK[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_EN", REG_MMIO, 0x18a, &mmGPIOPAD_INT_EN[0], sizeof(mmGPIOPAD_INT_EN)/sizeof(mmGPIOPAD_INT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_TYPE", REG_MMIO, 0x18b, &mmGPIOPAD_INT_TYPE[0], sizeof(mmGPIOPAD_INT_TYPE)/sizeof(mmGPIOPAD_INT_TYPE[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_POLARITY", REG_MMIO, 0x18c, &mmGPIOPAD_INT_POLARITY[0], sizeof(mmGPIOPAD_INT_POLARITY)/sizeof(mmGPIOPAD_INT_POLARITY[0]), 0, 0 },
+	{ "mmGPIOPAD_EXTERN_TRIG_CNTL", REG_MMIO, 0x18d, &mmGPIOPAD_EXTERN_TRIG_CNTL[0], sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL)/sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL[0]), 0, 0 },
+	{ "mmGPIOPAD_RCVR_SEL", REG_MMIO, 0x191, &mmGPIOPAD_RCVR_SEL[0], sizeof(mmGPIOPAD_RCVR_SEL)/sizeof(mmGPIOPAD_RCVR_SEL[0]), 0, 0 },
+	{ "mmGPIOPAD_PU_EN", REG_MMIO, 0x192, &mmGPIOPAD_PU_EN[0], sizeof(mmGPIOPAD_PU_EN)/sizeof(mmGPIOPAD_PU_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_PD_EN", REG_MMIO, 0x193, &mmGPIOPAD_PD_EN[0], sizeof(mmGPIOPAD_PD_EN)/sizeof(mmGPIOPAD_PD_EN[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_0", REG_MMIO, 0x1a6, &mmSMU_IND_INDEX_0[0], sizeof(mmSMU_IND_INDEX_0)/sizeof(mmSMU_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_0", REG_MMIO, 0x1a7, &mmSMU_IND_DATA_0[0], sizeof(mmSMU_IND_DATA_0)/sizeof(mmSMU_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_1", REG_MMIO, 0x1a8, &mmSMU_IND_INDEX_1[0], sizeof(mmSMU_IND_INDEX_1)/sizeof(mmSMU_IND_INDEX_1[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_1", REG_MMIO, 0x1a9, &mmSMU_IND_DATA_1[0], sizeof(mmSMU_IND_DATA_1)/sizeof(mmSMU_IND_DATA_1[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_2", REG_MMIO, 0x1aa, &mmSMU_IND_INDEX_2[0], sizeof(mmSMU_IND_INDEX_2)/sizeof(mmSMU_IND_INDEX_2[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_2", REG_MMIO, 0x1ab, &mmSMU_IND_DATA_2[0], sizeof(mmSMU_IND_DATA_2)/sizeof(mmSMU_IND_DATA_2[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_11", REG_MMIO, 0x1AC, NULL, 0, 0, 0 },
+	{ "mmSMU_IND_INDEX_3", REG_MMIO, 0x1ac, &mmSMU_IND_INDEX_3[0], sizeof(mmSMU_IND_INDEX_3)/sizeof(mmSMU_IND_INDEX_3[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_11", REG_MMIO, 0x1AD, NULL, 0, 0, 0 },
+	{ "mmSMU_IND_DATA_3", REG_MMIO, 0x1ad, &mmSMU_IND_DATA_3[0], sizeof(mmSMU_IND_DATA_3)/sizeof(mmSMU_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_4", REG_MMIO, 0x1ae, &mmSMU_IND_INDEX_4[0], sizeof(mmSMU_IND_INDEX_4)/sizeof(mmSMU_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_4", REG_MMIO, 0x1af, &mmSMU_IND_DATA_4[0], sizeof(mmSMU_IND_DATA_4)/sizeof(mmSMU_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_5", REG_MMIO, 0x1b0, &mmSMU_IND_INDEX_5[0], sizeof(mmSMU_IND_INDEX_5)/sizeof(mmSMU_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_5", REG_MMIO, 0x1b1, &mmSMU_IND_DATA_5[0], sizeof(mmSMU_IND_DATA_5)/sizeof(mmSMU_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_6", REG_MMIO, 0x1b2, &mmSMU_IND_INDEX_6[0], sizeof(mmSMU_IND_INDEX_6)/sizeof(mmSMU_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_6", REG_MMIO, 0x1b3, &mmSMU_IND_DATA_6[0], sizeof(mmSMU_IND_DATA_6)/sizeof(mmSMU_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_7", REG_MMIO, 0x1b4, &mmSMU_IND_INDEX_7[0], sizeof(mmSMU_IND_INDEX_7)/sizeof(mmSMU_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_7", REG_MMIO, 0x1b5, &mmSMU_IND_DATA_7[0], sizeof(mmSMU_IND_DATA_7)/sizeof(mmSMU_IND_DATA_7[0]), 0, 0 },
+	{ "mmCG_FPS_CNT", REG_MMIO, 0x1b6, &mmCG_FPS_CNT[0], sizeof(mmCG_FPS_CNT)/sizeof(mmCG_FPS_CNT[0]), 0, 0 },
+	{ "ixFIRMWARE_FLAGS", REG_SMC, 0x33000, &ixFIRMWARE_FLAGS[0], sizeof(ixFIRMWARE_FLAGS)/sizeof(ixFIRMWARE_FLAGS[0]), 0, 0 },
+	{ "ixTDC_STATUS", REG_SMC, 0x33004, &ixTDC_STATUS[0], sizeof(ixTDC_STATUS)/sizeof(ixTDC_STATUS[0]), 0, 0 },
+	{ "ixTDC_MV_AVERAGE", REG_SMC, 0x33008, &ixTDC_MV_AVERAGE[0], sizeof(ixTDC_MV_AVERAGE)/sizeof(ixTDC_MV_AVERAGE[0]), 0, 0 },
+	{ "ixTDC_VRM_LIMIT", REG_SMC, 0x3300c, &ixTDC_VRM_LIMIT[0], sizeof(ixTDC_VRM_LIMIT)/sizeof(ixTDC_VRM_LIMIT[0]), 0, 0 },
+	{ "ixFEATURE_STATUS", REG_SMC, 0x33010, &ixFEATURE_STATUS[0], sizeof(ixFEATURE_STATUS)/sizeof(ixFEATURE_STATUS[0]), 0, 0 },
+	{ "ixENTITY_TEMPERATURES_1", REG_SMC, 0x33014, &ixENTITY_TEMPERATURES_1[0], sizeof(ixENTITY_TEMPERATURES_1)/sizeof(ixENTITY_TEMPERATURES_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_1", REG_SMC, 0x33018, &ixMCARB_DRAM_TIMING_TABLE_1[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_1)/sizeof(ixMCARB_DRAM_TIMING_TABLE_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_2", REG_SMC, 0x3301c, &ixMCARB_DRAM_TIMING_TABLE_2[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_2)/sizeof(ixMCARB_DRAM_TIMING_TABLE_2[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_3", REG_SMC, 0x33020, &ixMCARB_DRAM_TIMING_TABLE_3[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_3)/sizeof(ixMCARB_DRAM_TIMING_TABLE_3[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_4", REG_SMC, 0x33024, &ixMCARB_DRAM_TIMING_TABLE_4[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_4)/sizeof(ixMCARB_DRAM_TIMING_TABLE_4[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_5", REG_SMC, 0x33028, &ixMCARB_DRAM_TIMING_TABLE_5[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_5)/sizeof(ixMCARB_DRAM_TIMING_TABLE_5[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_6", REG_SMC, 0x3302c, &ixMCARB_DRAM_TIMING_TABLE_6[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_6)/sizeof(ixMCARB_DRAM_TIMING_TABLE_6[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_7", REG_SMC, 0x33030, &ixMCARB_DRAM_TIMING_TABLE_7[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_7)/sizeof(ixMCARB_DRAM_TIMING_TABLE_7[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_8", REG_SMC, 0x33034, &ixMCARB_DRAM_TIMING_TABLE_8[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_8)/sizeof(ixMCARB_DRAM_TIMING_TABLE_8[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_9", REG_SMC, 0x33038, &ixMCARB_DRAM_TIMING_TABLE_9[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_9)/sizeof(ixMCARB_DRAM_TIMING_TABLE_9[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_10", REG_SMC, 0x3303c, &ixMCARB_DRAM_TIMING_TABLE_10[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_10)/sizeof(ixMCARB_DRAM_TIMING_TABLE_10[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_11", REG_SMC, 0x33040, &ixMCARB_DRAM_TIMING_TABLE_11[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_11)/sizeof(ixMCARB_DRAM_TIMING_TABLE_11[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_12", REG_SMC, 0x33044, &ixMCARB_DRAM_TIMING_TABLE_12[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_12)/sizeof(ixMCARB_DRAM_TIMING_TABLE_12[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_13", REG_SMC, 0x33048, &ixMCARB_DRAM_TIMING_TABLE_13[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_13)/sizeof(ixMCARB_DRAM_TIMING_TABLE_13[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_14", REG_SMC, 0x3304c, &ixMCARB_DRAM_TIMING_TABLE_14[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_14)/sizeof(ixMCARB_DRAM_TIMING_TABLE_14[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_15", REG_SMC, 0x33050, &ixMCARB_DRAM_TIMING_TABLE_15[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_15)/sizeof(ixMCARB_DRAM_TIMING_TABLE_15[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_16", REG_SMC, 0x33054, &ixMCARB_DRAM_TIMING_TABLE_16[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_16)/sizeof(ixMCARB_DRAM_TIMING_TABLE_16[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_17", REG_SMC, 0x33058, &ixMCARB_DRAM_TIMING_TABLE_17[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_17)/sizeof(ixMCARB_DRAM_TIMING_TABLE_17[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_18", REG_SMC, 0x3305c, &ixMCARB_DRAM_TIMING_TABLE_18[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_18)/sizeof(ixMCARB_DRAM_TIMING_TABLE_18[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_19", REG_SMC, 0x33060, &ixMCARB_DRAM_TIMING_TABLE_19[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_19)/sizeof(ixMCARB_DRAM_TIMING_TABLE_19[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_20", REG_SMC, 0x33064, &ixMCARB_DRAM_TIMING_TABLE_20[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_20)/sizeof(ixMCARB_DRAM_TIMING_TABLE_20[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_21", REG_SMC, 0x33068, &ixMCARB_DRAM_TIMING_TABLE_21[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_21)/sizeof(ixMCARB_DRAM_TIMING_TABLE_21[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_22", REG_SMC, 0x3306c, &ixMCARB_DRAM_TIMING_TABLE_22[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_22)/sizeof(ixMCARB_DRAM_TIMING_TABLE_22[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_23", REG_SMC, 0x33070, &ixMCARB_DRAM_TIMING_TABLE_23[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_23)/sizeof(ixMCARB_DRAM_TIMING_TABLE_23[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_24", REG_SMC, 0x33074, &ixMCARB_DRAM_TIMING_TABLE_24[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_24)/sizeof(ixMCARB_DRAM_TIMING_TABLE_24[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_25", REG_SMC, 0x33078, &ixMCARB_DRAM_TIMING_TABLE_25[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_25)/sizeof(ixMCARB_DRAM_TIMING_TABLE_25[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_26", REG_SMC, 0x3307c, &ixMCARB_DRAM_TIMING_TABLE_26[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_26)/sizeof(ixMCARB_DRAM_TIMING_TABLE_26[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_27", REG_SMC, 0x33080, &ixMCARB_DRAM_TIMING_TABLE_27[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_27)/sizeof(ixMCARB_DRAM_TIMING_TABLE_27[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_28", REG_SMC, 0x33084, &ixMCARB_DRAM_TIMING_TABLE_28[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_28)/sizeof(ixMCARB_DRAM_TIMING_TABLE_28[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_29", REG_SMC, 0x33088, &ixMCARB_DRAM_TIMING_TABLE_29[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_29)/sizeof(ixMCARB_DRAM_TIMING_TABLE_29[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_30", REG_SMC, 0x3308c, &ixMCARB_DRAM_TIMING_TABLE_30[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_30)/sizeof(ixMCARB_DRAM_TIMING_TABLE_30[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_31", REG_SMC, 0x33090, &ixMCARB_DRAM_TIMING_TABLE_31[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_31)/sizeof(ixMCARB_DRAM_TIMING_TABLE_31[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_32", REG_SMC, 0x33094, &ixMCARB_DRAM_TIMING_TABLE_32[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_32)/sizeof(ixMCARB_DRAM_TIMING_TABLE_32[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_33", REG_SMC, 0x33098, &ixMCARB_DRAM_TIMING_TABLE_33[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_33)/sizeof(ixMCARB_DRAM_TIMING_TABLE_33[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_34", REG_SMC, 0x3309c, &ixMCARB_DRAM_TIMING_TABLE_34[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_34)/sizeof(ixMCARB_DRAM_TIMING_TABLE_34[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_35", REG_SMC, 0x330a0, &ixMCARB_DRAM_TIMING_TABLE_35[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_35)/sizeof(ixMCARB_DRAM_TIMING_TABLE_35[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_36", REG_SMC, 0x330a4, &ixMCARB_DRAM_TIMING_TABLE_36[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_36)/sizeof(ixMCARB_DRAM_TIMING_TABLE_36[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_37", REG_SMC, 0x330a8, &ixMCARB_DRAM_TIMING_TABLE_37[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_37)/sizeof(ixMCARB_DRAM_TIMING_TABLE_37[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_38", REG_SMC, 0x330ac, &ixMCARB_DRAM_TIMING_TABLE_38[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_38)/sizeof(ixMCARB_DRAM_TIMING_TABLE_38[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_39", REG_SMC, 0x330b0, &ixMCARB_DRAM_TIMING_TABLE_39[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_39)/sizeof(ixMCARB_DRAM_TIMING_TABLE_39[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_40", REG_SMC, 0x330b4, &ixMCARB_DRAM_TIMING_TABLE_40[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_40)/sizeof(ixMCARB_DRAM_TIMING_TABLE_40[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_41", REG_SMC, 0x330b8, &ixMCARB_DRAM_TIMING_TABLE_41[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_41)/sizeof(ixMCARB_DRAM_TIMING_TABLE_41[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_42", REG_SMC, 0x330bc, &ixMCARB_DRAM_TIMING_TABLE_42[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_42)/sizeof(ixMCARB_DRAM_TIMING_TABLE_42[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_43", REG_SMC, 0x330c0, &ixMCARB_DRAM_TIMING_TABLE_43[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_43)/sizeof(ixMCARB_DRAM_TIMING_TABLE_43[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_44", REG_SMC, 0x330c4, &ixMCARB_DRAM_TIMING_TABLE_44[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_44)/sizeof(ixMCARB_DRAM_TIMING_TABLE_44[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_45", REG_SMC, 0x330c8, &ixMCARB_DRAM_TIMING_TABLE_45[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_45)/sizeof(ixMCARB_DRAM_TIMING_TABLE_45[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_46", REG_SMC, 0x330cc, &ixMCARB_DRAM_TIMING_TABLE_46[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_46)/sizeof(ixMCARB_DRAM_TIMING_TABLE_46[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_47", REG_SMC, 0x330d0, &ixMCARB_DRAM_TIMING_TABLE_47[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_47)/sizeof(ixMCARB_DRAM_TIMING_TABLE_47[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_48", REG_SMC, 0x330d4, &ixMCARB_DRAM_TIMING_TABLE_48[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_48)/sizeof(ixMCARB_DRAM_TIMING_TABLE_48[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_49", REG_SMC, 0x330d8, &ixMCARB_DRAM_TIMING_TABLE_49[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_49)/sizeof(ixMCARB_DRAM_TIMING_TABLE_49[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_50", REG_SMC, 0x330dc, &ixMCARB_DRAM_TIMING_TABLE_50[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_50)/sizeof(ixMCARB_DRAM_TIMING_TABLE_50[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_51", REG_SMC, 0x330e0, &ixMCARB_DRAM_TIMING_TABLE_51[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_51)/sizeof(ixMCARB_DRAM_TIMING_TABLE_51[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_52", REG_SMC, 0x330e4, &ixMCARB_DRAM_TIMING_TABLE_52[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_52)/sizeof(ixMCARB_DRAM_TIMING_TABLE_52[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_53", REG_SMC, 0x330e8, &ixMCARB_DRAM_TIMING_TABLE_53[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_53)/sizeof(ixMCARB_DRAM_TIMING_TABLE_53[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_54", REG_SMC, 0x330ec, &ixMCARB_DRAM_TIMING_TABLE_54[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_54)/sizeof(ixMCARB_DRAM_TIMING_TABLE_54[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_55", REG_SMC, 0x330f0, &ixMCARB_DRAM_TIMING_TABLE_55[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_55)/sizeof(ixMCARB_DRAM_TIMING_TABLE_55[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_56", REG_SMC, 0x330f4, &ixMCARB_DRAM_TIMING_TABLE_56[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_56)/sizeof(ixMCARB_DRAM_TIMING_TABLE_56[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_57", REG_SMC, 0x330f8, &ixMCARB_DRAM_TIMING_TABLE_57[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_57)/sizeof(ixMCARB_DRAM_TIMING_TABLE_57[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_58", REG_SMC, 0x330fc, &ixMCARB_DRAM_TIMING_TABLE_58[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_58)/sizeof(ixMCARB_DRAM_TIMING_TABLE_58[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_59", REG_SMC, 0x33100, &ixMCARB_DRAM_TIMING_TABLE_59[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_59)/sizeof(ixMCARB_DRAM_TIMING_TABLE_59[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_60", REG_SMC, 0x33104, &ixMCARB_DRAM_TIMING_TABLE_60[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_60)/sizeof(ixMCARB_DRAM_TIMING_TABLE_60[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_61", REG_SMC, 0x33108, &ixMCARB_DRAM_TIMING_TABLE_61[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_61)/sizeof(ixMCARB_DRAM_TIMING_TABLE_61[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_62", REG_SMC, 0x3310c, &ixMCARB_DRAM_TIMING_TABLE_62[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_62)/sizeof(ixMCARB_DRAM_TIMING_TABLE_62[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_63", REG_SMC, 0x33110, &ixMCARB_DRAM_TIMING_TABLE_63[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_63)/sizeof(ixMCARB_DRAM_TIMING_TABLE_63[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_64", REG_SMC, 0x33114, &ixMCARB_DRAM_TIMING_TABLE_64[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_64)/sizeof(ixMCARB_DRAM_TIMING_TABLE_64[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_65", REG_SMC, 0x33118, &ixMCARB_DRAM_TIMING_TABLE_65[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_65)/sizeof(ixMCARB_DRAM_TIMING_TABLE_65[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_66", REG_SMC, 0x3311c, &ixMCARB_DRAM_TIMING_TABLE_66[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_66)/sizeof(ixMCARB_DRAM_TIMING_TABLE_66[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_67", REG_SMC, 0x33120, &ixMCARB_DRAM_TIMING_TABLE_67[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_67)/sizeof(ixMCARB_DRAM_TIMING_TABLE_67[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_68", REG_SMC, 0x33124, &ixMCARB_DRAM_TIMING_TABLE_68[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_68)/sizeof(ixMCARB_DRAM_TIMING_TABLE_68[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_69", REG_SMC, 0x33128, &ixMCARB_DRAM_TIMING_TABLE_69[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_69)/sizeof(ixMCARB_DRAM_TIMING_TABLE_69[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_70", REG_SMC, 0x3312c, &ixMCARB_DRAM_TIMING_TABLE_70[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_70)/sizeof(ixMCARB_DRAM_TIMING_TABLE_70[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_71", REG_SMC, 0x33130, &ixMCARB_DRAM_TIMING_TABLE_71[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_71)/sizeof(ixMCARB_DRAM_TIMING_TABLE_71[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_72", REG_SMC, 0x33134, &ixMCARB_DRAM_TIMING_TABLE_72[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_72)/sizeof(ixMCARB_DRAM_TIMING_TABLE_72[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_73", REG_SMC, 0x33138, &ixMCARB_DRAM_TIMING_TABLE_73[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_73)/sizeof(ixMCARB_DRAM_TIMING_TABLE_73[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_74", REG_SMC, 0x3313c, &ixMCARB_DRAM_TIMING_TABLE_74[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_74)/sizeof(ixMCARB_DRAM_TIMING_TABLE_74[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_75", REG_SMC, 0x33140, &ixMCARB_DRAM_TIMING_TABLE_75[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_75)/sizeof(ixMCARB_DRAM_TIMING_TABLE_75[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_76", REG_SMC, 0x33144, &ixMCARB_DRAM_TIMING_TABLE_76[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_76)/sizeof(ixMCARB_DRAM_TIMING_TABLE_76[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_77", REG_SMC, 0x33148, &ixMCARB_DRAM_TIMING_TABLE_77[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_77)/sizeof(ixMCARB_DRAM_TIMING_TABLE_77[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_78", REG_SMC, 0x3314c, &ixMCARB_DRAM_TIMING_TABLE_78[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_78)/sizeof(ixMCARB_DRAM_TIMING_TABLE_78[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_79", REG_SMC, 0x33150, &ixMCARB_DRAM_TIMING_TABLE_79[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_79)/sizeof(ixMCARB_DRAM_TIMING_TABLE_79[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_80", REG_SMC, 0x33154, &ixMCARB_DRAM_TIMING_TABLE_80[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_80)/sizeof(ixMCARB_DRAM_TIMING_TABLE_80[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_81", REG_SMC, 0x33158, &ixMCARB_DRAM_TIMING_TABLE_81[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_81)/sizeof(ixMCARB_DRAM_TIMING_TABLE_81[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_82", REG_SMC, 0x3315c, &ixMCARB_DRAM_TIMING_TABLE_82[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_82)/sizeof(ixMCARB_DRAM_TIMING_TABLE_82[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_83", REG_SMC, 0x33160, &ixMCARB_DRAM_TIMING_TABLE_83[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_83)/sizeof(ixMCARB_DRAM_TIMING_TABLE_83[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_84", REG_SMC, 0x33164, &ixMCARB_DRAM_TIMING_TABLE_84[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_84)/sizeof(ixMCARB_DRAM_TIMING_TABLE_84[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_85", REG_SMC, 0x33168, &ixMCARB_DRAM_TIMING_TABLE_85[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_85)/sizeof(ixMCARB_DRAM_TIMING_TABLE_85[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_86", REG_SMC, 0x3316c, &ixMCARB_DRAM_TIMING_TABLE_86[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_86)/sizeof(ixMCARB_DRAM_TIMING_TABLE_86[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_87", REG_SMC, 0x33170, &ixMCARB_DRAM_TIMING_TABLE_87[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_87)/sizeof(ixMCARB_DRAM_TIMING_TABLE_87[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_88", REG_SMC, 0x33174, &ixMCARB_DRAM_TIMING_TABLE_88[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_88)/sizeof(ixMCARB_DRAM_TIMING_TABLE_88[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_89", REG_SMC, 0x33178, &ixMCARB_DRAM_TIMING_TABLE_89[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_89)/sizeof(ixMCARB_DRAM_TIMING_TABLE_89[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_90", REG_SMC, 0x3317c, &ixMCARB_DRAM_TIMING_TABLE_90[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_90)/sizeof(ixMCARB_DRAM_TIMING_TABLE_90[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_91", REG_SMC, 0x33180, &ixMCARB_DRAM_TIMING_TABLE_91[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_91)/sizeof(ixMCARB_DRAM_TIMING_TABLE_91[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_92", REG_SMC, 0x33184, &ixMCARB_DRAM_TIMING_TABLE_92[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_92)/sizeof(ixMCARB_DRAM_TIMING_TABLE_92[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_93", REG_SMC, 0x33188, &ixMCARB_DRAM_TIMING_TABLE_93[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_93)/sizeof(ixMCARB_DRAM_TIMING_TABLE_93[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_94", REG_SMC, 0x3318c, &ixMCARB_DRAM_TIMING_TABLE_94[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_94)/sizeof(ixMCARB_DRAM_TIMING_TABLE_94[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_95", REG_SMC, 0x33190, &ixMCARB_DRAM_TIMING_TABLE_95[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_95)/sizeof(ixMCARB_DRAM_TIMING_TABLE_95[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_96", REG_SMC, 0x33194, &ixMCARB_DRAM_TIMING_TABLE_96[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_96)/sizeof(ixMCARB_DRAM_TIMING_TABLE_96[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_1", REG_SMC, 0x33198, &ixMC_REGISTERS_TABLE_1[0], sizeof(ixMC_REGISTERS_TABLE_1)/sizeof(ixMC_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_2", REG_SMC, 0x3319c, &ixMC_REGISTERS_TABLE_2[0], sizeof(ixMC_REGISTERS_TABLE_2)/sizeof(ixMC_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_3", REG_SMC, 0x331a0, &ixMC_REGISTERS_TABLE_3[0], sizeof(ixMC_REGISTERS_TABLE_3)/sizeof(ixMC_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_4", REG_SMC, 0x331a4, &ixMC_REGISTERS_TABLE_4[0], sizeof(ixMC_REGISTERS_TABLE_4)/sizeof(ixMC_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_5", REG_SMC, 0x331a8, &ixMC_REGISTERS_TABLE_5[0], sizeof(ixMC_REGISTERS_TABLE_5)/sizeof(ixMC_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_6", REG_SMC, 0x331ac, &ixMC_REGISTERS_TABLE_6[0], sizeof(ixMC_REGISTERS_TABLE_6)/sizeof(ixMC_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_7", REG_SMC, 0x331b0, &ixMC_REGISTERS_TABLE_7[0], sizeof(ixMC_REGISTERS_TABLE_7)/sizeof(ixMC_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_8", REG_SMC, 0x331b4, &ixMC_REGISTERS_TABLE_8[0], sizeof(ixMC_REGISTERS_TABLE_8)/sizeof(ixMC_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_9", REG_SMC, 0x331b8, &ixMC_REGISTERS_TABLE_9[0], sizeof(ixMC_REGISTERS_TABLE_9)/sizeof(ixMC_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_10", REG_SMC, 0x331bc, &ixMC_REGISTERS_TABLE_10[0], sizeof(ixMC_REGISTERS_TABLE_10)/sizeof(ixMC_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_11", REG_SMC, 0x331c0, &ixMC_REGISTERS_TABLE_11[0], sizeof(ixMC_REGISTERS_TABLE_11)/sizeof(ixMC_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_12", REG_SMC, 0x331c4, &ixMC_REGISTERS_TABLE_12[0], sizeof(ixMC_REGISTERS_TABLE_12)/sizeof(ixMC_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_13", REG_SMC, 0x331c8, &ixMC_REGISTERS_TABLE_13[0], sizeof(ixMC_REGISTERS_TABLE_13)/sizeof(ixMC_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_14", REG_SMC, 0x331cc, &ixMC_REGISTERS_TABLE_14[0], sizeof(ixMC_REGISTERS_TABLE_14)/sizeof(ixMC_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_15", REG_SMC, 0x331d0, &ixMC_REGISTERS_TABLE_15[0], sizeof(ixMC_REGISTERS_TABLE_15)/sizeof(ixMC_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_16", REG_SMC, 0x331d4, &ixMC_REGISTERS_TABLE_16[0], sizeof(ixMC_REGISTERS_TABLE_16)/sizeof(ixMC_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_17", REG_SMC, 0x331d8, &ixMC_REGISTERS_TABLE_17[0], sizeof(ixMC_REGISTERS_TABLE_17)/sizeof(ixMC_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_18", REG_SMC, 0x331dc, &ixMC_REGISTERS_TABLE_18[0], sizeof(ixMC_REGISTERS_TABLE_18)/sizeof(ixMC_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_19", REG_SMC, 0x331e0, &ixMC_REGISTERS_TABLE_19[0], sizeof(ixMC_REGISTERS_TABLE_19)/sizeof(ixMC_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_20", REG_SMC, 0x331e4, &ixMC_REGISTERS_TABLE_20[0], sizeof(ixMC_REGISTERS_TABLE_20)/sizeof(ixMC_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_21", REG_SMC, 0x331e8, &ixMC_REGISTERS_TABLE_21[0], sizeof(ixMC_REGISTERS_TABLE_21)/sizeof(ixMC_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_22", REG_SMC, 0x331ec, &ixMC_REGISTERS_TABLE_22[0], sizeof(ixMC_REGISTERS_TABLE_22)/sizeof(ixMC_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_23", REG_SMC, 0x331f0, &ixMC_REGISTERS_TABLE_23[0], sizeof(ixMC_REGISTERS_TABLE_23)/sizeof(ixMC_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_24", REG_SMC, 0x331f4, &ixMC_REGISTERS_TABLE_24[0], sizeof(ixMC_REGISTERS_TABLE_24)/sizeof(ixMC_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_25", REG_SMC, 0x331f8, &ixMC_REGISTERS_TABLE_25[0], sizeof(ixMC_REGISTERS_TABLE_25)/sizeof(ixMC_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_26", REG_SMC, 0x331fc, &ixMC_REGISTERS_TABLE_26[0], sizeof(ixMC_REGISTERS_TABLE_26)/sizeof(ixMC_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_27", REG_SMC, 0x33200, &ixMC_REGISTERS_TABLE_27[0], sizeof(ixMC_REGISTERS_TABLE_27)/sizeof(ixMC_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_28", REG_SMC, 0x33204, &ixMC_REGISTERS_TABLE_28[0], sizeof(ixMC_REGISTERS_TABLE_28)/sizeof(ixMC_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_29", REG_SMC, 0x33208, &ixMC_REGISTERS_TABLE_29[0], sizeof(ixMC_REGISTERS_TABLE_29)/sizeof(ixMC_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_30", REG_SMC, 0x3320c, &ixMC_REGISTERS_TABLE_30[0], sizeof(ixMC_REGISTERS_TABLE_30)/sizeof(ixMC_REGISTERS_TABLE_30[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_31", REG_SMC, 0x33210, &ixMC_REGISTERS_TABLE_31[0], sizeof(ixMC_REGISTERS_TABLE_31)/sizeof(ixMC_REGISTERS_TABLE_31[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_32", REG_SMC, 0x33214, &ixMC_REGISTERS_TABLE_32[0], sizeof(ixMC_REGISTERS_TABLE_32)/sizeof(ixMC_REGISTERS_TABLE_32[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_33", REG_SMC, 0x33218, &ixMC_REGISTERS_TABLE_33[0], sizeof(ixMC_REGISTERS_TABLE_33)/sizeof(ixMC_REGISTERS_TABLE_33[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_34", REG_SMC, 0x3321c, &ixMC_REGISTERS_TABLE_34[0], sizeof(ixMC_REGISTERS_TABLE_34)/sizeof(ixMC_REGISTERS_TABLE_34[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_35", REG_SMC, 0x33220, &ixMC_REGISTERS_TABLE_35[0], sizeof(ixMC_REGISTERS_TABLE_35)/sizeof(ixMC_REGISTERS_TABLE_35[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_36", REG_SMC, 0x33224, &ixMC_REGISTERS_TABLE_36[0], sizeof(ixMC_REGISTERS_TABLE_36)/sizeof(ixMC_REGISTERS_TABLE_36[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_37", REG_SMC, 0x33228, &ixMC_REGISTERS_TABLE_37[0], sizeof(ixMC_REGISTERS_TABLE_37)/sizeof(ixMC_REGISTERS_TABLE_37[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_38", REG_SMC, 0x3322c, &ixMC_REGISTERS_TABLE_38[0], sizeof(ixMC_REGISTERS_TABLE_38)/sizeof(ixMC_REGISTERS_TABLE_38[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_39", REG_SMC, 0x33230, &ixMC_REGISTERS_TABLE_39[0], sizeof(ixMC_REGISTERS_TABLE_39)/sizeof(ixMC_REGISTERS_TABLE_39[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_40", REG_SMC, 0x33234, &ixMC_REGISTERS_TABLE_40[0], sizeof(ixMC_REGISTERS_TABLE_40)/sizeof(ixMC_REGISTERS_TABLE_40[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_41", REG_SMC, 0x33238, &ixMC_REGISTERS_TABLE_41[0], sizeof(ixMC_REGISTERS_TABLE_41)/sizeof(ixMC_REGISTERS_TABLE_41[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_42", REG_SMC, 0x3323c, &ixMC_REGISTERS_TABLE_42[0], sizeof(ixMC_REGISTERS_TABLE_42)/sizeof(ixMC_REGISTERS_TABLE_42[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_43", REG_SMC, 0x33240, &ixMC_REGISTERS_TABLE_43[0], sizeof(ixMC_REGISTERS_TABLE_43)/sizeof(ixMC_REGISTERS_TABLE_43[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_44", REG_SMC, 0x33244, &ixMC_REGISTERS_TABLE_44[0], sizeof(ixMC_REGISTERS_TABLE_44)/sizeof(ixMC_REGISTERS_TABLE_44[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_45", REG_SMC, 0x33248, &ixMC_REGISTERS_TABLE_45[0], sizeof(ixMC_REGISTERS_TABLE_45)/sizeof(ixMC_REGISTERS_TABLE_45[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_46", REG_SMC, 0x3324c, &ixMC_REGISTERS_TABLE_46[0], sizeof(ixMC_REGISTERS_TABLE_46)/sizeof(ixMC_REGISTERS_TABLE_46[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_47", REG_SMC, 0x33250, &ixMC_REGISTERS_TABLE_47[0], sizeof(ixMC_REGISTERS_TABLE_47)/sizeof(ixMC_REGISTERS_TABLE_47[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_48", REG_SMC, 0x33254, &ixMC_REGISTERS_TABLE_48[0], sizeof(ixMC_REGISTERS_TABLE_48)/sizeof(ixMC_REGISTERS_TABLE_48[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_49", REG_SMC, 0x33258, &ixMC_REGISTERS_TABLE_49[0], sizeof(ixMC_REGISTERS_TABLE_49)/sizeof(ixMC_REGISTERS_TABLE_49[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_50", REG_SMC, 0x3325c, &ixMC_REGISTERS_TABLE_50[0], sizeof(ixMC_REGISTERS_TABLE_50)/sizeof(ixMC_REGISTERS_TABLE_50[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_51", REG_SMC, 0x33260, &ixMC_REGISTERS_TABLE_51[0], sizeof(ixMC_REGISTERS_TABLE_51)/sizeof(ixMC_REGISTERS_TABLE_51[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_52", REG_SMC, 0x33264, &ixMC_REGISTERS_TABLE_52[0], sizeof(ixMC_REGISTERS_TABLE_52)/sizeof(ixMC_REGISTERS_TABLE_52[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_53", REG_SMC, 0x33268, &ixMC_REGISTERS_TABLE_53[0], sizeof(ixMC_REGISTERS_TABLE_53)/sizeof(ixMC_REGISTERS_TABLE_53[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_54", REG_SMC, 0x3326c, &ixMC_REGISTERS_TABLE_54[0], sizeof(ixMC_REGISTERS_TABLE_54)/sizeof(ixMC_REGISTERS_TABLE_54[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_55", REG_SMC, 0x33270, &ixMC_REGISTERS_TABLE_55[0], sizeof(ixMC_REGISTERS_TABLE_55)/sizeof(ixMC_REGISTERS_TABLE_55[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_56", REG_SMC, 0x33274, &ixMC_REGISTERS_TABLE_56[0], sizeof(ixMC_REGISTERS_TABLE_56)/sizeof(ixMC_REGISTERS_TABLE_56[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_57", REG_SMC, 0x33278, &ixMC_REGISTERS_TABLE_57[0], sizeof(ixMC_REGISTERS_TABLE_57)/sizeof(ixMC_REGISTERS_TABLE_57[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_58", REG_SMC, 0x3327c, &ixMC_REGISTERS_TABLE_58[0], sizeof(ixMC_REGISTERS_TABLE_58)/sizeof(ixMC_REGISTERS_TABLE_58[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_59", REG_SMC, 0x33280, &ixMC_REGISTERS_TABLE_59[0], sizeof(ixMC_REGISTERS_TABLE_59)/sizeof(ixMC_REGISTERS_TABLE_59[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_60", REG_SMC, 0x33284, &ixMC_REGISTERS_TABLE_60[0], sizeof(ixMC_REGISTERS_TABLE_60)/sizeof(ixMC_REGISTERS_TABLE_60[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_61", REG_SMC, 0x33288, &ixMC_REGISTERS_TABLE_61[0], sizeof(ixMC_REGISTERS_TABLE_61)/sizeof(ixMC_REGISTERS_TABLE_61[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_62", REG_SMC, 0x3328c, &ixMC_REGISTERS_TABLE_62[0], sizeof(ixMC_REGISTERS_TABLE_62)/sizeof(ixMC_REGISTERS_TABLE_62[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_63", REG_SMC, 0x33290, &ixMC_REGISTERS_TABLE_63[0], sizeof(ixMC_REGISTERS_TABLE_63)/sizeof(ixMC_REGISTERS_TABLE_63[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_64", REG_SMC, 0x33294, &ixMC_REGISTERS_TABLE_64[0], sizeof(ixMC_REGISTERS_TABLE_64)/sizeof(ixMC_REGISTERS_TABLE_64[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_65", REG_SMC, 0x33298, &ixMC_REGISTERS_TABLE_65[0], sizeof(ixMC_REGISTERS_TABLE_65)/sizeof(ixMC_REGISTERS_TABLE_65[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_66", REG_SMC, 0x3329c, &ixMC_REGISTERS_TABLE_66[0], sizeof(ixMC_REGISTERS_TABLE_66)/sizeof(ixMC_REGISTERS_TABLE_66[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_67", REG_SMC, 0x332a0, &ixMC_REGISTERS_TABLE_67[0], sizeof(ixMC_REGISTERS_TABLE_67)/sizeof(ixMC_REGISTERS_TABLE_67[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_68", REG_SMC, 0x332a4, &ixMC_REGISTERS_TABLE_68[0], sizeof(ixMC_REGISTERS_TABLE_68)/sizeof(ixMC_REGISTERS_TABLE_68[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_69", REG_SMC, 0x332a8, &ixMC_REGISTERS_TABLE_69[0], sizeof(ixMC_REGISTERS_TABLE_69)/sizeof(ixMC_REGISTERS_TABLE_69[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_70", REG_SMC, 0x332ac, &ixMC_REGISTERS_TABLE_70[0], sizeof(ixMC_REGISTERS_TABLE_70)/sizeof(ixMC_REGISTERS_TABLE_70[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_71", REG_SMC, 0x332b0, &ixMC_REGISTERS_TABLE_71[0], sizeof(ixMC_REGISTERS_TABLE_71)/sizeof(ixMC_REGISTERS_TABLE_71[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_72", REG_SMC, 0x332b4, &ixMC_REGISTERS_TABLE_72[0], sizeof(ixMC_REGISTERS_TABLE_72)/sizeof(ixMC_REGISTERS_TABLE_72[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_73", REG_SMC, 0x332b8, &ixMC_REGISTERS_TABLE_73[0], sizeof(ixMC_REGISTERS_TABLE_73)/sizeof(ixMC_REGISTERS_TABLE_73[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_74", REG_SMC, 0x332bc, &ixMC_REGISTERS_TABLE_74[0], sizeof(ixMC_REGISTERS_TABLE_74)/sizeof(ixMC_REGISTERS_TABLE_74[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_75", REG_SMC, 0x332c0, &ixMC_REGISTERS_TABLE_75[0], sizeof(ixMC_REGISTERS_TABLE_75)/sizeof(ixMC_REGISTERS_TABLE_75[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_76", REG_SMC, 0x332c4, &ixMC_REGISTERS_TABLE_76[0], sizeof(ixMC_REGISTERS_TABLE_76)/sizeof(ixMC_REGISTERS_TABLE_76[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_77", REG_SMC, 0x332c8, &ixMC_REGISTERS_TABLE_77[0], sizeof(ixMC_REGISTERS_TABLE_77)/sizeof(ixMC_REGISTERS_TABLE_77[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_78", REG_SMC, 0x332cc, &ixMC_REGISTERS_TABLE_78[0], sizeof(ixMC_REGISTERS_TABLE_78)/sizeof(ixMC_REGISTERS_TABLE_78[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_79", REG_SMC, 0x332d0, &ixMC_REGISTERS_TABLE_79[0], sizeof(ixMC_REGISTERS_TABLE_79)/sizeof(ixMC_REGISTERS_TABLE_79[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_80", REG_SMC, 0x332d4, &ixMC_REGISTERS_TABLE_80[0], sizeof(ixMC_REGISTERS_TABLE_80)/sizeof(ixMC_REGISTERS_TABLE_80[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_81", REG_SMC, 0x332d8, &ixMC_REGISTERS_TABLE_81[0], sizeof(ixMC_REGISTERS_TABLE_81)/sizeof(ixMC_REGISTERS_TABLE_81[0]), 0, 0 },
+	{ "ixDPM_TABLE_1", REG_SMC, 0x332dc, &ixDPM_TABLE_1[0], sizeof(ixDPM_TABLE_1)/sizeof(ixDPM_TABLE_1[0]), 0, 0 },
+	{ "ixDPM_TABLE_2", REG_SMC, 0x332e0, &ixDPM_TABLE_2[0], sizeof(ixDPM_TABLE_2)/sizeof(ixDPM_TABLE_2[0]), 0, 0 },
+	{ "ixDPM_TABLE_3", REG_SMC, 0x332e4, &ixDPM_TABLE_3[0], sizeof(ixDPM_TABLE_3)/sizeof(ixDPM_TABLE_3[0]), 0, 0 },
+	{ "ixDPM_TABLE_4", REG_SMC, 0x332e8, &ixDPM_TABLE_4[0], sizeof(ixDPM_TABLE_4)/sizeof(ixDPM_TABLE_4[0]), 0, 0 },
+	{ "ixDPM_TABLE_5", REG_SMC, 0x332ec, &ixDPM_TABLE_5[0], sizeof(ixDPM_TABLE_5)/sizeof(ixDPM_TABLE_5[0]), 0, 0 },
+	{ "ixDPM_TABLE_6", REG_SMC, 0x332f0, &ixDPM_TABLE_6[0], sizeof(ixDPM_TABLE_6)/sizeof(ixDPM_TABLE_6[0]), 0, 0 },
+	{ "ixDPM_TABLE_7", REG_SMC, 0x332f4, &ixDPM_TABLE_7[0], sizeof(ixDPM_TABLE_7)/sizeof(ixDPM_TABLE_7[0]), 0, 0 },
+	{ "ixDPM_TABLE_8", REG_SMC, 0x332f8, &ixDPM_TABLE_8[0], sizeof(ixDPM_TABLE_8)/sizeof(ixDPM_TABLE_8[0]), 0, 0 },
+	{ "ixDPM_TABLE_9", REG_SMC, 0x332fc, &ixDPM_TABLE_9[0], sizeof(ixDPM_TABLE_9)/sizeof(ixDPM_TABLE_9[0]), 0, 0 },
+	{ "ixDPM_TABLE_10", REG_SMC, 0x33300, &ixDPM_TABLE_10[0], sizeof(ixDPM_TABLE_10)/sizeof(ixDPM_TABLE_10[0]), 0, 0 },
+	{ "ixDPM_TABLE_11", REG_SMC, 0x33304, &ixDPM_TABLE_11[0], sizeof(ixDPM_TABLE_11)/sizeof(ixDPM_TABLE_11[0]), 0, 0 },
+	{ "ixDPM_TABLE_12", REG_SMC, 0x33308, &ixDPM_TABLE_12[0], sizeof(ixDPM_TABLE_12)/sizeof(ixDPM_TABLE_12[0]), 0, 0 },
+	{ "ixDPM_TABLE_13", REG_SMC, 0x3330c, &ixDPM_TABLE_13[0], sizeof(ixDPM_TABLE_13)/sizeof(ixDPM_TABLE_13[0]), 0, 0 },
+	{ "ixDPM_TABLE_14", REG_SMC, 0x33310, &ixDPM_TABLE_14[0], sizeof(ixDPM_TABLE_14)/sizeof(ixDPM_TABLE_14[0]), 0, 0 },
+	{ "ixDPM_TABLE_15", REG_SMC, 0x33314, &ixDPM_TABLE_15[0], sizeof(ixDPM_TABLE_15)/sizeof(ixDPM_TABLE_15[0]), 0, 0 },
+	{ "ixDPM_TABLE_16", REG_SMC, 0x33318, &ixDPM_TABLE_16[0], sizeof(ixDPM_TABLE_16)/sizeof(ixDPM_TABLE_16[0]), 0, 0 },
+	{ "ixDPM_TABLE_17", REG_SMC, 0x3331c, &ixDPM_TABLE_17[0], sizeof(ixDPM_TABLE_17)/sizeof(ixDPM_TABLE_17[0]), 0, 0 },
+	{ "ixDPM_TABLE_18", REG_SMC, 0x33320, &ixDPM_TABLE_18[0], sizeof(ixDPM_TABLE_18)/sizeof(ixDPM_TABLE_18[0]), 0, 0 },
+	{ "ixDPM_TABLE_19", REG_SMC, 0x33324, &ixDPM_TABLE_19[0], sizeof(ixDPM_TABLE_19)/sizeof(ixDPM_TABLE_19[0]), 0, 0 },
+	{ "ixDPM_TABLE_20", REG_SMC, 0x33328, &ixDPM_TABLE_20[0], sizeof(ixDPM_TABLE_20)/sizeof(ixDPM_TABLE_20[0]), 0, 0 },
+	{ "ixDPM_TABLE_21", REG_SMC, 0x3332c, &ixDPM_TABLE_21[0], sizeof(ixDPM_TABLE_21)/sizeof(ixDPM_TABLE_21[0]), 0, 0 },
+	{ "ixDPM_TABLE_22", REG_SMC, 0x33330, &ixDPM_TABLE_22[0], sizeof(ixDPM_TABLE_22)/sizeof(ixDPM_TABLE_22[0]), 0, 0 },
+	{ "ixDPM_TABLE_23", REG_SMC, 0x33334, &ixDPM_TABLE_23[0], sizeof(ixDPM_TABLE_23)/sizeof(ixDPM_TABLE_23[0]), 0, 0 },
+	{ "ixDPM_TABLE_24", REG_SMC, 0x33338, &ixDPM_TABLE_24[0], sizeof(ixDPM_TABLE_24)/sizeof(ixDPM_TABLE_24[0]), 0, 0 },
+	{ "ixDPM_TABLE_25", REG_SMC, 0x3333c, &ixDPM_TABLE_25[0], sizeof(ixDPM_TABLE_25)/sizeof(ixDPM_TABLE_25[0]), 0, 0 },
+	{ "ixDPM_TABLE_26", REG_SMC, 0x33340, &ixDPM_TABLE_26[0], sizeof(ixDPM_TABLE_26)/sizeof(ixDPM_TABLE_26[0]), 0, 0 },
+	{ "ixDPM_TABLE_27", REG_SMC, 0x33344, &ixDPM_TABLE_27[0], sizeof(ixDPM_TABLE_27)/sizeof(ixDPM_TABLE_27[0]), 0, 0 },
+	{ "ixDPM_TABLE_28", REG_SMC, 0x33348, &ixDPM_TABLE_28[0], sizeof(ixDPM_TABLE_28)/sizeof(ixDPM_TABLE_28[0]), 0, 0 },
+	{ "ixDPM_TABLE_29", REG_SMC, 0x3334c, &ixDPM_TABLE_29[0], sizeof(ixDPM_TABLE_29)/sizeof(ixDPM_TABLE_29[0]), 0, 0 },
+	{ "ixDPM_TABLE_30", REG_SMC, 0x33350, &ixDPM_TABLE_30[0], sizeof(ixDPM_TABLE_30)/sizeof(ixDPM_TABLE_30[0]), 0, 0 },
+	{ "ixDPM_TABLE_31", REG_SMC, 0x33354, &ixDPM_TABLE_31[0], sizeof(ixDPM_TABLE_31)/sizeof(ixDPM_TABLE_31[0]), 0, 0 },
+	{ "ixDPM_TABLE_32", REG_SMC, 0x33358, &ixDPM_TABLE_32[0], sizeof(ixDPM_TABLE_32)/sizeof(ixDPM_TABLE_32[0]), 0, 0 },
+	{ "ixDPM_TABLE_33", REG_SMC, 0x3335c, &ixDPM_TABLE_33[0], sizeof(ixDPM_TABLE_33)/sizeof(ixDPM_TABLE_33[0]), 0, 0 },
+	{ "ixDPM_TABLE_34", REG_SMC, 0x33360, &ixDPM_TABLE_34[0], sizeof(ixDPM_TABLE_34)/sizeof(ixDPM_TABLE_34[0]), 0, 0 },
+	{ "ixDPM_TABLE_35", REG_SMC, 0x33364, &ixDPM_TABLE_35[0], sizeof(ixDPM_TABLE_35)/sizeof(ixDPM_TABLE_35[0]), 0, 0 },
+	{ "ixDPM_TABLE_36", REG_SMC, 0x33368, &ixDPM_TABLE_36[0], sizeof(ixDPM_TABLE_36)/sizeof(ixDPM_TABLE_36[0]), 0, 0 },
+	{ "ixDPM_TABLE_37", REG_SMC, 0x3336c, &ixDPM_TABLE_37[0], sizeof(ixDPM_TABLE_37)/sizeof(ixDPM_TABLE_37[0]), 0, 0 },
+	{ "ixDPM_TABLE_38", REG_SMC, 0x33370, &ixDPM_TABLE_38[0], sizeof(ixDPM_TABLE_38)/sizeof(ixDPM_TABLE_38[0]), 0, 0 },
+	{ "ixDPM_TABLE_39", REG_SMC, 0x33374, &ixDPM_TABLE_39[0], sizeof(ixDPM_TABLE_39)/sizeof(ixDPM_TABLE_39[0]), 0, 0 },
+	{ "ixDPM_TABLE_40", REG_SMC, 0x33378, &ixDPM_TABLE_40[0], sizeof(ixDPM_TABLE_40)/sizeof(ixDPM_TABLE_40[0]), 0, 0 },
+	{ "ixDPM_TABLE_41", REG_SMC, 0x3337c, &ixDPM_TABLE_41[0], sizeof(ixDPM_TABLE_41)/sizeof(ixDPM_TABLE_41[0]), 0, 0 },
+	{ "ixDPM_TABLE_42", REG_SMC, 0x33380, &ixDPM_TABLE_42[0], sizeof(ixDPM_TABLE_42)/sizeof(ixDPM_TABLE_42[0]), 0, 0 },
+	{ "ixDPM_TABLE_43", REG_SMC, 0x33384, &ixDPM_TABLE_43[0], sizeof(ixDPM_TABLE_43)/sizeof(ixDPM_TABLE_43[0]), 0, 0 },
+	{ "ixDPM_TABLE_44", REG_SMC, 0x33388, &ixDPM_TABLE_44[0], sizeof(ixDPM_TABLE_44)/sizeof(ixDPM_TABLE_44[0]), 0, 0 },
+	{ "ixDPM_TABLE_45", REG_SMC, 0x3338c, &ixDPM_TABLE_45[0], sizeof(ixDPM_TABLE_45)/sizeof(ixDPM_TABLE_45[0]), 0, 0 },
+	{ "ixDPM_TABLE_46", REG_SMC, 0x33390, &ixDPM_TABLE_46[0], sizeof(ixDPM_TABLE_46)/sizeof(ixDPM_TABLE_46[0]), 0, 0 },
+	{ "ixDPM_TABLE_47", REG_SMC, 0x33394, &ixDPM_TABLE_47[0], sizeof(ixDPM_TABLE_47)/sizeof(ixDPM_TABLE_47[0]), 0, 0 },
+	{ "ixDPM_TABLE_48", REG_SMC, 0x33398, &ixDPM_TABLE_48[0], sizeof(ixDPM_TABLE_48)/sizeof(ixDPM_TABLE_48[0]), 0, 0 },
+	{ "ixDPM_TABLE_49", REG_SMC, 0x3339c, &ixDPM_TABLE_49[0], sizeof(ixDPM_TABLE_49)/sizeof(ixDPM_TABLE_49[0]), 0, 0 },
+	{ "ixDPM_TABLE_50", REG_SMC, 0x333a0, &ixDPM_TABLE_50[0], sizeof(ixDPM_TABLE_50)/sizeof(ixDPM_TABLE_50[0]), 0, 0 },
+	{ "ixDPM_TABLE_51", REG_SMC, 0x333a4, &ixDPM_TABLE_51[0], sizeof(ixDPM_TABLE_51)/sizeof(ixDPM_TABLE_51[0]), 0, 0 },
+	{ "ixDPM_TABLE_52", REG_SMC, 0x333a8, &ixDPM_TABLE_52[0], sizeof(ixDPM_TABLE_52)/sizeof(ixDPM_TABLE_52[0]), 0, 0 },
+	{ "ixDPM_TABLE_53", REG_SMC, 0x333ac, &ixDPM_TABLE_53[0], sizeof(ixDPM_TABLE_53)/sizeof(ixDPM_TABLE_53[0]), 0, 0 },
+	{ "ixDPM_TABLE_54", REG_SMC, 0x333b0, &ixDPM_TABLE_54[0], sizeof(ixDPM_TABLE_54)/sizeof(ixDPM_TABLE_54[0]), 0, 0 },
+	{ "ixDPM_TABLE_55", REG_SMC, 0x333b4, &ixDPM_TABLE_55[0], sizeof(ixDPM_TABLE_55)/sizeof(ixDPM_TABLE_55[0]), 0, 0 },
+	{ "ixDPM_TABLE_56", REG_SMC, 0x333b8, &ixDPM_TABLE_56[0], sizeof(ixDPM_TABLE_56)/sizeof(ixDPM_TABLE_56[0]), 0, 0 },
+	{ "ixDPM_TABLE_57", REG_SMC, 0x333bc, &ixDPM_TABLE_57[0], sizeof(ixDPM_TABLE_57)/sizeof(ixDPM_TABLE_57[0]), 0, 0 },
+	{ "ixDPM_TABLE_58", REG_SMC, 0x333c0, &ixDPM_TABLE_58[0], sizeof(ixDPM_TABLE_58)/sizeof(ixDPM_TABLE_58[0]), 0, 0 },
+	{ "ixDPM_TABLE_59", REG_SMC, 0x333c4, &ixDPM_TABLE_59[0], sizeof(ixDPM_TABLE_59)/sizeof(ixDPM_TABLE_59[0]), 0, 0 },
+	{ "ixDPM_TABLE_60", REG_SMC, 0x333c8, &ixDPM_TABLE_60[0], sizeof(ixDPM_TABLE_60)/sizeof(ixDPM_TABLE_60[0]), 0, 0 },
+	{ "ixDPM_TABLE_61", REG_SMC, 0x333cc, &ixDPM_TABLE_61[0], sizeof(ixDPM_TABLE_61)/sizeof(ixDPM_TABLE_61[0]), 0, 0 },
+	{ "ixDPM_TABLE_62", REG_SMC, 0x333d0, &ixDPM_TABLE_62[0], sizeof(ixDPM_TABLE_62)/sizeof(ixDPM_TABLE_62[0]), 0, 0 },
+	{ "ixDPM_TABLE_63", REG_SMC, 0x333d4, &ixDPM_TABLE_63[0], sizeof(ixDPM_TABLE_63)/sizeof(ixDPM_TABLE_63[0]), 0, 0 },
+	{ "ixDPM_TABLE_64", REG_SMC, 0x333d8, &ixDPM_TABLE_64[0], sizeof(ixDPM_TABLE_64)/sizeof(ixDPM_TABLE_64[0]), 0, 0 },
+	{ "ixDPM_TABLE_65", REG_SMC, 0x333dc, &ixDPM_TABLE_65[0], sizeof(ixDPM_TABLE_65)/sizeof(ixDPM_TABLE_65[0]), 0, 0 },
+	{ "ixDPM_TABLE_66", REG_SMC, 0x333e0, &ixDPM_TABLE_66[0], sizeof(ixDPM_TABLE_66)/sizeof(ixDPM_TABLE_66[0]), 0, 0 },
+	{ "ixDPM_TABLE_67", REG_SMC, 0x333e4, &ixDPM_TABLE_67[0], sizeof(ixDPM_TABLE_67)/sizeof(ixDPM_TABLE_67[0]), 0, 0 },
+	{ "ixDPM_TABLE_68", REG_SMC, 0x333e8, &ixDPM_TABLE_68[0], sizeof(ixDPM_TABLE_68)/sizeof(ixDPM_TABLE_68[0]), 0, 0 },
+	{ "ixDPM_TABLE_69", REG_SMC, 0x333ec, &ixDPM_TABLE_69[0], sizeof(ixDPM_TABLE_69)/sizeof(ixDPM_TABLE_69[0]), 0, 0 },
+	{ "ixDPM_TABLE_70", REG_SMC, 0x333f0, &ixDPM_TABLE_70[0], sizeof(ixDPM_TABLE_70)/sizeof(ixDPM_TABLE_70[0]), 0, 0 },
+	{ "ixDPM_TABLE_71", REG_SMC, 0x333f4, &ixDPM_TABLE_71[0], sizeof(ixDPM_TABLE_71)/sizeof(ixDPM_TABLE_71[0]), 0, 0 },
+	{ "ixDPM_TABLE_72", REG_SMC, 0x333f8, &ixDPM_TABLE_72[0], sizeof(ixDPM_TABLE_72)/sizeof(ixDPM_TABLE_72[0]), 0, 0 },
+	{ "ixDPM_TABLE_73", REG_SMC, 0x333fc, &ixDPM_TABLE_73[0], sizeof(ixDPM_TABLE_73)/sizeof(ixDPM_TABLE_73[0]), 0, 0 },
+	{ "ixDPM_TABLE_74", REG_SMC, 0x33400, &ixDPM_TABLE_74[0], sizeof(ixDPM_TABLE_74)/sizeof(ixDPM_TABLE_74[0]), 0, 0 },
+	{ "ixDPM_TABLE_75", REG_SMC, 0x33404, &ixDPM_TABLE_75[0], sizeof(ixDPM_TABLE_75)/sizeof(ixDPM_TABLE_75[0]), 0, 0 },
+	{ "ixDPM_TABLE_76", REG_SMC, 0x33408, &ixDPM_TABLE_76[0], sizeof(ixDPM_TABLE_76)/sizeof(ixDPM_TABLE_76[0]), 0, 0 },
+	{ "ixDPM_TABLE_77", REG_SMC, 0x3340c, &ixDPM_TABLE_77[0], sizeof(ixDPM_TABLE_77)/sizeof(ixDPM_TABLE_77[0]), 0, 0 },
+	{ "ixDPM_TABLE_78", REG_SMC, 0x33410, &ixDPM_TABLE_78[0], sizeof(ixDPM_TABLE_78)/sizeof(ixDPM_TABLE_78[0]), 0, 0 },
+	{ "ixDPM_TABLE_79", REG_SMC, 0x33414, &ixDPM_TABLE_79[0], sizeof(ixDPM_TABLE_79)/sizeof(ixDPM_TABLE_79[0]), 0, 0 },
+	{ "ixDPM_TABLE_80", REG_SMC, 0x33418, &ixDPM_TABLE_80[0], sizeof(ixDPM_TABLE_80)/sizeof(ixDPM_TABLE_80[0]), 0, 0 },
+	{ "ixDPM_TABLE_81", REG_SMC, 0x3341c, &ixDPM_TABLE_81[0], sizeof(ixDPM_TABLE_81)/sizeof(ixDPM_TABLE_81[0]), 0, 0 },
+	{ "ixDPM_TABLE_82", REG_SMC, 0x33420, &ixDPM_TABLE_82[0], sizeof(ixDPM_TABLE_82)/sizeof(ixDPM_TABLE_82[0]), 0, 0 },
+	{ "ixDPM_TABLE_83", REG_SMC, 0x33424, &ixDPM_TABLE_83[0], sizeof(ixDPM_TABLE_83)/sizeof(ixDPM_TABLE_83[0]), 0, 0 },
+	{ "ixDPM_TABLE_84", REG_SMC, 0x33428, &ixDPM_TABLE_84[0], sizeof(ixDPM_TABLE_84)/sizeof(ixDPM_TABLE_84[0]), 0, 0 },
+	{ "ixDPM_TABLE_85", REG_SMC, 0x3342c, &ixDPM_TABLE_85[0], sizeof(ixDPM_TABLE_85)/sizeof(ixDPM_TABLE_85[0]), 0, 0 },
+	{ "ixDPM_TABLE_86", REG_SMC, 0x33430, &ixDPM_TABLE_86[0], sizeof(ixDPM_TABLE_86)/sizeof(ixDPM_TABLE_86[0]), 0, 0 },
+	{ "ixDPM_TABLE_87", REG_SMC, 0x33434, &ixDPM_TABLE_87[0], sizeof(ixDPM_TABLE_87)/sizeof(ixDPM_TABLE_87[0]), 0, 0 },
+	{ "ixDPM_TABLE_88", REG_SMC, 0x33438, &ixDPM_TABLE_88[0], sizeof(ixDPM_TABLE_88)/sizeof(ixDPM_TABLE_88[0]), 0, 0 },
+	{ "ixDPM_TABLE_89", REG_SMC, 0x3343c, &ixDPM_TABLE_89[0], sizeof(ixDPM_TABLE_89)/sizeof(ixDPM_TABLE_89[0]), 0, 0 },
+	{ "ixDPM_TABLE_90", REG_SMC, 0x33440, &ixDPM_TABLE_90[0], sizeof(ixDPM_TABLE_90)/sizeof(ixDPM_TABLE_90[0]), 0, 0 },
+	{ "ixDPM_TABLE_91", REG_SMC, 0x33444, &ixDPM_TABLE_91[0], sizeof(ixDPM_TABLE_91)/sizeof(ixDPM_TABLE_91[0]), 0, 0 },
+	{ "ixDPM_TABLE_92", REG_SMC, 0x33448, &ixDPM_TABLE_92[0], sizeof(ixDPM_TABLE_92)/sizeof(ixDPM_TABLE_92[0]), 0, 0 },
+	{ "ixDPM_TABLE_93", REG_SMC, 0x3344c, &ixDPM_TABLE_93[0], sizeof(ixDPM_TABLE_93)/sizeof(ixDPM_TABLE_93[0]), 0, 0 },
+	{ "ixDPM_TABLE_94", REG_SMC, 0x33450, &ixDPM_TABLE_94[0], sizeof(ixDPM_TABLE_94)/sizeof(ixDPM_TABLE_94[0]), 0, 0 },
+	{ "ixDPM_TABLE_95", REG_SMC, 0x33454, &ixDPM_TABLE_95[0], sizeof(ixDPM_TABLE_95)/sizeof(ixDPM_TABLE_95[0]), 0, 0 },
+	{ "ixDPM_TABLE_96", REG_SMC, 0x33458, &ixDPM_TABLE_96[0], sizeof(ixDPM_TABLE_96)/sizeof(ixDPM_TABLE_96[0]), 0, 0 },
+	{ "ixDPM_TABLE_97", REG_SMC, 0x3345c, &ixDPM_TABLE_97[0], sizeof(ixDPM_TABLE_97)/sizeof(ixDPM_TABLE_97[0]), 0, 0 },
+	{ "ixDPM_TABLE_98", REG_SMC, 0x33460, &ixDPM_TABLE_98[0], sizeof(ixDPM_TABLE_98)/sizeof(ixDPM_TABLE_98[0]), 0, 0 },
+	{ "ixDPM_TABLE_99", REG_SMC, 0x33464, &ixDPM_TABLE_99[0], sizeof(ixDPM_TABLE_99)/sizeof(ixDPM_TABLE_99[0]), 0, 0 },
+	{ "ixDPM_TABLE_100", REG_SMC, 0x33468, &ixDPM_TABLE_100[0], sizeof(ixDPM_TABLE_100)/sizeof(ixDPM_TABLE_100[0]), 0, 0 },
+	{ "ixDPM_TABLE_101", REG_SMC, 0x3346c, &ixDPM_TABLE_101[0], sizeof(ixDPM_TABLE_101)/sizeof(ixDPM_TABLE_101[0]), 0, 0 },
+	{ "ixDPM_TABLE_102", REG_SMC, 0x33470, &ixDPM_TABLE_102[0], sizeof(ixDPM_TABLE_102)/sizeof(ixDPM_TABLE_102[0]), 0, 0 },
+	{ "ixDPM_TABLE_103", REG_SMC, 0x33474, &ixDPM_TABLE_103[0], sizeof(ixDPM_TABLE_103)/sizeof(ixDPM_TABLE_103[0]), 0, 0 },
+	{ "ixDPM_TABLE_104", REG_SMC, 0x33478, &ixDPM_TABLE_104[0], sizeof(ixDPM_TABLE_104)/sizeof(ixDPM_TABLE_104[0]), 0, 0 },
+	{ "ixDPM_TABLE_105", REG_SMC, 0x3347c, &ixDPM_TABLE_105[0], sizeof(ixDPM_TABLE_105)/sizeof(ixDPM_TABLE_105[0]), 0, 0 },
+	{ "ixDPM_TABLE_106", REG_SMC, 0x33480, &ixDPM_TABLE_106[0], sizeof(ixDPM_TABLE_106)/sizeof(ixDPM_TABLE_106[0]), 0, 0 },
+	{ "ixDPM_TABLE_107", REG_SMC, 0x33484, &ixDPM_TABLE_107[0], sizeof(ixDPM_TABLE_107)/sizeof(ixDPM_TABLE_107[0]), 0, 0 },
+	{ "ixDPM_TABLE_108", REG_SMC, 0x33488, &ixDPM_TABLE_108[0], sizeof(ixDPM_TABLE_108)/sizeof(ixDPM_TABLE_108[0]), 0, 0 },
+	{ "ixDPM_TABLE_109", REG_SMC, 0x3348c, &ixDPM_TABLE_109[0], sizeof(ixDPM_TABLE_109)/sizeof(ixDPM_TABLE_109[0]), 0, 0 },
+	{ "ixDPM_TABLE_110", REG_SMC, 0x33490, &ixDPM_TABLE_110[0], sizeof(ixDPM_TABLE_110)/sizeof(ixDPM_TABLE_110[0]), 0, 0 },
+	{ "ixDPM_TABLE_111", REG_SMC, 0x33494, &ixDPM_TABLE_111[0], sizeof(ixDPM_TABLE_111)/sizeof(ixDPM_TABLE_111[0]), 0, 0 },
+	{ "ixDPM_TABLE_112", REG_SMC, 0x33498, &ixDPM_TABLE_112[0], sizeof(ixDPM_TABLE_112)/sizeof(ixDPM_TABLE_112[0]), 0, 0 },
+	{ "ixDPM_TABLE_113", REG_SMC, 0x3349c, &ixDPM_TABLE_113[0], sizeof(ixDPM_TABLE_113)/sizeof(ixDPM_TABLE_113[0]), 0, 0 },
+	{ "ixDPM_TABLE_114", REG_SMC, 0x334a0, &ixDPM_TABLE_114[0], sizeof(ixDPM_TABLE_114)/sizeof(ixDPM_TABLE_114[0]), 0, 0 },
+	{ "ixDPM_TABLE_115", REG_SMC, 0x334a4, &ixDPM_TABLE_115[0], sizeof(ixDPM_TABLE_115)/sizeof(ixDPM_TABLE_115[0]), 0, 0 },
+	{ "ixDPM_TABLE_116", REG_SMC, 0x334a8, &ixDPM_TABLE_116[0], sizeof(ixDPM_TABLE_116)/sizeof(ixDPM_TABLE_116[0]), 0, 0 },
+	{ "ixDPM_TABLE_117", REG_SMC, 0x334ac, &ixDPM_TABLE_117[0], sizeof(ixDPM_TABLE_117)/sizeof(ixDPM_TABLE_117[0]), 0, 0 },
+	{ "ixDPM_TABLE_118", REG_SMC, 0x334b0, &ixDPM_TABLE_118[0], sizeof(ixDPM_TABLE_118)/sizeof(ixDPM_TABLE_118[0]), 0, 0 },
+	{ "ixDPM_TABLE_119", REG_SMC, 0x334b4, &ixDPM_TABLE_119[0], sizeof(ixDPM_TABLE_119)/sizeof(ixDPM_TABLE_119[0]), 0, 0 },
+	{ "ixDPM_TABLE_120", REG_SMC, 0x334b8, &ixDPM_TABLE_120[0], sizeof(ixDPM_TABLE_120)/sizeof(ixDPM_TABLE_120[0]), 0, 0 },
+	{ "ixDPM_TABLE_121", REG_SMC, 0x334bc, &ixDPM_TABLE_121[0], sizeof(ixDPM_TABLE_121)/sizeof(ixDPM_TABLE_121[0]), 0, 0 },
+	{ "ixDPM_TABLE_122", REG_SMC, 0x334c0, &ixDPM_TABLE_122[0], sizeof(ixDPM_TABLE_122)/sizeof(ixDPM_TABLE_122[0]), 0, 0 },
+	{ "ixDPM_TABLE_123", REG_SMC, 0x334c4, &ixDPM_TABLE_123[0], sizeof(ixDPM_TABLE_123)/sizeof(ixDPM_TABLE_123[0]), 0, 0 },
+	{ "ixDPM_TABLE_124", REG_SMC, 0x334c8, &ixDPM_TABLE_124[0], sizeof(ixDPM_TABLE_124)/sizeof(ixDPM_TABLE_124[0]), 0, 0 },
+	{ "ixDPM_TABLE_125", REG_SMC, 0x334cc, &ixDPM_TABLE_125[0], sizeof(ixDPM_TABLE_125)/sizeof(ixDPM_TABLE_125[0]), 0, 0 },
+	{ "ixDPM_TABLE_126", REG_SMC, 0x334d0, &ixDPM_TABLE_126[0], sizeof(ixDPM_TABLE_126)/sizeof(ixDPM_TABLE_126[0]), 0, 0 },
+	{ "ixDPM_TABLE_127", REG_SMC, 0x334d4, &ixDPM_TABLE_127[0], sizeof(ixDPM_TABLE_127)/sizeof(ixDPM_TABLE_127[0]), 0, 0 },
+	{ "ixDPM_TABLE_128", REG_SMC, 0x334d8, &ixDPM_TABLE_128[0], sizeof(ixDPM_TABLE_128)/sizeof(ixDPM_TABLE_128[0]), 0, 0 },
+	{ "ixDPM_TABLE_129", REG_SMC, 0x334dc, &ixDPM_TABLE_129[0], sizeof(ixDPM_TABLE_129)/sizeof(ixDPM_TABLE_129[0]), 0, 0 },
+	{ "ixDPM_TABLE_130", REG_SMC, 0x334e0, &ixDPM_TABLE_130[0], sizeof(ixDPM_TABLE_130)/sizeof(ixDPM_TABLE_130[0]), 0, 0 },
+	{ "ixDPM_TABLE_131", REG_SMC, 0x334e4, &ixDPM_TABLE_131[0], sizeof(ixDPM_TABLE_131)/sizeof(ixDPM_TABLE_131[0]), 0, 0 },
+	{ "ixDPM_TABLE_132", REG_SMC, 0x334e8, &ixDPM_TABLE_132[0], sizeof(ixDPM_TABLE_132)/sizeof(ixDPM_TABLE_132[0]), 0, 0 },
+	{ "ixDPM_TABLE_133", REG_SMC, 0x334ec, &ixDPM_TABLE_133[0], sizeof(ixDPM_TABLE_133)/sizeof(ixDPM_TABLE_133[0]), 0, 0 },
+	{ "ixDPM_TABLE_134", REG_SMC, 0x334f0, &ixDPM_TABLE_134[0], sizeof(ixDPM_TABLE_134)/sizeof(ixDPM_TABLE_134[0]), 0, 0 },
+	{ "ixDPM_TABLE_135", REG_SMC, 0x334f4, &ixDPM_TABLE_135[0], sizeof(ixDPM_TABLE_135)/sizeof(ixDPM_TABLE_135[0]), 0, 0 },
+	{ "ixDPM_TABLE_136", REG_SMC, 0x334f8, &ixDPM_TABLE_136[0], sizeof(ixDPM_TABLE_136)/sizeof(ixDPM_TABLE_136[0]), 0, 0 },
+	{ "ixDPM_TABLE_137", REG_SMC, 0x334fc, &ixDPM_TABLE_137[0], sizeof(ixDPM_TABLE_137)/sizeof(ixDPM_TABLE_137[0]), 0, 0 },
+	{ "ixDPM_TABLE_138", REG_SMC, 0x33500, &ixDPM_TABLE_138[0], sizeof(ixDPM_TABLE_138)/sizeof(ixDPM_TABLE_138[0]), 0, 0 },
+	{ "ixDPM_TABLE_139", REG_SMC, 0x33504, &ixDPM_TABLE_139[0], sizeof(ixDPM_TABLE_139)/sizeof(ixDPM_TABLE_139[0]), 0, 0 },
+	{ "ixDPM_TABLE_140", REG_SMC, 0x33508, &ixDPM_TABLE_140[0], sizeof(ixDPM_TABLE_140)/sizeof(ixDPM_TABLE_140[0]), 0, 0 },
+	{ "ixDPM_TABLE_141", REG_SMC, 0x3350c, &ixDPM_TABLE_141[0], sizeof(ixDPM_TABLE_141)/sizeof(ixDPM_TABLE_141[0]), 0, 0 },
+	{ "ixDPM_TABLE_142", REG_SMC, 0x33510, &ixDPM_TABLE_142[0], sizeof(ixDPM_TABLE_142)/sizeof(ixDPM_TABLE_142[0]), 0, 0 },
+	{ "ixDPM_TABLE_143", REG_SMC, 0x33514, &ixDPM_TABLE_143[0], sizeof(ixDPM_TABLE_143)/sizeof(ixDPM_TABLE_143[0]), 0, 0 },
+	{ "ixDPM_TABLE_144", REG_SMC, 0x33518, &ixDPM_TABLE_144[0], sizeof(ixDPM_TABLE_144)/sizeof(ixDPM_TABLE_144[0]), 0, 0 },
+	{ "ixDPM_TABLE_145", REG_SMC, 0x3351c, &ixDPM_TABLE_145[0], sizeof(ixDPM_TABLE_145)/sizeof(ixDPM_TABLE_145[0]), 0, 0 },
+	{ "ixDPM_TABLE_146", REG_SMC, 0x33520, &ixDPM_TABLE_146[0], sizeof(ixDPM_TABLE_146)/sizeof(ixDPM_TABLE_146[0]), 0, 0 },
+	{ "ixDPM_TABLE_147", REG_SMC, 0x33524, &ixDPM_TABLE_147[0], sizeof(ixDPM_TABLE_147)/sizeof(ixDPM_TABLE_147[0]), 0, 0 },
+	{ "ixDPM_TABLE_148", REG_SMC, 0x33528, &ixDPM_TABLE_148[0], sizeof(ixDPM_TABLE_148)/sizeof(ixDPM_TABLE_148[0]), 0, 0 },
+	{ "ixDPM_TABLE_149", REG_SMC, 0x3352c, &ixDPM_TABLE_149[0], sizeof(ixDPM_TABLE_149)/sizeof(ixDPM_TABLE_149[0]), 0, 0 },
+	{ "ixDPM_TABLE_150", REG_SMC, 0x33530, &ixDPM_TABLE_150[0], sizeof(ixDPM_TABLE_150)/sizeof(ixDPM_TABLE_150[0]), 0, 0 },
+	{ "ixDPM_TABLE_151", REG_SMC, 0x33534, &ixDPM_TABLE_151[0], sizeof(ixDPM_TABLE_151)/sizeof(ixDPM_TABLE_151[0]), 0, 0 },
+	{ "ixDPM_TABLE_152", REG_SMC, 0x33538, &ixDPM_TABLE_152[0], sizeof(ixDPM_TABLE_152)/sizeof(ixDPM_TABLE_152[0]), 0, 0 },
+	{ "ixDPM_TABLE_153", REG_SMC, 0x3353c, &ixDPM_TABLE_153[0], sizeof(ixDPM_TABLE_153)/sizeof(ixDPM_TABLE_153[0]), 0, 0 },
+	{ "ixDPM_TABLE_154", REG_SMC, 0x33540, &ixDPM_TABLE_154[0], sizeof(ixDPM_TABLE_154)/sizeof(ixDPM_TABLE_154[0]), 0, 0 },
+	{ "ixDPM_TABLE_155", REG_SMC, 0x33544, &ixDPM_TABLE_155[0], sizeof(ixDPM_TABLE_155)/sizeof(ixDPM_TABLE_155[0]), 0, 0 },
+	{ "ixDPM_TABLE_156", REG_SMC, 0x33548, &ixDPM_TABLE_156[0], sizeof(ixDPM_TABLE_156)/sizeof(ixDPM_TABLE_156[0]), 0, 0 },
+	{ "ixDPM_TABLE_157", REG_SMC, 0x3354c, &ixDPM_TABLE_157[0], sizeof(ixDPM_TABLE_157)/sizeof(ixDPM_TABLE_157[0]), 0, 0 },
+	{ "ixDPM_TABLE_158", REG_SMC, 0x33550, &ixDPM_TABLE_158[0], sizeof(ixDPM_TABLE_158)/sizeof(ixDPM_TABLE_158[0]), 0, 0 },
+	{ "ixDPM_TABLE_159", REG_SMC, 0x33554, &ixDPM_TABLE_159[0], sizeof(ixDPM_TABLE_159)/sizeof(ixDPM_TABLE_159[0]), 0, 0 },
+	{ "ixDPM_TABLE_160", REG_SMC, 0x33558, &ixDPM_TABLE_160[0], sizeof(ixDPM_TABLE_160)/sizeof(ixDPM_TABLE_160[0]), 0, 0 },
+	{ "ixDPM_TABLE_161", REG_SMC, 0x3355c, &ixDPM_TABLE_161[0], sizeof(ixDPM_TABLE_161)/sizeof(ixDPM_TABLE_161[0]), 0, 0 },
+	{ "ixDPM_TABLE_162", REG_SMC, 0x33560, &ixDPM_TABLE_162[0], sizeof(ixDPM_TABLE_162)/sizeof(ixDPM_TABLE_162[0]), 0, 0 },
+	{ "ixDPM_TABLE_163", REG_SMC, 0x33564, &ixDPM_TABLE_163[0], sizeof(ixDPM_TABLE_163)/sizeof(ixDPM_TABLE_163[0]), 0, 0 },
+	{ "ixDPM_TABLE_164", REG_SMC, 0x33568, &ixDPM_TABLE_164[0], sizeof(ixDPM_TABLE_164)/sizeof(ixDPM_TABLE_164[0]), 0, 0 },
+	{ "ixDPM_TABLE_165", REG_SMC, 0x3356c, &ixDPM_TABLE_165[0], sizeof(ixDPM_TABLE_165)/sizeof(ixDPM_TABLE_165[0]), 0, 0 },
+	{ "ixDPM_TABLE_166", REG_SMC, 0x33570, &ixDPM_TABLE_166[0], sizeof(ixDPM_TABLE_166)/sizeof(ixDPM_TABLE_166[0]), 0, 0 },
+	{ "ixDPM_TABLE_167", REG_SMC, 0x33574, &ixDPM_TABLE_167[0], sizeof(ixDPM_TABLE_167)/sizeof(ixDPM_TABLE_167[0]), 0, 0 },
+	{ "ixDPM_TABLE_168", REG_SMC, 0x33578, &ixDPM_TABLE_168[0], sizeof(ixDPM_TABLE_168)/sizeof(ixDPM_TABLE_168[0]), 0, 0 },
+	{ "ixDPM_TABLE_169", REG_SMC, 0x3357c, &ixDPM_TABLE_169[0], sizeof(ixDPM_TABLE_169)/sizeof(ixDPM_TABLE_169[0]), 0, 0 },
+	{ "ixDPM_TABLE_170", REG_SMC, 0x33580, &ixDPM_TABLE_170[0], sizeof(ixDPM_TABLE_170)/sizeof(ixDPM_TABLE_170[0]), 0, 0 },
+	{ "ixDPM_TABLE_171", REG_SMC, 0x33584, &ixDPM_TABLE_171[0], sizeof(ixDPM_TABLE_171)/sizeof(ixDPM_TABLE_171[0]), 0, 0 },
+	{ "ixDPM_TABLE_172", REG_SMC, 0x33588, &ixDPM_TABLE_172[0], sizeof(ixDPM_TABLE_172)/sizeof(ixDPM_TABLE_172[0]), 0, 0 },
+	{ "ixDPM_TABLE_173", REG_SMC, 0x3358c, &ixDPM_TABLE_173[0], sizeof(ixDPM_TABLE_173)/sizeof(ixDPM_TABLE_173[0]), 0, 0 },
+	{ "ixDPM_TABLE_174", REG_SMC, 0x33590, &ixDPM_TABLE_174[0], sizeof(ixDPM_TABLE_174)/sizeof(ixDPM_TABLE_174[0]), 0, 0 },
+	{ "ixDPM_TABLE_175", REG_SMC, 0x33594, &ixDPM_TABLE_175[0], sizeof(ixDPM_TABLE_175)/sizeof(ixDPM_TABLE_175[0]), 0, 0 },
+	{ "ixDPM_TABLE_176", REG_SMC, 0x33598, &ixDPM_TABLE_176[0], sizeof(ixDPM_TABLE_176)/sizeof(ixDPM_TABLE_176[0]), 0, 0 },
+	{ "ixDPM_TABLE_177", REG_SMC, 0x3359c, &ixDPM_TABLE_177[0], sizeof(ixDPM_TABLE_177)/sizeof(ixDPM_TABLE_177[0]), 0, 0 },
+	{ "ixDPM_TABLE_178", REG_SMC, 0x335a0, &ixDPM_TABLE_178[0], sizeof(ixDPM_TABLE_178)/sizeof(ixDPM_TABLE_178[0]), 0, 0 },
+	{ "ixDPM_TABLE_179", REG_SMC, 0x335a4, &ixDPM_TABLE_179[0], sizeof(ixDPM_TABLE_179)/sizeof(ixDPM_TABLE_179[0]), 0, 0 },
+	{ "ixDPM_TABLE_180", REG_SMC, 0x335a8, &ixDPM_TABLE_180[0], sizeof(ixDPM_TABLE_180)/sizeof(ixDPM_TABLE_180[0]), 0, 0 },
+	{ "ixDPM_TABLE_181", REG_SMC, 0x335ac, &ixDPM_TABLE_181[0], sizeof(ixDPM_TABLE_181)/sizeof(ixDPM_TABLE_181[0]), 0, 0 },
+	{ "ixDPM_TABLE_182", REG_SMC, 0x335b0, &ixDPM_TABLE_182[0], sizeof(ixDPM_TABLE_182)/sizeof(ixDPM_TABLE_182[0]), 0, 0 },
+	{ "ixDPM_TABLE_183", REG_SMC, 0x335b4, &ixDPM_TABLE_183[0], sizeof(ixDPM_TABLE_183)/sizeof(ixDPM_TABLE_183[0]), 0, 0 },
+	{ "ixDPM_TABLE_184", REG_SMC, 0x335b8, &ixDPM_TABLE_184[0], sizeof(ixDPM_TABLE_184)/sizeof(ixDPM_TABLE_184[0]), 0, 0 },
+	{ "ixDPM_TABLE_185", REG_SMC, 0x335bc, &ixDPM_TABLE_185[0], sizeof(ixDPM_TABLE_185)/sizeof(ixDPM_TABLE_185[0]), 0, 0 },
+	{ "ixDPM_TABLE_186", REG_SMC, 0x335c0, &ixDPM_TABLE_186[0], sizeof(ixDPM_TABLE_186)/sizeof(ixDPM_TABLE_186[0]), 0, 0 },
+	{ "ixDPM_TABLE_187", REG_SMC, 0x335c4, &ixDPM_TABLE_187[0], sizeof(ixDPM_TABLE_187)/sizeof(ixDPM_TABLE_187[0]), 0, 0 },
+	{ "ixDPM_TABLE_188", REG_SMC, 0x335c8, &ixDPM_TABLE_188[0], sizeof(ixDPM_TABLE_188)/sizeof(ixDPM_TABLE_188[0]), 0, 0 },
+	{ "ixDPM_TABLE_189", REG_SMC, 0x335cc, &ixDPM_TABLE_189[0], sizeof(ixDPM_TABLE_189)/sizeof(ixDPM_TABLE_189[0]), 0, 0 },
+	{ "ixDPM_TABLE_190", REG_SMC, 0x335d0, &ixDPM_TABLE_190[0], sizeof(ixDPM_TABLE_190)/sizeof(ixDPM_TABLE_190[0]), 0, 0 },
+	{ "ixDPM_TABLE_191", REG_SMC, 0x335d4, &ixDPM_TABLE_191[0], sizeof(ixDPM_TABLE_191)/sizeof(ixDPM_TABLE_191[0]), 0, 0 },
+	{ "ixDPM_TABLE_192", REG_SMC, 0x335d8, &ixDPM_TABLE_192[0], sizeof(ixDPM_TABLE_192)/sizeof(ixDPM_TABLE_192[0]), 0, 0 },
+	{ "ixDPM_TABLE_193", REG_SMC, 0x335dc, &ixDPM_TABLE_193[0], sizeof(ixDPM_TABLE_193)/sizeof(ixDPM_TABLE_193[0]), 0, 0 },
+	{ "ixDPM_TABLE_194", REG_SMC, 0x335e0, &ixDPM_TABLE_194[0], sizeof(ixDPM_TABLE_194)/sizeof(ixDPM_TABLE_194[0]), 0, 0 },
+	{ "ixDPM_TABLE_195", REG_SMC, 0x335e4, &ixDPM_TABLE_195[0], sizeof(ixDPM_TABLE_195)/sizeof(ixDPM_TABLE_195[0]), 0, 0 },
+	{ "ixDPM_TABLE_196", REG_SMC, 0x335e8, &ixDPM_TABLE_196[0], sizeof(ixDPM_TABLE_196)/sizeof(ixDPM_TABLE_196[0]), 0, 0 },
+	{ "ixDPM_TABLE_197", REG_SMC, 0x335ec, &ixDPM_TABLE_197[0], sizeof(ixDPM_TABLE_197)/sizeof(ixDPM_TABLE_197[0]), 0, 0 },
+	{ "ixDPM_TABLE_198", REG_SMC, 0x335f0, &ixDPM_TABLE_198[0], sizeof(ixDPM_TABLE_198)/sizeof(ixDPM_TABLE_198[0]), 0, 0 },
+	{ "ixDPM_TABLE_199", REG_SMC, 0x335f4, &ixDPM_TABLE_199[0], sizeof(ixDPM_TABLE_199)/sizeof(ixDPM_TABLE_199[0]), 0, 0 },
+	{ "ixDPM_TABLE_200", REG_SMC, 0x335f8, &ixDPM_TABLE_200[0], sizeof(ixDPM_TABLE_200)/sizeof(ixDPM_TABLE_200[0]), 0, 0 },
+	{ "ixDPM_TABLE_201", REG_SMC, 0x335fc, &ixDPM_TABLE_201[0], sizeof(ixDPM_TABLE_201)/sizeof(ixDPM_TABLE_201[0]), 0, 0 },
+	{ "ixDPM_TABLE_202", REG_SMC, 0x33600, &ixDPM_TABLE_202[0], sizeof(ixDPM_TABLE_202)/sizeof(ixDPM_TABLE_202[0]), 0, 0 },
+	{ "ixDPM_TABLE_203", REG_SMC, 0x33604, &ixDPM_TABLE_203[0], sizeof(ixDPM_TABLE_203)/sizeof(ixDPM_TABLE_203[0]), 0, 0 },
+	{ "ixDPM_TABLE_204", REG_SMC, 0x33608, &ixDPM_TABLE_204[0], sizeof(ixDPM_TABLE_204)/sizeof(ixDPM_TABLE_204[0]), 0, 0 },
+	{ "ixDPM_TABLE_205", REG_SMC, 0x3360c, &ixDPM_TABLE_205[0], sizeof(ixDPM_TABLE_205)/sizeof(ixDPM_TABLE_205[0]), 0, 0 },
+	{ "ixDPM_TABLE_206", REG_SMC, 0x33610, &ixDPM_TABLE_206[0], sizeof(ixDPM_TABLE_206)/sizeof(ixDPM_TABLE_206[0]), 0, 0 },
+	{ "ixDPM_TABLE_207", REG_SMC, 0x33614, &ixDPM_TABLE_207[0], sizeof(ixDPM_TABLE_207)/sizeof(ixDPM_TABLE_207[0]), 0, 0 },
+	{ "ixDPM_TABLE_208", REG_SMC, 0x33618, &ixDPM_TABLE_208[0], sizeof(ixDPM_TABLE_208)/sizeof(ixDPM_TABLE_208[0]), 0, 0 },
+	{ "ixDPM_TABLE_209", REG_SMC, 0x3361c, &ixDPM_TABLE_209[0], sizeof(ixDPM_TABLE_209)/sizeof(ixDPM_TABLE_209[0]), 0, 0 },
+	{ "ixDPM_TABLE_210", REG_SMC, 0x33620, &ixDPM_TABLE_210[0], sizeof(ixDPM_TABLE_210)/sizeof(ixDPM_TABLE_210[0]), 0, 0 },
+	{ "ixDPM_TABLE_211", REG_SMC, 0x33624, &ixDPM_TABLE_211[0], sizeof(ixDPM_TABLE_211)/sizeof(ixDPM_TABLE_211[0]), 0, 0 },
+	{ "ixDPM_TABLE_212", REG_SMC, 0x33628, &ixDPM_TABLE_212[0], sizeof(ixDPM_TABLE_212)/sizeof(ixDPM_TABLE_212[0]), 0, 0 },
+	{ "ixDPM_TABLE_213", REG_SMC, 0x3362c, &ixDPM_TABLE_213[0], sizeof(ixDPM_TABLE_213)/sizeof(ixDPM_TABLE_213[0]), 0, 0 },
+	{ "ixDPM_TABLE_214", REG_SMC, 0x33630, &ixDPM_TABLE_214[0], sizeof(ixDPM_TABLE_214)/sizeof(ixDPM_TABLE_214[0]), 0, 0 },
+	{ "ixDPM_TABLE_215", REG_SMC, 0x33634, &ixDPM_TABLE_215[0], sizeof(ixDPM_TABLE_215)/sizeof(ixDPM_TABLE_215[0]), 0, 0 },
+	{ "ixDPM_TABLE_216", REG_SMC, 0x33638, &ixDPM_TABLE_216[0], sizeof(ixDPM_TABLE_216)/sizeof(ixDPM_TABLE_216[0]), 0, 0 },
+	{ "ixDPM_TABLE_217", REG_SMC, 0x3363c, &ixDPM_TABLE_217[0], sizeof(ixDPM_TABLE_217)/sizeof(ixDPM_TABLE_217[0]), 0, 0 },
+	{ "ixDPM_TABLE_218", REG_SMC, 0x33640, &ixDPM_TABLE_218[0], sizeof(ixDPM_TABLE_218)/sizeof(ixDPM_TABLE_218[0]), 0, 0 },
+	{ "ixDPM_TABLE_219", REG_SMC, 0x33644, &ixDPM_TABLE_219[0], sizeof(ixDPM_TABLE_219)/sizeof(ixDPM_TABLE_219[0]), 0, 0 },
+	{ "ixDPM_TABLE_220", REG_SMC, 0x33648, &ixDPM_TABLE_220[0], sizeof(ixDPM_TABLE_220)/sizeof(ixDPM_TABLE_220[0]), 0, 0 },
+	{ "ixDPM_TABLE_221", REG_SMC, 0x3364c, &ixDPM_TABLE_221[0], sizeof(ixDPM_TABLE_221)/sizeof(ixDPM_TABLE_221[0]), 0, 0 },
+	{ "ixDPM_TABLE_222", REG_SMC, 0x33650, &ixDPM_TABLE_222[0], sizeof(ixDPM_TABLE_222)/sizeof(ixDPM_TABLE_222[0]), 0, 0 },
+	{ "ixDPM_TABLE_223", REG_SMC, 0x33654, &ixDPM_TABLE_223[0], sizeof(ixDPM_TABLE_223)/sizeof(ixDPM_TABLE_223[0]), 0, 0 },
+	{ "ixDPM_TABLE_224", REG_SMC, 0x33658, &ixDPM_TABLE_224[0], sizeof(ixDPM_TABLE_224)/sizeof(ixDPM_TABLE_224[0]), 0, 0 },
+	{ "ixDPM_TABLE_225", REG_SMC, 0x3365c, &ixDPM_TABLE_225[0], sizeof(ixDPM_TABLE_225)/sizeof(ixDPM_TABLE_225[0]), 0, 0 },
+	{ "ixDPM_TABLE_226", REG_SMC, 0x33660, &ixDPM_TABLE_226[0], sizeof(ixDPM_TABLE_226)/sizeof(ixDPM_TABLE_226[0]), 0, 0 },
+	{ "ixDPM_TABLE_227", REG_SMC, 0x33664, &ixDPM_TABLE_227[0], sizeof(ixDPM_TABLE_227)/sizeof(ixDPM_TABLE_227[0]), 0, 0 },
+	{ "ixDPM_TABLE_228", REG_SMC, 0x33668, &ixDPM_TABLE_228[0], sizeof(ixDPM_TABLE_228)/sizeof(ixDPM_TABLE_228[0]), 0, 0 },
+	{ "ixDPM_TABLE_229", REG_SMC, 0x3366c, &ixDPM_TABLE_229[0], sizeof(ixDPM_TABLE_229)/sizeof(ixDPM_TABLE_229[0]), 0, 0 },
+	{ "ixDPM_TABLE_230", REG_SMC, 0x33670, &ixDPM_TABLE_230[0], sizeof(ixDPM_TABLE_230)/sizeof(ixDPM_TABLE_230[0]), 0, 0 },
+	{ "ixDPM_TABLE_231", REG_SMC, 0x33674, &ixDPM_TABLE_231[0], sizeof(ixDPM_TABLE_231)/sizeof(ixDPM_TABLE_231[0]), 0, 0 },
+	{ "ixDPM_TABLE_232", REG_SMC, 0x33678, &ixDPM_TABLE_232[0], sizeof(ixDPM_TABLE_232)/sizeof(ixDPM_TABLE_232[0]), 0, 0 },
+	{ "ixDPM_TABLE_233", REG_SMC, 0x3367c, &ixDPM_TABLE_233[0], sizeof(ixDPM_TABLE_233)/sizeof(ixDPM_TABLE_233[0]), 0, 0 },
+	{ "ixDPM_TABLE_234", REG_SMC, 0x33680, &ixDPM_TABLE_234[0], sizeof(ixDPM_TABLE_234)/sizeof(ixDPM_TABLE_234[0]), 0, 0 },
+	{ "ixDPM_TABLE_235", REG_SMC, 0x33684, &ixDPM_TABLE_235[0], sizeof(ixDPM_TABLE_235)/sizeof(ixDPM_TABLE_235[0]), 0, 0 },
+	{ "ixDPM_TABLE_236", REG_SMC, 0x33688, &ixDPM_TABLE_236[0], sizeof(ixDPM_TABLE_236)/sizeof(ixDPM_TABLE_236[0]), 0, 0 },
+	{ "ixDPM_TABLE_237", REG_SMC, 0x3368c, &ixDPM_TABLE_237[0], sizeof(ixDPM_TABLE_237)/sizeof(ixDPM_TABLE_237[0]), 0, 0 },
+	{ "ixDPM_TABLE_238", REG_SMC, 0x33690, &ixDPM_TABLE_238[0], sizeof(ixDPM_TABLE_238)/sizeof(ixDPM_TABLE_238[0]), 0, 0 },
+	{ "ixDPM_TABLE_239", REG_SMC, 0x33694, &ixDPM_TABLE_239[0], sizeof(ixDPM_TABLE_239)/sizeof(ixDPM_TABLE_239[0]), 0, 0 },
+	{ "ixDPM_TABLE_240", REG_SMC, 0x33698, &ixDPM_TABLE_240[0], sizeof(ixDPM_TABLE_240)/sizeof(ixDPM_TABLE_240[0]), 0, 0 },
+	{ "ixDPM_TABLE_241", REG_SMC, 0x3369c, &ixDPM_TABLE_241[0], sizeof(ixDPM_TABLE_241)/sizeof(ixDPM_TABLE_241[0]), 0, 0 },
+	{ "ixDPM_TABLE_242", REG_SMC, 0x336a0, &ixDPM_TABLE_242[0], sizeof(ixDPM_TABLE_242)/sizeof(ixDPM_TABLE_242[0]), 0, 0 },
+	{ "ixDPM_TABLE_243", REG_SMC, 0x336a4, &ixDPM_TABLE_243[0], sizeof(ixDPM_TABLE_243)/sizeof(ixDPM_TABLE_243[0]), 0, 0 },
+	{ "ixDPM_TABLE_244", REG_SMC, 0x336a8, &ixDPM_TABLE_244[0], sizeof(ixDPM_TABLE_244)/sizeof(ixDPM_TABLE_244[0]), 0, 0 },
+	{ "ixDPM_TABLE_245", REG_SMC, 0x336ac, &ixDPM_TABLE_245[0], sizeof(ixDPM_TABLE_245)/sizeof(ixDPM_TABLE_245[0]), 0, 0 },
+	{ "ixDPM_TABLE_246", REG_SMC, 0x336b0, &ixDPM_TABLE_246[0], sizeof(ixDPM_TABLE_246)/sizeof(ixDPM_TABLE_246[0]), 0, 0 },
+	{ "ixDPM_TABLE_247", REG_SMC, 0x336b4, &ixDPM_TABLE_247[0], sizeof(ixDPM_TABLE_247)/sizeof(ixDPM_TABLE_247[0]), 0, 0 },
+	{ "ixDPM_TABLE_248", REG_SMC, 0x336b8, &ixDPM_TABLE_248[0], sizeof(ixDPM_TABLE_248)/sizeof(ixDPM_TABLE_248[0]), 0, 0 },
+	{ "ixDPM_TABLE_249", REG_SMC, 0x336bc, &ixDPM_TABLE_249[0], sizeof(ixDPM_TABLE_249)/sizeof(ixDPM_TABLE_249[0]), 0, 0 },
+	{ "ixDPM_TABLE_250", REG_SMC, 0x336c0, &ixDPM_TABLE_250[0], sizeof(ixDPM_TABLE_250)/sizeof(ixDPM_TABLE_250[0]), 0, 0 },
+	{ "ixDPM_TABLE_251", REG_SMC, 0x336c4, &ixDPM_TABLE_251[0], sizeof(ixDPM_TABLE_251)/sizeof(ixDPM_TABLE_251[0]), 0, 0 },
+	{ "ixDPM_TABLE_252", REG_SMC, 0x336c8, &ixDPM_TABLE_252[0], sizeof(ixDPM_TABLE_252)/sizeof(ixDPM_TABLE_252[0]), 0, 0 },
+	{ "ixDPM_TABLE_253", REG_SMC, 0x336cc, &ixDPM_TABLE_253[0], sizeof(ixDPM_TABLE_253)/sizeof(ixDPM_TABLE_253[0]), 0, 0 },
+	{ "ixDPM_TABLE_254", REG_SMC, 0x336d0, &ixDPM_TABLE_254[0], sizeof(ixDPM_TABLE_254)/sizeof(ixDPM_TABLE_254[0]), 0, 0 },
+	{ "ixDPM_TABLE_255", REG_SMC, 0x336d4, &ixDPM_TABLE_255[0], sizeof(ixDPM_TABLE_255)/sizeof(ixDPM_TABLE_255[0]), 0, 0 },
+	{ "ixDPM_TABLE_256", REG_SMC, 0x336d8, &ixDPM_TABLE_256[0], sizeof(ixDPM_TABLE_256)/sizeof(ixDPM_TABLE_256[0]), 0, 0 },
+	{ "ixDPM_TABLE_257", REG_SMC, 0x336dc, &ixDPM_TABLE_257[0], sizeof(ixDPM_TABLE_257)/sizeof(ixDPM_TABLE_257[0]), 0, 0 },
+	{ "ixDPM_TABLE_258", REG_SMC, 0x336e0, &ixDPM_TABLE_258[0], sizeof(ixDPM_TABLE_258)/sizeof(ixDPM_TABLE_258[0]), 0, 0 },
+	{ "ixDPM_TABLE_259", REG_SMC, 0x336e4, &ixDPM_TABLE_259[0], sizeof(ixDPM_TABLE_259)/sizeof(ixDPM_TABLE_259[0]), 0, 0 },
+	{ "ixDPM_TABLE_260", REG_SMC, 0x336e8, &ixDPM_TABLE_260[0], sizeof(ixDPM_TABLE_260)/sizeof(ixDPM_TABLE_260[0]), 0, 0 },
+	{ "ixDPM_TABLE_261", REG_SMC, 0x336ec, &ixDPM_TABLE_261[0], sizeof(ixDPM_TABLE_261)/sizeof(ixDPM_TABLE_261[0]), 0, 0 },
+	{ "ixDPM_TABLE_262", REG_SMC, 0x336f0, &ixDPM_TABLE_262[0], sizeof(ixDPM_TABLE_262)/sizeof(ixDPM_TABLE_262[0]), 0, 0 },
+	{ "ixDPM_TABLE_263", REG_SMC, 0x336f4, &ixDPM_TABLE_263[0], sizeof(ixDPM_TABLE_263)/sizeof(ixDPM_TABLE_263[0]), 0, 0 },
+	{ "ixDPM_TABLE_264", REG_SMC, 0x336f8, &ixDPM_TABLE_264[0], sizeof(ixDPM_TABLE_264)/sizeof(ixDPM_TABLE_264[0]), 0, 0 },
+	{ "ixDPM_TABLE_265", REG_SMC, 0x336fc, &ixDPM_TABLE_265[0], sizeof(ixDPM_TABLE_265)/sizeof(ixDPM_TABLE_265[0]), 0, 0 },
+	{ "ixDPM_TABLE_266", REG_SMC, 0x33700, &ixDPM_TABLE_266[0], sizeof(ixDPM_TABLE_266)/sizeof(ixDPM_TABLE_266[0]), 0, 0 },
+	{ "ixDPM_TABLE_267", REG_SMC, 0x33704, &ixDPM_TABLE_267[0], sizeof(ixDPM_TABLE_267)/sizeof(ixDPM_TABLE_267[0]), 0, 0 },
+	{ "ixDPM_TABLE_268", REG_SMC, 0x33708, &ixDPM_TABLE_268[0], sizeof(ixDPM_TABLE_268)/sizeof(ixDPM_TABLE_268[0]), 0, 0 },
+	{ "ixDPM_TABLE_269", REG_SMC, 0x3370c, &ixDPM_TABLE_269[0], sizeof(ixDPM_TABLE_269)/sizeof(ixDPM_TABLE_269[0]), 0, 0 },
+	{ "ixDPM_TABLE_270", REG_SMC, 0x33710, &ixDPM_TABLE_270[0], sizeof(ixDPM_TABLE_270)/sizeof(ixDPM_TABLE_270[0]), 0, 0 },
+	{ "ixDPM_TABLE_271", REG_SMC, 0x33714, &ixDPM_TABLE_271[0], sizeof(ixDPM_TABLE_271)/sizeof(ixDPM_TABLE_271[0]), 0, 0 },
+	{ "ixDPM_TABLE_272", REG_SMC, 0x33718, &ixDPM_TABLE_272[0], sizeof(ixDPM_TABLE_272)/sizeof(ixDPM_TABLE_272[0]), 0, 0 },
+	{ "ixDPM_TABLE_273", REG_SMC, 0x3371c, &ixDPM_TABLE_273[0], sizeof(ixDPM_TABLE_273)/sizeof(ixDPM_TABLE_273[0]), 0, 0 },
+	{ "ixDPM_TABLE_274", REG_SMC, 0x33720, &ixDPM_TABLE_274[0], sizeof(ixDPM_TABLE_274)/sizeof(ixDPM_TABLE_274[0]), 0, 0 },
+	{ "ixDPM_TABLE_275", REG_SMC, 0x33724, &ixDPM_TABLE_275[0], sizeof(ixDPM_TABLE_275)/sizeof(ixDPM_TABLE_275[0]), 0, 0 },
+	{ "ixDPM_TABLE_276", REG_SMC, 0x33728, &ixDPM_TABLE_276[0], sizeof(ixDPM_TABLE_276)/sizeof(ixDPM_TABLE_276[0]), 0, 0 },
+	{ "ixDPM_TABLE_277", REG_SMC, 0x3372c, &ixDPM_TABLE_277[0], sizeof(ixDPM_TABLE_277)/sizeof(ixDPM_TABLE_277[0]), 0, 0 },
+	{ "ixDPM_TABLE_278", REG_SMC, 0x33730, &ixDPM_TABLE_278[0], sizeof(ixDPM_TABLE_278)/sizeof(ixDPM_TABLE_278[0]), 0, 0 },
+	{ "ixDPM_TABLE_279", REG_SMC, 0x33734, &ixDPM_TABLE_279[0], sizeof(ixDPM_TABLE_279)/sizeof(ixDPM_TABLE_279[0]), 0, 0 },
+	{ "ixDPM_TABLE_280", REG_SMC, 0x33738, &ixDPM_TABLE_280[0], sizeof(ixDPM_TABLE_280)/sizeof(ixDPM_TABLE_280[0]), 0, 0 },
+	{ "ixDPM_TABLE_281", REG_SMC, 0x3373c, &ixDPM_TABLE_281[0], sizeof(ixDPM_TABLE_281)/sizeof(ixDPM_TABLE_281[0]), 0, 0 },
+	{ "ixDPM_TABLE_282", REG_SMC, 0x33740, &ixDPM_TABLE_282[0], sizeof(ixDPM_TABLE_282)/sizeof(ixDPM_TABLE_282[0]), 0, 0 },
+	{ "ixDPM_TABLE_283", REG_SMC, 0x33744, &ixDPM_TABLE_283[0], sizeof(ixDPM_TABLE_283)/sizeof(ixDPM_TABLE_283[0]), 0, 0 },
+	{ "ixDPM_TABLE_284", REG_SMC, 0x33748, &ixDPM_TABLE_284[0], sizeof(ixDPM_TABLE_284)/sizeof(ixDPM_TABLE_284[0]), 0, 0 },
+	{ "ixDPM_TABLE_285", REG_SMC, 0x3374c, &ixDPM_TABLE_285[0], sizeof(ixDPM_TABLE_285)/sizeof(ixDPM_TABLE_285[0]), 0, 0 },
+	{ "ixDPM_TABLE_286", REG_SMC, 0x33750, &ixDPM_TABLE_286[0], sizeof(ixDPM_TABLE_286)/sizeof(ixDPM_TABLE_286[0]), 0, 0 },
+	{ "ixDPM_TABLE_287", REG_SMC, 0x33754, &ixDPM_TABLE_287[0], sizeof(ixDPM_TABLE_287)/sizeof(ixDPM_TABLE_287[0]), 0, 0 },
+	{ "ixDPM_TABLE_288", REG_SMC, 0x33758, &ixDPM_TABLE_288[0], sizeof(ixDPM_TABLE_288)/sizeof(ixDPM_TABLE_288[0]), 0, 0 },
+	{ "ixDPM_TABLE_289", REG_SMC, 0x3375c, &ixDPM_TABLE_289[0], sizeof(ixDPM_TABLE_289)/sizeof(ixDPM_TABLE_289[0]), 0, 0 },
+	{ "ixDPM_TABLE_290", REG_SMC, 0x33760, &ixDPM_TABLE_290[0], sizeof(ixDPM_TABLE_290)/sizeof(ixDPM_TABLE_290[0]), 0, 0 },
+	{ "ixDPM_TABLE_291", REG_SMC, 0x33764, &ixDPM_TABLE_291[0], sizeof(ixDPM_TABLE_291)/sizeof(ixDPM_TABLE_291[0]), 0, 0 },
+	{ "ixDPM_TABLE_292", REG_SMC, 0x33768, &ixDPM_TABLE_292[0], sizeof(ixDPM_TABLE_292)/sizeof(ixDPM_TABLE_292[0]), 0, 0 },
+	{ "ixDPM_TABLE_293", REG_SMC, 0x3376c, &ixDPM_TABLE_293[0], sizeof(ixDPM_TABLE_293)/sizeof(ixDPM_TABLE_293[0]), 0, 0 },
+	{ "ixDPM_TABLE_294", REG_SMC, 0x33770, &ixDPM_TABLE_294[0], sizeof(ixDPM_TABLE_294)/sizeof(ixDPM_TABLE_294[0]), 0, 0 },
+	{ "ixDPM_TABLE_295", REG_SMC, 0x33774, &ixDPM_TABLE_295[0], sizeof(ixDPM_TABLE_295)/sizeof(ixDPM_TABLE_295[0]), 0, 0 },
+	{ "ixDPM_TABLE_296", REG_SMC, 0x33778, &ixDPM_TABLE_296[0], sizeof(ixDPM_TABLE_296)/sizeof(ixDPM_TABLE_296[0]), 0, 0 },
+	{ "ixDPM_TABLE_297", REG_SMC, 0x3377c, &ixDPM_TABLE_297[0], sizeof(ixDPM_TABLE_297)/sizeof(ixDPM_TABLE_297[0]), 0, 0 },
+	{ "ixDPM_TABLE_298", REG_SMC, 0x33780, &ixDPM_TABLE_298[0], sizeof(ixDPM_TABLE_298)/sizeof(ixDPM_TABLE_298[0]), 0, 0 },
+	{ "ixDPM_TABLE_299", REG_SMC, 0x33784, &ixDPM_TABLE_299[0], sizeof(ixDPM_TABLE_299)/sizeof(ixDPM_TABLE_299[0]), 0, 0 },
+	{ "ixDPM_TABLE_300", REG_SMC, 0x33788, &ixDPM_TABLE_300[0], sizeof(ixDPM_TABLE_300)/sizeof(ixDPM_TABLE_300[0]), 0, 0 },
+	{ "ixDPM_TABLE_301", REG_SMC, 0x3378c, &ixDPM_TABLE_301[0], sizeof(ixDPM_TABLE_301)/sizeof(ixDPM_TABLE_301[0]), 0, 0 },
+	{ "ixDPM_TABLE_302", REG_SMC, 0x33790, &ixDPM_TABLE_302[0], sizeof(ixDPM_TABLE_302)/sizeof(ixDPM_TABLE_302[0]), 0, 0 },
+	{ "ixDPM_TABLE_303", REG_SMC, 0x33794, &ixDPM_TABLE_303[0], sizeof(ixDPM_TABLE_303)/sizeof(ixDPM_TABLE_303[0]), 0, 0 },
+	{ "ixDPM_TABLE_304", REG_SMC, 0x33798, &ixDPM_TABLE_304[0], sizeof(ixDPM_TABLE_304)/sizeof(ixDPM_TABLE_304[0]), 0, 0 },
+	{ "ixDPM_TABLE_305", REG_SMC, 0x3379c, &ixDPM_TABLE_305[0], sizeof(ixDPM_TABLE_305)/sizeof(ixDPM_TABLE_305[0]), 0, 0 },
+	{ "ixDPM_TABLE_306", REG_SMC, 0x337a0, &ixDPM_TABLE_306[0], sizeof(ixDPM_TABLE_306)/sizeof(ixDPM_TABLE_306[0]), 0, 0 },
+	{ "ixDPM_TABLE_307", REG_SMC, 0x337a4, &ixDPM_TABLE_307[0], sizeof(ixDPM_TABLE_307)/sizeof(ixDPM_TABLE_307[0]), 0, 0 },
+	{ "ixDPM_TABLE_308", REG_SMC, 0x337a8, &ixDPM_TABLE_308[0], sizeof(ixDPM_TABLE_308)/sizeof(ixDPM_TABLE_308[0]), 0, 0 },
+	{ "ixDPM_TABLE_309", REG_SMC, 0x337ac, &ixDPM_TABLE_309[0], sizeof(ixDPM_TABLE_309)/sizeof(ixDPM_TABLE_309[0]), 0, 0 },
+	{ "ixDPM_TABLE_310", REG_SMC, 0x337b0, &ixDPM_TABLE_310[0], sizeof(ixDPM_TABLE_310)/sizeof(ixDPM_TABLE_310[0]), 0, 0 },
+	{ "ixDPM_TABLE_311", REG_SMC, 0x337b4, &ixDPM_TABLE_311[0], sizeof(ixDPM_TABLE_311)/sizeof(ixDPM_TABLE_311[0]), 0, 0 },
+	{ "ixDPM_TABLE_312", REG_SMC, 0x337b8, &ixDPM_TABLE_312[0], sizeof(ixDPM_TABLE_312)/sizeof(ixDPM_TABLE_312[0]), 0, 0 },
+	{ "ixDPM_TABLE_313", REG_SMC, 0x337bc, &ixDPM_TABLE_313[0], sizeof(ixDPM_TABLE_313)/sizeof(ixDPM_TABLE_313[0]), 0, 0 },
+	{ "ixDPM_TABLE_314", REG_SMC, 0x337c0, &ixDPM_TABLE_314[0], sizeof(ixDPM_TABLE_314)/sizeof(ixDPM_TABLE_314[0]), 0, 0 },
+	{ "ixDPM_TABLE_315", REG_SMC, 0x337c4, &ixDPM_TABLE_315[0], sizeof(ixDPM_TABLE_315)/sizeof(ixDPM_TABLE_315[0]), 0, 0 },
+	{ "ixDPM_TABLE_316", REG_SMC, 0x337c8, &ixDPM_TABLE_316[0], sizeof(ixDPM_TABLE_316)/sizeof(ixDPM_TABLE_316[0]), 0, 0 },
+	{ "ixDPM_TABLE_317", REG_SMC, 0x337cc, &ixDPM_TABLE_317[0], sizeof(ixDPM_TABLE_317)/sizeof(ixDPM_TABLE_317[0]), 0, 0 },
+	{ "ixDPM_TABLE_318", REG_SMC, 0x337d0, &ixDPM_TABLE_318[0], sizeof(ixDPM_TABLE_318)/sizeof(ixDPM_TABLE_318[0]), 0, 0 },
+	{ "ixDPM_TABLE_319", REG_SMC, 0x337d4, &ixDPM_TABLE_319[0], sizeof(ixDPM_TABLE_319)/sizeof(ixDPM_TABLE_319[0]), 0, 0 },
+	{ "ixDPM_TABLE_320", REG_SMC, 0x337d8, &ixDPM_TABLE_320[0], sizeof(ixDPM_TABLE_320)/sizeof(ixDPM_TABLE_320[0]), 0, 0 },
+	{ "ixDPM_TABLE_321", REG_SMC, 0x337dc, &ixDPM_TABLE_321[0], sizeof(ixDPM_TABLE_321)/sizeof(ixDPM_TABLE_321[0]), 0, 0 },
+	{ "ixDPM_TABLE_322", REG_SMC, 0x337e0, &ixDPM_TABLE_322[0], sizeof(ixDPM_TABLE_322)/sizeof(ixDPM_TABLE_322[0]), 0, 0 },
+	{ "ixDPM_TABLE_323", REG_SMC, 0x337e4, &ixDPM_TABLE_323[0], sizeof(ixDPM_TABLE_323)/sizeof(ixDPM_TABLE_323[0]), 0, 0 },
+	{ "ixDPM_TABLE_324", REG_SMC, 0x337e8, &ixDPM_TABLE_324[0], sizeof(ixDPM_TABLE_324)/sizeof(ixDPM_TABLE_324[0]), 0, 0 },
+	{ "ixDPM_TABLE_325", REG_SMC, 0x337ec, &ixDPM_TABLE_325[0], sizeof(ixDPM_TABLE_325)/sizeof(ixDPM_TABLE_325[0]), 0, 0 },
+	{ "ixDPM_TABLE_326", REG_SMC, 0x337f0, &ixDPM_TABLE_326[0], sizeof(ixDPM_TABLE_326)/sizeof(ixDPM_TABLE_326[0]), 0, 0 },
+	{ "ixDPM_TABLE_327", REG_SMC, 0x337f4, &ixDPM_TABLE_327[0], sizeof(ixDPM_TABLE_327)/sizeof(ixDPM_TABLE_327[0]), 0, 0 },
+	{ "ixDPM_TABLE_328", REG_SMC, 0x337f8, &ixDPM_TABLE_328[0], sizeof(ixDPM_TABLE_328)/sizeof(ixDPM_TABLE_328[0]), 0, 0 },
+	{ "ixDPM_TABLE_329", REG_SMC, 0x337fc, &ixDPM_TABLE_329[0], sizeof(ixDPM_TABLE_329)/sizeof(ixDPM_TABLE_329[0]), 0, 0 },
+	{ "ixDPM_TABLE_330", REG_SMC, 0x33800, &ixDPM_TABLE_330[0], sizeof(ixDPM_TABLE_330)/sizeof(ixDPM_TABLE_330[0]), 0, 0 },
+	{ "ixDPM_TABLE_331", REG_SMC, 0x33804, &ixDPM_TABLE_331[0], sizeof(ixDPM_TABLE_331)/sizeof(ixDPM_TABLE_331[0]), 0, 0 },
+	{ "ixDPM_TABLE_332", REG_SMC, 0x33808, &ixDPM_TABLE_332[0], sizeof(ixDPM_TABLE_332)/sizeof(ixDPM_TABLE_332[0]), 0, 0 },
+	{ "ixDPM_TABLE_333", REG_SMC, 0x3380c, &ixDPM_TABLE_333[0], sizeof(ixDPM_TABLE_333)/sizeof(ixDPM_TABLE_333[0]), 0, 0 },
+	{ "ixDPM_TABLE_334", REG_SMC, 0x33810, &ixDPM_TABLE_334[0], sizeof(ixDPM_TABLE_334)/sizeof(ixDPM_TABLE_334[0]), 0, 0 },
+	{ "ixDPM_TABLE_335", REG_SMC, 0x33814, &ixDPM_TABLE_335[0], sizeof(ixDPM_TABLE_335)/sizeof(ixDPM_TABLE_335[0]), 0, 0 },
+	{ "ixDPM_TABLE_336", REG_SMC, 0x33818, &ixDPM_TABLE_336[0], sizeof(ixDPM_TABLE_336)/sizeof(ixDPM_TABLE_336[0]), 0, 0 },
+	{ "ixDPM_TABLE_337", REG_SMC, 0x3381c, &ixDPM_TABLE_337[0], sizeof(ixDPM_TABLE_337)/sizeof(ixDPM_TABLE_337[0]), 0, 0 },
+	{ "ixDPM_TABLE_338", REG_SMC, 0x33820, &ixDPM_TABLE_338[0], sizeof(ixDPM_TABLE_338)/sizeof(ixDPM_TABLE_338[0]), 0, 0 },
+	{ "ixDPM_TABLE_339", REG_SMC, 0x33824, &ixDPM_TABLE_339[0], sizeof(ixDPM_TABLE_339)/sizeof(ixDPM_TABLE_339[0]), 0, 0 },
+	{ "ixDPM_TABLE_340", REG_SMC, 0x33828, &ixDPM_TABLE_340[0], sizeof(ixDPM_TABLE_340)/sizeof(ixDPM_TABLE_340[0]), 0, 0 },
+	{ "ixDPM_TABLE_341", REG_SMC, 0x3382c, &ixDPM_TABLE_341[0], sizeof(ixDPM_TABLE_341)/sizeof(ixDPM_TABLE_341[0]), 0, 0 },
+	{ "ixDPM_TABLE_342", REG_SMC, 0x33830, &ixDPM_TABLE_342[0], sizeof(ixDPM_TABLE_342)/sizeof(ixDPM_TABLE_342[0]), 0, 0 },
+	{ "ixDPM_TABLE_343", REG_SMC, 0x33834, &ixDPM_TABLE_343[0], sizeof(ixDPM_TABLE_343)/sizeof(ixDPM_TABLE_343[0]), 0, 0 },
+	{ "ixDPM_TABLE_344", REG_SMC, 0x33838, &ixDPM_TABLE_344[0], sizeof(ixDPM_TABLE_344)/sizeof(ixDPM_TABLE_344[0]), 0, 0 },
+	{ "ixDPM_TABLE_345", REG_SMC, 0x3383c, &ixDPM_TABLE_345[0], sizeof(ixDPM_TABLE_345)/sizeof(ixDPM_TABLE_345[0]), 0, 0 },
+	{ "ixDPM_TABLE_346", REG_SMC, 0x33840, &ixDPM_TABLE_346[0], sizeof(ixDPM_TABLE_346)/sizeof(ixDPM_TABLE_346[0]), 0, 0 },
+	{ "ixDPM_TABLE_347", REG_SMC, 0x33844, &ixDPM_TABLE_347[0], sizeof(ixDPM_TABLE_347)/sizeof(ixDPM_TABLE_347[0]), 0, 0 },
+	{ "ixDPM_TABLE_348", REG_SMC, 0x33848, &ixDPM_TABLE_348[0], sizeof(ixDPM_TABLE_348)/sizeof(ixDPM_TABLE_348[0]), 0, 0 },
+	{ "ixDPM_TABLE_349", REG_SMC, 0x3384c, &ixDPM_TABLE_349[0], sizeof(ixDPM_TABLE_349)/sizeof(ixDPM_TABLE_349[0]), 0, 0 },
+	{ "ixDPM_TABLE_350", REG_SMC, 0x33850, &ixDPM_TABLE_350[0], sizeof(ixDPM_TABLE_350)/sizeof(ixDPM_TABLE_350[0]), 0, 0 },
+	{ "ixDPM_TABLE_351", REG_SMC, 0x33854, &ixDPM_TABLE_351[0], sizeof(ixDPM_TABLE_351)/sizeof(ixDPM_TABLE_351[0]), 0, 0 },
+	{ "ixDPM_TABLE_352", REG_SMC, 0x33858, &ixDPM_TABLE_352[0], sizeof(ixDPM_TABLE_352)/sizeof(ixDPM_TABLE_352[0]), 0, 0 },
+	{ "ixDPM_TABLE_353", REG_SMC, 0x3385c, &ixDPM_TABLE_353[0], sizeof(ixDPM_TABLE_353)/sizeof(ixDPM_TABLE_353[0]), 0, 0 },
+	{ "ixDPM_TABLE_354", REG_SMC, 0x33860, &ixDPM_TABLE_354[0], sizeof(ixDPM_TABLE_354)/sizeof(ixDPM_TABLE_354[0]), 0, 0 },
+	{ "ixDPM_TABLE_355", REG_SMC, 0x33864, &ixDPM_TABLE_355[0], sizeof(ixDPM_TABLE_355)/sizeof(ixDPM_TABLE_355[0]), 0, 0 },
+	{ "ixDPM_TABLE_356", REG_SMC, 0x33868, &ixDPM_TABLE_356[0], sizeof(ixDPM_TABLE_356)/sizeof(ixDPM_TABLE_356[0]), 0, 0 },
+	{ "ixDPM_TABLE_357", REG_SMC, 0x3386c, &ixDPM_TABLE_357[0], sizeof(ixDPM_TABLE_357)/sizeof(ixDPM_TABLE_357[0]), 0, 0 },
+	{ "ixDPM_TABLE_358", REG_SMC, 0x33870, &ixDPM_TABLE_358[0], sizeof(ixDPM_TABLE_358)/sizeof(ixDPM_TABLE_358[0]), 0, 0 },
+	{ "ixDPM_TABLE_359", REG_SMC, 0x33874, &ixDPM_TABLE_359[0], sizeof(ixDPM_TABLE_359)/sizeof(ixDPM_TABLE_359[0]), 0, 0 },
+	{ "ixDPM_TABLE_360", REG_SMC, 0x33878, &ixDPM_TABLE_360[0], sizeof(ixDPM_TABLE_360)/sizeof(ixDPM_TABLE_360[0]), 0, 0 },
+	{ "ixDPM_TABLE_361", REG_SMC, 0x3387c, &ixDPM_TABLE_361[0], sizeof(ixDPM_TABLE_361)/sizeof(ixDPM_TABLE_361[0]), 0, 0 },
+	{ "ixDPM_TABLE_362", REG_SMC, 0x33880, &ixDPM_TABLE_362[0], sizeof(ixDPM_TABLE_362)/sizeof(ixDPM_TABLE_362[0]), 0, 0 },
+	{ "ixDPM_TABLE_363", REG_SMC, 0x33884, &ixDPM_TABLE_363[0], sizeof(ixDPM_TABLE_363)/sizeof(ixDPM_TABLE_363[0]), 0, 0 },
+	{ "ixDPM_TABLE_364", REG_SMC, 0x33888, &ixDPM_TABLE_364[0], sizeof(ixDPM_TABLE_364)/sizeof(ixDPM_TABLE_364[0]), 0, 0 },
+	{ "ixDPM_TABLE_365", REG_SMC, 0x3388c, &ixDPM_TABLE_365[0], sizeof(ixDPM_TABLE_365)/sizeof(ixDPM_TABLE_365[0]), 0, 0 },
+	{ "ixDPM_TABLE_366", REG_SMC, 0x33890, &ixDPM_TABLE_366[0], sizeof(ixDPM_TABLE_366)/sizeof(ixDPM_TABLE_366[0]), 0, 0 },
+	{ "ixDPM_TABLE_367", REG_SMC, 0x33894, &ixDPM_TABLE_367[0], sizeof(ixDPM_TABLE_367)/sizeof(ixDPM_TABLE_367[0]), 0, 0 },
+	{ "ixDPM_TABLE_368", REG_SMC, 0x33898, &ixDPM_TABLE_368[0], sizeof(ixDPM_TABLE_368)/sizeof(ixDPM_TABLE_368[0]), 0, 0 },
+	{ "ixDPM_TABLE_369", REG_SMC, 0x3389c, &ixDPM_TABLE_369[0], sizeof(ixDPM_TABLE_369)/sizeof(ixDPM_TABLE_369[0]), 0, 0 },
+	{ "ixDPM_TABLE_370", REG_SMC, 0x338a0, &ixDPM_TABLE_370[0], sizeof(ixDPM_TABLE_370)/sizeof(ixDPM_TABLE_370[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_1", REG_SMC, 0x338c8, &ixSOFT_REGISTERS_TABLE_1[0], sizeof(ixSOFT_REGISTERS_TABLE_1)/sizeof(ixSOFT_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_2", REG_SMC, 0x338cc, &ixSOFT_REGISTERS_TABLE_2[0], sizeof(ixSOFT_REGISTERS_TABLE_2)/sizeof(ixSOFT_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_3", REG_SMC, 0x338d0, &ixSOFT_REGISTERS_TABLE_3[0], sizeof(ixSOFT_REGISTERS_TABLE_3)/sizeof(ixSOFT_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_4", REG_SMC, 0x338d4, &ixSOFT_REGISTERS_TABLE_4[0], sizeof(ixSOFT_REGISTERS_TABLE_4)/sizeof(ixSOFT_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_5", REG_SMC, 0x338d8, &ixSOFT_REGISTERS_TABLE_5[0], sizeof(ixSOFT_REGISTERS_TABLE_5)/sizeof(ixSOFT_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_6", REG_SMC, 0x338dc, &ixSOFT_REGISTERS_TABLE_6[0], sizeof(ixSOFT_REGISTERS_TABLE_6)/sizeof(ixSOFT_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_7", REG_SMC, 0x338e0, &ixSOFT_REGISTERS_TABLE_7[0], sizeof(ixSOFT_REGISTERS_TABLE_7)/sizeof(ixSOFT_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_8", REG_SMC, 0x338e4, &ixSOFT_REGISTERS_TABLE_8[0], sizeof(ixSOFT_REGISTERS_TABLE_8)/sizeof(ixSOFT_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_9", REG_SMC, 0x338e8, &ixSOFT_REGISTERS_TABLE_9[0], sizeof(ixSOFT_REGISTERS_TABLE_9)/sizeof(ixSOFT_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_10", REG_SMC, 0x338ec, &ixSOFT_REGISTERS_TABLE_10[0], sizeof(ixSOFT_REGISTERS_TABLE_10)/sizeof(ixSOFT_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_11", REG_SMC, 0x338f0, &ixSOFT_REGISTERS_TABLE_11[0], sizeof(ixSOFT_REGISTERS_TABLE_11)/sizeof(ixSOFT_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_12", REG_SMC, 0x338f4, &ixSOFT_REGISTERS_TABLE_12[0], sizeof(ixSOFT_REGISTERS_TABLE_12)/sizeof(ixSOFT_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_13", REG_SMC, 0x338f8, &ixSOFT_REGISTERS_TABLE_13[0], sizeof(ixSOFT_REGISTERS_TABLE_13)/sizeof(ixSOFT_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_14", REG_SMC, 0x338fc, &ixSOFT_REGISTERS_TABLE_14[0], sizeof(ixSOFT_REGISTERS_TABLE_14)/sizeof(ixSOFT_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_15", REG_SMC, 0x33900, &ixSOFT_REGISTERS_TABLE_15[0], sizeof(ixSOFT_REGISTERS_TABLE_15)/sizeof(ixSOFT_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_16", REG_SMC, 0x33904, &ixSOFT_REGISTERS_TABLE_16[0], sizeof(ixSOFT_REGISTERS_TABLE_16)/sizeof(ixSOFT_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_17", REG_SMC, 0x33908, &ixSOFT_REGISTERS_TABLE_17[0], sizeof(ixSOFT_REGISTERS_TABLE_17)/sizeof(ixSOFT_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_18", REG_SMC, 0x3390c, &ixSOFT_REGISTERS_TABLE_18[0], sizeof(ixSOFT_REGISTERS_TABLE_18)/sizeof(ixSOFT_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_19", REG_SMC, 0x33910, &ixSOFT_REGISTERS_TABLE_19[0], sizeof(ixSOFT_REGISTERS_TABLE_19)/sizeof(ixSOFT_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_20", REG_SMC, 0x33914, &ixSOFT_REGISTERS_TABLE_20[0], sizeof(ixSOFT_REGISTERS_TABLE_20)/sizeof(ixSOFT_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_21", REG_SMC, 0x33918, &ixSOFT_REGISTERS_TABLE_21[0], sizeof(ixSOFT_REGISTERS_TABLE_21)/sizeof(ixSOFT_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_22", REG_SMC, 0x3391c, &ixSOFT_REGISTERS_TABLE_22[0], sizeof(ixSOFT_REGISTERS_TABLE_22)/sizeof(ixSOFT_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_23", REG_SMC, 0x33920, &ixSOFT_REGISTERS_TABLE_23[0], sizeof(ixSOFT_REGISTERS_TABLE_23)/sizeof(ixSOFT_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_24", REG_SMC, 0x33924, &ixSOFT_REGISTERS_TABLE_24[0], sizeof(ixSOFT_REGISTERS_TABLE_24)/sizeof(ixSOFT_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_25", REG_SMC, 0x33928, &ixSOFT_REGISTERS_TABLE_25[0], sizeof(ixSOFT_REGISTERS_TABLE_25)/sizeof(ixSOFT_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_26", REG_SMC, 0x3392c, &ixSOFT_REGISTERS_TABLE_26[0], sizeof(ixSOFT_REGISTERS_TABLE_26)/sizeof(ixSOFT_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_27", REG_SMC, 0x33930, &ixSOFT_REGISTERS_TABLE_27[0], sizeof(ixSOFT_REGISTERS_TABLE_27)/sizeof(ixSOFT_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_28", REG_SMC, 0x33934, &ixSOFT_REGISTERS_TABLE_28[0], sizeof(ixSOFT_REGISTERS_TABLE_28)/sizeof(ixSOFT_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_29", REG_SMC, 0x33938, &ixSOFT_REGISTERS_TABLE_29[0], sizeof(ixSOFT_REGISTERS_TABLE_29)/sizeof(ixSOFT_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixPM_FUSES_1", REG_SMC, 0x3394c, &ixPM_FUSES_1[0], sizeof(ixPM_FUSES_1)/sizeof(ixPM_FUSES_1[0]), 0, 0 },
+	{ "ixPM_FUSES_2", REG_SMC, 0x33950, &ixPM_FUSES_2[0], sizeof(ixPM_FUSES_2)/sizeof(ixPM_FUSES_2[0]), 0, 0 },
+	{ "ixPM_FUSES_3", REG_SMC, 0x33954, &ixPM_FUSES_3[0], sizeof(ixPM_FUSES_3)/sizeof(ixPM_FUSES_3[0]), 0, 0 },
+	{ "ixPM_FUSES_4", REG_SMC, 0x33958, &ixPM_FUSES_4[0], sizeof(ixPM_FUSES_4)/sizeof(ixPM_FUSES_4[0]), 0, 0 },
+	{ "ixPM_FUSES_5", REG_SMC, 0x3395c, &ixPM_FUSES_5[0], sizeof(ixPM_FUSES_5)/sizeof(ixPM_FUSES_5[0]), 0, 0 },
+	{ "ixPM_FUSES_6", REG_SMC, 0x33960, &ixPM_FUSES_6[0], sizeof(ixPM_FUSES_6)/sizeof(ixPM_FUSES_6[0]), 0, 0 },
+	{ "ixPM_FUSES_7", REG_SMC, 0x33964, &ixPM_FUSES_7[0], sizeof(ixPM_FUSES_7)/sizeof(ixPM_FUSES_7[0]), 0, 0 },
+	{ "ixPM_FUSES_8", REG_SMC, 0x33968, &ixPM_FUSES_8[0], sizeof(ixPM_FUSES_8)/sizeof(ixPM_FUSES_8[0]), 0, 0 },
+	{ "ixPM_FUSES_9", REG_SMC, 0x3396c, &ixPM_FUSES_9[0], sizeof(ixPM_FUSES_9)/sizeof(ixPM_FUSES_9[0]), 0, 0 },
+	{ "ixPM_FUSES_10", REG_SMC, 0x33970, &ixPM_FUSES_10[0], sizeof(ixPM_FUSES_10)/sizeof(ixPM_FUSES_10[0]), 0, 0 },
+	{ "ixPM_FUSES_11", REG_SMC, 0x33974, &ixPM_FUSES_11[0], sizeof(ixPM_FUSES_11)/sizeof(ixPM_FUSES_11[0]), 0, 0 },
+	{ "ixPM_FUSES_12", REG_SMC, 0x33978, &ixPM_FUSES_12[0], sizeof(ixPM_FUSES_12)/sizeof(ixPM_FUSES_12[0]), 0, 0 },
+	{ "ixPM_FUSES_13", REG_SMC, 0x3397c, &ixPM_FUSES_13[0], sizeof(ixPM_FUSES_13)/sizeof(ixPM_FUSES_13[0]), 0, 0 },
+	{ "ixPM_FUSES_14", REG_SMC, 0x33980, &ixPM_FUSES_14[0], sizeof(ixPM_FUSES_14)/sizeof(ixPM_FUSES_14[0]), 0, 0 },
+	{ "ixPM_FUSES_15", REG_SMC, 0x33984, &ixPM_FUSES_15[0], sizeof(ixPM_FUSES_15)/sizeof(ixPM_FUSES_15[0]), 0, 0 },
+	{ "ixPM_FUSES_16", REG_SMC, 0x33988, &ixPM_FUSES_16[0], sizeof(ixPM_FUSES_16)/sizeof(ixPM_FUSES_16[0]), 0, 0 },
+	{ "ixPM_FUSES_17", REG_SMC, 0x3398c, &ixPM_FUSES_17[0], sizeof(ixPM_FUSES_17)/sizeof(ixPM_FUSES_17[0]), 0, 0 },
+	{ "ixPM_FUSES_18", REG_SMC, 0x33990, &ixPM_FUSES_18[0], sizeof(ixPM_FUSES_18)/sizeof(ixPM_FUSES_18[0]), 0, 0 },
+	{ "ixPM_FUSES_19", REG_SMC, 0x33994, &ixPM_FUSES_19[0], sizeof(ixPM_FUSES_19)/sizeof(ixPM_FUSES_19[0]), 0, 0 },
+	{ "ixPM_FUSES_20", REG_SMC, 0x33998, &ixPM_FUSES_20[0], sizeof(ixPM_FUSES_20)/sizeof(ixPM_FUSES_20[0]), 0, 0 },
+	{ "ixPM_FUSES_21", REG_SMC, 0x3399c, &ixPM_FUSES_21[0], sizeof(ixPM_FUSES_21)/sizeof(ixPM_FUSES_21[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_0", REG_SMC, 0x33e00, &ixSMU_PM_STATUS_0[0], sizeof(ixSMU_PM_STATUS_0)/sizeof(ixSMU_PM_STATUS_0[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_1", REG_SMC, 0x33e04, &ixSMU_PM_STATUS_1[0], sizeof(ixSMU_PM_STATUS_1)/sizeof(ixSMU_PM_STATUS_1[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_2", REG_SMC, 0x33e08, &ixSMU_PM_STATUS_2[0], sizeof(ixSMU_PM_STATUS_2)/sizeof(ixSMU_PM_STATUS_2[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_3", REG_SMC, 0x33e0c, &ixSMU_PM_STATUS_3[0], sizeof(ixSMU_PM_STATUS_3)/sizeof(ixSMU_PM_STATUS_3[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_4", REG_SMC, 0x33e10, &ixSMU_PM_STATUS_4[0], sizeof(ixSMU_PM_STATUS_4)/sizeof(ixSMU_PM_STATUS_4[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_5", REG_SMC, 0x33e14, &ixSMU_PM_STATUS_5[0], sizeof(ixSMU_PM_STATUS_5)/sizeof(ixSMU_PM_STATUS_5[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_6", REG_SMC, 0x33e18, &ixSMU_PM_STATUS_6[0], sizeof(ixSMU_PM_STATUS_6)/sizeof(ixSMU_PM_STATUS_6[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_7", REG_SMC, 0x33e1c, &ixSMU_PM_STATUS_7[0], sizeof(ixSMU_PM_STATUS_7)/sizeof(ixSMU_PM_STATUS_7[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_8", REG_SMC, 0x33e20, &ixSMU_PM_STATUS_8[0], sizeof(ixSMU_PM_STATUS_8)/sizeof(ixSMU_PM_STATUS_8[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_9", REG_SMC, 0x33e24, &ixSMU_PM_STATUS_9[0], sizeof(ixSMU_PM_STATUS_9)/sizeof(ixSMU_PM_STATUS_9[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_10", REG_SMC, 0x33e28, &ixSMU_PM_STATUS_10[0], sizeof(ixSMU_PM_STATUS_10)/sizeof(ixSMU_PM_STATUS_10[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_11", REG_SMC, 0x33e2c, &ixSMU_PM_STATUS_11[0], sizeof(ixSMU_PM_STATUS_11)/sizeof(ixSMU_PM_STATUS_11[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_12", REG_SMC, 0x33e30, &ixSMU_PM_STATUS_12[0], sizeof(ixSMU_PM_STATUS_12)/sizeof(ixSMU_PM_STATUS_12[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_13", REG_SMC, 0x33e34, &ixSMU_PM_STATUS_13[0], sizeof(ixSMU_PM_STATUS_13)/sizeof(ixSMU_PM_STATUS_13[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_14", REG_SMC, 0x33e38, &ixSMU_PM_STATUS_14[0], sizeof(ixSMU_PM_STATUS_14)/sizeof(ixSMU_PM_STATUS_14[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_15", REG_SMC, 0x33e3c, &ixSMU_PM_STATUS_15[0], sizeof(ixSMU_PM_STATUS_15)/sizeof(ixSMU_PM_STATUS_15[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_16", REG_SMC, 0x33e40, &ixSMU_PM_STATUS_16[0], sizeof(ixSMU_PM_STATUS_16)/sizeof(ixSMU_PM_STATUS_16[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_17", REG_SMC, 0x33e44, &ixSMU_PM_STATUS_17[0], sizeof(ixSMU_PM_STATUS_17)/sizeof(ixSMU_PM_STATUS_17[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_18", REG_SMC, 0x33e48, &ixSMU_PM_STATUS_18[0], sizeof(ixSMU_PM_STATUS_18)/sizeof(ixSMU_PM_STATUS_18[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_19", REG_SMC, 0x33e4c, &ixSMU_PM_STATUS_19[0], sizeof(ixSMU_PM_STATUS_19)/sizeof(ixSMU_PM_STATUS_19[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_20", REG_SMC, 0x33e50, &ixSMU_PM_STATUS_20[0], sizeof(ixSMU_PM_STATUS_20)/sizeof(ixSMU_PM_STATUS_20[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_21", REG_SMC, 0x33e54, &ixSMU_PM_STATUS_21[0], sizeof(ixSMU_PM_STATUS_21)/sizeof(ixSMU_PM_STATUS_21[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_22", REG_SMC, 0x33e58, &ixSMU_PM_STATUS_22[0], sizeof(ixSMU_PM_STATUS_22)/sizeof(ixSMU_PM_STATUS_22[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_23", REG_SMC, 0x33e5c, &ixSMU_PM_STATUS_23[0], sizeof(ixSMU_PM_STATUS_23)/sizeof(ixSMU_PM_STATUS_23[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_24", REG_SMC, 0x33e60, &ixSMU_PM_STATUS_24[0], sizeof(ixSMU_PM_STATUS_24)/sizeof(ixSMU_PM_STATUS_24[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_25", REG_SMC, 0x33e64, &ixSMU_PM_STATUS_25[0], sizeof(ixSMU_PM_STATUS_25)/sizeof(ixSMU_PM_STATUS_25[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_26", REG_SMC, 0x33e68, &ixSMU_PM_STATUS_26[0], sizeof(ixSMU_PM_STATUS_26)/sizeof(ixSMU_PM_STATUS_26[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_27", REG_SMC, 0x33e6c, &ixSMU_PM_STATUS_27[0], sizeof(ixSMU_PM_STATUS_27)/sizeof(ixSMU_PM_STATUS_27[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_28", REG_SMC, 0x33e70, &ixSMU_PM_STATUS_28[0], sizeof(ixSMU_PM_STATUS_28)/sizeof(ixSMU_PM_STATUS_28[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_29", REG_SMC, 0x33e74, &ixSMU_PM_STATUS_29[0], sizeof(ixSMU_PM_STATUS_29)/sizeof(ixSMU_PM_STATUS_29[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_30", REG_SMC, 0x33e78, &ixSMU_PM_STATUS_30[0], sizeof(ixSMU_PM_STATUS_30)/sizeof(ixSMU_PM_STATUS_30[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_31", REG_SMC, 0x33e7c, &ixSMU_PM_STATUS_31[0], sizeof(ixSMU_PM_STATUS_31)/sizeof(ixSMU_PM_STATUS_31[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_32", REG_SMC, 0x33e80, &ixSMU_PM_STATUS_32[0], sizeof(ixSMU_PM_STATUS_32)/sizeof(ixSMU_PM_STATUS_32[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_33", REG_SMC, 0x33e84, &ixSMU_PM_STATUS_33[0], sizeof(ixSMU_PM_STATUS_33)/sizeof(ixSMU_PM_STATUS_33[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_34", REG_SMC, 0x33e88, &ixSMU_PM_STATUS_34[0], sizeof(ixSMU_PM_STATUS_34)/sizeof(ixSMU_PM_STATUS_34[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_35", REG_SMC, 0x33e8c, &ixSMU_PM_STATUS_35[0], sizeof(ixSMU_PM_STATUS_35)/sizeof(ixSMU_PM_STATUS_35[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_36", REG_SMC, 0x33e90, &ixSMU_PM_STATUS_36[0], sizeof(ixSMU_PM_STATUS_36)/sizeof(ixSMU_PM_STATUS_36[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_37", REG_SMC, 0x33e94, &ixSMU_PM_STATUS_37[0], sizeof(ixSMU_PM_STATUS_37)/sizeof(ixSMU_PM_STATUS_37[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_38", REG_SMC, 0x33e98, &ixSMU_PM_STATUS_38[0], sizeof(ixSMU_PM_STATUS_38)/sizeof(ixSMU_PM_STATUS_38[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_39", REG_SMC, 0x33e9c, &ixSMU_PM_STATUS_39[0], sizeof(ixSMU_PM_STATUS_39)/sizeof(ixSMU_PM_STATUS_39[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_40", REG_SMC, 0x33ea0, &ixSMU_PM_STATUS_40[0], sizeof(ixSMU_PM_STATUS_40)/sizeof(ixSMU_PM_STATUS_40[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_41", REG_SMC, 0x33ea4, &ixSMU_PM_STATUS_41[0], sizeof(ixSMU_PM_STATUS_41)/sizeof(ixSMU_PM_STATUS_41[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_42", REG_SMC, 0x33ea8, &ixSMU_PM_STATUS_42[0], sizeof(ixSMU_PM_STATUS_42)/sizeof(ixSMU_PM_STATUS_42[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_43", REG_SMC, 0x33eac, &ixSMU_PM_STATUS_43[0], sizeof(ixSMU_PM_STATUS_43)/sizeof(ixSMU_PM_STATUS_43[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_44", REG_SMC, 0x33eb0, &ixSMU_PM_STATUS_44[0], sizeof(ixSMU_PM_STATUS_44)/sizeof(ixSMU_PM_STATUS_44[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_45", REG_SMC, 0x33eb4, &ixSMU_PM_STATUS_45[0], sizeof(ixSMU_PM_STATUS_45)/sizeof(ixSMU_PM_STATUS_45[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_46", REG_SMC, 0x33eb8, &ixSMU_PM_STATUS_46[0], sizeof(ixSMU_PM_STATUS_46)/sizeof(ixSMU_PM_STATUS_46[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_47", REG_SMC, 0x33ebc, &ixSMU_PM_STATUS_47[0], sizeof(ixSMU_PM_STATUS_47)/sizeof(ixSMU_PM_STATUS_47[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_48", REG_SMC, 0x33ec0, &ixSMU_PM_STATUS_48[0], sizeof(ixSMU_PM_STATUS_48)/sizeof(ixSMU_PM_STATUS_48[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_49", REG_SMC, 0x33ec4, &ixSMU_PM_STATUS_49[0], sizeof(ixSMU_PM_STATUS_49)/sizeof(ixSMU_PM_STATUS_49[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_50", REG_SMC, 0x33ec8, &ixSMU_PM_STATUS_50[0], sizeof(ixSMU_PM_STATUS_50)/sizeof(ixSMU_PM_STATUS_50[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_51", REG_SMC, 0x33ecc, &ixSMU_PM_STATUS_51[0], sizeof(ixSMU_PM_STATUS_51)/sizeof(ixSMU_PM_STATUS_51[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_52", REG_SMC, 0x33ed0, &ixSMU_PM_STATUS_52[0], sizeof(ixSMU_PM_STATUS_52)/sizeof(ixSMU_PM_STATUS_52[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_53", REG_SMC, 0x33ed4, &ixSMU_PM_STATUS_53[0], sizeof(ixSMU_PM_STATUS_53)/sizeof(ixSMU_PM_STATUS_53[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_54", REG_SMC, 0x33ed8, &ixSMU_PM_STATUS_54[0], sizeof(ixSMU_PM_STATUS_54)/sizeof(ixSMU_PM_STATUS_54[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_55", REG_SMC, 0x33edc, &ixSMU_PM_STATUS_55[0], sizeof(ixSMU_PM_STATUS_55)/sizeof(ixSMU_PM_STATUS_55[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_56", REG_SMC, 0x33ee0, &ixSMU_PM_STATUS_56[0], sizeof(ixSMU_PM_STATUS_56)/sizeof(ixSMU_PM_STATUS_56[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_57", REG_SMC, 0x33ee4, &ixSMU_PM_STATUS_57[0], sizeof(ixSMU_PM_STATUS_57)/sizeof(ixSMU_PM_STATUS_57[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_58", REG_SMC, 0x33ee8, &ixSMU_PM_STATUS_58[0], sizeof(ixSMU_PM_STATUS_58)/sizeof(ixSMU_PM_STATUS_58[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_59", REG_SMC, 0x33eec, &ixSMU_PM_STATUS_59[0], sizeof(ixSMU_PM_STATUS_59)/sizeof(ixSMU_PM_STATUS_59[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_60", REG_SMC, 0x33ef0, &ixSMU_PM_STATUS_60[0], sizeof(ixSMU_PM_STATUS_60)/sizeof(ixSMU_PM_STATUS_60[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_61", REG_SMC, 0x33ef4, &ixSMU_PM_STATUS_61[0], sizeof(ixSMU_PM_STATUS_61)/sizeof(ixSMU_PM_STATUS_61[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_62", REG_SMC, 0x33ef8, &ixSMU_PM_STATUS_62[0], sizeof(ixSMU_PM_STATUS_62)/sizeof(ixSMU_PM_STATUS_62[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_63", REG_SMC, 0x33efc, &ixSMU_PM_STATUS_63[0], sizeof(ixSMU_PM_STATUS_63)/sizeof(ixSMU_PM_STATUS_63[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_64", REG_SMC, 0x33f00, &ixSMU_PM_STATUS_64[0], sizeof(ixSMU_PM_STATUS_64)/sizeof(ixSMU_PM_STATUS_64[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_65", REG_SMC, 0x33f04, &ixSMU_PM_STATUS_65[0], sizeof(ixSMU_PM_STATUS_65)/sizeof(ixSMU_PM_STATUS_65[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_66", REG_SMC, 0x33f08, &ixSMU_PM_STATUS_66[0], sizeof(ixSMU_PM_STATUS_66)/sizeof(ixSMU_PM_STATUS_66[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_67", REG_SMC, 0x33f0c, &ixSMU_PM_STATUS_67[0], sizeof(ixSMU_PM_STATUS_67)/sizeof(ixSMU_PM_STATUS_67[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_68", REG_SMC, 0x33f10, &ixSMU_PM_STATUS_68[0], sizeof(ixSMU_PM_STATUS_68)/sizeof(ixSMU_PM_STATUS_68[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_69", REG_SMC, 0x33f14, &ixSMU_PM_STATUS_69[0], sizeof(ixSMU_PM_STATUS_69)/sizeof(ixSMU_PM_STATUS_69[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_70", REG_SMC, 0x33f18, &ixSMU_PM_STATUS_70[0], sizeof(ixSMU_PM_STATUS_70)/sizeof(ixSMU_PM_STATUS_70[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_71", REG_SMC, 0x33f1c, &ixSMU_PM_STATUS_71[0], sizeof(ixSMU_PM_STATUS_71)/sizeof(ixSMU_PM_STATUS_71[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_72", REG_SMC, 0x33f20, &ixSMU_PM_STATUS_72[0], sizeof(ixSMU_PM_STATUS_72)/sizeof(ixSMU_PM_STATUS_72[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_73", REG_SMC, 0x33f24, &ixSMU_PM_STATUS_73[0], sizeof(ixSMU_PM_STATUS_73)/sizeof(ixSMU_PM_STATUS_73[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_74", REG_SMC, 0x33f28, &ixSMU_PM_STATUS_74[0], sizeof(ixSMU_PM_STATUS_74)/sizeof(ixSMU_PM_STATUS_74[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_75", REG_SMC, 0x33f2c, &ixSMU_PM_STATUS_75[0], sizeof(ixSMU_PM_STATUS_75)/sizeof(ixSMU_PM_STATUS_75[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_76", REG_SMC, 0x33f30, &ixSMU_PM_STATUS_76[0], sizeof(ixSMU_PM_STATUS_76)/sizeof(ixSMU_PM_STATUS_76[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_77", REG_SMC, 0x33f34, &ixSMU_PM_STATUS_77[0], sizeof(ixSMU_PM_STATUS_77)/sizeof(ixSMU_PM_STATUS_77[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_78", REG_SMC, 0x33f38, &ixSMU_PM_STATUS_78[0], sizeof(ixSMU_PM_STATUS_78)/sizeof(ixSMU_PM_STATUS_78[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_79", REG_SMC, 0x33f3c, &ixSMU_PM_STATUS_79[0], sizeof(ixSMU_PM_STATUS_79)/sizeof(ixSMU_PM_STATUS_79[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_80", REG_SMC, 0x33f40, &ixSMU_PM_STATUS_80[0], sizeof(ixSMU_PM_STATUS_80)/sizeof(ixSMU_PM_STATUS_80[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_81", REG_SMC, 0x33f44, &ixSMU_PM_STATUS_81[0], sizeof(ixSMU_PM_STATUS_81)/sizeof(ixSMU_PM_STATUS_81[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_82", REG_SMC, 0x33f48, &ixSMU_PM_STATUS_82[0], sizeof(ixSMU_PM_STATUS_82)/sizeof(ixSMU_PM_STATUS_82[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_83", REG_SMC, 0x33f4c, &ixSMU_PM_STATUS_83[0], sizeof(ixSMU_PM_STATUS_83)/sizeof(ixSMU_PM_STATUS_83[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_84", REG_SMC, 0x33f50, &ixSMU_PM_STATUS_84[0], sizeof(ixSMU_PM_STATUS_84)/sizeof(ixSMU_PM_STATUS_84[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_85", REG_SMC, 0x33f54, &ixSMU_PM_STATUS_85[0], sizeof(ixSMU_PM_STATUS_85)/sizeof(ixSMU_PM_STATUS_85[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_86", REG_SMC, 0x33f58, &ixSMU_PM_STATUS_86[0], sizeof(ixSMU_PM_STATUS_86)/sizeof(ixSMU_PM_STATUS_86[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_87", REG_SMC, 0x33f5c, &ixSMU_PM_STATUS_87[0], sizeof(ixSMU_PM_STATUS_87)/sizeof(ixSMU_PM_STATUS_87[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_88", REG_SMC, 0x33f60, &ixSMU_PM_STATUS_88[0], sizeof(ixSMU_PM_STATUS_88)/sizeof(ixSMU_PM_STATUS_88[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_89", REG_SMC, 0x33f64, &ixSMU_PM_STATUS_89[0], sizeof(ixSMU_PM_STATUS_89)/sizeof(ixSMU_PM_STATUS_89[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_90", REG_SMC, 0x33f68, &ixSMU_PM_STATUS_90[0], sizeof(ixSMU_PM_STATUS_90)/sizeof(ixSMU_PM_STATUS_90[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_91", REG_SMC, 0x33f6c, &ixSMU_PM_STATUS_91[0], sizeof(ixSMU_PM_STATUS_91)/sizeof(ixSMU_PM_STATUS_91[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_92", REG_SMC, 0x33f70, &ixSMU_PM_STATUS_92[0], sizeof(ixSMU_PM_STATUS_92)/sizeof(ixSMU_PM_STATUS_92[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_93", REG_SMC, 0x33f74, &ixSMU_PM_STATUS_93[0], sizeof(ixSMU_PM_STATUS_93)/sizeof(ixSMU_PM_STATUS_93[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_94", REG_SMC, 0x33f78, &ixSMU_PM_STATUS_94[0], sizeof(ixSMU_PM_STATUS_94)/sizeof(ixSMU_PM_STATUS_94[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_95", REG_SMC, 0x33f7c, &ixSMU_PM_STATUS_95[0], sizeof(ixSMU_PM_STATUS_95)/sizeof(ixSMU_PM_STATUS_95[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_96", REG_SMC, 0x33f80, &ixSMU_PM_STATUS_96[0], sizeof(ixSMU_PM_STATUS_96)/sizeof(ixSMU_PM_STATUS_96[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_97", REG_SMC, 0x33f84, &ixSMU_PM_STATUS_97[0], sizeof(ixSMU_PM_STATUS_97)/sizeof(ixSMU_PM_STATUS_97[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_98", REG_SMC, 0x33f88, &ixSMU_PM_STATUS_98[0], sizeof(ixSMU_PM_STATUS_98)/sizeof(ixSMU_PM_STATUS_98[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_99", REG_SMC, 0x33f8c, &ixSMU_PM_STATUS_99[0], sizeof(ixSMU_PM_STATUS_99)/sizeof(ixSMU_PM_STATUS_99[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_100", REG_SMC, 0x33f90, &ixSMU_PM_STATUS_100[0], sizeof(ixSMU_PM_STATUS_100)/sizeof(ixSMU_PM_STATUS_100[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_101", REG_SMC, 0x33f94, &ixSMU_PM_STATUS_101[0], sizeof(ixSMU_PM_STATUS_101)/sizeof(ixSMU_PM_STATUS_101[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_102", REG_SMC, 0x33f98, &ixSMU_PM_STATUS_102[0], sizeof(ixSMU_PM_STATUS_102)/sizeof(ixSMU_PM_STATUS_102[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_103", REG_SMC, 0x33f9c, &ixSMU_PM_STATUS_103[0], sizeof(ixSMU_PM_STATUS_103)/sizeof(ixSMU_PM_STATUS_103[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_104", REG_SMC, 0x33fa0, &ixSMU_PM_STATUS_104[0], sizeof(ixSMU_PM_STATUS_104)/sizeof(ixSMU_PM_STATUS_104[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_105", REG_SMC, 0x33fa4, &ixSMU_PM_STATUS_105[0], sizeof(ixSMU_PM_STATUS_105)/sizeof(ixSMU_PM_STATUS_105[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_106", REG_SMC, 0x33fa8, &ixSMU_PM_STATUS_106[0], sizeof(ixSMU_PM_STATUS_106)/sizeof(ixSMU_PM_STATUS_106[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_107", REG_SMC, 0x33fac, &ixSMU_PM_STATUS_107[0], sizeof(ixSMU_PM_STATUS_107)/sizeof(ixSMU_PM_STATUS_107[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_108", REG_SMC, 0x33fb0, &ixSMU_PM_STATUS_108[0], sizeof(ixSMU_PM_STATUS_108)/sizeof(ixSMU_PM_STATUS_108[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_109", REG_SMC, 0x33fb4, &ixSMU_PM_STATUS_109[0], sizeof(ixSMU_PM_STATUS_109)/sizeof(ixSMU_PM_STATUS_109[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_110", REG_SMC, 0x33fb8, &ixSMU_PM_STATUS_110[0], sizeof(ixSMU_PM_STATUS_110)/sizeof(ixSMU_PM_STATUS_110[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_111", REG_SMC, 0x33fbc, &ixSMU_PM_STATUS_111[0], sizeof(ixSMU_PM_STATUS_111)/sizeof(ixSMU_PM_STATUS_111[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_112", REG_SMC, 0x33fc0, &ixSMU_PM_STATUS_112[0], sizeof(ixSMU_PM_STATUS_112)/sizeof(ixSMU_PM_STATUS_112[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_113", REG_SMC, 0x33fc4, &ixSMU_PM_STATUS_113[0], sizeof(ixSMU_PM_STATUS_113)/sizeof(ixSMU_PM_STATUS_113[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_114", REG_SMC, 0x33fc8, &ixSMU_PM_STATUS_114[0], sizeof(ixSMU_PM_STATUS_114)/sizeof(ixSMU_PM_STATUS_114[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_115", REG_SMC, 0x33fcc, &ixSMU_PM_STATUS_115[0], sizeof(ixSMU_PM_STATUS_115)/sizeof(ixSMU_PM_STATUS_115[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_116", REG_SMC, 0x33fd0, &ixSMU_PM_STATUS_116[0], sizeof(ixSMU_PM_STATUS_116)/sizeof(ixSMU_PM_STATUS_116[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_117", REG_SMC, 0x33fd4, &ixSMU_PM_STATUS_117[0], sizeof(ixSMU_PM_STATUS_117)/sizeof(ixSMU_PM_STATUS_117[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_118", REG_SMC, 0x33fd8, &ixSMU_PM_STATUS_118[0], sizeof(ixSMU_PM_STATUS_118)/sizeof(ixSMU_PM_STATUS_118[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_119", REG_SMC, 0x33fdc, &ixSMU_PM_STATUS_119[0], sizeof(ixSMU_PM_STATUS_119)/sizeof(ixSMU_PM_STATUS_119[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_120", REG_SMC, 0x33fe0, &ixSMU_PM_STATUS_120[0], sizeof(ixSMU_PM_STATUS_120)/sizeof(ixSMU_PM_STATUS_120[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_121", REG_SMC, 0x33fe4, &ixSMU_PM_STATUS_121[0], sizeof(ixSMU_PM_STATUS_121)/sizeof(ixSMU_PM_STATUS_121[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_122", REG_SMC, 0x33fe8, &ixSMU_PM_STATUS_122[0], sizeof(ixSMU_PM_STATUS_122)/sizeof(ixSMU_PM_STATUS_122[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_123", REG_SMC, 0x33fec, &ixSMU_PM_STATUS_123[0], sizeof(ixSMU_PM_STATUS_123)/sizeof(ixSMU_PM_STATUS_123[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_124", REG_SMC, 0x33ff0, &ixSMU_PM_STATUS_124[0], sizeof(ixSMU_PM_STATUS_124)/sizeof(ixSMU_PM_STATUS_124[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_125", REG_SMC, 0x33ff4, &ixSMU_PM_STATUS_125[0], sizeof(ixSMU_PM_STATUS_125)/sizeof(ixSMU_PM_STATUS_125[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_126", REG_SMC, 0x33ff8, &ixSMU_PM_STATUS_126[0], sizeof(ixSMU_PM_STATUS_126)/sizeof(ixSMU_PM_STATUS_126[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_127", REG_SMC, 0x33ffc, &ixSMU_PM_STATUS_127[0], sizeof(ixSMU_PM_STATUS_127)/sizeof(ixSMU_PM_STATUS_127[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_INDEX", REG_MMIO, 0x80, &mmGCK_SMC_IND_INDEX[0], sizeof(mmGCK_SMC_IND_INDEX)/sizeof(mmGCK_SMC_IND_INDEX[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_0", REG_MMIO, 0x80, &mmSMC_IND_INDEX_0[0], sizeof(mmSMC_IND_INDEX_0)/sizeof(mmSMC_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX", REG_MMIO, 0x80, &mmSMC_IND_INDEX[0], sizeof(mmSMC_IND_INDEX)/sizeof(mmSMC_IND_INDEX[0]), 0, 0 },
+	{ "ixSMC_SYSCON_RESET_CNTL", REG_SMC, 0x80000000, &ixSMC_SYSCON_RESET_CNTL[0], sizeof(ixSMC_SYSCON_RESET_CNTL)/sizeof(ixSMC_SYSCON_RESET_CNTL[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_0", REG_SMC, 0x80000004, &ixSMC_SYSCON_CLOCK_CNTL_0[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_0)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_0[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_1", REG_SMC, 0x80000008, &ixSMC_SYSCON_CLOCK_CNTL_1[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_1)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_1[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_2", REG_SMC, 0x8000000c, &ixSMC_SYSCON_CLOCK_CNTL_2[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_2)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_2[0]), 0, 0 },
+	{ "ixSMC_SYSCON_MISC_CNTL", REG_SMC, 0x80000010, NULL, 0, 0, 0 },
+	{ "ixSMC_SYSCON_MSG_ARG_0", REG_SMC, 0x80000068, &ixSMC_SYSCON_MSG_ARG_0[0], sizeof(ixSMC_SYSCON_MSG_ARG_0)/sizeof(ixSMC_SYSCON_MSG_ARG_0[0]), 0, 0 },
+	{ "ixSMC_PC_C", REG_SMC, 0x80000370, &ixSMC_PC_C[0], sizeof(ixSMC_PC_C)/sizeof(ixSMC_PC_C[0]), 0, 0 },
+	{ "ixSMC_SCRATCH9", REG_SMC, 0x80000424, &ixSMC_SCRATCH9[0], sizeof(ixSMC_SCRATCH9)/sizeof(ixSMC_SCRATCH9[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_DATA", REG_MMIO, 0x81, &mmGCK_SMC_IND_DATA[0], sizeof(mmGCK_SMC_IND_DATA)/sizeof(mmGCK_SMC_IND_DATA[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_0", REG_MMIO, 0x81, &mmSMC_IND_DATA_0[0], sizeof(mmSMC_IND_DATA_0)/sizeof(mmSMC_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMC_IND_DATA", REG_MMIO, 0x81, &mmSMC_IND_DATA[0], sizeof(mmSMC_IND_DATA)/sizeof(mmSMC_IND_DATA[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_1", REG_MMIO, 0x82, &mmSMC_IND_INDEX_1[0], sizeof(mmSMC_IND_INDEX_1)/sizeof(mmSMC_IND_INDEX_1[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_1", REG_MMIO, 0x83, &mmSMC_IND_DATA_1[0], sizeof(mmSMC_IND_DATA_1)/sizeof(mmSMC_IND_DATA_1[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_2", REG_MMIO, 0x84, &mmSMC_IND_INDEX_2[0], sizeof(mmSMC_IND_INDEX_2)/sizeof(mmSMC_IND_INDEX_2[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_2", REG_MMIO, 0x85, &mmSMC_IND_DATA_2[0], sizeof(mmSMC_IND_DATA_2)/sizeof(mmSMC_IND_DATA_2[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_3", REG_MMIO, 0x86, &mmSMC_IND_INDEX_3[0], sizeof(mmSMC_IND_INDEX_3)/sizeof(mmSMC_IND_INDEX_3[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_3", REG_MMIO, 0x87, &mmSMC_IND_DATA_3[0], sizeof(mmSMC_IND_DATA_3)/sizeof(mmSMC_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_4", REG_MMIO, 0x88, &mmSMC_IND_INDEX_4[0], sizeof(mmSMC_IND_INDEX_4)/sizeof(mmSMC_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_4", REG_MMIO, 0x89, &mmSMC_IND_DATA_4[0], sizeof(mmSMC_IND_DATA_4)/sizeof(mmSMC_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_5", REG_MMIO, 0x8a, &mmSMC_IND_INDEX_5[0], sizeof(mmSMC_IND_INDEX_5)/sizeof(mmSMC_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_5", REG_MMIO, 0x8b, &mmSMC_IND_DATA_5[0], sizeof(mmSMC_IND_DATA_5)/sizeof(mmSMC_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_6", REG_MMIO, 0x8c, &mmSMC_IND_INDEX_6[0], sizeof(mmSMC_IND_INDEX_6)/sizeof(mmSMC_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_6", REG_MMIO, 0x8d, &mmSMC_IND_DATA_6[0], sizeof(mmSMC_IND_DATA_6)/sizeof(mmSMC_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_7", REG_MMIO, 0x8e, &mmSMC_IND_INDEX_7[0], sizeof(mmSMC_IND_INDEX_7)/sizeof(mmSMC_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_7", REG_MMIO, 0x8f, &mmSMC_IND_DATA_7[0], sizeof(mmSMC_IND_DATA_7)/sizeof(mmSMC_IND_DATA_7[0]), 0, 0 },
+	{ "mmSMC_IND_ACCESS_CNTL", REG_MMIO, 0x92, &mmSMC_IND_ACCESS_CNTL[0], sizeof(mmSMC_IND_ACCESS_CNTL)/sizeof(mmSMC_IND_ACCESS_CNTL[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_11", REG_MMIO, 0x93, &mmSMC_MSG_ARG_11[0], sizeof(mmSMC_MSG_ARG_11)/sizeof(mmSMC_MSG_ARG_11[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_0", REG_MMIO, 0x94, &mmSMC_MESSAGE_0[0], sizeof(mmSMC_MESSAGE_0)/sizeof(mmSMC_MESSAGE_0[0]), 0, 0 },
+	{ "mmSMC_RESP_0", REG_MMIO, 0x95, &mmSMC_RESP_0[0], sizeof(mmSMC_RESP_0)/sizeof(mmSMC_RESP_0[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_1", REG_MMIO, 0x96, &mmSMC_MESSAGE_1[0], sizeof(mmSMC_MESSAGE_1)/sizeof(mmSMC_MESSAGE_1[0]), 0, 0 },
+	{ "mmSMC_RESP_1", REG_MMIO, 0x97, &mmSMC_RESP_1[0], sizeof(mmSMC_RESP_1)/sizeof(mmSMC_RESP_1[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_2", REG_MMIO, 0x98, &mmSMC_MESSAGE_2[0], sizeof(mmSMC_MESSAGE_2)/sizeof(mmSMC_MESSAGE_2[0]), 0, 0 },
+	{ "mmSMC_RESP_2", REG_MMIO, 0x99, &mmSMC_RESP_2[0], sizeof(mmSMC_RESP_2)/sizeof(mmSMC_RESP_2[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_3", REG_MMIO, 0x9a, &mmSMC_MESSAGE_3[0], sizeof(mmSMC_MESSAGE_3)/sizeof(mmSMC_MESSAGE_3[0]), 0, 0 },
+	{ "mmSMC_RESP_3", REG_MMIO, 0x9b, &mmSMC_RESP_3[0], sizeof(mmSMC_RESP_3)/sizeof(mmSMC_RESP_3[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_4", REG_MMIO, 0x9c, &mmSMC_MESSAGE_4[0], sizeof(mmSMC_MESSAGE_4)/sizeof(mmSMC_MESSAGE_4[0]), 0, 0 },
+	{ "mmSMC_RESP_4", REG_MMIO, 0x9d, &mmSMC_RESP_4[0], sizeof(mmSMC_RESP_4)/sizeof(mmSMC_RESP_4[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_5", REG_MMIO, 0x9e, &mmSMC_MESSAGE_5[0], sizeof(mmSMC_MESSAGE_5)/sizeof(mmSMC_MESSAGE_5[0]), 0, 0 },
+	{ "mmSMC_RESP_5", REG_MMIO, 0x9f, &mmSMC_RESP_5[0], sizeof(mmSMC_RESP_5)/sizeof(mmSMC_RESP_5[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_6", REG_MMIO, 0xa0, &mmSMC_MESSAGE_6[0], sizeof(mmSMC_MESSAGE_6)/sizeof(mmSMC_MESSAGE_6[0]), 0, 0 },
+	{ "mmSMC_RESP_6", REG_MMIO, 0xa1, &mmSMC_RESP_6[0], sizeof(mmSMC_RESP_6)/sizeof(mmSMC_RESP_6[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_7", REG_MMIO, 0xa2, &mmSMC_MESSAGE_7[0], sizeof(mmSMC_MESSAGE_7)/sizeof(mmSMC_MESSAGE_7[0]), 0, 0 },
+	{ "mmSMC_RESP_7", REG_MMIO, 0xa3, &mmSMC_RESP_7[0], sizeof(mmSMC_RESP_7)/sizeof(mmSMC_RESP_7[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_0", REG_MMIO, 0xa4, &mmSMC_MSG_ARG_0[0], sizeof(mmSMC_MSG_ARG_0)/sizeof(mmSMC_MSG_ARG_0[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_1", REG_MMIO, 0xa5, &mmSMC_MSG_ARG_1[0], sizeof(mmSMC_MSG_ARG_1)/sizeof(mmSMC_MSG_ARG_1[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_2", REG_MMIO, 0xa6, &mmSMC_MSG_ARG_2[0], sizeof(mmSMC_MSG_ARG_2)/sizeof(mmSMC_MSG_ARG_2[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_3", REG_MMIO, 0xa7, &mmSMC_MSG_ARG_3[0], sizeof(mmSMC_MSG_ARG_3)/sizeof(mmSMC_MSG_ARG_3[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_4", REG_MMIO, 0xa8, &mmSMC_MSG_ARG_4[0], sizeof(mmSMC_MSG_ARG_4)/sizeof(mmSMC_MSG_ARG_4[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_5", REG_MMIO, 0xa9, &mmSMC_MSG_ARG_5[0], sizeof(mmSMC_MSG_ARG_5)/sizeof(mmSMC_MSG_ARG_5[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_6", REG_MMIO, 0xaa, &mmSMC_MSG_ARG_6[0], sizeof(mmSMC_MSG_ARG_6)/sizeof(mmSMC_MSG_ARG_6[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_7", REG_MMIO, 0xab, &mmSMC_MSG_ARG_7[0], sizeof(mmSMC_MSG_ARG_7)/sizeof(mmSMC_MSG_ARG_7[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_8", REG_MMIO, 0xb5, &mmSMC_MESSAGE_8[0], sizeof(mmSMC_MESSAGE_8)/sizeof(mmSMC_MESSAGE_8[0]), 0, 0 },
+	{ "mmSMC_RESP_8", REG_MMIO, 0xb6, &mmSMC_RESP_8[0], sizeof(mmSMC_RESP_8)/sizeof(mmSMC_RESP_8[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_9", REG_MMIO, 0xb7, &mmSMC_MESSAGE_9[0], sizeof(mmSMC_MESSAGE_9)/sizeof(mmSMC_MESSAGE_9[0]), 0, 0 },
+	{ "mmSMC_RESP_9", REG_MMIO, 0xb8, &mmSMC_RESP_9[0], sizeof(mmSMC_RESP_9)/sizeof(mmSMC_RESP_9[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_10", REG_MMIO, 0xb9, &mmSMC_MESSAGE_10[0], sizeof(mmSMC_MESSAGE_10)/sizeof(mmSMC_MESSAGE_10[0]), 0, 0 },
+	{ "mmSMC_RESP_10", REG_MMIO, 0xba, &mmSMC_RESP_10[0], sizeof(mmSMC_RESP_10)/sizeof(mmSMC_RESP_10[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_11", REG_MMIO, 0xbb, &mmSMC_MESSAGE_11[0], sizeof(mmSMC_MESSAGE_11)/sizeof(mmSMC_MESSAGE_11[0]), 0, 0 },
+	{ "mmSMC_RESP_11", REG_MMIO, 0xbc, &mmSMC_RESP_11[0], sizeof(mmSMC_RESP_11)/sizeof(mmSMC_RESP_11[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_8", REG_MMIO, 0xbd, &mmSMC_MSG_ARG_8[0], sizeof(mmSMC_MSG_ARG_8)/sizeof(mmSMC_MSG_ARG_8[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_9", REG_MMIO, 0xbe, &mmSMC_MSG_ARG_9[0], sizeof(mmSMC_MSG_ARG_9)/sizeof(mmSMC_MSG_ARG_9[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_10", REG_MMIO, 0xbf, &mmSMC_MSG_ARG_10[0], sizeof(mmSMC_MSG_ARG_10)/sizeof(mmSMC_MSG_ARG_10[0]), 0, 0 },
+	{ "ixRCU_UC_EVENTS", REG_SMC, 0xc0000004, &ixRCU_UC_EVENTS[0], sizeof(ixRCU_UC_EVENTS)/sizeof(ixRCU_UC_EVENTS[0]), 0, 0 },
+	{ "ixRCU_MISC_CTRL", REG_SMC, 0xc0000010, &ixRCU_MISC_CTRL[0], sizeof(ixRCU_MISC_CTRL)/sizeof(ixRCU_MISC_CTRL[0]), 0, 0 },
+	{ "ixCC_RCU_FUSES", REG_SMC, 0xc00c0000, &ixCC_RCU_FUSES[0], sizeof(ixCC_RCU_FUSES)/sizeof(ixCC_RCU_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_MISC_FUSES", REG_SMC, 0xc00c0004, &ixCC_SMU_MISC_FUSES[0], sizeof(ixCC_SMU_MISC_FUSES)/sizeof(ixCC_SMU_MISC_FUSES[0]), 0, 0 },
+	{ "ixCC_SCLK_VID_FUSES", REG_SMC, 0xc00c0008, &ixCC_SCLK_VID_FUSES[0], sizeof(ixCC_SCLK_VID_FUSES)/sizeof(ixCC_SCLK_VID_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOCCFG_FUSES", REG_SMC, 0xc00c000c, &ixCC_GIO_IOCCFG_FUSES[0], sizeof(ixCC_GIO_IOCCFG_FUSES)/sizeof(ixCC_GIO_IOCCFG_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOC_FUSES", REG_SMC, 0xc00c0010, &ixCC_GIO_IOC_FUSES[0], sizeof(ixCC_GIO_IOC_FUSES)/sizeof(ixCC_GIO_IOC_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_TST_EFUSE1_MISC", REG_SMC, 0xc00c001c, &ixCC_SMU_TST_EFUSE1_MISC[0], sizeof(ixCC_SMU_TST_EFUSE1_MISC)/sizeof(ixCC_SMU_TST_EFUSE1_MISC[0]), 0, 0 },
+	{ "ixCC_TST_ID_STRAPS", REG_SMC, 0xc00c0020, &ixCC_TST_ID_STRAPS[0], sizeof(ixCC_TST_ID_STRAPS)/sizeof(ixCC_TST_ID_STRAPS[0]), 0, 0 },
+	{ "ixCC_FCTRL_FUSES", REG_SMC, 0xc00c0024, &ixCC_FCTRL_FUSES[0], sizeof(ixCC_FCTRL_FUSES)/sizeof(ixCC_FCTRL_FUSES[0]), 0, 0 },
+	{ "ixCC_HARVEST_FUSES", REG_SMC, 0xc00c0028, &ixCC_HARVEST_FUSES[0], sizeof(ixCC_HARVEST_FUSES)/sizeof(ixCC_HARVEST_FUSES[0]), 0, 0 },
+	{ "ixSMU_EFUSE_0", REG_SMC, 0xc0100000, &ixSMU_EFUSE_0[0], sizeof(ixSMU_EFUSE_0)/sizeof(ixSMU_EFUSE_0[0]), 0, 0 },
+	{ "ixGENERAL_PWRMGT", REG_SMC, 0xc0200000, &ixGENERAL_PWRMGT[0], sizeof(ixGENERAL_PWRMGT)/sizeof(ixGENERAL_PWRMGT[0]), 0, 0 },
+	{ "ixCNB_PWRMGT_CNTL", REG_SMC, 0xc0200004, &ixCNB_PWRMGT_CNTL[0], sizeof(ixCNB_PWRMGT_CNTL)/sizeof(ixCNB_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixSCLK_PWRMGT_CNTL", REG_SMC, 0xc0200008, &ixSCLK_PWRMGT_CNTL[0], sizeof(ixSCLK_PWRMGT_CNTL)/sizeof(ixSCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX", REG_SMC, 0xc0200014, &ixTARGET_AND_CURRENT_PROFILE_INDEX[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX[0]), 0, 0 },
+	{ "ixPWR_PCC_CONTROL", REG_SMC, 0xc0200018, &ixPWR_PCC_CONTROL[0], sizeof(ixPWR_PCC_CONTROL)/sizeof(ixPWR_PCC_CONTROL[0]), 0, 0 },
+	{ "ixPWR_PCC_GPIO_SELECT", REG_SMC, 0xc020001c, &ixPWR_PCC_GPIO_SELECT[0], sizeof(ixPWR_PCC_GPIO_SELECT)/sizeof(ixPWR_PCC_GPIO_SELECT[0]), 0, 0 },
+	{ "ixPLL_TEST_CNTL", REG_SMC, 0xc020003c, &ixPLL_TEST_CNTL[0], sizeof(ixPLL_TEST_CNTL)/sizeof(ixPLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixCG_STATIC_SCREEN_PARAMETER", REG_SMC, 0xc0200044, &ixCG_STATIC_SCREEN_PARAMETER[0], sizeof(ixCG_STATIC_SCREEN_PARAMETER)/sizeof(ixCG_STATIC_SCREEN_PARAMETER[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL", REG_SMC, 0xc0200060, &ixCG_DISPLAY_GAP_CNTL[0], sizeof(ixCG_DISPLAY_GAP_CNTL)/sizeof(ixCG_DISPLAY_GAP_CNTL[0]), 0, 0 },
+	{ "ixCG_ACPI_CNTL", REG_SMC, 0xc0200064, &ixCG_ACPI_CNTL[0], sizeof(ixCG_ACPI_CNTL)/sizeof(ixCG_ACPI_CNTL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_14_CONTROL", REG_SMC, 0xc0200074, &ixPWR_DISP_TIMER_14_CONTROL[0], sizeof(ixPWR_DISP_TIMER_14_CONTROL)/sizeof(ixPWR_DISP_TIMER_14_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_15_CONTROL", REG_SMC, 0xc0200078, &ixPWR_DISP_TIMER_15_CONTROL[0], sizeof(ixPWR_DISP_TIMER_15_CONTROL)/sizeof(ixPWR_DISP_TIMER_15_CONTROL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc0200080, &ixSCLK_DEEP_SLEEP_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200084, &ixSCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL2)/sizeof(ixSCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_MISC_CNTL", REG_SMC, 0xc0200088, &ixSCLK_DEEP_SLEEP_MISC_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc020008c, &ixLCLK_DEEP_SLEEP_CNTL[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL)/sizeof(ixLCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL3", REG_SMC, 0xc020009c, &ixSCLK_DEEP_SLEEP_CNTL3[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL3)/sizeof(ixSCLK_DEEP_SLEEP_CNTL3[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_1", REG_SMC, 0xc02000f0, &ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0]), 0, 0 },
+	{ "ixCG_ULV_PARAMETER", REG_SMC, 0xc020015c, &ixCG_ULV_PARAMETER[0], sizeof(ixCG_ULV_PARAMETER)/sizeof(ixCG_ULV_PARAMETER[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_0", REG_SMC, 0xc02001a8, &ixCG_FREQ_TRAN_VOTING_0[0], sizeof(ixCG_FREQ_TRAN_VOTING_0)/sizeof(ixCG_FREQ_TRAN_VOTING_0[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_1", REG_SMC, 0xc02001ac, &ixCG_FREQ_TRAN_VOTING_1[0], sizeof(ixCG_FREQ_TRAN_VOTING_1)/sizeof(ixCG_FREQ_TRAN_VOTING_1[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_2", REG_SMC, 0xc02001b0, &ixCG_FREQ_TRAN_VOTING_2[0], sizeof(ixCG_FREQ_TRAN_VOTING_2)/sizeof(ixCG_FREQ_TRAN_VOTING_2[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_3", REG_SMC, 0xc02001b4, &ixCG_FREQ_TRAN_VOTING_3[0], sizeof(ixCG_FREQ_TRAN_VOTING_3)/sizeof(ixCG_FREQ_TRAN_VOTING_3[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_4", REG_SMC, 0xc02001b8, &ixCG_FREQ_TRAN_VOTING_4[0], sizeof(ixCG_FREQ_TRAN_VOTING_4)/sizeof(ixCG_FREQ_TRAN_VOTING_4[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_5", REG_SMC, 0xc02001bc, &ixCG_FREQ_TRAN_VOTING_5[0], sizeof(ixCG_FREQ_TRAN_VOTING_5)/sizeof(ixCG_FREQ_TRAN_VOTING_5[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, &ixCG_DISPLAY_GAP_CNTL2[0], sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_PARAMETER", REG_SMC, 0xc020036c, &ixVDDGFX_IDLE_PARAMETER[0], sizeof(ixVDDGFX_IDLE_PARAMETER)/sizeof(ixVDDGFX_IDLE_PARAMETER[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_CONTROL", REG_SMC, 0xc0200370, &ixVDDGFX_IDLE_CONTROL[0], sizeof(ixVDDGFX_IDLE_CONTROL)/sizeof(ixVDDGFX_IDLE_CONTROL[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_EXIT", REG_SMC, 0xc0200374, &ixVDDGFX_IDLE_EXIT[0], sizeof(ixVDDGFX_IDLE_EXIT)/sizeof(ixVDDGFX_IDLE_EXIT[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_CONTROL2", REG_SMC, 0xc0200378, &ixPWR_DISP_TIMER_CONTROL2[0], sizeof(ixPWR_DISP_TIMER_CONTROL2)/sizeof(ixPWR_DISP_TIMER_CONTROL2[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_1_CONTROL", REG_SMC, 0xc020037c, &ixPWR_DISP_TIMER_1_CONTROL[0], sizeof(ixPWR_DISP_TIMER_1_CONTROL)/sizeof(ixPWR_DISP_TIMER_1_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_0_CONTROL", REG_SMC, 0xc0200390, &ixPWR_DISP_TIMER_0_CONTROL[0], sizeof(ixPWR_DISP_TIMER_0_CONTROL)/sizeof(ixPWR_DISP_TIMER_0_CONTROL[0]), 0, 0 },
+	{ "ixSCLK_MIN_DIV", REG_SMC, 0xc02003ac, &ixSCLK_MIN_DIV[0], sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_2_CONTROL", REG_SMC, 0xc02003d0, &ixPWR_DISP_TIMER_2_CONTROL[0], sizeof(ixPWR_DISP_TIMER_2_CONTROL)/sizeof(ixPWR_DISP_TIMER_2_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_3_CONTROL", REG_SMC, 0xc02003d4, &ixPWR_DISP_TIMER_3_CONTROL[0], sizeof(ixPWR_DISP_TIMER_3_CONTROL)/sizeof(ixPWR_DISP_TIMER_3_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_4_CONTROL", REG_SMC, 0xc02003d8, &ixPWR_DISP_TIMER_4_CONTROL[0], sizeof(ixPWR_DISP_TIMER_4_CONTROL)/sizeof(ixPWR_DISP_TIMER_4_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_5_CONTROL", REG_SMC, 0xc02003dc, &ixPWR_DISP_TIMER_5_CONTROL[0], sizeof(ixPWR_DISP_TIMER_5_CONTROL)/sizeof(ixPWR_DISP_TIMER_5_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_6_CONTROL", REG_SMC, 0xc02003e0, &ixPWR_DISP_TIMER_6_CONTROL[0], sizeof(ixPWR_DISP_TIMER_6_CONTROL)/sizeof(ixPWR_DISP_TIMER_6_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_7_CONTROL", REG_SMC, 0xc02003e4, &ixPWR_DISP_TIMER_7_CONTROL[0], sizeof(ixPWR_DISP_TIMER_7_CONTROL)/sizeof(ixPWR_DISP_TIMER_7_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_8_CONTROL", REG_SMC, 0xc02003e8, &ixPWR_DISP_TIMER_8_CONTROL[0], sizeof(ixPWR_DISP_TIMER_8_CONTROL)/sizeof(ixPWR_DISP_TIMER_8_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_9_CONTROL", REG_SMC, 0xc02003ec, &ixPWR_DISP_TIMER_9_CONTROL[0], sizeof(ixPWR_DISP_TIMER_9_CONTROL)/sizeof(ixPWR_DISP_TIMER_9_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_10_CONTROL", REG_SMC, 0xc02003f0, &ixPWR_DISP_TIMER_10_CONTROL[0], sizeof(ixPWR_DISP_TIMER_10_CONTROL)/sizeof(ixPWR_DISP_TIMER_10_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_11_CONTROL", REG_SMC, 0xc02003f4, &ixPWR_DISP_TIMER_11_CONTROL[0], sizeof(ixPWR_DISP_TIMER_11_CONTROL)/sizeof(ixPWR_DISP_TIMER_11_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_12_CONTROL", REG_SMC, 0xc02003f8, &ixPWR_DISP_TIMER_12_CONTROL[0], sizeof(ixPWR_DISP_TIMER_12_CONTROL)/sizeof(ixPWR_DISP_TIMER_12_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_13_CONTROL", REG_SMC, 0xc02003fc, &ixPWR_DISP_TIMER_13_CONTROL[0], sizeof(ixPWR_DISP_TIMER_13_CONTROL)/sizeof(ixPWR_DISP_TIMER_13_CONTROL[0]), 0, 0 },
+	{ "ixCG_THERMAL_CTRL", REG_SMC, 0xc0300004, &ixCG_THERMAL_CTRL[0], sizeof(ixCG_THERMAL_CTRL)/sizeof(ixCG_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_STATUS", REG_SMC, 0xc0300008, &ixCG_THERMAL_STATUS[0], sizeof(ixCG_THERMAL_STATUS)/sizeof(ixCG_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT", REG_SMC, 0xc030000c, &ixCG_THERMAL_INT[0], sizeof(ixCG_THERMAL_INT)/sizeof(ixCG_THERMAL_INT[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_CTRL", REG_SMC, 0xc0300010, &ixCG_MULT_THERMAL_CTRL[0], sizeof(ixCG_MULT_THERMAL_CTRL)/sizeof(ixCG_MULT_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_STATUS", REG_SMC, 0xc0300014, &ixCG_MULT_THERMAL_STATUS[0], sizeof(ixCG_MULT_THERMAL_STATUS)/sizeof(ixCG_MULT_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL0", REG_SMC, 0xc0300064, &ixCG_FDO_CTRL0[0], sizeof(ixCG_FDO_CTRL0)/sizeof(ixCG_FDO_CTRL0[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL1", REG_SMC, 0xc0300068, &ixCG_FDO_CTRL1[0], sizeof(ixCG_FDO_CTRL1)/sizeof(ixCG_FDO_CTRL1[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL2", REG_SMC, 0xc030006c, &ixCG_FDO_CTRL2[0], sizeof(ixCG_FDO_CTRL2)/sizeof(ixCG_FDO_CTRL2[0]), 0, 0 },
+	{ "ixCG_TACH_CTRL", REG_SMC, 0xc0300070, &ixCG_TACH_CTRL[0], sizeof(ixCG_TACH_CTRL)/sizeof(ixCG_TACH_CTRL[0]), 0, 0 },
+	{ "ixCG_TACH_STATUS", REG_SMC, 0xc0300074, &ixCG_TACH_STATUS[0], sizeof(ixCG_TACH_STATUS)/sizeof(ixCG_TACH_STATUS[0]), 0, 0 },
+	{ "ixCC_THM_STRAPS0", REG_SMC, 0xc0300080, &ixCC_THM_STRAPS0[0], sizeof(ixCC_THM_STRAPS0)/sizeof(ixCC_THM_STRAPS0[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL0_DATA", REG_SMC, 0xc0300100, &ixTHM_TMON0_RDIL0_DATA[0], sizeof(ixTHM_TMON0_RDIL0_DATA)/sizeof(ixTHM_TMON0_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL1_DATA", REG_SMC, 0xc0300104, &ixTHM_TMON0_RDIL1_DATA[0], sizeof(ixTHM_TMON0_RDIL1_DATA)/sizeof(ixTHM_TMON0_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL2_DATA", REG_SMC, 0xc0300108, &ixTHM_TMON0_RDIL2_DATA[0], sizeof(ixTHM_TMON0_RDIL2_DATA)/sizeof(ixTHM_TMON0_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL3_DATA", REG_SMC, 0xc030010c, &ixTHM_TMON0_RDIL3_DATA[0], sizeof(ixTHM_TMON0_RDIL3_DATA)/sizeof(ixTHM_TMON0_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL4_DATA", REG_SMC, 0xc0300110, &ixTHM_TMON0_RDIL4_DATA[0], sizeof(ixTHM_TMON0_RDIL4_DATA)/sizeof(ixTHM_TMON0_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL5_DATA", REG_SMC, 0xc0300114, &ixTHM_TMON0_RDIL5_DATA[0], sizeof(ixTHM_TMON0_RDIL5_DATA)/sizeof(ixTHM_TMON0_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL6_DATA", REG_SMC, 0xc0300118, &ixTHM_TMON0_RDIL6_DATA[0], sizeof(ixTHM_TMON0_RDIL6_DATA)/sizeof(ixTHM_TMON0_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL7_DATA", REG_SMC, 0xc030011c, &ixTHM_TMON0_RDIL7_DATA[0], sizeof(ixTHM_TMON0_RDIL7_DATA)/sizeof(ixTHM_TMON0_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL8_DATA", REG_SMC, 0xc0300120, &ixTHM_TMON0_RDIL8_DATA[0], sizeof(ixTHM_TMON0_RDIL8_DATA)/sizeof(ixTHM_TMON0_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL9_DATA", REG_SMC, 0xc0300124, &ixTHM_TMON0_RDIL9_DATA[0], sizeof(ixTHM_TMON0_RDIL9_DATA)/sizeof(ixTHM_TMON0_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL10_DATA", REG_SMC, 0xc0300128, &ixTHM_TMON0_RDIL10_DATA[0], sizeof(ixTHM_TMON0_RDIL10_DATA)/sizeof(ixTHM_TMON0_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL11_DATA", REG_SMC, 0xc030012c, &ixTHM_TMON0_RDIL11_DATA[0], sizeof(ixTHM_TMON0_RDIL11_DATA)/sizeof(ixTHM_TMON0_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL12_DATA", REG_SMC, 0xc0300130, &ixTHM_TMON0_RDIL12_DATA[0], sizeof(ixTHM_TMON0_RDIL12_DATA)/sizeof(ixTHM_TMON0_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL13_DATA", REG_SMC, 0xc0300134, &ixTHM_TMON0_RDIL13_DATA[0], sizeof(ixTHM_TMON0_RDIL13_DATA)/sizeof(ixTHM_TMON0_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL14_DATA", REG_SMC, 0xc0300138, &ixTHM_TMON0_RDIL14_DATA[0], sizeof(ixTHM_TMON0_RDIL14_DATA)/sizeof(ixTHM_TMON0_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL15_DATA", REG_SMC, 0xc030013c, &ixTHM_TMON0_RDIL15_DATA[0], sizeof(ixTHM_TMON0_RDIL15_DATA)/sizeof(ixTHM_TMON0_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR0_DATA", REG_SMC, 0xc0300140, &ixTHM_TMON0_RDIR0_DATA[0], sizeof(ixTHM_TMON0_RDIR0_DATA)/sizeof(ixTHM_TMON0_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR1_DATA", REG_SMC, 0xc0300144, &ixTHM_TMON0_RDIR1_DATA[0], sizeof(ixTHM_TMON0_RDIR1_DATA)/sizeof(ixTHM_TMON0_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR2_DATA", REG_SMC, 0xc0300148, &ixTHM_TMON0_RDIR2_DATA[0], sizeof(ixTHM_TMON0_RDIR2_DATA)/sizeof(ixTHM_TMON0_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR3_DATA", REG_SMC, 0xc030014c, &ixTHM_TMON0_RDIR3_DATA[0], sizeof(ixTHM_TMON0_RDIR3_DATA)/sizeof(ixTHM_TMON0_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR4_DATA", REG_SMC, 0xc0300150, &ixTHM_TMON0_RDIR4_DATA[0], sizeof(ixTHM_TMON0_RDIR4_DATA)/sizeof(ixTHM_TMON0_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR5_DATA", REG_SMC, 0xc0300154, &ixTHM_TMON0_RDIR5_DATA[0], sizeof(ixTHM_TMON0_RDIR5_DATA)/sizeof(ixTHM_TMON0_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR6_DATA", REG_SMC, 0xc0300158, &ixTHM_TMON0_RDIR6_DATA[0], sizeof(ixTHM_TMON0_RDIR6_DATA)/sizeof(ixTHM_TMON0_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR7_DATA", REG_SMC, 0xc030015c, &ixTHM_TMON0_RDIR7_DATA[0], sizeof(ixTHM_TMON0_RDIR7_DATA)/sizeof(ixTHM_TMON0_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR8_DATA", REG_SMC, 0xc0300160, &ixTHM_TMON0_RDIR8_DATA[0], sizeof(ixTHM_TMON0_RDIR8_DATA)/sizeof(ixTHM_TMON0_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR9_DATA", REG_SMC, 0xc0300164, &ixTHM_TMON0_RDIR9_DATA[0], sizeof(ixTHM_TMON0_RDIR9_DATA)/sizeof(ixTHM_TMON0_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR10_DATA", REG_SMC, 0xc0300168, &ixTHM_TMON0_RDIR10_DATA[0], sizeof(ixTHM_TMON0_RDIR10_DATA)/sizeof(ixTHM_TMON0_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR11_DATA", REG_SMC, 0xc030016c, &ixTHM_TMON0_RDIR11_DATA[0], sizeof(ixTHM_TMON0_RDIR11_DATA)/sizeof(ixTHM_TMON0_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR12_DATA", REG_SMC, 0xc0300170, &ixTHM_TMON0_RDIR12_DATA[0], sizeof(ixTHM_TMON0_RDIR12_DATA)/sizeof(ixTHM_TMON0_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR13_DATA", REG_SMC, 0xc0300174, &ixTHM_TMON0_RDIR13_DATA[0], sizeof(ixTHM_TMON0_RDIR13_DATA)/sizeof(ixTHM_TMON0_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR14_DATA", REG_SMC, 0xc0300178, &ixTHM_TMON0_RDIR14_DATA[0], sizeof(ixTHM_TMON0_RDIR14_DATA)/sizeof(ixTHM_TMON0_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR15_DATA", REG_SMC, 0xc030017c, &ixTHM_TMON0_RDIR15_DATA[0], sizeof(ixTHM_TMON0_RDIR15_DATA)/sizeof(ixTHM_TMON0_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_INT_DATA", REG_SMC, 0xc0300300, &ixTHM_TMON0_INT_DATA[0], sizeof(ixTHM_TMON0_INT_DATA)/sizeof(ixTHM_TMON0_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_DEBUG", REG_SMC, 0xc0300310, &ixTHM_TMON0_DEBUG[0], sizeof(ixTHM_TMON0_DEBUG)/sizeof(ixTHM_TMON0_DEBUG[0]), 0, 0 },
+	{ "ixTHM_TMON0_STATUS", REG_SMC, 0xc0300320, &ixTHM_TMON0_STATUS[0], sizeof(ixTHM_TMON0_STATUS)/sizeof(ixTHM_TMON0_STATUS[0]), 0, 0 },
+	{ "ixLCAC_MC0_CNTL", REG_SMC, 0xc0400130, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0xc0400134, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0xc0400138, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC1_CNTL", REG_SMC, 0xc040013c, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0xc0400140, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0xc0400144, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC2_CNTL", REG_SMC, 0xc0400148, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0xc040014c, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0xc0400150, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC3_CNTL", REG_SMC, 0xc0400154, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0xc0400158, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0xc040015c, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_CPL_CNTL", REG_SMC, 0xc0400160, &ixLCAC_CPL_CNTL[0], sizeof(ixLCAC_CPL_CNTL)/sizeof(ixLCAC_CPL_CNTL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_SEL", REG_SMC, 0xc0400164, &ixLCAC_CPL_OVR_SEL[0], sizeof(ixLCAC_CPL_OVR_SEL)/sizeof(ixLCAC_CPL_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_VAL", REG_SMC, 0xc0400168, &ixLCAC_CPL_OVR_VAL[0], sizeof(ixLCAC_CPL_OVR_VAL)/sizeof(ixLCAC_CPL_OVR_VAL[0]), 0, 0 },
+	{ "ixCG_DCLK_CNTL", REG_SMC, 0xc050009c, &ixCG_DCLK_CNTL[0], sizeof(ixCG_DCLK_CNTL)/sizeof(ixCG_DCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_DCLK_STATUS", REG_SMC, 0xc05000a0, &ixCG_DCLK_STATUS[0], sizeof(ixCG_DCLK_STATUS)/sizeof(ixCG_DCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_VCLK_CNTL", REG_SMC, 0xc05000a4, &ixCG_VCLK_CNTL[0], sizeof(ixCG_VCLK_CNTL)/sizeof(ixCG_VCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_VCLK_STATUS", REG_SMC, 0xc05000a8, &ixCG_VCLK_STATUS[0], sizeof(ixCG_VCLK_STATUS)/sizeof(ixCG_VCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ECLK_CNTL", REG_SMC, 0xc05000ac, &ixCG_ECLK_CNTL[0], sizeof(ixCG_ECLK_CNTL)/sizeof(ixCG_ECLK_CNTL[0]), 0, 0 },
+	{ "ixCG_ECLK_STATUS", REG_SMC, 0xc05000b0, &ixCG_ECLK_STATUS[0], sizeof(ixCG_ECLK_STATUS)/sizeof(ixCG_ECLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ACLK_CNTL", REG_SMC, 0xc05000dc, &ixCG_ACLK_CNTL[0], sizeof(ixCG_ACLK_CNTL)/sizeof(ixCG_ACLK_CNTL[0]), 0, 0 },
+	{ "ixGCK_DFS_BYPASS_CNTL", REG_SMC, 0xc0500118, &ixGCK_DFS_BYPASS_CNTL[0], sizeof(ixGCK_DFS_BYPASS_CNTL)/sizeof(ixGCK_DFS_BYPASS_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL", REG_SMC, 0xc0500140, &ixCG_SPLL_FUNC_CNTL[0], sizeof(ixCG_SPLL_FUNC_CNTL)/sizeof(ixCG_SPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_2", REG_SMC, 0xc0500144, &ixCG_SPLL_FUNC_CNTL_2[0], sizeof(ixCG_SPLL_FUNC_CNTL_2)/sizeof(ixCG_SPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_3", REG_SMC, 0xc0500148, &ixCG_SPLL_FUNC_CNTL_3[0], sizeof(ixCG_SPLL_FUNC_CNTL_3)/sizeof(ixCG_SPLL_FUNC_CNTL_3[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_4", REG_SMC, 0xc050014c, &ixCG_SPLL_FUNC_CNTL_4[0], sizeof(ixCG_SPLL_FUNC_CNTL_4)/sizeof(ixCG_SPLL_FUNC_CNTL_4[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_5", REG_SMC, 0xc0500150, &ixCG_SPLL_FUNC_CNTL_5[0], sizeof(ixCG_SPLL_FUNC_CNTL_5)/sizeof(ixCG_SPLL_FUNC_CNTL_5[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_6", REG_SMC, 0xc0500154, &ixCG_SPLL_FUNC_CNTL_6[0], sizeof(ixCG_SPLL_FUNC_CNTL_6)/sizeof(ixCG_SPLL_FUNC_CNTL_6[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_7", REG_SMC, 0xc0500158, &ixCG_SPLL_FUNC_CNTL_7[0], sizeof(ixCG_SPLL_FUNC_CNTL_7)/sizeof(ixCG_SPLL_FUNC_CNTL_7[0]), 0, 0 },
+	{ "ixSPLL_CNTL_MODE", REG_SMC, 0xc0500160, &ixSPLL_CNTL_MODE[0], sizeof(ixSPLL_CNTL_MODE)/sizeof(ixSPLL_CNTL_MODE[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM", REG_SMC, 0xc0500164, &ixCG_SPLL_SPREAD_SPECTRUM[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM_2", REG_SMC, 0xc0500168, &ixCG_SPLL_SPREAD_SPECTRUM_2[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2[0]), 0, 0 },
+	{ "ixMPLL_BYPASSCLK_SEL", REG_SMC, 0xc050019c, &ixMPLL_BYPASSCLK_SEL[0], sizeof(ixMPLL_BYPASSCLK_SEL)/sizeof(ixMPLL_BYPASSCLK_SEL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL", REG_SMC, 0xc05001a0, &ixCG_CLKPIN_CNTL[0], sizeof(ixCG_CLKPIN_CNTL)/sizeof(ixCG_CLKPIN_CNTL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_2", REG_SMC, 0xc05001a4, &ixCG_CLKPIN_CNTL_2[0], sizeof(ixCG_CLKPIN_CNTL_2)/sizeof(ixCG_CLKPIN_CNTL_2[0]), 0, 0 },
+	{ "ixTHM_CLK_CNTL", REG_SMC, 0xc05001a8, &ixTHM_CLK_CNTL[0], sizeof(ixTHM_CLK_CNTL)/sizeof(ixTHM_CLK_CNTL[0]), 0, 0 },
+	{ "ixMISC_CLK_CTRL", REG_SMC, 0xc05001ac, &ixMISC_CLK_CTRL[0], sizeof(ixMISC_CLK_CTRL)/sizeof(ixMISC_CLK_CTRL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL", REG_SMC, 0xc05001c0, &ixGCK_PLL_TEST_CNTL[0], sizeof(ixGCK_PLL_TEST_CNTL)/sizeof(ixGCK_PLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL_2", REG_SMC, 0xc05001c4, &ixGCK_PLL_TEST_CNTL_2[0], sizeof(ixGCK_PLL_TEST_CNTL_2)/sizeof(ixGCK_PLL_TEST_CNTL_2[0]), 0, 0 },
+	{ "ixGCK_ADFS_CLK_BYPASS_CNTL1", REG_SMC, 0xc05001c8, &ixGCK_ADFS_CLK_BYPASS_CNTL1[0], sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1)/sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_DC", REG_SMC, 0xc0500204, &ixCG_CLKPIN_CNTL_DC[0], sizeof(ixCG_CLKPIN_CNTL_DC)/sizeof(ixCG_CLKPIN_CNTL_DC[0]), 0, 0 },
+	{ "ixROM_CNTL", REG_SMC, 0xc0600000, &ixROM_CNTL[0], sizeof(ixROM_CNTL)/sizeof(ixROM_CNTL[0]), 0, 0 },
+	{ "ixPAGE_MIRROR_CNTL", REG_SMC, 0xc0600004, &ixPAGE_MIRROR_CNTL[0], sizeof(ixPAGE_MIRROR_CNTL)/sizeof(ixPAGE_MIRROR_CNTL[0]), 0, 0 },
+	{ "ixROM_STATUS", REG_SMC, 0xc0600008, &ixROM_STATUS[0], sizeof(ixROM_STATUS)/sizeof(ixROM_STATUS[0]), 0, 0 },
+	{ "ixCGTT_ROM_CLK_CTRL0", REG_SMC, 0xc060000c, &ixCGTT_ROM_CLK_CTRL0[0], sizeof(ixCGTT_ROM_CLK_CTRL0)/sizeof(ixCGTT_ROM_CLK_CTRL0[0]), 0, 0 },
+	{ "ixROM_INDEX", REG_SMC, 0xc0600010, &ixROM_INDEX[0], sizeof(ixROM_INDEX)/sizeof(ixROM_INDEX[0]), 0, 0 },
+	{ "ixROM_DATA", REG_SMC, 0xc0600014, &ixROM_DATA[0], sizeof(ixROM_DATA)/sizeof(ixROM_DATA[0]), 0, 0 },
+	{ "ixROM_START", REG_SMC, 0xc0600018, &ixROM_START[0], sizeof(ixROM_START)/sizeof(ixROM_START[0]), 0, 0 },
+	{ "ixROM_SW_CNTL", REG_SMC, 0xc060001c, &ixROM_SW_CNTL[0], sizeof(ixROM_SW_CNTL)/sizeof(ixROM_SW_CNTL[0]), 0, 0 },
+	{ "ixROM_SW_STATUS", REG_SMC, 0xc0600020, &ixROM_SW_STATUS[0], sizeof(ixROM_SW_STATUS)/sizeof(ixROM_SW_STATUS[0]), 0, 0 },
+	{ "ixROM_SW_COMMAND", REG_SMC, 0xc0600024, &ixROM_SW_COMMAND[0], sizeof(ixROM_SW_COMMAND)/sizeof(ixROM_SW_COMMAND[0]), 0, 0 },
+	{ "ixROM_SW_DATA_1", REG_SMC, 0xc0600028, &ixROM_SW_DATA_1[0], sizeof(ixROM_SW_DATA_1)/sizeof(ixROM_SW_DATA_1[0]), 0, 0 },
+	{ "ixROM_SW_DATA_2", REG_SMC, 0xc060002c, &ixROM_SW_DATA_2[0], sizeof(ixROM_SW_DATA_2)/sizeof(ixROM_SW_DATA_2[0]), 0, 0 },
+	{ "ixROM_SW_DATA_3", REG_SMC, 0xc0600030, &ixROM_SW_DATA_3[0], sizeof(ixROM_SW_DATA_3)/sizeof(ixROM_SW_DATA_3[0]), 0, 0 },
+	{ "ixROM_SW_DATA_4", REG_SMC, 0xc0600034, &ixROM_SW_DATA_4[0], sizeof(ixROM_SW_DATA_4)/sizeof(ixROM_SW_DATA_4[0]), 0, 0 },
+	{ "ixROM_SW_DATA_5", REG_SMC, 0xc0600038, &ixROM_SW_DATA_5[0], sizeof(ixROM_SW_DATA_5)/sizeof(ixROM_SW_DATA_5[0]), 0, 0 },
+	{ "ixROM_SW_DATA_6", REG_SMC, 0xc060003c, &ixROM_SW_DATA_6[0], sizeof(ixROM_SW_DATA_6)/sizeof(ixROM_SW_DATA_6[0]), 0, 0 },
+	{ "ixROM_SW_DATA_7", REG_SMC, 0xc0600040, &ixROM_SW_DATA_7[0], sizeof(ixROM_SW_DATA_7)/sizeof(ixROM_SW_DATA_7[0]), 0, 0 },
+	{ "ixROM_SW_DATA_8", REG_SMC, 0xc0600044, &ixROM_SW_DATA_8[0], sizeof(ixROM_SW_DATA_8)/sizeof(ixROM_SW_DATA_8[0]), 0, 0 },
+	{ "ixROM_SW_DATA_9", REG_SMC, 0xc0600048, &ixROM_SW_DATA_9[0], sizeof(ixROM_SW_DATA_9)/sizeof(ixROM_SW_DATA_9[0]), 0, 0 },
+	{ "ixROM_SW_DATA_10", REG_SMC, 0xc060004c, &ixROM_SW_DATA_10[0], sizeof(ixROM_SW_DATA_10)/sizeof(ixROM_SW_DATA_10[0]), 0, 0 },
+	{ "ixROM_SW_DATA_11", REG_SMC, 0xc0600050, &ixROM_SW_DATA_11[0], sizeof(ixROM_SW_DATA_11)/sizeof(ixROM_SW_DATA_11[0]), 0, 0 },
+	{ "ixROM_SW_DATA_12", REG_SMC, 0xc0600054, &ixROM_SW_DATA_12[0], sizeof(ixROM_SW_DATA_12)/sizeof(ixROM_SW_DATA_12[0]), 0, 0 },
+	{ "ixROM_SW_DATA_13", REG_SMC, 0xc0600058, &ixROM_SW_DATA_13[0], sizeof(ixROM_SW_DATA_13)/sizeof(ixROM_SW_DATA_13[0]), 0, 0 },
+	{ "ixROM_SW_DATA_14", REG_SMC, 0xc060005c, &ixROM_SW_DATA_14[0], sizeof(ixROM_SW_DATA_14)/sizeof(ixROM_SW_DATA_14[0]), 0, 0 },
+	{ "ixROM_SW_DATA_15", REG_SMC, 0xc0600060, &ixROM_SW_DATA_15[0], sizeof(ixROM_SW_DATA_15)/sizeof(ixROM_SW_DATA_15[0]), 0, 0 },
+	{ "ixROM_SW_DATA_16", REG_SMC, 0xc0600064, &ixROM_SW_DATA_16[0], sizeof(ixROM_SW_DATA_16)/sizeof(ixROM_SW_DATA_16[0]), 0, 0 },
+	{ "ixROM_SW_DATA_17", REG_SMC, 0xc0600068, &ixROM_SW_DATA_17[0], sizeof(ixROM_SW_DATA_17)/sizeof(ixROM_SW_DATA_17[0]), 0, 0 },
+	{ "ixROM_SW_DATA_18", REG_SMC, 0xc060006c, &ixROM_SW_DATA_18[0], sizeof(ixROM_SW_DATA_18)/sizeof(ixROM_SW_DATA_18[0]), 0, 0 },
+	{ "ixROM_SW_DATA_19", REG_SMC, 0xc0600070, &ixROM_SW_DATA_19[0], sizeof(ixROM_SW_DATA_19)/sizeof(ixROM_SW_DATA_19[0]), 0, 0 },
+	{ "ixROM_SW_DATA_20", REG_SMC, 0xc0600074, &ixROM_SW_DATA_20[0], sizeof(ixROM_SW_DATA_20)/sizeof(ixROM_SW_DATA_20[0]), 0, 0 },
+	{ "ixROM_SW_DATA_21", REG_SMC, 0xc0600078, &ixROM_SW_DATA_21[0], sizeof(ixROM_SW_DATA_21)/sizeof(ixROM_SW_DATA_21[0]), 0, 0 },
+	{ "ixROM_SW_DATA_22", REG_SMC, 0xc060007c, &ixROM_SW_DATA_22[0], sizeof(ixROM_SW_DATA_22)/sizeof(ixROM_SW_DATA_22[0]), 0, 0 },
+	{ "ixROM_SW_DATA_23", REG_SMC, 0xc0600080, &ixROM_SW_DATA_23[0], sizeof(ixROM_SW_DATA_23)/sizeof(ixROM_SW_DATA_23[0]), 0, 0 },
+	{ "ixROM_SW_DATA_24", REG_SMC, 0xc0600084, &ixROM_SW_DATA_24[0], sizeof(ixROM_SW_DATA_24)/sizeof(ixROM_SW_DATA_24[0]), 0, 0 },
+	{ "ixROM_SW_DATA_25", REG_SMC, 0xc0600088, &ixROM_SW_DATA_25[0], sizeof(ixROM_SW_DATA_25)/sizeof(ixROM_SW_DATA_25[0]), 0, 0 },
+	{ "ixROM_SW_DATA_26", REG_SMC, 0xc060008c, &ixROM_SW_DATA_26[0], sizeof(ixROM_SW_DATA_26)/sizeof(ixROM_SW_DATA_26[0]), 0, 0 },
+	{ "ixROM_SW_DATA_27", REG_SMC, 0xc0600090, &ixROM_SW_DATA_27[0], sizeof(ixROM_SW_DATA_27)/sizeof(ixROM_SW_DATA_27[0]), 0, 0 },
+	{ "ixROM_SW_DATA_28", REG_SMC, 0xc0600094, &ixROM_SW_DATA_28[0], sizeof(ixROM_SW_DATA_28)/sizeof(ixROM_SW_DATA_28[0]), 0, 0 },
+	{ "ixROM_SW_DATA_29", REG_SMC, 0xc0600098, &ixROM_SW_DATA_29[0], sizeof(ixROM_SW_DATA_29)/sizeof(ixROM_SW_DATA_29[0]), 0, 0 },
+	{ "ixROM_SW_DATA_30", REG_SMC, 0xc060009c, &ixROM_SW_DATA_30[0], sizeof(ixROM_SW_DATA_30)/sizeof(ixROM_SW_DATA_30[0]), 0, 0 },
+	{ "ixROM_SW_DATA_31", REG_SMC, 0xc06000a0, &ixROM_SW_DATA_31[0], sizeof(ixROM_SW_DATA_31)/sizeof(ixROM_SW_DATA_31[0]), 0, 0 },
+	{ "ixROM_SW_DATA_32", REG_SMC, 0xc06000a4, &ixROM_SW_DATA_32[0], sizeof(ixROM_SW_DATA_32)/sizeof(ixROM_SW_DATA_32[0]), 0, 0 },
+	{ "ixROM_SW_DATA_33", REG_SMC, 0xc06000a8, &ixROM_SW_DATA_33[0], sizeof(ixROM_SW_DATA_33)/sizeof(ixROM_SW_DATA_33[0]), 0, 0 },
+	{ "ixROM_SW_DATA_34", REG_SMC, 0xc06000ac, &ixROM_SW_DATA_34[0], sizeof(ixROM_SW_DATA_34)/sizeof(ixROM_SW_DATA_34[0]), 0, 0 },
+	{ "ixROM_SW_DATA_35", REG_SMC, 0xc06000b0, &ixROM_SW_DATA_35[0], sizeof(ixROM_SW_DATA_35)/sizeof(ixROM_SW_DATA_35[0]), 0, 0 },
+	{ "ixROM_SW_DATA_36", REG_SMC, 0xc06000b4, &ixROM_SW_DATA_36[0], sizeof(ixROM_SW_DATA_36)/sizeof(ixROM_SW_DATA_36[0]), 0, 0 },
+	{ "ixROM_SW_DATA_37", REG_SMC, 0xc06000b8, &ixROM_SW_DATA_37[0], sizeof(ixROM_SW_DATA_37)/sizeof(ixROM_SW_DATA_37[0]), 0, 0 },
+	{ "ixROM_SW_DATA_38", REG_SMC, 0xc06000bc, &ixROM_SW_DATA_38[0], sizeof(ixROM_SW_DATA_38)/sizeof(ixROM_SW_DATA_38[0]), 0, 0 },
+	{ "ixROM_SW_DATA_39", REG_SMC, 0xc06000c0, &ixROM_SW_DATA_39[0], sizeof(ixROM_SW_DATA_39)/sizeof(ixROM_SW_DATA_39[0]), 0, 0 },
+	{ "ixROM_SW_DATA_40", REG_SMC, 0xc06000c4, &ixROM_SW_DATA_40[0], sizeof(ixROM_SW_DATA_40)/sizeof(ixROM_SW_DATA_40[0]), 0, 0 },
+	{ "ixROM_SW_DATA_41", REG_SMC, 0xc06000c8, &ixROM_SW_DATA_41[0], sizeof(ixROM_SW_DATA_41)/sizeof(ixROM_SW_DATA_41[0]), 0, 0 },
+	{ "ixROM_SW_DATA_42", REG_SMC, 0xc06000cc, &ixROM_SW_DATA_42[0], sizeof(ixROM_SW_DATA_42)/sizeof(ixROM_SW_DATA_42[0]), 0, 0 },
+	{ "ixROM_SW_DATA_43", REG_SMC, 0xc06000d0, &ixROM_SW_DATA_43[0], sizeof(ixROM_SW_DATA_43)/sizeof(ixROM_SW_DATA_43[0]), 0, 0 },
+	{ "ixROM_SW_DATA_44", REG_SMC, 0xc06000d4, &ixROM_SW_DATA_44[0], sizeof(ixROM_SW_DATA_44)/sizeof(ixROM_SW_DATA_44[0]), 0, 0 },
+	{ "ixROM_SW_DATA_45", REG_SMC, 0xc06000d8, &ixROM_SW_DATA_45[0], sizeof(ixROM_SW_DATA_45)/sizeof(ixROM_SW_DATA_45[0]), 0, 0 },
+	{ "ixROM_SW_DATA_46", REG_SMC, 0xc06000dc, &ixROM_SW_DATA_46[0], sizeof(ixROM_SW_DATA_46)/sizeof(ixROM_SW_DATA_46[0]), 0, 0 },
+	{ "ixROM_SW_DATA_47", REG_SMC, 0xc06000e0, &ixROM_SW_DATA_47[0], sizeof(ixROM_SW_DATA_47)/sizeof(ixROM_SW_DATA_47[0]), 0, 0 },
+	{ "ixROM_SW_DATA_48", REG_SMC, 0xc06000e4, &ixROM_SW_DATA_48[0], sizeof(ixROM_SW_DATA_48)/sizeof(ixROM_SW_DATA_48[0]), 0, 0 },
+	{ "ixROM_SW_DATA_49", REG_SMC, 0xc06000e8, &ixROM_SW_DATA_49[0], sizeof(ixROM_SW_DATA_49)/sizeof(ixROM_SW_DATA_49[0]), 0, 0 },
+	{ "ixROM_SW_DATA_50", REG_SMC, 0xc06000ec, &ixROM_SW_DATA_50[0], sizeof(ixROM_SW_DATA_50)/sizeof(ixROM_SW_DATA_50[0]), 0, 0 },
+	{ "ixROM_SW_DATA_51", REG_SMC, 0xc06000f0, &ixROM_SW_DATA_51[0], sizeof(ixROM_SW_DATA_51)/sizeof(ixROM_SW_DATA_51[0]), 0, 0 },
+	{ "ixROM_SW_DATA_52", REG_SMC, 0xc06000f4, &ixROM_SW_DATA_52[0], sizeof(ixROM_SW_DATA_52)/sizeof(ixROM_SW_DATA_52[0]), 0, 0 },
+	{ "ixROM_SW_DATA_53", REG_SMC, 0xc06000f8, &ixROM_SW_DATA_53[0], sizeof(ixROM_SW_DATA_53)/sizeof(ixROM_SW_DATA_53[0]), 0, 0 },
+	{ "ixROM_SW_DATA_54", REG_SMC, 0xc06000fc, &ixROM_SW_DATA_54[0], sizeof(ixROM_SW_DATA_54)/sizeof(ixROM_SW_DATA_54[0]), 0, 0 },
+	{ "ixROM_SW_DATA_55", REG_SMC, 0xc0600100, &ixROM_SW_DATA_55[0], sizeof(ixROM_SW_DATA_55)/sizeof(ixROM_SW_DATA_55[0]), 0, 0 },
+	{ "ixROM_SW_DATA_56", REG_SMC, 0xc0600104, &ixROM_SW_DATA_56[0], sizeof(ixROM_SW_DATA_56)/sizeof(ixROM_SW_DATA_56[0]), 0, 0 },
+	{ "ixROM_SW_DATA_57", REG_SMC, 0xc0600108, &ixROM_SW_DATA_57[0], sizeof(ixROM_SW_DATA_57)/sizeof(ixROM_SW_DATA_57[0]), 0, 0 },
+	{ "ixROM_SW_DATA_58", REG_SMC, 0xc060010c, &ixROM_SW_DATA_58[0], sizeof(ixROM_SW_DATA_58)/sizeof(ixROM_SW_DATA_58[0]), 0, 0 },
+	{ "ixROM_SW_DATA_59", REG_SMC, 0xc0600110, &ixROM_SW_DATA_59[0], sizeof(ixROM_SW_DATA_59)/sizeof(ixROM_SW_DATA_59[0]), 0, 0 },
+	{ "ixROM_SW_DATA_60", REG_SMC, 0xc0600114, &ixROM_SW_DATA_60[0], sizeof(ixROM_SW_DATA_60)/sizeof(ixROM_SW_DATA_60[0]), 0, 0 },
+	{ "ixROM_SW_DATA_61", REG_SMC, 0xc0600118, &ixROM_SW_DATA_61[0], sizeof(ixROM_SW_DATA_61)/sizeof(ixROM_SW_DATA_61[0]), 0, 0 },
+	{ "ixROM_SW_DATA_62", REG_SMC, 0xc060011c, &ixROM_SW_DATA_62[0], sizeof(ixROM_SW_DATA_62)/sizeof(ixROM_SW_DATA_62[0]), 0, 0 },
+	{ "ixROM_SW_DATA_63", REG_SMC, 0xc0600120, &ixROM_SW_DATA_63[0], sizeof(ixROM_SW_DATA_63)/sizeof(ixROM_SW_DATA_63[0]), 0, 0 },
+	{ "ixROM_SW_DATA_64", REG_SMC, 0xc0600124, &ixROM_SW_DATA_64[0], sizeof(ixROM_SW_DATA_64)/sizeof(ixROM_SW_DATA_64[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, &ixCG_THERMAL_INT_ENA[0], sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, &ixCG_THERMAL_INT_CTRL[0], sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, &ixCG_THERMAL_INT_STATUS[0], sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
+	{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, &ixSMU_MAIN_PLL_OP_FREQ[0], sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
+	{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
+	{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
+	{ "ixSMU_INPUT_DATA", REG_SMC, 0xe00030b8, &ixSMU_INPUT_DATA[0], sizeof(ixSMU_INPUT_DATA)/sizeof(ixSMU_INPUT_DATA[0]), 0, 0 },
diff --git a/src/lib/ip/smu712.c b/src/lib/ip/smu712.c
new file mode 100644
index 0000000..45b1b1e
--- /dev/null
+++ b/src/lib/ip/smu712.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "smu712_bits.i"
+
+static const struct umr_reg smu712_registers[] = {
+#include "smu712_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_smu712(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "smu712";
+	ip->no_regs = sizeof(smu712_registers)/sizeof(smu712_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(smu712_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, smu712_registers, sizeof(smu712_registers));
+	return ip;
+}
diff --git a/src/lib/ip/smu712_bits.i b/src/lib/ip/smu712_bits.i
new file mode 100644
index 0000000..2c5af08
--- /dev/null
+++ b/src/lib/ip/smu712_bits.i
@@ -0,0 +1,5317 @@
+static struct umr_bitfield mmGPIOPAD_SW_INT_STAT[] = {
+	 { "SW_INT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_STRENGTH[] = {
+	 { "GPIO_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GPIO_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_MASK[] = {
+	 { "GPIO_MASK", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_A[] = {
+	 { "GPIO_A", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EN[] = {
+	 { "GPIO_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_Y[] = {
+	 { "GPIO_Y", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PINSTRAPS[] = {
+	 { "GPIO_PINSTRAP_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_28", 28, 28, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_29", 29, 29, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_30", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_EN[] = {
+	 { "GPIO_INT_STAT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT[] = {
+	 { "GPIO_INT_STAT", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_AK[] = {
+	 { "GPIO_INT_STAT_AK_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_28", 28, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_AK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_EN[] = {
+	 { "GPIO_INT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_TYPE[] = {
+	 { "GPIO_INT_TYPE", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_POLARITY[] = {
+	 { "GPIO_INT_POLARITY", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_POLARITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EXTERN_TRIG_CNTL[] = {
+	 { "EXTERN_TRIG_SEL", 0, 4, &umr_bitfield_default },
+	 { "EXTERN_TRIG_CLR", 5, 5, &umr_bitfield_default },
+	 { "EXTERN_TRIG_READ", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_RCVR_SEL[] = {
+	 { "GPIO_RCVR_SEL", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PU_EN[] = {
+	 { "GPIO_PU_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PD_EN[] = {
+	 { "GPIO_PD_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCG_FPS_CNT[] = {
+	 { "FPS_CNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_1[] = {
+	 { "GraphicsPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_2[] = {
+	 { "GraphicsPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_3[] = {
+	 { "GraphicsPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_4[] = {
+	 { "GraphicsPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_5[] = {
+	 { "GraphicsPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_6[] = {
+	 { "GraphicsPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_7[] = {
+	 { "GraphicsPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_8[] = {
+	 { "GraphicsPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_9[] = {
+	 { "GraphicsPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_10[] = {
+	 { "MemoryPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_11[] = {
+	 { "MemoryPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_12[] = {
+	 { "MemoryPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_13[] = {
+	 { "MemoryPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_14[] = {
+	 { "MemoryPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_15[] = {
+	 { "MemoryPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_16[] = {
+	 { "MemoryPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_17[] = {
+	 { "MemoryPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_18[] = {
+	 { "MemoryPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_19[] = {
+	 { "LinkPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_20[] = {
+	 { "LinkPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_21[] = {
+	 { "LinkPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_22[] = {
+	 { "LinkPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_23[] = {
+	 { "LinkPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_24[] = {
+	 { "LinkPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_25[] = {
+	 { "LinkPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_26[] = {
+	 { "LinkPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_27[] = {
+	 { "LinkPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_28[] = {
+	 { "SystemFlags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_29[] = {
+	 { "VRConfig", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_30[] = {
+	 { "SmioMask1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_31[] = {
+	 { "SmioMask2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_32[] = {
+	 { "SmioTable1_Pattern_0_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_33[] = {
+	 { "SmioTable1_Pattern_1_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_34[] = {
+	 { "SmioTable1_Pattern_2_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_35[] = {
+	 { "SmioTable1_Pattern_3_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_36[] = {
+	 { "SmioTable2_Pattern_0_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_37[] = {
+	 { "SmioTable2_Pattern_1_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_38[] = {
+	 { "SmioTable2_Pattern_2_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_39[] = {
+	 { "SmioTable2_Pattern_3_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_40[] = {
+	 { "VddcLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_41[] = {
+	 { "VddciLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_42[] = {
+	 { "VddGfxLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_43[] = {
+	 { "MvddLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_44[] = {
+	 { "VddcTable_1", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_45[] = {
+	 { "VddcTable_3", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_46[] = {
+	 { "VddcTable_5", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_4", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_47[] = {
+	 { "VddcTable_7", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_6", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_48[] = {
+	 { "VddcTable_9", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_49[] = {
+	 { "VddcTable_11", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_10", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_50[] = {
+	 { "VddcTable_13", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_51[] = {
+	 { "VddcTable_15", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_52[] = {
+	 { "VddGfxTable_1", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_53[] = {
+	 { "VddGfxTable_3", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_54[] = {
+	 { "VddGfxTable_5", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_4", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_55[] = {
+	 { "VddGfxTable_7", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_6", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_56[] = {
+	 { "VddGfxTable_9", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_57[] = {
+	 { "VddGfxTable_11", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_10", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_58[] = {
+	 { "VddGfxTable_13", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_59[] = {
+	 { "VddGfxTable_15", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_60[] = {
+	 { "VddciTable_1", 0, 15, &umr_bitfield_default },
+	 { "VddciTable_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_61[] = {
+	 { "VddciTable_3", 0, 15, &umr_bitfield_default },
+	 { "VddciTable_2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_62[] = {
+	 { "VddciTable_5", 0, 15, &umr_bitfield_default },
+	 { "VddciTable_4", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_63[] = {
+	 { "VddciTable_7", 0, 15, &umr_bitfield_default },
+	 { "VddciTable_6", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_64[] = {
+	 { "BapmVddGfxVidHiSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_65[] = {
+	 { "BapmVddGfxVidHiSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_66[] = {
+	 { "BapmVddGfxVidHiSidd_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_67[] = {
+	 { "BapmVddGfxVidHiSidd_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_68[] = {
+	 { "BapmVddGfxVidLoSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_69[] = {
+	 { "BapmVddGfxVidLoSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_70[] = {
+	 { "BapmVddGfxVidLoSidd_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_71[] = {
+	 { "BapmVddGfxVidLoSidd_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_72[] = {
+	 { "BapmVddGfxVidHiSidd2_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_73[] = {
+	 { "BapmVddGfxVidHiSidd2_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_74[] = {
+	 { "BapmVddGfxVidHiSidd2_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_75[] = {
+	 { "BapmVddGfxVidHiSidd2_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_76[] = {
+	 { "BapmVddcVidHiSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_77[] = {
+	 { "BapmVddcVidHiSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_78[] = {
+	 { "BapmVddcVidHiSidd_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_79[] = {
+	 { "BapmVddcVidHiSidd_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_80[] = {
+	 { "BapmVddcVidLoSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_81[] = {
+	 { "BapmVddcVidLoSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_82[] = {
+	 { "BapmVddcVidLoSidd_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_83[] = {
+	 { "BapmVddcVidLoSidd_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_84[] = {
+	 { "BapmVddcVidHiSidd2_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_85[] = {
+	 { "BapmVddcVidHiSidd2_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_86[] = {
+	 { "BapmVddcVidHiSidd2_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_87[] = {
+	 { "BapmVddcVidHiSidd2_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_88[] = {
+	 { "MasterDeepSleepControl", 0, 7, &umr_bitfield_default },
+	 { "LinkLevelCount", 8, 15, &umr_bitfield_default },
+	 { "MemoryDpmLevelCount", 16, 23, &umr_bitfield_default },
+	 { "GraphicsDpmLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_89[] = {
+	 { "SamuLevelCount", 0, 7, &umr_bitfield_default },
+	 { "AcpLevelCount", 8, 15, &umr_bitfield_default },
+	 { "VceLevelCount", 16, 23, &umr_bitfield_default },
+	 { "UvdLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_90[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_91[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_92[] = {
+	 { "Reserved_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_93[] = {
+	 { "Reserved_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_94[] = {
+	 { "Reserved_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_95[] = {
+	 { "GraphicsLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_96[] = {
+	 { "GraphicsLevel_0_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_97[] = {
+	 { "GraphicsLevel_0_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_98[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_99[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_100[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_101[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_102[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_103[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_104[] = {
+	 { "GraphicsLevel_0_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_105[] = {
+	 { "GraphicsLevel_0_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_106[] = {
+	 { "GraphicsLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_107[] = {
+	 { "GraphicsLevel_1_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_108[] = {
+	 { "GraphicsLevel_1_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_109[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_110[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_111[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_112[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_113[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_114[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_115[] = {
+	 { "GraphicsLevel_1_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_116[] = {
+	 { "GraphicsLevel_1_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_117[] = {
+	 { "GraphicsLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_118[] = {
+	 { "GraphicsLevel_2_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_119[] = {
+	 { "GraphicsLevel_2_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_120[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_121[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_122[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_123[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_124[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_125[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_126[] = {
+	 { "GraphicsLevel_2_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_127[] = {
+	 { "GraphicsLevel_2_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_128[] = {
+	 { "GraphicsLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_129[] = {
+	 { "GraphicsLevel_3_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_130[] = {
+	 { "GraphicsLevel_3_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_131[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_132[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_133[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_134[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_135[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_136[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_137[] = {
+	 { "GraphicsLevel_3_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_138[] = {
+	 { "GraphicsLevel_3_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_139[] = {
+	 { "GraphicsLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_140[] = {
+	 { "GraphicsLevel_4_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_141[] = {
+	 { "GraphicsLevel_4_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_142[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_143[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_144[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_145[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_146[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_147[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_148[] = {
+	 { "GraphicsLevel_4_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_149[] = {
+	 { "GraphicsLevel_4_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_150[] = {
+	 { "GraphicsLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_151[] = {
+	 { "GraphicsLevel_5_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_152[] = {
+	 { "GraphicsLevel_5_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_153[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_154[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_155[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_156[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_157[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_158[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_159[] = {
+	 { "GraphicsLevel_5_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_160[] = {
+	 { "GraphicsLevel_5_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_161[] = {
+	 { "GraphicsLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_162[] = {
+	 { "GraphicsLevel_6_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_163[] = {
+	 { "GraphicsLevel_6_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_164[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_165[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_166[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_167[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_168[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_169[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_170[] = {
+	 { "GraphicsLevel_6_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_171[] = {
+	 { "GraphicsLevel_6_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_172[] = {
+	 { "GraphicsLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_173[] = {
+	 { "GraphicsLevel_7_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_174[] = {
+	 { "GraphicsLevel_7_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_175[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_176[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_177[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_178[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_179[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_180[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_181[] = {
+	 { "GraphicsLevel_7_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_182[] = {
+	 { "GraphicsLevel_7_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_183[] = {
+	 { "MemoryACPILevel_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_184[] = {
+	 { "MemoryACPILevel_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_185[] = {
+	 { "MemoryACPILevel_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_186[] = {
+	 { "MemoryACPILevel_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_187[] = {
+	 { "MemoryACPILevel_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_188[] = {
+	 { "MemoryACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_189[] = {
+	 { "MemoryACPILevel_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_190[] = {
+	 { "MemoryACPILevel_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_191[] = {
+	 { "MemoryACPILevel_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_192[] = {
+	 { "MemoryACPILevel_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_193[] = {
+	 { "MemoryACPILevel_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_194[] = {
+	 { "MemoryACPILevel_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_195[] = {
+	 { "MemoryACPILevel_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_196[] = {
+	 { "MemoryACPILevel_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_197[] = {
+	 { "MemoryACPILevel_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_198[] = {
+	 { "MemoryACPILevel_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_199[] = {
+	 { "MemoryLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_200[] = {
+	 { "MemoryLevel_0_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_201[] = {
+	 { "MemoryLevel_0_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_202[] = {
+	 { "MemoryLevel_0_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_203[] = {
+	 { "MemoryLevel_0_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_204[] = {
+	 { "MemoryLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_205[] = {
+	 { "MemoryLevel_0_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_206[] = {
+	 { "MemoryLevel_0_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_207[] = {
+	 { "MemoryLevel_0_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_208[] = {
+	 { "MemoryLevel_0_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_209[] = {
+	 { "MemoryLevel_0_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_210[] = {
+	 { "MemoryLevel_0_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_211[] = {
+	 { "MemoryLevel_0_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_212[] = {
+	 { "MemoryLevel_0_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_213[] = {
+	 { "MemoryLevel_0_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_214[] = {
+	 { "MemoryLevel_0_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_215[] = {
+	 { "MemoryLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_216[] = {
+	 { "MemoryLevel_1_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_217[] = {
+	 { "MemoryLevel_1_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_218[] = {
+	 { "MemoryLevel_1_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_219[] = {
+	 { "MemoryLevel_1_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_220[] = {
+	 { "MemoryLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_221[] = {
+	 { "MemoryLevel_1_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_222[] = {
+	 { "MemoryLevel_1_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_223[] = {
+	 { "MemoryLevel_1_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_224[] = {
+	 { "MemoryLevel_1_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_225[] = {
+	 { "MemoryLevel_1_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_226[] = {
+	 { "MemoryLevel_1_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_227[] = {
+	 { "MemoryLevel_1_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_228[] = {
+	 { "MemoryLevel_1_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_229[] = {
+	 { "MemoryLevel_1_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_230[] = {
+	 { "MemoryLevel_1_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_231[] = {
+	 { "MemoryLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_232[] = {
+	 { "MemoryLevel_2_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_233[] = {
+	 { "MemoryLevel_2_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_234[] = {
+	 { "MemoryLevel_2_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_235[] = {
+	 { "MemoryLevel_2_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_236[] = {
+	 { "MemoryLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_237[] = {
+	 { "MemoryLevel_2_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_238[] = {
+	 { "MemoryLevel_2_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_239[] = {
+	 { "MemoryLevel_2_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_240[] = {
+	 { "MemoryLevel_2_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_241[] = {
+	 { "MemoryLevel_2_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_242[] = {
+	 { "MemoryLevel_2_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_243[] = {
+	 { "MemoryLevel_2_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_244[] = {
+	 { "MemoryLevel_2_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_245[] = {
+	 { "MemoryLevel_2_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_246[] = {
+	 { "MemoryLevel_2_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_247[] = {
+	 { "MemoryLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_248[] = {
+	 { "MemoryLevel_3_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_249[] = {
+	 { "MemoryLevel_3_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_250[] = {
+	 { "MemoryLevel_3_StutterEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_RttEnable", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_EdcWriteEnable", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_EdcReadEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_251[] = {
+	 { "MemoryLevel_3_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_StrobeRatio", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_StrobeEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_252[] = {
+	 { "MemoryLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_253[] = {
+	 { "MemoryLevel_3_padding1", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_254[] = {
+	 { "MemoryLevel_3_MpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_255[] = {
+	 { "MemoryLevel_3_MpllFuncCntl_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_256[] = {
+	 { "MemoryLevel_3_MpllFuncCntl_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_257[] = {
+	 { "MemoryLevel_3_MpllAdFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_258[] = {
+	 { "MemoryLevel_3_MpllDqFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_259[] = {
+	 { "MemoryLevel_3_MclkPwrmgtCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_260[] = {
+	 { "MemoryLevel_3_DllCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_261[] = {
+	 { "MemoryLevel_3_MpllSs1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_262[] = {
+	 { "MemoryLevel_3_MpllSs2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_263[] = {
+	 { "LinkLevel_0_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_264[] = {
+	 { "LinkLevel_0_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_265[] = {
+	 { "LinkLevel_0_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_266[] = {
+	 { "LinkLevel_0_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_267[] = {
+	 { "LinkLevel_1_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_268[] = {
+	 { "LinkLevel_1_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_269[] = {
+	 { "LinkLevel_1_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_270[] = {
+	 { "LinkLevel_1_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_271[] = {
+	 { "LinkLevel_2_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_272[] = {
+	 { "LinkLevel_2_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_273[] = {
+	 { "LinkLevel_2_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_274[] = {
+	 { "LinkLevel_2_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_275[] = {
+	 { "LinkLevel_3_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_276[] = {
+	 { "LinkLevel_3_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_277[] = {
+	 { "LinkLevel_3_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_278[] = {
+	 { "LinkLevel_3_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_279[] = {
+	 { "LinkLevel_4_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_280[] = {
+	 { "LinkLevel_4_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_281[] = {
+	 { "LinkLevel_4_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_282[] = {
+	 { "LinkLevel_4_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_283[] = {
+	 { "LinkLevel_5_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_284[] = {
+	 { "LinkLevel_5_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_285[] = {
+	 { "LinkLevel_5_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_286[] = {
+	 { "LinkLevel_5_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_287[] = {
+	 { "LinkLevel_6_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_288[] = {
+	 { "LinkLevel_6_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_289[] = {
+	 { "LinkLevel_6_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_290[] = {
+	 { "LinkLevel_6_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_291[] = {
+	 { "LinkLevel_7_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_292[] = {
+	 { "LinkLevel_7_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_293[] = {
+	 { "LinkLevel_7_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_294[] = {
+	 { "LinkLevel_7_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_295[] = {
+	 { "ACPILevel_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_296[] = {
+	 { "ACPILevel_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_297[] = {
+	 { "ACPILevel_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_298[] = {
+	 { "ACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_299[] = {
+	 { "ACPILevel_CgSpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_300[] = {
+	 { "ACPILevel_CgSpllFuncCntl2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_301[] = {
+	 { "ACPILevel_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_302[] = {
+	 { "ACPILevel_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_303[] = {
+	 { "ACPILevel_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_304[] = {
+	 { "ACPILevel_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_305[] = {
+	 { "ACPILevel_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_306[] = {
+	 { "ACPILevel_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_307[] = {
+	 { "UvdLevel_0_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_308[] = {
+	 { "UvdLevel_0_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_309[] = {
+	 { "UvdLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_310[] = {
+	 { "UvdLevel_0_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_0_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_311[] = {
+	 { "UvdLevel_1_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_312[] = {
+	 { "UvdLevel_1_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_313[] = {
+	 { "UvdLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_314[] = {
+	 { "UvdLevel_1_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_1_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_315[] = {
+	 { "UvdLevel_2_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_316[] = {
+	 { "UvdLevel_2_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_317[] = {
+	 { "UvdLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_318[] = {
+	 { "UvdLevel_2_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_2_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_319[] = {
+	 { "UvdLevel_3_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_320[] = {
+	 { "UvdLevel_3_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_321[] = {
+	 { "UvdLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_322[] = {
+	 { "UvdLevel_3_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_3_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_323[] = {
+	 { "UvdLevel_4_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_324[] = {
+	 { "UvdLevel_4_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_325[] = {
+	 { "UvdLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_326[] = {
+	 { "UvdLevel_4_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_4_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_327[] = {
+	 { "UvdLevel_5_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_328[] = {
+	 { "UvdLevel_5_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_329[] = {
+	 { "UvdLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_330[] = {
+	 { "UvdLevel_5_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_5_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_331[] = {
+	 { "UvdLevel_6_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_332[] = {
+	 { "UvdLevel_6_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_333[] = {
+	 { "UvdLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_334[] = {
+	 { "UvdLevel_6_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_6_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_335[] = {
+	 { "UvdLevel_7_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_336[] = {
+	 { "UvdLevel_7_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_337[] = {
+	 { "UvdLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_338[] = {
+	 { "UvdLevel_7_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_7_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_339[] = {
+	 { "VceLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_340[] = {
+	 { "VceLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_341[] = {
+	 { "VceLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_0_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_342[] = {
+	 { "VceLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_343[] = {
+	 { "VceLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_344[] = {
+	 { "VceLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_1_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_345[] = {
+	 { "VceLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_346[] = {
+	 { "VceLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_347[] = {
+	 { "VceLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_2_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_348[] = {
+	 { "VceLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_349[] = {
+	 { "VceLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_350[] = {
+	 { "VceLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_3_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_351[] = {
+	 { "VceLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_352[] = {
+	 { "VceLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_353[] = {
+	 { "VceLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_4_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_354[] = {
+	 { "VceLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_355[] = {
+	 { "VceLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_356[] = {
+	 { "VceLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_5_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_357[] = {
+	 { "VceLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_358[] = {
+	 { "VceLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_359[] = {
+	 { "VceLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_6_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_360[] = {
+	 { "VceLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_361[] = {
+	 { "VceLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_362[] = {
+	 { "VceLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_7_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_363[] = {
+	 { "AcpLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_364[] = {
+	 { "AcpLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_365[] = {
+	 { "AcpLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_0_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_366[] = {
+	 { "AcpLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_367[] = {
+	 { "AcpLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_368[] = {
+	 { "AcpLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_1_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_369[] = {
+	 { "AcpLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_370[] = {
+	 { "AcpLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_371[] = {
+	 { "AcpLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_2_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_372[] = {
+	 { "AcpLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_373[] = {
+	 { "AcpLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_374[] = {
+	 { "AcpLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_3_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_375[] = {
+	 { "AcpLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_376[] = {
+	 { "AcpLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_377[] = {
+	 { "AcpLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_4_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_378[] = {
+	 { "AcpLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_379[] = {
+	 { "AcpLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_380[] = {
+	 { "AcpLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_5_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_381[] = {
+	 { "AcpLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_382[] = {
+	 { "AcpLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_383[] = {
+	 { "AcpLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_6_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_384[] = {
+	 { "AcpLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_385[] = {
+	 { "AcpLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_386[] = {
+	 { "AcpLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_7_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_387[] = {
+	 { "SamuLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_388[] = {
+	 { "SamuLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_389[] = {
+	 { "SamuLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_0_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_390[] = {
+	 { "SamuLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_391[] = {
+	 { "SamuLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_392[] = {
+	 { "SamuLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_1_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_393[] = {
+	 { "SamuLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_394[] = {
+	 { "SamuLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_395[] = {
+	 { "SamuLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_2_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_396[] = {
+	 { "SamuLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_397[] = {
+	 { "SamuLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_398[] = {
+	 { "SamuLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_3_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_399[] = {
+	 { "SamuLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_400[] = {
+	 { "SamuLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_401[] = {
+	 { "SamuLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_4_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_402[] = {
+	 { "SamuLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_403[] = {
+	 { "SamuLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_404[] = {
+	 { "SamuLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_5_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_405[] = {
+	 { "SamuLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_406[] = {
+	 { "SamuLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_407[] = {
+	 { "SamuLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_6_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_408[] = {
+	 { "SamuLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_409[] = {
+	 { "SamuLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_410[] = {
+	 { "SamuLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_7_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_411[] = {
+	 { "Ulv_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_412[] = {
+	 { "Ulv_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_413[] = {
+	 { "Ulv_VddcPhase", 0, 7, &umr_bitfield_default },
+	 { "Ulv_VddcOffsetVid", 8, 15, &umr_bitfield_default },
+	 { "Ulv_VddcOffset", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_414[] = {
+	 { "Ulv_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_415[] = {
+	 { "SclkStepSize", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_416[] = {
+	 { "Smio_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_417[] = {
+	 { "Smio_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_418[] = {
+	 { "Smio_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_419[] = {
+	 { "Smio_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_420[] = {
+	 { "Smio_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_421[] = {
+	 { "Smio_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_422[] = {
+	 { "Smio_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_423[] = {
+	 { "Smio_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_424[] = {
+	 { "Smio_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_425[] = {
+	 { "Smio_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_426[] = {
+	 { "Smio_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_427[] = {
+	 { "Smio_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_428[] = {
+	 { "Smio_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_429[] = {
+	 { "Smio_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_430[] = {
+	 { "Smio_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_431[] = {
+	 { "Smio_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_432[] = {
+	 { "Smio_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_433[] = {
+	 { "Smio_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_434[] = {
+	 { "Smio_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_435[] = {
+	 { "Smio_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_436[] = {
+	 { "Smio_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_437[] = {
+	 { "Smio_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_438[] = {
+	 { "Smio_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_439[] = {
+	 { "Smio_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_440[] = {
+	 { "Smio_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_441[] = {
+	 { "Smio_25", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_442[] = {
+	 { "Smio_26", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_443[] = {
+	 { "Smio_27", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_444[] = {
+	 { "Smio_28", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_445[] = {
+	 { "Smio_29", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_446[] = {
+	 { "Smio_30", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_447[] = {
+	 { "Smio_31", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_448[] = {
+	 { "SamuBootLevel", 0, 7, &umr_bitfield_default },
+	 { "AcpBootLevel", 8, 15, &umr_bitfield_default },
+	 { "VceBootLevel", 16, 23, &umr_bitfield_default },
+	 { "UvdBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_449[] = {
+	 { "GraphicsInterval", 0, 7, &umr_bitfield_default },
+	 { "GraphicsThermThrottleEnable", 8, 15, &umr_bitfield_default },
+	 { "GraphicsVoltageChangeEnable", 16, 23, &umr_bitfield_default },
+	 { "GraphicsBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_450[] = {
+	 { "TemperatureLimitHigh", 0, 15, &umr_bitfield_default },
+	 { "ThermalInterval", 16, 23, &umr_bitfield_default },
+	 { "VoltageInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_451[] = {
+	 { "MemoryVoltageChangeEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryBootLevel", 8, 15, &umr_bitfield_default },
+	 { "TemperatureLimitLow", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_452[] = {
+	 { "MemoryThermThrottleEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryInterval", 8, 15, &umr_bitfield_default },
+	 { "BootMVdd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_453[] = {
+	 { "PhaseResponseTime", 0, 15, &umr_bitfield_default },
+	 { "VoltageResponseTime", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_454[] = {
+	 { "DTEMode", 0, 7, &umr_bitfield_default },
+	 { "DTEInterval", 8, 15, &umr_bitfield_default },
+	 { "PCIeGenInterval", 16, 23, &umr_bitfield_default },
+	 { "PCIeBootLinkLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_455[] = {
+	 { "ThermGpio", 0, 7, &umr_bitfield_default },
+	 { "AcDcGpio", 8, 15, &umr_bitfield_default },
+	 { "VRHotGpio", 16, 23, &umr_bitfield_default },
+	 { "SVI2Enable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_456[] = {
+	 { "PPM_TemperatureLimit", 0, 15, &umr_bitfield_default },
+	 { "PPM_PkgPwrLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_457[] = {
+	 { "TargetTdp", 0, 15, &umr_bitfield_default },
+	 { "DefaultTdp", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_458[] = {
+	 { "FpsLowThreshold", 0, 15, &umr_bitfield_default },
+	 { "FpsHighThreshold", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_459[] = {
+	 { "BAPMTI_R_0_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_460[] = {
+	 { "BAPMTI_R_1_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_461[] = {
+	 { "BAPMTI_R_1_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_1_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_462[] = {
+	 { "BAPMTI_R_2_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_463[] = {
+	 { "BAPMTI_R_3_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_464[] = {
+	 { "BAPMTI_R_3_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_3_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_465[] = {
+	 { "BAPMTI_R_4_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_466[] = {
+	 { "BAPMTI_RC_0_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_467[] = {
+	 { "BAPMTI_RC_0_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_0_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_468[] = {
+	 { "BAPMTI_RC_1_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_469[] = {
+	 { "BAPMTI_RC_2_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_470[] = {
+	 { "BAPMTI_RC_2_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_2_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_471[] = {
+	 { "BAPMTI_RC_3_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_472[] = {
+	 { "BAPMTI_RC_4_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_473[] = {
+	 { "BAPMTI_RC_4_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_4_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_474[] = {
+	 { "GpuTjHyst", 0, 7, &umr_bitfield_default },
+	 { "GpuTjMax", 8, 15, &umr_bitfield_default },
+	 { "DTETjOffset", 16, 23, &umr_bitfield_default },
+	 { "DTEAmbientTempBase", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_475[] = {
+	 { "BootVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "BootVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "BootVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "BootVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_476[] = {
+	 { "BAPM_TEMP_GRADIENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_477[] = {
+	 { "LowSclkInterruptThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_478[] = {
+	 { "VddGfxReChkWait", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_479[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_480[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_481[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_482[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_483[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_484[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_485[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_486[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_487[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_488[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_489[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_490[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFIRMWARE_FLAGS[] = {
+	 { "INTERRUPTS_ENABLED", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 23, &umr_bitfield_default },
+	 { "TEST_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_STATUS[] = {
+	 { "VDD_Boost", 0, 7, &umr_bitfield_default },
+	 { "VDD_Throttle", 8, 15, &umr_bitfield_default },
+	 { "VDDC_Boost", 16, 23, &umr_bitfield_default },
+	 { "VDDC_Throttle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_MV_AVERAGE[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_VRM_LIMIT[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFEATURE_STATUS[] = {
+	 { "SCLK_DPM_ON", 0, 0, &umr_bitfield_default },
+	 { "MCLK_DPM_ON", 1, 1, &umr_bitfield_default },
+	 { "LCLK_DPM_ON", 2, 2, &umr_bitfield_default },
+	 { "UVD_DPM_ON", 3, 3, &umr_bitfield_default },
+	 { "VCE_DPM_ON", 4, 4, &umr_bitfield_default },
+	 { "ACP_DPM_ON", 5, 5, &umr_bitfield_default },
+	 { "SAMU_DPM_ON", 6, 6, &umr_bitfield_default },
+	 { "PCIE_DPM_ON", 7, 7, &umr_bitfield_default },
+	 { "BAPM_ON", 8, 8, &umr_bitfield_default },
+	 { "LPMX_ON", 9, 9, &umr_bitfield_default },
+	 { "NBDPM_ON", 10, 10, &umr_bitfield_default },
+	 { "LHTC_ON", 11, 11, &umr_bitfield_default },
+	 { "VPC_ON", 12, 12, &umr_bitfield_default },
+	 { "VOLTAGE_CONTROLLER_ON", 13, 13, &umr_bitfield_default },
+	 { "TDC_LIMIT_ON", 14, 14, &umr_bitfield_default },
+	 { "GPU_CAC_ON", 15, 15, &umr_bitfield_default },
+	 { "AVS_ON", 16, 16, &umr_bitfield_default },
+	 { "SPMI_ON", 17, 17, &umr_bitfield_default },
+	 { "SCLK_DPM_FORCED", 18, 18, &umr_bitfield_default },
+	 { "MCLK_DPM_FORCED", 19, 19, &umr_bitfield_default },
+	 { "LCLK_DPM_FORCED", 20, 20, &umr_bitfield_default },
+	 { "PCIE_DPM_FORCED", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixENTITY_TEMPERATURES_1[] = {
+	 { "GPU", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_1[] = {
+	 { "entries_0_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_2[] = {
+	 { "entries_0_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_3[] = {
+	 { "entries_0_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_4[] = {
+	 { "entries_0_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_5[] = {
+	 { "entries_0_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_6[] = {
+	 { "entries_0_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_7[] = {
+	 { "entries_0_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_8[] = {
+	 { "entries_0_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_9[] = {
+	 { "entries_0_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_10[] = {
+	 { "entries_0_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_11[] = {
+	 { "entries_0_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_12[] = {
+	 { "entries_0_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_13[] = {
+	 { "entries_1_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_14[] = {
+	 { "entries_1_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_15[] = {
+	 { "entries_1_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_16[] = {
+	 { "entries_1_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_17[] = {
+	 { "entries_1_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_18[] = {
+	 { "entries_1_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_19[] = {
+	 { "entries_1_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_20[] = {
+	 { "entries_1_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_21[] = {
+	 { "entries_1_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_22[] = {
+	 { "entries_1_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_23[] = {
+	 { "entries_1_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_24[] = {
+	 { "entries_1_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_25[] = {
+	 { "entries_2_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_26[] = {
+	 { "entries_2_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_27[] = {
+	 { "entries_2_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_28[] = {
+	 { "entries_2_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_29[] = {
+	 { "entries_2_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_30[] = {
+	 { "entries_2_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_31[] = {
+	 { "entries_2_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_32[] = {
+	 { "entries_2_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_33[] = {
+	 { "entries_2_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_34[] = {
+	 { "entries_2_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_35[] = {
+	 { "entries_2_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_36[] = {
+	 { "entries_2_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_37[] = {
+	 { "entries_3_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_38[] = {
+	 { "entries_3_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_39[] = {
+	 { "entries_3_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_40[] = {
+	 { "entries_3_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_41[] = {
+	 { "entries_3_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_42[] = {
+	 { "entries_3_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_43[] = {
+	 { "entries_3_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_44[] = {
+	 { "entries_3_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_45[] = {
+	 { "entries_3_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_46[] = {
+	 { "entries_3_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_47[] = {
+	 { "entries_3_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_48[] = {
+	 { "entries_3_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_49[] = {
+	 { "entries_4_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_50[] = {
+	 { "entries_4_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_51[] = {
+	 { "entries_4_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_52[] = {
+	 { "entries_4_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_53[] = {
+	 { "entries_4_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_54[] = {
+	 { "entries_4_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_55[] = {
+	 { "entries_4_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_56[] = {
+	 { "entries_4_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_57[] = {
+	 { "entries_4_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_58[] = {
+	 { "entries_4_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_59[] = {
+	 { "entries_4_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_60[] = {
+	 { "entries_4_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_61[] = {
+	 { "entries_5_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_62[] = {
+	 { "entries_5_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_63[] = {
+	 { "entries_5_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_64[] = {
+	 { "entries_5_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_65[] = {
+	 { "entries_5_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_66[] = {
+	 { "entries_5_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_67[] = {
+	 { "entries_5_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_68[] = {
+	 { "entries_5_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_69[] = {
+	 { "entries_5_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_70[] = {
+	 { "entries_5_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_71[] = {
+	 { "entries_5_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_72[] = {
+	 { "entries_5_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_73[] = {
+	 { "entries_6_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_74[] = {
+	 { "entries_6_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_75[] = {
+	 { "entries_6_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_76[] = {
+	 { "entries_6_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_77[] = {
+	 { "entries_6_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_78[] = {
+	 { "entries_6_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_79[] = {
+	 { "entries_6_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_80[] = {
+	 { "entries_6_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_81[] = {
+	 { "entries_6_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_82[] = {
+	 { "entries_6_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_83[] = {
+	 { "entries_6_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_84[] = {
+	 { "entries_6_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_85[] = {
+	 { "entries_7_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_86[] = {
+	 { "entries_7_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_87[] = {
+	 { "entries_7_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_88[] = {
+	 { "entries_7_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_89[] = {
+	 { "entries_7_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_90[] = {
+	 { "entries_7_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_91[] = {
+	 { "entries_7_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_92[] = {
+	 { "entries_7_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_93[] = {
+	 { "entries_7_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_94[] = {
+	 { "entries_7_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_95[] = {
+	 { "entries_7_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_96[] = {
+	 { "entries_7_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_1[] = {
+	 { "reserved_2", 0, 7, &umr_bitfield_default },
+	 { "reserved_1", 8, 15, &umr_bitfield_default },
+	 { "reserved_0", 16, 23, &umr_bitfield_default },
+	 { "last", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_2[] = {
+	 { "address_0_s1", 0, 15, &umr_bitfield_default },
+	 { "address_0_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_3[] = {
+	 { "address_1_s1", 0, 15, &umr_bitfield_default },
+	 { "address_1_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_4[] = {
+	 { "address_2_s1", 0, 15, &umr_bitfield_default },
+	 { "address_2_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_5[] = {
+	 { "address_3_s1", 0, 15, &umr_bitfield_default },
+	 { "address_3_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_6[] = {
+	 { "address_4_s1", 0, 15, &umr_bitfield_default },
+	 { "address_4_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_7[] = {
+	 { "address_5_s1", 0, 15, &umr_bitfield_default },
+	 { "address_5_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_8[] = {
+	 { "address_6_s1", 0, 15, &umr_bitfield_default },
+	 { "address_6_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_9[] = {
+	 { "address_7_s1", 0, 15, &umr_bitfield_default },
+	 { "address_7_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_10[] = {
+	 { "address_8_s1", 0, 15, &umr_bitfield_default },
+	 { "address_8_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_11[] = {
+	 { "address_9_s1", 0, 15, &umr_bitfield_default },
+	 { "address_9_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_12[] = {
+	 { "address_10_s1", 0, 15, &umr_bitfield_default },
+	 { "address_10_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_13[] = {
+	 { "address_11_s1", 0, 15, &umr_bitfield_default },
+	 { "address_11_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_14[] = {
+	 { "address_12_s1", 0, 15, &umr_bitfield_default },
+	 { "address_12_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_15[] = {
+	 { "address_13_s1", 0, 15, &umr_bitfield_default },
+	 { "address_13_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_16[] = {
+	 { "address_14_s1", 0, 15, &umr_bitfield_default },
+	 { "address_14_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_17[] = {
+	 { "address_15_s1", 0, 15, &umr_bitfield_default },
+	 { "address_15_s0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_18[] = {
+	 { "data_0_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_19[] = {
+	 { "data_0_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_20[] = {
+	 { "data_0_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_21[] = {
+	 { "data_0_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_22[] = {
+	 { "data_0_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_23[] = {
+	 { "data_0_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_24[] = {
+	 { "data_0_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_25[] = {
+	 { "data_0_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_26[] = {
+	 { "data_0_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_27[] = {
+	 { "data_0_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_28[] = {
+	 { "data_0_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_29[] = {
+	 { "data_0_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_30[] = {
+	 { "data_0_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_31[] = {
+	 { "data_0_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_32[] = {
+	 { "data_0_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_33[] = {
+	 { "data_0_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_34[] = {
+	 { "data_1_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_35[] = {
+	 { "data_1_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_36[] = {
+	 { "data_1_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_37[] = {
+	 { "data_1_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_38[] = {
+	 { "data_1_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_39[] = {
+	 { "data_1_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_40[] = {
+	 { "data_1_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_41[] = {
+	 { "data_1_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_42[] = {
+	 { "data_1_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_43[] = {
+	 { "data_1_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_44[] = {
+	 { "data_1_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_45[] = {
+	 { "data_1_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_46[] = {
+	 { "data_1_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_47[] = {
+	 { "data_1_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_48[] = {
+	 { "data_1_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_49[] = {
+	 { "data_1_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_50[] = {
+	 { "data_2_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_51[] = {
+	 { "data_2_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_52[] = {
+	 { "data_2_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_53[] = {
+	 { "data_2_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_54[] = {
+	 { "data_2_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_55[] = {
+	 { "data_2_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_56[] = {
+	 { "data_2_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_57[] = {
+	 { "data_2_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_58[] = {
+	 { "data_2_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_59[] = {
+	 { "data_2_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_60[] = {
+	 { "data_2_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_61[] = {
+	 { "data_2_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_62[] = {
+	 { "data_2_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_63[] = {
+	 { "data_2_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_64[] = {
+	 { "data_2_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_65[] = {
+	 { "data_2_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_66[] = {
+	 { "data_3_value_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_67[] = {
+	 { "data_3_value_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_68[] = {
+	 { "data_3_value_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_69[] = {
+	 { "data_3_value_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_70[] = {
+	 { "data_3_value_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_71[] = {
+	 { "data_3_value_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_72[] = {
+	 { "data_3_value_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_73[] = {
+	 { "data_3_value_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_74[] = {
+	 { "data_3_value_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_75[] = {
+	 { "data_3_value_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_76[] = {
+	 { "data_3_value_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_77[] = {
+	 { "data_3_value_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_78[] = {
+	 { "data_3_value_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_79[] = {
+	 { "data_3_value_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_80[] = {
+	 { "data_3_value_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMC_REGISTERS_TABLE_81[] = {
+	 { "data_3_value_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_1[] = {
+	 { "TempMin", 0, 15, &umr_bitfield_default },
+	 { "FdoMode", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_2[] = {
+	 { "TempMax", 0, 15, &umr_bitfield_default },
+	 { "TempMed", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_3[] = {
+	 { "Slope2", 0, 15, &umr_bitfield_default },
+	 { "Slope1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_4[] = {
+	 { "HystUp", 0, 15, &umr_bitfield_default },
+	 { "FdoMin", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_5[] = {
+	 { "HystSlope", 0, 15, &umr_bitfield_default },
+	 { "HystDown", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_6[] = {
+	 { "TempCurr", 0, 15, &umr_bitfield_default },
+	 { "TempRespLim", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_7[] = {
+	 { "PwmCurr", 0, 15, &umr_bitfield_default },
+	 { "SlopeCurr", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_8[] = {
+	 { "RefreshPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFAN_TABLE_9[] = {
+	 { "Padding", 0, 7, &umr_bitfield_default },
+	 { "TempSrc", 8, 15, &umr_bitfield_default },
+	 { "FdoMax", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_1[] = {
+	 { "RefClockFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_2[] = {
+	 { "PmTimerPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_3[] = {
+	 { "FeatureEnables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_4[] = {
+	 { "PreVBlankGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_5[] = {
+	 { "VBlankTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_6[] = {
+	 { "TrainTimeGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_7[] = {
+	 { "MvddSwitchTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_8[] = {
+	 { "LongestAcpiTrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_9[] = {
+	 { "AcpiDelay", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_10[] = {
+	 { "G5TrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_11[] = {
+	 { "DelayMpllPwron", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_12[] = {
+	 { "VoltageChangeTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_13[] = {
+	 { "HandshakeDisables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_14[] = {
+	 { "DisplayPhy4Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy3Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy2Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy1Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_15[] = {
+	 { "DisplayPhy8Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy7Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy6Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy5Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_16[] = {
+	 { "AverageGraphicsActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_17[] = {
+	 { "AverageMemoryActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_18[] = {
+	 { "AverageGioActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_19[] = {
+	 { "PCIeDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "LClkDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "MClkDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "SClkDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_20[] = {
+	 { "VCEDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "ACPDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "SAMUDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "UVDDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_21[] = {
+	 { "DRAM_LOG_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_22[] = {
+	 { "DRAM_LOG_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_23[] = {
+	 { "DRAM_LOG_PHY_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_24[] = {
+	 { "DRAM_LOG_PHY_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_25[] = {
+	 { "DRAM_LOG_BUFF_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_26[] = {
+	 { "UlvEnterCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_27[] = {
+	 { "UlvTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_28[] = {
+	 { "UcodeLoadStatus", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_29[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_30[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_1[] = {
+	 { "SviLoadLineOffsetVddC", 0, 7, &umr_bitfield_default },
+	 { "SviLoadLineTrimVddC", 8, 15, &umr_bitfield_default },
+	 { "SviLoadLineVddC", 16, 23, &umr_bitfield_default },
+	 { "SviLoadLineEn", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_2[] = {
+	 { "TDC_MAWt", 0, 7, &umr_bitfield_default },
+	 { "TDC_VDDC_ThrottleReleaseLimitPerc", 8, 15, &umr_bitfield_default },
+	 { "TDC_VDDC_PkgLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_3[] = {
+	 { "Reserved", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureMax", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureMin", 16, 23, &umr_bitfield_default },
+	 { "TdcWaterfallCtl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_4[] = {
+	 { "LPMLTemperatureScaler_3", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_2", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_1", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_5[] = {
+	 { "LPMLTemperatureScaler_7", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_6", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_5", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_6[] = {
+	 { "LPMLTemperatureScaler_11", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_10", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_9", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_7[] = {
+	 { "LPMLTemperatureScaler_15", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_14", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_13", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_8[] = {
+	 { "FuzzyFan_ErrorRateSetDelta", 0, 15, &umr_bitfield_default },
+	 { "FuzzyFan_ErrorSetDelta", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_9[] = {
+	 { "Reserved6", 0, 15, &umr_bitfield_default },
+	 { "FuzzyFan_PwmSetDelta", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_10[] = {
+	 { "GnbLPML_3", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_2", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_1", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_11[] = {
+	 { "GnbLPML_7", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_6", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_5", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_12[] = {
+	 { "GnbLPML_11", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_10", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_9", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_13[] = {
+	 { "GnbLPML_15", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_14", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_13", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_14[] = {
+	 { "Reserved1_1", 0, 7, &umr_bitfield_default },
+	 { "Reserved1_0", 8, 15, &umr_bitfield_default },
+	 { "GnbLPMLMinVid", 16, 23, &umr_bitfield_default },
+	 { "GnbLPMLMaxVid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_15[] = {
+	 { "BapmVddCBaseLeakageLoSidd", 0, 15, &umr_bitfield_default },
+	 { "BapmVddCBaseLeakageHiSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_16[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_17[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_18[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_19[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_20[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_21[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_22[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_24[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_25[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_26[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_27[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_28[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_29[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_30[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_31[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_32[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_33[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_34[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_35[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_36[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_37[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_38[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_39[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_40[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_41[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_42[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_43[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_44[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_46[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_47[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_48[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_49[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_50[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_51[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_52[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_53[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_54[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_55[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_56[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_57[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_58[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_59[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_60[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_61[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_62[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_63[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_64[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_65[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_66[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_67[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_68[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_69[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_70[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_71[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_72[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_73[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_74[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_75[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_76[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_77[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_78[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_79[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_80[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_81[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_82[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_83[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_84[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_85[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_86[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_87[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_88[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_89[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_90[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_91[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_92[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_93[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_94[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_95[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_96[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_97[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_98[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_99[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_100[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_101[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_102[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_103[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_104[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_105[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_106[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_107[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_108[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_109[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_110[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_111[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_112[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_113[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_114[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_115[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_116[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_117[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_118[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_119[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_120[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_121[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_122[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_123[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_124[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_125[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_126[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_127[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_RESET_CNTL[] = {
+	 { "rst_reg", 0, 0, &umr_bitfield_default },
+	 { "srbm_soft_rst_override", 1, 1, &umr_bitfield_default },
+	 { "RegReset", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_0[] = {
+	 { "ck_disable", 0, 0, &umr_bitfield_default },
+	 { "auto_cg_en", 1, 1, &umr_bitfield_default },
+	 { "auto_cg_timeout", 8, 23, &umr_bitfield_default },
+	 { "cken", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_1[] = {
+	 { "auto_ck_disable", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_2[] = {
+	 { "wake_on_irq", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_MISC_CNTL[] = {
+	 { "dma_no_outstanding", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_MSG_ARG_0[] = {
+	 { "smc_msg_arg", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_PC_C[] = {
+	 { "smc_pc_c", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SCRATCH9[] = {
+	 { "SCRATCH_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_ACCESS_CNTL[] = {
+	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_1", 1, 1, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_2", 2, 2, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_3", 3, 3, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_4", 4, 4, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_5", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_6", 6, 6, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_7", 7, 7, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_8", 8, 8, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_9", 9, 9, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_10", 10, 10, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_11", 11, 11, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_12", 12, 12, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_13", 13, 13, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_14", 14, 14, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_11[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_0[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_0[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_1[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_1[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_2[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_2[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_3[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_3[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_4[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_4[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_5[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_5[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_6[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_6[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_7[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_7[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_0[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_1[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_2[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_3[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_4[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_5[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_6[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_7[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_8[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_8[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_9[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_9[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_10[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_10[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_11[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_11[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_8[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_9[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_10[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_UC_EVENTS[] = {
+	 { "RCU_TST_jpc_rep_req", 0, 0, &umr_bitfield_default },
+	 { "TST_RCU_jpc_rep_done", 1, 1, &umr_bitfield_default },
+	 { "drv_rst_mode", 2, 2, &umr_bitfield_default },
+	 { "SMU_DC_efuse_status_invalid", 3, 3, &umr_bitfield_default },
+	 { "TP_Tester", 6, 6, &umr_bitfield_default },
+	 { "boot_seq_done", 7, 7, &umr_bitfield_default },
+	 { "sclk_deep_sleep_exit", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_ACTIVE", 9, 9, &umr_bitfield_default },
+	 { "BREAK_PT2_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "FCH_HALT", 11, 11, &umr_bitfield_default },
+	 { "RCU_GIO_fch_lockdown", 13, 13, &umr_bitfield_default },
+	 { "INTERRUPTS_ENABLED", 16, 16, &umr_bitfield_default },
+	 { "RCU_DtmCnt0_Done", 17, 17, &umr_bitfield_default },
+	 { "RCU_DtmCnt1_Done", 18, 18, &umr_bitfield_default },
+	 { "RCU_DtmCnt2_Done", 19, 19, &umr_bitfield_default },
+	 { "irq31_sel", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_MISC_CTRL[] = {
+	 { "REG_DRV_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "REG_RCU_MEMREP_DIS", 3, 3, &umr_bitfield_default },
+	 { "REG_CC_FUSE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "REG_SAMU_FUSE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "REG_CC_SRBM_RD_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_DONE", 16, 16, &umr_bitfield_default },
+	 { "BREAK_PT2_DONE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_START", 22, 22, &umr_bitfield_default },
+	 { "RST_PULSE_WIDTH", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_RCU_FUSES[] = {
+	 { "GPU_DIS", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "EFUSE_RD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "CG_RST_GLB_REQ_DIS", 5, 5, &umr_bitfield_default },
+	 { "DRV_RST_MODE", 6, 6, &umr_bitfield_default },
+	 { "ROM_DIS", 7, 7, &umr_bitfield_default },
+	 { "JPC_REP_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT1", 9, 9, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT2", 10, 10, &umr_bitfield_default },
+	 { "SMU_IOC_MST_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "FCH_LOCKOUT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "FCH_XFIRE_FILTER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XFIRE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_FUSE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "BIF_RST_POLLING_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "MEM_HARDREP_EN", 21, 21, &umr_bitfield_default },
+	 { "PCIE_INIT_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "DSMU_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "WRP_FUSE_VALID", 24, 24, &umr_bitfield_default },
+	 { "PHY_FUSE_VALID", 25, 25, &umr_bitfield_default },
+	 { "RCU_SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_MISC_FUSES[] = {
+	 { "IOMMU_V2_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "MinSClkDid", 2, 8, &umr_bitfield_default },
+	 { "MISC_SPARE", 9, 10, &umr_bitfield_default },
+	 { "PostResetGnbClkDid", 11, 17, &umr_bitfield_default },
+	 { "L2IMU_tn2_dtc_half", 18, 18, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_half", 19, 19, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_half", 20, 20, &umr_bitfield_default },
+	 { "L2IMU_tn2_pdc_half", 21, 21, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_dis", 22, 22, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_dis", 23, 23, &umr_bitfield_default },
+	 { "VCE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "IOC_IOMMU_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "GNB_SPARE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SCLK_VID_FUSES[] = {
+	 { "SClkVid0", 0, 7, &umr_bitfield_default },
+	 { "SClkVid1", 8, 15, &umr_bitfield_default },
+	 { "SClkVid2", 16, 23, &umr_bitfield_default },
+	 { "SClkVid3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOCCFG_FUSES[] = {
+	 { "NB_REV_ID", 1, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOC_FUSES[] = {
+	 { "IOC_FUSES", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_TST_EFUSE1_MISC[] = {
+	 { "RF_RM_6_2", 1, 5, &umr_bitfield_default },
+	 { "RME", 6, 6, &umr_bitfield_default },
+	 { "MBIST_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "HARD_REPAIR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SOFT_REPAIR_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "GPU_DIS", 10, 10, &umr_bitfield_default },
+	 { "SMS_PWRDWN_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "CRBBMP1500_DISA", 12, 12, &umr_bitfield_default },
+	 { "CRBBMP1500_DISB", 13, 13, &umr_bitfield_default },
+	 { "RM_RF8", 14, 14, &umr_bitfield_default },
+	 { "DFT_SPARE1", 22, 22, &umr_bitfield_default },
+	 { "DFT_SPARE2", 23, 23, &umr_bitfield_default },
+	 { "DFT_SPARE3", 24, 24, &umr_bitfield_default },
+	 { "VCE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "DCE_SCAN_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_TST_ID_STRAPS[] = {
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+	 { "ATI_REV_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_FCTRL_FUSES[] = {
+	 { "EXT_EFUSE_MACRO_PRESENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_HARVEST_FUSES[] = {
+	 { "VCE_DISABLE", 1, 2, &umr_bitfield_default },
+	 { "UVD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "ACP_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_DISABLE", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_EFUSE_0[] = {
+	 { "EFUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGENERAL_PWRMGT[] = {
+	 { "GLOBAL_PWRMGT_EN", 0, 0, &umr_bitfield_default },
+	 { "STATIC_PM_EN", 1, 1, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_DIS", 2, 2, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_TYPE", 3, 3, &umr_bitfield_default },
+	 { "SW_SMIO_INDEX", 6, 6, &umr_bitfield_default },
+	 { "LOW_VOLT_D2_ACPI", 8, 8, &umr_bitfield_default },
+	 { "LOW_VOLT_D3_ACPI", 9, 9, &umr_bitfield_default },
+	 { "VOLT_PWRMGT_EN", 10, 10, &umr_bitfield_default },
+	 { "SPARE11", 11, 11, &umr_bitfield_default },
+	 { "GPU_COUNTER_ACPI", 14, 14, &umr_bitfield_default },
+	 { "GPU_COUNTER_CLK", 15, 15, &umr_bitfield_default },
+	 { "GPU_COUNTER_OFF", 16, 16, &umr_bitfield_default },
+	 { "GPU_COUNTER_INTF_OFF", 17, 17, &umr_bitfield_default },
+	 { "SPARE18", 18, 18, &umr_bitfield_default },
+	 { "ACPI_D3_VID", 19, 20, &umr_bitfield_default },
+	 { "DYN_SPREAD_SPECTRUM_EN", 23, 23, &umr_bitfield_default },
+	 { "SPARE27", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCNB_PWRMGT_CNTL[] = {
+	 { "GNB_SLOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "GNB_SLOW", 2, 2, &umr_bitfield_default },
+	 { "FORCE_NB_PS1", 3, 3, &umr_bitfield_default },
+	 { "DPM_ENABLED", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_PWRMGT_CNTL[] = {
+	 { "SCLK_PWRMGT_OFF", 0, 0, &umr_bitfield_default },
+	 { "RESET_BUSY_CNT", 4, 4, &umr_bitfield_default },
+	 { "RESET_SCLK_CNT", 5, 5, &umr_bitfield_default },
+	 { "DYN_LIGHT_SLEEP_EN", 14, 14, &umr_bitfield_default },
+	 { "AUTO_SCLK_PULSE_SKIP", 15, 15, &umr_bitfield_default },
+	 { "LIGHT_SLEEP_COUNTER", 16, 20, &umr_bitfield_default },
+	 { "DYNAMIC_PM_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX[] = {
+	 { "TARGET_STATE", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_STATE", 4, 7, &umr_bitfield_default },
+	 { "CURR_MCLK_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MCLK_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_SCLK_INDEX", 16, 20, &umr_bitfield_default },
+	 { "TARG_SCLK_INDEX", 21, 25, &umr_bitfield_default },
+	 { "CURR_LCLK_INDEX", 26, 28, &umr_bitfield_default },
+	 { "TARG_LCLK_INDEX", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_PCC_CONTROL[] = {
+	 { "PCC_POLARITY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_PCC_GPIO_SELECT[] = {
+	 { "GPIO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 3, &umr_bitfield_default },
+	 { "TST_REF_SEL", 4, 7, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 8, 14, &umr_bitfield_default },
+	 { "TST_RESET", 15, 15, &umr_bitfield_default },
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_STATIC_SCREEN_PARAMETER[] = {
+	 { "STATIC_SCREEN_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL[] = {
+	 { "DISP_GAP", 0, 1, &umr_bitfield_default },
+	 { "VBI_TIMER_COUNT", 4, 17, &umr_bitfield_default },
+	 { "VBI_TIMER_UNIT", 20, 22, &umr_bitfield_default },
+	 { "DISP_GAP_MCHG", 24, 25, &umr_bitfield_default },
+	 { "VBI_TIMER_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACPI_CNTL[] = {
+	 { "SCLK_ACPI_DIV", 0, 6, &umr_bitfield_default },
+	 { "SCLK_CHANGE_SKIP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 16, 16, &umr_bitfield_default },
+	 { "SELF_REFRESH_MASK", 17, 17, &umr_bitfield_default },
+	 { "ALLOW_NBPSTATE_MASK", 18, 18, &umr_bitfield_default },
+	 { "BIF_BUSY_MASK", 19, 19, &umr_bitfield_default },
+	 { "UVD_BUSY_MASK", 20, 20, &umr_bitfield_default },
+	 { "MC0SRBM_BUSY_MASK", 21, 21, &umr_bitfield_default },
+	 { "MC1SRBM_BUSY_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_ALLOW_MASK", 23, 23, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 24, 24, &umr_bitfield_default },
+	 { "SELF_REFRESH_NLC_MASK", 25, 25, &umr_bitfield_default },
+	 { "FAST_EXIT_REQ_NBPSTATE", 26, 26, &umr_bitfield_default },
+	 { "DEEP_SLEEP_ENTRY_MODE", 27, 27, &umr_bitfield_default },
+	 { "MBUS2_ACTIVE_MASK", 28, 28, &umr_bitfield_default },
+	 { "VCE_BUSY_MASK", 29, 29, &umr_bitfield_default },
+	 { "AZ_BUSY_MASK", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RLC_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "HDP_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "ROM_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "PDMA_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "IDCT_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "SDMA_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_AZ_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK", 9, 9, &umr_bitfield_default },
+	 { "UVD_CG_MC_STAT_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "VCE_CG_MC_STAT_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "SAM_CG_MC_STAT_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "SAM_CG_STATUS_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 14, 14, &umr_bitfield_default },
+	 { "SHALLOW_DIV_ID", 21, 23, &umr_bitfield_default },
+	 { "INOUT_CUSHION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_MISC_CNTL[] = {
+	 { "DPM_DS_DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "DPM_SS_DIV_ID", 3, 5, &umr_bitfield_default },
+	 { "OCP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OCP_DS_DIV_ID", 17, 19, &umr_bitfield_default },
+	 { "OCP_SS_DIV_ID", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL3[] = {
+	 { "GRBM_0_SMU_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRBM_1_SMU_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "GRBM_2_SMU_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "GRBM_3_SMU_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "GRBM_4_SMU_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "GRBM_5_SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "GRBM_6_SMU_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "GRBM_7_SMU_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "GRBM_8_SMU_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "GRBM_9_SMU_BUSY_MASK", 9, 9, &umr_bitfield_default },
+	 { "GRBM_10_SMU_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "GRBM_11_SMU_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "GRBM_12_SMU_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "GRBM_13_SMU_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "GRBM_14_SMU_BUSY_MASK", 14, 14, &umr_bitfield_default },
+	 { "GRBM_15_SMU_BUSY_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_1[] = {
+	 { "CURR_VDDCI_INDEX", 0, 3, &umr_bitfield_default },
+	 { "TARG_VDDCI_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_MVDD_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MVDD_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_VDDC_INDEX", 16, 19, &umr_bitfield_default },
+	 { "TARG_VDDC_INDEX", 20, 23, &umr_bitfield_default },
+	 { "CURR_PCIE_INDEX", 24, 27, &umr_bitfield_default },
+	 { "TARG_PCIE_INDEX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ULV_PARAMETER[] = {
+	 { "ULV_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "ULV_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_0[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_1[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_2[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_3[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_4[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_5[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_6[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
+	 { "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "L1IMU_SMU_IDLE_MASK", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_BIT3", 3, 3, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 4, 4, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE1_MASK", 6, 6, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE2_MASK", 7, 7, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE3_MASK", 8, 8, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE4_MASK", 9, 9, &umr_bitfield_default },
+	 { "L1IMUGPP_IDLE_MASK", 10, 10, &umr_bitfield_default },
+	 { "L1IMUGPPSB_IDLE_MASK", 11, 11, &umr_bitfield_default },
+	 { "L1IMUBIF_IDLE_MASK", 12, 12, &umr_bitfield_default },
+	 { "L1IMUINTGEN_IDLE_MASK", 13, 13, &umr_bitfield_default },
+	 { "L2IMU_IDLE_MASK", 14, 14, &umr_bitfield_default },
+	 { "ORB_IDLE_MASK", 15, 15, &umr_bitfield_default },
+	 { "ON_INB_WAKE_MASK", 16, 16, &umr_bitfield_default },
+	 { "ON_INB_WAKE_ACK_MASK", 17, 17, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_MASK", 18, 18, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_ACK_MASK", 19, 19, &umr_bitfield_default },
+	 { "DMAACTIVE_MASK", 20, 20, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_CKS_ENABLE[] = {
+	 { "STRETCH_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "masterReset", 1, 1, &umr_bitfield_default },
+	 { "staticEnable", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_CKS_CNTL[] = {
+	 { "CKS_BYPASS", 0, 0, &umr_bitfield_default },
+	 { "CKS_PCCEnable", 1, 1, &umr_bitfield_default },
+	 { "CKS_TEMP_COMP", 2, 2, &umr_bitfield_default },
+	 { "CKS_STRETCH_AMOUNT", 3, 6, &umr_bitfield_default },
+	 { "CKS_SKIP_PHASE_BYPASS", 7, 7, &umr_bitfield_default },
+	 { "CKS_SAMPLE_SIZE", 8, 11, &umr_bitfield_default },
+	 { "CKS_FSM_WAIT_CYCLES", 12, 15, &umr_bitfield_default },
+	 { "CKS_USE_FOR_LOW_FREQ", 16, 16, &umr_bitfield_default },
+	 { "CKS_NO_EXTRA_COARSE_STEP", 17, 17, &umr_bitfield_default },
+	 { "CKS_LDO_REFSEL", 18, 21, &umr_bitfield_default },
+	 { "DDT_DEBUS_SEL", 22, 22, &umr_bitfield_default },
+	 { "CKS_LDO_READY_COUNT_VAL", 23, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_PARAMETER[] = {
+	 { "VDDGFX_IDLE_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "VDDGFX_IDLE_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_CONTROL[] = {
+	 { "VDDGFX_IDLE_EN", 0, 0, &umr_bitfield_default },
+	 { "VDDGFX_IDLE_DETECT", 1, 1, &umr_bitfield_default },
+	 { "FORCE_VDDGFX_IDLE_EXIT", 2, 2, &umr_bitfield_default },
+	 { "SMC_VDDGFX_IDLE_STATE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_EXIT[] = {
+	 { "BIF_EXIT_REQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_CONTROL2[] = {
+	 { "DISP_TIMER_PULSE_WIDTH", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_MIN_DIV[] = {
+	 { "FRACV", 0, 11, &umr_bitfield_default },
+	 { "INTV", 12, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MODE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_DEBUG[] = {
+	 { "DISP_TIMER_INT_RUNNING", 0, 0, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 1, 1, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 2, 2, &umr_bitfield_default },
+	 { "DISP_TIMER_RUN_VAL", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER2_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MODE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER2_DEBUG[] = {
+	 { "DISP_TIMER_INT_RUNNING", 0, 0, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 1, 1, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 2, 2, &umr_bitfield_default },
+	 { "DISP_TIMER_RUN_VAL", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_CTRL[] = {
+	 { "DPM_EVENT_SRC", 0, 2, &umr_bitfield_default },
+	 { "THERM_INC_CLK", 3, 3, &umr_bitfield_default },
+	 { "SPARE", 4, 13, &umr_bitfield_default },
+	 { "DIG_THERM_DPM", 14, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 24, &umr_bitfield_default },
+	 { "CTF_PAD_POLARITY", 25, 25, &umr_bitfield_default },
+	 { "CTF_PAD_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_STATUS[] = {
+	 { "SPARE", 0, 8, &umr_bitfield_default },
+	 { "FDO_PWM_DUTY", 9, 16, &umr_bitfield_default },
+	 { "THERM_ALERT", 17, 17, &umr_bitfield_default },
+	 { "GEN_STATUS", 18, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT[] = {
+	 { "DIG_THERM_CTF", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTH", 8, 15, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 16, 23, &umr_bitfield_default },
+	 { "THERM_INT_MASK", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_CTRL[] = {
+	 { "TS_FILTER", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 8, &umr_bitfield_default },
+	 { "THERMAL_RANGE_RST", 9, 9, &umr_bitfield_default },
+	 { "TEMP_SEL", 20, 27, &umr_bitfield_default },
+	 { "THM_READY_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_STATUS[] = {
+	 { "ASIC_MAX_TEMP", 0, 8, &umr_bitfield_default },
+	 { "CTF_TEMP", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL0[] = {
+	 { "FDO_STATIC_DUTY", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_DUTY", 8, 15, &umr_bitfield_default },
+	 { "FDO_PWM_MANUAL", 16, 16, &umr_bitfield_default },
+	 { "FDO_PWM_HYSTER", 17, 22, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP_EN", 23, 23, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL1[] = {
+	 { "FMAX_DUTY100", 0, 7, &umr_bitfield_default },
+	 { "FMIN_DUTY", 8, 15, &umr_bitfield_default },
+	 { "M", 16, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 29, &umr_bitfield_default },
+	 { "FDO_PWRDNB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL2[] = {
+	 { "TMIN", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_TIME", 8, 10, &umr_bitfield_default },
+	 { "FDO_PWM_MODE", 11, 13, &umr_bitfield_default },
+	 { "TMIN_HYSTER", 14, 16, &umr_bitfield_default },
+	 { "TMAX", 17, 24, &umr_bitfield_default },
+	 { "TACH_PWM_RESP_RATE", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_CTRL[] = {
+	 { "EDGE_PER_REV", 0, 2, &umr_bitfield_default },
+	 { "TARGET_PERIOD", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_STATUS[] = {
+	 { "TACH_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_THM_STRAPS0[] = {
+	 { "TMON0_BGADJ", 1, 8, &umr_bitfield_default },
+	 { "TMON1_BGADJ", 9, 16, &umr_bitfield_default },
+	 { "TMON_CMON_FUSE_SEL", 17, 17, &umr_bitfield_default },
+	 { "NUM_ACQ", 18, 20, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 21, 23, &umr_bitfield_default },
+	 { "TMON_CONFIG_SOURCE", 24, 24, &umr_bitfield_default },
+	 { "CTF_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "TMON0_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "TMON1_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "TMON2_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "TMON3_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "UNUSED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_STATUS[] = {
+	 { "CURRENT_RDI", 0, 4, &umr_bitfield_default },
+	 { "MEAS_DONE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_STATUS[] = {
+	 { "CURRENT_RDI", 0, 4, &umr_bitfield_default },
+	 { "MEAS_DONE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
+	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
+	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
+	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
+	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC1_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC1_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
+	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
+	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
+	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC2_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC2_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
+	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
+	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
+	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC3_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC3_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
+	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
+	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_CNTL[] = {
+	 { "CPL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CPL_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "CPL_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "CPL_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_SEL[] = {
+	 { "CPL_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_VAL[] = {
+	 { "CPL_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_CNTL[] = {
+	 { "DCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_STATUS[] = {
+	 { "DCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_CNTL[] = {
+	 { "VCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_STATUS[] = {
+	 { "VCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_CNTL[] = {
+	 { "ECLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_STATUS[] = {
+	 { "ECLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACLK_CNTL[] = {
+	 { "ACLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_DFS_BYPASS_CNTL[] = {
+	 { "BYPASSECLK", 0, 0, &umr_bitfield_default },
+	 { "BYPASSLCLK", 1, 1, &umr_bitfield_default },
+	 { "BYPASSEVCLK", 2, 2, &umr_bitfield_default },
+	 { "BYPASSDCLK", 3, 3, &umr_bitfield_default },
+	 { "BYPASSVCLK", 4, 4, &umr_bitfield_default },
+	 { "BYPASSDISPCLK", 5, 5, &umr_bitfield_default },
+	 { "BYPASSDPREFCLK", 6, 6, &umr_bitfield_default },
+	 { "BYPASSACLK", 7, 7, &umr_bitfield_default },
+	 { "BYPASSADIVCLK", 8, 8, &umr_bitfield_default },
+	 { "BYPASSPSPCLK", 9, 9, &umr_bitfield_default },
+	 { "BYPASSSAMCLK", 10, 10, &umr_bitfield_default },
+	 { "BYPASSSCLK", 11, 11, &umr_bitfield_default },
+	 { "USE_SPLL_BYPASS_EN", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL[] = {
+	 { "SPLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "SPLL_PWRON", 1, 1, &umr_bitfield_default },
+	 { "SPLL_DIVEN", 2, 2, &umr_bitfield_default },
+	 { "SPLL_BYPASS_EN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_BYPASS_THRU_DFS", 4, 4, &umr_bitfield_default },
+	 { "SPLL_REF_DIV", 5, 10, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_EN", 12, 12, &umr_bitfield_default },
+	 { "SPLL_PDIV_A", 20, 26, &umr_bitfield_default },
+	 { "SPLL_DIVA_ACK", 27, 27, &umr_bitfield_default },
+	 { "SPLL_OTEST_LOCK_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_2[] = {
+	 { "SCLK_MUX_SEL", 0, 8, &umr_bitfield_default },
+	 { "SPLL_CTLREQ", 11, 11, &umr_bitfield_default },
+	 { "SPLL_BYPASS_CHG", 22, 22, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_CHG", 23, 23, &umr_bitfield_default },
+	 { "SPLL_RESET_CHG", 24, 24, &umr_bitfield_default },
+	 { "SPLL_BABY_STEP_CHG", 25, 25, &umr_bitfield_default },
+	 { "SCLK_MUX_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "SPLL_UNLOCK_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "SPLL_CLKF_UPDATE", 28, 28, &umr_bitfield_default },
+	 { "SPLL_TEST_UNLOCK_CLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_3[] = {
+	 { "SPLL_FB_DIV", 0, 25, &umr_bitfield_default },
+	 { "SPLL_DITHEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_4[] = {
+	 { "SPLL_SCLK_TEST_SEL", 0, 3, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT_SEL", 5, 6, &umr_bitfield_default },
+	 { "SPLL_SCLK_EN", 7, 8, &umr_bitfield_default },
+	 { "SPLL_SPARE", 9, 18, &umr_bitfield_default },
+	 { "TEST_FRAC_BYPASS", 21, 21, &umr_bitfield_default },
+	 { "SPLL_ILOCK", 23, 23, &umr_bitfield_default },
+	 { "SPLL_FBCLK_SEL", 24, 24, &umr_bitfield_default },
+	 { "SPLL_VCTRLADC_EN", 25, 25, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT", 26, 27, &umr_bitfield_default },
+	 { "SPLL_SPARE_EXT", 28, 30, &umr_bitfield_default },
+	 { "SPLL_VTOI_BIAS_CNTL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_5[] = {
+	 { "FBDIV_SSC_BYPASS", 0, 0, &umr_bitfield_default },
+	 { "RISEFBVCO_EN", 1, 1, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 2, 3, &umr_bitfield_default },
+	 { "RESET_TIMER", 4, 5, &umr_bitfield_default },
+	 { "FAST_LOCK_CNTRL", 6, 7, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 8, 8, &umr_bitfield_default },
+	 { "RESET_ANTI_MUX", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_6[] = {
+	 { "SCLKMUX0_CLKOFF_CNT", 0, 7, &umr_bitfield_default },
+	 { "SCLKMUX1_CLKOFF_CNT", 8, 15, &umr_bitfield_default },
+	 { "SPLL_VCTL_EN", 16, 16, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_IN", 17, 20, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_OUT", 21, 24, &umr_bitfield_default },
+	 { "SPLL_LF_CNTR", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_7[] = {
+	 { "SPLL_BW_CNTRL", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPLL_CNTL_MODE[] = {
+	 { "SPLL_SW_DIR_CONTROL", 0, 0, &umr_bitfield_default },
+	 { "SPLL_LEGACY_PDIV", 1, 1, &umr_bitfield_default },
+	 { "SPLL_TEST", 2, 2, &umr_bitfield_default },
+	 { "SPLL_FASTEN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_ENSAT", 4, 4, &umr_bitfield_default },
+	 { "SPLL_TEST_CLK_EXT_DIV", 10, 11, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_DLY_CNT", 12, 19, &umr_bitfield_default },
+	 { "SPLL_RESET_EN", 28, 28, &umr_bitfield_default },
+	 { "SPLL_VCO_MODE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM[] = {
+	 { "SSEN", 0, 0, &umr_bitfield_default },
+	 { "CLKS", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM_2[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMPLL_BYPASSCLK_SEL[] = {
+	 { "MPLL_CLKOUT_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL[] = {
+	 { "XTALIN_DIVIDE", 1, 1, &umr_bitfield_default },
+	 { "BCLK_AS_XCLK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_2[] = {
+	 { "ENABLE_XCLK", 0, 0, &umr_bitfield_default },
+	 { "FORCE_BIF_REFCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "MUX_TCLK_TO_XCLK", 8, 8, &umr_bitfield_default },
+	 { "XO_IN_OSCIN_EN", 14, 14, &umr_bitfield_default },
+	 { "XO_IN_ICORE_CLK_OE", 15, 15, &umr_bitfield_default },
+	 { "XO_IN_CML_RXEN", 16, 16, &umr_bitfield_default },
+	 { "XO_IN_BIDIR_CML_OE", 17, 17, &umr_bitfield_default },
+	 { "XO_IN2_OSCIN_EN", 18, 18, &umr_bitfield_default },
+	 { "XO_IN2_ICORE_CLK_OE", 19, 19, &umr_bitfield_default },
+	 { "XO_IN2_CML_RXEN", 20, 20, &umr_bitfield_default },
+	 { "XO_IN2_BIDIR_CML_OE", 21, 21, &umr_bitfield_default },
+	 { "CML_CTRL", 22, 23, &umr_bitfield_default },
+	 { "CLK_SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_CLK_CNTL[] = {
+	 { "CMON_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "CTF_CLK_SHUTOFF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_CLK_CTRL[] = {
+	 { "DEEP_SLEEP_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "ZCLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "DFT_SMS_PG_CLK_SEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 4, &umr_bitfield_default },
+	 { "TST_REF_SEL", 5, 9, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 10, 16, &umr_bitfield_default },
+	 { "TST_RESET", 17, 17, &umr_bitfield_default },
+	 { "TST_CLK_SEL_MODE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL_2[] = {
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_ADFS_CLK_BYPASS_CNTL1[] = {
+	 { "ECLK_BYPASS_CNTL", 0, 2, &umr_bitfield_default },
+	 { "SCLK_BYPASS_CNTL", 3, 5, &umr_bitfield_default },
+	 { "LCLK_BYPASS_CNTL", 6, 8, &umr_bitfield_default },
+	 { "DCLK_BYPASS_CNTL", 9, 11, &umr_bitfield_default },
+	 { "VCLK_BYPASS_CNTL", 12, 14, &umr_bitfield_default },
+	 { "DISPCLK_BYPASS_CNTL", 15, 17, &umr_bitfield_default },
+	 { "DRREFCLK_BYPASS_CNTL", 18, 20, &umr_bitfield_default },
+	 { "ACLK_BYPASS_CNTL", 21, 23, &umr_bitfield_default },
+	 { "SAMCLK_BYPASS_CNTL", 24, 26, &umr_bitfield_default },
+	 { "ACLK_DIV_BYPASS_CNTL", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_DC[] = {
+	 { "OSC_EN", 0, 0, &umr_bitfield_default },
+	 { "XTL_LOW_GAIN", 1, 2, &umr_bitfield_default },
+	 { "XTALIN_SEL", 10, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_CNTL[] = {
+	 { "SCK_OVERWRITE", 1, 1, &umr_bitfield_default },
+	 { "CLOCK_GATING_EN", 2, 2, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_SETUP_TIME", 8, 15, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_HOLD_TIME", 16, 23, &umr_bitfield_default },
+	 { "SCK_PRESCALE_REFCLK", 24, 27, &umr_bitfield_default },
+	 { "SCK_PRESCALE_CRYSTAL_CLK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPAGE_MIRROR_CNTL[] = {
+	 { "PAGE_MIRROR_BASE_ADDR", 0, 23, &umr_bitfield_default },
+	 { "PAGE_MIRROR_INVALIDATE", 24, 24, &umr_bitfield_default },
+	 { "PAGE_MIRROR_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "PAGE_MIRROR_USAGE", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_STATUS[] = {
+	 { "ROM_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCGTT_ROM_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_INDEX[] = {
+	 { "ROM_INDEX", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_DATA[] = {
+	 { "ROM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_START[] = {
+	 { "ROM_START", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_CNTL[] = {
+	 { "DATA_SIZE", 0, 15, &umr_bitfield_default },
+	 { "COMMAND_SIZE", 16, 17, &umr_bitfield_default },
+	 { "ROM_SW_RETURN_DATA_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_STATUS[] = {
+	 { "ROM_SW_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_COMMAND[] = {
+	 { "ROM_SW_INSTRUCTION", 0, 7, &umr_bitfield_default },
+	 { "ROM_SW_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_1[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_2[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_3[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_4[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_5[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_6[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_7[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_8[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_9[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_10[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_11[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_12[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_13[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_14[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_15[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_16[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_17[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_18[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_19[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_20[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_21[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_22[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_23[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_24[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_25[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_26[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_27[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_28[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_29[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_30[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_31[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_32[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_33[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_34[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_35[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_36[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_37[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_38[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_39[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_40[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_41[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_42[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_43[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_44[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_45[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_46[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_47[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_48[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_49[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_50[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_51[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_52[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_53[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_54[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_55[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_56[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_57[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_58[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_59[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_60[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_61[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_62[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_63[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_64[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_ENA[] = {
+	 { "THERM_INTH_SET", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_SET", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_SET", 2, 2, &umr_bitfield_default },
+	 { "THERM_INTH_CLR", 3, 3, &umr_bitfield_default },
+	 { "THERM_INTL_CLR", 4, 4, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CLR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_CTRL[] = {
+	 { "DIG_THERM_INTH", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 8, 15, &umr_bitfield_default },
+	 { "GNB_TEMP_THRESHOLD", 16, 23, &umr_bitfield_default },
+	 { "THERM_INTH_MASK", 24, 24, &umr_bitfield_default },
+	 { "THERM_INTL_MASK", 25, 25, &umr_bitfield_default },
+	 { "THERM_TRIGGER_MASK", 26, 26, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_MASK", 27, 27, &umr_bitfield_default },
+	 { "THERM_GNB_HW_ENA", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_STATUS[] = {
+	 { "THERM_INTH_DETECT", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_DETECT", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_DETECT", 2, 2, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_DETECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MAIN_PLL_OP_FREQ[] = {
+	 { "PLL_OP_FREQ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_STATUS[] = {
+	 { "SMU_DONE", 0, 0, &umr_bitfield_default },
+	 { "SMU_PASS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_FIRMWARE[] = {
+	 { "SMU_IN_PROG", 0, 0, &umr_bitfield_default },
+	 { "SMU_RD_DONE", 1, 2, &umr_bitfield_default },
+	 { "SMU_SRAM_RD_BLOCK_EN", 3, 3, &umr_bitfield_default },
+	 { "SMU_SRAM_WR_BLOCK_EN", 4, 4, &umr_bitfield_default },
+	 { "SMU_counter", 8, 11, &umr_bitfield_default },
+	 { "SMU_MODE", 16, 16, &umr_bitfield_default },
+	 { "SMU_SEL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_INPUT_DATA[] = {
+	 { "START_ADDR", 0, 30, &umr_bitfield_default },
+	 { "AUTO_START", 31, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/smu712_regs.i b/src/lib/ip/smu712_regs.i
new file mode 100644
index 0000000..1b85832
--- /dev/null
+++ b/src/lib/ip/smu712_regs.i
@@ -0,0 +1,1227 @@
+	{ "mmGPIOPAD_SW_INT_STAT", REG_MMIO, 0x180, &mmGPIOPAD_SW_INT_STAT[0], sizeof(mmGPIOPAD_SW_INT_STAT)/sizeof(mmGPIOPAD_SW_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_STRENGTH", REG_MMIO, 0x181, &mmGPIOPAD_STRENGTH[0], sizeof(mmGPIOPAD_STRENGTH)/sizeof(mmGPIOPAD_STRENGTH[0]), 0, 0 },
+	{ "mmGPIOPAD_MASK", REG_MMIO, 0x182, &mmGPIOPAD_MASK[0], sizeof(mmGPIOPAD_MASK)/sizeof(mmGPIOPAD_MASK[0]), 0, 0 },
+	{ "mmGPIOPAD_A", REG_MMIO, 0x183, &mmGPIOPAD_A[0], sizeof(mmGPIOPAD_A)/sizeof(mmGPIOPAD_A[0]), 0, 0 },
+	{ "mmGPIOPAD_EN", REG_MMIO, 0x184, &mmGPIOPAD_EN[0], sizeof(mmGPIOPAD_EN)/sizeof(mmGPIOPAD_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_Y", REG_MMIO, 0x185, &mmGPIOPAD_Y[0], sizeof(mmGPIOPAD_Y)/sizeof(mmGPIOPAD_Y[0]), 0, 0 },
+	{ "mmGPIOPAD_PINSTRAPS", REG_MMIO, 0x186, &mmGPIOPAD_PINSTRAPS[0], sizeof(mmGPIOPAD_PINSTRAPS)/sizeof(mmGPIOPAD_PINSTRAPS[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_EN", REG_MMIO, 0x187, &mmGPIOPAD_INT_STAT_EN[0], sizeof(mmGPIOPAD_INT_STAT_EN)/sizeof(mmGPIOPAD_INT_STAT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT", REG_MMIO, 0x188, &mmGPIOPAD_INT_STAT[0], sizeof(mmGPIOPAD_INT_STAT)/sizeof(mmGPIOPAD_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_AK", REG_MMIO, 0x189, &mmGPIOPAD_INT_STAT_AK[0], sizeof(mmGPIOPAD_INT_STAT_AK)/sizeof(mmGPIOPAD_INT_STAT_AK[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_EN", REG_MMIO, 0x18a, &mmGPIOPAD_INT_EN[0], sizeof(mmGPIOPAD_INT_EN)/sizeof(mmGPIOPAD_INT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_TYPE", REG_MMIO, 0x18b, &mmGPIOPAD_INT_TYPE[0], sizeof(mmGPIOPAD_INT_TYPE)/sizeof(mmGPIOPAD_INT_TYPE[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_POLARITY", REG_MMIO, 0x18c, &mmGPIOPAD_INT_POLARITY[0], sizeof(mmGPIOPAD_INT_POLARITY)/sizeof(mmGPIOPAD_INT_POLARITY[0]), 0, 0 },
+	{ "mmGPIOPAD_EXTERN_TRIG_CNTL", REG_MMIO, 0x18d, &mmGPIOPAD_EXTERN_TRIG_CNTL[0], sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL)/sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL[0]), 0, 0 },
+	{ "mmGPIOPAD_RCVR_SEL", REG_MMIO, 0x191, &mmGPIOPAD_RCVR_SEL[0], sizeof(mmGPIOPAD_RCVR_SEL)/sizeof(mmGPIOPAD_RCVR_SEL[0]), 0, 0 },
+	{ "mmGPIOPAD_PU_EN", REG_MMIO, 0x192, &mmGPIOPAD_PU_EN[0], sizeof(mmGPIOPAD_PU_EN)/sizeof(mmGPIOPAD_PU_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_PD_EN", REG_MMIO, 0x193, &mmGPIOPAD_PD_EN[0], sizeof(mmGPIOPAD_PD_EN)/sizeof(mmGPIOPAD_PD_EN[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_0", REG_MMIO, 0x1a6, &mmSMU_IND_INDEX_0[0], sizeof(mmSMU_IND_INDEX_0)/sizeof(mmSMU_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_0", REG_MMIO, 0x1a7, &mmSMU_IND_DATA_0[0], sizeof(mmSMU_IND_DATA_0)/sizeof(mmSMU_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_1", REG_MMIO, 0x1a8, &mmSMU_IND_INDEX_1[0], sizeof(mmSMU_IND_INDEX_1)/sizeof(mmSMU_IND_INDEX_1[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_1", REG_MMIO, 0x1a9, &mmSMU_IND_DATA_1[0], sizeof(mmSMU_IND_DATA_1)/sizeof(mmSMU_IND_DATA_1[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_2", REG_MMIO, 0x1aa, &mmSMU_IND_INDEX_2[0], sizeof(mmSMU_IND_INDEX_2)/sizeof(mmSMU_IND_INDEX_2[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_2", REG_MMIO, 0x1ab, &mmSMU_IND_DATA_2[0], sizeof(mmSMU_IND_DATA_2)/sizeof(mmSMU_IND_DATA_2[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_11", REG_MMIO, 0x1AC, NULL, 0, 0, 0 },
+	{ "mmSMU_IND_INDEX_3", REG_MMIO, 0x1ac, &mmSMU_IND_INDEX_3[0], sizeof(mmSMU_IND_INDEX_3)/sizeof(mmSMU_IND_INDEX_3[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_11", REG_MMIO, 0x1AD, NULL, 0, 0, 0 },
+	{ "mmSMU_IND_DATA_3", REG_MMIO, 0x1ad, &mmSMU_IND_DATA_3[0], sizeof(mmSMU_IND_DATA_3)/sizeof(mmSMU_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_4", REG_MMIO, 0x1ae, &mmSMU_IND_INDEX_4[0], sizeof(mmSMU_IND_INDEX_4)/sizeof(mmSMU_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_4", REG_MMIO, 0x1af, &mmSMU_IND_DATA_4[0], sizeof(mmSMU_IND_DATA_4)/sizeof(mmSMU_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_5", REG_MMIO, 0x1b0, &mmSMU_IND_INDEX_5[0], sizeof(mmSMU_IND_INDEX_5)/sizeof(mmSMU_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_5", REG_MMIO, 0x1b1, &mmSMU_IND_DATA_5[0], sizeof(mmSMU_IND_DATA_5)/sizeof(mmSMU_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_6", REG_MMIO, 0x1b2, &mmSMU_IND_INDEX_6[0], sizeof(mmSMU_IND_INDEX_6)/sizeof(mmSMU_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_6", REG_MMIO, 0x1b3, &mmSMU_IND_DATA_6[0], sizeof(mmSMU_IND_DATA_6)/sizeof(mmSMU_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_7", REG_MMIO, 0x1b4, &mmSMU_IND_INDEX_7[0], sizeof(mmSMU_IND_INDEX_7)/sizeof(mmSMU_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_7", REG_MMIO, 0x1b5, &mmSMU_IND_DATA_7[0], sizeof(mmSMU_IND_DATA_7)/sizeof(mmSMU_IND_DATA_7[0]), 0, 0 },
+	{ "mmCG_FPS_CNT", REG_MMIO, 0x1b6, &mmCG_FPS_CNT[0], sizeof(mmCG_FPS_CNT)/sizeof(mmCG_FPS_CNT[0]), 0, 0 },
+	{ "ixDPM_TABLE_1", REG_SMC, 0x3f000, &ixDPM_TABLE_1[0], sizeof(ixDPM_TABLE_1)/sizeof(ixDPM_TABLE_1[0]), 0, 0 },
+	{ "ixDPM_TABLE_2", REG_SMC, 0x3f004, &ixDPM_TABLE_2[0], sizeof(ixDPM_TABLE_2)/sizeof(ixDPM_TABLE_2[0]), 0, 0 },
+	{ "ixDPM_TABLE_3", REG_SMC, 0x3f008, &ixDPM_TABLE_3[0], sizeof(ixDPM_TABLE_3)/sizeof(ixDPM_TABLE_3[0]), 0, 0 },
+	{ "ixDPM_TABLE_4", REG_SMC, 0x3f00c, &ixDPM_TABLE_4[0], sizeof(ixDPM_TABLE_4)/sizeof(ixDPM_TABLE_4[0]), 0, 0 },
+	{ "ixDPM_TABLE_5", REG_SMC, 0x3f010, &ixDPM_TABLE_5[0], sizeof(ixDPM_TABLE_5)/sizeof(ixDPM_TABLE_5[0]), 0, 0 },
+	{ "ixDPM_TABLE_6", REG_SMC, 0x3f014, &ixDPM_TABLE_6[0], sizeof(ixDPM_TABLE_6)/sizeof(ixDPM_TABLE_6[0]), 0, 0 },
+	{ "ixDPM_TABLE_7", REG_SMC, 0x3f018, &ixDPM_TABLE_7[0], sizeof(ixDPM_TABLE_7)/sizeof(ixDPM_TABLE_7[0]), 0, 0 },
+	{ "ixDPM_TABLE_8", REG_SMC, 0x3f01c, &ixDPM_TABLE_8[0], sizeof(ixDPM_TABLE_8)/sizeof(ixDPM_TABLE_8[0]), 0, 0 },
+	{ "ixDPM_TABLE_9", REG_SMC, 0x3f020, &ixDPM_TABLE_9[0], sizeof(ixDPM_TABLE_9)/sizeof(ixDPM_TABLE_9[0]), 0, 0 },
+	{ "ixDPM_TABLE_10", REG_SMC, 0x3f024, &ixDPM_TABLE_10[0], sizeof(ixDPM_TABLE_10)/sizeof(ixDPM_TABLE_10[0]), 0, 0 },
+	{ "ixDPM_TABLE_11", REG_SMC, 0x3f028, &ixDPM_TABLE_11[0], sizeof(ixDPM_TABLE_11)/sizeof(ixDPM_TABLE_11[0]), 0, 0 },
+	{ "ixDPM_TABLE_12", REG_SMC, 0x3f02c, &ixDPM_TABLE_12[0], sizeof(ixDPM_TABLE_12)/sizeof(ixDPM_TABLE_12[0]), 0, 0 },
+	{ "ixDPM_TABLE_13", REG_SMC, 0x3f030, &ixDPM_TABLE_13[0], sizeof(ixDPM_TABLE_13)/sizeof(ixDPM_TABLE_13[0]), 0, 0 },
+	{ "ixDPM_TABLE_14", REG_SMC, 0x3f034, &ixDPM_TABLE_14[0], sizeof(ixDPM_TABLE_14)/sizeof(ixDPM_TABLE_14[0]), 0, 0 },
+	{ "ixDPM_TABLE_15", REG_SMC, 0x3f038, &ixDPM_TABLE_15[0], sizeof(ixDPM_TABLE_15)/sizeof(ixDPM_TABLE_15[0]), 0, 0 },
+	{ "ixDPM_TABLE_16", REG_SMC, 0x3f03c, &ixDPM_TABLE_16[0], sizeof(ixDPM_TABLE_16)/sizeof(ixDPM_TABLE_16[0]), 0, 0 },
+	{ "ixDPM_TABLE_17", REG_SMC, 0x3f040, &ixDPM_TABLE_17[0], sizeof(ixDPM_TABLE_17)/sizeof(ixDPM_TABLE_17[0]), 0, 0 },
+	{ "ixDPM_TABLE_18", REG_SMC, 0x3f044, &ixDPM_TABLE_18[0], sizeof(ixDPM_TABLE_18)/sizeof(ixDPM_TABLE_18[0]), 0, 0 },
+	{ "ixDPM_TABLE_19", REG_SMC, 0x3f048, &ixDPM_TABLE_19[0], sizeof(ixDPM_TABLE_19)/sizeof(ixDPM_TABLE_19[0]), 0, 0 },
+	{ "ixDPM_TABLE_20", REG_SMC, 0x3f04c, &ixDPM_TABLE_20[0], sizeof(ixDPM_TABLE_20)/sizeof(ixDPM_TABLE_20[0]), 0, 0 },
+	{ "ixDPM_TABLE_21", REG_SMC, 0x3f050, &ixDPM_TABLE_21[0], sizeof(ixDPM_TABLE_21)/sizeof(ixDPM_TABLE_21[0]), 0, 0 },
+	{ "ixDPM_TABLE_22", REG_SMC, 0x3f054, &ixDPM_TABLE_22[0], sizeof(ixDPM_TABLE_22)/sizeof(ixDPM_TABLE_22[0]), 0, 0 },
+	{ "ixDPM_TABLE_23", REG_SMC, 0x3f058, &ixDPM_TABLE_23[0], sizeof(ixDPM_TABLE_23)/sizeof(ixDPM_TABLE_23[0]), 0, 0 },
+	{ "ixDPM_TABLE_24", REG_SMC, 0x3f05c, &ixDPM_TABLE_24[0], sizeof(ixDPM_TABLE_24)/sizeof(ixDPM_TABLE_24[0]), 0, 0 },
+	{ "ixDPM_TABLE_25", REG_SMC, 0x3f060, &ixDPM_TABLE_25[0], sizeof(ixDPM_TABLE_25)/sizeof(ixDPM_TABLE_25[0]), 0, 0 },
+	{ "ixDPM_TABLE_26", REG_SMC, 0x3f064, &ixDPM_TABLE_26[0], sizeof(ixDPM_TABLE_26)/sizeof(ixDPM_TABLE_26[0]), 0, 0 },
+	{ "ixDPM_TABLE_27", REG_SMC, 0x3f068, &ixDPM_TABLE_27[0], sizeof(ixDPM_TABLE_27)/sizeof(ixDPM_TABLE_27[0]), 0, 0 },
+	{ "ixDPM_TABLE_28", REG_SMC, 0x3f06c, &ixDPM_TABLE_28[0], sizeof(ixDPM_TABLE_28)/sizeof(ixDPM_TABLE_28[0]), 0, 0 },
+	{ "ixDPM_TABLE_29", REG_SMC, 0x3f070, &ixDPM_TABLE_29[0], sizeof(ixDPM_TABLE_29)/sizeof(ixDPM_TABLE_29[0]), 0, 0 },
+	{ "ixDPM_TABLE_30", REG_SMC, 0x3f074, &ixDPM_TABLE_30[0], sizeof(ixDPM_TABLE_30)/sizeof(ixDPM_TABLE_30[0]), 0, 0 },
+	{ "ixDPM_TABLE_31", REG_SMC, 0x3f078, &ixDPM_TABLE_31[0], sizeof(ixDPM_TABLE_31)/sizeof(ixDPM_TABLE_31[0]), 0, 0 },
+	{ "ixDPM_TABLE_32", REG_SMC, 0x3f07c, &ixDPM_TABLE_32[0], sizeof(ixDPM_TABLE_32)/sizeof(ixDPM_TABLE_32[0]), 0, 0 },
+	{ "ixDPM_TABLE_33", REG_SMC, 0x3f080, &ixDPM_TABLE_33[0], sizeof(ixDPM_TABLE_33)/sizeof(ixDPM_TABLE_33[0]), 0, 0 },
+	{ "ixDPM_TABLE_34", REG_SMC, 0x3f084, &ixDPM_TABLE_34[0], sizeof(ixDPM_TABLE_34)/sizeof(ixDPM_TABLE_34[0]), 0, 0 },
+	{ "ixDPM_TABLE_35", REG_SMC, 0x3f088, &ixDPM_TABLE_35[0], sizeof(ixDPM_TABLE_35)/sizeof(ixDPM_TABLE_35[0]), 0, 0 },
+	{ "ixDPM_TABLE_36", REG_SMC, 0x3f08c, &ixDPM_TABLE_36[0], sizeof(ixDPM_TABLE_36)/sizeof(ixDPM_TABLE_36[0]), 0, 0 },
+	{ "ixDPM_TABLE_37", REG_SMC, 0x3f090, &ixDPM_TABLE_37[0], sizeof(ixDPM_TABLE_37)/sizeof(ixDPM_TABLE_37[0]), 0, 0 },
+	{ "ixDPM_TABLE_38", REG_SMC, 0x3f094, &ixDPM_TABLE_38[0], sizeof(ixDPM_TABLE_38)/sizeof(ixDPM_TABLE_38[0]), 0, 0 },
+	{ "ixDPM_TABLE_39", REG_SMC, 0x3f098, &ixDPM_TABLE_39[0], sizeof(ixDPM_TABLE_39)/sizeof(ixDPM_TABLE_39[0]), 0, 0 },
+	{ "ixDPM_TABLE_40", REG_SMC, 0x3f09c, &ixDPM_TABLE_40[0], sizeof(ixDPM_TABLE_40)/sizeof(ixDPM_TABLE_40[0]), 0, 0 },
+	{ "ixDPM_TABLE_41", REG_SMC, 0x3f0a0, &ixDPM_TABLE_41[0], sizeof(ixDPM_TABLE_41)/sizeof(ixDPM_TABLE_41[0]), 0, 0 },
+	{ "ixDPM_TABLE_42", REG_SMC, 0x3f0a4, &ixDPM_TABLE_42[0], sizeof(ixDPM_TABLE_42)/sizeof(ixDPM_TABLE_42[0]), 0, 0 },
+	{ "ixDPM_TABLE_43", REG_SMC, 0x3f0a8, &ixDPM_TABLE_43[0], sizeof(ixDPM_TABLE_43)/sizeof(ixDPM_TABLE_43[0]), 0, 0 },
+	{ "ixDPM_TABLE_44", REG_SMC, 0x3f0ac, &ixDPM_TABLE_44[0], sizeof(ixDPM_TABLE_44)/sizeof(ixDPM_TABLE_44[0]), 0, 0 },
+	{ "ixDPM_TABLE_45", REG_SMC, 0x3f0b0, &ixDPM_TABLE_45[0], sizeof(ixDPM_TABLE_45)/sizeof(ixDPM_TABLE_45[0]), 0, 0 },
+	{ "ixDPM_TABLE_46", REG_SMC, 0x3f0b4, &ixDPM_TABLE_46[0], sizeof(ixDPM_TABLE_46)/sizeof(ixDPM_TABLE_46[0]), 0, 0 },
+	{ "ixDPM_TABLE_47", REG_SMC, 0x3f0b8, &ixDPM_TABLE_47[0], sizeof(ixDPM_TABLE_47)/sizeof(ixDPM_TABLE_47[0]), 0, 0 },
+	{ "ixDPM_TABLE_48", REG_SMC, 0x3f0bc, &ixDPM_TABLE_48[0], sizeof(ixDPM_TABLE_48)/sizeof(ixDPM_TABLE_48[0]), 0, 0 },
+	{ "ixDPM_TABLE_49", REG_SMC, 0x3f0c0, &ixDPM_TABLE_49[0], sizeof(ixDPM_TABLE_49)/sizeof(ixDPM_TABLE_49[0]), 0, 0 },
+	{ "ixDPM_TABLE_50", REG_SMC, 0x3f0c4, &ixDPM_TABLE_50[0], sizeof(ixDPM_TABLE_50)/sizeof(ixDPM_TABLE_50[0]), 0, 0 },
+	{ "ixDPM_TABLE_51", REG_SMC, 0x3f0c8, &ixDPM_TABLE_51[0], sizeof(ixDPM_TABLE_51)/sizeof(ixDPM_TABLE_51[0]), 0, 0 },
+	{ "ixDPM_TABLE_52", REG_SMC, 0x3f0cc, &ixDPM_TABLE_52[0], sizeof(ixDPM_TABLE_52)/sizeof(ixDPM_TABLE_52[0]), 0, 0 },
+	{ "ixDPM_TABLE_53", REG_SMC, 0x3f0d0, &ixDPM_TABLE_53[0], sizeof(ixDPM_TABLE_53)/sizeof(ixDPM_TABLE_53[0]), 0, 0 },
+	{ "ixDPM_TABLE_54", REG_SMC, 0x3f0d4, &ixDPM_TABLE_54[0], sizeof(ixDPM_TABLE_54)/sizeof(ixDPM_TABLE_54[0]), 0, 0 },
+	{ "ixDPM_TABLE_55", REG_SMC, 0x3f0d8, &ixDPM_TABLE_55[0], sizeof(ixDPM_TABLE_55)/sizeof(ixDPM_TABLE_55[0]), 0, 0 },
+	{ "ixDPM_TABLE_56", REG_SMC, 0x3f0dc, &ixDPM_TABLE_56[0], sizeof(ixDPM_TABLE_56)/sizeof(ixDPM_TABLE_56[0]), 0, 0 },
+	{ "ixDPM_TABLE_57", REG_SMC, 0x3f0e0, &ixDPM_TABLE_57[0], sizeof(ixDPM_TABLE_57)/sizeof(ixDPM_TABLE_57[0]), 0, 0 },
+	{ "ixDPM_TABLE_58", REG_SMC, 0x3f0e4, &ixDPM_TABLE_58[0], sizeof(ixDPM_TABLE_58)/sizeof(ixDPM_TABLE_58[0]), 0, 0 },
+	{ "ixDPM_TABLE_59", REG_SMC, 0x3f0e8, &ixDPM_TABLE_59[0], sizeof(ixDPM_TABLE_59)/sizeof(ixDPM_TABLE_59[0]), 0, 0 },
+	{ "ixDPM_TABLE_60", REG_SMC, 0x3f0ec, &ixDPM_TABLE_60[0], sizeof(ixDPM_TABLE_60)/sizeof(ixDPM_TABLE_60[0]), 0, 0 },
+	{ "ixDPM_TABLE_61", REG_SMC, 0x3f0f0, &ixDPM_TABLE_61[0], sizeof(ixDPM_TABLE_61)/sizeof(ixDPM_TABLE_61[0]), 0, 0 },
+	{ "ixDPM_TABLE_62", REG_SMC, 0x3f0f4, &ixDPM_TABLE_62[0], sizeof(ixDPM_TABLE_62)/sizeof(ixDPM_TABLE_62[0]), 0, 0 },
+	{ "ixDPM_TABLE_63", REG_SMC, 0x3f0f8, &ixDPM_TABLE_63[0], sizeof(ixDPM_TABLE_63)/sizeof(ixDPM_TABLE_63[0]), 0, 0 },
+	{ "ixDPM_TABLE_64", REG_SMC, 0x3f0fc, &ixDPM_TABLE_64[0], sizeof(ixDPM_TABLE_64)/sizeof(ixDPM_TABLE_64[0]), 0, 0 },
+	{ "ixDPM_TABLE_65", REG_SMC, 0x3f100, &ixDPM_TABLE_65[0], sizeof(ixDPM_TABLE_65)/sizeof(ixDPM_TABLE_65[0]), 0, 0 },
+	{ "ixDPM_TABLE_66", REG_SMC, 0x3f104, &ixDPM_TABLE_66[0], sizeof(ixDPM_TABLE_66)/sizeof(ixDPM_TABLE_66[0]), 0, 0 },
+	{ "ixDPM_TABLE_67", REG_SMC, 0x3f108, &ixDPM_TABLE_67[0], sizeof(ixDPM_TABLE_67)/sizeof(ixDPM_TABLE_67[0]), 0, 0 },
+	{ "ixDPM_TABLE_68", REG_SMC, 0x3f10c, &ixDPM_TABLE_68[0], sizeof(ixDPM_TABLE_68)/sizeof(ixDPM_TABLE_68[0]), 0, 0 },
+	{ "ixDPM_TABLE_69", REG_SMC, 0x3f110, &ixDPM_TABLE_69[0], sizeof(ixDPM_TABLE_69)/sizeof(ixDPM_TABLE_69[0]), 0, 0 },
+	{ "ixDPM_TABLE_70", REG_SMC, 0x3f114, &ixDPM_TABLE_70[0], sizeof(ixDPM_TABLE_70)/sizeof(ixDPM_TABLE_70[0]), 0, 0 },
+	{ "ixDPM_TABLE_71", REG_SMC, 0x3f118, &ixDPM_TABLE_71[0], sizeof(ixDPM_TABLE_71)/sizeof(ixDPM_TABLE_71[0]), 0, 0 },
+	{ "ixDPM_TABLE_72", REG_SMC, 0x3f11c, &ixDPM_TABLE_72[0], sizeof(ixDPM_TABLE_72)/sizeof(ixDPM_TABLE_72[0]), 0, 0 },
+	{ "ixDPM_TABLE_73", REG_SMC, 0x3f120, &ixDPM_TABLE_73[0], sizeof(ixDPM_TABLE_73)/sizeof(ixDPM_TABLE_73[0]), 0, 0 },
+	{ "ixDPM_TABLE_74", REG_SMC, 0x3f124, &ixDPM_TABLE_74[0], sizeof(ixDPM_TABLE_74)/sizeof(ixDPM_TABLE_74[0]), 0, 0 },
+	{ "ixDPM_TABLE_75", REG_SMC, 0x3f128, &ixDPM_TABLE_75[0], sizeof(ixDPM_TABLE_75)/sizeof(ixDPM_TABLE_75[0]), 0, 0 },
+	{ "ixDPM_TABLE_76", REG_SMC, 0x3f12c, &ixDPM_TABLE_76[0], sizeof(ixDPM_TABLE_76)/sizeof(ixDPM_TABLE_76[0]), 0, 0 },
+	{ "ixDPM_TABLE_77", REG_SMC, 0x3f130, &ixDPM_TABLE_77[0], sizeof(ixDPM_TABLE_77)/sizeof(ixDPM_TABLE_77[0]), 0, 0 },
+	{ "ixDPM_TABLE_78", REG_SMC, 0x3f134, &ixDPM_TABLE_78[0], sizeof(ixDPM_TABLE_78)/sizeof(ixDPM_TABLE_78[0]), 0, 0 },
+	{ "ixDPM_TABLE_79", REG_SMC, 0x3f138, &ixDPM_TABLE_79[0], sizeof(ixDPM_TABLE_79)/sizeof(ixDPM_TABLE_79[0]), 0, 0 },
+	{ "ixDPM_TABLE_80", REG_SMC, 0x3f13c, &ixDPM_TABLE_80[0], sizeof(ixDPM_TABLE_80)/sizeof(ixDPM_TABLE_80[0]), 0, 0 },
+	{ "ixDPM_TABLE_81", REG_SMC, 0x3f140, &ixDPM_TABLE_81[0], sizeof(ixDPM_TABLE_81)/sizeof(ixDPM_TABLE_81[0]), 0, 0 },
+	{ "ixDPM_TABLE_82", REG_SMC, 0x3f144, &ixDPM_TABLE_82[0], sizeof(ixDPM_TABLE_82)/sizeof(ixDPM_TABLE_82[0]), 0, 0 },
+	{ "ixDPM_TABLE_83", REG_SMC, 0x3f148, &ixDPM_TABLE_83[0], sizeof(ixDPM_TABLE_83)/sizeof(ixDPM_TABLE_83[0]), 0, 0 },
+	{ "ixDPM_TABLE_84", REG_SMC, 0x3f14c, &ixDPM_TABLE_84[0], sizeof(ixDPM_TABLE_84)/sizeof(ixDPM_TABLE_84[0]), 0, 0 },
+	{ "ixDPM_TABLE_85", REG_SMC, 0x3f150, &ixDPM_TABLE_85[0], sizeof(ixDPM_TABLE_85)/sizeof(ixDPM_TABLE_85[0]), 0, 0 },
+	{ "ixDPM_TABLE_86", REG_SMC, 0x3f154, &ixDPM_TABLE_86[0], sizeof(ixDPM_TABLE_86)/sizeof(ixDPM_TABLE_86[0]), 0, 0 },
+	{ "ixDPM_TABLE_87", REG_SMC, 0x3f158, &ixDPM_TABLE_87[0], sizeof(ixDPM_TABLE_87)/sizeof(ixDPM_TABLE_87[0]), 0, 0 },
+	{ "ixDPM_TABLE_88", REG_SMC, 0x3f15c, &ixDPM_TABLE_88[0], sizeof(ixDPM_TABLE_88)/sizeof(ixDPM_TABLE_88[0]), 0, 0 },
+	{ "ixDPM_TABLE_89", REG_SMC, 0x3f160, &ixDPM_TABLE_89[0], sizeof(ixDPM_TABLE_89)/sizeof(ixDPM_TABLE_89[0]), 0, 0 },
+	{ "ixDPM_TABLE_90", REG_SMC, 0x3f164, &ixDPM_TABLE_90[0], sizeof(ixDPM_TABLE_90)/sizeof(ixDPM_TABLE_90[0]), 0, 0 },
+	{ "ixDPM_TABLE_91", REG_SMC, 0x3f168, &ixDPM_TABLE_91[0], sizeof(ixDPM_TABLE_91)/sizeof(ixDPM_TABLE_91[0]), 0, 0 },
+	{ "ixDPM_TABLE_92", REG_SMC, 0x3f16c, &ixDPM_TABLE_92[0], sizeof(ixDPM_TABLE_92)/sizeof(ixDPM_TABLE_92[0]), 0, 0 },
+	{ "ixDPM_TABLE_93", REG_SMC, 0x3f170, &ixDPM_TABLE_93[0], sizeof(ixDPM_TABLE_93)/sizeof(ixDPM_TABLE_93[0]), 0, 0 },
+	{ "ixDPM_TABLE_94", REG_SMC, 0x3f174, &ixDPM_TABLE_94[0], sizeof(ixDPM_TABLE_94)/sizeof(ixDPM_TABLE_94[0]), 0, 0 },
+	{ "ixDPM_TABLE_95", REG_SMC, 0x3f178, &ixDPM_TABLE_95[0], sizeof(ixDPM_TABLE_95)/sizeof(ixDPM_TABLE_95[0]), 0, 0 },
+	{ "ixDPM_TABLE_96", REG_SMC, 0x3f17c, &ixDPM_TABLE_96[0], sizeof(ixDPM_TABLE_96)/sizeof(ixDPM_TABLE_96[0]), 0, 0 },
+	{ "ixDPM_TABLE_97", REG_SMC, 0x3f180, &ixDPM_TABLE_97[0], sizeof(ixDPM_TABLE_97)/sizeof(ixDPM_TABLE_97[0]), 0, 0 },
+	{ "ixDPM_TABLE_98", REG_SMC, 0x3f184, &ixDPM_TABLE_98[0], sizeof(ixDPM_TABLE_98)/sizeof(ixDPM_TABLE_98[0]), 0, 0 },
+	{ "ixDPM_TABLE_99", REG_SMC, 0x3f188, &ixDPM_TABLE_99[0], sizeof(ixDPM_TABLE_99)/sizeof(ixDPM_TABLE_99[0]), 0, 0 },
+	{ "ixDPM_TABLE_100", REG_SMC, 0x3f18c, &ixDPM_TABLE_100[0], sizeof(ixDPM_TABLE_100)/sizeof(ixDPM_TABLE_100[0]), 0, 0 },
+	{ "ixDPM_TABLE_101", REG_SMC, 0x3f190, &ixDPM_TABLE_101[0], sizeof(ixDPM_TABLE_101)/sizeof(ixDPM_TABLE_101[0]), 0, 0 },
+	{ "ixDPM_TABLE_102", REG_SMC, 0x3f194, &ixDPM_TABLE_102[0], sizeof(ixDPM_TABLE_102)/sizeof(ixDPM_TABLE_102[0]), 0, 0 },
+	{ "ixDPM_TABLE_103", REG_SMC, 0x3f198, &ixDPM_TABLE_103[0], sizeof(ixDPM_TABLE_103)/sizeof(ixDPM_TABLE_103[0]), 0, 0 },
+	{ "ixDPM_TABLE_104", REG_SMC, 0x3f19c, &ixDPM_TABLE_104[0], sizeof(ixDPM_TABLE_104)/sizeof(ixDPM_TABLE_104[0]), 0, 0 },
+	{ "ixDPM_TABLE_105", REG_SMC, 0x3f1a0, &ixDPM_TABLE_105[0], sizeof(ixDPM_TABLE_105)/sizeof(ixDPM_TABLE_105[0]), 0, 0 },
+	{ "ixDPM_TABLE_106", REG_SMC, 0x3f1a4, &ixDPM_TABLE_106[0], sizeof(ixDPM_TABLE_106)/sizeof(ixDPM_TABLE_106[0]), 0, 0 },
+	{ "ixDPM_TABLE_107", REG_SMC, 0x3f1a8, &ixDPM_TABLE_107[0], sizeof(ixDPM_TABLE_107)/sizeof(ixDPM_TABLE_107[0]), 0, 0 },
+	{ "ixDPM_TABLE_108", REG_SMC, 0x3f1ac, &ixDPM_TABLE_108[0], sizeof(ixDPM_TABLE_108)/sizeof(ixDPM_TABLE_108[0]), 0, 0 },
+	{ "ixDPM_TABLE_109", REG_SMC, 0x3f1b0, &ixDPM_TABLE_109[0], sizeof(ixDPM_TABLE_109)/sizeof(ixDPM_TABLE_109[0]), 0, 0 },
+	{ "ixDPM_TABLE_110", REG_SMC, 0x3f1b4, &ixDPM_TABLE_110[0], sizeof(ixDPM_TABLE_110)/sizeof(ixDPM_TABLE_110[0]), 0, 0 },
+	{ "ixDPM_TABLE_111", REG_SMC, 0x3f1b8, &ixDPM_TABLE_111[0], sizeof(ixDPM_TABLE_111)/sizeof(ixDPM_TABLE_111[0]), 0, 0 },
+	{ "ixDPM_TABLE_112", REG_SMC, 0x3f1bc, &ixDPM_TABLE_112[0], sizeof(ixDPM_TABLE_112)/sizeof(ixDPM_TABLE_112[0]), 0, 0 },
+	{ "ixDPM_TABLE_113", REG_SMC, 0x3f1c0, &ixDPM_TABLE_113[0], sizeof(ixDPM_TABLE_113)/sizeof(ixDPM_TABLE_113[0]), 0, 0 },
+	{ "ixDPM_TABLE_114", REG_SMC, 0x3f1c4, &ixDPM_TABLE_114[0], sizeof(ixDPM_TABLE_114)/sizeof(ixDPM_TABLE_114[0]), 0, 0 },
+	{ "ixDPM_TABLE_115", REG_SMC, 0x3f1c8, &ixDPM_TABLE_115[0], sizeof(ixDPM_TABLE_115)/sizeof(ixDPM_TABLE_115[0]), 0, 0 },
+	{ "ixDPM_TABLE_116", REG_SMC, 0x3f1cc, &ixDPM_TABLE_116[0], sizeof(ixDPM_TABLE_116)/sizeof(ixDPM_TABLE_116[0]), 0, 0 },
+	{ "ixDPM_TABLE_117", REG_SMC, 0x3f1d0, &ixDPM_TABLE_117[0], sizeof(ixDPM_TABLE_117)/sizeof(ixDPM_TABLE_117[0]), 0, 0 },
+	{ "ixDPM_TABLE_118", REG_SMC, 0x3f1d4, &ixDPM_TABLE_118[0], sizeof(ixDPM_TABLE_118)/sizeof(ixDPM_TABLE_118[0]), 0, 0 },
+	{ "ixDPM_TABLE_119", REG_SMC, 0x3f1d8, &ixDPM_TABLE_119[0], sizeof(ixDPM_TABLE_119)/sizeof(ixDPM_TABLE_119[0]), 0, 0 },
+	{ "ixDPM_TABLE_120", REG_SMC, 0x3f1dc, &ixDPM_TABLE_120[0], sizeof(ixDPM_TABLE_120)/sizeof(ixDPM_TABLE_120[0]), 0, 0 },
+	{ "ixDPM_TABLE_121", REG_SMC, 0x3f1e0, &ixDPM_TABLE_121[0], sizeof(ixDPM_TABLE_121)/sizeof(ixDPM_TABLE_121[0]), 0, 0 },
+	{ "ixDPM_TABLE_122", REG_SMC, 0x3f1e4, &ixDPM_TABLE_122[0], sizeof(ixDPM_TABLE_122)/sizeof(ixDPM_TABLE_122[0]), 0, 0 },
+	{ "ixDPM_TABLE_123", REG_SMC, 0x3f1e8, &ixDPM_TABLE_123[0], sizeof(ixDPM_TABLE_123)/sizeof(ixDPM_TABLE_123[0]), 0, 0 },
+	{ "ixDPM_TABLE_124", REG_SMC, 0x3f1ec, &ixDPM_TABLE_124[0], sizeof(ixDPM_TABLE_124)/sizeof(ixDPM_TABLE_124[0]), 0, 0 },
+	{ "ixDPM_TABLE_125", REG_SMC, 0x3f1f0, &ixDPM_TABLE_125[0], sizeof(ixDPM_TABLE_125)/sizeof(ixDPM_TABLE_125[0]), 0, 0 },
+	{ "ixDPM_TABLE_126", REG_SMC, 0x3f1f4, &ixDPM_TABLE_126[0], sizeof(ixDPM_TABLE_126)/sizeof(ixDPM_TABLE_126[0]), 0, 0 },
+	{ "ixDPM_TABLE_127", REG_SMC, 0x3f1f8, &ixDPM_TABLE_127[0], sizeof(ixDPM_TABLE_127)/sizeof(ixDPM_TABLE_127[0]), 0, 0 },
+	{ "ixDPM_TABLE_128", REG_SMC, 0x3f1fc, &ixDPM_TABLE_128[0], sizeof(ixDPM_TABLE_128)/sizeof(ixDPM_TABLE_128[0]), 0, 0 },
+	{ "ixDPM_TABLE_129", REG_SMC, 0x3f200, &ixDPM_TABLE_129[0], sizeof(ixDPM_TABLE_129)/sizeof(ixDPM_TABLE_129[0]), 0, 0 },
+	{ "ixDPM_TABLE_130", REG_SMC, 0x3f204, &ixDPM_TABLE_130[0], sizeof(ixDPM_TABLE_130)/sizeof(ixDPM_TABLE_130[0]), 0, 0 },
+	{ "ixDPM_TABLE_131", REG_SMC, 0x3f208, &ixDPM_TABLE_131[0], sizeof(ixDPM_TABLE_131)/sizeof(ixDPM_TABLE_131[0]), 0, 0 },
+	{ "ixDPM_TABLE_132", REG_SMC, 0x3f20c, &ixDPM_TABLE_132[0], sizeof(ixDPM_TABLE_132)/sizeof(ixDPM_TABLE_132[0]), 0, 0 },
+	{ "ixDPM_TABLE_133", REG_SMC, 0x3f210, &ixDPM_TABLE_133[0], sizeof(ixDPM_TABLE_133)/sizeof(ixDPM_TABLE_133[0]), 0, 0 },
+	{ "ixDPM_TABLE_134", REG_SMC, 0x3f214, &ixDPM_TABLE_134[0], sizeof(ixDPM_TABLE_134)/sizeof(ixDPM_TABLE_134[0]), 0, 0 },
+	{ "ixDPM_TABLE_135", REG_SMC, 0x3f218, &ixDPM_TABLE_135[0], sizeof(ixDPM_TABLE_135)/sizeof(ixDPM_TABLE_135[0]), 0, 0 },
+	{ "ixDPM_TABLE_136", REG_SMC, 0x3f21c, &ixDPM_TABLE_136[0], sizeof(ixDPM_TABLE_136)/sizeof(ixDPM_TABLE_136[0]), 0, 0 },
+	{ "ixDPM_TABLE_137", REG_SMC, 0x3f220, &ixDPM_TABLE_137[0], sizeof(ixDPM_TABLE_137)/sizeof(ixDPM_TABLE_137[0]), 0, 0 },
+	{ "ixDPM_TABLE_138", REG_SMC, 0x3f224, &ixDPM_TABLE_138[0], sizeof(ixDPM_TABLE_138)/sizeof(ixDPM_TABLE_138[0]), 0, 0 },
+	{ "ixDPM_TABLE_139", REG_SMC, 0x3f228, &ixDPM_TABLE_139[0], sizeof(ixDPM_TABLE_139)/sizeof(ixDPM_TABLE_139[0]), 0, 0 },
+	{ "ixDPM_TABLE_140", REG_SMC, 0x3f22c, &ixDPM_TABLE_140[0], sizeof(ixDPM_TABLE_140)/sizeof(ixDPM_TABLE_140[0]), 0, 0 },
+	{ "ixDPM_TABLE_141", REG_SMC, 0x3f230, &ixDPM_TABLE_141[0], sizeof(ixDPM_TABLE_141)/sizeof(ixDPM_TABLE_141[0]), 0, 0 },
+	{ "ixDPM_TABLE_142", REG_SMC, 0x3f234, &ixDPM_TABLE_142[0], sizeof(ixDPM_TABLE_142)/sizeof(ixDPM_TABLE_142[0]), 0, 0 },
+	{ "ixDPM_TABLE_143", REG_SMC, 0x3f238, &ixDPM_TABLE_143[0], sizeof(ixDPM_TABLE_143)/sizeof(ixDPM_TABLE_143[0]), 0, 0 },
+	{ "ixDPM_TABLE_144", REG_SMC, 0x3f23c, &ixDPM_TABLE_144[0], sizeof(ixDPM_TABLE_144)/sizeof(ixDPM_TABLE_144[0]), 0, 0 },
+	{ "ixDPM_TABLE_145", REG_SMC, 0x3f240, &ixDPM_TABLE_145[0], sizeof(ixDPM_TABLE_145)/sizeof(ixDPM_TABLE_145[0]), 0, 0 },
+	{ "ixDPM_TABLE_146", REG_SMC, 0x3f244, &ixDPM_TABLE_146[0], sizeof(ixDPM_TABLE_146)/sizeof(ixDPM_TABLE_146[0]), 0, 0 },
+	{ "ixDPM_TABLE_147", REG_SMC, 0x3f248, &ixDPM_TABLE_147[0], sizeof(ixDPM_TABLE_147)/sizeof(ixDPM_TABLE_147[0]), 0, 0 },
+	{ "ixDPM_TABLE_148", REG_SMC, 0x3f24c, &ixDPM_TABLE_148[0], sizeof(ixDPM_TABLE_148)/sizeof(ixDPM_TABLE_148[0]), 0, 0 },
+	{ "ixDPM_TABLE_149", REG_SMC, 0x3f250, &ixDPM_TABLE_149[0], sizeof(ixDPM_TABLE_149)/sizeof(ixDPM_TABLE_149[0]), 0, 0 },
+	{ "ixDPM_TABLE_150", REG_SMC, 0x3f254, &ixDPM_TABLE_150[0], sizeof(ixDPM_TABLE_150)/sizeof(ixDPM_TABLE_150[0]), 0, 0 },
+	{ "ixDPM_TABLE_151", REG_SMC, 0x3f258, &ixDPM_TABLE_151[0], sizeof(ixDPM_TABLE_151)/sizeof(ixDPM_TABLE_151[0]), 0, 0 },
+	{ "ixDPM_TABLE_152", REG_SMC, 0x3f25c, &ixDPM_TABLE_152[0], sizeof(ixDPM_TABLE_152)/sizeof(ixDPM_TABLE_152[0]), 0, 0 },
+	{ "ixDPM_TABLE_153", REG_SMC, 0x3f260, &ixDPM_TABLE_153[0], sizeof(ixDPM_TABLE_153)/sizeof(ixDPM_TABLE_153[0]), 0, 0 },
+	{ "ixDPM_TABLE_154", REG_SMC, 0x3f264, &ixDPM_TABLE_154[0], sizeof(ixDPM_TABLE_154)/sizeof(ixDPM_TABLE_154[0]), 0, 0 },
+	{ "ixDPM_TABLE_155", REG_SMC, 0x3f268, &ixDPM_TABLE_155[0], sizeof(ixDPM_TABLE_155)/sizeof(ixDPM_TABLE_155[0]), 0, 0 },
+	{ "ixDPM_TABLE_156", REG_SMC, 0x3f26c, &ixDPM_TABLE_156[0], sizeof(ixDPM_TABLE_156)/sizeof(ixDPM_TABLE_156[0]), 0, 0 },
+	{ "ixDPM_TABLE_157", REG_SMC, 0x3f270, &ixDPM_TABLE_157[0], sizeof(ixDPM_TABLE_157)/sizeof(ixDPM_TABLE_157[0]), 0, 0 },
+	{ "ixDPM_TABLE_158", REG_SMC, 0x3f274, &ixDPM_TABLE_158[0], sizeof(ixDPM_TABLE_158)/sizeof(ixDPM_TABLE_158[0]), 0, 0 },
+	{ "ixDPM_TABLE_159", REG_SMC, 0x3f278, &ixDPM_TABLE_159[0], sizeof(ixDPM_TABLE_159)/sizeof(ixDPM_TABLE_159[0]), 0, 0 },
+	{ "ixDPM_TABLE_160", REG_SMC, 0x3f27c, &ixDPM_TABLE_160[0], sizeof(ixDPM_TABLE_160)/sizeof(ixDPM_TABLE_160[0]), 0, 0 },
+	{ "ixDPM_TABLE_161", REG_SMC, 0x3f280, &ixDPM_TABLE_161[0], sizeof(ixDPM_TABLE_161)/sizeof(ixDPM_TABLE_161[0]), 0, 0 },
+	{ "ixDPM_TABLE_162", REG_SMC, 0x3f284, &ixDPM_TABLE_162[0], sizeof(ixDPM_TABLE_162)/sizeof(ixDPM_TABLE_162[0]), 0, 0 },
+	{ "ixDPM_TABLE_163", REG_SMC, 0x3f288, &ixDPM_TABLE_163[0], sizeof(ixDPM_TABLE_163)/sizeof(ixDPM_TABLE_163[0]), 0, 0 },
+	{ "ixDPM_TABLE_164", REG_SMC, 0x3f28c, &ixDPM_TABLE_164[0], sizeof(ixDPM_TABLE_164)/sizeof(ixDPM_TABLE_164[0]), 0, 0 },
+	{ "ixDPM_TABLE_165", REG_SMC, 0x3f290, &ixDPM_TABLE_165[0], sizeof(ixDPM_TABLE_165)/sizeof(ixDPM_TABLE_165[0]), 0, 0 },
+	{ "ixDPM_TABLE_166", REG_SMC, 0x3f294, &ixDPM_TABLE_166[0], sizeof(ixDPM_TABLE_166)/sizeof(ixDPM_TABLE_166[0]), 0, 0 },
+	{ "ixDPM_TABLE_167", REG_SMC, 0x3f298, &ixDPM_TABLE_167[0], sizeof(ixDPM_TABLE_167)/sizeof(ixDPM_TABLE_167[0]), 0, 0 },
+	{ "ixDPM_TABLE_168", REG_SMC, 0x3f29c, &ixDPM_TABLE_168[0], sizeof(ixDPM_TABLE_168)/sizeof(ixDPM_TABLE_168[0]), 0, 0 },
+	{ "ixDPM_TABLE_169", REG_SMC, 0x3f2a0, &ixDPM_TABLE_169[0], sizeof(ixDPM_TABLE_169)/sizeof(ixDPM_TABLE_169[0]), 0, 0 },
+	{ "ixDPM_TABLE_170", REG_SMC, 0x3f2a4, &ixDPM_TABLE_170[0], sizeof(ixDPM_TABLE_170)/sizeof(ixDPM_TABLE_170[0]), 0, 0 },
+	{ "ixDPM_TABLE_171", REG_SMC, 0x3f2a8, &ixDPM_TABLE_171[0], sizeof(ixDPM_TABLE_171)/sizeof(ixDPM_TABLE_171[0]), 0, 0 },
+	{ "ixDPM_TABLE_172", REG_SMC, 0x3f2ac, &ixDPM_TABLE_172[0], sizeof(ixDPM_TABLE_172)/sizeof(ixDPM_TABLE_172[0]), 0, 0 },
+	{ "ixDPM_TABLE_173", REG_SMC, 0x3f2b0, &ixDPM_TABLE_173[0], sizeof(ixDPM_TABLE_173)/sizeof(ixDPM_TABLE_173[0]), 0, 0 },
+	{ "ixDPM_TABLE_174", REG_SMC, 0x3f2b4, &ixDPM_TABLE_174[0], sizeof(ixDPM_TABLE_174)/sizeof(ixDPM_TABLE_174[0]), 0, 0 },
+	{ "ixDPM_TABLE_175", REG_SMC, 0x3f2b8, &ixDPM_TABLE_175[0], sizeof(ixDPM_TABLE_175)/sizeof(ixDPM_TABLE_175[0]), 0, 0 },
+	{ "ixDPM_TABLE_176", REG_SMC, 0x3f2bc, &ixDPM_TABLE_176[0], sizeof(ixDPM_TABLE_176)/sizeof(ixDPM_TABLE_176[0]), 0, 0 },
+	{ "ixDPM_TABLE_177", REG_SMC, 0x3f2c0, &ixDPM_TABLE_177[0], sizeof(ixDPM_TABLE_177)/sizeof(ixDPM_TABLE_177[0]), 0, 0 },
+	{ "ixDPM_TABLE_178", REG_SMC, 0x3f2c4, &ixDPM_TABLE_178[0], sizeof(ixDPM_TABLE_178)/sizeof(ixDPM_TABLE_178[0]), 0, 0 },
+	{ "ixDPM_TABLE_179", REG_SMC, 0x3f2c8, &ixDPM_TABLE_179[0], sizeof(ixDPM_TABLE_179)/sizeof(ixDPM_TABLE_179[0]), 0, 0 },
+	{ "ixDPM_TABLE_180", REG_SMC, 0x3f2cc, &ixDPM_TABLE_180[0], sizeof(ixDPM_TABLE_180)/sizeof(ixDPM_TABLE_180[0]), 0, 0 },
+	{ "ixDPM_TABLE_181", REG_SMC, 0x3f2d0, &ixDPM_TABLE_181[0], sizeof(ixDPM_TABLE_181)/sizeof(ixDPM_TABLE_181[0]), 0, 0 },
+	{ "ixDPM_TABLE_182", REG_SMC, 0x3f2d4, &ixDPM_TABLE_182[0], sizeof(ixDPM_TABLE_182)/sizeof(ixDPM_TABLE_182[0]), 0, 0 },
+	{ "ixDPM_TABLE_183", REG_SMC, 0x3f2d8, &ixDPM_TABLE_183[0], sizeof(ixDPM_TABLE_183)/sizeof(ixDPM_TABLE_183[0]), 0, 0 },
+	{ "ixDPM_TABLE_184", REG_SMC, 0x3f2dc, &ixDPM_TABLE_184[0], sizeof(ixDPM_TABLE_184)/sizeof(ixDPM_TABLE_184[0]), 0, 0 },
+	{ "ixDPM_TABLE_185", REG_SMC, 0x3f2e0, &ixDPM_TABLE_185[0], sizeof(ixDPM_TABLE_185)/sizeof(ixDPM_TABLE_185[0]), 0, 0 },
+	{ "ixDPM_TABLE_186", REG_SMC, 0x3f2e4, &ixDPM_TABLE_186[0], sizeof(ixDPM_TABLE_186)/sizeof(ixDPM_TABLE_186[0]), 0, 0 },
+	{ "ixDPM_TABLE_187", REG_SMC, 0x3f2e8, &ixDPM_TABLE_187[0], sizeof(ixDPM_TABLE_187)/sizeof(ixDPM_TABLE_187[0]), 0, 0 },
+	{ "ixDPM_TABLE_188", REG_SMC, 0x3f2ec, &ixDPM_TABLE_188[0], sizeof(ixDPM_TABLE_188)/sizeof(ixDPM_TABLE_188[0]), 0, 0 },
+	{ "ixDPM_TABLE_189", REG_SMC, 0x3f2f0, &ixDPM_TABLE_189[0], sizeof(ixDPM_TABLE_189)/sizeof(ixDPM_TABLE_189[0]), 0, 0 },
+	{ "ixDPM_TABLE_190", REG_SMC, 0x3f2f4, &ixDPM_TABLE_190[0], sizeof(ixDPM_TABLE_190)/sizeof(ixDPM_TABLE_190[0]), 0, 0 },
+	{ "ixDPM_TABLE_191", REG_SMC, 0x3f2f8, &ixDPM_TABLE_191[0], sizeof(ixDPM_TABLE_191)/sizeof(ixDPM_TABLE_191[0]), 0, 0 },
+	{ "ixDPM_TABLE_192", REG_SMC, 0x3f2fc, &ixDPM_TABLE_192[0], sizeof(ixDPM_TABLE_192)/sizeof(ixDPM_TABLE_192[0]), 0, 0 },
+	{ "ixDPM_TABLE_193", REG_SMC, 0x3f300, &ixDPM_TABLE_193[0], sizeof(ixDPM_TABLE_193)/sizeof(ixDPM_TABLE_193[0]), 0, 0 },
+	{ "ixDPM_TABLE_194", REG_SMC, 0x3f304, &ixDPM_TABLE_194[0], sizeof(ixDPM_TABLE_194)/sizeof(ixDPM_TABLE_194[0]), 0, 0 },
+	{ "ixDPM_TABLE_195", REG_SMC, 0x3f308, &ixDPM_TABLE_195[0], sizeof(ixDPM_TABLE_195)/sizeof(ixDPM_TABLE_195[0]), 0, 0 },
+	{ "ixDPM_TABLE_196", REG_SMC, 0x3f30c, &ixDPM_TABLE_196[0], sizeof(ixDPM_TABLE_196)/sizeof(ixDPM_TABLE_196[0]), 0, 0 },
+	{ "ixDPM_TABLE_197", REG_SMC, 0x3f310, &ixDPM_TABLE_197[0], sizeof(ixDPM_TABLE_197)/sizeof(ixDPM_TABLE_197[0]), 0, 0 },
+	{ "ixDPM_TABLE_198", REG_SMC, 0x3f314, &ixDPM_TABLE_198[0], sizeof(ixDPM_TABLE_198)/sizeof(ixDPM_TABLE_198[0]), 0, 0 },
+	{ "ixDPM_TABLE_199", REG_SMC, 0x3f318, &ixDPM_TABLE_199[0], sizeof(ixDPM_TABLE_199)/sizeof(ixDPM_TABLE_199[0]), 0, 0 },
+	{ "ixDPM_TABLE_200", REG_SMC, 0x3f31c, &ixDPM_TABLE_200[0], sizeof(ixDPM_TABLE_200)/sizeof(ixDPM_TABLE_200[0]), 0, 0 },
+	{ "ixDPM_TABLE_201", REG_SMC, 0x3f320, &ixDPM_TABLE_201[0], sizeof(ixDPM_TABLE_201)/sizeof(ixDPM_TABLE_201[0]), 0, 0 },
+	{ "ixDPM_TABLE_202", REG_SMC, 0x3f324, &ixDPM_TABLE_202[0], sizeof(ixDPM_TABLE_202)/sizeof(ixDPM_TABLE_202[0]), 0, 0 },
+	{ "ixDPM_TABLE_203", REG_SMC, 0x3f328, &ixDPM_TABLE_203[0], sizeof(ixDPM_TABLE_203)/sizeof(ixDPM_TABLE_203[0]), 0, 0 },
+	{ "ixDPM_TABLE_204", REG_SMC, 0x3f32c, &ixDPM_TABLE_204[0], sizeof(ixDPM_TABLE_204)/sizeof(ixDPM_TABLE_204[0]), 0, 0 },
+	{ "ixDPM_TABLE_205", REG_SMC, 0x3f330, &ixDPM_TABLE_205[0], sizeof(ixDPM_TABLE_205)/sizeof(ixDPM_TABLE_205[0]), 0, 0 },
+	{ "ixDPM_TABLE_206", REG_SMC, 0x3f334, &ixDPM_TABLE_206[0], sizeof(ixDPM_TABLE_206)/sizeof(ixDPM_TABLE_206[0]), 0, 0 },
+	{ "ixDPM_TABLE_207", REG_SMC, 0x3f338, &ixDPM_TABLE_207[0], sizeof(ixDPM_TABLE_207)/sizeof(ixDPM_TABLE_207[0]), 0, 0 },
+	{ "ixDPM_TABLE_208", REG_SMC, 0x3f33c, &ixDPM_TABLE_208[0], sizeof(ixDPM_TABLE_208)/sizeof(ixDPM_TABLE_208[0]), 0, 0 },
+	{ "ixDPM_TABLE_209", REG_SMC, 0x3f340, &ixDPM_TABLE_209[0], sizeof(ixDPM_TABLE_209)/sizeof(ixDPM_TABLE_209[0]), 0, 0 },
+	{ "ixDPM_TABLE_210", REG_SMC, 0x3f344, &ixDPM_TABLE_210[0], sizeof(ixDPM_TABLE_210)/sizeof(ixDPM_TABLE_210[0]), 0, 0 },
+	{ "ixDPM_TABLE_211", REG_SMC, 0x3f348, &ixDPM_TABLE_211[0], sizeof(ixDPM_TABLE_211)/sizeof(ixDPM_TABLE_211[0]), 0, 0 },
+	{ "ixDPM_TABLE_212", REG_SMC, 0x3f34c, &ixDPM_TABLE_212[0], sizeof(ixDPM_TABLE_212)/sizeof(ixDPM_TABLE_212[0]), 0, 0 },
+	{ "ixDPM_TABLE_213", REG_SMC, 0x3f350, &ixDPM_TABLE_213[0], sizeof(ixDPM_TABLE_213)/sizeof(ixDPM_TABLE_213[0]), 0, 0 },
+	{ "ixDPM_TABLE_214", REG_SMC, 0x3f354, &ixDPM_TABLE_214[0], sizeof(ixDPM_TABLE_214)/sizeof(ixDPM_TABLE_214[0]), 0, 0 },
+	{ "ixDPM_TABLE_215", REG_SMC, 0x3f358, &ixDPM_TABLE_215[0], sizeof(ixDPM_TABLE_215)/sizeof(ixDPM_TABLE_215[0]), 0, 0 },
+	{ "ixDPM_TABLE_216", REG_SMC, 0x3f35c, &ixDPM_TABLE_216[0], sizeof(ixDPM_TABLE_216)/sizeof(ixDPM_TABLE_216[0]), 0, 0 },
+	{ "ixDPM_TABLE_217", REG_SMC, 0x3f360, &ixDPM_TABLE_217[0], sizeof(ixDPM_TABLE_217)/sizeof(ixDPM_TABLE_217[0]), 0, 0 },
+	{ "ixDPM_TABLE_218", REG_SMC, 0x3f364, &ixDPM_TABLE_218[0], sizeof(ixDPM_TABLE_218)/sizeof(ixDPM_TABLE_218[0]), 0, 0 },
+	{ "ixDPM_TABLE_219", REG_SMC, 0x3f368, &ixDPM_TABLE_219[0], sizeof(ixDPM_TABLE_219)/sizeof(ixDPM_TABLE_219[0]), 0, 0 },
+	{ "ixDPM_TABLE_220", REG_SMC, 0x3f36c, &ixDPM_TABLE_220[0], sizeof(ixDPM_TABLE_220)/sizeof(ixDPM_TABLE_220[0]), 0, 0 },
+	{ "ixDPM_TABLE_221", REG_SMC, 0x3f370, &ixDPM_TABLE_221[0], sizeof(ixDPM_TABLE_221)/sizeof(ixDPM_TABLE_221[0]), 0, 0 },
+	{ "ixDPM_TABLE_222", REG_SMC, 0x3f374, &ixDPM_TABLE_222[0], sizeof(ixDPM_TABLE_222)/sizeof(ixDPM_TABLE_222[0]), 0, 0 },
+	{ "ixDPM_TABLE_223", REG_SMC, 0x3f378, &ixDPM_TABLE_223[0], sizeof(ixDPM_TABLE_223)/sizeof(ixDPM_TABLE_223[0]), 0, 0 },
+	{ "ixDPM_TABLE_224", REG_SMC, 0x3f37c, &ixDPM_TABLE_224[0], sizeof(ixDPM_TABLE_224)/sizeof(ixDPM_TABLE_224[0]), 0, 0 },
+	{ "ixDPM_TABLE_225", REG_SMC, 0x3f380, &ixDPM_TABLE_225[0], sizeof(ixDPM_TABLE_225)/sizeof(ixDPM_TABLE_225[0]), 0, 0 },
+	{ "ixDPM_TABLE_226", REG_SMC, 0x3f384, &ixDPM_TABLE_226[0], sizeof(ixDPM_TABLE_226)/sizeof(ixDPM_TABLE_226[0]), 0, 0 },
+	{ "ixDPM_TABLE_227", REG_SMC, 0x3f388, &ixDPM_TABLE_227[0], sizeof(ixDPM_TABLE_227)/sizeof(ixDPM_TABLE_227[0]), 0, 0 },
+	{ "ixDPM_TABLE_228", REG_SMC, 0x3f38c, &ixDPM_TABLE_228[0], sizeof(ixDPM_TABLE_228)/sizeof(ixDPM_TABLE_228[0]), 0, 0 },
+	{ "ixDPM_TABLE_229", REG_SMC, 0x3f390, &ixDPM_TABLE_229[0], sizeof(ixDPM_TABLE_229)/sizeof(ixDPM_TABLE_229[0]), 0, 0 },
+	{ "ixDPM_TABLE_230", REG_SMC, 0x3f394, &ixDPM_TABLE_230[0], sizeof(ixDPM_TABLE_230)/sizeof(ixDPM_TABLE_230[0]), 0, 0 },
+	{ "ixDPM_TABLE_231", REG_SMC, 0x3f398, &ixDPM_TABLE_231[0], sizeof(ixDPM_TABLE_231)/sizeof(ixDPM_TABLE_231[0]), 0, 0 },
+	{ "ixDPM_TABLE_232", REG_SMC, 0x3f39c, &ixDPM_TABLE_232[0], sizeof(ixDPM_TABLE_232)/sizeof(ixDPM_TABLE_232[0]), 0, 0 },
+	{ "ixDPM_TABLE_233", REG_SMC, 0x3f3a0, &ixDPM_TABLE_233[0], sizeof(ixDPM_TABLE_233)/sizeof(ixDPM_TABLE_233[0]), 0, 0 },
+	{ "ixDPM_TABLE_234", REG_SMC, 0x3f3a4, &ixDPM_TABLE_234[0], sizeof(ixDPM_TABLE_234)/sizeof(ixDPM_TABLE_234[0]), 0, 0 },
+	{ "ixDPM_TABLE_235", REG_SMC, 0x3f3a8, &ixDPM_TABLE_235[0], sizeof(ixDPM_TABLE_235)/sizeof(ixDPM_TABLE_235[0]), 0, 0 },
+	{ "ixDPM_TABLE_236", REG_SMC, 0x3f3ac, &ixDPM_TABLE_236[0], sizeof(ixDPM_TABLE_236)/sizeof(ixDPM_TABLE_236[0]), 0, 0 },
+	{ "ixDPM_TABLE_237", REG_SMC, 0x3f3b0, &ixDPM_TABLE_237[0], sizeof(ixDPM_TABLE_237)/sizeof(ixDPM_TABLE_237[0]), 0, 0 },
+	{ "ixDPM_TABLE_238", REG_SMC, 0x3f3b4, &ixDPM_TABLE_238[0], sizeof(ixDPM_TABLE_238)/sizeof(ixDPM_TABLE_238[0]), 0, 0 },
+	{ "ixDPM_TABLE_239", REG_SMC, 0x3f3b8, &ixDPM_TABLE_239[0], sizeof(ixDPM_TABLE_239)/sizeof(ixDPM_TABLE_239[0]), 0, 0 },
+	{ "ixDPM_TABLE_240", REG_SMC, 0x3f3bc, &ixDPM_TABLE_240[0], sizeof(ixDPM_TABLE_240)/sizeof(ixDPM_TABLE_240[0]), 0, 0 },
+	{ "ixDPM_TABLE_241", REG_SMC, 0x3f3c0, &ixDPM_TABLE_241[0], sizeof(ixDPM_TABLE_241)/sizeof(ixDPM_TABLE_241[0]), 0, 0 },
+	{ "ixDPM_TABLE_242", REG_SMC, 0x3f3c4, &ixDPM_TABLE_242[0], sizeof(ixDPM_TABLE_242)/sizeof(ixDPM_TABLE_242[0]), 0, 0 },
+	{ "ixDPM_TABLE_243", REG_SMC, 0x3f3c8, &ixDPM_TABLE_243[0], sizeof(ixDPM_TABLE_243)/sizeof(ixDPM_TABLE_243[0]), 0, 0 },
+	{ "ixDPM_TABLE_244", REG_SMC, 0x3f3cc, &ixDPM_TABLE_244[0], sizeof(ixDPM_TABLE_244)/sizeof(ixDPM_TABLE_244[0]), 0, 0 },
+	{ "ixDPM_TABLE_245", REG_SMC, 0x3f3d0, &ixDPM_TABLE_245[0], sizeof(ixDPM_TABLE_245)/sizeof(ixDPM_TABLE_245[0]), 0, 0 },
+	{ "ixDPM_TABLE_246", REG_SMC, 0x3f3d4, &ixDPM_TABLE_246[0], sizeof(ixDPM_TABLE_246)/sizeof(ixDPM_TABLE_246[0]), 0, 0 },
+	{ "ixDPM_TABLE_247", REG_SMC, 0x3f3d8, &ixDPM_TABLE_247[0], sizeof(ixDPM_TABLE_247)/sizeof(ixDPM_TABLE_247[0]), 0, 0 },
+	{ "ixDPM_TABLE_248", REG_SMC, 0x3f3dc, &ixDPM_TABLE_248[0], sizeof(ixDPM_TABLE_248)/sizeof(ixDPM_TABLE_248[0]), 0, 0 },
+	{ "ixDPM_TABLE_249", REG_SMC, 0x3f3e0, &ixDPM_TABLE_249[0], sizeof(ixDPM_TABLE_249)/sizeof(ixDPM_TABLE_249[0]), 0, 0 },
+	{ "ixDPM_TABLE_250", REG_SMC, 0x3f3e4, &ixDPM_TABLE_250[0], sizeof(ixDPM_TABLE_250)/sizeof(ixDPM_TABLE_250[0]), 0, 0 },
+	{ "ixDPM_TABLE_251", REG_SMC, 0x3f3e8, &ixDPM_TABLE_251[0], sizeof(ixDPM_TABLE_251)/sizeof(ixDPM_TABLE_251[0]), 0, 0 },
+	{ "ixDPM_TABLE_252", REG_SMC, 0x3f3ec, &ixDPM_TABLE_252[0], sizeof(ixDPM_TABLE_252)/sizeof(ixDPM_TABLE_252[0]), 0, 0 },
+	{ "ixDPM_TABLE_253", REG_SMC, 0x3f3f0, &ixDPM_TABLE_253[0], sizeof(ixDPM_TABLE_253)/sizeof(ixDPM_TABLE_253[0]), 0, 0 },
+	{ "ixDPM_TABLE_254", REG_SMC, 0x3f3f4, &ixDPM_TABLE_254[0], sizeof(ixDPM_TABLE_254)/sizeof(ixDPM_TABLE_254[0]), 0, 0 },
+	{ "ixDPM_TABLE_255", REG_SMC, 0x3f3f8, &ixDPM_TABLE_255[0], sizeof(ixDPM_TABLE_255)/sizeof(ixDPM_TABLE_255[0]), 0, 0 },
+	{ "ixDPM_TABLE_256", REG_SMC, 0x3f3fc, &ixDPM_TABLE_256[0], sizeof(ixDPM_TABLE_256)/sizeof(ixDPM_TABLE_256[0]), 0, 0 },
+	{ "ixDPM_TABLE_257", REG_SMC, 0x3f400, &ixDPM_TABLE_257[0], sizeof(ixDPM_TABLE_257)/sizeof(ixDPM_TABLE_257[0]), 0, 0 },
+	{ "ixDPM_TABLE_258", REG_SMC, 0x3f404, &ixDPM_TABLE_258[0], sizeof(ixDPM_TABLE_258)/sizeof(ixDPM_TABLE_258[0]), 0, 0 },
+	{ "ixDPM_TABLE_259", REG_SMC, 0x3f408, &ixDPM_TABLE_259[0], sizeof(ixDPM_TABLE_259)/sizeof(ixDPM_TABLE_259[0]), 0, 0 },
+	{ "ixDPM_TABLE_260", REG_SMC, 0x3f40c, &ixDPM_TABLE_260[0], sizeof(ixDPM_TABLE_260)/sizeof(ixDPM_TABLE_260[0]), 0, 0 },
+	{ "ixDPM_TABLE_261", REG_SMC, 0x3f410, &ixDPM_TABLE_261[0], sizeof(ixDPM_TABLE_261)/sizeof(ixDPM_TABLE_261[0]), 0, 0 },
+	{ "ixDPM_TABLE_262", REG_SMC, 0x3f414, &ixDPM_TABLE_262[0], sizeof(ixDPM_TABLE_262)/sizeof(ixDPM_TABLE_262[0]), 0, 0 },
+	{ "ixDPM_TABLE_263", REG_SMC, 0x3f418, &ixDPM_TABLE_263[0], sizeof(ixDPM_TABLE_263)/sizeof(ixDPM_TABLE_263[0]), 0, 0 },
+	{ "ixDPM_TABLE_264", REG_SMC, 0x3f41c, &ixDPM_TABLE_264[0], sizeof(ixDPM_TABLE_264)/sizeof(ixDPM_TABLE_264[0]), 0, 0 },
+	{ "ixDPM_TABLE_265", REG_SMC, 0x3f420, &ixDPM_TABLE_265[0], sizeof(ixDPM_TABLE_265)/sizeof(ixDPM_TABLE_265[0]), 0, 0 },
+	{ "ixDPM_TABLE_266", REG_SMC, 0x3f424, &ixDPM_TABLE_266[0], sizeof(ixDPM_TABLE_266)/sizeof(ixDPM_TABLE_266[0]), 0, 0 },
+	{ "ixDPM_TABLE_267", REG_SMC, 0x3f428, &ixDPM_TABLE_267[0], sizeof(ixDPM_TABLE_267)/sizeof(ixDPM_TABLE_267[0]), 0, 0 },
+	{ "ixDPM_TABLE_268", REG_SMC, 0x3f42c, &ixDPM_TABLE_268[0], sizeof(ixDPM_TABLE_268)/sizeof(ixDPM_TABLE_268[0]), 0, 0 },
+	{ "ixDPM_TABLE_269", REG_SMC, 0x3f430, &ixDPM_TABLE_269[0], sizeof(ixDPM_TABLE_269)/sizeof(ixDPM_TABLE_269[0]), 0, 0 },
+	{ "ixDPM_TABLE_270", REG_SMC, 0x3f434, &ixDPM_TABLE_270[0], sizeof(ixDPM_TABLE_270)/sizeof(ixDPM_TABLE_270[0]), 0, 0 },
+	{ "ixDPM_TABLE_271", REG_SMC, 0x3f438, &ixDPM_TABLE_271[0], sizeof(ixDPM_TABLE_271)/sizeof(ixDPM_TABLE_271[0]), 0, 0 },
+	{ "ixDPM_TABLE_272", REG_SMC, 0x3f43c, &ixDPM_TABLE_272[0], sizeof(ixDPM_TABLE_272)/sizeof(ixDPM_TABLE_272[0]), 0, 0 },
+	{ "ixDPM_TABLE_273", REG_SMC, 0x3f440, &ixDPM_TABLE_273[0], sizeof(ixDPM_TABLE_273)/sizeof(ixDPM_TABLE_273[0]), 0, 0 },
+	{ "ixDPM_TABLE_274", REG_SMC, 0x3f444, &ixDPM_TABLE_274[0], sizeof(ixDPM_TABLE_274)/sizeof(ixDPM_TABLE_274[0]), 0, 0 },
+	{ "ixDPM_TABLE_275", REG_SMC, 0x3f448, &ixDPM_TABLE_275[0], sizeof(ixDPM_TABLE_275)/sizeof(ixDPM_TABLE_275[0]), 0, 0 },
+	{ "ixDPM_TABLE_276", REG_SMC, 0x3f44c, &ixDPM_TABLE_276[0], sizeof(ixDPM_TABLE_276)/sizeof(ixDPM_TABLE_276[0]), 0, 0 },
+	{ "ixDPM_TABLE_277", REG_SMC, 0x3f450, &ixDPM_TABLE_277[0], sizeof(ixDPM_TABLE_277)/sizeof(ixDPM_TABLE_277[0]), 0, 0 },
+	{ "ixDPM_TABLE_278", REG_SMC, 0x3f454, &ixDPM_TABLE_278[0], sizeof(ixDPM_TABLE_278)/sizeof(ixDPM_TABLE_278[0]), 0, 0 },
+	{ "ixDPM_TABLE_279", REG_SMC, 0x3f458, &ixDPM_TABLE_279[0], sizeof(ixDPM_TABLE_279)/sizeof(ixDPM_TABLE_279[0]), 0, 0 },
+	{ "ixDPM_TABLE_280", REG_SMC, 0x3f45c, &ixDPM_TABLE_280[0], sizeof(ixDPM_TABLE_280)/sizeof(ixDPM_TABLE_280[0]), 0, 0 },
+	{ "ixDPM_TABLE_281", REG_SMC, 0x3f460, &ixDPM_TABLE_281[0], sizeof(ixDPM_TABLE_281)/sizeof(ixDPM_TABLE_281[0]), 0, 0 },
+	{ "ixDPM_TABLE_282", REG_SMC, 0x3f464, &ixDPM_TABLE_282[0], sizeof(ixDPM_TABLE_282)/sizeof(ixDPM_TABLE_282[0]), 0, 0 },
+	{ "ixDPM_TABLE_283", REG_SMC, 0x3f468, &ixDPM_TABLE_283[0], sizeof(ixDPM_TABLE_283)/sizeof(ixDPM_TABLE_283[0]), 0, 0 },
+	{ "ixDPM_TABLE_284", REG_SMC, 0x3f46c, &ixDPM_TABLE_284[0], sizeof(ixDPM_TABLE_284)/sizeof(ixDPM_TABLE_284[0]), 0, 0 },
+	{ "ixDPM_TABLE_285", REG_SMC, 0x3f470, &ixDPM_TABLE_285[0], sizeof(ixDPM_TABLE_285)/sizeof(ixDPM_TABLE_285[0]), 0, 0 },
+	{ "ixDPM_TABLE_286", REG_SMC, 0x3f474, &ixDPM_TABLE_286[0], sizeof(ixDPM_TABLE_286)/sizeof(ixDPM_TABLE_286[0]), 0, 0 },
+	{ "ixDPM_TABLE_287", REG_SMC, 0x3f478, &ixDPM_TABLE_287[0], sizeof(ixDPM_TABLE_287)/sizeof(ixDPM_TABLE_287[0]), 0, 0 },
+	{ "ixDPM_TABLE_288", REG_SMC, 0x3f47c, &ixDPM_TABLE_288[0], sizeof(ixDPM_TABLE_288)/sizeof(ixDPM_TABLE_288[0]), 0, 0 },
+	{ "ixDPM_TABLE_289", REG_SMC, 0x3f480, &ixDPM_TABLE_289[0], sizeof(ixDPM_TABLE_289)/sizeof(ixDPM_TABLE_289[0]), 0, 0 },
+	{ "ixDPM_TABLE_290", REG_SMC, 0x3f484, &ixDPM_TABLE_290[0], sizeof(ixDPM_TABLE_290)/sizeof(ixDPM_TABLE_290[0]), 0, 0 },
+	{ "ixDPM_TABLE_291", REG_SMC, 0x3f488, &ixDPM_TABLE_291[0], sizeof(ixDPM_TABLE_291)/sizeof(ixDPM_TABLE_291[0]), 0, 0 },
+	{ "ixDPM_TABLE_292", REG_SMC, 0x3f48c, &ixDPM_TABLE_292[0], sizeof(ixDPM_TABLE_292)/sizeof(ixDPM_TABLE_292[0]), 0, 0 },
+	{ "ixDPM_TABLE_293", REG_SMC, 0x3f490, &ixDPM_TABLE_293[0], sizeof(ixDPM_TABLE_293)/sizeof(ixDPM_TABLE_293[0]), 0, 0 },
+	{ "ixDPM_TABLE_294", REG_SMC, 0x3f494, &ixDPM_TABLE_294[0], sizeof(ixDPM_TABLE_294)/sizeof(ixDPM_TABLE_294[0]), 0, 0 },
+	{ "ixDPM_TABLE_295", REG_SMC, 0x3f498, &ixDPM_TABLE_295[0], sizeof(ixDPM_TABLE_295)/sizeof(ixDPM_TABLE_295[0]), 0, 0 },
+	{ "ixDPM_TABLE_296", REG_SMC, 0x3f49c, &ixDPM_TABLE_296[0], sizeof(ixDPM_TABLE_296)/sizeof(ixDPM_TABLE_296[0]), 0, 0 },
+	{ "ixDPM_TABLE_297", REG_SMC, 0x3f4a0, &ixDPM_TABLE_297[0], sizeof(ixDPM_TABLE_297)/sizeof(ixDPM_TABLE_297[0]), 0, 0 },
+	{ "ixDPM_TABLE_298", REG_SMC, 0x3f4a4, &ixDPM_TABLE_298[0], sizeof(ixDPM_TABLE_298)/sizeof(ixDPM_TABLE_298[0]), 0, 0 },
+	{ "ixDPM_TABLE_299", REG_SMC, 0x3f4a8, &ixDPM_TABLE_299[0], sizeof(ixDPM_TABLE_299)/sizeof(ixDPM_TABLE_299[0]), 0, 0 },
+	{ "ixDPM_TABLE_300", REG_SMC, 0x3f4ac, &ixDPM_TABLE_300[0], sizeof(ixDPM_TABLE_300)/sizeof(ixDPM_TABLE_300[0]), 0, 0 },
+	{ "ixDPM_TABLE_301", REG_SMC, 0x3f4b0, &ixDPM_TABLE_301[0], sizeof(ixDPM_TABLE_301)/sizeof(ixDPM_TABLE_301[0]), 0, 0 },
+	{ "ixDPM_TABLE_302", REG_SMC, 0x3f4b4, &ixDPM_TABLE_302[0], sizeof(ixDPM_TABLE_302)/sizeof(ixDPM_TABLE_302[0]), 0, 0 },
+	{ "ixDPM_TABLE_303", REG_SMC, 0x3f4b8, &ixDPM_TABLE_303[0], sizeof(ixDPM_TABLE_303)/sizeof(ixDPM_TABLE_303[0]), 0, 0 },
+	{ "ixDPM_TABLE_304", REG_SMC, 0x3f4bc, &ixDPM_TABLE_304[0], sizeof(ixDPM_TABLE_304)/sizeof(ixDPM_TABLE_304[0]), 0, 0 },
+	{ "ixDPM_TABLE_305", REG_SMC, 0x3f4c0, &ixDPM_TABLE_305[0], sizeof(ixDPM_TABLE_305)/sizeof(ixDPM_TABLE_305[0]), 0, 0 },
+	{ "ixDPM_TABLE_306", REG_SMC, 0x3f4c4, &ixDPM_TABLE_306[0], sizeof(ixDPM_TABLE_306)/sizeof(ixDPM_TABLE_306[0]), 0, 0 },
+	{ "ixDPM_TABLE_307", REG_SMC, 0x3f4c8, &ixDPM_TABLE_307[0], sizeof(ixDPM_TABLE_307)/sizeof(ixDPM_TABLE_307[0]), 0, 0 },
+	{ "ixDPM_TABLE_308", REG_SMC, 0x3f4cc, &ixDPM_TABLE_308[0], sizeof(ixDPM_TABLE_308)/sizeof(ixDPM_TABLE_308[0]), 0, 0 },
+	{ "ixDPM_TABLE_309", REG_SMC, 0x3f4d0, &ixDPM_TABLE_309[0], sizeof(ixDPM_TABLE_309)/sizeof(ixDPM_TABLE_309[0]), 0, 0 },
+	{ "ixDPM_TABLE_310", REG_SMC, 0x3f4d4, &ixDPM_TABLE_310[0], sizeof(ixDPM_TABLE_310)/sizeof(ixDPM_TABLE_310[0]), 0, 0 },
+	{ "ixDPM_TABLE_311", REG_SMC, 0x3f4d8, &ixDPM_TABLE_311[0], sizeof(ixDPM_TABLE_311)/sizeof(ixDPM_TABLE_311[0]), 0, 0 },
+	{ "ixDPM_TABLE_312", REG_SMC, 0x3f4dc, &ixDPM_TABLE_312[0], sizeof(ixDPM_TABLE_312)/sizeof(ixDPM_TABLE_312[0]), 0, 0 },
+	{ "ixDPM_TABLE_313", REG_SMC, 0x3f4e0, &ixDPM_TABLE_313[0], sizeof(ixDPM_TABLE_313)/sizeof(ixDPM_TABLE_313[0]), 0, 0 },
+	{ "ixDPM_TABLE_314", REG_SMC, 0x3f4e4, &ixDPM_TABLE_314[0], sizeof(ixDPM_TABLE_314)/sizeof(ixDPM_TABLE_314[0]), 0, 0 },
+	{ "ixDPM_TABLE_315", REG_SMC, 0x3f4e8, &ixDPM_TABLE_315[0], sizeof(ixDPM_TABLE_315)/sizeof(ixDPM_TABLE_315[0]), 0, 0 },
+	{ "ixDPM_TABLE_316", REG_SMC, 0x3f4ec, &ixDPM_TABLE_316[0], sizeof(ixDPM_TABLE_316)/sizeof(ixDPM_TABLE_316[0]), 0, 0 },
+	{ "ixDPM_TABLE_317", REG_SMC, 0x3f4f0, &ixDPM_TABLE_317[0], sizeof(ixDPM_TABLE_317)/sizeof(ixDPM_TABLE_317[0]), 0, 0 },
+	{ "ixDPM_TABLE_318", REG_SMC, 0x3f4f4, &ixDPM_TABLE_318[0], sizeof(ixDPM_TABLE_318)/sizeof(ixDPM_TABLE_318[0]), 0, 0 },
+	{ "ixDPM_TABLE_319", REG_SMC, 0x3f4f8, &ixDPM_TABLE_319[0], sizeof(ixDPM_TABLE_319)/sizeof(ixDPM_TABLE_319[0]), 0, 0 },
+	{ "ixDPM_TABLE_320", REG_SMC, 0x3f4fc, &ixDPM_TABLE_320[0], sizeof(ixDPM_TABLE_320)/sizeof(ixDPM_TABLE_320[0]), 0, 0 },
+	{ "ixDPM_TABLE_321", REG_SMC, 0x3f500, &ixDPM_TABLE_321[0], sizeof(ixDPM_TABLE_321)/sizeof(ixDPM_TABLE_321[0]), 0, 0 },
+	{ "ixDPM_TABLE_322", REG_SMC, 0x3f504, &ixDPM_TABLE_322[0], sizeof(ixDPM_TABLE_322)/sizeof(ixDPM_TABLE_322[0]), 0, 0 },
+	{ "ixDPM_TABLE_323", REG_SMC, 0x3f508, &ixDPM_TABLE_323[0], sizeof(ixDPM_TABLE_323)/sizeof(ixDPM_TABLE_323[0]), 0, 0 },
+	{ "ixDPM_TABLE_324", REG_SMC, 0x3f50c, &ixDPM_TABLE_324[0], sizeof(ixDPM_TABLE_324)/sizeof(ixDPM_TABLE_324[0]), 0, 0 },
+	{ "ixDPM_TABLE_325", REG_SMC, 0x3f510, &ixDPM_TABLE_325[0], sizeof(ixDPM_TABLE_325)/sizeof(ixDPM_TABLE_325[0]), 0, 0 },
+	{ "ixDPM_TABLE_326", REG_SMC, 0x3f514, &ixDPM_TABLE_326[0], sizeof(ixDPM_TABLE_326)/sizeof(ixDPM_TABLE_326[0]), 0, 0 },
+	{ "ixDPM_TABLE_327", REG_SMC, 0x3f518, &ixDPM_TABLE_327[0], sizeof(ixDPM_TABLE_327)/sizeof(ixDPM_TABLE_327[0]), 0, 0 },
+	{ "ixDPM_TABLE_328", REG_SMC, 0x3f51c, &ixDPM_TABLE_328[0], sizeof(ixDPM_TABLE_328)/sizeof(ixDPM_TABLE_328[0]), 0, 0 },
+	{ "ixDPM_TABLE_329", REG_SMC, 0x3f520, &ixDPM_TABLE_329[0], sizeof(ixDPM_TABLE_329)/sizeof(ixDPM_TABLE_329[0]), 0, 0 },
+	{ "ixDPM_TABLE_330", REG_SMC, 0x3f524, &ixDPM_TABLE_330[0], sizeof(ixDPM_TABLE_330)/sizeof(ixDPM_TABLE_330[0]), 0, 0 },
+	{ "ixDPM_TABLE_331", REG_SMC, 0x3f528, &ixDPM_TABLE_331[0], sizeof(ixDPM_TABLE_331)/sizeof(ixDPM_TABLE_331[0]), 0, 0 },
+	{ "ixDPM_TABLE_332", REG_SMC, 0x3f52c, &ixDPM_TABLE_332[0], sizeof(ixDPM_TABLE_332)/sizeof(ixDPM_TABLE_332[0]), 0, 0 },
+	{ "ixDPM_TABLE_333", REG_SMC, 0x3f530, &ixDPM_TABLE_333[0], sizeof(ixDPM_TABLE_333)/sizeof(ixDPM_TABLE_333[0]), 0, 0 },
+	{ "ixDPM_TABLE_334", REG_SMC, 0x3f534, &ixDPM_TABLE_334[0], sizeof(ixDPM_TABLE_334)/sizeof(ixDPM_TABLE_334[0]), 0, 0 },
+	{ "ixDPM_TABLE_335", REG_SMC, 0x3f538, &ixDPM_TABLE_335[0], sizeof(ixDPM_TABLE_335)/sizeof(ixDPM_TABLE_335[0]), 0, 0 },
+	{ "ixDPM_TABLE_336", REG_SMC, 0x3f53c, &ixDPM_TABLE_336[0], sizeof(ixDPM_TABLE_336)/sizeof(ixDPM_TABLE_336[0]), 0, 0 },
+	{ "ixDPM_TABLE_337", REG_SMC, 0x3f540, &ixDPM_TABLE_337[0], sizeof(ixDPM_TABLE_337)/sizeof(ixDPM_TABLE_337[0]), 0, 0 },
+	{ "ixDPM_TABLE_338", REG_SMC, 0x3f544, &ixDPM_TABLE_338[0], sizeof(ixDPM_TABLE_338)/sizeof(ixDPM_TABLE_338[0]), 0, 0 },
+	{ "ixDPM_TABLE_339", REG_SMC, 0x3f548, &ixDPM_TABLE_339[0], sizeof(ixDPM_TABLE_339)/sizeof(ixDPM_TABLE_339[0]), 0, 0 },
+	{ "ixDPM_TABLE_340", REG_SMC, 0x3f54c, &ixDPM_TABLE_340[0], sizeof(ixDPM_TABLE_340)/sizeof(ixDPM_TABLE_340[0]), 0, 0 },
+	{ "ixDPM_TABLE_341", REG_SMC, 0x3f550, &ixDPM_TABLE_341[0], sizeof(ixDPM_TABLE_341)/sizeof(ixDPM_TABLE_341[0]), 0, 0 },
+	{ "ixDPM_TABLE_342", REG_SMC, 0x3f554, &ixDPM_TABLE_342[0], sizeof(ixDPM_TABLE_342)/sizeof(ixDPM_TABLE_342[0]), 0, 0 },
+	{ "ixDPM_TABLE_343", REG_SMC, 0x3f558, &ixDPM_TABLE_343[0], sizeof(ixDPM_TABLE_343)/sizeof(ixDPM_TABLE_343[0]), 0, 0 },
+	{ "ixDPM_TABLE_344", REG_SMC, 0x3f55c, &ixDPM_TABLE_344[0], sizeof(ixDPM_TABLE_344)/sizeof(ixDPM_TABLE_344[0]), 0, 0 },
+	{ "ixDPM_TABLE_345", REG_SMC, 0x3f560, &ixDPM_TABLE_345[0], sizeof(ixDPM_TABLE_345)/sizeof(ixDPM_TABLE_345[0]), 0, 0 },
+	{ "ixDPM_TABLE_346", REG_SMC, 0x3f564, &ixDPM_TABLE_346[0], sizeof(ixDPM_TABLE_346)/sizeof(ixDPM_TABLE_346[0]), 0, 0 },
+	{ "ixDPM_TABLE_347", REG_SMC, 0x3f568, &ixDPM_TABLE_347[0], sizeof(ixDPM_TABLE_347)/sizeof(ixDPM_TABLE_347[0]), 0, 0 },
+	{ "ixDPM_TABLE_348", REG_SMC, 0x3f56c, &ixDPM_TABLE_348[0], sizeof(ixDPM_TABLE_348)/sizeof(ixDPM_TABLE_348[0]), 0, 0 },
+	{ "ixDPM_TABLE_349", REG_SMC, 0x3f570, &ixDPM_TABLE_349[0], sizeof(ixDPM_TABLE_349)/sizeof(ixDPM_TABLE_349[0]), 0, 0 },
+	{ "ixDPM_TABLE_350", REG_SMC, 0x3f574, &ixDPM_TABLE_350[0], sizeof(ixDPM_TABLE_350)/sizeof(ixDPM_TABLE_350[0]), 0, 0 },
+	{ "ixDPM_TABLE_351", REG_SMC, 0x3f578, &ixDPM_TABLE_351[0], sizeof(ixDPM_TABLE_351)/sizeof(ixDPM_TABLE_351[0]), 0, 0 },
+	{ "ixDPM_TABLE_352", REG_SMC, 0x3f57c, &ixDPM_TABLE_352[0], sizeof(ixDPM_TABLE_352)/sizeof(ixDPM_TABLE_352[0]), 0, 0 },
+	{ "ixDPM_TABLE_353", REG_SMC, 0x3f580, &ixDPM_TABLE_353[0], sizeof(ixDPM_TABLE_353)/sizeof(ixDPM_TABLE_353[0]), 0, 0 },
+	{ "ixDPM_TABLE_354", REG_SMC, 0x3f584, &ixDPM_TABLE_354[0], sizeof(ixDPM_TABLE_354)/sizeof(ixDPM_TABLE_354[0]), 0, 0 },
+	{ "ixDPM_TABLE_355", REG_SMC, 0x3f588, &ixDPM_TABLE_355[0], sizeof(ixDPM_TABLE_355)/sizeof(ixDPM_TABLE_355[0]), 0, 0 },
+	{ "ixDPM_TABLE_356", REG_SMC, 0x3f58c, &ixDPM_TABLE_356[0], sizeof(ixDPM_TABLE_356)/sizeof(ixDPM_TABLE_356[0]), 0, 0 },
+	{ "ixDPM_TABLE_357", REG_SMC, 0x3f590, &ixDPM_TABLE_357[0], sizeof(ixDPM_TABLE_357)/sizeof(ixDPM_TABLE_357[0]), 0, 0 },
+	{ "ixDPM_TABLE_358", REG_SMC, 0x3f594, &ixDPM_TABLE_358[0], sizeof(ixDPM_TABLE_358)/sizeof(ixDPM_TABLE_358[0]), 0, 0 },
+	{ "ixDPM_TABLE_359", REG_SMC, 0x3f598, &ixDPM_TABLE_359[0], sizeof(ixDPM_TABLE_359)/sizeof(ixDPM_TABLE_359[0]), 0, 0 },
+	{ "ixDPM_TABLE_360", REG_SMC, 0x3f59c, &ixDPM_TABLE_360[0], sizeof(ixDPM_TABLE_360)/sizeof(ixDPM_TABLE_360[0]), 0, 0 },
+	{ "ixDPM_TABLE_361", REG_SMC, 0x3f5a0, &ixDPM_TABLE_361[0], sizeof(ixDPM_TABLE_361)/sizeof(ixDPM_TABLE_361[0]), 0, 0 },
+	{ "ixDPM_TABLE_362", REG_SMC, 0x3f5a4, &ixDPM_TABLE_362[0], sizeof(ixDPM_TABLE_362)/sizeof(ixDPM_TABLE_362[0]), 0, 0 },
+	{ "ixDPM_TABLE_363", REG_SMC, 0x3f5a8, &ixDPM_TABLE_363[0], sizeof(ixDPM_TABLE_363)/sizeof(ixDPM_TABLE_363[0]), 0, 0 },
+	{ "ixDPM_TABLE_364", REG_SMC, 0x3f5ac, &ixDPM_TABLE_364[0], sizeof(ixDPM_TABLE_364)/sizeof(ixDPM_TABLE_364[0]), 0, 0 },
+	{ "ixDPM_TABLE_365", REG_SMC, 0x3f5b0, &ixDPM_TABLE_365[0], sizeof(ixDPM_TABLE_365)/sizeof(ixDPM_TABLE_365[0]), 0, 0 },
+	{ "ixDPM_TABLE_366", REG_SMC, 0x3f5b4, &ixDPM_TABLE_366[0], sizeof(ixDPM_TABLE_366)/sizeof(ixDPM_TABLE_366[0]), 0, 0 },
+	{ "ixDPM_TABLE_367", REG_SMC, 0x3f5b8, &ixDPM_TABLE_367[0], sizeof(ixDPM_TABLE_367)/sizeof(ixDPM_TABLE_367[0]), 0, 0 },
+	{ "ixDPM_TABLE_368", REG_SMC, 0x3f5bc, &ixDPM_TABLE_368[0], sizeof(ixDPM_TABLE_368)/sizeof(ixDPM_TABLE_368[0]), 0, 0 },
+	{ "ixDPM_TABLE_369", REG_SMC, 0x3f5c0, &ixDPM_TABLE_369[0], sizeof(ixDPM_TABLE_369)/sizeof(ixDPM_TABLE_369[0]), 0, 0 },
+	{ "ixDPM_TABLE_370", REG_SMC, 0x3f5c4, &ixDPM_TABLE_370[0], sizeof(ixDPM_TABLE_370)/sizeof(ixDPM_TABLE_370[0]), 0, 0 },
+	{ "ixDPM_TABLE_371", REG_SMC, 0x3f5c8, &ixDPM_TABLE_371[0], sizeof(ixDPM_TABLE_371)/sizeof(ixDPM_TABLE_371[0]), 0, 0 },
+	{ "ixDPM_TABLE_372", REG_SMC, 0x3f5cc, &ixDPM_TABLE_372[0], sizeof(ixDPM_TABLE_372)/sizeof(ixDPM_TABLE_372[0]), 0, 0 },
+	{ "ixDPM_TABLE_373", REG_SMC, 0x3f5d0, &ixDPM_TABLE_373[0], sizeof(ixDPM_TABLE_373)/sizeof(ixDPM_TABLE_373[0]), 0, 0 },
+	{ "ixDPM_TABLE_374", REG_SMC, 0x3f5d4, &ixDPM_TABLE_374[0], sizeof(ixDPM_TABLE_374)/sizeof(ixDPM_TABLE_374[0]), 0, 0 },
+	{ "ixDPM_TABLE_375", REG_SMC, 0x3f5d8, &ixDPM_TABLE_375[0], sizeof(ixDPM_TABLE_375)/sizeof(ixDPM_TABLE_375[0]), 0, 0 },
+	{ "ixDPM_TABLE_376", REG_SMC, 0x3f5dc, &ixDPM_TABLE_376[0], sizeof(ixDPM_TABLE_376)/sizeof(ixDPM_TABLE_376[0]), 0, 0 },
+	{ "ixDPM_TABLE_377", REG_SMC, 0x3f5e0, &ixDPM_TABLE_377[0], sizeof(ixDPM_TABLE_377)/sizeof(ixDPM_TABLE_377[0]), 0, 0 },
+	{ "ixDPM_TABLE_378", REG_SMC, 0x3f5e4, &ixDPM_TABLE_378[0], sizeof(ixDPM_TABLE_378)/sizeof(ixDPM_TABLE_378[0]), 0, 0 },
+	{ "ixDPM_TABLE_379", REG_SMC, 0x3f5e8, &ixDPM_TABLE_379[0], sizeof(ixDPM_TABLE_379)/sizeof(ixDPM_TABLE_379[0]), 0, 0 },
+	{ "ixDPM_TABLE_380", REG_SMC, 0x3f5ec, &ixDPM_TABLE_380[0], sizeof(ixDPM_TABLE_380)/sizeof(ixDPM_TABLE_380[0]), 0, 0 },
+	{ "ixDPM_TABLE_381", REG_SMC, 0x3f5f0, &ixDPM_TABLE_381[0], sizeof(ixDPM_TABLE_381)/sizeof(ixDPM_TABLE_381[0]), 0, 0 },
+	{ "ixDPM_TABLE_382", REG_SMC, 0x3f5f4, &ixDPM_TABLE_382[0], sizeof(ixDPM_TABLE_382)/sizeof(ixDPM_TABLE_382[0]), 0, 0 },
+	{ "ixDPM_TABLE_383", REG_SMC, 0x3f5f8, &ixDPM_TABLE_383[0], sizeof(ixDPM_TABLE_383)/sizeof(ixDPM_TABLE_383[0]), 0, 0 },
+	{ "ixDPM_TABLE_384", REG_SMC, 0x3f5fc, &ixDPM_TABLE_384[0], sizeof(ixDPM_TABLE_384)/sizeof(ixDPM_TABLE_384[0]), 0, 0 },
+	{ "ixDPM_TABLE_385", REG_SMC, 0x3f600, &ixDPM_TABLE_385[0], sizeof(ixDPM_TABLE_385)/sizeof(ixDPM_TABLE_385[0]), 0, 0 },
+	{ "ixDPM_TABLE_386", REG_SMC, 0x3f604, &ixDPM_TABLE_386[0], sizeof(ixDPM_TABLE_386)/sizeof(ixDPM_TABLE_386[0]), 0, 0 },
+	{ "ixDPM_TABLE_387", REG_SMC, 0x3f608, &ixDPM_TABLE_387[0], sizeof(ixDPM_TABLE_387)/sizeof(ixDPM_TABLE_387[0]), 0, 0 },
+	{ "ixDPM_TABLE_388", REG_SMC, 0x3f60c, &ixDPM_TABLE_388[0], sizeof(ixDPM_TABLE_388)/sizeof(ixDPM_TABLE_388[0]), 0, 0 },
+	{ "ixDPM_TABLE_389", REG_SMC, 0x3f610, &ixDPM_TABLE_389[0], sizeof(ixDPM_TABLE_389)/sizeof(ixDPM_TABLE_389[0]), 0, 0 },
+	{ "ixDPM_TABLE_390", REG_SMC, 0x3f614, &ixDPM_TABLE_390[0], sizeof(ixDPM_TABLE_390)/sizeof(ixDPM_TABLE_390[0]), 0, 0 },
+	{ "ixDPM_TABLE_391", REG_SMC, 0x3f618, &ixDPM_TABLE_391[0], sizeof(ixDPM_TABLE_391)/sizeof(ixDPM_TABLE_391[0]), 0, 0 },
+	{ "ixDPM_TABLE_392", REG_SMC, 0x3f61c, &ixDPM_TABLE_392[0], sizeof(ixDPM_TABLE_392)/sizeof(ixDPM_TABLE_392[0]), 0, 0 },
+	{ "ixDPM_TABLE_393", REG_SMC, 0x3f620, &ixDPM_TABLE_393[0], sizeof(ixDPM_TABLE_393)/sizeof(ixDPM_TABLE_393[0]), 0, 0 },
+	{ "ixDPM_TABLE_394", REG_SMC, 0x3f624, &ixDPM_TABLE_394[0], sizeof(ixDPM_TABLE_394)/sizeof(ixDPM_TABLE_394[0]), 0, 0 },
+	{ "ixDPM_TABLE_395", REG_SMC, 0x3f628, &ixDPM_TABLE_395[0], sizeof(ixDPM_TABLE_395)/sizeof(ixDPM_TABLE_395[0]), 0, 0 },
+	{ "ixDPM_TABLE_396", REG_SMC, 0x3f62c, &ixDPM_TABLE_396[0], sizeof(ixDPM_TABLE_396)/sizeof(ixDPM_TABLE_396[0]), 0, 0 },
+	{ "ixDPM_TABLE_397", REG_SMC, 0x3f630, &ixDPM_TABLE_397[0], sizeof(ixDPM_TABLE_397)/sizeof(ixDPM_TABLE_397[0]), 0, 0 },
+	{ "ixDPM_TABLE_398", REG_SMC, 0x3f634, &ixDPM_TABLE_398[0], sizeof(ixDPM_TABLE_398)/sizeof(ixDPM_TABLE_398[0]), 0, 0 },
+	{ "ixDPM_TABLE_399", REG_SMC, 0x3f638, &ixDPM_TABLE_399[0], sizeof(ixDPM_TABLE_399)/sizeof(ixDPM_TABLE_399[0]), 0, 0 },
+	{ "ixDPM_TABLE_400", REG_SMC, 0x3f63c, &ixDPM_TABLE_400[0], sizeof(ixDPM_TABLE_400)/sizeof(ixDPM_TABLE_400[0]), 0, 0 },
+	{ "ixDPM_TABLE_401", REG_SMC, 0x3f640, &ixDPM_TABLE_401[0], sizeof(ixDPM_TABLE_401)/sizeof(ixDPM_TABLE_401[0]), 0, 0 },
+	{ "ixDPM_TABLE_402", REG_SMC, 0x3f644, &ixDPM_TABLE_402[0], sizeof(ixDPM_TABLE_402)/sizeof(ixDPM_TABLE_402[0]), 0, 0 },
+	{ "ixDPM_TABLE_403", REG_SMC, 0x3f648, &ixDPM_TABLE_403[0], sizeof(ixDPM_TABLE_403)/sizeof(ixDPM_TABLE_403[0]), 0, 0 },
+	{ "ixDPM_TABLE_404", REG_SMC, 0x3f64c, &ixDPM_TABLE_404[0], sizeof(ixDPM_TABLE_404)/sizeof(ixDPM_TABLE_404[0]), 0, 0 },
+	{ "ixDPM_TABLE_405", REG_SMC, 0x3f650, &ixDPM_TABLE_405[0], sizeof(ixDPM_TABLE_405)/sizeof(ixDPM_TABLE_405[0]), 0, 0 },
+	{ "ixDPM_TABLE_406", REG_SMC, 0x3f654, &ixDPM_TABLE_406[0], sizeof(ixDPM_TABLE_406)/sizeof(ixDPM_TABLE_406[0]), 0, 0 },
+	{ "ixDPM_TABLE_407", REG_SMC, 0x3f658, &ixDPM_TABLE_407[0], sizeof(ixDPM_TABLE_407)/sizeof(ixDPM_TABLE_407[0]), 0, 0 },
+	{ "ixDPM_TABLE_408", REG_SMC, 0x3f65c, &ixDPM_TABLE_408[0], sizeof(ixDPM_TABLE_408)/sizeof(ixDPM_TABLE_408[0]), 0, 0 },
+	{ "ixDPM_TABLE_409", REG_SMC, 0x3f660, &ixDPM_TABLE_409[0], sizeof(ixDPM_TABLE_409)/sizeof(ixDPM_TABLE_409[0]), 0, 0 },
+	{ "ixDPM_TABLE_410", REG_SMC, 0x3f664, &ixDPM_TABLE_410[0], sizeof(ixDPM_TABLE_410)/sizeof(ixDPM_TABLE_410[0]), 0, 0 },
+	{ "ixDPM_TABLE_411", REG_SMC, 0x3f668, &ixDPM_TABLE_411[0], sizeof(ixDPM_TABLE_411)/sizeof(ixDPM_TABLE_411[0]), 0, 0 },
+	{ "ixDPM_TABLE_412", REG_SMC, 0x3f66c, &ixDPM_TABLE_412[0], sizeof(ixDPM_TABLE_412)/sizeof(ixDPM_TABLE_412[0]), 0, 0 },
+	{ "ixDPM_TABLE_413", REG_SMC, 0x3f670, &ixDPM_TABLE_413[0], sizeof(ixDPM_TABLE_413)/sizeof(ixDPM_TABLE_413[0]), 0, 0 },
+	{ "ixDPM_TABLE_414", REG_SMC, 0x3f674, &ixDPM_TABLE_414[0], sizeof(ixDPM_TABLE_414)/sizeof(ixDPM_TABLE_414[0]), 0, 0 },
+	{ "ixDPM_TABLE_415", REG_SMC, 0x3f678, &ixDPM_TABLE_415[0], sizeof(ixDPM_TABLE_415)/sizeof(ixDPM_TABLE_415[0]), 0, 0 },
+	{ "ixDPM_TABLE_416", REG_SMC, 0x3f67c, &ixDPM_TABLE_416[0], sizeof(ixDPM_TABLE_416)/sizeof(ixDPM_TABLE_416[0]), 0, 0 },
+	{ "ixDPM_TABLE_417", REG_SMC, 0x3f680, &ixDPM_TABLE_417[0], sizeof(ixDPM_TABLE_417)/sizeof(ixDPM_TABLE_417[0]), 0, 0 },
+	{ "ixDPM_TABLE_418", REG_SMC, 0x3f684, &ixDPM_TABLE_418[0], sizeof(ixDPM_TABLE_418)/sizeof(ixDPM_TABLE_418[0]), 0, 0 },
+	{ "ixDPM_TABLE_419", REG_SMC, 0x3f688, &ixDPM_TABLE_419[0], sizeof(ixDPM_TABLE_419)/sizeof(ixDPM_TABLE_419[0]), 0, 0 },
+	{ "ixDPM_TABLE_420", REG_SMC, 0x3f68c, &ixDPM_TABLE_420[0], sizeof(ixDPM_TABLE_420)/sizeof(ixDPM_TABLE_420[0]), 0, 0 },
+	{ "ixDPM_TABLE_421", REG_SMC, 0x3f690, &ixDPM_TABLE_421[0], sizeof(ixDPM_TABLE_421)/sizeof(ixDPM_TABLE_421[0]), 0, 0 },
+	{ "ixDPM_TABLE_422", REG_SMC, 0x3f694, &ixDPM_TABLE_422[0], sizeof(ixDPM_TABLE_422)/sizeof(ixDPM_TABLE_422[0]), 0, 0 },
+	{ "ixDPM_TABLE_423", REG_SMC, 0x3f698, &ixDPM_TABLE_423[0], sizeof(ixDPM_TABLE_423)/sizeof(ixDPM_TABLE_423[0]), 0, 0 },
+	{ "ixDPM_TABLE_424", REG_SMC, 0x3f69c, &ixDPM_TABLE_424[0], sizeof(ixDPM_TABLE_424)/sizeof(ixDPM_TABLE_424[0]), 0, 0 },
+	{ "ixDPM_TABLE_425", REG_SMC, 0x3f6a0, &ixDPM_TABLE_425[0], sizeof(ixDPM_TABLE_425)/sizeof(ixDPM_TABLE_425[0]), 0, 0 },
+	{ "ixDPM_TABLE_426", REG_SMC, 0x3f6a4, &ixDPM_TABLE_426[0], sizeof(ixDPM_TABLE_426)/sizeof(ixDPM_TABLE_426[0]), 0, 0 },
+	{ "ixDPM_TABLE_427", REG_SMC, 0x3f6a8, &ixDPM_TABLE_427[0], sizeof(ixDPM_TABLE_427)/sizeof(ixDPM_TABLE_427[0]), 0, 0 },
+	{ "ixDPM_TABLE_428", REG_SMC, 0x3f6ac, &ixDPM_TABLE_428[0], sizeof(ixDPM_TABLE_428)/sizeof(ixDPM_TABLE_428[0]), 0, 0 },
+	{ "ixDPM_TABLE_429", REG_SMC, 0x3f6b0, &ixDPM_TABLE_429[0], sizeof(ixDPM_TABLE_429)/sizeof(ixDPM_TABLE_429[0]), 0, 0 },
+	{ "ixDPM_TABLE_430", REG_SMC, 0x3f6b4, &ixDPM_TABLE_430[0], sizeof(ixDPM_TABLE_430)/sizeof(ixDPM_TABLE_430[0]), 0, 0 },
+	{ "ixDPM_TABLE_431", REG_SMC, 0x3f6b8, &ixDPM_TABLE_431[0], sizeof(ixDPM_TABLE_431)/sizeof(ixDPM_TABLE_431[0]), 0, 0 },
+	{ "ixDPM_TABLE_432", REG_SMC, 0x3f6bc, &ixDPM_TABLE_432[0], sizeof(ixDPM_TABLE_432)/sizeof(ixDPM_TABLE_432[0]), 0, 0 },
+	{ "ixDPM_TABLE_433", REG_SMC, 0x3f6c0, &ixDPM_TABLE_433[0], sizeof(ixDPM_TABLE_433)/sizeof(ixDPM_TABLE_433[0]), 0, 0 },
+	{ "ixDPM_TABLE_434", REG_SMC, 0x3f6c4, &ixDPM_TABLE_434[0], sizeof(ixDPM_TABLE_434)/sizeof(ixDPM_TABLE_434[0]), 0, 0 },
+	{ "ixDPM_TABLE_435", REG_SMC, 0x3f6c8, &ixDPM_TABLE_435[0], sizeof(ixDPM_TABLE_435)/sizeof(ixDPM_TABLE_435[0]), 0, 0 },
+	{ "ixDPM_TABLE_436", REG_SMC, 0x3f6cc, &ixDPM_TABLE_436[0], sizeof(ixDPM_TABLE_436)/sizeof(ixDPM_TABLE_436[0]), 0, 0 },
+	{ "ixDPM_TABLE_437", REG_SMC, 0x3f6d0, &ixDPM_TABLE_437[0], sizeof(ixDPM_TABLE_437)/sizeof(ixDPM_TABLE_437[0]), 0, 0 },
+	{ "ixDPM_TABLE_438", REG_SMC, 0x3f6d4, &ixDPM_TABLE_438[0], sizeof(ixDPM_TABLE_438)/sizeof(ixDPM_TABLE_438[0]), 0, 0 },
+	{ "ixDPM_TABLE_439", REG_SMC, 0x3f6d8, &ixDPM_TABLE_439[0], sizeof(ixDPM_TABLE_439)/sizeof(ixDPM_TABLE_439[0]), 0, 0 },
+	{ "ixDPM_TABLE_440", REG_SMC, 0x3f6dc, &ixDPM_TABLE_440[0], sizeof(ixDPM_TABLE_440)/sizeof(ixDPM_TABLE_440[0]), 0, 0 },
+	{ "ixDPM_TABLE_441", REG_SMC, 0x3f6e0, &ixDPM_TABLE_441[0], sizeof(ixDPM_TABLE_441)/sizeof(ixDPM_TABLE_441[0]), 0, 0 },
+	{ "ixDPM_TABLE_442", REG_SMC, 0x3f6e4, &ixDPM_TABLE_442[0], sizeof(ixDPM_TABLE_442)/sizeof(ixDPM_TABLE_442[0]), 0, 0 },
+	{ "ixDPM_TABLE_443", REG_SMC, 0x3f6e8, &ixDPM_TABLE_443[0], sizeof(ixDPM_TABLE_443)/sizeof(ixDPM_TABLE_443[0]), 0, 0 },
+	{ "ixDPM_TABLE_444", REG_SMC, 0x3f6ec, &ixDPM_TABLE_444[0], sizeof(ixDPM_TABLE_444)/sizeof(ixDPM_TABLE_444[0]), 0, 0 },
+	{ "ixDPM_TABLE_445", REG_SMC, 0x3f6f0, &ixDPM_TABLE_445[0], sizeof(ixDPM_TABLE_445)/sizeof(ixDPM_TABLE_445[0]), 0, 0 },
+	{ "ixDPM_TABLE_446", REG_SMC, 0x3f6f4, &ixDPM_TABLE_446[0], sizeof(ixDPM_TABLE_446)/sizeof(ixDPM_TABLE_446[0]), 0, 0 },
+	{ "ixDPM_TABLE_447", REG_SMC, 0x3f6f8, &ixDPM_TABLE_447[0], sizeof(ixDPM_TABLE_447)/sizeof(ixDPM_TABLE_447[0]), 0, 0 },
+	{ "ixDPM_TABLE_448", REG_SMC, 0x3f6fc, &ixDPM_TABLE_448[0], sizeof(ixDPM_TABLE_448)/sizeof(ixDPM_TABLE_448[0]), 0, 0 },
+	{ "ixDPM_TABLE_449", REG_SMC, 0x3f700, &ixDPM_TABLE_449[0], sizeof(ixDPM_TABLE_449)/sizeof(ixDPM_TABLE_449[0]), 0, 0 },
+	{ "ixDPM_TABLE_450", REG_SMC, 0x3f704, &ixDPM_TABLE_450[0], sizeof(ixDPM_TABLE_450)/sizeof(ixDPM_TABLE_450[0]), 0, 0 },
+	{ "ixDPM_TABLE_451", REG_SMC, 0x3f708, &ixDPM_TABLE_451[0], sizeof(ixDPM_TABLE_451)/sizeof(ixDPM_TABLE_451[0]), 0, 0 },
+	{ "ixDPM_TABLE_452", REG_SMC, 0x3f70c, &ixDPM_TABLE_452[0], sizeof(ixDPM_TABLE_452)/sizeof(ixDPM_TABLE_452[0]), 0, 0 },
+	{ "ixDPM_TABLE_453", REG_SMC, 0x3f710, &ixDPM_TABLE_453[0], sizeof(ixDPM_TABLE_453)/sizeof(ixDPM_TABLE_453[0]), 0, 0 },
+	{ "ixDPM_TABLE_454", REG_SMC, 0x3f714, &ixDPM_TABLE_454[0], sizeof(ixDPM_TABLE_454)/sizeof(ixDPM_TABLE_454[0]), 0, 0 },
+	{ "ixDPM_TABLE_455", REG_SMC, 0x3f718, &ixDPM_TABLE_455[0], sizeof(ixDPM_TABLE_455)/sizeof(ixDPM_TABLE_455[0]), 0, 0 },
+	{ "ixDPM_TABLE_456", REG_SMC, 0x3f71c, &ixDPM_TABLE_456[0], sizeof(ixDPM_TABLE_456)/sizeof(ixDPM_TABLE_456[0]), 0, 0 },
+	{ "ixDPM_TABLE_457", REG_SMC, 0x3f720, &ixDPM_TABLE_457[0], sizeof(ixDPM_TABLE_457)/sizeof(ixDPM_TABLE_457[0]), 0, 0 },
+	{ "ixDPM_TABLE_458", REG_SMC, 0x3f724, &ixDPM_TABLE_458[0], sizeof(ixDPM_TABLE_458)/sizeof(ixDPM_TABLE_458[0]), 0, 0 },
+	{ "ixDPM_TABLE_459", REG_SMC, 0x3f728, &ixDPM_TABLE_459[0], sizeof(ixDPM_TABLE_459)/sizeof(ixDPM_TABLE_459[0]), 0, 0 },
+	{ "ixDPM_TABLE_460", REG_SMC, 0x3f72c, &ixDPM_TABLE_460[0], sizeof(ixDPM_TABLE_460)/sizeof(ixDPM_TABLE_460[0]), 0, 0 },
+	{ "ixDPM_TABLE_461", REG_SMC, 0x3f730, &ixDPM_TABLE_461[0], sizeof(ixDPM_TABLE_461)/sizeof(ixDPM_TABLE_461[0]), 0, 0 },
+	{ "ixDPM_TABLE_462", REG_SMC, 0x3f734, &ixDPM_TABLE_462[0], sizeof(ixDPM_TABLE_462)/sizeof(ixDPM_TABLE_462[0]), 0, 0 },
+	{ "ixDPM_TABLE_463", REG_SMC, 0x3f738, &ixDPM_TABLE_463[0], sizeof(ixDPM_TABLE_463)/sizeof(ixDPM_TABLE_463[0]), 0, 0 },
+	{ "ixDPM_TABLE_464", REG_SMC, 0x3f73c, &ixDPM_TABLE_464[0], sizeof(ixDPM_TABLE_464)/sizeof(ixDPM_TABLE_464[0]), 0, 0 },
+	{ "ixDPM_TABLE_465", REG_SMC, 0x3f740, &ixDPM_TABLE_465[0], sizeof(ixDPM_TABLE_465)/sizeof(ixDPM_TABLE_465[0]), 0, 0 },
+	{ "ixDPM_TABLE_466", REG_SMC, 0x3f744, &ixDPM_TABLE_466[0], sizeof(ixDPM_TABLE_466)/sizeof(ixDPM_TABLE_466[0]), 0, 0 },
+	{ "ixDPM_TABLE_467", REG_SMC, 0x3f748, &ixDPM_TABLE_467[0], sizeof(ixDPM_TABLE_467)/sizeof(ixDPM_TABLE_467[0]), 0, 0 },
+	{ "ixDPM_TABLE_468", REG_SMC, 0x3f74c, &ixDPM_TABLE_468[0], sizeof(ixDPM_TABLE_468)/sizeof(ixDPM_TABLE_468[0]), 0, 0 },
+	{ "ixDPM_TABLE_469", REG_SMC, 0x3f750, &ixDPM_TABLE_469[0], sizeof(ixDPM_TABLE_469)/sizeof(ixDPM_TABLE_469[0]), 0, 0 },
+	{ "ixDPM_TABLE_470", REG_SMC, 0x3f754, &ixDPM_TABLE_470[0], sizeof(ixDPM_TABLE_470)/sizeof(ixDPM_TABLE_470[0]), 0, 0 },
+	{ "ixDPM_TABLE_471", REG_SMC, 0x3f758, &ixDPM_TABLE_471[0], sizeof(ixDPM_TABLE_471)/sizeof(ixDPM_TABLE_471[0]), 0, 0 },
+	{ "ixDPM_TABLE_472", REG_SMC, 0x3f75c, &ixDPM_TABLE_472[0], sizeof(ixDPM_TABLE_472)/sizeof(ixDPM_TABLE_472[0]), 0, 0 },
+	{ "ixDPM_TABLE_473", REG_SMC, 0x3f760, &ixDPM_TABLE_473[0], sizeof(ixDPM_TABLE_473)/sizeof(ixDPM_TABLE_473[0]), 0, 0 },
+	{ "ixDPM_TABLE_474", REG_SMC, 0x3f764, &ixDPM_TABLE_474[0], sizeof(ixDPM_TABLE_474)/sizeof(ixDPM_TABLE_474[0]), 0, 0 },
+	{ "ixDPM_TABLE_475", REG_SMC, 0x3f768, &ixDPM_TABLE_475[0], sizeof(ixDPM_TABLE_475)/sizeof(ixDPM_TABLE_475[0]), 0, 0 },
+	{ "ixDPM_TABLE_476", REG_SMC, 0x3f76c, &ixDPM_TABLE_476[0], sizeof(ixDPM_TABLE_476)/sizeof(ixDPM_TABLE_476[0]), 0, 0 },
+	{ "ixDPM_TABLE_477", REG_SMC, 0x3f770, &ixDPM_TABLE_477[0], sizeof(ixDPM_TABLE_477)/sizeof(ixDPM_TABLE_477[0]), 0, 0 },
+	{ "ixDPM_TABLE_478", REG_SMC, 0x3f774, &ixDPM_TABLE_478[0], sizeof(ixDPM_TABLE_478)/sizeof(ixDPM_TABLE_478[0]), 0, 0 },
+	{ "ixDPM_TABLE_479", REG_SMC, 0x3f778, &ixDPM_TABLE_479[0], sizeof(ixDPM_TABLE_479)/sizeof(ixDPM_TABLE_479[0]), 0, 0 },
+	{ "ixDPM_TABLE_480", REG_SMC, 0x3f77c, &ixDPM_TABLE_480[0], sizeof(ixDPM_TABLE_480)/sizeof(ixDPM_TABLE_480[0]), 0, 0 },
+	{ "ixDPM_TABLE_481", REG_SMC, 0x3f780, &ixDPM_TABLE_481[0], sizeof(ixDPM_TABLE_481)/sizeof(ixDPM_TABLE_481[0]), 0, 0 },
+	{ "ixDPM_TABLE_482", REG_SMC, 0x3f784, &ixDPM_TABLE_482[0], sizeof(ixDPM_TABLE_482)/sizeof(ixDPM_TABLE_482[0]), 0, 0 },
+	{ "ixDPM_TABLE_483", REG_SMC, 0x3f788, &ixDPM_TABLE_483[0], sizeof(ixDPM_TABLE_483)/sizeof(ixDPM_TABLE_483[0]), 0, 0 },
+	{ "ixDPM_TABLE_484", REG_SMC, 0x3f78c, &ixDPM_TABLE_484[0], sizeof(ixDPM_TABLE_484)/sizeof(ixDPM_TABLE_484[0]), 0, 0 },
+	{ "ixDPM_TABLE_485", REG_SMC, 0x3f790, &ixDPM_TABLE_485[0], sizeof(ixDPM_TABLE_485)/sizeof(ixDPM_TABLE_485[0]), 0, 0 },
+	{ "ixDPM_TABLE_486", REG_SMC, 0x3f794, &ixDPM_TABLE_486[0], sizeof(ixDPM_TABLE_486)/sizeof(ixDPM_TABLE_486[0]), 0, 0 },
+	{ "ixDPM_TABLE_487", REG_SMC, 0x3f798, &ixDPM_TABLE_487[0], sizeof(ixDPM_TABLE_487)/sizeof(ixDPM_TABLE_487[0]), 0, 0 },
+	{ "ixDPM_TABLE_488", REG_SMC, 0x3f79c, &ixDPM_TABLE_488[0], sizeof(ixDPM_TABLE_488)/sizeof(ixDPM_TABLE_488[0]), 0, 0 },
+	{ "ixDPM_TABLE_489", REG_SMC, 0x3f7a0, &ixDPM_TABLE_489[0], sizeof(ixDPM_TABLE_489)/sizeof(ixDPM_TABLE_489[0]), 0, 0 },
+	{ "ixDPM_TABLE_490", REG_SMC, 0x3f7a4, &ixDPM_TABLE_490[0], sizeof(ixDPM_TABLE_490)/sizeof(ixDPM_TABLE_490[0]), 0, 0 },
+	{ "ixFIRMWARE_FLAGS", REG_SMC, 0x3f800, &ixFIRMWARE_FLAGS[0], sizeof(ixFIRMWARE_FLAGS)/sizeof(ixFIRMWARE_FLAGS[0]), 0, 0 },
+	{ "ixTDC_STATUS", REG_SMC, 0x3f804, &ixTDC_STATUS[0], sizeof(ixTDC_STATUS)/sizeof(ixTDC_STATUS[0]), 0, 0 },
+	{ "ixTDC_MV_AVERAGE", REG_SMC, 0x3f808, &ixTDC_MV_AVERAGE[0], sizeof(ixTDC_MV_AVERAGE)/sizeof(ixTDC_MV_AVERAGE[0]), 0, 0 },
+	{ "ixTDC_VRM_LIMIT", REG_SMC, 0x3f80c, &ixTDC_VRM_LIMIT[0], sizeof(ixTDC_VRM_LIMIT)/sizeof(ixTDC_VRM_LIMIT[0]), 0, 0 },
+	{ "ixFEATURE_STATUS", REG_SMC, 0x3f810, &ixFEATURE_STATUS[0], sizeof(ixFEATURE_STATUS)/sizeof(ixFEATURE_STATUS[0]), 0, 0 },
+	{ "ixENTITY_TEMPERATURES_1", REG_SMC, 0x3f814, &ixENTITY_TEMPERATURES_1[0], sizeof(ixENTITY_TEMPERATURES_1)/sizeof(ixENTITY_TEMPERATURES_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_1", REG_SMC, 0x3f900, &ixMCARB_DRAM_TIMING_TABLE_1[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_1)/sizeof(ixMCARB_DRAM_TIMING_TABLE_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_2", REG_SMC, 0x3f904, &ixMCARB_DRAM_TIMING_TABLE_2[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_2)/sizeof(ixMCARB_DRAM_TIMING_TABLE_2[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_3", REG_SMC, 0x3f908, &ixMCARB_DRAM_TIMING_TABLE_3[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_3)/sizeof(ixMCARB_DRAM_TIMING_TABLE_3[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_4", REG_SMC, 0x3f90c, &ixMCARB_DRAM_TIMING_TABLE_4[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_4)/sizeof(ixMCARB_DRAM_TIMING_TABLE_4[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_5", REG_SMC, 0x3f910, &ixMCARB_DRAM_TIMING_TABLE_5[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_5)/sizeof(ixMCARB_DRAM_TIMING_TABLE_5[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_6", REG_SMC, 0x3f914, &ixMCARB_DRAM_TIMING_TABLE_6[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_6)/sizeof(ixMCARB_DRAM_TIMING_TABLE_6[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_7", REG_SMC, 0x3f918, &ixMCARB_DRAM_TIMING_TABLE_7[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_7)/sizeof(ixMCARB_DRAM_TIMING_TABLE_7[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_8", REG_SMC, 0x3f91c, &ixMCARB_DRAM_TIMING_TABLE_8[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_8)/sizeof(ixMCARB_DRAM_TIMING_TABLE_8[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_9", REG_SMC, 0x3f920, &ixMCARB_DRAM_TIMING_TABLE_9[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_9)/sizeof(ixMCARB_DRAM_TIMING_TABLE_9[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_10", REG_SMC, 0x3f924, &ixMCARB_DRAM_TIMING_TABLE_10[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_10)/sizeof(ixMCARB_DRAM_TIMING_TABLE_10[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_11", REG_SMC, 0x3f928, &ixMCARB_DRAM_TIMING_TABLE_11[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_11)/sizeof(ixMCARB_DRAM_TIMING_TABLE_11[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_12", REG_SMC, 0x3f92c, &ixMCARB_DRAM_TIMING_TABLE_12[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_12)/sizeof(ixMCARB_DRAM_TIMING_TABLE_12[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_13", REG_SMC, 0x3f930, &ixMCARB_DRAM_TIMING_TABLE_13[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_13)/sizeof(ixMCARB_DRAM_TIMING_TABLE_13[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_14", REG_SMC, 0x3f934, &ixMCARB_DRAM_TIMING_TABLE_14[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_14)/sizeof(ixMCARB_DRAM_TIMING_TABLE_14[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_15", REG_SMC, 0x3f938, &ixMCARB_DRAM_TIMING_TABLE_15[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_15)/sizeof(ixMCARB_DRAM_TIMING_TABLE_15[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_16", REG_SMC, 0x3f93c, &ixMCARB_DRAM_TIMING_TABLE_16[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_16)/sizeof(ixMCARB_DRAM_TIMING_TABLE_16[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_17", REG_SMC, 0x3f940, &ixMCARB_DRAM_TIMING_TABLE_17[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_17)/sizeof(ixMCARB_DRAM_TIMING_TABLE_17[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_18", REG_SMC, 0x3f944, &ixMCARB_DRAM_TIMING_TABLE_18[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_18)/sizeof(ixMCARB_DRAM_TIMING_TABLE_18[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_19", REG_SMC, 0x3f948, &ixMCARB_DRAM_TIMING_TABLE_19[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_19)/sizeof(ixMCARB_DRAM_TIMING_TABLE_19[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_20", REG_SMC, 0x3f94c, &ixMCARB_DRAM_TIMING_TABLE_20[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_20)/sizeof(ixMCARB_DRAM_TIMING_TABLE_20[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_21", REG_SMC, 0x3f950, &ixMCARB_DRAM_TIMING_TABLE_21[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_21)/sizeof(ixMCARB_DRAM_TIMING_TABLE_21[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_22", REG_SMC, 0x3f954, &ixMCARB_DRAM_TIMING_TABLE_22[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_22)/sizeof(ixMCARB_DRAM_TIMING_TABLE_22[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_23", REG_SMC, 0x3f958, &ixMCARB_DRAM_TIMING_TABLE_23[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_23)/sizeof(ixMCARB_DRAM_TIMING_TABLE_23[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_24", REG_SMC, 0x3f95c, &ixMCARB_DRAM_TIMING_TABLE_24[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_24)/sizeof(ixMCARB_DRAM_TIMING_TABLE_24[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_25", REG_SMC, 0x3f960, &ixMCARB_DRAM_TIMING_TABLE_25[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_25)/sizeof(ixMCARB_DRAM_TIMING_TABLE_25[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_26", REG_SMC, 0x3f964, &ixMCARB_DRAM_TIMING_TABLE_26[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_26)/sizeof(ixMCARB_DRAM_TIMING_TABLE_26[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_27", REG_SMC, 0x3f968, &ixMCARB_DRAM_TIMING_TABLE_27[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_27)/sizeof(ixMCARB_DRAM_TIMING_TABLE_27[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_28", REG_SMC, 0x3f96c, &ixMCARB_DRAM_TIMING_TABLE_28[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_28)/sizeof(ixMCARB_DRAM_TIMING_TABLE_28[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_29", REG_SMC, 0x3f970, &ixMCARB_DRAM_TIMING_TABLE_29[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_29)/sizeof(ixMCARB_DRAM_TIMING_TABLE_29[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_30", REG_SMC, 0x3f974, &ixMCARB_DRAM_TIMING_TABLE_30[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_30)/sizeof(ixMCARB_DRAM_TIMING_TABLE_30[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_31", REG_SMC, 0x3f978, &ixMCARB_DRAM_TIMING_TABLE_31[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_31)/sizeof(ixMCARB_DRAM_TIMING_TABLE_31[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_32", REG_SMC, 0x3f97c, &ixMCARB_DRAM_TIMING_TABLE_32[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_32)/sizeof(ixMCARB_DRAM_TIMING_TABLE_32[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_33", REG_SMC, 0x3f980, &ixMCARB_DRAM_TIMING_TABLE_33[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_33)/sizeof(ixMCARB_DRAM_TIMING_TABLE_33[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_34", REG_SMC, 0x3f984, &ixMCARB_DRAM_TIMING_TABLE_34[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_34)/sizeof(ixMCARB_DRAM_TIMING_TABLE_34[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_35", REG_SMC, 0x3f988, &ixMCARB_DRAM_TIMING_TABLE_35[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_35)/sizeof(ixMCARB_DRAM_TIMING_TABLE_35[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_36", REG_SMC, 0x3f98c, &ixMCARB_DRAM_TIMING_TABLE_36[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_36)/sizeof(ixMCARB_DRAM_TIMING_TABLE_36[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_37", REG_SMC, 0x3f990, &ixMCARB_DRAM_TIMING_TABLE_37[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_37)/sizeof(ixMCARB_DRAM_TIMING_TABLE_37[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_38", REG_SMC, 0x3f994, &ixMCARB_DRAM_TIMING_TABLE_38[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_38)/sizeof(ixMCARB_DRAM_TIMING_TABLE_38[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_39", REG_SMC, 0x3f998, &ixMCARB_DRAM_TIMING_TABLE_39[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_39)/sizeof(ixMCARB_DRAM_TIMING_TABLE_39[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_40", REG_SMC, 0x3f99c, &ixMCARB_DRAM_TIMING_TABLE_40[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_40)/sizeof(ixMCARB_DRAM_TIMING_TABLE_40[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_41", REG_SMC, 0x3f9a0, &ixMCARB_DRAM_TIMING_TABLE_41[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_41)/sizeof(ixMCARB_DRAM_TIMING_TABLE_41[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_42", REG_SMC, 0x3f9a4, &ixMCARB_DRAM_TIMING_TABLE_42[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_42)/sizeof(ixMCARB_DRAM_TIMING_TABLE_42[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_43", REG_SMC, 0x3f9a8, &ixMCARB_DRAM_TIMING_TABLE_43[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_43)/sizeof(ixMCARB_DRAM_TIMING_TABLE_43[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_44", REG_SMC, 0x3f9ac, &ixMCARB_DRAM_TIMING_TABLE_44[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_44)/sizeof(ixMCARB_DRAM_TIMING_TABLE_44[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_45", REG_SMC, 0x3f9b0, &ixMCARB_DRAM_TIMING_TABLE_45[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_45)/sizeof(ixMCARB_DRAM_TIMING_TABLE_45[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_46", REG_SMC, 0x3f9b4, &ixMCARB_DRAM_TIMING_TABLE_46[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_46)/sizeof(ixMCARB_DRAM_TIMING_TABLE_46[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_47", REG_SMC, 0x3f9b8, &ixMCARB_DRAM_TIMING_TABLE_47[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_47)/sizeof(ixMCARB_DRAM_TIMING_TABLE_47[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_48", REG_SMC, 0x3f9bc, &ixMCARB_DRAM_TIMING_TABLE_48[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_48)/sizeof(ixMCARB_DRAM_TIMING_TABLE_48[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_49", REG_SMC, 0x3f9c0, &ixMCARB_DRAM_TIMING_TABLE_49[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_49)/sizeof(ixMCARB_DRAM_TIMING_TABLE_49[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_50", REG_SMC, 0x3f9c4, &ixMCARB_DRAM_TIMING_TABLE_50[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_50)/sizeof(ixMCARB_DRAM_TIMING_TABLE_50[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_51", REG_SMC, 0x3f9c8, &ixMCARB_DRAM_TIMING_TABLE_51[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_51)/sizeof(ixMCARB_DRAM_TIMING_TABLE_51[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_52", REG_SMC, 0x3f9cc, &ixMCARB_DRAM_TIMING_TABLE_52[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_52)/sizeof(ixMCARB_DRAM_TIMING_TABLE_52[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_53", REG_SMC, 0x3f9d0, &ixMCARB_DRAM_TIMING_TABLE_53[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_53)/sizeof(ixMCARB_DRAM_TIMING_TABLE_53[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_54", REG_SMC, 0x3f9d4, &ixMCARB_DRAM_TIMING_TABLE_54[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_54)/sizeof(ixMCARB_DRAM_TIMING_TABLE_54[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_55", REG_SMC, 0x3f9d8, &ixMCARB_DRAM_TIMING_TABLE_55[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_55)/sizeof(ixMCARB_DRAM_TIMING_TABLE_55[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_56", REG_SMC, 0x3f9dc, &ixMCARB_DRAM_TIMING_TABLE_56[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_56)/sizeof(ixMCARB_DRAM_TIMING_TABLE_56[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_57", REG_SMC, 0x3f9e0, &ixMCARB_DRAM_TIMING_TABLE_57[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_57)/sizeof(ixMCARB_DRAM_TIMING_TABLE_57[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_58", REG_SMC, 0x3f9e4, &ixMCARB_DRAM_TIMING_TABLE_58[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_58)/sizeof(ixMCARB_DRAM_TIMING_TABLE_58[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_59", REG_SMC, 0x3f9e8, &ixMCARB_DRAM_TIMING_TABLE_59[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_59)/sizeof(ixMCARB_DRAM_TIMING_TABLE_59[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_60", REG_SMC, 0x3f9ec, &ixMCARB_DRAM_TIMING_TABLE_60[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_60)/sizeof(ixMCARB_DRAM_TIMING_TABLE_60[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_61", REG_SMC, 0x3f9f0, &ixMCARB_DRAM_TIMING_TABLE_61[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_61)/sizeof(ixMCARB_DRAM_TIMING_TABLE_61[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_62", REG_SMC, 0x3f9f4, &ixMCARB_DRAM_TIMING_TABLE_62[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_62)/sizeof(ixMCARB_DRAM_TIMING_TABLE_62[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_63", REG_SMC, 0x3f9f8, &ixMCARB_DRAM_TIMING_TABLE_63[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_63)/sizeof(ixMCARB_DRAM_TIMING_TABLE_63[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_64", REG_SMC, 0x3f9fc, &ixMCARB_DRAM_TIMING_TABLE_64[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_64)/sizeof(ixMCARB_DRAM_TIMING_TABLE_64[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_65", REG_SMC, 0x3fa00, &ixMCARB_DRAM_TIMING_TABLE_65[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_65)/sizeof(ixMCARB_DRAM_TIMING_TABLE_65[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_66", REG_SMC, 0x3fa04, &ixMCARB_DRAM_TIMING_TABLE_66[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_66)/sizeof(ixMCARB_DRAM_TIMING_TABLE_66[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_67", REG_SMC, 0x3fa08, &ixMCARB_DRAM_TIMING_TABLE_67[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_67)/sizeof(ixMCARB_DRAM_TIMING_TABLE_67[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_68", REG_SMC, 0x3fa0c, &ixMCARB_DRAM_TIMING_TABLE_68[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_68)/sizeof(ixMCARB_DRAM_TIMING_TABLE_68[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_69", REG_SMC, 0x3fa10, &ixMCARB_DRAM_TIMING_TABLE_69[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_69)/sizeof(ixMCARB_DRAM_TIMING_TABLE_69[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_70", REG_SMC, 0x3fa14, &ixMCARB_DRAM_TIMING_TABLE_70[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_70)/sizeof(ixMCARB_DRAM_TIMING_TABLE_70[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_71", REG_SMC, 0x3fa18, &ixMCARB_DRAM_TIMING_TABLE_71[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_71)/sizeof(ixMCARB_DRAM_TIMING_TABLE_71[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_72", REG_SMC, 0x3fa1c, &ixMCARB_DRAM_TIMING_TABLE_72[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_72)/sizeof(ixMCARB_DRAM_TIMING_TABLE_72[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_73", REG_SMC, 0x3fa20, &ixMCARB_DRAM_TIMING_TABLE_73[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_73)/sizeof(ixMCARB_DRAM_TIMING_TABLE_73[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_74", REG_SMC, 0x3fa24, &ixMCARB_DRAM_TIMING_TABLE_74[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_74)/sizeof(ixMCARB_DRAM_TIMING_TABLE_74[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_75", REG_SMC, 0x3fa28, &ixMCARB_DRAM_TIMING_TABLE_75[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_75)/sizeof(ixMCARB_DRAM_TIMING_TABLE_75[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_76", REG_SMC, 0x3fa2c, &ixMCARB_DRAM_TIMING_TABLE_76[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_76)/sizeof(ixMCARB_DRAM_TIMING_TABLE_76[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_77", REG_SMC, 0x3fa30, &ixMCARB_DRAM_TIMING_TABLE_77[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_77)/sizeof(ixMCARB_DRAM_TIMING_TABLE_77[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_78", REG_SMC, 0x3fa34, &ixMCARB_DRAM_TIMING_TABLE_78[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_78)/sizeof(ixMCARB_DRAM_TIMING_TABLE_78[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_79", REG_SMC, 0x3fa38, &ixMCARB_DRAM_TIMING_TABLE_79[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_79)/sizeof(ixMCARB_DRAM_TIMING_TABLE_79[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_80", REG_SMC, 0x3fa3c, &ixMCARB_DRAM_TIMING_TABLE_80[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_80)/sizeof(ixMCARB_DRAM_TIMING_TABLE_80[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_81", REG_SMC, 0x3fa40, &ixMCARB_DRAM_TIMING_TABLE_81[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_81)/sizeof(ixMCARB_DRAM_TIMING_TABLE_81[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_82", REG_SMC, 0x3fa44, &ixMCARB_DRAM_TIMING_TABLE_82[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_82)/sizeof(ixMCARB_DRAM_TIMING_TABLE_82[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_83", REG_SMC, 0x3fa48, &ixMCARB_DRAM_TIMING_TABLE_83[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_83)/sizeof(ixMCARB_DRAM_TIMING_TABLE_83[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_84", REG_SMC, 0x3fa4c, &ixMCARB_DRAM_TIMING_TABLE_84[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_84)/sizeof(ixMCARB_DRAM_TIMING_TABLE_84[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_85", REG_SMC, 0x3fa50, &ixMCARB_DRAM_TIMING_TABLE_85[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_85)/sizeof(ixMCARB_DRAM_TIMING_TABLE_85[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_86", REG_SMC, 0x3fa54, &ixMCARB_DRAM_TIMING_TABLE_86[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_86)/sizeof(ixMCARB_DRAM_TIMING_TABLE_86[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_87", REG_SMC, 0x3fa58, &ixMCARB_DRAM_TIMING_TABLE_87[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_87)/sizeof(ixMCARB_DRAM_TIMING_TABLE_87[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_88", REG_SMC, 0x3fa5c, &ixMCARB_DRAM_TIMING_TABLE_88[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_88)/sizeof(ixMCARB_DRAM_TIMING_TABLE_88[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_89", REG_SMC, 0x3fa60, &ixMCARB_DRAM_TIMING_TABLE_89[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_89)/sizeof(ixMCARB_DRAM_TIMING_TABLE_89[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_90", REG_SMC, 0x3fa64, &ixMCARB_DRAM_TIMING_TABLE_90[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_90)/sizeof(ixMCARB_DRAM_TIMING_TABLE_90[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_91", REG_SMC, 0x3fa68, &ixMCARB_DRAM_TIMING_TABLE_91[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_91)/sizeof(ixMCARB_DRAM_TIMING_TABLE_91[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_92", REG_SMC, 0x3fa6c, &ixMCARB_DRAM_TIMING_TABLE_92[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_92)/sizeof(ixMCARB_DRAM_TIMING_TABLE_92[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_93", REG_SMC, 0x3fa70, &ixMCARB_DRAM_TIMING_TABLE_93[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_93)/sizeof(ixMCARB_DRAM_TIMING_TABLE_93[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_94", REG_SMC, 0x3fa74, &ixMCARB_DRAM_TIMING_TABLE_94[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_94)/sizeof(ixMCARB_DRAM_TIMING_TABLE_94[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_95", REG_SMC, 0x3fa78, &ixMCARB_DRAM_TIMING_TABLE_95[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_95)/sizeof(ixMCARB_DRAM_TIMING_TABLE_95[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_96", REG_SMC, 0x3fa7c, &ixMCARB_DRAM_TIMING_TABLE_96[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_96)/sizeof(ixMCARB_DRAM_TIMING_TABLE_96[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_1", REG_SMC, 0x3fa80, &ixMC_REGISTERS_TABLE_1[0], sizeof(ixMC_REGISTERS_TABLE_1)/sizeof(ixMC_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_2", REG_SMC, 0x3fa84, &ixMC_REGISTERS_TABLE_2[0], sizeof(ixMC_REGISTERS_TABLE_2)/sizeof(ixMC_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_3", REG_SMC, 0x3fa88, &ixMC_REGISTERS_TABLE_3[0], sizeof(ixMC_REGISTERS_TABLE_3)/sizeof(ixMC_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_4", REG_SMC, 0x3fa8c, &ixMC_REGISTERS_TABLE_4[0], sizeof(ixMC_REGISTERS_TABLE_4)/sizeof(ixMC_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_5", REG_SMC, 0x3fa90, &ixMC_REGISTERS_TABLE_5[0], sizeof(ixMC_REGISTERS_TABLE_5)/sizeof(ixMC_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_6", REG_SMC, 0x3fa94, &ixMC_REGISTERS_TABLE_6[0], sizeof(ixMC_REGISTERS_TABLE_6)/sizeof(ixMC_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_7", REG_SMC, 0x3fa98, &ixMC_REGISTERS_TABLE_7[0], sizeof(ixMC_REGISTERS_TABLE_7)/sizeof(ixMC_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_8", REG_SMC, 0x3fa9c, &ixMC_REGISTERS_TABLE_8[0], sizeof(ixMC_REGISTERS_TABLE_8)/sizeof(ixMC_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_9", REG_SMC, 0x3faa0, &ixMC_REGISTERS_TABLE_9[0], sizeof(ixMC_REGISTERS_TABLE_9)/sizeof(ixMC_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_10", REG_SMC, 0x3faa4, &ixMC_REGISTERS_TABLE_10[0], sizeof(ixMC_REGISTERS_TABLE_10)/sizeof(ixMC_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_11", REG_SMC, 0x3faa8, &ixMC_REGISTERS_TABLE_11[0], sizeof(ixMC_REGISTERS_TABLE_11)/sizeof(ixMC_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_12", REG_SMC, 0x3faac, &ixMC_REGISTERS_TABLE_12[0], sizeof(ixMC_REGISTERS_TABLE_12)/sizeof(ixMC_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_13", REG_SMC, 0x3fab0, &ixMC_REGISTERS_TABLE_13[0], sizeof(ixMC_REGISTERS_TABLE_13)/sizeof(ixMC_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_14", REG_SMC, 0x3fab4, &ixMC_REGISTERS_TABLE_14[0], sizeof(ixMC_REGISTERS_TABLE_14)/sizeof(ixMC_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_15", REG_SMC, 0x3fab8, &ixMC_REGISTERS_TABLE_15[0], sizeof(ixMC_REGISTERS_TABLE_15)/sizeof(ixMC_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_16", REG_SMC, 0x3fabc, &ixMC_REGISTERS_TABLE_16[0], sizeof(ixMC_REGISTERS_TABLE_16)/sizeof(ixMC_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_17", REG_SMC, 0x3fac0, &ixMC_REGISTERS_TABLE_17[0], sizeof(ixMC_REGISTERS_TABLE_17)/sizeof(ixMC_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_18", REG_SMC, 0x3fac4, &ixMC_REGISTERS_TABLE_18[0], sizeof(ixMC_REGISTERS_TABLE_18)/sizeof(ixMC_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_19", REG_SMC, 0x3fac8, &ixMC_REGISTERS_TABLE_19[0], sizeof(ixMC_REGISTERS_TABLE_19)/sizeof(ixMC_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_20", REG_SMC, 0x3facc, &ixMC_REGISTERS_TABLE_20[0], sizeof(ixMC_REGISTERS_TABLE_20)/sizeof(ixMC_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_21", REG_SMC, 0x3fad0, &ixMC_REGISTERS_TABLE_21[0], sizeof(ixMC_REGISTERS_TABLE_21)/sizeof(ixMC_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_22", REG_SMC, 0x3fad4, &ixMC_REGISTERS_TABLE_22[0], sizeof(ixMC_REGISTERS_TABLE_22)/sizeof(ixMC_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_23", REG_SMC, 0x3fad8, &ixMC_REGISTERS_TABLE_23[0], sizeof(ixMC_REGISTERS_TABLE_23)/sizeof(ixMC_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_24", REG_SMC, 0x3fadc, &ixMC_REGISTERS_TABLE_24[0], sizeof(ixMC_REGISTERS_TABLE_24)/sizeof(ixMC_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_25", REG_SMC, 0x3fae0, &ixMC_REGISTERS_TABLE_25[0], sizeof(ixMC_REGISTERS_TABLE_25)/sizeof(ixMC_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_26", REG_SMC, 0x3fae4, &ixMC_REGISTERS_TABLE_26[0], sizeof(ixMC_REGISTERS_TABLE_26)/sizeof(ixMC_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_27", REG_SMC, 0x3fae8, &ixMC_REGISTERS_TABLE_27[0], sizeof(ixMC_REGISTERS_TABLE_27)/sizeof(ixMC_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_28", REG_SMC, 0x3faec, &ixMC_REGISTERS_TABLE_28[0], sizeof(ixMC_REGISTERS_TABLE_28)/sizeof(ixMC_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_29", REG_SMC, 0x3faf0, &ixMC_REGISTERS_TABLE_29[0], sizeof(ixMC_REGISTERS_TABLE_29)/sizeof(ixMC_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_30", REG_SMC, 0x3faf4, &ixMC_REGISTERS_TABLE_30[0], sizeof(ixMC_REGISTERS_TABLE_30)/sizeof(ixMC_REGISTERS_TABLE_30[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_31", REG_SMC, 0x3faf8, &ixMC_REGISTERS_TABLE_31[0], sizeof(ixMC_REGISTERS_TABLE_31)/sizeof(ixMC_REGISTERS_TABLE_31[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_32", REG_SMC, 0x3fafc, &ixMC_REGISTERS_TABLE_32[0], sizeof(ixMC_REGISTERS_TABLE_32)/sizeof(ixMC_REGISTERS_TABLE_32[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_33", REG_SMC, 0x3fb00, &ixMC_REGISTERS_TABLE_33[0], sizeof(ixMC_REGISTERS_TABLE_33)/sizeof(ixMC_REGISTERS_TABLE_33[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_34", REG_SMC, 0x3fb04, &ixMC_REGISTERS_TABLE_34[0], sizeof(ixMC_REGISTERS_TABLE_34)/sizeof(ixMC_REGISTERS_TABLE_34[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_35", REG_SMC, 0x3fb08, &ixMC_REGISTERS_TABLE_35[0], sizeof(ixMC_REGISTERS_TABLE_35)/sizeof(ixMC_REGISTERS_TABLE_35[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_36", REG_SMC, 0x3fb0c, &ixMC_REGISTERS_TABLE_36[0], sizeof(ixMC_REGISTERS_TABLE_36)/sizeof(ixMC_REGISTERS_TABLE_36[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_37", REG_SMC, 0x3fb10, &ixMC_REGISTERS_TABLE_37[0], sizeof(ixMC_REGISTERS_TABLE_37)/sizeof(ixMC_REGISTERS_TABLE_37[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_38", REG_SMC, 0x3fb14, &ixMC_REGISTERS_TABLE_38[0], sizeof(ixMC_REGISTERS_TABLE_38)/sizeof(ixMC_REGISTERS_TABLE_38[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_39", REG_SMC, 0x3fb18, &ixMC_REGISTERS_TABLE_39[0], sizeof(ixMC_REGISTERS_TABLE_39)/sizeof(ixMC_REGISTERS_TABLE_39[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_40", REG_SMC, 0x3fb1c, &ixMC_REGISTERS_TABLE_40[0], sizeof(ixMC_REGISTERS_TABLE_40)/sizeof(ixMC_REGISTERS_TABLE_40[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_41", REG_SMC, 0x3fb20, &ixMC_REGISTERS_TABLE_41[0], sizeof(ixMC_REGISTERS_TABLE_41)/sizeof(ixMC_REGISTERS_TABLE_41[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_42", REG_SMC, 0x3fb24, &ixMC_REGISTERS_TABLE_42[0], sizeof(ixMC_REGISTERS_TABLE_42)/sizeof(ixMC_REGISTERS_TABLE_42[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_43", REG_SMC, 0x3fb28, &ixMC_REGISTERS_TABLE_43[0], sizeof(ixMC_REGISTERS_TABLE_43)/sizeof(ixMC_REGISTERS_TABLE_43[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_44", REG_SMC, 0x3fb2c, &ixMC_REGISTERS_TABLE_44[0], sizeof(ixMC_REGISTERS_TABLE_44)/sizeof(ixMC_REGISTERS_TABLE_44[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_45", REG_SMC, 0x3fb30, &ixMC_REGISTERS_TABLE_45[0], sizeof(ixMC_REGISTERS_TABLE_45)/sizeof(ixMC_REGISTERS_TABLE_45[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_46", REG_SMC, 0x3fb34, &ixMC_REGISTERS_TABLE_46[0], sizeof(ixMC_REGISTERS_TABLE_46)/sizeof(ixMC_REGISTERS_TABLE_46[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_47", REG_SMC, 0x3fb38, &ixMC_REGISTERS_TABLE_47[0], sizeof(ixMC_REGISTERS_TABLE_47)/sizeof(ixMC_REGISTERS_TABLE_47[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_48", REG_SMC, 0x3fb3c, &ixMC_REGISTERS_TABLE_48[0], sizeof(ixMC_REGISTERS_TABLE_48)/sizeof(ixMC_REGISTERS_TABLE_48[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_49", REG_SMC, 0x3fb40, &ixMC_REGISTERS_TABLE_49[0], sizeof(ixMC_REGISTERS_TABLE_49)/sizeof(ixMC_REGISTERS_TABLE_49[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_50", REG_SMC, 0x3fb44, &ixMC_REGISTERS_TABLE_50[0], sizeof(ixMC_REGISTERS_TABLE_50)/sizeof(ixMC_REGISTERS_TABLE_50[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_51", REG_SMC, 0x3fb48, &ixMC_REGISTERS_TABLE_51[0], sizeof(ixMC_REGISTERS_TABLE_51)/sizeof(ixMC_REGISTERS_TABLE_51[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_52", REG_SMC, 0x3fb4c, &ixMC_REGISTERS_TABLE_52[0], sizeof(ixMC_REGISTERS_TABLE_52)/sizeof(ixMC_REGISTERS_TABLE_52[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_53", REG_SMC, 0x3fb50, &ixMC_REGISTERS_TABLE_53[0], sizeof(ixMC_REGISTERS_TABLE_53)/sizeof(ixMC_REGISTERS_TABLE_53[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_54", REG_SMC, 0x3fb54, &ixMC_REGISTERS_TABLE_54[0], sizeof(ixMC_REGISTERS_TABLE_54)/sizeof(ixMC_REGISTERS_TABLE_54[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_55", REG_SMC, 0x3fb58, &ixMC_REGISTERS_TABLE_55[0], sizeof(ixMC_REGISTERS_TABLE_55)/sizeof(ixMC_REGISTERS_TABLE_55[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_56", REG_SMC, 0x3fb5c, &ixMC_REGISTERS_TABLE_56[0], sizeof(ixMC_REGISTERS_TABLE_56)/sizeof(ixMC_REGISTERS_TABLE_56[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_57", REG_SMC, 0x3fb60, &ixMC_REGISTERS_TABLE_57[0], sizeof(ixMC_REGISTERS_TABLE_57)/sizeof(ixMC_REGISTERS_TABLE_57[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_58", REG_SMC, 0x3fb64, &ixMC_REGISTERS_TABLE_58[0], sizeof(ixMC_REGISTERS_TABLE_58)/sizeof(ixMC_REGISTERS_TABLE_58[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_59", REG_SMC, 0x3fb68, &ixMC_REGISTERS_TABLE_59[0], sizeof(ixMC_REGISTERS_TABLE_59)/sizeof(ixMC_REGISTERS_TABLE_59[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_60", REG_SMC, 0x3fb6c, &ixMC_REGISTERS_TABLE_60[0], sizeof(ixMC_REGISTERS_TABLE_60)/sizeof(ixMC_REGISTERS_TABLE_60[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_61", REG_SMC, 0x3fb70, &ixMC_REGISTERS_TABLE_61[0], sizeof(ixMC_REGISTERS_TABLE_61)/sizeof(ixMC_REGISTERS_TABLE_61[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_62", REG_SMC, 0x3fb74, &ixMC_REGISTERS_TABLE_62[0], sizeof(ixMC_REGISTERS_TABLE_62)/sizeof(ixMC_REGISTERS_TABLE_62[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_63", REG_SMC, 0x3fb78, &ixMC_REGISTERS_TABLE_63[0], sizeof(ixMC_REGISTERS_TABLE_63)/sizeof(ixMC_REGISTERS_TABLE_63[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_64", REG_SMC, 0x3fb7c, &ixMC_REGISTERS_TABLE_64[0], sizeof(ixMC_REGISTERS_TABLE_64)/sizeof(ixMC_REGISTERS_TABLE_64[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_65", REG_SMC, 0x3fb80, &ixMC_REGISTERS_TABLE_65[0], sizeof(ixMC_REGISTERS_TABLE_65)/sizeof(ixMC_REGISTERS_TABLE_65[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_66", REG_SMC, 0x3fb84, &ixMC_REGISTERS_TABLE_66[0], sizeof(ixMC_REGISTERS_TABLE_66)/sizeof(ixMC_REGISTERS_TABLE_66[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_67", REG_SMC, 0x3fb88, &ixMC_REGISTERS_TABLE_67[0], sizeof(ixMC_REGISTERS_TABLE_67)/sizeof(ixMC_REGISTERS_TABLE_67[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_68", REG_SMC, 0x3fb8c, &ixMC_REGISTERS_TABLE_68[0], sizeof(ixMC_REGISTERS_TABLE_68)/sizeof(ixMC_REGISTERS_TABLE_68[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_69", REG_SMC, 0x3fb90, &ixMC_REGISTERS_TABLE_69[0], sizeof(ixMC_REGISTERS_TABLE_69)/sizeof(ixMC_REGISTERS_TABLE_69[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_70", REG_SMC, 0x3fb94, &ixMC_REGISTERS_TABLE_70[0], sizeof(ixMC_REGISTERS_TABLE_70)/sizeof(ixMC_REGISTERS_TABLE_70[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_71", REG_SMC, 0x3fb98, &ixMC_REGISTERS_TABLE_71[0], sizeof(ixMC_REGISTERS_TABLE_71)/sizeof(ixMC_REGISTERS_TABLE_71[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_72", REG_SMC, 0x3fb9c, &ixMC_REGISTERS_TABLE_72[0], sizeof(ixMC_REGISTERS_TABLE_72)/sizeof(ixMC_REGISTERS_TABLE_72[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_73", REG_SMC, 0x3fba0, &ixMC_REGISTERS_TABLE_73[0], sizeof(ixMC_REGISTERS_TABLE_73)/sizeof(ixMC_REGISTERS_TABLE_73[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_74", REG_SMC, 0x3fba4, &ixMC_REGISTERS_TABLE_74[0], sizeof(ixMC_REGISTERS_TABLE_74)/sizeof(ixMC_REGISTERS_TABLE_74[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_75", REG_SMC, 0x3fba8, &ixMC_REGISTERS_TABLE_75[0], sizeof(ixMC_REGISTERS_TABLE_75)/sizeof(ixMC_REGISTERS_TABLE_75[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_76", REG_SMC, 0x3fbac, &ixMC_REGISTERS_TABLE_76[0], sizeof(ixMC_REGISTERS_TABLE_76)/sizeof(ixMC_REGISTERS_TABLE_76[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_77", REG_SMC, 0x3fbb0, &ixMC_REGISTERS_TABLE_77[0], sizeof(ixMC_REGISTERS_TABLE_77)/sizeof(ixMC_REGISTERS_TABLE_77[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_78", REG_SMC, 0x3fbb4, &ixMC_REGISTERS_TABLE_78[0], sizeof(ixMC_REGISTERS_TABLE_78)/sizeof(ixMC_REGISTERS_TABLE_78[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_79", REG_SMC, 0x3fbb8, &ixMC_REGISTERS_TABLE_79[0], sizeof(ixMC_REGISTERS_TABLE_79)/sizeof(ixMC_REGISTERS_TABLE_79[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_80", REG_SMC, 0x3fbbc, &ixMC_REGISTERS_TABLE_80[0], sizeof(ixMC_REGISTERS_TABLE_80)/sizeof(ixMC_REGISTERS_TABLE_80[0]), 0, 0 },
+	{ "ixMC_REGISTERS_TABLE_81", REG_SMC, 0x3fbc0, &ixMC_REGISTERS_TABLE_81[0], sizeof(ixMC_REGISTERS_TABLE_81)/sizeof(ixMC_REGISTERS_TABLE_81[0]), 0, 0 },
+	{ "ixFAN_TABLE_1", REG_SMC, 0x3fbc4, &ixFAN_TABLE_1[0], sizeof(ixFAN_TABLE_1)/sizeof(ixFAN_TABLE_1[0]), 0, 0 },
+	{ "ixFAN_TABLE_2", REG_SMC, 0x3fbc8, &ixFAN_TABLE_2[0], sizeof(ixFAN_TABLE_2)/sizeof(ixFAN_TABLE_2[0]), 0, 0 },
+	{ "ixFAN_TABLE_3", REG_SMC, 0x3fbcc, &ixFAN_TABLE_3[0], sizeof(ixFAN_TABLE_3)/sizeof(ixFAN_TABLE_3[0]), 0, 0 },
+	{ "ixFAN_TABLE_4", REG_SMC, 0x3fbd0, &ixFAN_TABLE_4[0], sizeof(ixFAN_TABLE_4)/sizeof(ixFAN_TABLE_4[0]), 0, 0 },
+	{ "ixFAN_TABLE_5", REG_SMC, 0x3fbd4, &ixFAN_TABLE_5[0], sizeof(ixFAN_TABLE_5)/sizeof(ixFAN_TABLE_5[0]), 0, 0 },
+	{ "ixFAN_TABLE_6", REG_SMC, 0x3fbd8, &ixFAN_TABLE_6[0], sizeof(ixFAN_TABLE_6)/sizeof(ixFAN_TABLE_6[0]), 0, 0 },
+	{ "ixFAN_TABLE_7", REG_SMC, 0x3fbdc, &ixFAN_TABLE_7[0], sizeof(ixFAN_TABLE_7)/sizeof(ixFAN_TABLE_7[0]), 0, 0 },
+	{ "ixFAN_TABLE_8", REG_SMC, 0x3fbe0, &ixFAN_TABLE_8[0], sizeof(ixFAN_TABLE_8)/sizeof(ixFAN_TABLE_8[0]), 0, 0 },
+	{ "ixFAN_TABLE_9", REG_SMC, 0x3fbe4, &ixFAN_TABLE_9[0], sizeof(ixFAN_TABLE_9)/sizeof(ixFAN_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_1", REG_SMC, 0x3fbe8, &ixSOFT_REGISTERS_TABLE_1[0], sizeof(ixSOFT_REGISTERS_TABLE_1)/sizeof(ixSOFT_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_2", REG_SMC, 0x3fbec, &ixSOFT_REGISTERS_TABLE_2[0], sizeof(ixSOFT_REGISTERS_TABLE_2)/sizeof(ixSOFT_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_3", REG_SMC, 0x3fbf0, &ixSOFT_REGISTERS_TABLE_3[0], sizeof(ixSOFT_REGISTERS_TABLE_3)/sizeof(ixSOFT_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_4", REG_SMC, 0x3fbf4, &ixSOFT_REGISTERS_TABLE_4[0], sizeof(ixSOFT_REGISTERS_TABLE_4)/sizeof(ixSOFT_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_5", REG_SMC, 0x3fbf8, &ixSOFT_REGISTERS_TABLE_5[0], sizeof(ixSOFT_REGISTERS_TABLE_5)/sizeof(ixSOFT_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_6", REG_SMC, 0x3fbfc, &ixSOFT_REGISTERS_TABLE_6[0], sizeof(ixSOFT_REGISTERS_TABLE_6)/sizeof(ixSOFT_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_7", REG_SMC, 0x3fc00, &ixSOFT_REGISTERS_TABLE_7[0], sizeof(ixSOFT_REGISTERS_TABLE_7)/sizeof(ixSOFT_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_8", REG_SMC, 0x3fc04, &ixSOFT_REGISTERS_TABLE_8[0], sizeof(ixSOFT_REGISTERS_TABLE_8)/sizeof(ixSOFT_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_9", REG_SMC, 0x3fc08, &ixSOFT_REGISTERS_TABLE_9[0], sizeof(ixSOFT_REGISTERS_TABLE_9)/sizeof(ixSOFT_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_10", REG_SMC, 0x3fc0c, &ixSOFT_REGISTERS_TABLE_10[0], sizeof(ixSOFT_REGISTERS_TABLE_10)/sizeof(ixSOFT_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_11", REG_SMC, 0x3fc10, &ixSOFT_REGISTERS_TABLE_11[0], sizeof(ixSOFT_REGISTERS_TABLE_11)/sizeof(ixSOFT_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_12", REG_SMC, 0x3fc14, &ixSOFT_REGISTERS_TABLE_12[0], sizeof(ixSOFT_REGISTERS_TABLE_12)/sizeof(ixSOFT_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_13", REG_SMC, 0x3fc18, &ixSOFT_REGISTERS_TABLE_13[0], sizeof(ixSOFT_REGISTERS_TABLE_13)/sizeof(ixSOFT_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_14", REG_SMC, 0x3fc1c, &ixSOFT_REGISTERS_TABLE_14[0], sizeof(ixSOFT_REGISTERS_TABLE_14)/sizeof(ixSOFT_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_15", REG_SMC, 0x3fc20, &ixSOFT_REGISTERS_TABLE_15[0], sizeof(ixSOFT_REGISTERS_TABLE_15)/sizeof(ixSOFT_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_16", REG_SMC, 0x3fc24, &ixSOFT_REGISTERS_TABLE_16[0], sizeof(ixSOFT_REGISTERS_TABLE_16)/sizeof(ixSOFT_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_17", REG_SMC, 0x3fc28, &ixSOFT_REGISTERS_TABLE_17[0], sizeof(ixSOFT_REGISTERS_TABLE_17)/sizeof(ixSOFT_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_18", REG_SMC, 0x3fc2c, &ixSOFT_REGISTERS_TABLE_18[0], sizeof(ixSOFT_REGISTERS_TABLE_18)/sizeof(ixSOFT_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_19", REG_SMC, 0x3fc30, &ixSOFT_REGISTERS_TABLE_19[0], sizeof(ixSOFT_REGISTERS_TABLE_19)/sizeof(ixSOFT_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_20", REG_SMC, 0x3fc34, &ixSOFT_REGISTERS_TABLE_20[0], sizeof(ixSOFT_REGISTERS_TABLE_20)/sizeof(ixSOFT_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_21", REG_SMC, 0x3fc38, &ixSOFT_REGISTERS_TABLE_21[0], sizeof(ixSOFT_REGISTERS_TABLE_21)/sizeof(ixSOFT_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_22", REG_SMC, 0x3fc3c, &ixSOFT_REGISTERS_TABLE_22[0], sizeof(ixSOFT_REGISTERS_TABLE_22)/sizeof(ixSOFT_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_23", REG_SMC, 0x3fc40, &ixSOFT_REGISTERS_TABLE_23[0], sizeof(ixSOFT_REGISTERS_TABLE_23)/sizeof(ixSOFT_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_24", REG_SMC, 0x3fc44, &ixSOFT_REGISTERS_TABLE_24[0], sizeof(ixSOFT_REGISTERS_TABLE_24)/sizeof(ixSOFT_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_25", REG_SMC, 0x3fc48, &ixSOFT_REGISTERS_TABLE_25[0], sizeof(ixSOFT_REGISTERS_TABLE_25)/sizeof(ixSOFT_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_26", REG_SMC, 0x3fc4c, &ixSOFT_REGISTERS_TABLE_26[0], sizeof(ixSOFT_REGISTERS_TABLE_26)/sizeof(ixSOFT_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_27", REG_SMC, 0x3fc50, &ixSOFT_REGISTERS_TABLE_27[0], sizeof(ixSOFT_REGISTERS_TABLE_27)/sizeof(ixSOFT_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_28", REG_SMC, 0x3fc54, &ixSOFT_REGISTERS_TABLE_28[0], sizeof(ixSOFT_REGISTERS_TABLE_28)/sizeof(ixSOFT_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_29", REG_SMC, 0x3fc58, &ixSOFT_REGISTERS_TABLE_29[0], sizeof(ixSOFT_REGISTERS_TABLE_29)/sizeof(ixSOFT_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_30", REG_SMC, 0x3fc5c, &ixSOFT_REGISTERS_TABLE_30[0], sizeof(ixSOFT_REGISTERS_TABLE_30)/sizeof(ixSOFT_REGISTERS_TABLE_30[0]), 0, 0 },
+	{ "ixPM_FUSES_1", REG_SMC, 0x3fc60, &ixPM_FUSES_1[0], sizeof(ixPM_FUSES_1)/sizeof(ixPM_FUSES_1[0]), 0, 0 },
+	{ "ixPM_FUSES_2", REG_SMC, 0x3fc64, &ixPM_FUSES_2[0], sizeof(ixPM_FUSES_2)/sizeof(ixPM_FUSES_2[0]), 0, 0 },
+	{ "ixPM_FUSES_3", REG_SMC, 0x3fc68, &ixPM_FUSES_3[0], sizeof(ixPM_FUSES_3)/sizeof(ixPM_FUSES_3[0]), 0, 0 },
+	{ "ixPM_FUSES_4", REG_SMC, 0x3fc6c, &ixPM_FUSES_4[0], sizeof(ixPM_FUSES_4)/sizeof(ixPM_FUSES_4[0]), 0, 0 },
+	{ "ixPM_FUSES_5", REG_SMC, 0x3fc70, &ixPM_FUSES_5[0], sizeof(ixPM_FUSES_5)/sizeof(ixPM_FUSES_5[0]), 0, 0 },
+	{ "ixPM_FUSES_6", REG_SMC, 0x3fc74, &ixPM_FUSES_6[0], sizeof(ixPM_FUSES_6)/sizeof(ixPM_FUSES_6[0]), 0, 0 },
+	{ "ixPM_FUSES_7", REG_SMC, 0x3fc78, &ixPM_FUSES_7[0], sizeof(ixPM_FUSES_7)/sizeof(ixPM_FUSES_7[0]), 0, 0 },
+	{ "ixPM_FUSES_8", REG_SMC, 0x3fc7c, &ixPM_FUSES_8[0], sizeof(ixPM_FUSES_8)/sizeof(ixPM_FUSES_8[0]), 0, 0 },
+	{ "ixPM_FUSES_9", REG_SMC, 0x3fc80, &ixPM_FUSES_9[0], sizeof(ixPM_FUSES_9)/sizeof(ixPM_FUSES_9[0]), 0, 0 },
+	{ "ixPM_FUSES_10", REG_SMC, 0x3fc84, &ixPM_FUSES_10[0], sizeof(ixPM_FUSES_10)/sizeof(ixPM_FUSES_10[0]), 0, 0 },
+	{ "ixPM_FUSES_11", REG_SMC, 0x3fc88, &ixPM_FUSES_11[0], sizeof(ixPM_FUSES_11)/sizeof(ixPM_FUSES_11[0]), 0, 0 },
+	{ "ixPM_FUSES_12", REG_SMC, 0x3fc8c, &ixPM_FUSES_12[0], sizeof(ixPM_FUSES_12)/sizeof(ixPM_FUSES_12[0]), 0, 0 },
+	{ "ixPM_FUSES_13", REG_SMC, 0x3fc90, &ixPM_FUSES_13[0], sizeof(ixPM_FUSES_13)/sizeof(ixPM_FUSES_13[0]), 0, 0 },
+	{ "ixPM_FUSES_14", REG_SMC, 0x3fc94, &ixPM_FUSES_14[0], sizeof(ixPM_FUSES_14)/sizeof(ixPM_FUSES_14[0]), 0, 0 },
+	{ "ixPM_FUSES_15", REG_SMC, 0x3fc98, &ixPM_FUSES_15[0], sizeof(ixPM_FUSES_15)/sizeof(ixPM_FUSES_15[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_0", REG_SMC, 0x3fe00, &ixSMU_PM_STATUS_0[0], sizeof(ixSMU_PM_STATUS_0)/sizeof(ixSMU_PM_STATUS_0[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_1", REG_SMC, 0x3fe04, &ixSMU_PM_STATUS_1[0], sizeof(ixSMU_PM_STATUS_1)/sizeof(ixSMU_PM_STATUS_1[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_2", REG_SMC, 0x3fe08, &ixSMU_PM_STATUS_2[0], sizeof(ixSMU_PM_STATUS_2)/sizeof(ixSMU_PM_STATUS_2[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_3", REG_SMC, 0x3fe0c, &ixSMU_PM_STATUS_3[0], sizeof(ixSMU_PM_STATUS_3)/sizeof(ixSMU_PM_STATUS_3[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_4", REG_SMC, 0x3fe10, &ixSMU_PM_STATUS_4[0], sizeof(ixSMU_PM_STATUS_4)/sizeof(ixSMU_PM_STATUS_4[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_5", REG_SMC, 0x3fe14, &ixSMU_PM_STATUS_5[0], sizeof(ixSMU_PM_STATUS_5)/sizeof(ixSMU_PM_STATUS_5[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_6", REG_SMC, 0x3fe18, &ixSMU_PM_STATUS_6[0], sizeof(ixSMU_PM_STATUS_6)/sizeof(ixSMU_PM_STATUS_6[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_7", REG_SMC, 0x3fe1c, &ixSMU_PM_STATUS_7[0], sizeof(ixSMU_PM_STATUS_7)/sizeof(ixSMU_PM_STATUS_7[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_8", REG_SMC, 0x3fe20, &ixSMU_PM_STATUS_8[0], sizeof(ixSMU_PM_STATUS_8)/sizeof(ixSMU_PM_STATUS_8[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_9", REG_SMC, 0x3fe24, &ixSMU_PM_STATUS_9[0], sizeof(ixSMU_PM_STATUS_9)/sizeof(ixSMU_PM_STATUS_9[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_10", REG_SMC, 0x3fe28, &ixSMU_PM_STATUS_10[0], sizeof(ixSMU_PM_STATUS_10)/sizeof(ixSMU_PM_STATUS_10[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_11", REG_SMC, 0x3fe2c, &ixSMU_PM_STATUS_11[0], sizeof(ixSMU_PM_STATUS_11)/sizeof(ixSMU_PM_STATUS_11[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_12", REG_SMC, 0x3fe30, &ixSMU_PM_STATUS_12[0], sizeof(ixSMU_PM_STATUS_12)/sizeof(ixSMU_PM_STATUS_12[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_13", REG_SMC, 0x3fe34, &ixSMU_PM_STATUS_13[0], sizeof(ixSMU_PM_STATUS_13)/sizeof(ixSMU_PM_STATUS_13[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_14", REG_SMC, 0x3fe38, &ixSMU_PM_STATUS_14[0], sizeof(ixSMU_PM_STATUS_14)/sizeof(ixSMU_PM_STATUS_14[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_15", REG_SMC, 0x3fe3c, &ixSMU_PM_STATUS_15[0], sizeof(ixSMU_PM_STATUS_15)/sizeof(ixSMU_PM_STATUS_15[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_16", REG_SMC, 0x3fe40, &ixSMU_PM_STATUS_16[0], sizeof(ixSMU_PM_STATUS_16)/sizeof(ixSMU_PM_STATUS_16[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_17", REG_SMC, 0x3fe44, &ixSMU_PM_STATUS_17[0], sizeof(ixSMU_PM_STATUS_17)/sizeof(ixSMU_PM_STATUS_17[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_18", REG_SMC, 0x3fe48, &ixSMU_PM_STATUS_18[0], sizeof(ixSMU_PM_STATUS_18)/sizeof(ixSMU_PM_STATUS_18[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_19", REG_SMC, 0x3fe4c, &ixSMU_PM_STATUS_19[0], sizeof(ixSMU_PM_STATUS_19)/sizeof(ixSMU_PM_STATUS_19[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_20", REG_SMC, 0x3fe50, &ixSMU_PM_STATUS_20[0], sizeof(ixSMU_PM_STATUS_20)/sizeof(ixSMU_PM_STATUS_20[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_21", REG_SMC, 0x3fe54, &ixSMU_PM_STATUS_21[0], sizeof(ixSMU_PM_STATUS_21)/sizeof(ixSMU_PM_STATUS_21[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_22", REG_SMC, 0x3fe58, &ixSMU_PM_STATUS_22[0], sizeof(ixSMU_PM_STATUS_22)/sizeof(ixSMU_PM_STATUS_22[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_23", REG_SMC, 0x3fe5c, &ixSMU_PM_STATUS_23[0], sizeof(ixSMU_PM_STATUS_23)/sizeof(ixSMU_PM_STATUS_23[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_24", REG_SMC, 0x3fe60, &ixSMU_PM_STATUS_24[0], sizeof(ixSMU_PM_STATUS_24)/sizeof(ixSMU_PM_STATUS_24[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_25", REG_SMC, 0x3fe64, &ixSMU_PM_STATUS_25[0], sizeof(ixSMU_PM_STATUS_25)/sizeof(ixSMU_PM_STATUS_25[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_26", REG_SMC, 0x3fe68, &ixSMU_PM_STATUS_26[0], sizeof(ixSMU_PM_STATUS_26)/sizeof(ixSMU_PM_STATUS_26[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_27", REG_SMC, 0x3fe6c, &ixSMU_PM_STATUS_27[0], sizeof(ixSMU_PM_STATUS_27)/sizeof(ixSMU_PM_STATUS_27[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_28", REG_SMC, 0x3fe70, &ixSMU_PM_STATUS_28[0], sizeof(ixSMU_PM_STATUS_28)/sizeof(ixSMU_PM_STATUS_28[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_29", REG_SMC, 0x3fe74, &ixSMU_PM_STATUS_29[0], sizeof(ixSMU_PM_STATUS_29)/sizeof(ixSMU_PM_STATUS_29[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_30", REG_SMC, 0x3fe78, &ixSMU_PM_STATUS_30[0], sizeof(ixSMU_PM_STATUS_30)/sizeof(ixSMU_PM_STATUS_30[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_31", REG_SMC, 0x3fe7c, &ixSMU_PM_STATUS_31[0], sizeof(ixSMU_PM_STATUS_31)/sizeof(ixSMU_PM_STATUS_31[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_32", REG_SMC, 0x3fe80, &ixSMU_PM_STATUS_32[0], sizeof(ixSMU_PM_STATUS_32)/sizeof(ixSMU_PM_STATUS_32[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_33", REG_SMC, 0x3fe84, &ixSMU_PM_STATUS_33[0], sizeof(ixSMU_PM_STATUS_33)/sizeof(ixSMU_PM_STATUS_33[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_34", REG_SMC, 0x3fe88, &ixSMU_PM_STATUS_34[0], sizeof(ixSMU_PM_STATUS_34)/sizeof(ixSMU_PM_STATUS_34[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_35", REG_SMC, 0x3fe8c, &ixSMU_PM_STATUS_35[0], sizeof(ixSMU_PM_STATUS_35)/sizeof(ixSMU_PM_STATUS_35[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_36", REG_SMC, 0x3fe90, &ixSMU_PM_STATUS_36[0], sizeof(ixSMU_PM_STATUS_36)/sizeof(ixSMU_PM_STATUS_36[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_37", REG_SMC, 0x3fe94, &ixSMU_PM_STATUS_37[0], sizeof(ixSMU_PM_STATUS_37)/sizeof(ixSMU_PM_STATUS_37[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_38", REG_SMC, 0x3fe98, &ixSMU_PM_STATUS_38[0], sizeof(ixSMU_PM_STATUS_38)/sizeof(ixSMU_PM_STATUS_38[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_39", REG_SMC, 0x3fe9c, &ixSMU_PM_STATUS_39[0], sizeof(ixSMU_PM_STATUS_39)/sizeof(ixSMU_PM_STATUS_39[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_40", REG_SMC, 0x3fea0, &ixSMU_PM_STATUS_40[0], sizeof(ixSMU_PM_STATUS_40)/sizeof(ixSMU_PM_STATUS_40[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_41", REG_SMC, 0x3fea4, &ixSMU_PM_STATUS_41[0], sizeof(ixSMU_PM_STATUS_41)/sizeof(ixSMU_PM_STATUS_41[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_42", REG_SMC, 0x3fea8, &ixSMU_PM_STATUS_42[0], sizeof(ixSMU_PM_STATUS_42)/sizeof(ixSMU_PM_STATUS_42[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_43", REG_SMC, 0x3feac, &ixSMU_PM_STATUS_43[0], sizeof(ixSMU_PM_STATUS_43)/sizeof(ixSMU_PM_STATUS_43[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_44", REG_SMC, 0x3feb0, &ixSMU_PM_STATUS_44[0], sizeof(ixSMU_PM_STATUS_44)/sizeof(ixSMU_PM_STATUS_44[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_45", REG_SMC, 0x3feb4, &ixSMU_PM_STATUS_45[0], sizeof(ixSMU_PM_STATUS_45)/sizeof(ixSMU_PM_STATUS_45[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_46", REG_SMC, 0x3feb8, &ixSMU_PM_STATUS_46[0], sizeof(ixSMU_PM_STATUS_46)/sizeof(ixSMU_PM_STATUS_46[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_47", REG_SMC, 0x3febc, &ixSMU_PM_STATUS_47[0], sizeof(ixSMU_PM_STATUS_47)/sizeof(ixSMU_PM_STATUS_47[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_48", REG_SMC, 0x3fec0, &ixSMU_PM_STATUS_48[0], sizeof(ixSMU_PM_STATUS_48)/sizeof(ixSMU_PM_STATUS_48[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_49", REG_SMC, 0x3fec4, &ixSMU_PM_STATUS_49[0], sizeof(ixSMU_PM_STATUS_49)/sizeof(ixSMU_PM_STATUS_49[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_50", REG_SMC, 0x3fec8, &ixSMU_PM_STATUS_50[0], sizeof(ixSMU_PM_STATUS_50)/sizeof(ixSMU_PM_STATUS_50[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_51", REG_SMC, 0x3fecc, &ixSMU_PM_STATUS_51[0], sizeof(ixSMU_PM_STATUS_51)/sizeof(ixSMU_PM_STATUS_51[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_52", REG_SMC, 0x3fed0, &ixSMU_PM_STATUS_52[0], sizeof(ixSMU_PM_STATUS_52)/sizeof(ixSMU_PM_STATUS_52[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_53", REG_SMC, 0x3fed4, &ixSMU_PM_STATUS_53[0], sizeof(ixSMU_PM_STATUS_53)/sizeof(ixSMU_PM_STATUS_53[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_54", REG_SMC, 0x3fed8, &ixSMU_PM_STATUS_54[0], sizeof(ixSMU_PM_STATUS_54)/sizeof(ixSMU_PM_STATUS_54[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_55", REG_SMC, 0x3fedc, &ixSMU_PM_STATUS_55[0], sizeof(ixSMU_PM_STATUS_55)/sizeof(ixSMU_PM_STATUS_55[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_56", REG_SMC, 0x3fee0, &ixSMU_PM_STATUS_56[0], sizeof(ixSMU_PM_STATUS_56)/sizeof(ixSMU_PM_STATUS_56[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_57", REG_SMC, 0x3fee4, &ixSMU_PM_STATUS_57[0], sizeof(ixSMU_PM_STATUS_57)/sizeof(ixSMU_PM_STATUS_57[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_58", REG_SMC, 0x3fee8, &ixSMU_PM_STATUS_58[0], sizeof(ixSMU_PM_STATUS_58)/sizeof(ixSMU_PM_STATUS_58[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_59", REG_SMC, 0x3feec, &ixSMU_PM_STATUS_59[0], sizeof(ixSMU_PM_STATUS_59)/sizeof(ixSMU_PM_STATUS_59[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_60", REG_SMC, 0x3fef0, &ixSMU_PM_STATUS_60[0], sizeof(ixSMU_PM_STATUS_60)/sizeof(ixSMU_PM_STATUS_60[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_61", REG_SMC, 0x3fef4, &ixSMU_PM_STATUS_61[0], sizeof(ixSMU_PM_STATUS_61)/sizeof(ixSMU_PM_STATUS_61[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_62", REG_SMC, 0x3fef8, &ixSMU_PM_STATUS_62[0], sizeof(ixSMU_PM_STATUS_62)/sizeof(ixSMU_PM_STATUS_62[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_63", REG_SMC, 0x3fefc, &ixSMU_PM_STATUS_63[0], sizeof(ixSMU_PM_STATUS_63)/sizeof(ixSMU_PM_STATUS_63[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_64", REG_SMC, 0x3ff00, &ixSMU_PM_STATUS_64[0], sizeof(ixSMU_PM_STATUS_64)/sizeof(ixSMU_PM_STATUS_64[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_65", REG_SMC, 0x3ff04, &ixSMU_PM_STATUS_65[0], sizeof(ixSMU_PM_STATUS_65)/sizeof(ixSMU_PM_STATUS_65[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_66", REG_SMC, 0x3ff08, &ixSMU_PM_STATUS_66[0], sizeof(ixSMU_PM_STATUS_66)/sizeof(ixSMU_PM_STATUS_66[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_67", REG_SMC, 0x3ff0c, &ixSMU_PM_STATUS_67[0], sizeof(ixSMU_PM_STATUS_67)/sizeof(ixSMU_PM_STATUS_67[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_68", REG_SMC, 0x3ff10, &ixSMU_PM_STATUS_68[0], sizeof(ixSMU_PM_STATUS_68)/sizeof(ixSMU_PM_STATUS_68[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_69", REG_SMC, 0x3ff14, &ixSMU_PM_STATUS_69[0], sizeof(ixSMU_PM_STATUS_69)/sizeof(ixSMU_PM_STATUS_69[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_70", REG_SMC, 0x3ff18, &ixSMU_PM_STATUS_70[0], sizeof(ixSMU_PM_STATUS_70)/sizeof(ixSMU_PM_STATUS_70[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_71", REG_SMC, 0x3ff1c, &ixSMU_PM_STATUS_71[0], sizeof(ixSMU_PM_STATUS_71)/sizeof(ixSMU_PM_STATUS_71[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_72", REG_SMC, 0x3ff20, &ixSMU_PM_STATUS_72[0], sizeof(ixSMU_PM_STATUS_72)/sizeof(ixSMU_PM_STATUS_72[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_73", REG_SMC, 0x3ff24, &ixSMU_PM_STATUS_73[0], sizeof(ixSMU_PM_STATUS_73)/sizeof(ixSMU_PM_STATUS_73[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_74", REG_SMC, 0x3ff28, &ixSMU_PM_STATUS_74[0], sizeof(ixSMU_PM_STATUS_74)/sizeof(ixSMU_PM_STATUS_74[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_75", REG_SMC, 0x3ff2c, &ixSMU_PM_STATUS_75[0], sizeof(ixSMU_PM_STATUS_75)/sizeof(ixSMU_PM_STATUS_75[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_76", REG_SMC, 0x3ff30, &ixSMU_PM_STATUS_76[0], sizeof(ixSMU_PM_STATUS_76)/sizeof(ixSMU_PM_STATUS_76[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_77", REG_SMC, 0x3ff34, &ixSMU_PM_STATUS_77[0], sizeof(ixSMU_PM_STATUS_77)/sizeof(ixSMU_PM_STATUS_77[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_78", REG_SMC, 0x3ff38, &ixSMU_PM_STATUS_78[0], sizeof(ixSMU_PM_STATUS_78)/sizeof(ixSMU_PM_STATUS_78[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_79", REG_SMC, 0x3ff3c, &ixSMU_PM_STATUS_79[0], sizeof(ixSMU_PM_STATUS_79)/sizeof(ixSMU_PM_STATUS_79[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_80", REG_SMC, 0x3ff40, &ixSMU_PM_STATUS_80[0], sizeof(ixSMU_PM_STATUS_80)/sizeof(ixSMU_PM_STATUS_80[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_81", REG_SMC, 0x3ff44, &ixSMU_PM_STATUS_81[0], sizeof(ixSMU_PM_STATUS_81)/sizeof(ixSMU_PM_STATUS_81[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_82", REG_SMC, 0x3ff48, &ixSMU_PM_STATUS_82[0], sizeof(ixSMU_PM_STATUS_82)/sizeof(ixSMU_PM_STATUS_82[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_83", REG_SMC, 0x3ff4c, &ixSMU_PM_STATUS_83[0], sizeof(ixSMU_PM_STATUS_83)/sizeof(ixSMU_PM_STATUS_83[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_84", REG_SMC, 0x3ff50, &ixSMU_PM_STATUS_84[0], sizeof(ixSMU_PM_STATUS_84)/sizeof(ixSMU_PM_STATUS_84[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_85", REG_SMC, 0x3ff54, &ixSMU_PM_STATUS_85[0], sizeof(ixSMU_PM_STATUS_85)/sizeof(ixSMU_PM_STATUS_85[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_86", REG_SMC, 0x3ff58, &ixSMU_PM_STATUS_86[0], sizeof(ixSMU_PM_STATUS_86)/sizeof(ixSMU_PM_STATUS_86[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_87", REG_SMC, 0x3ff5c, &ixSMU_PM_STATUS_87[0], sizeof(ixSMU_PM_STATUS_87)/sizeof(ixSMU_PM_STATUS_87[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_88", REG_SMC, 0x3ff60, &ixSMU_PM_STATUS_88[0], sizeof(ixSMU_PM_STATUS_88)/sizeof(ixSMU_PM_STATUS_88[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_89", REG_SMC, 0x3ff64, &ixSMU_PM_STATUS_89[0], sizeof(ixSMU_PM_STATUS_89)/sizeof(ixSMU_PM_STATUS_89[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_90", REG_SMC, 0x3ff68, &ixSMU_PM_STATUS_90[0], sizeof(ixSMU_PM_STATUS_90)/sizeof(ixSMU_PM_STATUS_90[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_91", REG_SMC, 0x3ff6c, &ixSMU_PM_STATUS_91[0], sizeof(ixSMU_PM_STATUS_91)/sizeof(ixSMU_PM_STATUS_91[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_92", REG_SMC, 0x3ff70, &ixSMU_PM_STATUS_92[0], sizeof(ixSMU_PM_STATUS_92)/sizeof(ixSMU_PM_STATUS_92[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_93", REG_SMC, 0x3ff74, &ixSMU_PM_STATUS_93[0], sizeof(ixSMU_PM_STATUS_93)/sizeof(ixSMU_PM_STATUS_93[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_94", REG_SMC, 0x3ff78, &ixSMU_PM_STATUS_94[0], sizeof(ixSMU_PM_STATUS_94)/sizeof(ixSMU_PM_STATUS_94[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_95", REG_SMC, 0x3ff7c, &ixSMU_PM_STATUS_95[0], sizeof(ixSMU_PM_STATUS_95)/sizeof(ixSMU_PM_STATUS_95[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_96", REG_SMC, 0x3ff80, &ixSMU_PM_STATUS_96[0], sizeof(ixSMU_PM_STATUS_96)/sizeof(ixSMU_PM_STATUS_96[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_97", REG_SMC, 0x3ff84, &ixSMU_PM_STATUS_97[0], sizeof(ixSMU_PM_STATUS_97)/sizeof(ixSMU_PM_STATUS_97[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_98", REG_SMC, 0x3ff88, &ixSMU_PM_STATUS_98[0], sizeof(ixSMU_PM_STATUS_98)/sizeof(ixSMU_PM_STATUS_98[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_99", REG_SMC, 0x3ff8c, &ixSMU_PM_STATUS_99[0], sizeof(ixSMU_PM_STATUS_99)/sizeof(ixSMU_PM_STATUS_99[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_100", REG_SMC, 0x3ff90, &ixSMU_PM_STATUS_100[0], sizeof(ixSMU_PM_STATUS_100)/sizeof(ixSMU_PM_STATUS_100[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_101", REG_SMC, 0x3ff94, &ixSMU_PM_STATUS_101[0], sizeof(ixSMU_PM_STATUS_101)/sizeof(ixSMU_PM_STATUS_101[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_102", REG_SMC, 0x3ff98, &ixSMU_PM_STATUS_102[0], sizeof(ixSMU_PM_STATUS_102)/sizeof(ixSMU_PM_STATUS_102[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_103", REG_SMC, 0x3ff9c, &ixSMU_PM_STATUS_103[0], sizeof(ixSMU_PM_STATUS_103)/sizeof(ixSMU_PM_STATUS_103[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_104", REG_SMC, 0x3ffa0, &ixSMU_PM_STATUS_104[0], sizeof(ixSMU_PM_STATUS_104)/sizeof(ixSMU_PM_STATUS_104[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_105", REG_SMC, 0x3ffa4, &ixSMU_PM_STATUS_105[0], sizeof(ixSMU_PM_STATUS_105)/sizeof(ixSMU_PM_STATUS_105[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_106", REG_SMC, 0x3ffa8, &ixSMU_PM_STATUS_106[0], sizeof(ixSMU_PM_STATUS_106)/sizeof(ixSMU_PM_STATUS_106[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_107", REG_SMC, 0x3ffac, &ixSMU_PM_STATUS_107[0], sizeof(ixSMU_PM_STATUS_107)/sizeof(ixSMU_PM_STATUS_107[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_108", REG_SMC, 0x3ffb0, &ixSMU_PM_STATUS_108[0], sizeof(ixSMU_PM_STATUS_108)/sizeof(ixSMU_PM_STATUS_108[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_109", REG_SMC, 0x3ffb4, &ixSMU_PM_STATUS_109[0], sizeof(ixSMU_PM_STATUS_109)/sizeof(ixSMU_PM_STATUS_109[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_110", REG_SMC, 0x3ffb8, &ixSMU_PM_STATUS_110[0], sizeof(ixSMU_PM_STATUS_110)/sizeof(ixSMU_PM_STATUS_110[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_111", REG_SMC, 0x3ffbc, &ixSMU_PM_STATUS_111[0], sizeof(ixSMU_PM_STATUS_111)/sizeof(ixSMU_PM_STATUS_111[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_112", REG_SMC, 0x3ffc0, &ixSMU_PM_STATUS_112[0], sizeof(ixSMU_PM_STATUS_112)/sizeof(ixSMU_PM_STATUS_112[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_113", REG_SMC, 0x3ffc4, &ixSMU_PM_STATUS_113[0], sizeof(ixSMU_PM_STATUS_113)/sizeof(ixSMU_PM_STATUS_113[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_114", REG_SMC, 0x3ffc8, &ixSMU_PM_STATUS_114[0], sizeof(ixSMU_PM_STATUS_114)/sizeof(ixSMU_PM_STATUS_114[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_115", REG_SMC, 0x3ffcc, &ixSMU_PM_STATUS_115[0], sizeof(ixSMU_PM_STATUS_115)/sizeof(ixSMU_PM_STATUS_115[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_116", REG_SMC, 0x3ffd0, &ixSMU_PM_STATUS_116[0], sizeof(ixSMU_PM_STATUS_116)/sizeof(ixSMU_PM_STATUS_116[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_117", REG_SMC, 0x3ffd4, &ixSMU_PM_STATUS_117[0], sizeof(ixSMU_PM_STATUS_117)/sizeof(ixSMU_PM_STATUS_117[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_118", REG_SMC, 0x3ffd8, &ixSMU_PM_STATUS_118[0], sizeof(ixSMU_PM_STATUS_118)/sizeof(ixSMU_PM_STATUS_118[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_119", REG_SMC, 0x3ffdc, &ixSMU_PM_STATUS_119[0], sizeof(ixSMU_PM_STATUS_119)/sizeof(ixSMU_PM_STATUS_119[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_120", REG_SMC, 0x3ffe0, &ixSMU_PM_STATUS_120[0], sizeof(ixSMU_PM_STATUS_120)/sizeof(ixSMU_PM_STATUS_120[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_121", REG_SMC, 0x3ffe4, &ixSMU_PM_STATUS_121[0], sizeof(ixSMU_PM_STATUS_121)/sizeof(ixSMU_PM_STATUS_121[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_122", REG_SMC, 0x3ffe8, &ixSMU_PM_STATUS_122[0], sizeof(ixSMU_PM_STATUS_122)/sizeof(ixSMU_PM_STATUS_122[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_123", REG_SMC, 0x3ffec, &ixSMU_PM_STATUS_123[0], sizeof(ixSMU_PM_STATUS_123)/sizeof(ixSMU_PM_STATUS_123[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_124", REG_SMC, 0x3fff0, &ixSMU_PM_STATUS_124[0], sizeof(ixSMU_PM_STATUS_124)/sizeof(ixSMU_PM_STATUS_124[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_125", REG_SMC, 0x3fff4, &ixSMU_PM_STATUS_125[0], sizeof(ixSMU_PM_STATUS_125)/sizeof(ixSMU_PM_STATUS_125[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_126", REG_SMC, 0x3fff8, &ixSMU_PM_STATUS_126[0], sizeof(ixSMU_PM_STATUS_126)/sizeof(ixSMU_PM_STATUS_126[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_127", REG_SMC, 0x3fffc, &ixSMU_PM_STATUS_127[0], sizeof(ixSMU_PM_STATUS_127)/sizeof(ixSMU_PM_STATUS_127[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_INDEX", REG_MMIO, 0x80, &mmGCK_SMC_IND_INDEX[0], sizeof(mmGCK_SMC_IND_INDEX)/sizeof(mmGCK_SMC_IND_INDEX[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_0", REG_MMIO, 0x80, &mmSMC_IND_INDEX_0[0], sizeof(mmSMC_IND_INDEX_0)/sizeof(mmSMC_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX", REG_MMIO, 0x80, &mmSMC_IND_INDEX[0], sizeof(mmSMC_IND_INDEX)/sizeof(mmSMC_IND_INDEX[0]), 0, 0 },
+	{ "ixSMC_SYSCON_RESET_CNTL", REG_SMC, 0x80000000, &ixSMC_SYSCON_RESET_CNTL[0], sizeof(ixSMC_SYSCON_RESET_CNTL)/sizeof(ixSMC_SYSCON_RESET_CNTL[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_0", REG_SMC, 0x80000004, &ixSMC_SYSCON_CLOCK_CNTL_0[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_0)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_0[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_1", REG_SMC, 0x80000008, &ixSMC_SYSCON_CLOCK_CNTL_1[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_1)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_1[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_2", REG_SMC, 0x8000000c, &ixSMC_SYSCON_CLOCK_CNTL_2[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_2)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_2[0]), 0, 0 },
+	{ "ixSMC_SYSCON_MISC_CNTL", REG_SMC, 0x80000010, &ixSMC_SYSCON_MISC_CNTL[0], sizeof(ixSMC_SYSCON_MISC_CNTL)/sizeof(ixSMC_SYSCON_MISC_CNTL[0]), 0, 0 },
+	{ "ixSMC_SYSCON_MSG_ARG_0", REG_SMC, 0x80000068, &ixSMC_SYSCON_MSG_ARG_0[0], sizeof(ixSMC_SYSCON_MSG_ARG_0)/sizeof(ixSMC_SYSCON_MSG_ARG_0[0]), 0, 0 },
+	{ "ixSMC_PC_C", REG_SMC, 0x80000370, &ixSMC_PC_C[0], sizeof(ixSMC_PC_C)/sizeof(ixSMC_PC_C[0]), 0, 0 },
+	{ "ixSMC_SCRATCH9", REG_SMC, 0x80000424, &ixSMC_SCRATCH9[0], sizeof(ixSMC_SCRATCH9)/sizeof(ixSMC_SCRATCH9[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_DATA", REG_MMIO, 0x81, &mmGCK_SMC_IND_DATA[0], sizeof(mmGCK_SMC_IND_DATA)/sizeof(mmGCK_SMC_IND_DATA[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_0", REG_MMIO, 0x81, &mmSMC_IND_DATA_0[0], sizeof(mmSMC_IND_DATA_0)/sizeof(mmSMC_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMC_IND_DATA", REG_MMIO, 0x81, &mmSMC_IND_DATA[0], sizeof(mmSMC_IND_DATA)/sizeof(mmSMC_IND_DATA[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_1", REG_MMIO, 0x82, &mmSMC_IND_INDEX_1[0], sizeof(mmSMC_IND_INDEX_1)/sizeof(mmSMC_IND_INDEX_1[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_1", REG_MMIO, 0x83, &mmSMC_IND_DATA_1[0], sizeof(mmSMC_IND_DATA_1)/sizeof(mmSMC_IND_DATA_1[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_2", REG_MMIO, 0x84, &mmSMC_IND_INDEX_2[0], sizeof(mmSMC_IND_INDEX_2)/sizeof(mmSMC_IND_INDEX_2[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_2", REG_MMIO, 0x85, &mmSMC_IND_DATA_2[0], sizeof(mmSMC_IND_DATA_2)/sizeof(mmSMC_IND_DATA_2[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_3", REG_MMIO, 0x86, &mmSMC_IND_INDEX_3[0], sizeof(mmSMC_IND_INDEX_3)/sizeof(mmSMC_IND_INDEX_3[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_3", REG_MMIO, 0x87, &mmSMC_IND_DATA_3[0], sizeof(mmSMC_IND_DATA_3)/sizeof(mmSMC_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_4", REG_MMIO, 0x88, &mmSMC_IND_INDEX_4[0], sizeof(mmSMC_IND_INDEX_4)/sizeof(mmSMC_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_4", REG_MMIO, 0x89, &mmSMC_IND_DATA_4[0], sizeof(mmSMC_IND_DATA_4)/sizeof(mmSMC_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_5", REG_MMIO, 0x8a, &mmSMC_IND_INDEX_5[0], sizeof(mmSMC_IND_INDEX_5)/sizeof(mmSMC_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_5", REG_MMIO, 0x8b, &mmSMC_IND_DATA_5[0], sizeof(mmSMC_IND_DATA_5)/sizeof(mmSMC_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_6", REG_MMIO, 0x8c, &mmSMC_IND_INDEX_6[0], sizeof(mmSMC_IND_INDEX_6)/sizeof(mmSMC_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_6", REG_MMIO, 0x8d, &mmSMC_IND_DATA_6[0], sizeof(mmSMC_IND_DATA_6)/sizeof(mmSMC_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_7", REG_MMIO, 0x8e, &mmSMC_IND_INDEX_7[0], sizeof(mmSMC_IND_INDEX_7)/sizeof(mmSMC_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_7", REG_MMIO, 0x8f, &mmSMC_IND_DATA_7[0], sizeof(mmSMC_IND_DATA_7)/sizeof(mmSMC_IND_DATA_7[0]), 0, 0 },
+	{ "mmSMC_IND_ACCESS_CNTL", REG_MMIO, 0x92, &mmSMC_IND_ACCESS_CNTL[0], sizeof(mmSMC_IND_ACCESS_CNTL)/sizeof(mmSMC_IND_ACCESS_CNTL[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_11", REG_MMIO, 0x93, &mmSMC_MSG_ARG_11[0], sizeof(mmSMC_MSG_ARG_11)/sizeof(mmSMC_MSG_ARG_11[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_0", REG_MMIO, 0x94, &mmSMC_MESSAGE_0[0], sizeof(mmSMC_MESSAGE_0)/sizeof(mmSMC_MESSAGE_0[0]), 0, 0 },
+	{ "mmSMC_RESP_0", REG_MMIO, 0x95, &mmSMC_RESP_0[0], sizeof(mmSMC_RESP_0)/sizeof(mmSMC_RESP_0[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_1", REG_MMIO, 0x96, &mmSMC_MESSAGE_1[0], sizeof(mmSMC_MESSAGE_1)/sizeof(mmSMC_MESSAGE_1[0]), 0, 0 },
+	{ "mmSMC_RESP_1", REG_MMIO, 0x97, &mmSMC_RESP_1[0], sizeof(mmSMC_RESP_1)/sizeof(mmSMC_RESP_1[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_2", REG_MMIO, 0x98, &mmSMC_MESSAGE_2[0], sizeof(mmSMC_MESSAGE_2)/sizeof(mmSMC_MESSAGE_2[0]), 0, 0 },
+	{ "mmSMC_RESP_2", REG_MMIO, 0x99, &mmSMC_RESP_2[0], sizeof(mmSMC_RESP_2)/sizeof(mmSMC_RESP_2[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_3", REG_MMIO, 0x9a, &mmSMC_MESSAGE_3[0], sizeof(mmSMC_MESSAGE_3)/sizeof(mmSMC_MESSAGE_3[0]), 0, 0 },
+	{ "mmSMC_RESP_3", REG_MMIO, 0x9b, &mmSMC_RESP_3[0], sizeof(mmSMC_RESP_3)/sizeof(mmSMC_RESP_3[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_4", REG_MMIO, 0x9c, &mmSMC_MESSAGE_4[0], sizeof(mmSMC_MESSAGE_4)/sizeof(mmSMC_MESSAGE_4[0]), 0, 0 },
+	{ "mmSMC_RESP_4", REG_MMIO, 0x9d, &mmSMC_RESP_4[0], sizeof(mmSMC_RESP_4)/sizeof(mmSMC_RESP_4[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_5", REG_MMIO, 0x9e, &mmSMC_MESSAGE_5[0], sizeof(mmSMC_MESSAGE_5)/sizeof(mmSMC_MESSAGE_5[0]), 0, 0 },
+	{ "mmSMC_RESP_5", REG_MMIO, 0x9f, &mmSMC_RESP_5[0], sizeof(mmSMC_RESP_5)/sizeof(mmSMC_RESP_5[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_6", REG_MMIO, 0xa0, &mmSMC_MESSAGE_6[0], sizeof(mmSMC_MESSAGE_6)/sizeof(mmSMC_MESSAGE_6[0]), 0, 0 },
+	{ "mmSMC_RESP_6", REG_MMIO, 0xa1, &mmSMC_RESP_6[0], sizeof(mmSMC_RESP_6)/sizeof(mmSMC_RESP_6[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_7", REG_MMIO, 0xa2, &mmSMC_MESSAGE_7[0], sizeof(mmSMC_MESSAGE_7)/sizeof(mmSMC_MESSAGE_7[0]), 0, 0 },
+	{ "mmSMC_RESP_7", REG_MMIO, 0xa3, &mmSMC_RESP_7[0], sizeof(mmSMC_RESP_7)/sizeof(mmSMC_RESP_7[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_0", REG_MMIO, 0xa4, &mmSMC_MSG_ARG_0[0], sizeof(mmSMC_MSG_ARG_0)/sizeof(mmSMC_MSG_ARG_0[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_1", REG_MMIO, 0xa5, &mmSMC_MSG_ARG_1[0], sizeof(mmSMC_MSG_ARG_1)/sizeof(mmSMC_MSG_ARG_1[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_2", REG_MMIO, 0xa6, &mmSMC_MSG_ARG_2[0], sizeof(mmSMC_MSG_ARG_2)/sizeof(mmSMC_MSG_ARG_2[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_3", REG_MMIO, 0xa7, &mmSMC_MSG_ARG_3[0], sizeof(mmSMC_MSG_ARG_3)/sizeof(mmSMC_MSG_ARG_3[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_4", REG_MMIO, 0xa8, &mmSMC_MSG_ARG_4[0], sizeof(mmSMC_MSG_ARG_4)/sizeof(mmSMC_MSG_ARG_4[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_5", REG_MMIO, 0xa9, &mmSMC_MSG_ARG_5[0], sizeof(mmSMC_MSG_ARG_5)/sizeof(mmSMC_MSG_ARG_5[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_6", REG_MMIO, 0xaa, &mmSMC_MSG_ARG_6[0], sizeof(mmSMC_MSG_ARG_6)/sizeof(mmSMC_MSG_ARG_6[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_7", REG_MMIO, 0xab, &mmSMC_MSG_ARG_7[0], sizeof(mmSMC_MSG_ARG_7)/sizeof(mmSMC_MSG_ARG_7[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_8", REG_MMIO, 0xb5, &mmSMC_MESSAGE_8[0], sizeof(mmSMC_MESSAGE_8)/sizeof(mmSMC_MESSAGE_8[0]), 0, 0 },
+	{ "mmSMC_RESP_8", REG_MMIO, 0xb6, &mmSMC_RESP_8[0], sizeof(mmSMC_RESP_8)/sizeof(mmSMC_RESP_8[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_9", REG_MMIO, 0xb7, &mmSMC_MESSAGE_9[0], sizeof(mmSMC_MESSAGE_9)/sizeof(mmSMC_MESSAGE_9[0]), 0, 0 },
+	{ "mmSMC_RESP_9", REG_MMIO, 0xb8, &mmSMC_RESP_9[0], sizeof(mmSMC_RESP_9)/sizeof(mmSMC_RESP_9[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_10", REG_MMIO, 0xb9, &mmSMC_MESSAGE_10[0], sizeof(mmSMC_MESSAGE_10)/sizeof(mmSMC_MESSAGE_10[0]), 0, 0 },
+	{ "mmSMC_RESP_10", REG_MMIO, 0xba, &mmSMC_RESP_10[0], sizeof(mmSMC_RESP_10)/sizeof(mmSMC_RESP_10[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_11", REG_MMIO, 0xbb, &mmSMC_MESSAGE_11[0], sizeof(mmSMC_MESSAGE_11)/sizeof(mmSMC_MESSAGE_11[0]), 0, 0 },
+	{ "mmSMC_RESP_11", REG_MMIO, 0xbc, &mmSMC_RESP_11[0], sizeof(mmSMC_RESP_11)/sizeof(mmSMC_RESP_11[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_8", REG_MMIO, 0xbd, &mmSMC_MSG_ARG_8[0], sizeof(mmSMC_MSG_ARG_8)/sizeof(mmSMC_MSG_ARG_8[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_9", REG_MMIO, 0xbe, &mmSMC_MSG_ARG_9[0], sizeof(mmSMC_MSG_ARG_9)/sizeof(mmSMC_MSG_ARG_9[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_10", REG_MMIO, 0xbf, &mmSMC_MSG_ARG_10[0], sizeof(mmSMC_MSG_ARG_10)/sizeof(mmSMC_MSG_ARG_10[0]), 0, 0 },
+	{ "ixRCU_UC_EVENTS", REG_SMC, 0xc0000004, &ixRCU_UC_EVENTS[0], sizeof(ixRCU_UC_EVENTS)/sizeof(ixRCU_UC_EVENTS[0]), 0, 0 },
+	{ "ixRCU_MISC_CTRL", REG_SMC, 0xc0000010, &ixRCU_MISC_CTRL[0], sizeof(ixRCU_MISC_CTRL)/sizeof(ixRCU_MISC_CTRL[0]), 0, 0 },
+	{ "ixRCU_VIRT_RESET_REQ", REG_SMC, 0xc0000024, &ixRCU_VIRT_RESET_REQ[0], sizeof(ixRCU_VIRT_RESET_REQ)/sizeof(ixRCU_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "ixCC_RCU_FUSES", REG_SMC, 0xc00c0000, &ixCC_RCU_FUSES[0], sizeof(ixCC_RCU_FUSES)/sizeof(ixCC_RCU_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_MISC_FUSES", REG_SMC, 0xc00c0004, &ixCC_SMU_MISC_FUSES[0], sizeof(ixCC_SMU_MISC_FUSES)/sizeof(ixCC_SMU_MISC_FUSES[0]), 0, 0 },
+	{ "ixCC_SCLK_VID_FUSES", REG_SMC, 0xc00c0008, &ixCC_SCLK_VID_FUSES[0], sizeof(ixCC_SCLK_VID_FUSES)/sizeof(ixCC_SCLK_VID_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOCCFG_FUSES", REG_SMC, 0xc00c000c, &ixCC_GIO_IOCCFG_FUSES[0], sizeof(ixCC_GIO_IOCCFG_FUSES)/sizeof(ixCC_GIO_IOCCFG_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOC_FUSES", REG_SMC, 0xc00c0010, &ixCC_GIO_IOC_FUSES[0], sizeof(ixCC_GIO_IOC_FUSES)/sizeof(ixCC_GIO_IOC_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_TST_EFUSE1_MISC", REG_SMC, 0xc00c001c, &ixCC_SMU_TST_EFUSE1_MISC[0], sizeof(ixCC_SMU_TST_EFUSE1_MISC)/sizeof(ixCC_SMU_TST_EFUSE1_MISC[0]), 0, 0 },
+	{ "ixCC_TST_ID_STRAPS", REG_SMC, 0xc00c0020, &ixCC_TST_ID_STRAPS[0], sizeof(ixCC_TST_ID_STRAPS)/sizeof(ixCC_TST_ID_STRAPS[0]), 0, 0 },
+	{ "ixCC_FCTRL_FUSES", REG_SMC, 0xc00c0024, &ixCC_FCTRL_FUSES[0], sizeof(ixCC_FCTRL_FUSES)/sizeof(ixCC_FCTRL_FUSES[0]), 0, 0 },
+	{ "ixCC_HARVEST_FUSES", REG_SMC, 0xc00c0028, &ixCC_HARVEST_FUSES[0], sizeof(ixCC_HARVEST_FUSES)/sizeof(ixCC_HARVEST_FUSES[0]), 0, 0 },
+	{ "ixSMU_EFUSE_0", REG_SMC, 0xc0100000, &ixSMU_EFUSE_0[0], sizeof(ixSMU_EFUSE_0)/sizeof(ixSMU_EFUSE_0[0]), 0, 0 },
+	{ "ixGENERAL_PWRMGT", REG_SMC, 0xc0200000, &ixGENERAL_PWRMGT[0], sizeof(ixGENERAL_PWRMGT)/sizeof(ixGENERAL_PWRMGT[0]), 0, 0 },
+	{ "ixCNB_PWRMGT_CNTL", REG_SMC, 0xc0200004, &ixCNB_PWRMGT_CNTL[0], sizeof(ixCNB_PWRMGT_CNTL)/sizeof(ixCNB_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixSCLK_PWRMGT_CNTL", REG_SMC, 0xc0200008, &ixSCLK_PWRMGT_CNTL[0], sizeof(ixSCLK_PWRMGT_CNTL)/sizeof(ixSCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX", REG_SMC, 0xc0200014, &ixTARGET_AND_CURRENT_PROFILE_INDEX[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX[0]), 0, 0 },
+	{ "ixPWR_PCC_CONTROL", REG_SMC, 0xc0200018, &ixPWR_PCC_CONTROL[0], sizeof(ixPWR_PCC_CONTROL)/sizeof(ixPWR_PCC_CONTROL[0]), 0, 0 },
+	{ "ixPWR_PCC_GPIO_SELECT", REG_SMC, 0xc020001c, &ixPWR_PCC_GPIO_SELECT[0], sizeof(ixPWR_PCC_GPIO_SELECT)/sizeof(ixPWR_PCC_GPIO_SELECT[0]), 0, 0 },
+	{ "ixPLL_TEST_CNTL", REG_SMC, 0xc020003c, &ixPLL_TEST_CNTL[0], sizeof(ixPLL_TEST_CNTL)/sizeof(ixPLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixCG_STATIC_SCREEN_PARAMETER", REG_SMC, 0xc0200044, &ixCG_STATIC_SCREEN_PARAMETER[0], sizeof(ixCG_STATIC_SCREEN_PARAMETER)/sizeof(ixCG_STATIC_SCREEN_PARAMETER[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL", REG_SMC, 0xc0200060, &ixCG_DISPLAY_GAP_CNTL[0], sizeof(ixCG_DISPLAY_GAP_CNTL)/sizeof(ixCG_DISPLAY_GAP_CNTL[0]), 0, 0 },
+	{ "ixCG_ACPI_CNTL", REG_SMC, 0xc0200064, &ixCG_ACPI_CNTL[0], sizeof(ixCG_ACPI_CNTL)/sizeof(ixCG_ACPI_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc0200080, &ixSCLK_DEEP_SLEEP_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200084, &ixSCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL2)/sizeof(ixSCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_MISC_CNTL", REG_SMC, 0xc0200088, &ixSCLK_DEEP_SLEEP_MISC_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc020008c, &ixLCLK_DEEP_SLEEP_CNTL[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL)/sizeof(ixLCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL3", REG_SMC, 0xc020009c, &ixSCLK_DEEP_SLEEP_CNTL3[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL3)/sizeof(ixSCLK_DEEP_SLEEP_CNTL3[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_1", REG_SMC, 0xc02000f0, &ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0]), 0, 0 },
+	{ "ixCG_ULV_PARAMETER", REG_SMC, 0xc020015c, &ixCG_ULV_PARAMETER[0], sizeof(ixCG_ULV_PARAMETER)/sizeof(ixCG_ULV_PARAMETER[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_0", REG_SMC, 0xc02001a8, &ixCG_FREQ_TRAN_VOTING_0[0], sizeof(ixCG_FREQ_TRAN_VOTING_0)/sizeof(ixCG_FREQ_TRAN_VOTING_0[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_1", REG_SMC, 0xc02001ac, &ixCG_FREQ_TRAN_VOTING_1[0], sizeof(ixCG_FREQ_TRAN_VOTING_1)/sizeof(ixCG_FREQ_TRAN_VOTING_1[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_2", REG_SMC, 0xc02001b0, &ixCG_FREQ_TRAN_VOTING_2[0], sizeof(ixCG_FREQ_TRAN_VOTING_2)/sizeof(ixCG_FREQ_TRAN_VOTING_2[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_3", REG_SMC, 0xc02001b4, &ixCG_FREQ_TRAN_VOTING_3[0], sizeof(ixCG_FREQ_TRAN_VOTING_3)/sizeof(ixCG_FREQ_TRAN_VOTING_3[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_4", REG_SMC, 0xc02001b8, &ixCG_FREQ_TRAN_VOTING_4[0], sizeof(ixCG_FREQ_TRAN_VOTING_4)/sizeof(ixCG_FREQ_TRAN_VOTING_4[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_5", REG_SMC, 0xc02001bc, &ixCG_FREQ_TRAN_VOTING_5[0], sizeof(ixCG_FREQ_TRAN_VOTING_5)/sizeof(ixCG_FREQ_TRAN_VOTING_5[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, &ixCG_DISPLAY_GAP_CNTL2[0], sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixPWR_CKS_ENABLE", REG_SMC, 0xc020034c, &ixPWR_CKS_ENABLE[0], sizeof(ixPWR_CKS_ENABLE)/sizeof(ixPWR_CKS_ENABLE[0]), 0, 0 },
+	{ "ixPWR_CKS_CNTL", REG_SMC, 0xc0200350, &ixPWR_CKS_CNTL[0], sizeof(ixPWR_CKS_CNTL)/sizeof(ixPWR_CKS_CNTL[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_PARAMETER", REG_SMC, 0xc020036c, &ixVDDGFX_IDLE_PARAMETER[0], sizeof(ixVDDGFX_IDLE_PARAMETER)/sizeof(ixVDDGFX_IDLE_PARAMETER[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_CONTROL", REG_SMC, 0xc0200370, &ixVDDGFX_IDLE_CONTROL[0], sizeof(ixVDDGFX_IDLE_CONTROL)/sizeof(ixVDDGFX_IDLE_CONTROL[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_EXIT", REG_SMC, 0xc0200374, &ixVDDGFX_IDLE_EXIT[0], sizeof(ixVDDGFX_IDLE_EXIT)/sizeof(ixVDDGFX_IDLE_EXIT[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_CONTROL2", REG_SMC, 0xc0200378, &ixPWR_DISP_TIMER_CONTROL2[0], sizeof(ixPWR_DISP_TIMER_CONTROL2)/sizeof(ixPWR_DISP_TIMER_CONTROL2[0]), 0, 0 },
+	{ "ixSCLK_MIN_DIV", REG_SMC, 0xc02003ac, &ixSCLK_MIN_DIV[0], sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_CONTROL", REG_SMC, 0xc02003c0, &ixPWR_DISP_TIMER_CONTROL[0], sizeof(ixPWR_DISP_TIMER_CONTROL)/sizeof(ixPWR_DISP_TIMER_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_DEBUG", REG_SMC, 0xc02003c4, &ixPWR_DISP_TIMER_DEBUG[0], sizeof(ixPWR_DISP_TIMER_DEBUG)/sizeof(ixPWR_DISP_TIMER_DEBUG[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER2_CONTROL", REG_SMC, 0xc02003c8, &ixPWR_DISP_TIMER2_CONTROL[0], sizeof(ixPWR_DISP_TIMER2_CONTROL)/sizeof(ixPWR_DISP_TIMER2_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER2_DEBUG", REG_SMC, 0xc02003cc, &ixPWR_DISP_TIMER2_DEBUG[0], sizeof(ixPWR_DISP_TIMER2_DEBUG)/sizeof(ixPWR_DISP_TIMER2_DEBUG[0]), 0, 0 },
+	{ "ixCG_THERMAL_CTRL", REG_SMC, 0xc0300004, &ixCG_THERMAL_CTRL[0], sizeof(ixCG_THERMAL_CTRL)/sizeof(ixCG_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_STATUS", REG_SMC, 0xc0300008, &ixCG_THERMAL_STATUS[0], sizeof(ixCG_THERMAL_STATUS)/sizeof(ixCG_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT", REG_SMC, 0xc030000c, &ixCG_THERMAL_INT[0], sizeof(ixCG_THERMAL_INT)/sizeof(ixCG_THERMAL_INT[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_CTRL", REG_SMC, 0xc0300010, &ixCG_MULT_THERMAL_CTRL[0], sizeof(ixCG_MULT_THERMAL_CTRL)/sizeof(ixCG_MULT_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_STATUS", REG_SMC, 0xc0300014, &ixCG_MULT_THERMAL_STATUS[0], sizeof(ixCG_MULT_THERMAL_STATUS)/sizeof(ixCG_MULT_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL0", REG_SMC, 0xc0300064, &ixCG_FDO_CTRL0[0], sizeof(ixCG_FDO_CTRL0)/sizeof(ixCG_FDO_CTRL0[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL1", REG_SMC, 0xc0300068, &ixCG_FDO_CTRL1[0], sizeof(ixCG_FDO_CTRL1)/sizeof(ixCG_FDO_CTRL1[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL2", REG_SMC, 0xc030006c, &ixCG_FDO_CTRL2[0], sizeof(ixCG_FDO_CTRL2)/sizeof(ixCG_FDO_CTRL2[0]), 0, 0 },
+	{ "ixCG_TACH_CTRL", REG_SMC, 0xc0300070, &ixCG_TACH_CTRL[0], sizeof(ixCG_TACH_CTRL)/sizeof(ixCG_TACH_CTRL[0]), 0, 0 },
+	{ "ixCG_TACH_STATUS", REG_SMC, 0xc0300074, &ixCG_TACH_STATUS[0], sizeof(ixCG_TACH_STATUS)/sizeof(ixCG_TACH_STATUS[0]), 0, 0 },
+	{ "ixCC_THM_STRAPS0", REG_SMC, 0xc0300080, &ixCC_THM_STRAPS0[0], sizeof(ixCC_THM_STRAPS0)/sizeof(ixCC_THM_STRAPS0[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL0_DATA", REG_SMC, 0xc0300100, &ixTHM_TMON0_RDIL0_DATA[0], sizeof(ixTHM_TMON0_RDIL0_DATA)/sizeof(ixTHM_TMON0_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL1_DATA", REG_SMC, 0xc0300104, &ixTHM_TMON0_RDIL1_DATA[0], sizeof(ixTHM_TMON0_RDIL1_DATA)/sizeof(ixTHM_TMON0_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL2_DATA", REG_SMC, 0xc0300108, &ixTHM_TMON0_RDIL2_DATA[0], sizeof(ixTHM_TMON0_RDIL2_DATA)/sizeof(ixTHM_TMON0_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL3_DATA", REG_SMC, 0xc030010c, &ixTHM_TMON0_RDIL3_DATA[0], sizeof(ixTHM_TMON0_RDIL3_DATA)/sizeof(ixTHM_TMON0_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL4_DATA", REG_SMC, 0xc0300110, &ixTHM_TMON0_RDIL4_DATA[0], sizeof(ixTHM_TMON0_RDIL4_DATA)/sizeof(ixTHM_TMON0_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL5_DATA", REG_SMC, 0xc0300114, &ixTHM_TMON0_RDIL5_DATA[0], sizeof(ixTHM_TMON0_RDIL5_DATA)/sizeof(ixTHM_TMON0_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL6_DATA", REG_SMC, 0xc0300118, &ixTHM_TMON0_RDIL6_DATA[0], sizeof(ixTHM_TMON0_RDIL6_DATA)/sizeof(ixTHM_TMON0_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL7_DATA", REG_SMC, 0xc030011c, &ixTHM_TMON0_RDIL7_DATA[0], sizeof(ixTHM_TMON0_RDIL7_DATA)/sizeof(ixTHM_TMON0_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL8_DATA", REG_SMC, 0xc0300120, &ixTHM_TMON0_RDIL8_DATA[0], sizeof(ixTHM_TMON0_RDIL8_DATA)/sizeof(ixTHM_TMON0_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL9_DATA", REG_SMC, 0xc0300124, &ixTHM_TMON0_RDIL9_DATA[0], sizeof(ixTHM_TMON0_RDIL9_DATA)/sizeof(ixTHM_TMON0_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL10_DATA", REG_SMC, 0xc0300128, &ixTHM_TMON0_RDIL10_DATA[0], sizeof(ixTHM_TMON0_RDIL10_DATA)/sizeof(ixTHM_TMON0_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL11_DATA", REG_SMC, 0xc030012c, &ixTHM_TMON0_RDIL11_DATA[0], sizeof(ixTHM_TMON0_RDIL11_DATA)/sizeof(ixTHM_TMON0_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL12_DATA", REG_SMC, 0xc0300130, &ixTHM_TMON0_RDIL12_DATA[0], sizeof(ixTHM_TMON0_RDIL12_DATA)/sizeof(ixTHM_TMON0_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL13_DATA", REG_SMC, 0xc0300134, &ixTHM_TMON0_RDIL13_DATA[0], sizeof(ixTHM_TMON0_RDIL13_DATA)/sizeof(ixTHM_TMON0_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL14_DATA", REG_SMC, 0xc0300138, &ixTHM_TMON0_RDIL14_DATA[0], sizeof(ixTHM_TMON0_RDIL14_DATA)/sizeof(ixTHM_TMON0_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL15_DATA", REG_SMC, 0xc030013c, &ixTHM_TMON0_RDIL15_DATA[0], sizeof(ixTHM_TMON0_RDIL15_DATA)/sizeof(ixTHM_TMON0_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR0_DATA", REG_SMC, 0xc0300140, &ixTHM_TMON0_RDIR0_DATA[0], sizeof(ixTHM_TMON0_RDIR0_DATA)/sizeof(ixTHM_TMON0_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR1_DATA", REG_SMC, 0xc0300144, &ixTHM_TMON0_RDIR1_DATA[0], sizeof(ixTHM_TMON0_RDIR1_DATA)/sizeof(ixTHM_TMON0_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR2_DATA", REG_SMC, 0xc0300148, &ixTHM_TMON0_RDIR2_DATA[0], sizeof(ixTHM_TMON0_RDIR2_DATA)/sizeof(ixTHM_TMON0_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR3_DATA", REG_SMC, 0xc030014c, &ixTHM_TMON0_RDIR3_DATA[0], sizeof(ixTHM_TMON0_RDIR3_DATA)/sizeof(ixTHM_TMON0_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR4_DATA", REG_SMC, 0xc0300150, &ixTHM_TMON0_RDIR4_DATA[0], sizeof(ixTHM_TMON0_RDIR4_DATA)/sizeof(ixTHM_TMON0_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR5_DATA", REG_SMC, 0xc0300154, &ixTHM_TMON0_RDIR5_DATA[0], sizeof(ixTHM_TMON0_RDIR5_DATA)/sizeof(ixTHM_TMON0_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR6_DATA", REG_SMC, 0xc0300158, &ixTHM_TMON0_RDIR6_DATA[0], sizeof(ixTHM_TMON0_RDIR6_DATA)/sizeof(ixTHM_TMON0_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR7_DATA", REG_SMC, 0xc030015c, &ixTHM_TMON0_RDIR7_DATA[0], sizeof(ixTHM_TMON0_RDIR7_DATA)/sizeof(ixTHM_TMON0_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR8_DATA", REG_SMC, 0xc0300160, &ixTHM_TMON0_RDIR8_DATA[0], sizeof(ixTHM_TMON0_RDIR8_DATA)/sizeof(ixTHM_TMON0_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR9_DATA", REG_SMC, 0xc0300164, &ixTHM_TMON0_RDIR9_DATA[0], sizeof(ixTHM_TMON0_RDIR9_DATA)/sizeof(ixTHM_TMON0_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR10_DATA", REG_SMC, 0xc0300168, &ixTHM_TMON0_RDIR10_DATA[0], sizeof(ixTHM_TMON0_RDIR10_DATA)/sizeof(ixTHM_TMON0_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR11_DATA", REG_SMC, 0xc030016c, &ixTHM_TMON0_RDIR11_DATA[0], sizeof(ixTHM_TMON0_RDIR11_DATA)/sizeof(ixTHM_TMON0_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR12_DATA", REG_SMC, 0xc0300170, &ixTHM_TMON0_RDIR12_DATA[0], sizeof(ixTHM_TMON0_RDIR12_DATA)/sizeof(ixTHM_TMON0_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR13_DATA", REG_SMC, 0xc0300174, &ixTHM_TMON0_RDIR13_DATA[0], sizeof(ixTHM_TMON0_RDIR13_DATA)/sizeof(ixTHM_TMON0_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR14_DATA", REG_SMC, 0xc0300178, &ixTHM_TMON0_RDIR14_DATA[0], sizeof(ixTHM_TMON0_RDIR14_DATA)/sizeof(ixTHM_TMON0_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR15_DATA", REG_SMC, 0xc030017c, &ixTHM_TMON0_RDIR15_DATA[0], sizeof(ixTHM_TMON0_RDIR15_DATA)/sizeof(ixTHM_TMON0_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL0_DATA", REG_SMC, 0xc0300180, &ixTHM_TMON1_RDIL0_DATA[0], sizeof(ixTHM_TMON1_RDIL0_DATA)/sizeof(ixTHM_TMON1_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL1_DATA", REG_SMC, 0xc0300184, &ixTHM_TMON1_RDIL1_DATA[0], sizeof(ixTHM_TMON1_RDIL1_DATA)/sizeof(ixTHM_TMON1_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL2_DATA", REG_SMC, 0xc0300188, &ixTHM_TMON1_RDIL2_DATA[0], sizeof(ixTHM_TMON1_RDIL2_DATA)/sizeof(ixTHM_TMON1_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL3_DATA", REG_SMC, 0xc030018c, &ixTHM_TMON1_RDIL3_DATA[0], sizeof(ixTHM_TMON1_RDIL3_DATA)/sizeof(ixTHM_TMON1_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL4_DATA", REG_SMC, 0xc0300190, &ixTHM_TMON1_RDIL4_DATA[0], sizeof(ixTHM_TMON1_RDIL4_DATA)/sizeof(ixTHM_TMON1_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL5_DATA", REG_SMC, 0xc0300194, &ixTHM_TMON1_RDIL5_DATA[0], sizeof(ixTHM_TMON1_RDIL5_DATA)/sizeof(ixTHM_TMON1_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL6_DATA", REG_SMC, 0xc0300198, &ixTHM_TMON1_RDIL6_DATA[0], sizeof(ixTHM_TMON1_RDIL6_DATA)/sizeof(ixTHM_TMON1_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL7_DATA", REG_SMC, 0xc030019c, &ixTHM_TMON1_RDIL7_DATA[0], sizeof(ixTHM_TMON1_RDIL7_DATA)/sizeof(ixTHM_TMON1_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL8_DATA", REG_SMC, 0xc03001a0, &ixTHM_TMON1_RDIL8_DATA[0], sizeof(ixTHM_TMON1_RDIL8_DATA)/sizeof(ixTHM_TMON1_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL9_DATA", REG_SMC, 0xc03001a4, &ixTHM_TMON1_RDIL9_DATA[0], sizeof(ixTHM_TMON1_RDIL9_DATA)/sizeof(ixTHM_TMON1_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL10_DATA", REG_SMC, 0xc03001a8, &ixTHM_TMON1_RDIL10_DATA[0], sizeof(ixTHM_TMON1_RDIL10_DATA)/sizeof(ixTHM_TMON1_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL11_DATA", REG_SMC, 0xc03001ac, &ixTHM_TMON1_RDIL11_DATA[0], sizeof(ixTHM_TMON1_RDIL11_DATA)/sizeof(ixTHM_TMON1_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL12_DATA", REG_SMC, 0xc03001b0, &ixTHM_TMON1_RDIL12_DATA[0], sizeof(ixTHM_TMON1_RDIL12_DATA)/sizeof(ixTHM_TMON1_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL13_DATA", REG_SMC, 0xc03001b4, &ixTHM_TMON1_RDIL13_DATA[0], sizeof(ixTHM_TMON1_RDIL13_DATA)/sizeof(ixTHM_TMON1_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL14_DATA", REG_SMC, 0xc03001b8, &ixTHM_TMON1_RDIL14_DATA[0], sizeof(ixTHM_TMON1_RDIL14_DATA)/sizeof(ixTHM_TMON1_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL15_DATA", REG_SMC, 0xc03001bc, &ixTHM_TMON1_RDIL15_DATA[0], sizeof(ixTHM_TMON1_RDIL15_DATA)/sizeof(ixTHM_TMON1_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR0_DATA", REG_SMC, 0xc03001c0, &ixTHM_TMON1_RDIR0_DATA[0], sizeof(ixTHM_TMON1_RDIR0_DATA)/sizeof(ixTHM_TMON1_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR1_DATA", REG_SMC, 0xc03001c4, &ixTHM_TMON1_RDIR1_DATA[0], sizeof(ixTHM_TMON1_RDIR1_DATA)/sizeof(ixTHM_TMON1_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR2_DATA", REG_SMC, 0xc03001c8, &ixTHM_TMON1_RDIR2_DATA[0], sizeof(ixTHM_TMON1_RDIR2_DATA)/sizeof(ixTHM_TMON1_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR3_DATA", REG_SMC, 0xc03001cc, &ixTHM_TMON1_RDIR3_DATA[0], sizeof(ixTHM_TMON1_RDIR3_DATA)/sizeof(ixTHM_TMON1_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR4_DATA", REG_SMC, 0xc03001d0, &ixTHM_TMON1_RDIR4_DATA[0], sizeof(ixTHM_TMON1_RDIR4_DATA)/sizeof(ixTHM_TMON1_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR5_DATA", REG_SMC, 0xc03001d4, &ixTHM_TMON1_RDIR5_DATA[0], sizeof(ixTHM_TMON1_RDIR5_DATA)/sizeof(ixTHM_TMON1_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR6_DATA", REG_SMC, 0xc03001d8, &ixTHM_TMON1_RDIR6_DATA[0], sizeof(ixTHM_TMON1_RDIR6_DATA)/sizeof(ixTHM_TMON1_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR7_DATA", REG_SMC, 0xc03001dc, &ixTHM_TMON1_RDIR7_DATA[0], sizeof(ixTHM_TMON1_RDIR7_DATA)/sizeof(ixTHM_TMON1_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR8_DATA", REG_SMC, 0xc03001e0, &ixTHM_TMON1_RDIR8_DATA[0], sizeof(ixTHM_TMON1_RDIR8_DATA)/sizeof(ixTHM_TMON1_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR9_DATA", REG_SMC, 0xc03001e4, &ixTHM_TMON1_RDIR9_DATA[0], sizeof(ixTHM_TMON1_RDIR9_DATA)/sizeof(ixTHM_TMON1_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR10_DATA", REG_SMC, 0xc03001e8, &ixTHM_TMON1_RDIR10_DATA[0], sizeof(ixTHM_TMON1_RDIR10_DATA)/sizeof(ixTHM_TMON1_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR11_DATA", REG_SMC, 0xc03001ec, &ixTHM_TMON1_RDIR11_DATA[0], sizeof(ixTHM_TMON1_RDIR11_DATA)/sizeof(ixTHM_TMON1_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR12_DATA", REG_SMC, 0xc03001f0, &ixTHM_TMON1_RDIR12_DATA[0], sizeof(ixTHM_TMON1_RDIR12_DATA)/sizeof(ixTHM_TMON1_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR13_DATA", REG_SMC, 0xc03001f4, &ixTHM_TMON1_RDIR13_DATA[0], sizeof(ixTHM_TMON1_RDIR13_DATA)/sizeof(ixTHM_TMON1_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR14_DATA", REG_SMC, 0xc03001f8, &ixTHM_TMON1_RDIR14_DATA[0], sizeof(ixTHM_TMON1_RDIR14_DATA)/sizeof(ixTHM_TMON1_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR15_DATA", REG_SMC, 0xc03001fc, &ixTHM_TMON1_RDIR15_DATA[0], sizeof(ixTHM_TMON1_RDIR15_DATA)/sizeof(ixTHM_TMON1_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_INT_DATA", REG_SMC, 0xc0300300, &ixTHM_TMON0_INT_DATA[0], sizeof(ixTHM_TMON0_INT_DATA)/sizeof(ixTHM_TMON0_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_INT_DATA", REG_SMC, 0xc0300304, &ixTHM_TMON1_INT_DATA[0], sizeof(ixTHM_TMON1_INT_DATA)/sizeof(ixTHM_TMON1_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_DEBUG", REG_SMC, 0xc0300310, &ixTHM_TMON0_DEBUG[0], sizeof(ixTHM_TMON0_DEBUG)/sizeof(ixTHM_TMON0_DEBUG[0]), 0, 0 },
+	{ "ixTHM_TMON1_DEBUG", REG_SMC, 0xc0300314, &ixTHM_TMON1_DEBUG[0], sizeof(ixTHM_TMON1_DEBUG)/sizeof(ixTHM_TMON1_DEBUG[0]), 0, 0 },
+	{ "ixTHM_TMON0_STATUS", REG_SMC, 0xc0300320, &ixTHM_TMON0_STATUS[0], sizeof(ixTHM_TMON0_STATUS)/sizeof(ixTHM_TMON0_STATUS[0]), 0, 0 },
+	{ "ixTHM_TMON1_STATUS", REG_SMC, 0xc0300324, &ixTHM_TMON1_STATUS[0], sizeof(ixTHM_TMON1_STATUS)/sizeof(ixTHM_TMON1_STATUS[0]), 0, 0 },
+	{ "ixLCAC_MC0_CNTL", REG_SMC, 0xc0400130, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0xc0400134, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0xc0400138, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC1_CNTL", REG_SMC, 0xc040013c, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0xc0400140, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0xc0400144, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC2_CNTL", REG_SMC, 0xc0400148, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0xc040014c, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0xc0400150, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC3_CNTL", REG_SMC, 0xc0400154, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0xc0400158, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0xc040015c, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_CPL_CNTL", REG_SMC, 0xc0400160, &ixLCAC_CPL_CNTL[0], sizeof(ixLCAC_CPL_CNTL)/sizeof(ixLCAC_CPL_CNTL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_SEL", REG_SMC, 0xc0400164, &ixLCAC_CPL_OVR_SEL[0], sizeof(ixLCAC_CPL_OVR_SEL)/sizeof(ixLCAC_CPL_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_VAL", REG_SMC, 0xc0400168, &ixLCAC_CPL_OVR_VAL[0], sizeof(ixLCAC_CPL_OVR_VAL)/sizeof(ixLCAC_CPL_OVR_VAL[0]), 0, 0 },
+	{ "ixCG_DCLK_CNTL", REG_SMC, 0xc050009c, &ixCG_DCLK_CNTL[0], sizeof(ixCG_DCLK_CNTL)/sizeof(ixCG_DCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_DCLK_STATUS", REG_SMC, 0xc05000a0, &ixCG_DCLK_STATUS[0], sizeof(ixCG_DCLK_STATUS)/sizeof(ixCG_DCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_VCLK_CNTL", REG_SMC, 0xc05000a4, &ixCG_VCLK_CNTL[0], sizeof(ixCG_VCLK_CNTL)/sizeof(ixCG_VCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_VCLK_STATUS", REG_SMC, 0xc05000a8, &ixCG_VCLK_STATUS[0], sizeof(ixCG_VCLK_STATUS)/sizeof(ixCG_VCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ECLK_CNTL", REG_SMC, 0xc05000ac, &ixCG_ECLK_CNTL[0], sizeof(ixCG_ECLK_CNTL)/sizeof(ixCG_ECLK_CNTL[0]), 0, 0 },
+	{ "ixCG_ECLK_STATUS", REG_SMC, 0xc05000b0, &ixCG_ECLK_STATUS[0], sizeof(ixCG_ECLK_STATUS)/sizeof(ixCG_ECLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ACLK_CNTL", REG_SMC, 0xc05000dc, &ixCG_ACLK_CNTL[0], sizeof(ixCG_ACLK_CNTL)/sizeof(ixCG_ACLK_CNTL[0]), 0, 0 },
+	{ "ixGCK_DFS_BYPASS_CNTL", REG_SMC, 0xc0500118, &ixGCK_DFS_BYPASS_CNTL[0], sizeof(ixGCK_DFS_BYPASS_CNTL)/sizeof(ixGCK_DFS_BYPASS_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL", REG_SMC, 0xc0500140, &ixCG_SPLL_FUNC_CNTL[0], sizeof(ixCG_SPLL_FUNC_CNTL)/sizeof(ixCG_SPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_2", REG_SMC, 0xc0500144, &ixCG_SPLL_FUNC_CNTL_2[0], sizeof(ixCG_SPLL_FUNC_CNTL_2)/sizeof(ixCG_SPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_3", REG_SMC, 0xc0500148, &ixCG_SPLL_FUNC_CNTL_3[0], sizeof(ixCG_SPLL_FUNC_CNTL_3)/sizeof(ixCG_SPLL_FUNC_CNTL_3[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_4", REG_SMC, 0xc050014c, &ixCG_SPLL_FUNC_CNTL_4[0], sizeof(ixCG_SPLL_FUNC_CNTL_4)/sizeof(ixCG_SPLL_FUNC_CNTL_4[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_5", REG_SMC, 0xc0500150, &ixCG_SPLL_FUNC_CNTL_5[0], sizeof(ixCG_SPLL_FUNC_CNTL_5)/sizeof(ixCG_SPLL_FUNC_CNTL_5[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_6", REG_SMC, 0xc0500154, &ixCG_SPLL_FUNC_CNTL_6[0], sizeof(ixCG_SPLL_FUNC_CNTL_6)/sizeof(ixCG_SPLL_FUNC_CNTL_6[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_7", REG_SMC, 0xc0500158, &ixCG_SPLL_FUNC_CNTL_7[0], sizeof(ixCG_SPLL_FUNC_CNTL_7)/sizeof(ixCG_SPLL_FUNC_CNTL_7[0]), 0, 0 },
+	{ "ixSPLL_CNTL_MODE", REG_SMC, 0xc0500160, &ixSPLL_CNTL_MODE[0], sizeof(ixSPLL_CNTL_MODE)/sizeof(ixSPLL_CNTL_MODE[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM", REG_SMC, 0xc0500164, &ixCG_SPLL_SPREAD_SPECTRUM[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM_2", REG_SMC, 0xc0500168, &ixCG_SPLL_SPREAD_SPECTRUM_2[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2[0]), 0, 0 },
+	{ "ixMPLL_BYPASSCLK_SEL", REG_SMC, 0xc050019c, &ixMPLL_BYPASSCLK_SEL[0], sizeof(ixMPLL_BYPASSCLK_SEL)/sizeof(ixMPLL_BYPASSCLK_SEL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL", REG_SMC, 0xc05001a0, &ixCG_CLKPIN_CNTL[0], sizeof(ixCG_CLKPIN_CNTL)/sizeof(ixCG_CLKPIN_CNTL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_2", REG_SMC, 0xc05001a4, &ixCG_CLKPIN_CNTL_2[0], sizeof(ixCG_CLKPIN_CNTL_2)/sizeof(ixCG_CLKPIN_CNTL_2[0]), 0, 0 },
+	{ "ixTHM_CLK_CNTL", REG_SMC, 0xc05001a8, &ixTHM_CLK_CNTL[0], sizeof(ixTHM_CLK_CNTL)/sizeof(ixTHM_CLK_CNTL[0]), 0, 0 },
+	{ "ixMISC_CLK_CTRL", REG_SMC, 0xc05001ac, &ixMISC_CLK_CTRL[0], sizeof(ixMISC_CLK_CTRL)/sizeof(ixMISC_CLK_CTRL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL", REG_SMC, 0xc05001c0, &ixGCK_PLL_TEST_CNTL[0], sizeof(ixGCK_PLL_TEST_CNTL)/sizeof(ixGCK_PLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL_2", REG_SMC, 0xc05001c4, &ixGCK_PLL_TEST_CNTL_2[0], sizeof(ixGCK_PLL_TEST_CNTL_2)/sizeof(ixGCK_PLL_TEST_CNTL_2[0]), 0, 0 },
+	{ "ixGCK_ADFS_CLK_BYPASS_CNTL1", REG_SMC, 0xc05001c8, &ixGCK_ADFS_CLK_BYPASS_CNTL1[0], sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1)/sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_DC", REG_SMC, 0xc0500204, &ixCG_CLKPIN_CNTL_DC[0], sizeof(ixCG_CLKPIN_CNTL_DC)/sizeof(ixCG_CLKPIN_CNTL_DC[0]), 0, 0 },
+	{ "ixROM_CNTL", REG_SMC, 0xc0600000, &ixROM_CNTL[0], sizeof(ixROM_CNTL)/sizeof(ixROM_CNTL[0]), 0, 0 },
+	{ "ixPAGE_MIRROR_CNTL", REG_SMC, 0xc0600004, &ixPAGE_MIRROR_CNTL[0], sizeof(ixPAGE_MIRROR_CNTL)/sizeof(ixPAGE_MIRROR_CNTL[0]), 0, 0 },
+	{ "ixROM_STATUS", REG_SMC, 0xc0600008, &ixROM_STATUS[0], sizeof(ixROM_STATUS)/sizeof(ixROM_STATUS[0]), 0, 0 },
+	{ "ixCGTT_ROM_CLK_CTRL0", REG_SMC, 0xc060000c, &ixCGTT_ROM_CLK_CTRL0[0], sizeof(ixCGTT_ROM_CLK_CTRL0)/sizeof(ixCGTT_ROM_CLK_CTRL0[0]), 0, 0 },
+	{ "ixROM_INDEX", REG_SMC, 0xc0600010, &ixROM_INDEX[0], sizeof(ixROM_INDEX)/sizeof(ixROM_INDEX[0]), 0, 0 },
+	{ "ixROM_DATA", REG_SMC, 0xc0600014, &ixROM_DATA[0], sizeof(ixROM_DATA)/sizeof(ixROM_DATA[0]), 0, 0 },
+	{ "ixROM_START", REG_SMC, 0xc0600018, &ixROM_START[0], sizeof(ixROM_START)/sizeof(ixROM_START[0]), 0, 0 },
+	{ "ixROM_SW_CNTL", REG_SMC, 0xc060001c, &ixROM_SW_CNTL[0], sizeof(ixROM_SW_CNTL)/sizeof(ixROM_SW_CNTL[0]), 0, 0 },
+	{ "ixROM_SW_STATUS", REG_SMC, 0xc0600020, &ixROM_SW_STATUS[0], sizeof(ixROM_SW_STATUS)/sizeof(ixROM_SW_STATUS[0]), 0, 0 },
+	{ "ixROM_SW_COMMAND", REG_SMC, 0xc0600024, &ixROM_SW_COMMAND[0], sizeof(ixROM_SW_COMMAND)/sizeof(ixROM_SW_COMMAND[0]), 0, 0 },
+	{ "ixROM_SW_DATA_1", REG_SMC, 0xc0600028, &ixROM_SW_DATA_1[0], sizeof(ixROM_SW_DATA_1)/sizeof(ixROM_SW_DATA_1[0]), 0, 0 },
+	{ "ixROM_SW_DATA_2", REG_SMC, 0xc060002c, &ixROM_SW_DATA_2[0], sizeof(ixROM_SW_DATA_2)/sizeof(ixROM_SW_DATA_2[0]), 0, 0 },
+	{ "ixROM_SW_DATA_3", REG_SMC, 0xc0600030, &ixROM_SW_DATA_3[0], sizeof(ixROM_SW_DATA_3)/sizeof(ixROM_SW_DATA_3[0]), 0, 0 },
+	{ "ixROM_SW_DATA_4", REG_SMC, 0xc0600034, &ixROM_SW_DATA_4[0], sizeof(ixROM_SW_DATA_4)/sizeof(ixROM_SW_DATA_4[0]), 0, 0 },
+	{ "ixROM_SW_DATA_5", REG_SMC, 0xc0600038, &ixROM_SW_DATA_5[0], sizeof(ixROM_SW_DATA_5)/sizeof(ixROM_SW_DATA_5[0]), 0, 0 },
+	{ "ixROM_SW_DATA_6", REG_SMC, 0xc060003c, &ixROM_SW_DATA_6[0], sizeof(ixROM_SW_DATA_6)/sizeof(ixROM_SW_DATA_6[0]), 0, 0 },
+	{ "ixROM_SW_DATA_7", REG_SMC, 0xc0600040, &ixROM_SW_DATA_7[0], sizeof(ixROM_SW_DATA_7)/sizeof(ixROM_SW_DATA_7[0]), 0, 0 },
+	{ "ixROM_SW_DATA_8", REG_SMC, 0xc0600044, &ixROM_SW_DATA_8[0], sizeof(ixROM_SW_DATA_8)/sizeof(ixROM_SW_DATA_8[0]), 0, 0 },
+	{ "ixROM_SW_DATA_9", REG_SMC, 0xc0600048, &ixROM_SW_DATA_9[0], sizeof(ixROM_SW_DATA_9)/sizeof(ixROM_SW_DATA_9[0]), 0, 0 },
+	{ "ixROM_SW_DATA_10", REG_SMC, 0xc060004c, &ixROM_SW_DATA_10[0], sizeof(ixROM_SW_DATA_10)/sizeof(ixROM_SW_DATA_10[0]), 0, 0 },
+	{ "ixROM_SW_DATA_11", REG_SMC, 0xc0600050, &ixROM_SW_DATA_11[0], sizeof(ixROM_SW_DATA_11)/sizeof(ixROM_SW_DATA_11[0]), 0, 0 },
+	{ "ixROM_SW_DATA_12", REG_SMC, 0xc0600054, &ixROM_SW_DATA_12[0], sizeof(ixROM_SW_DATA_12)/sizeof(ixROM_SW_DATA_12[0]), 0, 0 },
+	{ "ixROM_SW_DATA_13", REG_SMC, 0xc0600058, &ixROM_SW_DATA_13[0], sizeof(ixROM_SW_DATA_13)/sizeof(ixROM_SW_DATA_13[0]), 0, 0 },
+	{ "ixROM_SW_DATA_14", REG_SMC, 0xc060005c, &ixROM_SW_DATA_14[0], sizeof(ixROM_SW_DATA_14)/sizeof(ixROM_SW_DATA_14[0]), 0, 0 },
+	{ "ixROM_SW_DATA_15", REG_SMC, 0xc0600060, &ixROM_SW_DATA_15[0], sizeof(ixROM_SW_DATA_15)/sizeof(ixROM_SW_DATA_15[0]), 0, 0 },
+	{ "ixROM_SW_DATA_16", REG_SMC, 0xc0600064, &ixROM_SW_DATA_16[0], sizeof(ixROM_SW_DATA_16)/sizeof(ixROM_SW_DATA_16[0]), 0, 0 },
+	{ "ixROM_SW_DATA_17", REG_SMC, 0xc0600068, &ixROM_SW_DATA_17[0], sizeof(ixROM_SW_DATA_17)/sizeof(ixROM_SW_DATA_17[0]), 0, 0 },
+	{ "ixROM_SW_DATA_18", REG_SMC, 0xc060006c, &ixROM_SW_DATA_18[0], sizeof(ixROM_SW_DATA_18)/sizeof(ixROM_SW_DATA_18[0]), 0, 0 },
+	{ "ixROM_SW_DATA_19", REG_SMC, 0xc0600070, &ixROM_SW_DATA_19[0], sizeof(ixROM_SW_DATA_19)/sizeof(ixROM_SW_DATA_19[0]), 0, 0 },
+	{ "ixROM_SW_DATA_20", REG_SMC, 0xc0600074, &ixROM_SW_DATA_20[0], sizeof(ixROM_SW_DATA_20)/sizeof(ixROM_SW_DATA_20[0]), 0, 0 },
+	{ "ixROM_SW_DATA_21", REG_SMC, 0xc0600078, &ixROM_SW_DATA_21[0], sizeof(ixROM_SW_DATA_21)/sizeof(ixROM_SW_DATA_21[0]), 0, 0 },
+	{ "ixROM_SW_DATA_22", REG_SMC, 0xc060007c, &ixROM_SW_DATA_22[0], sizeof(ixROM_SW_DATA_22)/sizeof(ixROM_SW_DATA_22[0]), 0, 0 },
+	{ "ixROM_SW_DATA_23", REG_SMC, 0xc0600080, &ixROM_SW_DATA_23[0], sizeof(ixROM_SW_DATA_23)/sizeof(ixROM_SW_DATA_23[0]), 0, 0 },
+	{ "ixROM_SW_DATA_24", REG_SMC, 0xc0600084, &ixROM_SW_DATA_24[0], sizeof(ixROM_SW_DATA_24)/sizeof(ixROM_SW_DATA_24[0]), 0, 0 },
+	{ "ixROM_SW_DATA_25", REG_SMC, 0xc0600088, &ixROM_SW_DATA_25[0], sizeof(ixROM_SW_DATA_25)/sizeof(ixROM_SW_DATA_25[0]), 0, 0 },
+	{ "ixROM_SW_DATA_26", REG_SMC, 0xc060008c, &ixROM_SW_DATA_26[0], sizeof(ixROM_SW_DATA_26)/sizeof(ixROM_SW_DATA_26[0]), 0, 0 },
+	{ "ixROM_SW_DATA_27", REG_SMC, 0xc0600090, &ixROM_SW_DATA_27[0], sizeof(ixROM_SW_DATA_27)/sizeof(ixROM_SW_DATA_27[0]), 0, 0 },
+	{ "ixROM_SW_DATA_28", REG_SMC, 0xc0600094, &ixROM_SW_DATA_28[0], sizeof(ixROM_SW_DATA_28)/sizeof(ixROM_SW_DATA_28[0]), 0, 0 },
+	{ "ixROM_SW_DATA_29", REG_SMC, 0xc0600098, &ixROM_SW_DATA_29[0], sizeof(ixROM_SW_DATA_29)/sizeof(ixROM_SW_DATA_29[0]), 0, 0 },
+	{ "ixROM_SW_DATA_30", REG_SMC, 0xc060009c, &ixROM_SW_DATA_30[0], sizeof(ixROM_SW_DATA_30)/sizeof(ixROM_SW_DATA_30[0]), 0, 0 },
+	{ "ixROM_SW_DATA_31", REG_SMC, 0xc06000a0, &ixROM_SW_DATA_31[0], sizeof(ixROM_SW_DATA_31)/sizeof(ixROM_SW_DATA_31[0]), 0, 0 },
+	{ "ixROM_SW_DATA_32", REG_SMC, 0xc06000a4, &ixROM_SW_DATA_32[0], sizeof(ixROM_SW_DATA_32)/sizeof(ixROM_SW_DATA_32[0]), 0, 0 },
+	{ "ixROM_SW_DATA_33", REG_SMC, 0xc06000a8, &ixROM_SW_DATA_33[0], sizeof(ixROM_SW_DATA_33)/sizeof(ixROM_SW_DATA_33[0]), 0, 0 },
+	{ "ixROM_SW_DATA_34", REG_SMC, 0xc06000ac, &ixROM_SW_DATA_34[0], sizeof(ixROM_SW_DATA_34)/sizeof(ixROM_SW_DATA_34[0]), 0, 0 },
+	{ "ixROM_SW_DATA_35", REG_SMC, 0xc06000b0, &ixROM_SW_DATA_35[0], sizeof(ixROM_SW_DATA_35)/sizeof(ixROM_SW_DATA_35[0]), 0, 0 },
+	{ "ixROM_SW_DATA_36", REG_SMC, 0xc06000b4, &ixROM_SW_DATA_36[0], sizeof(ixROM_SW_DATA_36)/sizeof(ixROM_SW_DATA_36[0]), 0, 0 },
+	{ "ixROM_SW_DATA_37", REG_SMC, 0xc06000b8, &ixROM_SW_DATA_37[0], sizeof(ixROM_SW_DATA_37)/sizeof(ixROM_SW_DATA_37[0]), 0, 0 },
+	{ "ixROM_SW_DATA_38", REG_SMC, 0xc06000bc, &ixROM_SW_DATA_38[0], sizeof(ixROM_SW_DATA_38)/sizeof(ixROM_SW_DATA_38[0]), 0, 0 },
+	{ "ixROM_SW_DATA_39", REG_SMC, 0xc06000c0, &ixROM_SW_DATA_39[0], sizeof(ixROM_SW_DATA_39)/sizeof(ixROM_SW_DATA_39[0]), 0, 0 },
+	{ "ixROM_SW_DATA_40", REG_SMC, 0xc06000c4, &ixROM_SW_DATA_40[0], sizeof(ixROM_SW_DATA_40)/sizeof(ixROM_SW_DATA_40[0]), 0, 0 },
+	{ "ixROM_SW_DATA_41", REG_SMC, 0xc06000c8, &ixROM_SW_DATA_41[0], sizeof(ixROM_SW_DATA_41)/sizeof(ixROM_SW_DATA_41[0]), 0, 0 },
+	{ "ixROM_SW_DATA_42", REG_SMC, 0xc06000cc, &ixROM_SW_DATA_42[0], sizeof(ixROM_SW_DATA_42)/sizeof(ixROM_SW_DATA_42[0]), 0, 0 },
+	{ "ixROM_SW_DATA_43", REG_SMC, 0xc06000d0, &ixROM_SW_DATA_43[0], sizeof(ixROM_SW_DATA_43)/sizeof(ixROM_SW_DATA_43[0]), 0, 0 },
+	{ "ixROM_SW_DATA_44", REG_SMC, 0xc06000d4, &ixROM_SW_DATA_44[0], sizeof(ixROM_SW_DATA_44)/sizeof(ixROM_SW_DATA_44[0]), 0, 0 },
+	{ "ixROM_SW_DATA_45", REG_SMC, 0xc06000d8, &ixROM_SW_DATA_45[0], sizeof(ixROM_SW_DATA_45)/sizeof(ixROM_SW_DATA_45[0]), 0, 0 },
+	{ "ixROM_SW_DATA_46", REG_SMC, 0xc06000dc, &ixROM_SW_DATA_46[0], sizeof(ixROM_SW_DATA_46)/sizeof(ixROM_SW_DATA_46[0]), 0, 0 },
+	{ "ixROM_SW_DATA_47", REG_SMC, 0xc06000e0, &ixROM_SW_DATA_47[0], sizeof(ixROM_SW_DATA_47)/sizeof(ixROM_SW_DATA_47[0]), 0, 0 },
+	{ "ixROM_SW_DATA_48", REG_SMC, 0xc06000e4, &ixROM_SW_DATA_48[0], sizeof(ixROM_SW_DATA_48)/sizeof(ixROM_SW_DATA_48[0]), 0, 0 },
+	{ "ixROM_SW_DATA_49", REG_SMC, 0xc06000e8, &ixROM_SW_DATA_49[0], sizeof(ixROM_SW_DATA_49)/sizeof(ixROM_SW_DATA_49[0]), 0, 0 },
+	{ "ixROM_SW_DATA_50", REG_SMC, 0xc06000ec, &ixROM_SW_DATA_50[0], sizeof(ixROM_SW_DATA_50)/sizeof(ixROM_SW_DATA_50[0]), 0, 0 },
+	{ "ixROM_SW_DATA_51", REG_SMC, 0xc06000f0, &ixROM_SW_DATA_51[0], sizeof(ixROM_SW_DATA_51)/sizeof(ixROM_SW_DATA_51[0]), 0, 0 },
+	{ "ixROM_SW_DATA_52", REG_SMC, 0xc06000f4, &ixROM_SW_DATA_52[0], sizeof(ixROM_SW_DATA_52)/sizeof(ixROM_SW_DATA_52[0]), 0, 0 },
+	{ "ixROM_SW_DATA_53", REG_SMC, 0xc06000f8, &ixROM_SW_DATA_53[0], sizeof(ixROM_SW_DATA_53)/sizeof(ixROM_SW_DATA_53[0]), 0, 0 },
+	{ "ixROM_SW_DATA_54", REG_SMC, 0xc06000fc, &ixROM_SW_DATA_54[0], sizeof(ixROM_SW_DATA_54)/sizeof(ixROM_SW_DATA_54[0]), 0, 0 },
+	{ "ixROM_SW_DATA_55", REG_SMC, 0xc0600100, &ixROM_SW_DATA_55[0], sizeof(ixROM_SW_DATA_55)/sizeof(ixROM_SW_DATA_55[0]), 0, 0 },
+	{ "ixROM_SW_DATA_56", REG_SMC, 0xc0600104, &ixROM_SW_DATA_56[0], sizeof(ixROM_SW_DATA_56)/sizeof(ixROM_SW_DATA_56[0]), 0, 0 },
+	{ "ixROM_SW_DATA_57", REG_SMC, 0xc0600108, &ixROM_SW_DATA_57[0], sizeof(ixROM_SW_DATA_57)/sizeof(ixROM_SW_DATA_57[0]), 0, 0 },
+	{ "ixROM_SW_DATA_58", REG_SMC, 0xc060010c, &ixROM_SW_DATA_58[0], sizeof(ixROM_SW_DATA_58)/sizeof(ixROM_SW_DATA_58[0]), 0, 0 },
+	{ "ixROM_SW_DATA_59", REG_SMC, 0xc0600110, &ixROM_SW_DATA_59[0], sizeof(ixROM_SW_DATA_59)/sizeof(ixROM_SW_DATA_59[0]), 0, 0 },
+	{ "ixROM_SW_DATA_60", REG_SMC, 0xc0600114, &ixROM_SW_DATA_60[0], sizeof(ixROM_SW_DATA_60)/sizeof(ixROM_SW_DATA_60[0]), 0, 0 },
+	{ "ixROM_SW_DATA_61", REG_SMC, 0xc0600118, &ixROM_SW_DATA_61[0], sizeof(ixROM_SW_DATA_61)/sizeof(ixROM_SW_DATA_61[0]), 0, 0 },
+	{ "ixROM_SW_DATA_62", REG_SMC, 0xc060011c, &ixROM_SW_DATA_62[0], sizeof(ixROM_SW_DATA_62)/sizeof(ixROM_SW_DATA_62[0]), 0, 0 },
+	{ "ixROM_SW_DATA_63", REG_SMC, 0xc0600120, &ixROM_SW_DATA_63[0], sizeof(ixROM_SW_DATA_63)/sizeof(ixROM_SW_DATA_63[0]), 0, 0 },
+	{ "ixROM_SW_DATA_64", REG_SMC, 0xc0600124, &ixROM_SW_DATA_64[0], sizeof(ixROM_SW_DATA_64)/sizeof(ixROM_SW_DATA_64[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, &ixCG_THERMAL_INT_ENA[0], sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, &ixCG_THERMAL_INT_CTRL[0], sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, &ixCG_THERMAL_INT_STATUS[0], sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
+	{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, &ixSMU_MAIN_PLL_OP_FREQ[0], sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
+	{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
+	{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
+	{ "ixSMU_INPUT_DATA", REG_SMC, 0xe00030b8, &ixSMU_INPUT_DATA[0], sizeof(ixSMU_INPUT_DATA)/sizeof(ixSMU_INPUT_DATA[0]), 0, 0 },
diff --git a/src/lib/ip/smu713.c b/src/lib/ip/smu713.c
new file mode 100644
index 0000000..c1e0ff8
--- /dev/null
+++ b/src/lib/ip/smu713.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "smu713_bits.i"
+
+static const struct umr_reg smu713_registers[] = {
+#include "smu713_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_smu713(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "smu713";
+	ip->no_regs = sizeof(smu713_registers)/sizeof(smu713_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(smu713_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, smu713_registers, sizeof(smu713_registers));
+	return ip;
+}
diff --git a/src/lib/ip/smu713_bits.i b/src/lib/ip/smu713_bits.i
new file mode 100644
index 0000000..b166f93
--- /dev/null
+++ b/src/lib/ip/smu713_bits.i
@@ -0,0 +1,5380 @@
+static struct umr_bitfield mmGPIOPAD_SW_INT_STAT[] = {
+	 { "SW_INT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_STRENGTH[] = {
+	 { "GPIO_STRENGTH_SN", 0, 3, &umr_bitfield_default },
+	 { "GPIO_STRENGTH_SP", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_MASK[] = {
+	 { "GPIO_MASK", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_A[] = {
+	 { "GPIO_A", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EN[] = {
+	 { "GPIO_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_Y[] = {
+	 { "GPIO_Y", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PINSTRAPS[] = {
+	 { "GPIO_PINSTRAP_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_28", 28, 28, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_29", 29, 29, &umr_bitfield_default },
+	 { "GPIO_PINSTRAP_30", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_EN[] = {
+	 { "GPIO_INT_STAT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT[] = {
+	 { "GPIO_INT_STAT", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_STAT_AK[] = {
+	 { "GPIO_INT_STAT_AK_0", 0, 0, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_1", 1, 1, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_2", 2, 2, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_3", 3, 3, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_4", 4, 4, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_5", 5, 5, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_6", 6, 6, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_7", 7, 7, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_8", 8, 8, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_9", 9, 9, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_10", 10, 10, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_11", 11, 11, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_12", 12, 12, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_13", 13, 13, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_14", 14, 14, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_15", 15, 15, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_16", 16, 16, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_17", 17, 17, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_18", 18, 18, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_19", 19, 19, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_20", 20, 20, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_21", 21, 21, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_22", 22, 22, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_23", 23, 23, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_24", 24, 24, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_25", 25, 25, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_26", 26, 26, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_27", 27, 27, &umr_bitfield_default },
+	 { "GPIO_INT_STAT_AK_28", 28, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_STAT_AK", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_EN[] = {
+	 { "GPIO_INT_EN", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_TYPE[] = {
+	 { "GPIO_INT_TYPE", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_TYPE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_INT_POLARITY[] = {
+	 { "GPIO_INT_POLARITY", 0, 28, &umr_bitfield_default },
+	 { "SW_INITIATED_INT_POLARITY", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_EXTERN_TRIG_CNTL[] = {
+	 { "EXTERN_TRIG_SEL", 0, 4, &umr_bitfield_default },
+	 { "EXTERN_TRIG_CLR", 5, 5, &umr_bitfield_default },
+	 { "EXTERN_TRIG_READ", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_RCVR_SEL[] = {
+	 { "GPIO_RCVR_SEL", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PU_EN[] = {
+	 { "GPIO_PU_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGPIOPAD_PD_EN[] = {
+	 { "GPIO_PD_EN", 0, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmCG_FPS_CNT[] = {
+	 { "FPS_CNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_0[] = {
+	 { "WEIGHT_CU_SIG0", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_CAC_CGTT_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSE_CAC_CGTT_CLK_CTRL[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_DYN", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE_REG", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_CAC_LKG_AGGR_LOWER[] = {
+	 { "LKG_AGGR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_CAC_LKG_AGGR_UPPER[] = {
+	 { "LKG_AGGR_63_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_1[] = {
+	 { "WEIGHT_CU_SIG2", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_2[] = {
+	 { "WEIGHT_CU_SIG4", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG5", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_3[] = {
+	 { "WEIGHT_CU_SIG6", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG7", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_4[] = {
+	 { "WEIGHT_CU_SIG8", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG9", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_5[] = {
+	 { "WEIGHT_CU_SIG10", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG11", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_6[] = {
+	 { "WEIGHT_CU_SIG12", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG13", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_7[] = {
+	 { "WEIGHT_CU_SIG14", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG15", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFIRMWARE_FLAGS[] = {
+	 { "INTERRUPTS_ENABLED", 0, 0, &umr_bitfield_default },
+	 { "RESERVED", 1, 23, &umr_bitfield_default },
+	 { "TEST_COUNT", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_STATUS[] = {
+	 { "VDD_Boost", 0, 7, &umr_bitfield_default },
+	 { "VDD_Throttle", 8, 15, &umr_bitfield_default },
+	 { "VDDC_Boost", 16, 23, &umr_bitfield_default },
+	 { "VDDC_Throttle", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_MV_AVERAGE[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTDC_VRM_LIMIT[] = {
+	 { "IDD", 0, 15, &umr_bitfield_default },
+	 { "IDDC", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixFEATURE_STATUS[] = {
+	 { "SCLK_DPM_ON", 0, 0, &umr_bitfield_default },
+	 { "MCLK_DPM_ON", 1, 1, &umr_bitfield_default },
+	 { "LCLK_DPM_ON", 2, 2, &umr_bitfield_default },
+	 { "UVD_DPM_ON", 3, 3, &umr_bitfield_default },
+	 { "VCE_DPM_ON", 4, 4, &umr_bitfield_default },
+	 { "SAMU_DPM_ON", 5, 5, &umr_bitfield_default },
+	 { "ACP_DPM_ON", 6, 6, &umr_bitfield_default },
+	 { "PCIE_DPM_ON", 7, 7, &umr_bitfield_default },
+	 { "BAPM_ON", 8, 8, &umr_bitfield_default },
+	 { "LPMX_ON", 9, 9, &umr_bitfield_default },
+	 { "NBDPM_ON", 10, 10, &umr_bitfield_default },
+	 { "LHTC_ON", 11, 11, &umr_bitfield_default },
+	 { "VPC_ON", 12, 12, &umr_bitfield_default },
+	 { "VOLTAGE_CONTROLLER_ON", 13, 13, &umr_bitfield_default },
+	 { "TDC_LIMIT_ON", 14, 14, &umr_bitfield_default },
+	 { "GPU_CAC_ON", 15, 15, &umr_bitfield_default },
+	 { "AVS_ON", 16, 16, &umr_bitfield_default },
+	 { "SPMI_ON", 17, 17, &umr_bitfield_default },
+	 { "SCLK_DPM_FORCED", 18, 18, &umr_bitfield_default },
+	 { "MCLK_DPM_FORCED", 19, 19, &umr_bitfield_default },
+	 { "LCLK_DPM_FORCED", 20, 20, &umr_bitfield_default },
+	 { "PCIE_DPM_FORCED", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixENTITY_TEMPERATURES_1[] = {
+	 { "GPU", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_1[] = {
+	 { "entries_0_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_2[] = {
+	 { "entries_0_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_3[] = {
+	 { "entries_0_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_4[] = {
+	 { "entries_0_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_5[] = {
+	 { "entries_0_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_6[] = {
+	 { "entries_0_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_7[] = {
+	 { "entries_0_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_8[] = {
+	 { "entries_0_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_9[] = {
+	 { "entries_0_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_10[] = {
+	 { "entries_0_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_11[] = {
+	 { "entries_0_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_12[] = {
+	 { "entries_0_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_0_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_0_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_0_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_13[] = {
+	 { "entries_1_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_14[] = {
+	 { "entries_1_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_15[] = {
+	 { "entries_1_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_16[] = {
+	 { "entries_1_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_17[] = {
+	 { "entries_1_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_18[] = {
+	 { "entries_1_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_19[] = {
+	 { "entries_1_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_20[] = {
+	 { "entries_1_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_21[] = {
+	 { "entries_1_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_22[] = {
+	 { "entries_1_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_23[] = {
+	 { "entries_1_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_24[] = {
+	 { "entries_1_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_1_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_1_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_1_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_25[] = {
+	 { "entries_2_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_26[] = {
+	 { "entries_2_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_27[] = {
+	 { "entries_2_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_28[] = {
+	 { "entries_2_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_29[] = {
+	 { "entries_2_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_30[] = {
+	 { "entries_2_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_31[] = {
+	 { "entries_2_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_32[] = {
+	 { "entries_2_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_33[] = {
+	 { "entries_2_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_34[] = {
+	 { "entries_2_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_35[] = {
+	 { "entries_2_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_36[] = {
+	 { "entries_2_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_2_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_2_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_2_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_37[] = {
+	 { "entries_3_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_38[] = {
+	 { "entries_3_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_39[] = {
+	 { "entries_3_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_40[] = {
+	 { "entries_3_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_41[] = {
+	 { "entries_3_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_42[] = {
+	 { "entries_3_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_43[] = {
+	 { "entries_3_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_44[] = {
+	 { "entries_3_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_45[] = {
+	 { "entries_3_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_46[] = {
+	 { "entries_3_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_47[] = {
+	 { "entries_3_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_48[] = {
+	 { "entries_3_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_3_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_3_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_3_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_49[] = {
+	 { "entries_4_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_50[] = {
+	 { "entries_4_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_51[] = {
+	 { "entries_4_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_52[] = {
+	 { "entries_4_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_53[] = {
+	 { "entries_4_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_54[] = {
+	 { "entries_4_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_55[] = {
+	 { "entries_4_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_56[] = {
+	 { "entries_4_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_57[] = {
+	 { "entries_4_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_58[] = {
+	 { "entries_4_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_59[] = {
+	 { "entries_4_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_60[] = {
+	 { "entries_4_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_4_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_4_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_4_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_61[] = {
+	 { "entries_5_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_62[] = {
+	 { "entries_5_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_63[] = {
+	 { "entries_5_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_64[] = {
+	 { "entries_5_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_65[] = {
+	 { "entries_5_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_66[] = {
+	 { "entries_5_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_67[] = {
+	 { "entries_5_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_68[] = {
+	 { "entries_5_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_69[] = {
+	 { "entries_5_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_70[] = {
+	 { "entries_5_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_71[] = {
+	 { "entries_5_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_72[] = {
+	 { "entries_5_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_5_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_5_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_5_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_73[] = {
+	 { "entries_6_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_74[] = {
+	 { "entries_6_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_75[] = {
+	 { "entries_6_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_76[] = {
+	 { "entries_6_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_77[] = {
+	 { "entries_6_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_78[] = {
+	 { "entries_6_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_79[] = {
+	 { "entries_6_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_80[] = {
+	 { "entries_6_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_81[] = {
+	 { "entries_6_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_82[] = {
+	 { "entries_6_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_83[] = {
+	 { "entries_6_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_84[] = {
+	 { "entries_6_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_6_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_6_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_6_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_85[] = {
+	 { "entries_7_0_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_86[] = {
+	 { "entries_7_0_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_87[] = {
+	 { "entries_7_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_0_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_88[] = {
+	 { "entries_7_1_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_89[] = {
+	 { "entries_7_1_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_90[] = {
+	 { "entries_7_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_1_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_91[] = {
+	 { "entries_7_2_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_92[] = {
+	 { "entries_7_2_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_93[] = {
+	 { "entries_7_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_2_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_94[] = {
+	 { "entries_7_3_McArbDramTiming", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_95[] = {
+	 { "entries_7_3_McArbDramTiming2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMCARB_DRAM_TIMING_TABLE_96[] = {
+	 { "entries_7_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "entries_7_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "entries_7_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "entries_7_3_McArbBurstTime", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_1[] = {
+	 { "GraphicsPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_2[] = {
+	 { "GraphicsPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_3[] = {
+	 { "GraphicsPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_4[] = {
+	 { "GraphicsPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_5[] = {
+	 { "GraphicsPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_6[] = {
+	 { "GraphicsPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_7[] = {
+	 { "GraphicsPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_8[] = {
+	 { "GraphicsPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_9[] = {
+	 { "GraphicsPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_10[] = {
+	 { "MemoryPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_11[] = {
+	 { "MemoryPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_12[] = {
+	 { "MemoryPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_13[] = {
+	 { "MemoryPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_14[] = {
+	 { "MemoryPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_15[] = {
+	 { "MemoryPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_16[] = {
+	 { "MemoryPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_17[] = {
+	 { "MemoryPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_18[] = {
+	 { "MemoryPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_19[] = {
+	 { "LinkPIDController_Ki", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_20[] = {
+	 { "LinkPIDController_LFWindupUpperLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_21[] = {
+	 { "LinkPIDController_LFWindupLowerLim", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_22[] = {
+	 { "LinkPIDController_StatePrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_23[] = {
+	 { "LinkPIDController_LfPrecision", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_24[] = {
+	 { "LinkPIDController_LfOffset", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_25[] = {
+	 { "LinkPIDController_MaxState", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_26[] = {
+	 { "LinkPIDController_MaxLfFraction", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_27[] = {
+	 { "LinkPIDController_StateShift", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_28[] = {
+	 { "SystemFlags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_29[] = {
+	 { "VRConfig", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_30[] = {
+	 { "SmioMask1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_31[] = {
+	 { "SmioMask2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_32[] = {
+	 { "SmioTable1_Pattern_0_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_33[] = {
+	 { "SmioTable1_Pattern_1_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_34[] = {
+	 { "SmioTable1_Pattern_2_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_35[] = {
+	 { "SmioTable1_Pattern_3_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable1_Pattern_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_36[] = {
+	 { "SmioTable2_Pattern_0_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_0_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_0_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_37[] = {
+	 { "SmioTable2_Pattern_1_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_1_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_1_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_38[] = {
+	 { "SmioTable2_Pattern_2_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_2_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_2_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_39[] = {
+	 { "SmioTable2_Pattern_3_padding", 0, 7, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_3_Smio", 8, 15, &umr_bitfield_default },
+	 { "SmioTable2_Pattern_3_Voltage", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_40[] = {
+	 { "VddcLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_41[] = {
+	 { "VddciLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_42[] = {
+	 { "VddGfxLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_43[] = {
+	 { "MvddLevelCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_44[] = {
+	 { "VddcTable_1", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_45[] = {
+	 { "VddcTable_3", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_46[] = {
+	 { "VddcTable_5", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_4", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_47[] = {
+	 { "VddcTable_7", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_6", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_48[] = {
+	 { "VddcTable_9", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_49[] = {
+	 { "VddcTable_11", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_10", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_50[] = {
+	 { "VddcTable_13", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_51[] = {
+	 { "VddcTable_15", 0, 15, &umr_bitfield_default },
+	 { "VddcTable_14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_52[] = {
+	 { "VddGfxTable_1", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_53[] = {
+	 { "VddGfxTable_3", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_54[] = {
+	 { "VddGfxTable_5", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_4", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_55[] = {
+	 { "VddGfxTable_7", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_6", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_56[] = {
+	 { "VddGfxTable_9", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_8", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_57[] = {
+	 { "VddGfxTable_11", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_10", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_58[] = {
+	 { "VddGfxTable_13", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_12", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_59[] = {
+	 { "VddGfxTable_15", 0, 15, &umr_bitfield_default },
+	 { "VddGfxTable_14", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_60[] = {
+	 { "VddciTable_1", 0, 15, &umr_bitfield_default },
+	 { "VddciTable_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_61[] = {
+	 { "VddciTable_3", 0, 15, &umr_bitfield_default },
+	 { "VddciTable_2", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_62[] = {
+	 { "VddciTable_5", 0, 15, &umr_bitfield_default },
+	 { "VddciTable_4", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_63[] = {
+	 { "VddciTable_7", 0, 15, &umr_bitfield_default },
+	 { "VddciTable_6", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_64[] = {
+	 { "BapmVddGfxVidHiSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_65[] = {
+	 { "BapmVddGfxVidHiSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_66[] = {
+	 { "BapmVddGfxVidHiSidd_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_67[] = {
+	 { "BapmVddGfxVidHiSidd_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_68[] = {
+	 { "BapmVddGfxVidLoSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_69[] = {
+	 { "BapmVddGfxVidLoSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_70[] = {
+	 { "BapmVddGfxVidLoSidd_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_71[] = {
+	 { "BapmVddGfxVidLoSidd_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidLoSidd_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_72[] = {
+	 { "BapmVddGfxVidHiSidd2_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_73[] = {
+	 { "BapmVddGfxVidHiSidd2_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_74[] = {
+	 { "BapmVddGfxVidHiSidd2_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_75[] = {
+	 { "BapmVddGfxVidHiSidd2_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddGfxVidHiSidd2_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_76[] = {
+	 { "BapmVddcVidHiSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_77[] = {
+	 { "BapmVddcVidHiSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_78[] = {
+	 { "BapmVddcVidHiSidd_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_79[] = {
+	 { "BapmVddcVidHiSidd_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_80[] = {
+	 { "BapmVddcVidLoSidd_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_81[] = {
+	 { "BapmVddcVidLoSidd_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_82[] = {
+	 { "BapmVddcVidLoSidd_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_83[] = {
+	 { "BapmVddcVidLoSidd_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidLoSidd_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_84[] = {
+	 { "BapmVddcVidHiSidd2_3", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_2", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_1", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_85[] = {
+	 { "BapmVddcVidHiSidd2_7", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_6", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_5", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_86[] = {
+	 { "BapmVddcVidHiSidd2_11", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_10", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_9", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_87[] = {
+	 { "BapmVddcVidHiSidd2_15", 0, 7, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_14", 8, 15, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_13", 16, 23, &umr_bitfield_default },
+	 { "BapmVddcVidHiSidd2_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_88[] = {
+	 { "MasterDeepSleepControl", 0, 7, &umr_bitfield_default },
+	 { "LinkLevelCount", 8, 15, &umr_bitfield_default },
+	 { "MemoryDpmLevelCount", 16, 23, &umr_bitfield_default },
+	 { "GraphicsDpmLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_89[] = {
+	 { "SamuLevelCount", 0, 7, &umr_bitfield_default },
+	 { "AcpLevelCount", 8, 15, &umr_bitfield_default },
+	 { "VceLevelCount", 16, 23, &umr_bitfield_default },
+	 { "UvdLevelCount", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_90[] = {
+	 { "Reserved_0", 0, 7, &umr_bitfield_default },
+	 { "ThermOutMode", 8, 15, &umr_bitfield_default },
+	 { "ThermOutPolarity", 16, 23, &umr_bitfield_default },
+	 { "ThermOutGpio", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_91[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_92[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_93[] = {
+	 { "Reserved_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_94[] = {
+	 { "Reserved_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_95[] = {
+	 { "GraphicsLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_96[] = {
+	 { "GraphicsLevel_0_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_97[] = {
+	 { "GraphicsLevel_0_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_98[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_99[] = {
+	 { "GraphicsLevel_0_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_100[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_101[] = {
+	 { "GraphicsLevel_0_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_102[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_103[] = {
+	 { "GraphicsLevel_0_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_104[] = {
+	 { "GraphicsLevel_0_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_105[] = {
+	 { "GraphicsLevel_0_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_106[] = {
+	 { "GraphicsLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_107[] = {
+	 { "GraphicsLevel_1_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_108[] = {
+	 { "GraphicsLevel_1_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_109[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_110[] = {
+	 { "GraphicsLevel_1_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_111[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_112[] = {
+	 { "GraphicsLevel_1_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_113[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_114[] = {
+	 { "GraphicsLevel_1_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_115[] = {
+	 { "GraphicsLevel_1_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_116[] = {
+	 { "GraphicsLevel_1_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_117[] = {
+	 { "GraphicsLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_118[] = {
+	 { "GraphicsLevel_2_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_119[] = {
+	 { "GraphicsLevel_2_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_120[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_121[] = {
+	 { "GraphicsLevel_2_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_122[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_123[] = {
+	 { "GraphicsLevel_2_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_124[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_125[] = {
+	 { "GraphicsLevel_2_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_126[] = {
+	 { "GraphicsLevel_2_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_127[] = {
+	 { "GraphicsLevel_2_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_128[] = {
+	 { "GraphicsLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_129[] = {
+	 { "GraphicsLevel_3_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_130[] = {
+	 { "GraphicsLevel_3_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_131[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_132[] = {
+	 { "GraphicsLevel_3_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_133[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_134[] = {
+	 { "GraphicsLevel_3_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_135[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_136[] = {
+	 { "GraphicsLevel_3_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_137[] = {
+	 { "GraphicsLevel_3_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_138[] = {
+	 { "GraphicsLevel_3_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_139[] = {
+	 { "GraphicsLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_140[] = {
+	 { "GraphicsLevel_4_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_141[] = {
+	 { "GraphicsLevel_4_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_142[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_143[] = {
+	 { "GraphicsLevel_4_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_144[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_145[] = {
+	 { "GraphicsLevel_4_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_146[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_147[] = {
+	 { "GraphicsLevel_4_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_148[] = {
+	 { "GraphicsLevel_4_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_149[] = {
+	 { "GraphicsLevel_4_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_4_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_4_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_4_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_150[] = {
+	 { "GraphicsLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_151[] = {
+	 { "GraphicsLevel_5_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_152[] = {
+	 { "GraphicsLevel_5_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_153[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_154[] = {
+	 { "GraphicsLevel_5_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_155[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_156[] = {
+	 { "GraphicsLevel_5_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_157[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_158[] = {
+	 { "GraphicsLevel_5_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_159[] = {
+	 { "GraphicsLevel_5_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_160[] = {
+	 { "GraphicsLevel_5_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_5_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_5_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_5_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_161[] = {
+	 { "GraphicsLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_162[] = {
+	 { "GraphicsLevel_6_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_163[] = {
+	 { "GraphicsLevel_6_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_164[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_165[] = {
+	 { "GraphicsLevel_6_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_166[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_167[] = {
+	 { "GraphicsLevel_6_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_168[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_169[] = {
+	 { "GraphicsLevel_6_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_170[] = {
+	 { "GraphicsLevel_6_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_171[] = {
+	 { "GraphicsLevel_6_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_6_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_6_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_6_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_172[] = {
+	 { "GraphicsLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_173[] = {
+	 { "GraphicsLevel_7_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_174[] = {
+	 { "GraphicsLevel_7_ActivityLevel", 0, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DeepSleepDivId", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_pcieDpmLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_175[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_176[] = {
+	 { "GraphicsLevel_7_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_177[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_178[] = {
+	 { "GraphicsLevel_7_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_179[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_180[] = {
+	 { "GraphicsLevel_7_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_181[] = {
+	 { "GraphicsLevel_7_EnabledForThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_182[] = {
+	 { "GraphicsLevel_7_PowerThrottle", 0, 7, &umr_bitfield_default },
+	 { "GraphicsLevel_7_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "GraphicsLevel_7_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "GraphicsLevel_7_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_183[] = {
+	 { "MemoryACPILevel_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_184[] = {
+	 { "MemoryACPILevel_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_185[] = {
+	 { "MemoryACPILevel_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_186[] = {
+	 { "MemoryACPILevel_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_FreqRange", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_StutterEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_187[] = {
+	 { "MemoryACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryACPILevel_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_188[] = {
+	 { "MemoryACPILevel_MclkDivider", 0, 7, &umr_bitfield_default },
+	 { "MemoryACPILevel_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryACPILevel_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_189[] = {
+	 { "MemoryLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_190[] = {
+	 { "MemoryLevel_0_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_191[] = {
+	 { "MemoryLevel_0_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_192[] = {
+	 { "MemoryLevel_0_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_FreqRange", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_StutterEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_193[] = {
+	 { "MemoryLevel_0_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_0_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_194[] = {
+	 { "MemoryLevel_0_MclkDivider", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_0_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_0_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_195[] = {
+	 { "MemoryLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_196[] = {
+	 { "MemoryLevel_1_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_197[] = {
+	 { "MemoryLevel_1_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_198[] = {
+	 { "MemoryLevel_1_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_FreqRange", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_StutterEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_199[] = {
+	 { "MemoryLevel_1_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_1_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_200[] = {
+	 { "MemoryLevel_1_MclkDivider", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_1_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_1_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_201[] = {
+	 { "MemoryLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_202[] = {
+	 { "MemoryLevel_2_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_203[] = {
+	 { "MemoryLevel_2_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_204[] = {
+	 { "MemoryLevel_2_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_FreqRange", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_StutterEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_205[] = {
+	 { "MemoryLevel_2_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_2_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_206[] = {
+	 { "MemoryLevel_2_MclkDivider", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_2_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_2_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_207[] = {
+	 { "MemoryLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_208[] = {
+	 { "MemoryLevel_3_MinMvdd", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_209[] = {
+	 { "MemoryLevel_3_MclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_210[] = {
+	 { "MemoryLevel_3_EnabledForActivity", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_EnabledForThrottle", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_FreqRange", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_StutterEnable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_211[] = {
+	 { "MemoryLevel_3_padding", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_VoltageDownHyst", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_DownHyst", 16, 23, &umr_bitfield_default },
+	 { "MemoryLevel_3_UpHyst", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_212[] = {
+	 { "MemoryLevel_3_MclkDivider", 0, 7, &umr_bitfield_default },
+	 { "MemoryLevel_3_DisplayWatermark", 8, 15, &umr_bitfield_default },
+	 { "MemoryLevel_3_ActivityLevel", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_213[] = {
+	 { "LinkLevel_0_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_0_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_0_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_214[] = {
+	 { "LinkLevel_0_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_215[] = {
+	 { "LinkLevel_0_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_216[] = {
+	 { "LinkLevel_0_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_217[] = {
+	 { "LinkLevel_1_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_1_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_1_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_218[] = {
+	 { "LinkLevel_1_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_219[] = {
+	 { "LinkLevel_1_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_220[] = {
+	 { "LinkLevel_1_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_221[] = {
+	 { "LinkLevel_2_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_2_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_2_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_222[] = {
+	 { "LinkLevel_2_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_223[] = {
+	 { "LinkLevel_2_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_224[] = {
+	 { "LinkLevel_2_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_225[] = {
+	 { "LinkLevel_3_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_3_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_3_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_226[] = {
+	 { "LinkLevel_3_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_227[] = {
+	 { "LinkLevel_3_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_228[] = {
+	 { "LinkLevel_3_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_229[] = {
+	 { "LinkLevel_4_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_4_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_4_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_230[] = {
+	 { "LinkLevel_4_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_231[] = {
+	 { "LinkLevel_4_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_232[] = {
+	 { "LinkLevel_4_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_233[] = {
+	 { "LinkLevel_5_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_5_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_5_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_234[] = {
+	 { "LinkLevel_5_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_235[] = {
+	 { "LinkLevel_5_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_236[] = {
+	 { "LinkLevel_5_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_237[] = {
+	 { "LinkLevel_6_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_6_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_6_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_238[] = {
+	 { "LinkLevel_6_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_239[] = {
+	 { "LinkLevel_6_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_240[] = {
+	 { "LinkLevel_6_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_241[] = {
+	 { "LinkLevel_7_SPC", 0, 7, &umr_bitfield_default },
+	 { "LinkLevel_7_EnabledForActivity", 8, 15, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieLaneCount", 16, 23, &umr_bitfield_default },
+	 { "LinkLevel_7_PcieGenSpeed", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_242[] = {
+	 { "LinkLevel_7_DownThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_243[] = {
+	 { "LinkLevel_7_UpThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_244[] = {
+	 { "LinkLevel_7_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_245[] = {
+	 { "ACPILevel_Flags", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_246[] = {
+	 { "ACPILevel_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_247[] = {
+	 { "ACPILevel_SclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_248[] = {
+	 { "ACPILevel_padding", 0, 7, &umr_bitfield_default },
+	 { "ACPILevel_DeepSleepDivId", 8, 15, &umr_bitfield_default },
+	 { "ACPILevel_DisplayWatermark", 16, 23, &umr_bitfield_default },
+	 { "ACPILevel_SclkDid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_249[] = {
+	 { "ACPILevel_CgSpllFuncCntl", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_250[] = {
+	 { "ACPILevel_CgSpllFuncCntl2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_251[] = {
+	 { "ACPILevel_CgSpllFuncCntl3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_252[] = {
+	 { "ACPILevel_CgSpllFuncCntl4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_253[] = {
+	 { "ACPILevel_SpllSpreadSpectrum", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_254[] = {
+	 { "ACPILevel_SpllSpreadSpectrum2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_255[] = {
+	 { "ACPILevel_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_256[] = {
+	 { "ACPILevel_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_257[] = {
+	 { "UvdLevel_0_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_258[] = {
+	 { "UvdLevel_0_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_259[] = {
+	 { "UvdLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_260[] = {
+	 { "UvdLevel_0_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_0_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_0_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_0_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_261[] = {
+	 { "UvdLevel_1_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_262[] = {
+	 { "UvdLevel_1_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_263[] = {
+	 { "UvdLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_264[] = {
+	 { "UvdLevel_1_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_1_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_1_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_1_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_265[] = {
+	 { "UvdLevel_2_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_266[] = {
+	 { "UvdLevel_2_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_267[] = {
+	 { "UvdLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_268[] = {
+	 { "UvdLevel_2_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_2_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_2_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_2_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_269[] = {
+	 { "UvdLevel_3_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_270[] = {
+	 { "UvdLevel_3_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_271[] = {
+	 { "UvdLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_272[] = {
+	 { "UvdLevel_3_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_3_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_3_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_3_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_273[] = {
+	 { "UvdLevel_4_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_274[] = {
+	 { "UvdLevel_4_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_275[] = {
+	 { "UvdLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_276[] = {
+	 { "UvdLevel_4_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_4_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_4_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_4_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_277[] = {
+	 { "UvdLevel_5_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_278[] = {
+	 { "UvdLevel_5_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_279[] = {
+	 { "UvdLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_280[] = {
+	 { "UvdLevel_5_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_5_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_5_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_5_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_281[] = {
+	 { "UvdLevel_6_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_282[] = {
+	 { "UvdLevel_6_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_283[] = {
+	 { "UvdLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_284[] = {
+	 { "UvdLevel_6_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_6_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_6_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_6_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_285[] = {
+	 { "UvdLevel_7_VclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_286[] = {
+	 { "UvdLevel_7_DclkFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_287[] = {
+	 { "UvdLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_288[] = {
+	 { "UvdLevel_7_padding_1", 0, 7, &umr_bitfield_default },
+	 { "UvdLevel_7_padding_0", 8, 15, &umr_bitfield_default },
+	 { "UvdLevel_7_DclkDivider", 16, 23, &umr_bitfield_default },
+	 { "UvdLevel_7_VclkDivider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_289[] = {
+	 { "VceLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_290[] = {
+	 { "VceLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_291[] = {
+	 { "VceLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_0_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_292[] = {
+	 { "VceLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_293[] = {
+	 { "VceLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_294[] = {
+	 { "VceLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_1_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_295[] = {
+	 { "VceLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_296[] = {
+	 { "VceLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_297[] = {
+	 { "VceLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_2_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_298[] = {
+	 { "VceLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_299[] = {
+	 { "VceLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_300[] = {
+	 { "VceLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_3_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_301[] = {
+	 { "VceLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_302[] = {
+	 { "VceLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_303[] = {
+	 { "VceLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_4_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_304[] = {
+	 { "VceLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_305[] = {
+	 { "VceLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_306[] = {
+	 { "VceLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_5_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_307[] = {
+	 { "VceLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_308[] = {
+	 { "VceLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_309[] = {
+	 { "VceLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_6_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_310[] = {
+	 { "VceLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_311[] = {
+	 { "VceLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_312[] = {
+	 { "VceLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "VceLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "VceLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "VceLevel_7_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_313[] = {
+	 { "AcpLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_314[] = {
+	 { "AcpLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_315[] = {
+	 { "AcpLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_0_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_316[] = {
+	 { "AcpLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_317[] = {
+	 { "AcpLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_318[] = {
+	 { "AcpLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_1_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_319[] = {
+	 { "AcpLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_320[] = {
+	 { "AcpLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_321[] = {
+	 { "AcpLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_2_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_322[] = {
+	 { "AcpLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_323[] = {
+	 { "AcpLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_324[] = {
+	 { "AcpLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_3_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_325[] = {
+	 { "AcpLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_326[] = {
+	 { "AcpLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_327[] = {
+	 { "AcpLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_4_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_328[] = {
+	 { "AcpLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_329[] = {
+	 { "AcpLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_330[] = {
+	 { "AcpLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_5_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_331[] = {
+	 { "AcpLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_332[] = {
+	 { "AcpLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_333[] = {
+	 { "AcpLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_6_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_334[] = {
+	 { "AcpLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_335[] = {
+	 { "AcpLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_336[] = {
+	 { "AcpLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "AcpLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "AcpLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "AcpLevel_7_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_337[] = {
+	 { "SamuLevel_0_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_338[] = {
+	 { "SamuLevel_0_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_0_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_339[] = {
+	 { "SamuLevel_0_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_0_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_0_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_0_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_340[] = {
+	 { "SamuLevel_1_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_341[] = {
+	 { "SamuLevel_1_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_1_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_342[] = {
+	 { "SamuLevel_1_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_1_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_1_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_1_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_343[] = {
+	 { "SamuLevel_2_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_344[] = {
+	 { "SamuLevel_2_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_2_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_345[] = {
+	 { "SamuLevel_2_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_2_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_2_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_2_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_346[] = {
+	 { "SamuLevel_3_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_347[] = {
+	 { "SamuLevel_3_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_3_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_348[] = {
+	 { "SamuLevel_3_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_3_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_3_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_3_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_349[] = {
+	 { "SamuLevel_4_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_350[] = {
+	 { "SamuLevel_4_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_4_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_351[] = {
+	 { "SamuLevel_4_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_4_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_4_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_4_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_352[] = {
+	 { "SamuLevel_5_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_353[] = {
+	 { "SamuLevel_5_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_5_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_354[] = {
+	 { "SamuLevel_5_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_5_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_5_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_5_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_355[] = {
+	 { "SamuLevel_6_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_356[] = {
+	 { "SamuLevel_6_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_6_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_357[] = {
+	 { "SamuLevel_6_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_6_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_6_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_6_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_358[] = {
+	 { "SamuLevel_7_Frequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_359[] = {
+	 { "SamuLevel_7_MinVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_7_MinVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_360[] = {
+	 { "SamuLevel_7_padding_2", 0, 7, &umr_bitfield_default },
+	 { "SamuLevel_7_padding_1", 8, 15, &umr_bitfield_default },
+	 { "SamuLevel_7_padding_0", 16, 23, &umr_bitfield_default },
+	 { "SamuLevel_7_Divider", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_361[] = {
+	 { "Ulv_CcPwrDynRm", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_362[] = {
+	 { "Ulv_CcPwrDynRm1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_363[] = {
+	 { "Ulv_VddcPhase", 0, 7, &umr_bitfield_default },
+	 { "Ulv_VddcOffsetVid", 8, 15, &umr_bitfield_default },
+	 { "Ulv_VddcOffset", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_364[] = {
+	 { "Ulv_Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_365[] = {
+	 { "SclkStepSize", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_366[] = {
+	 { "Smio_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_367[] = {
+	 { "Smio_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_368[] = {
+	 { "Smio_2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_369[] = {
+	 { "Smio_3", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_370[] = {
+	 { "Smio_4", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_371[] = {
+	 { "Smio_5", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_372[] = {
+	 { "Smio_6", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_373[] = {
+	 { "Smio_7", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_374[] = {
+	 { "Smio_8", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_375[] = {
+	 { "Smio_9", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_376[] = {
+	 { "Smio_10", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_377[] = {
+	 { "Smio_11", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_378[] = {
+	 { "Smio_12", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_379[] = {
+	 { "Smio_13", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_380[] = {
+	 { "Smio_14", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_381[] = {
+	 { "Smio_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_382[] = {
+	 { "Smio_16", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_383[] = {
+	 { "Smio_17", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_384[] = {
+	 { "Smio_18", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_385[] = {
+	 { "Smio_19", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_386[] = {
+	 { "Smio_20", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_387[] = {
+	 { "Smio_21", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_388[] = {
+	 { "Smio_22", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_389[] = {
+	 { "Smio_23", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_390[] = {
+	 { "Smio_24", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_391[] = {
+	 { "Smio_25", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_392[] = {
+	 { "Smio_26", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_393[] = {
+	 { "Smio_27", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_394[] = {
+	 { "Smio_28", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_395[] = {
+	 { "Smio_29", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_396[] = {
+	 { "Smio_30", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_397[] = {
+	 { "Smio_31", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_398[] = {
+	 { "SamuBootLevel", 0, 7, &umr_bitfield_default },
+	 { "AcpBootLevel", 8, 15, &umr_bitfield_default },
+	 { "VceBootLevel", 16, 23, &umr_bitfield_default },
+	 { "UvdBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_399[] = {
+	 { "GraphicsInterval", 0, 7, &umr_bitfield_default },
+	 { "GraphicsThermThrottleEnable", 8, 15, &umr_bitfield_default },
+	 { "GraphicsVoltageChangeEnable", 16, 23, &umr_bitfield_default },
+	 { "GraphicsBootLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_400[] = {
+	 { "TemperatureLimitHigh", 0, 15, &umr_bitfield_default },
+	 { "ThermalInterval", 16, 23, &umr_bitfield_default },
+	 { "VoltageInterval", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_401[] = {
+	 { "MemoryVoltageChangeEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryBootLevel", 8, 15, &umr_bitfield_default },
+	 { "TemperatureLimitLow", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_402[] = {
+	 { "MemoryThermThrottleEnable", 0, 7, &umr_bitfield_default },
+	 { "MemoryInterval", 8, 15, &umr_bitfield_default },
+	 { "BootMVdd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_403[] = {
+	 { "PhaseResponseTime", 0, 15, &umr_bitfield_default },
+	 { "VoltageResponseTime", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_404[] = {
+	 { "DTEMode", 0, 7, &umr_bitfield_default },
+	 { "DTEInterval", 8, 15, &umr_bitfield_default },
+	 { "PCIeGenInterval", 16, 23, &umr_bitfield_default },
+	 { "PCIeBootLinkLevel", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_405[] = {
+	 { "ThermGpio", 0, 7, &umr_bitfield_default },
+	 { "AcDcGpio", 8, 15, &umr_bitfield_default },
+	 { "VRHotGpio", 16, 23, &umr_bitfield_default },
+	 { "SVI2Enable", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_406[] = {
+	 { "PPM_TemperatureLimit", 0, 15, &umr_bitfield_default },
+	 { "PPM_PkgPwrLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_407[] = {
+	 { "TargetTdp", 0, 15, &umr_bitfield_default },
+	 { "DefaultTdp", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_408[] = {
+	 { "FpsLowThreshold", 0, 15, &umr_bitfield_default },
+	 { "FpsHighThreshold", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_409[] = {
+	 { "BAPMTI_R_0_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_410[] = {
+	 { "BAPMTI_R_1_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_0_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_411[] = {
+	 { "BAPMTI_R_1_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_1_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_412[] = {
+	 { "BAPMTI_R_2_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_413[] = {
+	 { "BAPMTI_R_3_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_2_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_414[] = {
+	 { "BAPMTI_R_3_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_3_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_415[] = {
+	 { "BAPMTI_R_4_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_416[] = {
+	 { "BAPMTI_RC_0_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_R_4_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_417[] = {
+	 { "BAPMTI_RC_0_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_0_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_418[] = {
+	 { "BAPMTI_RC_1_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_419[] = {
+	 { "BAPMTI_RC_2_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_1_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_420[] = {
+	 { "BAPMTI_RC_2_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_2_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_421[] = {
+	 { "BAPMTI_RC_3_1_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_0_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_422[] = {
+	 { "BAPMTI_RC_4_0_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_3_2_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_423[] = {
+	 { "BAPMTI_RC_4_2_0", 0, 15, &umr_bitfield_default },
+	 { "BAPMTI_RC_4_1_0", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_424[] = {
+	 { "GpuTjHyst", 0, 7, &umr_bitfield_default },
+	 { "GpuTjMax", 8, 15, &umr_bitfield_default },
+	 { "DTETjOffset", 16, 23, &umr_bitfield_default },
+	 { "DTEAmbientTempBase", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_425[] = {
+	 { "BootVoltage_Phases", 0, 7, &umr_bitfield_default },
+	 { "BootVoltage_VddGfx", 8, 15, &umr_bitfield_default },
+	 { "BootVoltage_Vddci", 16, 23, &umr_bitfield_default },
+	 { "BootVoltage_Vddc", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_426[] = {
+	 { "BAPM_TEMP_GRADIENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_427[] = {
+	 { "LowSclkInterruptThreshold", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_428[] = {
+	 { "VddGfxReChkWait", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_429[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_1", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_padding_0", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_maxVID", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_minVID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_430[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_3", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_2", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_1", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_431[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_7", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_6", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_5", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_0_setting_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_432[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_1", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_padding_0", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_maxVID", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_minVID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_433[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_3", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_2", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_1", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_434[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_7", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_6", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_5", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_1_setting_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_435[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_1", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_padding_0", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_maxVID", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_minVID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_436[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_3", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_2", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_1", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_437[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_7", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_6", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_5", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_2_setting_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_438[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_1", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_padding_0", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_maxVID", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_minVID", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_439[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_3", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_2", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_1", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDPM_TABLE_440[] = {
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_7", 0, 7, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_6", 8, 15, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_5", 16, 23, &umr_bitfield_default },
+	 { "ClockStretcherDataTable_ClockStretcherDataTableEntry_3_setting_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_28[] = {
+	 { "UcodeLoadStatus", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_1[] = {
+	 { "RefClockFrequency", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_2[] = {
+	 { "PmTimerPeriod", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_3[] = {
+	 { "FeatureEnables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_4[] = {
+	 { "PreVBlankGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_5[] = {
+	 { "VBlankTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_6[] = {
+	 { "TrainTimeGap", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_7[] = {
+	 { "MvddSwitchTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_8[] = {
+	 { "LongestAcpiTrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_9[] = {
+	 { "AcpiDelay", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_10[] = {
+	 { "G5TrainTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_11[] = {
+	 { "DelayMpllPwron", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_12[] = {
+	 { "VoltageChangeTimeout", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_13[] = {
+	 { "HandshakeDisables", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_14[] = {
+	 { "DisplayPhy4Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy3Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy2Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy1Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_15[] = {
+	 { "DisplayPhy8Config", 0, 7, &umr_bitfield_default },
+	 { "DisplayPhy7Config", 8, 15, &umr_bitfield_default },
+	 { "DisplayPhy6Config", 16, 23, &umr_bitfield_default },
+	 { "DisplayPhy5Config", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_16[] = {
+	 { "AverageGraphicsActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_17[] = {
+	 { "AverageMemoryActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_18[] = {
+	 { "AverageGioActivity", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_19[] = {
+	 { "PCIeDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "LClkDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "MClkDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "SClkDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_20[] = {
+	 { "VCEDpmEnabledLevels", 0, 7, &umr_bitfield_default },
+	 { "ACPDpmEnabledLevels", 8, 15, &umr_bitfield_default },
+	 { "SAMUDpmEnabledLevels", 16, 23, &umr_bitfield_default },
+	 { "UVDDpmEnabledLevels", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_21[] = {
+	 { "DRAM_LOG_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_22[] = {
+	 { "DRAM_LOG_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_23[] = {
+	 { "DRAM_LOG_PHY_ADDR_H", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_24[] = {
+	 { "DRAM_LOG_PHY_ADDR_L", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_25[] = {
+	 { "DRAM_LOG_BUFF_SIZE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_26[] = {
+	 { "UlvEnterCount", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_27[] = {
+	 { "UlvTime", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_29[] = {
+	 { "Reserved_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOFT_REGISTERS_TABLE_30[] = {
+	 { "Reserved_1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_1[] = {
+	 { "SviLoadLineOffsetVddC", 0, 7, &umr_bitfield_default },
+	 { "SviLoadLineTrimVddC", 8, 15, &umr_bitfield_default },
+	 { "SviLoadLineVddC", 16, 23, &umr_bitfield_default },
+	 { "SviLoadLineEn", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_2[] = {
+	 { "TDC_MAWt", 0, 7, &umr_bitfield_default },
+	 { "TDC_VDDC_ThrottleReleaseLimitPerc", 8, 15, &umr_bitfield_default },
+	 { "TDC_VDDC_PkgLimit", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_3[] = {
+	 { "Reserved", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureMax", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureMin", 16, 23, &umr_bitfield_default },
+	 { "TdcWaterfallCtl", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_4[] = {
+	 { "LPMLTemperatureScaler_3", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_2", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_1", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_5[] = {
+	 { "LPMLTemperatureScaler_7", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_6", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_5", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_6[] = {
+	 { "LPMLTemperatureScaler_11", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_10", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_9", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_7[] = {
+	 { "LPMLTemperatureScaler_15", 0, 7, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_14", 8, 15, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_13", 16, 23, &umr_bitfield_default },
+	 { "LPMLTemperatureScaler_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_8[] = {
+	 { "FuzzyFan_ErrorRateSetDelta", 0, 15, &umr_bitfield_default },
+	 { "FuzzyFan_ErrorSetDelta", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_9[] = {
+	 { "Reserved6", 0, 15, &umr_bitfield_default },
+	 { "FuzzyFan_PwmSetDelta", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_10[] = {
+	 { "GnbLPML_3", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_2", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_1", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_0", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_11[] = {
+	 { "GnbLPML_7", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_6", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_5", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_4", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_12[] = {
+	 { "GnbLPML_11", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_10", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_9", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_8", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_13[] = {
+	 { "GnbLPML_15", 0, 7, &umr_bitfield_default },
+	 { "GnbLPML_14", 8, 15, &umr_bitfield_default },
+	 { "GnbLPML_13", 16, 23, &umr_bitfield_default },
+	 { "GnbLPML_12", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_14[] = {
+	 { "Reserved1_1", 0, 7, &umr_bitfield_default },
+	 { "Reserved1_0", 8, 15, &umr_bitfield_default },
+	 { "GnbLPMLMinVid", 16, 23, &umr_bitfield_default },
+	 { "GnbLPMLMaxVid", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPM_FUSES_15[] = {
+	 { "BapmVddCBaseLeakageLoSidd", 0, 15, &umr_bitfield_default },
+	 { "BapmVddCBaseLeakageHiSidd", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_16[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_17[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_18[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_19[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_20[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_21[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_22[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_24[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_25[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_26[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_27[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_28[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_29[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_30[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_31[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_32[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_33[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_34[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_35[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_36[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_37[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_38[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_39[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_40[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_41[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_42[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_43[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_44[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_46[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_47[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_48[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_49[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_50[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_51[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_52[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_53[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_54[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_55[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_56[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_57[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_58[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_59[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_60[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_61[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_62[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_63[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_64[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_65[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_66[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_67[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_68[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_69[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_70[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_71[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_72[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_73[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_74[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_75[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_76[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_77[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_78[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_79[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_80[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_81[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_82[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_83[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_84[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_85[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_86[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_87[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_88[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_89[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_90[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_91[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_92[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_93[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_94[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_95[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_96[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_97[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_98[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_99[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_100[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_101[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_102[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_103[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_104[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_105[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_106[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_107[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_108[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_109[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_110[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_111[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_112[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_113[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_114[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_115[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_116[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_117[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_118[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_119[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_120[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_121[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_122[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_123[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_124[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_125[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_126[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_PM_STATUS_127[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_0[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_RESET_CNTL[] = {
+	 { "rst_reg", 0, 0, &umr_bitfield_default },
+	 { "srbm_soft_rst_override", 1, 1, &umr_bitfield_default },
+	 { "RegReset", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_0[] = {
+	 { "ck_disable", 0, 0, &umr_bitfield_default },
+	 { "auto_cg_en", 1, 1, &umr_bitfield_default },
+	 { "auto_cg_timeout", 8, 23, &umr_bitfield_default },
+	 { "cken", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_1[] = {
+	 { "auto_ck_disable", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_CLOCK_CNTL_2[] = {
+	 { "wake_on_irq", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_MISC_CNTL[] = {
+	 { "dma_no_outstanding", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SYSCON_MSG_ARG_0[] = {
+	 { "smc_msg_arg", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_PC_C[] = {
+	 { "smc_pc_c", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMC_SCRATCH9[] = {
+	 { "SCRATCH_VALUE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGCK_SMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_0[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_1[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_1[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_2[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_2[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_3[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_3[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_4[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_4[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_5[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_5[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_6[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_6[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_INDEX_7[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_DATA_7[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_IND_ACCESS_CNTL[] = {
+	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_1", 1, 1, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_2", 2, 2, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_3", 3, 3, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_4", 4, 4, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_5", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_6", 6, 6, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_7", 7, 7, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_8", 8, 8, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_9", 9, 9, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_10", 10, 10, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_11", 11, 11, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_12", 12, 12, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_13", 13, 13, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_14", 14, 14, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_11[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_0[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_0[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_1[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_1[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_2[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_2[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_3[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_3[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_4[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_4[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_5[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_5[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_6[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_6[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_7[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_7[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_0[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_1[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_2[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_3[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_4[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_5[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_6[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_7[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_8[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_8[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_9[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_9[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_10[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU0[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_10[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MESSAGE_11[] = {
+	 { "SMC_MSG", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU2[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_RESP_11[] = {
+	 { "SMC_RESP", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU3[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_8[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU4[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_9[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMC_MSG_ARG_10[] = {
+	 { "SMC_MSG_ARG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU6[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_UC_EVENTS[] = {
+	 { "RCU_TST_jpc_rep_req", 0, 0, &umr_bitfield_default },
+	 { "TST_RCU_jpc_rep_done", 1, 1, &umr_bitfield_default },
+	 { "drv_rst_mode", 2, 2, &umr_bitfield_default },
+	 { "SMU_DC_efuse_status_invalid", 3, 3, &umr_bitfield_default },
+	 { "TP_Tester", 6, 6, &umr_bitfield_default },
+	 { "boot_seq_done", 7, 7, &umr_bitfield_default },
+	 { "sclk_deep_sleep_exit", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_ACTIVE", 9, 9, &umr_bitfield_default },
+	 { "BREAK_PT2_ACTIVE", 10, 10, &umr_bitfield_default },
+	 { "FCH_HALT", 11, 11, &umr_bitfield_default },
+	 { "RCU_GIO_fch_lockdown", 13, 13, &umr_bitfield_default },
+	 { "INTERRUPTS_ENABLED", 16, 16, &umr_bitfield_default },
+	 { "RCU_DtmCnt0_Done", 17, 17, &umr_bitfield_default },
+	 { "RCU_DtmCnt1_Done", 18, 18, &umr_bitfield_default },
+	 { "RCU_DtmCnt2_Done", 19, 19, &umr_bitfield_default },
+	 { "irq31_sel", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_MISC_CTRL[] = {
+	 { "REG_DRV_RST_MODE", 1, 1, &umr_bitfield_default },
+	 { "REG_RCU_MEMREP_DIS", 3, 3, &umr_bitfield_default },
+	 { "REG_CC_FUSE_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "REG_SAMU_FUSE_DISABLE", 5, 5, &umr_bitfield_default },
+	 { "REG_CC_SRBM_RD_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "BREAK_PT1_DONE", 16, 16, &umr_bitfield_default },
+	 { "BREAK_PT2_DONE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_START", 22, 22, &umr_bitfield_default },
+	 { "RST_PULSE_WIDTH", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCU_VIRT_RESET_REQ[] = {
+	 { "VF", 0, 15, &umr_bitfield_default },
+	 { "PF", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_RCU_FUSES[] = {
+	 { "GPU_DIS", 1, 1, &umr_bitfield_default },
+	 { "DEBUG_DISABLE", 2, 2, &umr_bitfield_default },
+	 { "EFUSE_RD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "CG_RST_GLB_REQ_DIS", 5, 5, &umr_bitfield_default },
+	 { "DRV_RST_MODE", 6, 6, &umr_bitfield_default },
+	 { "ROM_DIS", 7, 7, &umr_bitfield_default },
+	 { "JPC_REP_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT1", 9, 9, &umr_bitfield_default },
+	 { "RCU_BREAK_POINT2", 10, 10, &umr_bitfield_default },
+	 { "SMU_IOC_MST_DISABLE", 14, 14, &umr_bitfield_default },
+	 { "FCH_LOCKOUT_ENABLE", 15, 15, &umr_bitfield_default },
+	 { "FCH_XFIRE_FILTER_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "XFIRE_DISABLE", 17, 17, &umr_bitfield_default },
+	 { "SAMU_FUSE_DISABLE", 18, 18, &umr_bitfield_default },
+	 { "BIF_RST_POLLING_DISABLE", 19, 19, &umr_bitfield_default },
+	 { "MEM_HARDREP_EN", 21, 21, &umr_bitfield_default },
+	 { "PCIE_INIT_DISABLE", 22, 22, &umr_bitfield_default },
+	 { "DSMU_DISABLE", 23, 23, &umr_bitfield_default },
+	 { "WRP_FUSE_VALID", 24, 24, &umr_bitfield_default },
+	 { "PHY_FUSE_VALID", 25, 25, &umr_bitfield_default },
+	 { "RCU_SPARE", 26, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_MISC_FUSES[] = {
+	 { "IOMMU_V2_DISABLE", 1, 1, &umr_bitfield_default },
+	 { "MinSClkDid", 2, 8, &umr_bitfield_default },
+	 { "MISC_SPARE", 9, 10, &umr_bitfield_default },
+	 { "PostResetGnbClkDid", 11, 17, &umr_bitfield_default },
+	 { "L2IMU_tn2_dtc_half", 18, 18, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_half", 19, 19, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_half", 20, 20, &umr_bitfield_default },
+	 { "L2IMU_tn2_pdc_half", 21, 21, &umr_bitfield_default },
+	 { "L2IMU_tn2_ptc_dis", 22, 22, &umr_bitfield_default },
+	 { "L2IMU_tn2_itc_dis", 23, 23, &umr_bitfield_default },
+	 { "VCE_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "IOC_IOMMU_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "GNB_SPARE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SCLK_VID_FUSES[] = {
+	 { "SClkVid0", 0, 7, &umr_bitfield_default },
+	 { "SClkVid1", 8, 15, &umr_bitfield_default },
+	 { "SClkVid2", 16, 23, &umr_bitfield_default },
+	 { "SClkVid3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOCCFG_FUSES[] = {
+	 { "NB_REV_ID", 1, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_GIO_IOC_FUSES[] = {
+	 { "IOC_FUSES", 1, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_SMU_TST_EFUSE1_MISC[] = {
+	 { "RF_RM_6_2", 1, 5, &umr_bitfield_default },
+	 { "RME", 6, 6, &umr_bitfield_default },
+	 { "MBIST_DISABLE", 7, 7, &umr_bitfield_default },
+	 { "HARD_REPAIR_DISABLE", 8, 8, &umr_bitfield_default },
+	 { "SOFT_REPAIR_DISABLE", 9, 9, &umr_bitfield_default },
+	 { "GPU_DIS", 10, 10, &umr_bitfield_default },
+	 { "SMS_PWRDWN_DISABLE", 11, 11, &umr_bitfield_default },
+	 { "CRBBMP1500_DISA", 12, 12, &umr_bitfield_default },
+	 { "CRBBMP1500_DISB", 13, 13, &umr_bitfield_default },
+	 { "RM_RF8", 14, 14, &umr_bitfield_default },
+	 { "DFT_SPARE1", 22, 22, &umr_bitfield_default },
+	 { "DFT_SPARE2", 23, 23, &umr_bitfield_default },
+	 { "DFT_SPARE3", 24, 24, &umr_bitfield_default },
+	 { "VCE_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "DCE_SCAN_DISABLE", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_TST_ID_STRAPS[] = {
+	 { "DEVICE_ID", 4, 19, &umr_bitfield_default },
+	 { "MAJOR_REV_ID", 20, 23, &umr_bitfield_default },
+	 { "MINOR_REV_ID", 24, 27, &umr_bitfield_default },
+	 { "ATI_REV_ID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_FCTRL_FUSES[] = {
+	 { "EXT_EFUSE_MACRO_PRESENT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_HARVEST_FUSES[] = {
+	 { "VCE_DISABLE", 1, 2, &umr_bitfield_default },
+	 { "UVD_DISABLE", 4, 4, &umr_bitfield_default },
+	 { "ACP_DISABLE", 6, 6, &umr_bitfield_default },
+	 { "DC_DISABLE", 8, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_EFUSE_0[] = {
+	 { "EFUSE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGENERAL_PWRMGT[] = {
+	 { "GLOBAL_PWRMGT_EN", 0, 0, &umr_bitfield_default },
+	 { "STATIC_PM_EN", 1, 1, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_DIS", 2, 2, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_TYPE", 3, 3, &umr_bitfield_default },
+	 { "SW_SMIO_INDEX", 6, 6, &umr_bitfield_default },
+	 { "LOW_VOLT_D2_ACPI", 8, 8, &umr_bitfield_default },
+	 { "LOW_VOLT_D3_ACPI", 9, 9, &umr_bitfield_default },
+	 { "VOLT_PWRMGT_EN", 10, 10, &umr_bitfield_default },
+	 { "SPARE11", 11, 11, &umr_bitfield_default },
+	 { "GPU_COUNTER_ACPI", 14, 14, &umr_bitfield_default },
+	 { "GPU_COUNTER_CLK", 15, 15, &umr_bitfield_default },
+	 { "GPU_COUNTER_OFF", 16, 16, &umr_bitfield_default },
+	 { "GPU_COUNTER_INTF_OFF", 17, 17, &umr_bitfield_default },
+	 { "SPARE18", 18, 18, &umr_bitfield_default },
+	 { "ACPI_D3_VID", 19, 20, &umr_bitfield_default },
+	 { "DYN_SPREAD_SPECTRUM_EN", 23, 23, &umr_bitfield_default },
+	 { "SPARE27", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCNB_PWRMGT_CNTL[] = {
+	 { "GNB_SLOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "GNB_SLOW", 2, 2, &umr_bitfield_default },
+	 { "FORCE_NB_PS1", 3, 3, &umr_bitfield_default },
+	 { "DPM_ENABLED", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_PWRMGT_CNTL[] = {
+	 { "SCLK_PWRMGT_OFF", 0, 0, &umr_bitfield_default },
+	 { "RESET_BUSY_CNT", 4, 4, &umr_bitfield_default },
+	 { "RESET_SCLK_CNT", 5, 5, &umr_bitfield_default },
+	 { "DYN_LIGHT_SLEEP_EN", 14, 14, &umr_bitfield_default },
+	 { "AUTO_SCLK_PULSE_SKIP", 15, 15, &umr_bitfield_default },
+	 { "LIGHT_SLEEP_COUNTER", 16, 20, &umr_bitfield_default },
+	 { "DYNAMIC_PM_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX[] = {
+	 { "TARGET_STATE", 0, 3, &umr_bitfield_default },
+	 { "CURRENT_STATE", 4, 7, &umr_bitfield_default },
+	 { "CURR_MCLK_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MCLK_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_SCLK_INDEX", 16, 20, &umr_bitfield_default },
+	 { "TARG_SCLK_INDEX", 21, 25, &umr_bitfield_default },
+	 { "CURR_LCLK_INDEX", 26, 28, &umr_bitfield_default },
+	 { "TARG_LCLK_INDEX", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_PCC_CONTROL[] = {
+	 { "PCC_POLARITY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_PCC_GPIO_SELECT[] = {
+	 { "GPIO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 3, &umr_bitfield_default },
+	 { "TST_REF_SEL", 4, 7, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 8, 14, &umr_bitfield_default },
+	 { "TST_RESET", 15, 15, &umr_bitfield_default },
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_STATIC_SCREEN_PARAMETER[] = {
+	 { "STATIC_SCREEN_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL[] = {
+	 { "DISP_GAP", 0, 1, &umr_bitfield_default },
+	 { "VBI_TIMER_COUNT", 4, 17, &umr_bitfield_default },
+	 { "VBI_TIMER_UNIT", 20, 22, &umr_bitfield_default },
+	 { "DISP_GAP_MCHG", 24, 25, &umr_bitfield_default },
+	 { "VBI_TIMER_DISABLE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACPI_CNTL[] = {
+	 { "SCLK_ACPI_DIV", 0, 6, &umr_bitfield_default },
+	 { "SCLK_CHANGE_SKIP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 16, 16, &umr_bitfield_default },
+	 { "SELF_REFRESH_MASK", 17, 17, &umr_bitfield_default },
+	 { "ALLOW_NBPSTATE_MASK", 18, 18, &umr_bitfield_default },
+	 { "BIF_BUSY_MASK", 19, 19, &umr_bitfield_default },
+	 { "UVD_BUSY_MASK", 20, 20, &umr_bitfield_default },
+	 { "MC0SRBM_BUSY_MASK", 21, 21, &umr_bitfield_default },
+	 { "MC1SRBM_BUSY_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_ALLOW_MASK", 23, 23, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 24, 24, &umr_bitfield_default },
+	 { "SELF_REFRESH_NLC_MASK", 25, 25, &umr_bitfield_default },
+	 { "FAST_EXIT_REQ_NBPSTATE", 26, 26, &umr_bitfield_default },
+	 { "DEEP_SLEEP_ENTRY_MODE", 27, 27, &umr_bitfield_default },
+	 { "MBUS2_ACTIVE_MASK", 28, 28, &umr_bitfield_default },
+	 { "VCE_BUSY_MASK", 29, 29, &umr_bitfield_default },
+	 { "AZ_BUSY_MASK", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RLC_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "HDP_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "ROM_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "PDMA_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "IDCT_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "SDMA_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_AZ_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK", 9, 9, &umr_bitfield_default },
+	 { "UVD_CG_MC_STAT_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "VCE_CG_MC_STAT_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "SAM_CG_MC_STAT_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "SAM_CG_STATUS_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 14, 14, &umr_bitfield_default },
+	 { "SHALLOW_DIV_ID", 21, 23, &umr_bitfield_default },
+	 { "INOUT_CUSHION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_MISC_CNTL[] = {
+	 { "DPM_DS_DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "DPM_SS_DIV_ID", 3, 5, &umr_bitfield_default },
+	 { "OCP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OCP_DS_DIV_ID", 17, 19, &umr_bitfield_default },
+	 { "OCP_SS_DIV_ID", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL3[] = {
+	 { "GRBM_0_SMU_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRBM_1_SMU_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "GRBM_2_SMU_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "GRBM_3_SMU_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "GRBM_4_SMU_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "GRBM_5_SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "GRBM_6_SMU_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "GRBM_7_SMU_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "GRBM_8_SMU_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "GRBM_9_SMU_BUSY_MASK", 9, 9, &umr_bitfield_default },
+	 { "GRBM_10_SMU_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "GRBM_11_SMU_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "GRBM_12_SMU_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "GRBM_13_SMU_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "GRBM_14_SMU_BUSY_MASK", 14, 14, &umr_bitfield_default },
+	 { "GRBM_15_SMU_BUSY_MASK", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_1[] = {
+	 { "CURR_VDDCI_INDEX", 0, 3, &umr_bitfield_default },
+	 { "TARG_VDDCI_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_MVDD_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MVDD_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_VDDC_INDEX", 16, 19, &umr_bitfield_default },
+	 { "TARG_VDDC_INDEX", 20, 23, &umr_bitfield_default },
+	 { "CURR_PCIE_INDEX", 24, 27, &umr_bitfield_default },
+	 { "TARG_PCIE_INDEX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ULV_PARAMETER[] = {
+	 { "ULV_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "ULV_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_0[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_1[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_2[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_3[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_4[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_5[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_6[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "SAM_FREQ_THROTTLING_VOTE_EN", 12, 12, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DISPLAY_GAP_CNTL2[] = {
+	 { "VBI_PREDICTION", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "L1IMU_SMU_IDLE_MASK", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_BIT3", 3, 3, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 4, 4, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE1_MASK", 6, 6, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE2_MASK", 7, 7, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE3_MASK", 8, 8, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE4_MASK", 9, 9, &umr_bitfield_default },
+	 { "L1IMUGPP_IDLE_MASK", 10, 10, &umr_bitfield_default },
+	 { "L1IMUGPPSB_IDLE_MASK", 11, 11, &umr_bitfield_default },
+	 { "L1IMUBIF_IDLE_MASK", 12, 12, &umr_bitfield_default },
+	 { "L1IMUINTGEN_IDLE_MASK", 13, 13, &umr_bitfield_default },
+	 { "L2IMU_IDLE_MASK", 14, 14, &umr_bitfield_default },
+	 { "ORB_IDLE_MASK", 15, 15, &umr_bitfield_default },
+	 { "ON_INB_WAKE_MASK", 16, 16, &umr_bitfield_default },
+	 { "ON_INB_WAKE_ACK_MASK", 17, 17, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_MASK", 18, 18, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_ACK_MASK", 19, 19, &umr_bitfield_default },
+	 { "DMAACTIVE_MASK", 20, 20, &umr_bitfield_default },
+	 { "RLC_SMU_GFXCLK_OFF_MASK", 21, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_CKS_ENABLE[] = {
+	 { "STRETCH_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "masterReset", 1, 1, &umr_bitfield_default },
+	 { "staticEnable", 2, 2, &umr_bitfield_default },
+	 { "IGNORE_DROOP_DETECT", 3, 3, &umr_bitfield_default },
+	 { "PCC_HAND_SHAKE_EN", 4, 4, &umr_bitfield_default },
+	 { "MET_CTRL_SEL", 5, 6, &umr_bitfield_default },
+	 { "DS_HAND_SHAKE_EN", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_CKS_CNTL[] = {
+	 { "CKS_BYPASS", 0, 0, &umr_bitfield_default },
+	 { "CKS_PCCEnable", 1, 1, &umr_bitfield_default },
+	 { "CKS_TEMP_COMP", 2, 2, &umr_bitfield_default },
+	 { "CKS_STRETCH_AMOUNT", 3, 6, &umr_bitfield_default },
+	 { "CKS_SKIP_PHASE_BYPASS", 7, 7, &umr_bitfield_default },
+	 { "CKS_SAMPLE_SIZE", 8, 11, &umr_bitfield_default },
+	 { "CKS_FSM_WAIT_CYCLES", 12, 15, &umr_bitfield_default },
+	 { "CKS_USE_FOR_LOW_FREQ", 16, 16, &umr_bitfield_default },
+	 { "CKS_NO_EXTRA_COARSE_STEP", 17, 17, &umr_bitfield_default },
+	 { "CKS_LDO_REFSEL", 18, 21, &umr_bitfield_default },
+	 { "DDT_DEBUS_SEL", 22, 22, &umr_bitfield_default },
+	 { "CKS_LDO_READY_COUNT_VAL", 23, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_PARAMETER[] = {
+	 { "VDDGFX_IDLE_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "VDDGFX_IDLE_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_CONTROL[] = {
+	 { "VDDGFX_IDLE_EN", 0, 0, &umr_bitfield_default },
+	 { "VDDGFX_IDLE_DETECT", 1, 1, &umr_bitfield_default },
+	 { "FORCE_VDDGFX_IDLE_EXIT", 2, 2, &umr_bitfield_default },
+	 { "SMC_VDDGFX_IDLE_STATE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_EXIT[] = {
+	 { "BIF_EXIT_REQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_CONTROL2[] = {
+	 { "DISP_TIMER_PULSE_WIDTH", 0, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS_SEL[] = {
+	 { "AvfsSel", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS_CNTL[] = {
+	 { "MmBusIn", 0, 7, &umr_bitfield_default },
+	 { "MmLclRdEn", 8, 8, &umr_bitfield_default },
+	 { "MmLclWrEn", 9, 9, &umr_bitfield_default },
+	 { "MmLclSz", 10, 11, &umr_bitfield_default },
+	 { "MmState", 12, 17, &umr_bitfield_default },
+	 { "PsmScanMode", 18, 18, &umr_bitfield_default },
+	 { "PsmGater", 19, 19, &umr_bitfield_default },
+	 { "PsmTrst", 20, 20, &umr_bitfield_default },
+	 { "PsmEn", 21, 21, &umr_bitfield_default },
+	 { "SkipPhaseEn", 22, 22, &umr_bitfield_default },
+	 { "Isolate", 23, 23, &umr_bitfield_default },
+	 { "AvfsRst", 24, 24, &umr_bitfield_default },
+	 { "PccIsolateEn", 25, 25, &umr_bitfield_default },
+	 { "DeepSleepIsolateEn", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_MIN_DIV[] = {
+	 { "FRACV", 0, 11, &umr_bitfield_default },
+	 { "INTV", 12, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MODE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER_DEBUG[] = {
+	 { "DISP_TIMER_INT_RUNNING", 0, 0, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 1, 1, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 2, 2, &umr_bitfield_default },
+	 { "DISP_TIMER_RUN_VAL", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER2_CONTROL[] = {
+	 { "DISP_TIMER_INT_COUNT", 0, 24, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MASK", 27, 27, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT_AK", 28, 28, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_TYPE", 29, 29, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_MODE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DISP_TIMER2_DEBUG[] = {
+	 { "DISP_TIMER_INT_RUNNING", 0, 0, &umr_bitfield_default },
+	 { "DISP_TIMER_INT_STAT", 1, 1, &umr_bitfield_default },
+	 { "DISP_TIMER_INT", 2, 2, &umr_bitfield_default },
+	 { "DISP_TIMER_RUN_VAL", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS0_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS1_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS2_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS3_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS4_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS5_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS6_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS7_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS8_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS9_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS10_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS11_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS12_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS13_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS14_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS15_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS16_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS17_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS18_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS19_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS20_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS21_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS22_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS23_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS24_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS25_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS26_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_AVFS27_CNTL_STATUS[] = {
+	 { "MmDatOut", 0, 7, &umr_bitfield_default },
+	 { "PsmTdo", 8, 8, &umr_bitfield_default },
+	 { "AlarmFlag", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_CTRL[] = {
+	 { "DPM_EVENT_SRC", 0, 2, &umr_bitfield_default },
+	 { "THERM_INC_CLK", 3, 3, &umr_bitfield_default },
+	 { "SPARE", 4, 13, &umr_bitfield_default },
+	 { "DIG_THERM_DPM", 14, 21, &umr_bitfield_default },
+	 { "RESERVED", 22, 24, &umr_bitfield_default },
+	 { "CTF_PAD_POLARITY", 25, 25, &umr_bitfield_default },
+	 { "CTF_PAD_EN", 26, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_STATUS[] = {
+	 { "SPARE", 0, 8, &umr_bitfield_default },
+	 { "FDO_PWM_DUTY", 9, 16, &umr_bitfield_default },
+	 { "THERM_ALERT", 17, 17, &umr_bitfield_default },
+	 { "GEN_STATUS", 18, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT[] = {
+	 { "DIG_THERM_CTF", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTH", 8, 15, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 16, 23, &umr_bitfield_default },
+	 { "THERM_INT_MASK", 24, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_CTRL[] = {
+	 { "TS_FILTER", 0, 3, &umr_bitfield_default },
+	 { "UNUSED", 4, 8, &umr_bitfield_default },
+	 { "THERMAL_RANGE_RST", 9, 9, &umr_bitfield_default },
+	 { "TEMP_SEL", 20, 27, &umr_bitfield_default },
+	 { "THM_READY_CLEAR", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MULT_THERMAL_STATUS[] = {
+	 { "ASIC_MAX_TEMP", 0, 8, &umr_bitfield_default },
+	 { "CTF_TEMP", 9, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_CTRL[] = {
+	 { "POWER_DOWN", 0, 0, &umr_bitfield_default },
+	 { "BGADJ", 1, 8, &umr_bitfield_default },
+	 { "BGADJ_MODE", 9, 9, &umr_bitfield_default },
+	 { "TMON_PAUSE", 10, 10, &umr_bitfield_default },
+	 { "INT_MEAS_EN", 11, 11, &umr_bitfield_default },
+	 { "DEBUG_MODE", 12, 12, &umr_bitfield_default },
+	 { "EN_CFG_SERDES", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_CTRL2[] = {
+	 { "RDIL_PRESENT", 0, 15, &umr_bitfield_default },
+	 { "RDIR_PRESENT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_CSR_WR[] = {
+	 { "CSR_WRITE", 0, 0, &umr_bitfield_default },
+	 { "CSR_READ", 1, 1, &umr_bitfield_default },
+	 { "CSR_ADDR", 2, 11, &umr_bitfield_default },
+	 { "WRITE_DATA", 12, 23, &umr_bitfield_default },
+	 { "SPARE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_CSR_RD[] = {
+	 { "READ_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL0[] = {
+	 { "FDO_STATIC_DUTY", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_DUTY", 8, 15, &umr_bitfield_default },
+	 { "FDO_PWM_MANUAL", 16, 16, &umr_bitfield_default },
+	 { "FDO_PWM_HYSTER", 17, 22, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP_EN", 23, 23, &umr_bitfield_default },
+	 { "FDO_PWM_RAMP", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL1[] = {
+	 { "FMAX_DUTY100", 0, 7, &umr_bitfield_default },
+	 { "FMIN_DUTY", 8, 15, &umr_bitfield_default },
+	 { "M", 16, 23, &umr_bitfield_default },
+	 { "RESERVED", 24, 29, &umr_bitfield_default },
+	 { "FDO_PWRDNB", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FDO_CTRL2[] = {
+	 { "TMIN", 0, 7, &umr_bitfield_default },
+	 { "FAN_SPINUP_TIME", 8, 10, &umr_bitfield_default },
+	 { "FDO_PWM_MODE", 11, 13, &umr_bitfield_default },
+	 { "TMIN_HYSTER", 14, 16, &umr_bitfield_default },
+	 { "TMAX", 17, 24, &umr_bitfield_default },
+	 { "TACH_PWM_RESP_RATE", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_CTRL[] = {
+	 { "EDGE_PER_REV", 0, 2, &umr_bitfield_default },
+	 { "TARGET_PERIOD", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_TACH_STATUS[] = {
+	 { "TACH_PERIOD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCC_THM_STRAPS0[] = {
+	 { "TMON0_BGADJ", 1, 8, &umr_bitfield_default },
+	 { "TMON1_BGADJ", 9, 16, &umr_bitfield_default },
+	 { "TMON_CMON_FUSE_SEL", 17, 17, &umr_bitfield_default },
+	 { "NUM_ACQ", 18, 20, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 21, 23, &umr_bitfield_default },
+	 { "TMON_CONFIG_SOURCE", 24, 24, &umr_bitfield_default },
+	 { "CTF_DISABLE", 25, 25, &umr_bitfield_default },
+	 { "TMON0_DISABLE", 26, 26, &umr_bitfield_default },
+	 { "TMON1_DISABLE", 27, 27, &umr_bitfield_default },
+	 { "TMON2_DISABLE", 28, 28, &umr_bitfield_default },
+	 { "TMON3_DISABLE", 29, 29, &umr_bitfield_default },
+	 { "UNUSED", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIL15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR0_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR1_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR2_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR3_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR4_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR5_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR6_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR7_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR8_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR9_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR10_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR11_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR12_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR13_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR14_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_RDIR15_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_INT_DATA[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+	 { "VALID", 11, 11, &umr_bitfield_default },
+	 { "TEMP", 12, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_DEBUG[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+	 { "DEBUG_Z", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_STATUS[] = {
+	 { "CURRENT_RDI", 0, 4, &umr_bitfield_default },
+	 { "MEAS_DONE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_STATUS[] = {
+	 { "CURRENT_RDI", 0, 4, &umr_bitfield_default },
+	 { "MEAS_DONE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON2_STATUS[] = {
+	 { "CURRENT_RDI", 0, 4, &umr_bitfield_default },
+	 { "MEAS_DONE", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
+	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
+	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
+	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
+	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC1_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC1_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
+	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
+	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
+	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC2_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC2_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
+	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
+	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
+	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC3_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC3_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
+	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
+	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_CNTL[] = {
+	 { "CPL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CPL_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "CPL_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "CPL_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_SEL[] = {
+	 { "CPL_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_VAL[] = {
+	 { "CPL_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC4_CNTL[] = {
+	 { "MC4_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC4_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC4_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC4_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC4_OVR_SEL[] = {
+	 { "MC4_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC4_OVR_VAL[] = {
+	 { "MC4_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC5_CNTL[] = {
+	 { "MC5_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC5_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC5_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC5_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC5_OVR_SEL[] = {
+	 { "MC5_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC5_OVR_VAL[] = {
+	 { "MC5_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC6_CNTL[] = {
+	 { "MC6_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC6_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC6_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC6_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC6_OVR_SEL[] = {
+	 { "MC6_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC6_OVR_VAL[] = {
+	 { "MC6_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC7_CNTL[] = {
+	 { "MC7_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC7_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC7_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC7_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC7_OVR_SEL[] = {
+	 { "MC7_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC7_OVR_VAL[] = {
+	 { "MC7_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_MCLK_FUSES[] = {
+	 { "StartupMClkDid", 0, 6, &umr_bitfield_default },
+	 { "MClkADCA", 7, 10, &umr_bitfield_default },
+	 { "MClkDDCA", 11, 12, &umr_bitfield_default },
+	 { "MClkDiDtWait", 13, 15, &umr_bitfield_default },
+	 { "MClkDiDtFloor", 16, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_CNTL[] = {
+	 { "DCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_DCLK_STATUS[] = {
+	 { "DCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "DCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_CNTL[] = {
+	 { "VCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_VCLK_STATUS[] = {
+	 { "VCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_CNTL[] = {
+	 { "ECLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ECLK_STATUS[] = {
+	 { "ECLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "ECLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACLK_CNTL[] = {
+	 { "ACLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "ACLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_DFS_BYPASS_CNTL[] = {
+	 { "BYPASSECLK", 0, 0, &umr_bitfield_default },
+	 { "BYPASSLCLK", 1, 1, &umr_bitfield_default },
+	 { "BYPASSEVCLK", 2, 2, &umr_bitfield_default },
+	 { "BYPASSDCLK", 3, 3, &umr_bitfield_default },
+	 { "BYPASSVCLK", 4, 4, &umr_bitfield_default },
+	 { "BYPASSDISPCLK", 5, 5, &umr_bitfield_default },
+	 { "BYPASSDPREFCLK", 6, 6, &umr_bitfield_default },
+	 { "BYPASSACLK", 7, 7, &umr_bitfield_default },
+	 { "BYPASSADIVCLK", 8, 8, &umr_bitfield_default },
+	 { "BYPASSPSPCLK", 9, 9, &umr_bitfield_default },
+	 { "BYPASSSAMCLK", 10, 10, &umr_bitfield_default },
+	 { "BYPASSSCLK", 11, 11, &umr_bitfield_default },
+	 { "USE_SPLL_BYPASS_EN", 12, 12, &umr_bitfield_default },
+	 { "BYPASSMCLK", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MCLK_CNTL[] = {
+	 { "MCLK_DIVIDER", 0, 6, &umr_bitfield_default },
+	 { "MCLK_DIR_CNTL_EN", 8, 8, &umr_bitfield_default },
+	 { "MCLK_DIR_CNTL_TOG", 9, 9, &umr_bitfield_default },
+	 { "MCLK_DIR_CNTL_DIVIDER", 10, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_MCLK_STATUS[] = {
+	 { "MCLK_STATUS", 0, 0, &umr_bitfield_default },
+	 { "MCLK_DIR_CNTL_DONETOG", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL[] = {
+	 { "SPLL_RESET", 0, 0, &umr_bitfield_default },
+	 { "SPLL_PWRON", 1, 1, &umr_bitfield_default },
+	 { "SPLL_DIVEN", 2, 2, &umr_bitfield_default },
+	 { "SPLL_BYPASS_EN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_BYPASS_THRU_DFS", 4, 4, &umr_bitfield_default },
+	 { "SPLL_REF_DIV", 5, 10, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_UPDATE", 11, 11, &umr_bitfield_default },
+	 { "SPLL_PDIV_A_EN", 12, 12, &umr_bitfield_default },
+	 { "SPLL_PDIV_A", 20, 26, &umr_bitfield_default },
+	 { "SPLL_DIVA_ACK", 27, 27, &umr_bitfield_default },
+	 { "SPLL_OTEST_LOCK_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_2[] = {
+	 { "SCLK_MUX_SEL", 0, 8, &umr_bitfield_default },
+	 { "SPLL_CTLREQ", 11, 11, &umr_bitfield_default },
+	 { "SPLL_BYPASS_CHG", 22, 22, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_CHG", 23, 23, &umr_bitfield_default },
+	 { "SPLL_RESET_CHG", 24, 24, &umr_bitfield_default },
+	 { "SPLL_BABY_STEP_CHG", 25, 25, &umr_bitfield_default },
+	 { "SCLK_MUX_UPDATE", 26, 26, &umr_bitfield_default },
+	 { "SPLL_UNLOCK_CLEAR", 27, 27, &umr_bitfield_default },
+	 { "SPLL_CLKF_UPDATE", 28, 28, &umr_bitfield_default },
+	 { "SPLL_TEST_UNLOCK_CLR", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_3[] = {
+	 { "SPLL_FB_DIV", 0, 25, &umr_bitfield_default },
+	 { "SPLL_DITHEN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_4[] = {
+	 { "SPLL_SCLK_TEST_SEL", 0, 3, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT_SEL", 5, 6, &umr_bitfield_default },
+	 { "SPLL_SCLK_EN", 7, 8, &umr_bitfield_default },
+	 { "SPLL_SPARE", 9, 11, &umr_bitfield_default },
+	 { "PCC_INC_DIV", 12, 18, &umr_bitfield_default },
+	 { "TEST_FRAC_BYPASS", 21, 21, &umr_bitfield_default },
+	 { "SPLL_ILOCK", 23, 23, &umr_bitfield_default },
+	 { "SPLL_FBCLK_SEL", 24, 24, &umr_bitfield_default },
+	 { "SPLL_VCTRLADC_EN", 25, 25, &umr_bitfield_default },
+	 { "SPLL_SCLK_EXT", 26, 27, &umr_bitfield_default },
+	 { "SPLL_SPARE_EXT", 28, 30, &umr_bitfield_default },
+	 { "SPLL_VTOI_BIAS_CNTL", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_5[] = {
+	 { "FBDIV_SSC_BYPASS", 0, 0, &umr_bitfield_default },
+	 { "RISEFBVCO_EN", 1, 1, &umr_bitfield_default },
+	 { "PFD_RESET_CNTRL", 2, 3, &umr_bitfield_default },
+	 { "RESET_TIMER", 4, 5, &umr_bitfield_default },
+	 { "FAST_LOCK_CNTRL", 6, 7, &umr_bitfield_default },
+	 { "FAST_LOCK_EN", 8, 8, &umr_bitfield_default },
+	 { "RESET_ANTI_MUX", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_6[] = {
+	 { "SCLKMUX0_CLKOFF_CNT", 0, 7, &umr_bitfield_default },
+	 { "SCLKMUX1_CLKOFF_CNT", 8, 15, &umr_bitfield_default },
+	 { "SPLL_VCTL_EN", 16, 16, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_IN", 17, 20, &umr_bitfield_default },
+	 { "SPLL_VCTL_CNTRL_OUT", 21, 24, &umr_bitfield_default },
+	 { "SPLL_LF_CNTR", 25, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_FUNC_CNTL_7[] = {
+	 { "SPLL_BW_CNTRL", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPLL_CNTL_MODE[] = {
+	 { "SPLL_SW_DIR_CONTROL", 0, 0, &umr_bitfield_default },
+	 { "SPLL_LEGACY_PDIV", 1, 1, &umr_bitfield_default },
+	 { "SPLL_TEST", 2, 2, &umr_bitfield_default },
+	 { "SPLL_FASTEN", 3, 3, &umr_bitfield_default },
+	 { "SPLL_ENSAT", 4, 4, &umr_bitfield_default },
+	 { "SPLL_TEST_CLK_EXT_DIV", 10, 11, &umr_bitfield_default },
+	 { "SPLL_CTLREQ_DLY_CNT", 12, 19, &umr_bitfield_default },
+	 { "SPLL_RESET_EN", 28, 28, &umr_bitfield_default },
+	 { "SPLL_VCO_MODE", 29, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM[] = {
+	 { "SSEN", 0, 0, &umr_bitfield_default },
+	 { "CLKS", 4, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_SPLL_SPREAD_SPECTRUM_2[] = {
+	 { "CLKV", 0, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMPLL_BYPASSCLK_SEL[] = {
+	 { "MPLL_CLKOUT_SEL", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL[] = {
+	 { "XTALIN_DIVIDE", 1, 1, &umr_bitfield_default },
+	 { "BCLK_AS_XCLK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_2[] = {
+	 { "ENABLE_XCLK", 0, 0, &umr_bitfield_default },
+	 { "FORCE_BIF_REFCLK_EN", 3, 3, &umr_bitfield_default },
+	 { "MUX_TCLK_TO_XCLK", 8, 8, &umr_bitfield_default },
+	 { "XO_IN_OSCIN_EN", 14, 14, &umr_bitfield_default },
+	 { "XO_IN_ICORE_CLK_OE", 15, 15, &umr_bitfield_default },
+	 { "XO_IN_CML_RXEN", 16, 16, &umr_bitfield_default },
+	 { "XO_IN_BIDIR_CML_OE", 17, 17, &umr_bitfield_default },
+	 { "XO_IN2_OSCIN_EN", 18, 18, &umr_bitfield_default },
+	 { "XO_IN2_ICORE_CLK_OE", 19, 19, &umr_bitfield_default },
+	 { "XO_IN2_CML_RXEN", 20, 20, &umr_bitfield_default },
+	 { "XO_IN2_BIDIR_CML_OE", 21, 21, &umr_bitfield_default },
+	 { "CML_CTRL", 22, 23, &umr_bitfield_default },
+	 { "CLK_SPARE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_CLK_CNTL[] = {
+	 { "CMON_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "TMON_CLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "CTF_CLK_SHUTOFF_EN", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_CLK_CTRL[] = {
+	 { "DEEP_SLEEP_CLK_SEL", 0, 7, &umr_bitfield_default },
+	 { "ZCLK_SEL", 8, 15, &umr_bitfield_default },
+	 { "DFT_SMS_PG_CLK_SEL", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL[] = {
+	 { "TST_SRC_SEL", 0, 4, &umr_bitfield_default },
+	 { "TST_REF_SEL", 5, 9, &umr_bitfield_default },
+	 { "REF_TEST_COUNT", 10, 16, &umr_bitfield_default },
+	 { "TST_RESET", 17, 17, &umr_bitfield_default },
+	 { "TST_CLK_SEL_MODE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_PLL_TEST_CNTL_2[] = {
+	 { "TEST_COUNT", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGCK_ADFS_CLK_BYPASS_CNTL1[] = {
+	 { "ECLK_BYPASS_CNTL", 0, 2, &umr_bitfield_default },
+	 { "SCLK_BYPASS_CNTL", 3, 5, &umr_bitfield_default },
+	 { "LCLK_BYPASS_CNTL", 6, 8, &umr_bitfield_default },
+	 { "DCLK_BYPASS_CNTL", 9, 11, &umr_bitfield_default },
+	 { "VCLK_BYPASS_CNTL", 12, 14, &umr_bitfield_default },
+	 { "DISPCLK_BYPASS_CNTL", 15, 17, &umr_bitfield_default },
+	 { "DRREFCLK_BYPASS_CNTL", 18, 20, &umr_bitfield_default },
+	 { "ACLK_BYPASS_CNTL", 21, 23, &umr_bitfield_default },
+	 { "SAMCLK_BYPASS_CNTL", 24, 26, &umr_bitfield_default },
+	 { "ACLK_DIV_BYPASS_CNTL", 27, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_CLKPIN_CNTL_DC[] = {
+	 { "OSC_EN", 0, 0, &umr_bitfield_default },
+	 { "XTL_LOW_GAIN", 1, 2, &umr_bitfield_default },
+	 { "XTL_XOCLK_DRV_R_EN", 9, 9, &umr_bitfield_default },
+	 { "XTALIN_SEL", 10, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_CNTL[] = {
+	 { "SCK_OVERWRITE", 1, 1, &umr_bitfield_default },
+	 { "CLOCK_GATING_EN", 2, 2, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_SETUP_TIME", 8, 15, &umr_bitfield_default },
+	 { "CSB_ACTIVE_TO_SCK_HOLD_TIME", 16, 23, &umr_bitfield_default },
+	 { "SCK_PRESCALE_REFCLK", 24, 27, &umr_bitfield_default },
+	 { "SCK_PRESCALE_CRYSTAL_CLK", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPAGE_MIRROR_CNTL[] = {
+	 { "PAGE_MIRROR_BASE_ADDR", 0, 23, &umr_bitfield_default },
+	 { "PAGE_MIRROR_INVALIDATE", 24, 24, &umr_bitfield_default },
+	 { "PAGE_MIRROR_ENABLE", 25, 25, &umr_bitfield_default },
+	 { "PAGE_MIRROR_USAGE", 26, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_STATUS[] = {
+	 { "ROM_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCGTT_ROM_CLK_CTRL0[] = {
+	 { "ON_DELAY", 0, 3, &umr_bitfield_default },
+	 { "OFF_HYSTERESIS", 4, 11, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE1", 30, 30, &umr_bitfield_default },
+	 { "SOFT_OVERRIDE0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_INDEX[] = {
+	 { "ROM_INDEX", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_DATA[] = {
+	 { "ROM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_START[] = {
+	 { "ROM_START", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_CNTL[] = {
+	 { "DATA_SIZE", 0, 15, &umr_bitfield_default },
+	 { "COMMAND_SIZE", 16, 17, &umr_bitfield_default },
+	 { "ROM_SW_RETURN_DATA_ENABLE", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_STATUS[] = {
+	 { "ROM_SW_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_COMMAND[] = {
+	 { "ROM_SW_INSTRUCTION", 0, 7, &umr_bitfield_default },
+	 { "ROM_SW_ADDRESS", 8, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_1[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_2[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_3[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_4[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_5[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_6[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_7[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_8[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_9[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_10[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_11[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_12[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_13[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_14[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_15[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_16[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_17[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_18[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_19[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_20[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_21[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_22[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_23[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_24[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_25[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_26[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_27[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_28[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_29[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_30[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_31[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_32[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_33[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_34[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_35[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_36[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_37[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_38[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_39[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_40[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_41[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_42[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_43[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_44[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_45[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_46[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_47[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_48[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_49[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_50[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_51[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_52[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_53[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_54[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_55[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_56[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_57[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_58[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_59[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_60[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_61[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_62[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_63[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixROM_SW_DATA_64[] = {
+	 { "ROM_SW_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU7[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU8[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_ENA[] = {
+	 { "THERM_INTH_SET", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_SET", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_SET", 2, 2, &umr_bitfield_default },
+	 { "THERM_INTH_CLR", 3, 3, &umr_bitfield_default },
+	 { "THERM_INTL_CLR", 4, 4, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CLR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_CTRL[] = {
+	 { "DIG_THERM_INTH", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 8, 15, &umr_bitfield_default },
+	 { "GNB_TEMP_THRESHOLD", 16, 23, &umr_bitfield_default },
+	 { "THERM_INTH_MASK", 24, 24, &umr_bitfield_default },
+	 { "THERM_INTL_MASK", 25, 25, &umr_bitfield_default },
+	 { "THERM_TRIGGER_MASK", 26, 26, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_MASK", 27, 27, &umr_bitfield_default },
+	 { "THERM_GNB_HW_ENA", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_THERMAL_INT_STATUS[] = {
+	 { "THERM_INTH_DETECT", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_DETECT", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_DETECT", 2, 2, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_DETECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU9[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU10[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU11[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU12[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU13[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU14[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU15[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_MAIN_PLL_OP_FREQ[] = {
+	 { "PLL_OP_FREQ", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_STATUS[] = {
+	 { "SMU_DONE", 0, 0, &umr_bitfield_default },
+	 { "SMU_PASS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_FIRMWARE[] = {
+	 { "SMU_IN_PROG", 0, 0, &umr_bitfield_default },
+	 { "SMU_RD_DONE", 1, 2, &umr_bitfield_default },
+	 { "SMU_SRAM_RD_BLOCK_EN", 3, 3, &umr_bitfield_default },
+	 { "SMU_SRAM_WR_BLOCK_EN", 4, 4, &umr_bitfield_default },
+	 { "SMU_counter", 8, 11, &umr_bitfield_default },
+	 { "SMU_MODE", 16, 16, &umr_bitfield_default },
+	 { "SMU_SEL", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_INPUT_DATA[] = {
+	 { "START_ADDR", 0, 30, &umr_bitfield_default },
+	 { "AUTO_START", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_OVRD_CU[] = {
+	 { "OVRRD_SELECT", 0, 15, &umr_bitfield_default },
+	 { "OVRRD_VALUE", 16, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/smu713_regs.i b/src/lib/ip/smu713_regs.i
new file mode 100644
index 0000000..61a8af0
--- /dev/null
+++ b/src/lib/ip/smu713_regs.i
@@ -0,0 +1,1198 @@
+	{ "mmGPIOPAD_SW_INT_STAT", REG_MMIO, 0x180, &mmGPIOPAD_SW_INT_STAT[0], sizeof(mmGPIOPAD_SW_INT_STAT)/sizeof(mmGPIOPAD_SW_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_STRENGTH", REG_MMIO, 0x181, &mmGPIOPAD_STRENGTH[0], sizeof(mmGPIOPAD_STRENGTH)/sizeof(mmGPIOPAD_STRENGTH[0]), 0, 0 },
+	{ "mmGPIOPAD_MASK", REG_MMIO, 0x182, &mmGPIOPAD_MASK[0], sizeof(mmGPIOPAD_MASK)/sizeof(mmGPIOPAD_MASK[0]), 0, 0 },
+	{ "mmGPIOPAD_A", REG_MMIO, 0x183, &mmGPIOPAD_A[0], sizeof(mmGPIOPAD_A)/sizeof(mmGPIOPAD_A[0]), 0, 0 },
+	{ "mmGPIOPAD_EN", REG_MMIO, 0x184, &mmGPIOPAD_EN[0], sizeof(mmGPIOPAD_EN)/sizeof(mmGPIOPAD_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_Y", REG_MMIO, 0x185, &mmGPIOPAD_Y[0], sizeof(mmGPIOPAD_Y)/sizeof(mmGPIOPAD_Y[0]), 0, 0 },
+	{ "mmGPIOPAD_PINSTRAPS", REG_MMIO, 0x186, &mmGPIOPAD_PINSTRAPS[0], sizeof(mmGPIOPAD_PINSTRAPS)/sizeof(mmGPIOPAD_PINSTRAPS[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_EN", REG_MMIO, 0x187, &mmGPIOPAD_INT_STAT_EN[0], sizeof(mmGPIOPAD_INT_STAT_EN)/sizeof(mmGPIOPAD_INT_STAT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT", REG_MMIO, 0x188, &mmGPIOPAD_INT_STAT[0], sizeof(mmGPIOPAD_INT_STAT)/sizeof(mmGPIOPAD_INT_STAT[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_STAT_AK", REG_MMIO, 0x189, &mmGPIOPAD_INT_STAT_AK[0], sizeof(mmGPIOPAD_INT_STAT_AK)/sizeof(mmGPIOPAD_INT_STAT_AK[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_EN", REG_MMIO, 0x18a, &mmGPIOPAD_INT_EN[0], sizeof(mmGPIOPAD_INT_EN)/sizeof(mmGPIOPAD_INT_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_TYPE", REG_MMIO, 0x18b, &mmGPIOPAD_INT_TYPE[0], sizeof(mmGPIOPAD_INT_TYPE)/sizeof(mmGPIOPAD_INT_TYPE[0]), 0, 0 },
+	{ "mmGPIOPAD_INT_POLARITY", REG_MMIO, 0x18c, &mmGPIOPAD_INT_POLARITY[0], sizeof(mmGPIOPAD_INT_POLARITY)/sizeof(mmGPIOPAD_INT_POLARITY[0]), 0, 0 },
+	{ "mmGPIOPAD_EXTERN_TRIG_CNTL", REG_MMIO, 0x18d, &mmGPIOPAD_EXTERN_TRIG_CNTL[0], sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL)/sizeof(mmGPIOPAD_EXTERN_TRIG_CNTL[0]), 0, 0 },
+	{ "mmGPIOPAD_RCVR_SEL", REG_MMIO, 0x191, &mmGPIOPAD_RCVR_SEL[0], sizeof(mmGPIOPAD_RCVR_SEL)/sizeof(mmGPIOPAD_RCVR_SEL[0]), 0, 0 },
+	{ "mmGPIOPAD_PU_EN", REG_MMIO, 0x192, &mmGPIOPAD_PU_EN[0], sizeof(mmGPIOPAD_PU_EN)/sizeof(mmGPIOPAD_PU_EN[0]), 0, 0 },
+	{ "mmGPIOPAD_PD_EN", REG_MMIO, 0x193, &mmGPIOPAD_PD_EN[0], sizeof(mmGPIOPAD_PD_EN)/sizeof(mmGPIOPAD_PD_EN[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_0", REG_MMIO, 0x1a6, &mmSMU_IND_INDEX_0[0], sizeof(mmSMU_IND_INDEX_0)/sizeof(mmSMU_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_0", REG_MMIO, 0x1a7, &mmSMU_IND_DATA_0[0], sizeof(mmSMU_IND_DATA_0)/sizeof(mmSMU_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_1", REG_MMIO, 0x1a8, &mmSMU_IND_INDEX_1[0], sizeof(mmSMU_IND_INDEX_1)/sizeof(mmSMU_IND_INDEX_1[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_1", REG_MMIO, 0x1a9, &mmSMU_IND_DATA_1[0], sizeof(mmSMU_IND_DATA_1)/sizeof(mmSMU_IND_DATA_1[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_2", REG_MMIO, 0x1aa, &mmSMU_IND_INDEX_2[0], sizeof(mmSMU_IND_INDEX_2)/sizeof(mmSMU_IND_INDEX_2[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_2", REG_MMIO, 0x1ab, &mmSMU_IND_DATA_2[0], sizeof(mmSMU_IND_DATA_2)/sizeof(mmSMU_IND_DATA_2[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_11", REG_MMIO, 0x1AC, NULL, 0, 0, 0 },
+	{ "mmSMU_IND_INDEX_3", REG_MMIO, 0x1ac, &mmSMU_IND_INDEX_3[0], sizeof(mmSMU_IND_INDEX_3)/sizeof(mmSMU_IND_INDEX_3[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_11", REG_MMIO, 0x1AD, NULL, 0, 0, 0 },
+	{ "mmSMU_IND_DATA_3", REG_MMIO, 0x1ad, &mmSMU_IND_DATA_3[0], sizeof(mmSMU_IND_DATA_3)/sizeof(mmSMU_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_4", REG_MMIO, 0x1ae, &mmSMU_IND_INDEX_4[0], sizeof(mmSMU_IND_INDEX_4)/sizeof(mmSMU_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_4", REG_MMIO, 0x1af, &mmSMU_IND_DATA_4[0], sizeof(mmSMU_IND_DATA_4)/sizeof(mmSMU_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_5", REG_MMIO, 0x1b0, &mmSMU_IND_INDEX_5[0], sizeof(mmSMU_IND_INDEX_5)/sizeof(mmSMU_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_5", REG_MMIO, 0x1b1, &mmSMU_IND_DATA_5[0], sizeof(mmSMU_IND_DATA_5)/sizeof(mmSMU_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_6", REG_MMIO, 0x1b2, &mmSMU_IND_INDEX_6[0], sizeof(mmSMU_IND_INDEX_6)/sizeof(mmSMU_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_6", REG_MMIO, 0x1b3, &mmSMU_IND_DATA_6[0], sizeof(mmSMU_IND_DATA_6)/sizeof(mmSMU_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMU_IND_INDEX_7", REG_MMIO, 0x1b4, &mmSMU_IND_INDEX_7[0], sizeof(mmSMU_IND_INDEX_7)/sizeof(mmSMU_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMU_IND_DATA_7", REG_MMIO, 0x1b5, &mmSMU_IND_DATA_7[0], sizeof(mmSMU_IND_DATA_7)/sizeof(mmSMU_IND_DATA_7[0]), 0, 0 },
+	{ "mmCG_FPS_CNT", REG_MMIO, 0x1b6, &mmCG_FPS_CNT[0], sizeof(mmCG_FPS_CNT)/sizeof(mmCG_FPS_CNT[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_0", REG_SMC, 0x32, &ixGC_CAC_WEIGHT_CU_0[0], sizeof(ixGC_CAC_WEIGHT_CU_0)/sizeof(ixGC_CAC_WEIGHT_CU_0[0]), 0, 0 },
+	{ "mmGC_CAC_CGTT_CLK_CTRL", REG_MMIO, 0x3292, &mmGC_CAC_CGTT_CLK_CTRL[0], sizeof(mmGC_CAC_CGTT_CLK_CTRL)/sizeof(mmGC_CAC_CGTT_CLK_CTRL[0]), 0, 0 },
+	{ "mmSE_CAC_CGTT_CLK_CTRL", REG_MMIO, 0x3293, &mmSE_CAC_CGTT_CLK_CTRL[0], sizeof(mmSE_CAC_CGTT_CLK_CTRL)/sizeof(mmSE_CAC_CGTT_CLK_CTRL[0]), 0, 0 },
+	{ "mmGC_CAC_LKG_AGGR_LOWER", REG_MMIO, 0x3296, &mmGC_CAC_LKG_AGGR_LOWER[0], sizeof(mmGC_CAC_LKG_AGGR_LOWER)/sizeof(mmGC_CAC_LKG_AGGR_LOWER[0]), 0, 0 },
+	{ "mmGC_CAC_LKG_AGGR_UPPER", REG_MMIO, 0x3297, &mmGC_CAC_LKG_AGGR_UPPER[0], sizeof(mmGC_CAC_LKG_AGGR_UPPER)/sizeof(mmGC_CAC_LKG_AGGR_UPPER[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_1", REG_SMC, 0x33, &ixGC_CAC_WEIGHT_CU_1[0], sizeof(ixGC_CAC_WEIGHT_CU_1)/sizeof(ixGC_CAC_WEIGHT_CU_1[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_2", REG_SMC, 0x34, &ixGC_CAC_WEIGHT_CU_2[0], sizeof(ixGC_CAC_WEIGHT_CU_2)/sizeof(ixGC_CAC_WEIGHT_CU_2[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_3", REG_SMC, 0x35, &ixGC_CAC_WEIGHT_CU_3[0], sizeof(ixGC_CAC_WEIGHT_CU_3)/sizeof(ixGC_CAC_WEIGHT_CU_3[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_4", REG_SMC, 0x36, &ixGC_CAC_WEIGHT_CU_4[0], sizeof(ixGC_CAC_WEIGHT_CU_4)/sizeof(ixGC_CAC_WEIGHT_CU_4[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_5", REG_SMC, 0x37, &ixGC_CAC_WEIGHT_CU_5[0], sizeof(ixGC_CAC_WEIGHT_CU_5)/sizeof(ixGC_CAC_WEIGHT_CU_5[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_6", REG_SMC, 0x38, &ixGC_CAC_WEIGHT_CU_6[0], sizeof(ixGC_CAC_WEIGHT_CU_6)/sizeof(ixGC_CAC_WEIGHT_CU_6[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_7", REG_SMC, 0x39, &ixGC_CAC_WEIGHT_CU_7[0], sizeof(ixGC_CAC_WEIGHT_CU_7)/sizeof(ixGC_CAC_WEIGHT_CU_7[0]), 0, 0 },
+	{ "ixFIRMWARE_FLAGS", REG_SMC, 0x3f000, &ixFIRMWARE_FLAGS[0], sizeof(ixFIRMWARE_FLAGS)/sizeof(ixFIRMWARE_FLAGS[0]), 0, 0 },
+	{ "ixTDC_STATUS", REG_SMC, 0x3f004, &ixTDC_STATUS[0], sizeof(ixTDC_STATUS)/sizeof(ixTDC_STATUS[0]), 0, 0 },
+	{ "ixTDC_MV_AVERAGE", REG_SMC, 0x3f008, &ixTDC_MV_AVERAGE[0], sizeof(ixTDC_MV_AVERAGE)/sizeof(ixTDC_MV_AVERAGE[0]), 0, 0 },
+	{ "ixTDC_VRM_LIMIT", REG_SMC, 0x3f00c, &ixTDC_VRM_LIMIT[0], sizeof(ixTDC_VRM_LIMIT)/sizeof(ixTDC_VRM_LIMIT[0]), 0, 0 },
+	{ "ixFEATURE_STATUS", REG_SMC, 0x3f010, &ixFEATURE_STATUS[0], sizeof(ixFEATURE_STATUS)/sizeof(ixFEATURE_STATUS[0]), 0, 0 },
+	{ "ixENTITY_TEMPERATURES_1", REG_SMC, 0x3f014, &ixENTITY_TEMPERATURES_1[0], sizeof(ixENTITY_TEMPERATURES_1)/sizeof(ixENTITY_TEMPERATURES_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_1", REG_SMC, 0x3f018, &ixMCARB_DRAM_TIMING_TABLE_1[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_1)/sizeof(ixMCARB_DRAM_TIMING_TABLE_1[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_2", REG_SMC, 0x3f01c, &ixMCARB_DRAM_TIMING_TABLE_2[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_2)/sizeof(ixMCARB_DRAM_TIMING_TABLE_2[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_3", REG_SMC, 0x3f020, &ixMCARB_DRAM_TIMING_TABLE_3[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_3)/sizeof(ixMCARB_DRAM_TIMING_TABLE_3[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_4", REG_SMC, 0x3f024, &ixMCARB_DRAM_TIMING_TABLE_4[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_4)/sizeof(ixMCARB_DRAM_TIMING_TABLE_4[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_5", REG_SMC, 0x3f028, &ixMCARB_DRAM_TIMING_TABLE_5[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_5)/sizeof(ixMCARB_DRAM_TIMING_TABLE_5[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_6", REG_SMC, 0x3f02c, &ixMCARB_DRAM_TIMING_TABLE_6[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_6)/sizeof(ixMCARB_DRAM_TIMING_TABLE_6[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_7", REG_SMC, 0x3f030, &ixMCARB_DRAM_TIMING_TABLE_7[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_7)/sizeof(ixMCARB_DRAM_TIMING_TABLE_7[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_8", REG_SMC, 0x3f034, &ixMCARB_DRAM_TIMING_TABLE_8[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_8)/sizeof(ixMCARB_DRAM_TIMING_TABLE_8[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_9", REG_SMC, 0x3f038, &ixMCARB_DRAM_TIMING_TABLE_9[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_9)/sizeof(ixMCARB_DRAM_TIMING_TABLE_9[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_10", REG_SMC, 0x3f03c, &ixMCARB_DRAM_TIMING_TABLE_10[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_10)/sizeof(ixMCARB_DRAM_TIMING_TABLE_10[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_11", REG_SMC, 0x3f040, &ixMCARB_DRAM_TIMING_TABLE_11[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_11)/sizeof(ixMCARB_DRAM_TIMING_TABLE_11[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_12", REG_SMC, 0x3f044, &ixMCARB_DRAM_TIMING_TABLE_12[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_12)/sizeof(ixMCARB_DRAM_TIMING_TABLE_12[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_13", REG_SMC, 0x3f048, &ixMCARB_DRAM_TIMING_TABLE_13[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_13)/sizeof(ixMCARB_DRAM_TIMING_TABLE_13[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_14", REG_SMC, 0x3f04c, &ixMCARB_DRAM_TIMING_TABLE_14[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_14)/sizeof(ixMCARB_DRAM_TIMING_TABLE_14[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_15", REG_SMC, 0x3f050, &ixMCARB_DRAM_TIMING_TABLE_15[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_15)/sizeof(ixMCARB_DRAM_TIMING_TABLE_15[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_16", REG_SMC, 0x3f054, &ixMCARB_DRAM_TIMING_TABLE_16[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_16)/sizeof(ixMCARB_DRAM_TIMING_TABLE_16[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_17", REG_SMC, 0x3f058, &ixMCARB_DRAM_TIMING_TABLE_17[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_17)/sizeof(ixMCARB_DRAM_TIMING_TABLE_17[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_18", REG_SMC, 0x3f05c, &ixMCARB_DRAM_TIMING_TABLE_18[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_18)/sizeof(ixMCARB_DRAM_TIMING_TABLE_18[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_19", REG_SMC, 0x3f060, &ixMCARB_DRAM_TIMING_TABLE_19[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_19)/sizeof(ixMCARB_DRAM_TIMING_TABLE_19[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_20", REG_SMC, 0x3f064, &ixMCARB_DRAM_TIMING_TABLE_20[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_20)/sizeof(ixMCARB_DRAM_TIMING_TABLE_20[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_21", REG_SMC, 0x3f068, &ixMCARB_DRAM_TIMING_TABLE_21[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_21)/sizeof(ixMCARB_DRAM_TIMING_TABLE_21[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_22", REG_SMC, 0x3f06c, &ixMCARB_DRAM_TIMING_TABLE_22[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_22)/sizeof(ixMCARB_DRAM_TIMING_TABLE_22[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_23", REG_SMC, 0x3f070, &ixMCARB_DRAM_TIMING_TABLE_23[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_23)/sizeof(ixMCARB_DRAM_TIMING_TABLE_23[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_24", REG_SMC, 0x3f074, &ixMCARB_DRAM_TIMING_TABLE_24[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_24)/sizeof(ixMCARB_DRAM_TIMING_TABLE_24[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_25", REG_SMC, 0x3f078, &ixMCARB_DRAM_TIMING_TABLE_25[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_25)/sizeof(ixMCARB_DRAM_TIMING_TABLE_25[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_26", REG_SMC, 0x3f07c, &ixMCARB_DRAM_TIMING_TABLE_26[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_26)/sizeof(ixMCARB_DRAM_TIMING_TABLE_26[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_27", REG_SMC, 0x3f080, &ixMCARB_DRAM_TIMING_TABLE_27[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_27)/sizeof(ixMCARB_DRAM_TIMING_TABLE_27[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_28", REG_SMC, 0x3f084, &ixMCARB_DRAM_TIMING_TABLE_28[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_28)/sizeof(ixMCARB_DRAM_TIMING_TABLE_28[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_29", REG_SMC, 0x3f088, &ixMCARB_DRAM_TIMING_TABLE_29[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_29)/sizeof(ixMCARB_DRAM_TIMING_TABLE_29[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_30", REG_SMC, 0x3f08c, &ixMCARB_DRAM_TIMING_TABLE_30[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_30)/sizeof(ixMCARB_DRAM_TIMING_TABLE_30[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_31", REG_SMC, 0x3f090, &ixMCARB_DRAM_TIMING_TABLE_31[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_31)/sizeof(ixMCARB_DRAM_TIMING_TABLE_31[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_32", REG_SMC, 0x3f094, &ixMCARB_DRAM_TIMING_TABLE_32[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_32)/sizeof(ixMCARB_DRAM_TIMING_TABLE_32[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_33", REG_SMC, 0x3f098, &ixMCARB_DRAM_TIMING_TABLE_33[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_33)/sizeof(ixMCARB_DRAM_TIMING_TABLE_33[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_34", REG_SMC, 0x3f09c, &ixMCARB_DRAM_TIMING_TABLE_34[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_34)/sizeof(ixMCARB_DRAM_TIMING_TABLE_34[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_35", REG_SMC, 0x3f0a0, &ixMCARB_DRAM_TIMING_TABLE_35[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_35)/sizeof(ixMCARB_DRAM_TIMING_TABLE_35[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_36", REG_SMC, 0x3f0a4, &ixMCARB_DRAM_TIMING_TABLE_36[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_36)/sizeof(ixMCARB_DRAM_TIMING_TABLE_36[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_37", REG_SMC, 0x3f0a8, &ixMCARB_DRAM_TIMING_TABLE_37[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_37)/sizeof(ixMCARB_DRAM_TIMING_TABLE_37[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_38", REG_SMC, 0x3f0ac, &ixMCARB_DRAM_TIMING_TABLE_38[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_38)/sizeof(ixMCARB_DRAM_TIMING_TABLE_38[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_39", REG_SMC, 0x3f0b0, &ixMCARB_DRAM_TIMING_TABLE_39[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_39)/sizeof(ixMCARB_DRAM_TIMING_TABLE_39[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_40", REG_SMC, 0x3f0b4, &ixMCARB_DRAM_TIMING_TABLE_40[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_40)/sizeof(ixMCARB_DRAM_TIMING_TABLE_40[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_41", REG_SMC, 0x3f0b8, &ixMCARB_DRAM_TIMING_TABLE_41[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_41)/sizeof(ixMCARB_DRAM_TIMING_TABLE_41[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_42", REG_SMC, 0x3f0bc, &ixMCARB_DRAM_TIMING_TABLE_42[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_42)/sizeof(ixMCARB_DRAM_TIMING_TABLE_42[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_43", REG_SMC, 0x3f0c0, &ixMCARB_DRAM_TIMING_TABLE_43[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_43)/sizeof(ixMCARB_DRAM_TIMING_TABLE_43[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_44", REG_SMC, 0x3f0c4, &ixMCARB_DRAM_TIMING_TABLE_44[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_44)/sizeof(ixMCARB_DRAM_TIMING_TABLE_44[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_45", REG_SMC, 0x3f0c8, &ixMCARB_DRAM_TIMING_TABLE_45[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_45)/sizeof(ixMCARB_DRAM_TIMING_TABLE_45[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_46", REG_SMC, 0x3f0cc, &ixMCARB_DRAM_TIMING_TABLE_46[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_46)/sizeof(ixMCARB_DRAM_TIMING_TABLE_46[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_47", REG_SMC, 0x3f0d0, &ixMCARB_DRAM_TIMING_TABLE_47[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_47)/sizeof(ixMCARB_DRAM_TIMING_TABLE_47[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_48", REG_SMC, 0x3f0d4, &ixMCARB_DRAM_TIMING_TABLE_48[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_48)/sizeof(ixMCARB_DRAM_TIMING_TABLE_48[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_49", REG_SMC, 0x3f0d8, &ixMCARB_DRAM_TIMING_TABLE_49[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_49)/sizeof(ixMCARB_DRAM_TIMING_TABLE_49[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_50", REG_SMC, 0x3f0dc, &ixMCARB_DRAM_TIMING_TABLE_50[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_50)/sizeof(ixMCARB_DRAM_TIMING_TABLE_50[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_51", REG_SMC, 0x3f0e0, &ixMCARB_DRAM_TIMING_TABLE_51[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_51)/sizeof(ixMCARB_DRAM_TIMING_TABLE_51[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_52", REG_SMC, 0x3f0e4, &ixMCARB_DRAM_TIMING_TABLE_52[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_52)/sizeof(ixMCARB_DRAM_TIMING_TABLE_52[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_53", REG_SMC, 0x3f0e8, &ixMCARB_DRAM_TIMING_TABLE_53[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_53)/sizeof(ixMCARB_DRAM_TIMING_TABLE_53[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_54", REG_SMC, 0x3f0ec, &ixMCARB_DRAM_TIMING_TABLE_54[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_54)/sizeof(ixMCARB_DRAM_TIMING_TABLE_54[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_55", REG_SMC, 0x3f0f0, &ixMCARB_DRAM_TIMING_TABLE_55[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_55)/sizeof(ixMCARB_DRAM_TIMING_TABLE_55[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_56", REG_SMC, 0x3f0f4, &ixMCARB_DRAM_TIMING_TABLE_56[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_56)/sizeof(ixMCARB_DRAM_TIMING_TABLE_56[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_57", REG_SMC, 0x3f0f8, &ixMCARB_DRAM_TIMING_TABLE_57[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_57)/sizeof(ixMCARB_DRAM_TIMING_TABLE_57[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_58", REG_SMC, 0x3f0fc, &ixMCARB_DRAM_TIMING_TABLE_58[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_58)/sizeof(ixMCARB_DRAM_TIMING_TABLE_58[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_59", REG_SMC, 0x3f100, &ixMCARB_DRAM_TIMING_TABLE_59[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_59)/sizeof(ixMCARB_DRAM_TIMING_TABLE_59[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_60", REG_SMC, 0x3f104, &ixMCARB_DRAM_TIMING_TABLE_60[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_60)/sizeof(ixMCARB_DRAM_TIMING_TABLE_60[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_61", REG_SMC, 0x3f108, &ixMCARB_DRAM_TIMING_TABLE_61[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_61)/sizeof(ixMCARB_DRAM_TIMING_TABLE_61[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_62", REG_SMC, 0x3f10c, &ixMCARB_DRAM_TIMING_TABLE_62[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_62)/sizeof(ixMCARB_DRAM_TIMING_TABLE_62[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_63", REG_SMC, 0x3f110, &ixMCARB_DRAM_TIMING_TABLE_63[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_63)/sizeof(ixMCARB_DRAM_TIMING_TABLE_63[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_64", REG_SMC, 0x3f114, &ixMCARB_DRAM_TIMING_TABLE_64[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_64)/sizeof(ixMCARB_DRAM_TIMING_TABLE_64[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_65", REG_SMC, 0x3f118, &ixMCARB_DRAM_TIMING_TABLE_65[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_65)/sizeof(ixMCARB_DRAM_TIMING_TABLE_65[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_66", REG_SMC, 0x3f11c, &ixMCARB_DRAM_TIMING_TABLE_66[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_66)/sizeof(ixMCARB_DRAM_TIMING_TABLE_66[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_67", REG_SMC, 0x3f120, &ixMCARB_DRAM_TIMING_TABLE_67[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_67)/sizeof(ixMCARB_DRAM_TIMING_TABLE_67[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_68", REG_SMC, 0x3f124, &ixMCARB_DRAM_TIMING_TABLE_68[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_68)/sizeof(ixMCARB_DRAM_TIMING_TABLE_68[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_69", REG_SMC, 0x3f128, &ixMCARB_DRAM_TIMING_TABLE_69[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_69)/sizeof(ixMCARB_DRAM_TIMING_TABLE_69[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_70", REG_SMC, 0x3f12c, &ixMCARB_DRAM_TIMING_TABLE_70[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_70)/sizeof(ixMCARB_DRAM_TIMING_TABLE_70[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_71", REG_SMC, 0x3f130, &ixMCARB_DRAM_TIMING_TABLE_71[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_71)/sizeof(ixMCARB_DRAM_TIMING_TABLE_71[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_72", REG_SMC, 0x3f134, &ixMCARB_DRAM_TIMING_TABLE_72[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_72)/sizeof(ixMCARB_DRAM_TIMING_TABLE_72[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_73", REG_SMC, 0x3f138, &ixMCARB_DRAM_TIMING_TABLE_73[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_73)/sizeof(ixMCARB_DRAM_TIMING_TABLE_73[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_74", REG_SMC, 0x3f13c, &ixMCARB_DRAM_TIMING_TABLE_74[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_74)/sizeof(ixMCARB_DRAM_TIMING_TABLE_74[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_75", REG_SMC, 0x3f140, &ixMCARB_DRAM_TIMING_TABLE_75[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_75)/sizeof(ixMCARB_DRAM_TIMING_TABLE_75[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_76", REG_SMC, 0x3f144, &ixMCARB_DRAM_TIMING_TABLE_76[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_76)/sizeof(ixMCARB_DRAM_TIMING_TABLE_76[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_77", REG_SMC, 0x3f148, &ixMCARB_DRAM_TIMING_TABLE_77[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_77)/sizeof(ixMCARB_DRAM_TIMING_TABLE_77[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_78", REG_SMC, 0x3f14c, &ixMCARB_DRAM_TIMING_TABLE_78[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_78)/sizeof(ixMCARB_DRAM_TIMING_TABLE_78[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_79", REG_SMC, 0x3f150, &ixMCARB_DRAM_TIMING_TABLE_79[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_79)/sizeof(ixMCARB_DRAM_TIMING_TABLE_79[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_80", REG_SMC, 0x3f154, &ixMCARB_DRAM_TIMING_TABLE_80[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_80)/sizeof(ixMCARB_DRAM_TIMING_TABLE_80[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_81", REG_SMC, 0x3f158, &ixMCARB_DRAM_TIMING_TABLE_81[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_81)/sizeof(ixMCARB_DRAM_TIMING_TABLE_81[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_82", REG_SMC, 0x3f15c, &ixMCARB_DRAM_TIMING_TABLE_82[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_82)/sizeof(ixMCARB_DRAM_TIMING_TABLE_82[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_83", REG_SMC, 0x3f160, &ixMCARB_DRAM_TIMING_TABLE_83[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_83)/sizeof(ixMCARB_DRAM_TIMING_TABLE_83[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_84", REG_SMC, 0x3f164, &ixMCARB_DRAM_TIMING_TABLE_84[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_84)/sizeof(ixMCARB_DRAM_TIMING_TABLE_84[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_85", REG_SMC, 0x3f168, &ixMCARB_DRAM_TIMING_TABLE_85[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_85)/sizeof(ixMCARB_DRAM_TIMING_TABLE_85[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_86", REG_SMC, 0x3f16c, &ixMCARB_DRAM_TIMING_TABLE_86[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_86)/sizeof(ixMCARB_DRAM_TIMING_TABLE_86[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_87", REG_SMC, 0x3f170, &ixMCARB_DRAM_TIMING_TABLE_87[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_87)/sizeof(ixMCARB_DRAM_TIMING_TABLE_87[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_88", REG_SMC, 0x3f174, &ixMCARB_DRAM_TIMING_TABLE_88[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_88)/sizeof(ixMCARB_DRAM_TIMING_TABLE_88[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_89", REG_SMC, 0x3f178, &ixMCARB_DRAM_TIMING_TABLE_89[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_89)/sizeof(ixMCARB_DRAM_TIMING_TABLE_89[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_90", REG_SMC, 0x3f17c, &ixMCARB_DRAM_TIMING_TABLE_90[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_90)/sizeof(ixMCARB_DRAM_TIMING_TABLE_90[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_91", REG_SMC, 0x3f180, &ixMCARB_DRAM_TIMING_TABLE_91[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_91)/sizeof(ixMCARB_DRAM_TIMING_TABLE_91[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_92", REG_SMC, 0x3f184, &ixMCARB_DRAM_TIMING_TABLE_92[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_92)/sizeof(ixMCARB_DRAM_TIMING_TABLE_92[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_93", REG_SMC, 0x3f188, &ixMCARB_DRAM_TIMING_TABLE_93[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_93)/sizeof(ixMCARB_DRAM_TIMING_TABLE_93[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_94", REG_SMC, 0x3f18c, &ixMCARB_DRAM_TIMING_TABLE_94[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_94)/sizeof(ixMCARB_DRAM_TIMING_TABLE_94[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_95", REG_SMC, 0x3f190, &ixMCARB_DRAM_TIMING_TABLE_95[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_95)/sizeof(ixMCARB_DRAM_TIMING_TABLE_95[0]), 0, 0 },
+	{ "ixMCARB_DRAM_TIMING_TABLE_96", REG_SMC, 0x3f194, &ixMCARB_DRAM_TIMING_TABLE_96[0], sizeof(ixMCARB_DRAM_TIMING_TABLE_96)/sizeof(ixMCARB_DRAM_TIMING_TABLE_96[0]), 0, 0 },
+	{ "ixDPM_TABLE_1", REG_SMC, 0x3f198, &ixDPM_TABLE_1[0], sizeof(ixDPM_TABLE_1)/sizeof(ixDPM_TABLE_1[0]), 0, 0 },
+	{ "ixDPM_TABLE_2", REG_SMC, 0x3f19c, &ixDPM_TABLE_2[0], sizeof(ixDPM_TABLE_2)/sizeof(ixDPM_TABLE_2[0]), 0, 0 },
+	{ "ixDPM_TABLE_3", REG_SMC, 0x3f1a0, &ixDPM_TABLE_3[0], sizeof(ixDPM_TABLE_3)/sizeof(ixDPM_TABLE_3[0]), 0, 0 },
+	{ "ixDPM_TABLE_4", REG_SMC, 0x3f1a4, &ixDPM_TABLE_4[0], sizeof(ixDPM_TABLE_4)/sizeof(ixDPM_TABLE_4[0]), 0, 0 },
+	{ "ixDPM_TABLE_5", REG_SMC, 0x3f1a8, &ixDPM_TABLE_5[0], sizeof(ixDPM_TABLE_5)/sizeof(ixDPM_TABLE_5[0]), 0, 0 },
+	{ "ixDPM_TABLE_6", REG_SMC, 0x3f1ac, &ixDPM_TABLE_6[0], sizeof(ixDPM_TABLE_6)/sizeof(ixDPM_TABLE_6[0]), 0, 0 },
+	{ "ixDPM_TABLE_7", REG_SMC, 0x3f1b0, &ixDPM_TABLE_7[0], sizeof(ixDPM_TABLE_7)/sizeof(ixDPM_TABLE_7[0]), 0, 0 },
+	{ "ixDPM_TABLE_8", REG_SMC, 0x3f1b4, &ixDPM_TABLE_8[0], sizeof(ixDPM_TABLE_8)/sizeof(ixDPM_TABLE_8[0]), 0, 0 },
+	{ "ixDPM_TABLE_9", REG_SMC, 0x3f1b8, &ixDPM_TABLE_9[0], sizeof(ixDPM_TABLE_9)/sizeof(ixDPM_TABLE_9[0]), 0, 0 },
+	{ "ixDPM_TABLE_10", REG_SMC, 0x3f1bc, &ixDPM_TABLE_10[0], sizeof(ixDPM_TABLE_10)/sizeof(ixDPM_TABLE_10[0]), 0, 0 },
+	{ "ixDPM_TABLE_11", REG_SMC, 0x3f1c0, &ixDPM_TABLE_11[0], sizeof(ixDPM_TABLE_11)/sizeof(ixDPM_TABLE_11[0]), 0, 0 },
+	{ "ixDPM_TABLE_12", REG_SMC, 0x3f1c4, &ixDPM_TABLE_12[0], sizeof(ixDPM_TABLE_12)/sizeof(ixDPM_TABLE_12[0]), 0, 0 },
+	{ "ixDPM_TABLE_13", REG_SMC, 0x3f1c8, &ixDPM_TABLE_13[0], sizeof(ixDPM_TABLE_13)/sizeof(ixDPM_TABLE_13[0]), 0, 0 },
+	{ "ixDPM_TABLE_14", REG_SMC, 0x3f1cc, &ixDPM_TABLE_14[0], sizeof(ixDPM_TABLE_14)/sizeof(ixDPM_TABLE_14[0]), 0, 0 },
+	{ "ixDPM_TABLE_15", REG_SMC, 0x3f1d0, &ixDPM_TABLE_15[0], sizeof(ixDPM_TABLE_15)/sizeof(ixDPM_TABLE_15[0]), 0, 0 },
+	{ "ixDPM_TABLE_16", REG_SMC, 0x3f1d4, &ixDPM_TABLE_16[0], sizeof(ixDPM_TABLE_16)/sizeof(ixDPM_TABLE_16[0]), 0, 0 },
+	{ "ixDPM_TABLE_17", REG_SMC, 0x3f1d8, &ixDPM_TABLE_17[0], sizeof(ixDPM_TABLE_17)/sizeof(ixDPM_TABLE_17[0]), 0, 0 },
+	{ "ixDPM_TABLE_18", REG_SMC, 0x3f1dc, &ixDPM_TABLE_18[0], sizeof(ixDPM_TABLE_18)/sizeof(ixDPM_TABLE_18[0]), 0, 0 },
+	{ "ixDPM_TABLE_19", REG_SMC, 0x3f1e0, &ixDPM_TABLE_19[0], sizeof(ixDPM_TABLE_19)/sizeof(ixDPM_TABLE_19[0]), 0, 0 },
+	{ "ixDPM_TABLE_20", REG_SMC, 0x3f1e4, &ixDPM_TABLE_20[0], sizeof(ixDPM_TABLE_20)/sizeof(ixDPM_TABLE_20[0]), 0, 0 },
+	{ "ixDPM_TABLE_21", REG_SMC, 0x3f1e8, &ixDPM_TABLE_21[0], sizeof(ixDPM_TABLE_21)/sizeof(ixDPM_TABLE_21[0]), 0, 0 },
+	{ "ixDPM_TABLE_22", REG_SMC, 0x3f1ec, &ixDPM_TABLE_22[0], sizeof(ixDPM_TABLE_22)/sizeof(ixDPM_TABLE_22[0]), 0, 0 },
+	{ "ixDPM_TABLE_23", REG_SMC, 0x3f1f0, &ixDPM_TABLE_23[0], sizeof(ixDPM_TABLE_23)/sizeof(ixDPM_TABLE_23[0]), 0, 0 },
+	{ "ixDPM_TABLE_24", REG_SMC, 0x3f1f4, &ixDPM_TABLE_24[0], sizeof(ixDPM_TABLE_24)/sizeof(ixDPM_TABLE_24[0]), 0, 0 },
+	{ "ixDPM_TABLE_25", REG_SMC, 0x3f1f8, &ixDPM_TABLE_25[0], sizeof(ixDPM_TABLE_25)/sizeof(ixDPM_TABLE_25[0]), 0, 0 },
+	{ "ixDPM_TABLE_26", REG_SMC, 0x3f1fc, &ixDPM_TABLE_26[0], sizeof(ixDPM_TABLE_26)/sizeof(ixDPM_TABLE_26[0]), 0, 0 },
+	{ "ixDPM_TABLE_27", REG_SMC, 0x3f200, &ixDPM_TABLE_27[0], sizeof(ixDPM_TABLE_27)/sizeof(ixDPM_TABLE_27[0]), 0, 0 },
+	{ "ixDPM_TABLE_28", REG_SMC, 0x3f204, &ixDPM_TABLE_28[0], sizeof(ixDPM_TABLE_28)/sizeof(ixDPM_TABLE_28[0]), 0, 0 },
+	{ "ixDPM_TABLE_29", REG_SMC, 0x3f208, &ixDPM_TABLE_29[0], sizeof(ixDPM_TABLE_29)/sizeof(ixDPM_TABLE_29[0]), 0, 0 },
+	{ "ixDPM_TABLE_30", REG_SMC, 0x3f20c, &ixDPM_TABLE_30[0], sizeof(ixDPM_TABLE_30)/sizeof(ixDPM_TABLE_30[0]), 0, 0 },
+	{ "ixDPM_TABLE_31", REG_SMC, 0x3f210, &ixDPM_TABLE_31[0], sizeof(ixDPM_TABLE_31)/sizeof(ixDPM_TABLE_31[0]), 0, 0 },
+	{ "ixDPM_TABLE_32", REG_SMC, 0x3f214, &ixDPM_TABLE_32[0], sizeof(ixDPM_TABLE_32)/sizeof(ixDPM_TABLE_32[0]), 0, 0 },
+	{ "ixDPM_TABLE_33", REG_SMC, 0x3f218, &ixDPM_TABLE_33[0], sizeof(ixDPM_TABLE_33)/sizeof(ixDPM_TABLE_33[0]), 0, 0 },
+	{ "ixDPM_TABLE_34", REG_SMC, 0x3f21c, &ixDPM_TABLE_34[0], sizeof(ixDPM_TABLE_34)/sizeof(ixDPM_TABLE_34[0]), 0, 0 },
+	{ "ixDPM_TABLE_35", REG_SMC, 0x3f220, &ixDPM_TABLE_35[0], sizeof(ixDPM_TABLE_35)/sizeof(ixDPM_TABLE_35[0]), 0, 0 },
+	{ "ixDPM_TABLE_36", REG_SMC, 0x3f224, &ixDPM_TABLE_36[0], sizeof(ixDPM_TABLE_36)/sizeof(ixDPM_TABLE_36[0]), 0, 0 },
+	{ "ixDPM_TABLE_37", REG_SMC, 0x3f228, &ixDPM_TABLE_37[0], sizeof(ixDPM_TABLE_37)/sizeof(ixDPM_TABLE_37[0]), 0, 0 },
+	{ "ixDPM_TABLE_38", REG_SMC, 0x3f22c, &ixDPM_TABLE_38[0], sizeof(ixDPM_TABLE_38)/sizeof(ixDPM_TABLE_38[0]), 0, 0 },
+	{ "ixDPM_TABLE_39", REG_SMC, 0x3f230, &ixDPM_TABLE_39[0], sizeof(ixDPM_TABLE_39)/sizeof(ixDPM_TABLE_39[0]), 0, 0 },
+	{ "ixDPM_TABLE_40", REG_SMC, 0x3f234, &ixDPM_TABLE_40[0], sizeof(ixDPM_TABLE_40)/sizeof(ixDPM_TABLE_40[0]), 0, 0 },
+	{ "ixDPM_TABLE_41", REG_SMC, 0x3f238, &ixDPM_TABLE_41[0], sizeof(ixDPM_TABLE_41)/sizeof(ixDPM_TABLE_41[0]), 0, 0 },
+	{ "ixDPM_TABLE_42", REG_SMC, 0x3f23c, &ixDPM_TABLE_42[0], sizeof(ixDPM_TABLE_42)/sizeof(ixDPM_TABLE_42[0]), 0, 0 },
+	{ "ixDPM_TABLE_43", REG_SMC, 0x3f240, &ixDPM_TABLE_43[0], sizeof(ixDPM_TABLE_43)/sizeof(ixDPM_TABLE_43[0]), 0, 0 },
+	{ "ixDPM_TABLE_44", REG_SMC, 0x3f244, &ixDPM_TABLE_44[0], sizeof(ixDPM_TABLE_44)/sizeof(ixDPM_TABLE_44[0]), 0, 0 },
+	{ "ixDPM_TABLE_45", REG_SMC, 0x3f248, &ixDPM_TABLE_45[0], sizeof(ixDPM_TABLE_45)/sizeof(ixDPM_TABLE_45[0]), 0, 0 },
+	{ "ixDPM_TABLE_46", REG_SMC, 0x3f24c, &ixDPM_TABLE_46[0], sizeof(ixDPM_TABLE_46)/sizeof(ixDPM_TABLE_46[0]), 0, 0 },
+	{ "ixDPM_TABLE_47", REG_SMC, 0x3f250, &ixDPM_TABLE_47[0], sizeof(ixDPM_TABLE_47)/sizeof(ixDPM_TABLE_47[0]), 0, 0 },
+	{ "ixDPM_TABLE_48", REG_SMC, 0x3f254, &ixDPM_TABLE_48[0], sizeof(ixDPM_TABLE_48)/sizeof(ixDPM_TABLE_48[0]), 0, 0 },
+	{ "ixDPM_TABLE_49", REG_SMC, 0x3f258, &ixDPM_TABLE_49[0], sizeof(ixDPM_TABLE_49)/sizeof(ixDPM_TABLE_49[0]), 0, 0 },
+	{ "ixDPM_TABLE_50", REG_SMC, 0x3f25c, &ixDPM_TABLE_50[0], sizeof(ixDPM_TABLE_50)/sizeof(ixDPM_TABLE_50[0]), 0, 0 },
+	{ "ixDPM_TABLE_51", REG_SMC, 0x3f260, &ixDPM_TABLE_51[0], sizeof(ixDPM_TABLE_51)/sizeof(ixDPM_TABLE_51[0]), 0, 0 },
+	{ "ixDPM_TABLE_52", REG_SMC, 0x3f264, &ixDPM_TABLE_52[0], sizeof(ixDPM_TABLE_52)/sizeof(ixDPM_TABLE_52[0]), 0, 0 },
+	{ "ixDPM_TABLE_53", REG_SMC, 0x3f268, &ixDPM_TABLE_53[0], sizeof(ixDPM_TABLE_53)/sizeof(ixDPM_TABLE_53[0]), 0, 0 },
+	{ "ixDPM_TABLE_54", REG_SMC, 0x3f26c, &ixDPM_TABLE_54[0], sizeof(ixDPM_TABLE_54)/sizeof(ixDPM_TABLE_54[0]), 0, 0 },
+	{ "ixDPM_TABLE_55", REG_SMC, 0x3f270, &ixDPM_TABLE_55[0], sizeof(ixDPM_TABLE_55)/sizeof(ixDPM_TABLE_55[0]), 0, 0 },
+	{ "ixDPM_TABLE_56", REG_SMC, 0x3f274, &ixDPM_TABLE_56[0], sizeof(ixDPM_TABLE_56)/sizeof(ixDPM_TABLE_56[0]), 0, 0 },
+	{ "ixDPM_TABLE_57", REG_SMC, 0x3f278, &ixDPM_TABLE_57[0], sizeof(ixDPM_TABLE_57)/sizeof(ixDPM_TABLE_57[0]), 0, 0 },
+	{ "ixDPM_TABLE_58", REG_SMC, 0x3f27c, &ixDPM_TABLE_58[0], sizeof(ixDPM_TABLE_58)/sizeof(ixDPM_TABLE_58[0]), 0, 0 },
+	{ "ixDPM_TABLE_59", REG_SMC, 0x3f280, &ixDPM_TABLE_59[0], sizeof(ixDPM_TABLE_59)/sizeof(ixDPM_TABLE_59[0]), 0, 0 },
+	{ "ixDPM_TABLE_60", REG_SMC, 0x3f284, &ixDPM_TABLE_60[0], sizeof(ixDPM_TABLE_60)/sizeof(ixDPM_TABLE_60[0]), 0, 0 },
+	{ "ixDPM_TABLE_61", REG_SMC, 0x3f288, &ixDPM_TABLE_61[0], sizeof(ixDPM_TABLE_61)/sizeof(ixDPM_TABLE_61[0]), 0, 0 },
+	{ "ixDPM_TABLE_62", REG_SMC, 0x3f28c, &ixDPM_TABLE_62[0], sizeof(ixDPM_TABLE_62)/sizeof(ixDPM_TABLE_62[0]), 0, 0 },
+	{ "ixDPM_TABLE_63", REG_SMC, 0x3f290, &ixDPM_TABLE_63[0], sizeof(ixDPM_TABLE_63)/sizeof(ixDPM_TABLE_63[0]), 0, 0 },
+	{ "ixDPM_TABLE_64", REG_SMC, 0x3f294, &ixDPM_TABLE_64[0], sizeof(ixDPM_TABLE_64)/sizeof(ixDPM_TABLE_64[0]), 0, 0 },
+	{ "ixDPM_TABLE_65", REG_SMC, 0x3f298, &ixDPM_TABLE_65[0], sizeof(ixDPM_TABLE_65)/sizeof(ixDPM_TABLE_65[0]), 0, 0 },
+	{ "ixDPM_TABLE_66", REG_SMC, 0x3f29c, &ixDPM_TABLE_66[0], sizeof(ixDPM_TABLE_66)/sizeof(ixDPM_TABLE_66[0]), 0, 0 },
+	{ "ixDPM_TABLE_67", REG_SMC, 0x3f2a0, &ixDPM_TABLE_67[0], sizeof(ixDPM_TABLE_67)/sizeof(ixDPM_TABLE_67[0]), 0, 0 },
+	{ "ixDPM_TABLE_68", REG_SMC, 0x3f2a4, &ixDPM_TABLE_68[0], sizeof(ixDPM_TABLE_68)/sizeof(ixDPM_TABLE_68[0]), 0, 0 },
+	{ "ixDPM_TABLE_69", REG_SMC, 0x3f2a8, &ixDPM_TABLE_69[0], sizeof(ixDPM_TABLE_69)/sizeof(ixDPM_TABLE_69[0]), 0, 0 },
+	{ "ixDPM_TABLE_70", REG_SMC, 0x3f2ac, &ixDPM_TABLE_70[0], sizeof(ixDPM_TABLE_70)/sizeof(ixDPM_TABLE_70[0]), 0, 0 },
+	{ "ixDPM_TABLE_71", REG_SMC, 0x3f2b0, &ixDPM_TABLE_71[0], sizeof(ixDPM_TABLE_71)/sizeof(ixDPM_TABLE_71[0]), 0, 0 },
+	{ "ixDPM_TABLE_72", REG_SMC, 0x3f2b4, &ixDPM_TABLE_72[0], sizeof(ixDPM_TABLE_72)/sizeof(ixDPM_TABLE_72[0]), 0, 0 },
+	{ "ixDPM_TABLE_73", REG_SMC, 0x3f2b8, &ixDPM_TABLE_73[0], sizeof(ixDPM_TABLE_73)/sizeof(ixDPM_TABLE_73[0]), 0, 0 },
+	{ "ixDPM_TABLE_74", REG_SMC, 0x3f2bc, &ixDPM_TABLE_74[0], sizeof(ixDPM_TABLE_74)/sizeof(ixDPM_TABLE_74[0]), 0, 0 },
+	{ "ixDPM_TABLE_75", REG_SMC, 0x3f2c0, &ixDPM_TABLE_75[0], sizeof(ixDPM_TABLE_75)/sizeof(ixDPM_TABLE_75[0]), 0, 0 },
+	{ "ixDPM_TABLE_76", REG_SMC, 0x3f2c4, &ixDPM_TABLE_76[0], sizeof(ixDPM_TABLE_76)/sizeof(ixDPM_TABLE_76[0]), 0, 0 },
+	{ "ixDPM_TABLE_77", REG_SMC, 0x3f2c8, &ixDPM_TABLE_77[0], sizeof(ixDPM_TABLE_77)/sizeof(ixDPM_TABLE_77[0]), 0, 0 },
+	{ "ixDPM_TABLE_78", REG_SMC, 0x3f2cc, &ixDPM_TABLE_78[0], sizeof(ixDPM_TABLE_78)/sizeof(ixDPM_TABLE_78[0]), 0, 0 },
+	{ "ixDPM_TABLE_79", REG_SMC, 0x3f2d0, &ixDPM_TABLE_79[0], sizeof(ixDPM_TABLE_79)/sizeof(ixDPM_TABLE_79[0]), 0, 0 },
+	{ "ixDPM_TABLE_80", REG_SMC, 0x3f2d4, &ixDPM_TABLE_80[0], sizeof(ixDPM_TABLE_80)/sizeof(ixDPM_TABLE_80[0]), 0, 0 },
+	{ "ixDPM_TABLE_81", REG_SMC, 0x3f2d8, &ixDPM_TABLE_81[0], sizeof(ixDPM_TABLE_81)/sizeof(ixDPM_TABLE_81[0]), 0, 0 },
+	{ "ixDPM_TABLE_82", REG_SMC, 0x3f2dc, &ixDPM_TABLE_82[0], sizeof(ixDPM_TABLE_82)/sizeof(ixDPM_TABLE_82[0]), 0, 0 },
+	{ "ixDPM_TABLE_83", REG_SMC, 0x3f2e0, &ixDPM_TABLE_83[0], sizeof(ixDPM_TABLE_83)/sizeof(ixDPM_TABLE_83[0]), 0, 0 },
+	{ "ixDPM_TABLE_84", REG_SMC, 0x3f2e4, &ixDPM_TABLE_84[0], sizeof(ixDPM_TABLE_84)/sizeof(ixDPM_TABLE_84[0]), 0, 0 },
+	{ "ixDPM_TABLE_85", REG_SMC, 0x3f2e8, &ixDPM_TABLE_85[0], sizeof(ixDPM_TABLE_85)/sizeof(ixDPM_TABLE_85[0]), 0, 0 },
+	{ "ixDPM_TABLE_86", REG_SMC, 0x3f2ec, &ixDPM_TABLE_86[0], sizeof(ixDPM_TABLE_86)/sizeof(ixDPM_TABLE_86[0]), 0, 0 },
+	{ "ixDPM_TABLE_87", REG_SMC, 0x3f2f0, &ixDPM_TABLE_87[0], sizeof(ixDPM_TABLE_87)/sizeof(ixDPM_TABLE_87[0]), 0, 0 },
+	{ "ixDPM_TABLE_88", REG_SMC, 0x3f2f4, &ixDPM_TABLE_88[0], sizeof(ixDPM_TABLE_88)/sizeof(ixDPM_TABLE_88[0]), 0, 0 },
+	{ "ixDPM_TABLE_89", REG_SMC, 0x3f2f8, &ixDPM_TABLE_89[0], sizeof(ixDPM_TABLE_89)/sizeof(ixDPM_TABLE_89[0]), 0, 0 },
+	{ "ixDPM_TABLE_90", REG_SMC, 0x3f2fc, &ixDPM_TABLE_90[0], sizeof(ixDPM_TABLE_90)/sizeof(ixDPM_TABLE_90[0]), 0, 0 },
+	{ "ixDPM_TABLE_91", REG_SMC, 0x3f300, &ixDPM_TABLE_91[0], sizeof(ixDPM_TABLE_91)/sizeof(ixDPM_TABLE_91[0]), 0, 0 },
+	{ "ixDPM_TABLE_92", REG_SMC, 0x3f304, &ixDPM_TABLE_92[0], sizeof(ixDPM_TABLE_92)/sizeof(ixDPM_TABLE_92[0]), 0, 0 },
+	{ "ixDPM_TABLE_93", REG_SMC, 0x3f308, &ixDPM_TABLE_93[0], sizeof(ixDPM_TABLE_93)/sizeof(ixDPM_TABLE_93[0]), 0, 0 },
+	{ "ixDPM_TABLE_94", REG_SMC, 0x3f30c, &ixDPM_TABLE_94[0], sizeof(ixDPM_TABLE_94)/sizeof(ixDPM_TABLE_94[0]), 0, 0 },
+	{ "ixDPM_TABLE_95", REG_SMC, 0x3f310, &ixDPM_TABLE_95[0], sizeof(ixDPM_TABLE_95)/sizeof(ixDPM_TABLE_95[0]), 0, 0 },
+	{ "ixDPM_TABLE_96", REG_SMC, 0x3f314, &ixDPM_TABLE_96[0], sizeof(ixDPM_TABLE_96)/sizeof(ixDPM_TABLE_96[0]), 0, 0 },
+	{ "ixDPM_TABLE_97", REG_SMC, 0x3f318, &ixDPM_TABLE_97[0], sizeof(ixDPM_TABLE_97)/sizeof(ixDPM_TABLE_97[0]), 0, 0 },
+	{ "ixDPM_TABLE_98", REG_SMC, 0x3f31c, &ixDPM_TABLE_98[0], sizeof(ixDPM_TABLE_98)/sizeof(ixDPM_TABLE_98[0]), 0, 0 },
+	{ "ixDPM_TABLE_99", REG_SMC, 0x3f320, &ixDPM_TABLE_99[0], sizeof(ixDPM_TABLE_99)/sizeof(ixDPM_TABLE_99[0]), 0, 0 },
+	{ "ixDPM_TABLE_100", REG_SMC, 0x3f324, &ixDPM_TABLE_100[0], sizeof(ixDPM_TABLE_100)/sizeof(ixDPM_TABLE_100[0]), 0, 0 },
+	{ "ixDPM_TABLE_101", REG_SMC, 0x3f328, &ixDPM_TABLE_101[0], sizeof(ixDPM_TABLE_101)/sizeof(ixDPM_TABLE_101[0]), 0, 0 },
+	{ "ixDPM_TABLE_102", REG_SMC, 0x3f32c, &ixDPM_TABLE_102[0], sizeof(ixDPM_TABLE_102)/sizeof(ixDPM_TABLE_102[0]), 0, 0 },
+	{ "ixDPM_TABLE_103", REG_SMC, 0x3f330, &ixDPM_TABLE_103[0], sizeof(ixDPM_TABLE_103)/sizeof(ixDPM_TABLE_103[0]), 0, 0 },
+	{ "ixDPM_TABLE_104", REG_SMC, 0x3f334, &ixDPM_TABLE_104[0], sizeof(ixDPM_TABLE_104)/sizeof(ixDPM_TABLE_104[0]), 0, 0 },
+	{ "ixDPM_TABLE_105", REG_SMC, 0x3f338, &ixDPM_TABLE_105[0], sizeof(ixDPM_TABLE_105)/sizeof(ixDPM_TABLE_105[0]), 0, 0 },
+	{ "ixDPM_TABLE_106", REG_SMC, 0x3f33c, &ixDPM_TABLE_106[0], sizeof(ixDPM_TABLE_106)/sizeof(ixDPM_TABLE_106[0]), 0, 0 },
+	{ "ixDPM_TABLE_107", REG_SMC, 0x3f340, &ixDPM_TABLE_107[0], sizeof(ixDPM_TABLE_107)/sizeof(ixDPM_TABLE_107[0]), 0, 0 },
+	{ "ixDPM_TABLE_108", REG_SMC, 0x3f344, &ixDPM_TABLE_108[0], sizeof(ixDPM_TABLE_108)/sizeof(ixDPM_TABLE_108[0]), 0, 0 },
+	{ "ixDPM_TABLE_109", REG_SMC, 0x3f348, &ixDPM_TABLE_109[0], sizeof(ixDPM_TABLE_109)/sizeof(ixDPM_TABLE_109[0]), 0, 0 },
+	{ "ixDPM_TABLE_110", REG_SMC, 0x3f34c, &ixDPM_TABLE_110[0], sizeof(ixDPM_TABLE_110)/sizeof(ixDPM_TABLE_110[0]), 0, 0 },
+	{ "ixDPM_TABLE_111", REG_SMC, 0x3f350, &ixDPM_TABLE_111[0], sizeof(ixDPM_TABLE_111)/sizeof(ixDPM_TABLE_111[0]), 0, 0 },
+	{ "ixDPM_TABLE_112", REG_SMC, 0x3f354, &ixDPM_TABLE_112[0], sizeof(ixDPM_TABLE_112)/sizeof(ixDPM_TABLE_112[0]), 0, 0 },
+	{ "ixDPM_TABLE_113", REG_SMC, 0x3f358, &ixDPM_TABLE_113[0], sizeof(ixDPM_TABLE_113)/sizeof(ixDPM_TABLE_113[0]), 0, 0 },
+	{ "ixDPM_TABLE_114", REG_SMC, 0x3f35c, &ixDPM_TABLE_114[0], sizeof(ixDPM_TABLE_114)/sizeof(ixDPM_TABLE_114[0]), 0, 0 },
+	{ "ixDPM_TABLE_115", REG_SMC, 0x3f360, &ixDPM_TABLE_115[0], sizeof(ixDPM_TABLE_115)/sizeof(ixDPM_TABLE_115[0]), 0, 0 },
+	{ "ixDPM_TABLE_116", REG_SMC, 0x3f364, &ixDPM_TABLE_116[0], sizeof(ixDPM_TABLE_116)/sizeof(ixDPM_TABLE_116[0]), 0, 0 },
+	{ "ixDPM_TABLE_117", REG_SMC, 0x3f368, &ixDPM_TABLE_117[0], sizeof(ixDPM_TABLE_117)/sizeof(ixDPM_TABLE_117[0]), 0, 0 },
+	{ "ixDPM_TABLE_118", REG_SMC, 0x3f36c, &ixDPM_TABLE_118[0], sizeof(ixDPM_TABLE_118)/sizeof(ixDPM_TABLE_118[0]), 0, 0 },
+	{ "ixDPM_TABLE_119", REG_SMC, 0x3f370, &ixDPM_TABLE_119[0], sizeof(ixDPM_TABLE_119)/sizeof(ixDPM_TABLE_119[0]), 0, 0 },
+	{ "ixDPM_TABLE_120", REG_SMC, 0x3f374, &ixDPM_TABLE_120[0], sizeof(ixDPM_TABLE_120)/sizeof(ixDPM_TABLE_120[0]), 0, 0 },
+	{ "ixDPM_TABLE_121", REG_SMC, 0x3f378, &ixDPM_TABLE_121[0], sizeof(ixDPM_TABLE_121)/sizeof(ixDPM_TABLE_121[0]), 0, 0 },
+	{ "ixDPM_TABLE_122", REG_SMC, 0x3f37c, &ixDPM_TABLE_122[0], sizeof(ixDPM_TABLE_122)/sizeof(ixDPM_TABLE_122[0]), 0, 0 },
+	{ "ixDPM_TABLE_123", REG_SMC, 0x3f380, &ixDPM_TABLE_123[0], sizeof(ixDPM_TABLE_123)/sizeof(ixDPM_TABLE_123[0]), 0, 0 },
+	{ "ixDPM_TABLE_124", REG_SMC, 0x3f384, &ixDPM_TABLE_124[0], sizeof(ixDPM_TABLE_124)/sizeof(ixDPM_TABLE_124[0]), 0, 0 },
+	{ "ixDPM_TABLE_125", REG_SMC, 0x3f388, &ixDPM_TABLE_125[0], sizeof(ixDPM_TABLE_125)/sizeof(ixDPM_TABLE_125[0]), 0, 0 },
+	{ "ixDPM_TABLE_126", REG_SMC, 0x3f38c, &ixDPM_TABLE_126[0], sizeof(ixDPM_TABLE_126)/sizeof(ixDPM_TABLE_126[0]), 0, 0 },
+	{ "ixDPM_TABLE_127", REG_SMC, 0x3f390, &ixDPM_TABLE_127[0], sizeof(ixDPM_TABLE_127)/sizeof(ixDPM_TABLE_127[0]), 0, 0 },
+	{ "ixDPM_TABLE_128", REG_SMC, 0x3f394, &ixDPM_TABLE_128[0], sizeof(ixDPM_TABLE_128)/sizeof(ixDPM_TABLE_128[0]), 0, 0 },
+	{ "ixDPM_TABLE_129", REG_SMC, 0x3f398, &ixDPM_TABLE_129[0], sizeof(ixDPM_TABLE_129)/sizeof(ixDPM_TABLE_129[0]), 0, 0 },
+	{ "ixDPM_TABLE_130", REG_SMC, 0x3f39c, &ixDPM_TABLE_130[0], sizeof(ixDPM_TABLE_130)/sizeof(ixDPM_TABLE_130[0]), 0, 0 },
+	{ "ixDPM_TABLE_131", REG_SMC, 0x3f3a0, &ixDPM_TABLE_131[0], sizeof(ixDPM_TABLE_131)/sizeof(ixDPM_TABLE_131[0]), 0, 0 },
+	{ "ixDPM_TABLE_132", REG_SMC, 0x3f3a4, &ixDPM_TABLE_132[0], sizeof(ixDPM_TABLE_132)/sizeof(ixDPM_TABLE_132[0]), 0, 0 },
+	{ "ixDPM_TABLE_133", REG_SMC, 0x3f3a8, &ixDPM_TABLE_133[0], sizeof(ixDPM_TABLE_133)/sizeof(ixDPM_TABLE_133[0]), 0, 0 },
+	{ "ixDPM_TABLE_134", REG_SMC, 0x3f3ac, &ixDPM_TABLE_134[0], sizeof(ixDPM_TABLE_134)/sizeof(ixDPM_TABLE_134[0]), 0, 0 },
+	{ "ixDPM_TABLE_135", REG_SMC, 0x3f3b0, &ixDPM_TABLE_135[0], sizeof(ixDPM_TABLE_135)/sizeof(ixDPM_TABLE_135[0]), 0, 0 },
+	{ "ixDPM_TABLE_136", REG_SMC, 0x3f3b4, &ixDPM_TABLE_136[0], sizeof(ixDPM_TABLE_136)/sizeof(ixDPM_TABLE_136[0]), 0, 0 },
+	{ "ixDPM_TABLE_137", REG_SMC, 0x3f3b8, &ixDPM_TABLE_137[0], sizeof(ixDPM_TABLE_137)/sizeof(ixDPM_TABLE_137[0]), 0, 0 },
+	{ "ixDPM_TABLE_138", REG_SMC, 0x3f3bc, &ixDPM_TABLE_138[0], sizeof(ixDPM_TABLE_138)/sizeof(ixDPM_TABLE_138[0]), 0, 0 },
+	{ "ixDPM_TABLE_139", REG_SMC, 0x3f3c0, &ixDPM_TABLE_139[0], sizeof(ixDPM_TABLE_139)/sizeof(ixDPM_TABLE_139[0]), 0, 0 },
+	{ "ixDPM_TABLE_140", REG_SMC, 0x3f3c4, &ixDPM_TABLE_140[0], sizeof(ixDPM_TABLE_140)/sizeof(ixDPM_TABLE_140[0]), 0, 0 },
+	{ "ixDPM_TABLE_141", REG_SMC, 0x3f3c8, &ixDPM_TABLE_141[0], sizeof(ixDPM_TABLE_141)/sizeof(ixDPM_TABLE_141[0]), 0, 0 },
+	{ "ixDPM_TABLE_142", REG_SMC, 0x3f3cc, &ixDPM_TABLE_142[0], sizeof(ixDPM_TABLE_142)/sizeof(ixDPM_TABLE_142[0]), 0, 0 },
+	{ "ixDPM_TABLE_143", REG_SMC, 0x3f3d0, &ixDPM_TABLE_143[0], sizeof(ixDPM_TABLE_143)/sizeof(ixDPM_TABLE_143[0]), 0, 0 },
+	{ "ixDPM_TABLE_144", REG_SMC, 0x3f3d4, &ixDPM_TABLE_144[0], sizeof(ixDPM_TABLE_144)/sizeof(ixDPM_TABLE_144[0]), 0, 0 },
+	{ "ixDPM_TABLE_145", REG_SMC, 0x3f3d8, &ixDPM_TABLE_145[0], sizeof(ixDPM_TABLE_145)/sizeof(ixDPM_TABLE_145[0]), 0, 0 },
+	{ "ixDPM_TABLE_146", REG_SMC, 0x3f3dc, &ixDPM_TABLE_146[0], sizeof(ixDPM_TABLE_146)/sizeof(ixDPM_TABLE_146[0]), 0, 0 },
+	{ "ixDPM_TABLE_147", REG_SMC, 0x3f3e0, &ixDPM_TABLE_147[0], sizeof(ixDPM_TABLE_147)/sizeof(ixDPM_TABLE_147[0]), 0, 0 },
+	{ "ixDPM_TABLE_148", REG_SMC, 0x3f3e4, &ixDPM_TABLE_148[0], sizeof(ixDPM_TABLE_148)/sizeof(ixDPM_TABLE_148[0]), 0, 0 },
+	{ "ixDPM_TABLE_149", REG_SMC, 0x3f3e8, &ixDPM_TABLE_149[0], sizeof(ixDPM_TABLE_149)/sizeof(ixDPM_TABLE_149[0]), 0, 0 },
+	{ "ixDPM_TABLE_150", REG_SMC, 0x3f3ec, &ixDPM_TABLE_150[0], sizeof(ixDPM_TABLE_150)/sizeof(ixDPM_TABLE_150[0]), 0, 0 },
+	{ "ixDPM_TABLE_151", REG_SMC, 0x3f3f0, &ixDPM_TABLE_151[0], sizeof(ixDPM_TABLE_151)/sizeof(ixDPM_TABLE_151[0]), 0, 0 },
+	{ "ixDPM_TABLE_152", REG_SMC, 0x3f3f4, &ixDPM_TABLE_152[0], sizeof(ixDPM_TABLE_152)/sizeof(ixDPM_TABLE_152[0]), 0, 0 },
+	{ "ixDPM_TABLE_153", REG_SMC, 0x3f3f8, &ixDPM_TABLE_153[0], sizeof(ixDPM_TABLE_153)/sizeof(ixDPM_TABLE_153[0]), 0, 0 },
+	{ "ixDPM_TABLE_154", REG_SMC, 0x3f3fc, &ixDPM_TABLE_154[0], sizeof(ixDPM_TABLE_154)/sizeof(ixDPM_TABLE_154[0]), 0, 0 },
+	{ "ixDPM_TABLE_155", REG_SMC, 0x3f400, &ixDPM_TABLE_155[0], sizeof(ixDPM_TABLE_155)/sizeof(ixDPM_TABLE_155[0]), 0, 0 },
+	{ "ixDPM_TABLE_156", REG_SMC, 0x3f404, &ixDPM_TABLE_156[0], sizeof(ixDPM_TABLE_156)/sizeof(ixDPM_TABLE_156[0]), 0, 0 },
+	{ "ixDPM_TABLE_157", REG_SMC, 0x3f408, &ixDPM_TABLE_157[0], sizeof(ixDPM_TABLE_157)/sizeof(ixDPM_TABLE_157[0]), 0, 0 },
+	{ "ixDPM_TABLE_158", REG_SMC, 0x3f40c, &ixDPM_TABLE_158[0], sizeof(ixDPM_TABLE_158)/sizeof(ixDPM_TABLE_158[0]), 0, 0 },
+	{ "ixDPM_TABLE_159", REG_SMC, 0x3f410, &ixDPM_TABLE_159[0], sizeof(ixDPM_TABLE_159)/sizeof(ixDPM_TABLE_159[0]), 0, 0 },
+	{ "ixDPM_TABLE_160", REG_SMC, 0x3f414, &ixDPM_TABLE_160[0], sizeof(ixDPM_TABLE_160)/sizeof(ixDPM_TABLE_160[0]), 0, 0 },
+	{ "ixDPM_TABLE_161", REG_SMC, 0x3f418, &ixDPM_TABLE_161[0], sizeof(ixDPM_TABLE_161)/sizeof(ixDPM_TABLE_161[0]), 0, 0 },
+	{ "ixDPM_TABLE_162", REG_SMC, 0x3f41c, &ixDPM_TABLE_162[0], sizeof(ixDPM_TABLE_162)/sizeof(ixDPM_TABLE_162[0]), 0, 0 },
+	{ "ixDPM_TABLE_163", REG_SMC, 0x3f420, &ixDPM_TABLE_163[0], sizeof(ixDPM_TABLE_163)/sizeof(ixDPM_TABLE_163[0]), 0, 0 },
+	{ "ixDPM_TABLE_164", REG_SMC, 0x3f424, &ixDPM_TABLE_164[0], sizeof(ixDPM_TABLE_164)/sizeof(ixDPM_TABLE_164[0]), 0, 0 },
+	{ "ixDPM_TABLE_165", REG_SMC, 0x3f428, &ixDPM_TABLE_165[0], sizeof(ixDPM_TABLE_165)/sizeof(ixDPM_TABLE_165[0]), 0, 0 },
+	{ "ixDPM_TABLE_166", REG_SMC, 0x3f42c, &ixDPM_TABLE_166[0], sizeof(ixDPM_TABLE_166)/sizeof(ixDPM_TABLE_166[0]), 0, 0 },
+	{ "ixDPM_TABLE_167", REG_SMC, 0x3f430, &ixDPM_TABLE_167[0], sizeof(ixDPM_TABLE_167)/sizeof(ixDPM_TABLE_167[0]), 0, 0 },
+	{ "ixDPM_TABLE_168", REG_SMC, 0x3f434, &ixDPM_TABLE_168[0], sizeof(ixDPM_TABLE_168)/sizeof(ixDPM_TABLE_168[0]), 0, 0 },
+	{ "ixDPM_TABLE_169", REG_SMC, 0x3f438, &ixDPM_TABLE_169[0], sizeof(ixDPM_TABLE_169)/sizeof(ixDPM_TABLE_169[0]), 0, 0 },
+	{ "ixDPM_TABLE_170", REG_SMC, 0x3f43c, &ixDPM_TABLE_170[0], sizeof(ixDPM_TABLE_170)/sizeof(ixDPM_TABLE_170[0]), 0, 0 },
+	{ "ixDPM_TABLE_171", REG_SMC, 0x3f440, &ixDPM_TABLE_171[0], sizeof(ixDPM_TABLE_171)/sizeof(ixDPM_TABLE_171[0]), 0, 0 },
+	{ "ixDPM_TABLE_172", REG_SMC, 0x3f444, &ixDPM_TABLE_172[0], sizeof(ixDPM_TABLE_172)/sizeof(ixDPM_TABLE_172[0]), 0, 0 },
+	{ "ixDPM_TABLE_173", REG_SMC, 0x3f448, &ixDPM_TABLE_173[0], sizeof(ixDPM_TABLE_173)/sizeof(ixDPM_TABLE_173[0]), 0, 0 },
+	{ "ixDPM_TABLE_174", REG_SMC, 0x3f44c, &ixDPM_TABLE_174[0], sizeof(ixDPM_TABLE_174)/sizeof(ixDPM_TABLE_174[0]), 0, 0 },
+	{ "ixDPM_TABLE_175", REG_SMC, 0x3f450, &ixDPM_TABLE_175[0], sizeof(ixDPM_TABLE_175)/sizeof(ixDPM_TABLE_175[0]), 0, 0 },
+	{ "ixDPM_TABLE_176", REG_SMC, 0x3f454, &ixDPM_TABLE_176[0], sizeof(ixDPM_TABLE_176)/sizeof(ixDPM_TABLE_176[0]), 0, 0 },
+	{ "ixDPM_TABLE_177", REG_SMC, 0x3f458, &ixDPM_TABLE_177[0], sizeof(ixDPM_TABLE_177)/sizeof(ixDPM_TABLE_177[0]), 0, 0 },
+	{ "ixDPM_TABLE_178", REG_SMC, 0x3f45c, &ixDPM_TABLE_178[0], sizeof(ixDPM_TABLE_178)/sizeof(ixDPM_TABLE_178[0]), 0, 0 },
+	{ "ixDPM_TABLE_179", REG_SMC, 0x3f460, &ixDPM_TABLE_179[0], sizeof(ixDPM_TABLE_179)/sizeof(ixDPM_TABLE_179[0]), 0, 0 },
+	{ "ixDPM_TABLE_180", REG_SMC, 0x3f464, &ixDPM_TABLE_180[0], sizeof(ixDPM_TABLE_180)/sizeof(ixDPM_TABLE_180[0]), 0, 0 },
+	{ "ixDPM_TABLE_181", REG_SMC, 0x3f468, &ixDPM_TABLE_181[0], sizeof(ixDPM_TABLE_181)/sizeof(ixDPM_TABLE_181[0]), 0, 0 },
+	{ "ixDPM_TABLE_182", REG_SMC, 0x3f46c, &ixDPM_TABLE_182[0], sizeof(ixDPM_TABLE_182)/sizeof(ixDPM_TABLE_182[0]), 0, 0 },
+	{ "ixDPM_TABLE_183", REG_SMC, 0x3f470, &ixDPM_TABLE_183[0], sizeof(ixDPM_TABLE_183)/sizeof(ixDPM_TABLE_183[0]), 0, 0 },
+	{ "ixDPM_TABLE_184", REG_SMC, 0x3f474, &ixDPM_TABLE_184[0], sizeof(ixDPM_TABLE_184)/sizeof(ixDPM_TABLE_184[0]), 0, 0 },
+	{ "ixDPM_TABLE_185", REG_SMC, 0x3f478, &ixDPM_TABLE_185[0], sizeof(ixDPM_TABLE_185)/sizeof(ixDPM_TABLE_185[0]), 0, 0 },
+	{ "ixDPM_TABLE_186", REG_SMC, 0x3f47c, &ixDPM_TABLE_186[0], sizeof(ixDPM_TABLE_186)/sizeof(ixDPM_TABLE_186[0]), 0, 0 },
+	{ "ixDPM_TABLE_187", REG_SMC, 0x3f480, &ixDPM_TABLE_187[0], sizeof(ixDPM_TABLE_187)/sizeof(ixDPM_TABLE_187[0]), 0, 0 },
+	{ "ixDPM_TABLE_188", REG_SMC, 0x3f484, &ixDPM_TABLE_188[0], sizeof(ixDPM_TABLE_188)/sizeof(ixDPM_TABLE_188[0]), 0, 0 },
+	{ "ixDPM_TABLE_189", REG_SMC, 0x3f488, &ixDPM_TABLE_189[0], sizeof(ixDPM_TABLE_189)/sizeof(ixDPM_TABLE_189[0]), 0, 0 },
+	{ "ixDPM_TABLE_190", REG_SMC, 0x3f48c, &ixDPM_TABLE_190[0], sizeof(ixDPM_TABLE_190)/sizeof(ixDPM_TABLE_190[0]), 0, 0 },
+	{ "ixDPM_TABLE_191", REG_SMC, 0x3f490, &ixDPM_TABLE_191[0], sizeof(ixDPM_TABLE_191)/sizeof(ixDPM_TABLE_191[0]), 0, 0 },
+	{ "ixDPM_TABLE_192", REG_SMC, 0x3f494, &ixDPM_TABLE_192[0], sizeof(ixDPM_TABLE_192)/sizeof(ixDPM_TABLE_192[0]), 0, 0 },
+	{ "ixDPM_TABLE_193", REG_SMC, 0x3f498, &ixDPM_TABLE_193[0], sizeof(ixDPM_TABLE_193)/sizeof(ixDPM_TABLE_193[0]), 0, 0 },
+	{ "ixDPM_TABLE_194", REG_SMC, 0x3f49c, &ixDPM_TABLE_194[0], sizeof(ixDPM_TABLE_194)/sizeof(ixDPM_TABLE_194[0]), 0, 0 },
+	{ "ixDPM_TABLE_195", REG_SMC, 0x3f4a0, &ixDPM_TABLE_195[0], sizeof(ixDPM_TABLE_195)/sizeof(ixDPM_TABLE_195[0]), 0, 0 },
+	{ "ixDPM_TABLE_196", REG_SMC, 0x3f4a4, &ixDPM_TABLE_196[0], sizeof(ixDPM_TABLE_196)/sizeof(ixDPM_TABLE_196[0]), 0, 0 },
+	{ "ixDPM_TABLE_197", REG_SMC, 0x3f4a8, &ixDPM_TABLE_197[0], sizeof(ixDPM_TABLE_197)/sizeof(ixDPM_TABLE_197[0]), 0, 0 },
+	{ "ixDPM_TABLE_198", REG_SMC, 0x3f4ac, &ixDPM_TABLE_198[0], sizeof(ixDPM_TABLE_198)/sizeof(ixDPM_TABLE_198[0]), 0, 0 },
+	{ "ixDPM_TABLE_199", REG_SMC, 0x3f4b0, &ixDPM_TABLE_199[0], sizeof(ixDPM_TABLE_199)/sizeof(ixDPM_TABLE_199[0]), 0, 0 },
+	{ "ixDPM_TABLE_200", REG_SMC, 0x3f4b4, &ixDPM_TABLE_200[0], sizeof(ixDPM_TABLE_200)/sizeof(ixDPM_TABLE_200[0]), 0, 0 },
+	{ "ixDPM_TABLE_201", REG_SMC, 0x3f4b8, &ixDPM_TABLE_201[0], sizeof(ixDPM_TABLE_201)/sizeof(ixDPM_TABLE_201[0]), 0, 0 },
+	{ "ixDPM_TABLE_202", REG_SMC, 0x3f4bc, &ixDPM_TABLE_202[0], sizeof(ixDPM_TABLE_202)/sizeof(ixDPM_TABLE_202[0]), 0, 0 },
+	{ "ixDPM_TABLE_203", REG_SMC, 0x3f4c0, &ixDPM_TABLE_203[0], sizeof(ixDPM_TABLE_203)/sizeof(ixDPM_TABLE_203[0]), 0, 0 },
+	{ "ixDPM_TABLE_204", REG_SMC, 0x3f4c4, &ixDPM_TABLE_204[0], sizeof(ixDPM_TABLE_204)/sizeof(ixDPM_TABLE_204[0]), 0, 0 },
+	{ "ixDPM_TABLE_205", REG_SMC, 0x3f4c8, &ixDPM_TABLE_205[0], sizeof(ixDPM_TABLE_205)/sizeof(ixDPM_TABLE_205[0]), 0, 0 },
+	{ "ixDPM_TABLE_206", REG_SMC, 0x3f4cc, &ixDPM_TABLE_206[0], sizeof(ixDPM_TABLE_206)/sizeof(ixDPM_TABLE_206[0]), 0, 0 },
+	{ "ixDPM_TABLE_207", REG_SMC, 0x3f4d0, &ixDPM_TABLE_207[0], sizeof(ixDPM_TABLE_207)/sizeof(ixDPM_TABLE_207[0]), 0, 0 },
+	{ "ixDPM_TABLE_208", REG_SMC, 0x3f4d4, &ixDPM_TABLE_208[0], sizeof(ixDPM_TABLE_208)/sizeof(ixDPM_TABLE_208[0]), 0, 0 },
+	{ "ixDPM_TABLE_209", REG_SMC, 0x3f4d8, &ixDPM_TABLE_209[0], sizeof(ixDPM_TABLE_209)/sizeof(ixDPM_TABLE_209[0]), 0, 0 },
+	{ "ixDPM_TABLE_210", REG_SMC, 0x3f4dc, &ixDPM_TABLE_210[0], sizeof(ixDPM_TABLE_210)/sizeof(ixDPM_TABLE_210[0]), 0, 0 },
+	{ "ixDPM_TABLE_211", REG_SMC, 0x3f4e0, &ixDPM_TABLE_211[0], sizeof(ixDPM_TABLE_211)/sizeof(ixDPM_TABLE_211[0]), 0, 0 },
+	{ "ixDPM_TABLE_212", REG_SMC, 0x3f4e4, &ixDPM_TABLE_212[0], sizeof(ixDPM_TABLE_212)/sizeof(ixDPM_TABLE_212[0]), 0, 0 },
+	{ "ixDPM_TABLE_213", REG_SMC, 0x3f4e8, &ixDPM_TABLE_213[0], sizeof(ixDPM_TABLE_213)/sizeof(ixDPM_TABLE_213[0]), 0, 0 },
+	{ "ixDPM_TABLE_214", REG_SMC, 0x3f4ec, &ixDPM_TABLE_214[0], sizeof(ixDPM_TABLE_214)/sizeof(ixDPM_TABLE_214[0]), 0, 0 },
+	{ "ixDPM_TABLE_215", REG_SMC, 0x3f4f0, &ixDPM_TABLE_215[0], sizeof(ixDPM_TABLE_215)/sizeof(ixDPM_TABLE_215[0]), 0, 0 },
+	{ "ixDPM_TABLE_216", REG_SMC, 0x3f4f4, &ixDPM_TABLE_216[0], sizeof(ixDPM_TABLE_216)/sizeof(ixDPM_TABLE_216[0]), 0, 0 },
+	{ "ixDPM_TABLE_217", REG_SMC, 0x3f4f8, &ixDPM_TABLE_217[0], sizeof(ixDPM_TABLE_217)/sizeof(ixDPM_TABLE_217[0]), 0, 0 },
+	{ "ixDPM_TABLE_218", REG_SMC, 0x3f4fc, &ixDPM_TABLE_218[0], sizeof(ixDPM_TABLE_218)/sizeof(ixDPM_TABLE_218[0]), 0, 0 },
+	{ "ixDPM_TABLE_219", REG_SMC, 0x3f500, &ixDPM_TABLE_219[0], sizeof(ixDPM_TABLE_219)/sizeof(ixDPM_TABLE_219[0]), 0, 0 },
+	{ "ixDPM_TABLE_220", REG_SMC, 0x3f504, &ixDPM_TABLE_220[0], sizeof(ixDPM_TABLE_220)/sizeof(ixDPM_TABLE_220[0]), 0, 0 },
+	{ "ixDPM_TABLE_221", REG_SMC, 0x3f508, &ixDPM_TABLE_221[0], sizeof(ixDPM_TABLE_221)/sizeof(ixDPM_TABLE_221[0]), 0, 0 },
+	{ "ixDPM_TABLE_222", REG_SMC, 0x3f50c, &ixDPM_TABLE_222[0], sizeof(ixDPM_TABLE_222)/sizeof(ixDPM_TABLE_222[0]), 0, 0 },
+	{ "ixDPM_TABLE_223", REG_SMC, 0x3f510, &ixDPM_TABLE_223[0], sizeof(ixDPM_TABLE_223)/sizeof(ixDPM_TABLE_223[0]), 0, 0 },
+	{ "ixDPM_TABLE_224", REG_SMC, 0x3f514, &ixDPM_TABLE_224[0], sizeof(ixDPM_TABLE_224)/sizeof(ixDPM_TABLE_224[0]), 0, 0 },
+	{ "ixDPM_TABLE_225", REG_SMC, 0x3f518, &ixDPM_TABLE_225[0], sizeof(ixDPM_TABLE_225)/sizeof(ixDPM_TABLE_225[0]), 0, 0 },
+	{ "ixDPM_TABLE_226", REG_SMC, 0x3f51c, &ixDPM_TABLE_226[0], sizeof(ixDPM_TABLE_226)/sizeof(ixDPM_TABLE_226[0]), 0, 0 },
+	{ "ixDPM_TABLE_227", REG_SMC, 0x3f520, &ixDPM_TABLE_227[0], sizeof(ixDPM_TABLE_227)/sizeof(ixDPM_TABLE_227[0]), 0, 0 },
+	{ "ixDPM_TABLE_228", REG_SMC, 0x3f524, &ixDPM_TABLE_228[0], sizeof(ixDPM_TABLE_228)/sizeof(ixDPM_TABLE_228[0]), 0, 0 },
+	{ "ixDPM_TABLE_229", REG_SMC, 0x3f528, &ixDPM_TABLE_229[0], sizeof(ixDPM_TABLE_229)/sizeof(ixDPM_TABLE_229[0]), 0, 0 },
+	{ "ixDPM_TABLE_230", REG_SMC, 0x3f52c, &ixDPM_TABLE_230[0], sizeof(ixDPM_TABLE_230)/sizeof(ixDPM_TABLE_230[0]), 0, 0 },
+	{ "ixDPM_TABLE_231", REG_SMC, 0x3f530, &ixDPM_TABLE_231[0], sizeof(ixDPM_TABLE_231)/sizeof(ixDPM_TABLE_231[0]), 0, 0 },
+	{ "ixDPM_TABLE_232", REG_SMC, 0x3f534, &ixDPM_TABLE_232[0], sizeof(ixDPM_TABLE_232)/sizeof(ixDPM_TABLE_232[0]), 0, 0 },
+	{ "ixDPM_TABLE_233", REG_SMC, 0x3f538, &ixDPM_TABLE_233[0], sizeof(ixDPM_TABLE_233)/sizeof(ixDPM_TABLE_233[0]), 0, 0 },
+	{ "ixDPM_TABLE_234", REG_SMC, 0x3f53c, &ixDPM_TABLE_234[0], sizeof(ixDPM_TABLE_234)/sizeof(ixDPM_TABLE_234[0]), 0, 0 },
+	{ "ixDPM_TABLE_235", REG_SMC, 0x3f540, &ixDPM_TABLE_235[0], sizeof(ixDPM_TABLE_235)/sizeof(ixDPM_TABLE_235[0]), 0, 0 },
+	{ "ixDPM_TABLE_236", REG_SMC, 0x3f544, &ixDPM_TABLE_236[0], sizeof(ixDPM_TABLE_236)/sizeof(ixDPM_TABLE_236[0]), 0, 0 },
+	{ "ixDPM_TABLE_237", REG_SMC, 0x3f548, &ixDPM_TABLE_237[0], sizeof(ixDPM_TABLE_237)/sizeof(ixDPM_TABLE_237[0]), 0, 0 },
+	{ "ixDPM_TABLE_238", REG_SMC, 0x3f54c, &ixDPM_TABLE_238[0], sizeof(ixDPM_TABLE_238)/sizeof(ixDPM_TABLE_238[0]), 0, 0 },
+	{ "ixDPM_TABLE_239", REG_SMC, 0x3f550, &ixDPM_TABLE_239[0], sizeof(ixDPM_TABLE_239)/sizeof(ixDPM_TABLE_239[0]), 0, 0 },
+	{ "ixDPM_TABLE_240", REG_SMC, 0x3f554, &ixDPM_TABLE_240[0], sizeof(ixDPM_TABLE_240)/sizeof(ixDPM_TABLE_240[0]), 0, 0 },
+	{ "ixDPM_TABLE_241", REG_SMC, 0x3f558, &ixDPM_TABLE_241[0], sizeof(ixDPM_TABLE_241)/sizeof(ixDPM_TABLE_241[0]), 0, 0 },
+	{ "ixDPM_TABLE_242", REG_SMC, 0x3f55c, &ixDPM_TABLE_242[0], sizeof(ixDPM_TABLE_242)/sizeof(ixDPM_TABLE_242[0]), 0, 0 },
+	{ "ixDPM_TABLE_243", REG_SMC, 0x3f560, &ixDPM_TABLE_243[0], sizeof(ixDPM_TABLE_243)/sizeof(ixDPM_TABLE_243[0]), 0, 0 },
+	{ "ixDPM_TABLE_244", REG_SMC, 0x3f564, &ixDPM_TABLE_244[0], sizeof(ixDPM_TABLE_244)/sizeof(ixDPM_TABLE_244[0]), 0, 0 },
+	{ "ixDPM_TABLE_245", REG_SMC, 0x3f568, &ixDPM_TABLE_245[0], sizeof(ixDPM_TABLE_245)/sizeof(ixDPM_TABLE_245[0]), 0, 0 },
+	{ "ixDPM_TABLE_246", REG_SMC, 0x3f56c, &ixDPM_TABLE_246[0], sizeof(ixDPM_TABLE_246)/sizeof(ixDPM_TABLE_246[0]), 0, 0 },
+	{ "ixDPM_TABLE_247", REG_SMC, 0x3f570, &ixDPM_TABLE_247[0], sizeof(ixDPM_TABLE_247)/sizeof(ixDPM_TABLE_247[0]), 0, 0 },
+	{ "ixDPM_TABLE_248", REG_SMC, 0x3f574, &ixDPM_TABLE_248[0], sizeof(ixDPM_TABLE_248)/sizeof(ixDPM_TABLE_248[0]), 0, 0 },
+	{ "ixDPM_TABLE_249", REG_SMC, 0x3f578, &ixDPM_TABLE_249[0], sizeof(ixDPM_TABLE_249)/sizeof(ixDPM_TABLE_249[0]), 0, 0 },
+	{ "ixDPM_TABLE_250", REG_SMC, 0x3f57c, &ixDPM_TABLE_250[0], sizeof(ixDPM_TABLE_250)/sizeof(ixDPM_TABLE_250[0]), 0, 0 },
+	{ "ixDPM_TABLE_251", REG_SMC, 0x3f580, &ixDPM_TABLE_251[0], sizeof(ixDPM_TABLE_251)/sizeof(ixDPM_TABLE_251[0]), 0, 0 },
+	{ "ixDPM_TABLE_252", REG_SMC, 0x3f584, &ixDPM_TABLE_252[0], sizeof(ixDPM_TABLE_252)/sizeof(ixDPM_TABLE_252[0]), 0, 0 },
+	{ "ixDPM_TABLE_253", REG_SMC, 0x3f588, &ixDPM_TABLE_253[0], sizeof(ixDPM_TABLE_253)/sizeof(ixDPM_TABLE_253[0]), 0, 0 },
+	{ "ixDPM_TABLE_254", REG_SMC, 0x3f58c, &ixDPM_TABLE_254[0], sizeof(ixDPM_TABLE_254)/sizeof(ixDPM_TABLE_254[0]), 0, 0 },
+	{ "ixDPM_TABLE_255", REG_SMC, 0x3f590, &ixDPM_TABLE_255[0], sizeof(ixDPM_TABLE_255)/sizeof(ixDPM_TABLE_255[0]), 0, 0 },
+	{ "ixDPM_TABLE_256", REG_SMC, 0x3f594, &ixDPM_TABLE_256[0], sizeof(ixDPM_TABLE_256)/sizeof(ixDPM_TABLE_256[0]), 0, 0 },
+	{ "ixDPM_TABLE_257", REG_SMC, 0x3f598, &ixDPM_TABLE_257[0], sizeof(ixDPM_TABLE_257)/sizeof(ixDPM_TABLE_257[0]), 0, 0 },
+	{ "ixDPM_TABLE_258", REG_SMC, 0x3f59c, &ixDPM_TABLE_258[0], sizeof(ixDPM_TABLE_258)/sizeof(ixDPM_TABLE_258[0]), 0, 0 },
+	{ "ixDPM_TABLE_259", REG_SMC, 0x3f5a0, &ixDPM_TABLE_259[0], sizeof(ixDPM_TABLE_259)/sizeof(ixDPM_TABLE_259[0]), 0, 0 },
+	{ "ixDPM_TABLE_260", REG_SMC, 0x3f5a4, &ixDPM_TABLE_260[0], sizeof(ixDPM_TABLE_260)/sizeof(ixDPM_TABLE_260[0]), 0, 0 },
+	{ "ixDPM_TABLE_261", REG_SMC, 0x3f5a8, &ixDPM_TABLE_261[0], sizeof(ixDPM_TABLE_261)/sizeof(ixDPM_TABLE_261[0]), 0, 0 },
+	{ "ixDPM_TABLE_262", REG_SMC, 0x3f5ac, &ixDPM_TABLE_262[0], sizeof(ixDPM_TABLE_262)/sizeof(ixDPM_TABLE_262[0]), 0, 0 },
+	{ "ixDPM_TABLE_263", REG_SMC, 0x3f5b0, &ixDPM_TABLE_263[0], sizeof(ixDPM_TABLE_263)/sizeof(ixDPM_TABLE_263[0]), 0, 0 },
+	{ "ixDPM_TABLE_264", REG_SMC, 0x3f5b4, &ixDPM_TABLE_264[0], sizeof(ixDPM_TABLE_264)/sizeof(ixDPM_TABLE_264[0]), 0, 0 },
+	{ "ixDPM_TABLE_265", REG_SMC, 0x3f5b8, &ixDPM_TABLE_265[0], sizeof(ixDPM_TABLE_265)/sizeof(ixDPM_TABLE_265[0]), 0, 0 },
+	{ "ixDPM_TABLE_266", REG_SMC, 0x3f5bc, &ixDPM_TABLE_266[0], sizeof(ixDPM_TABLE_266)/sizeof(ixDPM_TABLE_266[0]), 0, 0 },
+	{ "ixDPM_TABLE_267", REG_SMC, 0x3f5c0, &ixDPM_TABLE_267[0], sizeof(ixDPM_TABLE_267)/sizeof(ixDPM_TABLE_267[0]), 0, 0 },
+	{ "ixDPM_TABLE_268", REG_SMC, 0x3f5c4, &ixDPM_TABLE_268[0], sizeof(ixDPM_TABLE_268)/sizeof(ixDPM_TABLE_268[0]), 0, 0 },
+	{ "ixDPM_TABLE_269", REG_SMC, 0x3f5c8, &ixDPM_TABLE_269[0], sizeof(ixDPM_TABLE_269)/sizeof(ixDPM_TABLE_269[0]), 0, 0 },
+	{ "ixDPM_TABLE_270", REG_SMC, 0x3f5cc, &ixDPM_TABLE_270[0], sizeof(ixDPM_TABLE_270)/sizeof(ixDPM_TABLE_270[0]), 0, 0 },
+	{ "ixDPM_TABLE_271", REG_SMC, 0x3f5d0, &ixDPM_TABLE_271[0], sizeof(ixDPM_TABLE_271)/sizeof(ixDPM_TABLE_271[0]), 0, 0 },
+	{ "ixDPM_TABLE_272", REG_SMC, 0x3f5d4, &ixDPM_TABLE_272[0], sizeof(ixDPM_TABLE_272)/sizeof(ixDPM_TABLE_272[0]), 0, 0 },
+	{ "ixDPM_TABLE_273", REG_SMC, 0x3f5d8, &ixDPM_TABLE_273[0], sizeof(ixDPM_TABLE_273)/sizeof(ixDPM_TABLE_273[0]), 0, 0 },
+	{ "ixDPM_TABLE_274", REG_SMC, 0x3f5dc, &ixDPM_TABLE_274[0], sizeof(ixDPM_TABLE_274)/sizeof(ixDPM_TABLE_274[0]), 0, 0 },
+	{ "ixDPM_TABLE_275", REG_SMC, 0x3f5e0, &ixDPM_TABLE_275[0], sizeof(ixDPM_TABLE_275)/sizeof(ixDPM_TABLE_275[0]), 0, 0 },
+	{ "ixDPM_TABLE_276", REG_SMC, 0x3f5e4, &ixDPM_TABLE_276[0], sizeof(ixDPM_TABLE_276)/sizeof(ixDPM_TABLE_276[0]), 0, 0 },
+	{ "ixDPM_TABLE_277", REG_SMC, 0x3f5e8, &ixDPM_TABLE_277[0], sizeof(ixDPM_TABLE_277)/sizeof(ixDPM_TABLE_277[0]), 0, 0 },
+	{ "ixDPM_TABLE_278", REG_SMC, 0x3f5ec, &ixDPM_TABLE_278[0], sizeof(ixDPM_TABLE_278)/sizeof(ixDPM_TABLE_278[0]), 0, 0 },
+	{ "ixDPM_TABLE_279", REG_SMC, 0x3f5f0, &ixDPM_TABLE_279[0], sizeof(ixDPM_TABLE_279)/sizeof(ixDPM_TABLE_279[0]), 0, 0 },
+	{ "ixDPM_TABLE_280", REG_SMC, 0x3f5f4, &ixDPM_TABLE_280[0], sizeof(ixDPM_TABLE_280)/sizeof(ixDPM_TABLE_280[0]), 0, 0 },
+	{ "ixDPM_TABLE_281", REG_SMC, 0x3f5f8, &ixDPM_TABLE_281[0], sizeof(ixDPM_TABLE_281)/sizeof(ixDPM_TABLE_281[0]), 0, 0 },
+	{ "ixDPM_TABLE_282", REG_SMC, 0x3f5fc, &ixDPM_TABLE_282[0], sizeof(ixDPM_TABLE_282)/sizeof(ixDPM_TABLE_282[0]), 0, 0 },
+	{ "ixDPM_TABLE_283", REG_SMC, 0x3f600, &ixDPM_TABLE_283[0], sizeof(ixDPM_TABLE_283)/sizeof(ixDPM_TABLE_283[0]), 0, 0 },
+	{ "ixDPM_TABLE_284", REG_SMC, 0x3f604, &ixDPM_TABLE_284[0], sizeof(ixDPM_TABLE_284)/sizeof(ixDPM_TABLE_284[0]), 0, 0 },
+	{ "ixDPM_TABLE_285", REG_SMC, 0x3f608, &ixDPM_TABLE_285[0], sizeof(ixDPM_TABLE_285)/sizeof(ixDPM_TABLE_285[0]), 0, 0 },
+	{ "ixDPM_TABLE_286", REG_SMC, 0x3f60c, &ixDPM_TABLE_286[0], sizeof(ixDPM_TABLE_286)/sizeof(ixDPM_TABLE_286[0]), 0, 0 },
+	{ "ixDPM_TABLE_287", REG_SMC, 0x3f610, &ixDPM_TABLE_287[0], sizeof(ixDPM_TABLE_287)/sizeof(ixDPM_TABLE_287[0]), 0, 0 },
+	{ "ixDPM_TABLE_288", REG_SMC, 0x3f614, &ixDPM_TABLE_288[0], sizeof(ixDPM_TABLE_288)/sizeof(ixDPM_TABLE_288[0]), 0, 0 },
+	{ "ixDPM_TABLE_289", REG_SMC, 0x3f618, &ixDPM_TABLE_289[0], sizeof(ixDPM_TABLE_289)/sizeof(ixDPM_TABLE_289[0]), 0, 0 },
+	{ "ixDPM_TABLE_290", REG_SMC, 0x3f61c, &ixDPM_TABLE_290[0], sizeof(ixDPM_TABLE_290)/sizeof(ixDPM_TABLE_290[0]), 0, 0 },
+	{ "ixDPM_TABLE_291", REG_SMC, 0x3f620, &ixDPM_TABLE_291[0], sizeof(ixDPM_TABLE_291)/sizeof(ixDPM_TABLE_291[0]), 0, 0 },
+	{ "ixDPM_TABLE_292", REG_SMC, 0x3f624, &ixDPM_TABLE_292[0], sizeof(ixDPM_TABLE_292)/sizeof(ixDPM_TABLE_292[0]), 0, 0 },
+	{ "ixDPM_TABLE_293", REG_SMC, 0x3f628, &ixDPM_TABLE_293[0], sizeof(ixDPM_TABLE_293)/sizeof(ixDPM_TABLE_293[0]), 0, 0 },
+	{ "ixDPM_TABLE_294", REG_SMC, 0x3f62c, &ixDPM_TABLE_294[0], sizeof(ixDPM_TABLE_294)/sizeof(ixDPM_TABLE_294[0]), 0, 0 },
+	{ "ixDPM_TABLE_295", REG_SMC, 0x3f630, &ixDPM_TABLE_295[0], sizeof(ixDPM_TABLE_295)/sizeof(ixDPM_TABLE_295[0]), 0, 0 },
+	{ "ixDPM_TABLE_296", REG_SMC, 0x3f634, &ixDPM_TABLE_296[0], sizeof(ixDPM_TABLE_296)/sizeof(ixDPM_TABLE_296[0]), 0, 0 },
+	{ "ixDPM_TABLE_297", REG_SMC, 0x3f638, &ixDPM_TABLE_297[0], sizeof(ixDPM_TABLE_297)/sizeof(ixDPM_TABLE_297[0]), 0, 0 },
+	{ "ixDPM_TABLE_298", REG_SMC, 0x3f63c, &ixDPM_TABLE_298[0], sizeof(ixDPM_TABLE_298)/sizeof(ixDPM_TABLE_298[0]), 0, 0 },
+	{ "ixDPM_TABLE_299", REG_SMC, 0x3f640, &ixDPM_TABLE_299[0], sizeof(ixDPM_TABLE_299)/sizeof(ixDPM_TABLE_299[0]), 0, 0 },
+	{ "ixDPM_TABLE_300", REG_SMC, 0x3f644, &ixDPM_TABLE_300[0], sizeof(ixDPM_TABLE_300)/sizeof(ixDPM_TABLE_300[0]), 0, 0 },
+	{ "ixDPM_TABLE_301", REG_SMC, 0x3f648, &ixDPM_TABLE_301[0], sizeof(ixDPM_TABLE_301)/sizeof(ixDPM_TABLE_301[0]), 0, 0 },
+	{ "ixDPM_TABLE_302", REG_SMC, 0x3f64c, &ixDPM_TABLE_302[0], sizeof(ixDPM_TABLE_302)/sizeof(ixDPM_TABLE_302[0]), 0, 0 },
+	{ "ixDPM_TABLE_303", REG_SMC, 0x3f650, &ixDPM_TABLE_303[0], sizeof(ixDPM_TABLE_303)/sizeof(ixDPM_TABLE_303[0]), 0, 0 },
+	{ "ixDPM_TABLE_304", REG_SMC, 0x3f654, &ixDPM_TABLE_304[0], sizeof(ixDPM_TABLE_304)/sizeof(ixDPM_TABLE_304[0]), 0, 0 },
+	{ "ixDPM_TABLE_305", REG_SMC, 0x3f658, &ixDPM_TABLE_305[0], sizeof(ixDPM_TABLE_305)/sizeof(ixDPM_TABLE_305[0]), 0, 0 },
+	{ "ixDPM_TABLE_306", REG_SMC, 0x3f65c, &ixDPM_TABLE_306[0], sizeof(ixDPM_TABLE_306)/sizeof(ixDPM_TABLE_306[0]), 0, 0 },
+	{ "ixDPM_TABLE_307", REG_SMC, 0x3f660, &ixDPM_TABLE_307[0], sizeof(ixDPM_TABLE_307)/sizeof(ixDPM_TABLE_307[0]), 0, 0 },
+	{ "ixDPM_TABLE_308", REG_SMC, 0x3f664, &ixDPM_TABLE_308[0], sizeof(ixDPM_TABLE_308)/sizeof(ixDPM_TABLE_308[0]), 0, 0 },
+	{ "ixDPM_TABLE_309", REG_SMC, 0x3f668, &ixDPM_TABLE_309[0], sizeof(ixDPM_TABLE_309)/sizeof(ixDPM_TABLE_309[0]), 0, 0 },
+	{ "ixDPM_TABLE_310", REG_SMC, 0x3f66c, &ixDPM_TABLE_310[0], sizeof(ixDPM_TABLE_310)/sizeof(ixDPM_TABLE_310[0]), 0, 0 },
+	{ "ixDPM_TABLE_311", REG_SMC, 0x3f670, &ixDPM_TABLE_311[0], sizeof(ixDPM_TABLE_311)/sizeof(ixDPM_TABLE_311[0]), 0, 0 },
+	{ "ixDPM_TABLE_312", REG_SMC, 0x3f674, &ixDPM_TABLE_312[0], sizeof(ixDPM_TABLE_312)/sizeof(ixDPM_TABLE_312[0]), 0, 0 },
+	{ "ixDPM_TABLE_313", REG_SMC, 0x3f678, &ixDPM_TABLE_313[0], sizeof(ixDPM_TABLE_313)/sizeof(ixDPM_TABLE_313[0]), 0, 0 },
+	{ "ixDPM_TABLE_314", REG_SMC, 0x3f67c, &ixDPM_TABLE_314[0], sizeof(ixDPM_TABLE_314)/sizeof(ixDPM_TABLE_314[0]), 0, 0 },
+	{ "ixDPM_TABLE_315", REG_SMC, 0x3f680, &ixDPM_TABLE_315[0], sizeof(ixDPM_TABLE_315)/sizeof(ixDPM_TABLE_315[0]), 0, 0 },
+	{ "ixDPM_TABLE_316", REG_SMC, 0x3f684, &ixDPM_TABLE_316[0], sizeof(ixDPM_TABLE_316)/sizeof(ixDPM_TABLE_316[0]), 0, 0 },
+	{ "ixDPM_TABLE_317", REG_SMC, 0x3f688, &ixDPM_TABLE_317[0], sizeof(ixDPM_TABLE_317)/sizeof(ixDPM_TABLE_317[0]), 0, 0 },
+	{ "ixDPM_TABLE_318", REG_SMC, 0x3f68c, &ixDPM_TABLE_318[0], sizeof(ixDPM_TABLE_318)/sizeof(ixDPM_TABLE_318[0]), 0, 0 },
+	{ "ixDPM_TABLE_319", REG_SMC, 0x3f690, &ixDPM_TABLE_319[0], sizeof(ixDPM_TABLE_319)/sizeof(ixDPM_TABLE_319[0]), 0, 0 },
+	{ "ixDPM_TABLE_320", REG_SMC, 0x3f694, &ixDPM_TABLE_320[0], sizeof(ixDPM_TABLE_320)/sizeof(ixDPM_TABLE_320[0]), 0, 0 },
+	{ "ixDPM_TABLE_321", REG_SMC, 0x3f698, &ixDPM_TABLE_321[0], sizeof(ixDPM_TABLE_321)/sizeof(ixDPM_TABLE_321[0]), 0, 0 },
+	{ "ixDPM_TABLE_322", REG_SMC, 0x3f69c, &ixDPM_TABLE_322[0], sizeof(ixDPM_TABLE_322)/sizeof(ixDPM_TABLE_322[0]), 0, 0 },
+	{ "ixDPM_TABLE_323", REG_SMC, 0x3f6a0, &ixDPM_TABLE_323[0], sizeof(ixDPM_TABLE_323)/sizeof(ixDPM_TABLE_323[0]), 0, 0 },
+	{ "ixDPM_TABLE_324", REG_SMC, 0x3f6a4, &ixDPM_TABLE_324[0], sizeof(ixDPM_TABLE_324)/sizeof(ixDPM_TABLE_324[0]), 0, 0 },
+	{ "ixDPM_TABLE_325", REG_SMC, 0x3f6a8, &ixDPM_TABLE_325[0], sizeof(ixDPM_TABLE_325)/sizeof(ixDPM_TABLE_325[0]), 0, 0 },
+	{ "ixDPM_TABLE_326", REG_SMC, 0x3f6ac, &ixDPM_TABLE_326[0], sizeof(ixDPM_TABLE_326)/sizeof(ixDPM_TABLE_326[0]), 0, 0 },
+	{ "ixDPM_TABLE_327", REG_SMC, 0x3f6b0, &ixDPM_TABLE_327[0], sizeof(ixDPM_TABLE_327)/sizeof(ixDPM_TABLE_327[0]), 0, 0 },
+	{ "ixDPM_TABLE_328", REG_SMC, 0x3f6b4, &ixDPM_TABLE_328[0], sizeof(ixDPM_TABLE_328)/sizeof(ixDPM_TABLE_328[0]), 0, 0 },
+	{ "ixDPM_TABLE_329", REG_SMC, 0x3f6b8, &ixDPM_TABLE_329[0], sizeof(ixDPM_TABLE_329)/sizeof(ixDPM_TABLE_329[0]), 0, 0 },
+	{ "ixDPM_TABLE_330", REG_SMC, 0x3f6bc, &ixDPM_TABLE_330[0], sizeof(ixDPM_TABLE_330)/sizeof(ixDPM_TABLE_330[0]), 0, 0 },
+	{ "ixDPM_TABLE_331", REG_SMC, 0x3f6c0, &ixDPM_TABLE_331[0], sizeof(ixDPM_TABLE_331)/sizeof(ixDPM_TABLE_331[0]), 0, 0 },
+	{ "ixDPM_TABLE_332", REG_SMC, 0x3f6c4, &ixDPM_TABLE_332[0], sizeof(ixDPM_TABLE_332)/sizeof(ixDPM_TABLE_332[0]), 0, 0 },
+	{ "ixDPM_TABLE_333", REG_SMC, 0x3f6c8, &ixDPM_TABLE_333[0], sizeof(ixDPM_TABLE_333)/sizeof(ixDPM_TABLE_333[0]), 0, 0 },
+	{ "ixDPM_TABLE_334", REG_SMC, 0x3f6cc, &ixDPM_TABLE_334[0], sizeof(ixDPM_TABLE_334)/sizeof(ixDPM_TABLE_334[0]), 0, 0 },
+	{ "ixDPM_TABLE_335", REG_SMC, 0x3f6d0, &ixDPM_TABLE_335[0], sizeof(ixDPM_TABLE_335)/sizeof(ixDPM_TABLE_335[0]), 0, 0 },
+	{ "ixDPM_TABLE_336", REG_SMC, 0x3f6d4, &ixDPM_TABLE_336[0], sizeof(ixDPM_TABLE_336)/sizeof(ixDPM_TABLE_336[0]), 0, 0 },
+	{ "ixDPM_TABLE_337", REG_SMC, 0x3f6d8, &ixDPM_TABLE_337[0], sizeof(ixDPM_TABLE_337)/sizeof(ixDPM_TABLE_337[0]), 0, 0 },
+	{ "ixDPM_TABLE_338", REG_SMC, 0x3f6dc, &ixDPM_TABLE_338[0], sizeof(ixDPM_TABLE_338)/sizeof(ixDPM_TABLE_338[0]), 0, 0 },
+	{ "ixDPM_TABLE_339", REG_SMC, 0x3f6e0, &ixDPM_TABLE_339[0], sizeof(ixDPM_TABLE_339)/sizeof(ixDPM_TABLE_339[0]), 0, 0 },
+	{ "ixDPM_TABLE_340", REG_SMC, 0x3f6e4, &ixDPM_TABLE_340[0], sizeof(ixDPM_TABLE_340)/sizeof(ixDPM_TABLE_340[0]), 0, 0 },
+	{ "ixDPM_TABLE_341", REG_SMC, 0x3f6e8, &ixDPM_TABLE_341[0], sizeof(ixDPM_TABLE_341)/sizeof(ixDPM_TABLE_341[0]), 0, 0 },
+	{ "ixDPM_TABLE_342", REG_SMC, 0x3f6ec, &ixDPM_TABLE_342[0], sizeof(ixDPM_TABLE_342)/sizeof(ixDPM_TABLE_342[0]), 0, 0 },
+	{ "ixDPM_TABLE_343", REG_SMC, 0x3f6f0, &ixDPM_TABLE_343[0], sizeof(ixDPM_TABLE_343)/sizeof(ixDPM_TABLE_343[0]), 0, 0 },
+	{ "ixDPM_TABLE_344", REG_SMC, 0x3f6f4, &ixDPM_TABLE_344[0], sizeof(ixDPM_TABLE_344)/sizeof(ixDPM_TABLE_344[0]), 0, 0 },
+	{ "ixDPM_TABLE_345", REG_SMC, 0x3f6f8, &ixDPM_TABLE_345[0], sizeof(ixDPM_TABLE_345)/sizeof(ixDPM_TABLE_345[0]), 0, 0 },
+	{ "ixDPM_TABLE_346", REG_SMC, 0x3f6fc, &ixDPM_TABLE_346[0], sizeof(ixDPM_TABLE_346)/sizeof(ixDPM_TABLE_346[0]), 0, 0 },
+	{ "ixDPM_TABLE_347", REG_SMC, 0x3f700, &ixDPM_TABLE_347[0], sizeof(ixDPM_TABLE_347)/sizeof(ixDPM_TABLE_347[0]), 0, 0 },
+	{ "ixDPM_TABLE_348", REG_SMC, 0x3f704, &ixDPM_TABLE_348[0], sizeof(ixDPM_TABLE_348)/sizeof(ixDPM_TABLE_348[0]), 0, 0 },
+	{ "ixDPM_TABLE_349", REG_SMC, 0x3f708, &ixDPM_TABLE_349[0], sizeof(ixDPM_TABLE_349)/sizeof(ixDPM_TABLE_349[0]), 0, 0 },
+	{ "ixDPM_TABLE_350", REG_SMC, 0x3f70c, &ixDPM_TABLE_350[0], sizeof(ixDPM_TABLE_350)/sizeof(ixDPM_TABLE_350[0]), 0, 0 },
+	{ "ixDPM_TABLE_351", REG_SMC, 0x3f710, &ixDPM_TABLE_351[0], sizeof(ixDPM_TABLE_351)/sizeof(ixDPM_TABLE_351[0]), 0, 0 },
+	{ "ixDPM_TABLE_352", REG_SMC, 0x3f714, &ixDPM_TABLE_352[0], sizeof(ixDPM_TABLE_352)/sizeof(ixDPM_TABLE_352[0]), 0, 0 },
+	{ "ixDPM_TABLE_353", REG_SMC, 0x3f718, &ixDPM_TABLE_353[0], sizeof(ixDPM_TABLE_353)/sizeof(ixDPM_TABLE_353[0]), 0, 0 },
+	{ "ixDPM_TABLE_354", REG_SMC, 0x3f71c, &ixDPM_TABLE_354[0], sizeof(ixDPM_TABLE_354)/sizeof(ixDPM_TABLE_354[0]), 0, 0 },
+	{ "ixDPM_TABLE_355", REG_SMC, 0x3f720, &ixDPM_TABLE_355[0], sizeof(ixDPM_TABLE_355)/sizeof(ixDPM_TABLE_355[0]), 0, 0 },
+	{ "ixDPM_TABLE_356", REG_SMC, 0x3f724, &ixDPM_TABLE_356[0], sizeof(ixDPM_TABLE_356)/sizeof(ixDPM_TABLE_356[0]), 0, 0 },
+	{ "ixDPM_TABLE_357", REG_SMC, 0x3f728, &ixDPM_TABLE_357[0], sizeof(ixDPM_TABLE_357)/sizeof(ixDPM_TABLE_357[0]), 0, 0 },
+	{ "ixDPM_TABLE_358", REG_SMC, 0x3f72c, &ixDPM_TABLE_358[0], sizeof(ixDPM_TABLE_358)/sizeof(ixDPM_TABLE_358[0]), 0, 0 },
+	{ "ixDPM_TABLE_359", REG_SMC, 0x3f730, &ixDPM_TABLE_359[0], sizeof(ixDPM_TABLE_359)/sizeof(ixDPM_TABLE_359[0]), 0, 0 },
+	{ "ixDPM_TABLE_360", REG_SMC, 0x3f734, &ixDPM_TABLE_360[0], sizeof(ixDPM_TABLE_360)/sizeof(ixDPM_TABLE_360[0]), 0, 0 },
+	{ "ixDPM_TABLE_361", REG_SMC, 0x3f738, &ixDPM_TABLE_361[0], sizeof(ixDPM_TABLE_361)/sizeof(ixDPM_TABLE_361[0]), 0, 0 },
+	{ "ixDPM_TABLE_362", REG_SMC, 0x3f73c, &ixDPM_TABLE_362[0], sizeof(ixDPM_TABLE_362)/sizeof(ixDPM_TABLE_362[0]), 0, 0 },
+	{ "ixDPM_TABLE_363", REG_SMC, 0x3f740, &ixDPM_TABLE_363[0], sizeof(ixDPM_TABLE_363)/sizeof(ixDPM_TABLE_363[0]), 0, 0 },
+	{ "ixDPM_TABLE_364", REG_SMC, 0x3f744, &ixDPM_TABLE_364[0], sizeof(ixDPM_TABLE_364)/sizeof(ixDPM_TABLE_364[0]), 0, 0 },
+	{ "ixDPM_TABLE_365", REG_SMC, 0x3f748, &ixDPM_TABLE_365[0], sizeof(ixDPM_TABLE_365)/sizeof(ixDPM_TABLE_365[0]), 0, 0 },
+	{ "ixDPM_TABLE_366", REG_SMC, 0x3f74c, &ixDPM_TABLE_366[0], sizeof(ixDPM_TABLE_366)/sizeof(ixDPM_TABLE_366[0]), 0, 0 },
+	{ "ixDPM_TABLE_367", REG_SMC, 0x3f750, &ixDPM_TABLE_367[0], sizeof(ixDPM_TABLE_367)/sizeof(ixDPM_TABLE_367[0]), 0, 0 },
+	{ "ixDPM_TABLE_368", REG_SMC, 0x3f754, &ixDPM_TABLE_368[0], sizeof(ixDPM_TABLE_368)/sizeof(ixDPM_TABLE_368[0]), 0, 0 },
+	{ "ixDPM_TABLE_369", REG_SMC, 0x3f758, &ixDPM_TABLE_369[0], sizeof(ixDPM_TABLE_369)/sizeof(ixDPM_TABLE_369[0]), 0, 0 },
+	{ "ixDPM_TABLE_370", REG_SMC, 0x3f75c, &ixDPM_TABLE_370[0], sizeof(ixDPM_TABLE_370)/sizeof(ixDPM_TABLE_370[0]), 0, 0 },
+	{ "ixDPM_TABLE_371", REG_SMC, 0x3f760, &ixDPM_TABLE_371[0], sizeof(ixDPM_TABLE_371)/sizeof(ixDPM_TABLE_371[0]), 0, 0 },
+	{ "ixDPM_TABLE_372", REG_SMC, 0x3f764, &ixDPM_TABLE_372[0], sizeof(ixDPM_TABLE_372)/sizeof(ixDPM_TABLE_372[0]), 0, 0 },
+	{ "ixDPM_TABLE_373", REG_SMC, 0x3f768, &ixDPM_TABLE_373[0], sizeof(ixDPM_TABLE_373)/sizeof(ixDPM_TABLE_373[0]), 0, 0 },
+	{ "ixDPM_TABLE_374", REG_SMC, 0x3f76c, &ixDPM_TABLE_374[0], sizeof(ixDPM_TABLE_374)/sizeof(ixDPM_TABLE_374[0]), 0, 0 },
+	{ "ixDPM_TABLE_375", REG_SMC, 0x3f770, &ixDPM_TABLE_375[0], sizeof(ixDPM_TABLE_375)/sizeof(ixDPM_TABLE_375[0]), 0, 0 },
+	{ "ixDPM_TABLE_376", REG_SMC, 0x3f774, &ixDPM_TABLE_376[0], sizeof(ixDPM_TABLE_376)/sizeof(ixDPM_TABLE_376[0]), 0, 0 },
+	{ "ixDPM_TABLE_377", REG_SMC, 0x3f778, &ixDPM_TABLE_377[0], sizeof(ixDPM_TABLE_377)/sizeof(ixDPM_TABLE_377[0]), 0, 0 },
+	{ "ixDPM_TABLE_378", REG_SMC, 0x3f77c, &ixDPM_TABLE_378[0], sizeof(ixDPM_TABLE_378)/sizeof(ixDPM_TABLE_378[0]), 0, 0 },
+	{ "ixDPM_TABLE_379", REG_SMC, 0x3f780, &ixDPM_TABLE_379[0], sizeof(ixDPM_TABLE_379)/sizeof(ixDPM_TABLE_379[0]), 0, 0 },
+	{ "ixDPM_TABLE_380", REG_SMC, 0x3f784, &ixDPM_TABLE_380[0], sizeof(ixDPM_TABLE_380)/sizeof(ixDPM_TABLE_380[0]), 0, 0 },
+	{ "ixDPM_TABLE_381", REG_SMC, 0x3f788, &ixDPM_TABLE_381[0], sizeof(ixDPM_TABLE_381)/sizeof(ixDPM_TABLE_381[0]), 0, 0 },
+	{ "ixDPM_TABLE_382", REG_SMC, 0x3f78c, &ixDPM_TABLE_382[0], sizeof(ixDPM_TABLE_382)/sizeof(ixDPM_TABLE_382[0]), 0, 0 },
+	{ "ixDPM_TABLE_383", REG_SMC, 0x3f790, &ixDPM_TABLE_383[0], sizeof(ixDPM_TABLE_383)/sizeof(ixDPM_TABLE_383[0]), 0, 0 },
+	{ "ixDPM_TABLE_384", REG_SMC, 0x3f794, &ixDPM_TABLE_384[0], sizeof(ixDPM_TABLE_384)/sizeof(ixDPM_TABLE_384[0]), 0, 0 },
+	{ "ixDPM_TABLE_385", REG_SMC, 0x3f798, &ixDPM_TABLE_385[0], sizeof(ixDPM_TABLE_385)/sizeof(ixDPM_TABLE_385[0]), 0, 0 },
+	{ "ixDPM_TABLE_386", REG_SMC, 0x3f79c, &ixDPM_TABLE_386[0], sizeof(ixDPM_TABLE_386)/sizeof(ixDPM_TABLE_386[0]), 0, 0 },
+	{ "ixDPM_TABLE_387", REG_SMC, 0x3f7a0, &ixDPM_TABLE_387[0], sizeof(ixDPM_TABLE_387)/sizeof(ixDPM_TABLE_387[0]), 0, 0 },
+	{ "ixDPM_TABLE_388", REG_SMC, 0x3f7a4, &ixDPM_TABLE_388[0], sizeof(ixDPM_TABLE_388)/sizeof(ixDPM_TABLE_388[0]), 0, 0 },
+	{ "ixDPM_TABLE_389", REG_SMC, 0x3f7a8, &ixDPM_TABLE_389[0], sizeof(ixDPM_TABLE_389)/sizeof(ixDPM_TABLE_389[0]), 0, 0 },
+	{ "ixDPM_TABLE_390", REG_SMC, 0x3f7ac, &ixDPM_TABLE_390[0], sizeof(ixDPM_TABLE_390)/sizeof(ixDPM_TABLE_390[0]), 0, 0 },
+	{ "ixDPM_TABLE_391", REG_SMC, 0x3f7b0, &ixDPM_TABLE_391[0], sizeof(ixDPM_TABLE_391)/sizeof(ixDPM_TABLE_391[0]), 0, 0 },
+	{ "ixDPM_TABLE_392", REG_SMC, 0x3f7b4, &ixDPM_TABLE_392[0], sizeof(ixDPM_TABLE_392)/sizeof(ixDPM_TABLE_392[0]), 0, 0 },
+	{ "ixDPM_TABLE_393", REG_SMC, 0x3f7b8, &ixDPM_TABLE_393[0], sizeof(ixDPM_TABLE_393)/sizeof(ixDPM_TABLE_393[0]), 0, 0 },
+	{ "ixDPM_TABLE_394", REG_SMC, 0x3f7bc, &ixDPM_TABLE_394[0], sizeof(ixDPM_TABLE_394)/sizeof(ixDPM_TABLE_394[0]), 0, 0 },
+	{ "ixDPM_TABLE_395", REG_SMC, 0x3f7c0, &ixDPM_TABLE_395[0], sizeof(ixDPM_TABLE_395)/sizeof(ixDPM_TABLE_395[0]), 0, 0 },
+	{ "ixDPM_TABLE_396", REG_SMC, 0x3f7c4, &ixDPM_TABLE_396[0], sizeof(ixDPM_TABLE_396)/sizeof(ixDPM_TABLE_396[0]), 0, 0 },
+	{ "ixDPM_TABLE_397", REG_SMC, 0x3f7c8, &ixDPM_TABLE_397[0], sizeof(ixDPM_TABLE_397)/sizeof(ixDPM_TABLE_397[0]), 0, 0 },
+	{ "ixDPM_TABLE_398", REG_SMC, 0x3f7cc, &ixDPM_TABLE_398[0], sizeof(ixDPM_TABLE_398)/sizeof(ixDPM_TABLE_398[0]), 0, 0 },
+	{ "ixDPM_TABLE_399", REG_SMC, 0x3f7d0, &ixDPM_TABLE_399[0], sizeof(ixDPM_TABLE_399)/sizeof(ixDPM_TABLE_399[0]), 0, 0 },
+	{ "ixDPM_TABLE_400", REG_SMC, 0x3f7d4, &ixDPM_TABLE_400[0], sizeof(ixDPM_TABLE_400)/sizeof(ixDPM_TABLE_400[0]), 0, 0 },
+	{ "ixDPM_TABLE_401", REG_SMC, 0x3f7d8, &ixDPM_TABLE_401[0], sizeof(ixDPM_TABLE_401)/sizeof(ixDPM_TABLE_401[0]), 0, 0 },
+	{ "ixDPM_TABLE_402", REG_SMC, 0x3f7dc, &ixDPM_TABLE_402[0], sizeof(ixDPM_TABLE_402)/sizeof(ixDPM_TABLE_402[0]), 0, 0 },
+	{ "ixDPM_TABLE_403", REG_SMC, 0x3f7e0, &ixDPM_TABLE_403[0], sizeof(ixDPM_TABLE_403)/sizeof(ixDPM_TABLE_403[0]), 0, 0 },
+	{ "ixDPM_TABLE_404", REG_SMC, 0x3f7e4, &ixDPM_TABLE_404[0], sizeof(ixDPM_TABLE_404)/sizeof(ixDPM_TABLE_404[0]), 0, 0 },
+	{ "ixDPM_TABLE_405", REG_SMC, 0x3f7e8, &ixDPM_TABLE_405[0], sizeof(ixDPM_TABLE_405)/sizeof(ixDPM_TABLE_405[0]), 0, 0 },
+	{ "ixDPM_TABLE_406", REG_SMC, 0x3f7ec, &ixDPM_TABLE_406[0], sizeof(ixDPM_TABLE_406)/sizeof(ixDPM_TABLE_406[0]), 0, 0 },
+	{ "ixDPM_TABLE_407", REG_SMC, 0x3f7f0, &ixDPM_TABLE_407[0], sizeof(ixDPM_TABLE_407)/sizeof(ixDPM_TABLE_407[0]), 0, 0 },
+	{ "ixDPM_TABLE_408", REG_SMC, 0x3f7f4, &ixDPM_TABLE_408[0], sizeof(ixDPM_TABLE_408)/sizeof(ixDPM_TABLE_408[0]), 0, 0 },
+	{ "ixDPM_TABLE_409", REG_SMC, 0x3f7f8, &ixDPM_TABLE_409[0], sizeof(ixDPM_TABLE_409)/sizeof(ixDPM_TABLE_409[0]), 0, 0 },
+	{ "ixDPM_TABLE_410", REG_SMC, 0x3f7fc, &ixDPM_TABLE_410[0], sizeof(ixDPM_TABLE_410)/sizeof(ixDPM_TABLE_410[0]), 0, 0 },
+	{ "ixDPM_TABLE_411", REG_SMC, 0x3f800, &ixDPM_TABLE_411[0], sizeof(ixDPM_TABLE_411)/sizeof(ixDPM_TABLE_411[0]), 0, 0 },
+	{ "ixDPM_TABLE_412", REG_SMC, 0x3f804, &ixDPM_TABLE_412[0], sizeof(ixDPM_TABLE_412)/sizeof(ixDPM_TABLE_412[0]), 0, 0 },
+	{ "ixDPM_TABLE_413", REG_SMC, 0x3f808, &ixDPM_TABLE_413[0], sizeof(ixDPM_TABLE_413)/sizeof(ixDPM_TABLE_413[0]), 0, 0 },
+	{ "ixDPM_TABLE_414", REG_SMC, 0x3f80c, &ixDPM_TABLE_414[0], sizeof(ixDPM_TABLE_414)/sizeof(ixDPM_TABLE_414[0]), 0, 0 },
+	{ "ixDPM_TABLE_415", REG_SMC, 0x3f810, &ixDPM_TABLE_415[0], sizeof(ixDPM_TABLE_415)/sizeof(ixDPM_TABLE_415[0]), 0, 0 },
+	{ "ixDPM_TABLE_416", REG_SMC, 0x3f814, &ixDPM_TABLE_416[0], sizeof(ixDPM_TABLE_416)/sizeof(ixDPM_TABLE_416[0]), 0, 0 },
+	{ "ixDPM_TABLE_417", REG_SMC, 0x3f818, &ixDPM_TABLE_417[0], sizeof(ixDPM_TABLE_417)/sizeof(ixDPM_TABLE_417[0]), 0, 0 },
+	{ "ixDPM_TABLE_418", REG_SMC, 0x3f81c, &ixDPM_TABLE_418[0], sizeof(ixDPM_TABLE_418)/sizeof(ixDPM_TABLE_418[0]), 0, 0 },
+	{ "ixDPM_TABLE_419", REG_SMC, 0x3f820, &ixDPM_TABLE_419[0], sizeof(ixDPM_TABLE_419)/sizeof(ixDPM_TABLE_419[0]), 0, 0 },
+	{ "ixDPM_TABLE_420", REG_SMC, 0x3f824, &ixDPM_TABLE_420[0], sizeof(ixDPM_TABLE_420)/sizeof(ixDPM_TABLE_420[0]), 0, 0 },
+	{ "ixDPM_TABLE_421", REG_SMC, 0x3f828, &ixDPM_TABLE_421[0], sizeof(ixDPM_TABLE_421)/sizeof(ixDPM_TABLE_421[0]), 0, 0 },
+	{ "ixDPM_TABLE_422", REG_SMC, 0x3f82c, &ixDPM_TABLE_422[0], sizeof(ixDPM_TABLE_422)/sizeof(ixDPM_TABLE_422[0]), 0, 0 },
+	{ "ixDPM_TABLE_423", REG_SMC, 0x3f830, &ixDPM_TABLE_423[0], sizeof(ixDPM_TABLE_423)/sizeof(ixDPM_TABLE_423[0]), 0, 0 },
+	{ "ixDPM_TABLE_424", REG_SMC, 0x3f834, &ixDPM_TABLE_424[0], sizeof(ixDPM_TABLE_424)/sizeof(ixDPM_TABLE_424[0]), 0, 0 },
+	{ "ixDPM_TABLE_425", REG_SMC, 0x3f838, &ixDPM_TABLE_425[0], sizeof(ixDPM_TABLE_425)/sizeof(ixDPM_TABLE_425[0]), 0, 0 },
+	{ "ixDPM_TABLE_426", REG_SMC, 0x3f83c, &ixDPM_TABLE_426[0], sizeof(ixDPM_TABLE_426)/sizeof(ixDPM_TABLE_426[0]), 0, 0 },
+	{ "ixDPM_TABLE_427", REG_SMC, 0x3f840, &ixDPM_TABLE_427[0], sizeof(ixDPM_TABLE_427)/sizeof(ixDPM_TABLE_427[0]), 0, 0 },
+	{ "ixDPM_TABLE_428", REG_SMC, 0x3f844, &ixDPM_TABLE_428[0], sizeof(ixDPM_TABLE_428)/sizeof(ixDPM_TABLE_428[0]), 0, 0 },
+	{ "ixDPM_TABLE_429", REG_SMC, 0x3f848, &ixDPM_TABLE_429[0], sizeof(ixDPM_TABLE_429)/sizeof(ixDPM_TABLE_429[0]), 0, 0 },
+	{ "ixDPM_TABLE_430", REG_SMC, 0x3f84c, &ixDPM_TABLE_430[0], sizeof(ixDPM_TABLE_430)/sizeof(ixDPM_TABLE_430[0]), 0, 0 },
+	{ "ixDPM_TABLE_431", REG_SMC, 0x3f850, &ixDPM_TABLE_431[0], sizeof(ixDPM_TABLE_431)/sizeof(ixDPM_TABLE_431[0]), 0, 0 },
+	{ "ixDPM_TABLE_432", REG_SMC, 0x3f854, &ixDPM_TABLE_432[0], sizeof(ixDPM_TABLE_432)/sizeof(ixDPM_TABLE_432[0]), 0, 0 },
+	{ "ixDPM_TABLE_433", REG_SMC, 0x3f858, &ixDPM_TABLE_433[0], sizeof(ixDPM_TABLE_433)/sizeof(ixDPM_TABLE_433[0]), 0, 0 },
+	{ "ixDPM_TABLE_434", REG_SMC, 0x3f85c, &ixDPM_TABLE_434[0], sizeof(ixDPM_TABLE_434)/sizeof(ixDPM_TABLE_434[0]), 0, 0 },
+	{ "ixDPM_TABLE_435", REG_SMC, 0x3f860, &ixDPM_TABLE_435[0], sizeof(ixDPM_TABLE_435)/sizeof(ixDPM_TABLE_435[0]), 0, 0 },
+	{ "ixDPM_TABLE_436", REG_SMC, 0x3f864, &ixDPM_TABLE_436[0], sizeof(ixDPM_TABLE_436)/sizeof(ixDPM_TABLE_436[0]), 0, 0 },
+	{ "ixDPM_TABLE_437", REG_SMC, 0x3f868, &ixDPM_TABLE_437[0], sizeof(ixDPM_TABLE_437)/sizeof(ixDPM_TABLE_437[0]), 0, 0 },
+	{ "ixDPM_TABLE_438", REG_SMC, 0x3f86c, &ixDPM_TABLE_438[0], sizeof(ixDPM_TABLE_438)/sizeof(ixDPM_TABLE_438[0]), 0, 0 },
+	{ "ixDPM_TABLE_439", REG_SMC, 0x3f870, &ixDPM_TABLE_439[0], sizeof(ixDPM_TABLE_439)/sizeof(ixDPM_TABLE_439[0]), 0, 0 },
+	{ "ixDPM_TABLE_440", REG_SMC, 0x3f874, &ixDPM_TABLE_440[0], sizeof(ixDPM_TABLE_440)/sizeof(ixDPM_TABLE_440[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_28", REG_SMC, 0x3f888, &ixSOFT_REGISTERS_TABLE_28[0], sizeof(ixSOFT_REGISTERS_TABLE_28)/sizeof(ixSOFT_REGISTERS_TABLE_28[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_1", REG_SMC, 0x3f89c, &ixSOFT_REGISTERS_TABLE_1[0], sizeof(ixSOFT_REGISTERS_TABLE_1)/sizeof(ixSOFT_REGISTERS_TABLE_1[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_2", REG_SMC, 0x3f8a0, &ixSOFT_REGISTERS_TABLE_2[0], sizeof(ixSOFT_REGISTERS_TABLE_2)/sizeof(ixSOFT_REGISTERS_TABLE_2[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_3", REG_SMC, 0x3f8a4, &ixSOFT_REGISTERS_TABLE_3[0], sizeof(ixSOFT_REGISTERS_TABLE_3)/sizeof(ixSOFT_REGISTERS_TABLE_3[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_4", REG_SMC, 0x3f8a8, &ixSOFT_REGISTERS_TABLE_4[0], sizeof(ixSOFT_REGISTERS_TABLE_4)/sizeof(ixSOFT_REGISTERS_TABLE_4[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_5", REG_SMC, 0x3f8ac, &ixSOFT_REGISTERS_TABLE_5[0], sizeof(ixSOFT_REGISTERS_TABLE_5)/sizeof(ixSOFT_REGISTERS_TABLE_5[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_6", REG_SMC, 0x3f8b0, &ixSOFT_REGISTERS_TABLE_6[0], sizeof(ixSOFT_REGISTERS_TABLE_6)/sizeof(ixSOFT_REGISTERS_TABLE_6[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_7", REG_SMC, 0x3f8b4, &ixSOFT_REGISTERS_TABLE_7[0], sizeof(ixSOFT_REGISTERS_TABLE_7)/sizeof(ixSOFT_REGISTERS_TABLE_7[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_8", REG_SMC, 0x3f8b8, &ixSOFT_REGISTERS_TABLE_8[0], sizeof(ixSOFT_REGISTERS_TABLE_8)/sizeof(ixSOFT_REGISTERS_TABLE_8[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_9", REG_SMC, 0x3f8bc, &ixSOFT_REGISTERS_TABLE_9[0], sizeof(ixSOFT_REGISTERS_TABLE_9)/sizeof(ixSOFT_REGISTERS_TABLE_9[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_10", REG_SMC, 0x3f8c0, &ixSOFT_REGISTERS_TABLE_10[0], sizeof(ixSOFT_REGISTERS_TABLE_10)/sizeof(ixSOFT_REGISTERS_TABLE_10[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_11", REG_SMC, 0x3f8c4, &ixSOFT_REGISTERS_TABLE_11[0], sizeof(ixSOFT_REGISTERS_TABLE_11)/sizeof(ixSOFT_REGISTERS_TABLE_11[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_12", REG_SMC, 0x3f8c8, &ixSOFT_REGISTERS_TABLE_12[0], sizeof(ixSOFT_REGISTERS_TABLE_12)/sizeof(ixSOFT_REGISTERS_TABLE_12[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_13", REG_SMC, 0x3f8cc, &ixSOFT_REGISTERS_TABLE_13[0], sizeof(ixSOFT_REGISTERS_TABLE_13)/sizeof(ixSOFT_REGISTERS_TABLE_13[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_14", REG_SMC, 0x3f8d0, &ixSOFT_REGISTERS_TABLE_14[0], sizeof(ixSOFT_REGISTERS_TABLE_14)/sizeof(ixSOFT_REGISTERS_TABLE_14[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_15", REG_SMC, 0x3f8d4, &ixSOFT_REGISTERS_TABLE_15[0], sizeof(ixSOFT_REGISTERS_TABLE_15)/sizeof(ixSOFT_REGISTERS_TABLE_15[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_16", REG_SMC, 0x3f8d8, &ixSOFT_REGISTERS_TABLE_16[0], sizeof(ixSOFT_REGISTERS_TABLE_16)/sizeof(ixSOFT_REGISTERS_TABLE_16[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_17", REG_SMC, 0x3f8dc, &ixSOFT_REGISTERS_TABLE_17[0], sizeof(ixSOFT_REGISTERS_TABLE_17)/sizeof(ixSOFT_REGISTERS_TABLE_17[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_18", REG_SMC, 0x3f8e0, &ixSOFT_REGISTERS_TABLE_18[0], sizeof(ixSOFT_REGISTERS_TABLE_18)/sizeof(ixSOFT_REGISTERS_TABLE_18[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_19", REG_SMC, 0x3f8e4, &ixSOFT_REGISTERS_TABLE_19[0], sizeof(ixSOFT_REGISTERS_TABLE_19)/sizeof(ixSOFT_REGISTERS_TABLE_19[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_20", REG_SMC, 0x3f8e8, &ixSOFT_REGISTERS_TABLE_20[0], sizeof(ixSOFT_REGISTERS_TABLE_20)/sizeof(ixSOFT_REGISTERS_TABLE_20[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_21", REG_SMC, 0x3f8ec, &ixSOFT_REGISTERS_TABLE_21[0], sizeof(ixSOFT_REGISTERS_TABLE_21)/sizeof(ixSOFT_REGISTERS_TABLE_21[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_22", REG_SMC, 0x3f8f0, &ixSOFT_REGISTERS_TABLE_22[0], sizeof(ixSOFT_REGISTERS_TABLE_22)/sizeof(ixSOFT_REGISTERS_TABLE_22[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_23", REG_SMC, 0x3f8f4, &ixSOFT_REGISTERS_TABLE_23[0], sizeof(ixSOFT_REGISTERS_TABLE_23)/sizeof(ixSOFT_REGISTERS_TABLE_23[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_24", REG_SMC, 0x3f8f8, &ixSOFT_REGISTERS_TABLE_24[0], sizeof(ixSOFT_REGISTERS_TABLE_24)/sizeof(ixSOFT_REGISTERS_TABLE_24[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_25", REG_SMC, 0x3f8fc, &ixSOFT_REGISTERS_TABLE_25[0], sizeof(ixSOFT_REGISTERS_TABLE_25)/sizeof(ixSOFT_REGISTERS_TABLE_25[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_26", REG_SMC, 0x3f900, &ixSOFT_REGISTERS_TABLE_26[0], sizeof(ixSOFT_REGISTERS_TABLE_26)/sizeof(ixSOFT_REGISTERS_TABLE_26[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_27", REG_SMC, 0x3f904, &ixSOFT_REGISTERS_TABLE_27[0], sizeof(ixSOFT_REGISTERS_TABLE_27)/sizeof(ixSOFT_REGISTERS_TABLE_27[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_29", REG_SMC, 0x3f90c, &ixSOFT_REGISTERS_TABLE_29[0], sizeof(ixSOFT_REGISTERS_TABLE_29)/sizeof(ixSOFT_REGISTERS_TABLE_29[0]), 0, 0 },
+	{ "ixSOFT_REGISTERS_TABLE_30", REG_SMC, 0x3f910, &ixSOFT_REGISTERS_TABLE_30[0], sizeof(ixSOFT_REGISTERS_TABLE_30)/sizeof(ixSOFT_REGISTERS_TABLE_30[0]), 0, 0 },
+	{ "ixPM_FUSES_1", REG_SMC, 0x3f914, &ixPM_FUSES_1[0], sizeof(ixPM_FUSES_1)/sizeof(ixPM_FUSES_1[0]), 0, 0 },
+	{ "ixPM_FUSES_2", REG_SMC, 0x3f918, &ixPM_FUSES_2[0], sizeof(ixPM_FUSES_2)/sizeof(ixPM_FUSES_2[0]), 0, 0 },
+	{ "ixPM_FUSES_3", REG_SMC, 0x3f91c, &ixPM_FUSES_3[0], sizeof(ixPM_FUSES_3)/sizeof(ixPM_FUSES_3[0]), 0, 0 },
+	{ "ixPM_FUSES_4", REG_SMC, 0x3f920, &ixPM_FUSES_4[0], sizeof(ixPM_FUSES_4)/sizeof(ixPM_FUSES_4[0]), 0, 0 },
+	{ "ixPM_FUSES_5", REG_SMC, 0x3f924, &ixPM_FUSES_5[0], sizeof(ixPM_FUSES_5)/sizeof(ixPM_FUSES_5[0]), 0, 0 },
+	{ "ixPM_FUSES_6", REG_SMC, 0x3f928, &ixPM_FUSES_6[0], sizeof(ixPM_FUSES_6)/sizeof(ixPM_FUSES_6[0]), 0, 0 },
+	{ "ixPM_FUSES_7", REG_SMC, 0x3f92c, &ixPM_FUSES_7[0], sizeof(ixPM_FUSES_7)/sizeof(ixPM_FUSES_7[0]), 0, 0 },
+	{ "ixPM_FUSES_8", REG_SMC, 0x3f930, &ixPM_FUSES_8[0], sizeof(ixPM_FUSES_8)/sizeof(ixPM_FUSES_8[0]), 0, 0 },
+	{ "ixPM_FUSES_9", REG_SMC, 0x3f934, &ixPM_FUSES_9[0], sizeof(ixPM_FUSES_9)/sizeof(ixPM_FUSES_9[0]), 0, 0 },
+	{ "ixPM_FUSES_10", REG_SMC, 0x3f938, &ixPM_FUSES_10[0], sizeof(ixPM_FUSES_10)/sizeof(ixPM_FUSES_10[0]), 0, 0 },
+	{ "ixPM_FUSES_11", REG_SMC, 0x3f93c, &ixPM_FUSES_11[0], sizeof(ixPM_FUSES_11)/sizeof(ixPM_FUSES_11[0]), 0, 0 },
+	{ "ixPM_FUSES_12", REG_SMC, 0x3f940, &ixPM_FUSES_12[0], sizeof(ixPM_FUSES_12)/sizeof(ixPM_FUSES_12[0]), 0, 0 },
+	{ "ixPM_FUSES_13", REG_SMC, 0x3f944, &ixPM_FUSES_13[0], sizeof(ixPM_FUSES_13)/sizeof(ixPM_FUSES_13[0]), 0, 0 },
+	{ "ixPM_FUSES_14", REG_SMC, 0x3f948, &ixPM_FUSES_14[0], sizeof(ixPM_FUSES_14)/sizeof(ixPM_FUSES_14[0]), 0, 0 },
+	{ "ixPM_FUSES_15", REG_SMC, 0x3f94c, &ixPM_FUSES_15[0], sizeof(ixPM_FUSES_15)/sizeof(ixPM_FUSES_15[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_0", REG_SMC, 0x3fe00, &ixSMU_PM_STATUS_0[0], sizeof(ixSMU_PM_STATUS_0)/sizeof(ixSMU_PM_STATUS_0[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_1", REG_SMC, 0x3fe04, &ixSMU_PM_STATUS_1[0], sizeof(ixSMU_PM_STATUS_1)/sizeof(ixSMU_PM_STATUS_1[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_2", REG_SMC, 0x3fe08, &ixSMU_PM_STATUS_2[0], sizeof(ixSMU_PM_STATUS_2)/sizeof(ixSMU_PM_STATUS_2[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_3", REG_SMC, 0x3fe0c, &ixSMU_PM_STATUS_3[0], sizeof(ixSMU_PM_STATUS_3)/sizeof(ixSMU_PM_STATUS_3[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_4", REG_SMC, 0x3fe10, &ixSMU_PM_STATUS_4[0], sizeof(ixSMU_PM_STATUS_4)/sizeof(ixSMU_PM_STATUS_4[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_5", REG_SMC, 0x3fe14, &ixSMU_PM_STATUS_5[0], sizeof(ixSMU_PM_STATUS_5)/sizeof(ixSMU_PM_STATUS_5[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_6", REG_SMC, 0x3fe18, &ixSMU_PM_STATUS_6[0], sizeof(ixSMU_PM_STATUS_6)/sizeof(ixSMU_PM_STATUS_6[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_7", REG_SMC, 0x3fe1c, &ixSMU_PM_STATUS_7[0], sizeof(ixSMU_PM_STATUS_7)/sizeof(ixSMU_PM_STATUS_7[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_8", REG_SMC, 0x3fe20, &ixSMU_PM_STATUS_8[0], sizeof(ixSMU_PM_STATUS_8)/sizeof(ixSMU_PM_STATUS_8[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_9", REG_SMC, 0x3fe24, &ixSMU_PM_STATUS_9[0], sizeof(ixSMU_PM_STATUS_9)/sizeof(ixSMU_PM_STATUS_9[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_10", REG_SMC, 0x3fe28, &ixSMU_PM_STATUS_10[0], sizeof(ixSMU_PM_STATUS_10)/sizeof(ixSMU_PM_STATUS_10[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_11", REG_SMC, 0x3fe2c, &ixSMU_PM_STATUS_11[0], sizeof(ixSMU_PM_STATUS_11)/sizeof(ixSMU_PM_STATUS_11[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_12", REG_SMC, 0x3fe30, &ixSMU_PM_STATUS_12[0], sizeof(ixSMU_PM_STATUS_12)/sizeof(ixSMU_PM_STATUS_12[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_13", REG_SMC, 0x3fe34, &ixSMU_PM_STATUS_13[0], sizeof(ixSMU_PM_STATUS_13)/sizeof(ixSMU_PM_STATUS_13[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_14", REG_SMC, 0x3fe38, &ixSMU_PM_STATUS_14[0], sizeof(ixSMU_PM_STATUS_14)/sizeof(ixSMU_PM_STATUS_14[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_15", REG_SMC, 0x3fe3c, &ixSMU_PM_STATUS_15[0], sizeof(ixSMU_PM_STATUS_15)/sizeof(ixSMU_PM_STATUS_15[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_16", REG_SMC, 0x3fe40, &ixSMU_PM_STATUS_16[0], sizeof(ixSMU_PM_STATUS_16)/sizeof(ixSMU_PM_STATUS_16[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_17", REG_SMC, 0x3fe44, &ixSMU_PM_STATUS_17[0], sizeof(ixSMU_PM_STATUS_17)/sizeof(ixSMU_PM_STATUS_17[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_18", REG_SMC, 0x3fe48, &ixSMU_PM_STATUS_18[0], sizeof(ixSMU_PM_STATUS_18)/sizeof(ixSMU_PM_STATUS_18[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_19", REG_SMC, 0x3fe4c, &ixSMU_PM_STATUS_19[0], sizeof(ixSMU_PM_STATUS_19)/sizeof(ixSMU_PM_STATUS_19[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_20", REG_SMC, 0x3fe50, &ixSMU_PM_STATUS_20[0], sizeof(ixSMU_PM_STATUS_20)/sizeof(ixSMU_PM_STATUS_20[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_21", REG_SMC, 0x3fe54, &ixSMU_PM_STATUS_21[0], sizeof(ixSMU_PM_STATUS_21)/sizeof(ixSMU_PM_STATUS_21[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_22", REG_SMC, 0x3fe58, &ixSMU_PM_STATUS_22[0], sizeof(ixSMU_PM_STATUS_22)/sizeof(ixSMU_PM_STATUS_22[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_23", REG_SMC, 0x3fe5c, &ixSMU_PM_STATUS_23[0], sizeof(ixSMU_PM_STATUS_23)/sizeof(ixSMU_PM_STATUS_23[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_24", REG_SMC, 0x3fe60, &ixSMU_PM_STATUS_24[0], sizeof(ixSMU_PM_STATUS_24)/sizeof(ixSMU_PM_STATUS_24[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_25", REG_SMC, 0x3fe64, &ixSMU_PM_STATUS_25[0], sizeof(ixSMU_PM_STATUS_25)/sizeof(ixSMU_PM_STATUS_25[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_26", REG_SMC, 0x3fe68, &ixSMU_PM_STATUS_26[0], sizeof(ixSMU_PM_STATUS_26)/sizeof(ixSMU_PM_STATUS_26[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_27", REG_SMC, 0x3fe6c, &ixSMU_PM_STATUS_27[0], sizeof(ixSMU_PM_STATUS_27)/sizeof(ixSMU_PM_STATUS_27[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_28", REG_SMC, 0x3fe70, &ixSMU_PM_STATUS_28[0], sizeof(ixSMU_PM_STATUS_28)/sizeof(ixSMU_PM_STATUS_28[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_29", REG_SMC, 0x3fe74, &ixSMU_PM_STATUS_29[0], sizeof(ixSMU_PM_STATUS_29)/sizeof(ixSMU_PM_STATUS_29[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_30", REG_SMC, 0x3fe78, &ixSMU_PM_STATUS_30[0], sizeof(ixSMU_PM_STATUS_30)/sizeof(ixSMU_PM_STATUS_30[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_31", REG_SMC, 0x3fe7c, &ixSMU_PM_STATUS_31[0], sizeof(ixSMU_PM_STATUS_31)/sizeof(ixSMU_PM_STATUS_31[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_32", REG_SMC, 0x3fe80, &ixSMU_PM_STATUS_32[0], sizeof(ixSMU_PM_STATUS_32)/sizeof(ixSMU_PM_STATUS_32[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_33", REG_SMC, 0x3fe84, &ixSMU_PM_STATUS_33[0], sizeof(ixSMU_PM_STATUS_33)/sizeof(ixSMU_PM_STATUS_33[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_34", REG_SMC, 0x3fe88, &ixSMU_PM_STATUS_34[0], sizeof(ixSMU_PM_STATUS_34)/sizeof(ixSMU_PM_STATUS_34[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_35", REG_SMC, 0x3fe8c, &ixSMU_PM_STATUS_35[0], sizeof(ixSMU_PM_STATUS_35)/sizeof(ixSMU_PM_STATUS_35[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_36", REG_SMC, 0x3fe90, &ixSMU_PM_STATUS_36[0], sizeof(ixSMU_PM_STATUS_36)/sizeof(ixSMU_PM_STATUS_36[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_37", REG_SMC, 0x3fe94, &ixSMU_PM_STATUS_37[0], sizeof(ixSMU_PM_STATUS_37)/sizeof(ixSMU_PM_STATUS_37[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_38", REG_SMC, 0x3fe98, &ixSMU_PM_STATUS_38[0], sizeof(ixSMU_PM_STATUS_38)/sizeof(ixSMU_PM_STATUS_38[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_39", REG_SMC, 0x3fe9c, &ixSMU_PM_STATUS_39[0], sizeof(ixSMU_PM_STATUS_39)/sizeof(ixSMU_PM_STATUS_39[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_40", REG_SMC, 0x3fea0, &ixSMU_PM_STATUS_40[0], sizeof(ixSMU_PM_STATUS_40)/sizeof(ixSMU_PM_STATUS_40[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_41", REG_SMC, 0x3fea4, &ixSMU_PM_STATUS_41[0], sizeof(ixSMU_PM_STATUS_41)/sizeof(ixSMU_PM_STATUS_41[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_42", REG_SMC, 0x3fea8, &ixSMU_PM_STATUS_42[0], sizeof(ixSMU_PM_STATUS_42)/sizeof(ixSMU_PM_STATUS_42[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_43", REG_SMC, 0x3feac, &ixSMU_PM_STATUS_43[0], sizeof(ixSMU_PM_STATUS_43)/sizeof(ixSMU_PM_STATUS_43[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_44", REG_SMC, 0x3feb0, &ixSMU_PM_STATUS_44[0], sizeof(ixSMU_PM_STATUS_44)/sizeof(ixSMU_PM_STATUS_44[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_45", REG_SMC, 0x3feb4, &ixSMU_PM_STATUS_45[0], sizeof(ixSMU_PM_STATUS_45)/sizeof(ixSMU_PM_STATUS_45[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_46", REG_SMC, 0x3feb8, &ixSMU_PM_STATUS_46[0], sizeof(ixSMU_PM_STATUS_46)/sizeof(ixSMU_PM_STATUS_46[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_47", REG_SMC, 0x3febc, &ixSMU_PM_STATUS_47[0], sizeof(ixSMU_PM_STATUS_47)/sizeof(ixSMU_PM_STATUS_47[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_48", REG_SMC, 0x3fec0, &ixSMU_PM_STATUS_48[0], sizeof(ixSMU_PM_STATUS_48)/sizeof(ixSMU_PM_STATUS_48[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_49", REG_SMC, 0x3fec4, &ixSMU_PM_STATUS_49[0], sizeof(ixSMU_PM_STATUS_49)/sizeof(ixSMU_PM_STATUS_49[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_50", REG_SMC, 0x3fec8, &ixSMU_PM_STATUS_50[0], sizeof(ixSMU_PM_STATUS_50)/sizeof(ixSMU_PM_STATUS_50[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_51", REG_SMC, 0x3fecc, &ixSMU_PM_STATUS_51[0], sizeof(ixSMU_PM_STATUS_51)/sizeof(ixSMU_PM_STATUS_51[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_52", REG_SMC, 0x3fed0, &ixSMU_PM_STATUS_52[0], sizeof(ixSMU_PM_STATUS_52)/sizeof(ixSMU_PM_STATUS_52[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_53", REG_SMC, 0x3fed4, &ixSMU_PM_STATUS_53[0], sizeof(ixSMU_PM_STATUS_53)/sizeof(ixSMU_PM_STATUS_53[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_54", REG_SMC, 0x3fed8, &ixSMU_PM_STATUS_54[0], sizeof(ixSMU_PM_STATUS_54)/sizeof(ixSMU_PM_STATUS_54[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_55", REG_SMC, 0x3fedc, &ixSMU_PM_STATUS_55[0], sizeof(ixSMU_PM_STATUS_55)/sizeof(ixSMU_PM_STATUS_55[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_56", REG_SMC, 0x3fee0, &ixSMU_PM_STATUS_56[0], sizeof(ixSMU_PM_STATUS_56)/sizeof(ixSMU_PM_STATUS_56[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_57", REG_SMC, 0x3fee4, &ixSMU_PM_STATUS_57[0], sizeof(ixSMU_PM_STATUS_57)/sizeof(ixSMU_PM_STATUS_57[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_58", REG_SMC, 0x3fee8, &ixSMU_PM_STATUS_58[0], sizeof(ixSMU_PM_STATUS_58)/sizeof(ixSMU_PM_STATUS_58[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_59", REG_SMC, 0x3feec, &ixSMU_PM_STATUS_59[0], sizeof(ixSMU_PM_STATUS_59)/sizeof(ixSMU_PM_STATUS_59[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_60", REG_SMC, 0x3fef0, &ixSMU_PM_STATUS_60[0], sizeof(ixSMU_PM_STATUS_60)/sizeof(ixSMU_PM_STATUS_60[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_61", REG_SMC, 0x3fef4, &ixSMU_PM_STATUS_61[0], sizeof(ixSMU_PM_STATUS_61)/sizeof(ixSMU_PM_STATUS_61[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_62", REG_SMC, 0x3fef8, &ixSMU_PM_STATUS_62[0], sizeof(ixSMU_PM_STATUS_62)/sizeof(ixSMU_PM_STATUS_62[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_63", REG_SMC, 0x3fefc, &ixSMU_PM_STATUS_63[0], sizeof(ixSMU_PM_STATUS_63)/sizeof(ixSMU_PM_STATUS_63[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_64", REG_SMC, 0x3ff00, &ixSMU_PM_STATUS_64[0], sizeof(ixSMU_PM_STATUS_64)/sizeof(ixSMU_PM_STATUS_64[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_65", REG_SMC, 0x3ff04, &ixSMU_PM_STATUS_65[0], sizeof(ixSMU_PM_STATUS_65)/sizeof(ixSMU_PM_STATUS_65[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_66", REG_SMC, 0x3ff08, &ixSMU_PM_STATUS_66[0], sizeof(ixSMU_PM_STATUS_66)/sizeof(ixSMU_PM_STATUS_66[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_67", REG_SMC, 0x3ff0c, &ixSMU_PM_STATUS_67[0], sizeof(ixSMU_PM_STATUS_67)/sizeof(ixSMU_PM_STATUS_67[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_68", REG_SMC, 0x3ff10, &ixSMU_PM_STATUS_68[0], sizeof(ixSMU_PM_STATUS_68)/sizeof(ixSMU_PM_STATUS_68[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_69", REG_SMC, 0x3ff14, &ixSMU_PM_STATUS_69[0], sizeof(ixSMU_PM_STATUS_69)/sizeof(ixSMU_PM_STATUS_69[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_70", REG_SMC, 0x3ff18, &ixSMU_PM_STATUS_70[0], sizeof(ixSMU_PM_STATUS_70)/sizeof(ixSMU_PM_STATUS_70[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_71", REG_SMC, 0x3ff1c, &ixSMU_PM_STATUS_71[0], sizeof(ixSMU_PM_STATUS_71)/sizeof(ixSMU_PM_STATUS_71[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_72", REG_SMC, 0x3ff20, &ixSMU_PM_STATUS_72[0], sizeof(ixSMU_PM_STATUS_72)/sizeof(ixSMU_PM_STATUS_72[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_73", REG_SMC, 0x3ff24, &ixSMU_PM_STATUS_73[0], sizeof(ixSMU_PM_STATUS_73)/sizeof(ixSMU_PM_STATUS_73[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_74", REG_SMC, 0x3ff28, &ixSMU_PM_STATUS_74[0], sizeof(ixSMU_PM_STATUS_74)/sizeof(ixSMU_PM_STATUS_74[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_75", REG_SMC, 0x3ff2c, &ixSMU_PM_STATUS_75[0], sizeof(ixSMU_PM_STATUS_75)/sizeof(ixSMU_PM_STATUS_75[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_76", REG_SMC, 0x3ff30, &ixSMU_PM_STATUS_76[0], sizeof(ixSMU_PM_STATUS_76)/sizeof(ixSMU_PM_STATUS_76[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_77", REG_SMC, 0x3ff34, &ixSMU_PM_STATUS_77[0], sizeof(ixSMU_PM_STATUS_77)/sizeof(ixSMU_PM_STATUS_77[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_78", REG_SMC, 0x3ff38, &ixSMU_PM_STATUS_78[0], sizeof(ixSMU_PM_STATUS_78)/sizeof(ixSMU_PM_STATUS_78[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_79", REG_SMC, 0x3ff3c, &ixSMU_PM_STATUS_79[0], sizeof(ixSMU_PM_STATUS_79)/sizeof(ixSMU_PM_STATUS_79[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_80", REG_SMC, 0x3ff40, &ixSMU_PM_STATUS_80[0], sizeof(ixSMU_PM_STATUS_80)/sizeof(ixSMU_PM_STATUS_80[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_81", REG_SMC, 0x3ff44, &ixSMU_PM_STATUS_81[0], sizeof(ixSMU_PM_STATUS_81)/sizeof(ixSMU_PM_STATUS_81[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_82", REG_SMC, 0x3ff48, &ixSMU_PM_STATUS_82[0], sizeof(ixSMU_PM_STATUS_82)/sizeof(ixSMU_PM_STATUS_82[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_83", REG_SMC, 0x3ff4c, &ixSMU_PM_STATUS_83[0], sizeof(ixSMU_PM_STATUS_83)/sizeof(ixSMU_PM_STATUS_83[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_84", REG_SMC, 0x3ff50, &ixSMU_PM_STATUS_84[0], sizeof(ixSMU_PM_STATUS_84)/sizeof(ixSMU_PM_STATUS_84[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_85", REG_SMC, 0x3ff54, &ixSMU_PM_STATUS_85[0], sizeof(ixSMU_PM_STATUS_85)/sizeof(ixSMU_PM_STATUS_85[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_86", REG_SMC, 0x3ff58, &ixSMU_PM_STATUS_86[0], sizeof(ixSMU_PM_STATUS_86)/sizeof(ixSMU_PM_STATUS_86[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_87", REG_SMC, 0x3ff5c, &ixSMU_PM_STATUS_87[0], sizeof(ixSMU_PM_STATUS_87)/sizeof(ixSMU_PM_STATUS_87[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_88", REG_SMC, 0x3ff60, &ixSMU_PM_STATUS_88[0], sizeof(ixSMU_PM_STATUS_88)/sizeof(ixSMU_PM_STATUS_88[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_89", REG_SMC, 0x3ff64, &ixSMU_PM_STATUS_89[0], sizeof(ixSMU_PM_STATUS_89)/sizeof(ixSMU_PM_STATUS_89[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_90", REG_SMC, 0x3ff68, &ixSMU_PM_STATUS_90[0], sizeof(ixSMU_PM_STATUS_90)/sizeof(ixSMU_PM_STATUS_90[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_91", REG_SMC, 0x3ff6c, &ixSMU_PM_STATUS_91[0], sizeof(ixSMU_PM_STATUS_91)/sizeof(ixSMU_PM_STATUS_91[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_92", REG_SMC, 0x3ff70, &ixSMU_PM_STATUS_92[0], sizeof(ixSMU_PM_STATUS_92)/sizeof(ixSMU_PM_STATUS_92[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_93", REG_SMC, 0x3ff74, &ixSMU_PM_STATUS_93[0], sizeof(ixSMU_PM_STATUS_93)/sizeof(ixSMU_PM_STATUS_93[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_94", REG_SMC, 0x3ff78, &ixSMU_PM_STATUS_94[0], sizeof(ixSMU_PM_STATUS_94)/sizeof(ixSMU_PM_STATUS_94[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_95", REG_SMC, 0x3ff7c, &ixSMU_PM_STATUS_95[0], sizeof(ixSMU_PM_STATUS_95)/sizeof(ixSMU_PM_STATUS_95[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_96", REG_SMC, 0x3ff80, &ixSMU_PM_STATUS_96[0], sizeof(ixSMU_PM_STATUS_96)/sizeof(ixSMU_PM_STATUS_96[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_97", REG_SMC, 0x3ff84, &ixSMU_PM_STATUS_97[0], sizeof(ixSMU_PM_STATUS_97)/sizeof(ixSMU_PM_STATUS_97[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_98", REG_SMC, 0x3ff88, &ixSMU_PM_STATUS_98[0], sizeof(ixSMU_PM_STATUS_98)/sizeof(ixSMU_PM_STATUS_98[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_99", REG_SMC, 0x3ff8c, &ixSMU_PM_STATUS_99[0], sizeof(ixSMU_PM_STATUS_99)/sizeof(ixSMU_PM_STATUS_99[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_100", REG_SMC, 0x3ff90, &ixSMU_PM_STATUS_100[0], sizeof(ixSMU_PM_STATUS_100)/sizeof(ixSMU_PM_STATUS_100[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_101", REG_SMC, 0x3ff94, &ixSMU_PM_STATUS_101[0], sizeof(ixSMU_PM_STATUS_101)/sizeof(ixSMU_PM_STATUS_101[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_102", REG_SMC, 0x3ff98, &ixSMU_PM_STATUS_102[0], sizeof(ixSMU_PM_STATUS_102)/sizeof(ixSMU_PM_STATUS_102[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_103", REG_SMC, 0x3ff9c, &ixSMU_PM_STATUS_103[0], sizeof(ixSMU_PM_STATUS_103)/sizeof(ixSMU_PM_STATUS_103[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_104", REG_SMC, 0x3ffa0, &ixSMU_PM_STATUS_104[0], sizeof(ixSMU_PM_STATUS_104)/sizeof(ixSMU_PM_STATUS_104[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_105", REG_SMC, 0x3ffa4, &ixSMU_PM_STATUS_105[0], sizeof(ixSMU_PM_STATUS_105)/sizeof(ixSMU_PM_STATUS_105[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_106", REG_SMC, 0x3ffa8, &ixSMU_PM_STATUS_106[0], sizeof(ixSMU_PM_STATUS_106)/sizeof(ixSMU_PM_STATUS_106[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_107", REG_SMC, 0x3ffac, &ixSMU_PM_STATUS_107[0], sizeof(ixSMU_PM_STATUS_107)/sizeof(ixSMU_PM_STATUS_107[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_108", REG_SMC, 0x3ffb0, &ixSMU_PM_STATUS_108[0], sizeof(ixSMU_PM_STATUS_108)/sizeof(ixSMU_PM_STATUS_108[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_109", REG_SMC, 0x3ffb4, &ixSMU_PM_STATUS_109[0], sizeof(ixSMU_PM_STATUS_109)/sizeof(ixSMU_PM_STATUS_109[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_110", REG_SMC, 0x3ffb8, &ixSMU_PM_STATUS_110[0], sizeof(ixSMU_PM_STATUS_110)/sizeof(ixSMU_PM_STATUS_110[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_111", REG_SMC, 0x3ffbc, &ixSMU_PM_STATUS_111[0], sizeof(ixSMU_PM_STATUS_111)/sizeof(ixSMU_PM_STATUS_111[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_112", REG_SMC, 0x3ffc0, &ixSMU_PM_STATUS_112[0], sizeof(ixSMU_PM_STATUS_112)/sizeof(ixSMU_PM_STATUS_112[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_113", REG_SMC, 0x3ffc4, &ixSMU_PM_STATUS_113[0], sizeof(ixSMU_PM_STATUS_113)/sizeof(ixSMU_PM_STATUS_113[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_114", REG_SMC, 0x3ffc8, &ixSMU_PM_STATUS_114[0], sizeof(ixSMU_PM_STATUS_114)/sizeof(ixSMU_PM_STATUS_114[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_115", REG_SMC, 0x3ffcc, &ixSMU_PM_STATUS_115[0], sizeof(ixSMU_PM_STATUS_115)/sizeof(ixSMU_PM_STATUS_115[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_116", REG_SMC, 0x3ffd0, &ixSMU_PM_STATUS_116[0], sizeof(ixSMU_PM_STATUS_116)/sizeof(ixSMU_PM_STATUS_116[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_117", REG_SMC, 0x3ffd4, &ixSMU_PM_STATUS_117[0], sizeof(ixSMU_PM_STATUS_117)/sizeof(ixSMU_PM_STATUS_117[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_118", REG_SMC, 0x3ffd8, &ixSMU_PM_STATUS_118[0], sizeof(ixSMU_PM_STATUS_118)/sizeof(ixSMU_PM_STATUS_118[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_119", REG_SMC, 0x3ffdc, &ixSMU_PM_STATUS_119[0], sizeof(ixSMU_PM_STATUS_119)/sizeof(ixSMU_PM_STATUS_119[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_120", REG_SMC, 0x3ffe0, &ixSMU_PM_STATUS_120[0], sizeof(ixSMU_PM_STATUS_120)/sizeof(ixSMU_PM_STATUS_120[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_121", REG_SMC, 0x3ffe4, &ixSMU_PM_STATUS_121[0], sizeof(ixSMU_PM_STATUS_121)/sizeof(ixSMU_PM_STATUS_121[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_122", REG_SMC, 0x3ffe8, &ixSMU_PM_STATUS_122[0], sizeof(ixSMU_PM_STATUS_122)/sizeof(ixSMU_PM_STATUS_122[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_123", REG_SMC, 0x3ffec, &ixSMU_PM_STATUS_123[0], sizeof(ixSMU_PM_STATUS_123)/sizeof(ixSMU_PM_STATUS_123[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_124", REG_SMC, 0x3fff0, &ixSMU_PM_STATUS_124[0], sizeof(ixSMU_PM_STATUS_124)/sizeof(ixSMU_PM_STATUS_124[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_125", REG_SMC, 0x3fff4, &ixSMU_PM_STATUS_125[0], sizeof(ixSMU_PM_STATUS_125)/sizeof(ixSMU_PM_STATUS_125[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_126", REG_SMC, 0x3fff8, &ixSMU_PM_STATUS_126[0], sizeof(ixSMU_PM_STATUS_126)/sizeof(ixSMU_PM_STATUS_126[0]), 0, 0 },
+	{ "ixSMU_PM_STATUS_127", REG_SMC, 0x3fffc, &ixSMU_PM_STATUS_127[0], sizeof(ixSMU_PM_STATUS_127)/sizeof(ixSMU_PM_STATUS_127[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_INDEX", REG_MMIO, 0x80, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_INDEX", REG_MMIO, 0x80, &mmGCK_SMC_IND_INDEX[0], sizeof(mmGCK_SMC_IND_INDEX)/sizeof(mmGCK_SMC_IND_INDEX[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_0", REG_MMIO, 0x80, &mmSMC_IND_INDEX_0[0], sizeof(mmSMC_IND_INDEX_0)/sizeof(mmSMC_IND_INDEX_0[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX", REG_MMIO, 0x80, &mmSMC_IND_INDEX[0], sizeof(mmSMC_IND_INDEX)/sizeof(mmSMC_IND_INDEX[0]), 0, 0 },
+	{ "ixSMC_SYSCON_RESET_CNTL", REG_SMC, 0x80000000, &ixSMC_SYSCON_RESET_CNTL[0], sizeof(ixSMC_SYSCON_RESET_CNTL)/sizeof(ixSMC_SYSCON_RESET_CNTL[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_0", REG_SMC, 0x80000004, &ixSMC_SYSCON_CLOCK_CNTL_0[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_0)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_0[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_1", REG_SMC, 0x80000008, &ixSMC_SYSCON_CLOCK_CNTL_1[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_1)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_1[0]), 0, 0 },
+	{ "ixSMC_SYSCON_CLOCK_CNTL_2", REG_SMC, 0x8000000c, &ixSMC_SYSCON_CLOCK_CNTL_2[0], sizeof(ixSMC_SYSCON_CLOCK_CNTL_2)/sizeof(ixSMC_SYSCON_CLOCK_CNTL_2[0]), 0, 0 },
+	{ "ixSMC_SYSCON_MISC_CNTL", REG_SMC, 0x80000010, &ixSMC_SYSCON_MISC_CNTL[0], sizeof(ixSMC_SYSCON_MISC_CNTL)/sizeof(ixSMC_SYSCON_MISC_CNTL[0]), 0, 0 },
+	{ "ixSMC_SYSCON_MSG_ARG_0", REG_SMC, 0x80000068, &ixSMC_SYSCON_MSG_ARG_0[0], sizeof(ixSMC_SYSCON_MSG_ARG_0)/sizeof(ixSMC_SYSCON_MSG_ARG_0[0]), 0, 0 },
+	{ "ixSMC_PC_C", REG_SMC, 0x80000370, &ixSMC_PC_C[0], sizeof(ixSMC_PC_C)/sizeof(ixSMC_PC_C[0]), 0, 0 },
+	{ "ixSMC_SCRATCH9", REG_SMC, 0x80000424, &ixSMC_SCRATCH9[0], sizeof(ixSMC_SCRATCH9)/sizeof(ixSMC_SCRATCH9[0]), 0, 0 },
+	{ "mmGCK0_GCK_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmSMC0_SMC_IND_DATA", REG_MMIO, 0x81, NULL, 0, 0, 0 },
+	{ "mmGCK_SMC_IND_DATA", REG_MMIO, 0x81, &mmGCK_SMC_IND_DATA[0], sizeof(mmGCK_SMC_IND_DATA)/sizeof(mmGCK_SMC_IND_DATA[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_0", REG_MMIO, 0x81, &mmSMC_IND_DATA_0[0], sizeof(mmSMC_IND_DATA_0)/sizeof(mmSMC_IND_DATA_0[0]), 0, 0 },
+	{ "mmSMC_IND_DATA", REG_MMIO, 0x81, &mmSMC_IND_DATA[0], sizeof(mmSMC_IND_DATA)/sizeof(mmSMC_IND_DATA[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_INDEX", REG_MMIO, 0x82, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_1", REG_MMIO, 0x82, &mmSMC_IND_INDEX_1[0], sizeof(mmSMC_IND_INDEX_1)/sizeof(mmSMC_IND_INDEX_1[0]), 0, 0 },
+	{ "mmGCK1_GCK_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC1_SMC_IND_DATA", REG_MMIO, 0x83, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_1", REG_MMIO, 0x83, &mmSMC_IND_DATA_1[0], sizeof(mmSMC_IND_DATA_1)/sizeof(mmSMC_IND_DATA_1[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_INDEX", REG_MMIO, 0x84, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_2", REG_MMIO, 0x84, &mmSMC_IND_INDEX_2[0], sizeof(mmSMC_IND_INDEX_2)/sizeof(mmSMC_IND_INDEX_2[0]), 0, 0 },
+	{ "mmGCK2_GCK_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC2_SMC_IND_DATA", REG_MMIO, 0x85, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_2", REG_MMIO, 0x85, &mmSMC_IND_DATA_2[0], sizeof(mmSMC_IND_DATA_2)/sizeof(mmSMC_IND_DATA_2[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_INDEX", REG_MMIO, 0x86, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_INDEX_3", REG_MMIO, 0x86, &mmSMC_IND_INDEX_3[0], sizeof(mmSMC_IND_INDEX_3)/sizeof(mmSMC_IND_INDEX_3[0]), 0, 0 },
+	{ "mmGCK3_GCK_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC3_SMC_IND_DATA", REG_MMIO, 0x87, NULL, 0, 0, 0 },
+	{ "mmSMC_IND_DATA_3", REG_MMIO, 0x87, &mmSMC_IND_DATA_3[0], sizeof(mmSMC_IND_DATA_3)/sizeof(mmSMC_IND_DATA_3[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_4", REG_MMIO, 0x88, &mmSMC_IND_INDEX_4[0], sizeof(mmSMC_IND_INDEX_4)/sizeof(mmSMC_IND_INDEX_4[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_4", REG_MMIO, 0x89, &mmSMC_IND_DATA_4[0], sizeof(mmSMC_IND_DATA_4)/sizeof(mmSMC_IND_DATA_4[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_5", REG_MMIO, 0x8a, &mmSMC_IND_INDEX_5[0], sizeof(mmSMC_IND_INDEX_5)/sizeof(mmSMC_IND_INDEX_5[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_5", REG_MMIO, 0x8b, &mmSMC_IND_DATA_5[0], sizeof(mmSMC_IND_DATA_5)/sizeof(mmSMC_IND_DATA_5[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_6", REG_MMIO, 0x8c, &mmSMC_IND_INDEX_6[0], sizeof(mmSMC_IND_INDEX_6)/sizeof(mmSMC_IND_INDEX_6[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_6", REG_MMIO, 0x8d, &mmSMC_IND_DATA_6[0], sizeof(mmSMC_IND_DATA_6)/sizeof(mmSMC_IND_DATA_6[0]), 0, 0 },
+	{ "mmSMC_IND_INDEX_7", REG_MMIO, 0x8e, &mmSMC_IND_INDEX_7[0], sizeof(mmSMC_IND_INDEX_7)/sizeof(mmSMC_IND_INDEX_7[0]), 0, 0 },
+	{ "mmSMC_IND_DATA_7", REG_MMIO, 0x8f, &mmSMC_IND_DATA_7[0], sizeof(mmSMC_IND_DATA_7)/sizeof(mmSMC_IND_DATA_7[0]), 0, 0 },
+	{ "mmSMC_IND_ACCESS_CNTL", REG_MMIO, 0x92, &mmSMC_IND_ACCESS_CNTL[0], sizeof(mmSMC_IND_ACCESS_CNTL)/sizeof(mmSMC_IND_ACCESS_CNTL[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_11", REG_MMIO, 0x93, &mmSMC_MSG_ARG_11[0], sizeof(mmSMC_MSG_ARG_11)/sizeof(mmSMC_MSG_ARG_11[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_0", REG_MMIO, 0x94, &mmSMC_MESSAGE_0[0], sizeof(mmSMC_MESSAGE_0)/sizeof(mmSMC_MESSAGE_0[0]), 0, 0 },
+	{ "mmSMC_RESP_0", REG_MMIO, 0x95, &mmSMC_RESP_0[0], sizeof(mmSMC_RESP_0)/sizeof(mmSMC_RESP_0[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_1", REG_MMIO, 0x96, &mmSMC_MESSAGE_1[0], sizeof(mmSMC_MESSAGE_1)/sizeof(mmSMC_MESSAGE_1[0]), 0, 0 },
+	{ "mmSMC_RESP_1", REG_MMIO, 0x97, &mmSMC_RESP_1[0], sizeof(mmSMC_RESP_1)/sizeof(mmSMC_RESP_1[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_2", REG_MMIO, 0x98, &mmSMC_MESSAGE_2[0], sizeof(mmSMC_MESSAGE_2)/sizeof(mmSMC_MESSAGE_2[0]), 0, 0 },
+	{ "mmSMC_RESP_2", REG_MMIO, 0x99, &mmSMC_RESP_2[0], sizeof(mmSMC_RESP_2)/sizeof(mmSMC_RESP_2[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_3", REG_MMIO, 0x9a, &mmSMC_MESSAGE_3[0], sizeof(mmSMC_MESSAGE_3)/sizeof(mmSMC_MESSAGE_3[0]), 0, 0 },
+	{ "mmSMC_RESP_3", REG_MMIO, 0x9b, &mmSMC_RESP_3[0], sizeof(mmSMC_RESP_3)/sizeof(mmSMC_RESP_3[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_4", REG_MMIO, 0x9c, &mmSMC_MESSAGE_4[0], sizeof(mmSMC_MESSAGE_4)/sizeof(mmSMC_MESSAGE_4[0]), 0, 0 },
+	{ "mmSMC_RESP_4", REG_MMIO, 0x9d, &mmSMC_RESP_4[0], sizeof(mmSMC_RESP_4)/sizeof(mmSMC_RESP_4[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_5", REG_MMIO, 0x9e, &mmSMC_MESSAGE_5[0], sizeof(mmSMC_MESSAGE_5)/sizeof(mmSMC_MESSAGE_5[0]), 0, 0 },
+	{ "mmSMC_RESP_5", REG_MMIO, 0x9f, &mmSMC_RESP_5[0], sizeof(mmSMC_RESP_5)/sizeof(mmSMC_RESP_5[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_6", REG_MMIO, 0xa0, &mmSMC_MESSAGE_6[0], sizeof(mmSMC_MESSAGE_6)/sizeof(mmSMC_MESSAGE_6[0]), 0, 0 },
+	{ "mmSMC_RESP_6", REG_MMIO, 0xa1, &mmSMC_RESP_6[0], sizeof(mmSMC_RESP_6)/sizeof(mmSMC_RESP_6[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_7", REG_MMIO, 0xa2, &mmSMC_MESSAGE_7[0], sizeof(mmSMC_MESSAGE_7)/sizeof(mmSMC_MESSAGE_7[0]), 0, 0 },
+	{ "mmSMC_RESP_7", REG_MMIO, 0xa3, &mmSMC_RESP_7[0], sizeof(mmSMC_RESP_7)/sizeof(mmSMC_RESP_7[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_0", REG_MMIO, 0xa4, &mmSMC_MSG_ARG_0[0], sizeof(mmSMC_MSG_ARG_0)/sizeof(mmSMC_MSG_ARG_0[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_1", REG_MMIO, 0xa5, &mmSMC_MSG_ARG_1[0], sizeof(mmSMC_MSG_ARG_1)/sizeof(mmSMC_MSG_ARG_1[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_2", REG_MMIO, 0xa6, &mmSMC_MSG_ARG_2[0], sizeof(mmSMC_MSG_ARG_2)/sizeof(mmSMC_MSG_ARG_2[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_3", REG_MMIO, 0xa7, &mmSMC_MSG_ARG_3[0], sizeof(mmSMC_MSG_ARG_3)/sizeof(mmSMC_MSG_ARG_3[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_4", REG_MMIO, 0xa8, &mmSMC_MSG_ARG_4[0], sizeof(mmSMC_MSG_ARG_4)/sizeof(mmSMC_MSG_ARG_4[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_5", REG_MMIO, 0xa9, &mmSMC_MSG_ARG_5[0], sizeof(mmSMC_MSG_ARG_5)/sizeof(mmSMC_MSG_ARG_5[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_6", REG_MMIO, 0xaa, &mmSMC_MSG_ARG_6[0], sizeof(mmSMC_MSG_ARG_6)/sizeof(mmSMC_MSG_ARG_6[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_7", REG_MMIO, 0xab, &mmSMC_MSG_ARG_7[0], sizeof(mmSMC_MSG_ARG_7)/sizeof(mmSMC_MSG_ARG_7[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_8", REG_MMIO, 0xb5, &mmSMC_MESSAGE_8[0], sizeof(mmSMC_MESSAGE_8)/sizeof(mmSMC_MESSAGE_8[0]), 0, 0 },
+	{ "mmSMC_RESP_8", REG_MMIO, 0xb6, &mmSMC_RESP_8[0], sizeof(mmSMC_RESP_8)/sizeof(mmSMC_RESP_8[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_9", REG_MMIO, 0xb7, &mmSMC_MESSAGE_9[0], sizeof(mmSMC_MESSAGE_9)/sizeof(mmSMC_MESSAGE_9[0]), 0, 0 },
+	{ "mmSMC_RESP_9", REG_MMIO, 0xb8, &mmSMC_RESP_9[0], sizeof(mmSMC_RESP_9)/sizeof(mmSMC_RESP_9[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_10", REG_MMIO, 0xb9, &mmSMC_MESSAGE_10[0], sizeof(mmSMC_MESSAGE_10)/sizeof(mmSMC_MESSAGE_10[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU0", REG_SMC, 0xba, &ixGC_CAC_ACC_CU0[0], sizeof(ixGC_CAC_ACC_CU0)/sizeof(ixGC_CAC_ACC_CU0[0]), 0, 0 },
+	{ "mmSMC_RESP_10", REG_MMIO, 0xba, &mmSMC_RESP_10[0], sizeof(mmSMC_RESP_10)/sizeof(mmSMC_RESP_10[0]), 0, 0 },
+	{ "mmSMC_MESSAGE_11", REG_MMIO, 0xbb, &mmSMC_MESSAGE_11[0], sizeof(mmSMC_MESSAGE_11)/sizeof(mmSMC_MESSAGE_11[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU2", REG_SMC, 0xbc, &ixGC_CAC_ACC_CU2[0], sizeof(ixGC_CAC_ACC_CU2)/sizeof(ixGC_CAC_ACC_CU2[0]), 0, 0 },
+	{ "mmSMC_RESP_11", REG_MMIO, 0xbc, &mmSMC_RESP_11[0], sizeof(mmSMC_RESP_11)/sizeof(mmSMC_RESP_11[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU3", REG_SMC, 0xbd, &ixGC_CAC_ACC_CU3[0], sizeof(ixGC_CAC_ACC_CU3)/sizeof(ixGC_CAC_ACC_CU3[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_8", REG_MMIO, 0xbd, &mmSMC_MSG_ARG_8[0], sizeof(mmSMC_MSG_ARG_8)/sizeof(mmSMC_MSG_ARG_8[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU4", REG_SMC, 0xbe, &ixGC_CAC_ACC_CU4[0], sizeof(ixGC_CAC_ACC_CU4)/sizeof(ixGC_CAC_ACC_CU4[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_9", REG_MMIO, 0xbe, &mmSMC_MSG_ARG_9[0], sizeof(mmSMC_MSG_ARG_9)/sizeof(mmSMC_MSG_ARG_9[0]), 0, 0 },
+	{ "mmSMC_MSG_ARG_10", REG_MMIO, 0xbf, &mmSMC_MSG_ARG_10[0], sizeof(mmSMC_MSG_ARG_10)/sizeof(mmSMC_MSG_ARG_10[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU6", REG_SMC, 0xc0, &ixGC_CAC_ACC_CU6[0], sizeof(ixGC_CAC_ACC_CU6)/sizeof(ixGC_CAC_ACC_CU6[0]), 0, 0 },
+	{ "ixRCU_UC_EVENTS", REG_SMC, 0xc0000004, &ixRCU_UC_EVENTS[0], sizeof(ixRCU_UC_EVENTS)/sizeof(ixRCU_UC_EVENTS[0]), 0, 0 },
+	{ "ixRCU_MISC_CTRL", REG_SMC, 0xc0000010, &ixRCU_MISC_CTRL[0], sizeof(ixRCU_MISC_CTRL)/sizeof(ixRCU_MISC_CTRL[0]), 0, 0 },
+	{ "ixRCU_VIRT_RESET_REQ", REG_SMC, 0xc0000024, &ixRCU_VIRT_RESET_REQ[0], sizeof(ixRCU_VIRT_RESET_REQ)/sizeof(ixRCU_VIRT_RESET_REQ[0]), 0, 0 },
+	{ "ixCC_RCU_FUSES", REG_SMC, 0xc00c0000, &ixCC_RCU_FUSES[0], sizeof(ixCC_RCU_FUSES)/sizeof(ixCC_RCU_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_MISC_FUSES", REG_SMC, 0xc00c0004, &ixCC_SMU_MISC_FUSES[0], sizeof(ixCC_SMU_MISC_FUSES)/sizeof(ixCC_SMU_MISC_FUSES[0]), 0, 0 },
+	{ "ixCC_SCLK_VID_FUSES", REG_SMC, 0xc00c0008, &ixCC_SCLK_VID_FUSES[0], sizeof(ixCC_SCLK_VID_FUSES)/sizeof(ixCC_SCLK_VID_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOCCFG_FUSES", REG_SMC, 0xc00c000c, &ixCC_GIO_IOCCFG_FUSES[0], sizeof(ixCC_GIO_IOCCFG_FUSES)/sizeof(ixCC_GIO_IOCCFG_FUSES[0]), 0, 0 },
+	{ "ixCC_GIO_IOC_FUSES", REG_SMC, 0xc00c0010, &ixCC_GIO_IOC_FUSES[0], sizeof(ixCC_GIO_IOC_FUSES)/sizeof(ixCC_GIO_IOC_FUSES[0]), 0, 0 },
+	{ "ixCC_SMU_TST_EFUSE1_MISC", REG_SMC, 0xc00c001c, &ixCC_SMU_TST_EFUSE1_MISC[0], sizeof(ixCC_SMU_TST_EFUSE1_MISC)/sizeof(ixCC_SMU_TST_EFUSE1_MISC[0]), 0, 0 },
+	{ "ixCC_TST_ID_STRAPS", REG_SMC, 0xc00c0020, &ixCC_TST_ID_STRAPS[0], sizeof(ixCC_TST_ID_STRAPS)/sizeof(ixCC_TST_ID_STRAPS[0]), 0, 0 },
+	{ "ixCC_FCTRL_FUSES", REG_SMC, 0xc00c0024, &ixCC_FCTRL_FUSES[0], sizeof(ixCC_FCTRL_FUSES)/sizeof(ixCC_FCTRL_FUSES[0]), 0, 0 },
+	{ "ixCC_HARVEST_FUSES", REG_SMC, 0xc00c0028, &ixCC_HARVEST_FUSES[0], sizeof(ixCC_HARVEST_FUSES)/sizeof(ixCC_HARVEST_FUSES[0]), 0, 0 },
+	{ "ixSMU_EFUSE_0", REG_SMC, 0xc0100000, &ixSMU_EFUSE_0[0], sizeof(ixSMU_EFUSE_0)/sizeof(ixSMU_EFUSE_0[0]), 0, 0 },
+	{ "ixGENERAL_PWRMGT", REG_SMC, 0xc0200000, &ixGENERAL_PWRMGT[0], sizeof(ixGENERAL_PWRMGT)/sizeof(ixGENERAL_PWRMGT[0]), 0, 0 },
+	{ "ixCNB_PWRMGT_CNTL", REG_SMC, 0xc0200004, &ixCNB_PWRMGT_CNTL[0], sizeof(ixCNB_PWRMGT_CNTL)/sizeof(ixCNB_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixSCLK_PWRMGT_CNTL", REG_SMC, 0xc0200008, &ixSCLK_PWRMGT_CNTL[0], sizeof(ixSCLK_PWRMGT_CNTL)/sizeof(ixSCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX", REG_SMC, 0xc0200014, &ixTARGET_AND_CURRENT_PROFILE_INDEX[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX[0]), 0, 0 },
+	{ "ixPWR_PCC_CONTROL", REG_SMC, 0xc0200018, &ixPWR_PCC_CONTROL[0], sizeof(ixPWR_PCC_CONTROL)/sizeof(ixPWR_PCC_CONTROL[0]), 0, 0 },
+	{ "ixPWR_PCC_GPIO_SELECT", REG_SMC, 0xc020001c, &ixPWR_PCC_GPIO_SELECT[0], sizeof(ixPWR_PCC_GPIO_SELECT)/sizeof(ixPWR_PCC_GPIO_SELECT[0]), 0, 0 },
+	{ "ixPLL_TEST_CNTL", REG_SMC, 0xc020003c, &ixPLL_TEST_CNTL[0], sizeof(ixPLL_TEST_CNTL)/sizeof(ixPLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixCG_STATIC_SCREEN_PARAMETER", REG_SMC, 0xc0200044, &ixCG_STATIC_SCREEN_PARAMETER[0], sizeof(ixCG_STATIC_SCREEN_PARAMETER)/sizeof(ixCG_STATIC_SCREEN_PARAMETER[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL", REG_SMC, 0xc0200060, &ixCG_DISPLAY_GAP_CNTL[0], sizeof(ixCG_DISPLAY_GAP_CNTL)/sizeof(ixCG_DISPLAY_GAP_CNTL[0]), 0, 0 },
+	{ "ixCG_ACPI_CNTL", REG_SMC, 0xc0200064, &ixCG_ACPI_CNTL[0], sizeof(ixCG_ACPI_CNTL)/sizeof(ixCG_ACPI_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc0200080, &ixSCLK_DEEP_SLEEP_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200084, &ixSCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL2)/sizeof(ixSCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_MISC_CNTL", REG_SMC, 0xc0200088, &ixSCLK_DEEP_SLEEP_MISC_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xc020008c, &ixLCLK_DEEP_SLEEP_CNTL[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL)/sizeof(ixLCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL3", REG_SMC, 0xc020009c, &ixSCLK_DEEP_SLEEP_CNTL3[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL3)/sizeof(ixSCLK_DEEP_SLEEP_CNTL3[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_1", REG_SMC, 0xc02000f0, &ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0]), 0, 0 },
+	{ "ixCG_ULV_PARAMETER", REG_SMC, 0xc020015c, &ixCG_ULV_PARAMETER[0], sizeof(ixCG_ULV_PARAMETER)/sizeof(ixCG_ULV_PARAMETER[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_0", REG_SMC, 0xc02001a8, &ixCG_FREQ_TRAN_VOTING_0[0], sizeof(ixCG_FREQ_TRAN_VOTING_0)/sizeof(ixCG_FREQ_TRAN_VOTING_0[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_1", REG_SMC, 0xc02001ac, &ixCG_FREQ_TRAN_VOTING_1[0], sizeof(ixCG_FREQ_TRAN_VOTING_1)/sizeof(ixCG_FREQ_TRAN_VOTING_1[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_2", REG_SMC, 0xc02001b0, &ixCG_FREQ_TRAN_VOTING_2[0], sizeof(ixCG_FREQ_TRAN_VOTING_2)/sizeof(ixCG_FREQ_TRAN_VOTING_2[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_3", REG_SMC, 0xc02001b4, &ixCG_FREQ_TRAN_VOTING_3[0], sizeof(ixCG_FREQ_TRAN_VOTING_3)/sizeof(ixCG_FREQ_TRAN_VOTING_3[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_4", REG_SMC, 0xc02001b8, &ixCG_FREQ_TRAN_VOTING_4[0], sizeof(ixCG_FREQ_TRAN_VOTING_4)/sizeof(ixCG_FREQ_TRAN_VOTING_4[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_5", REG_SMC, 0xc02001bc, &ixCG_FREQ_TRAN_VOTING_5[0], sizeof(ixCG_FREQ_TRAN_VOTING_5)/sizeof(ixCG_FREQ_TRAN_VOTING_5[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xc02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xc02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
+	{ "ixCG_DISPLAY_GAP_CNTL2", REG_SMC, 0xc0200230, &ixCG_DISPLAY_GAP_CNTL2[0], sizeof(ixCG_DISPLAY_GAP_CNTL2)/sizeof(ixCG_DISPLAY_GAP_CNTL2[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xc0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixPWR_CKS_ENABLE", REG_SMC, 0xc020034c, &ixPWR_CKS_ENABLE[0], sizeof(ixPWR_CKS_ENABLE)/sizeof(ixPWR_CKS_ENABLE[0]), 0, 0 },
+	{ "ixPWR_CKS_CNTL", REG_SMC, 0xc0200350, &ixPWR_CKS_CNTL[0], sizeof(ixPWR_CKS_CNTL)/sizeof(ixPWR_CKS_CNTL[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_PARAMETER", REG_SMC, 0xc020036c, &ixVDDGFX_IDLE_PARAMETER[0], sizeof(ixVDDGFX_IDLE_PARAMETER)/sizeof(ixVDDGFX_IDLE_PARAMETER[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_CONTROL", REG_SMC, 0xc0200370, &ixVDDGFX_IDLE_CONTROL[0], sizeof(ixVDDGFX_IDLE_CONTROL)/sizeof(ixVDDGFX_IDLE_CONTROL[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_EXIT", REG_SMC, 0xc0200374, &ixVDDGFX_IDLE_EXIT[0], sizeof(ixVDDGFX_IDLE_EXIT)/sizeof(ixVDDGFX_IDLE_EXIT[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_CONTROL2", REG_SMC, 0xc0200378, &ixPWR_DISP_TIMER_CONTROL2[0], sizeof(ixPWR_DISP_TIMER_CONTROL2)/sizeof(ixPWR_DISP_TIMER_CONTROL2[0]), 0, 0 },
+	{ "ixPWR_AVFS_SEL", REG_SMC, 0xc0200384, &ixPWR_AVFS_SEL[0], sizeof(ixPWR_AVFS_SEL)/sizeof(ixPWR_AVFS_SEL[0]), 0, 0 },
+	{ "ixPWR_AVFS_CNTL", REG_SMC, 0xc0200388, &ixPWR_AVFS_CNTL[0], sizeof(ixPWR_AVFS_CNTL)/sizeof(ixPWR_AVFS_CNTL[0]), 0, 0 },
+	{ "ixSCLK_MIN_DIV", REG_SMC, 0xc02003ac, &ixSCLK_MIN_DIV[0], sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_CONTROL", REG_SMC, 0xc02003c0, &ixPWR_DISP_TIMER_CONTROL[0], sizeof(ixPWR_DISP_TIMER_CONTROL)/sizeof(ixPWR_DISP_TIMER_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER_DEBUG", REG_SMC, 0xc02003c4, &ixPWR_DISP_TIMER_DEBUG[0], sizeof(ixPWR_DISP_TIMER_DEBUG)/sizeof(ixPWR_DISP_TIMER_DEBUG[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER2_CONTROL", REG_SMC, 0xc02003c8, &ixPWR_DISP_TIMER2_CONTROL[0], sizeof(ixPWR_DISP_TIMER2_CONTROL)/sizeof(ixPWR_DISP_TIMER2_CONTROL[0]), 0, 0 },
+	{ "ixPWR_DISP_TIMER2_DEBUG", REG_SMC, 0xc02003cc, &ixPWR_DISP_TIMER2_DEBUG[0], sizeof(ixPWR_DISP_TIMER2_DEBUG)/sizeof(ixPWR_DISP_TIMER2_DEBUG[0]), 0, 0 },
+	{ "ixPWR_AVFS0_CNTL_STATUS", REG_SMC, 0xc0200400, &ixPWR_AVFS0_CNTL_STATUS[0], sizeof(ixPWR_AVFS0_CNTL_STATUS)/sizeof(ixPWR_AVFS0_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS1_CNTL_STATUS", REG_SMC, 0xc0200404, &ixPWR_AVFS1_CNTL_STATUS[0], sizeof(ixPWR_AVFS1_CNTL_STATUS)/sizeof(ixPWR_AVFS1_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS2_CNTL_STATUS", REG_SMC, 0xc0200408, &ixPWR_AVFS2_CNTL_STATUS[0], sizeof(ixPWR_AVFS2_CNTL_STATUS)/sizeof(ixPWR_AVFS2_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS3_CNTL_STATUS", REG_SMC, 0xc020040c, &ixPWR_AVFS3_CNTL_STATUS[0], sizeof(ixPWR_AVFS3_CNTL_STATUS)/sizeof(ixPWR_AVFS3_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS4_CNTL_STATUS", REG_SMC, 0xc0200410, &ixPWR_AVFS4_CNTL_STATUS[0], sizeof(ixPWR_AVFS4_CNTL_STATUS)/sizeof(ixPWR_AVFS4_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS5_CNTL_STATUS", REG_SMC, 0xc0200414, &ixPWR_AVFS5_CNTL_STATUS[0], sizeof(ixPWR_AVFS5_CNTL_STATUS)/sizeof(ixPWR_AVFS5_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS6_CNTL_STATUS", REG_SMC, 0xc0200418, &ixPWR_AVFS6_CNTL_STATUS[0], sizeof(ixPWR_AVFS6_CNTL_STATUS)/sizeof(ixPWR_AVFS6_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS7_CNTL_STATUS", REG_SMC, 0xc020041c, &ixPWR_AVFS7_CNTL_STATUS[0], sizeof(ixPWR_AVFS7_CNTL_STATUS)/sizeof(ixPWR_AVFS7_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS8_CNTL_STATUS", REG_SMC, 0xc0200420, &ixPWR_AVFS8_CNTL_STATUS[0], sizeof(ixPWR_AVFS8_CNTL_STATUS)/sizeof(ixPWR_AVFS8_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS9_CNTL_STATUS", REG_SMC, 0xc0200424, &ixPWR_AVFS9_CNTL_STATUS[0], sizeof(ixPWR_AVFS9_CNTL_STATUS)/sizeof(ixPWR_AVFS9_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS10_CNTL_STATUS", REG_SMC, 0xc0200428, &ixPWR_AVFS10_CNTL_STATUS[0], sizeof(ixPWR_AVFS10_CNTL_STATUS)/sizeof(ixPWR_AVFS10_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS11_CNTL_STATUS", REG_SMC, 0xc020042c, &ixPWR_AVFS11_CNTL_STATUS[0], sizeof(ixPWR_AVFS11_CNTL_STATUS)/sizeof(ixPWR_AVFS11_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS12_CNTL_STATUS", REG_SMC, 0xc0200430, &ixPWR_AVFS12_CNTL_STATUS[0], sizeof(ixPWR_AVFS12_CNTL_STATUS)/sizeof(ixPWR_AVFS12_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS13_CNTL_STATUS", REG_SMC, 0xc0200434, &ixPWR_AVFS13_CNTL_STATUS[0], sizeof(ixPWR_AVFS13_CNTL_STATUS)/sizeof(ixPWR_AVFS13_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS14_CNTL_STATUS", REG_SMC, 0xc0200438, &ixPWR_AVFS14_CNTL_STATUS[0], sizeof(ixPWR_AVFS14_CNTL_STATUS)/sizeof(ixPWR_AVFS14_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS15_CNTL_STATUS", REG_SMC, 0xc020043c, &ixPWR_AVFS15_CNTL_STATUS[0], sizeof(ixPWR_AVFS15_CNTL_STATUS)/sizeof(ixPWR_AVFS15_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS16_CNTL_STATUS", REG_SMC, 0xc0200440, &ixPWR_AVFS16_CNTL_STATUS[0], sizeof(ixPWR_AVFS16_CNTL_STATUS)/sizeof(ixPWR_AVFS16_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS17_CNTL_STATUS", REG_SMC, 0xc0200444, &ixPWR_AVFS17_CNTL_STATUS[0], sizeof(ixPWR_AVFS17_CNTL_STATUS)/sizeof(ixPWR_AVFS17_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS18_CNTL_STATUS", REG_SMC, 0xc0200448, &ixPWR_AVFS18_CNTL_STATUS[0], sizeof(ixPWR_AVFS18_CNTL_STATUS)/sizeof(ixPWR_AVFS18_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS19_CNTL_STATUS", REG_SMC, 0xc020044c, &ixPWR_AVFS19_CNTL_STATUS[0], sizeof(ixPWR_AVFS19_CNTL_STATUS)/sizeof(ixPWR_AVFS19_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS20_CNTL_STATUS", REG_SMC, 0xc0200450, &ixPWR_AVFS20_CNTL_STATUS[0], sizeof(ixPWR_AVFS20_CNTL_STATUS)/sizeof(ixPWR_AVFS20_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS21_CNTL_STATUS", REG_SMC, 0xc0200454, &ixPWR_AVFS21_CNTL_STATUS[0], sizeof(ixPWR_AVFS21_CNTL_STATUS)/sizeof(ixPWR_AVFS21_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS22_CNTL_STATUS", REG_SMC, 0xc0200458, &ixPWR_AVFS22_CNTL_STATUS[0], sizeof(ixPWR_AVFS22_CNTL_STATUS)/sizeof(ixPWR_AVFS22_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS23_CNTL_STATUS", REG_SMC, 0xc020045c, &ixPWR_AVFS23_CNTL_STATUS[0], sizeof(ixPWR_AVFS23_CNTL_STATUS)/sizeof(ixPWR_AVFS23_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS24_CNTL_STATUS", REG_SMC, 0xc0200460, &ixPWR_AVFS24_CNTL_STATUS[0], sizeof(ixPWR_AVFS24_CNTL_STATUS)/sizeof(ixPWR_AVFS24_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS25_CNTL_STATUS", REG_SMC, 0xc0200464, &ixPWR_AVFS25_CNTL_STATUS[0], sizeof(ixPWR_AVFS25_CNTL_STATUS)/sizeof(ixPWR_AVFS25_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS26_CNTL_STATUS", REG_SMC, 0xc0200468, &ixPWR_AVFS26_CNTL_STATUS[0], sizeof(ixPWR_AVFS26_CNTL_STATUS)/sizeof(ixPWR_AVFS26_CNTL_STATUS[0]), 0, 0 },
+	{ "ixPWR_AVFS27_CNTL_STATUS", REG_SMC, 0xc020046c, &ixPWR_AVFS27_CNTL_STATUS[0], sizeof(ixPWR_AVFS27_CNTL_STATUS)/sizeof(ixPWR_AVFS27_CNTL_STATUS[0]), 0, 0 },
+	{ "ixCG_THERMAL_CTRL", REG_SMC, 0xc0300004, &ixCG_THERMAL_CTRL[0], sizeof(ixCG_THERMAL_CTRL)/sizeof(ixCG_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_STATUS", REG_SMC, 0xc0300008, &ixCG_THERMAL_STATUS[0], sizeof(ixCG_THERMAL_STATUS)/sizeof(ixCG_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT", REG_SMC, 0xc030000c, &ixCG_THERMAL_INT[0], sizeof(ixCG_THERMAL_INT)/sizeof(ixCG_THERMAL_INT[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_CTRL", REG_SMC, 0xc0300010, &ixCG_MULT_THERMAL_CTRL[0], sizeof(ixCG_MULT_THERMAL_CTRL)/sizeof(ixCG_MULT_THERMAL_CTRL[0]), 0, 0 },
+	{ "ixCG_MULT_THERMAL_STATUS", REG_SMC, 0xc0300014, &ixCG_MULT_THERMAL_STATUS[0], sizeof(ixCG_MULT_THERMAL_STATUS)/sizeof(ixCG_MULT_THERMAL_STATUS[0]), 0, 0 },
+	{ "ixTHM_TMON2_CTRL", REG_SMC, 0xc0300034, &ixTHM_TMON2_CTRL[0], sizeof(ixTHM_TMON2_CTRL)/sizeof(ixTHM_TMON2_CTRL[0]), 0, 0 },
+	{ "ixTHM_TMON2_CTRL2", REG_SMC, 0xc0300038, &ixTHM_TMON2_CTRL2[0], sizeof(ixTHM_TMON2_CTRL2)/sizeof(ixTHM_TMON2_CTRL2[0]), 0, 0 },
+	{ "ixTHM_TMON2_CSR_WR", REG_SMC, 0xc0300054, &ixTHM_TMON2_CSR_WR[0], sizeof(ixTHM_TMON2_CSR_WR)/sizeof(ixTHM_TMON2_CSR_WR[0]), 0, 0 },
+	{ "ixTHM_TMON2_CSR_RD", REG_SMC, 0xc0300058, &ixTHM_TMON2_CSR_RD[0], sizeof(ixTHM_TMON2_CSR_RD)/sizeof(ixTHM_TMON2_CSR_RD[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL0", REG_SMC, 0xc0300064, &ixCG_FDO_CTRL0[0], sizeof(ixCG_FDO_CTRL0)/sizeof(ixCG_FDO_CTRL0[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL1", REG_SMC, 0xc0300068, &ixCG_FDO_CTRL1[0], sizeof(ixCG_FDO_CTRL1)/sizeof(ixCG_FDO_CTRL1[0]), 0, 0 },
+	{ "ixCG_FDO_CTRL2", REG_SMC, 0xc030006c, &ixCG_FDO_CTRL2[0], sizeof(ixCG_FDO_CTRL2)/sizeof(ixCG_FDO_CTRL2[0]), 0, 0 },
+	{ "ixCG_TACH_CTRL", REG_SMC, 0xc0300070, &ixCG_TACH_CTRL[0], sizeof(ixCG_TACH_CTRL)/sizeof(ixCG_TACH_CTRL[0]), 0, 0 },
+	{ "ixCG_TACH_STATUS", REG_SMC, 0xc0300074, &ixCG_TACH_STATUS[0], sizeof(ixCG_TACH_STATUS)/sizeof(ixCG_TACH_STATUS[0]), 0, 0 },
+	{ "ixCC_THM_STRAPS0", REG_SMC, 0xc0300080, &ixCC_THM_STRAPS0[0], sizeof(ixCC_THM_STRAPS0)/sizeof(ixCC_THM_STRAPS0[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL0_DATA", REG_SMC, 0xc0300100, &ixTHM_TMON0_RDIL0_DATA[0], sizeof(ixTHM_TMON0_RDIL0_DATA)/sizeof(ixTHM_TMON0_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL1_DATA", REG_SMC, 0xc0300104, &ixTHM_TMON0_RDIL1_DATA[0], sizeof(ixTHM_TMON0_RDIL1_DATA)/sizeof(ixTHM_TMON0_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL2_DATA", REG_SMC, 0xc0300108, &ixTHM_TMON0_RDIL2_DATA[0], sizeof(ixTHM_TMON0_RDIL2_DATA)/sizeof(ixTHM_TMON0_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL3_DATA", REG_SMC, 0xc030010c, &ixTHM_TMON0_RDIL3_DATA[0], sizeof(ixTHM_TMON0_RDIL3_DATA)/sizeof(ixTHM_TMON0_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL4_DATA", REG_SMC, 0xc0300110, &ixTHM_TMON0_RDIL4_DATA[0], sizeof(ixTHM_TMON0_RDIL4_DATA)/sizeof(ixTHM_TMON0_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL5_DATA", REG_SMC, 0xc0300114, &ixTHM_TMON0_RDIL5_DATA[0], sizeof(ixTHM_TMON0_RDIL5_DATA)/sizeof(ixTHM_TMON0_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL6_DATA", REG_SMC, 0xc0300118, &ixTHM_TMON0_RDIL6_DATA[0], sizeof(ixTHM_TMON0_RDIL6_DATA)/sizeof(ixTHM_TMON0_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL7_DATA", REG_SMC, 0xc030011c, &ixTHM_TMON0_RDIL7_DATA[0], sizeof(ixTHM_TMON0_RDIL7_DATA)/sizeof(ixTHM_TMON0_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL8_DATA", REG_SMC, 0xc0300120, &ixTHM_TMON0_RDIL8_DATA[0], sizeof(ixTHM_TMON0_RDIL8_DATA)/sizeof(ixTHM_TMON0_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL9_DATA", REG_SMC, 0xc0300124, &ixTHM_TMON0_RDIL9_DATA[0], sizeof(ixTHM_TMON0_RDIL9_DATA)/sizeof(ixTHM_TMON0_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL10_DATA", REG_SMC, 0xc0300128, &ixTHM_TMON0_RDIL10_DATA[0], sizeof(ixTHM_TMON0_RDIL10_DATA)/sizeof(ixTHM_TMON0_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL11_DATA", REG_SMC, 0xc030012c, &ixTHM_TMON0_RDIL11_DATA[0], sizeof(ixTHM_TMON0_RDIL11_DATA)/sizeof(ixTHM_TMON0_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL12_DATA", REG_SMC, 0xc0300130, &ixTHM_TMON0_RDIL12_DATA[0], sizeof(ixTHM_TMON0_RDIL12_DATA)/sizeof(ixTHM_TMON0_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL13_DATA", REG_SMC, 0xc0300134, &ixTHM_TMON0_RDIL13_DATA[0], sizeof(ixTHM_TMON0_RDIL13_DATA)/sizeof(ixTHM_TMON0_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL14_DATA", REG_SMC, 0xc0300138, &ixTHM_TMON0_RDIL14_DATA[0], sizeof(ixTHM_TMON0_RDIL14_DATA)/sizeof(ixTHM_TMON0_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIL15_DATA", REG_SMC, 0xc030013c, &ixTHM_TMON0_RDIL15_DATA[0], sizeof(ixTHM_TMON0_RDIL15_DATA)/sizeof(ixTHM_TMON0_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR0_DATA", REG_SMC, 0xc0300140, &ixTHM_TMON0_RDIR0_DATA[0], sizeof(ixTHM_TMON0_RDIR0_DATA)/sizeof(ixTHM_TMON0_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR1_DATA", REG_SMC, 0xc0300144, &ixTHM_TMON0_RDIR1_DATA[0], sizeof(ixTHM_TMON0_RDIR1_DATA)/sizeof(ixTHM_TMON0_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR2_DATA", REG_SMC, 0xc0300148, &ixTHM_TMON0_RDIR2_DATA[0], sizeof(ixTHM_TMON0_RDIR2_DATA)/sizeof(ixTHM_TMON0_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR3_DATA", REG_SMC, 0xc030014c, &ixTHM_TMON0_RDIR3_DATA[0], sizeof(ixTHM_TMON0_RDIR3_DATA)/sizeof(ixTHM_TMON0_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR4_DATA", REG_SMC, 0xc0300150, &ixTHM_TMON0_RDIR4_DATA[0], sizeof(ixTHM_TMON0_RDIR4_DATA)/sizeof(ixTHM_TMON0_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR5_DATA", REG_SMC, 0xc0300154, &ixTHM_TMON0_RDIR5_DATA[0], sizeof(ixTHM_TMON0_RDIR5_DATA)/sizeof(ixTHM_TMON0_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR6_DATA", REG_SMC, 0xc0300158, &ixTHM_TMON0_RDIR6_DATA[0], sizeof(ixTHM_TMON0_RDIR6_DATA)/sizeof(ixTHM_TMON0_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR7_DATA", REG_SMC, 0xc030015c, &ixTHM_TMON0_RDIR7_DATA[0], sizeof(ixTHM_TMON0_RDIR7_DATA)/sizeof(ixTHM_TMON0_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR8_DATA", REG_SMC, 0xc0300160, &ixTHM_TMON0_RDIR8_DATA[0], sizeof(ixTHM_TMON0_RDIR8_DATA)/sizeof(ixTHM_TMON0_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR9_DATA", REG_SMC, 0xc0300164, &ixTHM_TMON0_RDIR9_DATA[0], sizeof(ixTHM_TMON0_RDIR9_DATA)/sizeof(ixTHM_TMON0_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR10_DATA", REG_SMC, 0xc0300168, &ixTHM_TMON0_RDIR10_DATA[0], sizeof(ixTHM_TMON0_RDIR10_DATA)/sizeof(ixTHM_TMON0_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR11_DATA", REG_SMC, 0xc030016c, &ixTHM_TMON0_RDIR11_DATA[0], sizeof(ixTHM_TMON0_RDIR11_DATA)/sizeof(ixTHM_TMON0_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR12_DATA", REG_SMC, 0xc0300170, &ixTHM_TMON0_RDIR12_DATA[0], sizeof(ixTHM_TMON0_RDIR12_DATA)/sizeof(ixTHM_TMON0_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR13_DATA", REG_SMC, 0xc0300174, &ixTHM_TMON0_RDIR13_DATA[0], sizeof(ixTHM_TMON0_RDIR13_DATA)/sizeof(ixTHM_TMON0_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR14_DATA", REG_SMC, 0xc0300178, &ixTHM_TMON0_RDIR14_DATA[0], sizeof(ixTHM_TMON0_RDIR14_DATA)/sizeof(ixTHM_TMON0_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_RDIR15_DATA", REG_SMC, 0xc030017c, &ixTHM_TMON0_RDIR15_DATA[0], sizeof(ixTHM_TMON0_RDIR15_DATA)/sizeof(ixTHM_TMON0_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL0_DATA", REG_SMC, 0xc0300180, &ixTHM_TMON1_RDIL0_DATA[0], sizeof(ixTHM_TMON1_RDIL0_DATA)/sizeof(ixTHM_TMON1_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL1_DATA", REG_SMC, 0xc0300184, &ixTHM_TMON1_RDIL1_DATA[0], sizeof(ixTHM_TMON1_RDIL1_DATA)/sizeof(ixTHM_TMON1_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL2_DATA", REG_SMC, 0xc0300188, &ixTHM_TMON1_RDIL2_DATA[0], sizeof(ixTHM_TMON1_RDIL2_DATA)/sizeof(ixTHM_TMON1_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL3_DATA", REG_SMC, 0xc030018c, &ixTHM_TMON1_RDIL3_DATA[0], sizeof(ixTHM_TMON1_RDIL3_DATA)/sizeof(ixTHM_TMON1_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL4_DATA", REG_SMC, 0xc0300190, &ixTHM_TMON1_RDIL4_DATA[0], sizeof(ixTHM_TMON1_RDIL4_DATA)/sizeof(ixTHM_TMON1_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL5_DATA", REG_SMC, 0xc0300194, &ixTHM_TMON1_RDIL5_DATA[0], sizeof(ixTHM_TMON1_RDIL5_DATA)/sizeof(ixTHM_TMON1_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL6_DATA", REG_SMC, 0xc0300198, &ixTHM_TMON1_RDIL6_DATA[0], sizeof(ixTHM_TMON1_RDIL6_DATA)/sizeof(ixTHM_TMON1_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL7_DATA", REG_SMC, 0xc030019c, &ixTHM_TMON1_RDIL7_DATA[0], sizeof(ixTHM_TMON1_RDIL7_DATA)/sizeof(ixTHM_TMON1_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL8_DATA", REG_SMC, 0xc03001a0, &ixTHM_TMON1_RDIL8_DATA[0], sizeof(ixTHM_TMON1_RDIL8_DATA)/sizeof(ixTHM_TMON1_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL9_DATA", REG_SMC, 0xc03001a4, &ixTHM_TMON1_RDIL9_DATA[0], sizeof(ixTHM_TMON1_RDIL9_DATA)/sizeof(ixTHM_TMON1_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL10_DATA", REG_SMC, 0xc03001a8, &ixTHM_TMON1_RDIL10_DATA[0], sizeof(ixTHM_TMON1_RDIL10_DATA)/sizeof(ixTHM_TMON1_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL11_DATA", REG_SMC, 0xc03001ac, &ixTHM_TMON1_RDIL11_DATA[0], sizeof(ixTHM_TMON1_RDIL11_DATA)/sizeof(ixTHM_TMON1_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL12_DATA", REG_SMC, 0xc03001b0, &ixTHM_TMON1_RDIL12_DATA[0], sizeof(ixTHM_TMON1_RDIL12_DATA)/sizeof(ixTHM_TMON1_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL13_DATA", REG_SMC, 0xc03001b4, &ixTHM_TMON1_RDIL13_DATA[0], sizeof(ixTHM_TMON1_RDIL13_DATA)/sizeof(ixTHM_TMON1_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL14_DATA", REG_SMC, 0xc03001b8, &ixTHM_TMON1_RDIL14_DATA[0], sizeof(ixTHM_TMON1_RDIL14_DATA)/sizeof(ixTHM_TMON1_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIL15_DATA", REG_SMC, 0xc03001bc, &ixTHM_TMON1_RDIL15_DATA[0], sizeof(ixTHM_TMON1_RDIL15_DATA)/sizeof(ixTHM_TMON1_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR0_DATA", REG_SMC, 0xc03001c0, &ixTHM_TMON1_RDIR0_DATA[0], sizeof(ixTHM_TMON1_RDIR0_DATA)/sizeof(ixTHM_TMON1_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR1_DATA", REG_SMC, 0xc03001c4, &ixTHM_TMON1_RDIR1_DATA[0], sizeof(ixTHM_TMON1_RDIR1_DATA)/sizeof(ixTHM_TMON1_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR2_DATA", REG_SMC, 0xc03001c8, &ixTHM_TMON1_RDIR2_DATA[0], sizeof(ixTHM_TMON1_RDIR2_DATA)/sizeof(ixTHM_TMON1_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR3_DATA", REG_SMC, 0xc03001cc, &ixTHM_TMON1_RDIR3_DATA[0], sizeof(ixTHM_TMON1_RDIR3_DATA)/sizeof(ixTHM_TMON1_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR4_DATA", REG_SMC, 0xc03001d0, &ixTHM_TMON1_RDIR4_DATA[0], sizeof(ixTHM_TMON1_RDIR4_DATA)/sizeof(ixTHM_TMON1_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR5_DATA", REG_SMC, 0xc03001d4, &ixTHM_TMON1_RDIR5_DATA[0], sizeof(ixTHM_TMON1_RDIR5_DATA)/sizeof(ixTHM_TMON1_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR6_DATA", REG_SMC, 0xc03001d8, &ixTHM_TMON1_RDIR6_DATA[0], sizeof(ixTHM_TMON1_RDIR6_DATA)/sizeof(ixTHM_TMON1_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR7_DATA", REG_SMC, 0xc03001dc, &ixTHM_TMON1_RDIR7_DATA[0], sizeof(ixTHM_TMON1_RDIR7_DATA)/sizeof(ixTHM_TMON1_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR8_DATA", REG_SMC, 0xc03001e0, &ixTHM_TMON1_RDIR8_DATA[0], sizeof(ixTHM_TMON1_RDIR8_DATA)/sizeof(ixTHM_TMON1_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR9_DATA", REG_SMC, 0xc03001e4, &ixTHM_TMON1_RDIR9_DATA[0], sizeof(ixTHM_TMON1_RDIR9_DATA)/sizeof(ixTHM_TMON1_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR10_DATA", REG_SMC, 0xc03001e8, &ixTHM_TMON1_RDIR10_DATA[0], sizeof(ixTHM_TMON1_RDIR10_DATA)/sizeof(ixTHM_TMON1_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR11_DATA", REG_SMC, 0xc03001ec, &ixTHM_TMON1_RDIR11_DATA[0], sizeof(ixTHM_TMON1_RDIR11_DATA)/sizeof(ixTHM_TMON1_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR12_DATA", REG_SMC, 0xc03001f0, &ixTHM_TMON1_RDIR12_DATA[0], sizeof(ixTHM_TMON1_RDIR12_DATA)/sizeof(ixTHM_TMON1_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR13_DATA", REG_SMC, 0xc03001f4, &ixTHM_TMON1_RDIR13_DATA[0], sizeof(ixTHM_TMON1_RDIR13_DATA)/sizeof(ixTHM_TMON1_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR14_DATA", REG_SMC, 0xc03001f8, &ixTHM_TMON1_RDIR14_DATA[0], sizeof(ixTHM_TMON1_RDIR14_DATA)/sizeof(ixTHM_TMON1_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_RDIR15_DATA", REG_SMC, 0xc03001fc, &ixTHM_TMON1_RDIR15_DATA[0], sizeof(ixTHM_TMON1_RDIR15_DATA)/sizeof(ixTHM_TMON1_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL0_DATA", REG_SMC, 0xc0300200, &ixTHM_TMON2_RDIL0_DATA[0], sizeof(ixTHM_TMON2_RDIL0_DATA)/sizeof(ixTHM_TMON2_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL1_DATA", REG_SMC, 0xc0300204, &ixTHM_TMON2_RDIL1_DATA[0], sizeof(ixTHM_TMON2_RDIL1_DATA)/sizeof(ixTHM_TMON2_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL2_DATA", REG_SMC, 0xc0300208, &ixTHM_TMON2_RDIL2_DATA[0], sizeof(ixTHM_TMON2_RDIL2_DATA)/sizeof(ixTHM_TMON2_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL3_DATA", REG_SMC, 0xc030020c, &ixTHM_TMON2_RDIL3_DATA[0], sizeof(ixTHM_TMON2_RDIL3_DATA)/sizeof(ixTHM_TMON2_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL4_DATA", REG_SMC, 0xc0300210, &ixTHM_TMON2_RDIL4_DATA[0], sizeof(ixTHM_TMON2_RDIL4_DATA)/sizeof(ixTHM_TMON2_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL5_DATA", REG_SMC, 0xc0300214, &ixTHM_TMON2_RDIL5_DATA[0], sizeof(ixTHM_TMON2_RDIL5_DATA)/sizeof(ixTHM_TMON2_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL6_DATA", REG_SMC, 0xc0300218, &ixTHM_TMON2_RDIL6_DATA[0], sizeof(ixTHM_TMON2_RDIL6_DATA)/sizeof(ixTHM_TMON2_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL7_DATA", REG_SMC, 0xc030021c, &ixTHM_TMON2_RDIL7_DATA[0], sizeof(ixTHM_TMON2_RDIL7_DATA)/sizeof(ixTHM_TMON2_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL8_DATA", REG_SMC, 0xc0300220, &ixTHM_TMON2_RDIL8_DATA[0], sizeof(ixTHM_TMON2_RDIL8_DATA)/sizeof(ixTHM_TMON2_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL9_DATA", REG_SMC, 0xc0300224, &ixTHM_TMON2_RDIL9_DATA[0], sizeof(ixTHM_TMON2_RDIL9_DATA)/sizeof(ixTHM_TMON2_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL10_DATA", REG_SMC, 0xc0300228, &ixTHM_TMON2_RDIL10_DATA[0], sizeof(ixTHM_TMON2_RDIL10_DATA)/sizeof(ixTHM_TMON2_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL11_DATA", REG_SMC, 0xc030022c, &ixTHM_TMON2_RDIL11_DATA[0], sizeof(ixTHM_TMON2_RDIL11_DATA)/sizeof(ixTHM_TMON2_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL12_DATA", REG_SMC, 0xc0300230, &ixTHM_TMON2_RDIL12_DATA[0], sizeof(ixTHM_TMON2_RDIL12_DATA)/sizeof(ixTHM_TMON2_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL13_DATA", REG_SMC, 0xc0300234, &ixTHM_TMON2_RDIL13_DATA[0], sizeof(ixTHM_TMON2_RDIL13_DATA)/sizeof(ixTHM_TMON2_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL14_DATA", REG_SMC, 0xc0300238, &ixTHM_TMON2_RDIL14_DATA[0], sizeof(ixTHM_TMON2_RDIL14_DATA)/sizeof(ixTHM_TMON2_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIL15_DATA", REG_SMC, 0xc030023c, &ixTHM_TMON2_RDIL15_DATA[0], sizeof(ixTHM_TMON2_RDIL15_DATA)/sizeof(ixTHM_TMON2_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR0_DATA", REG_SMC, 0xc0300240, &ixTHM_TMON2_RDIR0_DATA[0], sizeof(ixTHM_TMON2_RDIR0_DATA)/sizeof(ixTHM_TMON2_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR1_DATA", REG_SMC, 0xc0300244, &ixTHM_TMON2_RDIR1_DATA[0], sizeof(ixTHM_TMON2_RDIR1_DATA)/sizeof(ixTHM_TMON2_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR2_DATA", REG_SMC, 0xc0300248, &ixTHM_TMON2_RDIR2_DATA[0], sizeof(ixTHM_TMON2_RDIR2_DATA)/sizeof(ixTHM_TMON2_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR3_DATA", REG_SMC, 0xc030024c, &ixTHM_TMON2_RDIR3_DATA[0], sizeof(ixTHM_TMON2_RDIR3_DATA)/sizeof(ixTHM_TMON2_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR4_DATA", REG_SMC, 0xc0300250, &ixTHM_TMON2_RDIR4_DATA[0], sizeof(ixTHM_TMON2_RDIR4_DATA)/sizeof(ixTHM_TMON2_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR5_DATA", REG_SMC, 0xc0300254, &ixTHM_TMON2_RDIR5_DATA[0], sizeof(ixTHM_TMON2_RDIR5_DATA)/sizeof(ixTHM_TMON2_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR6_DATA", REG_SMC, 0xc0300258, &ixTHM_TMON2_RDIR6_DATA[0], sizeof(ixTHM_TMON2_RDIR6_DATA)/sizeof(ixTHM_TMON2_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR7_DATA", REG_SMC, 0xc030025c, &ixTHM_TMON2_RDIR7_DATA[0], sizeof(ixTHM_TMON2_RDIR7_DATA)/sizeof(ixTHM_TMON2_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR8_DATA", REG_SMC, 0xc0300260, &ixTHM_TMON2_RDIR8_DATA[0], sizeof(ixTHM_TMON2_RDIR8_DATA)/sizeof(ixTHM_TMON2_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR9_DATA", REG_SMC, 0xc0300264, &ixTHM_TMON2_RDIR9_DATA[0], sizeof(ixTHM_TMON2_RDIR9_DATA)/sizeof(ixTHM_TMON2_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR10_DATA", REG_SMC, 0xc0300268, &ixTHM_TMON2_RDIR10_DATA[0], sizeof(ixTHM_TMON2_RDIR10_DATA)/sizeof(ixTHM_TMON2_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR11_DATA", REG_SMC, 0xc030026c, &ixTHM_TMON2_RDIR11_DATA[0], sizeof(ixTHM_TMON2_RDIR11_DATA)/sizeof(ixTHM_TMON2_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR12_DATA", REG_SMC, 0xc0300270, &ixTHM_TMON2_RDIR12_DATA[0], sizeof(ixTHM_TMON2_RDIR12_DATA)/sizeof(ixTHM_TMON2_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR13_DATA", REG_SMC, 0xc0300274, &ixTHM_TMON2_RDIR13_DATA[0], sizeof(ixTHM_TMON2_RDIR13_DATA)/sizeof(ixTHM_TMON2_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR14_DATA", REG_SMC, 0xc0300278, &ixTHM_TMON2_RDIR14_DATA[0], sizeof(ixTHM_TMON2_RDIR14_DATA)/sizeof(ixTHM_TMON2_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_RDIR15_DATA", REG_SMC, 0xc030027c, &ixTHM_TMON2_RDIR15_DATA[0], sizeof(ixTHM_TMON2_RDIR15_DATA)/sizeof(ixTHM_TMON2_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_INT_DATA", REG_SMC, 0xc0300300, &ixTHM_TMON0_INT_DATA[0], sizeof(ixTHM_TMON0_INT_DATA)/sizeof(ixTHM_TMON0_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON1_INT_DATA", REG_SMC, 0xc0300304, &ixTHM_TMON1_INT_DATA[0], sizeof(ixTHM_TMON1_INT_DATA)/sizeof(ixTHM_TMON1_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON2_INT_DATA", REG_SMC, 0xc0300308, &ixTHM_TMON2_INT_DATA[0], sizeof(ixTHM_TMON2_INT_DATA)/sizeof(ixTHM_TMON2_INT_DATA[0]), 0, 0 },
+	{ "ixTHM_TMON0_DEBUG", REG_SMC, 0xc0300310, &ixTHM_TMON0_DEBUG[0], sizeof(ixTHM_TMON0_DEBUG)/sizeof(ixTHM_TMON0_DEBUG[0]), 0, 0 },
+	{ "ixTHM_TMON1_DEBUG", REG_SMC, 0xc0300314, &ixTHM_TMON1_DEBUG[0], sizeof(ixTHM_TMON1_DEBUG)/sizeof(ixTHM_TMON1_DEBUG[0]), 0, 0 },
+	{ "ixTHM_TMON2_DEBUG", REG_SMC, 0xc0300318, &ixTHM_TMON2_DEBUG[0], sizeof(ixTHM_TMON2_DEBUG)/sizeof(ixTHM_TMON2_DEBUG[0]), 0, 0 },
+	{ "ixTHM_TMON0_STATUS", REG_SMC, 0xc0300320, &ixTHM_TMON0_STATUS[0], sizeof(ixTHM_TMON0_STATUS)/sizeof(ixTHM_TMON0_STATUS[0]), 0, 0 },
+	{ "ixTHM_TMON1_STATUS", REG_SMC, 0xc0300324, &ixTHM_TMON1_STATUS[0], sizeof(ixTHM_TMON1_STATUS)/sizeof(ixTHM_TMON1_STATUS[0]), 0, 0 },
+	{ "ixTHM_TMON2_STATUS", REG_SMC, 0xc0300328, &ixTHM_TMON2_STATUS[0], sizeof(ixTHM_TMON2_STATUS)/sizeof(ixTHM_TMON2_STATUS[0]), 0, 0 },
+	{ "ixLCAC_MC0_CNTL", REG_SMC, 0xc0400130, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0xc0400134, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0xc0400138, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC1_CNTL", REG_SMC, 0xc040013c, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0xc0400140, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0xc0400144, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC2_CNTL", REG_SMC, 0xc0400148, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0xc040014c, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0xc0400150, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC3_CNTL", REG_SMC, 0xc0400154, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0xc0400158, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0xc040015c, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_CPL_CNTL", REG_SMC, 0xc0400160, &ixLCAC_CPL_CNTL[0], sizeof(ixLCAC_CPL_CNTL)/sizeof(ixLCAC_CPL_CNTL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_SEL", REG_SMC, 0xc0400164, &ixLCAC_CPL_OVR_SEL[0], sizeof(ixLCAC_CPL_OVR_SEL)/sizeof(ixLCAC_CPL_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_VAL", REG_SMC, 0xc0400168, &ixLCAC_CPL_OVR_VAL[0], sizeof(ixLCAC_CPL_OVR_VAL)/sizeof(ixLCAC_CPL_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC4_CNTL", REG_SMC, 0xc0400d60, &ixLCAC_MC4_CNTL[0], sizeof(ixLCAC_MC4_CNTL)/sizeof(ixLCAC_MC4_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC4_OVR_SEL", REG_SMC, 0xc0400d64, &ixLCAC_MC4_OVR_SEL[0], sizeof(ixLCAC_MC4_OVR_SEL)/sizeof(ixLCAC_MC4_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC4_OVR_VAL", REG_SMC, 0xc0400d68, &ixLCAC_MC4_OVR_VAL[0], sizeof(ixLCAC_MC4_OVR_VAL)/sizeof(ixLCAC_MC4_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC5_CNTL", REG_SMC, 0xc0400d6c, &ixLCAC_MC5_CNTL[0], sizeof(ixLCAC_MC5_CNTL)/sizeof(ixLCAC_MC5_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC5_OVR_SEL", REG_SMC, 0xc0400d70, &ixLCAC_MC5_OVR_SEL[0], sizeof(ixLCAC_MC5_OVR_SEL)/sizeof(ixLCAC_MC5_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC5_OVR_VAL", REG_SMC, 0xc0400d74, &ixLCAC_MC5_OVR_VAL[0], sizeof(ixLCAC_MC5_OVR_VAL)/sizeof(ixLCAC_MC5_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC6_CNTL", REG_SMC, 0xc0400d78, &ixLCAC_MC6_CNTL[0], sizeof(ixLCAC_MC6_CNTL)/sizeof(ixLCAC_MC6_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC6_OVR_SEL", REG_SMC, 0xc0400d7c, &ixLCAC_MC6_OVR_SEL[0], sizeof(ixLCAC_MC6_OVR_SEL)/sizeof(ixLCAC_MC6_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC6_OVR_VAL", REG_SMC, 0xc0400d80, &ixLCAC_MC6_OVR_VAL[0], sizeof(ixLCAC_MC6_OVR_VAL)/sizeof(ixLCAC_MC6_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC7_CNTL", REG_SMC, 0xc0400d84, &ixLCAC_MC7_CNTL[0], sizeof(ixLCAC_MC7_CNTL)/sizeof(ixLCAC_MC7_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC7_OVR_SEL", REG_SMC, 0xc0400d88, &ixLCAC_MC7_OVR_SEL[0], sizeof(ixLCAC_MC7_OVR_SEL)/sizeof(ixLCAC_MC7_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC7_OVR_VAL", REG_SMC, 0xc0400d8c, &ixLCAC_MC7_OVR_VAL[0], sizeof(ixLCAC_MC7_OVR_VAL)/sizeof(ixLCAC_MC7_OVR_VAL[0]), 0, 0 },
+	{ "ixGCK_MCLK_FUSES", REG_SMC, 0xc0500008, &ixGCK_MCLK_FUSES[0], sizeof(ixGCK_MCLK_FUSES)/sizeof(ixGCK_MCLK_FUSES[0]), 0, 0 },
+	{ "ixCG_DCLK_CNTL", REG_SMC, 0xc050009c, &ixCG_DCLK_CNTL[0], sizeof(ixCG_DCLK_CNTL)/sizeof(ixCG_DCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_DCLK_STATUS", REG_SMC, 0xc05000a0, &ixCG_DCLK_STATUS[0], sizeof(ixCG_DCLK_STATUS)/sizeof(ixCG_DCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_VCLK_CNTL", REG_SMC, 0xc05000a4, &ixCG_VCLK_CNTL[0], sizeof(ixCG_VCLK_CNTL)/sizeof(ixCG_VCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_VCLK_STATUS", REG_SMC, 0xc05000a8, &ixCG_VCLK_STATUS[0], sizeof(ixCG_VCLK_STATUS)/sizeof(ixCG_VCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ECLK_CNTL", REG_SMC, 0xc05000ac, &ixCG_ECLK_CNTL[0], sizeof(ixCG_ECLK_CNTL)/sizeof(ixCG_ECLK_CNTL[0]), 0, 0 },
+	{ "ixCG_ECLK_STATUS", REG_SMC, 0xc05000b0, &ixCG_ECLK_STATUS[0], sizeof(ixCG_ECLK_STATUS)/sizeof(ixCG_ECLK_STATUS[0]), 0, 0 },
+	{ "ixCG_ACLK_CNTL", REG_SMC, 0xc05000dc, &ixCG_ACLK_CNTL[0], sizeof(ixCG_ACLK_CNTL)/sizeof(ixCG_ACLK_CNTL[0]), 0, 0 },
+	{ "ixGCK_DFS_BYPASS_CNTL", REG_SMC, 0xc0500118, &ixGCK_DFS_BYPASS_CNTL[0], sizeof(ixGCK_DFS_BYPASS_CNTL)/sizeof(ixGCK_DFS_BYPASS_CNTL[0]), 0, 0 },
+	{ "ixCG_MCLK_CNTL", REG_SMC, 0xc0500120, &ixCG_MCLK_CNTL[0], sizeof(ixCG_MCLK_CNTL)/sizeof(ixCG_MCLK_CNTL[0]), 0, 0 },
+	{ "ixCG_MCLK_STATUS", REG_SMC, 0xc0500124, &ixCG_MCLK_STATUS[0], sizeof(ixCG_MCLK_STATUS)/sizeof(ixCG_MCLK_STATUS[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL", REG_SMC, 0xc0500140, &ixCG_SPLL_FUNC_CNTL[0], sizeof(ixCG_SPLL_FUNC_CNTL)/sizeof(ixCG_SPLL_FUNC_CNTL[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_2", REG_SMC, 0xc0500144, &ixCG_SPLL_FUNC_CNTL_2[0], sizeof(ixCG_SPLL_FUNC_CNTL_2)/sizeof(ixCG_SPLL_FUNC_CNTL_2[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_3", REG_SMC, 0xc0500148, &ixCG_SPLL_FUNC_CNTL_3[0], sizeof(ixCG_SPLL_FUNC_CNTL_3)/sizeof(ixCG_SPLL_FUNC_CNTL_3[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_4", REG_SMC, 0xc050014c, &ixCG_SPLL_FUNC_CNTL_4[0], sizeof(ixCG_SPLL_FUNC_CNTL_4)/sizeof(ixCG_SPLL_FUNC_CNTL_4[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_5", REG_SMC, 0xc0500150, &ixCG_SPLL_FUNC_CNTL_5[0], sizeof(ixCG_SPLL_FUNC_CNTL_5)/sizeof(ixCG_SPLL_FUNC_CNTL_5[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_6", REG_SMC, 0xc0500154, &ixCG_SPLL_FUNC_CNTL_6[0], sizeof(ixCG_SPLL_FUNC_CNTL_6)/sizeof(ixCG_SPLL_FUNC_CNTL_6[0]), 0, 0 },
+	{ "ixCG_SPLL_FUNC_CNTL_7", REG_SMC, 0xc0500158, &ixCG_SPLL_FUNC_CNTL_7[0], sizeof(ixCG_SPLL_FUNC_CNTL_7)/sizeof(ixCG_SPLL_FUNC_CNTL_7[0]), 0, 0 },
+	{ "ixSPLL_CNTL_MODE", REG_SMC, 0xc0500160, &ixSPLL_CNTL_MODE[0], sizeof(ixSPLL_CNTL_MODE)/sizeof(ixSPLL_CNTL_MODE[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM", REG_SMC, 0xc0500164, &ixCG_SPLL_SPREAD_SPECTRUM[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM[0]), 0, 0 },
+	{ "ixCG_SPLL_SPREAD_SPECTRUM_2", REG_SMC, 0xc0500168, &ixCG_SPLL_SPREAD_SPECTRUM_2[0], sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2)/sizeof(ixCG_SPLL_SPREAD_SPECTRUM_2[0]), 0, 0 },
+	{ "ixMPLL_BYPASSCLK_SEL", REG_SMC, 0xc050019c, &ixMPLL_BYPASSCLK_SEL[0], sizeof(ixMPLL_BYPASSCLK_SEL)/sizeof(ixMPLL_BYPASSCLK_SEL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL", REG_SMC, 0xc05001a0, &ixCG_CLKPIN_CNTL[0], sizeof(ixCG_CLKPIN_CNTL)/sizeof(ixCG_CLKPIN_CNTL[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_2", REG_SMC, 0xc05001a4, &ixCG_CLKPIN_CNTL_2[0], sizeof(ixCG_CLKPIN_CNTL_2)/sizeof(ixCG_CLKPIN_CNTL_2[0]), 0, 0 },
+	{ "ixTHM_CLK_CNTL", REG_SMC, 0xc05001a8, &ixTHM_CLK_CNTL[0], sizeof(ixTHM_CLK_CNTL)/sizeof(ixTHM_CLK_CNTL[0]), 0, 0 },
+	{ "ixMISC_CLK_CTRL", REG_SMC, 0xc05001ac, &ixMISC_CLK_CTRL[0], sizeof(ixMISC_CLK_CTRL)/sizeof(ixMISC_CLK_CTRL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL", REG_SMC, 0xc05001c0, &ixGCK_PLL_TEST_CNTL[0], sizeof(ixGCK_PLL_TEST_CNTL)/sizeof(ixGCK_PLL_TEST_CNTL[0]), 0, 0 },
+	{ "ixGCK_PLL_TEST_CNTL_2", REG_SMC, 0xc05001c4, &ixGCK_PLL_TEST_CNTL_2[0], sizeof(ixGCK_PLL_TEST_CNTL_2)/sizeof(ixGCK_PLL_TEST_CNTL_2[0]), 0, 0 },
+	{ "ixGCK_ADFS_CLK_BYPASS_CNTL1", REG_SMC, 0xc05001c8, &ixGCK_ADFS_CLK_BYPASS_CNTL1[0], sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1)/sizeof(ixGCK_ADFS_CLK_BYPASS_CNTL1[0]), 0, 0 },
+	{ "ixCG_CLKPIN_CNTL_DC", REG_SMC, 0xc0500204, &ixCG_CLKPIN_CNTL_DC[0], sizeof(ixCG_CLKPIN_CNTL_DC)/sizeof(ixCG_CLKPIN_CNTL_DC[0]), 0, 0 },
+	{ "ixROM_CNTL", REG_SMC, 0xc0600000, &ixROM_CNTL[0], sizeof(ixROM_CNTL)/sizeof(ixROM_CNTL[0]), 0, 0 },
+	{ "ixPAGE_MIRROR_CNTL", REG_SMC, 0xc0600004, &ixPAGE_MIRROR_CNTL[0], sizeof(ixPAGE_MIRROR_CNTL)/sizeof(ixPAGE_MIRROR_CNTL[0]), 0, 0 },
+	{ "ixROM_STATUS", REG_SMC, 0xc0600008, &ixROM_STATUS[0], sizeof(ixROM_STATUS)/sizeof(ixROM_STATUS[0]), 0, 0 },
+	{ "ixCGTT_ROM_CLK_CTRL0", REG_SMC, 0xc060000c, &ixCGTT_ROM_CLK_CTRL0[0], sizeof(ixCGTT_ROM_CLK_CTRL0)/sizeof(ixCGTT_ROM_CLK_CTRL0[0]), 0, 0 },
+	{ "ixROM_INDEX", REG_SMC, 0xc0600010, &ixROM_INDEX[0], sizeof(ixROM_INDEX)/sizeof(ixROM_INDEX[0]), 0, 0 },
+	{ "ixROM_DATA", REG_SMC, 0xc0600014, &ixROM_DATA[0], sizeof(ixROM_DATA)/sizeof(ixROM_DATA[0]), 0, 0 },
+	{ "ixROM_START", REG_SMC, 0xc0600018, &ixROM_START[0], sizeof(ixROM_START)/sizeof(ixROM_START[0]), 0, 0 },
+	{ "ixROM_SW_CNTL", REG_SMC, 0xc060001c, &ixROM_SW_CNTL[0], sizeof(ixROM_SW_CNTL)/sizeof(ixROM_SW_CNTL[0]), 0, 0 },
+	{ "ixROM_SW_STATUS", REG_SMC, 0xc0600020, &ixROM_SW_STATUS[0], sizeof(ixROM_SW_STATUS)/sizeof(ixROM_SW_STATUS[0]), 0, 0 },
+	{ "ixROM_SW_COMMAND", REG_SMC, 0xc0600024, &ixROM_SW_COMMAND[0], sizeof(ixROM_SW_COMMAND)/sizeof(ixROM_SW_COMMAND[0]), 0, 0 },
+	{ "ixROM_SW_DATA_1", REG_SMC, 0xc0600028, &ixROM_SW_DATA_1[0], sizeof(ixROM_SW_DATA_1)/sizeof(ixROM_SW_DATA_1[0]), 0, 0 },
+	{ "ixROM_SW_DATA_2", REG_SMC, 0xc060002c, &ixROM_SW_DATA_2[0], sizeof(ixROM_SW_DATA_2)/sizeof(ixROM_SW_DATA_2[0]), 0, 0 },
+	{ "ixROM_SW_DATA_3", REG_SMC, 0xc0600030, &ixROM_SW_DATA_3[0], sizeof(ixROM_SW_DATA_3)/sizeof(ixROM_SW_DATA_3[0]), 0, 0 },
+	{ "ixROM_SW_DATA_4", REG_SMC, 0xc0600034, &ixROM_SW_DATA_4[0], sizeof(ixROM_SW_DATA_4)/sizeof(ixROM_SW_DATA_4[0]), 0, 0 },
+	{ "ixROM_SW_DATA_5", REG_SMC, 0xc0600038, &ixROM_SW_DATA_5[0], sizeof(ixROM_SW_DATA_5)/sizeof(ixROM_SW_DATA_5[0]), 0, 0 },
+	{ "ixROM_SW_DATA_6", REG_SMC, 0xc060003c, &ixROM_SW_DATA_6[0], sizeof(ixROM_SW_DATA_6)/sizeof(ixROM_SW_DATA_6[0]), 0, 0 },
+	{ "ixROM_SW_DATA_7", REG_SMC, 0xc0600040, &ixROM_SW_DATA_7[0], sizeof(ixROM_SW_DATA_7)/sizeof(ixROM_SW_DATA_7[0]), 0, 0 },
+	{ "ixROM_SW_DATA_8", REG_SMC, 0xc0600044, &ixROM_SW_DATA_8[0], sizeof(ixROM_SW_DATA_8)/sizeof(ixROM_SW_DATA_8[0]), 0, 0 },
+	{ "ixROM_SW_DATA_9", REG_SMC, 0xc0600048, &ixROM_SW_DATA_9[0], sizeof(ixROM_SW_DATA_9)/sizeof(ixROM_SW_DATA_9[0]), 0, 0 },
+	{ "ixROM_SW_DATA_10", REG_SMC, 0xc060004c, &ixROM_SW_DATA_10[0], sizeof(ixROM_SW_DATA_10)/sizeof(ixROM_SW_DATA_10[0]), 0, 0 },
+	{ "ixROM_SW_DATA_11", REG_SMC, 0xc0600050, &ixROM_SW_DATA_11[0], sizeof(ixROM_SW_DATA_11)/sizeof(ixROM_SW_DATA_11[0]), 0, 0 },
+	{ "ixROM_SW_DATA_12", REG_SMC, 0xc0600054, &ixROM_SW_DATA_12[0], sizeof(ixROM_SW_DATA_12)/sizeof(ixROM_SW_DATA_12[0]), 0, 0 },
+	{ "ixROM_SW_DATA_13", REG_SMC, 0xc0600058, &ixROM_SW_DATA_13[0], sizeof(ixROM_SW_DATA_13)/sizeof(ixROM_SW_DATA_13[0]), 0, 0 },
+	{ "ixROM_SW_DATA_14", REG_SMC, 0xc060005c, &ixROM_SW_DATA_14[0], sizeof(ixROM_SW_DATA_14)/sizeof(ixROM_SW_DATA_14[0]), 0, 0 },
+	{ "ixROM_SW_DATA_15", REG_SMC, 0xc0600060, &ixROM_SW_DATA_15[0], sizeof(ixROM_SW_DATA_15)/sizeof(ixROM_SW_DATA_15[0]), 0, 0 },
+	{ "ixROM_SW_DATA_16", REG_SMC, 0xc0600064, &ixROM_SW_DATA_16[0], sizeof(ixROM_SW_DATA_16)/sizeof(ixROM_SW_DATA_16[0]), 0, 0 },
+	{ "ixROM_SW_DATA_17", REG_SMC, 0xc0600068, &ixROM_SW_DATA_17[0], sizeof(ixROM_SW_DATA_17)/sizeof(ixROM_SW_DATA_17[0]), 0, 0 },
+	{ "ixROM_SW_DATA_18", REG_SMC, 0xc060006c, &ixROM_SW_DATA_18[0], sizeof(ixROM_SW_DATA_18)/sizeof(ixROM_SW_DATA_18[0]), 0, 0 },
+	{ "ixROM_SW_DATA_19", REG_SMC, 0xc0600070, &ixROM_SW_DATA_19[0], sizeof(ixROM_SW_DATA_19)/sizeof(ixROM_SW_DATA_19[0]), 0, 0 },
+	{ "ixROM_SW_DATA_20", REG_SMC, 0xc0600074, &ixROM_SW_DATA_20[0], sizeof(ixROM_SW_DATA_20)/sizeof(ixROM_SW_DATA_20[0]), 0, 0 },
+	{ "ixROM_SW_DATA_21", REG_SMC, 0xc0600078, &ixROM_SW_DATA_21[0], sizeof(ixROM_SW_DATA_21)/sizeof(ixROM_SW_DATA_21[0]), 0, 0 },
+	{ "ixROM_SW_DATA_22", REG_SMC, 0xc060007c, &ixROM_SW_DATA_22[0], sizeof(ixROM_SW_DATA_22)/sizeof(ixROM_SW_DATA_22[0]), 0, 0 },
+	{ "ixROM_SW_DATA_23", REG_SMC, 0xc0600080, &ixROM_SW_DATA_23[0], sizeof(ixROM_SW_DATA_23)/sizeof(ixROM_SW_DATA_23[0]), 0, 0 },
+	{ "ixROM_SW_DATA_24", REG_SMC, 0xc0600084, &ixROM_SW_DATA_24[0], sizeof(ixROM_SW_DATA_24)/sizeof(ixROM_SW_DATA_24[0]), 0, 0 },
+	{ "ixROM_SW_DATA_25", REG_SMC, 0xc0600088, &ixROM_SW_DATA_25[0], sizeof(ixROM_SW_DATA_25)/sizeof(ixROM_SW_DATA_25[0]), 0, 0 },
+	{ "ixROM_SW_DATA_26", REG_SMC, 0xc060008c, &ixROM_SW_DATA_26[0], sizeof(ixROM_SW_DATA_26)/sizeof(ixROM_SW_DATA_26[0]), 0, 0 },
+	{ "ixROM_SW_DATA_27", REG_SMC, 0xc0600090, &ixROM_SW_DATA_27[0], sizeof(ixROM_SW_DATA_27)/sizeof(ixROM_SW_DATA_27[0]), 0, 0 },
+	{ "ixROM_SW_DATA_28", REG_SMC, 0xc0600094, &ixROM_SW_DATA_28[0], sizeof(ixROM_SW_DATA_28)/sizeof(ixROM_SW_DATA_28[0]), 0, 0 },
+	{ "ixROM_SW_DATA_29", REG_SMC, 0xc0600098, &ixROM_SW_DATA_29[0], sizeof(ixROM_SW_DATA_29)/sizeof(ixROM_SW_DATA_29[0]), 0, 0 },
+	{ "ixROM_SW_DATA_30", REG_SMC, 0xc060009c, &ixROM_SW_DATA_30[0], sizeof(ixROM_SW_DATA_30)/sizeof(ixROM_SW_DATA_30[0]), 0, 0 },
+	{ "ixROM_SW_DATA_31", REG_SMC, 0xc06000a0, &ixROM_SW_DATA_31[0], sizeof(ixROM_SW_DATA_31)/sizeof(ixROM_SW_DATA_31[0]), 0, 0 },
+	{ "ixROM_SW_DATA_32", REG_SMC, 0xc06000a4, &ixROM_SW_DATA_32[0], sizeof(ixROM_SW_DATA_32)/sizeof(ixROM_SW_DATA_32[0]), 0, 0 },
+	{ "ixROM_SW_DATA_33", REG_SMC, 0xc06000a8, &ixROM_SW_DATA_33[0], sizeof(ixROM_SW_DATA_33)/sizeof(ixROM_SW_DATA_33[0]), 0, 0 },
+	{ "ixROM_SW_DATA_34", REG_SMC, 0xc06000ac, &ixROM_SW_DATA_34[0], sizeof(ixROM_SW_DATA_34)/sizeof(ixROM_SW_DATA_34[0]), 0, 0 },
+	{ "ixROM_SW_DATA_35", REG_SMC, 0xc06000b0, &ixROM_SW_DATA_35[0], sizeof(ixROM_SW_DATA_35)/sizeof(ixROM_SW_DATA_35[0]), 0, 0 },
+	{ "ixROM_SW_DATA_36", REG_SMC, 0xc06000b4, &ixROM_SW_DATA_36[0], sizeof(ixROM_SW_DATA_36)/sizeof(ixROM_SW_DATA_36[0]), 0, 0 },
+	{ "ixROM_SW_DATA_37", REG_SMC, 0xc06000b8, &ixROM_SW_DATA_37[0], sizeof(ixROM_SW_DATA_37)/sizeof(ixROM_SW_DATA_37[0]), 0, 0 },
+	{ "ixROM_SW_DATA_38", REG_SMC, 0xc06000bc, &ixROM_SW_DATA_38[0], sizeof(ixROM_SW_DATA_38)/sizeof(ixROM_SW_DATA_38[0]), 0, 0 },
+	{ "ixROM_SW_DATA_39", REG_SMC, 0xc06000c0, &ixROM_SW_DATA_39[0], sizeof(ixROM_SW_DATA_39)/sizeof(ixROM_SW_DATA_39[0]), 0, 0 },
+	{ "ixROM_SW_DATA_40", REG_SMC, 0xc06000c4, &ixROM_SW_DATA_40[0], sizeof(ixROM_SW_DATA_40)/sizeof(ixROM_SW_DATA_40[0]), 0, 0 },
+	{ "ixROM_SW_DATA_41", REG_SMC, 0xc06000c8, &ixROM_SW_DATA_41[0], sizeof(ixROM_SW_DATA_41)/sizeof(ixROM_SW_DATA_41[0]), 0, 0 },
+	{ "ixROM_SW_DATA_42", REG_SMC, 0xc06000cc, &ixROM_SW_DATA_42[0], sizeof(ixROM_SW_DATA_42)/sizeof(ixROM_SW_DATA_42[0]), 0, 0 },
+	{ "ixROM_SW_DATA_43", REG_SMC, 0xc06000d0, &ixROM_SW_DATA_43[0], sizeof(ixROM_SW_DATA_43)/sizeof(ixROM_SW_DATA_43[0]), 0, 0 },
+	{ "ixROM_SW_DATA_44", REG_SMC, 0xc06000d4, &ixROM_SW_DATA_44[0], sizeof(ixROM_SW_DATA_44)/sizeof(ixROM_SW_DATA_44[0]), 0, 0 },
+	{ "ixROM_SW_DATA_45", REG_SMC, 0xc06000d8, &ixROM_SW_DATA_45[0], sizeof(ixROM_SW_DATA_45)/sizeof(ixROM_SW_DATA_45[0]), 0, 0 },
+	{ "ixROM_SW_DATA_46", REG_SMC, 0xc06000dc, &ixROM_SW_DATA_46[0], sizeof(ixROM_SW_DATA_46)/sizeof(ixROM_SW_DATA_46[0]), 0, 0 },
+	{ "ixROM_SW_DATA_47", REG_SMC, 0xc06000e0, &ixROM_SW_DATA_47[0], sizeof(ixROM_SW_DATA_47)/sizeof(ixROM_SW_DATA_47[0]), 0, 0 },
+	{ "ixROM_SW_DATA_48", REG_SMC, 0xc06000e4, &ixROM_SW_DATA_48[0], sizeof(ixROM_SW_DATA_48)/sizeof(ixROM_SW_DATA_48[0]), 0, 0 },
+	{ "ixROM_SW_DATA_49", REG_SMC, 0xc06000e8, &ixROM_SW_DATA_49[0], sizeof(ixROM_SW_DATA_49)/sizeof(ixROM_SW_DATA_49[0]), 0, 0 },
+	{ "ixROM_SW_DATA_50", REG_SMC, 0xc06000ec, &ixROM_SW_DATA_50[0], sizeof(ixROM_SW_DATA_50)/sizeof(ixROM_SW_DATA_50[0]), 0, 0 },
+	{ "ixROM_SW_DATA_51", REG_SMC, 0xc06000f0, &ixROM_SW_DATA_51[0], sizeof(ixROM_SW_DATA_51)/sizeof(ixROM_SW_DATA_51[0]), 0, 0 },
+	{ "ixROM_SW_DATA_52", REG_SMC, 0xc06000f4, &ixROM_SW_DATA_52[0], sizeof(ixROM_SW_DATA_52)/sizeof(ixROM_SW_DATA_52[0]), 0, 0 },
+	{ "ixROM_SW_DATA_53", REG_SMC, 0xc06000f8, &ixROM_SW_DATA_53[0], sizeof(ixROM_SW_DATA_53)/sizeof(ixROM_SW_DATA_53[0]), 0, 0 },
+	{ "ixROM_SW_DATA_54", REG_SMC, 0xc06000fc, &ixROM_SW_DATA_54[0], sizeof(ixROM_SW_DATA_54)/sizeof(ixROM_SW_DATA_54[0]), 0, 0 },
+	{ "ixROM_SW_DATA_55", REG_SMC, 0xc0600100, &ixROM_SW_DATA_55[0], sizeof(ixROM_SW_DATA_55)/sizeof(ixROM_SW_DATA_55[0]), 0, 0 },
+	{ "ixROM_SW_DATA_56", REG_SMC, 0xc0600104, &ixROM_SW_DATA_56[0], sizeof(ixROM_SW_DATA_56)/sizeof(ixROM_SW_DATA_56[0]), 0, 0 },
+	{ "ixROM_SW_DATA_57", REG_SMC, 0xc0600108, &ixROM_SW_DATA_57[0], sizeof(ixROM_SW_DATA_57)/sizeof(ixROM_SW_DATA_57[0]), 0, 0 },
+	{ "ixROM_SW_DATA_58", REG_SMC, 0xc060010c, &ixROM_SW_DATA_58[0], sizeof(ixROM_SW_DATA_58)/sizeof(ixROM_SW_DATA_58[0]), 0, 0 },
+	{ "ixROM_SW_DATA_59", REG_SMC, 0xc0600110, &ixROM_SW_DATA_59[0], sizeof(ixROM_SW_DATA_59)/sizeof(ixROM_SW_DATA_59[0]), 0, 0 },
+	{ "ixROM_SW_DATA_60", REG_SMC, 0xc0600114, &ixROM_SW_DATA_60[0], sizeof(ixROM_SW_DATA_60)/sizeof(ixROM_SW_DATA_60[0]), 0, 0 },
+	{ "ixROM_SW_DATA_61", REG_SMC, 0xc0600118, &ixROM_SW_DATA_61[0], sizeof(ixROM_SW_DATA_61)/sizeof(ixROM_SW_DATA_61[0]), 0, 0 },
+	{ "ixROM_SW_DATA_62", REG_SMC, 0xc060011c, &ixROM_SW_DATA_62[0], sizeof(ixROM_SW_DATA_62)/sizeof(ixROM_SW_DATA_62[0]), 0, 0 },
+	{ "ixROM_SW_DATA_63", REG_SMC, 0xc0600120, &ixROM_SW_DATA_63[0], sizeof(ixROM_SW_DATA_63)/sizeof(ixROM_SW_DATA_63[0]), 0, 0 },
+	{ "ixROM_SW_DATA_64", REG_SMC, 0xc0600124, &ixROM_SW_DATA_64[0], sizeof(ixROM_SW_DATA_64)/sizeof(ixROM_SW_DATA_64[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU7", REG_SMC, 0xc1, &ixGC_CAC_ACC_CU7[0], sizeof(ixGC_CAC_ACC_CU7)/sizeof(ixGC_CAC_ACC_CU7[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU8", REG_SMC, 0xc2, &ixGC_CAC_ACC_CU8[0], sizeof(ixGC_CAC_ACC_CU8)/sizeof(ixGC_CAC_ACC_CU8[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_ENA", REG_SMC, 0xc2100024, &ixCG_THERMAL_INT_ENA[0], sizeof(ixCG_THERMAL_INT_ENA)/sizeof(ixCG_THERMAL_INT_ENA[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_CTRL", REG_SMC, 0xc2100028, &ixCG_THERMAL_INT_CTRL[0], sizeof(ixCG_THERMAL_INT_CTRL)/sizeof(ixCG_THERMAL_INT_CTRL[0]), 0, 0 },
+	{ "ixCG_THERMAL_INT_STATUS", REG_SMC, 0xc210002c, &ixCG_THERMAL_INT_STATUS[0], sizeof(ixCG_THERMAL_INT_STATUS)/sizeof(ixCG_THERMAL_INT_STATUS[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU9", REG_SMC, 0xc3, &ixGC_CAC_ACC_CU9[0], sizeof(ixGC_CAC_ACC_CU9)/sizeof(ixGC_CAC_ACC_CU9[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU10", REG_SMC, 0xc4, &ixGC_CAC_ACC_CU10[0], sizeof(ixGC_CAC_ACC_CU10)/sizeof(ixGC_CAC_ACC_CU10[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU11", REG_SMC, 0xc5, &ixGC_CAC_ACC_CU11[0], sizeof(ixGC_CAC_ACC_CU11)/sizeof(ixGC_CAC_ACC_CU11[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU12", REG_SMC, 0xc6, &ixGC_CAC_ACC_CU12[0], sizeof(ixGC_CAC_ACC_CU12)/sizeof(ixGC_CAC_ACC_CU12[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU13", REG_SMC, 0xc7, &ixGC_CAC_ACC_CU13[0], sizeof(ixGC_CAC_ACC_CU13)/sizeof(ixGC_CAC_ACC_CU13[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU14", REG_SMC, 0xc8, &ixGC_CAC_ACC_CU14[0], sizeof(ixGC_CAC_ACC_CU14)/sizeof(ixGC_CAC_ACC_CU14[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU15", REG_SMC, 0xc9, &ixGC_CAC_ACC_CU15[0], sizeof(ixGC_CAC_ACC_CU15)/sizeof(ixGC_CAC_ACC_CU15[0]), 0, 0 },
+	{ "ixSMU_MAIN_PLL_OP_FREQ", REG_SMC, 0xe0003020, &ixSMU_MAIN_PLL_OP_FREQ[0], sizeof(ixSMU_MAIN_PLL_OP_FREQ)/sizeof(ixSMU_MAIN_PLL_OP_FREQ[0]), 0, 0 },
+	{ "ixSMU_STATUS", REG_SMC, 0xe0003088, &ixSMU_STATUS[0], sizeof(ixSMU_STATUS)/sizeof(ixSMU_STATUS[0]), 0, 0 },
+	{ "ixSMU_FIRMWARE", REG_SMC, 0xe00030a4, &ixSMU_FIRMWARE[0], sizeof(ixSMU_FIRMWARE)/sizeof(ixSMU_FIRMWARE[0]), 0, 0 },
+	{ "ixSMU_INPUT_DATA", REG_SMC, 0xe00030b8, &ixSMU_INPUT_DATA[0], sizeof(ixSMU_INPUT_DATA)/sizeof(ixSMU_INPUT_DATA[0]), 0, 0 },
+	{ "ixGC_CAC_OVRD_CU", REG_SMC, 0xe7, &ixGC_CAC_OVRD_CU[0], sizeof(ixGC_CAC_OVRD_CU)/sizeof(ixGC_CAC_OVRD_CU[0]), 0, 0 },
diff --git a/src/lib/ip/smu80.c b/src/lib/ip/smu80.c
new file mode 100644
index 0000000..d1cd966
--- /dev/null
+++ b/src/lib/ip/smu80.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "smu80_bits.i"
+
+static const struct umr_reg smu80_registers[] = {
+#include "smu80_regs.i"
+};
+
+static int grant(struct umr_asic *asic)
+{
+	(void)asic;
+	return 0;
+}
+
+static int deny(struct umr_asic *asic)
+{
+	(void)asic;
+	return -1;
+}
+
+struct umr_ip_block *umr_create_smu80(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "smu80";
+	ip->no_regs = sizeof(smu80_registers)/sizeof(smu80_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(smu80_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	ip->grant = (options->risky >= 2) ? grant : deny;
+	memcpy(ip->regs, smu80_registers, sizeof(smu80_registers));
+	return ip;
+}
diff --git a/src/lib/ip/smu80_bits.i b/src/lib/ip/smu80_bits.i
new file mode 100644
index 0000000..ed118e3
--- /dev/null
+++ b/src/lib/ip/smu80_bits.i
@@ -0,0 +1,2674 @@
+static struct umr_bitfield mmPWRHW_SMC_IND_INDEX[] = {
+	 { "SMC_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_0[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmPWRHW_SMC_IND_DATA[] = {
+	 { "SMC_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_0[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_1[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_1[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_2[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_2[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_3[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_3[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_4[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_4[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_5[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_5[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_6[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_6[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_7[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_7[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_8[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_8[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_9[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_9[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_10[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_10[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_11[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_11[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_12[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_12[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_13[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_13[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_14[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_14[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_INDEX_15[] = {
+	 { "MP0PUB_IND_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0PUB_IND_DATA_15[] = {
+	 { "MP0PUB_IND_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_IND_ACCESS_CNTL[] = {
+	 { "AUTO_INCREMENT_IND_0", 0, 0, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_1", 1, 1, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_2", 2, 2, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_3", 3, 3, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_4", 4, 4, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_5", 5, 5, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_6", 6, 6, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_7", 7, 7, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_8", 8, 8, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_9", 9, 9, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_10", 10, 10, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_11", 11, 11, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_12", 12, 12, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_13", 13, 13, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_14", 14, 14, &umr_bitfield_default },
+	 { "AUTO_INCREMENT_IND_15", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_MSP_MESSAGE_0[] = {
+	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_MSP_MESSAGE_1[] = {
+	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_MSP_MESSAGE_2[] = {
+	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_MSP_MESSAGE_3[] = {
+	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_MSP_MESSAGE_4[] = {
+	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_MSP_MESSAGE_5[] = {
+	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_MSP_MESSAGE_6[] = {
+	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_MSP_MESSAGE_7[] = {
+	 { "MP0_MSP_MSG", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSAM_IH_EXT_ERR_INTR[] = {
+	 { "UVD", 0, 0, &umr_bitfield_default },
+	 { "VCE", 1, 1, &umr_bitfield_default },
+	 { "ISP", 2, 2, &umr_bitfield_default },
+	 { "RESERVED", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSAM_IH_EXT_ERR_INTR_STATUS[] = {
+	 { "UVD", 0, 0, &umr_bitfield_default },
+	 { "VCE", 1, 1, &umr_bitfield_default },
+	 { "ISP", 2, 2, &umr_bitfield_default },
+	 { "RESERVED", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER0_CTRL0[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DEC", 16, 16, &umr_bitfield_default },
+	 { "PULSE_COUNT_MODE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER0_CTRL1[] = {
+	 { "PWM_OUTPUT_EN", 0, 0, &umr_bitfield_default },
+	 { "TIME_SLICE_MODE_EN", 8, 8, &umr_bitfield_default },
+	 { "TIMER_SATURATION_EN", 16, 16, &umr_bitfield_default },
+	 { "RESERVED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER0_CMP_AUTOINC[] = {
+	 { "AUTOINC", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER0_INTEN[] = {
+	 { "INTEN", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER0_OCMP_0_0[] = {
+	 { "OCMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER0_OCMP_0_1[] = {
+	 { "OCMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER0_CNT[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER1_CTRL0[] = {
+	 { "START", 0, 0, &umr_bitfield_default },
+	 { "CLEAR", 8, 8, &umr_bitfield_default },
+	 { "DEC", 16, 16, &umr_bitfield_default },
+	 { "PULSE_COUNT_MODE", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER1_CTRL1[] = {
+	 { "PWM_OUTPUT_EN", 0, 0, &umr_bitfield_default },
+	 { "TIME_SLICE_MODE_EN", 8, 8, &umr_bitfield_default },
+	 { "TIMER_SATURATION_EN", 16, 16, &umr_bitfield_default },
+	 { "RESERVED", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER1_CMP_AUTOINC[] = {
+	 { "AUTOINC", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER1_INTEN[] = {
+	 { "INTEN", 0, 3, &umr_bitfield_default },
+	 { "RESERVED", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER1_OCMP_0_0[] = {
+	 { "OCMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER1_OCMP_0_1[] = {
+	 { "OCMP", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP0_DISP_TIMER1_CNT[] = {
+	 { "COUNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_0[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_1[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_2[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_3[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_4[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_5[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_6[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_7[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_8[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_9[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_10[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_11[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_12[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_13[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_14[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_MSG_15[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_0[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_1[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_2[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_3[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_4[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_5[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_6[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_7[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_8[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_9[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_10[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_11[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_12[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_13[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_14[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_RESP_15[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_0[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_1[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_2[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_3[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_4[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_5[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_6[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_7[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_8[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_9[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_10[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_11[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_12[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_13[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_14[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_SRBM2P_ARG_15[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_ACP2MP_RESP[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_DC2MP_RESP[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_UVD2MP_RESP[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_VCE2MP_RESP[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_MP1_RLC2MP_RESP[] = {
+	 { "CONTENT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmMP_FPS_CNT[] = {
+	 { "FPS_CNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_DISP0_TIMER_INT_CONTROL[] = {
+	 { "INT_STAT", 0, 0, &umr_bitfield_default },
+	 { "INT_UNMASK", 1, 1, &umr_bitfield_default },
+	 { "INT_TYPE", 2, 2, &umr_bitfield_default },
+	 { "INT_ACK", 3, 3, &umr_bitfield_default },
+	 { "MASK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_DISP1_TIMER_INT_CONTROL[] = {
+	 { "INT_STAT", 0, 0, &umr_bitfield_default },
+	 { "INT_UNMASK", 1, 1, &umr_bitfield_default },
+	 { "INT_TYPE", 2, 2, &umr_bitfield_default },
+	 { "INT_ACK", 3, 3, &umr_bitfield_default },
+	 { "MASK", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmSMU_SRBM_CONFIG[] = {
+	 { "MSTR_CREDITS", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_0[] = {
+	 { "WEIGHT_CU_SIG0", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG1", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_CAC_LKG_AGGR_LOWER[] = {
+	 { "LKG_AGGR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmGC_CAC_LKG_AGGR_UPPER[] = {
+	 { "LKG_AGGR_63_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_1[] = {
+	 { "WEIGHT_CU_SIG2", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG3", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_2[] = {
+	 { "WEIGHT_CU_SIG4", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG5", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_WEIGHT_CU_3[] = {
+	 { "WEIGHT_CU_SIG6", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_CU_SIG7", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU0[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU1[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU2[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU3[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU4[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU5[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU6[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_ACC_CU7[] = {
+	 { "ACCUMULATOR_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_CTRL[] = {
+	 { "IOC_mst_send", 0, 0, &umr_bitfield_default },
+	 { "IOC_mst_stop", 1, 1, &umr_bitfield_default },
+	 { "IOC_mst_force_active", 2, 2, &umr_bitfield_default },
+	 { "IOC_mst_rdValid", 3, 3, &umr_bitfield_default },
+	 { "IOC_mst_busy", 4, 4, &umr_bitfield_default },
+	 { "IOC_mst_disabled", 5, 5, &umr_bitfield_default },
+	 { "IOC_mst_debug_rst", 6, 6, &umr_bitfield_default },
+	 { "IOC_mst_stop_ack", 7, 7, &umr_bitfield_default },
+	 { "IOC_mst_rderr", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_RDDATA[] = {
+	 { "IOC_mst_rdData", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_PHASE1[] = {
+	 { "BiuCqfC_AwqReqCommit", 1, 1, &umr_bitfield_default },
+	 { "BiuCqfC_AltReqRdCmd", 2, 2, &umr_bitfield_default },
+	 { "BiuCqfC_AltReqAddrLo", 3, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_PHASE2[] = {
+	 { "BiuCqfC_AltReqAddrMid", 0, 7, &umr_bitfield_default },
+	 { "BiuCqfC_AltReqMask", 8, 15, &umr_bitfield_default },
+	 { "BiuCqfC_AltReqSize", 16, 17, &umr_bitfield_default },
+	 { "BiuCqfC_AltReqAddrHi", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_PHASE3[] = {
+	 { "BiuDbfC_C2aDataOut", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_0[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_1[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_2[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_3[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_4[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_5[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_6[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_7[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_8[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_9[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_10[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_11[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_12[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_13[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_14[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_READ_15[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_0[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_1[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_2[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_3[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_4[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_5[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_6[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_7[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_8[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_9[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_10[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_11[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_12[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_13[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_14[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_IOC_WRITE_15[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_CNTL[] = {
+	 { "tag", 0, 16, &umr_bitfield_default },
+	 { "urg", 17, 20, &umr_bitfield_default },
+	 { "stall", 21, 21, &umr_bitfield_default },
+	 { "priv", 22, 22, &umr_bitfield_default },
+	 { "cid", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_CNTL_1[] = {
+	 { "vf", 0, 0, &umr_bitfield_default },
+	 { "vfid", 1, 7, &umr_bitfield_default },
+	 { "physical", 8, 8, &umr_bitfield_default },
+	 { "snoop", 9, 9, &umr_bitfield_default },
+	 { "inval", 10, 10, &umr_bitfield_default },
+	 { "op", 11, 17, &umr_bitfield_default },
+	 { "swap", 20, 21, &umr_bitfield_default },
+	 { "vmid", 22, 25, &umr_bitfield_default },
+	 { "atc", 26, 26, &umr_bitfield_default },
+	 { "fed", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_LOW_ADDR[] = {
+	 { "addr", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR[] = {
+	 { "addr_47_37", 0, 10, &umr_bitfield_default },
+	 { "reserved", 11, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_MASK[] = {
+	 { "mask", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_0[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_1[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_2[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_3[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_4[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_5[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_6[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_DATA_7[] = {
+	 { "data", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRREQ_STATUS[] = {
+	 { "credit_counter", 0, 4, &umr_bitfield_default },
+	 { "reserved0", 5, 7, &umr_bitfield_default },
+	 { "fifo_not_empty", 8, 8, &umr_bitfield_default },
+	 { "reserved1", 9, 15, &umr_bitfield_default },
+	 { "tag_pointer", 16, 19, &umr_bitfield_default },
+	 { "reserved2", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_WRRET_STATUS_0[] = {
+	 { "valid", 0, 0, &umr_bitfield_default },
+	 { "nack", 1, 2, &umr_bitfield_default },
+	 { "reserved", 3, 15, &umr_bitfield_default },
+	 { "tag", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDREQ_ADDR[] = {
+	 { "addr", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDREQ_CNTL[] = {
+	 { "tag", 0, 15, &umr_bitfield_default },
+	 { "mask", 16, 23, &umr_bitfield_default },
+	 { "addr_47_40", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDREQ_CNTL_1[] = {
+	 { "urg", 0, 3, &umr_bitfield_default },
+	 { "stall", 4, 4, &umr_bitfield_default },
+	 { "priv", 5, 5, &umr_bitfield_default },
+	 { "swap", 6, 7, &umr_bitfield_default },
+	 { "cid", 8, 16, &umr_bitfield_default },
+	 { "vmid", 17, 20, &umr_bitfield_default },
+	 { "atc", 21, 21, &umr_bitfield_default },
+	 { "physical", 22, 22, &umr_bitfield_default },
+	 { "exe", 23, 23, &umr_bitfield_default },
+	 { "snoop", 24, 24, &umr_bitfield_default },
+	 { "shared", 25, 25, &umr_bitfield_default },
+	 { "vf", 26, 26, &umr_bitfield_default },
+	 { "vfid", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_VALID[] = {
+	 { "vld_0", 0, 0, &umr_bitfield_default },
+	 { "vld_1", 1, 1, &umr_bitfield_default },
+	 { "vld_2", 2, 2, &umr_bitfield_default },
+	 { "vld_3", 3, 3, &umr_bitfield_default },
+	 { "vld_4", 4, 4, &umr_bitfield_default },
+	 { "vld_5", 5, 5, &umr_bitfield_default },
+	 { "vld_6", 6, 6, &umr_bitfield_default },
+	 { "vld_7", 7, 7, &umr_bitfield_default },
+	 { "reserved", 8, 23, &umr_bitfield_default },
+	 { "atomic", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_NACK[] = {
+	 { "nack_0", 0, 1, &umr_bitfield_default },
+	 { "nack_1", 2, 3, &umr_bitfield_default },
+	 { "nack_2", 4, 5, &umr_bitfield_default },
+	 { "nack_3", 6, 7, &umr_bitfield_default },
+	 { "nack_4", 8, 9, &umr_bitfield_default },
+	 { "nack_5", 10, 11, &umr_bitfield_default },
+	 { "nack_6", 12, 13, &umr_bitfield_default },
+	 { "nack_7", 14, 15, &umr_bitfield_default },
+	 { "reserved", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_2[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_3[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_4[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_5[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_6[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_7[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_8[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_9[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_10[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_11[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_12[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_13[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_14[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_15[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_16[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_17[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_18[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_19[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_20[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_21[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_22[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_23[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_24[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_25[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_26[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_27[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_28[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_29[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_30[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_31[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_32[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_33[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_34[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_35[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_36[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_37[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_38[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_39[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_40[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_41[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_42[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_43[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_44[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_45[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_46[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_47[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_48[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_49[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_50[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_51[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_52[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_53[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_54[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_55[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_56[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_57[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_58[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_59[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_60[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_61[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_62[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_DRAM_CNTL_RDRET_DATA_63[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_INTERRUPT_CONTROL[] = {
+	 { "MAX_CREDIT_VALUE", 0, 4, &umr_bitfield_default },
+	 { "MP0_SW_TRIG_MASK", 5, 5, &umr_bitfield_default },
+	 { "MP0_SW_INT_ACK", 6, 6, &umr_bitfield_default },
+	 { "MP1_SW_TRIG_MASK", 7, 7, &umr_bitfield_default },
+	 { "MP1_SW_INT_ACK", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP0_SW_INT[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "INT_ID", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP0_SW_INT_CTXID[] = {
+	 { "CTXID", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP1_SW_INT[] = {
+	 { "VALID", 0, 0, &umr_bitfield_default },
+	 { "INT_ID", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP1_SW_INT_CTXID[] = {
+	 { "CTXID", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDISP_TIMER_ID[] = {
+	 { "DISP_T0_INT_ID", 0, 7, &umr_bitfield_default },
+	 { "DISP_T1_INT_ID", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_FPS_CNT_XBAR[] = {
+	 { "FPS_CNT", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_SRBM_CONFIG_XBAR[] = {
+	 { "MSTR_CREDITS", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_SRBM_CONTROL[] = {
+	 { "ACC_VIO_EN", 0, 0, &umr_bitfield_default },
+	 { "ALLOW_NS_ACC", 1, 1, &umr_bitfield_default },
+	 { "SOFT_RST_MASK", 2, 2, &umr_bitfield_default },
+	 { "SOFT_RST_STS", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_SRBM_ACCVIO_LOG[] = {
+	 { "ACC_VIO_OP", 0, 0, &umr_bitfield_default },
+	 { "ACC_VIO_SRCID", 1, 3, &umr_bitfield_default },
+	 { "ACC_VIO_VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_SRBM_ACCVIO_ADDR[] = {
+	 { "ACC_VIO_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_CRBBM_CONTROL[] = {
+	 { "ACC_VIO_EN", 0, 0, &umr_bitfield_default },
+	 { "MP0_ACCESS", 1, 1, &umr_bitfield_default },
+	 { "ALLOW_NS_ACC", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_CRBBM_ACCVIO_LOG[] = {
+	 { "ACC_VIO_OP", 0, 0, &umr_bitfield_default },
+	 { "ACC_VIO_INTF", 1, 1, &umr_bitfield_default },
+	 { "ACC_VIO_VALID", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMP_CRBBM_ACCVIO_ADDR[] = {
+	 { "ACC_VIO_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGENERAL_PWRMGT[] = {
+	 { "GLOBAL_PWRMGT_EN", 0, 0, &umr_bitfield_default },
+	 { "STATIC_PM_EN", 1, 1, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_DIS", 2, 2, &umr_bitfield_default },
+	 { "THERMAL_PROTECTION_TYPE", 3, 3, &umr_bitfield_default },
+	 { "SW_SMIO_INDEX", 6, 6, &umr_bitfield_default },
+	 { "LOW_VOLT_D2_ACPI", 8, 8, &umr_bitfield_default },
+	 { "LOW_VOLT_D3_ACPI", 9, 9, &umr_bitfield_default },
+	 { "VOLT_PWRMGT_EN", 10, 10, &umr_bitfield_default },
+	 { "SPARE11", 11, 11, &umr_bitfield_default },
+	 { "GPU_COUNTER_ACPI", 14, 14, &umr_bitfield_default },
+	 { "GPU_COUNTER_CLK", 15, 15, &umr_bitfield_default },
+	 { "GPU_COUNTER_OFF", 16, 16, &umr_bitfield_default },
+	 { "GPU_COUNTER_INTF_OFF", 17, 17, &umr_bitfield_default },
+	 { "SPARE18", 18, 18, &umr_bitfield_default },
+	 { "ACPI_D3_VID", 19, 20, &umr_bitfield_default },
+	 { "DYN_SPREAD_SPECTRUM_EN", 23, 23, &umr_bitfield_default },
+	 { "SPARE27", 27, 27, &umr_bitfield_default },
+	 { "SPARE", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCNB_PWRMGT_CNTL[] = {
+	 { "GNB_SLOW_MODE", 0, 1, &umr_bitfield_default },
+	 { "GNB_SLOW", 2, 2, &umr_bitfield_default },
+	 { "FORCE_NB_PS1", 3, 3, &umr_bitfield_default },
+	 { "DPM_ENABLED", 4, 4, &umr_bitfield_default },
+	 { "SPARE", 5, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_PWRMGT_CNTL[] = {
+	 { "RESET_BUSY_CNT", 4, 4, &umr_bitfield_default },
+	 { "RESET_SCLK_CNT", 5, 5, &umr_bitfield_default },
+	 { "RESERVED_0", 6, 6, &umr_bitfield_default },
+	 { "RESERVED_3", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX[] = {
+	 { "TARG_ACPI_INDEX", 0, 3, &umr_bitfield_default },
+	 { "CURR_ACPI_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_MCLK_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MCLK_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_SCLK_INDEX", 16, 20, &umr_bitfield_default },
+	 { "TARG_SCLK_INDEX", 21, 25, &umr_bitfield_default },
+	 { "CURR_LCLK_INDEX", 26, 28, &umr_bitfield_default },
+	 { "TARG_LCLK_INDEX", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_STATIC_SCREEN_PARAMETER[] = {
+	 { "STATIC_SCREEN_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "STATIC_SCREEN_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ACPI_CNTL[] = {
+	 { "SCLK_ACPI_DIV", 0, 6, &umr_bitfield_default },
+	 { "SCLK_CHANGE_SKIP", 7, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 16, 16, &umr_bitfield_default },
+	 { "SELF_REFRESH_MASK", 17, 17, &umr_bitfield_default },
+	 { "ALLOW_NBPSTATE_MASK", 18, 18, &umr_bitfield_default },
+	 { "BIF_BUSY_MASK", 19, 19, &umr_bitfield_default },
+	 { "UVD_BUSY_MASK", 20, 20, &umr_bitfield_default },
+	 { "MC0SRBM_BUSY_MASK", 21, 21, &umr_bitfield_default },
+	 { "MC1SRBM_BUSY_MASK", 22, 22, &umr_bitfield_default },
+	 { "MC_ALLOW_MASK", 23, 23, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 24, 24, &umr_bitfield_default },
+	 { "SELF_REFRESH_NLC_MASK", 25, 25, &umr_bitfield_default },
+	 { "FAST_EXIT_REQ_NBPSTATE", 26, 26, &umr_bitfield_default },
+	 { "DEEP_SLEEP_ENTRY_MODE", 27, 27, &umr_bitfield_default },
+	 { "MBUS2_ACTIVE_MASK", 28, 28, &umr_bitfield_default },
+	 { "VCE_0_BUSY_MASK", 29, 29, &umr_bitfield_default },
+	 { "AZ_BUSY_MASK", 30, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RLC_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "HDP_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "ROM_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "PDMA_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "IDCT_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "SDMA_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "DC_AZ_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK", 9, 9, &umr_bitfield_default },
+	 { "UVD_CG_MC_STAT_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "VCE_0_CG_MC_STAT_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "VCE_1_BUSY_MASK", 21, 21, &umr_bitfield_default },
+	 { "VCE_1_CG_MC_STAT_BUSY_MASK", 22, 22, &umr_bitfield_default },
+	 { "REG_SCLK_DEEP_SLEEP_MASK", 23, 23, &umr_bitfield_default },
+	 { "INOUT_CUSHION", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_MISC_CNTL[] = {
+	 { "DPM_DS_DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "DPM_SS_DIV_ID", 3, 5, &umr_bitfield_default },
+	 { "OCP_ENABLE", 16, 16, &umr_bitfield_default },
+	 { "OCP_DS_DIV_ID", 17, 19, &umr_bitfield_default },
+	 { "OCP_SS_DIV_ID", 20, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL[] = {
+	 { "DIV_ID", 0, 2, &umr_bitfield_default },
+	 { "RAMP_DIS", 3, 3, &umr_bitfield_default },
+	 { "HYSTERESIS", 4, 15, &umr_bitfield_default },
+	 { "RESERVED", 16, 30, &umr_bitfield_default },
+	 { "ENABLE_DS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSMU_VOLTAGE_STATUS[] = {
+	 { "SMU_VOLTAGE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "SMU_VOLTAGE_CURRENT_LEVEL", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_DEEP_SLEEP_CNTL3[] = {
+	 { "GRBM_0_SMU_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "GRBM_1_SMU_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "GRBM_2_SMU_BUSY_MASK", 2, 2, &umr_bitfield_default },
+	 { "GRBM_3_SMU_BUSY_MASK", 3, 3, &umr_bitfield_default },
+	 { "GRBM_4_SMU_BUSY_MASK", 4, 4, &umr_bitfield_default },
+	 { "GRBM_5_SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "GRBM_6_SMU_BUSY_MASK", 6, 6, &umr_bitfield_default },
+	 { "GRBM_7_SMU_BUSY_MASK", 7, 7, &umr_bitfield_default },
+	 { "GRBM_8_SMU_BUSY_MASK", 8, 8, &umr_bitfield_default },
+	 { "GRBM_9_SMU_BUSY_MASK", 9, 9, &umr_bitfield_default },
+	 { "GRBM_10_SMU_BUSY_MASK", 10, 10, &umr_bitfield_default },
+	 { "GRBM_11_SMU_BUSY_MASK", 11, 11, &umr_bitfield_default },
+	 { "GRBM_12_SMU_BUSY_MASK", 12, 12, &umr_bitfield_default },
+	 { "GRBM_13_SMU_BUSY_MASK", 13, 13, &umr_bitfield_default },
+	 { "GRBM_14_SMU_BUSY_MASK", 14, 14, &umr_bitfield_default },
+	 { "GRBM_15_SMU_BUSY_MASK", 15, 15, &umr_bitfield_default },
+	 { "SMUIF_SLAVE_SCLK_BUSY_MASK", 16, 16, &umr_bitfield_default },
+	 { "SMUIF_MASTER_SCLK_BUSY_MASK", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_1[] = {
+	 { "CURR_VDDCI_INDEX", 0, 3, &umr_bitfield_default },
+	 { "TARG_VDDCI_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_MVDD_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_MVDD_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_VDDC_INDEX", 16, 19, &umr_bitfield_default },
+	 { "TARG_VDDC_INDEX", 20, 23, &umr_bitfield_default },
+	 { "CURR_PCIE_INDEX", 24, 27, &umr_bitfield_default },
+	 { "TARG_PCIE_INDEX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTARGET_AND_CURRENT_PROFILE_INDEX_2[] = {
+	 { "CURR_UVD_INDEX", 0, 3, &umr_bitfield_default },
+	 { "TARG_UVD_INDEX", 4, 7, &umr_bitfield_default },
+	 { "CURR_VCE_INDEX", 8, 11, &umr_bitfield_default },
+	 { "TARG_VCE_INDEX", 12, 15, &umr_bitfield_default },
+	 { "CURR_ACP_INDEX", 16, 19, &umr_bitfield_default },
+	 { "TARG_ACP_INDEX", 20, 23, &umr_bitfield_default },
+	 { "CURR_SAMU_INDEX", 24, 27, &umr_bitfield_default },
+	 { "TARG_SAMU_INDEX", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_ULV_PARAMETER[] = {
+	 { "ULV_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "ULV_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_0[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_1[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_2[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_3[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_4[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_5[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_6[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCG_FREQ_TRAN_VOTING_7[] = {
+	 { "BIF_FREQ_THROTTLING_VOTE_EN", 0, 0, &umr_bitfield_default },
+	 { "HDP_FREQ_THROTTLING_VOTE_EN", 1, 1, &umr_bitfield_default },
+	 { "ROM_FREQ_THROTTLING_VOTE_EN", 2, 2, &umr_bitfield_default },
+	 { "IH_SEM_FREQ_THROTTLING_VOTE_EN", 3, 3, &umr_bitfield_default },
+	 { "PDMA_FREQ_THROTTLING_VOTE_EN", 4, 4, &umr_bitfield_default },
+	 { "DRM_FREQ_THROTTLING_VOTE_EN", 5, 5, &umr_bitfield_default },
+	 { "IDCT_FREQ_THROTTLING_VOTE_EN", 6, 6, &umr_bitfield_default },
+	 { "ACP_FREQ_THROTTLING_VOTE_EN", 7, 7, &umr_bitfield_default },
+	 { "SDMA_FREQ_THROTTLING_VOTE_EN", 8, 8, &umr_bitfield_default },
+	 { "UVD_FREQ_THROTTLING_VOTE_EN", 9, 9, &umr_bitfield_default },
+	 { "VCE_0_FREQ_THROTTLING_VOTE_EN", 10, 10, &umr_bitfield_default },
+	 { "DC_AZ_FREQ_THROTTLING_VOTE_EN", 11, 11, &umr_bitfield_default },
+	 { "AVP_FREQ_THROTTLING_VOTE_EN", 13, 13, &umr_bitfield_default },
+	 { "GRBM_0_FREQ_THROTTLING_VOTE_EN", 14, 14, &umr_bitfield_default },
+	 { "GRBM_1_FREQ_THROTTLING_VOTE_EN", 15, 15, &umr_bitfield_default },
+	 { "GRBM_2_FREQ_THROTTLING_VOTE_EN", 16, 16, &umr_bitfield_default },
+	 { "GRBM_3_FREQ_THROTTLING_VOTE_EN", 17, 17, &umr_bitfield_default },
+	 { "GRBM_4_FREQ_THROTTLING_VOTE_EN", 18, 18, &umr_bitfield_default },
+	 { "GRBM_5_FREQ_THROTTLING_VOTE_EN", 19, 19, &umr_bitfield_default },
+	 { "GRBM_6_FREQ_THROTTLING_VOTE_EN", 20, 20, &umr_bitfield_default },
+	 { "GRBM_7_FREQ_THROTTLING_VOTE_EN", 21, 21, &umr_bitfield_default },
+	 { "GRBM_8_FREQ_THROTTLING_VOTE_EN", 22, 22, &umr_bitfield_default },
+	 { "GRBM_9_FREQ_THROTTLING_VOTE_EN", 23, 23, &umr_bitfield_default },
+	 { "GRBM_10_FREQ_THROTTLING_VOTE_EN", 24, 24, &umr_bitfield_default },
+	 { "GRBM_11_FREQ_THROTTLING_VOTE_EN", 25, 25, &umr_bitfield_default },
+	 { "GRBM_12_FREQ_THROTTLING_VOTE_EN", 26, 26, &umr_bitfield_default },
+	 { "GRBM_13_FREQ_THROTTLING_VOTE_EN", 27, 27, &umr_bitfield_default },
+	 { "GRBM_14_FREQ_THROTTLING_VOTE_EN", 28, 28, &umr_bitfield_default },
+	 { "GRBM_15_FREQ_THROTTLING_VOTE_EN", 29, 29, &umr_bitfield_default },
+	 { "RLC_FREQ_THROTTLING_VOTE_EN", 30, 30, &umr_bitfield_default },
+	 { "VCE_1_FREQ_THROTTLING_VOTE_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PGFSM_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "Power_Down", 8, 8, &umr_bitfield_default },
+	 { "Power_Up", 9, 9, &umr_bitfield_default },
+	 { "P1_Select", 10, 10, &umr_bitfield_default },
+	 { "P2_Select", 11, 11, &umr_bitfield_default },
+	 { "Write_Op", 12, 12, &umr_bitfield_default },
+	 { "Read_Op", 13, 13, &umr_bitfield_default },
+	 { "Reserved", 14, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PGFSM_WRITE[] = {
+	 { "Write_value", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSERDES_BUSY[] = {
+	 { "PCIE_SERDES_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PGFSM2_CONFIG[] = {
+	 { "FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "Power_Down", 8, 8, &umr_bitfield_default },
+	 { "Power_Up", 9, 9, &umr_bitfield_default },
+	 { "P1_Select", 10, 10, &umr_bitfield_default },
+	 { "P2_Select", 11, 11, &umr_bitfield_default },
+	 { "Write_Op", 12, 12, &umr_bitfield_default },
+	 { "Read_Op", 13, 13, &umr_bitfield_default },
+	 { "Reserved", 14, 27, &umr_bitfield_default },
+	 { "REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PGFSM2_WRITE[] = {
+	 { "Write_value", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSERDES2_BUSY[] = {
+	 { "PCIE_SERDES_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PGFSM_0_READ[] = {
+	 { "Read_value", 0, 23, &umr_bitfield_default },
+	 { "Read_valid", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPCIE_PGFSM_1_READ[] = {
+	 { "Read_value", 0, 23, &umr_bitfield_default },
+	 { "Read_valid", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DC_RESP[] = {
+	 { "RESPONSE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_VCE_RESP[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_UVD_RESP[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_ACP_RESP[] = {
+	 { "RESPONSE", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCLK_DEEP_SLEEP_CNTL2[] = {
+	 { "RFE_BUSY_MASK", 0, 0, &umr_bitfield_default },
+	 { "BIF_CG_LCLK_BUSY_MASK", 1, 1, &umr_bitfield_default },
+	 { "L1IMU_SMU_IDLE_MASK", 2, 2, &umr_bitfield_default },
+	 { "RESERVED_BIT3", 3, 3, &umr_bitfield_default },
+	 { "SCLK_RUNNING_MASK", 4, 4, &umr_bitfield_default },
+	 { "SMU_BUSY_MASK", 5, 5, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE1_MASK", 6, 6, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE2_MASK", 7, 7, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE3_MASK", 8, 8, &umr_bitfield_default },
+	 { "PCIE_LCLK_IDLE4_MASK", 9, 9, &umr_bitfield_default },
+	 { "L1IMUGPP_IDLE_MASK", 10, 10, &umr_bitfield_default },
+	 { "L1IMUGPPSB_IDLE_MASK", 11, 11, &umr_bitfield_default },
+	 { "L1IMUBIF_IDLE_MASK", 12, 12, &umr_bitfield_default },
+	 { "L1IMUINTGEN_IDLE_MASK", 13, 13, &umr_bitfield_default },
+	 { "L2IMU_IDLE_MASK", 14, 14, &umr_bitfield_default },
+	 { "ORB_IDLE_MASK", 15, 15, &umr_bitfield_default },
+	 { "ON_INB_WAKE_MASK", 16, 16, &umr_bitfield_default },
+	 { "ON_INB_WAKE_ACK_MASK", 17, 17, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_MASK", 18, 18, &umr_bitfield_default },
+	 { "ON_OUTB_WAKE_ACK_MASK", 19, 19, &umr_bitfield_default },
+	 { "DMAACTIVE_MASK", 20, 20, &umr_bitfield_default },
+	 { "L1IMUPCIE0_IDLE_MASK", 21, 21, &umr_bitfield_default },
+	 { "L1IMUPCIE1_IDLE_MASK", 22, 22, &umr_bitfield_default },
+	 { "L1IMUIOAGR_IDLE_MASK", 23, 23, &umr_bitfield_default },
+	 { "SPG_SMU_IDLE_MASK", 24, 24, &umr_bitfield_default },
+	 { "APG_SMU_IDLE_MASK", 25, 25, &umr_bitfield_default },
+	 { "IP_SMU_IDLE0_MASK", 26, 26, &umr_bitfield_default },
+	 { "IP_SMU_IDLE1_MASK", 27, 27, &umr_bitfield_default },
+	 { "IP_SMU_IDLE2_MASK", 28, 28, &umr_bitfield_default },
+	 { "IP_SMU_IDLE3_MASK", 29, 29, &umr_bitfield_default },
+	 { "RESERVED", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_ACPI_INTERRUPT[] = {
+	 { "BIF_CG_req", 0, 0, &umr_bitfield_default },
+	 { "AZ_CG_req", 1, 1, &umr_bitfield_default },
+	 { "AZ_CG_resp", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPWR_DC_REQ[] = {
+	 { "REQUEST", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_PARAMETER[] = {
+	 { "VDDGFX_IDLE_THRESHOLD", 0, 15, &umr_bitfield_default },
+	 { "VDDGFX_IDLE_THRESHOLD_UNIT", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_CONTROL[] = {
+	 { "VDDGFX_IDLE_EN", 0, 0, &umr_bitfield_default },
+	 { "VDDGFX_IDLE_DETECT", 1, 1, &umr_bitfield_default },
+	 { "FORCE_VDDGFX_IDLE_EXIT", 2, 2, &umr_bitfield_default },
+	 { "SMC_VDDGFX_IDLE_STATE", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixVDDGFX_IDLE_EXIT[] = {
+	 { "BIF_EXIT_REQ", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixREG_SCLK_DEEP_SLEEP_EXIT[] = {
+	 { "REG_sclk_deep_sleep_exit", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSCLK_MIN_DIV[] = {
+	 { "FRACV", 0, 11, &umr_bitfield_default },
+	 { "INTV", 12, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCAC_WEIGHT_LKG_DC_3[] = {
+	 { "WEIGHT_LKG_DC_SIG4", 0, 15, &umr_bitfield_default },
+	 { "WEIGHT_LKG_DC_SIG5", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_CNTL[] = {
+	 { "MC0_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC0_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC0_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC0_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_SEL[] = {
+	 { "MC0_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC0_OVR_VAL[] = {
+	 { "MC0_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_CNTL[] = {
+	 { "MC1_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC1_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC1_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC1_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_SEL[] = {
+	 { "MC1_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC1_OVR_VAL[] = {
+	 { "MC1_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_CNTL[] = {
+	 { "MC2_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC2_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC2_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC2_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_SEL[] = {
+	 { "MC2_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC2_OVR_VAL[] = {
+	 { "MC2_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_CNTL[] = {
+	 { "MC3_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "MC3_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "MC3_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "MC3_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_SEL[] = {
+	 { "MC3_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_MC3_OVR_VAL[] = {
+	 { "MC3_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_CNTL[] = {
+	 { "CPL_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "CPL_THRESHOLD", 1, 16, &umr_bitfield_default },
+	 { "CPL_BLOCK_ID", 17, 21, &umr_bitfield_default },
+	 { "CPL_SIGNAL_ID", 22, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_SEL[] = {
+	 { "CPL_OVR_SEL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLCAC_CPL_OVR_VAL[] = {
+	 { "CPL_OVR_VAL", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_UNB_PWRMGT_CFG0[] = {
+	 { "TARGET_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_UNB_PWRMGT_CFG1[] = {
+	 { "TIMER_EN", 0, 0, &umr_bitfield_default },
+	 { "TIMER_INTERVAL", 1, 16, &umr_bitfield_default },
+	 { "INT_GEN_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_UNB_PWRMGT_DATA[] = {
+	 { "NB_CROSS_TRIGGER", 0, 3, &umr_bitfield_default },
+	 { "NB_PRE_SELF_REFRESH", 4, 4, &umr_bitfield_default },
+	 { "NB_REQ_NB_PSTATE", 5, 5, &umr_bitfield_default },
+	 { "NB_FLUSH_ACK_TOGGLE", 6, 6, &umr_bitfield_default },
+	 { "NB_ON_INB_WAKE_ACK", 7, 7, &umr_bitfield_default },
+	 { "NB_ON3_CH0LINK_WAKE_ACK", 8, 8, &umr_bitfield_default },
+	 { "NB_ON3_CH1LINK_WAKE_ACK", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGNBPM_SMU_PWRMGT_DATA[] = {
+	 { "UNBPM_AllCpusInCC6", 0, 0, &umr_bitfield_default },
+	 { "UNBPM_HtcActive", 1, 1, &umr_bitfield_default },
+	 { "UNBPM_SmuInt", 2, 2, &umr_bitfield_default },
+	 { "UNBPM_SPARE", 3, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDMA_ACTIVE_SAMPLER_CFG[] = {
+	 { "SAMPLING_TIMER_EN", 0, 0, &umr_bitfield_default },
+	 { "SAMPLING_TIMER_PERIOD", 1, 16, &umr_bitfield_default },
+	 { "DMA_ACTIVE_TRANS_CNT", 17, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSOUTHBRIDGE_TYPE[] = {
+	 { "DISCRETE_SB", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGNBPM_SMU_PWRMGT_STATUS[] = {
+	 { "PM_AllCpusInCC6", 0, 0, &umr_bitfield_default },
+	 { "PM_HtcActive", 1, 1, &umr_bitfield_default },
+	 { "PM_SmuInt", 2, 2, &umr_bitfield_default },
+	 { "PM_SmuIntSuperVminExit", 3, 3, &umr_bitfield_default },
+	 { "PM_PreSelfRefresh", 4, 4, &umr_bitfield_default },
+	 { "PM_ReqNbPstate", 5, 5, &umr_bitfield_default },
+	 { "PM_AllowNbPstate", 6, 6, &umr_bitfield_default },
+	 { "PM_AllowSelfRefresh", 7, 7, &umr_bitfield_default },
+	 { "PM_IntrWake", 8, 8, &umr_bitfield_default },
+	 { "SPARE", 9, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixALLOW_SR_INTR_CTRL[] = {
+	 { "ALLOW_SR_INTR_CTRL", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_STATE_CPU0[] = {
+	 { "CURRENT_PSTATE_ID", 0, 2, &umr_bitfield_default },
+	 { "CURRENT_DID", 3, 5, &umr_bitfield_default },
+	 { "CURRENT_FID", 6, 11, &umr_bitfield_default },
+	 { "CPU_COF", 12, 23, &umr_bitfield_default },
+	 { "CPU_COF_IND_PROG", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCPU_REDUN_DONE0[] = {
+	 { "CPU_REDUN_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_VID_CPU0[] = {
+	 { "CURRENT_VID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_STATE_CPU1[] = {
+	 { "CURRENT_PSTATE_ID", 0, 2, &umr_bitfield_default },
+	 { "CURRENT_DID", 3, 5, &umr_bitfield_default },
+	 { "CURRENT_FID", 6, 11, &umr_bitfield_default },
+	 { "CPU_COF", 12, 23, &umr_bitfield_default },
+	 { "CPU_COF_IND_PROG", 24, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCPU_REDUN_DONE1[] = {
+	 { "CPU_REDUN_DONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_VID_CPU1[] = {
+	 { "CURRENT_VID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_PWRMGT_ACK[] = {
+	 { "REQUESTOR_CODE", 0, 4, &umr_bitfield_default },
+	 { "REQUEST_ACK", 8, 8, &umr_bitfield_default },
+	 { "REQUEST_NACK", 16, 16, &umr_bitfield_default },
+	 { "ERROR_CODE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_FREQ_STATE_NB[] = {
+	 { "CURRENT_FID", 0, 7, &umr_bitfield_default },
+	 { "CURRENT_DID", 8, 15, &umr_bitfield_default },
+	 { "NB_LOW_POWER", 16, 23, &umr_bitfield_default },
+	 { "NB_STUTTER_MODE", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_PSTATE_NB[] = {
+	 { "CURRENT_PSTATE_ID", 0, 7, &umr_bitfield_default },
+	 { "CURRENT_PSTATE_LO", 8, 8, &umr_bitfield_default },
+	 { "CURRENT_MEM_PSTATE_ID", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_MSG_INT_CONFIG[] = {
+	 { "MSG_REG_TARGET_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_NBPWRMGT_CMD[] = {
+	 { "TARGET_BLOCK", 0, 1, &umr_bitfield_default },
+	 { "TARGET_CMD", 8, 8, &umr_bitfield_default },
+	 { "DCT_SR_MAP", 16, 23, &umr_bitfield_default },
+	 { "RETURN_NB_ACK", 24, 24, &umr_bitfield_default },
+	 { "OVERRIDE_PARAMS", 25, 25, &umr_bitfield_default },
+	 { "SET_NB_LOW_POWER", 26, 26, &umr_bitfield_default },
+	 { "SET_NB_STUTTER_MODE", 27, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_NBPWRMGT_FSM_CFG[] = {
+	 { "DIS_AUTO_PWRGATE_ON_EXIT", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDDR0_FUSE_SSB_XFER[] = {
+	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDDR0_FUSE_SSB_XFER_CFG[] = {
+	 { "FUSE_DDR0_LAST_ADDR", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDDR1_FUSE_SSB_XFER[] = {
+	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixDDR1_FUSE_SSB_XFER_CFG[] = {
+	 { "FUSE_DDR1_LAST_ADDR", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_FUSES_VAL_PWROK[] = {
+	 { "CK_FUSES_VAL_PWROK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSYNFIFO_CLK_RATIO[] = {
+	 { "CK_CCLK_IS_FASTER0", 0, 0, &umr_bitfield_default },
+	 { "CK_CCLK_IS_FASTER1", 1, 1, &umr_bitfield_default },
+	 { "CK_NCLK_IS_FASTER0", 2, 2, &umr_bitfield_default },
+	 { "CK_NCLK_IS_FASTER1", 3, 3, &umr_bitfield_default },
+	 { "CK_SYNFIFO_ASYNC_EN0", 4, 4, &umr_bitfield_default },
+	 { "CK_SYNFIFO_ASYNC_EN1", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_SMU_PWRMGT_CFG0[] = {
+	 { "TARGET_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_GNB_PWRMGT_CFG1[] = {
+	 { "TIMER_EN", 0, 0, &umr_bitfield_default },
+	 { "TIMER_INTERVAL", 1, 16, &umr_bitfield_default },
+	 { "INT_GEN_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_SMU_PWRMGT_CFG1[] = {
+	 { "TIMER_EN", 0, 0, &umr_bitfield_default },
+	 { "TIMER_INTERVAL", 1, 16, &umr_bitfield_default },
+	 { "INT_GEN_EN", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_GNB_PWRMGT_DATA[] = {
+	 { "GN_ON_INB_WAKE", 0, 0, &umr_bitfield_default },
+	 { "GN_ALLOW_NB_PSTATES", 1, 1, &umr_bitfield_default },
+	 { "GN_FLUSH_REQ_TOGGLE", 2, 2, &umr_bitfield_default },
+	 { "GN_CROSS_TRIGGER", 3, 6, &umr_bitfield_default },
+	 { "GN_STOP_CLOCKS", 7, 7, &umr_bitfield_default },
+	 { "GN_ON3_CH0LINK_WAKE", 8, 8, &umr_bitfield_default },
+	 { "GN_ON3_CH1LINK_WAKE", 9, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGN_GNB_SLOW[] = {
+	 { "GN_GNB_SLOW_DATA", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGN_FORCE_NBPS1[] = {
+	 { "GN_FORCE_NBPS1_DATA", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_SMU_PWRMGT_DATA[] = {
+	 { "NB_NBPS", 0, 0, &umr_bitfield_default },
+	 { "NB_MEMPS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixNB_COF[] = {
+	 { "NB_COF", 0, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_CK_IRESET[] = {
+	 { "CK_IRESET_LOCAL", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCURRENT_VID_NB[] = {
+	 { "CURRENT_VID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_FUSE_PSTATEPWR1[] = {
+	 { "PwrValue0", 0, 7, &umr_bitfield_default },
+	 { "PwrValue1", 8, 15, &umr_bitfield_default },
+	 { "PwrValue2", 16, 23, &umr_bitfield_default },
+	 { "PwrValue3", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_FUSE_PSTATEPWR2[] = {
+	 { "PwrValue4", 0, 7, &umr_bitfield_default },
+	 { "PwrDiv0", 8, 9, &umr_bitfield_default },
+	 { "PwrDiv1", 10, 11, &umr_bitfield_default },
+	 { "PwrDiv2", 12, 13, &umr_bitfield_default },
+	 { "PwrDiv3", 14, 15, &umr_bitfield_default },
+	 { "PwrDiv4", 16, 17, &umr_bitfield_default },
+	 { "PwrDiv5", 18, 19, &umr_bitfield_default },
+	 { "PwrDiv6", 20, 21, &umr_bitfield_default },
+	 { "PwrDiv7", 22, 23, &umr_bitfield_default },
+	 { "Reserved", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_FUSE_PSTATEPWR3[] = {
+	 { "PwrValue5", 0, 7, &umr_bitfield_default },
+	 { "PwrValue6", 8, 15, &umr_bitfield_default },
+	 { "PwrValue7", 16, 23, &umr_bitfield_default },
+	 { "Reserved", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_FUSE_THERMAL_SCRATCH[] = {
+	 { "ThermalScratch", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_PRODUCT_INFO0[] = {
+	 { "BrandId", 0, 15, &umr_bitfield_default },
+	 { "Reserved0", 16, 18, &umr_bitfield_default },
+	 { "SerialNumRdDis", 19, 19, &umr_bitfield_default },
+	 { "Reserved1", 20, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_SERIALNUM_REG1[] = {
+	 { "SPR_SERIALNUM_REG1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_SERIALNUM_REG2[] = {
+	 { "SPR_SERIALNUM_REG2", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_PRODUCT_INFO1[] = {
+	 { "DiDtMode", 0, 0, &umr_bitfield_default },
+	 { "DiDtCfg0", 1, 5, &umr_bitfield_default },
+	 { "DiDtCfg1", 6, 13, &umr_bitfield_default },
+	 { "DiDtCfg2", 14, 15, &umr_bitfield_default },
+	 { "DiDtCfg3", 16, 16, &umr_bitfield_default },
+	 { "DiDtCfg4", 17, 20, &umr_bitfield_default },
+	 { "Reserved", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_EXT_PRODUCT_INFO[] = {
+	 { "Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_MSIDFUSE[] = {
+	 { "MSID", 0, 23, &umr_bitfield_default },
+	 { "Reserved", 24, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_LINK_PRODUCT_INFO[] = {
+	 { "Reserved", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_BRAND_NAME_ADDR[] = {
+	 { "Index", 0, 3, &umr_bitfield_default },
+	 { "Reserved", 4, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_BRAND_NAME_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_COMBO_PHY_PRODUCT_INFO[] = {
+	 { "SPR_COMBO_PHY_PRODUCT_INFO", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixMISC_GNB_PWRMGT_CFG0[] = {
+	 { "TARGET_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_EXIT_TO_PSTATE[] = {
+	 { "EXIT_TO_PSTATE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_WARM_RESET_HS_STATUS[] = {
+	 { "NB_CSTATE_ACTIVE", 0, 0, &umr_bitfield_default },
+	 { "WARM_RESET_HS_DONE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_VOLTAGE_CNTL[] = {
+	 { "VOLTAGE_EN", 0, 0, &umr_bitfield_default },
+	 { "VOLTAGE_LEVEL", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_VOLTAGE_STATUS[] = {
+	 { "VOLTAGE_STATUS", 0, 0, &umr_bitfield_default },
+	 { "VOLTAGE_CURRENT_LEVEL", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixNUM_BOOST_STATES[] = {
+	 { "NUM_BOOST_STATES", 0, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixWARM_RESET_NB_CONTROL[] = {
+	 { "WARM_RESET_CPU_VID", 0, 7, &umr_bitfield_default },
+	 { "NB_DISABLE_CORE", 8, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixONION_NO_STREAMS_PEND[] = {
+	 { "ONION_NO_STREAMS_PEND", 0, 0, &umr_bitfield_default },
+	 { "ONION3_NO_STREAMS_PEND_0", 1, 1, &umr_bitfield_default },
+	 { "ONION3_NO_STREAMS_PEND_1", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPR_PROGRAMMABLE_CTRL[] = {
+	 { "PllRegUpTime", 0, 1, &umr_bitfield_default },
+	 { "PllVddOutUpTime", 2, 3, &umr_bitfield_default },
+	 { "ResonanceTime", 4, 5, &umr_bitfield_default },
+	 { "C6PLLPwrDnReg", 6, 6, &umr_bitfield_default },
+	 { "CC6PLLPwrDnVCO", 7, 7, &umr_bitfield_default },
+	 { "CC6PLLPwrDnReg", 8, 8, &umr_bitfield_default },
+	 { "NbPLLPwrDnReg", 9, 9, &umr_bitfield_default },
+	 { "SOIWait", 10, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPHN_FUSERX_MISC_FUSES[] = {
+	 { "Spare", 0, 7, &umr_bitfield_default },
+	 { "OverClockRefClkDis", 8, 8, &umr_bitfield_default },
+	 { "MemPstate", 9, 12, &umr_bitfield_default },
+	 { "NbPstateHi", 13, 14, &umr_bitfield_default },
+	 { "NbPstateLo", 15, 16, &umr_bitfield_default },
+	 { "ScanCLK400MHz", 17, 17, &umr_bitfield_default },
+	 { "CoreDis", 18, 21, &umr_bitfield_default },
+	 { "PHN_FusesValid", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_PWRCTRL_MISC[] = {
+	 { "PWRGATEMASTERDIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCSTATE_ACTIVE_SAMPLER[] = {
+	 { "SAMPLE_TIME", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_DEBUG_CONFIG_STATUS[] = {
+	 { "AXI_MASTER_QOS", 0, 3, &umr_bitfield_default },
+	 { "FIFO_BUFF_FLUSH", 4, 4, &umr_bitfield_default },
+	 { "MASTER_DEBUG_EN", 5, 5, &umr_bitfield_default },
+	 { "AXI_MASTER_ACTIVE", 8, 8, &umr_bitfield_default },
+	 { "AXI_MASTER_BUSY", 9, 9, &umr_bitfield_default },
+	 { "FIFO_DATA_COUNT", 10, 13, &umr_bitfield_default },
+	 { "MST_OUTSTANDING_TRANS", 16, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_AXIMST_LAST_CMD[] = {
+	 { "AXI_MASTER_LAST_CMD", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNB_IF_INTRGEN_LAST_SENT[] = {
+	 { "GNBPM_LAST_DATA_SENT", 0, 15, &umr_bitfield_default },
+	 { "SMUPM_LAST_DATA_SENT", 16, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_DEBUG_BUS_CNTL[] = {
+	 { "DEBUG_BUS_LOGGING_EN", 0, 0, &umr_bitfield_default },
+	 { "DEBUG_BUS_CYCLE_NUM", 1, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_PWRMGT_REQ_DBG_STATUS[] = {
+	 { "NB_PwrMgtReqNb", 0, 0, &umr_bitfield_default },
+	 { "NB_PwrMgtReqDct", 1, 2, &umr_bitfield_default },
+	 { "NB_PwrMgtReqCpu", 3, 5, &umr_bitfield_default },
+	 { "NB_PwrMgtReqCpuPwrTog", 6, 6, &umr_bitfield_default },
+	 { "NB_PwrMgtReqNbPstateLo", 7, 7, &umr_bitfield_default },
+	 { "NB_PwrMgtReqNbMemPstate", 8, 8, &umr_bitfield_default },
+	 { "NB_PwrMgtReqCpuNbFid", 9, 14, &umr_bitfield_default },
+	 { "NB_PwrMgtReqDid", 15, 17, &umr_bitfield_default },
+	 { "NB_PwrMgtReqPstate", 18, 18, &umr_bitfield_default },
+	 { "NB_PwrMgtReqPstateId", 19, 21, &umr_bitfield_default },
+	 { "NB_PwrMgtReqGateEn", 22, 22, &umr_bitfield_default },
+	 { "NB_PwrMgtReqCpuPrbEn", 23, 23, &umr_bitfield_default },
+	 { "NbPwrMgtReqOutstanding", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_VIDCHG_REQ_DBG_STATUS[] = {
+	 { "NB_VidChgZeroVid", 0, 0, &umr_bitfield_default },
+	 { "NB_VidPlane", 1, 2, &umr_bitfield_default },
+	 { "NB_VidChgRamp", 3, 3, &umr_bitfield_default },
+	 { "NB_Vid", 4, 11, &umr_bitfield_default },
+	 { "NB_VSTime", 12, 14, &umr_bitfield_default },
+	 { "CK_VidChgBusy", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_SCRATCH_0[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUNBPM_SCRATCH_1[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPOWERON_CPU_0[] = {
+	 { "POWERON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPOWERREADY_CPU_0[] = {
+	 { "POWERREADY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPGRUNFEEDBACK_CPU_0[] = {
+	 { "PG_RUNFEEDBACK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCC3ON_CPU_0[] = {
+	 { "CK_RCC3ON", 0, 0, &umr_bitfield_default },
+	 { "RCC3_PSM_EN", 1, 1, &umr_bitfield_default },
+	 { "RCC3_PSM_CLK_DIV", 2, 3, &umr_bitfield_default },
+	 { "RCC3_AVG_EN", 4, 4, &umr_bitfield_default },
+	 { "RCC3_AVG_DIV", 5, 10, &umr_bitfield_default },
+	 { "RCC3_DIDT_TIMER", 11, 16, &umr_bitfield_default },
+	 { "RCC3_WAKE_MIN_14_0", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCC3EXITDONE_CPU_0[] = {
+	 { "RCC3EXITDONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_FUNC_LATE_SSB_XFER_0[] = {
+	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_FUNC_LATE_SSB_XFER_CFG_0[] = {
+	 { "FUSE_FUNC_LAST_ADDR", 0, 10, &umr_bitfield_default },
+	 { "FUSE_LATE_LAST_ADDR", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_REDUN_SSB_XFER_0[] = {
+	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_REDUN_SSB_XFER_CFG_0[] = {
+	 { "FUSE_REDUN_LAST_ADDR", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_APM_SSB_XFER_0[] = {
+	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_APM_SSB_XFER_CFG_0[] = {
+	 { "FUSE_APM_LAST_ADDR", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCOREPM_PWRCTRL_MISC_0[] = {
+	 { "PWRGATEMASTERDIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLDOIVRON_CPU_0[] = {
+	 { "CK_LDOIVRON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLDOIVREXITDONE_CPU_0[] = {
+	 { "LDOIVREXITDONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCC3_TARGETPSMREF_CPU_0[] = {
+	 { "RCC3_TARGETPSMREF", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIVR_TARGETPSMREF_CPU_0[] = {
+	 { "IVR_TARGETPSMREF", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCK_JTCOOLRESET_LATCHED_CPU_0[] = {
+	 { "CK_JTCOOLRESET_LATCHED", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCK_DISABLECORE_CPU_0[] = {
+	 { "CK_DISABLECORE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCOREPM_ID_0[] = {
+	 { "COREPM_INDEX", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCOREPM_SCRATCH_0[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCC3_WAKEMIN_CPU_0[] = {
+	 { "RCC3_WAKE_MIN_46_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_CONFIG0_0[] = {
+	 { "SPMI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SPMI_PATH_NUM_TIMING_FLOPS", 2, 6, &umr_bitfield_default },
+	 { "SPMI_SIGNALING_DELAY_CYCLES", 7, 11, &umr_bitfield_default },
+	 { "SPMI_SIGNALING_HOLD_CYCLES", 12, 16, &umr_bitfield_default },
+	 { "SPMI_PATH_ENABLE_DELAY_CYCLES", 17, 21, &umr_bitfield_default },
+	 { "SPMI_PATH_DISABLE_DELAY_CYCLES", 22, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_CONFIG1_0[] = {
+	 { "SPMI_SIGNALING_RESET_HOLD_CYCLES", 0, 4, &umr_bitfield_default },
+	 { "SPMI_CHAIN_SIZE", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FSM_READ_TRIGGER_0[] = {
+	 { "FSM_READ_TRIGGER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FSM_WRITE_TRIGGER_0[] = {
+	 { "FSM_WRITE_TRIGGER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FSM_RESET_TRIGGER_0[] = {
+	 { "FSM_RESET_TRIGGER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FSM_BUSY_0[] = {
+	 { "FSM_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_PATH_0[] = {
+	 { "PATH_ENABLE_REQ", 0, 0, &umr_bitfield_default },
+	 { "PATH_ENABLE_ACK", 1, 1, &umr_bitfield_default },
+	 { "PATH_ENABLE_REQ_auto_clear", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_C6_STATE_0[] = {
+	 { "SPMI_IF_C6_STATE_ENTERED", 0, 0, &umr_bitfield_default },
+	 { "SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY", 1, 1, &umr_bitfield_default },
+	 { "SPMI_IF_COUNTER_ADDRESS_C6", 2, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_JTAG_OVER_0[] = {
+	 { "SPMI_IF_JTAG_OVER_HAPPENED", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SRAM_ADDRESS_0[] = {
+	 { "SRAM_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SRAM_DATA_0[] = {
+	 { "SRAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_RESET_0[] = {
+	 { "ASYNC_RESET_0", 0, 0, &umr_bitfield_default },
+	 { "SYNC_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FORCE_CLOCK_GATERS_0[] = {
+	 { "CLOCK_GATER_0_FORCE", 0, 0, &umr_bitfield_default },
+	 { "SRAM_CLOCK_GATER_FORCE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SPARE_0[] = {
+	 { "SPARE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SPARE_EX_0[] = {
+	 { "SPARE_DATA_EX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SRAM_CLK_GATER_0[] = {
+	 { "SRAM_CLK_GATER_EN", 0, 0, &umr_bitfield_default },
+	 { "SRAM_CLK_GATER_TIMER", 1, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPOWERON_CPU_1[] = {
+	 { "POWERON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPOWERREADY_CPU_1[] = {
+	 { "POWERREADY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixPGRUNFEEDBACK_CPU_1[] = {
+	 { "PG_RUNFEEDBACK", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCC3ON_CPU_1[] = {
+	 { "CK_RCC3ON", 0, 0, &umr_bitfield_default },
+	 { "RCC3_PSM_EN", 1, 1, &umr_bitfield_default },
+	 { "RCC3_PSM_CLK_DIV", 2, 3, &umr_bitfield_default },
+	 { "RCC3_AVG_EN", 4, 4, &umr_bitfield_default },
+	 { "RCC3_AVG_DIV", 5, 10, &umr_bitfield_default },
+	 { "RCC3_DIDT_TIMER", 11, 16, &umr_bitfield_default },
+	 { "RCC3_WAKE_MIN_14_0", 17, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCC3EXITDONE_CPU_1[] = {
+	 { "RCC3EXITDONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_FUNC_LATE_SSB_XFER_1[] = {
+	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_FUNC_LATE_SSB_XFER_CFG_1[] = {
+	 { "FUSE_FUNC_LAST_ADDR", 0, 10, &umr_bitfield_default },
+	 { "FUSE_LATE_LAST_ADDR", 16, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_REDUN_SSB_XFER_1[] = {
+	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_REDUN_SSB_XFER_CFG_1[] = {
+	 { "FUSE_REDUN_LAST_ADDR", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_APM_SSB_XFER_1[] = {
+	 { "START_STATUS_XFER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCORE_APM_SSB_XFER_CFG_1[] = {
+	 { "FUSE_APM_LAST_ADDR", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCOREPM_PWRCTRL_MISC_1[] = {
+	 { "PWRGATEMASTERDIS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLDOIVRON_CPU_1[] = {
+	 { "CK_LDOIVRON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixLDOIVREXITDONE_CPU_1[] = {
+	 { "LDOIVREXITDONE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCC3_TARGETPSMREF_CPU_1[] = {
+	 { "RCC3_TARGETPSMREF", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixIVR_TARGETPSMREF_CPU_1[] = {
+	 { "IVR_TARGETPSMREF", 0, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCK_JTCOOLRESET_LATCHED_CPU_1[] = {
+	 { "CK_JTCOOLRESET_LATCHED", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCK_DISABLECORE_CPU_1[] = {
+	 { "CK_DISABLECORE", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCOREPM_ID_1[] = {
+	 { "COREPM_INDEX", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixCOREPM_SCRATCH_1[] = {
+	 { "SCRATCH_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixRCC3_WAKEMIN_CPU_1[] = {
+	 { "RCC3_WAKE_MIN_46_15", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_CONFIG0_1[] = {
+	 { "SPMI_ENABLE", 0, 0, &umr_bitfield_default },
+	 { "SPMI_PATH_NUM_TIMING_FLOPS", 2, 6, &umr_bitfield_default },
+	 { "SPMI_SIGNALING_DELAY_CYCLES", 7, 11, &umr_bitfield_default },
+	 { "SPMI_SIGNALING_HOLD_CYCLES", 12, 16, &umr_bitfield_default },
+	 { "SPMI_PATH_ENABLE_DELAY_CYCLES", 17, 21, &umr_bitfield_default },
+	 { "SPMI_PATH_DISABLE_DELAY_CYCLES", 22, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_CONFIG1_1[] = {
+	 { "SPMI_SIGNALING_RESET_HOLD_CYCLES", 0, 4, &umr_bitfield_default },
+	 { "SPMI_CHAIN_SIZE", 5, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FSM_READ_TRIGGER_1[] = {
+	 { "FSM_READ_TRIGGER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FSM_WRITE_TRIGGER_1[] = {
+	 { "FSM_WRITE_TRIGGER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FSM_RESET_TRIGGER_1[] = {
+	 { "FSM_RESET_TRIGGER", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FSM_BUSY_1[] = {
+	 { "FSM_BUSY", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_PATH_1[] = {
+	 { "PATH_ENABLE_REQ", 0, 0, &umr_bitfield_default },
+	 { "PATH_ENABLE_ACK", 1, 1, &umr_bitfield_default },
+	 { "PATH_ENABLE_REQ_auto_clear", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_C6_STATE_1[] = {
+	 { "SPMI_IF_C6_STATE_ENTERED", 0, 0, &umr_bitfield_default },
+	 { "SPMI_IF_C6_STATE_ENTERED_WHEN_FSM_BUSY", 1, 1, &umr_bitfield_default },
+	 { "SPMI_IF_COUNTER_ADDRESS_C6", 2, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_JTAG_OVER_1[] = {
+	 { "SPMI_IF_JTAG_OVER_HAPPENED", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SRAM_ADDRESS_1[] = {
+	 { "SRAM_ADDRESS", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SRAM_DATA_1[] = {
+	 { "SRAM_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_RESET_1[] = {
+	 { "ASYNC_RESET_0", 0, 0, &umr_bitfield_default },
+	 { "SYNC_RESET", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_FORCE_CLOCK_GATERS_1[] = {
+	 { "CLOCK_GATER_0_FORCE", 0, 0, &umr_bitfield_default },
+	 { "SRAM_CLOCK_GATER_FORCE", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SPARE_1[] = {
+	 { "SPARE_DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SPARE_EX_1[] = {
+	 { "SPARE_DATA_EX", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixSPMI_SRAM_CLK_GATER_1[] = {
+	 { "SRAM_CLK_GATER_EN", 0, 0, &umr_bitfield_default },
+	 { "SRAM_CLK_GATER_TIMER", 1, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_HTC[] = {
+	 { "HTC_EN", 0, 0, &umr_bitfield_default },
+	 { "RSVD0", 1, 1, &umr_bitfield_default },
+	 { "HTC_P_STATE_EN", 2, 2, &umr_bitfield_default },
+	 { "RSVD1", 3, 3, &umr_bitfield_default },
+	 { "HTC_ACTIVE", 4, 4, &umr_bitfield_default },
+	 { "HTC_ACTIVE_LOG", 5, 5, &umr_bitfield_default },
+	 { "HTC_APIC_HI_EN", 6, 6, &umr_bitfield_default },
+	 { "HTC_APIC_LO_EN", 7, 7, &umr_bitfield_default },
+	 { "HTC_DIAG", 8, 8, &umr_bitfield_default },
+	 { "DIS_PROCHOT_PIN", 9, 9, &umr_bitfield_default },
+	 { "HTC_TO_GNB_EN", 10, 10, &umr_bitfield_default },
+	 { "PROCHOT_TO_GNB_EN", 11, 11, &umr_bitfield_default },
+	 { "RSVD2", 12, 15, &umr_bitfield_default },
+	 { "HTC_TMP_LMT", 16, 22, &umr_bitfield_default },
+	 { "HTC_SLEW_SEL", 23, 23, &umr_bitfield_default },
+	 { "HTC_HYST_LMT", 24, 27, &umr_bitfield_default },
+	 { "HTC_PSTATE_LIMIT", 28, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_CUR_TMP[] = {
+	 { "PER_STEP_TIME_UP", 0, 4, &umr_bitfield_default },
+	 { "TMP_MAX_DIFF_UP", 5, 6, &umr_bitfield_default },
+	 { "TMP_SLEW_DN_EN", 7, 7, &umr_bitfield_default },
+	 { "PER_STEP_TIME_DN", 8, 12, &umr_bitfield_default },
+	 { "CUR_TEMP_TJ_SEL", 16, 17, &umr_bitfield_default },
+	 { "CUR_TEMP_TJ_SLEW_SEL", 18, 18, &umr_bitfield_default },
+	 { "CUR_TEMP_RANGE_SEL", 19, 19, &umr_bitfield_default },
+	 { "CUR_TEMP", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_THERM_TRIP[] = {
+	 { "RSVD0", 0, 0, &umr_bitfield_default },
+	 { "THERM_TP", 1, 1, &umr_bitfield_default },
+	 { "RSVD1", 2, 2, &umr_bitfield_default },
+	 { "THERM_TP_SENSE", 3, 3, &umr_bitfield_default },
+	 { "RSVD2", 4, 4, &umr_bitfield_default },
+	 { "THERM_TP_EN", 5, 5, &umr_bitfield_default },
+	 { "RSVD3", 6, 30, &umr_bitfield_default },
+	 { "SW_THERM_TP", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_GPIO_PROCHOT_CTRL[] = {
+	 { "TX12_EN", 0, 0, &umr_bitfield_default },
+	 { "PD", 1, 1, &umr_bitfield_default },
+	 { "PU", 2, 2, &umr_bitfield_default },
+	 { "SCHMEN", 3, 3, &umr_bitfield_default },
+	 { "SN", 4, 4, &umr_bitfield_default },
+	 { "OE_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "OE", 9, 9, &umr_bitfield_default },
+	 { "A_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "A", 11, 11, &umr_bitfield_default },
+	 { "Y", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_GPIO_THERMTRIP_CTRL[] = {
+	 { "TX12_EN", 0, 0, &umr_bitfield_default },
+	 { "PD", 1, 1, &umr_bitfield_default },
+	 { "PU", 2, 2, &umr_bitfield_default },
+	 { "SCHMEN", 3, 3, &umr_bitfield_default },
+	 { "SN", 4, 4, &umr_bitfield_default },
+	 { "OE_OVERRIDE", 8, 8, &umr_bitfield_default },
+	 { "OE", 9, 9, &umr_bitfield_default },
+	 { "A_OVERRIDE", 10, 10, &umr_bitfield_default },
+	 { "A", 11, 11, &umr_bitfield_default },
+	 { "Y", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_THERMAL_INT_ENA[] = {
+	 { "THERM_INTH_SET", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_SET", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_SET", 2, 2, &umr_bitfield_default },
+	 { "THERM_INTH_CLR", 3, 3, &umr_bitfield_default },
+	 { "THERM_INTL_CLR", 4, 4, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CLR", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_THERMAL_INT_CTRL[] = {
+	 { "DIG_THERM_INTH", 0, 7, &umr_bitfield_default },
+	 { "DIG_THERM_INTL", 8, 15, &umr_bitfield_default },
+	 { "GNB_TEMP_THRESHOLD", 16, 23, &umr_bitfield_default },
+	 { "THERM_INTH_MASK", 24, 24, &umr_bitfield_default },
+	 { "THERM_INTL_MASK", 25, 25, &umr_bitfield_default },
+	 { "THERM_TRIGGER_MASK", 26, 26, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_MASK", 27, 27, &umr_bitfield_default },
+	 { "THERM_GNB_HW_ENA", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_THERMAL_INT_STATUS[] = {
+	 { "THERM_INTH_DETECT", 0, 0, &umr_bitfield_default },
+	 { "THERM_INTL_DETECT", 1, 1, &umr_bitfield_default },
+	 { "THERM_TRIGGER_DETECT", 2, 2, &umr_bitfield_default },
+	 { "THERM_TRIGGER_CNB_DETECT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_CSR_CONFIG[] = {
+	 { "TCC_ADDR", 0, 9, &umr_bitfield_default },
+	 { "TCC_READ_OP", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_CSR_DATA[] = {
+	 { "TCC_DATA", 0, 11, &umr_bitfield_default },
+	 { "TCC_REQ_DONE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL0_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL1_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL2_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL3_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL4_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL5_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL6_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL7_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL8_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL9_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL10_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL11_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL12_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL13_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL14_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL15_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR0_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR1_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR2_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR3_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR4_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR5_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR6_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR7_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR8_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR9_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR10_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR11_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR12_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR13_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR14_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR15_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_INT_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL_PRESENT0[] = {
+	 { "RDIL_PRESENT_7_0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIL_PRESENT1[] = {
+	 { "RDIL_PRESENT_15_8", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR_PRESENT0[] = {
+	 { "RDIR_PRESENT_7_0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_RDIR_PRESENT1[] = {
+	 { "RDIR_PRESENT_15_8", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_CONFIG[] = {
+	 { "NUM_ACQ", 0, 2, &umr_bitfield_default },
+	 { "FORCE_MAX_ACQ", 3, 3, &umr_bitfield_default },
+	 { "RDI_INTERLEAVE", 4, 4, &umr_bitfield_default },
+	 { "RE_CALIB_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF0[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF1[] = {
+	 { "A", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF2[] = {
+	 { "B", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF3[] = {
+	 { "C", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_TEMP_CALC_COEFF4[] = {
+	 { "K", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_DEBUG0[] = {
+	 { "DEBUG_Z", 0, 10, &umr_bitfield_default },
+	 { "DEBUG_Z_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON0_DEBUG1[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL0_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL1_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL2_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL3_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL4_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL5_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL6_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL7_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL8_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL9_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL10_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL11_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL12_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL13_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL14_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL15_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR0_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR1_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR2_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR3_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR4_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR5_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR6_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR7_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR8_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR9_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR10_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR11_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR12_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR13_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR14_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR15_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_INT_DATA[] = {
+	 { "TEMP_Z_DATA", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL_PRESENT0[] = {
+	 { "RDIL_PRESENT_7_0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIL_PRESENT1[] = {
+	 { "RDIL_PRESENT_15_8", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR_PRESENT0[] = {
+	 { "RDIR_PRESENT_7_0", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_RDIR_PRESENT1[] = {
+	 { "RDIR_PRESENT_15_8", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_CONFIG[] = {
+	 { "NUM_ACQ", 0, 2, &umr_bitfield_default },
+	 { "FORCE_MAX_ACQ", 3, 3, &umr_bitfield_default },
+	 { "RDI_INTERLEAVE", 4, 4, &umr_bitfield_default },
+	 { "RE_CALIB_EN", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF0[] = {
+	 { "Z", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF1[] = {
+	 { "A", 0, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF2[] = {
+	 { "B", 0, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF3[] = {
+	 { "C", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_TEMP_CALC_COEFF4[] = {
+	 { "K", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_DEBUG0[] = {
+	 { "DEBUG_Z", 0, 10, &umr_bitfield_default },
+	 { "DEBUG_Z_EN", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTMON1_DEBUG1[] = {
+	 { "DEBUG_RDI", 0, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_REMOTE_START[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON0_REMOTE_END[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_REMOTE_START[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TMON1_REMOTE_END[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL0[] = {
+	 { "HaltPolling", 0, 0, &umr_bitfield_default },
+	 { "TMON0_PwrDn_Dis", 1, 1, &umr_bitfield_default },
+	 { "TMON1_PwrDn_Dis", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL1[] = {
+	 { "PwrDn_Limit_Temp", 0, 2, &umr_bitfield_default },
+	 { "PwrDn_DelaySlope", 3, 5, &umr_bitfield_default },
+	 { "PwrDn_MinDelay", 6, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL2[] = {
+	 { "PwrDn_MaxDlyMult", 0, 1, &umr_bitfield_default },
+	 { "PwrDn_NumSensors", 2, 3, &umr_bitfield_default },
+	 { "start_mission_polling", 4, 4, &umr_bitfield_default },
+	 { "short_stagger_count", 5, 5, &umr_bitfield_default },
+	 { "sbtsi_use_corrected", 6, 6, &umr_bitfield_default },
+	 { "csrslave_use_corrected", 7, 7, &umr_bitfield_default },
+	 { "smu_use_corrected", 8, 8, &umr_bitfield_default },
+	 { "skip_scale_correction", 11, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL3[] = {
+	 { "Global_TMAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL4[] = {
+	 { "Global_TMAX_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL5[] = {
+	 { "Global_TMIN", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL6[] = {
+	 { "Global_TMIN_ID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL7[] = {
+	 { "THERMID", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL8[] = {
+	 { "THERMMAX", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL9[] = {
+	 { "Tj_Max_TMON0", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL10[] = {
+	 { "TMON0_Tj_Max_RS_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL11[] = {
+	 { "Tj_Max_TMON1", 0, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL12[] = {
+	 { "TMON1_Tj_Max_RS_ID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL13[] = {
+	 { "PowerDownTmon0", 0, 0, &umr_bitfield_default },
+	 { "PowerDownTmon1", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_TCON_LOCAL14[] = {
+	 { "boot_done", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE0[] = {
+	 { "FUSE_TmonRsInterleave", 0, 0, &umr_bitfield_default },
+	 { "FUSE_TmonNumAcq", 1, 3, &umr_bitfield_default },
+	 { "FUSE_TmonForceMaxAcq", 4, 4, &umr_bitfield_default },
+	 { "FUSE_TmonClkDiv", 5, 6, &umr_bitfield_default },
+	 { "FUSE_TmonBGAdj1", 7, 14, &umr_bitfield_default },
+	 { "FUSE_TmonBGAdj0", 15, 22, &umr_bitfield_default },
+	 { "FUSE_TconZtValue", 23, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE1[] = {
+	 { "FUSE_TconZtValue", 0, 1, &umr_bitfield_default },
+	 { "FUSE_TconUseSecondary", 2, 3, &umr_bitfield_default },
+	 { "FUSE_TconTmpAdjLoRes", 4, 4, &umr_bitfield_default },
+	 { "FUSE_TconPwrUpStaggerTime", 5, 6, &umr_bitfield_default },
+	 { "FUSE_TconPwrDnTmpLmt", 7, 9, &umr_bitfield_default },
+	 { "FUSE_TconPwrDnNumSensors", 10, 11, &umr_bitfield_default },
+	 { "FUSE_TconPwrDnMinDelay", 12, 14, &umr_bitfield_default },
+	 { "FUSE_TconPwrDnMaxDelayMult", 15, 16, &umr_bitfield_default },
+	 { "FUSE_TconPwrDnDelaySlope", 17, 19, &umr_bitfield_default },
+	 { "FUSE_TconKValue", 20, 20, &umr_bitfield_default },
+	 { "FUSE_TconDtValue31", 21, 26, &umr_bitfield_default },
+	 { "FUSE_TconDtValue30", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE2[] = {
+	 { "FUSE_TconDtValue30", 0, 0, &umr_bitfield_default },
+	 { "FUSE_TconDtValue29", 1, 6, &umr_bitfield_default },
+	 { "FUSE_TconDtValue28", 7, 12, &umr_bitfield_default },
+	 { "FUSE_TconDtValue27", 13, 18, &umr_bitfield_default },
+	 { "FUSE_TconDtValue26", 19, 24, &umr_bitfield_default },
+	 { "FUSE_TconDtValue25", 25, 30, &umr_bitfield_default },
+	 { "FUSE_TconDtValue24", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE3[] = {
+	 { "FUSE_TconDtValue24", 0, 4, &umr_bitfield_default },
+	 { "FUSE_TconDtValue23", 5, 10, &umr_bitfield_default },
+	 { "FUSE_TconDtValue22", 11, 16, &umr_bitfield_default },
+	 { "FUSE_TconDtValue21", 17, 22, &umr_bitfield_default },
+	 { "FUSE_TconDtValue20", 23, 28, &umr_bitfield_default },
+	 { "FUSE_TconDtValue19", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE4[] = {
+	 { "FUSE_TconDtValue19", 0, 2, &umr_bitfield_default },
+	 { "FUSE_TconDtValue18", 3, 8, &umr_bitfield_default },
+	 { "FUSE_TconDtValue17", 9, 14, &umr_bitfield_default },
+	 { "FUSE_TconDtValue16", 15, 20, &umr_bitfield_default },
+	 { "FUSE_TconDtValue15", 21, 26, &umr_bitfield_default },
+	 { "FUSE_TconDtValue14", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE5[] = {
+	 { "FUSE_TconDtValue14", 0, 0, &umr_bitfield_default },
+	 { "FUSE_TconDtValue13", 1, 6, &umr_bitfield_default },
+	 { "FUSE_TconDtValue12", 7, 12, &umr_bitfield_default },
+	 { "FUSE_TconDtValue11", 13, 18, &umr_bitfield_default },
+	 { "FUSE_TconDtValue10", 19, 24, &umr_bitfield_default },
+	 { "FUSE_TconDtValue9", 25, 30, &umr_bitfield_default },
+	 { "FUSE_TconDtValue8", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE6[] = {
+	 { "FUSE_TconDtValue8", 0, 4, &umr_bitfield_default },
+	 { "FUSE_TconDtValue7", 5, 10, &umr_bitfield_default },
+	 { "FUSE_TconDtValue6", 11, 16, &umr_bitfield_default },
+	 { "FUSE_TconDtValue5", 17, 22, &umr_bitfield_default },
+	 { "FUSE_TconDtValue4", 23, 28, &umr_bitfield_default },
+	 { "FUSE_TconDtValue3", 29, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE7[] = {
+	 { "FUSE_TconDtValue3", 0, 2, &umr_bitfield_default },
+	 { "FUSE_TconDtValue2", 3, 8, &umr_bitfield_default },
+	 { "FUSE_TconDtValue1", 9, 14, &umr_bitfield_default },
+	 { "FUSE_TconDtValue0", 15, 20, &umr_bitfield_default },
+	 { "FUSE_TconCtValue1", 21, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE8[] = {
+	 { "FUSE_TconCtValue0", 0, 10, &umr_bitfield_default },
+	 { "FUSE_TconBtValue", 11, 16, &umr_bitfield_default },
+	 { "FUSE_TconBootDelay", 17, 18, &umr_bitfield_default },
+	 { "FUSE_TconAtValue1", 19, 30, &umr_bitfield_default },
+	 { "FUSE_TconAtValue0", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE9[] = {
+	 { "FUSE_TconAtValue0", 0, 10, &umr_bitfield_default },
+	 { "FUSE_ThermTripLimit", 11, 18, &umr_bitfield_default },
+	 { "FUSE_ThermTripEn", 19, 19, &umr_bitfield_default },
+	 { "FUSE_HtcTmpLmt", 20, 26, &umr_bitfield_default },
+	 { "FUSE_HtcMsrLock", 27, 27, &umr_bitfield_default },
+	 { "FUSE_HtcHystLmt", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE10[] = {
+	 { "FUSE_HtcDis", 0, 0, &umr_bitfield_default },
+	 { "FUSE_HtcClkInact", 1, 3, &umr_bitfield_default },
+	 { "FUSE_HtcClkAct", 4, 6, &umr_bitfield_default },
+	 { "FUSE_UnusedBits", 7, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE11[] = {
+	 { "PA_SPARE", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixTHM_FUSE12[] = {
+	 { "FusesValid", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield ixGC_CAC_OVRD_CU[] = {
+	 { "OVRRD_SELECT", 0, 15, &umr_bitfield_default },
+	 { "OVRRD_VALUE", 16, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/smu80_regs.i b/src/lib/ip/smu80_regs.i
new file mode 100644
index 0000000..5f0df4c
--- /dev/null
+++ b/src/lib/ip/smu80_regs.i
@@ -0,0 +1,635 @@
+	{ "mmMP_SMUIF0_MP0PUB_IND_INDEX", REG_MMIO, 0x180, NULL, 0, 0, 0 },
+	{ "mmPWRHW_SMC_IND_INDEX", REG_MMIO, 0x180, &mmPWRHW_SMC_IND_INDEX[0], sizeof(mmPWRHW_SMC_IND_INDEX)/sizeof(mmPWRHW_SMC_IND_INDEX[0]), 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_0", REG_MMIO, 0x180, &mmMP0PUB_IND_INDEX_0[0], sizeof(mmMP0PUB_IND_INDEX_0)/sizeof(mmMP0PUB_IND_INDEX_0[0]), 0, 0 },
+	{ "mmMP0PUB_IND_INDEX", REG_MMIO, 0x180, &mmMP0PUB_IND_INDEX[0], sizeof(mmMP0PUB_IND_INDEX)/sizeof(mmMP0PUB_IND_INDEX[0]), 0, 0 },
+	{ "mmMP_SMUIF0_MP0PUB_IND_DATA", REG_MMIO, 0x181, NULL, 0, 0, 0 },
+	{ "mmPWRHW_SMC_IND_DATA", REG_MMIO, 0x181, &mmPWRHW_SMC_IND_DATA[0], sizeof(mmPWRHW_SMC_IND_DATA)/sizeof(mmPWRHW_SMC_IND_DATA[0]), 0, 0 },
+	{ "mmMP0PUB_IND_DATA_0", REG_MMIO, 0x181, &mmMP0PUB_IND_DATA_0[0], sizeof(mmMP0PUB_IND_DATA_0)/sizeof(mmMP0PUB_IND_DATA_0[0]), 0, 0 },
+	{ "mmMP0PUB_IND_DATA", REG_MMIO, 0x181, &mmMP0PUB_IND_DATA[0], sizeof(mmMP0PUB_IND_DATA)/sizeof(mmMP0PUB_IND_DATA[0]), 0, 0 },
+	{ "mmMP_SMUIF1_MP0PUB_IND_INDEX", REG_MMIO, 0x182, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_1", REG_MMIO, 0x182, &mmMP0PUB_IND_INDEX_1[0], sizeof(mmMP0PUB_IND_INDEX_1)/sizeof(mmMP0PUB_IND_INDEX_1[0]), 0, 0 },
+	{ "mmMP_SMUIF1_MP0PUB_IND_DATA", REG_MMIO, 0x183, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_1", REG_MMIO, 0x183, &mmMP0PUB_IND_DATA_1[0], sizeof(mmMP0PUB_IND_DATA_1)/sizeof(mmMP0PUB_IND_DATA_1[0]), 0, 0 },
+	{ "mmMP_SMUIF2_MP0PUB_IND_INDEX", REG_MMIO, 0x184, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_2", REG_MMIO, 0x184, &mmMP0PUB_IND_INDEX_2[0], sizeof(mmMP0PUB_IND_INDEX_2)/sizeof(mmMP0PUB_IND_INDEX_2[0]), 0, 0 },
+	{ "mmMP_SMUIF2_MP0PUB_IND_DATA", REG_MMIO, 0x185, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_2", REG_MMIO, 0x185, &mmMP0PUB_IND_DATA_2[0], sizeof(mmMP0PUB_IND_DATA_2)/sizeof(mmMP0PUB_IND_DATA_2[0]), 0, 0 },
+	{ "mmMP_SMUIF3_MP0PUB_IND_INDEX", REG_MMIO, 0x186, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_3", REG_MMIO, 0x186, &mmMP0PUB_IND_INDEX_3[0], sizeof(mmMP0PUB_IND_INDEX_3)/sizeof(mmMP0PUB_IND_INDEX_3[0]), 0, 0 },
+	{ "mmMP_SMUIF3_MP0PUB_IND_DATA", REG_MMIO, 0x187, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_3", REG_MMIO, 0x187, &mmMP0PUB_IND_DATA_3[0], sizeof(mmMP0PUB_IND_DATA_3)/sizeof(mmMP0PUB_IND_DATA_3[0]), 0, 0 },
+	{ "mmMP_SMUIF4_MP0PUB_IND_INDEX", REG_MMIO, 0x188, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_4", REG_MMIO, 0x188, &mmMP0PUB_IND_INDEX_4[0], sizeof(mmMP0PUB_IND_INDEX_4)/sizeof(mmMP0PUB_IND_INDEX_4[0]), 0, 0 },
+	{ "mmMP_SMUIF4_MP0PUB_IND_DATA", REG_MMIO, 0x189, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_4", REG_MMIO, 0x189, &mmMP0PUB_IND_DATA_4[0], sizeof(mmMP0PUB_IND_DATA_4)/sizeof(mmMP0PUB_IND_DATA_4[0]), 0, 0 },
+	{ "mmMP_SMUIF5_MP0PUB_IND_INDEX", REG_MMIO, 0x18a, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_5", REG_MMIO, 0x18a, &mmMP0PUB_IND_INDEX_5[0], sizeof(mmMP0PUB_IND_INDEX_5)/sizeof(mmMP0PUB_IND_INDEX_5[0]), 0, 0 },
+	{ "mmMP_SMUIF5_MP0PUB_IND_DATA", REG_MMIO, 0x18b, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_5", REG_MMIO, 0x18b, &mmMP0PUB_IND_DATA_5[0], sizeof(mmMP0PUB_IND_DATA_5)/sizeof(mmMP0PUB_IND_DATA_5[0]), 0, 0 },
+	{ "mmMP_SMUIF6_MP0PUB_IND_INDEX", REG_MMIO, 0x18c, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_6", REG_MMIO, 0x18c, &mmMP0PUB_IND_INDEX_6[0], sizeof(mmMP0PUB_IND_INDEX_6)/sizeof(mmMP0PUB_IND_INDEX_6[0]), 0, 0 },
+	{ "mmMP_SMUIF6_MP0PUB_IND_DATA", REG_MMIO, 0x18d, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_6", REG_MMIO, 0x18d, &mmMP0PUB_IND_DATA_6[0], sizeof(mmMP0PUB_IND_DATA_6)/sizeof(mmMP0PUB_IND_DATA_6[0]), 0, 0 },
+	{ "mmMP_SMUIF7_MP0PUB_IND_INDEX", REG_MMIO, 0x18e, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_7", REG_MMIO, 0x18e, &mmMP0PUB_IND_INDEX_7[0], sizeof(mmMP0PUB_IND_INDEX_7)/sizeof(mmMP0PUB_IND_INDEX_7[0]), 0, 0 },
+	{ "mmMP_SMUIF7_MP0PUB_IND_DATA", REG_MMIO, 0x18f, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_7", REG_MMIO, 0x18f, &mmMP0PUB_IND_DATA_7[0], sizeof(mmMP0PUB_IND_DATA_7)/sizeof(mmMP0PUB_IND_DATA_7[0]), 0, 0 },
+	{ "mmMP_SMUIF8_MP0PUB_IND_INDEX", REG_MMIO, 0x190, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_8", REG_MMIO, 0x190, &mmMP0PUB_IND_INDEX_8[0], sizeof(mmMP0PUB_IND_INDEX_8)/sizeof(mmMP0PUB_IND_INDEX_8[0]), 0, 0 },
+	{ "mmMP_SMUIF8_MP0PUB_IND_DATA", REG_MMIO, 0x191, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_8", REG_MMIO, 0x191, &mmMP0PUB_IND_DATA_8[0], sizeof(mmMP0PUB_IND_DATA_8)/sizeof(mmMP0PUB_IND_DATA_8[0]), 0, 0 },
+	{ "mmMP_SMUIF9_MP0PUB_IND_INDEX", REG_MMIO, 0x192, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_9", REG_MMIO, 0x192, &mmMP0PUB_IND_INDEX_9[0], sizeof(mmMP0PUB_IND_INDEX_9)/sizeof(mmMP0PUB_IND_INDEX_9[0]), 0, 0 },
+	{ "mmMP_SMUIF9_MP0PUB_IND_DATA", REG_MMIO, 0x193, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_9", REG_MMIO, 0x193, &mmMP0PUB_IND_DATA_9[0], sizeof(mmMP0PUB_IND_DATA_9)/sizeof(mmMP0PUB_IND_DATA_9[0]), 0, 0 },
+	{ "mmMP_SMUIF10_MP0PUB_IND_INDEX", REG_MMIO, 0x194, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_10", REG_MMIO, 0x194, &mmMP0PUB_IND_INDEX_10[0], sizeof(mmMP0PUB_IND_INDEX_10)/sizeof(mmMP0PUB_IND_INDEX_10[0]), 0, 0 },
+	{ "mmMP_SMUIF10_MP0PUB_IND_DATA", REG_MMIO, 0x195, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_10", REG_MMIO, 0x195, &mmMP0PUB_IND_DATA_10[0], sizeof(mmMP0PUB_IND_DATA_10)/sizeof(mmMP0PUB_IND_DATA_10[0]), 0, 0 },
+	{ "mmMP_SMUIF11_MP0PUB_IND_INDEX", REG_MMIO, 0x196, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_11", REG_MMIO, 0x196, &mmMP0PUB_IND_INDEX_11[0], sizeof(mmMP0PUB_IND_INDEX_11)/sizeof(mmMP0PUB_IND_INDEX_11[0]), 0, 0 },
+	{ "mmMP_SMUIF11_MP0PUB_IND_DATA", REG_MMIO, 0x197, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_11", REG_MMIO, 0x197, &mmMP0PUB_IND_DATA_11[0], sizeof(mmMP0PUB_IND_DATA_11)/sizeof(mmMP0PUB_IND_DATA_11[0]), 0, 0 },
+	{ "mmMP_SMUIF12_MP0PUB_IND_INDEX", REG_MMIO, 0x198, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_12", REG_MMIO, 0x198, &mmMP0PUB_IND_INDEX_12[0], sizeof(mmMP0PUB_IND_INDEX_12)/sizeof(mmMP0PUB_IND_INDEX_12[0]), 0, 0 },
+	{ "mmMP_SMUIF12_MP0PUB_IND_DATA", REG_MMIO, 0x199, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_12", REG_MMIO, 0x199, &mmMP0PUB_IND_DATA_12[0], sizeof(mmMP0PUB_IND_DATA_12)/sizeof(mmMP0PUB_IND_DATA_12[0]), 0, 0 },
+	{ "mmMP_SMUIF13_MP0PUB_IND_INDEX", REG_MMIO, 0x19a, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_13", REG_MMIO, 0x19a, &mmMP0PUB_IND_INDEX_13[0], sizeof(mmMP0PUB_IND_INDEX_13)/sizeof(mmMP0PUB_IND_INDEX_13[0]), 0, 0 },
+	{ "mmMP_SMUIF13_MP0PUB_IND_DATA", REG_MMIO, 0x19b, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_13", REG_MMIO, 0x19b, &mmMP0PUB_IND_DATA_13[0], sizeof(mmMP0PUB_IND_DATA_13)/sizeof(mmMP0PUB_IND_DATA_13[0]), 0, 0 },
+	{ "mmMP_SMUIF14_MP0PUB_IND_INDEX", REG_MMIO, 0x19c, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_14", REG_MMIO, 0x19c, &mmMP0PUB_IND_INDEX_14[0], sizeof(mmMP0PUB_IND_INDEX_14)/sizeof(mmMP0PUB_IND_INDEX_14[0]), 0, 0 },
+	{ "mmMP_SMUIF14_MP0PUB_IND_DATA", REG_MMIO, 0x19d, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_14", REG_MMIO, 0x19d, &mmMP0PUB_IND_DATA_14[0], sizeof(mmMP0PUB_IND_DATA_14)/sizeof(mmMP0PUB_IND_DATA_14[0]), 0, 0 },
+	{ "mmMP_SMUIF15_MP0PUB_IND_INDEX", REG_MMIO, 0x19e, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_INDEX_15", REG_MMIO, 0x19e, &mmMP0PUB_IND_INDEX_15[0], sizeof(mmMP0PUB_IND_INDEX_15)/sizeof(mmMP0PUB_IND_INDEX_15[0]), 0, 0 },
+	{ "mmMP_SMUIF15_MP0PUB_IND_DATA", REG_MMIO, 0x19f, NULL, 0, 0, 0 },
+	{ "mmMP0PUB_IND_DATA_15", REG_MMIO, 0x19f, &mmMP0PUB_IND_DATA_15[0], sizeof(mmMP0PUB_IND_DATA_15)/sizeof(mmMP0PUB_IND_DATA_15[0]), 0, 0 },
+	{ "mmMP0_IND_ACCESS_CNTL", REG_MMIO, 0x1a0, &mmMP0_IND_ACCESS_CNTL[0], sizeof(mmMP0_IND_ACCESS_CNTL)/sizeof(mmMP0_IND_ACCESS_CNTL[0]), 0, 0 },
+	{ "mmMP0_MSP_MESSAGE_0", REG_MMIO, 0x1a1, &mmMP0_MSP_MESSAGE_0[0], sizeof(mmMP0_MSP_MESSAGE_0)/sizeof(mmMP0_MSP_MESSAGE_0[0]), 0, 0 },
+	{ "mmMP0_MSP_MESSAGE_1", REG_MMIO, 0x1a2, &mmMP0_MSP_MESSAGE_1[0], sizeof(mmMP0_MSP_MESSAGE_1)/sizeof(mmMP0_MSP_MESSAGE_1[0]), 0, 0 },
+	{ "mmMP0_MSP_MESSAGE_2", REG_MMIO, 0x1a3, &mmMP0_MSP_MESSAGE_2[0], sizeof(mmMP0_MSP_MESSAGE_2)/sizeof(mmMP0_MSP_MESSAGE_2[0]), 0, 0 },
+	{ "mmMP0_MSP_MESSAGE_3", REG_MMIO, 0x1a4, &mmMP0_MSP_MESSAGE_3[0], sizeof(mmMP0_MSP_MESSAGE_3)/sizeof(mmMP0_MSP_MESSAGE_3[0]), 0, 0 },
+	{ "mmMP0_MSP_MESSAGE_4", REG_MMIO, 0x1a5, &mmMP0_MSP_MESSAGE_4[0], sizeof(mmMP0_MSP_MESSAGE_4)/sizeof(mmMP0_MSP_MESSAGE_4[0]), 0, 0 },
+	{ "mmMP0_MSP_MESSAGE_5", REG_MMIO, 0x1a6, &mmMP0_MSP_MESSAGE_5[0], sizeof(mmMP0_MSP_MESSAGE_5)/sizeof(mmMP0_MSP_MESSAGE_5[0]), 0, 0 },
+	{ "mmMP0_MSP_MESSAGE_6", REG_MMIO, 0x1a7, &mmMP0_MSP_MESSAGE_6[0], sizeof(mmMP0_MSP_MESSAGE_6)/sizeof(mmMP0_MSP_MESSAGE_6[0]), 0, 0 },
+	{ "mmMP0_MSP_MESSAGE_7", REG_MMIO, 0x1a8, &mmMP0_MSP_MESSAGE_7[0], sizeof(mmMP0_MSP_MESSAGE_7)/sizeof(mmMP0_MSP_MESSAGE_7[0]), 0, 0 },
+	{ "mmSAM_IH_EXT_ERR_INTR", REG_MMIO, 0x1a9, &mmSAM_IH_EXT_ERR_INTR[0], sizeof(mmSAM_IH_EXT_ERR_INTR)/sizeof(mmSAM_IH_EXT_ERR_INTR[0]), 0, 0 },
+	{ "mmSAM_IH_EXT_ERR_INTR_STATUS", REG_MMIO, 0x1aa, &mmSAM_IH_EXT_ERR_INTR_STATUS[0], sizeof(mmSAM_IH_EXT_ERR_INTR_STATUS)/sizeof(mmSAM_IH_EXT_ERR_INTR_STATUS[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER0_CTRL0", REG_MMIO, 0x1ab, &mmMP0_DISP_TIMER0_CTRL0[0], sizeof(mmMP0_DISP_TIMER0_CTRL0)/sizeof(mmMP0_DISP_TIMER0_CTRL0[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER0_CTRL1", REG_MMIO, 0x1ac, &mmMP0_DISP_TIMER0_CTRL1[0], sizeof(mmMP0_DISP_TIMER0_CTRL1)/sizeof(mmMP0_DISP_TIMER0_CTRL1[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER0_CMP_AUTOINC", REG_MMIO, 0x1ad, &mmMP0_DISP_TIMER0_CMP_AUTOINC[0], sizeof(mmMP0_DISP_TIMER0_CMP_AUTOINC)/sizeof(mmMP0_DISP_TIMER0_CMP_AUTOINC[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER0_INTEN", REG_MMIO, 0x1ae, &mmMP0_DISP_TIMER0_INTEN[0], sizeof(mmMP0_DISP_TIMER0_INTEN)/sizeof(mmMP0_DISP_TIMER0_INTEN[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER0_OCMP_0_0", REG_MMIO, 0x1af, &mmMP0_DISP_TIMER0_OCMP_0_0[0], sizeof(mmMP0_DISP_TIMER0_OCMP_0_0)/sizeof(mmMP0_DISP_TIMER0_OCMP_0_0[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER0_OCMP_0_1", REG_MMIO, 0x1b0, &mmMP0_DISP_TIMER0_OCMP_0_1[0], sizeof(mmMP0_DISP_TIMER0_OCMP_0_1)/sizeof(mmMP0_DISP_TIMER0_OCMP_0_1[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER0_CNT", REG_MMIO, 0x1b1, &mmMP0_DISP_TIMER0_CNT[0], sizeof(mmMP0_DISP_TIMER0_CNT)/sizeof(mmMP0_DISP_TIMER0_CNT[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER1_CTRL0", REG_MMIO, 0x1b2, &mmMP0_DISP_TIMER1_CTRL0[0], sizeof(mmMP0_DISP_TIMER1_CTRL0)/sizeof(mmMP0_DISP_TIMER1_CTRL0[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER1_CTRL1", REG_MMIO, 0x1b3, &mmMP0_DISP_TIMER1_CTRL1[0], sizeof(mmMP0_DISP_TIMER1_CTRL1)/sizeof(mmMP0_DISP_TIMER1_CTRL1[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER1_CMP_AUTOINC", REG_MMIO, 0x1b4, &mmMP0_DISP_TIMER1_CMP_AUTOINC[0], sizeof(mmMP0_DISP_TIMER1_CMP_AUTOINC)/sizeof(mmMP0_DISP_TIMER1_CMP_AUTOINC[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER1_INTEN", REG_MMIO, 0x1b5, &mmMP0_DISP_TIMER1_INTEN[0], sizeof(mmMP0_DISP_TIMER1_INTEN)/sizeof(mmMP0_DISP_TIMER1_INTEN[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER1_OCMP_0_0", REG_MMIO, 0x1b6, &mmMP0_DISP_TIMER1_OCMP_0_0[0], sizeof(mmMP0_DISP_TIMER1_OCMP_0_0)/sizeof(mmMP0_DISP_TIMER1_OCMP_0_0[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER1_OCMP_0_1", REG_MMIO, 0x1b7, &mmMP0_DISP_TIMER1_OCMP_0_1[0], sizeof(mmMP0_DISP_TIMER1_OCMP_0_1)/sizeof(mmMP0_DISP_TIMER1_OCMP_0_1[0]), 0, 0 },
+	{ "mmMP0_DISP_TIMER1_CNT", REG_MMIO, 0x1b8, &mmMP0_DISP_TIMER1_CNT[0], sizeof(mmMP0_DISP_TIMER1_CNT)/sizeof(mmMP0_DISP_TIMER1_CNT[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_0", REG_MMIO, 0x1c0, &mmSMU_MP1_SRBM2P_MSG_0[0], sizeof(mmSMU_MP1_SRBM2P_MSG_0)/sizeof(mmSMU_MP1_SRBM2P_MSG_0[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_1", REG_MMIO, 0x1c1, &mmSMU_MP1_SRBM2P_MSG_1[0], sizeof(mmSMU_MP1_SRBM2P_MSG_1)/sizeof(mmSMU_MP1_SRBM2P_MSG_1[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_2", REG_MMIO, 0x1c2, &mmSMU_MP1_SRBM2P_MSG_2[0], sizeof(mmSMU_MP1_SRBM2P_MSG_2)/sizeof(mmSMU_MP1_SRBM2P_MSG_2[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_3", REG_MMIO, 0x1c3, &mmSMU_MP1_SRBM2P_MSG_3[0], sizeof(mmSMU_MP1_SRBM2P_MSG_3)/sizeof(mmSMU_MP1_SRBM2P_MSG_3[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_4", REG_MMIO, 0x1c4, &mmSMU_MP1_SRBM2P_MSG_4[0], sizeof(mmSMU_MP1_SRBM2P_MSG_4)/sizeof(mmSMU_MP1_SRBM2P_MSG_4[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_5", REG_MMIO, 0x1c5, &mmSMU_MP1_SRBM2P_MSG_5[0], sizeof(mmSMU_MP1_SRBM2P_MSG_5)/sizeof(mmSMU_MP1_SRBM2P_MSG_5[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_6", REG_MMIO, 0x1c6, &mmSMU_MP1_SRBM2P_MSG_6[0], sizeof(mmSMU_MP1_SRBM2P_MSG_6)/sizeof(mmSMU_MP1_SRBM2P_MSG_6[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_7", REG_MMIO, 0x1c7, &mmSMU_MP1_SRBM2P_MSG_7[0], sizeof(mmSMU_MP1_SRBM2P_MSG_7)/sizeof(mmSMU_MP1_SRBM2P_MSG_7[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_8", REG_MMIO, 0x1c8, &mmSMU_MP1_SRBM2P_MSG_8[0], sizeof(mmSMU_MP1_SRBM2P_MSG_8)/sizeof(mmSMU_MP1_SRBM2P_MSG_8[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_9", REG_MMIO, 0x1c9, &mmSMU_MP1_SRBM2P_MSG_9[0], sizeof(mmSMU_MP1_SRBM2P_MSG_9)/sizeof(mmSMU_MP1_SRBM2P_MSG_9[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_10", REG_MMIO, 0x1ca, &mmSMU_MP1_SRBM2P_MSG_10[0], sizeof(mmSMU_MP1_SRBM2P_MSG_10)/sizeof(mmSMU_MP1_SRBM2P_MSG_10[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_11", REG_MMIO, 0x1cb, &mmSMU_MP1_SRBM2P_MSG_11[0], sizeof(mmSMU_MP1_SRBM2P_MSG_11)/sizeof(mmSMU_MP1_SRBM2P_MSG_11[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_12", REG_MMIO, 0x1cc, &mmSMU_MP1_SRBM2P_MSG_12[0], sizeof(mmSMU_MP1_SRBM2P_MSG_12)/sizeof(mmSMU_MP1_SRBM2P_MSG_12[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_13", REG_MMIO, 0x1cd, &mmSMU_MP1_SRBM2P_MSG_13[0], sizeof(mmSMU_MP1_SRBM2P_MSG_13)/sizeof(mmSMU_MP1_SRBM2P_MSG_13[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_14", REG_MMIO, 0x1ce, &mmSMU_MP1_SRBM2P_MSG_14[0], sizeof(mmSMU_MP1_SRBM2P_MSG_14)/sizeof(mmSMU_MP1_SRBM2P_MSG_14[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_MSG_15", REG_MMIO, 0x1cf, &mmSMU_MP1_SRBM2P_MSG_15[0], sizeof(mmSMU_MP1_SRBM2P_MSG_15)/sizeof(mmSMU_MP1_SRBM2P_MSG_15[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_0", REG_MMIO, 0x1d0, &mmSMU_MP1_SRBM2P_RESP_0[0], sizeof(mmSMU_MP1_SRBM2P_RESP_0)/sizeof(mmSMU_MP1_SRBM2P_RESP_0[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_1", REG_MMIO, 0x1d1, &mmSMU_MP1_SRBM2P_RESP_1[0], sizeof(mmSMU_MP1_SRBM2P_RESP_1)/sizeof(mmSMU_MP1_SRBM2P_RESP_1[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_2", REG_MMIO, 0x1d2, &mmSMU_MP1_SRBM2P_RESP_2[0], sizeof(mmSMU_MP1_SRBM2P_RESP_2)/sizeof(mmSMU_MP1_SRBM2P_RESP_2[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_3", REG_MMIO, 0x1d3, &mmSMU_MP1_SRBM2P_RESP_3[0], sizeof(mmSMU_MP1_SRBM2P_RESP_3)/sizeof(mmSMU_MP1_SRBM2P_RESP_3[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_4", REG_MMIO, 0x1d4, &mmSMU_MP1_SRBM2P_RESP_4[0], sizeof(mmSMU_MP1_SRBM2P_RESP_4)/sizeof(mmSMU_MP1_SRBM2P_RESP_4[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_5", REG_MMIO, 0x1d5, &mmSMU_MP1_SRBM2P_RESP_5[0], sizeof(mmSMU_MP1_SRBM2P_RESP_5)/sizeof(mmSMU_MP1_SRBM2P_RESP_5[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_6", REG_MMIO, 0x1d6, &mmSMU_MP1_SRBM2P_RESP_6[0], sizeof(mmSMU_MP1_SRBM2P_RESP_6)/sizeof(mmSMU_MP1_SRBM2P_RESP_6[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_7", REG_MMIO, 0x1d7, &mmSMU_MP1_SRBM2P_RESP_7[0], sizeof(mmSMU_MP1_SRBM2P_RESP_7)/sizeof(mmSMU_MP1_SRBM2P_RESP_7[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_8", REG_MMIO, 0x1d8, &mmSMU_MP1_SRBM2P_RESP_8[0], sizeof(mmSMU_MP1_SRBM2P_RESP_8)/sizeof(mmSMU_MP1_SRBM2P_RESP_8[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_9", REG_MMIO, 0x1d9, &mmSMU_MP1_SRBM2P_RESP_9[0], sizeof(mmSMU_MP1_SRBM2P_RESP_9)/sizeof(mmSMU_MP1_SRBM2P_RESP_9[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_10", REG_MMIO, 0x1da, &mmSMU_MP1_SRBM2P_RESP_10[0], sizeof(mmSMU_MP1_SRBM2P_RESP_10)/sizeof(mmSMU_MP1_SRBM2P_RESP_10[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_11", REG_MMIO, 0x1db, &mmSMU_MP1_SRBM2P_RESP_11[0], sizeof(mmSMU_MP1_SRBM2P_RESP_11)/sizeof(mmSMU_MP1_SRBM2P_RESP_11[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_12", REG_MMIO, 0x1dc, &mmSMU_MP1_SRBM2P_RESP_12[0], sizeof(mmSMU_MP1_SRBM2P_RESP_12)/sizeof(mmSMU_MP1_SRBM2P_RESP_12[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_13", REG_MMIO, 0x1dd, &mmSMU_MP1_SRBM2P_RESP_13[0], sizeof(mmSMU_MP1_SRBM2P_RESP_13)/sizeof(mmSMU_MP1_SRBM2P_RESP_13[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_14", REG_MMIO, 0x1de, &mmSMU_MP1_SRBM2P_RESP_14[0], sizeof(mmSMU_MP1_SRBM2P_RESP_14)/sizeof(mmSMU_MP1_SRBM2P_RESP_14[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_RESP_15", REG_MMIO, 0x1df, &mmSMU_MP1_SRBM2P_RESP_15[0], sizeof(mmSMU_MP1_SRBM2P_RESP_15)/sizeof(mmSMU_MP1_SRBM2P_RESP_15[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_0", REG_MMIO, 0x1e0, &mmSMU_MP1_SRBM2P_ARG_0[0], sizeof(mmSMU_MP1_SRBM2P_ARG_0)/sizeof(mmSMU_MP1_SRBM2P_ARG_0[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_1", REG_MMIO, 0x1e1, &mmSMU_MP1_SRBM2P_ARG_1[0], sizeof(mmSMU_MP1_SRBM2P_ARG_1)/sizeof(mmSMU_MP1_SRBM2P_ARG_1[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_2", REG_MMIO, 0x1e2, &mmSMU_MP1_SRBM2P_ARG_2[0], sizeof(mmSMU_MP1_SRBM2P_ARG_2)/sizeof(mmSMU_MP1_SRBM2P_ARG_2[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_3", REG_MMIO, 0x1e3, &mmSMU_MP1_SRBM2P_ARG_3[0], sizeof(mmSMU_MP1_SRBM2P_ARG_3)/sizeof(mmSMU_MP1_SRBM2P_ARG_3[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_4", REG_MMIO, 0x1e4, &mmSMU_MP1_SRBM2P_ARG_4[0], sizeof(mmSMU_MP1_SRBM2P_ARG_4)/sizeof(mmSMU_MP1_SRBM2P_ARG_4[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_5", REG_MMIO, 0x1e5, &mmSMU_MP1_SRBM2P_ARG_5[0], sizeof(mmSMU_MP1_SRBM2P_ARG_5)/sizeof(mmSMU_MP1_SRBM2P_ARG_5[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_6", REG_MMIO, 0x1e6, &mmSMU_MP1_SRBM2P_ARG_6[0], sizeof(mmSMU_MP1_SRBM2P_ARG_6)/sizeof(mmSMU_MP1_SRBM2P_ARG_6[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_7", REG_MMIO, 0x1e7, &mmSMU_MP1_SRBM2P_ARG_7[0], sizeof(mmSMU_MP1_SRBM2P_ARG_7)/sizeof(mmSMU_MP1_SRBM2P_ARG_7[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_8", REG_MMIO, 0x1e8, &mmSMU_MP1_SRBM2P_ARG_8[0], sizeof(mmSMU_MP1_SRBM2P_ARG_8)/sizeof(mmSMU_MP1_SRBM2P_ARG_8[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_9", REG_MMIO, 0x1e9, &mmSMU_MP1_SRBM2P_ARG_9[0], sizeof(mmSMU_MP1_SRBM2P_ARG_9)/sizeof(mmSMU_MP1_SRBM2P_ARG_9[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_10", REG_MMIO, 0x1ea, &mmSMU_MP1_SRBM2P_ARG_10[0], sizeof(mmSMU_MP1_SRBM2P_ARG_10)/sizeof(mmSMU_MP1_SRBM2P_ARG_10[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_11", REG_MMIO, 0x1eb, &mmSMU_MP1_SRBM2P_ARG_11[0], sizeof(mmSMU_MP1_SRBM2P_ARG_11)/sizeof(mmSMU_MP1_SRBM2P_ARG_11[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_12", REG_MMIO, 0x1ec, &mmSMU_MP1_SRBM2P_ARG_12[0], sizeof(mmSMU_MP1_SRBM2P_ARG_12)/sizeof(mmSMU_MP1_SRBM2P_ARG_12[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_13", REG_MMIO, 0x1ed, &mmSMU_MP1_SRBM2P_ARG_13[0], sizeof(mmSMU_MP1_SRBM2P_ARG_13)/sizeof(mmSMU_MP1_SRBM2P_ARG_13[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_14", REG_MMIO, 0x1ee, &mmSMU_MP1_SRBM2P_ARG_14[0], sizeof(mmSMU_MP1_SRBM2P_ARG_14)/sizeof(mmSMU_MP1_SRBM2P_ARG_14[0]), 0, 0 },
+	{ "mmSMU_MP1_SRBM2P_ARG_15", REG_MMIO, 0x1ef, &mmSMU_MP1_SRBM2P_ARG_15[0], sizeof(mmSMU_MP1_SRBM2P_ARG_15)/sizeof(mmSMU_MP1_SRBM2P_ARG_15[0]), 0, 0 },
+	{ "mmSMU_MP1_ACP2MP_RESP", REG_MMIO, 0x1f0, &mmSMU_MP1_ACP2MP_RESP[0], sizeof(mmSMU_MP1_ACP2MP_RESP)/sizeof(mmSMU_MP1_ACP2MP_RESP[0]), 0, 0 },
+	{ "mmSMU_MP1_DC2MP_RESP", REG_MMIO, 0x1f1, &mmSMU_MP1_DC2MP_RESP[0], sizeof(mmSMU_MP1_DC2MP_RESP)/sizeof(mmSMU_MP1_DC2MP_RESP[0]), 0, 0 },
+	{ "mmSMU_MP1_UVD2MP_RESP", REG_MMIO, 0x1f2, &mmSMU_MP1_UVD2MP_RESP[0], sizeof(mmSMU_MP1_UVD2MP_RESP)/sizeof(mmSMU_MP1_UVD2MP_RESP[0]), 0, 0 },
+	{ "mmSMU_MP1_VCE2MP_RESP", REG_MMIO, 0x1f3, &mmSMU_MP1_VCE2MP_RESP[0], sizeof(mmSMU_MP1_VCE2MP_RESP)/sizeof(mmSMU_MP1_VCE2MP_RESP[0]), 0, 0 },
+	{ "mmSMU_MP1_RLC2MP_RESP", REG_MMIO, 0x1f4, &mmSMU_MP1_RLC2MP_RESP[0], sizeof(mmSMU_MP1_RLC2MP_RESP)/sizeof(mmSMU_MP1_RLC2MP_RESP[0]), 0, 0 },
+	{ "mmMP_FPS_CNT", REG_MMIO, 0x1f5, &mmMP_FPS_CNT[0], sizeof(mmMP_FPS_CNT)/sizeof(mmMP_FPS_CNT[0]), 0, 0 },
+	{ "mmSMU_DISP0_TIMER_INT_CONTROL", REG_MMIO, 0x1f6, &mmSMU_DISP0_TIMER_INT_CONTROL[0], sizeof(mmSMU_DISP0_TIMER_INT_CONTROL)/sizeof(mmSMU_DISP0_TIMER_INT_CONTROL[0]), 0, 0 },
+	{ "mmSMU_DISP1_TIMER_INT_CONTROL", REG_MMIO, 0x1f7, &mmSMU_DISP1_TIMER_INT_CONTROL[0], sizeof(mmSMU_DISP1_TIMER_INT_CONTROL)/sizeof(mmSMU_DISP1_TIMER_INT_CONTROL[0]), 0, 0 },
+	{ "mmSMU_SRBM_CONFIG", REG_MMIO, 0x1f8, &mmSMU_SRBM_CONFIG[0], sizeof(mmSMU_SRBM_CONFIG)/sizeof(mmSMU_SRBM_CONFIG[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_0", REG_SMC, 0x32, &ixGC_CAC_WEIGHT_CU_0[0], sizeof(ixGC_CAC_WEIGHT_CU_0)/sizeof(ixGC_CAC_WEIGHT_CU_0[0]), 0, 0 },
+	{ "mmGC_CAC_LKG_AGGR_LOWER", REG_MMIO, 0x3294, &mmGC_CAC_LKG_AGGR_LOWER[0], sizeof(mmGC_CAC_LKG_AGGR_LOWER)/sizeof(mmGC_CAC_LKG_AGGR_LOWER[0]), 0, 0 },
+	{ "mmGC_CAC_LKG_AGGR_UPPER", REG_MMIO, 0x3295, &mmGC_CAC_LKG_AGGR_UPPER[0], sizeof(mmGC_CAC_LKG_AGGR_UPPER)/sizeof(mmGC_CAC_LKG_AGGR_UPPER[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_1", REG_SMC, 0x33, &ixGC_CAC_WEIGHT_CU_1[0], sizeof(ixGC_CAC_WEIGHT_CU_1)/sizeof(ixGC_CAC_WEIGHT_CU_1[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_2", REG_SMC, 0x34, &ixGC_CAC_WEIGHT_CU_2[0], sizeof(ixGC_CAC_WEIGHT_CU_2)/sizeof(ixGC_CAC_WEIGHT_CU_2[0]), 0, 0 },
+	{ "ixGC_CAC_WEIGHT_CU_3", REG_SMC, 0x35, &ixGC_CAC_WEIGHT_CU_3[0], sizeof(ixGC_CAC_WEIGHT_CU_3)/sizeof(ixGC_CAC_WEIGHT_CU_3[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU0", REG_SMC, 0xba, &ixGC_CAC_ACC_CU0[0], sizeof(ixGC_CAC_ACC_CU0)/sizeof(ixGC_CAC_ACC_CU0[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU1", REG_SMC, 0xbb, &ixGC_CAC_ACC_CU1[0], sizeof(ixGC_CAC_ACC_CU1)/sizeof(ixGC_CAC_ACC_CU1[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU2", REG_SMC, 0xbc, &ixGC_CAC_ACC_CU2[0], sizeof(ixGC_CAC_ACC_CU2)/sizeof(ixGC_CAC_ACC_CU2[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU3", REG_SMC, 0xbd, &ixGC_CAC_ACC_CU3[0], sizeof(ixGC_CAC_ACC_CU3)/sizeof(ixGC_CAC_ACC_CU3[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU4", REG_SMC, 0xbe, &ixGC_CAC_ACC_CU4[0], sizeof(ixGC_CAC_ACC_CU4)/sizeof(ixGC_CAC_ACC_CU4[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU5", REG_SMC, 0xbf, &ixGC_CAC_ACC_CU5[0], sizeof(ixGC_CAC_ACC_CU5)/sizeof(ixGC_CAC_ACC_CU5[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU6", REG_SMC, 0xc0, &ixGC_CAC_ACC_CU6[0], sizeof(ixGC_CAC_ACC_CU6)/sizeof(ixGC_CAC_ACC_CU6[0]), 0, 0 },
+	{ "ixGC_CAC_ACC_CU7", REG_SMC, 0xc1, &ixGC_CAC_ACC_CU7[0], sizeof(ixGC_CAC_ACC_CU7)/sizeof(ixGC_CAC_ACC_CU7[0]), 0, 0 },
+	{ "ixMP_IOC_CTRL", REG_SMC, 0xcf100000, &ixMP_IOC_CTRL[0], sizeof(ixMP_IOC_CTRL)/sizeof(ixMP_IOC_CTRL[0]), 0, 0 },
+	{ "ixMP_IOC_RDDATA", REG_SMC, 0xcf100004, &ixMP_IOC_RDDATA[0], sizeof(ixMP_IOC_RDDATA)/sizeof(ixMP_IOC_RDDATA[0]), 0, 0 },
+	{ "ixMP_IOC_PHASE1", REG_SMC, 0xcf100008, &ixMP_IOC_PHASE1[0], sizeof(ixMP_IOC_PHASE1)/sizeof(ixMP_IOC_PHASE1[0]), 0, 0 },
+	{ "ixMP_IOC_PHASE2", REG_SMC, 0xcf10000c, &ixMP_IOC_PHASE2[0], sizeof(ixMP_IOC_PHASE2)/sizeof(ixMP_IOC_PHASE2[0]), 0, 0 },
+	{ "ixMP_IOC_PHASE3", REG_SMC, 0xcf100010, &ixMP_IOC_PHASE3[0], sizeof(ixMP_IOC_PHASE3)/sizeof(ixMP_IOC_PHASE3[0]), 0, 0 },
+	{ "ixMP_IOC_READ_0", REG_SMC, 0xcf100024, &ixMP_IOC_READ_0[0], sizeof(ixMP_IOC_READ_0)/sizeof(ixMP_IOC_READ_0[0]), 0, 0 },
+	{ "ixMP_IOC_READ_1", REG_SMC, 0xcf100028, &ixMP_IOC_READ_1[0], sizeof(ixMP_IOC_READ_1)/sizeof(ixMP_IOC_READ_1[0]), 0, 0 },
+	{ "ixMP_IOC_READ_2", REG_SMC, 0xcf10002c, &ixMP_IOC_READ_2[0], sizeof(ixMP_IOC_READ_2)/sizeof(ixMP_IOC_READ_2[0]), 0, 0 },
+	{ "ixMP_IOC_READ_3", REG_SMC, 0xcf100030, &ixMP_IOC_READ_3[0], sizeof(ixMP_IOC_READ_3)/sizeof(ixMP_IOC_READ_3[0]), 0, 0 },
+	{ "ixMP_IOC_READ_4", REG_SMC, 0xcf100034, &ixMP_IOC_READ_4[0], sizeof(ixMP_IOC_READ_4)/sizeof(ixMP_IOC_READ_4[0]), 0, 0 },
+	{ "ixMP_IOC_READ_5", REG_SMC, 0xcf100038, &ixMP_IOC_READ_5[0], sizeof(ixMP_IOC_READ_5)/sizeof(ixMP_IOC_READ_5[0]), 0, 0 },
+	{ "ixMP_IOC_READ_6", REG_SMC, 0xcf10003c, &ixMP_IOC_READ_6[0], sizeof(ixMP_IOC_READ_6)/sizeof(ixMP_IOC_READ_6[0]), 0, 0 },
+	{ "ixMP_IOC_READ_7", REG_SMC, 0xcf100040, &ixMP_IOC_READ_7[0], sizeof(ixMP_IOC_READ_7)/sizeof(ixMP_IOC_READ_7[0]), 0, 0 },
+	{ "ixMP_IOC_READ_8", REG_SMC, 0xcf100044, &ixMP_IOC_READ_8[0], sizeof(ixMP_IOC_READ_8)/sizeof(ixMP_IOC_READ_8[0]), 0, 0 },
+	{ "ixMP_IOC_READ_9", REG_SMC, 0xcf100048, &ixMP_IOC_READ_9[0], sizeof(ixMP_IOC_READ_9)/sizeof(ixMP_IOC_READ_9[0]), 0, 0 },
+	{ "ixMP_IOC_READ_10", REG_SMC, 0xcf10004c, &ixMP_IOC_READ_10[0], sizeof(ixMP_IOC_READ_10)/sizeof(ixMP_IOC_READ_10[0]), 0, 0 },
+	{ "ixMP_IOC_READ_11", REG_SMC, 0xcf100050, &ixMP_IOC_READ_11[0], sizeof(ixMP_IOC_READ_11)/sizeof(ixMP_IOC_READ_11[0]), 0, 0 },
+	{ "ixMP_IOC_READ_12", REG_SMC, 0xcf100054, &ixMP_IOC_READ_12[0], sizeof(ixMP_IOC_READ_12)/sizeof(ixMP_IOC_READ_12[0]), 0, 0 },
+	{ "ixMP_IOC_READ_13", REG_SMC, 0xcf100058, &ixMP_IOC_READ_13[0], sizeof(ixMP_IOC_READ_13)/sizeof(ixMP_IOC_READ_13[0]), 0, 0 },
+	{ "ixMP_IOC_READ_14", REG_SMC, 0xcf10005c, &ixMP_IOC_READ_14[0], sizeof(ixMP_IOC_READ_14)/sizeof(ixMP_IOC_READ_14[0]), 0, 0 },
+	{ "ixMP_IOC_READ_15", REG_SMC, 0xcf100060, &ixMP_IOC_READ_15[0], sizeof(ixMP_IOC_READ_15)/sizeof(ixMP_IOC_READ_15[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_0", REG_SMC, 0xcf100064, &ixMP_IOC_WRITE_0[0], sizeof(ixMP_IOC_WRITE_0)/sizeof(ixMP_IOC_WRITE_0[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_1", REG_SMC, 0xcf100068, &ixMP_IOC_WRITE_1[0], sizeof(ixMP_IOC_WRITE_1)/sizeof(ixMP_IOC_WRITE_1[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_2", REG_SMC, 0xcf10006c, &ixMP_IOC_WRITE_2[0], sizeof(ixMP_IOC_WRITE_2)/sizeof(ixMP_IOC_WRITE_2[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_3", REG_SMC, 0xcf100070, &ixMP_IOC_WRITE_3[0], sizeof(ixMP_IOC_WRITE_3)/sizeof(ixMP_IOC_WRITE_3[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_4", REG_SMC, 0xcf100074, &ixMP_IOC_WRITE_4[0], sizeof(ixMP_IOC_WRITE_4)/sizeof(ixMP_IOC_WRITE_4[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_5", REG_SMC, 0xcf100078, &ixMP_IOC_WRITE_5[0], sizeof(ixMP_IOC_WRITE_5)/sizeof(ixMP_IOC_WRITE_5[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_6", REG_SMC, 0xcf10007c, &ixMP_IOC_WRITE_6[0], sizeof(ixMP_IOC_WRITE_6)/sizeof(ixMP_IOC_WRITE_6[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_7", REG_SMC, 0xcf100080, &ixMP_IOC_WRITE_7[0], sizeof(ixMP_IOC_WRITE_7)/sizeof(ixMP_IOC_WRITE_7[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_8", REG_SMC, 0xcf100084, &ixMP_IOC_WRITE_8[0], sizeof(ixMP_IOC_WRITE_8)/sizeof(ixMP_IOC_WRITE_8[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_9", REG_SMC, 0xcf100088, &ixMP_IOC_WRITE_9[0], sizeof(ixMP_IOC_WRITE_9)/sizeof(ixMP_IOC_WRITE_9[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_10", REG_SMC, 0xcf10008c, &ixMP_IOC_WRITE_10[0], sizeof(ixMP_IOC_WRITE_10)/sizeof(ixMP_IOC_WRITE_10[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_11", REG_SMC, 0xcf100090, &ixMP_IOC_WRITE_11[0], sizeof(ixMP_IOC_WRITE_11)/sizeof(ixMP_IOC_WRITE_11[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_12", REG_SMC, 0xcf100094, &ixMP_IOC_WRITE_12[0], sizeof(ixMP_IOC_WRITE_12)/sizeof(ixMP_IOC_WRITE_12[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_13", REG_SMC, 0xcf100098, &ixMP_IOC_WRITE_13[0], sizeof(ixMP_IOC_WRITE_13)/sizeof(ixMP_IOC_WRITE_13[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_14", REG_SMC, 0xcf10009c, &ixMP_IOC_WRITE_14[0], sizeof(ixMP_IOC_WRITE_14)/sizeof(ixMP_IOC_WRITE_14[0]), 0, 0 },
+	{ "ixMP_IOC_WRITE_15", REG_SMC, 0xcf1000a0, &ixMP_IOC_WRITE_15[0], sizeof(ixMP_IOC_WRITE_15)/sizeof(ixMP_IOC_WRITE_15[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_CNTL", REG_SMC, 0xcf200000, &ixMP_DRAM_CNTL_WRREQ_CNTL[0], sizeof(ixMP_DRAM_CNTL_WRREQ_CNTL)/sizeof(ixMP_DRAM_CNTL_WRREQ_CNTL[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_CNTL_1", REG_SMC, 0xcf200004, &ixMP_DRAM_CNTL_WRREQ_CNTL_1[0], sizeof(ixMP_DRAM_CNTL_WRREQ_CNTL_1)/sizeof(ixMP_DRAM_CNTL_WRREQ_CNTL_1[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_LOW_ADDR", REG_SMC, 0xcf200008, &ixMP_DRAM_CNTL_WRREQ_LOW_ADDR[0], sizeof(ixMP_DRAM_CNTL_WRREQ_LOW_ADDR)/sizeof(ixMP_DRAM_CNTL_WRREQ_LOW_ADDR[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR", REG_SMC, 0xcf20000c, &ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR[0], sizeof(ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR)/sizeof(ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_MASK", REG_SMC, 0xcf200010, &ixMP_DRAM_CNTL_WRREQ_MASK[0], sizeof(ixMP_DRAM_CNTL_WRREQ_MASK)/sizeof(ixMP_DRAM_CNTL_WRREQ_MASK[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_DATA_0", REG_SMC, 0xcf200014, &ixMP_DRAM_CNTL_WRREQ_DATA_0[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_0)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_0[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_DATA_1", REG_SMC, 0xcf200018, &ixMP_DRAM_CNTL_WRREQ_DATA_1[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_1)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_1[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_DATA_2", REG_SMC, 0xcf20001c, &ixMP_DRAM_CNTL_WRREQ_DATA_2[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_2)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_2[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_DATA_3", REG_SMC, 0xcf200020, &ixMP_DRAM_CNTL_WRREQ_DATA_3[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_3)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_3[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_DATA_4", REG_SMC, 0xcf200024, &ixMP_DRAM_CNTL_WRREQ_DATA_4[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_4)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_4[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_DATA_5", REG_SMC, 0xcf200028, &ixMP_DRAM_CNTL_WRREQ_DATA_5[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_5)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_5[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_DATA_6", REG_SMC, 0xcf20002c, &ixMP_DRAM_CNTL_WRREQ_DATA_6[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_6)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_6[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_DATA_7", REG_SMC, 0xcf200030, &ixMP_DRAM_CNTL_WRREQ_DATA_7[0], sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_7)/sizeof(ixMP_DRAM_CNTL_WRREQ_DATA_7[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRREQ_STATUS", REG_SMC, 0xcf200038, &ixMP_DRAM_CNTL_WRREQ_STATUS[0], sizeof(ixMP_DRAM_CNTL_WRREQ_STATUS)/sizeof(ixMP_DRAM_CNTL_WRREQ_STATUS[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_WRRET_STATUS_0", REG_SMC, 0xcf20003c, &ixMP_DRAM_CNTL_WRRET_STATUS_0[0], sizeof(ixMP_DRAM_CNTL_WRRET_STATUS_0)/sizeof(ixMP_DRAM_CNTL_WRRET_STATUS_0[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDREQ_ADDR", REG_SMC, 0xcf200040, &ixMP_DRAM_CNTL_RDREQ_ADDR[0], sizeof(ixMP_DRAM_CNTL_RDREQ_ADDR)/sizeof(ixMP_DRAM_CNTL_RDREQ_ADDR[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDREQ_CNTL", REG_SMC, 0xcf200044, &ixMP_DRAM_CNTL_RDREQ_CNTL[0], sizeof(ixMP_DRAM_CNTL_RDREQ_CNTL)/sizeof(ixMP_DRAM_CNTL_RDREQ_CNTL[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDREQ_CNTL_1", REG_SMC, 0xcf200048, &ixMP_DRAM_CNTL_RDREQ_CNTL_1[0], sizeof(ixMP_DRAM_CNTL_RDREQ_CNTL_1)/sizeof(ixMP_DRAM_CNTL_RDREQ_CNTL_1[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_VALID", REG_SMC, 0xcf20004c, &ixMP_DRAM_CNTL_RDRET_VALID[0], sizeof(ixMP_DRAM_CNTL_RDRET_VALID)/sizeof(ixMP_DRAM_CNTL_RDRET_VALID[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_NACK", REG_SMC, 0xcf200050, &ixMP_DRAM_CNTL_RDRET_NACK[0], sizeof(ixMP_DRAM_CNTL_RDRET_NACK)/sizeof(ixMP_DRAM_CNTL_RDRET_NACK[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_0", REG_SMC, 0xcf200054, &ixMP_DRAM_CNTL_RDRET_DATA_0[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_0)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_0[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_1", REG_SMC, 0xcf200058, &ixMP_DRAM_CNTL_RDRET_DATA_1[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_1)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_1[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_2", REG_SMC, 0xcf20005c, &ixMP_DRAM_CNTL_RDRET_DATA_2[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_2)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_2[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_3", REG_SMC, 0xcf200060, &ixMP_DRAM_CNTL_RDRET_DATA_3[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_3)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_3[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_4", REG_SMC, 0xcf200064, &ixMP_DRAM_CNTL_RDRET_DATA_4[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_4)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_4[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_5", REG_SMC, 0xcf200068, &ixMP_DRAM_CNTL_RDRET_DATA_5[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_5)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_5[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_6", REG_SMC, 0xcf20006c, &ixMP_DRAM_CNTL_RDRET_DATA_6[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_6)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_6[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_7", REG_SMC, 0xcf200070, &ixMP_DRAM_CNTL_RDRET_DATA_7[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_7)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_7[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_8", REG_SMC, 0xcf200074, &ixMP_DRAM_CNTL_RDRET_DATA_8[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_8)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_8[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_9", REG_SMC, 0xcf200078, &ixMP_DRAM_CNTL_RDRET_DATA_9[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_9)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_9[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_10", REG_SMC, 0xcf20007c, &ixMP_DRAM_CNTL_RDRET_DATA_10[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_10)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_10[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_11", REG_SMC, 0xcf200080, &ixMP_DRAM_CNTL_RDRET_DATA_11[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_11)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_11[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_12", REG_SMC, 0xcf200084, &ixMP_DRAM_CNTL_RDRET_DATA_12[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_12)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_12[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_13", REG_SMC, 0xcf200088, &ixMP_DRAM_CNTL_RDRET_DATA_13[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_13)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_13[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_14", REG_SMC, 0xcf20008c, &ixMP_DRAM_CNTL_RDRET_DATA_14[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_14)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_14[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_15", REG_SMC, 0xcf200090, &ixMP_DRAM_CNTL_RDRET_DATA_15[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_15)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_15[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_16", REG_SMC, 0xcf200094, &ixMP_DRAM_CNTL_RDRET_DATA_16[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_16)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_16[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_17", REG_SMC, 0xcf200098, &ixMP_DRAM_CNTL_RDRET_DATA_17[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_17)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_17[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_18", REG_SMC, 0xcf20009c, &ixMP_DRAM_CNTL_RDRET_DATA_18[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_18)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_18[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_19", REG_SMC, 0xcf2000a0, &ixMP_DRAM_CNTL_RDRET_DATA_19[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_19)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_19[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_20", REG_SMC, 0xcf2000a4, &ixMP_DRAM_CNTL_RDRET_DATA_20[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_20)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_20[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_21", REG_SMC, 0xcf2000a8, &ixMP_DRAM_CNTL_RDRET_DATA_21[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_21)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_21[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_22", REG_SMC, 0xcf2000ac, &ixMP_DRAM_CNTL_RDRET_DATA_22[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_22)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_22[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_23", REG_SMC, 0xcf2000b0, &ixMP_DRAM_CNTL_RDRET_DATA_23[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_23)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_23[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_24", REG_SMC, 0xcf2000b4, &ixMP_DRAM_CNTL_RDRET_DATA_24[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_24)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_24[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_25", REG_SMC, 0xcf2000b8, &ixMP_DRAM_CNTL_RDRET_DATA_25[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_25)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_25[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_26", REG_SMC, 0xcf2000bc, &ixMP_DRAM_CNTL_RDRET_DATA_26[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_26)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_26[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_27", REG_SMC, 0xcf2000c0, &ixMP_DRAM_CNTL_RDRET_DATA_27[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_27)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_27[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_28", REG_SMC, 0xcf2000c4, &ixMP_DRAM_CNTL_RDRET_DATA_28[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_28)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_28[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_29", REG_SMC, 0xcf2000c8, &ixMP_DRAM_CNTL_RDRET_DATA_29[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_29)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_29[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_30", REG_SMC, 0xcf2000cc, &ixMP_DRAM_CNTL_RDRET_DATA_30[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_30)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_30[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_31", REG_SMC, 0xcf2000d0, &ixMP_DRAM_CNTL_RDRET_DATA_31[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_31)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_31[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_32", REG_SMC, 0xcf2000d4, &ixMP_DRAM_CNTL_RDRET_DATA_32[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_32)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_32[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_33", REG_SMC, 0xcf2000d8, &ixMP_DRAM_CNTL_RDRET_DATA_33[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_33)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_33[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_34", REG_SMC, 0xcf2000dc, &ixMP_DRAM_CNTL_RDRET_DATA_34[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_34)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_34[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_35", REG_SMC, 0xcf2000e0, &ixMP_DRAM_CNTL_RDRET_DATA_35[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_35)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_35[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_36", REG_SMC, 0xcf2000e4, &ixMP_DRAM_CNTL_RDRET_DATA_36[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_36)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_36[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_37", REG_SMC, 0xcf2000e8, &ixMP_DRAM_CNTL_RDRET_DATA_37[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_37)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_37[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_38", REG_SMC, 0xcf2000ec, &ixMP_DRAM_CNTL_RDRET_DATA_38[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_38)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_38[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_39", REG_SMC, 0xcf2000f0, &ixMP_DRAM_CNTL_RDRET_DATA_39[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_39)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_39[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_40", REG_SMC, 0xcf2000f4, &ixMP_DRAM_CNTL_RDRET_DATA_40[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_40)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_40[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_41", REG_SMC, 0xcf2000f8, &ixMP_DRAM_CNTL_RDRET_DATA_41[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_41)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_41[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_42", REG_SMC, 0xcf2000fc, &ixMP_DRAM_CNTL_RDRET_DATA_42[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_42)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_42[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_43", REG_SMC, 0xcf200100, &ixMP_DRAM_CNTL_RDRET_DATA_43[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_43)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_43[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_44", REG_SMC, 0xcf200104, &ixMP_DRAM_CNTL_RDRET_DATA_44[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_44)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_44[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_45", REG_SMC, 0xcf200108, &ixMP_DRAM_CNTL_RDRET_DATA_45[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_45)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_45[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_46", REG_SMC, 0xcf20010c, &ixMP_DRAM_CNTL_RDRET_DATA_46[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_46)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_46[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_47", REG_SMC, 0xcf200110, &ixMP_DRAM_CNTL_RDRET_DATA_47[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_47)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_47[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_48", REG_SMC, 0xcf200114, &ixMP_DRAM_CNTL_RDRET_DATA_48[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_48)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_48[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_49", REG_SMC, 0xcf200118, &ixMP_DRAM_CNTL_RDRET_DATA_49[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_49)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_49[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_50", REG_SMC, 0xcf20011c, &ixMP_DRAM_CNTL_RDRET_DATA_50[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_50)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_50[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_51", REG_SMC, 0xcf200120, &ixMP_DRAM_CNTL_RDRET_DATA_51[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_51)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_51[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_52", REG_SMC, 0xcf200124, &ixMP_DRAM_CNTL_RDRET_DATA_52[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_52)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_52[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_53", REG_SMC, 0xcf200128, &ixMP_DRAM_CNTL_RDRET_DATA_53[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_53)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_53[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_54", REG_SMC, 0xcf20012c, &ixMP_DRAM_CNTL_RDRET_DATA_54[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_54)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_54[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_55", REG_SMC, 0xcf200130, &ixMP_DRAM_CNTL_RDRET_DATA_55[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_55)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_55[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_56", REG_SMC, 0xcf200134, &ixMP_DRAM_CNTL_RDRET_DATA_56[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_56)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_56[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_57", REG_SMC, 0xcf200138, &ixMP_DRAM_CNTL_RDRET_DATA_57[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_57)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_57[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_58", REG_SMC, 0xcf20013c, &ixMP_DRAM_CNTL_RDRET_DATA_58[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_58)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_58[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_59", REG_SMC, 0xcf200140, &ixMP_DRAM_CNTL_RDRET_DATA_59[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_59)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_59[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_60", REG_SMC, 0xcf200144, &ixMP_DRAM_CNTL_RDRET_DATA_60[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_60)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_60[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_61", REG_SMC, 0xcf200148, &ixMP_DRAM_CNTL_RDRET_DATA_61[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_61)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_61[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_62", REG_SMC, 0xcf20014c, &ixMP_DRAM_CNTL_RDRET_DATA_62[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_62)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_62[0]), 0, 0 },
+	{ "ixMP_DRAM_CNTL_RDRET_DATA_63", REG_SMC, 0xcf200150, &ixMP_DRAM_CNTL_RDRET_DATA_63[0], sizeof(ixMP_DRAM_CNTL_RDRET_DATA_63)/sizeof(ixMP_DRAM_CNTL_RDRET_DATA_63[0]), 0, 0 },
+	{ "ixMP_INTERRUPT_CONTROL", REG_SMC, 0xcf200400, &ixMP_INTERRUPT_CONTROL[0], sizeof(ixMP_INTERRUPT_CONTROL)/sizeof(ixMP_INTERRUPT_CONTROL[0]), 0, 0 },
+	{ "ixMP0_SW_INT", REG_SMC, 0xcf200404, &ixMP0_SW_INT[0], sizeof(ixMP0_SW_INT)/sizeof(ixMP0_SW_INT[0]), 0, 0 },
+	{ "ixMP0_SW_INT_CTXID", REG_SMC, 0xcf200408, &ixMP0_SW_INT_CTXID[0], sizeof(ixMP0_SW_INT_CTXID)/sizeof(ixMP0_SW_INT_CTXID[0]), 0, 0 },
+	{ "ixMP1_SW_INT", REG_SMC, 0xcf20040c, &ixMP1_SW_INT[0], sizeof(ixMP1_SW_INT)/sizeof(ixMP1_SW_INT[0]), 0, 0 },
+	{ "ixMP1_SW_INT_CTXID", REG_SMC, 0xcf200410, &ixMP1_SW_INT_CTXID[0], sizeof(ixMP1_SW_INT_CTXID)/sizeof(ixMP1_SW_INT_CTXID[0]), 0, 0 },
+	{ "ixDISP_TIMER_ID", REG_SMC, 0xcf200414, &ixDISP_TIMER_ID[0], sizeof(ixDISP_TIMER_ID)/sizeof(ixDISP_TIMER_ID[0]), 0, 0 },
+	{ "ixMP_FPS_CNT_XBAR", REG_SMC, 0xcf200800, &ixMP_FPS_CNT_XBAR[0], sizeof(ixMP_FPS_CNT_XBAR)/sizeof(ixMP_FPS_CNT_XBAR[0]), 0, 0 },
+	{ "ixMP_SRBM_CONFIG_XBAR", REG_SMC, 0xcf200804, &ixMP_SRBM_CONFIG_XBAR[0], sizeof(ixMP_SRBM_CONFIG_XBAR)/sizeof(ixMP_SRBM_CONFIG_XBAR[0]), 0, 0 },
+	{ "ixMP_SRBM_CONTROL", REG_SMC, 0xcf200c00, &ixMP_SRBM_CONTROL[0], sizeof(ixMP_SRBM_CONTROL)/sizeof(ixMP_SRBM_CONTROL[0]), 0, 0 },
+	{ "ixMP_SRBM_ACCVIO_LOG", REG_SMC, 0xcf200c04, &ixMP_SRBM_ACCVIO_LOG[0], sizeof(ixMP_SRBM_ACCVIO_LOG)/sizeof(ixMP_SRBM_ACCVIO_LOG[0]), 0, 0 },
+	{ "ixMP_SRBM_ACCVIO_ADDR", REG_SMC, 0xcf200c08, &ixMP_SRBM_ACCVIO_ADDR[0], sizeof(ixMP_SRBM_ACCVIO_ADDR)/sizeof(ixMP_SRBM_ACCVIO_ADDR[0]), 0, 0 },
+	{ "ixMP_CRBBM_CONTROL", REG_SMC, 0xcf200c0c, &ixMP_CRBBM_CONTROL[0], sizeof(ixMP_CRBBM_CONTROL)/sizeof(ixMP_CRBBM_CONTROL[0]), 0, 0 },
+	{ "ixMP_CRBBM_ACCVIO_LOG", REG_SMC, 0xcf200c10, &ixMP_CRBBM_ACCVIO_LOG[0], sizeof(ixMP_CRBBM_ACCVIO_LOG)/sizeof(ixMP_CRBBM_ACCVIO_LOG[0]), 0, 0 },
+	{ "ixMP_CRBBM_ACCVIO_ADDR", REG_SMC, 0xcf200c14, &ixMP_CRBBM_ACCVIO_ADDR[0], sizeof(ixMP_CRBBM_ACCVIO_ADDR)/sizeof(ixMP_CRBBM_ACCVIO_ADDR[0]), 0, 0 },
+	{ "ixGENERAL_PWRMGT", REG_SMC, 0xd0200000, &ixGENERAL_PWRMGT[0], sizeof(ixGENERAL_PWRMGT)/sizeof(ixGENERAL_PWRMGT[0]), 0, 0 },
+	{ "ixCNB_PWRMGT_CNTL", REG_SMC, 0xd0200004, &ixCNB_PWRMGT_CNTL[0], sizeof(ixCNB_PWRMGT_CNTL)/sizeof(ixCNB_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixSCLK_PWRMGT_CNTL", REG_SMC, 0xd0200008, &ixSCLK_PWRMGT_CNTL[0], sizeof(ixSCLK_PWRMGT_CNTL)/sizeof(ixSCLK_PWRMGT_CNTL[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX", REG_SMC, 0xd0200014, &ixTARGET_AND_CURRENT_PROFILE_INDEX[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX[0]), 0, 0 },
+	{ "ixCG_STATIC_SCREEN_PARAMETER", REG_SMC, 0xd0200044, &ixCG_STATIC_SCREEN_PARAMETER[0], sizeof(ixCG_STATIC_SCREEN_PARAMETER)/sizeof(ixCG_STATIC_SCREEN_PARAMETER[0]), 0, 0 },
+	{ "ixCG_ACPI_CNTL", REG_SMC, 0xd0200064, &ixCG_ACPI_CNTL[0], sizeof(ixCG_ACPI_CNTL)/sizeof(ixCG_ACPI_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xd0200080, &ixSCLK_DEEP_SLEEP_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xd0200084, &ixSCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL2)/sizeof(ixSCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_MISC_CNTL", REG_SMC, 0xd0200088, &ixSCLK_DEEP_SLEEP_MISC_CNTL[0], sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL)/sizeof(ixSCLK_DEEP_SLEEP_MISC_CNTL[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL", REG_SMC, 0xd020008c, &ixLCLK_DEEP_SLEEP_CNTL[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL)/sizeof(ixLCLK_DEEP_SLEEP_CNTL[0]), 0, 0 },
+	{ "ixSMU_VOLTAGE_STATUS", REG_SMC, 0xd0200094, &ixSMU_VOLTAGE_STATUS[0], sizeof(ixSMU_VOLTAGE_STATUS)/sizeof(ixSMU_VOLTAGE_STATUS[0]), 0, 0 },
+	{ "ixSCLK_DEEP_SLEEP_CNTL3", REG_SMC, 0xd020009c, &ixSCLK_DEEP_SLEEP_CNTL3[0], sizeof(ixSCLK_DEEP_SLEEP_CNTL3)/sizeof(ixSCLK_DEEP_SLEEP_CNTL3[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_1", REG_SMC, 0xd02000f0, &ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_1[0]), 0, 0 },
+	{ "ixTARGET_AND_CURRENT_PROFILE_INDEX_2", REG_SMC, 0xd02000f4, &ixTARGET_AND_CURRENT_PROFILE_INDEX_2[0], sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_2)/sizeof(ixTARGET_AND_CURRENT_PROFILE_INDEX_2[0]), 0, 0 },
+	{ "ixCG_ULV_PARAMETER", REG_SMC, 0xd020015c, &ixCG_ULV_PARAMETER[0], sizeof(ixCG_ULV_PARAMETER)/sizeof(ixCG_ULV_PARAMETER[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_0", REG_SMC, 0xd02001a8, &ixCG_FREQ_TRAN_VOTING_0[0], sizeof(ixCG_FREQ_TRAN_VOTING_0)/sizeof(ixCG_FREQ_TRAN_VOTING_0[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_1", REG_SMC, 0xd02001ac, &ixCG_FREQ_TRAN_VOTING_1[0], sizeof(ixCG_FREQ_TRAN_VOTING_1)/sizeof(ixCG_FREQ_TRAN_VOTING_1[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_2", REG_SMC, 0xd02001b0, &ixCG_FREQ_TRAN_VOTING_2[0], sizeof(ixCG_FREQ_TRAN_VOTING_2)/sizeof(ixCG_FREQ_TRAN_VOTING_2[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_3", REG_SMC, 0xd02001b4, &ixCG_FREQ_TRAN_VOTING_3[0], sizeof(ixCG_FREQ_TRAN_VOTING_3)/sizeof(ixCG_FREQ_TRAN_VOTING_3[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_4", REG_SMC, 0xd02001b8, &ixCG_FREQ_TRAN_VOTING_4[0], sizeof(ixCG_FREQ_TRAN_VOTING_4)/sizeof(ixCG_FREQ_TRAN_VOTING_4[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_5", REG_SMC, 0xd02001bc, &ixCG_FREQ_TRAN_VOTING_5[0], sizeof(ixCG_FREQ_TRAN_VOTING_5)/sizeof(ixCG_FREQ_TRAN_VOTING_5[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_6", REG_SMC, 0xd02001c0, &ixCG_FREQ_TRAN_VOTING_6[0], sizeof(ixCG_FREQ_TRAN_VOTING_6)/sizeof(ixCG_FREQ_TRAN_VOTING_6[0]), 0, 0 },
+	{ "ixCG_FREQ_TRAN_VOTING_7", REG_SMC, 0xd02001c4, &ixCG_FREQ_TRAN_VOTING_7[0], sizeof(ixCG_FREQ_TRAN_VOTING_7)/sizeof(ixCG_FREQ_TRAN_VOTING_7[0]), 0, 0 },
+	{ "ixPCIE_PGFSM_CONFIG", REG_SMC, 0xd02002d0, &ixPCIE_PGFSM_CONFIG[0], sizeof(ixPCIE_PGFSM_CONFIG)/sizeof(ixPCIE_PGFSM_CONFIG[0]), 0, 0 },
+	{ "ixPCIE_PGFSM_WRITE", REG_SMC, 0xd02002d4, &ixPCIE_PGFSM_WRITE[0], sizeof(ixPCIE_PGFSM_WRITE)/sizeof(ixPCIE_PGFSM_WRITE[0]), 0, 0 },
+	{ "ixSERDES_BUSY", REG_SMC, 0xd02002d8, &ixSERDES_BUSY[0], sizeof(ixSERDES_BUSY)/sizeof(ixSERDES_BUSY[0]), 0, 0 },
+	{ "ixPCIE_PGFSM2_CONFIG", REG_SMC, 0xd02002dc, &ixPCIE_PGFSM2_CONFIG[0], sizeof(ixPCIE_PGFSM2_CONFIG)/sizeof(ixPCIE_PGFSM2_CONFIG[0]), 0, 0 },
+	{ "ixPCIE_PGFSM2_WRITE", REG_SMC, 0xd02002e0, &ixPCIE_PGFSM2_WRITE[0], sizeof(ixPCIE_PGFSM2_WRITE)/sizeof(ixPCIE_PGFSM2_WRITE[0]), 0, 0 },
+	{ "ixSERDES2_BUSY", REG_SMC, 0xd02002e4, &ixSERDES2_BUSY[0], sizeof(ixSERDES2_BUSY)/sizeof(ixSERDES2_BUSY[0]), 0, 0 },
+	{ "ixPCIE_PGFSM_0_READ", REG_SMC, 0xd02002e8, &ixPCIE_PGFSM_0_READ[0], sizeof(ixPCIE_PGFSM_0_READ)/sizeof(ixPCIE_PGFSM_0_READ[0]), 0, 0 },
+	{ "ixPCIE_PGFSM_1_READ", REG_SMC, 0xd02002ec, &ixPCIE_PGFSM_1_READ[0], sizeof(ixPCIE_PGFSM_1_READ)/sizeof(ixPCIE_PGFSM_1_READ[0]), 0, 0 },
+	{ "ixPWR_DC_RESP", REG_SMC, 0xd0200300, &ixPWR_DC_RESP[0], sizeof(ixPWR_DC_RESP)/sizeof(ixPWR_DC_RESP[0]), 0, 0 },
+	{ "ixPWR_VCE_RESP", REG_SMC, 0xd0200304, &ixPWR_VCE_RESP[0], sizeof(ixPWR_VCE_RESP)/sizeof(ixPWR_VCE_RESP[0]), 0, 0 },
+	{ "ixPWR_UVD_RESP", REG_SMC, 0xd0200308, &ixPWR_UVD_RESP[0], sizeof(ixPWR_UVD_RESP)/sizeof(ixPWR_UVD_RESP[0]), 0, 0 },
+	{ "ixPWR_ACP_RESP", REG_SMC, 0xd020030c, &ixPWR_ACP_RESP[0], sizeof(ixPWR_ACP_RESP)/sizeof(ixPWR_ACP_RESP[0]), 0, 0 },
+	{ "ixLCLK_DEEP_SLEEP_CNTL2", REG_SMC, 0xd0200310, &ixLCLK_DEEP_SLEEP_CNTL2[0], sizeof(ixLCLK_DEEP_SLEEP_CNTL2)/sizeof(ixLCLK_DEEP_SLEEP_CNTL2[0]), 0, 0 },
+	{ "ixPWR_ACPI_INTERRUPT", REG_SMC, 0xd0200318, &ixPWR_ACPI_INTERRUPT[0], sizeof(ixPWR_ACPI_INTERRUPT)/sizeof(ixPWR_ACPI_INTERRUPT[0]), 0, 0 },
+	{ "ixPWR_DC_REQ", REG_SMC, 0xd020031c, &ixPWR_DC_REQ[0], sizeof(ixPWR_DC_REQ)/sizeof(ixPWR_DC_REQ[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_PARAMETER", REG_SMC, 0xd020036c, &ixVDDGFX_IDLE_PARAMETER[0], sizeof(ixVDDGFX_IDLE_PARAMETER)/sizeof(ixVDDGFX_IDLE_PARAMETER[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_CONTROL", REG_SMC, 0xd0200370, &ixVDDGFX_IDLE_CONTROL[0], sizeof(ixVDDGFX_IDLE_CONTROL)/sizeof(ixVDDGFX_IDLE_CONTROL[0]), 0, 0 },
+	{ "ixVDDGFX_IDLE_EXIT", REG_SMC, 0xd0200374, &ixVDDGFX_IDLE_EXIT[0], sizeof(ixVDDGFX_IDLE_EXIT)/sizeof(ixVDDGFX_IDLE_EXIT[0]), 0, 0 },
+	{ "ixREG_SCLK_DEEP_SLEEP_EXIT", REG_SMC, 0xd0200378, &ixREG_SCLK_DEEP_SLEEP_EXIT[0], sizeof(ixREG_SCLK_DEEP_SLEEP_EXIT)/sizeof(ixREG_SCLK_DEEP_SLEEP_EXIT[0]), 0, 0 },
+	{ "ixSCLK_MIN_DIV", REG_SMC, 0xd02003ac, &ixSCLK_MIN_DIV[0], sizeof(ixSCLK_MIN_DIV)/sizeof(ixSCLK_MIN_DIV[0]), 0, 0 },
+	{ "ixCAC_WEIGHT_LKG_DC_3", REG_SMC, 0xd020803c, &ixCAC_WEIGHT_LKG_DC_3[0], sizeof(ixCAC_WEIGHT_LKG_DC_3)/sizeof(ixCAC_WEIGHT_LKG_DC_3[0]), 0, 0 },
+	{ "ixLCAC_MC0_CNTL", REG_SMC, 0xd0208130, &ixLCAC_MC0_CNTL[0], sizeof(ixLCAC_MC0_CNTL)/sizeof(ixLCAC_MC0_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_SEL", REG_SMC, 0xd0208134, &ixLCAC_MC0_OVR_SEL[0], sizeof(ixLCAC_MC0_OVR_SEL)/sizeof(ixLCAC_MC0_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC0_OVR_VAL", REG_SMC, 0xd0208138, &ixLCAC_MC0_OVR_VAL[0], sizeof(ixLCAC_MC0_OVR_VAL)/sizeof(ixLCAC_MC0_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC1_CNTL", REG_SMC, 0xd020813c, &ixLCAC_MC1_CNTL[0], sizeof(ixLCAC_MC1_CNTL)/sizeof(ixLCAC_MC1_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_SEL", REG_SMC, 0xd0208140, &ixLCAC_MC1_OVR_SEL[0], sizeof(ixLCAC_MC1_OVR_SEL)/sizeof(ixLCAC_MC1_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC1_OVR_VAL", REG_SMC, 0xd0208144, &ixLCAC_MC1_OVR_VAL[0], sizeof(ixLCAC_MC1_OVR_VAL)/sizeof(ixLCAC_MC1_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC2_CNTL", REG_SMC, 0xd0208148, &ixLCAC_MC2_CNTL[0], sizeof(ixLCAC_MC2_CNTL)/sizeof(ixLCAC_MC2_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_SEL", REG_SMC, 0xd020814c, &ixLCAC_MC2_OVR_SEL[0], sizeof(ixLCAC_MC2_OVR_SEL)/sizeof(ixLCAC_MC2_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC2_OVR_VAL", REG_SMC, 0xd0208150, &ixLCAC_MC2_OVR_VAL[0], sizeof(ixLCAC_MC2_OVR_VAL)/sizeof(ixLCAC_MC2_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_MC3_CNTL", REG_SMC, 0xd0208154, &ixLCAC_MC3_CNTL[0], sizeof(ixLCAC_MC3_CNTL)/sizeof(ixLCAC_MC3_CNTL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_SEL", REG_SMC, 0xd0208158, &ixLCAC_MC3_OVR_SEL[0], sizeof(ixLCAC_MC3_OVR_SEL)/sizeof(ixLCAC_MC3_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_MC3_OVR_VAL", REG_SMC, 0xd020815c, &ixLCAC_MC3_OVR_VAL[0], sizeof(ixLCAC_MC3_OVR_VAL)/sizeof(ixLCAC_MC3_OVR_VAL[0]), 0, 0 },
+	{ "ixLCAC_CPL_CNTL", REG_SMC, 0xd0208160, &ixLCAC_CPL_CNTL[0], sizeof(ixLCAC_CPL_CNTL)/sizeof(ixLCAC_CPL_CNTL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_SEL", REG_SMC, 0xd0208164, &ixLCAC_CPL_OVR_SEL[0], sizeof(ixLCAC_CPL_OVR_SEL)/sizeof(ixLCAC_CPL_OVR_SEL[0]), 0, 0 },
+	{ "ixLCAC_CPL_OVR_VAL", REG_SMC, 0xd0208168, &ixLCAC_CPL_OVR_VAL[0], sizeof(ixLCAC_CPL_OVR_VAL)/sizeof(ixLCAC_CPL_OVR_VAL[0]), 0, 0 },
+	{ "ixMISC_UNB_PWRMGT_CFG0", REG_SMC, 0xd020c000, &ixMISC_UNB_PWRMGT_CFG0[0], sizeof(ixMISC_UNB_PWRMGT_CFG0)/sizeof(ixMISC_UNB_PWRMGT_CFG0[0]), 0, 0 },
+	{ "ixMISC_UNB_PWRMGT_CFG1", REG_SMC, 0xd020c004, &ixMISC_UNB_PWRMGT_CFG1[0], sizeof(ixMISC_UNB_PWRMGT_CFG1)/sizeof(ixMISC_UNB_PWRMGT_CFG1[0]), 0, 0 },
+	{ "ixMISC_UNB_PWRMGT_DATA", REG_SMC, 0xd020c00c, &ixMISC_UNB_PWRMGT_DATA[0], sizeof(ixMISC_UNB_PWRMGT_DATA)/sizeof(ixMISC_UNB_PWRMGT_DATA[0]), 0, 0 },
+	{ "ixGNBPM_SMU_PWRMGT_DATA", REG_SMC, 0xd020c010, &ixGNBPM_SMU_PWRMGT_DATA[0], sizeof(ixGNBPM_SMU_PWRMGT_DATA)/sizeof(ixGNBPM_SMU_PWRMGT_DATA[0]), 0, 0 },
+	{ "ixDMA_ACTIVE_SAMPLER_CFG", REG_SMC, 0xd020c014, &ixDMA_ACTIVE_SAMPLER_CFG[0], sizeof(ixDMA_ACTIVE_SAMPLER_CFG)/sizeof(ixDMA_ACTIVE_SAMPLER_CFG[0]), 0, 0 },
+	{ "ixSOUTHBRIDGE_TYPE", REG_SMC, 0xd020c01c, &ixSOUTHBRIDGE_TYPE[0], sizeof(ixSOUTHBRIDGE_TYPE)/sizeof(ixSOUTHBRIDGE_TYPE[0]), 0, 0 },
+	{ "ixGNBPM_SMU_PWRMGT_STATUS", REG_SMC, 0xd020c020, &ixGNBPM_SMU_PWRMGT_STATUS[0], sizeof(ixGNBPM_SMU_PWRMGT_STATUS)/sizeof(ixGNBPM_SMU_PWRMGT_STATUS[0]), 0, 0 },
+	{ "ixALLOW_SR_INTR_CTRL", REG_SMC, 0xd020c024, &ixALLOW_SR_INTR_CTRL[0], sizeof(ixALLOW_SR_INTR_CTRL)/sizeof(ixALLOW_SR_INTR_CTRL[0]), 0, 0 },
+	{ "ixCURRENT_STATE_CPU0", REG_SMC, 0xd0210000, &ixCURRENT_STATE_CPU0[0], sizeof(ixCURRENT_STATE_CPU0)/sizeof(ixCURRENT_STATE_CPU0[0]), 0, 0 },
+	{ "ixCPU_REDUN_DONE0", REG_SMC, 0xd0210004, &ixCPU_REDUN_DONE0[0], sizeof(ixCPU_REDUN_DONE0)/sizeof(ixCPU_REDUN_DONE0[0]), 0, 0 },
+	{ "ixCURRENT_VID_CPU0", REG_SMC, 0xd0210008, &ixCURRENT_VID_CPU0[0], sizeof(ixCURRENT_VID_CPU0)/sizeof(ixCURRENT_VID_CPU0[0]), 0, 0 },
+	{ "ixCURRENT_STATE_CPU1", REG_SMC, 0xd0210010, &ixCURRENT_STATE_CPU1[0], sizeof(ixCURRENT_STATE_CPU1)/sizeof(ixCURRENT_STATE_CPU1[0]), 0, 0 },
+	{ "ixCPU_REDUN_DONE1", REG_SMC, 0xd0210014, &ixCPU_REDUN_DONE1[0], sizeof(ixCPU_REDUN_DONE1)/sizeof(ixCPU_REDUN_DONE1[0]), 0, 0 },
+	{ "ixCURRENT_VID_CPU1", REG_SMC, 0xd0210018, &ixCURRENT_VID_CPU1[0], sizeof(ixCURRENT_VID_CPU1)/sizeof(ixCURRENT_VID_CPU1[0]), 0, 0 },
+	{ "ixUNBPM_PWRMGT_ACK", REG_SMC, 0xd0211000, &ixUNBPM_PWRMGT_ACK[0], sizeof(ixUNBPM_PWRMGT_ACK)/sizeof(ixUNBPM_PWRMGT_ACK[0]), 0, 0 },
+	{ "ixCURRENT_FREQ_STATE_NB", REG_SMC, 0xd0211004, &ixCURRENT_FREQ_STATE_NB[0], sizeof(ixCURRENT_FREQ_STATE_NB)/sizeof(ixCURRENT_FREQ_STATE_NB[0]), 0, 0 },
+	{ "ixCURRENT_PSTATE_NB", REG_SMC, 0xd0211008, &ixCURRENT_PSTATE_NB[0], sizeof(ixCURRENT_PSTATE_NB)/sizeof(ixCURRENT_PSTATE_NB[0]), 0, 0 },
+	{ "ixUNBPM_MSG_INT_CONFIG", REG_SMC, 0xd021100c, &ixUNBPM_MSG_INT_CONFIG[0], sizeof(ixUNBPM_MSG_INT_CONFIG)/sizeof(ixUNBPM_MSG_INT_CONFIG[0]), 0, 0 },
+	{ "ixUNBPM_NBPWRMGT_CMD", REG_SMC, 0xd0211010, &ixUNBPM_NBPWRMGT_CMD[0], sizeof(ixUNBPM_NBPWRMGT_CMD)/sizeof(ixUNBPM_NBPWRMGT_CMD[0]), 0, 0 },
+	{ "ixUNBPM_NBPWRMGT_FSM_CFG", REG_SMC, 0xd0211014, &ixUNBPM_NBPWRMGT_FSM_CFG[0], sizeof(ixUNBPM_NBPWRMGT_FSM_CFG)/sizeof(ixUNBPM_NBPWRMGT_FSM_CFG[0]), 0, 0 },
+	{ "ixDDR0_FUSE_SSB_XFER", REG_SMC, 0xd0211018, &ixDDR0_FUSE_SSB_XFER[0], sizeof(ixDDR0_FUSE_SSB_XFER)/sizeof(ixDDR0_FUSE_SSB_XFER[0]), 0, 0 },
+	{ "ixDDR0_FUSE_SSB_XFER_CFG", REG_SMC, 0xd021101c, &ixDDR0_FUSE_SSB_XFER_CFG[0], sizeof(ixDDR0_FUSE_SSB_XFER_CFG)/sizeof(ixDDR0_FUSE_SSB_XFER_CFG[0]), 0, 0 },
+	{ "ixDDR1_FUSE_SSB_XFER", REG_SMC, 0xd0211020, &ixDDR1_FUSE_SSB_XFER[0], sizeof(ixDDR1_FUSE_SSB_XFER)/sizeof(ixDDR1_FUSE_SSB_XFER[0]), 0, 0 },
+	{ "ixDDR1_FUSE_SSB_XFER_CFG", REG_SMC, 0xd0211024, &ixDDR1_FUSE_SSB_XFER_CFG[0], sizeof(ixDDR1_FUSE_SSB_XFER_CFG)/sizeof(ixDDR1_FUSE_SSB_XFER_CFG[0]), 0, 0 },
+	{ "ixUNBPM_FUSES_VAL_PWROK", REG_SMC, 0xd0211028, &ixUNBPM_FUSES_VAL_PWROK[0], sizeof(ixUNBPM_FUSES_VAL_PWROK)/sizeof(ixUNBPM_FUSES_VAL_PWROK[0]), 0, 0 },
+	{ "ixSYNFIFO_CLK_RATIO", REG_SMC, 0xd021102c, &ixSYNFIFO_CLK_RATIO[0], sizeof(ixSYNFIFO_CLK_RATIO)/sizeof(ixSYNFIFO_CLK_RATIO[0]), 0, 0 },
+	{ "ixMISC_SMU_PWRMGT_CFG0", REG_SMC, 0xd0211030, &ixMISC_SMU_PWRMGT_CFG0[0], sizeof(ixMISC_SMU_PWRMGT_CFG0)/sizeof(ixMISC_SMU_PWRMGT_CFG0[0]), 0, 0 },
+	{ "ixMISC_GNB_PWRMGT_CFG1", REG_SMC, 0xd0211034, &ixMISC_GNB_PWRMGT_CFG1[0], sizeof(ixMISC_GNB_PWRMGT_CFG1)/sizeof(ixMISC_GNB_PWRMGT_CFG1[0]), 0, 0 },
+	{ "ixMISC_SMU_PWRMGT_CFG1", REG_SMC, 0xd0211038, &ixMISC_SMU_PWRMGT_CFG1[0], sizeof(ixMISC_SMU_PWRMGT_CFG1)/sizeof(ixMISC_SMU_PWRMGT_CFG1[0]), 0, 0 },
+	{ "ixMISC_GNB_PWRMGT_DATA", REG_SMC, 0xd021103c, &ixMISC_GNB_PWRMGT_DATA[0], sizeof(ixMISC_GNB_PWRMGT_DATA)/sizeof(ixMISC_GNB_PWRMGT_DATA[0]), 0, 0 },
+	{ "ixGN_GNB_SLOW", REG_SMC, 0xd0211040, &ixGN_GNB_SLOW[0], sizeof(ixGN_GNB_SLOW)/sizeof(ixGN_GNB_SLOW[0]), 0, 0 },
+	{ "ixGN_FORCE_NBPS1", REG_SMC, 0xd0211044, &ixGN_FORCE_NBPS1[0], sizeof(ixGN_FORCE_NBPS1)/sizeof(ixGN_FORCE_NBPS1[0]), 0, 0 },
+	{ "ixMISC_SMU_PWRMGT_DATA", REG_SMC, 0xd0211048, &ixMISC_SMU_PWRMGT_DATA[0], sizeof(ixMISC_SMU_PWRMGT_DATA)/sizeof(ixMISC_SMU_PWRMGT_DATA[0]), 0, 0 },
+	{ "ixNB_COF", REG_SMC, 0xd021104c, &ixNB_COF[0], sizeof(ixNB_COF)/sizeof(ixNB_COF[0]), 0, 0 },
+	{ "ixUNBPM_CK_IRESET", REG_SMC, 0xd0211050, &ixUNBPM_CK_IRESET[0], sizeof(ixUNBPM_CK_IRESET)/sizeof(ixUNBPM_CK_IRESET[0]), 0, 0 },
+	{ "ixCURRENT_VID_NB", REG_SMC, 0xd0211054, &ixCURRENT_VID_NB[0], sizeof(ixCURRENT_VID_NB)/sizeof(ixCURRENT_VID_NB[0]), 0, 0 },
+	{ "ixSPR_FUSE_PSTATEPWR1", REG_SMC, 0xd0211058, &ixSPR_FUSE_PSTATEPWR1[0], sizeof(ixSPR_FUSE_PSTATEPWR1)/sizeof(ixSPR_FUSE_PSTATEPWR1[0]), 0, 0 },
+	{ "ixSPR_FUSE_PSTATEPWR2", REG_SMC, 0xd021105c, &ixSPR_FUSE_PSTATEPWR2[0], sizeof(ixSPR_FUSE_PSTATEPWR2)/sizeof(ixSPR_FUSE_PSTATEPWR2[0]), 0, 0 },
+	{ "ixSPR_FUSE_PSTATEPWR3", REG_SMC, 0xd0211060, &ixSPR_FUSE_PSTATEPWR3[0], sizeof(ixSPR_FUSE_PSTATEPWR3)/sizeof(ixSPR_FUSE_PSTATEPWR3[0]), 0, 0 },
+	{ "ixSPR_FUSE_THERMAL_SCRATCH", REG_SMC, 0xd0211064, &ixSPR_FUSE_THERMAL_SCRATCH[0], sizeof(ixSPR_FUSE_THERMAL_SCRATCH)/sizeof(ixSPR_FUSE_THERMAL_SCRATCH[0]), 0, 0 },
+	{ "ixSPR_PRODUCT_INFO0", REG_SMC, 0xd0211068, &ixSPR_PRODUCT_INFO0[0], sizeof(ixSPR_PRODUCT_INFO0)/sizeof(ixSPR_PRODUCT_INFO0[0]), 0, 0 },
+	{ "ixSPR_SERIALNUM_REG1", REG_SMC, 0xd021106c, &ixSPR_SERIALNUM_REG1[0], sizeof(ixSPR_SERIALNUM_REG1)/sizeof(ixSPR_SERIALNUM_REG1[0]), 0, 0 },
+	{ "ixSPR_SERIALNUM_REG2", REG_SMC, 0xd0211070, &ixSPR_SERIALNUM_REG2[0], sizeof(ixSPR_SERIALNUM_REG2)/sizeof(ixSPR_SERIALNUM_REG2[0]), 0, 0 },
+	{ "ixSPR_PRODUCT_INFO1", REG_SMC, 0xd0211074, &ixSPR_PRODUCT_INFO1[0], sizeof(ixSPR_PRODUCT_INFO1)/sizeof(ixSPR_PRODUCT_INFO1[0]), 0, 0 },
+	{ "ixSPR_EXT_PRODUCT_INFO", REG_SMC, 0xd021107c, &ixSPR_EXT_PRODUCT_INFO[0], sizeof(ixSPR_EXT_PRODUCT_INFO)/sizeof(ixSPR_EXT_PRODUCT_INFO[0]), 0, 0 },
+	{ "ixSPR_MSIDFUSE", REG_SMC, 0xd0211080, &ixSPR_MSIDFUSE[0], sizeof(ixSPR_MSIDFUSE)/sizeof(ixSPR_MSIDFUSE[0]), 0, 0 },
+	{ "ixSPR_LINK_PRODUCT_INFO", REG_SMC, 0xd0211084, &ixSPR_LINK_PRODUCT_INFO[0], sizeof(ixSPR_LINK_PRODUCT_INFO)/sizeof(ixSPR_LINK_PRODUCT_INFO[0]), 0, 0 },
+	{ "ixSPR_BRAND_NAME_ADDR", REG_SMC, 0xd0211088, &ixSPR_BRAND_NAME_ADDR[0], sizeof(ixSPR_BRAND_NAME_ADDR)/sizeof(ixSPR_BRAND_NAME_ADDR[0]), 0, 0 },
+	{ "ixSPR_BRAND_NAME_DATA", REG_SMC, 0xd021108c, &ixSPR_BRAND_NAME_DATA[0], sizeof(ixSPR_BRAND_NAME_DATA)/sizeof(ixSPR_BRAND_NAME_DATA[0]), 0, 0 },
+	{ "ixSPR_COMBO_PHY_PRODUCT_INFO", REG_SMC, 0xd0211090, &ixSPR_COMBO_PHY_PRODUCT_INFO[0], sizeof(ixSPR_COMBO_PHY_PRODUCT_INFO)/sizeof(ixSPR_COMBO_PHY_PRODUCT_INFO[0]), 0, 0 },
+	{ "ixMISC_GNB_PWRMGT_CFG0", REG_SMC, 0xd0211094, &ixMISC_GNB_PWRMGT_CFG0[0], sizeof(ixMISC_GNB_PWRMGT_CFG0)/sizeof(ixMISC_GNB_PWRMGT_CFG0[0]), 0, 0 },
+	{ "ixUNBPM_EXIT_TO_PSTATE", REG_SMC, 0xd0211098, &ixUNBPM_EXIT_TO_PSTATE[0], sizeof(ixUNBPM_EXIT_TO_PSTATE)/sizeof(ixUNBPM_EXIT_TO_PSTATE[0]), 0, 0 },
+	{ "ixUNBPM_WARM_RESET_HS_STATUS", REG_SMC, 0xd021109c, &ixUNBPM_WARM_RESET_HS_STATUS[0], sizeof(ixUNBPM_WARM_RESET_HS_STATUS)/sizeof(ixUNBPM_WARM_RESET_HS_STATUS[0]), 0, 0 },
+	{ "ixUNBPM_VOLTAGE_CNTL", REG_SMC, 0xd02110a0, &ixUNBPM_VOLTAGE_CNTL[0], sizeof(ixUNBPM_VOLTAGE_CNTL)/sizeof(ixUNBPM_VOLTAGE_CNTL[0]), 0, 0 },
+	{ "ixUNBPM_VOLTAGE_STATUS", REG_SMC, 0xd02110a4, &ixUNBPM_VOLTAGE_STATUS[0], sizeof(ixUNBPM_VOLTAGE_STATUS)/sizeof(ixUNBPM_VOLTAGE_STATUS[0]), 0, 0 },
+	{ "ixNUM_BOOST_STATES", REG_SMC, 0xd02110a8, &ixNUM_BOOST_STATES[0], sizeof(ixNUM_BOOST_STATES)/sizeof(ixNUM_BOOST_STATES[0]), 0, 0 },
+	{ "ixWARM_RESET_NB_CONTROL", REG_SMC, 0xd02110ac, &ixWARM_RESET_NB_CONTROL[0], sizeof(ixWARM_RESET_NB_CONTROL)/sizeof(ixWARM_RESET_NB_CONTROL[0]), 0, 0 },
+	{ "ixONION_NO_STREAMS_PEND", REG_SMC, 0xd02110b0, &ixONION_NO_STREAMS_PEND[0], sizeof(ixONION_NO_STREAMS_PEND)/sizeof(ixONION_NO_STREAMS_PEND[0]), 0, 0 },
+	{ "ixSPR_PROGRAMMABLE_CTRL", REG_SMC, 0xd02110b4, &ixSPR_PROGRAMMABLE_CTRL[0], sizeof(ixSPR_PROGRAMMABLE_CTRL)/sizeof(ixSPR_PROGRAMMABLE_CTRL[0]), 0, 0 },
+	{ "ixPHN_FUSERX_MISC_FUSES", REG_SMC, 0xd02110b8, &ixPHN_FUSERX_MISC_FUSES[0], sizeof(ixPHN_FUSERX_MISC_FUSES)/sizeof(ixPHN_FUSERX_MISC_FUSES[0]), 0, 0 },
+	{ "ixUNBPM_PWRCTRL_MISC", REG_SMC, 0xd02110bc, &ixUNBPM_PWRCTRL_MISC[0], sizeof(ixUNBPM_PWRCTRL_MISC)/sizeof(ixUNBPM_PWRCTRL_MISC[0]), 0, 0 },
+	{ "ixCSTATE_ACTIVE_SAMPLER", REG_SMC, 0xd02110c0, &ixCSTATE_ACTIVE_SAMPLER[0], sizeof(ixCSTATE_ACTIVE_SAMPLER)/sizeof(ixCSTATE_ACTIVE_SAMPLER[0]), 0, 0 },
+	{ "ixUNBPM_DEBUG_CONFIG_STATUS", REG_SMC, 0xd02110c4, &ixUNBPM_DEBUG_CONFIG_STATUS[0], sizeof(ixUNBPM_DEBUG_CONFIG_STATUS)/sizeof(ixUNBPM_DEBUG_CONFIG_STATUS[0]), 0, 0 },
+	{ "ixUNBPM_AXIMST_LAST_CMD", REG_SMC, 0xd02110c8, &ixUNBPM_AXIMST_LAST_CMD[0], sizeof(ixUNBPM_AXIMST_LAST_CMD)/sizeof(ixUNBPM_AXIMST_LAST_CMD[0]), 0, 0 },
+	{ "ixUNB_IF_INTRGEN_LAST_SENT", REG_SMC, 0xd02110cc, &ixUNB_IF_INTRGEN_LAST_SENT[0], sizeof(ixUNB_IF_INTRGEN_LAST_SENT)/sizeof(ixUNB_IF_INTRGEN_LAST_SENT[0]), 0, 0 },
+	{ "ixUNBPM_DEBUG_BUS_CNTL", REG_SMC, 0xd02110d0, &ixUNBPM_DEBUG_BUS_CNTL[0], sizeof(ixUNBPM_DEBUG_BUS_CNTL)/sizeof(ixUNBPM_DEBUG_BUS_CNTL[0]), 0, 0 },
+	{ "ixUNBPM_PWRMGT_REQ_DBG_STATUS", REG_SMC, 0xd02110d4, &ixUNBPM_PWRMGT_REQ_DBG_STATUS[0], sizeof(ixUNBPM_PWRMGT_REQ_DBG_STATUS)/sizeof(ixUNBPM_PWRMGT_REQ_DBG_STATUS[0]), 0, 0 },
+	{ "ixUNBPM_VIDCHG_REQ_DBG_STATUS", REG_SMC, 0xd02110d8, &ixUNBPM_VIDCHG_REQ_DBG_STATUS[0], sizeof(ixUNBPM_VIDCHG_REQ_DBG_STATUS)/sizeof(ixUNBPM_VIDCHG_REQ_DBG_STATUS[0]), 0, 0 },
+	{ "ixUNBPM_SCRATCH_0", REG_SMC, 0xd021e000, &ixUNBPM_SCRATCH_0[0], sizeof(ixUNBPM_SCRATCH_0)/sizeof(ixUNBPM_SCRATCH_0[0]), 0, 0 },
+	{ "ixUNBPM_SCRATCH_1", REG_SMC, 0xd021e004, &ixUNBPM_SCRATCH_1[0], sizeof(ixUNBPM_SCRATCH_1)/sizeof(ixUNBPM_SCRATCH_1[0]), 0, 0 },
+	{ "ixPOWERON_CPU_0", REG_SMC, 0xd0220000, &ixPOWERON_CPU_0[0], sizeof(ixPOWERON_CPU_0)/sizeof(ixPOWERON_CPU_0[0]), 0, 0 },
+	{ "ixPOWERREADY_CPU_0", REG_SMC, 0xd0220004, &ixPOWERREADY_CPU_0[0], sizeof(ixPOWERREADY_CPU_0)/sizeof(ixPOWERREADY_CPU_0[0]), 0, 0 },
+	{ "ixPGRUNFEEDBACK_CPU_0", REG_SMC, 0xd0220008, &ixPGRUNFEEDBACK_CPU_0[0], sizeof(ixPGRUNFEEDBACK_CPU_0)/sizeof(ixPGRUNFEEDBACK_CPU_0[0]), 0, 0 },
+	{ "ixRCC3ON_CPU_0", REG_SMC, 0xd022000c, &ixRCC3ON_CPU_0[0], sizeof(ixRCC3ON_CPU_0)/sizeof(ixRCC3ON_CPU_0[0]), 0, 0 },
+	{ "ixRCC3EXITDONE_CPU_0", REG_SMC, 0xd0220010, &ixRCC3EXITDONE_CPU_0[0], sizeof(ixRCC3EXITDONE_CPU_0)/sizeof(ixRCC3EXITDONE_CPU_0[0]), 0, 0 },
+	{ "ixCORE_FUNC_LATE_SSB_XFER_0", REG_SMC, 0xd0220014, &ixCORE_FUNC_LATE_SSB_XFER_0[0], sizeof(ixCORE_FUNC_LATE_SSB_XFER_0)/sizeof(ixCORE_FUNC_LATE_SSB_XFER_0[0]), 0, 0 },
+	{ "ixCORE_FUNC_LATE_SSB_XFER_CFG_0", REG_SMC, 0xd0220018, &ixCORE_FUNC_LATE_SSB_XFER_CFG_0[0], sizeof(ixCORE_FUNC_LATE_SSB_XFER_CFG_0)/sizeof(ixCORE_FUNC_LATE_SSB_XFER_CFG_0[0]), 0, 0 },
+	{ "ixCORE_REDUN_SSB_XFER_0", REG_SMC, 0xd022001c, &ixCORE_REDUN_SSB_XFER_0[0], sizeof(ixCORE_REDUN_SSB_XFER_0)/sizeof(ixCORE_REDUN_SSB_XFER_0[0]), 0, 0 },
+	{ "ixCORE_REDUN_SSB_XFER_CFG_0", REG_SMC, 0xd0220020, &ixCORE_REDUN_SSB_XFER_CFG_0[0], sizeof(ixCORE_REDUN_SSB_XFER_CFG_0)/sizeof(ixCORE_REDUN_SSB_XFER_CFG_0[0]), 0, 0 },
+	{ "ixCORE_APM_SSB_XFER_0", REG_SMC, 0xd0220024, &ixCORE_APM_SSB_XFER_0[0], sizeof(ixCORE_APM_SSB_XFER_0)/sizeof(ixCORE_APM_SSB_XFER_0[0]), 0, 0 },
+	{ "ixCORE_APM_SSB_XFER_CFG_0", REG_SMC, 0xd0220028, &ixCORE_APM_SSB_XFER_CFG_0[0], sizeof(ixCORE_APM_SSB_XFER_CFG_0)/sizeof(ixCORE_APM_SSB_XFER_CFG_0[0]), 0, 0 },
+	{ "ixCOREPM_PWRCTRL_MISC_0", REG_SMC, 0xd022002c, &ixCOREPM_PWRCTRL_MISC_0[0], sizeof(ixCOREPM_PWRCTRL_MISC_0)/sizeof(ixCOREPM_PWRCTRL_MISC_0[0]), 0, 0 },
+	{ "ixLDOIVRON_CPU_0", REG_SMC, 0xd0220030, &ixLDOIVRON_CPU_0[0], sizeof(ixLDOIVRON_CPU_0)/sizeof(ixLDOIVRON_CPU_0[0]), 0, 0 },
+	{ "ixLDOIVREXITDONE_CPU_0", REG_SMC, 0xd0220034, &ixLDOIVREXITDONE_CPU_0[0], sizeof(ixLDOIVREXITDONE_CPU_0)/sizeof(ixLDOIVREXITDONE_CPU_0[0]), 0, 0 },
+	{ "ixRCC3_TARGETPSMREF_CPU_0", REG_SMC, 0xd0220038, &ixRCC3_TARGETPSMREF_CPU_0[0], sizeof(ixRCC3_TARGETPSMREF_CPU_0)/sizeof(ixRCC3_TARGETPSMREF_CPU_0[0]), 0, 0 },
+	{ "ixIVR_TARGETPSMREF_CPU_0", REG_SMC, 0xd022003c, &ixIVR_TARGETPSMREF_CPU_0[0], sizeof(ixIVR_TARGETPSMREF_CPU_0)/sizeof(ixIVR_TARGETPSMREF_CPU_0[0]), 0, 0 },
+	{ "ixCK_JTCOOLRESET_LATCHED_CPU_0", REG_SMC, 0xd0220044, &ixCK_JTCOOLRESET_LATCHED_CPU_0[0], sizeof(ixCK_JTCOOLRESET_LATCHED_CPU_0)/sizeof(ixCK_JTCOOLRESET_LATCHED_CPU_0[0]), 0, 0 },
+	{ "ixCK_DISABLECORE_CPU_0", REG_SMC, 0xd0220048, &ixCK_DISABLECORE_CPU_0[0], sizeof(ixCK_DISABLECORE_CPU_0)/sizeof(ixCK_DISABLECORE_CPU_0[0]), 0, 0 },
+	{ "ixCOREPM_ID_0", REG_SMC, 0xd022004c, &ixCOREPM_ID_0[0], sizeof(ixCOREPM_ID_0)/sizeof(ixCOREPM_ID_0[0]), 0, 0 },
+	{ "ixCOREPM_SCRATCH_0", REG_SMC, 0xd0220050, &ixCOREPM_SCRATCH_0[0], sizeof(ixCOREPM_SCRATCH_0)/sizeof(ixCOREPM_SCRATCH_0[0]), 0, 0 },
+	{ "ixRCC3_WAKEMIN_CPU_0", REG_SMC, 0xd0220054, &ixRCC3_WAKEMIN_CPU_0[0], sizeof(ixRCC3_WAKEMIN_CPU_0)/sizeof(ixRCC3_WAKEMIN_CPU_0[0]), 0, 0 },
+	{ "ixSPMI_CONFIG0_0", REG_SMC, 0xd0221000, &ixSPMI_CONFIG0_0[0], sizeof(ixSPMI_CONFIG0_0)/sizeof(ixSPMI_CONFIG0_0[0]), 0, 0 },
+	{ "ixSPMI_CONFIG1_0", REG_SMC, 0xd0221004, &ixSPMI_CONFIG1_0[0], sizeof(ixSPMI_CONFIG1_0)/sizeof(ixSPMI_CONFIG1_0[0]), 0, 0 },
+	{ "ixSPMI_FSM_READ_TRIGGER_0", REG_SMC, 0xd0221008, &ixSPMI_FSM_READ_TRIGGER_0[0], sizeof(ixSPMI_FSM_READ_TRIGGER_0)/sizeof(ixSPMI_FSM_READ_TRIGGER_0[0]), 0, 0 },
+	{ "ixSPMI_FSM_WRITE_TRIGGER_0", REG_SMC, 0xd022100c, &ixSPMI_FSM_WRITE_TRIGGER_0[0], sizeof(ixSPMI_FSM_WRITE_TRIGGER_0)/sizeof(ixSPMI_FSM_WRITE_TRIGGER_0[0]), 0, 0 },
+	{ "ixSPMI_FSM_RESET_TRIGGER_0", REG_SMC, 0xd0221010, &ixSPMI_FSM_RESET_TRIGGER_0[0], sizeof(ixSPMI_FSM_RESET_TRIGGER_0)/sizeof(ixSPMI_FSM_RESET_TRIGGER_0[0]), 0, 0 },
+	{ "ixSPMI_FSM_BUSY_0", REG_SMC, 0xd0221014, &ixSPMI_FSM_BUSY_0[0], sizeof(ixSPMI_FSM_BUSY_0)/sizeof(ixSPMI_FSM_BUSY_0[0]), 0, 0 },
+	{ "ixSPMI_PATH_0", REG_SMC, 0xd0221018, &ixSPMI_PATH_0[0], sizeof(ixSPMI_PATH_0)/sizeof(ixSPMI_PATH_0[0]), 0, 0 },
+	{ "ixSPMI_C6_STATE_0", REG_SMC, 0xd022101c, &ixSPMI_C6_STATE_0[0], sizeof(ixSPMI_C6_STATE_0)/sizeof(ixSPMI_C6_STATE_0[0]), 0, 0 },
+	{ "ixSPMI_JTAG_OVER_0", REG_SMC, 0xd0221020, &ixSPMI_JTAG_OVER_0[0], sizeof(ixSPMI_JTAG_OVER_0)/sizeof(ixSPMI_JTAG_OVER_0[0]), 0, 0 },
+	{ "ixSPMI_SRAM_ADDRESS_0", REG_SMC, 0xd0221024, &ixSPMI_SRAM_ADDRESS_0[0], sizeof(ixSPMI_SRAM_ADDRESS_0)/sizeof(ixSPMI_SRAM_ADDRESS_0[0]), 0, 0 },
+	{ "ixSPMI_SRAM_DATA_0", REG_SMC, 0xd0221028, &ixSPMI_SRAM_DATA_0[0], sizeof(ixSPMI_SRAM_DATA_0)/sizeof(ixSPMI_SRAM_DATA_0[0]), 0, 0 },
+	{ "ixSPMI_RESET_0", REG_SMC, 0xd022102c, &ixSPMI_RESET_0[0], sizeof(ixSPMI_RESET_0)/sizeof(ixSPMI_RESET_0[0]), 0, 0 },
+	{ "ixSPMI_FORCE_CLOCK_GATERS_0", REG_SMC, 0xd0221030, &ixSPMI_FORCE_CLOCK_GATERS_0[0], sizeof(ixSPMI_FORCE_CLOCK_GATERS_0)/sizeof(ixSPMI_FORCE_CLOCK_GATERS_0[0]), 0, 0 },
+	{ "ixSPMI_SPARE_0", REG_SMC, 0xd0221034, &ixSPMI_SPARE_0[0], sizeof(ixSPMI_SPARE_0)/sizeof(ixSPMI_SPARE_0[0]), 0, 0 },
+	{ "ixSPMI_SPARE_EX_0", REG_SMC, 0xd0221038, &ixSPMI_SPARE_EX_0[0], sizeof(ixSPMI_SPARE_EX_0)/sizeof(ixSPMI_SPARE_EX_0[0]), 0, 0 },
+	{ "ixSPMI_SRAM_CLK_GATER_0", REG_SMC, 0xd022103c, &ixSPMI_SRAM_CLK_GATER_0[0], sizeof(ixSPMI_SRAM_CLK_GATER_0)/sizeof(ixSPMI_SRAM_CLK_GATER_0[0]), 0, 0 },
+	{ "ixPOWERON_CPU_1", REG_SMC, 0xd0230000, &ixPOWERON_CPU_1[0], sizeof(ixPOWERON_CPU_1)/sizeof(ixPOWERON_CPU_1[0]), 0, 0 },
+	{ "ixPOWERREADY_CPU_1", REG_SMC, 0xd0230004, &ixPOWERREADY_CPU_1[0], sizeof(ixPOWERREADY_CPU_1)/sizeof(ixPOWERREADY_CPU_1[0]), 0, 0 },
+	{ "ixPGRUNFEEDBACK_CPU_1", REG_SMC, 0xd0230008, &ixPGRUNFEEDBACK_CPU_1[0], sizeof(ixPGRUNFEEDBACK_CPU_1)/sizeof(ixPGRUNFEEDBACK_CPU_1[0]), 0, 0 },
+	{ "ixRCC3ON_CPU_1", REG_SMC, 0xd023000c, &ixRCC3ON_CPU_1[0], sizeof(ixRCC3ON_CPU_1)/sizeof(ixRCC3ON_CPU_1[0]), 0, 0 },
+	{ "ixRCC3EXITDONE_CPU_1", REG_SMC, 0xd0230010, &ixRCC3EXITDONE_CPU_1[0], sizeof(ixRCC3EXITDONE_CPU_1)/sizeof(ixRCC3EXITDONE_CPU_1[0]), 0, 0 },
+	{ "ixCORE_FUNC_LATE_SSB_XFER_1", REG_SMC, 0xd0230014, &ixCORE_FUNC_LATE_SSB_XFER_1[0], sizeof(ixCORE_FUNC_LATE_SSB_XFER_1)/sizeof(ixCORE_FUNC_LATE_SSB_XFER_1[0]), 0, 0 },
+	{ "ixCORE_FUNC_LATE_SSB_XFER_CFG_1", REG_SMC, 0xd0230018, &ixCORE_FUNC_LATE_SSB_XFER_CFG_1[0], sizeof(ixCORE_FUNC_LATE_SSB_XFER_CFG_1)/sizeof(ixCORE_FUNC_LATE_SSB_XFER_CFG_1[0]), 0, 0 },
+	{ "ixCORE_REDUN_SSB_XFER_1", REG_SMC, 0xd023001c, &ixCORE_REDUN_SSB_XFER_1[0], sizeof(ixCORE_REDUN_SSB_XFER_1)/sizeof(ixCORE_REDUN_SSB_XFER_1[0]), 0, 0 },
+	{ "ixCORE_REDUN_SSB_XFER_CFG_1", REG_SMC, 0xd0230020, &ixCORE_REDUN_SSB_XFER_CFG_1[0], sizeof(ixCORE_REDUN_SSB_XFER_CFG_1)/sizeof(ixCORE_REDUN_SSB_XFER_CFG_1[0]), 0, 0 },
+	{ "ixCORE_APM_SSB_XFER_1", REG_SMC, 0xd0230024, &ixCORE_APM_SSB_XFER_1[0], sizeof(ixCORE_APM_SSB_XFER_1)/sizeof(ixCORE_APM_SSB_XFER_1[0]), 0, 0 },
+	{ "ixCORE_APM_SSB_XFER_CFG_1", REG_SMC, 0xd0230028, &ixCORE_APM_SSB_XFER_CFG_1[0], sizeof(ixCORE_APM_SSB_XFER_CFG_1)/sizeof(ixCORE_APM_SSB_XFER_CFG_1[0]), 0, 0 },
+	{ "ixCOREPM_PWRCTRL_MISC_1", REG_SMC, 0xd023002c, &ixCOREPM_PWRCTRL_MISC_1[0], sizeof(ixCOREPM_PWRCTRL_MISC_1)/sizeof(ixCOREPM_PWRCTRL_MISC_1[0]), 0, 0 },
+	{ "ixLDOIVRON_CPU_1", REG_SMC, 0xd0230030, &ixLDOIVRON_CPU_1[0], sizeof(ixLDOIVRON_CPU_1)/sizeof(ixLDOIVRON_CPU_1[0]), 0, 0 },
+	{ "ixLDOIVREXITDONE_CPU_1", REG_SMC, 0xd0230034, &ixLDOIVREXITDONE_CPU_1[0], sizeof(ixLDOIVREXITDONE_CPU_1)/sizeof(ixLDOIVREXITDONE_CPU_1[0]), 0, 0 },
+	{ "ixRCC3_TARGETPSMREF_CPU_1", REG_SMC, 0xd0230038, &ixRCC3_TARGETPSMREF_CPU_1[0], sizeof(ixRCC3_TARGETPSMREF_CPU_1)/sizeof(ixRCC3_TARGETPSMREF_CPU_1[0]), 0, 0 },
+	{ "ixIVR_TARGETPSMREF_CPU_1", REG_SMC, 0xd023003c, &ixIVR_TARGETPSMREF_CPU_1[0], sizeof(ixIVR_TARGETPSMREF_CPU_1)/sizeof(ixIVR_TARGETPSMREF_CPU_1[0]), 0, 0 },
+	{ "ixCK_JTCOOLRESET_LATCHED_CPU_1", REG_SMC, 0xd0230044, &ixCK_JTCOOLRESET_LATCHED_CPU_1[0], sizeof(ixCK_JTCOOLRESET_LATCHED_CPU_1)/sizeof(ixCK_JTCOOLRESET_LATCHED_CPU_1[0]), 0, 0 },
+	{ "ixCK_DISABLECORE_CPU_1", REG_SMC, 0xd0230048, &ixCK_DISABLECORE_CPU_1[0], sizeof(ixCK_DISABLECORE_CPU_1)/sizeof(ixCK_DISABLECORE_CPU_1[0]), 0, 0 },
+	{ "ixCOREPM_ID_1", REG_SMC, 0xd023004c, &ixCOREPM_ID_1[0], sizeof(ixCOREPM_ID_1)/sizeof(ixCOREPM_ID_1[0]), 0, 0 },
+	{ "ixCOREPM_SCRATCH_1", REG_SMC, 0xd0230050, &ixCOREPM_SCRATCH_1[0], sizeof(ixCOREPM_SCRATCH_1)/sizeof(ixCOREPM_SCRATCH_1[0]), 0, 0 },
+	{ "ixRCC3_WAKEMIN_CPU_1", REG_SMC, 0xd0230054, &ixRCC3_WAKEMIN_CPU_1[0], sizeof(ixRCC3_WAKEMIN_CPU_1)/sizeof(ixRCC3_WAKEMIN_CPU_1[0]), 0, 0 },
+	{ "ixSPMI_CONFIG0_1", REG_SMC, 0xd0231000, &ixSPMI_CONFIG0_1[0], sizeof(ixSPMI_CONFIG0_1)/sizeof(ixSPMI_CONFIG0_1[0]), 0, 0 },
+	{ "ixSPMI_CONFIG1_1", REG_SMC, 0xd0231004, &ixSPMI_CONFIG1_1[0], sizeof(ixSPMI_CONFIG1_1)/sizeof(ixSPMI_CONFIG1_1[0]), 0, 0 },
+	{ "ixSPMI_FSM_READ_TRIGGER_1", REG_SMC, 0xd0231008, &ixSPMI_FSM_READ_TRIGGER_1[0], sizeof(ixSPMI_FSM_READ_TRIGGER_1)/sizeof(ixSPMI_FSM_READ_TRIGGER_1[0]), 0, 0 },
+	{ "ixSPMI_FSM_WRITE_TRIGGER_1", REG_SMC, 0xd023100c, &ixSPMI_FSM_WRITE_TRIGGER_1[0], sizeof(ixSPMI_FSM_WRITE_TRIGGER_1)/sizeof(ixSPMI_FSM_WRITE_TRIGGER_1[0]), 0, 0 },
+	{ "ixSPMI_FSM_RESET_TRIGGER_1", REG_SMC, 0xd0231010, &ixSPMI_FSM_RESET_TRIGGER_1[0], sizeof(ixSPMI_FSM_RESET_TRIGGER_1)/sizeof(ixSPMI_FSM_RESET_TRIGGER_1[0]), 0, 0 },
+	{ "ixSPMI_FSM_BUSY_1", REG_SMC, 0xd0231014, &ixSPMI_FSM_BUSY_1[0], sizeof(ixSPMI_FSM_BUSY_1)/sizeof(ixSPMI_FSM_BUSY_1[0]), 0, 0 },
+	{ "ixSPMI_PATH_1", REG_SMC, 0xd0231018, &ixSPMI_PATH_1[0], sizeof(ixSPMI_PATH_1)/sizeof(ixSPMI_PATH_1[0]), 0, 0 },
+	{ "ixSPMI_C6_STATE_1", REG_SMC, 0xd023101c, &ixSPMI_C6_STATE_1[0], sizeof(ixSPMI_C6_STATE_1)/sizeof(ixSPMI_C6_STATE_1[0]), 0, 0 },
+	{ "ixSPMI_JTAG_OVER_1", REG_SMC, 0xd0231020, &ixSPMI_JTAG_OVER_1[0], sizeof(ixSPMI_JTAG_OVER_1)/sizeof(ixSPMI_JTAG_OVER_1[0]), 0, 0 },
+	{ "ixSPMI_SRAM_ADDRESS_1", REG_SMC, 0xd0231024, &ixSPMI_SRAM_ADDRESS_1[0], sizeof(ixSPMI_SRAM_ADDRESS_1)/sizeof(ixSPMI_SRAM_ADDRESS_1[0]), 0, 0 },
+	{ "ixSPMI_SRAM_DATA_1", REG_SMC, 0xd0231028, &ixSPMI_SRAM_DATA_1[0], sizeof(ixSPMI_SRAM_DATA_1)/sizeof(ixSPMI_SRAM_DATA_1[0]), 0, 0 },
+	{ "ixSPMI_RESET_1", REG_SMC, 0xd023102c, &ixSPMI_RESET_1[0], sizeof(ixSPMI_RESET_1)/sizeof(ixSPMI_RESET_1[0]), 0, 0 },
+	{ "ixSPMI_FORCE_CLOCK_GATERS_1", REG_SMC, 0xd0231030, &ixSPMI_FORCE_CLOCK_GATERS_1[0], sizeof(ixSPMI_FORCE_CLOCK_GATERS_1)/sizeof(ixSPMI_FORCE_CLOCK_GATERS_1[0]), 0, 0 },
+	{ "ixSPMI_SPARE_1", REG_SMC, 0xd0231034, &ixSPMI_SPARE_1[0], sizeof(ixSPMI_SPARE_1)/sizeof(ixSPMI_SPARE_1[0]), 0, 0 },
+	{ "ixSPMI_SPARE_EX_1", REG_SMC, 0xd0231038, &ixSPMI_SPARE_EX_1[0], sizeof(ixSPMI_SPARE_EX_1)/sizeof(ixSPMI_SPARE_EX_1[0]), 0, 0 },
+	{ "ixSPMI_SRAM_CLK_GATER_1", REG_SMC, 0xd023103c, &ixSPMI_SRAM_CLK_GATER_1[0], sizeof(ixSPMI_SRAM_CLK_GATER_1)/sizeof(ixSPMI_SRAM_CLK_GATER_1[0]), 0, 0 },
+	{ "ixTHM_TCON_HTC", REG_SMC, 0xd8200c64, &ixTHM_TCON_HTC[0], sizeof(ixTHM_TCON_HTC)/sizeof(ixTHM_TCON_HTC[0]), 0, 0 },
+	{ "ixTHM_TCON_CUR_TMP", REG_SMC, 0xd8200ca4, &ixTHM_TCON_CUR_TMP[0], sizeof(ixTHM_TCON_CUR_TMP)/sizeof(ixTHM_TCON_CUR_TMP[0]), 0, 0 },
+	{ "ixTHM_TCON_THERM_TRIP", REG_SMC, 0xd8200ce4, &ixTHM_TCON_THERM_TRIP[0], sizeof(ixTHM_TCON_THERM_TRIP)/sizeof(ixTHM_TCON_THERM_TRIP[0]), 0, 0 },
+	{ "ixTHM_GPIO_PROCHOT_CTRL", REG_SMC, 0xd8200d00, &ixTHM_GPIO_PROCHOT_CTRL[0], sizeof(ixTHM_GPIO_PROCHOT_CTRL)/sizeof(ixTHM_GPIO_PROCHOT_CTRL[0]), 0, 0 },
+	{ "ixTHM_GPIO_THERMTRIP_CTRL", REG_SMC, 0xd8200d04, &ixTHM_GPIO_THERMTRIP_CTRL[0], sizeof(ixTHM_GPIO_THERMTRIP_CTRL)/sizeof(ixTHM_GPIO_THERMTRIP_CTRL[0]), 0, 0 },
+	{ "ixTHM_THERMAL_INT_ENA", REG_SMC, 0xd8200d10, &ixTHM_THERMAL_INT_ENA[0], sizeof(ixTHM_THERMAL_INT_ENA)/sizeof(ixTHM_THERMAL_INT_ENA[0]), 0, 0 },
+	{ "ixTHM_THERMAL_INT_CTRL", REG_SMC, 0xd8200d14, &ixTHM_THERMAL_INT_CTRL[0], sizeof(ixTHM_THERMAL_INT_CTRL)/sizeof(ixTHM_THERMAL_INT_CTRL[0]), 0, 0 },
+	{ "ixTHM_THERMAL_INT_STATUS", REG_SMC, 0xd8200d18, &ixTHM_THERMAL_INT_STATUS[0], sizeof(ixTHM_THERMAL_INT_STATUS)/sizeof(ixTHM_THERMAL_INT_STATUS[0]), 0, 0 },
+	{ "ixTHM_TCON_CSR_CONFIG", REG_SMC, 0xd82014a4, &ixTHM_TCON_CSR_CONFIG[0], sizeof(ixTHM_TCON_CSR_CONFIG)/sizeof(ixTHM_TCON_CSR_CONFIG[0]), 0, 0 },
+	{ "ixTHM_TCON_CSR_DATA", REG_SMC, 0xd82014a8, &ixTHM_TCON_CSR_DATA[0], sizeof(ixTHM_TCON_CSR_DATA)/sizeof(ixTHM_TCON_CSR_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL0_DATA", REG_SMC, 0xd8202000, &ixTMON0_RDIL0_DATA[0], sizeof(ixTMON0_RDIL0_DATA)/sizeof(ixTMON0_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL1_DATA", REG_SMC, 0xd8202004, &ixTMON0_RDIL1_DATA[0], sizeof(ixTMON0_RDIL1_DATA)/sizeof(ixTMON0_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL2_DATA", REG_SMC, 0xd8202008, &ixTMON0_RDIL2_DATA[0], sizeof(ixTMON0_RDIL2_DATA)/sizeof(ixTMON0_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL3_DATA", REG_SMC, 0xd820200c, &ixTMON0_RDIL3_DATA[0], sizeof(ixTMON0_RDIL3_DATA)/sizeof(ixTMON0_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL4_DATA", REG_SMC, 0xd8202010, &ixTMON0_RDIL4_DATA[0], sizeof(ixTMON0_RDIL4_DATA)/sizeof(ixTMON0_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL5_DATA", REG_SMC, 0xd8202014, &ixTMON0_RDIL5_DATA[0], sizeof(ixTMON0_RDIL5_DATA)/sizeof(ixTMON0_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL6_DATA", REG_SMC, 0xd8202018, &ixTMON0_RDIL6_DATA[0], sizeof(ixTMON0_RDIL6_DATA)/sizeof(ixTMON0_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL7_DATA", REG_SMC, 0xd820201c, &ixTMON0_RDIL7_DATA[0], sizeof(ixTMON0_RDIL7_DATA)/sizeof(ixTMON0_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL8_DATA", REG_SMC, 0xd8202020, &ixTMON0_RDIL8_DATA[0], sizeof(ixTMON0_RDIL8_DATA)/sizeof(ixTMON0_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL9_DATA", REG_SMC, 0xd8202024, &ixTMON0_RDIL9_DATA[0], sizeof(ixTMON0_RDIL9_DATA)/sizeof(ixTMON0_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL10_DATA", REG_SMC, 0xd8202028, &ixTMON0_RDIL10_DATA[0], sizeof(ixTMON0_RDIL10_DATA)/sizeof(ixTMON0_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL11_DATA", REG_SMC, 0xd820202c, &ixTMON0_RDIL11_DATA[0], sizeof(ixTMON0_RDIL11_DATA)/sizeof(ixTMON0_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL12_DATA", REG_SMC, 0xd8202030, &ixTMON0_RDIL12_DATA[0], sizeof(ixTMON0_RDIL12_DATA)/sizeof(ixTMON0_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL13_DATA", REG_SMC, 0xd8202034, &ixTMON0_RDIL13_DATA[0], sizeof(ixTMON0_RDIL13_DATA)/sizeof(ixTMON0_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL14_DATA", REG_SMC, 0xd8202038, &ixTMON0_RDIL14_DATA[0], sizeof(ixTMON0_RDIL14_DATA)/sizeof(ixTMON0_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL15_DATA", REG_SMC, 0xd820203c, &ixTMON0_RDIL15_DATA[0], sizeof(ixTMON0_RDIL15_DATA)/sizeof(ixTMON0_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR0_DATA", REG_SMC, 0xd8202040, &ixTMON0_RDIR0_DATA[0], sizeof(ixTMON0_RDIR0_DATA)/sizeof(ixTMON0_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR1_DATA", REG_SMC, 0xd8202044, &ixTMON0_RDIR1_DATA[0], sizeof(ixTMON0_RDIR1_DATA)/sizeof(ixTMON0_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR2_DATA", REG_SMC, 0xd8202048, &ixTMON0_RDIR2_DATA[0], sizeof(ixTMON0_RDIR2_DATA)/sizeof(ixTMON0_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR3_DATA", REG_SMC, 0xd820204c, &ixTMON0_RDIR3_DATA[0], sizeof(ixTMON0_RDIR3_DATA)/sizeof(ixTMON0_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR4_DATA", REG_SMC, 0xd8202050, &ixTMON0_RDIR4_DATA[0], sizeof(ixTMON0_RDIR4_DATA)/sizeof(ixTMON0_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR5_DATA", REG_SMC, 0xd8202054, &ixTMON0_RDIR5_DATA[0], sizeof(ixTMON0_RDIR5_DATA)/sizeof(ixTMON0_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR6_DATA", REG_SMC, 0xd8202058, &ixTMON0_RDIR6_DATA[0], sizeof(ixTMON0_RDIR6_DATA)/sizeof(ixTMON0_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR7_DATA", REG_SMC, 0xd820205c, &ixTMON0_RDIR7_DATA[0], sizeof(ixTMON0_RDIR7_DATA)/sizeof(ixTMON0_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR8_DATA", REG_SMC, 0xd8202060, &ixTMON0_RDIR8_DATA[0], sizeof(ixTMON0_RDIR8_DATA)/sizeof(ixTMON0_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR9_DATA", REG_SMC, 0xd8202064, &ixTMON0_RDIR9_DATA[0], sizeof(ixTMON0_RDIR9_DATA)/sizeof(ixTMON0_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR10_DATA", REG_SMC, 0xd8202068, &ixTMON0_RDIR10_DATA[0], sizeof(ixTMON0_RDIR10_DATA)/sizeof(ixTMON0_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR11_DATA", REG_SMC, 0xd820206c, &ixTMON0_RDIR11_DATA[0], sizeof(ixTMON0_RDIR11_DATA)/sizeof(ixTMON0_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR12_DATA", REG_SMC, 0xd8202070, &ixTMON0_RDIR12_DATA[0], sizeof(ixTMON0_RDIR12_DATA)/sizeof(ixTMON0_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR13_DATA", REG_SMC, 0xd8202074, &ixTMON0_RDIR13_DATA[0], sizeof(ixTMON0_RDIR13_DATA)/sizeof(ixTMON0_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR14_DATA", REG_SMC, 0xd8202078, &ixTMON0_RDIR14_DATA[0], sizeof(ixTMON0_RDIR14_DATA)/sizeof(ixTMON0_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIR15_DATA", REG_SMC, 0xd820207c, &ixTMON0_RDIR15_DATA[0], sizeof(ixTMON0_RDIR15_DATA)/sizeof(ixTMON0_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTMON0_INT_DATA", REG_SMC, 0xd8202080, &ixTMON0_INT_DATA[0], sizeof(ixTMON0_INT_DATA)/sizeof(ixTMON0_INT_DATA[0]), 0, 0 },
+	{ "ixTMON0_RDIL_PRESENT0", REG_SMC, 0xd8202084, &ixTMON0_RDIL_PRESENT0[0], sizeof(ixTMON0_RDIL_PRESENT0)/sizeof(ixTMON0_RDIL_PRESENT0[0]), 0, 0 },
+	{ "ixTMON0_RDIL_PRESENT1", REG_SMC, 0xd8202088, &ixTMON0_RDIL_PRESENT1[0], sizeof(ixTMON0_RDIL_PRESENT1)/sizeof(ixTMON0_RDIL_PRESENT1[0]), 0, 0 },
+	{ "ixTMON0_RDIR_PRESENT0", REG_SMC, 0xd820208c, &ixTMON0_RDIR_PRESENT0[0], sizeof(ixTMON0_RDIR_PRESENT0)/sizeof(ixTMON0_RDIR_PRESENT0[0]), 0, 0 },
+	{ "ixTMON0_RDIR_PRESENT1", REG_SMC, 0xd8202090, &ixTMON0_RDIR_PRESENT1[0], sizeof(ixTMON0_RDIR_PRESENT1)/sizeof(ixTMON0_RDIR_PRESENT1[0]), 0, 0 },
+	{ "ixTMON0_CONFIG", REG_SMC, 0xd8202098, &ixTMON0_CONFIG[0], sizeof(ixTMON0_CONFIG)/sizeof(ixTMON0_CONFIG[0]), 0, 0 },
+	{ "ixTMON0_TEMP_CALC_COEFF0", REG_SMC, 0xd82020a0, &ixTMON0_TEMP_CALC_COEFF0[0], sizeof(ixTMON0_TEMP_CALC_COEFF0)/sizeof(ixTMON0_TEMP_CALC_COEFF0[0]), 0, 0 },
+	{ "ixTMON0_TEMP_CALC_COEFF1", REG_SMC, 0xd82020a4, &ixTMON0_TEMP_CALC_COEFF1[0], sizeof(ixTMON0_TEMP_CALC_COEFF1)/sizeof(ixTMON0_TEMP_CALC_COEFF1[0]), 0, 0 },
+	{ "ixTMON0_TEMP_CALC_COEFF2", REG_SMC, 0xd82020a8, &ixTMON0_TEMP_CALC_COEFF2[0], sizeof(ixTMON0_TEMP_CALC_COEFF2)/sizeof(ixTMON0_TEMP_CALC_COEFF2[0]), 0, 0 },
+	{ "ixTMON0_TEMP_CALC_COEFF3", REG_SMC, 0xd82020ac, &ixTMON0_TEMP_CALC_COEFF3[0], sizeof(ixTMON0_TEMP_CALC_COEFF3)/sizeof(ixTMON0_TEMP_CALC_COEFF3[0]), 0, 0 },
+	{ "ixTMON0_TEMP_CALC_COEFF4", REG_SMC, 0xd82020b0, &ixTMON0_TEMP_CALC_COEFF4[0], sizeof(ixTMON0_TEMP_CALC_COEFF4)/sizeof(ixTMON0_TEMP_CALC_COEFF4[0]), 0, 0 },
+	{ "ixTMON0_DEBUG0", REG_SMC, 0xd82020b4, &ixTMON0_DEBUG0[0], sizeof(ixTMON0_DEBUG0)/sizeof(ixTMON0_DEBUG0[0]), 0, 0 },
+	{ "ixTMON0_DEBUG1", REG_SMC, 0xd82020b8, &ixTMON0_DEBUG1[0], sizeof(ixTMON0_DEBUG1)/sizeof(ixTMON0_DEBUG1[0]), 0, 0 },
+	{ "ixTMON1_RDIL0_DATA", REG_SMC, 0xd8202100, &ixTMON1_RDIL0_DATA[0], sizeof(ixTMON1_RDIL0_DATA)/sizeof(ixTMON1_RDIL0_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL1_DATA", REG_SMC, 0xd8202104, &ixTMON1_RDIL1_DATA[0], sizeof(ixTMON1_RDIL1_DATA)/sizeof(ixTMON1_RDIL1_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL2_DATA", REG_SMC, 0xd8202108, &ixTMON1_RDIL2_DATA[0], sizeof(ixTMON1_RDIL2_DATA)/sizeof(ixTMON1_RDIL2_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL3_DATA", REG_SMC, 0xd820210c, &ixTMON1_RDIL3_DATA[0], sizeof(ixTMON1_RDIL3_DATA)/sizeof(ixTMON1_RDIL3_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL4_DATA", REG_SMC, 0xd8202110, &ixTMON1_RDIL4_DATA[0], sizeof(ixTMON1_RDIL4_DATA)/sizeof(ixTMON1_RDIL4_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL5_DATA", REG_SMC, 0xd8202114, &ixTMON1_RDIL5_DATA[0], sizeof(ixTMON1_RDIL5_DATA)/sizeof(ixTMON1_RDIL5_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL6_DATA", REG_SMC, 0xd8202118, &ixTMON1_RDIL6_DATA[0], sizeof(ixTMON1_RDIL6_DATA)/sizeof(ixTMON1_RDIL6_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL7_DATA", REG_SMC, 0xd820211c, &ixTMON1_RDIL7_DATA[0], sizeof(ixTMON1_RDIL7_DATA)/sizeof(ixTMON1_RDIL7_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL8_DATA", REG_SMC, 0xd8202120, &ixTMON1_RDIL8_DATA[0], sizeof(ixTMON1_RDIL8_DATA)/sizeof(ixTMON1_RDIL8_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL9_DATA", REG_SMC, 0xd8202124, &ixTMON1_RDIL9_DATA[0], sizeof(ixTMON1_RDIL9_DATA)/sizeof(ixTMON1_RDIL9_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL10_DATA", REG_SMC, 0xd8202128, &ixTMON1_RDIL10_DATA[0], sizeof(ixTMON1_RDIL10_DATA)/sizeof(ixTMON1_RDIL10_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL11_DATA", REG_SMC, 0xd820212c, &ixTMON1_RDIL11_DATA[0], sizeof(ixTMON1_RDIL11_DATA)/sizeof(ixTMON1_RDIL11_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL12_DATA", REG_SMC, 0xd8202130, &ixTMON1_RDIL12_DATA[0], sizeof(ixTMON1_RDIL12_DATA)/sizeof(ixTMON1_RDIL12_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL13_DATA", REG_SMC, 0xd8202134, &ixTMON1_RDIL13_DATA[0], sizeof(ixTMON1_RDIL13_DATA)/sizeof(ixTMON1_RDIL13_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL14_DATA", REG_SMC, 0xd8202138, &ixTMON1_RDIL14_DATA[0], sizeof(ixTMON1_RDIL14_DATA)/sizeof(ixTMON1_RDIL14_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL15_DATA", REG_SMC, 0xd820213c, &ixTMON1_RDIL15_DATA[0], sizeof(ixTMON1_RDIL15_DATA)/sizeof(ixTMON1_RDIL15_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR0_DATA", REG_SMC, 0xd8202140, &ixTMON1_RDIR0_DATA[0], sizeof(ixTMON1_RDIR0_DATA)/sizeof(ixTMON1_RDIR0_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR1_DATA", REG_SMC, 0xd8202144, &ixTMON1_RDIR1_DATA[0], sizeof(ixTMON1_RDIR1_DATA)/sizeof(ixTMON1_RDIR1_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR2_DATA", REG_SMC, 0xd8202148, &ixTMON1_RDIR2_DATA[0], sizeof(ixTMON1_RDIR2_DATA)/sizeof(ixTMON1_RDIR2_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR3_DATA", REG_SMC, 0xd820214c, &ixTMON1_RDIR3_DATA[0], sizeof(ixTMON1_RDIR3_DATA)/sizeof(ixTMON1_RDIR3_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR4_DATA", REG_SMC, 0xd8202150, &ixTMON1_RDIR4_DATA[0], sizeof(ixTMON1_RDIR4_DATA)/sizeof(ixTMON1_RDIR4_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR5_DATA", REG_SMC, 0xd8202154, &ixTMON1_RDIR5_DATA[0], sizeof(ixTMON1_RDIR5_DATA)/sizeof(ixTMON1_RDIR5_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR6_DATA", REG_SMC, 0xd8202158, &ixTMON1_RDIR6_DATA[0], sizeof(ixTMON1_RDIR6_DATA)/sizeof(ixTMON1_RDIR6_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR7_DATA", REG_SMC, 0xd820215c, &ixTMON1_RDIR7_DATA[0], sizeof(ixTMON1_RDIR7_DATA)/sizeof(ixTMON1_RDIR7_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR8_DATA", REG_SMC, 0xd8202160, &ixTMON1_RDIR8_DATA[0], sizeof(ixTMON1_RDIR8_DATA)/sizeof(ixTMON1_RDIR8_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR9_DATA", REG_SMC, 0xd8202164, &ixTMON1_RDIR9_DATA[0], sizeof(ixTMON1_RDIR9_DATA)/sizeof(ixTMON1_RDIR9_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR10_DATA", REG_SMC, 0xd8202168, &ixTMON1_RDIR10_DATA[0], sizeof(ixTMON1_RDIR10_DATA)/sizeof(ixTMON1_RDIR10_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR11_DATA", REG_SMC, 0xd820216c, &ixTMON1_RDIR11_DATA[0], sizeof(ixTMON1_RDIR11_DATA)/sizeof(ixTMON1_RDIR11_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR12_DATA", REG_SMC, 0xd8202170, &ixTMON1_RDIR12_DATA[0], sizeof(ixTMON1_RDIR12_DATA)/sizeof(ixTMON1_RDIR12_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR13_DATA", REG_SMC, 0xd8202174, &ixTMON1_RDIR13_DATA[0], sizeof(ixTMON1_RDIR13_DATA)/sizeof(ixTMON1_RDIR13_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR14_DATA", REG_SMC, 0xd8202178, &ixTMON1_RDIR14_DATA[0], sizeof(ixTMON1_RDIR14_DATA)/sizeof(ixTMON1_RDIR14_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIR15_DATA", REG_SMC, 0xd820217c, &ixTMON1_RDIR15_DATA[0], sizeof(ixTMON1_RDIR15_DATA)/sizeof(ixTMON1_RDIR15_DATA[0]), 0, 0 },
+	{ "ixTMON1_INT_DATA", REG_SMC, 0xd8202180, &ixTMON1_INT_DATA[0], sizeof(ixTMON1_INT_DATA)/sizeof(ixTMON1_INT_DATA[0]), 0, 0 },
+	{ "ixTMON1_RDIL_PRESENT0", REG_SMC, 0xd8202184, &ixTMON1_RDIL_PRESENT0[0], sizeof(ixTMON1_RDIL_PRESENT0)/sizeof(ixTMON1_RDIL_PRESENT0[0]), 0, 0 },
+	{ "ixTMON1_RDIL_PRESENT1", REG_SMC, 0xd8202188, &ixTMON1_RDIL_PRESENT1[0], sizeof(ixTMON1_RDIL_PRESENT1)/sizeof(ixTMON1_RDIL_PRESENT1[0]), 0, 0 },
+	{ "ixTMON1_RDIR_PRESENT0", REG_SMC, 0xd820218c, &ixTMON1_RDIR_PRESENT0[0], sizeof(ixTMON1_RDIR_PRESENT0)/sizeof(ixTMON1_RDIR_PRESENT0[0]), 0, 0 },
+	{ "ixTMON1_RDIR_PRESENT1", REG_SMC, 0xd8202190, &ixTMON1_RDIR_PRESENT1[0], sizeof(ixTMON1_RDIR_PRESENT1)/sizeof(ixTMON1_RDIR_PRESENT1[0]), 0, 0 },
+	{ "ixTMON1_CONFIG", REG_SMC, 0xd8202198, &ixTMON1_CONFIG[0], sizeof(ixTMON1_CONFIG)/sizeof(ixTMON1_CONFIG[0]), 0, 0 },
+	{ "ixTMON1_TEMP_CALC_COEFF0", REG_SMC, 0xd82021a0, &ixTMON1_TEMP_CALC_COEFF0[0], sizeof(ixTMON1_TEMP_CALC_COEFF0)/sizeof(ixTMON1_TEMP_CALC_COEFF0[0]), 0, 0 },
+	{ "ixTMON1_TEMP_CALC_COEFF1", REG_SMC, 0xd82021a4, &ixTMON1_TEMP_CALC_COEFF1[0], sizeof(ixTMON1_TEMP_CALC_COEFF1)/sizeof(ixTMON1_TEMP_CALC_COEFF1[0]), 0, 0 },
+	{ "ixTMON1_TEMP_CALC_COEFF2", REG_SMC, 0xd82021a8, &ixTMON1_TEMP_CALC_COEFF2[0], sizeof(ixTMON1_TEMP_CALC_COEFF2)/sizeof(ixTMON1_TEMP_CALC_COEFF2[0]), 0, 0 },
+	{ "ixTMON1_TEMP_CALC_COEFF3", REG_SMC, 0xd82021ac, &ixTMON1_TEMP_CALC_COEFF3[0], sizeof(ixTMON1_TEMP_CALC_COEFF3)/sizeof(ixTMON1_TEMP_CALC_COEFF3[0]), 0, 0 },
+	{ "ixTMON1_TEMP_CALC_COEFF4", REG_SMC, 0xd82021b0, &ixTMON1_TEMP_CALC_COEFF4[0], sizeof(ixTMON1_TEMP_CALC_COEFF4)/sizeof(ixTMON1_TEMP_CALC_COEFF4[0]), 0, 0 },
+	{ "ixTMON1_DEBUG0", REG_SMC, 0xd82021b4, &ixTMON1_DEBUG0[0], sizeof(ixTMON1_DEBUG0)/sizeof(ixTMON1_DEBUG0[0]), 0, 0 },
+	{ "ixTMON1_DEBUG1", REG_SMC, 0xd82021b8, &ixTMON1_DEBUG1[0], sizeof(ixTMON1_DEBUG1)/sizeof(ixTMON1_DEBUG1[0]), 0, 0 },
+	{ "ixTHM_TMON0_REMOTE_START", REG_SMC, 0xd8202800, &ixTHM_TMON0_REMOTE_START[0], sizeof(ixTHM_TMON0_REMOTE_START)/sizeof(ixTHM_TMON0_REMOTE_START[0]), 0, 0 },
+	{ "ixTHM_TMON0_REMOTE_END", REG_SMC, 0xd82028fc, &ixTHM_TMON0_REMOTE_END[0], sizeof(ixTHM_TMON0_REMOTE_END)/sizeof(ixTHM_TMON0_REMOTE_END[0]), 0, 0 },
+	{ "ixTHM_TMON1_REMOTE_START", REG_SMC, 0xd8202900, &ixTHM_TMON1_REMOTE_START[0], sizeof(ixTHM_TMON1_REMOTE_START)/sizeof(ixTHM_TMON1_REMOTE_START[0]), 0, 0 },
+	{ "ixTHM_TMON1_REMOTE_END", REG_SMC, 0xd82029fc, &ixTHM_TMON1_REMOTE_END[0], sizeof(ixTHM_TMON1_REMOTE_END)/sizeof(ixTHM_TMON1_REMOTE_END[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL0", REG_SMC, 0xd8202e00, &ixTHM_TCON_LOCAL0[0], sizeof(ixTHM_TCON_LOCAL0)/sizeof(ixTHM_TCON_LOCAL0[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL1", REG_SMC, 0xd8202e04, &ixTHM_TCON_LOCAL1[0], sizeof(ixTHM_TCON_LOCAL1)/sizeof(ixTHM_TCON_LOCAL1[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL2", REG_SMC, 0xd8202e08, &ixTHM_TCON_LOCAL2[0], sizeof(ixTHM_TCON_LOCAL2)/sizeof(ixTHM_TCON_LOCAL2[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL3", REG_SMC, 0xd8202e0c, &ixTHM_TCON_LOCAL3[0], sizeof(ixTHM_TCON_LOCAL3)/sizeof(ixTHM_TCON_LOCAL3[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL4", REG_SMC, 0xd8202e10, &ixTHM_TCON_LOCAL4[0], sizeof(ixTHM_TCON_LOCAL4)/sizeof(ixTHM_TCON_LOCAL4[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL5", REG_SMC, 0xd8202e14, &ixTHM_TCON_LOCAL5[0], sizeof(ixTHM_TCON_LOCAL5)/sizeof(ixTHM_TCON_LOCAL5[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL6", REG_SMC, 0xd8202e18, &ixTHM_TCON_LOCAL6[0], sizeof(ixTHM_TCON_LOCAL6)/sizeof(ixTHM_TCON_LOCAL6[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL7", REG_SMC, 0xd8202e1c, &ixTHM_TCON_LOCAL7[0], sizeof(ixTHM_TCON_LOCAL7)/sizeof(ixTHM_TCON_LOCAL7[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL8", REG_SMC, 0xd8202e20, &ixTHM_TCON_LOCAL8[0], sizeof(ixTHM_TCON_LOCAL8)/sizeof(ixTHM_TCON_LOCAL8[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL9", REG_SMC, 0xd8202e24, &ixTHM_TCON_LOCAL9[0], sizeof(ixTHM_TCON_LOCAL9)/sizeof(ixTHM_TCON_LOCAL9[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL10", REG_SMC, 0xd8202e28, &ixTHM_TCON_LOCAL10[0], sizeof(ixTHM_TCON_LOCAL10)/sizeof(ixTHM_TCON_LOCAL10[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL11", REG_SMC, 0xd8202e2c, &ixTHM_TCON_LOCAL11[0], sizeof(ixTHM_TCON_LOCAL11)/sizeof(ixTHM_TCON_LOCAL11[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL12", REG_SMC, 0xd8202e30, &ixTHM_TCON_LOCAL12[0], sizeof(ixTHM_TCON_LOCAL12)/sizeof(ixTHM_TCON_LOCAL12[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL13", REG_SMC, 0xd8202ef8, &ixTHM_TCON_LOCAL13[0], sizeof(ixTHM_TCON_LOCAL13)/sizeof(ixTHM_TCON_LOCAL13[0]), 0, 0 },
+	{ "ixTHM_TCON_LOCAL14", REG_SMC, 0xd8202efc, &ixTHM_TCON_LOCAL14[0], sizeof(ixTHM_TCON_LOCAL14)/sizeof(ixTHM_TCON_LOCAL14[0]), 0, 0 },
+	{ "ixTHM_FUSE0", REG_SMC, 0xd8210000, &ixTHM_FUSE0[0], sizeof(ixTHM_FUSE0)/sizeof(ixTHM_FUSE0[0]), 0, 0 },
+	{ "ixTHM_FUSE1", REG_SMC, 0xd8210004, &ixTHM_FUSE1[0], sizeof(ixTHM_FUSE1)/sizeof(ixTHM_FUSE1[0]), 0, 0 },
+	{ "ixTHM_FUSE2", REG_SMC, 0xd8210008, &ixTHM_FUSE2[0], sizeof(ixTHM_FUSE2)/sizeof(ixTHM_FUSE2[0]), 0, 0 },
+	{ "ixTHM_FUSE3", REG_SMC, 0xd821000c, &ixTHM_FUSE3[0], sizeof(ixTHM_FUSE3)/sizeof(ixTHM_FUSE3[0]), 0, 0 },
+	{ "ixTHM_FUSE4", REG_SMC, 0xd8210010, &ixTHM_FUSE4[0], sizeof(ixTHM_FUSE4)/sizeof(ixTHM_FUSE4[0]), 0, 0 },
+	{ "ixTHM_FUSE5", REG_SMC, 0xd8210014, &ixTHM_FUSE5[0], sizeof(ixTHM_FUSE5)/sizeof(ixTHM_FUSE5[0]), 0, 0 },
+	{ "ixTHM_FUSE6", REG_SMC, 0xd8210018, &ixTHM_FUSE6[0], sizeof(ixTHM_FUSE6)/sizeof(ixTHM_FUSE6[0]), 0, 0 },
+	{ "ixTHM_FUSE7", REG_SMC, 0xd821001c, &ixTHM_FUSE7[0], sizeof(ixTHM_FUSE7)/sizeof(ixTHM_FUSE7[0]), 0, 0 },
+	{ "ixTHM_FUSE8", REG_SMC, 0xd8210020, &ixTHM_FUSE8[0], sizeof(ixTHM_FUSE8)/sizeof(ixTHM_FUSE8[0]), 0, 0 },
+	{ "ixTHM_FUSE9", REG_SMC, 0xd8210024, &ixTHM_FUSE9[0], sizeof(ixTHM_FUSE9)/sizeof(ixTHM_FUSE9[0]), 0, 0 },
+	{ "ixTHM_FUSE10", REG_SMC, 0xd8210028, &ixTHM_FUSE10[0], sizeof(ixTHM_FUSE10)/sizeof(ixTHM_FUSE10[0]), 0, 0 },
+	{ "ixTHM_FUSE11", REG_SMC, 0xd821002c, &ixTHM_FUSE11[0], sizeof(ixTHM_FUSE11)/sizeof(ixTHM_FUSE11[0]), 0, 0 },
+	{ "ixTHM_FUSE12", REG_SMC, 0xd8210030, &ixTHM_FUSE12[0], sizeof(ixTHM_FUSE12)/sizeof(ixTHM_FUSE12[0]), 0, 0 },
+	{ "ixGC_CAC_OVRD_CU", REG_SMC, 0xe7, &ixGC_CAC_OVRD_CU[0], sizeof(ixGC_CAC_OVRD_CU)/sizeof(ixGC_CAC_OVRD_CU[0]), 0, 0 },
diff --git a/src/lib/ip/uvd40.c b/src/lib/ip/uvd40.c
new file mode 100644
index 0000000..7b3cb0a
--- /dev/null
+++ b/src/lib/ip/uvd40.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "uvd40_bits.i"
+
+static const struct umr_reg uvd40_registers[] = {
+#include "uvd40_regs.i"
+};
+
+struct umr_ip_block *umr_create_uvd40(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "uvd4";
+	ip->no_regs = sizeof(uvd40_registers)/sizeof(uvd40_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(uvd40_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, uvd40_registers, sizeof(uvd40_registers));
+	return ip;
+}
diff --git a/src/lib/ip/uvd40_bits.i b/src/lib/ip/uvd40_bits.i
new file mode 100644
index 0000000..c6793af
--- /dev/null
+++ b/src/lib/ip/uvd40_bits.i
@@ -0,0 +1,511 @@
+static struct umr_bitfield ixUVD_MIF_CURR_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_MIF_REF_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_CACHE_CTRL[] = {
+	 { "CM_EN", 2, 2, &umr_bitfield_default },
+	 { "CM_FLUSH", 3, 3, &umr_bitfield_default },
+	 { "IT_EN", 0, 0, &umr_bitfield_default },
+	 { "IT_FLUSH", 1, 1, &umr_bitfield_default },
+	 { "VCPU_EN", 4, 4, &umr_bitfield_default },
+	 { "VCPU_FLUSH", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_SWAP_CNTL2[] = {
+	 { "SCPU_R_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SCPU_W_MC_SWAP", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_ADDR_EXT2[] = {
+	 { "SCPU_ADDR_EXT", 0, 3, &umr_bitfield_default },
+	 { "SCPU_NC0_ADDR_EXT", 8, 11, &umr_bitfield_default },
+	 { "SCPU_NC1_ADDR_EXT", 12, 15, &umr_bitfield_default },
+	 { "SCPU_VM_ADDR_EXT", 4, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_CGC_MEM_CTRL[] = {
+	 { "LCM_LS_EN", 13, 13, &umr_bitfield_default },
+	 { "LMI_MC_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "LS_CLEAR_DELAY", 20, 23, &umr_bitfield_default },
+	 { "LS_SET_DELAY", 16, 19, &umr_bitfield_default },
+	 { "MIF_LS_EN", 12, 12, &umr_bitfield_default },
+	 { "MPC_LS_EN", 1, 1, &umr_bitfield_default },
+	 { "MPRD_LS_EN", 2, 2, &umr_bitfield_default },
+	 { "SCPU_LS_EN", 11, 11, &umr_bitfield_default },
+	 { "SYS_LS_EN", 9, 9, &umr_bitfield_default },
+	 { "UDEC_CM_LS_EN", 5, 5, &umr_bitfield_default },
+	 { "UDEC_DB_LS_EN", 7, 7, &umr_bitfield_default },
+	 { "UDEC_IT_LS_EN", 6, 6, &umr_bitfield_default },
+	 { "UDEC_MP_LS_EN", 8, 8, &umr_bitfield_default },
+	 { "UDEC_RE_LS_EN", 4, 4, &umr_bitfield_default },
+	 { "VCPU_LS_EN", 10, 10, &umr_bitfield_default },
+	 { "WCB_LS_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_CGC_CTRL2[] = {
+	 { "DYN_OCLK_RAMP_EN", 0, 0, &umr_bitfield_default },
+	 { "DYN_RCLK_RAMP_EN", 1, 1, &umr_bitfield_default },
+	 { "GATER_DIV_ID", 2, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_MIF_RECON1_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_CONFIG[] = {
+	 { "UVD_PGFSM_FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "UVD_PGFSM_P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "UVD_PGFSM_P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "UVD_PGFSM_POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "UVD_PGFSM_POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "UVD_PGFSM_READ", 13, 13, &umr_bitfield_default },
+	 { "UVD_PGFSM_REG_ADDR", 28, 31, &umr_bitfield_default },
+	 { "UVD_PGFSM_WRITE", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE1[] = {
+	 { "UVD_PGFSM_READ_TILE1_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE2[] = {
+	 { "UVD_PGFSM_READ_TILE2_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_POWER_STATUS[] = {
+	 { "UVD_POWER_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_ADDR_LOW[] = {
+	 { "ADDR_22_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_ADDR_HIGH[] = {
+	 { "ADDR_42_23", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_CMD[] = {
+	 { "MODE", 6, 6, &umr_bitfield_default },
+	 { "REQ_CMD", 0, 3, &umr_bitfield_default },
+	 { "VMID_EN", 7, 7, &umr_bitfield_default },
+	 { "VMID", 8, 11, &umr_bitfield_default },
+	 { "WR_PHASE", 4, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_CMD[] = {
+	 { "CMD", 1, 30, &umr_bitfield_default },
+	 { "CMD_SEND", 0, 0, &umr_bitfield_default },
+	 { "CMD_SOURCE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_ENGINE_CNTL[] = {
+	 { "ENGINE_START", 0, 0, &umr_bitfield_default },
+	 { "ENGINE_START_MODE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_DB_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_DBW_ADDR_CONFIG[] = {
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_CNTL[] = {
+	 { "ADVANCED_MODE_DIS", 1, 1, &umr_bitfield_default },
+	 { "SEMAPHORE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_EXT40_ADDR[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+	 { "INDEX", 16, 20, &umr_bitfield_default },
+	 { "WRITE_ADDR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CTX_INDEX[] = {
+	 { "INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CTX_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_GATE[] = {
+	 { "IDCT", 7, 7, &umr_bitfield_default },
+	 { "LBSI", 10, 10, &umr_bitfield_default },
+	 { "LMI_MC", 5, 5, &umr_bitfield_default },
+	 { "LMI_UMC", 6, 6, &umr_bitfield_default },
+	 { "LRBBM", 11, 11, &umr_bitfield_default },
+	 { "MPC", 9, 9, &umr_bitfield_default },
+	 { "MPEG2", 2, 2, &umr_bitfield_default },
+	 { "MPRD", 8, 8, &umr_bitfield_default },
+	 { "RBC", 4, 4, &umr_bitfield_default },
+	 { "REGS", 3, 3, &umr_bitfield_default },
+	 { "SCPU", 19, 19, &umr_bitfield_default },
+	 { "SYS", 0, 0, &umr_bitfield_default },
+	 { "UDEC_CM", 13, 13, &umr_bitfield_default },
+	 { "UDEC_DB", 15, 15, &umr_bitfield_default },
+	 { "UDEC_IT", 14, 14, &umr_bitfield_default },
+	 { "UDEC", 1, 1, &umr_bitfield_default },
+	 { "UDEC_MP", 16, 16, &umr_bitfield_default },
+	 { "UDEC_RE", 12, 12, &umr_bitfield_default },
+	 { "VCPU", 18, 18, &umr_bitfield_default },
+	 { "WCB", 17, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_STATUS[] = {
+	 { "IDCT_SCLK", 14, 14, &umr_bitfield_default },
+	 { "IDCT_VCLK", 15, 15, &umr_bitfield_default },
+	 { "LBSI_SCLK", 21, 21, &umr_bitfield_default },
+	 { "LBSI_VCLK", 22, 22, &umr_bitfield_default },
+	 { "LMI_MC_SCLK", 12, 12, &umr_bitfield_default },
+	 { "LMI_UMC_SCLK", 13, 13, &umr_bitfield_default },
+	 { "LRBBM_SCLK", 23, 23, &umr_bitfield_default },
+	 { "MPC_DCLK", 20, 20, &umr_bitfield_default },
+	 { "MPC_SCLK", 19, 19, &umr_bitfield_default },
+	 { "MPEG2_DCLK", 7, 7, &umr_bitfield_default },
+	 { "MPEG2_SCLK", 6, 6, &umr_bitfield_default },
+	 { "MPEG2_VCLK", 8, 8, &umr_bitfield_default },
+	 { "MPRD_DCLK", 17, 17, &umr_bitfield_default },
+	 { "MPRD_SCLK", 16, 16, &umr_bitfield_default },
+	 { "MPRD_VCLK", 18, 18, &umr_bitfield_default },
+	 { "RBC_SCLK", 11, 11, &umr_bitfield_default },
+	 { "REGS_SCLK", 9, 9, &umr_bitfield_default },
+	 { "REGS_VCLK", 10, 10, &umr_bitfield_default },
+	 { "SCPU_SCLK", 27, 27, &umr_bitfield_default },
+	 { "SCPU_VCLK", 28, 28, &umr_bitfield_default },
+	 { "SYS_DCLK", 1, 1, &umr_bitfield_default },
+	 { "SYS_SCLK", 0, 0, &umr_bitfield_default },
+	 { "SYS_VCLK", 2, 2, &umr_bitfield_default },
+	 { "UDEC_DCLK", 4, 4, &umr_bitfield_default },
+	 { "UDEC_SCLK", 3, 3, &umr_bitfield_default },
+	 { "UDEC_VCLK", 5, 5, &umr_bitfield_default },
+	 { "VCPU_SCLK", 25, 25, &umr_bitfield_default },
+	 { "VCPU_VCLK", 26, 26, &umr_bitfield_default },
+	 { "WCB_SCLK", 24, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_CTRL[] = {
+	 { "CLK_GATE_DLY_TIMER", 2, 5, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 6, 10, &umr_bitfield_default },
+	 { "DYN_CLOCK_MODE", 0, 0, &umr_bitfield_default },
+	 { "IDCT_MODE", 23, 23, &umr_bitfield_default },
+	 { "LBSI_MODE", 26, 26, &umr_bitfield_default },
+	 { "LMI_MC_MODE", 21, 21, &umr_bitfield_default },
+	 { "LMI_UMC_MODE", 22, 22, &umr_bitfield_default },
+	 { "LRBBM_MODE", 27, 27, &umr_bitfield_default },
+	 { "MPC_MODE", 25, 25, &umr_bitfield_default },
+	 { "MPEG2_MODE", 18, 18, &umr_bitfield_default },
+	 { "MPRD_MODE", 24, 24, &umr_bitfield_default },
+	 { "RBC_MODE", 20, 20, &umr_bitfield_default },
+	 { "REGS_MODE", 19, 19, &umr_bitfield_default },
+	 { "SCPU_MODE", 30, 30, &umr_bitfield_default },
+	 { "SYS_MODE", 16, 16, &umr_bitfield_default },
+	 { "UDEC_CM_MODE", 12, 12, &umr_bitfield_default },
+	 { "UDEC_DB_MODE", 14, 14, &umr_bitfield_default },
+	 { "UDEC_IT_MODE", 13, 13, &umr_bitfield_default },
+	 { "UDEC_MODE", 17, 17, &umr_bitfield_default },
+	 { "UDEC_MP_MODE", 15, 15, &umr_bitfield_default },
+	 { "UDEC_RE_MODE", 11, 11, &umr_bitfield_default },
+	 { "VCPU_MODE", 29, 29, &umr_bitfield_default },
+	 { "WCB_MODE", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_UDEC_STATUS[] = {
+	 { "CM_DCLK", 4, 4, &umr_bitfield_default },
+	 { "CM_SCLK", 3, 3, &umr_bitfield_default },
+	 { "CM_VCLK", 5, 5, &umr_bitfield_default },
+	 { "DB_DCLK", 10, 10, &umr_bitfield_default },
+	 { "DB_SCLK", 9, 9, &umr_bitfield_default },
+	 { "DB_VCLK", 11, 11, &umr_bitfield_default },
+	 { "IT_DCLK", 7, 7, &umr_bitfield_default },
+	 { "IT_SCLK", 6, 6, &umr_bitfield_default },
+	 { "IT_VCLK", 8, 8, &umr_bitfield_default },
+	 { "MP_DCLK", 13, 13, &umr_bitfield_default },
+	 { "MP_SCLK", 12, 12, &umr_bitfield_default },
+	 { "MP_VCLK", 14, 14, &umr_bitfield_default },
+	 { "RE_DCLK", 1, 1, &umr_bitfield_default },
+	 { "RE_SCLK", 0, 0, &umr_bitfield_default },
+	 { "RE_VCLK", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET0[] = {
+	 { "CACHE_OFFSET0", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE0[] = {
+	 { "CACHE_SIZE0", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE1[] = {
+	 { "CACHE_SIZE1", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET2[] = {
+	 { "CACHE_OFFSET2", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE2[] = {
+	 { "CACHE_SIZE2", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_CTRL2[] = {
+	 { "ASSERT_UMC_URGENT", 2, 2, &umr_bitfield_default },
+	 { "DRCITF_BUBBLE_FIX_DIS", 7, 7, &umr_bitfield_default },
+	 { "MASK_UMC_URGENT", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WR_WATERMARK", 4, 6, &umr_bitfield_default },
+	 { "MC_READ_ID_SEL", 9, 10, &umr_bitfield_default },
+	 { "MC_WRITE_ID_SEL", 11, 12, &umr_bitfield_default },
+	 { "SPH_DIS", 0, 0, &umr_bitfield_default },
+	 { "SPU_EXTRA_CID_EN", 15, 15, &umr_bitfield_default },
+	 { "STALL_ARB", 1, 1, &umr_bitfield_default },
+	 { "STALL_ARB_UMC", 8, 8, &umr_bitfield_default },
+	 { "VCPU_NC0_EXT_EN", 13, 13, &umr_bitfield_default },
+	 { "VCPU_NC1_EXT_EN", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MASTINT_EN[] = {
+	 { "INT_OVERRUN", 4, 22, &umr_bitfield_default },
+	 { "OVERRUN_RST", 0, 0, &umr_bitfield_default },
+	 { "SYS_EN", 2, 2, &umr_bitfield_default },
+	 { "VCPU_EN", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_ADDR_EXT[] = {
+	 { "CM_ADDR_EXT", 4, 7, &umr_bitfield_default },
+	 { "IT_ADDR_EXT", 8, 11, &umr_bitfield_default },
+	 { "MP_ADDR_EXT", 20, 23, &umr_bitfield_default },
+	 { "RE_ADDR_EXT", 16, 19, &umr_bitfield_default },
+	 { "VCPU_ADDR_EXT", 0, 3, &umr_bitfield_default },
+	 { "VCPU_NC0_ADDR_EXT", 24, 27, &umr_bitfield_default },
+	 { "VCPU_NC1_ADDR_EXT", 28, 31, &umr_bitfield_default },
+	 { "VCPU_VM_ADDR_EXT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_CTRL[] = {
+	 { "ASSERT_MC_URGENT", 11, 11, &umr_bitfield_default },
+	 { "CM_DATA_COHERENCY_EN", 22, 22, &umr_bitfield_default },
+	 { "CRC_RESET", 14, 14, &umr_bitfield_default },
+	 { "CRC_SEL", 15, 19, &umr_bitfield_default },
+	 { "DATA_COHERENCY_EN", 13, 13, &umr_bitfield_default },
+	 { "DB_DB_DATA_COHERENCY_EN", 23, 23, &umr_bitfield_default },
+	 { "DB_IT_DATA_COHERENCY_EN", 24, 24, &umr_bitfield_default },
+	 { "DISABLE_ON_FWV_FAIL", 20, 20, &umr_bitfield_default },
+	 { "IT_IT_DATA_COHERENCY_EN", 25, 25, &umr_bitfield_default },
+	 { "MASK_MC_URGENT", 12, 12, &umr_bitfield_default },
+	 { "MIF_MIF_DATA_COHERENCY_EN", 26, 26, &umr_bitfield_default },
+	 { "REQ_MODE", 9, 9, &umr_bitfield_default },
+	 { "RFU", 27, 31, &umr_bitfield_default },
+	 { "RFU", 26, 31, &umr_bitfield_default },
+	 { "VCPU_DATA_COHERENCY_EN", 21, 21, &umr_bitfield_default },
+	 { "WRITE_CLEAN_TIMER_EN", 8, 8, &umr_bitfield_default },
+	 { "WRITE_CLEAN_TIMER", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_STATUS[] = {
+	 { "ADP_MC_READ_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "ADP_UMC_READ_CLEAN", 13, 13, &umr_bitfield_default },
+	 { "PENDING_UVD_MC_WRITE", 7, 7, &umr_bitfield_default },
+	 { "READ_CLEAN", 0, 0, &umr_bitfield_default },
+	 { "READ_CLEAN_RAW", 8, 8, &umr_bitfield_default },
+	 { "UMC_AVP_IDLE", 11, 11, &umr_bitfield_default },
+	 { "UMC_READ_CLEAN", 4, 4, &umr_bitfield_default },
+	 { "UMC_READ_CLEAN_RAW", 9, 9, &umr_bitfield_default },
+	 { "UMC_UVD_IDLE", 10, 10, &umr_bitfield_default },
+	 { "UMC_WRITE_CLEAN", 5, 5, &umr_bitfield_default },
+	 { "UMC_WRITE_CLEAN_RAW", 6, 6, &umr_bitfield_default },
+	 { "VCPU_LMI_WRITE_CLEAN", 3, 3, &umr_bitfield_default },
+	 { "WRITE_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "WRITE_CLEAN_RAW", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_SWAP_CNTL[] = {
+	 { "CM_MC_SWAP", 10, 11, &umr_bitfield_default },
+	 { "CSM_MC_SWAP", 18, 19, &umr_bitfield_default },
+	 { "DB_R_MC_SWAP", 14, 15, &umr_bitfield_default },
+	 { "DB_W_MC_SWAP", 16, 17, &umr_bitfield_default },
+	 { "DBW_MC_SWAP", 24, 25, &umr_bitfield_default },
+	 { "IB_MC_SWAP", 2, 3, &umr_bitfield_default },
+	 { "IT_MC_SWAP", 12, 13, &umr_bitfield_default },
+	 { "MP_MC_SWAP", 30, 31, &umr_bitfield_default },
+	 { "MP_REF16_MC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "RB_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RB_RPTR_MC_SWAP", 4, 5, &umr_bitfield_default },
+	 { "RB_WR_MC_SWAP", 26, 27, &umr_bitfield_default },
+	 { "RE_MC_SWAP", 28, 29, &umr_bitfield_default },
+	 { "VCPU_R_MC_SWAP", 6, 7, &umr_bitfield_default },
+	 { "VCPU_W_MC_SWAP", 8, 9, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MP_SWAP_CNTL[] = {
+	 { "MP_REF0_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "MP_REF10_MC_SWAP", 20, 21, &umr_bitfield_default },
+	 { "MP_REF11_MC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "MP_REF12_MC_SWAP", 24, 25, &umr_bitfield_default },
+	 { "MP_REF13_MC_SWAP", 26, 27, &umr_bitfield_default },
+	 { "MP_REF14_MC_SWAP", 28, 29, &umr_bitfield_default },
+	 { "MP_REF15_MC_SWAP", 30, 31, &umr_bitfield_default },
+	 { "MP_REF1_MC_SWAP", 2, 3, &umr_bitfield_default },
+	 { "MP_REF2_MC_SWAP", 4, 5, &umr_bitfield_default },
+	 { "MP_REF3_MC_SWAP", 6, 7, &umr_bitfield_default },
+	 { "MP_REF4_MC_SWAP", 8, 9, &umr_bitfield_default },
+	 { "MP_REF5_MC_SWAP", 10, 11, &umr_bitfield_default },
+	 { "MP_REF6_MC_SWAP", 12, 13, &umr_bitfield_default },
+	 { "MP_REF7_MC_SWAP", 14, 15, &umr_bitfield_default },
+	 { "MP_REF8_MC_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MP_REF9_MC_SWAP", 18, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_CNTL[] = {
+	 { "AVE_WEIGHT", 16, 17, &umr_bitfield_default },
+	 { "DBG_MUX", 8, 10, &umr_bitfield_default },
+	 { "PERF_RST", 6, 6, &umr_bitfield_default },
+	 { "REPLACEMENT_MODE", 3, 5, &umr_bitfield_default },
+	 { "URGENT_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXA0[] = {
+	 { "VARA_0", 0, 5, &umr_bitfield_default },
+	 { "VARA_1", 6, 11, &umr_bitfield_default },
+	 { "VARA_2", 12, 17, &umr_bitfield_default },
+	 { "VARA_3", 18, 23, &umr_bitfield_default },
+	 { "VARA_4", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXA1[] = {
+	 { "VARA_5", 0, 5, &umr_bitfield_default },
+	 { "VARA_6", 6, 11, &umr_bitfield_default },
+	 { "VARA_7", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXB0[] = {
+	 { "VARB_0", 0, 5, &umr_bitfield_default },
+	 { "VARB_1", 6, 11, &umr_bitfield_default },
+	 { "VARB_2", 12, 17, &umr_bitfield_default },
+	 { "VARB_3", 18, 23, &umr_bitfield_default },
+	 { "VARB_4", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXB1[] = {
+	 { "VARB_5", 0, 5, &umr_bitfield_default },
+	 { "VARB_6", 6, 11, &umr_bitfield_default },
+	 { "VARB_7", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUX[] = {
+	 { "SET_0", 0, 2, &umr_bitfield_default },
+	 { "SET_1", 3, 5, &umr_bitfield_default },
+	 { "SET_2", 6, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_ALU[] = {
+	 { "FUNCT", 0, 2, &umr_bitfield_default },
+	 { "OPERAND", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CNTL[] = {
+	 { "ABORT_REQ", 8, 8, &umr_bitfield_default },
+	 { "AXI_MAX_BRST_SIZE_IS_4", 4, 4, &umr_bitfield_default },
+	 { "CABAC_MB_ACC", 28, 28, &umr_bitfield_default },
+	 { "CLK_ACTIVE", 17, 17, &umr_bitfield_default },
+	 { "CLK_EN", 9, 9, &umr_bitfield_default },
+	 { "DBG_MUX", 13, 15, &umr_bitfield_default },
+	 { "ECPU_AM32_EN", 29, 29, &umr_bitfield_default },
+	 { "IRQ_ERR", 0, 3, &umr_bitfield_default },
+	 { "JTAG_EN", 16, 16, &umr_bitfield_default },
+	 { "PMB_ED_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "PMB_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "PRB_TIMEOUT_VAL", 20, 27, &umr_bitfield_default },
+	 { "RBBM_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "TIMEOUT_DIS", 18, 18, &umr_bitfield_default },
+	 { "TRCE_EN", 10, 10, &umr_bitfield_default },
+	 { "TRCE_MUX", 11, 12, &umr_bitfield_default },
+	 { "WMV9_EN", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SOFT_RESET[] = {
+	 { "CSM_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "CXW_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "FWV_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "IDCT_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "IH_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "LBSI_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "LCM_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "LMI_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "LMI_UMC_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "MIF_SOFT_RESET", 15, 15, &umr_bitfield_default },
+	 { "MPC_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "MPRD_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "RBC_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "SPH_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "TAP_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "UDEC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "VCPU_SOFT_RESET", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_IB_BASE[] = {
+	 { "IB_BASE", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_IB_SIZE[] = {
+	 { "IB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_BASE[] = {
+	 { "RB_BASE", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_RPTR[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_WPTR[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_CNTL[] = {
+	 { "RB_BLKSZ", 8, 12, &umr_bitfield_default },
+	 { "RB_BUFSZ", 0, 4, &umr_bitfield_default },
+	 { "RB_NO_FETCH", 16, 16, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "RB_RPTR_WR_EN", 28, 28, &umr_bitfield_default },
+	 { "RB_WPTR_POLL_EN", 20, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_RPTR_ADDR[] = {
+	 { "RB_RPTR_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_STATUS[] = {
+	 { "RBC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VCPU_REPORT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_TIMEOUT_STATUS[] = {
+	 { "SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT", 2, 2, &umr_bitfield_default },
+	 { "SEMAPHORE_TIMEOUT_CLEAR", 3, 3, &umr_bitfield_default },
+	 { "SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT", 1, 1, &umr_bitfield_default },
+	 { "SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[] = {
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+	 { "WAIT_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default },
+	 { "WAIT_INCOMPLETE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[] = {
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+	 { "WAIT_FAULT_COUNT", 1, 20, &umr_bitfield_default },
+	 { "WAIT_FAULT_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[] = {
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+	 { "SIGNAL_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default },
+	 { "SIGNAL_INCOMPLETE_EN", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CONTEXT_ID[] = {
+	 { "CONTEXT_ID", 0, 31, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/uvd40_regs.i b/src/lib/ip/uvd40_regs.i
new file mode 100644
index 0000000..6365806
--- /dev/null
+++ b/src/lib/ip/uvd40_regs.i
@@ -0,0 +1,68 @@
+	{ "ixUVD_MIF_CURR_ADDR_CONFIG", REG_SMC, 0x0048, &ixUVD_MIF_CURR_ADDR_CONFIG[0], sizeof(ixUVD_MIF_CURR_ADDR_CONFIG)/sizeof(ixUVD_MIF_CURR_ADDR_CONFIG[0]), 0, 0 },
+	{ "ixUVD_MIF_REF_ADDR_CONFIG", REG_SMC, 0x004C, &ixUVD_MIF_REF_ADDR_CONFIG[0], sizeof(ixUVD_MIF_REF_ADDR_CONFIG)/sizeof(ixUVD_MIF_REF_ADDR_CONFIG[0]), 0, 0 },
+	{ "ixUVD_LMI_CACHE_CTRL", REG_SMC, 0x009B, &ixUVD_LMI_CACHE_CTRL[0], sizeof(ixUVD_LMI_CACHE_CTRL)/sizeof(ixUVD_LMI_CACHE_CTRL[0]), 0, 0 },
+	{ "ixUVD_LMI_SWAP_CNTL2", REG_SMC, 0x00AA, &ixUVD_LMI_SWAP_CNTL2[0], sizeof(ixUVD_LMI_SWAP_CNTL2)/sizeof(ixUVD_LMI_SWAP_CNTL2[0]), 0, 0 },
+	{ "ixUVD_LMI_ADDR_EXT2", REG_SMC, 0x00AB, &ixUVD_LMI_ADDR_EXT2[0], sizeof(ixUVD_LMI_ADDR_EXT2)/sizeof(ixUVD_LMI_ADDR_EXT2[0]), 0, 0 },
+	{ "ixUVD_CGC_MEM_CTRL", REG_SMC, 0x00C0, &ixUVD_CGC_MEM_CTRL[0], sizeof(ixUVD_CGC_MEM_CTRL)/sizeof(ixUVD_CGC_MEM_CTRL[0]), 0, 0 },
+	{ "ixUVD_CGC_CTRL2", REG_SMC, 0x00C1, &ixUVD_CGC_CTRL2[0], sizeof(ixUVD_CGC_CTRL2)/sizeof(ixUVD_CGC_CTRL2[0]), 0, 0 },
+	{ "ixUVD_MIF_RECON1_ADDR_CONFIG", REG_SMC, 0x0114, &ixUVD_MIF_RECON1_ADDR_CONFIG[0], sizeof(ixUVD_MIF_RECON1_ADDR_CONFIG)/sizeof(ixUVD_MIF_RECON1_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_PGFSM_CONFIG", REG_MMIO, 0x38F8, &mmUVD_PGFSM_CONFIG[0], sizeof(mmUVD_PGFSM_CONFIG)/sizeof(mmUVD_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE1", REG_MMIO, 0x38FA, &mmUVD_PGFSM_READ_TILE1[0], sizeof(mmUVD_PGFSM_READ_TILE1)/sizeof(mmUVD_PGFSM_READ_TILE1[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE2", REG_MMIO, 0x38FB, &mmUVD_PGFSM_READ_TILE2[0], sizeof(mmUVD_PGFSM_READ_TILE2)/sizeof(mmUVD_PGFSM_READ_TILE2[0]), 0, 0 },
+	{ "mmUVD_POWER_STATUS", REG_MMIO, 0x38FC, &mmUVD_POWER_STATUS[0], sizeof(mmUVD_POWER_STATUS)/sizeof(mmUVD_POWER_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_ADDR_LOW", REG_MMIO, 0x3BC0, &mmUVD_SEMA_ADDR_LOW[0], sizeof(mmUVD_SEMA_ADDR_LOW)/sizeof(mmUVD_SEMA_ADDR_LOW[0]), 0, 0 },
+	{ "mmUVD_SEMA_ADDR_HIGH", REG_MMIO, 0x3BC1, &mmUVD_SEMA_ADDR_HIGH[0], sizeof(mmUVD_SEMA_ADDR_HIGH)/sizeof(mmUVD_SEMA_ADDR_HIGH[0]), 0, 0 },
+	{ "mmUVD_SEMA_CMD", REG_MMIO, 0x3BC2, &mmUVD_SEMA_CMD[0], sizeof(mmUVD_SEMA_CMD)/sizeof(mmUVD_SEMA_CMD[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_CMD", REG_MMIO, 0x3BC3, &mmUVD_GPCOM_VCPU_CMD[0], sizeof(mmUVD_GPCOM_VCPU_CMD)/sizeof(mmUVD_GPCOM_VCPU_CMD[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_DATA0", REG_MMIO, 0x3BC4, &mmUVD_GPCOM_VCPU_DATA0[0], sizeof(mmUVD_GPCOM_VCPU_DATA0)/sizeof(mmUVD_GPCOM_VCPU_DATA0[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_DATA1", REG_MMIO, 0x3BC5, &mmUVD_GPCOM_VCPU_DATA1[0], sizeof(mmUVD_GPCOM_VCPU_DATA1)/sizeof(mmUVD_GPCOM_VCPU_DATA1[0]), 0, 0 },
+	{ "mmUVD_ENGINE_CNTL", REG_MMIO, 0x3BC6, &mmUVD_ENGINE_CNTL[0], sizeof(mmUVD_ENGINE_CNTL)/sizeof(mmUVD_ENGINE_CNTL[0]), 0, 0 },
+	{ "mmUVD_UDEC_ADDR_CONFIG", REG_MMIO, 0x3BD3, &mmUVD_UDEC_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_ADDR_CONFIG)/sizeof(mmUVD_UDEC_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_UDEC_DB_ADDR_CONFIG", REG_MMIO, 0x3BD4, &mmUVD_UDEC_DB_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DB_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_UDEC_DBW_ADDR_CONFIG", REG_MMIO, 0x3BD5, &mmUVD_UDEC_DBW_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_NO_OP", REG_MMIO, 0x3BFF, NULL, 0, 0, 0 },
+	{ "mmUVD_SEMA_CNTL", REG_MMIO, 0x3D00, &mmUVD_SEMA_CNTL[0], sizeof(mmUVD_SEMA_CNTL)/sizeof(mmUVD_SEMA_CNTL[0]), 0, 0 },
+	{ "mmUVD_LMI_EXT40_ADDR", REG_MMIO, 0x3D26, &mmUVD_LMI_EXT40_ADDR[0], sizeof(mmUVD_LMI_EXT40_ADDR)/sizeof(mmUVD_LMI_EXT40_ADDR[0]), 0, 0 },
+	{ "mmUVD_CTX_INDEX", REG_MMIO, 0x3D28, &mmUVD_CTX_INDEX[0], sizeof(mmUVD_CTX_INDEX)/sizeof(mmUVD_CTX_INDEX[0]), 0, 0 },
+	{ "mmUVD_CTX_DATA", REG_MMIO, 0x3D29, &mmUVD_CTX_DATA[0], sizeof(mmUVD_CTX_DATA)/sizeof(mmUVD_CTX_DATA[0]), 0, 0 },
+	{ "mmUVD_CGC_GATE", REG_MMIO, 0x3D2A, &mmUVD_CGC_GATE[0], sizeof(mmUVD_CGC_GATE)/sizeof(mmUVD_CGC_GATE[0]), 0, 0 },
+	{ "mmUVD_CGC_STATUS", REG_MMIO, 0x3D2B, &mmUVD_CGC_STATUS[0], sizeof(mmUVD_CGC_STATUS)/sizeof(mmUVD_CGC_STATUS[0]), 0, 0 },
+	{ "mmUVD_CGC_CTRL", REG_MMIO, 0x3D2C, &mmUVD_CGC_CTRL[0], sizeof(mmUVD_CGC_CTRL)/sizeof(mmUVD_CGC_CTRL[0]), 0, 0 },
+	{ "mmUVD_CGC_UDEC_STATUS", REG_MMIO, 0x3D2D, &mmUVD_CGC_UDEC_STATUS[0], sizeof(mmUVD_CGC_UDEC_STATUS)/sizeof(mmUVD_CGC_UDEC_STATUS[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET0", REG_MMIO, 0x3D36, &mmUVD_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_VCPU_CACHE_OFFSET0[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE0", REG_MMIO, 0x3D37, &mmUVD_VCPU_CACHE_SIZE0[0], sizeof(mmUVD_VCPU_CACHE_SIZE0)/sizeof(mmUVD_VCPU_CACHE_SIZE0[0]), 0, 0 },
+	{ "mmUVD_GP_SCRATCH4", REG_MMIO, 0x3D38, NULL, 0, 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE1", REG_MMIO, 0x3D39, &mmUVD_VCPU_CACHE_SIZE1[0], sizeof(mmUVD_VCPU_CACHE_SIZE1)/sizeof(mmUVD_VCPU_CACHE_SIZE1[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET2", REG_MMIO, 0x3D3A, &mmUVD_VCPU_CACHE_OFFSET2[0], sizeof(mmUVD_VCPU_CACHE_OFFSET2)/sizeof(mmUVD_VCPU_CACHE_OFFSET2[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE2", REG_MMIO, 0x3D3B, &mmUVD_VCPU_CACHE_SIZE2[0], sizeof(mmUVD_VCPU_CACHE_SIZE2)/sizeof(mmUVD_VCPU_CACHE_SIZE2[0]), 0, 0 },
+	{ "mmUVD_LMI_CTRL2", REG_MMIO, 0x3D3D, &mmUVD_LMI_CTRL2[0], sizeof(mmUVD_LMI_CTRL2)/sizeof(mmUVD_LMI_CTRL2[0]), 0, 0 },
+	{ "mmUVD_MASTINT_EN", REG_MMIO, 0x3D40, &mmUVD_MASTINT_EN[0], sizeof(mmUVD_MASTINT_EN)/sizeof(mmUVD_MASTINT_EN[0]), 0, 0 },
+	{ "mmUVD_LMI_ADDR_EXT", REG_MMIO, 0x3D65, &mmUVD_LMI_ADDR_EXT[0], sizeof(mmUVD_LMI_ADDR_EXT)/sizeof(mmUVD_LMI_ADDR_EXT[0]), 0, 0 },
+	{ "mmUVD_LMI_CTRL", REG_MMIO, 0x3D66, &mmUVD_LMI_CTRL[0], sizeof(mmUVD_LMI_CTRL)/sizeof(mmUVD_LMI_CTRL[0]), 0, 0 },
+	{ "mmUVD_LMI_STATUS", REG_MMIO, 0x3D67, &mmUVD_LMI_STATUS[0], sizeof(mmUVD_LMI_STATUS)/sizeof(mmUVD_LMI_STATUS[0]), 0, 0 },
+	{ "mmUVD_LMI_SWAP_CNTL", REG_MMIO, 0x3D6D, &mmUVD_LMI_SWAP_CNTL[0], sizeof(mmUVD_LMI_SWAP_CNTL)/sizeof(mmUVD_LMI_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUVD_MP_SWAP_CNTL", REG_MMIO, 0x3D6F, &mmUVD_MP_SWAP_CNTL[0], sizeof(mmUVD_MP_SWAP_CNTL)/sizeof(mmUVD_MP_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUVD_MPC_CNTL", REG_MMIO, 0x3D77, &mmUVD_MPC_CNTL[0], sizeof(mmUVD_MPC_CNTL)/sizeof(mmUVD_MPC_CNTL[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXA0", REG_MMIO, 0x3D79, &mmUVD_MPC_SET_MUXA0[0], sizeof(mmUVD_MPC_SET_MUXA0)/sizeof(mmUVD_MPC_SET_MUXA0[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXA1", REG_MMIO, 0x3D7A, &mmUVD_MPC_SET_MUXA1[0], sizeof(mmUVD_MPC_SET_MUXA1)/sizeof(mmUVD_MPC_SET_MUXA1[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXB0", REG_MMIO, 0x3D7B, &mmUVD_MPC_SET_MUXB0[0], sizeof(mmUVD_MPC_SET_MUXB0)/sizeof(mmUVD_MPC_SET_MUXB0[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXB1", REG_MMIO, 0x3D7C, &mmUVD_MPC_SET_MUXB1[0], sizeof(mmUVD_MPC_SET_MUXB1)/sizeof(mmUVD_MPC_SET_MUXB1[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUX", REG_MMIO, 0x3D7D, &mmUVD_MPC_SET_MUX[0], sizeof(mmUVD_MPC_SET_MUX)/sizeof(mmUVD_MPC_SET_MUX[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_ALU", REG_MMIO, 0x3D7E, &mmUVD_MPC_SET_ALU[0], sizeof(mmUVD_MPC_SET_ALU)/sizeof(mmUVD_MPC_SET_ALU[0]), 0, 0 },
+	{ "mmUVD_VCPU_CNTL", REG_MMIO, 0x3D98, &mmUVD_VCPU_CNTL[0], sizeof(mmUVD_VCPU_CNTL)/sizeof(mmUVD_VCPU_CNTL[0]), 0, 0 },
+	{ "mmUVD_SOFT_RESET", REG_MMIO, 0x3DA0, &mmUVD_SOFT_RESET[0], sizeof(mmUVD_SOFT_RESET)/sizeof(mmUVD_SOFT_RESET[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_BASE", REG_MMIO, 0x3DA1, &mmUVD_RBC_IB_BASE[0], sizeof(mmUVD_RBC_IB_BASE)/sizeof(mmUVD_RBC_IB_BASE[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_SIZE", REG_MMIO, 0x3DA2, &mmUVD_RBC_IB_SIZE[0], sizeof(mmUVD_RBC_IB_SIZE)/sizeof(mmUVD_RBC_IB_SIZE[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_BASE", REG_MMIO, 0x3DA3, &mmUVD_RBC_RB_BASE[0], sizeof(mmUVD_RBC_RB_BASE)/sizeof(mmUVD_RBC_RB_BASE[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_RPTR", REG_MMIO, 0x3DA4, &mmUVD_RBC_RB_RPTR[0], sizeof(mmUVD_RBC_RB_RPTR)/sizeof(mmUVD_RBC_RB_RPTR[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_WPTR", REG_MMIO, 0x3DA5, &mmUVD_RBC_RB_WPTR[0], sizeof(mmUVD_RBC_RB_WPTR)/sizeof(mmUVD_RBC_RB_WPTR[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_WPTR_CNTL", REG_MMIO, 0x3DA6, NULL, 0, 0, 0 },
+	{ "mmUVD_RBC_RB_CNTL", REG_MMIO, 0x3DA9, &mmUVD_RBC_RB_CNTL[0], sizeof(mmUVD_RBC_RB_CNTL)/sizeof(mmUVD_RBC_RB_CNTL[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_RPTR_ADDR", REG_MMIO, 0x3DAA, &mmUVD_RBC_RB_RPTR_ADDR[0], sizeof(mmUVD_RBC_RB_RPTR_ADDR)/sizeof(mmUVD_RBC_RB_RPTR_ADDR[0]), 0, 0 },
+	{ "mmUVD_STATUS", REG_MMIO, 0x3DAF, &mmUVD_STATUS[0], sizeof(mmUVD_STATUS)/sizeof(mmUVD_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_TIMEOUT_STATUS", REG_MMIO, 0x3DB0, &mmUVD_SEMA_TIMEOUT_STATUS[0], sizeof(mmUVD_SEMA_TIMEOUT_STATUS)/sizeof(mmUVD_SEMA_TIMEOUT_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3DB1, &mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL", REG_MMIO, 0x3DB2, &mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3DB3, &mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_CONTEXT_ID", REG_MMIO, 0x3DBD, &mmUVD_CONTEXT_ID[0], sizeof(mmUVD_CONTEXT_ID)/sizeof(mmUVD_CONTEXT_ID[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_SIZE_UPDATE", REG_MMIO, 0x3DF1, NULL, 0, 0, 0 },
diff --git a/src/lib/ip/uvd42.c b/src/lib/ip/uvd42.c
new file mode 100644
index 0000000..3a2efb7
--- /dev/null
+++ b/src/lib/ip/uvd42.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "uvd42_bits.i"
+
+static const struct umr_reg uvd42_registers[] = {
+#include "uvd42_regs.i"
+};
+
+struct umr_ip_block *umr_create_uvd42(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "uvd42";
+	ip->no_regs = sizeof(uvd42_registers)/sizeof(uvd42_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(uvd42_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, uvd42_registers, sizeof(uvd42_registers));
+	return ip;
+}
diff --git a/src/lib/ip/uvd42_bits.i b/src/lib/ip/uvd42_bits.i
new file mode 100644
index 0000000..ec059e8
--- /dev/null
+++ b/src/lib/ip/uvd42_bits.i
@@ -0,0 +1,516 @@
+static struct umr_bitfield ixUVD_MIF_RECON1_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_CONFIG[] = {
+	 { "UVD_PGFSM_FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "UVD_PGFSM_POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "UVD_PGFSM_POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "UVD_PGFSM_P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "UVD_PGFSM_P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "UVD_PGFSM_WRITE", 12, 12, &umr_bitfield_default },
+	 { "UVD_PGFSM_READ", 13, 13, &umr_bitfield_default },
+	 { "UVD_PGFSM_REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE1[] = {
+	 { "UVD_PGFSM_READ_TILE1_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE2[] = {
+	 { "UVD_PGFSM_READ_TILE2_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_POWER_STATUS[] = {
+	 { "UVD_POWER_STATUS", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_ADDR_LOW[] = {
+	 { "ADDR_22_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_ADDR_HIGH[] = {
+	 { "ADDR_42_23", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_CMD[] = {
+	 { "REQ_CMD", 0, 3, &umr_bitfield_default },
+	 { "WR_PHASE", 4, 5, &umr_bitfield_default },
+	 { "MODE", 6, 6, &umr_bitfield_default },
+	 { "VMID_EN", 7, 7, &umr_bitfield_default },
+	 { "VMID", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_CMD[] = {
+	 { "CMD_SEND", 0, 0, &umr_bitfield_default },
+	 { "CMD", 1, 30, &umr_bitfield_default },
+	 { "CMD_SOURCE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_ENGINE_CNTL[] = {
+	 { "ENGINE_START", 0, 0, &umr_bitfield_default },
+	 { "ENGINE_START_MODE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_DB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_DBW_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_CNTL[] = {
+	 { "SEMAPHORE_EN", 0, 0, &umr_bitfield_default },
+	 { "ADVANCED_MODE_DIS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_EXT40_ADDR[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+	 { "INDEX", 16, 20, &umr_bitfield_default },
+	 { "WRITE_ADDR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CTX_INDEX[] = {
+	 { "INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CTX_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_GATE[] = {
+	 { "SYS", 0, 0, &umr_bitfield_default },
+	 { "UDEC", 1, 1, &umr_bitfield_default },
+	 { "MPEG2", 2, 2, &umr_bitfield_default },
+	 { "REGS", 3, 3, &umr_bitfield_default },
+	 { "RBC", 4, 4, &umr_bitfield_default },
+	 { "LMI_MC", 5, 5, &umr_bitfield_default },
+	 { "LMI_UMC", 6, 6, &umr_bitfield_default },
+	 { "IDCT", 7, 7, &umr_bitfield_default },
+	 { "MPRD", 8, 8, &umr_bitfield_default },
+	 { "MPC", 9, 9, &umr_bitfield_default },
+	 { "LBSI", 10, 10, &umr_bitfield_default },
+	 { "LRBBM", 11, 11, &umr_bitfield_default },
+	 { "UDEC_RE", 12, 12, &umr_bitfield_default },
+	 { "UDEC_CM", 13, 13, &umr_bitfield_default },
+	 { "UDEC_IT", 14, 14, &umr_bitfield_default },
+	 { "UDEC_DB", 15, 15, &umr_bitfield_default },
+	 { "UDEC_MP", 16, 16, &umr_bitfield_default },
+	 { "WCB", 17, 17, &umr_bitfield_default },
+	 { "VCPU", 18, 18, &umr_bitfield_default },
+	 { "SCPU", 19, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_STATUS[] = {
+	 { "SYS_SCLK", 0, 0, &umr_bitfield_default },
+	 { "SYS_DCLK", 1, 1, &umr_bitfield_default },
+	 { "SYS_VCLK", 2, 2, &umr_bitfield_default },
+	 { "UDEC_SCLK", 3, 3, &umr_bitfield_default },
+	 { "UDEC_DCLK", 4, 4, &umr_bitfield_default },
+	 { "UDEC_VCLK", 5, 5, &umr_bitfield_default },
+	 { "MPEG2_SCLK", 6, 6, &umr_bitfield_default },
+	 { "MPEG2_DCLK", 7, 7, &umr_bitfield_default },
+	 { "MPEG2_VCLK", 8, 8, &umr_bitfield_default },
+	 { "REGS_SCLK", 9, 9, &umr_bitfield_default },
+	 { "REGS_VCLK", 10, 10, &umr_bitfield_default },
+	 { "RBC_SCLK", 11, 11, &umr_bitfield_default },
+	 { "LMI_MC_SCLK", 12, 12, &umr_bitfield_default },
+	 { "LMI_UMC_SCLK", 13, 13, &umr_bitfield_default },
+	 { "IDCT_SCLK", 14, 14, &umr_bitfield_default },
+	 { "IDCT_VCLK", 15, 15, &umr_bitfield_default },
+	 { "MPRD_SCLK", 16, 16, &umr_bitfield_default },
+	 { "MPRD_DCLK", 17, 17, &umr_bitfield_default },
+	 { "MPRD_VCLK", 18, 18, &umr_bitfield_default },
+	 { "MPC_SCLK", 19, 19, &umr_bitfield_default },
+	 { "MPC_DCLK", 20, 20, &umr_bitfield_default },
+	 { "LBSI_SCLK", 21, 21, &umr_bitfield_default },
+	 { "LBSI_VCLK", 22, 22, &umr_bitfield_default },
+	 { "LRBBM_SCLK", 23, 23, &umr_bitfield_default },
+	 { "WCB_SCLK", 24, 24, &umr_bitfield_default },
+	 { "VCPU_SCLK", 25, 25, &umr_bitfield_default },
+	 { "VCPU_VCLK", 26, 26, &umr_bitfield_default },
+	 { "SCPU_SCLK", 27, 27, &umr_bitfield_default },
+	 { "SCPU_VCLK", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_CTRL[] = {
+	 { "DYN_CLOCK_MODE", 0, 0, &umr_bitfield_default },
+	 { "CLK_GATE_DLY_TIMER", 2, 5, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 6, 10, &umr_bitfield_default },
+	 { "UDEC_RE_MODE", 11, 11, &umr_bitfield_default },
+	 { "UDEC_CM_MODE", 12, 12, &umr_bitfield_default },
+	 { "UDEC_IT_MODE", 13, 13, &umr_bitfield_default },
+	 { "UDEC_DB_MODE", 14, 14, &umr_bitfield_default },
+	 { "UDEC_MP_MODE", 15, 15, &umr_bitfield_default },
+	 { "SYS_MODE", 16, 16, &umr_bitfield_default },
+	 { "UDEC_MODE", 17, 17, &umr_bitfield_default },
+	 { "MPEG2_MODE", 18, 18, &umr_bitfield_default },
+	 { "REGS_MODE", 19, 19, &umr_bitfield_default },
+	 { "RBC_MODE", 20, 20, &umr_bitfield_default },
+	 { "LMI_MC_MODE", 21, 21, &umr_bitfield_default },
+	 { "LMI_UMC_MODE", 22, 22, &umr_bitfield_default },
+	 { "IDCT_MODE", 23, 23, &umr_bitfield_default },
+	 { "MPRD_MODE", 24, 24, &umr_bitfield_default },
+	 { "MPC_MODE", 25, 25, &umr_bitfield_default },
+	 { "LBSI_MODE", 26, 26, &umr_bitfield_default },
+	 { "LRBBM_MODE", 27, 27, &umr_bitfield_default },
+	 { "WCB_MODE", 28, 28, &umr_bitfield_default },
+	 { "VCPU_MODE", 29, 29, &umr_bitfield_default },
+	 { "SCPU_MODE", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_UDEC_STATUS[] = {
+	 { "RE_SCLK", 0, 0, &umr_bitfield_default },
+	 { "RE_DCLK", 1, 1, &umr_bitfield_default },
+	 { "RE_VCLK", 2, 2, &umr_bitfield_default },
+	 { "CM_SCLK", 3, 3, &umr_bitfield_default },
+	 { "CM_DCLK", 4, 4, &umr_bitfield_default },
+	 { "CM_VCLK", 5, 5, &umr_bitfield_default },
+	 { "IT_SCLK", 6, 6, &umr_bitfield_default },
+	 { "IT_DCLK", 7, 7, &umr_bitfield_default },
+	 { "IT_VCLK", 8, 8, &umr_bitfield_default },
+	 { "DB_SCLK", 9, 9, &umr_bitfield_default },
+	 { "DB_DCLK", 10, 10, &umr_bitfield_default },
+	 { "DB_VCLK", 11, 11, &umr_bitfield_default },
+	 { "MP_SCLK", 12, 12, &umr_bitfield_default },
+	 { "MP_DCLK", 13, 13, &umr_bitfield_default },
+	 { "MP_VCLK", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_CTRL2[] = {
+	 { "SPH_DIS", 0, 0, &umr_bitfield_default },
+	 { "STALL_ARB", 1, 1, &umr_bitfield_default },
+	 { "ASSERT_UMC_URGENT", 2, 2, &umr_bitfield_default },
+	 { "MASK_UMC_URGENT", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WR_WATERMARK", 4, 6, &umr_bitfield_default },
+	 { "DRCITF_BUBBLE_FIX_DIS", 7, 7, &umr_bitfield_default },
+	 { "STALL_ARB_UMC", 8, 8, &umr_bitfield_default },
+	 { "MC_READ_ID_SEL", 9, 10, &umr_bitfield_default },
+	 { "MC_WRITE_ID_SEL", 11, 12, &umr_bitfield_default },
+	 { "VCPU_NC0_EXT_EN", 13, 13, &umr_bitfield_default },
+	 { "VCPU_NC1_EXT_EN", 14, 14, &umr_bitfield_default },
+	 { "SPU_EXTRA_CID_EN", 15, 15, &umr_bitfield_default },
+	 { "RE_OFFLOAD_EN", 16, 16, &umr_bitfield_default },
+	 { "RE_OFLD_MIF_WR_REQ_NUM", 17, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MASTINT_EN[] = {
+	 { "OVERRUN_RST", 0, 0, &umr_bitfield_default },
+	 { "VCPU_EN", 1, 1, &umr_bitfield_default },
+	 { "SYS_EN", 2, 2, &umr_bitfield_default },
+	 { "INT_OVERRUN", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_ADDR_EXT[] = {
+	 { "VCPU_ADDR_EXT", 0, 3, &umr_bitfield_default },
+	 { "CM_ADDR_EXT", 4, 7, &umr_bitfield_default },
+	 { "IT_ADDR_EXT", 8, 11, &umr_bitfield_default },
+	 { "VCPU_VM_ADDR_EXT", 12, 15, &umr_bitfield_default },
+	 { "RE_ADDR_EXT", 16, 19, &umr_bitfield_default },
+	 { "MP_ADDR_EXT", 20, 23, &umr_bitfield_default },
+	 { "VCPU_NC0_ADDR_EXT", 24, 27, &umr_bitfield_default },
+	 { "VCPU_NC1_ADDR_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_CTRL[] = {
+	 { "WRITE_CLEAN_TIMER", 0, 7, &umr_bitfield_default },
+	 { "WRITE_CLEAN_TIMER_EN", 8, 8, &umr_bitfield_default },
+	 { "REQ_MODE", 9, 9, &umr_bitfield_default },
+	 { "ASSERT_MC_URGENT", 11, 11, &umr_bitfield_default },
+	 { "MASK_MC_URGENT", 12, 12, &umr_bitfield_default },
+	 { "DATA_COHERENCY_EN", 13, 13, &umr_bitfield_default },
+	 { "CRC_RESET", 14, 14, &umr_bitfield_default },
+	 { "CRC_SEL", 15, 19, &umr_bitfield_default },
+	 { "DISABLE_ON_FWV_FAIL", 20, 20, &umr_bitfield_default },
+	 { "VCPU_DATA_COHERENCY_EN", 21, 21, &umr_bitfield_default },
+	 { "CM_DATA_COHERENCY_EN", 22, 22, &umr_bitfield_default },
+	 { "DB_DB_DATA_COHERENCY_EN", 23, 23, &umr_bitfield_default },
+	 { "DB_IT_DATA_COHERENCY_EN", 24, 24, &umr_bitfield_default },
+	 { "IT_IT_DATA_COHERENCY_EN", 25, 25, &umr_bitfield_default },
+	 { "MIF_MIF_DATA_COHERENCY_EN", 26, 26, &umr_bitfield_default },
+	 { "RFU", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_STATUS[] = {
+	 { "READ_CLEAN", 0, 0, &umr_bitfield_default },
+	 { "WRITE_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "WRITE_CLEAN_RAW", 2, 2, &umr_bitfield_default },
+	 { "VCPU_LMI_WRITE_CLEAN", 3, 3, &umr_bitfield_default },
+	 { "UMC_READ_CLEAN", 4, 4, &umr_bitfield_default },
+	 { "UMC_WRITE_CLEAN", 5, 5, &umr_bitfield_default },
+	 { "UMC_WRITE_CLEAN_RAW", 6, 6, &umr_bitfield_default },
+	 { "PENDING_UVD_MC_WRITE", 7, 7, &umr_bitfield_default },
+	 { "READ_CLEAN_RAW", 8, 8, &umr_bitfield_default },
+	 { "UMC_READ_CLEAN_RAW", 9, 9, &umr_bitfield_default },
+	 { "UMC_UVD_IDLE", 10, 10, &umr_bitfield_default },
+	 { "UMC_AVP_IDLE", 11, 11, &umr_bitfield_default },
+	 { "ADP_MC_READ_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "ADP_UMC_READ_CLEAN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_SWAP_CNTL[] = {
+	 { "RB_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "IB_MC_SWAP", 2, 3, &umr_bitfield_default },
+	 { "RB_RPTR_MC_SWAP", 4, 5, &umr_bitfield_default },
+	 { "VCPU_R_MC_SWAP", 6, 7, &umr_bitfield_default },
+	 { "VCPU_W_MC_SWAP", 8, 9, &umr_bitfield_default },
+	 { "CM_MC_SWAP", 10, 11, &umr_bitfield_default },
+	 { "IT_MC_SWAP", 12, 13, &umr_bitfield_default },
+	 { "DB_R_MC_SWAP", 14, 15, &umr_bitfield_default },
+	 { "DB_W_MC_SWAP", 16, 17, &umr_bitfield_default },
+	 { "CSM_MC_SWAP", 18, 19, &umr_bitfield_default },
+	 { "MP_REF16_MC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DBW_MC_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RB_WR_MC_SWAP", 26, 27, &umr_bitfield_default },
+	 { "RE_MC_SWAP", 28, 29, &umr_bitfield_default },
+	 { "MP_MC_SWAP", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MP_SWAP_CNTL[] = {
+	 { "MP_REF0_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "MP_REF1_MC_SWAP", 2, 3, &umr_bitfield_default },
+	 { "MP_REF2_MC_SWAP", 4, 5, &umr_bitfield_default },
+	 { "MP_REF3_MC_SWAP", 6, 7, &umr_bitfield_default },
+	 { "MP_REF4_MC_SWAP", 8, 9, &umr_bitfield_default },
+	 { "MP_REF5_MC_SWAP", 10, 11, &umr_bitfield_default },
+	 { "MP_REF6_MC_SWAP", 12, 13, &umr_bitfield_default },
+	 { "MP_REF7_MC_SWAP", 14, 15, &umr_bitfield_default },
+	 { "MP_REF8_MC_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MP_REF9_MC_SWAP", 18, 19, &umr_bitfield_default },
+	 { "MP_REF10_MC_SWAP", 20, 21, &umr_bitfield_default },
+	 { "MP_REF11_MC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "MP_REF12_MC_SWAP", 24, 25, &umr_bitfield_default },
+	 { "MP_REF13_MC_SWAP", 26, 27, &umr_bitfield_default },
+	 { "MP_REF14_MC_SWAP", 28, 29, &umr_bitfield_default },
+	 { "MP_REF15_MC_SWAP", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_CNTL[] = {
+	 { "REPLACEMENT_MODE", 3, 5, &umr_bitfield_default },
+	 { "PERF_RST", 6, 6, &umr_bitfield_default },
+	 { "DBG_MUX", 8, 10, &umr_bitfield_default },
+	 { "AVE_WEIGHT", 16, 17, &umr_bitfield_default },
+	 { "URGENT_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXA0[] = {
+	 { "VARA_0", 0, 5, &umr_bitfield_default },
+	 { "VARA_1", 6, 11, &umr_bitfield_default },
+	 { "VARA_2", 12, 17, &umr_bitfield_default },
+	 { "VARA_3", 18, 23, &umr_bitfield_default },
+	 { "VARA_4", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXA1[] = {
+	 { "VARA_5", 0, 5, &umr_bitfield_default },
+	 { "VARA_6", 6, 11, &umr_bitfield_default },
+	 { "VARA_7", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXB0[] = {
+	 { "VARB_0", 0, 5, &umr_bitfield_default },
+	 { "VARB_1", 6, 11, &umr_bitfield_default },
+	 { "VARB_2", 12, 17, &umr_bitfield_default },
+	 { "VARB_3", 18, 23, &umr_bitfield_default },
+	 { "VARB_4", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXB1[] = {
+	 { "VARB_5", 0, 5, &umr_bitfield_default },
+	 { "VARB_6", 6, 11, &umr_bitfield_default },
+	 { "VARB_7", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUX[] = {
+	 { "SET_0", 0, 2, &umr_bitfield_default },
+	 { "SET_1", 3, 5, &umr_bitfield_default },
+	 { "SET_2", 6, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_ALU[] = {
+	 { "FUNCT", 0, 2, &umr_bitfield_default },
+	 { "OPERAND", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET0[] = {
+	 { "CACHE_OFFSET0", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE0[] = {
+	 { "CACHE_SIZE0", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET1[] = {
+	 { "CACHE_OFFSET1", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE1[] = {
+	 { "CACHE_SIZE1", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET2[] = {
+	 { "CACHE_OFFSET2", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE2[] = {
+	 { "CACHE_SIZE2", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CNTL[] = {
+	 { "IRQ_ERR", 0, 3, &umr_bitfield_default },
+	 { "AXI_MAX_BRST_SIZE_IS_4", 4, 4, &umr_bitfield_default },
+	 { "PMB_ED_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "PMB_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "RBBM_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "ABORT_REQ", 8, 8, &umr_bitfield_default },
+	 { "CLK_EN", 9, 9, &umr_bitfield_default },
+	 { "TRCE_EN", 10, 10, &umr_bitfield_default },
+	 { "TRCE_MUX", 11, 12, &umr_bitfield_default },
+	 { "DBG_MUX", 13, 15, &umr_bitfield_default },
+	 { "JTAG_EN", 16, 16, &umr_bitfield_default },
+	 { "CLK_ACTIVE", 17, 17, &umr_bitfield_default },
+	 { "TIMEOUT_DIS", 18, 18, &umr_bitfield_default },
+	 { "PRB_TIMEOUT_VAL", 20, 27, &umr_bitfield_default },
+	 { "CABAC_MB_ACC", 28, 28, &umr_bitfield_default },
+	 { "ECPU_AM32_EN", 29, 29, &umr_bitfield_default },
+	 { "WMV9_EN", 30, 30, &umr_bitfield_default },
+	 { "RE_OFFLOAD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SOFT_RESET[] = {
+	 { "RBC_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "LBSI_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "LMI_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "VCPU_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "UDEC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "CSM_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "CXW_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "TAP_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "MPC_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "FWV_SOFT_RESET", 9, 9, &umr_bitfield_default },
+	 { "IH_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "MPRD_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "IDCT_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "LMI_UMC_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "SPH_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "MIF_SOFT_RESET", 15, 15, &umr_bitfield_default },
+	 { "LCM_SOFT_RESET", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_IB_BASE[] = {
+	 { "IB_BASE", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_IB_SIZE[] = {
+	 { "IB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_BASE[] = {
+	 { "RB_BASE", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_RPTR[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_WPTR[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_CNTL[] = {
+	 { "RB_BUFSZ", 0, 4, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 12, &umr_bitfield_default },
+	 { "RB_NO_FETCH", 16, 16, &umr_bitfield_default },
+	 { "RB_WPTR_POLL_EN", 20, 20, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "RB_RPTR_WR_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_RPTR_ADDR[] = {
+	 { "RB_RPTR_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_STATUS[] = {
+	 { "RBC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VCPU_REPORT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_TIMEOUT_STATUS[] = {
+	 { "SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT", 0, 0, &umr_bitfield_default },
+	 { "SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT", 1, 1, &umr_bitfield_default },
+	 { "SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT", 2, 2, &umr_bitfield_default },
+	 { "SEMAPHORE_TIMEOUT_CLEAR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[] = {
+	 { "WAIT_INCOMPLETE_EN", 0, 0, &umr_bitfield_default },
+	 { "WAIT_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[] = {
+	 { "WAIT_FAULT_EN", 0, 0, &umr_bitfield_default },
+	 { "WAIT_FAULT_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[] = {
+	 { "SIGNAL_INCOMPLETE_EN", 0, 0, &umr_bitfield_default },
+	 { "SIGNAL_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CONTEXT_ID[] = {
+	 { "CONTEXT_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_MIF_CURR_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_MIF_REF_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_CACHE_CTRL[] = {
+	 { "IT_EN", 0, 0, &umr_bitfield_default },
+	 { "IT_FLUSH", 1, 1, &umr_bitfield_default },
+	 { "CM_EN", 2, 2, &umr_bitfield_default },
+	 { "CM_FLUSH", 3, 3, &umr_bitfield_default },
+	 { "VCPU_EN", 4, 4, &umr_bitfield_default },
+	 { "VCPU_FLUSH", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_SWAP_CNTL2[] = {
+	 { "SCPU_R_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SCPU_W_MC_SWAP", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_ADDR_EXT2[] = {
+	 { "SCPU_ADDR_EXT", 0, 3, &umr_bitfield_default },
+	 { "SCPU_VM_ADDR_EXT", 4, 7, &umr_bitfield_default },
+	 { "SCPU_NC0_ADDR_EXT", 8, 11, &umr_bitfield_default },
+	 { "SCPU_NC1_ADDR_EXT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_CGC_MEM_CTRL[] = {
+	 { "LMI_MC_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "MPC_LS_EN", 1, 1, &umr_bitfield_default },
+	 { "MPRD_LS_EN", 2, 2, &umr_bitfield_default },
+	 { "WCB_LS_EN", 3, 3, &umr_bitfield_default },
+	 { "UDEC_RE_LS_EN", 4, 4, &umr_bitfield_default },
+	 { "UDEC_CM_LS_EN", 5, 5, &umr_bitfield_default },
+	 { "UDEC_IT_LS_EN", 6, 6, &umr_bitfield_default },
+	 { "UDEC_DB_LS_EN", 7, 7, &umr_bitfield_default },
+	 { "UDEC_MP_LS_EN", 8, 8, &umr_bitfield_default },
+	 { "SYS_LS_EN", 9, 9, &umr_bitfield_default },
+	 { "VCPU_LS_EN", 10, 10, &umr_bitfield_default },
+	 { "SCPU_LS_EN", 11, 11, &umr_bitfield_default },
+	 { "MIF_LS_EN", 12, 12, &umr_bitfield_default },
+	 { "LCM_LS_EN", 13, 13, &umr_bitfield_default },
+	 { "LS_SET_DELAY", 16, 19, &umr_bitfield_default },
+	 { "LS_CLEAR_DELAY", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_CGC_CTRL2[] = {
+	 { "DYN_OCLK_RAMP_EN", 0, 0, &umr_bitfield_default },
+	 { "DYN_RCLK_RAMP_EN", 1, 1, &umr_bitfield_default },
+	 { "GATER_DIV_ID", 2, 4, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/uvd42_regs.i b/src/lib/ip/uvd42_regs.i
new file mode 100644
index 0000000..82ad30c
--- /dev/null
+++ b/src/lib/ip/uvd42_regs.i
@@ -0,0 +1,68 @@
+	{ "ixUVD_MIF_RECON1_ADDR_CONFIG", REG_SMC, 0x114, &ixUVD_MIF_RECON1_ADDR_CONFIG[0], sizeof(ixUVD_MIF_RECON1_ADDR_CONFIG)/sizeof(ixUVD_MIF_RECON1_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_PGFSM_CONFIG", REG_MMIO, 0x38f8, &mmUVD_PGFSM_CONFIG[0], sizeof(mmUVD_PGFSM_CONFIG)/sizeof(mmUVD_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE1", REG_MMIO, 0x38fa, &mmUVD_PGFSM_READ_TILE1[0], sizeof(mmUVD_PGFSM_READ_TILE1)/sizeof(mmUVD_PGFSM_READ_TILE1[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE2", REG_MMIO, 0x38fb, &mmUVD_PGFSM_READ_TILE2[0], sizeof(mmUVD_PGFSM_READ_TILE2)/sizeof(mmUVD_PGFSM_READ_TILE2[0]), 0, 0 },
+	{ "mmUVD_POWER_STATUS", REG_MMIO, 0x38fc, &mmUVD_POWER_STATUS[0], sizeof(mmUVD_POWER_STATUS)/sizeof(mmUVD_POWER_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_ADDR_LOW", REG_MMIO, 0x3bc0, &mmUVD_SEMA_ADDR_LOW[0], sizeof(mmUVD_SEMA_ADDR_LOW)/sizeof(mmUVD_SEMA_ADDR_LOW[0]), 0, 0 },
+	{ "mmUVD_SEMA_ADDR_HIGH", REG_MMIO, 0x3bc1, &mmUVD_SEMA_ADDR_HIGH[0], sizeof(mmUVD_SEMA_ADDR_HIGH)/sizeof(mmUVD_SEMA_ADDR_HIGH[0]), 0, 0 },
+	{ "mmUVD_SEMA_CMD", REG_MMIO, 0x3bc2, &mmUVD_SEMA_CMD[0], sizeof(mmUVD_SEMA_CMD)/sizeof(mmUVD_SEMA_CMD[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_CMD", REG_MMIO, 0x3bc3, &mmUVD_GPCOM_VCPU_CMD[0], sizeof(mmUVD_GPCOM_VCPU_CMD)/sizeof(mmUVD_GPCOM_VCPU_CMD[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_DATA0", REG_MMIO, 0x3bc4, &mmUVD_GPCOM_VCPU_DATA0[0], sizeof(mmUVD_GPCOM_VCPU_DATA0)/sizeof(mmUVD_GPCOM_VCPU_DATA0[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_DATA1", REG_MMIO, 0x3bc5, &mmUVD_GPCOM_VCPU_DATA1[0], sizeof(mmUVD_GPCOM_VCPU_DATA1)/sizeof(mmUVD_GPCOM_VCPU_DATA1[0]), 0, 0 },
+	{ "mmUVD_ENGINE_CNTL", REG_MMIO, 0x3bc6, &mmUVD_ENGINE_CNTL[0], sizeof(mmUVD_ENGINE_CNTL)/sizeof(mmUVD_ENGINE_CNTL[0]), 0, 0 },
+	{ "mmUVD_UDEC_ADDR_CONFIG", REG_MMIO, 0x3bd3, &mmUVD_UDEC_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_ADDR_CONFIG)/sizeof(mmUVD_UDEC_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_UDEC_DB_ADDR_CONFIG", REG_MMIO, 0x3bd4, &mmUVD_UDEC_DB_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DB_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_UDEC_DBW_ADDR_CONFIG", REG_MMIO, 0x3bd5, &mmUVD_UDEC_DBW_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_NO_OP", REG_MMIO, 0x3bff, NULL, 0, 0, 0 },
+	{ "mmUVD_SEMA_CNTL", REG_MMIO, 0x3d00, &mmUVD_SEMA_CNTL[0], sizeof(mmUVD_SEMA_CNTL)/sizeof(mmUVD_SEMA_CNTL[0]), 0, 0 },
+	{ "mmUVD_LMI_EXT40_ADDR", REG_MMIO, 0x3d26, &mmUVD_LMI_EXT40_ADDR[0], sizeof(mmUVD_LMI_EXT40_ADDR)/sizeof(mmUVD_LMI_EXT40_ADDR[0]), 0, 0 },
+	{ "mmUVD_CTX_INDEX", REG_MMIO, 0x3d28, &mmUVD_CTX_INDEX[0], sizeof(mmUVD_CTX_INDEX)/sizeof(mmUVD_CTX_INDEX[0]), 0, 0 },
+	{ "mmUVD_CTX_DATA", REG_MMIO, 0x3d29, &mmUVD_CTX_DATA[0], sizeof(mmUVD_CTX_DATA)/sizeof(mmUVD_CTX_DATA[0]), 0, 0 },
+	{ "mmUVD_CGC_GATE", REG_MMIO, 0x3d2a, &mmUVD_CGC_GATE[0], sizeof(mmUVD_CGC_GATE)/sizeof(mmUVD_CGC_GATE[0]), 0, 0 },
+	{ "mmUVD_CGC_STATUS", REG_MMIO, 0x3d2b, &mmUVD_CGC_STATUS[0], sizeof(mmUVD_CGC_STATUS)/sizeof(mmUVD_CGC_STATUS[0]), 0, 0 },
+	{ "mmUVD_CGC_CTRL", REG_MMIO, 0x3d2c, &mmUVD_CGC_CTRL[0], sizeof(mmUVD_CGC_CTRL)/sizeof(mmUVD_CGC_CTRL[0]), 0, 0 },
+	{ "mmUVD_CGC_UDEC_STATUS", REG_MMIO, 0x3d2d, &mmUVD_CGC_UDEC_STATUS[0], sizeof(mmUVD_CGC_UDEC_STATUS)/sizeof(mmUVD_CGC_UDEC_STATUS[0]), 0, 0 },
+	{ "mmUVD_LMI_CTRL2", REG_MMIO, 0x3d3d, &mmUVD_LMI_CTRL2[0], sizeof(mmUVD_LMI_CTRL2)/sizeof(mmUVD_LMI_CTRL2[0]), 0, 0 },
+	{ "mmUVD_MASTINT_EN", REG_MMIO, 0x3d40, &mmUVD_MASTINT_EN[0], sizeof(mmUVD_MASTINT_EN)/sizeof(mmUVD_MASTINT_EN[0]), 0, 0 },
+	{ "mmUVD_LMI_ADDR_EXT", REG_MMIO, 0x3d65, &mmUVD_LMI_ADDR_EXT[0], sizeof(mmUVD_LMI_ADDR_EXT)/sizeof(mmUVD_LMI_ADDR_EXT[0]), 0, 0 },
+	{ "mmUVD_LMI_CTRL", REG_MMIO, 0x3d66, &mmUVD_LMI_CTRL[0], sizeof(mmUVD_LMI_CTRL)/sizeof(mmUVD_LMI_CTRL[0]), 0, 0 },
+	{ "mmUVD_LMI_STATUS", REG_MMIO, 0x3d67, &mmUVD_LMI_STATUS[0], sizeof(mmUVD_LMI_STATUS)/sizeof(mmUVD_LMI_STATUS[0]), 0, 0 },
+	{ "mmUVD_LMI_SWAP_CNTL", REG_MMIO, 0x3d6d, &mmUVD_LMI_SWAP_CNTL[0], sizeof(mmUVD_LMI_SWAP_CNTL)/sizeof(mmUVD_LMI_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUVD_MP_SWAP_CNTL", REG_MMIO, 0x3d6f, &mmUVD_MP_SWAP_CNTL[0], sizeof(mmUVD_MP_SWAP_CNTL)/sizeof(mmUVD_MP_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUVD_MPC_CNTL", REG_MMIO, 0x3d77, &mmUVD_MPC_CNTL[0], sizeof(mmUVD_MPC_CNTL)/sizeof(mmUVD_MPC_CNTL[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXA0", REG_MMIO, 0x3d79, &mmUVD_MPC_SET_MUXA0[0], sizeof(mmUVD_MPC_SET_MUXA0)/sizeof(mmUVD_MPC_SET_MUXA0[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXA1", REG_MMIO, 0x3d7a, &mmUVD_MPC_SET_MUXA1[0], sizeof(mmUVD_MPC_SET_MUXA1)/sizeof(mmUVD_MPC_SET_MUXA1[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXB0", REG_MMIO, 0x3d7b, &mmUVD_MPC_SET_MUXB0[0], sizeof(mmUVD_MPC_SET_MUXB0)/sizeof(mmUVD_MPC_SET_MUXB0[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXB1", REG_MMIO, 0x3d7c, &mmUVD_MPC_SET_MUXB1[0], sizeof(mmUVD_MPC_SET_MUXB1)/sizeof(mmUVD_MPC_SET_MUXB1[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUX", REG_MMIO, 0x3d7d, &mmUVD_MPC_SET_MUX[0], sizeof(mmUVD_MPC_SET_MUX)/sizeof(mmUVD_MPC_SET_MUX[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_ALU", REG_MMIO, 0x3d7e, &mmUVD_MPC_SET_ALU[0], sizeof(mmUVD_MPC_SET_ALU)/sizeof(mmUVD_MPC_SET_ALU[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET0", REG_MMIO, 0x3d82, &mmUVD_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_VCPU_CACHE_OFFSET0[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE0", REG_MMIO, 0x3d83, &mmUVD_VCPU_CACHE_SIZE0[0], sizeof(mmUVD_VCPU_CACHE_SIZE0)/sizeof(mmUVD_VCPU_CACHE_SIZE0[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET1", REG_MMIO, 0x3d84, &mmUVD_VCPU_CACHE_OFFSET1[0], sizeof(mmUVD_VCPU_CACHE_OFFSET1)/sizeof(mmUVD_VCPU_CACHE_OFFSET1[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE1", REG_MMIO, 0x3d85, &mmUVD_VCPU_CACHE_SIZE1[0], sizeof(mmUVD_VCPU_CACHE_SIZE1)/sizeof(mmUVD_VCPU_CACHE_SIZE1[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET2", REG_MMIO, 0x3d86, &mmUVD_VCPU_CACHE_OFFSET2[0], sizeof(mmUVD_VCPU_CACHE_OFFSET2)/sizeof(mmUVD_VCPU_CACHE_OFFSET2[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE2", REG_MMIO, 0x3d87, &mmUVD_VCPU_CACHE_SIZE2[0], sizeof(mmUVD_VCPU_CACHE_SIZE2)/sizeof(mmUVD_VCPU_CACHE_SIZE2[0]), 0, 0 },
+	{ "mmUVD_VCPU_CNTL", REG_MMIO, 0x3d98, &mmUVD_VCPU_CNTL[0], sizeof(mmUVD_VCPU_CNTL)/sizeof(mmUVD_VCPU_CNTL[0]), 0, 0 },
+	{ "mmUVD_SOFT_RESET", REG_MMIO, 0x3da0, &mmUVD_SOFT_RESET[0], sizeof(mmUVD_SOFT_RESET)/sizeof(mmUVD_SOFT_RESET[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_BASE", REG_MMIO, 0x3da1, &mmUVD_RBC_IB_BASE[0], sizeof(mmUVD_RBC_IB_BASE)/sizeof(mmUVD_RBC_IB_BASE[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_SIZE", REG_MMIO, 0x3da2, &mmUVD_RBC_IB_SIZE[0], sizeof(mmUVD_RBC_IB_SIZE)/sizeof(mmUVD_RBC_IB_SIZE[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_BASE", REG_MMIO, 0x3da3, &mmUVD_RBC_RB_BASE[0], sizeof(mmUVD_RBC_RB_BASE)/sizeof(mmUVD_RBC_RB_BASE[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_RPTR", REG_MMIO, 0x3da4, &mmUVD_RBC_RB_RPTR[0], sizeof(mmUVD_RBC_RB_RPTR)/sizeof(mmUVD_RBC_RB_RPTR[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_WPTR", REG_MMIO, 0x3da5, &mmUVD_RBC_RB_WPTR[0], sizeof(mmUVD_RBC_RB_WPTR)/sizeof(mmUVD_RBC_RB_WPTR[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_WPTR_CNTL", REG_MMIO, 0x3da6, NULL, 0, 0, 0 },
+	{ "mmUVD_RBC_RB_CNTL", REG_MMIO, 0x3da9, &mmUVD_RBC_RB_CNTL[0], sizeof(mmUVD_RBC_RB_CNTL)/sizeof(mmUVD_RBC_RB_CNTL[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_RPTR_ADDR", REG_MMIO, 0x3daa, &mmUVD_RBC_RB_RPTR_ADDR[0], sizeof(mmUVD_RBC_RB_RPTR_ADDR)/sizeof(mmUVD_RBC_RB_RPTR_ADDR[0]), 0, 0 },
+	{ "mmUVD_STATUS", REG_MMIO, 0x3daf, &mmUVD_STATUS[0], sizeof(mmUVD_STATUS)/sizeof(mmUVD_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_TIMEOUT_STATUS", REG_MMIO, 0x3db0, &mmUVD_SEMA_TIMEOUT_STATUS[0], sizeof(mmUVD_SEMA_TIMEOUT_STATUS)/sizeof(mmUVD_SEMA_TIMEOUT_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3db1, &mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL", REG_MMIO, 0x3db2, &mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3db3, &mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_CONTEXT_ID", REG_MMIO, 0x3dbd, &mmUVD_CONTEXT_ID[0], sizeof(mmUVD_CONTEXT_ID)/sizeof(mmUVD_CONTEXT_ID[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_SIZE_UPDATE", REG_MMIO, 0x3df1, NULL, 0, 0, 0 },
+	{ "ixUVD_MIF_CURR_ADDR_CONFIG", REG_SMC, 0x48, &ixUVD_MIF_CURR_ADDR_CONFIG[0], sizeof(ixUVD_MIF_CURR_ADDR_CONFIG)/sizeof(ixUVD_MIF_CURR_ADDR_CONFIG[0]), 0, 0 },
+	{ "ixUVD_MIF_REF_ADDR_CONFIG", REG_SMC, 0x4c, &ixUVD_MIF_REF_ADDR_CONFIG[0], sizeof(ixUVD_MIF_REF_ADDR_CONFIG)/sizeof(ixUVD_MIF_REF_ADDR_CONFIG[0]), 0, 0 },
+	{ "ixUVD_LMI_CACHE_CTRL", REG_SMC, 0x9b, &ixUVD_LMI_CACHE_CTRL[0], sizeof(ixUVD_LMI_CACHE_CTRL)/sizeof(ixUVD_LMI_CACHE_CTRL[0]), 0, 0 },
+	{ "ixUVD_LMI_SWAP_CNTL2", REG_SMC, 0xaa, &ixUVD_LMI_SWAP_CNTL2[0], sizeof(ixUVD_LMI_SWAP_CNTL2)/sizeof(ixUVD_LMI_SWAP_CNTL2[0]), 0, 0 },
+	{ "ixUVD_LMI_ADDR_EXT2", REG_SMC, 0xab, &ixUVD_LMI_ADDR_EXT2[0], sizeof(ixUVD_LMI_ADDR_EXT2)/sizeof(ixUVD_LMI_ADDR_EXT2[0]), 0, 0 },
+	{ "ixUVD_CGC_MEM_CTRL", REG_SMC, 0xc0, &ixUVD_CGC_MEM_CTRL[0], sizeof(ixUVD_CGC_MEM_CTRL)/sizeof(ixUVD_CGC_MEM_CTRL[0]), 0, 0 },
+	{ "ixUVD_CGC_CTRL2", REG_SMC, 0xc1, &ixUVD_CGC_CTRL2[0], sizeof(ixUVD_CGC_CTRL2)/sizeof(ixUVD_CGC_CTRL2[0]), 0, 0 },
diff --git a/src/lib/ip/uvd5.c b/src/lib/ip/uvd5.c
new file mode 100644
index 0000000..805605f
--- /dev/null
+++ b/src/lib/ip/uvd5.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "uvd50_bits.i"
+
+static const struct umr_reg uvd5_registers[] = {
+#include "uvd50_regs.i"
+};
+
+struct umr_ip_block *umr_create_uvd5(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "uvd5";
+	ip->no_regs = sizeof(uvd5_registers)/sizeof(uvd5_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(uvd5_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, uvd5_registers, sizeof(uvd5_registers));
+	return ip;
+}
diff --git a/src/lib/ip/uvd50_bits.i b/src/lib/ip/uvd50_bits.i
new file mode 100644
index 0000000..21c638d
--- /dev/null
+++ b/src/lib/ip/uvd50_bits.i
@@ -0,0 +1,677 @@
+static struct umr_bitfield ixUVD_LMI_VMID_INTERNAL3[] = {
+	 { "MIF_GEN_RD0_VMID", 0, 3, &umr_bitfield_default },
+	 { "MIF_GEN_RD1_VMID", 4, 7, &umr_bitfield_default },
+	 { "MIF_GEN_WR0_VMID", 8, 11, &umr_bitfield_default },
+	 { "MIF_GEN_WR1_VMID", 12, 15, &umr_bitfield_default },
+	 { "MIF_SCLR_VMID", 16, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_CONFIG[] = {
+	 { "UVD_PGFSM_FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "UVD_PGFSM_POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "UVD_PGFSM_POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "UVD_PGFSM_P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "UVD_PGFSM_P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "UVD_PGFSM_WRITE", 12, 12, &umr_bitfield_default },
+	 { "UVD_PGFSM_READ", 13, 13, &umr_bitfield_default },
+	 { "UVD_PGFSM_REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE1[] = {
+	 { "UVD_PGFSM_READ_TILE1_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE2[] = {
+	 { "UVD_PGFSM_READ_TILE2_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_POWER_STATUS[] = {
+	 { "UVD_POWER_STATUS", 0, 1, &umr_bitfield_default },
+	 { "UVD_PG_MODE", 2, 2, &umr_bitfield_default },
+	 { "UVD_STATUS_CHECK_TIMEOUT", 3, 3, &umr_bitfield_default },
+	 { "PWR_ON_CHECK_TIMEOUT", 4, 4, &umr_bitfield_default },
+	 { "PWR_OFF_CHECK_TIMEOUT", 5, 5, &umr_bitfield_default },
+	 { "UVD_PGFSM_TIMEOUT_MODE", 6, 7, &umr_bitfield_default },
+	 { "UVD_PG_EN", 8, 8, &umr_bitfield_default },
+	 { "PAUSE_DPG_REQ", 9, 9, &umr_bitfield_default },
+	 { "PAUSE_DPG_ACK", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE3[] = {
+	 { "UVD_PGFSM_READ_TILE3_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE4[] = {
+	 { "UVD_PGFSM_READ_TILE4_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE5[] = {
+	 { "UVD_PGFSM_READ_TILE5_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE6[] = {
+	 { "UVD_PGFSM_READ_TILE6_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE7[] = {
+	 { "UVD_PGFSM_READ_TILE7_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MIF_CURR_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MIF_REF_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MIF_RECON1_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_JPEG_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_ADDR_LOW[] = {
+	 { "ADDR_22_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_ADDR_HIGH[] = {
+	 { "ADDR_42_23", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_CMD[] = {
+	 { "REQ_CMD", 0, 3, &umr_bitfield_default },
+	 { "WR_PHASE", 4, 5, &umr_bitfield_default },
+	 { "MODE", 6, 6, &umr_bitfield_default },
+	 { "VMID_EN", 7, 7, &umr_bitfield_default },
+	 { "VMID", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_CMD[] = {
+	 { "CMD_SEND", 0, 0, &umr_bitfield_default },
+	 { "CMD", 1, 30, &umr_bitfield_default },
+	 { "CMD_SOURCE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_ENGINE_CNTL[] = {
+	 { "ENGINE_START", 0, 0, &umr_bitfield_default },
+	 { "ENGINE_START_MODE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_DB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_DBW_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SUVD_CGC_GATE[] = {
+	 { "SRE", 0, 0, &umr_bitfield_default },
+	 { "SIT", 1, 1, &umr_bitfield_default },
+	 { "SMP", 2, 2, &umr_bitfield_default },
+	 { "SCM", 3, 3, &umr_bitfield_default },
+	 { "SDB", 4, 4, &umr_bitfield_default },
+	 { "SRE_H264", 5, 5, &umr_bitfield_default },
+	 { "SRE_HEVC", 6, 6, &umr_bitfield_default },
+	 { "SIT_H264", 7, 7, &umr_bitfield_default },
+	 { "SIT_HEVC", 8, 8, &umr_bitfield_default },
+	 { "SCM_H264", 9, 9, &umr_bitfield_default },
+	 { "SCM_HEVC", 10, 10, &umr_bitfield_default },
+	 { "SDB_H264", 11, 11, &umr_bitfield_default },
+	 { "SDB_HEVC", 12, 12, &umr_bitfield_default },
+	 { "SCLR", 13, 13, &umr_bitfield_default },
+	 { "UVD_SC", 14, 14, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SUVD_CGC_STATUS[] = {
+	 { "SRE_VCLK", 0, 0, &umr_bitfield_default },
+	 { "SRE_DCLK", 1, 1, &umr_bitfield_default },
+	 { "SIT_DCLK", 2, 2, &umr_bitfield_default },
+	 { "SMP_DCLK", 3, 3, &umr_bitfield_default },
+	 { "SCM_DCLK", 4, 4, &umr_bitfield_default },
+	 { "SDB_DCLK", 5, 5, &umr_bitfield_default },
+	 { "SRE_H264_VCLK", 6, 6, &umr_bitfield_default },
+	 { "SRE_HEVC_VCLK", 7, 7, &umr_bitfield_default },
+	 { "SIT_H264_DCLK", 8, 8, &umr_bitfield_default },
+	 { "SIT_HEVC_DCLK", 9, 9, &umr_bitfield_default },
+	 { "SCM_H264_DCLK", 10, 10, &umr_bitfield_default },
+	 { "SCM_HEVC_DCLK", 11, 11, &umr_bitfield_default },
+	 { "SDB_H264_DCLK", 12, 12, &umr_bitfield_default },
+	 { "SDB_HEVC_DCLK", 13, 13, &umr_bitfield_default },
+	 { "SCLR_DCLK", 14, 14, &umr_bitfield_default },
+	 { "UVD_SC", 15, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SUVD_CGC_CTRL[] = {
+	 { "SRE_MODE", 0, 0, &umr_bitfield_default },
+	 { "SIT_MODE", 1, 1, &umr_bitfield_default },
+	 { "SMP_MODE", 2, 2, &umr_bitfield_default },
+	 { "SCM_MODE", 3, 3, &umr_bitfield_default },
+	 { "SDB_MODE", 4, 4, &umr_bitfield_default },
+	 { "SCLR_MODE", 5, 5, &umr_bitfield_default },
+	 { "UVD_SC_MODE", 6, 6, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[] = {
+	 { "BITS_63_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[] = {
+	 { "BITS_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[] = {
+	 { "BITS_63_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[] = {
+	 { "BITS_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[] = {
+	 { "BITS_63_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[] = {
+	 { "BITS_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_CNTL[] = {
+	 { "SEMAPHORE_EN", 0, 0, &umr_bitfield_default },
+	 { "ADVANCED_MODE_DIS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_EXT40_ADDR[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+	 { "INDEX", 16, 20, &umr_bitfield_default },
+	 { "WRITE_ADDR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CTX_INDEX[] = {
+	 { "INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CTX_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_GATE[] = {
+	 { "SYS", 0, 0, &umr_bitfield_default },
+	 { "UDEC", 1, 1, &umr_bitfield_default },
+	 { "MPEG2", 2, 2, &umr_bitfield_default },
+	 { "REGS", 3, 3, &umr_bitfield_default },
+	 { "RBC", 4, 4, &umr_bitfield_default },
+	 { "LMI_MC", 5, 5, &umr_bitfield_default },
+	 { "LMI_UMC", 6, 6, &umr_bitfield_default },
+	 { "IDCT", 7, 7, &umr_bitfield_default },
+	 { "MPRD", 8, 8, &umr_bitfield_default },
+	 { "MPC", 9, 9, &umr_bitfield_default },
+	 { "LBSI", 10, 10, &umr_bitfield_default },
+	 { "LRBBM", 11, 11, &umr_bitfield_default },
+	 { "UDEC_RE", 12, 12, &umr_bitfield_default },
+	 { "UDEC_CM", 13, 13, &umr_bitfield_default },
+	 { "UDEC_IT", 14, 14, &umr_bitfield_default },
+	 { "UDEC_DB", 15, 15, &umr_bitfield_default },
+	 { "UDEC_MP", 16, 16, &umr_bitfield_default },
+	 { "WCB", 17, 17, &umr_bitfield_default },
+	 { "VCPU", 18, 18, &umr_bitfield_default },
+	 { "SCPU", 19, 19, &umr_bitfield_default },
+	 { "JPEG", 20, 20, &umr_bitfield_default },
+	 { "JPEG2", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_STATUS[] = {
+	 { "SYS_SCLK", 0, 0, &umr_bitfield_default },
+	 { "SYS_DCLK", 1, 1, &umr_bitfield_default },
+	 { "SYS_VCLK", 2, 2, &umr_bitfield_default },
+	 { "UDEC_SCLK", 3, 3, &umr_bitfield_default },
+	 { "UDEC_DCLK", 4, 4, &umr_bitfield_default },
+	 { "UDEC_VCLK", 5, 5, &umr_bitfield_default },
+	 { "MPEG2_SCLK", 6, 6, &umr_bitfield_default },
+	 { "MPEG2_DCLK", 7, 7, &umr_bitfield_default },
+	 { "MPEG2_VCLK", 8, 8, &umr_bitfield_default },
+	 { "REGS_SCLK", 9, 9, &umr_bitfield_default },
+	 { "REGS_VCLK", 10, 10, &umr_bitfield_default },
+	 { "RBC_SCLK", 11, 11, &umr_bitfield_default },
+	 { "LMI_MC_SCLK", 12, 12, &umr_bitfield_default },
+	 { "LMI_UMC_SCLK", 13, 13, &umr_bitfield_default },
+	 { "IDCT_SCLK", 14, 14, &umr_bitfield_default },
+	 { "IDCT_VCLK", 15, 15, &umr_bitfield_default },
+	 { "MPRD_SCLK", 16, 16, &umr_bitfield_default },
+	 { "MPRD_DCLK", 17, 17, &umr_bitfield_default },
+	 { "MPRD_VCLK", 18, 18, &umr_bitfield_default },
+	 { "MPC_SCLK", 19, 19, &umr_bitfield_default },
+	 { "MPC_DCLK", 20, 20, &umr_bitfield_default },
+	 { "LBSI_SCLK", 21, 21, &umr_bitfield_default },
+	 { "LBSI_VCLK", 22, 22, &umr_bitfield_default },
+	 { "LRBBM_SCLK", 23, 23, &umr_bitfield_default },
+	 { "WCB_SCLK", 24, 24, &umr_bitfield_default },
+	 { "VCPU_SCLK", 25, 25, &umr_bitfield_default },
+	 { "VCPU_VCLK", 26, 26, &umr_bitfield_default },
+	 { "SCPU_SCLK", 27, 27, &umr_bitfield_default },
+	 { "SCPU_VCLK", 28, 28, &umr_bitfield_default },
+	 { "JPEG_ACTIVE", 30, 30, &umr_bitfield_default },
+	 { "ALL_DEC_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_CTRL[] = {
+	 { "DYN_CLOCK_MODE", 0, 0, &umr_bitfield_default },
+	 { "JPEG2_MODE", 1, 1, &umr_bitfield_default },
+	 { "CLK_GATE_DLY_TIMER", 2, 5, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 6, 10, &umr_bitfield_default },
+	 { "UDEC_RE_MODE", 11, 11, &umr_bitfield_default },
+	 { "UDEC_CM_MODE", 12, 12, &umr_bitfield_default },
+	 { "UDEC_IT_MODE", 13, 13, &umr_bitfield_default },
+	 { "UDEC_DB_MODE", 14, 14, &umr_bitfield_default },
+	 { "UDEC_MP_MODE", 15, 15, &umr_bitfield_default },
+	 { "SYS_MODE", 16, 16, &umr_bitfield_default },
+	 { "UDEC_MODE", 17, 17, &umr_bitfield_default },
+	 { "MPEG2_MODE", 18, 18, &umr_bitfield_default },
+	 { "REGS_MODE", 19, 19, &umr_bitfield_default },
+	 { "RBC_MODE", 20, 20, &umr_bitfield_default },
+	 { "LMI_MC_MODE", 21, 21, &umr_bitfield_default },
+	 { "LMI_UMC_MODE", 22, 22, &umr_bitfield_default },
+	 { "IDCT_MODE", 23, 23, &umr_bitfield_default },
+	 { "MPRD_MODE", 24, 24, &umr_bitfield_default },
+	 { "MPC_MODE", 25, 25, &umr_bitfield_default },
+	 { "LBSI_MODE", 26, 26, &umr_bitfield_default },
+	 { "LRBBM_MODE", 27, 27, &umr_bitfield_default },
+	 { "WCB_MODE", 28, 28, &umr_bitfield_default },
+	 { "VCPU_MODE", 29, 29, &umr_bitfield_default },
+	 { "SCPU_MODE", 30, 30, &umr_bitfield_default },
+	 { "JPEG_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_UDEC_STATUS[] = {
+	 { "RE_SCLK", 0, 0, &umr_bitfield_default },
+	 { "RE_DCLK", 1, 1, &umr_bitfield_default },
+	 { "RE_VCLK", 2, 2, &umr_bitfield_default },
+	 { "CM_SCLK", 3, 3, &umr_bitfield_default },
+	 { "CM_DCLK", 4, 4, &umr_bitfield_default },
+	 { "CM_VCLK", 5, 5, &umr_bitfield_default },
+	 { "IT_SCLK", 6, 6, &umr_bitfield_default },
+	 { "IT_DCLK", 7, 7, &umr_bitfield_default },
+	 { "IT_VCLK", 8, 8, &umr_bitfield_default },
+	 { "DB_SCLK", 9, 9, &umr_bitfield_default },
+	 { "DB_DCLK", 10, 10, &umr_bitfield_default },
+	 { "DB_VCLK", 11, 11, &umr_bitfield_default },
+	 { "MP_SCLK", 12, 12, &umr_bitfield_default },
+	 { "MP_DCLK", 13, 13, &umr_bitfield_default },
+	 { "MP_VCLK", 14, 14, &umr_bitfield_default },
+	 { "JPEG_VCLK", 15, 15, &umr_bitfield_default },
+	 { "JPEG_SCLK", 16, 16, &umr_bitfield_default },
+	 { "JPEG2_VCLK", 17, 17, &umr_bitfield_default },
+	 { "JPEG2_SCLK", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_CTRL2[] = {
+	 { "SPH_DIS", 0, 0, &umr_bitfield_default },
+	 { "STALL_ARB", 1, 1, &umr_bitfield_default },
+	 { "ASSERT_UMC_URGENT", 2, 2, &umr_bitfield_default },
+	 { "MASK_UMC_URGENT", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WR_WATERMARK", 4, 6, &umr_bitfield_default },
+	 { "DRCITF_BUBBLE_FIX_DIS", 7, 7, &umr_bitfield_default },
+	 { "STALL_ARB_UMC", 8, 8, &umr_bitfield_default },
+	 { "MC_READ_ID_SEL", 9, 10, &umr_bitfield_default },
+	 { "MC_WRITE_ID_SEL", 11, 12, &umr_bitfield_default },
+	 { "VCPU_NC0_EXT_EN", 13, 13, &umr_bitfield_default },
+	 { "VCPU_NC1_EXT_EN", 14, 14, &umr_bitfield_default },
+	 { "SPU_EXTRA_CID_EN", 15, 15, &umr_bitfield_default },
+	 { "RE_OFFLOAD_EN", 16, 16, &umr_bitfield_default },
+	 { "RE_OFLD_MIF_WR_REQ_NUM", 17, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MASTINT_EN[] = {
+	 { "OVERRUN_RST", 0, 0, &umr_bitfield_default },
+	 { "VCPU_EN", 1, 1, &umr_bitfield_default },
+	 { "SYS_EN", 2, 2, &umr_bitfield_default },
+	 { "INT_OVERRUN", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_ADDR_EXT[] = {
+	 { "VCPU_ADDR_EXT", 0, 3, &umr_bitfield_default },
+	 { "CM_ADDR_EXT", 4, 7, &umr_bitfield_default },
+	 { "IT_ADDR_EXT", 8, 11, &umr_bitfield_default },
+	 { "VCPU_VM_ADDR_EXT", 12, 15, &umr_bitfield_default },
+	 { "RE_ADDR_EXT", 16, 19, &umr_bitfield_default },
+	 { "MP_ADDR_EXT", 20, 23, &umr_bitfield_default },
+	 { "VCPU_NC0_ADDR_EXT", 24, 27, &umr_bitfield_default },
+	 { "VCPU_NC1_ADDR_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_CTRL[] = {
+	 { "WRITE_CLEAN_TIMER", 0, 7, &umr_bitfield_default },
+	 { "WRITE_CLEAN_TIMER_EN", 8, 8, &umr_bitfield_default },
+	 { "REQ_MODE", 9, 9, &umr_bitfield_default },
+	 { "ASSERT_MC_URGENT", 11, 11, &umr_bitfield_default },
+	 { "MASK_MC_URGENT", 12, 12, &umr_bitfield_default },
+	 { "DATA_COHERENCY_EN", 13, 13, &umr_bitfield_default },
+	 { "CRC_RESET", 14, 14, &umr_bitfield_default },
+	 { "CRC_SEL", 15, 19, &umr_bitfield_default },
+	 { "DISABLE_ON_FWV_FAIL", 20, 20, &umr_bitfield_default },
+	 { "VCPU_DATA_COHERENCY_EN", 21, 21, &umr_bitfield_default },
+	 { "CM_DATA_COHERENCY_EN", 22, 22, &umr_bitfield_default },
+	 { "DB_DB_DATA_COHERENCY_EN", 23, 23, &umr_bitfield_default },
+	 { "DB_IT_DATA_COHERENCY_EN", 24, 24, &umr_bitfield_default },
+	 { "IT_IT_DATA_COHERENCY_EN", 25, 25, &umr_bitfield_default },
+	 { "MIF_MIF_DATA_COHERENCY_EN", 26, 26, &umr_bitfield_default },
+	 { "RFU", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_STATUS[] = {
+	 { "READ_CLEAN", 0, 0, &umr_bitfield_default },
+	 { "WRITE_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "WRITE_CLEAN_RAW", 2, 2, &umr_bitfield_default },
+	 { "VCPU_LMI_WRITE_CLEAN", 3, 3, &umr_bitfield_default },
+	 { "UMC_READ_CLEAN", 4, 4, &umr_bitfield_default },
+	 { "UMC_WRITE_CLEAN", 5, 5, &umr_bitfield_default },
+	 { "UMC_WRITE_CLEAN_RAW", 6, 6, &umr_bitfield_default },
+	 { "PENDING_UVD_MC_WRITE", 7, 7, &umr_bitfield_default },
+	 { "READ_CLEAN_RAW", 8, 8, &umr_bitfield_default },
+	 { "UMC_READ_CLEAN_RAW", 9, 9, &umr_bitfield_default },
+	 { "UMC_UVD_IDLE", 10, 10, &umr_bitfield_default },
+	 { "UMC_AVP_IDLE", 11, 11, &umr_bitfield_default },
+	 { "ADP_MC_READ_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "ADP_UMC_READ_CLEAN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_SWAP_CNTL[] = {
+	 { "RB_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "IB_MC_SWAP", 2, 3, &umr_bitfield_default },
+	 { "RB_RPTR_MC_SWAP", 4, 5, &umr_bitfield_default },
+	 { "VCPU_R_MC_SWAP", 6, 7, &umr_bitfield_default },
+	 { "VCPU_W_MC_SWAP", 8, 9, &umr_bitfield_default },
+	 { "CM_MC_SWAP", 10, 11, &umr_bitfield_default },
+	 { "IT_MC_SWAP", 12, 13, &umr_bitfield_default },
+	 { "DB_R_MC_SWAP", 14, 15, &umr_bitfield_default },
+	 { "DB_W_MC_SWAP", 16, 17, &umr_bitfield_default },
+	 { "CSM_MC_SWAP", 18, 19, &umr_bitfield_default },
+	 { "MP_REF16_MC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DBW_MC_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RB_WR_MC_SWAP", 26, 27, &umr_bitfield_default },
+	 { "RE_MC_SWAP", 28, 29, &umr_bitfield_default },
+	 { "MP_MC_SWAP", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MP_SWAP_CNTL[] = {
+	 { "MP_REF0_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "MP_REF1_MC_SWAP", 2, 3, &umr_bitfield_default },
+	 { "MP_REF2_MC_SWAP", 4, 5, &umr_bitfield_default },
+	 { "MP_REF3_MC_SWAP", 6, 7, &umr_bitfield_default },
+	 { "MP_REF4_MC_SWAP", 8, 9, &umr_bitfield_default },
+	 { "MP_REF5_MC_SWAP", 10, 11, &umr_bitfield_default },
+	 { "MP_REF6_MC_SWAP", 12, 13, &umr_bitfield_default },
+	 { "MP_REF7_MC_SWAP", 14, 15, &umr_bitfield_default },
+	 { "MP_REF8_MC_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MP_REF9_MC_SWAP", 18, 19, &umr_bitfield_default },
+	 { "MP_REF10_MC_SWAP", 20, 21, &umr_bitfield_default },
+	 { "MP_REF11_MC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "MP_REF12_MC_SWAP", 24, 25, &umr_bitfield_default },
+	 { "MP_REF13_MC_SWAP", 26, 27, &umr_bitfield_default },
+	 { "MP_REF14_MC_SWAP", 28, 29, &umr_bitfield_default },
+	 { "MP_REF15_MC_SWAP", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_CNTL[] = {
+	 { "REPLACEMENT_MODE", 3, 5, &umr_bitfield_default },
+	 { "PERF_RST", 6, 6, &umr_bitfield_default },
+	 { "DBG_MUX", 8, 11, &umr_bitfield_default },
+	 { "AVE_WEIGHT", 16, 17, &umr_bitfield_default },
+	 { "URGENT_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXA0[] = {
+	 { "VARA_0", 0, 5, &umr_bitfield_default },
+	 { "VARA_1", 6, 11, &umr_bitfield_default },
+	 { "VARA_2", 12, 17, &umr_bitfield_default },
+	 { "VARA_3", 18, 23, &umr_bitfield_default },
+	 { "VARA_4", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXA1[] = {
+	 { "VARA_5", 0, 5, &umr_bitfield_default },
+	 { "VARA_6", 6, 11, &umr_bitfield_default },
+	 { "VARA_7", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXB0[] = {
+	 { "VARB_0", 0, 5, &umr_bitfield_default },
+	 { "VARB_1", 6, 11, &umr_bitfield_default },
+	 { "VARB_2", 12, 17, &umr_bitfield_default },
+	 { "VARB_3", 18, 23, &umr_bitfield_default },
+	 { "VARB_4", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXB1[] = {
+	 { "VARB_5", 0, 5, &umr_bitfield_default },
+	 { "VARB_6", 6, 11, &umr_bitfield_default },
+	 { "VARB_7", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUX[] = {
+	 { "SET_0", 0, 2, &umr_bitfield_default },
+	 { "SET_1", 3, 5, &umr_bitfield_default },
+	 { "SET_2", 6, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_ALU[] = {
+	 { "FUNCT", 0, 2, &umr_bitfield_default },
+	 { "OPERAND", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET0[] = {
+	 { "CACHE_OFFSET0", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE0[] = {
+	 { "CACHE_SIZE0", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET1[] = {
+	 { "CACHE_OFFSET1", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE1[] = {
+	 { "CACHE_SIZE1", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET2[] = {
+	 { "CACHE_OFFSET2", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE2[] = {
+	 { "CACHE_SIZE2", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CNTL[] = {
+	 { "IRQ_ERR", 0, 3, &umr_bitfield_default },
+	 { "AXI_MAX_BRST_SIZE_IS_4", 4, 4, &umr_bitfield_default },
+	 { "PMB_ED_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "PMB_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "RBBM_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "ABORT_REQ", 8, 8, &umr_bitfield_default },
+	 { "CLK_EN", 9, 9, &umr_bitfield_default },
+	 { "TRCE_EN", 10, 10, &umr_bitfield_default },
+	 { "TRCE_MUX", 11, 12, &umr_bitfield_default },
+	 { "DBG_MUX", 13, 15, &umr_bitfield_default },
+	 { "JTAG_EN", 16, 16, &umr_bitfield_default },
+	 { "MIF_WR_LOW_THRESHOLD_BP", 17, 17, &umr_bitfield_default },
+	 { "TIMEOUT_DIS", 18, 18, &umr_bitfield_default },
+	 { "SUVD_EN", 19, 19, &umr_bitfield_default },
+	 { "PRB_TIMEOUT_VAL", 20, 27, &umr_bitfield_default },
+	 { "CABAC_MB_ACC", 28, 28, &umr_bitfield_default },
+	 { "WMV9_EN", 30, 30, &umr_bitfield_default },
+	 { "RE_OFFLOAD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SOFT_RESET[] = {
+	 { "RBC_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "LBSI_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "LMI_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "VCPU_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "UDEC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "CSM_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "CXW_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "TAP_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "MPC_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "JPEG_SCLK_RESET_STATUS", 9, 9, &umr_bitfield_default },
+	 { "IH_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "MPRD_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "IDCT_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "LMI_UMC_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "SPH_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "MIF_SOFT_RESET", 15, 15, &umr_bitfield_default },
+	 { "LCM_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "SUVD_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "LBSI_VCLK_RESET_STATUS", 18, 18, &umr_bitfield_default },
+	 { "VCPU_VCLK_RESET_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UDEC_VCLK_RESET_STATUS", 20, 20, &umr_bitfield_default },
+	 { "UDEC_DCLK_RESET_STATUS", 21, 21, &umr_bitfield_default },
+	 { "MPC_DCLK_RESET_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MPRD_VCLK_RESET_STATUS", 23, 23, &umr_bitfield_default },
+	 { "MPRD_DCLK_RESET_STATUS", 24, 24, &umr_bitfield_default },
+	 { "IDCT_VCLK_RESET_STATUS", 25, 25, &umr_bitfield_default },
+	 { "MIF_DCLK_RESET_STATUS", 26, 26, &umr_bitfield_default },
+	 { "LCM_DCLK_RESET_STATUS", 27, 27, &umr_bitfield_default },
+	 { "SUVD_VCLK_RESET_STATUS", 28, 28, &umr_bitfield_default },
+	 { "SUVD_DCLK_RESET_STATUS", 29, 29, &umr_bitfield_default },
+	 { "RE_DCLK_RESET_STATUS", 30, 30, &umr_bitfield_default },
+	 { "SRE_DCLK_RESET_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_IB_VMID[] = {
+	 { "IB_VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_IB_SIZE[] = {
+	 { "IB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_RB_VMID[] = {
+	 { "RB_VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_RPTR[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_WPTR[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_CNTL[] = {
+	 { "RB_BUFSZ", 0, 4, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 12, &umr_bitfield_default },
+	 { "RB_NO_FETCH", 16, 16, &umr_bitfield_default },
+	 { "RB_WPTR_POLL_EN", 20, 20, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "RB_RPTR_WR_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_RPTR_ADDR[] = {
+	 { "RB_RPTR_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_STATUS[] = {
+	 { "RBC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VCPU_REPORT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_TIMEOUT_STATUS[] = {
+	 { "SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT", 0, 0, &umr_bitfield_default },
+	 { "SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT", 1, 1, &umr_bitfield_default },
+	 { "SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT", 2, 2, &umr_bitfield_default },
+	 { "SEMAPHORE_TIMEOUT_CLEAR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[] = {
+	 { "WAIT_INCOMPLETE_EN", 0, 0, &umr_bitfield_default },
+	 { "WAIT_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[] = {
+	 { "WAIT_FAULT_EN", 0, 0, &umr_bitfield_default },
+	 { "WAIT_FAULT_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[] = {
+	 { "SIGNAL_INCOMPLETE_EN", 0, 0, &umr_bitfield_default },
+	 { "SIGNAL_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CONTEXT_ID[] = {
+	 { "CONTEXT_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_MIF_SCLR_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_VMID_INTERNAL[] = {
+	 { "VCPU_NC0_VMID", 0, 3, &umr_bitfield_default },
+	 { "VCPU_NC1_VMID", 4, 7, &umr_bitfield_default },
+	 { "DPB_VMID", 8, 11, &umr_bitfield_default },
+	 { "DBW_VMID", 12, 15, &umr_bitfield_default },
+	 { "LBSI_VMID", 16, 19, &umr_bitfield_default },
+	 { "IDCT_VMID", 20, 23, &umr_bitfield_default },
+	 { "JPEG_VMID", 24, 27, &umr_bitfield_default },
+	 { "JPEG2_VMID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_VMID_INTERNAL2[] = {
+	 { "MIF_GPGPU_VMID", 0, 3, &umr_bitfield_default },
+	 { "MIF_CURR_VMID", 4, 7, &umr_bitfield_default },
+	 { "MIF_REF_VMID", 8, 11, &umr_bitfield_default },
+	 { "MIF_DBW_VMID", 12, 15, &umr_bitfield_default },
+	 { "MIF_CM_COLOC_VMID", 16, 19, &umr_bitfield_default },
+	 { "MIF_BSD_VMID", 20, 23, &umr_bitfield_default },
+	 { "MIF_BSP_VMID", 24, 27, &umr_bitfield_default },
+	 { "VDMA_VMID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_CACHE_CTRL[] = {
+	 { "IT_EN", 0, 0, &umr_bitfield_default },
+	 { "IT_FLUSH", 1, 1, &umr_bitfield_default },
+	 { "CM_EN", 2, 2, &umr_bitfield_default },
+	 { "CM_FLUSH", 3, 3, &umr_bitfield_default },
+	 { "VCPU_EN", 4, 4, &umr_bitfield_default },
+	 { "VCPU_FLUSH", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_SWAP_CNTL2[] = {
+	 { "SCPU_R_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SCPU_W_MC_SWAP", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_ADDR_EXT2[] = {
+	 { "SCPU_ADDR_EXT", 0, 3, &umr_bitfield_default },
+	 { "SCPU_VM_ADDR_EXT", 4, 7, &umr_bitfield_default },
+	 { "SCPU_NC0_ADDR_EXT", 8, 11, &umr_bitfield_default },
+	 { "SCPU_NC1_ADDR_EXT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_CGC_MEM_CTRL[] = {
+	 { "LMI_MC_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "MPC_LS_EN", 1, 1, &umr_bitfield_default },
+	 { "MPRD_LS_EN", 2, 2, &umr_bitfield_default },
+	 { "WCB_LS_EN", 3, 3, &umr_bitfield_default },
+	 { "UDEC_RE_LS_EN", 4, 4, &umr_bitfield_default },
+	 { "UDEC_CM_LS_EN", 5, 5, &umr_bitfield_default },
+	 { "UDEC_IT_LS_EN", 6, 6, &umr_bitfield_default },
+	 { "UDEC_DB_LS_EN", 7, 7, &umr_bitfield_default },
+	 { "UDEC_MP_LS_EN", 8, 8, &umr_bitfield_default },
+	 { "SYS_LS_EN", 9, 9, &umr_bitfield_default },
+	 { "VCPU_LS_EN", 10, 10, &umr_bitfield_default },
+	 { "SCPU_LS_EN", 11, 11, &umr_bitfield_default },
+	 { "MIF_LS_EN", 12, 12, &umr_bitfield_default },
+	 { "LCM_LS_EN", 13, 13, &umr_bitfield_default },
+	 { "JPEG_LS_EN", 14, 14, &umr_bitfield_default },
+	 { "JPEG2_LS_EN", 15, 15, &umr_bitfield_default },
+	 { "LS_SET_DELAY", 16, 19, &umr_bitfield_default },
+	 { "LS_CLEAR_DELAY", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_CGC_CTRL2[] = {
+	 { "DYN_OCLK_RAMP_EN", 0, 0, &umr_bitfield_default },
+	 { "DYN_RCLK_RAMP_EN", 1, 1, &umr_bitfield_default },
+	 { "GATER_DIV_ID", 2, 4, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/uvd50_regs.i b/src/lib/ip/uvd50_regs.i
new file mode 100644
index 0000000..4846280
--- /dev/null
+++ b/src/lib/ip/uvd50_regs.i
@@ -0,0 +1,87 @@
+	{ "ixUVD_LMI_VMID_INTERNAL3", REG_SMC, 0x162, &ixUVD_LMI_VMID_INTERNAL3[0], sizeof(ixUVD_LMI_VMID_INTERNAL3)/sizeof(ixUVD_LMI_VMID_INTERNAL3[0]), 0, 0 },
+	{ "mmUVD_PGFSM_CONFIG", REG_MMIO, 0x38c0, &mmUVD_PGFSM_CONFIG[0], sizeof(mmUVD_PGFSM_CONFIG)/sizeof(mmUVD_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE1", REG_MMIO, 0x38c2, &mmUVD_PGFSM_READ_TILE1[0], sizeof(mmUVD_PGFSM_READ_TILE1)/sizeof(mmUVD_PGFSM_READ_TILE1[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE2", REG_MMIO, 0x38c3, &mmUVD_PGFSM_READ_TILE2[0], sizeof(mmUVD_PGFSM_READ_TILE2)/sizeof(mmUVD_PGFSM_READ_TILE2[0]), 0, 0 },
+	{ "mmUVD_POWER_STATUS", REG_MMIO, 0x38c4, &mmUVD_POWER_STATUS[0], sizeof(mmUVD_POWER_STATUS)/sizeof(mmUVD_POWER_STATUS[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE3", REG_MMIO, 0x38c5, &mmUVD_PGFSM_READ_TILE3[0], sizeof(mmUVD_PGFSM_READ_TILE3)/sizeof(mmUVD_PGFSM_READ_TILE3[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE4", REG_MMIO, 0x38c6, &mmUVD_PGFSM_READ_TILE4[0], sizeof(mmUVD_PGFSM_READ_TILE4)/sizeof(mmUVD_PGFSM_READ_TILE4[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE5", REG_MMIO, 0x38c8, &mmUVD_PGFSM_READ_TILE5[0], sizeof(mmUVD_PGFSM_READ_TILE5)/sizeof(mmUVD_PGFSM_READ_TILE5[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE6", REG_MMIO, 0x38ee, &mmUVD_PGFSM_READ_TILE6[0], sizeof(mmUVD_PGFSM_READ_TILE6)/sizeof(mmUVD_PGFSM_READ_TILE6[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE7", REG_MMIO, 0x38ef, &mmUVD_PGFSM_READ_TILE7[0], sizeof(mmUVD_PGFSM_READ_TILE7)/sizeof(mmUVD_PGFSM_READ_TILE7[0]), 0, 0 },
+	{ "mmUVD_MIF_CURR_ADDR_CONFIG", REG_MMIO, 0x3992, &mmUVD_MIF_CURR_ADDR_CONFIG[0], sizeof(mmUVD_MIF_CURR_ADDR_CONFIG)/sizeof(mmUVD_MIF_CURR_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_MIF_REF_ADDR_CONFIG", REG_MMIO, 0x3993, &mmUVD_MIF_REF_ADDR_CONFIG[0], sizeof(mmUVD_MIF_REF_ADDR_CONFIG)/sizeof(mmUVD_MIF_REF_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_MIF_RECON1_ADDR_CONFIG", REG_MMIO, 0x39c5, &mmUVD_MIF_RECON1_ADDR_CONFIG[0], sizeof(mmUVD_MIF_RECON1_ADDR_CONFIG)/sizeof(mmUVD_MIF_RECON1_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_JPEG_ADDR_CONFIG", REG_MMIO, 0x3a1f, &mmUVD_JPEG_ADDR_CONFIG[0], sizeof(mmUVD_JPEG_ADDR_CONFIG)/sizeof(mmUVD_JPEG_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_SEMA_ADDR_LOW", REG_MMIO, 0x3bc0, &mmUVD_SEMA_ADDR_LOW[0], sizeof(mmUVD_SEMA_ADDR_LOW)/sizeof(mmUVD_SEMA_ADDR_LOW[0]), 0, 0 },
+	{ "mmUVD_SEMA_ADDR_HIGH", REG_MMIO, 0x3bc1, &mmUVD_SEMA_ADDR_HIGH[0], sizeof(mmUVD_SEMA_ADDR_HIGH)/sizeof(mmUVD_SEMA_ADDR_HIGH[0]), 0, 0 },
+	{ "mmUVD_SEMA_CMD", REG_MMIO, 0x3bc2, &mmUVD_SEMA_CMD[0], sizeof(mmUVD_SEMA_CMD)/sizeof(mmUVD_SEMA_CMD[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_CMD", REG_MMIO, 0x3bc3, &mmUVD_GPCOM_VCPU_CMD[0], sizeof(mmUVD_GPCOM_VCPU_CMD)/sizeof(mmUVD_GPCOM_VCPU_CMD[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_DATA0", REG_MMIO, 0x3bc4, &mmUVD_GPCOM_VCPU_DATA0[0], sizeof(mmUVD_GPCOM_VCPU_DATA0)/sizeof(mmUVD_GPCOM_VCPU_DATA0[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_DATA1", REG_MMIO, 0x3bc5, &mmUVD_GPCOM_VCPU_DATA1[0], sizeof(mmUVD_GPCOM_VCPU_DATA1)/sizeof(mmUVD_GPCOM_VCPU_DATA1[0]), 0, 0 },
+	{ "mmUVD_ENGINE_CNTL", REG_MMIO, 0x3bc6, &mmUVD_ENGINE_CNTL[0], sizeof(mmUVD_ENGINE_CNTL)/sizeof(mmUVD_ENGINE_CNTL[0]), 0, 0 },
+	{ "mmUVD_UDEC_ADDR_CONFIG", REG_MMIO, 0x3bd3, &mmUVD_UDEC_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_ADDR_CONFIG)/sizeof(mmUVD_UDEC_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_UDEC_DB_ADDR_CONFIG", REG_MMIO, 0x3bd4, &mmUVD_UDEC_DB_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DB_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_UDEC_DBW_ADDR_CONFIG", REG_MMIO, 0x3bd5, &mmUVD_UDEC_DBW_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_SUVD_CGC_GATE", REG_MMIO, 0x3be4, &mmUVD_SUVD_CGC_GATE[0], sizeof(mmUVD_SUVD_CGC_GATE)/sizeof(mmUVD_SUVD_CGC_GATE[0]), 0, 0 },
+	{ "mmUVD_SUVD_CGC_STATUS", REG_MMIO, 0x3be5, &mmUVD_SUVD_CGC_STATUS[0], sizeof(mmUVD_SUVD_CGC_STATUS)/sizeof(mmUVD_SUVD_CGC_STATUS[0]), 0, 0 },
+	{ "mmUVD_SUVD_CGC_CTRL", REG_MMIO, 0x3be6, &mmUVD_SUVD_CGC_CTRL[0], sizeof(mmUVD_SUVD_CGC_CTRL)/sizeof(mmUVD_SUVD_CGC_CTRL[0]), 0, 0 },
+	{ "mmUVD_NO_OP", REG_MMIO, 0x3bff, NULL, 0, 0, 0 },
+	{ "mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH", REG_MMIO, 0x3c5e, &mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0]), 0, 0 },
+	{ "mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW", REG_MMIO, 0x3c5f, &mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH", REG_MMIO, 0x3c66, &mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_IB_64BIT_BAR_LOW", REG_MMIO, 0x3c67, &mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH", REG_MMIO, 0x3c68, &mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_RB_64BIT_BAR_LOW", REG_MMIO, 0x3c69, &mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[0]), 0, 0 },
+	{ "mmUVD_SEMA_CNTL", REG_MMIO, 0x3d00, &mmUVD_SEMA_CNTL[0], sizeof(mmUVD_SEMA_CNTL)/sizeof(mmUVD_SEMA_CNTL[0]), 0, 0 },
+	{ "mmUVD_LMI_EXT40_ADDR", REG_MMIO, 0x3d26, &mmUVD_LMI_EXT40_ADDR[0], sizeof(mmUVD_LMI_EXT40_ADDR)/sizeof(mmUVD_LMI_EXT40_ADDR[0]), 0, 0 },
+	{ "mmUVD_CTX_INDEX", REG_MMIO, 0x3d28, &mmUVD_CTX_INDEX[0], sizeof(mmUVD_CTX_INDEX)/sizeof(mmUVD_CTX_INDEX[0]), 0, 0 },
+	{ "mmUVD_CTX_DATA", REG_MMIO, 0x3d29, &mmUVD_CTX_DATA[0], sizeof(mmUVD_CTX_DATA)/sizeof(mmUVD_CTX_DATA[0]), 0, 0 },
+	{ "mmUVD_CGC_GATE", REG_MMIO, 0x3d2a, &mmUVD_CGC_GATE[0], sizeof(mmUVD_CGC_GATE)/sizeof(mmUVD_CGC_GATE[0]), 0, 0 },
+	{ "mmUVD_CGC_STATUS", REG_MMIO, 0x3d2b, &mmUVD_CGC_STATUS[0], sizeof(mmUVD_CGC_STATUS)/sizeof(mmUVD_CGC_STATUS[0]), 0, 0 },
+	{ "mmUVD_CGC_CTRL", REG_MMIO, 0x3d2c, &mmUVD_CGC_CTRL[0], sizeof(mmUVD_CGC_CTRL)/sizeof(mmUVD_CGC_CTRL[0]), 0, 0 },
+	{ "mmUVD_CGC_UDEC_STATUS", REG_MMIO, 0x3d2d, &mmUVD_CGC_UDEC_STATUS[0], sizeof(mmUVD_CGC_UDEC_STATUS)/sizeof(mmUVD_CGC_UDEC_STATUS[0]), 0, 0 },
+	{ "mmUVD_LMI_CTRL2", REG_MMIO, 0x3d3d, &mmUVD_LMI_CTRL2[0], sizeof(mmUVD_LMI_CTRL2)/sizeof(mmUVD_LMI_CTRL2[0]), 0, 0 },
+	{ "mmUVD_MASTINT_EN", REG_MMIO, 0x3d40, &mmUVD_MASTINT_EN[0], sizeof(mmUVD_MASTINT_EN)/sizeof(mmUVD_MASTINT_EN[0]), 0, 0 },
+	{ "mmUVD_LMI_ADDR_EXT", REG_MMIO, 0x3d65, &mmUVD_LMI_ADDR_EXT[0], sizeof(mmUVD_LMI_ADDR_EXT)/sizeof(mmUVD_LMI_ADDR_EXT[0]), 0, 0 },
+	{ "mmUVD_LMI_CTRL", REG_MMIO, 0x3d66, &mmUVD_LMI_CTRL[0], sizeof(mmUVD_LMI_CTRL)/sizeof(mmUVD_LMI_CTRL[0]), 0, 0 },
+	{ "mmUVD_LMI_STATUS", REG_MMIO, 0x3d67, &mmUVD_LMI_STATUS[0], sizeof(mmUVD_LMI_STATUS)/sizeof(mmUVD_LMI_STATUS[0]), 0, 0 },
+	{ "mmUVD_LMI_SWAP_CNTL", REG_MMIO, 0x3d6d, &mmUVD_LMI_SWAP_CNTL[0], sizeof(mmUVD_LMI_SWAP_CNTL)/sizeof(mmUVD_LMI_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUVD_MP_SWAP_CNTL", REG_MMIO, 0x3d6f, &mmUVD_MP_SWAP_CNTL[0], sizeof(mmUVD_MP_SWAP_CNTL)/sizeof(mmUVD_MP_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUVD_MPC_CNTL", REG_MMIO, 0x3d77, &mmUVD_MPC_CNTL[0], sizeof(mmUVD_MPC_CNTL)/sizeof(mmUVD_MPC_CNTL[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXA0", REG_MMIO, 0x3d79, &mmUVD_MPC_SET_MUXA0[0], sizeof(mmUVD_MPC_SET_MUXA0)/sizeof(mmUVD_MPC_SET_MUXA0[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXA1", REG_MMIO, 0x3d7a, &mmUVD_MPC_SET_MUXA1[0], sizeof(mmUVD_MPC_SET_MUXA1)/sizeof(mmUVD_MPC_SET_MUXA1[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXB0", REG_MMIO, 0x3d7b, &mmUVD_MPC_SET_MUXB0[0], sizeof(mmUVD_MPC_SET_MUXB0)/sizeof(mmUVD_MPC_SET_MUXB0[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXB1", REG_MMIO, 0x3d7c, &mmUVD_MPC_SET_MUXB1[0], sizeof(mmUVD_MPC_SET_MUXB1)/sizeof(mmUVD_MPC_SET_MUXB1[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUX", REG_MMIO, 0x3d7d, &mmUVD_MPC_SET_MUX[0], sizeof(mmUVD_MPC_SET_MUX)/sizeof(mmUVD_MPC_SET_MUX[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_ALU", REG_MMIO, 0x3d7e, &mmUVD_MPC_SET_ALU[0], sizeof(mmUVD_MPC_SET_ALU)/sizeof(mmUVD_MPC_SET_ALU[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET0", REG_MMIO, 0x3d82, &mmUVD_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_VCPU_CACHE_OFFSET0[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE0", REG_MMIO, 0x3d83, &mmUVD_VCPU_CACHE_SIZE0[0], sizeof(mmUVD_VCPU_CACHE_SIZE0)/sizeof(mmUVD_VCPU_CACHE_SIZE0[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET1", REG_MMIO, 0x3d84, &mmUVD_VCPU_CACHE_OFFSET1[0], sizeof(mmUVD_VCPU_CACHE_OFFSET1)/sizeof(mmUVD_VCPU_CACHE_OFFSET1[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE1", REG_MMIO, 0x3d85, &mmUVD_VCPU_CACHE_SIZE1[0], sizeof(mmUVD_VCPU_CACHE_SIZE1)/sizeof(mmUVD_VCPU_CACHE_SIZE1[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET2", REG_MMIO, 0x3d86, &mmUVD_VCPU_CACHE_OFFSET2[0], sizeof(mmUVD_VCPU_CACHE_OFFSET2)/sizeof(mmUVD_VCPU_CACHE_OFFSET2[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE2", REG_MMIO, 0x3d87, &mmUVD_VCPU_CACHE_SIZE2[0], sizeof(mmUVD_VCPU_CACHE_SIZE2)/sizeof(mmUVD_VCPU_CACHE_SIZE2[0]), 0, 0 },
+	{ "mmUVD_VCPU_CNTL", REG_MMIO, 0x3d98, &mmUVD_VCPU_CNTL[0], sizeof(mmUVD_VCPU_CNTL)/sizeof(mmUVD_VCPU_CNTL[0]), 0, 0 },
+	{ "mmUVD_SOFT_RESET", REG_MMIO, 0x3da0, &mmUVD_SOFT_RESET[0], sizeof(mmUVD_SOFT_RESET)/sizeof(mmUVD_SOFT_RESET[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_IB_VMID", REG_MMIO, 0x3da1, &mmUVD_LMI_RBC_IB_VMID[0], sizeof(mmUVD_LMI_RBC_IB_VMID)/sizeof(mmUVD_LMI_RBC_IB_VMID[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_SIZE", REG_MMIO, 0x3da2, &mmUVD_RBC_IB_SIZE[0], sizeof(mmUVD_RBC_IB_SIZE)/sizeof(mmUVD_RBC_IB_SIZE[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_RB_VMID", REG_MMIO, 0x3da3, &mmUVD_LMI_RBC_RB_VMID[0], sizeof(mmUVD_LMI_RBC_RB_VMID)/sizeof(mmUVD_LMI_RBC_RB_VMID[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_RPTR", REG_MMIO, 0x3da4, &mmUVD_RBC_RB_RPTR[0], sizeof(mmUVD_RBC_RB_RPTR)/sizeof(mmUVD_RBC_RB_RPTR[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_WPTR", REG_MMIO, 0x3da5, &mmUVD_RBC_RB_WPTR[0], sizeof(mmUVD_RBC_RB_WPTR)/sizeof(mmUVD_RBC_RB_WPTR[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_WPTR_CNTL", REG_MMIO, 0x3da6, NULL, 0, 0, 0 },
+	{ "mmUVD_RBC_RB_CNTL", REG_MMIO, 0x3da9, &mmUVD_RBC_RB_CNTL[0], sizeof(mmUVD_RBC_RB_CNTL)/sizeof(mmUVD_RBC_RB_CNTL[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_RPTR_ADDR", REG_MMIO, 0x3daa, &mmUVD_RBC_RB_RPTR_ADDR[0], sizeof(mmUVD_RBC_RB_RPTR_ADDR)/sizeof(mmUVD_RBC_RB_RPTR_ADDR[0]), 0, 0 },
+	{ "mmUVD_STATUS", REG_MMIO, 0x3daf, &mmUVD_STATUS[0], sizeof(mmUVD_STATUS)/sizeof(mmUVD_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_TIMEOUT_STATUS", REG_MMIO, 0x3db0, &mmUVD_SEMA_TIMEOUT_STATUS[0], sizeof(mmUVD_SEMA_TIMEOUT_STATUS)/sizeof(mmUVD_SEMA_TIMEOUT_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3db1, &mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL", REG_MMIO, 0x3db2, &mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3db3, &mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_CONTEXT_ID", REG_MMIO, 0x3dbd, &mmUVD_CONTEXT_ID[0], sizeof(mmUVD_CONTEXT_ID)/sizeof(mmUVD_CONTEXT_ID[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_SIZE_UPDATE", REG_MMIO, 0x3df1, NULL, 0, 0, 0 },
+	{ "ixUVD_MIF_SCLR_ADDR_CONFIG", REG_SMC, 0x4, &ixUVD_MIF_SCLR_ADDR_CONFIG[0], sizeof(ixUVD_MIF_SCLR_ADDR_CONFIG)/sizeof(ixUVD_MIF_SCLR_ADDR_CONFIG[0]), 0, 0 },
+	{ "ixUVD_LMI_VMID_INTERNAL", REG_SMC, 0x99, &ixUVD_LMI_VMID_INTERNAL[0], sizeof(ixUVD_LMI_VMID_INTERNAL)/sizeof(ixUVD_LMI_VMID_INTERNAL[0]), 0, 0 },
+	{ "ixUVD_LMI_VMID_INTERNAL2", REG_SMC, 0x9a, &ixUVD_LMI_VMID_INTERNAL2[0], sizeof(ixUVD_LMI_VMID_INTERNAL2)/sizeof(ixUVD_LMI_VMID_INTERNAL2[0]), 0, 0 },
+	{ "ixUVD_LMI_CACHE_CTRL", REG_SMC, 0x9b, &ixUVD_LMI_CACHE_CTRL[0], sizeof(ixUVD_LMI_CACHE_CTRL)/sizeof(ixUVD_LMI_CACHE_CTRL[0]), 0, 0 },
+	{ "ixUVD_LMI_SWAP_CNTL2", REG_SMC, 0xaa, &ixUVD_LMI_SWAP_CNTL2[0], sizeof(ixUVD_LMI_SWAP_CNTL2)/sizeof(ixUVD_LMI_SWAP_CNTL2[0]), 0, 0 },
+	{ "ixUVD_LMI_ADDR_EXT2", REG_SMC, 0xab, &ixUVD_LMI_ADDR_EXT2[0], sizeof(ixUVD_LMI_ADDR_EXT2)/sizeof(ixUVD_LMI_ADDR_EXT2[0]), 0, 0 },
+	{ "ixUVD_CGC_MEM_CTRL", REG_SMC, 0xc0, &ixUVD_CGC_MEM_CTRL[0], sizeof(ixUVD_CGC_MEM_CTRL)/sizeof(ixUVD_CGC_MEM_CTRL[0]), 0, 0 },
+	{ "ixUVD_CGC_CTRL2", REG_SMC, 0xc1, &ixUVD_CGC_CTRL2[0], sizeof(ixUVD_CGC_CTRL2)/sizeof(ixUVD_CGC_CTRL2[0]), 0, 0 },
diff --git a/src/lib/ip/uvd6.c b/src/lib/ip/uvd6.c
new file mode 100644
index 0000000..8f5cb8f
--- /dev/null
+++ b/src/lib/ip/uvd6.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "uvd60_bits.i"
+
+static const struct umr_reg uvd6_registers[] = {
+#include "uvd60_regs.i"
+};
+
+struct umr_ip_block *umr_create_uvd6(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "uvd6";
+	ip->no_regs = sizeof(uvd6_registers)/sizeof(uvd6_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(uvd6_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, uvd6_registers, sizeof(uvd6_registers));
+	return ip;
+}
diff --git a/src/lib/ip/uvd60_bits.i b/src/lib/ip/uvd60_bits.i
new file mode 100644
index 0000000..c3da80b
--- /dev/null
+++ b/src/lib/ip/uvd60_bits.i
@@ -0,0 +1,673 @@
+static struct umr_bitfield ixUVD_LMI_VMID_INTERNAL3[] = {
+	 { "MIF_GEN_RD0_VMID", 0, 3, &umr_bitfield_default },
+	 { "MIF_GEN_RD1_VMID", 4, 7, &umr_bitfield_default },
+	 { "MIF_GEN_WR0_VMID", 8, 11, &umr_bitfield_default },
+	 { "MIF_GEN_WR1_VMID", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_CONFIG[] = {
+	 { "UVD_PGFSM_FSM_ADDR", 0, 7, &umr_bitfield_default },
+	 { "UVD_PGFSM_POWER_DOWN", 8, 8, &umr_bitfield_default },
+	 { "UVD_PGFSM_POWER_UP", 9, 9, &umr_bitfield_default },
+	 { "UVD_PGFSM_P1_SELECT", 10, 10, &umr_bitfield_default },
+	 { "UVD_PGFSM_P2_SELECT", 11, 11, &umr_bitfield_default },
+	 { "UVD_PGFSM_WRITE", 12, 12, &umr_bitfield_default },
+	 { "UVD_PGFSM_READ", 13, 13, &umr_bitfield_default },
+	 { "UVD_PGFSM_REG_ADDR", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE1[] = {
+	 { "UVD_PGFSM_READ_TILE1_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE2[] = {
+	 { "UVD_PGFSM_READ_TILE2_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_POWER_STATUS[] = {
+	 { "UVD_POWER_STATUS", 0, 1, &umr_bitfield_default },
+	 { "UVD_PG_MODE", 2, 2, &umr_bitfield_default },
+	 { "UVD_STATUS_CHECK_TIMEOUT", 3, 3, &umr_bitfield_default },
+	 { "PWR_ON_CHECK_TIMEOUT", 4, 4, &umr_bitfield_default },
+	 { "PWR_OFF_CHECK_TIMEOUT", 5, 5, &umr_bitfield_default },
+	 { "UVD_PGFSM_TIMEOUT_MODE", 6, 7, &umr_bitfield_default },
+	 { "UVD_PG_EN", 8, 8, &umr_bitfield_default },
+	 { "PAUSE_DPG_REQ", 9, 9, &umr_bitfield_default },
+	 { "PAUSE_DPG_ACK", 10, 10, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE3[] = {
+	 { "UVD_PGFSM_READ_TILE3_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE4[] = {
+	 { "UVD_PGFSM_READ_TILE4_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE5[] = {
+	 { "UVD_PGFSM_READ_TILE5_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE6[] = {
+	 { "UVD_PGFSM_READ_TILE6_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_PGFSM_READ_TILE7[] = {
+	 { "UVD_PGFSM_READ_TILE7_VALUE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MIF_CURR_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MIF_REF_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MIF_RECON1_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_JPEG_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_ADDR_LOW[] = {
+	 { "ADDR_22_3", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_ADDR_HIGH[] = {
+	 { "ADDR_42_23", 0, 19, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_CMD[] = {
+	 { "REQ_CMD", 0, 3, &umr_bitfield_default },
+	 { "WR_PHASE", 4, 5, &umr_bitfield_default },
+	 { "MODE", 6, 6, &umr_bitfield_default },
+	 { "VMID_EN", 7, 7, &umr_bitfield_default },
+	 { "VMID", 8, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_CMD[] = {
+	 { "CMD_SEND", 0, 0, &umr_bitfield_default },
+	 { "CMD", 1, 30, &umr_bitfield_default },
+	 { "CMD_SOURCE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA0[] = {
+	 { "DATA0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_GPCOM_VCPU_DATA1[] = {
+	 { "DATA1", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_ENGINE_CNTL[] = {
+	 { "ENGINE_START", 0, 0, &umr_bitfield_default },
+	 { "ENGINE_START_MODE", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_DB_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_UDEC_DBW_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SUVD_CGC_GATE[] = {
+	 { "SRE", 0, 0, &umr_bitfield_default },
+	 { "SIT", 1, 1, &umr_bitfield_default },
+	 { "SMP", 2, 2, &umr_bitfield_default },
+	 { "SCM", 3, 3, &umr_bitfield_default },
+	 { "SDB", 4, 4, &umr_bitfield_default },
+	 { "SRE_H264", 5, 5, &umr_bitfield_default },
+	 { "SRE_HEVC", 6, 6, &umr_bitfield_default },
+	 { "SIT_H264", 7, 7, &umr_bitfield_default },
+	 { "SIT_HEVC", 8, 8, &umr_bitfield_default },
+	 { "SCM_H264", 9, 9, &umr_bitfield_default },
+	 { "SCM_HEVC", 10, 10, &umr_bitfield_default },
+	 { "SDB_H264", 11, 11, &umr_bitfield_default },
+	 { "SDB_HEVC", 12, 12, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SUVD_CGC_STATUS[] = {
+	 { "SRE_VCLK", 0, 0, &umr_bitfield_default },
+	 { "SRE_DCLK", 1, 1, &umr_bitfield_default },
+	 { "SIT_DCLK", 2, 2, &umr_bitfield_default },
+	 { "SMP_DCLK", 3, 3, &umr_bitfield_default },
+	 { "SCM_DCLK", 4, 4, &umr_bitfield_default },
+	 { "SDB_DCLK", 5, 5, &umr_bitfield_default },
+	 { "SRE_H264_VCLK", 6, 6, &umr_bitfield_default },
+	 { "SRE_HEVC_VCLK", 7, 7, &umr_bitfield_default },
+	 { "SIT_H264_DCLK", 8, 8, &umr_bitfield_default },
+	 { "SIT_HEVC_DCLK", 9, 9, &umr_bitfield_default },
+	 { "SCM_H264_DCLK", 10, 10, &umr_bitfield_default },
+	 { "SCM_HEVC_DCLK", 11, 11, &umr_bitfield_default },
+	 { "SDB_H264_DCLK", 12, 12, &umr_bitfield_default },
+	 { "SDB_HEVC_DCLK", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SUVD_CGC_CTRL[] = {
+	 { "SRE_MODE", 0, 0, &umr_bitfield_default },
+	 { "SIT_MODE", 1, 1, &umr_bitfield_default },
+	 { "SMP_MODE", 2, 2, &umr_bitfield_default },
+	 { "SCM_MODE", 3, 3, &umr_bitfield_default },
+	 { "SDB_MODE", 4, 4, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_POWER_STATUS_U[] = {
+	 { "UVD_POWER_STATUS", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[] = {
+	 { "BITS_63_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[] = {
+	 { "BITS_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[] = {
+	 { "BITS_63_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[] = {
+	 { "BITS_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[] = {
+	 { "BITS_63_32", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[] = {
+	 { "BITS_31_0", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_CNTL[] = {
+	 { "SEMAPHORE_EN", 0, 0, &umr_bitfield_default },
+	 { "ADVANCED_MODE_DIS", 1, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_EXT40_ADDR[] = {
+	 { "ADDR", 0, 7, &umr_bitfield_default },
+	 { "INDEX", 16, 20, &umr_bitfield_default },
+	 { "WRITE_ADDR", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CTX_INDEX[] = {
+	 { "INDEX", 0, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CTX_DATA[] = {
+	 { "DATA", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_GATE[] = {
+	 { "SYS", 0, 0, &umr_bitfield_default },
+	 { "UDEC", 1, 1, &umr_bitfield_default },
+	 { "MPEG2", 2, 2, &umr_bitfield_default },
+	 { "REGS", 3, 3, &umr_bitfield_default },
+	 { "RBC", 4, 4, &umr_bitfield_default },
+	 { "LMI_MC", 5, 5, &umr_bitfield_default },
+	 { "LMI_UMC", 6, 6, &umr_bitfield_default },
+	 { "IDCT", 7, 7, &umr_bitfield_default },
+	 { "MPRD", 8, 8, &umr_bitfield_default },
+	 { "MPC", 9, 9, &umr_bitfield_default },
+	 { "LBSI", 10, 10, &umr_bitfield_default },
+	 { "LRBBM", 11, 11, &umr_bitfield_default },
+	 { "UDEC_RE", 12, 12, &umr_bitfield_default },
+	 { "UDEC_CM", 13, 13, &umr_bitfield_default },
+	 { "UDEC_IT", 14, 14, &umr_bitfield_default },
+	 { "UDEC_DB", 15, 15, &umr_bitfield_default },
+	 { "UDEC_MP", 16, 16, &umr_bitfield_default },
+	 { "WCB", 17, 17, &umr_bitfield_default },
+	 { "VCPU", 18, 18, &umr_bitfield_default },
+	 { "SCPU", 19, 19, &umr_bitfield_default },
+	 { "JPEG", 20, 20, &umr_bitfield_default },
+	 { "JPEG2", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_STATUS[] = {
+	 { "SYS_SCLK", 0, 0, &umr_bitfield_default },
+	 { "SYS_DCLK", 1, 1, &umr_bitfield_default },
+	 { "SYS_VCLK", 2, 2, &umr_bitfield_default },
+	 { "UDEC_SCLK", 3, 3, &umr_bitfield_default },
+	 { "UDEC_DCLK", 4, 4, &umr_bitfield_default },
+	 { "UDEC_VCLK", 5, 5, &umr_bitfield_default },
+	 { "MPEG2_SCLK", 6, 6, &umr_bitfield_default },
+	 { "MPEG2_DCLK", 7, 7, &umr_bitfield_default },
+	 { "MPEG2_VCLK", 8, 8, &umr_bitfield_default },
+	 { "REGS_SCLK", 9, 9, &umr_bitfield_default },
+	 { "REGS_VCLK", 10, 10, &umr_bitfield_default },
+	 { "RBC_SCLK", 11, 11, &umr_bitfield_default },
+	 { "LMI_MC_SCLK", 12, 12, &umr_bitfield_default },
+	 { "LMI_UMC_SCLK", 13, 13, &umr_bitfield_default },
+	 { "IDCT_SCLK", 14, 14, &umr_bitfield_default },
+	 { "IDCT_VCLK", 15, 15, &umr_bitfield_default },
+	 { "MPRD_SCLK", 16, 16, &umr_bitfield_default },
+	 { "MPRD_DCLK", 17, 17, &umr_bitfield_default },
+	 { "MPRD_VCLK", 18, 18, &umr_bitfield_default },
+	 { "MPC_SCLK", 19, 19, &umr_bitfield_default },
+	 { "MPC_DCLK", 20, 20, &umr_bitfield_default },
+	 { "LBSI_SCLK", 21, 21, &umr_bitfield_default },
+	 { "LBSI_VCLK", 22, 22, &umr_bitfield_default },
+	 { "LRBBM_SCLK", 23, 23, &umr_bitfield_default },
+	 { "WCB_SCLK", 24, 24, &umr_bitfield_default },
+	 { "VCPU_SCLK", 25, 25, &umr_bitfield_default },
+	 { "VCPU_VCLK", 26, 26, &umr_bitfield_default },
+	 { "SCPU_SCLK", 27, 27, &umr_bitfield_default },
+	 { "SCPU_VCLK", 28, 28, &umr_bitfield_default },
+	 { "JPEG_ACTIVE", 30, 30, &umr_bitfield_default },
+	 { "ALL_DEC_ACTIVE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_CTRL[] = {
+	 { "DYN_CLOCK_MODE", 0, 0, &umr_bitfield_default },
+	 { "JPEG2_MODE", 1, 1, &umr_bitfield_default },
+	 { "CLK_GATE_DLY_TIMER", 2, 5, &umr_bitfield_default },
+	 { "CLK_OFF_DELAY", 6, 10, &umr_bitfield_default },
+	 { "UDEC_RE_MODE", 11, 11, &umr_bitfield_default },
+	 { "UDEC_CM_MODE", 12, 12, &umr_bitfield_default },
+	 { "UDEC_IT_MODE", 13, 13, &umr_bitfield_default },
+	 { "UDEC_DB_MODE", 14, 14, &umr_bitfield_default },
+	 { "UDEC_MP_MODE", 15, 15, &umr_bitfield_default },
+	 { "SYS_MODE", 16, 16, &umr_bitfield_default },
+	 { "UDEC_MODE", 17, 17, &umr_bitfield_default },
+	 { "MPEG2_MODE", 18, 18, &umr_bitfield_default },
+	 { "REGS_MODE", 19, 19, &umr_bitfield_default },
+	 { "RBC_MODE", 20, 20, &umr_bitfield_default },
+	 { "LMI_MC_MODE", 21, 21, &umr_bitfield_default },
+	 { "LMI_UMC_MODE", 22, 22, &umr_bitfield_default },
+	 { "IDCT_MODE", 23, 23, &umr_bitfield_default },
+	 { "MPRD_MODE", 24, 24, &umr_bitfield_default },
+	 { "MPC_MODE", 25, 25, &umr_bitfield_default },
+	 { "LBSI_MODE", 26, 26, &umr_bitfield_default },
+	 { "LRBBM_MODE", 27, 27, &umr_bitfield_default },
+	 { "WCB_MODE", 28, 28, &umr_bitfield_default },
+	 { "VCPU_MODE", 29, 29, &umr_bitfield_default },
+	 { "SCPU_MODE", 30, 30, &umr_bitfield_default },
+	 { "JPEG_MODE", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CGC_UDEC_STATUS[] = {
+	 { "RE_SCLK", 0, 0, &umr_bitfield_default },
+	 { "RE_DCLK", 1, 1, &umr_bitfield_default },
+	 { "RE_VCLK", 2, 2, &umr_bitfield_default },
+	 { "CM_SCLK", 3, 3, &umr_bitfield_default },
+	 { "CM_DCLK", 4, 4, &umr_bitfield_default },
+	 { "CM_VCLK", 5, 5, &umr_bitfield_default },
+	 { "IT_SCLK", 6, 6, &umr_bitfield_default },
+	 { "IT_DCLK", 7, 7, &umr_bitfield_default },
+	 { "IT_VCLK", 8, 8, &umr_bitfield_default },
+	 { "DB_SCLK", 9, 9, &umr_bitfield_default },
+	 { "DB_DCLK", 10, 10, &umr_bitfield_default },
+	 { "DB_VCLK", 11, 11, &umr_bitfield_default },
+	 { "MP_SCLK", 12, 12, &umr_bitfield_default },
+	 { "MP_DCLK", 13, 13, &umr_bitfield_default },
+	 { "MP_VCLK", 14, 14, &umr_bitfield_default },
+	 { "JPEG_VCLK", 15, 15, &umr_bitfield_default },
+	 { "JPEG_SCLK", 16, 16, &umr_bitfield_default },
+	 { "JPEG2_VCLK", 17, 17, &umr_bitfield_default },
+	 { "JPEG2_SCLK", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_CTRL2[] = {
+	 { "SPH_DIS", 0, 0, &umr_bitfield_default },
+	 { "STALL_ARB", 1, 1, &umr_bitfield_default },
+	 { "ASSERT_UMC_URGENT", 2, 2, &umr_bitfield_default },
+	 { "MASK_UMC_URGENT", 3, 3, &umr_bitfield_default },
+	 { "MCIF_WR_WATERMARK", 4, 6, &umr_bitfield_default },
+	 { "DRCITF_BUBBLE_FIX_DIS", 7, 7, &umr_bitfield_default },
+	 { "STALL_ARB_UMC", 8, 8, &umr_bitfield_default },
+	 { "MC_READ_ID_SEL", 9, 10, &umr_bitfield_default },
+	 { "MC_WRITE_ID_SEL", 11, 12, &umr_bitfield_default },
+	 { "VCPU_NC0_EXT_EN", 13, 13, &umr_bitfield_default },
+	 { "VCPU_NC1_EXT_EN", 14, 14, &umr_bitfield_default },
+	 { "SPU_EXTRA_CID_EN", 15, 15, &umr_bitfield_default },
+	 { "RE_OFFLOAD_EN", 16, 16, &umr_bitfield_default },
+	 { "RE_OFLD_MIF_WR_REQ_NUM", 17, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MASTINT_EN[] = {
+	 { "OVERRUN_RST", 0, 0, &umr_bitfield_default },
+	 { "VCPU_EN", 1, 1, &umr_bitfield_default },
+	 { "SYS_EN", 2, 2, &umr_bitfield_default },
+	 { "INT_OVERRUN", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_ADDR_EXT[] = {
+	 { "VCPU_ADDR_EXT", 0, 3, &umr_bitfield_default },
+	 { "CM_ADDR_EXT", 4, 7, &umr_bitfield_default },
+	 { "IT_ADDR_EXT", 8, 11, &umr_bitfield_default },
+	 { "VCPU_VM_ADDR_EXT", 12, 15, &umr_bitfield_default },
+	 { "RE_ADDR_EXT", 16, 19, &umr_bitfield_default },
+	 { "MP_ADDR_EXT", 20, 23, &umr_bitfield_default },
+	 { "VCPU_NC0_ADDR_EXT", 24, 27, &umr_bitfield_default },
+	 { "VCPU_NC1_ADDR_EXT", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_CTRL[] = {
+	 { "WRITE_CLEAN_TIMER", 0, 7, &umr_bitfield_default },
+	 { "WRITE_CLEAN_TIMER_EN", 8, 8, &umr_bitfield_default },
+	 { "REQ_MODE", 9, 9, &umr_bitfield_default },
+	 { "ASSERT_MC_URGENT", 11, 11, &umr_bitfield_default },
+	 { "MASK_MC_URGENT", 12, 12, &umr_bitfield_default },
+	 { "DATA_COHERENCY_EN", 13, 13, &umr_bitfield_default },
+	 { "CRC_RESET", 14, 14, &umr_bitfield_default },
+	 { "CRC_SEL", 15, 19, &umr_bitfield_default },
+	 { "DISABLE_ON_FWV_FAIL", 20, 20, &umr_bitfield_default },
+	 { "VCPU_DATA_COHERENCY_EN", 21, 21, &umr_bitfield_default },
+	 { "CM_DATA_COHERENCY_EN", 22, 22, &umr_bitfield_default },
+	 { "DB_DB_DATA_COHERENCY_EN", 23, 23, &umr_bitfield_default },
+	 { "DB_IT_DATA_COHERENCY_EN", 24, 24, &umr_bitfield_default },
+	 { "IT_IT_DATA_COHERENCY_EN", 25, 25, &umr_bitfield_default },
+	 { "MIF_MIF_DATA_COHERENCY_EN", 26, 26, &umr_bitfield_default },
+	 { "RFU", 27, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_STATUS[] = {
+	 { "READ_CLEAN", 0, 0, &umr_bitfield_default },
+	 { "WRITE_CLEAN", 1, 1, &umr_bitfield_default },
+	 { "WRITE_CLEAN_RAW", 2, 2, &umr_bitfield_default },
+	 { "VCPU_LMI_WRITE_CLEAN", 3, 3, &umr_bitfield_default },
+	 { "UMC_READ_CLEAN", 4, 4, &umr_bitfield_default },
+	 { "UMC_WRITE_CLEAN", 5, 5, &umr_bitfield_default },
+	 { "UMC_WRITE_CLEAN_RAW", 6, 6, &umr_bitfield_default },
+	 { "PENDING_UVD_MC_WRITE", 7, 7, &umr_bitfield_default },
+	 { "READ_CLEAN_RAW", 8, 8, &umr_bitfield_default },
+	 { "UMC_READ_CLEAN_RAW", 9, 9, &umr_bitfield_default },
+	 { "UMC_UVD_IDLE", 10, 10, &umr_bitfield_default },
+	 { "UMC_AVP_IDLE", 11, 11, &umr_bitfield_default },
+	 { "ADP_MC_READ_CLEAN", 12, 12, &umr_bitfield_default },
+	 { "ADP_UMC_READ_CLEAN", 13, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_SWAP_CNTL[] = {
+	 { "RB_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "IB_MC_SWAP", 2, 3, &umr_bitfield_default },
+	 { "RB_RPTR_MC_SWAP", 4, 5, &umr_bitfield_default },
+	 { "VCPU_R_MC_SWAP", 6, 7, &umr_bitfield_default },
+	 { "VCPU_W_MC_SWAP", 8, 9, &umr_bitfield_default },
+	 { "CM_MC_SWAP", 10, 11, &umr_bitfield_default },
+	 { "IT_MC_SWAP", 12, 13, &umr_bitfield_default },
+	 { "DB_R_MC_SWAP", 14, 15, &umr_bitfield_default },
+	 { "DB_W_MC_SWAP", 16, 17, &umr_bitfield_default },
+	 { "CSM_MC_SWAP", 18, 19, &umr_bitfield_default },
+	 { "MP_REF16_MC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "DBW_MC_SWAP", 24, 25, &umr_bitfield_default },
+	 { "RB_WR_MC_SWAP", 26, 27, &umr_bitfield_default },
+	 { "RE_MC_SWAP", 28, 29, &umr_bitfield_default },
+	 { "MP_MC_SWAP", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MP_SWAP_CNTL[] = {
+	 { "MP_REF0_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "MP_REF1_MC_SWAP", 2, 3, &umr_bitfield_default },
+	 { "MP_REF2_MC_SWAP", 4, 5, &umr_bitfield_default },
+	 { "MP_REF3_MC_SWAP", 6, 7, &umr_bitfield_default },
+	 { "MP_REF4_MC_SWAP", 8, 9, &umr_bitfield_default },
+	 { "MP_REF5_MC_SWAP", 10, 11, &umr_bitfield_default },
+	 { "MP_REF6_MC_SWAP", 12, 13, &umr_bitfield_default },
+	 { "MP_REF7_MC_SWAP", 14, 15, &umr_bitfield_default },
+	 { "MP_REF8_MC_SWAP", 16, 17, &umr_bitfield_default },
+	 { "MP_REF9_MC_SWAP", 18, 19, &umr_bitfield_default },
+	 { "MP_REF10_MC_SWAP", 20, 21, &umr_bitfield_default },
+	 { "MP_REF11_MC_SWAP", 22, 23, &umr_bitfield_default },
+	 { "MP_REF12_MC_SWAP", 24, 25, &umr_bitfield_default },
+	 { "MP_REF13_MC_SWAP", 26, 27, &umr_bitfield_default },
+	 { "MP_REF14_MC_SWAP", 28, 29, &umr_bitfield_default },
+	 { "MP_REF15_MC_SWAP", 30, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_CNTL[] = {
+	 { "REPLACEMENT_MODE", 3, 5, &umr_bitfield_default },
+	 { "PERF_RST", 6, 6, &umr_bitfield_default },
+	 { "DBG_MUX", 8, 11, &umr_bitfield_default },
+	 { "AVE_WEIGHT", 16, 17, &umr_bitfield_default },
+	 { "URGENT_EN", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXA0[] = {
+	 { "VARA_0", 0, 5, &umr_bitfield_default },
+	 { "VARA_1", 6, 11, &umr_bitfield_default },
+	 { "VARA_2", 12, 17, &umr_bitfield_default },
+	 { "VARA_3", 18, 23, &umr_bitfield_default },
+	 { "VARA_4", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXA1[] = {
+	 { "VARA_5", 0, 5, &umr_bitfield_default },
+	 { "VARA_6", 6, 11, &umr_bitfield_default },
+	 { "VARA_7", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXB0[] = {
+	 { "VARB_0", 0, 5, &umr_bitfield_default },
+	 { "VARB_1", 6, 11, &umr_bitfield_default },
+	 { "VARB_2", 12, 17, &umr_bitfield_default },
+	 { "VARB_3", 18, 23, &umr_bitfield_default },
+	 { "VARB_4", 24, 29, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUXB1[] = {
+	 { "VARB_5", 0, 5, &umr_bitfield_default },
+	 { "VARB_6", 6, 11, &umr_bitfield_default },
+	 { "VARB_7", 12, 17, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_MUX[] = {
+	 { "SET_0", 0, 2, &umr_bitfield_default },
+	 { "SET_1", 3, 5, &umr_bitfield_default },
+	 { "SET_2", 6, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_MPC_SET_ALU[] = {
+	 { "FUNCT", 0, 2, &umr_bitfield_default },
+	 { "OPERAND", 4, 11, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET0[] = {
+	 { "CACHE_OFFSET0", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE0[] = {
+	 { "CACHE_SIZE0", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET1[] = {
+	 { "CACHE_OFFSET1", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE1[] = {
+	 { "CACHE_SIZE1", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_OFFSET2[] = {
+	 { "CACHE_OFFSET2", 0, 24, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CACHE_SIZE2[] = {
+	 { "CACHE_SIZE2", 0, 20, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_VCPU_CNTL[] = {
+	 { "IRQ_ERR", 0, 3, &umr_bitfield_default },
+	 { "AXI_MAX_BRST_SIZE_IS_4", 4, 4, &umr_bitfield_default },
+	 { "PMB_ED_ENABLE", 5, 5, &umr_bitfield_default },
+	 { "PMB_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "RBBM_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "ABORT_REQ", 8, 8, &umr_bitfield_default },
+	 { "CLK_EN", 9, 9, &umr_bitfield_default },
+	 { "TRCE_EN", 10, 10, &umr_bitfield_default },
+	 { "TRCE_MUX", 11, 12, &umr_bitfield_default },
+	 { "DBG_MUX", 13, 15, &umr_bitfield_default },
+	 { "JTAG_EN", 16, 16, &umr_bitfield_default },
+	 { "MIF_WR_LOW_THRESHOLD_BP", 17, 17, &umr_bitfield_default },
+	 { "TIMEOUT_DIS", 18, 18, &umr_bitfield_default },
+	 { "SUVD_EN", 19, 19, &umr_bitfield_default },
+	 { "PRB_TIMEOUT_VAL", 20, 27, &umr_bitfield_default },
+	 { "CABAC_MB_ACC", 28, 28, &umr_bitfield_default },
+	 { "WMV9_EN", 30, 30, &umr_bitfield_default },
+	 { "RE_OFFLOAD_EN", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SOFT_RESET[] = {
+	 { "RBC_SOFT_RESET", 0, 0, &umr_bitfield_default },
+	 { "LBSI_SOFT_RESET", 1, 1, &umr_bitfield_default },
+	 { "LMI_SOFT_RESET", 2, 2, &umr_bitfield_default },
+	 { "VCPU_SOFT_RESET", 3, 3, &umr_bitfield_default },
+	 { "UDEC_SOFT_RESET", 4, 4, &umr_bitfield_default },
+	 { "CSM_SOFT_RESET", 5, 5, &umr_bitfield_default },
+	 { "CXW_SOFT_RESET", 6, 6, &umr_bitfield_default },
+	 { "TAP_SOFT_RESET", 7, 7, &umr_bitfield_default },
+	 { "MPC_SOFT_RESET", 8, 8, &umr_bitfield_default },
+	 { "JPEG_SCLK_RESET_STATUS", 9, 9, &umr_bitfield_default },
+	 { "IH_SOFT_RESET", 10, 10, &umr_bitfield_default },
+	 { "MPRD_SOFT_RESET", 11, 11, &umr_bitfield_default },
+	 { "IDCT_SOFT_RESET", 12, 12, &umr_bitfield_default },
+	 { "LMI_UMC_SOFT_RESET", 13, 13, &umr_bitfield_default },
+	 { "SPH_SOFT_RESET", 14, 14, &umr_bitfield_default },
+	 { "MIF_SOFT_RESET", 15, 15, &umr_bitfield_default },
+	 { "LCM_SOFT_RESET", 16, 16, &umr_bitfield_default },
+	 { "SUVD_SOFT_RESET", 17, 17, &umr_bitfield_default },
+	 { "LBSI_VCLK_RESET_STATUS", 18, 18, &umr_bitfield_default },
+	 { "VCPU_VCLK_RESET_STATUS", 19, 19, &umr_bitfield_default },
+	 { "UDEC_VCLK_RESET_STATUS", 20, 20, &umr_bitfield_default },
+	 { "UDEC_DCLK_RESET_STATUS", 21, 21, &umr_bitfield_default },
+	 { "MPC_DCLK_RESET_STATUS", 22, 22, &umr_bitfield_default },
+	 { "MPRD_VCLK_RESET_STATUS", 23, 23, &umr_bitfield_default },
+	 { "MPRD_DCLK_RESET_STATUS", 24, 24, &umr_bitfield_default },
+	 { "IDCT_VCLK_RESET_STATUS", 25, 25, &umr_bitfield_default },
+	 { "MIF_DCLK_RESET_STATUS", 26, 26, &umr_bitfield_default },
+	 { "LCM_DCLK_RESET_STATUS", 27, 27, &umr_bitfield_default },
+	 { "SUVD_VCLK_RESET_STATUS", 28, 28, &umr_bitfield_default },
+	 { "SUVD_DCLK_RESET_STATUS", 29, 29, &umr_bitfield_default },
+	 { "RE_DCLK_RESET_STATUS", 30, 30, &umr_bitfield_default },
+	 { "SRE_DCLK_RESET_STATUS", 31, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_IB_VMID[] = {
+	 { "IB_VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_IB_SIZE[] = {
+	 { "IB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_LMI_RBC_RB_VMID[] = {
+	 { "RB_VMID", 0, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_RPTR[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_WPTR[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_CNTL[] = {
+	 { "RB_BUFSZ", 0, 4, &umr_bitfield_default },
+	 { "RB_BLKSZ", 8, 12, &umr_bitfield_default },
+	 { "RB_NO_FETCH", 16, 16, &umr_bitfield_default },
+	 { "RB_WPTR_POLL_EN", 20, 20, &umr_bitfield_default },
+	 { "RB_NO_UPDATE", 24, 24, &umr_bitfield_default },
+	 { "RB_RPTR_WR_EN", 28, 28, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_RBC_RB_RPTR_ADDR[] = {
+	 { "RB_RPTR_ADDR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_STATUS[] = {
+	 { "RBC_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VCPU_REPORT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_TIMEOUT_STATUS[] = {
+	 { "SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT", 0, 0, &umr_bitfield_default },
+	 { "SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT", 1, 1, &umr_bitfield_default },
+	 { "SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT", 2, 2, &umr_bitfield_default },
+	 { "SEMAPHORE_TIMEOUT_CLEAR", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[] = {
+	 { "WAIT_INCOMPLETE_EN", 0, 0, &umr_bitfield_default },
+	 { "WAIT_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[] = {
+	 { "WAIT_FAULT_EN", 0, 0, &umr_bitfield_default },
+	 { "WAIT_FAULT_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[] = {
+	 { "SIGNAL_INCOMPLETE_EN", 0, 0, &umr_bitfield_default },
+	 { "SIGNAL_INCOMPLETE_COUNT", 1, 20, &umr_bitfield_default },
+	 { "RESEND_TIMER", 24, 26, &umr_bitfield_default },
+};
+static struct umr_bitfield mmUVD_CONTEXT_ID[] = {
+	 { "CONTEXT_ID", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_MIF_SCLR_ADDR_CONFIG[] = {
+	 { "NUM_PIPES", 0, 2, &umr_bitfield_default },
+	 { "PIPE_INTERLEAVE_SIZE", 4, 6, &umr_bitfield_default },
+	 { "BANK_INTERLEAVE_SIZE", 8, 10, &umr_bitfield_default },
+	 { "NUM_SHADER_ENGINES", 12, 13, &umr_bitfield_default },
+	 { "SHADER_ENGINE_TILE_SIZE", 16, 18, &umr_bitfield_default },
+	 { "NUM_GPUS", 20, 22, &umr_bitfield_default },
+	 { "MULTI_GPU_TILE_SIZE", 24, 25, &umr_bitfield_default },
+	 { "ROW_SIZE", 28, 29, &umr_bitfield_default },
+	 { "NUM_LOWER_PIPES", 30, 30, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_VMID_INTERNAL[] = {
+	 { "VCPU_NC0_VMID", 0, 3, &umr_bitfield_default },
+	 { "VCPU_NC1_VMID", 4, 7, &umr_bitfield_default },
+	 { "DPB_VMID", 8, 11, &umr_bitfield_default },
+	 { "DBW_VMID", 12, 15, &umr_bitfield_default },
+	 { "LBSI_VMID", 16, 19, &umr_bitfield_default },
+	 { "IDCT_VMID", 20, 23, &umr_bitfield_default },
+	 { "JPEG_VMID", 24, 27, &umr_bitfield_default },
+	 { "JPEG2_VMID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_VMID_INTERNAL2[] = {
+	 { "MIF_GPGPU_VMID", 0, 3, &umr_bitfield_default },
+	 { "MIF_CURR_VMID", 4, 7, &umr_bitfield_default },
+	 { "MIF_REF_VMID", 8, 11, &umr_bitfield_default },
+	 { "MIF_DBW_VMID", 12, 15, &umr_bitfield_default },
+	 { "MIF_CM_COLOC_VMID", 16, 19, &umr_bitfield_default },
+	 { "MIF_BSD_VMID", 20, 23, &umr_bitfield_default },
+	 { "MIF_BSP_VMID", 24, 27, &umr_bitfield_default },
+	 { "VDMA_VMID", 28, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_CACHE_CTRL[] = {
+	 { "IT_EN", 0, 0, &umr_bitfield_default },
+	 { "IT_FLUSH", 1, 1, &umr_bitfield_default },
+	 { "CM_EN", 2, 2, &umr_bitfield_default },
+	 { "CM_FLUSH", 3, 3, &umr_bitfield_default },
+	 { "VCPU_EN", 4, 4, &umr_bitfield_default },
+	 { "VCPU_FLUSH", 5, 5, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_SWAP_CNTL2[] = {
+	 { "SCPU_R_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "SCPU_W_MC_SWAP", 2, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_LMI_ADDR_EXT2[] = {
+	 { "SCPU_ADDR_EXT", 0, 3, &umr_bitfield_default },
+	 { "SCPU_VM_ADDR_EXT", 4, 7, &umr_bitfield_default },
+	 { "SCPU_NC0_ADDR_EXT", 8, 11, &umr_bitfield_default },
+	 { "SCPU_NC1_ADDR_EXT", 12, 15, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_CGC_MEM_CTRL[] = {
+	 { "LMI_MC_LS_EN", 0, 0, &umr_bitfield_default },
+	 { "MPC_LS_EN", 1, 1, &umr_bitfield_default },
+	 { "MPRD_LS_EN", 2, 2, &umr_bitfield_default },
+	 { "WCB_LS_EN", 3, 3, &umr_bitfield_default },
+	 { "UDEC_RE_LS_EN", 4, 4, &umr_bitfield_default },
+	 { "UDEC_CM_LS_EN", 5, 5, &umr_bitfield_default },
+	 { "UDEC_IT_LS_EN", 6, 6, &umr_bitfield_default },
+	 { "UDEC_DB_LS_EN", 7, 7, &umr_bitfield_default },
+	 { "UDEC_MP_LS_EN", 8, 8, &umr_bitfield_default },
+	 { "SYS_LS_EN", 9, 9, &umr_bitfield_default },
+	 { "VCPU_LS_EN", 10, 10, &umr_bitfield_default },
+	 { "SCPU_LS_EN", 11, 11, &umr_bitfield_default },
+	 { "MIF_LS_EN", 12, 12, &umr_bitfield_default },
+	 { "LCM_LS_EN", 13, 13, &umr_bitfield_default },
+	 { "JPEG_LS_EN", 14, 14, &umr_bitfield_default },
+	 { "JPEG2_LS_EN", 15, 15, &umr_bitfield_default },
+	 { "LS_SET_DELAY", 16, 19, &umr_bitfield_default },
+	 { "LS_CLEAR_DELAY", 20, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield ixUVD_CGC_CTRL2[] = {
+	 { "DYN_OCLK_RAMP_EN", 0, 0, &umr_bitfield_default },
+	 { "DYN_RCLK_RAMP_EN", 1, 1, &umr_bitfield_default },
+	 { "GATER_DIV_ID", 2, 4, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/uvd60_regs.i b/src/lib/ip/uvd60_regs.i
new file mode 100644
index 0000000..a5d84bb
--- /dev/null
+++ b/src/lib/ip/uvd60_regs.i
@@ -0,0 +1,91 @@
+	{ "ixUVD_LMI_VMID_INTERNAL3", REG_SMC, 0x162, &ixUVD_LMI_VMID_INTERNAL3[0], sizeof(ixUVD_LMI_VMID_INTERNAL3)/sizeof(ixUVD_LMI_VMID_INTERNAL3[0]), 0, 0 },
+	{ "mmUVD_PGFSM_CONFIG", REG_MMIO, 0x38c0, &mmUVD_PGFSM_CONFIG[0], sizeof(mmUVD_PGFSM_CONFIG)/sizeof(mmUVD_PGFSM_CONFIG[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE1", REG_MMIO, 0x38c2, &mmUVD_PGFSM_READ_TILE1[0], sizeof(mmUVD_PGFSM_READ_TILE1)/sizeof(mmUVD_PGFSM_READ_TILE1[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE2", REG_MMIO, 0x38c3, &mmUVD_PGFSM_READ_TILE2[0], sizeof(mmUVD_PGFSM_READ_TILE2)/sizeof(mmUVD_PGFSM_READ_TILE2[0]), 0, 0 },
+	{ "mmUVD_POWER_STATUS", REG_MMIO, 0x38c4, &mmUVD_POWER_STATUS[0], sizeof(mmUVD_POWER_STATUS)/sizeof(mmUVD_POWER_STATUS[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE3", REG_MMIO, 0x38c5, &mmUVD_PGFSM_READ_TILE3[0], sizeof(mmUVD_PGFSM_READ_TILE3)/sizeof(mmUVD_PGFSM_READ_TILE3[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE4", REG_MMIO, 0x38c6, &mmUVD_PGFSM_READ_TILE4[0], sizeof(mmUVD_PGFSM_READ_TILE4)/sizeof(mmUVD_PGFSM_READ_TILE4[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE5", REG_MMIO, 0x38c8, &mmUVD_PGFSM_READ_TILE5[0], sizeof(mmUVD_PGFSM_READ_TILE5)/sizeof(mmUVD_PGFSM_READ_TILE5[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE6", REG_MMIO, 0x38ee, &mmUVD_PGFSM_READ_TILE6[0], sizeof(mmUVD_PGFSM_READ_TILE6)/sizeof(mmUVD_PGFSM_READ_TILE6[0]), 0, 0 },
+	{ "mmUVD_PGFSM_READ_TILE7", REG_MMIO, 0x38ef, &mmUVD_PGFSM_READ_TILE7[0], sizeof(mmUVD_PGFSM_READ_TILE7)/sizeof(mmUVD_PGFSM_READ_TILE7[0]), 0, 0 },
+	{ "mmUVD_MIF_CURR_ADDR_CONFIG", REG_MMIO, 0x3992, &mmUVD_MIF_CURR_ADDR_CONFIG[0], sizeof(mmUVD_MIF_CURR_ADDR_CONFIG)/sizeof(mmUVD_MIF_CURR_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_MIF_REF_ADDR_CONFIG", REG_MMIO, 0x3993, &mmUVD_MIF_REF_ADDR_CONFIG[0], sizeof(mmUVD_MIF_REF_ADDR_CONFIG)/sizeof(mmUVD_MIF_REF_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_MIF_RECON1_ADDR_CONFIG", REG_MMIO, 0x39c5, &mmUVD_MIF_RECON1_ADDR_CONFIG[0], sizeof(mmUVD_MIF_RECON1_ADDR_CONFIG)/sizeof(mmUVD_MIF_RECON1_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_JPEG_ADDR_CONFIG", REG_MMIO, 0x3a1f, &mmUVD_JPEG_ADDR_CONFIG[0], sizeof(mmUVD_JPEG_ADDR_CONFIG)/sizeof(mmUVD_JPEG_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_SEMA_ADDR_LOW", REG_MMIO, 0x3bc0, &mmUVD_SEMA_ADDR_LOW[0], sizeof(mmUVD_SEMA_ADDR_LOW)/sizeof(mmUVD_SEMA_ADDR_LOW[0]), 0, 0 },
+	{ "mmUVD_SEMA_ADDR_HIGH", REG_MMIO, 0x3bc1, &mmUVD_SEMA_ADDR_HIGH[0], sizeof(mmUVD_SEMA_ADDR_HIGH)/sizeof(mmUVD_SEMA_ADDR_HIGH[0]), 0, 0 },
+	{ "mmUVD_SEMA_CMD", REG_MMIO, 0x3bc2, &mmUVD_SEMA_CMD[0], sizeof(mmUVD_SEMA_CMD)/sizeof(mmUVD_SEMA_CMD[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_CMD", REG_MMIO, 0x3bc3, &mmUVD_GPCOM_VCPU_CMD[0], sizeof(mmUVD_GPCOM_VCPU_CMD)/sizeof(mmUVD_GPCOM_VCPU_CMD[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_DATA0", REG_MMIO, 0x3bc4, &mmUVD_GPCOM_VCPU_DATA0[0], sizeof(mmUVD_GPCOM_VCPU_DATA0)/sizeof(mmUVD_GPCOM_VCPU_DATA0[0]), 0, 0 },
+	{ "mmUVD_GPCOM_VCPU_DATA1", REG_MMIO, 0x3bc5, &mmUVD_GPCOM_VCPU_DATA1[0], sizeof(mmUVD_GPCOM_VCPU_DATA1)/sizeof(mmUVD_GPCOM_VCPU_DATA1[0]), 0, 0 },
+	{ "mmUVD_ENGINE_CNTL", REG_MMIO, 0x3bc6, &mmUVD_ENGINE_CNTL[0], sizeof(mmUVD_ENGINE_CNTL)/sizeof(mmUVD_ENGINE_CNTL[0]), 0, 0 },
+	{ "mmUVD_UDEC_ADDR_CONFIG", REG_MMIO, 0x3bd3, &mmUVD_UDEC_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_ADDR_CONFIG)/sizeof(mmUVD_UDEC_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_UDEC_DB_ADDR_CONFIG", REG_MMIO, 0x3bd4, &mmUVD_UDEC_DB_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DB_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DB_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_UDEC_DBW_ADDR_CONFIG", REG_MMIO, 0x3bd5, &mmUVD_UDEC_DBW_ADDR_CONFIG[0], sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG)/sizeof(mmUVD_UDEC_DBW_ADDR_CONFIG[0]), 0, 0 },
+	{ "mmUVD_SUVD_CGC_GATE", REG_MMIO, 0x3be4, &mmUVD_SUVD_CGC_GATE[0], sizeof(mmUVD_SUVD_CGC_GATE)/sizeof(mmUVD_SUVD_CGC_GATE[0]), 0, 0 },
+	{ "mmUVD_SUVD_CGC_STATUS", REG_MMIO, 0x3be5, &mmUVD_SUVD_CGC_STATUS[0], sizeof(mmUVD_SUVD_CGC_STATUS)/sizeof(mmUVD_SUVD_CGC_STATUS[0]), 0, 0 },
+	{ "mmUVD_SUVD_CGC_CTRL", REG_MMIO, 0x3be6, &mmUVD_SUVD_CGC_CTRL[0], sizeof(mmUVD_SUVD_CGC_CTRL)/sizeof(mmUVD_SUVD_CGC_CTRL[0]), 0, 0 },
+	{ "mmUVD_POWER_STATUS_U", REG_MMIO, 0x3bfd, &mmUVD_POWER_STATUS_U[0], sizeof(mmUVD_POWER_STATUS_U)/sizeof(mmUVD_POWER_STATUS_U[0]), 0, 0 },
+	{ "mmUVD_NO_OP", REG_MMIO, 0x3bff, NULL, 0, 0, 0 },
+	{ "mmUVD_GP_SCRATCH8", REG_MMIO, 0x3c0a, NULL, 0, 0, 0 },
+	{ "mmUVD_GP_SCRATCH9", REG_MMIO, 0x3c0b, NULL, 0, 0, 0 },
+	{ "mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH", REG_MMIO, 0x3c5e, &mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH[0]), 0, 0 },
+	{ "mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW", REG_MMIO, 0x3c5f, &mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH", REG_MMIO, 0x3c66, &mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_IB_64BIT_BAR_LOW", REG_MMIO, 0x3c67, &mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH", REG_MMIO, 0x3c68, &mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[0], sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH)/sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_RB_64BIT_BAR_LOW", REG_MMIO, 0x3c69, &mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[0], sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW)/sizeof(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[0]), 0, 0 },
+	{ "mmUVD_SEMA_CNTL", REG_MMIO, 0x3d00, &mmUVD_SEMA_CNTL[0], sizeof(mmUVD_SEMA_CNTL)/sizeof(mmUVD_SEMA_CNTL[0]), 0, 0 },
+	{ "mmUVD_LMI_EXT40_ADDR", REG_MMIO, 0x3d26, &mmUVD_LMI_EXT40_ADDR[0], sizeof(mmUVD_LMI_EXT40_ADDR)/sizeof(mmUVD_LMI_EXT40_ADDR[0]), 0, 0 },
+	{ "mmUVD_CTX_INDEX", REG_MMIO, 0x3d28, &mmUVD_CTX_INDEX[0], sizeof(mmUVD_CTX_INDEX)/sizeof(mmUVD_CTX_INDEX[0]), 0, 0 },
+	{ "mmUVD_CTX_DATA", REG_MMIO, 0x3d29, &mmUVD_CTX_DATA[0], sizeof(mmUVD_CTX_DATA)/sizeof(mmUVD_CTX_DATA[0]), 0, 0 },
+	{ "mmUVD_CGC_GATE", REG_MMIO, 0x3d2a, &mmUVD_CGC_GATE[0], sizeof(mmUVD_CGC_GATE)/sizeof(mmUVD_CGC_GATE[0]), 0, 0 },
+	{ "mmUVD_CGC_STATUS", REG_MMIO, 0x3d2b, &mmUVD_CGC_STATUS[0], sizeof(mmUVD_CGC_STATUS)/sizeof(mmUVD_CGC_STATUS[0]), 0, 0 },
+	{ "mmUVD_CGC_CTRL", REG_MMIO, 0x3d2c, &mmUVD_CGC_CTRL[0], sizeof(mmUVD_CGC_CTRL)/sizeof(mmUVD_CGC_CTRL[0]), 0, 0 },
+	{ "mmUVD_CGC_UDEC_STATUS", REG_MMIO, 0x3d2d, &mmUVD_CGC_UDEC_STATUS[0], sizeof(mmUVD_CGC_UDEC_STATUS)/sizeof(mmUVD_CGC_UDEC_STATUS[0]), 0, 0 },
+	{ "mmUVD_GP_SCRATCH4", REG_MMIO, 0x3d38, NULL, 0, 0, 0 },
+	{ "mmUVD_LMI_CTRL2", REG_MMIO, 0x3d3d, &mmUVD_LMI_CTRL2[0], sizeof(mmUVD_LMI_CTRL2)/sizeof(mmUVD_LMI_CTRL2[0]), 0, 0 },
+	{ "mmUVD_MASTINT_EN", REG_MMIO, 0x3d40, &mmUVD_MASTINT_EN[0], sizeof(mmUVD_MASTINT_EN)/sizeof(mmUVD_MASTINT_EN[0]), 0, 0 },
+	{ "mmUVD_LMI_ADDR_EXT", REG_MMIO, 0x3d65, &mmUVD_LMI_ADDR_EXT[0], sizeof(mmUVD_LMI_ADDR_EXT)/sizeof(mmUVD_LMI_ADDR_EXT[0]), 0, 0 },
+	{ "mmUVD_LMI_CTRL", REG_MMIO, 0x3d66, &mmUVD_LMI_CTRL[0], sizeof(mmUVD_LMI_CTRL)/sizeof(mmUVD_LMI_CTRL[0]), 0, 0 },
+	{ "mmUVD_LMI_STATUS", REG_MMIO, 0x3d67, &mmUVD_LMI_STATUS[0], sizeof(mmUVD_LMI_STATUS)/sizeof(mmUVD_LMI_STATUS[0]), 0, 0 },
+	{ "mmUVD_LMI_SWAP_CNTL", REG_MMIO, 0x3d6d, &mmUVD_LMI_SWAP_CNTL[0], sizeof(mmUVD_LMI_SWAP_CNTL)/sizeof(mmUVD_LMI_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUVD_MP_SWAP_CNTL", REG_MMIO, 0x3d6f, &mmUVD_MP_SWAP_CNTL[0], sizeof(mmUVD_MP_SWAP_CNTL)/sizeof(mmUVD_MP_SWAP_CNTL[0]), 0, 0 },
+	{ "mmUVD_MPC_CNTL", REG_MMIO, 0x3d77, &mmUVD_MPC_CNTL[0], sizeof(mmUVD_MPC_CNTL)/sizeof(mmUVD_MPC_CNTL[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXA0", REG_MMIO, 0x3d79, &mmUVD_MPC_SET_MUXA0[0], sizeof(mmUVD_MPC_SET_MUXA0)/sizeof(mmUVD_MPC_SET_MUXA0[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXA1", REG_MMIO, 0x3d7a, &mmUVD_MPC_SET_MUXA1[0], sizeof(mmUVD_MPC_SET_MUXA1)/sizeof(mmUVD_MPC_SET_MUXA1[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXB0", REG_MMIO, 0x3d7b, &mmUVD_MPC_SET_MUXB0[0], sizeof(mmUVD_MPC_SET_MUXB0)/sizeof(mmUVD_MPC_SET_MUXB0[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUXB1", REG_MMIO, 0x3d7c, &mmUVD_MPC_SET_MUXB1[0], sizeof(mmUVD_MPC_SET_MUXB1)/sizeof(mmUVD_MPC_SET_MUXB1[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_MUX", REG_MMIO, 0x3d7d, &mmUVD_MPC_SET_MUX[0], sizeof(mmUVD_MPC_SET_MUX)/sizeof(mmUVD_MPC_SET_MUX[0]), 0, 0 },
+	{ "mmUVD_MPC_SET_ALU", REG_MMIO, 0x3d7e, &mmUVD_MPC_SET_ALU[0], sizeof(mmUVD_MPC_SET_ALU)/sizeof(mmUVD_MPC_SET_ALU[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET0", REG_MMIO, 0x3d82, &mmUVD_VCPU_CACHE_OFFSET0[0], sizeof(mmUVD_VCPU_CACHE_OFFSET0)/sizeof(mmUVD_VCPU_CACHE_OFFSET0[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE0", REG_MMIO, 0x3d83, &mmUVD_VCPU_CACHE_SIZE0[0], sizeof(mmUVD_VCPU_CACHE_SIZE0)/sizeof(mmUVD_VCPU_CACHE_SIZE0[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET1", REG_MMIO, 0x3d84, &mmUVD_VCPU_CACHE_OFFSET1[0], sizeof(mmUVD_VCPU_CACHE_OFFSET1)/sizeof(mmUVD_VCPU_CACHE_OFFSET1[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE1", REG_MMIO, 0x3d85, &mmUVD_VCPU_CACHE_SIZE1[0], sizeof(mmUVD_VCPU_CACHE_SIZE1)/sizeof(mmUVD_VCPU_CACHE_SIZE1[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_OFFSET2", REG_MMIO, 0x3d86, &mmUVD_VCPU_CACHE_OFFSET2[0], sizeof(mmUVD_VCPU_CACHE_OFFSET2)/sizeof(mmUVD_VCPU_CACHE_OFFSET2[0]), 0, 0 },
+	{ "mmUVD_VCPU_CACHE_SIZE2", REG_MMIO, 0x3d87, &mmUVD_VCPU_CACHE_SIZE2[0], sizeof(mmUVD_VCPU_CACHE_SIZE2)/sizeof(mmUVD_VCPU_CACHE_SIZE2[0]), 0, 0 },
+	{ "mmUVD_VCPU_CNTL", REG_MMIO, 0x3d98, &mmUVD_VCPU_CNTL[0], sizeof(mmUVD_VCPU_CNTL)/sizeof(mmUVD_VCPU_CNTL[0]), 0, 0 },
+	{ "mmUVD_SOFT_RESET", REG_MMIO, 0x3da0, &mmUVD_SOFT_RESET[0], sizeof(mmUVD_SOFT_RESET)/sizeof(mmUVD_SOFT_RESET[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_IB_VMID", REG_MMIO, 0x3da1, &mmUVD_LMI_RBC_IB_VMID[0], sizeof(mmUVD_LMI_RBC_IB_VMID)/sizeof(mmUVD_LMI_RBC_IB_VMID[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_SIZE", REG_MMIO, 0x3da2, &mmUVD_RBC_IB_SIZE[0], sizeof(mmUVD_RBC_IB_SIZE)/sizeof(mmUVD_RBC_IB_SIZE[0]), 0, 0 },
+	{ "mmUVD_LMI_RBC_RB_VMID", REG_MMIO, 0x3da3, &mmUVD_LMI_RBC_RB_VMID[0], sizeof(mmUVD_LMI_RBC_RB_VMID)/sizeof(mmUVD_LMI_RBC_RB_VMID[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_RPTR", REG_MMIO, 0x3da4, &mmUVD_RBC_RB_RPTR[0], sizeof(mmUVD_RBC_RB_RPTR)/sizeof(mmUVD_RBC_RB_RPTR[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_WPTR", REG_MMIO, 0x3da5, &mmUVD_RBC_RB_WPTR[0], sizeof(mmUVD_RBC_RB_WPTR)/sizeof(mmUVD_RBC_RB_WPTR[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_WPTR_CNTL", REG_MMIO, 0x3da6, NULL, 0, 0, 0 },
+	{ "mmUVD_RBC_RB_CNTL", REG_MMIO, 0x3da9, &mmUVD_RBC_RB_CNTL[0], sizeof(mmUVD_RBC_RB_CNTL)/sizeof(mmUVD_RBC_RB_CNTL[0]), 0, 0 },
+	{ "mmUVD_RBC_RB_RPTR_ADDR", REG_MMIO, 0x3daa, &mmUVD_RBC_RB_RPTR_ADDR[0], sizeof(mmUVD_RBC_RB_RPTR_ADDR)/sizeof(mmUVD_RBC_RB_RPTR_ADDR[0]), 0, 0 },
+	{ "mmUVD_STATUS", REG_MMIO, 0x3daf, &mmUVD_STATUS[0], sizeof(mmUVD_STATUS)/sizeof(mmUVD_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_TIMEOUT_STATUS", REG_MMIO, 0x3db0, &mmUVD_SEMA_TIMEOUT_STATUS[0], sizeof(mmUVD_SEMA_TIMEOUT_STATUS)/sizeof(mmUVD_SEMA_TIMEOUT_STATUS[0]), 0, 0 },
+	{ "mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3db1, &mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL", REG_MMIO, 0x3db2, &mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL", REG_MMIO, 0x3db3, &mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0], sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL)/sizeof(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL[0]), 0, 0 },
+	{ "mmUVD_CONTEXT_ID", REG_MMIO, 0x3dbd, &mmUVD_CONTEXT_ID[0], sizeof(mmUVD_CONTEXT_ID)/sizeof(mmUVD_CONTEXT_ID[0]), 0, 0 },
+	{ "mmUVD_RBC_IB_SIZE_UPDATE", REG_MMIO, 0x3df1, NULL, 0, 0, 0 },
+	{ "ixUVD_MIF_SCLR_ADDR_CONFIG", REG_SMC, 0x4, &ixUVD_MIF_SCLR_ADDR_CONFIG[0], sizeof(ixUVD_MIF_SCLR_ADDR_CONFIG)/sizeof(ixUVD_MIF_SCLR_ADDR_CONFIG[0]), 0, 0 },
+	{ "ixUVD_LMI_VMID_INTERNAL", REG_SMC, 0x99, &ixUVD_LMI_VMID_INTERNAL[0], sizeof(ixUVD_LMI_VMID_INTERNAL)/sizeof(ixUVD_LMI_VMID_INTERNAL[0]), 0, 0 },
+	{ "ixUVD_LMI_VMID_INTERNAL2", REG_SMC, 0x9a, &ixUVD_LMI_VMID_INTERNAL2[0], sizeof(ixUVD_LMI_VMID_INTERNAL2)/sizeof(ixUVD_LMI_VMID_INTERNAL2[0]), 0, 0 },
+	{ "ixUVD_LMI_CACHE_CTRL", REG_SMC, 0x9b, &ixUVD_LMI_CACHE_CTRL[0], sizeof(ixUVD_LMI_CACHE_CTRL)/sizeof(ixUVD_LMI_CACHE_CTRL[0]), 0, 0 },
+	{ "ixUVD_LMI_SWAP_CNTL2", REG_SMC, 0xaa, &ixUVD_LMI_SWAP_CNTL2[0], sizeof(ixUVD_LMI_SWAP_CNTL2)/sizeof(ixUVD_LMI_SWAP_CNTL2[0]), 0, 0 },
+	{ "ixUVD_LMI_ADDR_EXT2", REG_SMC, 0xab, &ixUVD_LMI_ADDR_EXT2[0], sizeof(ixUVD_LMI_ADDR_EXT2)/sizeof(ixUVD_LMI_ADDR_EXT2[0]), 0, 0 },
+	{ "ixUVD_CGC_MEM_CTRL", REG_SMC, 0xc0, &ixUVD_CGC_MEM_CTRL[0], sizeof(ixUVD_CGC_MEM_CTRL)/sizeof(ixUVD_CGC_MEM_CTRL[0]), 0, 0 },
+	{ "ixUVD_CGC_CTRL2", REG_SMC, 0xc1, &ixUVD_CGC_CTRL2[0], sizeof(ixUVD_CGC_CTRL2)/sizeof(ixUVD_CGC_CTRL2[0]), 0, 0 },
diff --git a/src/lib/ip/vce1.c b/src/lib/ip/vce1.c
new file mode 100644
index 0000000..897f44b
--- /dev/null
+++ b/src/lib/ip/vce1.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "vce10_bits.i"
+
+static const struct umr_reg vce1_registers[] = {
+#include "vce10_regs.i"
+};
+
+struct umr_ip_block *umr_create_vce1(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "vce1";
+	ip->no_regs = sizeof(vce1_registers)/sizeof(vce1_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(vce1_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, vce1_registers, sizeof(vce1_registers));
+	return ip;
+}
diff --git a/src/lib/ip/vce10_bits.i b/src/lib/ip/vce10_bits.i
new file mode 100644
index 0000000..a8d72d7
--- /dev/null
+++ b/src/lib/ip/vce10_bits.i
@@ -0,0 +1,91 @@
+static struct umr_bitfield mmVCE_STATUS[] = {
+	 { "JOB_BUSY", 0, 0, &umr_bitfield_default },
+	 { "UENC_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VCPU_REPORT", 1, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CNTL[] = {
+	 { "CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "RBBM_SOFT_RESET", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET0[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE0[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET1[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE1[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET2[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE2[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SOFT_RESET[] = {
+	 { "ECPU_SOFT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_LO2[] = {
+	 { "RB_BASE_LO", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_HI2[] = {
+	 { "RB_BASE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_SIZE2[] = {
+	 { "RB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_RPTR2[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_WPTR2[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_LO[] = {
+	 { "RB_BASE_LO", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_SIZE[] = {
+	 { "RB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_RPTR[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_WPTR[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_UENC_DMA_DCLK_CTRL[] = {
+	 { "RDDMCLK_FORCEON", 1, 1, &umr_bitfield_default },
+	 { "REGCLK_FORCEON", 2, 2, &umr_bitfield_default },
+	 { "WRDMCLK_FORCEON", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SYS_INT_EN[] = {
+	 { "VCE_SYS_INT_TRAP_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SYS_INT_ACK[] = {
+	 { "VCE_SYS_INT_TRAP_INTERRUPT_ACK", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_VCPU_CACHE_40BIT_BAR[] = {
+	 { "BAR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CTRL2[] = {
+	 { "STALL_ARB_UMC", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CTRL[] = {
+	 { "VCPU_DATA_COHERENCY_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL[] = {
+	 { "VCPU_W_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "WR_MC_CID_SWAP", 2, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL1[] = {
+	 { "RD_MC_CID_SWAP", 2, 13, &umr_bitfield_default },
+	 { "VCPU_R_MC_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CACHE_CTRL[] = {
+	 { "VCPU_EN", 0, 0, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/vce10_regs.i b/src/lib/ip/vce10_regs.i
new file mode 100644
index 0000000..8ec2958
--- /dev/null
+++ b/src/lib/ip/vce10_regs.i
@@ -0,0 +1,36 @@
+	{ "mmVCE_STATUS", REG_MMIO, 0x8001, &mmVCE_STATUS[0], sizeof(mmVCE_STATUS)/sizeof(mmVCE_STATUS[0]), 0, 0 },
+	{ "mmVCE_VCPU_CNTL", REG_MMIO, 0x8005, &mmVCE_VCPU_CNTL[0], sizeof(mmVCE_VCPU_CNTL)/sizeof(mmVCE_VCPU_CNTL[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET0", REG_MMIO, 0x8009, &mmVCE_VCPU_CACHE_OFFSET0[0], sizeof(mmVCE_VCPU_CACHE_OFFSET0)/sizeof(mmVCE_VCPU_CACHE_OFFSET0[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE0", REG_MMIO, 0x800A, &mmVCE_VCPU_CACHE_SIZE0[0], sizeof(mmVCE_VCPU_CACHE_SIZE0)/sizeof(mmVCE_VCPU_CACHE_SIZE0[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET1", REG_MMIO, 0x800B, &mmVCE_VCPU_CACHE_OFFSET1[0], sizeof(mmVCE_VCPU_CACHE_OFFSET1)/sizeof(mmVCE_VCPU_CACHE_OFFSET1[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE1", REG_MMIO, 0x800C, &mmVCE_VCPU_CACHE_SIZE1[0], sizeof(mmVCE_VCPU_CACHE_SIZE1)/sizeof(mmVCE_VCPU_CACHE_SIZE1[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET2", REG_MMIO, 0x800D, &mmVCE_VCPU_CACHE_OFFSET2[0], sizeof(mmVCE_VCPU_CACHE_OFFSET2)/sizeof(mmVCE_VCPU_CACHE_OFFSET2[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE2", REG_MMIO, 0x800E, &mmVCE_VCPU_CACHE_SIZE2[0], sizeof(mmVCE_VCPU_CACHE_SIZE2)/sizeof(mmVCE_VCPU_CACHE_SIZE2[0]), 0, 0 },
+	{ "mmVCE_SOFT_RESET", REG_MMIO, 0x8048, &mmVCE_SOFT_RESET[0], sizeof(mmVCE_SOFT_RESET)/sizeof(mmVCE_SOFT_RESET[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_LO2", REG_MMIO, 0x805B, &mmVCE_RB_BASE_LO2[0], sizeof(mmVCE_RB_BASE_LO2)/sizeof(mmVCE_RB_BASE_LO2[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_HI2", REG_MMIO, 0x805C, &mmVCE_RB_BASE_HI2[0], sizeof(mmVCE_RB_BASE_HI2)/sizeof(mmVCE_RB_BASE_HI2[0]), 0, 0 },
+	{ "mmVCE_RB_SIZE2", REG_MMIO, 0x805D, &mmVCE_RB_SIZE2[0], sizeof(mmVCE_RB_SIZE2)/sizeof(mmVCE_RB_SIZE2[0]), 0, 0 },
+	{ "mmVCE_RB_RPTR2", REG_MMIO, 0x805E, &mmVCE_RB_RPTR2[0], sizeof(mmVCE_RB_RPTR2)/sizeof(mmVCE_RB_RPTR2[0]), 0, 0 },
+	{ "mmVCE_RB_WPTR2", REG_MMIO, 0x805F, &mmVCE_RB_WPTR2[0], sizeof(mmVCE_RB_WPTR2)/sizeof(mmVCE_RB_WPTR2[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_LO", REG_MMIO, 0x8060, &mmVCE_RB_BASE_LO[0], sizeof(mmVCE_RB_BASE_LO)/sizeof(mmVCE_RB_BASE_LO[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_HI", REG_MMIO, 0x8061, &mmVCE_RB_BASE_HI[0], sizeof(mmVCE_RB_BASE_HI)/sizeof(mmVCE_RB_BASE_HI[0]), 0, 0 },
+	{ "mmVCE_RB_SIZE", REG_MMIO, 0x8062, &mmVCE_RB_SIZE[0], sizeof(mmVCE_RB_SIZE)/sizeof(mmVCE_RB_SIZE[0]), 0, 0 },
+	{ "mmVCE_RB_RPTR", REG_MMIO, 0x8063, &mmVCE_RB_RPTR[0], sizeof(mmVCE_RB_RPTR)/sizeof(mmVCE_RB_RPTR[0]), 0, 0 },
+	{ "mmVCE_RB_WPTR", REG_MMIO, 0x8064, &mmVCE_RB_WPTR[0], sizeof(mmVCE_RB_WPTR)/sizeof(mmVCE_RB_WPTR[0]), 0, 0 },
+	{ "mmVCE_RB_ARB_CTRL", REG_MMIO, 0x809F, NULL, 0, 0, 0 },
+	{ "mmVCE_CLOCK_GATING_A", REG_MMIO, 0x80BE, NULL, 0, 0, 0 },
+	{ "mmVCE_CLOCK_GATING_B", REG_MMIO, 0x80BF, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_CLOCK_GATING", REG_MMIO, 0x816F, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_REG_CLOCK_GATING", REG_MMIO, 0x8170, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_DMA_DCLK_CTRL", REG_MMIO, 0x8250, &mmVCE_UENC_DMA_DCLK_CTRL[0], sizeof(mmVCE_UENC_DMA_DCLK_CTRL)/sizeof(mmVCE_UENC_DMA_DCLK_CTRL[0]), 0, 0 },
+	{ "mmVCE_SYS_INT_EN", REG_MMIO, 0x8340, &mmVCE_SYS_INT_EN[0], sizeof(mmVCE_SYS_INT_EN)/sizeof(mmVCE_SYS_INT_EN[0]), 0, 0 },
+	{ "mmVCE_SYS_INT_ACK", REG_MMIO, 0x8341, &mmVCE_SYS_INT_ACK[0], sizeof(mmVCE_SYS_INT_ACK)/sizeof(mmVCE_SYS_INT_ACK[0]), 0, 0 },
+	{ "mmVCE_LMI_VCPU_CACHE_40BIT_BAR", REG_MMIO, 0x8397, &mmVCE_LMI_VCPU_CACHE_40BIT_BAR[0], sizeof(mmVCE_LMI_VCPU_CACHE_40BIT_BAR)/sizeof(mmVCE_LMI_VCPU_CACHE_40BIT_BAR[0]), 0, 0 },
+	{ "mmVCE_LMI_CTRL2", REG_MMIO, 0x839D, &mmVCE_LMI_CTRL2[0], sizeof(mmVCE_LMI_CTRL2)/sizeof(mmVCE_LMI_CTRL2[0]), 0, 0 },
+	{ "mmVCE_LMI_CTRL", REG_MMIO, 0x83A6, &mmVCE_LMI_CTRL[0], sizeof(mmVCE_LMI_CTRL)/sizeof(mmVCE_LMI_CTRL[0]), 0, 0 },
+	{ "mmVCE_LMI_STATUS", REG_MMIO, 0x83A7, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_VM_CTRL", REG_MMIO, 0x83A8, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL", REG_MMIO, 0x83AD, &mmVCE_LMI_SWAP_CNTL[0], sizeof(mmVCE_LMI_SWAP_CNTL)/sizeof(mmVCE_LMI_SWAP_CNTL[0]), 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL1", REG_MMIO, 0x83AE, &mmVCE_LMI_SWAP_CNTL1[0], sizeof(mmVCE_LMI_SWAP_CNTL1)/sizeof(mmVCE_LMI_SWAP_CNTL1[0]), 0, 0 },
+	{ "mmVCE_LMI_MISC_CTRL", REG_MMIO, 0x83B5, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_CACHE_CTRL", REG_MMIO, 0x83BD, &mmVCE_LMI_CACHE_CTRL[0], sizeof(mmVCE_LMI_CACHE_CTRL)/sizeof(mmVCE_LMI_CACHE_CTRL[0]), 0, 0 },
diff --git a/src/lib/ip/vce2.c b/src/lib/ip/vce2.c
new file mode 100644
index 0000000..2e6f7ac
--- /dev/null
+++ b/src/lib/ip/vce2.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "vce20_bits.i"
+
+static const struct umr_reg vce2_registers[] = {
+#include "vce20_regs.i"
+};
+
+struct umr_ip_block *umr_create_vce2(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "vce2";
+	ip->no_regs = sizeof(vce2_registers)/sizeof(vce2_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(vce2_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, vce2_registers, sizeof(vce2_registers));
+	return ip;
+}
diff --git a/src/lib/ip/vce20_bits.i b/src/lib/ip/vce20_bits.i
new file mode 100644
index 0000000..c213230
--- /dev/null
+++ b/src/lib/ip/vce20_bits.i
@@ -0,0 +1,100 @@
+static struct umr_bitfield mmVCE_STATUS[] = {
+	 { "JOB_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VCPU_REPORT", 1, 7, &umr_bitfield_default },
+	 { "UENC_BUSY", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CNTL[] = {
+	 { "CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "RBBM_SOFT_RESET", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET0[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE0[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET1[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE1[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET2[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE2[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SOFT_RESET[] = {
+	 { "ECPU_SOFT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_LO2[] = {
+	 { "RB_BASE_LO", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_HI2[] = {
+	 { "RB_BASE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_SIZE2[] = {
+	 { "RB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_RPTR2[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_WPTR2[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_LO[] = {
+	 { "RB_BASE_LO", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_SIZE[] = {
+	 { "RB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_RPTR[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_WPTR[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_UENC_DMA_DCLK_CTRL[] = {
+	 { "WRDMCLK_FORCEON", 0, 0, &umr_bitfield_default },
+	 { "RDDMCLK_FORCEON", 1, 1, &umr_bitfield_default },
+	 { "REGCLK_FORCEON", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SYS_INT_EN[] = {
+	 { "VCE_SYS_INT_TRAP_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SYS_INT_STATUS[] = {
+	 { "VCE_SYS_INT_TRAP_INTERRUPT_INT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SYS_INT_ACK[] = {
+	 { "VCE_SYS_INT_TRAP_INTERRUPT_ACK", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_VCPU_CACHE_40BIT_BAR[] = {
+	 { "BAR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CTRL2[] = {
+	 { "STALL_ARB_UMC", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL3[] = {
+	 { "RD_MC_CID_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CTRL[] = {
+	 { "VCPU_DATA_COHERENCY_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL[] = {
+	 { "VCPU_W_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "WR_MC_CID_SWAP", 2, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL1[] = {
+	 { "VCPU_R_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RD_MC_CID_SWAP", 2, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL2[] = {
+	 { "WR_MC_CID_SWAP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CACHE_CTRL[] = {
+	 { "VCPU_EN", 0, 0, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/vce20_regs.i b/src/lib/ip/vce20_regs.i
new file mode 100644
index 0000000..508739f
--- /dev/null
+++ b/src/lib/ip/vce20_regs.i
@@ -0,0 +1,40 @@
+	{ "mmVCE_STATUS", REG_MMIO, 0x8001, &mmVCE_STATUS[0], sizeof(mmVCE_STATUS)/sizeof(mmVCE_STATUS[0]), 0, 0 },
+	{ "mmVCE_VCPU_CNTL", REG_MMIO, 0x8005, &mmVCE_VCPU_CNTL[0], sizeof(mmVCE_VCPU_CNTL)/sizeof(mmVCE_VCPU_CNTL[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET0", REG_MMIO, 0x8009, &mmVCE_VCPU_CACHE_OFFSET0[0], sizeof(mmVCE_VCPU_CACHE_OFFSET0)/sizeof(mmVCE_VCPU_CACHE_OFFSET0[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE0", REG_MMIO, 0x800a, &mmVCE_VCPU_CACHE_SIZE0[0], sizeof(mmVCE_VCPU_CACHE_SIZE0)/sizeof(mmVCE_VCPU_CACHE_SIZE0[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET1", REG_MMIO, 0x800b, &mmVCE_VCPU_CACHE_OFFSET1[0], sizeof(mmVCE_VCPU_CACHE_OFFSET1)/sizeof(mmVCE_VCPU_CACHE_OFFSET1[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE1", REG_MMIO, 0x800c, &mmVCE_VCPU_CACHE_SIZE1[0], sizeof(mmVCE_VCPU_CACHE_SIZE1)/sizeof(mmVCE_VCPU_CACHE_SIZE1[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET2", REG_MMIO, 0x800d, &mmVCE_VCPU_CACHE_OFFSET2[0], sizeof(mmVCE_VCPU_CACHE_OFFSET2)/sizeof(mmVCE_VCPU_CACHE_OFFSET2[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE2", REG_MMIO, 0x800e, &mmVCE_VCPU_CACHE_SIZE2[0], sizeof(mmVCE_VCPU_CACHE_SIZE2)/sizeof(mmVCE_VCPU_CACHE_SIZE2[0]), 0, 0 },
+	{ "mmVCE_SOFT_RESET", REG_MMIO, 0x8048, &mmVCE_SOFT_RESET[0], sizeof(mmVCE_SOFT_RESET)/sizeof(mmVCE_SOFT_RESET[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_LO2", REG_MMIO, 0x805b, &mmVCE_RB_BASE_LO2[0], sizeof(mmVCE_RB_BASE_LO2)/sizeof(mmVCE_RB_BASE_LO2[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_HI2", REG_MMIO, 0x805c, &mmVCE_RB_BASE_HI2[0], sizeof(mmVCE_RB_BASE_HI2)/sizeof(mmVCE_RB_BASE_HI2[0]), 0, 0 },
+	{ "mmVCE_RB_SIZE2", REG_MMIO, 0x805d, &mmVCE_RB_SIZE2[0], sizeof(mmVCE_RB_SIZE2)/sizeof(mmVCE_RB_SIZE2[0]), 0, 0 },
+	{ "mmVCE_RB_RPTR2", REG_MMIO, 0x805e, &mmVCE_RB_RPTR2[0], sizeof(mmVCE_RB_RPTR2)/sizeof(mmVCE_RB_RPTR2[0]), 0, 0 },
+	{ "mmVCE_RB_WPTR2", REG_MMIO, 0x805f, &mmVCE_RB_WPTR2[0], sizeof(mmVCE_RB_WPTR2)/sizeof(mmVCE_RB_WPTR2[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_LO", REG_MMIO, 0x8060, &mmVCE_RB_BASE_LO[0], sizeof(mmVCE_RB_BASE_LO)/sizeof(mmVCE_RB_BASE_LO[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_HI", REG_MMIO, 0x8061, &mmVCE_RB_BASE_HI[0], sizeof(mmVCE_RB_BASE_HI)/sizeof(mmVCE_RB_BASE_HI[0]), 0, 0 },
+	{ "mmVCE_RB_SIZE", REG_MMIO, 0x8062, &mmVCE_RB_SIZE[0], sizeof(mmVCE_RB_SIZE)/sizeof(mmVCE_RB_SIZE[0]), 0, 0 },
+	{ "mmVCE_RB_RPTR", REG_MMIO, 0x8063, &mmVCE_RB_RPTR[0], sizeof(mmVCE_RB_RPTR)/sizeof(mmVCE_RB_RPTR[0]), 0, 0 },
+	{ "mmVCE_RB_WPTR", REG_MMIO, 0x8064, &mmVCE_RB_WPTR[0], sizeof(mmVCE_RB_WPTR)/sizeof(mmVCE_RB_WPTR[0]), 0, 0 },
+	{ "mmVCE_RB_ARB_CTRL", REG_MMIO, 0x809f, NULL, 0, 0, 0 },
+	{ "mmVCE_CLOCK_GATING_A", REG_MMIO, 0x80be, NULL, 0, 0, 0 },
+	{ "mmVCE_CLOCK_GATING_B", REG_MMIO, 0x80bf, NULL, 0, 0, 0 },
+	{ "mmVCE_CGTT_CLK_OVERRIDE", REG_MMIO, 0x81e8, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_CLOCK_GATING", REG_MMIO, 0x81ef, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_REG_CLOCK_GATING", REG_MMIO, 0x81f0, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_DMA_DCLK_CTRL", REG_MMIO, 0x8390, &mmVCE_UENC_DMA_DCLK_CTRL[0], sizeof(mmVCE_UENC_DMA_DCLK_CTRL)/sizeof(mmVCE_UENC_DMA_DCLK_CTRL[0]), 0, 0 },
+	{ "mmVCE_SYS_INT_EN", REG_MMIO, 0x84c0, &mmVCE_SYS_INT_EN[0], sizeof(mmVCE_SYS_INT_EN)/sizeof(mmVCE_SYS_INT_EN[0]), 0, 0 },
+	{ "mmVCE_SYS_INT_STATUS", REG_MMIO, 0x84c1, &mmVCE_SYS_INT_STATUS[0], sizeof(mmVCE_SYS_INT_STATUS)/sizeof(mmVCE_SYS_INT_STATUS[0]), 0, 0 },
+	{ "mmVCE_SYS_INT_ACK", REG_MMIO, 0x84c1, &mmVCE_SYS_INT_ACK[0], sizeof(mmVCE_SYS_INT_ACK)/sizeof(mmVCE_SYS_INT_ACK[0]), 0, 0 },
+	{ "mmVCE_LMI_VCPU_CACHE_40BIT_BAR", REG_MMIO, 0x8517, &mmVCE_LMI_VCPU_CACHE_40BIT_BAR[0], sizeof(mmVCE_LMI_VCPU_CACHE_40BIT_BAR)/sizeof(mmVCE_LMI_VCPU_CACHE_40BIT_BAR[0]), 0, 0 },
+	{ "mmVCE_LMI_CTRL2", REG_MMIO, 0x851d, &mmVCE_LMI_CTRL2[0], sizeof(mmVCE_LMI_CTRL2)/sizeof(mmVCE_LMI_CTRL2[0]), 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL3", REG_MMIO, 0x851e, &mmVCE_LMI_SWAP_CNTL3[0], sizeof(mmVCE_LMI_SWAP_CNTL3)/sizeof(mmVCE_LMI_SWAP_CNTL3[0]), 0, 0 },
+	{ "mmVCE_LMI_CTRL", REG_MMIO, 0x8526, &mmVCE_LMI_CTRL[0], sizeof(mmVCE_LMI_CTRL)/sizeof(mmVCE_LMI_CTRL[0]), 0, 0 },
+	{ "mmVCE_LMI_STATUS", REG_MMIO, 0x8527, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_VM_CTRL", REG_MMIO, 0x8528, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL", REG_MMIO, 0x852d, &mmVCE_LMI_SWAP_CNTL[0], sizeof(mmVCE_LMI_SWAP_CNTL)/sizeof(mmVCE_LMI_SWAP_CNTL[0]), 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL1", REG_MMIO, 0x852e, &mmVCE_LMI_SWAP_CNTL1[0], sizeof(mmVCE_LMI_SWAP_CNTL1)/sizeof(mmVCE_LMI_SWAP_CNTL1[0]), 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL2", REG_MMIO, 0x8533, &mmVCE_LMI_SWAP_CNTL2[0], sizeof(mmVCE_LMI_SWAP_CNTL2)/sizeof(mmVCE_LMI_SWAP_CNTL2[0]), 0, 0 },
+	{ "mmVCE_LMI_MISC_CTRL", REG_MMIO, 0x8535, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_CACHE_CTRL", REG_MMIO, 0x853d, &mmVCE_LMI_CACHE_CTRL[0], sizeof(mmVCE_LMI_CACHE_CTRL)/sizeof(mmVCE_LMI_CACHE_CTRL[0]), 0, 0 },
diff --git a/src/lib/ip/vce3.c b/src/lib/ip/vce3.c
new file mode 100644
index 0000000..3e304d1
--- /dev/null
+++ b/src/lib/ip/vce3.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+#include "vce30_bits.i"
+
+static const struct umr_reg vce3_registers[] = {
+#include "vce30_regs.i"
+};
+
+struct umr_ip_block *umr_create_vce3(struct umr_options *options)
+{
+	struct umr_ip_block *ip;
+
+	(void)options;
+
+	ip = calloc(1, sizeof *ip);
+	if (!ip)
+		return NULL;
+
+	ip->ipname = "vce3";
+	ip->no_regs = sizeof(vce3_registers)/sizeof(vce3_registers[0]);
+	ip->regs = calloc(ip->no_regs, sizeof(vce3_registers[0]));
+	if (!ip->regs) {
+		free(ip);
+		return NULL;
+	}
+	memcpy(ip->regs, vce3_registers, sizeof(vce3_registers));
+	return ip;
+}
diff --git a/src/lib/ip/vce30_bits.i b/src/lib/ip/vce30_bits.i
new file mode 100644
index 0000000..5a92b84
--- /dev/null
+++ b/src/lib/ip/vce30_bits.i
@@ -0,0 +1,120 @@
+static struct umr_bitfield mmVCE_STATUS[] = {
+	 { "JOB_BUSY", 0, 0, &umr_bitfield_default },
+	 { "VCPU_REPORT", 1, 7, &umr_bitfield_default },
+	 { "UENC_BUSY", 8, 8, &umr_bitfield_default },
+	 { "VCE_CONFIGURATION", 22, 23, &umr_bitfield_default },
+	 { "VCE_INSTANCE_ID", 24, 25, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CNTL[] = {
+	 { "CLK_EN", 0, 0, &umr_bitfield_default },
+	 { "RBBM_SOFT_RESET", 18, 18, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET0[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE0[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET1[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE1[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_OFFSET2[] = {
+	 { "OFFSET", 0, 27, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_VCPU_CACHE_SIZE2[] = {
+	 { "SIZE", 0, 23, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SOFT_RESET[] = {
+	 { "ECPU_SOFT_RESET", 0, 0, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_LO2[] = {
+	 { "RB_BASE_LO", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_HI2[] = {
+	 { "RB_BASE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_SIZE2[] = {
+	 { "RB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_RPTR2[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_WPTR2[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_LO[] = {
+	 { "RB_BASE_LO", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_HI[] = {
+	 { "RB_BASE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_SIZE[] = {
+	 { "RB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_RPTR[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_WPTR[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_ARB_CTRL[] = {
+	 { "VCE_CGTT_OVERRIDE", 16, 16, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_LO3[] = {
+	 { "RB_BASE_LO", 6, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_BASE_HI3[] = {
+	 { "RB_BASE_HI", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_SIZE3[] = {
+	 { "RB_SIZE", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_RPTR3[] = {
+	 { "RB_RPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_RB_WPTR3[] = {
+	 { "RB_WPTR", 4, 22, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_UENC_DMA_DCLK_CTRL[] = {
+	 { "WRDMCLK_FORCEON", 0, 0, &umr_bitfield_default },
+	 { "RDDMCLK_FORCEON", 1, 1, &umr_bitfield_default },
+	 { "REGCLK_FORCEON", 2, 2, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SYS_INT_EN[] = {
+	 { "VCE_SYS_INT_TRAP_INTERRUPT_EN", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SYS_INT_STATUS[] = {
+	 { "VCE_SYS_INT_TRAP_INTERRUPT_INT", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_SYS_INT_ACK[] = {
+	 { "VCE_SYS_INT_TRAP_INTERRUPT_ACK", 3, 3, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_VCPU_CACHE_40BIT_BAR[] = {
+	 { "BAR", 0, 31, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CTRL2[] = {
+	 { "STALL_ARB_UMC", 8, 8, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL3[] = {
+	 { "RD_MC_CID_SWAP", 0, 1, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CTRL[] = {
+	 { "VCPU_DATA_COHERENCY_EN", 21, 21, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL[] = {
+	 { "VCPU_W_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "WR_MC_CID_SWAP", 2, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL1[] = {
+	 { "VCPU_R_MC_SWAP", 0, 1, &umr_bitfield_default },
+	 { "RD_MC_CID_SWAP", 2, 13, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_SWAP_CNTL2[] = {
+	 { "WR_MC_CID_SWAP", 0, 7, &umr_bitfield_default },
+};
+static struct umr_bitfield mmVCE_LMI_CACHE_CTRL[] = {
+	 { "VCPU_EN", 0, 0, &umr_bitfield_default },
+};
diff --git a/src/lib/ip/vce30_regs.i b/src/lib/ip/vce30_regs.i
new file mode 100644
index 0000000..643b008
--- /dev/null
+++ b/src/lib/ip/vce30_regs.i
@@ -0,0 +1,45 @@
+	{ "mmVCE_STATUS", REG_MMIO, 0x8001, &mmVCE_STATUS[0], sizeof(mmVCE_STATUS)/sizeof(mmVCE_STATUS[0]), 0, 0 },
+	{ "mmVCE_VCPU_CNTL", REG_MMIO, 0x8005, &mmVCE_VCPU_CNTL[0], sizeof(mmVCE_VCPU_CNTL)/sizeof(mmVCE_VCPU_CNTL[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET0", REG_MMIO, 0x8009, &mmVCE_VCPU_CACHE_OFFSET0[0], sizeof(mmVCE_VCPU_CACHE_OFFSET0)/sizeof(mmVCE_VCPU_CACHE_OFFSET0[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE0", REG_MMIO, 0x800a, &mmVCE_VCPU_CACHE_SIZE0[0], sizeof(mmVCE_VCPU_CACHE_SIZE0)/sizeof(mmVCE_VCPU_CACHE_SIZE0[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET1", REG_MMIO, 0x800b, &mmVCE_VCPU_CACHE_OFFSET1[0], sizeof(mmVCE_VCPU_CACHE_OFFSET1)/sizeof(mmVCE_VCPU_CACHE_OFFSET1[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE1", REG_MMIO, 0x800c, &mmVCE_VCPU_CACHE_SIZE1[0], sizeof(mmVCE_VCPU_CACHE_SIZE1)/sizeof(mmVCE_VCPU_CACHE_SIZE1[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_OFFSET2", REG_MMIO, 0x800d, &mmVCE_VCPU_CACHE_OFFSET2[0], sizeof(mmVCE_VCPU_CACHE_OFFSET2)/sizeof(mmVCE_VCPU_CACHE_OFFSET2[0]), 0, 0 },
+	{ "mmVCE_VCPU_CACHE_SIZE2", REG_MMIO, 0x800e, &mmVCE_VCPU_CACHE_SIZE2[0], sizeof(mmVCE_VCPU_CACHE_SIZE2)/sizeof(mmVCE_VCPU_CACHE_SIZE2[0]), 0, 0 },
+	{ "mmVCE_SOFT_RESET", REG_MMIO, 0x8048, &mmVCE_SOFT_RESET[0], sizeof(mmVCE_SOFT_RESET)/sizeof(mmVCE_SOFT_RESET[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_LO2", REG_MMIO, 0x805b, &mmVCE_RB_BASE_LO2[0], sizeof(mmVCE_RB_BASE_LO2)/sizeof(mmVCE_RB_BASE_LO2[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_HI2", REG_MMIO, 0x805c, &mmVCE_RB_BASE_HI2[0], sizeof(mmVCE_RB_BASE_HI2)/sizeof(mmVCE_RB_BASE_HI2[0]), 0, 0 },
+	{ "mmVCE_RB_SIZE2", REG_MMIO, 0x805d, &mmVCE_RB_SIZE2[0], sizeof(mmVCE_RB_SIZE2)/sizeof(mmVCE_RB_SIZE2[0]), 0, 0 },
+	{ "mmVCE_RB_RPTR2", REG_MMIO, 0x805e, &mmVCE_RB_RPTR2[0], sizeof(mmVCE_RB_RPTR2)/sizeof(mmVCE_RB_RPTR2[0]), 0, 0 },
+	{ "mmVCE_RB_WPTR2", REG_MMIO, 0x805f, &mmVCE_RB_WPTR2[0], sizeof(mmVCE_RB_WPTR2)/sizeof(mmVCE_RB_WPTR2[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_LO", REG_MMIO, 0x8060, &mmVCE_RB_BASE_LO[0], sizeof(mmVCE_RB_BASE_LO)/sizeof(mmVCE_RB_BASE_LO[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_HI", REG_MMIO, 0x8061, &mmVCE_RB_BASE_HI[0], sizeof(mmVCE_RB_BASE_HI)/sizeof(mmVCE_RB_BASE_HI[0]), 0, 0 },
+	{ "mmVCE_RB_SIZE", REG_MMIO, 0x8062, &mmVCE_RB_SIZE[0], sizeof(mmVCE_RB_SIZE)/sizeof(mmVCE_RB_SIZE[0]), 0, 0 },
+	{ "mmVCE_RB_RPTR", REG_MMIO, 0x8063, &mmVCE_RB_RPTR[0], sizeof(mmVCE_RB_RPTR)/sizeof(mmVCE_RB_RPTR[0]), 0, 0 },
+	{ "mmVCE_RB_WPTR", REG_MMIO, 0x8064, &mmVCE_RB_WPTR[0], sizeof(mmVCE_RB_WPTR)/sizeof(mmVCE_RB_WPTR[0]), 0, 0 },
+	{ "mmVCE_RB_ARB_CTRL", REG_MMIO, 0x809f, &mmVCE_RB_ARB_CTRL[0], sizeof(mmVCE_RB_ARB_CTRL)/sizeof(mmVCE_RB_ARB_CTRL[0]), 0, 0 },
+	{ "mmVCE_CLOCK_GATING_A", REG_MMIO, 0x80be, NULL, 0, 0, 0 },
+	{ "mmVCE_CLOCK_GATING_B", REG_MMIO, 0x80bf, NULL, 0, 0, 0 },
+	{ "mmVCE_RB_BASE_LO3", REG_MMIO, 0x80d4, &mmVCE_RB_BASE_LO3[0], sizeof(mmVCE_RB_BASE_LO3)/sizeof(mmVCE_RB_BASE_LO3[0]), 0, 0 },
+	{ "mmVCE_RB_BASE_HI3", REG_MMIO, 0x80d5, &mmVCE_RB_BASE_HI3[0], sizeof(mmVCE_RB_BASE_HI3)/sizeof(mmVCE_RB_BASE_HI3[0]), 0, 0 },
+	{ "mmVCE_RB_SIZE3", REG_MMIO, 0x80d6, &mmVCE_RB_SIZE3[0], sizeof(mmVCE_RB_SIZE3)/sizeof(mmVCE_RB_SIZE3[0]), 0, 0 },
+	{ "mmVCE_RB_RPTR3", REG_MMIO, 0x80d7, &mmVCE_RB_RPTR3[0], sizeof(mmVCE_RB_RPTR3)/sizeof(mmVCE_RB_RPTR3[0]), 0, 0 },
+	{ "mmVCE_RB_WPTR3", REG_MMIO, 0x80d8, &mmVCE_RB_WPTR3[0], sizeof(mmVCE_RB_WPTR3)/sizeof(mmVCE_RB_WPTR3[0]), 0, 0 },
+	{ "mmVCE_UENC_CLOCK_GATING", REG_MMIO, 0x81ef, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_REG_CLOCK_GATING", REG_MMIO, 0x81f0, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_CLOCK_GATING_2", REG_MMIO, 0x8210, NULL, 0, 0, 0 },
+	{ "mmVCE_UENC_DMA_DCLK_CTRL", REG_MMIO, 0x8390, &mmVCE_UENC_DMA_DCLK_CTRL[0], sizeof(mmVCE_UENC_DMA_DCLK_CTRL)/sizeof(mmVCE_UENC_DMA_DCLK_CTRL[0]), 0, 0 },
+	{ "mmVCE_SYS_INT_EN", REG_MMIO, 0x8540, &mmVCE_SYS_INT_EN[0], sizeof(mmVCE_SYS_INT_EN)/sizeof(mmVCE_SYS_INT_EN[0]), 0, 0 },
+	{ "mmVCE_SYS_INT_STATUS", REG_MMIO, 0x8541, &mmVCE_SYS_INT_STATUS[0], sizeof(mmVCE_SYS_INT_STATUS)/sizeof(mmVCE_SYS_INT_STATUS[0]), 0, 0 },
+	{ "mmVCE_SYS_INT_ACK", REG_MMIO, 0x8541, &mmVCE_SYS_INT_ACK[0], sizeof(mmVCE_SYS_INT_ACK)/sizeof(mmVCE_SYS_INT_ACK[0]), 0, 0 },
+	{ "mmVCE_LMI_VCPU_CACHE_40BIT_BAR", REG_MMIO, 0x8597, &mmVCE_LMI_VCPU_CACHE_40BIT_BAR[0], sizeof(mmVCE_LMI_VCPU_CACHE_40BIT_BAR)/sizeof(mmVCE_LMI_VCPU_CACHE_40BIT_BAR[0]), 0, 0 },
+	{ "mmVCE_LMI_CTRL2", REG_MMIO, 0x859d, &mmVCE_LMI_CTRL2[0], sizeof(mmVCE_LMI_CTRL2)/sizeof(mmVCE_LMI_CTRL2[0]), 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL3", REG_MMIO, 0x859e, &mmVCE_LMI_SWAP_CNTL3[0], sizeof(mmVCE_LMI_SWAP_CNTL3)/sizeof(mmVCE_LMI_SWAP_CNTL3[0]), 0, 0 },
+	{ "mmVCE_LMI_CTRL", REG_MMIO, 0x85a6, &mmVCE_LMI_CTRL[0], sizeof(mmVCE_LMI_CTRL)/sizeof(mmVCE_LMI_CTRL[0]), 0, 0 },
+	{ "mmVCE_LMI_STATUS", REG_MMIO, 0x85a7, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_VM_CTRL", REG_MMIO, 0x85a8, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL", REG_MMIO, 0x85ad, &mmVCE_LMI_SWAP_CNTL[0], sizeof(mmVCE_LMI_SWAP_CNTL)/sizeof(mmVCE_LMI_SWAP_CNTL[0]), 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL1", REG_MMIO, 0x85ae, &mmVCE_LMI_SWAP_CNTL1[0], sizeof(mmVCE_LMI_SWAP_CNTL1)/sizeof(mmVCE_LMI_SWAP_CNTL1[0]), 0, 0 },
+	{ "mmVCE_LMI_SWAP_CNTL2", REG_MMIO, 0x85b3, &mmVCE_LMI_SWAP_CNTL2[0], sizeof(mmVCE_LMI_SWAP_CNTL2)/sizeof(mmVCE_LMI_SWAP_CNTL2[0]), 0, 0 },
+	{ "mmVCE_LMI_MISC_CTRL", REG_MMIO, 0x85b5, NULL, 0, 0, 0 },
+	{ "mmVCE_LMI_CACHE_CTRL", REG_MMIO, 0x85bd, &mmVCE_LMI_CACHE_CTRL[0], sizeof(mmVCE_LMI_CACHE_CTRL)/sizeof(mmVCE_LMI_CACHE_CTRL[0]), 0, 0 },
diff --git a/src/lib/mmio.c b/src/lib/mmio.c
new file mode 100644
index 0000000..725f3fc
--- /dev/null
+++ b/src/lib/mmio.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+uint32_t umr_read_reg(struct umr_asic *asic, uint64_t addr)
+{
+	uint32_t value=0;
+	if (!addr)
+		fprintf(stderr, "warning: reading from addr==0 is likely a bug\n");
+
+	if (asic->pci.mem && !(addr & ~0xFFFFFULL)) { // only use pci if enabled and not using high bits 
+		return asic->pci.mem[addr/4];
+	} else {
+		if (lseek(asic->fd.mmio, addr, SEEK_SET) < 0)
+			perror("Cannot seek to MMIO address");
+		if (read(asic->fd.mmio, &value, 4) != 4)
+			perror("Cannot read from MMIO reg");
+		return value;
+	}
+}
+
+int umr_write_reg(struct umr_asic *asic, uint64_t addr, uint32_t value)
+{
+	if (!addr)
+		fprintf(stderr, "warning: reading from addr==0 is likely a bug\n");
+
+	if (asic->pci.mem && !(addr & ~0xFFFFFULL)) {
+		asic->pci.mem[addr/4] = value;
+	} else {
+		if (lseek(asic->fd.mmio, addr, SEEK_SET) < 0) {
+			perror("Cannot seek to MMIO address");
+			return -1;
+		}
+		if (write(asic->fd.mmio, &value, 4) != 4) {
+			perror("Cannot write to MMIO reg");
+			return -1;
+		}
+	}
+	return 0;
+}
+
+uint32_t umr_read_reg_by_name(struct umr_asic *asic, char *name)
+{
+	return umr_read_reg(asic, umr_find_reg(asic, name) * 4);
+}
+
+int umr_write_reg_by_name(struct umr_asic *asic, char *name, uint32_t value)
+{
+	return umr_write_reg(asic, umr_find_reg(asic, name) * 4, value);
+}
+
+uint32_t umr_bitslice_reg(struct umr_asic *asic, struct umr_reg *reg, char *bitname, uint32_t regvalue)
+{
+	int i;
+	for (i = 0; i < reg->no_bits; i++) {
+		if (!strcmp(bitname, reg->bits[i].regname)) {
+			regvalue >>= reg->bits[i].start;
+			regvalue &= (1UL << (reg->bits[i].stop - reg->bits[i].start + 1)) - 1;
+			return regvalue;
+		}
+	}
+	fprintf(stderr, "BUG: Bitfield [%s] not found in reg [%s] on asic [%s]\n", bitname, reg->regname, asic->asicname);
+	return 0;
+}
+
+uint32_t umr_bitslice_reg_by_name(struct umr_asic *asic, char *regname, char *bitname, uint32_t regvalue)
+{
+	struct umr_reg *reg;
+	reg = umr_find_reg_data(asic, regname);
+	return umr_bitslice_reg(asic, reg, bitname, regvalue);
+}
diff --git a/src/lib/query_drm.c b/src/lib/query_drm.c
new file mode 100644
index 0000000..b9d80a8
--- /dev/null
+++ b/src/lib/query_drm.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+#include <asm/ioctl.h>
+#include <sys/ioctl.h>
+#include <drm/drm.h>
+#include <drm/amdgpu_drm.h>
+
+#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
+#define DRM_IOC_WRITE           _IOC_WRITE
+#define DRM_IOCTL_BASE                  'd'
+#define DRM_COMMAND_BASE                0x40
+
+int umr_query_drm(struct umr_asic *asic, int field, uint64_t *ret)
+{
+	struct drm_amdgpu_info inf;
+
+	memset(&inf, 0, sizeof inf);
+	inf.return_pointer = (uintptr_t)ret;
+	inf.return_size = sizeof(*ret);
+	inf.query = field;
+	return ioctl(asic->fd.drm, DRM_IOC(DRM_IOC_WRITE, DRM_IOCTL_BASE, DRM_COMMAND_BASE + DRM_AMDGPU_INFO, sizeof(inf)), &inf);
+
+}
diff --git a/src/lib/read_sgpr.c b/src/lib/read_sgpr.c
new file mode 100644
index 0000000..f12983e
--- /dev/null
+++ b/src/lib/read_sgpr.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+int umr_read_sgprs(struct umr_asic *asic, struct umr_wave_status *ws, uint32_t *dst)
+{
+	uint64_t addr, shift;
+
+	if (asic->family <= FAMILY_CIK)
+		shift = 3;  // on SI..CIK allocations were done in 8-dword blocks
+	else
+		shift = 4;  // on VI allocations are in 16-dword blocks
+
+	addr =
+		(1ULL << 60)                             | // reading SGPRs
+		((uint64_t)ws->gpr_alloc.sgpr_base << shift) | // starting address to read from
+		((uint64_t)ws->hw_id.se_id << 12)        |
+		((uint64_t)ws->hw_id.sh_id << 20)        |
+		((uint64_t)ws->hw_id.cu_id << 28)        |
+		((uint64_t)ws->hw_id.wave_id << 36)      |
+		((uint64_t)ws->hw_id.simd_id << 44)      |
+		(0ULL << 52); // thread_id
+
+	lseek(asic->fd.gpr, addr, SEEK_SET);
+	return read(asic->fd.gpr, dst, 4 * ((ws->gpr_alloc.sgpr_size + 1) << shift));
+}
diff --git a/src/lib/read_vram.c b/src/lib/read_vram.c
new file mode 100644
index 0000000..31fca99
--- /dev/null
+++ b/src/lib/read_vram.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <inttypes.h>
+
+int umr_read_vram(struct umr_asic *asic, uint32_t vmid, uint64_t address, uint32_t size, void *dst)
+{
+	if (vmid == 0xFFFF) {
+		// addressing is physical
+		lseek(asic->fd.vram, address, SEEK_SET);
+		read(asic->fd.vram, dst, size);
+		return 0;
+	}
+	return 0;
+}
diff --git a/src/lib/ring_decode.c b/src/lib/ring_decode.c
new file mode 100644
index 0000000..f2c27d0
--- /dev/null
+++ b/src/lib/ring_decode.c
@@ -0,0 +1,460 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umrapp.h"
+#include <inttypes.h>
+
+static const char *pm4_pkt3_opcode_names[] = {
+	"UNK", // 00
+	"UNK", // 01
+	"UNK", // 02
+	"UNK", // 03
+	"UNK", // 04
+	"UNK", // 05
+	"UNK", // 06
+	"UNK", // 07
+	"UNK", // 08
+	"UNK", // 09
+	"UNK", // 0a
+	"UNK", // 0b
+	"UNK", // 0c
+	"UNK", // 0d
+	"UNK", // 0e
+	"UNK", // 0f
+	"PKT3_NOP", // 10
+	"PKT3_SET_BASE", // 11
+	"PKT3_CLEAR_STATE", // 12
+	"PKT3_INDEX_BUFFER_SIZE", // 13
+	"UNK", // 14
+	"PKT3_DISPATCH_DIRECT", // 15
+	"PKT3_DISPATCH_INDIRECT", // 16
+	"UNK", // 17
+	"UNK", // 18
+	"UNK", // 19
+	"UNK", // 1a
+	"UNK", // 1b
+	"UNK", // 1c
+	"UNK", // 1d
+	"UNK", // 1e
+	"PKT3_OCCLUSION_QUERY", // 1f
+	"PKT3_SET_PREDICATION", // 20
+	"UNK", // 21
+	"PKT3_COND_EXEC", // 22
+	"PKT3_PRED_EXEC", // 23
+	"PKT3_DRAW_INDIRECT", // 24
+	"PKT3_DRAW_INDEX_INDIRECT", // 25
+	"PKT3_INDEX_BASE", // 26
+	"PKT3_DRAW_INDEX_2", // 27
+	"PKT3_CONTEXT_CONTROL", // 28
+	"UNK", // 29
+	"PKT3_INDEX_TYPE", // 2a
+	"UNK", // 2b
+	"PKT3_DRAW_INDIRECT_MULTI", // 2c
+	"PKT3_DRAW_INDEX_AUTO", // 2d
+	"PKT3_DRAW_INDEX_IMMD", // 2e
+	"PKT3_NUM_INSTANCES", // 2f
+	"PKT3_DRAW_INDEX_MULTI_AUTO", // 30
+	"UNK", // 31
+	"PKT3_INDIRECT_BUFFER_SI", // 32
+	"PKT3_INDIRECT_BUFFER_CONST", // 33
+	"PKT3_STRMOUT_BUFFER_UPDATE", // 34
+	"PKT3_DRAW_INDEX_OFFSET_2", // 35
+	"PKT3_DRAW_PREAMBLE", // 36
+	"PKT3_WRITE_DATA", // 37
+	"PKT3_DRAW_INDEX_INDIRECT_MULTI", // 38
+	"PKT3_MEM_SEMAPHORE", // 39
+	"PKT3_MPEG_INDEX", // 3a
+	"UNK", // 3b
+	"PKT3_WAIT_REG_MEM", // 3c
+	"PKT3_MEM_WRITE", // 3d
+	"UNK", // 3e
+	"PKT3_INDIRECT_BUFFER_CIK", // 3f
+	"PKT3_COPY_DATA", // 40
+	"PKT3_CP_DMA", // 41
+	"PKT3_PFP_SYNC_ME", // 42
+	"PKT3_SURFACE_SYNC", // 43
+	"PKT3_ME_INITIALIZE", // 44
+	"PKT3_COND_WRITE", // 45
+	"PKT3_EVENT_WRITE", // 46
+	"PKT3_EVENT_WRITE_EOP", // 47
+	"PKT3_EVENT_WRITE_EOS", // 48
+	"UNK", // 49
+	"UNK", // 4a
+	"UNK", // 4b
+	"UNK", // 4c
+	"UNK", // 4d
+	"UNK", // 4e
+	"UNK", // 4f
+	"PKT3_DMA_DATA", // 50
+	"UNK", // 51
+	"UNK", // 52
+	"UNK", // 53
+	"UNK", // 54
+	"UNK", // 55
+	"UNK", // 56
+	"PKT3_ONE_REG_WRITE", // 57
+	"PKT3_ACQUIRE_MEM", // 58
+	"UNK", // 59
+	"UNK", // 5a
+	"UNK", // 5b
+	"UNK", // 5c
+	"UNK", // 5d
+	"UNK", // 5e
+	"UNK", // 5f
+	"UNK", // 60
+	"UNK", // 61
+	"UNK", // 62
+	"UNK", // 63
+	"UNK", // 64
+	"UNK", // 65
+	"UNK", // 66
+	"UNK", // 67
+	"PKT3_SET_CONFIG_REG", // 68
+	"PKT3_SET_CONTEXT_REG", // 69
+	"UNK", // 6a
+	"UNK", // 6b
+	"UNK", // 6c
+	"UNK", // 6d
+	"UNK", // 6e
+	"UNK", // 6f
+	"UNK", // 70
+	"UNK", // 71
+	"UNK", // 72
+	"UNK", // 73
+	"UNK", // 74
+	"UNK", // 75
+	"PKT3_SET_SH_REG", // 76
+	"PKT3_SET_SH_REG_OFFSET", // 77
+	"UNK", // 78
+	"PKT3_SET_UCONFIG_REG", // 79
+	"UNK", // 7a
+	"UNK", // 7b
+	"UNK", // 7c
+	"UNK", // 7d
+	"UNK", // 7e
+	"UNK", // 7f
+	"PKT3_LOAD_CONST_RAM", // 80
+	"PKT3_WRITE_CONST_RAM", // 81
+	"UNK", // 82
+	"PKT3_DUMP_CONST_RAM", // 83
+	"PKT3_INCREMENT_CE_COUNTER", // 84
+	"PKT3_INCREMENT_DE_COUNTER", // 85
+	"PKT3_WAIT_ON_CE_COUNTER", // 86
+	"UNK", // 87
+	"UNK", // 88
+	"UNK", // 89
+	"UNK", // 8a
+	"UNK", // 8b
+	"UNK", // 8c
+	"UNK", // 8d
+	"UNK", // 8e
+	"UNK", // 8f
+	"UNK", // 90
+	"UNK", // 91
+	"UNK", // 92
+	"UNK", // 93
+	"UNK", // 94
+	"UNK", // 95
+	"UNK", // 96
+	"UNK", // 97
+	"UNK", // 98
+	"UNK", // 99
+	"UNK", // 9a
+	"UNK", // 9b
+	"UNK", // 9c
+	"UNK", // 9d
+	"UNK", // 9e
+	"UNK", // 9f
+	"UNK", // a0
+	"UNK", // a1
+	"UNK", // a2
+	"UNK", // a3
+	"UNK", // a4
+	"UNK", // a5
+	"UNK", // a6
+	"UNK", // a7
+	"UNK", // a8
+	"UNK", // a9
+	"UNK", // aa
+	"UNK", // ab
+	"UNK", // ac
+	"UNK", // ad
+	"UNK", // ae
+	"UNK", // af
+	"UNK", // b0
+	"UNK", // b1
+	"UNK", // b2
+	"UNK", // b3
+	"UNK", // b4
+	"UNK", // b5
+	"UNK", // b6
+	"UNK", // b7
+	"UNK", // b8
+	"UNK", // b9
+	"UNK", // ba
+	"UNK", // bb
+	"UNK", // bc
+	"UNK", // bd
+	"UNK", // be
+	"UNK", // bf
+	"UNK", // c0
+	"UNK", // c1
+	"UNK", // c2
+	"UNK", // c3
+	"UNK", // c4
+	"UNK", // c5
+	"UNK", // c6
+	"UNK", // c7
+	"UNK", // c8
+	"UNK", // c9
+	"UNK", // ca
+	"UNK", // cb
+	"UNK", // cc
+	"UNK", // cd
+	"UNK", // ce
+	"UNK", // cf
+	"UNK", // d0
+	"UNK", // d1
+	"UNK", // d2
+	"UNK", // d3
+	"UNK", // d4
+	"UNK", // d5
+	"UNK", // d6
+	"UNK", // d7
+	"UNK", // d8
+	"UNK", // d9
+	"UNK", // da
+	"UNK", // db
+	"UNK", // dc
+	"UNK", // dd
+	"UNK", // de
+	"UNK", // df
+	"UNK", // e0
+	"UNK", // e1
+	"UNK", // e2
+	"UNK", // e3
+	"UNK", // e4
+	"UNK", // e5
+	"UNK", // e6
+	"UNK", // e7
+	"UNK", // e8
+	"UNK", // e9
+	"UNK", // ea
+	"UNK", // eb
+	"UNK", // ec
+	"UNK", // ed
+	"UNK", // ee
+	"UNK", // ef
+	"UNK", // f0
+	"UNK", // f1
+	"UNK", // f2
+	"UNK", // f3
+	"UNK", // f4
+	"UNK", // f5
+	"UNK", // f6
+	"UNK", // f7
+	"UNK", // f8
+	"UNK", // f9
+	"UNK", // fa
+	"UNK", // fb
+	"UNK", // fc
+	"UNK", // fd
+	"UNK", // fe
+	"UNK", // ff
+};
+
+#define BITS(x, a, b) (unsigned long)((x >> a) & ((1ULL << (b-a))-1))
+
+void add_ib(struct umr_ring_decoder *decoder)
+{
+	struct umr_ring_decoder *pdecoder;
+
+	pdecoder = decoder;
+	while (pdecoder->next_ib)
+		pdecoder = pdecoder->next_ib;
+
+	pdecoder->next_ib = calloc(1, sizeof(*(pdecoder->next_ib)));
+	pdecoder = pdecoder->next_ib;
+	pdecoder->pm = 4;
+	pdecoder->next_ib_info.ib_addr = ((uint64_t)decoder->pm4.next_ib_state.ib_addr_hi << 32) |
+					 decoder->pm4.next_ib_state.ib_addr_lo;
+	pdecoder->next_ib_info.size    = decoder->pm4.next_ib_state.ib_size;
+	pdecoder->next_ib_info.vmid    = decoder->pm4.next_ib_state.ib_vmid;
+	pdecoder->next_ib_info.vm_base_addr = ~0ULL; // not used yet.
+
+	memset(&decoder->pm4.next_ib_state, 0, sizeof(decoder->pm4.next_ib_state));
+}
+
+char *umr_reg_name(struct umr_asic *asic, uint64_t addr)
+{
+	int i, j;
+
+	for (i = 0; i < asic->no_blocks; i++)
+	for (j = 0; j < asic->blocks[i]->no_regs; j++)
+		if (asic->blocks[i]->regs[j].addr == addr)
+			return asic->blocks[i]->regs[j].regname;
+	return "<unknown>";
+}
+
+static void print_decode_pm4_pkt3(struct umr_asic *asic, struct umr_ring_decoder *decoder, uint32_t ib)
+{
+	static const char *op_3c_functions[] = { "true", "<", "<=", "==", "!=", ">=", ">", "reserved" };
+	static const char *op_37_engines[] = { "ME", "PFP", "CE", "DE" };
+	static const char *op_37_dst_sel[] = { "mem-mapped reg", "memory sync", "TC/L2", "GDS", "reserved", "memory async", "reserved", "reserved" };
+	printf("   PKT3 OPCODE 0x%02x, word %u: ", (unsigned)decoder->pm4.cur_opcode, (unsigned)decoder->pm4.cur_word);
+	switch (decoder->pm4.cur_opcode) {
+		case 0x3f: // INDIRECT_BUFFER_CIK
+		case 0x33: // INDIRECT_BUFFER_CONST
+			switch (decoder->pm4.cur_word) {
+				case 0: printf("IB_BASE_LO: 0x%08lx, SWAP:%lu", BITS(ib, 2, 32), BITS(ib, 0, 2));
+					decoder->pm4.next_ib_state.ib_addr_lo = BITS(ib, 2, 32);
+					break;
+				case 1: printf("IB_BASE_HI: 0x%08lx", BITS(ib, 0, 16));
+					decoder->pm4.next_ib_state.ib_addr_hi = BITS(ib, 0, 16);
+					break;
+				case 2: printf("IB_SIZE:%lu, VMID: %lu", BITS(ib, 0, 20), BITS(ib, 24, 32));
+					decoder->pm4.next_ib_state.ib_size = BITS(ib, 0, 20);
+					decoder->pm4.next_ib_state.ib_vmid = BITS(ib, 24, 32);
+					add_ib(decoder);
+					break;
+				default: printf("Invalid word for opcode 0x%02lx", (unsigned long)decoder->pm4.cur_opcode);
+			}
+			break;
+		case 0x37: // WRITE_DATA
+			switch (decoder->pm4.cur_word) {
+				case 0: printf("ENGINE:[%s], WR_CONFIRM:%lu, WR_ONE_ADDR:%lu, DST_SEL:[%s]",
+						op_37_engines[BITS(ib,30,32)],
+						BITS(ib,20,21),
+						BITS(ib,16,17),
+						op_37_dst_sel[BITS(ib, 8, 12)]);
+					decoder->pm4.control = ib;
+					decoder->pm4.next_write_mem.type = BITS(ib, 8, 12);
+					break;
+				case 1: printf("DST_ADDR_LO: 0x%08lx", (unsigned long)ib);
+					decoder->pm4.next_write_mem.addr_lo = ib;
+					break;
+				case 2: printf("DST_ADDR_HI: 0x%08lx", (unsigned long)ib);
+					decoder->pm4.next_write_mem.addr_hi = ib;
+					break;
+				default:
+					if (decoder->pm4.next_write_mem.type == 0) { // mem-mapped reg
+						printf("%s <= %08lx", umr_reg_name(asic, ((uint64_t)decoder->pm4.next_write_mem.addr_hi << 32) | decoder->pm4.next_write_mem.addr_lo), (unsigned long)ib);
+						decoder->pm4.next_write_mem.addr_lo++;
+						if (!decoder->pm4.next_write_mem.addr_lo)
+							decoder->pm4.next_write_mem.addr_hi++;
+					} else {
+						printf("DATA");
+					}
+			}
+			break;
+		case 0x3C: // WAIT_MEM_REG
+			switch(decoder->pm4.cur_word) {
+				case 0: printf("ENGINE:%s, MEMSPACE:%s, FUNC:[%s]",
+						BITS(ib, 8, 9) ? "PFP" : "ME",
+						BITS(ib, 4, 5) ? "REG" : "MEM",
+						op_3c_functions[BITS(ib, 0, 4)]);
+					break;
+				case 1: printf("POLL_ADDRESS_LO: 0x%08lx, SWAP: %lu", BITS(ib, 2, 32), BITS(ib, 0, 2));
+					break;
+				case 2: printf("POLL_ADDRESS_HI: 0x%08lx", (unsigned long)ib);
+					break;
+				case 3: printf("REFERENCE: 0x%08lx", (unsigned long)ib);
+					break;
+				case 4: printf("MASK: 0x%08lx", (unsigned long)ib);
+					break;
+				case 5: printf("POLL INTERVAL: 0x%08lx", BITS(ib, 0, 16));
+					break;
+				default: printf("Invalid word for opcode 0x%02lx", (unsigned long)decoder->pm4.cur_opcode);
+			}
+			break;
+		case 0x47: // EVENT_WRITE_EOP
+			switch(decoder->pm4.cur_word) {
+				case 0: printf("INV_L2:%lu, EVENT_INDEX:%lu, EVENT_TYPE:%lu",
+						BITS(ib, 20, 21),
+						BITS(ib, 8, 12),
+						BITS(ib, 0, 6));
+					break;
+				case 1: printf("ADDRESS_LO: 0x%08lx", BITS(ib, 2, 32));
+					break;
+				case 2: printf("DATA_SEL:%lu, INT_SEL:%lu, ADDRESS_HI: 0x%08lx",
+						BITS(ib, 29, 32),
+						BITS(ib, 24, 26),
+						BITS(ib, 0,  16));
+					break;
+				case 3: printf("DATA_LO: 0x%08lx", (unsigned long)ib);
+					break;
+				case 4: printf("DATA_HI: 0x%08lx", (unsigned long)ib);
+					break;
+				default: printf("Invalid word for opcode 0x%02lx", (unsigned long)decoder->pm4.cur_opcode);
+			}
+			break;
+		default:
+			printf("PKT3 DATA");
+			break;
+	}
+}
+
+static void print_decode_pm4(struct umr_asic *asic, struct umr_ring_decoder *decoder, uint32_t ib)
+{
+	switch (decoder->pm4.cur_opcode) {
+		case 0xFFFFFFFF: // initial decode
+			decoder->pm4.pkt_type = ib >> 30;
+			decoder->pm4.n_words  = (((ib >> 16) + 1) & 0x3FFF);
+			decoder->pm4.cur_word = 0;
+
+			if (decoder->pm4.pkt_type == 0) {
+				printf("PKT0, COUNT:%lu, BASE_INDEX:0x%lx", (unsigned long)decoder->pm4.n_words, (unsigned long)(ib & 0xFFFF));
+				decoder->pm4.cur_opcode = 0x80000000; // TYPE-0 opcode...
+				decoder->pm4.next_write_mem.addr_lo = ib & 0xFFFF;
+			} else if (decoder->pm4.pkt_type == 2) {
+				printf("PKT2");
+			} else if (decoder->pm4.pkt_type == 3) {
+				decoder->pm4.cur_opcode = (ib >> 8) & 0xFF;
+				printf("PKT3, COUNT:%lu, PREDICATE:%lu, SHADER_TYPE:%lu, OPCODE:%02lx[%s]", (unsigned long)decoder->pm4.n_words, (unsigned long)(ib&1), (unsigned long)((ib>>1)&1), (unsigned long)decoder->pm4.cur_opcode, pm4_pkt3_opcode_names[decoder->pm4.cur_opcode&0xFF]);
+			}
+			if (!decoder->pm4.n_words)
+				decoder->pm4.cur_opcode = 0xFFFFFFFF;
+			return;
+		case 0x80000000:
+			printf("PKT0 %s(0x%lx) == %lx", umr_reg_name(asic, decoder->pm4.next_write_mem.addr_lo), (unsigned long)decoder->pm4.next_write_mem.addr_lo, (unsigned long)ib);
+			decoder->pm4.next_write_mem.addr_lo++;
+			break;
+		default:
+			print_decode_pm4_pkt3(asic, decoder, ib);
+			++(decoder->pm4.cur_word);
+			break;
+	}
+	if (!--(decoder->pm4.n_words) ) {
+		decoder->pm4.cur_opcode = 0xFFFFFFFF;
+	}
+}
+
+void umr_print_decode(struct umr_asic *asic, struct umr_ring_decoder *decoder, uint32_t ib)
+{
+	switch (decoder->pm) {
+		case 4:
+			print_decode_pm4(asic, decoder, ib);
+			break;
+	}
+}
diff --git a/src/lib/scan_config.c b/src/lib/scan_config.c
new file mode 100644
index 0000000..85865f9
--- /dev/null
+++ b/src/lib/scan_config.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+#include <inttypes.h>
+
+static void parse_rev0(struct umr_asic *asic, uint32_t *data, int *r)
+{
+	*r = 1;
+	asic->config.gfx.max_shader_engines = data[(*r)++];
+	asic->config.gfx.max_tile_pipes = data[(*r)++];
+	asic->config.gfx.max_cu_per_sh = data[(*r)++];
+	asic->config.gfx.max_sh_per_se = data[(*r)++];
+	asic->config.gfx.max_backends_per_se = data[(*r)++];
+	asic->config.gfx.max_texture_channel_caches = data[(*r)++];
+	asic->config.gfx.max_gprs = data[(*r)++];
+	asic->config.gfx.max_gs_threads = data[(*r)++];
+	asic->config.gfx.max_hw_contexts = data[(*r)++];
+	asic->config.gfx.sc_prim_fifo_size_frontend = data[(*r)++];
+	asic->config.gfx.sc_prim_fifo_size_backend = data[(*r)++];
+	asic->config.gfx.sc_hiz_tile_fifo_size = data[(*r)++];
+	asic->config.gfx.sc_earlyz_tile_fifo_size = data[(*r)++];
+	asic->config.gfx.num_tile_pipes = data[(*r)++];
+	asic->config.gfx.backend_enable_mask = data[(*r)++];
+	asic->config.gfx.mem_max_burst_length_bytes = data[(*r)++];
+	asic->config.gfx.mem_row_size_in_kb = data[(*r)++];
+	asic->config.gfx.shader_engine_tile_size = data[(*r)++];
+	asic->config.gfx.num_gpus = data[(*r)++];
+	asic->config.gfx.multi_gpu_tile_size = data[(*r)++];
+	asic->config.gfx.mc_arb_ramcfg = data[(*r)++];
+	asic->config.gfx.gb_addr_config = data[(*r)++];
+	asic->config.gfx.num_rbs = data[(*r)++];
+}
+
+static void parse_rev1(struct umr_asic *asic, uint32_t *data, int *r)
+{
+	parse_rev0(asic, data, r);
+	asic->config.gfx.rev_id = data[(*r)++];
+	asic->config.gfx.pg_flags = data[(*r)++];
+	asic->config.gfx.cg_flags = data[(*r)++];
+}
+
+static void parse_rev2(struct umr_asic *asic, uint32_t *data, int *r)
+{
+	parse_rev1(asic, data, r);
+	asic->config.gfx.family = data[(*r)++];
+	asic->config.gfx.external_rev_id = data[(*r)++];
+}
+
+void umr_scan_config(struct umr_asic *asic)
+{
+	uint32_t data[512];
+	FILE *f;
+	char fname[256];
+	int r;
+
+	/* process FW block */
+	snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_firmware_info", asic->instance);
+	f = fopen(fname, "r");
+	if (!f)
+		goto gca_config;
+	r = 0;
+	while (r < UMR_MAX_FW && fgets(fname, sizeof(fname)-1, f)) {
+		sscanf(fname, "%s feature version: %" SCNu32 ", firmware version: 0x%" SCNx32 "\n",
+			asic->config.fw[r].name,
+			&asic->config.fw[r].feature_version,
+			&asic->config.fw[r].firmware_version);
+		++r;
+	}
+	fclose(f);
+
+	/* process GFX block */
+gca_config:
+	snprintf(fname, sizeof(fname)-1, "/sys/kernel/debug/dri/%d/amdgpu_gca_config", asic->instance);
+	f = fopen(fname, "rb");
+	if (!f)
+		return;
+	fread(data, 1, sizeof(data), f);
+	fclose(f);
+
+	switch (data[0]) {
+		case 0: parse_rev0(asic, data, &r);
+			break;
+		case 1: parse_rev1(asic, data, &r);
+			break;
+		case 2: parse_rev2(asic, data, &r);
+			break;
+		default:
+			printf("Invalid gca config data header\n");
+	}
+}
diff --git a/src/lib/wave_status.c b/src/lib/wave_status.c
new file mode 100644
index 0000000..04ebec4
--- /dev/null
+++ b/src/lib/wave_status.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include "umr.h"
+
+static int umr_get_wave_sq_info_vi(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, struct umr_wave_status *ws)
+{
+	uint32_t value;
+	uint64_t index, data, bank;
+
+	index = umr_find_reg(asic, "mmSQ_IND_INDEX") * 4;
+	data = umr_find_reg(asic, "mmSQ_IND_DATA") * 4;
+	bank =
+		(1ULL << 62) |
+		(((uint64_t)se) << 24) |
+		(((uint64_t)sh) << 34) |
+		(((uint64_t)cu) << 44);
+
+	if (!index || !data) {
+		fprintf(stderr, "Cannot find SQ indirect registers on this asic!\n");
+		return -1;
+	}
+
+	umr_write_reg(asic, index|bank, 8 << 16);
+	value = umr_read_reg(asic, data|bank);
+	ws->sq_info.busy = value & 1;
+	ws->sq_info.wave_level = (value >> 4) & 0x3F;
+	return 0;
+}
+
+static int umr_get_wave_status_vi(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, unsigned simd, unsigned wave, struct umr_wave_status *ws)
+{
+	uint32_t x, value, buf[32];
+
+	memset(buf, 0, sizeof buf);
+
+	lseek(asic->fd.wave,
+		0 |
+		((uint64_t)se << 7) |
+		((uint64_t)sh << 15) |
+		((uint64_t)cu << 23) |
+		((uint64_t)wave << 31) |
+		((uint64_t)simd << 37), SEEK_SET);
+	read(asic->fd.wave, &buf, 32*4);
+
+	if (buf[0] != 0) {
+		fprintf(stderr, "Was expecting type 0 wave data on a CZ/VI part!\n");
+		return -1;
+	}
+
+	x = 1;
+	ws->wave_status.value = value = buf[x++];
+		ws->wave_status.scc = (value & 1);
+		ws->wave_status.execz = (value >> 9) & 1;
+		ws->wave_status.vccz  = (value >> 10) & 1;
+		ws->wave_status.in_tg = (value >> 11) & 1;
+		ws->wave_status.halt = (value >> 13) & 1;
+		ws->wave_status.valid = (value >> 16) & 1;
+		ws->wave_status.spi_prio = (value >> 1) & 3;
+		ws->wave_status.wave_prio = (value >> 3) & 3;
+		ws->wave_status.trap_en = (value >> 6) & 1;
+		ws->wave_status.ttrace_en = (value >> 7) & 1;
+		ws->wave_status.export_rdy = (value >> 8) & 1;
+		ws->wave_status.in_barrier = (value >> 0xc) & 1;
+		ws->wave_status.trap = (value >> 0xe) & 1;
+		ws->wave_status.ecc_err = (value >> 0x11) & 1;
+		ws->wave_status.skip_export = (value >> 0x12) & 1;
+		ws->wave_status.perf_en = (value >> 0x13) & 1;
+		ws->wave_status.cond_dbg_user = (value >> 0x14) & 1;
+		ws->wave_status.cond_dbg_sys = (value >> 0x15) & 1;
+		ws->wave_status.data_atc = (value >> 0x16) & 1;
+		ws->wave_status.inst_atc = (value >> 0x17) & 1;
+		ws->wave_status.dispatch_cache_ctrl = (value >> 0x18) & 3;
+		ws->wave_status.must_export = (value >> 0x1b) & 1;
+
+	ws->pc_lo = buf[x++];
+	ws->pc_hi = buf[x++];
+	ws->exec_lo = buf[x++];
+	ws->exec_hi = buf[x++];
+
+	ws->hw_id.value = value = buf[x++];
+		ws->hw_id.wave_id = (value & 0xf);
+		ws->hw_id.simd_id = (value >> 4) & 3;
+		ws->hw_id.pipe_id = (value >> 6) & 3;
+		ws->hw_id.cu_id   = (value >> 8) & 0xF;
+		ws->hw_id.sh_id   = (value >> 12) & 1;
+		ws->hw_id.se_id   = (value >> 13) & 3;
+		ws->hw_id.tg_id   = (value >> 16) & 0xf;
+		ws->hw_id.vm_id   = (value >> 20) & 0xF;
+		ws->hw_id.queue_id = (value >> 24) & 7;
+		ws->hw_id.state_id = (value >> 27) & 7;
+		ws->hw_id.me_id    = (value >> 30) & 3;
+
+	ws->wave_inst_dw0 = buf[x++];
+	ws->wave_inst_dw1 = buf[x++];
+
+	ws->gpr_alloc.value = value = buf[x++];
+		ws->gpr_alloc.vgpr_base = (value & 0x3f);
+		ws->gpr_alloc.vgpr_size = (value >> 8) & 0x3f;
+		ws->gpr_alloc.sgpr_base = (value >> 0x10) & 0x3f;
+		ws->gpr_alloc.sgpr_size = (value >> 0x18) & 0xf;
+
+	ws->lds_alloc.value = value = buf[x++];
+		ws->lds_alloc.lds_base = (value >> 0) & 0xFF;
+		ws->lds_alloc.lds_size = (value >> 0xc) & 0x1FF;
+
+	ws->trapsts.value = value = buf[x++];
+		ws->trapsts.excp = (value >> 0) & 0x1ff;
+		ws->trapsts.excp_cycle = (value >> 0x10) & 0x3f;
+		ws->trapsts.dp_rate = (value >> 0x1d) & 0xe;
+		
+	ws->ib_sts.value = value = buf[x++];
+		ws->ib_sts.vm_cnt = (value >> 0) & 0xF;
+		ws->ib_sts.exp_cnt = (value >> 4) & 0x7;
+		ws->ib_sts.lgkm_cnt = (value >> 8) & 0xF;
+		ws->ib_sts.valu_cnt = (value >> 0xc) & 0x7;
+
+	ws->tba_lo = buf[x++];
+	ws->tba_hi = buf[x++];
+	ws->tma_lo = buf[x++];
+	ws->tma_hi = buf[x++];
+	ws->ib_dbg0 = buf[x++];
+	ws->m0 = buf[x++];
+
+	return 0;
+}
+
+int umr_get_wave_status(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, unsigned simd, unsigned wave, struct umr_wave_status *ws)
+{
+	if (asic->family <= FAMILY_VI)
+		return umr_get_wave_status_vi(asic, se, sh, cu, simd, wave, ws);
+	return -1;
+}
+
+int umr_get_wave_sq_info(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, struct umr_wave_status *ws)
+{
+	if (asic->family <= FAMILY_VI)
+		return umr_get_wave_sq_info_vi(asic, se, sh, cu, ws);
+	return -1;
+}
diff --git a/src/umr.h b/src/umr.h
new file mode 100644
index 0000000..38d7419
--- /dev/null
+++ b/src/umr.h
@@ -0,0 +1,423 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <pciaccess.h>
+
+/* sourced from amd_powerplay.h from the kernel */
+enum amd_pp_sensors {
+	AMDGPU_PP_SENSOR_GFX_SCLK = 0,
+	AMDGPU_PP_SENSOR_VDDNB,
+	AMDGPU_PP_SENSOR_VDDGFX,
+	AMDGPU_PP_SENSOR_UVD_VCLK,
+	AMDGPU_PP_SENSOR_UVD_DCLK,
+	AMDGPU_PP_SENSOR_VCE_ECCLK,
+	AMDGPU_PP_SENSOR_GPU_LOAD,
+	AMDGPU_PP_SENSOR_GFX_MCLK,
+	AMDGPU_PP_SENSOR_GPU_TEMP,
+};
+
+enum chipfamily {
+	FAMILY_SI=0,
+	FAMILY_CIK,
+	FAMILY_VI,
+	FAMILY_NEXT,
+};
+
+enum regclass {
+	REG_MMIO,
+	REG_DIDT,
+	REG_SMC,
+	REG_PCIE
+};
+
+struct umr_asic;
+
+struct umr_bitfield {
+	/* if regname is NULL the bitfield is considered inactive */
+	char *regname;
+	/* bit start/stop locations starting from 0 up to 31 */
+	unsigned char start, stop;
+	/* helper to print bitfield, optional */
+	void (*bitfield_print)(struct umr_asic *asic, char *asicname, char *ipname, char *regname, char *bitname, int start, int stop, uint32_t value); 
+};
+
+struct umr_reg {
+	char *regname;
+	enum regclass type;
+	uint32_t addr;
+	struct umr_bitfield *bits;
+	int no_bits;
+	uint32_t value, reserved;
+};
+
+
+struct umr_ip_block {
+	char *ipname;
+	int no_regs;
+	struct umr_reg *regs;
+	int (*grant)(struct umr_asic *asic);
+	int (*release)(struct umr_asic *asic);
+};
+
+struct umr_gfx_config {
+	unsigned max_shader_engines;
+	unsigned max_tile_pipes;
+	unsigned max_cu_per_sh;
+	unsigned max_sh_per_se;
+	unsigned max_backends_per_se;
+	unsigned max_texture_channel_caches;
+	unsigned max_gprs;
+	unsigned max_gs_threads;
+	unsigned max_hw_contexts;
+	unsigned sc_prim_fifo_size_frontend;
+	unsigned sc_prim_fifo_size_backend;
+	unsigned sc_hiz_tile_fifo_size;
+	unsigned sc_earlyz_tile_fifo_size;
+
+	unsigned num_tile_pipes;
+	unsigned backend_enable_mask;
+	unsigned mem_max_burst_length_bytes;
+	unsigned mem_row_size_in_kb;
+	unsigned shader_engine_tile_size;
+	unsigned num_gpus;
+	unsigned multi_gpu_tile_size;
+	unsigned mc_arb_ramcfg;
+	unsigned gb_addr_config;
+	unsigned num_rbs;
+
+	unsigned rev_id;
+	unsigned cg_flags;
+	unsigned pg_flags;
+
+	unsigned family;
+	unsigned external_rev_id;
+};
+
+struct umr_fw_config {
+	char name[16];
+	uint32_t feature_version,
+		 firmware_version;
+};
+
+#define UMR_MAX_FW 32
+
+struct umr_options {
+	int instance,
+	    need_scan,
+	    print,
+	    risky,
+	    bitfields,
+	    bitfields_full,
+	    named,
+	    empty_log,
+	    follow,
+	    use_bank,
+	    many,
+	    use_pci,
+	    use_colour,
+	    read_smc,
+	    quiet;
+	unsigned
+	    instance_bank,
+	    se_bank,
+	    sh_bank;
+	long forcedid;
+	char *scanblock;
+	char dev_name[32];
+};
+
+struct umr_asic {
+	char *asicname;
+	int no_blocks;
+	int instance;
+	enum chipfamily family;
+	unsigned did;
+	struct umr_ip_block **blocks;
+	struct {
+		struct umr_gfx_config gfx;
+		struct umr_fw_config fw[UMR_MAX_FW];
+	} config;
+	struct {
+		int mmio,
+		    didt,
+		    pcie,
+		    smc,
+		    sensors,
+		    drm,
+		    wave,
+		    vram,
+		    gpr;
+	} fd;
+	struct {
+		struct pci_device *pdevice;
+		uint32_t *mem; // virtual address
+		int region;
+	} pci;
+	struct umr_options options;
+};
+
+struct umr_wave_status {
+	struct {
+		uint32_t
+			busy,
+			wave_level;
+	} sq_info;
+
+	struct {
+		uint32_t
+			value,
+			scc,
+			execz,
+			vccz,
+			in_tg,
+			halt,
+			valid,
+			spi_prio,
+			wave_prio,
+			trap_en,
+			ttrace_en,
+			export_rdy,
+			in_barrier,
+			trap,
+			ecc_err,
+			skip_export,
+			perf_en,
+			cond_dbg_user,
+			cond_dbg_sys,
+			data_atc,
+			inst_atc,
+			dispatch_cache_ctrl,
+			must_export;
+	} wave_status;
+
+	uint32_t
+		pc_lo,
+		pc_hi,
+		exec_lo,
+		exec_hi,
+		wave_inst_dw0,
+		wave_inst_dw1,
+		tba_lo,
+		tba_hi,
+		tma_lo,
+		tma_hi,
+		ib_dbg0,
+		m0;
+
+	struct {
+		uint32_t
+			value,
+			wave_id,
+			simd_id,
+			pipe_id,
+			cu_id,
+			sh_id,
+			se_id,
+			tg_id,
+			vm_id,
+			queue_id,
+			state_id,
+			me_id;
+	} hw_id;
+
+
+	struct {
+		uint32_t
+			value,
+			vgpr_base,
+			vgpr_size,
+			sgpr_base,
+			sgpr_size;
+	} gpr_alloc;
+
+	struct {
+		uint32_t
+			value,
+			lds_base,
+			lds_size;
+	} lds_alloc;
+
+	struct {
+		uint32_t
+			value,
+			vm_cnt,
+			exp_cnt,
+			lgkm_cnt,
+			valu_cnt;
+	} ib_sts;
+
+	struct {
+		uint32_t
+			value,
+			excp,
+			excp_cycle,
+			dp_rate;
+	} trapsts;
+};
+
+struct umr_ring_decoder {
+	int
+		pm;
+
+	struct {
+		uint32_t
+			cur_opcode,
+			pkt_type,
+			n_words,
+			cur_word,
+			control;
+
+		struct {
+			uint32_t ib_addr_lo,
+				 ib_addr_hi,
+				 ib_size,
+				 ib_vmid;
+		} next_ib_state;
+
+		struct {
+			uint32_t type,
+				 addr_lo,
+				 addr_hi,
+				 value;
+		} next_write_mem;
+	} pm4;
+
+	struct umr_ring_decoder *next_ib;
+
+	// only used by tail end of ring_read ...
+	struct {
+		uint64_t ib_addr,
+			 vm_base_addr; // not used yet (will be used by IB parser...)
+		uint32_t vmid,
+			 size;
+	} next_ib_info;
+};
+
+/* ip block constructors */
+struct umr_ip_block *umr_create_uvd40(struct umr_options *options);
+struct umr_ip_block *umr_create_uvd42(struct umr_options *options);
+struct umr_ip_block *umr_create_uvd5(struct umr_options *options);
+struct umr_ip_block *umr_create_uvd6(struct umr_options *options);
+struct umr_ip_block *umr_create_vce1(struct umr_options *options);
+struct umr_ip_block *umr_create_vce2(struct umr_options *options);
+struct umr_ip_block *umr_create_vce3(struct umr_options *options);
+struct umr_ip_block *umr_create_gmc60(struct umr_options *options);
+struct umr_ip_block *umr_create_gmc70(struct umr_options *options);
+struct umr_ip_block *umr_create_gmc71(struct umr_options *options);
+struct umr_ip_block *umr_create_gmc81(struct umr_options *options);
+struct umr_ip_block *umr_create_gmc82(struct umr_options *options);
+struct umr_ip_block *umr_create_dce60(struct umr_options *options);
+struct umr_ip_block *umr_create_dce80(struct umr_options *options);
+struct umr_ip_block *umr_create_dce100(struct umr_options *options);
+struct umr_ip_block *umr_create_dce110(struct umr_options *options);
+struct umr_ip_block *umr_create_dce112(struct umr_options *options);
+struct umr_ip_block *umr_create_gfx60(struct umr_options *options);
+struct umr_ip_block *umr_create_gfx70(struct umr_options *options);
+struct umr_ip_block *umr_create_gfx72(struct umr_options *options);
+struct umr_ip_block *umr_create_gfx80(struct umr_options *options);
+struct umr_ip_block *umr_create_gfx81(struct umr_options *options);
+struct umr_ip_block *umr_create_sdma30(struct umr_options *options);
+struct umr_ip_block *umr_create_sdma30x2(struct umr_options *options);
+struct umr_ip_block *umr_create_tonga_ih(struct umr_options *options);
+struct umr_ip_block *umr_create_smu60(struct umr_options *options);
+struct umr_ip_block *umr_create_smu700(struct umr_options *options);
+struct umr_ip_block *umr_create_smu701(struct umr_options *options);
+struct umr_ip_block *umr_create_smu710(struct umr_options *options);
+struct umr_ip_block *umr_create_smu711(struct umr_options *options);
+struct umr_ip_block *umr_create_smu712(struct umr_options *options);
+struct umr_ip_block *umr_create_smu713(struct umr_options *options);
+struct umr_ip_block *umr_create_smu80(struct umr_options *options);
+struct umr_ip_block *umr_create_oss10(struct umr_options *options);
+struct umr_ip_block *umr_create_oss20(struct umr_options *options);
+struct umr_ip_block *umr_create_oss30(struct umr_options *options);
+struct umr_ip_block *umr_create_bif30(struct umr_options *options);
+struct umr_ip_block *umr_create_bif41(struct umr_options *options);
+struct umr_ip_block *umr_create_bif50(struct umr_options *options);
+struct umr_ip_block *umr_create_bif51(struct umr_options *options);
+
+/* asic constructors */
+struct umr_asic *umr_create_asic_helper(char *name, int family, ...);
+struct umr_asic *umr_create_bonaire(struct umr_options *options);
+struct umr_asic *umr_create_carrizo(struct umr_options *options);
+struct umr_asic *umr_create_fiji(struct umr_options *options);
+struct umr_asic *umr_create_hainan(struct umr_options *options);
+struct umr_asic *umr_create_kaveri(struct umr_options *options);
+struct umr_asic *umr_create_oland(struct umr_options *options);
+struct umr_asic *umr_create_pitcairn(struct umr_options *options);
+struct umr_asic *umr_create_polaris10(struct umr_options *options);
+struct umr_asic *umr_create_polaris11(struct umr_options *options);
+struct umr_asic *umr_create_polaris12(struct umr_options *options);
+struct umr_asic *umr_create_stoney(struct umr_options *options);
+struct umr_asic *umr_create_tahiti(struct umr_options *options);
+struct umr_asic *umr_create_tonga(struct umr_options *options);
+struct umr_asic *umr_create_topaz(struct umr_options *options);
+struct umr_asic *umr_create_verde(struct umr_options *options);
+
+
+/* discover */
+struct umr_asic *umr_discover_asic(struct umr_options *options);
+struct umr_asic *umr_discover_asic_by_did(struct umr_options *options, long did);
+struct umr_asic *umr_discover_asic_by_name(struct umr_options *options, char *name);
+void umr_close_asic(struct umr_asic *asic);
+int umr_query_drm(struct umr_asic *asic, int field, uint64_t *ret);
+void umr_enumerate_devices(void);
+
+/* lib helpers */
+int umr_get_wave_status(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, unsigned simd, unsigned wave, struct umr_wave_status *ws);
+int umr_get_wave_sq_info(struct umr_asic *asic, unsigned se, unsigned sh, unsigned cu, struct umr_wave_status *ws);
+int umr_read_sgprs(struct umr_asic *asic, struct umr_wave_status *ws, uint32_t *dst);
+
+/* mmio helpers */
+uint32_t umr_find_reg(struct umr_asic *asic, char *regname);
+struct umr_reg *umr_find_reg_data(struct umr_asic *asic, char *regname);
+uint32_t umr_read_reg(struct umr_asic *asic, uint64_t addr);
+int umr_write_reg(struct umr_asic *asic, uint64_t addr, uint32_t value);
+uint32_t umr_read_reg_by_name(struct umr_asic *asic, char *name);
+int umr_write_reg_by_name(struct umr_asic *asic, char *name, uint32_t value);
+uint32_t umr_bitslice_reg(struct umr_asic *asic, struct umr_reg *reg, char *bitname, uint32_t regvalue);
+uint32_t umr_bitslice_reg_by_name(struct umr_asic *asic, char *regname, char *bitname, uint32_t regvalue);
+
+/* IB/ring decoding/dumping/etc */
+void umr_print_decode(struct umr_asic *asic, struct umr_ring_decoder *decoder, uint32_t ib);
+void umr_dump_ib(struct umr_asic *asic, struct umr_ring_decoder *decoder);
+int umr_read_vram(struct umr_asic *asic, uint32_t vmid, uint64_t address, uint32_t size, void *dst);
+int umr_grab_framebuffer(struct umr_asic *asic, void **fb, uint32_t *size);
+
+#define RED     (options.use_colour ? "\x1b[31;1m" : "")
+#define YELLOW  (options.use_colour ? "\x1b[33;1m" : "")
+#define GREEN   (options.use_colour ? "\x1b[32;1m" : "")
+#define BLUE    (options.use_colour ? "\x1b[34;1m" : "")
+#define CYAN    (options.use_colour ? "\x1b[36;1m" : "")
+#define RST     (options.use_colour ? "\x1b[0m" : "")
+
+void umr_bitfield_default(struct umr_asic *asic, char *asicname, char *ipname, char *regname, char *bitname, int start, int stop, uint32_t value);
+void umr_scan_config(struct umr_asic *asic);
diff --git a/src/umrapp.h b/src/umrapp.h
new file mode 100644
index 0000000..e5911aa
--- /dev/null
+++ b/src/umrapp.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis <tom.stdenis@amd.com>
+ *
+ */
+extern struct umr_options options;
+#include "umr.h"
+
+/* Application functions */
+
+/* scan functions */
+int umr_scan_asic(struct umr_asic *asic, char *asicname, char *ipname, char *regname);
+
+/* print functions */
+void umr_print_asic(struct umr_asic *asic, char *ipname);
+
+/* set register */
+int umr_set_register(struct umr_asic *asic, char *regpath, char *regvalue);
+int umr_set_register_bit(struct umr_asic *asic, char *regpath, char *regvalue);
+
+/* Read and display a ring buffer */
+void umr_read_ring(struct umr_asic *asic, char *ringpath);
+
+void umr_lookup(struct umr_asic *asic, char *address, char *value);
+void umr_scan_log(struct umr_asic *asic);
+void umr_top(struct umr_asic *asic);
+
+void umr_print_config(struct umr_asic *asic);
+void umr_print_waves(struct umr_asic *asic);